Kindle 3 kernel diff .gitignore | 66 Documentation/DocBook/.gitignore | 6 Documentation/filesystems/ext4.txt | 133 Documentation/filesystems/proc.txt | 23 Documentation/filesystems/ubifs.txt | 173 MAINTAINERS | 12 Makefile | 10 arch/.gitignore | 2 arch/Kconfig | 5 arch/arm/Kconfig | 44 arch/arm/Kconfig.debug | 8 arch/arm/Makefile | 6 arch/arm/boot/.gitignore | 5 arch/arm/boot/compressed/.gitignore | 2 arch/arm/boot/compressed/Makefile | 6 arch/arm/boot/compressed/head.S | 16 arch/arm/boot/compressed/vmlinux.lds | 56 arch/arm/common/time-acorn.c | 2 arch/arm/kernel/Makefile | 7 arch/arm/kernel/armksyms.c | 5 arch/arm/kernel/dma.c | 2 arch/arm/kernel/early_console.c | 40 arch/arm/kernel/entry-common.S | 164 arch/arm/kernel/fiq.c | 4 arch/arm/kernel/ftrace.c | 116 arch/arm/kernel/irq.c | 10 arch/arm/kernel/kgdb.c | 206 arch/arm/kernel/process.c | 29 arch/arm/kernel/ptrace.c | 57 arch/arm/kernel/setup.c | 57 arch/arm/kernel/signal.c | 8 arch/arm/kernel/smp.c | 2 arch/arm/kernel/time.c | 38 arch/arm/kernel/traps.c | 121 arch/arm/kernel/vmlinux.lds.S | 15 arch/arm/lib/Makefile | 1 arch/arm/lib/stacktrace.c | 7 arch/arm/mach-at91/gpio.c | 8 arch/arm/mach-footbridge/netwinder-hw.c | 2 arch/arm/mach-footbridge/netwinder-leds.c | 2 arch/arm/mach-integrator/core.c | 2 arch/arm/mach-integrator/pci_v3.c | 2 arch/arm/mach-ixp4xx/common-pci.c | 2 arch/arm/mach-mx21/Kconfig | 17 arch/arm/mach-mx21/Makefile | 12 arch/arm/mach-mx21/Makefile.boot | 3 arch/arm/mach-mx21/board-mx21ads.h | 145 arch/arm/mach-mx21/clock.c | 664 arch/arm/mach-mx21/crm_regs.h | 163 arch/arm/mach-mx21/devices.c | 278 arch/arm/mach-mx21/dma.c | 491 arch/arm/mach-mx21/gpio_mux.c | 302 arch/arm/mach-mx21/gpio_mux.h | 78 arch/arm/mach-mx21/mm.c | 55 arch/arm/mach-mx21/mx21_pins.h | 233 arch/arm/mach-mx21/mx21ads.c | 353 arch/arm/mach-mx21/mx21ads_gpio.c | 384 arch/arm/mach-mx21/serial.c | 200 arch/arm/mach-mx21/serial.h | 139 arch/arm/mach-mx21/system.c | 65 arch/arm/mach-mx21/time.c | 168 arch/arm/mach-mx27/Kconfig | 43 arch/arm/mach-mx27/Makefile | 18 arch/arm/mach-mx27/Makefile.boot | 3 arch/arm/mach-mx27/board-mx27ads.h | 385 arch/arm/mach-mx27/clock.c | 1549 arch/arm/mach-mx27/cpu.c | 33 arch/arm/mach-mx27/crm_regs.h | 283 arch/arm/mach-mx27/devices.c | 697 arch/arm/mach-mx27/dma.c | 553 arch/arm/mach-mx27/dptc.c | 49 arch/arm/mach-mx27/gpio_mux.c | 308 arch/arm/mach-mx27/gpio_mux.h | 78 arch/arm/mach-mx27/mm.c | 62 arch/arm/mach-mx27/mx27_pins.h | 207 arch/arm/mach-mx27/mx27ads.c | 823 arch/arm/mach-mx27/mx27ads_gpio.c | 1226 arch/arm/mach-mx27/mxc_pm.c | 458 arch/arm/mach-mx27/pm.c | 102 arch/arm/mach-mx27/serial.c | 275 arch/arm/mach-mx27/serial.h | 170 arch/arm/mach-mx27/system.c | 60 arch/arm/mach-mx27/time.c | 240 arch/arm/mach-mx27/usb.h | 116 arch/arm/mach-mx27/usb_dr.c | 126 arch/arm/mach-mx27/usb_h1.c | 53 arch/arm/mach-mx27/usb_h2.c | 53 arch/arm/mach-mx3/Kconfig | 90 arch/arm/mach-mx3/Makefile | 16 arch/arm/mach-mx3/board-mx31ads.h | 326 arch/arm/mach-mx3/board-mx3_3stack.h | 150 arch/arm/mach-mx3/clock.c | 1380 arch/arm/mach-mx3/cpu.c | 78 arch/arm/mach-mx3/crm_regs.h | 394 arch/arm/mach-mx3/devices.c | 858 arch/arm/mach-mx3/dma.c | 745 arch/arm/mach-mx3/dptc.c | 103 arch/arm/mach-mx3/dvfs_v2.c | 530 arch/arm/mach-mx3/iomux.c | 259 arch/arm/mach-mx3/iomux.h | 185 arch/arm/mach-mx3/mm.c | 48 arch/arm/mach-mx3/mx31_pins.h | 429 arch/arm/mach-mx3/mx31ads.c | 1004 arch/arm/mach-mx3/mx31ads_gpio.c | 1561 arch/arm/mach-mx3/mx3_3stack.c | 1081 arch/arm/mach-mx3/mx3_3stack_gpio.c | 1298 arch/arm/mach-mx3/mxc_pm.c | 446 arch/arm/mach-mx3/pm.c | 113 arch/arm/mach-mx3/sdma_script_code.h | 581 arch/arm/mach-mx3/sdma_script_code_pass2.h | 434 arch/arm/mach-mx3/serial.c | 267 arch/arm/mach-mx3/serial.h | 158 arch/arm/mach-mx3/system.c | 103 arch/arm/mach-mx3/time.c | 148 arch/arm/mach-mx3/usb.h | 122 arch/arm/mach-mx3/usb_dr.c | 128 arch/arm/mach-mx3/usb_h1.c | 53 arch/arm/mach-mx3/usb_h2.c | 75 arch/arm/mach-mx35/Kconfig | 148 arch/arm/mach-mx35/Makefile | 24 arch/arm/mach-mx35/Makefile.boot | 9 arch/arm/mach-mx35/board-mx35_3stack.h | 210 arch/arm/mach-mx35/board-mx35evb.h | 151 arch/arm/mach-mx35/boardid.c | 207 arch/arm/mach-mx35/boardid.h | 20 arch/arm/mach-mx35/boot_globals.c | 777 arch/arm/mach-mx35/bootdata.c | 809 arch/arm/mach-mx35/clock.c | 2021 arch/arm/mach-mx35/cpu.c | 80 arch/arm/mach-mx35/cpufreq.c | 306 arch/arm/mach-mx35/crm_regs.h | 444 arch/arm/mach-mx35/devices.c | 712 arch/arm/mach-mx35/dma.c | 1046 arch/arm/mach-mx35/dvfs.c | 788 arch/arm/mach-mx35/iomux.c | 474 arch/arm/mach-mx35/iomux.h | 293 arch/arm/mach-mx35/mm.c | 92 arch/arm/mach-mx35/mx35_3stack.c | 773 arch/arm/mach-mx35/mx35_3stack_cpld.c | 159 arch/arm/mach-mx35/mx35_3stack_gpio.c | 1353 arch/arm/mach-mx35/mx35_3stack_irq.c | 371 arch/arm/mach-mx35/mx35_accessory.c | 458 arch/arm/mach-mx35/mx35_luigi.c | 1004 arch/arm/mach-mx35/mx35_luigi_gpio.c | 2180 arch/arm/mach-mx35/mx35_pins.h | 338 arch/arm/mach-mx35/mx35evb.c | 396 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drivers/net/wireless/ar6000/include/AR6002/AR6K_version.h | 52 drivers/net/wireless/ar6000/include/AR6002/addrs.h | 63 drivers/net/wireless/ar6000/include/AR6002/hw/mbox_host_reg.h | 409 drivers/net/wireless/ar6000/include/a_config.h | 41 drivers/net/wireless/ar6000/include/a_debug.h | 53 drivers/net/wireless/ar6000/include/a_drv.h | 42 drivers/net/wireless/ar6000/include/a_drv_api.h | 198 drivers/net/wireless/ar6000/include/a_osapi.h | 47 drivers/net/wireless/ar6000/include/a_types.h | 42 drivers/net/wireless/ar6000/include/ar6000_api.h | 42 drivers/net/wireless/ar6000/include/ar6000_diag.h | 42 drivers/net/wireless/ar6000/include/ar6k.h | 199 drivers/net/wireless/ar6000/include/athdefs.h | 102 drivers/net/wireless/ar6000/include/athdrv.h | 35 drivers/net/wireless/ar6000/include/athendpack.h | 44 drivers/net/wireless/ar6000/include/athstartpack.h | 44 drivers/net/wireless/ar6000/include/bmi.h | 115 drivers/net/wireless/ar6000/include/bmi_internal.h | 50 drivers/net/wireless/ar6000/include/bmi_msg.h | 234 drivers/net/wireless/ar6000/include/common_drv.h | 79 drivers/net/wireless/ar6000/include/dbglog.h | 128 drivers/net/wireless/ar6000/include/dbglog_api.h | 52 drivers/net/wireless/ar6000/include/dl_list.h | 118 drivers/net/wireless/ar6000/include/dset_api.h | 65 drivers/net/wireless/ar6000/include/gpio.h | 49 drivers/net/wireless/ar6000/include/gpio_api.h | 59 drivers/net/wireless/ar6000/include/hif.h | 317 drivers/net/wireless/ar6000/include/hif_internal.h | 88 drivers/net/wireless/ar6000/include/host_version.h | 52 drivers/net/wireless/ar6000/include/htc.h | 204 drivers/net/wireless/ar6000/include/htc_api.h | 474 drivers/net/wireless/ar6000/include/htc_internal.h | 176 drivers/net/wireless/ar6000/include/htc_packet.h | 160 drivers/net/wireless/ar6000/include/htc_services.h | 52 drivers/net/wireless/ar6000/include/ieee80211.h | 344 drivers/net/wireless/ar6000/include/ieee80211_node.h | 85 drivers/net/wireless/ar6000/include/regdump.h | 49 drivers/net/wireless/ar6000/include/roaming.h | 41 drivers/net/wireless/ar6000/include/targaddrs.h | 175 drivers/net/wireless/ar6000/include/testcmd.h | 163 drivers/net/wireless/ar6000/include/wlan_api.h | 110 drivers/net/wireless/ar6000/include/wmi.h | 1871 drivers/net/wireless/ar6000/include/wmi_api.h | 289 drivers/net/wireless/ar6000/include/wmi_host.h | 77 drivers/net/wireless/ar6000/include/wmix.h | 279 drivers/net/wireless/ar6000/ioctl.c | 2756 + drivers/net/wireless/ar6000/netbuf.c | 229 drivers/net/wireless/ar6000/os/linux/include/ar6000_drv.h | 377 drivers/net/wireless/ar6000/os/linux/include/ar6xapi_linux.h | 143 drivers/net/wireless/ar6000/os/linux/include/athdrv_linux.h | 1053 drivers/net/wireless/ar6000/os/linux/include/athtypes_linux.h | 49 drivers/net/wireless/ar6000/os/linux/include/config_linux.h | 54 drivers/net/wireless/ar6000/os/linux/include/debug_linux.h | 90 drivers/net/wireless/ar6000/os/linux/include/engine.h | 97 drivers/net/wireless/ar6000/os/linux/include/ieee80211_ioctl.h | 165 drivers/net/wireless/ar6000/os/linux/include/osapi_linux.h | 331 drivers/net/wireless/ar6000/wireless_ext.c | 2313 + drivers/net/wireless/ar6000/wlan_node.c | 467 drivers/net/wireless/ar6000/wlan_recv_beacon.c | 185 drivers/net/wireless/ar6000/wlan_utils.c | 61 drivers/net/wireless/ar6000/wmi.c | 4780 ++ drivers/net/wireless/ath6k/AR6002_regdump.h | 59 drivers/net/wireless/ath6k/AR6K_version.h | 52 drivers/net/wireless/ath6k/AR6K_version.h.NEW | 38 drivers/net/wireless/ath6k/Kconfig | 14 drivers/net/wireless/ath6k/Makefile | 20 drivers/net/wireless/ath6k/README.txt | 3 drivers/net/wireless/ath6k/a_config.h | 45 drivers/net/wireless/ath6k/a_debug.h | 59 drivers/net/wireless/ath6k/a_drv.h | 46 drivers/net/wireless/ath6k/a_drv_api.h | 207 drivers/net/wireless/ath6k/a_osapi.h | 56 drivers/net/wireless/ath6k/a_pyxis.h | 60 drivers/net/wireless/ath6k/a_types.h | 46 drivers/net/wireless/ath6k/addrs.h | 85 drivers/net/wireless/ath6k/analog_intf_reg.h | 87 drivers/net/wireless/ath6k/analog_reg.h | 1955 drivers/net/wireless/ath6k/apb_map.h | 36 drivers/net/wireless/ath6k/ar6000_api.h | 46 drivers/net/wireless/ath6k/ar6000_diag.h | 42 drivers/net/wireless/ath6k/ar6000_drv.c | 4300 + drivers/net/wireless/ath6k/ar6000_drv.h | 444 drivers/net/wireless/ath6k/ar6000_raw_if.c | 443 drivers/net/wireless/ath6k/ar6k.c | 1033 drivers/net/wireless/ath6k/ar6k.h | 206 drivers/net/wireless/ath6k/ar6k_events.c | 665 drivers/net/wireless/ath6k/ar6kap_common.h | 40 drivers/net/wireless/ath6k/ar6xapi_linux.h | 158 drivers/net/wireless/ath6k/athbtfilter.h | 131 drivers/net/wireless/ath6k/athdefs.h | 84 drivers/net/wireless/ath6k/athdrv.h | 35 drivers/net/wireless/ath6k/athdrv_linux.h | 1091 drivers/net/wireless/ath6k/athendpack.h | 49 drivers/net/wireless/ath6k/athstartpack.h | 48 drivers/net/wireless/ath6k/athtypes_linux.h | 56 drivers/net/wireless/ath6k/bmi.c | 879 drivers/net/wireless/ath6k/bmi.h | 115 drivers/net/wireless/ath6k/bmi_internal.h | 51 drivers/net/wireless/ath6k/bmi_msg.h | 235 drivers/net/wireless/ath6k/cnxmgmt.h | 33 drivers/net/wireless/ath6k/common_drv.c | 663 drivers/net/wireless/ath6k/common_drv.h | 79 drivers/net/wireless/ath6k/config_linux.h | 51 drivers/net/wireless/ath6k/credit_dist.c | 373 drivers/net/wireless/ath6k/dbglog.h | 126 drivers/net/wireless/ath6k/dbglog_api.h | 52 drivers/net/wireless/ath6k/dbglog_id.h | 491 drivers/net/wireless/ath6k/debug_linux.h | 89 drivers/net/wireless/ath6k/discovery.h | 74 drivers/net/wireless/ath6k/dl_list.h | 119 drivers/net/wireless/ath6k/dset_api.h | 65 drivers/net/wireless/ath6k/dset_internal.h | 55 drivers/net/wireless/ath6k/dsetid.h | 126 drivers/net/wireless/ath6k/eeprom.c | 586 drivers/net/wireless/ath6k/engine.c | 278 drivers/net/wireless/ath6k/engine.h | 75 drivers/net/wireless/ath6k/gpio.h | 49 drivers/net/wireless/ath6k/gpio_api.h | 59 drivers/net/wireless/ath6k/gpio_reg.h | 1000 drivers/net/wireless/ath6k/hif.c | 737 drivers/net/wireless/ath6k/hif.h | 323 drivers/net/wireless/ath6k/hif_internal.h | 89 drivers/net/wireless/ath6k/host_version.h | 52 drivers/net/wireless/ath6k/htc.c | 525 drivers/net/wireless/ath6k/htc.h | 204 drivers/net/wireless/ath6k/htc_api.h | 463 drivers/net/wireless/ath6k/htc_debug.h | 69 drivers/net/wireless/ath6k/htc_internal.h | 177 drivers/net/wireless/ath6k/htc_packet.h | 162 drivers/net/wireless/ath6k/htc_recv.c | 785 drivers/net/wireless/ath6k/htc_send.c | 612 drivers/net/wireless/ath6k/htc_services.c | 412 drivers/net/wireless/ath6k/htc_services.h | 52 drivers/net/wireless/ath6k/ieee80211.h | 404 drivers/net/wireless/ath6k/ieee80211_ioctl.h | 173 drivers/net/wireless/ath6k/ieee80211_node.h | 85 drivers/net/wireless/ath6k/ini_dset.h | 90 drivers/net/wireless/ath6k/ioctl.c | 3381 + drivers/net/wireless/ath6k/mbox_host_reg.h | 409 drivers/net/wireless/ath6k/mbox_reg.h | 504 drivers/net/wireless/ath6k/netbuf.c | 229 drivers/net/wireless/ath6k/osapi_linux.h | 333 drivers/net/wireless/ath6k/regDb.h | 30 drivers/net/wireless/ath6k/reg_dbschema.h | 211 drivers/net/wireless/ath6k/reg_dbvalues.h | 476 drivers/net/wireless/ath6k/regdump.h | 49 drivers/net/wireless/ath6k/roaming.h | 41 drivers/net/wireless/ath6k/rtc_reg.h | 1186 drivers/net/wireless/ath6k/si_reg.h | 209 drivers/net/wireless/ath6k/targaddrs.h | 202 drivers/net/wireless/ath6k/testcmd.h | 165 drivers/net/wireless/ath6k/uart_reg.h | 350 drivers/net/wireless/ath6k/vmc_reg.h | 99 drivers/net/wireless/ath6k/wireless_ext.c | 2077 drivers/net/wireless/ath6k/wlan_api.h | 119 drivers/net/wireless/ath6k/wlan_defs.h | 55 drivers/net/wireless/ath6k/wlan_dset.h | 34 drivers/net/wireless/ath6k/wlan_node.c | 470 drivers/net/wireless/ath6k/wlan_recv_beacon.c | 203 drivers/net/wireless/ath6k/wlan_utils.c | 61 drivers/net/wireless/ath6k/wmi.c | 5805 ++ drivers/net/wireless/ath6k/wmi.h | 2263 + drivers/net/wireless/ath6k/wmi_api.h | 367 drivers/net/wireless/ath6k/wmi_filter_linux.h | 246 drivers/net/wireless/ath6k/wmi_host.h | 80 drivers/net/wireless/ath6k/wmix.h | 279 drivers/net/wireless/ath6k22.133/AR6002_regdump.h | 59 drivers/net/wireless/ath6k22.133/AR6K_version.h | 52 drivers/net/wireless/ath6k22.133/Makefile | 37 drivers/net/wireless/ath6k22.133/a_config.h | 46 drivers/net/wireless/ath6k22.133/a_debug.h | 59 drivers/net/wireless/ath6k22.133/a_drv.h | 46 drivers/net/wireless/ath6k22.133/a_drv_api.h | 211 drivers/net/wireless/ath6k22.133/a_osapi.h | 56 drivers/net/wireless/ath6k22.133/a_pyxis.h | 59 drivers/net/wireless/ath6k22.133/a_types.h | 46 drivers/net/wireless/ath6k22.133/addrs.h | 85 drivers/net/wireless/ath6k22.133/analog_intf_reg.h | 87 drivers/net/wireless/ath6k22.133/analog_reg.h | 1955 drivers/net/wireless/ath6k22.133/apb_map.h | 36 drivers/net/wireless/ath6k22.133/ar6000_api.h | 46 drivers/net/wireless/ath6k22.133/ar6000_diag.h | 42 drivers/net/wireless/ath6k22.133/ar6000_drv.c | 4917 ++ drivers/net/wireless/ath6k22.133/ar6000_drv.h | 451 drivers/net/wireless/ath6k22.133/ar6000_raw_if.c | 442 drivers/net/wireless/ath6k22.133/ar6k.c | 1033 drivers/net/wireless/ath6k22.133/ar6k.h | 206 drivers/net/wireless/ath6k22.133/ar6k_events.c | 665 drivers/net/wireless/ath6k22.133/ar6kap_common.h | 40 drivers/net/wireless/ath6k22.133/ar6xapi_linux.h | 159 drivers/net/wireless/ath6k22.133/athbtfilter.h | 131 drivers/net/wireless/ath6k22.133/athdefs.h | 84 drivers/net/wireless/ath6k22.133/athdrv.h | 35 drivers/net/wireless/ath6k22.133/athdrv_linux.h | 1089 drivers/net/wireless/ath6k22.133/athendpack.h | 49 drivers/net/wireless/ath6k22.133/athstartpack.h | 48 drivers/net/wireless/ath6k22.133/athtypes_linux.h | 56 drivers/net/wireless/ath6k22.133/bmi.c | 879 drivers/net/wireless/ath6k22.133/bmi.h | 115 drivers/net/wireless/ath6k22.133/bmi_internal.h | 51 drivers/net/wireless/ath6k22.133/bmi_msg.h | 235 drivers/net/wireless/ath6k22.133/cnxmgmt.h | 33 drivers/net/wireless/ath6k22.133/common_drv.c | 663 drivers/net/wireless/ath6k22.133/common_drv.h | 79 drivers/net/wireless/ath6k22.133/config_linux.h | 51 drivers/net/wireless/ath6k22.133/credit_dist.c | 373 drivers/net/wireless/ath6k22.133/dbglog.h | 126 drivers/net/wireless/ath6k22.133/dbglog_api.h | 52 drivers/net/wireless/ath6k22.133/dbglog_id.h | 505 drivers/net/wireless/ath6k22.133/debug_linux.h | 91 drivers/net/wireless/ath6k22.133/discovery.h | 74 drivers/net/wireless/ath6k22.133/dl_list.h | 119 drivers/net/wireless/ath6k22.133/dset_api.h | 65 drivers/net/wireless/ath6k22.133/dset_internal.h | 55 drivers/net/wireless/ath6k22.133/dsetid.h | 126 drivers/net/wireless/ath6k22.133/eeprom.c | 588 drivers/net/wireless/ath6k22.133/engine.c | 278 drivers/net/wireless/ath6k22.133/engine.h | 75 drivers/net/wireless/ath6k22.133/gpio.h | 49 drivers/net/wireless/ath6k22.133/gpio_api.h | 59 drivers/net/wireless/ath6k22.133/gpio_reg.h | 1000 drivers/net/wireless/ath6k22.133/hif.c | 753 drivers/net/wireless/ath6k22.133/hif.h | 323 drivers/net/wireless/ath6k22.133/hif_internal.h | 90 drivers/net/wireless/ath6k22.133/host_version.h | 52 drivers/net/wireless/ath6k22.133/htc.c | 525 drivers/net/wireless/ath6k22.133/htc.h | 204 drivers/net/wireless/ath6k22.133/htc_api.h | 463 drivers/net/wireless/ath6k22.133/htc_debug.h | 69 drivers/net/wireless/ath6k22.133/htc_internal.h | 179 drivers/net/wireless/ath6k22.133/htc_packet.h | 162 drivers/net/wireless/ath6k22.133/htc_recv.c | 785 drivers/net/wireless/ath6k22.133/htc_send.c | 612 drivers/net/wireless/ath6k22.133/htc_services.c | 412 drivers/net/wireless/ath6k22.133/htc_services.h | 52 drivers/net/wireless/ath6k22.133/ieee80211.h | 405 drivers/net/wireless/ath6k22.133/ieee80211_ioctl.h | 173 drivers/net/wireless/ath6k22.133/ieee80211_node.h | 90 drivers/net/wireless/ath6k22.133/ini_dset.h | 90 drivers/net/wireless/ath6k22.133/ioctl.c | 3484 + drivers/net/wireless/ath6k22.133/mbox_host_reg.h | 409 drivers/net/wireless/ath6k22.133/mbox_reg.h | 504 drivers/net/wireless/ath6k22.133/miscdrv.h | 44 drivers/net/wireless/ath6k22.133/netbuf.c | 229 drivers/net/wireless/ath6k22.133/osapi_linux.h | 333 drivers/net/wireless/ath6k22.133/regDb.h | 30 drivers/net/wireless/ath6k22.133/regTableData.h | 456 drivers/net/wireless/ath6k22.133/reg_dbschema.h | 211 drivers/net/wireless/ath6k22.133/reg_dbvalues.h | 477 drivers/net/wireless/ath6k22.133/regdump.h | 49 drivers/net/wireless/ath6k22.133/roaming.h | 41 drivers/net/wireless/ath6k22.133/rtc_reg.h | 1186 drivers/net/wireless/ath6k22.133/si_reg.h | 209 drivers/net/wireless/ath6k22.133/targaddrs.h | 202 drivers/net/wireless/ath6k22.133/testcmd.h | 165 drivers/net/wireless/ath6k22.133/uart_reg.h | 350 drivers/net/wireless/ath6k22.133/vmc_reg.h | 99 drivers/net/wireless/ath6k22.133/wireless_ext.c | 2340 + drivers/net/wireless/ath6k22.133/wlan_api.h | 119 drivers/net/wireless/ath6k22.133/wlan_defs.h | 55 drivers/net/wireless/ath6k22.133/wlan_dset.h | 34 drivers/net/wireless/ath6k22.133/wlan_node.c | 470 drivers/net/wireless/ath6k22.133/wlan_recv_beacon.c | 207 drivers/net/wireless/ath6k22.133/wlan_utils.c | 61 drivers/net/wireless/ath6k22.133/wmi.c | 5879 ++ drivers/net/wireless/ath6k22.133/wmi.h | 2256 + drivers/net/wireless/ath6k22.133/wmi_api.h | 368 drivers/net/wireless/ath6k22.133/wmi_filter_linux.h | 250 drivers/net/wireless/ath6k22.133/wmi_host.h | 82 drivers/net/wireless/ath6k22.133/wmix.h | 279 drivers/net/wireless/ath6k22/AR6002_regdump.h | 59 drivers/net/wireless/ath6k22/AR6K_version.h | 52 drivers/net/wireless/ath6k22/Makefile | 20 drivers/net/wireless/ath6k22/a_config.h | 45 drivers/net/wireless/ath6k22/a_debug.h | 59 drivers/net/wireless/ath6k22/a_drv.h | 46 drivers/net/wireless/ath6k22/a_drv_api.h | 211 drivers/net/wireless/ath6k22/a_osapi.h | 56 drivers/net/wireless/ath6k22/a_pyxis.h | 60 drivers/net/wireless/ath6k22/a_types.h | 46 drivers/net/wireless/ath6k22/addrs.h | 85 drivers/net/wireless/ath6k22/analog_intf_reg.h | 87 drivers/net/wireless/ath6k22/analog_reg.h | 1955 drivers/net/wireless/ath6k22/apb_map.h | 36 drivers/net/wireless/ath6k22/ar6000_api.h | 46 drivers/net/wireless/ath6k22/ar6000_diag.h | 42 drivers/net/wireless/ath6k22/ar6000_drv.c | 4475 ++ drivers/net/wireless/ath6k22/ar6000_drv.h | 447 drivers/net/wireless/ath6k22/ar6000_raw_if.c | 443 drivers/net/wireless/ath6k22/ar6k.c | 1033 drivers/net/wireless/ath6k22/ar6k.h | 206 drivers/net/wireless/ath6k22/ar6k_events.c | 665 drivers/net/wireless/ath6k22/ar6kap_common.h | 40 drivers/net/wireless/ath6k22/ar6xapi_linux.h | 159 drivers/net/wireless/ath6k22/athbtfilter.h | 131 drivers/net/wireless/ath6k22/athdefs.h | 84 drivers/net/wireless/ath6k22/athdrv.h | 35 drivers/net/wireless/ath6k22/athdrv_linux.h | 1091 drivers/net/wireless/ath6k22/athendpack.h | 49 drivers/net/wireless/ath6k22/athstartpack.h | 48 drivers/net/wireless/ath6k22/athtypes_linux.h | 56 drivers/net/wireless/ath6k22/bmi.c | 879 drivers/net/wireless/ath6k22/bmi.h | 115 drivers/net/wireless/ath6k22/bmi_internal.h | 51 drivers/net/wireless/ath6k22/bmi_msg.h | 235 drivers/net/wireless/ath6k22/cnxmgmt.h | 33 drivers/net/wireless/ath6k22/common_drv.c | 663 drivers/net/wireless/ath6k22/common_drv.h | 79 drivers/net/wireless/ath6k22/config_linux.h | 51 drivers/net/wireless/ath6k22/credit_dist.c | 373 drivers/net/wireless/ath6k22/dbglog.h | 126 drivers/net/wireless/ath6k22/dbglog_api.h | 52 drivers/net/wireless/ath6k22/dbglog_id.h | 505 drivers/net/wireless/ath6k22/debug_linux.h | 92 drivers/net/wireless/ath6k22/discovery.h | 74 drivers/net/wireless/ath6k22/dl_list.h | 119 drivers/net/wireless/ath6k22/dset_api.h | 65 drivers/net/wireless/ath6k22/dset_internal.h | 55 drivers/net/wireless/ath6k22/dsetid.h | 126 drivers/net/wireless/ath6k22/eeprom.c | 588 drivers/net/wireless/ath6k22/engine.c | 278 drivers/net/wireless/ath6k22/engine.h | 75 drivers/net/wireless/ath6k22/gpio.h | 49 drivers/net/wireless/ath6k22/gpio_api.h | 59 drivers/net/wireless/ath6k22/gpio_reg.h | 1000 drivers/net/wireless/ath6k22/hif.c | 739 drivers/net/wireless/ath6k22/hif.h | 323 drivers/net/wireless/ath6k22/hif_internal.h | 89 drivers/net/wireless/ath6k22/host_version.h | 52 drivers/net/wireless/ath6k22/htc.c | 525 drivers/net/wireless/ath6k22/htc.h | 204 drivers/net/wireless/ath6k22/htc_api.h | 463 drivers/net/wireless/ath6k22/htc_debug.h | 69 drivers/net/wireless/ath6k22/htc_internal.h | 177 drivers/net/wireless/ath6k22/htc_packet.h | 162 drivers/net/wireless/ath6k22/htc_recv.c | 785 drivers/net/wireless/ath6k22/htc_send.c | 612 drivers/net/wireless/ath6k22/htc_services.c | 412 drivers/net/wireless/ath6k22/htc_services.h | 52 drivers/net/wireless/ath6k22/ieee80211.h | 404 drivers/net/wireless/ath6k22/ieee80211_ioctl.h | 173 drivers/net/wireless/ath6k22/ieee80211_node.h | 85 drivers/net/wireless/ath6k22/ini_dset.h | 90 drivers/net/wireless/ath6k22/ioctl.c | 3466 + drivers/net/wireless/ath6k22/mbox_host_reg.h | 409 drivers/net/wireless/ath6k22/mbox_reg.h | 504 drivers/net/wireless/ath6k22/miscdrv.h | 44 drivers/net/wireless/ath6k22/netbuf.c | 229 drivers/net/wireless/ath6k22/osapi_linux.h | 333 drivers/net/wireless/ath6k22/regDb.h | 30 drivers/net/wireless/ath6k22/regdump.h | 49 drivers/net/wireless/ath6k22/roaming.h | 41 drivers/net/wireless/ath6k22/rtc_reg.h | 1186 drivers/net/wireless/ath6k22/si_reg.h | 209 drivers/net/wireless/ath6k22/targaddrs.h | 202 drivers/net/wireless/ath6k22/testcmd.h | 165 drivers/net/wireless/ath6k22/uart_reg.h | 350 drivers/net/wireless/ath6k22/vmc_reg.h | 99 drivers/net/wireless/ath6k22/wireless_ext.c | 2240 + drivers/net/wireless/ath6k22/wlan_api.h | 119 drivers/net/wireless/ath6k22/wlan_defs.h | 55 drivers/net/wireless/ath6k22/wlan_dset.h | 34 drivers/net/wireless/ath6k22/wlan_node.c | 470 drivers/net/wireless/ath6k22/wlan_recv_beacon.c | 207 drivers/net/wireless/ath6k22/wlan_utils.c | 61 drivers/net/wireless/ath6k22/wmi.c | 5873 ++ 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include/asm-arm26/irq_regs.h | 1 include/asm-blackfin/.gitignore | 1 include/asm-frv/highmem.h | 2 include/asm-generic/bug.h | 16 include/asm-generic/cmpxchg-local.h | 8 include/asm-generic/percpu.h | 18 include/asm-generic/tlb.h | 9 include/asm-generic/vmlinux.lds.h | 57 include/asm-ia64/irqflags.h | 95 include/asm-ia64/mmu_context.h | 2 include/asm-ia64/processor.h | 6 include/asm-ia64/rtc.h | 7 include/asm-ia64/rwsem.h | 32 include/asm-ia64/sal.h | 2 include/asm-ia64/spinlock.h | 26 include/asm-ia64/spinlock_types.h | 4 include/asm-ia64/system.h | 69 include/asm-ia64/tlb.h | 10 include/asm-m68knommu/bitops.h | 30 include/asm-m68knommu/byteorder.h | 16 include/asm-m68knommu/commproc.h | 19 include/asm-m68knommu/m523xsim.h | 147 include/asm-m68knommu/m528xsim.h | 63 include/asm-m68knommu/m532xsim.h | 86 include/asm-m68knommu/system.h | 18 include/asm-mips/asmmacro.h | 8 include/asm-mips/atomic.h | 25 include/asm-mips/bitops.h | 5 include/asm-mips/hw_irq.h | 1 include/asm-mips/i8259.h | 2 include/asm-mips/io.h | 1 include/asm-mips/linkage.h | 5 include/asm-mips/m48t35.h | 2 include/asm-mips/mach-tx49xx/cpu-feature-overrides.h | 7 include/asm-mips/rwsem.h | 176 include/asm-mips/spinlock.h | 18 include/asm-mips/spinlock_types.h | 4 include/asm-mips/system.h | 3 include/asm-mips/time.h | 2 include/asm-mips/timeofday.h | 5 include/asm-mips/uaccess.h | 12 include/asm-mn10300/.gitignore | 2 include/asm-parisc/cacheflush.h | 4 include/asm-powerpc/ftrace.h | 14 include/asm-powerpc/hw_irq.h | 38 include/asm-powerpc/irq.h | 19 include/asm-powerpc/mpic.h | 2 include/asm-powerpc/pgtable-ppc64.h | 9 include/asm-powerpc/pmac_feature.h | 2 include/asm-powerpc/rtas.h | 2 include/asm-powerpc/rwsem.h | 40 include/asm-powerpc/spinlock.h | 50 include/asm-powerpc/spinlock_types.h | 4 include/asm-powerpc/tlb.h | 6 include/asm-powerpc/tlbflush.h | 31 include/asm-ppc/highmem.h | 4 include/asm-sh/.gitignore | 3 include/asm-sparc64/ftrace.h | 14 include/asm-x86/acpi.h | 4 include/asm-x86/alternative.h | 2 include/asm-x86/apic.h | 2 include/asm-x86/atomic_32.h | 4 include/asm-x86/calling.h | 50 include/asm-x86/ftrace.h | 24 include/asm-x86/highmem.h | 27 include/asm-x86/hw_irq_64.h | 2 include/asm-x86/i8253.h | 2 include/asm-x86/i8259.h | 2 include/asm-x86/irqflags.h | 24 include/asm-x86/mach-default/irq_vectors.h | 2 include/asm-x86/nmi.h | 3 include/asm-x86/page_64.h | 9 include/asm-x86/pgalloc.h | 1 include/asm-x86/rwsem.h | 51 include/asm-x86/smp.h | 4 include/asm-x86/spinlock.h | 32 include/asm-x86/spinlock_types.h | 4 include/asm-x86/timer.h | 8 include/asm-x86/tlbflush.h | 24 include/asm-x86/unistd_32.h | 2 include/asm-x86/unistd_64.h | 2 include/asm-x86/vgtod.h | 2 include/asm-x86/vsyscall.h | 3 include/asm-x86/xor_32.h | 19 include/linux/bit_spinlock.h | 4 include/linux/bottom_half.h | 9 include/linux/buffer_head.h | 6 include/linux/compiler.h | 2 include/linux/completion.h | 1 include/linux/console.h | 12 include/linux/debugfs.h | 4 include/linux/einkfb.h | 467 include/linux/etherdevice.h | 5 include/linux/fs.h | 46 include/linux/fsl_devices.h | 66 include/linux/ftrace.h | 330 include/linux/futex.h | 1 include/linux/genhd.h | 15 include/linux/hardirq.h | 80 include/linux/hrtimer.h | 16 include/linux/init.h | 2 include/linux/init_task.h | 26 include/linux/input.h | 26 include/linux/interrupt.h | 104 include/linux/ioport.h | 6 include/linux/ioprio.h | 2 include/linux/ipu.h | 1187 include/linux/irq.h | 27 include/linux/irqflags.h | 54 include/linux/irqnr.h | 23 include/linux/jbd.h | 21 include/linux/jbd2.h | 73 include/linux/kernel.h | 13 include/linux/kernel_stat.h | 14 include/linux/kobject.h | 4 include/linux/kprobes.h | 7 include/linux/list.h | 66 include/linux/lock_list.h | 74 include/linux/lockdep.h | 45 include/linux/mm.h | 32 include/linux/mm_types.h | 3 include/linux/mmc/card.h | 5 include/linux/mmc/core.h | 3 include/linux/mmc/host.h | 19 include/linux/mmc/mmc.h | 1 include/linux/mmc/pm.h | 31 include/linux/mmc/sdio.h | 2 include/linux/mmc/sdio_func.h | 5 include/linux/mmiotrace.h | 85 include/linux/module.h | 17 include/linux/mpage.h | 10 include/linux/mtd/nand.h | 4 include/linux/mtd/ubi.h | 5 include/linux/mutex.h | 79 include/linux/mxc_asrc.h | 206 include/linux/mxc_mlb.h | 51 include/linux/mxc_pf.h | 125 include/linux/mxc_scc2_driver.h | 973 include/linux/mxc_scc_driver.h | 1031 include/linux/mxc_si4702.h | 39 include/linux/mxc_v4l2.h | 42 include/linux/mxcfb.h | 75 include/linux/netdevice.h | 20 include/linux/netfilter/xt_TCPMSS.h | 10 include/linux/netfilter/xt_tcpmss.h | 9 include/linux/netfilter_ipv4/ipt_CONNMARK.h | 19 include/linux/netfilter_ipv4/ipt_MARK.h | 18 include/linux/netfilter_ipv4/ipt_TOS.h | 12 include/linux/netfilter_ipv4/ipt_TTL.h | 21 include/linux/netfilter_ipv4/ipt_connmark.h | 7 include/linux/netfilter_ipv4/ipt_mark.h | 9 include/linux/netfilter_ipv4/ipt_tos.h | 13 include/linux/netfilter_ipv4/ipt_ttl.h | 21 include/linux/netfilter_ipv6/ip6t_HL.h | 22 include/linux/netfilter_ipv6/ip6t_hl.h | 22 include/linux/netpoll.h | 2 include/linux/oprofile.h | 2 include/linux/page-flags.h | 5 include/linux/pagemap.h | 198 include/linux/pagevec.h | 2 include/linux/parport.h | 2 include/linux/pci.h | 6 include/linux/pci_regs.h | 1 include/linux/percpu.h | 40 include/linux/percpu_counter.h | 14 include/linux/percpu_list.h | 119 include/linux/pickop.h | 32 include/linux/platform_lab126.h | 67 include/linux/plist.h | 19 include/linux/pmic_adc.h | 455 include/linux/pmic_battery.h | 419 include/linux/pmic_external.h | 1137 include/linux/pmic_light.h | 1082 include/linux/pmic_rtc.h | 153 include/linux/pmic_status.h | 82 include/linux/posix-timers.h | 2 include/linux/preempt.h | 53 include/linux/profile.h | 13 include/linux/proportions.h | 6 include/linux/pwm.h | 31 include/linux/quicklist.h | 27 include/linux/radix-tree.h | 121 include/linux/rcuclassic.h | 6 include/linux/rcupdate.h | 66 include/linux/rcupreempt.h | 87 include/linux/regulator/mcu_max8660-bus.h | 102 include/linux/regulator/regulator-drv.h | 107 include/linux/regulator/regulator-platform.h | 102 include/linux/regulator/regulator.h | 332 include/linux/regulator/wm8350/wm8350-audio.h | 638 include/linux/regulator/wm8350/wm8350-bus.h | 118 include/linux/regulator/wm8350/wm8350-comparator.h | 183 include/linux/regulator/wm8350/wm8350-gpio.h | 345 include/linux/regulator/wm8350/wm8350-pmic.h | 805 include/linux/regulator/wm8350/wm8350-rtc.h | 282 include/linux/regulator/wm8350/wm8350-supply.h | 159 include/linux/regulator/wm8350/wm8350-wdt.h | 29 include/linux/regulator/wm8350/wm8350.h | 1863 include/linux/rt_lock.h | 313 include/linux/rtmutex.h | 35 include/linux/rwsem-spinlock.h | 35 include/linux/rwsem.h | 108 include/linux/sched.h | 293 include/linux/sched_prio.h | 23 include/linux/semaphore.h | 78 include/linux/seqlock.h | 316 include/linux/serial_core.h | 3 include/linux/smp.h | 23 include/linux/smp_lock.h | 2 include/linux/soundcard.h | 7 include/linux/spinlock.h | 609 include/linux/spinlock_api_smp.h | 91 include/linux/spinlock_api_up.h | 76 include/linux/spinlock_types.h | 61 include/linux/spinlock_types_up.h | 6 include/linux/spinlock_up.h | 8 include/linux/srcu.h | 22 include/linux/stacktrace.h | 3 include/linux/swap.h | 2 include/linux/sysfs.h | 7 include/linux/tick.h | 5 include/linux/time.h | 2 include/linux/timer.h | 4 include/linux/tracepoint.h | 127 include/linux/tty.h | 2 include/linux/uaccess.h | 33 include/linux/usb.h | 3 include/linux/usb/fsl_xcvr.h | 44 include/linux/usb/gadget.h | 1 include/linux/vmstat.h | 10 include/linux/wireless.h | 2 include/linux/workqueue.h | 35 include/linux/writeback.h | 3 include/llog.h | 527 include/mtd/mtd-abi.h | 3 include/mtd/ubi-user.h | 76 include/net/dn_dev.h | 6 include/net/mwan.h | 34 include/net/netfilter/nf_conntrack.h | 4 include/net/netfilter/nf_conntrack_ecache.h | 13 include/sound/driver.h | 52 include/sound/soc-dapm.h | 51 include/sound/soc.h | 31 include/trace/sched.h | 60 init/Kconfig | 18 init/Makefile | 3 init/do_mounts.c | 3 init/main.c | 88 ipc/mqueue.c | 5 ipc/msg.c | 25 ipc/sem.c | 6 ipc/shm.c | 4 kernel/.gitignore | 6 kernel/Kconfig.hz | 2 kernel/Kconfig.preempt | 107 kernel/Makefile | 26 kernel/cgroup.c | 2 kernel/cpu.c | 9 kernel/exit.c | 20 kernel/fork.c | 199 kernel/futex.c | 29 kernel/hrtimer.c | 122 kernel/irq/Makefile | 1 kernel/irq/autoprobe.c | 1 kernel/irq/chip.c | 50 kernel/irq/handle.c | 80 kernel/irq/internals.h | 6 kernel/irq/manage.c | 348 kernel/irq/migration.c | 14 kernel/irq/pm.c | 81 kernel/irq/proc.c | 129 kernel/irq/spurious.c | 25 kernel/itimer.c | 1 kernel/kprobes.c | 2 kernel/lockdep.c | 162 kernel/lockdep_internals.h | 4 kernel/lockdep_proc.c | 4 kernel/module.c | 81 kernel/notifier.c | 4 kernel/panic.c | 56 kernel/pm_qos_params.c | 25 kernel/posix-cpu-timers.c | 207 kernel/posix-timers.c | 3 kernel/power/poweroff.c | 1 kernel/printk.c | 84 kernel/profile.c | 14 kernel/rcuclassic.c | 10 kernel/rcupdate.c | 20 kernel/rcupreempt-boost.c | 600 kernel/rcupreempt.c | 424 kernel/rcupreempt_trace.c | 14 kernel/rcutorture.c | 138 kernel/relay.c | 14 kernel/rt.c | 528 kernel/rtmutex-debug.c | 111 kernel/rtmutex-debug.h | 12 kernel/rtmutex.c | 2028 kernel/rtmutex_common.h | 83 kernel/rwlock_torture.c | 845 kernel/rwsem.c | 44 kernel/sched.c | 936 kernel/sched_clock.c | 13 kernel/sched_cpupri.c | 174 kernel/sched_cpupri.h | 36 kernel/sched_debug.c | 13 kernel/sched_fair.c | 28 kernel/sched_rt.c | 360 kernel/semaphore.c | 46 kernel/signal.c | 4 kernel/softirq.c | 600 kernel/softlockup.c | 23 kernel/spinlock.c | 264 kernel/srcu.c | 86 kernel/stacktrace.c | 14 kernel/stop_machine.c | 8 kernel/sys.c | 11 kernel/sysctl.c | 106 kernel/time/clockevents.c | 5 kernel/time/clocksource.c | 2 kernel/time/tick-broadcast.c | 2 kernel/time/tick-common.c | 3 kernel/time/tick-internal.h | 2 kernel/time/tick-sched.c | 22 kernel/time/timekeeping.c | 4 kernel/time/timer_stats.c | 6 kernel/timer.c | 226 kernel/trace/Kconfig | 199 kernel/trace/Makefile | 32 kernel/trace/ftrace.c | 1961 kernel/trace/preempt-trace.c | 30 kernel/trace/trace.c | 3989 + kernel/trace/trace.h | 512 kernel/trace/trace_events.c | 655 kernel/trace/trace_functions.c | 81 kernel/trace/trace_hist.c | 657 kernel/trace/trace_hist.h | 39 kernel/trace/trace_irqsoff.c | 515 kernel/trace/trace_mmiotrace.c | 295 kernel/trace/trace_sched_switch.c | 214 kernel/trace/trace_sched_wakeup.c | 383 kernel/trace/trace_selftest.c | 575 kernel/trace/trace_selftest_dynamic.c | 7 kernel/trace/trace_stack.c | 305 kernel/trace/trace_sysprof.c | 363 kernel/tracepoint.c | 476 kernel/user.c | 8 kernel/workqueue.c | 334 lib/.gitignore | 6 lib/Kconfig.debug | 50 lib/Makefile | 14 lib/dec_and_lock.c | 4 lib/kernel_lock.c | 129 lib/kobject_uevent.c | 176 lib/lock_list.c | 161 lib/locking-selftest.c | 35 lib/percpu_counter.c | 7 lib/plist.c | 70 lib/radix-tree.c | 766 lib/ratelimit.c | 2 lib/rwsem-spinlock.c | 29 lib/rwsem.c | 6 lib/spinlock_debug.c | 64 localversion | 1 mm/bounce.c | 4 mm/filemap.c | 236 mm/highmem.c | 521 mm/memory.c | 65 mm/migrate.c | 28 mm/mmap.c | 10 mm/page-writeback.c | 52 mm/page_alloc.c | 133 mm/quicklist.c | 15 mm/readahead.c | 4 mm/shmem.c | 8 mm/slab.c | 517 mm/swap.c | 93 mm/swap_state.c | 26 mm/swapfile.c | 14 mm/truncate.c | 8 mm/vmscan.c | 24 mm/vmstat.c | 38 net/core/dev.c | 41 net/core/flow.c | 22 net/core/netpoll.c | 62 net/core/sock.c | 7 net/decnet/dn_dev.c | 44 net/ethernet/eth.c | 22 net/ipv4/icmp.c | 5 net/ipv4/netfilter/arp_tables.c | 4 net/ipv4/netfilter/ip_tables.c | 2 net/ipv4/netfilter/ipt_ECN.c | 146 net/ipv4/netfilter/ipt_TTL.c | 102 net/ipv4/netfilter/ipt_ecn.c | 135 net/ipv4/netfilter/ipt_ttl.c | 66 net/ipv4/route.c | 6 net/ipv4/tcp.c | 4 net/ipv4/tcp_ipv4.c | 152 net/ipv6/netfilter/ip6_tables.c | 2 net/ipv6/netfilter/ip6t_HL.c | 100 net/ipv6/netfilter/ip6t_hl.c | 71 net/irda/irttp.c | 1 net/netfilter/nf_conntrack_core.c | 18 net/netfilter/nf_conntrack_ecache.c | 16 net/netfilter/xt_CONNMARK.c | 261 net/netfilter/xt_TCPMSS.c | 340 net/netfilter/xt_connmark.c | 204 net/netfilter/xt_tcpmss.c | 113 net/sched/sch_generic.c | 14 scripts/.gitignore | 9 scripts/Makefile | 6 scripts/Makefile.build | 9 scripts/Makefile.lib | 3 scripts/basic/.gitignore | 3 scripts/genksyms/.gitignore | 4 scripts/kconfig/.gitignore | 19 scripts/kconfig/lxdialog/.gitignore | 4 scripts/mkcompile_h | 4 scripts/mod/.gitignore | 4 scripts/recordmcount.pl | 395 scripts/testlpp.c | 159 security/selinux/hooks.c | 9 sound/arm/Kconfig | 54 sound/arm/Makefile | 11 sound/arm/mxc-alsa-common.h | 68 sound/arm/mxc-alsa-mixer.c | 410 sound/arm/mxc-alsa-pmic.c | 3786 + sound/arm/mxc-alsa-pmic.h | 110 sound/arm/mxc-alsa-spdif.c | 2264 + sound/core/pcm_lib.c | 1 sound/oss/.gitignore | 4 sound/soc/Kconfig | 1 sound/soc/Makefile | 4 sound/soc/codecs/Kconfig | 29 sound/soc/codecs/Makefile | 14 sound/soc/codecs/ak4647.c | 811 sound/soc/codecs/ak4647.h | 95 sound/soc/codecs/bluetooth.c | 133 sound/soc/codecs/sgtl5000.c | 1044 sound/soc/codecs/sgtl5000.h | 403 sound/soc/codecs/wm8350.c | 1536 sound/soc/codecs/wm8350.h | 49 sound/soc/codecs/wm8580.c | 1240 sound/soc/codecs/wm8580.h | 45 sound/soc/codecs/wm8903.c | 1880 sound/soc/codecs/wm8903.h | 1453 sound/soc/codecs/wm8960.c | 1804 sound/soc/codecs/wm8960.h | 132 sound/soc/imx/Kconfig | 84 sound/soc/imx/Makefile | 30 sound/soc/imx/imx-3stack-ak4647.c | 527 sound/soc/imx/imx-3stack-bt.c | 335 sound/soc/imx/imx-3stack-bt.h | 23 sound/soc/imx/imx-3stack-sgtl5000.c | 896 sound/soc/imx/imx-3stack-wm8350.c | 658 sound/soc/imx/imx-3stack-wm8580.c | 543 sound/soc/imx/imx-3stack-wm8903.c | 560 sound/soc/imx/imx-esai.c | 950 sound/soc/imx/imx-esai.h | 23 sound/soc/imx/imx-pcm.c | 715 sound/soc/imx/imx-pcm.h | 78 sound/soc/imx/imx-ssi.c | 869 sound/soc/imx/imx-ssi.h | 219 sound/soc/imx/imx31-pcm.h | 72 sound/soc/imx/imx35-pcm.c | 609 sound/soc/imx/imx35-pcm.h | 72 sound/soc/imx/mx35luigi_wm8960.c | 388 sound/soc/imx/mxc_fiq_ssi.S | 129 sound/soc/imx/mxc_pcm.c | 601 sound/soc/imx/mxc_pcm.h | 73 sound/soc/imx/mxc_pcm_fiq.c | 313 sound/soc/imx/mxc_ssi_ksym.c | 19 sound/soc/imx/ssi_fiq.h | 8 sound/soc/soc-core.c | 144 sound/soc/soc-dapm.c | 197 sound/soc/soc-helper.c | 71 usr/.gitignore | 8 2243 files changed, 644909 insertions(+), 8840 deletions(-) diff -urN linux-2.6.26/.gitignore linux-2.6.26-lab126/.gitignore --- linux-2.6.26/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,66 +0,0 @@ -# -# NOTE! Don't add files that are generated in specific -# subdirectories here. Add them in the ".gitignore" file -# in that subdirectory instead. -# -# NOTE! Please use 'git-ls-files -i --exclude-standard' -# command after changing this file, to see if there are -# any tracked files which get ignored after the change. -# -# Normal rules -# -.* -*.o -*.o.* -*.a -*.s -*.ko -*.so -*.so.dbg -*.mod.c -*.i -*.lst -*.symtypes -*.order -*.elf -*.bin -*.gz - -# -# Top-level generic files -# -tags -TAGS -vmlinux -System.map -Module.markers -Module.symvers -!.gitignore -!.mailmap - -# -# Generated include files -# -include/asm -include/asm-*/asm-offsets.h -include/config -include/linux/autoconf.h -include/linux/compile.h -include/linux/version.h -include/linux/utsrelease.h -include/linux/bounds.h - -# stgit generated dirs -patches-* - -# quilt's files -patches -series - -# cscope files -cscope.* -ncscope.* - -*.orig -*~ -\#*# diff -urN linux-2.6.26/Documentation/DocBook/.gitignore linux-2.6.26-lab126/Documentation/DocBook/.gitignore --- linux-2.6.26/Documentation/DocBook/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/Documentation/DocBook/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,6 +0,0 @@ -*.xml -*.ps -*.pdf -*.html -*.9.gz -*.9 diff -urN linux-2.6.26/Documentation/filesystems/ext4.txt linux-2.6.26-lab126/Documentation/filesystems/ext4.txt --- linux-2.6.26/Documentation/filesystems/ext4.txt 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/Documentation/filesystems/ext4.txt 2010-08-10 04:13:43.000000000 -0400 @@ -13,72 +13,99 @@ 1. Quick usage instructions: =========================== - - Grab updated e2fsprogs from - ftp://ftp.kernel.org/pub/linux/kernel/people/tytso/e2fsprogs-interim/ - This is a patchset on top of e2fsprogs-1.39, which can be found at + - Compile and install the latest version of e2fsprogs (as of this + writing version 1.41) from: + + http://sourceforge.net/project/showfiles.php?group_id=2406 + + or + ftp://ftp.kernel.org/pub/linux/kernel/people/tytso/e2fsprogs/ - - It's still mke2fs -j /dev/hda1 + or grab the latest git repository from: + + git://git.kernel.org/pub/scm/fs/ext2/e2fsprogs.git + + - Note that it is highly important to install the mke2fs.conf file + that comes with the e2fsprogs 1.41.x sources in /etc/mke2fs.conf. If + you have edited the /etc/mke2fs.conf file installed on your system, + you will need to merge your changes with the version from e2fsprogs + 1.41.x. + + - Create a new filesystem using the ext4dev filesystem type: + + # mke2fs -t ext4dev /dev/hda1 + + Or configure an existing ext3 filesystem to support extents and set + the test_fs flag to indicate that it's ok for an in-development + filesystem to touch this filesystem: - - mount /dev/hda1 /wherever -t ext4dev + # tune2fs -O extents -E test_fs /dev/hda1 - - To enable extents, + If the filesystem was created with 128 byte inodes, it can be + converted to use 256 byte for greater efficiency via: - mount /dev/hda1 /wherever -t ext4dev -o extents + # tune2fs -I 256 /dev/hda1 - - The filesystem is compatible with the ext3 driver until you add a file - which has extents (ie: `mount -o extents', then create a file). + (Note: we currently do not have tools to convert an ext4dev + filesystem back to ext3; so please do not do try this on production + filesystems.) - NOTE: The "extents" mount flag is temporary. It will soon go away and - extents will be enabled by the "-o extents" flag to mke2fs or tune2fs + - Mounting: + + # mount -t ext4dev /dev/hda1 /wherever - When comparing performance with other filesystems, remember that - ext3/4 by default offers higher data integrity guarantees than most. So - when comparing with a metadata-only journalling filesystem, use `mount -o - data=writeback'. And you might as well use `mount -o nobh' too along - with it. Making the journal larger than the mke2fs default often helps - performance with metadata-intensive workloads. + ext3/4 by default offers higher data integrity guarantees than most. + So when comparing with a metadata-only journalling filesystem, such + as ext3, use `mount -o data=writeback'. And you might as well use + `mount -o nobh' too along with it. Making the journal larger than + the mke2fs default often helps performance with metadata-intensive + workloads. 2. Features =========== 2.1 Currently available -* ability to use filesystems > 16TB +* ability to use filesystems > 16TB (e2fsprogs support not available yet) * extent format reduces metadata overhead (RAM, IO for access, transactions) * extent format more robust in face of on-disk corruption due to magics, * internal redunancy in tree - -2.1 Previously available, soon to be enabled by default by "mkefs.ext4": - -* dir_index and resize inode will be on by default -* large inodes will be used by default for fast EAs, nsec timestamps, etc +* improved file allocation (multi-block alloc) +* fix 32000 subdirectory limit +* nsec timestamps for mtime, atime, ctime, create time +* inode version field on disk (NFSv4, Lustre) +* reduced e2fsck time via uninit_bg feature +* journal checksumming for robustness, performance +* persistent file preallocation (e.g for streaming media, databases) +* ability to pack bitmaps and inode tables into larger virtual groups via the + flex_bg feature +* large file support +* Inode allocation using large virtual block groups via flex_bg +* delayed allocation +* large block (up to pagesize) support +* efficent new ordered mode in JBD2 and ext4(avoid using buffer head to force + the ordering) 2.2 Candidate features for future inclusion -There are several under discussion, whether they all make it in is -partly a function of how much time everyone has to work on them: +* Online defrag (patches available but not well tested) +* reduced mke2fs time via lazy itable initialization in conjuction with + the uninit_bg feature (capability to do this is available in e2fsprogs + but a kernel thread to do lazy zeroing of unused inode table blocks + after filesystem is first mounted is required for safety) + +There are several others under discussion, whether they all make it in is +partly a function of how much time everyone has to work on them. Features like +metadata checksumming have been discussed and planned for a bit but no patches +exist yet so I'm not sure they're in the near-term roadmap. -* improved file allocation (multi-block alloc, delayed alloc; basically done) -* fix 32000 subdirectory limit (patch exists, needs some e2fsck work) -* nsec timestamps for mtime, atime, ctime, create time (patch exists, - needs some e2fsck work) -* inode version field on disk (NFSv4, Lustre; prototype exists) -* reduced mke2fs/e2fsck time via uninitialized groups (prototype exists) -* journal checksumming for robustness, performance (prototype exists) -* persistent file preallocation (e.g for streaming media, databases) +The big performance win will come with mballoc, delalloc and flex_bg +grouping of bitmaps and inode tables. Some test results available here: -Features like metadata checksumming have been discussed and planned for -a bit but no patches exist yet so I'm not sure they're in the near-term -roadmap. - -The big performance win will come with mballoc and delalloc. CFS has -been using mballoc for a few years already with Lustre, and IBM + Bull -did a lot of benchmarking on it. The reason it isn't in the first set of -patches is partly a manageability issue, and partly because it doesn't -directly affect the on-disk format (outside of much better allocation) -so it isn't critical to get into the first round of changes. I believe -Alex is working on a new set of patches right now. + - http://www.bullopensource.org/ext4/20080530/ffsb-write-2.6.26-rc2.html + - http://www.bullopensource.org/ext4/20080530/ffsb-readwrite-2.6.26-rc2.html 3. Options ========== @@ -222,9 +249,11 @@ to use for allocation size and alignment. For RAID5/6 systems this should be the number of data disks * RAID chunk size in file system blocks. - +delalloc (*) Deferring block allocation until write-out time. +nodelalloc Disable delayed allocation. Blocks are allocation + when data is copied from user to page cache. Data Mode ---------- +========= There are 3 different data modes: * writeback mode @@ -236,10 +265,10 @@ * ordered mode In data=ordered mode, ext4 only officially journals metadata, but it logically -groups metadata and data blocks into a single unit called a transaction. When -it's time to write the new metadata out to disk, the associated data blocks -are written first. In general, this mode performs slightly slower than -writeback but significantly faster than journal mode. +groups metadata information related to data changes with the data blocks into a +single unit called a transaction. When it's time to write the new metadata +out to disk, the associated data blocks are written first. In general, +this mode performs slightly slower than writeback but significantly faster than journal mode. * journal mode data=journal mode provides full data and metadata journaling. All new data is @@ -247,7 +276,8 @@ In the event of a crash, the journal can be replayed, bringing both data and metadata into a consistent state. This mode is the slowest except when data needs to be read from and written to disk at the same time where it -outperforms all others modes. +outperforms all others modes. Curently ext4 does not have delayed +allocation support if this data journalling mode is selected. References ========== @@ -256,7 +286,8 @@ programs: http://e2fsprogs.sourceforge.net/ - http://ext2resize.sourceforge.net useful links: http://fedoraproject.org/wiki/ext3-devel http://www.bullopensource.org/ext4/ + http://ext4.wiki.kernel.org/index.php/Main_Page + http://fedoraproject.org/wiki/Features/Ext4 diff -urN linux-2.6.26/Documentation/filesystems/proc.txt linux-2.6.26-lab126/Documentation/filesystems/proc.txt --- linux-2.6.26/Documentation/filesystems/proc.txt 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/Documentation/filesystems/proc.txt 2010-08-10 04:13:43.000000000 -0400 @@ -288,6 +288,7 @@ rtc Real time clock scsi SCSI info (see text) slabinfo Slab pool info + softirqs softirq usage stat Overall statistics swaps Swap space utilization sys See chapter 2 @@ -550,6 +551,22 @@ VmallocUsed: amount of vmalloc area which is used VmallocChunk: largest contigious block of vmalloc area which is free +.............................................................................. +softirqs: + +Provides counts of softirq handlers serviced since boot time. + +> cat /proc/softirqs + CPU0 CPU1 CPU2 CPU3 + HI: 0 0 0 0 + TIMER: 27166 27120 27097 27034 + NET_TX: 0 0 0 17 + NET_RX: 42 0 0 39 + BLOCK: 0 0 107 1121 + TASKLET: 0 0 0 290 + SCHED: 27035 26983 26971 26746 + HRTIMER: 0 0 0 0 + RCU: 1678 1769 2178 2250 1.3 IDE devices in /proc/ide ---------------------------- @@ -837,6 +854,7 @@ processes 2915 procs_running 1 procs_blocked 0 + softirq 183433 0 21755 12 39 1137 231 21459 2263 The very first "cpu" line aggregates the numbers in all of the other "cpuN" lines. These numbers identify the amount of time the CPU has spent performing @@ -872,6 +890,11 @@ The "procs_blocked" line gives the number of processes currently blocked, waiting for I/O to complete. +The "softirq" line gives counts of softirqs serviced since boot time, for each +of the possible system softirqs. The first column is the total of all +softirqs serviced; each subsequent column is the total for that particular +softirq. + 1.9 Ext4 file system parameters ------------------------------ Ext4 file system have one directory per partition under /proc/fs/ext4/ diff -urN linux-2.6.26/Documentation/filesystems/ubifs.txt linux-2.6.26-lab126/Documentation/filesystems/ubifs.txt --- linux-2.6.26/Documentation/filesystems/ubifs.txt 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/Documentation/filesystems/ubifs.txt 2010-08-10 04:13:43.000000000 -0400 @@ -0,0 +1,173 @@ +Introduction +============= + +UBIFS file-system stands for UBI File System. UBI stands for "Unsorted +Block Images". UBIFS is a flash file system, which means it is designed +to work with flash devices. It is important to understand, that UBIFS +is completely different to any traditional file-system in Linux, like +Ext2, XFS, JFS, etc. UBIFS represents a separate class of file-systems +which work with MTD devices, not block devices. The other Linux +file-system of this class is JFFS2. + +To make it more clear, here is a small comparison of MTD devices and +block devices. + +1 MTD devices represent flash devices and they consist of eraseblocks of + rather large size, typically about 128KiB. Block devices consist of + small blocks, typically 512 bytes. +2 MTD devices support 3 main operations - read from some offset within an + eraseblock, write to some offset within an eraseblock, and erase a whole + eraseblock. Block devices support 2 main operations - read a whole + block and write a whole block. +3 The whole eraseblock has to be erased before it becomes possible to + re-write its contents. Blocks may be just re-written. +4 Eraseblocks become worn out after some number of erase cycles - + typically 100K-1G for SLC NAND and NOR flashes, and 1K-10K for MLC + NAND flashes. Blocks do not have the wear-out property. +5 Eraseblocks may become bad (only on NAND flashes) and software should + deal with this. Blocks on hard drives typically do not become bad, + because hardware has mechanisms to substitute bad blocks, at least in + modern LBA disks. + +It should be quite obvious why UBIFS is very different to traditional +file-systems. + +UBIFS works on top of UBI. UBI is a separate software layer which may be +found in drivers/mtd/ubi. UBI is basically a volume management and +wear-leveling layer. It provides so called UBI volumes which is a higher +level abstraction than a MTD device. The programming model of UBI devices +is very similar to MTD devices - they still consist of large eraseblocks, +they have read/write/erase operations, but UBI devices are devoid of +limitations like wear and bad blocks (items 4 and 5 in the above list). + +In a sense, UBIFS is a next generation of JFFS2 file-system, but it is +very different and incompatible to JFFS2. The following are the main +differences. + +* JFFS2 works on top of MTD devices, UBIFS depends on UBI and works on + top of UBI volumes. +* JFFS2 does not have on-media index and has to build it while mounting, + which requires full media scan. UBIFS maintains the FS indexing + information on the flash media and does not require full media scan, + so it mounts many times faster than JFFS2. +* JFFS2 is a write-through file-system, while UBIFS supports write-back, + which makes UBIFS much faster on writes. + +Similarly to JFFS2, UBIFS supports on-the-flight compression which makes +it possible to fit quite a lot of data to the flash. + +Similarly to JFFS2, UBIFS is tolerant of unclean reboots and power-cuts. +It does not need stuff like ckfs.ext2. UBIFS automatically replays its +journal and recovers from crashes, ensuring that the on-flash data +structures are consistent. + +UBIFS scales logarithmically (most of the data structures it uses are +trees), so the mount time and memory consumption do not linearly depend +on the flash size, like in case of JFFS2. This is because UBIFS +maintains the FS index on the flash media. However, UBIFS depends on +UBI, which scales linearly. So overall UBI/UBIFS stack scales linearly. +Nevertheless, UBI/UBIFS scales considerably better than JFFS2. + +The authors of UBIFS believe, that it is possible to develop UBI2 which +would scale logarithmically as well. UBI2 would support the same API as UBI, +but it would be binary incompatible to UBI. So UBIFS would not need to be +changed to use UBI2 + + +Mount options +============= + +(*) == default. + +norm_unmount (*) commit on unmount; the journal is committed + when the file-system is unmounted so that the + next mount does not have to replay the journal + and it becomes very fast; +fast_unmount do not commit on unmount; this option makes + unmount faster, but the next mount slower + because of the need to replay the journal. +bulk_read read more in one go to take advantage of flash + media that read faster sequentially +no_bulk_read (*) do not bulk-read +no_chk_data_crc skip checking of CRCs on data nodes in order to + improve read performance. Use this option only + if the flash media is highly reliable. The effect + of this option is that corruption of the contents + of a file can go unnoticed. +chk_data_crc (*) do not skip checking CRCs on data nodes + + +Quick usage instructions +======================== + +The UBI volume to mount is specified using "ubiX_Y" or "ubiX:NAME" syntax, +where "X" is UBI device number, "Y" is UBI volume number, and "NAME" is +UBI volume name. + +Mount volume 0 on UBI device 0 to /mnt/ubifs: +$ mount -t ubifs ubi0_0 /mnt/ubifs + +Mount "rootfs" volume of UBI device 0 to /mnt/ubifs ("rootfs" is volume +name): +$ mount -t ubifs ubi0:rootfs /mnt/ubifs + +The following is an example of the kernel boot arguments to attach mtd0 +to UBI and mount volume "rootfs": +ubi.mtd=0 root=ubi0:rootfs rootfstype=ubifs + + +Module Parameters for Debugging +=============================== + +When UBIFS has been compiled with debugging enabled, there are 3 module +parameters that are available to control aspects of testing and debugging. +The parameters are unsigned integers where each bit controls an option. +The parameters are: + +debug_msgs Selects which debug messages to display, as follows: + + Message Type Flag value + + General messages 1 + Journal messages 2 + Mount messages 4 + Commit messages 8 + LEB search messages 16 + Budgeting messages 32 + Garbage collection messages 64 + Tree Node Cache (TNC) messages 128 + LEB properties (lprops) messages 256 + Input/output messages 512 + Log messages 1024 + Scan messages 2048 + Recovery messages 4096 + +debug_chks Selects extra checks that UBIFS can do while running: + + Check Flag value + + General checks 1 + Check Tree Node Cache (TNC) 2 + Check indexing tree size 4 + Check orphan area 8 + Check old indexing tree 16 + Check LEB properties (lprops) 32 + Check leaf nodes and inodes 64 + +debug_tsts Selects a mode of testing, as follows: + + Test mode Flag value + + Force in-the-gaps method 2 + Failure mode for recovery testing 4 + +For example, set debug_msgs to 5 to display General messages and Mount +messages. + + +References +========== + +UBIFS documentation and FAQ/HOWTO at the MTD web site: +http://www.linux-mtd.infradead.org/doc/ubifs.html +http://www.linux-mtd.infradead.org/faq/ubifs.html diff -urN linux-2.6.26/MAINTAINERS linux-2.6.26-lab126/MAINTAINERS --- linux-2.6.26/MAINTAINERS 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/MAINTAINERS 2010-08-10 04:17:28.000000000 -0400 @@ -2307,6 +2307,16 @@ W: http://www.linux-mtd.infradead.org/doc/jffs2.html S: Maintained +UBI FILE SYSTEM (UBIFS) +P: Artem Bityutskiy +M: dedekind@infradead.org +P: Adrian Hunter +M: ext-adrian.hunter@nokia.com +L: linux-mtd@lists.infradead.org +T: git git://git.infradead.org/~dedekind/ubifs-2.6.git +W: http://www.linux-mtd.infradead.org/doc/ubifs.html +S: Maintained + JFS FILESYSTEM P: Dave Kleikamp M: shaggy@austin.ibm.com @@ -2751,7 +2761,7 @@ M: dedekind@infradead.org W: http://www.linux-mtd.infradead.org/ L: linux-mtd@lists.infradead.org -T: git git://git.infradead.org/~dedekind/ubi-2.6.git +T: git git://git.infradead.org/ubi-2.6.git S: Maintained MICROTEK X6 SCANNER diff -urN linux-2.6.26/Makefile linux-2.6.26-lab126/Makefile --- linux-2.6.26/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/Makefile 2010-08-10 04:17:28.000000000 -0400 @@ -336,8 +336,10 @@ KBUILD_AFLAGS := -D__ASSEMBLY__ # Read KERNELRELEASE from include/config/kernel.release (if it exists) -KERNELRELEASE = $(shell cat include/config/kernel.release 2> /dev/null) -KERNELVERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) +#KERNELRELEASE = $(shell cat include/config/kernel.release 2> /dev/null) +#KERNELVERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) +KERNELRELEASE = 2.6.26-rt-lab126 +KERNELVERSION = 2.6.26-rt-lab126 export VERSION PATCHLEVEL SUBLEVEL KERNELRELEASE KERNELVERSION export ARCH SRCARCH CONFIG_SHELL HOSTCC HOSTCFLAGS CROSS_COMPILE AS LD CC @@ -528,6 +530,10 @@ KBUILD_AFLAGS += -gdwarf-2 endif +ifdef CONFIG_FTRACE +KBUILD_CFLAGS += -pg +endif + # We trigger additional mismatches with less inlining ifdef CONFIG_DEBUG_SECTION_MISMATCH KBUILD_CFLAGS += $(call cc-option, -fno-inline-functions-called-once) diff -urN linux-2.6.26/arch/.gitignore linux-2.6.26-lab126/arch/.gitignore --- linux-2.6.26/arch/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,2 +0,0 @@ -i386 -x86_64 diff -urN linux-2.6.26/arch/Kconfig linux-2.6.26-lab126/arch/Kconfig --- linux-2.6.26/arch/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/Kconfig 2010-08-10 04:15:13.000000000 -0400 @@ -16,6 +16,11 @@ config HAVE_OPROFILE def_bool n +config PROFILE_NMI + bool + depends on OPROFILE + default y + config KPROBES bool "Kprobes" depends on KALLSYMS && MODULES diff -urN linux-2.6.26/arch/arm/Kconfig linux-2.6.26-lab126/arch/arm/Kconfig --- linux-2.6.26/arch/arm/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/Kconfig 2010-08-10 04:14:16.000000000 -0400 @@ -12,8 +12,11 @@ select RTC_LIB select SYS_SUPPORTS_APM_EMULATION select HAVE_OPROFILE + select HAVE_ARCH_KGDB select HAVE_KPROBES if (!XIP_KERNEL) select HAVE_KRETPROBES if (HAVE_KPROBES) + select HAVE_FTRACE if (!XIP_KERNEL) + select HAVE_DYNAMIC_FTRACE if (HAVE_FTRACE) help The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and @@ -33,6 +36,10 @@ bool default n +config GENERIC_CMOS_UPDATE + bool + default y + config GENERIC_CLOCKEVENTS bool default n @@ -42,6 +49,10 @@ depends on GENERIC_CLOCKEVENTS default y if SMP && !LOCAL_TIMERS +config STACKTRACE_SUPPORT + bool + default y + config MMU bool default y @@ -368,6 +379,8 @@ config ARCH_MXC bool "Freescale MXC/iMX-based" select ARCH_MTD_XIP + select GENERIC_TIME + select GENERIC_CLOCKEVENTS help Support for Freescale MXC/iMX-based family of processors @@ -690,18 +703,7 @@ accounting to be spread across the timer interval, preventing a "thundering herd" at every timer tick. -config PREEMPT - bool "Preemptible Kernel (EXPERIMENTAL)" - depends on EXPERIMENTAL - help - This option reduces the latency of the kernel when reacting to - real-time or interactive events by allowing a low priority process to - be preempted even if it is in kernel mode executing a system call. - This allows applications to run more reliably even when the system is - under load. - - Say Y here if you are building a kernel for a desktop, embedded - or real-time system. Say N if you are unsure. +source kernel/Kconfig.preempt config NO_IDLE_HZ bool "Dynamic tick timer" @@ -795,7 +797,7 @@ ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ ARCH_AT91 || MACH_TRIZEPS4 || ARCH_DAVINCI || \ - ARCH_KS8695 || MACH_RD88F5182 + ARCH_KS8695 || MACH_RD88F5182 || ARCH_MXC help If you say Y here, the LEDs on your machine will be used to provide useful information about your current system status. @@ -954,7 +956,7 @@ endmenu -if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA) +if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA || ARCH_MXC) menu "CPU Frequency scaling" @@ -996,6 +998,12 @@ default y select CPU_FREQ_DEFAULT_GOV_USERSPACE +config CPU_FREQ_IMX + tristate "CPUfreq driver for i.MX CPUs" + depends on ARCH_MXC && CPU_FREQ && REGULATOR + help + This enables the CPUfreq driver for i.MX CPUs. + endmenu endif @@ -1105,6 +1113,8 @@ source "drivers/mtd/Kconfig" endif +source "drivers/regulator/Kconfig" + source "drivers/parport/Kconfig" source "drivers/pnp/Kconfig" @@ -1141,6 +1151,8 @@ source "drivers/i2c/Kconfig" +source "drivers/i2c-slave/Kconfig" + source "drivers/spi/Kconfig" source "drivers/gpio/Kconfig" @@ -1181,6 +1193,10 @@ source "drivers/uio/Kconfig" +if ARCH_MXC +source "drivers/mxc/Kconfig" +endif + endmenu source "fs/Kconfig" diff -urN linux-2.6.26/arch/arm/Kconfig.debug linux-2.6.26-lab126/arch/arm/Kconfig.debug --- linux-2.6.26/arch/arm/Kconfig.debug 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/Kconfig.debug 2010-08-10 04:14:16.000000000 -0400 @@ -59,6 +59,14 @@ in the kernel. This is helpful if you are debugging code that executes before the console is initialized. +config DEBUG_LL_EARLY_CONSOLE + bool "Kernel early console" + depends on DEBUG_LL + help + Say Y here if you want to have an early console using the Kernel + low-level debugging functions. Add earlyconsole to your kernel + parameters to enable this console. + config DEBUG_ICEDCC bool "Kernel low-level debugging via EmbeddedICE DCC channel" depends on DEBUG_LL diff -urN linux-2.6.26/arch/arm/Makefile linux-2.6.26-lab126/arch/arm/Makefile --- linux-2.6.26/arch/arm/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/Makefile 2010-08-10 04:14:16.000000000 -0400 @@ -138,6 +138,12 @@ machine-$(CONFIG_ARCH_KS8695) := ks8695 incdir-$(CONFIG_ARCH_MXC) := mxc machine-$(CONFIG_ARCH_MX3) := mx3 + machine-$(CONFIG_ARCH_MX35) := mx35 + machine-$(CONFIG_ARCH_MX37) := mx37 + machine-$(CONFIG_ARCH_MX51) := mx51 + machine-$(CONFIG_ARCH_MX27) := mx27 + machine-$(CONFIG_ARCH_MX25) := mx25 + machine-$(CONFIG_ARCH_MX21) := mx21 machine-$(CONFIG_ARCH_ORION5X) := orion5x machine-$(CONFIG_ARCH_MSM7X00A) := msm diff -urN linux-2.6.26/arch/arm/boot/.gitignore linux-2.6.26-lab126/arch/arm/boot/.gitignore --- linux-2.6.26/arch/arm/boot/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/boot/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,5 +0,0 @@ -Image -zImage -xipImage -bootpImage -uImage diff -urN linux-2.6.26/arch/arm/boot/compressed/.gitignore linux-2.6.26-lab126/arch/arm/boot/compressed/.gitignore --- linux-2.6.26/arch/arm/boot/compressed/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/boot/compressed/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,2 +0,0 @@ -piggy.gz -font.c diff -urN linux-2.6.26/arch/arm/boot/compressed/Makefile linux-2.6.26-lab126/arch/arm/boot/compressed/Makefile --- linux-2.6.26/arch/arm/boot/compressed/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/boot/compressed/Makefile 2010-08-10 04:14:03.000000000 -0400 @@ -69,6 +69,12 @@ targets := vmlinux vmlinux.lds piggy.gz piggy.o font.o font.c \ head.o misc.o $(OBJS) + +ifeq ($(CONFIG_FTRACE),y) +ORIG_CFLAGS := $(KBUILD_CFLAGS) +KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) +endif + EXTRA_CFLAGS := -fpic -fno-builtin EXTRA_AFLAGS := diff -urN linux-2.6.26/arch/arm/boot/compressed/head.S linux-2.6.26-lab126/arch/arm/boot/compressed/head.S --- linux-2.6.26/arch/arm/boot/compressed/head.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/boot/compressed/head.S 2010-08-10 04:14:03.000000000 -0400 @@ -711,6 +711,9 @@ __armv7_mmu_cache_off: mrc p15, 0, r0, c1, c0 bic r0, r0, #0x000d +#if defined(CONFIG_ARCH_MX51) + bic r0, r0, #0x1000 +#endif mcr p15, 0, r0, c1, c0 @ turn MMU and cache off mov r12, lr bl __armv7_mmu_cache_flush @@ -941,6 +944,19 @@ #endif .ltorg +#ifdef CONFIG_MCOUNT +/* CONFIG_MCOUNT causes boot header to be built with -pg requiring this + * trampoline + */ + .text + .align 0 + .type mcount %function + .global mcount +mcount: + mov pc, lr @ just return +#endif + + reloc_end: .align diff -urN linux-2.6.26/arch/arm/boot/compressed/vmlinux.lds linux-2.6.26-lab126/arch/arm/boot/compressed/vmlinux.lds --- linux-2.6.26/arch/arm/boot/compressed/vmlinux.lds 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/boot/compressed/vmlinux.lds 2010-08-10 04:14:03.000000000 -0400 @@ -0,0 +1,56 @@ +/* + * linux/arch/arm/boot/compressed/vmlinux.lds.in + * + * Copyright (C) 2000 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0; + _text = .; + + .text : { + _start = .; + *(.start) + *(.text) + *(.text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata) + *(.rodata.*) + *(.glue_7) + *(.glue_7t) + *(.piggydata) + . = ALIGN(4); + } + + _etext = .; + + _got_start = .; + .got : { *(.got) } + _got_end = .; + .got.plt : { *(.got.plt) } + .data : { *(.data) } + _edata = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; + + .stack (NOLOAD) : { *(.stack) } + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } +} + diff -urN linux-2.6.26/arch/arm/common/time-acorn.c linux-2.6.26-lab126/arch/arm/common/time-acorn.c --- linux-2.6.26/arch/arm/common/time-acorn.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/common/time-acorn.c 2010-08-10 04:14:12.000000000 -0400 @@ -75,7 +75,7 @@ static struct irqaction ioc_timer_irq = { .name = "timer", - .flags = IRQF_DISABLED, + .flags = IRQF_DISABLED | IRQF_NODELAY, .handler = ioc_timer_interrupt }; diff -urN linux-2.6.26/arch/arm/kernel/Makefile linux-2.6.26-lab126/arch/arm/kernel/Makefile --- linux-2.6.26/arch/arm/kernel/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/kernel/Makefile 2010-08-10 04:14:06.000000000 -0400 @@ -4,6 +4,10 @@ AFLAGS_head.o := -DTEXT_OFFSET=$(TEXT_OFFSET) +ifdef CONFIG_DYNAMIC_FTRACE +CFLAGS_REMOVE_ftrace.o = -pg +endif + # Object file lists. obj-y := compat.o entry-armv.o entry-common.o irq.o \ @@ -18,11 +22,13 @@ obj-$(CONFIG_ISA_DMA) += dma-isa.o obj-$(CONFIG_PCI) += bios32.o isa.o obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o obj-$(CONFIG_KPROBES) += kprobes.o kprobes-decode.o obj-$(CONFIG_ATAGS_PROC) += atags.o obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o obj-$(CONFIG_ARM_THUMBEE) += thumbee.o +obj-$(CONFIG_KGDB) += kgdb.o obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 @@ -38,5 +44,6 @@ head-y := head$(MMUEXT).o obj-$(CONFIG_DEBUG_LL) += debug.o +obj-$(CONFIG_DEBUG_LL_EARLY_CONSOLE) += early_console.o extra-y := $(head-y) init_task.o vmlinux.lds diff -urN linux-2.6.26/arch/arm/kernel/armksyms.c linux-2.6.26-lab126/arch/arm/kernel/armksyms.c --- linux-2.6.26/arch/arm/kernel/armksyms.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/kernel/armksyms.c 2010-08-10 04:14:06.000000000 -0400 @@ -18,6 +18,7 @@ #include #include #include +#include /* * libgcc functions - functions that are used internally by the @@ -181,3 +182,7 @@ #endif EXPORT_SYMBOL(copy_page); + +#ifdef CONFIG_FTRACE +EXPORT_SYMBOL(mcount); +#endif diff -urN linux-2.6.26/arch/arm/kernel/dma.c linux-2.6.26-lab126/arch/arm/kernel/dma.c --- linux-2.6.26/arch/arm/kernel/dma.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/kernel/dma.c 2010-08-10 04:14:06.000000000 -0400 @@ -20,7 +20,7 @@ #include -DEFINE_SPINLOCK(dma_spin_lock); +DEFINE_RAW_SPINLOCK(dma_spin_lock); EXPORT_SYMBOL(dma_spin_lock); static dma_t dma_chan[MAX_DMA_CHANNELS]; diff -urN linux-2.6.26/arch/arm/kernel/early_console.c linux-2.6.26-lab126/arch/arm/kernel/early_console.c --- linux-2.6.26/arch/arm/kernel/early_console.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/kernel/early_console.c 2010-08-10 04:14:06.000000000 -0400 @@ -0,0 +1,40 @@ +/* + * linux/arch/arm/kernel/early_printk.c + * + * Copyright 2008-2009 Amazon.com Technologies Inc., All Rights Reserved. + * Manish Lachwani (lachwani@lab126.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +extern void printch(int); + +static void early_console_write(struct console *con, const char *s, unsigned n) +{ + while (*s && n-- > 0) { + if (*s == '\n') + printch('\r'); + printch(*s); + s++; + } +} + +static struct console early_serial_console = { + .name = "earlycons", + .write = early_console_write, + .flags = CON_PRINTBUFFER | CON_BOOT, + .index = -1, +}; + +static int __init setup_early_console(char *buf) +{ + register_console(&early_serial_console); + return 0; +} + +early_param("earlyconsole", setup_early_console); diff -urN linux-2.6.26/arch/arm/kernel/entry-common.S linux-2.6.26-lab126/arch/arm/kernel/entry-common.S --- linux-2.6.26/arch/arm/kernel/entry-common.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/kernel/entry-common.S 2010-08-10 04:14:06.000000000 -0400 @@ -3,12 +3,15 @@ * * Copyright (C) 2000 Russell King * + * FUNCTION_TRACE/mcount support (C) 2005 Timesys john.cooper@timesys.com + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include +#include #include #include "entry-header.S" @@ -54,7 +57,8 @@ b ret_slow_syscall @ Check work again work_resched: - bl schedule + bl __schedule + /* * "slow" syscall return path. "why" tells us if this was a real syscall. */ @@ -99,6 +103,56 @@ #undef CALL #define CALL(x) .long x +#ifdef CONFIG_FTRACE +#ifdef CONFIG_DYNAMIC_FTRACE +ENTRY(mcount) + stmdb sp!, {r0-r3, lr} + mov r0, lr + sub r0, r0, #MCOUNT_INSN_SIZE + + .globl mcount_call +mcount_call: + bl ftrace_stub + ldmia sp!, {r0-r3, pc} + +ENTRY(ftrace_caller) + stmdb sp!, {r0-r3, lr} + ldr r1, [fp, #-4] + mov r0, lr + sub r0, r0, #MCOUNT_INSN_SIZE + + .globl ftrace_call +ftrace_call: + bl ftrace_stub + ldmia sp!, {r0-r3, pc} + +#else + +ENTRY(mcount) + stmdb sp!, {r0-r3, lr} + ldr r0, =ftrace_trace_function + ldr r2, [r0] + adr r0, ftrace_stub + cmp r0, r2 + bne trace + ldmia sp!, {r0-r3, pc} + +trace: + ldr r1, [fp, #-4] + mov r0, lr + sub r0, r0, #MCOUNT_INSN_SIZE + mov lr, pc + mov pc, r2 + ldmia sp!, {r0-r3, pc} + +#endif /* CONFIG_DYNAMIC_FTRACE */ + + .globl ftrace_stub +ftrace_stub: + mov pc, lr + +#endif /* CONFIG_FTRACE */ + /*============================================================================= * SWI handler *----------------------------------------------------------------------------- @@ -399,6 +453,114 @@ #include "calls.S" #undef ABI #undef OBSOLETE +#endif + +#ifdef CONFIG_FRAME_POINTER + +#ifdef CONFIG_MCOUNT +/* + * At the point where we are in mcount() we maintain the + * frame of the prologue code and keep the call to mcount() + * out of the stack frame list: + + saved pc <---\ caller of instrumented routine + saved lr | + ip/prev_sp | + fp -----^ | + : | + | + -> saved pc | instrumented routine + | saved lr | + | ip/prev_sp | + | fp ---------/ + | : + | + | mcount + | saved pc + | saved lr + | ip/prev sp + -- fp + r3 + r2 + r1 + sp-> r0 + : + */ + + .text + .align 0 + .type mcount %function + .global mcount + +/* gcc -pg generated FUNCTION_PROLOGUE references mcount() + * and has already created the stack frame invocation for + * the routine we have been called to instrument. We create + * a complete frame nevertheless, as we want to use the same + * call to mcount() from c code. + */ +mcount: + + ldr ip, =mcount_enabled @ leave early, if disabled + ldr ip, [ip] + cmp ip, #0 + moveq pc, lr + + mov ip, sp + stmdb sp!, {r0 - r3, fp, ip, lr, pc} @ create stack frame + + mov r2, =mcount_trace_function + + ldr r1, [fp, #-4] @ get lr (the return address + @ of the caller of the + @ instrumented function) + mov r0, lr @ get lr - (the return address + @ of the instrumented function) + + sub fp, ip, #4 @ point fp at this frame + + bl r2 +1: + ldmdb fp, {r0 - r3, fp, sp, pc} @ pop entry frame and return + +#endif + +/* ARM replacement for unsupported gcc __builtin_return_address(n) + * where 0 < n. n == 0 is supported here as well. + * + * Walk up the stack frame until the desired frame is found or a NULL + * fp is encountered, return NULL in the latter case. + * + * Note: it is possible under code optimization for the stack invocation + * of an ancestor function (level N) to be removed before calling a + * descendant function (level N+1). No easy means is available to deduce + * this scenario with the result being [for example] caller_addr(0) when + * called from level N+1 returning level N-1 rather than the expected + * level N. This optimization issue appears isolated to the case of + * a call to a level N+1 routine made at the tail end of a level N + * routine -- the level N frame is deleted and a simple branch is made + * to the level N+1 routine. + */ + + .text + .align 0 + .type arm_return_addr %function + .global arm_return_addr + +arm_return_addr: + mov ip, r0 + mov r0, fp +3: + cmp r0, #0 + beq 1f @ frame list hit end, bail + cmp ip, #0 + beq 2f @ reached desired frame + ldr r0, [r0, #-12] @ else continue, get next fp + sub ip, ip, #1 + b 3b +2: + ldr r0, [r0, #-4] @ get target return address +1: + mov pc, lr #endif diff -urN linux-2.6.26/arch/arm/kernel/fiq.c linux-2.6.26-lab126/arch/arm/kernel/fiq.c --- linux-2.6.26/arch/arm/kernel/fiq.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/kernel/fiq.c 2010-08-10 04:14:06.000000000 -0400 @@ -89,7 +89,7 @@ * disable irqs for the duration. Note - these functions are almost * entirely coded in assembly. */ -void __attribute__((naked)) set_fiq_regs(struct pt_regs *regs) +void notrace __attribute__((naked)) set_fiq_regs(struct pt_regs *regs) { register unsigned long tmp; asm volatile ( @@ -107,7 +107,7 @@ : "r" (®s->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | FIQ_MODE)); } -void __attribute__((naked)) get_fiq_regs(struct pt_regs *regs) +void notrace __attribute__((naked)) get_fiq_regs(struct pt_regs *regs) { register unsigned long tmp; asm volatile ( diff -urN linux-2.6.26/arch/arm/kernel/ftrace.c linux-2.6.26-lab126/arch/arm/kernel/ftrace.c --- linux-2.6.26/arch/arm/kernel/ftrace.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/kernel/ftrace.c 2010-08-10 04:14:06.000000000 -0400 @@ -0,0 +1,116 @@ +/* + * Dynamic function tracing support. + * + * Copyright (C) 2008 Abhishek Sagar + * + * For licencing details, see COPYING. + * + * Defines low-level handling of mcount calls when the kernel + * is compiled with the -pg flag. When using dynamic ftrace, the + * mcount call-sites get patched lazily with NOP till they are + * enabled. All code mutation routines here take effect atomically. + */ + +#include + +#include +#include + +#define PC_OFFSET 8 +#define BL_OPCODE 0xeb000000 +#define BL_OFFSET_MASK 0x00ffffff + +static unsigned long bl_insn; +static const unsigned long NOP = 0xe1a00000; /* mov r0, r0 */ + +unsigned char *ftrace_nop_replace(void) +{ + return (char *)&NOP; +} + +/* construct a branch (BL) instruction to addr */ +unsigned char *ftrace_call_replace(unsigned long pc, unsigned long addr) +{ + long offset; + + offset = (long)addr - (long)(pc + PC_OFFSET); + if (unlikely(offset < -33554432 || offset > 33554428)) { + /* Can't generate branches that far (from ARM ARM). Ftrace + * doesn't generate branches outside of kernel text. + */ + WARN_ON_ONCE(1); + return NULL; + } + offset = (offset >> 2) & BL_OFFSET_MASK; + bl_insn = BL_OPCODE | offset; + return (unsigned char *)&bl_insn; +} + +int ftrace_modify_code(unsigned long pc, unsigned char *old_code, + unsigned char *new_code) +{ + unsigned long err = 0, replaced = 0, old, new; + + old = *(unsigned long *)old_code; + new = *(unsigned long *)new_code; + + __asm__ __volatile__ ( + "1: ldr %1, [%2] \n" + " cmp %1, %4 \n" + "2: streq %3, [%2] \n" + " cmpne %1, %3 \n" + " movne %0, #2 \n" + "3:\n" + + ".section .fixup, \"ax\"\n" + "4: mov %0, #1 \n" + " b 3b \n" + ".previous\n" + + ".section __ex_table, \"a\"\n" + " .long 1b, 4b \n" + " .long 2b, 4b \n" + ".previous\n" + + : "=r"(err), "=r"(replaced) + : "r"(pc), "r"(new), "r"(old), "0"(err), "1"(replaced) + : "memory"); + + if (!err && (replaced == old)) + flush_icache_range(pc, pc + MCOUNT_INSN_SIZE); + + return err; +} + +int ftrace_update_ftrace_func(ftrace_func_t func) +{ + int ret; + unsigned long pc, old; + unsigned char *new; + + pc = (unsigned long)&ftrace_call; + memcpy(&old, &ftrace_call, MCOUNT_INSN_SIZE); + new = ftrace_call_replace(pc, (unsigned long)func); + ret = ftrace_modify_code(pc, (unsigned char *)&old, new); + return ret; +} + +int ftrace_mcount_set(unsigned long *data) +{ + unsigned long pc, old; + unsigned long *addr = data; + unsigned char *new; + + pc = (unsigned long)&mcount_call; + memcpy(&old, &mcount_call, MCOUNT_INSN_SIZE); + new = ftrace_call_replace(pc, *addr); + *addr = ftrace_modify_code(pc, (unsigned char *)&old, new); + return 0; +} + +/* run from kstop_machine */ +int __init ftrace_dyn_arch_init(void *data) +{ + ftrace_mcount_set(data); + return 0; +} diff -urN linux-2.6.26/arch/arm/kernel/irq.c linux-2.6.26-lab126/arch/arm/kernel/irq.c --- linux-2.6.26/arch/arm/kernel/irq.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/kernel/irq.c 2010-08-10 04:14:06.000000000 -0400 @@ -37,6 +37,8 @@ #include #include +#include + #include #include @@ -85,7 +87,7 @@ unlock: spin_unlock_irqrestore(&irq_desc[i].lock, flags); } else if (i == NR_IRQS) { -#ifdef CONFIG_ARCH_ACORN +#ifdef CONFIG_FIQ show_fiq_list(p, v); #endif #ifdef CONFIG_SMP @@ -100,7 +102,7 @@ /* Handle bad interrupts */ static struct irq_desc bad_irq_desc = { .handle_irq = handle_bad_irq, - .lock = SPIN_LOCK_UNLOCKED + .lock = RAW_SPIN_LOCK_UNLOCKED(bad_irq_desc.lock) }; /* @@ -108,11 +110,13 @@ * come via this function. Instead, they should provide their * own 'handler' */ -asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs) +asmlinkage void __exception notrace asm_do_IRQ(unsigned int irq, struct pt_regs *regs) { struct pt_regs *old_regs = set_irq_regs(regs); struct irq_desc *desc = irq_desc + irq; + trace_event_irq(irq, user_mode(regs), instruction_pointer(regs)); + /* * Some hardware gives randomly wrong interrupts. Rather * than crashing, do something sensible. diff -urN linux-2.6.26/arch/arm/kernel/kgdb.c linux-2.6.26-lab126/arch/arm/kernel/kgdb.c --- linux-2.6.26/arch/arm/kernel/kgdb.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/kernel/kgdb.c 2010-08-10 04:14:06.000000000 -0400 @@ -0,0 +1,206 @@ +/* + * arch/arm/kernel/kgdb.c + * + * ARM KGDB support + * + * Copyright (c) 2002-2004 MontaVista Software, Inc + * Copyright (c) 2008 Wind River Systems, Inc. + * + * Authors: George Davis + * Deepak Saxena + * + * Copyright 2009 Amazon Technologies, Inc. All Rights Reserved. + * Manish Lachwani (lachwani@lab126.com) + */ + +#include +#include + +/* Make a local copy of the registers passed into the handler (bletch) */ +void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *kernel_regs) +{ + int regno; + + /* Initialize all to zero. */ + for (regno = 0; regno < GDB_MAX_REGS; regno++) + gdb_regs[regno] = 0; + + gdb_regs[_R0] = kernel_regs->ARM_r0; + gdb_regs[_R1] = kernel_regs->ARM_r1; + gdb_regs[_R2] = kernel_regs->ARM_r2; + gdb_regs[_R3] = kernel_regs->ARM_r3; + gdb_regs[_R4] = kernel_regs->ARM_r4; + gdb_regs[_R5] = kernel_regs->ARM_r5; + gdb_regs[_R6] = kernel_regs->ARM_r6; + gdb_regs[_R7] = kernel_regs->ARM_r7; + gdb_regs[_R8] = kernel_regs->ARM_r8; + gdb_regs[_R9] = kernel_regs->ARM_r9; + gdb_regs[_R10] = kernel_regs->ARM_r10; + gdb_regs[_FP] = kernel_regs->ARM_fp; + gdb_regs[_IP] = kernel_regs->ARM_ip; + gdb_regs[_SPT] = kernel_regs->ARM_sp; + gdb_regs[_LR] = kernel_regs->ARM_lr; + gdb_regs[_PC] = kernel_regs->ARM_pc; + gdb_regs[_CPSR] = kernel_regs->ARM_cpsr; +} + +/* Copy local gdb registers back to kgdb regs, for later copy to kernel */ +void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *kernel_regs) +{ + kernel_regs->ARM_r0 = gdb_regs[_R0]; + kernel_regs->ARM_r1 = gdb_regs[_R1]; + kernel_regs->ARM_r2 = gdb_regs[_R2]; + kernel_regs->ARM_r3 = gdb_regs[_R3]; + kernel_regs->ARM_r4 = gdb_regs[_R4]; + kernel_regs->ARM_r5 = gdb_regs[_R5]; + kernel_regs->ARM_r6 = gdb_regs[_R6]; + kernel_regs->ARM_r7 = gdb_regs[_R7]; + kernel_regs->ARM_r8 = gdb_regs[_R8]; + kernel_regs->ARM_r9 = gdb_regs[_R9]; + kernel_regs->ARM_r10 = gdb_regs[_R10]; + kernel_regs->ARM_fp = gdb_regs[_FP]; + kernel_regs->ARM_ip = gdb_regs[_IP]; + kernel_regs->ARM_sp = gdb_regs[_SPT]; + kernel_regs->ARM_lr = gdb_regs[_LR]; + kernel_regs->ARM_pc = gdb_regs[_PC]; + kernel_regs->ARM_cpsr = gdb_regs[_CPSR]; +} + +void +sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *task) +{ + struct pt_regs *thread_regs; + int regno; + + /* Just making sure... */ + if (task == NULL) + return; + + /* Initialize to zero */ + for (regno = 0; regno < GDB_MAX_REGS; regno++) + gdb_regs[regno] = 0; + + /* Otherwise, we have only some registers from switch_to() */ + thread_regs = task_pt_regs(task); + gdb_regs[_R0] = thread_regs->ARM_r0; + gdb_regs[_R1] = thread_regs->ARM_r1; + gdb_regs[_R2] = thread_regs->ARM_r2; + gdb_regs[_R3] = thread_regs->ARM_r3; + gdb_regs[_R4] = thread_regs->ARM_r4; + gdb_regs[_R5] = thread_regs->ARM_r5; + gdb_regs[_R6] = thread_regs->ARM_r6; + gdb_regs[_R7] = thread_regs->ARM_r7; + gdb_regs[_R8] = thread_regs->ARM_r8; + gdb_regs[_R9] = thread_regs->ARM_r9; + gdb_regs[_R10] = thread_regs->ARM_r10; + gdb_regs[_FP] = thread_regs->ARM_fp; + gdb_regs[_IP] = thread_regs->ARM_ip; + gdb_regs[_SPT] = thread_regs->ARM_sp; + gdb_regs[_LR] = thread_regs->ARM_lr; + gdb_regs[_PC] = thread_regs->ARM_pc; + gdb_regs[_CPSR] = thread_regs->ARM_cpsr; +} + +static int compiled_break; + +int kgdb_arch_handle_exception(int exception_vector, int signo, + int err_code, char *remcom_in_buffer, + char *remcom_out_buffer, + struct pt_regs *linux_regs) +{ + unsigned long addr; + char *ptr; + + switch (remcom_in_buffer[0]) { + case 'D': + case 'k': + case 'c': + kgdb_contthread = NULL; + + /* + * Try to read optional parameter, pc unchanged if no parm. + * If this was a compiled breakpoint, we need to move + * to the next instruction or we will just breakpoint + * over and over again. + */ + ptr = &remcom_in_buffer[1]; + if (kgdb_hex2long(&ptr, &addr)) + linux_regs->ARM_pc = addr; + else if (compiled_break == 1) + linux_regs->ARM_pc += 4; + + compiled_break = 0; + + return 0; + } + + return -1; +} + +static int kgdb_brk_fn(struct pt_regs *regs, unsigned int instr) +{ + kgdb_handle_exception(1, SIGTRAP, 0, regs); + + return 0; +} + +static int kgdb_compiled_brk_fn(struct pt_regs *regs, unsigned int instr) +{ + compiled_break = 1; + kgdb_handle_exception(1, SIGTRAP, 0, regs); + + return 0; +} + +static struct undef_hook kgdb_brkpt_hook = { + .instr_mask = 0xffffffff, + .instr_val = KGDB_BREAKINST, + .fn = kgdb_brk_fn +}; + +static struct undef_hook kgdb_compiled_brkpt_hook = { + .instr_mask = 0xffffffff, + .instr_val = KGDB_COMPILED_BREAK, + .fn = kgdb_compiled_brk_fn +}; + +/** + * kgdb_arch_init - Perform any architecture specific initalization. + * + * This function will handle the initalization of any architecture + * specific callbacks. + */ +int kgdb_arch_init(void) +{ + register_undef_hook(&kgdb_brkpt_hook); + register_undef_hook(&kgdb_compiled_brkpt_hook); + + return 0; +} + +/** + * kgdb_arch_exit - Perform any architecture specific uninitalization. + * + * This function will handle the uninitalization of any architecture + * specific callbacks, for dynamic registration and unregistration. + */ +void kgdb_arch_exit(void) +{ + unregister_undef_hook(&kgdb_brkpt_hook); + unregister_undef_hook(&kgdb_compiled_brkpt_hook); +} + +/* + * Register our undef instruction hooks with ARM undef core. + * We regsiter a hook specifically looking for the KGB break inst + * and we handle the normal undef case within the do_undefinstr + * handler. + */ +struct kgdb_arch arch_kgdb_ops = { +#ifndef __ARMEB__ + .gdb_bpt_instr = {0xfe, 0xde, 0xff, 0xe7} +#else /* ! __ARMEB__ */ + .gdb_bpt_instr = {0xe7, 0xff, 0xde, 0xfe} +#endif +}; + diff -urN linux-2.6.26/arch/arm/kernel/process.c linux-2.6.26-lab126/arch/arm/kernel/process.c --- linux-2.6.26/arch/arm/kernel/process.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/kernel/process.c 2010-08-10 04:14:06.000000000 -0400 @@ -36,6 +36,8 @@ #include #include +DEFINE_RAW_SPINLOCK(futex_atomic_lock); + static const char *processor_modes[] = { "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" , "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26", @@ -164,14 +166,16 @@ if (!idle) idle = default_idle; leds_event(led_idle_start); - tick_nohz_stop_sched_tick(); + tick_nohz_stop_sched_tick(1); while (!need_resched()) idle(); leds_event(led_idle_end); tick_nohz_restart_sched_tick(); - preempt_enable_no_resched(); - schedule(); + local_irq_disable(); + __preempt_enable_no_resched(); + __schedule(); preempt_disable(); + local_irq_enable(); } } @@ -185,17 +189,17 @@ __setup("reboot=", reboot_setup); -void machine_halt(void) -{ -} - - void machine_power_off(void) { if (pm_power_off) pm_power_off(); } +void machine_halt(void) +{ + machine_power_off(); +} + void machine_restart(char * __unused) { arm_pm_restart(reboot_mode); @@ -352,6 +356,15 @@ } /* + * Fill in the task's elfregs structure for a core dump. + */ +int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs) +{ + elf_core_copy_regs(elfregs, task_pt_regs(t)); + return 1; +} + +/* * fill in the fpe structure for a core dump... */ int dump_fpu (struct pt_regs *regs, struct user_fp *fp) diff -urN linux-2.6.26/arch/arm/kernel/ptrace.c linux-2.6.26-lab126/arch/arm/kernel/ptrace.c --- linux-2.6.26/arch/arm/kernel/ptrace.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/kernel/ptrace.c 2010-08-10 04:14:06.000000000 -0400 @@ -655,6 +655,54 @@ } #endif +#ifdef CONFIG_VFP +/* + * Get the child VFP state. + */ +static int ptrace_getvfpregs(struct task_struct *tsk, void __user *data) +{ + struct thread_info *thread = task_thread_info(tsk); + union vfp_state *vfp = &thread->vfpstate; + struct user_vfp __user *ufp = data; + + vfp_sync_state(thread); + + /* copy the floating point registers */ + if (copy_to_user(&ufp->fpregs, &vfp->hard.fpregs, + sizeof(vfp->hard.fpregs))) + return -EFAULT; + + /* copy the status and control register */ + if (put_user(vfp->hard.fpscr, &ufp->fpscr)) + return -EFAULT; + + return 0; +} + +/* + * Set the child VFP state. + */ +static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data) +{ + struct thread_info *thread = task_thread_info(tsk); + union vfp_state *vfp = &thread->vfpstate; + struct user_vfp __user *ufp = data; + + vfp_sync_state(thread); + + /* copy the floating point registers */ + if (copy_from_user(&vfp->hard.fpregs, &ufp->fpregs, + sizeof(vfp->hard.fpregs))) + return -EFAULT; + + /* copy the status and control register */ + if (get_user(vfp->hard.fpscr, &ufp->fpscr)) + return -EFAULT; + + return 0; +} +#endif + long arch_ptrace(struct task_struct *child, long request, long addr, long data) { int ret; @@ -777,6 +825,15 @@ break; #endif +#ifdef CONFIG_VFP + case PTRACE_GETVFPREGS: + ret = ptrace_getvfpregs(child, (void __user *)data); + break; + + case PTRACE_SETVFPREGS: + ret = ptrace_setvfpregs(child, (void __user *)data); + break; +#endif default: ret = ptrace_request(child, request, addr, data); break; diff -urN linux-2.6.26/arch/arm/kernel/setup.c linux-2.6.26-lab126/arch/arm/kernel/setup.c --- linux-2.6.26/arch/arm/kernel/setup.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/kernel/setup.c 2010-08-10 04:14:06.000000000 -0400 @@ -36,6 +36,7 @@ #include #include #include +#include #include "compat.h" #include "atags.h" @@ -68,6 +69,12 @@ unsigned int __atags_pointer __initdata; +unsigned char system_rev16[REVISION16_SIZE]; +EXPORT_SYMBOL(system_rev16); + +unsigned char system_serial16[SERIAL16_SIZE]; +EXPORT_SYMBOL(system_serial16); + unsigned int system_rev; EXPORT_SYMBOL(system_rev); @@ -717,9 +724,30 @@ __tagtable(ATAG_REVISION, parse_tag_revision); +static int __init parse_tag_serial16(const struct tag *tag) +{ + memcpy(system_serial16, tag->u.id16.data, SERIAL16_SIZE); +#if 0 + printk(KERN_DEBUG "ATAGS:serial16:str=\"%.*s\"\n", SERIAL16_SIZE, system_serial16); +#endif + return 0; +} + +__tagtable(ATAG_SERIAL16, parse_tag_serial16); + +static int __init parse_tag_revision16(const struct tag *tag) +{ + memcpy(system_rev16, tag->u.id16.data, REVISION16_SIZE); + printk(KERN_DEBUG "ATAGS:rev16:str=\"%.*s\"\n", REVISION16_SIZE, system_rev16); + return 0; +} +__tagtable(ATAG_REVISION16, parse_tag_revision16); + static int __init parse_tag_cmdline(const struct tag *tag) { +#if 0 strlcpy(default_command_line, tag->u.cmdline.cmdline, COMMAND_LINE_SIZE); +#endif return 0; } @@ -737,6 +765,7 @@ for (t = &__tagtable_begin; t < &__tagtable_end; t++) if (tag->hdr.tag == t->tag) { + // printk(KERN_DEBUG "ATAGS:tag=0x%08x size=%d\n", tag->hdr.tag, tag->hdr.size); t->parse(tag); break; } @@ -750,11 +779,12 @@ */ static void __init parse_tags(const struct tag *t) { - for (; t->hdr.size; t = tag_next(t)) + for (; (t->hdr.tag != ATAG_NONE) && t->hdr.size; t = tag_next(t)) { if (!parse_tag(t)) printk(KERN_WARNING "Ignoring unrecognised tag 0x%08x\n", t->hdr.tag); + } } /* @@ -853,6 +883,7 @@ conswitchp = &dummy_con; #endif #endif + early_trap_init(); } @@ -980,8 +1011,28 @@ seq_printf(m, "Hardware\t: %s\n", machine_name); seq_printf(m, "Revision\t: %04x\n", system_rev); - seq_printf(m, "Serial\t\t: %08x%08x\n", - system_serial_high, system_serial_low); + + /* if 16-byte serial was initialized, print that. */ + if (system_serial16[0]) { + char serial_num[SERIAL16_SIZE + 1]; + + memset(serial_num, '\0', sizeof(serial_num)); + strncpy(serial_num, system_serial16, SERIAL16_SIZE); + seq_printf(m, "Serial\t\t: \"%s\"\n", serial_num); + } else { + /* no 16-byte serial, use the 64-bit one. */ + seq_printf(m, "Serial\t\t: %08x%08x\n", + system_serial_high, system_serial_low); + } + + /* if 16-byte revision was initialized, print that. */ + if (system_rev16[0]) { + char board_id[REVISION16_SIZE + 1]; + + memset(board_id, '\0', sizeof(board_id)); + strncpy(board_id, system_rev16, REVISION16_SIZE); + seq_printf(m, "BoardId\t\t: \"%s\"\n", board_id); + } return 0; } diff -urN linux-2.6.26/arch/arm/kernel/signal.c linux-2.6.26-lab126/arch/arm/kernel/signal.c --- linux-2.6.26/arch/arm/kernel/signal.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/kernel/signal.c 2010-08-10 04:14:06.000000000 -0400 @@ -623,6 +623,14 @@ siginfo_t info; int signr; +#ifdef CONFIG_PREEMPT_RT + /* + * Fully-preemptible kernel does not need interrupts disabled: + */ + local_irq_enable(); + preempt_check_resched(); +#endif + /* * We want the common case to go fast, which * is why we may in certain cases get here from diff -urN linux-2.6.26/arch/arm/kernel/smp.c linux-2.6.26-lab126/arch/arm/kernel/smp.c --- linux-2.6.26/arch/arm/kernel/smp.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/kernel/smp.c 2010-08-10 04:14:06.000000000 -0400 @@ -542,7 +542,7 @@ cpu_clear(cpu, data->unfinished); } -static DEFINE_SPINLOCK(stop_lock); +static DEFINE_RAW_SPINLOCK(stop_lock); /* * ipi_cpu_stop - handle IPI from smp_send_stop() diff -urN linux-2.6.26/arch/arm/kernel/time.c linux-2.6.26-lab126/arch/arm/kernel/time.c --- linux-2.6.26/arch/arm/kernel/time.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/kernel/time.c 2010-08-10 04:14:06.000000000 -0400 @@ -70,7 +70,7 @@ /* * hook for setting the RTC's idea of the current time. */ -int (*set_rtc)(void); +int (*set_rtc)(struct timespec now); #ifndef CONFIG_GENERIC_TIME static unsigned long dummy_gettimeoffset(void) @@ -79,34 +79,12 @@ } #endif -static unsigned long next_rtc_update; - -/* - * If we have an externally synchronized linux clock, then update - * CMOS clock accordingly every ~11 minutes. set_rtc() has to be - * called as close as possible to 500 ms before the new second - * starts. - */ -static inline void do_set_rtc(void) +int update_persistent_clock(struct timespec now) { - if (!ntp_synced() || set_rtc == NULL) - return; - - if (next_rtc_update && - time_before((unsigned long)xtime.tv_sec, next_rtc_update)) - return; + if (set_rtc == NULL) + return -1; - if (xtime.tv_nsec < 500000000 - ((unsigned) tick_nsec >> 1) && - xtime.tv_nsec >= 500000000 + ((unsigned) tick_nsec >> 1)) - return; - - if (set_rtc()) - /* - * rtc update failed. Try again in 60s - */ - next_rtc_update = xtime.tv_sec + 60; - else - next_rtc_update = xtime.tv_sec + 660; + return set_rtc(now); } #ifdef CONFIG_LEDS @@ -293,9 +271,10 @@ */ void save_time_delta(struct timespec *delta, struct timespec *rtc) { + struct timespec now = current_kernel_time(); set_normalized_timespec(delta, - xtime.tv_sec - rtc->tv_sec, - xtime.tv_nsec - rtc->tv_nsec); + now.tv_sec - rtc->tv_sec, + now.tv_nsec - rtc->tv_nsec); } EXPORT_SYMBOL(save_time_delta); @@ -324,7 +303,6 @@ { profile_tick(CPU_PROFILING); do_leds(); - do_set_rtc(); write_seqlock(&xtime_lock); do_timer(1); write_sequnlock(&xtime_lock); diff -urN linux-2.6.26/arch/arm/kernel/traps.c linux-2.6.26-lab126/arch/arm/kernel/traps.c --- linux-2.6.26/arch/arm/kernel/traps.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/kernel/traps.c 2010-08-10 04:14:06.000000000 -0400 @@ -29,10 +29,15 @@ #include #include +#ifdef CONFIG_MACH_LUIGI_LAB126 +#include +#endif + #include "ptrace.h" #include "signal.h" static const char *handler[]= { "prefetch abort", "data abort", "address exception", "interrupt" }; +extern void mxc_wd_reset(void); #ifdef CONFIG_DEBUG_USER unsigned int user_debug; @@ -45,6 +50,14 @@ __setup("user_debug=", user_debug_setup); #endif +#ifdef CONFIG_MACH_LUIGI_LAB126 +char bug_buffer[100]; +static int bug_buffer_filled = 0; + +int kernel_oops_counter = 0; +EXPORT_SYMBOL(kernel_oops_counter); +#endif + static void dump_mem(const char *str, unsigned long bottom, unsigned long top); void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame) @@ -205,13 +218,45 @@ #define S_SMP "" #endif +char die_buffer[OOPS_SAVE_SIZE]; +char *die_start; +unsigned die_len; +static unsigned die_oops_enable; + +void insert_oops_chars(char c) +{ + if (!die_oops_enable) + return; + + die_buffer[die_len++] = c; +} +EXPORT_SYMBOL(insert_oops_chars); + static void __die(const char *str, int err, struct thread_info *thread, struct pt_regs *regs) { struct task_struct *tsk = thread->task; static int die_counter; +#ifdef CONFIG_MACH_LUIGI_LAB126 + die_len = 0; /* Initialize */ + die_start = die_buffer; + kernel_oops_counter++; + + die_buffer[die_len++] = 'O'; + die_buffer[die_len++] = 'O'; + die_buffer[die_len++] = 'P'; + die_buffer[die_len++] = 'S'; + die_buffer[die_len++] = ':'; + die_start += die_len; + + if (bug_buffer_filled == 1) { + die_len += sprintf(die_start, "%s\n", bug_buffer); + die_start += die_len; + } +#endif printk("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n", str, err, ++die_counter); + sysfs_printk_last_file(); print_modules(); __show_regs(regs); printk("Process %s (pid: %d, stack limit = 0x%p)\n", @@ -225,7 +270,11 @@ } } -DEFINE_SPINLOCK(die_lock); +DEFINE_RAW_SPINLOCK(die_lock); + +#ifdef CONFIG_MACH_LUIGI_LAB126 +extern void *oops_start; +#endif /* * This function is protected against re-entrancy. @@ -233,24 +282,39 @@ NORET_TYPE void die(const char *str, struct pt_regs *regs, int err) { struct thread_info *thread = current_thread_info(); - +#ifdef CONFIG_MACH_LUIGI_LAB126 + void *die_oops_start = oops_start; + memset(die_oops_start, 0, OOPS_SAVE_SIZE); + die_oops_enable = 1; +#endif oops_enter(); - console_verbose(); spin_lock_irq(&die_lock); + console_verbose(); bust_spinlocks(1); __die(str, err, thread, regs); +#ifdef CONFIG_MACH_LUIGI_LAB126 + die_oops_enable = 0; + die_buffer[die_len++] = '\0'; +#endif bust_spinlocks(0); add_taint(TAINT_DIE); +#ifdef CONFIG_MACH_LUIGI_LAB126 + memcpy((void *)die_oops_start, (void *)die_buffer, OOPS_SAVE_SIZE); +#endif spin_unlock_irq(&die_lock); + oops_exit(); +#ifdef CONFIG_MACH_LUIGI_LAB126 + if (bug_buffer_filled) + mxc_wd_reset(); +#endif if (in_interrupt()) panic("Fatal exception in interrupt"); if (panic_on_oops) panic("Fatal exception"); - oops_exit(); do_exit(SIGSEGV); } @@ -268,7 +332,7 @@ } static LIST_HEAD(undef_hook); -static DEFINE_SPINLOCK(undef_lock); +static DEFINE_RAW_SPINLOCK(undef_lock); void register_undef_hook(struct undef_hook *hook) { @@ -288,14 +352,27 @@ spin_unlock_irqrestore(&undef_lock, flags); } +static int call_arm_undef_hook(struct pt_regs *regs, unsigned int instr) +{ + struct undef_hook *hook; + unsigned long flags; + int (*fn)(struct pt_regs *regs, unsigned int instr) = NULL; + + spin_lock_irqsave(&undef_lock, flags); + list_for_each_entry(hook, &undef_hook, node) + if ((instr & hook->instr_mask) == hook->instr_val && + (regs->ARM_cpsr & hook->cpsr_mask) == hook->cpsr_val) + fn = hook->fn; + spin_unlock_irqrestore(&undef_lock, flags); + return fn ? fn(regs, instr) : 1; +} + asmlinkage void __exception do_undefinstr(struct pt_regs *regs) { unsigned int correction = thumb_mode(regs) ? 2 : 4; unsigned int instr; - struct undef_hook *hook; siginfo_t info; void __user *pc; - unsigned long flags; /* * According to the ARM ARM, PC is 2 or 4 bytes ahead, @@ -325,17 +402,8 @@ } #endif - spin_lock_irqsave(&undef_lock, flags); - list_for_each_entry(hook, &undef_hook, node) { - if ((instr & hook->instr_mask) == hook->instr_val && - (regs->ARM_cpsr & hook->cpsr_mask) == hook->cpsr_val) { - if (hook->fn(regs, instr) == 0) { - spin_unlock_irqrestore(&undef_lock, flags); - return; - } - } - } - spin_unlock_irqrestore(&undef_lock, flags); + if (call_arm_undef_hook(regs, instr) == 0) + return; #ifdef CONFIG_DEBUG_USER if (user_debug & UDBG_UNDEFINED) { @@ -357,6 +425,7 @@ { printk("Hmm. Unexpected FIQ received, but trying to continue\n"); printk("You may have a hardware problem...\n"); + print_preempt_trace(current); } /* @@ -556,7 +625,7 @@ if not implemented, rather than raising SIGILL. This way the calling program can gracefully determine whether a feature is supported. */ - if (no <= 0x7ff) + if ((no & 0xffff) <= 0x7ff) return -ENOSYS; break; } @@ -660,7 +729,16 @@ void __attribute__((noreturn)) __bug(const char *file, int line) { +#ifdef CONFIG_MACH_LUIGI_LAB126 + unsigned tlen; + char *start = bug_buffer; + + tlen = sprintf(start, "kernel BUG at %s:%d!\n", file, line); + printk(KERN_CRIT"%s\n", bug_buffer); + bug_buffer_filled = 1; +#else printk(KERN_CRIT"kernel BUG at %s:%d!\n", file, line); +#endif *(int *)0 = 0; /* Avoid "noreturn function does return" */ @@ -708,6 +786,11 @@ void __init trap_init(void) { + return; +} + +void __init early_trap_init(void) +{ unsigned long vectors = CONFIG_VECTORS_BASE; extern char __stubs_start[], __stubs_end[]; extern char __vectors_start[], __vectors_end[]; diff -urN linux-2.6.26/arch/arm/kernel/vmlinux.lds.S linux-2.6.26-lab126/arch/arm/kernel/vmlinux.lds.S --- linux-2.6.26/arch/arm/kernel/vmlinux.lds.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/kernel/vmlinux.lds.S 2010-08-10 04:14:06.000000000 -0400 @@ -6,6 +6,7 @@ #include #include #include +#include OUTPUT_ARCH(arm) ENTRY(stext) @@ -63,7 +64,7 @@ usr/built-in.o(.init.ramfs) __initramfs_end = .; #endif - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); __per_cpu_start = .; *(.data.percpu) *(.data.percpu.shared_aligned) @@ -71,7 +72,7 @@ #ifndef CONFIG_XIP_KERNEL __init_begin = _stext; INIT_DATA - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); __init_end = .; #endif } @@ -106,7 +107,7 @@ *(.got) /* Global offset table */ } - RODATA + RO_DATA(PAGE_SIZE) _etext = .; /* End of text and rodata section */ @@ -128,17 +129,17 @@ *(.data.init_task) #ifdef CONFIG_XIP_KERNEL - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); __init_begin = .; INIT_DATA - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); __init_end = .; #endif - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); __nosave_begin = .; *(.data.nosave) - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); __nosave_end = .; /* diff -urN linux-2.6.26/arch/arm/lib/Makefile linux-2.6.26-lab126/arch/arm/lib/Makefile --- linux-2.6.26/arch/arm/lib/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/lib/Makefile 2010-08-10 04:14:10.000000000 -0400 @@ -41,6 +41,7 @@ lib-$(CONFIG_ARCH_CLPS7500) += io-acorn.o lib-$(CONFIG_ARCH_L7200) += io-acorn.o lib-$(CONFIG_ARCH_SHARK) += io-shark.o +lib-$(CONFIG_STACKTRACE) += stacktrace.o $(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S $(obj)/csumpartialcopyuser.o: $(obj)/csumpartialcopygeneric.S diff -urN linux-2.6.26/arch/arm/lib/stacktrace.c linux-2.6.26-lab126/arch/arm/lib/stacktrace.c --- linux-2.6.26/arch/arm/lib/stacktrace.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/lib/stacktrace.c 2010-08-10 04:14:10.000000000 -0400 @@ -0,0 +1,7 @@ +#include +#include + +void save_stack_trace(struct stack_trace *trace) +{ +} + diff -urN linux-2.6.26/arch/arm/mach-at91/gpio.c linux-2.6.26-lab126/arch/arm/mach-at91/gpio.c --- linux-2.6.26/arch/arm/mach-at91/gpio.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mach-at91/gpio.c 2010-08-10 04:14:04.000000000 -0400 @@ -368,12 +368,18 @@ } } +static void gpio_irq_ack_noop(unsigned int irq) +{ + /* Dummy function. */ +} + static struct irq_chip gpio_irqchip = { .name = "GPIO", .mask = gpio_irq_mask, .unmask = gpio_irq_unmask, .set_type = gpio_irq_type, .set_wake = gpio_irq_set_wake, + .ack = gpio_irq_ack_noop, }; static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) @@ -522,7 +528,7 @@ * shorter, and the AIC handles interrupts sanely. */ set_irq_chip(pin, &gpio_irqchip); - set_irq_handler(pin, handle_simple_irq); + set_irq_handler(pin, handle_edge_irq); set_irq_flags(pin, IRQF_VALID); } diff -urN linux-2.6.26/arch/arm/mach-footbridge/netwinder-hw.c linux-2.6.26-lab126/arch/arm/mach-footbridge/netwinder-hw.c --- linux-2.6.26/arch/arm/mach-footbridge/netwinder-hw.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mach-footbridge/netwinder-hw.c 2010-08-10 04:14:13.000000000 -0400 @@ -67,7 +67,7 @@ /* * This is a lock for accessing ports GP1_IO_BASE and GP2_IO_BASE */ -DEFINE_SPINLOCK(gpio_lock); +DEFINE_RAW_SPINLOCK(gpio_lock); static unsigned int current_gpio_op; static unsigned int current_gpio_io; diff -urN linux-2.6.26/arch/arm/mach-footbridge/netwinder-leds.c linux-2.6.26-lab126/arch/arm/mach-footbridge/netwinder-leds.c --- linux-2.6.26/arch/arm/mach-footbridge/netwinder-leds.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mach-footbridge/netwinder-leds.c 2010-08-10 04:14:13.000000000 -0400 @@ -32,7 +32,7 @@ static char hw_led_state; static DEFINE_SPINLOCK(leds_lock); -extern spinlock_t gpio_lock; +extern raw_spinlock_t gpio_lock; static void netwinder_leds_event(led_event_t evt) { diff -urN linux-2.6.26/arch/arm/mach-integrator/core.c linux-2.6.26-lab126/arch/arm/mach-integrator/core.c --- linux-2.6.26/arch/arm/mach-integrator/core.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mach-integrator/core.c 2010-08-10 04:14:04.000000000 -0400 @@ -164,7 +164,7 @@ #define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_CTRL_OFFSET -static DEFINE_SPINLOCK(cm_lock); +static DEFINE_RAW_SPINLOCK(cm_lock); /** * cm_control - update the CM_CTRL register. diff -urN linux-2.6.26/arch/arm/mach-integrator/pci_v3.c linux-2.6.26-lab126/arch/arm/mach-integrator/pci_v3.c --- linux-2.6.26/arch/arm/mach-integrator/pci_v3.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mach-integrator/pci_v3.c 2010-08-10 04:14:04.000000000 -0400 @@ -162,7 +162,7 @@ * 7:2 register number * */ -static DEFINE_SPINLOCK(v3_lock); +static DEFINE_RAW_SPINLOCK(v3_lock); #define PCI_BUS_NONMEM_START 0x00000000 #define PCI_BUS_NONMEM_SIZE SZ_256M diff -urN linux-2.6.26/arch/arm/mach-ixp4xx/common-pci.c linux-2.6.26-lab126/arch/arm/mach-ixp4xx/common-pci.c --- linux-2.6.26/arch/arm/mach-ixp4xx/common-pci.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mach-ixp4xx/common-pci.c 2010-08-10 04:14:16.000000000 -0400 @@ -53,7 +53,7 @@ * these transactions are atomic or we will end up * with corrupt data on the bus or in a driver. */ -static DEFINE_SPINLOCK(ixp4xx_pci_lock); +static DEFINE_RAW_SPINLOCK(ixp4xx_pci_lock); /* * Read from PCI config space diff -urN linux-2.6.26/arch/arm/mach-mx21/Kconfig linux-2.6.26-lab126/arch/arm/mach-mx21/Kconfig --- linux-2.6.26/arch/arm/mach-mx21/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx21/Kconfig 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,17 @@ +menu "MX21 Options" + depends on ARCH_MX21 + +config MX21_OPTIONS + bool + default y + select CPU_ARM926T + select MXC_EMMA + +config MACH_MX21ADS + bool "Support MX21 ADS platforms" + default y + help + Include support for MX21 ADS platform. This includes specific + configurations for the board and its peripherals. + +endmenu diff -urN linux-2.6.26/arch/arm/mach-mx21/Makefile linux-2.6.26-lab126/arch/arm/mach-mx21/Makefile --- linux-2.6.26/arch/arm/mach-mx21/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx21/Makefile 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,12 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. + +obj-y := mm.o time.o dma.o gpio_mux.o clock.o devices.o serial.o system.o +obj-$(CONFIG_MACH_MX21ADS) += mx21ads.o mx21ads_gpio.o + +# power management +obj-$(CONFIG_PM) += pm.o mxc_pm.o +obj-$(CONFIG_DPM) += dpm.o diff -urN linux-2.6.26/arch/arm/mach-mx21/Makefile.boot linux-2.6.26-lab126/arch/arm/mach-mx21/Makefile.boot --- linux-2.6.26/arch/arm/mach-mx21/Makefile.boot 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx21/Makefile.boot 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,3 @@ + zreladdr-y := 0xC0008000 +params_phys-y := 0xC0000100 +initrd_phys-y := 0xC0800000 diff -urN linux-2.6.26/arch/arm/mach-mx21/board-mx21ads.h linux-2.6.26-lab126/arch/arm/mach-mx21/board-mx21ads.h --- linux-2.6.26/arch/arm/mach-mx21/board-mx21ads.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx21/board-mx21ads.h 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,145 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX21ADS_H__ +#define __ASM_ARCH_MXC_BOARD_MX21ADS_H__ + +/*! + * @defgroup BRDCFG Board Configuration Options + * @ingroup MSL + */ + +/*! + * @file arch-mxc/board-mx21ads.h + * + * @brief This file contains all the board level configuration options. + * + * It currently hold the options defined for MX21 ADS Platform. + * + * @ingroup BRDCFG + */ + +/* + * Include Files + */ +#include + +/* Start of physical RAM */ +#define PHYS_OFFSET UL(0xC0000000) + +/* Size of contiguous memory for DMA and other h/w blocks */ +#define CONSISTENT_DMA_SIZE SZ_8M + +/*! + * @name MXC UART EVB board level configurations + */ +/*! @{ */ +/*! + * Specify the max baudrate for the MXC UARTs for your board, do not specify a max + * baudrate greater than 1500000. This is used while specifying the UART Power + * management constraints. + */ +#define MAX_UART_BAUDRATE 1500000 +/*! + * Specifies if the Irda transmit path is inverting + */ +#define MXC_IRDA_TX_INV 0 +/*! + * Specifies if the Irda receive path is inverting + */ +#define MXC_IRDA_RX_INV 0 +/* UART 1 configuration */ +/*! + * This define specifies if the UART port is configured to be in DTE or + * DCE mode. There exists a define like this for each UART port. Valid + * values that can be used are \b MODE_DTE or \b MODE_DCE. + */ +#define UART1_MODE MODE_DCE +/*! + * This define specifies if the UART is to be used for IRDA. There exists a + * define like this for each UART port. Valid values that can be used are + * \b IRDA or \b NO_IRDA. + */ +#define UART1_IR NO_IRDA +/*! + * This define is used to enable or disable a particular UART port. If + * disabled, the UART will not be registered in the file system and the user + * will not be able to access it. There exists a define like this for each UART + * port. Specify a value of 1 to enable the UART and 0 to disable it. + */ +#define UART1_ENABLED 1 +/*! @} */ +/* UART 2 configuration */ +#define UART2_MODE MODE_DCE +#define UART2_IR NO_IRDA +#define UART2_ENABLED 1 +/* UART 3 configuration */ +#define UART3_MODE MODE_DTE +#define UART3_IR IRDA +#define UART3_ENABLED 1 +/* UART 4 configuration */ +#define UART4_MODE MODE_DTE +#define UART4_IR NO_IRDA +#define UART4_ENABLED 1 /* Enable UART 4 */ + +#define MXC_LL_EXTUART_PADDR (CS1_BASE_ADDR + 0x200000) +#define MXC_LL_EXTUART_VADDR CS1_IO_ADDRESS(MXC_LL_EXTUART_PADDR) +#define MXC_LL_EXTUART_16BIT_BUS + +#define MXC_LL_UART_PADDR UART1_BASE_ADDR +#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR) + +/*! + * @name Memory Size parameters + */ +/*! @{ */ +/*! + * Size of SDRAM memory + */ +#define SDRAM_MEM_SIZE SZ_64M +/*! + * Size of display buffer memory + */ +#define MXCLCDC_MEM_SIZE SZ_8M +/*! + * Size of memory available to kernel + */ +#define MEM_SIZE (SDRAM_MEM_SIZE - MXCLCDC_MEM_SIZE) +/*! @} */ + +/*! @{ */ +/*! + * @name Keypad Configurations + */ +/*! @{ */ +/*! + * Maximum number of rows (0 to 7) + */ +#define MAXROW 6 +/*! + * Maximum number of columns (0 to 7) + */ +#define MAXCOL 6 +/*! @} */ + +/*! + * @name Defines Base address and IRQ used for CS8900A Ethernet Controller on MXC Boards + */ +/*! @{*/ +/*! This is System IRQ used by CS8900A for interrupt generation taken from platform.h */ +#define CS8900AIRQ IOMUX_TO_IRQ(MX21_PIN_UART3_RTS) +/*! This is I/O Base address used to access registers of CS8900A on MXC ADS */ +#define CS8900A_BASE_ADDRESS (IO_ADDRESS(CS1_BASE_ADDR)) +/*! @} */ + +#endif /* __ASM_ARCH_MXC_BOARD_MX21ADS_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx21/clock.c linux-2.6.26-lab126/arch/arm/mach-mx21/clock.c --- linux-2.6.26/arch/arm/mach-mx21/clock.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx21/clock.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,664 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file clock.c + * @brief API for setting up and retrieving clocks. + * + * This file contains API for setting up and retrieving clocks. + * + * @ingroup CLOCKS + */ + +#include +#include +#include +#include +#include "crm_regs.h" +/*! + * Spinlock to protect CRM register accesses + */ +static DEFINE_SPINLOCK(mxc_crm_lock); + +/*! + * g_emma_clock_map is defined to control the emma_clock . + * emma_clock will be disabled until emma_prp_clk and emma_pp_clk are closed. + */ +#define MXC_CLK_EMMA_PRP 0 +#define MXC_CLK_EMMA_PP 1 +static int g_emma_clock_map = 0; + +#define MXC_REG_BIT_MOD(r, off, en) (r = (r & (~(1 << off))) | (en << off)) + +/*! + * This function enables the emma clock. + * @param source each bit of source indicate the clock status of mdoule + * which is using emma clk + * @return none + */ +static void inline __enable_emma_clk(unsigned long source) +{ + unsigned long reg; + + if (g_emma_clock_map == 0) { + reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR0); + MXC_REG_BIT_MOD(reg, CCM_PCCR0_EMMA_OFFSET, 1); + MXC_REG_BIT_MOD(reg, CCM_PCCR0_HCLK_EMMA_OFFSET, 1); + __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR0); + } + g_emma_clock_map |= (1 << source); +} + +/*! + * This function disables the emma clock. + * @param source each bit of source indicate the clock status of mdoule + * which is using emma clk + * @return none + */ +static void inline __disable_emma_clk(unsigned long source) +{ + unsigned long reg; + + g_emma_clock_map &= ~(1 << source); + if (g_emma_clock_map == 0) { + reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR0); + MXC_REG_BIT_MOD(reg, CCM_PCCR0_EMMA_OFFSET, 0); + MXC_REG_BIT_MOD(reg, CCM_PCCR0_HCLK_EMMA_OFFSET, 0); + __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR0); + } +} + +/*! + * This function returns the PLL output value in Hz based on pll. + * @param pll PLL as defined in enum plls + * @return PLL value in Hz. + */ +unsigned long mxc_pll_clock(enum plls pll) +{ + unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0; + unsigned long ref_clk = 0, pll_out = 0; + volatile unsigned long reg, cscr; + + cscr = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR); + if (pll == MCUPLL) { + if ((cscr & CCM_CSCR_MCU) != 0) { + ref_clk = CKIH_CLK_FREQ; + } else { + ref_clk = CKIL_CLK_FREQ; + } + reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_MPCTL0); + pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET; + mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET; + mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET; + mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET; + } else if (pll == SERIALPLL) { + if ((cscr & CCM_CSCR_SP) != 0) { + ref_clk = CKIH_CLK_FREQ; + } else { + ref_clk = CKIL_CLK_FREQ; + } + reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_SPCTL0); + pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET; + mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET; + mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET; + mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET; + } else { + printk(KERN_ERR "Wrong PLL: %d\n", pll); + BUG(); /* oops */ + } + + mfi = (mfi <= 5) ? 5 : mfi; + pll_out = (2 * ref_clk * mfi + ((2 * ref_clk / (mfd + 1)) * mfn)) / + (pdf + 1); + return pll_out; +} + +/*! + * This function returns the mcu main clock frequency + * + * @return mcu main clock value in Hz. + */ +static unsigned long mxc_mcu_main_clock(void) +{ + return mxc_pll_clock(MCUPLL); +} + +/*! + * This function returns the main clock values in Hz. + * + * @param clk as defined in enum mxc_clocks + * + * @return clock value in Hz + */ +unsigned long mxc_get_clocks(enum mxc_clocks clk) +{ + unsigned long pll, spll, ret_val = 0, hclk; + unsigned long presc_pdf, ipg_pdf, nfc_pdf, usb_pdf; + volatile unsigned long cscr = + __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR); + volatile unsigned long pcdr0 = + __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR0); + volatile unsigned long pcdr1 = + __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR1); + + unsigned long fclk, ipgclk, perclk1, perclk2, perclk3, perclk4; + unsigned long bclk_pdf; + unsigned long perclk1_pdf, perclk2_pdf, perclk3_pdf, perclk4_pdf; + unsigned long clk_src; + unsigned long ssi1_pdf = 0; + unsigned long ssi2_pdf = 0; + presc_pdf = (cscr & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET; + bclk_pdf = (cscr & CCM_CSCR_BCLK_MASK) >> CCM_CSCR_BCLK_OFFSET; + ipg_pdf = (cscr & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET; + perclk1_pdf = + (pcdr1 & CCM_PCDR1_PERDIV1_MASK) >> CCM_PCDR1_PERDIV1_OFFSET; + perclk2_pdf = + (pcdr1 & CCM_PCDR1_PERDIV2_MASK) >> CCM_PCDR1_PERDIV2_OFFSET; + perclk3_pdf = + (pcdr1 & CCM_PCDR1_PERDIV3_MASK) >> CCM_PCDR1_PERDIV3_OFFSET; + perclk4_pdf = + (pcdr1 & CCM_PCDR1_PERDIV4_MASK) >> CCM_PCDR1_PERDIV4_OFFSET; + + pll = mxc_mcu_main_clock(); + spll = mxc_pll_clock(SERIALPLL); + fclk = pll / (presc_pdf + 1); + hclk = fclk / (bclk_pdf + 1); + ipgclk = hclk / (ipg_pdf + 1); + perclk1 = pll / (perclk1_pdf + 1); + perclk2 = pll / (perclk2_pdf + 1); + perclk3 = pll / (perclk3_pdf + 1); + perclk4 = pll / (perclk4_pdf + 1); + switch (clk) { + case CPU_CLK: + ret_val = fclk; + break; + case AHB_CLK: + ret_val = hclk; + break; + case PERCLK1: + case UART6_BAUD: + case UART5_BAUD: + case UART4_BAUD: + case UART3_BAUD: + case UART2_BAUD: + case UART1_BAUD: + case GPT6_CLK: + case GPT5_CLK: + case GPT4_CLK: + case GPT3_CLK: + case GPT2_CLK: + case GPT1_CLK: + case PWM_CLK: + ret_val = perclk1; + break; + case PERCLK2: + case SDHC2_CLK: + case SDHC1_CLK: + case CSPI3_CLK: + case CSPI2_CLK: + case CSPI1_CLK: + ret_val = perclk2; + break; + case PERCLK3: + case LCDC_CLK: + ret_val = perclk3; + break; + case PERCLK4: + case CSI_BAUD: + ret_val = perclk4; + break; + case USB_CLK: + usb_pdf = (cscr & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET; + ret_val = spll / (usb_pdf + 1); + break; + case SSI1_BAUD: + ssi1_pdf = (pcdr0 & CCM_PCDR0_SSI1BAUDDIV_MASK) >> + CCM_PCDR0_SSI1BAUDDIV_OFFSET; + clk_src = (cscr & CCM_CSCR_SSI1) >> CCM_CSCR_SSI1_OFFSET; + if (clk_src) + ret_val = pll / (ssi1_pdf + 1); + else + ret_val = spll / (ssi1_pdf + 1); + break; + case SSI2_BAUD: + ssi1_pdf = (pcdr0 & CCM_PCDR0_SSI2BAUDDIV_MASK) >> + CCM_PCDR0_SSI2BAUDDIV_OFFSET; + clk_src = (cscr & CCM_CSCR_SSI2) >> CCM_CSCR_SSI2_OFFSET; + if (clk_src) + ret_val = pll / (ssi2_pdf + 1); + else + ret_val = spll / (ssi2_pdf + 1); + break; + case NFC_CLK: + nfc_pdf = (pcdr0 & CCM_PCDR0_NFCDIV_MASK) >> + CCM_PCDR0_NFCDIV_OFFSET; + ret_val = hclk / (nfc_pdf + 1); + break; + default: + ret_val = ipgclk; + break; + } + return ret_val; +} + +/*! + * This function returns the parent clock values in Hz. + * + * @param clk as defined in enum mxc_clocks + * + * @return clock value in Hz + */ +unsigned long mxc_get_clocks_parent(enum mxc_clocks clk) +{ + unsigned long ret_val = 0; + + switch (clk) { + case CSI_BAUD: + ret_val = mxc_mcu_main_clock(); + break; + default: + break; + } + return ret_val; +} + +/*! + * This function sets the PLL source for a clock. + * + * @param clk as defined in enum mxc_clocks + * @param pll_num the PLL that you wish to use as source for this clock + */ +void mxc_set_clocks_pll(enum mxc_clocks clk, enum plls pll_num) +{ + volatile unsigned long cscr; + unsigned long flags; + + spin_lock_irqsave(&mxc_crm_lock, flags); + cscr = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR); + + switch (clk) { + case SSI1_BAUD: + cscr = (cscr & (~CCM_CSCR_SSI1)) | + (pll_num << CCM_CSCR_SSI1_OFFSET); + break; + case SSI2_BAUD: + cscr = (cscr & (~CCM_CSCR_SSI2)) | + (pll_num << CCM_CSCR_SSI2_OFFSET); + break; + default: + pr_info("Can't choose its clock source: %d\n", clk); + break; + } + __raw_writel(cscr, IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR); + spin_unlock_irqrestore(&mxc_crm_lock, flags); + return; +} + +/*! + * This function sets the divider value for a clock. + * + * @param clk as defined in enum mxc_clocks + * @param div the division factor to be used for the clock (For SSI & CSI, pass + * in 2 times the expected division value to account for FP vals on certain + * platforms) + */ +void mxc_set_clocks_div(enum mxc_clocks clk, unsigned int div) +{ + volatile unsigned long reg; + unsigned long flags; + + spin_lock_irqsave(&mxc_crm_lock, flags); + + switch (clk) { + case SSI2_BAUD: + reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR0); + reg = (reg & (~CCM_PCDR0_SSI2BAUDDIV_MASK)) | + ((div - 1) << CCM_PCDR0_SSI2BAUDDIV_OFFSET); + __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR0); + break; + case SSI1_BAUD: + reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR0); + reg = (reg & (~CCM_PCDR0_SSI1BAUDDIV_MASK)) | + ((div - 1) << CCM_PCDR0_SSI1BAUDDIV_OFFSET); + __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR0); + break; + case NFC_CLK: + reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR0); + reg = (reg & (~CCM_PCDR0_NFCDIV_MASK)) | + ((div - 1) << CCM_PCDR0_NFCDIV_OFFSET); + __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR0); + break; + case PERCLK1: + case UART4_BAUD: + case UART3_BAUD: + case UART2_BAUD: + case UART1_BAUD: + case GPT3_CLK: + case GPT2_CLK: + case GPT1_CLK: + case PWM_CLK: + reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR1); + reg = (reg & (~CCM_PCDR1_PERDIV1_MASK)) | + ((div - 1) << CCM_PCDR1_PERDIV1_OFFSET); + __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR1); + break; + case PERCLK2: + case SDHC2_CLK: + case SDHC1_CLK: + case CSPI3_CLK: + case CSPI2_CLK: + case CSPI1_CLK: + reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR1); + reg = (reg & (~CCM_PCDR1_PERDIV2_MASK)) | + ((div - 1) << CCM_PCDR1_PERDIV2_OFFSET); + __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR1); + break; + case PERCLK3: + case LCDC_CLK: + reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR1); + reg = (reg & (~CCM_PCDR1_PERDIV3_MASK)) | + ((div - 1) << CCM_PCDR1_PERDIV3_OFFSET); + __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR1); + break; + case PERCLK4: + case CSI_BAUD: + reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR1); + reg = (reg & (~CCM_PCDR1_PERDIV4_MASK)) | + ((div - 1) << CCM_PCDR1_PERDIV4_OFFSET); + __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR1); + break; + case USB_CLK: + reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR); + reg = (reg & (~CCM_CSCR_USB_MASK)) | + ((div - 1) << CCM_CSCR_USB_OFFSET); + __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR); + break; + case IPG_CLK: + reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR); + reg = (reg & (~CCM_CSCR_IPDIV)) | + ((div - 1) << CCM_CSCR_IPDIV_OFFSET); + __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR); + break; + case CPU_CLK: + reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR); + reg = (reg & (~CCM_CSCR_PRESC_MASK)) | + ((div - 1) << CCM_CSCR_PRESC_OFFSET); + __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR); + break; + case AHB_CLK: + reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR); + reg = (reg & (~CCM_CSCR_BCLK_MASK)) | + ((div - 1) << CCM_CSCR_BCLK_OFFSET); + __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR); + break; + default: + break; + } + + spin_unlock_irqrestore(&mxc_crm_lock, flags); +} + +static void __mxc_clks_config(enum mxc_clocks clk, int enable) +{ + unsigned long flags, reg_up = 0; + volatile unsigned long reg0, reg1; + + spin_lock_irqsave(&mxc_crm_lock, flags); + + reg0 = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR0); + reg1 = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR1); + + switch (clk) { + case CSI_BAUD: + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_PERCLK4_OFFSET, enable); + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_HCLK_CSI_OFFSET, enable); + break; + case DMA_CLK: + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_DMA_OFFSET, enable); + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_HCLK_DMA_OFFSET, enable); + break; + case BROM_CLK: + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_HCLK_BROM_OFFSET, enable); + break; + case EMMA_PRP_CLK: + __enable_emma_clk(MXC_CLK_EMMA_PRP); + goto clk_cfg_out; + break; + case EMMA_PP_CLK: + __enable_emma_clk(MXC_CLK_EMMA_PP); + goto clk_cfg_out; + break; + case LCDC_CLK: + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_HCLK_LCDC_OFFSET, enable); + break; + case SLCDC_CLK: + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_SLCDC_OFFSET, enable); + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_HCLK_SLCDC_OFFSET, enable); + break; + case USB_CLK: + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_HCLK_USBOTG_OFFSET, enable); + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_USBOTG_OFFSET, enable); + break; + case SSI1_BAUD: + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_SSI1_BAUD_OFFSET, enable); + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_SSI1_OFFSET, enable); + break; + case SSI2_BAUD: + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_SSI2_BAUD_OFFSET, enable); + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_SSI2_OFFSET, enable); + break; + case NFC_CLK: + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_NFC_OFFSET, enable); + break; + case UART1_BAUD: + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_UART1_OFFSET, enable); + break; + case UART2_BAUD: + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_UART2_OFFSET, enable); + break; + case UART3_BAUD: + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_UART3_OFFSET, enable); + break; + case UART4_BAUD: + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_UART4_OFFSET, enable); + break; + case WDOG_CLK: + MXC_REG_BIT_MOD(reg1, CCM_PCCR1_WDT_OFFSET, enable); + reg_up = 1; + break; + case CSPI3_CLK: + MXC_REG_BIT_MOD(reg1, CCM_PCCR1_CSPI3_OFFSET, enable); + break; + case CSPI2_CLK: + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_CSPI2_OFFSET, enable); + break; + case CSPI1_CLK: + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_CSPI1_OFFSET, enable); + break; + case GPIO_CLK: + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_GPIO_OFFSET, enable); + break; + case GPT3_CLK: + MXC_REG_BIT_MOD(reg1, CCM_PCCR1_GPT3_OFFSET, enable); + reg_up = 1; + break; + case GPT2_CLK: + MXC_REG_BIT_MOD(reg1, CCM_PCCR1_GPT2_OFFSET, enable); + reg_up = 1; + break; + case GPT1_CLK: + MXC_REG_BIT_MOD(reg1, CCM_PCCR1_GPT1_OFFSET, enable); + reg_up = 1; + break; + case I2C1_CLK: + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_I2C_OFFSET, enable); + break; + case KPP_CLK: + MXC_REG_BIT_MOD(reg1, CCM_PCCR1_KPP_OFFSET, enable); + reg_up = 1; + break; + case OWIRE_CLK: + MXC_REG_BIT_MOD(reg1, CCM_PCCR1_OWIRE_OFFSET, enable); + reg_up = 1; + break; + case PWM_CLK: + MXC_REG_BIT_MOD(reg1, CCM_PCCR1_PWM_OFFSET, enable); + reg_up = 1; + break; + case RTC_CLK: + MXC_REG_BIT_MOD(reg1, CCM_PCCR1_RTC_OFFSET, enable); + reg_up = 1; + break; + case SDHC2_CLK: + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_SDHC2_OFFSET, enable); + break; + case SDHC1_CLK: + MXC_REG_BIT_MOD(reg0, CCM_PCCR0_SDHC1_OFFSET, enable); + break; + default: + goto clk_cfg_out; + } + if (reg_up == 0) { + __raw_writel(reg0, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR0); + } else if (reg_up == 1) { + __raw_writel(reg1, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR1); + } else { + __raw_writel(reg0, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR0); + __raw_writel(reg1, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCCR1); + } + + clk_cfg_out: + spin_unlock_irqrestore(&mxc_crm_lock, flags); +} + +/*! + * This function is called to enable the individual module clocks + * + * @param clk as defined in enum mxc_clocks + */ + +void mxc_clks_enable(enum mxc_clocks clk) +{ + __mxc_clks_config(clk, 1); +} + +/*! + * This function is called to disable the individual module clocks + * + * @param clk as defined in enum mxc_clocks + */ +void mxc_clks_disable(enum mxc_clocks clk) +{ + __mxc_clks_config(clk, 0); +} + +/*! + * This function is used to modify PLL registers to generate the required + * frequency. + * + * @param pll_num the PLL that you wish to modify + * @param mfi multiplication factor integer part + * @param pdf pre-division factor + * @param mfd multiplication factor denominator + * @param mfn multiplication factor numerator + */ +void mxc_pll_set(enum plls pll_num, unsigned int mfi, unsigned int pdf, + unsigned int mfd, unsigned int mfn) +{ + volatile unsigned long cscr; + unsigned long flags; + unsigned long new_pll = 0; + + spin_lock_irqsave(&mxc_crm_lock, flags); + + if (pll_num == MCUPLL) { + /* Change the Pll value */ + new_pll = (mfi << CCM_MPCTL0_MFI_OFFSET) | + (mfn << CCM_MPCTL0_MFN_OFFSET) | + (mfd << CCM_MPCTL0_MFD_OFFSET) | + (pdf << CCM_MPCTL0_PD_OFFSET); + + __raw_writel(new_pll, IO_ADDRESS(CCM_BASE_ADDR) + CCM_MPCTL0); + /* Swap to reference clock and disable PLL */ + cscr = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR); + cscr |= CCM_CSCR_MPLLRES; + __raw_writel(cscr, IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR); + } else { + if (pll_num == SERIALPLL) { + /* Change the Pll value */ + new_pll = (mfi << CCM_SPCTL0_MFI_OFFSET) | + (mfn << CCM_SPCTL0_MFN_OFFSET) | + (mfd << CCM_SPCTL0_MFD_OFFSET) | + (pdf << CCM_SPCTL0_PD_OFFSET); + + __raw_writel(new_pll, + IO_ADDRESS(CCM_BASE_ADDR) + CCM_SPCTL0); + /* Swap to reference clock and disable PLL */ + cscr = + __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR); + cscr |= CCM_CSCR_SPLLRES; + __raw_writel(cscr, + IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR); + } + } + + spin_unlock_irqrestore(&mxc_crm_lock, flags); +} + +/*! + * Configure clock output on CKO pins + * + * @param output clock output pin + * @param clk clock source to output + * @param div CLKO divider + * + */ +void mxc_set_clock_output(enum mxc_clk_out output, enum mxc_clocks clk, int div) +{ + unsigned long flags; + volatile unsigned long reg; + + if (output != CKO) { + return; + } + + spin_lock_irqsave(&mxc_crm_lock, flags); + + switch (clk) { + case CKIH_CLK: + reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CCSR); + reg = (reg & (~0x1f)) | 0x2; + __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_CCSR); + + reg = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR0); + reg = (reg & (~0x03c00000)) | 0x02000000 | ((div - 1) << 22); + __raw_writel(reg, IO_ADDRESS(CCM_BASE_ADDR) + CCM_PCDR0); + + break; + default: + break; + }; + + spin_unlock_irqrestore(&mxc_crm_lock, flags); + return; +} + +EXPORT_SYMBOL(mxc_pll_set); +EXPORT_SYMBOL(mxc_pll_clock); +EXPORT_SYMBOL(mxc_get_clocks); +EXPORT_SYMBOL(mxc_set_clocks_pll); +EXPORT_SYMBOL(mxc_set_clocks_div); +EXPORT_SYMBOL(mxc_clks_disable); +EXPORT_SYMBOL(mxc_clks_enable); +EXPORT_SYMBOL(mxc_set_clock_output); +EXPORT_SYMBOL(mxc_get_clocks_parent); diff -urN linux-2.6.26/arch/arm/mach-mx21/crm_regs.h linux-2.6.26-lab126/arch/arm/mach-mx21/crm_regs.h --- linux-2.6.26/arch/arm/mach-mx21/crm_regs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx21/crm_regs.h 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,163 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ARCH_ARM_MACH_MX21_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MX21_CRM_REGS_H__ + +#include + +/* Register offsets */ +#define CCM_CSCR 0x0 +#define CCM_MPCTL0 0x4 +#define CCM_MPCTL1 0x8 +#define CCM_SPCTL0 0xC +#define CCM_SPCTL1 0x10 +#define CCM_OSC26MCTL 0x14 +#define CCM_PCDR0 0x18 +#define CCM_PCDR1 0x1C +#define CCM_PCCR0 0x20 +#define CCM_PCCR1 0x24 +#define CCM_CCSR 0x28 +#define CCM_PMCTL 0x2C +#define CCM_PMCOUNT 0x30 +#define CCM_WKGDCTL 0x34 + +#define CCM_CSCR_PRESC_OFFSET 29 +#define CCM_CSCR_PRESC_MASK (0x7 << 29) +#define CCM_CSCR_USB_OFFSET 26 +#define CCM_CSCR_USB_MASK (0x7 << 26) +#define CCM_CSCR_SD_OFFSET 24 +#define CCM_CSCR_SD_MASK (0x3 << 24) +#define CCM_CSCR_SPLLRES (1 << 22) +#define CCM_CSCR_MPLLRES (1 << 21) +#define CCM_CSCR_SSI2 (1 << 20) +#define CCM_CSCR_SSI2_OFFSET 20 +#define CCM_CSCR_SSI1 (1 << 19) +#define CCM_CSCR_SSI1_OFFSET 19 +#define CCM_CSCR_SP (1 << 17) +#define CCM_CSCR_MCU (1 << 16) +#define CCM_CSCR_BCLK_OFFSET 10 +#define CCM_CSCR_BCLK_MASK (0xF << 10) +#define CCM_CSCR_IPDIV_OFFSET 9 +#define CCM_CSCR_IPDIV (1 << 9) +#define CCM_CSCR_OSC26MDIV (1 << 4) +#define CCM_CSCR_OSC26M (1 << 3) +#define CCM_CSCR_FPM (1 << 2) +#define CCM_CSCR_SPEN (1 << 1) +#define CCM_CSCR_MPEN (1 << 0) + +#define CCM_MPCTL0_CPLM (1 << 31) +#define CCM_MPCTL0_PD_OFFSET 26 +#define CCM_MPCTL0_PD_MASK (0xF << 26) +#define CCM_MPCTL0_MFD_OFFSET 16 +#define CCM_MPCTL0_MFD_MASK (0x3FF << 16) +#define CCM_MPCTL0_MFI_OFFSET 10 +#define CCM_MPCTL0_MFI_MASK (0xF << 10) +#define CCM_MPCTL0_MFN_OFFSET 0 +#define CCM_MPCTL0_MFN_MASK 0x3FF + +#define CCM_MPCTL1_LF (1 << 15) +#define CCM_MPCTL1_BRMO (1 << 6) + +#define CCM_SPCTL0_CPLM (1 << 31) +#define CCM_SPCTL0_PD_OFFSET 26 +#define CCM_SPCTL0_PD_MASK (0xF << 26) +#define CCM_SPCTL0_MFD_OFFSET 16 +#define CCM_SPCTL0_MFD_MASK (0x3FF << 16) +#define CCM_SPCTL0_MFI_OFFSET 10 +#define CCM_SPCTL0_MFI_MASK (0xF << 10) +#define CCM_SPCTL0_MFN_OFFSET 0 +#define CCM_SPCTL0_MFN_MASK 0x3FF + +#define CCM_SPCTL1_LF (1 << 15) +#define CCM_SPCTL1_BRMO (1 << 6) + +#define CCM_OSC26MCTL_PEAK_OFFSET 16 +#define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16) +#define CCM_OSC26MCTL_AGC_OFFSET 8 +#define CCM_OSC26MCTL_AGC_MASK (0x3F << 8) + +#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26 +#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3F << 26) +#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16 +#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3F << 16) +#define CCM_PCDR0_NFCDIV_OFFSET 12 +#define CCM_PCDR0_NFCDIV_MASK (0xF << 12) +#define CCM_PCDR0_CLKO48MDIV_OFFSET 5 +#define CCM_PCDR0_CLKO48MDIV_MASK (0x7 << 5) +#define CCM_PCDR0_FIRIDIV_OFFSET 0 +#define CCM_PCDR0_FIRIDIV_MASK 0x1F + +#define CCM_PCDR1_PERDIV4_OFFSET 24 +#define CCM_PCDR1_PERDIV4_MASK (0x3F << 24) +#define CCM_PCDR1_PERDIV3_OFFSET 16 +#define CCM_PCDR1_PERDIV3_MASK (0x3F << 16) +#define CCM_PCDR1_PERDIV2_OFFSET 8 +#define CCM_PCDR1_PERDIV2_MASK (0x3F << 8) +#define CCM_PCDR1_PERDIV1_OFFSET 0 +#define CCM_PCDR1_PERDIV1_MASK 0x3F + +#define CCM_PCCR0_HCLK_CSI_OFFSET 31 +#define CCM_PCCR0_HCLK_DMA_OFFSET 30 +#define CCM_PCCR0_HCLK_BROM_OFFSET 28 +#define CCM_PCCR0_HCLK_EMMA_OFFSET 27 +#define CCM_PCCR0_HCLK_LCDC_OFFSET 26 +#define CCM_PCCR0_HCLK_SLCDC_OFFSET 25 +#define CCM_PCCR0_HCLK_USBOTG_OFFSET 24 +#define CCM_PCCR0_HCLK_BMI_OFFSET 23 +#define CCM_PCCR0_PERCLK4_OFFSET 22 +#define CCM_PCCR0_SLCDC_OFFSET 21 +#define CCM_PCCR0_FIRI_BAUD_OFFSET 20 +#define CCM_PCCR0_NFC_OFFSET 19 +#define CCM_PCCR0_PERCLK3_OFFSET 18 +#define CCM_PCCR0_SSI1_BAUD_OFFSET 17 +#define CCM_PCCR0_SSI2_BAUD_OFFSET 16 +#define CCM_PCCR0_EMMA_OFFSET 15 +#define CCM_PCCR0_USBOTG_OFFSET 14 +#define CCM_PCCR0_DMA_OFFSET 13 +#define CCM_PCCR0_I2C_OFFSET 12 +#define CCM_PCCR0_GPIO_OFFSET 11 +#define CCM_PCCR0_SDHC2_OFFSET 10 +#define CCM_PCCR0_SDHC1_OFFSET 9 +#define CCM_PCCR0_FIRI_OFFSET 8 +#define CCM_PCCR0_SSI2_OFFSET 7 +#define CCM_PCCR0_SSI1_OFFSET 6 +#define CCM_PCCR0_CSPI2_OFFSET 5 +#define CCM_PCCR0_CSPI1_OFFSET 4 +#define CCM_PCCR0_UART4_OFFSET 3 +#define CCM_PCCR0_UART3_OFFSET 2 +#define CCM_PCCR0_UART2_OFFSET 1 +#define CCM_PCCR0_UART1_OFFSET 0 + +#define CCM_PCCR1_OWIRE_OFFSET 31 +#define CCM_PCCR1_KPP_OFFSET 30 +#define CCM_PCCR1_RTC_OFFSET 29 +#define CCM_PCCR1_PWM_OFFSET 28 +#define CCM_PCCR1_GPT3_OFFSET 27 +#define CCM_PCCR1_GPT2_OFFSET 26 +#define CCM_PCCR1_GPT1_OFFSET 25 +#define CCM_PCCR1_WDT_OFFSET 24 +#define CCM_PCCR1_CSPI3_OFFSET 23 +#define CCM_PCCR1_RTIC_OFFSET 22 +#define CCM_PCCR1_RNGA_OFFSET 21 + +#define CCM_CCSR_32KSR (1 << 15) +#define CCM_CCSR_CLKOSEL_OFFSET 0 +#define CCM_CCSR_CLKOSEL_MASK 0x1f + +#define CKIH_CLK_FREQ 26000000 /* 26M reference clk */ +#define CKIL_CLK_FREQ (32768 * 512) /* 32.768k oscillator in */ + +#define SYS_FMCR 0x8 /* Functional Muxing Control Reg */ + +#endif /* __ARCH_ARM_MACH_MX21_CRM_REGS_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx21/devices.c linux-2.6.26-lab126/arch/arm/mach-mx21/devices.c --- linux-2.6.26/arch/arm/mach-mx21/devices.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx21/devices.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,278 @@ +/* + * Author: MontaVista Software, Inc. + * + * + * Based on the OMAP devices.c + * + * 2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ +#include +#include +#include +#include + +#include +#include +#include + + /*! + * @file devices.c + * @brief device configurations including nor/nand/watchdog for mx27. + * + * @ingroup MSL + */ + +/* FIXME: SDHC is not supported yet! */ + +static void mxc_nop_release(struct device *dev) +{ + /* Nothing */ +} + +#if defined(CONFIG_MXC_WATCHDOG) || defined(CONFIG_MXC_WATCHDOG_MODULE) + +static struct resource wdt_resources[] = { + { + .start = WDOG_BASE_ADDR, + .end = WDOG_BASE_ADDR + 0x30, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mxc_wdt_device = { + .name = "mxc_wdt", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(wdt_resources), + .resource = wdt_resources, +}; + +static void mxc_init_wdt(void) +{ + mxc_clks_enable(WDOG_CLK); + (void)platform_device_register(&mxc_wdt_device); +} +#else +static inline void mxc_init_wdt(void) +{ +} +#endif + +/* MMC device data */ + +#if defined(CONFIG_MMC_MXC) || defined(CONFIG_MMC_MXC_MODULE) + +extern unsigned int sdhc_get_card_det_status(struct device *dev); +extern int sdhc_init_card_det(int id); + +static struct mxc_mmc_platform_data mmc_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30, + .min_clk = 150000, + .max_clk = 25000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, +}; + +/*! + * Resource definition for the SDHC1 + */ +static struct resource mxcsdhc1_resources[] = { + [0] = { + .start = SDHC1_BASE_ADDR, + .end = SDHC1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_SDHC1, + .end = INT_SDHC1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = MXC_SDIO1_CARD_IRQ, + .end = MXC_SDIO1_CARD_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! + * Resource definition for the SDHC2 + */ +static struct resource mxcsdhc2_resources[] = { + [0] = { + .start = SDHC2_BASE_ADDR, + .end = SDHC2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_SDHC2, + .end = INT_SDHC2, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = MXC_SDIO2_CARD_IRQ, + .end = MXC_SDIO2_CARD_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Device Definition for MXC SDHC1 */ +static struct platform_device mxcsdhc1_device = { + .name = "mxcmci", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc_data, + }, + .num_resources = ARRAY_SIZE(mxcsdhc1_resources), + .resource = mxcsdhc1_resources, +}; + +/*! Device Definition for MXC SDHC2 */ +static struct platform_device mxcsdhc2_device = { + .name = "mxcmci", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc_data, + }, + .num_resources = ARRAY_SIZE(mxcsdhc2_resources), + .resource = mxcsdhc2_resources, +}; + +static inline void mxc_init_mmc(void) +{ + int cd_irq; + + /*cd_irq = sdhc_init_card_det(0); + if (cd_irq) { + mxcsdhc1_device.resource[2].start = cd_irq; + mxcsdhc1_device.resource[2].end = cd_irq; + } */ + cd_irq = sdhc_init_card_det(1); + if (cd_irq) { + mxcsdhc2_device.resource[2].start = cd_irq; + mxcsdhc2_device.resource[2].end = cd_irq; + } + + /*(void)platform_device_register(&mxcsdhc1_device); */ + (void)platform_device_register(&mxcsdhc2_device); +} +#else +static inline void mxc_init_mmc(void) +{ +} +#endif + +/* I2C controller and device data */ +#if defined(CONFIG_I2C_MXC) || defined(CONFIG_I2C_MXC_MODULE) + +/*! + * Resource definition for the I2C1 + */ +static struct resource mxci2c1_resources[] = { + [0] = { + .start = I2C_BASE_ADDR, + .end = I2C_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_I2C, + .end = INT_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC I2C */ +static struct mxc_i2c_platform_data mxci2c1_data = { + .clk = I2C_CLK, + .i2c_clk = 100000, +}; + +/*! Device Definition for MXC I2C1 */ +static struct platform_device mxci2c1_device = { + .name = "mxc_i2c", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxci2c1_data, + }, + .num_resources = ARRAY_SIZE(mxci2c1_resources), + .resource = mxci2c1_resources, +}; + +static inline void mxc_init_i2c(void) +{ + if (platform_device_register(&mxci2c1_device) < 0) + dev_err(&mxci2c1_device.dev, "Unable to register I2C device\n"); +} +#else +static inline void mxc_init_i2c(void) +{ +} +#endif + +struct mxc_gpio_port mxc_gpio_ports[GPIO_PORT_NUM] = { + { + .num = 0, + .base = IO_ADDRESS(GPIO_BASE_ADDR), + .irq = INT_GPIO, + .virtual_irq_start = MXC_GPIO_BASE, + }, + { + .num = 1, + .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x100, + .irq = INT_GPIO, + .virtual_irq_start = MXC_GPIO_BASE + GPIO_NUM_PIN, + }, + { + .num = 2, + .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x200, + .irq = INT_GPIO, + .virtual_irq_start = MXC_GPIO_BASE + GPIO_NUM_PIN * 2, + }, + { + .num = 3, + .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x300, + .irq = INT_GPIO, + .virtual_irq_start = MXC_GPIO_BASE + GPIO_NUM_PIN * 3, + }, + { + .num = 4, + .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x400, + .irq = INT_GPIO, + .virtual_irq_start = MXC_GPIO_BASE + GPIO_NUM_PIN * 4, + }, + { + .num = 5, + .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x500, + .irq = INT_GPIO, + .virtual_irq_start = MXC_GPIO_BASE + GPIO_NUM_PIN * 5, + }, +}; + +static int __init mxc_init_devices(void) +{ + mxc_init_wdt(); + mxc_init_mmc(); + mxc_init_i2c(); + return 0; +} + +arch_initcall(mxc_init_devices); diff -urN linux-2.6.26/arch/arm/mach-mx21/dma.c linux-2.6.26-lab126/arch/arm/mach-mx21/dma.c --- linux-2.6.26/arch/arm/mach-mx21/dma.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx21/dma.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,491 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + *@file dma_data.c + *@brief This file contains the private definition . + * @ingroup DMA + */ + +#include +#include +#include + +/*! + * @brief the structure stored device_id and dma_info pointer + */ +typedef struct dma_info_entry_s { + mxc_dma_device_t device; + /* if there are two dma_info , first is for reading, another is for writing */ + mx2_dma_info_t *info[2]; +} dma_info_entry_t; + +/*! + * @brief dma_info from memory to memory for dma testing + */ +static mx2_dma_info_t ram2ram_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 0, + .burstLength = 4,.request = 0,.busuntils = 0, + .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_32BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT, + .M2D_Valid = 0 +}; + +/*! + * @brief dma_info from 2D memory to 2D memory for dma testing + */ +static mx2_dma_info_t ram2d2ram2d_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .rto_en = 0, + .AcRpt = 0,.repeat = 0,.ren = 0, + .burstLength = 4,.request = 0,.busuntils = 0, + .sourceType = DMA_TYPE_2D,.sourcePort = TRANSFER_32BIT, + .destType = DMA_TYPE_2D,.destPort = TRANSFER_32BIT, + .M2D_Valid = 1,.msel = 0,.W = 0x80,.X = 0x40,.Y = 0x10 +}; + +/*! + * @brief dma_info from memory to 2D memory for dma testing + */ +static mx2_dma_info_t ram2ram2d_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 0, + .burstLength = 4,.request = 0,.busuntils = 0, + .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_32BIT, + .destType = DMA_TYPE_2D,.destPort = TRANSFER_32BIT, + .M2D_Valid = 1,.msel = 0,.W = 0x100,.X = 0x80,.Y = 0x10 +}; + +/*! + * @brief dma_info from 2D memory to memory for dma testing + */ +static mx2_dma_info_t ram2d2ram_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 0, + .burstLength = 4,.request = 0,.busuntils = 0, + .sourceType = DMA_TYPE_2D,.sourcePort = TRANSFER_32BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT, + .M2D_Valid = 1,.msel = 0,.W = 0x100,.X = 0x100,.Y = 0x10 +}; + +/*! + * @brief dma_info with dma chaining feature for dma testing + */ +static mx2_dma_info_t hw_chaining_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 1,.repeat = 1,.ren = 0, + .burstLength = 4,.request = 0,.busuntils = 0, + .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_32BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT, + .M2D_Valid = 0, +}; + +/*! + * @brief dma_info without dma chaining feature for dma testing + */ +static mx2_dma_info_t sw_chaining_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 0, + .burstLength = 4,.request = 0,.busuntils = 0, + .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_32BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT, + .M2D_Valid = 0, +}; + +/*! + * @brief dma_info for UART1 recieveing + */ +static mx2_dma_info_t uart1_rx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 1, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 1,.request = 26,.busuntils = 8, + .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT, + .per_address = (UART1_BASE_ADDR), + .M2D_Valid = 0, +}; + +/*! + * @brief: dma_info for UART1 transmitting + */ +static mx2_dma_info_t uart1_tx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 1,.request = 27,.busuntils = 0, + .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_FIFO,.destPort = TRANSFER_8BIT, + .per_address = (UART1_BASE_ADDR + 0x40), + .M2D_Valid = 0, +}; + +/*! + * @brief dma_info for UART2 recieveing + */ +static mx2_dma_info_t uart2_rx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 1,.request = 24,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT, + .per_address = (UART2_BASE_ADDR), + .M2D_Valid = 0, +}; + +/*! + * @brief: dma_info for UART2 transmitting + */ +static mx2_dma_info_t uart2_tx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 1,.request = 25,.busuntils = 0, + .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_FIFO,.destPort = TRANSFER_8BIT, + .per_address = (UART2_BASE_ADDR + 0x40), + .M2D_Valid = 0, +}; + +/*! + * @brief dma_info for UART3 recieveing + */ +static mx2_dma_info_t uart3_rx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 1,.request = 22,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT, + .per_address = (UART3_BASE_ADDR), + .M2D_Valid = 0, +}; + +/*! + * @brief: dma_info for UART3 transmitting + */ +static mx2_dma_info_t uart3_tx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 1,.request = 23,.busuntils = 0, + .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_FIFO,.destPort = TRANSFER_8BIT, + .per_address = (UART3_BASE_ADDR + 0x40), + .M2D_Valid = 0, +}; + +/*! + * @brief dma_info for UART4 recieveing + */ +static mx2_dma_info_t uart4_rx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 1,.request = 20,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT, + .per_address = (UART4_BASE_ADDR), + .M2D_Valid = 0, +}; + +/*! + * @brief: dma_info for UART4transmitting + */ +static mx2_dma_info_t uart4_tx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 1,.request = 21,.busuntils = 0, + .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_FIFO,.destPort = TRANSFER_8BIT, + .per_address = (UART4_BASE_ADDR + 0x40), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t ssi1_16bit_rx0_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 8,.request = DMA_REQ_SSI1_RX0,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_16, + .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32, + .per_address = (SSI1_BASE_ADDR + 0x08), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t ssi1_16bit_tx0_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 8,.request = DMA_REQ_SSI1_TX0,.busuntils = 0, + .sourceType = DMA_TYPE_LINEAR,.sourcePort = DMA_MEM_SIZE_32, + .destType = DMA_TYPE_FIFO,.destPort = DMA_MEM_SIZE_16, + .per_address = (SSI1_BASE_ADDR), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t ssi2_16bit_rx0_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 8,.request = DMA_REQ_SSI2_RX0,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_16, + .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32, + .per_address = (SSI2_BASE_ADDR + 0x08), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t ssi2_16bit_tx0_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 8,.request = DMA_REQ_SSI2_TX0,.busuntils = 0, + .sourceType = DMA_TYPE_LINEAR,.sourcePort = DMA_MEM_SIZE_32, + .destType = DMA_TYPE_FIFO,.destPort = DMA_MEM_SIZE_16, + .per_address = (SSI2_BASE_ADDR), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t mmc1_width1_dma_rx_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 16,.request = DMA_REQ_SDHC1,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_32, + .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32, + .per_address = (SDHC1_BASE_ADDR + 0x38), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t mmc1_width1_dma_tx_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 16,.request = DMA_REQ_SDHC1,.busuntils = 0, + .sourceType = DMA_TYPE_LINEAR,.sourcePort = DMA_MEM_SIZE_32, + .destType = DMA_TYPE_FIFO,.destPort = DMA_MEM_SIZE_32, + .per_address = (SDHC1_BASE_ADDR + 0x38), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t mmc1_width4_dma_rx_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 0,.request = DMA_REQ_SDHC1,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_32, + .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32, + .per_address = (SDHC1_BASE_ADDR + 0x38), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t mmc1_width4_dma_tx_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 0,.request = DMA_REQ_SDHC1,.busuntils = 0, + .sourceType = DMA_TYPE_LINEAR,.sourcePort = DMA_MEM_SIZE_32, + .destType = DMA_TYPE_FIFO,.destPort = DMA_MEM_SIZE_32, + .per_address = (SDHC1_BASE_ADDR + 0x38), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t mmc2_width1_dma_rx_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 16,.request = DMA_REQ_SDHC2,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_32, + .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32, + .per_address = (SDHC2_BASE_ADDR + 0x38), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t mmc2_width1_dma_tx_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 16,.request = DMA_REQ_SDHC2,.busuntils = 0, + .sourceType = DMA_TYPE_LINEAR,.sourcePort = DMA_MEM_SIZE_32, + .destType = DMA_TYPE_FIFO,.destPort = DMA_MEM_SIZE_32, + .per_address = (SDHC2_BASE_ADDR + 0x38), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t mmc2_width4_dma_rx_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 0,.request = DMA_REQ_SDHC2,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_32, + .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32, + .per_address = (SDHC2_BASE_ADDR + 0x38), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t mmc2_width4_dma_tx_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .cb_end = 1, + .rto_en = 0, + .dir = 0, + .AcRpt = 0,.repeat = 0,.ren = 1, + .burstLength = 0,.request = DMA_REQ_SDHC2,.busuntils = 0, + .sourceType = DMA_TYPE_LINEAR,.sourcePort = DMA_MEM_SIZE_32, + .destType = DMA_TYPE_FIFO,.destPort = DMA_MEM_SIZE_32, + .per_address = (SDHC2_BASE_ADDR + 0x38), + .M2D_Valid = 0, +}; + +/*! + * @brief dma info array which is actived + * DEVICE_ID RX/(RX&TX) TX + */ +static dma_info_entry_t active_dma_info[] = { + {MXC_DMA_TEST_RAM2RAM, {&ram2ram_dma_info, NULL}}, + {MXC_DMA_TEST_RAM2D2RAM2D, {&ram2d2ram2d_dma_info, NULL}}, + {MXC_DMA_TEST_RAM2RAM2D, {&ram2ram2d_dma_info, NULL}}, + {MXC_DMA_TEST_RAM2D2RAM, {&ram2d2ram_dma_info, NULL}}, + {MXC_DMA_TEST_HW_CHAINING, {&hw_chaining_dma_info, NULL}}, + {MXC_DMA_TEST_SW_CHAINING, {&sw_chaining_dma_info, NULL}}, + {MXC_DMA_UART1_RX, {&uart1_rx_dma_info, NULL}}, + {MXC_DMA_UART1_TX, {NULL, &uart1_tx_dma_info}}, + {MXC_DMA_UART2_RX, {&uart2_rx_dma_info, NULL}}, + {MXC_DMA_UART2_TX, {NULL, &uart2_tx_dma_info}}, + {MXC_DMA_UART3_RX, {&uart3_rx_dma_info, NULL}}, + {MXC_DMA_UART3_TX, {NULL, &uart3_tx_dma_info}}, + {MXC_DMA_UART4_RX, {&uart4_rx_dma_info, NULL}}, + {MXC_DMA_UART4_TX, {NULL, &uart4_tx_dma_info}}, + {MXC_DMA_SSI1_16BIT_RX0, {&ssi1_16bit_rx0_dma_info, NULL}}, + {MXC_DMA_SSI1_16BIT_TX0, {NULL, &ssi1_16bit_tx0_dma_info}}, + {MXC_DMA_SSI2_16BIT_RX0, {&ssi2_16bit_rx0_dma_info, NULL}}, + {MXC_DMA_SSI2_16BIT_TX0, {NULL, &ssi2_16bit_tx0_dma_info}}, + {MXC_DMA_MMC1_WIDTH_1, + {&mmc1_width1_dma_rx_info, &mmc1_width1_dma_tx_info}}, + {MXC_DMA_MMC1_WIDTH_4, + {&mmc1_width4_dma_rx_info, &mmc1_width4_dma_tx_info}}, + {MXC_DMA_MMC2_WIDTH_1, + {&mmc2_width1_dma_rx_info, &mmc2_width1_dma_tx_info}}, + {MXC_DMA_MMC2_WIDTH_4, + {&mmc2_width4_dma_rx_info, &mmc2_width4_dma_tx_info}}, +}; + +/*! + * @brief the number of actived dma info + */ +static int dma_info_entrys = + sizeof(active_dma_info) / sizeof(active_dma_info[0]); + +/*! + * @brief get the dma info by channel_id + */ +mx2_dma_info_t **mxc_dma_get_info(mxc_dma_device_t channel_id) +{ + dma_info_entry_t *p = active_dma_info; + int i; + for (i = 0; i < dma_info_entrys; i++, p++) { + if (p->device == channel_id) + return p->info; + } + return NULL; +} + +/*! + * @brief: scan dma parameter list . And collect information about which channels are dynamic . + */ +void mxc_dma_load_info(mxc_dma_channel_t * dma) +{ + int i, idx; + dma_info_entry_t *p = active_dma_info; + + BUG_ON(dma == NULL); + BUG_ON(p == NULL); + + for (i = 0; i < MXC_DMA_CHANNELS; i++) { + dma[i].dynamic = 1; + } + + for (i = 0; i < dma_info_entrys; i++, p++) { + BUG_ON((p->info[0] == NULL) && (p->info[1] == NULL)); + + idx = + (p->info[0]) ? p->info[0]->dma_chan : p->info[1]->dma_chan; + + BUG_ON(((idx >= MAX_DMA_CHANNELS) + && (idx != MXC_DMA_DYNAMIC_CHANNEL))); + if ((idx < 0) || (idx == MXC_DMA_DYNAMIC_CHANNEL)) + continue; + dma[idx].dynamic = 0; + } +} + +EXPORT_SYMBOL(mxc_dma_get_info); +EXPORT_SYMBOL(mxc_dma_load_info); diff -urN linux-2.6.26/arch/arm/mach-mx21/gpio_mux.c linux-2.6.26-lab126/arch/arm/mach-mx21/gpio_mux.c --- linux-2.6.26/arch/arm/mach-mx21/gpio_mux.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx21/gpio_mux.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,302 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + *@file gpio_mux.c + *@brief This file contains the IOMUX implementation details. + * @ingroup GPIO + */ + +#include +#include +#include + +#include +#include +#include +#include "gpio_mux.h" + +/*! + * This structure defines the offset of registers in gpio module. + */ +enum gpio_reg { + GPIO_GIUS = 0x20, + GPIO_GPR = 0x38, + GPIO_PUEN = 0x40, + GPIO_DDIR = 0x00, + GPIO_OCR1 = 0x04, + GPIO_OCR2 = 0x08, + GPIO_ICONFA1 = 0x0C, + GPIO_ICONFA2 = 0x10, + GPIO_ICONFB1 = 0x14, + GPIO_ICONFB2 = 0x18, +}; + +/*! + * This enumeration data type defines the configuration for input mode. + */ +typedef enum { + GPIO_INPUT_GPIO = 0x00, + GPIO_INPUT_INTR = 0x01, + GPIO_INPUT_LOW = 0x02, + GPIO_INPUT_HIGH = 0x03 +} gpio_input_cfg_t; + +/*! + * This enumeration data type defines the configuration for output mode. + */ +typedef enum { + GPIO_OUTPUT_A = 0x00, + GPIO_OUTPUT_B = 0x01, + GPIO_OUTPUT_C = 0x02, + GPIO_OUTPUT_DR = 0x03 +} gpio_output_cfg_t; + +extern struct mxc_gpio_port mxc_gpio_ports[]; + +/*! + * defines a spinlock to protected the accessing to gpio pin. + */ +DEFINE_SPINLOCK(gpio_mux_lock); + +/*! + * This function enable or disable the pullup feature to the pin. + * @param port a pointer of gpio port + * @param index the index of the pin in the port + * @param en 0 if disable pullup, otherwise enable it. + * @return none + */ +static inline void _gpio_set_puen(struct mxc_gpio_port *port, u32 index, + bool en) +{ + u32 reg; + + reg = __raw_readl(port->base + GPIO_PUEN); + if (en) { + reg |= 1 << index; + } else { + reg &= ~(1 << index); + } + __raw_writel(reg, port->base + GPIO_PUEN); +} + +/*! + * This function set the input configuration A. + * @param port a pointer of gpio port + * @param index the index of the pin in the port + * @param config a mode as define in \b #gpio_input_cfg_t + * @return none + */ +static inline void _gpio_set_iconfa(struct mxc_gpio_port *port, u32 index, + gpio_input_cfg_t config) +{ + u32 reg, val; + u32 mask; + + mask = 0x3 << ((index % 16) << 1); + + if (index >= 16) { + reg = port->base + GPIO_ICONFA2; + val = config << ((index - 16) * 2); + } else { + reg = port->base + GPIO_ICONFA1; + val = config << (index * 2); + } + val |= __raw_readl(reg) & ~(mask); + __raw_writel(val, reg); +} + +/*! + * This function set the input configuration B. + * @param port a pointer of gpio port + * @param index the index of the pin in the port + * @param config a mode as define in \b #gpio_input_cfg_t + * @return none + */ +static inline void _gpio_set_iconfb(struct mxc_gpio_port *port, u32 index, + gpio_input_cfg_t config) +{ + u32 reg, val; + u32 mask; + + mask = 0x3 << ((index % 16) << 1); + + if (index >= 16) { + reg = port->base + GPIO_ICONFB2; + val = config << ((index - 16) * 2); + } else { + reg = port->base + GPIO_ICONFB1; + val = config << (index * 2); + } + val |= __raw_readl(reg) & (~mask); + __raw_writel(val, reg); +} + +/*! + * This function set the output configuration. + * @param port a pointer of gpio port + * @param index the index of the pin in the port + * @param config a mode as define in \b #gpio_output_cfg_t + * @return none + */ +static inline void _gpio_set_ocr(struct mxc_gpio_port *port, u32 index, + gpio_output_cfg_t config) +{ + u32 reg, val; + u32 mask; + + mask = 0x3 << ((index % 16) << 1); + if (index >= 16) { + reg = port->base + GPIO_OCR2; + val = config << ((index - 16) * 2); + } else { + reg = port->base + GPIO_OCR1; + val = config << (index * 2); + } + val |= __raw_readl(reg) & (~mask); + __raw_writel(val, reg); +} + +/*! + *@brief gpio_config_mux - just configure the mode of the gpio pin. + *@param pin a pin number as defined in \b #iomux_pin_name_t + *@param mode a module as define in \b #gpio_mux_mode_t; + * GPIO_MUX_PRIMARY set pin to work as primary function. + * GPIO_MUX_ALT set pin to work as alternate function. + * GPIO_MUX_GPIO set pin to work as output function based the data register + * GPIO_MUX_INPUT1 set pin to work as input function connected with A_OUT + * GPIO_MUX_INPUT2 set pin to work as input function connected with B_OUT + * GPIO_MUX_OUTPUT1 set pin to work as output function connected with A_IN + * GPIO_MUX_OUTPUT2 set pin to work as output function connected with B_IN + * GPIO_MUX_OUTPUT3 set pin to work as output function connected with C_IN + *@return 0 if successful, Non-zero otherwise + */ + +int gpio_config_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode) +{ + unsigned long lock_flags; + u32 gius_reg, gpr_reg; + struct mxc_gpio_port *port; + u32 index, gpio = IOMUX_TO_GPIO(pin); + + port = &(mxc_gpio_ports[GPIO_TO_PORT(gpio)]); + index = GPIO_TO_INDEX(gpio); + + pr_debug("%s: Configuring PORT %c, bit %d\n", + __FUNCTION__, port->num + 'A', index); + + spin_lock_irqsave(&gpio_mux_lock, lock_flags); + + gius_reg = __raw_readl(port->base + GPIO_GIUS); + gpr_reg = __raw_readl(port->base + GPIO_GPR); + + switch (mode) { + case GPIO_MUX_PRIMARY: + gius_reg &= ~(1L << index); + gpr_reg &= ~(1L << index); + break; + case GPIO_MUX_ALT: + gius_reg &= ~(1L << index); + gpr_reg |= (1L << index); + break; + case GPIO_MUX_GPIO: + gius_reg |= (1L << index); + _gpio_set_ocr(port, index, GPIO_OUTPUT_DR); + break; + case GPIO_MUX_INPUT1: + gius_reg |= (1L << index); + _gpio_set_iconfa(port, index, GPIO_INPUT_GPIO); + break; + case GPIO_MUX_INPUT2: + gius_reg |= (1L << index); + _gpio_set_iconfb(port, index, GPIO_INPUT_GPIO); + break; + case GPIO_MUX_OUTPUT1: + gius_reg |= (1L << index); + _gpio_set_ocr(port, index, GPIO_OUTPUT_A); + break; + case GPIO_MUX_OUTPUT2: + gius_reg |= (1L << index); + _gpio_set_ocr(port, index, GPIO_OUTPUT_B); + break; + case GPIO_MUX_OUTPUT3: + gius_reg |= (1L << index); + _gpio_set_ocr(port, index, GPIO_OUTPUT_C); + break; + default: + spin_unlock_irqrestore(&gpio_mux_lock, lock_flags); + return -1; + } + + __raw_writel(gius_reg, port->base + GPIO_GIUS); + __raw_writel(gpr_reg, port->base + GPIO_GPR); + + spin_unlock_irqrestore(&gpio_mux_lock, lock_flags); + return 0; +} + +/*! + * This function is just used to enable or disable the pull up feature . + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param en 0 if disable, Non-zero enable + * @return 0 if successful, Non-zero otherwise + */ +int gpio_set_puen(iomux_pin_name_t pin, bool en) +{ + unsigned long lock_flags; + + struct mxc_gpio_port *port; + u32 index, gpio = IOMUX_TO_GPIO(pin); + + port = &(mxc_gpio_ports[GPIO_TO_PORT(gpio)]); + index = GPIO_TO_INDEX(gpio); + + pr_debug("%s: Configuring output mode of PORT %c, bit %d\n", + __FUNCTION__, port->num + 'A', index); + + spin_lock_irqsave(&gpio_mux_lock, lock_flags); + + _gpio_set_puen(port, index, en); + spin_unlock_irqrestore(&gpio_mux_lock, lock_flags); + return 0; + +} + +/*! + * This function is just used to request a pin and configure it. + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param mode a module as define in \b #gpio_mux_mode_t; + * @return 0 if successful, Non-zero otherwise + */ +int gpio_request_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode) +{ + int ret; + ret = mxc_request_gpio(pin); + if (ret == 0) { + ret = gpio_config_mux(pin, mode); + if (ret) { + mxc_free_gpio(pin); + } + } + return ret; +} + +/*! + * This function is just used to release a pin. + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @return none + */ +void gpio_free_mux(iomux_pin_name_t pin) +{ + mxc_free_gpio(pin); +} diff -urN linux-2.6.26/arch/arm/mach-mx21/gpio_mux.h linux-2.6.26-lab126/arch/arm/mach-mx21/gpio_mux.h --- linux-2.6.26/arch/arm/mach-mx21/gpio_mux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx21/gpio_mux.h 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,78 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + *@file gpio_mux.h + *@brief This file contains the private definition . + * @ingroup GPIO_MX27 + */ + +#ifndef __ARCH_ARM_MACH_MX21_GPIO_MUX_H__ +#define __ARCH_ARM_MACH_MX21_GPIO_MUX_H__ + +#include "mx21_pins.h" + +/*! + * This enumeration data type defines the modes of the pin . + * GPIO_MUX_PRIMARY is the primary mode. + * GPIO_MUX_ALT is the alternate mode. + * GPIO_MUX_GPIO is the output mode and the signal source is data register. + * GPIO_MUX_INPUT1 is the input mode and the signal destination is A_OUT. + * GPIO_MUX_INPUT2 is the input mode and the signal destination is B_OUT. + * GPIO_MUX_OUTPUT1 is the output mode and the signal destination is A_IN. + * GPIO_MUX_OUTPUT2 is the output mode and the signal destination is B_IN. + * GPIO_MUX_OUTPUT3 is the output mode and the signal destination is C_IN. + */ +typedef enum { + GPIO_MUX_PRIMARY, + GPIO_MUX_ALT, + GPIO_MUX_GPIO, + GPIO_MUX_INPUT1, + GPIO_MUX_INPUT2, + GPIO_MUX_OUTPUT1, + GPIO_MUX_OUTPUT2, + GPIO_MUX_OUTPUT3, +} gpio_mux_mode_t; + +/*! + * This function is just used to request a pin and configure it. + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param mode a module as define in \b #gpio_mux_mode_t; + * @return 0 if successful, Non-zero otherwise + */ +extern int gpio_request_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode); + +/*! + * This function is just used to configure a pin . + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param mode a module as define in \b #gpio_mux_mode_t; + * @return 0 if successful, Non-zero otherwise + */ +extern int gpio_config_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode); + +/*! + * This function is just used to enable or disable the pull up feature . + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param en 0 if disable, Non-zero enable + * @return 0 if successful, Non-zero otherwise + */ +extern int gpio_set_puen(iomux_pin_name_t pin, bool en); + +/*! + * This function is just used to release a pin. + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @return none + */ +extern void gpio_free_mux(iomux_pin_name_t pin); + +#endif /* __ARCH_ARM_MACH_MX21_GPIO_MUX_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx21/mm.c linux-2.6.26-lab126/arch/arm/mach-mx21/mm.c --- linux-2.6.26/arch/arm/mach-mx21/mm.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx21/mm.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,55 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mm.c + * + * @brief This file creates static mapping between physical to virtual memory. + * + * @ingroup Memory + */ + +#include +#include + +#include +#include +#include + +static struct map_desc mxc_io_desc[] __initdata = { + { + .virtual = AIPI_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPI_BASE_ADDR), + .length = AIPI_SIZE, + .type = MT_DEVICE}, + { + .virtual = SAHB1_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(SAHB1_BASE_ADDR), + .length = SAHB1_SIZE, + .type = MT_DEVICE}, + { + .virtual = X_MEMC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR), + .length = X_MEMC_SIZE, + .type = MT_DEVICE}, + { + .virtual = CS1_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(CS1_BASE_ADDR), + .length = CS1_SIZE, + .type = MT_DEVICE} +}; + +void __init mxc_map_io(void) +{ + iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); +} diff -urN linux-2.6.26/arch/arm/mach-mx21/mx21_pins.h linux-2.6.26-lab126/arch/arm/mach-mx21/mx21_pins.h --- linux-2.6.26/arch/arm/mach-mx21/mx21_pins.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx21/mx21_pins.h 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,233 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_MX21_PINS_H__ +#define __ASM_ARCH_MXC_MX21_PINS_H__ + +#ifndef __ASSEMBLY__ + +/*! + * @name IOMUX/PAD Bit field definitions + */ + +/*! @{ */ + +/*! + * In order to identify pins more effectively, each mux-controlled pin's + * enumerated value is constructed in the following way: + * + * ------------------------------------------------------------------- + * 31-29 | 28 - 24 |23 - 21| 20 | 19 - 18 | 17 - 10| 9 - 8 | 7 - 0 + * ------------------------------------------------------------------- + * IO_P | IO_I | RSVD | PAD_F | PAD_I | MUX_F | MUX_I + * ------------------------------------------------------------------- + * + * Bit 0 to 7 contains MUX_I used to identify the register + * offset (0-based. base is IOMUX_module_base + 0xC) defined in the Section + * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. Bit 8 to 9 is MUX_F which + * contains the offset value defined WITHIN the same register (each IOMUX + * control register contains four 8-bit fields for four different pins). The + * similar field definitions are used for the pad control register. + * For example, the MX21_PIN_A0 is defined in the enumeration: + * ( 73 << MUX_I) | (0 << MUX_F)|( 98 << PAD_I) | (0 << PAD_F) + * It means the mux control register is at register offset 73. So the absolute + * address is: 0xC+73*4=0x130 0 << MUX_F means the control bits are at the + * least significant bits within the register. The pad control register offset + * is: 0x154+98*4=0x2DC and also occupy the least significant bits within the + * register. + */ + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * MUX control register index (0-based) + */ +#define MUX_I 0 + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * field within IOMUX control register for control bits + * (legal values are 0, 1, 2, 3) + */ +#define MUX_F 8 + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * PAD control register index (0-based) + */ +#define PAD_I 10 + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * field within PAD control register for control bits + * (legal values are 0, 1, 2) + */ +#define PAD_F 18 + +#define _MX21_BUILD_PIN(gp,gi) (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I)) + +/*! @} End IOMUX/PAD Bit field definitions */ + +/*! + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ +enum iomux_pins { + MX21_PIN_LSCLK = _MX21_BUILD_PIN(0, 5), + MX21_PIN_LD0 = _MX21_BUILD_PIN(0, 6), + MX21_PIN_LD1 = _MX21_BUILD_PIN(0, 7), + MX21_PIN_LD2 = _MX21_BUILD_PIN(0, 8), + MX21_PIN_LD3 = _MX21_BUILD_PIN(0, 9), + MX21_PIN_LD4 = _MX21_BUILD_PIN(0, 10), + MX21_PIN_LD5 = _MX21_BUILD_PIN(0, 11), + MX21_PIN_LD6 = _MX21_BUILD_PIN(0, 12), + MX21_PIN_LD7 = _MX21_BUILD_PIN(0, 13), + MX21_PIN_LD8 = _MX21_BUILD_PIN(0, 14), + MX21_PIN_LD9 = _MX21_BUILD_PIN(0, 15), + MX21_PIN_LD10 = _MX21_BUILD_PIN(0, 16), + MX21_PIN_LD11 = _MX21_BUILD_PIN(0, 17), + MX21_PIN_LD12 = _MX21_BUILD_PIN(0, 18), + MX21_PIN_LD13 = _MX21_BUILD_PIN(0, 19), + MX21_PIN_LD14 = _MX21_BUILD_PIN(0, 20), + MX21_PIN_LD15 = _MX21_BUILD_PIN(0, 21), + MX21_PIN_LD16 = _MX21_BUILD_PIN(0, 22), + MX21_PIN_LD17 = _MX21_BUILD_PIN(0, 23), + MX21_PIN_REV = _MX21_BUILD_PIN(0, 24), + MX21_PIN_CLS = _MX21_BUILD_PIN(0, 25), + MX21_PIN_PS = _MX21_BUILD_PIN(0, 26), + MX21_PIN_SPL_SPR = _MX21_BUILD_PIN(0, 27), + MX21_PIN_HSYNC = _MX21_BUILD_PIN(0, 28), + MX21_PIN_VSYNC = _MX21_BUILD_PIN(0, 29), + MX21_PIN_CONTRAST = _MX21_BUILD_PIN(0, 30), + MX21_PIN_OE_ACD = _MX21_BUILD_PIN(0, 31), + + MX21_PIN_SD2_D0 = _MX21_BUILD_PIN(1, 4), + MX21_PIN_SD2_D1 = _MX21_BUILD_PIN(1, 5), + MX21_PIN_SD2_D2 = _MX21_BUILD_PIN(1, 6), + MX21_PIN_SD2_D3 = _MX21_BUILD_PIN(1, 7), + MX21_PIN_SD2_CMD = _MX21_BUILD_PIN(1, 8), + MX21_PIN_SD2_CLK = _MX21_BUILD_PIN(1, 9), + MX21_PIN_CSI_D0 = _MX21_BUILD_PIN(1, 10), + MX21_PIN_CSI_D1 = _MX21_BUILD_PIN(1, 11), + MX21_PIN_CSI_D2 = _MX21_BUILD_PIN(1, 12), + MX21_PIN_CSI_D3 = _MX21_BUILD_PIN(1, 13), + MX21_PIN_CSI_D4 = _MX21_BUILD_PIN(1, 14), + MX21_PIN_CSI_MCLK = _MX21_BUILD_PIN(1, 15), + MX21_PIN_CSI_PIXCLK = _MX21_BUILD_PIN(1, 16), + MX21_PIN_CSI_D5 = _MX21_BUILD_PIN(1, 17), + MX21_PIN_CSI_D6 = _MX21_BUILD_PIN(1, 18), + MX21_PIN_CSI_D7 = _MX21_BUILD_PIN(1, 19), + MX21_PIN_CSI_VSYNC = _MX21_BUILD_PIN(1, 20), + MX21_PIN_CSI_HSYNC = _MX21_BUILD_PIN(1, 21), + MX21_PIN_USB_BYP = _MX21_BUILD_PIN(1, 22), + MX21_PIN_USB_PWR = _MX21_BUILD_PIN(1, 23), + MX21_PIN_USB_OC = _MX21_BUILD_PIN(1, 24), + MX21_PIN_USBH_ON = _MX21_BUILD_PIN(1, 25), + MX21_PIN_USBH1_FS = _MX21_BUILD_PIN(1, 26), + MX21_PIN_USBH1_OE = _MX21_BUILD_PIN(1, 27), + MX21_PIN_USBH1_TXDM = _MX21_BUILD_PIN(1, 28), + MX21_PIN_USBH1_TXDP = _MX21_BUILD_PIN(1, 29), + MX21_PIN_USBH1_RXDM = _MX21_BUILD_PIN(1, 30), + MX21_PIN_USBH1_RXDP = _MX21_BUILD_PIN(1, 31), + + MX21_PIN_USBG_SDA = _MX21_BUILD_PIN(2, 5), + MX21_PIN_USBG_SCL = _MX21_BUILD_PIN(2, 5), + MX21_PIN_USBG_ON = _MX21_BUILD_PIN(2, 7), + MX21_PIN_USBG_FS = _MX21_BUILD_PIN(2, 8), + MX21_PIN_USBG_OE = _MX21_BUILD_PIN(2, 9), + MX21_PIN_USBG_TXDM = _MX21_BUILD_PIN(2, 10), + MX21_PIN_USBG_TXDP = _MX21_BUILD_PIN(2, 11), + MX21_PIN_USBG_RXDM = _MX21_BUILD_PIN(2, 12), + MX21_PIN_USBG_RXDP = _MX21_BUILD_PIN(2, 13), + MX21_PIN_TOUT = _MX21_BUILD_PIN(2, 14), + MX21_PIN_TIN = _MX21_BUILD_PIN(2, 15), + MX21_PIN_SAP_FS = _MX21_BUILD_PIN(2, 16), + MX21_PIN_SAP_RXD = _MX21_BUILD_PIN(2, 17), + MX21_PIN_SAP_TXD = _MX21_BUILD_PIN(2, 18), + MX21_PIN_SAP_CLK = _MX21_BUILD_PIN(2, 19), + MX21_PIN_SSI1_FS = _MX21_BUILD_PIN(2, 20), + MX21_PIN_SSI1_RXD = _MX21_BUILD_PIN(2, 21), + MX21_PIN_SSI1_TXD = _MX21_BUILD_PIN(2, 22), + MX21_PIN_SSI1_CLK = _MX21_BUILD_PIN(2, 23), + MX21_PIN_SSI2_FS = _MX21_BUILD_PIN(2, 24), + MX21_PIN_SSI2_RXD = _MX21_BUILD_PIN(2, 25), + MX21_PIN_SSI2_TXD = _MX21_BUILD_PIN(2, 26), + MX21_PIN_SSI2_CLK = _MX21_BUILD_PIN(2, 27), + MX21_PIN_SSI3_FS = _MX21_BUILD_PIN(2, 28), + MX21_PIN_SSI3_RXD = _MX21_BUILD_PIN(2, 29), + MX21_PIN_SSI3_TXD = _MX21_BUILD_PIN(2, 30), + MX21_PIN_SSI3_CLK = _MX21_BUILD_PIN(2, 31), + + MX21_PIN_I2C_DATA = _MX21_BUILD_PIN(3, 17), + MX21_PIN_I2C_CLK = _MX21_BUILD_PIN(3, 18), + MX21_PIN_CSPI2_SS2 = _MX21_BUILD_PIN(3, 19), + MX21_PIN_CSPI2_SS1 = _MX21_BUILD_PIN(3, 20), + MX21_PIN_CSPI2_SS0 = _MX21_BUILD_PIN(3, 21), + MX21_PIN_CSPI2_SCLK = _MX21_BUILD_PIN(3, 22), + MX21_PIN_CSPI2_MISO = _MX21_BUILD_PIN(3, 23), + MX21_PIN_CSPI2_MOSI = _MX21_BUILD_PIN(3, 24), + MX21_PIN_CSPI1_RDY = _MX21_BUILD_PIN(3, 25), + MX21_PIN_CSPI1_SS2 = _MX21_BUILD_PIN(3, 26), + MX21_PIN_CSPI1_SS1 = _MX21_BUILD_PIN(3, 27), + MX21_PIN_CSPI1_SS0 = _MX21_BUILD_PIN(3, 28), + MX21_PIN_CSPI1_SCLK = _MX21_BUILD_PIN(3, 29), + MX21_PIN_CSPI1_MISO = _MX21_BUILD_PIN(3, 30), + MX21_PIN_CSPI1_MOSI = _MX21_BUILD_PIN(3, 31), + + MX21_PIN_WB2 = _MX21_BUILD_PIN(4, 0), + MX21_PIN_WB1 = _MX21_BUILD_PIN(4, 1), + MX21_PIN_WB0 = _MX21_BUILD_PIN(4, 2), + MX21_PIN_UART2_CTS = _MX21_BUILD_PIN(4, 3), + MX21_PIN_UART2_RTS = _MX21_BUILD_PIN(4, 4), + MX21_PIN_PWMO = _MX21_BUILD_PIN(4, 5), + MX21_PIN_UART2_TXD = _MX21_BUILD_PIN(4, 6), + MX21_PIN_UART2_RXD = _MX21_BUILD_PIN(4, 7), + MX21_PIN_UART3_TXD = _MX21_BUILD_PIN(4, 8), + MX21_PIN_UART3_RXD = _MX21_BUILD_PIN(4, 9), + MX21_PIN_UART3_CTS = _MX21_BUILD_PIN(4, 10), + MX21_PIN_UART3_RTS = _MX21_BUILD_PIN(4, 11), + MX21_PIN_UART1_TXD = _MX21_BUILD_PIN(4, 12), + MX21_PIN_UART1_RXD = _MX21_BUILD_PIN(4, 13), + MX21_PIN_UART1_CTS = _MX21_BUILD_PIN(4, 14), + MX21_PIN_UART1_RTS = _MX21_BUILD_PIN(4, 15), + MX21_PIN_RTCK = _MX21_BUILD_PIN(4, 16), + MX21_PIN_RESET_OUT = _MX21_BUILD_PIN(4, 17), + MX21_PIN_SD1_D0 = _MX21_BUILD_PIN(4, 18), + MX21_PIN_SD1_D1 = _MX21_BUILD_PIN(4, 19), + MX21_PIN_SD1_D2 = _MX21_BUILD_PIN(4, 20), + MX21_PIN_SD1_D3 = _MX21_BUILD_PIN(4, 21), + MX21_PIN_SD1_CMD = _MX21_BUILD_PIN(4, 22), + MX21_PIN_SD1_CLK = _MX21_BUILD_PIN(4, 23), + + MX21_PIN_NFRB = _MX21_BUILD_PIN(5, 0), + MX21_PIN_NFCE = _MX21_BUILD_PIN(5, 1), + MX21_PIN_NFWP = _MX21_BUILD_PIN(5, 2), + MX21_PIN_NFCLE = _MX21_BUILD_PIN(5, 3), + MX21_PIN_NFALE = _MX21_BUILD_PIN(5, 4), + MX21_PIN_NFRE = _MX21_BUILD_PIN(5, 5), + MX21_PIN_NFWE = _MX21_BUILD_PIN(5, 6), + MX21_PIN_NFIO0 = _MX21_BUILD_PIN(5, 7), + MX21_PIN_NFIO1 = _MX21_BUILD_PIN(5, 8), + MX21_PIN_NFIO2 = _MX21_BUILD_PIN(5, 9), + MX21_PIN_NFIO3 = _MX21_BUILD_PIN(5, 10), + MX21_PIN_NFIO4 = _MX21_BUILD_PIN(5, 11), + MX21_PIN_NFIO5 = _MX21_BUILD_PIN(5, 12), + MX21_PIN_NFIO6 = _MX21_BUILD_PIN(5, 13), + MX21_PIN_NFIO7 = _MX21_BUILD_PIN(5, 14), + MX21_PIN_CLKO = _MX21_BUILD_PIN(5, 15), + MX21_PIN_PF16 = _MX21_BUILD_PIN(5, 16), + MX21_PIN_CS4 = _MX21_BUILD_PIN(5, 21), + MX21_PIN_CS5 = _MX21_BUILD_PIN(5, 22), +}; + +#endif +#endif diff -urN linux-2.6.26/arch/arm/mach-mx21/mx21ads.c linux-2.6.26-lab126/arch/arm/mach-mx21/mx21ads.c --- linux-2.6.26/arch/arm/mach-mx21/mx21ads.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx21/mx21ads.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,353 @@ +/* + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE) +#include +#include +#include + +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "gpio_mux.h" + +/*! + * @file mx21ads.c + * @brief This file contains the board specific initialization routines. + * + * @ingroup System + */ + +extern void mxc_map_io(void); +extern void mxc_init_irq(void); +extern void mxc_cpu_init(void) __init; +extern void gpio_nand_active(void); +extern struct sys_timer mxc_timer; + +static void mxc_nop_release(struct device *dev) +{ + /* Nothing */ +} + +#if defined(CONFIG_KEYBOARD_MXC) || defined(CONFIG_KEYBOARD_MXC_MODULE) + +/*! + * This array is used for mapping mx27 ADS keypad scancodes to input keyboard + * keycodes. + */ +static u16 mxckpd_keycodes[(MAXROW * MAXCOL)] = { + KEY_KP9, KEY_LEFTSHIFT, KEY_0, KEY_KPASTERISK, KEY_RECORD, KEY_POWER, + KEY_KP8, KEY_9, KEY_8, KEY_7, KEY_KP5, KEY_VOLUMEDOWN, + KEY_KP7, KEY_6, KEY_5, KEY_4, KEY_KP4, KEY_VOLUMEUP, + KEY_KP6, KEY_3, KEY_2, KEY_1, KEY_KP3, KEY_DOWN, + KEY_BACK, KEY_RIGHT, KEY_ENTER, KEY_LEFT, KEY_HOME, KEY_KP2, + KEY_END, KEY_F2, KEY_UP, KEY_F1, KEY_F4, KEY_KP1, +}; + +static struct keypad_data evb_6_by_6_keypad = { + .rowmax = 6, + .colmax = 6, + .irq = INT_KPP, + .learning = 0, + .delay = 2, + .matrix = mxckpd_keycodes, +}; + +static struct resource mxc_kpp_resources[] = { + [0] = { + .start = INT_KPP, + .end = INT_KPP, + .flags = IORESOURCE_IRQ, + } +}; + +/* mxc keypad driver */ +static struct platform_device mxc_keypad_device = { + .name = "mxc_keypad", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_kpp_resources), + .resource = mxc_kpp_resources, + .dev = { + .release = mxc_nop_release, + .platform_data = &evb_6_by_6_keypad, + }, +}; + +static void mxc_init_keypad(void) +{ + printk("mx27ads.c: registering mxc keypad device..."); + (void)platform_device_register(&mxc_keypad_device); +} +#else +static inline void mxc_init_keypad(void) +{ +} +#endif + +/* MTD NOR flash */ + +#if defined(CONFIG_MTD_MXC) || defined(CONFIG_MTD_MXC_MODULE) + +static struct mtd_partition mxc_nor_partitions[] = { + { + .name = "Bootloader", + .size = 512 * 1024, + .offset = 0x00000000, + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, + { + .name = "nor.Kernel", + .size = 2 * 1024 * 1024, + .offset = MTDPART_OFS_APPEND, + .mask_flags = 0}, + { + .name = "nor.userfs", + .size = 14 * 1024 * 1024, + .offset = MTDPART_OFS_APPEND, + .mask_flags = 0}, + { + .name = "nor.rootfs", + .size = 12 * 1024 * 1024, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE}, + { + .name = "FIS directory", + .size = 12 * 1024, + .offset = 0x01FE0000, + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, + { + .name = "Redboot config", + .size = MTDPART_SIZ_FULL, + .offset = 0x01FFF000, + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, +}; + +static struct flash_platform_data mxc_flash_data = { + .map_name = "cfi_probe", + .width = 4, + .parts = mxc_nor_partitions, + .nr_parts = ARRAY_SIZE(mxc_nor_partitions), +}; + +static struct resource mxc_flash_resource = { + .start = 0xC8000000, + .end = 0xC8000000 + 0x02000000 - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device mxc_nor_mtd_device = { + .name = "mxc_nor_flash", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_flash_data, + }, + .num_resources = 1, + .resource = &mxc_flash_resource, +}; + +static void mxc_init_nor_mtd(void) +{ + (void)platform_device_register(&mxc_nor_mtd_device); +} +#else +static void mxc_init_nor_mtd(void) +{ +} +#endif + +/* MTD NAND flash */ + +#if defined(CONFIG_MTD_NAND_MXC) || defined(CONFIG_MTD_NAND_MXC_MODULE) + +static struct mtd_partition mxc_nand_partitions[4] = { + { + .name = "nand.bootloader", + .offset = 0, + .size = 1024 * 1024}, + { + .name = "nand.kernel", + .offset = MTDPART_OFS_APPEND, + .size = 5 * 1024 * 1024}, + { + .name = "nand.rootfs", + .offset = MTDPART_OFS_APPEND, + .size = 22 * 1024 * 1024}, + { + .name = "nand.userfs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL}, +}; + +static struct flash_platform_data mxc_nand_data = { + .parts = mxc_nand_partitions, + .nr_parts = ARRAY_SIZE(mxc_nand_partitions), + .width = 1, +}; + +static struct platform_device mxc_nand_mtd_device = { + .name = "mxc_nand_flash", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_nand_data, + }, +}; + +static void mxc_init_nand_mtd(void) +{ + gpio_nand_active(); + (void)platform_device_register(&mxc_nand_mtd_device); +} +#else +static inline void mxc_init_nand_mtd(void) +{ +} +#endif + +#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) +static const char fb_default_mode[] = "Sharp-QVGA"; + +/* mxc lcd driver */ +static struct platform_device mxc_fb_device = { + .name = "mxc_sdc_fb", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &fb_default_mode, + .coherent_dma_mask = 0xFFFFFFFF, + }, +}; + +static void mxc_init_fb(void) +{ + (void)platform_device_register(&mxc_fb_device); +} +#else +static inline void mxc_init_fb(void) +{ +} +#endif + +#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) +/*! + * The serial port definition structure. The fields contain: + * {UART, CLK, PORT, IRQ, FLAGS} + */ +static struct plat_serial8250_port serial_platform_data[] = { + { + .membase = (void __iomem *)(CS1_BASE_ADDR_VIRT + 0x00200000), + .mapbase = (unsigned long)(CS1_BASE_ADDR + 0x00200000), + .irq = IOMUX_TO_IRQ(MX21_PIN_TIN), + .uartclk = 3686400, + .regshift = 1, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + }, +}; + +/*! + * REVISIT: document me + */ +static struct platform_device serial_device = { + .name = "serial8250", + .id = 0, + .dev = { + .platform_data = &serial_platform_data[0], + }, +}; + +/*! + * REVISIT: document me + */ +static int __init mxc_init_extuart(void) +{ + gpio_config_mux(MX21_PIN_TIN, GPIO_MUX_GPIO); + set_irq_type(serial_platform_data[0].irq, IRQT_RISING); + return platform_device_register(&serial_device); +} +#else +static inline int mxc_init_extuart(void) +{ + return 0; +} +#endif + +void mxc_init_enet(void) +{ + gpio_config_mux(MX21_PIN_UART3_RTS, GPIO_MUX_GPIO); + set_irq_type(CS8900AIRQ, IRQT_RISING); +} + +static void mxc_board_init(void) +{ + mxc_gpio_init(); + + mxc_init_keypad(); + mxc_init_enet(); + mxc_init_nor_mtd(); + mxc_init_nand_mtd(); + mxc_init_extuart(); + mxc_init_fb(); +} + +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ +} + +/* *INDENT-OFF* */ +MACHINE_START(MX21ADS, "Freescale i.MX21 ADS") + /* maintainer: Freescale Semiconductor, Inc. */ +#ifdef CONFIG_SERIAL_8250_CONSOLE + .phys_io = CS1_BASE_ADDR, + .io_pg_offst = ((CS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, +#else + .phys_io = AIPI_BASE_ADDR, + .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, +#endif + .boot_params = PHYS_OFFSET + 0x100, + .fixup = fixup_mxc_board, + .map_io = mxc_map_io, + .init_irq = mxc_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff -urN linux-2.6.26/arch/arm/mach-mx21/mx21ads_gpio.c linux-2.6.26-lab126/arch/arm/mach-mx21/mx21ads_gpio.c --- linux-2.6.26/arch/arm/mach-mx21/mx21ads_gpio.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx21/mx21ads_gpio.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,384 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "gpio_mux.h" +#include "crm_regs.h" + +static int g_uart_actived[4] = { 0, 0, 0, 0 }; + +/*! + * @file mx21ads_gpio.c + * + * @brief This file contains all the GPIO setup functions for the board. + * + * @ingroup GPIO + */ + +/*! + * Setup GPIO for a UART port to be active + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_active(int port, int no_irda) +{ + if (port < 0 || port >= MXC_UART_NR) { + pr_info("Wrong GPIO port number: %d\n", port); + BUG(); + } + + if (g_uart_actived[port]) { + pr_info("UART %d GPIO have been actived multi-times\n", + port + 1); + return; + } + g_uart_actived[port] = 1; + + switch (port) { + case 0: + gpio_request_mux(MX21_PIN_UART1_TXD, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_UART1_RXD, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_UART1_CTS, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_UART1_RTS, GPIO_MUX_PRIMARY); + break; + case 1: + gpio_request_mux(MX21_PIN_UART2_TXD, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_UART2_RXD, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_UART2_CTS, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_UART2_RTS, GPIO_MUX_PRIMARY); + break; + default: + break; + } +} + +/*! + * Setup GPIO for a UART port to be inactive + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_inactive(int port, int no_irda) +{ + if (port < 0 || port >= MXC_UART_NR) { + pr_info("Wrong GPIO port number: %d\n", port); + BUG(); + } + + if (g_uart_actived[port] == 0) { + pr_info("UART %d GPIO have not been actived \n", port + 1); + return; + } + g_uart_actived[port] = 0; + + switch (port) { + case 0: + gpio_free_mux(MX21_PIN_UART1_TXD); + gpio_free_mux(MX21_PIN_UART1_RXD); + gpio_free_mux(MX21_PIN_UART1_CTS); + gpio_free_mux(MX21_PIN_UART1_RTS); + break; + case 1: + gpio_free_mux(MX21_PIN_UART2_TXD); + gpio_free_mux(MX21_PIN_UART2_RXD); + gpio_free_mux(MX21_PIN_UART2_CTS); + gpio_free_mux(MX21_PIN_UART2_RTS); + break; + case 2: + break; + case 3: + break; + default: + break; + } +} + +/*! + * Configure the IOMUX GPR register to receive shared SDMA UART events + * + * @param port a UART port + */ +void config_uartdma_event(int port) +{ + return; +} + +/************************************************************************/ +/* for i2c gpio */ +/* PD17,PD18 -- Primary */ +/************************************************************************/ +#define GPIO_I2C (( 1<<17 ) |( 1<<18) ) +/*! +* Setup GPIO for an I2C device to be active +* +* @param i2c_num an I2C device +*/ +void gpio_i2c_active(int i2c_num) +{ + switch (i2c_num) { + case 0: + gpio_request_mux(MX21_PIN_I2C_CLK, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_I2C_DATA, GPIO_MUX_PRIMARY); + break; + default: + printk("gpio_i2c_active no compatible I2C adapter\n"); + break; + } +} + +/*! + * * Setup GPIO for an I2C device to be inactive + * * + * * @param i2c_num an I2C device + */ +void gpio_i2c_inactive(int i2c_num) +{ + switch (i2c_num) { + case 0: + gpio_free_mux(MX21_PIN_I2C_CLK); + gpio_free_mux(MX21_PIN_I2C_DATA); + break; + default: + break; + } +} + +/*! + * Setup GPIO for a CSPI device to be active + * + * @param cspi_mod an CSPI device + */ +void gpio_spi_active(int cspi_mod) +{ + switch (cspi_mod) { + case 0: + /* SPI1 */ + gpio_request_mux(MX21_PIN_CSPI1_RDY, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_CSPI1_SS2, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_CSPI1_SS1, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_CSPI1_SS0, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_CSPI1_MISO, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_CSPI1_MOSI, GPIO_MUX_PRIMARY); + break; + case 1: + /* SPI2 */ + gpio_request_mux(MX21_PIN_CSPI2_SS2, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_CSPI2_SS1, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_CSPI2_SS0, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_CSPI2_MISO, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_CSPI2_MOSI, GPIO_MUX_PRIMARY); + break; + + default: + break; + } +} + +/*! + * Setup GPIO for a CSPI device to be inactive + * + * @param cspi_mod a CSPI device + */ +void gpio_spi_inactive(int cspi_mod) +{ + switch (cspi_mod) { + case 0: + /* SPI1 */ + gpio_free_mux(MX21_PIN_CSPI1_RDY); + gpio_free_mux(MX21_PIN_CSPI1_SS2); + gpio_free_mux(MX21_PIN_CSPI1_SS1); + gpio_free_mux(MX21_PIN_CSPI1_SS0); + gpio_free_mux(MX21_PIN_CSPI1_MISO); + gpio_free_mux(MX21_PIN_CSPI1_MOSI); + break; + case 1: + /* SPI2 */ + gpio_free_mux(MX21_PIN_CSPI2_SS2); + gpio_free_mux(MX21_PIN_CSPI2_SS1); + gpio_free_mux(MX21_PIN_CSPI2_SS0); + gpio_free_mux(MX21_PIN_CSPI2_MISO); + gpio_free_mux(MX21_PIN_CSPI2_MOSI); + break; + + default: + break; + } +} + +/*! + * Setup GPIO for a nand flash device to be active + * + */ +void gpio_nand_active(void) +{ + gpio_request_mux(MX21_PIN_NFALE, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_NFCE, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_NFCLE, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_NFRB, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_NFRE, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_NFWE, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_NFWP, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_NFIO1, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_NFIO2, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_NFIO3, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_NFIO4, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_NFIO5, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_NFIO6, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_NFIO7, GPIO_MUX_PRIMARY); +} + +/*! + * Setup GPIO for a nand flash device to be inactive + * + */ +void gpio_nand_inactive(void) +{ + gpio_free_mux(MX21_PIN_NFALE); + gpio_free_mux(MX21_PIN_NFCE); + gpio_free_mux(MX21_PIN_NFCLE); + gpio_free_mux(MX21_PIN_NFRB); + gpio_free_mux(MX21_PIN_NFRE); + gpio_free_mux(MX21_PIN_NFWE); + gpio_free_mux(MX21_PIN_NFWP); + gpio_free_mux(MX21_PIN_NFIO1); + gpio_free_mux(MX21_PIN_NFIO2); + gpio_free_mux(MX21_PIN_NFIO3); + gpio_free_mux(MX21_PIN_NFIO4); + gpio_free_mux(MX21_PIN_NFIO5); + gpio_free_mux(MX21_PIN_NFIO6); + gpio_free_mux(MX21_PIN_NFIO7); +} + +/*! + * Setup GPIO for LCDC device to be active + * + */ +void gpio_lcdc_active(void) +{ + gpio_request_mux(MX21_PIN_LSCLK, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_LD0, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_LD1, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_LD2, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_LD3, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_LD4, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_LD5, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_LD6, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_LD7, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_LD8, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_LD9, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_LD10, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_LD11, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_LD12, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_LD13, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_LD14, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_LD15, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_LD16, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_LD17, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_REV, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_CLS, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_PS, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_SPL_SPR, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_HSYNC, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_VSYNC, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_CONTRAST, GPIO_MUX_PRIMARY); + gpio_request_mux(MX21_PIN_OE_ACD, GPIO_MUX_PRIMARY); +} + +/*! + * Setup GPIO for LCDC device to be inactive + * + */ +void gpio_lcdc_inactive(void) +{ + gpio_free_mux(MX21_PIN_LSCLK); + gpio_free_mux(MX21_PIN_LD0); + gpio_free_mux(MX21_PIN_LD1); + gpio_free_mux(MX21_PIN_LD2); + gpio_free_mux(MX21_PIN_LD3); + gpio_free_mux(MX21_PIN_LD4); + gpio_free_mux(MX21_PIN_LD5); + gpio_free_mux(MX21_PIN_LD6); + gpio_free_mux(MX21_PIN_LD7); + gpio_free_mux(MX21_PIN_LD8); + gpio_free_mux(MX21_PIN_LD9); + gpio_free_mux(MX21_PIN_LD10); + gpio_free_mux(MX21_PIN_LD11); + gpio_free_mux(MX21_PIN_LD12); + gpio_free_mux(MX21_PIN_LD13); + gpio_free_mux(MX21_PIN_LD14); + gpio_free_mux(MX21_PIN_LD15); + gpio_free_mux(MX21_PIN_LD16); + gpio_free_mux(MX21_PIN_LD17); + gpio_free_mux(MX21_PIN_REV); + gpio_free_mux(MX21_PIN_CLS); + gpio_free_mux(MX21_PIN_PS); + gpio_free_mux(MX21_PIN_SPL_SPR); + gpio_free_mux(MX21_PIN_HSYNC); + gpio_free_mux(MX21_PIN_VSYNC); + gpio_free_mux(MX21_PIN_CONTRAST); + gpio_free_mux(MX21_PIN_OE_ACD); +} + +/*! + * GPIO settings not required for keypad + * + */ +void gpio_keypad_active(void) +{ +} + +/*! + * GPIO settings not required for keypad + * + */ +void gpio_keypad_inactive(void) +{ +} + +void board_power_lcd(int on) +{ + volatile unsigned short reg; + + reg = __raw_readw(CS1_BASE_ADDR_VIRT + 0x800000); + if (on == 0) + /* turn it off */ + reg &= ~0x0200; + else + /* turn it on */ + reg |= 0x0200; + + __raw_writew(reg, CS1_BASE_ADDR_VIRT + 0x800000); +} + +EXPORT_SYMBOL(gpio_uart_active); +EXPORT_SYMBOL(gpio_uart_inactive); +EXPORT_SYMBOL(config_uartdma_event); +EXPORT_SYMBOL(gpio_i2c_active); +EXPORT_SYMBOL(gpio_i2c_inactive); +EXPORT_SYMBOL(gpio_spi_active); +EXPORT_SYMBOL(gpio_spi_inactive); +EXPORT_SYMBOL(gpio_nand_active); +EXPORT_SYMBOL(gpio_nand_inactive); +EXPORT_SYMBOL(gpio_lcdc_active); +EXPORT_SYMBOL(gpio_lcdc_inactive); +EXPORT_SYMBOL(gpio_keypad_active); +EXPORT_SYMBOL(gpio_keypad_inactive); +EXPORT_SYMBOL(board_power_lcd); diff -urN linux-2.6.26/arch/arm/mach-mx21/serial.c linux-2.6.26-lab126/arch/arm/mach-mx21/serial.c --- linux-2.6.26/arch/arm/mach-mx21/serial.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx21/serial.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,200 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @file serial.c + * + * @brief This file contains the UART initiliazation. + * + * @ingroup System + */ +#include +#include +#include +#include +#include +#include "serial.h" + +#if defined(CONFIG_SERIAL_MXC) || defined(CONFIG_SERIAL_MXC_MODULE) + +/*! + * This is an array where each element holds information about a UART port, + * like base address of the UART, interrupt numbers etc. This structure is + * passed to the serial_core.c file. Based on which UART is used, the core file + * passes back the appropriate port structure as an argument to the control + * functions. + */ +static uart_mxc_port mxc_ports[] = { + [0] = { + .port = { + .membase = (void *)IO_ADDRESS(UART1_BASE_ADDR), + .mapbase = UART1_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART1_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 0, + }, + .ints_muxed = UART1_MUX_INTS, + .irqs = {UART1_INT2, UART1_INT3}, + .mode = UART1_MODE, + .ir_mode = UART1_IR, + .enabled = UART1_ENABLED, + .hardware_flow = UART1_HW_FLOW, + .cts_threshold = UART1_UCR4_CTSTL, + .dma_enabled = UART1_DMA_ENABLE, + .dma_rxbuf_size = UART1_DMA_RXBUFSIZE, + .rx_threshold = UART1_UFCR_RXTL, + .tx_threshold = UART1_UFCR_TXTL, + .shared = UART1_SHARED_PERI, + .clock_id = UART1_BAUD, + .dma_tx_id = MXC_DMA_UART1_TX, + .dma_rx_id = MXC_DMA_UART1_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, + [1] = { + .port = { + .membase = (void *)IO_ADDRESS(UART2_BASE_ADDR), + .mapbase = UART2_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART2_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 1, + }, + .ints_muxed = UART2_MUX_INTS, + .irqs = {UART2_INT2, UART2_INT3}, + .mode = UART2_MODE, + .ir_mode = UART2_IR, + .enabled = UART2_ENABLED, + .hardware_flow = UART2_HW_FLOW, + .cts_threshold = UART2_UCR4_CTSTL, + .dma_enabled = UART2_DMA_ENABLE, + .dma_rxbuf_size = UART2_DMA_RXBUFSIZE, + .rx_threshold = UART2_UFCR_RXTL, + .tx_threshold = UART2_UFCR_TXTL, + .shared = UART2_SHARED_PERI, + .clock_id = UART2_BAUD, + .dma_tx_id = MXC_DMA_UART2_TX, + .dma_rx_id = MXC_DMA_UART2_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, + [2] = { + .port = { + .membase = (void *)IO_ADDRESS(UART3_BASE_ADDR), + .mapbase = UART3_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART3_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 2, + }, + .ints_muxed = UART3_MUX_INTS, + .irqs = {UART3_INT2, UART3_INT3}, + .mode = UART3_MODE, + .ir_mode = UART3_IR, + .enabled = UART3_ENABLED, + .hardware_flow = UART3_HW_FLOW, + .cts_threshold = UART3_UCR4_CTSTL, + .dma_enabled = UART3_DMA_ENABLE, + .dma_rxbuf_size = UART3_DMA_RXBUFSIZE, + .rx_threshold = UART3_UFCR_RXTL, + .tx_threshold = UART3_UFCR_TXTL, + .shared = UART3_SHARED_PERI, + .clock_id = UART3_BAUD, + .dma_tx_id = MXC_DMA_UART3_TX, + .dma_rx_id = MXC_DMA_UART3_RX, + .rxd_mux = MXC_UART_IR_RXDMUX, + }, + [3] = { + .port = { + .membase = (void *)IO_ADDRESS(UART4_BASE_ADDR), + .mapbase = UART4_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART4_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 3, + }, + .ints_muxed = UART4_MUX_INTS, + .irqs = {UART4_INT2, UART4_INT3}, + .mode = UART4_MODE, + .ir_mode = UART4_IR, + .enabled = UART4_ENABLED, + .hardware_flow = UART4_HW_FLOW, + .cts_threshold = UART4_UCR4_CTSTL, + .dma_enabled = UART4_DMA_ENABLE, + .dma_rxbuf_size = UART4_DMA_RXBUFSIZE, + .rx_threshold = UART4_UFCR_RXTL, + .tx_threshold = UART4_UFCR_TXTL, + .shared = UART4_SHARED_PERI, + .clock_id = UART4_BAUD, + .dma_tx_id = MXC_DMA_UART4_TX, + .dma_rx_id = MXC_DMA_UART4_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, +}; + +static struct platform_device mxc_uart_device1 = { + .name = "mxcintuart", + .id = 0, + .dev = { + .platform_data = &mxc_ports[0], + }, +}; + +static struct platform_device mxc_uart_device2 = { + .name = "mxcintuart", + .id = 1, + .dev = { + .platform_data = &mxc_ports[1], + }, +}; + +static struct platform_device mxc_uart_device3 = { + .name = "mxcintuart", + .id = 2, + .dev = { + .platform_data = &mxc_ports[2], + }, +}; + +static struct platform_device mxc_uart_device4 = { + .name = "mxcintuart", + .id = 3, + .dev = { + .platform_data = &mxc_ports[3], + }, +}; + +static int __init mxc_init_uart(void) +{ + /* Register all the MXC UART platform device structures */ + platform_device_register(&mxc_uart_device1); + platform_device_register(&mxc_uart_device2); + platform_device_register(&mxc_uart_device3); + +#if UART4_ENABLED == 1 + platform_device_register(&mxc_uart_device4); +#endif /* UART4_ENABLED */ + + return 0; +} + +#else +static int __init mxc_init_uart(void) +{ + return 0; +} +#endif + +arch_initcall(mxc_init_uart); diff -urN linux-2.6.26/arch/arm/mach-mx21/serial.h linux-2.6.26-lab126/arch/arm/mach-mx21/serial.h --- linux-2.6.26/arch/arm/mach-mx21/serial.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx21/serial.h 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,139 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ARCH_ARM_MACH_MX21_SERIAL_H__ +#define __ARCH_ARM_MACH_MX21_SERIAL_H__ + +#include + +/* UART 1 configuration */ +/*! + * This option allows to choose either an interrupt-driven software controlled + * hardware flow control (set this option to 0) or hardware-driven hardware + * flow control (set this option to 1). + */ +#define UART1_HW_FLOW 1 +/*! + * This specifies the threshold at which the CTS pin is deasserted by the + * RXFIFO. Set this value in Decimal to anything from 0 to 32 for + * hardware-driven hardware flow control. Read the HW spec while specifying + * this value. When using interrupt-driven software controlled hardware + * flow control set this option to -1. + */ +#define UART1_UCR4_CTSTL 16 +/*! + * This is option to enable (set this option to 1) or disable DMA data transfer + */ +#define UART1_DMA_ENABLE 0 +/*! + * Specify the size of the DMA receive buffer. The minimum buffer size is 512 + * bytes. The buffer size should be a multiple of 256. + */ +#define UART1_DMA_RXBUFSIZE 1024 +/*! + * Specify the MXC UART's Receive Trigger Level. This controls the threshold at + * which a maskable interrupt is generated by the RxFIFO. Set this value in + * Decimal to anything from 0 to 32. Read the HW spec while specifying this + * value. + */ +#define UART1_UFCR_RXTL 16 +/*! + * Specify the MXC UART's Transmit Trigger Level. This controls the threshold at + * which a maskable interrupt is generated by the TxFIFO. Set this value in + * Decimal to anything from 0 to 32. Read the HW spec while specifying this + * value. + */ +#define UART1_UFCR_TXTL 16 +/* UART 2 configuration */ +#define UART2_HW_FLOW 0 +#define UART2_UCR4_CTSTL -1 +#define UART2_DMA_ENABLE 0 +#define UART2_DMA_RXBUFSIZE 512 +#define UART2_UFCR_RXTL 16 +#define UART2_UFCR_TXTL 16 +/* UART 3 configuration */ +#define UART3_HW_FLOW 1 +#define UART3_UCR4_CTSTL 16 +#define UART3_DMA_ENABLE 0 +#define UART3_DMA_RXBUFSIZE 1024 +#define UART3_UFCR_RXTL 16 +#define UART3_UFCR_TXTL 16 +/* UART 4 configuration */ +#define UART4_HW_FLOW 1 +#define UART4_UCR4_CTSTL 16 +#define UART4_DMA_ENABLE 0 +#define UART4_DMA_RXBUFSIZE 512 +#define UART4_UFCR_RXTL 16 +#define UART4_UFCR_TXTL 16 +/* + * UART Chip level Configuration that a user may not have to edit. These + * configuration vary depending on how the UART module is integrated with + * the ARM core + */ +/* + * Is the MUXED interrupt output sent to the ARM core + */ +#define INTS_NOTMUXED 0 +#define INTS_MUXED 1 +/* UART 1 configuration */ +/*! + * This define specifies whether the muxed ANDed interrupt line or the + * individual interrupts from the UART port is integrated with the ARM core. + * There exists a define like this for each UART port. Valid values that can + * be used are \b INTS_NOTMUXED or \b INTS_MUXED. + */ +#define UART1_MUX_INTS INTS_MUXED +/*! + * This define specifies the transmitter interrupt number or the interrupt + * number of the ANDed interrupt in case the interrupts are muxed. There exists + * a define like this for each UART port. + */ +#define UART1_INT1 INT_UART1 +/*! + * This define specifies the receiver interrupt number. If the interrupts of + * the UART are muxed, then we specify here a dummy value -1. There exists a + * define like this for each UART port. + */ +#define UART1_INT2 -1 +/*! + * This specifies the master interrupt number. If the interrupts of the UART + * are muxed, then we specify here a dummy value of -1. There exists a define + * like this for each UART port. + */ +#define UART1_INT3 -1 +/*! + * This specifies if the UART is a shared peripheral. It holds the shared + * peripheral number if it is shared or -1 if it is not shared. There exists + * a define like this for each UART port. + */ +#define UART1_SHARED_PERI -1 +/* UART 2 configuration */ +#define UART2_MUX_INTS INTS_MUXED +#define UART2_INT1 INT_UART2 +#define UART2_INT2 -1 +#define UART2_INT3 -1 +#define UART2_SHARED_PERI -1 +/* UART 3 configuration */ +#define UART3_MUX_INTS INTS_MUXED +#define UART3_INT1 INT_UART3 +#define UART3_INT2 -1 +#define UART3_INT3 -1 +#define UART3_SHARED_PERI -1 +/* UART 4 configuration */ +#define UART4_MUX_INTS INTS_MUXED +#define UART4_INT1 INT_UART4 +#define UART4_INT2 -1 +#define UART4_INT3 -1 +#define UART4_SHARED_PERI -1 + +#endif /* __ARCH_ARM_MACH_MX21_SERIAL_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx21/system.c linux-2.6.26-lab126/arch/arm/mach-mx21/system.c --- linux-2.6.26/arch/arm/mach-mx21/system.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx21/system.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,65 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +/*! + * @defgroup MSL Machine Specific Layer (MSL) + */ + +/*! + * @defgroup System System-wide Misc Files for MSL + * @ingroup MSL + */ + +/*! + * @file system.c + * @brief This file contains idle and reset functions. + * + * @ingroup System + */ + +/*! + * This function puts the CPU into idle mode. It is called by default_idle() + * in process.c file. + */ +void arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks. + */ + cpu_do_idle(); +} + +/* + * This function resets the system. It is called by machine_restart(). + * + * @param mode indicates different kinds of resets + */ +void arch_reset(char mode) +{ + /* Assert Watchdog Reset signal */ + mxc_wd_reset(); +} diff -urN linux-2.6.26/arch/arm/mach-mx21/time.c linux-2.6.26-lab126/arch/arm/mach-mx21/time.c --- linux-2.6.26/arch/arm/mach-mx21/time.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx21/time.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,168 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* System Timer Interrupt reconfigured to run in free-run mode. + * Author: Vitaly Wool + * Copyright 2004 MontaVista Software Inc. + */ + +/*! + * @file time.c + * @brief This file contains OS tick implementations. + * + * This file contains OS tick implementations. + * + * @ingroup Timers + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifndef __noinstrument +#define __noinstrument +#endif + +/* OS tick defines */ +#define MXC_GPT_INT_TICK INT_GPT +#define MXC_GPT_CLOCK_TICK GPT1_CLK +#define MXC_GPT_TCMP_TICK MXC_GPT_TCMP(MXC_TIMER_GPT1) +#define MXC_GPT_TSTAT_TICK MXC_GPT_TSTAT(MXC_TIMER_GPT1) +#define MXC_GPT_TCTL_TICK MXC_GPT_TCTL(MXC_TIMER_GPT1) +#define MXC_GPT_TPRER_TICK MXC_GPT_TPRER(MXC_TIMER_GPT1) +#define MXC_GPT_TCN_TICK MXC_GPT_TCN(MXC_TIMER_GPT1) +/* High resolution timer defines */ +#define MXC_GPT_INT_HRT INT_GPT2 +#define MXC_GPT_CLOCK_HRT GPT2_CLK +#define MXC_GPT_TCMP_HRT MXC_GPT_TCMP(MXC_TIMER_GPT2) +#define MXC_GPT_TSTAT_HRT MXC_GPT_TSTAT(MXC_TIMER_GPT2) +#define MXC_GPT_TCTL_HRT MXC_GPT_TCTL(MXC_TIMER_GPT2) +#define MXC_GPT_TPRER_HRT MXC_GPT_TPRER(MXC_TIMER_GPT2) +#define MXC_GPT_TCN_HRT MXC_GPT_TCN(MXC_TIMER_GPT2) + +/*! + * This is the timer interrupt service routine to do required tasks. + * + * @param irq GPT interrupt source number (not used) + * @param dev_id this parameter is not used + * @param regs pointer to a structure containing the processor + * registers and state prior to servicing the interrupt + * @return always returns \b IRQ_HANDLED as defined in + * include/linux/interrupt.h. + */ +static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id, + struct pt_regs *regs) +{ + unsigned int next_match; + + write_seqlock(&xtime_lock); + + do { + timer_tick(regs); + next_match = __raw_readl(MXC_GPT_TCMP_TICK) + LATCH; + __raw_writel(GPT_TSTAT_COMP, MXC_GPT_TSTAT_TICK); + __raw_writel(next_match, MXC_GPT_TCMP_TICK); + } while ((signed long)(next_match - __raw_readl(MXC_GPT_TCN_TICK)) <= + 0); + + write_sequnlock(&xtime_lock); + + return IRQ_HANDLED; +} + +/*! + * This function is used to obtain the number of microseconds since the last + * timer interrupt. Note that interrupts is disabled by do_gettimeofday(). + * + * @return the number of microseconds since the last timer interrupt. + */ +static unsigned long __noinstrument mxc_gettimeoffset(void) +{ + long ticks_to_match, elapsed, usec; + + /* Get ticks before next timer match */ + ticks_to_match = + __raw_readl(MXC_GPT_TCMP_TICK) - __raw_readl(MXC_GPT_TCN_TICK); + + /* We need elapsed ticks since last match */ + elapsed = LATCH - ticks_to_match; + + /* Now convert them to usec */ + usec = (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH; + + return usec; +} + +/*! + * The OS tick timer interrupt structure. + */ +static struct irqaction timer_irq = { + .name = "MXC Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = mxc_timer_interrupt +}; + +/*! + * This function is used to initialize the GPT to produce an interrupt + * every 10 msec. It is called by the start_kernel() during system startup. + */ +void __init mxc_init_time(void) +{ + u32 reg, v; + + mxc_clks_enable(MXC_GPT_CLOCK_TICK); + __raw_writel(0, MXC_GPT_TCTL_TICK); + __raw_writel(GPT_TCTL_SWR, MXC_GPT_TCTL_TICK); + + while ((__raw_readl(MXC_GPT_TCTL_TICK) & GPT_TCTL_SWR) != 0) + mb(); + + reg = GPT_TCTL_FRR | GPT_TCTL_COMPEN | GPT_TCTL_SRC_PER1; + + __raw_writel(reg, MXC_GPT_TCTL_TICK); + + v = mxc_get_clocks(MXC_GPT_CLOCK_TICK); + __raw_writel((v / CLOCK_TICK_RATE) - 1, MXC_GPT_TPRER_TICK); + + if ((v % CLOCK_TICK_RATE) != 0) { + pr_info("\nWARNING: Can't generate CLOCK_TICK_RATE at %d Hz\n", + CLOCK_TICK_RATE); + } + pr_info("Actual CLOCK_TICK_RATE is %d Hz\n", + v / ((__raw_readl(MXC_GPT_TPRER_TICK) & 0x7FF) + 1)); + + reg = __raw_readl(MXC_GPT_TCN_TICK); + reg += LATCH; + __raw_writel(reg, MXC_GPT_TCMP_TICK); + + setup_irq(MXC_GPT_INT_TICK, &timer_irq); + + reg = __raw_readl(MXC_GPT_TCTL_TICK) | GPT_TCTL_TEN; + __raw_writel(reg, MXC_GPT_TCTL_TICK); + +#ifdef CONFIG_KFI + os_timer_initialized = 1; +#endif +} + +struct sys_timer mxc_timer = { + .init = mxc_init_time, + .offset = mxc_gettimeoffset, +}; diff -urN linux-2.6.26/arch/arm/mach-mx27/Kconfig linux-2.6.26-lab126/arch/arm/mach-mx27/Kconfig --- linux-2.6.26/arch/arm/mach-mx27/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/Kconfig 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,43 @@ +menu "MX27 Options" + depends on ARCH_MX27 + +config MX27_OPTIONS + bool + default y + select CPU_ARM926T + select MXC_EMMA + select USB_ARCH_HAS_EHCI + +config MACH_MX27ADS + bool "Support MX27ADS platforms" + default y + help + Include support for MX27ADS platform. This includes specific + configurations for the board and its peripherals. + +config ARCH_MXC_HAS_NFC_V1 + bool "MXC NFC Hardware Version 1" + default y + help + This selects the Freescale MXC Nand Flash Controller Hardware Version 1 + If unsure, say N. + +menu "Device options" + +config I2C_MXC_SELECT1 + bool "Enable I2C1 module" + default y + depends on I2C_MXC + help + Enable MX31 I2C1 module. + +config I2C_MXC_SELECT2 + bool "Enable I2C2 module" + default n + depends on I2C_MXC + help + Enable MX31 I2C2 module. + +endmenu + +endmenu diff -urN linux-2.6.26/arch/arm/mach-mx27/Makefile linux-2.6.26-lab126/arch/arm/mach-mx27/Makefile --- linux-2.6.26/arch/arm/mach-mx27/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/Makefile 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,18 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. + +obj-y := mm.o time.o dma.o gpio_mux.o clock.o devices.o serial.o system.o cpu.o dptc.o +obj-$(CONFIG_MACH_MX27ADS) += mx27ads.o mx27ads_gpio.o + +# power management +obj-$(CONFIG_PM) += pm.o mxc_pm.o + +obj-$(CONFIG_USB_EHCI_ARC_H1) += usb_h1.o +obj-$(CONFIG_USB_EHCI_ARC_H2) += usb_h2.o + +ifneq ($(strip $(CONFIG_USB_GADGET_ARC) $(CONFIG_USB_EHCI_ARC_OTG)),) + obj-y += usb_dr.o +endif diff -urN linux-2.6.26/arch/arm/mach-mx27/Makefile.boot linux-2.6.26-lab126/arch/arm/mach-mx27/Makefile.boot --- linux-2.6.26/arch/arm/mach-mx27/Makefile.boot 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/Makefile.boot 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,3 @@ + zreladdr-y := 0xA0008000 +params_phys-y := 0xA0000100 +initrd_phys-y := 0xA0800000 diff -urN linux-2.6.26/arch/arm/mach-mx27/board-mx27ads.h linux-2.6.26-lab126/arch/arm/mach-mx27/board-mx27ads.h --- linux-2.6.26/arch/arm/mach-mx27/board-mx27ads.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/board-mx27ads.h 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,385 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__ +#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__ + +/*! + * @defgroup BRDCFG_MX27 Board Configuration Options + * @ingroup MSL_MX27 + */ + +/*! + * @file mach-mx27/board-mx27ads.h + * + * @brief This file contains all the board level configuration options. + * + * It currently hold the options defined for MX27 ADS Platform. + * + * @ingroup BRDCFG_MX27 + */ + +/* + * Include Files + */ +#include + +/*! + * @name MXC UART EVB board level configurations + */ +/*! @{ */ +/*! + * Specifies if the Irda transmit path is inverting + */ +#define MXC_IRDA_TX_INV 0 +/*! + * Specifies if the Irda receive path is inverting + */ +#define MXC_IRDA_RX_INV 0 +/* UART 1 configuration */ +/*! + * This define specifies if the UART port is configured to be in DTE or + * DCE mode. There exists a define like this for each UART port. Valid + * values that can be used are \b MODE_DTE or \b MODE_DCE. + */ +#define UART1_MODE MODE_DCE +/*! + * This define specifies if the UART is to be used for IRDA. There exists a + * define like this for each UART port. Valid values that can be used are + * \b IRDA or \b NO_IRDA. + */ +#define UART1_IR NO_IRDA +/*! + * This define is used to enable or disable a particular UART port. If + * disabled, the UART will not be registered in the file system and the user + * will not be able to access it. There exists a define like this for each UART + * port. Specify a value of 1 to enable the UART and 0 to disable it. + */ +#define UART1_ENABLED 1 +/*! @} */ +/* UART 2 configuration */ +#define UART2_MODE MODE_DCE +#define UART2_IR NO_IRDA +#define UART2_ENABLED 1 +/* UART 3 configuration */ +#define UART3_MODE MODE_DCE +#define UART3_IR IRDA +#define UART3_ENABLED 1 +/* UART 4 configuration */ +#define UART4_MODE MODE_DTE +#define UART4_IR NO_IRDA +#define UART4_ENABLED 0 /* Disable UART 4 as its pins are shared with ATA */ +/* UART 5 configuration */ +#define UART5_MODE MODE_DTE +#define UART5_IR NO_IRDA +#define UART5_ENABLED 1 +/* UART 6 configuration */ +#define UART6_MODE MODE_DTE +#define UART6_IR NO_IRDA +#define UART6_ENABLED 1 + +#define MXC_LL_EXTUART_PADDR (CS4_BASE_ADDR + 0x20000) +#define MXC_LL_EXTUART_VADDR (CS4_BASE_ADDR_VIRT + 0x20000) +#define MXC_LL_EXTUART_16BIT_BUS + +#define MXC_LL_UART_PADDR UART1_BASE_ADDR +#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR) + +/*! + * @name PBC Controller parameters + */ +/*! @{ */ +/*! + * Base address of PBC controller, CS4 + */ +#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) +#define PBC_REG_ADDR(offset) (PBC_BASE_ADDRESS + (offset)) + +/*! + * PBC Interupt name definitions + */ +#define PBC_GPIO1_0 0 +#define PBC_GPIO1_1 1 +#define PBC_GPIO1_2 2 +#define PBC_GPIO1_3 3 +#define PBC_GPIO1_4 4 +#define PBC_GPIO1_5 5 + +#define PBC_INTR_MAX_NUM 6 +#define PBC_INTR_SHARED_MAX_NUM 8 + +/* When the PBC address connection is fixed in h/w, defined as 1 */ +#define PBC_ADDR_SH 0 + +/* Offsets for the PBC Controller register */ +/*! + * PBC Board version register offset + */ +#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH) +/*! + * PBC Board control register 1 set address. + */ +#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH) +/*! + * PBC Board control register 1 clear address. + */ +#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH) +/*! + * PBC Board control register 2 set address. + */ +#define PBC_BCTRL2_SET_REG PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH) +/*! + * PBC Board control register 2 clear address. + */ +#define PBC_BCTRL2_CLEAR_REG PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH) +/*! + * PBC Board control register 3 set address. + */ +#define PBC_BCTRL3_SET_REG PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH) +/*! + * PBC Board control register 3 clear address. + */ +#define PBC_BCTRL3_CLEAR_REG PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH) +/*! + * PBC Board control register 3 set address. + */ +#define PBC_BCTRL4_SET_REG PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH) +/*! + * PBC Board control register 4 clear address. + */ +#define PBC_BCTRL4_CLEAR_REG PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH) +/*!PBC_ADDR_SH + * PBC Board status register 1. + */ +#define PBC_BSTAT1_REG PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH) +/*! + * PBC Board interrupt status register. + */ +#define PBC_INTSTATUS_REG PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH) +/*! + * PBC Board interrupt current status register. + */ +#define PBC_INTCURR_STATUS_REG PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH) +/*! + * PBC Interrupt mask register set address. + */ +#define PBC_INTMASK_SET_REG PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH) +/*! + * PBC Interrupt mask register clear address. + */ +#define PBC_INTMASK_CLEAR_REG PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH) +/*! + * External UART A. + */ +#define PBC_SC16C652_UARTA_REG PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH) +/*! + * UART 4 Expanding Signal Status. + */ +#define PBC_UART_STATUS_REG PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH) +/*! + * UART 4 Expanding Signal Control Set. + */ +#define PBC_UCTRL_SET_REG PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH) +/*! + * UART 4 Expanding Signal Control Clear. + */ +#define PBC_UCTRL_CLR_REG PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH) +/*! + * Ethernet Controller IO base address. + */ +#define PBC_CS8900A_IOBASE_REG PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH) +/*! + * Ethernet Controller Memory base address. + */ +#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH) +/*! + * Ethernet Controller DMA base address. + */ +#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH) + +/* PBC Board Version Register bit definition */ +#define PBC_VERSION_ADS 0x8000 /* Bit15=1 means version for ads */ +#define PBC_VERSION_EVB_REVB 0x4000 /* BIT14=1 means version for evb revb */ + +/* PBC Board Control Register 1 bit definitions */ +#define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */ +#define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */ +#define PBC_BCTRL1_FRST 0x0004 /* FEC Reset */ +#define PBC_BCTRL1_ESLEEP 0x0010 /* Enable ethernet Sleep */ +#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */ + +/* PBC Board Control Register 2 bit definitions */ +#define PBC_BCTRL2_VCC_EN 0x0004 /* Enable VCC */ +#define PBC_BCTRL2_VPP_EN 0x0008 /* Enable Vpp */ +#define PBC_BCTRL2_ATAFEC_EN 0X0010 +#define PBC_BCTRL2_ATAFEC_SEL 0X0020 +#define PBC_BCTRL2_ATA_EN 0X0040 +#define PBC_BCTRL2_IRDA_SD 0X0080 +#define PBC_BCTRL2_IRDA_EN 0X0100 +#define PBC_BCTRL2_CCTL10 0X0200 +#define PBC_BCTRL2_CCTL11 0X0400 + +/* PBC Board Control Register 3 bit definitions */ +#define PBC_BCTRL3_HSH_EN 0X0020 +#define PBC_BCTRL3_FSH_MOD 0X0040 +#define PBC_BCTRL3_OTG_HS_EN 0X0080 +#define PBC_BCTRL3_OTG_VBUS_EN 0X0100 +#define PBC_BCTRL3_FSH_VBUS_EN 0X0200 +#define PBC_BCTRL3_USB_OTG_ON 0X0800 +#define PBC_BCTRL3_USB_FSH_ON 0X1000 + +/* PBC Board Control Register 4 bit definitions */ +#define PBC_BCTRL4_REGEN_SEL 0X0001 +#define PBC_BCTRL4_USER_OFF 0X0002 +#define PBC_BCTRL4_VIB_EN 0X0004 +#define PBC_BCTRL4_PWRGT1_EN 0X0008 +#define PBC_BCTRL4_PWRGT2_EN 0X0010 +#define PBC_BCTRL4_STDBY_PRI 0X0020 + +#ifndef __ASSEMBLY__ +/*! + * Enumerations for SD cards and memory stick card. This corresponds to + * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN. + */ +enum mxc_card_no { + MXC_CARD_SD2 = 0, + MXC_CARD_SD3, + MXC_CARD_MS, + MXC_CARD_SD1, + MXC_CARD_MIN = MXC_CARD_SD2, + MXC_CARD_MAX = MXC_CARD_SD1, +}; +#endif + +#define MXC_CPLD_VER_1_50 0x01 + +/*! + * PBC BSTAT Register bit definitions + */ +#define PBC_BSTAT_PRI_INT 0X0001 +#define PBC_BSTAT_USB_BYP 0X0002 +#define PBC_BSTAT_ATA_IOCS16 0X0004 +#define PBC_BSTAT_ATA_CBLID 0X0008 +#define PBC_BSTAT_ATA_DASP 0X0010 +#define PBC_BSTAT_PWR_RDY 0X0020 +#define PBC_BSTAT_SD3_WP 0X0100 +#define PBC_BSTAT_SD2_WP 0X0200 +#define PBC_BSTAT_SD1_WP 0X0400 +#define PBC_BSTAT_SD3_DET 0X0800 +#define PBC_BSTAT_SD2_DET 0X1000 +#define PBC_BSTAT_SD1_DET 0X2000 +#define PBC_BSTAT_MS_DET 0X4000 +#define PBC_BSTAT_SD3_DET_BIT 11 +#define PBC_BSTAT_SD2_DET_BIT 12 +#define PBC_BSTAT_SD1_DET_BIT 13 +#define PBC_BSTAT_MS_DET_BIT 14 +#define MXC_BSTAT_BIT(n) ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \ + ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \ + ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \ + ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : 0x0)))) + +/*! + * PBC UART Control Register bit definitions + */ +#define PBC_UCTRL_DCE_DCD 0X0001 +#define PBC_UCTRL_DCE_DSR 0X0002 +#define PBC_UCTRL_DCE_RI 0X0004 +#define PBC_UCTRL_DTE_DTR 0X0100 + +/*! + * PBC UART Status Register bit definitions + */ +#define PBC_USTAT_DTE_DCD 0X0001 +#define PBC_USTAT_DTE_DSR 0X0002 +#define PBC_USTAT_DTE_RI 0X0004 +#define PBC_USTAT_DCE_DTR 0X0100 + +/*! + * PBC Interupt mask register bit definitions + */ +#define PBC_INTR_SD3_R_EN_BIT 4 +#define PBC_INTR_SD2_R_EN_BIT 0 +#define PBC_INTR_SD1_R_EN_BIT 6 +#define PBC_INTR_MS_R_EN_BIT 5 +#define PBC_INTR_SD3_EN_BIT 13 +#define PBC_INTR_SD2_EN_BIT 12 +#define PBC_INTR_MS_EN_BIT 14 +#define PBC_INTR_SD1_EN_BIT 15 + +#define PBC_INTR_SD2_R_EN 0x0001 +#define PBC_INTR_LOW_BAT 0X0002 +#define PBC_INTR_OTG_FSOVER 0X0004 +#define PBC_INTR_FSH_OVER 0X0008 +#define PBC_INTR_SD3_R_EN 0x0010 +#define PBC_INTR_MS_R_EN 0x0020 +#define PBC_INTR_SD1_R_EN 0x0040 +#define PBC_INTR_FEC_INT 0X0080 +#define PBC_INTR_ENET_INT 0X0100 +#define PBC_INTR_OTGFS_INT 0X0200 +#define PBC_INTR_XUART_INT 0X0400 +#define PBC_INTR_CCTL12 0X0800 +#define PBC_INTR_SD2_EN 0x1000 +#define PBC_INTR_SD3_EN 0x2000 +#define PBC_INTR_MS_EN 0x4000 +#define PBC_INTR_SD1_EN 0x8000 + +/*! @} */ + +#define CKIH_27MHZ_BIT_SET (1 << 3) + +/* For interrupts like xuart, enet etc */ +#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX27_PIN_TIN) + +/* + * This corresponds to PBC_INTMASK_SET_REG at offset 0x38. + * + */ +#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 1) +#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2) +#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3) +#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4) +#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5) +#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6) +#define EXPIO_INT_FEC (MXC_EXP_IO_BASE + 7) +#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8) +#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9) +#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) +#define EXPIO_INT_CCTL12_INT (MXC_EXP_IO_BASE + 11) +#define EXPIO_INT_SD2_EN (MXC_EXP_IO_BASE + 12) +#define EXPIO_INT_SD3_EN (MXC_EXP_IO_BASE + 13) +#define EXPIO_INT_MS_EN (MXC_EXP_IO_BASE + 14) +#define EXPIO_INT_SD1_EN (MXC_EXP_IO_BASE + 15) + +/*! This is System IRQ used by CS8900A for interrupt generation taken from platform.h */ +#define CS8900AIRQ EXPIO_INT_ENET_INT +/*! This is I/O Base address used to access registers of CS8900A on MXC ADS */ +#define CS8900A_BASE_ADDRESS (PBC_CS8900A_IOBASE_REG + 0x300) + +#define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX27_PIN_TOUT) + +/*! +* This is used to detect if the CPLD version is for mx27 evb board rev-a +*/ +#define PBC_CPLD_VERSION_IS_REVA() \ + ((__raw_readw(PBC_VERSION_REG) & \ + (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\ + == 0) + +#define MXC_BD_LED1 (1 << 5) +#define MXC_BD_LED2 (1 << 6) +#define MXC_BD_LED_ON(led) \ + __raw_writew(led, PBC_BCTRL1_SET_REG) +#define MXC_BD_LED_OFF(led) \ + __raw_writew(led, PBC_BCTRL1_CLEAR_REG) + +#endif /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx27/clock.c linux-2.6.26-lab126/arch/arm/mach-mx27/clock.c --- linux-2.6.26/arch/arm/mach-mx27/clock.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/clock.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,1549 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include "crm_regs.h" + +#define CKIH_CLK_FREQ 26000000 /* 26M reference clk */ +#define CKIH_CLK_FREQ_27MHZ 27000000 +#define CKIL_CLK_FREQ 32768 /* 32.768k oscillator in */ + +static struct clk ckil_clk; +static struct clk mpll_clk; +static struct clk mpll_main_clk[]; +static struct clk spll_clk; + +static int _clk_enable(struct clk *clk) +{ + unsigned long reg; + + reg = __raw_readl(clk->enable_reg); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + return 0; +} + +static void _clk_disable(struct clk *clk) +{ + unsigned long reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(1 << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); +} + +static int _clk_spll_enable(struct clk *clk) +{ + unsigned long reg; + + reg = __raw_readl(CCM_CSCR); + reg |= CCM_CSCR_SPEN; + __raw_writel(reg, CCM_CSCR); + + while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0) ; + + return 0; +} + +static void _clk_spll_disable(struct clk *clk) +{ + unsigned long reg; + + reg = __raw_readl(CCM_CSCR); + reg &= ~CCM_CSCR_SPEN; + __raw_writel(reg, CCM_CSCR); +} + +static void _clk_pccr01_enable(unsigned long mask0, unsigned long mask1) +{ + unsigned long reg; + + reg = __raw_readl(CCM_PCCR0); + reg |= mask0; + __raw_writel(reg, CCM_PCCR0); + + reg = __raw_readl(CCM_PCCR1); + reg |= mask1; + __raw_writel(reg, CCM_PCCR1); + +} + +static void _clk_pccr01_disable(unsigned long mask0, unsigned long mask1) +{ + unsigned long reg; + + reg = __raw_readl(CCM_PCCR0); + reg &= ~mask0; + __raw_writel(reg, CCM_PCCR0); + + reg = __raw_readl(CCM_PCCR1); + reg &= ~mask1; + __raw_writel(reg, CCM_PCCR1); +} + +static void _clk_pccr10_enable(unsigned long mask1, unsigned long mask0) +{ + unsigned long reg; + + reg = __raw_readl(CCM_PCCR1); + reg |= mask1; + __raw_writel(reg, CCM_PCCR1); + + reg = __raw_readl(CCM_PCCR0); + reg |= mask0; + __raw_writel(reg, CCM_PCCR0); +} + +static void _clk_pccr10_disable(unsigned long mask1, unsigned long mask0) +{ + unsigned long reg; + + reg = __raw_readl(CCM_PCCR1); + reg &= ~mask1; + __raw_writel(reg, CCM_PCCR1); + + reg = __raw_readl(CCM_PCCR0); + reg &= ~mask0; + __raw_writel(reg, CCM_PCCR0); +} + +static int _clk_dma_enable(struct clk *clk) +{ + _clk_pccr01_enable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK); + + return 0; +} + +static void _clk_dma_disable(struct clk *clk) +{ + _clk_pccr01_disable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK); +} + +static int _clk_rtic_enable(struct clk *clk) +{ + _clk_pccr01_enable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK); + + return 0; +} + +static void _clk_rtic_disable(struct clk *clk) +{ + _clk_pccr01_disable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK); +} + +static int _clk_emma_enable(struct clk *clk) +{ + _clk_pccr01_enable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK); + + return 0; +} + +static void _clk_emma_disable(struct clk *clk) +{ + _clk_pccr01_disable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK); +} + +static int _clk_slcdc_enable(struct clk *clk) +{ + _clk_pccr01_enable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK); + + return 0; +} + +static void _clk_slcdc_disable(struct clk *clk) +{ + _clk_pccr01_disable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK); +} + +static int _clk_fec_enable(struct clk *clk) +{ + _clk_pccr01_enable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK); + + return 0; +} + +static void _clk_fec_disable(struct clk *clk) +{ + _clk_pccr01_disable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK); +} + +static int _clk_vpu_enable(struct clk *clk) +{ + unsigned long reg; + + reg = __raw_readl(CCM_PCCR1); + reg |= CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK; + __raw_writel(reg, CCM_PCCR1); + + return 0; +} + +static void _clk_vpu_disable(struct clk *clk) +{ + unsigned long reg; + + reg = __raw_readl(CCM_PCCR1); + reg &= ~(CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK); + __raw_writel(reg, CCM_PCCR1); +} + +static int _clk_sahara2_enable(struct clk *clk) +{ + _clk_pccr01_enable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK); + + return 0; +} + +static void _clk_sahara2_disable(struct clk *clk) +{ + _clk_pccr01_disable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK); +} + +static int _clk_mstick1_enable(struct clk *clk) +{ + _clk_pccr10_enable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK); + + return 0; +} + +static void _clk_mstick1_disable(struct clk *clk) +{ + _clk_pccr10_disable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK); +} + +#define CSCR() (__raw_readl(CCM_CSCR)) +#define PCDR0() (__raw_readl(CCM_PCDR0)) +#define PCDR1() (__raw_readl(CCM_PCDR1)) + +static void _clk_pll_recalc(struct clk *clk) +{ + unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0; + unsigned long ref_clk; + unsigned long reg; + unsigned long long temp; + + ref_clk = clk->parent->rate; + if (clk->parent == &ckil_clk) { + ref_clk *= 1024; + } + + if (clk == &mpll_clk) { + reg = __raw_readl(CCM_MPCTL0); + pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET; + mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET; + mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET; + mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET; + } else if (clk == &spll_clk) { + reg = __raw_readl(CCM_SPCTL0); + /*TODO: This is TO2 Bug */ + if (cpu_is_mx27_rev(CHIP_REV_2_0) == 1) { + __raw_writel(reg, CCM_SPCTL0); + } + pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET; + mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET; + mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET; + mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET; + } else { + BUG(); /* oops */ + } + + mfi = (mfi <= 5) ? 5 : mfi; + temp = 2LL * ref_clk * mfn; + do_div(temp, mfd + 1); + temp = 2LL * ref_clk * mfi + temp; + do_div(temp, pdf + 1); + + clk->rate = temp; +} + +static void _clk_mpll_main_recalc(struct clk *clk) +{ + /* i.MX27 TO2: + * clk->id == 0: arm clock source path 1 which is from 2*MPLL/DIV_2 + * clk->id == 1: arm clock source path 2 which is from 2*MPLL/DIV_3 + */ + switch (clk->id) { + case 0: + clk->rate = clk->parent->rate; + break; + case 1: + clk->rate = 2 * clk->parent->rate / 3; + } +} + +static int _clk_cpu_set_parent(struct clk *clk, struct clk *parent) +{ + int cscr = CSCR(); + + if (clk->parent == parent) + return 0; + + if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) { + if (parent == &mpll_main_clk[0]) { + cscr |= CCM_CSCR_ARM_SRC; + } else { + if (parent == &mpll_main_clk[1]) { + cscr &= ~CCM_CSCR_ARM_SRC; + } else { + return -EINVAL; + } + } + __raw_writel(CCM_CSCR, cscr); + } else { + return -ENODEV; + } + clk->parent = parent; + return 0; +} + +static unsigned long _clk_cpu_round_rate(struct clk *clk, unsigned long rate) +{ + int div; + div = clk->parent->rate / rate; + if (clk->parent->rate % rate) { + div++; + } + + if (div > 4) { + div = 4; + } + return clk->parent->rate / div; +} + +static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate) +{ + int div, reg; + div = clk->parent->rate / rate; + + if (div > 4 || div < 1 || ((clk->parent->rate / div) != rate)) { + return -EINVAL; + } + div--; + + reg = (CSCR() & ~CCM_CSCR_ARM_MASK) | (div << CCM_CSCR_ARM_OFFSET); + __raw_writel(CCM_CSCR, reg); + clk->rate = rate; + return 0; +} + +static void _clk_cpu_recalc(struct clk *clk) +{ + unsigned long div; + + if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) { + div = (CSCR() & CCM_CSCR_ARM_MASK) >> CCM_CSCR_ARM_OFFSET; + } else { + div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET; + } + + clk->rate = clk->parent->rate / (div + 1); +} + +static void _clk_ahb_recalc(struct clk *clk) +{ + unsigned long bclk_pdf; + + if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) { + bclk_pdf = (CSCR() & CCM_CSCR_AHB_MASK) >> CCM_CSCR_AHB_OFFSET; + } else { + bclk_pdf = + (CSCR() & CCM_CSCR_BCLK_MASK) >> CCM_CSCR_BCLK_OFFSET; + } + clk->rate = clk->parent->rate / (bclk_pdf + 1); +} + +static void _clk_perclkx_recalc(struct clk *clk) +{ + unsigned long perclk_pdf; + + if (clk->id < 0 || clk->id > 3) + return; + + perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK; + + clk->rate = clk->parent->rate / (perclk_pdf + 1); +} + +static unsigned long _clk_perclkx_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + if (clk->parent->rate % rate) + div++; + + if (div > 64) { + div = 64; + } + + return clk->parent->rate / div; +} + +static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + + if (clk->id < 0 || clk->id > 3) + return -EINVAL; + + div = clk->parent->rate / rate; + if (div > 64 || div < 1 || ((clk->parent->rate / div) != rate)) { + return -EINVAL; + } + div--; + + reg = + __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK << + (clk->id << 3)); + reg |= div << (clk->id << 3); + __raw_writel(reg, CCM_PCDR1); + + clk->rate = rate; + + return 0; +} + +static void _clk_usb_recalc(struct clk *clk) +{ + unsigned long usb_pdf; + + usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET; + + clk->rate = clk->parent->rate / (usb_pdf + 1); +} + +static void _clk_ssi1_recalc(struct clk *clk) +{ + unsigned long ssi1_pdf; + + ssi1_pdf = (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK) >> + CCM_PCDR0_SSI1BAUDDIV_OFFSET; + + if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) { + ssi1_pdf += 4; + } else { + ssi1_pdf = (ssi1_pdf < 2) ? 124 : ssi1_pdf; + } + + clk->rate = 2 * clk->parent->rate / ssi1_pdf; +} + +static void _clk_ssi2_recalc(struct clk *clk) +{ + unsigned long ssi2_pdf; + + ssi2_pdf = (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >> + CCM_PCDR0_SSI2BAUDDIV_OFFSET; + + if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) { + ssi2_pdf += 4; + } else { + ssi2_pdf = (ssi2_pdf < 2) ? 124 : ssi2_pdf; + } + + clk->rate = 2 * clk->parent->rate / ssi2_pdf; +} + +static void _clk_nfc_recalc(struct clk *clk) +{ + unsigned long nfc_pdf; + + if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) { + nfc_pdf = + (PCDR0() & CCM_PCDR0_NFCDIV2_MASK) >> + CCM_PCDR0_NFCDIV2_OFFSET; + } else { + nfc_pdf = + (PCDR0() & CCM_PCDR0_NFCDIV_MASK) >> + CCM_PCDR0_NFCDIV_OFFSET; + } + + clk->rate = clk->parent->rate / (nfc_pdf + 1); +} + +static void _clk_vpu_recalc(struct clk *clk) +{ + unsigned long vpu_pdf; + + if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) { + vpu_pdf = + (PCDR0() & CCM_PCDR0_VPUDIV2_MASK) >> + CCM_PCDR0_VPUDIV2_OFFSET; + vpu_pdf += 4; + } else { + vpu_pdf = + (PCDR0() & CCM_PCDR0_VPUDIV_MASK) >> + CCM_PCDR0_VPUDIV_OFFSET; + vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf; + } + clk->rate = 2 * clk->parent->rate / vpu_pdf; +} + +static void _clk_ipg_recalc(struct clk *clk) +{ + unsigned long ipg_pdf; + + if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) { + ipg_pdf = 1; + } else { + ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET; + } + + clk->rate = clk->parent->rate / (ipg_pdf + 1); +} + +static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate) +{ + return clk->parent->round_rate(clk->parent, rate); +} + +static int _clk_parent_set_rate(struct clk *clk, unsigned long rate) +{ + int ret; + if ((ret = clk->parent->set_rate(clk->parent, rate)) == 0) + clk->rate = rate; + return ret; +} + +static struct clk ckih_clk = { + .name = "ckih", + .rate = 0, /* determined at boot time (26 or 27 MHz) */ + .flags = RATE_PROPAGATES, +}; + +static struct clk ckil_clk = { + .name = "ckil", + .rate = CKIL_CLK_FREQ, + .flags = RATE_PROPAGATES, +}; + +static struct clk mpll_clk = { + .name = "mpll", + .parent = &ckih_clk, + .recalc = _clk_pll_recalc, + .flags = RATE_PROPAGATES, +}; + +static struct clk mpll_main_clk[] = { + { + /* For i.MX27 TO2, it is the MPLL path 1 of ARM core + * It provide the clock source whose rate is same as MPLL + */ + .name = "mpll_main", + .id = 0, + .parent = &mpll_clk, + .recalc = _clk_mpll_main_recalc,}, + { + /* For i.MX27 TO2, it is the MPLL path 1 of ARM core + * It provide the clock source whose rate is same as MPLL + */ + .name = "mpll_main", + .id = 1, + .parent = &mpll_clk, + .recalc = _clk_mpll_main_recalc,} +}; + +static struct clk spll_clk = { + .name = "spll", + .parent = &ckih_clk, + .recalc = _clk_pll_recalc, + .enable = _clk_spll_enable, + .disable = _clk_spll_disable, + .flags = RATE_PROPAGATES, +}; + +static struct clk cpu_clk = { + .name = "cpu_clk", + .parent = &mpll_main_clk[1], + .set_parent = _clk_cpu_set_parent, + .round_rate = _clk_cpu_round_rate, + .set_rate = _clk_cpu_set_rate, + .recalc = _clk_cpu_recalc, + .flags = RATE_PROPAGATES, +}; + +static struct clk ahb_clk = { + .name = "ahb_clk", + .parent = &mpll_main_clk[1], + .recalc = _clk_ahb_recalc, + .flags = RATE_PROPAGATES, +}; + +static struct clk ipg_clk = { + .name = "ipg_clk", + .parent = &ahb_clk, + .recalc = _clk_ipg_recalc, + .flags = RATE_PROPAGATES, +}; + +static struct clk per_clk[] = { + { + .name = "per_clk", + .id = 0, + .parent = &mpll_main_clk[1], + .recalc = _clk_perclkx_recalc, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_PERCLK1_OFFSET, + .disable = _clk_disable, + .flags = RATE_PROPAGATES,}, + { + .name = "per_clk", + .id = 1, + .parent = &mpll_main_clk[1], + .recalc = _clk_perclkx_recalc, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_PERCLK2_OFFSET, + .disable = _clk_disable, + .flags = RATE_PROPAGATES,}, + { + .name = "per_clk", + .id = 2, + .parent = &mpll_main_clk[1], + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .recalc = _clk_perclkx_recalc, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_PERCLK3_OFFSET, + .disable = _clk_disable, + .flags = RATE_PROPAGATES,}, + { + .name = "per_clk", + .id = 3, + .parent = &mpll_main_clk[1], + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .recalc = _clk_perclkx_recalc, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_PERCLK4_OFFSET, + .disable = _clk_disable, + .flags = RATE_PROPAGATES,}, +}; + +struct clk uart1_clk[] = { + { + .name = "uart_clk", + .id = 0, + .parent = &per_clk[0], + .secondary = &uart1_clk[1],}, + { + .name = "uart_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_UART1_OFFSET, + .disable = _clk_disable,}, +}; + +struct clk uart2_clk[] = { + { + .name = "uart_clk", + .id = 1, + .parent = &per_clk[0], + .secondary = &uart2_clk[1],}, + { + .name = "uart_ipg_clk", + .id = 1, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_UART2_OFFSET, + .disable = _clk_disable,}, +}; + +struct clk uart3_clk[] = { + { + .name = "uart_clk", + .id = 2, + .parent = &per_clk[0], + .secondary = &uart3_clk[1],}, + { + .name = "uart_ipg_clk", + .id = 2, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_UART3_OFFSET, + .disable = _clk_disable,}, +}; + +struct clk uart4_clk[] = { + { + .name = "uart_clk", + .id = 3, + .parent = &per_clk[0], + .secondary = &uart4_clk[1],}, + { + .name = "uart_ipg_clk", + .id = 3, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_UART4_OFFSET, + .disable = _clk_disable,}, +}; + +struct clk uart5_clk[] = { + { + .name = "uart_clk", + .id = 4, + .parent = &per_clk[0], + .secondary = &uart5_clk[1],}, + { + .name = "uart_ipg_clk", + .id = 4, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_UART5_OFFSET, + .disable = _clk_disable,}, +}; + +struct clk uart6_clk[] = { + { + .name = "uart_clk", + .id = 5, + .parent = &per_clk[0], + .secondary = &uart6_clk[1],}, + { + .name = "uart_ipg_clk", + .id = 5, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_UART6_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk gpt1_clk[] = { + { + .name = "gpt_clk", + .id = 0, + .parent = &per_clk[0], + .secondary = &gpt1_clk[1],}, + { + .name = "gpt_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_GPT1_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk gpt2_clk[] = { + { + .name = "gpt_clk", + .id = 1, + .parent = &per_clk[0], + .secondary = &gpt2_clk[1],}, + { + .name = "gpt_ipg_clk", + .id = 1, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_GPT2_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk gpt3_clk[] = { + { + .name = "gpt_clk", + .id = 2, + .parent = &per_clk[0], + .secondary = &gpt3_clk[1],}, + { + .name = "gpt_ipg_clk", + .id = 2, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_GPT3_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk gpt4_clk[] = { + { + .name = "gpt_clk", + .id = 3, + .parent = &per_clk[0], + .secondary = &gpt4_clk[1],}, + { + .name = "gpt_ipg_clk", + .id = 3, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_GPT4_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk gpt5_clk[] = { + { + .name = "gpt_clk", + .id = 4, + .parent = &per_clk[0], + .secondary = &gpt5_clk[1],}, + { + .name = "gpt_ipg_clk", + .id = 4, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_GPT5_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk gpt6_clk[] = { + { + .name = "gpt_clk", + .id = 5, + .parent = &per_clk[0], + .secondary = &gpt6_clk[1],}, + { + .name = "gpt_ipg_clk", + .id = 5, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_GPT6_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk pwm_clk[] = { + { + .name = "pwm_clk", + .parent = &per_clk[0], + .secondary = &pwm_clk[1],}, + { + .name = "pwm_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_PWM_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk sdhc1_clk[] = { + { + .name = "sdhc_clk", + .id = 0, + .parent = &per_clk[1], + .secondary = &sdhc1_clk[1],}, + { + .name = "sdhc_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_SDHC1_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk sdhc2_clk[] = { + { + .name = "sdhc_clk", + .id = 1, + .parent = &per_clk[1], + .secondary = &sdhc2_clk[1],}, + { + .name = "sdhc_ipg_clk", + .id = 1, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_SDHC2_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk sdhc3_clk[] = { + { + .name = "sdhc_clk", + .id = 2, + .parent = &per_clk[1], + .secondary = &sdhc3_clk[1],}, + { + .name = "sdhc_ipg_clk", + .id = 2, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_SDHC3_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk cspi1_clk[] = { + { + .name = "cspi_clk", + .id = 0, + .parent = &per_clk[1], + .secondary = &cspi1_clk[1],}, + { + .name = "cspi_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_CSPI1_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk cspi2_clk[] = { + { + .name = "cspi_clk", + .id = 1, + .parent = &per_clk[1], + .secondary = &cspi2_clk[1],}, + { + .name = "cspi_ipg_clk", + .id = 1, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_CSPI2_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk cspi3_clk[] = { + { + .name = "cspi_clk", + .id = 2, + .parent = &per_clk[1], + .secondary = &cspi3_clk[1],}, + { + .name = "cspi_ipg_clk", + .id = 2, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_CSPI3_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk lcdc_clk[] = { + { + .name = "lcdc_clk", + .parent = &per_clk[2], + .secondary = &lcdc_clk[1], + .round_rate = _clk_parent_round_rate, + .set_rate = _clk_parent_set_rate,}, + { + .name = "lcdc_ipg_clk", + .parent = &ipg_clk, + .secondary = &lcdc_clk[2], + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_LCDC_OFFSET, + .disable = _clk_disable,}, + { + .name = "lcdc_ahb_clk", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_HCLK_LCDC_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk csi_clk[] = { + { + .name = "csi_perclk", + .parent = &per_clk[3], + .secondary = &csi_clk[1], + .round_rate = _clk_parent_round_rate, + .set_rate = _clk_parent_set_rate,}, + { + .name = "csi_ahb_clk", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_HCLK_CSI_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk usb_clk[] = { + { + .name = "usb_clk", + .parent = &spll_clk, + .recalc = _clk_usb_recalc, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_USBOTG_OFFSET, + .disable = _clk_disable,}, + { + .name = "usb_ahb_clk", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_HCLK_USBOTG_OFFSET, + .disable = _clk_disable,} +}; + +static struct clk ssi1_clk[] = { + { + .name = "ssi_clk", + .id = 0, + .parent = &mpll_main_clk[1], + .secondary = &ssi1_clk[1], + .recalc = _clk_ssi1_recalc, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_SSI1_BAUD_OFFSET, + .disable = _clk_disable,}, + { + .name = "ssi_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_SSI1_IPG_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk ssi2_clk[] = { + { + .name = "ssi_clk", + .id = 1, + .parent = &mpll_main_clk[1], + .secondary = &ssi2_clk[1], + .recalc = _clk_ssi2_recalc, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_SSI2_BAUD_OFFSET, + .disable = _clk_disable,}, + { + .name = "ssi_ipg_clk", + .id = 1, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_SSI2_IPG_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk nfc_clk = { + .name = "nfc_clk", + .parent = &cpu_clk, + .recalc = _clk_nfc_recalc, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_NFC_BAUD_OFFSET, + .disable = _clk_disable, +}; + +static struct clk vpu_clk = { + .name = "vpu_clk", + .parent = &mpll_main_clk[1], + .recalc = _clk_vpu_recalc, + .enable = _clk_vpu_enable, + .disable = _clk_vpu_disable, +}; + +static struct clk dma_clk = { + .name = "dma_clk", + .parent = &ahb_clk, + .enable = _clk_dma_enable, + .disable = _clk_dma_disable, +}; + +static struct clk rtic_clk = { + .name = "rtic_clk", + .parent = &ahb_clk, + .enable = _clk_rtic_enable, + .disable = _clk_rtic_disable, +}; + +static struct clk brom_clk = { + .name = "brom_clk", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_HCLK_BROM_OFFSET, + .disable = _clk_disable, +}; + +static struct clk emma_clk = { + .name = "emma_clk", + .parent = &ahb_clk, + .enable = _clk_emma_enable, + .disable = _clk_emma_disable, +}; + +static struct clk slcdc_clk = { + .name = "slcdc_clk", + .parent = &ahb_clk, + .enable = _clk_slcdc_enable, + .disable = _clk_slcdc_disable, +}; + +static struct clk fec_clk = { + .name = "fec_clk", + .parent = &ahb_clk, + .enable = _clk_fec_enable, + .disable = _clk_fec_disable, +}; + +static struct clk emi_clk = { + .name = "emi_clk", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_HCLK_EMI_OFFSET, + .disable = _clk_disable, +}; + +static struct clk sahara2_clk = { + .name = "sahara_clk", + .parent = &ahb_clk, + .enable = _clk_sahara2_enable, + .disable = _clk_sahara2_disable, +}; + +static struct clk ata_clk = { + .name = "ata_clk", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_HCLK_ATA_OFFSET, + .disable = _clk_disable, +}; + +static struct clk mstick1_clk = { + .name = "mstick1_clk", + .parent = &ipg_clk, + .enable = _clk_mstick1_enable, + .disable = _clk_mstick1_disable, +}; + +static struct clk wdog_clk = { + .name = "wdog_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR1_WDT_OFFSET, + .disable = _clk_disable, +}; + +static struct clk gpio_clk = { + .name = "gpio_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR1, + .enable_shift = CCM_PCCR0_GPIO_OFFSET, + .disable = _clk_disable, +}; + +static struct clk i2c_clk[] = { + { + .name = "i2c_clk", + .id = 0, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_I2C1_OFFSET, + .disable = _clk_disable,}, + { + .name = "i2c_clk", + .id = 1, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_I2C2_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk iim_clk = { + .name = "iim_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_IIM_OFFSET, + .disable = _clk_disable, +}; + +static struct clk kpp_clk = { + .name = "kpp_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_KPP_OFFSET, + .disable = _clk_disable, +}; + +static struct clk owire_clk = { + .name = "owire_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_OWIRE_OFFSET, + .disable = _clk_disable, +}; + +static struct clk rtc_clk = { + .name = "rtc_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_RTC_OFFSET, + .disable = _clk_disable, +}; + +static struct clk scc_clk = { + .name = "scc_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = CCM_PCCR0, + .enable_shift = CCM_PCCR0_SCC_OFFSET, + .disable = _clk_disable, +}; + +static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + if (clk->parent->rate % rate) + div++; + + if (div > 8) { + div = 8; + } + + return clk->parent->rate / div; +} + +static int _clk_clko_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + + div = clk->parent->rate / rate; + + if (div > 8 || div < 1 || ((clk->parent->rate / div) != rate)) { + return -EINVAL; + } + div--; + + reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKODIV_MASK; + reg |= div << CCM_PCDR0_CLKODIV_OFFSET; + __raw_writel(reg, CCM_PCDR0); + + clk->rate = rate; + + return 0; +} + +static void _clk_clko_recalc(struct clk *clk) +{ + u32 div; + + div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_CLKODIV_MASK >> + CCM_PCDR0_CLKODIV_OFFSET; + div++; + + clk->rate = clk->parent->rate / div; +} + +static int _clk_clko_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK; + + if (parent == &ckil_clk) { + reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET; + } else if (parent == &ckih_clk) { + reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET; + } else if (parent == mpll_clk.parent) { + reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET; + } else if (parent == spll_clk.parent) { + reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET; + } else if (parent == &mpll_clk) { + reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET; + } else if (parent == &spll_clk) { + reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET; + } else if (parent == &cpu_clk) { + reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET; + } else if (parent == &ahb_clk) { + reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET; + } else if (parent == &ipg_clk) { + reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET; + } else if (parent == &per_clk[0]) { + reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET; + } else if (parent == &per_clk[1]) { + reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET; + } else if (parent == &per_clk[2]) { + reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET; + } else if (parent == &per_clk[3]) { + reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET; + } else if (parent == &ssi1_clk[0]) { + reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET; + } else if (parent == &ssi2_clk[0]) { + reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET; + } else if (parent == &nfc_clk) { + reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET; + } else if (parent == &mstick1_clk) { + reg |= 0x11 << CCM_CCSR_CLKOSEL_OFFSET; + } else if (parent == &vpu_clk) { + reg |= 0x12 << CCM_CCSR_CLKOSEL_OFFSET; + } else if (parent == &usb_clk[0]) { + reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET; + } else { + return -EINVAL; + } + + __raw_writel(reg, CCM_CCSR); + + return 0; +} + +static int _clk_clko_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(CCM_PCDR0) | CCM_PCDR0_CLKO_EN; + __raw_writel(reg, CCM_PCDR0); + + return 0; +} + +static void _clk_clko_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKO_EN; + __raw_writel(reg, CCM_PCDR0); +} + +static struct clk clko_clk = { + .name = "clko_clk", + .recalc = _clk_clko_recalc, + .set_rate = _clk_clko_set_rate, + .round_rate = _clk_clko_round_rate, + .set_parent = _clk_clko_set_parent, + .enable = _clk_clko_enable, + .disable = _clk_clko_disable, +}; + +static struct clk *mxc_clks[] = { + &ckih_clk, + &ckil_clk, + &mpll_clk, + &mpll_main_clk[0], + &mpll_main_clk[1], + &spll_clk, + &cpu_clk, + &ahb_clk, + &ipg_clk, + &per_clk[0], + &per_clk[1], + &per_clk[2], + &per_clk[3], + &clko_clk, + &uart1_clk[0], + &uart1_clk[1], + &uart2_clk[0], + &uart2_clk[1], + &uart3_clk[0], + &uart3_clk[1], + &uart4_clk[0], + &uart4_clk[1], + &uart5_clk[0], + &uart5_clk[1], + &uart6_clk[0], + &uart6_clk[1], + &gpt1_clk[0], + &gpt1_clk[1], + &gpt2_clk[0], + &gpt2_clk[1], + &gpt3_clk[0], + &gpt3_clk[1], + &gpt4_clk[0], + &gpt4_clk[1], + &gpt5_clk[0], + &gpt5_clk[1], + &gpt6_clk[0], + &gpt6_clk[1], + &pwm_clk[0], + &pwm_clk[1], + &sdhc1_clk[0], + &sdhc1_clk[1], + &sdhc2_clk[0], + &sdhc2_clk[1], + &sdhc3_clk[0], + &sdhc3_clk[1], + &cspi1_clk[0], + &cspi1_clk[1], + &cspi2_clk[0], + &cspi2_clk[1], + &cspi3_clk[0], + &cspi3_clk[1], + &lcdc_clk[0], + &lcdc_clk[1], + &lcdc_clk[2], + &csi_clk[0], + &csi_clk[1], + &usb_clk[0], + &usb_clk[1], + &ssi1_clk[0], + &ssi1_clk[1], + &ssi2_clk[0], + &ssi2_clk[1], + &nfc_clk, + &vpu_clk, + &dma_clk, + &rtic_clk, + &brom_clk, + &emma_clk, + &slcdc_clk, + &fec_clk, + &emi_clk, + &sahara2_clk, + &ata_clk, + &mstick1_clk, + &wdog_clk, + &gpio_clk, + &i2c_clk[0], + &i2c_clk[1], + &iim_clk, + &kpp_clk, + &owire_clk, + &rtc_clk, + &scc_clk, +}; + +static void probe_mxc_clocks(void) +{ + int i; + + if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) { + if (CSCR() & 0x8000) { + cpu_clk.parent = &mpll_main_clk[0]; + } + + if (!(CSCR() & 0x00800000)) { + ssi2_clk[0].parent = &spll_clk; + } + + if (!(CSCR() & 0x00400000)) { + ssi1_clk[0].parent = &spll_clk; + } + + if (!(CSCR() & 0x00200000)) { + vpu_clk.parent = &spll_clk; + } + } else { + cpu_clk.parent = &mpll_clk; + cpu_clk.set_parent = NULL; + cpu_clk.round_rate = NULL; + cpu_clk.set_rate = NULL; + ahb_clk.parent = &mpll_clk; + + for (i = 0; i < sizeof(per_clk) / sizeof(per_clk[0]); i++) { + per_clk[i].parent = &mpll_clk; + } + + ssi1_clk[0].parent = &mpll_clk; + ssi2_clk[0].parent = &mpll_clk; + + vpu_clk.parent = &mpll_clk; + } +} + +/*! + * Function to get timer clock rate early in boot process before clock tree is + * initialized. + * + * @return Clock rate for timer + */ +unsigned long __init clk_early_get_timer_rate(void) +{ + if (CSCR() & CCM_CSCR_MCU) { + mpll_clk.parent = &ckih_clk; + } else { + mpll_clk.parent = &ckil_clk; + } + + /* Determine which high frequency clock source is coming in */ + ckih_clk.rate = board_get_ckih_rate(); + + probe_mxc_clocks(); + + mpll_clk.recalc(&mpll_clk); + if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) { + mpll_main_clk[0].recalc(&mpll_main_clk[0]); + mpll_main_clk[1].recalc(&mpll_main_clk[1]); + } + per_clk[0].recalc(&per_clk[0]); + per_clk[0].enable(&per_clk[0]); + gpt1_clk[1].enable(&gpt1_clk[1]); + return per_clk[0].rate; +} + +extern void propagate_rate(struct clk *tclk); + +int __init mxc_clocks_init(void) +{ + u32 cscr; + struct clk **clkp; + + for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) { + if (*clkp == &mpll_main_clk[0] || *clkp == &mpll_main_clk[1]) { + if (cpu_is_mx27_rev(CHIP_REV_1_0) == 1) + continue; + } + clk_register(*clkp); + } + + /* Turn off all possible clocks */ + __raw_writel(CCM_PCCR0_GPT1_MASK, CCM_PCCR0); + __raw_writel(CCM_PCCR1_PERCLK1_MASK | CCM_PCCR1_HCLK_EMI_MASK, + CCM_PCCR1); + spll_clk.disable(&spll_clk); + + cscr = CSCR(); + if (cscr & CCM_CSCR_MCU) { + mpll_clk.parent = &ckih_clk; + } else { + mpll_clk.parent = &ckil_clk; + } + if (cscr & CCM_CSCR_SP) { + spll_clk.parent = &ckih_clk; + } else { + spll_clk.parent = &ckil_clk; + } + + pr_info("Clock input source is %ld\n", ckih_clk.rate); + + /* This will propagate to all children and init all the clock rates */ + propagate_rate(&ckih_clk); + propagate_rate(&ckil_clk); + + clk_enable(&emi_clk); + clk_enable(&gpio_clk); + clk_enable(&iim_clk); + clk_enable(&gpt1_clk[0]); + + return 0; +} diff -urN linux-2.6.26/arch/arm/mach-mx27/cpu.c linux-2.6.26-lab126/arch/arm/mach-mx27/cpu.c --- linux-2.6.26/arch/arm/mach-mx27/cpu.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/cpu.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2001 Deep Blue Solutions Ltd. + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +/*! + * @file mach-mx27/cpu.c + * + * @brief This file contains the CPU initialization code. + * + * @ingroup MSL_MX27 + */ + +#include +#include +#include +#include + +/*! + * CPU initialization. It is called by fixup_mxc_board() + */ +void __init mxc_cpu_init(void) +{ + if (!system_rev) { + mxc_set_system_rev(0x27, CHIP_REV_2_0); + } +} diff -urN linux-2.6.26/arch/arm/mach-mx27/crm_regs.h linux-2.6.26-lab126/arch/arm/mach-mx27/crm_regs.h --- linux-2.6.26/arch/arm/mach-mx27/crm_regs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/crm_regs.h 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,283 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ARCH_ARM_MACH_MX27_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MX27_CRM_REGS_H__ + +#include + +#define SYSCTRL_BASE IO_ADDRESS(SYSCTRL_BASE_ADDR) + +/* Register offsets */ +#define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0) +#define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4) +#define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8) +#define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC) +#define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10) +#define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14) +#define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18) +#define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c) +#define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20) +#define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24) +#define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28) +#define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c) +#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30) +#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34) +#define MXC_CCM_PMCR0 (SYSCTRL_BASE + 0x60) +#define MXC_CCM_DCVR0 (SYSCTRL_BASE + 0x64) +#define MXC_CCM_DCVR1 (SYSCTRL_BASE + 0x68) +#define MXC_CCM_DCVR2 (SYSCTRL_BASE + 0x72) +#define MXC_CCM_DCVR3 (SYSCTRL_BASE + 0x76) +#define MXC_CCM_PMCR0_DPTEN 0x00000001 +#define MXC_CCM_DIE 0x00000002 +#define MXC_CCM_DIM 0x0000000C +#define MXC_CCM_DCR 0x00000200 +#define MXC_CCM_PMCR0_DRCE0 0x00000010 +#define MXC_CCM_PMCR0_DRCE1 0x00000020 +#define MXC_CCM_PMCR0_DRCE2 0x00000040 +#define MXC_CCM_PMCR0_DRCE3 0x00000080 +#define MXC_CCM_PMCR0_PTVAIM MXC_CCM_DIM + +#define CCM_CSCR_USB_OFFSET 28 +#define CCM_CSCR_USB_MASK (0x7 << 28) +#define CCM_CSCR_SD_OFFSET 24 +#define CCM_CSCR_SD_MASK (0x3 << 24) +#define CCM_CSCR_SSI2 (1 << 23) +#define CCM_CSCR_SSI2_OFFSET 23 +#define CCM_CSCR_SSI1 (1 << 22) +#define CCM_CSCR_SSI1_OFFSET 22 +#define CCM_CSCR_VPU (1 << 21) +#define CCM_CSCR_VPU_OFFSET 21 +#define CCM_CSCR_MSHC (1 << 20) +#define CCM_CSCR_SPLLRES (1 << 19) +#define CCM_CSCR_MPLLRES (1 << 18) +#define CCM_CSCR_SP (1 << 17) +#define CCM_CSCR_MCU (1 << 16) +/* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/ +#define CCM_CSCR_ARM_SRC (1 << 15) +#define CCM_CSCR_ARM_OFFSET 12 +#define CCM_CSCR_ARM_MASK (0x3 << 12) +/* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/ +#define CCM_CSCR_PRESC_OFFSET 13 +#define CCM_CSCR_PRESC_MASK (0x7 << 13) +#define CCM_CSCR_BCLK_OFFSET 9 +#define CCM_CSCR_BCLK_MASK (0xf << 9) +#define CCM_CSCR_IPDIV_OFFSET 8 +#define CCM_CSCR_IPDIV (1 << 8) +/* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/ +#define CCM_CSCR_AHB_OFFSET 8 +#define CCM_CSCR_AHB_MASK (0x3 << 8) +/* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/ +#define CCM_CSCR_OSC26MDIV (1 << 4) +#define CCM_CSCR_OSC26M (1 << 3) +#define CCM_CSCR_FPM (1 << 2) +#define CCM_CSCR_SPEN (1 << 1) +#define CCM_CSCR_MPEN 1 + +#define CCM_MPCTL0_CPLM (1 << 31) +#define CCM_MPCTL0_PD_OFFSET 26 +#define CCM_MPCTL0_PD_MASK (0xf << 26) +#define CCM_MPCTL0_MFD_OFFSET 16 +#define CCM_MPCTL0_MFD_MASK (0x3ff << 16) +#define CCM_MPCTL0_MFI_OFFSET 10 +#define CCM_MPCTL0_MFI_MASK (0xf << 10) +#define CCM_MPCTL0_MFN_OFFSET 0 +#define CCM_MPCTL0_MFN_MASK 0x3ff + +#define CCM_MPCTL1_LF (1 << 15) +#define CCM_MPCTL1_BRMO (1 << 6) + +#define CCM_SPCTL0_CPLM (1 << 31) +#define CCM_SPCTL0_PD_OFFSET 26 +#define CCM_SPCTL0_PD_MASK (0xf << 26) +#define CCM_SPCTL0_MFD_OFFSET 16 +#define CCM_SPCTL0_MFD_MASK (0x3ff << 16) +#define CCM_SPCTL0_MFI_OFFSET 10 +#define CCM_SPCTL0_MFI_MASK (0xf << 10) +#define CCM_SPCTL0_MFN_OFFSET 0 +#define CCM_SPCTL0_MFN_MASK 0x3ff + +#define CCM_SPCTL1_LF (1 << 15) +#define CCM_SPCTL1_BRMO (1 << 6) + +#define CCM_OSC26MCTL_PEAK_OFFSET 16 +#define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16) +#define CCM_OSC26MCTL_AGC_OFFSET 8 +#define CCM_OSC26MCTL_AGC_MASK (0x3f << 8) +#define CCM_OSC26MCTL_ANATEST_OFFSET 0 +#define CCM_OSC26MCTL_ANATEST_MASK 0x3f + +#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26 +#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26) +#define CCM_PCDR0_CLKO_EN 25 +#define CCM_PCDR0_CLKODIV_OFFSET 22 +#define CCM_PCDR0_CLKODIV_MASK (0x7 << 22) +#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16 +#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16) +/*The difinition for i.MX27 TO2*/ +#define CCM_PCDR0_VPUDIV2_OFFSET 10 +#define CCM_PCDR0_VPUDIV2_MASK (0x3f << 10) +#define CCM_PCDR0_NFCDIV2_OFFSET 6 +#define CCM_PCDR0_NFCDIV2_MASK (0xf << 6) +#define CCM_PCDR0_MSHCDIV2_MASK 0x3f +/*The difinition for i.MX27 TO2*/ +#define CCM_PCDR0_NFCDIV_OFFSET 12 +#define CCM_PCDR0_NFCDIV_MASK (0xf << 12) +#define CCM_PCDR0_VPUDIV_OFFSET 8 +#define CCM_PCDR0_VPUDIV_MASK (0xf << 8) +#define CCM_PCDR0_MSHCDIV_OFFSET 0 +#define CCM_PCDR0_MSHCDIV_MASK 0x1f + +#define CCM_PCDR1_PERDIV4_OFFSET 24 +#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24) +#define CCM_PCDR1_PERDIV3_OFFSET 16 +#define CCM_PCDR1_PERDIV3_MASK (0x3f << 16) +#define CCM_PCDR1_PERDIV2_OFFSET 8 +#define CCM_PCDR1_PERDIV2_MASK (0x3f << 8) +#define CCM_PCDR1_PERDIV1_OFFSET 0 +#define CCM_PCDR1_PERDIV1_MASK 0x3f + +#define CCM_PCCR0_CSPI1_OFFSET 31 +#define CCM_PCCR0_CSPI1_MASK (1 << 31) +#define CCM_PCCR0_CSPI2_OFFSET 30 +#define CCM_PCCR0_CSPI2_MASK (1 << 30) +#define CCM_PCCR0_CSPI3_OFFSET 29 +#define CCM_PCCR0_CSPI3_MASK (1 << 29) +#define CCM_PCCR0_DMA_OFFSET 28 +#define CCM_PCCR0_DMA_MASK (1 << 28) +#define CCM_PCCR0_EMMA_OFFSET 27 +#define CCM_PCCR0_EMMA_MASK (1 << 27) +#define CCM_PCCR0_FEC_OFFSET 26 +#define CCM_PCCR0_FEC_MASK (1 << 26) +#define CCM_PCCR0_GPIO_OFFSET 25 +#define CCM_PCCR0_GPIO_MASK (1 << 25) +#define CCM_PCCR0_GPT1_OFFSET 24 +#define CCM_PCCR0_GPT1_MASK (1 << 24) +#define CCM_PCCR0_GPT2_OFFSET 23 +#define CCM_PCCR0_GPT2_MASK (1 << 23) +#define CCM_PCCR0_GPT3_OFFSET 22 +#define CCM_PCCR0_GPT3_MASK (1 << 22) +#define CCM_PCCR0_GPT4_OFFSET 21 +#define CCM_PCCR0_GPT4_MASK (1 << 21) +#define CCM_PCCR0_GPT5_OFFSET 20 +#define CCM_PCCR0_GPT5_MASK (1 << 20) +#define CCM_PCCR0_GPT6_OFFSET 19 +#define CCM_PCCR0_GPT6_MASK (1 << 19) +#define CCM_PCCR0_I2C1_OFFSET 18 +#define CCM_PCCR0_I2C1_MASK (1 << 18) +#define CCM_PCCR0_I2C2_OFFSET 17 +#define CCM_PCCR0_I2C2_MASK (1 << 17) +#define CCM_PCCR0_IIM_OFFSET 16 +#define CCM_PCCR0_IIM_MASK (1 << 16) +#define CCM_PCCR0_KPP_OFFSET 15 +#define CCM_PCCR0_KPP_MASK (1 << 15) +#define CCM_PCCR0_LCDC_OFFSET 14 +#define CCM_PCCR0_LCDC_MASK (1 << 14) +#define CCM_PCCR0_MSHC_OFFSET 13 +#define CCM_PCCR0_MSHC_MASK (1 << 13) +#define CCM_PCCR0_OWIRE_OFFSET 12 +#define CCM_PCCR0_OWIRE_MASK (1 << 12) +#define CCM_PCCR0_PWM_OFFSET 11 +#define CCM_PCCR0_PWM_MASK (1 << 11) +#define CCM_PCCR0_RTC_OFFSET 9 +#define CCM_PCCR0_RTC_MASK (1 << 9) +#define CCM_PCCR0_RTIC_OFFSET 8 +#define CCM_PCCR0_RTIC_MASK (1 << 8) +#define CCM_PCCR0_SAHARA_OFFSET 7 +#define CCM_PCCR0_SAHARA_MASK (1 << 7) +#define CCM_PCCR0_SCC_OFFSET 6 +#define CCM_PCCR0_SCC_MASK (1 << 6) +#define CCM_PCCR0_SDHC1_OFFSET 5 +#define CCM_PCCR0_SDHC1_MASK (1 << 5) +#define CCM_PCCR0_SDHC2_OFFSET 4 +#define CCM_PCCR0_SDHC2_MASK (1 << 4) +#define CCM_PCCR0_SDHC3_OFFSET 3 +#define CCM_PCCR0_SDHC3_MASK (1 << 3) +#define CCM_PCCR0_SLCDC_OFFSET 2 +#define CCM_PCCR0_SLCDC_MASK (1 << 2) +#define CCM_PCCR0_SSI1_IPG_OFFSET 1 +#define CCM_PCCR0_SSI1_IPG_MASK (1 << 1) +#define CCM_PCCR0_SSI2_IPG_OFFSET 0 +#define CCM_PCCR0_SSI2_IPG_MASK (1 << 0) + +#define CCM_PCCR1_UART1_OFFSET 31 +#define CCM_PCCR1_UART1_MASK (1 << 31) +#define CCM_PCCR1_UART2_OFFSET 30 +#define CCM_PCCR1_UART2_MASK (1 << 30) +#define CCM_PCCR1_UART3_OFFSET 29 +#define CCM_PCCR1_UART3_MASK (1 << 29) +#define CCM_PCCR1_UART4_OFFSET 28 +#define CCM_PCCR1_UART4_MASK (1 << 28) +#define CCM_PCCR1_UART5_OFFSET 27 +#define CCM_PCCR1_UART5_MASK (1 << 27) +#define CCM_PCCR1_UART6_OFFSET 26 +#define CCM_PCCR1_UART6_MASK (1 << 26) +#define CCM_PCCR1_USBOTG_OFFSET 25 +#define CCM_PCCR1_USBOTG_MASK (1 << 25) +#define CCM_PCCR1_WDT_OFFSET 24 +#define CCM_PCCR1_WDT_MASK (1 << 24) +#define CCM_PCCR1_HCLK_ATA_OFFSET 23 +#define CCM_PCCR1_HCLK_ATA_MASK (1 << 23) +#define CCM_PCCR1_HCLK_BROM_OFFSET 22 +#define CCM_PCCR1_HCLK_BROM_MASK (1 << 22) +#define CCM_PCCR1_HCLK_CSI_OFFSET 21 +#define CCM_PCCR1_HCLK_CSI_MASK (1 << 21) +#define CCM_PCCR1_HCLK_DMA_OFFSET 20 +#define CCM_PCCR1_HCLK_DMA_MASK (1 << 20) +#define CCM_PCCR1_HCLK_EMI_OFFSET 19 +#define CCM_PCCR1_HCLK_EMI_MASK (1 << 19) +#define CCM_PCCR1_HCLK_EMMA_OFFSET 18 +#define CCM_PCCR1_HCLK_EMMA_MASK (1 << 18) +#define CCM_PCCR1_HCLK_FEC_OFFSET 17 +#define CCM_PCCR1_HCLK_FEC_MASK (1 << 17) +#define CCM_PCCR1_HCLK_VPU_OFFSET 16 +#define CCM_PCCR1_HCLK_VPU_MASK (1 << 16) +#define CCM_PCCR1_HCLK_LCDC_OFFSET 15 +#define CCM_PCCR1_HCLK_LCDC_MASK (1 << 15) +#define CCM_PCCR1_HCLK_RTIC_OFFSET 14 +#define CCM_PCCR1_HCLK_RTIC_MASK (1 << 14) +#define CCM_PCCR1_HCLK_SAHARA_OFFSET 13 +#define CCM_PCCR1_HCLK_SAHARA_MASK (1 << 13) +#define CCM_PCCR1_HCLK_SLCDC_OFFSET 12 +#define CCM_PCCR1_HCLK_SLCDC_MASK (1 << 12) +#define CCM_PCCR1_HCLK_USBOTG_OFFSET 11 +#define CCM_PCCR1_HCLK_USBOTG_MASK (1 << 11) +#define CCM_PCCR1_PERCLK1_OFFSET 10 +#define CCM_PCCR1_PERCLK1_MASK (1 << 10) +#define CCM_PCCR1_PERCLK2_OFFSET 9 +#define CCM_PCCR1_PERCLK2_MASK (1 << 9) +#define CCM_PCCR1_PERCLK3_OFFSET 8 +#define CCM_PCCR1_PERCLK3_MASK (1 << 8) +#define CCM_PCCR1_PERCLK4_OFFSET 7 +#define CCM_PCCR1_PERCLK4_MASK (1 << 7) +#define CCM_PCCR1_VPU_BAUD_OFFSET 6 +#define CCM_PCCR1_VPU_BAUD_MASK (1 << 6) +#define CCM_PCCR1_SSI1_BAUD_OFFSET 5 +#define CCM_PCCR1_SSI1_BAUD_MASK (1 << 5) +#define CCM_PCCR1_SSI2_BAUD_OFFSET 4 +#define CCM_PCCR1_SSI2_BAUD_MASK (1 << 4) +#define CCM_PCCR1_NFC_BAUD_OFFSET 3 +#define CCM_PCCR1_NFC_BAUD_MASK (1 << 3) +#define CCM_PCCR1_MSHC_BAUD_OFFSET 2 +#define CCM_PCCR1_MSHC_BAUD_MASK (1 << 2) + +#define CCM_CCSR_32KSR (1 << 15) +#define CCM_CCSR_CLKMODE1 (1 << 9) +#define CCM_CCSR_CLKMODE0 (1 << 8) +#define CCM_CCSR_CLKOSEL_OFFSET 0 +#define CCM_CCSR_CLKOSEL_MASK 0x1f + +#define SYS_FMCR 0x14 /* Functional Muxing Control Reg */ +#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */ + +#endif /* __ARCH_ARM_MACH_MX27_CRM_REGS_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx27/devices.c linux-2.6.26-lab126/arch/arm/mach-mx27/devices.c --- linux-2.6.26/arch/arm/mach-mx27/devices.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/devices.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,697 @@ +/* + * Author: MontaVista Software, Inc. + * + * + * Based on the OMAP devices.c + * + * 2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Copyright 2006-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + + /*! + * @file mach-mx27/devices.c + * @brief device configurations including nor/nand/watchdog for mx27. + * + * @ingroup MSL_MX27 + */ + +#ifndef CONFIG_MX27_DPTC +extern struct dptc_wp dptc_wp_allfreq[DPTC_WP_SUPPORTED]; +#endif + +static void mxc_nop_release(struct device *dev) +{ + /* Nothing */ +} + +#if defined(CONFIG_W1_MASTER_MXC) || defined(CONFIG_W1_MASTER_MXC_MODULE) +static struct mxc_w1_config mxc_w1_data = { + .search_rom_accelerator = 0, +}; + +static struct platform_device mxc_w1_devices = { + .name = "mxc_w1", + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_w1_data, + }, + .id = 0 +}; + +static void mxc_init_owire(void) +{ + (void)platform_device_register(&mxc_w1_devices); +} +#else +static inline void mxc_init_owire(void) +{ +} +#endif + +#if defined(CONFIG_RTC_MXC) || defined(CONFIG_RTC_MXC_MODULE) +static struct resource rtc_resources[] = { + { + .start = RTC_BASE_ADDR, + .end = RTC_BASE_ADDR + 0x30, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_RTC, + .flags = IORESOURCE_IRQ, + }, +}; +static struct platform_device mxc_rtc_device = { + .name = "mxc_rtc", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, +}; +static void mxc_init_rtc(void) +{ + (void)platform_device_register(&mxc_rtc_device); +} +#else +static inline void mxc_init_rtc(void) +{ +} +#endif +#if defined(CONFIG_MXC_WATCHDOG) || defined(CONFIG_MXC_WATCHDOG_MODULE) + +static struct resource wdt_resources[] = { + { + .start = WDOG1_BASE_ADDR, + .end = WDOG1_BASE_ADDR + 0x30, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mxc_wdt_device = { + .name = "mxc_wdt", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(wdt_resources), + .resource = wdt_resources, +}; + +static void mxc_init_wdt(void) +{ + (void)platform_device_register(&mxc_wdt_device); +} +#else +static inline void mxc_init_wdt(void) +{ +} +#endif +/*! + * This is platform device structure for adding SCC + */ +#if defined(CONFIG_MXC_SECURITY_SCC) || defined(CONFIG_MXC_SECURITY_SCC_MODULE) +static struct platform_device mxc_scc_device = { + .name = "mxc_scc", + .id = 0, +}; + +static void mxc_init_scc(void) +{ + platform_device_register(&mxc_scc_device); +} +#else +static inline void mxc_init_scc(void) +{ +} +#endif +/* MMC device data */ + +#if defined(CONFIG_MMC_MXC) || defined(CONFIG_MMC_MXC_MODULE) + +extern unsigned int sdhc_get_card_det_status(struct device *dev); +extern int sdhc_init_card_det(int id); + +static struct mxc_mmc_platform_data mmc_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30, + .min_clk = 150000, + .max_clk = 25000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, +}; + +/*! + * Resource definition for the SDHC1 + */ +static struct resource mxcsdhc1_resources[] = { + [0] = { + .start = SDHC1_BASE_ADDR, + .end = SDHC1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_SDHC1, + .end = MXC_INT_SDHC1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! + * Resource definition for the SDHC2 + */ +static struct resource mxcsdhc2_resources[] = { + [0] = { + .start = SDHC2_BASE_ADDR, + .end = SDHC2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_SDHC2, + .end = MXC_INT_SDHC2, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Device Definition for MXC SDHC1 */ +static struct platform_device mxcsdhc1_device = { + .name = "mxcmci", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc_data, + }, + .num_resources = ARRAY_SIZE(mxcsdhc1_resources), + .resource = mxcsdhc1_resources, +}; + +/*! Device Definition for MXC SDHC2 */ +static struct platform_device mxcsdhc2_device = { + .name = "mxcmci", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc_data, + }, + .num_resources = ARRAY_SIZE(mxcsdhc2_resources), + .resource = mxcsdhc2_resources, +}; + +#ifdef CONFIG_MXC_SDHC3 +/*! + * Resource definition for the SDHC3 + */ +static struct resource mxcsdhc3_resources[] = { + [0] = { + .start = SDHC3_BASE_ADDR, + .end = SDHC3_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_SDHC3, + .end = MXC_INT_SDHC3, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = MXC_SDIO3_CARD_IRQ, + .end = MXC_SDIO3_CARD_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Device Definition for MXC SDHC3 */ +static struct platform_device mxcsdhc3_device = { + .name = "mxcmci", + .id = 2, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc_data, + }, + .num_resources = ARRAY_SIZE(mxcsdhc3_resources), + .resource = mxcsdhc3_resources, +}; +#endif + +static inline void mxc_init_mmc(void) +{ + int cd_irq; + + cd_irq = sdhc_init_card_det(0); + if (cd_irq) { + mxcsdhc1_device.resource[2].start = cd_irq; + mxcsdhc1_device.resource[2].end = cd_irq; + } + cd_irq = sdhc_init_card_det(1); + if (cd_irq) { + mxcsdhc2_device.resource[2].start = cd_irq; + mxcsdhc2_device.resource[2].end = cd_irq; + } + + (void)platform_device_register(&mxcsdhc1_device); + (void)platform_device_register(&mxcsdhc2_device); +#ifdef CONFIG_MXC_SDHC3 + (void)platform_device_register(&mxcsdhc3_device); +#endif +} +#else +static inline void mxc_init_mmc(void) +{ +} +#endif + +/* SPI controller and device data */ +#if defined(CONFIG_SPI_MXC) || defined(CONFIG_SPI_MXC_MODULE) + +#ifdef CONFIG_SPI_MXC_SELECT1 +/*! + * Resource definition for the CSPI1 + */ +static struct resource mxcspi1_resources[] = { + [0] = { + .start = CSPI1_BASE_ADDR, + .end = CSPI1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_CSPI1, + .end = MXC_INT_CSPI1, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC CSPI1 */ +static struct mxc_spi_master mxcspi1_data = { + .maxchipselect = 4, + .spi_version = 0, +}; + +/*! Device Definition for MXC CSPI1 */ +static struct platform_device mxcspi1_device = { + .name = "mxc_spi", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxcspi1_data, + }, + .num_resources = ARRAY_SIZE(mxcspi1_resources), + .resource = mxcspi1_resources, +}; + +#endif /* CONFIG_SPI_MXC_SELECT1 */ + +#ifdef CONFIG_SPI_MXC_SELECT2 +/*! + * Resource definition for the CSPI2 + */ +static struct resource mxcspi2_resources[] = { + [0] = { + .start = CSPI2_BASE_ADDR, + .end = CSPI2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_CSPI2, + .end = MXC_INT_CSPI2, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC CSPI2 */ +static struct mxc_spi_master mxcspi2_data = { + .maxchipselect = 4, + .spi_version = 0, +}; + +/*! Device Definition for MXC CSPI2 */ +static struct platform_device mxcspi2_device = { + .name = "mxc_spi", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxcspi2_data, + }, + .num_resources = ARRAY_SIZE(mxcspi2_resources), + .resource = mxcspi2_resources, +}; +#endif /* CONFIG_SPI_MXC_SELECT2 */ + +#ifdef CONFIG_SPI_MXC_SELECT3 +/*! + * Resource definition for the CSPI3 + */ +static struct resource mxcspi3_resources[] = { + [0] = { + .start = CSPI3_BASE_ADDR, + .end = CSPI3_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_CSPI3, + .end = MXC_INT_CSPI3, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC CSPI3 */ +static struct mxc_spi_master mxcspi3_data = { + .maxchipselect = 4, + .spi_version = 0, +}; + +/*! Device Definition for MXC CSPI3 */ +static struct platform_device mxcspi3_device = { + .name = "mxc_spi", + .id = 2, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxcspi3_data, + }, + .num_resources = ARRAY_SIZE(mxcspi3_resources), + .resource = mxcspi3_resources, +}; +#endif /* CONFIG_SPI_MXC_SELECT3 */ + +static inline void mxc_init_spi(void) +{ +#ifdef CONFIG_SPI_MXC_SELECT1 + if (platform_device_register(&mxcspi1_device) < 0) + printk(KERN_ERR "Registering the SPI Controller_1\n"); +#endif /* CONFIG_SPI_MXC_SELECT1 */ +#ifdef CONFIG_SPI_MXC_SELECT2 + if (platform_device_register(&mxcspi2_device) < 0) + printk(KERN_ERR "Registering the SPI Controller_2\n"); +#endif /* CONFIG_SPI_MXC_SELECT2 */ +#ifdef CONFIG_SPI_MXC_SELECT3 + if (platform_device_register(&mxcspi3_device) < 0) + printk(KERN_ERR "Registering the SPI Controller_3\n"); +#endif /* CONFIG_SPI_MXC_SELECT3 */ +} +#else +static inline void mxc_init_spi(void) +{ +} +#endif + +#if defined(CONFIG_SND_MXC_PMIC) || defined(CONFIG_SND_MXC_PMIC_MODULE) +static struct mxc_audio_platform_data mxc_audio_data; + +static struct platform_device mxc_alsa_device = { + .name = "mxc_alsa", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_audio_data, + }, + +}; + +static void mxc_init_audio(void) +{ + mxc_audio_data.ssi_clk[0] = clk_get(NULL, "ssi_clk.0"); + clk_put(mxc_audio_data.ssi_clk[0]); + mxc_audio_data.ssi_clk[1] = clk_get(NULL, "ssi_clk.1"); + clk_put(mxc_audio_data.ssi_clk[1]); + mxc_audio_data.ssi_num = 2; + mxc_audio_data.src_port = 0; + platform_device_register(&mxc_alsa_device); +} +#else + +static void mxc_init_audio(void) +{ +} +#endif + +#if defined(CONFIG_MXC_SSI) || defined(CONFIG_MXC_SSI_MODULE) +/*! + * Resource definition for the SSI + */ +static struct resource mxcssi2_resources[] = { + [0] = { + .start = SSI2_BASE_ADDR, + .end = SSI2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource mxcssi1_resources[] = { + [0] = { + .start = SSI1_BASE_ADDR, + .end = SSI1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +/*! Device Definition for MXC SSI */ +static struct platform_device mxc_ssi1_device = { + .name = "mxc_ssi", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_audio_data, + }, + .num_resources = ARRAY_SIZE(mxcssi1_resources), + .resource = mxcssi1_resources, +}; + +static struct platform_device mxc_ssi2_device = { + .name = "mxc_ssi", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_audio_data, + }, + .num_resources = ARRAY_SIZE(mxcssi2_resources), + .resource = mxcssi2_resources, +}; + +static void mxc_init_ssi(void) +{ + platform_device_register(&mxc_ssi1_device); + platform_device_register(&mxc_ssi2_device); +} +#else + +static void mxc_init_ssi(void) +{ +} +#endif + +/* I2C controller and device data */ +#if defined(CONFIG_I2C_MXC) || defined(CONFIG_I2C_MXC_MODULE) + +#ifdef CONFIG_I2C_MXC_SELECT1 +/*! + * Resource definition for the I2C1 + */ +static struct resource mxci2c1_resources[] = { + [0] = { + .start = I2C_BASE_ADDR, + .end = I2C_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_I2C, + .end = MXC_INT_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC I2C */ +static struct mxc_i2c_platform_data mxci2c1_data = { + .i2c_clk = 100000, +}; +#endif + +#ifdef CONFIG_I2C_MXC_SELECT2 +/*! + * Resource definition for the I2C2 + */ +static struct resource mxci2c2_resources[] = { + [0] = { + .start = I2C2_BASE_ADDR, + .end = I2C2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_I2C2, + .end = MXC_INT_I2C2, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC I2C */ +static struct mxc_i2c_platform_data mxci2c2_data = { + .i2c_clk = 100000, +}; +#endif + +/*! Device Definition for MXC I2C */ +static struct platform_device mxci2c_devices[] = { +#ifdef CONFIG_I2C_MXC_SELECT1 + { + .name = "mxc_i2c", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxci2c1_data, + }, + .num_resources = ARRAY_SIZE(mxci2c1_resources), + .resource = mxci2c1_resources,}, +#endif +#ifdef CONFIG_I2C_MXC_SELECT2 + { + .name = "mxc_i2c", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxci2c2_data, + }, + .num_resources = ARRAY_SIZE(mxci2c2_resources), + .resource = mxci2c2_resources,}, +#endif +}; + +static inline void mxc_init_i2c(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mxci2c_devices); i++) { + if (platform_device_register(&mxci2c_devices[i]) < 0) + dev_err(&mxci2c_devices[i].dev, + "Unable to register I2C device\n"); + } +} +#else +static inline void mxc_init_i2c(void) +{ +} +#endif + +#ifdef CONFIG_MXC_VPU +/*! Platform Data for MXC VPU */ +static struct platform_device mxcvpu_device = { + .name = "mxc_vpu", + .dev = { + .release = mxc_nop_release, + }, + .id = 0, +}; + +static inline void mxc_init_vpu(void) +{ + if (platform_device_register(&mxcvpu_device) < 0) + printk(KERN_ERR "Error: Registering the VPU.\n"); +} +#else +static inline void mxc_init_vpu(void) +{ +} +#endif + +struct mxc_gpio_port mxc_gpio_ports[GPIO_PORT_NUM] = { + { + .num = 0, + .base = IO_ADDRESS(GPIO_BASE_ADDR), + .irq = MXC_INT_GPIO, + .virtual_irq_start = MXC_GPIO_INT_BASE, + }, + { + .num = 1, + .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x100, + .irq = MXC_INT_GPIO, + .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN, + }, + { + .num = 2, + .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x200, + .irq = MXC_INT_GPIO, + .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 2, + }, + { + .num = 3, + .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x300, + .irq = MXC_INT_GPIO, + .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 3, + }, + { + .num = 4, + .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x400, + .irq = MXC_INT_GPIO, + .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 4, + }, + { + .num = 5, + .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x500, + .irq = MXC_INT_GPIO, + .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 5, + }, +}; + +#ifndef CONFIG_MX27_DPTC +/*! Device Definition for DPTC */ +static struct platform_device mxc_dptc_device = { + .name = "mxc_dptc", + .dev = { + .release = mxc_nop_release, + .platform_data = &dptc_wp_allfreq, + }, +}; + +static inline void mxc_init_dptc(void) +{ + (void)platform_device_register(&mxc_dptc_device); +} +#endif + +static int __init mxc_init_devices(void) +{ + mxc_init_wdt(); + mxc_init_mmc(); + mxc_init_spi(); + mxc_init_i2c(); + mxc_init_rtc(); + mxc_init_ssi(); + mxc_init_audio(); + mxc_init_scc(); + mxc_init_owire(); + mxc_init_vpu(); +#ifndef CONFIG_MX27_DPTC + mxc_init_dptc(); +#endif + + return 0; +} + +arch_initcall(mxc_init_devices); diff -urN linux-2.6.26/arch/arm/mach-mx27/dma.c linux-2.6.26-lab126/arch/arm/mach-mx27/dma.c --- linux-2.6.26/arch/arm/mach-mx27/dma.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/dma.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,553 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + *@file mach-mx27/dma.c + *@brief This file contains the dma parameter which is depend on the platform . + * @ingroup DMA_MX27 + */ + +#include +#include +#include + +#define MXC_SOUND_PLAYBACK_CHAIN_DMA 1 +#define MXC_SOUND_CAPTURE_CHAIN_DMA 1 + +/*! + * @brief the structure stored device_id and dma_info pointer + */ +typedef struct dma_info_entry_s { + mxc_dma_device_t device; + /* if there are two dma_info , first is for reading, another is for writing */ + mx2_dma_info_t *info; +} dma_info_entry_t; + +/*! + * @brief dma_info from memory to memory for dma testing + */ +static mx2_dma_info_t ram2ram_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 0, + .burstLength = 4,.request = 0,.busuntils = 0, + .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_32BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT, + .M2D_Valid = 0 +}; + +/*! + * @brief dma_info from 2D memory to 2D memory for dma testing + */ +static mx2_dma_info_t ram2d2ram2d_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 0, + .dir = 0, + .rto_en = 0, + .dma_chaining = 0,.ren = 0, + .burstLength = 4,.request = 0,.busuntils = 0, + .sourceType = DMA_TYPE_2D,.sourcePort = TRANSFER_32BIT, + .destType = DMA_TYPE_2D,.destPort = TRANSFER_32BIT, + .M2D_Valid = 1,.msel = 0,.W = 0x80,.X = 0x40,.Y = 0x10 +}; + +/*! + * @brief dma_info from memory to 2D memory for dma testing + */ +static mx2_dma_info_t ram2ram2d_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 0, + .burstLength = 4,.request = 0,.busuntils = 0, + .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_32BIT, + .destType = DMA_TYPE_2D,.destPort = TRANSFER_32BIT, + .M2D_Valid = 1,.msel = 0,.W = 0x100,.X = 0x80,.Y = 0x10 +}; + +/*! + * @brief dma_info from 2D memory to memory for dma testing + */ +static mx2_dma_info_t ram2d2ram_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 0, + .burstLength = 4,.request = 0,.busuntils = 0, + .sourceType = DMA_TYPE_2D,.sourcePort = TRANSFER_32BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT, + .M2D_Valid = 1,.msel = 0,.W = 0x100,.X = 0x100,.Y = 0x10 +}; + +/*! + * @brief dma_info with dma chaining feature for dma testing + */ +static mx2_dma_info_t hw_chaining_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 0, + .dir = 0, + .dma_chaining = 1,.ren = 0, + .burstLength = 4,.request = 0,.busuntils = 0, + .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_32BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT, + .M2D_Valid = 0, +}; + +/*! + * @brief dma_info without dma chaining feature for dma testing + */ +static mx2_dma_info_t sw_chaining_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 0, + .burstLength = 4,.request = 0,.busuntils = 0, + .sourceType = DMA_TYPE_LINEAR,.sourcePort = TRANSFER_32BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT, + .M2D_Valid = 0, +}; + +/*! + * @brief dma_info for ATA recieveing + */ +static mx2_dma_info_t ata_rx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 1, + .burstLength = 32,.request = 29,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_32BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT, + .per_address = (ATA_BASE_ADDR + 0x18), + .M2D_Valid = 0, +}; + +/*! + * @brief: dma_info for ATA transmitting + */ +static mx2_dma_info_t ata_tx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 1, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 1, + .burstLength = 32,.request = 28,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_32BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_32BIT, + .per_address = (ATA_BASE_ADDR + 0x18), + .M2D_Valid = 0, +}; + +/*! + * @brief dma_info for UART1 recieveing + */ +static mx2_dma_info_t uart1_rx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 1, + .dir = 0, + .dma_chaining = 0,.ren = 1, + .burstLength = 1,.request = 26,.busuntils = 8, + .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT, + .per_address = (UART1_BASE_ADDR), + .M2D_Valid = 0, +}; + +/*! + * @brief: dma_info for UART1 transmitting + */ +static mx2_dma_info_t uart1_tx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 1, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 1, + .burstLength = 1,.request = 27,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT, + .per_address = (UART1_BASE_ADDR + 0x40), + .M2D_Valid = 0, +}; + +/*! + * @brief dma_info for UART2 recieveing + */ +static mx2_dma_info_t uart2_rx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 1, + .burstLength = 1,.request = 24,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT, + .per_address = (UART2_BASE_ADDR), + .M2D_Valid = 0, +}; + +/*! + * @brief: dma_info for UART2 transmitting + */ +static mx2_dma_info_t uart2_tx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 1, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 1, + .burstLength = 1,.request = 25,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT, + .per_address = (UART2_BASE_ADDR + 0x40), + .M2D_Valid = 0, +}; + +/*! + * @brief dma_info for UART3 recieveing + */ +static mx2_dma_info_t uart3_rx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 1, + .burstLength = 1,.request = 22,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT, + .per_address = (UART3_BASE_ADDR), + .M2D_Valid = 0, +}; + +/*! + * @brief: dma_info for UART3 transmitting + */ +static mx2_dma_info_t uart3_tx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 1, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 1, + .burstLength = 1,.request = 23,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT, + .per_address = (UART3_BASE_ADDR + 0x40), + .M2D_Valid = 0, +}; + +/*! + * @brief dma_info for UART4 recieveing + */ +static mx2_dma_info_t uart4_rx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 1, + .burstLength = 1,.request = 20,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT, + .per_address = (UART4_BASE_ADDR), + .M2D_Valid = 0, +}; + +/*! + * @brief: dma_info for UART4transmitting + */ +static mx2_dma_info_t uart4_tx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 1, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 1, + .burstLength = 1,.request = 21,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT, + .per_address = (UART4_BASE_ADDR + 0x40), + .M2D_Valid = 0, +}; + +/*! + * @brief dma_info for UART5 recieveing + */ +static mx2_dma_info_t uart5_rx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 1, + .burstLength = 1,.request = 32,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT, + .per_address = (UART5_BASE_ADDR), + .M2D_Valid = 0, +}; + +/*! + * @brief: dma_info for UART5 transmitting + */ +static mx2_dma_info_t uart5_tx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 1, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 1, + .burstLength = 1,.request = 33,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT, + .per_address = (UART5_BASE_ADDR + 0x40), + .M2D_Valid = 0, +}; + +/*! + * @brief dma_info for UART6 recieveing + */ +static mx2_dma_info_t uart6_rx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 1, + .burstLength = 1,.request = 34,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT, + .per_address = (UART6_BASE_ADDR), + .M2D_Valid = 0, +}; + +/*! + * @brief: dma_info for UART6 transmitting + */ +static mx2_dma_info_t uart6_tx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 1, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 1, + .burstLength = 1,.request = 35,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = TRANSFER_8BIT, + .destType = DMA_TYPE_LINEAR,.destPort = TRANSFER_8BIT, + .per_address = (UART6_BASE_ADDR + 0x40), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t ssi1_16bit_rx0_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 0, + .dir = 0, + .dma_chaining = MXC_SOUND_CAPTURE_CHAIN_DMA,.ren = 1, + .burstLength = 8,.request = DMA_REQ_SSI1_RX0,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_16, + .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32, + .per_address = (SSI1_BASE_ADDR + 0x08), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t ssi1_16bit_tx0_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 1, + .rto_en = 0, + .dir = 0, + .dma_chaining = MXC_SOUND_PLAYBACK_CHAIN_DMA,.ren = 1, + .burstLength = 8,.request = DMA_REQ_SSI1_TX0,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_16, + .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32, + .per_address = (SSI1_BASE_ADDR), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t ssi2_16bit_rx0_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 0, + .dir = 0, + .dma_chaining = MXC_SOUND_CAPTURE_CHAIN_DMA,.ren = 1, + .burstLength = 8,.request = DMA_REQ_SSI2_RX0,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_16, + .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32, + .per_address = (SSI2_BASE_ADDR + 0x08), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t ssi2_16bit_tx0_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 1, + .rto_en = 0, + .dir = 0, + .dma_chaining = MXC_SOUND_PLAYBACK_CHAIN_DMA,.ren = 1, + .burstLength = 8,.request = DMA_REQ_SSI2_TX0,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_16, + .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32, + .per_address = (SSI2_BASE_ADDR), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t mmc1_width1_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 1, + .burstLength = 16,.request = DMA_REQ_SDHC1,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_32, + .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32, + .per_address = (SDHC1_BASE_ADDR + 0x38), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t mmc1_width4_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 1, + .burstLength = 0,.request = DMA_REQ_SDHC1,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_32, + .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32, + .per_address = (SDHC1_BASE_ADDR + 0x38), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t mmc2_width1_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 1, + .burstLength = 16,.request = DMA_REQ_SDHC2,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_32, + .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32, + .per_address = (SDHC2_BASE_ADDR + 0x38), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t mmc2_width4_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 0, + .dir = 0, + .dma_chaining = 0,.ren = 1, + .burstLength = 0,.request = DMA_REQ_SDHC2,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_32, + .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32, + .per_address = (SDHC2_BASE_ADDR + 0x38), + .M2D_Valid = 0, +}; + +static mx2_dma_info_t csi_rx_dma_info = { + .dma_chan = MXC_DMA_DYNAMIC_CHANNEL, + .mode = 0, + .rto_en = 0, + .dir = 0, + .dma_chaining = 1,.ren = 1, + .burstLength = 64,.request = DMA_REQ_CSI_RX,.busuntils = 0, + .sourceType = DMA_TYPE_FIFO,.sourcePort = DMA_MEM_SIZE_32, + .destType = DMA_TYPE_LINEAR,.destPort = DMA_MEM_SIZE_32, + .per_address = (CSI_BASE_ADDR + 0x10), + .M2D_Valid = 0, +}; + +/*! + * @brief dma info array which is actived + * DEVICE_ID RX/(RX&TX) TX + */ +static dma_info_entry_t active_dma_info[] = { + {MXC_DMA_TEST_RAM2RAM, &ram2ram_dma_info}, + {MXC_DMA_TEST_RAM2D2RAM2D, &ram2d2ram2d_dma_info}, + {MXC_DMA_TEST_RAM2RAM2D, &ram2ram2d_dma_info}, + {MXC_DMA_TEST_RAM2D2RAM, &ram2d2ram_dma_info}, + {MXC_DMA_TEST_HW_CHAINING, &hw_chaining_dma_info}, + {MXC_DMA_TEST_SW_CHAINING, &sw_chaining_dma_info}, + {MXC_DMA_ATA_RX, &ata_rx_dma_info}, + {MXC_DMA_ATA_TX, &ata_tx_dma_info}, + {MXC_DMA_UART1_RX, &uart1_rx_dma_info}, + {MXC_DMA_UART1_TX, &uart1_tx_dma_info}, + {MXC_DMA_UART2_RX, &uart2_rx_dma_info}, + {MXC_DMA_UART2_TX, &uart2_tx_dma_info}, + {MXC_DMA_UART3_RX, &uart3_rx_dma_info}, + {MXC_DMA_UART3_TX, &uart3_tx_dma_info}, + {MXC_DMA_UART4_RX, &uart4_rx_dma_info}, + {MXC_DMA_UART4_TX, &uart4_tx_dma_info}, + {MXC_DMA_UART5_RX, &uart5_rx_dma_info}, + {MXC_DMA_UART5_TX, &uart5_tx_dma_info}, + {MXC_DMA_UART6_RX, &uart6_rx_dma_info}, + {MXC_DMA_UART6_TX, &uart6_tx_dma_info}, + {MXC_DMA_SSI1_16BIT_RX0, &ssi1_16bit_rx0_dma_info}, + {MXC_DMA_SSI1_16BIT_TX0, &ssi1_16bit_tx0_dma_info}, + {MXC_DMA_SSI2_16BIT_RX0, &ssi2_16bit_rx0_dma_info}, + {MXC_DMA_SSI2_16BIT_TX0, &ssi2_16bit_tx0_dma_info}, + {MXC_DMA_MMC1_WIDTH_1, &mmc1_width1_dma_info}, + {MXC_DMA_MMC1_WIDTH_4, &mmc1_width4_dma_info}, + {MXC_DMA_MMC2_WIDTH_1, &mmc2_width1_dma_info}, + {MXC_DMA_MMC2_WIDTH_4, &mmc2_width4_dma_info}, + {MXC_DMA_CSI_RX, &csi_rx_dma_info}, +}; + +/*! + * @brief the number of actived dma info + */ +static int dma_info_entrys = + sizeof(active_dma_info) / sizeof(active_dma_info[0]); + +/*! + * @brief get the dma info by channel_id + */ +mx2_dma_info_t *mxc_dma_get_info(mxc_dma_device_t channel_id) +{ + dma_info_entry_t *p = active_dma_info; + int i; + for (i = 0; i < dma_info_entrys; i++, p++) { + if (p->device == channel_id) + return p->info; + } + return NULL; +} + +/*! + * @brief: scan dma parameter list . And collect information about which channels are dynamic . + */ +void mxc_dma_load_info(mxc_dma_channel_t * dma) +{ + int i, idx; + dma_info_entry_t *p = active_dma_info; + + BUG_ON(dma == NULL); + BUG_ON(p == NULL); + + for (i = 0; i < MXC_DMA_CHANNELS; i++) { + dma[i].dynamic = 1; + } + + for (i = 0; i < dma_info_entrys; i++, p++) { + BUG_ON((p->info == NULL)); + + idx = p->info->dma_chan; + + BUG_ON(((idx >= MAX_DMA_CHANNELS) + && (idx != MXC_DMA_DYNAMIC_CHANNEL))); + if ((idx < 0) || (idx == MXC_DMA_DYNAMIC_CHANNEL)) + continue; + dma[idx].dynamic = 0; + } +} + +EXPORT_SYMBOL(mxc_dma_get_info); +EXPORT_SYMBOL(mxc_dma_load_info); diff -urN linux-2.6.26/arch/arm/mach-mx27/dptc.c linux-2.6.26-lab126/arch/arm/mach-mx27/dptc.c --- linux-2.6.26/arch/arm/mach-mx27/dptc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/dptc.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,49 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dptc.c + * + * @brief DPTC table for the Freescale Semiconductor MXC DPTC module. + * + * @ingroup PM + */ + +#include +#include + +struct dptc_wp dptc_wp_allfreq[DPTC_WP_SUPPORTED] = { + /* 532MHz */ + /* dcvr0 dcvr1 dcvr2 dcvr3 voltage */ + /* wp0 */ + {0xffe00000, 0x18e2e85b, 0xffe00000, 0x25c4688a, 1600}, + {0xffe00000, 0x18e2e85b, 0xffe00000, 0x25c4688a, 1575}, + {0xffe00000, 0x1902e85b, 0xffe00000, 0x25e4688a, 1550}, + {0xffe00000, 0x1922e85b, 0xffe00000, 0x25e4688a, 1525}, + {0xffe00000, 0x1942ec5b, 0xffe00000, 0x2604688a, 1500}, + /* wp5 */ + {0xffe00000, 0x1942ec5b, 0xffe00000, 0x26646c8a, 1475}, + {0xffe00000, 0x1962ec5b, 0xffe00000, 0x26c4708b, 1450}, + {0xffe00000, 0x1962ec5b, 0xffe00000, 0x26e4708b, 1425}, + {0xffe00000, 0x1982f05c, 0xffe00000, 0x2704748b, 1400}, + {0xffe00000, 0x19c2f05c, 0xffe00000, 0x2744748b, 1375}, + /* wp10 */ + {0xffe00000, 0x1a02f45c, 0xffe00000, 0x2784788b, 1350}, + {0xffe00000, 0x1a42f45c, 0xffe00000, 0x27c47c8b, 1325}, + {0xffe00000, 0x1a82f85c, 0xffe00000, 0x2824808c, 1300}, + {0xffe00000, 0x1aa2f85c, 0xffe00000, 0x2884848c, 1275}, + {0xffe00000, 0x1ac2fc5c, 0xffe00000, 0x28e4888c, 1250}, + /* wp15 */ + {0xffe00000, 0x1ae2fc5c, 0xffe00000, 0x2924888c, 1225}, + {0xffe00000, 0x1b23005d, 0xffe00000, 0x29648c8c, 1200}, +}; diff -urN linux-2.6.26/arch/arm/mach-mx27/gpio_mux.c linux-2.6.26-lab126/arch/arm/mach-mx27/gpio_mux.c --- linux-2.6.26/arch/arm/mach-mx27/gpio_mux.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/gpio_mux.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,308 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup GPIO_MX27 Board GPIO and Muxing Setup + * @ingroup MSL_MX27 + */ +/*! + * @file mach-mx27/gpio_mux.c + * + * @brief I/O Muxing control functions + * + * @ingroup GPIO_MX27 + */ + +#include +#include +#include + +#include +#include +#include +#include "gpio_mux.h" + +/*! + * This structure defines the offset of registers in gpio module. + */ +enum gpio_reg { + GPIO_GIUS = 0x20, + GPIO_GPR = 0x38, + GPIO_PUEN = 0x40, + GPIO_DDIR = 0x00, + GPIO_OCR1 = 0x04, + GPIO_OCR2 = 0x08, + GPIO_ICONFA1 = 0x0C, + GPIO_ICONFA2 = 0x10, + GPIO_ICONFB1 = 0x14, + GPIO_ICONFB2 = 0x18, +}; + +/*! + * This enumeration data type defines the configuration for input mode. + */ +typedef enum { + GPIO_INPUT_GPIO = 0x00, + GPIO_INPUT_INTR = 0x01, + GPIO_INPUT_LOW = 0x02, + GPIO_INPUT_HIGH = 0x03 +} gpio_input_cfg_t; + +/*! + * This enumeration data type defines the configuration for output mode. + */ +typedef enum { + GPIO_OUTPUT_A = 0x00, + GPIO_OUTPUT_B = 0x01, + GPIO_OUTPUT_C = 0x02, + GPIO_OUTPUT_DR = 0x03 +} gpio_output_cfg_t; + +extern struct mxc_gpio_port mxc_gpio_ports[]; + +/*! + * defines a spinlock to protected the accessing to gpio pin. + */ +DEFINE_SPINLOCK(gpio_mux_lock); + +/*! + * This function enable or disable the pullup feature to the pin. + * @param port a pointer of gpio port + * @param index the index of the pin in the port + * @param en 0 if disable pullup, otherwise enable it. + * @return none + */ +static inline void _gpio_set_puen(struct mxc_gpio_port *port, u32 index, + bool en) +{ + u32 reg; + + reg = __raw_readl(port->base + GPIO_PUEN); + if (en) { + reg |= 1 << index; + } else { + reg &= ~(1 << index); + } + __raw_writel(reg, port->base + GPIO_PUEN); +} + +/*! + * This function set the input configuration A. + * @param port a pointer of gpio port + * @param index the index of the pin in the port + * @param config a mode as define in \b #gpio_input_cfg_t + * @return none + */ +static inline void _gpio_set_iconfa(struct mxc_gpio_port *port, u32 index, + gpio_input_cfg_t config) +{ + u32 reg, val; + u32 mask; + + mask = 0x3 << ((index % 16) << 1); + + if (index >= 16) { + reg = port->base + GPIO_ICONFA2; + val = config << ((index - 16) * 2); + } else { + reg = port->base + GPIO_ICONFA1; + val = config << (index * 2); + } + val |= __raw_readl(reg) & ~(mask); + __raw_writel(val, reg); +} + +/*! + * This function set the input configuration B. + * @param port a pointer of gpio port + * @param index the index of the pin in the port + * @param config a mode as define in \b #gpio_input_cfg_t + * @return none + */ +static inline void _gpio_set_iconfb(struct mxc_gpio_port *port, u32 index, + gpio_input_cfg_t config) +{ + u32 reg, val; + u32 mask; + + mask = 0x3 << ((index % 16) << 1); + + if (index >= 16) { + reg = port->base + GPIO_ICONFB2; + val = config << ((index - 16) * 2); + } else { + reg = port->base + GPIO_ICONFB1; + val = config << (index * 2); + } + val |= __raw_readl(reg) & (~mask); + __raw_writel(val, reg); +} + +/*! + * This function set the output configuration. + * @param port a pointer of gpio port + * @param index the index of the pin in the port + * @param config a mode as define in \b #gpio_output_cfg_t + * @return none + */ +static inline void _gpio_set_ocr(struct mxc_gpio_port *port, u32 index, + gpio_output_cfg_t config) +{ + u32 reg, val; + u32 mask; + + mask = 0x3 << ((index % 16) << 1); + if (index >= 16) { + reg = port->base + GPIO_OCR2; + val = config << ((index - 16) * 2); + } else { + reg = port->base + GPIO_OCR1; + val = config << (index * 2); + } + val |= __raw_readl(reg) & (~mask); + __raw_writel(val, reg); +} + +/*! + *@brief gpio_config_mux - just configure the mode of the gpio pin. + *@param pin a pin number as defined in \b #iomux_pin_name_t + *@param mode a module as define in \b #gpio_mux_mode_t; + * GPIO_MUX_PRIMARY set pin to work as primary function. + * GPIO_MUX_ALT set pin to work as alternate function. + * GPIO_MUX_GPIO set pin to work as output function based the data register + * GPIO_MUX_INPUT1 set pin to work as input function connected with A_OUT + * GPIO_MUX_INPUT2 set pin to work as input function connected with B_OUT + * GPIO_MUX_OUTPUT1 set pin to work as output function connected with A_IN + * GPIO_MUX_OUTPUT2 set pin to work as output function connected with B_IN + * GPIO_MUX_OUTPUT3 set pin to work as output function connected with C_IN + *@return 0 if successful, Non-zero otherwise + */ + +int gpio_config_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode) +{ + unsigned long lock_flags; + u32 gius_reg, gpr_reg; + struct mxc_gpio_port *port; + u32 index, gpio = IOMUX_TO_GPIO(pin); + + port = &(mxc_gpio_ports[GPIO_TO_PORT(gpio)]); + index = GPIO_TO_INDEX(gpio); + + pr_debug("%s: Configuring PORT %c, bit %d\n", + __FUNCTION__, port->num + 'A', index); + + spin_lock_irqsave(&gpio_mux_lock, lock_flags); + + gius_reg = __raw_readl(port->base + GPIO_GIUS); + gpr_reg = __raw_readl(port->base + GPIO_GPR); + + switch (mode) { + case GPIO_MUX_PRIMARY: + gius_reg &= ~(1L << index); + gpr_reg &= ~(1L << index); + break; + case GPIO_MUX_ALT: + gius_reg &= ~(1L << index); + gpr_reg |= (1L << index); + break; + case GPIO_MUX_GPIO: + gius_reg |= (1L << index); + _gpio_set_ocr(port, index, GPIO_OUTPUT_DR); + break; + case GPIO_MUX_INPUT1: + gius_reg |= (1L << index); + _gpio_set_iconfa(port, index, GPIO_INPUT_GPIO); + break; + case GPIO_MUX_INPUT2: + gius_reg |= (1L << index); + _gpio_set_iconfb(port, index, GPIO_INPUT_GPIO); + break; + case GPIO_MUX_OUTPUT1: + gius_reg |= (1L << index); + _gpio_set_ocr(port, index, GPIO_OUTPUT_A); + break; + case GPIO_MUX_OUTPUT2: + gius_reg |= (1L << index); + _gpio_set_ocr(port, index, GPIO_OUTPUT_B); + break; + case GPIO_MUX_OUTPUT3: + gius_reg |= (1L << index); + _gpio_set_ocr(port, index, GPIO_OUTPUT_C); + break; + default: + spin_unlock_irqrestore(&gpio_mux_lock, lock_flags); + return -1; + } + + __raw_writel(gius_reg, port->base + GPIO_GIUS); + __raw_writel(gpr_reg, port->base + GPIO_GPR); + + spin_unlock_irqrestore(&gpio_mux_lock, lock_flags); + return 0; +} + +/*! + * This function is just used to enable or disable the pull up feature . + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param en 0 if disable, Non-zero enable + * @return 0 if successful, Non-zero otherwise + */ +int gpio_set_puen(iomux_pin_name_t pin, bool en) +{ + unsigned long lock_flags; + + struct mxc_gpio_port *port; + u32 index, gpio = IOMUX_TO_GPIO(pin); + + port = &(mxc_gpio_ports[GPIO_TO_PORT(gpio)]); + index = GPIO_TO_INDEX(gpio); + + pr_debug("%s: Configuring output mode of PORT %c, bit %d\n", + __FUNCTION__, port->num + 'A', index); + + spin_lock_irqsave(&gpio_mux_lock, lock_flags); + + _gpio_set_puen(port, index, en); + spin_unlock_irqrestore(&gpio_mux_lock, lock_flags); + return 0; + +} + +/*! + * This function is just used to request a pin and configure it. + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param mode a module as define in \b #gpio_mux_mode_t; + * @return 0 if successful, Non-zero otherwise + */ +int gpio_request_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode) +{ + int ret; + ret = mxc_request_gpio(pin); + if (ret == 0) { + ret = gpio_config_mux(pin, mode); + if (ret) { + mxc_free_gpio(pin); + } + } + return ret; +} + +/*! + * This function is just used to release a pin. + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @return none + */ +void gpio_free_mux(iomux_pin_name_t pin) +{ + mxc_free_gpio(pin); +} diff -urN linux-2.6.26/arch/arm/mach-mx27/gpio_mux.h linux-2.6.26-lab126/arch/arm/mach-mx27/gpio_mux.h --- linux-2.6.26/arch/arm/mach-mx27/gpio_mux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/gpio_mux.h 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,78 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + *@file mach-mx27/gpio_mux.h + *@brief This file contains the private definition . + * @ingroup GPIO_MX27 + */ + +#ifndef __ARCH_ARM_MACH_MX27_GPIO_MUX_H__ +#define __ARCH_ARM_MACH_MX27_GPIO_MUX_H__ + +#include "mx27_pins.h" + +/*! + * This enumeration data type defines the modes of the pin . + * GPIO_MUX_PRIMARY is the primary mode. + * GPIO_MUX_ALT is the alternate mode. + * GPIO_MUX_GPIO is the output mode and the signal source is data register. + * GPIO_MUX_INPUT1 is the input mode and the signal destination is A_OUT. + * GPIO_MUX_INPUT2 is the input mode and the signal destination is B_OUT. + * GPIO_MUX_OUTPUT1 is the output mode and the signal destination is A_IN. + * GPIO_MUX_OUTPUT2 is the output mode and the signal destination is B_IN. + * GPIO_MUX_OUTPUT3 is the output mode and the signal destination is C_IN. + */ +typedef enum { + GPIO_MUX_PRIMARY, + GPIO_MUX_ALT, + GPIO_MUX_GPIO, + GPIO_MUX_INPUT1, + GPIO_MUX_INPUT2, + GPIO_MUX_OUTPUT1, + GPIO_MUX_OUTPUT2, + GPIO_MUX_OUTPUT3, +} gpio_mux_mode_t; + +/*! + * This function is just used to request a pin and configure it. + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param mode a module as define in \b #gpio_mux_mode_t; + * @return 0 if successful, Non-zero otherwise + */ +extern int gpio_request_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode); + +/*! + * This function is just used to configure a pin . + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param mode a module as define in \b #gpio_mux_mode_t; + * @return 0 if successful, Non-zero otherwise + */ +extern int gpio_config_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode); + +/*! + * This function is just used to enable or disable the pull up feature . + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param en 0 if disable, Non-zero enable + * @return 0 if successful, Non-zero otherwise + */ +extern int gpio_set_puen(iomux_pin_name_t pin, bool en); + +/*! + * This function is just used to release a pin. + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @return none + */ +extern void gpio_free_mux(iomux_pin_name_t pin); + +#endif /* __ARCH_ARM_MACH_MX27_GPIO_MUX_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx27/mm.c linux-2.6.26-lab126/arch/arm/mach-mx27/mm.c --- linux-2.6.26/arch/arm/mach-mx27/mm.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/mm.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,62 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include + +/*! + * @file mach-mx27/mm.c + * + * @brief This file creates static mapping between physical to virtual memory. + * + * @ingroup Memory_MX27 + */ + +/*! + * This structure defines the MX27 memory map. + */ +static struct map_desc mxc_io_desc[] __initdata = { + { + .virtual = AIPI_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPI_BASE_ADDR), + .length = AIPI_SIZE, + .type = MT_DEVICE}, + { + .virtual = SAHB1_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(SAHB1_BASE_ADDR), + .length = SAHB1_SIZE, + .type = MT_DEVICE}, + { + .virtual = X_MEMC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR), + .length = X_MEMC_SIZE, + .type = MT_DEVICE}, + { + .virtual = CS4_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(CS4_BASE_ADDR), + .length = CS4_SIZE, + .type = MT_DEVICE} +}; + +/*! + * This function initializes the memory map. It is called during the + * system startup to create static physical to virtual memory map for + * the IO modules. + */ +void __init mxc_map_io(void) +{ + iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); +} diff -urN linux-2.6.26/arch/arm/mach-mx27/mx27_pins.h linux-2.6.26-lab126/arch/arm/mach-mx27/mx27_pins.h --- linux-2.6.26/arch/arm/mach-mx27/mx27_pins.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/mx27_pins.h 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,207 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_MX27_PINS_H__ +#define __ASM_ARCH_MXC_MX27_PINS_H__ + +/*! + * @file arch-mxc/mx27_pins.h + * + * @brief MX27 I/O Pin List + * + * @ingroup GPIO_MX27 + */ + +#ifndef __ASSEMBLY__ + +#define _MX27_BUILD_PIN(gp,gi) (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I)) + +enum iomux_pins { + MX27_PIN_USBH2_CLK = _MX27_BUILD_PIN(0, 0), + MX27_PIN_USBH2_DIR = _MX27_BUILD_PIN(0, 1), + MX27_PIN_USBH2_DATA7 = _MX27_BUILD_PIN(0, 2), + MX27_PIN_USBH2_NXT = _MX27_BUILD_PIN(0, 3), + MX27_PIN_USBH2_STP = _MX27_BUILD_PIN(0, 4), + MX27_PIN_LSCLK = _MX27_BUILD_PIN(0, 5), + MX27_PIN_LD0 = _MX27_BUILD_PIN(0, 6), + MX27_PIN_LD1 = _MX27_BUILD_PIN(0, 7), + MX27_PIN_LD2 = _MX27_BUILD_PIN(0, 8), + MX27_PIN_LD3 = _MX27_BUILD_PIN(0, 9), + MX27_PIN_LD4 = _MX27_BUILD_PIN(0, 10), + MX27_PIN_LD5 = _MX27_BUILD_PIN(0, 11), + MX27_PIN_LD6 = _MX27_BUILD_PIN(0, 12), + MX27_PIN_LD7 = _MX27_BUILD_PIN(0, 13), + MX27_PIN_LD8 = _MX27_BUILD_PIN(0, 14), + MX27_PIN_LD9 = _MX27_BUILD_PIN(0, 15), + MX27_PIN_LD10 = _MX27_BUILD_PIN(0, 16), + MX27_PIN_LD11 = _MX27_BUILD_PIN(0, 17), + MX27_PIN_LD12 = _MX27_BUILD_PIN(0, 18), + MX27_PIN_LD13 = _MX27_BUILD_PIN(0, 19), + MX27_PIN_LD14 = _MX27_BUILD_PIN(0, 20), + MX27_PIN_LD15 = _MX27_BUILD_PIN(0, 21), + MX27_PIN_LD16 = _MX27_BUILD_PIN(0, 22), + MX27_PIN_LD17 = _MX27_BUILD_PIN(0, 23), + MX27_PIN_REV = _MX27_BUILD_PIN(0, 24), + MX27_PIN_CLS = _MX27_BUILD_PIN(0, 25), + MX27_PIN_PS = _MX27_BUILD_PIN(0, 26), + MX27_PIN_SPL_SPR = _MX27_BUILD_PIN(0, 27), + MX27_PIN_HSYNC = _MX27_BUILD_PIN(0, 28), + MX27_PIN_VSYNC = _MX27_BUILD_PIN(0, 29), + MX27_PIN_CONTRAST = _MX27_BUILD_PIN(0, 30), + MX27_PIN_OE_ACD = _MX27_BUILD_PIN(0, 31), + + MX27_PIN_SD2_D0 = _MX27_BUILD_PIN(1, 4), + MX27_PIN_SD2_D1 = _MX27_BUILD_PIN(1, 5), + MX27_PIN_SD2_D2 = _MX27_BUILD_PIN(1, 6), + MX27_PIN_SD2_D3 = _MX27_BUILD_PIN(1, 7), + MX27_PIN_SD2_CMD = _MX27_BUILD_PIN(1, 8), + MX27_PIN_SD2_CLK = _MX27_BUILD_PIN(1, 9), + MX27_PIN_CSI_D0 = _MX27_BUILD_PIN(1, 10), + MX27_PIN_CSI_D1 = _MX27_BUILD_PIN(1, 11), + MX27_PIN_CSI_D2 = _MX27_BUILD_PIN(1, 12), + MX27_PIN_CSI_D3 = _MX27_BUILD_PIN(1, 13), + MX27_PIN_CSI_D4 = _MX27_BUILD_PIN(1, 14), + MX27_PIN_CSI_MCLK = _MX27_BUILD_PIN(1, 15), + MX27_PIN_CSI_PIXCLK = _MX27_BUILD_PIN(1, 16), + MX27_PIN_CSI_D5 = _MX27_BUILD_PIN(1, 17), + MX27_PIN_CSI_D6 = _MX27_BUILD_PIN(1, 18), + MX27_PIN_CSI_D7 = _MX27_BUILD_PIN(1, 19), + MX27_PIN_CSI_VSYNC = _MX27_BUILD_PIN(1, 20), + MX27_PIN_CSI_HSYNC = _MX27_BUILD_PIN(1, 21), + MX27_PIN_USBH1_SUSP = _MX27_BUILD_PIN(1, 22), + MX27_PIN_USB_PWR = _MX27_BUILD_PIN(1, 23), + MX27_PIN_USB_OC_B = _MX27_BUILD_PIN(1, 24), + MX27_PIN_USBH1_RCV = _MX27_BUILD_PIN(1, 25), + MX27_PIN_USBH1_FS = _MX27_BUILD_PIN(1, 26), + MX27_PIN_USBH1_OE_B = _MX27_BUILD_PIN(1, 27), + MX27_PIN_USBH1_TXDM = _MX27_BUILD_PIN(1, 28), + MX27_PIN_USBH1_TXDP = _MX27_BUILD_PIN(1, 29), + MX27_PIN_USBH1_RXDM = _MX27_BUILD_PIN(1, 30), + MX27_PIN_USBH1_RXDP = _MX27_BUILD_PIN(1, 31), + + MX27_PIN_I2C2_SDA = _MX27_BUILD_PIN(2, 5), + MX27_PIN_I2C2_SCL = _MX27_BUILD_PIN(2, 6), + MX27_PIN_USBOTG_DATA5 = _MX27_BUILD_PIN(2, 7), + MX27_PIN_USBOTG_DATA6 = _MX27_BUILD_PIN(2, 8), + MX27_PIN_USBOTG_DATA0 = _MX27_BUILD_PIN(2, 9), + MX27_PIN_USBOTG_DATA2 = _MX27_BUILD_PIN(2, 10), + MX27_PIN_USBOTG_DATA1 = _MX27_BUILD_PIN(2, 11), + MX27_PIN_USBOTG_DATA4 = _MX27_BUILD_PIN(2, 12), + MX27_PIN_USBOTG_DATA3 = _MX27_BUILD_PIN(2, 13), + MX27_PIN_TOUT = _MX27_BUILD_PIN(2, 14), + MX27_PIN_TIN = _MX27_BUILD_PIN(2, 15), + MX27_PIN_SSI4_FS = _MX27_BUILD_PIN(2, 16), + MX27_PIN_SSI4_RXDAT = _MX27_BUILD_PIN(2, 17), + MX27_PIN_SSI4_TXDAT = _MX27_BUILD_PIN(2, 18), + MX27_PIN_SSI4_CLK = _MX27_BUILD_PIN(2, 19), + MX27_PIN_SSI1_FS = _MX27_BUILD_PIN(2, 20), + MX27_PIN_SSI1_RXDAT = _MX27_BUILD_PIN(2, 21), + MX27_PIN_SSI1_TXDAT = _MX27_BUILD_PIN(2, 22), + MX27_PIN_SSI1_CLK = _MX27_BUILD_PIN(2, 23), + MX27_PIN_SSI2_FS = _MX27_BUILD_PIN(2, 24), + MX27_PIN_SSI2_RXDAT = _MX27_BUILD_PIN(2, 25), + MX27_PIN_SSI2_TXDAT = _MX27_BUILD_PIN(2, 26), + MX27_PIN_SSI2_CLK = _MX27_BUILD_PIN(2, 27), + MX27_PIN_SSI3_FS = _MX27_BUILD_PIN(2, 28), + MX27_PIN_SSI3_RXDAT = _MX27_BUILD_PIN(2, 29), + MX27_PIN_SSI3_TXDAT = _MX27_BUILD_PIN(2, 30), + MX27_PIN_SSI3_CLK = _MX27_BUILD_PIN(2, 31), + + MX27_PIN_SD3_CMD = _MX27_BUILD_PIN(3, 0), + MX27_PIN_SD3_CLK = _MX27_BUILD_PIN(3, 1), + MX27_PIN_ATA_DATA0 = _MX27_BUILD_PIN(3, 2), + MX27_PIN_ATA_DATA1 = _MX27_BUILD_PIN(3, 3), + MX27_PIN_ATA_DATA2 = _MX27_BUILD_PIN(3, 4), + MX27_PIN_ATA_DATA3 = _MX27_BUILD_PIN(3, 5), + MX27_PIN_ATA_DATA4 = _MX27_BUILD_PIN(3, 6), + MX27_PIN_ATA_DATA5 = _MX27_BUILD_PIN(3, 7), + MX27_PIN_ATA_DATA6 = _MX27_BUILD_PIN(3, 8), + MX27_PIN_ATA_DATA7 = _MX27_BUILD_PIN(3, 9), + MX27_PIN_ATA_DATA8 = _MX27_BUILD_PIN(3, 10), + MX27_PIN_ATA_DATA9 = _MX27_BUILD_PIN(3, 11), + MX27_PIN_ATA_DATA10 = _MX27_BUILD_PIN(3, 12), + MX27_PIN_ATA_DATA11 = _MX27_BUILD_PIN(3, 13), + MX27_PIN_ATA_DATA12 = _MX27_BUILD_PIN(3, 14), + MX27_PIN_ATA_DATA13 = _MX27_BUILD_PIN(3, 15), + MX27_PIN_ATA_DATA14 = _MX27_BUILD_PIN(3, 16), + MX27_PIN_I2C_DATA = _MX27_BUILD_PIN(3, 17), + MX27_PIN_I2C_CLK = _MX27_BUILD_PIN(3, 18), + MX27_PIN_CSPI2_SS2 = _MX27_BUILD_PIN(3, 19), + MX27_PIN_CSPI2_SS1 = _MX27_BUILD_PIN(3, 20), + MX27_PIN_CSPI2_SS0 = _MX27_BUILD_PIN(3, 21), + MX27_PIN_CSPI2_SCLK = _MX27_BUILD_PIN(3, 22), + MX27_PIN_CSPI2_MISO = _MX27_BUILD_PIN(3, 23), + MX27_PIN_CSPI2_MOSI = _MX27_BUILD_PIN(3, 24), + MX27_PIN_CSPI1_RDY = _MX27_BUILD_PIN(3, 25), + MX27_PIN_CSPI1_SS2 = _MX27_BUILD_PIN(3, 26), + MX27_PIN_CSPI1_SS1 = _MX27_BUILD_PIN(3, 27), + MX27_PIN_CSPI1_SS0 = _MX27_BUILD_PIN(3, 28), + MX27_PIN_CSPI1_SCLK = _MX27_BUILD_PIN(3, 29), + MX27_PIN_CSPI1_MISO = _MX27_BUILD_PIN(3, 30), + MX27_PIN_CSPI1_MOSI = _MX27_BUILD_PIN(3, 31), + + MX27_PIN_USBOTG_NXT = _MX27_BUILD_PIN(4, 0), + MX27_PIN_USBOTG_STP = _MX27_BUILD_PIN(4, 1), + MX27_PIN_USBOTG_DIR = _MX27_BUILD_PIN(4, 2), + MX27_PIN_UART2_CTS = _MX27_BUILD_PIN(4, 3), + MX27_PIN_UART2_RTS = _MX27_BUILD_PIN(4, 4), + MX27_PIN_PWMO = _MX27_BUILD_PIN(4, 5), + MX27_PIN_UART2_TXD = _MX27_BUILD_PIN(4, 6), + MX27_PIN_UART2_RXD = _MX27_BUILD_PIN(4, 7), + MX27_PIN_UART3_TXD = _MX27_BUILD_PIN(4, 8), + MX27_PIN_UART3_RXD = _MX27_BUILD_PIN(4, 9), + MX27_PIN_UART3_CTS = _MX27_BUILD_PIN(4, 10), + MX27_PIN_UART3_RTS = _MX27_BUILD_PIN(4, 11), + MX27_PIN_UART1_TXD = _MX27_BUILD_PIN(4, 12), + MX27_PIN_UART1_RXD = _MX27_BUILD_PIN(4, 13), + MX27_PIN_UART1_CTS = _MX27_BUILD_PIN(4, 14), + MX27_PIN_UART1_RTS = _MX27_BUILD_PIN(4, 15), + MX27_PIN_RTCK = _MX27_BUILD_PIN(4, 16), + MX27_PIN_RESET_OUT_B = _MX27_BUILD_PIN(4, 17), + MX27_PIN_SD1_D0 = _MX27_BUILD_PIN(4, 18), + MX27_PIN_SD1_D1 = _MX27_BUILD_PIN(4, 19), + MX27_PIN_SD1_D2 = _MX27_BUILD_PIN(4, 20), + MX27_PIN_SD1_D3 = _MX27_BUILD_PIN(4, 21), + MX27_PIN_SD1_CMD = _MX27_BUILD_PIN(4, 22), + MX27_PIN_SD1_CLK = _MX27_BUILD_PIN(4, 23), + MX27_PIN_USBOTG_CLK = _MX27_BUILD_PIN(4, 24), + MX27_PIN_USBOTG_DATA7 = _MX27_BUILD_PIN(4, 25), + + MX27_PIN_NFRB = _MX27_BUILD_PIN(5, 0), + MX27_PIN_NFCLE = _MX27_BUILD_PIN(5, 1), + MX27_PIN_NFWP_B = _MX27_BUILD_PIN(5, 2), + MX27_PIN_NFCE_B = _MX27_BUILD_PIN(5, 3), + MX27_PIN_NFALE = _MX27_BUILD_PIN(5, 4), + MX27_PIN_NFRE_B = _MX27_BUILD_PIN(5, 5), + MX27_PIN_NFWE_B = _MX27_BUILD_PIN(5, 6), + MX27_PIN_PC_POE = _MX27_BUILD_PIN(5, 7), + MX27_PIN_PC_RW_B = _MX27_BUILD_PIN(5, 8), + MX27_PIN_IOIS16 = _MX27_BUILD_PIN(5, 9), + MX27_PIN_PC_RST = _MX27_BUILD_PIN(5, 10), + MX27_PIN_PC_BVD2 = _MX27_BUILD_PIN(5, 11), + MX27_PIN_PC_BVD1 = _MX27_BUILD_PIN(5, 12), + MX27_PIN_PC_VS2 = _MX27_BUILD_PIN(5, 13), + MX27_PIN_PC_VS1 = _MX27_BUILD_PIN(5, 14), + MX27_PIN_CLKO = _MX27_BUILD_PIN(5, 15), + MX27_PIN_PC_PWRON = _MX27_BUILD_PIN(5, 16), + MX27_PIN_PC_READY = _MX27_BUILD_PIN(5, 17), + MX27_PIN_PC_WAIT_B = _MX27_BUILD_PIN(5, 18), + MX27_PIN_PC_CD2_B = _MX27_BUILD_PIN(5, 19), + MX27_PIN_PC_CD1_B = _MX27_BUILD_PIN(5, 20), + MX27_PIN_CS4_B = _MX27_BUILD_PIN(5, 21), + MX27_PIN_CS5_B = _MX27_BUILD_PIN(5, 22), + MX27_PIN_ATA_DATA15 = _MX27_BUILD_PIN(5, 23), +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_MXC_MX27_PINS_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx27/mx27ads.c linux-2.6.26-lab126/arch/arm/mach-mx27/mx27ads.c --- linux-2.6.26/arch/arm/mach-mx27/mx27ads.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/mx27ads.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,823 @@ +/* + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * Copyright 2006-2008 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE) +#include +#include +#include + +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "gpio_mux.h" +#include "board-mx27ads.h" + +/*! + * @file mach-mx27/mx27ads.c + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX27 + */ + +extern void mxc_map_io(void); +extern void mxc_init_irq(void); +extern void mxc_cpu_init(void) __init; +extern void mxc_clocks_init(void); +extern void mxc_cpu_common_init(void); +extern struct sys_timer mxc_timer; +extern void __init early_console_setup(char *); + +static char command_line[COMMAND_LINE_SIZE]; +static int mxc_card_status; +int mxc_board_is_ads = 1; + +static void mxc_nop_release(struct device *dev) +{ + /* Nothing */ +} + +unsigned long board_get_ckih_rate(void) +{ + if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0) { + return 27000000; + } + return 26000000; +} + +#if defined(CONFIG_CS89x0) || defined(CONFIG_CS89x0_MODULE) +/*! Null terminated portlist used to probe for the CS8900A device on ISA Bus + * Add 3 to reset the page window before probing (fixes eth probe when deployed + * using nand_boot) + */ +unsigned int netcard_portlist[] = { CS8900A_BASE_ADDRESS + 3, 0 }; + +EXPORT_SYMBOL(netcard_portlist); +/*! + * The CS8900A has 4 IRQ pins, which is software selectable, CS8900A interrupt + * pin 0 is used for interrupt generation. + */ +unsigned int cs8900_irq_map[] = { CS8900AIRQ, 0, 0, 0 }; + +EXPORT_SYMBOL(cs8900_irq_map); +#endif + +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) +unsigned int expio_intr_fec = MXC_EXP_IO_BASE + 7; + +EXPORT_SYMBOL(expio_intr_fec); +#endif + +#if defined(CONFIG_KEYBOARD_MXC) || defined(CONFIG_KEYBOARD_MXC_MODULE) + +/*! + * This array is used for mapping mx27 ADS keypad scancodes to input keyboard + * keycodes. + */ +static u16 mxckpd_keycodes[] = { + KEY_KP9, KEY_LEFTSHIFT, KEY_0, KEY_KPASTERISK, KEY_RECORD, KEY_POWER, + KEY_KP8, KEY_9, KEY_8, KEY_7, KEY_KP5, KEY_VOLUMEDOWN, + KEY_KP7, KEY_6, KEY_5, KEY_4, KEY_KP4, KEY_VOLUMEUP, + KEY_KP6, KEY_3, KEY_2, KEY_1, KEY_KP3, KEY_DOWN, + KEY_BACK, KEY_RIGHT, KEY_ENTER, KEY_LEFT, KEY_HOME, KEY_KP2, + KEY_END, KEY_F2, KEY_UP, KEY_F1, KEY_F4, KEY_KP1, +}; + +static struct keypad_data evb_6_by_6_keypad = { + .rowmax = 6, + .colmax = 6, + .irq = MXC_INT_KPP, + .learning = 0, + .delay = 2, + .matrix = mxckpd_keycodes, +}; + +static struct resource mxc_kpp_resources[] = { + [0] = { + .start = MXC_INT_KPP, + .end = MXC_INT_KPP, + .flags = IORESOURCE_IRQ, + } +}; + +/* mxc keypad driver */ +static struct platform_device mxc_keypad_device = { + .name = "mxc_keypad", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_kpp_resources), + .resource = mxc_kpp_resources, + .dev = { + .release = mxc_nop_release, + .platform_data = &evb_6_by_6_keypad, + }, +}; + +static void mxc_init_keypad(void) +{ + (void)platform_device_register(&mxc_keypad_device); +} +#else +static inline void mxc_init_keypad(void) +{ +} +#endif + +/* MTD NOR flash */ + +#if defined(CONFIG_MTD_MXC) || defined(CONFIG_MTD_MXC_MODULE) + +static struct mtd_partition mxc_nor_partitions[] = { + { + .name = "Bootloader", + .size = 512 * 1024, + .offset = 0x00000000, + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, + { + .name = "nor.Kernel", + .size = 2 * 1024 * 1024, + .offset = MTDPART_OFS_APPEND, + .mask_flags = 0}, + { + .name = "nor.userfs", + .size = 14 * 1024 * 1024, + .offset = MTDPART_OFS_APPEND, + .mask_flags = 0}, + { + .name = "nor.rootfs", + .size = 12 * 1024 * 1024, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE}, + { + .name = "FIS directory", + .size = 12 * 1024, + .offset = 0x01FE0000, + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, + { + .name = "Redboot config", + .size = MTDPART_SIZ_FULL, + .offset = 0x01FFF000, + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, +}; + +static struct flash_platform_data mxc_flash_data = { + .map_name = "cfi_probe", + .width = 2, + .parts = mxc_nor_partitions, + .nr_parts = ARRAY_SIZE(mxc_nor_partitions), +}; + +static struct resource mxc_flash_resource = { + .start = 0xc0000000, + .end = 0xc0000000 + 0x02000000 - 1, + .flags = IORESOURCE_MEM, + +}; + +static struct platform_device mxc_nor_mtd_device = { + .name = "mxc_nor_flash", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_flash_data, + }, + .num_resources = 1, + .resource = &mxc_flash_resource, +}; + +static void mxc_init_nor_mtd(void) +{ + (void)platform_device_register(&mxc_nor_mtd_device); +} +#else +static void mxc_init_nor_mtd(void) +{ +} +#endif + +/* MTD NAND flash */ + +#if defined(CONFIG_MTD_NAND_MXC) || defined(CONFIG_MTD_NAND_MXC_MODULE) + +static struct mtd_partition mxc_nand_partitions[4] = { + { + .name = "nand.bootloader", + .offset = 0, + .size = 1024 * 1024}, + { + .name = "nand.kernel", + .offset = MTDPART_OFS_APPEND, + .size = 5 * 1024 * 1024}, + { + .name = "nand.rootfs", + .offset = MTDPART_OFS_APPEND, + .size = 22 * 1024 * 1024}, + { + .name = "nand.userfs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL}, +}; + +static struct flash_platform_data mxc_nand_data = { + .parts = mxc_nand_partitions, + .nr_parts = ARRAY_SIZE(mxc_nand_partitions), + .width = 1, +}; + +static struct platform_device mxc_nand_mtd_device = { + .name = "mxc_nand_flash", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_nand_data, + }, +}; + +static void mxc_init_nand_mtd(void) +{ + (void)platform_device_register(&mxc_nand_mtd_device); +} +#else +static inline void mxc_init_nand_mtd(void) +{ +} +#endif + +#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) +static const char fb_default_mode[] = "Sharp-QVGA"; + +/* mxc lcd driver */ +static struct platform_device mxc_fb_device = { + .name = "mxc_sdc_fb", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &fb_default_mode, + .coherent_dma_mask = 0xFFFFFFFF, + }, +}; + +static void mxc_init_fb(void) +{ + (void)platform_device_register(&mxc_fb_device); +} +#else +static inline void mxc_init_fb(void) +{ +} +#endif + +#if defined(CONFIG_BACKLIGHT_MXC) +static struct platform_device mxcbl_devices[] = { +#if defined(CONFIG_BACKLIGHT_MXC_PMIC) || defined(CONFIG_BACKLIGHT_MXC_PMIC_MODULE) + { + .name = "mxc_pmic_bl", + .id = 0, + .dev = { + .platform_data = (void *)-1, /* DISP # for this backlight */ + }, + }, + { + .name = "mxc_pmic_bl", + .id = 1, + .dev = { + .platform_data = (void *)0, /* DISP # for this backlight */ + }, + }, +#endif +#if defined(CONFIG_BACKLIGHT_MXC_LCDC) || defined(CONFIG_BACKLIGHT_MXC_LCDC_MODULE) + { + .name = "mxc_lcdc_bl", + .id = 0, + .dev = { + .platform_data = (void *)3, /* DISP # for this backlight */ + }, + }, +#endif +}; +static inline void mxc_init_bl(void) +{ + int i; + for (i = 0; i < ARRAY_SIZE(mxcbl_devices); i++) { + platform_device_register(&mxcbl_devices[i]); + } +} +#else +static inline void mxc_init_bl(void) +{ +} +#endif + +static struct spi_board_info mxc_spi_board_info[] __initdata = { + { + .modalias = "pmic_spi", + .irq = IOMUX_TO_IRQ(MX27_PIN_TOUT), + .max_speed_hz = 4000000, + .bus_num = 1, + .chip_select = 0, + }, +}; + +#if 0 +#define MXC_CARD_DEBUG +#endif + +static const int pbc_card_bit[4][3] = { + /* BSTAT IMR enable IMR removal */ + {PBC_BSTAT_SD2_DET, PBC_INTR_SD2_EN, PBC_INTR_SD2_R_EN}, + {PBC_BSTAT_SD3_DET, PBC_INTR_SD3_EN, PBC_INTR_SD3_R_EN}, + {PBC_BSTAT_MS_DET, PBC_INTR_MS_EN, PBC_INTR_MS_R_EN}, + {PBC_BSTAT_SD1_DET, PBC_INTR_SD1_EN, PBC_INTR_SD1_R_EN}, +}; + +/*! + * Check if a SD card has been inserted or not. + * + * @param num a card number as defined in \b enum \b mxc_card_no + * @return 0 if a card is not present; non-zero otherwise. + */ +int mxc_card_detected(enum mxc_card_no num) +{ + u32 status; + + status = __raw_readw(PBC_BSTAT1_REG); + return ((status & MXC_BSTAT_BIT(num)) == 0); +} + +/* + * Check if there is any state change by reading the IMR register and the + * previous and current states of the board status register (offset 0x28). + * A state change is defined to be card insertion OR removal. So the driver + * may have to call the mxc_card_detected() function to see if it is card + * insertion or removal. + * + * @param mask current IMR value + * @param s0 previous status register value (offset 0x28) + * @param s1 current status register value (offset 0x28) + * + * @return 0 if no card status change OR the corresponding bits in the IMR + * (passed in as 'mask') is NOT set. + * A non-zero value indicates some card state changes. For example, + * 0b0001 means SD3 has a card state change (bit0 is set) AND its + * associated insertion or removal bits in IMR is SET. + * 0b0100 means SD1 has a card state change (bit2 is set) AND its + * associated insertion or removal bits in IMR is SET. + * 0b1001 means both MS and SD3 have state changes + */ +static u32 mxc_card_state_changed(u32 mask, u32 s0, u32 s1) +{ + u32 i, retval = 0; + u32 stat = (s0 ^ s1) & 0x7800; + + if (stat == 0) + return 0; + + for (i = MXC_CARD_MIN; i <= MXC_CARD_MAX; i++) { + if ((stat & pbc_card_bit[i][0]) != 0 && + (mask & (pbc_card_bit[i][1] | pbc_card_bit[i][2])) != 0) { + retval |= 1 << i; + } + } +#ifdef MXC_CARD_DEBUG + printk(KERN_INFO "\nmask=%x, s0=%x, s1=%x\n", mask, s0, s1); + printk(KERN_INFO "retval=%x, stat=%x\n", retval, stat); +#endif + return retval; +} + +/*! + * Interrupt handler for the expio (CPLD) to deal with interrupts from + * FEC, external UART, CS8900 Ethernet and SD cards, etc. + */ +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) +{ + u32 imr, card_int, i; + u32 int_valid; + u32 expio_irq; + u32 stat = __raw_readw(PBC_BSTAT1_REG); + + desc->chip->mask(irq); /* irq = gpio irq number */ + + imr = __raw_readw(PBC_INTMASK_SET_REG); + + card_int = mxc_card_state_changed(imr, mxc_card_status, stat); + mxc_card_status = stat; + + if (card_int != 0) { + for (i = MXC_CARD_MIN; i <= MXC_CARD_MAX; i++) { + if ((card_int & (1 << i)) != 0) { + pr_debug("card no %d state changed\n", i); + } + } + } + + /* Bits defined in PBC_INTSTATUS_REG at 0x2C */ + int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr; + /* combined with the card interrupt valid information */ + int_valid = (int_valid & 0x0F8E) | (card_int << PBC_INTR_SD2_EN_BIT); + + if (unlikely(!int_valid)) { + pr_debug("\nEXPIO: Spurious interrupt:0x%0x\n\n", int_valid); + pr_debug("CPLD IMR(0x38)=0x%x, BSTAT1(0x28)=0x%x\n", imr, stat); + goto out; + } + + expio_irq = MXC_EXP_IO_BASE; + for (; int_valid != 0; int_valid >>= 1, expio_irq++) { + struct irq_desc *d; + if ((int_valid & 1) == 0) + continue; + d = irq_desc + expio_irq; + if (unlikely(!(d->handle_irq))) { + printk(KERN_ERR "\nEXPIO irq: %d unhandeled\n", + expio_irq); + BUG(); /* oops */ + } + d->handle_irq(expio_irq, d); + } + + out: + desc->chip->ack(irq); + desc->chip->unmask(irq); +} + +#ifdef MXC_CARD_DEBUG + +static irqreturn_t mxc_sd_test_handler(int irq, void *desc) +{ + int s = -1; + + printk(KERN_INFO "%s(irq=%d) for ", __FUNCTION__, irq); + if (irq == EXPIO_INT_SD1_EN) { + printk(KERN_INFO "SD1"); + s = MXC_CARD_SD1; + } else if (irq == EXPIO_INT_SD2_EN) { + printk(KERN_INFO "SD2"); + s = MXC_CARD_SD2; + } else if (irq == EXPIO_INT_SD3_EN) { + printk(KERN_INFO "SD3"); + s = MXC_CARD_SD3; + } else if (irq == EXPIO_INT_MS_EN) { + printk(KERN_INFO "MS"); + s = MXC_CARD_MS; + } else { + printk(KERN_INFO "None!!!!"); + } + if (mxc_card_detected(s)) { + printk(KERN_INFO " inserted\n"); + } else { + printk(KERN_INFO " removed\n"); + } + + return IRQ_HANDLED; +} +#endif /* MXC_CARD_DEBUG */ + +/* + * Disable an expio pin's interrupt by setting the bit in the imr. + * @param irq an expio virtual irq number + */ +static void expio_mask_irq(u32 irq) +{ + u32 expio = MXC_IRQ_TO_EXPIO(irq); + + /* mask the interrupt */ + if (irq < EXPIO_INT_SD2_EN) { + __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG); + } else { + irq -= EXPIO_INT_SD2_EN; + /* clear both SDx_EN and SDx_R_EN bits */ + __raw_writew((pbc_card_bit[irq][1] | pbc_card_bit[irq][2]), + PBC_INTMASK_CLEAR_REG); + } +} + +/* + * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. + * @param irq an expanded io virtual irq number + */ +static void expio_ack_irq(u32 irq) +{ + u32 expio = MXC_IRQ_TO_EXPIO(irq); + /* clear the interrupt status */ + __raw_writew(1 << expio, PBC_INTSTATUS_REG); + /* mask the interrupt */ + expio_mask_irq(irq); +} + +/* + * Enable a expio pin's interrupt by clearing the bit in the imr. + * @param irq an expio virtual irq number + */ +static void expio_unmask_irq(u32 irq) +{ + u32 expio = MXC_IRQ_TO_EXPIO(irq); + + /* unmask the interrupt */ + if (irq < EXPIO_INT_SD2_EN) { + if (irq == EXPIO_INT_XUART_INTA) { + /* Set 8250 MCR register bit 3 - Forces the INT (A-B + * outputs to the active mode and sets OP2 to logic 0. + * This is needed to avoid spurious int caused by the + * internal CPLD pull-up for the interrupt pin. + */ + u16 val = __raw_readw(MXC_LL_EXTUART_VADDR + 8); + __raw_writew(val | 0x8, MXC_LL_EXTUART_VADDR + 8); + } + __raw_writew(1 << expio, PBC_INTMASK_SET_REG); + } else { + irq -= EXPIO_INT_SD2_EN; + + if (mxc_card_detected(irq)) { + __raw_writew(pbc_card_bit[irq][2], PBC_INTMASK_SET_REG); + } else { + __raw_writew(pbc_card_bit[irq][1], PBC_INTMASK_SET_REG); + } + } +} + +static struct irq_chip expio_irq_chip = { + .ack = expio_ack_irq, + .mask = expio_mask_irq, + .unmask = expio_unmask_irq, +}; + +static int __init mxc_expio_init(void) +{ + int i, ver; + + ver = (__raw_readw(PBC_VERSION_REG) >> 8) & 0xFF; + if ((ver & 0x80) != 0) { + pr_info("MX27 ADS EXPIO(CPLD) hardware\n"); + pr_info("CPLD version: 0x%x\n", ver); + } else { + mxc_board_is_ads = 0; + ver &= 0x0F; + pr_info("MX27 EVB EXPIO(CPLD) hardware\n"); + if (ver == 0xF || ver <= MXC_CPLD_VER_1_50) + pr_info("Wrong CPLD version: %d\n", ver); + else { + pr_info("CPLD version: %d\n", ver); + } + } + + mxc_card_status = __raw_readw(PBC_BSTAT1_REG); + +#ifdef MXC_CARD_DEBUG + for (i = MXC_CARD_MIN; i <= MXC_CARD_MAX; i++) { + if (mxc_card_detected(i)) { + pr_info("Card %d is detected\n", 3 - i); + } + } +#endif + /* + * Configure INT line as GPIO input + */ + gpio_config_mux(MX27_PIN_TIN, GPIO_MUX_GPIO); + mxc_set_gpio_direction(MX27_PIN_TIN, 1); + + /* disable the interrupt and clear the status */ + __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG); + __raw_writew(0xFFFF, PBC_INTSTATUS_REG); + + for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); + i++) { + set_irq_chip(i, &expio_irq_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + set_irq_type(EXPIO_PARENT_INT, IRQT_HIGH); + set_irq_chained_handler(EXPIO_PARENT_INT, mxc_expio_irq_handler); + + return 0; +} + +#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) + +/*! + * The serial port definition structure. The fields contain: + * {UART, CLK, PORT, IRQ, FLAGS} + */ +static struct plat_serial8250_port serial_platform_data[] = { + { + .membase = (void __iomem *)(CS4_BASE_ADDR_VIRT + 0x20000), + .mapbase = (unsigned long)(CS4_BASE_ADDR + 0x20000), + .irq = EXPIO_INT_XUART_INTA, + .uartclk = 3686400, + .regshift = 1, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ, + /*.pm = serial_platform_pm, */ + }, + {}, +}; + +/*! + * REVISIT: document me + */ +static struct platform_device serial_device = { + .name = "serial8250", + .id = 0, + .dev = { + .platform_data = &serial_platform_data[0], + }, +}; + +/*! + * REVISIT: document me + */ +static int __init mxc_init_extuart(void) +{ + int value; + /*reset ext uart in cpld */ + __raw_writew(PBC_BCTRL1_URST, PBC_BCTRL1_SET_REG); + /*delay some time for reset finish */ + for (value = 0; value < 1000; value++) ; + __raw_writew(PBC_BCTRL1_URST, PBC_BCTRL1_CLEAR_REG); + return platform_device_register(&serial_device); +} +#else +static inline int mxc_init_extuart(void) +{ + return 0; +} +#endif + +#if (defined(CONFIG_MXC_PMIC_MC13783) || \ + defined(CONFIG_MXC_PMIC_MC13783_MODULE)) \ + && (defined(CONFIG_SND_MXC_PMIC) || defined(CONFIG_SND_MXC_PMIC_MODULE)) +extern void gpio_ssi_active(int ssi_num); + +static void __init mxc_init_pmic_audio(void) +{ + struct clk *ckih_clk; + struct clk *cko_clk; + + /* Enable 26 mhz clock on CKO1 for PMIC audio */ + ckih_clk = clk_get(NULL, "ckih"); + cko_clk = clk_get(NULL, "clko_clk"); + if (IS_ERR(ckih_clk) || IS_ERR(cko_clk)) { + printk(KERN_ERR "Unable to set CLKO output to CKIH\n"); + } else { + clk_set_parent(cko_clk, ckih_clk); + clk_set_rate(cko_clk, clk_get_rate(ckih_clk)); + clk_enable(cko_clk); + } + clk_put(ckih_clk); + clk_put(cko_clk); + + gpio_ssi_active(0); + gpio_ssi_active(1); +} +#else +static void __inline mxc_init_pmic_audio(void) +{ +} +#endif + +/* IDE device data */ +#if defined(CONFIG_BLK_DEV_IDE_MXC) || defined(CONFIG_BLK_DEV_IDE_MXC_MODULE) + +/*! Platform Data for MXC IDE */ +static struct mxc_ide_platform_data mxc_ide_data = { + .power_drive = NULL, + .power_io = NULL, +}; + +static struct platform_device mxc_ide_device = { + .name = "mxc_ide", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_ide_data, + }, +}; + +static inline void mxc_init_ide(void) +{ + if (platform_device_register(&mxc_ide_device) < 0) + printk(KERN_ERR "Error: Registering the ide.\n"); +} +#else +static inline void mxc_init_ide(void) +{ +} +#endif + +static __init void mxc_board_init(void) +{ + pr_info("AIPI VA base: 0x%x\n", IO_ADDRESS(AIPI_BASE_ADDR)); + mxc_cpu_common_init(); + mxc_clocks_init(); + early_console_setup(saved_command_line); + mxc_gpio_init(); + mxc_expio_init(); + mxc_init_keypad(); + mxc_init_nor_mtd(); + mxc_init_nand_mtd(); + mxc_init_extuart(); + mxc_init_pmic_audio(); +#ifdef MXC_CARD_DEBUG + request_irq(EXPIO_INT_SD1_EN, mxc_sd_test_handler, 0, "SD_card1", NULL); + request_irq(EXPIO_INT_SD2_EN, mxc_sd_test_handler, 0, "SD_card2", NULL); + request_irq(EXPIO_INT_SD3_EN, mxc_sd_test_handler, 0, "SD_card3", NULL); + request_irq(EXPIO_INT_MS_EN, mxc_sd_test_handler, 0, "MS_card", NULL); +#endif + + spi_register_board_info(mxc_spi_board_info, + ARRAY_SIZE(mxc_spi_board_info)); + + mxc_init_fb(); + mxc_init_bl(); + mxc_init_ide(); +} + +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ +#ifdef CONFIG_KGDB_8250 + int i; + for (i = 0; + i < + (sizeof(serial_platform_data) / sizeof(serial_platform_data[0])); + i += 1) + kgdb8250_add_platform_port(i, &serial_platform_data[i]); +#endif + + mxc_cpu_init(); + /* Store command line for use on mxc_board_init */ + strcpy(command_line, *cmdline); + +#ifdef CONFIG_DISCONTIGMEM + do { + int nid; + mi->nr_banks = MXC_NUMNODES; + for (nid = 0; nid < mi->nr_banks; nid++) { + SET_NODE(mi, nid); + } + } while (0); +#endif +} + +EXPORT_SYMBOL(mxc_card_detected); +EXPORT_SYMBOL(mxc_board_is_ads); + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX27ADS data structure. + */ +/* *INDENT-OFF* */ +MACHINE_START(MX27ADS, "Freescale i.MX27ADS") + /* maintainer: Freescale Semiconductor, Inc. */ +#ifdef CONFIG_SERIAL_8250_CONSOLE + .phys_io = CS4_BASE_ADDR, + .io_pg_offst = ((CS4_BASE_ADDR_VIRT) >> 18) & 0xfffc, +#else + .phys_io = AIPI_BASE_ADDR, + .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, +#endif + .boot_params = PHYS_OFFSET + 0x100, + .fixup = fixup_mxc_board, + .map_io = mxc_map_io, + .init_irq = mxc_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff -urN linux-2.6.26/arch/arm/mach-mx27/mx27ads_gpio.c linux-2.6.26-lab126/arch/arm/mach-mx27/mx27ads_gpio.c --- linux-2.6.26/arch/arm/mach-mx27/mx27ads_gpio.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/mx27ads_gpio.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,1226 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include + +#include "board-mx27ads.h" +#include "gpio_mux.h" +#include "crm_regs.h" + +static int g_uart_activated[MXC_UART_NR] = { 0, 0, 0, 0, 0, 0 }; + +/*! + * @file mach-mx27/mx27ads_gpio.c + * + * @brief This file contains all the GPIO setup functions for the board. + * + * @ingroup GPIO_MX27 + */ + +/*! + * Setup GPIO for a UART port to be active + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_active(int port, int no_irda) +{ + if (port < 0 || port >= MXC_UART_NR) { + pr_info("Wrong port number: %d\n", port); + BUG(); + } + + if (g_uart_activated[port]) { + pr_info("UART %d has been activated multi-times\n", port + 1); + return; + } + g_uart_activated[port] = 1; + + switch (port) { + case 0: + gpio_request_mux(MX27_PIN_UART1_TXD, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_UART1_RXD, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_UART1_CTS, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_UART1_RTS, GPIO_MUX_PRIMARY); + break; + case 1: + gpio_request_mux(MX27_PIN_UART2_TXD, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_UART2_RXD, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_UART2_CTS, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_UART2_RTS, GPIO_MUX_PRIMARY); + break; + case 2: + gpio_request_mux(MX27_PIN_UART3_TXD, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_UART3_RXD, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_UART3_CTS, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_UART3_RTS, GPIO_MUX_PRIMARY); + + /* Enable IRDA in CPLD */ + __raw_writew(PBC_BCTRL2_IRDA_EN, PBC_BCTRL2_CLEAR_REG); + break; + case 3: + gpio_request_mux(MX27_PIN_USBH1_TXDM, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_USBH1_RXDP, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_USBH1_TXDP, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_USBH1_FS, GPIO_MUX_ALT); + break; + case 4: + gpio_request_mux(MX27_PIN_CSI_D6, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_CSI_D7, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_CSI_VSYNC, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_CSI_HSYNC, GPIO_MUX_ALT); + break; + case 5: + gpio_request_mux(MX27_PIN_CSI_D0, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_CSI_D1, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_CSI_D2, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_CSI_D3, GPIO_MUX_ALT); + break; + default: + break; + } +} + +/*! + * Setup GPIO for a UART port to be inactive + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_inactive(int port, int no_irda) +{ + if (port < 0 || port >= MXC_UART_NR) { + pr_info("Wrong port number: %d\n", port); + BUG(); + } + + if (g_uart_activated[port] == 0) { + pr_info("UART %d has not been activated \n", port + 1); + return; + } + g_uart_activated[port] = 0; + + switch (port) { + case 0: + gpio_free_mux(MX27_PIN_UART1_TXD); + gpio_free_mux(MX27_PIN_UART1_RXD); + gpio_free_mux(MX27_PIN_UART1_CTS); + gpio_free_mux(MX27_PIN_UART1_RTS); + break; + case 1: + gpio_free_mux(MX27_PIN_UART2_TXD); + gpio_free_mux(MX27_PIN_UART2_RXD); + gpio_free_mux(MX27_PIN_UART2_CTS); + gpio_free_mux(MX27_PIN_UART2_RTS); + break; + case 2: + gpio_free_mux(MX27_PIN_UART3_TXD); + gpio_free_mux(MX27_PIN_UART3_RXD); + gpio_free_mux(MX27_PIN_UART3_CTS); + gpio_free_mux(MX27_PIN_UART3_RTS); + + /* Disable IRDA in CPLD */ + __raw_writew(PBC_BCTRL2_IRDA_EN, PBC_BCTRL2_SET_REG); + break; + case 3: + gpio_free_mux(MX27_PIN_USBH1_TXDM); + gpio_free_mux(MX27_PIN_USBH1_RXDP); + gpio_free_mux(MX27_PIN_USBH1_TXDP); + gpio_free_mux(MX27_PIN_USBH1_FS); + break; + case 4: + gpio_free_mux(MX27_PIN_CSI_D6); + gpio_free_mux(MX27_PIN_CSI_D7); + gpio_free_mux(MX27_PIN_CSI_VSYNC); + gpio_free_mux(MX27_PIN_CSI_HSYNC); + break; + case 5: + gpio_free_mux(MX27_PIN_CSI_D0); + gpio_free_mux(MX27_PIN_CSI_D1); + gpio_free_mux(MX27_PIN_CSI_D2); + gpio_free_mux(MX27_PIN_CSI_D3); + break; + default: + break; + } +} + +void gpio_power_key_active(void) +{ +} +EXPORT_SYMBOL(gpio_power_key_active); + +/*! + * Configure the IOMUX GPR register to receive shared SDMA UART events + * + * @param port a UART port + */ +void config_uartdma_event(int port) +{ + return; +} + +static int usbh1_hs_active; +/*! + * Setup GPIO for USB, Total 34 signals + * PIN Configuration for USBOTG: High/Full speed OTG + * PE2,PE1,PE0,PE24,PE25 -- PRIMARY + PC7 - PC13 -- PRIMARY + PB23,PB24 -- PRIMARY + + * PIN Configuration for USBH2: : High/Full/Low speed host + * PA0 - PA4 -- PRIMARY + PD19, PD20,PD21,PD22,PD23,PD24,PD26 --Alternate (SECONDARY) + + * PIN Configuration for USBH1: Full/low speed host + * PB25 - PB31 -- PRIMARY + PB22 -- PRIMARY + */ +int gpio_usbh1_active(void) +{ + if (usbh1_hs_active) + return 0; + + if (gpio_request_mux(MX27_PIN_USBH1_SUSP, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBH1_RCV, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBH1_FS, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBH1_OE_B, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBH1_TXDM, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBH1_TXDP, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBH1_RXDM, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBH1_RXDP, GPIO_MUX_PRIMARY)) + return -EINVAL; + + __raw_writew(PBC_BCTRL3_FSH_MOD, PBC_BCTRL3_CLEAR_REG); + __raw_writew(PBC_BCTRL3_FSH_VBUS_EN, PBC_BCTRL3_CLEAR_REG); + usbh1_hs_active = 1; + return 0; +} +void gpio_usbh1_inactive(void) +{ + if (usbh1_hs_active == 0) + return; + + gpio_free_mux(MX27_PIN_USBH1_SUSP); + gpio_free_mux(MX27_PIN_USBH1_RCV); + gpio_free_mux(MX27_PIN_USBH1_FS); + gpio_free_mux(MX27_PIN_USBH1_OE_B); + gpio_free_mux(MX27_PIN_USBH1_TXDM); + gpio_free_mux(MX27_PIN_USBH1_TXDP); + gpio_free_mux(MX27_PIN_USBH1_RXDM); + gpio_free_mux(MX27_PIN_USBH1_RXDP); + __raw_writew(PBC_BCTRL3_FSH_VBUS_EN, PBC_BCTRL3_SET_REG); + + usbh1_hs_active = 0; +} + +static int usbh2_hs_active; +/* + * conflicts with CSPI1 (MC13783) and CSPI2 (Connector) + */ +int gpio_usbh2_active(void) +{ + if (usbh2_hs_active) + return 0; + + if (gpio_set_puen(MX27_PIN_USBH2_CLK, 0) || + gpio_set_puen(MX27_PIN_USBH2_DIR, 0) || + gpio_set_puen(MX27_PIN_USBH2_DATA7, 0) || + gpio_set_puen(MX27_PIN_USBH2_NXT, 0) || + gpio_set_puen(MX27_PIN_USBH2_STP, 0) || + gpio_set_puen(MX27_PIN_CSPI2_SS2, 0) || + gpio_set_puen(MX27_PIN_CSPI2_SS1, 0) || + gpio_set_puen(MX27_PIN_CSPI2_SS0, 0) || + gpio_set_puen(MX27_PIN_CSPI2_SCLK, 0) || + gpio_set_puen(MX27_PIN_CSPI2_MISO, 0) || + gpio_set_puen(MX27_PIN_CSPI2_MOSI, 0) || + gpio_set_puen(MX27_PIN_CSPI1_SS2, 0)) + return -EINVAL; + + if (gpio_request_mux(MX27_PIN_USBH2_CLK, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBH2_DIR, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBH2_DATA7, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBH2_NXT, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBH2_STP, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_CSPI2_SS2, GPIO_MUX_ALT) || + gpio_request_mux(MX27_PIN_CSPI2_SS1, GPIO_MUX_ALT) || + gpio_request_mux(MX27_PIN_CSPI2_SS0, GPIO_MUX_ALT) || + gpio_request_mux(MX27_PIN_CSPI2_SCLK, GPIO_MUX_ALT) || + gpio_request_mux(MX27_PIN_CSPI2_MISO, GPIO_MUX_ALT) || + gpio_request_mux(MX27_PIN_CSPI2_MOSI, GPIO_MUX_ALT) || + gpio_request_mux(MX27_PIN_CSPI1_SS2, GPIO_MUX_ALT)) + return -EINVAL; + + __raw_writew(PBC_BCTRL3_HSH_EN, PBC_BCTRL3_CLEAR_REG); + usbh2_hs_active = 1; + return 0; +} +void gpio_usbh2_inactive(void) +{ + if (usbh2_hs_active == 0) + return; + + gpio_free_mux(MX27_PIN_USBH2_CLK); + gpio_free_mux(MX27_PIN_USBH2_DIR); + gpio_free_mux(MX27_PIN_USBH2_DATA7); + gpio_free_mux(MX27_PIN_USBH2_NXT); + gpio_free_mux(MX27_PIN_USBH2_STP); + + gpio_free_mux(MX27_PIN_CSPI2_SS2); + gpio_free_mux(MX27_PIN_CSPI2_SS1); + gpio_free_mux(MX27_PIN_CSPI2_SS0); + gpio_free_mux(MX27_PIN_CSPI2_SCLK); + gpio_free_mux(MX27_PIN_CSPI2_MISO); + gpio_free_mux(MX27_PIN_CSPI2_MOSI); + gpio_free_mux(MX27_PIN_CSPI1_SS2); + + gpio_set_puen(MX27_PIN_USBH2_CLK, 1); + gpio_set_puen(MX27_PIN_USBH2_DIR, 1); + gpio_set_puen(MX27_PIN_USBH2_DATA7, 1); + gpio_set_puen(MX27_PIN_USBH2_NXT, 1); + gpio_set_puen(MX27_PIN_USBH2_STP, 1); + gpio_set_puen(MX27_PIN_CSPI2_SS2, 1); + gpio_set_puen(MX27_PIN_CSPI2_SS1, 1); + gpio_set_puen(MX27_PIN_CSPI2_SS0, 1); + gpio_set_puen(MX27_PIN_CSPI2_SCLK, 1); + gpio_set_puen(MX27_PIN_CSPI2_MISO, 1); + gpio_set_puen(MX27_PIN_CSPI2_MOSI, 1); + gpio_set_puen(MX27_PIN_CSPI1_SS2, 1); + __raw_writew(PBC_BCTRL3_HSH_EN, PBC_BCTRL3_SET_REG); + + usbh2_hs_active = 0; +} + +static int usbotg_hs_active; +int gpio_usbotg_hs_active(void) +{ + if (usbotg_hs_active) + return 0; + + if (gpio_request_mux(MX27_PIN_USBOTG_DATA5, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBOTG_DATA6, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBOTG_DATA0, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBOTG_DATA2, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBOTG_DATA1, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBOTG_DATA3, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBOTG_DATA4, GPIO_MUX_PRIMARY) || + + gpio_request_mux(MX27_PIN_USBOTG_DIR, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBOTG_STP, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBOTG_NXT, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBOTG_CLK, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USBOTG_DATA7, GPIO_MUX_PRIMARY) || + + gpio_request_mux(MX27_PIN_USB_OC_B, GPIO_MUX_PRIMARY) || + gpio_request_mux(MX27_PIN_USB_PWR, GPIO_MUX_PRIMARY)) + return -EINVAL; + + __raw_writew(PBC_BCTRL3_OTG_HS_EN, PBC_BCTRL3_CLEAR_REG); + __raw_writew(PBC_BCTRL3_OTG_VBUS_EN, PBC_BCTRL3_CLEAR_REG); + + usbotg_hs_active = 1; + return 0; +} + +void gpio_usbotg_hs_inactive(void) +{ + if (usbotg_hs_active == 0) + return; + + gpio_free_mux(MX27_PIN_USBOTG_DATA5); + gpio_free_mux(MX27_PIN_USBOTG_DATA6); + gpio_free_mux(MX27_PIN_USBOTG_DATA0); + gpio_free_mux(MX27_PIN_USBOTG_DATA2); + gpio_free_mux(MX27_PIN_USBOTG_DATA1); + gpio_free_mux(MX27_PIN_USBOTG_DATA3); + gpio_free_mux(MX27_PIN_USBOTG_DATA4); + + gpio_free_mux(MX27_PIN_USBOTG_DIR); + gpio_free_mux(MX27_PIN_USBOTG_STP); + gpio_free_mux(MX27_PIN_USBOTG_NXT); + gpio_free_mux(MX27_PIN_USBOTG_CLK); + gpio_free_mux(MX27_PIN_USBOTG_DATA7); + + gpio_free_mux(MX27_PIN_USB_OC_B); + gpio_free_mux(MX27_PIN_USB_PWR); + __raw_writew(PBC_BCTRL3_OTG_HS_EN, PBC_BCTRL3_SET_REG); + + usbotg_hs_active = 0; +} + +int gpio_usbotg_fs_active(void) +{ + return gpio_usbotg_hs_active(); +} + +void gpio_usbotg_fs_inactive(void) +{ + gpio_usbotg_hs_inactive(); +} + +/*! + * end Setup GPIO for USB + * + */ + +/************************************************************************/ +/* for i2c gpio */ +/* I2C1: PD17,PD18 -- Primary */ +/* I2C2: PC5,PC6 -- Primary */ +/************************************************************************/ +/*! +* Setup GPIO for an I2C device to be active +* +* @param i2c_num an I2C device +*/ +void gpio_i2c_active(int i2c_num) +{ + switch (i2c_num) { + case 0: + gpio_request_mux(MX27_PIN_I2C_CLK, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_I2C_DATA, GPIO_MUX_PRIMARY); + break; + case 1: + gpio_request_mux(MX27_PIN_I2C2_SCL, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_I2C2_SDA, GPIO_MUX_PRIMARY); + break; + default: + printk(KERN_ERR "gpio_i2c_active no compatible I2C adapter\n"); + break; + } +} + +/*! + * * Setup GPIO for an I2C device to be inactive + * * + * * @param i2c_num an I2C device + */ +void gpio_i2c_inactive(int i2c_num) +{ + switch (i2c_num) { + case 0: + gpio_free_mux(MX27_PIN_I2C_CLK); + gpio_free_mux(MX27_PIN_I2C_DATA); + break; + case 1: + gpio_free_mux(MX27_PIN_I2C2_SCL); + gpio_free_mux(MX27_PIN_I2C2_SDA); + break; + default: + break; + } +} + +/*! + * Setup GPIO for a CSPI device to be active + * + * @param cspi_mod an CSPI device + */ +void gpio_spi_active(int cspi_mod) +{ + switch (cspi_mod) { + case 0: + /* SPI1 */ + gpio_request_mux(MX27_PIN_CSPI1_MOSI, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSPI1_MISO, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSPI1_SCLK, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSPI1_RDY, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSPI1_SS0, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSPI1_SS1, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSPI1_SS2, GPIO_MUX_PRIMARY); + break; + case 1: + /*SPI2 */ + gpio_request_mux(MX27_PIN_CSPI2_MOSI, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSPI2_MISO, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSPI2_SCLK, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSPI2_SS0, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSPI2_SS1, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSPI2_SS2, GPIO_MUX_PRIMARY); + break; + case 2: + /*SPI3 */ + gpio_request_mux(MX27_PIN_SD1_D0, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_SD1_CMD, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_SD1_CLK, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_SD1_D3, GPIO_MUX_ALT); + break; + + default: + break; + } +} + +/*! + * Setup GPIO for a CSPI device to be inactive + * + * @param cspi_mod a CSPI device + */ +void gpio_spi_inactive(int cspi_mod) +{ + switch (cspi_mod) { + case 0: + /* SPI1 */ + gpio_free_mux(MX27_PIN_CSPI1_MOSI); + gpio_free_mux(MX27_PIN_CSPI1_MISO); + gpio_free_mux(MX27_PIN_CSPI1_SCLK); + gpio_free_mux(MX27_PIN_CSPI1_RDY); + gpio_free_mux(MX27_PIN_CSPI1_SS0); + gpio_free_mux(MX27_PIN_CSPI1_SS1); + gpio_free_mux(MX27_PIN_CSPI1_SS2); + break; + case 1: + /*SPI2 */ + gpio_free_mux(MX27_PIN_CSPI2_MOSI); + gpio_free_mux(MX27_PIN_CSPI2_MISO); + gpio_free_mux(MX27_PIN_CSPI2_SCLK); + gpio_free_mux(MX27_PIN_CSPI2_SS0); + gpio_free_mux(MX27_PIN_CSPI2_SS1); + gpio_free_mux(MX27_PIN_CSPI2_SS2); + break; + case 2: + /*SPI3 */ + gpio_free_mux(MX27_PIN_SD1_D0); + gpio_free_mux(MX27_PIN_SD1_CMD); + gpio_free_mux(MX27_PIN_SD1_CLK); + gpio_free_mux(MX27_PIN_SD1_D3); + break; + + default: + break; + } +} + +/*! + * Setup GPIO for a nand flash device to be active + * + */ +void gpio_nand_active(void) +{ + unsigned long reg; + reg = __raw_readl(IO_ADDRESS(SYSCTRL_BASE_ADDR) + SYS_FMCR); + reg &= ~(1 << 4); + __raw_writel(reg, IO_ADDRESS(SYSCTRL_BASE_ADDR) + SYS_FMCR); + + gpio_request_mux(MX27_PIN_NFRB, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_NFCE_B, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_NFWP_B, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_NFCLE, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_NFALE, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_NFRE_B, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_NFWE_B, GPIO_MUX_PRIMARY); +} + +/*! + * Setup GPIO for a nand flash device to be inactive + * + */ +void gpio_nand_inactive(void) +{ + gpio_free_mux(MX27_PIN_NFRB); + gpio_free_mux(MX27_PIN_NFCE_B); + gpio_free_mux(MX27_PIN_NFWP_B); + gpio_free_mux(MX27_PIN_NFCLE); + gpio_free_mux(MX27_PIN_NFALE); + gpio_free_mux(MX27_PIN_NFRE_B); + gpio_free_mux(MX27_PIN_NFWE_B); +} + +/*! + * Setup GPIO for CSI device to be active + * + */ +void gpio_sensor_active(void) +{ + gpio_request_mux(MX27_PIN_CSI_D0, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSI_D1, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSI_D2, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSI_D3, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSI_D4, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSI_MCLK, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSI_PIXCLK, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSI_D5, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSI_D6, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSI_D7, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSI_VSYNC, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CSI_HSYNC, GPIO_MUX_PRIMARY); + +#ifdef CONFIG_MXC_CAMERA_MC521DA + __raw_writew(0x100, PBC_BCTRL2_SET_REG); +#else + __raw_writew(0x400, PBC_BCTRL2_SET_REG); +#endif +} + +void gpio_sensor_inactive(void) +{ + gpio_free_mux(MX27_PIN_CSI_D0); + gpio_free_mux(MX27_PIN_CSI_D1); + gpio_free_mux(MX27_PIN_CSI_D2); + gpio_free_mux(MX27_PIN_CSI_D3); + gpio_free_mux(MX27_PIN_CSI_D4); + gpio_free_mux(MX27_PIN_CSI_MCLK); + gpio_free_mux(MX27_PIN_CSI_PIXCLK); + gpio_free_mux(MX27_PIN_CSI_D5); + gpio_free_mux(MX27_PIN_CSI_D6); + gpio_free_mux(MX27_PIN_CSI_D7); + gpio_free_mux(MX27_PIN_CSI_VSYNC); + gpio_free_mux(MX27_PIN_CSI_HSYNC); + +#ifdef CONFIG_MXC_CAMERA_MC521DA + __raw_writew(0x100, PBC_BCTRL2_CLEAR_REG); +#else + __raw_writew(0x400, PBC_BCTRL2_CLEAR_REG); +#endif +} + +void gpio_sensor_reset(bool flag) +{ + u16 temp; + + if (flag) { + temp = 0x200; + __raw_writew(temp, PBC_BCTRL2_CLEAR_REG); + } else { + temp = 0x200; + __raw_writew(temp, PBC_BCTRL2_SET_REG); + } +} + +/*! + * Setup GPIO for LCDC device to be active + * + */ +void gpio_lcdc_active(void) +{ + gpio_request_mux(MX27_PIN_LSCLK, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_LD0, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_LD1, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_LD2, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_LD3, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_LD4, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_LD5, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_LD6, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_LD7, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_LD8, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_LD9, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_LD10, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_LD11, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_LD12, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_LD13, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_LD14, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_LD15, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_LD16, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_LD17, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_REV, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CLS, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_PS, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_SPL_SPR, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_HSYNC, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_VSYNC, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_CONTRAST, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_OE_ACD, GPIO_MUX_PRIMARY); +} + +/*! + * Setup GPIO for LCDC device to be inactive + * + */ +void gpio_lcdc_inactive(void) +{ + gpio_free_mux(MX27_PIN_LSCLK); + gpio_free_mux(MX27_PIN_LD0); + gpio_free_mux(MX27_PIN_LD1); + gpio_free_mux(MX27_PIN_LD2); + gpio_free_mux(MX27_PIN_LD3); + gpio_free_mux(MX27_PIN_LD4); + gpio_free_mux(MX27_PIN_LD5); + gpio_free_mux(MX27_PIN_LD6); + gpio_free_mux(MX27_PIN_LD7); + gpio_free_mux(MX27_PIN_LD8); + gpio_free_mux(MX27_PIN_LD9); + gpio_free_mux(MX27_PIN_LD10); + gpio_free_mux(MX27_PIN_LD11); + gpio_free_mux(MX27_PIN_LD12); + gpio_free_mux(MX27_PIN_LD13); + gpio_free_mux(MX27_PIN_LD14); + gpio_free_mux(MX27_PIN_LD15); + gpio_free_mux(MX27_PIN_LD16); + gpio_free_mux(MX27_PIN_LD17); + gpio_free_mux(MX27_PIN_REV); + gpio_free_mux(MX27_PIN_CLS); + gpio_free_mux(MX27_PIN_PS); + gpio_free_mux(MX27_PIN_SPL_SPR); + gpio_free_mux(MX27_PIN_HSYNC); + gpio_free_mux(MX27_PIN_VSYNC); + gpio_free_mux(MX27_PIN_CONTRAST); + gpio_free_mux(MX27_PIN_OE_ACD); +} + +/*! + * Setup GPIO PA25 low to start hard reset FS453 TV encoder + * + */ +void gpio_fs453_reset_low(void) +{ + gpio_free_mux(MX27_PIN_CLS); + if (gpio_request_mux(MX27_PIN_CLS, GPIO_MUX_GPIO)) { + printk(KERN_ERR "bug: request GPIO PA25 failed.\n"); + return; + } + + /* PA25 (CLS) as output */ + mxc_set_gpio_direction(MX27_PIN_CLS, 0); + gpio_config_mux(MX27_PIN_CLS, GPIO_MUX_GPIO); + mxc_set_gpio_dataout(MX27_PIN_CLS, 0); +} + +/*! + * Setup GPIO PA25 high to end hard reset FS453 TV encoder + * + */ +void gpio_fs453_reset_high(void) +{ + gpio_free_mux(MX27_PIN_CLS); + if (gpio_request_mux(MX27_PIN_CLS, GPIO_MUX_GPIO)) { + printk(KERN_ERR "bug: request GPIO PA25 failed.\n"); + return; + } + + /* PA25 (CLS) as output */ + mxc_set_gpio_direction(MX27_PIN_CLS, 0); + gpio_config_mux(MX27_PIN_CLS, GPIO_MUX_GPIO); + mxc_set_gpio_dataout(MX27_PIN_CLS, 1); +} + +/*! + * This function configures the IOMux block for PMIC standard operations. + * + */ +void gpio_pmic_active(void) +{ + gpio_config_mux(MX27_PIN_TOUT, GPIO_MUX_GPIO); + mxc_set_gpio_direction(MX27_PIN_TOUT, 1); +} + +/*! + * GPIO settings not required for keypad + * + */ +void gpio_keypad_active(void) +{ +} + +/*! + * GPIO settings not required for keypad + * + */ +void gpio_keypad_inactive(void) +{ +} + +/*! + * Setup GPIO for ATA device to be active + * + */ +void gpio_ata_active(void) +{ + gpio_request_mux(MX27_PIN_ATA_DATA0, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_ATA_DATA1, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_ATA_DATA2, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_ATA_DATA3, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_ATA_DATA4, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_ATA_DATA5, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_ATA_DATA6, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_ATA_DATA7, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_ATA_DATA8, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_ATA_DATA9, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_ATA_DATA10, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_ATA_DATA11, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_ATA_DATA12, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_ATA_DATA13, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_ATA_DATA14, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_ATA_DATA15, GPIO_MUX_PRIMARY); + + gpio_request_mux(MX27_PIN_PC_CD1_B, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_PC_CD2_B, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_PC_WAIT_B, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_PC_READY, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_PC_PWRON, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_PC_VS1, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_PC_VS2, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_PC_BVD1, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_PC_BVD2, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_PC_RST, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_IOIS16, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_PC_RW_B, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_PC_POE, GPIO_MUX_ALT); + + __raw_writew(PBC_BCTRL2_ATAFEC_EN | PBC_BCTRL2_ATAFEC_SEL | + PBC_BCTRL2_ATA_EN, PBC_BCTRL2_CLEAR_REG); +} + +/*! + * Setup GPIO for ATA device to be inactive + * + */ +void gpio_ata_inactive(void) +{ + __raw_writew(PBC_BCTRL2_ATAFEC_EN | PBC_BCTRL2_ATAFEC_SEL | + PBC_BCTRL2_ATA_EN, PBC_BCTRL2_SET_REG); + + gpio_free_mux(MX27_PIN_ATA_DATA0); + gpio_free_mux(MX27_PIN_ATA_DATA1); + gpio_free_mux(MX27_PIN_ATA_DATA2); + gpio_free_mux(MX27_PIN_ATA_DATA3); + gpio_free_mux(MX27_PIN_ATA_DATA4); + gpio_free_mux(MX27_PIN_ATA_DATA5); + gpio_free_mux(MX27_PIN_ATA_DATA6); + gpio_free_mux(MX27_PIN_ATA_DATA7); + gpio_free_mux(MX27_PIN_ATA_DATA8); + gpio_free_mux(MX27_PIN_ATA_DATA9); + gpio_free_mux(MX27_PIN_ATA_DATA10); + gpio_free_mux(MX27_PIN_ATA_DATA11); + gpio_free_mux(MX27_PIN_ATA_DATA12); + gpio_free_mux(MX27_PIN_ATA_DATA13); + gpio_free_mux(MX27_PIN_ATA_DATA14); + gpio_free_mux(MX27_PIN_ATA_DATA15); + + gpio_free_mux(MX27_PIN_PC_CD1_B); + gpio_free_mux(MX27_PIN_PC_CD2_B); + gpio_free_mux(MX27_PIN_PC_WAIT_B); + gpio_free_mux(MX27_PIN_PC_READY); + gpio_free_mux(MX27_PIN_PC_PWRON); + gpio_free_mux(MX27_PIN_PC_VS1); + gpio_free_mux(MX27_PIN_PC_VS2); + gpio_free_mux(MX27_PIN_PC_BVD1); + gpio_free_mux(MX27_PIN_PC_BVD2); + gpio_free_mux(MX27_PIN_PC_RST); + gpio_free_mux(MX27_PIN_IOIS16); + gpio_free_mux(MX27_PIN_PC_RW_B); + gpio_free_mux(MX27_PIN_PC_POE); +} + +/*! + * Setup GPIO for FEC device to be active + * + */ +void gpio_fec_active(void) +{ + gpio_request_mux(MX27_PIN_ATA_DATA15, GPIO_MUX_OUTPUT1); + mxc_set_gpio_direction(MX27_PIN_ATA_DATA15, 0); + gpio_request_mux(MX27_PIN_ATA_DATA14, GPIO_MUX_OUTPUT1); + mxc_set_gpio_direction(MX27_PIN_ATA_DATA14, 0); + gpio_request_mux(MX27_PIN_ATA_DATA13, GPIO_MUX_INPUT1); + mxc_set_gpio_direction(MX27_PIN_ATA_DATA13, 1); + gpio_request_mux(MX27_PIN_ATA_DATA12, GPIO_MUX_INPUT1); + mxc_set_gpio_direction(MX27_PIN_ATA_DATA12, 1); + gpio_request_mux(MX27_PIN_ATA_DATA11, GPIO_MUX_INPUT1); + mxc_set_gpio_direction(MX27_PIN_ATA_DATA11, 1); + gpio_request_mux(MX27_PIN_ATA_DATA10, GPIO_MUX_INPUT1); + mxc_set_gpio_direction(MX27_PIN_ATA_DATA10, 1); + gpio_request_mux(MX27_PIN_ATA_DATA9, GPIO_MUX_INPUT1); + mxc_set_gpio_direction(MX27_PIN_ATA_DATA9, 1); + gpio_request_mux(MX27_PIN_ATA_DATA8, GPIO_MUX_INPUT1); + mxc_set_gpio_direction(MX27_PIN_ATA_DATA8, 1); + gpio_request_mux(MX27_PIN_ATA_DATA7, GPIO_MUX_OUTPUT1); + mxc_set_gpio_direction(MX27_PIN_ATA_DATA7, 0); + + gpio_request_mux(MX27_PIN_ATA_DATA6, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_ATA_DATA5, GPIO_MUX_INPUT1); + mxc_set_gpio_direction(MX27_PIN_ATA_DATA5, 1); + gpio_request_mux(MX27_PIN_ATA_DATA4, GPIO_MUX_INPUT1); + mxc_set_gpio_direction(MX27_PIN_ATA_DATA4, 1); + gpio_request_mux(MX27_PIN_ATA_DATA3, GPIO_MUX_INPUT1); + mxc_set_gpio_direction(MX27_PIN_ATA_DATA3, 1); + gpio_request_mux(MX27_PIN_ATA_DATA2, GPIO_MUX_INPUT1); + mxc_set_gpio_direction(MX27_PIN_ATA_DATA2, 1); + gpio_request_mux(MX27_PIN_ATA_DATA1, GPIO_MUX_OUTPUT1); + mxc_set_gpio_direction(MX27_PIN_ATA_DATA1, 0); + gpio_request_mux(MX27_PIN_ATA_DATA0, GPIO_MUX_OUTPUT1); + mxc_set_gpio_direction(MX27_PIN_ATA_DATA0, 0); + gpio_request_mux(MX27_PIN_SD3_CLK, GPIO_MUX_OUTPUT1); + mxc_set_gpio_direction(MX27_PIN_SD3_CLK, 0); + gpio_request_mux(MX27_PIN_SD3_CMD, GPIO_MUX_OUTPUT1); + mxc_set_gpio_direction(MX27_PIN_SD3_CMD, 0); + + __raw_writew(PBC_BCTRL2_ATAFEC_EN, PBC_BCTRL2_CLEAR_REG); + __raw_writew(PBC_BCTRL2_ATAFEC_SEL, PBC_BCTRL2_SET_REG); +} + +/*! + * Setup GPIO for FEC device to be inactive + * + */ +void gpio_fec_inactive(void) +{ + gpio_free_mux(MX27_PIN_ATA_DATA0); + gpio_free_mux(MX27_PIN_ATA_DATA1); + gpio_free_mux(MX27_PIN_ATA_DATA2); + gpio_free_mux(MX27_PIN_ATA_DATA3); + gpio_free_mux(MX27_PIN_ATA_DATA4); + gpio_free_mux(MX27_PIN_ATA_DATA5); + gpio_free_mux(MX27_PIN_ATA_DATA6); + gpio_free_mux(MX27_PIN_ATA_DATA7); + gpio_free_mux(MX27_PIN_ATA_DATA8); + gpio_free_mux(MX27_PIN_ATA_DATA9); + gpio_free_mux(MX27_PIN_ATA_DATA10); + gpio_free_mux(MX27_PIN_ATA_DATA11); + gpio_free_mux(MX27_PIN_ATA_DATA12); + gpio_free_mux(MX27_PIN_ATA_DATA13); + gpio_free_mux(MX27_PIN_ATA_DATA14); + gpio_free_mux(MX27_PIN_ATA_DATA15); + + gpio_free_mux(MX27_PIN_SD3_CMD); + gpio_free_mux(MX27_PIN_SD3_CLK); +} + +/*! + * Setup GPIO for SLCDC device to be active + * + */ +void gpio_slcdc_active(int type) +{ + switch (type) { + case 0: + gpio_request_mux(MX27_PIN_SSI3_CLK, GPIO_MUX_ALT); /* CLK */ + gpio_request_mux(MX27_PIN_SSI3_TXDAT, GPIO_MUX_ALT); /* CS */ + gpio_request_mux(MX27_PIN_SSI3_RXDAT, GPIO_MUX_ALT); /* RS */ + gpio_request_mux(MX27_PIN_SSI3_FS, GPIO_MUX_ALT); /* D0 */ + break; + + case 1: + gpio_request_mux(MX27_PIN_SD2_D1, GPIO_MUX_GPIO); /* CLK */ + gpio_request_mux(MX27_PIN_SD2_D2, GPIO_MUX_GPIO); /* D0 */ + gpio_request_mux(MX27_PIN_SD2_D3, GPIO_MUX_GPIO); /* RS */ + gpio_request_mux(MX27_PIN_SD2_CMD, GPIO_MUX_GPIO); /* CS */ + break; + + case 2: + gpio_request_mux(MX27_PIN_LD0, GPIO_MUX_GPIO); + gpio_request_mux(MX27_PIN_LD1, GPIO_MUX_GPIO); + gpio_request_mux(MX27_PIN_LD2, GPIO_MUX_GPIO); + gpio_request_mux(MX27_PIN_LD3, GPIO_MUX_GPIO); + gpio_request_mux(MX27_PIN_LD4, GPIO_MUX_GPIO); + gpio_request_mux(MX27_PIN_LD5, GPIO_MUX_GPIO); + gpio_request_mux(MX27_PIN_LD6, GPIO_MUX_GPIO); + gpio_request_mux(MX27_PIN_LD7, GPIO_MUX_GPIO); + gpio_request_mux(MX27_PIN_LD8, GPIO_MUX_GPIO); + gpio_request_mux(MX27_PIN_LD9, GPIO_MUX_GPIO); + gpio_request_mux(MX27_PIN_LD10, GPIO_MUX_GPIO); + gpio_request_mux(MX27_PIN_LD11, GPIO_MUX_GPIO); + gpio_request_mux(MX27_PIN_LD12, GPIO_MUX_GPIO); + gpio_request_mux(MX27_PIN_LD13, GPIO_MUX_GPIO); + gpio_request_mux(MX27_PIN_LD14, GPIO_MUX_GPIO); + gpio_request_mux(MX27_PIN_LD15, GPIO_MUX_GPIO); + break; + + default: + break; + } + + return; +} + +/*! + * Setup GPIO for SLCDC device to be inactive + * + */ +void gpio_slcdc_inactive(int type) +{ + switch (type) { + case 0: + gpio_free_mux(MX27_PIN_SSI3_CLK); /* CLK */ + gpio_free_mux(MX27_PIN_SSI3_TXDAT); /* CS */ + gpio_free_mux(MX27_PIN_SSI3_RXDAT); /* RS */ + gpio_free_mux(MX27_PIN_SSI3_FS); /* D0 */ + break; + + case 1: + gpio_free_mux(MX27_PIN_SD2_D1); /* CLK */ + gpio_free_mux(MX27_PIN_SD2_D2); /* D0 */ + gpio_free_mux(MX27_PIN_SD2_D3); /* RS */ + gpio_free_mux(MX27_PIN_SD2_CMD); /* CS */ + break; + + case 2: + gpio_free_mux(MX27_PIN_LD0); + gpio_free_mux(MX27_PIN_LD1); + gpio_free_mux(MX27_PIN_LD2); + gpio_free_mux(MX27_PIN_LD3); + gpio_free_mux(MX27_PIN_LD4); + gpio_free_mux(MX27_PIN_LD5); + gpio_free_mux(MX27_PIN_LD6); + gpio_free_mux(MX27_PIN_LD7); + gpio_free_mux(MX27_PIN_LD8); + gpio_free_mux(MX27_PIN_LD9); + gpio_free_mux(MX27_PIN_LD10); + gpio_free_mux(MX27_PIN_LD11); + gpio_free_mux(MX27_PIN_LD12); + gpio_free_mux(MX27_PIN_LD13); + gpio_free_mux(MX27_PIN_LD14); + gpio_free_mux(MX27_PIN_LD15); + break; + + default: + break; + } + + return; +} + +void gpio_ssi_active(int ssi_num) +{ + switch (ssi_num) { + case 0: + gpio_request_mux(MX27_PIN_SSI1_FS, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_SSI1_RXDAT, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_SSI1_TXDAT, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_SSI1_CLK, GPIO_MUX_PRIMARY); + gpio_set_puen(MX27_PIN_SSI1_FS, 0); + gpio_set_puen(MX27_PIN_SSI1_RXDAT, 0); + gpio_set_puen(MX27_PIN_SSI1_TXDAT, 0); + gpio_set_puen(MX27_PIN_SSI1_CLK, 0); + break; + case 1: + gpio_request_mux(MX27_PIN_SSI2_FS, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_SSI2_RXDAT, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_SSI2_TXDAT, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_SSI2_CLK, GPIO_MUX_PRIMARY); + gpio_set_puen(MX27_PIN_SSI2_FS, 0); + gpio_set_puen(MX27_PIN_SSI2_RXDAT, 0); + gpio_set_puen(MX27_PIN_SSI2_TXDAT, 0); + gpio_set_puen(MX27_PIN_SSI2_CLK, 0); + break; + default: + break; + } + return; +} + +/*! + * * Setup GPIO for a SSI port to be inactive + * * + * * @param ssi_num an SSI port num + */ + +void gpio_ssi_inactive(int ssi_num) +{ + switch (ssi_num) { + case 0: + gpio_free_mux(MX27_PIN_SSI1_FS); + gpio_free_mux(MX27_PIN_SSI1_RXDAT); + gpio_free_mux(MX27_PIN_SSI1_TXDAT); + gpio_free_mux(MX27_PIN_SSI1_CLK); + break; + case 1: + gpio_free_mux(MX27_PIN_SSI2_FS); + gpio_free_mux(MX27_PIN_SSI2_RXDAT); + gpio_free_mux(MX27_PIN_SSI2_TXDAT); + gpio_free_mux(MX27_PIN_SSI2_CLK); + break; + default: + break; + } + return; +} + +/*! + * Setup GPIO for SDHC to be active + * + * @param module SDHC module number + */ +void gpio_sdhc_active(int module) +{ + u16 data; + switch (module) { + case 0: + gpio_request_mux(MX27_PIN_SD1_CLK, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_SD1_CMD, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_SD1_D0, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_SD1_D1, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_SD1_D2, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_SD1_D3, GPIO_MUX_PRIMARY); + /* 22k pull up for sd1 dat3 pins */ + data = __raw_readw(IO_ADDRESS(SYSCTRL_BASE_ADDR + 0x54)); + data |= 0x0c; + __raw_writew(data, IO_ADDRESS(SYSCTRL_BASE_ADDR + 0x54)); + /*mxc_clks_enable(SDHC1_CLK); + mxc_clks_enable(PERCLK2); */ + break; + case 1: + gpio_request_mux(MX27_PIN_SD2_CLK, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_SD2_CMD, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_SD2_D0, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_SD2_D1, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_SD2_D2, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_SD2_D3, GPIO_MUX_PRIMARY); + /* 22k pull up for sd2 pins */ + data = __raw_readw(IO_ADDRESS(SYSCTRL_BASE_ADDR + 0x54)); + data &= ~0xfff0; + data |= 0xfff0; + __raw_writew(data, IO_ADDRESS(SYSCTRL_BASE_ADDR + 0x54)); + /*mxc_clks_enable(SDHC2_CLK); + mxc_clks_enable(PERCLK2); */ + break; + case 2: + gpio_request_mux(MX27_PIN_SD3_CLK, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_SD3_CMD, GPIO_MUX_PRIMARY); + gpio_request_mux(MX27_PIN_ATA_DATA0, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_ATA_DATA1, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_ATA_DATA2, GPIO_MUX_ALT); + gpio_request_mux(MX27_PIN_ATA_DATA3, GPIO_MUX_ALT); + /*mxc_clks_enable(SDHC3_CLK); + mxc_clks_enable(PERCLK2); */ + break; + default: + break; + } +} + +/*! + * Setup GPIO for SDHC1 to be inactive + * + * @param module SDHC module number + */ +void gpio_sdhc_inactive(int module) +{ + switch (module) { + case 0: + gpio_free_mux(MX27_PIN_SD1_CLK); + gpio_free_mux(MX27_PIN_SD1_CMD); + gpio_free_mux(MX27_PIN_SD1_D0); + gpio_free_mux(MX27_PIN_SD1_D1); + gpio_free_mux(MX27_PIN_SD1_D2); + gpio_free_mux(MX27_PIN_SD1_D3); + /*mxc_clks_disable(SDHC1_CLK); */ + break; + case 1: + gpio_free_mux(MX27_PIN_SD2_CLK); + gpio_free_mux(MX27_PIN_SD2_CMD); + gpio_free_mux(MX27_PIN_SD2_D0); + gpio_free_mux(MX27_PIN_SD2_D1); + gpio_free_mux(MX27_PIN_SD2_D2); + gpio_free_mux(MX27_PIN_SD2_D3); + /*mxc_clks_disable(SDHC2_CLK); */ + break; + case 2: + gpio_free_mux(MX27_PIN_SD3_CLK); + gpio_free_mux(MX27_PIN_SD3_CMD); + gpio_free_mux(MX27_PIN_ATA_DATA0); + gpio_free_mux(MX27_PIN_ATA_DATA1); + gpio_free_mux(MX27_PIN_ATA_DATA2); + gpio_free_mux(MX27_PIN_ATA_DATA3); + /*mxc_clks_disable(SDHC3_CLK); */ + break; + default: + break; + } +} + +/* + * Probe for the card. If present the GPIO data would be set. + */ +int sdhc_get_card_det_status(struct device *dev) +{ + return 0; +} + +/* + * Return the card detect pin. + */ +int sdhc_init_card_det(int id) +{ + int ret = 0; + switch (id) { + case 0: + ret = EXPIO_INT_SD1_EN; + break; + case 1: + ret = EXPIO_INT_SD2_EN; + break; + default: + ret = 0; + break; + } + return ret; +} + +/* + * Power on/off Sharp QVGA panel. + */ +void board_power_lcd(int on) +{ + if (on) + __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG); + else + __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG); +} + +void gpio_owire_active(void) +{ + gpio_request_mux(MX27_PIN_RTCK, GPIO_MUX_ALT); +} + +void gpio_owire_inactive(void) +{ + gpio_request_mux(MX27_PIN_RTCK, GPIO_MUX_PRIMARY); +} + +EXPORT_SYMBOL(gpio_uart_active); +EXPORT_SYMBOL(gpio_uart_inactive); +EXPORT_SYMBOL(config_uartdma_event); +EXPORT_SYMBOL(gpio_usbh1_active); +EXPORT_SYMBOL(gpio_usbh1_inactive); +EXPORT_SYMBOL(gpio_usbh2_active); +EXPORT_SYMBOL(gpio_usbh2_inactive); +EXPORT_SYMBOL(gpio_usbotg_hs_active); +EXPORT_SYMBOL(gpio_usbotg_hs_inactive); +EXPORT_SYMBOL(gpio_usbotg_fs_active); +EXPORT_SYMBOL(gpio_usbotg_fs_inactive); +EXPORT_SYMBOL(gpio_i2c_active); +EXPORT_SYMBOL(gpio_i2c_inactive); +EXPORT_SYMBOL(gpio_spi_active); +EXPORT_SYMBOL(gpio_spi_inactive); +EXPORT_SYMBOL(gpio_nand_active); +EXPORT_SYMBOL(gpio_nand_inactive); +EXPORT_SYMBOL(gpio_sensor_active); +EXPORT_SYMBOL(gpio_sensor_inactive); +EXPORT_SYMBOL(gpio_sensor_reset); +EXPORT_SYMBOL(gpio_lcdc_active); +EXPORT_SYMBOL(gpio_lcdc_inactive); +EXPORT_SYMBOL(gpio_fs453_reset_low); +EXPORT_SYMBOL(gpio_fs453_reset_high); +EXPORT_SYMBOL(gpio_pmic_active); +EXPORT_SYMBOL(gpio_keypad_active); +EXPORT_SYMBOL(gpio_keypad_inactive); +EXPORT_SYMBOL(gpio_ata_active); +EXPORT_SYMBOL(gpio_ata_inactive); +EXPORT_SYMBOL(gpio_fec_active); +EXPORT_SYMBOL(gpio_fec_inactive); +EXPORT_SYMBOL(gpio_slcdc_active); +EXPORT_SYMBOL(gpio_slcdc_inactive); +EXPORT_SYMBOL(gpio_ssi_active); +EXPORT_SYMBOL(gpio_ssi_inactive); +EXPORT_SYMBOL(gpio_sdhc_active); +EXPORT_SYMBOL(gpio_sdhc_inactive); +EXPORT_SYMBOL(sdhc_get_card_det_status); +EXPORT_SYMBOL(sdhc_init_card_det); +EXPORT_SYMBOL(board_power_lcd); +EXPORT_SYMBOL(gpio_owire_active); +EXPORT_SYMBOL(gpio_owire_inactive); diff -urN linux-2.6.26/arch/arm/mach-mx27/mxc_pm.c linux-2.6.26-lab126/arch/arm/mach-mx27/mxc_pm.c --- linux-2.6.26/arch/arm/mach-mx27/mxc_pm.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/mxc_pm.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,458 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup DPM_MX27 Power Management + * @ingroup MSL_MX27 + */ +/*! + * @file mach-mx27/mxc_pm.c + * + * @brief This file contains the implementation of the Low-level power + * management driver. It modifies the registers of the PLL and clock module + * of the i.MX27. + * + * @ingroup DPM_MX27 + */ + +/* + * Include Files + */ +#include +#include +#include +#include +#include +#include +#include +#include "crm_regs.h" + +/* Local defines */ +#define MAX_ARM_FREQ 400000000 +#define MAX_AHB_FREQ 133000000 +#define MAX_IPG_FREQ 66500000 +#define FREQ_COMP_TOLERANCE 100 /* tolerance percentage times 100 */ +#define MX27_LLPM_DEBUG 0 + +/* + * Global variables + */ +#if 0 +/*! + * These variables hold the various clock values when the module is loaded. + * This is needed because these clocks are derived from MPLL and when MPLL + * output changes, these clocks need to be adjusted. + */ +static u32 perclk1, perclk2, perclk3, perclk4, nfcclk, cpuclk; + +/*! + * Compare two frequences using allowable tolerance + * + * The MX27 PLL can generate many frequencies. This function + * compares the generated frequency to the requested frequency + * and determines it they are within and acceptable tolerance. + * + * @param freq1 desired frequency + * @param freq2 generated frequency + * + * @return Returns 0 is frequencies are within talerance + * and non-zero is they are not. + */ +static s32 freq_equal(u32 freq1, u32 freq2) +{ + if (freq1 > freq2) { + return (freq1 - freq2) <= (freq1 / FREQ_COMP_TOLERANCE); + } + return (freq2 - freq1) <= (freq1 / FREQ_COMP_TOLERANCE); +} + +/*! + * Select the PLL frequency based on the desired ARM frequency. + * + * The MPLL will be configured to output three frequencies, 400/333/266 MHz. + * + * @param armfreq Desired ARM frequency + * + * @return Returns one of the selected PLL frequency (400/333/266 MHz). + * Returns -1 on error. + * + */ +static s32 select_freq_pll(u32 armfreq) +{ + u32 div; + + div = 266000000 / armfreq; + if ((div == 0) || (!freq_equal(armfreq, 266000000 / div))) { + div = 400000000 / armfreq; + if ((div == 0) || (!freq_equal(armfreq, 400000000 / div))) { + return -1; + } + + return 400000000; + } + + return 266000000; +} + +/*! + * Check whether the desired ARM and AHB frequencies are valid. + * + * @param armfreq Desired ARM frequency + * @param ahbfreq Desired AHB frequency + * + * @return Returns 0 on success + * Return -1 on error + */ +static s32 mx27_pm_check_parameters(u32 armfreq, u32 ahbfreq) +{ + u32 ahbdiv; + + /* No idea about minimum frequencies.. just a guess! */ + if ((armfreq < 1000000) || (ahbfreq < 1000000)) { + printk("arm or ahb frequencies are less\n"); + return -1; + } + + if ((armfreq > MAX_ARM_FREQ) || (ahbfreq > MAX_AHB_FREQ)) { + printk("arm or ahb freq. are too much\n"); + return -1; + } + + /* AHB divider value is restricted to less than 8 */ + ahbdiv = armfreq / ahbfreq; + if ((ahbdiv == 0) || (ahbdiv > 8)) { + printk("Invalid ahb frequency\n"); + return -1; + } + + return 0; +} + +/*! + * Integer clock scaling + * + * Change the main ARM clock frequencies without changing the MPLL. + * The integer dividers (PRESC and BCLKDIV) are changed to obtain the + * desired frequency. Since NFC clock is derived from ARM frequency, + * NFCDIV is also adjusted. + * + * @param arm_freq Desired ARM frequency + * @param ahb_freq Desired AHB frequency + * @param pll_freq Current PLL frequency + * + * @return Returns 0 + */ +static s32 mx27_pm_intscale(u32 arm_freq, u32 ahb_freq, s32 pll_freq) +{ + u32 pre_div, bclk_div, nfc_div; + + /* Calculate ARM divider */ + pre_div = pll_freq / arm_freq; + if (pre_div == 0) + pre_div = 1; + + /* Calculate AHB divider */ + bclk_div = arm_freq / ahb_freq; + if (bclk_div == 0) + bclk_div = 1; + + if ((arm_freq / bclk_div) > ahb_freq) + bclk_div++; + + /* NFC clock is dependent on ARM clock */ + nfc_div = arm_freq / nfcclk; + if ((arm_freq / nfc_div) > nfcclk) + nfc_div++; + + /* Adjust NFC divider */ + mxc_set_clocks_div(NFC_CLK, nfc_div); + +#if MX27_LLPM_DEBUG + printk("DIVIDERS: PreDiv = %d BCLKDIV = %d \n", pre_div, bclk_div); + printk("Integer scaling\n"); + printk("PLL = %d : ARM = %d: AHB = %d\n", pll_freq, arm_freq, ahb_freq); +#endif + + /* + * This part is tricky. What to adjust first (PRESC or BCLKDIV)? + * After trial and error, if current ARM frequency is greater than + * desired ARM frequency, then adjust PRESC first, else if current + * ARM frequency is less than desired ARM frequency, then adjust + * BCLKDIV first. + */ + if (cpuclk > arm_freq) { + mxc_set_clocks_div(CPU_CLK, pre_div); + mxc_set_clocks_div(AHB_CLK, bclk_div); + } else { + mxc_set_clocks_div(AHB_CLK, bclk_div); + mxc_set_clocks_div(CPU_CLK, pre_div); + } + + cpuclk = arm_freq; + mdelay(50); + return 0; +} + +/*! + * Set dividers for various peripheral clocks. + * + * PERCLK1, PERCLK2, PERCLK3 and PERCLK4 are adjusted based on the MPLL + * output frequency. + * + * @param pll_freq Desired MPLL output frequency + */ +static void mx27_set_dividers(u32 pll_freq) +{ + s32 perdiv1, perdiv2, perdiv3, perdiv4; + + perdiv1 = pll_freq / perclk1; + if ((pll_freq / perdiv1) > perclk1) + perdiv1++; + + perdiv2 = pll_freq / perclk2; + if ((pll_freq / perdiv2) > perclk2) + perdiv2++; + + perdiv3 = pll_freq / perclk3; + if ((pll_freq / perdiv3) > perclk3) + perdiv3++; + + perdiv4 = pll_freq / perclk4; + if ((pll_freq / perdiv4) > perclk4) + perdiv4++; + + mxc_set_clocks_div(PERCLK1, perdiv1); + mxc_set_clocks_div(PERCLK2, perdiv2); + mxc_set_clocks_div(PERCLK3, perdiv3); + mxc_set_clocks_div(PERCLK4, perdiv4); +} + +/*! + * Change MPLL output frequency and adjust derived clocks to produce the + * desired frequencies. + * + * @param arm_freq Desired ARM frequency + * @param ahb_freq Desired AHB frequency + * @param org_pll Current PLL frequency + * + * @return Returns 0 on success + * Returns -1 on error + */ +static s32 mx27_pm_pllscale(u32 arm_freq, u32 ahb_freq, s32 org_pll) +{ + u32 mfi, mfn, mfd, pd = 1, cscr; + s32 pll_freq; + + /* Obtain the PLL frequency for the desired ARM frequency */ + pll_freq = select_freq_pll(arm_freq); + if (pll_freq == -1) { + return -1; + } + + /* The MPCTL0 register values are programmed based on the oscillator */ + cscr = __raw_readl(IO_ADDRESS(CCM_BASE_ADDR) + CCM_CSCR); + if ((cscr & CCM_CSCR_OSC26M) == 0) { + /* MPCTL0 register values are programmed for 400/266 MHz */ + switch (pll_freq) { + case 400000000: + mfi = 7; + mfn = 9; + mfd = 12; + pd = 0; + break; + + case 266000000: + mfi = 10; + mfn = 6; + mfd = 25; + break; + + default: + return -1; + } + } else { + /* MPCTL0 register values are programmed for 400/266 MHz */ + switch (pll_freq) { + case 400000000: + mfi = 12; + mfn = 2; + mfd = 3; + break; + + case 266000000: + mfi = 8; + mfn = 10; + mfd = 31; + break; + + default: + return -1; + } + } + +#if MX27_LLPM_DEBUG + printk("PLL scaling\n"); + printk("PLL = %d : ARM = %d: AHB = %d\n", pll_freq, arm_freq, ahb_freq); +#endif + + /* Adjust the peripheral clock dividers for new PLL frequency */ + mx27_set_dividers(pll_freq); + + if (pll_freq > org_pll) { + /* Set the dividers first */ + mx27_pm_intscale(arm_freq, ahb_freq, pll_freq); + + /* Set the PLL */ + mxc_pll_set(MCUPLL, mfi, pd, mfd, mfn); + mdelay(50); + } else { + /* Set the PLL first */ + mxc_pll_set(MCUPLL, mfi, pd, mfd, mfn); + mdelay(50); + + /* Set the dividers later */ + mx27_pm_intscale(arm_freq, ahb_freq, pll_freq); + } + + return 0; +} +#endif +/*! + * Implement steps required to transition to low-power modes. + * + * @param mode The desired low-power mode. Possible values are, + * DOZE_MODE + * WAIT_MODE + * STOP_MODE + * DSM_MODE + */ +void mxc_pm_lowpower(s32 mode) +{ + u32 cscr; + + local_irq_disable(); + + /* WAIT and DOZE execute WFI only */ + switch (mode) { + case STOP_MODE: + case DSM_MODE: + /* Clear MPEN and SPEN to disable MPLL/SPLL */ + cscr = __raw_readl(CCM_CSCR); + cscr &= 0xFFFFFFFC; + __raw_writel(cscr, CCM_CSCR); + break; + } + + /* Executes WFI */ + arch_idle(); + + local_irq_enable(); +} + +#if 0 +/*! + * Called to change the core frequency. This function internally decides + * whether to do integer scaling or pll scaling. + * + * @param arm_freq Desired ARM frequency + * @param ahb_freq Desired AHB frequency + * @param ipg_freq Desired IP frequency, constant AHB / 2 always. + * + * @return Returns 0 on success + * Returns -1 on error + */ +int mxc_pm_dvfs(unsigned long arm_freq, long ahb_freq, long ipg_freq) +{ + u32 divider; + s32 pll_freq, ret; + unsigned long flags; + + if (mx27_pm_check_parameters(arm_freq, ahb_freq) != 0) { + return -1; + } + + local_irq_save(flags); + + /* Get the current PLL frequency */ + pll_freq = mxc_pll_clock(MCUPLL); + +#if MX27_LLPM_DEBUG + printk("MCU PLL frequency is %d\n", pll_freq); +#endif + + /* Decide whether to do integer scaling or pll scaling */ + if (arm_freq > pll_freq) { + /* Do PLL scaling */ + ret = mx27_pm_pllscale(arm_freq, ahb_freq, pll_freq); + } else { + /* We need integer divider values */ + divider = pll_freq / arm_freq; + if (!freq_equal(arm_freq, pll_freq / divider)) { + /* Do PLL scaling */ + ret = mx27_pm_pllscale(arm_freq, ahb_freq, pll_freq); + } else { + /* Do integer scaling */ + ret = mx27_pm_intscale(arm_freq, ahb_freq, pll_freq); + } + } + + local_irq_restore(flags); + return ret; +} +#endif +/* + * This API is not supported on i.MX27 + */ +int mxc_pm_intscale(long armfreq, long ahbfreq, long ipfreq) +{ + return -MXC_PM_API_NOT_SUPPORTED; +} + +/* + * This API is not supported on i.MX27 + */ +int mxc_pm_pllscale(long armfreq, long ahbfreq, long ipfreq) +{ + return -MXC_PM_API_NOT_SUPPORTED; +} + +/*! + * This function is used to load the module. + * + * @return Returns an Integer on success + */ +static int __init mxc_pm_init_module(void) +{ + printk(KERN_INFO "MX27: Power management module initialized\n"); + return 0; +} + +/*! + * This function is used to unload the module + */ +static void __exit mxc_pm_cleanup_module(void) +{ + printk(KERN_INFO "MX27: Power management module exit\n"); +} + +module_init(mxc_pm_init_module); +module_exit(mxc_pm_cleanup_module); + +EXPORT_SYMBOL(mxc_pm_lowpower); +//EXPORT_SYMBOL(mxc_pm_dvfs); +EXPORT_SYMBOL(mxc_pm_pllscale); +EXPORT_SYMBOL(mxc_pm_intscale); + +MODULE_AUTHOR("Freescale Semiconductor"); +MODULE_DESCRIPTION("i.MX27 low level PM driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/mach-mx27/pm.c linux-2.6.26-lab126/arch/arm/mach-mx27/pm.c --- linux-2.6.26/arch/arm/mach-mx27/pm.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/pm.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,102 @@ +/* + * linux/arch/arm/mach-mx27/pm.c + * + * MX27 Power Management Routines + * + * Original code for the SA11x0: + * Copyright (c) 2001 Cliff Brake + * + * Modified for the PXA250 by Nicolas Pitre: + * Copyright (c) 2002 Monta Vista Software, Inc. + * + * Modified for the OMAP1510 by David Singleton: + * Copyright (c) 2002 Monta Vista Software, Inc. + * + * Cleanup 2004 for OMAP1510/1610 by Dirk Behme + * + * Modified for the MX27 + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +#include + +/* + * TODO: whatta save? + */ + +static int mx27_suspend_enter(suspend_state_t state) +{ + pr_debug("Hi, from mx27_pm_enter\n"); + switch (state) { + case PM_SUSPEND_STANDBY: + mxc_pm_lowpower(STOP_MODE); + break; + case PM_SUSPEND_MEM: + mxc_pm_lowpower(DSM_MODE); + break; + default: + return -1; + } + return 0; +} + +/* + * Called after processes are frozen, but before we shut down devices. + */ +static int mx27_suspend_prepare(void) +{ + return 0; +} + +/* + * Called after devices are re-setup, but before processes are thawed. + */ +static void mx27_suspend_finish(void) +{ + return; +} + +static int mx27_pm_valid(suspend_state_t state) +{ + return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); +} + +struct platform_suspend_ops mx27_suspend_ops = { + .valid = mx27_pm_valid, + .prepare = mx27_suspend_prepare, + .enter = mx27_suspend_enter, + .finish = mx27_suspend_finish, +}; + +static int __init mx27_pm_init(void) +{ + pr_debug("Power Management for Freescale MX27\n"); + suspend_set_ops(&mx27_suspend_ops); + + return 0; +} + +late_initcall(mx27_pm_init); diff -urN linux-2.6.26/arch/arm/mach-mx27/serial.c linux-2.6.26-lab126/arch/arm/mach-mx27/serial.c --- linux-2.6.26/arch/arm/mach-mx27/serial.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/serial.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,275 @@ +/* + * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @file mach-mx27/serial.c + * + * @brief This file contains the UART initiliazation. + * + * @ingroup MSL_MX27 + */ +#include +#include +#include +#include +#include +#include "serial.h" +#include "board-mx27ads.h" + +#if defined(CONFIG_SERIAL_MXC) || defined(CONFIG_SERIAL_MXC_MODULE) + +/*! + * This is an array where each element holds information about a UART port, + * like base address of the UART, interrupt numbers etc. This structure is + * passed to the serial_core.c file. Based on which UART is used, the core file + * passes back the appropriate port structure as an argument to the control + * functions. + */ +static uart_mxc_port mxc_ports[] = { + [0] = { + .port = { + .membase = (void *)IO_ADDRESS(UART1_BASE_ADDR), + .mapbase = UART1_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART1_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 0, + }, + .ints_muxed = UART1_MUX_INTS, + .irqs = {UART1_INT2, UART1_INT3}, + .mode = UART1_MODE, + .ir_mode = UART1_IR, + .enabled = UART1_ENABLED, + .hardware_flow = UART1_HW_FLOW, + .cts_threshold = UART1_UCR4_CTSTL, + .dma_enabled = UART1_DMA_ENABLE, + .dma_rxbuf_size = UART1_DMA_RXBUFSIZE, + .rx_threshold = UART1_UFCR_RXTL, + .tx_threshold = UART1_UFCR_TXTL, + .shared = UART1_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART1_TX, + .dma_rx_id = MXC_DMA_UART1_RX, + .rxd_mux = MXC_UART_RXDMUX, + .ir_tx_inv = MXC_IRDA_TX_INV, + .ir_rx_inv = MXC_IRDA_RX_INV, + }, + [1] = { + .port = { + .membase = (void *)IO_ADDRESS(UART2_BASE_ADDR), + .mapbase = UART2_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART2_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 1, + }, + .ints_muxed = UART2_MUX_INTS, + .irqs = {UART2_INT2, UART2_INT3}, + .mode = UART2_MODE, + .ir_mode = UART2_IR, + .enabled = UART2_ENABLED, + .hardware_flow = UART2_HW_FLOW, + .cts_threshold = UART2_UCR4_CTSTL, + .dma_enabled = UART2_DMA_ENABLE, + .dma_rxbuf_size = UART2_DMA_RXBUFSIZE, + .rx_threshold = UART2_UFCR_RXTL, + .tx_threshold = UART2_UFCR_TXTL, + .shared = UART2_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART2_TX, + .dma_rx_id = MXC_DMA_UART2_RX, + .rxd_mux = MXC_UART_RXDMUX, + .ir_tx_inv = MXC_IRDA_TX_INV, + .ir_rx_inv = MXC_IRDA_RX_INV, + }, + [2] = { + .port = { + .membase = (void *)IO_ADDRESS(UART3_BASE_ADDR), + .mapbase = UART3_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART3_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 2, + }, + .ints_muxed = UART3_MUX_INTS, + .irqs = {UART3_INT2, UART3_INT3}, + .mode = UART3_MODE, + .ir_mode = UART3_IR, + .enabled = UART3_ENABLED, + .hardware_flow = UART3_HW_FLOW, + .cts_threshold = UART3_UCR4_CTSTL, + .dma_enabled = UART3_DMA_ENABLE, + .dma_rxbuf_size = UART3_DMA_RXBUFSIZE, + .rx_threshold = UART3_UFCR_RXTL, + .tx_threshold = UART3_UFCR_TXTL, + .shared = UART3_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART3_TX, + .dma_rx_id = MXC_DMA_UART3_RX, + .rxd_mux = MXC_UART_IR_RXDMUX, + .ir_tx_inv = MXC_IRDA_TX_INV, + .ir_rx_inv = MXC_IRDA_RX_INV, + }, + [3] = { + .port = { + .membase = (void *)IO_ADDRESS(UART4_BASE_ADDR), + .mapbase = UART4_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART4_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 3, + }, + .ints_muxed = UART4_MUX_INTS, + .irqs = {UART4_INT2, UART4_INT3}, + .mode = UART4_MODE, + .ir_mode = UART4_IR, + .enabled = UART4_ENABLED, + .hardware_flow = UART4_HW_FLOW, + .cts_threshold = UART4_UCR4_CTSTL, + .dma_enabled = UART4_DMA_ENABLE, + .dma_rxbuf_size = UART4_DMA_RXBUFSIZE, + .rx_threshold = UART4_UFCR_RXTL, + .tx_threshold = UART4_UFCR_TXTL, + .shared = UART4_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART4_TX, + .dma_rx_id = MXC_DMA_UART4_RX, + .rxd_mux = MXC_UART_RXDMUX, + .ir_tx_inv = MXC_IRDA_TX_INV, + .ir_rx_inv = MXC_IRDA_RX_INV, + }, + [4] = { + .port = { + .membase = (void *)IO_ADDRESS(UART5_BASE_ADDR), + .mapbase = UART5_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART5_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 4, + }, + .ints_muxed = UART5_MUX_INTS, + .irqs = {UART5_INT2, UART5_INT3}, + .mode = UART5_MODE, + .ir_mode = UART5_IR, + .enabled = UART5_ENABLED, + .hardware_flow = UART5_HW_FLOW, + .cts_threshold = UART5_UCR4_CTSTL, + .dma_enabled = UART5_DMA_ENABLE, + .dma_rxbuf_size = UART5_DMA_RXBUFSIZE, + .rx_threshold = UART5_UFCR_RXTL, + .tx_threshold = UART5_UFCR_TXTL, + .shared = UART5_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART5_TX, + .dma_rx_id = MXC_DMA_UART5_RX, + .rxd_mux = MXC_UART_RXDMUX, + .ir_tx_inv = MXC_IRDA_TX_INV, + .ir_rx_inv = MXC_IRDA_RX_INV, + }, + [5] = { + .port = { + .membase = (void *)IO_ADDRESS(UART6_BASE_ADDR), + .mapbase = UART6_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART6_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 5, + }, + .ints_muxed = UART6_MUX_INTS, + .irqs = {UART6_INT2, UART6_INT3}, + .mode = UART6_MODE, + .ir_mode = UART6_IR, + .enabled = UART6_ENABLED, + .hardware_flow = UART6_HW_FLOW, + .cts_threshold = UART6_UCR4_CTSTL, + .dma_enabled = UART6_DMA_ENABLE, + .dma_rxbuf_size = UART6_DMA_RXBUFSIZE, + .rx_threshold = UART6_UFCR_RXTL, + .tx_threshold = UART6_UFCR_TXTL, + .shared = UART6_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART6_TX, + .dma_rx_id = MXC_DMA_UART6_RX, + .rxd_mux = MXC_UART_RXDMUX, + .ir_tx_inv = MXC_IRDA_TX_INV, + .ir_rx_inv = MXC_IRDA_RX_INV, + }, +}; + +static struct platform_device mxc_uart_device1 = { + .name = "mxcintuart", + .id = 0, + .dev = { + .platform_data = &mxc_ports[0], + }, +}; + +static struct platform_device mxc_uart_device2 = { + .name = "mxcintuart", + .id = 1, + .dev = { + .platform_data = &mxc_ports[1], + }, +}; + +static struct platform_device mxc_uart_device3 = { + .name = "mxcintuart", + .id = 2, + .dev = { + .platform_data = &mxc_ports[2], + }, +}; + +static struct platform_device mxc_uart_device4 = { + .name = "mxcintuart", + .id = 3, + .dev = { + .platform_data = &mxc_ports[3], + }, +}; +static struct platform_device mxc_uart_device5 = { + .name = "mxcintuart", + .id = 4, + .dev = { + .platform_data = &mxc_ports[4], + }, +}; +static struct platform_device mxc_uart_device6 = { + .name = "mxcintuart", + .id = 5, + .dev = { + .platform_data = &mxc_ports[5], + }, +}; + +static int __init mxc_init_uart(void) +{ + /* Register all the MXC UART platform device structures */ + platform_device_register(&mxc_uart_device1); + platform_device_register(&mxc_uart_device2); + platform_device_register(&mxc_uart_device3); + + platform_device_register(&mxc_uart_device4); + + platform_device_register(&mxc_uart_device5); + platform_device_register(&mxc_uart_device6); + return 0; +} + +#else +static int __init mxc_init_uart(void) +{ + return 0; +} +#endif + +arch_initcall(mxc_init_uart); diff -urN linux-2.6.26/arch/arm/mach-mx27/serial.h linux-2.6.26-lab126/arch/arm/mach-mx27/serial.h --- linux-2.6.26/arch/arm/mach-mx27/serial.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/serial.h 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,170 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ARCH_ARM_MACH_MX27_SERIAL_H__ +#define __ARCH_ARM_MACH_MX27_SERIAL_H__ + +/*! + * @file mach-mx27/serial.h + * + * @ingroup MSL_MX27 + */ +#include + +/* UART 1 configuration */ +/*! + * This option allows to choose either an interrupt-driven software controlled + * hardware flow control (set this option to 0) or hardware-driven hardware + * flow control (set this option to 1). + */ +#define UART1_HW_FLOW 1 +/*! + * This specifies the threshold at which the CTS pin is deasserted by the + * RXFIFO. Set this value in Decimal to anything from 0 to 32 for + * hardware-driven hardware flow control. Read the HW spec while specifying + * this value. When using interrupt-driven software controlled hardware + * flow control set this option to -1. + */ +#define UART1_UCR4_CTSTL 16 +/*! + * This is option to enable (set this option to 1) or disable DMA data transfer + */ +#define UART1_DMA_ENABLE 0 +/*! + * Specify the size of the DMA receive buffer. The buffer size should be same with + * sub buffer size which is defined in mxc_uart.c for all data can be transfered. + */ +#define UART1_DMA_RXBUFSIZE 128 +/*! + * Specify the MXC UART's Receive Trigger Level. This controls the threshold at + * which a maskable interrupt is generated by the RxFIFO. Set this value in + * Decimal to anything from 0 to 32. Read the HW spec while specifying this + * value. + */ +#define UART1_UFCR_RXTL 16 +/*! + * Specify the MXC UART's Transmit Trigger Level. This controls the threshold at + * which a maskable interrupt is generated by the TxFIFO. Set this value in + * Decimal to anything from 0 to 32. Read the HW spec while specifying this + * value. + */ +#define UART1_UFCR_TXTL 16 +/* UART 2 configuration */ +#define UART2_HW_FLOW 1 +#define UART2_UCR4_CTSTL 16 +#define UART2_DMA_ENABLE 0 +#define UART2_DMA_RXBUFSIZE 512 +#define UART2_UFCR_RXTL 16 +#define UART2_UFCR_TXTL 16 +/* UART 3 configuration */ +#define UART3_HW_FLOW 0 +#define UART3_UCR4_CTSTL -1 +#define UART3_DMA_ENABLE 0 +#define UART3_DMA_RXBUFSIZE 512 +#define UART3_UFCR_RXTL 16 +#define UART3_UFCR_TXTL 16 +/* UART 4 configuration */ +#define UART4_HW_FLOW 1 +#define UART4_UCR4_CTSTL 16 +#define UART4_DMA_ENABLE 0 +#define UART4_DMA_RXBUFSIZE 512 +#define UART4_UFCR_RXTL 16 +#define UART4_UFCR_TXTL 16 +/* UART 5 configuration */ +#define UART5_HW_FLOW 1 +#define UART5_UCR4_CTSTL 16 +#define UART5_DMA_ENABLE 0 +#define UART5_DMA_RXBUFSIZE 512 +#define UART5_UFCR_RXTL 16 +#define UART5_UFCR_TXTL 16 +/* UART 6 configuration */ +#define UART6_HW_FLOW 1 +#define UART6_UCR4_CTSTL 16 +#define UART6_DMA_ENABLE 0 +#define UART6_DMA_RXBUFSIZE 512 +#define UART6_UFCR_RXTL 16 +#define UART6_UFCR_TXTL 16 +/* + * UART Chip level Configuration that a user may not have to edit. These + * configuration vary depending on how the UART module is integrated with + * the ARM core + */ +/* + * Is the MUXED interrupt output sent to the ARM core + */ +#define INTS_NOTMUXED 0 +#define INTS_MUXED 1 +/* UART 1 configuration */ +/*! + * This define specifies whether the muxed ANDed interrupt line or the + * individual interrupts from the UART port is integrated with the ARM core. + * There exists a define like this for each UART port. Valid values that can + * be used are \b INTS_NOTMUXED or \b INTS_MUXED. + */ +#define UART1_MUX_INTS INTS_MUXED +/*! + * This define specifies the transmitter interrupt number or the interrupt + * number of the ANDed interrupt in case the interrupts are muxed. There exists + * a define like this for each UART port. + */ +#define UART1_INT1 MXC_INT_UART1 +/*! + * This define specifies the receiver interrupt number. If the interrupts of + * the UART are muxed, then we specify here a dummy value -1. There exists a + * define like this for each UART port. + */ +#define UART1_INT2 -1 +/*! + * This specifies the master interrupt number. If the interrupts of the UART + * are muxed, then we specify here a dummy value of -1. There exists a define + * like this for each UART port. + */ +#define UART1_INT3 -1 +/*! + * This specifies if the UART is a shared peripheral. It holds the shared + * peripheral number if it is shared or -1 if it is not shared. There exists + * a define like this for each UART port. + */ +#define UART1_SHARED_PERI -1 +/* UART 2 configuration */ +#define UART2_MUX_INTS INTS_MUXED +#define UART2_INT1 MXC_INT_UART2 +#define UART2_INT2 -1 +#define UART2_INT3 -1 +#define UART2_SHARED_PERI -1 +/* UART 3 configuration */ +#define UART3_MUX_INTS INTS_MUXED +#define UART3_INT1 MXC_INT_UART3 +#define UART3_INT2 -1 +#define UART3_INT3 -1 +#define UART3_SHARED_PERI -1 +/* UART 4 configuration */ +#define UART4_MUX_INTS INTS_MUXED +#define UART4_INT1 MXC_INT_UART4 +#define UART4_INT2 -1 +#define UART4_INT3 -1 +#define UART4_SHARED_PERI -1 +/* UART 5 configuration */ +#define UART5_MUX_INTS INTS_MUXED +#define UART5_INT1 MXC_INT_UART5 +#define UART5_INT2 -1 +#define UART5_INT3 -1 +#define UART5_SHARED_PERI -1 +/* UART 6 configuration */ +#define UART6_MUX_INTS INTS_MUXED +#define UART6_INT1 MXC_INT_UART6 +#define UART6_INT2 -1 +#define UART6_INT3 -1 +#define UART6_SHARED_PERI -1 + +#endif /* __ARCH_ARM_MACH_MX27_SERIAL_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx27/system.c linux-2.6.26-lab126/arch/arm/mach-mx27/system.c --- linux-2.6.26/arch/arm/mach-mx27/system.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/system.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,60 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +/*! + * @defgroup MSL_MX27 i.MX27 Machine Specific Layer (MSL) + */ + +/*! + * @file mach-mx27/system.c + * @brief This file contains idle and reset functions. + * + * @ingroup MSL_MX27 + */ + +/*! + * This function puts the CPU into idle mode. It is called by default_idle() + * in process.c file. + */ +void arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks. + */ + cpu_do_idle(); +} + +/* + * This function resets the system. It is called by machine_restart(). + * + * @param mode indicates different kinds of resets + */ +void arch_reset(char mode) +{ + /* Assert Watchdog Reset signal */ + mxc_wd_reset(); +} diff -urN linux-2.6.26/arch/arm/mach-mx27/time.c linux-2.6.26-lab126/arch/arm/mach-mx27/time.c --- linux-2.6.26/arch/arm/mach-mx27/time.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/time.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,240 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* System Timer Interrupt reconfigured to run in free-run mode. + * Author: Vitaly Wool + * Copyright 2004 MontaVista Software Inc. + */ + +/*! + * @defgroup Timers_MX27 OS Tick Timer + * @ingroup MSL_MX27 + */ +/*! + * @file mach-mx27/time.c + * @brief This file contains OS tick timer implementation. + * + * This file contains OS tick timer implementation. + * + * @ingroup Timers_MX27 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*! + * GPT register address definitions + */ +#define GPT_BASE_ADDR (IO_ADDRESS(GPT1_BASE_ADDR)) +#define MXC_GPT_GPTCR (GPT_BASE_ADDR + 0x00) +#define MXC_GPT_GPTPR (GPT_BASE_ADDR + 0x04) +#define MXC_GPT_GPTOCR1 (GPT_BASE_ADDR + 0x08) +#define MXC_GPT_GPTICR1 (GPT_BASE_ADDR + 0x0C) +#define MXC_GPT_GPTCNT (GPT_BASE_ADDR + 0x10) +#define MXC_GPT_GPTSR (GPT_BASE_ADDR + 0x14) + +/*! + * GPT Control register bit definitions + */ +#define GPTCR_COMPEN (1 << 4) +#define GPTCR_SWR (1 << 15) +#define GPTCR_FRR (1 << 8) + +#define GPTCR_CLKSRC_SHIFT 1 +#define GPTCR_CLKSRC_MASK (7 << GPTCR_CLKSRC_SHIFT) +#define GPTCR_CLKSRC_NOCLOCK (0 << GPTCR_CLKSRC_SHIFT) +#define GPTCR_CLKSRC_HIGHFREQ (1 << GPTCR_CLKSRC_SHIFT) +#define GPTCR_CLKSRC_CLKIN (3 << GPTCR_CLKSRC_SHIFT) +#define GPTCR_CLKSRC_CLK32K (4 << GPTCR_CLKSRC_SHIFT) + +#define GPTCR_ENABLE (1 << 0) + +#define GPTSR_OF1 (1 << 0) + +extern unsigned long clk_early_get_timer_rate(void); + +static int mxc_gpt_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + unsigned long now, expires; + u32 reg; + + now = __raw_readl(MXC_GPT_GPTCNT); + expires = now + cycles; + __raw_writel(expires, MXC_GPT_GPTOCR1); + __raw_writel(GPTSR_OF1, MXC_GPT_GPTSR); + + /* enable interrupt */ + reg = __raw_readl(MXC_GPT_GPTCR); + reg |= GPTCR_COMPEN; + __raw_writel(reg, MXC_GPT_GPTCR); + + return 0; +} + +static void mxc_gpt_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + u32 reg; + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + panic("MXC GPT: CLOCK_EVT_MODE_PERIODIC not supported\n"); + break; + case CLOCK_EVT_MODE_ONESHOT: + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + /* Disable interrupts */ + reg = __raw_readl(MXC_GPT_GPTCR); + reg &= ~GPTCR_COMPEN; + __raw_writel(reg, MXC_GPT_GPTCR); + break; + case CLOCK_EVT_MODE_RESUME: + break; + } +} + +static struct clock_event_device gpt_clockevent = { + .name = "mxc_gpt", + .features = CLOCK_EVT_FEAT_ONESHOT, + .rating = 300, + .shift = 32, + .set_next_event = mxc_gpt_set_next_event, + .set_mode = mxc_gpt_set_mode, +}; + +/*! + * This is the timer interrupt service routine to do required tasks. + * It also services the WDOG timer at the frequency of twice per WDOG + * timeout value. For example, if the WDOG's timeout value is 4 (2 + * seconds since the WDOG runs at 0.5Hz), it will be serviced once + * every 2/2=1 second. + * + * @param irq GPT interrupt source number (not used) + * @param dev_id this parameter is not used + * @return always returns \b IRQ_HANDLED as defined in + * include/linux/interrupt.h. + */ +static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) +{ + unsigned int gptsr; + u32 reg; + + gptsr = __raw_readl(MXC_GPT_GPTSR); + if (gptsr & GPTSR_OF1) { + /* Disable interrupt */ + reg = __raw_readl(MXC_GPT_GPTCR); + reg &= ~GPTCR_COMPEN; + __raw_writel(reg, MXC_GPT_GPTCR); + /* Clear interrupt */ + __raw_writel(GPTSR_OF1, MXC_GPT_GPTSR); + + gpt_clockevent.event_handler(&gpt_clockevent); + } + + return IRQ_HANDLED; +} + +/*! + * The clockevents timer interrupt structure. + */ +static struct irqaction timer_irq = { + .name = "gpt-irq", + .flags = IRQF_DISABLED, + .handler = mxc_timer_interrupt, +}; + +static cycle_t __xipram mxc_gpt_read(void) +{ + return __raw_readl(MXC_GPT_GPTCNT); +} + +static struct clocksource gpt_clocksrc = { + .name = "mxc_gpt", + .rating = 300, + .read = mxc_gpt_read, + .mask = CLOCKSOURCE_MASK(32), + .shift = 24, + .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_VALID_FOR_HRES, +}; + +/*! + * This function is used to initialize the GPT as a clocksource and clockevent. + * It is called by the start_kernel() during system startup. + */ +void __init mxc_init_time(void) +{ + int ret; + unsigned long rate; + u32 reg, div; + + /* Reset GPT */ + __raw_writel(GPTCR_SWR, MXC_GPT_GPTCR); + while ((__raw_readl(MXC_GPT_GPTCR) & GPTCR_SWR) != 0) + mb(); + + /* Normal clk api are not yet initialized, so use early verion */ + rate = clk_early_get_timer_rate(); + if (rate == 0) + panic("MXC GPT: Can't get timer clock rate\n"); + +#ifdef CLOCK_TICK_RATE + div = rate / CLOCK_TICK_RATE; + WARN_ON((div * CLOCK_TICK_RATE) != rate); +#else /* Hopefully CLOCK_TICK_RATE will go away soon */ + div = 1; + while ((rate / div) > 20000000) { + div++; + } +#endif + rate /= div; + __raw_writel(div - 1, MXC_GPT_GPTPR); + + reg = GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ | GPTCR_ENABLE; + __raw_writel(reg, MXC_GPT_GPTCR); + + gpt_clocksrc.mult = clocksource_hz2mult(rate, gpt_clocksrc.shift); + ret = clocksource_register(&gpt_clocksrc); + if (ret < 0) { + goto err; + } + + gpt_clockevent.mult = div_sc(rate, NSEC_PER_SEC, gpt_clockevent.shift); + gpt_clockevent.max_delta_ns = clockevent_delta2ns(-1, &gpt_clockevent); + gpt_clockevent.min_delta_ns = clockevent_delta2ns(1, &gpt_clockevent); + + gpt_clockevent.cpumask = cpumask_of_cpu(0); + clockevents_register_device(&gpt_clockevent); + + ret = setup_irq(MXC_INT_GPT, &timer_irq); + if (ret < 0) { + goto err; + } + + pr_info("MXC GPT timer initialized, rate = %lu\n", rate); + return; + err: + panic("Unable to initialize timer\n"); +} + +struct sys_timer mxc_timer = { + .init = mxc_init_time, +}; diff -urN linux-2.6.26/arch/arm/mach-mx27/usb.h linux-2.6.26-lab126/arch/arm/mach-mx27/usb.h --- linux-2.6.26/arch/arm/mach-mx27/usb.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/usb.h 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,116 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +extern int usbotg_init(struct platform_device *pdev); +extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata); +extern int gpio_usbotg_fs_active(void); +extern void gpio_usbotg_fs_inactive(void); +extern int gpio_usbotg_hs_active(void); +extern void gpio_usbotg_hs_inactive(void); +extern struct platform_device *host_pdev_register(struct resource *res, + int n_res, struct fsl_usb2_platform_data *config); + +extern int fsl_usb_host_init(struct platform_device *pdev); +extern void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata); +extern int gpio_usbh1_active(void); +extern void gpio_usbh1_inactive(void); +extern int gpio_usbh2_active(void); +extern void gpio_usbh2_inactive(void); + +/* + * Determine which platform_data struct to use, based on which + * transceiver is configured. + * PDATA is a pointer to it. + */ +#if defined(CONFIG_ISP1504_MXC) +static struct fsl_usb2_platform_data __maybe_unused dr_1504_config; +#define PDATA (&dr_1504_config) +#elif defined(CONFIG_ISP1301_MXC) +static struct fsl_usb2_platform_data __maybe_unused dr_1301_config; +#define PDATA (&dr_1301_config) +#elif defined(CONFIG_MC13783_MXC) +static struct fsl_usb2_platform_data __maybe_unused dr_13783_config; +#define PDATA (&dr_13783_config) +#endif + + +/* + * Used to set pdata->operating_mode before registering the platform_device. + * If OTG is configured, the controller operates in OTG mode, + * otherwise it's either host or device. + */ +#ifdef CONFIG_USB_OTG +#define DR_UDC_MODE FSL_USB2_DR_OTG +#define DR_HOST_MODE FSL_USB2_DR_OTG +#else +#define DR_UDC_MODE FSL_USB2_DR_DEVICE +#define DR_HOST_MODE FSL_USB2_DR_HOST +#endif + + +#ifdef CONFIG_USB_EHCI_ARC_OTG +static inline void dr_register_host(struct resource *r, int rs) +{ + PDATA->operating_mode = DR_HOST_MODE; + host_pdev_register(r, rs, PDATA); +} +#else +static inline void dr_register_host(struct resource *r, int rs) +{ +} +#endif + +#ifdef CONFIG_USB_GADGET_ARC +static struct platform_device dr_udc_device; + +static inline void dr_register_udc(void) +{ + PDATA->operating_mode = DR_UDC_MODE; + dr_udc_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_udc_device)) + printk(KERN_ERR "usb: can't register DR gadget\n"); + else + printk(KERN_INFO "usb: DR gadget (%s) registered\n", + PDATA->transceiver); +} +#else +static inline void dr_register_udc(void) +{ +} +#endif + +#ifdef CONFIG_USB_OTG +static struct platform_device dr_otg_device; + +/* + * set the proper operating_mode and + * platform_data pointer, then register the + * device. + */ +static inline void dr_register_otg(void) +{ + PDATA->operating_mode = FSL_USB2_DR_OTG; + dr_otg_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_otg_device)) + printk(KERN_ERR "usb: can't register otg device\n"); + else + printk(KERN_INFO "usb: DR OTG registered\n"); +} +#else +static inline void dr_register_otg(void) +{ +} +#endif diff -urN linux-2.6.26/arch/arm/mach-mx27/usb_dr.c linux-2.6.26-lab126/arch/arm/mach-mx27/usb_dr.c --- linux-2.6.26/arch/arm/mach-mx27/usb_dr.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/usb_dr.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,126 @@ +#define DEBUG +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include "usb.h" + +/* + * platform data structs + * - Which one to use is determined by CONFIG options in usb.h + * - operating_mode plugged at run time + */ +static struct fsl_usb2_platform_data __maybe_unused dr_13783_config = { + .name = "DR", + .platform_init = usbotg_init, + .platform_uninit = usbotg_uninit, + .phy_mode = FSL_USB2_PHY_SERIAL, + .power_budget = 500, /* 500 mA max power */ + .gpio_usb_active = gpio_usbotg_fs_active, + .gpio_usb_inactive = gpio_usbotg_fs_inactive, + .transceiver = "mc13783", +}; + +static struct fsl_usb2_platform_data __maybe_unused dr_1301_config = { + .name = "DR", + .platform_init = usbotg_init, + .platform_uninit = usbotg_uninit, + .phy_mode = FSL_USB2_PHY_SERIAL, + .power_budget = 500, /* 500 mA max power */ + .gpio_usb_active = gpio_usbotg_fs_active, + .gpio_usb_inactive = gpio_usbotg_fs_inactive, + .transceiver = "isp1301", +}; + +static struct fsl_usb2_platform_data __maybe_unused dr_1504_config = { + .name = "DR", + .platform_init = usbotg_init, + .platform_uninit = usbotg_uninit, + .phy_mode = FSL_USB2_PHY_ULPI, + .power_budget = 500, /* 500 mA max power */ + .gpio_usb_active = gpio_usbotg_hs_active, + .gpio_usb_inactive = gpio_usbotg_hs_inactive, + .transceiver = "isp1504", +}; + + +/* + * resources + */ +static struct resource otg_resources[] = { + [0] = { + .start = (u32)(USB_OTGREGS_BASE), + .end = (u32)(USB_OTGREGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_USB3, + .flags = IORESOURCE_IRQ, + }, +}; + + +static u64 dr_udc_dmamask = ~(u32) 0; +static void dr_udc_release(struct device *dev) +{ +} + +static u64 dr_otg_dmamask = ~(u32) 0; +static void dr_otg_release(struct device *dev) +{ +} + +/* + * platform device structs + * dev.platform_data field plugged at run time + */ +static struct platform_device __maybe_unused dr_udc_device = { + .name = "fsl-usb2-udc", + .id = -1, + .dev = { + .release = dr_udc_release, + .dma_mask = &dr_udc_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), +}; + +static struct platform_device __maybe_unused dr_otg_device = { + .name = "fsl-usb2-otg", + .id = -1, + .dev = { + .release = dr_otg_release, + .dma_mask = &dr_otg_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), +}; + +static int __init usb_dr_init(void) +{ + pr_debug("%s: \n", __func__); + + dr_register_otg(); + dr_register_host(otg_resources, ARRAY_SIZE(otg_resources)); + dr_register_udc(); + + return 0; +} + +module_init(usb_dr_init); diff -urN linux-2.6.26/arch/arm/mach-mx27/usb_h1.c linux-2.6.26-lab126/arch/arm/mach-mx27/usb_h1.c --- linux-2.6.26/arch/arm/mach-mx27/usb_h1.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/usb_h1.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,53 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include "usb.h" + +static struct fsl_usb2_platform_data usbh1_config = { + .name = "Host 1", + .platform_init = fsl_usb_host_init, + .platform_uninit = fsl_usb_host_uninit, + .operating_mode = FSL_USB2_MPH_HOST, + .phy_mode = FSL_USB2_PHY_SERIAL, + .power_budget = 500, /* 500 mA max power */ + .gpio_usb_active = gpio_usbh1_active, + .gpio_usb_inactive = gpio_usbh1_inactive, + .transceiver = "serial", +}; + +static struct resource usbh1_resources[] = { + [0] = { + .start = (u32) (USB_H1REGS_BASE), + .end = (u32) (USB_H1REGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_USB1, + .flags = IORESOURCE_IRQ, + }, +}; + +static int __init usbh1_init(void) +{ + pr_debug("%s: \n", __func__); + + host_pdev_register(usbh1_resources, ARRAY_SIZE(usbh1_resources), + &usbh1_config); + return 0; +} +module_init(usbh1_init); diff -urN linux-2.6.26/arch/arm/mach-mx27/usb_h2.c linux-2.6.26-lab126/arch/arm/mach-mx27/usb_h2.c --- linux-2.6.26/arch/arm/mach-mx27/usb_h2.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx27/usb_h2.c 2010-08-10 04:14:09.000000000 -0400 @@ -0,0 +1,53 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include "usb.h" + +static struct fsl_usb2_platform_data usbh2_config = { + .name = "Host 2", + .platform_init = fsl_usb_host_init, + .platform_uninit = fsl_usb_host_uninit, + .operating_mode = FSL_USB2_MPH_HOST, + .phy_mode = FSL_USB2_PHY_ULPI, + .power_budget = 500, /* 500 mA max power */ + .gpio_usb_active = gpio_usbh2_active, + .gpio_usb_inactive = gpio_usbh2_inactive, + .transceiver = "isp1504", +}; + +static struct resource usbh2_resources[] = { + [0] = { + .start = (u32) (USB_H2REGS_BASE), + .end = (u32) (USB_H2REGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_USB2, + .flags = IORESOURCE_IRQ, + }, +}; + +static int __init usbh2_init(void) +{ + pr_debug("%s: \n", __func__); + + host_pdev_register(usbh2_resources, ARRAY_SIZE(usbh2_resources), + &usbh2_config); + return 0; +} +module_init(usbh2_init); diff -urN linux-2.6.26/arch/arm/mach-mx3/Kconfig linux-2.6.26-lab126/arch/arm/mach-mx3/Kconfig --- linux-2.6.26/arch/arm/mach-mx3/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/Kconfig 2010-08-10 04:14:16.000000000 -0400 @@ -1,12 +1,100 @@ menu "MX3 Options" depends on ARCH_MX3 +config MX3_OPTIONS + bool + default y + select CPU_V6 + select CACHE_L2X0 + select OUTER_CACHE + select USB_ARCH_HAS_EHCI + select ARCH_HAS_EVTMON + select ARCH_HAS_RNGA + config MACH_MX31ADS bool "Support MX31ADS platforms" - default y help Include support for MX31ADS platform. This includes specific configurations for the board and its peripherals. +config MACH_MX31_3DS + bool "Support MX31/MX32 3-Stack platforms" + help + Include support for MX31/MX32 3-Stack platform. This includes specific + configurations for the board and its peripherals. + +config MX3_DOZE_DURING_IDLE + bool "Enter Doze mode during idle" + help + Turning on this option will put the CPU into Doze mode during idle. + The default is to enter Wait mode during idle. Doze mode during + idle will save additional power over Wait mode. + +config MXC_SDMA_API + bool "Use SDMA API" + default y + help + This selects the Freescale MXC SDMA API. + If unsure, say N. + +menu "SDMA options" + depends on MXC_SDMA_API + +config SDMA_IRAM + bool "Use Internal RAM for SDMA transfer" + default n + help + Support Internal RAM as SDMA buffer or control structures + +config SDMA_IRAM_SIZE + hex "Reserved bytes of IRAM for SDMA (0x800-0x2000)" + range 0x800 0x2000 + depends on SDMA_IRAM + default "0x1000" + help + Set the size of IRAM for SDMA. It must be multiple of 512bytes. +endmenu + +config ARCH_MXC_HAS_NFC_V1 + bool "MXC NFC Hardware Version 1" + depends on !(MACH_MX31ADS && XIP_KERNEL) + default y + help + This selects the Freescale MXC Nand Flash Controller Hardware Version 1 + If unsure, say N. + +config ARCH_MXC_HAS_NFC_V2 + bool "MXC NFC Hardware Version 2" + depends on !(MACH_MX31ADS && XIP_KERNEL) + default y + help + This selects the Freescale MXC Nand Flash Controller Hardware Version 2 + If unsure, say N. + +menu "Device options" + +config I2C_MXC_SELECT1 + bool "Enable I2C1 module" + default y + depends on I2C_MXC + help + Enable MX31 I2C1 module. + +config I2C_MXC_SELECT2 + bool "Enable I2C2 module" + default n + depends on I2C_MXC + help + Enable MX31 I2C2 module. + +config I2C_MXC_SELECT3 + bool "Enable I2C3 module" + default n + depends on I2C_MXC + help + Enable MX31 I2C3 module. + +endmenu + endmenu diff -urN linux-2.6.26/arch/arm/mach-mx3/Makefile linux-2.6.26-lab126/arch/arm/mach-mx3/Makefile --- linux-2.6.26/arch/arm/mach-mx3/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/Makefile 2010-08-10 04:14:16.000000000 -0400 @@ -4,5 +4,17 @@ # Object file lists. -obj-y := mm.o time.o -obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o +obj-y := system.o iomux.o cpu.o mm.o clock.o dptc.o devices.o serial.o dma.o mxc_pm.o dvfs_v2.o +obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o mx31ads_gpio.o +obj-$(CONFIG_MACH_MX31_3DS) += mx3_3stack.o mx3_3stack_gpio.o + +# power management +obj-$(CONFIG_PM) += pm.o + +obj-$(CONFIG_USB_EHCI_ARC_H1) += usb_h1.o +obj-$(CONFIG_USB_EHCI_ARC_H2) += usb_h2.o + +ifneq ($(strip $(CONFIG_USB_GADGET_ARC) $(CONFIG_USB_EHCI_ARC_OTG)),) + obj-y += usb_dr.o +endif + diff -urN linux-2.6.26/arch/arm/mach-mx3/board-mx31ads.h linux-2.6.26-lab126/arch/arm/mach-mx3/board-mx31ads.h --- linux-2.6.26/arch/arm/mach-mx3/board-mx31ads.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/board-mx31ads.h 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,326 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ +#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ + +#ifdef CONFIG_MACH_MX31ADS +/*! + * @defgroup BRDCFG_MX31 Board Configuration Options + * @ingroup MSL_MX31 + */ + +/*! + * @file mach-mx3/board-mx31ads.h + * + * @brief This file contains all the board level configuration options. + * + * It currently hold the options defined for MX31 ADS Platform. + * + * @ingroup BRDCFG_MX31 + */ + +/* + * Include Files + */ +#include + +/*! + * @name MXC UART EVB board level configurations + */ +/*! @{ */ +/*! + * Specifies if the Irda transmit path is inverting + */ +#define MXC_IRDA_TX_INV 0 +/*! + * Specifies if the Irda receive path is inverting + */ +#define MXC_IRDA_RX_INV 0 + +/* UART 1 configuration */ +/*! + * This define specifies if the UART port is configured to be in DTE or + * DCE mode. There exists a define like this for each UART port. Valid + * values that can be used are \b MODE_DTE or \b MODE_DCE. + */ +#define UART1_MODE MODE_DCE +/*! + * This define specifies if the UART is to be used for IRDA. There exists a + * define like this for each UART port. Valid values that can be used are + * \b IRDA or \b NO_IRDA. + */ +#define UART1_IR NO_IRDA +/*! + * This define is used to enable or disable a particular UART port. If + * disabled, the UART will not be registered in the file system and the user + * will not be able to access it. There exists a define like this for each UART + * port. Specify a value of 1 to enable the UART and 0 to disable it. + */ +#define UART1_ENABLED 1 +/*! @} */ +/* UART 2 configuration */ +#define UART2_MODE MODE_DCE +#define UART2_IR IRDA +#ifdef CONFIG_MXC_FIR_MODULE +#define UART2_ENABLED 0 +#else +#define UART2_ENABLED 1 +#endif +/* UART 3 configuration */ +#define UART3_MODE MODE_DTE +#define UART3_IR NO_IRDA +#define UART3_ENABLED 1 +/* UART 4 configuration */ +#define UART4_MODE MODE_DTE +#define UART4_IR NO_IRDA +#define UART4_ENABLED 0 /* Disable UART 4 as its pins are shared with ATA */ +/* UART 5 configuration */ +#define UART5_MODE MODE_DTE +#define UART5_IR NO_IRDA +#define UART5_ENABLED 1 + +#define MXC_LL_EXTUART_PADDR (CS4_BASE_ADDR + 0x10000) +#define MXC_LL_EXTUART_VADDR CS4_IO_ADDRESS(MXC_LL_EXTUART_PADDR) +#undef MXC_LL_EXTUART_16BIT_BUS + +#define MXC_LL_UART_PADDR UART1_BASE_ADDR +#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) + +/*! + * @name PBC Controller parameters + */ +/*! @{ */ +/*! + * Base address of PBC controller + */ +#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) +/* Offsets for the PBC Controller register */ +/*! + * PBC Board status register offset + */ +#define PBC_BSTAT 0x000002 +/*! + * PBC Board control register 1 set address. + */ +#define PBC_BCTRL1_SET 0x000004 +/*! + * PBC Board control register 1 clear address. + */ +#define PBC_BCTRL1_CLEAR 0x000006 +/*! + * PBC Board control register 2 set address. + */ +#define PBC_BCTRL2_SET 0x000008 +/*! + * PBC Board control register 2 clear address. + */ +#define PBC_BCTRL2_CLEAR 0x00000A +/*! + * PBC Board control register 3 set address. + */ +#define PBC_BCTRL3_SET 0x00000C +/*! + * PBC Board control register 3 clear address. + */ +#define PBC_BCTRL3_CLEAR 0x00000E +/*! + * PBC Board control register 4 set address. + */ +#define PBC_BCTRL4_SET 0x000010 +/*! + * PBC Board control register 4 clear address. + */ +#define PBC_BCTRL4_CLEAR 0x000012 +/*! + * PBC Board status register 1. + */ +#define PBC_BSTAT1 0x000014 +/*! + * PBC Board interrupt status register. + */ +#define PBC_INTSTATUS 0x000016 +/*! + * PBC Board interrupt current status register. + */ +#define PBC_INTCURR_STATUS 0x000018 +/*! + * PBC Interrupt mask register set address. + */ +#define PBC_INTMASK_SET 0x00001A +/*! + * PBC Interrupt mask register clear address. + */ +#define PBC_INTMASK_CLEAR 0x00001C + +/*! + * External UART A. + */ +#define PBC_SC16C652_UARTA 0x010000 +/*! + * External UART B. + */ +#define PBC_SC16C652_UARTB 0x010010 +/*! + * Ethernet Controller IO base address. + */ +#define PBC_CS8900A_IOBASE 0x020000 +/*! + * Ethernet Controller Memory base address. + */ +#define PBC_CS8900A_MEMBASE 0x021000 +/*! + * Ethernet Controller DMA base address. + */ +#define PBC_CS8900A_DMABASE 0x022000 +/*! + * External chip select 0. + */ +#define PBC_XCS0 0x040000 +/*! + * LCD Display enable. + */ +#define PBC_LCD_EN_B 0x060000 +/*! + * Code test debug enable. + */ +#define PBC_CODE_B 0x070000 +/*! + * PSRAM memory select. + */ +#define PBC_PSRAM_B 0x5000000 + +/* PBC Board Status Register 1 bit definitions */ +#define PBC_BSTAT1_NF_DET 0x0001 /* NAND flash card. 0 = connected */ +#define PBC_BSTAT1_KP_ON 0x0002 /* KPP board. 0 = connected */ +#define PBC_BSTAT1_LS 0x0004 /* KPP:LightSense signal */ +#define PBC_BSTAT1_ATA_IOCS16 0x0008 /* ATA_IOCS16 signal */ +#define PBC_BSTAT1_ATA_CBLID 0x0010 /* ATA_CBLID signal */ +#define PBC_BSTAT1_ATA_DASP 0x0020 /* ATA_DASP signal */ +#define PBC_BSTAT1_PWR_RDY 0x0040 /* MC13783 power. 1 = ready */ +#define PBC_BSTAT1_SD1_WP 0x0080 /* 0 = SD1 card is write protected */ +#define PBC_BSTAT1_SD2_WP 0x0100 /* 0 = SD2 card is write protected */ +#define PBC_BSTAT1_FS1 0x0200 /* KPP:FlipSense1 signal */ +#define PBC_BSTAT1_FS2 0x0400 /* KPP:FlipSense2 signal */ +#define PBC_BSTAT1_PTT 0x0800 /* KPP:PTT signal */ +#define PBC_BSTAT1_MC13783_IN 0x1000 /* MC13783 board. 0 = connected. */ + +/* PBC Board Control Register 1 bit definitions */ +#define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */ +#define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */ +#define PBC_BCTRL1_UENA 0x0004 /* Enable UART A transceiver */ +#define PBC_BCTRL1_UENB 0x0008 /* Enable UART B transceiver */ +#define PBC_BCTRL1_UENCE 0x0010 /* Enable UART CE transceiver */ +#define PBC_BCTRL1_IREN 0x0020 /* Enable the IRDA transmitter */ +#define PBC_BCTRL1_LED0 0x0040 /* Used to control LED 0 (green) */ +#define PBC_BCTRL1_LED1 0x0080 /* Used to control LED 1 (yellow) */ +#define PBC_BCTRL1_SENSOR1_ON 0x0600 /* Enable Sensor 1 */ +#define PBC_BCTRL1_SENSOR2_ON 0x3000 /* Enable Sensor 2 */ +#define PBC_BCTRL1_BEND 0x4000 /* Big Endian Select */ +#define PBC_BCTRL1_LCDON 0x8000 /* Enable the LCD */ + +/* PBC Board Control Register 2 bit definitions */ +#define PBC_BCTRL2_USELA 0x0001 /* UART A Select, 0 = UART1, 1 = UART5 */ +#define PBC_BCTRL2_USELB 0x0002 /* UART B Select, 0 = UART3, 1 = UART5 */ +#define PBC_BCTRL2_USELC 0x0004 /* UART C Select, 0 = UART2, 1 = UART1 */ +#define PBC_BCTRL2_UMODENA 0x0008 /* UART A Modem Signals Enable, 0 = enabled */ +#define PBC_BCTRL2_UMODENC 0x0008 /* UART C Modem Signals Enable, 0 = enabled */ +#define PBC_BCTRL2_CSI_EN 0x0020 /* Enable the CSI interface, 0 = enabled */ +#define PBC_BCTRL2_ATA_EN 0x0040 /* Enable the ATA interface, 0 = enabled */ +#define PBC_BCTRL2_ATA_SEL 0x0080 /* ATA Select, 0 = group A, 1 = group B */ +#define PBC_BCTRL2_IRDA_MOD 0x0100 /* IRDA Mode (see CPLD spec) */ +#define PBC_BCTRL2_LDC_RST0 0x0200 /* LCD 0 Reset, 1 = reset signal asserted */ +#define PBC_BCTRL2_LDC_RST1 0x0400 /* LCD 1 Reset, 1 = reset signal asserted */ +#define PBC_BCTRL2_LDC_RST2 0x0800 /* LCD 2 Reset, 1 = reset signal asserted */ +#define PBC_BCTRL2_LDCIO_EN 0x1000 /* LCD GPIO Enable, 0 = enabled */ +#define PBC_BCTRL2_CT_CS 0x2000 /* Code Test Chip Select, = Code Test selected */ +#define PBC_BCTRL2_VPP_EN 0x4000 /* PCMCIA VPP Enable, 1 = power on */ +#define PBC_BCTRL2_VCC_EN 0x8000 /* PCMCIA VCC Enable, 1 = power on */ + +/* PBC Board Control Register 3 bit definitions */ +#define PBC_BCTRL3_OTG_FS_SEL 0x0001 /* USB OTG Full Speed Select, 0 = PMIC, 1 = CPU */ +#define PBC_BCTRL3_OTG_FS_EN 0x0002 /* USB OTG Full Speed Enable, 0 = enabled */ +#define PBC_BCTRL3_FSH_SEL 0x0004 /* USB Full Speed Host Select, 0 = Group A, 1 = Group B */ +#define PBC_BCTRL3_FSH_EN 0x0008 /* USB Full Speed Host Enable, 0 = enabled */ +#define PBC_BCTRL3_HSH_SEL 0x0010 /* USB High Speed Host Select, 0 = Group A, 1 = Group B */ +#define PBC_BCTRL3_HSH_EN 0x0020 /* USB High Speed Host Enable, 0 = enabled */ +#define PBC_BCTRL3_FSH_MOD 0x0040 /* USB Full Speed Host Mode, 0 = Differential, 1 = Single ended */ +#define PBC_BCTRL3_OTG_HS_EN 0x0080 /* USB OTG High Speed Enable, 0 = enabled */ +#define PBC_BCTRL3_OTG_VBUS_EN 0x0100 /* USB OTG VBUS Regulator Enable, 0 = enabled */ +#define PBC_BCTRL3_FSH_VBUS_EN 0x0200 /* USB Full Speed Host VBUS Regulator Enable, 0 = enabled */ +#define PBC_BCTRL3_CARD1_SEL 0x0400 /* Card1 Select, 0 = SD1, 1 = MS1 */ +#define PBC_BCTRL3_CARD2_SEL 0x0800 /* Card2 Select, 0 = PCMCIA & SD2, 1 = MS2 */ +#define PBC_BCTRL3_SYNTH_RST 0x1000 /* Audio Synthesizer Reset, 0 = reset asserted */ +#define PBC_BCTRL3_VSIM_EN 0x2000 /* VSIM Regulator Enable, 1 = enabled */ +#define PBC_BCTRL3_VESIM_EN 0x4000 /* VESIM Regulator Enable, 1 = enabled */ +#define PBC_BCTRL3_SPI3_RESET 0x8000 /* CSPI3 Connector Reset, 0 = reset asserted */ + +/* PBC Board Control Register 4 bit definitions */ +#define PBC_BCTRL4_CSI_MSB_EN 0x0001 /* CSI MSB Enable, 0 = CSI_Data[3:0] enabled */ +#define PBC_BCTRL4_REGEN_SEL 0x0002 /* Regulator Enable Select, 0 = enabled */ +#define PBC_BCTRL4_USER_OFF 0x0004 /* User Off Indication, 1 = user off confirmation */ +#define PBC_BCTRL4_VIB_EN 0x0008 /* Vibrator Enable, 1 = enabled */ +#define PBC_BCTRL4_PCMCIA_EN 0x0010 /* PCMCIA Enable, 0 = buffer enabled */ + +#define CKIH_27MHZ_BIT_SET (1 << 4) + +#define PBC_INT_CS8900A 4 +/*! @} */ + +#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) +#define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS) +#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS) +#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) +#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4) + +#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0) +#define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1) +#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2) +#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3) +#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4) +#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5) +#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6) +#define EXPIO_INT_RES7 (MXC_EXP_IO_BASE + 7) +#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8) +#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9) +#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) +#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11) +#define EXPIO_INT_SYNTH_IRQ (MXC_EXP_IO_BASE + 12) +#define EXPIO_INT_CE_INT1 (MXC_EXP_IO_BASE + 13) +#define EXPIO_INT_CE_INT2 (MXC_EXP_IO_BASE + 14) +#define EXPIO_INT_RES15 (MXC_EXP_IO_BASE + 15) + +/*! + * @name Defines Base address and IRQ used for CS8900A Ethernet Controller on MXC Boards + */ +/*! @{*/ +/*! This is System IRQ used by CS8900A for interrupt generation taken from platform.h */ +#define CS8900AIRQ EXPIO_INT_ENET_INT +/*! This is I/O Base address used to access registers of CS8900A on MXC ADS */ +#define CS8900A_BASE_ADDRESS (PBC_BASE_ADDRESS + PBC_CS8900A_IOBASE + 0x300) +/*! @} */ + +#define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX31_PIN_GPIO1_3) + +#define AHB_FREQ 133000000 +#define IPG_FREQ 66500000 + +#define MXC_BD_LED1 (1 << 6) +#define MXC_BD_LED2 (1 << 7) +#define MXC_BD_LED_ON(led) \ + __raw_writew(led, PBC_BASE_ADDRESS + PBC_BCTRL1_SET) +#define MXC_BD_LED_OFF(led) \ + __raw_writew(led, PBC_BASE_ADDRESS + PBC_BCTRL1_CLEAR) + +#endif /* CONFIG_MACH_MX31ADS */ +#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx3/board-mx3_3stack.h linux-2.6.26-lab126/arch/arm/mach-mx3/board-mx3_3stack.h --- linux-2.6.26/arch/arm/mach-mx3/board-mx3_3stack.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/board-mx3_3stack.h 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,150 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__ +#define __ASM_ARCH_MXC_BOARD_MX31PDK_H__ + +#ifdef CONFIG_MACH_MX31_3DS +/*! + * @defgroup BRDCFG_MX31 Board Configuration Options + * @ingroup MSL_MX31 + */ + +/*! + * @file mach-mx3/board-mx3_3stack.h + * + * @brief This file contains all the board level configuration options. + * + * It currently hold the options defined for MX31 3STACK Platform. + * + * @ingroup BRDCFG_MX31 + */ + +/* + * Include Files + */ +#include + +/*! + * @name MXC UART EVB board level configurations + */ +/*! @{ */ +/*! + * Specifies if the Irda transmit path is inverting + */ +#define MXC_IRDA_TX_INV 0 +/*! + * Specifies if the Irda receive path is inverting + */ +#define MXC_IRDA_RX_INV 0 + +/* UART 1 configuration */ +/*! + * This define specifies if the UART port is configured to be in DTE or + * DCE mode. There exists a define like this for each UART port. Valid + * values that can be used are \b MODE_DTE or \b MODE_DCE. + */ +#define UART1_MODE MODE_DCE +/*! + * This define specifies if the UART is to be used for IRDA. There exists a + * define like this for each UART port. Valid values that can be used are + * \b IRDA or \b NO_IRDA. + */ +#define UART1_IR NO_IRDA +/*! + * This define is used to enable or disable a particular UART port. If + * disabled, the UART will not be registered in the file system and the user + * will not be able to access it. There exists a define like this for each UART + * port. Specify a value of 1 to enable the UART and 0 to disable it. + */ +#define UART1_ENABLED 1 +/*! @} */ +/* UART 2 configuration */ +#define UART2_MODE MODE_DCE +#define UART2_IR NO_IRDA +#define UART2_ENABLED 1 +/* UART 3 configuration */ +#define UART3_MODE MODE_DTE +#define UART3_IR NO_IRDA +#define UART3_ENABLED 1 +/* UART 4 configuration */ +#define UART4_MODE MODE_DTE +#define UART4_IR NO_IRDA +#define UART4_ENABLED 0 /* Disable UART 4 as its pins are shared with ATA */ +/* UART 5 configuration */ +#define UART5_MODE MODE_DTE +#define UART5_IR NO_IRDA +#define UART5_ENABLED 0 + +#define MXC_LL_UART_PADDR UART1_BASE_ADDR +#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) + +#define DEBUG_BASE_ADDRESS CS5_BASE_ADDR +/* LAN9217 ethernet base address */ +#define LAN9217_BASE_ADDR DEBUG_BASE_ADDRESS +/* External UART */ +#define UARTA_BASE_ADDR (DEBUG_BASE_ADDRESS + 0x8000) +#define UARTB_BASE_ADDR (DEBUG_BASE_ADDRESS + 0x10000) + +#define BOARD_IO_ADDR (DEBUG_BASE_ADDRESS + 0x20000) +/* LED switchs */ +#define LED_SWITCH_REG 0x00 +/* buttons */ +#define SWITCH_BUTTONS_REG 0x08 +/* status, interrupt */ +#define INTR_STATUS_REG 0x10 +#define INTR_MASK_REG 0x38 +#define INTR_RESET_REG 0x20 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER1_REG 0x40 +#define MAGIC_NUMBER2_REG 0x48 +/* CPLD code version */ +#define CPLD_CODE_VER_REG 0x50 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER3_REG 0x58 +/* module reset register*/ +#define MODULE_RESET_REG 0x60 +/* CPU ID and Personality ID */ +#define MCU_BOARD_ID_REG 0x68 + +/* interrupts like external uart , external ethernet etc*/ +#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1) + +#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0) +#define EXPIO_INT_XUART_A (MXC_EXP_IO_BASE + 1) +#define EXPIO_INT_XUART_B (MXC_EXP_IO_BASE + 2) +#define EXPIO_INT_BUTTON_A (MXC_EXP_IO_BASE + 3) +#define EXPIO_INT_BUTTON_B (MXC_EXP_IO_BASE + 4) + +/*! This is System IRQ used by LAN9217 */ +#define LAN9217_IRQ EXPIO_INT_ENET + +/*! LED definition*/ +#define MXC_BD_LED1 (1) +#define MXC_BD_LED2 (1 << 1) +#define MXC_BD_LED3 (1 << 2) +#define MXC_BD_LED4 (1 << 3) +#define MXC_BD_LED5 (1 << 4) +#define MXC_BD_LED6 (1 << 5) +#define MXC_BD_LED7 (1 << 6) +#define MXC_BD_LED8 (1 << 7) + +#define MXC_BD_LED_ON(led) +#define MXC_BD_LED_OFF(led) + +extern unsigned int sdhc_get_card_det_status(struct device *dev); +extern int sdhc_init_card_det(int id); +extern int sdhc_write_protect(struct device *dev); + +#endif /* CONFIG_MACH_MX31_3DS */ +#endif /* __ASM_ARCH_MXC_BOARD_MX31PDK_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx3/clock.c linux-2.6.26-lab126/arch/arm/mach-mx3/clock.c --- linux-2.6.26/arch/arm/mach-mx3/clock.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/clock.c 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,1380 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "crm_regs.h" + +#define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */ +#define PROPAGATE_RATE_DIS 2 + +static int cpu_clk_set_wp(int wp); +struct timer_list dptcen_timer; + +static void __calc_pre_post_dividers(u32 div, u32 * pre, u32 * post) +{ + u32 min_pre, temp_pre, old_err, err; + + if (div >= 512) { + *pre = 8; + *post = 64; + } else if (div >= 64) { + min_pre = (div - 1) / 64 + 1; + old_err = 8; + for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) { + err = div % temp_pre; + if (err == 0) { + *pre = temp_pre; + break; + } + err = temp_pre - err; + if (err < old_err) { + old_err = err; + *pre = temp_pre; + } + } + *post = (div + *pre - 1) / *pre; + } else if (div <= 8) { + *pre = div; + *post = 1; + } else { + *pre = 1; + *post = div; + } +} + +static struct clk mcu_pll_clk; +static struct clk mcu_main_clk; +static struct clk usb_pll_clk; +static struct clk serial_pll_clk; +static struct clk ipg_clk; +static struct clk ckih_clk; +static struct clk ahb_clk; + +static int _clk_enable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg |= 3 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + return 0; +} + +static void _clk_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(3 << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); +} + +static void _clk_emi_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(3 << clk->enable_shift); + reg |= (1 << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); +} + +static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + signed long pd = 1; /* Pre-divider */ + signed long mfi; /* Multiplication Factor (Integer part) */ + signed long mfn; /* Multiplication Factor (Integer part) */ + signed long mfd; /* Multiplication Factor (Denominator Part) */ + signed long tmp; + u32 ref_freq = clk->parent->rate; + + while (((ref_freq / pd) * 10) > rate) { + pd++; + } + + if ((ref_freq / pd) < PRE_DIV_MIN_FREQ) { + return -EINVAL; + } + + /* the ref_freq/2 in the following is to round up */ + mfi = (((rate / 2) * pd) + (ref_freq / 2)) / ref_freq; + if (mfi < 5 || mfi > 15) { + return -EINVAL; + } + + /* pick a mfd value that will work + * then solve for mfn */ + mfd = ref_freq / 50000; + + /* + * pll_freq * pd * mfd + * mfn = -------------------- - (mfi * mfd) + * 2 * ref_freq + */ + /* the tmp/2 is for rounding */ + tmp = ref_freq / 10000; + mfn = + ((((((rate / 2) + (tmp / 2)) / tmp) * pd) * mfd) / 10000) - + (mfi * mfd); + + mfn = mfn & 0x3ff; + pd--; + mfd--; + + /* Change the Pll value */ + reg = (mfi << MXC_CCM_PCTL_MFI_OFFSET) | + (mfn << MXC_CCM_PCTL_MFN_OFFSET) | + (mfd << MXC_CCM_PCTL_MFD_OFFSET) | (pd << MXC_CCM_PCTL_PD_OFFSET); + + if (clk == &mcu_pll_clk) { + __raw_writel(reg, MXC_CCM_MPCTL); + } else if (clk == &usb_pll_clk) { + __raw_writel(reg, MXC_CCM_UPCTL); + } else if (clk == &serial_pll_clk) { + __raw_writel(reg, MXC_CCM_SRPCTL); + } + + clk->rate = rate; + return 0; +} + +static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate) +{ + if ((rate < ahb_clk.rate) || (rate % ahb_clk.rate != 0)) { + printk(KERN_ERR "Wrong rate %lu in _clk_cpu_set_rate\n", rate); + return -EINVAL; + } + + cpu_clk_set_wp(rate / ahb_clk.rate - 1); + + return PROPAGATE_RATE_DIS; +} + +static void _clk_pll_recalc(struct clk *clk) +{ + long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; + volatile unsigned long reg, ccmr; + s64 temp; + unsigned int prcs; + + ccmr = __raw_readl(MXC_CCM_CCMR); + prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET; + if (prcs == 0x1) { + ref_clk = CKIL_CLK_FREQ * 1024; + } else { + ref_clk = ckih_clk.rate; + } + + if (clk == &mcu_pll_clk) { + if ((ccmr & MXC_CCM_CCMR_MPE) == 0) { + clk->rate = ref_clk; + return; + } + if ((ccmr & MXC_CCM_CCMR_MDS) != 0) { + clk->rate = ref_clk; + return; + } + reg = __raw_readl(MXC_CCM_MPCTL); + } else if (clk == &usb_pll_clk) { + reg = __raw_readl(MXC_CCM_UPCTL); + } else if (clk == &serial_pll_clk) { + reg = __raw_readl(MXC_CCM_SRPCTL); + } else { + BUG(); + } + pdf = (reg & MXC_CCM_PCTL_PD_MASK) >> MXC_CCM_PCTL_PD_OFFSET; + mfd = (reg & MXC_CCM_PCTL_MFD_MASK) >> MXC_CCM_PCTL_MFD_OFFSET; + mfi = (reg & MXC_CCM_PCTL_MFI_MASK) >> MXC_CCM_PCTL_MFI_OFFSET; + mfi = (mfi <= 5) ? 5 : mfi; + mfn = mfn_abs = reg & MXC_CCM_PCTL_MFN_MASK; + + if (mfn >= 0x200) { + mfn |= 0xFFFFFE00; + mfn_abs = -mfn; + } + + ref_clk *= 2; + ref_clk /= pdf + 1; + + temp = (u64) ref_clk *mfn_abs; + do_div(temp, mfd + 1); + if (mfn < 0) + temp = -temp; + temp = (ref_clk * mfi) + temp; + + clk->rate = temp; +} + +static int _clk_usb_pll_enable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(MXC_CCM_CCMR); + reg |= MXC_CCM_CCMR_UPE; + __raw_writel(reg, MXC_CCM_CCMR); + + /* No lock bit on MX31, so using max time from spec */ + udelay(80); + + return 0; +} + +static void _clk_usb_pll_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCMR); + reg &= ~MXC_CCM_CCMR_UPE; + __raw_writel(reg, MXC_CCM_CCMR); +} + +static int _clk_serial_pll_enable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(MXC_CCM_CCMR); + reg |= MXC_CCM_CCMR_SPE; + __raw_writel(reg, MXC_CCM_CCMR); + + /* No lock bit on MX31, so using max time from spec */ + udelay(80); + + return 0; +} + +static void _clk_serial_pll_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCMR); + reg &= ~MXC_CCM_CCMR_SPE; + __raw_writel(reg, MXC_CCM_CCMR); +} + +#define PDR0(mask, off) ((__raw_readl(MXC_CCM_PDR0) & mask) >> off) +#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off) +#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off) + +static void _clk_mcu_main_recalc(struct clk *clk) +{ + u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0); + + if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL) { + serial_pll_clk.recalc(&serial_pll_clk); + clk->rate = serial_pll_clk.rate; + } else { + mcu_pll_clk.recalc(&mcu_pll_clk); + clk->rate = mcu_pll_clk.rate; + } +} + +static void _clk_cpu_recalc(struct clk *clk) +{ + unsigned long mcu_pdf; + + mcu_pdf = PDR0(MXC_CCM_PDR0_MCU_PODF_MASK, + MXC_CCM_PDR0_MCU_PODF_OFFSET); + clk->rate = clk->parent->rate / (mcu_pdf + 1); +} + +static void _clk_hclk_recalc(struct clk *clk) +{ + unsigned long max_pdf; + + max_pdf = PDR0(MXC_CCM_PDR0_MAX_PODF_MASK, + MXC_CCM_PDR0_MAX_PODF_OFFSET); + clk->rate = clk->parent->rate / (max_pdf + 1); +} + +static void _clk_ipg_recalc(struct clk *clk) +{ + unsigned long ipg_pdf; + + ipg_pdf = PDR0(MXC_CCM_PDR0_IPG_PODF_MASK, + MXC_CCM_PDR0_IPG_PODF_OFFSET); + clk->rate = clk->parent->rate / (ipg_pdf + 1); +} + +static void _clk_nfc_recalc(struct clk *clk) +{ + unsigned long nfc_pdf; + + nfc_pdf = PDR0(MXC_CCM_PDR0_NFC_PODF_MASK, + MXC_CCM_PDR0_NFC_PODF_OFFSET); + clk->rate = clk->parent->rate / (nfc_pdf + 1); +} + +static void _clk_hsp_recalc(struct clk *clk) +{ + unsigned long hsp_pdf; + + hsp_pdf = PDR0(MXC_CCM_PDR0_HSP_PODF_MASK, + MXC_CCM_PDR0_HSP_PODF_OFFSET); + clk->rate = clk->parent->rate / (hsp_pdf + 1); +} + +static void _clk_usb_recalc(struct clk *clk) +{ + unsigned long usb_pdf, usb_prepdf; + + usb_pdf = PDR1(MXC_CCM_PDR1_USB_PODF_MASK, + MXC_CCM_PDR1_USB_PODF_OFFSET); + usb_prepdf = PDR1(MXC_CCM_PDR1_USB_PRDF_MASK, + MXC_CCM_PDR1_USB_PRDF_OFFSET); + clk->rate = clk->parent->rate / (usb_prepdf + 1) / (usb_pdf + 1); +} + +static void _clk_csi_recalc(struct clk *clk) +{ + u32 reg; + u32 pre, post; + + reg = __raw_readl(MXC_CCM_PDR0); + pre = (reg & MXC_CCM_PDR0_CSI_PRDF_MASK) >> + MXC_CCM_PDR0_CSI_PRDF_OFFSET; + pre++; + post = (reg & MXC_CCM_PDR0_CSI_PODF_MASK) >> + MXC_CCM_PDR0_CSI_PODF_OFFSET; + post++; + clk->rate = clk->parent->rate / (pre * post); +} + +static unsigned long _clk_csi_round_rate(struct clk *clk, unsigned long rate) +{ + u32 pre, post; + u32 div = clk->parent->rate / rate; + if (clk->parent->rate % rate) + div++; + + __calc_pre_post_dividers(div, &pre, &post); + + return clk->parent->rate / (pre * post); +} + +static int _clk_csi_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 pre, post; + + div = clk->parent->rate / rate; + + if ((clk->parent->rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + /* Set CSI clock divider */ + reg = __raw_readl(MXC_CCM_PDR0) & + ~(MXC_CCM_PDR0_CSI_PODF_MASK | MXC_CCM_PDR0_CSI_PRDF_MASK); + reg |= (post - 1) << MXC_CCM_PDR0_CSI_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_PDR0_CSI_PRDF_OFFSET; + __raw_writel(reg, MXC_CCM_PDR0); + + clk->rate = rate; + return 0; +} + +static void _clk_per_recalc(struct clk *clk) +{ + unsigned long per_pdf; + + per_pdf = PDR0(MXC_CCM_PDR0_PER_PODF_MASK, + MXC_CCM_PDR0_PER_PODF_OFFSET); + clk->rate = clk->parent->rate / (per_pdf + 1); +} + +static void _clk_ssi1_recalc(struct clk *clk) +{ + unsigned long ssi1_pdf, ssi1_prepdf; + + ssi1_pdf = PDR1(MXC_CCM_PDR1_SSI1_PODF_MASK, + MXC_CCM_PDR1_SSI1_PODF_OFFSET); + ssi1_prepdf = PDR1(MXC_CCM_PDR1_SSI1_PRE_PODF_MASK, + MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET); + clk->rate = clk->parent->rate / (ssi1_prepdf + 1) / (ssi1_pdf + 1); +} + +static void _clk_ssi2_recalc(struct clk *clk) +{ + unsigned long ssi2_pdf, ssi2_prepdf; + + ssi2_pdf = PDR1(MXC_CCM_PDR1_SSI2_PODF_MASK, + MXC_CCM_PDR1_SSI2_PODF_OFFSET); + ssi2_prepdf = PDR1(MXC_CCM_PDR1_SSI2_PRE_PODF_MASK, + MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET); + clk->rate = clk->parent->rate / (ssi2_prepdf + 1) / (ssi2_pdf + 1); +} + +static void _clk_firi_recalc(struct clk *clk) +{ + unsigned long firi_pdf, firi_prepdf; + + firi_pdf = PDR1(MXC_CCM_PDR1_FIRI_PODF_MASK, + MXC_CCM_PDR1_FIRI_PODF_OFFSET); + firi_prepdf = PDR1(MXC_CCM_PDR1_FIRI_PRE_PODF_MASK, + MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET); + clk->rate = clk->parent->rate / (firi_prepdf + 1) / (firi_pdf + 1); +} + +static unsigned long _clk_firi_round_rate(struct clk *clk, unsigned long rate) +{ + u32 pre, post; + u32 div = clk->parent->rate / rate; + if (clk->parent->rate % rate) + div++; + + __calc_pre_post_dividers(div, &pre, &post); + + return clk->parent->rate / (pre * post); + +} + +static int _clk_firi_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div, pre, post; + + div = clk->parent->rate / rate; + + if ((clk->parent->rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + /* Set FIRI clock divider */ + reg = __raw_readl(MXC_CCM_PDR1) & + ~(MXC_CCM_PDR1_FIRI_PODF_MASK | MXC_CCM_PDR1_FIRI_PRE_PODF_MASK); + reg |= (pre - 1) << MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET; + reg |= (post - 1) << MXC_CCM_PDR1_FIRI_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_PDR1); + + clk->rate = rate; + return 0; +} + +static void _clk_mbx_recalc(struct clk *clk) +{ + clk->rate = clk->parent->rate / 2; +} + +static void _clk_mstick1_recalc(struct clk *clk) +{ + unsigned long msti_pdf; + + msti_pdf = PDR2(MXC_CCM_PDR2_MST1_PDF_MASK, + MXC_CCM_PDR2_MST1_PDF_OFFSET); + clk->rate = clk->parent->rate / (msti_pdf + 1); +} + +static void _clk_mstick2_recalc(struct clk *clk) +{ + unsigned long msti_pdf; + + msti_pdf = PDR2(MXC_CCM_PDR2_MST2_PDF_MASK, + MXC_CCM_PDR2_MST2_PDF_OFFSET); + clk->rate = clk->parent->rate / (msti_pdf + 1); +} + +static struct clk ckih_clk = { + .name = "ckih", + .rate = 0, /* determined later (26 or 27 MHz) */ + .flags = RATE_PROPAGATES, +}; + +static struct clk ckil_clk = { + .name = "ckil", + .rate = CKIL_CLK_FREQ, + .flags = RATE_PROPAGATES, +}; + +static struct clk mcu_pll_clk = { + .name = "mcu_pll", + .parent = &ckih_clk, + .set_rate = _clk_pll_set_rate, + .recalc = _clk_pll_recalc, + .flags = RATE_PROPAGATES, +}; + +static struct clk mcu_main_clk = { + .name = "mcu_main_clk", + .parent = &mcu_pll_clk, + .recalc = _clk_mcu_main_recalc, +}; + +static struct clk serial_pll_clk = { + .name = "serial_pll", + .parent = &ckih_clk, + .set_rate = _clk_pll_set_rate, + .recalc = _clk_pll_recalc, + .enable = _clk_serial_pll_enable, + .disable = _clk_serial_pll_disable, + .flags = RATE_PROPAGATES, +}; + +static struct clk usb_pll_clk = { + .name = "usb_pll", + .parent = &ckih_clk, + .set_rate = _clk_pll_set_rate, + .recalc = _clk_pll_recalc, + .enable = _clk_usb_pll_enable, + .disable = _clk_usb_pll_disable, + .flags = RATE_PROPAGATES, +}; + +static struct clk cpu_clk = { + .name = "cpu_clk", + .parent = &mcu_main_clk, + .recalc = _clk_cpu_recalc, + .set_rate = _clk_cpu_set_rate, +}; + +static struct clk ahb_clk = { + .name = "ahb_clk", + .parent = &mcu_main_clk, + .recalc = _clk_hclk_recalc, + .flags = RATE_PROPAGATES, +}; + +static struct clk per_clk = { + .name = "per_clk", + .parent = &usb_pll_clk, + .recalc = _clk_per_recalc, + .flags = RATE_PROPAGATES, +}; + +static struct clk perclk_clk = { + .name = "perclk_clk", + .parent = &ipg_clk, + .flags = RATE_PROPAGATES, +}; + +static struct clk cspi_clk[] = { + { + .name = "cspi_clk", + .id = 0, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_CSPI1_OFFSET, + .disable = _clk_disable,}, + { + .name = "cspi_clk", + .id = 1, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_CSPI2_OFFSET, + .disable = _clk_disable,}, + { + .name = "cspi_clk", + .id = 2, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_CSPI3_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk ipg_clk = { + .name = "ipg_clk", + .parent = &ahb_clk, + .recalc = _clk_ipg_recalc, + .flags = RATE_PROPAGATES, +}; + +static struct clk emi_clk = { + .name = "emi_clk", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_EMI_OFFSET, + .disable = _clk_emi_disable, +}; + +static struct clk gpt_clk = { + .name = "gpt_clk", + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_GPT_OFFSET, + .disable = _clk_disable, +}; + +static struct clk pwm_clk = { + .name = "pwm_clk", + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR1_PWM_OFFSET, + .disable = _clk_disable, +}; + +static struct clk epit_clk[] = { + { + .name = "epit_clk", + .id = 0, + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_EPIT1_OFFSET, + .disable = _clk_disable,}, + { + .name = "epit_clk", + .id = 1, + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_EPIT2_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk nfc_clk = { + .name = "nfc_clk", + .parent = &ahb_clk, + .recalc = _clk_nfc_recalc, +}; + +static struct clk scc_clk = { + .name = "scc_clk", + .parent = &ipg_clk, +}; + +static struct clk ipu_clk = { + .name = "ipu_clk", + .parent = &mcu_main_clk, + .recalc = _clk_hsp_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_IPU_OFFSET, + .disable = _clk_disable, +}; + +static struct clk kpp_clk = { + .name = "kpp_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_KPP_OFFSET, + .disable = _clk_disable, +}; + +static struct clk wdog_clk = { + .name = "wdog_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_WDOG_OFFSET, + .disable = _clk_disable, +}; +static struct clk rtc_clk = { + .name = "rtc_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_RTC_OFFSET, + .disable = _clk_disable, +}; + +static struct clk usb_clk[] = { + { + .name = "usb_clk", + .parent = &usb_pll_clk, + .recalc = _clk_usb_recalc,}, + { + .name = "usb_ahb_clk", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_USBOTG_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk csi_clk = { + .name = "csi_clk", + .parent = &serial_pll_clk, + .recalc = _clk_csi_recalc, + .round_rate = _clk_csi_round_rate, + .set_rate = _clk_csi_set_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_CSI_OFFSET, + .disable = _clk_disable, +}; + +static struct clk uart_clk[] = { + { + .name = "uart_clk", + .id = 0, + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_UART1_OFFSET, + .disable = _clk_disable,}, + { + .name = "uart_clk", + .id = 1, + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_UART2_OFFSET, + .disable = _clk_disable,}, + { + .name = "uart_clk", + .id = 2, + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_UART3_OFFSET, + .disable = _clk_disable,}, + { + .name = "uart_clk", + .id = 3, + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_UART4_OFFSET, + .disable = _clk_disable,}, + { + .name = "uart_clk", + .id = 4, + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_UART5_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk i2c_clk[] = { + { + .name = "i2c_clk", + .id = 0, + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_I2C1_OFFSET, + .disable = _clk_disable,}, + { + .name = "i2c_clk", + .id = 1, + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_I2C2_OFFSET, + .disable = _clk_disable,}, + { + .name = "i2c_clk", + .id = 2, + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_I2C3_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk owire_clk = { + .name = "owire_clk", + .parent = &perclk_clk, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_OWIRE_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk sdhc_clk[] = { + { + .name = "sdhc_clk", + .id = 0, + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_SD_MMC1_OFFSET, + .disable = _clk_disable,}, + { + .name = "sdhc_clk", + .id = 1, + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_SD_MMC2_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk ssi_clk[] = { + { + .name = "ssi_clk", + .parent = &serial_pll_clk, + .recalc = _clk_ssi1_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_SSI1_OFFSET, + .disable = _clk_disable,}, + { + .name = "ssi_clk", + .id = 1, + .parent = &serial_pll_clk, + .recalc = _clk_ssi2_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_SSI2_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk firi_clk = { + .name = "firi_clk", + .parent = &usb_pll_clk, + .round_rate = _clk_firi_round_rate, + .set_rate = _clk_firi_set_rate, + .recalc = _clk_firi_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_FIRI_OFFSET, + .disable = _clk_disable, +}; + +static struct clk ata_clk = { + .name = "ata_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_ATA_OFFSET, + .disable = _clk_disable, +}; + +static struct clk mbx_clk = { + .name = "mbx_clk", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_GACC_OFFSET, + .recalc = _clk_mbx_recalc, +}; + +static struct clk vpu_clk = { + .name = "vpu_clk", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_GACC_OFFSET, + .recalc = _clk_mbx_recalc, +}; + +static struct clk rtic_clk = { + .name = "rtic_clk", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_RTIC_OFFSET, + .disable = _clk_disable, +}; + +static struct clk rng_clk = { + .name = "rng_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_RNG_OFFSET, + .disable = _clk_disable, +}; + +static struct clk sdma_clk[] = { + { + .name = "sdma_ahb_clk", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_SDMA_OFFSET, + .disable = _clk_disable,}, + { + .name = "sdma_ipg_clk", + .parent = &ipg_clk,} +}; + +static struct clk mpeg4_clk = { + .name = "mpeg4_clk", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET, + .disable = _clk_disable, +}; + +static struct clk vl2cc_clk = { + .name = "vl2cc_clk", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET, + .disable = _clk_disable, +}; + +static struct clk mstick_clk[] = { + { + .name = "mstick_clk", + .id = 0, + .parent = &usb_pll_clk, + .recalc = _clk_mstick1_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_MEMSTICK1_OFFSET, + .disable = _clk_disable,}, + { + .name = "mstick_clk", + .id = 1, + .parent = &usb_pll_clk, + .recalc = _clk_mstick2_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_MEMSTICK2_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk iim_clk = { + .name = "iim_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_IIM_OFFSET, + .disable = _clk_disable, +}; + +static unsigned long _clk_cko1_round_rate(struct clk *clk, unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + if (clk->parent->rate % rate) + div++; + + if (div > 8) { + div = 16; + } else if (div > 4) { + div = 8; + } else if (div > 2) { + div = 4; + } + + return clk->parent->rate / div; +} + +static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + + div = clk->parent->rate / rate; + + if (div == 16) { + div = 4; + } else if (div == 8) { + div = 3; + } else if (div == 4) { + div = 2; + } else if (div == 2) { + div = 1; + } else if (div == 1) { + div = 0; + } else { + return -EINVAL; + } + + reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOUTDIV_MASK; + reg |= div << MXC_CCM_COSR_CLKOUTDIV_OFFSET; + __raw_writel(reg, MXC_CCM_COSR); + + return 0; +} + +static void _clk_cko1_recalc(struct clk *clk) +{ + u32 div; + + div = __raw_readl(MXC_CCM_COSR) & MXC_CCM_COSR_CLKOUTDIV_MASK >> + MXC_CCM_COSR_CLKOUTDIV_OFFSET; + + clk->rate = clk->parent->rate / (1 << div); +} + +static int _clk_cko1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOSEL_MASK; + + if (parent == &mcu_main_clk) { + reg |= 0 << MXC_CCM_COSR_CLKOSEL_OFFSET; + } else if (parent == &ipg_clk) { + reg |= 1 << MXC_CCM_COSR_CLKOSEL_OFFSET; + } else if (parent == &usb_pll_clk) { + reg |= 2 << MXC_CCM_COSR_CLKOSEL_OFFSET; + } else if (parent == mcu_main_clk.parent) { + reg |= 3 << MXC_CCM_COSR_CLKOSEL_OFFSET; + } else if (parent == &ahb_clk) { + reg |= 5 << MXC_CCM_COSR_CLKOSEL_OFFSET; + } else if (parent == &cpu_clk) { + reg |= 6 << MXC_CCM_COSR_CLKOSEL_OFFSET; + } else if (parent == &serial_pll_clk) { + reg |= 7 << MXC_CCM_COSR_CLKOSEL_OFFSET; + } else if (parent == &ckih_clk) { + reg |= 8 << MXC_CCM_COSR_CLKOSEL_OFFSET; + } else if (parent == &emi_clk) { + reg |= 9 << MXC_CCM_COSR_CLKOSEL_OFFSET; + } else if (parent == &ipu_clk) { + reg |= 0xA << MXC_CCM_COSR_CLKOSEL_OFFSET; + } else if (parent == &nfc_clk) { + reg |= 0xB << MXC_CCM_COSR_CLKOSEL_OFFSET; + } else if (parent == &uart_clk[0]) { + reg |= 0xC << MXC_CCM_COSR_CLKOSEL_OFFSET; + } else { + return -EINVAL; + } + + __raw_writel(reg, MXC_CCM_COSR); + + return 0; +} + +static int _clk_cko1_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_COSR) | MXC_CCM_COSR_CLKOEN; + __raw_writel(reg, MXC_CCM_COSR); + + return 0; +} + +static void _clk_cko1_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOEN; + __raw_writel(reg, MXC_CCM_COSR); +} + +static struct clk cko1_clk = { + .name = "cko1_clk", + .recalc = _clk_cko1_recalc, + .set_rate = _clk_cko1_set_rate, + .round_rate = _clk_cko1_round_rate, + .set_parent = _clk_cko1_set_parent, + .enable = _clk_cko1_enable, + .disable = _clk_cko1_disable, +}; + +static struct clk *mxc_clks[] = { + &ckih_clk, + &ckil_clk, + &mcu_pll_clk, + &usb_pll_clk, + &serial_pll_clk, + &mcu_main_clk, + &cpu_clk, + &ahb_clk, + &per_clk, + &perclk_clk, + &cko1_clk, + &emi_clk, + &cspi_clk[0], + &cspi_clk[1], + &cspi_clk[2], + &ipg_clk, + &gpt_clk, + &pwm_clk, + &wdog_clk, + &rtc_clk, + &epit_clk[0], + &epit_clk[1], + &nfc_clk, + &ipu_clk, + &kpp_clk, + &usb_clk[0], + &usb_clk[1], + &csi_clk, + &uart_clk[0], + &uart_clk[1], + &uart_clk[2], + &uart_clk[3], + &uart_clk[4], + &i2c_clk[0], + &i2c_clk[1], + &i2c_clk[2], + &owire_clk, + &sdhc_clk[0], + &sdhc_clk[1], + &ssi_clk[0], + &ssi_clk[1], + &firi_clk, + &ata_clk, + &rtic_clk, + &rng_clk, + &sdma_clk[0], + &sdma_clk[1], + &mstick_clk[0], + &mstick_clk[1], + &scc_clk, + &iim_clk, +}; + +static int cpu_curr_wp; +static struct cpu_wp *cpu_wp_tbl; + +static int cpu_wp_nr; + +extern void propagate_rate(struct clk *tclk); + +int __init mxc_clocks_init(void) +{ + u32 reg; + struct clk **clkp; + + for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) { + clk_register(*clkp); + } + + if (cpu_is_mx31()) { + clk_register(&mpeg4_clk); + clk_register(&mbx_clk); + } else { + clk_register(&vpu_clk); + clk_register(&vl2cc_clk); + } + + /* CCMR stby control */ + reg = __raw_readl(MXC_CCM_CCMR); + reg |= MXC_CCM_CCMR_VSTBY | MXC_CCM_CCMR_WAMO; + __raw_writel(reg, MXC_CCM_CCMR); + + /* Turn off all possible clocks */ + __raw_writel(MXC_CCM_CGR0_GPT_MASK, MXC_CCM_CGR0); + __raw_writel(0, MXC_CCM_CGR1); + + reg = MXC_CCM_CGR2_EMI_MASK | /*For MX32 */ + MXC_CCM_CGR2_IPMUX1_MASK | /*For MX32 */ + MXC_CCM_CGR2_IPMUX2_MASK | /*For MX32 */ + MXC_CCM_CGR2_MXCCLKENSEL_MASK | /*For MX32 */ + MXC_CCM_CGR2_CHIKCAMPEN_MASK | /*For MX32 */ + MXC_CCM_CGR2_OVRVPUBUSY_MASK | /*For MX32 */ + 0x3 << 27 | /*Bit 27 and 28 are not defined for MX32, + but still requires to be set */ + MXC_CCM_CGR2_APMSYSCLKSEL_MASK | MXC_CCM_CGR2_AOMENA_MASK; + __raw_writel(reg, MXC_CCM_CGR2); + + cko1_clk.disable(&cko1_clk); + usb_pll_clk.disable(&usb_pll_clk); + + pr_info("Clock input source is %ld\n", ckih_clk.rate); + + /* This will propagate to all children and init all the clock rates */ + propagate_rate(&ckih_clk); + + clk_enable(&gpt_clk); + clk_enable(&emi_clk); + clk_enable(&iim_clk); + + clk_enable(&serial_pll_clk); + + cpu_curr_wp = cpu_clk.rate / ahb_clk.rate - 1; + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + + /* Init serial PLL according */ + clk_set_rate(&serial_pll_clk, (cpu_wp_tbl[2].pll_rate)); + + if (cpu_is_mx31_rev(CHIP_REV_2_0) < 0) { + /* replace 399MHz wp with 266MHz one */ + memcpy(&cpu_wp_tbl[2], &cpu_wp_tbl[1], sizeof(cpu_wp_tbl[0])); + } + + return 0; +} + +/*! + * Function to get timer clock rate early in boot process before clock tree is + * initialized. + * + * @return Clock rate for timer + */ +unsigned long __init clk_early_get_timer_rate(void) +{ + /* Determine which high frequency clock source is coming in */ + ckih_clk.rate = board_get_ckih_rate(); + + mcu_main_clk.recalc(&mcu_main_clk); + ahb_clk.recalc(&ahb_clk); + ipg_clk.recalc(&ipg_clk); + return ipg_clk.rate; +} + +#define MXC_PMCR0_DVFS_MASK (MXC_CCM_PMCR0_DVSUP_MASK | \ + MXC_CCM_PMCR0_UDSC_MASK | \ + MXC_CCM_PMCR0_VSCNT_MASK | \ + MXC_CCM_PMCR0_DPVCR) + +#define MXC_PDR0_MAX_MCU_MASK (MXC_CCM_PDR0_MAX_PODF_MASK | \ + MXC_CCM_PDR0_MCU_PODF_MASK | \ + MXC_CCM_PDR0_HSP_PODF_MASK | \ + MXC_CCM_PDR0_IPG_PODF_MASK | \ + MXC_CCM_PDR0_NFC_PODF_MASK) + +static DEFINE_SPINLOCK(mxc_dfs_lock); + +static void dptcen_after_timeout(unsigned long ptr) +{ + u32 flags = 0; + + spin_lock_irqsave(&mxc_dfs_lock, flags); + + /* + * If DPTC is still active and core is running in Turbo mode + */ + if (dptcen_timer.data == cpu_wp_nr - 1) { + dptc_resume(DPTC_GP_ID); + } + spin_unlock_irqrestore(&mxc_dfs_lock, flags); +} + +/*! + * Setup cpu clock based on working point. + * @param wp cpu freq working point (0 is the slowest) + * @return 0 on success or error code on failure. + */ +static int cpu_clk_set_wp(int wp) +{ + struct cpu_wp *p; + u32 dvsup; + u32 pmcr0, pmcr1; + u32 pdr0; + u32 cgr2 = 0x80000000; + u32 vscnt = MXC_CCM_PMCR0_VSCNT_2; + u32 udsc = MXC_CCM_PMCR0_UDSC_DOWN; + u32 ipu_base = IO_ADDRESS(IPU_CTRL_BASE_ADDR); + u32 ipu_conf; + + if (wp >= cpu_wp_nr || wp < 0) { + printk(KERN_ERR "Wrong wp: %d for cpu_clk_set_wp\n", wp); + return -EINVAL; + } + if (wp == cpu_curr_wp) { + return 0; + } + + pmcr0 = __raw_readl(MXC_CCM_PMCR0); + pmcr1 = __raw_readl(MXC_CCM_PMCR1); + pdr0 = __raw_readl(MXC_CCM_PDR0); + + if (!(pmcr0 & MXC_CCM_PMCR0_UPDTEN)) { + return -EBUSY; + } + + if (wp > cpu_curr_wp) { + /* going faster */ + if (wp == (cpu_wp_nr - 1)) { + /* Only update vscnt going into Turbo */ + vscnt = MXC_CCM_PMCR0_VSCNT_8; + } + udsc = MXC_CCM_PMCR0_UDSC_UP; + } + + p = &cpu_wp_tbl[wp]; + + dvsup = (cpu_wp_nr - 1 - wp) << MXC_CCM_PMCR0_DVSUP_OFFSET; + + if ((mcu_main_clk.rate == 399000000) && (p->cpu_rate == 532000000)) { + cgr2 = __raw_readl(MXC_CCM_CGR2); + cgr2 &= 0x7fffffff; + vscnt = 0; + pmcr0 = (pmcr0 & ~MXC_PMCR0_DVFS_MASK) | dvsup | vscnt; + pr_debug("manul dvfs, dvsup = %x\n", dvsup); + __raw_writel(cgr2, MXC_CCM_CGR2); + __raw_writel(pmcr0, MXC_CCM_PMCR0); + udelay(100); + } + + if (mcu_main_clk.rate == p->pll_rate) { + /* No pll switching and relocking needed */ + pmcr0 |= MXC_CCM_PMCR0_DFSUP0_PDR; + } else { + /* pll switching and relocking needed */ + pmcr0 ^= MXC_CCM_PMCR0_DFSUP1; /* flip MSB bit */ + pmcr0 &= ~(MXC_CCM_PMCR0_DFSUP0); + } + + pmcr0 = (pmcr0 & ~MXC_PMCR0_DVFS_MASK) | dvsup | vscnt | udsc; + /* also enable DVFS hardware */ + pmcr0 |= MXC_CCM_PMCR0_DVFEN; + + __raw_writel(pmcr0, MXC_CCM_PMCR0); + + /* IPU and DI submodule must be on for PDR0 update to take effect */ + if (!clk_get_usecount(&ipu_clk)) + ipu_clk.enable(&ipu_clk); + ipu_conf = __raw_readl(ipu_base); + if (!(ipu_conf & 0x40)) + __raw_writel(ipu_conf | 0x40, ipu_base); + + __raw_writel((pdr0 & ~MXC_PDR0_MAX_MCU_MASK) | p->pdr0_reg, + MXC_CCM_PDR0); + + if ((pmcr0 & MXC_CCM_PMCR0_DFSUP0) == MXC_CCM_PMCR0_DFSUP0_PLL) { + /* prevent pll restart */ + pmcr1 |= 0x80; + __raw_writel(pmcr1, MXC_CCM_PMCR1); + /* PLL and post divider update */ + if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL) { + __raw_writel(p->pll_reg, MXC_CCM_SRPCTL); + serial_pll_clk.rate = p->pll_rate; + mcu_main_clk.parent = &serial_pll_clk; + } else { + __raw_writel(p->pll_reg, MXC_CCM_MPCTL); + mcu_pll_clk.rate = p->pll_rate; + mcu_main_clk.parent = &mcu_pll_clk; + } + } + + if ((cgr2 & 0x80000000) == 0x0) { + pr_debug("start auto dvfs\n"); + cgr2 |= 0x80000000; + __raw_writel(cgr2, MXC_CCM_CGR2); + } + + mcu_main_clk.rate = p->pll_rate; + cpu_clk.rate = p->cpu_rate; + + cpu_curr_wp = wp; + + /* Restore IPU_CONF setting */ + __raw_writel(ipu_conf, ipu_base); + if (!clk_get_usecount(&ipu_clk)) + ipu_clk.disable(&ipu_clk); + + if (wp == cpu_wp_nr - 1) { + init_timer(&dptcen_timer); + dptcen_timer.expires = jiffies + 2; + dptcen_timer.function = dptcen_after_timeout; + dptcen_timer.data = wp; + add_timer(&dptcen_timer); + } else { + dptc_suspend(DPTC_GP_ID); + } + + return 0; +} diff -urN linux-2.6.26/arch/arm/mach-mx3/cpu.c linux-2.6.26-lab126/arch/arm/mach-mx3/cpu.c --- linux-2.6.26/arch/arm/mach-mx3/cpu.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/cpu.c 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2001 Deep Blue Solutions Ltd. + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +/*! + * @file mach-mx3/cpu.c + * + * @brief This file contains the CPU initialization code. + * + * @ingroup MSL_MX31 + */ + +#include +#include +#include +#include +#include +#include + +/*! + * CPU initialization. It is called by fixup_mxc_board() + */ +void __init mxc_cpu_init(void) +{ + /* Setup Peripheral Port Remap register for AVIC */ + asm("ldr r0, =0xC0000015 \n\ + mcr p15, 0, r0, c15, c2, 4"); + if (!system_rev) { + mxc_set_system_rev(0x31, CHIP_REV_2_0); + } +} + +/*! + * Post CPU init code + * + * @return 0 always + */ +static int __init post_cpu_init(void) +{ + void *l2_base; + volatile unsigned long aips_reg; + + /* Initialize L2 cache */ + l2_base = ioremap(L2CC_BASE_ADDR, SZ_4K); + if (l2_base) { + l2x0_init(l2_base, 0x00030024, 0x00000000); + } + + /* + * S/W workaround: Clear the off platform peripheral modules + * Supervisor Protect bit for SDMA to access them. + */ + __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x40)); + __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x44)); + __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x48)); + __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x4C)); + aips_reg = __raw_readl(IO_ADDRESS(AIPS1_BASE_ADDR + 0x50)); + aips_reg &= 0x00FFFFFF; + __raw_writel(aips_reg, IO_ADDRESS(AIPS1_BASE_ADDR + 0x50)); + + __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x40)); + __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x44)); + __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x48)); + __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x4C)); + aips_reg = __raw_readl(IO_ADDRESS(AIPS2_BASE_ADDR + 0x50)); + aips_reg &= 0x00FFFFFF; + __raw_writel(aips_reg, IO_ADDRESS(AIPS2_BASE_ADDR + 0x50)); + + return 0; +} + +postcore_initcall(post_cpu_init); diff -urN linux-2.6.26/arch/arm/mach-mx3/crm_regs.h linux-2.6.26-lab126/arch/arm/mach-mx3/crm_regs.h --- linux-2.6.26/arch/arm/mach-mx3/crm_regs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/crm_regs.h 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,394 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ARCH_ARM_MACH_MX3_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MX3_CRM_REGS_H__ + +#define CKIH_CLK_FREQ 26000000 +#define CKIH_CLK_FREQ_27MHZ 27000000 +#define CKIL_CLK_FREQ 32768 + +#define MXC_CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) + +/* Register addresses */ +#define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00) +#define MXC_CCM_PDR0 (MXC_CCM_BASE + 0x04) +#define MXC_CCM_PDR1 (MXC_CCM_BASE + 0x08) +#define MXC_CCM_RCSR (MXC_CCM_BASE + 0x0C) +#define MXC_CCM_MPCTL (MXC_CCM_BASE + 0x10) +#define MXC_CCM_UPCTL (MXC_CCM_BASE + 0x14) +#define MXC_CCM_SRPCTL (MXC_CCM_BASE + 0x18) +#define MXC_CCM_COSR (MXC_CCM_BASE + 0x1C) +#define MXC_CCM_CGR0 (MXC_CCM_BASE + 0x20) +#define MXC_CCM_CGR1 (MXC_CCM_BASE + 0x24) +#define MXC_CCM_CGR2 (MXC_CCM_BASE + 0x28) +#define MXC_CCM_WIMR (MXC_CCM_BASE + 0x2C) +#define MXC_CCM_LDC (MXC_CCM_BASE + 0x30) +#define MXC_CCM_DCVR0 (MXC_CCM_BASE + 0x34) +#define MXC_CCM_DCVR1 (MXC_CCM_BASE + 0x38) +#define MXC_CCM_DCVR2 (MXC_CCM_BASE + 0x3C) +#define MXC_CCM_DCVR3 (MXC_CCM_BASE + 0x40) +#define MXC_CCM_LTR0 (MXC_CCM_BASE + 0x44) +#define MXC_CCM_LTR1 (MXC_CCM_BASE + 0x48) +#define MXC_CCM_LTR2 (MXC_CCM_BASE + 0x4C) +#define MXC_CCM_LTR3 (MXC_CCM_BASE + 0x50) +#define MXC_CCM_LTBR0 (MXC_CCM_BASE + 0x54) +#define MXC_CCM_LTBR1 (MXC_CCM_BASE + 0x58) +#define MXC_CCM_PMCR0 (MXC_CCM_BASE + 0x5C) +#define MXC_CCM_PMCR1 (MXC_CCM_BASE + 0x60) +#define MXC_CCM_PDR2 (MXC_CCM_BASE + 0x64) + +/* Register bit definitions */ +#define MXC_CCM_CCMR_VSTBY (1 << 28) +#define MXC_CCM_CCMR_WBEN (1 << 27) +#define MXC_CCM_CCMR_CSCS (1 << 25) +#define MXC_CCM_CCMR_PERCS (1 << 24) +#define MXC_CCM_CCMR_SSI1S_OFFSET 18 +#define MXC_CCM_CCMR_SSI1S_MASK (0x3 << 18) +#define MXC_CCM_CCMR_SSI2S_OFFSET 21 +#define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21) +#define MXC_CCM_CCMR_LPM_OFFSET 14 +#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) +#define MXC_CCM_CCMR_FIRS_OFFSET 11 +#define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11) +#define MXC_CCM_CCMR_WAMO (1 << 10) +#define MXC_CCM_CCMR_UPE (1 << 9) +#define MXC_CCM_CCMR_SPE (1 << 8) +#define MXC_CCM_CCMR_MDS (1 << 7) +#define MXC_CCM_CCMR_SBYCS (1 << 4) +#define MXC_CCM_CCMR_MPE (1 << 3) +#define MXC_CCM_CCMR_PRCS_OFFSET 1 +#define MXC_CCM_CCMR_PRCS_MASK (0x3 << 1) + +#define MXC_CCM_PDR0_CSI_PODF_OFFSET 26 +#define MXC_CCM_PDR0_CSI_PODF_MASK (0x3F << 26) +#define MXC_CCM_PDR0_CSI_PRDF_OFFSET 23 +#define MXC_CCM_PDR0_CSI_PRDF_MASK (0x7 << 23) +#define MXC_CCM_PDR0_PER_PODF_OFFSET 16 +#define MXC_CCM_PDR0_PER_PODF_MASK (0x1F << 16) +#define MXC_CCM_PDR0_HSP_PODF_OFFSET 11 +#define MXC_CCM_PDR0_HSP_PODF_MASK (0x7 << 11) +#define MXC_CCM_PDR0_NFC_PODF_OFFSET 8 +#define MXC_CCM_PDR0_NFC_PODF_MASK (0x7 << 8) +#define MXC_CCM_PDR0_IPG_PODF_OFFSET 6 +#define MXC_CCM_PDR0_IPG_PODF_MASK (0x3 << 6) +#define MXC_CCM_PDR0_MAX_PODF_OFFSET 3 +#define MXC_CCM_PDR0_MAX_PODF_MASK (0x7 << 3) +#define MXC_CCM_PDR0_MCU_PODF_OFFSET 0 +#define MXC_CCM_PDR0_MCU_PODF_MASK 0x7 + +#define MXC_CCM_PDR0_HSP_DIV_1 (0x0 << 11) +#define MXC_CCM_PDR0_HSP_DIV_2 (0x1 << 11) +#define MXC_CCM_PDR0_HSP_DIV_3 (0x2 << 11) +#define MXC_CCM_PDR0_HSP_DIV_4 (0x3 << 11) +#define MXC_CCM_PDR0_HSP_DIV_5 (0x4 << 11) +#define MXC_CCM_PDR0_HSP_DIV_6 (0x5 << 11) +#define MXC_CCM_PDR0_HSP_DIV_7 (0x6 << 11) +#define MXC_CCM_PDR0_HSP_DIV_8 (0x7 << 11) + +#define MXC_CCM_PDR0_IPG_DIV_1 (0x0 << 6) +#define MXC_CCM_PDR0_IPG_DIV_2 (0x1 << 6) +#define MXC_CCM_PDR0_IPG_DIV_3 (0x2 << 6) +#define MXC_CCM_PDR0_IPG_DIV_4 (0x3 << 6) + +#define MXC_CCM_PDR0_MAX_DIV_1 (0x0 << 3) +#define MXC_CCM_PDR0_MAX_DIV_2 (0x1 << 3) +#define MXC_CCM_PDR0_MAX_DIV_3 (0x2 << 3) +#define MXC_CCM_PDR0_MAX_DIV_4 (0x3 << 3) +#define MXC_CCM_PDR0_MAX_DIV_5 (0x4 << 3) +#define MXC_CCM_PDR0_MAX_DIV_6 (0x5 << 3) +#define MXC_CCM_PDR0_MAX_DIV_7 (0x6 << 3) +#define MXC_CCM_PDR0_MAX_DIV_8 (0x7 << 3) + +#define MXC_CCM_PDR0_NFC_DIV_1 (0x0 << 8) +#define MXC_CCM_PDR0_NFC_DIV_2 (0x1 << 8) +#define MXC_CCM_PDR0_NFC_DIV_3 (0x2 << 8) +#define MXC_CCM_PDR0_NFC_DIV_4 (0x3 << 8) +#define MXC_CCM_PDR0_NFC_DIV_5 (0x4 << 8) +#define MXC_CCM_PDR0_NFC_DIV_6 (0x5 << 8) +#define MXC_CCM_PDR0_NFC_DIV_7 (0x6 << 8) +#define MXC_CCM_PDR0_NFC_DIV_8 (0x7 << 8) + +#define MXC_CCM_PDR0_MCU_DIV_1 0x0 +#define MXC_CCM_PDR0_MCU_DIV_2 0x1 +#define MXC_CCM_PDR0_MCU_DIV_3 0x2 +#define MXC_CCM_PDR0_MCU_DIV_4 0x3 +#define MXC_CCM_PDR0_MCU_DIV_5 0x4 +#define MXC_CCM_PDR0_MCU_DIV_6 0x5 +#define MXC_CCM_PDR0_MCU_DIV_7 0x6 +#define MXC_CCM_PDR0_MCU_DIV_8 0x7 + +#define MXC_CCM_PDR1_USB_PRDF_OFFSET 30 +#define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30) +#define MXC_CCM_PDR1_USB_PODF_OFFSET 27 +#define MXC_CCM_PDR1_USB_PODF_MASK (0x7 << 27) +#define MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET 24 +#define MXC_CCM_PDR1_FIRI_PRE_PODF_MASK (0x7 << 24) +#define MXC_CCM_PDR1_FIRI_PODF_OFFSET 18 +#define MXC_CCM_PDR1_FIRI_PODF_MASK (0x3F << 18) +#define MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET 15 +#define MXC_CCM_PDR1_SSI2_PRE_PODF_MASK (0x7 << 15) +#define MXC_CCM_PDR1_SSI2_PODF_OFFSET 9 +#define MXC_CCM_PDR1_SSI2_PODF_MASK (0x3F << 9) +#define MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET 6 +#define MXC_CCM_PDR1_SSI1_PRE_PODF_MASK (0x7 << 6) +#define MXC_CCM_PDR1_SSI1_PODF_OFFSET 0 +#define MXC_CCM_PDR1_SSI1_PODF_MASK 0x3F + +/* Bit definitions for RCSR */ +#define MXC_CCM_RCSR_NF16B 0x80000000 + +/* Bit definitions for both MCU, USB and SR PLL control registers */ +#define MXC_CCM_PCTL_BRM 0x80000000 +#define MXC_CCM_PCTL_PD_OFFSET 26 +#define MXC_CCM_PCTL_PD_MASK (0xF << 26) +#define MXC_CCM_PCTL_MFD_OFFSET 16 +#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) +#define MXC_CCM_PCTL_MFI_OFFSET 10 +#define MXC_CCM_PCTL_MFI_MASK (0xF << 10) +#define MXC_CCM_PCTL_MFN_OFFSET 0 +#define MXC_CCM_PCTL_MFN_MASK 0x3FF + +#define MXC_CCM_CGR0_SD_MMC1_OFFSET 0 +#define MXC_CCM_CGR0_SD_MMC1_MASK (0x3 << 0) +#define MXC_CCM_CGR0_SD_MMC2_OFFSET 2 +#define MXC_CCM_CGR0_SD_MMC2_MASK (0x3 << 2) +#define MXC_CCM_CGR0_GPT_OFFSET 4 +#define MXC_CCM_CGR0_GPT_MASK (0x3 << 4) +#define MXC_CCM_CGR0_EPIT1_OFFSET 6 +#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 6) +#define MXC_CCM_CGR0_EPIT2_OFFSET 8 +#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 8) +#define MXC_CCM_CGR0_IIM_OFFSET 10 +#define MXC_CCM_CGR0_IIM_MASK (0x3 << 10) +#define MXC_CCM_CGR0_ATA_OFFSET 12 +#define MXC_CCM_CGR0_ATA_MASK (0x3 << 12) +#define MXC_CCM_CGR0_SDMA_OFFSET 14 +#define MXC_CCM_CGR0_SDMA_MASK (0x3 << 14) +#define MXC_CCM_CGR0_CSPI3_OFFSET 16 +#define MXC_CCM_CGR0_CSPI3_MASK (0x3 << 16) +#define MXC_CCM_CGR0_RNG_OFFSET 18 +#define MXC_CCM_CGR0_RNG_MASK (0x3 << 18) +#define MXC_CCM_CGR0_UART1_OFFSET 20 +#define MXC_CCM_CGR0_UART1_MASK (0x3 << 20) +#define MXC_CCM_CGR0_UART2_OFFSET 22 +#define MXC_CCM_CGR0_UART2_MASK (0x3 << 22) +#define MXC_CCM_CGR0_SSI1_OFFSET 24 +#define MXC_CCM_CGR0_SSI1_MASK (0x3 << 24) +#define MXC_CCM_CGR0_I2C1_OFFSET 26 +#define MXC_CCM_CGR0_I2C1_MASK (0x3 << 26) +#define MXC_CCM_CGR0_I2C2_OFFSET 28 +#define MXC_CCM_CGR0_I2C2_MASK (0x3 << 28) +#define MXC_CCM_CGR0_I2C3_OFFSET 30 +#define MXC_CCM_CGR0_I2C3_MASK (0x3 << 30) + +#define MXC_CCM_CGR1_HANTRO_OFFSET 0 +#define MXC_CCM_CGR1_HANTRO_MASK (0x3 << 0) +#define MXC_CCM_CGR1_MEMSTICK1_OFFSET 2 +#define MXC_CCM_CGR1_MEMSTICK1_MASK (0x3 << 2) +#define MXC_CCM_CGR1_MEMSTICK2_OFFSET 4 +#define MXC_CCM_CGR1_MEMSTICK2_MASK (0x3 << 4) +#define MXC_CCM_CGR1_CSI_OFFSET 6 +#define MXC_CCM_CGR1_CSI_MASK (0x3 << 6) +#define MXC_CCM_CGR1_RTC_OFFSET 8 +#define MXC_CCM_CGR1_RTC_MASK (0x3 << 8) +#define MXC_CCM_CGR1_WDOG_OFFSET 10 +#define MXC_CCM_CGR1_WDOG_MASK (0x3 << 10) +#define MXC_CCM_CGR1_PWM_OFFSET 12 +#define MXC_CCM_CGR1_PWM_MASK (0x3 << 12) +#define MXC_CCM_CGR1_SIM_OFFSET 14 +#define MXC_CCM_CGR1_SIM_MASK (0x3 << 14) +#define MXC_CCM_CGR1_ECT_OFFSET 16 +#define MXC_CCM_CGR1_ECT_MASK (0x3 << 16) +#define MXC_CCM_CGR1_USBOTG_OFFSET 18 +#define MXC_CCM_CGR1_USBOTG_MASK (0x3 << 18) +#define MXC_CCM_CGR1_KPP_OFFSET 20 +#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) +#define MXC_CCM_CGR1_IPU_OFFSET 22 +#define MXC_CCM_CGR1_IPU_MASK (0x3 << 22) +#define MXC_CCM_CGR1_UART3_OFFSET 24 +#define MXC_CCM_CGR1_UART3_MASK (0x3 << 24) +#define MXC_CCM_CGR1_UART4_OFFSET 26 +#define MXC_CCM_CGR1_UART4_MASK (0x3 << 26) +#define MXC_CCM_CGR1_UART5_OFFSET 28 +#define MXC_CCM_CGR1_UART5_MASK (0x3 << 28) +#define MXC_CCM_CGR1_OWIRE_OFFSET 30 +#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 30) + +#define MXC_CCM_CGR2_SSI2_OFFSET 0 +#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 0) +#define MXC_CCM_CGR2_CSPI1_OFFSET 2 +#define MXC_CCM_CGR2_CSPI1_MASK (0x3 << 2) +#define MXC_CCM_CGR2_CSPI2_OFFSET 4 +#define MXC_CCM_CGR2_CSPI2_MASK (0x3 << 4) +#define MXC_CCM_CGR2_GACC_OFFSET 6 +#define MXC_CCM_CGR2_GACC_MASK (0x3 << 6) +#define MXC_CCM_CGR2_EMI_OFFSET 8 +#define MXC_CCM_CGR2_EMI_MASK (0x3 << 8) +#define MXC_CCM_CGR2_RTIC_OFFSET 10 +#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 10) +#define MXC_CCM_CGR2_FIRI_OFFSET 12 +#define MXC_CCM_CGR2_FIRI_MASK (0x3 << 12) +#define MXC_CCM_CGR2_IPMUX1_OFFSET 14 +#define MXC_CCM_CGR2_IPMUX1_MASK (0x3 << 14) +#define MXC_CCM_CGR2_IPMUX2_OFFSET 16 +#define MXC_CCM_CGR2_IPMUX2_MASK (0x3 << 16) + +/* These new CGR2 bits are added in MX32 */ +#define MXC_CCM_CGR2_APMSYSCLKSEL_OFFSET 18 +#define MXC_CCM_CGR2_APMSYSCLKSEL_MASK (0x3 << 18) +#define MXC_CCM_CGR2_APMSSICLKSEL_OFFSET 20 +#define MXC_CCM_CGR2_APMSSICLKSEL_MASK (0x3 << 20) +#define MXC_CCM_CGR2_APMPERCLKSEL_OFFSET 22 +#define MXC_CCM_CGR2_APMPERCLKSEL_MASK (0x3 << 22) +#define MXC_CCM_CGR2_MXCCLKENSEL_OFFSET 24 +#define MXC_CCM_CGR2_MXCCLKENSEL_MASK (0x1 << 24) +#define MXC_CCM_CGR2_CHIKCAMPEN_OFFSET 25 +#define MXC_CCM_CGR2_CHIKCAMPEN_MASK (0x1 << 25) +#define MXC_CCM_CGR2_OVRVPUBUSY_OFFSET 26 +#define MXC_CCM_CGR2_OVRVPUBUSY_MASK (0x1 << 26) +#define MXC_CCM_CGR2_APMENA_OFFSET 30 +#define MXC_CCM_CGR2_AOMENA_MASK (0x1 << 30) + +/* + * LTR0 register offsets + */ +#define MXC_CCM_LTR0_DIV3CK_OFFSET 1 +#define MXC_CCM_LTR0_DIV3CK_MASK (0x3 << 1) +#define MXC_CCM_LTR0_DNTHR_OFFSET 16 +#define MXC_CCM_LTR0_DNTHR_MASK (0x3F << 16) +#define MXC_CCM_LTR0_UPTHR_OFFSET 22 +#define MXC_CCM_LTR0_UPTHR_MASK (0x3F << 22) + +/* + * LTR1 register offsets + */ +#define MXC_CCM_LTR1_PNCTHR_OFFSET 0 +#define MXC_CCM_LTR1_PNCTHR_MASK 0x3F +#define MXC_CCM_LTR1_UPCNT_OFFSET 6 +#define MXC_CCM_LTR1_UPCNT_MASK (0xFF << 6) +#define MXC_CCM_LTR1_DNCNT_OFFSET 14 +#define MXC_CCM_LTR1_DNCNT_MASK (0xFF << 14) +#define MXC_CCM_LTR1_LTBRSR_MASK 0x400000 +#define MXC_CCM_LTR1_LTBRSR_OFFSET 22 +#define MXC_CCM_LTR1_LTBRSR 0x400000 +#define MXC_CCM_LTR1_LTBRSH 0x800000 + +/* + * LTR2 bit definitions. x ranges from 0 for WSW9 to 6 for WSW15 + */ +#define MXC_CCM_LTR2_WSW_OFFSET(x) (11 + (x) * 3) +#define MXC_CCM_LTR2_WSW_MASK(x) (0x7 << MXC_CCM_LTR2_WSW_OFFSET((x))) +#define MXC_CCM_LTR2_EMAC_OFFSET 0 +#define MXC_CCM_LTR2_EMAC_MASK 0x1FF + +/* + * LTR3 bit definitions. x ranges from 0 for WSW0 to 8 for WSW8 + */ +#define MXC_CCM_LTR3_WSW_OFFSET(x) (5 + (x) * 3) +#define MXC_CCM_LTR3_WSW_MASK(x) (0x7 << MXC_CCM_LTR3_WSW_OFFSET((x))) + +#define MXC_CCM_PMCR0_DFSUP1 0x80000000 +#define MXC_CCM_PMCR0_DFSUP1_SPLL (0 << 31) +#define MXC_CCM_PMCR0_DFSUP1_MPLL (1 << 31) +#define MXC_CCM_PMCR0_DFSUP0 0x40000000 +#define MXC_CCM_PMCR0_DFSUP0_PLL (0 << 30) +#define MXC_CCM_PMCR0_DFSUP0_PDR (1 << 30) +#define MXC_CCM_PMCR0_DFSUP_MASK (0x3 << 30) + +#define DVSUP_TURBO 0 +#define DVSUP_HIGH 1 +#define DVSUP_MEDIUM 2 +#define DVSUP_LOW 3 +#define MXC_CCM_PMCR0_DVSUP_TURBO (DVSUP_TURBO << 28) +#define MXC_CCM_PMCR0_DVSUP_HIGH (DVSUP_HIGH << 28) +#define MXC_CCM_PMCR0_DVSUP_MEDIUM (DVSUP_MEDIUM << 28) +#define MXC_CCM_PMCR0_DVSUP_LOW (DVSUP_LOW << 28) +#define MXC_CCM_PMCR0_DVSUP_OFFSET 28 +#define MXC_CCM_PMCR0_DVSUP_MASK (0x3 << 28) +#define MXC_CCM_PMCR0_UDSC 0x08000000 +#define MXC_CCM_PMCR0_UDSC_MASK (1 << 27) +#define MXC_CCM_PMCR0_UDSC_UP (1 << 27) +#define MXC_CCM_PMCR0_UDSC_DOWN (0 << 27) + +#define MXC_CCM_PMCR0_VSCNT_1 (0x0 << 24) +#define MXC_CCM_PMCR0_VSCNT_2 (0x1 << 24) +#define MXC_CCM_PMCR0_VSCNT_3 (0x2 << 24) +#define MXC_CCM_PMCR0_VSCNT_4 (0x3 << 24) +#define MXC_CCM_PMCR0_VSCNT_5 (0x4 << 24) +#define MXC_CCM_PMCR0_VSCNT_6 (0x5 << 24) +#define MXC_CCM_PMCR0_VSCNT_7 (0x6 << 24) +#define MXC_CCM_PMCR0_VSCNT_8 (0x7 << 24) +#define MXC_CCM_PMCR0_VSCNT_OFFSET 24 +#define MXC_CCM_PMCR0_VSCNT_MASK (0x7 << 24) +#define MXC_CCM_PMCR0_DVFEV 0x00800000 +#define MXC_CCM_PMCR0_DVFIS 0x00400000 +#define MXC_CCM_PMCR0_LBMI 0x00200000 +#define MXC_CCM_PMCR0_LBFL 0x00100000 +#define MXC_CCM_PMCR0_LBCF_4 (0x0 << 18) +#define MXC_CCM_PMCR0_LBCF_8 (0x1 << 18) +#define MXC_CCM_PMCR0_LBCF_12 (0x2 << 18) +#define MXC_CCM_PMCR0_LBCF_16 (0x3 << 18) +#define MXC_CCM_PMCR0_LBCF_OFFSET 18 +#define MXC_CCM_PMCR0_LBCF_MASK (0x3 << 18) +#define MXC_CCM_PMCR0_PTVIS 0x00020000 +#define MXC_CCM_PMCR0_UPDTEN 0x00010000 +#define MXC_CCM_PMCR0_UPDTEN_MASK (0x1 << 16) +#define MXC_CCM_PMCR0_FSVAIM 0x00008000 +#define MXC_CCM_PMCR0_FSVAI_OFFSET 13 +#define MXC_CCM_PMCR0_FSVAI_MASK (0x3 << 13) +#define MXC_CCM_PMCR0_DPVCR 0x00001000 +#define MXC_CCM_PMCR0_DPVV 0x00000800 +#define MXC_CCM_PMCR0_WFIM 0x00000400 +#define MXC_CCM_PMCR0_DRCE3 0x00000200 +#define MXC_CCM_PMCR0_DRCE2 0x00000100 +#define MXC_CCM_PMCR0_DRCE1 0x00000080 +#define MXC_CCM_PMCR0_DRCE0 0x00000040 +#define MXC_CCM_PMCR0_DCR 0x00000020 +#define MXC_CCM_PMCR0_DVFEN 0x00000010 +#define MXC_CCM_PMCR0_PTVAIM 0x00000008 +#define MXC_CCM_PMCR0_PTVAI_OFFSET 1 +#define MXC_CCM_PMCR0_PTVAI_MASK (0x3 << 1) +#define MXC_CCM_PMCR0_DPTEN 0x00000001 + +#define MXC_CCM_PMCR1_DVGP_OFFSET 0 +#define MXC_CCM_PMCR1_DVGP_MASK (0xF) + +#define MXC_CCM_PMCR1_PLLRDIS (0x1 << 7) +#define MXC_CCM_PMCR1_EMIRQ_EN (0x1 << 8) + +#define MXC_CCM_DCVR_ULV_MASK (0x3FF << 22) +#define MXC_CCM_DCVR_ULV_OFFSET 22 +#define MXC_CCM_DCVR_LLV_MASK (0x3FF << 12) +#define MXC_CCM_DCVR_LLV_OFFSET 12 +#define MXC_CCM_DCVR_ELV_MASK (0x3FF << 2) +#define MXC_CCM_DCVR_ELV_OFFSET 2 + +#define MXC_CCM_PDR2_MST2_PDF_MASK (0x3F << 7) +#define MXC_CCM_PDR2_MST2_PDF_OFFSET 7 +#define MXC_CCM_PDR2_MST1_PDF_MASK 0x3F +#define MXC_CCM_PDR2_MST1_PDF_OFFSET 0 + +#define MXC_CCM_COSR_CLKOSEL_MASK 0x0F +#define MXC_CCM_COSR_CLKOSEL_OFFSET 0 +#define MXC_CCM_COSR_CLKOUTDIV_MASK (0x07 << 6) +#define MXC_CCM_COSR_CLKOUTDIV_OFFSET 6 +#define MXC_CCM_COSR_CLKOEN (1 << 9) + +/* + * PMCR0 register offsets + */ +#define MXC_CCM_PMCR0_LBFL_OFFSET 20 +#define MXC_CCM_PMCR0_DFSUP0_OFFSET 30 +#define MXC_CCM_PMCR0_DFSUP1_OFFSET 31 + +#endif /* __ARCH_ARM_MACH_MX3_CRM_REGS_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx3/devices.c linux-2.6.26-lab126/arch/arm/mach-mx3/devices.c --- linux-2.6.26/arch/arm/mach-mx3/devices.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/devices.c 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,858 @@ +/* + * Author: MontaVista Software, Inc. + * + * + * Based on the OMAP devices.c + * + * 2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include +#include "iomux.h" +#include "crm_regs.h" +#include +#include "sdma_script_code.h" +#include "sdma_script_code_pass2.h" + +extern struct dptc_wp dptc_wp_allfreq_26ckih[DPTC_WP_SUPPORTED]; +extern struct dptc_wp dptc_wp_allfreq_26ckih_TO_2_0[DPTC_WP_SUPPORTED]; +extern struct dptc_wp dptc_wp_allfreq_27ckih_TO_2_0[DPTC_WP_SUPPORTED]; +/* + * Clock structures + */ +static struct clk *ckih_clk; + +void mxc_sdma_get_script_info(sdma_script_start_addrs * sdma_script_addr) +{ + if (cpu_is_mx31_rev(CHIP_REV_1_0) == 1) { + sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR; + sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1; + sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1; + sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR; + sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR; + sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1; + sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_start_addr = + (unsigned short *)sdma_code; + sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr = + uartsh_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE; + sdma_script_addr->mxc_sdma_ram_code_start_addr = + RAM_CODE_START_ADDR; + sdma_script_addr->mxc_sdma_dptc_dvfs_addr = dptc_dvfs_ADDR; + sdma_script_addr->mxc_sdma_firi_2_mcu_addr = firi_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_firi_2_per_addr = -1; + sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = mshc_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_per_2_app_addr = -1; + sdma_script_addr->mxc_sdma_per_2_firi_addr = -1; + sdma_script_addr->mxc_sdma_per_2_shp_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_ata_addr = mcu_2_ata_ADDR; + sdma_script_addr->mxc_sdma_mcu_2_firi_addr = mcu_2_firi_ADDR; + sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = mcu_2_mshc_ADDR; + sdma_script_addr->mxc_sdma_ata_2_mcu_addr = ata_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_uartsh_2_per_addr = -1; + sdma_script_addr->mxc_sdma_shp_2_per_addr = -1; + sdma_script_addr->mxc_sdma_uart_2_per_addr = -1; + sdma_script_addr->mxc_sdma_app_2_per_addr = -1; + } else { + sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR_2; + sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR_2; + sdma_script_addr->mxc_sdma_ap_2_ap_fixed_addr = + ap_2_ap_fixed_addr_ADDR_2; + sdma_script_addr->mxc_sdma_ap_2_bp_addr = ap_2_bp_ADDR_2; + sdma_script_addr->mxc_sdma_ap_2_ap_fixed_addr = + ap_2_ap_fixed_addr_ADDR_2; + sdma_script_addr->mxc_sdma_bp_2_ap_addr = bp_2_ap_ADDR_2; + sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR_2; + sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR_2; + sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1; + sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR_2; + sdma_script_addr->mxc_sdma_start_addr = + (unsigned short *)sdma_code_2; + sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr = + uartsh_2_mcu_ADDR_2; + sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR_2; + sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE_2; + sdma_script_addr->mxc_sdma_ram_code_start_addr = + RAM_CODE_START_ADDR_2; + sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1; + sdma_script_addr->mxc_sdma_firi_2_mcu_addr = firi_2_mcu_ADDR_2; + sdma_script_addr->mxc_sdma_firi_2_per_addr = -1; + sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = mshc_2_mcu_ADDR_2; + sdma_script_addr->mxc_sdma_per_2_app_addr = per_2_app_ADDR_2; + sdma_script_addr->mxc_sdma_per_2_firi_addr = -1; + sdma_script_addr->mxc_sdma_per_2_shp_addr = per_2_shp_ADDR_2; + sdma_script_addr->mxc_sdma_mcu_2_ata_addr = mcu_2_ata_ADDR_2; + sdma_script_addr->mxc_sdma_mcu_2_firi_addr = mcu_2_firi_ADDR_2; + sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = mcu_2_mshc_ADDR_2; + sdma_script_addr->mxc_sdma_ata_2_mcu_addr = ata_2_mcu_ADDR_2; + sdma_script_addr->mxc_sdma_uartsh_2_per_addr = -1; + sdma_script_addr->mxc_sdma_shp_2_per_addr = shp_2_per_ADDR_2; + sdma_script_addr->mxc_sdma_uart_2_per_addr = -1; + sdma_script_addr->mxc_sdma_app_2_per_addr = app_2_per_ADDR_2; + } +} + +static void mxc_nop_release(struct device *dev) +{ + /* Nothing */ +} + +#if defined(CONFIG_W1_MASTER_MXC) || defined(CONFIG_W1_MASTER_MXC_MODULE) +static struct mxc_w1_config mxc_w1_data = { + .search_rom_accelerator = 0, +}; + +static struct platform_device mxc_w1_devices = { + .name = "mxc_w1", + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_w1_data, + }, + .id = 0 +}; + +static void mxc_init_owire(void) +{ + (void)platform_device_register(&mxc_w1_devices); +} +#else +static inline void mxc_init_owire(void) +{ +} +#endif + +#if defined(CONFIG_RTC_MXC) || defined(CONFIG_RTC_MXC_MODULE) +static struct resource rtc_resources[] = { + { + .start = RTC_BASE_ADDR, + .end = RTC_BASE_ADDR + 0x30, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_RTC, + .flags = IORESOURCE_IRQ, + }, +}; +static struct platform_device mxc_rtc_device = { + .name = "mxc_rtc", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, +}; +static void mxc_init_rtc(void) +{ + (void)platform_device_register(&mxc_rtc_device); +} +#else +static inline void mxc_init_rtc(void) +{ +} +#endif + +#if defined(CONFIG_MXC_WATCHDOG) || defined(CONFIG_MXC_WATCHDOG_MODULE) + +static struct resource wdt_resources[] = { + { + .start = WDOG1_BASE_ADDR, + .end = WDOG1_BASE_ADDR + 0x30, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mxc_wdt_device = { + .name = "mxc_wdt", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(wdt_resources), + .resource = wdt_resources, +}; + +static void mxc_init_wdt(void) +{ + (void)platform_device_register(&mxc_wdt_device); +} +#else +static inline void mxc_init_wdt(void) +{ +} +#endif + +#if defined(CONFIG_MXC_IPU) || defined(CONFIG_MXC_IPU_MODULE) +static struct mxc_ipu_config mxc_ipu_data = { + .rev = 1, +}; + +static struct resource ipu_resources[] = { + { + .start = IPU_CTRL_BASE_ADDR, + .end = IPU_CTRL_BASE_ADDR + SZ_4K, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_IPU_SYN, + .flags = IORESOURCE_IRQ, + }, + { + .start = MXC_INT_IPU_ERR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxc_ipu_device = { + .name = "mxc_ipu", + .id = -1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_ipu_data, + }, + .num_resources = ARRAY_SIZE(ipu_resources), + .resource = ipu_resources, +}; + +static void mxc_init_ipu(void) +{ + platform_device_register(&mxc_ipu_device); +} +#else +static inline void mxc_init_ipu(void) +{ +} +#endif + +#if defined(CONFIG_SND_MXC_PMIC) || defined(CONFIG_SND_MXC_PMIC_MODULE) +static struct mxc_audio_platform_data mxc_audio_data; + +static struct platform_device mxc_alsa_device = { + .name = "mxc_alsa", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_audio_data, + }, + +}; + +static void mxc_init_audio(void) +{ + struct clk *pll_clk; + pll_clk = clk_get(NULL, "usb_pll"); + mxc_audio_data.ssi_clk[0] = clk_get(NULL, "ssi_clk.0"); + clk_set_parent(mxc_audio_data.ssi_clk[0], pll_clk); + clk_put(mxc_audio_data.ssi_clk[0]); + if (machine_is_mx31_3ds()) { + mxc_audio_data.ssi_num = 1; + } else { + mxc_audio_data.ssi_num = 2; + mxc_audio_data.ssi_clk[1] = clk_get(NULL, "ssi_clk.1"); + clk_set_parent(mxc_audio_data.ssi_clk[1], pll_clk); + clk_put(mxc_audio_data.ssi_clk[1]); + } + clk_put(pll_clk); + mxc_audio_data.src_port = 0; + platform_device_register(&mxc_alsa_device); +} +#else + +static void mxc_init_audio(void) +{ +} + +#endif + +#if defined(CONFIG_MXC_SSI) || defined(CONFIG_MXC_SSI_MODULE) +/*! + * Resource definition for the SSI + */ +static struct resource mxcssi2_resources[] = { + [0] = { + .start = SSI2_BASE_ADDR, + .end = SSI2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource mxcssi1_resources[] = { + [0] = { + .start = SSI1_BASE_ADDR, + .end = SSI1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +/*! Device Definition for MXC SSI */ +static struct platform_device mxc_ssi1_device = { + .name = "mxc_ssi", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_audio_data, + }, + .num_resources = ARRAY_SIZE(mxcssi1_resources), + .resource = mxcssi1_resources, +}; + +static struct platform_device mxc_ssi2_device = { + .name = "mxc_ssi", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_audio_data, + }, + .num_resources = ARRAY_SIZE(mxcssi2_resources), + .resource = mxcssi2_resources, +}; + +static void mxc_init_ssi(void) +{ + platform_device_register(&mxc_ssi1_device); + platform_device_register(&mxc_ssi2_device); +} +#else + +static void mxc_init_ssi(void) +{ +} +#endif + +/*! + * This is platform device structure for adding SCC + */ +#if defined(CONFIG_MXC_SECURITY_SCC) || defined(CONFIG_MXC_SECURITY_SCC_MODULE) +static struct platform_device mxc_scc_device = { + .name = "mxc_scc", + .id = 0, +}; + +static void mxc_init_scc(void) +{ + platform_device_register(&mxc_scc_device); +} +#else +static inline void mxc_init_scc(void) +{ +} +#endif + +/* SPI controller and device data */ +#if defined(CONFIG_SPI_MXC) || defined(CONFIG_SPI_MXC_MODULE) + +#ifdef CONFIG_SPI_MXC_SELECT1 +/*! + * Resource definition for the CSPI1 + */ +static struct resource mxcspi1_resources[] = { + [0] = { + .start = CSPI1_BASE_ADDR, + .end = CSPI1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_CSPI1, + .end = MXC_INT_CSPI1, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC CSPI1 */ +static struct mxc_spi_master mxcspi1_data = { + .maxchipselect = 4, + .spi_version = 4, +}; + +/*! Device Definition for MXC CSPI1 */ +static struct platform_device mxcspi1_device = { + .name = "mxc_spi", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxcspi1_data, + }, + .num_resources = ARRAY_SIZE(mxcspi1_resources), + .resource = mxcspi1_resources, +}; + +#endif /* CONFIG_SPI_MXC_SELECT1 */ + +#ifdef CONFIG_SPI_MXC_SELECT2 +/*! + * Resource definition for the CSPI2 + */ +static struct resource mxcspi2_resources[] = { + [0] = { + .start = CSPI2_BASE_ADDR, + .end = CSPI2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_CSPI2, + .end = MXC_INT_CSPI2, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC CSPI2 */ +static struct mxc_spi_master mxcspi2_data = { + .maxchipselect = 4, + .spi_version = 4, +}; + +/*! Device Definition for MXC CSPI2 */ +static struct platform_device mxcspi2_device = { + .name = "mxc_spi", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxcspi2_data, + }, + .num_resources = ARRAY_SIZE(mxcspi2_resources), + .resource = mxcspi2_resources, +}; +#endif /* CONFIG_SPI_MXC_SELECT2 */ + +#ifdef CONFIG_SPI_MXC_SELECT3 +/*! + * Resource definition for the CSPI3 + */ +static struct resource mxcspi3_resources[] = { + [0] = { + .start = CSPI3_BASE_ADDR, + .end = CSPI3_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_CSPI3, + .end = MXC_INT_CSPI3, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC CSPI3 */ +static struct mxc_spi_master mxcspi3_data = { + .maxchipselect = 4, + .spi_version = 4, +}; + +/*! Device Definition for MXC CSPI3 */ +static struct platform_device mxcspi3_device = { + .name = "mxc_spi", + .id = 2, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxcspi3_data, + }, + .num_resources = ARRAY_SIZE(mxcspi3_resources), + .resource = mxcspi3_resources, +}; +#endif /* CONFIG_SPI_MXC_SELECT3 */ + +static inline void mxc_init_spi(void) +{ + /* SPBA configuration for CSPI2 - MCU is set */ + spba_take_ownership(SPBA_CSPI2, SPBA_MASTER_A); +#ifdef CONFIG_SPI_MXC_SELECT1 + if (platform_device_register(&mxcspi1_device) < 0) + printk("Error: Registering the SPI Controller_1\n"); +#endif /* CONFIG_SPI_MXC_SELECT1 */ +#ifdef CONFIG_SPI_MXC_SELECT2 + if (platform_device_register(&mxcspi2_device) < 0) + printk("Error: Registering the SPI Controller_2\n"); +#endif /* CONFIG_SPI_MXC_SELECT2 */ +#ifdef CONFIG_SPI_MXC_SELECT3 + if (platform_device_register(&mxcspi3_device) < 0) + printk("Error: Registering the SPI Controller_3\n"); +#endif /* CONFIG_SPI_MXC_SELECT3 */ +} +#else +static inline void mxc_init_spi(void) +{ +} +#endif + +/* I2C controller and device data */ +#if defined(CONFIG_I2C_MXC) || defined(CONFIG_I2C_MXC_MODULE) + +#ifdef CONFIG_I2C_MXC_SELECT1 +/*! + * Resource definition for the I2C1 + */ +static struct resource mxci2c1_resources[] = { + [0] = { + .start = I2C_BASE_ADDR, + .end = I2C_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_I2C, + .end = MXC_INT_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC I2C */ +static struct mxc_i2c_platform_data mxci2c1_data = { + .i2c_clk = 100000, +}; +#endif + +#ifdef CONFIG_I2C_MXC_SELECT2 +/*! + * Resource definition for the I2C2 + */ +static struct resource mxci2c2_resources[] = { + [0] = { + .start = I2C2_BASE_ADDR, + .end = I2C2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_I2C2, + .end = MXC_INT_I2C2, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC I2C */ +static struct mxc_i2c_platform_data mxci2c2_data = { + .i2c_clk = 100000, +}; +#endif + +#ifdef CONFIG_I2C_MXC_SELECT3 +/*! + * Resource definition for the I2C3 + */ +static struct resource mxci2c3_resources[] = { + [0] = { + .start = I2C3_BASE_ADDR, + .end = I2C3_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_I2C3, + .end = MXC_INT_I2C3, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC I2C */ +static struct mxc_i2c_platform_data mxci2c3_data = { + .i2c_clk = 100000, +}; +#endif + +/*! Device Definition for MXC I2C1 */ +static struct platform_device mxci2c_devices[] = { +#ifdef CONFIG_I2C_MXC_SELECT1 + { + .name = "mxc_i2c", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxci2c1_data, + }, + .num_resources = ARRAY_SIZE(mxci2c1_resources), + .resource = mxci2c1_resources,}, +#endif +#ifdef CONFIG_I2C_MXC_SELECT2 + { + .name = "mxc_i2c", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxci2c2_data, + }, + .num_resources = ARRAY_SIZE(mxci2c2_resources), + .resource = mxci2c2_resources,}, +#endif +#ifdef CONFIG_I2C_MXC_SELECT3 + { + .name = "mxc_i2c", + .id = 2, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxci2c3_data, + }, + .num_resources = ARRAY_SIZE(mxci2c3_resources), + .resource = mxci2c3_resources,}, +#endif +}; + +static inline void mxc_init_i2c(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mxci2c_devices); i++) { + if (platform_device_register(&mxci2c_devices[i]) < 0) + dev_err(&mxci2c_devices[i].dev, + "Unable to register I2C device\n"); + } +} +#else +static inline void mxc_init_i2c(void) +{ +} +#endif + +struct mxc_gpio_port mxc_gpio_ports[GPIO_PORT_NUM] = { + { + .num = 0, + .base = IO_ADDRESS(GPIO1_BASE_ADDR), + .irq = MXC_INT_GPIO1, + .virtual_irq_start = MXC_GPIO_INT_BASE, + }, + { + .num = 1, + .base = IO_ADDRESS(GPIO2_BASE_ADDR), + .irq = MXC_INT_GPIO2, + .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN, + }, + { + .num = 2, + .base = IO_ADDRESS(GPIO3_BASE_ADDR), + .irq = MXC_INT_GPIO3, + .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 2, + }, +}; + +#if defined(CONFIG_PCMCIA_MX31ADS) || defined(CONFIG_PCMCIA_MX31ADS_MODULE) + +static struct platform_device mx31ads_device = { + .name = "Mx31ads_pcmcia_socket", + .id = 0, + .dev.release = mxc_nop_release, +}; +static inline void mxc_init_pcmcia(void) +{ + platform_device_register(&mx31ads_device); +} +#else +static inline void mxc_init_pcmcia(void) +{ +} +#endif + +#if defined(CONFIG_MXC_HMP4E) || defined(CONFIG_MXC_HMP4E_MODULE) +static struct platform_device hmp4e_device = { + .name = "mxc_hmp4e", + .id = 0, + .dev = { + .release = mxc_nop_release, + } +}; + +static inline void mxc_init_hmp4e(void) +{ + if (cpu_is_mx32()) + return; + + /* override fuse for Hantro HW clock */ + if (readl(IO_ADDRESS(IIM_BASE_ADDR + 0x808)) == 0x4) { + if (!(readl(IO_ADDRESS(IIM_BASE_ADDR + 0x800)) & (1 << 5))) { + writel(readl(IO_ADDRESS(IIM_BASE_ADDR + 0x808)) & + 0xfffffffb, IO_ADDRESS(IIM_BASE_ADDR + 0x808)); + } + } + + platform_device_register(&hmp4e_device); +} +#else +static inline void mxc_init_hmp4e(void) +{ +} +#endif + +static struct platform_device mxc_dma_device = { + .name = "mxc_dma", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, +}; + +static inline void mxc_init_dma(void) +{ + (void)platform_device_register(&mxc_dma_device); +} + +/*! + * Resource definition for the DPTC LP + */ +static struct resource dptc_resources[] = { + [0] = { + .start = MXC_CCM_BASE, + .end = MXC_CCM_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_CCM, + .end = MXC_INT_CCM, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for DPTC */ +static struct mxc_dptc_data dptc_data = { + .reg_id = "SW1A_NORMAL", + .clk_id = "cpu_clk", + .dptccr_reg_addr = MXC_CCM_PMCR0, + .dcvr0_reg_addr = MXC_CCM_DCVR0, + .gpc_cntr_reg_addr = MXC_CCM_PMCR0, + .dptccr = 0xFFFFFFFF, + .dptc_wp_supported = DPTC_WP_SUPPORTED, + .dptc_wp_allfreq = dptc_wp_allfreq_26ckih, + .clk_max_val = 532000000, + .gpc_adu = 0x0, + .vai_mask = MXC_CCM_PMCR0_PTVAI_MASK, + .vai_offset = MXC_CCM_PMCR0_PTVAI_OFFSET, + .dptc_enable_bit = MXC_CCM_PMCR0_DPTEN, + .irq_mask = MXC_CCM_PMCR0_PTVAIM, + .dptc_nvcr_bit = 0x0, + .gpc_irq_bit = 0x00000000, + .init_config = + MXC_CCM_PMCR0_PTVIS | MXC_CCM_PMCR0_DRCE3 | MXC_CCM_PMCR0_DRCE1, + .enable_config = + MXC_CCM_PMCR0_DPTEN | MXC_CCM_PMCR0_DPVCR | MXC_CCM_PMCR0_DPVV, + .dcr_mask = MXC_CCM_PMCR0_DCR, +}; + +/*! Device Definition for MXC DPTC */ +static struct platform_device mxc_dptc_device = { + .name = "mxc_dptc", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &dptc_data, + }, + .num_resources = ARRAY_SIZE(dptc_resources), + .resource = dptc_resources, +}; + +static inline void mxc_init_dptc(void) +{ + if (clk_get_rate(ckih_clk) == 27000000) { + + if (mxc_cpu_is_rev(CHIP_REV_2_0) < 0) + dptc_data.dptc_wp_allfreq = NULL; + else + dptc_data.dptc_wp_allfreq = + dptc_wp_allfreq_27ckih_TO_2_0; + + } else if (clk_get_rate(ckih_clk) == 26000000 + && mxc_cpu_is_rev(CHIP_REV_2_0) == 1) { + dptc_data.dptc_wp_allfreq = dptc_wp_allfreq_26ckih_TO_2_0; + } + + (void)platform_device_register(&mxc_dptc_device); +} + +#ifdef CONFIG_MXC_VPU +static struct resource vpu_resources[] = { + { + .start = VL2CC_BASE_ADDR, + .end = VL2CC_BASE_ADDR + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +/*! Platform Data for MXC VPU */ +static struct platform_device mxcvpu_device = { + .name = "mxc_vpu", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(vpu_resources), + .resource = vpu_resources, +}; + +static inline void mxc_init_vpu(void) +{ + if (cpu_is_mx32()) { + if (platform_device_register(&mxcvpu_device) < 0) + printk(KERN_ERR "Error: Registering the VPU.\n"); + } +} +#else +static inline void mxc_init_vpu(void) +{ +} +#endif + +#if defined(CONFIG_HW_RANDOM_FSL_RNGA) || \ +defined(CONFIG_HW_RANDOM_FSL_RNGA_MODULE) +static struct resource rnga_resources[] = { + { + .start = RNGA_BASE_ADDR, + .end = RNGA_BASE_ADDR + 0x28, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device fsl_rnga_device = { + .name = "fsl_rnga", + .id = -1, + .num_resources = 1, + .resource = rnga_resources, +}; + +static inline void mxc_init_rnga(void) +{ + platform_device_register(&fsl_rnga_device); +} +#else +static inline void mxc_init_rnga(void) +{ +} +#endif + +int __init mxc_init_devices(void) +{ + mxc_init_wdt(); + mxc_init_ipu(); + mxc_init_spi(); + mxc_init_i2c(); + mxc_init_rtc(); + mxc_init_owire(); + mxc_init_pcmcia(); + mxc_init_scc(); + mxc_init_ssi(); + mxc_init_hmp4e(); + mxc_init_dma(); + mxc_init_audio(); + ckih_clk = clk_get(NULL, "ckih"); + mxc_init_dptc(); + mxc_init_vpu(); + mxc_init_rnga(); + + /* SPBA configuration for SSI2 - SDMA and MCU are set */ + spba_take_ownership(SPBA_SSI2, SPBA_MASTER_C | SPBA_MASTER_A); + return 0; +} diff -urN linux-2.6.26/arch/arm/mach-mx3/dma.c linux-2.6.26-lab126/arch/arm/mach-mx3/dma.c --- linux-2.6.26/arch/arm/mach-mx3/dma.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/dma.c 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,745 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include + +#include "serial.h" + +#define MXC_MMC_BUFFER_ACCESS 0x38 +#define MXC_SSI_TX0_REG 0x0 +#define MXC_SSI_TX1_REG 0x4 +#define MXC_SSI_RX0_REG 0x8 +#define MXC_SSI_RX1_REG 0xC +#define MXC_FIRI_TXFIFO 0x14 +#define MXC_SDHC_MMC_WML 16 +#define MXC_SDHC_SD_WML 64 +#define MXC_SSI_TXFIFO_WML 0x4 +#define MXC_SSI_RXFIFO_WML 0x6 +#define MXC_FIRI_WML 16 + +#ifdef CONFIG_SDMA_IRAM +#define trans_type int_2_per +#else +#define trans_type emi_2_per +#endif + +typedef struct mxc_sdma_info_entry_s { + mxc_dma_device_t device; + mxc_sdma_channel_params_t *chnl_info; +} mxc_sdma_info_entry_t; + +static mxc_sdma_channel_params_t mxc_sdma_uart1_rx_params = { + .chnl_params = { + .watermark_level = UART1_UFCR_RXTL, + .per_address = UART1_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART1_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART1_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart1_tx_params = { + .chnl_params = { + .watermark_level = UART1_UFCR_TXTL, + .per_address = UART1_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART1_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART1_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart2_rx_params = { + .chnl_params = { + .watermark_level = UART2_UFCR_RXTL, + .per_address = UART2_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART2_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART2_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart2_tx_params = { + .chnl_params = { + .watermark_level = UART2_UFCR_TXTL, + .per_address = UART2_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART2_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART2_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart3_rx_params = { + .chnl_params = { + .watermark_level = UART3_UFCR_RXTL, + .per_address = UART3_BASE_ADDR, + .peripheral_type = UART_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART3_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART3_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart3_tx_params = { + .chnl_params = { + .watermark_level = UART3_UFCR_TXTL, + .per_address = UART3_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART3_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART3_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart4_rx_params = { + .chnl_params = { + .watermark_level = UART4_UFCR_RXTL, + .per_address = UART4_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART4_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART4_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart4_tx_params = { + .chnl_params = { + .watermark_level = UART4_UFCR_TXTL, + .per_address = UART4_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART4_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART4_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart5_rx_params = { + .chnl_params = { + .watermark_level = UART5_UFCR_RXTL, + .per_address = UART5_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART5_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART5_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart5_tx_params = { + .chnl_params = { + .watermark_level = UART5_UFCR_TXTL, + .per_address = UART5_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART5_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART5_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc1_width1_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_MMC_WML, + .per_address = + MMC_SDHC1_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SDHC1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MMC1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc1_width4_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_SD_WML, + .per_address = + MMC_SDHC1_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SDHC1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MMC1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc2_width1_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_MMC_WML, + .per_address = + MMC_SDHC2_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SDHC2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MMC2, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc2_width4_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_SD_WML, + .per_address = + MMC_SDHC2_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SDHC2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MMC2, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = trans_type, + .event_id = DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = trans_type, + .event_id = DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = trans_type, + .event_id = DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = trans_type, + .event_id = DMA_REQ_SSI2_TX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = trans_type, + .event_id = DMA_REQ_SSI2_TX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_fir_rx_params = { + .chnl_params = { + .watermark_level = MXC_FIRI_WML, + .per_address = FIRI_BASE_ADDR, + .peripheral_type = FIRI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_FIRI_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_FIR_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_fir_tx_params = { + .chnl_params = { + .watermark_level = MXC_FIRI_WML, + .per_address = FIRI_BASE_ADDR + MXC_FIRI_TXFIFO, + .peripheral_type = FIRI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_FIRI_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_FIR_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_memory_params = { + .chnl_params = { + .peripheral_type = MEMORY, + .transfer_type = emi_2_emi, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MEMORY, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_fifo_memory_params = { + .chnl_params = { + .peripheral_type = FIFO_MEMORY, + .per_address = MXC_FIFO_MEM_DEST_FIXED, + .transfer_type = emi_2_emi, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .event_id = 0, + }, + .channel_num = MXC_DMA_CHANNEL_FIFO_MEMORY, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ata_rx_params = { + .chnl_params = { + .watermark_level = MXC_IDE_DMA_WATERMARK, + .per_address = ATA_DMA_BASE_ADDR, + .peripheral_type = ATA, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ATA_TX_END, + .event_id2 = DMA_REQ_ATA_RX, + .bd_number = MXC_IDE_DMA_BD_NR, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ATA_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ata_tx_params = { + .chnl_params = { + .watermark_level = MXC_IDE_DMA_WATERMARK, + .per_address = ATA_DMA_BASE_ADDR + 0x18, + .peripheral_type = ATA, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_ATA_TX_END, + .event_id2 = DMA_REQ_ATA_TX, + .bd_number = MXC_IDE_DMA_BD_NR, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ATA_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; +static mxc_sdma_info_entry_t mxc_sdma_active_dma_info[] = { + {MXC_DMA_UART1_RX, &mxc_sdma_uart1_rx_params}, + {MXC_DMA_UART1_TX, &mxc_sdma_uart1_tx_params}, + {MXC_DMA_UART2_RX, &mxc_sdma_uart2_rx_params}, + {MXC_DMA_UART2_TX, &mxc_sdma_uart2_tx_params}, + {MXC_DMA_UART3_RX, &mxc_sdma_uart3_rx_params}, + {MXC_DMA_UART3_TX, &mxc_sdma_uart3_tx_params}, + {MXC_DMA_UART4_RX, &mxc_sdma_uart4_rx_params}, + {MXC_DMA_UART4_TX, &mxc_sdma_uart4_tx_params}, + {MXC_DMA_UART5_RX, &mxc_sdma_uart5_rx_params}, + {MXC_DMA_UART5_TX, &mxc_sdma_uart5_tx_params}, + {MXC_DMA_MMC1_WIDTH_1, &mxc_sdma_mmc1_width1_params}, + {MXC_DMA_MMC1_WIDTH_4, &mxc_sdma_mmc1_width4_params}, + {MXC_DMA_MMC2_WIDTH_1, &mxc_sdma_mmc2_width1_params}, + {MXC_DMA_MMC2_WIDTH_4, &mxc_sdma_mmc2_width4_params}, + {MXC_DMA_SSI1_8BIT_RX0, &mxc_sdma_ssi1_8bit_rx0_params}, + {MXC_DMA_SSI1_8BIT_TX0, &mxc_sdma_ssi1_8bit_tx0_params}, + {MXC_DMA_SSI1_16BIT_RX0, &mxc_sdma_ssi1_16bit_rx0_params}, + {MXC_DMA_SSI1_16BIT_TX0, &mxc_sdma_ssi1_16bit_tx0_params}, + {MXC_DMA_SSI1_24BIT_RX0, &mxc_sdma_ssi1_24bit_rx0_params}, + {MXC_DMA_SSI1_24BIT_TX0, &mxc_sdma_ssi1_24bit_tx0_params}, + {MXC_DMA_SSI1_8BIT_RX1, &mxc_sdma_ssi1_8bit_rx1_params}, + {MXC_DMA_SSI1_8BIT_TX1, &mxc_sdma_ssi1_8bit_tx1_params}, + {MXC_DMA_SSI1_16BIT_RX1, &mxc_sdma_ssi1_16bit_rx1_params}, + {MXC_DMA_SSI1_16BIT_TX1, &mxc_sdma_ssi1_16bit_tx1_params}, + {MXC_DMA_SSI1_24BIT_RX1, &mxc_sdma_ssi1_24bit_rx1_params}, + {MXC_DMA_SSI1_24BIT_TX1, &mxc_sdma_ssi1_24bit_tx1_params}, + {MXC_DMA_SSI2_8BIT_RX0, &mxc_sdma_ssi2_8bit_rx0_params}, + {MXC_DMA_SSI2_8BIT_TX0, &mxc_sdma_ssi2_8bit_tx0_params}, + {MXC_DMA_SSI2_16BIT_RX0, &mxc_sdma_ssi2_16bit_rx0_params}, + {MXC_DMA_SSI2_16BIT_TX0, &mxc_sdma_ssi2_16bit_tx0_params}, + {MXC_DMA_SSI2_24BIT_RX0, &mxc_sdma_ssi2_24bit_rx0_params}, + {MXC_DMA_SSI2_24BIT_TX0, &mxc_sdma_ssi2_24bit_tx0_params}, + {MXC_DMA_SSI2_8BIT_RX1, &mxc_sdma_ssi2_8bit_rx1_params}, + {MXC_DMA_SSI2_8BIT_TX1, &mxc_sdma_ssi2_8bit_tx1_params}, + {MXC_DMA_SSI2_16BIT_RX1, &mxc_sdma_ssi2_16bit_rx1_params}, + {MXC_DMA_SSI2_16BIT_TX1, &mxc_sdma_ssi2_16bit_tx1_params}, + {MXC_DMA_SSI2_24BIT_RX1, &mxc_sdma_ssi2_24bit_rx1_params}, + {MXC_DMA_SSI2_24BIT_TX1, &mxc_sdma_ssi2_24bit_tx1_params}, + {MXC_DMA_FIR_RX, &mxc_sdma_fir_rx_params}, + {MXC_DMA_FIR_TX, &mxc_sdma_fir_tx_params}, + {MXC_DMA_MEMORY, &mxc_sdma_memory_params}, + {MXC_DMA_FIFO_MEMORY, &mxc_sdma_fifo_memory_params}, + {MXC_DMA_ATA_RX, &mxc_sdma_ata_rx_params}, + {MXC_DMA_ATA_TX, &mxc_sdma_ata_tx_params}, +}; + +static int mxc_sdma_info_entrys = + sizeof(mxc_sdma_active_dma_info) / sizeof(mxc_sdma_active_dma_info[0]); + +/*! + * This functions Returns the SDMA paramaters associated for a module + * + * @param channel_id the ID of the module requesting DMA + * @return returns the sdma parameters structure for the device + */ +mxc_sdma_channel_params_t *mxc_sdma_get_channel_params(mxc_dma_device_t + channel_id) +{ + mxc_sdma_info_entry_t *p = mxc_sdma_active_dma_info; + int i; + + for (i = 0; i < mxc_sdma_info_entrys; i++, p++) { + if (p->device == channel_id) { + return p->chnl_info; + } + } + return NULL; +} + +/*! + * This functions marks the SDMA channels that are statically allocated + * + * @param chnl the channel array used to store channel information + */ +void mxc_get_static_channels(mxc_dma_channel_t * chnl) +{ +#ifdef CONFIG_SDMA_IRAM + int i; + for (i = MXC_DMA_CHANNEL_IRAM; i < MAX_DMA_CHANNELS; i++) + chnl[i].dynamic = 0; +#endif /*CONFIG_SDMA_IRAM */ +} + +EXPORT_SYMBOL(mxc_sdma_get_channel_params); +EXPORT_SYMBOL(mxc_get_static_channels); diff -urN linux-2.6.26/arch/arm/mach-mx3/dptc.c linux-2.6.26-lab126/arch/arm/mach-mx3/dptc.c --- linux-2.6.26/arch/arm/mach-mx3/dptc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/dptc.c 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,103 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dptc.c + * + * @brief DPTC table for the Freescale Semiconductor MXC DPTC module. + * + * @ingroup PM + */ + +#include +#include + +struct dptc_wp dptc_wp_allfreq_26ckih[DPTC_WP_SUPPORTED] = { + /* 532MHz */ + /* dcvr0 dcvr1 dcvr2 dcvr3 voltage */ + /* wp0 */ + {0xffc00000, 0x95c00000, 0xffc00000, 0xe5800000, 1625}, + {0xffc00000, 0x95e3e8e4, 0xffc00000, 0xe5b6fda0, 1600}, + {0xffc00000, 0x95e3e8e4, 0xffc00000, 0xe5b6fda0, 1575}, + {0xffc00000, 0x95e3e8e8, 0xffc00000, 0xe5f70da4, 1550}, + {0xffc00000, 0x9623f8e8, 0xffc00000, 0xe6371da8, 1525}, + /* wp5 */ + {0xffc00000, 0x966408f0, 0xffc00000, 0xe6b73db0, 1500}, + {0xffc00000, 0x96e428f4, 0xffc00000, 0xe7776dbc, 1475}, + {0xffc00000, 0x976448fc, 0xffc00000, 0xe8379dc8, 1450}, + {0xffc00000, 0x97e46904, 0xffc00000, 0xe977ddd8, 1425}, + {0xffc00000, 0x98a48910, 0xffc00000, 0xeab81de8, 1400}, + /* wp10 */ + {0xffc00000, 0x9964b918, 0xffc00000, 0xebf86df8, 1375}, + {0xffc00000, 0xffe4e924, 0xffc00000, 0xfff8ae08, 1350}, + {0xffc00000, 0xffe5192c, 0xffc00000, 0xfff8fe1c, 1350}, + {0xffc00000, 0xffe54938, 0xffc00000, 0xfff95e2c, 1350}, + {0xffc00000, 0xffe57944, 0xffc00000, 0xfff9ae44, 1350}, + /* wp15 */ + {0xffc00000, 0xffe5b954, 0xffc00000, 0xfffa0e58, 1350}, + {0xffc00000, 0xffe5e960, 0xffc00000, 0xfffa6e70, 1350}, +}; + +struct dptc_wp dptc_wp_allfreq_26ckih_TO_2_0[DPTC_WP_SUPPORTED] = { + /* Mx31 TO 2.0 Offset table */ + /* 532MHz */ + /* dcvr0 dcvr1 dcvr2 dcvr3 voltage */ + /* wp0 */ + {0xffc00000, 0x9E265978, 0xffc00000, 0xE4371D9C, 1625}, + {0xffc00000, 0x9E665978, 0xffc00000, 0xE4772D9C, 1600}, + {0xffc00000, 0x9EA65978, 0xffc00000, 0xE4772DA0, 1575}, + {0xffc00000, 0x9EE66978, 0xffc00000, 0xE4B73DA0, 1550}, + {0xffc00000, 0x9F26697C, 0xffc00000, 0xE4F73DA0, 1525}, + /* wp5 */ + {0xffc00000, 0x9F66797C, 0xffc00000, 0xE5774DA4, 1500}, + {0xffc00000, 0x9FE6797C, 0xffc00000, 0xE5F75DA4, 1475}, + {0xffc00000, 0xA026897C, 0xffc00000, 0xE6776DA4, 1450}, + {0xffc00000, 0xA0A6897C, 0xffc00000, 0xE6F77DA8, 1425}, + {0xffc00000, 0xA0E69980, 0xffc00000, 0xE7B78DAC, 1400}, + /* wp10 */ + {0xffc00000, 0xA1669980, 0xffc00000, 0xE8379DAC, 1375}, + {0xffc00000, 0xA1A6A980, 0xffc00000, 0xE8F7ADB0, 1350}, + {0xffc00000, 0xA226B984, 0xffc00000, 0xE9F7CDB0, 1325}, + {0xffc00000, 0xA2A6C984, 0xffc00000, 0xEAB7DDB4, 1300}, + {0xffc00000, 0xA326C988, 0xffc00000, 0xEBB7FDB8, 1275}, + /* wp15 */ + {0xffc00000, 0xA3A6D988, 0xffc00000, 0xECB80DBC, 1250}, + {0xffc00000, 0xA426E988, 0xffc00000, 0xEDB82DC0, 1225}, +}; + +struct dptc_wp dptc_wp_allfreq_27ckih_TO_2_0[DPTC_WP_SUPPORTED] = { + /* Mx31 TO 2.0 Offset table */ + /* 532MHz */ + /* dcvr0 dcvr1 dcvr2 dcvr3 voltage */ + /* wp0 */ + {0xffc00000, 0x9864E920, 0xffc00000, 0xDBB50D1C, 1625}, + {0xffc00000, 0x98A4E920, 0xffc00000, 0xDBF51D1C, 1600}, + {0xffc00000, 0x98E4E920, 0xffc00000, 0xDBF51D20, 1575}, + {0xffc00000, 0x9924F920, 0xffc00000, 0xDC352D20, 1550}, + {0xffc00000, 0x9924F924, 0xffc00000, 0xDC752D20, 1525}, + /* wp5 */ + {0xffc00000, 0x99650924, 0xffc00000, 0xDCF53D24, 1500}, + {0xffc00000, 0x99E50924, 0xffc00000, 0xDD754D24, 1475}, + {0xffc00000, 0x9A251924, 0xffc00000, 0xDDF55D24, 1450}, + {0xffc00000, 0x9AA51924, 0xffc00000, 0xDE756D28, 1425}, + {0xffc00000, 0x9AE52928, 0xffc00000, 0xDF357D2C, 1400}, + /* wp10 */ + {0xffc00000, 0x9B652928, 0xffc00000, 0xDFB58D2C, 1375}, + {0xffc00000, 0x9BA53928, 0xffc00000, 0xE0759D30, 1350}, + {0xffc00000, 0x9C254928, 0xffc00000, 0xE135BD30, 1325}, + {0xffc00000, 0x9CA55928, 0xffc00000, 0xE1F5CD34, 1300}, + {0xffc00000, 0x9D25592C, 0xffc00000, 0xE2F5ED38, 1275}, + /* wp15 */ + {0xffc00000, 0x9DA5692C, 0xffc00000, 0xE3F5FD38, 1250}, + {0xffc00000, 0x9E25792C, 0xffc00000, 0xE4F61D3C, 1225}, +}; diff -urN linux-2.6.26/arch/arm/mach-mx3/dvfs_v2.c linux-2.6.26-lab126/arch/arm/mach-mx3/dvfs_v2.c --- linux-2.6.26/arch/arm/mach-mx3/dvfs_v2.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/dvfs_v2.c 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,530 @@ +/* + * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dvfs_v2.c + * + * @brief A simplied driver for the Freescale Semiconductor MXC DVFS module. + * + * Upon initialization, the DVFS driver initializes the DVFS hardware + * sets up driver nodes attaches to the DVFS interrupt and initializes internal + * data structures. When the DVFS interrupt occurs the driver checks the cause + * of the interrupt (lower frequency, increase frequency or emergency) and changes + * the CPU voltage according to translation table that is loaded into the driver. + * + * @ingroup PM + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "iomux.h" +#include "crm_regs.h" + +static int dvfs_is_active; + +/* Used for tracking the number of interrupts */ +static u32 dvfs_nr_up[4]; +static u32 dvfs_nr_dn[4]; + +/* + * Clock structures + */ +static struct clk *cpu_clk; +static struct clk *ahb_clk; + +enum { + FSVAI_FREQ_NOCHANGE = 0x0, + FSVAI_FREQ_INCREASE, + FSVAI_FREQ_DECREASE, + FSVAI_FREQ_EMERG, +}; + +/* + * Frequency increase threshold. Increase frequency change request + * will be sent if DVFS counter value will be more than this value. + */ +#define DVFS_UPTHR (30 << MXC_CCM_LTR0_UPTHR_OFFSET) + +/* + * Frequency decrease threshold. Decrease frequency change request + * will be sent if DVFS counter value will be less than this value. + */ +#define DVFS_DNTHR (18 << MXC_CCM_LTR0_DNTHR_OFFSET) + +/* + * With the ARM clocked at 532, this setting yields a DIV_3_CLK of 2.03 kHz. + */ +#define DVFS_DIV3CK (3 << MXC_CCM_LTR0_DIV3CK_OFFSET) + +/* + * DNCNT defines the amount of times the down threshold should be exceeded + * before DVFS will trigger frequency decrease request. + */ +#define DVFS_DNCNT (0x33 << MXC_CCM_LTR1_DNCNT_OFFSET) + +/* + * UPCNT defines the amount of times the up threshold should be exceeded + * before DVFS will trigger frequency increase request. + */ +#define DVFS_UPCNT (0x33 << MXC_CCM_LTR1_UPCNT_OFFSET) + +/* + * Panic threshold. Panic frequency change request + * will be sent if DVFS counter value will be more than this value. + */ +#define DVFS_PNCTHR (63 << MXC_CCM_LTR1_PNCTHR_OFFSET) + +/* + * Load tracking buffer source: 1 for ld_add; 0 for pre_ld_add + */ +#define DVFS_LTBRSR (1 << MXC_CCM_LTR1_LTBRSR_OFFSET) + +/* EMAC defines how many samples are included in EMA calculation */ +#define DVFS_EMAC (0x20 << MXC_CCM_LTR2_EMAC_OFFSET) + +const static u8 ltr_gp_weight[] = { + 0, /* 0 */ + 0, + 0, + 0, + 0, + 0, /* 5 */ + 0, + 0, + 0, + 0, + 0, /* 10 */ + 0, + 7, + 7, + 7, + 7, /* 15 */ +}; + +DEFINE_SPINLOCK(mxc_dvfs_lock); + +/*! + * This function sets the weight of general purpose signals + * @param gp_id number of general purpose bit + * @param weight the weight of the general purpose bit + */ +static void set_gp_weight(int gp_id, u8 weight) +{ + u32 reg; + + if (gp_id < 9) { + reg = __raw_readl(MXC_CCM_LTR3); + reg = (reg & ~(MXC_CCM_LTR3_WSW_MASK(gp_id))) | + (weight << MXC_CCM_LTR3_WSW_OFFSET(gp_id)); + __raw_writel(reg, MXC_CCM_LTR3); + } else if (gp_id < 16) { + reg = __raw_readl(MXC_CCM_LTR2); + reg = (reg & ~(MXC_CCM_LTR2_WSW_MASK(gp_id))) | + (weight << MXC_CCM_LTR2_WSW_OFFSET(gp_id)); + __raw_writel(reg, MXC_CCM_LTR2); + } +} + +static int start_dvfs(void) +{ + u32 reg, flags; + + if (dvfs_is_active) { + return 0; + } + + spin_lock_irqsave(&mxc_dvfs_lock, flags); + + reg = __raw_readl(MXC_CCM_PMCR0); + + /* enable dvfs and interrupt */ + reg = (reg & ~MXC_CCM_PMCR0_FSVAIM) | MXC_CCM_PMCR0_DVFEN; + + __raw_writel(reg, MXC_CCM_PMCR0); + + dvfs_is_active = 1; + + spin_unlock_irqrestore(&mxc_dvfs_lock, flags); + + pr_info("DVFS is started\n"); + + return 0; +} + +#define MXC_CCM_LTR0_CONFIG_MASK (MXC_CCM_LTR0_UPTHR_MASK | \ + MXC_CCM_LTR0_DNTHR_MASK | \ + MXC_CCM_LTR0_DIV3CK_MASK) +#define MXC_CCM_LTR0_CONFIG_VAL (DVFS_UPTHR | DVFS_DNTHR | DVFS_DIV3CK) + +#define MXC_CCM_LTR1_CONFIG_MASK (MXC_CCM_LTR1_UPCNT_MASK | \ + MXC_CCM_LTR1_DNCNT_MASK | \ + MXC_CCM_LTR1_PNCTHR_MASK | \ + MXC_CCM_LTR1_LTBRSR_MASK) +#define MXC_CCM_LTR1_CONFIG_VAL (DVFS_UPCNT | DVFS_DNCNT | \ + DVFS_PNCTHR | DVFS_LTBRSR) + +/*! + * This function is called for module initialization. + * It sets up the DVFS hardware. + * It sets default values for DVFS thresholds and counters. The default + * values was chosen from a set of different reasonable values. They was tested + * and the default values in the driver gave the best results. + * More work should be done to find optimal values. + * + * @return 0 if successful; non-zero otherwise. + * + */ +static int init_dvfs_controller(void) +{ + u32 i, reg; + + /* Configure 2 MC13783 DVFS pins */ + mxc_request_iomux(MX31_PIN_DVFS0, OUTPUTCONFIG_FUNC, INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_DVFS1, OUTPUTCONFIG_FUNC, INPUTCONFIG_NONE); + + /* Configure MC13783 voltage ready input pin */ + mxc_request_iomux(MX31_PIN_GPIO1_5, OUTPUTCONFIG_GPIO, + INPUTCONFIG_FUNC); + + /* setup LTR0 */ + reg = __raw_readl(MXC_CCM_LTR0); + reg = (reg & ~(MXC_CCM_LTR0_CONFIG_MASK)) | MXC_CCM_LTR0_CONFIG_VAL; + __raw_writel(reg, MXC_CCM_LTR0); + + /* set up LTR1 */ + reg = __raw_readl(MXC_CCM_LTR1); + reg = (reg & ~(MXC_CCM_LTR1_CONFIG_MASK)) | MXC_CCM_LTR1_CONFIG_VAL; + __raw_writel(reg, MXC_CCM_LTR1); + + /* setup LTR2 */ + reg = __raw_readl(MXC_CCM_LTR2); + reg = (reg & ~(MXC_CCM_LTR2_EMAC_MASK)) | DVFS_EMAC; + __raw_writel(reg, MXC_CCM_LTR2); + + /* Set general purpose weights to 0 */ + for (i = 0; i < 16; i++) { + set_gp_weight(i, ltr_gp_weight[i]); + } + + /* ARM interrupt, mask load buf full interrupt */ + reg = __raw_readl(MXC_CCM_PMCR0); + reg |= MXC_CCM_PMCR0_DVFIS | MXC_CCM_PMCR0_LBMI; + __raw_writel(reg, MXC_CCM_PMCR0); + + /* configuring EMI Handshake and PLL relock disable */ + reg = __raw_readl(MXC_CCM_PMCR1); + reg |= MXC_CCM_PMCR1_PLLRDIS; + reg |= MXC_CCM_PMCR1_EMIRQ_EN; + __raw_writel(reg, MXC_CCM_PMCR1); + + return 0; +} + +static irqreturn_t dvfs_irq(int irq, void *dev_id) +{ + u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0); + u32 fsvai = (pmcr0 & MXC_CCM_PMCR0_FSVAI_MASK) >> + MXC_CCM_PMCR0_FSVAI_OFFSET; + u32 dvsup = (pmcr0 & MXC_CCM_PMCR0_DVSUP_MASK) >> + MXC_CCM_PMCR0_DVSUP_OFFSET; + u32 curr_ahb, curr_cpu, rate; + + /* Should not be here if FSVAIM is set */ + BUG_ON(pmcr0 & MXC_CCM_PMCR0_FSVAIM); + + if (fsvai == FSVAI_FREQ_NOCHANGE) { + /* Do nothing. Freq change is not required */ + printk(KERN_WARNING "fsvai should not be 0\n"); + return IRQ_HANDLED; + } + + if (!(pmcr0 & MXC_CCM_PMCR0_UPDTEN)) { + /* Do nothing. DVFS didn't finish previous flow update */ + return IRQ_HANDLED; + } + + if (((dvsup == DVSUP_LOW) && (fsvai == FSVAI_FREQ_DECREASE)) || + ((dvsup == DVSUP_TURBO) && ((fsvai == FSVAI_FREQ_INCREASE) || + (fsvai == FSVAI_FREQ_EMERG)))) { + /* Interrupt should be disabled in these cases according to + * the spec since DVFS is already at lowest (highest) state */ + printk(KERN_WARNING "Something is wrong?\n"); + return IRQ_HANDLED; + } + + curr_ahb = clk_get_rate(ahb_clk); + if (fsvai == FSVAI_FREQ_DECREASE) { + curr_cpu = clk_get_rate(cpu_clk); + rate = ((curr_cpu / curr_ahb) - 1) * curr_ahb; + if ((cpu_is_mx31_rev(CHIP_REV_2_0) < 0) && + ((curr_cpu / curr_ahb) == 4)) { + rate = ((curr_cpu / curr_ahb) - 2) * curr_ahb; + } + dvfs_nr_dn[dvsup]++; + } else { + rate = 4 * curr_ahb; + dvfs_nr_up[dvsup]++; + } + + clk_set_rate(cpu_clk, rate); + return IRQ_HANDLED; +} + +/*! + * This function disables the DVFS module. + */ +static void stop_dvfs(void) +{ + u32 pmcr0, dvsup, flags; + u32 curr_ahb = clk_get_rate(ahb_clk); + + if (dvfs_is_active) { + spin_lock_irqsave(&mxc_dvfs_lock, flags); + + pmcr0 = __raw_readl(MXC_CCM_PMCR0); + dvsup = (pmcr0 & MXC_CCM_PMCR0_DVSUP_MASK) >> + MXC_CCM_PMCR0_DVSUP_OFFSET; + if (dvsup != DVSUP_TURBO) { + /* Use sw delay to insure volt/freq change */ + clk_set_rate(cpu_clk, (4 * curr_ahb)); + udelay(200); + } + + pmcr0 = __raw_readl(MXC_CCM_PMCR0); + /* disable dvfs and its interrupt */ + pmcr0 = (pmcr0 & ~MXC_CCM_PMCR0_DVFEN) | MXC_CCM_PMCR0_FSVAIM; + __raw_writel(pmcr0, MXC_CCM_PMCR0); + + dvfs_is_active = 0; + + spin_unlock_irqrestore(&mxc_dvfs_lock, flags); + } + + pr_info("DVFS is stopped\n"); +} + +void pmic_voltage_init(void) +{ + t_regulator_voltage volt; + + /* Enable 4 mc13783 output voltages */ + pmic_write_reg(REG_ARBITRATION_SWITCHERS, (1 << 5), (1 << 5)); + + /* Set mc13783 DVS speed 25mV each 4us */ + pmic_write_reg(REG_SWITCHERS_4, (0 << 6), (3 << 6)); + + if (cpu_is_mx31()) + volt.sw1a = SW1A_1_625V; + else + volt.sw1a = SW1A_1_425V; + + pmic_power_regulator_set_voltage(SW_SW1A, volt); + + volt.sw1a = SW1A_1_25V; + pmic_power_switcher_set_dvs(SW_SW1A, volt); + + if (cpu_is_mx32()) { + volt.sw1a = SW1A_0_975V; + pmic_power_switcher_set_stby(SW_SW1A, volt); + } + + volt.sw1b = SW1A_1_25V; + pmic_power_switcher_set_dvs(SW_SW1B, volt); + + volt.sw1b = SW1A_1_25V; + pmic_power_switcher_set_stby(SW_SW1B, volt); +} + +static ssize_t dvfs_enable_store(struct sys_device *dev, const char *buf, + size_t size) +{ + if (strstr(buf, "1") != NULL) { + if (start_dvfs() != 0) { + printk(KERN_ERR "Failed to start DVFS\n"); + } + } else if (strstr(buf, "0") != NULL) { + stop_dvfs(); + } + + return size; +} + +static ssize_t dvfs_status_show(struct sys_device *dev, char *buf) +{ + int size = 0; + + if (dvfs_is_active) { + size = sprintf(buf, "DVFS is enabled\n"); + } else { + size = sprintf(buf, "DVFS is disabled\n"); + } + size += + sprintf((buf + size), "UP:\t%d\t%d\t%d\t%d\n", dvfs_nr_up[0], + dvfs_nr_up[1], dvfs_nr_up[2], dvfs_nr_up[3]); + size += + sprintf((buf + size), "DOWN:\t%d\t%d\t%d\t%d\n\n", dvfs_nr_dn[0], + dvfs_nr_dn[1], dvfs_nr_dn[2], dvfs_nr_dn[3]); + + return size; +} + +static ssize_t dvfs_status_store(struct sys_device *dev, const char *buf, + size_t size) +{ + if (strstr(buf, "reset") != NULL) { + int i; + for (i = 0; i < 4; i++) { + dvfs_nr_up[i] = 0; + dvfs_nr_dn[i] = 0; + } + } + + return size; +} + +static ssize_t dvfs_debug_show(struct sys_device *dev, char *buf) +{ + int size = 0; + u32 curr_ahb, curr_cpu; + + curr_ahb = clk_get_rate(ahb_clk); + curr_cpu = clk_get_rate(cpu_clk); + + pr_debug("ahb %d, cpu %d\n", curr_ahb, curr_cpu); + + return size; +} + +static ssize_t dvfs_debug_store(struct sys_device *dev, const char *buf, + size_t size) +{ + u32 curr_ahb, curr_cpu, rate = 0; + + curr_ahb = clk_get_rate(ahb_clk); + curr_cpu = clk_get_rate(cpu_clk); + + if (strstr(buf, "inc") != NULL) { + rate = 4 * curr_ahb; + pr_debug("inc to %d\n", rate); + } + + if (strstr(buf, "dec") != NULL) { + rate = ((curr_cpu / curr_ahb) - 1) * curr_ahb; + if ((cpu_is_mx31_rev(CHIP_REV_2_0) < 0) && + ((curr_cpu / curr_ahb) == 4)) + rate = ((curr_cpu / curr_ahb) - 2) * curr_ahb; + + pr_debug("dec to %d\n", rate); + } + + clk_set_rate(cpu_clk, rate); + + return size; +} + +static SYSDEV_ATTR(enable, 0200, NULL, dvfs_enable_store); +static SYSDEV_ATTR(status, 0644, dvfs_status_show, dvfs_status_store); +static SYSDEV_ATTR(debug, 0644, dvfs_debug_show, dvfs_debug_store); + +static struct sysdev_class dvfs_sysclass = { + .name = "dvfs", +}; + +static struct sys_device dvfs_device = { + .id = 0, + .cls = &dvfs_sysclass, +}; + +static int dvfs_sysdev_ctrl_init(void) +{ + int err; + + err = sysdev_class_register(&dvfs_sysclass); + if (!err) + err = sysdev_register(&dvfs_device); + if (!err) { + err = sysdev_create_file(&dvfs_device, &attr_enable); + err = sysdev_create_file(&dvfs_device, &attr_status); + err = sysdev_create_file(&dvfs_device, &attr_debug); + } + + return err; +} + +static void dvfs_sysdev_ctrl_exit(void) +{ + sysdev_remove_file(&dvfs_device, &attr_enable); + sysdev_remove_file(&dvfs_device, &attr_status); + sysdev_unregister(&dvfs_device); + sysdev_class_unregister(&dvfs_sysclass); +} + +static int __init dvfs_init(void) +{ + int err = 0; + pmic_voltage_init(); + + cpu_clk = clk_get(NULL, "cpu_clk"); + ahb_clk = clk_get(NULL, "ahb_clk"); + err = init_dvfs_controller(); + if (err) { + printk(KERN_ERR "DVFS: Unable to initialize DVFS"); + return err; + } + + /* request the DVFS interrupt */ + err = request_irq(MXC_INT_DVFS, dvfs_irq, IRQF_DISABLED, "dvfs", NULL); + if (err) { + printk(KERN_ERR "DVFS: Unable to attach to DVFS interrupt"); + } + + err = dvfs_sysdev_ctrl_init(); + if (err) { + printk(KERN_ERR + "DVFS: Unable to register sysdev entry for dvfs"); + return err; + } + + return err; +} + +static void __exit dvfs_cleanup(void) +{ + stop_dvfs(); + + /* release the DVFS interrupt */ + free_irq(MXC_INT_DVFS, NULL); + + dvfs_sysdev_ctrl_exit(); + + clk_put(cpu_clk); + clk_put(ahb_clk); +} + +module_init(dvfs_init); +module_exit(dvfs_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("DVFS driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/mach-mx3/iomux.c linux-2.6.26-lab126/arch/arm/mach-mx3/iomux.c --- linux-2.6.26/arch/arm/mach-mx3/iomux.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/iomux.c 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,259 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup GPIO_MX31 Board GPIO and Muxing Setup + * @ingroup MSL_MX31 + */ +/*! + * @file mach-mx3/iomux.c + * + * @brief I/O Muxing control functions + * + * @ingroup GPIO_MX31 + */ + +#include +#include +#include +#include +#include "iomux.h" + +/*! + * 4 control fields per MUX register + */ +#define MUX_CTL_FIELDS 4 + +/*! + * 3 control fields per PAD register + */ +#define PAD_CTL_FIELDS 3 + +/*! + * Maximum number of MUX pins + * Number of pins = (highest iomux reg - lowest iomux reg + 1) * (4 pins/reg) + */ +#define MUX_PIN_NUM_MAX \ + (((u32 *)IOMUXSW_MUX_END - (u32 *)IOMUXSW_MUX_CTL + 1) * MUX_CTL_FIELDS) + +/*! + * Number of pad controls = + * (highest pad ctl reg - lowest pad ctl reg + 1) * (3 pins/reg) + */ +#define PAD_CTL_NUM_MAX \ + (((u32 *)IOMUXSW_PAD_END - (u32 *)IOMUXSW_PAD_CTL + 1) * PAD_CTL_FIELDS) + +#define PIN_TO_IOMUX_INDEX(pin) ((pin >> MUX_I) & ((1 << (MUX_F - MUX_I)) - 1)) +#define PIN_TO_IOMUX_FIELD(pin) ((pin >> MUX_F) & ((1 << (PAD_I - MUX_F)) - 1)) + +/*! + * 8 bits for each MUX control field + */ +#define MUX_CTL_BIT_LEN 8 + +/*! + * 10 bits for each PAD control field + */ +#define MUX_PAD_BIT_LEN 10 + +/*! + * IOMUX register (base) addresses + */ +enum iomux_reg_addr { + IOMUXGPR = IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x008, /*!< General purpose */ + IOMUXSW_MUX_CTL = IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x00C, /*!< MUX control */ + IOMUXSW_MUX_END = IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x150, /*!< last MUX control register */ + IOMUXSW_PAD_CTL = IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x154, /*!< Pad control */ + IOMUXSW_PAD_END = IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x308, /*!< last Pad control register */ + IOMUXINT_OBS1 = IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x000, /*!< Observe interrupts 1 */ + IOMUXINT_OBS2 = IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x004, /*!< Observe interrupts 2 */ +}; + +/* len - mask bit length; fld - mask bit field. Example, to have the mask: + * 0xFF000000, use GET_FIELD_MASK(8, 3). Translate in plain language: + * "set the 3rd (0-based) 8-bit-long field to all 1's */ +#define GET_FIELD_MASK(len, fld) (((1 << len) - 1) << (len * fld)) +static DEFINE_SPINLOCK(gpio_mux_lock); +static u8 iomux_pin_res_table[MUX_PIN_NUM_MAX]; + +/*! + * This function is used to configure a pin through the IOMUX module. + * FIXED ME: for backward compatible. Will be static function! + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param out an output function as defined in \b #iomux_pin_ocfg_t + * @param in an input function as defined in \b #iomux_pin_icfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_ocfg_t out, + iomux_pin_icfg_t in) +{ + u32 reg, l, ret = 0; + u32 mux_index = PIN_TO_IOMUX_INDEX(pin); + u32 mux_field = PIN_TO_IOMUX_FIELD(pin); + u32 mux_mask = GET_FIELD_MASK(MUX_CTL_BIT_LEN, mux_field); + u8 *rp; + + BUG_ON((mux_index > (MUX_PIN_NUM_MAX / MUX_CTL_FIELDS - 1)) || + (mux_field >= MUX_CTL_FIELDS)); + + reg = IOMUXSW_MUX_CTL + (mux_index * 4); + spin_lock(&gpio_mux_lock); + l = __raw_readl(reg); + l = (l & (~mux_mask)) | + (((out << 4) | in) << (mux_field * MUX_CTL_BIT_LEN)); + __raw_writel(l, reg); + /* + * Log a warning if a pin changes ownership + */ + rp = iomux_pin_res_table + mux_index * MUX_CTL_FIELDS + mux_field; + if (out & *rp && *rp != ((out << 4) | in)) { + /* + * Don't call printk if we're tweaking the console uart or + * we'll deadlock. + */ + if (pin != MX31_PIN_CTS1 && + pin != MX31_PIN_RTS1 && + pin != MX31_PIN_DCD_DCE1 && + pin != MX31_PIN_DSR_DTE1 && + pin != MX31_PIN_DTR_DTE1 && + pin != MX31_PIN_RI_DCE1 && + pin != MX31_PIN_DSR_DCE1 && + pin != MX31_PIN_DTR_DCE1 && + pin != MX31_PIN_RXD1 && pin != MX31_PIN_TXD1) { + printk(KERN_ERR "iomux_config_mux: Warning: iomux pin" + " config changed, index=%d field=%d, " + " prev=0x%x new=0x%x\n", mux_index, mux_field, + *rp, (out << 4) | in); + } + ret = -EINVAL; + } + *rp = (out << 4) | in; + spin_unlock(&gpio_mux_lock); + + return ret; +} + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param out an output function as defined in \b #iomux_pin_ocfg_t + * @param in an input function as defined in \b #iomux_pin_icfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_ocfg_t out, + iomux_pin_icfg_t in) +{ + int ret = iomux_config_mux(pin, out, in); + if (out == OUTPUTCONFIG_GPIO && in == INPUTCONFIG_GPIO) { + ret |= mxc_request_gpio(pin); + } + return ret; +} + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param out an output function as defined in \b #iomux_pin_ocfg_t + * @param in an input function as defined in \b #iomux_pin_icfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_ocfg_t out, + iomux_pin_icfg_t in) +{ + u32 mux_index = PIN_TO_IOMUX_INDEX(pin); + u32 mux_field = PIN_TO_IOMUX_FIELD(pin); + u8 *rp = iomux_pin_res_table + mux_index * MUX_CTL_FIELDS + mux_field; + + BUG_ON((mux_index > (MUX_PIN_NUM_MAX / MUX_CTL_FIELDS - 1)) || + (mux_field >= MUX_CTL_FIELDS)); + + *rp = 0; + if (out == OUTPUTCONFIG_GPIO && in == INPUTCONFIG_GPIO) { + mxc_free_gpio(pin); + } +} + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) +{ + u32 reg, l; + u32 pad_index = (pin >> PAD_I) & ((1 << (PAD_F - PAD_I)) - 1); + u32 pad_field = (pin >> PAD_F) & ((1 << (MUX_IO_I - PAD_F)) - 1); + u32 pad_mask = GET_FIELD_MASK(MUX_PAD_BIT_LEN, pad_field); + + BUG_ON((pad_index > (PAD_CTL_NUM_MAX / PAD_CTL_FIELDS - 1)) || + (pad_field >= PAD_CTL_FIELDS)); + + reg = IOMUXSW_PAD_CTL + (pad_index * 4); + spin_lock(&gpio_mux_lock); + l = __raw_readl(reg); + l = (l & (~pad_mask)) | (config << (pad_field * MUX_PAD_BIT_LEN)); + __raw_writel(l, reg); + spin_unlock(&gpio_mux_lock); +} + +/* + * FIXED ME: for backward compatible. to be removed! + */ +void iomux_config_pad(iomux_pin_name_t pin, u32 config) +{ + mxc_iomux_set_pad(pin, config); +} + +/*! + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in \b #iomux_gp_func_t + * @param en \b #true to enable; \b #false to disable + */ +void mxc_iomux_set_gpr(iomux_gp_func_t gp, bool en) +{ + u32 l; + + spin_lock(&gpio_mux_lock); + l = __raw_readl(IOMUXGPR); + if (en) { + l |= gp; + } else { + l &= ~gp; + } + __raw_writel(l, IOMUXGPR); + spin_unlock(&gpio_mux_lock); +} + +/*! + * FIXED ME: for backward compatible. to be removed! + */ +void iomux_config_gpr(iomux_gp_func_t gp, bool en) +{ + mxc_iomux_set_gpr(gp, en); +} + +EXPORT_SYMBOL(mxc_request_iomux); +EXPORT_SYMBOL(mxc_free_iomux); +EXPORT_SYMBOL(mxc_iomux_set_pad); +EXPORT_SYMBOL(mxc_iomux_set_gpr); +EXPORT_SYMBOL(iomux_config_pad); +EXPORT_SYMBOL(iomux_config_gpr); +EXPORT_SYMBOL(iomux_config_mux); diff -urN linux-2.6.26/arch/arm/mach-mx3/iomux.h linux-2.6.26-lab126/arch/arm/mach-mx3/iomux.h --- linux-2.6.26/arch/arm/mach-mx3/iomux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/iomux.h 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,185 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MACH_MX31_IOMUX_H__ +#define __MACH_MX31_IOMUX_H__ + +#include +#include +#include "mx31_pins.h" + +/*! + * @file mach-mx3/iomux.h + * + * @brief I/O Muxing control definitions and functions + * + * @ingroup GPIO_MX31 + */ + +/*! + * various IOMUX output functions + */ +typedef enum iomux_output_config { + OUTPUTCONFIG_GPIO = 0, /*!< used as GPIO */ + OUTPUTCONFIG_FUNC, /*!< used as function */ + OUTPUTCONFIG_ALT1, /*!< used as alternate function 1 */ + OUTPUTCONFIG_ALT2, /*!< used as alternate function 2 */ + OUTPUTCONFIG_ALT3, /*!< used as alternate function 3 */ + OUTPUTCONFIG_ALT4, /*!< used as alternate function 4 */ + OUTPUTCONFIG_ALT5, /*!< used as alternate function 5 */ + OUTPUTCONFIG_ALT6 /*!< used as alternate function 6 */ +} iomux_pin_ocfg_t; + +/*! + * various IOMUX input functions + */ +typedef enum iomux_input_config { + INPUTCONFIG_NONE = 0, /*!< not configured for input */ + INPUTCONFIG_GPIO = 1 << 0, /*!< used as GPIO */ + INPUTCONFIG_FUNC = 1 << 1, /*!< used as function */ + INPUTCONFIG_ALT1 = 1 << 2, /*!< used as alternate function 1 */ + INPUTCONFIG_ALT2 = 1 << 3 /*!< used as alternate function 2 */ +} iomux_pin_icfg_t; + +/*! + * various IOMUX pad functions + */ +typedef enum iomux_pad_config { + PAD_CTL_NOLOOPBACK = 0x0 << 9, + PAD_CTL_LOOPBACK = 0x1 << 9, + PAD_CTL_PKE_NONE = 0x0 << 8, + PAD_CTL_PKE_ENABLE = 0x1 << 8, + PAD_CTL_PUE_KEEPER = 0x0 << 7, + PAD_CTL_PUE_PUD = 0x1 << 7, + PAD_CTL_100K_PD = 0x0 << 5, + PAD_CTL_100K_PU = 0x1 << 5, + PAD_CTL_47K_PU = 0x2 << 5, + PAD_CTL_22K_PU = 0x3 << 5, + PAD_CTL_HYS_CMOS = 0x0 << 4, + PAD_CTL_HYS_SCHMITZ = 0x1 << 4, + PAD_CTL_ODE_CMOS = 0x0 << 3, + PAD_CTL_ODE_OpenDrain = 0x1 << 3, + PAD_CTL_DRV_NORMAL = 0x0 << 1, + PAD_CTL_DRV_HIGH = 0x1 << 1, + PAD_CTL_DRV_MAX = 0x2 << 1, + PAD_CTL_SRE_SLOW = 0x0 << 0, + PAD_CTL_SRE_FAST = 0x1 << 0 +} iomux_pad_config_t; + +/*! + * various IOMUX general purpose functions + */ +typedef enum iomux_gp_func { + MUX_PGP_FIRI = 0x1 << 0, + MUX_DDR_MODE = 0x1 << 1, + MUX_PGP_CSPI_BB = 0x1 << 2, + MUX_PGP_ATA_1 = 0x1 << 3, + MUX_PGP_ATA_2 = 0x1 << 4, + MUX_PGP_ATA_3 = 0x1 << 5, + MUX_PGP_ATA_4 = 0x1 << 6, + MUX_PGP_ATA_5 = 0x1 << 7, + MUX_PGP_ATA_6 = 0x1 << 8, + MUX_PGP_ATA_7 = 0x1 << 9, + MUX_PGP_ATA_8 = 0x1 << 10, + MUX_PGP_UH2 = 0x1 << 11, + MUX_SDCTL_CSD0_SEL = 0x1 << 12, + MUX_SDCTL_CSD1_SEL = 0x1 << 13, + MUX_CSPI1_UART3 = 0x1 << 14, + MUX_EXTDMAREQ2_MBX_SEL = 0x1 << 15, + MUX_TAMPER_DETECT_EN = 0x1 << 16, + MUX_PGP_USB_4WIRE = 0x1 << 17, + MUX_PGB_USB_COMMON = 0x1 << 18, + MUX_SDHC_MEMSTICK1 = 0x1 << 19, + MUX_SDHC_MEMSTICK2 = 0x1 << 20, + MUX_PGP_SPLL_BYP = 0x1 << 21, + MUX_PGP_UPLL_BYP = 0x1 << 22, + MUX_PGP_MSHC1_CLK_SEL = 0x1 << 23, + MUX_PGP_MSHC2_CLK_SEL = 0x1 << 24, + MUX_CSPI3_UART5_SEL = 0x1 << 25, + MUX_PGP_ATA_9 = 0x1 << 26, + MUX_PGP_USB_SUSPEND = 0x1 << 27, + MUX_PGP_USB_OTG_LOOPBACK = 0x1 << 28, + MUX_PGP_USB_HS1_LOOPBACK = 0x1 << 29, + MUX_PGP_USB_HS2_LOOPBACK = 0x1 << 30, + MUX_CLKO_DDR_MODE = 0x1 << 31, +} iomux_gp_func_t; + +/*! + * This function is used to configure a pin through the IOMUX module. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param out an output function as defined in \b #iomux_pin_ocfg_t + * @param in an input function as defined in \b #iomux_pin_icfg_t + * @return 0 if successful; Non-zero otherwise + */ +int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_ocfg_t out, + iomux_pin_icfg_t in); + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pins + * @param config ORed value of elements defined in \b #iomux_pad_config_t + */ +void iomux_config_pad(iomux_pin_name_t pin, __u32 config); + +/*! + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in \b #iomux_gp_func_t + * @param en \b #true to enable; \b #false to disable + */ +void iomux_config_gpr(iomux_gp_func_t gp, bool en); + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param out an output function as defined in \b #iomux_pin_ocfg_t + * @param in an input function as defined in \b #iomux_pin_icfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_ocfg_t out, + iomux_pin_icfg_t in); + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param out an output function as defined in \b #iomux_pin_ocfg_t + * @param in an input function as defined in \b #iomux_pin_icfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_ocfg_t out, + iomux_pin_icfg_t in); + +/*! + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in \b #iomux_gp_func_t + * @param en \b #true to enable; \b #false to disable + */ +void mxc_iomux_set_gpr(iomux_gp_func_t gp, bool en); + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); + +#endif diff -urN linux-2.6.26/arch/arm/mach-mx3/mm.c linux-2.6.26-lab126/arch/arm/mach-mx3/mm.c --- linux-2.6.26/arch/arm/mach-mx3/mm.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/mm.c 2010-08-10 04:14:16.000000000 -0400 @@ -28,11 +28,11 @@ #include /*! - * @file mm.c + * @file mach-mx3/mm.c * * @brief This file creates static virtual to physical mappings, common to all MX3 boards. * - * @ingroup Memory + * @ingroup Memory_MX31 */ /*! @@ -41,16 +41,40 @@ */ static struct map_desc mxc_io_desc[] __initdata = { { - .virtual = X_MEMC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR), - .length = X_MEMC_SIZE, - .type = MT_DEVICE - }, { - .virtual = AVIC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(AVIC_BASE_ADDR), - .length = AVIC_SIZE, - .type = MT_NONSHARED_DEVICE - }, + .virtual = IRAM_BASE_ADDR_VIRT & 0xFFF00000, + .pfn = __phys_to_pfn(IRAM_BASE_ADDR & 0xFFF00000), + .length = SZ_1M, + .type = MT_NONSHARED_DEVICE}, + { + .virtual = X_MEMC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR), + .length = X_MEMC_SIZE, + .type = MT_DEVICE}, + { + .virtual = AVIC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AVIC_BASE_ADDR), + .length = AVIC_SIZE, + .type = MT_NONSHARED_DEVICE}, + { + .virtual = AIPS1_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), + .length = AIPS1_SIZE, + .type = MT_NONSHARED_DEVICE}, + { + .virtual = SPBA0_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), + .length = SPBA0_SIZE, + .type = MT_NONSHARED_DEVICE}, + { + .virtual = AIPS2_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), + .length = AIPS2_SIZE, + .type = MT_NONSHARED_DEVICE}, + { + .virtual = CS4_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(CS4_BASE_ADDR), + .length = CS4_SIZE, + .type = MT_DEVICE}, }; /*! diff -urN linux-2.6.26/arch/arm/mach-mx3/mx31_pins.h linux-2.6.26-lab126/arch/arm/mach-mx3/mx31_pins.h --- linux-2.6.26/arch/arm/mach-mx3/mx31_pins.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/mx31_pins.h 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,429 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_MX31_PINS_H__ +#define __ASM_ARCH_MXC_MX31_PINS_H__ + +/*! + * @file arch-mxc/mx31_pins.h + * + * @brief MX31 I/O Pin List + * + * @ingroup GPIO_MX31 + */ + +#ifndef __ASSEMBLY__ + +/*! + * @name IOMUX/PAD Bit field definitions + */ + +/*! @{ */ + +/*! + * In order to identify pins more effectively, each mux-controlled pin's + * enumerated value is constructed in the following way: + * + * ------------------------------------------------------------------- + * 31-29 | 28 - 24 |23 - 21| 20 | 19 - 18 | 17 - 10| 9 - 8 | 7 - 0 + * ------------------------------------------------------------------- + * IO_P | IO_I | RSVD | PAD_F | PAD_I | MUX_F | MUX_I + * ------------------------------------------------------------------- + * + * Bit 0 to 7 contains MUX_I used to identify the register + * offset (0-based. base is IOMUX_module_base + 0xC) defined in the Section + * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. Bit 8 to 9 is MUX_F which + * contains the offset value defined WITHIN the same register (each IOMUX + * control register contains four 8-bit fields for four different pins). The + * similar field definitions are used for the pad control register. + * For example, the MX31_PIN_A0 is defined in the enumeration: + * ( 73 << MUX_I) | (0 << MUX_F)|( 98 << PAD_I) | (0 << PAD_F) + * It means the mux control register is at register offset 73. So the absolute + * address is: 0xC+73*4=0x130 0 << MUX_F means the control bits are at the + * least significant bits within the register. The pad control register offset + * is: 0x154+98*4=0x2DC and also occupy the least significant bits within the + * register. + */ + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * MUX control register index (0-based) + */ +#define MUX_I 0 + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * field within IOMUX control register for control bits + * (legal values are 0, 1, 2, 3) + */ +#define MUX_F 8 + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * PAD control register index (0-based) + */ +#define PAD_I 10 + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * field within PAD control register for control bits + * (legal values are 0, 1, 2) + */ +#define PAD_F 18 + +#define _MXC_BUILD_PIN(gp,gi,mi,mf,pi,pf) \ + ((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | ((mi) << MUX_I) | \ + ((mf) << MUX_F) | ((pi) << PAD_I) | ((pf) << PAD_F) + +#define _MXC_BUILD_GPIO_PIN(gp,gi,mi,mf,pi,pf) \ + _MXC_BUILD_PIN(gp,gi,mi,mf,pi,pf) +#define _MXC_BUILD_NON_GPIO_PIN(mi,mf,pi,pf) \ + _MXC_BUILD_PIN(7,0,mi,mf,pi,pf) + +/*! + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ +enum iomux_pins { + MX31_PIN_CSPI3_MISO = _MXC_BUILD_NON_GPIO_PIN(0, 3, 1, 2), + MX31_PIN_CSPI3_SCLK = _MXC_BUILD_NON_GPIO_PIN(0, 2, 1, 1), + MX31_PIN_CSPI3_SPI_RDY = _MXC_BUILD_NON_GPIO_PIN(0, 1, 1, 0), + MX31_PIN_TTM_PAD = _MXC_BUILD_NON_GPIO_PIN(0, 0, 0, 2), + MX31_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(2, 31, 1, 3, 3, 0), + MX31_PIN_CE_CONTROL = _MXC_BUILD_NON_GPIO_PIN(1, 2, 2, 2), + MX31_PIN_CLKSS = _MXC_BUILD_NON_GPIO_PIN(1, 1, 2, 1), + MX31_PIN_CSPI3_MOSI = _MXC_BUILD_NON_GPIO_PIN(1, 0, 2, 0), + MX31_PIN_ATA_CS1 = _MXC_BUILD_GPIO_PIN(2, 27, 2, 3, 4, 1), + MX31_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(2, 28, 2, 2, 4, 0), + MX31_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(2, 29, 2, 1, 3, 2), + MX31_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(2, 30, 2, 0, 3, 1), + MX31_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(1, 29, 3, 3, 5, 2), + MX31_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(1, 30, 3, 2, 5, 1), + MX31_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(1, 31, 3, 1, 5, 0), + MX31_PIN_ATA_CS0 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0, 4, 2), + MX31_PIN_D3_SPL = _MXC_BUILD_NON_GPIO_PIN(4, 3, 7, 0), + MX31_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(1, 26, 4, 2, 6, 2), + MX31_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(1, 27, 4, 1, 6, 1), + MX31_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(1, 28, 4, 0, 6, 0), + MX31_PIN_VSYNC3 = _MXC_BUILD_NON_GPIO_PIN(5, 3, 8, 1), + MX31_PIN_CONTRAST = _MXC_BUILD_NON_GPIO_PIN(5, 2, 8, 0), + MX31_PIN_D3_REV = _MXC_BUILD_NON_GPIO_PIN(5, 1, 7, 2), + MX31_PIN_D3_CLS = _MXC_BUILD_NON_GPIO_PIN(5, 0, 7, 1), + MX31_PIN_SER_RS = _MXC_BUILD_GPIO_PIN(2, 25, 6, 3, 9, 2), + MX31_PIN_PAR_RS = _MXC_BUILD_NON_GPIO_PIN(6, 2, 9, 1), + MX31_PIN_WRITE = _MXC_BUILD_NON_GPIO_PIN(6, 1, 9, 0), + MX31_PIN_READ = _MXC_BUILD_NON_GPIO_PIN(6, 0, 8, 2), + MX31_PIN_SD_D_IO = _MXC_BUILD_GPIO_PIN(2, 21, 7, 3, 11, 0), + MX31_PIN_SD_D_CLK = _MXC_BUILD_GPIO_PIN(2, 22, 7, 2, 10, 2), + MX31_PIN_LCS0 = _MXC_BUILD_GPIO_PIN(2, 23, 7, 1, 10, 1), + MX31_PIN_LCS1 = _MXC_BUILD_GPIO_PIN(2, 24, 7, 0, 10, 0), + MX31_PIN_HSYNC = _MXC_BUILD_NON_GPIO_PIN(8, 3, 12, 1), + MX31_PIN_FPSHIFT = _MXC_BUILD_NON_GPIO_PIN(8, 2, 12, 0), + MX31_PIN_DRDY0 = _MXC_BUILD_NON_GPIO_PIN(8, 1, 11, 2), + MX31_PIN_SD_D_I = _MXC_BUILD_GPIO_PIN(2, 20, 8, 0, 11, 1), + MX31_PIN_LD15 = _MXC_BUILD_NON_GPIO_PIN(9, 3, 13, 2), + MX31_PIN_LD16 = _MXC_BUILD_NON_GPIO_PIN(9, 2, 13, 1), + MX31_PIN_LD17 = _MXC_BUILD_NON_GPIO_PIN(9, 1, 13, 0), + MX31_PIN_VSYNC0 = _MXC_BUILD_NON_GPIO_PIN(9, 0, 12, 2), + MX31_PIN_LD11 = _MXC_BUILD_NON_GPIO_PIN(10, 3, 15, 0), + MX31_PIN_LD12 = _MXC_BUILD_NON_GPIO_PIN(10, 2, 14, 2), + MX31_PIN_LD13 = _MXC_BUILD_NON_GPIO_PIN(10, 1, 14, 1), + MX31_PIN_LD14 = _MXC_BUILD_NON_GPIO_PIN(10, 0, 14, 0), + MX31_PIN_LD7 = _MXC_BUILD_NON_GPIO_PIN(11, 3, 16, 1), + MX31_PIN_LD8 = _MXC_BUILD_NON_GPIO_PIN(11, 2, 16, 0), + MX31_PIN_LD9 = _MXC_BUILD_NON_GPIO_PIN(11, 1, 15, 2), + MX31_PIN_LD10 = _MXC_BUILD_NON_GPIO_PIN(11, 0, 15, 1), + MX31_PIN_LD3 = _MXC_BUILD_NON_GPIO_PIN(12, 3, 17, 2), + MX31_PIN_LD4 = _MXC_BUILD_NON_GPIO_PIN(12, 2, 17, 1), + MX31_PIN_LD5 = _MXC_BUILD_NON_GPIO_PIN(12, 1, 17, 0), + MX31_PIN_LD6 = _MXC_BUILD_NON_GPIO_PIN(12, 0, 16, 2), + MX31_PIN_USBH2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(13, 3, 19, 0), + MX31_PIN_LD0 = _MXC_BUILD_NON_GPIO_PIN(13, 2, 18, 2), + MX31_PIN_LD1 = _MXC_BUILD_NON_GPIO_PIN(13, 1, 18, 1), + MX31_PIN_LD2 = _MXC_BUILD_NON_GPIO_PIN(13, 0, 18, 0), + MX31_PIN_USBH2_DIR = _MXC_BUILD_NON_GPIO_PIN(14, 3, 20, 1), + MX31_PIN_USBH2_STP = _MXC_BUILD_NON_GPIO_PIN(14, 2, 20, 0), + MX31_PIN_USBH2_NXT = _MXC_BUILD_NON_GPIO_PIN(14, 1, 19, 2), + MX31_PIN_USBH2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(14, 0, 19, 1), + MX31_PIN_USBOTG_DATA5 = _MXC_BUILD_NON_GPIO_PIN(15, 3, 21, 2), + MX31_PIN_USBOTG_DATA6 = _MXC_BUILD_NON_GPIO_PIN(15, 2, 21, 1), + MX31_PIN_USBOTG_DATA7 = _MXC_BUILD_NON_GPIO_PIN(15, 1, 21, 0), + MX31_PIN_USBH2_CLK = _MXC_BUILD_NON_GPIO_PIN(15, 0, 20, 2), + MX31_PIN_USBOTG_DATA1 = _MXC_BUILD_NON_GPIO_PIN(16, 3, 23, 0), + MX31_PIN_USBOTG_DATA2 = _MXC_BUILD_NON_GPIO_PIN(16, 2, 22, 2), + MX31_PIN_USBOTG_DATA3 = _MXC_BUILD_NON_GPIO_PIN(16, 1, 22, 1), + MX31_PIN_USBOTG_DATA4 = _MXC_BUILD_NON_GPIO_PIN(16, 0, 22, 0), + MX31_PIN_USBOTG_DIR = _MXC_BUILD_NON_GPIO_PIN(17, 3, 24, 1), + MX31_PIN_USBOTG_STP = _MXC_BUILD_NON_GPIO_PIN(17, 2, 24, 0), + MX31_PIN_USBOTG_NXT = _MXC_BUILD_NON_GPIO_PIN(17, 1, 23, 2), + MX31_PIN_USBOTG_DATA0 = _MXC_BUILD_NON_GPIO_PIN(17, 0, 23, 1), + MX31_PIN_USB_PWR = _MXC_BUILD_GPIO_PIN(0, 29, 18, 3, 25, 2), + MX31_PIN_USB_OC = _MXC_BUILD_GPIO_PIN(0, 30, 18, 2, 25, 1), + MX31_PIN_USB_BYP = _MXC_BUILD_GPIO_PIN(0, 31, 18, 1, 25, 0), + MX31_PIN_USBOTG_CLK = _MXC_BUILD_NON_GPIO_PIN(18, 0, 24, 2), + MX31_PIN_TDO = _MXC_BUILD_NON_GPIO_PIN(19, 3, 27, 0), + MX31_PIN_TRSTB = _MXC_BUILD_NON_GPIO_PIN(19, 2, 26, 2), + MX31_PIN_DE_B = _MXC_BUILD_NON_GPIO_PIN(19, 1, 26, 1), + MX31_PIN_SJC_MOD = _MXC_BUILD_NON_GPIO_PIN(19, 0, 26, 0), + MX31_PIN_RTCK = _MXC_BUILD_NON_GPIO_PIN(20, 3, 28, 1), + MX31_PIN_TCK = _MXC_BUILD_NON_GPIO_PIN(20, 2, 28, 0), + MX31_PIN_TMS = _MXC_BUILD_NON_GPIO_PIN(20, 1, 27, 2), + MX31_PIN_TDI = _MXC_BUILD_NON_GPIO_PIN(20, 0, 27, 1), + MX31_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN(1, 22, 21, 3, 29, 2), + MX31_PIN_KEY_COL5 = _MXC_BUILD_GPIO_PIN(1, 23, 21, 2, 29, 1), + MX31_PIN_KEY_COL6 = _MXC_BUILD_GPIO_PIN(1, 24, 21, 1, 29, 0), + MX31_PIN_KEY_COL7 = _MXC_BUILD_GPIO_PIN(1, 25, 21, 0, 28, 2), + MX31_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(22, 3, 31, 0), + MX31_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(22, 2, 30, 2), + MX31_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(22, 1, 30, 1), + MX31_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(22, 0, 30, 0), + MX31_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN(1, 18, 23, 3, 32, 1), + MX31_PIN_KEY_ROW5 = _MXC_BUILD_GPIO_PIN(1, 19, 23, 2, 32, 0), + MX31_PIN_KEY_ROW6 = _MXC_BUILD_GPIO_PIN(1, 20, 23, 1, 31, 2), + MX31_PIN_KEY_ROW7 = _MXC_BUILD_GPIO_PIN(1, 21, 23, 0, 31, 1), + MX31_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(24, 3, 33, 2), + MX31_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(24, 2, 33, 1), + MX31_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(24, 1, 33, 0), + MX31_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(24, 0, 32, 2), + MX31_PIN_TXD2 = _MXC_BUILD_GPIO_PIN(0, 28, 25, 3, 35, 0), + MX31_PIN_RTS2 = _MXC_BUILD_NON_GPIO_PIN(25, 2, 34, 2), + MX31_PIN_CTS2 = _MXC_BUILD_NON_GPIO_PIN(25, 1, 34, 1), + MX31_PIN_BATT_LINE = _MXC_BUILD_GPIO_PIN(1, 17, 25, 0, 34, 0), + MX31_PIN_RI_DTE1 = _MXC_BUILD_GPIO_PIN(1, 14, 26, 3, 36, 1), + MX31_PIN_DCD_DTE1 = _MXC_BUILD_GPIO_PIN(1, 15, 26, 2, 36, 0), + MX31_PIN_DTR_DCE2 = _MXC_BUILD_GPIO_PIN(1, 16, 26, 1, 35, 2), + MX31_PIN_RXD2 = _MXC_BUILD_GPIO_PIN(0, 27, 26, 0, 35, 1), + MX31_PIN_RI_DCE1 = _MXC_BUILD_GPIO_PIN(1, 10, 27, 3, 37, 2), + MX31_PIN_DCD_DCE1 = _MXC_BUILD_GPIO_PIN(1, 11, 27, 2, 37, 1), + MX31_PIN_DTR_DTE1 = _MXC_BUILD_GPIO_PIN(1, 12, 27, 1, 37, 0), + MX31_PIN_DSR_DTE1 = _MXC_BUILD_GPIO_PIN(1, 13, 27, 0, 36, 2), + MX31_PIN_RTS1 = _MXC_BUILD_GPIO_PIN(1, 6, 28, 3, 39, 0), + MX31_PIN_CTS1 = _MXC_BUILD_GPIO_PIN(1, 7, 28, 2, 38, 2), + MX31_PIN_DTR_DCE1 = _MXC_BUILD_GPIO_PIN(1, 8, 28, 1, 38, 1), + MX31_PIN_DSR_DCE1 = _MXC_BUILD_GPIO_PIN(1, 9, 28, 0, 38, 0), + MX31_PIN_CSPI2_SCLK = _MXC_BUILD_NON_GPIO_PIN(29, 3, 40, 1), + MX31_PIN_CSPI2_SPI_RDY = _MXC_BUILD_NON_GPIO_PIN(29, 2, 40, 0), + MX31_PIN_RXD1 = _MXC_BUILD_GPIO_PIN(1, 4, 29, 1, 39, 2), + MX31_PIN_TXD1 = _MXC_BUILD_GPIO_PIN(1, 5, 29, 0, 39, 1), + MX31_PIN_CSPI2_MISO = _MXC_BUILD_NON_GPIO_PIN(30, 3, 41, 2), + MX31_PIN_CSPI2_SS0 = _MXC_BUILD_NON_GPIO_PIN(30, 2, 41, 1), + MX31_PIN_CSPI2_SS1 = _MXC_BUILD_NON_GPIO_PIN(30, 1, 41, 0), + MX31_PIN_CSPI2_SS2 = _MXC_BUILD_NON_GPIO_PIN(30, 0, 40, 2), + MX31_PIN_CSPI1_SS2 = _MXC_BUILD_NON_GPIO_PIN(31, 3, 43, 0), + MX31_PIN_CSPI1_SCLK = _MXC_BUILD_NON_GPIO_PIN(31, 2, 42, 2), + MX31_PIN_CSPI1_SPI_RDY = _MXC_BUILD_NON_GPIO_PIN(31, 1, 42, 1), + MX31_PIN_CSPI2_MOSI = _MXC_BUILD_NON_GPIO_PIN(31, 0, 42, 0), + MX31_PIN_CSPI1_MOSI = _MXC_BUILD_NON_GPIO_PIN(32, 3, 44, 1), + MX31_PIN_CSPI1_MISO = _MXC_BUILD_NON_GPIO_PIN(32, 2, 44, 0), + MX31_PIN_CSPI1_SS0 = _MXC_BUILD_NON_GPIO_PIN(32, 1, 43, 2), + MX31_PIN_CSPI1_SS1 = _MXC_BUILD_NON_GPIO_PIN(32, 0, 43, 1), + MX31_PIN_STXD6 = _MXC_BUILD_GPIO_PIN(0, 23, 33, 3, 45, 2), + MX31_PIN_SRXD6 = _MXC_BUILD_GPIO_PIN(0, 24, 33, 2, 45, 1), + MX31_PIN_SCK6 = _MXC_BUILD_GPIO_PIN(0, 25, 33, 1, 45, 0), + MX31_PIN_SFS6 = _MXC_BUILD_GPIO_PIN(0, 26, 33, 0, 44, 2), + MX31_PIN_STXD5 = _MXC_BUILD_GPIO_PIN(0, 21, 34, 3, 47, 0), + MX31_PIN_SRXD5 = _MXC_BUILD_GPIO_PIN(0, 22, 34, 2, 46, 2), + MX31_PIN_SCK5 = _MXC_BUILD_NON_GPIO_PIN(34, 1, 46, 1), + MX31_PIN_SFS5 = _MXC_BUILD_NON_GPIO_PIN(34, 0, 46, 0), + MX31_PIN_STXD4 = _MXC_BUILD_GPIO_PIN(0, 19, 35, 3, 48, 1), + MX31_PIN_SRXD4 = _MXC_BUILD_GPIO_PIN(0, 20, 35, 2, 48, 0), + MX31_PIN_SCK4 = _MXC_BUILD_NON_GPIO_PIN(35, 1, 47, 2), + MX31_PIN_SFS4 = _MXC_BUILD_NON_GPIO_PIN(35, 0, 47, 1), + MX31_PIN_STXD3 = _MXC_BUILD_GPIO_PIN(0, 17, 36, 3, 49, 2), + MX31_PIN_SRXD3 = _MXC_BUILD_GPIO_PIN(0, 18, 36, 2, 49, 1), + MX31_PIN_SCK3 = _MXC_BUILD_NON_GPIO_PIN(36, 1, 49, 0), + MX31_PIN_SFS3 = _MXC_BUILD_NON_GPIO_PIN(36, 0, 48, 2), + MX31_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(2, 18, 37, 3, 51, 0), + MX31_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(2, 19, 37, 2, 50, 2), + MX31_PIN_I2C_CLK = _MXC_BUILD_NON_GPIO_PIN(37, 1, 50, 1), + MX31_PIN_I2C_DAT = _MXC_BUILD_NON_GPIO_PIN(37, 0, 50, 0), + MX31_PIN_CSI_D14 = _MXC_BUILD_GPIO_PIN(2, 14, 38, 3, 52, 1), + MX31_PIN_CSI_D15 = _MXC_BUILD_GPIO_PIN(2, 15, 38, 2, 52, 0), + MX31_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(2, 16, 38, 1, 51, 2), + MX31_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(2, 17, 38, 0, 51, 1), + MX31_PIN_CSI_D10 = _MXC_BUILD_GPIO_PIN(2, 10, 39, 3, 53, 2), + MX31_PIN_CSI_D11 = _MXC_BUILD_GPIO_PIN(2, 11, 39, 2, 53, 1), + MX31_PIN_CSI_D12 = _MXC_BUILD_GPIO_PIN(2, 12, 39, 1, 53, 0), + MX31_PIN_CSI_D13 = _MXC_BUILD_GPIO_PIN(2, 13, 39, 0, 52, 2), + MX31_PIN_CSI_D6 = _MXC_BUILD_GPIO_PIN(2, 6, 40, 3, 55, 0), + MX31_PIN_CSI_D7 = _MXC_BUILD_GPIO_PIN(2, 7, 40, 2, 54, 2), + MX31_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(2, 8, 40, 1, 54, 1), + MX31_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(2, 9, 40, 0, 54, 0), + MX31_PIN_M_REQUEST = _MXC_BUILD_NON_GPIO_PIN(41, 3, 56, 1), + MX31_PIN_M_GRANT = _MXC_BUILD_NON_GPIO_PIN(41, 2, 56, 0), + MX31_PIN_CSI_D4 = _MXC_BUILD_GPIO_PIN(2, 4, 41, 1, 55, 2), + MX31_PIN_CSI_D5 = _MXC_BUILD_GPIO_PIN(2, 5, 41, 0, 55, 1), + MX31_PIN_PC_RST = _MXC_BUILD_NON_GPIO_PIN(42, 3, 57, 2), + MX31_PIN_IOIS16 = _MXC_BUILD_NON_GPIO_PIN(42, 2, 57, 1), + MX31_PIN_PC_RW_B = _MXC_BUILD_NON_GPIO_PIN(42, 1, 57, 0), + MX31_PIN_PC_POE = _MXC_BUILD_NON_GPIO_PIN(42, 0, 56, 2), + MX31_PIN_PC_VS1 = _MXC_BUILD_NON_GPIO_PIN(43, 3, 59, 0), + MX31_PIN_PC_VS2 = _MXC_BUILD_NON_GPIO_PIN(43, 2, 58, 2), + MX31_PIN_PC_BVD1 = _MXC_BUILD_NON_GPIO_PIN(43, 1, 58, 1), + MX31_PIN_PC_BVD2 = _MXC_BUILD_NON_GPIO_PIN(43, 0, 58, 0), + MX31_PIN_PC_CD2_B = _MXC_BUILD_NON_GPIO_PIN(44, 3, 60, 1), + MX31_PIN_PC_WAIT_B = _MXC_BUILD_NON_GPIO_PIN(44, 2, 60, 0), + MX31_PIN_PC_READY = _MXC_BUILD_NON_GPIO_PIN(44, 1, 59, 2), + MX31_PIN_PC_PWRON = _MXC_BUILD_NON_GPIO_PIN(44, 0, 59, 1), + MX31_PIN_D2 = _MXC_BUILD_NON_GPIO_PIN(45, 3, 61, 2), + MX31_PIN_D1 = _MXC_BUILD_NON_GPIO_PIN(45, 2, 61, 1), + MX31_PIN_D0 = _MXC_BUILD_NON_GPIO_PIN(45, 1, 61, 0), + MX31_PIN_PC_CD1_B = _MXC_BUILD_NON_GPIO_PIN(45, 0, 60, 2), + MX31_PIN_D6 = _MXC_BUILD_NON_GPIO_PIN(46, 3, 63, 0), + MX31_PIN_D5 = _MXC_BUILD_NON_GPIO_PIN(46, 2, 62, 2), + MX31_PIN_D4 = _MXC_BUILD_NON_GPIO_PIN(46, 1, 62, 1), + MX31_PIN_D3 = _MXC_BUILD_NON_GPIO_PIN(46, 0, 62, 0), + MX31_PIN_D10 = _MXC_BUILD_NON_GPIO_PIN(47, 3, 64, 1), + MX31_PIN_D9 = _MXC_BUILD_NON_GPIO_PIN(47, 2, 64, 0), + MX31_PIN_D8 = _MXC_BUILD_NON_GPIO_PIN(47, 1, 63, 2), + MX31_PIN_D7 = _MXC_BUILD_NON_GPIO_PIN(47, 0, 63, 1), + MX31_PIN_D14 = _MXC_BUILD_NON_GPIO_PIN(48, 3, 65, 2), + MX31_PIN_D13 = _MXC_BUILD_NON_GPIO_PIN(48, 2, 65, 1), + MX31_PIN_D12 = _MXC_BUILD_NON_GPIO_PIN(48, 1, 65, 0), + MX31_PIN_D11 = _MXC_BUILD_NON_GPIO_PIN(48, 0, 64, 2), + MX31_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(0, 14, 49, 3, 67, 0), + MX31_PIN_NFCE_B = _MXC_BUILD_GPIO_PIN(0, 15, 49, 2, 66, 2), + MX31_PIN_NFRB = _MXC_BUILD_GPIO_PIN(0, 16, 49, 1, 66, 1), + MX31_PIN_D15 = _MXC_BUILD_NON_GPIO_PIN(49, 0, 66, 0), + MX31_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(0, 10, 50, 3, 68, 1), + MX31_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(0, 11, 50, 2, 68, 0), + MX31_PIN_NFALE = _MXC_BUILD_GPIO_PIN(0, 12, 50, 1, 67, 2), + MX31_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(0, 13, 50, 0, 67, 1), + MX31_PIN_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(51, 3, 69, 2), + MX31_PIN_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(51, 2, 69, 1), + MX31_PIN_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(51, 1, 69, 0), + MX31_PIN_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(51, 0, 68, 2), + MX31_PIN_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(52, 3, 71, 0), + MX31_PIN_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(52, 2, 70, 2), + MX31_PIN_SDCLK = _MXC_BUILD_NON_GPIO_PIN(52, 1, 70, 1), + MX31_PIN_SDCLK_B = _MXC_BUILD_NON_GPIO_PIN(52, 0, 70, 0), + MX31_PIN_RW = _MXC_BUILD_NON_GPIO_PIN(53, 3, 72, 1), + MX31_PIN_RAS = _MXC_BUILD_NON_GPIO_PIN(53, 2, 72, 0), + MX31_PIN_CAS = _MXC_BUILD_NON_GPIO_PIN(53, 1, 71, 2), + MX31_PIN_SDWE = _MXC_BUILD_NON_GPIO_PIN(53, 0, 71, 1), + MX31_PIN_CS5 = _MXC_BUILD_NON_GPIO_PIN(54, 3, 73, 2), + MX31_PIN_ECB = _MXC_BUILD_NON_GPIO_PIN(54, 2, 73, 1), + MX31_PIN_LBA = _MXC_BUILD_NON_GPIO_PIN(54, 1, 73, 0), + MX31_PIN_BCLK = _MXC_BUILD_NON_GPIO_PIN(54, 0, 72, 2), + MX31_PIN_CS1 = _MXC_BUILD_NON_GPIO_PIN(55, 3, 75, 0), + MX31_PIN_CS2 = _MXC_BUILD_NON_GPIO_PIN(55, 2, 74, 2), + MX31_PIN_CS3 = _MXC_BUILD_NON_GPIO_PIN(55, 1, 74, 1), + MX31_PIN_CS4 = _MXC_BUILD_NON_GPIO_PIN(55, 0, 74, 0), + MX31_PIN_EB0 = _MXC_BUILD_NON_GPIO_PIN(56, 3, 76, 1), + MX31_PIN_EB1 = _MXC_BUILD_NON_GPIO_PIN(56, 2, 76, 0), + MX31_PIN_OE = _MXC_BUILD_NON_GPIO_PIN(56, 1, 75, 2), + MX31_PIN_CS0 = _MXC_BUILD_NON_GPIO_PIN(56, 0, 75, 1), + MX31_PIN_DQM0 = _MXC_BUILD_NON_GPIO_PIN(57, 3, 77, 2), + MX31_PIN_DQM1 = _MXC_BUILD_NON_GPIO_PIN(57, 2, 77, 1), + MX31_PIN_DQM2 = _MXC_BUILD_NON_GPIO_PIN(57, 1, 77, 0), + MX31_PIN_DQM3 = _MXC_BUILD_NON_GPIO_PIN(57, 0, 76, 2), + MX31_PIN_SD28 = _MXC_BUILD_NON_GPIO_PIN(58, 3, 79, 0), + MX31_PIN_SD29 = _MXC_BUILD_NON_GPIO_PIN(58, 2, 78, 2), + MX31_PIN_SD30 = _MXC_BUILD_NON_GPIO_PIN(58, 1, 78, 1), + MX31_PIN_SD31 = _MXC_BUILD_NON_GPIO_PIN(58, 0, 78, 0), + MX31_PIN_SD24 = _MXC_BUILD_NON_GPIO_PIN(59, 3, 80, 1), + MX31_PIN_SD25 = _MXC_BUILD_NON_GPIO_PIN(59, 2, 80, 0), + MX31_PIN_SD26 = _MXC_BUILD_NON_GPIO_PIN(59, 1, 79, 2), + MX31_PIN_SD27 = _MXC_BUILD_NON_GPIO_PIN(59, 0, 79, 1), + MX31_PIN_SD20 = _MXC_BUILD_NON_GPIO_PIN(60, 3, 81, 2), + MX31_PIN_SD21 = _MXC_BUILD_NON_GPIO_PIN(60, 2, 81, 1), + MX31_PIN_SD22 = _MXC_BUILD_NON_GPIO_PIN(60, 1, 81, 0), + MX31_PIN_SD23 = _MXC_BUILD_NON_GPIO_PIN(60, 0, 80, 2), + MX31_PIN_SD16 = _MXC_BUILD_NON_GPIO_PIN(61, 3, 83, 0), + MX31_PIN_SD17 = _MXC_BUILD_NON_GPIO_PIN(61, 2, 82, 2), + MX31_PIN_SD18 = _MXC_BUILD_NON_GPIO_PIN(61, 1, 82, 1), + MX31_PIN_SD19 = _MXC_BUILD_NON_GPIO_PIN(61, 0, 82, 0), + MX31_PIN_SD12 = _MXC_BUILD_NON_GPIO_PIN(62, 3, 84, 1), + MX31_PIN_SD13 = _MXC_BUILD_NON_GPIO_PIN(62, 2, 84, 0), + MX31_PIN_SD14 = _MXC_BUILD_NON_GPIO_PIN(62, 1, 83, 2), + MX31_PIN_SD15 = _MXC_BUILD_NON_GPIO_PIN(62, 0, 83, 1), + MX31_PIN_SD8 = _MXC_BUILD_NON_GPIO_PIN(63, 3, 85, 2), + MX31_PIN_SD9 = _MXC_BUILD_NON_GPIO_PIN(63, 2, 85, 1), + MX31_PIN_SD10 = _MXC_BUILD_NON_GPIO_PIN(63, 1, 85, 0), + MX31_PIN_SD11 = _MXC_BUILD_NON_GPIO_PIN(63, 0, 84, 2), + MX31_PIN_SD4 = _MXC_BUILD_NON_GPIO_PIN(64, 3, 87, 0), + MX31_PIN_SD5 = _MXC_BUILD_NON_GPIO_PIN(64, 2, 86, 2), + MX31_PIN_SD6 = _MXC_BUILD_NON_GPIO_PIN(64, 1, 86, 1), + MX31_PIN_SD7 = _MXC_BUILD_NON_GPIO_PIN(64, 0, 86, 0), + MX31_PIN_SD0 = _MXC_BUILD_NON_GPIO_PIN(65, 3, 88, 1), + MX31_PIN_SD1 = _MXC_BUILD_NON_GPIO_PIN(65, 2, 88, 0), + MX31_PIN_SD2 = _MXC_BUILD_NON_GPIO_PIN(65, 1, 87, 2), + MX31_PIN_SD3 = _MXC_BUILD_NON_GPIO_PIN(65, 0, 87, 1), + MX31_PIN_A24 = _MXC_BUILD_NON_GPIO_PIN(66, 3, 89, 2), + MX31_PIN_A25 = _MXC_BUILD_NON_GPIO_PIN(66, 2, 89, 1), + MX31_PIN_SDBA1 = _MXC_BUILD_NON_GPIO_PIN(66, 1, 89, 0), + MX31_PIN_SDBA0 = _MXC_BUILD_NON_GPIO_PIN(66, 0, 88, 2), + MX31_PIN_A20 = _MXC_BUILD_NON_GPIO_PIN(67, 3, 91, 0), + MX31_PIN_A21 = _MXC_BUILD_NON_GPIO_PIN(67, 2, 90, 2), + MX31_PIN_A22 = _MXC_BUILD_NON_GPIO_PIN(67, 1, 90, 1), + MX31_PIN_A23 = _MXC_BUILD_NON_GPIO_PIN(67, 0, 90, 0), + MX31_PIN_A16 = _MXC_BUILD_NON_GPIO_PIN(68, 3, 92, 1), + MX31_PIN_A17 = _MXC_BUILD_NON_GPIO_PIN(68, 2, 92, 0), + MX31_PIN_A18 = _MXC_BUILD_NON_GPIO_PIN(68, 1, 91, 2), + MX31_PIN_A19 = _MXC_BUILD_NON_GPIO_PIN(68, 0, 91, 1), + MX31_PIN_A12 = _MXC_BUILD_NON_GPIO_PIN(69, 3, 93, 2), + MX31_PIN_A13 = _MXC_BUILD_NON_GPIO_PIN(69, 2, 93, 1), + MX31_PIN_A14 = _MXC_BUILD_NON_GPIO_PIN(69, 1, 93, 0), + MX31_PIN_A15 = _MXC_BUILD_NON_GPIO_PIN(69, 0, 92, 2), + MX31_PIN_A9 = _MXC_BUILD_NON_GPIO_PIN(70, 3, 95, 0), + MX31_PIN_A10 = _MXC_BUILD_NON_GPIO_PIN(70, 2, 94, 2), + MX31_PIN_MA10 = _MXC_BUILD_NON_GPIO_PIN(70, 1, 94, 1), + MX31_PIN_A11 = _MXC_BUILD_NON_GPIO_PIN(70, 0, 94, 0), + MX31_PIN_A5 = _MXC_BUILD_NON_GPIO_PIN(71, 3, 96, 1), + MX31_PIN_A6 = _MXC_BUILD_NON_GPIO_PIN(71, 2, 96, 0), + MX31_PIN_A7 = _MXC_BUILD_NON_GPIO_PIN(71, 1, 95, 2), + MX31_PIN_A8 = _MXC_BUILD_NON_GPIO_PIN(71, 0, 95, 1), + MX31_PIN_A1 = _MXC_BUILD_NON_GPIO_PIN(72, 3, 97, 2), + MX31_PIN_A2 = _MXC_BUILD_NON_GPIO_PIN(72, 2, 97, 1), + MX31_PIN_A3 = _MXC_BUILD_NON_GPIO_PIN(72, 1, 97, 0), + MX31_PIN_A4 = _MXC_BUILD_NON_GPIO_PIN(72, 0, 96, 2), + MX31_PIN_DVFS1 = _MXC_BUILD_NON_GPIO_PIN(73, 3, 99, 0), + MX31_PIN_VPG0 = _MXC_BUILD_NON_GPIO_PIN(73, 2, 98, 2), + MX31_PIN_VPG1 = _MXC_BUILD_NON_GPIO_PIN(73, 1, 98, 1), + MX31_PIN_A0 = _MXC_BUILD_NON_GPIO_PIN(73, 0, 98, 0), + MX31_PIN_CKIL = _MXC_BUILD_NON_GPIO_PIN(74, 3, 100, 1), + MX31_PIN_POWER_FAIL = _MXC_BUILD_NON_GPIO_PIN(74, 2, 100, 0), + MX31_PIN_VSTBY = _MXC_BUILD_NON_GPIO_PIN(74, 1, 99, 2), + MX31_PIN_DVFS0 = _MXC_BUILD_NON_GPIO_PIN(74, 0, 99, 1), + MX31_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(75, 3, 101, 2), + MX31_PIN_BOOT_MODE2 = _MXC_BUILD_NON_GPIO_PIN(75, 2, 101, 1), + MX31_PIN_BOOT_MODE3 = _MXC_BUILD_NON_GPIO_PIN(75, 1, 101, 0), + MX31_PIN_BOOT_MODE4 = _MXC_BUILD_NON_GPIO_PIN(75, 0, 100, 2), + MX31_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(76, 3, 103, 0), + MX31_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN(76, 2, 102, 2), + MX31_PIN_CLKO = _MXC_BUILD_NON_GPIO_PIN(76, 1, 102, 1), + MX31_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(76, 0, 102, 0), + MX31_PIN_STX0 = _MXC_BUILD_GPIO_PIN(1, 1, 77, 3, 104, 1), + MX31_PIN_SRX0 = _MXC_BUILD_GPIO_PIN(1, 2, 77, 2, 104, 0), + MX31_PIN_SIMPD0 = _MXC_BUILD_GPIO_PIN(1, 3, 77, 1, 103, 2), + MX31_PIN_CKIH = _MXC_BUILD_NON_GPIO_PIN(77, 0, 103, 1), + MX31_PIN_GPIO3_1 = _MXC_BUILD_GPIO_PIN(2, 1, 78, 3, 105, 2), + MX31_PIN_SCLK0 = _MXC_BUILD_GPIO_PIN(2, 2, 78, 2, 105, 1), + MX31_PIN_SRST0 = _MXC_BUILD_GPIO_PIN(2, 3, 78, 1, 105, 0), + MX31_PIN_SVEN0 = _MXC_BUILD_GPIO_PIN(1, 0, 78, 0, 104, 2), + MX31_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 79, 3, 107, 0), + MX31_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 79, 2, 106, 2), + MX31_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 79, 1, 106, 1), + MX31_PIN_GPIO3_0 = _MXC_BUILD_GPIO_PIN(2, 0, 79, 0, 106, 0), + MX31_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 80, 3, 108, 1), + MX31_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 80, 2, 108, 0), + MX31_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 80, 1, 107, 2), + MX31_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 80, 0, 107, 1), + MX31_PIN_CAPTURE = _MXC_BUILD_GPIO_PIN(0, 7, 81, 3, 109, 2), + MX31_PIN_COMPARE = _MXC_BUILD_GPIO_PIN(0, 8, 81, 2, 109, 1), + MX31_PIN_WATCHDOG_RST = _MXC_BUILD_NON_GPIO_PIN(81, 1, 109, 0), + MX31_PIN_PWMO = _MXC_BUILD_GPIO_PIN(0, 9, 81, 0, 108, 2), +}; + +#endif +#endif diff -urN linux-2.6.26/arch/arm/mach-mx3/mx31ads.c linux-2.6.26-lab126/arch/arm/mach-mx3/mx31ads.c --- linux-2.6.26/arch/arm/mach-mx3/mx31ads.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/mx31ads.c 2010-08-10 04:14:16.000000000 -0400 @@ -1,7 +1,7 @@ /* * Copyright (C) 2000 Deep Blue Solutions Ltd * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,56 +19,183 @@ */ #include +#include +#include #include -#include #include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE) +#include +#include +#include + +#include +#endif #include +#include +#include #include #include -#include -#include +#include +#include #include +#include +#include +#include +#include +#include "board-mx31ads.h" +#include "crm_regs.h" +#include "iomux.h" /*! - * @file mx31ads.c + * @file mach-mx3/mx31ads.c * * @brief This file contains the board-specific initialization routines. * - * @ingroup System + * @ingroup MSL_MX31 */ +extern void mxc_cpu_init(void) __init; +extern void mx31ads_gpio_init(void) __init; +extern void mxc_cpu_common_init(void); +extern int mxc_clocks_init(void); +extern void __init early_console_setup(char *); +extern int mxc_init_devices(void); + +static void mxc_nop_release(struct device *dev) +{ + /* Nothing */ +} + +unsigned long board_get_ckih_rate(void) +{ + if ((__raw_readw(PBC_BASE_ADDRESS + PBC_BSTAT) & + CKIH_27MHZ_BIT_SET) != 0) { + return 27000000; + } + return 26000000; +} + +#if defined(CONFIG_CS89x0) || defined(CONFIG_CS89x0_MODULE) +/*! Null terminated portlist used to probe for the CS8900A device on ISA Bus + * Add 3 to reset the page window before probing (fixes eth probe when deployed + * using nand_boot) + */ +unsigned int netcard_portlist[] = { CS8900A_BASE_ADDRESS + 3, 0 }; + +EXPORT_SYMBOL(netcard_portlist); +/*! + * The CS8900A has 4 IRQ pins, which is software selectable, CS8900A interrupt + * pin 0 is used for interrupt generation. + */ +unsigned int cs8900_irq_map[] = { CS8900AIRQ, 0, 0, 0 }; + +EXPORT_SYMBOL(cs8900_irq_map); +#endif + +#if defined(CONFIG_KEYBOARD_MXC) || defined(CONFIG_KEYBOARD_MXC_MODULE) + +/* Keypad keycodes for the EVB 8x8 + * keypad. POWER and PTT keys don't generate + * any interrupts via this driver so they are + * not support. Change any keys as u like! + */ +static u16 keymapping[64] = { + KEY_SELECT, KEY_LEFT, KEY_DOWN, KEY_RIGHT, + KEY_UP, KEY_F12, KEY_END, KEY_BACK, + KEY_F1, KEY_SENDFILE, KEY_HOME, KEY_F6, + KEY_VOLUMEUP, KEY_F8, KEY_F9, KEY_F10, + KEY_3, KEY_2, KEY_1, KEY_4, + KEY_VOLUMEDOWN, KEY_7, KEY_5, KEY_6, + KEY_9, KEY_LEFTSHIFT, KEY_8, KEY_0, + KEY_KPASTERISK, KEY_RECORD, KEY_Q, KEY_W, + KEY_A, KEY_S, KEY_D, KEY_E, + KEY_F, KEY_R, KEY_T, KEY_Y, + KEY_TAB, KEY_F7, KEY_CAPSLOCK, KEY_Z, + KEY_X, KEY_C, KEY_V, KEY_G, + KEY_B, KEY_H, KEY_N, KEY_M, + KEY_J, KEY_K, KEY_U, KEY_I, + KEY_SPACE, KEY_F2, KEY_DOT, KEY_ENTER, + KEY_L, KEY_BACKSPACE, KEY_P, KEY_O, +}; + +static struct resource mxc_kpp_resources[] = { + [0] = { + .start = MXC_INT_KPP, + .end = MXC_INT_KPP, + .flags = IORESOURCE_IRQ, + } +}; + +static struct keypad_data evb_8_by_8_keypad = { + .rowmax = 8, + .colmax = 8, + .irq = MXC_INT_KPP, + .learning = 0, + .delay = 2, + .matrix = keymapping, +}; + +/* mxc keypad driver */ +static struct platform_device mxc_keypad_device = { + .name = "mxc_keypad", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_kpp_resources), + .resource = mxc_kpp_resources, + .dev = { + .release = mxc_nop_release, + .platform_data = &evb_8_by_8_keypad, + }, +}; + +static void mxc_init_keypad(void) +{ + (void)platform_device_register(&mxc_keypad_device); +} +#else +static inline void mxc_init_keypad(void) +{ +} +#endif + #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) /*! * The serial port definition structure. */ static struct plat_serial8250_port serial_platform_data[] = { { - .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA), - .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTA), - .irq = EXPIO_INT_XUART_INTA, - .uartclk = 14745600, - .regshift = 0, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ, - }, { - .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB), - .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTB), - .irq = EXPIO_INT_XUART_INTB, - .uartclk = 14745600, - .regshift = 0, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ, - }, + .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA), + .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTA), + .irq = EXPIO_INT_XUART_INTA, + .uartclk = 14745600, + .regshift = 0, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,}, + { + .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB), + .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTB), + .irq = EXPIO_INT_XUART_INTB, + .uartclk = 14745600, + .regshift = 0, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,}, {}, }; static struct platform_device serial_device = { - .name = "serial8250", - .id = 0, - .dev = { + .name = "serial8250", + .id = 0, + .dev = { .platform_data = serial_platform_data, - }, + }, }; static int __init mxc_init_extuart(void) @@ -81,62 +208,819 @@ return 0; } #endif +/* MTD NOR flash */ + +#if defined(CONFIG_MTD_MXC) || defined(CONFIG_MTD_MXC_MODULE) + +static struct mtd_partition mxc_nor_partitions[] = { + { + .name = "Bootloader", + .size = 512 * 1024, + .offset = 0x00000000, + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, + { + .name = "nor.Kernel", + .size = 2 * 1024 * 1024, + .offset = MTDPART_OFS_APPEND, + .mask_flags = 0}, + { + .name = "nor.userfs", + .size = 14 * 1024 * 1024, + .offset = MTDPART_OFS_APPEND, + .mask_flags = 0}, + { + .name = "nor.rootfs", + .size = 12 * 1024 * 1024, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE}, + { + .name = "FIS directory", + .size = 12 * 1024, + .offset = 0x01FE0000, + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, + { + .name = "Redboot config", + .size = MTDPART_SIZ_FULL, + .offset = 0x01FFF000, + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, +}; + +static struct flash_platform_data mxc_flash_data = { + .map_name = "cfi_probe", + .width = 2, + .parts = mxc_nor_partitions, + .nr_parts = ARRAY_SIZE(mxc_nor_partitions), +}; + +static struct resource mxc_flash_resource = { + .start = 0xa0000000, + .end = 0xa0000000 + 0x02000000 - 1, + .flags = IORESOURCE_MEM, + +}; + +static struct platform_device mxc_nor_mtd_device = { + .name = "mxc_nor_flash", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_flash_data, + }, + .num_resources = 1, + .resource = &mxc_flash_resource, +}; + +static void mxc_init_nor_mtd(void) +{ + (void)platform_device_register(&mxc_nor_mtd_device); +} +#else +static void mxc_init_nor_mtd(void) +{ +} +#endif + +/* MTD NAND flash */ + +#if defined(CONFIG_MTD_NAND_MXC) || defined(CONFIG_MTD_NAND_MXC_MODULE) \ + || defined(CONFIG_MTD_NAND_MXC_V2) || defined(CONFIG_MTD_NAND_MXC_V2_MODULE) + +static struct mtd_partition mxc_nand_partitions[4] = { + { + .name = "nand.bootloader", + .offset = 0, + .size = 1024 * 1024}, + { + .name = "nand.kernel", + .offset = MTDPART_OFS_APPEND, + .size = 5 * 1024 * 1024}, + { + .name = "nand.rootfs", + .offset = MTDPART_OFS_APPEND, + .size = 22 * 1024 * 1024}, + { + .name = "nand.userfs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL}, +}; + +static struct flash_platform_data mxc_nand_data = { + .parts = mxc_nand_partitions, + .nr_parts = ARRAY_SIZE(mxc_nand_partitions), + .width = 1, +}; + +static struct platform_device mxc_nand_mtd_device = { + .name = "mxc_nand_flash", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_nand_data, + }, +}; + +static struct platform_device mxc_nandv2_mtd_device = { + .name = "mxc_nandv2_flash", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_nand_data, + }, +}; + +static void mxc_init_nand_mtd(void) +{ + if (__raw_readl(MXC_CCM_RCSR) & MXC_CCM_RCSR_NF16B) { + mxc_nand_data.width = 2; + } + if (cpu_is_mx31()) { + (void)platform_device_register(&mxc_nand_mtd_device); + } + if (cpu_is_mx32()) { + (void)platform_device_register(&mxc_nandv2_mtd_device); + } +} +#else +static inline void mxc_init_nand_mtd(void) +{ +} +#endif + +static struct spi_board_info mxc_spi_board_info[] __initdata = { + { + .modalias = "pmic_spi", + .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), + .max_speed_hz = 4000000, + .bus_num = 2, + .chip_select = 0, + }, +}; + +#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) +static const char fb_default_mode[] = "Sharp-QVGA"; + +/* mxc lcd driver */ +static struct platform_device mxc_fb_device = { + .name = "mxc_sdc_fb", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &fb_default_mode, + .coherent_dma_mask = 0xFFFFFFFF, + }, +}; + +static void mxc_init_fb(void) +{ + (void)platform_device_register(&mxc_fb_device); +} +#else +static inline void mxc_init_fb(void) +{ +} +#endif + +#if defined(CONFIG_BACKLIGHT_MXC) +static struct platform_device mxcbl_devices[] = { +#if defined(CONFIG_BACKLIGHT_MXC_PMIC) || defined(CONFIG_BACKLIGHT_MXC_PMIC_MODULE) + { + .name = "mxc_pmic_bl", + .id = 0, + .dev = { + .platform_data = (void *)-1, /* DISP # for this backlight */ + }, + }, + { + .name = "mxc_pmic_bl", + .id = 1, + .dev = { + .platform_data = (void *)0, /* DISP # for this backlight */ + }, + }, +#endif +#if defined(CONFIG_BACKLIGHT_MXC_IPU) || defined(CONFIG_BACKLIGHT_MXC_IPU_MODULE) + { + .name = "mxc_ipu_bl", + .id = 0, + .dev = { + .platform_data = (void *)3, /* DISP # for this backlight */ + }, + }, +#endif +}; +static inline void mxc_init_bl(void) +{ + int i; + for (i = 0; i < ARRAY_SIZE(mxcbl_devices); i++) { + platform_device_register(&mxcbl_devices[i]); + } +} +#else +static inline void mxc_init_bl(void) +{ +} +#endif + +/*! + * Data structures and data for mt9v111 camera. + */ +static struct mxc_camera_platform_data camera_mt9v111_data = { + .mclk = 27000000, +}; + +/*! + * Data structures and data for ov2640 camera. + */ +static struct mxc_camera_platform_data camera_ov2640_data = { + .core_regulator = NULL, + .io_regulator = NULL, + .analog_regulator = NULL, + .gpo_regulator = NULL, + .mclk = 24000000, +}; /*! - * This structure defines static mappings for the i.MX31ADS board. + * Info to register i2c devices. */ -static struct map_desc mx31ads_io_desc[] __initdata = { +static struct i2c_board_info mxc_i2c_info[] __initdata = { + { + .type = "mt9v111", + .addr = 0x48, + .platform_data = (void *)&camera_mt9v111_data, + }, { - .virtual = AIPS1_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), - .length = AIPS1_SIZE, - .type = MT_NONSHARED_DEVICE - }, { - .virtual = SPBA0_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), - .length = SPBA0_SIZE, - .type = MT_NONSHARED_DEVICE - }, { - .virtual = AIPS2_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), - .length = AIPS2_SIZE, - .type = MT_NONSHARED_DEVICE - }, { - .virtual = CS4_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(CS4_BASE_ADDR), - .length = CS4_SIZE / 2, - .type = MT_DEVICE - }, + .type = "ov2640", + .addr = 0x30, + .platform_data = (void *)&camera_ov2640_data, + }, +}; + +#if defined(CONFIG_MXC_FIR) || defined(CONFIG_MXC_FIR_MODULE) +/*! + * Resource definition for the FIR + */ +static struct resource mxcir_resources[] = { + [0] = { + .start = UART2_BASE_ADDR, + .end = UART2_BASE_ADDR + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_UART2, + .end = MXC_INT_UART2, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = FIRI_BASE_ADDR, + .end = FIRI_BASE_ADDR + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = MXC_INT_FIRI, + .end = MXC_INT_FIRI, + .flags = IORESOURCE_IRQ, + }, + [4] = { + .start = MXC_INT_UART2, + .end = MXC_INT_UART2, + .flags = IORESOURCE_IRQ, + } +}; + +static struct mxc_ir_platform_data ir_data = { + .uart_ir_mux = 1, + .ir_rx_invert = MXC_IRDA_RX_INV, + .ir_tx_invert = MXC_IRDA_TX_INV, +}; + +/*! Device Definition for MXC FIR */ +static struct platform_device mxcir_device = { + .name = "mxcir", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &ir_data, + }, + .num_resources = ARRAY_SIZE(mxcir_resources), + .resource = mxcir_resources, +}; + +static inline void mxc_init_ir(void) +{ + ir_data.uart_clk = clk_get(NULL, "uart_clk.1");; + (void)platform_device_register(&mxcir_device); +} +#else +static inline void mxc_init_ir(void) +{ +} +#endif + +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) +{ + u32 imr_val; + u32 int_valid; + u32 expio_irq; + + desc->chip->mask(irq); /* irq = gpio irq number */ + + imr_val = __raw_readw(PBC_INTMASK_SET_REG); + int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val; + + if (unlikely(!int_valid)) { + printk(KERN_ERR "\nEXPIO: Spurious interrupt:0x%0x\n\n", + int_valid); + goto out; + } + + expio_irq = MXC_EXP_IO_BASE; + for (; int_valid != 0; int_valid >>= 1, expio_irq++) { + struct irq_desc *d; + if ((int_valid & 1) == 0) + continue; + d = irq_desc + expio_irq; + if (unlikely(!(d->handle_irq))) { + printk(KERN_ERR "\nEXPIO irq: %d unhandeled\n", + expio_irq); + BUG(); /* oops */ + } + d->handle_irq(expio_irq, d); + } + + out: + desc->chip->ack(irq); + desc->chip->unmask(irq); +} + +/* + * Disable an expio pin's interrupt by setting the bit in the imr. + * @param irq an expio virtual irq number + */ +static void expio_mask_irq(u32 irq) +{ + u32 expio = MXC_IRQ_TO_EXPIO(irq); + /* mask the interrupt */ + __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG); +} + +/* + * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. + * @param irq an expanded io virtual irq number + */ +static void expio_ack_irq(u32 irq) +{ + u32 expio = MXC_IRQ_TO_EXPIO(irq); + /* clear the interrupt status */ + __raw_writew(1 << expio, PBC_INTSTATUS_REG); + /* mask the interrupt */ + expio_mask_irq(irq); +} + +/* + * Enable a expio pin's interrupt by clearing the bit in the imr. + * @param irq a expio virtual irq number + */ +static void expio_unmask_irq(u32 irq) +{ + u32 expio = MXC_IRQ_TO_EXPIO(irq); + /* unmask the interrupt */ + __raw_writew(1 << expio, PBC_INTMASK_SET_REG); +} + +static struct irq_chip expio_irq_chip = { + .ack = expio_ack_irq, + .mask = expio_mask_irq, + .unmask = expio_unmask_irq, +}; + +static int initialized = 0; + +static int __init _mxc_expio_init(void) +{ + int i; + + initialized = 1; + + printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n"); + /* + * Configure INT line as GPIO input + */ + mxc_request_iomux(MX31_PIN_GPIO1_4, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_set_gpio_direction(MX31_PIN_GPIO1_4, 1); + + /* disable the interrupt and clear the status */ + __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG); + __raw_writew(0xFFFF, PBC_INTSTATUS_REG); + for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); + i++) { + set_irq_chip(i, &expio_irq_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + set_irq_type(EXPIO_PARENT_INT, IRQT_HIGH); + set_irq_chained_handler(EXPIO_PARENT_INT, mxc_expio_irq_handler); + + return 0; +} + +/* + * This may get called early from board specific init + */ +int mxc_expio_init(void) +{ + if (!initialized) + return _mxc_expio_init(); + else + return 0; +} + +/* MMC device data */ + +#if defined(CONFIG_MMC_MXC) || defined(CONFIG_MMC_MXC_MODULE) +extern unsigned int sdhc_get_card_det_status(struct device *dev); +extern int sdhc_init_card_det(int id); + +static struct mxc_mmc_platform_data mmc0_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30, + .min_clk = 150000, + .max_clk = 25000000, + .card_inserted_state = 1, + .status = sdhc_get_card_det_status, + .power_mmc = "VMMC1", +}; +static struct mxc_mmc_platform_data mmc1_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30, + .min_clk = 150000, + .max_clk = 25000000, + .card_inserted_state = 1, + .status = sdhc_get_card_det_status, + .power_mmc = "VMMC2", +}; + +/*! + * Resource definition for the SDHC1 + */ +static struct resource mxcsdhc1_resources[] = { + [0] = { + .start = MMC_SDHC1_BASE_ADDR, + .end = MMC_SDHC1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_MMC_SDHC1, + .end = MXC_INT_MMC_SDHC1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ, + }, }; /*! - * Set up static virtual mappings. + * Resource definition for the SDHC2 */ -void __init mx31ads_map_io(void) +static struct resource mxcsdhc2_resources[] = { + [0] = { + .start = MMC_SDHC2_BASE_ADDR, + .end = MMC_SDHC2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_MMC_SDHC2, + .end = MXC_INT_MMC_SDHC2, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Device Definition for MXC SDHC1 */ +static struct platform_device mxcsdhc1_device = { + .name = "mxcmci", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc0_data, + }, + .num_resources = ARRAY_SIZE(mxcsdhc1_resources), + .resource = mxcsdhc1_resources, +}; + +/*! Device Definition for MXC SDHC2 */ +static struct platform_device mxcsdhc2_device = { + .name = "mxcmci", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc1_data, + }, + .num_resources = ARRAY_SIZE(mxcsdhc2_resources), + .resource = mxcsdhc2_resources, +}; + +static inline void mxc_init_mmc(void) +{ + int cd_irq; + + cd_irq = sdhc_init_card_det(0); + if (cd_irq) { + mxcsdhc1_device.resource[2].start = cd_irq; + mxcsdhc1_device.resource[2].end = cd_irq; + } + + cd_irq = sdhc_init_card_det(1); + if (cd_irq) { + mxcsdhc2_device.resource[2].start = cd_irq; + mxcsdhc2_device.resource[2].end = cd_irq; + } + + spba_take_ownership(SPBA_SDHC1, SPBA_MASTER_A | SPBA_MASTER_C); + (void)platform_device_register(&mxcsdhc1_device); + spba_take_ownership(SPBA_SDHC2, SPBA_MASTER_A | SPBA_MASTER_C); + (void)platform_device_register(&mxcsdhc2_device); +} +#else +static inline void mxc_init_mmc(void) { - mxc_map_io(); - iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc)); } +#endif + +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mxc_cpu_init(); +} + +#if (defined(CONFIG_MXC_PMIC_MC13783) || \ + defined(CONFIG_MXC_PMIC_MC13783_MODULE)) \ + && (defined(CONFIG_SND_MXC_PMIC) || defined(CONFIG_SND_MXC_PMIC_MODULE)) +extern void gpio_activate_audio_ports(void); + +static void __init mxc_init_pmic_audio(void) +{ + struct clk *ckih_clk; + struct clk *cko_clk; + + /* Enable 26 mhz clock on CKO1 for PMIC audio */ + ckih_clk = clk_get(NULL, "ckih"); + cko_clk = clk_get(NULL, "cko1_clk"); + if (IS_ERR(ckih_clk) || IS_ERR(cko_clk)) { + printk(KERN_ERR "Unable to set CKO1 output to CKIH\n"); + } else { + clk_set_parent(cko_clk, ckih_clk); + clk_set_rate(cko_clk, clk_get_rate(ckih_clk)); + clk_enable(cko_clk); + } + clk_put(ckih_clk); + clk_put(cko_clk); + + gpio_activate_audio_ports(); +} +#else +static void __inline mxc_init_pmic_audio(void) +{ +} +#endif + +/* IDE device data */ +#if defined(CONFIG_BLK_DEV_IDE_MXC) || defined(CONFIG_BLK_DEV_IDE_MXC_MODULE) + +/*! Platform Data for MXC IDE */ +static struct mxc_ide_platform_data mxc_ide_data = { + .power_drive = NULL, + .power_io = NULL, +}; + +static struct platform_device mxc_ide_device = { + .name = "mxc_ide", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_ide_data, + }, +}; + +static inline void mxc_init_ide(void) +{ + if (platform_device_register(&mxc_ide_device) < 0) + printk(KERN_ERR "Error: Registering the ide.\n"); +} +#else +static inline void mxc_init_ide(void) +{ +} +#endif + +#if defined(CONFIG_PATA_FSL) || defined(CONFIG_PATA_FSL_MODULE) +extern void gpio_ata_active(void); +extern void gpio_ata_inactive(void); + +static int ata_init(struct platform_device *pdev) +{ + /* Configure the pins */ + gpio_ata_active(); + + return 0; +} + +static void ata_exit(void) +{ + /* Free the pins */ + gpio_ata_inactive(); +} + +static struct fsl_ata_platform_data ata_data = { + .udma_mask = ATA_UDMA3, /* board can handle up to UDMA3 */ + .mwdma_mask = ATA_MWDMA2, + .pio_mask = ATA_PIO4, + .fifo_alarm = MXC_IDE_DMA_WATERMARK / 2, + .max_sg = MXC_IDE_DMA_BD_NR, + .init = ata_init, + .exit = ata_exit, + .core_reg = NULL, /*"LDO2", */ + .io_reg = NULL, /*"LDO3", */ +}; + +static struct resource pata_fsl_resources[] = { + [0] = { /* I/O */ + .start = ATA_BASE_ADDR + 0x00, + .end = ATA_BASE_ADDR + 0xD8, + .flags = IORESOURCE_MEM, + }, + [2] = { /* IRQ */ + .start = MXC_INT_ATA, + .end = MXC_INT_ATA, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pata_fsl_device = { + .name = "pata_fsl", + .id = -1, + .num_resources = ARRAY_SIZE(pata_fsl_resources), + .resource = pata_fsl_resources, + .dev = { + .platform_data = &ata_data, + .coherent_dma_mask = ~0, + }, +}; + +static void __init mxc_init_pata(void) +{ + (void)platform_device_register(&pata_fsl_device); +} +#else /* CONFIG_PATA_FSL */ +static void __init mxc_init_pata(void) +{ +} +#endif /* CONFIG_PATA_FSL */ /*! * Board specific initialization. */ static void __init mxc_board_init(void) { + mxc_cpu_common_init(); + mxc_clocks_init(); + early_console_setup(saved_command_line); + mxc_init_devices(); + mxc_init_pmic_audio(); + mxc_gpio_init(); + mx31ads_gpio_init(); + mxc_expio_init(); + mxc_init_keypad(); mxc_init_extuart(); + mxc_init_nor_mtd(); + mxc_init_nand_mtd(); + + i2c_register_board_info(0, mxc_i2c_info, ARRAY_SIZE(mxc_i2c_info)); + spi_register_board_info(mxc_spi_board_info, + ARRAY_SIZE(mxc_spi_board_info)); + + mxc_init_fb(); + mxc_init_bl(); + mxc_init_ir(); + mxc_init_mmc(); + mxc_init_ide(); + mxc_init_pata(); +} + +#define PLL_PCTL_REG(pd, mfd, mfi, mfn) \ + ((((pd) - 1) << 26) + (((mfd) - 1) << 16) + ((mfi) << 10) + mfn) + +/* For 26MHz input clock */ +#define PLL_532MHZ PLL_PCTL_REG(1, 13, 10, 3) +#define PLL_399MHZ PLL_PCTL_REG(1, 52, 7, 35) +#define PLL_133MHZ PLL_PCTL_REG(2, 26, 5, 3) + +/* For 27MHz input clock */ +#define PLL_532_8MHZ PLL_PCTL_REG(1, 15, 9, 13) +#define PLL_399_6MHZ PLL_PCTL_REG(1, 18, 7, 7) +#define PLL_133_2MHZ PLL_PCTL_REG(3, 5, 7, 2) + +#define PDR0_REG(mcu, max, hsp, ipg, nfc) \ + (MXC_CCM_PDR0_MCU_DIV_##mcu | MXC_CCM_PDR0_MAX_DIV_##max | \ + MXC_CCM_PDR0_HSP_DIV_##hsp | MXC_CCM_PDR0_IPG_DIV_##ipg | \ + MXC_CCM_PDR0_NFC_DIV_##nfc) + +/* working point(wp): 0 - 133MHz; 1 - 266MHz; 2 - 399MHz; 3 - 532MHz */ +/* 26MHz input clock table */ +static struct cpu_wp cpu_wp_26[] = { + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 133000000, + .pdr0_reg = PDR0_REG(4, 4, 4, 2, 6),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 266000000, + .pdr0_reg = PDR0_REG(2, 4, 4, 2, 6),}, + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 399000000, + .pdr0_reg = PDR0_REG(1, 3, 3, 2, 6),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 532000000, + .pdr0_reg = PDR0_REG(1, 4, 4, 2, 6),}, +}; + +/* 27MHz input clock table */ +static struct cpu_wp cpu_wp_27[] = { + { + .pll_reg = PLL_532_8MHZ, + .pll_rate = 532800000, + .cpu_rate = 133200000, + .pdr0_reg = PDR0_REG(4, 4, 4, 2, 6),}, + { + .pll_reg = PLL_532_8MHZ, + .pll_rate = 532800000, + .cpu_rate = 266400000, + .pdr0_reg = PDR0_REG(2, 4, 4, 2, 6),}, + { + .pll_reg = PLL_399_6MHZ, + .pll_rate = 399600000, + .cpu_rate = 399600000, + .pdr0_reg = PDR0_REG(1, 3, 3, 2, 6),}, + { + .pll_reg = PLL_532_8MHZ, + .pll_rate = 532800000, + .cpu_rate = 532800000, + .pdr0_reg = PDR0_REG(1, 4, 4, 2, 6),}, +}; + +struct cpu_wp *get_cpu_wp(int *wp) +{ + *wp = 4; + if ((__raw_readw(PBC_BASE_ADDRESS + PBC_BSTAT) & + CKIH_27MHZ_BIT_SET) != 0) { + return cpu_wp_27; + } else { + return cpu_wp_26; + } } /* * The following uses standard kernel macros defined in arch.h in order to * initialize __mach_desc_MX31ADS data structure. */ -MACHINE_START(MX31ADS, "Freescale MX31ADS") +/* *INDENT-OFF* */ +MACHINE_START(MX31ADS, "Freescale MX31/MX32 ADS") /* Maintainer: Freescale Semiconductor, Inc. */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, - .map_io = mx31ads_map_io, - .init_irq = mxc_init_irq, - .init_machine = mxc_board_init, - .timer = &mxc_timer, +#ifdef CONFIG_SERIAL_8250_CONSOLE + .phys_io = CS4_BASE_ADDR, + .io_pg_offst = ((CS4_BASE_ADDR_VIRT) >> 18) & 0xfffc, +#else + .phys_io = AIPS1_BASE_ADDR, + .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, +#endif + .boot_params = PHYS_OFFSET + 0x100, + .fixup = fixup_mxc_board, + .map_io = mxc_map_io, + .init_irq = mxc_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, MACHINE_END diff -urN linux-2.6.26/arch/arm/mach-mx3/mx31ads_gpio.c linux-2.6.26-lab126/arch/arm/mach-mx3/mx31ads_gpio.c --- linux-2.6.26/arch/arm/mach-mx3/mx31ads_gpio.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/mx31ads_gpio.c 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,1561 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include "board-mx31ads.h" +#include "iomux.h" + +/*! + * @file mach-mx3/mx31ads_gpio.c + * + * @brief This file contains all the GPIO setup functions for the board. + * + * @ingroup GPIO_MX31 + */ + +void gpio_activate_audio_ports(void); + +/*! + * This system-wise GPIO function initializes the pins during system startup. + * All the statically linked device drivers should put the proper GPIO initialization + * code inside this function. It is called by \b fixup_mx31ads() during + * system startup. This function is board specific. + */ +void mx31ads_gpio_init(void) +{ + /* config CS4 */ + mxc_request_iomux(MX31_PIN_CS4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + + /*Connect DAM ports 4 & 5 to enable audio I/O */ + gpio_activate_audio_ports(); +} + +/*! + * Setup GPIO for a UART port to be active + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_active(int port, int no_irda) +{ + unsigned int pbc_bctrl1_clr = 0, pbc_bctrl2_set = 0, pbc_bctrl2_clr = 0; + /* + * Configure the IOMUX control registers for the UART signals + */ + switch (port) { + /* UART 1 IOMUX Configs */ + case 0: + mxc_request_iomux(MX31_PIN_RXD1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_TXD1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_RTS1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CTS1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_DTR_DCE1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_DSR_DCE1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_RI_DCE1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_DCD_DCE1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + + /* Enable the transceiver */ + pbc_bctrl1_clr |= PBC_BCTRL1_UENCE; + pbc_bctrl2_set |= PBC_BCTRL2_USELC; + break; + /* UART 2 IOMUX Configs */ + case 1: + mxc_request_iomux(MX31_PIN_TXD2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_RXD2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + + if (no_irda == 1) { + mxc_request_iomux(MX31_PIN_RTS2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CTS2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_DTR_DCE2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + pbc_bctrl1_clr |= PBC_BCTRL1_UENCE; + pbc_bctrl2_clr |= PBC_BCTRL2_USELC; + } else { + pbc_bctrl1_clr |= PBC_BCTRL1_IREN; + pbc_bctrl2_clr |= PBC_BCTRL2_IRDA_MOD; + } + break; + /* UART 3 IOMUX Configs */ + case 2: + mxc_request_iomux(MX31_PIN_CSPI3_MOSI, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_CSPI3_MISO, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_CSPI3_SCLK, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_CSPI3_SPI_RDY, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + + pbc_bctrl1_clr |= PBC_BCTRL1_UENB; + pbc_bctrl2_clr |= PBC_BCTRL2_USELB; + break; + /* UART 4 IOMUX Configs */ + case 3: + mxc_request_iomux(MX31_PIN_ATA_CS0, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_ATA_CS1, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_ATA_DIOR, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_ATA_DIOW, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + + pbc_bctrl1_clr |= PBC_BCTRL1_UENB; + pbc_bctrl2_set |= PBC_BCTRL2_USELB; + break; + /* UART 5 IOMUX Configs */ + case 4: + mxc_request_iomux(MX31_PIN_PC_VS2, OUTPUTCONFIG_ALT2, + INPUTCONFIG_ALT2); + mxc_request_iomux(MX31_PIN_PC_RST, OUTPUTCONFIG_ALT2, + INPUTCONFIG_ALT2); + mxc_request_iomux(MX31_PIN_PC_BVD1, OUTPUTCONFIG_ALT2, + INPUTCONFIG_ALT2); + mxc_request_iomux(MX31_PIN_PC_BVD2, OUTPUTCONFIG_ALT2, + INPUTCONFIG_ALT2); + + pbc_bctrl1_clr |= PBC_BCTRL1_UENA; + pbc_bctrl2_set |= PBC_BCTRL2_USELA; + break; + default: + break; + } + + __raw_writew(pbc_bctrl1_clr, PBC_BASE_ADDRESS + PBC_BCTRL1_CLEAR); + __raw_writew(pbc_bctrl2_set, PBC_BASE_ADDRESS + PBC_BCTRL2_SET); + __raw_writew(pbc_bctrl2_clr, PBC_BASE_ADDRESS + PBC_BCTRL2_CLEAR); + /* + * TODO: Configure the Pad registers for the UART pins + */ +} + +/*! + * Setup GPIO for a UART port to be inactive + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_inactive(int port, int no_irda) +{ + unsigned int pbc_bctrl1_set = 0; + + switch (port) { + case 0: + mxc_request_gpio(MX31_PIN_RXD1); + mxc_request_gpio(MX31_PIN_TXD1); + mxc_request_gpio(MX31_PIN_RTS1); + mxc_request_gpio(MX31_PIN_CTS1); + mxc_request_gpio(MX31_PIN_DTR_DCE1); + mxc_request_gpio(MX31_PIN_DSR_DCE1); + mxc_request_gpio(MX31_PIN_RI_DCE1); + mxc_request_gpio(MX31_PIN_DCD_DCE1); + + mxc_free_iomux(MX31_PIN_RXD1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_TXD1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_RTS1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_CTS1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_DTR_DCE1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_DSR_DCE1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_RI_DCE1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_DCD_DCE1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + + pbc_bctrl1_set |= PBC_BCTRL1_UENCE; + break; + case 1: + mxc_request_gpio(MX31_PIN_TXD2); + mxc_request_gpio(MX31_PIN_RXD2); + + mxc_free_iomux(MX31_PIN_TXD2, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_RXD2, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + + if (no_irda == 1) { + mxc_request_gpio(MX31_PIN_DTR_DCE2); + mxc_free_iomux(MX31_PIN_DTR_DCE2, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + + pbc_bctrl1_set |= PBC_BCTRL1_UENCE; + } else { + pbc_bctrl1_set |= PBC_BCTRL1_IREN; + } + break; + case 2: + pbc_bctrl1_set |= PBC_BCTRL1_UENB; + break; + case 3: + mxc_request_gpio(MX31_PIN_ATA_CS0); + mxc_request_gpio(MX31_PIN_ATA_CS1); + mxc_request_gpio(MX31_PIN_ATA_DIOR); + mxc_request_gpio(MX31_PIN_ATA_DIOW); + + mxc_free_iomux(MX31_PIN_ATA_CS0, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_ATA_CS1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_ATA_DIOR, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_ATA_DIOW, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + + pbc_bctrl1_set |= PBC_BCTRL1_UENB; + break; + case 4: + pbc_bctrl1_set |= PBC_BCTRL1_UENA; + break; + default: + break; + } + __raw_writew(pbc_bctrl1_set, PBC_BASE_ADDRESS + PBC_BCTRL1_SET); +} + +/*! + * Configure the IOMUX GPR register to receive shared SDMA UART events + * + * @param port a UART port + */ +void config_uartdma_event(int port) +{ + switch (port) { + case 1: + /* Configure to receive UART 2 SDMA events */ + mxc_iomux_set_gpr(MUX_PGP_FIRI, false); + break; + case 2: + /* Configure to receive UART 3 SDMA events */ + mxc_iomux_set_gpr(MUX_CSPI1_UART3, true); + break; + case 4: + /* Configure to receive UART 5 SDMA events */ + mxc_iomux_set_gpr(MUX_CSPI3_UART5_SEL, true); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_uart_active); +EXPORT_SYMBOL(gpio_uart_inactive); +EXPORT_SYMBOL(config_uartdma_event); + +/*! + * Setup GPIO for Keypad to be active + * + */ +void gpio_keypad_active(void) +{ + /* + * Configure the IOMUX control register for keypad signals. + */ + mxc_request_iomux(MX31_PIN_KEY_COL0, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_COL1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_COL2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_COL3, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_COL4, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_COL5, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_COL6, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_COL7, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_ROW0, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_ROW1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_ROW2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_ROW3, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_ROW4, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_ROW5, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_ROW6, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_ROW7, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); +} + +EXPORT_SYMBOL(gpio_keypad_active); + +/*! + * Setup GPIO for Keypad to be inactive + * + */ +void gpio_keypad_inactive(void) +{ + mxc_request_iomux(MX31_PIN_KEY_COL4, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_request_iomux(MX31_PIN_KEY_COL5, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_request_iomux(MX31_PIN_KEY_COL6, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_request_iomux(MX31_PIN_KEY_COL7, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + + mxc_request_iomux(MX31_PIN_KEY_ROW4, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_request_iomux(MX31_PIN_KEY_ROW5, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_request_iomux(MX31_PIN_KEY_ROW6, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_request_iomux(MX31_PIN_KEY_ROW7, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); +} + +EXPORT_SYMBOL(gpio_keypad_inactive); + +void gpio_power_key_active(void) +{ +} +EXPORT_SYMBOL(gpio_power_key_active); + +/*! + * Setup GPIO for a CSPI device to be active + * + * @param cspi_mod an CSPI device + */ +void gpio_spi_active(int cspi_mod) +{ + switch (cspi_mod) { + case 0: + /* SPI1 */ + mxc_request_iomux(MX31_PIN_CSPI1_MISO, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI1_MOSI, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI1_SCLK, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI1_SPI_RDY, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI1_SS0, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI1_SS1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI1_SS2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + break; + case 1: + /* SPI2 */ + mxc_request_iomux(MX31_PIN_CSPI2_MISO, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_MOSI, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_SCLK, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_SPI_RDY, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_SS0, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_SS1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_SS2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + break; + case 2: + /* SPI3 */ + /* + mxc_request_iomux(MX31_PIN_CSPI2_MISO, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_MOSI, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_SCLK, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_SPI_RDY, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_SS0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_SS1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_SS2, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + */ + break; + default: + break; + } +} + +/*! + * Setup 1-Wire to be active + */ +void gpio_owire_active(void) +{ + /* + * Configure the IOMUX control register for 1-wire signals. + */ + iomux_config_mux(MX31_PIN_BATT_LINE, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + iomux_config_pad(MX31_PIN_BATT_LINE, PAD_CTL_LOOPBACK); +} + +/*! + * Setup 1-Wire to be active + */ +void gpio_owire_inactive(void) +{ + /* + * Configure the IOMUX control register for 1-wire signals. + */ + iomux_config_mux(MX31_PIN_BATT_LINE, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); +} + +EXPORT_SYMBOL(gpio_owire_active); +EXPORT_SYMBOL(gpio_owire_inactive); + +/*! + * Setup GPIO for a CSPI device to be inactive + * + * @param cspi_mod a CSPI device + */ +void gpio_spi_inactive(int cspi_mod) +{ + /* Do nothing as CSPI pins doesn't have/support GPIO mode */ +} + +/*! + * Setup GPIO for an I2C device to be active + * + * @param i2c_num an I2C device + */ +void gpio_i2c_active(int i2c_num) +{ + switch (i2c_num) { + case 0: + mxc_request_iomux(MX31_PIN_I2C_CLK, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_I2C_DAT, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + break; + case 1: + mxc_request_iomux(MX31_PIN_CSPI2_MOSI, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_CSPI2_MISO, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + break; + case 2: + mxc_request_iomux(MX31_PIN_CSPI2_SS2, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_CSPI2_SCLK, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + break; + default: + break; + } + +} + +/*! + * Setup GPIO for an I2C device to be inactive + * + * @param i2c_num an I2C device + */ +void gpio_i2c_inactive(int i2c_num) +{ + switch (i2c_num) { + case 0: + break; + case 1: + break; + case 2: + mxc_request_iomux(MX31_PIN_CSPI2_SS2, OUTPUTCONFIG_GPIO, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_CSPI2_SCLK, OUTPUTCONFIG_GPIO, + INPUTCONFIG_ALT1); + break; + default: + break; + } +} + +/*! + * This function configures the IOMux block for PMIC standard operations. + * + */ +void gpio_pmic_active(void) +{ + mxc_request_iomux(MX31_PIN_GPIO1_3, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_set_gpio_direction(MX31_PIN_GPIO1_3, 1); +// mxc_set_gpio_edge_ctrl(MX31_PIN_GPIO1_3, GPIO_INT_RISE_EDGE); +} + +EXPORT_SYMBOL(gpio_pmic_active); + +/*! + * This function activates DAM ports 4 & 5 to enable + * audio I/O. Thsi function is called from mx31ads_gpio_init + * function, which is board-specific. + */ +void gpio_activate_audio_ports(void) +{ + /* config Audio ports (4 & 5) */ + mxc_request_iomux(MX31_PIN_SCK4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SRXD4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_STXD4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SFS4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SCK5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SRXD5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_STXD5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SFS5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); +} + +/*! + * Setup GPIO for SDHC to be active + * + * @param module SDHC module number + */ +void gpio_sdhc_active(int module) +{ + switch (module) { + case 0: + mxc_request_iomux(MX31_PIN_SD1_CLK, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SD1_CMD, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SD1_DATA0, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SD1_DATA1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SD1_DATA2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SD1_DATA3, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + + mxc_iomux_set_pad(MX31_PIN_SD1_CLK, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_SD1_CMD, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + break; + case 1: + mxc_request_iomux(MX31_PIN_PC_CD2_B, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_PC_CD1_B, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_PC_WAIT_B, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_PC_READY, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_PC_VS1, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_PC_PWRON, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_sdhc_active); + +/*! + * Setup GPIO for SDHC1 to be inactive + * + * @param module SDHC module number + */ +void gpio_sdhc_inactive(int module) +{ + switch (module) { + case 0: + mxc_request_iomux(MX31_PIN_SD1_CLK, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_SD1_CMD, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_SD1_DATA0, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_SD1_DATA1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_SD1_DATA2, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_SD1_DATA3, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + + mxc_iomux_set_pad(MX31_PIN_SD1_CLK, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX31_PIN_SD1_CMD, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + break; + case 1: + /* TODO:what are the pins for SDHC2? */ + mxc_request_iomux(MX31_PIN_PC_CD2_B, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_PC_CD1_B, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_PC_WAIT_B, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_PC_READY, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_PC_VS1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_PC_PWRON, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_sdhc_inactive); + +/* + * Probe for the card. If present the GPIO data would be set. + */ +int sdhc_get_card_det_status(struct device *dev) +{ + if (to_platform_device(dev)->id == 0) { + return mxc_get_gpio_datain(MX31_PIN_GPIO1_1); + } else { + return mxc_get_gpio_datain(MX31_PIN_GPIO1_2); + } +} + +EXPORT_SYMBOL(sdhc_get_card_det_status); + +/* + * Return the card detect pin. + */ +int sdhc_init_card_det(int id) +{ + if (id == 0) { + iomux_config_mux(MX31_PIN_GPIO1_1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + return IOMUX_TO_IRQ(MX31_PIN_GPIO1_1); + } else { + iomux_config_mux(MX31_PIN_GPIO1_2, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + return IOMUX_TO_IRQ(MX31_PIN_GPIO1_2); + + } +} + +EXPORT_SYMBOL(sdhc_init_card_det); + +/*! + * Setup GPIO for LCD to be active + * + */ +void gpio_lcd_active(void) +{ + u16 temp; + + mxc_request_iomux(MX31_PIN_LD0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD2, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD7, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD8, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD9, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD10, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD11, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD12, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD13, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD14, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD15, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD16, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // LD16 + mxc_request_iomux(MX31_PIN_LD17, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // LD17 + mxc_request_iomux(MX31_PIN_VSYNC3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // VSYNC + mxc_request_iomux(MX31_PIN_HSYNC, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // HSYNC + mxc_request_iomux(MX31_PIN_FPSHIFT, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // CLK + mxc_request_iomux(MX31_PIN_DRDY0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // DRDY + mxc_request_iomux(MX31_PIN_D3_REV, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // REV + mxc_request_iomux(MX31_PIN_CONTRAST, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // CONTR + mxc_request_iomux(MX31_PIN_D3_SPL, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // SPL + mxc_request_iomux(MX31_PIN_D3_CLS, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // CLS + + temp = PBC_BCTRL1_LCDON; + __raw_writew(temp, PBC_BASE_ADDRESS + PBC_BCTRL1_SET); +} + +/*! + * Setup GPIO for LCD to be inactive + * + */ +void gpio_lcd_inactive(void) +{ + u16 pbc_bctrl1_set = 0; + + pbc_bctrl1_set = (u16) PBC_BCTRL1_LCDON; + __raw_writew(pbc_bctrl1_set, PBC_BASE_ADDRESS + PBC_BCTRL1_SET + 2); +} + +/*! + * Setup pins for SLCD to be active + * + */ +void slcd_gpio_config(void) +{ + u16 temp; + + /* Reset smart lcd */ + temp = PBC_BCTRL2_LDC_RST0; + __raw_writew(temp, PBC_BASE_ADDRESS + PBC_BCTRL2_CLEAR); + msleep(2); + /* Bring out of reset */ + __raw_writew(temp, PBC_BASE_ADDRESS + PBC_BCTRL2_SET); + msleep(2); + + mxc_request_iomux(MX31_PIN_LD0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD2, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD7, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD8, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD9, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD10, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD11, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD12, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD13, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD14, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD15, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD16, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD17, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + + mxc_request_iomux(MX31_PIN_READ, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); /* read */ + mxc_request_iomux(MX31_PIN_WRITE, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); /* write */ + mxc_request_iomux(MX31_PIN_PAR_RS, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); /* RS */ + mxc_request_iomux(MX31_PIN_LCS0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); /* chip select */ + + /* Enable smart lcd interface */ + temp = PBC_BCTRL2_LDCIO_EN; + __raw_writew(temp, PBC_BASE_ADDRESS + PBC_BCTRL2_CLEAR); +} + +/*! + * Switch to the specified sensor - MX31 ADS has two + * + */ +void gpio_sensor_select(int sensor) +{ + u16 temp; + + switch (sensor) { + case 0: +#ifdef CONFIG_MXC_CAMERA_MC521DA + temp = 0x100; + __raw_writew(temp, PBC_BASE_ADDRESS + PBC_BCTRL1_SET); +#else + temp = PBC_BCTRL1_SENSOR2_ON; + __raw_writew(temp, PBC_BASE_ADDRESS + PBC_BCTRL1_CLEAR); + temp = PBC_BCTRL1_SENSOR1_ON; + __raw_writew(temp, PBC_BASE_ADDRESS + PBC_BCTRL1_SET); +#endif + break; + case 1: + temp = PBC_BCTRL1_SENSOR1_ON; + __raw_writew(temp, PBC_BASE_ADDRESS + PBC_BCTRL1_CLEAR); + temp = PBC_BCTRL1_SENSOR2_ON; + __raw_writew(temp, PBC_BASE_ADDRESS + PBC_BCTRL1_SET); + break; + default: + break; + } +} + +/*! + * Setup GPIO for sensor to be active + * + */ +void gpio_sensor_active(void) +{ + gpio_sensor_select(0); + + /* + * Configure the iomuxen for the CSI. + */ + + mxc_request_iomux(MX31_PIN_CSI_D4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D7, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D8, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D9, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D10, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D11, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D12, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D13, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D14, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D15, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_HSYNC, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_MCLK, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_PIXCLK, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_VSYNC, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + +#ifdef CONFIG_MXC_IPU_CAMERA_16BIT + /* + * The other 4 data bits are multiplexed on MX31. + */ + mxc_request_iomux(MX31_PIN_ATA_CS0, OUTPUTCONFIG_ALT2, + INPUTCONFIG_ALT2); + mxc_request_iomux(MX31_PIN_ATA_CS1, OUTPUTCONFIG_ALT2, + INPUTCONFIG_ALT2); + mxc_request_iomux(MX31_PIN_ATA_DIOR, OUTPUTCONFIG_ALT2, + INPUTCONFIG_ALT2); + mxc_request_iomux(MX31_PIN_ATA_DIOW, OUTPUTCONFIG_ALT2, + INPUTCONFIG_ALT2); +#endif + + /* + * Now enable the CSI buffers + */ + + __raw_writew(PBC_BCTRL2_CSI_EN, PBC_BASE_ADDRESS + PBC_BCTRL2_CLEAR); + +#ifdef CONFIG_MXC_IPU_CAMERA_16BIT + /* + * Enable the other buffer for the additional 4 data bits. + */ + __raw_writew(PBC_BCTRL4_CSI_MSB_EN, + PBC_BASE_ADDRESS + PBC_BCTRL4_CLEAR); +#endif +} + +EXPORT_SYMBOL(gpio_sensor_active); + +void gpio_sensor_reset(bool flag) +{ + u16 temp; + + if (flag) { + temp = 0x200; + __raw_writew(temp, PBC_BASE_ADDRESS + PBC_BCTRL1_CLEAR); + } else { + temp = 0x200; + __raw_writew(temp, PBC_BASE_ADDRESS + PBC_BCTRL1_SET); + } +} + +EXPORT_SYMBOL(gpio_sensor_reset); + +/*! + * Setup GPIO for sensor to be inactive + * + */ +void gpio_sensor_inactive(void) +{ + mxc_free_iomux(MX31_PIN_CSI_D4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D7, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D8, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D9, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D10, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D11, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D12, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D13, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D14, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D15, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_HSYNC, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_MCLK, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_PIXCLK, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_VSYNC, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); +} + +EXPORT_SYMBOL(gpio_sensor_inactive); + +/*! + * Setup GPIO for ATA interface + * + */ +void gpio_ata_active(void) +{ + /* + * Configure the GPR for ATA group B signals + */ + __raw_writew(PBC_BCTRL2_ATA_SEL, PBC_BASE_ADDRESS + PBC_BCTRL2_SET); + __raw_writew(PBC_BCTRL2_ATA_EN, PBC_BASE_ADDRESS + PBC_BCTRL2_CLEAR); + + mxc_iomux_set_gpr(MUX_PGP_ATA_7 | MUX_PGP_ATA_6 | MUX_PGP_ATA_2 | + MUX_PGP_ATA_1, true); + + /* + * Configure the IOMUX for ATA group B signals + */ + + mxc_request_iomux(MX31_PIN_CSPI1_MOSI, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D0 + mxc_request_iomux(MX31_PIN_CSPI1_MISO, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D1 + mxc_request_iomux(MX31_PIN_CSPI1_SS0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D2 + mxc_request_iomux(MX31_PIN_CSPI1_SS1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D3 + mxc_request_iomux(MX31_PIN_CSPI1_SS2, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D4 + mxc_request_iomux(MX31_PIN_CSPI1_SCLK, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D5 + mxc_request_iomux(MX31_PIN_CSPI1_SPI_RDY, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D6 + mxc_request_iomux(MX31_PIN_STXD3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D7 + mxc_request_iomux(MX31_PIN_SRXD3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D8 + mxc_request_iomux(MX31_PIN_SCK3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D9 + mxc_request_iomux(MX31_PIN_SFS3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D10 + mxc_request_iomux(MX31_PIN_STXD6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D11 + mxc_request_iomux(MX31_PIN_SRXD6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D12 + mxc_request_iomux(MX31_PIN_SCK6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D13 + mxc_request_iomux(MX31_PIN_CAPTURE, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D14 + mxc_request_iomux(MX31_PIN_COMPARE, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D15 + + mxc_request_iomux(MX31_PIN_USBH2_STP, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_DMARQ_B + mxc_request_iomux(MX31_PIN_USBH2_CLK, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_INTRQ_B + mxc_request_iomux(MX31_PIN_USBH2_NXT, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_DA0 + mxc_request_iomux(MX31_PIN_USBH2_DATA0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_DA1 + mxc_request_iomux(MX31_PIN_USBH2_DATA1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_DA2 + mxc_request_iomux(MX31_PIN_USBH2_DIR, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_BUFFER_DIR + + /* These ATA pins are common to Group A and Group B */ + + mxc_request_iomux(MX31_PIN_ATA_CS0, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_ATA_CS1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_ATA_DIOR, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_ATA_DIOW, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_ATA_DMACK, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_ATA_RESET_B, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_PWMO, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + + /* Need fast slew rate for UDMA mode */ + + mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE); // data 0 + mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE); // data 1 + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE); // data 2 + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE); // data 3 + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE); // data 4 + mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE); // data 5 + mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE); // data 6 + mxc_iomux_set_pad(MX31_PIN_STXD3, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE); // data 7 + mxc_iomux_set_pad(MX31_PIN_SRXD3, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE); // data 8 + mxc_iomux_set_pad(MX31_PIN_SCK3, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE); // data 9 + mxc_iomux_set_pad(MX31_PIN_SFS3, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE); // data 10 + mxc_iomux_set_pad(MX31_PIN_STXD6, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE); // data 11 + mxc_iomux_set_pad(MX31_PIN_SRXD6, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE); // data 12 + mxc_iomux_set_pad(MX31_PIN_SCK6, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE); // data 13 + mxc_iomux_set_pad(MX31_PIN_CAPTURE, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE); // data 14 + mxc_iomux_set_pad(MX31_PIN_COMPARE, PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE); // data 12 + + /* + * Turn off default pullups on high asserted control signals. + * These are pulled down externally, so it will just waste + * power and create voltage divider action to pull them up + * on chip. + */ + mxc_iomux_set_pad(MX31_PIN_USBH2_STP, PAD_CTL_PKE_NONE); // ATA_DMARQ + mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, PAD_CTL_PKE_NONE); // ATA_INTRQ +} + +EXPORT_SYMBOL(gpio_ata_active); + +/*! + * Restore ATA interface pins to reset values + * + */ +void gpio_ata_inactive(void) +{ + __raw_writew(PBC_BCTRL2_ATA_EN, PBC_BASE_ADDRESS + PBC_BCTRL2_SET); + /* + * Turn off ATA group B signals + */ + mxc_request_iomux(MX31_PIN_STXD3, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D7 + mxc_request_iomux(MX31_PIN_SRXD3, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D8 + mxc_request_iomux(MX31_PIN_STXD6, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D11 + mxc_request_iomux(MX31_PIN_SRXD6, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D12 + mxc_request_iomux(MX31_PIN_SCK6, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D13 + mxc_request_iomux(MX31_PIN_CAPTURE, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D14 + mxc_request_iomux(MX31_PIN_COMPARE, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D15 + + /* These ATA pins are common to Group A and Group B */ + + mxc_request_iomux(MX31_PIN_ATA_CS0, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_ATA_CS1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_ATA_DIOR, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_ATA_DIOW, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_ATA_DMACK, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_ATA_RESET_B, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + + /* Needed fast slew rate for UDMA mode */ + + mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE); // data 0 + mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE); // data 1 + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE); // data 2 + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE); // data 3 + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE); // data 4 + mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE); // data 5 + mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE); // data 6 + mxc_iomux_set_pad(MX31_PIN_STXD3, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE); // data 7 + mxc_iomux_set_pad(MX31_PIN_SRXD3, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE); // data 8 + mxc_iomux_set_pad(MX31_PIN_SCK3, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE); // data 9 + mxc_iomux_set_pad(MX31_PIN_SFS3, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE); // data 10 + mxc_iomux_set_pad(MX31_PIN_STXD3, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE); // data 11 + mxc_iomux_set_pad(MX31_PIN_SRXD6, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE); // data 12 + mxc_iomux_set_pad(MX31_PIN_SCK6, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE); // data 13 + mxc_iomux_set_pad(MX31_PIN_CAPTURE, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE); // data 14 + mxc_iomux_set_pad(MX31_PIN_COMPARE, PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE); // data 12 +} + +EXPORT_SYMBOL(gpio_ata_inactive); + +/*! + * Setup EDIO/IOMUX for external UART. + * + * @param port UART port + * @param irq Interrupt line to allocate + * @param handler Function to be called when the IRQ occurs + * @param irq_flags Interrupt type flags + * @param devname An ascii name for the claiming device + * @param dev_id A cookie passed back to the handler function + * @return Returns 0 if the interrupt was successfully requested, + * otherwise returns an error code. + */ +int extuart_intr_setup(unsigned int port, unsigned int irq, + irqreturn_t(*handler) (int, void *), + unsigned long irq_flags, const char *devname, + void *dev_id) +{ + return 0; +} + +/*! + * Get the EDIO interrupt, clear if set. + * + * @param port UART port + */ +void extuart_intr_clear(unsigned int port) +{ +} + +/*! + * Do IOMUX configs required to put the + * pin back in low power mode. + * + * @param port UART port + * @param irq Interrupt line to free + * @param dev_id Device identity to free + * @return Returns 0 if the interrupt was successfully freed, + * otherwise returns an error code. + */ +int extuart_intr_cleanup(unsigned int port, unsigned int irq, void *dev_id) +{ + return 0; +} + +/* *INDENT-OFF* */ +/* + * USB Host 1 + * pins conflict with SPI1, ATA, UART3 + */ +int gpio_usbh1_active(void) +{ + if (mxc_request_iomux(MX31_PIN_CSPI1_MOSI, /* USBH1_RXDM */ + OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1) || + mxc_request_iomux(MX31_PIN_CSPI1_MISO, /* USBH1_RXDP */ + OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1) || + mxc_request_iomux(MX31_PIN_CSPI1_SS0, /* USBH1_TXDM */ + OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1) || + mxc_request_iomux(MX31_PIN_CSPI1_SS1, /* USBH1_TXDP */ + OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1) || + mxc_request_iomux(MX31_PIN_CSPI1_SS2, /* USBH1_RCV */ + OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1) || + mxc_request_iomux(MX31_PIN_CSPI1_SCLK, /* USBH1_OEB (_TXOE) */ + OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1) || + mxc_request_iomux(MX31_PIN_CSPI1_SPI_RDY, /* USBH1_FS */ + OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1)) { + return -EINVAL; + } + + mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, /* USBH1_RXDM */ + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + + mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, /* USBH1_RXDP */ + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, /* USBH1_TXDM */ + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, /* USBH1_TXDP */ + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, /* USBH1_RCV */ + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + + mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, /* USBH1_OEB (_TXOE) */ + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + + mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, /* USBH1_FS */ + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + + mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); + + __raw_writew(PBC_BCTRL3_FSH_EN, PBC_BASE_ADDRESS + PBC_BCTRL3_CLEAR); /* enable FSH */ + __raw_writew(PBC_BCTRL3_FSH_SEL, PBC_BASE_ADDRESS + PBC_BCTRL3_SET); /* Group B */ + __raw_writew(PBC_BCTRL3_FSH_MOD, PBC_BASE_ADDRESS + PBC_BCTRL3_CLEAR); /* single ended */ + __raw_writew(PBC_BCTRL3_FSH_VBUS_EN, PBC_BASE_ADDRESS + PBC_BCTRL3_CLEAR); /* enable FSH VBUS */ + + return 0; +} + +EXPORT_SYMBOL(gpio_usbh1_active); + +void gpio_usbh1_inactive(void) +{ + /* Do nothing as pins don't have/support GPIO mode */ + +} + +EXPORT_SYMBOL(gpio_usbh1_inactive); + +/* + * USB Host 2 + * pins conflict with UART5, PCMCIA + */ +int gpio_usbh2_active(void) +{ + if (mxc_request_iomux(MX31_PIN_USBH2_CLK, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBH2_DIR, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBH2_NXT, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBH2_STP, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBH2_DATA0, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBH2_DATA1, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_PC_VS2, /* USBH2_DATA2 */ + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE) || + mxc_request_iomux(MX31_PIN_PC_BVD1, /* USBH2_DATA3 */ + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE) || + mxc_request_iomux(MX31_PIN_PC_BVD2, /* USBH2_DATA4 */ + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE) || + mxc_request_iomux(MX31_PIN_PC_RST, /* USBH2_DATA5 */ + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE) || + mxc_request_iomux(MX31_PIN_IOIS16, /* USBH2_DATA6 */ + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE) || + mxc_request_iomux(MX31_PIN_PC_RW_B, /* USBH2_DATA7 */ + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE) || + mxc_request_iomux(MX31_PIN_NFWE_B, + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE) || + mxc_request_iomux(MX31_PIN_NFRE_B, + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE) || + mxc_request_iomux(MX31_PIN_NFALE, + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE) || + mxc_request_iomux(MX31_PIN_NFCLE, + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE) || + mxc_request_iomux(MX31_PIN_NFWP_B, + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE) || + mxc_request_iomux(MX31_PIN_NFCE_B, + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE)) { + return -EINVAL; + } + +#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) + mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */ + mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */ + mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */ + mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */ + mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ + mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ +#undef H2_PAD_CFG + + mxc_iomux_set_gpr(MUX_PGP_UH2, true); + + __raw_writew(PBC_BCTRL3_HSH_SEL, PBC_BASE_ADDRESS + PBC_BCTRL3_SET); /* enable HSH select */ + __raw_writew(PBC_BCTRL3_HSH_EN, PBC_BASE_ADDRESS + PBC_BCTRL3_CLEAR); /* enable HSH */ + + return 0; +} + +EXPORT_SYMBOL(gpio_usbh2_active); + +void gpio_usbh2_inactive(void) +{ + iomux_config_gpr(MUX_PGP_UH2, false); + + iomux_config_pad(MX31_PIN_USBH2_CLK, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + iomux_config_pad(MX31_PIN_USBH2_DIR, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + iomux_config_pad(MX31_PIN_USBH2_NXT, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + iomux_config_pad(MX31_PIN_USBH2_STP, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + iomux_config_pad(MX31_PIN_USBH2_DATA0, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + iomux_config_pad(MX31_PIN_USBH2_DATA1, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + iomux_config_pad(MX31_PIN_SRXD6, /* USBH2_DATA2 */ + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + iomux_config_pad(MX31_PIN_STXD6, /* USBH2_DATA3 */ + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + iomux_config_pad(MX31_PIN_SFS3, /* USBH2_DATA4 */ + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + iomux_config_pad(MX31_PIN_SCK3, /* USBH2_DATA5 */ + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + iomux_config_pad(MX31_PIN_SRXD3, /* USBH2_DATA6 */ + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + iomux_config_pad(MX31_PIN_STXD3, /* USBH2_DATA7 */ + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + + mxc_free_iomux(MX31_PIN_NFWE_B, + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_NFRE_B, + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_NFALE, + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_NFCLE, + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_NFWP_B, + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_NFCE_B, + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + + __raw_writew(PBC_BCTRL3_HSH_SEL, PBC_BASE_ADDRESS + PBC_BCTRL3_CLEAR); + __raw_writew(PBC_BCTRL3_HSH_EN, PBC_BASE_ADDRESS + PBC_BCTRL3_SET); +} + +EXPORT_SYMBOL(gpio_usbh2_inactive); + +/* + * USB OTG HS port + */ +int gpio_usbotg_hs_active(void) +{ + if (mxc_request_iomux(MX31_PIN_USBOTG_DATA0, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA1, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA2, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA3, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA4, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA5, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA6, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA7, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_CLK, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DIR, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_NXT, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_STP, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC)) { + return -EINVAL; + } + + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + + /* enable OTG/HS */ + __raw_writew(PBC_BCTRL3_OTG_HS_EN, PBC_BASE_ADDRESS + PBC_BCTRL3_CLEAR); + /* disable OTG/FS */ + __raw_writew(PBC_BCTRL3_OTG_FS_EN, PBC_BASE_ADDRESS + PBC_BCTRL3_SET); + return 0; +} + +EXPORT_SYMBOL(gpio_usbotg_hs_active); + +void gpio_usbotg_hs_inactive(void) +{ + /* Do nothing as pins doesn't have/support GPIO mode */ + +} + +EXPORT_SYMBOL(gpio_usbotg_hs_inactive); + +/* + * USB OTG FS port + */ +int gpio_usbotg_fs_active(void) +{ + if (mxc_request_iomux(MX31_PIN_USBOTG_DATA0, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA1, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA2, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA3, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA4, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA5, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA6, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA7, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_CLK, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DIR, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_NXT, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_STP, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USB_PWR, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC)) { + return -EINVAL; + } + + /* disable OTG/HS */ + __raw_writew(PBC_BCTRL3_OTG_HS_EN, PBC_BASE_ADDRESS + PBC_BCTRL3_SET); + /* enable OTG/FS */ + __raw_writew(PBC_BCTRL3_OTG_FS_EN, PBC_BASE_ADDRESS + PBC_BCTRL3_CLEAR); + +#if defined(CONFIG_MC13783_MXC) + /* Select PMIC transceiver */ + __raw_writew(PBC_BCTRL3_OTG_FS_SEL, PBC_BASE_ADDRESS + PBC_BCTRL3_CLEAR); +#endif + return 0; + +} + +EXPORT_SYMBOL(gpio_usbotg_fs_active); + +void gpio_usbotg_fs_inactive(void) +{ + /* Do nothing as pins doesn't have/support GPIO mode */ + +} + +EXPORT_SYMBOL(gpio_usbotg_fs_inactive); +/* *INDENT-ON* */ + +/*! + * Setup GPIO for PCMCIA interface + * + */ +void gpio_pcmcia_active(void) +{ + u16 temp; + + mxc_request_iomux(MX31_PIN_SDBA0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SDBA1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + + iomux_config_mux(MX31_PIN_LBA, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + iomux_config_mux(MX31_PIN_RW, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + iomux_config_mux(MX31_PIN_EB0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + iomux_config_mux(MX31_PIN_EB1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + iomux_config_mux(MX31_PIN_OE, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + + iomux_config_mux(MX31_PIN_IOIS16, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + iomux_config_mux(MX31_PIN_PC_BVD1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + iomux_config_mux(MX31_PIN_PC_BVD2, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + iomux_config_mux(MX31_PIN_PC_CD1_B, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + iomux_config_mux(MX31_PIN_PC_CD2_B, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + iomux_config_mux(MX31_PIN_PC_POE, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + iomux_config_mux(MX31_PIN_PC_PWRON, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + iomux_config_mux(MX31_PIN_PC_READY, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + iomux_config_mux(MX31_PIN_PC_RST, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + iomux_config_mux(MX31_PIN_PC_RW_B, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + iomux_config_mux(MX31_PIN_PC_VS1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + iomux_config_mux(MX31_PIN_PC_VS2, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + iomux_config_mux(MX31_PIN_PC_WAIT_B, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + + /* PCMCIA VPP, VCC Enable, 1 = power on */ + temp = PBC_BCTRL2_VPP_EN | PBC_BCTRL2_VCC_EN; + __raw_writew(temp, PBC_BASE_ADDRESS + PBC_BCTRL2_SET); + + /* Set up Card2 Select pin for PCMCIA, 0 = PCMCIA & SD2 */ + temp = PBC_BCTRL3_CARD2_SEL; + __raw_writew(temp, PBC_BASE_ADDRESS + PBC_BCTRL3_CLEAR); + + /* PCMCIA Enable, 0 = enable */ + temp = PBC_BCTRL4_PCMCIA_EN; + __raw_writew(temp, PBC_BASE_ADDRESS + PBC_BCTRL4_CLEAR); + mdelay(1); +} + +EXPORT_SYMBOL(gpio_pcmcia_active); + +/*! + * Setup GPIO for pcmcia to be inactive + */ +void gpio_pcmcia_inactive(void) +{ + u16 temp; + + /* PCMCIA Enable, 0 = enable */ + temp = PBC_BCTRL4_PCMCIA_EN; + __raw_writew(temp, PBC_BASE_ADDRESS + PBC_BCTRL4_SET); + + /* Set up Card2 Select pin for PCMCIA, 0 = PCMCIA & SD2 */ + temp = PBC_BCTRL3_CARD2_SEL; + __raw_writew(temp, PBC_BASE_ADDRESS + PBC_BCTRL3_SET); + + /* PCMCIA VPP, VCC Enable, 1 = power on */ + temp = PBC_BCTRL2_VPP_EN | PBC_BCTRL2_VCC_EN; + __raw_writew(temp, PBC_BASE_ADDRESS + PBC_BCTRL2_CLEAR); +} + +EXPORT_SYMBOL(gpio_pcmcia_inactive); +/*! + * Setup IR to be used by UART and FIRI + */ +void gpio_firi_init(void) +{ + gpio_uart_active(1, 0); +} + +EXPORT_SYMBOL(gpio_firi_init); + +/*! + * Setup IR to be used by UART + */ +void gpio_firi_inactive(void) +{ + unsigned int pbc_bctrl2_set = 0, pbc_bctrl2_clr = 0; + + iomux_config_gpr(MUX_PGP_FIRI, false); + mxc_request_iomux(MX31_PIN_TXD2, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_RXD2, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + + pbc_bctrl2_set |= PBC_BCTRL2_IRDA_MOD; + __raw_writew(pbc_bctrl2_set, PBC_BASE_ADDRESS + PBC_BCTRL2_SET); + + pbc_bctrl2_clr |= PBC_BCTRL2_IRDA_MOD; + __raw_writew(pbc_bctrl2_clr, PBC_BASE_ADDRESS + PBC_BCTRL2_CLEAR); +} + +EXPORT_SYMBOL(gpio_firi_inactive); + +/*! + * Setup IR to be used by FIRI + */ +void gpio_firi_active(void *fir_cong_reg_base, unsigned int tpp_mask) +{ + unsigned int pbc_bctrl2_set = 0, pbc_bctrl2_clr = 0; + unsigned int cr; + + iomux_config_gpr(MUX_PGP_FIRI, true); + + cr = readl(fir_cong_reg_base); + cr &= ~tpp_mask; + writel(cr, fir_cong_reg_base); + + pbc_bctrl2_clr |= PBC_BCTRL2_IRDA_MOD; + __raw_writew(pbc_bctrl2_clr, PBC_BASE_ADDRESS + PBC_BCTRL2_CLEAR); + + pbc_bctrl2_set |= PBC_BCTRL2_IRDA_MOD; + __raw_writew(pbc_bctrl2_set, PBC_BASE_ADDRESS + PBC_BCTRL2_SET); + + cr = readl(fir_cong_reg_base); + cr |= tpp_mask; + writel(cr, fir_cong_reg_base); + + __raw_writew(pbc_bctrl2_clr, PBC_BASE_ADDRESS + PBC_BCTRL2_CLEAR); + + cr = readl(fir_cong_reg_base); + cr &= ~tpp_mask; + writel(cr, fir_cong_reg_base); +} + +EXPORT_SYMBOL(gpio_firi_active); diff -urN linux-2.6.26/arch/arm/mach-mx3/mx3_3stack.c linux-2.6.26-lab126/arch/arm/mach-mx3/mx3_3stack.c --- linux-2.6.26/arch/arm/mach-mx3/mx3_3stack.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/mx3_3stack.c 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,1081 @@ +/* + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE) +#include +#include +#include + +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "board-mx3_3stack.h" +#include "crm_regs.h" +#include "iomux.h" +/*! + * @file mach-mx3/mx3_3stack.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX31 + */ + +extern void mxc_map_io(void); +extern void mxc_init_irq(void); +extern void mxc_cpu_init(void) __init; +extern struct sys_timer mxc_timer; +extern void mxc_cpu_common_init(void); +extern int mxc_clocks_init(void); +extern void __init early_console_setup(char *); +extern int mxc_init_devices(void); + +static void mxc_nop_release(struct device *dev) +{ + /* Nothing */ +} + +unsigned long board_get_ckih_rate(void) +{ + return 26000000; +} + +#if defined(CONFIG_KEYBOARD_MXC) || defined(CONFIG_KEYBOARD_MXC_MODULE) +static u16 keymapping[12] = { + KEY_UP, KEY_DOWN, 0, 0, + KEY_RIGHT, KEY_LEFT, KEY_ENTER, 0, + KEY_F6, KEY_F8, KEY_F9, KEY_F10, +}; + +static struct resource mxc_kpp_resources[] = { + [0] = { + .start = MXC_INT_KPP, + .end = MXC_INT_KPP, + .flags = IORESOURCE_IRQ, + } +}; + +static struct keypad_data keypad_plat_data = { + .rowmax = 3, + .colmax = 4, + .irq = MXC_INT_KPP, + .learning = 0, + .delay = 2, + .matrix = keymapping, +}; + +/* mxc keypad driver */ +static struct platform_device mxc_keypad_device = { + .name = "mxc_keypad", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_kpp_resources), + .resource = mxc_kpp_resources, + .dev = { + .release = mxc_nop_release, + .platform_data = &keypad_plat_data, + }, +}; + +static void mxc_init_keypad(void) +{ + (void)platform_device_register(&mxc_keypad_device); +} +#else +static inline void mxc_init_keypad(void) +{ +} +#endif + +/* MTD NAND flash */ +#if defined(CONFIG_MTD_NAND_MXC) || defined(CONFIG_MTD_NAND_MXC_MODULE) \ + || defined(CONFIG_MTD_NAND_MXC_V2) || defined(CONFIG_MTD_NAND_MXC_V2_MODULE) + +static struct mtd_partition mxc_nand_partitions[] = { + { + .name = "nand.bootloader", + .offset = 0, + .size = 1024 * 1024}, + { + .name = "nand.kernel", + .offset = MTDPART_OFS_APPEND, + .size = 5 * 1024 * 1024}, + { + .name = "nand.rootfs", + .offset = MTDPART_OFS_APPEND, + .size = 96 * 1024 * 1024}, + { + .name = "nand.configure", + .offset = MTDPART_OFS_APPEND, + .size = 8 * 1024 * 1024}, + { + .name = "nand.userfs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL}, +}; + +static struct flash_platform_data mxc_nand_data = { + .parts = mxc_nand_partitions, + .nr_parts = ARRAY_SIZE(mxc_nand_partitions), + .width = 1, +}; + +static struct platform_device mxc_nand_mtd_device = { + .name = "mxc_nand_flash", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_nand_data, + }, +}; + +static struct platform_device mxc_nandv2_mtd_device = { + .name = "mxc_nandv2_flash", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_nand_data, + }, +}; + +static void mxc_init_nand_mtd(void) +{ + if (__raw_readl(MXC_CCM_RCSR) & MXC_CCM_RCSR_NF16B) { + mxc_nand_data.width = 2; + } + if (cpu_is_mx31()) { + (void)platform_device_register(&mxc_nand_mtd_device); + } + if (cpu_is_mx32()) { + (void)platform_device_register(&mxc_nandv2_mtd_device); + } +} +#else +static inline void mxc_init_nand_mtd(void) +{ +} +#endif + +static void lcd_reset(void) +{ + /* ensure that LCDIO(1.8V) has been turn on */ + /* active reset line GPIO */ + mxc_request_iomux(MX31_PIN_LCS1, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_set_gpio_dataout(MX31_PIN_LCS1, 0); + mxc_set_gpio_direction(MX31_PIN_LCS1, 0); + /* do reset */ + msleep(10); /* tRES >= 100us */ + mxc_set_gpio_dataout(MX31_PIN_LCS1, 1); + msleep(60); +#ifdef CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL + mxc_set_gpio_dataout(MX31_PIN_LCS1, 0); +#endif +} + +static struct mxc_lcd_platform_data lcd_data = { + .io_reg = "VGEN", +#ifdef CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL + .core_reg = "GPO1", +#else + .core_reg = "VMMC1", +#endif + .reset = lcd_reset, +}; + +static struct mxc_camera_platform_data camera_data = { + .core_regulator = "VVIB", + .io_regulator = "VMMC1", + .analog_regulator = "SW2B_NORMAL", + .gpo_regulator = "GPO3", + .mclk = 27000000, +}; + +struct mxc_tvout_platform_data tvout_data = { + .io_reg = "VGEN", + .core_reg = "GPO3", + .analog_reg = "GPO1", + .detect_line = MX31_PIN_BATT_LINE, +}; + +void si4702_reset(void) +{ + mxc_set_gpio_dataout(MX31_PIN_SRST0, 0); + msleep(100); + mxc_set_gpio_dataout(MX31_PIN_SRST0, 1); + msleep(100); +} + +void si4702_clock_ctl(int flag) +{ + mxc_set_gpio_dataout(MX31_PIN_SIMPD0, flag); +} + +static void si4702_gpio_get(void) +{ + /* reset pin */ + mxc_request_iomux(MX31_PIN_SRST0, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_set_gpio_direction(MX31_PIN_SRST0, 0); + + mxc_request_iomux(MX31_PIN_SIMPD0, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_set_gpio_direction(MX31_PIN_SIMPD0, 0); +} + +static void si4702_gpio_put(void) +{ + mxc_free_iomux(MX31_PIN_SRST0, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_SIMPD0, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); +} + +static struct mxc_fm_platform_data si4702_data = { + .reg_vio = "GPO3", + .reg_vdd = "VMMC1", + .gpio_get = si4702_gpio_get, + .gpio_put = si4702_gpio_put, + .reset = si4702_reset, + .clock_ctl = si4702_clock_ctl, +}; + +/* setup GPIO for mma7450 */ +static void gpio_mma7450_get(void) +{ + mxc_request_iomux(MX31_PIN_STX0, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO); + mxc_iomux_set_pad(MX31_PIN_STX0, PAD_CTL_PKE_NONE); + mxc_set_gpio_direction(MX31_PIN_STX0, 1); + + mxc_request_iomux(MX31_PIN_SRX0, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO); + mxc_iomux_set_pad(MX31_PIN_SRX0, PAD_CTL_PKE_NONE); + mxc_set_gpio_direction(MX31_PIN_SRX0, 1); +} + +static void gpio_mma7450_put(void) +{ + mxc_free_iomux(MX31_PIN_STX0, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_SRX0, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO); +} + +static struct mxc_mma7450_platform_data mma7450_data = { + .reg_dvdd_io = "GPO3", + .reg_avdd = "VMMC1", + .gpio_pin_get = gpio_mma7450_get, + .gpio_pin_put = gpio_mma7450_put, + .int1 = IOMUX_TO_IRQ(MX31_PIN_STX0), + .int2 = IOMUX_TO_IRQ(MX31_PIN_SRX0), +}; + +static struct i2c_board_info mxc_i2c_board_info[] __initdata = { + { + .type = "ov2640", + .addr = 0x30, + .platform_data = (void *)&camera_data,}, + { + .type = "ch7024", + .addr = 0x76, + .platform_data = (void *)&tvout_data, + .irq = IOMUX_TO_IRQ(MX31_PIN_BATT_LINE),}, + { + .type = "si4702", + .addr = 0x10, + .platform_data = (void *)&si4702_data, + }, + { + .type = "mma7450", + .addr = 0x1d, + .platform_data = (void *)&mma7450_data, + }, +}; + +static struct spi_board_info mxc_spi_board_info[] __initdata = { + { + .modalias = "pmic_spi", + .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), + .max_speed_hz = 4000000, + .bus_num = 2, + .platform_data = (void *)IOMUX_TO_IRQ(MX31_PIN_GPIO1_2), + .chip_select = 2,}, + { + .modalias = "lcd_spi", + .platform_data = (void *)&lcd_data, + .max_speed_hz = 5000000, + .bus_num = 1, + .chip_select = 2,}, +}; + +/*lan9217 device*/ +#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) +static struct resource smsc911x_resources[] = { + { + .start = LAN9217_BASE_ADDR, + .end = LAN9217_BASE_ADDR + 0x100, + .flags = IORESOURCE_MEM, + }, + { + .start = LAN9217_IRQ, + .end = LAN9217_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct platform_device smsc_lan9217_device = { + .name = "smsc911x", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, +}; +static void mxc_init_enet(void) +{ + (void)platform_device_register(&smsc_lan9217_device); +} +#else +static inline void mxc_init_enet(void) +{ +} +#endif + +#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) +static const char fb_default_mode[] = "Epson-VGA"; + +/* mxc lcd driver */ +static struct platform_device mxc_fb_device = { + .name = "mxc_sdc_fb", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &fb_default_mode, + .coherent_dma_mask = 0xFFFFFFFF, + }, +}; + +static struct platform_device mxc_fb_wvga_device = { + .name = "lcd_claa", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &lcd_data, + }, +}; + +static void mxc_init_fb(void) +{ + (void)platform_device_register(&mxc_fb_device); + (void)platform_device_register(&mxc_fb_wvga_device); +} +#else +static inline void mxc_init_fb(void) +{ +} +#endif + +#if defined(CONFIG_BACKLIGHT_MXC) +static struct platform_device mxcbl_devices[] = { +#if defined(CONFIG_BACKLIGHT_MXC_IPU) || defined(CONFIG_BACKLIGHT_MXC_IPU_MODULE) + { + .name = "mxc_ipu_bl", + .id = 0, + .dev = { + .platform_data = (void *)3, /* DISP # for this backlight */ + }, + }, +#endif +}; +static inline void mxc_init_bl(void) +{ + int i; + for (i = 0; i < ARRAY_SIZE(mxcbl_devices); i++) { + platform_device_register(&mxcbl_devices[i]); + } +} +#else +static inline void mxc_init_bl(void) +{ +} +#endif + +#if defined(CONFIG_FB_MXC_TVOUT_CH7024) || \ + defined(CONFIG_FB_MXC_TVOUT_CH7024_MODULE) +static int mxc_init_ch7024(void) +{ + /* request gpio for phone jack detect */ + mxc_request_iomux(MX31_PIN_BATT_LINE, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_iomux_set_pad(MX31_PIN_BATT_LINE, PAD_CTL_PKE_NONE); + mxc_set_gpio_direction(MX31_PIN_BATT_LINE, 1); + + return 0; +} +#else +static inline int mxc_init_ch7024(void) +{ + return 0; +} +#endif + +static u32 brd_io; + +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) +{ + u32 imr_val; + u32 int_valid; + u32 expio_irq; + + desc->chip->mask(irq); /* irq = gpio irq number */ + + imr_val = __raw_readw(brd_io + INTR_MASK_REG); + int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val; + + if (unlikely(!int_valid)) { + goto out; + } + + expio_irq = MXC_EXP_IO_BASE; + for (; int_valid != 0; int_valid >>= 1, expio_irq++) { + struct irq_desc *d; + if ((int_valid & 1) == 0) + continue; + d = irq_desc + expio_irq; + if (unlikely(!(d->handle_irq))) { + printk(KERN_ERR "\nEXPIO irq: %d unhandled\n", + expio_irq); + BUG(); /* oops */ + } + d->handle_irq(expio_irq, d); + } + + out: + desc->chip->ack(irq); + desc->chip->unmask(irq); +} + +/* + * Disable an expio pin's interrupt by setting the bit in the imr. + * @param irq an expio virtual irq number + */ +static void expio_mask_irq(u32 irq) +{ + u16 reg; + u32 expio = MXC_IRQ_TO_EXPIO(irq); + /* mask the interrupt */ + reg = __raw_readw(brd_io + INTR_MASK_REG); + reg |= (1 << expio); + __raw_writew(reg, brd_io + INTR_MASK_REG); +} + +/* + * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. + * @param irq an expanded io virtual irq number + */ +static void expio_ack_irq(u32 irq) +{ + u32 expio = MXC_IRQ_TO_EXPIO(irq); + /* clear the interrupt status */ + __raw_writew(1 << expio, brd_io + INTR_RESET_REG); + __raw_writew(0, brd_io + INTR_RESET_REG); + /* mask the interrupt */ + expio_mask_irq(irq); +} + +/* + * Enable a expio pin's interrupt by clearing the bit in the imr. + * @param irq a expio virtual irq number + */ +static void expio_unmask_irq(u32 irq) +{ + u16 reg; + u32 expio = MXC_IRQ_TO_EXPIO(irq); + /* unmask the interrupt */ + reg = __raw_readw(brd_io + INTR_MASK_REG); + reg &= ~(1 << expio); + __raw_writew(reg, brd_io + INTR_MASK_REG); +} + +static struct irq_chip expio_irq_chip = { + .ack = expio_ack_irq, + .mask = expio_mask_irq, + .unmask = expio_unmask_irq, +}; + +static int __init mxc_expio_init(void) +{ + int i; + + brd_io = (u32) ioremap(BOARD_IO_ADDR, SZ_4K); + if (brd_io == 0) + return -ENOMEM; + + if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) || + (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) || + (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) { + iounmap((void *)brd_io); + brd_io = 0; + return -ENODEV; + } + + pr_info("3-Stack Debug board detected, rev = 0x%04X\n", + readw(brd_io + CPLD_CODE_VER_REG)); + + /* + * Configure INT line as GPIO input + */ + mxc_request_iomux(MX31_PIN_GPIO1_1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_set_gpio_direction(MX31_PIN_GPIO1_1, 1); + + /* disable the interrupt and clear the status */ + __raw_writew(0, brd_io + INTR_MASK_REG); + __raw_writew(0xFFFF, brd_io + INTR_RESET_REG); + __raw_writew(0, brd_io + INTR_RESET_REG); + __raw_writew(0x1F, brd_io + INTR_MASK_REG); + for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); + i++) { + set_irq_chip(i, &expio_irq_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + set_irq_type(EXPIO_PARENT_INT, IRQT_LOW); + set_irq_chained_handler(EXPIO_PARENT_INT, mxc_expio_irq_handler); + + return 0; +} + +static int __init mxc_init_regulator(void) +{ + int err; + struct regulator *gpo1; + struct regulator *gpo2; + struct regulator *gpo3; + struct regulator *gpo4; + + gpo1 = regulator_get(NULL, "GPO1"); + gpo2 = regulator_get(NULL, "GPO2"); + gpo3 = regulator_get(NULL, "GPO3"); + gpo4 = regulator_get(NULL, "GPO4"); + + err = regulator_set_platform_source(gpo2, gpo1); + if (err) + printk(KERN_ERR "Unable to set GPO1 be the parent of GPO2\n"); + + err = regulator_set_platform_source(gpo3, gpo1); + if (err) + printk(KERN_ERR "Unable to set GPO1 be the parent of GPO3\n"); + + err = regulator_set_platform_source(gpo4, gpo1); + if (err) + printk(KERN_ERR "Unable to set GPO1 be the parent of GPO4\n"); + + return 0; +} + +module_init(mxc_init_regulator); + +#if (defined(CONFIG_MXC_PMIC_MC13783) || \ + defined(CONFIG_MXC_PMIC_MC13783_MODULE)) \ + && (defined(CONFIG_SND_MXC_PMIC) || defined(CONFIG_SND_MXC_PMIC_MODULE)) +static void __init mxc_init_pmic_audio(void) +{ + struct clk *ckih_clk; + struct clk *cko_clk; + + /* Enable 26 mhz clock on CKO1 for PMIC audio */ + ckih_clk = clk_get(NULL, "ckih"); + cko_clk = clk_get(NULL, "cko1_clk"); + if (IS_ERR(ckih_clk) || IS_ERR(cko_clk)) { + printk(KERN_ERR "Unable to set CKO1 output to CKIH\n"); + } else { + clk_set_parent(cko_clk, ckih_clk); + clk_set_rate(cko_clk, clk_get_rate(ckih_clk)); + clk_enable(cko_clk); + } + clk_put(ckih_clk); + clk_put(cko_clk); + + /* config Audio ports (4 & 5) */ + mxc_request_iomux(MX31_PIN_SCK4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SRXD4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_STXD4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SFS4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SCK5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SRXD5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_STXD5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SFS5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); +} +#else +static void __inline mxc_init_pmic_audio(void) +{ +} +#endif + +/* MMC device data */ + +#if defined(CONFIG_MMC_MXC) || defined(CONFIG_MMC_MXC_MODULE) +static struct mxc_mmc_platform_data mmc0_data = { + .ocr_mask = MMC_VDD_32_33, + .min_clk = 150000, + .max_clk = 25000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .power_mmc = "GPO1", +}; + +/*! + * Resource definition for the SDHC1 + */ +static struct resource mxcsdhc1_resources[] = { + [0] = { + .start = MMC_SDHC1_BASE_ADDR, + .end = MMC_SDHC1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_MMC_SDHC1, + .end = MXC_INT_MMC_SDHC1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mxc_mmc_platform_data mmc1_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | + MMC_VDD_31_32, + .min_clk = 150000, + .max_clk = 25000000, + .card_fixed = 1, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .power_mmc = "VMMC2", +}; + +/*! + * Resource definition for the SDHC1 + */ +static struct resource mxcsdhc2_resources[] = { + [0] = { + .start = MMC_SDHC2_BASE_ADDR, + .end = MMC_SDHC2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_MMC_SDHC2, + .end = MXC_INT_MMC_SDHC2, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Device Definition for MXC SDHC1 */ +static struct platform_device mxcsdhc1_device = { + .name = "mxcmci", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc0_data, + }, + .num_resources = ARRAY_SIZE(mxcsdhc1_resources), + .resource = mxcsdhc1_resources, +}; + +/*! Device Definition for MXC SDHC2 */ +static struct platform_device mxcsdhc2_device = { + .name = "mxcmci", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc1_data, + }, + .num_resources = ARRAY_SIZE(mxcsdhc2_resources), + .resource = mxcsdhc2_resources, +}; + +static inline void mxc_init_mmc(void) +{ + int cd_irq; + + cd_irq = sdhc_init_card_det(0); + if (cd_irq) { + mxcsdhc1_device.resource[2].start = cd_irq; + mxcsdhc1_device.resource[2].end = cd_irq; + } + + cd_irq = sdhc_init_card_det(1); + if (cd_irq) { + mxcsdhc2_device.resource[2].start = cd_irq; + mxcsdhc2_device.resource[2].end = cd_irq; + } + + spba_take_ownership(SPBA_SDHC1, SPBA_MASTER_A | SPBA_MASTER_C); + (void)platform_device_register(&mxcsdhc1_device); + + spba_take_ownership(SPBA_SDHC2, SPBA_MASTER_A | SPBA_MASTER_C); + (void)platform_device_register(&mxcsdhc2_device); +} +#else +static inline void mxc_init_mmc(void) +{ +} +#endif + +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mxc_cpu_init(); + +#ifdef CONFIG_DISCONTIGMEM + do { + int nid; + mi->nr_banks = MXC_NUMNODES; + for (nid = 0; nid < mi->nr_banks; nid++) { + SET_NODE(mi, nid); + } + } while (0); +#endif +} + +/* IDE device data */ +#if defined(CONFIG_BLK_DEV_IDE_MXC) || defined(CONFIG_BLK_DEV_IDE_MXC_MODULE) + +/*! Platform Data for MXC IDE */ +static struct mxc_ide_platform_data mxc_ide_data = { + .power_drive = "GPO2", + .power_io = "GPO3", +}; + +static struct platform_device mxc_ide_device = { + .name = "mxc_ide", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_ide_data, + }, +}; + +static inline void mxc_init_ide(void) +{ + if (platform_device_register(&mxc_ide_device) < 0) + printk(KERN_ERR "Error: Registering the ide.\n"); +} +#else +static inline void mxc_init_ide(void) +{ +} +#endif + +#if defined(CONFIG_PATA_FSL) || defined(CONFIG_PATA_FSL_MODULE) +extern void gpio_ata_active(void); +extern void gpio_ata_inactive(void); + +static int ata_init(struct platform_device *pdev) +{ + /* Configure the pins */ + gpio_ata_active(); + + return 0; +} + +static void ata_exit(void) +{ + /* Free the pins */ + gpio_ata_inactive(); +} + +static struct fsl_ata_platform_data ata_data = { + .udma_mask = ATA_UDMA3, /* board can handle up to UDMA3 */ + .mwdma_mask = ATA_MWDMA2, + .pio_mask = ATA_PIO4, + .fifo_alarm = MXC_IDE_DMA_WATERMARK / 2, + .max_sg = MXC_IDE_DMA_BD_NR, + .init = ata_init, + .exit = ata_exit, + .core_reg = "GPO2", /*"LDO2", */ + .io_reg = "GPO3", /*"LDO3", */ +}; + +static struct resource pata_fsl_resources[] = { + [0] = { /* I/O */ + .start = ATA_BASE_ADDR + 0x00, + .end = ATA_BASE_ADDR + 0xD8, + .flags = IORESOURCE_MEM, + }, + [2] = { /* IRQ */ + .start = MXC_INT_ATA, + .end = MXC_INT_ATA, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pata_fsl_device = { + .name = "pata_fsl", + .id = -1, + .num_resources = ARRAY_SIZE(pata_fsl_resources), + .resource = pata_fsl_resources, + .dev = { + .platform_data = &ata_data, + .coherent_dma_mask = ~0, + }, +}; + +static void __init mxc_init_pata(void) +{ + (void)platform_device_register(&pata_fsl_device); +} +#else /* CONFIG_PATA_FSL */ +static void __init mxc_init_pata(void) +{ +} +#endif /* CONFIG_PATA_FSL */ + +static void bt_reset(void) +{ + mxc_set_gpio_dataout(MX31_PIN_DCD_DCE1, 1); +} + +static struct mxc_bt_platform_data mxc_bt_data = { + .bt_vdd = "VMMC2", + .bt_vdd_parent = "GPO1", + .bt_vusb = NULL, + .bt_vusb_parent = "GPO3", + .bt_reset = bt_reset, +}; + +static struct platform_device mxc_bt_device = { + .name = "mxc_bt", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_bt_data, + }, +}; + +static void mxc_init_bluetooth(void) +{ + (void)platform_device_register(&mxc_bt_device); +} + +static void mxc_unifi_hardreset(void) +{ + mxc_set_gpio_dataout(MX31_PIN_DCD_DCE1, 0); + msleep(100); + mxc_set_gpio_dataout(MX31_PIN_DCD_DCE1, 1); +} + +static struct mxc_unifi_platform_data unifi_data = { + .hardreset = mxc_unifi_hardreset, + + /* GPO3 -> enables SW2B 1.8V out - this becomes 1V8 on personality + * board, then 1V8_EXT, then BT_VUSB + */ + .reg_gpo1 = "GPO3", + + /* GPO4 -> WiFi_PWEN, but this signal is not used on current boards */ + .reg_gpo2 = "GPO4", + + .reg_1v5_ana_bb = "VRF1", /* VRF1 -> WL_1V5ANA and WL_1V5BB */ + .reg_vdd_vpa = "VMMC2", /* VMMC2 -> WL_VDD and WL_VPA */ + .reg_1v5_dd = "VRF2", /* VRF2 -> WL_1V5DD */ + + .host_id = 1, +}; + +struct mxc_unifi_platform_data *get_unifi_plat_data(void) +{ + return &unifi_data; +} + +EXPORT_SYMBOL(get_unifi_plat_data); + +#if defined(CONFIG_GPS_IOCTRL) || defined(CONFIG_GPS_IOCTRL_MODULE) +static struct mxc_gps_platform_data gps_data = { + .core_reg = "GPO3", + .analog_reg = "GPO1", +}; + +static struct platform_device mxc_gps_device = { + .name = "gps_ioctrl", + .id = -1, + .dev = { + .platform_data = &gps_data, + }, +}; + +static void __init mxc_init_gps(void) +{ + (void)platform_device_register(&mxc_gps_device); +} +#else +static void __init mxc_init_gps(void) +{ +} +#endif + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + /* config CS5 for debug board */ + mxc_request_iomux(MX31_PIN_CS5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + + mxc_cpu_common_init(); + mxc_clocks_init(); + mxc_gpio_init(); + early_console_setup(saved_command_line); + mxc_init_devices(); + + /*Pull down MX31_PIN_USB_BYP to reset USB3317 */ + mxc_request_iomux(MX31_PIN_USB_BYP, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_set_gpio_direction(MX31_PIN_USB_BYP, 0); + mxc_set_gpio_dataout(MX31_PIN_USB_BYP, 0); + mxc_free_iomux(MX31_PIN_USB_BYP, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + + /* Reset BT/WiFi chip */ + mxc_request_iomux(MX31_PIN_DCD_DCE1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_set_gpio_direction(MX31_PIN_DCD_DCE1, 0); + mxc_set_gpio_dataout(MX31_PIN_DCD_DCE1, 0); + + mxc_init_pmic_audio(); + mxc_expio_init(); + mxc_init_keypad(); + mxc_init_enet(); + mxc_init_nand_mtd(); + mxc_init_ch7024(); + + i2c_register_board_info(0, mxc_i2c_board_info, + ARRAY_SIZE(mxc_i2c_board_info)); + spi_register_board_info(mxc_spi_board_info, + ARRAY_SIZE(mxc_spi_board_info)); + + mxc_init_fb(); + mxc_init_bl(); + mxc_init_mmc(); + mxc_init_ide(); + mxc_init_pata(); + mxc_init_bluetooth(); + mxc_init_gps(); +} + +#define PLL_PCTL_REG(pd, mfd, mfi, mfn) \ + ((((pd) - 1) << 26) + (((mfd) - 1) << 16) + ((mfi) << 10) + mfn) + +/* For 26MHz input clock */ +#define PLL_532MHZ PLL_PCTL_REG(1, 13, 10, 3) +#define PLL_399MHZ PLL_PCTL_REG(1, 52, 7, 35) +#define PLL_133MHZ PLL_PCTL_REG(2, 26, 5, 3) + +#define PDR0_REG(mcu, max, hsp, ipg, nfc) \ + (MXC_CCM_PDR0_MCU_DIV_##mcu | MXC_CCM_PDR0_MAX_DIV_##max | \ + MXC_CCM_PDR0_HSP_DIV_##hsp | MXC_CCM_PDR0_IPG_DIV_##ipg | \ + MXC_CCM_PDR0_NFC_DIV_##nfc) + +/* working point(wp): 0 - 133MHz; 1 - 266MHz; 2 - 399MHz; 3 - 532MHz */ +/* 26MHz input clock table */ +static struct cpu_wp cpu_wp_26[] = { + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 133000000, + .pdr0_reg = PDR0_REG(4, 4, 4, 2, 6),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 266000000, + .pdr0_reg = PDR0_REG(2, 4, 4, 2, 6),}, + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 399000000, + .pdr0_reg = PDR0_REG(1, 3, 3, 2, 6),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 532000000, + .pdr0_reg = PDR0_REG(1, 4, 4, 2, 6),}, +}; + +struct cpu_wp *get_cpu_wp(int *wp) +{ + *wp = 4; + return cpu_wp_26; +} + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX3_3STACK data structure. + */ +/* *INDENT-OFF* */ +MACHINE_START(MX31_3DS, "Freescale MX31/MX32 3-Stack Board") + /* Maintainer: Freescale Semiconductor, Inc. */ + .phys_io = AIPS1_BASE_ADDR, + .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .fixup = fixup_mxc_board, + .map_io = mxc_map_io, + .init_irq = mxc_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff -urN linux-2.6.26/arch/arm/mach-mx3/mx3_3stack_gpio.c linux-2.6.26-lab126/arch/arm/mach-mx3/mx3_3stack_gpio.c --- linux-2.6.26/arch/arm/mach-mx3/mx3_3stack_gpio.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/mx3_3stack_gpio.c 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,1298 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board-mx3_3stack.h" +#include "iomux.h" + +/*! + * @file mach-mx3/mx3_3stack_gpio.c + * + * @brief This file contains all the GPIO setup functions for the board. + * + * @ingroup GPIO_MX31 + */ + +/*! + * Setup GPIO for a UART port to be active + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_active(int port, int no_irda) +{ + /* + * Configure the IOMUX control registers for the UART signals + */ + switch (port) { + /* UART 1 IOMUX Configs */ + case 0: + mxc_request_iomux(MX31_PIN_RXD1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_TXD1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_RTS1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CTS1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + break; + /* UART 2 IOMUX Configs */ + case 1: + mxc_request_iomux(MX31_PIN_TXD2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_RXD2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + + mxc_request_iomux(MX31_PIN_RTS2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CTS2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + break; + /* UART 3 IOMUX Configs */ + case 2: + mxc_request_iomux(MX31_PIN_CSPI3_MOSI, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_CSPI3_MISO, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_CSPI3_SCLK, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_CSPI3_SPI_RDY, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + break; + default: + break; + } + + /* + * TODO: Configure the Pad registers for the UART pins + */ +} + +/*! + * Setup GPIO for a UART port to be inactive + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_inactive(int port, int no_irda) +{ + switch (port) { + case 0: + mxc_request_gpio(MX31_PIN_RXD1); + mxc_request_gpio(MX31_PIN_TXD1); + mxc_request_gpio(MX31_PIN_RTS1); + mxc_request_gpio(MX31_PIN_CTS1); + + mxc_free_iomux(MX31_PIN_RXD1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_TXD1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_RTS1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_CTS1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + break; + case 1: + mxc_request_gpio(MX31_PIN_TXD2); + mxc_request_gpio(MX31_PIN_RXD2); + + mxc_free_iomux(MX31_PIN_TXD2, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_RXD2, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_RTS2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CTS2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + break; + default: + break; + } +} + +/*! + * Configure the IOMUX GPR register to receive shared SDMA UART events + * + * @param port a UART port + */ +void config_uartdma_event(int port) +{ + switch (port) { + case 1: + /* Configure to receive UART 2 SDMA events */ + mxc_iomux_set_gpr(MUX_PGP_FIRI, false); + break; + case 2: + /* Configure to receive UART 3 SDMA events */ + mxc_iomux_set_gpr(MUX_CSPI1_UART3, true); + break; + case 4: + /* Configure to receive UART 5 SDMA events */ + mxc_iomux_set_gpr(MUX_CSPI3_UART5_SEL, true); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_uart_active); +EXPORT_SYMBOL(gpio_uart_inactive); +EXPORT_SYMBOL(config_uartdma_event); + +/*! + * Setup GPIO for Keypad to be active + * + */ +void gpio_keypad_active(void) +{ + /* + * Configure the IOMUX control register for keypad signals. + */ + mxc_request_iomux(MX31_PIN_KEY_COL0, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_COL1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_COL2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_COL3, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_ROW0, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_ROW1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_KEY_ROW2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); +} + +EXPORT_SYMBOL(gpio_keypad_active); + +/*! + * Setup GPIO for Keypad to be inactive + * + */ +void gpio_keypad_inactive(void) +{ + mxc_request_gpio(MX31_PIN_KEY_COL0); + mxc_request_gpio(MX31_PIN_KEY_COL1); + mxc_request_gpio(MX31_PIN_KEY_COL2); + mxc_request_gpio(MX31_PIN_KEY_COL3); + mxc_request_gpio(MX31_PIN_KEY_ROW0); + mxc_request_gpio(MX31_PIN_KEY_ROW1); + mxc_request_gpio(MX31_PIN_KEY_ROW2); + + mxc_free_iomux(MX31_PIN_KEY_COL0, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_KEY_COL1, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_KEY_COL2, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_KEY_COL3, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_KEY_ROW0, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_KEY_ROW1, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_KEY_ROW2, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO); +} + +EXPORT_SYMBOL(gpio_keypad_inactive); + +void gpio_power_key_active(void) +{ + mxc_request_iomux(MX31_PIN_GPIO1_2, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_set_gpio_direction(MX31_PIN_GPIO1_2, 1); + mxc_iomux_set_pad(MX31_PIN_GPIO1_2, PAD_CTL_PKE_NONE); +} + +EXPORT_SYMBOL(gpio_power_key_active); + +/*! + * Setup GPIO for a CSPI device to be active + * + * @param cspi_mod an CSPI device + */ +void gpio_spi_active(int cspi_mod) +{ + switch (cspi_mod) { + case 0: + /* SPI1 */ + /* setup GPR for CSPI BB */ + iomux_config_gpr(MUX_PGP_CSPI_BB, true); + /* CSPI1 clock and RDY use full UART ALT1 mode */ + mxc_request_iomux(MX31_PIN_DSR_DCE1, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_RI_DCE1, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + break; + case 1: + /* SPI2 */ + mxc_request_iomux(MX31_PIN_CSPI2_MISO, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_MOSI, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_SCLK, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_SPI_RDY, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_SS0, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_SS2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + break; + case 2: + /* SPI3 */ + /* + mxc_request_iomux(MX31_PIN_CSPI2_MISO, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_MOSI, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_SCLK, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_SPI_RDY, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_SS0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_SS1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSPI2_SS2, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + */ + break; + default: + break; + } +} + +/*! + * Setup 1-Wire to be active + */ +void gpio_owire_active(void) +{ + /* + * Configure the IOMUX control register for 1-wire signals. + */ + iomux_config_mux(MX31_PIN_BATT_LINE, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + iomux_config_pad(MX31_PIN_BATT_LINE, PAD_CTL_LOOPBACK); +} + +/*! + * Setup 1-Wire to be active + */ +void gpio_owire_inactive(void) +{ + /* + * Configure the IOMUX control register for 1-wire signals. + */ + iomux_config_mux(MX31_PIN_BATT_LINE, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); +} + +EXPORT_SYMBOL(gpio_owire_active); +EXPORT_SYMBOL(gpio_owire_inactive); + +/*! + * Setup GPIO for a CSPI device to be inactive + * + * @param cspi_mod a CSPI device + */ +void gpio_spi_inactive(int cspi_mod) +{ + switch (cspi_mod) { + case 0: + /* SPI1 */ + /* setup GPR for CSPI BB */ + iomux_config_gpr(MUX_PGP_CSPI_BB, false); + /* CSPI1 clock and RDY use full UART ALT1 mode */ + mxc_free_iomux(MX31_PIN_DSR_DCE1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_RI_DCE1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + break; + case 1: + /* SPI2 */ + mxc_free_iomux(MX31_PIN_CSPI2_MISO, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSPI2_MOSI, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSPI2_SCLK, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSPI2_SPI_RDY, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSPI2_SS0, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSPI2_SS2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + break; + case 2: + /* SPI3 */ + break; + default: + break; + } +} + +/*! + * Setup GPIO for an I2C device to be active + * + * @param i2c_num an I2C device + */ +void gpio_i2c_active(int i2c_num) +{ + switch (i2c_num) { + case 0: + mxc_request_iomux(MX31_PIN_I2C_CLK, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_I2C_DAT, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + break; + case 1: + mxc_request_iomux(MX31_PIN_CSPI2_MOSI, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_CSPI2_MISO, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + break; + case 2: + mxc_request_iomux(MX31_PIN_CSPI2_SS2, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_CSPI2_SCLK, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + break; + default: + break; + } + +} + +/*! + * Setup GPIO for an I2C device to be inactive + * + * @param i2c_num an I2C device + */ +void gpio_i2c_inactive(int i2c_num) +{ + switch (i2c_num) { + case 0: + mxc_free_iomux(MX31_PIN_I2C_CLK, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_I2C_DAT, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + break; + case 1: + mxc_free_iomux(MX31_PIN_CSPI2_MOSI, OUTPUTCONFIG_FUNC, + INPUTCONFIG_ALT1); + mxc_free_iomux(MX31_PIN_CSPI2_MISO, OUTPUTCONFIG_FUNC, + INPUTCONFIG_ALT1); + break; + case 2: + mxc_request_iomux(MX31_PIN_CSPI2_SS2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_CSPI2_SCLK, OUTPUTCONFIG_FUNC, + INPUTCONFIG_ALT1); + break; + default: + break; + } +} + +/*! + * This function configures the IOMux block for PMIC standard operations. + * + */ +void gpio_pmic_active(void) +{ + mxc_request_iomux(MX31_PIN_GPIO1_3, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_set_gpio_direction(MX31_PIN_GPIO1_3, 1); +} + +EXPORT_SYMBOL(gpio_pmic_active); + +/*! + * Setup GPIO for SDHC to be active + * + * @param module SDHC module number + */ +void gpio_sdhc_active(int module) +{ + switch (module) { + case 0: + mxc_request_iomux(MX31_PIN_SD1_CLK, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SD1_CMD, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SD1_DATA0, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SD1_DATA1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SD1_DATA2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_SD1_DATA3, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + + mxc_iomux_set_pad(MX31_PIN_SD1_CLK, + (PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST + | PAD_CTL_100K_PU)); + mxc_iomux_set_pad(MX31_PIN_SD1_CMD, + (PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST + | PAD_CTL_100K_PU)); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, + (PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST + | PAD_CTL_100K_PU)); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, + (PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST + | PAD_CTL_100K_PU)); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, + (PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST + | PAD_CTL_100K_PU)); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, + (PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST + | PAD_CTL_100K_PU)); + + /* + * Active the Buffer Enable Pin only if there is + * a card in slot. + * To fix the card voltage issue caused by + * bi-directional chip TXB0108 on 3Stack + */ + if (mxc_get_gpio_datain(MX31_PIN_GPIO3_1)) + mxc_set_gpio_dataout(MX31_PIN_GPIO3_0, 0); + else + mxc_set_gpio_dataout(MX31_PIN_GPIO3_0, 1); + break; + case 1: + mxc_request_iomux(MX31_PIN_PC_CD2_B, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_PC_CD1_B, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_PC_WAIT_B, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_PC_READY, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_PC_VS1, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + mxc_request_iomux(MX31_PIN_PC_PWRON, OUTPUTCONFIG_ALT1, + INPUTCONFIG_ALT1); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_sdhc_active); + +/*! + * Setup GPIO for SDHC1 to be inactive + * + * @param module SDHC module number + */ +void gpio_sdhc_inactive(int module) +{ + switch (module) { + case 0: + mxc_free_iomux(MX31_PIN_SD1_CLK, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_SD1_CMD, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_SD1_DATA0, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_SD1_DATA1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_SD1_DATA2, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_SD1_DATA3, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + + mxc_iomux_set_pad(MX31_PIN_SD1_CLK, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX31_PIN_SD1_CMD, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + + /* Buffer Enable Pin of SD, Active HI */ + mxc_set_gpio_dataout(MX31_PIN_GPIO3_0, 0); + break; + case 1: + /* TODO:what are the pins for SDHC2? */ + mxc_free_iomux(MX31_PIN_PC_CD2_B, OUTPUTCONFIG_FUNC, + INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_PC_CD1_B, OUTPUTCONFIG_FUNC, + INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_PC_WAIT_B, OUTPUTCONFIG_FUNC, + INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_PC_READY, OUTPUTCONFIG_FUNC, + INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_PC_VS1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_PC_PWRON, OUTPUTCONFIG_FUNC, + INPUTCONFIG_NONE); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_sdhc_inactive); + +/* + * Probe for the card. If present the GPIO data would be set. + */ +unsigned int sdhc_get_card_det_status(struct device *dev) +{ + int ret; + + if (to_platform_device(dev)->id == 0) { + ret = mxc_get_gpio_datain(MX31_PIN_GPIO3_1); + /* + * Active the Buffer Enable Pin only if there is + * a card in slot. + * To fix the card voltage issue caused by + * bi-directional chip TXB0108 on 3Stack + */ + if (ret) + mxc_set_gpio_dataout(MX31_PIN_GPIO3_0, 0); + else + mxc_set_gpio_dataout(MX31_PIN_GPIO3_0, 1); + return ret; + } else + return mxc_get_gpio_datain(MX31_PIN_GPIO1_2); +} + +EXPORT_SYMBOL(sdhc_get_card_det_status); + +/* + * Return the card detect pin. + */ +int sdhc_init_card_det(int id) +{ + if (id == 0) { + /* Buffer Enable Pin, Active HI */ + mxc_request_iomux(MX31_PIN_GPIO3_0, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_set_gpio_direction(MX31_PIN_GPIO3_0, 0); + mxc_set_gpio_dataout(MX31_PIN_GPIO3_0, 0); + + /* CD Pin */ + mxc_request_iomux(MX31_PIN_GPIO3_1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_iomux_set_pad(MX31_PIN_GPIO3_1, PAD_CTL_PKE_NONE); + mxc_set_gpio_direction(MX31_PIN_GPIO3_1, 1); + return IOMUX_TO_IRQ(MX31_PIN_GPIO3_1); + } else { + iomux_config_mux(MX31_PIN_GPIO1_2, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + return IOMUX_TO_IRQ(MX31_PIN_GPIO1_2); + + } +} + +EXPORT_SYMBOL(sdhc_init_card_det); + +/*! + * Get SD1_WP ADIN7 of ATLAS pin value to detect write protection + */ +int sdhc_write_protect(struct device *dev) +{ + unsigned short rc = 0; + + pmic_adc_convert(GEN_PURPOSE_AD7, &rc); + if (rc > 0) + return 1; + else + return 0; +} + +EXPORT_SYMBOL(sdhc_write_protect); + +/*! + * Setup GPIO for LCD to be active + * + */ +void gpio_lcd_active(void) +{ + + mxc_request_iomux(MX31_PIN_LD0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD2, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD7, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD8, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD9, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD10, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD11, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD12, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD13, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD14, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD15, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_LD16, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // LD16 + mxc_request_iomux(MX31_PIN_LD17, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // LD17 + mxc_request_iomux(MX31_PIN_VSYNC3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // VSYNC + mxc_request_iomux(MX31_PIN_HSYNC, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // HSYNC + mxc_request_iomux(MX31_PIN_FPSHIFT, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // CLK + mxc_request_iomux(MX31_PIN_CONTRAST, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // CONTR + +#ifdef CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL + mxc_request_iomux(MX31_PIN_DRDY0, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); /* DRDY */ + mxc_request_iomux(MX31_PIN_D3_REV, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); /* REV */ + mxc_request_iomux(MX31_PIN_D3_SPL, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); /* SPL */ + mxc_request_iomux(MX31_PIN_D3_CLS, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); /* CLS */ +#else + /* ensure that LCDIO(1.8V) has been turn on */ + /* active reset line GPIO */ + mxc_request_iomux(MX31_PIN_LCS1, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_set_gpio_direction(MX31_PIN_LCS1, 0); + /* do reset */ + mdelay(10); /* tRES >= 100us */ + mxc_set_gpio_dataout(MX31_PIN_LCS1, 1); + + /* enable data */ + mxc_request_iomux(MX31_PIN_SER_RS, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_set_gpio_direction(MX31_PIN_SER_RS, 0); + mxc_set_gpio_dataout(MX31_PIN_SER_RS, 1); +#endif +} + +/*! + * Setup GPIO for LCD to be inactive + * + */ +void gpio_lcd_inactive(void) +{ + mxc_set_gpio_dataout(MX31_PIN_SER_RS, 0); +} + +/*! + * Switch to the specified sensor - MX31 ADS has two + * + */ +void gpio_sensor_select(int sensor) +{ +} + +/*! + * Setup GPIO for sensor to be active + * + */ +void gpio_sensor_active(void) +{ + gpio_sensor_select(0); + + /* + * Configure the iomuxen for the CSI. + */ + + mxc_request_iomux(MX31_PIN_CSI_D5, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_set_gpio_direction(MX31_PIN_CSI_D5, 0); + mxc_set_gpio_dataout(MX31_PIN_CSI_D5, 0); + + mxc_request_iomux(MX31_PIN_CSI_D6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D7, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D8, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D9, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D10, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D11, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D12, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D13, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D14, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_D15, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_HSYNC, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_MCLK, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_PIXCLK, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_CSI_VSYNC, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + + if (mxc_request_iomux(MX31_PIN_A23, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE) + == 0) { + printk(KERN_ERR "%s:REGEN set request gpio ok\n", __func__); + } else { + printk(KERN_ERR "%s:REGEN set error, request gpio error\n", + __func__); + return; + } + mxc_set_gpio_direction(MX31_PIN_SD_D_IO, 0); + mxc_set_gpio_dataout(MX31_PIN_SD_D_IO, 1); +} + +EXPORT_SYMBOL(gpio_sensor_active); + +void gpio_sensor_reset(bool flag) +{ +} + +EXPORT_SYMBOL(gpio_sensor_reset); + +/*! + * Setup GPIO for sensor to be inactive + * + */ +void gpio_sensor_inactive(void) +{ + mxc_free_iomux(MX31_PIN_CSI_D5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D7, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D8, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D9, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D10, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D11, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D12, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D13, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D14, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_D15, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_HSYNC, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_MCLK, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_PIXCLK, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_free_iomux(MX31_PIN_CSI_VSYNC, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); +} + +EXPORT_SYMBOL(gpio_sensor_inactive); + +/*! + * Setup GPIO for ATA interface + * + */ +void gpio_ata_active(void) +{ + /* + * Configure the GPR for ATA group B signals + */ + mxc_iomux_set_gpr(MUX_PGP_ATA_8 | MUX_PGP_ATA_5 | MUX_PGP_ATA_4 | + MUX_PGP_ATA_3 | MUX_PGP_ATA_2, false); + + mxc_iomux_set_gpr(MUX_PGP_ATA_9 | MUX_PGP_ATA_7 | MUX_PGP_ATA_6 | + MUX_PGP_ATA_1, true); + + /* + * Configure the IOMUX for ATA group B signals + */ + + mxc_request_iomux(MX31_PIN_CSPI1_MOSI, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D0 + mxc_request_iomux(MX31_PIN_CSPI1_MISO, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D1 + mxc_request_iomux(MX31_PIN_CSPI1_SS0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D2 + mxc_request_iomux(MX31_PIN_CSPI1_SS1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D3 + mxc_request_iomux(MX31_PIN_CSPI1_SS2, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D4 + mxc_request_iomux(MX31_PIN_CSPI1_SCLK, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D5 + mxc_request_iomux(MX31_PIN_CSPI1_SPI_RDY, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D6 + mxc_request_iomux(MX31_PIN_STXD3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D7 + mxc_request_iomux(MX31_PIN_SRXD3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D8 + mxc_request_iomux(MX31_PIN_SCK3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D9 + mxc_request_iomux(MX31_PIN_SFS3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D10 + mxc_request_iomux(MX31_PIN_STXD6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D11 + mxc_request_iomux(MX31_PIN_SRXD6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D12 + mxc_request_iomux(MX31_PIN_SCK6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D13 + mxc_request_iomux(MX31_PIN_CAPTURE, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D14 + mxc_request_iomux(MX31_PIN_COMPARE, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_D15 + + /* Config the multiplex pin of ATA interface DIR, DA0-2, INTRQ, DMARQ */ + mxc_request_iomux(MX31_PIN_KEY_COL4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_DMARQ_B + mxc_request_iomux(MX31_PIN_KEY_ROW6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_INTRQ_B + mxc_request_iomux(MX31_PIN_KEY_COL5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_DA0 + mxc_request_iomux(MX31_PIN_KEY_COL6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_DA1 + mxc_request_iomux(MX31_PIN_KEY_COL7, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_DA2 + mxc_request_iomux(MX31_PIN_KEY_ROW7, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // ATA_BUFFER_DIR + + /* HDD_ENABLE_B(H:Disable,L:Enable) */ + mxc_request_iomux(MX31_PIN_CSI_D4, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO); // HDD_ENABLE_B + mxc_set_gpio_direction(MX31_PIN_CSI_D4, 0); + mdelay(10); + mxc_set_gpio_dataout(MX31_PIN_CSI_D4, 0); + mdelay(10); + + /* These ATA pins are common to Group A and Group B */ + + mxc_request_iomux(MX31_PIN_ATA_CS0, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_ATA_CS1, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_ATA_DIOR, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_ATA_DIOW, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_ATA_DMACK, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_ATA_RESET_B, OUTPUTCONFIG_FUNC, + INPUTCONFIG_FUNC); + mxc_request_iomux(MX31_PIN_PWMO, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); + + /* Need fast slew rate for UDMA mode */ + +#define ATA_DAT_PAD_CFG (PAD_CTL_SRE_FAST | PAD_CTL_PKE_NONE | PAD_CTL_100K_PU) + mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, ATA_DAT_PAD_CFG); // data 0 + mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, ATA_DAT_PAD_CFG); // data 1 + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, ATA_DAT_PAD_CFG); // data 2 + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, ATA_DAT_PAD_CFG); // data 3 + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, ATA_DAT_PAD_CFG); // data 4 + mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, ATA_DAT_PAD_CFG); // data 5 + mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, ATA_DAT_PAD_CFG); // data 6 + mxc_iomux_set_pad(MX31_PIN_STXD3, ATA_DAT_PAD_CFG); // data 7 + mxc_iomux_set_pad(MX31_PIN_SRXD3, ATA_DAT_PAD_CFG); // data 8 + mxc_iomux_set_pad(MX31_PIN_SCK3, ATA_DAT_PAD_CFG); // data 9 + mxc_iomux_set_pad(MX31_PIN_SFS3, ATA_DAT_PAD_CFG); // data 10 + mxc_iomux_set_pad(MX31_PIN_STXD6, ATA_DAT_PAD_CFG); // data 11 + mxc_iomux_set_pad(MX31_PIN_SRXD6, ATA_DAT_PAD_CFG); // data 12 + mxc_iomux_set_pad(MX31_PIN_SCK6, ATA_DAT_PAD_CFG); // data 13 + mxc_iomux_set_pad(MX31_PIN_CAPTURE, ATA_DAT_PAD_CFG); // data 14 + mxc_iomux_set_pad(MX31_PIN_COMPARE, ATA_DAT_PAD_CFG); // data 15 +#undef ATA_DAT_PAD_CFG + +#define ATA_CTL_PAD_CFG (PAD_CTL_SRE_SLOW | PAD_CTL_PKE_NONE) + mxc_iomux_set_pad(MX31_PIN_KEY_COL4, ATA_CTL_PAD_CFG); // ATA_DMARQ); + mxc_iomux_set_pad(MX31_PIN_KEY_ROW6, ATA_CTL_PAD_CFG); // ATA_INTRQ); + mxc_iomux_set_pad(MX31_PIN_KEY_COL5, ATA_CTL_PAD_CFG); // + mxc_iomux_set_pad(MX31_PIN_KEY_COL6, ATA_CTL_PAD_CFG); // + mxc_iomux_set_pad(MX31_PIN_KEY_COL7, ATA_CTL_PAD_CFG); // + mxc_iomux_set_pad(MX31_PIN_KEY_ROW7, ATA_CTL_PAD_CFG); // + + mxc_iomux_set_pad(MX31_PIN_ATA_CS0, ATA_CTL_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_ATA_CS1, ATA_CTL_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_ATA_DIOR, ATA_CTL_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_ATA_DIOW, ATA_CTL_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_ATA_DMACK, ATA_CTL_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_ATA_RESET_B, ATA_CTL_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_PWMO, ATA_CTL_PAD_CFG); +#undef ATA_CTL_PAD_CFG +} + +EXPORT_SYMBOL(gpio_ata_active); + +/*! + * Restore ATA interface pins to reset values + * + */ +void gpio_ata_inactive(void) +{ + /* + * Turn off ATA group B signals + */ + mxc_request_iomux(MX31_PIN_CSPI1_MOSI, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D0 + mxc_request_iomux(MX31_PIN_CSPI1_MISO, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D1 + mxc_request_iomux(MX31_PIN_CSPI1_SS0, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D2 + mxc_request_iomux(MX31_PIN_CSPI1_SS1, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D3 + mxc_request_iomux(MX31_PIN_CSPI1_SS2, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D4 + mxc_request_iomux(MX31_PIN_CSPI1_SCLK, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D5 + mxc_request_iomux(MX31_PIN_CSPI1_SPI_RDY, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D6 + mxc_request_iomux(MX31_PIN_STXD3, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D7 + mxc_request_iomux(MX31_PIN_SRXD3, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D8 + mxc_request_iomux(MX31_PIN_SCK3, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D9 + mxc_request_iomux(MX31_PIN_SFS3, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D10 + mxc_request_iomux(MX31_PIN_STXD6, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D11 + mxc_request_iomux(MX31_PIN_SRXD6, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D12 + mxc_request_iomux(MX31_PIN_SCK6, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D13 + mxc_request_iomux(MX31_PIN_CAPTURE, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D14 + mxc_request_iomux(MX31_PIN_COMPARE, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_D15 + + /* Config the multiplex pin of ATA interface DIR, DA0-2, INTRQ, DMARQ */ + mxc_request_iomux(MX31_PIN_KEY_COL4, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_DMARQ_B + mxc_request_iomux(MX31_PIN_KEY_ROW6, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_INTRQ_B + mxc_request_iomux(MX31_PIN_KEY_COL5, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_DA0 + mxc_request_iomux(MX31_PIN_KEY_COL6, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_DA1 + mxc_request_iomux(MX31_PIN_KEY_COL7, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_DA2 + mxc_request_iomux(MX31_PIN_KEY_ROW7, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); // ATA_BUFFER_DIR + + /* HDD_BUFF_EN (H:A->B, L:B->A) and HDD_ENABLE_B(H:Disable,L:Enable) */ + mxc_free_iomux(MX31_PIN_CSI_D4, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO); + + /* These ATA pins are common to Group A and Group B */ + + mxc_request_iomux(MX31_PIN_ATA_CS0, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_ATA_CS1, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_ATA_DIOR, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_ATA_DIOW, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_ATA_DMACK, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_ATA_RESET_B, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_request_iomux(MX31_PIN_PWMO, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + + /* Needed fast slew rate for UDMA mode */ + +#define ATA_DAT_PAD_CFG (PAD_CTL_SRE_SLOW | PAD_CTL_DRV_NORMAL | PAD_CTL_PKE_NONE) + mxc_iomux_set_pad(MX31_PIN_KEY_COL4, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_KEY_ROW6, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_KEY_COL5, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_KEY_COL6, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_KEY_COL7, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_KEY_ROW7, ATA_DAT_PAD_CFG); + + mxc_iomux_set_pad(MX31_PIN_ATA_CS0, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_ATA_CS1, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_ATA_DIOR, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_ATA_DIOW, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_ATA_DMACK, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_ATA_RESET_B, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_PWMO, ATA_DAT_PAD_CFG); + + mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_STXD3, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SRXD3, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SCK3, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SFS3, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_STXD6, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SRXD6, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SCK6, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CAPTURE, ATA_DAT_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_COMPARE, ATA_DAT_PAD_CFG); +#undef ATA_DAT_PAD_CFG +} + +EXPORT_SYMBOL(gpio_ata_inactive); + +/* *INDENT-OFF* */ +/* + * USB Host 1 + * pins conflict with SPI1, ATA, UART3 + */ +int gpio_usbh1_active(void) +{ + return 0; +} + +EXPORT_SYMBOL(gpio_usbh1_active); + +void gpio_usbh1_inactive(void) +{ + /* Do nothing as pins don't have/support GPIO mode */ + +} + +EXPORT_SYMBOL(gpio_usbh1_inactive); + +/* + * USB Host 2 + * pins conflict with UART5, PCMCIA + */ +int gpio_usbh2_active(void) +{ + if (mxc_request_iomux(MX31_PIN_USBH2_CLK, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBH2_DIR, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBH2_NXT, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBH2_STP, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBH2_DATA0, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBH2_DATA1, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_PC_VS2, /* USBH2_DATA2 */ + OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1) || + mxc_request_iomux(MX31_PIN_PC_BVD1, /* USBH2_DATA3 */ + OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1) || + mxc_request_iomux(MX31_PIN_PC_BVD2, /* USBH2_DATA4 */ + OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1) || + mxc_request_iomux(MX31_PIN_PC_RST, /* USBH2_DATA5 */ + OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1) || + mxc_request_iomux(MX31_PIN_IOIS16, /* USBH2_DATA6 */ + OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1) || + mxc_request_iomux(MX31_PIN_PC_RW_B, /* USBH2_DATA7 */ + OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1)) { + return -EINVAL; + } + mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | + PAD_CTL_PKE_NONE)); + mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBH2_STP, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_PC_VS2, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_PC_BVD1, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_PC_BVD2, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_PC_RST, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_IOIS16, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_PC_RW_B, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + + mxc_request_iomux(MX31_PIN_USB_BYP, OUTPUTCONFIG_GPIO, + INPUTCONFIG_NONE); + mxc_set_gpio_direction(MX31_PIN_USB_BYP, 0); + mxc_set_gpio_dataout(MX31_PIN_USB_BYP, 0); + mdelay(1); + mxc_set_gpio_dataout(MX31_PIN_USB_BYP, 1); + return 0; +} + +EXPORT_SYMBOL(gpio_usbh2_active); + +void gpio_usbh2_inactive(void) +{ + mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBH2_STP, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_PC_VS2, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_PC_BVD1, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_PC_BVD2, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_PC_RST, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_IOIS16, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_PC_RW_B, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_FAST)); + + mxc_free_iomux(MX31_PIN_USBH2_CLK, + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_USBH2_DIR, + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_USBH2_NXT, + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_USBH2_STP, + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_USBH2_DATA0, + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_USBH2_DATA1, + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + + mxc_free_iomux(MX31_PIN_PC_VS2, /* USBH2_DATA2 */ + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_PC_BVD1, /* USBH2_DATA3 */ + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_PC_BVD2, /* USBH2_DATA4 */ + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_PC_RST, /* USBH2_DATA5 */ + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_IOIS16, /* USBH2_DATA6 */ + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + mxc_free_iomux(MX31_PIN_PC_RW_B, /* USBH2_DATA7 */ + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); + + mxc_free_iomux(MX31_PIN_USB_BYP, /* USBH2 PHY reset */ + OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE); +} + +EXPORT_SYMBOL(gpio_usbh2_inactive); + +/* + * USB OTG HS port + */ +int gpio_usbotg_hs_active(void) +{ + if (mxc_request_iomux(MX31_PIN_USBOTG_DATA0, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA1, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA2, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA3, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA4, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA5, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA6, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA7, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_CLK, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DIR, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_NXT, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_STP, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC)) { + return -EINVAL; + } + + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, + (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)); + + /* reset transceiver */ + mxc_request_iomux(MX31_PIN_USB_PWR, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); + mxc_set_gpio_direction(MX31_PIN_USB_PWR, 0); + mxc_set_gpio_dataout(MX31_PIN_USB_PWR, 0); + mdelay(1); + mxc_set_gpio_dataout(MX31_PIN_USB_PWR, 1); + + return 0; +} + +EXPORT_SYMBOL(gpio_usbotg_hs_active); + +void gpio_usbotg_hs_inactive(void) +{ + mxc_free_iomux(MX31_PIN_USB_PWR, OUTPUTCONFIG_GPIO, + INPUTCONFIG_GPIO); +} + +EXPORT_SYMBOL(gpio_usbotg_hs_inactive); + +/*! + * USB OTG FS port + */ +int gpio_usbotg_fs_active(void) +{ + if (mxc_request_iomux(MX31_PIN_USBOTG_DATA0, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA1, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA2, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA3, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA4, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA5, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA6, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DATA7, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_CLK, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_DIR, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_NXT, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USBOTG_STP, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC) || + mxc_request_iomux(MX31_PIN_USB_PWR, + OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC)) + return -EINVAL; + return 0; +} + +EXPORT_SYMBOL(gpio_usbotg_fs_active); + +void gpio_usbotg_fs_inactive(void) +{ + /* Do nothing as pins doesn't have/support GPIO mode */ + +} + +EXPORT_SYMBOL(gpio_usbotg_fs_inactive); + +/*! + * GPS GPIO + */ +void gpio_gps_active(void) +{ + /* POWER_EN */ + mxc_request_iomux(MX31_PIN_SCLK0, + OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO); + mxc_set_gpio_direction(MX31_PIN_SCLK0, 0); + /* Reset Pin */ + mxc_request_iomux(MX31_PIN_DCD_DTE1, + OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO); + mxc_set_gpio_direction(MX31_PIN_DCD_DTE1, 0); + + mxc_set_gpio_dataout(MX31_PIN_SCLK0, 0); + mxc_set_gpio_dataout(MX31_PIN_DCD_DTE1, 0); + + msleep(5); + mxc_set_gpio_dataout(MX31_PIN_DCD_DTE1, 1); + msleep(5); +} + +EXPORT_SYMBOL(gpio_gps_active); + +int gpio_gps_access(int para) +{ + iomux_pin_name_t pin; + pin = (para & 0x1) ? MX31_PIN_SCLK0 : MX31_PIN_DCD_DTE1; + + if (para & 0x4) /* Read GPIO */ + return mxc_get_gpio_datain(pin); + else if (para & 0x2) /* Write GPIO */ + mxc_set_gpio_dataout(pin, 1); + else + mxc_set_gpio_dataout(pin, 0); + return 0; +} + +EXPORT_SYMBOL(gpio_gps_access); + +void gpio_gps_inactive(void) +{ + mxc_free_iomux(MX31_PIN_DCD_DTE1, + OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO); + mxc_free_iomux(MX31_PIN_SCLK0, + OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO); +} + +EXPORT_SYMBOL(gpio_gps_inactive); diff -urN linux-2.6.26/arch/arm/mach-mx3/mxc_pm.c linux-2.6.26-lab126/arch/arm/mach-mx3/mxc_pm.c --- linux-2.6.26/arch/arm/mach-mx3/mxc_pm.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/mxc_pm.c 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,446 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup DPM_MX31 Power Management + * @ingroup MSL_MX31 + */ +/*! + * @file mach-mx3/mxc_pm.c + * + * @brief This file provides all the kernel level and user level API + * definitions for the CRM_MCU and DPLL in mx3. + * + * @ingroup DPM_MX31 + */ + +/* + * Include Files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "crm_regs.h" + +/* Local defines */ +#define FREQ_COMP_TOLERANCE 200 /* tolerance percentage times 100 */ +#define MCU_PLL_MAX_FREQ 600000000 /* Maximum frequency MCU PLL clock */ +#define MCU_PLL_MIN_FREQ 160000000 /* Minimum frequency MCU PLL clock */ +#define NFC_MAX_FREQ 20000000 /* Maximum frequency NFC clock */ +#define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */ + +static struct clk *mcu_pll_clk; +static struct clk *cpu_clk; +static struct clk *ahb_clk; +static struct clk *ipg_clk; + +/*! + * Spinlock to protect CRM register accesses + */ +static DEFINE_SPINLOCK(mxc_crm_lock); + +/*! + * This function is called to modify the contents of a CCM_MCU register + * + * @param reg_offset the CCM_MCU register that will read + * @param mask the mask to be used to clear the bits that are to be modified + * @param data the data that should be written to the register + */ +void mxc_ccm_modify_reg(unsigned int reg_offset, unsigned int mask, + unsigned int data) +{ + unsigned long flags; + unsigned long reg; + + spin_lock_irqsave(&mxc_crm_lock, flags); + reg = __raw_readl(reg_offset); + reg = (reg & (~mask)) | data; + __raw_writel(reg, reg_offset); + spin_unlock_irqrestore(&mxc_crm_lock, flags); +} + +/*! + * Compare two frequences using allowable tolerance + * + * The MX3 PLL can generate many frequencies. This function + * compares the generated frequency to the requested frequency + * and determines it they are within and acceptable tolerance. + * + * @param freq1 desired frequency + * @param freq2 generated frequency + * + * @return Returns 0 is frequencies are within talerance + * and non-zero is they are not. + */ +static int freq_equal(unsigned long freq1, unsigned long freq2) +{ + if (freq1 > freq2) { + return (freq1 - freq2) <= (freq1 / FREQ_COMP_TOLERANCE); + } + return (freq2 - freq1) <= (freq1 / FREQ_COMP_TOLERANCE); +} + +/*! + * Calculate new MCU clock dividers for the PDR0 regiser. + * + * @param mcu_main_clk PLL output frequency (Hz) + * @param arm_freq desired ARM frequency (Hz) + * @param max_freq desired MAX frequency (Hz) + * @param ip_freq desired IP frequency (Hz) + * @param mask were to return PDR0 mask + * @param value were to return PDR0 value + * + * @return Returns 0 on success or + * Returns non zero if error + * PLL_LESS_ARM_ERR if pll frequency is less than + * desired core frequency + * FREQ_OUT_OF_RANGE if desided frequencies ar not + * possible with the current mcu pll frequency. + */ +static int +cal_pdr0_value(unsigned long mcu_main_clk, + long arm_freq, + long max_freq, + long ip_freq, unsigned long *mask, unsigned long *value) +{ + unsigned long arm_div; /* ARM core clock divider */ + unsigned long max_div; /* MAX clock divider */ + unsigned long ipg_div; /* IPG clock divider */ + unsigned long nfc_div; /* NFC (Nand Flash Controller) clock divider */ + unsigned long hsp_div; /* HSP clock divider */ + + if (arm_freq > mcu_main_clk) { + return -PLL_LESS_ARM_ERR; + } + + arm_div = mcu_main_clk / arm_freq; + if ((arm_div == 0) || !freq_equal(arm_freq, mcu_main_clk / arm_div)) { + return FREQ_OUT_OF_RANGE; + } + max_div = mcu_main_clk / max_freq; + if ((max_div == 0) || !freq_equal(max_freq, mcu_main_clk / max_div)) { + return FREQ_OUT_OF_RANGE; + } + hsp_div = max_div; + + ipg_div = max_freq / ip_freq; + if ((ipg_div == 0) || !freq_equal(ip_freq, max_freq / ipg_div)) { + return FREQ_OUT_OF_RANGE; + } + + nfc_div = ((max_freq - 1000000) / NFC_MAX_FREQ) + 1; + + /* All of the divider values have been calculated. + * Now change the hardware register. */ + + *mask = MXC_CCM_PDR0_HSP_PODF_MASK | + MXC_CCM_PDR0_NFC_PODF_MASK | + MXC_CCM_PDR0_IPG_PODF_MASK | + MXC_CCM_PDR0_MAX_PODF_MASK | MXC_CCM_PDR0_MCU_PODF_MASK; + + *value = ((hsp_div - 1) << MXC_CCM_PDR0_HSP_PODF_OFFSET) | + ((nfc_div - 1) << MXC_CCM_PDR0_NFC_PODF_OFFSET) | + ((ipg_div - 1) << MXC_CCM_PDR0_IPG_PODF_OFFSET) | + ((max_div - 1) << MXC_CCM_PDR0_MAX_PODF_OFFSET) | + ((arm_div - 1) << MXC_CCM_PDR0_MCU_PODF_OFFSET); + + return 0; +} + +/*! + * Integer clock scaling + * + * Change main arm clock frequencies without changing the PLL. + * The integer dividers are changed to produce the desired + * frequencies. The number of valid frequency are limited and + * are determined by the current MCU PLL frequency + * + * @param arm_freq desired ARM frequency (Hz) + * @param max_freq desired MAX frequency (Hz) + * @param ip_freq desired IP frequency (Hz) + * + * @return Returns 0 on success or + * Returns non zero if error + * PLL_LESS_ARM_ERR if pll frequency is less than + * desired core frequency + * FREQ_OUT_OF_RANGE if desided frequencies ar not + * possible with the current mcu pll frequency. + */ +int mxc_pm_intscale(long arm_freq, long max_freq, long ip_freq) +{ + unsigned long mcu_main_clk; /* mcu clock domain main clock */ + unsigned long mask; + unsigned long value; + int ret_value; + + printk(KERN_INFO "arm_freq=%ld, max_freq=%ld, ip_freq=%ld\n", + arm_freq, max_freq, ip_freq); + //print_frequencies(); /* debug */ + + mcu_main_clk = clk_get_rate(mcu_pll_clk); + ret_value = cal_pdr0_value(mcu_main_clk, arm_freq, max_freq, ip_freq, + &mask, &value); + if ((arm_freq != clk_round_rate(cpu_clk, arm_freq)) || + (max_freq != clk_round_rate(ahb_clk, max_freq)) || + (ip_freq != clk_round_rate(ipg_clk, ip_freq))) { + return -EINVAL; + } + + if ((max_freq != clk_get_rate(ahb_clk)) || + (ip_freq != clk_get_rate(ipg_clk))) { + return -EINVAL; + } + + if (arm_freq != clk_get_rate(cpu_clk)) { + ret_value = clk_set_rate(cpu_clk, arm_freq); + } + return ret_value; +} + +/*! + * PLL clock scaling + * + * Change MCU PLL frequency and adjust derived clocks. Integer + * dividers are used generate the derived clocks so changed to produce + * the desired the valid frequencies are limited by the desired ARM + * frequency. + * + * The clock source for the MCU is set to the MCU PLL. + * + * @param arm_freq desired ARM frequency (Hz) + * @param max_freq desired MAX frequency (Hz) + * @param ip_freq desired IP frequency (Hz) + * + * @return Returns 0 on success or + * Returns non zero if error + * PLL_LESS_ARM_ERR if pll frequency is less than + * desired core frequency + * FREQ_OUT_OF_RANGE if desided frequencies ar not + * possible with the current mcu pll frequency. + */ +int mxc_pm_pllscale(long arm_freq, long max_freq, long ip_freq) +{ + signed long pll_freq = 0; /* target pll frequency */ + unsigned long old_pll; + unsigned long mask; + unsigned long value; + int ret_value; + + printk(KERN_INFO "arm_freq=%ld, max_freq=%ld, ip_freq=%ld\n", + arm_freq, max_freq, ip_freq); + //print_frequencies(); + + do { + pll_freq += arm_freq; + if ((pll_freq > MCU_PLL_MAX_FREQ) || (pll_freq / 8 > arm_freq)) { + return FREQ_OUT_OF_RANGE; + } + if (pll_freq < MCU_PLL_MIN_FREQ) { + ret_value = 111; + } else { + ret_value = + cal_pdr0_value(pll_freq, arm_freq, max_freq, + ip_freq, &mask, &value); + } + } while (ret_value != 0); + + old_pll = clk_get_rate(mcu_pll_clk); + if (pll_freq > old_pll) { + /* if pll freq is increasing then change dividers first */ + mxc_ccm_modify_reg(MXC_CCM_PDR0, mask, value); + ret_value = clk_set_rate(mcu_pll_clk, pll_freq); + } else { + /* if pll freq is decreasing then change pll first */ + ret_value = clk_set_rate(mcu_pll_clk, pll_freq); + mxc_ccm_modify_reg(MXC_CCM_PDR0, mask, value); + } + //print_frequencies(); + return ret_value; +} + +/*! + * Implementing steps required to transition to low-power modes + * + * @param mode The desired low-power mode. Possible values are, + * WAIT_MODE, DOZE_MODE, STOP_MODE or DSM_MODE + * + */ +void mxc_pm_lowpower(int mode) +{ + unsigned int lpm; + int enable_flag; + unsigned long reg; + + local_irq_disable(); + enable_flag = 0; + + switch (mode) { + case STOP_MODE: + /* State Retention mode */ + lpm = 2; + /* Disable timer interrupt */ + disable_irq(MXC_INT_GPT); + enable_flag = 1; + + /* Enable Well Bias and set VSTBY + * VSTBY pin will be asserted during SR mode. This asks the + * PM IC to set the core voltage to the standby voltage + * Must clear the MXC_CCM_CCMR_SBYCS bit as well */ + mxc_ccm_modify_reg(MXC_CCM_CCMR, + MXC_CCM_CCMR_WBEN | MXC_CCM_CCMR_VSTBY | + MXC_CCM_CCMR_SBYCS, + MXC_CCM_CCMR_WBEN | MXC_CCM_CCMR_VSTBY | + MXC_CCM_CCMR_SBYCS); + + mxc_ccm_modify_reg(MXC_CCM_CCMR, + MXC_CCM_CCMR_LPM_MASK, + lpm << MXC_CCM_CCMR_LPM_OFFSET); + cpu_do_idle(); + break; + + case DSM_MODE: + /* Deep Sleep Mode */ + lpm = 3; + /* Disable timer interrupt */ + disable_irq(MXC_INT_GPT); + enable_flag = 1; + /* Enabled Well Bias + * SBYCS = 0, MCU clock source is disabled*/ + mxc_ccm_modify_reg(MXC_CCM_CCMR, + MXC_CCM_CCMR_WBEN | MXC_CCM_CCMR_VSTBY | + MXC_CCM_CCMR_SBYCS | MXC_CCM_CCMR_LPM_MASK, + MXC_CCM_CCMR_WBEN | MXC_CCM_CCMR_VSTBY | + MXC_CCM_CCMR_SBYCS | + (lpm << MXC_CCM_CCMR_LPM_OFFSET)); + + /* wake up by keypad and usbotg */ + reg = __raw_readl(MXC_CCM_WIMR); + reg &= ~(1 << 18); +#if defined(CONFIG_USB_GADGET_WAKE_UP) || \ + defined(CONFIG_USB_EHCI_ARC_OTG_WAKE_UP) + reg &= ~(1 << 5); +#endif +#ifdef CONFIG_USB_EHCI_ARC_H2_WAKE_UP + reg &= ~(1 << 6); +#endif + __raw_writel(reg, MXC_CCM_WIMR); + + flush_cache_all(); + l2x0_disable(); + + mxc_pm_arch_entry(IO_ADDRESS(NFC_BASE_ADDR), 2048); + printk(KERN_INFO "Resume from DSM\n"); + + l2x0_enable(); + mxc_init_irq(); + + break; + default: + case WAIT_MODE: + /* Wait is the default mode used when idle. */ + reg = __raw_readl(MXC_CCM_CCMR); + reg &= ~MXC_CCM_CCMR_LPM_MASK; + __raw_writel(reg, MXC_CCM_CCMR); + break; + } + + if (enable_flag) { + /* Enable timer interrupt */ + enable_irq(MXC_INT_GPT); + } + local_irq_enable(); +} + +#ifdef CONFIG_MXC_DVFS +/*! + * Changes MCU frequencies using dvfs. + * + * @param armfreq desired ARM frequency in Hz + * @param ahbfreq desired AHB frequency in Hz + * @param ipfreq desired IP frequency in Hz + * + * @return Returns 0 on success, non-zero on error + */ +int mxc_pm_dvfs(unsigned long armfreq, long ahbfreq, long ipfreq) +{ + int ret_value; + int i; + + if (ahbfreq != 133000000) { + return FREQ_OUT_OF_RANGE; + } + if (ipfreq != 66500000) { + return FREQ_OUT_OF_RANGE; + } + ret_value = FREQ_OUT_OF_RANGE; + for (i = 0; i < dvfs_states_tbl->num_of_states; i++) { + if (dvfs_states_tbl->freqs[i] == armfreq) { + ret_value = dvfs_set_state(i); + break; + } + } + + return ret_value; +} +#endif /* CONFIG_MXC_DVFS */ + +/*! + * This function is used to load the module. + * + * @return Returns an Integer on success + */ +static int __init mxc_pm_init_module(void) +{ + printk(KERN_INFO "Low-Level PM Driver module loaded\n"); + + mcu_pll_clk = clk_get(NULL, "mcu_pll"); + cpu_clk = clk_get(NULL, "cpu_clk"); + ahb_clk = clk_get(NULL, "ahb_clk"); + ipg_clk = clk_get(NULL, "ipg_clk"); + return 0; +} + +/*! + * This function is used to unload the module + */ +static void __exit mxc_pm_cleanup_module(void) +{ + clk_put(mcu_pll_clk); + clk_put(cpu_clk); + clk_put(ahb_clk); + clk_put(ipg_clk); + printk(KERN_INFO "Low-Level PM Driver module Unloaded\n"); +} + +module_init(mxc_pm_init_module); +module_exit(mxc_pm_cleanup_module); + +EXPORT_SYMBOL(mxc_pm_intscale); +EXPORT_SYMBOL(mxc_pm_pllscale); +EXPORT_SYMBOL(mxc_pm_lowpower); +#ifdef CONFIG_MXC_DVFS +EXPORT_SYMBOL(mxc_pm_dvfs); +#endif + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MX3 Low-level Power Management Driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/mach-mx3/pm.c linux-2.6.26-lab126/arch/arm/mach-mx3/pm.c --- linux-2.6.26/arch/arm/mach-mx3/pm.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/pm.c 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,113 @@ +/* + * linux/arch/arm/mach-mx3/pm.c + * + * MX3 Power Management Routines + * + * Original code for the SA11x0: + * Copyright (c) 2001 Cliff Brake + * + * Modified for the PXA250 by Nicolas Pitre: + * Copyright (c) 2002 Monta Vista Software, Inc. + * + * Modified for the OMAP1510 by David Singleton: + * Copyright (c) 2002 Monta Vista Software, Inc. + * + * Cleanup 2004 for OMAP1510/1610 by Dirk Behme + * + * Modified for the MX31 + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include + +/* + * TODO: whatta save? + */ + +static int mx31_suspend_enter(suspend_state_t state) +{ + printk(KERN_INFO "Hi, from mx31_pm_enter\n"); + switch (state) { + case PM_SUSPEND_MEM: + mxc_pm_lowpower(DSM_MODE); + break; + case PM_SUSPEND_STANDBY: + mxc_pm_lowpower(STOP_MODE); + break; + default: + return -1; + } + return 0; +} + +/* + * Called after processes are frozen, but before we shut down devices. + */ +static int mx31_suspend_prepare(void) +{ + struct regulator *reg_core; + reg_core = regulator_get(NULL, "SW1A_STBY"); + if (reg_core == NULL || IS_ERR(reg_core)) { + printk(KERN_ERR "Get regulator SW1A_STBY fail\n"); + return -1; + } + regulator_set_voltage(reg_core, 1250000); + regulator_set_mode(reg_core, REGULATOR_MODE_STANDBY); + regulator_put(reg_core, NULL); + + return 0; +} + +/* + * Called after devices are re-setup, but before processes are thawed. + */ +static void mx31_suspend_finish(void) +{ + return; +} + +static int mx31_pm_valid(suspend_state_t state) +{ + return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); +} + +struct platform_suspend_ops mx31_suspend_ops = { + .valid = mx31_pm_valid, + .prepare = mx31_suspend_prepare, + .enter = mx31_suspend_enter, + .finish = mx31_suspend_finish, +}; + +static int __init mx31_pm_init(void) +{ + printk(KERN_INFO "Power Management for Freescale MX31\n"); + suspend_set_ops(&mx31_suspend_ops); + + return 0; +} + +late_initcall(mx31_pm_init); diff -urN linux-2.6.26/arch/arm/mach-mx3/sdma_script_code.h linux-2.6.26-lab126/arch/arm/mach-mx3/sdma_script_code.h --- linux-2.6.26/arch/arm/mach-mx3/sdma_script_code.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/sdma_script_code.h 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,581 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __SDMA_SCRIPT_CODE_H__ +#define __SDMA_SCRIPT_CODE_H__ + +/*! +* Following define start address of start script +*/ +#define start_ADDR 0 +/*! +* Following define size of start script +*/ +#define start_SIZE 21 + +/*! +* Following define start address of core script +*/ +#define core_ADDR 80 +/*! +* Following define size of core script +*/ +#define core_SIZE 152 + +/*! +* Following define start address of common script +*/ +#define common_ADDR 232 +/*! +* Following define size of common script +*/ +#define common_SIZE 191 + +/*! +* Following define start address of burst_copy script +*/ +#define burst_copy_ADDR 423 +/*! +* Following define size of burst_copy script +*/ +#define burst_copy_SIZE 87 + +/*! +* Following define start address of dsp_2_burst script +*/ +#define dsp_2_burst_ADDR 510 +/*! +* Following define size of dsp_2_burst script +*/ +#define dsp_2_burst_SIZE 24 + +/*! +* Following define start address of burst_2_dsp script +*/ +#define burst_2_dsp_ADDR 534 +/*! +* Following define size of burst_2_dsp script +*/ +#define burst_2_dsp_SIZE 24 + +/*! +* Following define start address of dsp_copy script +*/ +#define dsp_copy_ADDR 558 +/*! +* Following define size of dsp_copy script +*/ +#define dsp_copy_SIZE 86 + +/*! +* Following define start address of mcu_2_mcu script +*/ +#define mcu_2_mcu_ADDR 644 +/*! +* Following define size of mcu_2_mcu script +*/ +#define mcu_2_mcu_SIZE 79 + +/*! +* Following define start address of mcu_2_per script +*/ +#define mcu_2_per_ADDR 723 +/*! +* Following define size of mcu_2_per script +*/ +#define mcu_2_per_SIZE 88 + +/*! +* Following define start address of test script +*/ +#define test_ADDR 811 +/*! +* Following define size of test script +*/ +#define test_SIZE 63 + +/*! +* Following define start address of mcu_2_dsp script +*/ +#define mcu_2_dsp_ADDR 874 +/*! +* Following define size of mcu_2_dsp script +*/ +#define mcu_2_dsp_SIZE 30 + +/*! +* Following define start address of mcu_2_dsp_2buf script +*/ +#define mcu_2_dsp_2buf_ADDR 904 +/*! +* Following define size of mcu_2_dsp_2buf script +*/ +#define mcu_2_dsp_2buf_SIZE 113 + +/*! +* Following define start address of dsp_2_mcu script +*/ +#define dsp_2_mcu_ADDR 1017 +/*! +* Following define size of dsp_2_mcu script +*/ +#define dsp_2_mcu_SIZE 30 + +/*! +* Following define start address of dsp_2_mcu_2buf script +*/ +#define dsp_2_mcu_2buf_ADDR 1047 +/*! +* Following define size of dsp_2_mcu_2buf script +*/ +#define dsp_2_mcu_2buf_SIZE 113 + +/*! +* Following define start address of dsp_2_dsp script +*/ +#define dsp_2_dsp_ADDR 1160 +/*! +* Following define size of dsp_2_dsp script +*/ +#define dsp_2_dsp_SIZE 64 + +/*! +* Following define start address of per_2_mcu script +*/ +#define per_2_mcu_ADDR 1224 +/*! +* Following define size of per_2_mcu script +*/ +#define per_2_mcu_SIZE 121 + +/*! +* Following define start address of dsp_2_per_2buf script +*/ +#define dsp_2_per_2buf_ADDR 1345 +/*! +* Following define size of dsp_2_per_2buf script +*/ +#define dsp_2_per_2buf_SIZE 164 + +/*! +* Following define start address of per_2_dsp_2buf script +*/ +#define per_2_dsp_2buf_ADDR 1509 +/*! +* Following define size of per_2_dsp_2buf script +*/ +#define per_2_dsp_2buf_SIZE 168 + +/*! +* Following define start address of per_2_per script +*/ +#define per_2_per_ADDR 1677 +/*! +* Following define size of per_2_per script +*/ +#define per_2_per_SIZE 67 + +/*! +* Following define start address of error_dsp script +*/ +#define error_dsp_ADDR 1744 +/*! +* Following define size of error_dsp script +*/ +#define error_dsp_SIZE 34 + +/*! +* Following define start address of ap_2_ap script +*/ +#define ap_2_ap_ADDR 6144 +/*! +* Following define size of ap_2_ap script +*/ +#define ap_2_ap_SIZE 294 + +/*! +* Following define start address of app_2_mcu script +*/ +#define app_2_mcu_ADDR 6438 +/*! +* Following define size of app_2_mcu script +*/ +#define app_2_mcu_SIZE 101 + +/*! +* Following define start address of ata_2_mcu script +*/ +#define ata_2_mcu_ADDR 6539 +/*! +* Following define size of ata_2_mcu script +*/ +#define ata_2_mcu_SIZE 110 + +/*! +* Following define start address of dptc_dvfs script +*/ +#define dptc_dvfs_ADDR 6649 +/*! +* Following define size of dptc_dvfs script +*/ +#define dptc_dvfs_SIZE 274 + +/*! +* Following define start address of error script +*/ +#define error_ADDR 6923 +/*! +* Following define size of error script +*/ +#define error_SIZE 73 + +/*! +* Following define start address of firi_2_mcu script +*/ +#define firi_2_mcu_ADDR 6996 +/*! +* Following define size of firi_2_mcu script +*/ +#define firi_2_mcu_SIZE 114 + +/*! +* Following define start address of mcu_2_app script +*/ +#define mcu_2_app_ADDR 7110 +/*! +* Following define size of mcu_2_app script +*/ +#define mcu_2_app_SIZE 127 + +/*! +* Following define start address of mcu_2_ata script +*/ +#define mcu_2_ata_ADDR 7237 +/*! +* Following define size of mcu_2_ata script +*/ +#define mcu_2_ata_SIZE 87 + +/*! +* Following define start address of mcu_2_firi script +*/ +#define mcu_2_firi_ADDR 7324 +/*! +* Following define size of mcu_2_firi script +*/ +#define mcu_2_firi_SIZE 77 + +/*! +* Following define start address of mcu_2_mshc script +*/ +#define mcu_2_mshc_ADDR 7401 +/*! +* Following define size of mcu_2_mshc script +*/ +#define mcu_2_mshc_SIZE 48 + +/*! +* Following define start address of mcu_2_shp script +*/ +#define mcu_2_shp_ADDR 7449 +/*! +* Following define size of mcu_2_shp script +*/ +#define mcu_2_shp_SIZE 123 + +/*! +* Following define start address of mshc_2_mcu script +*/ +#define mshc_2_mcu_ADDR 7572 +/*! +* Following define size of mshc_2_mcu script +*/ +#define mshc_2_mcu_SIZE 60 + +/*! +* Following define start address of shp_2_mcu script +*/ +#define shp_2_mcu_ADDR 7632 +/*! +* Following define size of shp_2_mcu script +*/ +#define shp_2_mcu_SIZE 101 + +/*! +* Following define start address of uart_2_mcu script +*/ +#define uart_2_mcu_ADDR 7733 +/*! +* Following define size of uart_2_mcu script +*/ +#define uart_2_mcu_SIZE 105 + +/*! +* Following define start address of uartsh_2_mcu script +*/ +#define uartsh_2_mcu_ADDR 7838 +/*! +* Following define size of uartsh_2_mcu script +*/ +#define uartsh_2_mcu_SIZE 98 + +/*! +* Following define the start address of sdma ram +*/ + +#define RAM_CODE_START_ADDR 6144 +/*! +* Following define the size of sdma ram +*/ +#define RAM_CODE_SIZE 1792 + +/*! +* This function returns buffer that holds the image of SDMA RAM. +* This is required to start on a 4-byte aligned boundary on some platforms +* for SDMA to work properly. +* +* @return pointer to buffer that holds the image of SDMA RAM +*/ + +__attribute__ ((__aligned__(4))) +#ifndef CONFIG_XIP_KERNEL +const +#endif +static short sdma_code[] = { + 0xc0ec, 0x7d59, 0x0970, 0x0111, 0x5111, 0x5ad1, 0x5bd9, 0xc0fe, + 0x5ce1, 0x7d02, 0x0200, 0x9806, 0x08ff, 0x0011, 0x28ff, 0x00bc, + 0x05df, 0x7d4b, 0x06df, 0x7d2f, 0x6dc5, 0x6ed5, 0x5ef1, 0x0288, + 0xd81a, 0x9854, 0x0b04, 0x00d3, 0x7d20, 0x06a5, 0x3e03, 0x3d03, + 0x03a5, 0x3b03, 0x008b, 0x058b, 0x7802, 0x63d8, 0x0000, 0x7e72, + 0x63ff, 0x7e70, 0x02a5, 0x008a, 0x4e00, 0x7d01, 0x983d, 0x6dcf, + 0x6edf, 0x0015, 0x0015, 0x7802, 0x63d8, 0x0000, 0x7e63, 0x63ff, + 0x7e61, 0x3a03, 0x008a, 0x6dcd, 0x6edd, 0x7801, 0x63d8, 0x7e5a, + 0x63ff, 0x7e58, 0x0006, 0x6dc5, 0x6e07, 0x5ef1, 0x0288, 0xd8f7, + 0x7e02, 0x7f04, 0x9854, 0x0007, 0x68cc, 0x6b28, 0x54e1, 0x0089, + 0xdb13, 0x0188, 0x5ce1, 0x9854, 0x52d1, 0x53d9, 0x54e1, 0xc10d, + 0x7dad, 0x0200, 0x9800, 0x0200, 0x9800, 0x06df, 0x7d06, 0x6d23, + 0x6ed5, 0x5ef1, 0x0288, 0xd8cd, 0x9854, 0x5ef1, 0x6e07, 0x6d03, + 0x0b04, 0x00d3, 0x7d59, 0x06a5, 0x3e03, 0x3d03, 0x4d00, 0x7d09, + 0x03a5, 0x00a3, 0x0588, 0x008b, 0xd8c9, 0x7ed8, 0x620c, 0x7ed6, + 0x008d, 0x4e00, 0x7c25, 0x0a20, 0x00da, 0x7c22, 0x6503, 0x3d1f, + 0x02a5, 0x00a2, 0x0215, 0x0215, 0x6a18, 0x6a28, 0x7fc7, 0x0a20, + 0x0b08, 0x00da, 0x7c06, 0x6b18, 0x6b28, 0x7fc0, 0x0000, 0x2020, + 0x9889, 0x0688, 0x0015, 0x0015, 0x6818, 0x6828, 0x7fb7, 0x98c2, + 0x0007, 0x6a0c, 0x54e1, 0x0089, 0xdb0f, 0x0188, 0x5ce1, 0x9854, + 0x0b04, 0x00d3, 0x7d21, 0x0389, 0x1b12, 0x048b, 0x0688, 0x0015, + 0x0015, 0x0588, 0x038c, 0x0a08, 0x05da, 0x008d, 0x7c01, 0x008a, + 0x05a0, 0x7803, 0x620b, 0x5a03, 0x1b01, 0x7e98, 0x008b, 0x00a4, + 0x038c, 0x7803, 0x5203, 0x6a0b, 0x1b01, 0x6a28, 0x7f8f, 0x0000, + 0x4d00, 0x7ce8, 0x008e, 0x3803, 0xd8c9, 0x7e88, 0x620c, 0x7e86, + 0x9854, 0x7802, 0x6209, 0x6a29, 0x0006, 0x3e03, 0x4e00, 0x7d11, + 0x0b04, 0x03a6, 0x02db, 0x7d01, 0x038a, 0x02a3, 0x048a, 0x008b, + 0x7802, 0x6329, 0x6bc8, 0x7ebc, 0x63c8, 0x7ebc, 0x008c, 0x4800, + 0x7d15, 0x0488, 0x0015, 0x0015, 0x6edf, 0x7803, 0x632b, 0x6bc8, + 0x0000, 0x7eae, 0x63c8, 0x7eae, 0x008c, 0x3803, 0x6edd, 0x7803, + 0x6329, 0x6bc8, 0x0000, 0x7ea4, 0x63c8, 0x7ea4, 0x0006, 0x3d03, + 0x4d00, 0x7d0e, 0x0b04, 0x03a5, 0x02db, 0x7d01, 0x038a, 0x02a3, + 0x048a, 0x008b, 0x7802, 0x63c8, 0x6b09, 0x7e1e, 0x7f1e, 0x008c, + 0x0488, 0x0015, 0x0015, 0x6dcf, 0x0288, 0x008a, 0x0d08, 0x02dd, + 0x7c01, 0x008d, 0x7802, 0x63c8, 0x6b0b, 0x7e0e, 0x6b28, 0x7f0d, + 0x0000, 0x02dd, 0x7c02, 0x2208, 0x990d, 0x008c, 0x3803, 0x65c0, + 0x6dc5, 0x7802, 0x63c8, 0x6b09, 0x6b28, 0x0006, 0x0870, 0x0011, + 0x5010, 0xc0ec, 0x7d5e, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, + 0x7d02, 0x0200, 0x992c, 0x6ec3, 0x6d07, 0x5df0, 0x0dff, 0x0511, + 0x1dff, 0x05bc, 0x4d00, 0x7d44, 0x0b70, 0x0311, 0x522b, 0x5313, + 0x02b9, 0x4a00, 0x7c04, 0x6a28, 0x7f3a, 0x0400, 0x993c, 0x008f, + 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x0a03, 0x0212, 0x02bc, 0x0210, + 0x4a00, 0x7d1c, 0x4a02, 0x7d20, 0x4a01, 0x7d23, 0x0b70, 0x0311, + 0x53eb, 0x62c8, 0x7e24, 0x0360, 0x7d02, 0x0210, 0x0212, 0x6a09, + 0x7f1e, 0x0212, 0x6a09, 0x7f1b, 0x0212, 0x6a09, 0x7f18, 0x2003, + 0x4800, 0x7cef, 0x0b70, 0x0311, 0x5313, 0x997d, 0x0015, 0x0015, + 0x7802, 0x62c8, 0x6a0b, 0x997c, 0x0015, 0x7802, 0x62c8, 0x6a0a, + 0x997c, 0x7802, 0x62c8, 0x6a09, 0x7c02, 0x0000, 0x993a, 0xdb13, + 0x6a28, 0x7ffd, 0x008b, 0x52c3, 0x53cb, 0xc10d, 0x7da5, 0x0200, + 0x992c, 0x0200, 0x9929, 0xc19d, 0xc0ec, 0x7d69, 0x0c70, 0x0411, + 0x5414, 0x5ac4, 0x028c, 0x58da, 0x5efa, 0xc0fe, 0x56fa, 0x7d02, + 0x0200, 0x9994, 0x6d07, 0x5bca, 0x5cd2, 0x0bff, 0x0311, 0x1bff, + 0x04bb, 0x0415, 0x53da, 0x4c00, 0x7d47, 0x0a70, 0x0211, 0x552a, + 0x5212, 0x008d, 0x00bb, 0x4800, 0x7c07, 0x05b9, 0x4d00, 0x7c13, + 0x6928, 0x7f2d, 0x0400, 0x99a5, 0x008f, 0x0015, 0x04d8, 0x7d01, + 0x008c, 0x04a0, 0x0015, 0x7802, 0x55c6, 0x6d0b, 0x7e29, 0x6d28, + 0x7f1e, 0x0000, 0x99a3, 0x1e20, 0x5506, 0x2620, 0x008d, 0x0560, + 0x7c08, 0x065f, 0x55c6, 0x063f, 0x7e1b, 0x6d0a, 0x7f10, 0x4c00, + 0x7d1b, 0x04d8, 0x7d02, 0x008c, 0x0020, 0x04a0, 0x0015, 0x7802, + 0x55c6, 0x6d0b, 0x7e0d, 0x6d28, 0x7f02, 0x0000, 0x99ec, 0x0007, + 0x680c, 0x6d0c, 0x6507, 0x6d07, 0x6d2b, 0x6d28, 0x0007, 0x680c, + 0x0007, 0x54d2, 0x0454, 0x99ef, 0x6928, 0x7ff1, 0x54d2, 0x008a, + 0x52c0, 0x53c8, 0xc10d, 0x0288, 0x7d9f, 0x0200, 0x9994, 0x0200, + 0x998c, 0xc0ec, 0x7d72, 0x0800, 0x0970, 0x0111, 0x5111, 0x5ac1, + 0x5bc9, 0x028e, 0xc0fe, 0x068a, 0x7c6a, 0x5dd9, 0x5ce1, 0x0bff, + 0x0311, 0x1bff, 0x03bc, 0x5bd1, 0x1a5c, 0x6ac3, 0x63c8, 0x0363, + 0x7c05, 0x036f, 0x7d27, 0x0374, 0x7c7a, 0x9a71, 0xdb04, 0x3c06, + 0x4c00, 0x7df7, 0x028f, 0x1a04, 0x6a23, 0x620b, 0x6f23, 0x301f, + 0x00aa, 0x0462, 0x7c04, 0x4a00, 0x7d0b, 0x2001, 0x9a30, 0x048a, + 0x620b, 0x2201, 0x1c01, 0x1801, 0x02dc, 0x7d02, 0x301f, 0x00aa, + 0x048f, 0x1c04, 0x6c07, 0x0488, 0x3c1f, 0x6c2b, 0x0045, 0x028e, + 0x1a5c, 0x9a11, 0x058f, 0x1d0c, 0x6d23, 0x650b, 0x007d, 0x7c01, + 0x1d08, 0x007c, 0x7c01, 0x1d04, 0x6d23, 0x650b, 0x0488, 0x3c1f, + 0x0417, 0x0417, 0x0417, 0x0417, 0x059c, 0x6d23, 0x028e, 0x1a34, + 0x6ad7, 0x0488, 0x0804, 0x7802, 0x650b, 0x6dc8, 0x008c, 0x1a28, + 0x6ad7, 0x63c8, 0x034c, 0x6bc8, 0x54d1, 0x4c00, 0x7d06, 0x0065, + 0x7c02, 0x0101, 0x0025, 0x0400, 0x9a0d, 0x52c1, 0x53c9, 0x54e1, + 0x0453, 0xc10d, 0x7d95, 0x0200, 0x9a00, 0x0200, 0x99f9, 0x0200, + 0x9a00, 0x55d9, 0x6d07, 0x54d1, 0x058a, 0x2508, 0x6dc7, 0x0373, + 0x7c03, 0x65c8, 0x6d0b, 0x2408, 0x0372, 0x7c04, 0x65c8, 0x6d0b, + 0x2408, 0x9a86, 0x6cce, 0x65c8, 0x6d0a, 0x2404, 0x6d28, 0x6507, + 0x5dd9, 0x5cd1, 0x6ad7, 0x6ae3, 0x63c8, 0x0334, 0x6bc8, 0x0370, + 0x7ca9, 0x0c60, 0x0411, 0x04bb, 0x4c00, 0x7da4, 0x0410, 0x1c30, + 0x0410, 0x04bb, 0x046d, 0x7d0a, 0x047d, 0x7c03, 0x047c, 0x7c01, + 0x9a3a, 0x003b, 0x003a, 0x0039, 0x0058, 0x9ab5, 0x047d, 0x7d03, + 0x047c, 0x7d01, 0x9a3a, 0x005b, 0xdaf9, 0x1d18, 0x6d23, 0x650b, + 0x0510, 0x003a, 0x0039, 0x0038, 0x00ad, 0xdb04, 0x0c30, 0x0410, + 0x04bb, 0x003c, 0x003d, 0x00ac, 0xdaf9, 0x007b, 0x7c04, 0x003d, + 0x003c, 0x1d0c, 0x9ad6, 0x048f, 0x1c14, 0x6c23, 0x640b, 0x4401, + 0x7d04, 0x005d, 0x005c, 0x1d0c, 0x9ad6, 0x0310, 0x3b30, 0x4b30, + 0x7d01, 0x1b10, 0x0310, 0x003d, 0x003c, 0x00ab, 0x6ad7, 0x63c8, + 0x6d23, 0x650b, 0x0560, 0x7d03, 0x005e, 0xdaed, 0x9a3a, 0x003e, + 0x0c80, 0x0410, 0x0394, 0xdaed, 0x640b, 0x037f, 0x7d02, 0x1a14, + 0x9aea, 0x1a0c, 0x6ad7, 0x6cc8, 0x9a3a, 0x0c7f, 0x0410, 0x03b4, + 0x04b8, 0x03ac, 0x640b, 0x6bc8, 0x028e, 0x1a04, 0x6ad7, 0x6cc8, + 0x0006, 0x058f, 0x1d08, 0x6d23, 0x650b, 0x007d, 0x7c01, 0x1d38, + 0x007c, 0x7c01, 0x1d1c, 0x0006, 0x048b, 0x042c, 0x0454, 0x042b, + 0x6ad7, 0x6cc8, 0x0006, 0x0007, 0x684c, 0x6144, 0x9b1c, 0x0007, + 0x68cc, 0x61d0, 0x9b1c, 0x0007, 0x680c, 0x680c, 0x6107, 0x6907, + 0x692b, 0x6928, 0x0007, 0x680c, 0x0d70, 0x0511, 0x5515, 0x55f5, + 0x01a5, 0x0dff, 0x0512, 0x1dff, 0x0512, 0x04bd, 0x0499, 0x0454, + 0x0006, 0x08ff, 0x0011, 0x28ff, 0x0006, 0x038c, 0x0eff, 0x0611, + 0x2eff, 0x03b6, 0x0006, 0x53d6, 0x0398, 0x5bd6, 0x53ee, 0x0398, + 0x5bee, 0x0006, 0x52de, 0x53e6, 0x54ee, 0x0498, 0x0454, 0x0006, + 0x50f6, 0x52c6, 0x53ce, 0x54d6, 0x0498, 0x0454, 0x0006, 0x6207, + 0x0b70, 0x0311, 0x5013, 0x55f0, 0x02a5, 0x0bff, 0x0312, 0x1bff, + 0x0312, 0x04bb, 0x049a, 0x0006, 0x1e10, 0x0870, 0x0011, 0x5010, + 0xc0ec, 0x7d39, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, + 0x0200, 0x9b5b, 0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, + 0x4d00, 0x7d17, 0x6ec3, 0x62c8, 0x7e28, 0x0264, 0x7d08, 0x0b70, + 0x0311, 0x522b, 0x02b9, 0x4a00, 0x7c18, 0x0400, 0x9b6a, 0x0212, + 0x3aff, 0x008a, 0x05d8, 0x7d01, 0x008d, 0x0a10, 0x6ed3, 0x6ac8, + 0xdba5, 0x6a28, 0x7f17, 0x0b70, 0x0311, 0x5013, 0xdbbd, 0x52c0, + 0x53c8, 0xc10d, 0x7dd0, 0x0200, 0x9b5b, 0x008f, 0x00d5, 0x7d01, + 0x008d, 0xdba5, 0x9b68, 0x0200, 0x9b58, 0x0007, 0x68cc, 0x6a28, + 0x7f01, 0x9ba3, 0x0007, 0x6a0c, 0x6a0c, 0x6207, 0x6a07, 0x6a2b, + 0x6a28, 0x0007, 0x680c, 0x0454, 0x9b81, 0x05a0, 0x1e08, 0x6ec3, + 0x0388, 0x3b03, 0x0015, 0x0015, 0x7802, 0x62c8, 0x6a0b, 0x7ee5, + 0x6a28, 0x7fe8, 0x0000, 0x6ec1, 0x008b, 0x7802, 0x62c8, 0x6a09, + 0x7edc, 0x6a28, 0x7fdf, 0x2608, 0x0006, 0x55f0, 0x6207, 0x02a5, + 0x0dff, 0x0511, 0x1dff, 0x04b5, 0x049a, 0x0006, 0x0870, 0x0011, + 0x5010, 0xc0ec, 0x7d78, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, + 0x7d02, 0x0200, 0x9bcc, 0x6d03, 0x6ed3, 0x0dff, 0x0511, 0x1dff, + 0x05bc, 0x5df8, 0x4d00, 0x7d5e, 0x0b70, 0x0311, 0x522b, 0x5313, + 0x02b9, 0x4a00, 0x7c04, 0x62ff, 0x7e3f, 0x0400, 0x9bdc, 0x008f, + 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5ddb, 0x0d03, 0x0512, 0x05bc, + 0x0510, 0x5dd3, 0x4d00, 0x7d27, 0x4d02, 0x7d20, 0x4d01, 0x7d1a, + 0x0b70, 0x0311, 0x53eb, 0x0360, 0x7d05, 0x6509, 0x7e25, 0x620a, + 0x7e23, 0x9c06, 0x620a, 0x7e20, 0x6509, 0x7e1e, 0x0512, 0x0512, + 0x02ad, 0x6ac8, 0x7f19, 0x2003, 0x4800, 0x7ced, 0x0b70, 0x0311, + 0x5313, 0x9c21, 0x7802, 0x6209, 0x6ac8, 0x9c20, 0x0015, 0x7802, + 0x620a, 0x6ac8, 0x9c20, 0x0015, 0x0015, 0x7802, 0x620b, 0x6ac8, + 0x7c03, 0x0000, 0x55db, 0x9bda, 0x0007, 0x68cc, 0x680c, 0x55d3, + 0x4d00, 0x7d03, 0x4d02, 0x7d02, 0x9c2f, 0x0017, 0x0017, 0x55db, + 0x009d, 0x55fb, 0x05a0, 0x08ff, 0x0011, 0x18ff, 0x0010, 0x04b8, + 0x04ad, 0x0454, 0x62ff, 0x7ee8, 0x008b, 0x52c0, 0x53c8, 0xc10d, + 0x7d8b, 0x0200, 0x9bcc, 0x0200, 0x9bc9, 0xc19d, 0xc0ec, 0x7d52, + 0x0c70, 0x0411, 0x5414, 0x5ac4, 0x028c, 0x58da, 0x5efa, 0xc0fe, + 0x56fa, 0x7d02, 0x0200, 0x9c4e, 0x6d03, 0x5bca, 0x5cd2, 0x0bff, + 0x0311, 0x1bff, 0x04bb, 0x0415, 0x53da, 0x0a70, 0x0211, 0x4c00, + 0x7d28, 0x552a, 0x05bb, 0x4d00, 0x7c02, 0x0400, 0x9c61, 0x4c01, + 0x7d0f, 0x008f, 0x0015, 0x04d8, 0x7d01, 0x008c, 0x0020, 0x04a0, + 0x0015, 0x7802, 0x650b, 0x5d06, 0x0000, 0x7e0c, 0x7f0d, 0x9c5f, + 0x650a, 0x7e08, 0x008d, 0x0011, 0x0010, 0x05a8, 0x065f, 0x5d06, + 0x063f, 0x7f02, 0x0007, 0x680c, 0x0007, 0x5012, 0x54d0, 0x0454, + 0x9c8b, 0x5012, 0x54d0, 0x0473, 0x7c06, 0x552a, 0x05b9, 0x4d00, + 0x7c02, 0x0400, 0x9c8d, 0x52c0, 0x53c8, 0xc10d, 0x0288, 0x7db6, + 0x0200, 0x9c4e, 0x0200, 0x9c46, 0x0870, 0x0011, 0x5010, 0xc0ec, + 0x7d46, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, + 0x9ca2, 0x0b70, 0x0311, 0x6ed3, 0x6d03, 0x0dff, 0x0511, 0x1dff, + 0x05bc, 0x4d00, 0x7d2b, 0x522b, 0x02b9, 0x4a00, 0x7c04, 0x62c8, + 0x7e1f, 0x0400, 0x9cb3, 0x008f, 0x00d5, 0x7d01, 0x008d, 0x05a0, + 0x0060, 0x7c05, 0x6edd, 0x6209, 0x7e16, 0x6ac8, 0x7f11, 0x0015, + 0x0060, 0x7c05, 0x6ede, 0x620a, 0x7e0e, 0x6ac8, 0x7f09, 0x6edf, + 0x0015, 0x7802, 0x620b, 0x6ac8, 0x0000, 0x7e05, 0x7f01, 0x9cb1, + 0x0007, 0x68cc, 0x9cdd, 0x0007, 0x6a0c, 0x0454, 0x62c8, 0x7ef8, + 0x5013, 0x52c0, 0x53c8, 0xc10d, 0x7dbd, 0x0200, 0x9ca2, 0x0200, + 0x9c9f, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d29, 0x5010, 0x5ac0, + 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9cf0, 0x0870, 0x0011, + 0x6d03, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d12, 0x5228, + 0x02b9, 0x4a00, 0x7c02, 0x0400, 0x9cff, 0x620b, 0x7e06, 0x5a06, + 0x7f06, 0x0000, 0x2504, 0x7d05, 0x9cff, 0x0007, 0x680c, 0x0007, + 0x0454, 0x5010, 0x52c0, 0xc10d, 0x7ddb, 0x0200, 0x9cf0, 0x0200, + 0x9cec, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d74, 0x5010, 0x5ac0, + 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9d20, 0x6d03, + 0x0d03, 0x0512, 0x05bc, 0x0510, 0x5dd0, 0x0dff, 0x0511, 0x1dff, + 0x05bc, 0x5df8, 0x4d00, 0x7d57, 0x0a70, 0x0211, 0x532a, 0x5212, + 0x03b9, 0x4b00, 0x7c02, 0x0400, 0x9d34, 0x008f, 0x05d8, 0x7d01, + 0x008d, 0x05a0, 0x5dda, 0x55d2, 0x4d00, 0x7d27, 0x4d02, 0x7d20, + 0x4d01, 0x7d1a, 0x0a70, 0x0211, 0x52ea, 0x0260, 0x7d05, 0x6509, + 0x7e25, 0x630a, 0x7e23, 0x9d58, 0x630a, 0x7e20, 0x6509, 0x7e1e, + 0x0512, 0x0512, 0x03ad, 0x5b06, 0x7f19, 0x2003, 0x4800, 0x7ced, + 0x0a70, 0x0211, 0x5212, 0x9d73, 0x7802, 0x6309, 0x5b06, 0x9d72, + 0x0015, 0x7802, 0x630a, 0x5b06, 0x9d72, 0x0015, 0x0015, 0x7802, + 0x630b, 0x5b06, 0x7c03, 0x55da, 0x0000, 0x9d32, 0x0007, 0x680c, + 0x55d2, 0x4d00, 0x7d03, 0x4d02, 0x7d02, 0x9d80, 0x0017, 0x0017, + 0x55da, 0x009d, 0x55fa, 0x05a0, 0x08ff, 0x0011, 0x18ff, 0x0010, + 0x04b8, 0x04ad, 0x0454, 0x008a, 0x52c0, 0x53c8, 0xc10d, 0x7d90, + 0x0200, 0x9d20, 0x0200, 0x9d1c, 0xc19d, 0x0870, 0x0011, 0xc0ec, + 0x7d35, 0x5010, 0x5ac0, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, + 0x9d9b, 0x0870, 0x0011, 0x6d07, 0x0dff, 0x0511, 0x1dff, 0x05bc, + 0x4d00, 0x7d1c, 0x5228, 0x02b9, 0x4a00, 0x7c04, 0x6928, 0x7f0b, + 0x0400, 0x9daa, 0x5206, 0x7e10, 0x6a0b, 0x6928, 0x7f04, 0x0000, + 0x2504, 0x7d0c, 0x9daa, 0x0007, 0x680c, 0x680c, 0x6207, 0x6a07, + 0x6a2b, 0x6a28, 0x0007, 0x680c, 0x0007, 0x0454, 0x6928, 0x7ff3, + 0x5010, 0x52c0, 0xc10d, 0x7dcf, 0x0200, 0x9d9b, 0x0200, 0x9d97, + 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d5e, 0x5010, 0x5ac0, 0x5bc8, + 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9dd7, 0x6d07, 0x5df0, + 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d44, 0x0a70, 0x0211, + 0x532a, 0x5212, 0x03b9, 0x4b00, 0x7c04, 0x6a28, 0x7f3a, 0x0400, + 0x9de6, 0x008f, 0x05d8, 0x7d01, 0x008d, 0x05a0, 0x0b03, 0x0312, + 0x03bc, 0x0310, 0x4b00, 0x7d1c, 0x4b02, 0x7d20, 0x4b01, 0x7d23, + 0x0a70, 0x0211, 0x52ea, 0x5306, 0x7e24, 0x0260, 0x7d02, 0x0310, + 0x0312, 0x6b09, 0x7f1e, 0x0312, 0x6b09, 0x7f1b, 0x0312, 0x6b09, + 0x7f18, 0x2003, 0x4800, 0x7cef, 0x0a70, 0x0211, 0x5212, 0x9e27, + 0x0015, 0x0015, 0x7802, 0x5306, 0x6b0b, 0x9e26, 0x0015, 0x7802, + 0x5306, 0x6b0a, 0x9e26, 0x7802, 0x5306, 0x6b09, 0x7c02, 0x0000, + 0x9de4, 0xdb13, 0x6928, 0x7ffd, 0x008a, 0x52c0, 0x53c8, 0xc10d, + 0x7da6, 0x0200, 0x9dd7, 0x0200, 0x9dd3, 0x0870, 0x0011, 0x5010, + 0xc0ec, 0x7d5b, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, + 0x0200, 0x9e3b, 0x0b70, 0x0311, 0x6ec3, 0x6d07, 0x5df0, 0x0dff, + 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d3d, 0x522b, 0x02b9, 0x4a00, + 0x7c04, 0x6a28, 0x7f33, 0x0400, 0x9e4d, 0x028e, 0x1a94, 0x6ac3, + 0x62c8, 0x0269, 0x7d1b, 0x1e94, 0x6ec3, 0x6ed3, 0x62c8, 0x0248, + 0x6ac8, 0x2694, 0x6ec3, 0x62c8, 0x026e, 0x7d31, 0x6a09, 0x7f1e, + 0x2501, 0x4d00, 0x7d1f, 0x028e, 0x1a98, 0x6ac3, 0x62c8, 0x6ec3, + 0x0260, 0x7df1, 0x6a28, 0x7f12, 0xdb47, 0x9e8c, 0x6ee3, 0x008f, + 0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x62c8, 0x026e, 0x7d17, + 0x6a09, 0x7f04, 0x2001, 0x7cf9, 0x0000, 0x9e4b, 0x0289, 0xdb13, + 0x018a, 0x9e9b, 0x6a28, 0x7ffa, 0x0b70, 0x0311, 0x5013, 0x52c0, + 0x53c8, 0xc10d, 0x7da8, 0x0200, 0x9e3b, 0x0200, 0x9e38, 0x6a28, + 0x7fed, 0xdb47, 0x9e9b, 0x0458, 0x0454, 0x9e8c, 0xc19d, 0x0870, + 0x0011, 0xc0ec, 0x7d54, 0x5010, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, + 0x56f8, 0x7d02, 0x0200, 0x9ea5, 0x0b70, 0x0311, 0x6d07, 0x5df0, + 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d36, 0x522b, 0x02b9, + 0x4a00, 0x7c04, 0x6928, 0x7f2c, 0x0400, 0x9eb6, 0x028e, 0x1a94, + 0x5202, 0x0269, 0x7d16, 0x1e94, 0x5206, 0x0248, 0x5a06, 0x2694, + 0x5206, 0x026e, 0x7d2e, 0x6a09, 0x7f1b, 0x2501, 0x4d00, 0x7d1c, + 0x028e, 0x1a98, 0x5202, 0x0260, 0x7df3, 0x6a28, 0x7f11, 0xdb47, + 0x9eee, 0x008f, 0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5206, + 0x026e, 0x7d17, 0x6a09, 0x7f04, 0x2001, 0x7cf9, 0x0000, 0x9eb4, + 0x0289, 0xdb13, 0x018a, 0x9efd, 0x6928, 0x7ffa, 0x0b70, 0x0311, + 0x5013, 0x52c0, 0x53c8, 0xc10d, 0x7db0, 0x0200, 0x9ea5, 0x0200, + 0x9ea1, 0x6a28, 0x7fed, 0xdb47, 0x9efd, 0x0458, 0x0454, 0x9eee, + 0x9eee +}; +#endif diff -urN linux-2.6.26/arch/arm/mach-mx3/sdma_script_code_pass2.h linux-2.6.26-lab126/arch/arm/mach-mx3/sdma_script_code_pass2.h --- linux-2.6.26/arch/arm/mach-mx3/sdma_script_code_pass2.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/sdma_script_code_pass2.h 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,434 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + +/*! + * @file sdma_script_code.h + * @brief This file contains functions of SDMA scripts code initialization + * + * The file was generated automatically. Based on sdma scripts library. + * + * @ingroup SDMA + */ +/******************************************************************************* + + SDMA RELEASE LABEL: "SS15_MX31" + +*******************************************************************************/ + +#ifndef __SDMA_SCRIPT_CODE_PASS2_H__ +#define __SDMA_SCRIPT_CODE_PASS2_H__ + +/*! +* SDMA ROM scripts start addresses and sizes +*/ + +#define start_ADDR_2 0 +#define start_SIZE_2 20 + +#define core_ADDR_2 80 +#define core_SIZE_2 152 + +#define common_ADDR_2 232 +#define common_SIZE_2 191 + +#define ap_2_ap_ADDR_2 423 +#define ap_2_ap_SIZE_2 294 + +#define bp_2_bp_ADDR_2 717 +#define bp_2_bp_SIZE_2 112 + +#define ap_2_bp_ADDR_2 829 +#define ap_2_bp_SIZE_2 200 + +#define bp_2_ap_ADDR_2 1029 +#define bp_2_ap_SIZE_2 223 + +#define app_2_mcu_ADDR_2 1252 +#define app_2_mcu_SIZE_2 101 + +#define mcu_2_app_ADDR_2 1353 +#define mcu_2_app_SIZE_2 127 + +#define uart_2_mcu_ADDR_2 1480 +#define uart_2_mcu_SIZE_2 105 + +#define uartsh_2_mcu_ADDR_2 1585 +#define uartsh_2_mcu_SIZE_2 98 + +#define mcu_2_shp_ADDR_2 1683 +#define mcu_2_shp_SIZE_2 123 + +#define shp_2_mcu_ADDR_2 1806 +#define shp_2_mcu_SIZE_2 101 + +#define error_ADDR_2 1907 +#define error_SIZE_2 73 + +#define test_ADDR_2 1980 +#define test_SIZE_2 63 + +#define signature_ADDR_2 1023 +#define signature_SIZE_2 1 + +/*! +* SDMA RAM scripts start addresses and sizes +*/ + +#define ap_2_ap_fixed_addr_ADDR_2 6144 +#define ap_2_ap_fixed_addr_SIZE_2 68 + +#define app_2_mcu_patched_ADDR_2 6212 +#define app_2_mcu_patched_SIZE_2 104 + +#undef app_2_mcu_ADDR_2 +#undef app_2_mcu_SIZE_2 + +/*mapping the app_2_mcu start address to the patched(RAM)script start address*/ +#define app_2_mcu_ADDR_2 app_2_mcu_patched_ADDR_2 +#define app_2_mcu_SIZE_2 app_2_mcu_patched_SIZE_2 + +#define app_2_per_ADDR_2 6316 +#define app_2_per_SIZE_2 105 + +#define ata_2_mcu_ADDR_2 6421 +#define ata_2_mcu_SIZE_2 110 + +#define firi_2_mcu_ADDR_2 6531 +#define firi_2_mcu_SIZE_2 114 + +#define loop_DMAs_fixed_addr_ADDR_2 6645 +#define loop_DMAs_fixed_addr_SIZE_2 90 + +#define mcu_2_app_patched_ADDR_2 6735 +#define mcu_2_app_patched_SIZE_2 129 + +#undef mcu_2_app_ADDR_2 +#undef mcu_2_app_SIZE_2 + +/*mapping the mcu_2_app start address to the patched(RAM)script start address*/ +#define mcu_2_app_ADDR_2 mcu_2_app_patched_ADDR_2 +#define mcu_2_app_SIZE_2 mcu_2_app_patched_SIZE_2 + +#define mcu_2_ata_ADDR_2 6864 +#define mcu_2_ata_SIZE_2 87 + +#define mcu_2_firi_ADDR_2 6951 +#define mcu_2_firi_SIZE_2 77 + +#define mcu_2_mshc_ADDR_2 7028 +#define mcu_2_mshc_SIZE_2 48 + +#define mcu_2_shp_patched_ADDR_2 7076 +#define mcu_2_shp_patched_SIZE_2 125 + +#undef mcu_2_shp_ADDR_2 +#undef mcu_2_shp_SIZE_2 + +/*mapping the mcu_2_shp start address to the patched(RAM)script start address*/ +#define mcu_2_shp_ADDR_2 mcu_2_shp_patched_ADDR_2 +#define mcu_2_shp_SIZE_2 mcu_2_shp_patched_SIZE_2 + +#define mshc_2_mcu_ADDR_2 7201 +#define mshc_2_mcu_SIZE_2 60 + +#define per_2_app_ADDR_2 7261 +#define per_2_app_SIZE_2 131 + +#define per_2_shp_ADDR_2 7392 +#define per_2_shp_SIZE_2 131 + +#define shp_2_mcu_patched_ADDR_2 7523 +#define shp_2_mcu_patched_SIZE_2 104 + +#undef shp_2_mcu_ADDR_2 +#undef shp_2_mcu_SIZE_2 + +/*mapping the shp_2_mcu start address to the patched(RAM)script start address*/ +#define shp_2_mcu_ADDR_2 shp_2_mcu_patched_ADDR_2 +#define shp_2_mcu_SIZE_2 shp_2_mcu_patched_SIZE_2 + +#define shp_2_per_ADDR_2 7627 +#define shp_2_per_SIZE_2 109 + +#define uart_2_mcu_patched_ADDR_2 7736 +#define uart_2_mcu_patched_SIZE_2 106 + +#undef uart_2_mcu_ADDR_2 +#undef uart_2_mcu_SIZE_2 + +/*mapping the uart_2_mcu start address to the patched(RAM)script start address*/ +#define uart_2_mcu_ADDR_2 uart_2_mcu_patched_ADDR_2 +#define uart_2_mcu_SIZE_2 uart_2_mcu_patched_SIZE_2 + +#define uartsh_2_mcu_patched_ADDR_2 7842 +#define uartsh_2_mcu_patched_SIZE_2 99 + +#undef uartsh_2_mcu_ADDR_2 +#undef uartsh_2_mcu_SIZE_2 + +/* + * mapping the uartsh_2_mcu start address to the patched(RAM)script + * start address + */ +#define uartsh_2_mcu_ADDR_2 uartsh_2_mcu_patched_ADDR_2 +#define uartsh_2_mcu_SIZE_2 uartsh_2_mcu_patched_SIZE_2 + +/*! +* SDMA RAM image start address and size +*/ + +#define RAM_CODE_START_ADDR_2 6144 +#define RAM_CODE_SIZE_2 1797 + +/*! +* Buffer that holds the SDMA RAM image +*/ + +__attribute__ ((__aligned__(4))) +#ifndef CONFIG_XIP_KERNEL +const +#endif +static const short sdma_code_2[] = { + 0x0970, 0x0111, 0x5111, 0x5ef9, 0xc0ec, 0x7d23, 0x5ad1, 0x5bd9, + 0xc0fe, 0x7c1f, 0x5ce1, 0x5de9, 0x5ef1, 0x08ff, 0x0011, 0x28ff, + 0x00bc, 0x048e, 0x56f9, 0x0660, 0x7d05, 0x0661, 0x7c2b, 0x6c07, + 0x6d13, 0x9821, 0x0661, 0x7d26, 0x6c17, 0x6d03, 0x028d, 0x058c, + 0x048a, 0xd9f5, 0x7e08, 0x7f07, 0x54e1, 0x52d1, 0x53d9, 0xc10d, + 0x7dde, 0x0200, 0x9804, 0x0660, 0x7d03, 0x6007, 0x52f1, 0x9832, + 0x6003, 0x52e9, 0x00a2, 0x0007, 0x6a0c, 0x6a0c, 0x6207, 0x6a07, + 0x6a2b, 0x6a28, 0x0007, 0x6a0c, 0x54e1, 0xc795, 0x048b, 0x0498, + 0x0454, 0x9825, 0x0800, 0x983c, 0x0870, 0x0011, 0x5010, 0xc0ec, + 0x7d61, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, + 0x984a, 0x6ec3, 0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, + 0x4d00, 0x7d45, 0x0b70, 0x0311, 0x522b, 0x5313, 0x02b9, 0x4a00, + 0x7c04, 0x6a28, 0x7f3b, 0x0400, 0x985a, 0x008f, 0x00d5, 0x7d01, + 0x008d, 0x05a0, 0x0a03, 0x0212, 0x02bc, 0x0210, 0x4a00, 0x7d1c, + 0x4a02, 0x7d20, 0x4a01, 0x7d23, 0x0b70, 0x0311, 0x53eb, 0x62c8, + 0x7e25, 0x0360, 0x7d02, 0x0210, 0x0212, 0x6a09, 0x7f1f, 0x0212, + 0x6a09, 0x7f1c, 0x0212, 0x6a09, 0x7f19, 0x2003, 0x4800, 0x7cef, + 0x0b70, 0x0311, 0x5313, 0x989b, 0x0015, 0x0015, 0x7802, 0x62c8, + 0x6a0b, 0x989a, 0x0015, 0x7802, 0x62c8, 0x6a0a, 0x989a, 0x7802, + 0x62c8, 0x6a09, 0x7c03, 0x6a28, 0x0000, 0x9858, 0xc77b, 0x6a28, + 0x7ffd, 0x0870, 0x0011, 0x5010, 0x52c0, 0x53c8, 0xc10d, 0x7da2, + 0x0200, 0x984a, 0x0200, 0x9847, 0x0870, 0x0011, 0x5010, 0xc0ec, + 0x7d62, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, + 0x98b2, 0x6ec3, 0x6dd7, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, + 0x4d00, 0x7d46, 0x0b70, 0x0311, 0x522b, 0x5313, 0x02b9, 0x4a00, + 0x7c04, 0x62ff, 0x7e3c, 0x0400, 0x98c2, 0x008f, 0x00d5, 0x7d01, + 0x008d, 0x05a0, 0x0a03, 0x0212, 0x02bc, 0x0210, 0x4a00, 0x7d28, + 0x4a02, 0x7d20, 0x4a01, 0x7d19, 0x6ddd, 0x0b70, 0x0311, 0x53eb, + 0x62c8, 0x7e25, 0x0360, 0x7d02, 0x0210, 0x0212, 0x6ac8, 0x7f1f, + 0x0212, 0x6ac8, 0x7f1c, 0x0212, 0x6ac8, 0x7f19, 0x2003, 0x4800, + 0x7cef, 0x0b70, 0x0311, 0x5313, 0x9905, 0x6ddd, 0x7802, 0x62c8, + 0x6ac8, 0x9904, 0x6dde, 0x0015, 0x7802, 0x62c8, 0x6ac8, 0x9904, + 0x0015, 0x0015, 0x7801, 0x62d8, 0x7c02, 0x0000, 0x98c0, 0xc777, + 0x62ff, 0x7efd, 0x0870, 0x0011, 0x5010, 0x52c0, 0x53c8, 0xc10d, + 0x7da1, 0x0200, 0x98b2, 0x0200, 0x98af, 0xc19d, 0xc0ec, 0x7d69, + 0x0c70, 0x0411, 0x5414, 0x5ac4, 0x028c, 0x58da, 0x5efa, 0xc0fe, + 0x56fa, 0x7d02, 0x0200, 0x991e, 0x6d07, 0x5bca, 0x5cd2, 0x0bff, + 0x0311, 0x1bff, 0x04bb, 0x0415, 0x53da, 0x4c00, 0x7d47, 0x0a70, + 0x0211, 0x552a, 0x5212, 0x008d, 0x00bb, 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0x532a, 0x5212, 0x03b9, + 0x4b00, 0x7c02, 0x0400, 0x9cfb, 0x008f, 0x05d8, 0x7d01, 0x008d, + 0x05a0, 0x5dda, 0x55d2, 0x4d00, 0x7d2c, 0x4d02, 0x7d24, 0x4d01, + 0x7d1e, 0x59e2, 0x0a70, 0x0211, 0x52ea, 0x61c8, 0x7e2c, 0x63c8, + 0x7e2a, 0x65c8, 0x7e28, 0x0260, 0x7d03, 0x0112, 0x0112, 0x9d22, + 0x0512, 0x0512, 0x0311, 0x03a9, 0x03ad, 0x5b06, 0x7f1c, 0x2003, + 0x4800, 0x7ceb, 0x0a70, 0x0211, 0x5212, 0x51e2, 0x9d40, 0x7802, + 0x63c8, 0x5b06, 0x9d3f, 0x6dce, 0x0015, 0x7802, 0x63c8, 0x5b06, + 0x9d3f, 0x6dcf, 0x0015, 0x0015, 0x7802, 0x63c8, 0x5b06, 0x7c03, + 0x55da, 0x0000, 0x9cf9, 0x0007, 0x68ff, 0x55d2, 0x4d00, 0x7d03, + 0x4d02, 0x7d02, 0x9d4d, 0x0017, 0x0017, 0x55da, 0x009d, 0x55fa, + 0x05a0, 0x08ff, 0x0011, 0x18ff, 0x0010, 0x04b8, 0x04ad, 0x0454, + 0x0870, 0x0011, 0x5010, 0x52c0, 0x53c8, 0xc10d, 0x7d88, 0x0200, + 0x9ce7, 0x0200, 0x9ce3, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d61, + 0x5010, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, + 0x9d6a, 0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, + 0x7d45, 0x0a70, 0x0211, 0x532a, 0x5212, 0x03b9, 0x4b00, 0x7c04, + 0x6a28, 0x7f3b, 0x0400, 0x9d79, 0x008f, 0x05d8, 0x7d01, 0x008d, + 0x05a0, 0x0b03, 0x0312, 0x03bc, 0x0310, 0x4b00, 0x7d1c, 0x4b02, + 0x7d20, 0x4b01, 0x7d23, 0x0a70, 0x0211, 0x52ea, 0x5306, 0x7e25, + 0x0260, 0x7d02, 0x0310, 0x0312, 0x6b09, 0x7f1f, 0x0312, 0x6b09, + 0x7f1c, 0x0312, 0x6b09, 0x7f19, 0x2003, 0x4800, 0x7cef, 0x0a70, + 0x0211, 0x5212, 0x9dba, 0x0015, 0x0015, 0x7802, 0x5306, 0x6b0b, + 0x9db9, 0x0015, 0x7802, 0x5306, 0x6b0a, 0x9db9, 0x7802, 0x5306, + 0x6b09, 0x7c03, 0x6b28, 0x0000, 0x9d77, 0xc77b, 0x6928, 0x7ffd, + 0x0870, 0x0011, 0x5010, 0x52c0, 0x53c8, 0xc10d, 0x7da3, 0x0200, + 0x9d6a, 0x0200, 0x9d66, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d60, + 0x5010, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, + 0x9dd2, 0x6dd7, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, + 0x7d46, 0x0a70, 0x0211, 0x532a, 0x5212, 0x03b9, 0x4b00, 0x7c02, + 0x0400, 0x9de1, 0x008f, 0x05d8, 0x7d01, 0x008d, 0x05a0, 0x0b03, + 0x0312, 0x03bc, 0x0310, 0x4b00, 0x7d28, 0x4b02, 0x7d20, 0x4b01, + 0x7d19, 0x6ddd, 0x0a70, 0x0211, 0x52ea, 0x5306, 0x7e27, 0x0260, + 0x7d02, 0x0310, 0x0312, 0x6bc8, 0x7f21, 0x0312, 0x6bc8, 0x7f1e, + 0x0312, 0x6bc8, 0x7f1b, 0x2003, 0x4800, 0x7cef, 0x0a70, 0x0211, + 0x5212, 0x9e23, 0x6ddd, 0x7802, 0x5306, 0x6bc8, 0x9e22, 0x6dde, + 0x0015, 0x7802, 0x5306, 0x6bc8, 0x9e22, 0x0015, 0x0015, 0x7802, + 0x5306, 0x6bc8, 0x7c03, 0x0000, 0xde32, 0x9ddf, 0xc777, 0x0870, + 0x0011, 0x5010, 0x52c0, 0x53c8, 0xc10d, 0x7da4, 0x0200, 0x9dd2, + 0x0200, 0x9dce, 0x63ff, 0x0368, 0x7d02, 0x0369, 0x7def, 0x0006, + 0x0870, 0x0011, 0x5010, 0xc0ec, 0x7d5c, 0x5ac0, 0x5bc8, 0x5ef8, + 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9e3e, 0x0b70, 0x0311, 0x6ec3, + 0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d3e, + 0x522b, 0x02b9, 0x4a00, 0x7c04, 0x6a28, 0x7f34, 0x0400, 0x9e50, + 0x028e, 0x1a94, 0x6ac3, 0x62c8, 0x0269, 0x7d1b, 0x1e94, 0x6ec3, + 0x6ed3, 0x62c8, 0x0248, 0x6ac8, 0x2694, 0x6ec3, 0x62c8, 0x026e, + 0x7d32, 0x6a09, 0x7f1f, 0x2501, 0x4d00, 0x7d20, 0x028e, 0x1a98, + 0x6ac3, 0x62c8, 0x6ec3, 0x0260, 0x7df1, 0x6a28, 0x7f13, 0xc7af, + 0x9e90, 0x6ee3, 0x008f, 0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0, + 0x62c8, 0x026e, 0x7d18, 0x6a09, 0x7f05, 0x2001, 0x7cf9, 0x6a28, + 0x0000, 0x9e4e, 0x0289, 0xc77b, 0x018a, 0x9e9f, 0x6a28, 0x7ffa, + 0x0b70, 0x0311, 0x5013, 0x52c0, 0x53c8, 0xc10d, 0x7da7, 0x0200, + 0x9e3e, 0x0200, 0x9e3b, 0x6a28, 0x7fed, 0xc7af, 0x9e9f, 0x0458, + 0x0454, 0x9e90, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d55, 0x5010, + 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9ea9, + 0x0b70, 0x0311, 0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, + 0x4d00, 0x7d37, 0x522b, 0x02b9, 0x4a00, 0x7c04, 0x6928, 0x7f2d, + 0x0400, 0x9eba, 0x028e, 0x1a94, 0x5202, 0x0269, 0x7d16, 0x1e94, + 0x5206, 0x0248, 0x5a06, 0x2694, 0x5206, 0x026e, 0x7d2f, 0x6a09, + 0x7f1c, 0x2501, 0x4d00, 0x7d1d, 0x028e, 0x1a98, 0x5202, 0x0260, + 0x7df3, 0x6a28, 0x7f12, 0xc7af, 0x9ef3, 0x008f, 0x2001, 0x00d5, + 0x7d01, 0x008d, 0x05a0, 0x5206, 0x026e, 0x7d18, 0x6a09, 0x7f05, + 0x2001, 0x7cf9, 0x6a28, 0x0000, 0x9eb8, 0x0289, 0xc77b, 0x018a, + 0x9f02, 0x6928, 0x7ffa, 0x0b70, 0x0311, 0x5013, 0x52c0, 0x53c8, + 0xc10d, 0x7daf, 0x0200, 0x9ea9, 0x0200, 0x9ea5, 0x6a28, 0x7fed, + 0xc7af, 0x9f02, 0x0458, 0x0454, 0x9ef3 +}; +#endif diff -urN linux-2.6.26/arch/arm/mach-mx3/serial.c linux-2.6.26-lab126/arch/arm/mach-mx3/serial.c --- linux-2.6.26/arch/arm/mach-mx3/serial.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/serial.c 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,267 @@ +/* + * Copyright 2006-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @file mach-mx3/serial.c + * + * @brief This file contains the UART initiliazation. + * + * @ingroup MSL_MX31 + */ +#include +#include +#include +#include +#include +#include +#include "serial.h" +#include "board-mx31ads.h" +#include "board-mx3_3stack.h" + +#if defined(CONFIG_SERIAL_MXC) || defined(CONFIG_SERIAL_MXC_MODULE) + +/*! + * This is an array where each element holds information about a UART port, + * like base address of the UART, interrupt numbers etc. This structure is + * passed to the serial_core.c file. Based on which UART is used, the core file + * passes back the appropriate port structure as an argument to the control + * functions. + */ +static uart_mxc_port mxc_ports[MXC_UART_NR] = { + [0] = { + .port = { + .membase = (void *)IO_ADDRESS(UART1_BASE_ADDR), + .mapbase = UART1_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART1_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 0, + }, + .ints_muxed = UART1_MUX_INTS, + .irqs = {UART1_INT2, UART1_INT3}, + .mode = UART1_MODE, + .ir_mode = UART1_IR, + .enabled = UART1_ENABLED, + .hardware_flow = UART1_HW_FLOW, + .cts_threshold = UART1_UCR4_CTSTL, + .dma_enabled = UART1_DMA_ENABLE, + .dma_rxbuf_size = UART1_DMA_RXBUFSIZE, + .rx_threshold = UART1_UFCR_RXTL, + .tx_threshold = UART1_UFCR_TXTL, + .shared = UART1_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART1_TX, + .dma_rx_id = MXC_DMA_UART1_RX, + .rxd_mux = MXC_UART_RXDMUX, + .ir_tx_inv = MXC_IRDA_TX_INV, + .ir_rx_inv = MXC_IRDA_RX_INV, + }, + [1] = { + .port = { + .membase = (void *)IO_ADDRESS(UART2_BASE_ADDR), + .mapbase = UART2_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART2_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 1, + }, + .ints_muxed = UART2_MUX_INTS, + .irqs = {UART2_INT2, UART2_INT3}, + .mode = UART2_MODE, + .ir_mode = UART2_IR, + .enabled = UART2_ENABLED, + .hardware_flow = UART2_HW_FLOW, + .cts_threshold = UART2_UCR4_CTSTL, + .dma_enabled = UART2_DMA_ENABLE, + .dma_rxbuf_size = UART2_DMA_RXBUFSIZE, + .rx_threshold = UART2_UFCR_RXTL, + .tx_threshold = UART2_UFCR_TXTL, + .shared = UART2_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART2_TX, + .dma_rx_id = MXC_DMA_UART2_RX, + .rxd_mux = MXC_UART_IR_RXDMUX, + .ir_tx_inv = MXC_IRDA_TX_INV, + .ir_rx_inv = MXC_IRDA_RX_INV, + }, +#if UART3_ENABLED == 1 + [2] = { + .port = { + .membase = (void *)IO_ADDRESS(UART3_BASE_ADDR), + .mapbase = UART3_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART3_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 2, + }, + .ints_muxed = UART3_MUX_INTS, + .irqs = {UART3_INT2, UART3_INT3}, + .mode = UART3_MODE, + .ir_mode = UART3_IR, + .enabled = UART3_ENABLED, + .hardware_flow = UART3_HW_FLOW, + .cts_threshold = UART3_UCR4_CTSTL, + .dma_enabled = UART3_DMA_ENABLE, + .dma_rxbuf_size = UART3_DMA_RXBUFSIZE, + .rx_threshold = UART3_UFCR_RXTL, + .tx_threshold = UART3_UFCR_TXTL, + .shared = UART3_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART3_TX, + .dma_rx_id = MXC_DMA_UART3_RX, + .rxd_mux = MXC_UART_RXDMUX, + .ir_tx_inv = MXC_IRDA_TX_INV, + .ir_rx_inv = MXC_IRDA_RX_INV, + }, +#endif +#if UART4_ENABLED == 1 + [3] = { + .port = { + .membase = (void *)IO_ADDRESS(UART4_BASE_ADDR), + .mapbase = UART4_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART4_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 3, + }, + .ints_muxed = UART4_MUX_INTS, + .irqs = {UART4_INT2, UART4_INT3}, + .mode = UART4_MODE, + .ir_mode = UART4_IR, + .enabled = UART4_ENABLED, + .hardware_flow = UART4_HW_FLOW, + .cts_threshold = UART4_UCR4_CTSTL, + .dma_enabled = UART4_DMA_ENABLE, + .dma_rxbuf_size = UART4_DMA_RXBUFSIZE, + .rx_threshold = UART4_UFCR_RXTL, + .tx_threshold = UART4_UFCR_TXTL, + .shared = UART4_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART4_TX, + .dma_rx_id = MXC_DMA_UART4_RX, + .rxd_mux = MXC_UART_RXDMUX, + .ir_tx_inv = MXC_IRDA_TX_INV, + .ir_rx_inv = MXC_IRDA_RX_INV, + }, +#endif +#if UART5_ENABLED == 1 + [4] = { + .port = { + .membase = (void *)IO_ADDRESS(UART5_BASE_ADDR), + .mapbase = UART5_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART5_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 4, + }, + .ints_muxed = UART5_MUX_INTS, + .irqs = {UART5_INT2, UART5_INT3}, + .mode = UART5_MODE, + .ir_mode = UART5_IR, + .enabled = UART5_ENABLED, + .hardware_flow = UART5_HW_FLOW, + .cts_threshold = UART5_UCR4_CTSTL, + .dma_enabled = UART5_DMA_ENABLE, + .dma_rxbuf_size = UART5_DMA_RXBUFSIZE, + .rx_threshold = UART5_UFCR_RXTL, + .tx_threshold = UART5_UFCR_TXTL, + .shared = UART5_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART5_TX, + .dma_rx_id = MXC_DMA_UART5_RX, + .rxd_mux = MXC_UART_RXDMUX, + .ir_tx_inv = MXC_IRDA_TX_INV, + .ir_rx_inv = MXC_IRDA_RX_INV, + }, +#endif +}; + +static struct platform_device mxc_uart_device1 = { + .name = "mxcintuart", + .id = 0, + .dev = { + .platform_data = &mxc_ports[0], + }, +}; + +static struct platform_device mxc_uart_device2 = { + .name = "mxcintuart", + .id = 1, + .dev = { + .platform_data = &mxc_ports[1], + }, +}; + +#if UART3_ENABLED == 1 +static struct platform_device mxc_uart_device3 = { + .name = "mxcintuart", + .id = 2, + .dev = { + .platform_data = &mxc_ports[2], + }, +}; +#endif + +#if UART4_ENABLED == 1 +static struct platform_device mxc_uart_device4 = { + .name = "mxcintuart", + .id = 3, + .dev = { + .platform_data = &mxc_ports[3], + }, +}; +#endif + +#if UART5_ENABLED == 1 +static struct platform_device mxc_uart_device5 = { + .name = "mxcintuart", + .id = 4, + .dev = { + .platform_data = &mxc_ports[4], + }, +}; +#endif + +static int __init mxc_init_uart(void) +{ + /* Register all the MXC UART platform device structures */ + platform_device_register(&mxc_uart_device1); + platform_device_register(&mxc_uart_device2); + + /* Grab ownership of shared UARTs 3 and 4, only when enabled */ +#if UART3_ENABLED == 1 +#if UART3_DMA_ENABLE == 1 + spba_take_ownership(UART3_SHARED_PERI, (SPBA_MASTER_A | SPBA_MASTER_C)); +#else + spba_take_ownership(UART3_SHARED_PERI, SPBA_MASTER_A); +#endif /* UART3_DMA_ENABLE */ + platform_device_register(&mxc_uart_device3); +#endif /* UART3_ENABLED */ + +#if UART4_ENABLED == 1 + platform_device_register(&mxc_uart_device4); +#endif /* UART4_ENABLED */ + +#if UART5_ENABLED == 1 + platform_device_register(&mxc_uart_device5); +#endif /* UART5_ENABLED */ + return 0; +} + +#else +static int __init mxc_init_uart(void) +{ + return 0; +} +#endif + +arch_initcall(mxc_init_uart); diff -urN linux-2.6.26/arch/arm/mach-mx3/serial.h linux-2.6.26-lab126/arch/arm/mach-mx3/serial.h --- linux-2.6.26/arch/arm/mach-mx3/serial.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/serial.h 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,158 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ARCH_ARM_MACH_MX3_SERIAL_H__ +#define __ARCH_ARM_MACH_MX3_SERIAL_H__ + +/*! + * @file mach-mx3/serial.h + * + * @ingroup MSL_MX31 + */ +#include + +/* UART 1 configuration */ +/*! + * This option allows to choose either an interrupt-driven software controlled + * hardware flow control (set this option to 0) or hardware-driven hardware + * flow control (set this option to 1). + */ +/* UART used as wakeup source */ +#define UART1_HW_FLOW 0 +/*! + * This specifies the threshold at which the CTS pin is deasserted by the + * RXFIFO. Set this value in Decimal to anything from 0 to 32 for + * hardware-driven hardware flow control. Read the HW spec while specifying + * this value. When using interrupt-driven software controlled hardware + * flow control set this option to -1. + */ +#define UART1_UCR4_CTSTL 16 +/*! + * This is option to enable (set this option to 1) or disable DMA data transfer + */ +#define UART1_DMA_ENABLE 0 +/*! + * Specify the size of the DMA receive buffer. The minimum buffer size is 512 + * bytes. The buffer size should be a multiple of 256. + */ +#define UART1_DMA_RXBUFSIZE 1024 +/*! + * Specify the MXC UART's Receive Trigger Level. This controls the threshold at + * which a maskable interrupt is generated by the RxFIFO. Set this value in + * Decimal to anything from 0 to 32. Read the HW spec while specifying this + * value. + */ +#define UART1_UFCR_RXTL 16 +/*! + * Specify the MXC UART's Transmit Trigger Level. This controls the threshold at + * which a maskable interrupt is generated by the TxFIFO. Set this value in + * Decimal to anything from 0 to 32. Read the HW spec while specifying this + * value. + */ +#define UART1_UFCR_TXTL 16 +/* UART 2 configuration */ +#define UART2_HW_FLOW 0 +#define UART2_UCR4_CTSTL -1 +#define UART2_DMA_ENABLE 0 +#define UART2_DMA_RXBUFSIZE 512 +#define UART2_UFCR_RXTL 16 +#define UART2_UFCR_TXTL 16 +/* UART 3 configuration */ +#define UART3_HW_FLOW 1 +#define UART3_UCR4_CTSTL 16 +#define UART3_DMA_ENABLE 1 +#define UART3_DMA_RXBUFSIZE 1024 +#define UART3_UFCR_RXTL 16 +#define UART3_UFCR_TXTL 16 +/* UART 4 configuration */ +#define UART4_HW_FLOW 1 +#define UART4_UCR4_CTSTL 16 +#define UART4_DMA_ENABLE 0 +#define UART4_DMA_RXBUFSIZE 512 +#define UART4_UFCR_RXTL 16 +#define UART4_UFCR_TXTL 16 +/* UART 5 configuration */ +#define UART5_HW_FLOW 1 +#define UART5_UCR4_CTSTL 16 +#define UART5_DMA_ENABLE 0 +#define UART5_DMA_RXBUFSIZE 512 +#define UART5_UFCR_RXTL 16 +#define UART5_UFCR_TXTL 16 +/* + * UART Chip level Configuration that a user may not have to edit. These + * configuration vary depending on how the UART module is integrated with + * the ARM core + */ +/* + * Is the MUXED interrupt output sent to the ARM core + */ +#define INTS_NOTMUXED 0 +#define INTS_MUXED 1 +/* UART 1 configuration */ +/*! + * This define specifies whether the muxed ANDed interrupt line or the + * individual interrupts from the UART port is integrated with the ARM core. + * There exists a define like this for each UART port. Valid values that can + * be used are \b INTS_NOTMUXED or \b INTS_MUXED. + */ +#define UART1_MUX_INTS INTS_MUXED +/*! + * This define specifies the transmitter interrupt number or the interrupt + * number of the ANDed interrupt in case the interrupts are muxed. There exists + * a define like this for each UART port. + */ +#define UART1_INT1 MXC_INT_UART1 +/*! + * This define specifies the receiver interrupt number. If the interrupts of + * the UART are muxed, then we specify here a dummy value -1. There exists a + * define like this for each UART port. + */ +#define UART1_INT2 -1 +/*! + * This specifies the master interrupt number. If the interrupts of the UART + * are muxed, then we specify here a dummy value of -1. There exists a define + * like this for each UART port. + */ +#define UART1_INT3 -1 +/*! + * This specifies if the UART is a shared peripheral. It holds the shared + * peripheral number if it is shared or -1 if it is not shared. There exists + * a define like this for each UART port. + */ +#define UART1_SHARED_PERI -1 +/* UART 2 configuration */ +#define UART2_MUX_INTS INTS_MUXED +#define UART2_INT1 MXC_INT_UART2 +#define UART2_INT2 -1 +#define UART2_INT3 -1 +#define UART2_SHARED_PERI -1 +/* UART 3 configuration */ +#define UART3_MUX_INTS INTS_MUXED +#define UART3_INT1 MXC_INT_UART3 +#define UART3_INT2 -1 +#define UART3_INT3 -1 +#define UART3_SHARED_PERI SPBA_UART3 +/* UART 4 configuration */ +#define UART4_MUX_INTS INTS_MUXED +#define UART4_INT1 MXC_INT_UART4 +#define UART4_INT2 -1 +#define UART4_INT3 -1 +#define UART4_SHARED_PERI -1 +/* UART 5 configuration */ +#define UART5_MUX_INTS INTS_MUXED +#define UART5_INT1 MXC_INT_UART5 +#define UART5_INT2 -1 +#define UART5_INT3 -1 +#define UART5_SHARED_PERI -1 + +#endif /* __ARCH_ARM_MACH_MX3_SERIAL_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx3/system.c linux-2.6.26-lab126/arch/arm/mach-mx3/system.c --- linux-2.6.26/arch/arm/mach-mx3/system.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/system.c 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,103 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include "crm_regs.h" + +/*! + * @defgroup MSL_MX31 i.MX31 Machine Specific Layer (MSL) + */ + +/*! + * @file mach-mx3/system.c + * @brief This file contains idle and reset functions. + * + * @ingroup MSL_MX31 + */ + +static int clks_initialized = 0; +static struct clk *sdma_clk, *mbx_clk, *ipu_clk, *mpeg_clk, *vpu_clk, *usb_clk, + *rtic_clk, *nfc_clk, *emi_clk; + +extern int mxc_jtag_enabled; + +/*! + * This function puts the CPU into idle mode. It is called by default_idle() + * in process.c file. + */ +void arch_idle(void) +{ + int emi_gated_off = 0; + + /* + * This should do all the clock switching + * and wait for interrupt tricks. + */ + if (!mxc_jtag_enabled) { + if (clks_initialized == 0) { + clks_initialized = 1; + sdma_clk = clk_get(NULL, "sdma_ahb_clk"); + ipu_clk = clk_get(NULL, "ipu_clk"); + if (cpu_is_mx31()) { + mpeg_clk = clk_get(NULL, "mpeg4_clk"); + mbx_clk = clk_get(NULL, "mbx_clk"); + } else { + vpu_clk = clk_get(NULL, "vpu_clk"); + } + usb_clk = clk_get(NULL, "usb_ahb_clk"); + rtic_clk = clk_get(NULL, "rtic_clk"); + nfc_clk = clk_get(NULL, "nfc_clk"); + emi_clk = clk_get(NULL, "emi_clk"); + } + + if ((clk_get_usecount(sdma_clk) == 0) + && (clk_get_usecount(ipu_clk) <= 1) + && (clk_get_usecount(usb_clk) == 0) + && (clk_get_usecount(rtic_clk) == 0) + && (clk_get_usecount(mpeg_clk) == 0) + && (clk_get_usecount(mbx_clk) == 0) + && (clk_get_usecount(nfc_clk) == 0) + && (clk_get_usecount(vpu_clk) == 0)) { + emi_gated_off = 1; + clk_disable(emi_clk); + } + + cpu_do_idle(); + if (emi_gated_off == 1) { + clk_enable(emi_clk); + } + } +} + +/* + * This function resets the system. It is called by machine_restart(). + * + * @param mode indicates different kinds of resets + */ +void arch_reset(char mode) +{ + /* Assert SRS signal */ + mxc_wd_reset(); +} diff -urN linux-2.6.26/arch/arm/mach-mx3/time.c linux-2.6.26-lab126/arch/arm/mach-mx3/time.c --- linux-2.6.26/arch/arm/mach-mx3/time.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/time.c 1969-12-31 19:00:00.000000000 -0500 @@ -1,148 +0,0 @@ -/* - * System Timer Interrupt reconfigured to run in free-run mode. - * Author: Vitaly Wool - * Copyright 2004 MontaVista Software Inc. - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/*! - * @file time.c - * @brief This file contains OS tick and wdog timer implementations. - * - * This file contains OS tick and wdog timer implementations. - * - * @ingroup Timers - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/*! - * This is the timer interrupt service routine to do required tasks. - * It also services the WDOG timer at the frequency of twice per WDOG - * timeout value. For example, if the WDOG's timeout value is 4 (2 - * seconds since the WDOG runs at 0.5Hz), it will be serviced once - * every 2/2=1 second. - * - * @param irq GPT interrupt source number (not used) - * @param dev_id this parameter is not used - * @return always returns \b IRQ_HANDLED as defined in - * include/linux/interrupt.h. - */ -static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) -{ - unsigned int next_match; - - if (__raw_readl(MXC_GPT_GPTSR) & GPTSR_OF1) { - do { - timer_tick(); - next_match = __raw_readl(MXC_GPT_GPTOCR1) + LATCH; - __raw_writel(GPTSR_OF1, MXC_GPT_GPTSR); - __raw_writel(next_match, MXC_GPT_GPTOCR1); - } while ((signed long)(next_match - - __raw_readl(MXC_GPT_GPTCNT)) <= 0); - } - - return IRQ_HANDLED; -} - -/*! - * This function is used to obtain the number of microseconds since the last - * timer interrupt. Note that interrupts is disabled by do_gettimeofday(). - * - * @return the number of microseconds since the last timer interrupt. - */ -static unsigned long mxc_gettimeoffset(void) -{ - unsigned long ticks_to_match, elapsed, usec, tick_usec, i; - - /* Get ticks before next timer match */ - ticks_to_match = - __raw_readl(MXC_GPT_GPTOCR1) - __raw_readl(MXC_GPT_GPTCNT); - - /* We need elapsed ticks since last match */ - elapsed = LATCH - ticks_to_match; - - /* Now convert them to usec */ - /* Insure no overflow when calculating the usec below */ - for (i = 1, tick_usec = tick_nsec / 1000;; i *= 2) { - tick_usec /= i; - if ((0xFFFFFFFF / tick_usec) > elapsed) - break; - } - usec = (unsigned long)(elapsed * tick_usec) / (LATCH / i); - - return usec; -} - -/*! - * The OS tick timer interrupt structure. - */ -static struct irqaction timer_irq = { - .name = "MXC Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = mxc_timer_interrupt -}; - -/*! - * This function is used to initialize the GPT to produce an interrupt - * based on HZ. It is called by start_kernel() during system startup. - */ -void __init mxc_init_time(void) -{ - u32 reg, v; - reg = __raw_readl(MXC_GPT_GPTCR); - reg &= ~GPTCR_ENABLE; - __raw_writel(reg, MXC_GPT_GPTCR); - reg |= GPTCR_SWR; - __raw_writel(reg, MXC_GPT_GPTCR); - - while ((__raw_readl(MXC_GPT_GPTCR) & GPTCR_SWR) != 0) - cpu_relax(); - - reg = GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ; - __raw_writel(reg, MXC_GPT_GPTCR); - - /* TODO: get timer rate from clk driver */ - v = 66500000; - - __raw_writel((v / CLOCK_TICK_RATE) - 1, MXC_GPT_GPTPR); - - if ((v % CLOCK_TICK_RATE) != 0) { - pr_info("\nWARNING: Can't generate CLOCK_TICK_RATE at %d Hz\n", - CLOCK_TICK_RATE); - } - pr_info("Actual CLOCK_TICK_RATE is %d Hz\n", - v / ((__raw_readl(MXC_GPT_GPTPR) & 0xFFF) + 1)); - - reg = __raw_readl(MXC_GPT_GPTCNT); - reg += LATCH; - __raw_writel(reg, MXC_GPT_GPTOCR1); - - setup_irq(MXC_INT_GPT, &timer_irq); - - reg = __raw_readl(MXC_GPT_GPTCR); - reg = - GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ | GPTCR_STOPEN | GPTCR_DOZEN | - GPTCR_WAITEN | GPTCR_ENMOD | GPTCR_ENABLE; - __raw_writel(reg, MXC_GPT_GPTCR); - - __raw_writel(GPTIR_OF1IE, MXC_GPT_GPTIR); -} - -struct sys_timer mxc_timer = { - .init = mxc_init_time, - .offset = mxc_gettimeoffset, -}; diff -urN linux-2.6.26/arch/arm/mach-mx3/usb.h linux-2.6.26-lab126/arch/arm/mach-mx3/usb.h --- linux-2.6.26/arch/arm/mach-mx3/usb.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/usb.h 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,122 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +extern int usbotg_init(struct platform_device *pdev); +extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata); +extern int gpio_usbotg_fs_active(void); +extern void gpio_usbotg_fs_inactive(void); +extern int gpio_usbotg_hs_active(void); +extern void gpio_usbotg_hs_inactive(void); +extern struct platform_device *host_pdev_register(struct resource *res, + int n_res, struct fsl_usb2_platform_data *config); + +extern int fsl_usb_host_init(struct platform_device *pdev); +extern void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata); +extern int gpio_usbh1_active(void); +extern void gpio_usbh1_inactive(void); +extern int gpio_usbh2_active(void); +extern void gpio_usbh2_inactive(void); + +/* + * Determine which platform_data struct to use for the DR controller, + * based on which transceiver is configured. + * PDATA is a pointer to it. + */ +#if defined(CONFIG_ISP1504_MXC) +static struct fsl_usb2_platform_data __maybe_unused dr_1504_config; +#define PDATA (&dr_1504_config) +#elif defined(CONFIG_ISP1301_MXC) +static struct fsl_usb2_platform_data __maybe_unused dr_1301_config; +#define PDATA (&dr_1301_config) +#elif defined(CONFIG_MC13783_MXC) +static struct fsl_usb2_platform_data __maybe_unused dr_13783_config; +#define PDATA (&dr_13783_config) +#endif + + +/* + * Used to set pdata->operating_mode before registering the platform_device. + * If OTG is configured, the controller operates in OTG mode, + * otherwise it's either host or device. + */ +#ifdef CONFIG_USB_OTG +#define DR_UDC_MODE FSL_USB2_DR_OTG +#define DR_HOST_MODE FSL_USB2_DR_OTG +#else +#define DR_UDC_MODE FSL_USB2_DR_DEVICE +#define DR_HOST_MODE FSL_USB2_DR_HOST +#endif + + +#ifdef CONFIG_USB_EHCI_ARC_OTG +static inline void dr_register_host(struct resource *r, int rs) +{ + struct platform_device *dr_pdev; + + PDATA->operating_mode = DR_HOST_MODE; + dr_pdev = host_pdev_register(r, rs, PDATA); +#ifdef CONFIG_USB_EHCI_ARC_OTG_WAKE_UP + /* set host may and should wakeup */ + device_init_wakeup(&(dr_pdev->dev), 1); +#endif +} +#else +static inline void dr_register_host(struct resource *r, int rs) +{ +} +#endif + +#ifdef CONFIG_USB_GADGET_ARC +static struct platform_device dr_udc_device; + +static inline void dr_register_udc(void) +{ + PDATA->operating_mode = DR_UDC_MODE; + dr_udc_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_udc_device)) + printk(KERN_ERR "usb: can't register DR gadget\n"); + else + printk(KERN_INFO "usb: DR gadget (%s) registered\n", + PDATA->transceiver); +} +#else +static inline void dr_register_udc(void) +{ +} +#endif + +#ifdef CONFIG_USB_OTG +static struct platform_device dr_otg_device; + +/* + * set the proper operating_mode and + * platform_data pointer, then register the + * device. + */ +static inline void dr_register_otg(void) +{ + PDATA->operating_mode = FSL_USB2_DR_OTG; + dr_otg_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_otg_device)) + printk(KERN_ERR "usb: can't register otg device\n"); + else + printk(KERN_INFO "usb: DR OTG registered\n"); +} +#else +static inline void dr_register_otg(void) +{ +} +#endif diff -urN linux-2.6.26/arch/arm/mach-mx3/usb_dr.c linux-2.6.26-lab126/arch/arm/mach-mx3/usb_dr.c --- linux-2.6.26/arch/arm/mach-mx3/usb_dr.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/usb_dr.c 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,128 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include "usb.h" + +/* + * platform data structs + * - Which one to use is determined by CONFIG options in usb.h + * - operating_mode plugged at run time + */ +static struct fsl_usb2_platform_data __maybe_unused dr_13783_config = { + .name = "DR", + .platform_init = usbotg_init, + .platform_uninit = usbotg_uninit, + .phy_mode = FSL_USB2_PHY_SERIAL, + .power_budget = 500, /* 500 mA max power */ + .gpio_usb_active = gpio_usbotg_fs_active, + .gpio_usb_inactive = gpio_usbotg_fs_inactive, + .transceiver = "mc13783", +}; + +static struct fsl_usb2_platform_data __maybe_unused dr_1301_config = { + .name = "DR", + .platform_init = usbotg_init, + .platform_uninit = usbotg_uninit, + .phy_mode = FSL_USB2_PHY_SERIAL, + .power_budget = 150, /* 150 mA max power */ + .gpio_usb_active = gpio_usbotg_fs_active, + .gpio_usb_inactive = gpio_usbotg_fs_inactive, + .transceiver = "isp1301", +}; + +static struct fsl_usb2_platform_data __maybe_unused dr_1504_config = { + .name = "DR", + .platform_init = usbotg_init, + .platform_uninit = usbotg_uninit, + .phy_mode = FSL_USB2_PHY_ULPI, + .power_budget = 150, /* 150 mA max power */ + .gpio_usb_active = gpio_usbotg_hs_active, + .gpio_usb_inactive = gpio_usbotg_hs_inactive, + .transceiver = "isp1504", +}; + + +/* + * resources + */ +static struct resource otg_resources[] = { + [0] = { + .start = (u32)(USB_OTGREGS_BASE), + .end = (u32)(USB_OTGREGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_USB3, + .flags = IORESOURCE_IRQ, + }, +}; + + +static u64 dr_udc_dmamask = ~(u32) 0; +static void dr_udc_release(struct device *dev) +{ +} + +static u64 dr_otg_dmamask = ~(u32) 0; +static void dr_otg_release(struct device *dev) +{ +} + +/* + * platform device structs + * dev.platform_data field plugged at run time + */ +static struct platform_device __maybe_unused dr_udc_device = { + .name = "fsl-usb2-udc", + .id = -1, + .dev = { + .release = dr_udc_release, + .dma_mask = &dr_udc_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), +}; + +static struct platform_device __maybe_unused dr_otg_device = { + .name = "fsl-usb2-otg", + .id = -1, + .dev = { + .release = dr_otg_release, + .dma_mask = &dr_otg_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), +}; + +static int __init usb_dr_init(void) +{ + pr_debug("%s: \n", __func__); + + dr_register_otg(); + dr_register_host(otg_resources, ARRAY_SIZE(otg_resources)); + dr_register_udc(); +#ifdef CONFIG_USB_GADGET_WAKE_UP + /* set udc may and should wakeup */ + device_init_wakeup(&(dr_udc_device.dev), 1); +#endif + return 0; +} + +module_init(usb_dr_init); diff -urN linux-2.6.26/arch/arm/mach-mx3/usb_h1.c linux-2.6.26-lab126/arch/arm/mach-mx3/usb_h1.c --- linux-2.6.26/arch/arm/mach-mx3/usb_h1.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/usb_h1.c 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,53 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include "usb.h" + +static struct fsl_usb2_platform_data usbh1_config = { + .name = "Host 1", + .platform_init = fsl_usb_host_init, + .platform_uninit = fsl_usb_host_uninit, + .operating_mode = FSL_USB2_MPH_HOST, + .phy_mode = FSL_USB2_PHY_SERIAL, + .power_budget = 500, /* 500 mA max power */ + .gpio_usb_active = gpio_usbh1_active, + .gpio_usb_inactive = gpio_usbh1_inactive, + .transceiver = "serial", +}; + +static struct resource usbh1_resources[] = { + [0] = { + .start = (u32) (USB_H1REGS_BASE), + .end = (u32) (USB_H1REGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_USB1, + .flags = IORESOURCE_IRQ, + }, +}; + +static int __init usbh1_init(void) +{ + pr_debug("%s: \n", __func__); + + host_pdev_register(usbh1_resources, ARRAY_SIZE(usbh1_resources), + &usbh1_config); + return 0; +} +module_init(usbh1_init); diff -urN linux-2.6.26/arch/arm/mach-mx3/usb_h2.c linux-2.6.26-lab126/arch/arm/mach-mx3/usb_h2.c --- linux-2.6.26/arch/arm/mach-mx3/usb_h2.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx3/usb_h2.c 2010-08-10 04:14:16.000000000 -0400 @@ -0,0 +1,75 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "usb.h" + +static struct fsl_usb2_platform_data usbh2_config = { + .name = "Host 2", + .platform_init = fsl_usb_host_init, + .platform_uninit = fsl_usb_host_uninit, + .operating_mode = FSL_USB2_MPH_HOST, + .phy_mode = FSL_USB2_PHY_ULPI, + .power_budget = 500, /* 500 mA max power */ + .gpio_usb_active = gpio_usbh2_active, + .gpio_usb_inactive = gpio_usbh2_inactive, + .transceiver = "isp1504", +}; + +static struct resource usbh2_resources[] = { + [0] = { + .start = (u32) (USB_H2REGS_BASE), + .end = (u32) (USB_H2REGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_USB2, + .flags = IORESOURCE_IRQ, + }, +}; + +static int __init usbh2_init(void) +{ + struct platform_device *h2_pdev; + + pr_debug("%s: \n", __func__); + + if (machine_is_mx31_3ds()) { + struct regulator *usbh2_regux; + usbh2_config.xcvr_pwr = + kmalloc(sizeof(struct fsl_xcvr_power), GFP_KERNEL); + if (!(usbh2_config.xcvr_pwr)) + return -ENOMEM; + + usbh2_regux = regulator_get(NULL, "GPO1"); + usbh2_config.xcvr_pwr->regu1 = usbh2_regux; + usbh2_regux = regulator_get(NULL, "GPO3"); + usbh2_config.xcvr_pwr->regu2 = usbh2_regux; + } + + h2_pdev = host_pdev_register(usbh2_resources, + ARRAY_SIZE(usbh2_resources), &usbh2_config); +#ifdef CONFIG_USB_EHCI_ARC_H2_WAKE_UP + /* set host2 may and should wakeup */ + device_init_wakeup(&(h2_pdev->dev), 1); +#endif + return 0; +} +module_init(usbh2_init); diff -urN linux-2.6.26/arch/arm/mach-mx35/Kconfig linux-2.6.26-lab126/arch/arm/mach-mx35/Kconfig --- linux-2.6.26/arch/arm/mach-mx35/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/Kconfig 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,148 @@ +menu "MX35 Options" + depends on ARCH_MX35 + +config MX35_OPTIONS + bool + default y + select CPU_V6 + select CACHE_L2X0 + select OUTER_CACHE + select USB_ARCH_HAS_EHCI + select ARCH_HAS_EVTMON + select ARCH_HAS_RNGC + +config MACH_MX35_3DS + bool "Support MX35 3STACK platforms" + default y + select MXC_PSEUDO_IRQS if MXC_PMIC_MC9SDZ60 + help + Include support for MX35 3STACK platform. This includes specific + configurations for the board and its peripherals. + +config MACH_MX35_LUIGI + bool "Support for MX35 LUIGI Platform" + default y + select MACH_LUIGI_LAB126 + help + Include support for the MX35 Luigi Platform from LAB126. + +config MACH_LUIGI_LAB126 + bool "Enable Lab126 specific changes for the Luigi Platform" + +config MACH_MX35EVB + bool "Support MX35EVB platforms" + default n + help + Include support for MX35EVB platform. This includes specific + configurations for the board and its peripherals. + +config MX35_DOZE_DURING_IDLE + bool "Enter Doze mode during idle" + help + Turning on this option will put the CPU into Doze mode during idle. + The default is to enter Wait mode during idle. Doze mode during + idle will save additional power over Wait mode. + +config MXC_GPIO_DEBUG + bool "Dump backtrace to debug GPIO issues" + help + There are several places in the kernel/drivers code where + a GPIO pin is reserved twice or freed twice. This option when enabled + dumps a backtrace the point the location which tried to request/free + the GPIO pin twice + +config MX35_FIQ + bool "Enable the FIQ on the MX35" + select FIQ + help + This option enables the FIQ on MX35 based SoC + +config MXC_SDMA_API + bool "Use SDMA API" + default y + help + This selects the Freescale MXC SDMA API. + If unsure, say N. + +menu "SDMA options" + depends on MXC_SDMA_API + +config SDMA_IRAM + bool "Use Internal RAM for SDMA transfer" + default n + help + Support Internal RAM as SDMA buffer or control structures + +config SDMA_IRAM_SIZE + hex "Reserved bytes of IRAM for SDMA (0x800-0x1000)" + range 0x800 0x1000 + depends on SDMA_IRAM + default "0x1000" + help + Set the size of IRAM for SDMA. It must be a multiple of 512bytes. +endmenu + +config ARCH_MXC_HAS_NFC_V2 + bool "MXC NFC Hardware Version 2" + depends on ARCH_MX35 + default y + help + This selects the Freescale MXC Nand Flash Controller Hardware Version 3 + If unsure, say N. + +config ARCH_MXC_HAS_NFC_V2_1 + bool "MXC NFC Hardware Version 2.1" + depends on ARCH_MXC_HAS_NFC_V2 + default y + help + This selects the Freescale MXC Nand Flash Controller Hardware Version 2.1 + If unsure, say N. + +menu "Device options" + +config I2C_MXC_SELECT1 + bool "Enable I2C1 module" + default y + depends on I2C_MXC + help + Enable MX35 I2C1 module. + +config I2C_MXC_SELECT2 + bool "Enable I2C2 module" + default n + depends on I2C_MXC + help + Enable MX35 I2C2 module. + +config I2C_MXC_SELECT3 + bool "Enable I2C3 module" + default n + depends on I2C_MXC + help + Enable MX35 I2C3 module. + +endmenu + +config MXC_PSEUDO_IRQS + bool + +config PROC_BOOTDATA + bool "Boot data driver" + default y + depends on MACH_MX35_LUIGI + ---help--- + This option enables the creation of the /proc/bd/ entries, + which provide an interface for accessing various shared boot + global data entries in the common memory space between the + kernel and bootloader. + +config PROC_BOARDID + bool "Device Board ID and Serial Number driver" + default y + depends on MACH_MX35_LUIGI + ---help--- + This option enables the creation of the /proc/board_id and + /proc/serialnumber entries, which returns the unique serial number of + the device. + +endmenu diff -urN linux-2.6.26/arch/arm/mach-mx35/Makefile linux-2.6.26-lab126/arch/arm/mach-mx35/Makefile --- linux-2.6.26/arch/arm/mach-mx35/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/Makefile 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,24 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. + +obj-y := system.o iomux.o cpu.o mm.o clock.o devices.o serial.o +obj-$(CONFIG_MXC_SDMA_API) += dma.o +obj-$(CONFIG_MACH_MX35_3DS) += mx35_3stack.o mx35_3stack_gpio.o mx35_3stack_cpld.o dvfs.o +obj-$(CONFIG_MACH_MX35EVB) += mx35evb.o mx35evb_cpld.o mx35evb_gpio.o +obj-$(CONFIG_MACH_MX35_LUIGI) += mx35_luigi.o mx35_luigi_gpio.o dvfs.o wifi.o boot_globals.o mx35_accessory.o + +obj-$(CONFIG_MXC_PSEUDO_IRQS) += mx35_3stack_irq.o +obj-$(CONFIG_PM) += pm.o + +obj-$(CONFIG_CPU_FREQ) += cpufreq.o +obj-$(CONFIG_USB_EHCI_ARC_H2) += usb_h2.o + +ifneq ($(strip $(CONFIG_USB_GADGET_ARC) $(CONFIG_USB_EHCI_ARC_OTG)),) + obj-y += usb_dr.o +endif + +obj-$(CONFIG_PROC_BOOTDATA) += bootdata.o +obj-$(CONFIG_PROC_BOARDID) += boardid.o diff -urN linux-2.6.26/arch/arm/mach-mx35/Makefile.boot linux-2.6.26-lab126/arch/arm/mach-mx35/Makefile.boot --- linux-2.6.26/arch/arm/mach-mx35/Makefile.boot 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/Makefile.boot 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,9 @@ +ifeq ($(CONFIG_MACH_MX35EVB), y) + zreladdr-y := 0x90008000 +params_phys-y := 0x90000100 +initrd_phys-y := 0x90800000 +else + zreladdr-y := 0x80008000 +params_phys-y := 0x80000100 +initrd_phys-y := 0x80800000 +endif diff -urN linux-2.6.26/arch/arm/mach-mx35/board-mx35_3stack.h linux-2.6.26-lab126/arch/arm/mach-mx35/board-mx35_3stack.h --- linux-2.6.26/arch/arm/mach-mx35/board-mx35_3stack.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/board-mx35_3stack.h 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,210 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX35_3STACK_H__ +#define __ASM_ARCH_MXC_BOARD_MX35_3STACK_H__ + +#if defined(CONFIG_MACH_MX35_3DS) || defined(CONFIG_MACH_MX35_LUIGI) + +/*! + * @defgroup BRDCFG_MX35 Board Configuration Options + * @ingroup MSL_MX35 + */ + +/*! + * @file mach-mx35/board-mx35_3stack.h + * + * @brief This file contains all the board level configuration options. + * + * It currently hold the options defined for MX35 3STACK Platform. + * + * @ingroup BRDCFG_MX35 + */ + +/* + * Include Files + */ +#include + +/*! + * @name MXC UART EVB board level configurations + */ +/*! @{ */ +/*! + * Specifies if the Irda transmit path is inverting + */ +#define MXC_IRDA_TX_INV 0 +/*! + * Specifies if the Irda receive path is inverting + */ +#define MXC_IRDA_RX_INV 0 + +/* UART 1 configuration */ +/*! + * This define specifies if the UART port is configured to be in DTE or + * DCE mode. There exists a define like this for each UART port. Valid + * values that can be used are \b MODE_DTE or \b MODE_DCE. + */ +#define UART1_MODE MODE_DCE +/*! + * This define specifies if the UART is to be used for IRDA. There exists a + * define like this for each UART port. Valid values that can be used are + * \b IRDA or \b NO_IRDA. + */ +#define UART1_IR NO_IRDA +/*! + * This define is used to enable or disable a particular UART port. If + * disabled, the UART will not be registered in the file system and the user + * will not be able to access it. There exists a define like this for each UART + * port. Specify a value of 1 to enable the UART and 0 to disable it. + */ +#define UART1_ENABLED 1 +/*! @} */ +/* UART 2 configuration */ +#define UART2_MODE MODE_DTE +#define UART2_IR NO_IRDA +#define UART2_ENABLED 1 + +/* UART 3 configuration */ +#define UART3_MODE MODE_DTE +#define UART3_IR NO_IRDA +#define UART3_ENABLED 1 + +#define MXC_LL_UART_PADDR UART1_BASE_ADDR +#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) + +#define MXC_PSEUDO_PARENT MXC_INT_RESV0 + +enum { + MCU_INT_HEADPHONE = 0, + MCU_INT_GPS, + MCU_INT_SD1_CD, + MCU_INT_SD1_WP, + MCU_INT_SD2_CD, + MCU_INT_SD2_WP, + MCU_INT_POWER_KEY, + MCU_INT_RTC, + MCU_INT_TS_ADC, + MCU_INT_TS_CALIBRATE, + MCU_INT_KEYPAD, +}; + +#define MXC_PSEUDO_IRQ_HEADPHONE (MXC_PSEUDO_IO_BASE + MCU_INT_HEADPHONE) +#define MXC_PSEUDO_IRQ_GPS (MXC_PSEUDO_IO_BASE + MCU_INT_GPS) +#define MXC_PSEUDO_IRQ_SD1_CD (MXC_PSEUDO_IO_BASE + MCU_INT_SD1_CD) +#define MXC_PSEUDO_IRQ_SD1_WP (MXC_PSEUDO_IO_BASE + MCU_INT_SD1_WP) +#define MXC_PSEUDO_IRQ_SD2_CD (MXC_PSEUDO_IO_BASE + MCU_INT_SD2_CD) +#define MXC_PSEUDO_IRQ_SD2_WP (MXC_PSEUDO_IO_BASE + MCU_INT_SD2_WP) +#define MXC_PSEUDO_IRQ_POWER_KEY (MXC_PSEUDO_IO_BASE + MCU_INT_POWER_KEY) +#define MXC_PSEUDO_IRQ_KEYPAD (MXC_PSEUDO_IO_BASE + MCU_INT_KEYPAD) +#define MXC_PSEUDO_IRQ_RTC (MXC_PSEUDO_IO_BASE + MCU_INT_RTC) +#define MXC_PSEUDO_IRQ_TS_ADC (MXC_PSEUDO_IO_BASE + MCU_INT_TS_ADC) + +/*! + * @name debug board parameters + */ +/*! @{ */ +/*! + * Base address of debug board + */ +#define DEBUG_BASE_ADDRESS CS5_BASE_ADDR + +/* External ethernet LAN9217 base address */ +#define LAN9217_BASE_ADDR DEBUG_BASE_ADDRESS + +/* External UART */ +#define UARTA_BASE_ADDR (DEBUG_BASE_ADDRESS + 0x08000) +#define UARTB_BASE_ADDR (DEBUG_BASE_ADDRESS + 0x10000) + +#define BOARD_IO_ADDR (DEBUG_BASE_ADDRESS + 0x20000) + +/* LED switchs */ +#define LED_SWITCH_REG 0x00 +/* buttons */ +#define SWITCH_BUTTON_REG 0x08 +/* status, interrupt */ +#define INTR_STATUS_REG 0x10 +#define INTR_RESET_REG 0x20 +/*CPLD configuration*/ +#define CONFIG1_REG 0x28 +#define CONFIG2_REG 0x30 +/*interrupt mask */ +#define INTR_MASK_REG 0x38 + +/* magic word for debug CPLD */ +#define MAGIC_NUMBER1_REG 0x40 +#define MAGIC_NUMBER2_REG 0x48 +/* CPLD code version */ +#define CPLD_CODE_VER_REG 0x50 +/* magic word for debug CPLD */ +#define MAGIC3_NUMBER3_REG 0x58 +/* module reset register*/ +#define CONTROL_REG 0x60 +/* CPU ID and Personality ID*/ +#define IDENT_REG 0x68 + +/* For interrupts like xuart, enet etc */ +#define EXPIO_PARENT_INT MX35_PIN_GPIO1_1 + +#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 0) +#define EXPIO_INT_XUARTA_INT (MXC_EXP_IO_BASE + 1) +#define EXPIO_INT_XUARTB_INT (MXC_EXP_IO_BASE + 2) +#define EXPIO_INT_BUTTONA_INT (MXC_EXP_IO_BASE + 3) +#define EXPIO_INT_BUTTONB_INT (MXC_EXP_IO_BASE + 4) + +/*! This is System IRQ used by LAN9217 for interrupt generation taken + * from platform.h + */ +#define LAN9217_IRQ EXPIO_INT_ENET_INT + +/*! This is base virtual address of debug board*/ +extern unsigned int mx35_3stack_board_io; + +#define MXC_BD_LED1 (1) +#define MXC_BD_LED2 (1 << 1) +#define MXC_BD_LED3 (1 << 2) +#define MXC_BD_LED4 (1 << 3) +#define MXC_BD_LED5 (1 << 4) +#define MXC_BD_LED6 (1 << 5) +#define MXC_BD_LED7 (1 << 6) +#define MXC_BD_LED8 (1 << 7) +#define MXC_BD_LED_ON(led) +#define MXC_BD_LED_OFF(led) + +/*! @} */ + +#define AHB_FREQ 133000000 +#define IPG_FREQ 66500000 + +extern void mxc_map_io(void); +extern void mxc_init_irq(void); +extern void mxc_cpu_init(void) __init; +#ifdef CONFIG_MACH_MX35_LUIGI +extern void mx35_luigi_gpio_init(void) __init; +#else +extern void mx35_3stack_gpio_init(void) __init; +#endif +extern struct sys_timer mxc_timer; +extern void mxc_cpu_common_init(void); +extern int mxc_clocks_init(void); +extern void __init early_console_setup(char *); +extern void gpio_tsc_active(void); +extern void gpio_tsc_inactive(void); +extern unsigned int sdhc_get_card_det_status(struct device *dev); +extern int sdhc_write_protect(struct device *dev); +extern void gpio_can_active(int id); +extern void gpio_can_inactive(int id); +extern struct flexcan_platform_data flexcan_data[]; + +#endif /* CONFIG_MACH_MX35_3DS */ +#endif /* __ASM_ARCH_MXC_BOARD_MX35_3STACK_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx35/board-mx35evb.h linux-2.6.26-lab126/arch/arm/mach-mx35/board-mx35evb.h --- linux-2.6.26/arch/arm/mach-mx35/board-mx35evb.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/board-mx35evb.h 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,151 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX35EVB_H__ +#define __ASM_ARCH_MXC_BOARD_MX35EVB_H__ + +#ifdef CONFIG_MACH_MX35EVB +/*! + * @defgroup BRDCFG_MX35 Board Configuration Options + * @ingroup MSL_MX35 + */ + +/*! + * @file mach-mx35/board-mx35evb.h + * + * @brief This file contains all the board level configuration options. + * + * It currently hold the options defined for MX35 EVB Platform. + * + * @ingroup BRDCFG_MX35 + */ + +/* + * Include Files + */ +#include + +/*! + * @name MXC UART EVB board level configurations + */ +/*! @{ */ +/*! + * Specifies if the Irda transmit path is inverting + */ +#define MXC_IRDA_TX_INV 0 +/*! + * Specifies if the Irda receive path is inverting + */ +#define MXC_IRDA_RX_INV 0 + +/* UART 1 configuration */ +/*! + * This define specifies if the UART port is configured to be in DTE or + * DCE mode. There exists a define like this for each UART port. Valid + * values that can be used are \b MODE_DTE or \b MODE_DCE. + */ +#define UART1_MODE MODE_DCE +/*! + * This define specifies if the UART is to be used for IRDA. There exists a + * define like this for each UART port. Valid values that can be used are + * \b IRDA or \b NO_IRDA. + */ +#define UART1_IR NO_IRDA +/*! + * This define is used to enable or disable a particular UART port. If + * disabled, the UART will not be registered in the file system and the user + * will not be able to access it. There exists a define like this for each UART + * port. Specify a value of 1 to enable the UART and 0 to disable it. + */ +#define UART1_ENABLED 1 +/*! @} */ +/* UART 2 configuration */ +#define UART2_MODE MODE_DCE +#define UART2_IR NO_IRDA +#define UART2_ENABLED 1 + +/* UART 3 configuration */ +#define UART3_MODE MODE_DTE +#define UART3_IR NO_IRDA +#define UART3_ENABLED 1 + +#define MXC_LL_UART_PADDR UART1_BASE_ADDR +#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) + +/*! + * @name PBC Controller parameters + */ +/*! + * Base address of PBC controller + */ +/*! @{ */ +#define PBC_BASE_ADDRESS CS4_BASE_ADDR + +#define PBC_VERSION 0x0000 +#define PBC_BCTRL1_SET 0x0008 +#define PBC_BCTRL1_CLR 0x000C +#define PBC_BCTRL2_SET 0x0010 +#define PBC_BCTRL2_CLR 0x0014 +#define PBC_IMR1_SET 0x0018 +#define PBC_IMR1_CLR 0x001C +#define PBC_IMR2_SET 0x0020 +#define PBC_IMR2_CLR 0x0024 +#define PBC_BSTAT1 0x0028 +#define PBC_ISR 0x002C + +#define ENET_BASE_ADDRESS (PBC_BASE_ADDRESS + 0x20000) + +/*! Definitions in Board Control Register 1 */ +#define PBC_BCTRL1_ENET_RESET_B (1) +#define PBC_BCTRL1_FEC_RESET_B (1<<2) + +/*! @} */ + +#define EXPIO_PARENT_INT_0 IOMUX_TO_IRQ(MX35_PIN_GPIO1_0) +#define EXPIO_PARENT_INT_1 IOMUX_TO_IRQ(MX35_PIN_GPIO1_1) + +#define EXPIO_PARENT_INT EXPIO_PARENT_INT_1 +#define EXPIO_PARENT_INT_PIN MX35_PIN_GPIO1_1 + +#define EXPIO_INT_FEC (EXPIO_PARENT_INT + 0) +#define EXPIO_INT_ENET (EXPIO_PARENT_INT + 1) + +extern unsigned int mx35evb_board_io; + +#define MXC_BD_LED1 (1) +#define MXC_BD_LED2 (1 << 1) +#define MXC_BD_LED3 (1 << 2) +#define MXC_BD_LED4 (1 << 3) +#define MXC_BD_LED_ON(led) \ + __raw_writew(led, mx35evb_bard_io + PBC_BCTRL2_SET) +#define MXC_BD_LED_OFF(led) \ + __raw_writew(led, mx35evb_bard_io + PBC_BCTRL2_CLR) + +#define AHB_FREQ 133000000 +#define IPG_FREQ 66500000 +/*! + * Specifies if the MXC Write Protectect function is suppport or not. + */ +#define MXC_MMC_WRITE_PROTECT 1 + +extern void mxc_map_io(void); +extern void mxc_init_irq(void); +extern void mxc_cpu_init(void) __init; +extern void mx35evb_gpio_init(void) __init; +extern struct sys_timer mxc_timer; +extern void mxc_cpu_common_init(void); +extern int mxc_clocks_init(void); +extern void __init early_console_setup(char *); + +#endif /* CONFIG_MACH_MX35EVB */ +#endif /* __ASM_ARCH_MXC_BOARD_MX35EVB_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx35/boardid.c linux-2.6.26-lab126/arch/arm/mach-mx35/boardid.c --- linux-2.6.26/arch/arm/mach-mx35/boardid.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/boardid.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,207 @@ +/* + * boardid.c + * + * Copyright (C) 2008,2009 Amazon Technologies, Inc. All rights reserved. + * Jon Mayo + * + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_VER "1.0" +#define DRIVER_INFO "Board ID and Serial Number driver for Lab126 boards version " DRIVER_VER + +#define BOARDID_USID_PROCNAME "usid" +#define BOARDID_PROCNAME_BOARDID "board_id" +#define BOARDID_PROCNAME_PANELID "panel_id" +#define BOARDID_PROCNAME_PCBSN "pcbsn" + +#define SERIAL_NUM_BASE 0 +#define SERIAL_NUM_SIZE 16 + +#define BOARD_ID_BASE (SERIAL_NUM_BASE + SERIAL_NUM_SIZE) +#define BOARD_ID_SIZE 16 + +#define PANEL_ID_BASE (BOARD_ID_BASE + BOARD_ID_SIZE) +#define PANEL_ID_SIZE 32 + +#define PCB_ID_BASE 516 +#define PCB_ID_SIZE 8 + +#ifndef MIN +#define MIN(x,y) ((x) < (y) ? (x) : (y)) +#endif + +char mx35_serial_number[SERIAL_NUM_SIZE + 1]; +EXPORT_SYMBOL(mx35_serial_number); + +char mx35_board_id[BOARD_ID_SIZE + 1]; +EXPORT_SYMBOL(mx35_board_id); + +char mx35_panel_id[PANEL_ID_SIZE + 1]; +EXPORT_SYMBOL(mx35_panel_id); + +char mx35_pcb_id[PCB_ID_SIZE + 1]; +EXPORT_SYMBOL(mx35_pcb_id); + +static int proc_id_read(char *page, char **start, off_t off, int count, + int *eof, void *data, char *id) +{ + strcpy(page, id); + *eof = 1; + + return strlen(page); +} + +#define PROC_ID_READ(id) proc_id_read(page, start, off, count, eof, data, id) + +static int proc_usid_read(char *page, char **start, off_t off, int count, + int *eof, void *data) +{ + return PROC_ID_READ(mx35_serial_number); +} + +static int proc_usid_write(struct file *file, const char __user *buf, unsigned long count, void *data) +{ + char lbuf[SERIAL_NUM_SIZE]; + + memset(lbuf, 0, sizeof(lbuf)); + + if (copy_from_user(lbuf, buf, sizeof(lbuf))) { + return -EFAULT; + } + strcpy(mx35_serial_number, lbuf); + mx35_serial_number[SERIAL_NUM_SIZE]='\0'; + /* printk("MX35 Serial Number - %s\n", mx35_serial_number); */ + printk("MX35 Serial Number changed.\n"); + strncpy(system_serial16, mx35_serial_number, SERIAL16_SIZE); + return count; +} + +static int proc_board_id_read(char *page, char **start, off_t off, int count, + int *eof, void *data) +{ + return PROC_ID_READ(mx35_board_id); +} + +static int proc_panel_id_read(char *page, char **start, off_t off, int count, + int *eof, void *data) +{ + return PROC_ID_READ(mx35_panel_id); +} + +static int proc_panel_id_write(struct file *file, const char __user *buf, unsigned long count, void *data) +{ + char lbuf[PANEL_ID_SIZE]; + memset(lbuf, 0, sizeof(lbuf)); + + if (copy_from_user(lbuf, buf, sizeof(lbuf))) { + return -EFAULT; + } + strcpy(mx35_panel_id, lbuf); + mx35_panel_id[PANEL_ID_SIZE]='\0'; + printk ("MX35 Panel id - %s\n", mx35_panel_id); + return count; +} + +static int proc_pcb_id_read(char *page, char **start, off_t off, int count, + int *eof, void *data) +{ + return PROC_ID_READ(mx35_pcb_id); +} + +static int proc_pcb_id_write(struct file *file, const char __user *buf, unsigned long count, void *data) +{ + char lbuf[PCB_ID_SIZE]; + memset(lbuf, 0, sizeof(lbuf)); + + if (copy_from_user(lbuf, buf, sizeof(lbuf))) { + return -EFAULT; + } + strcpy(mx35_pcb_id, lbuf); + mx35_pcb_id[PCB_ID_SIZE]='\0'; + printk ("MX35 PCB id - %s\n", mx35_pcb_id); + return count; +} + +/* initialize the proc accessors */ +static void mx35_serialnumber_init(void) +{ + struct proc_dir_entry *proc_usid = create_proc_entry(BOARDID_USID_PROCNAME, S_IRUGO, NULL); + struct proc_dir_entry *proc_board_id = create_proc_entry(BOARDID_PROCNAME_BOARDID, S_IRUGO, NULL); + struct proc_dir_entry *proc_panel_id = create_proc_entry(BOARDID_PROCNAME_PANELID, S_IRUGO, NULL); + struct proc_dir_entry *proc_pcb_id = create_proc_entry(BOARDID_PROCNAME_PCBSN, S_IRUGO, NULL); + + if (proc_usid != NULL) { + proc_usid->data = NULL; + proc_usid->read_proc = proc_usid_read; + proc_usid->write_proc = proc_usid_write; + } + + if (proc_board_id != NULL) { + proc_board_id->data = NULL; + proc_board_id->read_proc = proc_board_id_read; + proc_board_id->write_proc = NULL; + } + + if (proc_panel_id != NULL) { + proc_panel_id->data = NULL; + proc_panel_id->read_proc = proc_panel_id_read; + proc_panel_id->write_proc = proc_panel_id_write; + } + + if (proc_pcb_id != NULL) { + proc_pcb_id->data = NULL; + proc_pcb_id->read_proc = proc_pcb_id_read; + proc_pcb_id->write_proc = proc_pcb_id_write; + } +} + +/* copy the serial numbers from the special area of memory into the kernel */ +static void mx35_serial_board_numbers(void) +{ + memcpy(mx35_serial_number, system_serial16, MIN(sizeof(mx35_serial_number)-1, sizeof(system_serial16))); + mx35_serial_number[sizeof(mx35_serial_number)-1] = '\0'; + + memcpy(mx35_board_id, system_rev16, MIN(sizeof(mx35_board_id)-1, sizeof(system_rev16))); + mx35_board_id[sizeof(mx35_board_id)-1] = '\0'; + + strcpy(mx35_panel_id, ""); /* start these as empty and populate later. */ + strcpy(mx35_pcb_id, ""); + + // Removed per official request to rid the log of FSN + //printk ("MX35 Serial Number - %s\n", mx35_serial_number); + printk ("MX35 Board id - %s\n", mx35_board_id); + + /* these wouldn't be initialized through ATAGS this early, so don't print them. */ + /* + printk ("MX35 Panel id - %s\n", mx35_panel_id); + printk ("MX35 PCB id - %s\n", mx35_pcb_id); + */ +} + +void mx35_init_boardid(void) +{ + pr_info(DRIVER_INFO "\n"); + + mx35_serial_board_numbers(); + + mx35_serialnumber_init(); +} diff -urN linux-2.6.26/arch/arm/mach-mx35/boardid.h linux-2.6.26-lab126/arch/arm/mach-mx35/boardid.h --- linux-2.6.26/arch/arm/mach-mx35/boardid.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/boardid.h 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,20 @@ +/* + * Copyright 2009 Lab126, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MACH_MX35_BOARDID_H__ +#define __MACH_MX35_BOARDID_H__ + +/* boardid.c */ +void mx35_init_boardid(void); + +#endif diff -urN linux-2.6.26/arch/arm/mach-mx35/boot_globals.c linux-2.6.26-lab126/arch/arm/mach-mx35/boot_globals.c --- linux-2.6.26/arch/arm/mach-mx35/boot_globals.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/boot_globals.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,777 @@ +/* + * Globals used to communicate between the bootloader (U-Boot) and the + * the kernel (Linux) across boot-ups and restarts. + * + * Copyright (C)2006-2008 Lab126, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define CRC32_RESIDUE 0xdebb20e3UL + +extern int boot_milestone_write(const char *name, unsigned long name_len); + +static const struct flag_cb { + char *path; + unsigned long (*flag_get)(void); + void (*flag_set)(unsigned long); +} flag_proc[] = { + { "warm_restart_flag", get_warm_restart_flag, set_warm_restart_flag }, + { "kernel_boot_flag", get_kernel_boot_flag, set_kernel_boot_flag }, +}; + +static unsigned long boot_globals_start = BOOT_GLOBALS_BASE; +static boot_globals_t *boot_globals = NULL; + +/* Return the CRC of the bytes buf[0..len-1]. */ +static unsigned bg_crc32(unsigned char *buf, int len) { + return ~crc32_le(~0L, buf, len); +} + +static int reboot_boot_globals(struct notifier_block *self, unsigned long u, void *v) +{ + // Say we're "warm" and not (still) hardware-reset. + // + set_warm_restart_flag(BOOT_GLOBALS_WARM_FLAG); + + return NOTIFY_DONE; +} + +static struct notifier_block reboot_boot_globals_nb = { + .notifier_call = reboot_boot_globals, + .priority = 0, /* do boot globals last */ +}; + +static void install_reboot_notifier(void) +{ + register_reboot_notifier(&reboot_boot_globals_nb); +} + +static int check_boot_globals(void) +{ + u32 computed_residue, checksum; + + if ( !boot_globals ) { + printk("boot globals: W boot globals not allocated\n"); + return 0; /* failed because bootglobals not allocated */ + } + + if ( BOOT_GLOBALS_WARM_FLAG != get_warm_restart_flag() ) { + printk("boot globals: I warm restart flag not set (0x%08lX)\n", get_warm_restart_flag()); + return 0; /* failed because we did not restart warmly */ + } + + checksum = boot_globals->checksum; + + computed_residue = ~bg_crc32((u8 *)boot_globals, BOOT_GLOBALS_SIZE); + + printk("boot globals: I computed checksum = 0x%08X, checksum = 0x%08X\n", computed_residue, checksum); + + if ( CRC32_RESIDUE != computed_residue ) + { + printk("boot globals: I failed checksum = 0x%08lX\n", boot_globals->checksum); + return 0; + } + + printk("boot globals: I passed\n"); + return 1; +} + +static void save_boot_globals(void) +{ + if ( boot_globals ) { + boot_globals->checksum = bg_crc32((u8 *)boot_globals, BOOT_GLOBALS_SIZE - sizeof (u32)); + } +} + +boot_globals_t *get_boot_globals(void) +{ + return boot_globals; +} + +void configure_boot_globals(void) +{ + static boot_globals_t bg; + + if (boot_globals_start != 0) { + boot_globals=__arm_ioremap(boot_globals_start, BOOT_GLOBALS_SIZE, 0); + } + + if(boot_globals) { + printk("boot globals: I reserved %lu bytes at 0x%08lX\n", BOOT_GLOBALS_SIZE, boot_globals_start); + } else { + printk("boot globals: W could not reserve them, faking it\n"); + boot_globals = &bg; + } + + /* sanity check the position of elements in the boot globals structure */ + if (offsetof(bg_in_use_t, kernel_boot_flag) != 0x410) { + printk("boot globals: E offset of kernel_boot_flag is wrong!! is: %#x should be: %#x\n", offsetof(bg_in_use_t, kernel_boot_flag), 0x410); + } + + if(!check_boot_globals()) { + unsigned long kernel_boot_flag_tmp; + + printk("boot globals: I invalid, clearing\n"); + + /* preserve the boot_flag even in a cold start case */ + kernel_boot_flag_tmp=get_kernel_boot_flag(); + + memset(boot_globals, 0, BOOT_GLOBALS_SIZE); + + /* preserve the boot_flag even in a cold start case */ + set_kernel_boot_flag(kernel_boot_flag_tmp); + + // Flag that we booted dirty (or just cold). + // + set_dirty_boot_flag(1); + } else { + + // Flag that we didn't boot dirty (warm). + // + set_dirty_boot_flag(0); + } + + if(get_kernel_boot_flag()==0) { + printk("boot globals: E kernel_boot_flag cannot be 0 on start up!\n"); + } + + // We're not warm until we've rebooted again cleanly, which our reboot notifier + // callback will say. + // + set_warm_restart_flag(BOOT_GLOBALS_COLD_FLAG); + install_reboot_notifier(); +} + +static int proc_flag_read (char *page, char **start, off_t off, int count, + int *eof, void *data) +{ + const struct flag_cb *p = data; + + *eof=1; + if(p && p->flag_get) { + return snprintf(page, PAGE_SIZE, "%lu\n", p->flag_get()); + } else { + return -EIO; + } +} + +static int proc_flag_write (struct file *file, const char __user *buffer, + unsigned long count, void *data) +{ + const struct flag_cb *p = data; + char buf[128]; + + if (count > sizeof(buf) - 1) + return -EINVAL; + if(!count) + return 0; + if (copy_from_user(buf, buffer, count)) + return -EFAULT; + buf[count] = '\0'; + + /* printk("proc_flag_write:%p:%s\n", data, buf); */ + if(p && p->flag_set) { + unsigned long i; + for(i=0;iflag_set(1); + return count; + } + } + /* was all zeros - clear the flag */ + /* printk("proc_flag_write:clearing\n"); */ + p->flag_set(0); + return count; + } else { + return -EIO; + } +} + +int __init boot_globals_init(void) +{ + unsigned i; + struct proc_dir_entry *dir; + void configure_boot_globals(void); + + configure_boot_globals(); + + dir=proc_mkdir("bootglobals", NULL); + if(!dir) { + printk(KERN_WARNING "could not create /proc/%s\n", "bootglobals"); + return 0; + } + + for(i=0;i<(sizeof flag_proc/sizeof *flag_proc);i++) { + struct proc_dir_entry *tmp; + mode_t mode; + + mode=0; + if(flag_proc[i].flag_get) { + mode|=S_IRUGO; + } + if(flag_proc[i].flag_set) { + mode|=S_IWUGO; + } + + tmp=create_proc_entry(flag_proc[i].path, mode, dir); + if (tmp) { + tmp->data = (void*)&flag_proc[i]; + tmp->read_proc = proc_flag_read; + tmp->write_proc = proc_flag_write; + } else { + printk(KERN_WARNING "boot globals: W could not create /proc/%s/%s\n", "bootglobals", flag_proc[i].path); + } + } + boot_milestone_write("Bg00", 4); + return 1; +} +late_initcall(boot_globals_init); + +// warm_restart_flag + +void set_warm_restart_flag(unsigned long warm_restart_flag) +{ + printk("boot globals: I setting warm restart to 0x%08lX\n", warm_restart_flag); + get_boot_globals()->globals.warm_restart_flag = warm_restart_flag; + save_boot_globals(); +} + +unsigned long get_warm_restart_flag(void) +{ + return get_boot_globals()->globals.warm_restart_flag; +} + +// kernel_boot_flag + +void set_kernel_boot_flag(unsigned long kernel_boot_flag) +{ + printk("boot globals: I setting kernel_boot_flag = %ld\n", kernel_boot_flag); + get_boot_globals()->globals.kernel_boot_flag = kernel_boot_flag; +} + +unsigned long get_kernel_boot_flag(void) +{ + /* printk("boot globals: I reading kernel_boot_flag = %ld\n", get_boot_globals()->globals.kernel_boot_flag); */ + return get_boot_globals()->globals.kernel_boot_flag; +} + +// apollo_init_display_flag + +void set_apollo_init_display_flag(unsigned long apollo_init_display_flag) +{ + get_boot_globals()->globals.apollo_init_display_flag = apollo_init_display_flag; +} + +unsigned long get_apollo_init_display_flag(void) +{ + return get_boot_globals()->globals.apollo_init_display_flag; +} + +EXPORT_SYMBOL(set_apollo_init_display_flag); +EXPORT_SYMBOL(get_apollo_init_display_flag); + +// dirty_boot_flag + +void set_dirty_boot_flag(unsigned char dirty_boot_flag) +{ + get_boot_globals()->globals.dirty_boot_flag = dirty_boot_flag; +} + +unsigned long get_dirty_boot_flag(void) +{ + return get_boot_globals()->globals.dirty_boot_flag; +} + +// progress_bar_value + +void set_progress_bar_value(int progress_bar_value) +{ + get_boot_globals()->globals.progress_bar_value = progress_bar_value; +} + +int get_progress_bar_value(void) +{ + return get_boot_globals()->globals.progress_bar_value; +} + +EXPORT_SYMBOL(set_progress_bar_value); +EXPORT_SYMBOL(get_progress_bar_value); + +// user_boot_screen + +void set_user_boot_screen(int user_boot_screen) +{ + get_boot_globals()->globals.user_boot_screen = user_boot_screen; +} + +int get_user_boot_screen(void) +{ + return get_boot_globals()->globals.user_boot_screen; +} + +EXPORT_SYMBOL(set_user_boot_screen); +EXPORT_SYMBOL(get_user_boot_screen); + +// update_flag + +void set_update_flag(unsigned long update_flag) +{ + get_boot_globals()->globals.update_flag = update_flag; +} + +unsigned long get_update_flag(void) +{ + return get_boot_globals()->globals.update_flag; +} + +// update_data + +void set_update_data(unsigned long update_data) +{ + get_boot_globals()->globals.update_data = update_data; +} + +unsigned long get_update_data(void) +{ + return get_boot_globals()->globals.update_data; +} + +// scratch + +void set_scratch(char *scratch) +{ + if ( scratch && (SCRATCH_SIZE >= strlen(scratch)) ) + strcpy(get_boot_globals()->globals.scratch, scratch); +} + +char *get_scratch(void) +{ + return get_boot_globals()->globals.scratch; +} + +// panel_id + +void set_panel_id(panel_id_t *panel_id) +{ + if ( panel_id ) + memcpy(&get_boot_globals()->globals.panel_id, panel_id, sizeof(panel_id_t)); +} + +panel_id_t *get_panel_id(void) +{ + return &get_boot_globals()->globals.panel_id; +} + +EXPORT_SYMBOL(get_panel_id); + +void clear_panel_id(void) +{ + memset(&get_boot_globals()->globals.panel_id, 0, sizeof(panel_id_t)); +} + +void set_panel_size(unsigned char size) +{ + panel_id_t *panel_id = get_panel_id(); + panel_id->size = size; +} + +unsigned char get_panel_size(void) +{ + panel_id_t *panel_id = get_panel_id(); + return ( panel_id->size ); +} + +// async/sync_settings + +void set_async_settings(sync_async_t *async_settings) +{ + if ( async_settings ) + memcpy(&get_boot_globals()->globals.async_settings, async_settings, sizeof(sync_async_t)); +} + +sync_async_t *get_async_settings(void) +{ + return &get_boot_globals()->globals.async_settings; +} + +void set_sync_settings(sync_async_t *sync_settings) +{ + if ( sync_settings ) + memcpy(&get_boot_globals()->globals.sync_settings, sync_settings, sizeof(sync_async_t)); +} + +sync_async_t *get_sync_settings(void) +{ + return &get_boot_globals()->globals.sync_settings; +} + +void clear_async_sync_settings(void) +{ + memset(&get_boot_globals()->globals.async_settings, 0, sizeof(sync_async_t)); + memset(&get_boot_globals()->globals.sync_settings, 0, sizeof(sync_async_t)); +} + +// clear_dbs + +void set_clear_dbs(int clear_dbs) +{ + get_boot_globals()->globals.clear_dbs = clear_dbs; +} + +int get_clear_dbs(void) +{ + return get_boot_globals()->globals.clear_dbs; +} + +// framebuffer_start + +void set_framebuffer_start(unsigned long framebuffer_start) +{ + get_boot_globals()->globals.framebuffer_start = framebuffer_start; +} + +unsigned long get_framebuffer_start(void) +{ + return get_boot_globals()->globals.framebuffer_start; +} + +EXPORT_SYMBOL(get_framebuffer_start); + +// drivemode_screen_ready + +void set_drivemode_screen_ready(int drivemode_screen_ready) +{ + get_boot_globals()->globals.drivemode_screen_ready = drivemode_screen_ready; +} + +int get_drivemode_screen_ready(void) +{ + return get_boot_globals()->globals.drivemode_screen_ready; +} + +EXPORT_SYMBOL(set_drivemode_screen_ready); +EXPORT_SYMBOL(get_drivemode_screen_ready); + +// hw_flags + +void set_hw_flags(hw_flags_t *hw_flags) +{ + if ( hw_flags ) + memcpy(&get_boot_globals()->globals.hw_flags, hw_flags, sizeof(hw_flags_t)); +} + +hw_flags_t *get_hw_flags(void) +{ + return &get_boot_globals()->globals.hw_flags; +} + +EXPORT_SYMBOL(get_hw_flags); + +// framework_started, framework_running + +void set_framework_started(int framework_started) +{ + get_boot_globals()->globals.framework_started = framework_started; +} + +int get_framework_started(void) +{ + return get_boot_globals()->globals.framework_started; +} + +void set_framework_running(int framework_running) +{ + get_boot_globals()->globals.framework_running = framework_running; +} + +int get_framework_running(void) +{ + return get_boot_globals()->globals.framework_running; +} + +void set_framework_stopped(int framework_stopped) +{ + get_boot_globals()->globals.framework_stopped = framework_stopped; +} + +int get_framework_stopped(void) +{ + return get_boot_globals()->globals.framework_stopped; +} + +EXPORT_SYMBOL(set_framework_started); +EXPORT_SYMBOL(get_framework_started); +EXPORT_SYMBOL(set_framework_running); +EXPORT_SYMBOL(get_framework_running); +EXPORT_SYMBOL(set_framework_stopped); +EXPORT_SYMBOL(get_framework_stopped); + +// screen_clear + +void set_screen_clear(int screen_clear) +{ + get_boot_globals()->globals.screen_clear = screen_clear; +} + +int get_screen_clear(void) +{ + return get_boot_globals()->globals.screen_clear; +} + +EXPORT_SYMBOL(set_screen_clear); +EXPORT_SYMBOL(get_screen_clear); + +// battery_watermarks + +void set_battery_watermarks(bat_level_t *battery_watermarks) +{ + if ( battery_watermarks ) + memcpy(&get_boot_globals()->globals.battery_watermarks, battery_watermarks, sizeof(bat_level_t)); +} + +bat_level_t *get_battery_watermarks(void) +{ + return &get_boot_globals()->globals.battery_watermarks; +} + +// dev_mode + +void set_dev_mode(int dev_mode) +{ + get_boot_globals()->globals.dev_mode = dev_mode; +} + +int get_dev_mode(void) +{ + return get_boot_globals()->globals.dev_mode; +} + +// env_script + +void set_env_script(char *env_script) +{ + if ( env_script && (ENV_SCRIPT_SIZE >= strlen(env_script)) ) + strcpy(get_boot_globals()->globals.env_script, env_script); +} + +char *get_env_script(void) +{ + return get_boot_globals()->globals.env_script; +} + +// fb_ioctl + +void set_fb_ioctl(sys_ioctl_t fb_ioctl) +{ + get_boot_globals()->globals.fb_ioctl = fb_ioctl; +} + +sys_ioctl_t get_fb_ioctl(void) +{ + return get_boot_globals()->globals.fb_ioctl; +} + +EXPORT_SYMBOL(set_fb_ioctl); +EXPORT_SYMBOL(get_fb_ioctl); + +// fb_init_flag + +void set_fb_init_flag(unsigned long fb_init_flag) +{ + get_boot_globals()->globals.fb_init_flag = fb_init_flag; +} + +unsigned long get_fb_init_flag(void) +{ + return get_boot_globals()->globals.fb_init_flag; +} + +EXPORT_SYMBOL(set_fb_init_flag); +EXPORT_SYMBOL(get_fb_init_flag); + +// op_amp_offset, update_op_amp_offset_env + +void set_update_op_amp_offset_env(int update_op_amp_offset_env) +{ + get_boot_globals()->globals.update_op_amp_offset_env = update_op_amp_offset_env; +} + +int get_update_op_amp_offset_env(void) +{ + return get_boot_globals()->globals.update_op_amp_offset_env; +} + +void set_op_amp_offset(int op_amp_offset) +{ + get_boot_globals()->globals.op_amp_offset = op_amp_offset; +} + +int get_op_amp_offset(void) +{ + return get_boot_globals()->globals.op_amp_offset; +} + +// rve_value + +void set_rve_value(unsigned long rve_value) +{ + get_boot_globals()->globals.rve_value = rve_value; +} + +unsigned long get_rve_value(void) +{ + return get_boot_globals()->globals.rve_value; +} + +// gain_value + +void set_gain_value(unsigned long gain_value) +{ + get_boot_globals()->globals.gain_value = gain_value; +} + +unsigned long get_gain_value(void) +{ + return get_boot_globals()->globals.gain_value; +} + +// pnlcd_flags + +void set_pnlcd_flags(pnlcd_flags_t *pnlcd_flags) +{ + if ( pnlcd_flags ) + memcpy(&get_boot_globals()->globals.pnlcd_flags, pnlcd_flags, sizeof(pnlcd_flags_t)); +} + +pnlcd_flags_t *get_pnlcd_flags(void) +{ + return &get_boot_globals()->globals.pnlcd_flags; +} + +int inc_pnlcd_event_count(void) +{ + return ++get_pnlcd_flags()->event_count; +} + +int dec_pnlcd_event_count(void) +{ + int event_count = --get_pnlcd_flags()->event_count; + + if ( event_count < 0 ) + get_pnlcd_flags()->event_count = 0; + + return get_pnlcd_flags()->event_count; +} + +EXPORT_SYMBOL(set_pnlcd_flags); +EXPORT_SYMBOL(get_pnlcd_flags); + +EXPORT_SYMBOL(inc_pnlcd_event_count); +EXPORT_SYMBOL(dec_pnlcd_event_count); + +// pnlcd_ioctl + +void set_pnlcd_ioctl(sys_ioctl_t pnlcd_ioctl) +{ + get_boot_globals()->globals.pnlcd_ioctl = pnlcd_ioctl; +} + +sys_ioctl_t get_pnlcd_ioctl(void) +{ + return get_boot_globals()->globals.pnlcd_ioctl; +} + +EXPORT_SYMBOL(set_pnlcd_ioctl); +EXPORT_SYMBOL(get_pnlcd_ioctl); + +// mw_flags + +void set_mw_flags(mw_flags_t *mw_flags) +{ + if ( mw_flags ) + memcpy(&get_boot_globals()->globals.mw_flags, mw_flags, sizeof(mw_flags_t)); +} + +mw_flags_t *get_mw_flags(void) +{ + return &get_boot_globals()->globals.mw_flags; +} + +// rcs_flags + +void set_rcs_flags(rcs_flags_t *rcs_flags) +{ + if ( rcs_flags ) + memcpy(&get_boot_globals()->globals.rcs_flags, rcs_flags, sizeof(rcs_flags_t)); +} + +rcs_flags_t *get_rcs_flags(void) +{ + return &get_boot_globals()->globals.rcs_flags; +} + +// fb_apply_fx + +void set_fb_apply_fx(fb_apply_fx_t fb_apply_fx) +{ + get_boot_globals()->globals.fb_apply_fx = fb_apply_fx; +} + +fb_apply_fx_t get_fb_apply_fx(void) +{ + return get_boot_globals()->globals.fb_apply_fx; +} + +EXPORT_SYMBOL(set_fb_apply_fx); +EXPORT_SYMBOL(get_fb_apply_fx); + +// drivemode_online + +void set_drivemode_online(int drivemode_online) +{ + get_boot_globals()->globals.drivemode_online = drivemode_online; +} + +int get_drivemode_online(void) +{ + return get_boot_globals()->globals.drivemode_online; +} + +EXPORT_SYMBOL(set_drivemode_online); +EXPORT_SYMBOL(get_drivemode_online); + +int boot_milestone_to_str(unsigned int bom_idx, char *str) +{ + const struct boot_milestone *bom_start, *bom; + uint32_t start_jiff, jiff; + unsigned int msecs; + + bom_start = &get_boot_globals()->globals.boot_milestones[0]; + bom = bom_start + bom_idx; + start_jiff = INITIAL_JIFFIES; + jiff = bom->jiff - start_jiff; + if (jiff >= 0x20000000) { + /* We assume that it doesn't take more than 1000 hours to + * boot. This allows us to handle the case where jiffies wraps + * around. */ + jiff = 1 + (MAX_JIFFY_OFFSET - start_jiff) + bom->jiff; + } + if (bom_idx > MAX_BOOT_MILESTONES) { + return scnprintf(str, BOOT_MILESTONE_TO_STR_SZ, "invalid"); + } + msecs = jiffies_to_msecs(jiff); + return scnprintf(str, BOOT_MILESTONE_TO_STR_SZ, "%c%c%c%c %u\n", + bom->name[0], bom->name[1], bom->name[2], bom->name[3], + msecs); +} diff -urN linux-2.6.26/arch/arm/mach-mx35/bootdata.c linux-2.6.26-lab126/arch/arm/mach-mx35/bootdata.c --- linux-2.6.26/arch/arm/mach-mx35/bootdata.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/bootdata.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,809 @@ +/* + * bootdata.c + * + * Copyright (C) 2006-2010 Amazon Technologies + * + */ + +#include +#include +#include +#include +#include +#include + +// Templates for reading/writing numeric boot-global data. +// +typedef unsigned long (*get_boot_data_t)(void); +typedef void (*set_boot_data_t)(unsigned long boot_data); + +#define PROC_GET_BOOT_DATA(f) return proc_get_boot_data(page, start, off, count, eof, data, (get_boot_data_t)f) +#define PROC_SET_BOOT_DATA(f) return proc_set_boot_data(file, buf, count, data, (set_boot_data_t)f) + +static int +proc_get_boot_data( + char *page, + char **start, + off_t off, + int count, + int *eof, + void *data, + get_boot_data_t get_boot_data) +{ + int len = sprintf(page, "%08X\n", (unsigned int)(*get_boot_data)()); + + *eof = 1; + + return len; +} + +static int +proc_set_boot_data( + struct file *file, + const char __user *buf, + unsigned long count, + void *data, + set_boot_data_t set_boot_data) +{ + char lbuf[16]; + + memset(lbuf, 0, 16); + + if (copy_from_user(lbuf, buf, 8)) { + return -EFAULT; + } + + (*set_boot_data)(simple_strtol(lbuf, NULL, 16)); + + return count; +} + +// read/write update_flag +// +static int +proc_update_flag_read( + char *page, + char **start, + off_t off, + int count, + int *eof, + void *data) +{ + PROC_GET_BOOT_DATA(get_update_flag); +} + +static int +proc_update_flag_write( + struct file *file, + const char __user *buf, + unsigned long count, + void *data) +{ + PROC_SET_BOOT_DATA(set_update_flag); +} + +// read/write update_data +// +static int +proc_update_data_read( + char *page, + char **start, + off_t off, + int count, + int *eof, + void *data) +{ + PROC_GET_BOOT_DATA(get_update_data); +} + +static int +proc_update_data_write( + struct file *file, + const char __user *buf, + unsigned long count, + void *data) +{ + PROC_SET_BOOT_DATA(set_update_data); +} + +// read/write drivemode_screen_ready +// +static int +proc_drivemode_screen_ready_read( + char *page, + char **start, + off_t off, + int count, + int *eof, + void *data) +{ + PROC_GET_BOOT_DATA(get_drivemode_screen_ready); +} + +static int +proc_drivemode_screen_ready_write( + struct file *file, + const char __user *buf, + unsigned long count, + void *data) +{ + PROC_SET_BOOT_DATA(set_drivemode_screen_ready); +} + +// read/write framework_started, framework_running, framework_stopped +// +static int +proc_framework_started_read( + char *page, + char **start, + off_t off, + int count, + int *eof, + void *data) +{ + PROC_GET_BOOT_DATA(get_framework_started); +} + +static int +proc_framework_started_write( + struct file *file, + const char __user *buf, + unsigned long count, + void *data) +{ + PROC_SET_BOOT_DATA(set_framework_started); +} + +static int +proc_framework_running_read( + char *page, + char **start, + off_t off, + int count, + int *eof, + void *data) +{ + PROC_GET_BOOT_DATA(get_framework_running); +} + +static int +proc_framework_running_write( + struct file *file, + const char __user *buf, + unsigned long count, + void *data) +{ + PROC_SET_BOOT_DATA(set_framework_running); +} + +static int +proc_framework_stopped_read( + char *page, + char **start, + off_t off, + int count, + int *eof, + void *data) +{ + PROC_GET_BOOT_DATA(get_framework_stopped); +} + +static int +proc_framework_stopped_write( + struct file *file, + const char __user *buf, + unsigned long count, + void *data) +{ + PROC_SET_BOOT_DATA(set_framework_stopped); +} + +// read/write env_script +// +static int +proc_env_script_read( + char *page, + char **start, + off_t off, + int count, + int *eof, + void *data) +{ + int len = sprintf(page, "%s", get_env_script()); + + *eof = 1; + + return len; +} + +static int +proc_env_script_write( + struct file *file, + const char __user *buf, + unsigned long count, + void *data) +{ + char lbuf[ENV_SCRIPT_SIZE]; + + if (count > ENV_SCRIPT_SIZE) { + return -EINVAL; + } + + memset(lbuf, 0, count); + + if (copy_from_user(lbuf, buf, count)) { + return -EFAULT; + } + + lbuf[count] = '\0'; + set_env_script(lbuf); + + return count; +} + +// read/write dirty_boot_flag +// +static int +proc_dirty_boot_read( + char *page, + char **start, + off_t off, + int count, + int *eof, + void *data) +{ + PROC_GET_BOOT_DATA(get_dirty_boot_flag); +} + +static int +proc_dirty_boot_write( + struct file *file, + const char __user *buf, + unsigned long count, + void *data) +{ + PROC_SET_BOOT_DATA(set_dirty_boot_flag); +} + +// read calibration_info +// +static int +proc_calibration_read( + char *page, + char **start, + off_t off, + int count, + int *eof, + void *data) +{ + int len = sprintf(page, "%d, %ld, %ld\n", get_op_amp_offset(), get_gain_value(), get_rve_value()); + + *eof = 1; + + return len; +} + +// read/write panel_size +// +static int +proc_panel_size_read( + char *page, + char **start, + off_t off, + int count, + int *eof, + void *data) +{ + PROC_GET_BOOT_DATA(get_panel_size); +} + +static int +proc_panel_size_write( + struct file *file, + const char __user *buf, + unsigned long count, + void *data) +{ + PROC_SET_BOOT_DATA(set_panel_size); +} + +// read panel params +// +static char * +get_panel_params( + void) +{ + char *result = NULL; + + switch ( get_panel_size() ) + { + case PANEL_ID_6_0_INCH_SIZE: + default: + result = PANEL_ID_6_0_INCH_PARAMS; + break; + + case PANEL_ID_9_7_INCH_SIZE: + result = PANEL_ID_9_7_INCH_PARAMS; + break; + } + + return ( result ); +} + +static int +proc_panel_params_read( + char *page, + char **start, + off_t off, + int count, + int *eof, + void *data) +{ + int len = sprintf(page, "%s\n", get_panel_params()); + + *eof = 1; + + return len; +} + +// read/write mw_flags +// +static int +proc_mw_flags_read( + char *page, + char **start, + off_t off, + int count, + int *eof, + void *data) +{ + unsigned long raw_mw_flags = *(unsigned long *)get_mw_flags(); + int len = sprintf(page, "%08lX\n", raw_mw_flags); + + *eof = 1; + + return len; +} + +static int +proc_mw_flags_write( + struct file *file, + const char __user *buf, + unsigned long count, + void *data) +{ + unsigned long raw_mw_flags; + mw_flags_t mw_flags; + char lbuf[16]; + + memset(lbuf, 0, 16); + + if (copy_from_user(lbuf, buf, 8)) { + return -EFAULT; + } + + raw_mw_flags = (unsigned long)simple_strtol(lbuf, NULL, 0); + memcpy(&mw_flags, &raw_mw_flags, sizeof(mw_flags_t)); + + set_mw_flags(&mw_flags); + + return count; +} + +// read/write rcs_flags +// +static int +proc_rcs_flags_read( + char *page, + char **start, + off_t off, + int count, + int *eof, + void *data) +{ + unsigned long raw_rcs_flags = *(unsigned long *)get_rcs_flags(); + int len = sprintf(page, "%08lX\n", raw_rcs_flags); + + *eof = 1; + + return len; +} + +static int +proc_rcs_flags_write( + struct file *file, + const char __user *buf, + unsigned long count, + void *data) +{ + unsigned long raw_rcs_flags; + rcs_flags_t rcs_flags; + char lbuf[16]; + + memset(lbuf, 0, 16); + + if (copy_from_user(lbuf, buf, 8)) { + return -EFAULT; + } + + raw_rcs_flags = (unsigned long)simple_strtol(lbuf, NULL, 0); + memcpy(&rcs_flags, &raw_rcs_flags, sizeof(rcs_flags_t)); + + set_rcs_flags(&rcs_flags); + + return count; +} + +// read/write progress_count +// +static int +proc_progress_count_read( + char *page, + char **start, + off_t off, + int count, + int *eof, + void *data) +{ + PROC_GET_BOOT_DATA(get_progress_bar_value); +} + +static int +proc_progress_count_write( + struct file *file, + const char __user *buf, + unsigned long count, + void *data) +{ + PROC_SET_BOOT_DATA(set_progress_bar_value); +} + +/* Current number of boot milestones. This starts initialized to 0 */ +static unsigned int num_boot_milestones; + +static rwlock_t boot_milestone_lock; + +/** Read the boot milestones. + * + * Reading this file will return garbage after the system has been up for about + * 1000 hours or so, due to the use of the 32-bit jiffies counter. Since this + * mechanism is intended to measure boot time, this is acceptable. This could be + * resolved by using the 64-bit jiffies counter instead. + * + * @param buf (out param) the buffer to put the boot milestones into. + * Must have at least PAGE_SIZE bytes. + * + * @return Total number of bytes read, or a negative error code. + */ +static int boot_milestone_read(char *buf) +{ + char *b; + unsigned int i; + int total_read; + + /* We assume that we can fit all of our output into a single page. If + * that turns out not to be true, this has to be rewritten in a more + * complex way. + */ + BUILD_BUG_ON(BOOT_MILESTONE_TO_STR_SZ * MAX_BOOT_MILESTONES > PAGE_SIZE); + + read_lock(&boot_milestone_lock); + if (num_boot_milestones > MAX_BOOT_MILESTONES) { + printk("error: too many boot milestones!\n"); + read_unlock(&boot_milestone_lock); + return -EINVAL; + } + total_read = 0; + for (i = 0, b = buf; i < num_boot_milestones; i++) { + int res; + res = boot_milestone_to_str(i, b); + b += res; + total_read += res; + } + read_unlock(&boot_milestone_lock); + return total_read; +} + +int boot_milestone_write(const char *name, unsigned long name_len) +{ + struct boot_milestone *bom; + unsigned int ret, i; + + write_lock(&boot_milestone_lock); + if (name_len != BOOT_MILESTONE_NAME_SZ) { + printk(KERN_WARNING " W : milestone name must be exactly " + "%d alphanumeric bytes, not %ld\n", + BOOT_MILESTONE_NAME_SZ, name_len); + ret = -EINVAL; + goto done; + } + for (i = 0; i < BOOT_MILESTONE_NAME_SZ; i++) { + if (! isalnum(name[i])) { + printk(KERN_WARNING " W : won't accept " + "non-alphanumeric milestone name " + "0x%02x%02x%02x%02x\n", + name[0], name[1], name[2], name[3]); + ret = -EINVAL; + goto done; + } + } + if (! memcmp(name, "clrm", BOOT_MILESTONE_NAME_SZ)) { + printk(KERN_NOTICE "clrm: cleared all boot milestones.\n"); + num_boot_milestones = 0; + ret = 0; + goto done; + } + if (num_boot_milestones >= MAX_BOOT_MILESTONES) { + printk(KERN_WARNING " W : can't add another boot milestone. " + "We already have %d boot milestones, and the maximum " + "is %d\n", num_boot_milestones, MAX_BOOT_MILESTONES); + ret = -EINVAL; + goto done; + } + bom = get_boot_globals()->globals.boot_milestones + num_boot_milestones; + num_boot_milestones++; + memcpy(bom->name, name, BOOT_MILESTONE_NAME_SZ); + bom->jiff = jiffies; + ret = 0; + +done: + write_unlock(&boot_milestone_lock); + return ret; +} + +// read/write boot milestones +// +static int +proc_boot_milestone_read(char *page, char **start, + off_t off, int count, int *eof, void *data) +{ + return boot_milestone_read(page); +} + +static int +proc_boot_milestone_write(struct file *file, const char __user *buf, + unsigned long count, void *data) +{ + int ret; + ret = boot_milestone_write(buf, count); + return ret ? ret : BOOT_MILESTONE_NAME_SZ; +} + +// Entry/Exit +// +#define BD_PROC_MODE_PARENT (S_IFDIR | S_IRUGO | S_IXUGO) +#define BD_PROC_MODE_CHILD_RW (S_IWUGO | S_IRUGO) +#define BD_PROC_MODE_CHILD_R (S_IRUGO) + +#define BD_PROC_PARENT "bd" +#define BD_PROC_UPDATE_FLAG "update_flag" +#define BD_PROC_UPDATE_DATA "update_data" +#define BD_PROC_DRIVEMODE "drivemode_screen_ready" +#define BD_PROC_FRAMEWORK1 "framework_started" +#define BD_PROC_FRAMEWORK2 "framework_running" +#define BD_PROC_FRAMEWORK3 "framework_stopped" +#define BD_PROC_ENV_SCRIPT "env_script" +#define BD_PROC_DIRTY_BOOT "dirty_boot_flag" +#define BD_PROC_CALIBRATION "calibration_info" +#define BD_PROC_PANEL_SIZE "panel_size" +#define BD_PROC_PANEL_PARAMS "panel_params" +#define BD_PROC_MW_FLAGS "mw_flags" +#define BD_PROC_RCS_FLAGS "rcs_flags" +#define BD_PROC_PROGRESS_COUNT "progress_count" +#define BD_PROC_BOOT_MILESTONE "boot_milestone" + +static struct proc_dir_entry *proc_bd_parent = NULL; +static struct proc_dir_entry *proc_update_flag = NULL; +static struct proc_dir_entry *proc_update_data = NULL; +static struct proc_dir_entry *proc_drivemode = NULL; +static struct proc_dir_entry *proc_framework1 = NULL; +static struct proc_dir_entry *proc_framework2 = NULL; +static struct proc_dir_entry *proc_framework3 = NULL; +static struct proc_dir_entry *proc_env_script = NULL; +static struct proc_dir_entry *proc_dirty_boot = NULL; +static struct proc_dir_entry *proc_calibration = NULL; +static struct proc_dir_entry *proc_panel_size = NULL; +static struct proc_dir_entry *proc_panel_params = NULL; +static struct proc_dir_entry *proc_mw_flags = NULL; +static struct proc_dir_entry *proc_rcs_flags = NULL; +static struct proc_dir_entry *proc_progress_count = NULL; +static struct proc_dir_entry *proc_boot_milestone = NULL; + +static struct proc_dir_entry *create_bd_proc_entry(const char *name, mode_t mode, struct proc_dir_entry *parent, + read_proc_t *read_proc, write_proc_t *write_proc) +{ + struct proc_dir_entry *bd_proc_entry = create_proc_entry(name, mode, parent); + + if (bd_proc_entry) { + bd_proc_entry->owner = THIS_MODULE; + bd_proc_entry->data = NULL; + bd_proc_entry->read_proc = read_proc; + bd_proc_entry->write_proc = write_proc; + } + + return bd_proc_entry; +} + +#define remove_bd_proc_entry(name, entry, parent) \ + do \ + if ( entry ) \ + { \ + remove_proc_entry(name, parent); \ + entry = NULL; \ + } \ + while ( 0 ) + +static void +bootdata_cleanup( + void) +{ + if ( proc_bd_parent ) + { + remove_bd_proc_entry(BD_PROC_UPDATE_FLAG, proc_update_flag, proc_bd_parent); + remove_bd_proc_entry(BD_PROC_UPDATE_DATA, proc_update_data, proc_bd_parent); + remove_bd_proc_entry(BD_PROC_DRIVEMODE, proc_drivemode, proc_bd_parent); + remove_bd_proc_entry(BD_PROC_FRAMEWORK1, proc_framework1, proc_bd_parent); + remove_bd_proc_entry(BD_PROC_FRAMEWORK2, proc_framework2, proc_bd_parent); + remove_bd_proc_entry(BD_PROC_FRAMEWORK3, proc_framework3, proc_bd_parent); + remove_bd_proc_entry(BD_PROC_ENV_SCRIPT, proc_env_script, proc_bd_parent); + remove_bd_proc_entry(BD_PROC_DIRTY_BOOT, proc_dirty_boot, proc_bd_parent); + remove_bd_proc_entry(BD_PROC_CALIBRATION, proc_calibration, proc_bd_parent); + remove_bd_proc_entry(BD_PROC_PANEL_SIZE, proc_panel_size, proc_bd_parent); + remove_bd_proc_entry(BD_PROC_PANEL_PARAMS, proc_panel_params, proc_bd_parent); + remove_bd_proc_entry(BD_PROC_MW_FLAGS, proc_mw_flags, proc_bd_parent); + remove_bd_proc_entry(BD_PROC_RCS_FLAGS, proc_rcs_flags, proc_bd_parent); + remove_bd_proc_entry(BD_PROC_PROGRESS_COUNT, proc_progress_count, proc_bd_parent); + remove_bd_proc_entry(BD_PROC_BOOT_MILESTONE, proc_boot_milestone, proc_bd_parent); + remove_bd_proc_entry(BD_PROC_PARENT, proc_bd_parent, NULL); + } +} + +static int __init +bootdata_init( + void) +{ + int result = -ENOMEM; + + // Parent: /proc/bd. + // + proc_bd_parent = create_proc_entry(BD_PROC_PARENT, BD_PROC_MODE_PARENT, NULL); + + if (proc_bd_parent) + { + int null_check = -1; + + // Child: /proc/bd/update_flag. + // + proc_update_flag = create_bd_proc_entry(BD_PROC_UPDATE_FLAG, BD_PROC_MODE_CHILD_RW, proc_bd_parent, + proc_update_flag_read, proc_update_flag_write); + + null_check &= (int)proc_update_flag; + + // Child: /proc/bd/update_data. + // + proc_update_data = create_bd_proc_entry(BD_PROC_UPDATE_DATA, BD_PROC_MODE_CHILD_RW, proc_bd_parent, + proc_update_data_read, proc_update_data_write); + + null_check &= (int)proc_update_data; + + // Child: /proc/bd/drivemode_screen_ready. + // + proc_drivemode = create_bd_proc_entry(BD_PROC_DRIVEMODE, BD_PROC_MODE_CHILD_RW, proc_bd_parent, + proc_drivemode_screen_ready_read, proc_drivemode_screen_ready_write); + + null_check &= (int)proc_drivemode; + + // Child: /proc/bd/framework_started. + // + proc_framework1 = create_bd_proc_entry(BD_PROC_FRAMEWORK1, BD_PROC_MODE_CHILD_RW, proc_bd_parent, + proc_framework_started_read, proc_framework_started_write); + + null_check &= (int)proc_framework1; + + // Child: /proc/bd/framework_running. + // + proc_framework2 = create_bd_proc_entry(BD_PROC_FRAMEWORK2, BD_PROC_MODE_CHILD_RW, proc_bd_parent, + proc_framework_running_read, proc_framework_running_write); + + null_check &= (int)proc_framework2; + + // Child: /proc/bd/framework_stopped. + // + proc_framework3 = create_bd_proc_entry(BD_PROC_FRAMEWORK3, BD_PROC_MODE_CHILD_RW, proc_bd_parent, + proc_framework_stopped_read, proc_framework_stopped_write); + + null_check &= (int)proc_framework3; + + // Child: /proc/bd/env_script. + // + proc_env_script = create_bd_proc_entry(BD_PROC_ENV_SCRIPT, BD_PROC_MODE_CHILD_RW, proc_bd_parent, + proc_env_script_read, proc_env_script_write); + + null_check &= (int)proc_env_script; + + // Child: /proc/bd/dirty_boot_flag. + // + proc_dirty_boot = create_bd_proc_entry(BD_PROC_DIRTY_BOOT, BD_PROC_MODE_CHILD_RW, proc_bd_parent, + proc_dirty_boot_read, proc_dirty_boot_write); + + null_check &= (int)proc_dirty_boot; + + // Child: /proc/bd/calibration_info. + // + proc_calibration = create_bd_proc_entry(BD_PROC_CALIBRATION, BD_PROC_MODE_CHILD_R, proc_bd_parent, + proc_calibration_read, NULL); + + null_check &= (int)proc_calibration; + + // Child: /proc/bd/panel_size. + // + proc_panel_size = create_bd_proc_entry(BD_PROC_PANEL_SIZE, BD_PROC_MODE_CHILD_RW, proc_bd_parent, + proc_panel_size_read, proc_panel_size_write); + + null_check &= (int)proc_panel_size; + + // Child: /proc/bd/panel_params. + // + proc_panel_params = create_bd_proc_entry(BD_PROC_PANEL_PARAMS, BD_PROC_MODE_CHILD_R, proc_bd_parent, + proc_panel_params_read, NULL); + + null_check &= (int)proc_panel_params; + + // Child: /proc/bd/mw_flags. + // + proc_mw_flags = create_bd_proc_entry(BD_PROC_MW_FLAGS, BD_PROC_MODE_CHILD_RW, proc_bd_parent, + proc_mw_flags_read, proc_mw_flags_write); + + null_check &= (int)proc_mw_flags; + + // Child: /proc/bd/rcs_flags. + // + proc_rcs_flags = create_bd_proc_entry(BD_PROC_RCS_FLAGS, BD_PROC_MODE_CHILD_RW, proc_bd_parent, + proc_rcs_flags_read, proc_rcs_flags_write); + + null_check &= (int)proc_rcs_flags; + + // Child: /proc/bd/progress_count. + // + proc_progress_count = create_bd_proc_entry(BD_PROC_PROGRESS_COUNT, BD_PROC_MODE_CHILD_RW, proc_bd_parent, + proc_progress_count_read, proc_progress_count_write); + + null_check &= (int)proc_progress_count; + + // Child: /proc/bd/boot_milestone. + // + proc_boot_milestone = create_bd_proc_entry(BD_PROC_BOOT_MILESTONE, BD_PROC_MODE_CHILD_RW, proc_bd_parent, + proc_boot_milestone_read, proc_boot_milestone_write); + + null_check &= (int)proc_boot_milestone; + num_boot_milestones = 0; + rwlock_init(&boot_milestone_lock); + + // Success? + // + if ( 0 == null_check ) + bootdata_cleanup(); + else + result = 0; + } + + // Done. + // + return ( result ); +} + +static void __exit +bootdata_exit( + void) +{ + bootdata_cleanup(); +} + +module_init(bootdata_init); +module_exit(bootdata_exit); + +EXPORT_SYMBOL(boot_milestone_write); + +MODULE_DESCRIPTION("bootdata driver"); +MODULE_AUTHOR("Lab126"); +MODULE_LICENSE("Proprietary"); diff -urN linux-2.6.26/arch/arm/mach-mx35/clock.c linux-2.6.26-lab126/arch/arm/mach-mx35/clock.c --- linux-2.6.26/arch/arm/mach-mx35/clock.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/clock.c 2010-08-11 00:35:00.000000000 -0400 @@ -0,0 +1,2021 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_DEBUG_FS +#include +#endif + +#include "crm_regs.h" + +#define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */ +#define PROPAGATE_RATE_DIS 2 +#define MXC_PERCLK_DIVIDER 0x1000 + +static int cpu_curr_wp; +static struct cpu_wp *cpu_wp_tbl; +static int cpu_wp_nr; +static int cpu_wp_offset; + +static struct clk mcu_pll_clk; +static struct clk peri_pll_clk; +static struct clk ipg_clk; +static struct clk ckih_clk; +static struct clk ckie_clk; +static struct clk ahb_clk; +static struct clk cpu_clk; + +#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel)) +#define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF) +#define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF) +#define CLK_CODE_PATH(c) ((c) & 0xFF) + +static int __get_arm_div(unsigned long pdr0, int *fi, int *fd); + +static int g_clk_mux_auto[8] = { + CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1, + CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1, +}; + +static int g_clk_mux_consumer[16] = { + CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(2, 2, 0), -1, + -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0), + CLK_CODE(1, 8, 0), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1, + -1, -1, CLK_CODE(4, 2, 0), -1, +}; + +static int g_hsp_div_table[3][16] = { + {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1}, + {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1}, + {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1}, +}; + +static void __calc_dividers(u32 div, u32 *pre, u32 *post, u32 base) +{ + u32 min_pre, temp_pre, old_err, err; + min_pre = (div - 1) / base + 1; + old_err = 8; + for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) { + if (div > (temp_pre * base)) + break; + if (div < (temp_pre * temp_pre)) + continue; + err = div % temp_pre; + if (err == 0) { + *pre = temp_pre; + break; + } + err = temp_pre - err; + if (err < old_err) { + old_err = err; + *pre = temp_pre; + } + } + *post = (div + *pre - 1) / *pre; +} + +static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post) +{ + if (div >= 512) { + *pre = 8; + *post = 64; + } else if (div >= 64) { + __calc_dividers(div, pre, post, 64); + } else if (div <= 8) { + *pre = div; + *post = 1; + } else { + *pre = 1; + *post = div; + } +} + +static void __calc_two_dividers(u32 div, u32 *pre, u32 *post) +{ + if (div >= 64) { + *pre = *post = 8; + } else if (div > 8) { + __calc_dividers(div, pre, post, 8); + } else { + *pre = 1; + *post = div; + } +} + +static unsigned long _clk_per_post_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 pre, post; + u32 div = clk->parent->rate / rate; + if (clk->parent->rate % rate) + div++; + + __calc_pre_post_dividers(div, &pre, &post); + + return clk->parent->rate / (pre * post); +} + +static unsigned long _clk_round_rate(struct clk *clk, unsigned long rate) +{ + u32 pre, post; + u32 div = clk->parent->rate / rate; + if (clk->parent->rate % rate) + div++; + + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) { + __calc_two_dividers(div, &pre, &post); + return clk->parent->rate / (pre * post); + } else + return clk->parent->rate / div; +} + +static int __switch_cpu_wp(struct clk *clk, unsigned long rate) +{ + int i; + if (cpu_wp_tbl[cpu_curr_wp].cpu_rate < rate) { + for (i = cpu_curr_wp + 2; i < cpu_wp_nr; i += 2) { + if (rate == cpu_wp_tbl[i].cpu_rate) + goto found; + } + return -EINVAL; + } else { + for (i = cpu_curr_wp - 2; i >= 0; i -= 2) { + if (rate == cpu_wp_tbl[i].cpu_rate) + goto found; + } + return -EINVAL; + } + found: + __raw_writel(cpu_wp_tbl[i].pdr0_reg | MXC_PERCLK_DIVIDER, MXC_CCM_PDR0); + + if (cpu_wp_tbl[i].pll_rate != cpu_wp_tbl[cpu_curr_wp].pll_rate) + clk_set_rate(clk->parent, cpu_wp_tbl[i].pll_rate); + cpu_curr_wp = i; + clk->rate = rate; + return 0; +} + +static int __switch_cpu_rate(struct clk *clk, unsigned long rate) +{ + int prev; + unsigned long tmp; + int arm_div, fi, fd, start, end; + if (cpu_wp_tbl[cpu_curr_wp].cpu_rate < rate) { + start = cpu_curr_wp + 2; + end = cpu_wp_nr; + prev = cpu_curr_wp; + } else { + start = cpu_wp_offset + 2; + end = cpu_curr_wp; + prev = cpu_wp_offset; + } + while (start < end) { + arm_div = __get_arm_div(cpu_wp_tbl[start].pdr0_reg, &fi, &fd); + tmp = (mcu_pll_clk.rate * fi) / (arm_div * fd); + if (tmp == rate) { + prev = start; + break; + } + if (tmp < rate) { + if (prev < start) + prev = start; + } else { + break; + } + start += 2; + } + if (start >= end) + return -EINVAL; + + if (prev == cpu_curr_wp) + return 0; + + __raw_writel(cpu_wp_tbl[prev].pdr0_reg | MXC_PERCLK_DIVIDER, MXC_CCM_PDR0); + + cpu_curr_wp = prev; + clk->rate = rate; + return 0; +} + +static int __get_arm_div(unsigned long pdr0, int *fi, int *fd) +{ + int *pclk_mux; + if ((pdr0 & MXC_CCM_PDR0_AUTO_CON) + || (cpu_is_mx35_rev(CHIP_REV_2_0) >= 1)) + pclk_mux = + g_clk_mux_consumer + + ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> + MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); + else { + pclk_mux = g_clk_mux_auto + + ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >> + MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET); + } + + if ((*pclk_mux) == -1) { + BUG(); + return -EINVAL; + } + + if (fi && fd) { + if (!CLK_CODE_PATH(*pclk_mux)) { + *fi = *fd = 1; + return CLK_CODE_ARM(*pclk_mux); + } + if ((pdr0 & MXC_CCM_PDR0_AUTO_CON) + || (cpu_is_mx35_rev(CHIP_REV_2_0) >= 1)) { + *fi = 3; + *fd = 4; + } else { + *fi = 2; + *fd = 3; + } + } + return CLK_CODE_ARM(*pclk_mux); +} + +static int __get_ahb_div(unsigned long pdr0) +{ + int *pclk_mux; + if ((pdr0 & MXC_CCM_PDR0_AUTO_CON) + || (cpu_is_mx35_rev(CHIP_REV_2_0) >= 1)) { + pclk_mux = + g_clk_mux_consumer + + ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> + MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); + } else { + pclk_mux = g_clk_mux_auto + + ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >> + MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET); + } + + if ((*pclk_mux) == -1) { + BUG(); + return -EINVAL; + } + return CLK_CODE_AHB(*pclk_mux); +} + +static void sync_cpu_wb(void) +{ + int i; + struct cpu_wp *p; + unsigned long reg = __raw_readl(MXC_CCM_PDR0); + if ((reg & MXC_CCM_PDR0_AUTO_CON) + || (cpu_is_mx35_rev(CHIP_REV_2_0) >= 1)) { + reg &= MXC_CCM_PDR0_CON_MUX_DIV_MASK; + } else { + reg &= MXC_CCM_PDR0_AUTO_MUX_DIV_MASK; + } + for (i = 0; i < cpu_wp_nr; i++) { + p = cpu_wp_tbl + cpu_curr_wp; + if (p->pdr0_reg == (reg & 0xF0E00)) + break; + cpu_curr_wp = (cpu_curr_wp + 1) % cpu_wp_nr; + } + cpu_wp_offset = cpu_curr_wp & 1; +} + +static int _clk_enable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg |= 3 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + return 0; +} + +static void _clk_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(3 << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); +} + +static void _clk_emi_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(3 << clk->enable_shift); + reg |= (1 << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); +} + +static int _clk_asrc_enable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(MXC_CCM_COSR); + __raw_writel(reg | MXC_CCM_COSR_ASRC_AUDIO_EN, MXC_CCM_COSR); + return 0; +} + +static void _clk_asrc_disable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(MXC_CCM_COSR); + __raw_writel(reg & (~MXC_CCM_COSR_ASRC_AUDIO_EN), MXC_CCM_COSR); +} + +static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + signed long pd = 1; /* Pre-divider */ + signed long mfi; /* Multiplication Factor (Integer part) */ + signed long mfn; /* Multiplication Factor (Integer part) */ + signed long mfd; /* Multiplication Factor (Denominator Part) */ + signed long tmp; + u32 ref_freq = clk->parent->rate; + + if ((clk == &mcu_pll_clk) + && (clk->parent->rate == cpu_wp_tbl[cpu_curr_wp].pll_rate)) { + __raw_writel(cpu_wp_tbl[cpu_curr_wp].pll_reg, MXC_CCM_MPCTL); + clk->rate = rate; + return 0; + } + + while (((ref_freq / pd) * 10) > rate) + pd++; + + if ((ref_freq / pd) < PRE_DIV_MIN_FREQ) + return -EINVAL; + + /* the ref_freq/2 in the following is to round up */ + mfi = (((rate / 2) * pd) + (ref_freq / 2)) / ref_freq; + if (mfi < 5 || mfi > 15) + return -EINVAL; + + /* pick a mfd value that will work + * then solve for mfn */ + mfd = ref_freq / 50000; + + /* + * pll_freq * pd * mfd + * mfn = -------------------- - (mfi * mfd) + * 2 * ref_freq + */ + /* the tmp/2 is for rounding */ + tmp = ref_freq / 10000; + mfn = + ((((((rate / 2) + (tmp / 2)) / tmp) * pd) * mfd) / 10000) - + (mfi * mfd); + + mfn = mfn & 0x3ff; + pd--; + mfd--; + + /* Change the Pll value */ + reg = (mfi << MXC_CCM_PCTL_MFI_OFFSET) | + (mfn << MXC_CCM_PCTL_MFN_OFFSET) | + (mfd << MXC_CCM_PCTL_MFD_OFFSET) | (pd << MXC_CCM_PCTL_PD_OFFSET); + + if (clk == &mcu_pll_clk) + __raw_writel(reg, MXC_CCM_MPCTL); + else if (clk == &peri_pll_clk) + __raw_writel(reg, MXC_CCM_PPCTL); + + clk->rate = rate; + return 0; +} + +static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate) +{ + if ((rate < ahb_clk.rate) || (rate % ahb_clk.rate != 0)) { + printk(KERN_ERR "Wrong rate %lu in _clk_cpu_set_rate\n", rate); + return -EINVAL; + } + + if (clk->rate == rate) + return 0; + + if (clk->parent->rate == cpu_wp_tbl[cpu_curr_wp].pll_rate) + return __switch_cpu_wp(clk, rate); + return __switch_cpu_rate(clk, rate); +} + +static void _clk_pll_recalc(struct clk *clk) +{ + long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; + unsigned long reg = 0; + s64 temp; + + ref_clk = ckih_clk.rate; + + if (clk == &mcu_pll_clk) + reg = __raw_readl(MXC_CCM_MPCTL); + else if (clk == &peri_pll_clk) + reg = __raw_readl(MXC_CCM_PPCTL); + else + BUG(); + + pdf = (reg & MXC_CCM_PCTL_PD_MASK) >> MXC_CCM_PCTL_PD_OFFSET; + mfd = (reg & MXC_CCM_PCTL_MFD_MASK) >> MXC_CCM_PCTL_MFD_OFFSET; + mfi = (reg & MXC_CCM_PCTL_MFI_MASK) >> MXC_CCM_PCTL_MFI_OFFSET; + mfi = (mfi <= 5) ? 5 : mfi; + mfn = mfn_abs = reg & MXC_CCM_PCTL_MFN_MASK; + + if (mfn >= 0x200) { + mfn |= 0xFFFFFE00; + mfn_abs = -mfn; + } + + ref_clk *= 2; + ref_clk /= pdf + 1; + + temp = (u64) ref_clk * mfn_abs; + do_div(temp, mfd + 1); + if (mfn < 0) + temp = -temp; + temp = (ref_clk * mfi) + temp; + + clk->rate = temp; +} + +static int _clk_peri_pll_enable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(MXC_CCM_CCMR); + reg |= MXC_CCM_CCMR_UPE; + __raw_writel(reg, MXC_CCM_CCMR); + + /* No lock bit on MX31, so using max time from spec */ + udelay(80); + + return 0; +} + +static void _clk_peri_pll_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCMR); + reg &= ~MXC_CCM_CCMR_UPE; + __raw_writel(reg, MXC_CCM_CCMR); +} + +#define PDR0(mask, off) ((__raw_readl(MXC_CCM_PDR0) & mask) >> off) +#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off) +#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off) +#define PDR3(mask, off) ((__raw_readl(MXC_CCM_PDR3) & mask) >> off) +#define PDR4(mask, off) ((__raw_readl(MXC_CCM_PDR4) & mask) >> off) + +static void _clk_cpu_recalc(struct clk *clk) +{ + unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0); + int arm_div, fi, fd; + if (clk->parent->rate == cpu_wp_tbl[cpu_curr_wp].pll_rate) { + clk->rate = cpu_wp_tbl[cpu_curr_wp].cpu_rate; + } else { + arm_div = __get_arm_div(pdr0, &fi, &fd); + clk->rate = (clk->parent->rate * fi) / (arm_div * fd); + } +} + +static void _clk_hclk_recalc(struct clk *clk) +{ + unsigned long ahb_div, pdr0 = __raw_readl(MXC_CCM_PDR0); + ahb_div = __get_ahb_div(pdr0); + clk->rate = clk->parent->rate / ahb_div; +} + +static void _clk_ipg_recalc(struct clk *clk) +{ + clk->rate = clk->parent->rate / 2; +} + +static void _clk_nfc_recalc(struct clk *clk) +{ + unsigned long nfc_pdf; + + nfc_pdf = PDR4(MXC_CCM_PDR4_NFC_PODF_MASK, + MXC_CCM_PDR4_NFC_PODF_OFFSET); + clk->rate = clk->parent->rate / (nfc_pdf + 1); +} + +static void _clk_hsp_recalc(struct clk *clk) +{ + int hsp_pdf; + unsigned long reg; + reg = __raw_readl(MXC_CCM_PDR0); + + if ((reg & MXC_CCM_PDR0_AUTO_CON) + || (cpu_is_mx35_rev(CHIP_REV_2_0) >= 1)) { + hsp_pdf = + (reg & MXC_CCM_PDR0_HSP_PODF_MASK) >> + MXC_CCM_PDR0_HSP_PODF_OFFSET; + reg = + (reg & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> + MXC_CCM_PDR0_CON_MUX_DIV_OFFSET; + if (hsp_pdf < 3) { + hsp_pdf = g_hsp_div_table[hsp_pdf][reg]; + if (hsp_pdf > 0) + clk->rate = clk->parent->rate / hsp_pdf; + } + } else { + clk->rate = clk->parent->rate; + } +} + +static void _clk_mlb_recalc(struct clk *clk) +{ + clk->rate = clk->parent->rate * 2; +} + +static void _clk_usb_recalc(struct clk *clk) +{ + unsigned long usb_podf, usb_prdf; + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) { + usb_podf = PDR4(MXC_CCM_PDR4_USB_PODF_MASK, + MXC_CCM_PDR4_USB_PODF_OFFSET); + usb_prdf = PDR4(MXC_CCM_PDR4_USB_PRDF_MASK, + MXC_CCM_PDR4_USB_PRDF_OFFSET); + clk->rate = + clk->parent->rate / ((usb_prdf + 1) * (usb_podf + 1)); + } else { + usb_podf = PDR4(MXC_CCM_PDR4_USB_PODF_MASK_V2, + MXC_CCM_PDR4_USB_PODF_OFFSET); + clk->rate = clk->parent->rate / (usb_podf + 1); + } +} + +static int _clk_usb_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 podf, prdf; + + div = clk->parent->rate / rate; + + if ((clk->parent->rate / div) != rate) + return -EINVAL; + + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) { + __calc_two_dividers(div, &prdf, &podf); + reg = __raw_readl(MXC_CCM_PDR4) & + ~(MXC_CCM_PDR4_USB_PODF_MASK | MXC_CCM_PDR4_USB_PRDF_MASK); + reg |= (podf - 1) << MXC_CCM_PDR4_USB_PODF_OFFSET; + reg |= (prdf - 1) << MXC_CCM_PDR4_USB_PRDF_OFFSET; + } else { + podf = div - 1; + reg = + __raw_readl(MXC_CCM_PDR4) & ~MXC_CCM_PDR4_USB_PODF_MASK_V2; + reg |= (podf - 1) << MXC_CCM_PDR4_USB_PODF_OFFSET; + } + __raw_writel(reg, MXC_CCM_PDR4); + clk->rate = rate; + return 0; +} + +static void _clk_csi_recalc(struct clk *clk) +{ + u32 podf, prdf; + + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) { + prdf = PDR2(MXC_CCM_PDR2_CSI_PRDF_MASK, + MXC_CCM_PDR2_CSI_PRDF_OFFSET); + podf = + PDR2(MXC_CCM_PDR2_CSI_PODF_MASK, + MXC_CCM_PDR2_CSI_PODF_OFFSET); + clk->rate = clk->parent->rate / ((prdf + 1) * (podf + 1)); + } else { + podf = + PDR2(MXC_CCM_PDR2_CSI_PODF_MASK_V2, + MXC_CCM_PDR2_CSI_PODF_OFFSET); + clk->rate = clk->parent->rate / (podf + 1); + } +} + +static int _clk_csi_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 prdf, podf; + + div = clk->parent->rate / rate; + + if ((clk->parent->rate / div) != rate) + return -EINVAL; + + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) { + __calc_two_dividers(div, &prdf, &podf); + reg = __raw_readl(MXC_CCM_PDR2) & + ~(MXC_CCM_PDR2_CSI_PRDF_MASK | MXC_CCM_PDR2_CSI_PODF_MASK); + reg |= (podf - 1) << MXC_CCM_PDR2_CSI_PODF_OFFSET; + reg |= (prdf - 1) << MXC_CCM_PDR2_CSI_PRDF_OFFSET; + } else { + reg = + __raw_readl(MXC_CCM_PDR2) & ~MXC_CCM_PDR2_CSI_PODF_MASK_V2; + reg |= (div - 1) << MXC_CCM_PDR2_CSI_PODF_OFFSET; + } + + /* Set CSI clock divider */ + __raw_writel(reg, MXC_CCM_PDR2); + clk->rate = rate; + return 0; +} + +static int _clk_csi_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + if (parent == &cpu_clk) + reg = __raw_readl(MXC_CCM_PDR2) | MXC_CCM_PDR2_CSI_M_U; + else if (parent == &peri_pll_clk) + reg = __raw_readl(MXC_CCM_PDR2) & (~MXC_CCM_PDR2_CSI_M_U); + else + return -EINVAL; + __raw_writel(reg, MXC_CCM_PDR2); + return 0; +} + +static void _clk_per_recalc(struct clk *clk) +{ + u32 podf = 0, prdf = 0; + + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) { + if (clk->parent == &cpu_clk) { + prdf = PDR4(MXC_CCM_PDR4_PER0_PRDF_MASK, + MXC_CCM_PDR4_PER0_PRDF_OFFSET); + podf = PDR4(MXC_CCM_PDR4_PER0_PODF_MASK, + MXC_CCM_PDR4_PER0_PODF_OFFSET); + } else { + podf = PDR0(MXC_CCM_PDR0_PER_PODF_MASK, + MXC_CCM_PDR0_PER_PODF_OFFSET); + } + clk->rate = clk->parent->rate / ((podf + 1) * (prdf + 1)); + } else { + if (clk->parent == &ahb_clk) + podf = PDR0(MXC_CCM_PDR0_PER_PODF_MASK, + MXC_CCM_PDR0_PER_PODF_OFFSET); + else if (clk->parent == &cpu_clk) { + podf = PDR4(MXC_CCM_PDR4_PER0_PODF_MASK_V2, + MXC_CCM_PDR4_PER0_PODF_OFFSET); + } + clk->rate = clk->parent->rate / (podf + 1); + } +} + +static void _clk_uart_per_recalc(struct clk *clk) +{ + unsigned long podf, prdf; + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) { + prdf = PDR4(MXC_CCM_PDR4_UART_PRDF_MASK, + MXC_CCM_PDR4_UART_PRDF_OFFSET); + podf = PDR4(MXC_CCM_PDR4_UART_PODF_MASK, + MXC_CCM_PDR4_UART_PODF_OFFSET); + clk->rate = clk->parent->rate / ((prdf + 1) * (podf + 1)); + } else { + podf = + PDR4(MXC_CCM_PDR4_UART_PODF_MASK_V2, + MXC_CCM_PDR4_UART_PODF_OFFSET); + clk->rate = clk->parent->rate / (podf + 1); + } + +} + +static int _clk_uart_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 prdf, podf; + + div = clk->parent->rate / rate; + + if ((clk->parent->rate / div) != rate) + return -EINVAL; + + /* Set UART clock divider */ + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) { + __calc_two_dividers(div, &prdf, &podf); + reg = __raw_readl(MXC_CCM_PDR4) & + ~(MXC_CCM_PDR4_UART_PRDF_MASK | + MXC_CCM_PDR4_UART_PODF_MASK); + reg |= (podf - 1) << MXC_CCM_PDR4_UART_PODF_OFFSET; + reg |= (prdf - 1) << MXC_CCM_PDR4_UART_PRDF_OFFSET; + } else { + reg = + __raw_readl(MXC_CCM_PDR4) & ~MXC_CCM_PDR4_UART_PODF_MASK_V2; + reg |= (div - 1) << MXC_CCM_PDR4_UART_PODF_OFFSET; + } + __raw_writel(reg, MXC_CCM_PDR4); + clk->rate = rate; + return 0; +} + +static void _clk_ssi_recalc(struct clk *clk) +{ + unsigned long ssi_pdf, ssi_prepdf; + + if (clk->id == 1) { + ssi_pdf = PDR2(MXC_CCM_PDR2_SSI2_PODF_MASK, + MXC_CCM_PDR2_SSI2_PODF_OFFSET); + ssi_prepdf = PDR2(MXC_CCM_PDR2_SSI2_PRDF_MASK, + MXC_CCM_PDR2_SSI2_PRDF_OFFSET); + } else { + ssi_pdf = PDR2(MXC_CCM_PDR2_SSI1_PODF_MASK, + MXC_CCM_PDR2_SSI1_PODF_OFFSET); + ssi_prepdf = PDR2(MXC_CCM_PDR2_SSI1_PRDF_MASK, + MXC_CCM_PDR2_SSI1_PRDF_OFFSET); + } + clk->rate = clk->parent->rate / ((ssi_prepdf + 1) * (ssi_pdf + 1)); +} + +static int _clk_ssi_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 pre, post; + + div = clk->parent->rate / rate; + + if ((clk->parent->rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + if (clk->id == 1) { + reg = __raw_readl(MXC_CCM_PDR2) & + ~(MXC_CCM_PDR2_SSI2_PRDF_MASK | + MXC_CCM_PDR2_SSI2_PODF_MASK); + reg |= (post - 1) << MXC_CCM_PDR2_SSI2_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_PDR2_SSI2_PRDF_OFFSET; + } else { + reg = __raw_readl(MXC_CCM_PDR2) & + ~(MXC_CCM_PDR2_SSI1_PRDF_MASK | + MXC_CCM_PDR2_SSI1_PODF_MASK); + reg |= (post - 1) << MXC_CCM_PDR2_SSI1_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_PDR2_SSI1_PRDF_OFFSET; + } + __raw_writel(reg, MXC_CCM_PDR2); + + clk->rate = rate; + return 0; +} + +static void _clk_mstick1_recalc(struct clk *clk) +{ + unsigned long prdf, podf; + prdf = PDR1(MXC_CCM_PDR1_MSHC_PRDF_MASK, MXC_CCM_PDR1_MSHC_PRDF_OFFSET); + podf = PDR1(MXC_CCM_PDR1_MSHC_PODF_MASK, MXC_CCM_PDR1_MSHC_PODF_OFFSET); + clk->rate = clk->parent->rate / ((prdf + 1) * (podf + 1)); +} + +static int _clk_mstick1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 pre, post; + + div = clk->parent->rate / rate; + + if ((clk->parent->rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + reg = __raw_readl(MXC_CCM_PDR1) & + ~(MXC_CCM_PDR1_MSHC_PRDF_MASK | MXC_CCM_PDR1_MSHC_PODF_MASK); + reg |= (post - 1) << MXC_CCM_PDR1_MSHC_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_PDR1_MSHC_PRDF_OFFSET; + __raw_writel(reg, MXC_CCM_PDR1); + + clk->rate = rate; + return 0; +} + +static int _clk_mstick1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + if (parent == &cpu_clk) + reg = __raw_readl(MXC_CCM_PDR1) | MXC_CCM_PDR1_MSHC_M_U; + else if (parent == &peri_pll_clk) + reg = __raw_readl(MXC_CCM_PDR1) & (~MXC_CCM_PDR1_MSHC_M_U); + else + return -EINVAL; + __raw_writel(reg, MXC_CCM_PDR1); + return 0; +} + +static void _clk_spdif_recalc(struct clk *clk) +{ + unsigned long prdf, podf; + prdf = + PDR3(MXC_CCM_PDR3_SPDIF_PRDF_MASK, MXC_CCM_PDR3_SPDIF_PRDF_OFFSET); + podf = + PDR3(MXC_CCM_PDR3_SPDIF_PODF_MASK, MXC_CCM_PDR3_SPDIF_PODF_OFFSET); + clk->rate = clk->parent->rate / ((prdf + 1) * (podf + 1)); +} + +static int _clk_spdif_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 pre, post; + + div = clk->parent->rate / rate; + + if ((clk->parent->rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + reg = __raw_readl(MXC_CCM_PDR3) & + ~(MXC_CCM_PDR3_SPDIF_PRDF_MASK | MXC_CCM_PDR3_SPDIF_PODF_MASK); + reg |= (post - 1) << MXC_CCM_PDR3_SPDIF_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_PDR3_SPDIF_PRDF_OFFSET; + __raw_writel(reg, MXC_CCM_PDR3); + + clk->rate = rate; + return 0; +} + +static int _clk_spdif_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + if (parent == &cpu_clk) + reg = __raw_readl(MXC_CCM_PDR3) | MXC_CCM_PDR3_SPDIF_M_U; + else if (parent == &peri_pll_clk) + reg = __raw_readl(MXC_CCM_PDR3) & (~MXC_CCM_PDR3_SPDIF_M_U); + else + return -EINVAL; + __raw_writel(reg, MXC_CCM_PDR3); + return 0; +} + +static void _clk_asrc_recalc(struct clk *clk) +{ + unsigned long div; + div = __raw_readl(MXC_CCM_COSR) & MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK; + div = div >> MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET; + clk->rate = clk->parent->rate / (div + 1); +} + +static int _clk_asrc_set_rate(struct clk *clk, unsigned long rate) +{ + int div; + unsigned long reg; + if (clk->parent->rate % rate) + return -EINVAL; + + div = clk->parent->rate / rate; + reg = __raw_readl(MXC_CCM_COSR) & (~MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK); + reg |= (div - 1) << MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_COSR); + clk->rate = rate; + return 0; +} + +static void _clk_sdhc_recalc(struct clk *clk) +{ + u32 podf = 0, prdf = 0; + + switch (clk->id) { + case 0: + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) { + prdf = PDR3(MXC_CCM_PDR3_ESDHC1_PRDF_MASK, + MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET); + podf = PDR3(MXC_CCM_PDR3_ESDHC1_PODF_MASK, + MXC_CCM_PDR3_ESDHC1_PODF_OFFSET); + } else + podf = PDR3(MXC_CCM_PDR3_ESDHC1_PODF_MASK_V2, + MXC_CCM_PDR3_ESDHC1_PODF_OFFSET); + break; + case 1: + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) { + prdf = PDR3(MXC_CCM_PDR3_ESDHC2_PRDF_MASK, + MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET); + podf = PDR3(MXC_CCM_PDR3_ESDHC2_PODF_MASK, + MXC_CCM_PDR3_ESDHC2_PODF_OFFSET); + } else + podf = PDR3(MXC_CCM_PDR3_ESDHC2_PODF_MASK_V2, + MXC_CCM_PDR3_ESDHC2_PODF_OFFSET); + break; + case 2: + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) { + prdf = PDR3(MXC_CCM_PDR3_ESDHC3_PRDF_MASK, + MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET); + podf = PDR3(MXC_CCM_PDR3_ESDHC3_PODF_MASK, + MXC_CCM_PDR3_ESDHC3_PODF_OFFSET); + } else + podf = PDR3(MXC_CCM_PDR3_ESDHC3_PODF_MASK_V2, + MXC_CCM_PDR3_ESDHC3_PODF_OFFSET); + break; + default: + return; + } + clk->rate = clk->parent->rate / ((podf + 1) * (prdf + 1)); +} + +static int _clk_sdhc_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 prdf, podf; + + div = clk->parent->rate / rate; + + if ((clk->parent->rate / div) != rate) + return -EINVAL; + + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) + __calc_pre_post_dividers(div, &prdf, &podf); + + switch (clk->id) { + case 0: + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) { + reg = __raw_readl(MXC_CCM_PDR3) & + ~(MXC_CCM_PDR3_ESDHC1_PRDF_MASK | + MXC_CCM_PDR3_ESDHC1_PODF_MASK); + reg |= (podf - 1) << MXC_CCM_PDR3_ESDHC1_PODF_OFFSET; + reg |= (prdf - 1) << MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET; + } else { + reg = __raw_readl(MXC_CCM_PDR3) & + ~MXC_CCM_PDR3_ESDHC1_PODF_MASK_V2; + reg |= (div - 1) << MXC_CCM_PDR3_ESDHC1_PODF_OFFSET; + } + break; + case 1: + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) { + reg = __raw_readl(MXC_CCM_PDR3) & + ~(MXC_CCM_PDR3_ESDHC2_PRDF_MASK | + MXC_CCM_PDR3_ESDHC2_PODF_MASK); + reg |= (podf - 1) << MXC_CCM_PDR3_ESDHC2_PODF_OFFSET; + reg |= (prdf - 1) << MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET; + } else { + reg = __raw_readl(MXC_CCM_PDR3) & + ~MXC_CCM_PDR3_ESDHC2_PODF_MASK_V2; + reg |= (div - 1) << MXC_CCM_PDR3_ESDHC2_PODF_OFFSET; + } + break; + case 2: + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) { + reg = __raw_readl(MXC_CCM_PDR3) & + ~(MXC_CCM_PDR3_ESDHC3_PRDF_MASK | + MXC_CCM_PDR3_ESDHC3_PODF_MASK); + reg |= (podf - 1) << MXC_CCM_PDR3_ESDHC3_PODF_OFFSET; + reg |= (prdf - 1) << MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET; + } else { + reg = __raw_readl(MXC_CCM_PDR3) & + ~MXC_CCM_PDR3_ESDHC3_PODF_MASK_V2; + reg |= (div - 1) << MXC_CCM_PDR3_ESDHC3_PODF_OFFSET; + } + break; + default: + return -EINVAL; + } + __raw_writel(reg, MXC_CCM_PDR3); + + clk->rate = rate; + return 0; +} + +static int _clk_ckie_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_PMCR2) & ~MXC_CCM_PMCR2_OSC_AUDIO_DOWN; + __raw_writel(reg, MXC_CCM_PMCR2); + + return 0; +} + +static void _clk_ckie_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_PMCR2) | MXC_CCM_PMCR2_OSC_AUDIO_DOWN; + __raw_writel(reg, MXC_CCM_PMCR2); +} + +static struct clk ckih_clk = { + .name = "ckih", + .rate = CKIH_CLK_FREQ, + .flags = RATE_FIXED, +}; + +static struct clk int_32k_clk = { + .name = "int_32k", + .rate = CKIL_CLK_FREQ, + .flags = RATE_FIXED, +}; + +static struct clk ext_32k_clk = { + .name = "ext_32k", + .rate = CKIL_EXT_FREQ, + .flags = RATE_FIXED, +}; + +static int _clk_ckil_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + if (parent == &int_32k_clk) { + reg = __raw_readl(MXC_CCM_PDR0) & (~MXC_CCM_PDR0_CKIL_SEL); + clk->rate = parent->rate; + } else if (parent == &ext_32k_clk) { + reg = __raw_readl(MXC_CCM_PDR0) | MXC_CCM_PDR0_CKIL_SEL; + clk->rate = parent->rate; + } else + return -EINVAL; + + __raw_writel(reg, MXC_CCM_PDR0); + return 0; +} + +static int _clk_ckil_set_rate(struct clk *clk, unsigned long rate) +{ + clk->rate = clk->parent->rate; + return 0; +} + +static struct clk ckil_clk = { + .name = "ckil", + .parent = &ext_32k_clk, + .set_parent = _clk_ckil_set_parent, + .set_rate = _clk_ckil_set_rate, +}; + +static struct clk ckie_clk = { + .name = "ckie", + .rate = CKIE_CLK_FREQ, + .flags = RATE_FIXED, + .enable = _clk_ckie_enable, + .disable = _clk_ckie_disable, +}; + +static struct clk mcu_pll_clk = { + .name = "mcu_pll", + .parent = &ckih_clk, + .set_rate = _clk_pll_set_rate, + .recalc = _clk_pll_recalc, + .flags = RATE_PROPAGATES, +}; + +static struct clk peri_pll_clk = { + .name = "peri_pll", + .parent = &ckih_clk, + .set_rate = _clk_pll_set_rate, + .recalc = _clk_pll_recalc, + .enable = _clk_peri_pll_enable, + .disable = _clk_peri_pll_disable, + .flags = RATE_PROPAGATES, +}; + +static struct clk cpu_clk = { + .name = "cpu_clk", + .parent = &mcu_pll_clk, + .recalc = _clk_cpu_recalc, + .set_rate = _clk_cpu_set_rate, +}; + +static struct clk ahb_clk = { + .name = "ahb_clk", + .parent = &cpu_clk, + .recalc = _clk_hclk_recalc, + .flags = RATE_PROPAGATES, +}; + +static struct clk ipg_clk = { + .name = "ipg_clk", + .parent = &ahb_clk, + .recalc = _clk_ipg_recalc, + .flags = RATE_PROPAGATES, +}; + +static struct clk perclk_clk = { + .name = "perclk_clk", + .parent = &ahb_clk, + .recalc = _clk_per_recalc, + .flags = RATE_PROPAGATES, +}; + +static struct clk uart_per_clk = { + .name = "uart_per_clk", + .parent = &peri_pll_clk, + .recalc = _clk_uart_per_recalc, + .round_rate = _clk_round_rate, + .set_rate = _clk_uart_set_rate, + .flags = RATE_PROPAGATES, +}; + +static struct clk asrc_clk[] = { + { + .name = "asrc_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_ASRC_OFFSET, + .disable = _clk_disable,}, + { + .name = "asrc_audio_clk", + .parent = &ckie_clk, + .recalc = _clk_asrc_recalc, + .round_rate = _clk_round_rate, + .set_rate = _clk_asrc_set_rate, + .enable = _clk_asrc_enable, + .disable = _clk_asrc_disable,}, +}; + +static struct clk ata_clk = { + .name = "ata_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_ATA_OFFSET, + .disable = _clk_disable, +}; + +static struct clk can_clk[] = { + { + .name = "can_clk", + .id = 0, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_CAN1_OFFSET, + .disable = _clk_disable,}, + { + .name = "can_clk", + .id = 1, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_CAN2_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk cspi_clk[] = { + { + .name = "cspi_clk", + .id = 0, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_CSPI1_OFFSET, + .disable = _clk_disable,}, + { + .name = "cspi_clk", + .id = 1, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_CSPI2_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk ect_clk = { + .name = "ect_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_ECT_OFFSET, + .disable = _clk_disable, +}; + +static struct clk emi_clk = { + .name = "emi_clk", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_EMI_OFFSET, + .disable = _clk_emi_disable, +}; + +static struct clk epit_clk[] = { + { + .name = "epit_clk", + .id = 0, + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_EPIT1_OFFSET, + .disable = _clk_disable,}, + { + .name = "epit_clk", + .id = 1, + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_EPIT2_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk esai_clk = { + .name = "esai_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_ESAI_OFFSET, + .disable = _clk_disable, +}; + +static struct clk sdhc_clk[] = { + { + .name = "sdhc_clk", + .id = 0, + .parent = &peri_pll_clk, + .recalc = _clk_sdhc_recalc, + .set_rate = _clk_sdhc_set_rate, + .round_rate = _clk_round_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_ESDHC1_OFFSET, + .disable = _clk_disable,}, + { + .name = "sdhc_clk", + .id = 1, + .parent = &peri_pll_clk, + .recalc = _clk_sdhc_recalc, + .set_rate = _clk_sdhc_set_rate, + .round_rate = _clk_round_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_ESDHC2_OFFSET, + .disable = _clk_disable,}, + { + .name = "sdhc_clk", + .id = 2, + .parent = &peri_pll_clk, + .recalc = _clk_sdhc_recalc, + .set_rate = _clk_sdhc_set_rate, + .round_rate = _clk_round_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR0, + .enable_shift = MXC_CCM_CGR0_ESDHC3_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk fec_clk = { + .name = "fec_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_FEC_OFFSET, + .disable = _clk_disable, +}; + +static struct clk gpt_clk = { + .name = "gpt_clk", + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_GPT_OFFSET, + .disable = _clk_disable, +}; + +static struct clk i2c_clk[] = { + { + .name = "i2c_clk", + .id = 0, + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_I2C1_OFFSET, + .disable = _clk_disable,}, + { + .name = "i2c_clk", + .id = 1, + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_I2C2_OFFSET, + .disable = _clk_disable,}, + { + .name = "i2c_clk", + .id = 2, + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_I2C3_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk ipu_clk = { + .name = "ipu_clk", + .parent = &cpu_clk, + .recalc = _clk_hsp_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_IPU_OFFSET, + .disable = _clk_disable, +}; + +static struct clk kpp_clk = { + .name = "kpp_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_KPP_OFFSET, + .disable = _clk_disable, +}; + +static struct clk mlb_clk = { + .name = "mlb_clk", + .parent = &ahb_clk, + .recalc = _clk_mlb_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_MLB_OFFSET, + .disable = _clk_disable, +}; + +static struct clk mstick_clk = { + .name = "mstick_clk", + .id = 0, + .parent = &peri_pll_clk, + .recalc = _clk_mstick1_recalc, + .set_rate = _clk_mstick1_set_rate, + .round_rate = _clk_per_post_round_rate, + .set_parent = _clk_mstick1_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_MSHC_OFFSET, + .disable = _clk_disable, +}; + +static struct clk owire_clk = { + .name = "owire_clk", + .parent = &perclk_clk, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_OWIRE_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk pwm_clk = { + .name = "pwm_clk", + .parent = &perclk_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_PWM_OFFSET, + .disable = _clk_disable, +}; + +static struct clk rng_clk = { + .name = "rng_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR1, + .enable_shift = MXC_CCM_CGR1_RNGC_OFFSET, + .disable = _clk_disable, +}; + +static struct clk rtc_clk = { + .name = "rtc_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_RTC_OFFSET, + .disable = _clk_disable, +}; + +static struct clk rtic_clk = { + .name = "rtic_clk", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_RTIC_OFFSET, + .disable = _clk_disable, +}; + +static struct clk scc_clk = { + .name = "scc_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_SCC_OFFSET, + .disable = _clk_disable, +}; + +static struct clk sdma_clk[] = { + { + .name = "sdma_ahb_clk", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_SDMA_OFFSET, + .disable = _clk_disable,}, + { + .name = "sdma_ipg_clk", + .parent = &ipg_clk,} +}; + +static struct clk spba_clk = { + .name = "spba_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_SPBA_OFFSET, + .disable = _clk_disable, +}; + +static struct clk spdif_clk[] = { + { + .name = "spdif_clk", + .parent = &peri_pll_clk, + .recalc = _clk_spdif_recalc, + .set_rate = _clk_spdif_set_rate, + .round_rate = _clk_per_post_round_rate, + .set_parent = _clk_spdif_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_SPDIF_OFFSET, + .disable = _clk_disable,}, + { + .name = "spdif_audio_clk", + .parent = &ckie_clk,}, + { + .name = "spdif_ipg_clk", + .parent = &ipg_clk,}, +}; + +static struct clk ssi_clk[] = { + { + .name = "ssi_clk", + .parent = &peri_pll_clk, + .recalc = _clk_ssi_recalc, + .set_rate = _clk_ssi_set_rate, + .round_rate = _clk_per_post_round_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_SSI1_OFFSET, + .disable = _clk_disable,}, + { + .name = "ssi_clk", + .id = 1, + .parent = &peri_pll_clk, + .recalc = _clk_ssi_recalc, + .set_rate = _clk_ssi_set_rate, + .round_rate = _clk_per_post_round_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_SSI2_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk uart_clk[] = { + { + .name = "uart_clk", + .id = 0, + .parent = &uart_per_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_UART1_OFFSET, + .disable = _clk_disable,}, + { + .name = "uart_clk", + .id = 1, + .parent = &uart_per_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_UART2_OFFSET, + .disable = _clk_disable,}, + { + .name = "uart_clk", + .id = 2, + .parent = &uart_per_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_UART3_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk usb_clk[] = { + { + .name = "usb_clk", + .parent = &peri_pll_clk, + .recalc = _clk_usb_recalc, + .round_rate = _clk_round_rate, + .set_rate = _clk_usb_set_rate,}, + { + .name = "usb_ahb_clk", + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_USBOTG_OFFSET, + .disable = _clk_disable,}, +}; + +static struct clk wdog_clk = { + .name = "wdog_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR2, + .enable_shift = MXC_CCM_CGR2_WDOG_OFFSET, + .disable = _clk_disable, +}; + +static struct clk csi_clk = { + .name = "csi_clk", + .parent = &peri_pll_clk, + .recalc = _clk_csi_recalc, + .round_rate = _clk_round_rate, + .set_rate = _clk_csi_set_rate, + .set_parent = _clk_csi_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR3, + .enable_shift = MXC_CCM_CGR3_CSI_OFFSET, + .disable = _clk_disable, +}; + +static struct clk iim_clk = { + .name = "iim_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CGR3, + .enable_shift = MXC_CCM_CGR3_IIM_OFFSET, + .disable = _clk_disable, +}; + +static struct clk nfc_clk = { + .name = "nfc_clk", + .parent = &ahb_clk, + .recalc = _clk_nfc_recalc, +}; + +static unsigned long _clk_cko1_round_rate(struct clk *clk, unsigned long rate) +{ + u32 div = 0, div1 = 1; + + div = clk->parent->rate / rate; + if (clk->parent->rate % rate) + div++; + + if (div > 64) { + div = (div + 1) >> 1; + div1++; + } + + if (div > 128) + div = 64; + return clk->parent->rate / (div * div1); +} + +static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div, div1 = 0; + u32 prdf, podf; + + div = clk->parent->rate / rate; + if ((clk->parent->rate / div) != rate) + return -EINVAL; + if (div > 64) { + div1 = MXC_CCM_COSR_CLKOUTDIV_1; + div >>= 1; + } else { + div1 = 0; + } + + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) { + __calc_two_dividers(div, &prdf, &podf); + reg = __raw_readl(MXC_CCM_COSR) & + ~(MXC_CCM_COSR_CLKOUT_PREDIV_MASK | + MXC_CCM_COSR_CLKOUT_PRODIV_MASK | + MXC_CCM_COSR_CLKOUTDIV_1); + reg |= ((prdf - 1) << MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET) + | ((podf - 1) << MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET) + | div1; + } else { + reg = __raw_readl(MXC_CCM_COSR) & + ~(MXC_CCM_COSR_CLKOUT_PRODIV_MASK_V2 | + MXC_CCM_COSR_CLKOUTDIV_1); + reg |= ((div - 1) << MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET) | div1; + } + __raw_writel(reg, MXC_CCM_COSR); + + return 0; +} + +static void _clk_cko1_recalc(struct clk *clk) +{ + u32 prdf = 0; + u32 podf, div1; + u32 reg = __raw_readl(MXC_CCM_COSR); + + div1 = 1 << ((reg & MXC_CCM_COSR_CLKOUTDIV_1) != 0); + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) { + prdf = (reg & MXC_CCM_COSR_CLKOUT_PREDIV_MASK) >> + MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET; + podf = (reg & MXC_CCM_COSR_CLKOUT_PRODIV_MASK) >> + MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET; + } else + podf = (reg & MXC_CCM_COSR_CLKOUT_PRODIV_MASK_V2) >> + MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET; + + clk->rate = clk->parent->rate / (div1 * (podf + 1) * (prdf + 1)); +} + +static int _clk_cko1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOSEL_MASK; + + if (parent == &ckil_clk) { + reg &= ~MXC_CCM_COSR_CKIL_CKIH_MASK; + reg |= 0 << MXC_CCM_COSR_CLKOSEL_OFFSET; + } else if (parent == &ckih_clk) { + reg |= 1 << MXC_CCM_COSR_CLKOSEL_OFFSET; + } else if (parent == &ckie_clk) + reg |= 2 << MXC_CCM_COSR_CLKOSEL_OFFSET; + else if (parent == &peri_pll_clk) + reg |= 6 << MXC_CCM_COSR_CLKOSEL_OFFSET; + else if (parent == &cpu_clk) + reg |= 7 << MXC_CCM_COSR_CLKOSEL_OFFSET; + else if (parent == &ahb_clk) + reg |= 8 << MXC_CCM_COSR_CLKOSEL_OFFSET; + else if (parent == &ipg_clk) + reg |= 9 << MXC_CCM_COSR_CLKOSEL_OFFSET; + else if (parent == &usb_clk[1]) + reg |= 0xB << MXC_CCM_COSR_CLKOSEL_OFFSET; + else if (parent == &sdhc_clk[1]) + reg |= 0xC << MXC_CCM_COSR_CLKOSEL_OFFSET; + else if (parent == &ssi_clk[1]) + reg |= 0xD << MXC_CCM_COSR_CLKOSEL_OFFSET; + else if (parent == &mlb_clk) + reg |= 0xE << MXC_CCM_COSR_CLKOSEL_OFFSET; + else if (parent == &csi_clk) + reg |= 0x11 << MXC_CCM_COSR_CLKOSEL_OFFSET; + else if (parent == &spdif_clk[0]) + reg |= 0x12 << MXC_CCM_COSR_CLKOSEL_OFFSET; + else if (parent == &uart_clk[0]) + reg |= 0x13 << MXC_CCM_COSR_CLKOSEL_OFFSET; + else if (parent == &asrc_clk[1]) + reg |= 0x14 << MXC_CCM_COSR_CLKOSEL_OFFSET; + else if ((parent == &nfc_clk) && (cpu_is_mx35_rev(CHIP_REV_2_0) >= 1)) + reg |= 0x17 << MXC_CCM_COSR_CLKOSEL_OFFSET; + else if ((parent == &ipu_clk) && (cpu_is_mx35_rev(CHIP_REV_2_0) >= 1)) + reg |= 0x18 << MXC_CCM_COSR_CLKOSEL_OFFSET; + else + return -EINVAL; + + __raw_writel(reg, MXC_CCM_COSR); + return 0; +} + +static int _clk_cko1_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_COSR) | MXC_CCM_COSR_CLKOEN; + __raw_writel(reg, MXC_CCM_COSR); + + return 0; +} + +static void _clk_cko1_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOEN; + __raw_writel(reg, MXC_CCM_COSR); +} + +static struct clk cko1_clk = { + .name = "cko1_clk", + .recalc = _clk_cko1_recalc, + .set_rate = _clk_cko1_set_rate, + .round_rate = _clk_cko1_round_rate, + .set_parent = _clk_cko1_set_parent, + .enable = _clk_cko1_enable, + .disable = _clk_cko1_disable, +}; + +static struct clk *mxc_clks[] = { + &int_32k_clk, + &ext_32k_clk, + &ckih_clk, + &ckil_clk, + &ckie_clk, + &mcu_pll_clk, + &peri_pll_clk, + &cpu_clk, + &ahb_clk, + &ipg_clk, + &perclk_clk, + &uart_per_clk, + &asrc_clk[0], + &asrc_clk[1], + &ata_clk, + &can_clk[0], + &can_clk[1], + &cspi_clk[0], + &cspi_clk[1], + &ect_clk, + &emi_clk, + &epit_clk[0], + &epit_clk[1], + &esai_clk, + &sdhc_clk[0], + &sdhc_clk[1], + &sdhc_clk[2], + &fec_clk, + &gpt_clk, + &i2c_clk[0], + &i2c_clk[1], + &i2c_clk[2], + &ipu_clk, + &kpp_clk, + &mlb_clk, + &mstick_clk, + &owire_clk, + &rng_clk, + &pwm_clk, + &rtc_clk, + &rtic_clk, + &scc_clk, + &sdma_clk[0], + &sdma_clk[1], + &spba_clk, + &spdif_clk[0], + &spdif_clk[1], + &spdif_clk[2], + &ssi_clk[0], + &ssi_clk[1], + &uart_clk[0], + &uart_clk[1], + &uart_clk[2], + &usb_clk[0], + &usb_clk[1], + &wdog_clk, + &csi_clk, + &iim_clk, + &nfc_clk, + &cko1_clk, +}; + +extern void propagate_rate(struct clk *tclk); + +static void mxc_clockout_scan(void) +{ + u32 reg = __raw_readl(MXC_CCM_COSR) & MXC_CCM_COSR_CLKOSEL_MASK; + reg >>= MXC_CCM_COSR_CLKOSEL_OFFSET; + switch (reg) { + case 0: + cko1_clk.parent = &ckil_clk; + break; + case 1: + cko1_clk.parent = &ckih_clk; + break; + case 2: + cko1_clk.parent = &ckie_clk; + break; + case 6: + cko1_clk.parent = &peri_pll_clk; + break; + case 7: + cko1_clk.parent = &cpu_clk; + break; + case 8: + cko1_clk.parent = &ahb_clk; + break; + case 9: + cko1_clk.parent = &ipg_clk; + break; + case 0xB: + cko1_clk.parent = &usb_clk[1]; + break; + case 0xC: + cko1_clk.parent = &sdhc_clk[1]; + break; + case 0xD: + cko1_clk.parent = &ssi_clk[1]; + break; + case 0xE: + cko1_clk.parent = &mlb_clk; + break; + case 0x11: + cko1_clk.parent = &csi_clk; + break; + case 0x12: + cko1_clk.parent = &spdif_clk[0]; + break; + case 0x13: + cko1_clk.parent = &uart_clk[0]; + break; + case 0x14: + cko1_clk.parent = &asrc_clk[1]; + break; + case 0x17: + cko1_clk.parent = &nfc_clk; + break; + case 0x18: + cko1_clk.parent = &ipu_clk; + break; + } +} + +static void mxc_update_clocks(void) +{ + unsigned long reg; + reg = __raw_readl(MXC_CCM_PDR0); + if ((!(reg & MXC_CCM_PDR0_AUTO_CON)) + && (cpu_is_mx35_rev(CHIP_REV_2_0) < 1)) + ipu_clk.parent = &ahb_clk; + + if (reg & MXC_CCM_PDR0_PER_SEL) + perclk_clk.parent = &cpu_clk; + + reg = __raw_readl(MXC_CCM_PDR1); + if (reg & MXC_CCM_PDR1_MSHC_M_U) + mstick_clk.parent = &cpu_clk; + + reg = __raw_readl(MXC_CCM_PDR2); + if (reg & MXC_CCM_PDR2_CSI_M_U) + csi_clk.parent = &cpu_clk; + if (reg & MXC_CCM_PDR2_SSI_M_U) { + ssi_clk[0].parent = &cpu_clk; + ssi_clk[1].parent = &cpu_clk; + } + + reg = __raw_readl(MXC_CCM_PDR3); + if (reg & MXC_CCM_PDR3_SPDIF_M_U) + spdif_clk[0].parent = &cpu_clk; + + if (reg & MXC_CCM_PDR3_UART_M_U) + uart_per_clk.parent = &cpu_clk; + + if (reg & MXC_CCM_PDR3_ESDHC_M_U) { + sdhc_clk[0].parent = &cpu_clk; + sdhc_clk[1].parent = &cpu_clk; + sdhc_clk[2].parent = &cpu_clk; + } + + reg = __raw_readl(MXC_CCM_PDR4); + if (reg & MXC_CCM_PDR4_USB_M_U) + usb_clk[0].parent = &cpu_clk; + + mxc_clockout_scan(); +} + +/* + * Based on the MX35 Reference Manual, the SLAVE port can + * be put into a low power mode when IDLE. These are + * bits 5 and 4 in the SGPCR register + */ +#define MXC_MAX_SLAVE_LOW_POWER 0x20 + +int __init mxc_clocks_init(void) +{ + unsigned int reg = 0; + struct clk **clkp; + unsigned int ll = 0; + + /* + * Put the SLAVE ports into low power Parking mode. PCTL bits in + * SGCPR register + */ + __raw_writel(MXC_MAX_SLAVE_LOW_POWER, MXC_MAX_SGPCR_0); + __raw_writel(MXC_MAX_SLAVE_LOW_POWER, MXC_MAX_SGPCR_1); + __raw_writel(MXC_MAX_SLAVE_LOW_POWER, MXC_MAX_SGPCR_2); + __raw_writel(MXC_MAX_SLAVE_LOW_POWER, MXC_MAX_SGPCR_3); + __raw_writel(MXC_MAX_SLAVE_LOW_POWER, MXC_MAX_SGPCR_4); + + for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) + clk_register(*clkp); + +#ifdef CONFIG_DEBUG_LL_EARLY_CONSOLE + ll = MXC_CCM_CGR2_UART1_MASK; +#endif + /* Turn off all possible clocks */ + __raw_writel(MXC_CCM_CGR0_ECT_MASK | MXC_CCM_CGR0_EMI_MASK, + MXC_CCM_CGR0); + __raw_writel(MXC_CCM_CGR1_GPIO1_MASK | MXC_CCM_CGR1_GPIO2_MASK | + MXC_CCM_CGR1_GPIO3_MASK | MXC_CCM_CGR1_GPT_MASK | + MXC_CCM_CGR1_IOMUXC_MASK, MXC_CCM_CGR1); + __raw_writel(MXC_CCM_CGR2_MAX_MASK | MXC_CCM_CGR2_SPBA_MASK | + MXC_CCM_CGR2_AUDMUX_MASK | MXC_CCM_CGR2_MAX_ENABLE | ll, + MXC_CCM_CGR2); + __raw_writel(MXC_CCM_CGR3_IIM_MASK, MXC_CCM_CGR3); + + __raw_writel((__raw_readl(MXC_CCM_PMCR2) | + MXC_CCM_PMCR2_OSC24M_DOWN | + MXC_CCM_PMCR2_OSC_AUDIO_DOWN), MXC_CCM_PMCR2); + + /* + * Set the parent/speed of cko1 + */ + reg = __raw_readl(MXC_CCM_COSR); + reg &= 0xffff03ff; + __raw_writel(reg, MXC_CCM_COSR); + + reg = __raw_readl(MXC_CCM_COSR); + reg &= 0xffffffa0; + reg |= 0x1; + __raw_writel(reg, MXC_CCM_COSR); + + mxc_update_clocks(); + + /* This will propagate to all children and init all the clock rates */ + propagate_rate(&ckih_clk); + propagate_rate(&ext_32k_clk); + propagate_rate(&ckie_clk); + + clk_enable(&mcu_pll_clk); + clk_enable(&gpt_clk); + clk_enable(&emi_clk); + clk_enable(&iim_clk); + clk_enable(&spba_clk); + + /* Init serial PLL according */ + clk_set_rate(&peri_pll_clk, 300000000); + + clk_enable(&peri_pll_clk); + + /* + * Reduce the speed of the MSHC clock as it is + * unused. Increase the pre (bits 28-30) and post + * dividers (bits 22-27) in the PDR1 + */ + reg = __raw_readl(MXC_CCM_PDR1); + reg |= 0x7fc00000; + __raw_writel(reg, MXC_CCM_PDR1); + + /* + * Reduce the speeds of the CSI and SSI2 clocks as it + * is unused. + */ + reg = __raw_readl(MXC_CCM_PDR2); + reg |= 0x383f3f00; + __raw_writel(reg, MXC_CCM_PDR2); + + reg = __raw_readl(MXC_CCM_RCSR); + printk(KERN_INFO "MX35 Reset Control and Status Register: 0x%x\n", reg); + + return 0; +} + +/*! + * Function to get timer clock rate early in boot process before clock tree is + * initialized. + * + * @return Clock rate for timer + */ +unsigned long __init clk_early_get_timer_rate(void) +{ + /* Determine which high frequency clock source is coming in */ + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + sync_cpu_wb(); + mcu_pll_clk.recalc(&mcu_pll_clk); + + /* Set the mcu_pll to 512 MHz */ + _clk_pll_set_rate(&mcu_pll_clk, 512000000); + + cpu_clk.recalc(&cpu_clk); + ahb_clk.recalc(&ahb_clk); + ipg_clk.recalc(&ipg_clk); + perclk_clk.recalc(&perclk_clk); + return perclk_clk.rate; +} + +#ifdef CONFIG_DEBUG_FS + +int mx35_show_registers(struct seq_file *s) +{ + int t = 0; + + t += seq_printf(s, "CCMR: 0x%x\n", __raw_readl(MXC_CCM_CCMR)); + t += seq_printf(s, "RCSR: 0x%x\n", __raw_readl(MXC_CCM_RCSR)); + + t += seq_printf(s, "PDR0: 0x%x\n", __raw_readl(MXC_CCM_PDR0)); + t += seq_printf(s, "PDR1: 0x%x\n", __raw_readl(MXC_CCM_PDR1)); + t += seq_printf(s, "PDR2: 0x%x\n", __raw_readl(MXC_CCM_PDR2)); + t += seq_printf(s, "PDR3: 0x%x\n", __raw_readl(MXC_CCM_PDR3)); + t += seq_printf(s, "PDR4: 0x%x\n", __raw_readl(MXC_CCM_PDR4)); + + t += seq_printf(s, "MPCTL: 0x%x\n", __raw_readl(MXC_CCM_MPCTL)); + + t += seq_printf(s, "CGR0: 0x%x\n", __raw_readl(MXC_CCM_CGR0)); + t += seq_printf(s, "CGR1: 0x%x\n", __raw_readl(MXC_CCM_CGR1)); + t += seq_printf(s, "CGR2: 0x%x\n", __raw_readl(MXC_CCM_CGR2)); + t += seq_printf(s, "CGR3: 0x%x\n", __raw_readl(MXC_CCM_CGR3)); + + t += seq_printf(s, "PMCR0: 0x%x\n", __raw_readl(MXC_CCM_PMCR0)); + t += seq_printf(s, "PMCR1: 0x%x\n", __raw_readl(MXC_CCM_PMCR1)); + t += seq_printf(s, "PMCR2: 0x%x\n", __raw_readl(MXC_CCM_PMCR2)); + + t += seq_printf(s, "COSR: 0x%x\n", __raw_readl(MXC_CCM_COSR)); + + return 0; +} +EXPORT_SYMBOL(mx35_show_registers); + +#endif diff -urN linux-2.6.26/arch/arm/mach-mx35/cpu.c linux-2.6.26-lab126/arch/arm/mach-mx35/cpu.c --- linux-2.6.26/arch/arm/mach-mx35/cpu.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/cpu.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,80 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mach-mx35/cpu.c + * + * @brief This file contains the CPU initialization code. + * + * @ingroup MSL_MX35 + */ + +#include +#include +#include +#include +#include +#include + +/*! + * CPU initialization. It is called by fixup_mxc_board() + */ +void __init mxc_cpu_init(void) +{ + + /* Setup Peripheral Port Remap register for AVIC */ + asm("ldr r0, =0xC0000015 \n\ + mcr p15, 0, r0, c15, c2, 4"); + /*TODO:Add code to check chip version */ + + mxc_set_system_rev(0x35, CHIP_REV_2_0); +} + +/*! + * Post CPU init code + * + * @return 0 always + */ +static int __init post_cpu_init(void) +{ + void *l2_base; + unsigned long aips_reg; + + /* Initialize L2 cache */ + l2_base = ioremap(L2CC_BASE_ADDR, SZ_4K); + if (l2_base) + l2x0_init(l2_base, 0x00030024, 0x00000000); + + /* + * S/W workaround: Clear the off platform peripheral modules + * Supervisor Protect bit for SDMA to access them. + */ + __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x40)); + __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x44)); + __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x48)); + __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x4C)); + aips_reg = __raw_readl(IO_ADDRESS(AIPS1_BASE_ADDR + 0x50)); + aips_reg &= 0x00FFFFFF; + __raw_writel(aips_reg, IO_ADDRESS(AIPS1_BASE_ADDR + 0x50)); + __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x40)); + __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x44)); + __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x48)); + __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x4C)); + aips_reg = __raw_readl(IO_ADDRESS(AIPS2_BASE_ADDR + 0x50)); + aips_reg &= 0x00FFFFFF; + __raw_writel(aips_reg, IO_ADDRESS(AIPS2_BASE_ADDR + 0x50)); + + return 0; +} + +postcore_initcall(post_cpu_init); diff -urN linux-2.6.26/arch/arm/mach-mx35/cpufreq.c linux-2.6.26-lab126/arch/arm/mach-mx35/cpufreq.c --- linux-2.6.26/arch/arm/mach-mx35/cpufreq.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/cpufreq.c 2010-08-11 00:35:00.000000000 -0400 @@ -0,0 +1,306 @@ +/* + * cpufreq.c -- MX35 CPUfreq driver. + * MX35 cpufreq driver + * + * Copyright 2009 Lab126, Inc. All rights reserved. + * Manish Lachwani (lachwani@lab126.com) + * + * Support for CPUFreq on the Luigi. It supports two operating points: + * 256MHz and 512MHz. Along with the CPU Frequency scaling, the voltage + * is also adjusted to be 1.25V (256MHz) or 1.4V (512MHz). + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "crm_regs.h" + +static struct clk *cpu_clk; +static struct regulator *core_regulator; + +char *core_reg_id = "SW2"; + +int cpufreq_suspended = 0; +EXPORT_SYMBOL(cpufreq_suspended); + +#define MAX_CPU_FREQUENCY 512000000 /* MAX speed of the CPU */ + +DEFINE_RAW_SPINLOCK(cpufreq_lock); + +#define MXC_PERCLK_DIVIDER 0x1000 +#define MX35_CPU_MIN_FREQ 256000 +#define MX35_CPU_MAX_FREQ 512000 + +/* + * Use one PMIC call to set the SW2 and SW2_DVS voltage levels. We + * don't want to use the regulator_* functions as it issues multiple PMIC call + * and causes unnecessary SPI traffic. + * + * SW2 and SW2_DVS min voltage of 1.25V and max voltage of 1.4V. + * Bits 0-9 in Register 25 + */ +#define MX35_CPU_MIN_VOLTAGE 0xC6 /* 1.25V */ +#define MX35_CPU_MAX_VOLTAGE 0x1CE /* 1.4V */ + +/* Bits 0-9 mask for register 25 */ +#define SW2_VOLTAGE_MASK 0x3ff + +#define MX35_VPLL_MIN_VOLTAGE 0x1 /* 1.25 V */ +#define MX35_VPLL_MAX_VOLTAGE 0x2 /* 1.5V */ +#define MX35_VPLL_VOLTAGE_MASK 0x3 /* Bits 9 and 10 */ +#define MX35_VPLL_LSH 9 + +/* Check if SW2HI is set or not */ +extern void mx35_check_sw2hi_bit(void); + +/* + * turn debug on/off + */ +#undef MX35_CPU_FREQ_DEBUG + +static struct cpufreq_frequency_table mx35_freq_table_con[] = { + {0x01, MX35_CPU_MIN_FREQ}, + {0x02, MX35_CPU_MAX_FREQ}, + {0, CPUFREQ_TABLE_END}, +}; + +static int mx35_verify_speed(struct cpufreq_policy *policy) +{ + if (policy->cpu != 0) + return -EINVAL; + + return cpufreq_frequency_table_verify(policy, mx35_freq_table_con); +} + +static unsigned int mx35_get_speed(unsigned int cpu) +{ + if (cpu) + return 0; + return clk_get_rate(cpu_clk) / 1000; +} + +static int calc_frequency_con(int target, unsigned int relation) +{ + int i = 0; + + if (relation == CPUFREQ_RELATION_H) { + for (i = 1; i >= 0; i--) { + if (mx35_freq_table_con[i].frequency <= target) + return mx35_freq_table_con[i].frequency; + } + } else if (relation == CPUFREQ_RELATION_L) { + for (i = 0; i <= 1; i++) { + if (mx35_freq_table_con[i].frequency >= target) + return mx35_freq_table_con[i].frequency; + } + } + printk(KERN_ERR "Error: No valid cpufreq relation\n"); + return MX35_CPU_MAX_FREQ; +} + +/* + * Set the destination CPU frequency target + */ +int set_cpu_freq(int freq) +{ + if (freq == MX35_CPU_MIN_FREQ * 1000) + CHECK_ERROR(pmic_write_reg(REG_SW_1, MX35_CPU_MIN_VOLTAGE, SW2_VOLTAGE_MASK)); + else + CHECK_ERROR(pmic_write_reg(REG_SW_1, MX35_CPU_MAX_VOLTAGE, SW2_VOLTAGE_MASK)); + + udelay(20); /* 20 us for the stepping to finish up */ + +#ifdef MX35_CPU_FREQ_DEBUG + printk ("ARM frequency: %dHz\n", (int)clk_get_rate(cpu_clk)); +#endif + clk_set_rate(cpu_clk, freq); + +#ifdef MX35_CPU_FREQ_DEBUG + printk ("ARM frequency after change: %dHz\n", (int)clk_get_rate(cpu_clk)); +#endif + clk_put(cpu_clk); + return 0; +} +EXPORT_SYMBOL(set_cpu_freq); + +/* + * Set the destination CPU frequency target + */ +static int mx35_set_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + struct cpufreq_freqs freqs; + long freq; + int orig_cpu_rate = clk_get_rate(cpu_clk); + int ret = 0; + + if (cpufreq_suspended) + return ret; + + if (target_freq < policy->cpuinfo.min_freq) + target_freq = policy->cpuinfo.min_freq; + + if (target_freq < policy->min) + target_freq = policy->min; + + freq = calc_frequency_con(target_freq, relation) * 1000; + freqs.old = clk_get_rate(cpu_clk) / 1000; + freqs.new = (freq + 500) / 1000; + freqs.cpu = 0; + freqs.flags = 0; + + if (freq == orig_cpu_rate) + return 0; + + if (freq == MX35_CPU_MIN_FREQ * 1000) + pmic_write_reg(REG_SW_1, MX35_CPU_MIN_VOLTAGE, SW2_VOLTAGE_MASK); + else + pmic_write_reg(REG_SW_1, MX35_CPU_MAX_VOLTAGE, SW2_VOLTAGE_MASK); + + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + +#ifdef MX35_CPU_FREQ_DEBUG + printk ("ARM frequency: %dHz\n", (int)clk_get_rate(cpu_clk)); +#endif + /* + * MCU clk + */ + clk_set_rate(cpu_clk, freq); + +#ifdef MX35_CPU_FREQ_DEBUG + printk ("ARM frequency after change: %dHz\n", (int)clk_get_rate(cpu_clk)); +#endif + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + clk_put(cpu_clk); + return ret; +} + +/*! + * Disable CPUFReq now that a charger has been detected + */ +void disable_cpufreq(void) +{ + struct cpufreq_freqs freqs; + int org_freq = clk_get_rate(cpu_clk); + + freqs.old = org_freq / 1000; + freqs.new = MAX_CPU_FREQUENCY / 1000; + freqs.cpu = 0; + freqs.flags = 0; + + cpufreq_suspended = 1; + + if (clk_get_rate(cpu_clk) != MAX_CPU_FREQUENCY) { + set_cpu_freq(MAX_CPU_FREQUENCY); + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + } +} +EXPORT_SYMBOL(disable_cpufreq); + +/*! + * Re-enable CPUFreq now that the charger is removed + */ +void enable_cpufreq(void) +{ + cpufreq_suspended = 0; +} +EXPORT_SYMBOL(enable_cpufreq); + +/* + * Driver initialization + */ +static int __init mx35_cpufreq_driver_init(struct cpufreq_policy *policy) +{ + int ret = 0; + + printk("Luigi/Freescale MX35 CPUFREQ driver\n"); + + if (policy->cpu != 0) + return -EINVAL; + + cpu_clk = clk_get(NULL, "cpu_clk"); + + if (IS_ERR(cpu_clk)) + return PTR_ERR(cpu_clk); + + policy->cur = policy->min = policy->max = + clk_get_rate(cpu_clk) / 1000; + policy->governor = CPUFREQ_DEFAULT_GOVERNOR; + policy->cpuinfo.min_freq = MX35_CPU_MIN_FREQ; + policy->cpuinfo.max_freq = MX35_CPU_MAX_FREQ; + + /* Set the transition latency to 50 us */ + policy->cpuinfo.transition_latency = 5 * 10000; + + ret = cpufreq_frequency_table_cpuinfo(policy, mx35_freq_table_con); + + if (ret < 0) + return ret; + + clk_put(cpu_clk); + cpufreq_frequency_table_get_attr(mx35_freq_table_con, policy->cpu); + + core_regulator = regulator_get(NULL, core_reg_id); + if (IS_ERR(core_regulator)) { + printk(KERN_ERR "%s: failed to get core regulator\n", __func__); + return PTR_ERR(core_regulator); + } + + /* Change the stepping on SW2 to 25mV every 2 us */ + pmic_write_reg(REG_SW_4, (0x0 << 16), (0x3 << 16)); + + return 0; +} + +static int mx35_cpufreq_driver_exit(struct cpufreq_policy *policy) +{ + cpufreq_frequency_table_put_attr(policy->cpu); + clk_set_rate(cpu_clk, MX35_CPU_MAX_FREQ * 1000); + + clk_put(cpu_clk); + regulator_put(core_regulator, NULL); + return 0; +} + +static struct cpufreq_driver mx35_driver = { + .flags = CPUFREQ_STICKY, + .verify = mx35_verify_speed, + .target = mx35_set_target, + .get = mx35_get_speed, + .init = mx35_cpufreq_driver_init, + .exit = mx35_cpufreq_driver_exit, + .name = "MX35", +}; + +static int __init mx35_cpufreq_init(void) +{ + return cpufreq_register_driver(&mx35_driver); +} + +static void __exit mx35_cpufreq_exit(void) +{ + cpufreq_unregister_driver(&mx35_driver); +} + +module_init(mx35_cpufreq_init); +module_exit(mx35_cpufreq_exit); + +MODULE_AUTHOR("Manish Lachwani"); +MODULE_DESCRIPTION("MX35 Luigi CPUFreq Driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/mach-mx35/crm_regs.h linux-2.6.26-lab126/arch/arm/mach-mx35/crm_regs.h --- linux-2.6.26/arch/arm/mach-mx35/crm_regs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/crm_regs.h 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,444 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ARCH_ARM_MACH_MX35_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MX35_CRM_REGS_H__ + +#define CKIH_CLK_FREQ 24000000 +#define CKIE_CLK_FREQ 24576000 +#define CKIL_CLK_FREQ 32000 +#define CKIL_EXT_FREQ 32768 + +#define MXC_CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) + +/* Register addresses */ +#define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00) +#define MXC_CCM_PDR0 (MXC_CCM_BASE + 0x04) +#define MXC_CCM_PDR1 (MXC_CCM_BASE + 0x08) +#define MXC_CCM_PDR2 (MXC_CCM_BASE + 0x0C) +#define MXC_CCM_PDR3 (MXC_CCM_BASE + 0x10) +#define MXC_CCM_PDR4 (MXC_CCM_BASE + 0x14) +#define MXC_CCM_RCSR (MXC_CCM_BASE + 0x18) +#define MXC_CCM_MPCTL (MXC_CCM_BASE + 0x1C) +#define MXC_CCM_PPCTL (MXC_CCM_BASE + 0x20) +#define MXC_CCM_ACMR (MXC_CCM_BASE + 0x24) +#define MXC_CCM_COSR (MXC_CCM_BASE + 0x28) +#define MXC_CCM_CGR0 (MXC_CCM_BASE + 0x2C) +#define MXC_CCM_CGR1 (MXC_CCM_BASE + 0x30) +#define MXC_CCM_CGR2 (MXC_CCM_BASE + 0x34) +#define MXC_CCM_CGR3 (MXC_CCM_BASE + 0x38) +#define MXC_CCM_RESV (MXC_CCM_BASE + 0x3C) +#define MXC_CCM_DCVR0 (MXC_CCM_BASE + 0x40) +#define MXC_CCM_DCVR1 (MXC_CCM_BASE + 0x44) +#define MXC_CCM_DCVR2 (MXC_CCM_BASE + 0x48) +#define MXC_CCM_DCVR3 (MXC_CCM_BASE + 0x4C) +#define MXC_CCM_LTR0 (MXC_CCM_BASE + 0x50) +#define MXC_CCM_LTR1 (MXC_CCM_BASE + 0x54) +#define MXC_CCM_LTR2 (MXC_CCM_BASE + 0x58) +#define MXC_CCM_LTR3 (MXC_CCM_BASE + 0x5C) +#define MXC_CCM_LTBR0 (MXC_CCM_BASE + 0x60) +#define MXC_CCM_LTBR1 (MXC_CCM_BASE + 0x64) +#define MXC_CCM_PMCR0 (MXC_CCM_BASE + 0x68) +#define MXC_CCM_PMCR1 (MXC_CCM_BASE + 0x6C) +#define MXC_CCM_PMCR2 (MXC_CCM_BASE + 0x70) + +/* Register bit definitions */ +#define MXC_CCM_CCMR_WFI (1 << 30) +#define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29) +#define MXC_CCM_CCMR_VSTBY (1 << 28) +#define MXC_CCM_CCMR_WBEN (1 << 27) +#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20 +#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) +#define MXC_CCM_CCMR_ROMW_OFFSET 18 +#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18) +#define MXC_CCM_CCMR_RAMW_OFFSET 21 +#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 21) +#define MXC_CCM_CCMR_LPM_OFFSET 14 +#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) +#define MXC_CCM_CCMR_UPE (1 << 9) +#define MXC_CCM_CCMR_MPE (1 << 3) + +#define MXC_CCM_PDR0_PER_SEL (1 << 26) +#define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23) +#define MXC_CCM_PDR0_HSP_PODF_OFFSET 20 +#define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20) +#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16 +#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) +#define MXC_CCM_PDR0_CKIL_SEL (1 << 15) +#define MXC_CCM_PDR0_PER_PODF_OFFSET 12 +#define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12) +#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 +#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9) +#define MXC_CCM_PDR0_AUTO_CON 0x1 + +#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28 +#define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28) +#define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22 +#define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22) +#define MXC_CCM_PDR1_MSHC_M_U (1 << 7) + +#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27 +#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) +#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24 +#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24) +#define MXC_CCM_PDR2_CSI_PRDF_OFFSET 19 +#define MXC_CCM_PDR2_CSI_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16 +#define MXC_CCM_PDR2_CSI_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 +#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) +#define MXC_CCM_PDR2_CSI_M_U (1 << 7) +#define MXC_CCM_PDR2_SSI_M_U (1 << 6) +#define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0 +#define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F) + +/* Extra definitions for Chip Version 2*/ +#define MXC_CCM_PDR2_CSI_PODF_MASK_V2 (0x3F << 16) + +#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29 +#define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29) +#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 +#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) +#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) +#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET 19 +#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 +#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR3_UART_M_U (1 << 15) +#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET 11 +#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK (0x7 << 11) +#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 +#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x7 << 8) +#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) +#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET 3 +#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK (0x7 << 3) +#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 +#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x7) + +/* Extra definitions for Chip Version 2 */ +#define MXC_CCM_PDR3_ESDHC3_PODF_MASK_V2 (0x3F << 16) +#define MXC_CCM_PDR3_ESDHC2_PODF_MASK_V2 (0x3F << 8) +#define MXC_CCM_PDR3_ESDHC1_PODF_MASK_V2 0x3F + +#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28 +#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28) +#define MXC_CCM_PDR4_USB_PRDF_OFFSET 25 +#define MXC_CCM_PDR4_USB_PRDF_MASK (0x7 << 25) +#define MXC_CCM_PDR4_USB_PODF_OFFSET 22 +#define MXC_CCM_PDR4_USB_PODF_MASK (0x7 << 22) +#define MXC_CCM_PDR4_PER0_PRDF_OFFSET 19 +#define MXC_CCM_PDR4_PER0_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16 +#define MXC_CCM_PDR4_PER0_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR4_UART_PRDF_OFFSET 13 +#define MXC_CCM_PDR4_UART_PRDF_MASK (0x7 << 13) +#define MXC_CCM_PDR4_UART_PODF_OFFSET 10 +#define MXC_CCM_PDR4_UART_PODF_MASK (0x7 << 10) +#define MXC_CCM_PDR4_USB_M_U (1 << 9) + +/* Extra definitions for Chip Version 2 */ +#define MXC_CCM_PDR4_USB_PODF_MASK_V2 (0x3F << 22) +#define MXC_CCM_PDR4_PER0_PODF_MASK_V2 (0x3F << 16) +#define MXC_CCM_PDR4_UART_PODF_MASK_V2 (0x3F << 10) + +/* Bit definitions for RCSR */ +#define MXC_CCM_RCSR_BUS_WIDTH (1 << 29) +#define MXC_CCM_RCSR_BUS_16BIT (1 << 29) +#define MXC_CCM_RCSR_PAGE_SIZE (3 << 27) +#define MXC_CCM_RCSR_PAGE_512 (0 << 27) +#define MXC_CCM_RCSR_PAGE_2K (1 << 27) +#define MXC_CCM_RCSR_PAGE_4K1 (2 << 27) +#define MXC_CCM_RCSR_PAGE_4K2 (3 << 27) +#define MXC_CCM_RCSR_SOFT_RESET (1 << 15) +#define MXC_CCM_RCSR_NF16B (1 << 14) +#define MXC_CCM_RCSR_NFC_4K (1 << 9) +#define MXC_CCM_RCSR_NFC_FMS (1 << 8) +#define MXC_CCM_RCSR_WDOG_TO (1 << 3) + +/* Bit definitions for both MCU, PERIPHERAL PLL control registers */ +#define MXC_CCM_PCTL_BRM 0x80000000 +#define MXC_CCM_PCTL_PD_OFFSET 26 +#define MXC_CCM_PCTL_PD_MASK (0xF << 26) +#define MXC_CCM_PCTL_MFD_OFFSET 16 +#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) +#define MXC_CCM_PCTL_MFI_OFFSET 10 +#define MXC_CCM_PCTL_MFI_MASK (0xF << 10) +#define MXC_CCM_PCTL_MFN_OFFSET 0 +#define MXC_CCM_PCTL_MFN_MASK 0x3FF + +/* Bit definitions for Audio clock mux register*/ +#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12 +#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12) +#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8 +#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8) +#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4 +#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4) +#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0 +#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0) + +/* Extra definitions for Version 2 */ +#define MXC_CCM_ACMR_CKILH_PODF0_OFFSET 16 +#define MXC_CCM_ACMR_CKILH_PODF1_OFFSET 19 +#define MXC_CCM_ACMR_CKILH_PODF2_OFFSET 22 +#define MXC_CCM_ACMR_CKILH_PODF3_OFFSET 25 +#define MXC_CCM_ACMR_CKILH_PODF_MASK 0x7 + +/* Bit definitions for Clock gating Register*/ +#define MXC_CCM_CGR0_ASRC_OFFSET 0 +#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0) +#define MXC_CCM_CGR0_ATA_OFFSET 2 +#define MXC_CCM_CGR0_ATA_MASK (0x3 << 2) +#define MXC_CCM_CGR0_CAN1_OFFSET 6 +#define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6) +#define MXC_CCM_CGR0_CAN2_OFFSET 8 +#define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8) +#define MXC_CCM_CGR0_CSPI1_OFFSET 10 +#define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10) +#define MXC_CCM_CGR0_CSPI2_OFFSET 12 +#define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12) +#define MXC_CCM_CGR0_ECT_OFFSET 14 +#define MXC_CCM_CGR0_ECT_MASK (0x3 << 14) +#define MXC_CCM_CGR0_EMI_OFFSET 18 +#define MXC_CCM_CGR0_EMI_MASK (0x3 << 18) +#define MXC_CCM_CGR0_EPIT1_OFFSET 20 +#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20) +#define MXC_CCM_CGR0_EPIT2_OFFSET 22 +#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22) +#define MXC_CCM_CGR0_ESAI_OFFSET 24 +#define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24) +#define MXC_CCM_CGR0_ESDHC1_OFFSET 26 +#define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26) +#define MXC_CCM_CGR0_ESDHC2_OFFSET 28 +#define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28) +#define MXC_CCM_CGR0_ESDHC3_OFFSET 30 +#define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30) + +#define MXC_CCM_CGR1_FEC_OFFSET 0 +#define MXC_CCM_CGR1_FEC_MASK (0x3 << 0) +#define MXC_CCM_CGR1_GPIO1_OFFSET 2 +#define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2) +#define MXC_CCM_CGR1_GPIO2_OFFSET 4 +#define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4) +#define MXC_CCM_CGR1_GPIO3_OFFSET 6 +#define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6) +#define MXC_CCM_CGR1_GPT_OFFSET 8 +#define MXC_CCM_CGR1_GPT_MASK (0x3 << 8) +#define MXC_CCM_CGR1_I2C1_OFFSET 10 +#define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10) +#define MXC_CCM_CGR1_I2C2_OFFSET 12 +#define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12) +#define MXC_CCM_CGR1_I2C3_OFFSET 14 +#define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14) +#define MXC_CCM_CGR1_IOMUXC_OFFSET 16 +#define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16) +#define MXC_CCM_CGR1_IPU_OFFSET 18 +#define MXC_CCM_CGR1_IPU_MASK (0x3 << 18) +#define MXC_CCM_CGR1_KPP_OFFSET 20 +#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) +#define MXC_CCM_CGR1_MLB_OFFSET 22 +#define MXC_CCM_CGR1_MLB_MASK (0x3 << 22) +#define MXC_CCM_CGR1_MSHC_OFFSET 24 +#define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24) +#define MXC_CCM_CGR1_OWIRE_OFFSET 26 +#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26) +#define MXC_CCM_CGR1_PWM_OFFSET 28 +#define MXC_CCM_CGR1_PWM_MASK (0x3 << 28) +#define MXC_CCM_CGR1_RNGC_OFFSET 30 +#define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30) + +#define MXC_CCM_CGR2_RTC_OFFSET 0 +#define MXC_CCM_CGR2_RTC_MASK (0x3 << 0) +#define MXC_CCM_CGR2_RTIC_OFFSET 2 +#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2) +#define MXC_CCM_CGR2_SCC_OFFSET 4 +#define MXC_CCM_CGR2_SCC_MASK (0x3 << 4) +#define MXC_CCM_CGR2_SDMA_OFFSET 6 +#define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6) +#define MXC_CCM_CGR2_SPBA_OFFSET 8 +#define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8) +#define MXC_CCM_CGR2_SPDIF_OFFSET 10 +#define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10) +#define MXC_CCM_CGR2_SSI1_OFFSET 12 +#define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12) +#define MXC_CCM_CGR2_SSI2_OFFSET 14 +#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14) +#define MXC_CCM_CGR2_UART1_OFFSET 16 +#define MXC_CCM_CGR2_UART1_MASK (0x3 << 16) +#define MXC_CCM_CGR2_UART2_OFFSET 18 +#define MXC_CCM_CGR2_UART2_MASK (0x3 << 18) +#define MXC_CCM_CGR2_UART3_OFFSET 20 +#define MXC_CCM_CGR2_UART3_MASK (0x3 << 20) +#define MXC_CCM_CGR2_USBOTG_OFFSET 22 +#define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22) +#define MXC_CCM_CGR2_WDOG_OFFSET 24 +#define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24) +#define MXC_CCM_CGR2_MAX_OFFSET 26 +#define MXC_CCM_CGR2_MAX_MASK (0x3 << 26) +#define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26) +#define MXC_CCM_CGR2_AUDMUX_OFFSET 30 +#define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30) + +#define MXC_CCM_CGR3_CSI_OFFSET 0 +#define MXC_CCM_CGR3_CSI_MASK (0x3 << 0) +#define MXC_CCM_CGR3_IIM_OFFSET 2 +#define MXC_CCM_CGR3_IIM_MASK (0x3 << 2) +#define MXC_CCM_CGR3_GPU2D_OFFSET 4 +#define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4) +/* + * LTR0 register offsets + */ +#define MXC_CCM_LTR0_DNTHR_OFFSET 16 +#define MXC_CCM_LTR0_DNTHR_MASK (0x3F << 16) +#define MXC_CCM_LTR0_UPTHR_OFFSET 22 +#define MXC_CCM_LTR0_UPTHR_MASK (0x3F << 22) +#define MXC_CCM_LTR0_DIV3CK_OFFSET 1 +#define MXC_CCM_LTR0_DIV3CK_MASK (0x3 << 1) + +/* + * LTR1 register offsets + */ +#define MXC_CCM_LTR1_PNCTHR_OFFSET 0 +#define MXC_CCM_LTR1_PNCTHR_MASK 0x3F +#define MXC_CCM_LTR1_UPCNT_OFFSET 6 +#define MXC_CCM_LTR1_UPCNT_MASK (0xFF << 6) +#define MXC_CCM_LTR1_DNCNT_OFFSET 14 +#define MXC_CCM_LTR1_DNCNT_MASK (0xFF << 14) +#define MXC_CCM_LTR1_LTBRSR_MASK 0x400000 +#define MXC_CCM_LTR1_LTBRSR_OFFSET 22 +#define MXC_CCM_LTR1_LTBRSR 0x400000 +#define MXC_CCM_LTR1_LTBRSH 0x800000 + +/* + * LTR2 bit definitions. x ranges from 0 for WSW9 to 6 for WSW15 + */ +#define MXC_CCM_LTR2_WSW_OFFSET(x) (11 + (x) * 3) +#define MXC_CCM_LTR2_WSW_MASK(x) (0x7 << MXC_CCM_LTR2_WSW_OFFSET((x))) +#define MXC_CCM_LTR2_EMAC_OFFSET 0 +#define MXC_CCM_LTR2_EMAC_MASK 0x1FF + +/* + * LTR3 bit definitions. x ranges from 0 for WSW0 to 8 for WSW8 + */ +#define MXC_CCM_LTR3_WSW_OFFSET(x) (5 + (x) * 3) +#define MXC_CCM_LTR3_WSW_MASK(x) (0x7 << MXC_CCM_LTR3_WSW_OFFSET((x))) + +#define DVSUP_TURBO 0 +#define DVSUP_HIGH 1 +#define DVSUP_MEDIUM 2 +#define DVSUP_LOW 3 +#define MXC_CCM_PMCR0_DVSUP_TURBO (DVSUP_TURBO << 28) +#define MXC_CCM_PMCR0_DVSUP_HIGH (DVSUP_HIGH << 28) +#define MXC_CCM_PMCR0_DVSUP_MEDIUM (DVSUP_MEDIUM << 28) +#define MXC_CCM_PMCR0_DVSUP_LOW (DVSUP_LOW << 28) +#define MXC_CCM_PMCR0_DVSUP_OFFSET 28 +#define MXC_CCM_PMCR0_DVSUP_MASK (0x3 << 28) +#define MXC_CCM_PMCR0_DVFS_UPDATE_FINISH 0x01000000 +#define MXC_CCM_PMCR0_DVFEV 0x00800000 +#define MXC_CCM_PMCR0_DVFIS 0x00400000 +#define MXC_CCM_PMCR0_LBMI 0x00200000 +#define MXC_CCM_PMCR0_LBFL 0x00100000 +#define MXC_CCM_PMCR0_LBCF_4 (0x0 << 18) +#define MXC_CCM_PMCR0_LBCF_8 (0x1 << 18) +#define MXC_CCM_PMCR0_LBCF_12 (0x2 << 18) +#define MXC_CCM_PMCR0_LBCF_16 (0x3 << 18) +#define MXC_CCM_PMCR0_LBCF_OFFSET 18 +#define MXC_CCM_PMCR0_LBCF_MASK (0x3 << 18) +#define MXC_CCM_PMCR0_PTVIS 0x00020000 +#define MXC_CCM_PMCR0_DVFS_START 0x00010000 +#define MXC_CCM_PMCR0_DVFS_START_MASK 0x1 << 16) +#define MXC_CCM_PMCR0_FSVAIM 0x00008000 +#define MXC_CCM_PMCR0_FSVAI_OFFSET 13 +#define MXC_CCM_PMCR0_FSVAI_MASK (0x3 << 13) +#define MXC_CCM_PMCR0_DPVCR 0x00001000 +#define MXC_CCM_PMCR0_DPVV 0x00000800 +#define MXC_CCM_PMCR0_WFIM 0x00000400 +#define MXC_CCM_PMCR0_DRCE3 0x00000200 +#define MXC_CCM_PMCR0_DRCE2 0x00000100 +#define MXC_CCM_PMCR0_DRCE1 0x00000080 +#define MXC_CCM_PMCR0_DRCE0 0x00000040 +#define MXC_CCM_PMCR0_DCR 0x00000020 +#define MXC_CCM_PMCR0_DVFEN 0x00000010 +#define MXC_CCM_PMCR0_PTVAIM 0x00000008 +#define MXC_CCM_PMCR0_PTVAI_OFFSET 1 +#define MXC_CCM_PMCR0_PTVAI_MASK (0x3 << 1) +#define MXC_CCM_PMCR0_DPTEN 0x00000001 + +#define MXC_CCM_PMCR1_DVGP_OFFSET 0 +#define MXC_CCM_PMCR1_DVGP_MASK (0xF) + +#define MXC_CCM_PMCR1_PLLRDIS (0x1 << 7) +#define MXC_CCM_PMCR1_EMIRQ_EN (0x1 << 8) + +/* PMCR2 Audio OSC */ +#define MXC_CCM_PMCR2_OSC24M_DOWN (1 << 16) +#define MXC_CCM_PMCR2_OSC_AUDIO_DOWN (1 << 17) + +#define MXC_CCM_DCVR_ULV_MASK (0x3FF << 22) +#define MXC_CCM_DCVR_ULV_OFFSET 22 +#define MXC_CCM_DCVR_LLV_MASK (0x3FF << 12) +#define MXC_CCM_DCVR_LLV_OFFSET 12 +#define MXC_CCM_DCVR_ELV_MASK (0x3FF << 2) +#define MXC_CCM_DCVR_ELV_OFFSET 2 + +#define MXC_CCM_PDR2_MST2_PDF_MASK (0x3F << 7) +#define MXC_CCM_PDR2_MST2_PDF_OFFSET 7 +#define MXC_CCM_PDR2_MST1_PDF_MASK 0x3F +#define MXC_CCM_PDR2_MST1_PDF_OFFSET 0 + +#define MXC_CCM_COSR_CLKOSEL_MASK 0x1F +#define MXC_CCM_COSR_CLKOSEL_OFFSET 0 +#define MXC_CCM_COSR_CLKOEN (1 << 5) +#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) +#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK (0x7 << 13) +#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET 13 +#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK (0x7 << 10) +#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET 10 +#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) +#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16 +#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18) +#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18 +#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20) +#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20 +#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22) +#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22 +#define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24) +#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26) +#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26 + +/* extra definitions for Version 2 */ +#define MXC_CCM_COSR_CKIL_CKIH_MASK (1 << 7) +#define MXC_CCM_COSR_CKIL_CKIH_OFFSET 7 +#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK_V2 (0x3F << 10) + +/* + * PMCR0 register offsets + */ +#define MXC_CCM_PMCR0_LBFL_OFFSET 20 +#define MXC_CCM_PMCR0_DFSUP0_OFFSET 30 +#define MXC_CCM_PMCR0_DFSUP1_OFFSET 31 + +/* + * PMCR2 register definitions + */ +#define MXC_CCM_PMCR2_OSC24M_DOWN (1 << 16) +#define MXC_CCM_PMCR2_OSC_AUDIO_DOWN (1 << 17) + +/* + * SGPCR registers + */ +#define MXC_MAX_SGPCR_0 IO_ADDRESS(MAX_BASE_ADDR + 0x010) +#define MXC_MAX_SGPCR_1 IO_ADDRESS(MAX_BASE_ADDR + 0x110) +#define MXC_MAX_SGPCR_2 IO_ADDRESS(MAX_BASE_ADDR + 0x210) +#define MXC_MAX_SGPCR_3 IO_ADDRESS(MAX_BASE_ADDR + 0x310) +#define MXC_MAX_SGPCR_4 IO_ADDRESS(MAX_BASE_ADDR + 0x410) + +#endif /* __ARCH_ARM_MACH_MX3_CRM_REGS_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx35/devices.c linux-2.6.26-lab126/arch/arm/mach-mx35/devices.c --- linux-2.6.26/arch/arm/mach-mx35/devices.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/devices.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,712 @@ +/* + * Copyright 2008-2009 Amazon.com All Rights Reserved. + * Manish Lachwani (lachwani@lab126.com) + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "iomux.h" +#include "sdma_script_code.h" +#include "sdma_script_code_v2.h" +#include "board-mx35_3stack.h" + +void mxc_sdma_get_script_info(sdma_script_start_addrs * sdma_script_addr) +{ + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) { + sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR; + sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1; + sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1; + sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1; + sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1; + + sdma_script_addr->mxc_sdma_firi_2_per_addr = -1; + sdma_script_addr->mxc_sdma_firi_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_per_2_firi_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_firi_addr = -1; + + sdma_script_addr->mxc_sdma_uart_2_per_addr = uart_2_per_ADDR; + sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_per_2_app_addr = per_2_app_ADDR; + sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR; + + sdma_script_addr->mxc_sdma_per_2_per_addr = p_2_p_ADDR; + + sdma_script_addr->mxc_sdma_uartsh_2_per_addr = + uartsh_2_per_ADDR; + sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr = + uartsh_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_per_2_shp_addr = per_2_shp_ADDR; + sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR; + + sdma_script_addr->mxc_sdma_ata_2_mcu_addr = ata_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_mcu_2_ata_addr = mcu_2_ata_ADDR; + + sdma_script_addr->mxc_sdma_app_2_per_addr = app_2_per_ADDR; + sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_shp_2_per_addr = shp_2_per_ADDR; + sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR; + + sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = -1; + + sdma_script_addr->mxc_sdma_spdif_2_mcu_addr = spdif_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_mcu_2_spdif_addr = mcu_2_spdif_ADDR; + + sdma_script_addr->mxc_sdma_asrc_2_mcu_addr = asrc__mcu_ADDR; + + sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1; + sdma_script_addr->mxc_sdma_ext_mem_2_ipu_addr = + ext_mem__ipu_ram_ADDR; + sdma_script_addr->mxc_sdma_descrambler_addr = -1; + + sdma_script_addr->mxc_sdma_start_addr = + (unsigned short *)sdma_code; + sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE; + sdma_script_addr->mxc_sdma_ram_code_start_addr = + RAM_CODE_START_ADDR; + } else { + sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR_V2; + sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1; + sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1; + sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1; + sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1; + + sdma_script_addr->mxc_sdma_firi_2_per_addr = -1; + sdma_script_addr->mxc_sdma_firi_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_per_2_firi_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_firi_addr = -1; + + sdma_script_addr->mxc_sdma_uart_2_per_addr = uart_2_per_ADDR_V2; + sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR_V2; + sdma_script_addr->mxc_sdma_per_2_app_addr = per_2_app_ADDR_V2; + sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR_V2; + + sdma_script_addr->mxc_sdma_per_2_per_addr = p_2_p_ADDR_V2; + + sdma_script_addr->mxc_sdma_uartsh_2_per_addr = + uartsh_2_per_ADDR_V2; + sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr = + uartsh_2_mcu_ADDR_V2; + sdma_script_addr->mxc_sdma_per_2_shp_addr = per_2_shp_ADDR_V2; + sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR_V2; + + sdma_script_addr->mxc_sdma_ata_2_mcu_addr = ata_2_mcu_ADDR_V2; + sdma_script_addr->mxc_sdma_mcu_2_ata_addr = mcu_2_ata_ADDR_V2; + + sdma_script_addr->mxc_sdma_app_2_per_addr = app_2_per_ADDR_V2; + sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR_V2; + sdma_script_addr->mxc_sdma_shp_2_per_addr = shp_2_per_ADDR_V2; + sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR_V2; + + sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = -1; + + sdma_script_addr->mxc_sdma_spdif_2_mcu_addr = + spdif_2_mcu_ADDR_V2; + sdma_script_addr->mxc_sdma_mcu_2_spdif_addr = + mcu_2_spdif_ADDR_V2; + + sdma_script_addr->mxc_sdma_asrc_2_mcu_addr = asrc__mcu_ADDR_V2; + + sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1; + sdma_script_addr->mxc_sdma_ext_mem_2_ipu_addr = + ext_mem__ipu_ram_ADDR_V2; + sdma_script_addr->mxc_sdma_descrambler_addr = -1; + + sdma_script_addr->mxc_sdma_start_addr = + (unsigned short *)sdma_code_v2; + sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE; + sdma_script_addr->mxc_sdma_ram_code_start_addr = + RAM_CODE_START_ADDR_V2; + } +} + +static void mxc_nop_release(struct device *dev) +{ + /* Nothing */ +} + +#if defined(CONFIG_RTC_MXC) || defined(CONFIG_RTC_MXC_MODULE) +static struct resource rtc_resources[] = { + { + .start = RTC_BASE_ADDR, + .end = RTC_BASE_ADDR + 0x30, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_RTC, + .flags = IORESOURCE_IRQ, + }, +}; +static struct platform_device mxc_rtc_device = { + .name = "mxc_rtc", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, +}; +static void mxc_init_rtc(void) +{ + (void)platform_device_register(&mxc_rtc_device); +} +#else +static inline void mxc_init_rtc(void) +{ +} +#endif + +#if defined(CONFIG_MXC_MC9SDZ60_RTC) || defined(CONFIG_MXC_MC9SDZ60_RTC_MODULE) +static struct resource pmic_rtc_resources[] = { + { + .start = MXC_PSEUDO_IRQ_RTC, + .flags = IORESOURCE_IRQ, + }, +}; +static struct platform_device pmic_rtc_device = { + .name = "pmic_rtc", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(pmic_rtc_resources), + .resource = pmic_rtc_resources, +}; +static void pmic_init_rtc(void) +{ + platform_device_register(&pmic_rtc_device); +} +#else +static void pmic_init_rtc(void) +{ +} +#endif + +#if defined(CONFIG_MXC_WATCHDOG) || defined(CONFIG_MXC_WATCHDOG_MODULE) +static struct resource wdt_resources[] = { + { + .start = WDOG1_BASE_ADDR, + .end = WDOG1_BASE_ADDR + 0x30, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mxc_wdt_device = { + .name = "mxc_wdt", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(wdt_resources), + .resource = wdt_resources, +}; + +static void mxc_init_wdt(void) +{ + (void)platform_device_register(&mxc_wdt_device); +} +#else +static inline void mxc_init_wdt(void) +{ +} +#endif + +#if defined(CONFIG_MXC_IPU) || defined(CONFIG_MXC_IPU_MODULE) +static struct mxc_ipu_config mxc_ipu_data = { + .rev = 2, +}; + +static struct resource ipu_resources[] = { + { + .start = IPU_CTRL_BASE_ADDR, + .end = IPU_CTRL_BASE_ADDR + SZ_4K, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_IPU_SYN, + .flags = IORESOURCE_IRQ, + }, + { + .start = MXC_INT_IPU_ERR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxc_ipu_device = { + .name = "mxc_ipu", + .id = -1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_ipu_data, + }, + .num_resources = ARRAY_SIZE(ipu_resources), + .resource = ipu_resources, +}; + +static void mxc_init_ipu(void) +{ + platform_device_register(&mxc_ipu_device); +} +#else +static inline void mxc_init_ipu(void) +{ +} +#endif + +/* SPI controller and device data */ +#if defined(CONFIG_SPI_MXC) || defined(CONFIG_SPI_MXC_MODULE) + +#ifdef CONFIG_SPI_MXC_SELECT1 +/*! + * Resource definition for the CSPI1 + */ +static struct resource mxcspi1_resources[] = { + [0] = { + .start = CSPI1_BASE_ADDR, + .end = CSPI1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_CSPI1, + .end = MXC_INT_CSPI1, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC CSPI1 */ +static struct mxc_spi_master mxcspi1_data = { + .maxchipselect = 4, + .spi_version = 7, +}; + +/*! Device Definition for MXC CSPI1 */ +static struct platform_device mxcspi1_device = { + .name = "mxc_spi", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxcspi1_data, + }, + .num_resources = ARRAY_SIZE(mxcspi1_resources), + .resource = mxcspi1_resources, +}; + +#endif /* CONFIG_SPI_MXC_SELECT1 */ + +#ifdef CONFIG_SPI_MXC_SELECT2 +/*! + * Resource definition for the CSPI2 + */ +static struct resource mxcspi2_resources[] = { + [0] = { + .start = CSPI2_BASE_ADDR, + .end = CSPI2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_CSPI2, + .end = MXC_INT_CSPI2, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC CSPI2 */ +static struct mxc_spi_master mxcspi2_data = { + .maxchipselect = 4, + .spi_version = 7, +}; + +/*! Device Definition for MXC CSPI2 */ +static struct platform_device mxcspi2_device = { + .name = "mxc_spi", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxcspi2_data, + }, + .num_resources = ARRAY_SIZE(mxcspi2_resources), + .resource = mxcspi2_resources, +}; +#endif /* CONFIG_SPI_MXC_SELECT2 */ + +static inline void mxc_init_spi(void) +{ + /* SPBA configuration for CSPI2 - MCU is set */ + spba_take_ownership(SPBA_CSPI2, SPBA_MASTER_A); +#ifdef CONFIG_SPI_MXC_SELECT1 + if (platform_device_register(&mxcspi1_device) < 0) + printk(KERN_ERR "Error: Registering the SPI Controller_1\n"); +#endif /* CONFIG_SPI_MXC_SELECT1 */ +#ifdef CONFIG_SPI_MXC_SELECT2 + if (platform_device_register(&mxcspi2_device) < 0) + printk(KERN_ERR "Error: Registering the SPI Controller_2\n"); +#endif /* CONFIG_SPI_MXC_SELECT2 */ +} +#else +static inline void mxc_init_spi(void) +{ +} +#endif + +/* I2C controller and device data */ +#if defined(CONFIG_I2C_MXC) || defined(CONFIG_I2C_MXC_MODULE) + +#ifdef CONFIG_I2C_MXC_SELECT1 +/*! + * Resource definition for the I2C1 + */ +static struct resource mxci2c1_resources[] = { + [0] = { + .start = I2C_BASE_ADDR, + .end = I2C_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_I2C, + .end = MXC_INT_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC I2C */ +static struct mxc_i2c_platform_data mxci2c1_data = { +#ifdef CONFIG_I2C_MXC_FAST_MODE_BUS_0 + .i2c_clk = 400000, +#else + .i2c_clk = 100000, +#endif +}; +#endif + +/*! + * Resource definition for the I2C2 + */ +static struct resource mxci2c2_resources[] = { + [0] = { + .start = I2C2_BASE_ADDR, + .end = I2C2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_I2C2, + .end = MXC_INT_I2C2, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC I2C */ +static struct mxc_i2c_platform_data mxci2c2_data = { +#ifdef CONFIG_I2C_MXC_FAST_MODE_BUS_1 + .i2c_clk = 400000, +#else + .i2c_clk = 100000, +#endif +}; + +#ifdef CONFIG_I2C_MXC_SELECT3 +/*! + * Resource definition for the I2C3 + */ +static struct resource mxci2c3_resources[] = { + [0] = { + .start = I2C3_BASE_ADDR, + .end = I2C3_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_I2C3, + .end = MXC_INT_I2C3, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC I2C */ +static struct mxc_i2c_platform_data mxci2c3_data = { +#ifdef CONFIG_I2C_MXC_FAST_MODE_BUS_2 + .i2c_clk = 400000, +#else + .i2c_clk = 100000, +#endif +}; +#endif + +/*! Device Definition for MXC I2C1 */ +static struct platform_device mxci2c_devices[] = { +#ifdef CONFIG_I2C_MXC_SELECT1 + { + .name = "mxc_i2c", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxci2c1_data, + }, + .num_resources = ARRAY_SIZE(mxci2c1_resources), + .resource = mxci2c1_resources,}, +#endif + { + .name = "mxc_i2c", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxci2c2_data, + }, + .num_resources = ARRAY_SIZE(mxci2c2_resources), + .resource = mxci2c2_resources,}, +#ifdef CONFIG_I2C_MXC_SELECT3 + { + .name = "mxc_i2c", + .id = 2, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxci2c3_data, + }, + .num_resources = ARRAY_SIZE(mxci2c3_resources), + .resource = mxci2c3_resources,}, +#endif +}; + +static inline void mxc_init_i2c(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mxci2c_devices); i++) { + if (platform_device_register(&mxci2c_devices[i]) < 0) + dev_err(&mxci2c_devices[i].dev, + "Unable to register I2C device\n"); + } +} +#else +static inline void mxc_init_i2c(void) +{ +} +#endif + +struct mxc_gpio_port mxc_gpio_ports[GPIO_PORT_NUM] = { + { + .num = 0, + .base = IO_ADDRESS(GPIO1_BASE_ADDR), + .irq = MXC_INT_GPIO1, + .virtual_irq_start = MXC_GPIO_INT_BASE, + }, + { + .num = 1, + .base = IO_ADDRESS(GPIO2_BASE_ADDR), + .irq = MXC_INT_GPIO2, + .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN, + }, + { + .num = 2, + .base = IO_ADDRESS(GPIO3_BASE_ADDR), + .irq = MXC_INT_GPIO3, + .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 2, + }, +}; + +static struct platform_device mxc_dma_device = { + .name = "mxc_dma", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, +}; + +static inline void mxc_init_dma(void) +{ + (void)platform_device_register(&mxc_dma_device); +} + +static struct resource spdif_resources[] = { + { + .start = SPDIF_BASE_ADDR, + .end = SPDIF_BASE_ADDR + 0x50, + .flags = IORESOURCE_MEM, + }, +}; + +static struct mxc_spdif_platform_data mxc_spdif_data = { + .spdif_tx = 1, + .spdif_rx = 1, + .spdif_clk_44100 = 3, /* spdif_ext_clk source for 44.1KHz */ + .spdif_clk_48000 = 0, /* audio osc source */ + .spdif_clkid = 0, + .spdif_clk = NULL, /* spdif bus clk */ +}; + +static struct platform_device mxc_alsa_spdif_device = { + .name = "mxc_alsa_spdif", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_spdif_data, + }, + .num_resources = ARRAY_SIZE(spdif_resources), + .resource = spdif_resources, +}; + +static inline void mxc_init_spdif(void) +{ + mxc_spdif_data.spdif_clk = clk_get(NULL, "spdif_ipg_clk"); + clk_put(mxc_spdif_data.spdif_clk); + mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_clk"); + clk_put(mxc_spdif_data.spdif_core_clk); + platform_device_register(&mxc_alsa_spdif_device); +} + +static struct resource asrc_resources[] = { + { + .start = ASRC_BASE_ADDR, + .end = ASRC_BASE_ADDR + 0x9C, + .flags = IORESOURCE_MEM, + }, +}; + +static struct mxc_asrc_platform_data mxc_asrc_data; + +static struct platform_device mxc_asrc_device = { + .name = "mxc_asrc", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_asrc_data, + }, + .num_resources = ARRAY_SIZE(asrc_resources), + .resource = asrc_resources, +}; + +/*! + * Currently not called. If the Luigi Audio design decides to use + * ASRC, then a call to this will be added in the __init fn + */ +static inline void mxc_init_asrc(void) +{ + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) + mxc_asrc_data.channel_bits = 3; + else + mxc_asrc_data.channel_bits = 4; + + mxc_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk"); + clk_put(mxc_asrc_data.asrc_core_clk); + mxc_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_audio_clk"); + clk_set_rate(mxc_asrc_data.asrc_audio_clk, 768000); + clk_put(mxc_asrc_data.asrc_audio_clk); + platform_device_register(&mxc_asrc_device); +} + +static void mxc_luigi_init_audio(void) +{ + struct clk *cko_clk; + struct clk *ckih_clk; + + cko_clk = clk_get(NULL, "cko1_clk"); + ckih_clk = clk_get(NULL, "ckih"); + + clk_set_parent(cko_clk, ckih_clk); + clk_enable(cko_clk); +} + +#if defined(CONFIG_MXC_PWM) +static struct resource pwm_resources[] = { + { + .start = PWM_BASE_ADDR, + .end = PWM_BASE_ADDR + 0x14, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_PWM, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxc_pwm_device = { + .name = "mxc_pwm", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(pwm_resources), + .resource = pwm_resources, +}; + +static void mxc_init_pwm(void) +{ + printk(KERN_INFO "mxc_pwm_device registered\n"); + if (platform_device_register(&mxc_pwm_device) < 0) + printk(KERN_ERR "registration of mxc_pwm device failed\n"); +} + +#else + +static void mxc_init_pwm(void) +{ + +} + +#endif + +#if defined(CONFIG_MXC_IIM) || defined(CONFIG_MXC_IIM_MODULE) +static struct resource mxc_iim_resources[] = { + { + .start = IIM_BASE_ADDR, + .end = IIM_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mxc_iim_device = { + .name = "mxc_iim", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(mxc_iim_resources), + .resource = mxc_iim_resources +}; + +static inline void mxc_init_iim(void) +{ + if (platform_device_register(&mxc_iim_device) < 0) + dev_err(&mxc_iim_device.dev, + "Unable to register mxc iim device\n"); +} +#else +static inline void mxc_init_iim(void) +{ +} +#endif + +int __init mxc_init_devices(void) +{ + mxc_init_wdt(); + mxc_init_ipu(); + mxc_init_spi(); + mxc_init_i2c(); + pmic_init_rtc(); + mxc_init_rtc(); + mxc_init_dma(); + mxc_luigi_init_audio(); + mxc_init_pwm(); + mxc_init_iim(); + + /* SPBA configuration for SSI2 - SDMA and MCU are set */ + spba_take_ownership(SPBA_SSI2, SPBA_MASTER_C | SPBA_MASTER_A); + return 0; +} diff -urN linux-2.6.26/arch/arm/mach-mx35/dma.c linux-2.6.26-lab126/arch/arm/mach-mx35/dma.c --- linux-2.6.26/arch/arm/mach-mx35/dma.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/dma.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,1046 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include + +#include "serial.h" + +#ifdef CONFIG_SND_MXC_SOC_IRAM +#define soc_trans_type int_2_per +#else +#define soc_trans_type emi_2_per +#endif + +#define MXC_SPDIF_TXFIFO_WML 8 +#define MXC_SPDIF_RXFIFO_WML 8 +#define MXC_SPDIF_TX_REG 0x2C +#define MXC_SPDIF_RX_REG 0x14 + +#define MXC_SSI_TX0_REG 0x0 +#define MXC_SSI_TX1_REG 0x4 +#define MXC_SSI_RX0_REG 0x8 +#define MXC_SSI_RX1_REG 0xC +#define MXC_SSI_TXFIFO_WML 0x4 +#define MXC_SSI_RXFIFO_WML 0x6 + +#define MXC_ASRC_FIFO_WML 0x40 +#define MXC_ASRCA_RX_REG 0x60 +#define MXC_ASRCA_TX_REG 0x64 +#define MXC_ASRCB_RX_REG 0x68 +#define MXC_ASRCB_TX_REG 0x6C +#define MXC_ASRCC_RX_REG 0x70 +#define MXC_ASRCC_TX_REG 0x74 + +#define MXC_ESAI_TX_REG 0x00 +#define MXC_ESAI_RX_REG 0x04 +#define MXC_ESAI_FIFO_WML 0x40 + +struct mxc_sdma_info_entry_s { + mxc_dma_device_t device; + void *chnl_info; +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart1_rx_params = { + .chnl_params = { + .watermark_level = UART1_UFCR_RXTL, + .per_address = UART1_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART1_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART1_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart1_tx_params = { + .chnl_params = { + .watermark_level = UART1_UFCR_TXTL, + .per_address = UART1_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART1_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART1_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart2_rx_params = { + .chnl_params = { + .watermark_level = UART2_UFCR_RXTL, + .per_address = UART2_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART2_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART2_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart2_tx_params = { + .chnl_params = { + .watermark_level = UART2_UFCR_TXTL, + .per_address = UART2_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART2_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART2_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart3_rx_params = { + .chnl_params = { + .watermark_level = UART3_UFCR_RXTL, + .per_address = UART3_BASE_ADDR, + .peripheral_type = UART_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART3_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART3_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart3_tx_params = { + .chnl_params = { + .watermark_level = UART3_UFCR_TXTL, + .per_address = UART3_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART3_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART3_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_spdif_16bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_SPDIF_TXFIFO_WML, + .per_address = SPDIF_BASE_ADDR + MXC_SPDIF_TX_REG, + .peripheral_type = SPDIF, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SPDIF_TX, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SPDIF_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_spdif_32bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_SPDIF_TXFIFO_WML, + .per_address = SPDIF_BASE_ADDR + MXC_SPDIF_TX_REG, + .peripheral_type = SPDIF, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SPDIF_TX, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SPDIF_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_spdif_32bit_rx_params = { + .chnl_params = { + .watermark_level = MXC_SPDIF_RXFIFO_WML, + .per_address = SPDIF_BASE_ADDR + MXC_SPDIF_RX_REG, + .peripheral_type = SPDIF, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SPDIF_RX, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SPDIF_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_memory_params = { + .chnl_params = { + .peripheral_type = MEMORY, + .transfer_type = emi_2_emi, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MEMORY, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = soc_trans_type, + .event_id = DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = soc_trans_type, + .event_id = DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = soc_trans_type, + .event_id = DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = soc_trans_type, + .event_id = DMA_REQ_SSI1_TX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = soc_trans_type, + .event_id = DMA_REQ_SSI1_TX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = soc_trans_type, + .event_id = DMA_REQ_SSI1_TX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrca_rx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML, + .per_address = ASRC_BASE_ADDR + MXC_ASRCA_RX_REG, + .peripheral_type = ASRC, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_ASRC_DMA1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrca_tx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML, + .per_address = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrcb_rx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML, + .per_address = ASRC_BASE_ADDR + MXC_ASRCB_RX_REG, + .peripheral_type = ASRC, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_ASRC_DMA2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrcb_tx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML, + .per_address = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrcc_rx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML * 3, + .per_address = ASRC_BASE_ADDR + MXC_ASRCC_RX_REG, + .peripheral_type = ASRC, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_ASRC_DMA3, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCC_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrcc_tx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML * 3, + .per_address = ASRC_BASE_ADDR + MXC_ASRCC_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ASRC_DMA6, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCC_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi1_tx0_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI1_TX1, + .event_id2 = DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_SSI1_TX0, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi1_tx1_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI1_TX2, + .event_id2 = DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_SSI1_TX1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi2_tx0_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .event_id2 = DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_SSI2_TX0, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi2_tx1_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI2_TX2, + .event_id2 = DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_SSI2_TX1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi1_tx0_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI1_TX1, + .event_id2 = DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_SSI1_TX0, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi1_tx1_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI1_TX2, + .event_id2 = DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_SSI1_TX1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi2_tx0_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .event_id2 = DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_SSI2_TX0, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi2_tx1_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI2_TX2, + .event_id2 = DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_SSI2_TX1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_esai_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_ESAI_TX, + .event_id2 = DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_ESAI_FIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_ESAI, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_esai_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_ESAI_TX, + .event_id2 = DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_ESAI_FIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_ESAI, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcc_esai_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_ESAI_TX, + .event_id2 = DMA_REQ_ASRC_DMA6, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_ASRC_FIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCC_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCC_ESAI, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_16bit_rx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = ESAI_BASE_ADDR + MXC_ESAI_RX_REG, + .peripheral_type = ESAI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ESAI_RX, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ESAI_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_16bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ESAI, + .transfer_type = soc_trans_type, + .event_id = DMA_REQ_ESAI_TX, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ESAI_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_24bit_rx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = ESAI_BASE_ADDR + MXC_ESAI_RX_REG, + .peripheral_type = ESAI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ESAI_RX, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ESAI_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_24bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ESAI, + .transfer_type = soc_trans_type, + .event_id = DMA_REQ_ESAI_TX, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ESAI_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static struct mxc_sdma_info_entry_s mxc_sdma_active_dma_info[] = { + {MXC_DMA_UART1_RX, &mxc_sdma_uart1_rx_params}, + {MXC_DMA_UART1_TX, &mxc_sdma_uart1_tx_params}, + {MXC_DMA_UART2_RX, &mxc_sdma_uart2_rx_params}, + {MXC_DMA_UART2_TX, &mxc_sdma_uart2_tx_params}, + {MXC_DMA_UART3_RX, &mxc_sdma_uart3_rx_params}, + {MXC_DMA_UART3_TX, &mxc_sdma_uart3_tx_params}, + {MXC_DMA_SPDIF_16BIT_TX, &mxc_sdma_spdif_16bit_tx_params}, + {MXC_DMA_SPDIF_32BIT_TX, &mxc_sdma_spdif_32bit_tx_params}, + {MXC_DMA_SPDIF_32BIT_RX, &mxc_sdma_spdif_32bit_rx_params}, + {MXC_DMA_SSI1_8BIT_RX0, &mxc_sdma_ssi1_8bit_rx0_params}, + {MXC_DMA_SSI1_8BIT_TX0, &mxc_sdma_ssi1_8bit_tx0_params}, + {MXC_DMA_SSI1_16BIT_RX0, &mxc_sdma_ssi1_16bit_rx0_params}, + {MXC_DMA_SSI1_16BIT_TX0, &mxc_sdma_ssi1_16bit_tx0_params}, + {MXC_DMA_SSI1_24BIT_RX0, &mxc_sdma_ssi1_24bit_rx0_params}, + {MXC_DMA_SSI1_24BIT_TX0, &mxc_sdma_ssi1_24bit_tx0_params}, + {MXC_DMA_SSI1_8BIT_RX1, &mxc_sdma_ssi1_8bit_rx1_params}, + {MXC_DMA_SSI1_8BIT_TX1, &mxc_sdma_ssi1_8bit_tx1_params}, + {MXC_DMA_SSI1_16BIT_RX1, &mxc_sdma_ssi1_16bit_rx1_params}, + {MXC_DMA_SSI1_16BIT_TX1, &mxc_sdma_ssi1_16bit_tx1_params}, + {MXC_DMA_SSI1_24BIT_RX1, &mxc_sdma_ssi1_24bit_rx1_params}, + {MXC_DMA_SSI1_24BIT_TX1, &mxc_sdma_ssi1_24bit_tx1_params}, + {MXC_DMA_SSI2_8BIT_RX0, &mxc_sdma_ssi2_8bit_rx0_params}, + {MXC_DMA_SSI2_8BIT_TX0, &mxc_sdma_ssi2_8bit_tx0_params}, + {MXC_DMA_SSI2_16BIT_RX0, &mxc_sdma_ssi2_16bit_rx0_params}, + {MXC_DMA_SSI2_16BIT_TX0, &mxc_sdma_ssi2_16bit_tx0_params}, + {MXC_DMA_SSI2_24BIT_RX0, &mxc_sdma_ssi2_24bit_rx0_params}, + {MXC_DMA_SSI2_24BIT_TX0, &mxc_sdma_ssi2_24bit_tx0_params}, + {MXC_DMA_SSI2_8BIT_RX1, &mxc_sdma_ssi2_8bit_rx1_params}, + {MXC_DMA_SSI2_8BIT_TX1, &mxc_sdma_ssi2_8bit_tx1_params}, + {MXC_DMA_SSI2_16BIT_RX1, &mxc_sdma_ssi2_16bit_rx1_params}, + {MXC_DMA_SSI2_16BIT_TX1, &mxc_sdma_ssi2_16bit_tx1_params}, + {MXC_DMA_SSI2_24BIT_RX1, &mxc_sdma_ssi2_24bit_rx1_params}, + {MXC_DMA_SSI2_24BIT_TX1, &mxc_sdma_ssi2_24bit_tx1_params}, + {MXC_DMA_ASRC_A_RX, &mxc_sdma_asrca_rx_params}, + {MXC_DMA_ASRC_A_TX, &mxc_sdma_asrca_tx_params}, + {MXC_DMA_ASRC_B_RX, &mxc_sdma_asrcb_rx_params}, + {MXC_DMA_ASRC_B_TX, &mxc_sdma_asrcb_tx_params}, + {MXC_DMA_ASRC_C_RX, &mxc_sdma_asrcc_rx_params}, + {MXC_DMA_ASRC_C_TX, &mxc_sdma_asrcc_tx_params}, + {MXC_DMA_ASRCA_ESAI, &mxc_sdma_asrca_esai_params}, + {MXC_DMA_ASRCB_ESAI, &mxc_sdma_asrcb_esai_params}, + {MXC_DMA_ASRCC_ESAI, &mxc_sdma_asrcc_esai_params}, + {MXC_DMA_ASRCA_SSI1_TX0, &mxc_sdma_asrca_ssi1_tx0_params}, + {MXC_DMA_ASRCA_SSI1_TX1, &mxc_sdma_asrca_ssi1_tx1_params}, + {MXC_DMA_ASRCA_SSI2_TX0, &mxc_sdma_asrca_ssi2_tx0_params}, + {MXC_DMA_ASRCA_SSI2_TX1, &mxc_sdma_asrca_ssi2_tx1_params}, + {MXC_DMA_ASRCB_SSI1_TX0, &mxc_sdma_asrcb_ssi1_tx0_params}, + {MXC_DMA_ASRCB_SSI1_TX1, &mxc_sdma_asrcb_ssi1_tx1_params}, + {MXC_DMA_ASRCB_SSI2_TX0, &mxc_sdma_asrcb_ssi2_tx0_params}, + {MXC_DMA_ASRCB_SSI2_TX1, &mxc_sdma_asrcb_ssi2_tx1_params}, + {MXC_DMA_ESAI_16BIT_RX, &mxc_sdma_esai_16bit_rx_params}, + {MXC_DMA_ESAI_16BIT_TX, &mxc_sdma_esai_16bit_tx_params}, + {MXC_DMA_ESAI_24BIT_RX, &mxc_sdma_esai_24bit_rx_params}, + {MXC_DMA_ESAI_24BIT_TX, &mxc_sdma_esai_24bit_tx_params}, + {MXC_DMA_MEMORY, &mxc_sdma_memory_params}, +}; + +static int mxc_sdma_info_entrys = + sizeof(mxc_sdma_active_dma_info) / sizeof(mxc_sdma_active_dma_info[0]); +/*! + * This functions Returns the SDMA paramaters associated for a module + * + * @param channel_id the ID of the module requesting DMA + * @return returns the sdma parameters structure for the device + */ +mxc_sdma_channel_params_t *mxc_sdma_get_channel_params(mxc_dma_device_t + channel_id) +{ + struct mxc_sdma_info_entry_s *p = mxc_sdma_active_dma_info; + int i; + + for (i = 0; i < mxc_sdma_info_entrys; i++, p++) { + if (p->device == channel_id) + return p->chnl_info; + } + return NULL; +} + +EXPORT_SYMBOL(mxc_sdma_get_channel_params); + +/*! + * This functions marks the SDMA channels that are statically allocated + * + * @param chnl the channel array used to store channel information + */ +void mxc_get_static_channels(mxc_dma_channel_t *chnl) +{ + /* No channels statically allocated for MX35 */ +#ifdef CONFIG_SDMA_IRAM + int i; + for (i = MXC_DMA_CHANNEL_IRAM; i < MAX_DMA_CHANNELS; i++) + chnl[i].dynamic = 0; +#endif +} + +EXPORT_SYMBOL(mxc_get_static_channels); diff -urN linux-2.6.26/arch/arm/mach-mx35/dvfs.c linux-2.6.26-lab126/arch/arm/mach-mx35/dvfs.c --- linux-2.6.26/arch/arm/mach-mx35/dvfs.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/dvfs.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,788 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (c) 2009 Amazon.com. All rights reserved + * Manish Lachwani(lachwani@lab126.com) + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * @file dvfs.c + * + * @brief A simplied driver for the Freescale Semiconductor MXC DVFS module. + * + * Upon initialization, the DVFS driver initializes the DVFS hardware + * sets up driver nodes attaches to the DVFS interrupt and initializes internal + * data structures. When the DVFS interrupt occurs the driver checks the cause + * of the interrupt (lower frequency, increase frequency or emergency) and + * changes the CPU voltage according to translation table that is loaded into + * the driver. + * + * @ingroup PM + */ + +/* + * Luigi power initialization. Do not use the MX35 DVFS but rather use + * CPUFreq. SW3 is turned off by default and turned on by the WiFi code. + * SW3 is unused. VUSB2, VDIG and SWBST turned off for good. + * + * VGEN2 and VSD put in low power in suspend. VPLL put in low power in + * suspend. Now that mcu_pll is disabled in suspend, VPLL can be reduced. + * SW4 is 1.8V in run mode and 1.65V in suspend. SW2 is for the CPU. SW2 + * scales b/w 1.22V and 1.33V. See the cpufreq driver. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "crm_regs.h" + +/* + * With the ARM clocked at 532, this setting yields a DIV_3_CLK of 4.16 kHz. + */ +#define DVFS_DIV3CK (3 << MXC_CCM_LTR0_DIV3CK_OFFSET) + +/* + * Panic threshold. Panic frequency change request + * will be sent if DVFS counter value will be more than this value. + */ +#define DVFS_PNCTHR (63 << MXC_CCM_LTR1_PNCTHR_OFFSET) + +/* + * Load tracking buffer source: 1 for ld_add; 0 for pre_ld_add + */ +#define DVFS_LTBRSR (1 << MXC_CCM_LTR1_LTBRSR_OFFSET) + +/* EMAC defines how many samples are included in EMA calculation */ +#define DVFS_EMAC (0x20 << MXC_CCM_LTR2_EMAC_OFFSET) + +/* + * Frequency increase threshold. Increase frequency change request + * will be sent if DVFS counter value will be more than this value. + */ +#define DVFS_UPTHR(val) (val << MXC_CCM_LTR0_UPTHR_OFFSET) + +/* + * Frequency decrease threshold. Decrease frequency change request + * will be sent if DVFS counter value will be less than this value. + */ +#define DVFS_DNTHR(val) (val << MXC_CCM_LTR0_DNTHR_OFFSET) + +/* + * DNCNT defines the amount of times the down threshold should be exceeded + * before DVFS will trigger frequency decrease request. + */ +#define DVFS_DNCNT(val) (val << MXC_CCM_LTR1_DNCNT_OFFSET) + +/* + * UPCNT defines the amount of times the up threshold should be exceeded + * before DVFS will trigger frequency increase request. + */ +#define DVFS_UPCNT(val) (val << MXC_CCM_LTR1_UPCNT_OFFSET) + +#define DVFS_DVSUP(val) (val << MXC_CCM_PMCR0_DVSUP_OFFSET) + +#define MXC_DVFS_MAX_WP_NUM 2 + +/* + * Memory Hold mode for the four buck switchers + */ +#define SW1_MHMODE_LSH 4 +#define SW1_MHMODE_VALUE 0 +#define SW1_MHMODE_MASK 1 + +#define SW2_MHMODE_LSH 14 +#define SW2_MHMODE_VALUE 0 +#define SW2_MHMODE_MASK 1 + +#define SW3_MHMODE_LSH 4 +#define SW3_MHMODE_VALUE 0 +#define SW3_MHMODE_MASK 1 + +#define SW4_MHMODE_LSH 12 +#define SW4_MHMODE_VALUE 1 +#define SW4_MHMODE_MASK 1 + +#define GPO2STBY_ENABLE 1 +#define GPO2STBY_LSH 9 +#define GPO2STBY_MASK 1 + +/* STANDBY and STANDBYSEC is active low */ +#define STANDBYINV 10 +#define STANDBYSECINV 11 + +#define PMIC_BUTTON_DEBOUNCE_MASK 0x3 +#define PMIC_BUTTON_DEBOUNCE_VALUE 0x1 + +/* WDIRESET bit #12 */ +#define WDIRESET 12 + +enum { + FSVAI_FREQ_NOCHANGE = 0x0, + FSVAI_FREQ_INCREASE, + FSVAI_FREQ_DECREASE, + FSVAI_FREQ_EMERG, +}; + +struct dvfs_wp { + unsigned long cpu_rate; + u32 core_voltage; + u32 dvsup; + u32 dnthr; + u32 upthr; + u32 dncnt; + u32 upcnt; +}; + +static struct dvfs_wp dvfs_wp_tbl[MXC_DVFS_MAX_WP_NUM] = { + {256000000, 1250000, DVFS_DVSUP(DVSUP_MEDIUM), DVFS_DNTHR(18), + DVFS_UPTHR(31), DVFS_DNCNT(0x33), + DVFS_UPCNT(0x33)}, + {512000000, 1400000, DVFS_DVSUP(DVSUP_TURBO), DVFS_DNTHR(18), + DVFS_UPTHR(30), DVFS_DNCNT(0x33), + DVFS_UPCNT(0x33)} +}; + +static u8 dvfs_wp_num = MXC_DVFS_MAX_WP_NUM; + + /* Used for tracking the number of interrupts */ +static u32 dvfs_nr_up[MXC_DVFS_MAX_WP_NUM]; +static u32 dvfs_nr_dn[MXC_DVFS_MAX_WP_NUM]; +static unsigned long stored_cpu_rate; /* cpu rate before DVFS starts */ +static u32 stored_pmcr0; +static int dvfs_is_active; /* indicate DVFS is active or not */ + +static struct delayed_work dvfs_work; + +/* + * Clock structures + */ +static struct clk *cpu_clk; +static struct regulator *sw3_reg; + +const static u8 ltr_gp_weight[] = { + 0, /* 0 */ + 0, + 0, + 0, + 0, + 0, /* 5 */ + 0, + 0, + 0, + 0, + 0, /* 10 */ + 0, + 0, + 0, + 0, + 0, /* 15 */ +}; + +DEFINE_SPINLOCK(mxc_dvfs_lock); + +/*! + * This function sets the weight of general purpose signals + * @param gp_id number of general purpose bit + * @param weight the weight of the general purpose bit + */ +static void set_gp_weight(int gp_id, u8 weight) +{ + u32 reg; + + if (gp_id < 9) { + reg = __raw_readl(MXC_CCM_LTR3); + reg = (reg & ~(MXC_CCM_LTR3_WSW_MASK(gp_id))) | + (weight << MXC_CCM_LTR3_WSW_OFFSET(gp_id)); + __raw_writel(reg, MXC_CCM_LTR3); + } else if (gp_id < 16) { + reg = __raw_readl(MXC_CCM_LTR2); + reg = (reg & ~(MXC_CCM_LTR2_WSW_MASK(gp_id))) | + (weight << MXC_CCM_LTR2_WSW_OFFSET(gp_id)); + __raw_writel(reg, MXC_CCM_LTR2); + } +} + +/*! + * This function sets upper threshold, lower threshold, + * up-counter, down-counter for load tracking. + * @param upthr upper threshold + * @param dnthr lower threshold + * @param upcnt up counter + * @param dncnt down counter + */ +static void set_ltr_thres_counter(u32 upthr, u32 dnthr, u32 upcnt, u32 dncnt) +{ + u32 reg; + reg = __raw_readl(MXC_CCM_LTR0); + reg = + (reg & + ~(MXC_CCM_LTR0_UPTHR_MASK | + MXC_CCM_LTR0_DNTHR_MASK)) | upthr | dnthr; + __raw_writel(reg, MXC_CCM_LTR0); + + reg = __raw_readl(MXC_CCM_LTR1); + reg = + (reg & + ~(MXC_CCM_LTR1_UPCNT_MASK | + MXC_CCM_LTR1_DNCNT_MASK)) | upcnt | dncnt; + __raw_writel(reg, MXC_CCM_LTR1); +} + +/*! + * This function is called for module initialization. + * It sets up the DVFS hardware. + * It sets default values for DVFS thresholds and counters. The default + * values was chosen from a set of different reasonable values. They was tested + * and the default values in the driver gave the best results. + * More work should be done to find optimal values. + * + * @return 0 if successful; non-zero otherwise. + * + */ +static int init_dvfs_controller(void) +{ + u32 i, reg; + + /* setup LTR0 */ + reg = __raw_readl(MXC_CCM_LTR0); + reg = (reg & ~(MXC_CCM_LTR0_DIV3CK_MASK)) | DVFS_DIV3CK; + __raw_writel(reg, MXC_CCM_LTR0); + + /* set up LTR1 */ + reg = __raw_readl(MXC_CCM_LTR1); + reg = (reg & ~(MXC_CCM_LTR1_PNCTHR_MASK | MXC_CCM_LTR1_LTBRSR_MASK)); + reg = reg | DVFS_PNCTHR | DVFS_LTBRSR; + __raw_writel(reg, MXC_CCM_LTR1); + + /* setup LTR2 */ + reg = __raw_readl(MXC_CCM_LTR2); + reg = (reg & ~(MXC_CCM_LTR2_EMAC_MASK)) | DVFS_EMAC; + __raw_writel(reg, MXC_CCM_LTR2); + + /* Set general purpose weights to 0 */ + for (i = 0; i < 16; i++) + set_gp_weight(i, ltr_gp_weight[i]); + + /* ARM interrupt, mask load buf full interrupt */ + reg = __raw_readl(MXC_CCM_PMCR0); + reg |= MXC_CCM_PMCR0_DVFIS | MXC_CCM_PMCR0_LBMI; + __raw_writel(reg, MXC_CCM_PMCR0); + + return 0; +} + +static void dvfs_workqueue_handler(struct work_struct *work) +{ + u32 pmcr0 = stored_pmcr0; + u32 fsvai = (pmcr0 & MXC_CCM_PMCR0_FSVAI_MASK) >> + MXC_CCM_PMCR0_FSVAI_OFFSET; + u32 dvsup = (pmcr0 & MXC_CCM_PMCR0_DVSUP_MASK) >> + MXC_CCM_PMCR0_DVSUP_OFFSET; + u32 curr_cpu; + u8 curr_dvfs; + + if (!dvfs_is_active) + return; + + if (fsvai == FSVAI_FREQ_NOCHANGE) { + /* Do nothing. Freq change is not required */ + printk(KERN_WARNING "fsvai should not be 0\n"); + goto exit; + } + + if (((dvsup == DVSUP_LOW) && (fsvai == FSVAI_FREQ_DECREASE)) || + ((dvsup == DVSUP_TURBO) && ((fsvai == FSVAI_FREQ_INCREASE) || + (fsvai == FSVAI_FREQ_EMERG)))) { + /* Interrupt should be disabled in these cases according to + * the spec since DVFS is already at lowest (highest) state */ + printk(KERN_WARNING "Something is wrong?\n"); + goto exit; + } + + /*Disable DPTC voltage update */ + pmcr0 = pmcr0 & ~MXC_CCM_PMCR0_DPVCR; + __raw_writel(pmcr0, MXC_CCM_PMCR0); + + curr_cpu = clk_get_rate(cpu_clk); + for (curr_dvfs = 0; curr_dvfs < dvfs_wp_num; curr_dvfs++) { + if (dvfs_wp_tbl[curr_dvfs].cpu_rate == curr_cpu) { + if (fsvai == FSVAI_FREQ_DECREASE) { + curr_dvfs--; + dvfs_nr_dn[dvsup]++; + /*reduce frequency and then voltage */ + clk_set_rate(cpu_clk, + dvfs_wp_tbl[curr_dvfs].cpu_rate); + regulator_set_voltage(sw3_reg, + dvfs_wp_tbl[curr_dvfs]. + core_voltage); + pr_info("Decrease frequency to: %ld \n", + dvfs_wp_tbl[curr_dvfs].cpu_rate); + } else { + /*increase freq to the highest one */ + curr_dvfs = dvfs_wp_num - 1; + dvfs_nr_up[dvsup]++; + /*Increase voltage and then frequency */ + regulator_set_voltage(sw3_reg, + dvfs_wp_tbl[curr_dvfs]. + core_voltage); + clk_set_rate(cpu_clk, + dvfs_wp_tbl[curr_dvfs].cpu_rate); + pr_info("Increase frequency to: %ld \n", + dvfs_wp_tbl[curr_dvfs].cpu_rate); + } + pmcr0 = (pmcr0 & ~MXC_CCM_PMCR0_DVSUP_MASK) + | (dvfs_wp_tbl[curr_dvfs].dvsup); + __raw_writel(pmcr0, MXC_CCM_PMCR0); + + set_ltr_thres_counter(dvfs_wp_tbl[curr_dvfs].upthr, + dvfs_wp_tbl[curr_dvfs].dnthr, + dvfs_wp_tbl[curr_dvfs].upcnt, + dvfs_wp_tbl[curr_dvfs].dncnt); + break; + } + } + + exit: + /* unmask interrupt */ + pmcr0 = pmcr0 & ~MXC_CCM_PMCR0_FSVAIM; + __raw_writel(pmcr0, MXC_CCM_PMCR0); + /*DVFS update finish */ + pmcr0 = (pmcr0 | MXC_CCM_PMCR0_DVFS_UPDATE_FINISH); + __raw_writel(pmcr0, MXC_CCM_PMCR0); +} + +static irqreturn_t dvfs_irq(int irq, void *dev_id) +{ + + u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0); + + /* Config dvfs_start bit */ + pmcr0 = pmcr0 | MXC_CCM_PMCR0_DVFS_START; + /*Mask interrupt */ + pmcr0 = pmcr0 | MXC_CCM_PMCR0_FSVAIM; + __raw_writel(pmcr0, MXC_CCM_PMCR0); + + stored_pmcr0 = pmcr0; + schedule_delayed_work(&dvfs_work, 0); + + return IRQ_RETVAL(1); +} + +/*! + * This function enables the DVFS module. + */ +static int start_dvfs(void) +{ + u32 reg = 0; + unsigned long flags; + u8 i; + + if (dvfs_is_active) { + pr_info("DVFS is already started\n"); + return 0; + } + + spin_lock_irqsave(&mxc_dvfs_lock, flags); + + stored_cpu_rate = clk_get_rate(cpu_clk); + for (i = 0; i < dvfs_wp_num; i++) { + if (dvfs_wp_tbl[i].cpu_rate == stored_cpu_rate) { + /*Set LTR0 and LTR1 */ + set_ltr_thres_counter(dvfs_wp_tbl[i].upthr, + dvfs_wp_tbl[i].dnthr, + dvfs_wp_tbl[i].upcnt, + dvfs_wp_tbl[i].dncnt); + + reg = __raw_readl(MXC_CCM_PMCR0); + reg = + (reg & ~MXC_CCM_PMCR0_DVSUP_MASK) | (dvfs_wp_tbl[i]. + dvsup); + /* enable dvfs and interrupt */ + reg = + (reg & ~MXC_CCM_PMCR0_FSVAIM) | MXC_CCM_PMCR0_DVFEN; + + __raw_writel(reg, MXC_CCM_PMCR0); + + dvfs_is_active = 1; + pr_info("DVFS Starts\n"); + break; + } + } + + spin_unlock_irqrestore(&mxc_dvfs_lock, flags); + if (dvfs_is_active) + return 0; + else + return 1; +} + +/*! + * This function disables the DVFS module. + */ +static void stop_dvfs(void) +{ + u32 pmcr0; + unsigned long curr_cpu = clk_get_rate(cpu_clk); + u8 index; + + if (dvfs_is_active) { + + pmcr0 = __raw_readl(MXC_CCM_PMCR0); + /* disable dvfs and its interrupt */ + pmcr0 = (pmcr0 & ~MXC_CCM_PMCR0_DVFEN) | MXC_CCM_PMCR0_FSVAIM; + __raw_writel(pmcr0, MXC_CCM_PMCR0); + + if (stored_cpu_rate < curr_cpu) { + for (index = 0; index < dvfs_wp_num; index++) { + if (dvfs_wp_tbl[index].cpu_rate == + stored_cpu_rate) + break; + } + clk_set_rate(cpu_clk, stored_cpu_rate); + regulator_set_voltage(sw3_reg, + dvfs_wp_tbl[index].core_voltage); + } else if (stored_cpu_rate > curr_cpu) { + for (index = 0; index < dvfs_wp_num; index++) { + if (dvfs_wp_tbl[index].cpu_rate == + stored_cpu_rate) + break; + } + regulator_set_voltage(sw3_reg, + dvfs_wp_tbl[index].core_voltage); + clk_set_rate(cpu_clk, stored_cpu_rate); + } + + dvfs_is_active = 0; + } + + pr_info("DVFS is stopped\n"); +} + +static ssize_t dvfs_enable_store(struct sys_device *dev, const char *buf, + size_t size) +{ + if (strstr(buf, "1") != NULL) { + if (start_dvfs() != 0) + printk(KERN_ERR "Failed to start DVFS\n"); + } else if (strstr(buf, "0") != NULL) { + stop_dvfs(); + } + + return size; +} + +static ssize_t dvfs_status_show(struct sys_device *dev, char *buf) +{ + int size = 0; + + if (dvfs_is_active) + size = sprintf(buf, "DVFS is enabled\n"); + else + size = sprintf(buf, "DVFS is disabled\n"); + + size += + sprintf((buf + size), "UP:\t%d\t%d\t%d\t%d\n", dvfs_nr_up[0], + dvfs_nr_up[1], dvfs_nr_up[2], dvfs_nr_up[3]); + size += + sprintf((buf + size), "DOWN:\t%d\t%d\t%d\t%d\n\n", dvfs_nr_dn[0], + dvfs_nr_dn[1], dvfs_nr_dn[2], dvfs_nr_dn[3]); + + return size; +} + +static ssize_t dvfs_status_store(struct sys_device *dev, const char *buf, + size_t size) +{ + if (strstr(buf, "reset") != NULL) { + int i; + for (i = 0; i < MXC_DVFS_MAX_WP_NUM; i++) { + dvfs_nr_up[i] = 0; + dvfs_nr_dn[i] = 0; + } + } + + return size; +} + +static SYSDEV_ATTR(enable, 0200, NULL, dvfs_enable_store); +static SYSDEV_ATTR(status, 0644, dvfs_status_show, dvfs_status_store); + +static struct sysdev_class dvfs_sysclass = { + .name = "dvfs", +}; + +static struct sys_device dvfs_device = { + .id = 0, + .cls = &dvfs_sysclass, +}; + +static int dvfs_sysdev_ctrl_init(void) +{ + int err; + + err = sysdev_class_register(&dvfs_sysclass); + if (!err) + err = sysdev_register(&dvfs_device); + if (!err) { + err = sysdev_create_file(&dvfs_device, &attr_enable); + err = sysdev_create_file(&dvfs_device, &attr_status); + } + + return err; +} + +static void dvfs_sysdev_ctrl_exit(void) +{ + sysdev_remove_file(&dvfs_device, &attr_enable); + sysdev_remove_file(&dvfs_device, &attr_status); + sysdev_unregister(&dvfs_device); + sysdev_class_unregister(&dvfs_sysclass); +} + +/*! + * Get the current version of the Altas part + */ +int get_pmic_revision(void) +{ + int rev_id = 0; + int finid = 0; + + pmic_read(REG_IDENTIFICATION, &rev_id); + finid = (rev_id & 0x01E00) >> 9; + + return finid; +} +EXPORT_SYMBOL(get_pmic_revision); + +static int __init dvfs_init(void) +{ + int err = 0; + u8 index; + unsigned long curr_cpu; + static struct regulator *sw2_dvs_reg, *sw1_wifi_reg, *sw4_reg; + static struct regulator *viohi_reg, *vdig_reg, *swbst_reg, *vpll_reg, *vusb2_reg; + static struct regulator *sw2_stdby_reg, *sw3_normal_reg, *sw1_stby_reg; + int finid = get_pmic_revision(); + unsigned int reg = 0; + + cpu_clk = clk_get(NULL, "cpu_clk"); + curr_cpu = clk_get_rate(cpu_clk); + sw3_reg = regulator_get(NULL, "SW2"); + dvfs_is_active = 0; + + printk(KERN_INFO "Initializing MX35 DVFS on MC13892 Finid: %d\n", finid); + + /* + * WIFI SW1 - Turn off by default + */ + sw1_wifi_reg = regulator_get(NULL, "SW1"); + sw1_stby_reg = regulator_get(NULL, "SW1_STBY"); + regulator_enable(sw1_wifi_reg); + regulator_set_voltage(sw1_wifi_reg, 0); + pmic_write_reg(28, 0, 0xf << 0); /* Set to off in Normal mode */ + pmic_write_reg(24, 0, 0x1f << 0); /* Set 0V in Normal mode */ + regulator_set_voltage(sw1_stby_reg, 1200000); + if (finid == 2) + pmic_write_reg(28, (0x0 << 0), (0xf << 0)); + mdelay(10); + + /* + * CPU SW2 + */ + pmic_write_reg(25, (1 << 23), (1 << 23)); + sw2_dvs_reg = regulator_get(NULL, "SW2_DVS"); + sw2_stdby_reg = regulator_get(NULL, "SW2_STBY"); + regulator_set_voltage(sw2_dvs_reg, 1400000); + regulator_set_voltage(sw3_reg, 1400000); + regulator_set_voltage(sw2_stdby_reg, 1100000); + + /* + * Turn off SW3 + */ + sw3_normal_reg = regulator_get(NULL, "SW3"); + regulator_set_voltage(sw3_normal_reg, 0); + pmic_write_reg(29, 0, 0xf << 0); /* Set to off in Normal mode */ + pmic_write_reg(26, 0, 0x1f << 0); /* Set 0V in Normal mode */ + if (finid == 2) + pmic_write_reg(28, (0x8 << 10), (0xf << 10)); + mdelay(20); + + /* + * Set SW4 to 1.8V by default + */ + if (finid == 2) + pmic_write_reg(29, (0x8 << 8), (0xf << 8)); + sw4_reg = regulator_get(NULL, "SW4"); + regulator_set_voltage(sw4_reg, 1800000); + + /* Set the SW4 Standby to 1.8V */ + pmic_write_reg(27, (0x1C << 10), (0x1f << 10)); + + /* + * STANDBY and STANDBYSEC are both active low + */ + pmic_write_reg(REG_POWER_CTL2, (0 << STANDBYINV), (1 << STANDBYINV)); + pmic_write_reg(REG_POWER_CTL2, (0 << STANDBYSECINV), (1 << STANDBYSECINV)); + + /* Enable WDIRESET on the PMIC */ + pmic_write_reg(REG_POWER_CTL2, (1 << WDIRESET), (1 << WDIRESET)); + + /* Turn on GPO2STBY to disable the regulator in Atlas standby mode */ + pmic_write_reg(REG_POWER_MISC, (GPO2STBY_ENABLE << GPO2STBY_LSH), + (GPO2STBY_MASK << GPO2STBY_LSH)); + + /* + * VIOHI + */ + viohi_reg = regulator_get(NULL, "VIOHI"); + regulator_enable(viohi_reg); + + /* + * VDIG + */ + vdig_reg = regulator_get(NULL, "VDIG"); + regulator_enable(vdig_reg); + regulator_disable(vdig_reg); + + /* + * VUSB2 + */ + vusb2_reg = regulator_get(NULL, "VUSB2"); + regulator_enable(vusb2_reg); + regulator_disable(vusb2_reg); + + /* + * SWBST - off + */ + swbst_reg = regulator_get(NULL, "SWBST"); + regulator_enable(swbst_reg); + regulator_disable(swbst_reg); + + /* Turn off SWBST */ + pmic_write_reg(REG_SW_5, (0 << 20), (1 << 20)); + + /* + * VPLL - Controlled by Standby + */ + vpll_reg = regulator_get(NULL, "VPLL"); + /* VPLL controlled by standby */ + pmic_write_reg(32, (1 << 16), (1 << 16)); + + /* + * VSD - Controlled by Standby + */ + pmic_write_reg(33, (1 << 18), (1 << 18)); + pmic_write_reg(33, (1 << 19), (1 << 19)); + pmic_write_reg(32, (1 << 13), (1 << 13)); + + /* + * Power button debounce time + */ + + pmic_read_reg(REG_POWER_CTL2, ®, 0xffffffff); + printk(KERN_INFO "Power Button Debounce Settings: 0x%x\n", reg); + + /* Configure debounce time for power button 1 */ + pmic_write_reg(REG_POWER_CTL2, (PMIC_BUTTON_DEBOUNCE_VALUE << 4), (PMIC_BUTTON_DEBOUNCE_MASK << 4)); + + /* Configure debounce time for power button 2 */ + pmic_write_reg(REG_POWER_CTL2, (PMIC_BUTTON_DEBOUNCE_VALUE << 6), (PMIC_BUTTON_DEBOUNCE_MASK << 6)); + + /* Configure debounce time for power button 3 */ + pmic_write_reg(REG_POWER_CTL2, (PMIC_BUTTON_DEBOUNCE_VALUE << 8), (PMIC_BUTTON_DEBOUNCE_MASK << 8)); + + /* + * Set the USEROFF Mode for the Switchers + */ + pmic_write_reg(REG_SW_4, (SW1_MHMODE_VALUE << SW1_MHMODE_LSH), + (SW1_MHMODE_MASK << SW1_MHMODE_LSH)); + + pmic_write_reg(REG_SW_4, (SW2_MHMODE_VALUE << SW2_MHMODE_LSH), + (SW2_MHMODE_MASK << SW2_MHMODE_LSH)); + + pmic_write_reg(REG_SW_5, (SW3_MHMODE_VALUE << SW3_MHMODE_LSH), + (SW3_MHMODE_MASK << SW3_MHMODE_LSH)); + + pmic_write_reg(REG_SW_5, (SW4_MHMODE_VALUE << SW4_MHMODE_LSH), + (SW4_MHMODE_MASK << SW4_MHMODE_LSH)); + + /* for auto path, only 3 working points are supported */ + if (!(__raw_readl(MXC_CCM_PDR0) & MXC_CCM_PDR0_AUTO_CON)) { + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) { + dvfs_wp_num = 3; + dvfs_wp_tbl[2].dvsup = DVFS_DVSUP(DVSUP_TURBO); + } + } + + printk(KERN_INFO "MX35 Luigi working points: %d\n", dvfs_wp_num); + + /*Set voltage */ + for (index = 0; index < dvfs_wp_num; index++) { + if (dvfs_wp_tbl[index].cpu_rate == curr_cpu) { + regulator_set_voltage(sw3_reg, + dvfs_wp_tbl[index].core_voltage); + break; + } + } + + err = init_dvfs_controller(); + if (err) { + printk(KERN_ERR "DVFS: Unable to initialize DVFS"); + return err; + } + + INIT_DELAYED_WORK(&dvfs_work, dvfs_workqueue_handler); + + /* request the DVFS interrupt */ + err = request_irq(MXC_INT_DVFS, dvfs_irq, IRQF_DISABLED, "dvfs", NULL); + if (err) { + printk(KERN_ERR "DVFS: Unable to attach to DVFS interrupt"); + return err; + } + + err = dvfs_sysdev_ctrl_init(); + if (err) { + printk(KERN_ERR + "DVFS: Unable to register sysdev entry for dvfs"); + return err; + } + + return err; +} + +static void __exit dvfs_cleanup(void) +{ + stop_dvfs(); + + /* release the DVFS interrupt */ + free_irq(MXC_INT_DVFS, NULL); + + dvfs_sysdev_ctrl_exit(); + + clk_put(cpu_clk); + regulator_put(sw3_reg, NULL); +} + +module_init(dvfs_init); +module_exit(dvfs_cleanup); + +MODULE_AUTHOR("Freescale Seminconductor, Inc."); +MODULE_DESCRIPTION("DVFS driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/mach-mx35/iomux.c linux-2.6.26-lab126/arch/arm/mach-mx35/iomux.c --- linux-2.6.26/arch/arm/mach-mx35/iomux.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/iomux.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,474 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup GPIO_MX35 Board GPIO and Muxing Setup + * @ingroup MSL_MX35 + */ +/*! + * @file mach-mx35/iomux.c + * + * @brief I/O Muxing control functions + * + * @ingroup GPIO_MX35 + */ + +#include +#include +#include +#include +#include "iomux.h" + +#ifdef CONFIG_DEBUG_FS +#include +#endif + +/*! + * IOMUX register (base) addresses + */ +enum iomux_reg_addr { + IOMUXGPR = IO_ADDRESS(IOMUXC_BASE_ADDR), + /*!< General purpose */ + IOMUXSW_MUX_CTL = IO_ADDRESS(IOMUXC_BASE_ADDR) + 4, + /*!< MUX control */ + IOMUXSW_MUX_END = IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x324, + /*!< last MUX control register */ + IOMUXSW_PAD_CTL = IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x328, + /*!< Pad control */ + IOMUXSW_PAD_END = IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x790, + /*!< last Pad control register */ + IOMUXSW_INPUT_CTL = IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x7A8, + /*!< input select register */ + IOMUXSW_INPUT_END = IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x9F4, + /*!< last input select register */ +}; + +#define MUX_PIN_NUM_MAX \ + (((IOMUXSW_PAD_END - IOMUXSW_PAD_CTL) >> 2) + 1) +#define MUX_INPUT_NUM_MUX \ + (((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1) + +#define PIN_TO_IOMUX_INDEX(pin) ((PIN_TO_IOMUX_PAD(pin) - 0x328) >> 2) + +static DEFINE_RAW_SPINLOCK(gpio_mux_lock); +static u8 iomux_pin_res_table[MUX_PIN_NUM_MAX]; + +#ifdef CONFIG_DEBUG_FS + +struct mx35_pins { + char *name; + int value; +}; + +#define MX35_MAX_PINS 223 /* Total number of pins on MX35 */ + +#endif + +/*! + * This function is used to configure a pin through the IOMUX module. + * FIXED ME: for backward compatible. Will be static function! + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param cfg an output function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + u32 ret = 0; + u32 pin_index = PIN_TO_IOMUX_INDEX(pin); + u32 mux_reg = PIN_TO_IOMUX_MUX(pin); + u8 *rp; + + BUG_ON(pin_index > MUX_PIN_NUM_MAX); + if (mux_reg != NON_MUX_I) { + mux_reg += IOMUXGPR; + BUG_ON((mux_reg > IOMUXSW_MUX_END) + || (mux_reg < IOMUXSW_MUX_CTL)); + spin_lock(&gpio_mux_lock); + __raw_writel(cfg, mux_reg); + /* + * Log a warning if a pin changes ownership + */ + rp = iomux_pin_res_table + pin_index; + if ((cfg & *rp) && (*rp != cfg)) { + /*Console: how to do */ + printk(KERN_ERR "iomux_config_mux: Warning: iomux pin" + " config changed, index=%d register=%d, " + " prev=0x%x new=0x%x\n", pin_index, mux_reg, + *rp, cfg); + ret = -EINVAL; + } + *rp = cfg; + spin_unlock(&gpio_mux_lock); + } + + return ret; +} + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + int ret = iomux_config_mux(pin, cfg); + if (GPIO_TO_PORT(IOMUX_TO_GPIO(pin)) < GPIO_PORT_NUM) { + if (((cfg & (~MUX_CONFIG_SION)) == MUX_CONFIG_GPIO) || + (((cfg & (~MUX_CONFIG_SION)) == MUX_CONFIG_FUNC) && + ((pin == MX35_PIN_GPIO1_0) || (pin == MX35_PIN_GPIO1_1) || + (pin == MX35_PIN_GPIO2_0) || (pin == MX35_PIN_GPIO3_0)))) + ret |= mxc_request_gpio(pin); + } + return ret; +} + +EXPORT_SYMBOL(mxc_request_iomux); + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + u32 pin_index = PIN_TO_IOMUX_INDEX(pin); + u8 *rp = iomux_pin_res_table + pin_index; + + BUG_ON((pin_index > MUX_PIN_NUM_MAX)); + + *rp = 0; + if (GPIO_TO_PORT(IOMUX_TO_GPIO(pin)) < GPIO_PORT_NUM) { + if (((cfg & (~MUX_CONFIG_SION)) == MUX_CONFIG_GPIO) || + (((cfg & (~MUX_CONFIG_SION)) == MUX_CONFIG_FUNC) && + ((pin == MX35_PIN_GPIO1_0) || (pin == MX35_PIN_GPIO1_1) || + (pin == MX35_PIN_GPIO2_0) || (pin == MX35_PIN_GPIO3_0)))) + mxc_free_gpio(pin); + } +} + +EXPORT_SYMBOL(mxc_free_iomux); + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) +{ + u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin); + + BUG_ON((pad_reg > IOMUXSW_PAD_END) || (pad_reg < IOMUXSW_PAD_CTL)); + + spin_lock(&gpio_mux_lock); + __raw_writel(config, pad_reg); + spin_unlock(&gpio_mux_lock); +} + +EXPORT_SYMBOL(mxc_iomux_set_pad); + +/*! + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in \b #iomux_gp_func_t + * @param en \b #true to enable; \b #false to disable + */ +void mxc_iomux_set_gpr(iomux_gp_func_t gp, bool en) +{ + u32 l; + + spin_lock(&gpio_mux_lock); + l = __raw_readl(IOMUXGPR); + + if (en) + l |= gp; + else + l &= ~gp; + + __raw_writel(l, IOMUXGPR); + spin_unlock(&gpio_mux_lock); +} + +EXPORT_SYMBOL(mxc_iomux_set_gpr); + +/*! + * This function configures input path. + * + * @param input index of input select register as defined in \b + * #iomux_input_select_t + * @param config the binary value of elements defined in \b + * #iomux_input_config_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config) +{ + u32 reg = IOMUXSW_INPUT_CTL + (input << 2); + + BUG_ON(input >= MUX_INPUT_NUM_MUX); + + spin_lock(&gpio_mux_lock); + __raw_writel(config, reg); + spin_unlock(&gpio_mux_lock); +} + +EXPORT_SYMBOL(mxc_iomux_set_input); + +#ifdef CONFIG_DEBUG_FS + +static struct mx35_pins mx35_luigi_pins[] = { + { "MX35_PIN_CAPTURE", _MXC_BUILD_GPIO_PIN(0, 4, 0x4, 0x328) }, + { "MX35_PIN_COMPARE", _MXC_BUILD_GPIO_PIN(0, 5, 0x8, 0x32C) }, + { "MX35_PIN_WATCHDOG_RST", _MXC_BUILD_GPIO_PIN(0, 6, 0xC, 0x330) }, + { "MX35_PIN_GPIO1_0", _MXC_BUILD_GPIO_PIN(0, 0, 0x10, 0x334) }, + { "MX35_PIN_GPIO1_1", _MXC_BUILD_GPIO_PIN(0, 1, 0x14, 0x338) }, + { "MX35_PIN_GPIO2_0", _MXC_BUILD_GPIO_PIN(1, 0, 0x18, 0x33C) }, + { "MX35_PIN_GPIO3_0", _MXC_BUILD_GPIO_PIN(2, 1, 0x1C, 0x340) }, + { "MX35_PIN_CLKO", _MXC_BUILD_GPIO_PIN(0, 8, 0x20, 0x34C) }, + { "MX35_PIN_POWER_FAIL", _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x360) }, + { "MX35_PIN_VSTBY", _MXC_BUILD_GPIO_PIN(0, 7, 0x24, 0x364) }, + { "MX35_PIN_A0", _MXC_BUILD_NON_GPIO_PIN(0x28, 0x368) }, + { "MX35_PIN_A1", _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x36C) }, + { "MX35_PIN_A2", _MXC_BUILD_NON_GPIO_PIN(0x30, 0x370) }, + { "MX35_PIN_A3", _MXC_BUILD_NON_GPIO_PIN(0x34, 0x374) }, + { "MX35_PIN_A4", _MXC_BUILD_NON_GPIO_PIN(0x38, 0x378) }, + { "MX35_PIN_A5", _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x37C) }, + { "MX35_PIN_A6", _MXC_BUILD_NON_GPIO_PIN(0x40, 0x380) }, + { "MX35_PIN_A7", _MXC_BUILD_NON_GPIO_PIN(0x44, 0x384) }, + { "MX35_PIN_A8", _MXC_BUILD_NON_GPIO_PIN(0x48, 0x388) }, + { "MX35_PIN_A9", _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x38C) }, + { "MX35_PIN_A10", _MXC_BUILD_NON_GPIO_PIN(0x50, 0x390) }, + { "MX35_PIN_MA10", _MXC_BUILD_NON_GPIO_PIN(0x54, 0x394) }, + { "MX35_PIN_A11", _MXC_BUILD_NON_GPIO_PIN(0x58, 0x398) }, + { "MX35_PIN_A12", _MXC_BUILD_NON_GPIO_PIN(0x5C, 0x39C) }, + { "MX35_PIN_A13", _MXC_BUILD_NON_GPIO_PIN(0x60, 0x3A0) }, + { "MX35_PIN_A14", _MXC_BUILD_NON_GPIO_PIN(0x64, 0x3A4) }, + { "MX35_PIN_A15", _MXC_BUILD_NON_GPIO_PIN(0x68, 0x3A8) }, + { "MX35_PIN_A16", _MXC_BUILD_NON_GPIO_PIN(0x6C, 0x3AC) }, + { "MX35_PIN_A17", _MXC_BUILD_NON_GPIO_PIN(0x70, 0x3B0) }, + { "MX35_PIN_A18", _MXC_BUILD_NON_GPIO_PIN(0x74, 0x3B4) }, + { "MX35_PIN_A19", _MXC_BUILD_NON_GPIO_PIN(0x78, 0x3B8) }, + { "MX35_PIN_A20", _MXC_BUILD_NON_GPIO_PIN(0x7C, 0x3BC) }, + { "MX35_PIN_A21", _MXC_BUILD_NON_GPIO_PIN(0x80, 0x3C0) }, + { "MX35_PIN_A22", _MXC_BUILD_NON_GPIO_PIN(0x84, 0x3C4) }, + { "MX35_PIN_A23", _MXC_BUILD_NON_GPIO_PIN(0x88, 0x3C8) }, + { "MX35_PIN_A24", _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x3CC) }, + { "MX35_PIN_A25", _MXC_BUILD_NON_GPIO_PIN(0x90, 0x3D0) }, + { "MX35_PIN_EB0", _MXC_BUILD_NON_GPIO_PIN(0x94, 0x46C) }, + { "MX35_PIN_EB1", _MXC_BUILD_NON_GPIO_PIN(0x98, 0x470) }, + { "MX35_PIN_OE", _MXC_BUILD_NON_GPIO_PIN(0x9C, 0x474) }, + { "MX35_PIN_CS0", _MXC_BUILD_NON_GPIO_PIN(0xA0, 0x478) }, + { "MX35_PIN_CS1", _MXC_BUILD_NON_GPIO_PIN(0xA4, 0x47C) }, + { "MX35_PIN_CS2", _MXC_BUILD_NON_GPIO_PIN(0xA8, 0x480) }, + { "MX35_PIN_CS3", _MXC_BUILD_NON_GPIO_PIN(0xAC, 0x484) }, + { "MX35_PIN_CS4", _MXC_BUILD_GPIO_PIN(0, 20, 0xB0, 0x488) }, + { "MX35_PIN_CS5", _MXC_BUILD_GPIO_PIN(0, 21, 0xB4, 0x48C) }, + { "MX35_PIN_NFCE_B", _MXC_BUILD_GPIO_PIN(0, 22, 0xB8, 0x490) }, + { "MX35_PIN_LBA", _MXC_BUILD_NON_GPIO_PIN(0xBC, 0x498) }, + { "MX35_PIN_BCLK", _MXC_BUILD_NON_GPIO_PIN(0xC0, 0x49C) }, + { "MX35_PIN_RW", _MXC_BUILD_NON_GPIO_PIN(0xC4, 0x4A0) }, + { "MX35_PIN_RAS", _MXC_BUILD_NON_GPIO_PIN(0xC8, 0x4A4) }, + { "MX35_PIN_CAS", _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x4A8) }, + { "MX35_PIN_SDWE", _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x4AC) }, + { "MX35_PIN_SDCKE0", _MXC_BUILD_NON_GPIO_PIN(0xD4, 0x4B0) }, + { "MX35_PIN_SDCKE1", _MXC_BUILD_NON_GPIO_PIN(0xD8, 0x4B4) }, + { "MX35_PIN_NFWE_B", _MXC_BUILD_GPIO_PIN(0, 18, 0xC8, 0x4CC) }, + { "MX35_PIN_NFRE_B", _MXC_BUILD_GPIO_PIN(0, 19, 0xCC, 0x4D0) }, + { "MX35_PIN_NFALE", _MXC_BUILD_GPIO_PIN(0, 20, 0xD0, 0x4D4) }, + { "MX35_PIN_NFCLE", _MXC_BUILD_GPIO_PIN(0, 21, 0xD4, 0x4D8) }, + { "MX35_PIN_NFWP_B", _MXC_BUILD_GPIO_PIN(0, 22, 0xD8, 0x4DC) }, + { "MX35_PIN_NFRB", _MXC_BUILD_GPIO_PIN(0, 23, 0xDC, 0x4E0) }, + { "MX35_PIN_D15", _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E4) }, + { "MX35_PIN_D14", _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E8) }, + { "MX35_PIN_D13", _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4EC) }, + { "MX35_PIN_D12", _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F0) }, + { "MX35_PIN_D11", _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F4) }, + { "MX35_PIN_D10", _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F8) }, + { "MX35_PIN_D9", _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4FC) }, + { "MX35_PIN_D8", _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x500) }, + { "MX35_PIN_D7", _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x504) }, + { "MX35_PIN_D6", _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x508) }, + { "MX35_PIN_D5", _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x50C) }, + { "MX35_PIN_D4", _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x510) }, + { "MX35_PIN_D3", _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x514) }, + { "MX35_PIN_D2", _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x518) }, + { "MX35_PIN_D1", _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x51C) }, + { "MX35_PIN_D0", _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x520) }, + { "MX35_PIN_CSI_D8", _MXC_BUILD_GPIO_PIN(0, 20, 0xE0, 0x524) }, + { "MX35_PIN_CSI_D9", _MXC_BUILD_GPIO_PIN(0, 21, 0xE4, 0x528) }, + { "MX35_PIN_CSI_D10", _MXC_BUILD_GPIO_PIN(0, 22, 0xE8, 0x52C) }, + { "MX35_PIN_CSI_D11", _MXC_BUILD_GPIO_PIN(0, 23, 0xEC, 0x530) }, + { "MX35_PIN_CSI_D12", _MXC_BUILD_GPIO_PIN(0, 24, 0xF0, 0x534) }, + { "MX35_PIN_CSI_D13", _MXC_BUILD_GPIO_PIN(0, 25, 0xF4, 0x538) }, + { "MX35_PIN_CSI_D14", _MXC_BUILD_GPIO_PIN(0, 26, 0xF8, 0x53C) }, + { "MX35_PIN_CSI_D15", _MXC_BUILD_GPIO_PIN(0, 27, 0xFC, 0x540) }, + { "MX35_PIN_CSI_MCLK", _MXC_BUILD_GPIO_PIN(0, 28, 0x100, 0x544) }, + { "MX35_PIN_CSI_VSYNC", _MXC_BUILD_GPIO_PIN(0, 29, 0x104, 0x548) }, + { "MX35_PIN_CSI_HSYNC", _MXC_BUILD_GPIO_PIN(0, 30, 0x108, 0x54C) }, + { "MX35_PIN_CSI_PIXCLK", _MXC_BUILD_GPIO_PIN(0, 31, 0x10C, 0x550) }, + { "MX35_PIN_I2C1_CLK", _MXC_BUILD_GPIO_PIN(1, 24, 0x110, 0x554) }, + { "MX35_PIN_I2C1_DAT", _MXC_BUILD_GPIO_PIN(1, 25, 0x114, 0x558) }, + { "MX35_PIN_I2C2_CLK", _MXC_BUILD_GPIO_PIN(1, 26, 0x118, 0x55C) }, + { "MX35_PIN_I2C2_DAT", _MXC_BUILD_GPIO_PIN(1, 27, 0x11C, 0x560) }, + { "MX35_PIN_STXD4", _MXC_BUILD_GPIO_PIN(1, 28, 0x120, 0x564) }, + { "MX35_PIN_SRXD4", _MXC_BUILD_GPIO_PIN(1, 29, 0x124, 0x568) }, + { "MX35_PIN_SCK4", _MXC_BUILD_GPIO_PIN(1, 30, 0x128, 0x56C) }, + { "MX35_PIN_STXFS4", _MXC_BUILD_GPIO_PIN(1, 31, 0x12C, 0x570) }, + { "MX35_PIN_STXD5", _MXC_BUILD_GPIO_PIN(0, 0, 0x130, 0x574) }, + { "MX35_PIN_SRXD5", _MXC_BUILD_GPIO_PIN(0, 1, 0x134, 0x578) }, + { "MX35_PIN_SCK5", _MXC_BUILD_GPIO_PIN(0, 2, 0x138, 0x57C) }, + { "MX35_PIN_STXFS5", _MXC_BUILD_GPIO_PIN(0, 3, 0x13C, 0x580) }, + { "MX35_PIN_SCKR", _MXC_BUILD_GPIO_PIN(0, 4, 0x140, 0x584) }, + { "MX35_PIN_FSR", _MXC_BUILD_GPIO_PIN(0, 5, 0x144, 0x588) }, + { "MX35_PIN_HCKR", _MXC_BUILD_GPIO_PIN(0, 6, 0x148, 0x58C) }, + { "MX35_PIN_SCKT", _MXC_BUILD_GPIO_PIN(0, 7, 0x14C, 0x590) }, + { "MX35_PIN_FST", _MXC_BUILD_GPIO_PIN(0, 8, 0x150, 0x594) }, + { "MX35_PIN_HCKT", _MXC_BUILD_GPIO_PIN(0, 9, 0x154, 0x598) }, + { "MX35_PIN_TX5_RX0", _MXC_BUILD_GPIO_PIN(0, 10, 0x158, 0x59C) }, + { "MX35_PIN_TX4_RX1", _MXC_BUILD_GPIO_PIN(0, 11, 0x15C, 0x5A0) }, + { "MX35_PIN_TX3_RX2", _MXC_BUILD_GPIO_PIN(0, 12, 0x160, 0x5A4) }, + { "MX35_PIN_TX2_RX3", _MXC_BUILD_GPIO_PIN(0, 13, 0x164, 0x5A8) }, + { "MX35_PIN_TX1", _MXC_BUILD_GPIO_PIN(0, 14, 0x168, 0x5AC) }, + { "MX35_PIN_TX0", _MXC_BUILD_GPIO_PIN(0, 15, 0x16C, 0x5B0) }, + { "MX35_PIN_CSPI1_MOSI", _MXC_BUILD_GPIO_PIN(0, 16, 0x170, 0x5B4) }, + { "MX35_PIN_CSPI1_MISO", _MXC_BUILD_GPIO_PIN(0, 17, 0x174, 0x5B8) }, + { "MX35_PIN_CSPI1_SS0", _MXC_BUILD_GPIO_PIN(0, 18, 0x178, 0x5BC) }, + { "MX35_PIN_CSPI1_SS1", _MXC_BUILD_GPIO_PIN(0, 19, 0x17C, 0x5C0) }, + { "MX35_PIN_CSPI1_SCLK", _MXC_BUILD_GPIO_PIN(2, 4, 0x180, 0x5C4) }, + { "MX35_PIN_CSPI1_SPI_RDY", _MXC_BUILD_GPIO_PIN(2, 5, 0x184, 0x5C8) }, + { "MX35_PIN_RXD1", _MXC_BUILD_GPIO_PIN(2, 6, 0x188, 0x5CC) }, + { "MX35_PIN_TXD1", _MXC_BUILD_GPIO_PIN(2, 7, 0x18C, 0x5D0) }, + { "MX35_PIN_RTS1", _MXC_BUILD_GPIO_PIN(2, 8, 0x190, 0x5D4) }, + { "MX35_PIN_CTS1", _MXC_BUILD_GPIO_PIN(2, 9, 0x194, 0x5D8) }, + { "MX35_PIN_RXD2", _MXC_BUILD_GPIO_PIN(2, 10, 0x198, 0x5DC) }, + { "MX35_PIN_TXD2", _MXC_BUILD_GPIO_PIN(1, 11, 0x19C, 0x5E0) }, + { "MX35_PIN_RTS2", _MXC_BUILD_GPIO_PIN(1, 12, 0x1A0, 0x5E4) }, + { "MX35_PIN_CTS2", _MXC_BUILD_GPIO_PIN(1, 13, 0x1A4, 0x5E8) }, + { "MX35_PIN_USBOTG_PWR", _MXC_BUILD_GPIO_PIN(2, 14, 0x1A8, 0x60C) }, + { "MX35_PIN_USBOTG_OC", _MXC_BUILD_GPIO_PIN(2, 15, 0x1AC, 0x610) }, + { "MX35_PIN_LD0", _MXC_BUILD_GPIO_PIN(1, 0, 0x1B0, 0x614) }, + { "MX35_PIN_LD1", _MXC_BUILD_GPIO_PIN(1, 1, 0x1B4, 0x618) }, + { "MX35_PIN_LD2", _MXC_BUILD_GPIO_PIN(1, 2, 0x1B8, 0x61C) }, + { "MX35_PIN_LD3", _MXC_BUILD_GPIO_PIN(1, 3, 0x1BC, 0x620) }, + { "MX35_PIN_LD4", _MXC_BUILD_GPIO_PIN(1, 4, 0x1C0, 0x624) }, + { "MX35_PIN_LD5", _MXC_BUILD_GPIO_PIN(1, 5, 0x1C4, 0x628) }, + { "MX35_PIN_LD6", _MXC_BUILD_GPIO_PIN(1, 6, 0x1C8, 0x62C) }, + { "MX35_PIN_LD7", _MXC_BUILD_GPIO_PIN(1, 7, 0x1CC, 0x630) }, + { "MX35_PIN_LD8", _MXC_BUILD_GPIO_PIN(1, 8, 0x1D0, 0x634) }, + { "MX35_PIN_LD9", _MXC_BUILD_GPIO_PIN(1, 9, 0x1D4, 0x638) }, + { "MX35_PIN_LD10", _MXC_BUILD_GPIO_PIN(1, 10, 0x1D8, 0x63C) }, + { "MX35_PIN_LD11", _MXC_BUILD_GPIO_PIN(1, 11, 0x1DC, 0x640) }, + { "MX35_PIN_LD12", _MXC_BUILD_GPIO_PIN(1, 12, 0x1E0, 0x644) }, + { "MX35_PIN_LD13", _MXC_BUILD_GPIO_PIN(1, 13, 0x1E4, 0x648) }, + { "MX35_PIN_LD14", _MXC_BUILD_GPIO_PIN(1, 14, 0x1E8, 0x64C) }, + { "MX35_PIN_LD15", _MXC_BUILD_GPIO_PIN(1, 15, 0x1EC, 0x650) }, + { "MX35_PIN_LD16", _MXC_BUILD_GPIO_PIN(1, 16, 0x1F0, 0x654) }, + { "MX35_PIN_LD17", _MXC_BUILD_GPIO_PIN(1, 17, 0x1F4, 0x658) }, + { "MX35_PIN_LD18", _MXC_BUILD_GPIO_PIN(2, 24, 0x1F8, 0x65C) }, + { "MX35_PIN_LD19", _MXC_BUILD_GPIO_PIN(2, 25, 0x1FC, 0x660) }, + { "MX35_PIN_LD20", _MXC_BUILD_GPIO_PIN(2, 26, 0x200, 0x664) }, + { "MX35_PIN_LD21", _MXC_BUILD_GPIO_PIN(2, 27, 0x204, 0x668) }, + { "MX35_PIN_LD22", _MXC_BUILD_GPIO_PIN(2, 28, 0x208, 0x66C) }, + { "MX35_PIN_LD23", _MXC_BUILD_GPIO_PIN(2, 29, 0x20C, 0x670) }, + { "MX35_PIN_D3_HSYNC", _MXC_BUILD_GPIO_PIN(2, 30, 0x210, 0x674) }, + { "MX35_PIN_D3_FPSHIFT", _MXC_BUILD_GPIO_PIN(2, 31, 0x214, 0x678) }, + { "MX35_PIN_D3_DRDY", _MXC_BUILD_GPIO_PIN(0, 0, 0x218, 0x67C) }, + { "MX35_PIN_CONTRAST", _MXC_BUILD_GPIO_PIN(0, 1, 0x21C, 0x680) }, + { "MX35_PIN_D3_VSYNC", _MXC_BUILD_GPIO_PIN(0, 2, 0x220, 0x684) }, + { "MX35_PIN_D3_REV", _MXC_BUILD_GPIO_PIN(0, 3, 0x224, 0x688) }, + { "MX35_PIN_D3_CLS", _MXC_BUILD_GPIO_PIN(0, 4, 0x228, 0x68C) }, + { "MX35_PIN_D3_SPL", _MXC_BUILD_GPIO_PIN(0, 5, 0x22C, 0x690) }, + { "MX35_PIN_SD1_CMD", _MXC_BUILD_GPIO_PIN(0, 6, 0x230, 0x694) }, + { "MX35_PIN_SD1_CLK", _MXC_BUILD_GPIO_PIN(0, 7, 0x234, 0x698) }, + { "MX35_PIN_SD1_DATA0", _MXC_BUILD_GPIO_PIN(0, 8, 0x238, 0x69C) }, + { "MX35_PIN_SD1_DATA1", _MXC_BUILD_GPIO_PIN(0, 9, 0x23C, 0x6A0) }, + { "MX35_PIN_SD1_DATA2", _MXC_BUILD_GPIO_PIN(0, 10, 0x240, 0x6A4) }, + { "MX35_PIN_SD1_DATA3", _MXC_BUILD_GPIO_PIN(0, 11, 0x244, 0x6A8) }, + { "MX35_PIN_SD2_CMD", _MXC_BUILD_GPIO_PIN(1, 0, 0x248, 0x6AC) }, + { "MX35_PIN_SD2_CLK", _MXC_BUILD_GPIO_PIN(1, 1, 0x24C, 0x6B0) }, + { "MX35_PIN_SD2_DATA0", _MXC_BUILD_GPIO_PIN(1, 2, 0x250, 0x6B4) }, + { "MX35_PIN_SD2_DATA1", _MXC_BUILD_GPIO_PIN(1, 3, 0x254, 0x6B8) }, + { "MX35_PIN_SD2_DATA2", _MXC_BUILD_GPIO_PIN(1, 4, 0x258, 0x6BC) }, + { "MX35_PIN_SD2_DATA3", _MXC_BUILD_GPIO_PIN(1, 5, 0x25C, 0x6C0) }, + { "MX35_PIN_ATA_CS0", _MXC_BUILD_GPIO_PIN(1, 6, 0x260, 0x6C4) }, + { "MX35_PIN_ATA_CS1", _MXC_BUILD_GPIO_PIN(1, 7, 0x264, 0x6C8) }, + { "MX35_PIN_ATA_DIOR", _MXC_BUILD_GPIO_PIN(1, 8, 0x268, 0x6CC) }, + { "MX35_PIN_ATA_DIOW", _MXC_BUILD_GPIO_PIN(1, 9, 0x26C, 0x6D0) }, + { "MX35_PIN_ATA_DMACK", _MXC_BUILD_GPIO_PIN(1, 10, 0x270, 0x6D4) }, + { "MX35_PIN_ATA_RESET_B", _MXC_BUILD_GPIO_PIN(1, 11, 0x274, 0x6D8) }, + { "MX35_PIN_ATA_IORDY", _MXC_BUILD_GPIO_PIN(1, 12, 0x278, 0x6DC) }, + { "MX35_PIN_ATA_DATA0", _MXC_BUILD_GPIO_PIN(1, 13, 0x27C, 0x6E0) }, + { "MX35_PIN_ATA_DATA1", _MXC_BUILD_GPIO_PIN(1, 14, 0x280, 0x6E4) }, + { "MX35_PIN_ATA_DATA2", _MXC_BUILD_GPIO_PIN(1, 15, 0x284, 0x6E8) }, + { "MX35_PIN_ATA_DATA3", _MXC_BUILD_GPIO_PIN(1, 16, 0x288, 0x6EC) }, + { "MX35_PIN_ATA_DATA4", _MXC_BUILD_GPIO_PIN(1, 17, 0x28C, 0x6F0) }, + { "MX35_PIN_ATA_DATA5", _MXC_BUILD_GPIO_PIN(1, 18, 0x290, 0x6F4) }, + { "MX35_PIN_ATA_DATA6", _MXC_BUILD_GPIO_PIN(1, 19, 0x294, 0x6F8) }, + { "MX35_PIN_ATA_DATA7", _MXC_BUILD_GPIO_PIN(1, 20, 0x298, 0x6FC) }, + { "MX35_PIN_ATA_DATA8", _MXC_BUILD_GPIO_PIN(1, 21, 0x29C, 0x700) }, + { "MX35_PIN_ATA_DATA9", _MXC_BUILD_GPIO_PIN(1, 22, 0x2A0, 0x704) }, + { "MX35_PIN_ATA_DATA10", _MXC_BUILD_GPIO_PIN(1, 23, 0x2A4, 0x708) }, + { "MX35_PIN_ATA_DATA11", _MXC_BUILD_GPIO_PIN(1, 24, 0x2A8, 0x70C) }, + { "MX35_PIN_ATA_DATA12", _MXC_BUILD_GPIO_PIN(1, 25, 0x2AC, 0x710) }, + { "MX35_PIN_ATA_DATA13", _MXC_BUILD_GPIO_PIN(1, 26, 0x2B0, 0x714) }, + { "MX35_PIN_ATA_DATA14", _MXC_BUILD_GPIO_PIN(1, 27, 0x2B4, 0x718) }, + { "MX35_PIN_ATA_DATA15", _MXC_BUILD_GPIO_PIN(1, 28, 0x2B8, 0x71C) }, + { "MX35_PIN_ATA_INTRQ", _MXC_BUILD_GPIO_PIN(1, 29, 0x2BC, 0x720) }, + { "MX35_PIN_ATA_BUFF_EN", _MXC_BUILD_GPIO_PIN(1, 30, 0x2C0, 0x724) }, + { "MX35_PIN_ATA_DMARQ", _MXC_BUILD_GPIO_PIN(1, 31, 0x2C4, 0x728) }, + { "MX35_PIN_ATA_DA0", _MXC_BUILD_GPIO_PIN(2, 0, 0x2C8, 0x72C) }, + { "MX35_PIN_ATA_DA1", _MXC_BUILD_GPIO_PIN(2, 1, 0x2CC, 0x730) }, + { "MX35_PIN_ATA_DA2", _MXC_BUILD_GPIO_PIN(2, 2, 0x2D0, 0x734) }, + { "MX35_PIN_MLB_CLK", _MXC_BUILD_GPIO_PIN(2, 3, 0x2D4, 0x738) }, + { "MX35_PIN_MLB_DAT", _MXC_BUILD_GPIO_PIN(2, 4, 0x2D8, 0x73C) }, + { "MX35_PIN_MLB_SIG", _MXC_BUILD_GPIO_PIN(2, 5, 0x2DC, 0x740) }, + { "MX35_PIN_FEC_TX_CLK", _MXC_BUILD_GPIO_PIN(2, 6, 0x2E0, 0x744) }, + { "MX35_PIN_FEC_RX_CLK", _MXC_BUILD_GPIO_PIN(2, 7, 0x2E4, 0x748) }, + { "MX35_PIN_FEC_RX_DV", _MXC_BUILD_GPIO_PIN(2, 8, 0x2E8, 0x74C) }, + { "MX35_PIN_FEC_COL", _MXC_BUILD_GPIO_PIN(2, 9, 0x2EC, 0x750) }, + { "MX35_PIN_FEC_RDATA0", _MXC_BUILD_GPIO_PIN(2, 10, 0x2F0, 0x754) }, + { "MX35_PIN_FEC_TDATA0", _MXC_BUILD_GPIO_PIN(2, 11, 0x2F4, 0x758) }, + { "MX35_PIN_FEC_TX_EN", _MXC_BUILD_GPIO_PIN(2, 12, 0x2F8, 0x75C) }, + { "MX35_PIN_FEC_MDC", _MXC_BUILD_GPIO_PIN(2, 13, 0x2FC, 0x760) }, + { "MX35_PIN_FEC_MDIO", _MXC_BUILD_GPIO_PIN(2, 14, 0x300, 0x764) }, + { "MX35_PIN_FEC_TX_ERR", _MXC_BUILD_GPIO_PIN(2, 15, 0x304, 0x768) }, + { "MX35_PIN_FEC_RX_ERR", _MXC_BUILD_GPIO_PIN(2, 16, 0x308, 0x76C) }, + { "MX35_PIN_FEC_CRS", _MXC_BUILD_GPIO_PIN(2, 17, 0x30C, 0x770) }, + { "MX35_PIN_FEC_RDATA1", _MXC_BUILD_GPIO_PIN(2, 18, 0x310, 0x774) }, + { "MX35_PIN_FEC_TDATA1", _MXC_BUILD_GPIO_PIN(2, 19, 0x314, 0x778) }, + { "MX35_PIN_FEC_RDATA2", _MXC_BUILD_GPIO_PIN(2, 20, 0x318, 0x77C) }, + { "MX35_PIN_FEC_TDATA2", _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780) }, + { "MX35_PIN_FEC_RDATA3", _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784) }, + { "MX35_PIN_FEC_TDATA3", _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788) }, +}; + +void mx35_show_pins(struct seq_file *s) +{ + int pin = 0, val = 0, t = 0; + + for (pin = 0; pin < MX35_MAX_PINS; pin++) { + val = __raw_readl(IOMUXGPR + PIN_TO_IOMUX_PAD(mx35_luigi_pins[pin].value)); + t += seq_printf(s, "%s Pad Value = 0x%x\n", mx35_luigi_pins[pin].name, val); + } + return; +} + +EXPORT_SYMBOL(mx35_show_pins); + +#endif /* CONFIG_DEBUG_FS */ diff -urN linux-2.6.26/arch/arm/mach-mx35/iomux.h linux-2.6.26-lab126/arch/arm/mach-mx35/iomux.h --- linux-2.6.26/arch/arm/mach-mx35/iomux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/iomux.h 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,293 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MACH_MX35_IOMUX_H__ +#define __MACH_MX35_IOMUX_H__ + +#include +#include +#include "mx35_pins.h" + +/*! + * @file mach-mx35/iomux.h + * + * @brief I/O Muxing control definitions and functions + * + * @ingroup GPIO_MX35 + */ + +/*! + * various IOMUX functions + */ +typedef enum iomux_pin_config { + MUX_CONFIG_FUNC = 0, /*!< used as function */ + MUX_CONFIG_ALT1, /*!< used as alternate function 1 */ + MUX_CONFIG_ALT2, /*!< used as alternate function 2 */ + MUX_CONFIG_ALT3, /*!< used as alternate function 3 */ + MUX_CONFIG_ALT4, /*!< used as alternate function 4 */ + MUX_CONFIG_ALT5, /*!< used as alternate function 5 */ + MUX_CONFIG_ALT6, /*!< used as alternate function 6 */ + MUX_CONFIG_ALT7, /*!< used as alternate function 7 */ + MUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */ + MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /*!< used as GPIO */ +} iomux_pin_cfg_t; + +/*! + * various IOMUX pad functions + */ +typedef enum iomux_pad_config { + PAD_CTL_DRV_3_3V = 0x0 << 13, + PAD_CTL_DRV_1_8V = 0x1 << 13, + PAD_CTL_HYS_CMOS = 0x0 << 8, + PAD_CTL_HYS_SCHMITZ = 0x1 << 8, + PAD_CTL_PKE_NONE = 0x0 << 7, + PAD_CTL_PKE_ENABLE = 0x1 << 7, + PAD_CTL_PUE_KEEPER = 0x0 << 6, + PAD_CTL_PUE_PUD = 0x1 << 6, + PAD_CTL_100K_PD = 0x0 << 4, + PAD_CTL_47K_PU = 0x1 << 4, + PAD_CTL_100K_PU = 0x2 << 4, + PAD_CTL_22K_PU = 0x3 << 4, + PAD_CTL_ODE_CMOS = 0x0 << 3, + PAD_CTL_ODE_OpenDrain = 0x1 << 3, + PAD_CTL_DRV_NORMAL = 0x0 << 1, + PAD_CTL_DRV_HIGH = 0x1 << 1, + PAD_CTL_DRV_MAX = 0x2 << 1, + PAD_CTL_SRE_SLOW = 0x0 << 0, + PAD_CTL_SRE_FAST = 0x1 << 0 +} iomux_pad_config_t; + +/*! + * various IOMUX general purpose functions + */ +typedef enum iomux_gp_func { + MUX_SDCTL_CSD0_SEL = 0x1 << 0, + MUX_SDCTL_CSD1_SEL = 0x1 << 1, + MUX_TAMPER_DETECT_EN = 0x1 << 2, +} iomux_gp_func_t; + +/*! + * various IOMUX input select register index + */ +typedef enum iomux_input_select { + MUX_IN_AMX_P5_RXCLK = 0, + MUX_IN_AMX_P5_RXFS, + MUX_IN_AMX_P6_DA, + MUX_IN_AMX_P6_DB, + MUX_IN_AMX_P6_RXCLK, + MUX_IN_AMX_P6_RXFS, + MUX_IN_AMX_P6_TXCLK, + MUX_IN_AMX_P6_TXFS, + MUX_IN_CAN1_CANRX, + MUX_IN_CAN2_CANRX, + MUX_IN_CCM_32K_MUXED, + MUX_IN_CCM_PMIC_RDY, + MUX_IN_CSPI1_SS2_B, + MUX_IN_CSPI1_SS3_B, + MUX_IN_CSPI2_CLK_IN, + MUX_IN_CSPI2_DATAREADY_B, + MUX_IN_CSPI2_MISO, + MUX_IN_CSPI2_MOSI, + MUX_IN_CSPI2_SS0_B, + MUX_IN_CSPI2_SS1_B, + MUX_IN_CSPI2_SS2_B, + MUX_IN_CSPI2_SS3_B, + MUX_IN_EMI_WEIM_DTACK_B, + MUX_IN_ESDHC1_DAT4_IN, + MUX_IN_ESDHC1_DAT5_IN, + MUX_IN_ESDHC1_DAT6_IN, + MUX_IN_ESDHC1_DAT7_IN, + MUX_IN_ESDHC3_CARD_CLK_IN, + MUX_IN_ESDHC3_CMD_IN, + MUX_IN_ESDHC3_DAT0, + MUX_IN_ESDHC3_DAT1, + MUX_IN_ESDHC3_DAT2, + MUX_IN_ESDHC3_DAT3, + MUX_IN_GPIO1_IN_0, + MUX_IN_GPIO1_IN_10, + MUX_IN_GPIO1_IN_11, + MUX_IN_GPIO1_IN_1, + MUX_IN_GPIO1_IN_20, + MUX_IN_GPIO1_IN_21, + MUX_IN_GPIO1_IN_22, + MUX_IN_GPIO1_IN_2, + MUX_IN_GPIO1_IN_3, + MUX_IN_GPIO1_IN_4, + MUX_IN_GPIO1_IN_5, + MUX_IN_GPIO1_IN_6, + MUX_IN_GPIO1_IN_7, + MUX_IN_GPIO1_IN_8, + MUX_IN_GPIO1_IN_9, + MUX_IN_GPIO2_IN_0, + MUX_IN_GPIO2_IN_10, + MUX_IN_GPIO2_IN_11, + MUX_IN_GPIO2_IN_12, + MUX_IN_GPIO2_IN_13, + MUX_IN_GPIO2_IN_14, + MUX_IN_GPIO2_IN_15, + MUX_IN_GPIO2_IN_16, + MUX_IN_GPIO2_IN_17, + MUX_IN_GPIO2_IN_18, + MUX_IN_GPIO2_IN_19, + MUX_IN_GPIO2_IN_1, + MUX_IN_GPIO2_IN_20, + MUX_IN_GPIO2_IN_21, + MUX_IN_GPIO2_IN_22, + MUX_IN_GPIO2_IN_23, + MUX_IN_GPIO2_IN_24, + MUX_IN_GPIO2_IN_25, + MUX_IN_GPIO2_IN_26, + MUX_IN_GPIO2_IN_27, + MUX_IN_GPIO2_IN_28, + MUX_IN_GPIO2_IN_29, + MUX_IN_GPIO2_IN_2, + MUX_IN_GPIO2_IN_30, + MUX_IN_GPIO2_IN_31, + MUX_IN_GPIO2_IN_3, + MUX_IN_GPIO2_IN_4, + MUX_IN_GPIO2_IN_5, + MUX_IN_GPIO2_IN_6, + MUX_IN_GPIO2_IN_7, + MUX_IN_GPIO2_IN_8, + MUX_IN_GPIO2_IN_9, + MUX_IN_GPIO3_IN_0, + MUX_IN_GPIO3_IN_10, + MUX_IN_GPIO3_IN_11, + MUX_IN_GPIO3_IN_12, + MUX_IN_GPIO3_IN_13, + MUX_IN_GPIO3_IN_14, + MUX_IN_GPIO3_IN_15, + MUX_IN_GPIO3_IN_4, + MUX_IN_GPIO3_IN_5, + MUX_IN_GPIO3_IN_6, + MUX_IN_GPIO3_IN_7, + MUX_IN_GPIO3_IN_8, + MUX_IN_GPIO3_IN_9, + MUX_IN_I2C3_SCL_IN, + MUX_IN_I2C3_SDA_IN, + MUX_IN_IPU_DISPB_D0_VSYNC, + MUX_IN_IPU_DISPB_D12_VSYNC, + MUX_IN_IPU_DISPB_SD_D, + MUX_IN_IPU_SENSB_DATA_0, + MUX_IN_IPU_SENSB_DATA_1, + MUX_IN_IPU_SENSB_DATA_2, + MUX_IN_IPU_SENSB_DATA_3, + MUX_IN_IPU_SENSB_DATA_4, + MUX_IN_IPU_SENSB_DATA_5, + MUX_IN_IPU_SENSB_DATA_6, + MUX_IN_IPU_SENSB_DATA_7, + MUX_IN_KPP_COL_0, + MUX_IN_KPP_COL_1, + MUX_IN_KPP_COL_2, + MUX_IN_KPP_COL_3, + MUX_IN_KPP_COL_4, + MUX_IN_KPP_COL_5, + MUX_IN_KPP_COL_6, + MUX_IN_KPP_COL_7, + MUX_IN_KPP_ROW_0, + MUX_IN_KPP_ROW_1, + MUX_IN_KPP_ROW_2, + MUX_IN_KPP_ROW_3, + MUX_IN_KPP_ROW_4, + MUX_IN_KPP_ROW_5, + MUX_IN_KPP_ROW_6, + MUX_IN_KPP_ROW_7, + MUX_IN_OWIRE_BATTERY_LINE, + MUX_IN_SPDIF_HCKT_CLK2, + MUX_IN_SPDIF_SPDIF_IN1, + MUX_IN_UART3_UART_RTS_B, + MUX_IN_UART3_UART_RXD_MUX, + MUX_IN_USB_OTG_DATA_0, + MUX_IN_USB_OTG_DATA_1, + MUX_IN_USB_OTG_DATA_2, + MUX_IN_USB_OTG_DATA_3, + MUX_IN_USB_OTG_DATA_4, + MUX_IN_USB_OTG_DATA_5, + MUX_IN_USB_OTG_DATA_6, + MUX_IN_USB_OTG_DATA_7, + MUX_IN_USB_OTG_DIR, + MUX_IN_USB_OTG_NXT, + MUX_IN_USB_UH2_DATA_0, + MUX_IN_USB_UH2_DATA_1, + MUX_IN_USB_UH2_DATA_2, + MUX_IN_USB_UH2_DATA_3, + MUX_IN_USB_UH2_DATA_4, + MUX_IN_USB_UH2_DATA_5, + MUX_IN_USB_UH2_DATA_6, + MUX_IN_USB_UH2_DATA_7, + MUX_IN_USB_UH2_DIR, + MUX_IN_USB_UH2_NXT, + MUX_IN_USB_UH2_USB_OC, +} iomux_input_select_t; + +/*! + * various IOMUX input functions + */ +typedef enum iomux_input_config { + INPUT_CTL_PATH0 = 0x0, + INPUT_CTL_PATH1, + INPUT_CTL_PATH2, + INPUT_CTL_PATH3, + INPUT_CTL_PATH4, + INPUT_CTL_PATH5, + INPUT_CTL_PATH6, + INPUT_CTL_PATH7, +} iomux_input_cfg_t; + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg); + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg); + +/*! + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in \b #iomux_gp_func_t + * @param en \b #true to enable; \b #false to disable + */ +void mxc_iomux_set_gpr(iomux_gp_func_t gp, bool en); + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b + * #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); + +/*! + * This function configures input path. + * + * @param input index of input select register as defined in \b + * #iomux_input_select_t + * @param config the binary value of elements defined in \b + * #iomux_input_cfg_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config); +#endif diff -urN linux-2.6.26/arch/arm/mach-mx35/mm.c linux-2.6.26-lab126/arch/arm/mach-mx35/mm.c --- linux-2.6.26/arch/arm/mach-mx35/mm.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/mm.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,92 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include + +/*! + * @file mach-mx35/mm.c + * + * @brief This file creates static mapping between physical to virtual memory. + * + * @ingroup Memory_MX35 + */ + +/*! + * This structure defines the MX35 memory map. + */ +static struct map_desc mxc_io_desc[] __initdata = { + { + .virtual = IRAM_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(IRAM_BASE_ADDR), + .length = IRAM_SIZE, + .type = MT_NONSHARED_DEVICE}, + { + .virtual = X_MEMC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR), + .length = X_MEMC_SIZE, + .type = MT_DEVICE}, + { + .virtual = NFC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(NFC_BASE_ADDR), + .length = NFC_SIZE, + .type = MT_NONSHARED_DEVICE}, + { + .virtual = ROMP_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(ROMP_BASE_ADDR), + .length = ROMP_SIZE, + .type = MT_NONSHARED_DEVICE}, + { + .virtual = AVIC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AVIC_BASE_ADDR), + .length = AVIC_SIZE, + .type = MT_NONSHARED_DEVICE}, + { + .virtual = AIPS1_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), + .length = AIPS1_SIZE, + .type = MT_NONSHARED_DEVICE}, + { + .virtual = SPBA0_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), + .length = SPBA0_SIZE, + .type = MT_NONSHARED_DEVICE}, + { + .virtual = AIPS2_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), + .length = AIPS2_SIZE, + .type = MT_NONSHARED_DEVICE}, +}; + +/*! + * This function initializes the memory map. It is called during the + * system startup to create static physical to virtual memory map for + * the IO modules. + */ +void __init mxc_map_io(void) +{ + iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); +} + +/** Wrapper for the get_task_comm function in fs/exec.c */ +char *mxc_get_task_comm(char *buf, struct task_struct *tsk) +{ + return get_task_comm(buf, tsk); +} + +EXPORT_SYMBOL(mxc_get_task_comm); diff -urN linux-2.6.26/arch/arm/mach-mx35/mx35_3stack.c linux-2.6.26-lab126/arch/arm/mach-mx35/mx35_3stack.c --- linux-2.6.26/arch/arm/mach-mx35/mx35_3stack.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/mx35_3stack.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,773 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "board-mx35_3stack.h" +#include "crm_regs.h" +#include "iomux.h" + +/*! + * @file mach-mx35/mx35_3stack.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX35 + */ + +extern int mxc_init_devices(void); + +unsigned int mx35_3stack_board_io; + +static void mxc_nop_release(struct device *dev) +{ + /* Nothing */ +} + +/* MTD NOR flash */ + +#if defined(CONFIG_MTD_MXC) || defined(CONFIG_MTD_MXC_MODULE) + +static struct mtd_partition mxc_nor_partitions[] = { + { + .name = "Bootloader", + .size = 512 * 1024, + .offset = 0x00000000, + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, + { + .name = "nor.Kernel", + .size = 4 * 1024 * 1024, + .offset = MTDPART_OFS_APPEND, + .mask_flags = 0}, + { + .name = "nor.userfs", + .size = 30 * 1024 * 1024, + .offset = MTDPART_OFS_APPEND, + .mask_flags = 0}, + { + .name = "nor.rootfs", + .size = 28 * 1024 * 1024, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE}, + { + .name = "FIS directory", + .size = 12 * 1024, + .offset = 0x01FE0000, + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, + { + .name = "Redboot config", + .size = MTDPART_SIZ_FULL, + .offset = 0x01FFF000, + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, +}; + +static struct flash_platform_data mxc_flash_data = { + .map_name = "cfi_probe", + .width = 2, + .parts = mxc_nor_partitions, + .nr_parts = ARRAY_SIZE(mxc_nor_partitions), +}; + +static struct resource mxc_flash_resource = { + .start = 0xa0000000, + .end = 0xa0000000 + 0x04000000 - 1, + .flags = IORESOURCE_MEM, + +}; + +static struct platform_device mxc_nor_mtd_device = { + .name = "mxc_nor_flash", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_flash_data, + }, + .num_resources = 1, + .resource = &mxc_flash_resource, +}; + +static void mxc_init_nor_mtd(void) +{ + (void)platform_device_register(&mxc_nor_mtd_device); +} +#else +static void mxc_init_nor_mtd(void) +{ +} +#endif + +/* MTD NAND flash */ + +#if defined(CONFIG_MTD_NAND_MXC) || defined(CONFIG_MTD_NAND_MXC_MODULE) \ +|| defined(CONFIG_MTD_NAND_MXC_V2) || defined(CONFIG_MTD_NAND_MXC_V2_MODULE) + +static struct mtd_partition mxc_nand_partitions[] = { + { + .name = "nand.bootloader", + .offset = 0, + .size = 1024 * 1024}, + { + .name = "nand.kernel", + .offset = MTDPART_OFS_APPEND, + .size = 5 * 1024 * 1024}, + { + .name = "nand.rootfs", + .offset = MTDPART_OFS_APPEND, + .size = 96 * 1024 * 1024}, + { + .name = "nand.configure", + .offset = MTDPART_OFS_APPEND, + .size = 8 * 1024 * 1024}, + { + .name = "nand.userfs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL}, +}; + +static struct flash_platform_data mxc_nand_data = { + .parts = mxc_nand_partitions, + .nr_parts = ARRAY_SIZE(mxc_nand_partitions), + .width = 1, +}; + +static struct platform_device mxc_nand_mtd_device = { + .name = "mxc_nandv2_flash", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_nand_data, + }, +}; + +static void mxc_init_nand_mtd(void) +{ + if (__raw_readl(MXC_CCM_RCSR) & MXC_CCM_RCSR_NF16B) + mxc_nand_data.width = 2; + + platform_device_register(&mxc_nand_mtd_device); +} +#else +static inline void mxc_init_nand_mtd(void) +{ +} +#endif + +static struct mxc_lcd_platform_data lcd_data = { + .io_reg = "LCD" +}; + +static struct platform_device lcd_dev = { + .name = "lcd_claa", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = (void *)&lcd_data, + }, +}; + +static void mxc_init_lcd(void) +{ + platform_device_register(&lcd_dev); +} + +#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) +/* mxc lcd driver */ +static struct platform_device mxc_fb_device = { + .name = "mxc_sdc_fb", + .id = 0, + .dev = { + .release = mxc_nop_release, + .coherent_dma_mask = 0xFFFFFFFF, + }, +}; + +static void mxc_init_fb(void) +{ + (void)platform_device_register(&mxc_fb_device); +} +#else +static inline void mxc_init_fb(void) +{ +} +#endif + +#if defined(CONFIG_BACKLIGHT_MXC) +static struct platform_device mxcbl_devices[] = { +#if defined(CONFIG_BACKLIGHT_MXC_IPU) || defined(CONFIG_BACKLIGHT_MXC_IPU_MODULE) + { + .name = "mxc_ipu_bl", + .id = 0, + .dev = { + .platform_data = (void *)3, /* DISP # for this backlight */ + }, + } +#endif +}; + +static inline void mxc_init_bl(void) +{ + int i; + for (i = 0; i < ARRAY_SIZE(mxcbl_devices); i++) { + platform_device_register(&mxcbl_devices[i]); + } +} +#else +static inline void mxc_init_bl(void) +{ +} +#endif + +#if defined(CONFIG_MXC_MLB) || defined(CONFIG_MXC_MLB_MODULE) +static struct resource mlb_resource[] = { + [0] = { + .start = MLB_BASE_ADDR, + .end = MLB_BASE_ADDR + 0x300, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_MLB, + .end = MXC_INT_MLB, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mxc_mlb_platform_data mlb_data = { + .buf_address = IRAM_BASE_ADDR_VIRT + MLB_IRAM_ADDR_OFFSET, + .phy_address = IRAM_BASE_ADDR + MLB_IRAM_ADDR_OFFSET, + .reg_nvcc = "VVIDEO", + .mlb_clk = "mlb_clk", +}; + +static struct platform_device mlb_dev = { + .name = "mxc_mlb", + .id = 0, + .dev = { + .platform_data = &mlb_data, + }, + .num_resources = ARRAY_SIZE(mlb_resource), + .resource = mlb_resource, +}; + +static inline void mxc_init_mlb(void) +{ + platform_device_register(&mlb_dev); +} +#else +static inline void mxc_init_mlb(void) +{ +} +#endif + +#if defined(CONFIG_SDIO_UNIFI_FS) || defined(CONFIG_SDIO_UNIFI_FS_MODULE) +static void mxc_unifi_hardreset(void) +{ + pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 1, 0); + msleep(100); + pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 1, 1); +} + +static void mxc_unifi_enable(int en) +{ + if (en) { + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 5, 1); + msleep(10); + } else + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 5, 0); +} + +static struct mxc_unifi_platform_data unifi_data = { + .hardreset = mxc_unifi_hardreset, + .enable = mxc_unifi_enable, + .reg_gpo1 = "GPO2", + .reg_gpo2 = "GPO3", + .reg_1v5_ana_bb = "PWGT1", + .reg_vdd_vpa = "VAUDIO", + .reg_1v5_dd = "SW1", + .host_id = 1, +}; + +struct mxc_unifi_platform_data *get_unifi_plat_data(void) +{ + return &unifi_data; +} +#else +struct mxc_unifi_platform_data *get_unifi_plat_data(void) +{ + return NULL; +} +#endif + +EXPORT_SYMBOL(get_unifi_plat_data); + +static struct mxc_tsc_platform_data tsc2007_data = { + .vdd_reg = "SW1", + .penup_threshold = 30, + .active = gpio_tsc_active, + .inactive = gpio_tsc_inactive, +}; + +static struct mxc_camera_platform_data camera_data = { + .core_regulator = "SW1", + .io_regulator = "VAUDIO", + .analog_regulator = NULL, + .gpo_regulator = "PWGT1", + .mclk = 27000000, +}; + +static struct i2c_board_info mxc_i2c_board_info[] __initdata = { + { + .type = "mc9sdz60", + .addr = 0x69, + }, + { + .type = "max8660", + .addr = 0x34, + }, +#if defined(CONFIG_I2C_SLAVE_CLIENT) + { + .type = "i2c-slave-client", + .addr = 0x55, + }, +#endif +}; + +static struct spi_board_info mxc_spi_board_info[] __initdata = { + { + .modalias = "pmic_spi", + .irq = IOMUX_TO_IRQ(MX35_PIN_ATA_IORDY), + .max_speed_hz = 4000000, /* max spi SCK clock speed in HZ */ + .bus_num = 1, + .chip_select = 0, + }, +}; + +#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) +static struct resource smsc911x_resources[] = { + { + .start = LAN9217_BASE_ADDR, + .end = LAN9217_BASE_ADDR + 0x100, + .flags = IORESOURCE_MEM, + }, + { + .start = LAN9217_IRQ, + .end = LAN9217_IRQ, + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device mxc_smsc911x_device = { + .name = "smsc911x", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, +}; + +static void mxc_init_enet(void) +{ + platform_device_register(&mxc_smsc911x_device); +} +#else +static inline void mxc_init_enet(void) +{ +} +#endif + +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) +unsigned int expio_intr_fec; + +EXPORT_SYMBOL(expio_intr_fec); +#endif + +static struct mxc_mmc_platform_data mmc_data = { + .ocr_mask = MMC_VDD_31_32 | MMC_VDD_32_33, + .min_clk = 150000, + .max_clk = 52000000, + .card_inserted_state = 1, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "sdhc_clk", + .power_mmc = "VGEN2", +}; + +static struct mxc_mmc_platform_data mmc_data_3 = { + .ocr_mask = MMC_VDD_31_32 | MMC_VDD_32_33, + .min_clk = 400000, + .max_clk = 52000000, + .card_inserted_state = 1, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "sdhc_clk", +}; + +#define MMC_SDHC3_DETECT_IRQ IOMUX_TO_IRQ(MX35_PIN_USBOTG_PWR) + +/*! + * Resource definition for the SDHC1 + */ +static struct resource mxcsdhc1_resources[] = { + [0] = { + .start = MMC_SDHC1_BASE_ADDR, + .end = MMC_SDHC1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_MMC_SDHC1, + .end = MXC_INT_MMC_SDHC1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 65, + .end = 65, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Device Definition for MXC SDHC1 */ +static struct platform_device mxcsdhc1_device = { + .name = "mxsdhci", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc_data, + }, + .num_resources = ARRAY_SIZE(mxcsdhc1_resources), + .resource = mxcsdhc1_resources, +}; + +static struct resource mxcsdhc3_resources[] = { + [0] = { + .start = MMC_SDHC3_BASE_ADDR, + .end = MMC_SDHC3_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_MMC_SDHC3, + .end = MXC_INT_MMC_SDHC3, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = MMC_SDHC3_DETECT_IRQ, + .end = MMC_SDHC3_DETECT_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Device Definition for MXC SDHC3 */ +static struct platform_device mxcsdhc3_device = { + .name = "mxsdhci", + .id = 2, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc_data_3, + }, + .num_resources = ARRAY_SIZE(mxcsdhc3_resources), + .resource = mxcsdhc3_resources, +}; + +static inline void mxc_init_mmc(void) +{ + printk("mxc_init_mmc\n"); + (void)platform_device_register(&mxcsdhc1_device); + (void)platform_device_register(&mxcsdhc3_device); +} + +#ifdef CONFIG_MXC_PSEUDO_IRQS +/*! Device Definition for MXC SDHC1 */ +static struct platform_device mxc_pseudo_irq_device = { + .name = "mxc_pseudo_irq", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, +}; + +static inline int mxc_init_pseudo_irq(void) +{ + return platform_device_register(&mxc_pseudo_irq_device); +} + +late_initcall(mxc_init_pseudo_irq); + +/*! + * Power Key interrupt handler. + */ +static irqreturn_t power_key_int(int irq, void *dev_id) +{ + pr_info(KERN_INFO "on-off key pressed\n"); + return 0; +} + +/*! + * Power Key initialization. + */ +static int __init mxc_init_power_key(void) +{ + if (!board_is_mx35(BOARD_REV_2)) { + /*Set power key as wakeup resource */ + int irq, ret; + irq = MXC_PSEUDO_IRQ_POWER_KEY; + set_irq_type(irq, IRQF_TRIGGER_RISING); + ret = request_irq(irq, power_key_int, 0, "power_key", 0); + if (ret) + pr_info("register on-off key interrupt failed\n"); + else + enable_irq_wake(irq); + return ret; + } + return 0; +} + +late_initcall(mxc_init_power_key); +#endif + +/*! + * the event handler for power on event + */ +static void power_on_evt_handler(void) +{ + pr_info("pwr on event1 is received \n"); +} + +/*! + * pmic board initialization code + */ +static int __init mxc_init_pmic(void) +{ + unsigned int value; + + /* Battery charger default settings */ + /* current limit = 1200mA, PLIM = 1000mw, disable auto charge */ + value = 0x210068; + pmic_write_reg(REG_CHARGE, value, 0x018078); + + return 0; +} + +late_initcall(mxc_init_pmic); + +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mxc_cpu_init(); + +#ifdef CONFIG_DISCONTIGMEM + do { + int nid; + mi->nr_banks = MXC_NUMNODES; + for (nid = 0; nid < mi->nr_banks; nid++) + SET_NODE(mi, nid); + } while (0); +#endif +} + +/*! + * fixup for mx35 3stack board v1.0 (MAX8660) + */ +static void mx35_3stack_fixup_for_board_v1(void) +{ +} + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + mxc_cpu_common_init(); + + mxc_clocks_init(); + early_console_setup(saved_command_line); + mxc_gpio_init(); + mxc_init_devices(); + if (!board_is_mx35(BOARD_REV_2)) + mx35_3stack_fixup_for_board_v1(); + mx35_3stack_gpio_init(); + mxc_init_enet(); + mxc_init_nor_mtd(); + mxc_init_nand_mtd(); + + mxc_init_lcd(); + + i2c_register_board_info(0, mxc_i2c_board_info, + ARRAY_SIZE(mxc_i2c_board_info)); + + spi_register_board_info(mxc_spi_board_info, + ARRAY_SIZE(mxc_spi_board_info)); + mxc_init_mmc(); +} + +#define PLL_PCTL_REG(brmo, pd, mfd, mfi, mfn) \ + (((brmo) << 31) + (((pd) - 1) << 26) + (((mfd) - 1) << 16) + \ + ((mfi) << 10) + mfn) + +/* For 24MHz input clock */ +#define PLL_665MHZ PLL_PCTL_REG(1, 1, 48, 13, 41) +#define PLL_532MHZ PLL_PCTL_REG(1, 1, 12, 11, 1) +#define PLL_399MHZ PLL_PCTL_REG(0, 1, 16, 8, 5) + +/* working point(wp): 0,1 - 133MHz; 2,3 - 266MHz; 4,5 - 399MHz;*/ +/* auto input clock table */ +static struct cpu_wp cpu_wp_auto[] = { + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 133000000, + .pdr0_reg = (0x2 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 133000000, + .pdr0_reg = (0x6 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 266000000, + .pdr0_reg = (0x1 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 266000000, + .pdr0_reg = (0x5 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 399000000, + .pdr0_reg = (0x0 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 399000000, + .pdr0_reg = (0x6 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),}, +}; + +/* consumer input clock table */ +static struct cpu_wp cpu_wp_con[] = { + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 133000000, + .pdr0_reg = (0x6 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 133000000, + .pdr0_reg = (0xE << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 266000000, + .pdr0_reg = (0x2 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 266000000, + .pdr0_reg = (0xA << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 399000000, + .pdr0_reg = (0x1 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 399000000, + .pdr0_reg = (0x9 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 532000000, + .pdr0_reg = (0x0 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 532000000, + .pdr0_reg = (0x8 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_665MHZ, + .pll_rate = 665000000, + .cpu_rate = 665000000, + .pdr0_reg = (0x7 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, +}; + +struct cpu_wp *get_cpu_wp(int *wp) +{ + if (cpu_is_mx35_rev(CHIP_REV_2_0) >= 1) { + *wp = 9; + return cpu_wp_con; + } else { + if (__raw_readl(MXC_CCM_PDR0) & MXC_CCM_PDR0_AUTO_CON) { + *wp = 9; + return cpu_wp_con; + } else { + *wp = 6; + return cpu_wp_auto; + } + } +} + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX35_3DS data structure. + */ +/* *INDENT-OFF* */ +MACHINE_START(MX35_LUIGI, "Freescale MX35 3-Stack Board") + /* Maintainer: Freescale Semiconductor, Inc. */ + .phys_io = AIPS1_BASE_ADDR, + .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .fixup = fixup_mxc_board, + .map_io = mxc_map_io, + .init_irq = mxc_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff -urN linux-2.6.26/arch/arm/mach-mx35/mx35_3stack_cpld.c linux-2.6.26-lab126/arch/arm/mach-mx35/mx35_3stack_cpld.c --- linux-2.6.26/arch/arm/mach-mx35/mx35_3stack_cpld.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/mx35_3stack_cpld.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,159 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "board-mx35_3stack.h" +#include "crm_regs.h" +#include "iomux.h" + +/*! + * @file mach-mx35/mx35_3stack_cpld.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX35 + */ +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) +{ + u32 expio_irq; + u32 index, mask; + desc->chip->mask(irq); /* irq = gpio irq number */ + + index = __raw_readw(mx35_3stack_board_io + INTR_STATUS_REG); + mask = __raw_readw(mx35_3stack_board_io + INTR_MASK_REG); + + if (unlikely(!(index & (~mask)))) { + printk(KERN_ERR "\nEXPIO: Spurious interrupt:0x%0x\n\n", index); + pr_info("CPLD IMR(0x38)=0x%x, PENDING(0x28)=0x%x\n", mask, + index); + goto out; + } + index = index & (~mask); + expio_irq = MXC_EXP_IO_BASE; + for (; index != 0; index >>= 1, expio_irq++) { + struct irq_desc *d; + if ((index & 1) == 0) + continue; + d = irq_desc + expio_irq; + if (unlikely(!(d->handle_irq))) { + printk(KERN_ERR "\nEXPIO irq: %d unhandeled\n", + expio_irq); + BUG(); /* oops */ + } + d->handle_irq(expio_irq, d); + } + + out: + desc->chip->ack(irq); + desc->chip->unmask(irq); +} + +/* + * Disable an expio pin's interrupt by setting the bit in the imr. + * @param irq an expio virtual irq number + */ +static void expio_mask_irq(u32 irq) +{ + u16 reg, expio = MXC_IRQ_TO_EXPIO(irq); + + reg = __raw_readw(mx35_3stack_board_io + INTR_MASK_REG); + /* mask the interrupt */ + __raw_writew(reg | (1 << expio), mx35_3stack_board_io + INTR_MASK_REG); +} + +/* + * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. + * @param irq an expanded io virtual irq number + */ +static void expio_ack_irq(u32 irq) +{ + u32 expio = MXC_IRQ_TO_EXPIO(irq); + /* clear the interrupt status */ + __raw_writew(1 << expio, mx35_3stack_board_io + INTR_RESET_REG); + __raw_writew(0, mx35_3stack_board_io + INTR_RESET_REG); + /* mask the interrupt */ + expio_mask_irq(irq); +} + +/* + * Enable a expio pin's interrupt by clearing the bit in the imr. + * @param irq a expio virtual irq number + */ +static void expio_unmask_irq(u32 irq) +{ + u16 reg, expio = MXC_IRQ_TO_EXPIO(irq); + + reg = __raw_readw(mx35_3stack_board_io + INTR_MASK_REG); + /* unmask the interrupt */ + __raw_writew(reg & (~(1 << expio)), + mx35_3stack_board_io + INTR_MASK_REG); +} + +static struct irq_chip expio_irq_chip = { + .ack = expio_ack_irq, + .mask = expio_mask_irq, + .unmask = expio_unmask_irq, +}; + +static int __init mxc_expio_init(void) +{ + int i; + + mx35_3stack_board_io = (u32) ioremap(BOARD_IO_ADDR, SZ_4K); + if (mx35_3stack_board_io == 0) + return -ENOMEM; + + if ((__raw_readw(mx35_3stack_board_io + MAGIC_NUMBER1_REG) != 0xAAAA) || + (__raw_readw(mx35_3stack_board_io + MAGIC_NUMBER2_REG) != 0x5555)) + return -ENODEV; + + pr_info("3-Stack Debug board detected, rev = 0x%04X\n", + readw(mx35_3stack_board_io + CPLD_CODE_VER_REG)); + + /* + * Configure INT line as GPIO input + */ + mxc_request_iomux(EXPIO_PARENT_INT, MUX_CONFIG_FUNC); + mxc_set_gpio_direction(EXPIO_PARENT_INT, 1); + + /* disable the interrupt and clear the status */ + __raw_writew(0, mx35_3stack_board_io + INTR_MASK_REG); + __raw_writew(0xFFFF, mx35_3stack_board_io + INTR_RESET_REG); + __raw_writew(0, mx35_3stack_board_io + INTR_RESET_REG); + __raw_writew(0x1F, mx35_3stack_board_io + INTR_MASK_REG); + for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); + i++) { + set_irq_chip(i, &expio_irq_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + set_irq_type(IOMUX_TO_IRQ(EXPIO_PARENT_INT), IRQT_LOW); + set_irq_chained_handler(IOMUX_TO_IRQ(EXPIO_PARENT_INT), + mxc_expio_irq_handler); + return 0; +} + +arch_initcall(mxc_expio_init); diff -urN linux-2.6.26/arch/arm/mach-mx35/mx35_3stack_gpio.c linux-2.6.26-lab126/arch/arm/mach-mx35/mx35_3stack_gpio.c --- linux-2.6.26/arch/arm/mach-mx35/mx35_3stack_gpio.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/mx35_3stack_gpio.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,1353 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "board-mx35_3stack.h" +#include "iomux.h" + +/*! + * @file mach-mx35/mx35_3stack_gpio.c + * + * @brief This file contains all the GPIO setup functions for the board. + * + * @ingroup GPIO_MX35 + */ + +/*! + * This system-wise GPIO function initializes the pins during system startup. + * All the statically linked device drivers should put the proper GPIO + * initialization code inside this function. It is called by \b fixup_mx31ads() + * during system startup. This function is board specific. + */ +void mx35_3stack_gpio_init(void) +{ + /* config CS5 */ + mxc_request_iomux(MX35_PIN_CS5, MUX_CONFIG_FUNC); + +} + +/*! + * Setup GPIO for a UART port to be active + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_active(int port, int no_irda) +{ + /* + * Configure the IOMUX control registers for the UART signals + */ + switch (port) { + /* UART 1 IOMUX Configs */ + case 0: + mxc_request_iomux(MX35_PIN_RXD1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_TXD1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_RTS1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CTS1, MUX_CONFIG_FUNC); + + mxc_iomux_set_pad(MX35_PIN_RXD1, + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX35_PIN_TXD1, + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_RTS1, + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX35_PIN_CTS1, + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); + + break; + /* UART 2 IOMUX Configs */ + case 1: + mxc_request_iomux(MX35_PIN_TXD2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_RXD2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_RTS2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CTS2, MUX_CONFIG_FUNC); + mxc_iomux_set_pad(MX35_PIN_RXD2, + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX35_PIN_TXD2, + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_RTS2, + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX35_PIN_CTS2, + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); + break; + /* UART 3 IOMUX Configs */ + case 2: + mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_ALT2); + mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_ALT2); + mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_ALT2); + mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_ALT2); + + mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX35_PIN_FEC_COL, + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); + + mxc_iomux_set_input(MUX_IN_UART3_UART_RTS_B, INPUT_CTL_PATH2); + mxc_iomux_set_input(MUX_IN_UART3_UART_RXD_MUX, INPUT_CTL_PATH3); + break; + default: + break; + } + +} + +EXPORT_SYMBOL(gpio_uart_active); + +/*! + * Setup GPIO for a UART port to be inactive + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_inactive(int port, int no_irda) +{ + switch (port) { + case 0: + mxc_request_gpio(MX35_PIN_RXD1); + mxc_request_gpio(MX35_PIN_TXD1); + mxc_request_gpio(MX35_PIN_RTS1); + mxc_request_gpio(MX35_PIN_CTS1); + + mxc_free_iomux(MX35_PIN_RXD1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_TXD1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_RTS1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_CTS1, MUX_CONFIG_GPIO); + break; + case 1: + mxc_request_gpio(MX35_PIN_RXD2); + mxc_request_gpio(MX35_PIN_TXD2); + mxc_request_gpio(MX35_PIN_RTS2); + mxc_request_gpio(MX35_PIN_CTS2); + + mxc_free_iomux(MX35_PIN_RXD2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_TXD2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_RTS2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_CTS2, MUX_CONFIG_GPIO); + break; + case 2: + mxc_request_gpio(MX35_PIN_FEC_TX_CLK); + mxc_request_gpio(MX35_PIN_FEC_RX_CLK); + mxc_request_gpio(MX35_PIN_FEC_COL); + mxc_request_gpio(MX35_PIN_FEC_RX_DV); + + mxc_free_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_GPIO); + + mxc_iomux_set_input(MUX_IN_UART3_UART_RTS_B, INPUT_CTL_PATH0); + mxc_iomux_set_input(MUX_IN_UART3_UART_RXD_MUX, INPUT_CTL_PATH0); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_uart_inactive); + +/*! + * Configure the IOMUX GPR register to receive shared SDMA UART events + * + * @param port a UART port + */ +void config_uartdma_event(int port) +{ +} + +EXPORT_SYMBOL(config_uartdma_event); + +void gpio_fec_active(void) +{ + mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC); + +#define FEC_PAD_CTL_COMMON (PAD_CTL_DRV_3_3V|PAD_CTL_PUE_PUD| \ + PAD_CTL_ODE_CMOS|PAD_CTL_DRV_NORMAL|PAD_CTL_SRE_SLOW) + mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, FEC_PAD_CTL_COMMON | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_COL, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS | + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS | + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_MDC, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS | + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU); + mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS | + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_CRS, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS | + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS | + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS | + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); +#undef FEC_PAD_CTL_COMMON + /* Pull GPIO1_5 to be high for routing signal to FEC */ + if (board_is_mx35(BOARD_REV_2)) { + mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX35_PIN_COMPARE, PAD_CTL_DRV_NORMAL | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | + PAD_CTL_SRE_SLOW); + mxc_set_gpio_direction(MX35_PIN_COMPARE, 0); + mxc_set_gpio_dataout(MX35_PIN_COMPARE, 1); + } + + /* FEC enable */ + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 2, 1); + /* FEC reset */ + pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 7, 0); + msleep(10); + pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 7, 1); + msleep(100); +} + +EXPORT_SYMBOL(gpio_fec_active); + +void gpio_fec_inactive(void) +{ + mxc_request_gpio(MX35_PIN_FEC_TX_CLK); + mxc_request_gpio(MX35_PIN_FEC_RX_CLK); + mxc_request_gpio(MX35_PIN_FEC_RX_DV); + mxc_request_gpio(MX35_PIN_FEC_COL); + mxc_request_gpio(MX35_PIN_FEC_RDATA0); + mxc_request_gpio(MX35_PIN_FEC_TDATA0); + mxc_request_gpio(MX35_PIN_FEC_TX_EN); + mxc_request_gpio(MX35_PIN_FEC_MDC); + mxc_request_gpio(MX35_PIN_FEC_MDIO); + mxc_request_gpio(MX35_PIN_FEC_TX_ERR); + mxc_request_gpio(MX35_PIN_FEC_RX_ERR); + mxc_request_gpio(MX35_PIN_FEC_CRS); + mxc_request_gpio(MX35_PIN_FEC_RDATA1); + mxc_request_gpio(MX35_PIN_FEC_TDATA1); + mxc_request_gpio(MX35_PIN_FEC_RDATA2); + mxc_request_gpio(MX35_PIN_FEC_TDATA2); + mxc_request_gpio(MX35_PIN_FEC_RDATA3); + mxc_request_gpio(MX35_PIN_FEC_TDATA3); + + mxc_free_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_GPIO); + + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 2, 0); + + /* Free GPIO1_5 */ + if (board_is_mx35(BOARD_REV_2)) + mxc_free_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO); +} + +EXPORT_SYMBOL(gpio_fec_inactive); + +/*! + * Setup GPIO for an I2C device to be active + * + * @param i2c_num an I2C device + */ +void gpio_i2c_active(int i2c_num) +{ + +#define PAD_CONFIG (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain) + + switch (i2c_num) { + case 0: + mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION); + + mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, PAD_CONFIG); + mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, PAD_CONFIG); + break; + case 1: + mxc_request_iomux(MX35_PIN_I2C2_CLK, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_I2C2_DAT, MUX_CONFIG_SION); + + mxc_iomux_set_pad(MX35_PIN_I2C2_CLK, PAD_CONFIG); + mxc_iomux_set_pad(MX35_PIN_I2C2_DAT, PAD_CONFIG); + + break; + case 2: + mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1); + mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX35_PIN_TX3_RX2, PAD_CONFIG); + mxc_iomux_set_pad(MX35_PIN_TX2_RX3, PAD_CONFIG); + break; + default: + break; + } + +#undef PAD_CONFIG + +} + +EXPORT_SYMBOL(gpio_i2c_active); + +/*! + * Setup GPIO for an I2C device to be inactive + * + * @param i2c_num an I2C device + */ +void gpio_i2c_inactive(int i2c_num) +{ + switch (i2c_num) { + case 0: + break; + case 1: + break; + case 2: + mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_GPIO); + mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_GPIO); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_i2c_inactive); + +/*! + * Setup GPIO for a CSPI device to be active + * + * @param cspi_mod an CSPI device + */ +void gpio_spi_active(int cspi_mod) +{ + switch (cspi_mod) { + case 0: + /* SPI1 */ + mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSPI1_SPI_RDY, MUX_CONFIG_FUNC); + + mxc_iomux_set_pad(MX35_PIN_CSPI1_MOSI, + PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | + PAD_CTL_100K_PD | PAD_CTL_DRV_NORMAL); + mxc_iomux_set_pad(MX35_PIN_CSPI1_MISO, + PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | + PAD_CTL_100K_PD | PAD_CTL_DRV_NORMAL); + mxc_iomux_set_pad(MX35_PIN_CSPI1_SS0, + PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | + PAD_CTL_100K_PU | PAD_CTL_ODE_CMOS | + PAD_CTL_DRV_NORMAL); + mxc_iomux_set_pad(MX35_PIN_CSPI1_SS1, + PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | + PAD_CTL_100K_PU | PAD_CTL_ODE_CMOS | + PAD_CTL_DRV_NORMAL); + mxc_iomux_set_pad(MX35_PIN_CSPI1_SCLK, + PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | + PAD_CTL_100K_PD | PAD_CTL_DRV_NORMAL); + mxc_iomux_set_pad(MX35_PIN_CSPI1_SPI_RDY, + PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | + PAD_CTL_100K_PU | PAD_CTL_DRV_NORMAL); + break; + case 1: + /* SPI2 */ + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_spi_active); + +/*! + * Setup GPIO for a CSPI device to be inactive + * + * @param cspi_mod a CSPI device + */ +void gpio_spi_inactive(int cspi_mod) +{ + switch (cspi_mod) { + case 0: + /* SPI1 */ + mxc_request_gpio(MX35_PIN_CSPI1_MOSI); + mxc_request_gpio(MX35_PIN_CSPI1_MISO); + mxc_request_gpio(MX35_PIN_CSPI1_SS0); + mxc_request_gpio(MX35_PIN_CSPI1_SS1); + mxc_request_gpio(MX35_PIN_CSPI1_SCLK); + mxc_request_gpio(MX35_PIN_CSPI1_SPI_RDY); + + mxc_free_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_CSPI1_SPI_RDY, MUX_CONFIG_GPIO); + break; + case 1: + /* SPI2 */ + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_spi_inactive); + +/*! + * Setup GPIO for LCD to be active + */ +void gpio_lcd_active(void) +{ + mxc_request_iomux(MX35_PIN_LD0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_LD1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_LD2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_LD3, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_LD4, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_LD5, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_LD6, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_LD7, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_LD8, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_LD9, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_LD10, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_LD11, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_LD12, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_LD13, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_LD14, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_LD15, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_LD16, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_LD17, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_D3_VSYNC, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_D3_HSYNC, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_D3_FPSHIFT, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_D3_DRDY, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CONTRAST, MUX_CONFIG_FUNC); +} + +EXPORT_SYMBOL(gpio_lcd_active); + +/*! + * Setup GPIO for LCD to be inactive + */ +void gpio_lcd_inactive(void) +{ +} + +EXPORT_SYMBOL(gpio_lcd_inactive); + +/*! + * Setup pin for touchscreen + */ +void gpio_tsc_active(void) +{ + unsigned int pad_val = PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU; + mxc_request_iomux(MX35_PIN_CAPTURE, MUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX35_PIN_CAPTURE, pad_val); + mxc_set_gpio_direction(MX35_PIN_CAPTURE, 1); +} + +/*! + * Release pin for touchscreen + */ +void gpio_tsc_inactive(void) +{ + mxc_free_iomux(MX35_PIN_CAPTURE, MUX_CONFIG_GPIO); +} + +/*! + * Setup GPIO for SDHC to be active + * + * @param module SDHC module number + */ +void gpio_sdhc_active(int module) +{ + unsigned int pad_val; + + switch (module) { + case 0: + mxc_request_iomux(MX35_PIN_SD1_CLK, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD1_CMD, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD1_DATA0, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD1_DATA1, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD1_DATA2, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD1_DATA3, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); +#if defined(CONFIG_SDIO_UNIFI_FS) || defined(CONFIG_SDIO_UNIFI_FS_MODULE) +#else + /* MUX4_CTR , 0: SD2 to WIFI, 1:SD2 to SD1 8bit */ + if (board_is_mx35(BOARD_REV_2)) + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, + 7, 1); + mxc_request_iomux(MX35_PIN_SD2_CMD, + MUX_CONFIG_ALT2 | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD2_CLK, + MUX_CONFIG_ALT2 | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD2_DATA0, + MUX_CONFIG_ALT2 | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD2_DATA1, + MUX_CONFIG_ALT2 | MUX_CONFIG_SION); +#endif + + pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX | + PAD_CTL_47K_PU | PAD_CTL_SRE_FAST; + mxc_iomux_set_pad(MX35_PIN_SD1_CMD, pad_val); + mxc_iomux_set_pad(MX35_PIN_SD1_DATA0, pad_val); + mxc_iomux_set_pad(MX35_PIN_SD1_DATA1, pad_val); + mxc_iomux_set_pad(MX35_PIN_SD1_DATA2, pad_val); + pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_MAX | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST; + mxc_iomux_set_pad(MX35_PIN_SD1_CLK, pad_val); + pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX | + PAD_CTL_100K_PU | PAD_CTL_SRE_FAST; + mxc_iomux_set_pad(MX35_PIN_SD1_DATA3, pad_val); +#if defined(CONFIG_SDIO_UNIFI_FS) || defined(CONFIG_SDIO_UNIFI_FS_MODULE) +#else + pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX | + PAD_CTL_47K_PU | PAD_CTL_SRE_FAST; + mxc_iomux_set_pad(MX35_PIN_SD2_CMD, pad_val); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA0, pad_val); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA1, pad_val); + pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_MAX | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST; + mxc_iomux_set_pad(MX35_PIN_SD2_CLK, pad_val); +#endif + break; + case 1: + /* MUX4_CTR , 0: SD2 to WIFI, 1:SD2 to SD1 8bit */ + if (board_is_mx35(BOARD_REV_2)) + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, + 7, 0); + mxc_request_iomux(MX35_PIN_SD2_CLK, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD2_CMD, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD2_DATA0, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD2_DATA1, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD2_DATA2, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD2_DATA3, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + + pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX | + PAD_CTL_47K_PU | PAD_CTL_SRE_FAST; + + mxc_iomux_set_pad(MX35_PIN_SD2_CLK, pad_val); + mxc_iomux_set_pad(MX35_PIN_SD2_CMD, pad_val); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA0, pad_val); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA1, pad_val); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA2, pad_val); + + pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX | + PAD_CTL_100K_PU | PAD_CTL_SRE_FAST; + + mxc_iomux_set_pad(MX35_PIN_SD2_DATA3, pad_val); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_sdhc_active); + +/*! + * Setup GPIO for SDHC1 to be inactive + * + * @param module SDHC module number + */ +void gpio_sdhc_inactive(int module) +{ + switch (module) { + case 0: + mxc_free_iomux(MX35_PIN_SD1_CLK, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_free_iomux(MX35_PIN_SD1_CMD, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_free_iomux(MX35_PIN_SD1_DATA0, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_free_iomux(MX35_PIN_SD1_DATA1, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_free_iomux(MX35_PIN_SD1_DATA2, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_free_iomux(MX35_PIN_SD1_DATA3, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_free_iomux(MX35_PIN_SD2_CMD, + MUX_CONFIG_ALT2 | MUX_CONFIG_SION); + mxc_free_iomux(MX35_PIN_SD2_CLK, + MUX_CONFIG_ALT2 | MUX_CONFIG_SION); + mxc_free_iomux(MX35_PIN_SD2_DATA0, + MUX_CONFIG_ALT2 | MUX_CONFIG_SION); + mxc_free_iomux(MX35_PIN_SD2_DATA1, + MUX_CONFIG_ALT2 | MUX_CONFIG_SION); + + mxc_iomux_set_pad(MX35_PIN_SD1_CLK, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX35_PIN_SD1_CMD, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX35_PIN_SD1_DATA0, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX35_PIN_SD1_DATA1, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX35_PIN_SD1_DATA2, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX35_PIN_SD1_DATA3, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX35_PIN_SD2_CMD, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX35_PIN_SD2_CLK, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA0, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA1, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + break; + case 1: + mxc_free_iomux(MX35_PIN_SD2_CLK, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_free_iomux(MX35_PIN_SD2_CMD, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_free_iomux(MX35_PIN_SD2_DATA0, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_free_iomux(MX35_PIN_SD2_DATA1, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_free_iomux(MX35_PIN_SD2_DATA2, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_free_iomux(MX35_PIN_SD2_DATA3, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + + mxc_iomux_set_pad(MX35_PIN_SD2_CLK, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX35_PIN_SD2_CMD, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA0, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA1, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA2, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA3, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_sdhc_inactive); + +/* + * Probe for the card. If present the GPIO data would be set. + */ +unsigned int sdhc_get_card_det_status(struct device *dev) +{ + unsigned int ret; + + if (to_platform_device(dev)->id == 0) { + if (0 != pmic_gpio_get_designation_bit_val(2, &ret)) + printk(KERN_ERR "Get cd status error."); + return ret; + } else { /* config the det pin for SDHC2 */ + return 0; + } +} + +EXPORT_SYMBOL(sdhc_get_card_det_status); + +/*! + * Get pin value to detect write protection + */ +int sdhc_write_protect(struct device *dev) +{ + unsigned int rc = 0; + + if (0 != pmic_gpio_get_designation_bit_val(3, &rc)) + printk(KERN_ERR "Get wp status error."); + return rc; +} + +EXPORT_SYMBOL(sdhc_write_protect); + +/* + * USB Host2 + */ +int gpio_usbh2_active(void) +{ + if (board_is_mx35(BOARD_REV_2)) { + /* MUX3_CTR to be low for USB Host2 DP&DM */ + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 6, 0); + /* CAN_PWDN to be high for USB Host2 Power&OC */ + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 1, 1); + } + + mxc_request_iomux(MX35_PIN_I2C2_CLK, MUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX35_PIN_I2C2_CLK, 0x0040); + + mxc_request_iomux(MX35_PIN_I2C2_DAT, MUX_CONFIG_ALT2); + mxc_iomux_set_input(MUX_IN_USB_UH2_USB_OC, INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX35_PIN_I2C2_DAT, 0x01c0); + + return 0; +} + +EXPORT_SYMBOL(gpio_usbh2_active); + +void gpio_usbh2_inactive(void) +{ + mxc_request_gpio(MX35_PIN_I2C2_DAT); + mxc_free_iomux(MX35_PIN_I2C2_DAT, MUX_CONFIG_GPIO); + mxc_request_gpio(MX35_PIN_I2C2_CLK); + mxc_free_iomux(MX35_PIN_I2C2_CLK, MUX_CONFIG_GPIO); +} + +EXPORT_SYMBOL(gpio_usbh2_inactive); + +/* + * USB OTG UTMI + */ +int gpio_usbotg_utmi_active(void) +{ + mxc_request_iomux(MX35_PIN_USBOTG_PWR, MUX_CONFIG_FUNC); + mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, 0x0040); + mxc_request_iomux(MX35_PIN_USBOTG_OC, MUX_CONFIG_FUNC); + mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, 0x01c0); + + return 0; +} + +EXPORT_SYMBOL(gpio_usbotg_utmi_active); + +void gpio_usbotg_utmi_inactive(void) +{ + mxc_request_gpio(MX35_PIN_USBOTG_PWR); + mxc_free_iomux(MX35_PIN_USBOTG_PWR, MUX_CONFIG_GPIO); + mxc_request_gpio(MX35_PIN_USBOTG_OC); + mxc_free_iomux(MX35_PIN_USBOTG_OC, MUX_CONFIG_GPIO); +} + +EXPORT_SYMBOL(gpio_usbotg_utmi_inactive); + +void gpio_sensor_active(void) +{ + /*CSI D6 */ + mxc_request_iomux(MX35_PIN_TX1, MUX_CONFIG_ALT6); + /*CSI D7 */ + mxc_request_iomux(MX35_PIN_TX0, MUX_CONFIG_ALT6); + mxc_request_iomux(MX35_PIN_CSI_D8, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_D9, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_D10, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_D11, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_D12, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_D13, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_D14, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_D15, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_HSYNC, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_MCLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_PIXCLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_VSYNC, MUX_CONFIG_FUNC); +} + +EXPORT_SYMBOL(gpio_sensor_active); + +void gpio_sensor_inactive(void) +{ + mxc_request_iomux(MX35_PIN_TX1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_TX0, MUX_CONFIG_FUNC); +} + +EXPORT_SYMBOL(gpio_sensor_inactive); + +/*! + * Setup GPIO for spdif tx/rx to be active + */ +void gpio_spdif_active(void) +{ + /* SPDIF OUT */ + mxc_request_iomux(MX35_PIN_STXD5, MUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX35_PIN_STXD5, PAD_CTL_PKE_NONE | PAD_CTL_PUE_PUD); + /* SPDIF IN */ + mxc_request_iomux(MX35_PIN_SRXD5, MUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX35_PIN_SRXD5, PAD_CTL_PKE_ENABLE + | PAD_CTL_100K_PU | PAD_CTL_HYS_SCHMITZ); + /* SPDIF ext clock */ + mxc_request_iomux(MX35_PIN_SCK5, MUX_CONFIG_ALT1); + if (board_is_mx35(BOARD_REV_2)) + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 5, 1); + else + pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_2, 0, 1); +} + +EXPORT_SYMBOL(gpio_spdif_active); + +/*! + * Setup GPIO for spdif tx/rx to be inactive + */ +void gpio_spdif_inactive(void) +{ + /* SPDIF OUT */ + mxc_free_iomux(MX35_PIN_STXD5, MUX_CONFIG_ALT1); + /* SPDIF IN */ + mxc_free_iomux(MX35_PIN_SRXD5, MUX_CONFIG_ALT1); + /* SPDIF ext clock */ + mxc_free_iomux(MX35_PIN_SCK5, MUX_CONFIG_ALT1); +} + +EXPORT_SYMBOL(gpio_spdif_inactive); + +/*! + * This function activates DAM ports 3 to enable + * audio I/O. + */ +void gpio_activate_audio_ports(void) +{ + unsigned int pad_val; + + mxc_request_iomux(MX35_PIN_STXD4, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SRXD4, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SCK4, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_STXFS4, MUX_CONFIG_FUNC); + + pad_val = PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_PUE_PUD; + mxc_iomux_set_pad(MX35_PIN_STXD4, pad_val); + mxc_iomux_set_pad(MX35_PIN_SRXD4, pad_val); + mxc_iomux_set_pad(MX35_PIN_SCK4, pad_val); + mxc_iomux_set_pad(MX35_PIN_STXFS4, pad_val); +} + +EXPORT_SYMBOL(gpio_activate_audio_ports); + +/*! + * This function activates DAM ports 5 to enable + * audio I/O. + */ +void gpio_activate_bt_audio_port(void) +{ + unsigned int pad_val; + + mxc_request_iomux(MX35_PIN_STXD5, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SRXD5, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SCK5, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_STXFS5, MUX_CONFIG_FUNC); + + pad_val = PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_PUE_PUD; + mxc_iomux_set_pad(MX35_PIN_STXD5, pad_val); + mxc_iomux_set_pad(MX35_PIN_SRXD5, pad_val); + mxc_iomux_set_pad(MX35_PIN_SCK5, pad_val); + mxc_iomux_set_pad(MX35_PIN_STXFS5, pad_val); + if (board_is_mx35(BOARD_REV_2)) + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 5, 0); + else + pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_2, 0, 0); +} + +EXPORT_SYMBOL(gpio_activate_bt_audio_port); + +/*! + * Setup GPIO for bluetooth audio to be inactive + */ +void gpio_inactivate_bt_audio_port(void) +{ + mxc_free_iomux(MX35_PIN_STXD5, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_SRXD5, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_SCK5, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_STXFS5, MUX_CONFIG_FUNC); +} + +EXPORT_SYMBOL(gpio_inactivate_bt_audio_port); + +/*! + * Setup GPIO for ATA interface + * + */ +void gpio_ata_active(void) +{ + unsigned int ata_ctl_pad_cfg, ata_dat_pad_cfg; + + /* HDD_ENBALE */ + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 3, 0); + /* Power On the HDD */ + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 4, 1); + msleep(300); + + /*IOMUX Settings */ + /*PATA_DIOR */ + mxc_request_iomux(MX35_PIN_ATA_DIOR, MUX_CONFIG_FUNC); + /*PATA_DIOW */ + mxc_request_iomux(MX35_PIN_ATA_DIOW, MUX_CONFIG_FUNC); + /*PATA_DMARQ_B */ + mxc_request_iomux(MX35_PIN_ATA_DMARQ, MUX_CONFIG_FUNC); + /*PATA_DMACK */ + mxc_request_iomux(MX35_PIN_ATA_DMACK, MUX_CONFIG_FUNC); + /*PATA_RESET_B */ + mxc_request_iomux(MX35_PIN_ATA_RESET_B, MUX_CONFIG_FUNC); + /*PATA_IORDY */ + mxc_request_iomux(MX35_PIN_ATA_IORDY, MUX_CONFIG_FUNC); + /*PATA_INTRQ_B */ + mxc_request_iomux(MX35_PIN_ATA_INTRQ, MUX_CONFIG_FUNC); + /*PATA_CS_0 */ + mxc_request_iomux(MX35_PIN_ATA_CS0, MUX_CONFIG_FUNC); + /*PATA_CS_1 */ + mxc_request_iomux(MX35_PIN_ATA_CS1, MUX_CONFIG_FUNC); + /*PATA_DA0 */ + mxc_request_iomux(MX35_PIN_ATA_DA0, MUX_CONFIG_FUNC); + /*PATA_DA1 */ + mxc_request_iomux(MX35_PIN_ATA_DA1, MUX_CONFIG_FUNC); + /*PATA_DA2 */ + mxc_request_iomux(MX35_PIN_ATA_DA2, MUX_CONFIG_FUNC); + /* BUFFER_ENABLE - HDD_ENABLE_B */ + mxc_request_iomux(MX35_PIN_ATA_BUFF_EN, MUX_CONFIG_FUNC); + + /*PATA_D0 */ + mxc_request_iomux(MX35_PIN_ATA_DATA0, MUX_CONFIG_FUNC); + /*PATA_D1 */ + mxc_request_iomux(MX35_PIN_ATA_DATA1, MUX_CONFIG_FUNC); + /*PATA_D2 */ + mxc_request_iomux(MX35_PIN_ATA_DATA2, MUX_CONFIG_FUNC); + /*PATA_D3 */ + mxc_request_iomux(MX35_PIN_ATA_DATA3, MUX_CONFIG_FUNC); + /*PATA_D4 */ + mxc_request_iomux(MX35_PIN_ATA_DATA4, MUX_CONFIG_FUNC); + /*PATA_D5 */ + mxc_request_iomux(MX35_PIN_ATA_DATA5, MUX_CONFIG_FUNC); + /*PATA_D6 */ + mxc_request_iomux(MX35_PIN_ATA_DATA6, MUX_CONFIG_FUNC); + /*PATA_D7 */ + mxc_request_iomux(MX35_PIN_ATA_DATA7, MUX_CONFIG_FUNC); + /*PATA_D8 */ + mxc_request_iomux(MX35_PIN_ATA_DATA8, MUX_CONFIG_FUNC); + /*PATA_D9 */ + mxc_request_iomux(MX35_PIN_ATA_DATA9, MUX_CONFIG_FUNC); + /*PATA_D10 */ + mxc_request_iomux(MX35_PIN_ATA_DATA10, MUX_CONFIG_FUNC); + /*PATA_D11 */ + mxc_request_iomux(MX35_PIN_ATA_DATA11, MUX_CONFIG_FUNC); + /*PATA_D12 */ + mxc_request_iomux(MX35_PIN_ATA_DATA12, MUX_CONFIG_FUNC); + /*PATA_D13 */ + mxc_request_iomux(MX35_PIN_ATA_DATA13, MUX_CONFIG_FUNC); + /*PATA_D14 */ + mxc_request_iomux(MX35_PIN_ATA_DATA14, MUX_CONFIG_FUNC); + /*PATA_D15 */ + mxc_request_iomux(MX35_PIN_ATA_DATA15, MUX_CONFIG_FUNC); + + /* IOMUX Pad Settings */ + ata_ctl_pad_cfg = PAD_CTL_SRE_SLOW | PAD_CTL_DRV_NORMAL | + PAD_CTL_ODE_CMOS | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | + PAD_CTL_HYS_CMOS | PAD_CTL_DRV_3_3V; + ata_dat_pad_cfg = PAD_CTL_SRE_FAST | PAD_CTL_DRV_MAX | + PAD_CTL_ODE_CMOS | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_3_3V; + + mxc_iomux_set_pad(MX35_PIN_ATA_DMARQ, ata_dat_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DIOR, ata_ctl_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DIOW, ata_ctl_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DMACK, ata_ctl_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_RESET_B, PAD_CTL_SRE_SLOW | + PAD_CTL_DRV_NORMAL | PAD_CTL_ODE_CMOS | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | + PAD_CTL_100K_PU | PAD_CTL_HYS_CMOS | + PAD_CTL_DRV_3_3V); + mxc_iomux_set_pad(MX35_PIN_ATA_IORDY, ata_dat_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_INTRQ, ata_dat_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_CS0, ata_ctl_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_CS1, ata_ctl_pad_cfg); + + mxc_iomux_set_pad(MX35_PIN_ATA_DATA0, ata_dat_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DATA1, ata_dat_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DATA2, ata_dat_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DATA3, ata_dat_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DATA4, ata_dat_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DATA5, ata_dat_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DATA6, ata_dat_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DATA7, ata_dat_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DATA8, ata_dat_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DATA9, ata_dat_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DATA10, ata_dat_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DATA11, ata_dat_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DATA12, ata_dat_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DATA13, ata_dat_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DATA14, ata_dat_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DATA15, ata_dat_pad_cfg); + + mxc_iomux_set_pad(MX35_PIN_ATA_DA0, ata_ctl_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DA1, ata_ctl_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_DA2, ata_ctl_pad_cfg); + mxc_iomux_set_pad(MX35_PIN_ATA_BUFF_EN, ata_ctl_pad_cfg); +} + +EXPORT_SYMBOL(gpio_ata_active); + +/*! + * Restore ATA interface pins to reset values + * + */ +void gpio_ata_inactive(void) +{ + /*Turn off the IOMUX for ATA group B signals */ + mxc_free_iomux(MX35_PIN_ATA_DATA0, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DATA1, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DATA2, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DATA3, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DATA4, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DATA5, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DATA6, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DATA7, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DATA8, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DATA9, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DATA10, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DATA11, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DATA12, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DATA13, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DATA14, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DATA15, MUX_CONFIG_FUNC); + + /* Config the multiplex pin of ATA interface DIR, DA0-2, INTRQ, DMARQ */ + mxc_free_iomux(MX35_PIN_ATA_DMARQ, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DIOR, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DIOW, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DMACK, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_RESET_B, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_IORDY, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_INTRQ, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_CS0, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_CS1, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DA0, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DA1, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_DA2, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_ATA_BUFF_EN, MUX_CONFIG_FUNC); + + /* Power Off the HDD */ + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 4, 0); + /* HDD_ENBALE */ + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 3, 1); +} + +EXPORT_SYMBOL(gpio_ata_inactive); + +/*! + * This function activates ESAI ports to enable + * surround sound I/O + */ +void gpio_activate_esai_ports(void) +{ + unsigned int pad_val; + /* ESAI TX - WM8580 */ + mxc_request_iomux(MX35_PIN_HCKT, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SCKT, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FST, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_TX0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_TX1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_FUNC); + + /* ESAI RX - AK5702 */ + /*mxc_request_iomux(MX35_PIN_HCKR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SCKR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FSR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_TX4_RX1, MUX_CONFIG_FUNC);*/ + + pad_val = PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_PUE_PUD; + /* ESAI TX - WM8580 */ + mxc_iomux_set_pad(MX35_PIN_SCKT, pad_val); + mxc_iomux_set_pad(MX35_PIN_FST, pad_val); + mxc_iomux_set_pad(MX35_PIN_TX0, pad_val); + mxc_iomux_set_pad(MX35_PIN_TX1, pad_val); + mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad_val); + + /* ESAI RX - AK5702 */ + /*mxc_iomux_set_pad(MX35_PIN_SCKR, pad_val); + mxc_iomux_set_pad(MX35_PIN_FSR, pad_val); + mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad_val); + mxc_iomux_set_pad(MX35_PIN_TX4_RX1, pad_val);*/ + + pad_val = + PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_PUE_PUD; + + /* ESAI TX - WM8580 */ + mxc_iomux_set_pad(MX35_PIN_HCKT, pad_val); + /* ESAI RX - AK5702 */ + /*mxc_iomux_set_pad(MX35_PIN_HCKR, pad_val);*/ +} + +EXPORT_SYMBOL(gpio_activate_esai_ports); + +/*! + * This function deactivates ESAI ports to disable + * surround sound I/O + */ +void gpio_deactivate_esai_ports(void) +{ + + mxc_free_iomux(MX35_PIN_HCKT, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_SCKT, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FST, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_TX0, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_TX1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_GPIO); + /*mxc_free_iomux(MX35_PIN_HCKR, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_SCKR, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FSR, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_TX4_RX1, MUX_CONFIG_GPIO);*/ +} + +EXPORT_SYMBOL(gpio_deactivate_esai_ports); + +/*! + * This function enable and reset GPS GPIO + */ +void gpio_gps_active(void) +{ + /* Pull GPIO1_5 to be low for routing signal to UART3/GPS */ + if (board_is_mx35(BOARD_REV_2)) { + mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX35_PIN_COMPARE, PAD_CTL_DRV_NORMAL | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | + PAD_CTL_SRE_SLOW); + mxc_set_gpio_direction(MX35_PIN_COMPARE, 0); + mxc_set_gpio_dataout(MX35_PIN_COMPARE, 0); + } + + /* PWR_EN_GPS is set to be 0, will be toggled on in app by ioctl */ + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 0, 0); + + /* GPS 32KHz clock enbale */ + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 7, 1); + + /* GPS reset */ + pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 5, 0); + msleep(5); + pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 5, 1); + msleep(5); +} + +EXPORT_SYMBOL(gpio_gps_active); + +/*! + * This function get GPS GPIO status. + */ +int gpio_gps_access(int para) +{ + unsigned int gps_val; + + if (para & 0x4) { /* Read GPIO */ + if (para & 0x1) /* Read PWR_EN */ + pmic_gpio_get_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 0, + &gps_val); + else /* Read nReset */ + pmic_gpio_get_bit_val(MCU_GPIO_REG_RESET_1, 5, + &gps_val); + return gps_val; + } else { /* Write GPIO */ + gps_val = (para & 0x2) ? 1 : 0; + if (para & 0x1) + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 0, + gps_val); + else + pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 5, gps_val); + } + return 0; +} + +EXPORT_SYMBOL(gpio_gps_access); + +/*! + * This function disable GPS GPIO + */ +void gpio_gps_inactive(void) +{ + /* GPS disable */ + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 0, 0); + /* Free GPIO1_5 */ + if (board_is_mx35(BOARD_REV_2)) + mxc_free_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO); +} + +EXPORT_SYMBOL(gpio_gps_inactive); + +/*! + * The MLB gpio configuration routine + */ +void gpio_mlb_active(void) +{ + mxc_request_iomux(MX35_PIN_MLB_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_MLB_SIG, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_MLB_DAT, MUX_CONFIG_FUNC); +} + +EXPORT_SYMBOL(gpio_mlb_active); + +void gpio_mlb_inactive(void) +{ + mxc_free_iomux(MX35_PIN_MLB_CLK, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_MLB_SIG, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_MLB_DAT, MUX_CONFIG_FUNC); +} + +EXPORT_SYMBOL(gpio_mlb_inactive); + +void gpio_can_active(int id) +{ + int pad; + + switch (id) { + case 0: + pad = PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | \ + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH; + mxc_request_iomux(MX35_PIN_I2C2_CLK, MUX_CONFIG_ALT1); + mxc_request_iomux(MX35_PIN_I2C2_DAT, MUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX35_PIN_I2C2_CLK, pad); + mxc_iomux_set_pad(MX35_PIN_I2C2_DAT, pad); + mxc_iomux_set_input(MUX_IN_CAN1_CANRX, INPUT_CTL_PATH0); + break; + case 1: + pad = PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU; + mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_ALT1); + mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad); + mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad); + mxc_iomux_set_input(MUX_IN_CAN2_CANRX, INPUT_CTL_PATH2); + break; + default: + printk(KERN_ERR "NO such device\n"); + } +} + +void gpio_can_inactive(int id) +{ + switch (id) { + case 0: + mxc_free_iomux(MX35_PIN_I2C2_CLK, MUX_CONFIG_ALT1); + mxc_free_iomux(MX35_PIN_I2C2_DAT, MUX_CONFIG_ALT1); + mxc_iomux_set_input(MUX_IN_CAN1_CANRX, INPUT_CTL_PATH0); + break; + case 1: + mxc_free_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_ALT1); + mxc_free_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_ALT1); + mxc_iomux_set_input(MUX_IN_CAN2_CANRX, INPUT_CTL_PATH0); + break; + default: + printk(KERN_ERR "NO such device\n"); + } +} + +void gpio_pmic_active(void) +{ + unsigned int pad_val = PAD_CTL_SRE_SLOW | PAD_CTL_DRV_NORMAL + | PAD_CTL_HYS_CMOS | PAD_CTL_100K_PU | PAD_CTL_DRV_3_3V; + mxc_request_iomux(MX35_PIN_GPIO2_0, MUX_CONFIG_FUNC); + mxc_iomux_set_pad(MX35_PIN_GPIO2_0, pad_val); + mxc_set_gpio_direction(MX35_PIN_GPIO2_0, 1); +} + +EXPORT_SYMBOL(gpio_pmic_active); + + diff -urN linux-2.6.26/arch/arm/mach-mx35/mx35_3stack_irq.c linux-2.6.26-lab126/arch/arm/mach-mx35/mx35_3stack_irq.c --- linux-2.6.26/arch/arm/mach-mx35/mx35_3stack_irq.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/mx35_3stack_irq.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,371 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "board-mx35_3stack.h" +#include "iomux.h" + +/*! + * @file mach-mx35/mx35_3stack_irq.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX35 + */ +#ifdef CONFIG_MXC_PSEUDO_IRQS + +/* + * The interrupt status and mask variables. + */ +static unsigned long pseudo_irq_pending; +static unsigned long pseudo_irq_enable; +static unsigned long pseudo_irq_wakeup; +static unsigned long pseudo_suspend; +static atomic_t pseudo_irq_state = ATOMIC_INIT(0); + +/* + * The declaration of handler of two work queue. + * The one is the work queue to indentify the events from MCU. + * The another is the work queue to change the events mask. + */ +static void mcu_event_handler(struct work_struct *work); +static void mcu_state_handler(struct work_struct *work); +static void mcu_event_delay(unsigned long data); + +/*! + * The work structure for mcu events. + */ +static DECLARE_WORK(mcu_event_ws, mcu_event_handler); +static DECLARE_WORK(mcu_state_ws, mcu_state_handler); +static DEFINE_TIMER(mcu_delay_timer, mcu_event_delay, HZ, 0); + +static inline void mxc_pseudo_irq_ack(void) +{ + disable_irq(MXC_PSEUDO_PARENT); + atomic_set(&pseudo_irq_state, 0); +} + +static inline void mxc_pseudo_irq_trigger(void) +{ + if (!atomic_xchg(&pseudo_irq_state, 1)) + enable_irq(MXC_PSEUDO_PARENT); +} + +/* + * mask a pseudo interrupt by setting the bit in the mask variable. + * @param irq a pseudo virtual irq number + */ +static void pseudo_mask_irq(u32 irq) +{ + int index = irq - MXC_PSEUDO_IO_BASE; + clear_bit(index, &pseudo_irq_enable); +} + +/* + * disable a pseudo interrupt by triggerring a work queue + * @param irq a pseudo virtual irq number + */ +static void pseudo_disable_irq(u32 irq) +{ + struct irq_desc *desc = irq_desc + irq; + desc->chip->mask(irq); + desc->status |= IRQ_MASKED; + schedule_work(&mcu_state_ws); +} + +/* + * Acknowledge a pseudo interrupt by clearing the bit in the isr variable. + * @param irq a pseudo virtual irq number + */ +static void pseudo_ack_irq(u32 irq) +{ + int index = irq - MXC_PSEUDO_IO_BASE; + /* clear the interrupt status */ + clear_bit(index, &pseudo_irq_pending); +} + +/* + * unmask a pseudo interrupt by clearing the bit in the imr. + * @param irq a pseudo virtual irq number + */ +static void pseudo_unmask_irq(u32 irq) +{ + int index = irq - MXC_PSEUDO_IO_BASE; + + set_bit(index, &pseudo_irq_enable); + + if (test_bit(index, &pseudo_irq_pending)) + mxc_pseudo_irq_trigger(); +} + +/* + * Enable a pseudo interrupt by triggerring a work queue + * @param irq a pseudo virtual irq number + */ +static void pseudo_enable_irq(u32 irq) +{ + struct irq_desc *desc = irq_desc + irq; + desc->chip->unmask(irq); + desc->status &= ~IRQ_MASKED; + schedule_work(&mcu_state_ws); +} + +/* + * set pseudo irq as a wake-up source. + * @param irq a pseudo virtual irq number + * @param enable enable as wake-up if equal to non-ero + * @return This function return 0 on success + */ +static int pseudo_set_wake_irq(u32 irq, u32 enable) +{ + int index = irq - MXC_PSEUDO_IO_BASE; + + if (index >= MXC_MAX_PSEUDO_IO_LINES) + return -ENODEV; + + if (enable) { + if (!pseudo_irq_wakeup) + enable_irq_wake(IOMUX_TO_IRQ(MX35_PIN_GPIO1_0)); + pseudo_irq_wakeup |= (1 << index); + } else { + pseudo_irq_wakeup &= ~(1 << index); + if (!pseudo_irq_wakeup) + disable_irq_wake(IOMUX_TO_IRQ(MX35_PIN_GPIO1_0)); + } + return 0; +} + +static struct irq_chip pseudo_irq_chip = { + .ack = pseudo_ack_irq, + .mask = pseudo_mask_irq, + .disable = pseudo_disable_irq, + .unmask = pseudo_unmask_irq, + .enable = pseudo_enable_irq, + .set_wake = pseudo_set_wake_irq, +}; + +static void mxc_pseudo_irq_handler(u32 irq, struct irq_desc *desc) +{ + u32 pseudo_irq; + u32 index, mask; + + desc->chip->mask(irq); + mxc_pseudo_irq_ack(); + + mask = pseudo_irq_enable; + index = pseudo_irq_pending; + + if (unlikely(!(index & mask))) { + printk(KERN_ERR "\nPseudo IRQ: Spurious interrupt:0x%0x\n\n", + index); + pr_info("IEN=0x%x, PENDING=0x%x\n", mask, index); + return; + } + + index = index & mask; + pseudo_irq = MXC_PSEUDO_IO_BASE; + for (; index != 0; index >>= 1, pseudo_irq++) { + struct irq_desc *d; + if ((index & 1) == 0) + continue; + d = irq_desc + pseudo_irq; + if (unlikely(!(d->handle_irq))) { + printk(KERN_ERR "\nPseudo irq: %d unhandeled\n", + pseudo_irq); + BUG(); /* oops */ + } + d->handle_irq(pseudo_irq, d); + d->chip->ack(pseudo_irq); + } +} + +static void mcu_event_delay(unsigned long data) +{ + schedule_work(&mcu_event_ws); +} + +/*! + * This function is called when mcu interrupt occurs on the processor. + * It is the interrupt handler for the mcu. + * + * @param irq the irq number + * @param dev_id the pointer on the device + * + * @return The function returns IRQ_HANDLED when handled. + */ +static irqreturn_t mcu_irq_handler(int irq, void *dev_id) +{ + disable_irq(IOMUX_TO_IRQ(MX35_PIN_GPIO1_0)); + if (pseudo_suspend) + mod_timer(&mcu_delay_timer, jiffies + HZ); + else + schedule_work(&mcu_event_ws); + + return IRQ_HANDLED; +} + +/*! + * This function is the work handler of mcu interrupt. + * It reads the events status and trigger the pseudo irq. + */ +static void mcu_event_handler(struct work_struct *work) +{ + int i, err; + unsigned int flag1, flag2; + + /* read int flags and ack int */ + for (i = 0; i < 3; i++) { + err = mcu_pmic_read_reg(REG_MCU_INT_FLAG_1, &flag1, 0xFFFFFFFF); + err |= mcu_pmic_read_reg(REG_MCU_INT_FLAG_2, + &flag2, 0xFFFFFFFF); + err |= mcu_pmic_write_reg(REG_MCU_INT_FLAG_1, 0, 0xFFFFFFFF); + err |= mcu_pmic_write_reg(REG_MCU_INT_FLAG_2, 0, 0xFFFFFFFF); + if (err == 0) + break; + } + + if (i >= 3) { + printk(KERN_ERR "Reads MCU event fail\n"); + goto no_new_events; + } + + for (i = 0; flag1 && (i < MCU_INT_RTC); i++, flag1 >>= 1) + if (flag1 & 1) + set_bit(i, &pseudo_irq_pending); + + for (i = MCU_INT_RTC; flag2 && (i <= MCU_INT_KEYPAD); i++, flag2 >>= 1) + if (flag2 & 1) + set_bit(i, &pseudo_irq_pending); + no_new_events: + if (pseudo_irq_pending & pseudo_irq_enable) + mxc_pseudo_irq_trigger(); + enable_irq(IOMUX_TO_IRQ(MX35_PIN_GPIO1_0)); +} + +static void mcu_state_handler(struct work_struct *work) +{ + int err, i; + unsigned int event1, event2; + event1 = pseudo_irq_enable & ((1 << MCU_INT_RTC) - 1); + event2 = pseudo_irq_enable >> MCU_INT_RTC; + + for (i = 0; i < 3; i++) { + err = mcu_pmic_write_reg(REG_MCU_INT_ENABLE_1, event1, 0xFF); + err |= mcu_pmic_write_reg(REG_MCU_INT_ENABLE_2, event2, 0xFF); + if (err == 0) + break; + } + if (i >= 3) + printk(KERN_ERR "Change MCU event mask fail\n"); +} + +static int __init mxc_pseudo_init(void) +{ + int i; + + /* disable the interrupt and clear the status */ + pseudo_irq_pending = 0; + pseudo_irq_enable = 0; + + pr_info("3-Stack Pseudo interrupt rev=0.1v\n"); + + for (i = MXC_PSEUDO_IO_BASE; + i < (MXC_PSEUDO_IO_BASE + MXC_MAX_PSEUDO_IO_LINES); i++) { + set_irq_chip(i, &pseudo_irq_chip); + set_irq_handler(i, handle_simple_irq); + set_irq_flags(i, IRQF_VALID); + } + + set_irq_flags(MXC_PSEUDO_PARENT, IRQF_NOAUTOEN); + set_irq_handler(MXC_PSEUDO_PARENT, mxc_pseudo_irq_handler); + + /* Set and install PMIC IRQ handler */ + mxc_request_iomux(MX35_PIN_GPIO1_0, MUX_CONFIG_FUNC); + mxc_iomux_set_pad(MX35_PIN_GPIO1_0, PAD_CTL_PKE_NONE); + mxc_set_gpio_direction(MX35_PIN_GPIO1_0, 1); + + set_irq_type(IOMUX_TO_IRQ(MX35_PIN_GPIO1_0), IRQT_RISING); + if (request_irq(IOMUX_TO_IRQ(MX35_PIN_GPIO1_0), mcu_irq_handler, + 0, "MCU_IRQ", 0)) { + printk(KERN_ERR "mcu request irq failed\n"); + return -1; + } + return 0; +} + +fs_initcall_sync(mxc_pseudo_init); + +static int mxc_pseudo_irq_suspend(struct platform_device *dev, + pm_message_t mesg) +{ + int err, i; + unsigned int event1, event2; + + if (!pseudo_irq_wakeup) + return 0; + + event1 = pseudo_irq_wakeup & ((1 << MCU_INT_RTC) - 1); + event2 = pseudo_irq_wakeup >> MCU_INT_RTC; + + for (i = 0; i < 3; i++) { + err = mcu_pmic_write_reg(REG_MCU_INT_ENABLE_1, event1, 0xFF); + err |= mcu_pmic_write_reg(REG_MCU_INT_ENABLE_2, event2, 0xFF); + if (err == 0) + break; + } + pseudo_suspend = 1; + return err; +} + +static int mxc_pseudo_irq_resume(struct platform_device *dev) +{ + if (!pseudo_irq_wakeup) + return 0; + + schedule_work(&mcu_state_ws); + pseudo_suspend = 0; + return 0; +} + +static struct platform_driver mxc_pseudo_irq_driver = { + .driver = { + .name = "mxc_pseudo_irq", + }, + .suspend = mxc_pseudo_irq_suspend, + .resume = mxc_pseudo_irq_resume, +}; + +static int __init mxc_pseudo_sysinit(void) +{ + return platform_driver_register(&mxc_pseudo_irq_driver); +} + +late_initcall(mxc_pseudo_sysinit); +#endif /* CONFIG_MXC_PSEUDO_IRQS */ diff -urN linux-2.6.26/arch/arm/mach-mx35/mx35_accessory.c linux-2.6.26-lab126/arch/arm/mach-mx35/mx35_accessory.c --- linux-2.6.26/arch/arm/mach-mx35/mx35_accessory.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/mx35_accessory.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,458 @@ +/* + * mx35_accessory -- MX35 Accessory Port + * + * Copyright 2009-2010 Amazon Technologies Inc., All rights reserved + * Manish Lachwani (lachwani@lab126.com) + * + * Support for the MX35 Accessory Port + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +extern void gpio_acc_active(void); +extern int gpio_acc_get_irq(void); +extern void gpio_acc_inactive(void); +extern int gpio_acc_detected(void); +extern int gpio_acc_power_irq(void); + +/* Define accessory as a misc device */ +#define ACCESSORY_PORT_MINOR 159 /* /dev/accessoryport */ + +#define CHGDETS 0x40 /* Charger detect bit */ + +static struct miscdevice accessory_misc_device = { + ACCESSORY_PORT_MINOR, + "accessoryport", + NULL, +}; + +#define MX35_ACCESSORY_VOLTAGE 3150000 /* 3.15V */ +#define MX35_ACCESSORY_MIN_VOLTAGE 1200000 /* 1.2V */ +#define ACC_THRESHOLD 1000 /* 1 second */ + +#define VGEN1_ENABLE 1 +#define VGEN1_DISABLE 0 +#define VGEN1_LSH 0 +#define VGEN1_MASK 1 + +#define GPO2_ENABLE 1 +#define GPO2_DISABLE 0 +#define GPO2_LSH 8 +#define GPO2_MASK 1 + +#define GPO4_ENABLE 1 +#define GPO4_DISABLE 0 +#define GPO4_LSH 12 +#define GPO4_MASK 1 + +#define GPO4ADIN_DIS 0 +#define GPO4ADIN_MASK 1 +#define GPO4ADIN_LSH 21 + +#define VGEN1_NEEDED() (IS_SHASTA() && IS_EVT() && (GET_BOARD_HW_VERSION() == 1)) +#define GPO4_NEEDED() (IS_SHASTA() && (IS_DVT() || IS_PVT())) + +char *vgen1_reg_id = "VGEN1"; +static struct regulator *vgen1_regulator; + +char *gpo2_reg_id = "GPO2"; +static struct regulator *gpo2_regulator; + +extern void gpio_acc_charger_enable(int); +extern int gpio_acc_power_ok(void); + +static int accessory_irq_state = 0; /* Disabled by default */ + +static int mx35_accessory_reboot(struct notifier_block *self, unsigned long action, void *cpu); + +static struct notifier_block mx35_accessory_reboot_nb = +{ + .notifier_call = mx35_accessory_reboot, +}; + +/*! + * This function sets the accessory voltage + * on VGEN1 + */ +static void accessory_regulator_vgen1_voltage(int enable) +{ + int err = 0; + + if (enable) { + pmic_write_reg(REG_MODE_0, (VGEN1_ENABLE << VGEN1_LSH), + (VGEN1_MASK << VGEN1_LSH)); + err = regulator_set_voltage(vgen1_regulator, MX35_ACCESSORY_VOLTAGE); + if (err < 0) + printk(KERN_ERR "do_accessory_work: Could not set VGEN1 voltage\n"); + } + else { + err = regulator_set_voltage(vgen1_regulator, MX35_ACCESSORY_MIN_VOLTAGE); + if (err < 0) + printk(KERN_ERR "do_accessory_work: Could not set VGEN1 voltage\n"); + + pmic_write_reg(REG_MODE_0, (VGEN1_DISABLE << VGEN1_LSH), + (VGEN1_MASK << VGEN1_LSH)); + } +} + +/*! + * Check if charger connected + */ +static int pmic_connected_charger(void) +{ + int sense_0 = 0; + int ret = 0; /* Default: no host */ + + pmic_read_reg(REG_INT_SENSE0, &sense_0, 0xffffff); + + if (sense_0 & CHGDETS) + ret = 1; + + return ret; +} + +/*! + * This function sets the accessory voltage + * on GPO2 + */ +static void accessory_regulator_gpo2_voltage(int enable) +{ + if (enable) { + pmic_write_reg(REG_POWER_MISC, (GPO2_ENABLE << GPO2_LSH), + (GPO2_MASK << GPO2_LSH)); + + if (GPO4_NEEDED()) { + if (pmic_connected_charger()) { + pmic_write_reg(REG_POWER_MISC, (GPO4_ENABLE << GPO4_LSH), + (GPO4_MASK << GPO4_LSH)); + } + else { + pmic_write_reg(REG_POWER_MISC, (GPO4_DISABLE << GPO4_LSH), + (GPO4_MASK << GPO4_LSH)); + } + } + } + else { + pmic_write_reg(REG_POWER_MISC, (GPO2_DISABLE << GPO2_LSH), + (GPO2_MASK << GPO2_LSH)); + } +} + +/*! + * Enable GPO4 to start accessory charging + */ +void enable_accessory_gpo4(void) +{ + if (GPO4_NEEDED() && !gpio_acc_detected()) { + pmic_write_reg(REG_POWER_MISC, (GPO4_DISABLE << GPO4_LSH), + (GPO4_MASK << GPO4_LSH)); + } +} + +EXPORT_SYMBOL(enable_accessory_gpo4); + +/*! + * Disable GPO4 to stop accessory charging + */ +void disable_accessory_gpo4(void) +{ + if (GPO4_NEEDED()) { + pmic_write_reg(REG_POWER_MISC, (GPO4_ENABLE << GPO4_LSH), + (GPO4_MASK << GPO4_LSH)); + } +} +EXPORT_SYMBOL(disable_accessory_gpo4); + +static void enable_accessory_pmic(void) +{ + if (!gpio_acc_detected()) { + printk(KERN_INFO "Accessory detected!\n"); + + if (VGEN1_NEEDED()) + accessory_regulator_vgen1_voltage(1); + else + accessory_regulator_gpo2_voltage(1); + + set_irq_type(gpio_acc_get_irq(), IRQF_TRIGGER_HIGH); + + if (!gpio_acc_power_ok()) { + kobject_uevent_atomic(&accessory_misc_device.this_device->kobj, KOBJ_ONLINE); + gpio_acc_charger_enable(0); + } + else + kobject_uevent_atomic(&accessory_misc_device.this_device->kobj, KOBJ_OFFLINE); + + } + else { + printk(KERN_INFO "No Accessory Found\n"); + + if (VGEN1_NEEDED()) + accessory_regulator_vgen1_voltage(0); + else + accessory_regulator_gpo2_voltage(0); + + set_irq_type(gpio_acc_get_irq(), IRQF_TRIGGER_LOW); + gpio_acc_charger_enable(1); + kobject_uevent_atomic(&accessory_misc_device.this_device->kobj, KOBJ_OFFLINE); + } +} + +static void do_accessory_work(struct work_struct *dummy) +{ + enable_accessory_pmic(); + + if (!accessory_irq_state) { + enable_irq(gpio_acc_get_irq()); + accessory_irq_state = 1; + } +} +static DECLARE_DELAYED_WORK(accessory_work, do_accessory_work); + +static void do_power_ok_work(struct work_struct *dummy) +{ + int power_ok = gpio_acc_power_irq(); + + if (!gpio_acc_power_ok()) { + set_irq_type(power_ok, IRQF_TRIGGER_HIGH); + gpio_acc_charger_enable(0); + kobject_uevent_atomic(&accessory_misc_device.this_device->kobj, KOBJ_ONLINE); + } + else { + set_irq_type(power_ok, IRQF_TRIGGER_LOW); + gpio_acc_charger_enable(1); + kobject_uevent_atomic(&accessory_misc_device.this_device->kobj, KOBJ_OFFLINE); + } + + enable_irq(power_ok); +} +static DECLARE_DELAYED_WORK(power_ok_work, do_power_ok_work); + +static irqreturn_t accessory_port_irq(int irq, void *devid) +{ + if (accessory_irq_state) { + disable_irq(irq); + accessory_irq_state = 0; + } + + /* Debounce for 1 second */ + schedule_delayed_work(&accessory_work, msecs_to_jiffies(ACC_THRESHOLD)); + + return IRQ_HANDLED; +} + +static irqreturn_t accessory_power_ok_irq(int irq, void *devid) +{ + disable_irq(irq); + + /* Debounce for 1 second */ + schedule_delayed_work(&power_ok_work, msecs_to_jiffies(ACC_THRESHOLD)); + + return IRQ_HANDLED; +} + +/*! + * sysfs + */ +void mx35_accessory_enable(int enable) +{ + if (!enable) { + printk(KERN_INFO "Accessory port disabled!\n"); + + if (VGEN1_NEEDED()) + accessory_regulator_vgen1_voltage(0); + else + accessory_regulator_gpo2_voltage(0); + + if (accessory_irq_state) { + disable_irq(gpio_acc_get_irq()); + accessory_irq_state = 0; + } + } + else { + printk(KERN_INFO "Accessory port enable\n"); + /* Schedule a 1 second workqueue */ + schedule_delayed_work(&accessory_work, msecs_to_jiffies(ACC_THRESHOLD)); + } +} +EXPORT_SYMBOL(mx35_accessory_enable); + +static ssize_t +mx35_show_accessory_charging(struct sys_device *dev, char *buf) +{ + return sprintf(buf, "%d\n", !gpio_acc_power_ok()); +} +static SYSDEV_ATTR(mx35_accessory_charging, 0644, mx35_show_accessory_charging, NULL); + +static ssize_t +mx35_store_accessory_state(struct sys_device *dev, const char *buf, size_t size) +{ + int value; + + if ((sscanf(buf, "%d", &value) > 0) && + ((value == 0) || (value == 1))) { + mx35_accessory_enable(value); + return strlen(buf); + } + + return -EINVAL; +} +static SYSDEV_ATTR(mx35_accessory_state, 0644, NULL, mx35_store_accessory_state); + +static struct sysdev_class mx35_accessory_sysclass = { + .name = "mx35_accessory", +}; + +static struct sys_device mx35_accessory_device = { + .id = 0, + .cls = &mx35_accessory_sysclass, +}; + +static int mx35_accessory_sysdev_ctrl_init(void) +{ + int err = 0; + + err = sysdev_class_register(&mx35_accessory_sysclass); + if (!err) + err = sysdev_register(&mx35_accessory_device); + if (!err) { + sysdev_create_file(&mx35_accessory_device, &attr_mx35_accessory_state); + sysdev_create_file(&mx35_accessory_device, &attr_mx35_accessory_charging); + } + + return err; +} + +static void mx35_accessory_sysdev_ctrl_exit(void) +{ + sysdev_remove_file(&mx35_accessory_device, &attr_mx35_accessory_charging); + sysdev_remove_file(&mx35_accessory_device, &attr_mx35_accessory_state); + sysdev_unregister(&mx35_accessory_device); + sysdev_class_unregister(&mx35_accessory_sysclass); +} + +static int __init accessory_port_init(void) +{ + int err = 0, irq = gpio_acc_get_irq(); + int power_ok = gpio_acc_power_irq(); + + printk(KERN_INFO "Initializing MX35 Luigi/Shasta Accessory Port\n"); + + gpio_acc_active(); + + if (!gpio_acc_detected()) + set_irq_type(irq, IRQF_TRIGGER_HIGH); + else + set_irq_type(irq, IRQF_TRIGGER_LOW); + + err = request_irq(irq, accessory_port_irq, 0, "MX35_Accessory", NULL); + + if (err != 0) { + printk(KERN_ERR "IRQF_DISABLED: Could not get IRQ %d\n", irq); + return err; + } + + accessory_irq_state = 1; + + if (!gpio_acc_power_ok()) + set_irq_type(power_ok, IRQF_TRIGGER_HIGH); + else + set_irq_type(power_ok, IRQF_TRIGGER_LOW); + + err = request_irq(power_ok, accessory_power_ok_irq, 0, "Accessory_Charger", NULL); + if (err != 0) { + printk(KERN_ERR "IRQF_DISABLED: Could not get IRQ %d\n", power_ok); + return err; + } + + if (VGEN1_NEEDED()) { + vgen1_regulator = regulator_get(NULL, vgen1_reg_id); + if (IS_ERR(vgen1_regulator)) { + printk(KERN_ERR "%s: failed to get vgen1 regulator\n", __func__); + return PTR_ERR(vgen1_regulator); + } + } + else { + gpo2_regulator = regulator_get(NULL, gpo2_reg_id); + if (IS_ERR(gpo2_regulator)) { + printk(KERN_ERR "%s: failed to get gpo2 regulator\n", __func__); + return PTR_ERR(gpo2_regulator); + } + } + + if (misc_register (&accessory_misc_device)) { + printk (KERN_WARNING "accessoryport: Couldn't register device 10, " + "%d.\n", ACCESSORY_PORT_MINOR); + return -EBUSY; + } + + enable_accessory_pmic(); + if (mx35_accessory_sysdev_ctrl_init() < 0) + printk(KERN_ERR "mx35_accessory: Could not create sysfs interface\n"); + + /* Disable GPO4ADIN */ + pmic_write_reg(REG_POWER_MISC, (GPO4ADIN_DIS << GPO4ADIN_LSH), + (GPO4ADIN_MASK << GPO4ADIN_LSH)); + + register_reboot_notifier(&mx35_accessory_reboot_nb); + + return err; +} + +static void accessory_port_cleanup(void) +{ + mx35_accessory_enable(0); + + accessory_irq_state = 0; + misc_deregister(&accessory_misc_device); + gpio_acc_inactive(); + if (VGEN1_NEEDED()) + regulator_put(vgen1_regulator, NULL); + else + regulator_put(gpo2_regulator, NULL); + free_irq(gpio_acc_get_irq(), NULL); + mx35_accessory_sysdev_ctrl_exit(); +} + +static int mx35_accessory_reboot(struct notifier_block *self, unsigned long action, void *cpu) +{ + printk(KERN_INFO "MX35 Accessory shutdown\n"); + accessory_port_cleanup(); + return 0; +} + +static void __exit accessory_port_remove(void) +{ + accessory_port_cleanup(); + unregister_reboot_notifier(&mx35_accessory_reboot_nb); +} + +module_init(accessory_port_init); +module_exit(accessory_port_remove); + +MODULE_AUTHOR("Manish Lachwani"); +MODULE_DESCRIPTION("MX35 Accessory Port"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/mach-mx35/mx35_luigi.c linux-2.6.26-lab126/arch/arm/mach-mx35/mx35_luigi.c --- linux-2.6.26/arch/arm/mach-mx35/mx35_luigi.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/mx35_luigi.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,1004 @@ +/* + * Copyright 2008-2009 Amazon.com All Rights Reserved. + * Manish Lachwani (lachwani@lab126.com) + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "board-mx35_3stack.h" +#include "crm_regs.h" +#include "iomux.h" + +#if defined(CONFIG_PROC_BOARDID) +#include "boardid.h" +#endif + +/*! + * @file mach-mx35/mx35_luigi.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX35 + */ + +#define VSD_LSH 18 +#define SW4_HALT_MHMODE_LSH 12 +#define SW4_HALT_MHMODE_VALUE 0 +#define SW4_HALT_MHMODE_MASK 1 +#define VUSB_LSH 0 /* VUSBIN in Register #50 */ +#define VUSBEN_LSH 3 /* VUSBEN in Register #50 */ +#define WDIRESET 12 /* Bit 12 in register 15 */ + +extern int mxc_init_devices(void); +extern void arch_reset(char); + +unsigned int mx35_3stack_board_io; + +/* Define a miscdevice for sending uevent for fat fs */ +#define FATFS_MISCDEV_PORT_MINOR 160 /* /dev/fatfsdev */ + +static struct miscdevice fatfsdev_misc_device = { + FATFS_MISCDEV_PORT_MINOR, + "fatfsdev", + NULL, +}; + +static int __init mxc_fatfsdev_init(void) +{ + if (misc_register (&fatfsdev_misc_device)) { + printk (KERN_WARNING "fatfsdev: Couldn't register device\n"); + return -EBUSY; + } + + return 0; +} +module_init(mxc_fatfsdev_init); + +static void __exit mxc_fatfsdev_remove(void) +{ + misc_deregister(&fatfsdev_misc_device); +} +module_exit(mxc_fatfsdev_remove); + +void mxc_send_fatfs_event(void) +{ + kobject_uevent_atomic(&fatfsdev_misc_device.this_device->kobj, KOBJ_ONLINE); +} +EXPORT_SYMBOL(mxc_send_fatfs_event); + +static void mxc_nop_release(struct device *dev) +{ + /* Nothing */ +} + +static struct mxc_lcd_platform_data lcd_data = { + .io_reg = "LCD" +}; + +static struct platform_device lcd_dev = { + .name = "lcd_claa", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = (void *)&lcd_data, + }, +}; + +static void mxc_init_lcd(void) +{ + platform_device_register(&lcd_dev); +} + +#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) +/* mxc lcd driver */ +static struct platform_device mxc_fb_device = { + .name = "mxc_sdc_fb", + .id = 0, + .dev = { + .release = mxc_nop_release, + .coherent_dma_mask = 0xFFFFFFFF, + }, +}; + +static void mxc_init_fb(void) +{ + (void)platform_device_register(&mxc_fb_device); +} +#else +static inline void mxc_init_fb(void) +{ +} +#endif + +#if defined(CONFIG_BACKLIGHT_MXC) +static struct platform_device mxcbl_devices[] = { +#if defined(CONFIG_BACKLIGHT_MXC_IPU) || defined(CONFIG_BACKLIGHT_MXC_IPU_MODULE) + { + .name = "mxc_ipu_bl", + .id = 0, + .dev = { + .platform_data = (void *)3, /* DISP # for this backlight */ + }, + } +#endif +}; + +static inline void mxc_init_bl(void) +{ + int i; + for (i = 0; i < ARRAY_SIZE(mxcbl_devices); i++) { + platform_device_register(&mxcbl_devices[i]); + } +} +#else +static inline void mxc_init_bl(void) +{ +} +#endif + +#if defined(CONFIG_SDIO_UNIFI_FS) || defined(CONFIG_SDIO_UNIFI_FS_MODULE) +static void mxc_unifi_hardreset(void) +{ + pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 1, 0); + msleep(100); + pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 1, 1); +} + +static void mxc_unifi_enable(int en) +{ + if (en) { + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 5, 1); + msleep(10); + } else + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 5, 0); +} + +static struct mxc_unifi_platform_data unifi_data = { + .hardreset = mxc_unifi_hardreset, + .enable = mxc_unifi_enable, + .reg_gpo1 = "GPO2", + .reg_gpo2 = "GPO3", + .reg_1v5_ana_bb = "PWGT1", + .reg_vdd_vpa = "VAUDIO", + .reg_1v5_dd = "SW1", + .host_id = 1, +}; + +struct mxc_unifi_platform_data *get_unifi_plat_data(void) +{ + return &unifi_data; +} +#else +struct mxc_unifi_platform_data *get_unifi_plat_data(void) +{ + return NULL; +} +#endif + +EXPORT_SYMBOL(get_unifi_plat_data); + +static struct i2c_board_info mxc_i2c_board_info[] __initdata = { + { + .type = "mc9sdz60", + .addr = 0x69, + }, + { + .type = "max8660", + .addr = 0x34, + }, +}; + +static struct spi_board_info mxc_spi_board_info[] __initdata = { + { + .modalias = "pmic_spi", + .irq = IOMUX_TO_IRQ(MX35_PIN_ATA_IORDY), + .max_speed_hz = 4000000, /* max spi SCK clock speed in HZ */ + .bus_num = 1, + .chip_select = 0, + }, +}; + +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) +unsigned int expio_intr_fec; + +EXPORT_SYMBOL(expio_intr_fec); +#endif + +static struct mxc_mmc_platform_data mmc_data = { + .ocr_mask = MMC_VDD_31_32 | MMC_VDD_32_33, + .min_clk = 150000, + .max_clk = 52000000, + .card_inserted_state = 1, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "sdhc_clk", + .power_mmc = "VGEN2", +}; + +/* + * SD Slot - MMC #3 + */ +static struct mxc_mmc_platform_data mmc_data_3 = { + .ocr_mask = MMC_VDD_31_32 | MMC_VDD_32_33, + .min_clk = 400000, + .max_clk = 52000000, + .card_inserted_state = 1, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "sdhc_clk", +}; + +/* + * WiFi + */ +static struct mxc_mmc_platform_data mmc_data_2 = { + .ocr_mask = MMC_VDD_31_32 | MMC_VDD_32_33, + .min_clk = 400000, + .max_clk = 25000000, + .card_inserted_state = 1, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "sdhc_clk", + .power_mmc = "SW1", +}; + +#define MMC_SDHC1_DETECT_IRQ 65 /* Fake Value */ +#define MMC_SDHC2_DETECT_IRQ 66 /* Fake value */ + +#ifndef CONFIG_FEC +#define MMC_SDHC3_DETECT_IRQ IOMUX_TO_IRQ(MX35_PIN_FEC_TX_EN) +#else +#define MMC_SDHC3_DETECT_IRQ -1 /* Some random number now that FEC is in use */ +#endif + +/*! + * Resource definition for the SDHC1 + */ +static struct resource mxcsdhc1_resources[] = { + [0] = { + .start = MMC_SDHC1_BASE_ADDR, + .end = MMC_SDHC1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_MMC_SDHC1, + .end = MXC_INT_MMC_SDHC1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = MMC_SDHC1_DETECT_IRQ, + .end = MMC_SDHC1_DETECT_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Device Definition for MXC SDHC1 */ +static struct platform_device mxcsdhc1_device = { + .name = "mxsdhci", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc_data, + }, + .num_resources = ARRAY_SIZE(mxcsdhc1_resources), + .resource = mxcsdhc1_resources, +}; + +static struct resource mxcsdhc3_resources[] = { + [0] = { + .start = MMC_SDHC3_BASE_ADDR, + .end = MMC_SDHC3_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_MMC_SDHC3, + .end = MXC_INT_MMC_SDHC3, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = MMC_SDHC3_DETECT_IRQ, + .end = MMC_SDHC3_DETECT_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Device Definition for MXC SDHC3 */ +static struct platform_device mxcsdhc3_device = { + .name = "mxsdhci", + .id = 2, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc_data_3, + }, + .num_resources = ARRAY_SIZE(mxcsdhc3_resources), + .resource = mxcsdhc3_resources, +}; + +static struct resource mxcsdhc2_resources[] = { + [0] = { + .start = MMC_SDHC2_BASE_ADDR, + .end = MMC_SDHC2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_MMC_SDHC2, + .end = MXC_INT_MMC_SDHC2, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = MMC_SDHC2_DETECT_IRQ, + .end = MMC_SDHC2_DETECT_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxcsdhc4_device = { + .name = "mxsdhci", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc_data_2, + }, + .num_resources = ARRAY_SIZE(mxcsdhc2_resources), + .resource = mxcsdhc2_resources, +}; + +static inline void mxc_init_mmc(void) +{ + (void)platform_device_register(&mxcsdhc1_device); + (void)platform_device_register(&mxcsdhc4_device); + (void)platform_device_register(&mxcsdhc3_device); +} + +/* + * In case of a battery drain down, this saves the last good time. + */ +u32 saved_last_seconds = 0; +EXPORT_SYMBOL(saved_last_seconds); + +/*! + * pmic board initialization code + */ +static int __init mxc_init_pmic(void) +{ + unsigned int regA = 0, regB = 0; + /* + * Charger settings + * + * Set PLIM to 800mW and set PLIMDIS to 0 + */ + /* PLIM: bits 15 and 16 */ + CHECK_ERROR(pmic_write_reg(REG_CHARGE, (0x1 << 15), (0x3 << 15))); + + /* PLIMDIS: bit 17 */ + CHECK_ERROR(pmic_write_reg(REG_CHARGE, (0 << 17), (1 << 17))); + + /* Get the last good saved seconds */ + pmic_read_reg(REG_MEM_A, ®A, (0xff << 16)); + pmic_read_reg(REG_MEM_B, ®B, 0x00ffffff); + saved_last_seconds = (regA << 8)| regB; + + printk(KERN_INFO "Last saved time: 0x%x\n", saved_last_seconds); + + /* Turn off the VUSBIN that is responsible for leakage */ + CHECK_ERROR(pmic_write_reg(REG_USB1, (0 << VUSB_LSH), (1 << VUSB_LSH))); + + /* Turn off VUSBEN */ + CHECK_ERROR(pmic_write_reg(REG_USB1, (0 << VUSBEN_LSH), (1 << VUSBEN_LSH))); + + return 0; +} + +late_initcall(mxc_init_pmic); + +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mxc_cpu_init(); + +#ifdef CONFIG_DISCONTIGMEM + do { + int nid; + mi->nr_banks = MXC_NUMNODES; + for (nid = 0; nid < mi->nr_banks; nid++) + SET_NODE(mi, nid); + } while (0); +#endif + mi->bank[0].start = PLFRM_MEM_BASE; + mi->bank[0].size = PLFRM_MEM_SIZE; + mi->nr_banks = 1; +} + +#if defined(CONFIG_KEYBOARD_MXC) || defined(CONFIG_KEYBOARD_MXC_MODULE) + +/* + * Keypad keycodes for the keypads. + * NOTE: for each keypad supported, add the same number of keys (64); + * otherwise the mapping will NOT work! + */ +/* + * IMPORTANT! Change the following parameter when adding a new KB map + * to the array below. + */ + +#define NUMBER_OF_KB_MAPPINGS 2 + +static u16 keymapping[NUMBER_OF_KB_MAPPINGS][64] = { + +/* + * keymapping[0] = key mapping for Luigi3 boards + * NOTE: 64 keys; even those unused + * NOTE: The number keys are combined with the first + * row of letters (Q/1, W/2, etc). We still need to define + * the number key codes in the matrix so that they are enabled + * for the input event driver. Since we cannot define two key codes + * in one row/col entry, these 10 keycodes are defined in unused + * row/col entries. + */ + { + /* Row 0 */ + KEY_HOME, KEY_1, KEY_R, KEY_S, KEY_RESERVED, KEY_RESERVED, + KEY_BACKSPACE, KEY_DOT, /* "123" Key */ + /* Row 1 */ + KEY_MENU, KEY_2, KEY_T, KEY_D, KEY_RESERVED, KEY_RESERVED, + KEY_Z, KEY_RESERVED, + /* Row 2 */ + KEY_BACK, KEY_3, KEY_Y, KEY_F, KEY_RESERVED, KEY_RESERVED, + KEY_X, KEY_ENTER, + /* Row 3 */ + KEY_PAGEUP /* Next-page left button */, KEY_4, KEY_U, KEY_G, + KEY_5, KEY_RESERVED, KEY_C, KEY_LEFTSHIFT, + /* Row 4 */ + KEY_F21 /* Next-page right button */, KEY_6, KEY_I, KEY_H, + KEY_7, KEY_RESERVED, KEY_V, KEY_LEFTALT, + /* Row 5 */ + KEY_F23 /* Prev-page left button */, KEY_Q, KEY_O, KEY_J, + KEY_RESERVED, KEY_8, KEY_B, KEY_SPACE, + /* Row 6 */ + KEY_PAGEDOWN /* Prev-page right button */, KEY_W, KEY_P, KEY_K, + KEY_RESERVED, KEY_9, KEY_N, KEY_F20 /* Font Size */, + /* Row 7 */ + KEY_0, KEY_E, KEY_A, KEY_L, KEY_RESERVED, KEY_RESERVED, + KEY_M, KEY_RIGHTMETA /* SYM */, + }, + +/* + * keymapping[1] = key mapping for Shasta boards + * + */ + { + /* Row 0 */ + KEY_MENU, KEY_1, KEY_R, KEY_S, KEY_RESERVED, KEY_RESERVED, + KEY_BACKSPACE, KEY_DOT, + /* Row 1 */ + KEY_HOME, KEY_2, KEY_T, KEY_D, KEY_RESERVED, KEY_RESERVED, + KEY_Z, KEY_RESERVED, + /* Row 2 */ + KEY_BACK, KEY_3, KEY_Y, KEY_F, KEY_RESERVED, KEY_RESERVED, + KEY_X, KEY_ENTER, + /* Row 3 */ + KEY_F21 /* Next-page right button */, KEY_4, KEY_U, KEY_G, + KEY_5, KEY_RESERVED, KEY_C, KEY_LEFTSHIFT, + /* Row 4 */ + KEY_PAGEUP /* Next-page left button */, KEY_6, KEY_I, KEY_H, + KEY_7, KEY_RESERVED, KEY_V, KEY_LEFTALT, + /* Row 5 */ + KEY_PAGEDOWN /* Prev-page right button */, KEY_Q, KEY_O, KEY_J, + KEY_RESERVED, KEY_8, KEY_B, KEY_SPACE, + /* Row 6 */ + KEY_F23 /* Prev-page left button */, KEY_W, KEY_P, KEY_K, + KEY_RESERVED, KEY_9, KEY_N, KEY_F20 /* Font Size */, + /* Row 7 */ + KEY_0, KEY_E, KEY_A, KEY_L, KEY_RESERVED, KEY_RESERVED, + KEY_M, KEY_RIGHTMETA /* SYM */, + }, + +/* + * NOTE: If you add more keypad mappings, remember to increment + * NUMBER_OF_KB_MAPPINGS above + */ +}; + +static struct resource mxc_kpp_resources[] = { + [0] = { + .start = MXC_INT_KPP, + .end = MXC_INT_KPP, + .flags = IORESOURCE_IRQ, + } +}; + +static struct keypad_data evb_8_by_8_keypad = { + .rowmax = 8, + .colmax = 8, + .irq = MXC_INT_KPP, + .learning = 0, + .delay = 2, + .matrix = (u16 *)keymapping, +}; + +/* mxc keypad driver */ +static struct platform_device mxc_keypad_device = { + .name = "mxc_keypad", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_kpp_resources), + .resource = mxc_kpp_resources, + .dev = { + .release = mxc_nop_release, + .platform_data = &evb_8_by_8_keypad, + }, +}; + +static void mxc_init_keypad(void) +{ + (void)platform_device_register(&mxc_keypad_device); +} +#else +static inline void mxc_init_keypad(void) +{ + +} +#endif + +static void __init luigi_mxc_init_irq(void) +{ + reserve_bootmem(BOOT_GLOBALS_BASE, BOOT_GLOBALS_SIZE, BOOTMEM_DEFAULT); + reserve_bootmem(OOPS_SAVE_BASE, OOPS_SAVE_SIZE, BOOTMEM_DEFAULT); + + mxc_init_irq(); +} + +extern void gpio_papyrus_reset(void); +extern void gpio_i2c_active(int i2c_num); +extern void gpio_chrgled_iomux(void); +extern void gpio_chrgled_active(int enable); +extern void wan_sysdev_ctrl_init(void); +extern void gpio_test_pm(void); + +static int __init mx35_luigi_sysfs_init(void) +{ + int err = 0; + + wan_sysdev_ctrl_init(); + + return err; +} +late_initcall(mx35_luigi_sysfs_init); + +static void mx35_pmic_power_off(void); +static void mx35_configure_rtc(int atlas_3_1); +static void mx35_rtc_pmic_off(void); + +/* + * Power off for the MX35 + */ +void mx35_power_off(void) +{ + unsigned int reg = 0; + + pmic_read_reg(REG_IDENTIFICATION, ®, 0xffffffff); + + /* Check if Atlas Rev 3.1 */ + if (reg & 0x1) + mx35_configure_rtc(1); + else + mx35_configure_rtc(0); + + mx35_pmic_power_off(); +} +EXPORT_SYMBOL(mx35_power_off); + +extern void watchdog_pin_gpio(void); + +static void mx35_configure_rtc(int atlas_3_1) +{ + struct timeval pmic_time; + + pmic_write_reg(REG_INT_STATUS1, 0, 0x2); + pmic_write_reg(REG_INT_MASK1, 0, 0x2); + pmic_rtc_get_time(&pmic_time); + if (atlas_3_1) + pmic_time.tv_sec += 2; + else + pmic_time.tv_sec += 10; + + pmic_rtc_set_time_alarm(&pmic_time); +} + +#define PMIC_BUTTON_DEBOUNCE_VALUE 0x2 +#define PMIC_BUTTON_DEBOUNCE_MASK 0x3 + +static void mxc_configure_pb_debounce(void) +{ + /* Configure debounce time for power button 1 */ + pmic_write_reg(REG_POWER_CTL2, (PMIC_BUTTON_DEBOUNCE_VALUE << 4), (PMIC_BUTTON_DEBOUNCE_MASK << 4)); + + /* Configure debounce time for power button 2 */ + pmic_write_reg(REG_POWER_CTL2, (PMIC_BUTTON_DEBOUNCE_VALUE << 6), (PMIC_BUTTON_DEBOUNCE_MASK << 6)); + + /* Configure debounce time for power button 3 */ + pmic_write_reg(REG_POWER_CTL2, (PMIC_BUTTON_DEBOUNCE_VALUE << 8), (PMIC_BUTTON_DEBOUNCE_MASK << 8)); +} + +/*! + * The power off is different for the Atlas Rev 3.1 + */ +static void mx35_pmic_power_off(void) +{ + unsigned int reg = 0; + + mxc_configure_pb_debounce(); + + pmic_read_reg(REG_IDENTIFICATION, ®, 0xffffffff); + + /* Check if Atlas Rev 3.1 */ + if (reg & 0x1) { + /* Set VUSBIN */ + pmic_write_reg(REG_USB1, (0 << VUSB_LSH), (1 << VUSB_LSH)); + + /* Clear WDIRESET */ + pmic_write_reg(REG_POWER_CTL2, (0 << WDIRESET), (1 << WDIRESET)); + + /* Configure WATCHDOG PIN as GPIO and pull it low */ + watchdog_pin_gpio(); + } + else { + /* Turn off VSD */ + pmic_write_reg(REG_MODE_1, (0 << VSD_LSH), (1 << VSD_LSH)); + + /* Turn off SW4 in halt/poweroff */ + pmic_write_reg(REG_SW_5, (SW4_HALT_MHMODE_VALUE << SW4_HALT_MHMODE_LSH), + (SW4_HALT_MHMODE_MASK << SW4_HALT_MHMODE_LSH)); + + /* Clear out bit #2 in MEMA */ + pmic_write_reg(REG_MEM_A, (0 << 2), (1 << 2)); + + /* Turn on bit #2 */ + pmic_write_reg(REG_MEM_A, (1 << 2), (1 << 2)); + + /* + * This puts Atlas in USEROFF power cut mode + */ + pmic_power_off(); + } +} + +void mxc_kernel_uptime(void) +{ + struct timespec uptime; + + /* Record the kernel boot time, now that this is the last thing */ + do_posix_clock_monotonic_gettime(&uptime); + monotonic_to_bootbased(&uptime); + + printk("%lu.%02lu seconds:\n", (unsigned long) uptime.tv_sec, + (uptime.tv_nsec / (NSEC_PER_SEC / 100))); +} +EXPORT_SYMBOL(mxc_kernel_uptime); + +/*! + * Check if the reset was due to a watchdog timeout. If yes, + * then do a clean restart + */ +static void mx35_check_wdog_rst(void) +{ + unsigned int reg_memory_a; + + pmic_read_reg(REG_MEM_A, ®_memory_a, (0x1f << 0)); + + if (reg_memory_a & 0x2) { + /* Clear out bit #1 in MEMA */ + pmic_write_reg(REG_MEM_A, (0 << 1), (1 << 1)); + printk(KERN_ERR "boot: I def:rbt:Device Reboot Encountered:\n"); + goto out; + } + + if (reg_memory_a & 0x4) { + /* Clear out bit #2 in MEMA */ + pmic_write_reg(REG_MEM_A, (0 << 2), (1 << 2)); + printk(KERN_ERR "boot: I def:hlt:Device Halt Encountered:\n"); + goto out; + } + + /* Check if this is a button reset or a watchdog reset */ + if (reg_memory_a & 0x8) { + printk(KERN_ERR "boot: I def:rst:Hard reset or Watchdog Reset Encountered:\n"); + goto out; + } + + /* If nothing matches above, then it is a battery cut */ + printk(KERN_ERR "boot: I def:bcut:15 second battery cut Encountered:\n"); +out: + /* Check if we booted out of critical battery */ + if (reg_memory_a & 0x10) { + /* Clear out bit #4 */ + pmic_write_reg(REG_MEM_A, (0 << 4), (1 << 4)); + printk(KERN_ERR "boot: I def:crit:Booting out of critical battery:\n"); + } + + /* Clear out the Atlas flags bits 0-2 */ + pmic_write_reg(REG_MEM_A, (0 << 0), (7 << 0)); + + /* + * This is a place holder to track resets and reboots. This Atlas bit can + * be cleared if there is a battery cut, reboot, halt. Reboots and halt are + * tracked as above. this wont be cleared by button reset or watchdog reset. + */ + pmic_write_reg(REG_MEM_A, (1 << 3), (1 << 3)); + + printk(KERN_INFO "kernel: I perf:kernel:kernel_loaded="); + mxc_kernel_uptime(); + + return; +} + +/*! + * Check for the OOPS on bootup + */ +void *oops_start; +static int __init mxc_check_oops(void) +{ + char oops_buffer[OOPS_SAVE_SIZE]; + oops_start = __arm_ioremap(OOPS_SAVE_BASE, OOPS_SAVE_SIZE, 0); + + memcpy((void *)oops_buffer, oops_start, OOPS_SAVE_SIZE); + + if ( (oops_buffer[0] == 'O') && (oops_buffer[1] == 'O') && + (oops_buffer[2] == 'P') && (oops_buffer[3] == 'S') ) { + printk("Kernel Crash Start\n"); + printk("%s", oops_buffer); + printk("\nKernel Crash End\n"); + } + else { + mx35_check_wdog_rst(); + } + + memset(oops_start, 0, OOPS_SAVE_SIZE); + return 0; +} +late_initcall(mxc_check_oops); + +extern void watchdog_reset_config(void); + +/*! + * This function clears out the RTC specific registers and masks out the + * RTC alarm interrupt. When a device is halted, it is not expected to + * wake on an RTC expiry. Hence, these interrupt sources have been cleared. + * Also, the RTC alarm time and day registers are also cleared. + */ +static void mx35_rtc_pmic_off(void) +{ + /* Clear out the RTC time interrupt */ + pmic_write_reg(REG_INT_STATUS1, 0, 0x2); + + /* Mask the RTC alarm interrupt */ + pmic_write_reg(REG_INT_MASK1, 0x3, 0x3); + + /* Zero out the RTC alarm day */ + pmic_write_reg(REG_RTC_ALARM, 0x0, 0xffffffff); + + /* Zero out the RTC alarm time */ + pmic_write_reg(REG_RTC_DAY_ALARM, 0x0, 0xffffffff); + + /* Now invoke power_off */ + mx35_pmic_power_off(); +} + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + pm_power_off = mx35_rtc_pmic_off; + + mxc_cpu_common_init(); +#if defined(CONFIG_PROC_BOARDID) + mx35_init_boardid(); +#endif + mxc_clocks_init(); + early_console_setup(saved_command_line); + mxc_gpio_init(); + mxc_init_devices(); + mx35_luigi_gpio_init(); + mxc_init_keypad(); + mxc_init_lcd(); + + watchdog_reset_config(); + + i2c_register_board_info(0, mxc_i2c_board_info, + ARRAY_SIZE(mxc_i2c_board_info)); + + spi_register_board_info(mxc_spi_board_info, + ARRAY_SIZE(mxc_spi_board_info)); + mxc_init_mmc(); + gpio_i2c_active(0); + gpio_i2c_active(1); + + /* Turn on support for the GPIO that controls the charger led */ + gpio_chrgled_iomux(); + gpio_chrgled_active(1); + + /* Reset papyrus */ + gpio_papyrus_reset(); + + /* Initialize the PM test point */ + gpio_test_pm(); +} + +#define PLL_PCTL_REG(brmo, pd, mfd, mfi, mfn) \ + (((brmo) << 31) + (((pd) - 1) << 26) + (((mfd) - 1) << 16) + \ + ((mfi) << 10) + mfn) + +/* For 24MHz input clock */ +#define PLL_665MHZ PLL_PCTL_REG(1, 1, 48, 13, 41) +#define PLL_532MHZ PLL_PCTL_REG(0, 0, 2, 2, 10) +#define PLL_399MHZ PLL_PCTL_REG(0, 1, 16, 8, 5) + +/* working point(wp): 0,1 - 133MHz; 2,3 - 266MHz; 4,5 - 399MHz;*/ +/* auto input clock table */ +static struct cpu_wp cpu_wp_auto[] = { + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 133000000, + .pdr0_reg = (0x2 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 133000000, + .pdr0_reg = (0x6 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 266000000, + .pdr0_reg = (0x1 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 266000000, + .pdr0_reg = (0x5 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 399000000, + .pdr0_reg = (0x0 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 399000000, + .pdr0_reg = (0x6 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),}, +}; + +/* consumer input clock table */ +static struct cpu_wp cpu_wp_con[] = { + { + .pll_reg = PLL_532MHZ, + .pll_rate = 512000000, + .cpu_rate = 128000000, + .pdr0_reg = (0x6 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 512000000, + .cpu_rate = 128000000, + .pdr0_reg = (0xE << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 512000000, + .cpu_rate = 256000000, + .pdr0_reg = (0x2 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 512000000, + .cpu_rate = 256000000, + .pdr0_reg = (0xA << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 399000000, + .pdr0_reg = (0x1 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 399000000, + .pdr0_reg = (0x9 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 512000000, + .cpu_rate = 512000000, + .pdr0_reg = (0x0 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 512000000, + .cpu_rate = 512000000, + .pdr0_reg = (0x8 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_665MHZ, + .pll_rate = 665000000, + .cpu_rate = 665000000, + .pdr0_reg = (0x7 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, +}; + +struct cpu_wp *get_cpu_wp(int *wp) +{ + if (cpu_is_mx35_rev(CHIP_REV_2_0) >= 1) { + *wp = 9; + return cpu_wp_con; + } else { + if (__raw_readl(MXC_CCM_PDR0) & MXC_CCM_PDR0_AUTO_CON) { + *wp = 9; + return cpu_wp_con; + } else { + *wp = 6; + return cpu_wp_auto; + } + } +} + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX35_LUIGI data structure. + */ +/* *INDENT-OFF* */ +MACHINE_START(MX35_LUIGI, "Amazon MX35 Luigi Board") + /* Maintainer: Manish Lachwani (lachwani@lab126.com) */ + .phys_io = AIPS1_BASE_ADDR, + .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .fixup = fixup_mxc_board, + .map_io = mxc_map_io, + .init_irq = luigi_mxc_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff -urN linux-2.6.26/arch/arm/mach-mx35/mx35_luigi_gpio.c linux-2.6.26-lab126/arch/arm/mach-mx35/mx35_luigi_gpio.c --- linux-2.6.26/arch/arm/mach-mx35/mx35_luigi_gpio.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/mx35_luigi_gpio.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,2180 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2009-2010 Amazon.com + * Manish Lachwani (lachwani@lab126.com) + * Marcos Frid (mfrid@lab126.com) + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * MX35 Luigi GPIO definitions + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board-mx35_3stack.h" +#include "iomux.h" + +/*! + * @file mach-mx35/mx35_3stack_gpio.c + * + * @brief This file contains all the GPIO setup functions for the board. + * + * @ingroup GPIO_MX35 + */ + +/*! + * This system-wise GPIO function initializes the pins during system startup. + * All the statically linked device drivers should put the proper GPIO + * initialization code inside this function. It is called by \b fixup_mx31ads() + * during system startup. This function is board specific. + */ +void mx35_luigi_gpio_init(void) +{ + /* config CS1 */ + mxc_request_iomux(MX35_PIN_CS1, MUX_CONFIG_FUNC); + +} + +void mx35_luigi_pullup_enable(iomux_pin_name_t pin) +{ + mxc_iomux_set_pad(pin, (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD)); +} + +EXPORT_SYMBOL(mx35_luigi_pullup_enable); + +void mx35_luigi_pullup_disable(iomux_pin_name_t pin) +{ + mxc_iomux_set_pad(pin, PAD_CTL_PKE_ENABLE); +} + +EXPORT_SYMBOL(mx35_luigi_pullup_disable); + +/* + * Accessory port settings + */ + +#define ACC_CHARGER_OK MX35_PIN_MLB_SIG +#define ACC_DET_B MX35_PIN_ATA_CS0 +#define ACC_EN MX35_PIN_GPIO1_0 + +void gpio_acc_active(void) +{ + unsigned int pad_val; + + mxc_request_iomux(ACC_CHARGER_OK, MUX_CONFIG_ALT5); + mxc_request_iomux(ACC_DET_B, MUX_CONFIG_ALT5); + mxc_request_iomux(ACC_EN, MUX_CONFIG_FUNC); + + pad_val = PAD_CTL_DRV_NORMAL | PAD_CTL_100K_PU | + PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | + PAD_CTL_SRE_SLOW | PAD_CTL_DRV_1_8V; + + mxc_iomux_set_pad(ACC_CHARGER_OK, pad_val); + + pad_val = PAD_CTL_DRV_NORMAL | PAD_CTL_100K_PU | + PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | + PAD_CTL_SRE_SLOW | PAD_CTL_DRV_1_8V; + + mxc_iomux_set_pad(ACC_DET_B, pad_val); + mxc_iomux_set_pad(ACC_EN, pad_val); + + mxc_set_gpio_direction(ACC_CHARGER_OK, 1); + mxc_set_gpio_direction(ACC_DET_B, 1); + mxc_iomux_set_input(MUX_IN_GPIO2_IN_6, INPUT_CTL_PATH1); + mxc_set_gpio_direction(ACC_EN, 0); + mxc_iomux_set_input(MUX_IN_GPIO3_IN_5, INPUT_CTL_PATH1); +} +EXPORT_SYMBOL(gpio_acc_active); + +int gpio_acc_get_irq(void) +{ + return IOMUX_TO_IRQ(ACC_DET_B); +} +EXPORT_SYMBOL(gpio_acc_get_irq); + +int gpio_acc_detected(void) +{ + return mxc_get_gpio_datain(ACC_DET_B); +} +EXPORT_SYMBOL(gpio_acc_detected); + +int gpio_acc_power_ok(void) +{ + return mxc_get_gpio_datain(ACC_CHARGER_OK); +} +EXPORT_SYMBOL(gpio_acc_power_ok); + +int gpio_acc_power_irq(void) +{ + return IOMUX_TO_IRQ(ACC_CHARGER_OK); +} +EXPORT_SYMBOL(gpio_acc_power_irq); + +void gpio_acc_charger_enable(int enable) +{ + mxc_set_gpio_dataout(ACC_EN, enable); +} +EXPORT_SYMBOL(gpio_acc_charger_enable); + +void gpio_acc_inactive(void) +{ + mxc_free_iomux(ACC_CHARGER_OK, MUX_CONFIG_ALT5); + mxc_free_iomux(ACC_DET_B, MUX_CONFIG_ALT5); + mxc_free_iomux(ACC_EN, MUX_CONFIG_ALT5); +} +EXPORT_SYMBOL(gpio_acc_inactive); + +void watchdog_reset_config(void) +{ + mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_FUNC); +} +EXPORT_SYMBOL(watchdog_reset_config); + +void watchdog_pin_gpio(void) +{ + int pad_val = PAD_CTL_DRV_NORMAL | PAD_CTL_100K_PU | + PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_SRE_SLOW | PAD_CTL_DRV_1_8V | + PAD_CTL_HYS_SCHMITZ; + + mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_ALT5); + mxc_iomux_set_pad(MX35_PIN_WATCHDOG_RST, pad_val); + mxc_set_gpio_direction(MX35_PIN_WATCHDOG_RST, 0); + mxc_set_gpio_dataout(MX35_PIN_WATCHDOG_RST, 0); +} +EXPORT_SYMBOL(watchdog_pin_gpio); + +void gpio_usbotg_oc_disable(int enable) +{ + if (!enable) { + mxc_free_iomux(MX35_PIN_USBOTG_OC, MUX_CONFIG_FUNC); + } + else { + mxc_request_iomux(MX35_PIN_USBOTG_OC, MUX_CONFIG_FUNC); + mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, PAD_CTL_100K_PD); + } +} +EXPORT_SYMBOL(gpio_usbotg_oc_disable); + +/*! + * Configure the papyrus IRQ line + */ +void gpio_papyrus_irq_configure(int enable) +{ + int pad_val = PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | + PAD_CTL_SRE_SLOW | PAD_CTL_DRV_1_8V | PAD_CTL_HYS_CMOS | + PAD_CTL_PKE_NONE | PAD_CTL_100K_PU; + +#ifdef CONFIG_FEC + return; +#endif + + if (enable) { + mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_ALT5); + mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad_val); + mxc_set_gpio_direction(MX35_PIN_FEC_MDC, 1); + mxc_iomux_set_input(MUX_IN_GPIO3_IN_13, INPUT_CTL_PATH1); + } + else { + mxc_set_gpio_direction(MX35_PIN_FEC_MDC, 0); + mxc_free_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_ALT5); + } +} +EXPORT_SYMBOL(gpio_papyrus_irq_configure); + +int gpio_papyrus_get_irq(void) +{ +#ifdef CONFIG_FEC + return -1; +#else + return IOMUX_TO_IRQ(MX35_PIN_FEC_MDC); +#endif +} +EXPORT_SYMBOL(gpio_papyrus_get_irq); + +/*! + * Configure the papyrus power good line + */ +void gpio_papyrus_pg_configure(int enable) +{ + int pad_val = PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | + PAD_CTL_SRE_SLOW | PAD_CTL_DRV_1_8V | PAD_CTL_HYS_CMOS | + PAD_CTL_PKE_NONE | PAD_CTL_100K_PU; + + if (enable) { + mxc_request_iomux(MX35_PIN_STXFS5, MUX_CONFIG_ALT5); + mxc_iomux_set_pad(MX35_PIN_STXFS5, pad_val); + mxc_set_gpio_direction(MX35_PIN_STXFS5, 1); + mxc_iomux_set_input(MUX_IN_GPIO1_IN_3, INPUT_CTL_PATH0); + } + else { + mxc_set_gpio_direction(MX35_PIN_STXFS5, 0); + mxc_free_iomux(MX35_PIN_STXFS5, MUX_CONFIG_GPIO); + } +} +EXPORT_SYMBOL(gpio_papyrus_pg_configure); + +int gpio_papyrus_get_pg(void) +{ + return IOMUX_TO_IRQ(MX35_PIN_STXFS5); +} +EXPORT_SYMBOL(gpio_papyrus_get_pg); + +/*! + * Configure papyrus power state + */ +static int papyrus_enable_state = 0; + +static int gpio_papryus_needs_legacy_polarity(void) +{ + return ( (IS_SHASTA() && IS_EVT() && (1 == GET_BOARD_HW_VERSION())) || + (IS_LUIGI() && (3 == GET_BOARD_HW_VERSION())) ); +} + +void gpio_papyrus_configure(int enable) +{ +#ifdef CONFIG_FEC + return; +#endif + + if (papyrus_enable_state != enable) { + int pad_val; + + if (enable) { + pad_val = PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | + PAD_CTL_SRE_SLOW | PAD_CTL_DRV_1_8V | PAD_CTL_HYS_CMOS | + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD; + + mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_ALT5); + mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad_val); + mxc_set_gpio_direction(MX35_PIN_FEC_MDIO, 0); + mxc_iomux_set_input(MUX_IN_GPIO3_IN_14, INPUT_CTL_PATH1); + + if (gpio_papryus_needs_legacy_polarity()) + mxc_set_gpio_dataout(MX35_PIN_FEC_MDIO, 0); + else + mxc_set_gpio_dataout(MX35_PIN_FEC_MDIO, 1); + } + else { + pad_val = PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW | PAD_CTL_100K_PU; + + if (gpio_papryus_needs_legacy_polarity()) + mxc_set_gpio_dataout(MX35_PIN_FEC_MDIO, 1); + else + mxc_set_gpio_dataout(MX35_PIN_FEC_MDIO, 0); + + mxc_set_gpio_direction(MX35_PIN_FEC_MDIO, 1); + mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad_val); + mxc_free_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_ALT5); + } + + papyrus_enable_state = enable; + } +} +EXPORT_SYMBOL(gpio_papyrus_configure); + +void gpio_papyrus_reset(void) +{ + gpio_papyrus_configure(1); + mdelay(20); + gpio_papyrus_configure(0); + mdelay(20); + gpio_papyrus_configure(1); +} +EXPORT_SYMBOL(gpio_papyrus_reset); + +static int charger_led_state = 0; + +/* + * Shasta boards have a GPIO to control the charger led + */ +void gpio_chrgled_iomux(void) +{ + mxc_request_iomux(MX35_PIN_CSI_D12, MUX_CONFIG_ALT5); +} +EXPORT_SYMBOL(gpio_chrgled_iomux); + +static int gpio_chrgled_needs_legacy_polarity(void) +{ + return ( (IS_SHASTA() && IS_EVT() && (1 == GET_BOARD_HW_VERSION())) || + (IS_LUIGI() && (3 == GET_BOARD_HW_VERSION())) ); +} + +void gpio_chrgled_active(int enable) +{ + int pad_val = PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW | PAD_CTL_DRV_1_8V | + PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE | PAD_CTL_100K_PU; + + if (charger_led_state != enable) { + mxc_set_gpio_direction(MX35_PIN_CSI_D12, 0); + if (gpio_chrgled_needs_legacy_polarity()) + mxc_set_gpio_dataout(MX35_PIN_CSI_D12, enable); + else + mxc_set_gpio_dataout(MX35_PIN_CSI_D12, !enable); + mxc_iomux_set_pad(MX35_PIN_CSI_D12, pad_val); + charger_led_state = enable; + } +} +EXPORT_SYMBOL(gpio_chrgled_active); + +void gpio_chrgled_inactive(void) +{ + mxc_set_gpio_dataout(MX35_PIN_CSI_D12, 0); +} +EXPORT_SYMBOL(gpio_chrgled_inactive); + +void gpio_fec_active(void) +{ + mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC); + +#define FEC_PAD_CTL_COMMON (PAD_CTL_PUE_PUD| \ + PAD_CTL_ODE_CMOS|PAD_CTL_DRV_NORMAL|PAD_CTL_SRE_SLOW | PAD_CTL_DRV_1_8V) + mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, FEC_PAD_CTL_COMMON | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_COL, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS | + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS | + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_MDC, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS | + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU); + mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS | + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_CRS, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS | + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS | + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, + FEC_PAD_CTL_COMMON | PAD_CTL_HYS_CMOS | + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); +#undef FEC_PAD_CTL_COMMON +} +EXPORT_SYMBOL(gpio_fec_active); + +/*! + * Setup GPIO for a UART port to be active + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_active(int port, int no_irda) +{ + /* + * Configure the IOMUX control registers for the UART signals + */ + switch (port) { + /* UART 1 IOMUX Configs */ + case 0: + mxc_request_iomux(MX35_PIN_RXD1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_TXD1, MUX_CONFIG_FUNC); + break; + /* UART 2 IOMUX Configs */ + case 1: + mxc_request_iomux(MX35_PIN_TXD2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_RXD2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_RTS2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CTS2, MUX_CONFIG_FUNC); + mxc_iomux_set_pad(MX35_PIN_RXD2, + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX35_PIN_TXD2, + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_RTS2, + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX35_PIN_CTS2, + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); + break; + /* UART 3 IOMUX Configs */ + case 2: +#ifdef CONFIG_FEC + return; +#endif + + mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_ALT2); + mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_ALT2); + mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_ALT2); + mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_ALT2); + + mxc_iomux_set_input(MUX_IN_UART3_UART_RTS_B, INPUT_CTL_PATH2); + mxc_iomux_set_input(MUX_IN_UART3_UART_RXD_MUX, INPUT_CTL_PATH3); + break; + default: + break; + } + +} + +EXPORT_SYMBOL(gpio_uart_active); + +/*! + * Setup GPIO for a UART port to be inactive + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_inactive(int port, int no_irda) +{ + switch (port) { + case 0: + break; + case 1: + mxc_free_iomux(MX35_PIN_RXD2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_TXD2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_RTS2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_CTS2, MUX_CONFIG_GPIO); + break; + case 2: + mxc_request_gpio(MX35_PIN_FEC_TX_CLK); + mxc_request_gpio(MX35_PIN_FEC_RX_CLK); + mxc_request_gpio(MX35_PIN_FEC_COL); + mxc_request_gpio(MX35_PIN_FEC_RX_DV); + + mxc_free_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_GPIO); + + mxc_iomux_set_input(MUX_IN_UART3_UART_RTS_B, INPUT_CTL_PATH0); + mxc_iomux_set_input(MUX_IN_UART3_UART_RXD_MUX, INPUT_CTL_PATH0); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_uart_inactive); + +/*! + * Add a test point to track down suspend/resume issues + */ +void gpio_test_pm(void) +{ + mxc_request_iomux(MX35_PIN_CSI_VSYNC, MUX_CONFIG_ALT5); + + /* Configure as an output */ + mxc_set_gpio_direction(MX35_PIN_CSI_VSYNC, 0); + + /* Default value is 0 */ + mxc_set_gpio_dataout(MX35_PIN_CSI_VSYNC, 0); +} +EXPORT_SYMBOL(gpio_test_pm); + +void gpio_pm_set_value(int val) +{ + mxc_set_gpio_direction(MX35_PIN_CSI_VSYNC, 0); + mxc_set_gpio_dataout(MX35_PIN_CSI_VSYNC, val); +} +EXPORT_SYMBOL(gpio_pm_set_value); + +/*! + * Configure the IOMUX GPR register to receive shared SDMA UART events + * + * @param port a UART port + */ +void config_uartdma_event(int port) +{ +} + +EXPORT_SYMBOL(config_uartdma_event); + +/*! + * Setup GPIO for an I2C device to be active + * + * @param i2c_num an I2C device + */ +void gpio_i2c_active(int i2c_num) +{ + unsigned int pad_val = PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain; + + switch (i2c_num) { + case 0: + mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION); + + mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad_val); + mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad_val); + break; + case 1: + mxc_request_iomux(MX35_PIN_I2C2_CLK, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_I2C2_DAT, MUX_CONFIG_SION); + + mxc_iomux_set_pad(MX35_PIN_I2C2_CLK, pad_val); + mxc_iomux_set_pad(MX35_PIN_I2C2_DAT, pad_val); + + break; + case 2: + mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1); + mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad_val); + mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad_val); + break; + default: + break; + } + +#undef PAD_CONFIG + +} + +EXPORT_SYMBOL(gpio_i2c_active); + +/*! + * Setup GPIO for an I2C device to be inactive + * + * @param i2c_num an I2C device + */ +void gpio_i2c_inactive(int i2c_num) +{ + switch (i2c_num) { + case 0: + break; + case 1: + break; + case 2: + mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_GPIO); + mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_GPIO); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_i2c_inactive); + +/*! + * Setup GPIO for a CSPI device to be active + * + * @param cspi_mod an CSPI device + */ +void gpio_spi_active(int cspi_mod) +{ + switch (cspi_mod) { + case 0: + /* SPI1 */ + mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSPI1_SPI_RDY, MUX_CONFIG_FUNC); + + mxc_iomux_set_pad(MX35_PIN_CSPI1_MOSI, + PAD_CTL_DRV_1_8V | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | + PAD_CTL_100K_PD | PAD_CTL_DRV_NORMAL); + mxc_iomux_set_pad(MX35_PIN_CSPI1_MISO, + PAD_CTL_DRV_1_8V | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | + PAD_CTL_100K_PD | PAD_CTL_DRV_NORMAL); + mxc_iomux_set_pad(MX35_PIN_CSPI1_SS0, + PAD_CTL_DRV_1_8V | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | + PAD_CTL_100K_PU | PAD_CTL_ODE_CMOS | + PAD_CTL_DRV_NORMAL); + mxc_iomux_set_pad(MX35_PIN_CSPI1_SCLK, + PAD_CTL_DRV_1_8V | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | + PAD_CTL_100K_PD | PAD_CTL_DRV_NORMAL); + mxc_iomux_set_pad(MX35_PIN_CSPI1_SPI_RDY, + PAD_CTL_DRV_1_8V | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | + PAD_CTL_100K_PU | PAD_CTL_DRV_NORMAL); + break; + case 1: + /* SPI2 */ + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_spi_active); + +/*! + * Setup GPIO for a CSPI device to be inactive + * + * @param cspi_mod a CSPI device + */ +void gpio_spi_inactive(int cspi_mod) +{ + switch (cspi_mod) { + case 0: + /* SPI1 */ + mxc_free_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_CSPI1_SPI_RDY, MUX_CONFIG_GPIO); + break; + case 1: + /* SPI2 */ + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_spi_inactive); + +#define LCD_DATA_pad_enable PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | \ + PAD_CTL_DRV_1_8V | PAD_CTL_100K_PU | \ + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH +#define LCD_DATA_pad_disable PAD_CTL_PKE_ENABLE + +/*! + * Setup GPIO for LCD to be inactive + */ +#define CLEAR_LCD_PIN(pin, func) \ + mxc_iomux_set_pad(pin, LCD_DATA_pad_disable); \ + mxc_free_iomux(pin, func); + +void gpio_lcd_inactive(void) +{ + CLEAR_LCD_PIN(MX35_PIN_LD0, MUX_CONFIG_FUNC); + CLEAR_LCD_PIN(MX35_PIN_LD1, MUX_CONFIG_FUNC); + CLEAR_LCD_PIN(MX35_PIN_LD2, MUX_CONFIG_FUNC); + CLEAR_LCD_PIN(MX35_PIN_LD3, MUX_CONFIG_FUNC); + CLEAR_LCD_PIN(MX35_PIN_LD4, MUX_CONFIG_FUNC); + CLEAR_LCD_PIN(MX35_PIN_LD5, MUX_CONFIG_FUNC); + CLEAR_LCD_PIN(MX35_PIN_LD6, MUX_CONFIG_FUNC); + CLEAR_LCD_PIN(MX35_PIN_LD7, MUX_CONFIG_FUNC); + CLEAR_LCD_PIN(MX35_PIN_LD8, MUX_CONFIG_FUNC); + CLEAR_LCD_PIN(MX35_PIN_LD9, MUX_CONFIG_FUNC); + CLEAR_LCD_PIN(MX35_PIN_LD10, MUX_CONFIG_FUNC); + CLEAR_LCD_PIN(MX35_PIN_LD11, MUX_CONFIG_FUNC); + CLEAR_LCD_PIN(MX35_PIN_LD12, MUX_CONFIG_FUNC); + CLEAR_LCD_PIN(MX35_PIN_LD13, MUX_CONFIG_FUNC); + CLEAR_LCD_PIN(MX35_PIN_LD14, MUX_CONFIG_FUNC); + CLEAR_LCD_PIN(MX35_PIN_LD15, MUX_CONFIG_FUNC); + + CLEAR_LCD_PIN(MX35_PIN_LD20, MUX_CONFIG_ALT1); /* CHIP SELECT */ + CLEAR_LCD_PIN(MX35_PIN_LD21, MUX_CONFIG_ALT1); /* PAR_RS */ + CLEAR_LCD_PIN(MX35_PIN_LD22, MUX_CONFIG_ALT1); /* WRITE */ + CLEAR_LCD_PIN(MX35_PIN_LD23, MUX_CONFIG_ALT1); /* READ */ + } + +EXPORT_SYMBOL(gpio_lcd_inactive); + +/*! + * Setup GPIO for LCD to be active + */ +#define SET_LCD_PIN(pin, func) \ + err = mxc_request_iomux(pin, func); \ + if (err) { \ + goto disable_lcd_lines; \ + } \ + mxc_iomux_set_pad(pin, LCD_DATA_pad_enable); \ + +int gpio_lcd_active(void) +{ + int err; + + SET_LCD_PIN(MX35_PIN_LD0, MUX_CONFIG_FUNC); + SET_LCD_PIN(MX35_PIN_LD1, MUX_CONFIG_FUNC); + SET_LCD_PIN(MX35_PIN_LD2, MUX_CONFIG_FUNC); + SET_LCD_PIN(MX35_PIN_LD3, MUX_CONFIG_FUNC); + SET_LCD_PIN(MX35_PIN_LD4, MUX_CONFIG_FUNC); + SET_LCD_PIN(MX35_PIN_LD5, MUX_CONFIG_FUNC); + SET_LCD_PIN(MX35_PIN_LD6, MUX_CONFIG_FUNC); + SET_LCD_PIN(MX35_PIN_LD7, MUX_CONFIG_FUNC); + SET_LCD_PIN(MX35_PIN_LD8, MUX_CONFIG_FUNC); + SET_LCD_PIN(MX35_PIN_LD9, MUX_CONFIG_FUNC); + SET_LCD_PIN(MX35_PIN_LD10, MUX_CONFIG_FUNC); + SET_LCD_PIN(MX35_PIN_LD11, MUX_CONFIG_FUNC); + SET_LCD_PIN(MX35_PIN_LD12, MUX_CONFIG_FUNC); + SET_LCD_PIN(MX35_PIN_LD13, MUX_CONFIG_FUNC); + SET_LCD_PIN(MX35_PIN_LD14, MUX_CONFIG_FUNC); + SET_LCD_PIN(MX35_PIN_LD15, MUX_CONFIG_FUNC); + + return err; + +disable_lcd_lines: + gpio_lcd_inactive(); + return err; +} + +EXPORT_SYMBOL(gpio_lcd_active); + +/*! + * Setup pins for SLCD to be active + */ +void slcd_gpio_config(void) +{ + mxc_request_iomux(MX35_PIN_LD20, MUX_CONFIG_ALT1); /* CHIP SELECT */ + mxc_request_iomux(MX35_PIN_LD21, MUX_CONFIG_ALT1); /* PAR_RS */ + mxc_request_iomux(MX35_PIN_LD22, MUX_CONFIG_ALT1); /* WRITE */ + mxc_request_iomux(MX35_PIN_LD23, MUX_CONFIG_ALT1); /* READ */ +} + +EXPORT_SYMBOL(slcd_gpio_config); + +/*! + * Setup pins for Broadsheet/ISIS. + */ +#define CONTROLLER_HIRQ_LINE MX35_PIN_LD19 +#define CONTROLLER_HRST_LINE MX35_PIN_LD17 +#define CONTROLLER_HRDY_LINE MX35_PIN_LD18 +#define CONTROLLER_SUPPLY_FAULT MX35_PIN_STXFS5 +#define CONTROLLER_RESET_VAL 0 +#define CONTROLLER_NON_RESET_VAL 1 +#define WR_GPIO_LINE(addr, val) mxc_set_gpio_dataout(addr, val); +#define CONTROLLER_HIRQ_IRQ IOMUX_TO_IRQ(CONTROLLER_HIRQ_LINE) +#define CONTROLLER_PAD_EN PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | \ + PAD_CTL_DRV_1_8V | PAD_CTL_100K_PU | \ + PAD_CTL_HYS_SCHMITZ +#define CONTROLLER_PAD_DIS PAD_CTL_PKE_ENABLE + +int controller_common_gpio_config(irq_handler_t controller_irq_handler, char *controller_irq_handler_name) +{ + int result = CONTROLLER_COMMON_GPIO_INIT_SUCCESS; + + gpio_lcd_active(); + slcd_gpio_config(); + + if ( controller_irq_handler ) + { + // Set up IRQ for for Broadsheet HIRQ line. + // + disable_irq(CONTROLLER_HIRQ_IRQ); + set_irq_type(CONTROLLER_HIRQ_IRQ, IRQF_TRIGGER_RISING); + + if ( request_irq(CONTROLLER_HIRQ_IRQ, controller_irq_handler, 0, controller_irq_handler_name, NULL) ) + result = CONTROLLER_COMMON_HIRQ_RQST_FAILURE; + else + { + if ( mxc_request_iomux(CONTROLLER_HIRQ_LINE, MUX_CONFIG_GPIO) ) + result = CONTROLLER_COMMON_HIRQ_INIT_FAILURE; + else + { + // Set HIRQ pin as input. + // + mxc_set_gpio_direction(CONTROLLER_HIRQ_LINE, 1); + mxc_iomux_set_pad(CONTROLLER_HIRQ_LINE, CONTROLLER_PAD_EN); + } + } + } + + if ( CONTROLLER_COMMON_GPIO_INIT_SUCCESS == result ) + { + if ( mxc_request_iomux(CONTROLLER_HRST_LINE, MUX_CONFIG_GPIO) ) + result = CONTROLLER_COMMON_HRST_INIT_FAILURE; + else + { + // Set HRST pin as an output and initialize it to zero (it's active LOW). + // + mxc_set_gpio_direction(CONTROLLER_HRST_LINE, 0); + mxc_iomux_set_pad(CONTROLLER_HRST_LINE, CONTROLLER_PAD_EN); + mxc_set_gpio_dataout(CONTROLLER_HRST_LINE, 0); + } + } + + if ( CONTROLLER_COMMON_GPIO_INIT_SUCCESS == result ) + { + if ( mxc_request_iomux(CONTROLLER_HRDY_LINE, MUX_CONFIG_GPIO) ) + result = CONTROLLER_COMMON_HRDY_INIT_FAILURE; + else + { + // Set HRDY pin as an input. + // + mxc_set_gpio_direction(CONTROLLER_HRDY_LINE, 1); + mxc_iomux_set_pad(CONTROLLER_HRDY_LINE, CONTROLLER_PAD_EN); + } + } + + return ( result ); +} + +void controller_common_gpio_disable(int disable_bs_irq) +{ + if ( disable_bs_irq ) + { + disable_irq(CONTROLLER_HIRQ_IRQ); + free_irq(CONTROLLER_HIRQ_IRQ, NULL); + + mxc_iomux_set_pad(CONTROLLER_HIRQ_LINE, CONTROLLER_PAD_DIS); + mxc_free_iomux(CONTROLLER_HIRQ_LINE, MUX_CONFIG_GPIO); + } + + mxc_iomux_set_pad(CONTROLLER_HRST_LINE, CONTROLLER_PAD_DIS); + mxc_free_iomux(CONTROLLER_HRST_LINE, MUX_CONFIG_GPIO); + + mxc_iomux_set_pad(CONTROLLER_HRDY_LINE, CONTROLLER_PAD_DIS); + mxc_free_iomux(CONTROLLER_HRDY_LINE, MUX_CONFIG_GPIO); +} + +void controller_common_reset(void) +{ + WR_GPIO_LINE(CONTROLLER_HRST_LINE, CONTROLLER_RESET_VAL); // Assert RST. + mdelay(100); // Pause 100 ms during reset. + WR_GPIO_LINE(CONTROLLER_HRST_LINE, CONTROLLER_NON_RESET_VAL); // Clear RST. + mdelay(400); // Pause 400 ms to allow Broasheet time to come up. +} + +int controller_common_ready(void) +{ + return ( mxc_get_gpio_datain(CONTROLLER_HRDY_LINE) ); +} + +EXPORT_SYMBOL(controller_common_gpio_config); +EXPORT_SYMBOL(controller_common_gpio_disable); +EXPORT_SYMBOL(controller_common_reset); +EXPORT_SYMBOL(controller_common_ready); + +/*! + * Setup pin for touchscreen + */ +void gpio_tsc_active(void) +{ + unsigned int pad_val = PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU; + mxc_request_iomux(MX35_PIN_CAPTURE, MUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX35_PIN_CAPTURE, pad_val); + mxc_set_gpio_direction(MX35_PIN_CAPTURE, 1); +} + +/*! + * Release pin for touchscreen + */ +void gpio_tsc_inactive(void) +{ + mxc_free_iomux(MX35_PIN_CAPTURE, MUX_CONFIG_GPIO); +} + +void gpio_iomux_32khz(int enable) +{ + if (enable) { + mxc_request_iomux(MX35_PIN_CAPTURE, MUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX35_PIN_CAPTURE, + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_PUE_PUD); + mxc_iomux_set_input(MUX_IN_CCM_32K_MUXED, INPUT_CTL_PATH0); + } + else { + mxc_free_iomux(MX35_PIN_CAPTURE, MUX_CONFIG_ALT4); + } +} + +/* + * GPIO definitions for the LUIGI fiveway device + */ + +#define FIVEWAY_up_gpio MX35_PIN_ATA_DATA14 +#define FIVEWAY_down_gpio MX35_PIN_ATA_DATA15 +#define FIVEWAY_left_gpio MX35_PIN_TX5_RX0 +#define FIVEWAY_right_gpio MX35_PIN_ATA_BUFF_EN +#define FIVEWAY_select_gpio MX35_PIN_ATA_DMARQ +#define FIVEWAY_pad_enable PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | \ + PAD_CTL_DRV_1_8V | PAD_CTL_100K_PU +#define FIVEWAY_pad_disable PAD_CTL_PKE_ENABLE + + +void gpio_fiveway_inactive(void) +{ + mxc_iomux_set_pad(FIVEWAY_up_gpio, FIVEWAY_pad_disable); + mxc_iomux_set_pad(FIVEWAY_down_gpio, FIVEWAY_pad_disable); + mxc_iomux_set_pad(FIVEWAY_left_gpio, FIVEWAY_pad_disable); + mxc_iomux_set_pad(FIVEWAY_right_gpio, FIVEWAY_pad_disable); + mxc_iomux_set_pad(FIVEWAY_select_gpio, FIVEWAY_pad_disable); + mxc_free_gpio(FIVEWAY_up_gpio); + mxc_free_gpio(FIVEWAY_down_gpio); + mxc_free_gpio(FIVEWAY_left_gpio); + mxc_free_gpio(FIVEWAY_right_gpio); + mxc_free_gpio(FIVEWAY_select_gpio); +} +EXPORT_SYMBOL(gpio_fiveway_inactive); + + +#define SET_FIVEWAY_GPIO(gpio, select, path) \ + err = mxc_request_iomux(gpio, MUX_CONFIG_GPIO); \ + if (err) { \ + goto disable_fiveway_gpios; \ + } \ + mxc_set_gpio_direction(gpio, 1); \ + mxc_iomux_set_pad(gpio, FIVEWAY_pad_enable); \ + mxc_iomux_set_input(select, path); + +int gpio_fiveway_active(void) +{ + int err; + + SET_FIVEWAY_GPIO(FIVEWAY_up_gpio, MUX_IN_GPIO2_IN_27, + INPUT_CTL_PATH1); + SET_FIVEWAY_GPIO(FIVEWAY_down_gpio, MUX_IN_GPIO2_IN_28, + INPUT_CTL_PATH1); + SET_FIVEWAY_GPIO(FIVEWAY_left_gpio, MUX_IN_GPIO1_IN_10, + INPUT_CTL_PATH0); + SET_FIVEWAY_GPIO(FIVEWAY_right_gpio, MUX_IN_GPIO2_IN_30, + INPUT_CTL_PATH1); + SET_FIVEWAY_GPIO(FIVEWAY_select_gpio, MUX_IN_GPIO2_IN_31, + INPUT_CTL_PATH1); + + return err; + +disable_fiveway_gpios: + gpio_fiveway_inactive(); + return err; +} +EXPORT_SYMBOL(gpio_fiveway_active); + + +int fiveway_datain(int line_direction) +{ + iomux_pin_name_t gpio; + int err = -1; + + switch (line_direction) { + case 0: gpio = FIVEWAY_up_gpio; + break; + case 1: gpio = FIVEWAY_down_gpio; + break; + case 2: gpio = FIVEWAY_left_gpio; + break; + case 3: gpio = FIVEWAY_right_gpio; + break; + case 4: gpio = FIVEWAY_select_gpio; + break; + default: return err; + } + return mxc_get_gpio_datain(gpio); +} +EXPORT_SYMBOL(fiveway_datain); + + +int fiveway_get_irq(int line_direction) +{ + iomux_pin_name_t gpio; + int err = -1; + + switch (line_direction) { + case 0: gpio = FIVEWAY_up_gpio; + break; + case 1: gpio = FIVEWAY_down_gpio; + break; + case 2: gpio = FIVEWAY_left_gpio; + break; + case 3: gpio = FIVEWAY_right_gpio; + break; + case 4: gpio = FIVEWAY_select_gpio; + break; + default: return err; + } + return IOMUX_TO_IRQ(gpio); +} +EXPORT_SYMBOL(fiveway_get_irq); + + +/* + * GPIO definitions for the LUIGI Volume keys + */ + +#define VOLUME_UP_gpio MX35_PIN_SCKR +#define VOLUME_DOWN_gpio MX35_PIN_FSR + +#define VOLUME_pad_enable PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | \ + PAD_CTL_DRV_1_8V | PAD_CTL_100K_PU | \ + PAD_CTL_HYS_SCHMITZ +#define VOLUME_pad_disable PAD_CTL_PKE_ENABLE + + +void gpio_volume_inactive(void) +{ + mxc_iomux_set_pad(VOLUME_UP_gpio, VOLUME_pad_disable); + mxc_iomux_set_pad(VOLUME_DOWN_gpio, VOLUME_pad_disable); + mxc_free_gpio(VOLUME_UP_gpio); + mxc_free_gpio(VOLUME_DOWN_gpio); +} +EXPORT_SYMBOL(gpio_volume_inactive); + + +#define SET_VOLUME_GPIO(gpio, select, path) \ + err = mxc_request_iomux(gpio, MUX_CONFIG_GPIO); \ + if (err) { \ + goto disable_volume_gpios; \ + } \ + mxc_set_gpio_direction(gpio, 1); \ + mxc_iomux_set_pad(gpio, VOLUME_pad_enable); \ + if (select != (iomux_input_select_t)NULL) { \ + mxc_iomux_set_input(select, path); \ + } + +int gpio_volume_active(void) +{ + int err; + + SET_VOLUME_GPIO(VOLUME_UP_gpio, MUX_IN_GPIO1_IN_4, INPUT_CTL_PATH1); + SET_VOLUME_GPIO(VOLUME_DOWN_gpio, MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH1); + + return err; + +disable_volume_gpios: + gpio_volume_inactive(); + return err; +} +EXPORT_SYMBOL(gpio_volume_active); + + +int volume_datain(int line_direction) +{ + iomux_pin_name_t gpio; + int err = -1; + + switch (line_direction) { + case 0: gpio = VOLUME_UP_gpio; + break; + case 1: gpio = VOLUME_DOWN_gpio; + break; + default: return err; + } + return mxc_get_gpio_datain(gpio); +} +EXPORT_SYMBOL(volume_datain); + + +int volume_get_irq(int line_direction) +{ + iomux_pin_name_t gpio; + int err = -1; + + switch (line_direction) { + case 0: gpio = VOLUME_UP_gpio; + break; + case 1: gpio = VOLUME_DOWN_gpio; + break; + default: return err; + } + return IOMUX_TO_IRQ(gpio); +} +EXPORT_SYMBOL(volume_get_irq); + + +/*! + * Luigi keypad pin definitions + */ + +#define KB_PIN_COL0 MX35_PIN_TX2_RX3 +#define KB_PIN_COL1 MX35_PIN_TX1 +#define KB_PIN_COL2 MX35_PIN_TX0 +#define KB_PIN_COL3 MX35_PIN_HCKT +#define KB_PIN_COL6 MX35_PIN_RTS1 +#define KB_PIN_COL7 MX35_PIN_CTS1 +#define KB_PIN_ROW0 MX35_PIN_TX4_RX1 +#define KB_PIN_ROW1 MX35_PIN_TX3_RX2 +#define KB_PIN_ROW2 MX35_PIN_SCKT +#define KB_PIN_ROW3 MX35_PIN_FST +#define KB_PIN_ROW4 MX35_PIN_RXD2 +#define KB_PIN_ROW5 MX35_PIN_TXD2 +#define KB_PIN_ROW6 MX35_PIN_RTS2 +#define KB_PIN_ROW7 MX35_PIN_CTS2 +#define KB_PAD_ENABLE PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | \ + PAD_CTL_DRV_1_8V | PAD_CTL_100K_PU +#define KB_PAD_DISABLE PAD_CTL_PKE_ENABLE + + +/*! + * Release Keypad pins + */ +void gpio_keypad_inactive(void) +{ + mxc_iomux_set_pad(KB_PIN_ROW7, KB_PAD_DISABLE); + mxc_iomux_set_pad(KB_PIN_ROW6, KB_PAD_DISABLE); + mxc_iomux_set_pad(KB_PIN_ROW5, KB_PAD_DISABLE); + mxc_iomux_set_pad(KB_PIN_ROW4, KB_PAD_DISABLE); + mxc_iomux_set_pad(KB_PIN_ROW3, KB_PAD_DISABLE); + mxc_iomux_set_pad(KB_PIN_ROW2, KB_PAD_DISABLE); + mxc_iomux_set_pad(KB_PIN_ROW1, KB_PAD_DISABLE); + mxc_iomux_set_pad(KB_PIN_ROW0, KB_PAD_DISABLE); + mxc_iomux_set_pad(KB_PIN_COL7, KB_PAD_DISABLE); + mxc_iomux_set_pad(KB_PIN_COL6, KB_PAD_DISABLE); + mxc_iomux_set_pad(KB_PIN_COL3, KB_PAD_DISABLE); + mxc_iomux_set_pad(KB_PIN_COL2, KB_PAD_DISABLE); + mxc_iomux_set_pad(KB_PIN_COL1, KB_PAD_DISABLE); + mxc_iomux_set_pad(KB_PIN_COL0, KB_PAD_DISABLE); + mxc_free_iomux(KB_PIN_ROW7, MUX_CONFIG_ALT4); + mxc_free_iomux(KB_PIN_ROW6, MUX_CONFIG_ALT4); + mxc_free_iomux(KB_PIN_ROW5, MUX_CONFIG_ALT4); + mxc_free_iomux(KB_PIN_ROW4, MUX_CONFIG_ALT4); + mxc_free_iomux(KB_PIN_ROW3, MUX_CONFIG_ALT7); + mxc_free_iomux(KB_PIN_ROW2, MUX_CONFIG_ALT7); + mxc_free_iomux(KB_PIN_ROW1, MUX_CONFIG_ALT7); + mxc_free_iomux(KB_PIN_ROW0, MUX_CONFIG_ALT7); + mxc_free_iomux(KB_PIN_COL7, MUX_CONFIG_ALT4); + mxc_free_iomux(KB_PIN_COL6, MUX_CONFIG_ALT4); + mxc_free_iomux(KB_PIN_COL3, MUX_CONFIG_ALT7); + mxc_free_iomux(KB_PIN_COL2, MUX_CONFIG_ALT7); + mxc_free_iomux(KB_PIN_COL1, MUX_CONFIG_ALT7); + mxc_free_iomux(KB_PIN_COL0, MUX_CONFIG_ALT7); +} + +EXPORT_SYMBOL(gpio_keypad_inactive); + + +#define SET_KB_FUNC(gpio, config, select, path) \ + err = mxc_request_iomux(gpio, config); \ + if (err) { \ + goto disable_kb_gpios; \ + } \ + mxc_iomux_set_pad(gpio, KB_PAD_ENABLE); \ + mxc_iomux_set_input(select, path); + +/*! + * Setup Keypad pins for their special function + * + */ +int gpio_keypad_active(void) +{ + int err; + + SET_KB_FUNC(KB_PIN_COL0, MUX_CONFIG_ALT7, + MUX_IN_KPP_COL_0, INPUT_CTL_PATH1); + SET_KB_FUNC(KB_PIN_COL1, MUX_CONFIG_ALT7, + MUX_IN_KPP_COL_1, INPUT_CTL_PATH1); + SET_KB_FUNC(KB_PIN_COL2, MUX_CONFIG_ALT7, + MUX_IN_KPP_COL_2, INPUT_CTL_PATH1); + SET_KB_FUNC(KB_PIN_COL3, MUX_CONFIG_ALT7, + MUX_IN_KPP_COL_3, INPUT_CTL_PATH1); + SET_KB_FUNC(KB_PIN_COL6, MUX_CONFIG_ALT4, + MUX_IN_KPP_COL_6, INPUT_CTL_PATH0); + SET_KB_FUNC(KB_PIN_COL7, MUX_CONFIG_ALT4, + MUX_IN_KPP_COL_7, INPUT_CTL_PATH0); + SET_KB_FUNC(KB_PIN_ROW0, MUX_CONFIG_ALT7, + MUX_IN_KPP_ROW_0, INPUT_CTL_PATH1); + SET_KB_FUNC(KB_PIN_ROW1, MUX_CONFIG_ALT7, + MUX_IN_KPP_ROW_1, INPUT_CTL_PATH1); + SET_KB_FUNC(KB_PIN_ROW2, MUX_CONFIG_ALT7, + MUX_IN_KPP_ROW_2, INPUT_CTL_PATH1); + SET_KB_FUNC(KB_PIN_ROW3, MUX_CONFIG_ALT7, + MUX_IN_KPP_ROW_3, INPUT_CTL_PATH1); + SET_KB_FUNC(KB_PIN_ROW4, MUX_CONFIG_ALT4, + MUX_IN_KPP_ROW_4, INPUT_CTL_PATH0); + SET_KB_FUNC(KB_PIN_ROW5, MUX_CONFIG_ALT4, + MUX_IN_KPP_ROW_5, INPUT_CTL_PATH0); + SET_KB_FUNC(KB_PIN_ROW6, MUX_CONFIG_ALT4, + MUX_IN_KPP_ROW_6, INPUT_CTL_PATH0); + SET_KB_FUNC(KB_PIN_ROW7, MUX_CONFIG_ALT4, + MUX_IN_KPP_ROW_7, INPUT_CTL_PATH0); + + return err; + +disable_kb_gpios: + gpio_keypad_inactive(); + return err; +} + +EXPORT_SYMBOL(gpio_keypad_active); + +/* + * Get the SDIO DATA1 IRQ + */ +int gpio_sdio_irq(void) +{ + return IOMUX_TO_IRQ(MX35_PIN_SD2_DATA1); +} +EXPORT_SYMBOL(gpio_sdio_irq); + +/* + * Configure SDIO Data1 line to be an IRQ + */ +void gpio_sdio_data1(int enable) +{ + int pad_val = 0; + + if (enable) { + mxc_request_iomux(MX35_PIN_SD2_DATA1, MUX_CONFIG_ALT5); + mxc_iomux_set_input(MUX_IN_GPIO2_IN_3, INPUT_CTL_PATH1); + pad_val = PAD_CTL_DRV_NORMAL | PAD_CTL_100K_PU | PAD_CTL_PUE_PUD | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_SRE_SLOW | PAD_CTL_DRV_1_8V; + mxc_iomux_set_pad(MX35_PIN_SD2_DATA1, pad_val); + mxc_set_gpio_direction(MX35_PIN_SD2_DATA1, 1); + } + else { + mxc_free_iomux(MX35_PIN_SD2_DATA1, MUX_CONFIG_ALT5); + } +} +EXPORT_SYMBOL(gpio_sdio_data1); + +/*! + * Setup GPIO for SDHC to be active + * + * @param module SDHC module number + */ +void gpio_sdhc_active(int module) +{ + unsigned int pad_val; + + switch (module) { + case 0: + mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC | MUX_CONFIG_SION); + +#ifndef CONFIG_FEC + /* DAT4 - DAT7 Data lines for MMC 8-bit bus width */ + mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_ALT1); + mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_ALT1); + mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_ALT1); + mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_ALT1); +#endif + /* Configure the pads on SD1_CLK */ + mxc_iomux_set_pad(MX35_PIN_SD1_CLK, PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_CMOS | PAD_CTL_ODE_CMOS | + PAD_CTL_PUE_PUD | PAD_CTL_SRE_FAST | PAD_CTL_DRV_1_8V); + + pad_val = PAD_CTL_DRV_MAX | PAD_CTL_47K_PU | + PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | + PAD_CTL_SRE_FAST | PAD_CTL_DRV_1_8V; + + mxc_iomux_set_pad(MX35_PIN_SD1_CMD, pad_val); + mxc_iomux_set_pad(MX35_PIN_SD1_DATA0, pad_val); + mxc_iomux_set_pad(MX35_PIN_SD1_DATA1, pad_val); + mxc_iomux_set_pad(MX35_PIN_SD1_DATA2, pad_val); + +#ifndef CONFIG_FEC + /* DAT4 to DAT7 IOMUX setting */ + mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad_val); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad_val); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad_val); + mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad_val); + + mxc_iomux_set_input(MUX_IN_ESDHC1_DAT4_IN, INPUT_CTL_PATH1); + mxc_iomux_set_input(MUX_IN_ESDHC1_DAT5_IN, INPUT_CTL_PATH1); + mxc_iomux_set_input(MUX_IN_ESDHC1_DAT6_IN, INPUT_CTL_PATH1); + mxc_iomux_set_input(MUX_IN_ESDHC1_DAT7_IN, INPUT_CTL_PATH1); +#endif + + pad_val = PAD_CTL_DRV_MAX | PAD_CTL_100K_PU | + PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | + PAD_CTL_SRE_FAST | PAD_CTL_DRV_1_8V; + + mxc_iomux_set_pad(MX35_PIN_SD1_DATA3, pad_val); + + mdelay(100); /* Setting time */ + + break; + case 1: + /* + * ESDHC2 - Atheros WiFi + */ + mxc_request_iomux(MX35_PIN_SD2_CLK, MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD2_CMD, MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD2_DATA0, MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD2_DATA1, MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD2_DATA2, MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_SD2_DATA3, MUX_CONFIG_FUNC | MUX_CONFIG_SION); + + /* Configure the SD2_CLK */ + mxc_iomux_set_pad(MX35_PIN_SD2_CLK, PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_CMOS | PAD_CTL_ODE_CMOS | + PAD_CTL_PUE_PUD | PAD_CTL_SRE_FAST | PAD_CTL_DRV_1_8V); + + pad_val = PAD_CTL_DRV_MAX | PAD_CTL_47K_PU | + PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | + PAD_CTL_SRE_FAST | PAD_CTL_DRV_1_8V; + + mxc_iomux_set_pad(MX35_PIN_SD2_CMD, pad_val); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA0, pad_val); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA1, pad_val); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA2, pad_val); + + pad_val = PAD_CTL_DRV_MAX | PAD_CTL_100K_PU | + PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | + PAD_CTL_SRE_FAST | PAD_CTL_DRV_1_8V; + + mxc_iomux_set_pad(MX35_PIN_SD2_DATA3, pad_val); + + mdelay(100); /* Setting time */ + + break; + case 2: +#ifdef CONFIG_FEC + return; +#endif + + /* + * ESDHC3 + */ + mxc_request_iomux(MX35_PIN_ATA_DATA3, MUX_CONFIG_ALT1 | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_ATA_DATA4, MUX_CONFIG_ALT1 | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_ATA_DIOR, MUX_CONFIG_ALT1 | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_ATA_DIOW, MUX_CONFIG_ALT1 | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_ATA_DMACK, MUX_CONFIG_ALT1 | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_ATA_RESET_B, MUX_CONFIG_ALT1 | MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_ALT5); + mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_ALT5); + + mxc_iomux_set_input(MUX_IN_ESDHC3_CARD_CLK_IN, INPUT_CTL_PATH1); + mxc_iomux_set_input(MUX_IN_ESDHC3_CMD_IN, INPUT_CTL_PATH1); + mxc_iomux_set_input(MUX_IN_ESDHC3_DAT0, INPUT_CTL_PATH1); + mxc_iomux_set_input(MUX_IN_ESDHC3_DAT1, INPUT_CTL_PATH1); + mxc_iomux_set_input(MUX_IN_ESDHC3_DAT2, INPUT_CTL_PATH1); + mxc_iomux_set_input(MUX_IN_ESDHC3_DAT3, INPUT_CTL_PATH1); + + /* + * Card Detect + */ + pad_val = PAD_CTL_100K_PU; + mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad_val); + mxc_iomux_set_input(MUX_IN_GPIO3_IN_12, INPUT_CTL_PATH1); + + /* WP */ + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad_val); + mxc_set_gpio_direction(MX35_PIN_FEC_TDATA0, 0); + mxc_set_gpio_dataout(MX35_PIN_FEC_TDATA0, 1); + + pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX | + PAD_CTL_47K_PU | PAD_CTL_SRE_FAST | PAD_CTL_DRV_1_8V; + + mxc_iomux_set_pad(MX35_PIN_ATA_RESET_B, pad_val); + + pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX | + PAD_CTL_47K_PU | PAD_CTL_SRE_FAST | PAD_CTL_DRV_1_8V; + + mxc_iomux_set_pad(MX35_PIN_ATA_DATA4, pad_val); + mxc_iomux_set_pad(MX35_PIN_ATA_DIOR, pad_val); + mxc_iomux_set_pad(MX35_PIN_ATA_DIOW, pad_val); + mxc_iomux_set_pad(MX35_PIN_ATA_DMACK, pad_val); + mxc_iomux_set_pad(MX35_PIN_ATA_DATA3, pad_val); + + mdelay(100); /* Setting time */ + + break; + default: + break; + } + +} + +EXPORT_SYMBOL(gpio_sdhc_active); + + +/* + * WiFi Power Configure + */ +static void gpio_wifi_power(int enable) +{ + unsigned int pad_val; + + if (enable == 1) { + mxc_request_iomux(MX35_PIN_ATA_DATA5, MUX_CONFIG_ALT5); + pad_val = PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW | + PAD_CTL_DRV_1_8V | PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_ODE_OpenDrain; + mxc_iomux_set_pad(MX35_PIN_ATA_DATA5, pad_val); + } + else { + mxc_free_iomux(MX35_PIN_ATA_DATA5, MUX_CONFIG_ALT5); + pad_val = PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW; + mxc_iomux_set_pad(MX35_PIN_ATA_DATA5, pad_val); + } +} + +/* Hook to reset the WiFi line */ +void gpio_wifi_do_reset(void) +{ + /* Set the direction to output */ + mxc_set_gpio_direction(MX35_PIN_ATA_DATA7, 0); + + /* Pull the line low */ + mxc_set_gpio_dataout(MX35_PIN_ATA_DATA7, 0); + + mdelay(10); + + /* Pull the line high */ + mxc_set_gpio_dataout(MX35_PIN_ATA_DATA7, 1); + + mdelay(10); +} +EXPORT_SYMBOL(gpio_wifi_do_reset); + +/* + * WiFi Reset Configure + */ +static void gpio_wifi_reset(int enable) +{ + unsigned int pad_val; + + if (enable == 1) { + mxc_request_iomux(MX35_PIN_ATA_DATA7, MUX_CONFIG_ALT5); + pad_val = PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW | + PAD_CTL_DRV_1_8V | PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_ODE_OpenDrain; + mxc_iomux_set_pad(MX35_PIN_ATA_DATA7, pad_val); + } + else { + mxc_free_iomux(MX35_PIN_ATA_DATA7, MUX_CONFIG_ALT5); + pad_val = PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW; + mxc_iomux_set_pad(MX35_PIN_ATA_DATA7, pad_val); + } +} + +void gpio_wifi_enable(int enable) +{ + if (enable == 1) { + gpio_wifi_power(1); + msleep(10); /* Settling time */ + gpio_wifi_reset(1); + + mxc_set_gpio_direction(MX35_PIN_ATA_DATA5, 0); + mxc_set_gpio_dataout(MX35_PIN_ATA_DATA5, 1); + mdelay(10); /* Settling time */ + mxc_set_gpio_direction(MX35_PIN_ATA_DATA7, 0); + mxc_set_gpio_dataout(MX35_PIN_ATA_DATA7, 1); + } else { + mxc_set_gpio_direction(MX35_PIN_ATA_DATA5, 0); + mxc_set_gpio_dataout(MX35_PIN_ATA_DATA5, 0); + mdelay(10); /* Settling time */ + mxc_set_gpio_direction(MX35_PIN_ATA_DATA7, 0); + mxc_set_gpio_dataout(MX35_PIN_ATA_DATA7, 0); + gpio_wifi_power(0); + msleep(10); /* Settling time */ + gpio_wifi_reset(0); + } + +} +EXPORT_SYMBOL(gpio_wifi_enable); + +void gpio_wifi_power_enable(int enable) +{ + mxc_set_gpio_direction(MX35_PIN_ATA_DATA5, 0); + mxc_set_gpio_dataout(MX35_PIN_ATA_DATA5, enable); +} +EXPORT_SYMBOL(gpio_wifi_power_enable); + +static int wan_gpios_configured = 0; + +void gpio_wan_configure_gpios (void) +{ + unsigned int pad_val; + mxc_iomux_set_input(MUX_IN_GPIO2_IN_14, INPUT_CTL_PATH1); + + /* set up wan power pad, gpio direction, and initial state */ + mxc_request_iomux(MX35_PIN_ATA_DATA1, MUX_CONFIG_ALT5); + pad_val = PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW | + PAD_CTL_DRV_1_8V | PAD_CTL_PKE_NONE | + PAD_CTL_ODE_CMOS; + mxc_iomux_set_pad(MX35_PIN_ATA_DATA1, pad_val); + mxc_set_gpio_direction(MX35_PIN_ATA_DATA1, 0); + mxc_set_gpio_dataout(MX35_PIN_ATA_DATA1, 0); + + /* set up wan rf enable pad, gpio direction, and initial state */ + mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_ALT5); + pad_val = PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW | + PAD_CTL_DRV_1_8V | PAD_CTL_PKE_NONE | + PAD_CTL_ODE_OpenDrain; + mxc_iomux_set_pad(MX35_PIN_CSPI1_SS1, pad_val); + mxc_set_gpio_direction(MX35_PIN_CSPI1_SS1, 0); + mxc_set_gpio_dataout(MX35_PIN_CSPI1_SS1, 0); + + /* set up wan usb enable pad, gpio direction, and initial state */ + mxc_request_iomux(MX35_PIN_GPIO2_0, MUX_CONFIG_FUNC); + pad_val = PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW | + PAD_CTL_DRV_1_8V | PAD_CTL_PKE_NONE | + PAD_CTL_ODE_CMOS; + mxc_iomux_set_pad(MX35_PIN_GPIO2_0, pad_val); + mxc_set_gpio_direction(MX35_PIN_GPIO2_0, 0); + mxc_set_gpio_dataout(MX35_PIN_GPIO2_0, 0); + + wan_gpios_configured = 1; +} + +void gpio_wan_power(int enable) +{ + mxc_set_gpio_dataout(MX35_PIN_ATA_DATA1, enable ? 1 : 0); +} + +EXPORT_SYMBOL(gpio_wan_power); + +void gpio_wan_rf_enable(int enable) +{ + mxc_set_gpio_dataout(MX35_PIN_CSPI1_SS1, enable ? 1 : 0); +} + +EXPORT_SYMBOL(gpio_wan_rf_enable); + +void gpio_wan_usb_enable(int enable) +{ + mxc_set_gpio_dataout(MX35_PIN_GPIO2_0, enable ? 1 : 0); +} + +EXPORT_SYMBOL(gpio_wan_usb_enable); + +void gpio_wan_experiment_enable(int enable) +{ + if (!wan_gpios_configured) { + gpio_wan_configure_gpios(); + } + gpio_wan_power(enable); + gpio_wan_rf_enable(enable); + gpio_wan_usb_enable(enable); +} + +EXPORT_SYMBOL(gpio_wan_experiment_enable); + +void gpio_wan_exit(void *tph_event_callback) +{ + /* clear the PMIC event handler */ + pmic_power_event_unsub(PWR_IT_ONOFD2I, tph_event_callback); +} + +EXPORT_SYMBOL(gpio_wan_exit); + +void gpio_wan_init(void *tph_event_callback) +{ + int error = 0; + + /* set up the GPIO lines */ + gpio_wan_configure_gpios(); + + /* set up the PMIC event configuration for the "ON2B" line */ + pmic_power_set_conf_button(BT_ON2B, 0, 0); + error = pmic_power_event_sub(PWR_IT_ONOFD2I, tph_event_callback); + if (error < 0) + printk(KERN_ERR "Could not subscribe to the WAN TPH handler : %d\n", error); +} + +EXPORT_SYMBOL(gpio_wan_init); + +static ssize_t wan_enable_store(struct sys_device *dev, const char *buf, + size_t size) +{ + if (strstr(buf, "1") != NULL) + gpio_wan_experiment_enable(1); + else if (strstr(buf, "0") != NULL) + gpio_wan_experiment_enable(0); + + return size; +} + +static SYSDEV_ATTR(wan_enable, 0644, NULL, wan_enable_store); + +static struct sysdev_class wan_sysclass = { + .name = "wan", +}; + +static struct sys_device wan_device = { + .id = 0, + .cls = &wan_sysclass, +}; + +int wan_sysdev_ctrl_init(void) +{ + int err; + + err = sysdev_class_register(&wan_sysclass); + if (!err) + err = sysdev_register(&wan_device); + if (!err) + err = sysdev_create_file(&wan_device, &attr_wan_enable); + + return err; +} +EXPORT_SYMBOL(wan_sysdev_ctrl_init); + +void wan_sysdev_ctrl_exit(void) +{ + sysdev_remove_file(&wan_device, &attr_wan_enable); + sysdev_unregister(&wan_device); + sysdev_class_unregister(&wan_sysclass); +} +EXPORT_SYMBOL(wan_sysdev_ctrl_exit); + + +/*! + * Setup GPIO for SDHC1 to be inactive + * + * @param module SDHC module number + */ +void gpio_sdhc_inactive(int module) +{ + unsigned int pad_val; + + switch (module) { + case 0: + mxc_free_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_free_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_free_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_ALT1); + mxc_free_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_ALT1); + mxc_free_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_ALT1); + mxc_free_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_ALT1); + + mxc_iomux_set_pad(MX35_PIN_SD1_CLK, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW | PAD_CTL_100K_PD)); + mxc_iomux_set_pad(MX35_PIN_SD1_CMD, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW | PAD_CTL_100K_PD)); + mxc_iomux_set_pad(MX35_PIN_SD1_DATA0, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW | PAD_CTL_100K_PD)); + mxc_iomux_set_pad(MX35_PIN_SD1_DATA1, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW | PAD_CTL_100K_PD)); + mxc_iomux_set_pad(MX35_PIN_SD1_DATA2, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW | PAD_CTL_100K_PD)); + mxc_iomux_set_pad(MX35_PIN_SD1_DATA3, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW | PAD_CTL_100K_PD)); + + mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW | PAD_CTL_100K_PD)); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW | PAD_CTL_100K_PD)); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW | PAD_CTL_100K_PD)); + mxc_iomux_set_pad(MX35_PIN_FEC_COL, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW | PAD_CTL_100K_PD)); + break; + case 1: + mxc_free_iomux(MX35_PIN_SD2_CLK, MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_free_iomux(MX35_PIN_SD2_CMD, MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_free_iomux(MX35_PIN_SD2_DATA0, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_SD2_DATA1, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_SD2_DATA2, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_SD2_DATA3, MUX_CONFIG_FUNC); + + mxc_iomux_set_pad(MX35_PIN_SD2_CLK, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX35_PIN_SD2_CMD, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA0, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA1, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA2, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX35_PIN_SD2_DATA3, + (PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW)); + break; + case 2: + /* + * ESDHC3 + */ + mxc_free_iomux(MX35_PIN_ATA_DATA3, MUX_CONFIG_ALT1); + mxc_free_iomux(MX35_PIN_ATA_DATA4, MUX_CONFIG_ALT1); + mxc_free_iomux(MX35_PIN_ATA_DIOR, MUX_CONFIG_ALT1); + mxc_free_iomux(MX35_PIN_ATA_DIOW, MUX_CONFIG_ALT1); + mxc_free_iomux(MX35_PIN_ATA_DMACK, MUX_CONFIG_ALT1); + mxc_free_iomux(MX35_PIN_ATA_RESET_B, MUX_CONFIG_ALT1); + mxc_free_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_ALT5); + mxc_free_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_ALT5); + + pad_val = PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW; + + mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad_val); + mxc_iomux_set_pad(MX35_PIN_ATA_RESET_B, pad_val); + mxc_iomux_set_pad(MX35_PIN_ATA_DATA4, pad_val); + mxc_iomux_set_pad(MX35_PIN_ATA_DIOR, pad_val); + mxc_iomux_set_pad(MX35_PIN_ATA_DIOW, pad_val); + mxc_iomux_set_pad(MX35_PIN_ATA_DMACK, pad_val); + mxc_iomux_set_pad(MX35_PIN_ATA_DATA3, pad_val); + break; + default: + break; + } +} +EXPORT_SYMBOL(gpio_sdhc_inactive); + +/* + * Probe for the card. If present the GPIO data would be set. + */ +unsigned int sdhc_get_card_det_status(struct device *dev) +{ + if (to_platform_device(dev)->id == 0) + return 0; + else { +#ifdef CONFIG_FEC + return -1; +#else + return mxc_get_gpio_datain(MX35_PIN_FEC_TX_EN); +#endif + } +} + +EXPORT_SYMBOL(sdhc_get_card_det_status); + +/*! + * Get pin value to detect write protection + */ +int sdhc_write_protect(struct device *dev) +{ + unsigned int rc = 0; + + return rc; +} + +EXPORT_SYMBOL(sdhc_write_protect); + +/*! + * This function configures the IOMux block for PMIC standard operations. + * + */ +void gpio_pmic_active(void) +{ + unsigned int pad_val; + + /* + * PMIC IRQ + */ + mxc_request_iomux(MX35_PIN_ATA_IORDY, MUX_CONFIG_ALT5); + mxc_set_gpio_direction(MX35_PIN_ATA_IORDY, 1); + pad_val = PAD_CTL_100K_PD; + mxc_iomux_set_pad(MX35_PIN_ATA_IORDY, pad_val); + + mxc_iomux_set_input(MUX_IN_GPIO2_IN_12, INPUT_CTL_PATH1); +} + +/* + * USB Host2 + */ +int gpio_usbh2_active(void) +{ + unsigned int pad_val = PAD_CTL_DRV_MAX | PAD_CTL_100K_PU | + PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_SCHMITZ | + PAD_CTL_SRE_FAST | PAD_CTL_DRV_1_8V; + + mxc_iomux_set_input(MUX_IN_USB_UH2_USB_OC, INPUT_CTL_PATH2); +#ifndef CONFIG_FEC + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad_val); +#endif + return 0; +} + +EXPORT_SYMBOL(gpio_usbh2_active); + +void gpio_usbh2_inactive(void) +{ + /* + * Do Nothing + */ +} + +EXPORT_SYMBOL(gpio_usbh2_inactive); + +/* + * USB OTG UTMI + */ +int gpio_usbotg_utmi_active(void) +{ + /* + * Do Nothing as the Gadget is driven by Atlas + */ + return 0; +} + +EXPORT_SYMBOL(gpio_usbotg_utmi_active); + +void gpio_usbotg_utmi_inactive(void) +{ + /* + * Do nothing as the gadget is driven by Atlas + */ +} + +EXPORT_SYMBOL(gpio_usbotg_utmi_inactive); + +void gpio_sensor_active(void) +{ + /*CSI D6 */ + mxc_request_iomux(MX35_PIN_TX1, MUX_CONFIG_ALT6); + /*CSI D7 */ + mxc_request_iomux(MX35_PIN_TX0, MUX_CONFIG_ALT6); + mxc_request_iomux(MX35_PIN_CSI_D8, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_D9, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_D10, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_D11, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_D12, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_D13, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_D14, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_D15, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_HSYNC, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_MCLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_PIXCLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSI_VSYNC, MUX_CONFIG_FUNC); +} + +EXPORT_SYMBOL(gpio_sensor_active); + +void gpio_sensor_inactive(void) +{ + mxc_request_iomux(MX35_PIN_TX1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_TX0, MUX_CONFIG_FUNC); +} + +EXPORT_SYMBOL(gpio_sensor_inactive); + +/*! + * Setup GPIO for spdif tx/rx to be active + */ +void gpio_spdif_active(void) +{ + /* SPDIF OUT */ + mxc_request_iomux(MX35_PIN_STXD5, MUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX35_PIN_STXD5, PAD_CTL_PKE_NONE | PAD_CTL_PUE_PUD); + /* SPDIF IN */ + mxc_request_iomux(MX35_PIN_SRXD5, MUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX35_PIN_SRXD5, PAD_CTL_PKE_ENABLE + | PAD_CTL_100K_PU | PAD_CTL_HYS_SCHMITZ); + /* SPDIF ext clock */ + mxc_request_iomux(MX35_PIN_SCK5, MUX_CONFIG_ALT1); +} + +EXPORT_SYMBOL(gpio_spdif_active); + +/*! + * Setup GPIO for spdif tx/rx to be inactive + */ +void gpio_spdif_inactive(void) +{ + /* SPDIF OUT */ + mxc_free_iomux(MX35_PIN_STXD5, MUX_CONFIG_GPIO); + /* SPDIF IN */ + mxc_free_iomux(MX35_PIN_SRXD5, MUX_CONFIG_GPIO); + /* SPDIF ext clock */ + mxc_free_iomux(MX35_PIN_SCK5, MUX_CONFIG_GPIO); +} + +EXPORT_SYMBOL(gpio_spdif_inactive); + +/*! + * This function activates DAM ports 3 to enable + * audio I/O. + */ +void gpio_activate_audio_ports(void) +{ + unsigned int pad_val; + + mxc_request_iomux(MX35_PIN_STXD4, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SRXD4, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SCK4, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_STXFS4, MUX_CONFIG_FUNC); + + /* Audio GPIO for headset detect */ + mxc_request_iomux(MX35_PIN_CSI_PIXCLK, MUX_CONFIG_ALT5); + + pad_val = PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_PUE_PUD | PAD_CTL_DRV_1_8V; + + mxc_iomux_set_pad(MX35_PIN_STXD4, pad_val); + mxc_iomux_set_pad(MX35_PIN_SRXD4, pad_val); + mxc_iomux_set_pad(MX35_PIN_SCK4, pad_val); + mxc_iomux_set_pad(MX35_PIN_STXFS4, pad_val); + mxc_iomux_set_pad(MX35_PIN_CSI_PIXCLK, pad_val); + + mxc_set_gpio_direction(MX35_PIN_CSI_PIXCLK, 1); +} + +EXPORT_SYMBOL(gpio_activate_audio_ports); + +int gpio_headset_irq(void) +{ + return IOMUX_TO_IRQ(MX35_PIN_CSI_PIXCLK); +} + +EXPORT_SYMBOL(gpio_headset_irq); + +int gpio_headset_status(void) +{ + return mxc_get_gpio_datain(MX35_PIN_CSI_PIXCLK); +} + +EXPORT_SYMBOL(gpio_headset_status); + +/*! + * This function activates ESAI ports to enable + * surround sound I/O + */ +void gpio_activate_esai_ports(void) +{ + unsigned int pad_val; + /* ESAI TX - WM8580 */ + mxc_request_iomux(MX35_PIN_HCKT, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SCKT, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FST, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_TX0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_TX1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_FUNC); + + /* ESAI RX - AK5702 */ + /*mxc_request_iomux(MX35_PIN_HCKR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SCKR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FSR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_TX4_RX1, MUX_CONFIG_FUNC);*/ + + pad_val = PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_PUE_PUD; + /* ESAI TX - WM8580 */ + mxc_iomux_set_pad(MX35_PIN_SCKT, pad_val); + mxc_iomux_set_pad(MX35_PIN_FST, pad_val); + mxc_iomux_set_pad(MX35_PIN_TX0, pad_val); + mxc_iomux_set_pad(MX35_PIN_TX1, pad_val); + mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad_val); + + /* ESAI RX - AK5702 */ + /*mxc_iomux_set_pad(MX35_PIN_SCKR, pad_val); + mxc_iomux_set_pad(MX35_PIN_FSR, pad_val); + mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad_val); + mxc_iomux_set_pad(MX35_PIN_TX4_RX1, pad_val);*/ + + pad_val = + PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_PUE_PUD; + + /* ESAI TX - WM8580 */ + mxc_iomux_set_pad(MX35_PIN_HCKT, pad_val); + /* ESAI RX - AK5702 */ + /*mxc_iomux_set_pad(MX35_PIN_HCKR, pad_val);*/ +} + +EXPORT_SYMBOL(gpio_activate_esai_ports); + +/*! + * This function deactivates ESAI ports to disable + * surround sound I/O + */ +void gpio_deactivate_esai_ports(void) +{ + + mxc_free_iomux(MX35_PIN_HCKT, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_SCKT, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FST, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_TX0, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_TX1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_GPIO); + /*mxc_free_iomux(MX35_PIN_HCKR, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_SCKR, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FSR, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_TX4_RX1, MUX_CONFIG_GPIO);*/ +} + +EXPORT_SYMBOL(gpio_deactivate_esai_ports); + +/*! + * The MLB gpio configuration routine + */ +void gpio_mlb_active(void) +{ + mxc_request_iomux(MX35_PIN_MLB_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_MLB_SIG, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_MLB_DAT, MUX_CONFIG_FUNC); +} + +EXPORT_SYMBOL(gpio_mlb_active); + +void gpio_mlb_inactive(void) +{ + mxc_free_iomux(MX35_PIN_MLB_CLK, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_MLB_SIG, MUX_CONFIG_FUNC); + mxc_free_iomux(MX35_PIN_MLB_DAT, MUX_CONFIG_FUNC); +} + +EXPORT_SYMBOL(gpio_mlb_inactive); + +void gpio_can_active(int id) +{ + int pad; + + switch (id) { + case 0: + pad = PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | \ + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU | PAD_CTL_ODE_OpenDrain; + mxc_request_iomux(MX35_PIN_I2C2_CLK, MUX_CONFIG_ALT1); + mxc_request_iomux(MX35_PIN_I2C2_DAT, MUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX35_PIN_I2C2_CLK, pad); + mxc_iomux_set_pad(MX35_PIN_I2C2_DAT, pad); + mxc_iomux_set_input(MUX_IN_CAN1_CANRX, INPUT_CTL_PATH0); + break; + case 1: + pad = PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU; + mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_ALT1); + mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad); + mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad); + mxc_iomux_set_input(MUX_IN_CAN2_CANRX, INPUT_CTL_PATH2); + break; + default: + printk(KERN_ERR "NO such device\n"); + } +} + +void gpio_can_inactive(int id) +{ + switch (id) { + case 0: + mxc_free_iomux(MX35_PIN_I2C2_CLK, MUX_CONFIG_ALT1); + mxc_free_iomux(MX35_PIN_I2C2_DAT, MUX_CONFIG_ALT1); + mxc_iomux_set_input(MUX_IN_CAN1_CANRX, INPUT_CTL_PATH0); + break; + case 1: + mxc_free_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_ALT1); + mxc_free_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_ALT1); + mxc_iomux_set_input(MUX_IN_CAN2_CANRX, INPUT_CTL_PATH0); + break; + default: + printk(KERN_ERR "NO such device\n"); + } +} + +static int usbh1_gpio_state = 0; /* Currently disable */ +static int usbh1_gpio_configured = 0; /* Configure the GPIO */ + +static void gpio_usbh1_configure(void) +{ + mxc_request_iomux(MX35_PIN_ATA_DATA1, MUX_CONFIG_ALT5); +} + +static void gpio_usbh1_power_enable(int enable) +{ + int pad_val = 0; + + if (enable == usbh1_gpio_state) + return; + + if (enable) { + if (!usbh1_gpio_configured) { + usbh1_gpio_configured = 1; + gpio_usbh1_configure(); + } + + pad_val = PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW | + PAD_CTL_DRV_1_8V | PAD_CTL_PKE_NONE | + PAD_CTL_ODE_CMOS; + mxc_iomux_set_pad(MX35_PIN_ATA_DATA1, pad_val); + mxc_set_gpio_direction(MX35_PIN_ATA_DATA1, 0); + mxc_set_gpio_dataout(MX35_PIN_ATA_DATA1, 1); + usbh1_gpio_state = 1; + } + else { + mxc_set_gpio_dataout(MX35_PIN_ATA_DATA1, 0); + usbh1_gpio_state = 0; + } +} + +static ssize_t usbh1_gpio_store(struct sys_device *dev, const char *buf, + size_t size) +{ + if (strstr(buf, "1") != NULL) + gpio_usbh1_power_enable(1); + else if (strstr(buf, "0") != NULL) + gpio_usbh1_power_enable(0); + + return size; +} + +static SYSDEV_ATTR(usbh1_gpio_enable, 0644, NULL, usbh1_gpio_store); + +static struct sysdev_class usbh1_gpio_sysclass = { + .name = "usbh1_gpio", +}; + +static struct sys_device usbh1_gpio_device = { + .id = 0, + .cls = &usbh1_gpio_sysclass, +}; + +static int __init usbh1_gpio_sysdev_ctrl_init(void) +{ + int err; + + err = sysdev_class_register(&usbh1_gpio_sysclass); + if (!err) + err = sysdev_register(&usbh1_gpio_device); + if (!err) + err = sysdev_create_file(&usbh1_gpio_device, &attr_usbh1_gpio_enable); + + return err; +} +module_init(usbh1_gpio_sysdev_ctrl_init); + +static void __exit usbh1_gpio_sysdev_ctrl_exit(void) +{ + sysdev_remove_file(&usbh1_gpio_device, &attr_usbh1_gpio_enable); + sysdev_unregister(&usbh1_gpio_device); + sysdev_class_unregister(&usbh1_gpio_sysclass); +} +module_exit(usbh1_gpio_sysdev_ctrl_exit); diff -urN linux-2.6.26/arch/arm/mach-mx35/mx35_pins.h linux-2.6.26-lab126/arch/arm/mach-mx35/mx35_pins.h --- linux-2.6.26/arch/arm/mach-mx35/mx35_pins.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/mx35_pins.h 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,338 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_MX35_PINS_H__ +#define __ASM_ARCH_MXC_MX35_PINS_H__ + +/*! + * @file arch-mxc/mx35_pins.h + * + * @brief MX35 I/O Pin List + * + * @ingroup GPIO_MX35 + */ + +#ifndef __ASSEMBLY__ + +/*! + * @name IOMUX/PAD Bit field definitions + */ + +/*! @{ */ + +/*! + * In order to identify pins more effectively, each mux-controlled pin's + * enumerated value is constructed in the following way: + * + * ------------------------------------------------------------------- + * 31-29 | 28 - 24 |23 - 21| 20 - 10| 9 - 0 + * ------------------------------------------------------------------- + * IO_P | IO_I | RSVD | PAD_I | MUX_I + * ------------------------------------------------------------------- + * + * Bit 0 to 7 contains MUX_I used to identify the register + * offset (base is IOMUX_module_base ) defined in the Section + * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The similar field + * definitions are used for the pad control register.the MX35_PIN_A0 is + * defined in the enumeration: ( 0x28 << MUX_I) |( 0x368 << PAD_I) + * So the absolute address is: IOMUX_module_base + 0x28. + * The pad control register offset is: 0x368. + */ + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * MUX control register offset + */ +#define MUX_I 0 +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * PAD control register offset + */ +#define PAD_I 10 + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * reserved filed + */ +#define RSVD_I 21 + +#define NON_GPIO_I 0x7 +#define PIN_TO_MUX_MASK ((1<<(PAD_I - MUX_I)) - 1) +#define PIN_TO_PAD_MASK ((1<<(RSVD_I - PAD_I)) - 1) +#define NON_MUX_I PIN_TO_MUX_MASK + +#define _MXC_BUILD_PIN(gp, gi, mi, pi) \ + (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ + ((mi) << MUX_I) | ((pi) << PAD_I)) + +#define _MXC_BUILD_GPIO_PIN(gp, gi, mi, pi) \ + _MXC_BUILD_PIN(gp, gi, mi, pi) + +#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \ + _MXC_BUILD_PIN(NON_GPIO_I, 0, mi, pi) + +#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) +#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) + +/*! @} End IOMUX/PAD Bit field definitions */ + +/*! + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX35 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ +enum iomux_pins { + MX35_PIN_CAPTURE = _MXC_BUILD_GPIO_PIN(0, 4, 0x4, 0x328), + MX35_PIN_COMPARE = _MXC_BUILD_GPIO_PIN(0, 5, 0x8, 0x32C), + MX35_PIN_WATCHDOG_RST = _MXC_BUILD_GPIO_PIN(0, 6, 0xC, 0x330), + MX35_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 0x10, 0x334), + MX35_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 0x14, 0x338), + MX35_PIN_GPIO2_0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x18, 0x33C), + MX35_PIN_GPIO3_0 = _MXC_BUILD_GPIO_PIN(2, 1, 0x1C, 0x340), + MX35_PIN_CLKO = _MXC_BUILD_GPIO_PIN(0, 8, 0x20, 0x34C), + + MX35_PIN_POWER_FAIL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x360), + MX35_PIN_VSTBY = _MXC_BUILD_GPIO_PIN(0, 7, 0x24, 0x364), + MX35_PIN_A0 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x368), + MX35_PIN_A1 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x36C), + MX35_PIN_A2 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x370), + MX35_PIN_A3 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x374), + MX35_PIN_A4 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x378), + MX35_PIN_A5 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x37C), + MX35_PIN_A6 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x380), + MX35_PIN_A7 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x384), + MX35_PIN_A8 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x388), + MX35_PIN_A9 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x38C), + MX35_PIN_A10 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x390), + MX35_PIN_MA10 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x394), + MX35_PIN_A11 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x398), + MX35_PIN_A12 = _MXC_BUILD_NON_GPIO_PIN(0x5C, 0x39C), + MX35_PIN_A13 = _MXC_BUILD_NON_GPIO_PIN(0x60, 0x3A0), + MX35_PIN_A14 = _MXC_BUILD_NON_GPIO_PIN(0x64, 0x3A4), + MX35_PIN_A15 = _MXC_BUILD_NON_GPIO_PIN(0x68, 0x3A8), + MX35_PIN_A16 = _MXC_BUILD_NON_GPIO_PIN(0x6C, 0x3AC), + MX35_PIN_A17 = _MXC_BUILD_NON_GPIO_PIN(0x70, 0x3B0), + MX35_PIN_A18 = _MXC_BUILD_NON_GPIO_PIN(0x74, 0x3B4), + MX35_PIN_A19 = _MXC_BUILD_NON_GPIO_PIN(0x78, 0x3B8), + MX35_PIN_A20 = _MXC_BUILD_NON_GPIO_PIN(0x7C, 0x3BC), + MX35_PIN_A21 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x3C0), + MX35_PIN_A22 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x3C4), + MX35_PIN_A23 = _MXC_BUILD_NON_GPIO_PIN(0x88, 0x3C8), + MX35_PIN_A24 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x3CC), + MX35_PIN_A25 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x3D0), + + MX35_PIN_EB0 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x46C), + MX35_PIN_EB1 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x470), + MX35_PIN_OE = _MXC_BUILD_NON_GPIO_PIN(0x9C, 0x474), + MX35_PIN_CS0 = _MXC_BUILD_NON_GPIO_PIN(0xA0, 0x478), + MX35_PIN_CS1 = _MXC_BUILD_NON_GPIO_PIN(0xA4, 0x47C), + MX35_PIN_CS2 = _MXC_BUILD_NON_GPIO_PIN(0xA8, 0x480), + MX35_PIN_CS3 = _MXC_BUILD_NON_GPIO_PIN(0xAC, 0x484), + MX35_PIN_CS4 = _MXC_BUILD_GPIO_PIN(0, 20, 0xB0, 0x488), + MX35_PIN_CS5 = _MXC_BUILD_GPIO_PIN(0, 21, 0xB4, 0x48C), + MX35_PIN_NFCE_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xB8, 0x490), + + MX35_PIN_LBA = _MXC_BUILD_NON_GPIO_PIN(0xBC, 0x498), + MX35_PIN_BCLK = _MXC_BUILD_NON_GPIO_PIN(0xC0, 0x49C), + MX35_PIN_RW = _MXC_BUILD_NON_GPIO_PIN(0xC4, 0x4A0), + MX35_PIN_RAS = _MXC_BUILD_NON_GPIO_PIN(0xC8, 0x4A4), + MX35_PIN_CAS = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x4A8), + MX35_PIN_SDWE = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x4AC), + MX35_PIN_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0xD4, 0x4B0), + MX35_PIN_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0xD8, 0x4B4), + + MX35_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(0, 18, 0xC8, 0x4CC), + MX35_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(0, 19, 0xCC, 0x4D0), + MX35_PIN_NFALE = _MXC_BUILD_GPIO_PIN(0, 20, 0xD0, 0x4D4), + MX35_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(0, 21, 0xD4, 0x4D8), + MX35_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xD8, 0x4DC), + MX35_PIN_NFRB = _MXC_BUILD_GPIO_PIN(0, 23, 0xDC, 0x4E0), + + MX35_PIN_D15 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E4), + MX35_PIN_D14 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E8), + MX35_PIN_D13 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4EC), + MX35_PIN_D12 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F0), + MX35_PIN_D11 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F4), + MX35_PIN_D10 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F8), + MX35_PIN_D9 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4FC), + MX35_PIN_D8 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x500), + MX35_PIN_D7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x504), + MX35_PIN_D6 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x508), + MX35_PIN_D5 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x50C), + MX35_PIN_D4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x510), + MX35_PIN_D3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x514), + MX35_PIN_D2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x518), + MX35_PIN_D1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x51C), + MX35_PIN_D0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x520), + + MX35_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(0, 20, 0xE0, 0x524), + MX35_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(0, 21, 0xE4, 0x528), + MX35_PIN_CSI_D10 = _MXC_BUILD_GPIO_PIN(0, 22, 0xE8, 0x52C), + MX35_PIN_CSI_D11 = _MXC_BUILD_GPIO_PIN(0, 23, 0xEC, 0x530), + MX35_PIN_CSI_D12 = _MXC_BUILD_GPIO_PIN(0, 24, 0xF0, 0x534), + MX35_PIN_CSI_D13 = _MXC_BUILD_GPIO_PIN(0, 25, 0xF4, 0x538), + MX35_PIN_CSI_D14 = _MXC_BUILD_GPIO_PIN(0, 26, 0xF8, 0x53C), + MX35_PIN_CSI_D15 = _MXC_BUILD_GPIO_PIN(0, 27, 0xFC, 0x540), + MX35_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(0, 28, 0x100, 0x544), + MX35_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(0, 29, 0x104, 0x548), + MX35_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(0, 30, 0x108, 0x54C), + MX35_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(0, 31, 0x10C, 0x550), + + MX35_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(1, 24, 0x110, 0x554), + MX35_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(1, 25, 0x114, 0x558), + MX35_PIN_I2C2_CLK = _MXC_BUILD_GPIO_PIN(1, 26, 0x118, 0x55C), + MX35_PIN_I2C2_DAT = _MXC_BUILD_GPIO_PIN(1, 27, 0x11C, 0x560), + + MX35_PIN_STXD4 = _MXC_BUILD_GPIO_PIN(1, 28, 0x120, 0x564), + MX35_PIN_SRXD4 = _MXC_BUILD_GPIO_PIN(1, 29, 0x124, 0x568), + MX35_PIN_SCK4 = _MXC_BUILD_GPIO_PIN(1, 30, 0x128, 0x56C), + MX35_PIN_STXFS4 = _MXC_BUILD_GPIO_PIN(1, 31, 0x12C, 0x570), + MX35_PIN_STXD5 = _MXC_BUILD_GPIO_PIN(0, 0, 0x130, 0x574), + MX35_PIN_SRXD5 = _MXC_BUILD_GPIO_PIN(0, 1, 0x134, 0x578), + MX35_PIN_SCK5 = _MXC_BUILD_GPIO_PIN(0, 2, 0x138, 0x57C), + MX35_PIN_STXFS5 = _MXC_BUILD_GPIO_PIN(0, 3, 0x13C, 0x580), + + MX35_PIN_SCKR = _MXC_BUILD_GPIO_PIN(0, 4, 0x140, 0x584), + MX35_PIN_FSR = _MXC_BUILD_GPIO_PIN(0, 5, 0x144, 0x588), + MX35_PIN_HCKR = _MXC_BUILD_GPIO_PIN(0, 6, 0x148, 0x58C), + MX35_PIN_SCKT = _MXC_BUILD_GPIO_PIN(0, 7, 0x14C, 0x590), + MX35_PIN_FST = _MXC_BUILD_GPIO_PIN(0, 8, 0x150, 0x594), + MX35_PIN_HCKT = _MXC_BUILD_GPIO_PIN(0, 9, 0x154, 0x598), + MX35_PIN_TX5_RX0 = _MXC_BUILD_GPIO_PIN(0, 10, 0x158, 0x59C), + MX35_PIN_TX4_RX1 = _MXC_BUILD_GPIO_PIN(0, 11, 0x15C, 0x5A0), + MX35_PIN_TX3_RX2 = _MXC_BUILD_GPIO_PIN(0, 12, 0x160, 0x5A4), + MX35_PIN_TX2_RX3 = _MXC_BUILD_GPIO_PIN(0, 13, 0x164, 0x5A8), + MX35_PIN_TX1 = _MXC_BUILD_GPIO_PIN(0, 14, 0x168, 0x5AC), + MX35_PIN_TX0 = _MXC_BUILD_GPIO_PIN(0, 15, 0x16C, 0x5B0), + + MX35_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(0, 16, 0x170, 0x5B4), + MX35_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(0, 17, 0x174, 0x5B8), + MX35_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(0, 18, 0x178, 0x5BC), + MX35_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(0, 19, 0x17C, 0x5C0), + MX35_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(2, 4, 0x180, 0x5C4), + MX35_PIN_CSPI1_SPI_RDY = _MXC_BUILD_GPIO_PIN(2, 5, 0x184, 0x5C8), + + MX35_PIN_RXD1 = _MXC_BUILD_GPIO_PIN(2, 6, 0x188, 0x5CC), + MX35_PIN_TXD1 = _MXC_BUILD_GPIO_PIN(2, 7, 0x18C, 0x5D0), + MX35_PIN_RTS1 = _MXC_BUILD_GPIO_PIN(2, 8, 0x190, 0x5D4), + MX35_PIN_CTS1 = _MXC_BUILD_GPIO_PIN(2, 9, 0x194, 0x5D8), + MX35_PIN_RXD2 = _MXC_BUILD_GPIO_PIN(2, 10, 0x198, 0x5DC), + MX35_PIN_TXD2 = _MXC_BUILD_GPIO_PIN(1, 11, 0x19C, 0x5E0), + MX35_PIN_RTS2 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1A0, 0x5E4), + MX35_PIN_CTS2 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1A4, 0x5E8), + + MX35_PIN_USBOTG_PWR = _MXC_BUILD_GPIO_PIN(2, 14, 0x1A8, 0x60C), + MX35_PIN_USBOTG_OC = _MXC_BUILD_GPIO_PIN(2, 15, 0x1AC, 0x610), + + MX35_PIN_LD0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x1B0, 0x614), + MX35_PIN_LD1 = _MXC_BUILD_GPIO_PIN(1, 1, 0x1B4, 0x618), + MX35_PIN_LD2 = _MXC_BUILD_GPIO_PIN(1, 2, 0x1B8, 0x61C), + MX35_PIN_LD3 = _MXC_BUILD_GPIO_PIN(1, 3, 0x1BC, 0x620), + MX35_PIN_LD4 = _MXC_BUILD_GPIO_PIN(1, 4, 0x1C0, 0x624), + MX35_PIN_LD5 = _MXC_BUILD_GPIO_PIN(1, 5, 0x1C4, 0x628), + MX35_PIN_LD6 = _MXC_BUILD_GPIO_PIN(1, 6, 0x1C8, 0x62C), + MX35_PIN_LD7 = _MXC_BUILD_GPIO_PIN(1, 7, 0x1CC, 0x630), + MX35_PIN_LD8 = _MXC_BUILD_GPIO_PIN(1, 8, 0x1D0, 0x634), + MX35_PIN_LD9 = _MXC_BUILD_GPIO_PIN(1, 9, 0x1D4, 0x638), + MX35_PIN_LD10 = _MXC_BUILD_GPIO_PIN(1, 10, 0x1D8, 0x63C), + MX35_PIN_LD11 = _MXC_BUILD_GPIO_PIN(1, 11, 0x1DC, 0x640), + MX35_PIN_LD12 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1E0, 0x644), + MX35_PIN_LD13 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1E4, 0x648), + MX35_PIN_LD14 = _MXC_BUILD_GPIO_PIN(1, 14, 0x1E8, 0x64C), + MX35_PIN_LD15 = _MXC_BUILD_GPIO_PIN(1, 15, 0x1EC, 0x650), + MX35_PIN_LD16 = _MXC_BUILD_GPIO_PIN(1, 16, 0x1F0, 0x654), + MX35_PIN_LD17 = _MXC_BUILD_GPIO_PIN(1, 17, 0x1F4, 0x658), + MX35_PIN_LD18 = _MXC_BUILD_GPIO_PIN(2, 24, 0x1F8, 0x65C), + MX35_PIN_LD19 = _MXC_BUILD_GPIO_PIN(2, 25, 0x1FC, 0x660), + MX35_PIN_LD20 = _MXC_BUILD_GPIO_PIN(2, 26, 0x200, 0x664), + MX35_PIN_LD21 = _MXC_BUILD_GPIO_PIN(2, 27, 0x204, 0x668), + MX35_PIN_LD22 = _MXC_BUILD_GPIO_PIN(2, 28, 0x208, 0x66C), + MX35_PIN_LD23 = _MXC_BUILD_GPIO_PIN(2, 29, 0x20C, 0x670), + + MX35_PIN_D3_HSYNC = _MXC_BUILD_GPIO_PIN(2, 30, 0x210, 0x674), + MX35_PIN_D3_FPSHIFT = _MXC_BUILD_GPIO_PIN(2, 31, 0x214, 0x678), + MX35_PIN_D3_DRDY = _MXC_BUILD_GPIO_PIN(0, 0, 0x218, 0x67C), + MX35_PIN_CONTRAST = _MXC_BUILD_GPIO_PIN(0, 1, 0x21C, 0x680), + MX35_PIN_D3_VSYNC = _MXC_BUILD_GPIO_PIN(0, 2, 0x220, 0x684), + MX35_PIN_D3_REV = _MXC_BUILD_GPIO_PIN(0, 3, 0x224, 0x688), + MX35_PIN_D3_CLS = _MXC_BUILD_GPIO_PIN(0, 4, 0x228, 0x68C), + MX35_PIN_D3_SPL = _MXC_BUILD_GPIO_PIN(0, 5, 0x22C, 0x690), + + MX35_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 6, 0x230, 0x694), + MX35_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 7, 0x234, 0x698), + MX35_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 8, 0x238, 0x69C), + MX35_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 9, 0x23C, 0x6A0), + MX35_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 10, 0x240, 0x6A4), + MX35_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 11, 0x244, 0x6A8), + MX35_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(1, 0, 0x248, 0x6AC), + MX35_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(1, 1, 0x24C, 0x6B0), + MX35_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(1, 2, 0x250, 0x6B4), + MX35_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(1, 3, 0x254, 0x6B8), + MX35_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(1, 4, 0x258, 0x6BC), + MX35_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(1, 5, 0x25C, 0x6C0), + + MX35_PIN_ATA_CS0 = _MXC_BUILD_GPIO_PIN(1, 6, 0x260, 0x6C4), + MX35_PIN_ATA_CS1 = _MXC_BUILD_GPIO_PIN(1, 7, 0x264, 0x6C8), + MX35_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(1, 8, 0x268, 0x6CC), + MX35_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(1, 9, 0x26C, 0x6D0), + MX35_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(1, 10, 0x270, 0x6D4), + MX35_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(1, 11, 0x274, 0x6D8), + MX35_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(1, 12, 0x278, 0x6DC), + MX35_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 13, 0x27C, 0x6E0), + MX35_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 14, 0x280, 0x6E4), + MX35_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 15, 0x284, 0x6E8), + MX35_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 16, 0x288, 0x6EC), + MX35_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 17, 0x28C, 0x6F0), + MX35_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 18, 0x290, 0x6F4), + MX35_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 19, 0x294, 0x6F8), + MX35_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 20, 0x298, 0x6FC), + MX35_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 21, 0x29C, 0x700), + MX35_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 22, 0x2A0, 0x704), + MX35_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 23, 0x2A4, 0x708), + MX35_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 24, 0x2A8, 0x70C), + MX35_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 25, 0x2AC, 0x710), + MX35_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 26, 0x2B0, 0x714), + MX35_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 27, 0x2B4, 0x718), + MX35_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 28, 0x2B8, 0x71C), + MX35_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(1, 29, 0x2BC, 0x720), + MX35_PIN_ATA_BUFF_EN = _MXC_BUILD_GPIO_PIN(1, 30, 0x2C0, 0x724), + MX35_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(1, 31, 0x2C4, 0x728), + MX35_PIN_ATA_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 0x2C8, 0x72C), + MX35_PIN_ATA_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 0x2CC, 0x730), + MX35_PIN_ATA_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 0x2D0, 0x734), + + MX35_PIN_MLB_CLK = _MXC_BUILD_GPIO_PIN(2, 3, 0x2D4, 0x738), + MX35_PIN_MLB_DAT = _MXC_BUILD_GPIO_PIN(2, 4, 0x2D8, 0x73C), + MX35_PIN_MLB_SIG = _MXC_BUILD_GPIO_PIN(2, 5, 0x2DC, 0x740), + + MX35_PIN_FEC_TX_CLK = _MXC_BUILD_GPIO_PIN(2, 6, 0x2E0, 0x744), + MX35_PIN_FEC_RX_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 0x2E4, 0x748), + MX35_PIN_FEC_RX_DV = _MXC_BUILD_GPIO_PIN(2, 8, 0x2E8, 0x74C), + MX35_PIN_FEC_COL = _MXC_BUILD_GPIO_PIN(2, 9, 0x2EC, 0x750), + MX35_PIN_FEC_RDATA0 = _MXC_BUILD_GPIO_PIN(2, 10, 0x2F0, 0x754), + MX35_PIN_FEC_TDATA0 = _MXC_BUILD_GPIO_PIN(2, 11, 0x2F4, 0x758), + MX35_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(2, 12, 0x2F8, 0x75C), + MX35_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(2, 13, 0x2FC, 0x760), + MX35_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(2, 14, 0x300, 0x764), + MX35_PIN_FEC_TX_ERR = _MXC_BUILD_GPIO_PIN(2, 15, 0x304, 0x768), + MX35_PIN_FEC_RX_ERR = _MXC_BUILD_GPIO_PIN(2, 16, 0x308, 0x76C), + MX35_PIN_FEC_CRS = _MXC_BUILD_GPIO_PIN(2, 17, 0x30C, 0x770), + MX35_PIN_FEC_RDATA1 = _MXC_BUILD_GPIO_PIN(2, 18, 0x310, 0x774), + MX35_PIN_FEC_TDATA1 = _MXC_BUILD_GPIO_PIN(2, 19, 0x314, 0x778), + MX35_PIN_FEC_RDATA2 = _MXC_BUILD_GPIO_PIN(2, 20, 0x318, 0x77C), + MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780), + MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784), + MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788), +}; + +#endif +#endif diff -urN linux-2.6.26/arch/arm/mach-mx35/mx35evb.c linux-2.6.26-lab126/arch/arm/mach-mx35/mx35evb.c --- linux-2.6.26/arch/arm/mach-mx35/mx35evb.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/mx35evb.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,396 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE) +#include +#include +#include + +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "board-mx35evb.h" +#include "crm_regs.h" +#include "iomux.h" + +/*! + * @file mach-mx35/mx35evb.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX35 + */ + +unsigned int mx35evb_board_io; + +static void mxc_nop_release(struct device *dev) +{ + /* Nothing */ +} + +/* MTD NOR flash */ + +#if defined(CONFIG_MTD_MXC) || defined(CONFIG_MTD_MXC_MODULE) + +static struct mtd_partition mxc_nor_partitions[] = { + { + .name = "Bootloader", + .size = 512 * 1024, + .offset = 0x00000000, + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, + { + .name = "nor.Kernel", + .size = 4 * 1024 * 1024, + .offset = MTDPART_OFS_APPEND, + .mask_flags = 0}, + { + .name = "nor.userfs", + .size = 30 * 1024 * 1024, + .offset = MTDPART_OFS_APPEND, + .mask_flags = 0}, + { + .name = "nor.rootfs", + .size = 28 * 1024 * 1024, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE}, + { + .name = "FIS directory", + .size = 12 * 1024, + .offset = 0x01FE0000, + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, + { + .name = "Redboot config", + .size = MTDPART_SIZ_FULL, + .offset = 0x01FFF000, + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, +}; + +static struct flash_platform_data mxc_flash_data = { + .map_name = "cfi_probe", + .width = 2, + .parts = mxc_nor_partitions, + .nr_parts = ARRAY_SIZE(mxc_nor_partitions), +}; + +static struct resource mxc_flash_resource = { + .start = 0xa0000000, + .end = 0xa0000000 + 0x04000000 - 1, + .flags = IORESOURCE_MEM, + +}; + +static struct platform_device mxc_nor_mtd_device = { + .name = "mxc_nor_flash", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_flash_data, + }, + .num_resources = 1, + .resource = &mxc_flash_resource, +}; + +static void mxc_init_nor_mtd(void) +{ + (void)platform_device_register(&mxc_nor_mtd_device); +} +#else +static void mxc_init_nor_mtd(void) +{ +} +#endif + +/* MTD NAND flash */ + +#if defined(CONFIG_MTD_NAND_MXC) || defined(CONFIG_MTD_NAND_MXC_MODULE) + +static struct mtd_partition mxc_nand_partitions[] = { + { + .name = "IPL-SPL", + .offset = 0, + .size = 256 * 1024}, + { + .name = "nand.kernel", + .offset = MTDPART_OFS_APPEND, + .size = 4 * 1024 * 1024}, + { + .name = "nand.rootfs", + .offset = MTDPART_OFS_APPEND, + .size = 96 * 1024 * 1024}, + { + .name = "nand.configure", + .offset = MTDPART_OFS_APPEND, + .size = 8 * 1024 * 1024}, + { + .name = "nand.userfs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL}, +}; + +static struct flash_platform_data mxc_nand_data = { + .parts = mxc_nand_partitions, + .nr_parts = ARRAY_SIZE(mxc_nand_partitions), + .width = 1, +}; + +static struct platform_device mxc_nand_mtd_device = { + .name = "mxc_nand_flash", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_nand_data, + }, +}; + +static void mxc_init_nand_mtd(void) +{ + if (__raw_readl(MXC_CCM_RCSR) & MXC_CCM_RCSR_NF16B) + mxc_nand_data.width = 2; + + platform_device_register(&mxc_nand_mtd_device); +} +#else +static inline void mxc_init_nand_mtd(void) +{ +} +#endif + +#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) +static struct resource smsc911x_resources[] = { + { + .start = ENET_BASE_ADDRESS, + .end = ENET_BASE_ADDRESS + 0x100, + .flags = IORESOURCE_MEM,}, + { + .start = EXPIO_INT_ENET, + .end = EXPIO_INT_ENET, + .flags = IORESOURCE_IRQ,} +}; + +static struct platform_device mxc_smsc911x_device = { + .name = "smsc911x", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, +}; + +static void mxc_init_enet(void) +{ + int i; + /*reset ext uart in cpld */ + __raw_writew(PBC_BCTRL1_ENET_RST_B, PBC_BCTRL1_SET); + /*delay some time for reset finish */ + for (i = 0; i < 10000; i++) ; + __raw_writew(PBC_BCTRL1_ENET_RST_B, PBC_BCTRL1_CLR); + + platform_device_register(&mxc_smsc911x_device); +} +#else +static inline void mxc_init_enet(void) +{ +} +#endif + +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) +unsigned int expio_intr_fec; + +EXPORT_SYMBOL(expio_intr_fec); +#endif + +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mxc_cpu_init(); + +#ifdef CONFIG_DISCONTIGMEM + do { + int nid; + mi->nr_banks = MXC_NUMNODES; + for (nid = 0; nid < mi->nr_banks; nid++) + SET_NODE(mi, nid); + } while (0); +#endif +} + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + mxc_cpu_common_init(); + mxc_clocks_init(); + early_console_setup(saved_command_line); + mxc_gpio_init(); + mx35evb_gpio_init(); + mxc_init_enet(); + mxc_init_nor_mtd(); + mxc_init_nand_mtd(); + +} + +#define PLL_PCTL_REG(brmo, pd, mfd, mfi, mfn) \ + (((brmo) << 31) + (((pd) - 1) << 26) + (((mfd) - 1) << 16) + \ + ((mfi) << 10) + mfn) + +/* For 24MHz input clock */ +#define PLL_665MHZ PLL_PCTL_REG(1, 1, 48, 13, 41) +#define PLL_532MHZ PLL_PCTL_REG(1, 1, 12, 11, 1) +#define PLL_399MHZ PLL_PCTL_REG(0, 1, 16, 8, 5) + +/* working point(wp): 0,1 - 133MHz; 2,3 - 266MHz; 4,5 - 399MHz;*/ +/* auto input clock table */ +static struct cpu_wp cpu_wp_auto[] = { + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 133000000, + .pdr0_reg = (0x2 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 133000000, + .pdr0_reg = (0x6 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 266000000, + .pdr0_reg = (0x1 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 266000000, + .pdr0_reg = (0x5 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 399000000, + .pdr0_reg = (0x0 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 399000000, + .pdr0_reg = (0x6 << MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET),}, +}; + +/* consumer input clock table */ +static struct cpu_wp cpu_wp_con[] = { + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 133000000, + .pdr0_reg = (0x6 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 133000000, + .pdr0_reg = (0xE << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 266000000, + .pdr0_reg = (0x2 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 266000000, + .pdr0_reg = (0xA << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 399000000, + .pdr0_reg = (0x1 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 399000000, + .pdr0_reg = (0x9 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 532000000, + .pdr0_reg = (0x0 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 532000000, + .pdr0_reg = (0x8 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, + { + .pll_reg = PLL_665MHZ, + .pll_rate = 665000000, + .cpu_rate = 665000000, + .pdr0_reg = (0x7 << MXC_CCM_PDR0_CON_MUX_DIV_OFFSET),}, +}; + +struct cpu_wp *get_cpu_wp(int *wp) +{ + if (__raw_readl(MXC_CCM_PDR0) & MXC_CCM_PDR0_AUTO_CON) { + *wp = 9; + return cpu_wp_con; + } else { + *wp = 6; + return cpu_wp_auto; + } +} + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX35EVB data structure. + */ +/* *INDENT-OFF* */ +MACHINE_START(MX35EVB, "Freescale MX35 EVB") + /* Maintainer: Freescale Semiconductor, Inc. */ + .phys_io = AIPS1_BASE_ADDR, + .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .fixup = fixup_mxc_board, + .map_io = mxc_map_io, + .init_irq = mxc_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff -urN linux-2.6.26/arch/arm/mach-mx35/mx35evb_cpld.c linux-2.6.26-lab126/arch/arm/mach-mx35/mx35evb_cpld.c --- linux-2.6.26/arch/arm/mach-mx35/mx35evb_cpld.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/mx35evb_cpld.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,82 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "board-mx35evb.h" +#include "iomux.h" + +/*! + * @file mach-mx35/mx35evb_cpld.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX35 + */ + +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) +{ + /*TODO:virtual interrupt dispatcher */ +} + +/* + * Disable an expio pin's interrupt by setting the bit in the imr. + * @param irq an expio virtual irq number + */ +static void expio_mask_irq(u32 irq) +{ + /*TODO:mask virtual interrupt #irq */ +} + +/* + * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. + * @param irq an expanded io virtual irq number + */ +static void expio_ack_irq(u32 irq) +{ + /*TODO:ack & mask virtual interrupt #irq */ +} + +/* + * Enable a expio pin's interrupt by clearing the bit in the imr. + * @param irq a expio virtual irq number + */ +static void expio_unmask_irq(u32 irq) +{ + /*TODO:enable virtual interrupt #irq */ +} + +static struct irq_chip expio_irq_chip = { + .ack = expio_ack_irq, + .mask = expio_mask_irq, + .unmask = expio_unmask_irq, +}; + +static int __init mxc_expio_init(void) +{ + /*TODO:enable virtual interrupts generated by CPLD */ + return 0; +} + +arch_initcall(mxc_expio_init); diff -urN linux-2.6.26/arch/arm/mach-mx35/mx35evb_gpio.c linux-2.6.26-lab126/arch/arm/mach-mx35/mx35evb_gpio.c --- linux-2.6.26/arch/arm/mach-mx35/mx35evb_gpio.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/mx35evb_gpio.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,276 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include "board-mx35evb.h" +#include "iomux.h" + +/*! + * @file mach-mx35/mx35evb_gpio.c + * + * @brief This file contains all the GPIO setup functions for the board. + * + * @ingroup GPIO_MX35 + */ + +/*! + * This system-wise GPIO function initializes the pins during system startup. + * All the statically linked device drivers should put the proper GPIO + * initialization code inside this function. It is called by \b fixup_mx31ads() + * during system startup. This function is board specific. + */ +void mx35evb_gpio_init(void) +{ + /* config CS4 */ + mxc_request_iomux(MX35_PIN_CS4, MUX_CONFIG_FUNC); + +} + +/*! + * Setup GPIO for a UART port to be active + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_active(int port, int no_irda) +{ + /* + * Configure the IOMUX control registers for the UART signals + */ + switch (port) { + /* UART 1 IOMUX Configs */ + case 0: + mxc_request_iomux(MX35_PIN_RXD1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_TXD1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_RTS1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CTS1, MUX_CONFIG_FUNC); + + mxc_iomux_set_pad(MX35_PIN_RXD1, + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX35_PIN_TXD1, + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_RTS1, + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX35_PIN_CTS1, + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); + + break; + /* UART 2 IOMUX Configs */ + case 1: + mxc_request_iomux(MX35_PIN_TXD2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_RXD2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_RTS2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CTS2, MUX_CONFIG_FUNC); + + mxc_iomux_set_pad(MX35_PIN_RXD2, + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX35_PIN_TXD2, + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_RTS2, + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX35_PIN_CTS2, + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); + + break; + /* UART 3 IOMUX Configs */ + case 2: + mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_ALT2); + mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_ALT2); + mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_ALT2); + mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_ALT2); + + mxc_iomux_set_input(MUX_IN_UART3_UART_RTS_B, INPUT_CTL_PATH2); + mxc_iomux_set_input(MUX_IN_UART3_UART_RXD_MUX, INPUT_CTL_PATH3); + break; + default: + break; + } + +} + +EXPORT_SYMBOL(gpio_uart_active); + +/*! + * Setup GPIO for a UART port to be inactive + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_inactive(int port, int no_irda) +{ + switch (port) { + case 0: + mxc_request_gpio(MX35_PIN_RXD1); + mxc_request_gpio(MX35_PIN_TXD1); + mxc_request_gpio(MX35_PIN_RTS1); + mxc_request_gpio(MX35_PIN_CTS1); + + mxc_free_iomux(MX35_PIN_RXD1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_TXD1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_RTS1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_CTS1, MUX_CONFIG_GPIO); + break; + case 1: + mxc_request_gpio(MX35_PIN_RXD2); + mxc_request_gpio(MX35_PIN_TXD2); + mxc_request_gpio(MX35_PIN_RTS2); + mxc_request_gpio(MX35_PIN_CTS2); + + mxc_free_iomux(MX35_PIN_RXD2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_TXD2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_RTS2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_CTS2, MUX_CONFIG_GPIO); + break; + case 2: + mxc_request_gpio(MX35_PIN_FEC_TX_CLK); + mxc_request_gpio(MX35_PIN_FEC_RX_CLK); + mxc_request_gpio(MX35_PIN_FEC_COL); + mxc_request_gpio(MX35_PIN_FEC_RX_DV); + + mxc_free_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_GPIO); + + mxc_iomux_set_input(MUX_IN_UART3_UART_RTS_B, INPUT_CTL_PATH0); + mxc_iomux_set_input(MUX_IN_UART3_UART_RXD_MUX, INPUT_CTL_PATH0); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_uart_inactive); + +/*! + * Configure the IOMUX GPR register to receive shared SDMA UART events + * + * @param port a UART port + */ +void config_uartdma_event(int port) +{ +} + +EXPORT_SYMBOL(config_uartdma_event); + +void gpio_fec_active(void) +{ + /*TODO:require the pins related with FEC */ +} + +EXPORT_SYMBOL(gpio_fec_active); + +void gpio_fec_inactive(void) +{ + /*TODO:release the pins related with FEC */ +} + +EXPORT_SYMBOL(gpio_fec_inactive); + +/*! + * Setup GPIO for a CSPI device to be active + * + * @param cspi_mod an CSPI device + */ +void gpio_spi_active(int cspi_mod) +{ + switch (cspi_mod) { + case 0: + /* SPI1 */ + mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_CSPI1_SPI_RDY, MUX_CONFIG_FUNC); + + mxc_iomux_set_pad(MX35_PIN_CSPI1_MOSI, + PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | + PAD_CTL_100K_PD | PAD_CTL_DRV_NORMAL); + mxc_iomux_set_pad(MX35_PIN_CSPI1_MISO, + PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | + PAD_CTL_100K_PD | PAD_CTL_DRV_NORMAL); + mxc_iomux_set_pad(MX35_PIN_CSPI1_SS0, + PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | + PAD_CTL_100K_PU | PAD_CTL_ODE_CMOS | + PAD_CTL_DRV_NORMAL); + mxc_iomux_set_pad(MX35_PIN_CSPI1_SS1, + PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | + PAD_CTL_100K_PU | PAD_CTL_ODE_CMOS | + PAD_CTL_DRV_NORMAL); + mxc_iomux_set_pad(MX35_PIN_CSPI1_SCLK, + PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | + PAD_CTL_100K_PD | PAD_CTL_DRV_NORMAL); + mxc_iomux_set_pad(MX35_PIN_CSPI1_SPI_RDY, + PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | + PAD_CTL_100K_PU | PAD_CTL_DRV_NORMAL); + break; + case 1: + /* SPI2 */ + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_spi_active); + +/*! + * Setup GPIO for a CSPI device to be inactive + * + * @param cspi_mod a CSPI device + */ +void gpio_spi_inactive(int cspi_mod) +{ + switch (cspi_mod) { + case 0: + /* SPI1 */ + mxc_request_gpio(MX35_PIN_CSPI1_MOSI); + mxc_request_gpio(MX35_PIN_CSPI1_MISO); + mxc_request_gpio(MX35_PIN_CSPI1_SS0); + mxc_request_gpio(MX35_PIN_CSPI1_SS1); + mxc_request_gpio(MX35_PIN_CSPI1_SCLK); + mxc_request_gpio(MX35_PIN_CSPI1_SPI_RDY); + + mxc_free_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_GPIO); + mxc_free_iomux(MX35_PIN_CSPI1_SPI_RDY, MUX_CONFIG_GPIO); + break; + case 1: + /* SPI2 */ + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_spi_inactive); diff -urN linux-2.6.26/arch/arm/mach-mx35/pm.c linux-2.6.26-lab126/arch/arm/mach-mx35/pm.c --- linux-2.6.26/arch/arm/mach-mx35/pm.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/pm.c 2010-08-11 00:35:00.000000000 -0400 @@ -0,0 +1,383 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * Implement low power state retention mode for MX35 Luigi + * + * State Retention mode is the STOP mode of the MX35. Here is how the processor + * transitions to STOP mode. + * + * The CLKMOD is set to 11. This should be sufficient to gate the mcu_pll clock. + * The 24MHz oscillator disabled in STOP mode. Once OSC24 is disabled, mcu_pll + * can be gated. The clock source will shift to the 32KHz coming from Atlas. This + * ckil_clk is alternate source. + * Once mcu_pll is gated, VPLL can be put in low power + * + * Copyright (C) 2009 Amazon Technologies, Inc. All Rights Reserved. + * Manish Lachwani (lachwani@lab126.com) + */ +#include +#include +#include +#include +#include +#if defined(CONFIG_CPU_FREQ) +#include +#endif +#include + +#include +#include "crm_regs.h" +#include "iomux.h" + +#include + +extern int get_pmic_revision(void); + +extern void gpio_papyrus_configure(int enable); +extern void gpio_pm_set_value(int val); + +extern void cko1_enable(void); +extern void cko1_disable(void); + +static struct cpu_wp *cpu_wp_tbl; +static struct clk *cpu_clk; +extern struct cpu_wp *get_cpu_wp(int *wp); + +extern void gpio_iomux_32khz(int); + +extern void doze_disable(void); +extern void doze_enable(void); + +/*! + * Turn off accessory on suspend and enable on resume + */ +extern void mx35_accessory_enable(int enable); + + +/*! + * @defgroup MSL_MX35 i.MX35 Machine Specific Layer (MSL) + */ + +#if defined(CONFIG_CPU_FREQ) + +#define MAX_CPU_FREQUENCY 512000000 +#define MIN_CPU_FREQUENCY 256000000 + +extern int cpufreq_suspended; +extern int set_cpu_freq(int wp); + +#endif + +/*! Workaround the Broken mode switch on Atlas parts */ +static int mc13892_broken_mode_switch = 1; + +/*! + * Defines for SW2 - CPU + */ +#define SW2HI_LSH 23 /* Bit 23 in Register 25 */ +#define SW2NORMAL_LSH 0 /* Normal mode voltage for SW2 */ +#define SW2STANDBY_LSH 10 /* Standby mode voltage for SW2 */ +#define SW2_NORMAL_MASK 0x3ff /* SW2 Voltage Mask */ +#define SW2_STANDBY_MASK 0x1f +#define SW2HI_VOLTAGE 0x35A /* 1.25V with SW2HI bit 0 */ +#define SW2LOW_VOLTAGE 0x10 /* 1.0V with SW2HI bit 0 */ + +#define MX35_CPU_MAX_VOLTAGE 0x16B /* 1.47V */ +#define SW2_VOLTAGE_MASK 0x3ff /* Bits 0-9 mask for register 25 */ + +/*! + * Charger detect + */ +#define CHGDETS 0x40 /* Sense bit for CHGDET */ + +/*! + * Track down device suspends + */ +atomic_t mxc_device_suspended = ATOMIC_INIT(0); + +/*! + * Generic GPIO disable on system suspend + */ +static void mx35_suspend_gpio(void) +{ + gpio_papyrus_configure(0); + + /* Turn on the 32KHz clock */ + gpio_iomux_32khz(1); + + /* Pull the test point low */ + gpio_pm_set_value(0); +} + +/*! + * Generic GPIO enable on system resume + */ +static void mx35_resume_gpio(void) +{ + /* Pull the test point high */ + gpio_pm_set_value(1); + + gpio_papyrus_configure(1); + + /* Reset the 32Khz GPIO */ + gpio_iomux_32khz(0); +} + +/*! + * Check if Atlas Rev 3.1 + */ +static int check_atlas_rev31(void) +{ + int reg = 0; + + pmic_read_reg(REG_IDENTIFICATION, ®, 0xffffffff); + + if (reg & 0x1) + return 1; + else + return 0; +} + +/*! + * @file mach-mx35/pm.c + * @brief This file contains suspend operations + * + * @ingroup MSL_MX35 + */ +static int mx35_suspend_enter(suspend_state_t state) +{ + unsigned int ccmr = __raw_readl(MXC_CCM_CCMR); /* Known good value */ + unsigned int reg; + unsigned int pmcr2 = __raw_readl(MXC_CCM_PMCR2); + + __raw_writel(MXC_INT_GPT, AVIC_INTDISNUM); + local_fiq_disable(); + + /* Increment the suspended counter */ + atomic_set(&mxc_device_suspended, 1); + + mx35_suspend_gpio(); + + /* + * Turn off the CAN modules 0 and 1. This is in the CGR0, bits 4, 5, 6, 7 + * The CAN bus is driven from the 24MHz Audio oscillator. Since the Luigi + * V3 boards have the audio oscillator removed, the CAN bus needs to be gated + * first + */ + reg = __raw_readl(MXC_CCM_CGR0); + reg &= 0xfffffC3f; + __raw_writel(reg, MXC_CCM_CGR0); + + pmcr2 |= 0x10000; /* Set the OSC24MDOWN bit to 1 */ + pmcr2 |= 0x20000; /* Set the OSC_AUDIO_DOWN to 0 */ + pmcr2 |= 0xff800000; /* Set the OSD_RDY_CNT */ + __raw_writel(pmcr2, MXC_CCM_PMCR2); + + reg = ccmr & ~(MXC_CCM_CCMR_UPE); + reg |= 0xF << MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET; + __raw_writel(reg, MXC_CCM_CCMR); /* Gate the peri_pll_clk */ + + switch (state) { + case PM_SUSPEND_MEM: + mxc_cpu_lp_set(STOP_POWER_OFF); + break; + case PM_SUSPEND_STANDBY: + mxc_cpu_lp_set(STOP_POWER_ON); + break; + default: + return -EINVAL; + } + + cko1_disable(); + + /* Executing CP15 (Wait-for-Interrupt) Instruction */ + cpu_do_idle(); + + /* kernel resumes and enable peri_pll */ + __raw_writel(ccmr | MXC_CCM_CCMR_UPE, MXC_CCM_CCMR); + udelay(1000); + + cko1_enable(); + + mx35_resume_gpio(); + + local_fiq_enable(); + __raw_writel(MXC_INT_GPT, AVIC_INTENNUM); + + return 0; +} +/* Is there a charger connected? */ +static int charger_connected(void) +{ + int sense_0 = 0; + int ret = 0; /* Default: no charger */ + + pmic_read_reg(REG_INT_SENSE0, &sense_0, 0xffffff); + if (sense_0 & CHGDETS) + ret = 1; + + return ret; +} + +/* Read the SW2 HI bit */ +static int read_sw2hi_bit(void) +{ + int sw2hi = 0; + + pmic_read_reg(REG_SW_1, &sw2hi, 0xffffff); + if (sw2hi & 0x800000) + return 1; + else + return 0; +} + +void mx35_check_sw2hi_bit(void) +{ + /* SW HI bit switching does not occur on Atlas parts < 3.1 */ + if (!check_atlas_rev31()) + return; + + if (!read_sw2hi_bit()) + pmic_write_reg(REG_SW_1, 1 << SW2HI_LSH, 1 << SW2HI_LSH); +} +EXPORT_SYMBOL(mx35_check_sw2hi_bit); + +/*! + * Check the current status of the WAN. This is needed for the + * peri_pll_clk gating logic. peri_pll_clk is the parent of the + * usb_clk. + */ +static int check_wan_status(void) +{ + if ( (wan_get_power_status() == WAN_OFF) || + (wan_get_power_status() == WAN_INVALID)) { + return 1; + } + else + return 0; +} + +/* + * Called after processes are frozen, but before we shut down devices. + */ +static int mx35_suspend_prepare(suspend_state_t state) +{ +#if defined(CONFIG_CPU_FREQ) + struct cpufreq_freqs freqs; + int org_freq = clk_get_rate(cpu_clk); + + freqs.old = org_freq / 1000; + freqs.new = MAX_CPU_FREQUENCY / 1000; + freqs.cpu = 0; + freqs.flags = 0; + + cpufreq_suspended = 1; + if (clk_get_rate(cpu_clk) != MAX_CPU_FREQUENCY) { + set_cpu_freq(MAX_CPU_FREQUENCY); + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + } +#endif + + /* Disable doze mode */ + doze_disable(); + + if (check_atlas_rev31() && check_wan_status() && !mc13892_broken_mode_switch) { + pmic_write_reg(REG_SW_1, SW2HI_VOLTAGE << SW2NORMAL_LSH, SW2_NORMAL_MASK << SW2NORMAL_LSH); + pmic_write_reg(REG_SW_1, SW2LOW_VOLTAGE << SW2STANDBY_LSH, SW2_STANDBY_MASK << SW2STANDBY_LSH); + + /* Set the SW2HI bit to 0 for lower voltage values */ + pmic_write_reg(REG_SW_1, 0 << SW2HI_LSH, 1 << SW2HI_LSH); + } + + /* Turn off accessory */ + mx35_accessory_enable(0); + return 0; +} + +/* + * Called after devices are re-setup, but before processes are thawed. + */ +static void mx35_suspend_finish(void) +{ +#if defined(CONFIG_CPU_FREQ) + struct cpufreq_freqs freqs; +#endif + + /* Set the SW2HI bit only if it is 0 */ + if (check_atlas_rev31() && !read_sw2hi_bit()) + pmic_write_reg(REG_SW_1, 1 << SW2HI_LSH, 1 << SW2HI_LSH); + +#if defined(CONFIG_CPU_FREQ) + pmic_write_reg(REG_SW_1, MX35_CPU_MAX_VOLTAGE, SW2_VOLTAGE_MASK); + udelay(100); /* 100 us settling time */ + + freqs.old = clk_get_rate(cpu_clk) / 1000; + freqs.new = MAX_CPU_FREQUENCY / 1000; + freqs.cpu = 0; + freqs.flags = 0; + + if (clk_get_rate(cpu_clk) != MAX_CPU_FREQUENCY) { + set_cpu_freq(MAX_CPU_FREQUENCY); + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + } +#endif + if (get_pmic_revision() == 2) + pmic_write_reg(29, (0x8 << 8), (0xf << 8)); + else + pmic_write_reg(29, (0x5 << 8), (0xf << 8)); + + /* Re-enable doze mode */ + doze_enable(); + +#if defined(CONFIG_CPU_FREQ) + /* Restart scaling only if no charger connected */ + if (!charger_connected()) + cpufreq_suspended = 0; +#endif + +} + +static int mx35_pm_valid(suspend_state_t state) +{ + return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); +} + +struct platform_suspend_ops mx35_suspend_ops = { + .valid = mx35_pm_valid, + .begin = mx35_suspend_prepare, + .enter = mx35_suspend_enter, + .end = mx35_suspend_finish, +}; + +static int __init mx35_pm_init(void) +{ + int cpu_wp_nr; + + pr_info("Static Power Management for Freescale i.MX35\n"); + suspend_set_ops(&mx35_suspend_ops); + + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + + cpu_clk = clk_get(NULL, "cpu_clk"); + if (IS_ERR(cpu_clk)) { + printk(KERN_DEBUG "%s: failed to get cpu_clk\n", __func__); + return PTR_ERR(cpu_clk); + } + + return 0; +} + +late_initcall(mx35_pm_init); diff -urN linux-2.6.26/arch/arm/mach-mx35/sdma_script_code.h linux-2.6.26-lab126/arch/arm/mach-mx35/sdma_script_code.h --- linux-2.6.26/arch/arm/mach-mx35/sdma_script_code.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/sdma_script_code.h 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,254 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + +/*! + * @file sdma_script_code.h + * @brief This file contains functions of SDMA scripts code initialization + * + * The file was generated automatically. Based on sdma scripts library. + * + * @ingroup SDMA + */ +/******************************************************************************* + + SDMA RELEASE LABEL: "SS15_RINGO" + +*******************************************************************************/ + +#ifndef __SDMA_SCRIPT_CODE_H__ +#define __SDMA_SCRIPT_CODE_H__ + +/*! +* SDMA ROM scripts start addresses and sizes +*/ + +#define start_ADDR 0 +#define start_SIZE 22 + +#define core_ADDR 80 +#define core_SIZE 232 + +#define common_ADDR 312 +#define common_SIZE 330 + +#define ap_2_ap_ADDR 642 +#define ap_2_ap_SIZE 41 + +#define app_2_mcu_ADDR 683 +#define app_2_mcu_SIZE 64 + +#define mcu_2_app_ADDR 747 +#define mcu_2_app_SIZE 70 + +#define uart_2_mcu_ADDR 817 +#define uart_2_mcu_SIZE 75 + +#define shp_2_mcu_ADDR 892 +#define shp_2_mcu_SIZE 69 + +#define mcu_2_shp_ADDR 961 +#define mcu_2_shp_SIZE 72 + +#define per_2_shp_ADDR 1033 +#define per_2_shp_SIZE 78 + +#define shp_2_per_ADDR 1111 +#define shp_2_per_SIZE 72 + +#define uartsh_2_mcu_ADDR 1183 +#define uartsh_2_mcu_SIZE 69 + +#define mcu_2_ata_ADDR 1252 +#define mcu_2_ata_SIZE 81 + +#define ata_2_mcu_ADDR 1333 +#define ata_2_mcu_SIZE 96 + +#define loop_DMAs_routines_ADDR 1429 +#define loop_DMAs_routines_SIZE 227 + +#define test_ADDR 1656 +#define test_SIZE 63 + +#define signature_ADDR 1023 +#define signature_SIZE 1 + +/*! +* SDMA RAM scripts start addresses and sizes +*/ + +#define app_2_per_ADDR 6144 +#define app_2_per_SIZE 66 + +#define asrc__mcu_ADDR 6210 +#define asrc__mcu_SIZE 114 + +#define ext_mem__ipu_ram_ADDR 6324 +#define ext_mem__ipu_ram_SIZE 123 + +#define mcu_2_spdif_ADDR 6447 +#define mcu_2_spdif_SIZE 103 + +#define p_2_p_ADDR 6550 +#define p_2_p_SIZE 254 + +#define per_2_app_ADDR 6804 +#define per_2_app_SIZE 74 + +#define spdif_2_mcu_ADDR 6878 +#define spdif_2_mcu_SIZE 47 + +#define uart_2_per_ADDR 6925 +#define uart_2_per_SIZE 73 + +#define uartsh_2_per_ADDR 6998 +#define uartsh_2_per_SIZE 67 + +/*! +* SDMA RAM image start address and size +*/ + +#define RAM_CODE_START_ADDR 6144 +#define RAM_CODE_SIZE 921 + +/*! +* Buffer that holds the SDMA RAM image +*/ +__attribute__ ((__aligned__(4))) +#ifndef CONFIG_XIP_KERNEL +const +#endif +static const short sdma_code[] = { + 0xc1e3, 0x57db, 0x52fb, 0x6ac3, 0x52f3, 0x6ad7, 0x008f, 0x00d5, + 0x7d01, 0x008d, 0x05a0, 0x0478, 0x7d03, 0x0479, 0x7d1c, 0x7c21, + 0x0479, 0x7c14, 0x6ddd, 0x56ee, 0x62c8, 0x7e28, 0x0660, 0x7d02, + 0x0210, 0x0212, 0x6ac8, 0x7f22, 0x0212, 0x6ac8, 0x7f1f, 0x0212, + 0x6ac8, 0x7f1c, 0x2003, 0x4800, 0x7cef, 0x9836, 0x6ddd, 0x7802, + 0x62c8, 0x6ac8, 0x9835, 0x6dde, 0x0015, 0x7802, 0x62c8, 0x6ac8, + 0x9835, 0x0015, 0x0015, 0x7801, 0x62d8, 0x7c08, 0x6ddf, 0x7f06, + 0x0000, 0x4d00, 0x7d05, 0xc1fa, 0x57db, 0x9806, 0xc273, 0x0454, + 0xc20a, 0x9801, 0xc1d9, 0xc1e3, 0x56f3, 0x57db, 0x047a, 0x7d07, + 0x072f, 0x076e, 0x7d02, 0x6ec7, 0x9855, 0x6ed7, 0x9855, 0x074f, + 0x076e, 0x7d02, 0x6e01, 0x9855, 0x6e05, 0x5ce3, 0x048f, 0x0410, + 0x3c0f, 0x5c93, 0x0eff, 0x06bf, 0x06d5, 0x7d01, 0x068d, 0x05a6, + 0x5deb, 0x55fb, 0x008e, 0x0768, 0x7d02, 0x0769, 0x7c04, 0x06d4, + 0x7d01, 0x008c, 0x04a0, 0x06a0, 0x076f, 0x7d0c, 0x076e, 0x7d05, + 0x7802, 0x62c8, 0x5a05, 0x7c2b, 0x9887, 0x7802, 0x5205, 0x6ac8, + 0x7c26, 0x9887, 0x076e, 0x7d05, 0x7802, 0x620b, 0x5a05, 0x7c21, + 0x9887, 0x7802, 0x5205, 0x6a0b, 0x7c1c, 0x6a28, 0x7f1a, 0x0768, + 0x7d02, 0x0769, 0x7c0a, 0x4c00, 0x7c08, 0x0768, 0x7d03, 0x5a05, + 0x7f11, 0x9894, 0x5205, 0x7e0e, 0x5493, 0x4e00, 0x7ccb, 0x0000, + 0x54e3, 0x55eb, 0x4d00, 0x7d0a, 0xc1fa, 0x57db, 0x9856, 0x68cc, + 0x98a2, 0x680c, 0x009e, 0x0007, 0x54e3, 0xd8a8, 0xc20a, 0x9844, + 0x55eb, 0x009d, 0x058c, 0x0aff, 0x0211, 0x1aff, 0x05ba, 0x05a0, + 0x04b2, 0x04ad, 0x0454, 0x0006, 0x0e70, 0x0611, 0x5616, 0xc13c, + 0x7d2a, 0x5ade, 0x008e, 0xc14e, 0x7c26, 0x5be0, 0x5ef0, 0x5ce8, + 0x0688, 0x08ff, 0x0011, 0x28ff, 0x00bc, 0x53f6, 0x05df, 0x7d0b, + 0x6dc5, 0x03df, 0x7d03, 0x6bd5, 0xd903, 0x98df, 0x6b05, 0xc5f5, + 0x7e27, 0x7f29, 0x98df, 0x6d01, 0x03df, 0x7d05, 0x6bd5, 0xc61f, + 0x7e18, 0x7f1a, 0x98df, 0x6b05, 0xc595, 0x7e07, 0x7f06, 0x52de, + 0x53e6, 0xc159, 0x7dd7, 0x0200, 0x98b7, 0x0007, 0x6004, 0x680c, + 0x53f6, 0x028e, 0x00a3, 0xc256, 0x048b, 0x0498, 0x0454, 0x068a, + 0x98df, 0x0207, 0x680c, 0x6ddf, 0x0107, 0x68ff, 0x60d0, 0x98e8, + 0x0207, 0x68ff, 0x6d28, 0x0107, 0x6004, 0x680c, 0x98e8, 0x0007, + 0x68ff, 0x60d0, 0x98e8, 0x0288, 0x03a5, 0x3b03, 0x3d03, 0x4d00, + 0x7d0a, 0x0804, 0x00a5, 0x00da, 0x7d1a, 0x02a0, 0x7b01, 0x65d8, + 0x7eee, 0x65ff, 0x7eec, 0x0804, 0x02d0, 0x7d11, 0x4b00, 0x7c0f, + 0x008a, 0x3003, 0x6dcf, 0x6bdf, 0x0015, 0x0015, 0x7b02, 0x65d8, + 0x0000, 0x7edd, 0x63ff, 0x7edb, 0x3a03, 0x6dcd, 0x6bdd, 0x008a, + 0x7b02, 0x65d8, 0x0000, 0x7ed3, 0x65ff, 0x7ed1, 0x0006, 0xc1d9, + 0xc1e3, 0x57db, 0x52f3, 0x047a, 0x7d06, 0x0479, 0x7c02, 0x6ac6, + 0x993c, 0x6ac7, 0x993c, 0x6a01, 0x008f, 0x00d5, 0x7d01, 0x008d, + 0x05a0, 0x5deb, 0x56fb, 0x0478, 0x7d4e, 0x0479, 0x7c1f, 0x0015, + 0x0388, 0x047a, 0x7d03, 0x62c8, 0x7e39, 0x9950, 0x620a, 0x7e38, + 0x0808, 0x7801, 0x0217, 0x5a06, 0x7f34, 0x2301, 0x047a, 0x7d03, + 0x62c8, 0x7e2c, 0x995d, 0x620a, 0x7e2b, 0x0808, 0x7801, 0x0217, + 0x5a26, 0x7f27, 0x2301, 0x4b00, 0x7ce4, 0x997c, 0x0015, 0x0015, + 0x0015, 0x047a, 0x7d09, 0x7806, 0x0b00, 0x62c8, 0x5a06, 0x0b01, + 0x62c8, 0x5a26, 0x7c13, 0x997c, 0x7806, 0x0b00, 0x620b, 0x5a06, + 0x0b01, 0x620b, 0x5a26, 0x7c0c, 0x0b70, 0x0311, 0x5313, 0x0000, + 0x55eb, 0x4d00, 0x7d11, 0xc1fa, 0x57db, 0x993c, 0x68cc, 0x9989, + 0x680c, 0x0007, 0x0479, 0x7c02, 0x008b, 0x9990, 0x0017, 0x00a3, + 0x0b70, 0x0311, 0x5313, 0xc213, 0xc20a, 0x9931, 0x0b70, 0x0311, + 0x5313, 0x076c, 0x7c01, 0xc1d9, 0x5efb, 0x068a, 0x076b, 0x7c01, + 0xc1d9, 0x5ef3, 0x59db, 0x58d3, 0x018f, 0x0110, 0x390f, 0x008b, + 0xc13c, 0x7d2b, 0x5ac0, 0x5bc8, 0xc14e, 0x7c27, 0x0388, 0x0689, + 0x5ce3, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x073e, 0x4d00, 0x7d18, + 0x0870, 0x0011, 0x077e, 0x7d09, 0x077d, 0x7d02, 0x5228, 0x99c1, + 0x52f8, 0x54db, 0x02bc, 0x02cc, 0x7c09, 0x077c, 0x7d02, 0x5228, + 0x99ca, 0x52f8, 0x54d3, 0x02bc, 0x02cc, 0x7d09, 0x0400, 0x99b8, + 0x008b, 0x52c0, 0x53c8, 0xc159, 0x7dd6, 0x0200, 0x99a8, 0x08ff, + 0x00bf, 0x077f, 0x7d15, 0x0488, 0x00d5, 0x7d01, 0x008d, 0x05a0, + 0x5deb, 0x028f, 0x0212, 0x0212, 0x3aff, 0x05da, 0x7c02, 0x073e, + 0x99f3, 0x02a4, 0x02dd, 0x7d02, 0x073e, 0x99f3, 0x075e, 0x99f3, + 0x55eb, 0x0598, 0x5deb, 0x52f3, 0x54fb, 0x076a, 0x7d26, 0x076c, + 0x7d01, 0x9a30, 0x076b, 0x7c57, 0x0769, 0x7d04, 0x0768, 0x7d02, + 0x0e01, 0x9a0a, 0x5893, 0x00d6, 0x7d01, 0x008e, 0x5593, 0x05a0, + 0x5d93, 0x06a0, 0x7802, 0x5502, 0x5d04, 0x7c1d, 0x4e00, 0x7c08, + 0x0769, 0x7d03, 0x5502, 0x7e17, 0x9a17, 0x5d04, 0x7f14, 0x0689, + 0x5093, 0x4800, 0x7d01, 0x9a02, 0x9a7b, 0x0015, 0x7806, 0x5502, + 0x5d04, 0x074f, 0x5502, 0x5d24, 0x072f, 0x7c01, 0x9a7b, 0x0017, + 0x076f, 0x7c01, 0x2001, 0x5593, 0x009d, 0x0007, 0xda82, 0x99d0, + 0x6cd3, 0x0769, 0x7d04, 0x0768, 0x7d02, 0x0e01, 0x9a3f, 0x5893, + 0x00d6, 0x7d01, 0x008e, 0x5593, 0x05a0, 0x5d93, 0x06a0, 0x7802, + 0x5502, 0x6dc8, 0x7c0f, 0x4e00, 0x7c08, 0x0769, 0x7d03, 0x5502, + 0x7e09, 0x9a4c, 0x6dc8, 0x7f06, 0x0689, 0x5093, 0x4800, 0x7d01, + 0x9a37, 0x9a7b, 0x9a75, 0x6ac3, 0x0769, 0x7d04, 0x0768, 0x7d02, + 0x0e01, 0x9a62, 0x5893, 0x00d6, 0x7d01, 0x008e, 0x5593, 0x05a0, + 0x5d93, 0x06a0, 0x7802, 0x65c8, 0x5d04, 0x7c0f, 0x4e00, 0x7c08, + 0x0769, 0x7d03, 0x65c8, 0x7e09, 0x9a6f, 0x5d04, 0x7f06, 0x0689, + 0x5093, 0x4800, 0x7d01, 0x9a5a, 0x9a7b, 0x5593, 0x009d, 0x0007, + 0x6cff, 0xda82, 0x99d0, 0x0000, 0x54e3, 0x55eb, 0x4d00, 0x7c01, + 0x99d0, 0x99b8, 0x54e3, 0x55eb, 0x0aff, 0x0211, 0x1aff, 0x077f, + 0x7c02, 0x05a0, 0x9a8f, 0x009d, 0x058c, 0x05ba, 0x05a0, 0x0210, + 0x04ba, 0x04ad, 0x0454, 0x0006, 0xc1e3, 0x57db, 0x52f3, 0x6ac5, + 0x52fb, 0x6ad3, 0x008f, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5deb, + 0x0478, 0x7d03, 0x0479, 0x7d20, 0x7c25, 0x0479, 0x7c19, 0x59e3, + 0x56ee, 0x61c8, 0x7e2e, 0x62c8, 0x7e2c, 0x65c8, 0x7e2a, 0x0660, + 0x7d03, 0x0112, 0x0112, 0x9ab6, 0x0512, 0x0512, 0x0211, 0x02a9, + 0x02ad, 0x6ac8, 0x7f1e, 0x2003, 0x4800, 0x7ceb, 0x51e3, 0x9ad0, + 0x7802, 0x62c8, 0x6ac8, 0x9acf, 0x6dce, 0x0015, 0x7802, 0x62c8, + 0x6ac8, 0x9acf, 0x6dcf, 0x0015, 0x0015, 0x7801, 0x62d8, 0x7c09, + 0x6ddf, 0x7f07, 0x0000, 0x55eb, 0x4d00, 0x7d06, 0xc1fa, 0x57db, + 0x9a9a, 0x0007, 0x68ff, 0xc213, 0xc20a, 0x9a95, 0xc1d9, 0xc1e3, + 0x57db, 0x52f3, 0x047a, 0x7d02, 0x6ad7, 0x9ae7, 0x6a05, 0x008f, + 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x56fb, 0x0015, 0x0015, 0x0015, + 0x047a, 0x7d07, 0x7804, 0x5206, 0x6ac8, 0x5226, 0x6ac8, 0x7c0f, + 0x9b01, 0x7804, 0x5206, 0x6a0b, 0x5226, 0x6a0b, 0x7c0a, 0x6a28, + 0x7f08, 0x0000, 0x4d00, 0x7d07, 0xc1fa, 0x57db, 0x9ae7, 0xc273, + 0x9b0a, 0xc277, 0x0454, 0xc20a, 0x9ae0, 0xc1e3, 0x57db, 0x52f3, + 0x6ad5, 0x56fb, 0x028e, 0x1a94, 0x6ac3, 0x62c8, 0x0269, 0x7d1e, + 0x1e94, 0x6ee3, 0x62d0, 0x5aeb, 0x62c8, 0x0248, 0x6ed3, 0x6ac8, + 0x2694, 0x52eb, 0x6ad5, 0x6ee3, 0x62c8, 0x026e, 0x7d27, 0x6ac8, + 0x7f23, 0x2501, 0x4d00, 0x7d26, 0x028e, 0x1a98, 0x6ac3, 0x62c8, + 0x6ec3, 0x0260, 0x7df1, 0x62d0, 0xc27a, 0x9b52, 0x6ee3, 0x008f, + 0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x62c8, 0x026e, 0x7d0e, + 0x6ac8, 0x7f0a, 0x2001, 0x7cf9, 0x6add, 0x7f06, 0x0000, 0x4d00, + 0x7d09, 0xc1fa, 0x57db, 0x9b11, 0x0007, 0x6aff, 0x62d0, 0xc27a, + 0x0458, 0x0454, 0x6add, 0x7ff8, 0xc20a, 0x9b0e, 0xc1d9, 0xc1e3, + 0x57db, 0x52f3, 0x6ad5, 0x56fb, 0x028e, 0x1a94, 0x5202, 0x0269, + 0x7d17, 0x1e94, 0x5206, 0x0248, 0x5a06, 0x2694, 0x5206, 0x026e, + 0x7d26, 0x6ac8, 0x7f22, 0x2501, 0x4d00, 0x7d27, 0x028e, 0x1a98, + 0x5202, 0x0260, 0x7df3, 0x6add, 0x7f18, 0x62d0, 0xc27a, 0x9b95, + 0x008f, 0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5206, 0x026e, + 0x7d0e, 0x6ac8, 0x7f0a, 0x2001, 0x7cf9, 0x6add, 0x7f06, 0x0000, + 0x4d00, 0x7d0b, 0xc1fa, 0x57db, 0x9b5b, 0x0007, 0x6aff, 0x6add, + 0x7ffc, 0x62d0, 0xc27a, 0x0458, 0x0454, 0x6add, 0x7ff6, 0xc20a, + 0x9b58 +}; +#endif diff -urN linux-2.6.26/arch/arm/mach-mx35/sdma_script_code_v2.h linux-2.6.26-lab126/arch/arm/mach-mx35/sdma_script_code_v2.h --- linux-2.6.26/arch/arm/mach-mx35/sdma_script_code_v2.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/sdma_script_code_v2.h 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,234 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + +/*! + * @file sdma_script_code.h + * @brief This file contains functions of SDMA scripts code initialization + * + * The file was generated automatically. Based on sdma scripts library. + * + * @ingroup SDMA + */ +/******************************************************************************* + + SDMA RELEASE LABEL: "SDMA_RINGO.03.00.00" + +*******************************************************************************/ + +#ifndef SDMA_SCRIPT_CODE_V2_H +#define SDMA_SCRIPT_CODE_V2_H + +/*! +* SDMA ROM scripts start addresses and sizes +*/ + +#define start_ADDR_V2 0 +#define start_SIZE_V2 24 + +#define core_ADDR_V2 80 +#define core_SIZE_V2 233 + +#define common_ADDR_V2 313 +#define common_SIZE_V2 416 + +#define ap_2_ap_ADDR_V2 729 +#define ap_2_ap_SIZE_V2 41 + +#define app_2_mcu_ADDR_V2 770 +#define app_2_mcu_SIZE_V2 64 + +#define mcu_2_app_ADDR_V2 834 +#define mcu_2_app_SIZE_V2 70 + +#define uart_2_mcu_ADDR_V2 904 +#define uart_2_mcu_SIZE_V2 75 + +#define shp_2_mcu_ADDR_V2 979 +#define shp_2_mcu_SIZE_V2 69 + +#define mcu_2_shp_ADDR_V2 1048 +#define mcu_2_shp_SIZE_V2 72 + +#define per_2_shp_ADDR_V2 1120 +#define per_2_shp_SIZE_V2 78 + +#define shp_2_per_ADDR_V2 1198 +#define shp_2_per_SIZE_V2 72 + +#define uartsh_2_mcu_ADDR_V2 1270 +#define uartsh_2_mcu_SIZE_V2 69 + +#define mcu_2_ata_ADDR_V2 1339 +#define mcu_2_ata_SIZE_V2 90 + +#define ata_2_mcu_ADDR_V2 1429 +#define ata_2_mcu_SIZE_V2 102 + +#define app_2_per_ADDR_V2 1531 +#define app_2_per_SIZE_V2 66 + +#define per_2_app_ADDR_V2 1597 +#define per_2_app_SIZE_V2 74 + +#define loop_DMAs_routines_ADDR_V2 1671 +#define loop_DMAs_routines_SIZE_V2 240 + +#define test_ADDR_V2 1911 +#define test_SIZE_V2 63 + +#define signature_ADDR_V2 1022 +#define signature_SIZE_V2 1 + +/*! +* SDMA RAM scripts start addresses and sizes +*/ + +#define asrc__mcu_ADDR_V2 6144 +#define asrc__mcu_SIZE_V2 116 + +#define ext_mem__ipu_ram_ADDR_V2 6260 +#define ext_mem__ipu_ram_SIZE_V2 123 + +#define mcu_2_spdif_ADDR_V2 6383 +#define mcu_2_spdif_SIZE_V2 103 + +#define p_2_p_ADDR_V2 6486 +#define p_2_p_SIZE_V2 260 + +#define spdif_2_mcu_ADDR_V2 6746 +#define spdif_2_mcu_SIZE_V2 47 + +#define uart_2_per_ADDR_V2 6793 +#define uart_2_per_SIZE_V2 73 + +#define uartsh_2_per_ADDR_V2 6866 +#define uartsh_2_per_SIZE_V2 67 + +/*! +* SDMA RAM image start address and size +*/ + +#define RAM_CODE_START_ADDR_V2 6144 +#define RAM_CODE_SIZE_V2 789 + +/*! +* Buffer that holds the SDMA RAM image +*/ + +static const short sdma_code_v2[] = { + 0xc230, 0xc23a, 0x56f3, 0x57db, 0x047a, 0x7d07, 0x072f, 0x076e, + 0x7d02, 0x6ec7, 0x9813, 0x6ed7, 0x9813, 0x074f, 0x076e, 0x7d02, + 0x6e01, 0x9813, 0x6e05, 0x5ce3, 0x048f, 0x0410, 0x3c0f, 0x5c93, + 0x0e03, 0x0611, 0x1eff, 0x06bf, 0x06d5, 0x7d01, 0x068d, 0x05a6, + 0x5deb, 0x55fb, 0x008e, 0x076a, 0x7d02, 0x076b, 0x7c04, 0x06d4, + 0x7d01, 0x008c, 0x04a0, 0x06a0, 0x076f, 0x7d0c, 0x076e, 0x7d05, + 0x7802, 0x62c8, 0x5a05, 0x7c2b, 0x9847, 0x7802, 0x5205, 0x6ac8, + 0x7c26, 0x9847, 0x076e, 0x7d05, 0x7802, 0x620b, 0x5a05, 0x7c21, + 0x9847, 0x7802, 0x5205, 0x6a0b, 0x7c1c, 0x6a28, 0x7f1a, 0x076a, + 0x7d02, 0x076b, 0x7c0a, 0x4c00, 0x7c08, 0x076a, 0x7d03, 0x5a05, + 0x7f11, 0x9854, 0x5205, 0x7e0e, 0x5493, 0x4e00, 0x7ccb, 0x0000, + 0x54e3, 0x55eb, 0x4d00, 0x7d0a, 0xc251, 0x57db, 0x9814, 0x68cc, + 0x9862, 0x680c, 0x009e, 0x0007, 0x54e3, 0xd868, 0xc261, 0x9802, + 0x55eb, 0x009d, 0x058c, 0x0aff, 0x0211, 0x1aff, 0x05ba, 0x05a0, + 0x04b2, 0x04ad, 0x0454, 0x0006, 0x0e70, 0x0611, 0x5616, 0xc18a, + 0x7d2a, 0x5ade, 0x008e, 0xc19c, 0x7c26, 0x5be0, 0x5ef0, 0x5ce8, + 0x0688, 0x08ff, 0x0011, 0x28ff, 0x00bc, 0x53f6, 0x05df, 0x7d0b, + 0x6dc5, 0x03df, 0x7d03, 0x6bd5, 0xd8c3, 0x989f, 0x6b05, 0xc6e7, + 0x7e27, 0x7f29, 0x989f, 0x6d01, 0x03df, 0x7d05, 0x6bd5, 0xc711, + 0x7e18, 0x7f1a, 0x989f, 0x6b05, 0xc687, 0x7e07, 0x7f06, 0x52de, + 0x53e6, 0xc1a8, 0x7dd7, 0x0200, 0x9877, 0x0007, 0x6004, 0x680c, + 0x53f6, 0x028e, 0x00a3, 0xc2ad, 0x048b, 0x0498, 0x0454, 0x068a, + 0x989f, 0x0207, 0x680c, 0x6ddf, 0x0107, 0x68ff, 0x60d0, 0x98a8, + 0x0207, 0x68ff, 0x6d28, 0x0107, 0x6004, 0x680c, 0x98a8, 0x0007, + 0x68ff, 0x60d0, 0x98a8, 0x0288, 0x03a5, 0x3b03, 0x3d03, 0x4d00, + 0x7d0a, 0x0804, 0x00a5, 0x00da, 0x7d1a, 0x02a0, 0x7b01, 0x65d8, + 0x7eee, 0x65ff, 0x7eec, 0x0804, 0x02d0, 0x7d11, 0x4b00, 0x7c0f, + 0x008a, 0x3003, 0x6dcf, 0x6bdf, 0x0015, 0x0015, 0x7b02, 0x65d8, + 0x0000, 0x7edd, 0x63ff, 0x7edb, 0x3a03, 0x6dcd, 0x6bdd, 0x008a, + 0x7b02, 0x65d8, 0x0000, 0x7ed3, 0x65ff, 0x7ed1, 0x0006, 0xc230, + 0xc23a, 0x57db, 0x52f3, 0x047a, 0x7d06, 0x0479, 0x7c02, 0x6ac6, + 0x98fc, 0x6ac7, 0x98fc, 0x6a01, 0x008f, 0x00d5, 0x7d01, 0x008d, + 0x05a0, 0x5deb, 0x56fb, 0x0478, 0x7d4e, 0x0479, 0x7c1f, 0x0015, + 0x0388, 0x047a, 0x7d03, 0x62c8, 0x7e39, 0x9910, 0x620a, 0x7e38, + 0x0808, 0x7801, 0x0217, 0x5a06, 0x7f34, 0x2301, 0x047a, 0x7d03, + 0x62c8, 0x7e2c, 0x991d, 0x620a, 0x7e2b, 0x0808, 0x7801, 0x0217, + 0x5a26, 0x7f27, 0x2301, 0x4b00, 0x7ce4, 0x993c, 0x0015, 0x0015, + 0x0015, 0x047a, 0x7d09, 0x7806, 0x0b00, 0x62c8, 0x5a06, 0x0b01, + 0x62c8, 0x5a26, 0x7c13, 0x993c, 0x7806, 0x0b00, 0x620b, 0x5a06, + 0x0b01, 0x620b, 0x5a26, 0x7c0c, 0x0b70, 0x0311, 0x5313, 0x0000, + 0x55eb, 0x4d00, 0x7d11, 0xc251, 0x57db, 0x98fc, 0x68cc, 0x9949, + 0x680c, 0x0007, 0x0479, 0x7c02, 0x008b, 0x9950, 0x0017, 0x00a3, + 0x0b70, 0x0311, 0x5313, 0xc26a, 0xc261, 0x98f1, 0x0b70, 0x0311, + 0x5313, 0x076c, 0x7c01, 0xc230, 0x5efb, 0x068a, 0x076b, 0x7c01, + 0xc230, 0x5ef3, 0x59db, 0x58d3, 0x018f, 0x0110, 0x390f, 0x008b, + 0xc18a, 0x7d2b, 0x5ac0, 0x5bc8, 0xc19c, 0x7c27, 0x0388, 0x0689, + 0x5ce3, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x073e, 0x4d00, 0x7d18, + 0x0870, 0x0011, 0x077e, 0x7d09, 0x077d, 0x7d02, 0x5228, 0x9981, + 0x52f8, 0x54db, 0x02bc, 0x02cc, 0x7c09, 0x077c, 0x7d02, 0x5228, + 0x998a, 0x52f8, 0x54d3, 0x02bc, 0x02cc, 0x7d09, 0x0400, 0x9978, + 0x008b, 0x52c0, 0x53c8, 0xc1a8, 0x7dd6, 0x0200, 0x9968, 0x08ff, + 0x00bf, 0x077f, 0x7d1b, 0x0488, 0x00d5, 0x7d01, 0x008d, 0x05a0, + 0x5deb, 0x028f, 0x32ff, 0x0210, 0x32ff, 0x0210, 0x0212, 0x0217, + 0x0217, 0x32ff, 0x0212, 0x05da, 0x7c02, 0x073e, 0x99b9, 0x02a4, + 0x02dd, 0x7d02, 0x073e, 0x99b9, 0x075e, 0x99b9, 0x55eb, 0x0598, + 0x5deb, 0x52f3, 0x54fb, 0x076a, 0x7d26, 0x076c, 0x7d01, 0x99f6, + 0x076b, 0x7c57, 0x0769, 0x7d04, 0x0768, 0x7d02, 0x0e01, 0x99d0, + 0x5893, 0x00d6, 0x7d01, 0x008e, 0x5593, 0x05a0, 0x5d93, 0x06a0, + 0x7802, 0x5502, 0x5d04, 0x7c1d, 0x4e00, 0x7c08, 0x0769, 0x7d03, + 0x5502, 0x7e17, 0x99dd, 0x5d04, 0x7f14, 0x0689, 0x5093, 0x4800, + 0x7d01, 0x99c8, 0x9a41, 0x0015, 0x7806, 0x5502, 0x5d04, 0x074d, + 0x5502, 0x5d24, 0x072d, 0x7c01, 0x9a41, 0x0017, 0x076d, 0x7c01, + 0x2001, 0x5593, 0x009d, 0x0007, 0xda48, 0x9990, 0x6cd3, 0x0769, + 0x7d04, 0x0768, 0x7d02, 0x0e01, 0x9a05, 0x5893, 0x00d6, 0x7d01, + 0x008e, 0x5593, 0x05a0, 0x5d93, 0x06a0, 0x7802, 0x5502, 0x6dc8, + 0x7c0f, 0x4e00, 0x7c08, 0x0769, 0x7d03, 0x5502, 0x7e09, 0x9a12, + 0x6dc8, 0x7f06, 0x0689, 0x5093, 0x4800, 0x7d01, 0x99fd, 0x9a41, + 0x9a3b, 0x6ac3, 0x0769, 0x7d04, 0x0768, 0x7d02, 0x0e01, 0x9a28, + 0x5893, 0x00d6, 0x7d01, 0x008e, 0x5593, 0x05a0, 0x5d93, 0x06a0, + 0x7802, 0x65c8, 0x5d04, 0x7c0f, 0x4e00, 0x7c08, 0x0769, 0x7d03, + 0x65c8, 0x7e09, 0x9a35, 0x5d04, 0x7f06, 0x0689, 0x5093, 0x4800, + 0x7d01, 0x9a20, 0x9a41, 0x5593, 0x009d, 0x0007, 0x6cff, 0xda48, + 0x9990, 0x0000, 0x54e3, 0x55eb, 0x4d00, 0x7c01, 0x9990, 0x9978, + 0x54e3, 0x55eb, 0x0aff, 0x0211, 0x1aff, 0x077f, 0x7c02, 0x05a0, + 0x9a55, 0x009d, 0x058c, 0x05ba, 0x05a0, 0x0210, 0x04ba, 0x04ad, + 0x0454, 0x0006, 0xc230, 0xc23a, 0x57db, 0x52f3, 0x047a, 0x7d02, + 0x6ad7, 0x9a63, 0x6a05, 0x008f, 0x00d5, 0x7d01, 0x008d, 0x05a0, + 0x56fb, 0x0015, 0x0015, 0x0015, 0x047a, 0x7d07, 0x7804, 0x5206, + 0x6ac8, 0x5226, 0x6ac8, 0x7c0f, 0x9a7d, 0x7804, 0x5206, 0x6a0b, + 0x5226, 0x6a0b, 0x7c0a, 0x6a28, 0x7f08, 0x0000, 0x4d00, 0x7d07, + 0xc251, 0x57db, 0x9a63, 0xc2ca, 0x9a86, 0xc2ce, 0x0454, 0xc261, + 0x9a5c, 0xc23a, 0x57db, 0x52f3, 0x6ad5, 0x56fb, 0x028e, 0x1a94, + 0x6ac3, 0x62c8, 0x0269, 0x7d1e, 0x1e94, 0x6ee3, 0x62d0, 0x5aeb, + 0x62c8, 0x0248, 0x6ed3, 0x6ac8, 0x2694, 0x52eb, 0x6ad5, 0x6ee3, + 0x62c8, 0x026e, 0x7d27, 0x6ac8, 0x7f23, 0x2501, 0x4d00, 0x7d26, + 0x028e, 0x1a98, 0x6ac3, 0x62c8, 0x6ec3, 0x0260, 0x7df1, 0x62d0, + 0xc2d1, 0x9ace, 0x6ee3, 0x008f, 0x2001, 0x00d5, 0x7d01, 0x008d, + 0x05a0, 0x62c8, 0x026e, 0x7d0e, 0x6ac8, 0x7f0a, 0x2001, 0x7cf9, + 0x6add, 0x7f06, 0x0000, 0x4d00, 0x7d09, 0xc251, 0x57db, 0x9a8d, + 0x0007, 0x6aff, 0x62d0, 0xc2d1, 0x0458, 0x0454, 0x6add, 0x7ff8, + 0xc261, 0x9a8a, 0xc230, 0xc23a, 0x57db, 0x52f3, 0x6ad5, 0x56fb, + 0x028e, 0x1a94, 0x5202, 0x0269, 0x7d17, 0x1e94, 0x5206, 0x0248, + 0x5a06, 0x2694, 0x5206, 0x026e, 0x7d26, 0x6ac8, 0x7f22, 0x2501, + 0x4d00, 0x7d27, 0x028e, 0x1a98, 0x5202, 0x0260, 0x7df3, 0x6add, + 0x7f18, 0x62d0, 0xc2d1, 0x9b11, 0x008f, 0x2001, 0x00d5, 0x7d01, + 0x008d, 0x05a0, 0x5206, 0x026e, 0x7d0e, 0x6ac8, 0x7f0a, 0x2001, + 0x7cf9, 0x6add, 0x7f06, 0x0000, 0x4d00, 0x7d0b, 0xc251, 0x57db, + 0x9ad7, 0x0007, 0x6aff, 0x6add, 0x7ffc, 0x62d0, 0xc2d1, 0x0458, + 0x0454, 0x6add, 0x7ff6, 0xc261, 0x9ad4 +}; +#endif diff -urN linux-2.6.26/arch/arm/mach-mx35/serial.c linux-2.6.26-lab126/arch/arm/mach-mx35/serial.c --- linux-2.6.26/arch/arm/mach-mx35/serial.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/serial.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,180 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @file mach-mx35/serial.c + * + * @brief This file contains the UART initiliazation. + * + * @ingroup MSL_MX35 + */ +#include +#include +#include +#include +#include +#include +#include "serial.h" +#include "board-mx35evb.h" +#include "board-mx35_3stack.h" + +#if defined(CONFIG_SERIAL_MXC) || defined(CONFIG_SERIAL_MXC_MODULE) + +/*! + * This is an array where each element holds information about a UART port, + * like base address of the UART, interrupt numbers etc. This structure is + * passed to the serial_core.c file. Based on which UART is used, the core file + * passes back the appropriate port structure as an argument to the control + * functions. + */ +static uart_mxc_port mxc_ports[] = { + [0] = { + .port = { + .membase = (void *)IO_ADDRESS(UART1_BASE_ADDR), + .mapbase = UART1_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART1_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 0, + }, + .ints_muxed = UART1_MUX_INTS, + .irqs = {UART1_INT2, UART1_INT3}, + .mode = UART1_MODE, + .ir_mode = UART1_IR, + .enabled = UART1_ENABLED, + .hardware_flow = UART1_HW_FLOW, + .cts_threshold = UART1_UCR4_CTSTL, + .dma_enabled = UART1_DMA_ENABLE, + .dma_rxbuf_size = UART1_DMA_RXBUFSIZE, + .rx_threshold = UART1_UFCR_RXTL, + .tx_threshold = UART1_UFCR_TXTL, + .shared = UART1_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART1_TX, + .dma_rx_id = MXC_DMA_UART1_RX, + .rxd_mux = MXC_UART_RXDMUX, + .ir_tx_inv = MXC_IRDA_TX_INV, + .ir_rx_inv = MXC_IRDA_RX_INV, + }, + [1] = { + .port = { + .membase = (void *)IO_ADDRESS(UART2_BASE_ADDR), + .mapbase = UART2_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART2_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 1, + }, + .ints_muxed = UART2_MUX_INTS, + .irqs = {UART2_INT2, UART2_INT3}, + .mode = UART2_MODE, + .ir_mode = UART2_IR, + .enabled = UART2_ENABLED, + .hardware_flow = UART2_HW_FLOW, + .cts_threshold = UART2_UCR4_CTSTL, + .dma_enabled = UART2_DMA_ENABLE, + .dma_rxbuf_size = UART2_DMA_RXBUFSIZE, + .rx_threshold = UART2_UFCR_RXTL, + .tx_threshold = UART2_UFCR_TXTL, + .shared = UART2_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART2_TX, + .dma_rx_id = MXC_DMA_UART2_RX, + .rxd_mux = MXC_UART_IR_RXDMUX, + .ir_tx_inv = MXC_IRDA_TX_INV, + .ir_rx_inv = MXC_IRDA_RX_INV, + }, +#if UART3_ENABLED == 1 + [2] = { + .port = { + .membase = (void *)IO_ADDRESS(UART3_BASE_ADDR), + .mapbase = UART3_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART3_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 2, + }, + .ints_muxed = UART3_MUX_INTS, + .irqs = {UART3_INT2, UART3_INT3}, + .mode = UART3_MODE, + .ir_mode = UART3_IR, + .enabled = UART3_ENABLED, + .hardware_flow = UART3_HW_FLOW, + .cts_threshold = UART3_UCR4_CTSTL, + .dma_enabled = UART3_DMA_ENABLE, + .dma_rxbuf_size = UART3_DMA_RXBUFSIZE, + .rx_threshold = UART3_UFCR_RXTL, + .tx_threshold = UART3_UFCR_TXTL, + .shared = UART3_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART3_TX, + .dma_rx_id = MXC_DMA_UART3_RX, + .rxd_mux = MXC_UART_RXDMUX, + .ir_tx_inv = MXC_IRDA_TX_INV, + .ir_rx_inv = MXC_IRDA_RX_INV, + }, +#endif +}; + +static struct platform_device mxc_uart_device1 = { + .name = "mxcintuart", + .id = 0, + .dev = { + .platform_data = &mxc_ports[0], + }, +}; + +static struct platform_device mxc_uart_device2 = { + .name = "mxcintuart", + .id = 1, + .dev = { + .platform_data = &mxc_ports[1], + }, +}; + +#if UART3_ENABLED == 1 +static struct platform_device mxc_uart_device3 = { + .name = "mxcintuart", + .id = 2, + .dev = { + .platform_data = &mxc_ports[2], + }, +}; +#endif + +static int __init mxc_init_uart(void) +{ + /* Register all the MXC UART platform device structures */ + platform_device_register(&mxc_uart_device1); + platform_device_register(&mxc_uart_device2); + + /* Grab ownership of shared UARTs 3 and 4, only when enabled */ +#if UART3_ENABLED == 1 +#if UART3_DMA_ENABLE == 1 + spba_take_ownership(UART3_SHARED_PERI, (SPBA_MASTER_A | SPBA_MASTER_C)); +#else + spba_take_ownership(UART3_SHARED_PERI, SPBA_MASTER_A); +#endif /* UART3_DMA_ENABLE */ + platform_device_register(&mxc_uart_device3); +#endif /* UART3_ENABLED */ + + return 0; +} + +#else +static int __init mxc_init_uart(void) +{ + return 0; +} +#endif + +arch_initcall(mxc_init_uart); diff -urN linux-2.6.26/arch/arm/mach-mx35/serial.h linux-2.6.26-lab126/arch/arm/mach-mx35/serial.h --- linux-2.6.26/arch/arm/mach-mx35/serial.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/serial.h 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,132 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ARCH_ARM_MACH_MX35_SERIAL_H__ +#define __ARCH_ARM_MACH_MX35_SERIAL_H__ + +/*! + * @file mach-mx35/serial.h + * + * @ingroup MSL_MX35 + */ +#include + +/* UART 1 configuration */ +/*! + * This option allows to choose either an interrupt-driven software controlled + * hardware flow control (set this option to 0) or hardware-driven hardware + * flow control (set this option to 1). + */ +#define UART1_HW_FLOW 1 +/*! + * This specifies the threshold at which the CTS pin is deasserted by the + * RXFIFO. Set this value in Decimal to anything from 0 to 32 for + * hardware-driven hardware flow control. Read the HW spec while specifying + * this value. When using interrupt-driven software controlled hardware + * flow control set this option to -1. + */ +#define UART1_UCR4_CTSTL 16 +/*! + * This is option to enable (set this option to 1) or disable DMA data transfer + */ +#define UART1_DMA_ENABLE 0 +/*! + * Specify the size of the DMA receive buffer. The minimum buffer size is 512 + * bytes. The buffer size should be a multiple of 256. + */ +#define UART1_DMA_RXBUFSIZE 1024 +/*! + * Specify the MXC UART's Receive Trigger Level. This controls the threshold at + * which a maskable interrupt is generated by the RxFIFO. Set this value in + * Decimal to anything from 0 to 32. Read the HW spec while specifying this + * value. + */ +#define UART1_UFCR_RXTL 16 +/*! + * Specify the MXC UART's Transmit Trigger Level. This controls the threshold at + * which a maskable interrupt is generated by the TxFIFO. Set this value in + * Decimal to anything from 0 to 32. Read the HW spec while specifying this + * value. + */ +#define UART1_UFCR_TXTL 16 +/* UART 2 configuration */ +#define UART2_HW_FLOW 1 +#define UART2_UCR4_CTSTL 16 +#define UART2_DMA_ENABLE 0 +#define UART2_DMA_RXBUFSIZE 1024 +#define UART2_UFCR_RXTL 16 +#define UART2_UFCR_TXTL 16 +/* UART 3 configuration */ +#define UART3_HW_FLOW 1 +#define UART3_UCR4_CTSTL 16 +#define UART3_DMA_ENABLE 1 +#define UART3_DMA_RXBUFSIZE 1024 +#define UART3_UFCR_RXTL 16 +#define UART3_UFCR_TXTL 16 + +/* + * UART Chip level Configuration that a user may not have to edit. These + * configuration vary depending on how the UART module is integrated with + * the ARM core + */ +/* + * Is the MUXED interrupt output sent to the ARM core + */ +#define INTS_NOTMUXED 0 +#define INTS_MUXED 1 +/* UART 1 configuration */ +/*! + * This define specifies whether the muxed ANDed interrupt line or the + * individual interrupts from the UART port is integrated with the ARM core. + * There exists a define like this for each UART port. Valid values that can + * be used are \b INTS_NOTMUXED or \b INTS_MUXED. + */ +#define UART1_MUX_INTS INTS_MUXED +/*! + * This define specifies the transmitter interrupt number or the interrupt + * number of the ANDed interrupt in case the interrupts are muxed. There exists + * a define like this for each UART port. + */ +#define UART1_INT1 MXC_INT_UART1 +/*! + * This define specifies the receiver interrupt number. If the interrupts of + * the UART are muxed, then we specify here a dummy value -1. There exists a + * define like this for each UART port. + */ +#define UART1_INT2 -1 +/*! + * This specifies the master interrupt number. If the interrupts of the UART + * are muxed, then we specify here a dummy value of -1. There exists a define + * like this for each UART port. + */ +#define UART1_INT3 -1 +/*! + * This specifies if the UART is a shared peripheral. It holds the shared + * peripheral number if it is shared or -1 if it is not shared. There exists + * a define like this for each UART port. + */ +#define UART1_SHARED_PERI -1 +/* UART 2 configuration */ +#define UART2_MUX_INTS INTS_MUXED +#define UART2_INT1 MXC_INT_UART2 +#define UART2_INT2 -1 +#define UART2_INT3 -1 +#define UART2_SHARED_PERI -1 +/* UART 3 configuration */ +#define UART3_MUX_INTS INTS_MUXED +#define UART3_INT1 MXC_INT_UART3 +#define UART3_INT2 -1 +#define UART3_INT3 -1 +#define UART3_SHARED_PERI SPBA_UART3 + +#endif /* __ARCH_ARM_MACH_MX35_SERIAL_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx35/system.c linux-2.6.26-lab126/arch/arm/mach-mx35/system.c --- linux-2.6.26/arch/arm/mach-mx35/system.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/system.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,640 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2009 Amazon Technologies, Inc. All Rights Reserved. + * Author: Manish Lachwani (lachwani@lab126.com) + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * Support for IDLE and Suspend modes on the MX35 Luigi. + * + * In the IDLE mode, we try to cut down the emi_clk that will then + * reduce the SDRAM current utilization. emi_clk drives several clocks + * and we need to check the refcnt of those clocks before cutting emi_clk. + * + * Couple of places where emi_clk is not gated - playing audio and when USB is + * active. However, USB autosuspend changes all of this. + * + * In suspend mode, we use suspend to RAM or state retention mode of the MX35 + * + * peri_pll_clk is the parent of usb_clk, sdhc_clk and uart_clk. Gate peri_pll_clk + * by gating sdhc_clk and uart_clk. usb_clk cannot be gated. Hence, check if the + * host controller is in use or not. this is done by checking the WAN status. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "crm_regs.h" + +#include +#include +#include + +/*! + * @defgroup MSL_MX35 i.MX35 Machine Specific Layer (MSL) + */ + +/*! + * @file mach-mx35/system.c + * @brief This file contains idle and reset functions. + * + * @ingroup MSL_MX35 + */ + +static int clks_initialized = 0; +static struct clk *sdma_clk, *ipu_clk, *usb_clk, *emi_clk, *nfc_clk, *usb_ahb_clk; +static struct clk *ata_clk, *esai_clk, *wdog_clk, *peri_pll_clk, *fec_clk; +static struct clk *spba_clk, *uart_clk, *sdhc_clk, *sdhc1_clk, *sdhc2_clk, *cspi_clk; +static struct clk *i2c1_clk, *i2c2_clk; + +static int emi_zero_count = 0, peri_pll_zero = 0; + +/*! +* MX35 low-power mode +*/ +enum mx35_low_pwr_mode { + MX35_RUN_MODE, + MX35_WAIT_MODE, + MX35_DOZE_MODE, + MX35_STOP_MODE +}; + +extern int mxc_jtag_enabled; +extern int kernel_oops_counter; + +/* Idle clock masks for the CGR */ + +/* CSPI1, EMI, ESDHC1, ESDHC2 and ESDHC3 */ +#define MX35_CGR0_MASK 0x3c0c0c00 + +/* GPT, I2C1 and I2C2 */ +#define MX35_CGR1_MASK 0x00003F00 + +#define MX35_CGR1_MASK_I2C 0x00000300 + +#ifdef CONFIG_FEC + +/* CGR1 MASK when Fast Ethernet Controller is enabled */ + +#define MX35_CGR1_MASK_FEC 0x00003F03 + +#define MX35_CGR1_MASK_I2C_FEC 0x00000303 + +#endif + +/* IPU - bits 18-19 in CGR1 */ +#define MX35_CGR1_IPU_MASK 0xc0000 + +/* SDMA, SPBA, UART1, USBOTG, MAX, WDOG */ +#define MX35_CGR2_MASK 0x0cc303F0 + +/* SDMA, SPBA, UART1, MAX, WDOG */ +#define MX35_CGR2_USBOTG_MASK 0x0c0303F0 + +/* All gated except the ones marked as reserved and IIM */ +#define MX35_CGR3_MASK 0xffffffc0 + +/* Prototype */ +static int check_i2c_clk(void); + +/*! + * This function is used to set cpu low power mode before WFI instruction + * + * @param mode indicates different kinds of power modes + */ +void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) +{ + unsigned int lpm; + unsigned long reg; + + /*read CCMR value */ + reg = __raw_readl(MXC_CCM_CCMR); + + switch (mode) { + case WAIT_UNCLOCKED_POWER_OFF: + lpm = MX35_DOZE_MODE; + reg |= MXC_CCM_CCMR_WBEN; + break; + + case STOP_POWER_ON: + case STOP_POWER_OFF: + lpm = MX35_STOP_MODE; + /* Enabled Standby */ + reg |= MXC_CCM_CCMR_VSTBY | MXC_CCM_CCMR_WBEN; + break; + + case WAIT_CLOCKED: + case WAIT_UNCLOCKED: + default: + /* Wait is the default mode used when idle. */ + lpm = MX35_WAIT_MODE; + break; + } + + /* program LPM bit */ + reg = (reg & (~MXC_CCM_CCMR_LPM_MASK)) | lpm << MXC_CCM_CCMR_LPM_OFFSET; + /* program Interrupt holdoff bit */ + reg = reg | MXC_CCM_CCMR_WFI; + /* TBD: PMIC has put the voltage back to Normal if the voltage ready */ + /* counter finished */ + reg = reg | MXC_CCM_CCMR_STBY_EXIT_SRC; + + __raw_writel(reg, MXC_CCM_CCMR); +} + +EXPORT_SYMBOL(mxc_cpu_lp_set); + +/* Is SD doing any DMA? */ +extern int sd_turn_of_dma; + +static inline cputime64_t get_cpu_idle_time(unsigned int cpu) +{ + cputime64_t idle_time; + cputime64_t cur_jiffies; + cputime64_t busy_time; + + cur_jiffies = jiffies64_to_cputime64(get_jiffies_64()); + busy_time = cputime64_add(kstat_cpu(cpu).cpustat.user, + kstat_cpu(cpu).cpustat.system); + + busy_time = cputime64_add(busy_time, kstat_cpu(cpu).cpustat.irq); + busy_time = cputime64_add(busy_time, kstat_cpu(cpu).cpustat.softirq); + busy_time = cputime64_add(busy_time, kstat_cpu(cpu).cpustat.steal); + + busy_time = cputime64_add(busy_time, + kstat_cpu(cpu).cpustat.nice); + idle_time = cputime64_sub(cur_jiffies, busy_time); + return jiffies_to_usecs(idle_time); +} + +/* + * sysfs interface to CPU idle counts + */ +static ssize_t +sysfs_show_idle_count(struct sys_device *dev, char *buf) +{ + char *curr = buf; + + curr += sprintf(curr, "sdma_clk usecount: %d\n", clk_get_usecount(sdma_clk)); + curr += sprintf(curr, "usb_ahb_clk usecount: %d\n", clk_get_usecount(usb_ahb_clk)); + curr += sprintf(curr, "emi_clk_gating_count: %d\n", emi_zero_count); + curr += sprintf(curr, "ipu_clk usecount: %d\n", clk_get_usecount(ipu_clk)); + curr += sprintf(curr, "Internal SD DMA: %d\n", sd_turn_of_dma); + curr += sprintf(curr, "peri_pll_zero_count: %d\n", peri_pll_zero); + curr += sprintf(curr, "emi_clk: %d\n", clk_get_usecount(emi_clk)); + curr += sprintf(curr, "idle_time: %llu us\n", get_cpu_idle_time(0)); + curr += sprintf(curr, "\n"); + return curr - buf; +} + +/* + * Sysfs setup bits + */ +static SYSDEV_ATTR(idle_count, 0600, sysfs_show_idle_count, NULL); + +static struct sysdev_class cpu_idle_sysclass = { + .name = "cpu_idle_count", +}; + +static struct sys_device device_cpu_idle = { + .id = 0, + .cls = &cpu_idle_sysclass, +}; + +static int __init init_cpu_idle_sysfs(void) +{ + int error = sysdev_class_register(&cpu_idle_sysclass); + + if (!error) + error = sysdev_register(&device_cpu_idle); + + if (!error) + error = sysdev_create_file( + &device_cpu_idle, &attr_idle_count); + return error; +} + +device_initcall(init_cpu_idle_sysfs); + +/* Flag to check if USB HC1 is gated or not */ +int usb_hc1_gated = 0; +EXPORT_SYMBOL(usb_hc1_gated); + +/* Flag to check if USB OTG is gated or not */ +int usb_otg_gated_off = 0; +EXPORT_SYMBOL(usb_otg_gated_off); + +static void disable_clks_for_good(void) +{ + clk_disable(ata_clk); + clk_disable(esai_clk); +} + +static void pmcr2_disable_oscaudio(void) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_PMCR2) | MXC_CCM_PMCR2_OSC_AUDIO_DOWN; + __raw_writel(reg, MXC_CCM_PMCR2); + + /* Turn off DPTC */ + reg = __raw_readl(MXC_CCM_PMCR0) & ~(0x1); + __raw_writel(reg, MXC_CCM_PMCR0); +} + +static void enable_cgr_clks(void) +{ + unsigned long reg = 0xffffffff; + + __raw_writel(reg, MXC_CCM_CGR0); + __raw_writel(reg, MXC_CCM_CGR1); + __raw_writel(reg, MXC_CCM_CGR2); + __raw_writel(reg, MXC_CCM_CGR3); + +} + +static int eink_doze_counter(void); +static int eink_doze_disable_cnt = 0; + +/*! + * Disable CGR clocks during IDLE + */ +static inline void disable_cgr_clks(void) +{ + unsigned long reg; + + reg = MX35_CGR0_MASK; + + /* Check the count on the cspi_clk */ + if (!cspi_clk->usecount) + reg &= ~(0xc00); + + __raw_writel(reg, MXC_CCM_CGR0); + + if (check_i2c_clk()) { +#ifdef CONFIG_FEC + reg = MX35_CGR1_MASK_FEC; +#else + reg = MX35_CGR1_MASK; +#endif + } else { +#ifdef CONFIG_FEC + reg = MX35_CGR1_MASK_I2C_FEC; +#else + reg = MX35_CGR1_MASK_I2C; +#endif + } + if (eink_doze_disable_cnt) + reg &= ~(MX35_CGR1_IPU_MASK); + + __raw_writel(reg, MXC_CCM_CGR1); + + if (usb_ahb_clk->usecount) + reg = MX35_CGR2_MASK; + else + reg = MX35_CGR2_USBOTG_MASK; + + if (!uart_clk->usecount) + reg &= ~(0x30000); + + __raw_writel(reg, MXC_CCM_CGR2); + + __raw_writel(MX35_CGR3_MASK, MXC_CCM_CGR3); + +} + +/*! + * cko_clk needed during audio and video + */ +void noinline cko1_enable(void) +{ + u32 reg = __raw_readl(MXC_CCM_COSR) | MXC_CCM_COSR_CLKOEN; + __raw_writel(reg, MXC_CCM_COSR); +} + +EXPORT_SYMBOL(cko1_enable); + +void noinline cko1_disable(void) +{ + u32 reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOEN; + /* Turn off ASRC AUDIO_EN */ + reg &= ~(0x01000000); + __raw_writel(reg, MXC_CCM_COSR); +} + +EXPORT_SYMBOL(cko1_disable); + +static void initialize_clocks(void) +{ + sdma_clk = clk_get(NULL, "sdma_ahb_clk"); + usb_ahb_clk = clk_get(NULL, "usb_ahb_clk"); + + emi_clk = clk_get(NULL, "emi_clk"); + ipu_clk = clk_get(NULL, "ipu_clk"); + nfc_clk = clk_get(NULL, "nfc_clk"); + usb_clk = clk_get(NULL, "usb_clk"); + ata_clk = clk_get(NULL, "ata_clk"); + esai_clk = clk_get(NULL, "esai_clk"); + wdog_clk = clk_get(NULL, "wdog_clk"); + peri_pll_clk = clk_get(NULL, "peri_pll"); + fec_clk = clk_get(NULL, "fec_clk"); + spba_clk = clk_get(NULL, "spba_clk"); + uart_clk = clk_get(NULL, "uart_clk.0"); + + sdhc_clk = clk_get(NULL, "sdhc_clk.0"); + sdhc1_clk = clk_get(NULL, "sdhc_clk.1"); + sdhc2_clk = clk_get(NULL, "sdhc_clk.2"); + + cspi_clk = clk_get(NULL, "cspi_clk.0"); + i2c1_clk = clk_get(NULL, "i2c_clk.0"); + i2c2_clk = clk_get(NULL, "i2c_clk.1"); +} + +static int check_sdhc_clk(void) +{ + return (sdhc_clk->usecount | + sdhc1_clk->usecount| + sdhc2_clk->usecount); +} + +static int check_i2c_clk(void) +{ + return (i2c1_clk->usecount | + i2c2_clk->usecount); +} + +/*! + * Check the current status of the WAN. This is needed for the + * peri_pll_clk gating logic. peri_pll_clk is the parent of the + * usb_clk. + */ +static int check_wan_status(void) +{ + if ( (wan_get_power_status() == WAN_OFF) || + (wan_get_power_status() == WAN_INVALID)) { + return 1; + } + else + return 0; +} + +static void reduce_nfc_clk_speed(void) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_PDR4); + reg |= (16 << MXC_CCM_PDR4_NFC_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_PDR4); +} + +static void noinline peri_pll_enable(void) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCMR); + reg |= MXC_CCM_CCMR_UPE; + __raw_writel(reg, MXC_CCM_CCMR); + + udelay(80); +} + +static void noinline peri_pll_disable(void) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCMR); + reg &= ~MXC_CCM_CCMR_UPE; + __raw_writel(reg, MXC_CCM_CCMR); +} + +/* + * Don't deep idle if audio is playing + */ +extern int mx35_luigi_audio_playing_flag; +static int doze_lpm_flag = 0; + +void eink_doze_enable(int enable) +{ + eink_doze_disable_cnt = enable; +} + +EXPORT_SYMBOL(eink_doze_enable); + +static int eink_doze_counter(void) +{ + return eink_doze_disable_cnt; +} + +void doze_disable(void) +{ + doze_lpm_flag = 1; +} +EXPORT_SYMBOL(doze_disable); + +void doze_enable(void) +{ + doze_lpm_flag = 0; +} +EXPORT_SYMBOL(doze_enable); + +/*! + * Disable the SPBA clock + */ +static void mxc_spba_disable(void) +{ + unsigned long reg; + + reg = __raw_readl(MXC_CCM_CGR2); + reg &= ~0xC0; + __raw_writel(reg, MXC_CCM_CGR2); +} + +/*! + * Enable the SPBA clock + */ +static void mxc_spba_enable(void) +{ + unsigned long reg; + + reg = __raw_readl(MXC_CCM_CGR2); + reg |= 0xC0; + __raw_writel(reg, MXC_CCM_CGR2); +} + +/*! + * This function puts the CPU into idle mode. It is called by default_idle() + * in process.c file. + */ +void arch_idle(void) +{ + int emi_gated_off = 0, peri_pll_gated = 0; + int usb_hc1_gated_off = 0; + + if (mxc_jtag_enabled) + return; + + /* + * This should do all the clock switching + * and wait for interrupt tricks. + */ + if (!mx35_luigi_audio_playing_flag && !doze_lpm_flag) { + if (clks_initialized == 0) { + clks_initialized = 1; + initialize_clocks(); + disable_clks_for_good(); + pmcr2_disable_oscaudio(); + reduce_nfc_clk_speed(); + } + + disable_cgr_clks(); + if (eink_doze_counter()) + cko1_disable(); + clk_disable(ipu_clk); + + if (check_wan_status()) + usb_hc1_gated_off = 1; + else { + if (usb_hc1_gated) + usb_hc1_gated_off = 1; + } + + /* + * Check if emi_clk can be gated + */ + if ((!sdma_clk->usecount) + && (ipu_clk->usecount <= 1) + && (usb_hc1_gated_off == 1) + && (usb_otg_gated_off == 1) + && (nfc_clk->usecount == 0) + && (sd_turn_of_dma == 0) + && (fec_clk->usecount == 0) ) { + emi_gated_off = 1; + clk_disable(emi_clk); + } + + /* + * Check if the peri_pll_clk can be gated + */ + if (!check_sdhc_clk() + && (emi_gated_off == 1) + && (!usb_ahb_clk->usecount) + && (!uart_clk->usecount)) { + peri_pll_disable(); + peri_pll_gated = 1; + } + + mxc_cpu_lp_set(WAIT_UNCLOCKED); + cpu_do_idle(); + + if (peri_pll_gated == 1) + peri_pll_enable(); + + if (emi_gated_off == 1) { + clk_enable(emi_clk); + } + + clk_enable(ipu_clk); + cko1_enable(); + enable_cgr_clks(); + } + else { + mxc_cpu_lp_set(WAIT_UNCLOCKED); + cpu_do_idle(); + enable_cgr_clks(); + } +} + +extern int cpufreq_suspended; +extern int set_cpu_freq(int wp); +extern void mx35_power_off(void); + +/* + * This function resets the system. It is called by machine_restart(). + * + * @param mode indicates different kinds of resets + */ +void arch_reset(char mode) +{ + unsigned long reg; + unsigned long reg_1 = 0xffffffff; + + reg = __raw_readl(MXC_CCM_CGR0); + reg |= (MXC_CCM_CGR0_ESDHC1_MASK | MXC_CCM_CGR0_ESDHC2_MASK | + MXC_CCM_CGR0_ESDHC3_MASK); + __raw_writel(reg, MXC_CCM_CGR0); + + reg = __raw_readl(MXC_CCM_CGR3); + reg |= MXC_CCM_CGR3_IIM_MASK; + __raw_writel(reg, MXC_CCM_CGR3); + + printk(KERN_INFO "MX35 arch_reset\n"); + + if (in_interrupt() || kernel_oops_counter) { + mxc_wd_reset(); + return; + } + + local_irq_enable(); + /* Clear out bit #1 in MEMA */ + pmic_write_reg(REG_MEM_A, (0 << 1), (1 << 1)); + + /* Turn on bit #1 */ + pmic_write_reg(REG_MEM_A, (1 << 1), (1 << 1)); + + doze_disable(); + + /* Turn off VSD */ + pmic_write_reg(REG_MODE_1, (0 << 18), (1 << 18)); + + cpufreq_suspended = 1; + set_cpu_freq(512000000); + + mdelay(100); + + peri_pll_enable(); + + __raw_writel(reg_1, MXC_CCM_CGR0); + __raw_writel(reg_1, MXC_CCM_CGR1); + __raw_writel(reg_1, MXC_CCM_CGR2); + __raw_writel(reg_1, MXC_CCM_CGR3); + + mdelay(100); + + /* Memory Hold Mode */ + mx35_power_off(); +} +EXPORT_SYMBOL(arch_reset); + +#ifdef CONFIG_MACH_LUIGI_LAB126 +EXPORT_SYMBOL(sys_open); +EXPORT_SYMBOL(sys_write); +EXPORT_SYMBOL(sys_read); + +#include +unsigned long einkfb_logging = _LLOG_LEVEL_DEFAULT; +EXPORT_SYMBOL(einkfb_logging); +#endif diff -urN linux-2.6.26/arch/arm/mach-mx35/usb.h linux-2.6.26-lab126/arch/arm/mach-mx35/usb.h --- linux-2.6.26/arch/arm/mach-mx35/usb.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/usb.h 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,104 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +extern int usbotg_init(struct platform_device *pdev); +extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata); +extern struct platform_device *host_pdev_register(struct resource *res, + int n_res, struct fsl_usb2_platform_data *config); + +extern int fsl_usb_host_init(struct platform_device *pdev); +extern void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata); +extern int gpio_usbh2_active(void); +extern void gpio_usbh2_inactive(void); +extern int gpio_usbotg_utmi_active(void); +extern void gpio_usbotg_utmi_inactive(void); + +/* + * Determine which platform_data struct to use for the DR controller, + * based on which transceiver is configured. + * PDATA is a pointer to it. + */ +static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config; +#define PDATA (&dr_utmi_config) + + +/* + * Used to set pdata->operating_mode before registering the platform_device. + * If OTG is configured, the controller operates in OTG mode, + * otherwise it's either host or device. + */ +#ifdef CONFIG_USB_OTG +#define DR_UDC_MODE FSL_USB2_DR_OTG +#define DR_HOST_MODE FSL_USB2_DR_OTG +#else +#define DR_UDC_MODE FSL_USB2_DR_DEVICE +#define DR_HOST_MODE FSL_USB2_DR_HOST +#endif + + +#ifdef CONFIG_USB_EHCI_ARC_OTG +static inline void dr_register_host(struct resource *r, int rs) +{ + PDATA->operating_mode = DR_HOST_MODE; + host_pdev_register(r, rs, PDATA); +} +#else +static inline void dr_register_host(struct resource *r, int rs) +{ +} +#endif + +#ifdef CONFIG_USB_GADGET_ARC +static struct platform_device dr_udc_device; + +static inline void dr_register_udc(void) +{ + PDATA->operating_mode = DR_UDC_MODE; + dr_udc_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_udc_device)) + printk(KERN_ERR "usb: can't register DR gadget\n"); + else + printk(KERN_INFO "usb: DR gadget (%s) registered\n", + PDATA->transceiver); +} +#else +static inline void dr_register_udc(void) +{ +} +#endif + +#ifdef CONFIG_USB_OTG +static struct platform_device dr_otg_device; + +/* + * set the proper operating_mode and + * platform_data pointer, then register the + * device. + */ +static inline void dr_register_otg(void) +{ + PDATA->operating_mode = FSL_USB2_DR_OTG; + dr_otg_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_otg_device)) + printk(KERN_ERR "usb: can't register otg device\n"); + else + printk(KERN_INFO "usb: DR OTG registered\n"); +} +#else +static inline void dr_register_otg(void) +{ +} +#endif diff -urN linux-2.6.26/arch/arm/mach-mx35/usb_dr.c linux-2.6.26-lab126/arch/arm/mach-mx35/usb_dr.c --- linux-2.6.26/arch/arm/mach-mx35/usb_dr.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/usb_dr.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,222 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include "usb.h" + +/* + * platform data structs + * - Which one to use is determined by CONFIG options in usb.h + * - operating_mode plugged at run time + */ +static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = { + .name = "DR", + .platform_init = usbotg_init, + .platform_uninit = usbotg_uninit, + .phy_mode = FSL_USB2_PHY_UTMI_WIDE, + .power_budget = 500, /* 500 mA max power */ + .gpio_usb_active = gpio_usbotg_utmi_active, + .gpio_usb_inactive = gpio_usbotg_utmi_inactive, + .transceiver = "utmi", +}; + + +/* + * resources + */ +static struct resource otg_resources[] = { + [0] = { + .start = (u32)(USB_OTGREGS_BASE), + .end = (u32)(USB_OTGREGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_USB_OTG, + .flags = IORESOURCE_IRQ, + }, +}; + + +static u64 dr_udc_dmamask = ~(u32) 0; +static void dr_udc_release(struct device *dev) +{ +} + +static u64 dr_otg_dmamask = ~(u32) 0; +static void dr_otg_release(struct device *dev) +{ +} + +/* + * platform device structs + * dev.platform_data field plugged at run time + */ +static struct platform_device __maybe_unused dr_udc_device = { + .name = "fsl-usb2-udc", + .id = -1, + .dev = { + .release = dr_udc_release, + .dma_mask = &dr_udc_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), +}; + +static struct platform_device __maybe_unused dr_otg_device = { + .name = "fsl-usb2-otg", + .id = -1, + .dev = { + .release = dr_otg_release, + .dma_mask = &dr_otg_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), +}; + +struct usb_dr_dc { + /* Capability register */ + u32 id; + u32 res1[35]; + u32 sbuscfg; /* sbuscfg ahb burst */ + u32 res11[27]; + u16 caplength; /* Capability Register Length */ + u16 hciversion; /* Host Controller Interface Version */ + u32 hcsparams; /* Host Controller Structual Parameters */ + u32 hccparams; /* Host Controller Capability Parameters */ + u32 res2[5]; + u32 dciversion; /* Device Controller Interface Version */ + u32 dccparams; /* Device Controller Capability Parameters */ + u32 res3[6]; + /* Operation register */ + u32 usbcmd; /* USB Command Register */ + u32 usbsts; /* USB Status Register */ + u32 usbintr; /* USB Interrupt Enable Register */ + u32 frindex; /* Frame Index Register */ + u32 res4; + u32 deviceaddr; /* Device Address */ + u32 endpointlistaddr; /* Endpoint List Address Register */ + u32 res5; + u32 burstsize; /* Master Interface Data Burst Size Register */ + u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ + u32 res6[6]; + u32 configflag; /* Configure Flag Register */ + u32 portsc1; /* Port 1 Status and Control Register */ + u32 res7[7]; + u32 otgsc; /* On-The-Go Status and Control */ + u32 usbmode; /* USB Mode Register */ + u32 endptsetupstat; /* Endpoint Setup Status Register */ + u32 endpointprime; /* Endpoint Initialization Register */ + u32 endptflush; /* Endpoint Flush Register */ + u32 endptstatus; /* Endpoint Status Register */ + u32 endptcomplete; /* Endpoint Complete Register */ + u32 endptctrl[8 * 2]; /* Endpoint Control Registers */ +}; + +unsigned int usbdr_early_portsc1_read(void) +{ + volatile struct usb_dr_dc *dr_regs; + int start = USB_OTGREGS_BASE; + int end = USB_OTGREGS_BASE + 0x1ff; + unsigned int portsc1; + unsigned int temp; + unsigned long timeout; + + if (!request_mem_region(start, (end - start + 1), "fsl-usb-dr")) + return -1; + + dr_regs = ioremap(start, (end - start + 1)); + if (!dr_regs) { + release_mem_region(start, (end - start + 1)); + return -1; + } + + /* Stop and reset the usb controller */ + temp = readl(&dr_regs->usbcmd); + temp &= ~0x1; + writel(temp, &dr_regs->usbcmd); + + temp = readl(&dr_regs->usbcmd); + temp |= 0x2; + writel(temp, &dr_regs->usbcmd); + + /* Wait for reset to complete */ + timeout = jiffies + 1000; + while (readl(&dr_regs->usbcmd) & 0x2) { + if (time_after(jiffies, timeout)) { + printk("udc reset timeout! \n"); + return -ETIMEDOUT; + } + cpu_relax(); + } + + /* Set the controller as device mode */ + temp = readl(&dr_regs->usbmode); + temp &= ~0x3; /* clear mode bits */ + temp |= 0x2; + /* Disable Setup Lockout */ + temp |= 0x8; + writel(temp, &dr_regs->usbmode); + + /* Config PHY interface */ + portsc1 = readl(&dr_regs->portsc1); + portsc1 &= ~(0xc0000000 | 0x10000000 | 0x80) | 0x10000000 | 0x40; + writel(portsc1, &dr_regs->portsc1); + + /* Set controller to Run */ + temp = readl(&dr_regs->usbcmd); + temp |= 0x1; + writel(temp, &dr_regs->usbcmd); + + mdelay(100); + + /* Get the line status bits */ + portsc1 = readl(&dr_regs->portsc1) & 0xc00; + + /* disable all INTR */ + writel(0, &dr_regs->usbintr); + + /* set controller to Stop */ + temp = readl(&dr_regs->usbcmd); + temp &= ~0x1; + writel(temp, &dr_regs->usbcmd); + + release_mem_region(start, (end - start + 1)); + return portsc1; +} +EXPORT_SYMBOL(usbdr_early_portsc1_read); + +static int __init usb_dr_init(void) +{ + pr_debug("%s: \n", __func__); + + /* i.MX35 1.0 should work in INCR mode */ + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 0) { + PDATA->change_ahb_burst = 1; + PDATA->ahb_burst_mode = 0; + } + + dr_register_otg(); + dr_register_host(otg_resources, ARRAY_SIZE(otg_resources)); + dr_register_udc(); + + return 0; +} + +module_init(usb_dr_init); diff -urN linux-2.6.26/arch/arm/mach-mx35/usb_h2.c linux-2.6.26-lab126/arch/arm/mach-mx35/usb_h2.c --- linux-2.6.26/arch/arm/mach-mx35/usb_h2.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/usb_h2.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,62 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include + +#include +#include "usb.h" + +static struct fsl_usb2_platform_data usbh2_config = { + .name = "Host 2", + .platform_init = fsl_usb_host_init, + .platform_uninit = fsl_usb_host_uninit, + .operating_mode = FSL_USB2_MPH_HOST, + .phy_mode = FSL_USB2_PHY_SERIAL, + .power_budget = 500, /* 500 mA max power */ + .gpio_usb_active = gpio_usbh2_active, + .gpio_usb_inactive = gpio_usbh2_inactive, + .transceiver = "serial", +}; + +static struct resource usbh2_resources[] = { + [0] = { + .start = (u32) (USB_H2REGS_BASE), + .end = (u32) (USB_H2REGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_USB_HS, + .flags = IORESOURCE_IRQ, + }, +}; + + +static int __init usbh2_init(void) +{ + pr_debug("%s: \n", __func__); + + /* i.MX35 1.0 should work in INCR mode */ + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 0) { + usbh2_config.change_ahb_burst = 1; + usbh2_config.ahb_burst_mode = 0; + } + + host_pdev_register(usbh2_resources, ARRAY_SIZE(usbh2_resources), + &usbh2_config); + return 0; +} +module_init(usbh2_init); diff -urN linux-2.6.26/arch/arm/mach-mx35/wifi.c linux-2.6.26-lab126/arch/arm/mach-mx35/wifi.c --- linux-2.6.26/arch/arm/mach-mx35/wifi.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx35/wifi.c 2010-08-10 04:14:14.000000000 -0400 @@ -0,0 +1,197 @@ +/* + * wifi.c -- MX35 WiFi driver. + * + * Copyright 2009 Lab126, Inc. All rights reserved. + * Manish Lachwani (lachwani@lab126.com) + * + * Support for WiFi on MX35 Luigi + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Turn on the WiFi Power and Reset GPIO + */ +extern void gpio_wifi_enable(int enable); +extern int get_pmic_revision(void); +extern void gpio_wifi_do_reset(void); + +#define SW1_VOLTAGE 1200000 /* SW1 voltage level in normal mode */ +#define SW1_REGISTER 28 /* SW1 register to turn it off/on */ +#define SW1_VALUE 24 /* SW1 register to set voltage */ + +static int luigi_wifi_status = 0; + +/*! + * Check if Atlas Rev 3.1 + */ +static int check_atlas_rev31(void) +{ + int reg = 0; + + pmic_read_reg(REG_IDENTIFICATION, ®, 0xffffffff); + + if (reg & 0x1) + return 1; + else + return 0; +} + +static void mx35_sw1_power_state(int enable) +{ + static struct regulator *sw1_wifi_reg; + + sw1_wifi_reg = regulator_get(NULL, "SW1"); + + if (enable == 1) { + /* Enable SW1: Auto for Normal and Auto in standby */ + if (check_atlas_rev31()) + pmic_write_reg(SW1_REGISTER, 0x4, 0xf << 0); + else + pmic_write_reg(SW1_REGISTER, 0x6, 0xf << 0); + + regulator_enable(sw1_wifi_reg); + regulator_set_voltage(sw1_wifi_reg, SW1_VOLTAGE); + } + else { + regulator_disable(sw1_wifi_reg); + regulator_set_voltage(sw1_wifi_reg, 0); + + /* Set to off in Normal mode */ + pmic_write_reg(SW1_REGISTER, enable, 0xf << 0); + + /* Set 0V in Normal mode */ + pmic_write_reg(SW1_VALUE, 0, 0x1f << 0); + } + + mdelay(10); +} + +/* Reset the WiFi chip */ +void mx35_wifi_reset(void) +{ + printk(KERN_INFO "Resetting Atheros WiFi\n"); + gpio_wifi_do_reset(); + +} +EXPORT_SYMBOL(mx35_wifi_reset); + +static void luigi_wifi_enable(int enable) +{ + luigi_wifi_status = enable; + mx35_sw1_power_state(enable); + gpio_wifi_enable(enable); + mdelay(10); +} + +static ssize_t wifi_enable_store(struct sys_device *dev, const char *buf, + size_t size) +{ + int value; + + if (sscanf(buf, "%d", &value) > 0) { + luigi_wifi_enable(value); + return strlen(buf); + } + + return -EINVAL; +} + +static ssize_t wifi_enable_show(struct sys_device *dev, char *buf) +{ + char *curr = buf; + + curr += sprintf(curr, "WiFi status: %d\n", luigi_wifi_status); + curr += sprintf(curr, "\n"); + + return (curr - buf); +} + +static SYSDEV_ATTR(wifi_enable, 0644, wifi_enable_show, wifi_enable_store); + +static ssize_t wifi_reset_store(struct sys_device *dev, const char *buf, + size_t size) +{ + int value; + + if (sscanf(buf, "%d", &value) > 0) { + mx35_wifi_reset(); + return strlen(buf); + } + + return -EINVAL; +} +static SYSDEV_ATTR(wifi_reset, 0644, NULL, wifi_reset_store); + +static struct sysdev_class wifi_sysclass = { + .name = "wifi", +}; + +static struct sys_device wifi_device = { + .id = 0, + .cls = &wifi_sysclass, +}; + +static int luigi_wifi_sysdev_ctrl_init(void) +{ + int err = 0; + + err = sysdev_class_register(&wifi_sysclass); + if (!err) + err = sysdev_register(&wifi_device); + if (!err) { + err = sysdev_create_file(&wifi_device, &attr_wifi_enable); + err = sysdev_create_file(&wifi_device, &attr_wifi_reset); + } + + return err; +} + +void luigi_wifi_sysdev_ctrl_exit(void) +{ + sysdev_remove_file(&wifi_device, &attr_wifi_enable); + sysdev_remove_file(&wifi_device, &attr_wifi_reset); + sysdev_unregister(&wifi_device); + sysdev_class_unregister(&wifi_sysclass); +} + +static int __init wifi_init(void) +{ + int err = 0; + + printk(KERN_INFO "Initializing Luigi WiFi \n"); + + if (luigi_wifi_sysdev_ctrl_init() < 0) { + printk(KERN_ERR "Luigi Wifi: Error setting up sysdev entries\n"); + return err; + } + + luigi_wifi_enable(1); + return err; +} + +static void __exit wifi_cleanup(void) +{ + luigi_wifi_enable(0); +} + +module_init(wifi_init); +module_exit(wifi_cleanup); + +MODULE_AUTHOR("Manish Lachwani"); +MODULE_DESCRIPTION("WiFi driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/mach-mx37/Kconfig linux-2.6.26-lab126/arch/arm/mach-mx37/Kconfig --- linux-2.6.26/arch/arm/mach-mx37/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/Kconfig 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,89 @@ +menu "MX37 Options" + depends on ARCH_MX37 + +config MX37_OPTIONS + bool + default y + select CPU_V6 + select CACHE_L2X0 + select OUTER_CACHE + select USB_ARCH_HAS_EHCI + select ARCH_HAS_EVTMON + select MXC_TZIC + select ARCH_HAS_RNGC + +config MACH_MX37_3DS + bool "Support MX37 3-Stack platforms" + default y + help + Include support for MX37 3-Stack platform. This includes specific + configurations for the board and its peripherals. + +config MXC_SDMA_API + bool "Use SDMA API" + default y + help + This selects the Freescale MXC SDMA API. + If unsure, say N. + +menu "SDMA options" + depends on MXC_SDMA_API + +config SDMA_IRAM + bool "Use Internal RAM for SDMA transfer" + default n + help + Support Internal RAM as SDMA buffer or control structures + +config SDMA_IRAM_SIZE + hex "Reserved bytes of IRAM for SDMA (0x800-0x1000)" + range 0x800 0x1000 + depends on SDMA_IRAM + default "0x1000" + help + Set the size of IRAM for SDMA. It must be a multiple of 512bytes. +endmenu + +config ARCH_MXC_HAS_NFC_V3 + bool "MXC NFC Hardware Version 3" + depends on ARCH_MX37 + default y + help + This selects the Freescale MXC Nand Flash Controller Hardware Version 3 + If unsure, say N. + +config ARCH_MXC_HAS_NFC_V3_1 + bool "MXC NFC Hardware Version 3.1" + depends on ARCH_MXC_HAS_NFC_V3 + default y + help + This selects the Freescale MXC Nand Flash Controller Hardware Version 3.1 + If unsure, say N. + +menu "Device options" + +config I2C_MXC_SELECT1 + bool "Enable I2C1 module" + default y + depends on I2C_MXC + help + Enable MX37 I2C1 module. + +config I2C_MXC_SELECT2 + bool "Enable I2C2 module" + default n + depends on I2C_MXC + help + Enable MX37 I2C2 module. + +config I2C_MXC_SELECT3 + bool "Enable I2C3 module" + default n + depends on I2C_MXC + help + Enable MX37 I2C3 module. + +endmenu + +endmenu + diff -urN linux-2.6.26/arch/arm/mach-mx37/Makefile linux-2.6.26-lab126/arch/arm/mach-mx37/Makefile --- linux-2.6.26/arch/arm/mach-mx37/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/Makefile 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,19 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. + +obj-y := system.o iomux.o cpu.o mm.o clock.o devices.o serial.o dma.o lpmodes.o dptc.o + + +obj-$(CONFIG_MACH_MX37_3DS) += mx37_3stack.o mx37_3stack_gpio.o +obj-$(CONFIG_SPI_MXC) += mx37_3stack_cpld.o +obj-$(CONFIG_REGULATOR_WM8350) += mx37_3stack_pmic_wm8350.o + +# power management +obj-$(CONFIG_PM) += pm.o + +ifneq ($(strip $(CONFIG_USB_GADGET_ARC) $(CONFIG_USB_EHCI_ARC_OTG)),) + obj-y += usb_dr.o +endif diff -urN linux-2.6.26/arch/arm/mach-mx37/Makefile.boot linux-2.6.26-lab126/arch/arm/mach-mx37/Makefile.boot --- linux-2.6.26/arch/arm/mach-mx37/Makefile.boot 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/Makefile.boot 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,3 @@ + zreladdr-y := 0x40008000 +params_phys-y := 0x40000100 +initrd_phys-y := 0x40800000 diff -urN linux-2.6.26/arch/arm/mach-mx37/board-mx37_3stack.h linux-2.6.26-lab126/arch/arm/mach-mx37/board-mx37_3stack.h --- linux-2.6.26/arch/arm/mach-mx37/board-mx37_3stack.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/board-mx37_3stack.h 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,121 @@ +/* + * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX37_3STACK_H__ +#define __ASM_ARCH_MXC_BOARD_MX37_3STACK_H__ + +/*! + * @defgroup BRDCFG_MX37 Board Configuration Options + * @ingroup MSL_MX37 + */ + +/*! + * @file mach-mx37/board-mx37_3stack.h + * + * @brief This file contains all the board level configuration options. + * + * It currently hold the options defined for MX31 ADS Platform. + * + * @ingroup BRDCFG_MX37 + */ + +/* + * Include Files + */ +#include +#include + +/*! + * @name MXC UART EVB board level configurations + */ +/*! @{ */ +/*! + * Specifies if the Irda transmit path is inverting + */ +#define MXC_IRDA_TX_INV 0 +/*! + * Specifies if the Irda receive path is inverting + */ +#define MXC_IRDA_RX_INV 0 + +/* UART 1 configuration */ +/*! + * This define specifies if the UART port is configured to be in DTE or + * DCE mode. There exists a define like this for each UART port. Valid + * values that can be used are \b MODE_DTE or \b MODE_DCE. + */ +#define UART1_MODE MODE_DCE +/*! + * This define specifies if the UART is to be used for IRDA. There exists a + * define like this for each UART port. Valid values that can be used are + * \b IRDA or \b NO_IRDA. + */ +#define UART1_IR NO_IRDA +/*! + * This define is used to enable or disable a particular UART port. If + * disabled, the UART will not be registered in the file system and the user + * will not be able to access it. There exists a define like this for each UART + * port. Specify a value of 1 to enable the UART and 0 to disable it. + */ +#define UART1_ENABLED 1 +/*! @} */ +/* UART 2 configuration */ +#define UART2_MODE MODE_DCE +#define UART2_IR NO_IRDA +#define UART2_ENABLED 1 +/* UART 3 configuration */ +#define UART3_MODE MODE_DCE +#define UART3_IR NO_IRDA +#define UART3_ENABLED 1 + +#define MXC_LL_UART_PADDR UART1_BASE_ADDR +#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) + +#define DEBUG_BASE_ADDRESS 0x78000000 /* Use a Dummy base address */ +/* LAN9217 ethernet base address */ +#define LAN9217_BASE_ADDR DEBUG_BASE_ADDRESS +/* External UART */ +#define UARTA_BASE_ADDR (DEBUG_BASE_ADDRESS + 0x8000) +#define UARTB_BASE_ADDR (DEBUG_BASE_ADDRESS + 0x10000) + +#define BOARD_IO_ADDR 0x20000 +/* LED switchs */ +#define LED_SWITCH_REG BOARD_IO_ADDR + 0x00 +/* buttons */ +#define SWITCH_BUTTONS_REG BOARD_IO_ADDR + 0x08 +/* status, interrupt */ +#define INTR_STATUS_REG BOARD_IO_ADDR + 0x10 +#define INTR_MASK_REG BOARD_IO_ADDR + 0x38 +#define INTR_RESET_REG BOARD_IO_ADDR + 0x20 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER1_REG BOARD_IO_ADDR + 0x40 +#define MAGIC_NUMBER2_REG BOARD_IO_ADDR + 0x48 +/* CPLD code version */ +#define CPLD_CODE_VER_REG BOARD_IO_ADDR + 0x50 + +#define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX37_PIN_GPIO1_4) + +extern unsigned int sdhc_get_card_det_status(struct device *dev); +extern int sdhc_write_protect(struct device *dev); +extern int sdhc_init_card_det(int id); +extern irqreturn_t wm8350_irq_handler(int irq, void *v); +extern void wm8350_irq_work(struct work_struct *work); +extern struct tve_platform_data tve_data; +extern struct mxc_dptc_data dptc_lp_data; +extern struct mxc_dptc_data dptc_gp_data; +extern struct mxc_dvfs_platform_data dvfs_core_data; +extern char *gp_reg_id; +extern char *lp_reg_id; + +extern int headphone_det_status(void); +#endif /* __ASM_ARCH_MXC_BOARD_MX37_3STACK_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx37/clock.c linux-2.6.26-lab126/arch/arm/mach-mx37/clock.c --- linux-2.6.26/arch/arm/mach-mx37/clock.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/clock.c 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,3008 @@ +/* + * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "crm_regs.h" +#include "iomux.h" + +extern int mxc_jtag_enabled; + +static unsigned long pll_base[] = { + (unsigned long)MXC_DPLL1_BASE, + (unsigned long)MXC_DPLL2_BASE, + (unsigned long)MXC_DPLL3_BASE, +}; + +static struct clk pll1_main_clk; +static struct clk pll1_sw_clk; +static struct clk pll2_sw_clk; +static struct clk pll3_sw_clk; +static struct clk lp_apm_clk; +static struct clk emi_core_clk; +static struct clk emi_fast_clk; +static struct clk emi_slow_clk; +static struct clk emi_intr_clk; +static struct clk ddr_clk; +static struct clk ipu_clk[]; +static struct clk axi_a_clk; +static struct clk axi_b_clk; +static struct clk axi_c_clk; +static int cpu_curr_wp; +static struct cpu_wp *cpu_wp_tbl; + +int cpu_wp_nr; + +extern void propagate_rate(struct clk *tclk); +extern void board_ref_clk_rate(unsigned long *ckil, unsigned long *osc, + unsigned long *ckih); +static int cpu_clk_set_wp(int wp); + +static int _clk_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + return 0; +} + +static void _clk_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); +} + +static void _clk_disable_inwait(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); +} + +/* + * For the 4-to-1 muxed input clock + */ +static inline u32 _get_mux(struct clk *parent, struct clk *m0, + struct clk *m1, struct clk *m2, struct clk *m3) +{ + if (parent == m0) { + return 0; + } else if (parent == m1) { + return 1; + } else if (parent == m2) { + return 2; + } else if (parent == m3) { + return 3; + } else { + BUG(); + } + return 0; +} + +static inline unsigned long _get_pll_base(struct clk *pll) +{ + if (pll == &pll1_main_clk) { + return pll_base[0]; + } else if (pll == &pll2_sw_clk) { + return pll_base[1]; + } else if (pll == &pll3_sw_clk) { + return pll_base[2]; + } else { + BUG(); + } + return 0; +} + +static struct clk ckih_clk = { + .name = "ckih", + .flags = RATE_PROPAGATES, +}; + +static struct clk osc_clk = { + .name = "osc", + .flags = RATE_PROPAGATES, +}; + +static struct clk ckil_clk = { + .name = "ckil", + .flags = RATE_PROPAGATES, +}; + +static void _fpm_recalc(struct clk *clk) +{ + clk->rate = ckil_clk.rate * 512; + if ((__raw_readl(MXC_CCM_CCR) & MXC_CCM_CCR_FPM_MULT_MASK) != 0) { + clk->rate *= 2; + } +} + +static int _fpm_enable(struct clk *clk) +{ + u32 reg = __raw_readl(MXC_CCM_CCR); + reg |= MXC_CCM_CCR_FPM_EN; + __raw_writel(reg, MXC_CCM_CCR); + return 0; +} + +static void _fpm_disable(struct clk *clk) +{ + u32 reg = __raw_readl(MXC_CCM_CCR); + reg &= ~MXC_CCM_CCR_FPM_EN; + __raw_writel(reg, MXC_CCM_CCR); +} + +static struct clk fpm_clk = { + .name = "fpm_clk", + .parent = &ckil_clk, + .recalc = _fpm_recalc, + .enable = _fpm_enable, + .disable = _fpm_disable, + .flags = RATE_PROPAGATES, +}; + +static void _fpm_div2_recalc(struct clk *clk) +{ + clk->rate = clk->parent->rate / 2; +} + +static struct clk fpm_div2_clk = { + .name = "fpm_div2_clk", + .parent = &fpm_clk, + .recalc = _fpm_div2_recalc, + .flags = RATE_PROPAGATES, +}; + +static void _clk_pll_recalc(struct clk *clk) +{ + long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; + unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; + unsigned long pllbase; + s64 temp; + + pllbase = _get_pll_base(clk); + + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; + dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; + + if (pll_hfsm == 0) { + dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); + } else { + dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP); + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD); + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN); + } + pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; + mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; + mfi = (mfi <= 5) ? 5 : mfi; + mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; + mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; + /* Sign extend to 32-bits */ + if (mfn >= 0x04000000) { + mfn |= 0xFC000000; + mfn_abs = -mfn; + } + + ref_clk = 2 * clk->parent->rate; + if (dbl != 0) { + ref_clk *= 2; + } + ref_clk /= (pdf + 1); + temp = (u64) ref_clk *mfn_abs; + do_div(temp, mfd + 1); + if (mfn < 0) + temp = -temp; + temp = (ref_clk * mfi) + temp; + + clk->rate = temp; +} + +static int _clk_pll_enable(struct clk *clk) +{ + u32 reg; + u32 pllbase; + + pllbase = _get_pll_base(clk); + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); + + /* Wait for lock */ + while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF)) ; + + return 0; +} + +static void _clk_pll_disable(struct clk *clk) +{ + u32 reg; + u32 pllbase; + + pllbase = _get_pll_base(clk); + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); +} + +static struct clk pll1_main_clk = { + .name = "pll1_main_clk", + .parent = &osc_clk, + .recalc = _clk_pll_recalc, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .flags = RATE_PROPAGATES, +}; + +static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CCSR); + + if (parent == &pll1_main_clk) { + reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + } else { + mux = _get_mux(parent, &lp_apm_clk, NULL, &pll2_sw_clk, + &pll3_sw_clk); + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | + (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CCSR); + reg = __raw_readl(MXC_CCM_CCSR); + reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + } + __raw_writel(reg, MXC_CCM_CCSR); + return 0; +} + +static void _clk_pll1_sw_recalc(struct clk *clk) +{ + u32 reg, div; + div = 1; + reg = __raw_readl(MXC_CCM_CCSR); + + if (clk->parent == &pll2_sw_clk) { + div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >> + MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1; + } else if (clk->parent == &pll3_sw_clk) { + div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >> + MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1; + } + clk->rate = clk->parent->rate / div; +} + +/* pll1 switch clock */ +static struct clk pll1_sw_clk = { + .name = "pll1_sw_clk", + .parent = &pll1_main_clk, + .set_parent = _clk_pll1_sw_set_parent, + .recalc = _clk_pll1_sw_recalc, + .flags = RATE_PROPAGATES, +}; + +/* same as pll2_main_clk. These two clocks should always be the same */ +static struct clk pll2_sw_clk = { + .name = "pll2", + .parent = &osc_clk, + .recalc = _clk_pll_recalc, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .flags = RATE_PROPAGATES, +}; + +/* same as pll3_main_clk. These two clocks should always be the same */ +static struct clk pll3_sw_clk = { + .name = "pll3", + .parent = &osc_clk, + .recalc = _clk_pll_recalc, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .flags = RATE_PROPAGATES, +}; + +static struct clk gpc_dvfs_clk = { + .name = "gpc_dvfs_clk", + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG15_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + if (parent == &osc_clk) { + reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL; + } else if (parent == &fpm_clk) { + reg = __raw_readl(MXC_CCM_CCSR) | MXC_CCM_CCSR_LP_APM_SEL; + } else { + return -EINVAL; + } + __raw_writel(reg, MXC_CCM_CCSR); + + return 0; +} + +static struct clk lp_apm_clk = { + .name = "lp_apm", + .parent = &osc_clk, + .set_parent = _clk_lp_apm_set_parent, + .flags = RATE_PROPAGATES, +}; + +static void _clk_arm_recalc(struct clk *clk) +{ + u32 cacrr, div; + + cacrr = __raw_readl(MXC_CCM_CACRR); + div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1; + clk->rate = clk->parent->rate / div; +} + +static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate) +{ + u32 i; + for (i = 0; i < cpu_wp_nr; i++) { + if (rate == cpu_wp_tbl[i].cpu_rate) + break; + } + if (i > cpu_wp_nr) + return -EINVAL; + cpu_clk_set_wp(i); + + return 0; +} + +static unsigned long _clk_cpu_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 i; + u32 wp; + + for (i = 0; i < cpu_wp_nr; i++) { + if (rate == cpu_wp_tbl[i].cpu_rate) + break; + } + + if (i > cpu_wp_nr) + wp = 0; + + return cpu_wp_tbl[wp].cpu_rate; +} + +static struct clk cpu_clk = { + .name = "cpu_clk", + .parent = &pll1_sw_clk, + .recalc = _clk_arm_recalc, + .set_rate = _clk_cpu_set_rate, + .round_rate = _clk_cpu_round_rate, +}; + +static int _clk_periph_apm_set_parent(struct clk *clk, + struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL); + + reg = __raw_readl(MXC_CCM_CAMR) & ~MXC_CCM_CAMR_PERIPH_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CAMR_PERIPH_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CAMR); + + return 0; +} + +static struct clk periph_apm_clk = { + .name = "periph_apm_clk", + .parent = &pll1_sw_clk, + .set_parent = _clk_periph_apm_set_parent, + .flags = RATE_PROPAGATES, +}; + +/* TODO: Need to sync with GPC to determine if DVFS is in place so that + * the DVFS_PODF divider can be applied in CDCR register. + */ +static void _clk_main_bus_recalc(struct clk *clk) +{ + clk->rate = clk->parent->rate; +} + +static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, stat; + + if (emi_fast_clk.usecount == 0) + emi_fast_clk.enable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.enable(&emi_slow_clk); + if (emi_intr_clk.usecount == 0) + emi_intr_clk.enable(&emi_intr_clk); + + if (parent == &pll2_sw_clk) { + reg = __raw_readl(MXC_CCM_CBCDR6) & + ~MXC_CCM_CBCDR6_PERIPH_CLK_SEL; + } else if (parent == &periph_apm_clk) { + reg = __raw_readl(MXC_CCM_CBCDR6) | + MXC_CCM_CBCDR6_PERIPH_CLK_SEL; + } else { + return -EINVAL; + } + __raw_writel(reg, MXC_CCM_CBCDR6); + + /* Set the Load-dividers bit in CCM */ + reg = __raw_readl(MXC_CCM_CCDR); + reg |= MXC_CCM_CCDR_LOAD_DIVIDERS; + __raw_writel(reg, MXC_CCM_CCDR); + + do { + stat = __raw_readl(MXC_CCM_CCDR) & MXC_CCM_CCDR_LOAD_DIVIDERS; + } while (stat); + + if (emi_fast_clk.usecount == 0) + emi_fast_clk.disable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.disable(&emi_slow_clk); + if (emi_intr_clk.usecount == 0) + emi_intr_clk.disable(&emi_intr_clk); + + return 0; +} + +static struct clk main_bus_clk = { + .name = "main_bus_clk", + .parent = &pll2_sw_clk, + .set_parent = _clk_main_bus_set_parent, + .recalc = _clk_main_bus_recalc, + .flags = RATE_PROPAGATES, +}; + +static int _clk_axi_a_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, stat; + + div = clk->parent->rate / rate; + if (div == 0) + div++; + if (((clk->parent->rate / div) != rate) || (div > 8)) + return -EINVAL; + + if (ddr_clk.parent == &axi_a_clk && emi_fast_clk.usecount == 0) + emi_fast_clk.enable(&emi_fast_clk); + + reg = __raw_readl(MXC_CCM_CBCDR3); + reg &= ~MXC_CCM_CBCDR3_AXI_A_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR3_AXI_A_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR3); + + /* Set the Load-dividers bit in CCM */ + reg = __raw_readl(MXC_CCM_CCDR); + reg |= MXC_CCM_CCDR_LOAD_DIVIDERS; + __raw_writel(reg, MXC_CCM_CCDR); + + do { + stat = __raw_readl(MXC_CCM_CCDR) & MXC_CCM_CCDR_LOAD_DIVIDERS; + } while (stat); + clk->rate = rate; + + if (ddr_clk.parent == &axi_a_clk && emi_fast_clk.usecount == 0) + emi_fast_clk.disable(&emi_fast_clk); + + return 0; +} + +static void _clk_axi_a_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR3); + div = ((reg & MXC_CCM_CBCDR3_AXI_A_PODF_MASK) >> + MXC_CCM_CBCDR3_AXI_A_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + +static unsigned long _clk_axi_a_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return clk->parent->rate / div; +} + +static struct clk axi_a_clk = { + .name = "axi_a_clk", + .parent = &main_bus_clk, + .recalc = _clk_axi_a_recalc, + .set_rate = _clk_axi_a_set_rate, + .round_rate = _clk_axi_a_round_rate, + .flags = RATE_PROPAGATES, +}; + +static int _clk_axi_b_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, stat; + + div = clk->parent->rate / rate; + if (div == 0) + div++; + if (((clk->parent->rate / div) != rate) || (div > 8)) + return -EINVAL; + + if (ddr_clk.parent == &axi_b_clk && emi_fast_clk.usecount == 0) + emi_fast_clk.enable(&emi_fast_clk); + + reg = __raw_readl(MXC_CCM_CBCDR4); + reg &= ~MXC_CCM_CBCDR4_AXI_B_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR4_AXI_B_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR4); + + /* Set the Load-dividers bit in CCM */ + reg = __raw_readl(MXC_CCM_CCDR); + reg |= MXC_CCM_CCDR_LOAD_DIVIDERS; + __raw_writel(reg, MXC_CCM_CCDR); + + do { + stat = __raw_readl(MXC_CCM_CCDR) & MXC_CCM_CCDR_LOAD_DIVIDERS; + } while (stat); + clk->rate = rate; + + if (ddr_clk.parent == &axi_c_clk && emi_fast_clk.usecount == 0) + emi_fast_clk.disable(&emi_fast_clk); + + return 0; +} + +static void _clk_axi_b_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR4); + div = ((reg & MXC_CCM_CBCDR4_AXI_B_PODF_MASK) >> + MXC_CCM_CBCDR4_AXI_B_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + +static unsigned long _clk_axi_b_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return clk->parent->rate / div; +} + +static struct clk axi_b_clk = { + .name = "axi_b_clk", + .parent = &main_bus_clk, + .recalc = _clk_axi_b_recalc, + .set_rate = _clk_axi_b_set_rate, + .round_rate = _clk_axi_b_round_rate, + .flags = RATE_PROPAGATES, +}; + +static int _clk_axi_c_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, stat; + + div = clk->parent->rate / rate; + if (div == 0) + div++; + if (((clk->parent->rate / div) != rate) || (div > 8)) + return -EINVAL; + + if (ddr_clk.parent == &axi_c_clk && emi_fast_clk.usecount == 0) + emi_fast_clk.enable(&emi_fast_clk); + + reg = __raw_readl(MXC_CCM_CBCDR5); + reg &= ~MXC_CCM_CBCDR5_AXI_C_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR5_AXI_C_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR5); + + /* Set the Load-dividers bit in CCM */ + reg = __raw_readl(MXC_CCM_CCDR); + reg |= MXC_CCM_CCDR_LOAD_DIVIDERS; + __raw_writel(reg, MXC_CCM_CCDR); + + do { + stat = __raw_readl(MXC_CCM_CCDR) & MXC_CCM_CCDR_LOAD_DIVIDERS; + } while (stat); + clk->rate = rate; + + if (ddr_clk.parent == &axi_c_clk && emi_fast_clk.usecount == 0) + emi_fast_clk.disable(&emi_fast_clk); + + return 0; +} + +static void _clk_axi_c_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR5); + div = ((reg & MXC_CCM_CBCDR5_AXI_C_PODF_MASK) >> + MXC_CCM_CBCDR5_AXI_C_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + +static unsigned long _clk_axi_c_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return clk->parent->rate / div; +} + +static struct clk axi_c_clk = { + .name = "axi_c_clk", + .parent = &main_bus_clk, + .recalc = _clk_axi_c_recalc, + .set_rate = _clk_axi_c_set_rate, + .round_rate = _clk_axi_c_round_rate, + .flags = RATE_PROPAGATES, +}; + +static void _clk_ahb_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR2); + div = ((reg & MXC_CCM_CBCDR2_AHB_PODF_MASK) >> + MXC_CCM_CBCDR2_AHB_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + +static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + + div = clk->parent->rate / rate; + if (div == 0) + div++; + if (((clk->parent->rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CBCDR2); + reg &= ~MXC_CCM_CBCDR2_AHB_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR2_AHB_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR2); + clk->rate = rate; + + return 0; +} + +static unsigned long _clk_ahb_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return clk->parent->rate / div; +} + +static struct clk ahb_clk = { + .name = "ahb_clk", + .parent = &main_bus_clk, + .recalc = _clk_ahb_recalc, + .set_rate = _clk_ahb_set_rate, + .round_rate = _clk_ahb_round_rate, + .flags = RATE_PROPAGATES, +}; + +static struct clk ahb_max_clk = { + .name = "max_clk", + .parent = &ahb_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGR0_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, +}; + +static int _clk_emi_core_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, stat; + + div = clk->parent->rate / rate; + if (div == 0) + div++; + if (((clk->parent->rate / div) != rate) || (div > 8)) + return -EINVAL; + + if (emi_fast_clk.usecount == 0) + emi_fast_clk.enable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.enable(&emi_slow_clk); + if (emi_intr_clk.usecount == 0) + emi_intr_clk.enable(&emi_intr_clk); + + reg = __raw_readl(MXC_CCM_CBCDR6); + reg &= ~MXC_CCM_CBCDR6_EMI_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR6_EMI_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR6); + + /* Set the Load-dividers bit in CCM */ + reg = __raw_readl(MXC_CCM_CCDR); + reg |= MXC_CCM_CCDR_LOAD_DIVIDERS; + __raw_writel(reg, MXC_CCM_CCDR); + + do { + stat = __raw_readl(MXC_CCM_CCDR) & MXC_CCM_CCDR_LOAD_DIVIDERS; + } while (stat); + + clk->rate = rate; + + if (emi_fast_clk.usecount == 0) + emi_fast_clk.disable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.disable(&emi_slow_clk); + if (emi_intr_clk.usecount == 0) + emi_intr_clk.disable(&emi_intr_clk); + + return 0; +} + +static void _clk_emi_core_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR6); + div = ((reg & MXC_CCM_CBCDR6_EMI_PODF_MASK) >> + MXC_CCM_CBCDR6_EMI_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + +static int _clk_emi_core_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CBCDR6); + if (parent == &ahb_clk) { + reg |= MXC_CCM_CBCDR6_EMI_CLK_SEL; + } else if (parent == &main_bus_clk) { + reg &= ~MXC_CCM_CBCDR6_EMI_CLK_SEL; + } else { + BUG(); + } + __raw_writel(reg, MXC_CCM_CBCDR6); + + return 0; +} + +static unsigned long _clk_emi_core_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return clk->parent->rate / div; +} + +static struct clk emi_core_clk = { + .name = "emi_core_clk", + .set_parent = _clk_emi_core_set_parent, + .recalc = _clk_emi_core_recalc, + .set_rate = _clk_emi_core_set_rate, + .round_rate = _clk_emi_core_round_rate, + .flags = RATE_PROPAGATES, +}; + +static struct clk ahbmux1_clk = { + .name = "ahbmux1_clk", + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG4_OFFSET, + .disable = _clk_disable_inwait, +}; + +static struct clk ahbmux2_clk = { + .name = "ahbmux2_clk", + .id = 0, + .parent = &emi_core_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGR0_CG7_OFFSET, + .disable = _clk_disable_inwait, +}; + +static struct clk emi_fast_clk = { + .name = "emi_fast_clk", + .parent = &emi_core_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG12_OFFSET, + .disable = _clk_disable_inwait, +}; + +static struct clk emi_slow_clk = { + .name = "emi_slow_clk", + .parent = &emi_core_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG13_OFFSET, + .disable = _clk_disable_inwait, +}; + +static struct clk emi_intr_clk = { + .name = "emi_intr_clk", + .parent = &emi_core_clk, + .secondary = &ahbmux2_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG14_OFFSET, + .disable = _clk_disable_inwait, +}; + +static void _clk_ipg_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR2); + div = ((reg & MXC_CCM_CBCDR2_IPG_PODF_MASK) >> + MXC_CCM_CBCDR2_IPG_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + +static struct clk ipg_clk = { + .name = "ipg_clk", + .parent = &ahb_clk, + .recalc = _clk_ipg_recalc, + .flags = RATE_PROPAGATES, +}; + +static void _clk_ipg_per_recalc(struct clk *clk) +{ + u32 reg, prediv1, prediv2, podf; + + if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) { + /* the main_bus_clk is the one before the DVFS engine */ + reg = __raw_readl(MXC_CCM_CBCDR2); + prediv1 = ((reg & MXC_CCM_CBCDR2_PERCLK_PRED1_MASK) >> + MXC_CCM_CBCDR2_PERCLK_PRED1_OFFSET) + 1; + prediv2 = ((reg & MXC_CCM_CBCDR2_PERCLK_PRED2_MASK) >> + MXC_CCM_CBCDR2_PERCLK_PRED2_OFFSET) + 1; + podf = ((reg & MXC_CCM_CBCDR2_PERCLK_PODF_MASK) >> + MXC_CCM_CBCDR2_PERCLK_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / (prediv1 * prediv2 * podf); + } else if (clk->parent == &ipg_clk) { + clk->rate = ipg_clk.rate; + } else { + BUG(); + } +} + +static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR1); + mux = _get_mux(parent, &main_bus_clk, &lp_apm_clk, &ipg_clk, NULL); + if (mux == 2) { + reg |= MXC_CCM_CSCMR1_PERCLK_IPG_CLK_SEL; + } else { + reg &= ~MXC_CCM_CSCMR1_PERCLK_IPG_CLK_SEL; + if (mux == 0) { + reg &= ~MXC_CCM_CSCMR1_PERCLK_LP_APM_CLK_SEL; + } else { + reg |= MXC_CCM_CSCMR1_PERCLK_LP_APM_CLK_SEL; + } + } + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ipg_perclk = { + .name = "ipg_perclk", + .parent = &ipg_clk, + .recalc = _clk_ipg_per_recalc, + .set_parent = _clk_ipg_per_set_parent, + .flags = RATE_PROPAGATES, +}; + +static struct clk aips_tz1_clk = { + .name = "aips_tz1_clk", + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGR0_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, +}; + +static struct clk aips_tz2_clk = { + .name = "aips_tz2_clk", + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGR0_CG14_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, +}; + +static struct clk sdma_clk[] = { + { + .name = "sdma_ahb_clk", + .parent = &ahb_clk, + .secondary = &emi_fast_clk, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG0_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "sdma_ipg_clk", + .parent = &ipg_clk, +#ifdef CONFIG_SDMA_IRAM + .secondary = &emi_intr_clk, +#endif + }, +}; + +static int _clk_tve_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + + if (parent == &pll3_sw_clk) { + reg &= ~(MXC_CCM_CSCMR1_TVE_CLK_SEL); + } else if (parent == &osc_clk) { + reg |= MXC_CCM_CSCMR1_TVE_CLK_SEL; + reg &= MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL; + } else if (parent == &ckih_clk) { + reg |= MXC_CCM_CSCMR1_TVE_CLK_SEL; + reg |= MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL; + } else { + BUG(); + } + + __raw_writel(reg, MXC_CCM_CSCMR1); + return 0; +} + +static void _clk_tve_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if ((reg & MXC_CCM_CSCMR1_TVE_CLK_SEL) == 0) { + reg = __raw_readl(MXC_CCM_CDCDR) & + MXC_CCM_CDCDR_TVE_CLK_PRED_MASK; + div = (reg >> MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET) + 1; + clk->rate = clk->parent->rate / div; + } else { + clk->rate = clk->parent->rate; + } +} + +static unsigned long _clk_tve_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (reg & MXC_CCM_CSCMR1_TVE_CLK_SEL) { + return -EINVAL; + } + + div = clk->parent->rate / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return clk->parent->rate / div; +} + +static int _clk_tve_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (reg & MXC_CCM_CSCMR1_TVE_CLK_SEL) { + return -EINVAL; + } + + div = clk->parent->rate / rate; + if (div == 0) + div++; + if (((clk->parent->rate / div) != rate) || (div > 8)) { + return -EINVAL; + } + + div--; + reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_TVE_CLK_PRED_MASK; + reg |= div << MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CDCDR); + clk->rate = rate; + return 0; +} + +static struct clk tve_clk = { + .name = "tve_clk", + .parent = &pll3_sw_clk, + .secondary = &aips_tz1_clk, + .set_parent = _clk_tve_set_parent, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGR0_CG10_OFFSET, + .recalc = _clk_tve_recalc, + .round_rate = _clk_tve_round_rate, + .set_rate = _clk_tve_set_rate, + .enable = _clk_enable, + .disable = _clk_disable, + .flags = RATE_PROPAGATES, +}; + +static struct clk spba_clk = { + .name = "spba_clk", + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG1_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static void _clk_uart_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static int _clk_uart_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, post_div = 1; + + div = clk->parent->rate / rate; + if (div == 0) + div++; + if (((clk->parent->rate / div) != rate) || (div > 64) || (div == 1)) + return -EINVAL; + + if (div > 8) { + int i = 1; + while ((div / (2 * i)) > 8) + i++; + post_div = i * 2; + div = div / post_div; + } + + reg = __raw_readl(MXC_CCM_CSCDR1); + reg &= ~MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; + reg &= ~MXC_CCM_CSCDR1_UART_CLK_PRED_MASK; + reg |= (div - 1) << MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET | + (post_div - 1) << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR1); + clk->rate = rate; + + return 0; +} + +static unsigned long _clk_uart_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + if (div > 64) + div = 64; + else if (div == 0) + div++; + return clk->parent->rate / div; +} + +static struct clk uart_main_clk = { + .name = "uart_main_clk", + .parent = &pll2_sw_clk, + .recalc = _clk_uart_recalc, + .set_parent = _clk_uart_set_parent, + .set_rate = _clk_uart_set_rate, + .round_rate = _clk_uart_round_rate, + .flags = RATE_PROPAGATES, +}; + +static struct clk uart1_clk[] = { + { + .name = "uart_clk", + .id = 0, + .parent = &uart_main_clk, + .secondary = &uart1_clk[1], + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG5_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "uart_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .secondary = &aips_tz2_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG4_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk uart2_clk[] = { + { + .name = "uart_clk", + .id = 1, + .parent = &uart_main_clk, + .secondary = &uart2_clk[1], + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "uart_ipg_clk", + .id = 1, + .parent = &ipg_clk, + .secondary = &aips_tz2_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk uart3_clk[] = { + { + .name = "uart_clk", + .id = 2, + .parent = &uart_main_clk, + .secondary = &uart3_clk[1], + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "uart_ipg_clk", + .id = 2, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk gpt_clk[] = { + { + .name = "gpt_clk", + .parent = &ipg_clk, + .id = 0, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "gpt_ipg_clk", + .id = 0, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "gpt_32k_clk", + .id = 0, + .parent = &ckil_clk, + }, +}; + +static struct clk i2c_clk[] = { + { + .name = "i2c_clk", + .id = 0, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG14_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "i2c_clk", + .id = 1, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG15_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "i2c_clk", + .id = 2, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG0_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static void _clk_cspi_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR2); + prediv = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >> + MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >> + MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static int _clk_cspi_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static int _clk_cspi_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, post_div = 1; + + div = clk->parent->rate / rate; + if (div == 0) + div++; + if (((clk->parent->rate / div) != rate) || (div > 512) || (div == 1)) + return -EINVAL; + + if (div > 8) { + int i = 1; + while ((div / (2 * i)) > 8) + i++; + post_div = i * 2; + div = div / post_div; + } + + reg = __raw_readl(MXC_CCM_CSCDR2); + reg &= ~MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK; + reg &= ~MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK; + reg |= (div - 1) << MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET; + reg |= (post_div - 1) << MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR2); + clk->rate = rate; + + return 0; +} + +static unsigned long _clk_cspi_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + if (div > 512) + div = 8; + else if (div == 1) + div = 2; + else if (div == 0) + div++; + return clk->parent->rate / div; +} + +static struct clk cspi_main_clk = { + .name = "cspi_main_clk", + .parent = &pll3_sw_clk, + .recalc = _clk_cspi_recalc, + .set_parent = _clk_cspi_set_parent, + .set_rate = _clk_cspi_set_rate, + .round_rate = _clk_cspi_round_rate, + .flags = RATE_PROPAGATES, +}; + +static struct clk cspi1_clk[] = { + { + .name = "cspi_clk", + .id = 0, + .parent = &cspi_main_clk, + .secondary = &cspi1_clk[1], + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "cspi_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .secondary = &aips_tz2_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk cspi2_clk[] = { + { + .name = "cspi_clk", + .id = 1, + .parent = &cspi_main_clk, + .secondary = &cspi2_clk[1], + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "cspi_ipg_clk", + .id = 1, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk cspi3_clk[] = { + { + .name = "cspi_clk", + .id = 2, + .parent = &cspi_main_clk, + .secondary = &cspi3_clk[1], + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "cspi_ipg_clk", + .id = 2, + .parent = &ipg_clk, + .secondary = &aips_tz2_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static int _clk_ssi_lp_apm_set_parent(struct clk *clk, + struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + + if (parent == &ckih_clk) { + reg &= ~MXC_CCM_CSCMR1_SSI_APM_CLK_SEL; + } else if (parent == &lp_apm_clk) { + reg |= MXC_CCM_CSCMR1_SSI_APM_CLK_SEL; + } else { + BUG(); + } + + __raw_writel(reg, MXC_CCM_CSCMR1); + return 0; +} + +static struct clk ssi_lp_apm_clk = { + .name = "ssi_lp_apm_clk", + .parent = &ckih_clk, + .set_parent = _clk_ssi_lp_apm_set_parent, +}; + +static void _clk_ssi1_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CS1CDR); + prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK) >> + MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK) >> + MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} +static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, + &pll3_sw_clk, &ssi_lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi1_clk[] = { + { + .name = "ssi_clk", + .id = 0, + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi1_set_parent, + .secondary = &ssi1_clk[1], + .recalc = _clk_ssi1_recalc, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "ssi_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .secondary = &ssi1_clk[2], + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "ssi_dep_clk", + .id = 0, + .parent = &aips_tz2_clk, +#ifdef CONFIG_SND_MXC_SOC_IRAM + .secondary = &emi_intr_clk, +#else + .secondary = &emi_fast_clk, +#endif + }, +}; + +static void _clk_ssi2_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CS2CDR); + prediv = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK) >> + MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK) >> + MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, + &pll3_sw_clk, &ssi_lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi2_clk[] = { + { + .name = "ssi_clk", + .id = 1, + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi2_set_parent, + .secondary = &ssi2_clk[1], + .recalc = _clk_ssi2_recalc, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "ssi_ipg_clk", + .id = 1, + .parent = &ipg_clk, + .secondary = &ssi2_clk[2], + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "ssi_dep_clk", + .id = 1, + .parent = &spba_clk, +#ifdef CONFIG_SND_MXC_SOC_IRAM + .secondary = &emi_intr_clk, +#else + .secondary = &emi_fast_clk, +#endif + }, +}; + +static void _clk_ssi_ext1_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + clk->rate = clk->parent->rate; + reg = __raw_readl(MXC_CCM_CSCMR1); + if ((reg & MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL) == 0) { + reg = __raw_readl(MXC_CCM_CSECDR1); + prediv = ((reg & MXC_CCM_CSECDR1_SSI_EXT1_CLK_PRED_MASK) >> + MXC_CCM_CSECDR1_SSI_EXT1_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CSECDR1_SSI_EXT1_CLK_PODF_MASK) >> + MXC_CCM_CSECDR1_SSI_EXT1_CLK_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / (prediv * podf); + } +} + +static int _clk_ssi_ext1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &ssi1_clk[0]) { + reg |= MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL; + } else { + reg &= ~MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL; + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &ssi_lp_apm_clk); + reg = (reg & ~MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET); + } + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi_ext1_clk = { + .name = "ssi_ext1_clk", + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi_ext1_set_parent, + .recalc = _clk_ssi_ext1_recalc, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static void _clk_ssi_ext2_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + clk->rate = clk->parent->rate; + reg = __raw_readl(MXC_CCM_CSCMR1); + if ((reg & MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL) == 0) { + reg = __raw_readl(MXC_CCM_CSECDR2); + prediv = ((reg & MXC_CCM_CSECDR2_SSI_EXT2_CLK_PRED_MASK) >> + MXC_CCM_CSECDR2_SSI_EXT2_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CSECDR2_SSI_EXT2_CLK_PODF_MASK) >> + MXC_CCM_CSECDR2_SSI_EXT2_CLK_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / (prediv * podf); + } +} + +static int _clk_ssi_ext2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &ssi2_clk[0]) { + reg |= MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL; + } else { + reg &= ~MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL; + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &ssi_lp_apm_clk); + reg = (reg & ~MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET); + } + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi_ext2_clk = { + .name = "ssi_ext2_clk", + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi_ext2_set_parent, + .recalc = _clk_ssi_ext2_recalc, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk iim_clk = { + .name = "iim_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGR0_CG15_OFFSET, + .disable = _clk_disable, +}; + +static struct clk tmax1_clk = { + .name = "tmax1_clk", + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG0_OFFSET, + .disable = _clk_disable, +}; + +static struct clk tmax2_clk = { + .name = "tmax2_clk", + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG1_OFFSET, + .disable = _clk_disable, +}; + +static void _clk_usboh2_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_USBOH2_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_USBOH2_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CSCDR1_USBOH2_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_USBOH2_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static int _clk_usboh2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH2_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_USBOH2_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +/* + * This is USB core clock. + ** need access DDR/iram, TMAX + */ +static struct clk usb_core_clk[] = { + { + .name = "usb_ahb_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG11_OFFSET, + .disable = _clk_disable, + .secondary = &usb_core_clk[1], + }, + { + .name = "usb_tmax_clk", + .parent = &tmax1_clk, + .secondary = &usb_core_clk[2], + }, + { + .name = "usb_ddr_clk", + .parent = &emi_fast_clk, +#if defined CONFIG_USB_STATIC_IRAM_PPH || defined CONFIG_USB_STATIC_IRAM + .secondary = &usb_core_clk[3], +#endif + }, + /* iram patch, need access internal ram */ + { + .name = "usb_iram_clk", + .parent = &emi_intr_clk, + }, +}; + +/* used for connecting external PHY */ +static struct clk usboh2_clk = { + .name = "usboh2_clk", + .parent = &pll3_sw_clk, + .set_parent = _clk_usboh2_set_parent, + .recalc = _clk_usboh2_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG12_OFFSET, + .disable = _clk_disable, +}; + +static void _clk_usb_phy_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + if (clk->parent == &pll3_sw_clk) { + reg = __raw_readl(MXC_CCM_CDCDR); + prediv = ((reg & MXC_CCM_CDCDR_USB_PHY_PRED_MASK) >> + MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CDCDR_USB_PHY_PODF_MASK) >> + MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); + } else + clk->rate = clk->parent->rate; +} + +static int _clk_usb_phy_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &osc_clk) { + reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; + } else if (parent == &pll3_sw_clk) { + reg |= MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; + } else { + BUG(); + } + + __raw_writel(reg, MXC_CCM_CSCMR1); + return 0; +} + +static struct clk usb_phy_clk = { + .name = "usb_phy_clk", + .parent = &osc_clk, + .set_parent = _clk_usb_phy_set_parent, + .recalc = _clk_usb_phy_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGR0_CG6_OFFSET, + .disable = _clk_disable, +}; + +static struct clk esdhc_dep_clks = { + .name = "sd_dep_clk", + .parent = &spba_clk, + .secondary = &emi_fast_clk, +}; + + +static void _clk_esdhc1_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static int _clk_esdhc1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & + ~MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk esdhc1_clk[] = { + { + .name = "esdhc_clk", + .id = 0, + .parent = &pll3_sw_clk, + .set_parent = _clk_esdhc1_set_parent, + .recalc = _clk_esdhc1_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG14_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc1_clk[1], + }, + { + .name = "esdhc_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG13_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc1_clk[2], + }, + { + .name = "esdhc1_sec_clk", + .parent = &tmax2_clk, + .secondary = &esdhc_dep_clks, + }, +}; + +static void _clk_esdhc2_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static int _clk_esdhc2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & + ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk esdhc2_clk[] = { + { + .name = "esdhc_clk", + .id = 1, + .parent = &pll3_sw_clk, + .set_parent = _clk_esdhc2_set_parent, + .recalc = _clk_esdhc2_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG0_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc2_clk[1], + }, + { + .name = "esdhc_ipg_clk", + .id = 1, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG15_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc2_clk[2], + }, + { + .name = "esdhc2_sec_clk", + .parent = &ahb_max_clk, + .secondary = &esdhc_dep_clks, + }, +}; + +static int _clk_esdhc3_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &esdhc1_clk[0]) { + reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL; + } else if (parent == &esdhc2_clk[0]) { + reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL; + } else { + BUG(); + } + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk esdhc3_clk[] = { + { + .name = "esdhc_clk", + .id = 2, + .parent = &esdhc1_clk[0], + .set_parent = _clk_esdhc3_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG2_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc3_clk[1], + }, + { + .name = "esdhc_ipg_clk", + .id = 2, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG1_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc3_clk[2], + }, + { + .name = "esdhc3_sec_clk", + .parent = &ahb_max_clk, + .secondary = &esdhc_dep_clks, + }, + +}; + +static void _clk_nfc_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR7); + div = ((reg & MXC_CCM_CBCDR7_NFC_PODF_MASK) >> + MXC_CCM_CBCDR7_NFC_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + +static int _clk_nfc_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, stat; + + div = clk->parent->rate / rate; + if (div == 0) + div++; + if (((clk->parent->rate / div) != rate) || (div > 8)) + return -EINVAL; + + if (emi_fast_clk.usecount == 0) + emi_fast_clk.enable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.enable(&emi_slow_clk); + if (emi_intr_clk.usecount == 0) + emi_intr_clk.enable(&emi_intr_clk); + + reg = __raw_readl(MXC_CCM_CBCDR7); + reg &= ~MXC_CCM_CBCDR7_NFC_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR7_NFC_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR7); + + /* Set the Load-dividers bit in CCM */ + reg = __raw_readl(MXC_CCM_CCDR); + reg |= MXC_CCM_CCDR_LOAD_DIVIDERS; + __raw_writel(reg, MXC_CCM_CCDR); + + do { + stat = __raw_readl(MXC_CCM_CCDR) & MXC_CCM_CCDR_LOAD_DIVIDERS; + } while (stat); + clk->rate = rate; + + if (emi_fast_clk.usecount == 0) + emi_fast_clk.disable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.disable(&emi_slow_clk); + if (emi_intr_clk.usecount == 0) + emi_intr_clk.disable(&emi_intr_clk); + + return 0; +} + +static unsigned long _clk_nfc_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return clk->parent->rate / div; +} + +static struct clk nfc_clk = { + .name = "nfc_clk", + .parent = &emi_core_clk, + .secondary = &emi_slow_clk, + .recalc = _clk_nfc_recalc, + .set_rate = _clk_nfc_set_rate, + .round_rate = _clk_nfc_round_rate, +}; + +static int _clk_spdif_xtal_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &osc_clk) { + reg &= ~MXC_CCM_CSCMR1_SPDIF_CLK_SEL; + } else if (parent == &ckih_clk) { + reg |= MXC_CCM_CSCMR1_SPDIF_CLK_SEL; + } else { + BUG(); + } + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk spdif_xtal_clk = { + .name = "spdif_xtal_clk", + .parent = &osc_clk, + .set_parent = _clk_spdif_xtal_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG10_OFFSET, + .disable = _clk_disable, +}; + +static int _clk_spdif0_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR2); + reg |= MXC_CCM_CSCMR2_SPDIF0_COM; + if (parent != &ssi1_clk[0]) { + reg &= ~MXC_CCM_CSCMR2_SPDIF0_COM; + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &spdif_xtal_clk); + reg = (reg & ~MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET); + } + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static void _clk_spdif0_recalc(struct clk *clk) +{ + u32 reg, pred, podf; + + if (clk->parent == &ssi1_clk[0]) { + clk->rate = clk->parent->rate; + } else { + reg = __raw_readl(MXC_CCM_CDCDR); + pred = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK) >> + MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK) >> + MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / (pred * podf); + } +} + +static struct clk spdif0_clk[] = { + { + .name = "spdif_clk", + .id = 0, + .parent = &pll3_sw_clk, + .secondary = &spdif0_clk[1], + .set_parent = _clk_spdif0_set_parent, + .recalc = _clk_spdif0_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG11_OFFSET, + .disable = _clk_disable, + }, + { + .name = "spdif_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG10_OFFSET, + .disable = _clk_disable, + }, +}; + +static int _clk_spdif1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR2); + reg |= MXC_CCM_CSCMR2_SPDIF1_COM; + if (parent != &ssi2_clk[0]) { + reg &= ~MXC_CCM_CSCMR2_SPDIF1_COM; + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &spdif_xtal_clk); + reg = (reg & ~MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET); + } + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static void _clk_spdif1_recalc(struct clk *clk) +{ + u32 reg, pred, podf; + + if (clk->parent == &ssi2_clk[0]) { + clk->rate = clk->parent->rate; + } else { + reg = __raw_readl(MXC_CCM_CDCDR); + pred = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK) >> + MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK) >> + MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / (pred * podf); + } +} + +static struct clk spdif1_clk[] = { + { + .name = "spdif_clk", + .id = 1, + .parent = &pll3_sw_clk, + .secondary = &spdif1_clk[1], + .set_parent = _clk_spdif1_set_parent, + .recalc = _clk_spdif1_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG12_OFFSET, + .disable = _clk_disable, + }, + { + .name = "spdif_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG10_OFFSET, + .disable = _clk_disable, + }, +}; + +static int _clk_ipu_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + /* Handshake with IPU when certain clock rates are changed. */ + reg = __raw_readl(MXC_CCM_CCDR); + reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; + __raw_writel(reg, MXC_CCM_CCDR); + return 0; +} + +static void _clk_ipu_disable(struct clk *clk) +{ + u32 reg; + _clk_disable(clk); + + /* No handshake with IPU as its not enabled. */ + reg = __raw_readl(MXC_CCM_CCDR); + reg |= MXC_CCM_CCDR_IPU_HS_MASK; + __raw_writel(reg, MXC_CCM_CCDR); +} + +static int _clk_ipu_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + reg = __raw_readl(MXC_CCM_CAMR); + mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &axi_c_clk, + &emi_core_clk); + reg = (reg & ~MXC_CCM_CAMR_IPU_HSP_CLK_SEL_MASK) | + (mux << MXC_CCM_CAMR_IPU_HSP_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CAMR); + + return 0; +} + +static struct clk ipu_clk[] = { + { + .name = "ipu_clk", + .parent = &axi_a_clk, + .secondary = &ipu_clk[1], + .set_parent = _clk_ipu_set_parent, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG15_OFFSET, + .enable = _clk_ipu_enable, + .disable = _clk_ipu_disable, + .flags = CPU_FREQ_TRIG_UPDATE, + }, + { + .name = "ipu_sec_clk", + .parent = &emi_fast_clk, + .secondary = &ahbmux1_clk, + } +}; + +static int _clk_ipu_di_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + if (parent == &tve_clk) { + mxc_iomux_set_gpr(MUX_IPUv3D_CAMP, false, 0); + } else if (parent == &ckih_clk) { + mxc_iomux_set_gpr(MUX_IPUv3D_CAMP, true, 0); + reg = __raw_readl(MXC_CCM_CSCMR1); + reg |= MXC_CCM_CSCMR1_DI_CLK_SEL; + __raw_writel(reg, MXC_CCM_CSCMR1); + } else if (parent == &osc_clk) { + mxc_iomux_set_gpr(MUX_IPUv3D_CAMP, true, 0); + reg = __raw_readl(MXC_CCM_CSCMR1); + reg &= ~MXC_CCM_CSCMR1_DI_CLK_SEL; + __raw_writel(reg, MXC_CCM_CSCMR1); + } else { + return -EINVAL; + } + + return 0; +} + +static void _clk_ipu_di_recalc(struct clk *clk) +{ + if (clk->parent == &tve_clk) { + clk->rate = clk->parent->rate / 8; + } else { + clk->rate = clk->parent->rate; + } +} + +static struct clk ipu_di_clk = { + .name = "ipu_di_clk", + .parent = &tve_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG14_OFFSET, + .recalc = _clk_ipu_di_recalc, + .set_parent = _clk_ipu_di_set_parent, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static int _clk_ddr_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + reg = __raw_readl(MXC_CCM_CAMR); + mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &axi_c_clk, + &emi_core_clk); + reg = (reg & ~MXC_CCM_CAMR_DDR_CLK_SEL_MASK) | + (mux << MXC_CCM_CAMR_DDR_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CAMR); + + return 0; +} + +static struct clk ddr_clk = { + .name = "ddr_clk", + .parent = &axi_c_clk, + .set_parent = _clk_ddr_set_parent, +}; + +static int _clk_arm_axi_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + reg = __raw_readl(MXC_CCM_CAMR); + mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &axi_c_clk, + &emi_core_clk); + reg = (reg & ~MXC_CCM_CAMR_ARM_AXI_CLK_SEL_MASK) | + (mux << MXC_CCM_CAMR_ARM_AXI_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CAMR); + + return 0; +} + +static struct clk arm_axi_clk = { + .name = "arm_axi_clk", + .parent = &axi_a_clk, + .set_parent = _clk_arm_axi_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGR0_CG1_OFFSET, + .disable = _clk_disable, +}; + +static int _clk_vpu_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + reg = __raw_readl(MXC_CCM_CAMR); + mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &axi_c_clk, + &emi_core_clk); + reg = (reg & ~MXC_CCM_CAMR_VPU_AXI_CLK_SEL_MASK) | + (mux << MXC_CCM_CAMR_VPU_AXI_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CAMR); + + return 0; +} + +static int _clk_vpu_core_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + reg = __raw_readl(MXC_CCM_CAMR); + mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &axi_c_clk, + &emi_core_clk); + reg = (reg & ~MXC_CCM_CAMR_VPU_CLK_SEL_MASK) | + (mux << MXC_CCM_CAMR_VPU_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CAMR); + + return 0; +} + +static struct clk vpu_clk[] = { + { + .name = "vpu_clk", + .parent = &axi_a_clk, + .set_parent = _clk_vpu_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG7_OFFSET, + .disable = _clk_disable, + .secondary = &vpu_clk[1], + .flags = CPU_FREQ_TRIG_UPDATE, + }, + { + .name = "vpu_core_clk", + .parent = &axi_a_clk, + .secondary = &vpu_clk[2], + .set_parent = _clk_vpu_core_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG6_OFFSET, + .disable = _clk_disable, + }, + { + .name = "vpu_emi_clk", + .parent = &emi_fast_clk, +#ifdef CONFIG_MXC_VPU_IRAM + .secondary = &emi_intr_clk, +#endif + } +}; + +static int _clk_lpsr_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + reg = __raw_readl(MXC_CCM_CLPCR); + mux = _get_mux(parent, &ckil_clk, &fpm_clk, &fpm_div2_clk, NULL); + reg = (reg & ~MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK) | + (mux << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CLPCR); + + return 0; +} + +static struct clk lpsr_clk = { + .name = "lpsr_clk", + .parent = &ckil_clk, + .set_parent = _clk_lpsr_set_parent, +}; + +static void _clk_pgc_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCDR1); + div = (reg & MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET; + div = 1 >> div; + clk->rate = clk->parent->rate / div; +} + +static struct clk pgc_clk = { + .name = "pgc_clk", + .parent = &ipg_clk, + .recalc = _clk_pgc_recalc, +}; + +/*usb OTG clock */ +/*Notes: in mx37, usb clock get from UTMI PHY, always 60MHz*/ + +static struct clk usb_clk = { + .name = "usb_clk", + .rate = 60000000, +}; + +static struct clk rtc_clk = { + .name = "rtc_clk", + .parent = &ckil_clk, + .secondary = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG13_OFFSET, + .disable = _clk_disable, +}; + +static struct clk ata_clk = { + .name = "ata_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG14_OFFSET, + .disable = _clk_disable, +}; + +static struct clk rng_clk = { + .name = "rng_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG5_OFFSET, + .disable = _clk_disable, +}; + +static struct clk scc_clk = { + .name = "scc_clk", + .parent = &ipg_clk, + .secondary = &emi_fast_clk, +}; + +static void cko1_recalc(struct clk *clk) +{ + unsigned long rate; + u32 reg; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= MXC_CCM_CCOSR_CKOL_DIV_MASK; + reg = reg >> MXC_CCM_CCOSR_CKOL_DIV_OFFSET; + rate = clk->parent->rate; + clk->rate = rate / (reg + 1); +} + +static int cko1_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg |= MXC_CCM_CCOSR_CKOL_EN; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; +} + +static void cko1_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MXC_CCM_CCOSR_CKOL_EN; + __raw_writel(reg, MXC_CCM_CCOSR); +} + +static int cko1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + + div = (clk->parent->rate/rate - 1) & 0x7; + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK; + reg |= div << MXC_CCM_CCOSR_CKOL_DIV_OFFSET; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; +} + +static unsigned long cko1_round_rate(struct clk *clk, unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + div = div < 1 ? 1 : div; + div = div > 8 ? 8 : div; + return clk->parent->rate / div; +} + +static int cko1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 sel, reg; + + if (parent == &cpu_clk) + sel = 0; + else if (parent == &pll1_sw_clk) + sel = 1; + else if (parent == &pll2_sw_clk) + sel = 2; + else if (parent == &pll3_sw_clk) + sel = 3; + else if (parent == &emi_core_clk) + sel = 4; + else if (parent == &nfc_clk) + sel = 6; + else if (parent == &vpu_clk[1]) + sel = 7; + else if (parent == &ipu_di_clk) + sel = 8; + else if (parent == &ahb_clk) + sel = 11; + else if (parent == &ipg_clk) + sel = 12; + else if (parent == &ipg_perclk) + sel = 13; + else + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK; + reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; +} +static struct clk cko1_clk = { + .name = "cko1_clk", + .recalc = cko1_recalc, + .enable = cko1_enable, + .disable = cko1_disable, + .set_rate = cko1_set_rate, + .round_rate = cko1_round_rate, + .set_parent = cko1_set_parent, +}; + +static struct clk *mxc_clks[] = { + &osc_clk, + &ckih_clk, + &ckil_clk, + &fpm_clk, + &fpm_div2_clk, + &pll1_main_clk, + &pll1_sw_clk, + &pll2_sw_clk, + &pll3_sw_clk, + &gpc_dvfs_clk, + &lp_apm_clk, + &cpu_clk, + &periph_apm_clk, + &main_bus_clk, + &axi_a_clk, + &axi_b_clk, + &axi_c_clk, + &ahb_clk, + &ahb_max_clk, + &aips_tz1_clk, + &aips_tz2_clk, + &ipg_clk, + &ipg_perclk, + &sdma_clk[0], + &sdma_clk[1], + &ipu_clk[0], + &ipu_clk[1], + &ipu_di_clk, + &tve_clk, + &uart_main_clk, + &uart1_clk[0], + &uart1_clk[1], + &uart2_clk[0], + &uart2_clk[1], + &uart3_clk[0], + &uart3_clk[1], + &spba_clk, + &i2c_clk[0], + &i2c_clk[1], + &i2c_clk[2], + &gpt_clk[0], + &gpt_clk[1], + &gpt_clk[2], + &cspi_main_clk, + &cspi1_clk[0], + &cspi1_clk[1], + &cspi2_clk[0], + &cspi2_clk[1], + &cspi3_clk[0], + &cspi3_clk[1], + &ssi_lp_apm_clk, + &ssi1_clk[0], + &ssi1_clk[1], + &ssi2_clk[0], + &ssi2_clk[1], + &ssi_ext1_clk, + &ssi_ext2_clk, + &iim_clk, + &tmax1_clk, + &tmax2_clk, + &ahbmux1_clk, + &ahbmux2_clk, + &usb_core_clk[0], + &usb_core_clk[1], + &usb_core_clk[2], + &usb_core_clk[3], + &usboh2_clk, + &usb_phy_clk, + &usb_clk, + &esdhc1_clk[0], + &esdhc1_clk[1], + &esdhc1_clk[2], + &esdhc2_clk[0], + &esdhc2_clk[1], + &esdhc2_clk[2], + &esdhc3_clk[0], + &esdhc3_clk[1], + &esdhc3_clk[2], + &esdhc_dep_clks, + &emi_core_clk, + &emi_fast_clk, + &emi_slow_clk, + &emi_intr_clk, + &nfc_clk, + &spdif_xtal_clk, + &spdif0_clk[0], + &spdif0_clk[1], + &spdif1_clk[0], + &spdif1_clk[1], + &ddr_clk, + &arm_axi_clk, + &vpu_clk[0], + &vpu_clk[1], + &vpu_clk[2], + &lpsr_clk, + &pgc_clk, + &rtc_clk, + &ata_clk, + &rng_clk, + &scc_clk, + &cko1_clk, +}; + +static void clk_tree_init(void) +{ + u32 reg, dp_ctl; + + /* set pll1_main_clk parent */ + pll1_main_clk.parent = &osc_clk; + dp_ctl = __raw_readl(pll_base[0] + MXC_PLL_DP_CTL); + if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) + pll1_main_clk.parent = &fpm_clk; + /* set pll2_sw_clk parent */ + pll2_sw_clk.parent = &osc_clk; + dp_ctl = __raw_readl(pll_base[1] + MXC_PLL_DP_CTL); + if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) + pll2_sw_clk.parent = &fpm_clk; + /* set pll3_clk parent */ + pll3_sw_clk.parent = &osc_clk; + dp_ctl = __raw_readl(pll_base[2] + MXC_PLL_DP_CTL); + if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) + pll3_sw_clk.parent = &fpm_clk; + + /* set emi_core_clk parent */ + emi_core_clk.parent = &main_bus_clk; + reg = __raw_readl(MXC_CCM_CBCDR6); + if ((reg & MXC_CCM_CBCDR6_EMI_CLK_SEL) != 0) { + emi_core_clk.parent = &ahb_clk; + } + + /* set ipg_perclk parent */ + ipg_perclk.parent = &lp_apm_clk; + reg = __raw_readl(MXC_CCM_CSCMR1); + if ((reg & MXC_CCM_CSCMR1_PERCLK_IPG_CLK_SEL) != 0) { + ipg_perclk.parent = &ipg_clk; + } else { + if ((reg & MXC_CCM_CSCMR1_PERCLK_LP_APM_CLK_SEL) == 0) + ipg_perclk.parent = &main_bus_clk; + } + + /* set DDR clock parent */ + reg = __raw_readl(MXC_CCM_CAMR) & MXC_CCM_CAMR_DDR_CLK_SEL_MASK; + reg >>= MXC_CCM_CAMR_DDR_CLK_SEL_OFFSET; + if (reg == 0) { + ddr_clk.parent = &axi_a_clk; + } else if (reg == 1) { + ddr_clk.parent = &axi_b_clk; + } else if (reg == 2) { + ddr_clk.parent = &axi_c_clk; + } else { + ddr_clk.parent = &emi_core_clk; + } +} + +int __init mxc_clocks_init(void) +{ + struct clk **clkp; + u32 reg; + int i; + + for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) { + clk_register(*clkp); + } + + /* Turn off all possible clocks */ + if (mxc_jtag_enabled) { + __raw_writel((1 << MXC_CCM_CCGR0_CG0_OFFSET) | + (1 << MXC_CCM_CCGR0_CG1_OFFSET) | + (1 << MXC_CCM_CCGR0_CG2_OFFSET) | + (1 << MXC_CCM_CCGR0_CG12_OFFSET) | + (1 << MXC_CCM_CCGR0_CG13_OFFSET) | + (1 << MXC_CCM_CCGR0_CG7_OFFSET) | + (1 << MXC_CCM_CCGR0_CG14_OFFSET), MXC_CCM_CCGR0); + } else { + __raw_writel((1 << MXC_CCM_CCGR0_CG0_OFFSET) | + (1 << MXC_CCM_CCGR0_CG1_OFFSET) | + (1 << MXC_CCM_CCGR0_CG12_OFFSET) | + (1 << MXC_CCM_CCGR0_CG13_OFFSET) | + (1 << MXC_CCM_CCGR0_CG7_OFFSET) | + (1 << MXC_CCM_CCGR0_CG14_OFFSET), MXC_CCM_CCGR0); + } + __raw_writel(0, MXC_CCM_CCGR1); + + /* TMAX clocks. */ + reg = __raw_readl(MXC_CCM_CCGR1); + reg |= 1 << MXC_CCM_CCGR1_CG0_OFFSET; + reg |= 1 << MXC_CCM_CCGR1_CG1_OFFSET; + __raw_writel(reg, MXC_CCM_CCGR1); + + __raw_writel(0, MXC_CCM_CCGR2); + __raw_writel(0, MXC_CCM_CCGR3); + __raw_writel(0, MXC_CCM_CCGR4); + /* Initialise the EMI clocks to be OFF when ARM is in WAIT mode. */ + __raw_writel((1 << MXC_CCM_CCGR5_CG4_OFFSET) | + (1 << MXC_CCM_CCGR5_CG12_OFFSET) | + (1 << MXC_CCM_CCGR5_CG13_OFFSET) | + (1 << MXC_CCM_CCGR5_CG14_OFFSET) | + MXC_CCM_CCGR5_CG11_MASK, MXC_CCM_CCGR5); + + reg = __raw_readl(MXC_CCM_CCSR); + /*STEP_CLK - make sure its source is lp_apm */ + reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK; + __raw_writel(reg, MXC_CCM_CCSR); + + /* This will propagate to all children and init all the clock rates */ + propagate_rate(&osc_clk); + propagate_rate(&ckih_clk); + propagate_rate(&ckil_clk); + + _clk_pll_disable(&pll3_sw_clk); + + clk_enable(&cpu_clk); + clk_enable(&main_bus_clk); + + clk_enable(&gpt_clk[1]); + + /* Move UART to run from pll2_sw_clk */ + clk_set_parent(&uart_main_clk, &pll2_sw_clk); + + /* Set the UART dividers to divide by 10, so the UART_CLK is 66.5MHz. */ + reg = __raw_readl(MXC_CCM_CSCDR1); + reg &= ~MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; + reg &= ~MXC_CCM_CSCDR1_UART_CLK_PRED_MASK; + reg |= (4 << MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) | + (1 << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CSCDR1); + + /* move cspi to 24MHz */ + clk_set_parent(&cspi_main_clk, &lp_apm_clk); + clk_set_rate(&cspi_main_clk, 12000000); + + /*move the spdif0 to spdif_xtal_ckl */ + clk_set_parent(&spdif0_clk[0], &spdif_xtal_clk); + /*set the SPDIF dividers to 1 */ + reg = __raw_readl(MXC_CCM_CDCDR); + reg &= ~MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK; + reg &= ~MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK; + __raw_writel(reg, MXC_CCM_CDCDR); + + /* move the spdif1 to 24MHz */ + clk_set_parent(&spdif1_clk[0], &spdif_xtal_clk); + /* set the spdif1 dividers to 1 */ + reg = __raw_readl(MXC_CCM_CDCDR); + reg &= ~MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK; + reg &= ~MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK; + __raw_writel(reg, MXC_CCM_CDCDR); + + /* Move SSI clocks to SSI_LP_APM clock */ + clk_set_parent(&ssi_lp_apm_clk, &lp_apm_clk); + + clk_set_parent(&ssi1_clk[0], &ssi_lp_apm_clk); + /* set the SSI dividers to divide by 2 */ + reg = __raw_readl(MXC_CCM_CS1CDR); + reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK; + reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK; + reg |= 1 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CS1CDR); + + clk_set_parent(&ssi2_clk[0], &ssi_lp_apm_clk); + reg = __raw_readl(MXC_CCM_CS2CDR); + reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK; + reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK; + reg |= 1 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CS2CDR); + + /* Change the SSI_EXT1_CLK to be sourced from SSI1_CLK_ROOT */ + clk_set_parent(&ssi_ext1_clk, &ssi1_clk[0]); + clk_set_parent(&ssi_ext2_clk, &ssi2_clk[0]); + + propagate_rate(&ssi_lp_apm_clk); + + clk_set_parent(&ipu_clk[0], &emi_core_clk); + clk_set_parent(&arm_axi_clk, &emi_core_clk); + clk_set_parent(&vpu_clk[0], &emi_core_clk); + clk_set_parent(&vpu_clk[1], &emi_core_clk); + clk_set_parent(&usb_phy_clk, &osc_clk); + + clk_set_parent(&cko1_clk, &ipg_perclk); + + /* Set the current working point. */ + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + for (i = 0; i < cpu_wp_nr; i++) { + if (clk_get_rate(&cpu_clk) == cpu_wp_tbl[i].cpu_rate) { + cpu_curr_wp = i; + break; + } + } + if (i > cpu_wp_nr) + BUG(); + + propagate_rate(&osc_clk); + propagate_rate(&pll1_sw_clk); + propagate_rate(&pll2_sw_clk); + + return 0; +} + +/*! + * Function to get timer clock rate early in boot process before clock tree is + * initialized. + * + * @return Clock rate for timer + */ +unsigned long __init clk_early_get_timer_rate(void) +{ + u32 reg; + + ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk); + + /* + *Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at + * 8MHz, its derived from lp_apm. + */ + reg = __raw_readl(MXC_CCM_CBCDR2); + reg &= ~MXC_CCM_CBCDR2_PERCLK_PRED1_MASK; + reg &= ~MXC_CCM_CBCDR2_PERCLK_PRED2_MASK; + reg &= ~MXC_CCM_CBCDR2_PERCLK_PODF_MASK; + reg |= (2 << MXC_CCM_CBCDR2_PERCLK_PRED1_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR2); + + board_ref_clk_rate(&ckil_clk.rate, &osc_clk.rate, &ckih_clk.rate); + clk_tree_init(); + + lp_apm_clk.rate = lp_apm_clk.parent->rate; + ipg_perclk.recalc(&ipg_perclk); + clk_enable(&ipg_perclk); + gpt_clk[1].enable(&gpt_clk[1]); + + return ipg_perclk.rate; +} + +/*! + * Setup cpu clock based on working point. + * @param wp cpu freq working point + * @return 0 on success or error code on failure. + */ +static int cpu_clk_set_wp(int wp) +{ + struct cpu_wp *p; + u32 reg; + u32 stat; + + if (wp == cpu_curr_wp) + return 0; + + p = &cpu_wp_tbl[wp]; + + /* Change the ARM clock to requested frequency */ + /* First move the ARM clock to step clock which is running at 24MHz. */ + + /* Change the source of pll1_sw_clk to be the step_clk */ + reg = __raw_readl(MXC_CCM_CCSR); + reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + __raw_writel(reg, MXC_CCM_CCSR); + + /* Stop the PLL */ + reg = __raw_readl(MXC_DPLL1_BASE + MXC_PLL_DP_CTL); + reg &= ~MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, MXC_DPLL1_BASE + MXC_PLL_DP_CTL); + + /* PDF and MFI */ + reg = p->pdf | p->mfi << MXC_PLL_DP_OP_MFI_OFFSET; + __raw_writel(reg, MXC_DPLL1_BASE + MXC_PLL_DP_OP); + + /* MFD */ + __raw_writel(p->mfd, MXC_DPLL1_BASE + MXC_PLL_DP_MFD); + + /* MFI */ + __raw_writel(p->mfn, MXC_DPLL1_BASE + MXC_PLL_DP_MFN); + + reg = __raw_readl(MXC_DPLL1_BASE + MXC_PLL_DP_CTL); + reg |= MXC_PLL_DP_CTL_UPEN; + /* Set the UPEN bits */ + __raw_writel(reg, MXC_DPLL1_BASE + MXC_PLL_DP_CTL); + /* Forcefully restart the PLL */ + reg |= MXC_PLL_DP_CTL_RST; + __raw_writel(reg, MXC_DPLL1_BASE + MXC_PLL_DP_CTL); + + /* Wait for the PLL to lock */ + do { + stat = __raw_readl(MXC_DPLL1_BASE + MXC_PLL_DP_CTL) & + MXC_PLL_DP_CTL_LRF; + } while (!stat); + + reg = __raw_readl(MXC_CCM_CCSR); + /* Move the PLL1 back to the pll1_main_clk */ + reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + __raw_writel(reg, MXC_CCM_CCSR); + + cpu_curr_wp = wp; + + pll1_sw_clk.rate = cpu_wp_tbl[wp].cpu_rate; + pll1_main_clk.rate = pll1_sw_clk.rate; + cpu_clk.rate = pll1_sw_clk.rate; + + if (wp == 0) + dptc_resume(DPTC_GP_ID); + else + dptc_suspend(DPTC_GP_ID); + + return 0; +} diff -urN linux-2.6.26/arch/arm/mach-mx37/cpu.c linux-2.6.26-lab126/arch/arm/mach-mx37/cpu.c --- linux-2.6.26/arch/arm/mach-mx37/cpu.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/cpu.c 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2001 Deep Blue Solutions Ltd. + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +/*! + * @file mach-mx37/cpu.c + * + * @brief This file contains the CPU initialization code. + * + * @ingroup MSL_MX37 + */ + +#include +#include +#include +#include +#include +#include + +/*! + * CPU initialization. It is called by fixup_mxc_board() + */ +void __init mxc_cpu_init(void) +{ + if (!system_rev) { + mxc_set_system_rev(0x37, CHIP_REV_1_0); + } +} + +/*! + * Post CPU init code + * + * @return 0 always + */ +static int __init post_cpu_init(void) +{ + void *l2_base; + volatile unsigned long aips_reg; + + /* Initialize L2 cache */ + l2_base = ioremap(L2CC_BASE_ADDR, SZ_4K); + if (l2_base) { + l2x0_init(l2_base, 0x0003001B, 0x00000000); + } + + __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x40)); + __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x44)); + __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x48)); + __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x4C)); + aips_reg = __raw_readl(IO_ADDRESS(AIPS1_BASE_ADDR + 0x50)); + aips_reg &= 0x00FFFFFF; + __raw_writel(aips_reg, IO_ADDRESS(AIPS1_BASE_ADDR + 0x50)); + + __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x40)); + __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x44)); + __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x48)); + __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x4C)); + aips_reg = __raw_readl(IO_ADDRESS(AIPS2_BASE_ADDR + 0x50)); + aips_reg &= 0x00FFFFFF; + __raw_writel(aips_reg, IO_ADDRESS(AIPS2_BASE_ADDR + 0x50)); + + return 0; +} + +postcore_initcall(post_cpu_init); diff -urN linux-2.6.26/arch/arm/mach-mx37/crm_regs.h linux-2.6.26-lab126/arch/arm/mach-mx37/crm_regs.h --- linux-2.6.26/arch/arm/mach-mx37/crm_regs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/crm_regs.h 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,611 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ARCH_ARM_MACH_MX37_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MX37_CRM_REGS_H__ + +#define MXC_CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) +#define MXC_DPLL1_BASE IO_ADDRESS(PLL0_BASE_ADDR) +#define MXC_DPLL2_BASE IO_ADDRESS(PLL1_BASE_ADDR) +#define MXC_DPLL3_BASE IO_ADDRESS(PLL2_BASE_ADDR) + +/* PLL Register Offsets */ +#define MXC_PLL_DP_CTL 0x00 +#define MXC_PLL_DP_CONFIG 0x04 +#define MXC_PLL_DP_OP 0x08 +#define MXC_PLL_DP_MFD 0x0C +#define MXC_PLL_DP_MFN 0x10 +#define MXC_PLL_DP_MFNMINUS 0x14 +#define MXC_PLL_DP_MFNPLUS 0x18 +#define MXC_PLL_DP_HFS_OP 0x1C +#define MXC_PLL_DP_HFS_MFD 0x20 +#define MXC_PLL_DP_HFS_MFN 0x24 +#define MXC_PLL_DP_MFN_TOGC 0x28 +#define MXC_PLL_DP_DESTAT 0x2c + +/* PLL Register Bit definitions */ +#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 +#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 +#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 +#define MXC_PLL_DP_CTL_ADE 0x800 +#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 +#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) +#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 +#define MXC_PLL_DP_CTL_HFSM 0x80 +#define MXC_PLL_DP_CTL_PRE 0x40 +#define MXC_PLL_DP_CTL_UPEN 0x20 +#define MXC_PLL_DP_CTL_RST 0x10 +#define MXC_PLL_DP_CTL_RCP 0x8 +#define MXC_PLL_DP_CTL_PLM 0x4 +#define MXC_PLL_DP_CTL_BRM0 0x2 +#define MXC_PLL_DP_CTL_LRF 0x1 + +#define MXC_PLL_DP_CONFIG_BIST 0x8 +#define MXC_PLL_DP_CONFIG_SJC_CE 0x4 +#define MXC_PLL_DP_CONFIG_AREN 0x2 +#define MXC_PLL_DP_CONFIG_LDREQ 0x1 + +#define MXC_PLL_DP_OP_MFI_OFFSET 4 +#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) +#define MXC_PLL_DP_OP_PDF_OFFSET 0 +#define MXC_PLL_DP_OP_PDF_MASK 0xF + +#define MXC_PLL_DP_MFD_OFFSET 0 +#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF + +#define MXC_PLL_DP_MFN_OFFSET 0x0 +#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF + +#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) +#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) +#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 +#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF + +#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) +#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF + +/* Register addresses of CCM*/ +#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00) +#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04) +#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08) +#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C) +#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10) +#define MXC_CCM_CBCDR2 (MXC_CCM_BASE + 0x18) +#define MXC_CCM_CBCDR3 (MXC_CCM_BASE + 0x1C) +#define MXC_CCM_CBCDR4 (MXC_CCM_BASE + 0x20) +#define MXC_CCM_CBCDR5 (MXC_CCM_BASE + 0x24) +#define MXC_CCM_CBCDR6 (MXC_CCM_BASE + 0x28) +#define MXC_CCM_CBCDR7 (MXC_CCM_BASE + 0x2C) +#define MXC_CCM_CAMR (MXC_CCM_BASE + 0x30) +#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x34) +#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x38) +#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x3C) +#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x40) +#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x44) +#define MXC_CCM_CSECDR1 (MXC_CCM_BASE + 0x48) +#define MXC_CCM_CSECDR2 (MXC_CCM_BASE + 0x4C) +#define MXC_CCM_CECDR (MXC_CCM_BASE + 0x50) +#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x54) +#define MXC_CCM_CH1CDR (MXC_CCM_BASE + 0x58) +#define MXC_CCM_CH2CDR (MXC_CCM_BASE + 0x5C) +#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x60) +#define MXC_CCM_CR2 (MXC_CCM_BASE + 0x64) +#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x68) +#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x6C) +#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x70) +#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x74) +#define MXC_CCM_CISR (MXC_CCM_BASE + 0x78) +#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x7C) +#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x80) +#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x84) +#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x88) +#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x8C) +#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x90) +#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x94) +#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x98) +#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x9C) +#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0xA0) + +/* Define the bits in register CCR */ +#define MXC_CCM_CCR_COSC_EN (1 << 11) +#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 10) +#define MXC_CCM_CCR_CAMP_EN (1 << 9) +#define MXC_CCM_CCR_FPM_EN (1 << 8) +#define MXC_CCM_CCR_OSCNT_OFFSET (0) +#define MXC_CCM_CCR_OSCNT_MASK (0xFF) + +/* Define the bits in register CCDR */ +#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) +#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16) +#define MXC_CCM_CCDR_LOAD_DIVIDERS (0x1 << 0) + +/* Define the bits in register CSR */ +#define MXC_CCM_CSR_COSR_READY (1 << 4) +#define MXC_CCM_CSR_LVS_VALUE (1 << 3) +#define MXC_CCM_CSR_CAMP_READY (1 << 2) +#define MXC_CCM_CSR_FPM_READY (1 << 1) +#define MXC_CCM_CSR_REF_EN_B (1 << 0) + +/* Define the bits in register CCSR */ +#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9) +#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7) +#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) +#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5) +#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5) +#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3) +#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3) +#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) +#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) +#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) + +/* Define the bits in register CACRR */ +#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0) +#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7) + +/* Define the bits in register CBCDR2 */ +#define MXC_CCM_CBCDR2_AHB_PODF_OFFSET (10) +#define MXC_CCM_CBCDR2_AHB_PODF_MASK (0x7 << 10) +#define MXC_CCM_CBCDR2_IPG_PODF_OFFSET (8) +#define MXC_CCM_CBCDR2_IPG_PODF_MASK (0x3 << 8) +#define MXC_CCM_CBCDR2_PERCLK_PRED1_OFFSET (6) +#define MXC_CCM_CBCDR2_PERCLK_PRED1_MASK (0x3 << 6) +#define MXC_CCM_CBCDR2_PERCLK_PRED2_OFFSET (3) +#define MXC_CCM_CBCDR2_PERCLK_PRED2_MASK (0x7 << 3) +#define MXC_CCM_CBCDR2_PERCLK_PODF_OFFSET (0) +#define MXC_CCM_CBCDR2_PERCLK_PODF_MASK (0x7) + +/* Define the bits in register CBCDR3 */ +#define MXC_CCM_CBCDR3_AXI_A_PODF_OFFSET (0) +#define MXC_CCM_CBCDR3_AXI_A_PODF_MASK (0x7) + +/* Define the bits in register CBCDR4 */ +#define MXC_CCM_CBCDR4_AXI_B_PODF_OFFSET (0) +#define MXC_CCM_CBCDR4_AXI_B_PODF_MASK (0x7) + +/* Define the bits in register CBCDR5 */ +#define MXC_CCM_CBCDR5_AXI_C_PODF_OFFSET (0) +#define MXC_CCM_CBCDR5_AXI_C_PODF_MASK (0x7) + +/* Define the bits in register CBCDR6 */ +#define MXC_CCM_CBCDR6_EMI_PODF_OFFSET (0) +#define MXC_CCM_CBCDR6_EMI_PODF_MASK (0x7) +#define MXC_CCM_CBCDR6_EMI_CLK_SEL (0x1 << 3) +#define MXC_CCM_CBCDR6_PERIPH_CLK_SEL (0x1 << 4) + +/* Define the bits in register CBCDR7 */ +#define MXC_CCM_CBCDR7_IPG_INT_MEM_PODF_OFFSET (3) +#define MXC_CCM_CBCDR7_IPG_INIT_MEM_PODF_MASK (0x3 << 3) +#define MXC_CCM_CBCDR7_NFC_PODF_OFFSET (0) +#define MXC_CCM_CBCDR7_NFC_PODF_MASK (0x7) + +/* Define the bits in register CAMR */ +#define MXC_CCM_CAMR_PERIPH_CLK_SEL_OFFSET (12) +#define MXC_CCM_CAMR_PERIPH_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CAMR_DDR_CLK_SEL_OFFSET (10) +#define MXC_CCM_CAMR_DDR_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CAMR_ARM_AXI_CLK_SEL_OFFSET (8) +#define MXC_CCM_CAMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CAMR_VPU_CLK_SEL_OFFSET (6) +#define MXC_CCM_CAMR_VPU_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CAMR_VPU_AXI_CLK_SEL_OFFSET (4) +#define MXC_CCM_CAMR_VPU_AXI_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CAMR_IPU_HSP_CLK_SEL_OFFSET (2) +#define MXC_CCM_CAMR_IPU_HSP_CLK_SEL_MASK (0x3 << 2) + +/* Define the bits in register CSCMR1 */ +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30) +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) +#define MXC_CCM_CSCMR1_DI_CLK_SEL (0x1 << 27) +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26) +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR1_USBOH2_CLK_SEL_OFFSET (22) +#define MXC_CCM_CSCMR1_USBOH2_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) +#define MXC_CCM_CSCMR1_PERCLK_IPG_CLK_SEL (0x1 << 18) +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL (0x1 << 9) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL (0x1 << 8) +#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) +#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CSCMR1_PERCLK_LP_APM_CLK_SEL (0x1 << 2) +#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1) + +/* Define the bits in register CSCMR2 */ +#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5) +#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4) +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2) +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0) +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3) + +/* Define the bits in register CSCDR1 */ +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR1_USBOH2_CLK_PRED_OFFSET (8) +#define MXC_CCM_CSCDR1_USBOH2_CLK_PRED_MASK (0x7 << 8) +#define MXC_CCM_CSCDR1_USBOH2_CLK_PODF_OFFSET (6) +#define MXC_CCM_CSCDR1_USBOH2_CLK_PODF_MASK (0x3 << 6) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7) + +/* Define the bits in register CS1CDR and CS2CDR */ +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6) +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0) +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F) + +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6) +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0) +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F) + +/* Define the bits in register CSECDR1 and CSECDR2 */ +#define MXC_CCM_CSECDR1_SSI_EXT1_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSECDR1_SSI_EXT1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSECDR1_SSI_EXT1_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSECDR1_SSI_EXT1_CLK_PODF_MASK (0x3F) + +#define MXC_CCM_CSECDR2_SSI_EXT2_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSECDR2_SSI_EXT2_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSECDR2_SSI_EXT2_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSECDR2_SSI_EXT2_CLK_PODF_MASK (0x3F) + +/* Define the bits in register CDCDR */ +#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28) +#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (4) +#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 4) +#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (1) +#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7 << 1) + +/* Define the bits in register CSCDR2 */ +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) + +/* Define the bits in register CDHIPR */ +#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) +#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4) +#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 3) +#define MXC_CCM_CDHIPR_AXI_C_PODF_BUSY (1 << 2) +#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1) +#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0) + +/* Define the bits in register CDCR */ +#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2) +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0) +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3) + +/* Define the bits in register CLPCR */ +#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) +#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) +#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) +#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) +#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) +#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17) +#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16) +#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11) +#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9) +#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) +#define MXC_CCM_CLPCR_VSTBY (0x1 << 8) +#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7) +#define MXC_CCM_CLPCR_SBYOS (0x1 << 6) +#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3) +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) +#define MXC_CCM_CLPCR_LPM_OFFSET (0) +#define MXC_CCM_CLPCR_LPM_MASK (0x3) + +/* Define the bits in register CISR */ +#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25) +#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) +#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 20) +#define MXC_CCM_CISR_AXI_C_PODF_LOADED (0x1 << 19) +#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18) +#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17) +#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16) +#define MXC_CCM_CISR_COSC_READY (0x1 << 5) +#define MXC_CCM_CISR_CKIH_READY (0x1 << 4) +#define MXC_CCM_CISR_FPM_READY (0x1 << 3) +#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2) +#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1) +#define MXC_CCM_CISR_LRF_PLL1 (0x1) + +/* Define the bits in register CIMR */ +#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25) +#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) +#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20) +#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19) +#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18) +#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17) +#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16) +#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5) +#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4) +#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3) +#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2) +#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1) +#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1) + +/* Define the bits in register CCOSR */ +#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24) +#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21) +#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) +#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16) +#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) +#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) +#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4) +#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) +#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0) +#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF) + +/* Define the bits in registers CGPR */ +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4) +#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3) +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0) +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7) + +/* Define the bits in registers CCGRx */ +#define MXC_CCM_CCGR_CG_MASK 0x3 + +#define MXC_CCM_CCGR0_CG15_OFFSET 30 +#define MXC_CCM_CCGR0_CG14_OFFSET 28 +#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGR0_CG13_OFFSET 26 +#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGR0_CG12_OFFSET 24 +#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGR0_CG11_OFFSET 22 +#define MXC_CCM_CCGR0_CG10_OFFSET 20 +#define MXC_CCM_CCGR0_CG9_OFFSET 18 +#define MXC_CCM_CCGR0_CG8_OFFSET 16 +#define MXC_CCM_CCGR0_CG7_OFFSET 14 +#define MXC_CCM_CCGR0_CG6_OFFSET 12 +#define MXC_CCM_CCGR0_CG5_OFFSET 10 +#define MXC_CCM_CCGR0_CG4_OFFSET 8 +#define MXC_CCM_CCGR0_CG3_OFFSET 6 +#define MXC_CCM_CCGR0_CG2_OFFSET 4 +#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4) +#define MXC_CCM_CCGR0_CG1_OFFSET 2 +#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2) +#define MXC_CCM_CCGR0_CG0_OFFSET 0 +#define MXC_CCM_CCGR0_CG0_MASK 0x3 + +#define MXC_CCM_CCGR1_CG15_OFFSET 30 +#define MXC_CCM_CCGR1_CG14_OFFSET 28 +#define MXC_CCM_CCGR1_CG13_OFFSET 26 +#define MXC_CCM_CCGR1_CG12_OFFSET 24 +#define MXC_CCM_CCGR1_CG11_OFFSET 22 +#define MXC_CCM_CCGR1_CG10_OFFSET 20 +#define MXC_CCM_CCGR1_CG9_OFFSET 18 +#define MXC_CCM_CCGR1_CG8_OFFSET 16 +#define MXC_CCM_CCGR1_CG7_OFFSET 14 +#define MXC_CCM_CCGR1_CG6_OFFSET 12 +#define MXC_CCM_CCGR1_CG5_OFFSET 10 +#define MXC_CCM_CCGR1_CG4_OFFSET 8 +#define MXC_CCM_CCGR1_CG3_OFFSET 6 +#define MXC_CCM_CCGR1_CG2_OFFSET 4 +#define MXC_CCM_CCGR1_CG1_OFFSET 2 +#define MXC_CCM_CCGR1_CG0_OFFSET 0 + +#define MXC_CCM_CCGR2_CG15_OFFSET 30 +#define MXC_CCM_CCGR2_CG14_OFFSET 28 +#define MXC_CCM_CCGR2_CG13_OFFSET 26 +#define MXC_CCM_CCGR2_CG12_OFFSET 24 +#define MXC_CCM_CCGR2_CG11_OFFSET 22 +#define MXC_CCM_CCGR2_CG10_OFFSET 20 +#define MXC_CCM_CCGR2_CG9_OFFSET 18 +#define MXC_CCM_CCGR2_CG8_OFFSET 16 +#define MXC_CCM_CCGR2_CG7_OFFSET 14 +#define MXC_CCM_CCGR2_CG6_OFFSET 12 +#define MXC_CCM_CCGR2_CG5_OFFSET 10 +#define MXC_CCM_CCGR2_CG4_OFFSET 8 +#define MXC_CCM_CCGR2_CG3_OFFSET 6 +#define MXC_CCM_CCGR2_CG2_OFFSET 4 +#define MXC_CCM_CCGR2_CG1_OFFSET 2 +#define MXC_CCM_CCGR2_CG0_OFFSET 0 + +#define MXC_CCM_CCGR3_CG15_OFFSET 30 +#define MXC_CCM_CCGR3_CG14_OFFSET 28 +#define MXC_CCM_CCGR3_CG13_OFFSET 26 +#define MXC_CCM_CCGR3_CG12_OFFSET 24 +#define MXC_CCM_CCGR3_CG11_OFFSET 22 +#define MXC_CCM_CCGR3_CG10_OFFSET 20 +#define MXC_CCM_CCGR3_CG9_OFFSET 18 +#define MXC_CCM_CCGR3_CG8_OFFSET 16 +#define MXC_CCM_CCGR3_CG7_OFFSET 14 +#define MXC_CCM_CCGR3_CG6_OFFSET 12 +#define MXC_CCM_CCGR3_CG5_OFFSET 10 +#define MXC_CCM_CCGR3_CG4_OFFSET 8 +#define MXC_CCM_CCGR3_CG3_OFFSET 6 +#define MXC_CCM_CCGR3_CG2_OFFSET 4 +#define MXC_CCM_CCGR3_CG1_OFFSET 2 +#define MXC_CCM_CCGR3_CG0_OFFSET 0 + +#define MXC_CCM_CCGR4_CG15_OFFSET 30 +#define MXC_CCM_CCGR4_CG14_OFFSET 28 +#define MXC_CCM_CCGR4_CG13_OFFSET 26 +#define MXC_CCM_CCGR4_CG12_OFFSET 24 +#define MXC_CCM_CCGR4_CG11_OFFSET 22 +#define MXC_CCM_CCGR4_CG10_OFFSET 20 +#define MXC_CCM_CCGR4_CG9_OFFSET 18 +#define MXC_CCM_CCGR4_CG8_OFFSET 16 +#define MXC_CCM_CCGR4_CG7_OFFSET 14 +#define MXC_CCM_CCGR4_CG6_OFFSET 12 +#define MXC_CCM_CCGR4_CG5_OFFSET 10 +#define MXC_CCM_CCGR4_CG4_OFFSET 8 +#define MXC_CCM_CCGR4_CG3_OFFSET 6 +#define MXC_CCM_CCGR4_CG2_OFFSET 4 +#define MXC_CCM_CCGR4_CG1_OFFSET 2 +#define MXC_CCM_CCGR4_CG0_OFFSET 0 + +#define MXC_CCM_CCGR5_CG15_OFFSET 30 +#define MXC_CCM_CCGR5_CG14_OFFSET 28 +#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGR5_CG13_OFFSET 26 +#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGR5_CG12_OFFSET 24 +#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGR5_CG11_OFFSET 22 +#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGR5_CG10_OFFSET 20 +#define MXC_CCM_CCGR5_CG9_OFFSET 18 +#define MXC_CCM_CCGR5_CG8_OFFSET 16 +#define MXC_CCM_CCGR5_CG7_OFFSET 14 +#define MXC_CCM_CCGR5_CG6_OFFSET 12 +#define MXC_CCM_CCGR5_CG5_OFFSET 10 +#define MXC_CCM_CCGR5_CG4_OFFSET 8 +#define MXC_CCM_CCGR5_CG3_OFFSET 6 +#define MXC_CCM_CCGR5_CG2_OFFSET 4 +#define MXC_CCM_CCGR5_CG1_OFFSET 2 +#define MXC_CCM_CCGR5_CG0_OFFSET 0 + +#define MXC_ARM1176_BASE IO_ADDRESS(ARM1176_BASE_ADDR) +#define MXC_GPC_BASE IO_ADDRESS(GPC_BASE_ADDR) +#define MXC_DPTC_LP_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x80) +#define MXC_DPTC_GP_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x100) +#define MXC_DVFS_CORE_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x180) +#define MXC_DPTC_PER_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x1C0) +#define MXC_PGC_IPU_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x220) +#define MXC_PGC_VPU_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x240) +#define MXC_SRPGC_EMI_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x280) +#define MXC_SRPGC_ARM_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x2A0) +#define MXC_EMPGC0_ARM_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x2C0) +#define MXC_EMPGC1_ARM_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x2D0) + +/* ARM1176 platform */ +#define MXC_ARM1176_PLAT_PVID (MXC_ARM1176_BASE + 0x0) +#define MXC_ARM1176_PLAT_GPC (MXC_ARM1176_BASE + 0x4) +#define MXC_ARM1176_PLAT_PIC (MXC_ARM1176_BASE + 0x8) +#define MXC_ARM1176_PLAT_L2SO (MXC_ARM1176_BASE + 0xC) +#define MXC_ARM1176_PLAT_EMSO (MXC_ARM1176_BASE + 0x10) +#define MXC_ARM1176_PLAT_LPC (MXC_ARM1176_BASE + 0x14) +#define MXC_ARM1176_PLAT_ICGC (MXC_ARM1176_BASE + 0x18) +#define MXC_ARM1176_PLAT_AMC (MXC_ARM1176_BASE + 0x1C) + +/* GPC */ +#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0) +#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4) +#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8) + +/* DVFS CORE */ +#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) +#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04) +#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08) +#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C) +#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10) +#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14) +#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18) +#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C) +#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20) +#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24) +#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28) +#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C) +#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30) +#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34) +#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38) +#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C) +#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40) + +/* DPTC GP */ +#define MXC_GP_DPTCCR (MXC_DPTC_GP_BASE + 0x00) +#define MXC_GP_DPTCDBG (MXC_DPTC_GP_BASE + 0x04) +#define MXC_GP_DCVR0 (MXC_DPTC_GP_BASE + 0x08) +#define MXC_GP_DCVR1 (MXC_DPTC_GP_BASE + 0x0C) +#define MXC_GP_DCVR2 (MXC_DPTC_GP_BASE + 0x10) +#define MXC_GP_DCVR3 (MXC_DPTC_GP_BASE + 0x14) + +/* DPTC LP */ +#define MXC_LP_DPTCCR (MXC_DPTC_LP_BASE + 0x00) +#define MXC_LP_DPTCDBG (MXC_DPTC_LP_BASE + 0x04) +#define MXC_LP_DCVR0 (MXC_DPTC_LP_BASE + 0x08) +#define MXC_LP_DCVR1 (MXC_DPTC_LP_BASE + 0x0C) +#define MXC_LP_DCVR2 (MXC_DPTC_LP_BASE + 0x10) +#define MXC_LP_DCVR3 (MXC_DPTC_LP_BASE + 0x14) + +#define MXC_DPTCCR_DRCE3 0x00400000 +#define MXC_DPTCCR_DRCE2 0x00200000 +#define MXC_DPTCCR_DRCE1 0x00100000 +#define MXC_DPTCCR_DRCE0 0x00080000 +#define MXC_DPTCCR_DCR_256 0x00060000 +#define MXC_DPTCCR_DCR_128 0x00040000 +#define MXC_DPTCCR_DCR_64 0x00020000 +#define MXC_DPTCCR_DCR_32 0x00000000 +#define MXC_DPTCCR_DSMM 0x00000040 +#define MXC_DPTCCR_DPNVCR 0x00000020 +#define MXC_DPTCCR_DPVV 0x00000010 +#define MXC_DPTCCR_VAIM 0x00000008 +#define MXC_DPTCCR_VAI_OFFSET 1 +#define MXC_DPTCCR_VAI_MASK 0x00000006 +#define MXC_DPTCCR_DEN 0x00000001 + +#define MXC_GPCCNTR_GPCIRQ 0x00100000 +#define MXC_GPCCNTR_DPTC0CR 0x00040000 +#define MXC_GPCCNTR_DPTC1CR 0x00080000 +#define MXC_GPCCNTR_ADU 0x00008000 + +/* SRPG */ +#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0) +#define MXC_SRPGC_ARM_SRPGCR (MXC_SRPGC_ARM_BASE + 0x0) +#define MXC_EMPGC0_ARM_EMPGCR (MXC_EMPGC0_ARM_BASE + 0x0) +#define MXC_EMPGC1_ARM_EMPGCR (MXC_EMPGC1_ARM_BASE + 0x0) + +#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0) +#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC) +#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0) +#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC) + +#define MXC_ARM1176_PLAT_LPC_DSM (1 << 16) +#define MXC_ARM1176_PLAT_LPC_DBG_DSM (1 << 17) + +#define MXC_GPC_PGR_ARMPG_OFFSET 8 +#define MXC_GPC_PGR_ARMPG_MASK (3 << 8) + +#define MXC_PGCR_PCR 1 +#define MXC_SRPGCR_PCR 1 +#define MXC_EMPGCR_PCR 1 + +#define MXC_PGSR_PSR 1 + +#endif /* __ARCH_ARM_MACH_MX37_CRM_REGS_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx37/devices.c linux-2.6.26-lab126/arch/arm/mach-mx37/devices.c --- linux-2.6.26/arch/arm/mach-mx37/devices.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/devices.c 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,941 @@ +/* + * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include +#include "iomux.h" +#include +#include "sdma_script_code.h" +#include "crm_regs.h" + +extern struct dptc_wp dptc_gp_wp_allfreq[DPTC_GP_WP_SUPPORTED]; +extern struct dptc_wp dptc_lp_wp_allfreq[DPTC_LP_WP_SUPPORTED]; + +void mxc_sdma_get_script_info(sdma_script_start_addrs * sdma_script_addr) +{ + sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR; + sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1; + sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1; + sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR; + sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR; + sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1; + sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_start_addr = (unsigned short *)sdma_code; + sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr = uartsh_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE; + sdma_script_addr->mxc_sdma_ram_code_start_addr = RAM_CODE_START_ADDR; + sdma_script_addr->mxc_sdma_dptc_dvfs_addr = dptc_dvfs_ADDR; + sdma_script_addr->mxc_sdma_firi_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_firi_2_per_addr = -1; + sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_per_2_app_addr = -1; + sdma_script_addr->mxc_sdma_per_2_firi_addr = -1; + sdma_script_addr->mxc_sdma_per_2_shp_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_ata_addr = mcu_2_ata_ADDR; + sdma_script_addr->mxc_sdma_mcu_2_firi_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = -1; + sdma_script_addr->mxc_sdma_ata_2_mcu_addr = ata_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_uartsh_2_per_addr = -1; + sdma_script_addr->mxc_sdma_shp_2_per_addr = -1; + sdma_script_addr->mxc_sdma_uart_2_per_addr = -1; + sdma_script_addr->mxc_sdma_app_2_per_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_spdif_addr = mcu_2_spdif_marley_ADDR; +} + +static void mxc_nop_release(struct device *dev) +{ + /* Nothing */ +} + +#if defined(CONFIG_W1_MASTER_MXC) || defined(CONFIG_W1_MASTER_MXC_MODULE) +static struct mxc_w1_config mxc_w1_data = { + .search_rom_accelerator = 0, +}; + +static struct platform_device mxc_w1_devices = { + .name = "mxc_w1", + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_w1_data, + }, + .id = 0 +}; + +static void mxc_init_owire(void) +{ + (void)platform_device_register(&mxc_w1_devices); +} +#else +static inline void mxc_init_owire(void) +{ +} +#endif + +#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE) +static struct mxc_srtc_platform_data srtc_data = { + .srtc_sec_mode_addr = 0xC3FAC80C, +}; + +static struct resource rtc_resources[] = { + { + .start = SRTC_BASE_ADDR, + .end = SRTC_BASE_ADDR + 0x40, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_SRTC_NTZ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct platform_device mxc_rtc_device = { + .name = "mxc_rtc", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &srtc_data, + }, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, +}; +static void mxc_init_rtc(void) +{ + (void)platform_device_register(&mxc_rtc_device); +} +#else +static inline void mxc_init_rtc(void) +{ +} +#endif + +#if defined(CONFIG_MXC_WATCHDOG) || defined(CONFIG_MXC_WATCHDOG_MODULE) + +static struct resource wdt_resources[] = { + { + .start = WDOG1_BASE_ADDR, + .end = WDOG1_BASE_ADDR + 0x30, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mxc_wdt_device = { + .name = "mxc_wdt", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(wdt_resources), + .resource = wdt_resources, +}; + +static void mxc_init_wdt(void) +{ + (void)platform_device_register(&mxc_wdt_device); +} +#else +static inline void mxc_init_wdt(void) +{ +} +#endif + +#if defined(CONFIG_MXC_IPU_V3) || defined(CONFIG_MXC_IPU_V3_MODULE) +static struct mxc_ipu_config mxc_ipu_data = { + .rev = 1, +}; + +static struct resource ipu_resources[] = { + { + .start = IPU_CTRL_BASE_ADDR, + .end = IPU_CTRL_BASE_ADDR + SZ_512M, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_IPU_SYN, + .flags = IORESOURCE_IRQ, + }, + { + .start = MXC_INT_IPU_ERR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxc_ipu_device = { + .name = "mxc_ipu", + .id = -1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_ipu_data, + }, + .num_resources = ARRAY_SIZE(ipu_resources), + .resource = ipu_resources, +}; + +static void mxc_init_ipu(void) +{ + mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di_clk"); + + platform_device_register(&mxc_ipu_device); +} +#else +static inline void mxc_init_ipu(void) +{ +} +#endif + +/*! + * This is platform device structure for adding SCC + */ +#if defined(CONFIG_MXC_SECURITY_SCC) || defined(CONFIG_MXC_SECURITY_SCC_MODULE) +static struct platform_device mxc_scc_device = { + .name = "mxc_scc", + .id = 0, +}; + +static void mxc_init_scc(void) +{ + platform_device_register(&mxc_scc_device); +} +#else +static inline void mxc_init_scc(void) +{ + uint32_t reg_value; + uint8_t *UMID_base; + uint32_t *MAP_base; + uint8_t i; + uint32_t partition_no; + uint32_t scc_partno; + void *scm_ram_base; + void *scc_base; + + scc_base = ioremap((uint32_t) SCC_BASE_ADDR, 0x140); + if (scc_base == NULL) { + printk(KERN_ERR "FAILED TO MAP IRAM REGS\n"); + return; + } + scm_ram_base = ioremap((uint32_t) IRAM_BASE_ADDR, IRAM_SIZE); + if (scm_ram_base == NULL) { + printk(KERN_ERR "FAILED TO MAP IRAM\n"); + return; + } + + for (partition_no = 0; partition_no < 9; partition_no++) { + reg_value = ((partition_no << SCM_ZCMD_PART_SHIFT) & + SCM_ZCMD_PART_MASK) | ((0x03 << + SCM_ZCMD_CCMD_SHIFT) + & SCM_ZCMD_CCMD_MASK); + __raw_writel(reg_value, scc_base + SCM_ZCMD_REG); + + while ((__raw_readl(scc_base + SCM_STATUS_REG) & + SCM_STATUS_SRS_READY) != SCM_STATUS_SRS_READY) ; + + __raw_writel(0, scc_base + (SCM_SMID0_REG + 8 * partition_no)); + + reg_value = __raw_readl(scc_base + SCM_PART_OWNERS_REG); + + if (((reg_value >> (2 * (partition_no))) & 3) != 3) { + printk(KERN_ERR "FAILED TO ACQUIRE IRAM PARTITION\n"); + iounmap(scm_ram_base); + return; + } + + MAP_base = scm_ram_base + (partition_no * 0x2000); + UMID_base = (uint8_t *) MAP_base + 0x10; + + for (i = 0; i < 16; i++) + UMID_base[i] = 0; + + MAP_base[0] = SCM_PERM_NO_ZEROIZE | SCM_PERM_HD_SUP_DISABLE | + SCM_PERM_HD_READ | SCM_PERM_HD_WRITE | + SCM_PERM_TH_READ | SCM_PERM_TH_WRITE; + + } + + /*Freeing 2 partitions for SCC2 */ + scc_partno = 9 - (SCC_IRAM_SIZE / SZ_8K); + for (partition_no = scc_partno; partition_no < 9; partition_no++) { + reg_value = ((partition_no << SCM_ZCMD_PART_SHIFT) & + SCM_ZCMD_PART_MASK) | ((0x03 << + SCM_ZCMD_CCMD_SHIFT) + & SCM_ZCMD_CCMD_MASK); + __raw_writel(reg_value, scc_base + SCM_ZCMD_REG); + + while ((__raw_readl(scc_base + SCM_STATUS_REG) & + SCM_STATUS_SRS_READY) != SCM_STATUS_SRS_READY) ; + } + iounmap(scm_ram_base); + iounmap(scc_base); + printk(KERN_INFO "IRAM READY\n"); + +} +#endif + +/* SPI controller and device data */ +#if defined(CONFIG_SPI_MXC) || defined(CONFIG_SPI_MXC_MODULE) + +#ifdef CONFIG_SPI_MXC_SELECT1 +/*! + * Resource definition for the CSPI1 + */ +static struct resource mxcspi1_resources[] = { + [0] = { + .start = CSPI1_BASE_ADDR, + .end = CSPI1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_CSPI1, + .end = MXC_INT_CSPI1, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC CSPI1 */ +static struct mxc_spi_master mxcspi1_data = { + .maxchipselect = 4, + .spi_version = 23, +}; + +/*! Device Definition for MXC CSPI1 */ +static struct platform_device mxcspi1_device = { + .name = "mxc_spi", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxcspi1_data, + }, + .num_resources = ARRAY_SIZE(mxcspi1_resources), + .resource = mxcspi1_resources, +}; + +#endif /* CONFIG_SPI_MXC_SELECT1 */ + +#ifdef CONFIG_SPI_MXC_SELECT2 +/*! + * Resource definition for the CSPI2 + */ +static struct resource mxcspi2_resources[] = { + [0] = { + .start = CSPI2_BASE_ADDR, + .end = CSPI2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_CSPI2, + .end = MXC_INT_CSPI2, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC CSPI2 */ +static struct mxc_spi_master mxcspi2_data = { + .maxchipselect = 4, + .spi_version = 23, +}; + +/*! Device Definition for MXC CSPI2 */ +static struct platform_device mxcspi2_device = { + .name = "mxc_spi", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxcspi2_data, + }, + .num_resources = ARRAY_SIZE(mxcspi2_resources), + .resource = mxcspi2_resources, +}; +#endif /* CONFIG_SPI_MXC_SELECT2 */ + +#ifdef CONFIG_SPI_MXC_SELECT3 +/*! + * Resource definition for the CSPI3 + */ +static struct resource mxcspi3_resources[] = { + [0] = { + .start = CSPI3_BASE_ADDR, + .end = CSPI3_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_CSPI3, + .end = MXC_INT_CSPI3, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC CSPI3 */ +static struct mxc_spi_master mxcspi3_data = { + .maxchipselect = 4, + .spi_version = 23, +}; + +/*! Device Definition for MXC CSPI3 */ +static struct platform_device mxcspi3_device = { + .name = "mxc_spi", + .id = 2, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxcspi3_data, + }, + .num_resources = ARRAY_SIZE(mxcspi3_resources), + .resource = mxcspi3_resources, +}; +#endif /* CONFIG_SPI_MXC_SELECT3 */ + +void __init mxc_init_spi(void) +{ + /* SPBA configuration for CSPI2 - MCU is set */ + spba_take_ownership(SPBA_CSPI2, SPBA_MASTER_A); +#ifdef CONFIG_SPI_MXC_SELECT1 + if (platform_device_register(&mxcspi1_device) < 0) + printk("Error: Registering the SPI Controller_1\n"); +#endif /* CONFIG_SPI_MXC_SELECT1 */ +#ifdef CONFIG_SPI_MXC_SELECT2 + if (platform_device_register(&mxcspi2_device) < 0) + printk("Error: Registering the SPI Controller_2\n"); +#endif /* CONFIG_SPI_MXC_SELECT2 */ +#ifdef CONFIG_SPI_MXC_SELECT3 + if (platform_device_register(&mxcspi3_device) < 0) + printk("Error: Registering the SPI Controller_3\n"); +#endif /* CONFIG_SPI_MXC_SELECT3 */ +} +#else +void __init mxc_init_spi(void) +{ +} +#endif + +/* I2C controller and device data */ +#if defined(CONFIG_I2C_MXC) || defined(CONFIG_I2C_MXC_MODULE) + +#ifdef CONFIG_I2C_MXC_SELECT1 +/*! + * Resource definition for the I2C1 + */ +static struct resource mxci2c1_resources[] = { + [0] = { + .start = I2C_BASE_ADDR, + .end = I2C_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_I2C, + .end = MXC_INT_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC I2C */ +static struct mxc_i2c_platform_data mxci2c1_data = { + .i2c_clk = 100000, +}; +#endif + +#ifdef CONFIG_I2C_MXC_SELECT2 +/*! + * Resource definition for the I2C2 + */ +static struct resource mxci2c2_resources[] = { + [0] = { + .start = I2C2_BASE_ADDR, + .end = I2C2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_I2C2, + .end = MXC_INT_I2C2, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC I2C */ +static struct mxc_i2c_platform_data mxci2c2_data = { + .i2c_clk = 100000, +}; +#endif + +#ifdef CONFIG_I2C_MXC_SELECT3 +/*! + * Resource definition for the I2C3 + */ +static struct resource mxci2c3_resources[] = { + [0] = { + .start = I2C3_BASE_ADDR, + .end = I2C3_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_I2C3, + .end = MXC_INT_I2C3, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC I2C */ +static struct mxc_i2c_platform_data mxci2c3_data = { + .i2c_clk = 100000, +}; +#endif + +/*! Device Definition for MXC I2C1 */ +static struct platform_device mxci2c_devices[] = { +#ifdef CONFIG_I2C_MXC_SELECT1 + { + .name = "mxc_i2c", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxci2c1_data, + }, + .num_resources = ARRAY_SIZE(mxci2c1_resources), + .resource = mxci2c1_resources,}, +#endif +#ifdef CONFIG_I2C_MXC_SELECT2 + { + .name = "mxc_i2c", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxci2c2_data, + }, + .num_resources = ARRAY_SIZE(mxci2c2_resources), + .resource = mxci2c2_resources,}, +#endif +#ifdef CONFIG_I2C_MXC_SELECT3 + { + .name = "mxc_i2c", + .id = 2, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxci2c3_data, + }, + .num_resources = ARRAY_SIZE(mxci2c3_resources), + .resource = mxci2c3_resources,}, +#endif +}; + +static inline void mxc_init_i2c(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mxci2c_devices); i++) { + if (platform_device_register(&mxci2c_devices[i]) < 0) + dev_err(&mxci2c_devices[i].dev, + "Unable to register I2C device\n"); + } +} +#else +static inline void mxc_init_i2c(void) +{ +} +#endif + +struct tve_platform_data tve_data = { + .dac_reg = "VVIDEO", + .dig_reg = "VDIG", +}; + +static struct resource tve_resources[] = { + { + .start = TVE_BASE_ADDR, + .end = TVE_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_TVOUT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxc_tve_device = { + .name = "tve", + .dev = { + .release = mxc_nop_release, + .platform_data = &tve_data, + }, + .num_resources = ARRAY_SIZE(tve_resources), + .resource = tve_resources, +}; + +void __init mxc_init_tve(void) +{ + platform_device_register(&mxc_tve_device); +} + +/*! + * Resource definition for the DVFS CORE + */ +static struct resource dvfs_core_resources[] = { + [0] = { + .start = MXC_DVFS_CORE_BASE, + .end = MXC_DVFS_CORE_BASE + 4 * SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_GPC1, + .end = MXC_INT_GPC1, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for DVFS CORE */ +struct mxc_dvfs_platform_data dvfs_core_data = { + .reg_id = "SW1", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_reg_addr = MXC_GPC_CNTR, + .gpc_vcr_reg_addr = MXC_GPC_VCR, + .dvfs_thrs_reg_addr = MXC_DVFSTHRS, + .dvfs_coun_reg_addr = MXC_DVFSCOUN, + .dvfs_emac_reg_addr = MXC_DVFSEMAC, + .dvfs_cntr_reg_addr = MXC_DVFSCNTR, + .div3ck_mask = 0x00000006, + .div3ck_offset = 1, + .div3ck_val = 3, + .emac_val = 0x10, + .upthr_val = 28, + .dnthr_val = 10, + .pncthr_val = 33, + .upcnt_val = 5, + .dncnt_val = 5, + .delay_time = 100, + .num_wp = 3, +}; + +/*! Device Definition for MXC DVFS core */ +static struct platform_device mxc_dvfs_core_device = { + .name = "mxc_dvfs_core", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &dvfs_core_data, + }, + .num_resources = ARRAY_SIZE(dvfs_core_resources), + .resource = dvfs_core_resources, +}; + +static inline void mxc_init_dvfs(void) +{ + if (platform_device_register(&mxc_dvfs_core_device) < 0) + dev_err(&mxc_dvfs_core_device.dev, + "Unable to register DVFS core device\n"); +} + +/*! + * Resource definition for the DPTC GP + */ +static struct resource dptc_gp_resources[] = { + [0] = { + .start = MXC_DPTC_GP_BASE, + .end = MXC_DPTC_GP_BASE + 8 * SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_GPC1, + .end = MXC_INT_GPC1, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for DPTC GP */ +struct mxc_dptc_data dptc_gp_data = { + .reg_id = "SW1", + .clk_id = "cpu_clk", + .dptccr_reg_addr = MXC_GP_DPTCCR, + .dcvr0_reg_addr = MXC_GP_DCVR0, + .gpc_cntr_reg_addr = MXC_GPC_CNTR, + .dptccr = MXC_GPCCNTR_DPTC0CR, + .dptc_wp_supported = DPTC_GP_WP_SUPPORTED, + .dptc_wp_allfreq = dptc_gp_wp_allfreq, + .clk_max_val = 532000000, + .gpc_adu = MXC_GPCCNTR_ADU, + .vai_mask = MXC_DPTCCR_VAI_MASK, + .vai_offset = MXC_DPTCCR_VAI_OFFSET, + .dptc_enable_bit = MXC_DPTCCR_DEN, + .irq_mask = MXC_DPTCCR_VAIM, + .dptc_nvcr_bit = MXC_DPTCCR_DPNVCR, + .gpc_irq_bit = MXC_GPCCNTR_GPCIRQ, + .init_config = + MXC_DPTCCR_DRCE0 | MXC_DPTCCR_DRCE1 | MXC_DPTCCR_DRCE2 | + MXC_DPTCCR_DRCE3 | MXC_DPTCCR_DCR_128 | MXC_DPTCCR_DPNVCR | + MXC_DPTCCR_DPVV, + .enable_config = + MXC_DPTCCR_DEN | MXC_DPTCCR_DPNVCR | MXC_DPTCCR_DPVV | + MXC_DPTCCR_DSMM, + .dcr_mask = MXC_DPTCCR_DCR_256, +}; + +/*! + * Resource definition for the DPTC LP + */ +static struct resource dptc_lp_resources[] = { + [0] = { + .start = MXC_DPTC_LP_BASE, + .end = MXC_DPTC_LP_BASE + 8 * SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_GPC1, + .end = MXC_INT_GPC1, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC DPTC LP */ +struct mxc_dptc_data dptc_lp_data = { + .reg_id = "SW2", + .clk_id = "ahb_clk", + .dptccr_reg_addr = MXC_LP_DPTCCR, + .dcvr0_reg_addr = MXC_LP_DCVR0, + .gpc_cntr_reg_addr = MXC_GPC_CNTR, + .dptccr = MXC_GPCCNTR_DPTC1CR, + .dptc_wp_supported = DPTC_LP_WP_SUPPORTED, + .dptc_wp_allfreq = dptc_lp_wp_allfreq, + .clk_max_val = 133000000, + .gpc_adu = 0x0, + .vai_mask = MXC_DPTCCR_VAI_MASK, + .vai_offset = MXC_DPTCCR_VAI_OFFSET, + .dptc_enable_bit = MXC_DPTCCR_DEN, + .irq_mask = MXC_DPTCCR_VAIM, + .dptc_nvcr_bit = MXC_DPTCCR_DPNVCR, + .gpc_irq_bit = MXC_GPCCNTR_GPCIRQ, + .init_config = + MXC_DPTCCR_DRCE0 | MXC_DPTCCR_DRCE1 | MXC_DPTCCR_DRCE2 | + MXC_DPTCCR_DRCE3 | MXC_DPTCCR_DCR_128 | MXC_DPTCCR_DPNVCR | + MXC_DPTCCR_DPVV, + .enable_config = + MXC_DPTCCR_DEN | MXC_DPTCCR_DPNVCR | MXC_DPTCCR_DPVV | + MXC_DPTCCR_DSMM, + .dcr_mask = MXC_DPTCCR_DCR_256, +}; + +/*! Device Definition for MXC DPTC */ +static struct platform_device mxc_dptc_devices[] = { + { + .name = "mxc_dptc", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &dptc_gp_data, + }, + .num_resources = ARRAY_SIZE(dptc_gp_resources), + .resource = dptc_gp_resources, + }, + { + .name = "mxc_dptc", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &dptc_lp_data, + }, + .num_resources = ARRAY_SIZE(dptc_lp_resources), + .resource = dptc_lp_resources, + }, +}; + +static inline void mxc_init_dptc(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mxc_dptc_devices); i++) { + if (platform_device_register(&mxc_dptc_devices[i]) < 0) + dev_err(&mxc_dptc_devices[i].dev, + "Unable to register DPTC device\n"); + } +} + +struct mxc_gpio_port mxc_gpio_ports[GPIO_PORT_NUM] = { + { + .num = 0, + .base = IO_ADDRESS(GPIO1_BASE_ADDR), + .irq_0_15 = MXC_INT_GPIO1_LOW, + .irq_16_31 = MXC_INT_GPIO1_HIGH, + .virtual_irq_start = MXC_GPIO_INT_BASE, + }, + { + .num = 1, + .base = IO_ADDRESS(GPIO2_BASE_ADDR), + .irq_0_15 = MXC_INT_GPIO2_LOW, + .irq_16_31 = MXC_INT_GPIO2_HIGH, + .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 1, + }, + { + .num = 2, + .base = IO_ADDRESS(GPIO3_BASE_ADDR), + .irq_0_15 = MXC_INT_GPIO3_LOW, + .irq_16_31 = MXC_INT_GPIO3_HIGH, + .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 2, + }, +}; + +#if defined(CONFIG_MXC_VPU) || defined(CONFIG_MXC_VPU_MODULE) +static struct resource vpu_resources[] = { + { + .start = VPU_IRAM_BASE_ADDR, + .end = VPU_IRAM_BASE_ADDR + VPU_IRAM_SIZE, + .flags = IORESOURCE_MEM, + }, +}; + +/*! Platform Data for MXC VPU */ +static struct platform_device mxcvpu_device = { + .name = "mxc_vpu", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(vpu_resources), + .resource = vpu_resources, +}; + +static inline void mxc_init_vpu(void) +{ + if (platform_device_register(&mxcvpu_device) < 0) + printk(KERN_ERR "Error: Registering the VPU.\n"); +} +#else +static inline void mxc_init_vpu(void) +{ +} +#endif + +static struct platform_device mxc_dma_device = { + .name = "mxc_dma", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, +}; + +static inline void mxc_init_dma(void) +{ + (void)platform_device_register(&mxc_dma_device); +} + +static struct resource spdif_resources[] = { + { + .start = SPDIF_BASE_ADDR, + .end = SPDIF_BASE_ADDR + 0x50, + .flags = IORESOURCE_MEM, + }, +}; + +static struct mxc_spdif_platform_data mxc_spdif_data = { + .spdif_tx = 1, + .spdif_rx = 0, + .spdif_clk_44100 = 0, + .spdif_clk_48000 = 3, + .spdif_clk = NULL, + .spdif_core_clk = NULL, +}; + +static struct platform_device mxc_alsa_spdif_device = { + .name = "mxc_alsa_spdif", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_spdif_data, + }, + .num_resources = ARRAY_SIZE(spdif_resources), + .resource = spdif_resources, +}; + +static inline void mxc_init_spdif(void) +{ + struct clk *ckih_clk; + ckih_clk = clk_get(NULL, "ckih"); + mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk"); + clk_set_parent(mxc_spdif_data.spdif_core_clk, ckih_clk); + clk_put(ckih_clk); + clk_put(mxc_spdif_data.spdif_core_clk); + platform_device_register(&mxc_alsa_spdif_device); +} + +static struct platform_device mx37_lpmode_device = { + .name = "mx37_lpmode", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, +}; + +static inline void mx37_init_lpmode(void) +{ + (void)platform_device_register(&mx37_lpmode_device); +} + +#if defined(CONFIG_HW_RANDOM_FSL_RNGC) || \ +defined(CONFIG_HW_RANDOM_FSL_RNGC_MODULE) +static struct resource rngc_resources[] = { + { + .start = RNGC_BASE_ADDR, + .end = RNGC_BASE_ADDR + 0x34, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_RNG, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device fsl_rngc_device = { + .name = "fsl_rngc", + .id = -1, + .num_resources = ARRAY_SIZE(rngc_resources), + .resource = rngc_resources, +}; + +static inline void mxc_init_rngc(void) +{ + platform_device_register(&fsl_rngc_device); +} +#else +static inline void mxc_init_rngc(void) +{ +} +#endif + +int __init mxc_init_devices(void) +{ + mxc_init_wdt(); + mxc_init_ipu(); + mxc_init_spi(); + mxc_init_i2c(); + mxc_init_rtc(); + mxc_init_owire(); + mxc_init_scc(); + mxc_init_dma(); + mxc_init_vpu(); + mxc_init_spdif(); + mxc_init_tve(); + mx37_init_lpmode(); + mxc_init_dvfs(); + mxc_init_dptc(); + mxc_init_rngc(); + + /* SPBA configuration for SSI2 - SDMA and MCU are set */ + spba_take_ownership(SPBA_SSI2, SPBA_MASTER_C | SPBA_MASTER_A); + return 0; +} diff -urN linux-2.6.26/arch/arm/mach-mx37/dma.c linux-2.6.26-lab126/arch/arm/mach-mx37/dma.c --- linux-2.6.26/arch/arm/mach-mx37/dma.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/dma.c 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,666 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include + +#include "serial.h" + +#define MXC_MMC_BUFFER_ACCESS 0x20 +#define MXC_SDHC_MMC_WML 512 +#define MXC_SDHC_SD_WML 512 +#define MXC_SSI_TX0_REG 0x0 +#define MXC_SSI_TX1_REG 0x4 +#define MXC_SSI_RX0_REG 0x8 +#define MXC_SSI_RX1_REG 0xC +#define MXC_SSI_TXFIFO_WML 0x4 +#define MXC_SSI_RXFIFO_WML 0x6 +#define MXC_SPDIF_TXFIFO_WML 0x0 +#define MXC_SPDIF_TX_REG 0x2C + +typedef struct mxc_sdma_info_entry_s { + mxc_dma_device_t device; + mxc_sdma_channel_params_t *chnl_info; +} mxc_sdma_info_entry_t; + +static mxc_sdma_channel_params_t mxc_sdma_uart1_rx_params = { + .chnl_params = { + .watermark_level = UART1_UFCR_RXTL, + .per_address = UART1_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART1_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART1_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart1_tx_params = { + .chnl_params = { + .watermark_level = UART1_UFCR_TXTL, + .per_address = UART1_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART1_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART1_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart2_rx_params = { + .chnl_params = { + .watermark_level = UART2_UFCR_RXTL, + .per_address = UART2_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART2_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART2_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart2_tx_params = { + .chnl_params = { + .watermark_level = UART2_UFCR_TXTL, + .per_address = UART2_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART2_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART2_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart3_rx_params = { + .chnl_params = { + .watermark_level = UART3_UFCR_RXTL, + .per_address = UART3_BASE_ADDR, + .peripheral_type = UART_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART3_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART3_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart3_tx_params = { + .chnl_params = { + .watermark_level = UART3_UFCR_TXTL, + .per_address = UART3_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART3_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART3_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc1_width1_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_MMC_WML, + .per_address = + MMC_SDHC1_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SDHC1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MMC1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc1_width4_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_SD_WML, + .per_address = + MMC_SDHC1_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SDHC1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MMC1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc2_width1_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_MMC_WML / 32, + .per_address = + MMC_SDHC2_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SDHC2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MMC2, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc2_width4_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_SD_WML / 8, + .per_address = + MMC_SDHC2_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SDHC2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MMC2, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_memory_params = { + .chnl_params = { + .peripheral_type = MEMORY, + .transfer_type = emi_2_emi, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MEMORY, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ata_rx_params = { + .chnl_params = { + .watermark_level = MXC_IDE_DMA_WATERMARK, + .per_address = ATA_DMA_BASE_ADDR, + .peripheral_type = ATA, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ATA_TX_END, + .event_id2 = DMA_REQ_ATA_RX, + .bd_number = MXC_IDE_DMA_BD_NR, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ATA_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ata_tx_params = { + .chnl_params = { + .watermark_level = MXC_IDE_DMA_WATERMARK, + .per_address = ATA_DMA_BASE_ADDR + 0x18, + .peripheral_type = ATA, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_ATA_TX_END, + .event_id2 = DMA_REQ_ATA_TX, + .bd_number = MXC_IDE_DMA_BD_NR, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ATA_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_spdif_16bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_SPDIF_TXFIFO_WML, + .per_address = SPDIF_BASE_ADDR + MXC_SPDIF_TX_REG, + .peripheral_type = SPDIF, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SPDIF_TX, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SPDIF_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_spdif_32bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_SPDIF_TXFIFO_WML, + .per_address = SPDIF_BASE_ADDR + MXC_SPDIF_TX_REG, + .peripheral_type = SPDIF, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SPDIF_TX, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SPDIF_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_info_entry_t mxc_sdma_active_dma_info[] = { + {MXC_DMA_UART1_RX, &mxc_sdma_uart1_rx_params}, + {MXC_DMA_UART1_TX, &mxc_sdma_uart1_tx_params}, + {MXC_DMA_UART2_RX, &mxc_sdma_uart2_rx_params}, + {MXC_DMA_UART2_TX, &mxc_sdma_uart2_tx_params}, + {MXC_DMA_UART3_RX, &mxc_sdma_uart3_rx_params}, + {MXC_DMA_UART3_TX, &mxc_sdma_uart3_tx_params}, + {MXC_DMA_MMC1_WIDTH_1, &mxc_sdma_mmc1_width1_params}, + {MXC_DMA_MMC1_WIDTH_4, &mxc_sdma_mmc1_width4_params}, + {MXC_DMA_MMC2_WIDTH_1, &mxc_sdma_mmc2_width1_params}, + {MXC_DMA_MMC2_WIDTH_4, &mxc_sdma_mmc2_width4_params}, + {MXC_DMA_SSI1_8BIT_RX0, &mxc_sdma_ssi1_8bit_rx0_params}, + {MXC_DMA_SSI1_8BIT_TX0, &mxc_sdma_ssi1_8bit_tx0_params}, + {MXC_DMA_SSI1_16BIT_RX0, &mxc_sdma_ssi1_16bit_rx0_params}, + {MXC_DMA_SSI1_16BIT_TX0, &mxc_sdma_ssi1_16bit_tx0_params}, + {MXC_DMA_SSI1_24BIT_RX0, &mxc_sdma_ssi1_24bit_rx0_params}, + {MXC_DMA_SSI1_24BIT_TX0, &mxc_sdma_ssi1_24bit_tx0_params}, + {MXC_DMA_SSI1_8BIT_RX1, &mxc_sdma_ssi1_8bit_rx1_params}, + {MXC_DMA_SSI1_8BIT_TX1, &mxc_sdma_ssi1_8bit_tx1_params}, + {MXC_DMA_SSI1_16BIT_RX1, &mxc_sdma_ssi1_16bit_rx1_params}, + {MXC_DMA_SSI1_16BIT_TX1, &mxc_sdma_ssi1_16bit_tx1_params}, + {MXC_DMA_SSI1_24BIT_RX1, &mxc_sdma_ssi1_24bit_rx1_params}, + {MXC_DMA_SSI1_24BIT_TX1, &mxc_sdma_ssi1_24bit_tx1_params}, + {MXC_DMA_SSI2_8BIT_RX0, &mxc_sdma_ssi2_8bit_rx0_params}, + {MXC_DMA_SSI2_8BIT_TX0, &mxc_sdma_ssi2_8bit_tx0_params}, + {MXC_DMA_SSI2_16BIT_RX0, &mxc_sdma_ssi2_16bit_rx0_params}, + {MXC_DMA_SSI2_16BIT_TX0, &mxc_sdma_ssi2_16bit_tx0_params}, + {MXC_DMA_SSI2_24BIT_RX0, &mxc_sdma_ssi2_24bit_rx0_params}, + {MXC_DMA_SSI2_24BIT_TX0, &mxc_sdma_ssi2_24bit_tx0_params}, + {MXC_DMA_SSI2_8BIT_RX1, &mxc_sdma_ssi2_8bit_rx1_params}, + {MXC_DMA_SSI2_8BIT_TX1, &mxc_sdma_ssi2_8bit_tx1_params}, + {MXC_DMA_SSI2_16BIT_RX1, &mxc_sdma_ssi2_16bit_rx1_params}, + {MXC_DMA_SSI2_16BIT_TX1, &mxc_sdma_ssi2_16bit_tx1_params}, + {MXC_DMA_SSI2_24BIT_RX1, &mxc_sdma_ssi2_24bit_rx1_params}, + {MXC_DMA_SSI2_24BIT_TX1, &mxc_sdma_ssi2_24bit_tx1_params}, + {MXC_DMA_MEMORY, &mxc_sdma_memory_params}, + {MXC_DMA_ATA_RX, &mxc_sdma_ata_rx_params}, + {MXC_DMA_ATA_TX, &mxc_sdma_ata_tx_params}, + {MXC_DMA_SPDIF_16BIT_TX, &mxc_sdma_spdif_16bit_tx_params}, + {MXC_DMA_SPDIF_32BIT_TX, &mxc_sdma_spdif_32bit_tx_params}, +}; + +static int mxc_sdma_info_entrys = + sizeof(mxc_sdma_active_dma_info) / sizeof(mxc_sdma_active_dma_info[0]); + +/*! + * This functions Returns the SDMA paramaters associated for a module + * + * @param channel_id the ID of the module requesting DMA + * @return returns the sdma parameters structure for the device + */ +mxc_sdma_channel_params_t *mxc_sdma_get_channel_params(mxc_dma_device_t + channel_id) +{ + mxc_sdma_info_entry_t *p = mxc_sdma_active_dma_info; + int i; + + for (i = 0; i < mxc_sdma_info_entrys; i++, p++) { + if (p->device == channel_id) { + return p->chnl_info; + } + } + return NULL; +} + +/*! + * This functions marks the SDMA channels that are statically allocated + * + * @param chnl the channel array used to store channel information + */ +void mxc_get_static_channels(mxc_dma_channel_t * chnl) +{ +#ifdef CONFIG_SDMA_IRAM + int i; + for (i = MXC_DMA_CHANNEL_IRAM; i < MAX_DMA_CHANNELS; i++) + chnl[i].dynamic = 0; +#endif +} + +EXPORT_SYMBOL(mxc_sdma_get_channel_params); +EXPORT_SYMBOL(mxc_get_static_channels); diff -urN linux-2.6.26/arch/arm/mach-mx37/dptc.c linux-2.6.26-lab126/arch/arm/mach-mx37/dptc.c --- linux-2.6.26/arch/arm/mach-mx37/dptc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/dptc.c 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,69 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dptc_gp.c + * + * @brief DPTC table for the Freescale Semiconductor MXC DPTC module. + * + * @ingroup PM + */ + +#include +#include + +struct dptc_wp dptc_gp_wp_allfreq[DPTC_GP_WP_SUPPORTED] = { + /* 532MHz */ + /* dcvr0 dcvr1 dcvr2 + dcvr3 voltage */ + /* wp0 */ + {DCVR(107, 108, 112), DCVR(122, 123, 127), DCVR(133, 134, 139), + DCVR(115, 116, 121), 1000}, + {DCVR(107, 108, 113), DCVR(122, 123, 127), DCVR(133, 134, 139), + DCVR(115, 117, 122), 975}, + {DCVR(107, 109, 113), DCVR(122, 123, 127), DCVR(133, 134, 139), + DCVR(115, 117, 122), 950}, + {DCVR(107, 109, 114), DCVR(122, 123, 127), DCVR(133, 135, 140), + DCVR(115, 117, 122), 925}, + {DCVR(108, 109, 115), DCVR(122, 123, 127), DCVR(133, 136, 142), + DCVR(115, 117, 123), 900}, + {DCVR(108, 110, 115), DCVR(122, 123, 127), DCVR(133, 136, 142), + DCVR(115, 117, 123), 875}, + {DCVR(108, 110, 115), DCVR(122, 124, 128), DCVR(133, 136, 143), + DCVR(115, 118, 124), 850}, +}; + +struct dptc_wp dptc_lp_wp_allfreq[DPTC_LP_WP_SUPPORTED] = { + /* 532MHz */ + /* dcvr0 dcvr1 dcvr2 + dcvr3 regulator voltage */ + /* wp0 */ + {DCVR(141, 143, 149), DCVR(155, 157, 162), DCVR(106, 108, 112), + DCVR(124, 126, 130), 1200}, + {DCVR(141, 143, 149), DCVR(155, 157, 162), DCVR(106, 108, 113), + DCVR(124, 126, 131), 1175}, + {DCVR(141, 144, 150), DCVR(155, 157, 163), DCVR(106, 108, 113), + DCVR(124, 126, 131), 1150}, + {DCVR(141, 144, 151), DCVR(155, 157, 163), DCVR(106, 108, 114), + DCVR(124, 126, 131), 1125}, + {DCVR(142, 144, 152), DCVR(155, 157, 163), DCVR(107, 109, 114), + DCVR(125, 127, 132), 1100}, + {DCVR(142, 145, 153), DCVR(155, 157, 164), DCVR(107, 109, 115), + DCVR(125, 127, 133), 1075}, + {DCVR(142, 145, 153), DCVR(155, 158, 164), DCVR(107, 109, 116), + DCVR(125, 127, 133), 1050}, + {DCVR(142, 145, 154), DCVR(155, 158, 165), DCVR(107, 110, 117), + DCVR(125, 127, 134), 1025}, + {DCVR(142, 146, 156), DCVR(155, 158, 165), DCVR(107, 110, 117), + DCVR(125, 128, 135), 1000}, +}; diff -urN linux-2.6.26/arch/arm/mach-mx37/iomux.c linux-2.6.26-lab126/arch/arm/mach-mx37/iomux.c --- linux-2.6.26/arch/arm/mach-mx37/iomux.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/iomux.c 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,204 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup GPIO_MX37 Board GPIO and Muxing Setup + * @ingroup MSL_MX37 + */ +/*! + * @file mach-mx37/iomux.c + * + * @brief I/O Muxing control functions + * + * @ingroup GPIO_MX37 + */ + +#include +#include +#include +#include +#include "iomux.h" + +/*! + * IOMUX register (base) addresses + */ +enum iomux_reg_addr { + IOMUXGPR0 = IO_ADDRESS(IOMUXC_BASE_ADDR), /*!< General purpose 0 */ + IOMUXGPR1 = IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x004, /*!< General purpose 1 */ + IOMUXSW_MUX_CTL = IO_ADDRESS(IOMUXC_BASE_ADDR) + MUX_I_START, /*!< MUX control */ + IOMUXSW_MUX_END = IO_ADDRESS(IOMUXC_BASE_ADDR) + PAD_I_END, /*!< last MUX control register */ + IOMUXSW_PAD_CTL = IO_ADDRESS(IOMUXC_BASE_ADDR) + PAD_I_START, /*!< Pad control */ + IOMUXSW_PAD_END = IO_ADDRESS(IOMUXC_BASE_ADDR) + PAD_I_END, /*!< last Pad control register */ + IOMUXSW_INPUT_CTL = IO_ADDRESS(IOMUXC_BASE_ADDR) + INPUT_CTL_START, /*!< input select register */ + IOMUXSW_INPUT_END = IO_ADDRESS(IOMUXC_BASE_ADDR) + INPUT_CTL_END, /*!< last input select register */ +}; + +#define MUX_PIN_NUM_MAX (((IOMUXSW_MUX_END - IOMUXSW_MUX_CTL) >> 2) + 1) +#define MUX_INPUT_NUM_MUX (((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1) + +static u8 iomux_pin_res_table[MUX_PIN_NUM_MAX]; +static DEFINE_SPINLOCK(gpio_mux_lock); + +/*! + * This function is used to configure a pin through the IOMUX module. + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config a configuration as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t config) +{ + u32 ret = 0; + u32 pin_index = PIN_TO_IOMUX_INDEX(pin); + u32 mux_reg = IOMUXSW_MUX_CTL + PIN_TO_IOMUX_MUX(pin); + u32 mux_data = 0; + u8 *rp; + + BUG_ON((mux_reg > IOMUXSW_MUX_END) || (mux_reg < IOMUXSW_MUX_CTL)); + spin_lock(&gpio_mux_lock); + + if (config == IOMUX_CONFIG_GPIO) { + mux_data = PIN_TO_ALT_GPIO(pin); + } else { + mux_data = config; + } + + __raw_writel(mux_data, mux_reg); + + /* + * Log a warning if a pin changes ownership + */ + rp = iomux_pin_res_table + pin_index; + if ((mux_data & *rp) && (*rp != mux_data)) { + /* + * Don't call printk if we're tweaking the console uart or + * we'll deadlock. + */ + printk(KERN_ERR "iomux_config_mux: Warning: iomux pin" + " config changed, pin=%d, " + " prev=0x%x new=0x%x\n", mux_reg, *rp, mux_data); + ret = -EINVAL; + } + *rp = mux_data; + spin_unlock(&gpio_mux_lock); + return ret; +} + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param config a configuration as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config) +{ + int ret = iomux_config_mux(pin, config); + int gpio_port = GPIO_TO_PORT(IOMUX_TO_GPIO(pin)); + + if (!ret && (gpio_port != NON_GPIO_PORT) + && ((config == IOMUX_CONFIG_GPIO) + || (config == PIN_TO_ALT_GPIO(pin)))) { + ret |= mxc_request_gpio(pin); + } + return ret; +} + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param config config as defined in \b #iomux_pin_ocfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config) +{ + u32 pin_index = PIN_TO_IOMUX_INDEX(pin); + u8 *rp = iomux_pin_res_table + pin_index; + int gpio_port = GPIO_TO_PORT(IOMUX_TO_GPIO(pin)); + + BUG_ON(pin_index > MUX_PIN_NUM_MAX); + *rp = 0; + if ((gpio_port != NON_GPIO_PORT) + && ((config == IOMUX_CONFIG_GPIO) + || (config == PIN_TO_ALT_GPIO(pin)))) { + mxc_free_gpio(pin); + } +} + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) +{ + u32 pad_reg = IOMUXSW_PAD_CTL + PIN_TO_IOMUX_PAD(pin); + + BUG_ON((pad_reg > IOMUXSW_PAD_END) || (pad_reg < IOMUXSW_PAD_CTL)); + spin_lock(&gpio_mux_lock); + __raw_writel(config, pad_reg); + spin_unlock(&gpio_mux_lock); +} + +unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin) +{ + volatile u32 pad_reg = IOMUXSW_PAD_CTL + PIN_TO_IOMUX_PAD(pin); + return __raw_readl(pad_reg); +} + +/*! + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in \b #iomux_gp_func_t + * @param en \b #true to enable; \b #false to disable + * @param index 0 for GPR0 and 1 for GPR1 + */ +void mxc_iomux_set_gpr(iomux_gp_func_t gp, bool en, u8 index) +{ + volatile u32 l; + + spin_lock(&gpio_mux_lock); + l = __raw_readl(IOMUXGPR0 + (index << 2)); + if (en) { + l |= gp; + } else { + l &= ~gp; + } + __raw_writel(l, IOMUXGPR0 + (index << 2)); + spin_unlock(&gpio_mux_lock); +} + +/*! + * This function configures input path. + * + * @param input index of input select register as defined in \b #iomux_input_select_t + * @param config the binary value of elements defined in \b #iomux_input_config_t + * */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config) +{ + u32 reg = IOMUXSW_INPUT_CTL + (input << 2); + + BUG_ON(input >= MUX_INPUT_NUM_MUX); + __raw_writel(config, reg); +} + +EXPORT_SYMBOL(mxc_request_iomux); +EXPORT_SYMBOL(mxc_free_iomux); +EXPORT_SYMBOL(mxc_iomux_set_input); +EXPORT_SYMBOL(mxc_iomux_set_pad); +EXPORT_SYMBOL(mxc_iomux_set_gpr); diff -urN linux-2.6.26/arch/arm/mach-mx37/iomux.h linux-2.6.26-lab126/arch/arm/mach-mx37/iomux.h --- linux-2.6.26/arch/arm/mach-mx37/iomux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/iomux.h 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,226 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MACH_MX37_IOMUX_H__ +#define __MACH_MX37_IOMUX_H__ + +#include +#include +#include "mx37_pins.h" + +/*! + * @file mach-mx37/iomux.h + * + * @brief I/O Muxing control definitions and functions + * + * @ingroup GPIO_MX37 + */ + +/*! + * various IOMUX output functions + */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */ + IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */ + IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */ + IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */ + IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */ + IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */ + IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */ + IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */ + IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +/*! + * various IOMUX pad functions + */ +typedef enum iomux_pad_config { + PAD_CTL_SRE_SLOW = 0x0 << 0, + PAD_CTL_SRE_FAST = 0x1 << 0, + PAD_CTL_DRV_LOW = 0x0 << 1, + PAD_CTL_DRV_MEDIUM = 0x1 << 1, + PAD_CTL_DRV_HIGH = 0x2 << 1, + PAD_CTL_DRV_MAX = 0x3 << 1, + PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, + PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3, + PAD_CTL_100K_PD = 0x0 << 4, + PAD_CTL_47K_PU = 0x1 << 4, + PAD_CTL_100K_PU = 0x2 << 4, + PAD_CTL_22K_PU = 0x3 << 4, + PAD_CTL_PUE_KEEPER = 0x0 << 6, + PAD_CTL_PUE_PULL = 0x1 << 6, + PAD_CTL_PKE_NONE = 0x0 << 7, + PAD_CTL_PKE_ENABLE = 0x1 << 7, + PAD_CTL_HYS_NONE = 0x0 << 8, + PAD_CTL_HYS_ENABLE = 0x1 << 8, + PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9, + PAD_CTL_DDR_INPUT_DDR = 0x1 << 9, + PAD_CTL_DRV_VOT_LOW = 0x0 << 13, + PAD_CTL_DRV_VOT_HIGH = 0x1 << 13, +} iomux_pad_config_t; + +/*! + * various IOMUX general purpose functions + */ +typedef enum iomux_gp_func { + MUX_IPD_ESDHC_DREQ_B = 0x0 << 0, + MUX_XDRQ = 0x1 << 0, + MUX_EMI_DMA_ACCESS_1 = 0x0 << 4, + MUX_KEY_COL2 = 0x1 << 4, + MUX_TAMPER_DETECT_EN = 0x1 << 8, + MUX_IPUv3D_TVE = 0x0 << 12, + MUX_IPUv3D_CAMP = 0x1 << 12, +} iomux_gp_func_t; + +/*! + * various IOMUX input select register index + */ +typedef enum iomux_input_select { + MUX_IN_CCM_PLL1_BYPASS_CLK = 0, + MUX_IN_CCM_PLL2_BYPASS_CLK, + MUX_IN_CCM_PLL3_BYPASS_CLK, + MUX_IN_CSPI3_CSPI_CLK, + MUX_IN_CSPI3_MISO, + MUX_IN_CSPI3_MOSI, + MUX_IN_EMI_READ_MADDR_DATA_0, + MUX_IN_EMI_READ_MADDR_DATA_10, + MUX_IN_EMI_READ_MADDR_DATA_11, + MUX_IN_EMI_READ_MADDR_DATA_12, + MUX_IN_EMI_READ_MADDR_DATA_13, + MUX_IN_EMI_READ_MADDR_DATA_14, + MUX_IN_EMI_READ_MADDR_DATA_15, + MUX_IN_EMI_READ_MADDR_DATA_1, + MUX_IN_EMI_READ_MADDR_DATA_2, + MUX_IN_EMI_READ_MADDR_DATA_3, + MUX_IN_EMI_READ_MADDR_DATA_4, + MUX_IN_EMI_READ_MADDR_DATA_5, + MUX_IN_EMI_READ_MADDR_DATA_6, + MUX_IN_EMI_READ_MADDR_DATA_7, + MUX_IN_EMI_READ_MADDR_DATA_8, + MUX_IN_EMI_READ_MADDR_DATA_9, + MUX_IN_EMI_NFC_READ_DATA_IN_0, + MUX_IN_EMI_NFC_READ_DATA_IN_10, + MUX_IN_EMI_NFC_READ_DATA_IN_11, + MUX_IN_EMI_NFC_READ_DATA_IN_12, + MUX_IN_EMI_NFC_READ_DATA_IN_13, + MUX_IN_EMI_NFC_READ_DATA_IN_14, + MUX_IN_EMI_NFC_READ_DATA_IN_15, + MUX_IN_EMI_NFC_READ_DATA_IN_1, + MUX_IN_EMI_NFC_READ_DATA_IN_2, + MUX_IN_EMI_NFC_READ_DATA_IN_3, + MUX_IN_EMI_NFC_READ_DATA_IN_4, + MUX_IN_EMI_NFC_READ_DATA_IN_5, + MUX_IN_EMI_NFC_READ_DATA_IN_6, + MUX_IN_EMI_NFC_READ_DATA_IN_7, + MUX_IN_EMI_NFC_READ_DATA_IN_8, + MUX_IN_EMI_NFC_READ_DATA_IN_9, + MUX_IN_FEC_FEC_COL, + MUX_IN_FEC_FEC_CRS, MUX_IN_FEC_FEC_MDI, + MUX_IN_FEC_FEC_RDATA_0, + MUX_IN_FEC_FEC_RX_CLK, + MUX_IN_FEC_FEC_RX_DV, + MUX_IN_FEC_FEC_RX_ER, + MUX_IN_FEC_FEC_TX_CLK, + MUX_IN_I2C1_SCL, + MUX_IN_I2C1_SDA, + MUX_IN_I2C2_SCL, + MUX_IN_I2C2_SDA, + MUX_IN_I2C3_SCL, + MUX_IN_I2C3_SDA, + MUX_IN_IPU_DI_0_IND_DISPB_D0_VSYNC, + MUX_IN__IPU_DI_0_IND_DISPB_SD_D, + MUX_IN_KPP_ROW_0, + MUX_IN_KPP_ROW_1, + MUX_IN_KPP_ROW_2, + MUX_IN_KPP_ROW_3, + MUX_IN_KPP_ROW_4, + MUX_IN_KPP_ROW_5, + MUX_IN_KPP_ROW_6, + MUX_IN_KPP_ROW_7, + MUX_IN_UART1_UART_RTS_B, + MUX_IN_UART1_UART_RXD_MUX, + MUX_IN_UART2_UART_RTS_B, + MUX_IN_UART2_UART_RXD_MUX, + MUX_IN_UART3_UART_RTS_B, + MUX_IN_UART3_UART_RXD_MUX, +} iomux_input_select_t; + +/*! + * various IOMUX input functions + */ +typedef enum iomux_input_config { + INPUT_CTL_PATH0 = 0x0, + INPUT_CTL_PATH1, + INPUT_CTL_PATH2, + INPUT_CTL_PATH3, + INPUT_CTL_PATH4, + INPUT_CTL_PATH5, + INPUT_CTL_PATH6, + INPUT_CTL_PATH7, +} iomux_input_config_t; + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param config config as defined in \b #iomux_pin_ocfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param config config as defined in \b #iomux_pin_ocfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); + +/*! + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in \b #iomux_gp_func_t + * @param en \b #true to enable; \b #false to disable + * @param index 0 for GPR0 and 1 for GPR1 + */ +void mxc_iomux_set_gpr(iomux_gp_func_t gp, bool en, u8 index); + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); + +/*! + * This function gets the current pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @return current pad value + */ +unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin); + +/*! + * This function configures input path. + * + * @param input index of input select register as defined in \b #iomux_input_select_t + * @param config the binary value of elements defined in \b #iomux_input_config_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config); + +#endif /* __MACH_MX37_IOMUX_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx37/lpmodes.c linux-2.6.26-lab126/arch/arm/mach-mx37/lpmodes.c --- linux-2.6.26/arch/arm/mach-mx37/lpmodes.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/lpmodes.c 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,408 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mx37_lpmodes.c + * + * @brief Driver for the Freescale Semiconductor MXC low power modes setup. + * + * MX37 is designed to play and video with minimal power consumption. + * This driver enables the platform to enter and exit audio and video low + * power modes. + * + * @ingroup PM + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "crm_regs.h" + +#define ARM_LP_CLK 200000000 +#define GP_LPM_VOLTAGE 850000 +#define LP_LPM_VOLTAGE 1000000 +#define GP_NORMAL_VOLTAGE 1000000 +#define LP_NORMAL_VOLTAGE 1200000 + +static int org_cpu_rate; +int lp_video_mode; +int lp_audio_mode; +static struct device *lpmode_dev; + +void enter_lp_video_mode(void) +{ + int ret = 0; + + struct clk *p_clk; + struct clk *tclk; + struct clk *vmode_parent_clk; + struct regulator *gp_core; + + tclk = clk_get(NULL, "main_bus_clk"); + vmode_parent_clk = clk_get(NULL, "pll2"); + p_clk = clk_get_parent(tclk); + + if (p_clk != vmode_parent_clk) { + clk_set_parent(tclk, vmode_parent_clk); + + clk_set_rate(clk_get(NULL, "axi_a_clk"), 133000000); + clk_set_rate(clk_get(NULL, "axi_b_clk"), 66500000); + clk_set_rate(clk_get(NULL, "axi_c_clk"), 166000000); + clk_set_rate(clk_get(NULL, "emi_core_clk"), 133000000); + clk_set_rate(clk_get(NULL, "nfc_clk"), 26600000); + clk_set_rate(clk_get(NULL, "ahb_clk"), 133000000); + } + + /* move VPU clock to source from the emi_core_clk */ + tclk = clk_get(NULL, "vpu_clk"); + vmode_parent_clk = clk_get(NULL, "emi_core_clk"); + if (clk_get_parent(tclk) != vmode_parent_clk) + clk_set_parent(tclk, vmode_parent_clk); + + tclk = clk_get(NULL, "vpu_core_clk"); + if (clk_get_parent(tclk) != vmode_parent_clk) + clk_set_parent(tclk, vmode_parent_clk); + + tclk = clk_get(NULL, "arm_axi_clk"); + if (clk_get_parent(tclk) != vmode_parent_clk) + clk_set_parent(tclk, vmode_parent_clk); + + tclk = clk_get(NULL, "ddr_clk"); + vmode_parent_clk = clk_get(NULL, "axi_c_clk"); + if (clk_get_parent(tclk) != vmode_parent_clk) + clk_set_parent(tclk, vmode_parent_clk); + + /* disable PLL3 */ + tclk = clk_get(NULL, "pll3"); + if (tclk->usecount == 1) + clk_disable(tclk); + + tclk = clk_get(NULL, "cpu_clk"); + org_cpu_rate = clk_get_rate(tclk); + + ret = clk_set_rate(tclk, ARM_LP_CLK); + if (ret != 0) + printk(KERN_DEBUG "cannot set CPU clock rate\n"); + + /* Set the voltage to 0.8v for the GP domain. */ + + if (!board_is_mx37(BOARD_REV_2)) + gp_core = regulator_get(NULL, "DCDC1"); + else + gp_core = regulator_get(NULL, "SW1"); + + ret = regulator_set_voltage(gp_core, GP_LPM_VOLTAGE); + if (ret < 0) + printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!\n"); + + lp_video_mode = 1; +} + +void exit_lp_video_mode(void) +{ + int ret = 0; + static struct clk *tclk; + struct regulator *gp_core; + + /*Set the voltage to 0.8v for the GP domain. */ + if (!board_is_mx37(BOARD_REV_2)) + gp_core = regulator_get(NULL, "DCDC1"); + else + gp_core = regulator_get(NULL, "SW1"); + + ret = regulator_set_voltage(gp_core, GP_NORMAL_VOLTAGE); + if (ret < 0) + printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!\n"); + + tclk = clk_get(NULL, "cpu_clk"); + + ret = clk_set_rate(tclk, org_cpu_rate); + if (ret != 0) + printk(KERN_DEBUG "cannot set CPU clock rate\n"); + + lp_video_mode = 0; +} + +void enter_lp_audio_mode(void) +{ + int ret = 0; + + struct clk *p_clk; + struct clk *tclk; + struct clk *amode_parent_clk; + struct regulator *gp_core; + struct regulator *lp_core; + + tclk = clk_get(NULL, "ipu_clk"); + if (clk_get_usecount(tclk) != 0) { + printk(KERN_INFO + "Cannot enter AUDIO LPM mode - display is still active\n"); + return; + } + + tclk = clk_get(NULL, "periph_apm_clk"); + amode_parent_clk = clk_get(NULL, "lp_apm"); + p_clk = clk_get_parent(tclk); + + /* Make sure osc_clk is the parent of lp_apm. */ + clk_set_parent(amode_parent_clk, clk_get(NULL, "osc")); + + /* Set the parent of periph_apm_clk to be lp_apm */ + clk_set_parent(tclk, amode_parent_clk); + amode_parent_clk = tclk; + + tclk = clk_get(NULL, "main_bus_clk"); + p_clk = clk_get_parent(tclk); + /* Set the parent of main_bus_clk to be periph_apm_clk */ + clk_set_parent(tclk, amode_parent_clk); + + clk_set_rate(clk_get(NULL, "axi_a_clk"), 24000000); + clk_set_rate(clk_get(NULL, "axi_b_clk"), 24000000); + clk_set_rate(clk_get(NULL, "axi_c_clk"), 24000000); + clk_set_rate(clk_get(NULL, "emi_core_clk"), 24000000); + clk_set_rate(clk_get(NULL, "nfc_clk"), 4800000); + clk_set_rate(clk_get(NULL, "ahb_clk"), 24000000); + + amode_parent_clk = clk_get(NULL, "emi_core_clk"); + + tclk = clk_get(NULL, "arm_axi_clk"); + p_clk = clk_get_parent(tclk); + if (p_clk != amode_parent_clk) { + clk_set_parent(tclk, amode_parent_clk); + } + + tclk = clk_get(NULL, "vpu_clk"); + p_clk = clk_get_parent(tclk); + if (p_clk != amode_parent_clk) { + clk_set_parent(tclk, amode_parent_clk); + } + + tclk = clk_get(NULL, "vpu_core_clk"); + p_clk = clk_get_parent(tclk); + if (p_clk != amode_parent_clk) { + clk_set_parent(tclk, amode_parent_clk); + } + + /* disable PLL3 */ + tclk = clk_get(NULL, "pll3"); + if (tclk->usecount == 1) + clk_disable(tclk); + + /* disable PLL2 */ + tclk = clk_get(NULL, "pll2"); + if (tclk->usecount == 1) + clk_disable(tclk); + + /* Set the voltage to 1.0v for the LP domain. */ + if (!board_is_mx37(BOARD_REV_2)) + lp_core = regulator_get(NULL, "DCDC4"); + else + lp_core = regulator_get(NULL, "SW2"); + + if (lp_core != NULL) { + ret = regulator_set_voltage(lp_core, LP_LPM_VOLTAGE); + if (ret < 0) + printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!!!\n"); + } + + tclk = clk_get(NULL, "cpu_clk"); + org_cpu_rate = clk_get_rate(tclk); + + ret = clk_set_rate(tclk, ARM_LP_CLK); + if (ret != 0) + printk(KERN_DEBUG "cannot set CPU clock rate\n"); + + /* Set the voltage to 0.8v for the GP domain. */ + if (!board_is_mx37(BOARD_REV_2)) + gp_core = regulator_get(NULL, "DCDC1"); + else + gp_core = regulator_get(NULL, "SW1"); + + if (gp_core != NULL) { + ret = regulator_set_voltage(gp_core, GP_LPM_VOLTAGE); + if (ret < 0) + printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!!\n"); + } + lp_audio_mode = 1; +} + +void exit_lp_audio_mode(void) +{ + struct regulator *gp_core; + struct regulator *lp_core; + struct clk *tclk; + struct clk *p_clk; + struct clk *rmode_parent_clk; + int ret; + + lp_audio_mode = 0; + /* Set the voltage to 1.2v for the LP domain. */ + if (!board_is_mx37(BOARD_REV_2)) + lp_core = regulator_get(NULL, "DCDC4"); + else + lp_core = regulator_get(NULL, "SW2"); + + if (lp_core != NULL) { + ret = regulator_set_voltage(lp_core, LP_NORMAL_VOLTAGE); + if (ret < 0) + printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!!!\n"); + } + + /* Set the voltage to 1.0v for the GP domain. */ + if (!board_is_mx37(BOARD_REV_2)) + gp_core = regulator_get(NULL, "DCDC1"); + else + gp_core = regulator_get(NULL, "SW1"); + + ret = regulator_set_voltage(gp_core, GP_NORMAL_VOLTAGE); + if (ret < 0) + printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!\n"); + + tclk = clk_get(NULL, "cpu_clk"); + + ret = clk_set_rate(tclk, org_cpu_rate); + if (ret != 0) + printk(KERN_DEBUG "cannot set CPU clock rate\n"); + + rmode_parent_clk = clk_get(NULL, "pll2"); + clk_enable(rmode_parent_clk); + + tclk = clk_get(NULL, "main_bus_clk"); + p_clk = clk_get_parent(tclk); + + /* Set the dividers before setting the parent clock. */ + clk_set_rate(clk_get(NULL, "axi_a_clk"), 4800000); + clk_set_rate(clk_get(NULL, "axi_b_clk"), 4000000); + clk_set_rate(clk_get(NULL, "axi_c_clk"), 6000000); + clk_set_rate(clk_get(NULL, "emi_core_clk"), 4800000); + clk_set_rate(clk_get(NULL, "ahb_clk"), 4800000); + + /* Set the parent of main_bus_clk to be pll2 */ + clk_set_parent(tclk, rmode_parent_clk); + udelay(5); +} + +static ssize_t lp_curr_mode(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (lp_video_mode) + return sprintf(buf, "in lp_video_mode\n"); + else if (lp_audio_mode) + return sprintf(buf, "in lp_audio_mode\n"); + else + return sprintf(buf, "in normal mode\n"); +} + +static ssize_t set_lp_mode(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + printk(KERN_DEBUG "In set_lp_mode() \n"); + + if (strstr(buf, "enable_lp_video") != NULL) { + if (!lp_video_mode) + enter_lp_video_mode(); + } else if (strstr(buf, "disable_lp_video") != NULL) { + if (lp_video_mode) + exit_lp_video_mode(); + } else if (strstr(buf, "enable_lp_audio") != NULL) { + if (!lp_audio_mode) + enter_lp_audio_mode(); + } else if (strstr(buf, "disable_lp_audio") != NULL) { + if (lp_audio_mode) + exit_lp_audio_mode(); + } + return size; +} + +static DEVICE_ATTR(lp_modes, 0644, lp_curr_mode, set_lp_mode); + +/*! + * This is the probe routine for the lp_mode driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + * + */ +static int __devinit mx37_lpmode_probe(struct platform_device *pdev) +{ + u32 res = 0; + lpmode_dev = &pdev->dev; + + res = sysfs_create_file(&lpmode_dev->kobj, &dev_attr_lp_modes.attr); + if (res) { + printk(KERN_ERR + "lpmode_dev: Unable to register sysdev entry for lpmode_dev"); + return res; + } + + if (res != 0) { + printk(KERN_ERR "lpmode_dev: Unable to start"); + return res; + } + lp_video_mode = 0; + lp_audio_mode = 0; + + return 0; +} + +static struct platform_driver mx37_lpmode_driver = { + .driver = { + .name = "mx37_lpmode", + }, + .probe = mx37_lpmode_probe, +}; + +/*! + * Initialise the mx37_lpmode_driver. + * + * @return The function always returns 0. + */ + +static int __init lpmode_init(void) +{ + if (platform_driver_register(&mx37_lpmode_driver) != 0) { + printk(KERN_ERR "mx37_lpmode_driver register failed\n"); + return -ENODEV; + } + + printk(KERN_INFO "LPMode driver module loaded\n"); + return 0; +} + +static void __exit lpmode_cleanup(void) +{ + sysfs_remove_file(&lpmode_dev->kobj, &dev_attr_lp_modes.attr); + + /* Unregister the device structure */ + platform_driver_unregister(&mx37_lpmode_driver); +} + +module_init(lpmode_init); +module_exit(lpmode_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("LPMode driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/mach-mx37/mm.c linux-2.6.26-lab126/arch/arm/mach-mx37/mm.c --- linux-2.6.26/arch/arm/mach-mx37/mm.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/mm.c 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,82 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include + +/*! + * @file mach-mx37/mm.c + * + * @brief This file creates static mapping between physical to virtual memory. + * + * @ingroup Memory_MX37 + */ + +/*! + * This structure defines the MX37 memory map. + */ +static struct map_desc mxc_io_desc[] __initdata = { + { + .virtual = IRAM_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(IRAM_BASE_ADDR), + .length = IRAM_SIZE, + .type = MT_NONSHARED_DEVICE}, + { + .virtual = PLATFORM_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(PLATFORM_BASE_ADDR), + .length = PLATFORM_SIZE, + .type = MT_DEVICE}, + { + .virtual = DEBUG_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(DEBUG_BASE_ADDR), + .length = DEBUG_SIZE, + .type = MT_NONSHARED_DEVICE}, + { + .virtual = TZIC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(TZIC_BASE_ADDR), + .length = TZIC_SIZE, + .type = MT_NONSHARED_DEVICE}, + { + .virtual = AIPS1_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), + .length = AIPS1_SIZE, + .type = MT_NONSHARED_DEVICE}, + { + .virtual = SPBA0_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), + .length = SPBA0_SIZE, + .type = MT_NONSHARED_DEVICE}, + { + .virtual = AIPS2_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), + .length = AIPS2_SIZE, + .type = MT_NONSHARED_DEVICE}, + { + .virtual = NFC_BASE_ADDR_AXI_VIRT, + .pfn = __phys_to_pfn(NFC_BASE_ADDR_AXI), + .length = NFC_AXI_SIZE, + .type = MT_DEVICE}, +}; + +/*! + * This function initializes the memory map. It is called during the + * system startup to create static physical to virtual memory map for + * the IO modules. + */ +void __init mxc_map_io(void) +{ + iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); +} diff -urN linux-2.6.26/arch/arm/mach-mx37/mx37_3stack.c linux-2.6.26-lab126/arch/arm/mach-mx37/mx37_3stack.c --- linux-2.6.26/arch/arm/mach-mx37/mx37_3stack.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/mx37_3stack.c 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,962 @@ +/* + * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE) +#include +#include +#include + +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board-mx37_3stack.h" +#include "iomux.h" +#include "crm_regs.h" + +/*! + * @file mach-mx37/mx37_3stack.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX37 + */ +extern void gpio_lcd_active(); +extern void mxc_map_io(void); +extern void mxc_init_irq(void); +extern void mxc_cpu_init(void) __init; +extern struct sys_timer mxc_timer; +extern void mxc_cpu_common_init(void); +extern int mxc_clocks_init(void); +extern void __init early_console_setup(char *); +extern int mxc_init_devices(void); + +/* working point(wp): 0 - 532MHz; 1 - 200MHz; */ +static struct cpu_wp cpu_wp_auto[] = { + { + .pll_rate = 532000000, + .cpu_rate = 532000000, + .pdf = 0, + .mfi = 5, + .mfd = 23, + .mfn = 13, + .cpu_voltage = 1000000,}, + { + .pll_rate = 400000000, + .cpu_rate = 400000000, + .pdf = 1, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_voltage = 900000,}, + { + .pll_rate = 200000000, + .cpu_rate = 200000000, + .pdf = 3, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_voltage = 850000,}, + { + .pll_rate = 600000000, + .cpu_rate = 600000000, + .pdf = 0, + .mfi = 6, + .mfd = 3, + .mfn = 1, + .cpu_voltage = 1200000,}, +}; + +struct cpu_wp *get_cpu_wp(int *wp) +{ + *wp = 3; + return cpu_wp_auto; +} + +static int mc13892_reg_int(void) +{ + int i = 0; + unsigned int value; + struct regulator *regulator; + struct cpu_wp *cpu_wp_tbl1; + int cpu_wp_nr1; + char *reg_name[] = { + "SW1", + "SW2", + "SW3", + "SW4", + "SW1_STBY", + "SW2_STBY", + "SW3_STBY", + "SW4_STBY", + "SW1_DVS", + "SW2_DVS", + "SWBST", + "VIOHI", + "VPLL", + "VDIG", + "VSD", + "VUSB2", + "VVIDEO", + "VAUDIO", + "VCAM", + "VGEN1", + "VGEN2", + "VGEN3", + "USB", + "GPO1", + "GPO2", + "GPO3", + "GPO4", + }; + + /* for board v1.1 do nothing*/ + if (!board_is_mx37(BOARD_REV_2)) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(reg_name); i++) { + regulator = regulator_get(NULL, reg_name[i]); + if (regulator != ERR_PTR(-ENOENT)) { + regulator_enable(regulator); + regulator_put(regulator, NULL); + } + } + for (i = 0; i < ARRAY_SIZE(reg_name); i++) { + if ((strcmp(reg_name[i], "VIOHI") == 0) || + (strcmp(reg_name[i], "VPLL") == 0) || + (strcmp(reg_name[i], "VDIG") == 0) || + (strcmp(reg_name[i], "VGEN2") == 0)) + continue; + regulator = regulator_get(NULL, reg_name[i]); + if (regulator != ERR_PTR(-ENOENT)) { + regulator_disable(regulator); + regulator_put(regulator, NULL); + } + } + + /* Set the current working point. */ + cpu_wp_tbl1 = get_cpu_wp(&cpu_wp_nr1); + for (i = 0; i < cpu_wp_nr1; i++) + cpu_wp_tbl1[i].cpu_voltage += 50000; + + /* Bit 4 DRM: keep VSRTC and CLK32KMCU on for all states */ + pmic_read_reg(REG_POWER_CTL0, &value, 0xffffff); + value |= 0x000010; + pmic_write_reg(REG_POWER_CTL0, value, 0xffffff); + + return 0; +} + +late_initcall(mc13892_reg_int); + +static void mxc_nop_release(struct device *dev) +{ + /* Nothing */ +} + +/* Get reference input clocks */ +void board_ref_clk_rate(unsigned long *ckil, unsigned long *osc, + unsigned long *ckih) +{ + *ckil = 32768; + *osc = 24000000; + *ckih = 22579200; +} + +/* MTD NAND flash */ +#if defined(CONFIG_MTD_NAND_MXC) || defined(CONFIG_MTD_NAND_MXC_MODULE) \ + || defined(CONFIG_MTD_NAND_MXC_V2) || defined(CONFIG_MTD_NAND_MXC_V2_MODULE) \ + || defined(CONFIG_MTD_NAND_MXC_V3) + +static struct mtd_partition mxc_nand_partitions[] = { + { + .name = "nand.bootloader", + .offset = 0, + .size = 2 * 1024 * 1024}, + { + .name = "nand.kernel", + .offset = MTDPART_OFS_APPEND, + .size = 4 * 1024 * 1024}, + { + .name = "nand.rootfs", + .offset = MTDPART_OFS_APPEND, + .size = 128 * 1024 * 1024}, + { + .name = "nand.userfs1", + .offset = MTDPART_OFS_APPEND, + .size = 256 * 1024 * 1024}, + { + .name = "nand.userfs2", + .offset = MTDPART_OFS_APPEND, + .size = 512 * 1024 * 1024}, + { + .name = "nand.userfs3", + .offset = MTDPART_OFS_APPEND, + .size = 1024 * 1024 * 1024}, +}; + +static struct flash_platform_data mxc_nand_data = { + .parts = mxc_nand_partitions, + .nr_parts = ARRAY_SIZE(mxc_nand_partitions), + .width = 1, +}; + +static struct platform_device mxc_nandv2_mtd_device = { + .name = "mxc_nandv2_flash", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_nand_data, + }, +}; + +static void mxc_init_nand_mtd(void) +{ +// if (__raw_readl(MXC_CCM_RCSR) & MXC_CCM_RCSR_NF16B) { +// mxc_nand_data.width = 2; +// } + (void)platform_device_register(&mxc_nandv2_mtd_device); +} +#else +static inline void mxc_init_nand_mtd(void) +{ +} +#endif + +static void lcd_reset(void) +{ + static int first; + + /* ensure that LCDIO(1.8V) has been turn on */ + /* active reset line GPIO */ + if (!first) { + mxc_request_iomux(MX37_PIN_GPIO1_5, IOMUX_CONFIG_GPIO); + first = 1; + } + mxc_set_gpio_dataout(MX37_PIN_GPIO1_5, 0); + mxc_set_gpio_direction(MX37_PIN_GPIO1_5, 0); + /* do reset */ + msleep(10); /* tRES >= 100us */ + mxc_set_gpio_dataout(MX37_PIN_GPIO1_5, 1); + msleep(60); +} + +static struct mxc_lcd_platform_data lcd_data = { + .core_reg = "VVIDEO", + .io_reg = "SW4", + .reset = lcd_reset, +}; + +#if defined(CONFIG_KEYBOARD_MPR084) || defined(CONFIG_KEYBOARD_MPR084_MODULE) +/*! + * These functions are used to configure and the GPIO pins for keypad to + * activate and deactivate it. + */ +extern void gpio_keypad_active(void); + +extern void gpio_keypad_inactive(void); + +static u16 keymap[] = { + KEY_DOWN, KEY_LEFT, KEY_ENTER, + KEY_RIGHT, KEY_UP, KEY_LEFTALT, + KEY_TAB, KEY_ESC, +}; + +static struct mxc_keyp_platform_data keypad_data = { + .matrix = keymap, + .active = gpio_keypad_active, + .inactive = gpio_keypad_inactive, + .vdd_reg = "VGEN2", +}; +#else + +static struct mxc_keyp_platform_data keypad_data = {}; + +#endif + +static struct mxc_lightsensor_platform_data ls_data = { + .vdd_reg = "VGEN2", + .rext = 100, +}; +static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { + { + .type = "tsc2007", + .addr = 0x48, + .irq = IOMUX_TO_IRQ(MX37_PIN_AUD5_RXFS), + }, + { + .type = "mpr084", + .addr = 0x5D, + .platform_data = &keypad_data, + .irq = IOMUX_TO_IRQ(MX37_PIN_GPIO1_3), + }, + { + .type = "isl29003", + .addr = 0x44, + .platform_data = &ls_data, + }, +}; + +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { + { + .type = "mc13892", + .addr = 0x08, + .platform_data = (void *)MX37_PIN_OWIRE_LINE, + }, + { + .type = "sgtl5000-i2c", + .addr = 0x0a, + }, +}; + +static struct spi_board_info mxc_spi_board_info[] __initdata = { + { + .modalias = "cpld_spi", + .max_speed_hz = 27000000, + .bus_num = 2, + .chip_select = 0, + }, + { + .modalias = "lcd_spi", + .max_speed_hz = 5000000, + .bus_num = 2, + .platform_data = &lcd_data, + .chip_select = 1,}, +}; + +#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) +static struct platform_device mxc_fb_device[] = { + { + .name = "mxc_sdc_fb", + .id = 0, + .dev = { + .release = mxc_nop_release, + .coherent_dma_mask = 0xFFFFFFFF, + }, + }, + { + .name = "mxc_sdc_fb", + .id = 1, + .dev = { + .release = mxc_nop_release, + .coherent_dma_mask = 0xFFFFFFFF, + }, + }, + { + .name = "mxc_sdc_fb", + .id = 2, + .dev = { + .release = mxc_nop_release, + .coherent_dma_mask = 0xFFFFFFFF, + }, + }, +}; + +static void mxc_init_fb(void) +{ + (void)platform_device_register(&mxc_fb_device[0]); + (void)platform_device_register(&mxc_fb_device[1]); + (void)platform_device_register(&mxc_fb_device[2]); + gpio_lcd_active(); +} +#else +static inline void mxc_init_fb(void) +{ +} +#endif + +static struct platform_device mxcbl_device = { + .name = "mxc_mc13892_bl", +}; + +static inline void mxc_init_bl(void) +{ + platform_device_register(&mxcbl_device); +} + +#if defined(CONFIG_TOUCHSCREEN_TSC2007) || defined(CONFIG_TOUCHSCREEN_TSC2007_MODULE) + +static int __init mxc_init_touchscreen(void) +{ + int pad_val; + + mxc_request_iomux(MX37_PIN_AUD5_RXFS, IOMUX_CONFIG_GPIO); + pad_val = PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU; + mxc_iomux_set_pad(MX37_PIN_AUD5_RXFS, pad_val); + mxc_set_gpio_direction(MX37_PIN_AUD5_RXFS, 1); + + return 0; +} +#else +static int __init mxc_init_touchscreen(void) +{ + return 0; +} +#endif + +/*lan9217 device*/ +#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) +static struct resource smsc911x_resources[] = { + { + .start = LAN9217_BASE_ADDR, + .end = LAN9217_BASE_ADDR + 255, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_EXP_IO_BASE, + .flags = IORESOURCE_IRQ, + }, +}; +static struct platform_device smsc_lan9217_device = { + .name = "smsc911x", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, +}; + +static int __init mxc_init_enet(void) +{ + (void)platform_device_register(&smsc_lan9217_device); + return 0; +} +#else +static int __init mxc_init_enet(void) +{ + return 0; +} +#endif + +late_initcall(mxc_init_enet); + +#if defined(CONFIG_PATA_FSL) || defined(CONFIG_PATA_FSL_MODULE) +extern void gpio_ata_active(void); +extern void gpio_ata_inactive(void); + +static int ata_init(struct platform_device *pdev) +{ + /* Configure the pins */ + gpio_ata_active(); + + return 0; +} + +static void ata_exit(void) +{ + /* Free the pins */ + gpio_ata_inactive(); +} + +static struct fsl_ata_platform_data ata_data = { + .udma_mask = ATA_UDMA3, /* board can handle up to UDMA3 */ + .mwdma_mask = ATA_MWDMA2, + .pio_mask = ATA_PIO4, + .fifo_alarm = MXC_IDE_DMA_WATERMARK / 2, + .max_sg = MXC_IDE_DMA_BD_NR, + .init = ata_init, + .exit = ata_exit, + .core_reg = NULL, /*"LDO2", */ + .io_reg = NULL, /*"LDO3", */ +}; + +static struct resource pata_fsl_resources[] = { + [0] = { /* I/O */ + .start = ATA_BASE_ADDR, + .end = ATA_BASE_ADDR + 0x000000C8, + .flags = IORESOURCE_MEM, + }, + [2] = { /* IRQ */ + .start = MXC_INT_ATA, + .end = MXC_INT_ATA, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pata_fsl_device = { + .name = "pata_fsl", + .id = -1, + .num_resources = ARRAY_SIZE(pata_fsl_resources), + .resource = pata_fsl_resources, + .dev = { + .platform_data = &ata_data, + .coherent_dma_mask = ~0, + }, +}; + +static void __init mxc_init_pata(void) +{ + (void)platform_device_register(&pata_fsl_device); +} +#else /* CONFIG_PATA_FSL */ +static void __init mxc_init_pata(void) +{ +} +#endif /* CONFIG_PATA_FSL */ + +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mxc_cpu_init(); + +#ifdef CONFIG_DISCONTIGMEM + do { + int nid; + mi->nr_banks = MXC_NUMNODES; + for (nid = 0; nid < mi->nr_banks; nid++) { + SET_NODE(mi, nid); + } + } while (0); +#endif +} + +#if defined(CONFIG_SDIO_UNIFI_FS) || defined(CONFIG_SDIO_UNIFI_FS_MODULE) +static void mxc_unifi_hardreset(void) +{ + struct regulator *gpo4; + + if (board_is_mx37(BOARD_REV_2)) { + gpo4 = regulator_get(NULL, "GPO4"); + if (!IS_ERR(gpo4)) + regulator_enable(gpo4); + regulator_put(gpo4, NULL); + } else { + mxc_request_iomux(MX37_PIN_AUD5_RXC, IOMUX_CONFIG_GPIO); + mxc_set_gpio_dataout(MX37_PIN_AUD5_RXC, 1); + mxc_set_gpio_direction(MX37_PIN_AUD5_RXC, 0); + mxc_free_iomux(MX37_PIN_AUD5_RXC, IOMUX_CONFIG_GPIO); + } +} + +static struct mxc_unifi_platform_data unifi_data = { + .hardreset = mxc_unifi_hardreset, + .enable = NULL, + .reg_1v5_ana_bb = "VGEN1", + .reg_vdd_vpa = "VCAM", + .reg_1v5_dd = "VGEN1", + .host_id = 1, +}; + +struct mxc_unifi_platform_data *get_unifi_plat_data(void) +{ + return &unifi_data; +} +#else +struct mxc_unifi_platform_data *get_unifi_plat_data(void) +{ + return NULL; +} +#endif + +EXPORT_SYMBOL(get_unifi_plat_data); + +#if defined(CONFIG_MMC_IMX_ESDHCI) || defined(CONFIG_MMC_IMX_ESDHCI_MODULE) +static struct mxc_mmc_platform_data mmc_data = { + .ocr_mask = MMC_VDD_32_33, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 150000, + .max_clk = 52000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", +}; + +/*! + * Resource definition for the SDHC1 + */ +static struct resource mxcsdhc1_resources[] = { + [0] = { + .start = MMC_SDHC1_BASE_ADDR, + .end = MMC_SDHC1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_MMC_SDHC1, + .end = MXC_INT_MMC_SDHC1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Device Definition for MXC SDHC1 */ +static struct platform_device mxcsdhc1_device = { + .name = "mxsdhci", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc_data, + }, + .num_resources = ARRAY_SIZE(mxcsdhc1_resources), + .resource = mxcsdhc1_resources, +}; + +#if defined(CONFIG_SDIO_UNIFI_FS) || defined(CONFIG_SDIO_UNIFI_FS_MODULE) +static struct mxc_mmc_platform_data mmc1_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | + MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 150000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", +}; + +static struct resource mxcsdhc2_resources[] = { + [0] = { + .start = MMC_SDHC2_BASE_ADDR, + .end = MMC_SDHC2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_MMC_SDHC2, + .end = MXC_INT_MMC_SDHC2, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxcsdhc2_device = { + .name = "mxsdhci", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc1_data, + }, + .num_resources = ARRAY_SIZE(mxcsdhc2_resources), + .resource = mxcsdhc2_resources, +}; +#endif + +static inline void mxc_init_mmc(void) +{ + int cd_irq; + + cd_irq = sdhc_init_card_det(0); + if (cd_irq) { + mxcsdhc1_device.resource[2].start = cd_irq; + mxcsdhc1_device.resource[2].end = cd_irq; + } + + spba_take_ownership(SPBA_SDHC1, SPBA_MASTER_A | SPBA_MASTER_C); + (void)platform_device_register(&mxcsdhc1_device); +#if defined(CONFIG_SDIO_UNIFI_FS) || defined(CONFIG_SDIO_UNIFI_FS_MODULE) + cd_irq = sdhc_init_card_det(1); + if (cd_irq) { + mxcsdhc2_device.resource[2].start = cd_irq; + mxcsdhc2_device.resource[2].end = cd_irq; + } + spba_take_ownership(SPBA_SDHC2, SPBA_MASTER_A | SPBA_MASTER_C); + (void)platform_device_register(&mxcsdhc2_device); +#endif +} +#else +static inline void mxc_init_mmc(void) +{ +} +#endif + +static void bt_reset(void) +{ + struct regulator *gpo4; + if (board_is_mx37(BOARD_REV_2)) { + gpo4 = regulator_get(NULL, "GPO4"); + if (!IS_ERR(gpo4)) + regulator_enable(gpo4); + regulator_put(gpo4, NULL); + } else { + mxc_request_iomux(MX37_PIN_AUD5_RXC, IOMUX_CONFIG_GPIO); + mxc_set_gpio_dataout(MX37_PIN_AUD5_RXC, 1); + mxc_set_gpio_direction(MX37_PIN_AUD5_RXC, 0); + } +} + +static struct mxc_bt_platform_data mxc_bt_data = { + .bt_vdd = "VGEN2", + .bt_vdd_parent = NULL, + .bt_vusb = "SW4", + .bt_vusb_parent = NULL, + .bt_reset = bt_reset, +}; + +static struct platform_device mxc_bt_device = { + .name = "mxc_bt", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_bt_data, + }, +}; + +static void mxc_init_bluetooth(void) +{ + (void)platform_device_register(&mxc_bt_device); +} + +#if defined(CONFIG_SND_SOC_IMX_3STACK_SGTL5000) \ + || defined(CONFIG_SND_SOC_IMX_3STACK_SGTL5000_MODULE) +static int mxc_sgtl5000_plat_init(void); +static int mxc_sgtl5000_plat_finit(void); +static int mxc_sgtl5000_amp_enable(int enable); + +static struct mxc_sgtl5000_platform_data sgtl5000_data = { + .ssi_num = 1, + .src_port = 2, + .ext_port = 5, + .hp_irq = IOMUX_TO_IRQ(MX37_PIN_AUD5_RXFS), + .hp_status = headphone_det_status, + .vddio_reg = "SW3", + .vdda_reg = "VAUDIO", + .amp_enable = mxc_sgtl5000_amp_enable, + .vddio = 1850000, + .vdda = 2775000, + .vddd = 0, + .init = mxc_sgtl5000_plat_init, + .finit = mxc_sgtl5000_plat_finit, +}; + +static struct platform_device sgtl5000_device = { + .name = "sgtl5000-imx", + .dev = { + .release = mxc_nop_release, + .platform_data = &sgtl5000_data, + }, +}; + +static int mxc_sgtl5000_plat_init(void) +{ + struct regulator *reg; + reg = regulator_get(&sgtl5000_device.dev, "GPO2"); + if (IS_ERR(reg)) + return -EINVAL; + sgtl5000_data.priv = reg; + return 0; +} + +static int mxc_sgtl5000_plat_finit(void) +{ + struct regulator *reg; + reg = sgtl5000_data.priv; + if (reg) { + regulator_put(reg, &sgtl5000_device.dev); + sgtl5000_data.priv = NULL; + } + return 0; +} + +static int mxc_sgtl5000_amp_enable(int enable) +{ + struct regulator *reg; + reg = sgtl5000_data.priv; + + if (!reg) + return -EINVAL; + if (enable) + regulator_enable(reg); + else + regulator_disable(reg); + return 0; +} + +static void mxc_sgtl5000_init(void) +{ + int err, pin; + struct clk *cko1, *parent; + unsigned long rate; + + /* for board v1.1 do nothing*/ + if (!board_is_mx37(BOARD_REV_2)) + return; + + pin = MX37_PIN_AUD5_RXFS; + err = mxc_request_iomux(pin, IOMUX_CONFIG_GPIO); + if (err) { + sgtl5000_data.hp_irq = -1; + printk(KERN_ERR "Error: sgtl5000_init request gpio failed!\n"); + return; + } + mxc_iomux_set_pad(pin, PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU); + mxc_set_gpio_direction(pin, 1); + + /* cko1 clock */ + mxc_request_iomux(MX37_PIN_GPIO1_6, IOMUX_CONFIG_ALT2); + + cko1 = clk_get(NULL, "cko1_clk"); + if (IS_ERR(cko1)) + return; + parent = clk_get(NULL, "ipg_perclk"); + if (IS_ERR(parent)) + return; + clk_set_parent(cko1, parent); + rate = clk_round_rate(cko1, 13000000); + if (rate < 8000000 || rate > 27000000) { + printk(KERN_ERR "Error: SGTL5000 mclk freq %d out of range!\n", + rate); + clk_put(parent); + clk_put(cko1); + return; + } + clk_set_rate(cko1, rate); + clk_enable(cko1); + sgtl5000_data.sysclk = rate; + platform_device_register(&sgtl5000_device); +} +#else +static inline void mxc_sgtl5000_init(void) +{ +} +#endif + +/*! + * fixup for mx37 3stack board v1.1(wm8350) + */ +static void mx37_3stack_fixup_for_board_v1(void) +{ + dptc_gp_data.reg_id = "DCDC1"; + dptc_lp_data.reg_id = "DCDC4"; + gp_reg_id = "DCDC1"; + lp_reg_id = "DCDC4"; + tve_data.dac_reg = "LDO2"; + tve_data.dig_reg = "LDO3"; + lcd_data.core_reg = "LDO1"; + lcd_data.io_reg = "DCDC6"; + dvfs_core_data.reg_id = "DCDC1"; + ls_data.vdd_reg = "DCDC3"; + mxc_bt_data.bt_vdd = "DCDC3"; + mxc_bt_data.bt_vusb = "DCDC6"; + mxc_init_touchscreen(); +#if defined(CONFIG_SDIO_UNIFI_FS) || defined(CONFIG_SDIO_UNIFI_FS_MODULE) + unifi_data.reg_1v5_ana_bb = NULL; /* VMAIN is used on v1 board */ + unifi_data.reg_vdd_vpa = NULL; + unifi_data.reg_1v5_dd = NULL; +#endif +#if defined(CONFIG_KEYBOARD_MPR084) || defined(CONFIG_KEYBOARD_MPR084_MODULE) + keypad_data.vdd_reg = "DCDC3"; +#endif +} + +#if defined(CONFIG_GPS_IOCTRL) || defined(CONFIG_GPS_IOCTRL_MODULE) +static struct mxc_gps_platform_data gps_data = { + .core_reg = "VIOHI", + .analog_reg = "SW3", +}; + +static struct platform_device mxc_gps_device = { + .name = "gps_ioctrl", + .id = 0, + .dev = { + .platform_data = &gps_data, + }, +}; + +static void __init mxc_init_gps(void) +{ + (void)platform_device_register(&mxc_gps_device); +} +#else +static void __init mxc_init_gps(void) +{ +} +#endif + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + mxc_cpu_common_init(); + mxc_clocks_init(); + mxc_gpio_init(); + early_console_setup(saved_command_line); + mxc_init_devices(); + if (!board_is_mx37(BOARD_REV_2)) + mx37_3stack_fixup_for_board_v1(); + i2c_register_board_info(0, mxc_i2c0_board_info, + ARRAY_SIZE(mxc_i2c0_board_info)); + i2c_register_board_info(1, mxc_i2c1_board_info, + ARRAY_SIZE(mxc_i2c1_board_info)); + + spi_register_board_info(mxc_spi_board_info, + ARRAY_SIZE(mxc_spi_board_info)); + mxc_init_nand_mtd(); + mxc_init_mmc(); + mxc_init_pata(); + mxc_init_fb(); + mxc_init_bl(); + mxc_init_bluetooth(); + mxc_init_gps(); + mxc_sgtl5000_init(); +} + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX37_3STACK data structure. + */ +/* *INDENT-OFF* */ +MACHINE_START(MX37_3DS, "Freescale MX37 3-Stack Board") + /* Maintainer: Freescale Semiconductor, Inc. */ + .phys_io = AIPS1_BASE_ADDR, + .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .fixup = fixup_mxc_board, + .map_io = mxc_map_io, + .init_irq = mxc_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff -urN linux-2.6.26/arch/arm/mach-mx37/mx37_3stack_cpld.c linux-2.6.26-lab126/arch/arm/mach-mx37/mx37_3stack_cpld.c --- linux-2.6.26/arch/arm/mach-mx37/mx37_3stack_cpld.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/mx37_3stack_cpld.c 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,231 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include "board-mx37_3stack.h" +#include "iomux.h" + +/*! + * @file mach-mx37/mx37_3stack_cpld.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX37 + */ + +extern int mxc_spi_poll_transfer(struct spi_device *spi, + struct spi_transfer *t); + +struct spi_device *cpld_spi; + +/*! + * This function is used to tranfer data to CPLD regs over CSPI + */ +static inline int mx37_3ds_cpld_rw(u8 * buf, size_t len) +{ + struct spi_transfer t = { + .tx_buf = (const void *)buf, + .rx_buf = buf, + .len = len, + .cs_change = 0, + .delay_usecs = 0, + }; + mxc_spi_poll_transfer(cpld_spi, &t); + return 0; +} + +/*! + * This function is called to read a CPLD register over CSPI. + * + * @param offset number of the cpld register to be read + * + * @return Returns 0 on success -1 on failure. + */ +unsigned int spi_cpld_read(unsigned int offset) +{ + unsigned int frame[2]; + unsigned int reg_num = offset >> 1; + unsigned int data = 0; + + frame[0] = (1 << 13) | ((reg_num & 0x0001FFFF) >> 5) | 0x00001000; + frame[1] = (((reg_num & 0x0000001F) << 27) | 0x0200001f); + mx37_3ds_cpld_rw((u8 *) frame, 2); + data = (frame[1] >> 6) & 0xFFFF; + + reg_num = (offset + 2) >> 1; + frame[0] = (1 << 13) | ((reg_num & 0x0001FFFF) >> 5) | 0x00001000; + frame[1] = (((reg_num & 0x0000001F) << 27) | 0x0200001f); + mx37_3ds_cpld_rw((u8 *) frame, 2); + + data |= (((frame[1] >> 6) & 0xFFFF) << 16); + return data; +} +EXPORT_SYMBOL(spi_cpld_read); + +/*! + * This function is called to write to a CPLD register over CSPI. + * + * @param offset number of the cpld register to be written + * @param reg_val value to be written + * + * @return Returns 0 on success -1 on failure. + */ +unsigned int spi_cpld_write(unsigned int offset, unsigned int reg_val) +{ + unsigned int frame[2] = { 0, 0 }; + unsigned int reg_num = offset >> 1; + unsigned int data = reg_val; + + frame[0] = ((reg_num & 0x0001FFFF) >> 5) | 0x00001000; + frame[1] = (((reg_num & 0x0000001F) << 27) | + ((data & 0x0000FFFF) << 6) | 0x03C00027); + mx37_3ds_cpld_rw((u8 *) frame, 2); + + reg_num = (offset + 2) >> 1; + data = reg_val >> 16; + frame[0] = 0; + frame[1] = 0; + frame[0] = ((reg_num & 0x0001FFFF) >> 5) | 0x00001000; + frame[1] = (((reg_num & 0x0000001F) << 27) | + ((data & 0x0000FFFF) << 6) | 0x03C00027); + + mx37_3ds_cpld_rw((u8 *) frame, 2); + + return 0; +} +EXPORT_SYMBOL(spi_cpld_write); + +static int __devinit mx37_3ds_cpld_probe(struct spi_device *spi) +{ + unsigned int i = 0; + + spi->bits_per_word = 46; + cpld_spi = spi; + + spi_setup(spi); + i = spi_cpld_read(CPLD_CODE_VER_REG); + pr_info("3-Stack Debug board detected, rev = 0x%04X\n", i); + spi_cpld_write(LED_SWITCH_REG, 0xFF); + + /* disable the interrupt and clear the status */ + spi_cpld_write(INTR_MASK_REG, 0); + spi_cpld_write(INTR_RESET_REG, 0xFFFF); + spi_cpld_write(INTR_RESET_REG, 0); + spi_cpld_write(INTR_MASK_REG, 0x1E); + return 0; +} + +/*! + * This structure contains pointers to the CPLD callback functions. + */ +static struct spi_driver mx37_3ds_cpld_driver = { + .driver = { + .name = "cpld_spi", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + .probe = mx37_3ds_cpld_probe, +}; + +static int __init mx37_3ds_cpld_init(void) +{ + pr_debug("Registering the CPLD Driver\n"); + return spi_register_driver(&mx37_3ds_cpld_driver); +} + +device_initcall(mx37_3ds_cpld_init); + +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) +{ + u32 expio_irq; + struct irq_desc *d; + + desc->chip->mask(irq); /* irq = gpio irq number */ + + expio_irq = MXC_EXP_IO_BASE; + + d = irq_desc + expio_irq; + if (unlikely(!(d->handle_irq))) { + printk(KERN_ERR "\nEXPIO irq: %d unhandled\n", expio_irq); + BUG(); /* oops */ + } + d->handle_irq(expio_irq, d); + + desc->chip->ack(irq); + desc->chip->unmask(irq); +} + +/* + * Disable an expio pin's interrupt by setting the bit in the imr. + * @param irq an expio virtual irq number + */ +static void expio_mask_irq(u32 irq) +{ +} + +/* + * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. + * @param irq an expanded io virtual irq number + */ +static void expio_ack_irq(u32 irq) +{ + /* clear the interrupt status */ + spi_cpld_write(INTR_RESET_REG, 1); + spi_cpld_write(INTR_RESET_REG, 0); +} + +/* + * Enable a expio pin's interrupt by clearing the bit in the imr. + * @param irq a expio virtual irq number + */ +static void expio_unmask_irq(u32 irq) +{ +} + +static struct irq_chip expio_irq_chip = { + .ack = expio_ack_irq, + .mask = expio_mask_irq, + .unmask = expio_unmask_irq, +}; + +static int __init mxc_expio_init(void) +{ + int i; + int pad_val; + + /* + * Configure INT line as GPIO input + */ + mxc_request_iomux(MX37_PIN_GPIO1_2, IOMUX_CONFIG_GPIO); + pad_val = mxc_iomux_get_pad(MX37_PIN_GPIO1_2); + pad_val |= PAD_CTL_PUE_PULL; + mxc_iomux_set_pad(MX37_PIN_GPIO1_2, pad_val); + mxc_set_gpio_direction(MX37_PIN_GPIO1_2, 1); + + for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); + i++) { + set_irq_chip(i, &expio_irq_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + set_irq_type(IOMUX_TO_IRQ(MX37_PIN_GPIO1_2), IRQT_LOW); + set_irq_chained_handler(IOMUX_TO_IRQ(MX37_PIN_GPIO1_2), + mxc_expio_irq_handler); + return 0; +} + +arch_initcall(mxc_expio_init); diff -urN linux-2.6.26/arch/arm/mach-mx37/mx37_3stack_gpio.c linux-2.6.26-lab126/arch/arm/mach-mx37/mx37_3stack_gpio.c --- linux-2.6.26/arch/arm/mach-mx37/mx37_3stack_gpio.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/mx37_3stack_gpio.c 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,1018 @@ +/* + * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "iomux.h" + +/*! + * @file mx37_3stack_gpio.c + * + * @brief This file contains all the GPIO setup functions for the board. + * + * @ingroup GPIO + */ + +void gpio_activate_audio_ports(void); + +/*! + * Setup GPIO for a UART port to be active + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_active(int port, int no_irda) +{ + /* + * Configure the IOMUX control registers for the UART signals + * and enable the UART transceivers + */ + switch (port) { + /* UART 1 IOMUX Configs */ + case 0: + mxc_request_iomux(MX37_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX37_PIN_UART1_RXD, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_input(MUX_IN_UART1_UART_RXD_MUX, INPUT_CTL_PATH4); + mxc_request_iomux(MX37_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX37_PIN_UART1_TXD, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX37_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX37_PIN_UART1_RTS, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH); + mxc_iomux_set_input(MUX_IN_UART1_UART_RTS_B, INPUT_CTL_PATH4); + mxc_request_iomux(MX37_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX37_PIN_UART1_CTS, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH); + break; + case 1: + mxc_request_iomux(MX37_PIN_UART1_DCD, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX37_PIN_UART1_DCD, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_input(MUX_IN_UART2_UART_RXD_MUX, INPUT_CTL_PATH1); + mxc_request_iomux(MX37_PIN_UART1_RI, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX37_PIN_UART1_RI, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX37_PIN_UART1_DSR, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX37_PIN_UART1_DSR, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH); + mxc_iomux_set_input(MUX_IN_UART2_UART_RTS_B, INPUT_CTL_PATH1); + mxc_request_iomux(MX37_PIN_UART1_DTR, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX37_PIN_UART1_DTR, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH); + break; + case 2: + mxc_request_iomux(MX37_PIN_AUD3_BB_TXD, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX37_PIN_AUD3_BB_TXD, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_input(MUX_IN_UART3_UART_RXD_MUX, INPUT_CTL_PATH0); + mxc_request_iomux(MX37_PIN_AUD3_BB_RXD, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX37_PIN_AUD3_BB_RXD, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX37_PIN_AUD3_BB_CK, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX37_PIN_AUD3_BB_CK, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH); + mxc_iomux_set_input(MUX_IN_UART3_UART_RTS_B, INPUT_CTL_PATH0); + mxc_request_iomux(MX37_PIN_AUD3_BB_FS, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX37_PIN_AUD3_BB_FS, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH); + break; + default: + break; + } +} + +/*! + * Setup GPIO for a UART port to be inactive + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_inactive(int port, int no_irda) +{ + /* + * Configure the IOMUX control registers for the UART signals + * and disable the UART transceivers + */ + switch (port) { + case 0: + mxc_request_iomux(MX37_PIN_UART1_RXD, IOMUX_CONFIG_GPIO); + mxc_request_iomux(MX37_PIN_UART1_TXD, IOMUX_CONFIG_GPIO); + mxc_request_iomux(MX37_PIN_UART1_RTS, IOMUX_CONFIG_GPIO); + mxc_request_iomux(MX37_PIN_UART1_CTS, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX37_PIN_UART1_RXD, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX37_PIN_UART1_TXD, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX37_PIN_UART1_RTS, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX37_PIN_UART1_CTS, IOMUX_CONFIG_GPIO); + break; + case 1: + mxc_request_iomux(MX37_PIN_UART1_DCD, IOMUX_CONFIG_GPIO); + mxc_request_iomux(MX37_PIN_UART1_RI, IOMUX_CONFIG_GPIO); + mxc_request_iomux(MX37_PIN_UART1_DSR, IOMUX_CONFIG_GPIO); + mxc_request_iomux(MX37_PIN_UART1_DTR, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX37_PIN_UART1_DCD, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX37_PIN_UART1_RI, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX37_PIN_UART1_DSR, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX37_PIN_UART1_DTR, IOMUX_CONFIG_GPIO); + break; + /* UART 3 IOMUX Configs */ + case 2: + mxc_request_iomux(MX37_PIN_AUD3_BB_TXD, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX37_PIN_AUD3_BB_TXD, IOMUX_CONFIG_GPIO); + mxc_request_iomux(MX37_PIN_AUD3_BB_RXD, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX37_PIN_AUD3_BB_RXD, IOMUX_CONFIG_GPIO); + mxc_request_iomux(MX37_PIN_AUD3_BB_CK, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX37_PIN_AUD3_BB_CK, IOMUX_CONFIG_GPIO); + mxc_request_iomux(MX37_PIN_AUD3_BB_FS, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX37_PIN_AUD3_BB_FS, IOMUX_CONFIG_GPIO); + break; + default: + break; + } +} + +/*! + * Configure the IOMUX GPR register to receive shared SDMA UART events + * + * @param port a UART port + */ +void config_uartdma_event(int port) +{ + +} + +EXPORT_SYMBOL(gpio_uart_active); +EXPORT_SYMBOL(gpio_uart_inactive); +EXPORT_SYMBOL(config_uartdma_event); + +/*! + * Setup GPIO for a CSPI device to be active + * + * @param cspi_mod an CSPI device + */ +void gpio_spi_active(int cspi_mod) +{ + switch (cspi_mod) { + case 0: + break; + case 1: + /* SPI2 */ + mxc_request_iomux(MX37_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX37_PIN_CSPI2_MISO, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX37_PIN_GRP_H9, PAD_CTL_HYS_ENABLE); + + mxc_request_iomux(MX37_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX37_PIN_CSPI2_MOSI, PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX37_PIN_UART1_CTS, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX37_PIN_UART1_CTS, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + + mxc_request_iomux(MX37_PIN_CSPI2_SCLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX37_PIN_CSPI2_SCLK, PAD_CTL_HYS_ENABLE | + PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX37_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX37_PIN_CSPI2_SS1, PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX37_PIN_CSPI2_SS0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX37_PIN_CSPI2_SS0, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX37_PIN_GRP_H10, PAD_CTL_HYS_ENABLE); + break; + case 2: + break; + default: + break; + } +} + +/*! + * Setup GPIO for a CSPI device to be inactive + * + * @param cspi_mod a CSPI device + */ +void gpio_spi_inactive(int cspi_mod) +{ +} + +/*! + * Setup 1-Wire to be active + */ +void gpio_owire_active(void) +{ + /*TODO*/} + +/*! + * Setup 1-Wire to be active + */ +void gpio_owire_inactive(void) +{ + /*TODO*/} + +EXPORT_SYMBOL(gpio_owire_active); +EXPORT_SYMBOL(gpio_owire_inactive); + +/*! + * Setup GPIO for an I2C device to be active + * + * @param i2c_num an I2C device + */ +void gpio_i2c_active(int i2c_num) +{ + iomux_pad_config_t regval = 0; + + switch (i2c_num) { + case 0: + /* Touch */ + /* select I2C1_SCK as daisy chain input */ + mxc_request_iomux(MX37_PIN_I2C1_CLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_input(MUX_IN_I2C1_SCL, INPUT_CTL_PATH1); + /* OpenDrain enabled, 100k PU enabled */ + regval = + PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_PKE_ENABLE; + mxc_iomux_set_pad(MX37_PIN_I2C1_CLK, regval); + + /*select I2C1_SDA as daisy chain input */ + mxc_request_iomux(MX37_PIN_I2C1_DAT, IOMUX_CONFIG_ALT0); + mxc_iomux_set_input(MUX_IN_I2C1_SDA, INPUT_CTL_PATH1); + mxc_iomux_set_pad(MX37_PIN_I2C1_DAT, regval); + mxc_iomux_set_pad(MX37_PIN_GRP_H3, PAD_CTL_HYS_ENABLE); + break; + case 1: + /* PMIC */ + /*select I2C2_SCL as daisy chain input */ + mxc_iomux_set_input(MUX_IN_I2C2_SCL, INPUT_CTL_PATH1); + regval = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | + PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_DRV_HIGH; + mxc_iomux_set_pad(MX37_PIN_GPIO1_0, regval); + mxc_request_iomux(MX37_PIN_GPIO1_0, + (IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT2)); + + /*select I2C2_SDA as daisy chain input */ + mxc_iomux_set_input(MUX_IN_I2C2_SDA, INPUT_CTL_PATH1); + mxc_iomux_set_pad(MX37_PIN_GPIO1_1, regval); + mxc_request_iomux(MX37_PIN_GPIO1_1, + (IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT2)); + break; + case 2: + break; + default: + break; + } +} + +/*! + * Setup GPIO for an I2C device to be inactive + * + * @param i2c_num an I2C device + */ +void gpio_i2c_inactive(int i2c_num) +{ + /*TODO*/} + +/*! + * This function activates DAM ports 4 & 5 to enable + * audio I/O. + */ +void gpio_activate_audio_ports(void) +{ + unsigned int pad_val; + + /* AUD4_TXD */ + mxc_request_iomux(MX37_PIN_DISP1_DAT20, IOMUX_CONFIG_ALT5); + /* AUD4_RXD */ + mxc_request_iomux(MX37_PIN_DISP1_DAT21, IOMUX_CONFIG_ALT5); + /* AUD4_TXC */ + mxc_request_iomux(MX37_PIN_DISP1_DAT22, IOMUX_CONFIG_ALT5); + /* AUD4_TXFS */ + mxc_request_iomux(MX37_PIN_DISP1_DAT23, IOMUX_CONFIG_ALT5); + + pad_val = PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST; + mxc_iomux_set_pad(MX37_PIN_AUD5_WB_CK, PAD_CTL_100K_PU | pad_val); + mxc_request_iomux(MX37_PIN_AUD5_WB_CK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX37_PIN_AUD5_WB_RXD, pad_val); + mxc_request_iomux(MX37_PIN_AUD5_WB_RXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX37_PIN_AUD5_WB_TXD, pad_val); + mxc_request_iomux(MX37_PIN_AUD5_WB_TXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX37_PIN_AUD5_WB_FS, PAD_CTL_100K_PU | pad_val); + mxc_request_iomux(MX37_PIN_AUD5_WB_FS, IOMUX_CONFIG_ALT0); + + /* Enable hysteresis for AUD5_WB_CK, AUD5_WB_RXD, AUD5_WB_TXD, AUD5_WB_FS */ + mxc_iomux_set_pad(MX37_PIN_GRP_H5, PAD_CTL_HYS_ENABLE); +} + +EXPORT_SYMBOL(gpio_activate_audio_ports); + +/*! + * Setup GPIO for SDHC to be active + * + * @param module SDHC module number + */ +void gpio_sdhc_active(int module) +{ + unsigned int pad_val; + + switch (module) { + case 0: + mxc_request_iomux(MX37_PIN_SD1_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX37_PIN_SD1_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX37_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX37_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX37_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX37_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + + mxc_iomux_set_pad(MX37_PIN_SD1_CMD, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX37_PIN_SD1_CLK, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX37_PIN_SD1_DATA0, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX37_PIN_SD1_DATA1, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX37_PIN_SD1_DATA2, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX37_PIN_SD1_DATA3, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + + /* Write Protected Pin */ + mxc_request_iomux(MX37_PIN_CSPI1_SS0, + IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX37_PIN_CSPI1_SS0, + PAD_CTL_DRV_HIGH | PAD_CTL_HYS_NONE | + PAD_CTL_SRE_FAST); + /* + * SW workaround for the eSDHC1 Write Protected feature + * The PSR of CSPI1_SS0 (GPIO3_2) should be read. + */ + mxc_set_gpio_direction(MX37_PIN_CSPI1_SS0, 0); + mxc_set_gpio_dataout(MX37_PIN_CSPI1_SS0, 1); + break; + case 1: + mxc_request_iomux(MX37_PIN_SD2_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX37_PIN_SD2_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX37_PIN_SD2_DATA0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX37_PIN_SD2_DATA1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX37_PIN_SD2_DATA2, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX37_PIN_SD2_DATA3, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + + mxc_iomux_set_pad(MX37_PIN_SD2_CMD, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX37_PIN_SD2_CLK, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX37_PIN_SD2_DATA0, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX37_PIN_SD2_DATA1, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX37_PIN_SD2_DATA2, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX37_PIN_SD2_DATA3, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_sdhc_active); + +/*! + * Setup GPIO for SDHC1 to be inactive + * + * @param module SDHC module number + */ +void gpio_sdhc_inactive(int module) +{ + switch (module) { + case 0: + mxc_free_iomux(MX37_PIN_SD1_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX37_PIN_SD1_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX37_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX37_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX37_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX37_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + + mxc_iomux_set_pad(MX37_PIN_SD1_CLK, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX37_PIN_SD1_CMD, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX37_PIN_SD1_DATA0, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX37_PIN_SD1_DATA1, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX37_PIN_SD1_DATA2, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX37_PIN_SD1_DATA3, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + + /* Free Write Protected Pin */ + mxc_free_iomux(MX37_PIN_CSPI1_SS0, + IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX37_PIN_CSPI1_SS0, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + break; + case 1: + mxc_free_iomux(MX37_PIN_SD2_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX37_PIN_SD2_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX37_PIN_SD2_DATA0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX37_PIN_SD2_DATA1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX37_PIN_SD2_DATA2, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX37_PIN_SD2_DATA3, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + + mxc_iomux_set_pad(MX37_PIN_SD2_CLK, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX37_PIN_SD2_CMD, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX37_PIN_SD2_DATA0, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX37_PIN_SD2_DATA1, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX37_PIN_SD2_DATA2, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX37_PIN_SD2_DATA3, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_sdhc_inactive); + +/* + * Probe for the card. If present the GPIO data would be set. + */ +int sdhc_get_card_det_status(struct device *dev) +{ + int ret; + + if (to_platform_device(dev)->id == 0) { + if (board_is_mx37(BOARD_REV_2)) + ret = mxc_get_gpio_datain(MX37_PIN_GPIO1_4); + else + ret = mxc_get_gpio_datain(MX37_PIN_OWIRE_LINE); + return ret; + } else { /* config the det pin for SDHC2 */ + return 0; + } +} + +EXPORT_SYMBOL(sdhc_get_card_det_status); + +/* + * Return the card detect pin. + */ +int sdhc_init_card_det(int id) +{ + if (id == 0) { + if (board_is_mx37(BOARD_REV_2)) { + mxc_request_iomux(MX37_PIN_GPIO1_4, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX37_PIN_GPIO1_4, + PAD_CTL_DRV_HIGH | + PAD_CTL_HYS_NONE | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_NONE | PAD_CTL_SRE_FAST); + mxc_set_gpio_direction(MX37_PIN_GPIO1_4, 1); + return IOMUX_TO_IRQ(MX37_PIN_GPIO1_4); + } else { + mxc_request_iomux(MX37_PIN_OWIRE_LINE, + IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX37_PIN_OWIRE_LINE, + PAD_CTL_DRV_HIGH | + PAD_CTL_HYS_NONE | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_NONE | PAD_CTL_SRE_FAST); + mxc_set_gpio_direction(MX37_PIN_OWIRE_LINE, 1); + return IOMUX_TO_IRQ(MX37_PIN_OWIRE_LINE); + } + } else { /* config the det pin for SDHC2 */ + return 0; + + } +} + +EXPORT_SYMBOL(sdhc_init_card_det); + +/*! + * Get CSPI1_SS0 pin value to detect write protection + */ +int sdhc_write_protect(struct device *dev) +{ + unsigned short rc = 0; + + rc = mxc_get_gpio_datain(MX37_PIN_CSPI1_SS0); + if (rc > 0) + return 1; + else + return 0; +} + +EXPORT_SYMBOL(sdhc_write_protect); + +/*! + * Setup GPIO for LCD to be active + * + */ +void gpio_lcd_active(void) +{ + mxc_request_iomux(MX37_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_PAD_DI1_PIN3, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_DISP_CLK, IOMUX_CONFIG_ALT0); +} + +/*! + * Setup GPIO for LCD to be inactive + * + */ +void gpio_lcd_inactive(void) +{ + /*TODO*/} + +/*! + * Setup pins for SLCD to be active + * + */ +void slcd_gpio_config(void) +{ + /*TODO*/} + +/*! + * Switch to the specified sensor - MX33 ADS has two + * + */ +void gpio_sensor_select(int sensor) +{ + /*TODO*/} + +/*! + * Setup GPIO for sensor to be active + * + */ +void gpio_sensor_active(void) +{ + /*TODO*/} + +EXPORT_SYMBOL(gpio_sensor_active); + +/*! + * Setup GPIO for sensor to be inactive + * + */ +void gpio_sensor_inactive(void) +{ + /*TODO*/} + +EXPORT_SYMBOL(gpio_sensor_inactive); + +/*! + * Setup GPIO for ATA interface + * + */ +void gpio_ata_active(void) +{ + /*IOMUX Settings */ + /*PATA_DMARQ_B */ + mxc_request_iomux(MX37_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1); + /*PATA_DIOR */ + mxc_request_iomux(MX37_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1); + /*PATA_DIOW */ + mxc_request_iomux(MX37_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1); + /*PATA_DMACK */ + mxc_request_iomux(MX37_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1); + /*PATA_RESET_B */ + mxc_request_iomux(MX37_PIN_NANDF_RB, IOMUX_CONFIG_ALT1); + /*PATA_IORDY */ + mxc_request_iomux(MX37_PIN_NANDF_CS0, IOMUX_CONFIG_ALT1); + /*PATA_INTRQ_B */ + mxc_request_iomux(MX37_PIN_NANDF_CS1, IOMUX_CONFIG_ALT1); + /*PATA_CS_0 */ + mxc_request_iomux(MX37_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1); + /*PATA_CS_1 */ + mxc_request_iomux(MX37_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1); + + /*PATA_D0 */ + mxc_request_iomux(MX37_PIN_EIM_D0, IOMUX_CONFIG_ALT1); + /*PATA_D1 */ + mxc_request_iomux(MX37_PIN_EIM_D1, IOMUX_CONFIG_ALT1); + /*PATA_D2 */ + mxc_request_iomux(MX37_PIN_EIM_D2, IOMUX_CONFIG_ALT1); + /*PATA_D3 */ + mxc_request_iomux(MX37_PIN_EIM_D3, IOMUX_CONFIG_ALT1); + /*PATA_D4 */ + mxc_request_iomux(MX37_PIN_EIM_D4, IOMUX_CONFIG_ALT1); + /*PATA_D5 */ + mxc_request_iomux(MX37_PIN_EIM_D5, IOMUX_CONFIG_ALT1); + /*PATA_D6 */ + mxc_request_iomux(MX37_PIN_EIM_D6, IOMUX_CONFIG_ALT1); + /*PATA_D7 */ + mxc_request_iomux(MX37_PIN_EIM_D7, IOMUX_CONFIG_ALT1); + /*PATA_D8 */ + mxc_request_iomux(MX37_PIN_EIM_D8, IOMUX_CONFIG_ALT1); + /*PATA_D9 */ + mxc_request_iomux(MX37_PIN_EIM_D9, IOMUX_CONFIG_ALT1); + /*PATA_D10 */ + mxc_request_iomux(MX37_PIN_EIM_D10, IOMUX_CONFIG_ALT1); + /*PATA_D11 */ + mxc_request_iomux(MX37_PIN_EIM_D11, IOMUX_CONFIG_ALT1); + /*PATA_D12 */ + mxc_request_iomux(MX37_PIN_EIM_D12, IOMUX_CONFIG_ALT1); + /*PATA_D13 */ + mxc_request_iomux(MX37_PIN_EIM_D13, IOMUX_CONFIG_ALT1); + /*PATA_D14 */ + mxc_request_iomux(MX37_PIN_EIM_D14, IOMUX_CONFIG_ALT1); + /*PATA_D15 */ + mxc_request_iomux(MX37_PIN_EIM_D15, IOMUX_CONFIG_ALT1); + /*PATA_DA0 */ + mxc_request_iomux(MX37_PIN_SD2_DATA3, IOMUX_CONFIG_ALT1); + /*PATA_DA1 */ + mxc_request_iomux(MX37_PIN_SD2_DATA2, IOMUX_CONFIG_ALT1); + /*PATA_DA2 */ + mxc_request_iomux(MX37_PIN_SD2_DATA1, IOMUX_CONFIG_ALT1); + + /* BUFFER_ENABLE - HDD_ENABLE_B */ + mxc_request_iomux(MX37_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1); + + /* IOMUX Pad Settings */ + mxc_iomux_set_pad(MX37_PIN_EIM_D0, 0xc0); + mxc_iomux_set_pad(MX37_PIN_EIM_D1, 0xc0); + mxc_iomux_set_pad(MX37_PIN_EIM_D2, 0xc0); + mxc_iomux_set_pad(MX37_PIN_EIM_D3, 0xc0); + mxc_iomux_set_pad(MX37_PIN_EIM_D4, 0xc0); + mxc_iomux_set_pad(MX37_PIN_EIM_D5, 0xc0); + mxc_iomux_set_pad(MX37_PIN_EIM_D6, 0xc0); + mxc_iomux_set_pad(MX37_PIN_EIM_D7, 0xc0); + mxc_iomux_set_pad(MX37_PIN_EIM_D8, 0xc0); + mxc_iomux_set_pad(MX37_PIN_EIM_D9, 0xc0); + mxc_iomux_set_pad(MX37_PIN_EIM_D10, 0xc0); + mxc_iomux_set_pad(MX37_PIN_EIM_D11, 0xc0); + mxc_iomux_set_pad(MX37_PIN_EIM_D12, 0xc0); + mxc_iomux_set_pad(MX37_PIN_EIM_D13, 0xc0); + mxc_iomux_set_pad(MX37_PIN_EIM_D14, 0xc0); + mxc_iomux_set_pad(MX37_PIN_EIM_D15, 0xc0); + + mxc_iomux_set_pad(MX37_PIN_NANDF_RE_B, 0x0080); + mxc_iomux_set_pad(MX37_PIN_NANDF_CS1, 0x0020); + mxc_iomux_set_pad(MX37_PIN_SD2_DATA3, 0x00); + mxc_iomux_set_pad(MX37_PIN_SD2_DATA2, 0x00); + mxc_iomux_set_pad(MX37_PIN_SD2_DATA1, 0x00); + mxc_iomux_set_pad(MX37_PIN_NANDF_ALE, 0x00); + mxc_iomux_set_pad(MX37_PIN_NANDF_CS2, 0x00); + mxc_iomux_set_pad(MX37_PIN_NANDF_CS3, 0x00); + mxc_iomux_set_pad(MX37_PIN_NANDF_WE_B, 0x00); + mxc_iomux_set_pad(MX37_PIN_NANDF_CLE, 0x00); + mxc_iomux_set_pad(MX37_PIN_NANDF_WP_B, 0x00); + mxc_iomux_set_pad(MX37_PIN_NANDF_RB, 0x00); + mxc_iomux_set_pad(MX37_PIN_NANDF_CS0, 0x0020); + +} + +EXPORT_SYMBOL(gpio_ata_active); + +/*! + * Restore ATA interface pins to reset values + * + */ +void gpio_ata_inactive(void) +{ + /*Turn off the IOMUX for ATA group B signals */ + mxc_request_iomux(MX37_PIN_EIM_D0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_EIM_D1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_EIM_D2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_EIM_D3, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_EIM_D4, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_EIM_D5, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_EIM_D6, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_EIM_D7, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_EIM_D8, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_EIM_D9, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_EIM_D10, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_EIM_D11, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_EIM_D12, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_EIM_D13, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_EIM_D14, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_EIM_D15, IOMUX_CONFIG_ALT0); + + /* Config the multiplex pin of ATA interface DIR, DA0-2, INTRQ, DMARQ */ + mxc_request_iomux(MX37_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0); + + /* HDD_BUFF_EN (H:A->B, L:B->A) and HDD_ENABLE_B(H:Disable,L:Enable) */ + mxc_free_iomux(MX37_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0); + + /* These ATA pins are common to Group A and Group B */ + mxc_request_iomux(MX37_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_NANDF_RB, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX37_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0); + +} + +EXPORT_SYMBOL(gpio_ata_inactive); + +/*! + * Setup GPIO for Keypad to be active + * + */ +void gpio_keypad_active(void) +{ + int pad_val; + + /* + * Configure the IOMUX control register for keypad signals. + */ + /*KEY_INT */ + mxc_request_iomux(MX37_PIN_GPIO1_3, IOMUX_CONFIG_ALT0); + /*KEY_WAKE */ + mxc_request_iomux(MX37_PIN_DISP1_DAT18, IOMUX_CONFIG_ALT4); + + /* fast slew rate */ + pad_val = (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_22K_PU | \ + PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_HYS_NONE | \ + PAD_CTL_DDR_INPUT_CMOS | PAD_CTL_DRV_VOT_LOW); + /*KEY_INT */ + mxc_iomux_set_pad(MX37_PIN_GPIO1_3, pad_val); + + /* fast slew rate */ + pad_val = (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | \ + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_HYS_NONE | \ + PAD_CTL_DDR_INPUT_CMOS | PAD_CTL_DRV_VOT_LOW); + /*KEY_WAKE */ + mxc_iomux_set_pad(MX37_PIN_DISP1_DAT18, pad_val); + + mxc_set_gpio_direction(MX37_PIN_DISP1_DAT18, 0); + mxc_set_gpio_direction(MX37_PIN_GPIO1_3, 1); + + /* drive initial value */ + mxc_set_gpio_dataout(MX37_PIN_DISP1_DAT18, 1); +} + +EXPORT_SYMBOL(gpio_keypad_active); + +/*! + * Setup GPIO for Keypad to be inactive + * + */ +void gpio_keypad_inactive(void) +{ + /*KEY_INT */ + mxc_request_iomux(MX37_PIN_GPIO1_3, IOMUX_CONFIG_ALT0); + /*KEY_WAKE */ + mxc_request_iomux(MX37_PIN_DISP1_DAT18, IOMUX_CONFIG_ALT0); +} + +EXPORT_SYMBOL(gpio_keypad_inactive); + +/* + * USB OTG HS port + */ +int gpio_usbotg_hs_active(void) +{ + /*TODO*/ return 0; +} + +EXPORT_SYMBOL(gpio_usbotg_hs_active); + +void gpio_usbotg_hs_inactive(void) +{ + /*TODO*/} + +EXPORT_SYMBOL(gpio_usbotg_hs_inactive); + +/*! + * Setup GPIO for PCMCIA interface + * + */ +void gpio_pcmcia_active(void) +{ + /*TODO*/} + +EXPORT_SYMBOL(gpio_pcmcia_active); + +/*! + * Setup GPIO for pcmcia to be inactive + */ +void gpio_pcmcia_inactive(void) +{ + /*TODO*/} + +EXPORT_SYMBOL(gpio_pcmcia_inactive); + +/*! + * Setup GPIO for fec to be active + */ +void gpio_fec_active(void) +{ + /*TODO*/} + +EXPORT_SYMBOL(gpio_fec_active); +/*! + * Setup GPIO for fec to be inactive + */ +void gpio_fec_inactive(void) +{ + /*TODO*/} + +EXPORT_SYMBOL(gpio_fec_inactive); + +void gpio_spdif_active(void) +{ + iomux_pad_config_t regval = 0; + regval = + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU; + mxc_iomux_set_pad(MX37_PIN_AUD3_BB_RXD, regval); + mxc_request_iomux(MX37_PIN_AUD3_BB_RXD, IOMUX_CONFIG_ALT1); +} + +EXPORT_SYMBOL(gpio_spdif_active); + +void gpio_spdif_inactive(void) +{ + mxc_free_iomux(MX37_PIN_AUD3_BB_RXD, IOMUX_CONFIG_ALT1); +} + +EXPORT_SYMBOL(gpio_spdif_inactive); + +void gpio_pmic_active(void) +{ + mxc_request_iomux(MX37_PIN_OWIRE_LINE, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX37_PIN_OWIRE_LINE, PAD_CTL_SRE_SLOW | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_MEDIUM | + PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DDR_INPUT_CMOS); + mxc_set_gpio_direction(MX37_PIN_OWIRE_LINE, 1); +} + +EXPORT_SYMBOL(gpio_pmic_active); + +void gpio_gps_active(void) +{ + /* PWR_EN */ + mxc_request_iomux(MX37_PIN_EIM_OE, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX37_PIN_EIM_OE, PAD_CTL_100K_PU | + PAD_CTL_DRV_HIGH | PAD_CTL_HYS_NONE | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_set_gpio_direction(MX37_PIN_EIM_OE, 0); + + /* RESET */ + mxc_request_iomux(MX37_PIN_EIM_BCLK, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX37_PIN_EIM_BCLK, PAD_CTL_DRV_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_set_gpio_direction(MX37_PIN_EIM_BCLK, 0); + + mxc_set_gpio_dataout(MX37_PIN_EIM_OE, 0); + mxc_set_gpio_dataout(MX37_PIN_EIM_BCLK, 0); + + msleep(5); + mxc_set_gpio_dataout(MX37_PIN_EIM_BCLK, 1); + + msleep(5); +} + +EXPORT_SYMBOL(gpio_gps_active); + +int gpio_gps_access(int para) +{ + iomux_pin_name_t pin; + pin = (para & 0x1) ? MX37_PIN_EIM_OE : MX37_PIN_EIM_BCLK; + + if (para & 0x4) + return mxc_get_gpio_datain(pin); + else if (para & 0x2) + mxc_set_gpio_dataout(pin, 1); + else + mxc_set_gpio_dataout(pin, 0); + + return 0; +} + +EXPORT_SYMBOL(gpio_gps_access); + +void gpio_gps_inactive(void) +{ + mxc_free_iomux(MX37_PIN_EIM_BCLK, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX37_PIN_EIM_OE, IOMUX_CONFIG_GPIO); +} + +EXPORT_SYMBOL(gpio_gps_inactive); + +int headphone_det_status(void) +{ + return mxc_get_gpio_datain(MX37_PIN_AUD5_RXFS); +} + +EXPORT_SYMBOL(headphone_det_status); diff -urN linux-2.6.26/arch/arm/mach-mx37/mx37_3stack_pmic_wm8350.c linux-2.6.26-lab126/arch/arm/mach-mx37/mx37_3stack_pmic_wm8350.c --- linux-2.6.26/arch/arm/mach-mx37/mx37_3stack_pmic_wm8350.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/mx37_3stack_pmic_wm8350.c 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,411 @@ +/* + * mx37-3stack-pmic-wm8350.c -- i.MX37 3STACK Driver for Wolfson WM8350 PMIC + * + * Copyright 2007 Wolfson Microelectronics PLC. + * Copyright 2008-2009 Freescale Semiconductor Inc. + * + * Author: Liam Girdwood + * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include "iomux.h" +#include "board-mx37_3stack.h" + +static void wm8350_regulator_init(void) +{ + int i = 0; + struct regulator *regulator; + char *wm8350_global_regulator[] = { + "DCDC1", + "DCDC3", + "DCDC4", + "DCDC6", + "LDO3", + }; + + /* for board v2.0 later, do nothing here*/ + if (board_is_mx37(BOARD_REV_2)) + return; + while (!IS_ERR_VALUE((unsigned long)(regulator = regulator_get(NULL, + wm8350_global_regulator[i])))) { + regulator_enable(regulator); + i++; + } +} +late_initcall(wm8350_regulator_init); + +/* + * Set to 1 when testing battery that is connected otherwise spuriuos debug + */ +#define BATTERY 0 + +/* extern const char imx_3stack_audio[32]; */ + +struct mxc_audio_platform_data imx_3stack_audio_platform_data = { + .ssi_num = 2, + .src_port = 2, + .ext_port = 5, + .regulator1 = "DCDC6", + .regulator2 = "DCDC3" +}; + +static void imx37_3stack_switch_handler(struct wm8350 *wm8350, int irq) +{ + printk("switch pressed %d\n", irq); +} + +static struct platform_device *imx_snd_device; + +void wm8350_free(struct wm8350 *wm8350) +{ +#if BATTERY + struct wm8350_power *power = &wm8350->power; +#endif + + wm8350_mask_irq(wm8350, WM8350_IRQ_GPIO(7)); + wm8350_free_irq(wm8350, WM8350_IRQ_GPIO(7)); + wm8350_mask_irq(wm8350, WM8350_IRQ_WKUP_ONKEY); + wm8350_free_irq(wm8350, WM8350_IRQ_WKUP_ONKEY); + +#if BATTERY + wm8350_charger_enable(power, 0); + wm8350_fast_charger_enable(power, 0); +#endif + if (wm8350->nirq) + free_irq(wm8350->nirq, wm8350); + + flush_scheduled_work(); + + if (device_is_registered(&wm8350->pmic.dev)) + device_unregister(&wm8350->pmic.dev); + if (device_is_registered(&wm8350->rtc.dev)) + device_unregister(&wm8350->rtc.dev); + if (device_is_registered(&wm8350->wdg.dev)) + device_unregister(&wm8350->wdg.dev); + if (device_is_registered(&wm8350->power.dev)) + device_unregister(&wm8350->power.dev); + + platform_device_unregister(imx_snd_device); +} + +#if BATTERY +static int wm8350_init_battery(struct wm8350 *wm8350) +{ + struct wm8350_power *power = &wm8350->power; + struct wm8350_charger_policy *policy = &power->policy; + + policy->eoc_mA = WM8350_CHG_EOC_mA(10); + policy->charge_mV = WM8350_CHG_4_05V; + policy->fast_limit_mA = WM8350_CHG_FAST_LIMIT_mA(400); + policy->charge_timeout = WM8350_CHG_TIME_MIN(60); + policy->trickle_start_mV = WM8350_CHG_TRICKLE_3_1V; + policy->trickle_charge_mA = WM8350_CHG_TRICKLE_50mA; + + wm8350_charger_enable(power, 1); + wm8350_fast_charger_enable(power, 1); + return 0; +} +#endif + +#ifdef NOT_PORTED_TO_IMX37_3STACK_YET +static int config_gpios(struct wm8350 *wm8350) +{ + /* power on */ + wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN, + WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW, + WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF, + WM8350_GPIO_DEBOUNCE_ON); + + /* Sw3 --> PWR_OFF_GPIO3 */ + /* lg - TODO: GPIO1_0 to be pulled down */ + wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN, + WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH, + WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, + WM8350_GPIO_DEBOUNCE_ON); + + /* MR or MEMRST ????? */ + wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN, + WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH, + WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, + WM8350_GPIO_DEBOUNCE_OFF); + + /* Hibernate -- GPIO 7 */ + wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN, + WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH, + WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, + WM8350_GPIO_DEBOUNCE_OFF); + + /* SDOUT */ + wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT, + WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH, + WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, + WM8350_GPIO_DEBOUNCE_OFF); + + /* GPIO switch SW2 */ + wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN, WM8350_GPIO7_GPIO_IN, + WM8350_GPIO_ACTIVE_HIGH, WM8350_GPIO_PULL_DOWN, + WM8350_GPIO_INVERT_OFF, WM8350_GPIO_DEBOUNCE_ON); + wm8350_register_irq(wm8350, WM8350_IRQ_GPIO(7), + imx37_3stack_switch_handler, NULL); + wm8350_unmask_irq(wm8350, WM8350_IRQ_GPIO(7)); + + /* PWR_FAIL */ + wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT, + WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW, + WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, + WM8350_GPIO_DEBOUNCE_OFF); + + /* BATT Fault */ + wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT, + WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW, + WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, + WM8350_GPIO_DEBOUNCE_OFF); + + return 0; +} + +static int config_hibernate(struct wm8350 *wm8350) +{ + struct wm8350_pmic *pmic = &wm8350->pmic; + + /* dont assert RTS when hibernating */ + wm8350_set_bits(wm8350, WM8350_SYSTEM_HIBERNATE, WM8350_RST_HIB_MODE); + + /* set up hibernate voltages -- needs refining */ + wm8350_dcdc_set_image_voltage(pmic, WM8350_DCDC_1, 1400, /*1200, *//* 1.0v for mx32 */ + WM8350_DCDC_HIB_MODE_IMAGE, + WM8350_DCDC_HIB_SIG_REG); + wm8350_dcdc_set_image_voltage(pmic, WM8350_DCDC_3, 2800, + WM8350_DCDC_HIB_MODE_IMAGE, + WM8350_DCDC_HIB_SIG_REG); + wm8350_dcdc_set_image_voltage(pmic, WM8350_DCDC_4, 1800, + WM8350_DCDC_HIB_MODE_IMAGE, + WM8350_DCDC_HIB_SIG_REG); + wm8350_dcdc_set_image_voltage(pmic, WM8350_DCDC_6, 1800, + WM8350_DCDC_HIB_MODE_IMAGE, + WM8350_DCDC_HIB_SIG_REG); + wm8350_ldo_set_image_voltage(pmic, WM8350_LDO_1, 2800, + WM8350_LDO_HIB_MODE_IMAGE, + WM8350_LDO_HIB_SIG_REG); + wm8350_ldo_set_image_voltage(pmic, WM8350_LDO_2, 3300, + WM8350_LDO_HIB_MODE_IMAGE, + WM8350_LDO_HIB_SIG_REG); + wm8350_ldo_set_image_voltage(pmic, WM8350_LDO_3, 1500, + WM8350_LDO_HIB_MODE_IMAGE, + WM8350_LDO_HIB_SIG_REG); + wm8350_ldo_set_image_voltage(pmic, WM8350_LDO_4, 2500, + WM8350_LDO_HIB_MODE_IMAGE, + WM8350_LDO_HIB_MODE_DIS); + return 0; +} +#endif + +struct regulation_constraints led_regulation_constraints = { + .min_uA = 0, + .max_uA = 230000, + .valid_ops_mask = REGULATOR_CHANGE_CURRENT, +}; +struct regulation_constraints dcdc1_regulation_constraints = { + .min_uV = mV_to_uV(850), + .max_uV = mV_to_uV(1200), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE, +}; +struct regulation_constraints dcdc4_regulation_constraints = { + .min_uV = mV_to_uV(1000), + .max_uV = mV_to_uV(1200), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE, +}; + +static void set_regulator_constraints(struct wm8350 *wm8350) +{ + regulator_set_platform_constraints("DCDC1", + &dcdc1_regulation_constraints); + regulator_set_platform_constraints("DCDC4", + &dcdc4_regulation_constraints); + regulator_set_platform_constraints("ISINKA", + &led_regulation_constraints); +} + +static void wm8350_nop_release(struct device *dev) +{ + /* Nothing */ +} + +static int wm8350_check_fb(struct fb_info *info) +{ + return (to_platform_device(info->device)->id == 0); +} + +struct wm8350_bl_platform_data wm8350_bl_data = { + .isink = WM8350_ISINK_A, + .dcdc = WM8350_DCDC_5, + .voltage_ramp = WM8350_DC5_RMP_20V, + .retries = 5, + .max_brightness = 63, + .power = FB_BLANK_UNBLANK, + .brightness = 50, + .check_fb = wm8350_check_fb, +}; + +static struct platform_device mxc_wm8350_devices[] = { + { + .name = "wm8350-bl", + .id = 2, + .dev = { + .release = wm8350_nop_release, + .platform_data = &wm8350_bl_data, + }, + }, +}; + +static inline void mxc_init_wm8350(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mxc_wm8350_devices); i++) { + if (platform_device_register(&mxc_wm8350_devices[i]) < 0) + dev_err(&mxc_wm8350_devices[i].dev, + "Unable to register WM8350 device\n"); + } + + /*set INT pin*/ + mxc_request_iomux(MX37_PIN_GPIO1_4, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX37_PIN_GPIO1_4, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_22K_PU | + PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_HYS_NONE | + PAD_CTL_DDR_INPUT_CMOS | PAD_CTL_DRV_VOT_LOW); +} + +int wm8350_init(struct wm8350 *wm8350) +{ + int ret = 0; + + /* register regulator and set constraints */ + wm8350_device_register_pmic(wm8350); + set_regulator_constraints(wm8350); +#ifdef NOT_PORTED_TO_IMX37 + wm8350_device_register_rtc(wm8350); + wm8350_device_register_wdg(wm8350); + wm8350_device_register_power(wm8350); +#endif + mxc_init_wm8350(); + + /*Note: Needs to be moved into a regulator function. */ + /* Configuring -- GPIO 7 pin */ + if (wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_OUT, 0, + WM8350_GPIO_ACTIVE_LOW, WM8350_GPIO_PULL_NONE, + WM8350_GPIO_INVERT_OFF, + WM8350_GPIO_DEBOUNCE_OFF) == 0) + wm8350_gpio_set_status(wm8350, 7, 1); + else + printk(KERN_ERR "Error in setting Wolfson GPIO pin 7 \n"); + /* enable gpio4:USB_VBUS_EN */ + ret = + wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN, + WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH, + WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF, + WM8350_GPIO_DEBOUNCE_OFF); + if (ret) + printk(KERN_ERR "Error in setting USB VBUS enable pin\n"); + + /*PMIC RDY*/ + if (wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT, WM8350_GPIO9_GPIO_OUT, + WM8350_GPIO_ACTIVE_LOW, WM8350_GPIO_PULL_NONE, + WM8350_GPIO_INVERT_OFF, WM8350_GPIO_DEBOUNCE_OFF) == 0) + wm8350_gpio_set_status(wm8350, 9, 1); + else + printk(KERN_ERR "Error in setting Wolfson GPIO pin 9 \n"); + + /* register sound */ + printk("Registering imx37_snd_device"); + imx_snd_device = platform_device_alloc("wm8350-imx-3stack-audio", -1); + if (!imx_snd_device) { + ret = -ENOMEM; + goto err; + } + imx_snd_device->dev.platform_data = &imx_3stack_audio_platform_data; + platform_set_drvdata(imx_snd_device, &wm8350->audio); + ret = platform_device_add(imx_snd_device); + if (ret) + goto snd_err; + + /* set up PMIC IRQ (active high) to i.MX32ADS */ + printk("Registering PMIC INT"); + INIT_WORK(&wm8350->work, wm8350_irq_work); + wm8350_reg_unlock(wm8350); + wm8350_set_bits(wm8350, WM8350_SYSTEM_CONTROL_1, WM8350_IRQ_POL); + wm8350_reg_lock(wm8350); + set_irq_type(MXC_PMIC_INT_LINE, IRQT_RISING); + ret = request_irq(MXC_PMIC_INT_LINE, wm8350_irq_handler, + IRQF_DISABLED, "wm8350-pmic", wm8350); + if (ret != 0) { + printk(KERN_ERR "wm8350: cant request irq %d\n", + MXC_PMIC_INT_LINE); + goto err; + } + wm8350->nirq = MXC_PMIC_INT_LINE; + + set_irq_wake(MXC_PMIC_INT_LINE, 1); + +#ifdef NOT_PORTED_TO_IMX37 + printk("Configuring WM8350 GPIOS"); + config_gpios(wm8350); + config_hibernate(wm8350); +#endif + + /* Sw1 --> PWR_ON */ + printk("Registering and unmasking the WM8350 wakeup key\n"); + wm8350_register_irq(wm8350, WM8350_IRQ_WKUP_ONKEY, + imx37_3stack_switch_handler, NULL); + wm8350_unmask_irq(wm8350, WM8350_IRQ_WKUP_ONKEY); + + /* unmask all & clear sticky */ + printk("Unmasking WM8350 local interrupts\n"); + wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x3ffe); + schedule_work(&wm8350->work); + +#if BATTERY + /* not much use without a battery atm */ + wm8350_init_battery(wm8350); +#endif + + printk("Exiting normally from wm8350_init()"); + return ret; + snd_err: + platform_device_put(imx_snd_device); + + err: + printk("wm8350_init() FAILED"); + kfree(wm8350->reg_cache); + return ret; +} diff -urN linux-2.6.26/arch/arm/mach-mx37/mx37_pins.h linux-2.6.26-lab126/arch/arm/mach-mx37/mx37_pins.h --- linux-2.6.26/arch/arm/mach-mx37/mx37_pins.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/mx37_pins.h 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,256 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_MX37_PINS_H__ +#define __ASM_ARCH_MXC_MX37_PINS_H__ + +/*! + * @file arch-mxc/mx37_pins.h + * + * @brief MX37 I/O Pin List + * + * @ingroup GPIO_MX37 + */ + +#ifndef __ASSEMBLY__ + +/*! + * @name IOMUX/PAD Bit field definitions + */ + +/*! @{ */ + +/*! + * In order to identify pins more effectively, each mux-controlled pin's + * enumerated value is constructed in the following way: + * + * ------------------------------------------------------------------- + * 31-29 | 28 - 24 | 23 | 22 - 20 | 19 - 10| 9 - 0 + * ------------------------------------------------------------------- + * IO_P | IO_I | RSVD_I | GPIO_I | PAD_I | MUX_I + * ------------------------------------------------------------------- + * + * Bit 0 to 9 contains MUX_I used to identify the register + * offset (0-based. base is IOMUX_module_base) defined in the Section + * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The + * similar field definitions are used for the pad control register. + * For example, the MX37_PIN_ETM_D0 is defined in the enumeration: + * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I) + * It means the mux control register is at register offset 0x28. The pad control + * register offset is: 0x250 and also occupy the least significant bits + * within the register. + */ + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * MUX control register offset + */ +#define MUX_I 0 +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * PAD control register offset + */ +#define PAD_I 10 +/*! + * Starting bit position within each entry of \b iomux_pins to represent which + * mux mode is for GPIO (0-based) + */ +#define GPIO_I 20 +/*! + * Starting bit position which is reserved. + */ +#define RSVD_I 23 + +#define NON_GPIO_PORT 0x7 +#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) -1) +#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1) +#define PIN_TO_ALT_GPIO_MASK ((1 << (RSVD_I - GPIO_I)) - 1) + +#define NON_MUX_I PIN_TO_MUX_MASK +#define MUX_I_START 0x0008 +#define MUX_I_END (PAD_I_START - 4) +#define PAD_I_START 0x230 +#define PAD_I_END (INPUT_CTL_START - 4) +#define INPUT_CTL_START 0x508 +#define INPUT_CTL_END 0x614 + +#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \ + (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ + ((mi - MUX_I_START) << MUX_I) | \ + ((pi - PAD_I_START) << PAD_I) | \ + ((ga) << GPIO_I)) + +#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \ + _MXC_BUILD_PIN(gp, gi, ga, mi, pi) + +#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \ + _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi) + +#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) +#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) +#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK) +#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2) + +/*! @} End IOMUX/PAD Bit field definitions */ + +/*! + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX37 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ +enum iomux_pins { + MX37_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x8, 0x230), + MX37_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0xC, 0x234), + MX37_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x10, 0x238), + MX37_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x14, 0x23C), + MX37_PIN_KEY_ROW4 = _MXC_BUILD_NON_GPIO_PIN(0x18, 0x240), + MX37_PIN_KEY_ROW5 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x244), + MX37_PIN_KEY_ROW6 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x248), + MX37_PIN_KEY_ROW7 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x24C), + MX37_PIN_ETM_D0 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x250), + MX37_PIN_ETM_D1 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x254), + MX37_PIN_ETM_D2 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x258), + MX37_PIN_ETM_D3 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x25C), + MX37_PIN_ETM_D4 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x260), + MX37_PIN_ETM_D5 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x264), + MX37_PIN_ETM_D6 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x268), + MX37_PIN_ETM_D7 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x26C), + MX37_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(0, 15, 3, 0x48, 0x2A8), + MX37_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(0, 14, 3, 0x4C, 0x2AC), + MX37_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(0, 13, 3, 0x50, 0x2B0), + MX37_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x54, 0x2B4), + MX37_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x58, 0x2B8), + MX37_PIN_EIM_ECB = _MXC_BUILD_GPIO_PIN(0, 12, 3, 0x5C, 0x2BC), + MX37_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(0, 11, 3, 0x60, 0x2C0), + MX37_PIN_EIM_BCLK = _MXC_BUILD_GPIO_PIN(0, 10, 3, 0x64, 0x2C4), + MX37_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(0, 9, 3, 0x68, 0x2C8), + MX37_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(1, 2, 4, 0x6C, 0x2CC), + MX37_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(1, 3, 4, 0x70, 0x2D0), + MX37_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(1, 4, 4, 0x74, 0x2D4), + MX37_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(1, 5, 4, 0x78, 0x2D8), + MX37_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(1, 6, 4, 0x7C, 0x2DC), + MX37_PIN_NANDF_RB = _MXC_BUILD_GPIO_PIN(1, 7, 4, 0x80, 0x2E0), + MX37_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(1, 8, 4, 0x84, 0x2E4), + MX37_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(1, 9, 4, 0x88, 0x2E8), + MX37_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(1, 10, 4, 0x8C, 0x2EC), + MX37_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(1, 11, 4, 0x90, 0x2F0), + MX37_PIN_EIM_D15 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x2F4), + MX37_PIN_EIM_D14 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x2F8), + MX37_PIN_EIM_D13 = _MXC_BUILD_NON_GPIO_PIN(0x9C, 0x2FC), + MX37_PIN_EIM_D12 = _MXC_BUILD_NON_GPIO_PIN(0xA0, 0x300), + MX37_PIN_EIM_D11 = _MXC_BUILD_NON_GPIO_PIN(0xA4, 0x304), + MX37_PIN_EIM_D10 = _MXC_BUILD_NON_GPIO_PIN(0xA8, 0x308), + MX37_PIN_EIM_D9 = _MXC_BUILD_NON_GPIO_PIN(0xAC, 0x30C), + MX37_PIN_EIM_D8 = _MXC_BUILD_GPIO_PIN(0, 8, 3, 0xB0, 0x310), + MX37_PIN_EIM_D7 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0xB4, 0x314), + MX37_PIN_EIM_D6 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0xB8, 0x318), + MX37_PIN_EIM_D5 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0xBC, 0x31C), + MX37_PIN_EIM_D4 = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0xC0, 0x320), + MX37_PIN_EIM_D3 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0xC4, 0x324), + MX37_PIN_EIM_D2 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0xC8, 0x328), + MX37_PIN_EIM_D1 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0xCC, 0x32C), + MX37_PIN_EIM_D0 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0xD0, 0x330), + MX37_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 16, 3, 0xD4, 0x334), + MX37_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 17, 3, 0xD8, 0x338), + MX37_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 18, 3, 0xDC, 0x33C), + MX37_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 19, 3, 0xE0, 0x340), + MX37_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0xE4, 0x344), + MX37_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0xE8, 0x348), + MX37_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0xEC, 0x34C), + MX37_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0xF0, 0x350), + MX37_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0xF4, 0x354), + MX37_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(0, 25, 3, 0xF8, 0x358), + MX37_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(0, 26, 3, 0xFC, 0x35C), + MX37_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(0, 27, 3, 0x100, 0x360), + MX37_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(1, 12, 4, 0x104, 0x364), + MX37_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(1, 13, 4, 0x108, 0x368), + MX37_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(1, 14, 4, 0x10C, 0x36C), + MX37_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(1, 15, 4, 0x110, 0x370), + MX37_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(1, 16, 4, 0x114, 0x374), + MX37_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(1, 17, 4, 0x118, 0x378), + MX37_PIN_AUD5_RXFS = _MXC_BUILD_GPIO_PIN(1, 18, 4, 0x11C, 0x37C), + MX37_PIN_AUD5_RXC = _MXC_BUILD_GPIO_PIN(1, 19, 4, 0x120, 0x380), + MX37_PIN_AUD5_WB_TXD = _MXC_BUILD_GPIO_PIN(1, 20, 4, 0x124, 0x384), + MX37_PIN_AUD5_WB_RXD = _MXC_BUILD_GPIO_PIN(1, 21, 4, 0x128, 0x388), + MX37_PIN_AUD5_WB_CK = _MXC_BUILD_GPIO_PIN(1, 22, 4, 0x12C, 0x38C), + MX37_PIN_AUD5_WB_FS = _MXC_BUILD_GPIO_PIN(1, 23, 4, 0x130, 0x390), + MX37_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x134, 0x394), + MX37_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x138, 0x398), + MX37_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x13C, 0x39C), + MX37_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x140, 0x3A0), + MX37_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x144, 0x3A4), + MX37_PIN_CSPI2_MOSI = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x148, 0x3A8), + MX37_PIN_CSPI2_MISO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x14C, 0x3AC), + MX37_PIN_CSPI2_SS0 = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x150, 0x3B0), + MX37_PIN_CSPI2_SS1 = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x154, 0x3B4), + MX37_PIN_CSPI2_SCLK = _MXC_BUILD_GPIO_PIN(2, 9, 4, 0x158, 0x3B8), + MX37_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(1, 24, 4, 0x15C, 0x3BC), + MX37_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(1, 25, 4, 0x160, 0x3C0), + MX37_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(1, 26, 4, 0x164, 0x3C4), + MX37_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(1, 27, 4, 0x168, 0x3C8), + MX37_PIN_UART1_DTR = _MXC_BUILD_GPIO_PIN(1, 28, 4, 0x16C, 0x3CC), + MX37_PIN_UART1_DSR = _MXC_BUILD_GPIO_PIN(1, 29, 4, 0x170, 0x3D0), + MX37_PIN_UART1_RI = _MXC_BUILD_GPIO_PIN(1, 30, 4, 0x174, 0x3D4), + MX37_PIN_UART1_DCD = _MXC_BUILD_GPIO_PIN(1, 31, 4, 0x178, 0x3D8), + MX37_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 31, 4, 0x17C, 0x3DC), + MX37_PIN_JTAG_DE_B = _MXC_BUILD_NON_GPIO_PIN(0x180, 0x3E0), + MX37_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 10, 4, 0x184, 0x3E4), + MX37_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 11, 4, 0x188, 0x3E8), + MX37_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 12, 4, 0x18C, 0x3EC), + MX37_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 13, 4, 0x190, 0x3F0), + MX37_PIN_DI1_PIN15 = _MXC_BUILD_GPIO_PIN(0, 30, 4, 0x194, 0), + MX37_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x198, 0x3F4), + MX37_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x3F8), + MX37_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x3FC), + MX37_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x400), + MX37_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x404), + MX37_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x408), + MX37_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x40C), + MX37_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x410), + MX37_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x414), + MX37_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x418), + MX37_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x41C), + MX37_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x420), + MX37_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x424), + MX37_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x1CC, 0x428), + MX37_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x1D0, 0x42C), + MX37_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x1D4, 0x430), + MX37_PIN_DISP1_DAT16 = _MXC_BUILD_GPIO_PIN(0, 28, 4, 0x1D8, 0x434), + MX37_PIN_DISP1_DAT17 = _MXC_BUILD_GPIO_PIN(0, 29, 4, 0x1DC, 0x438), + MX37_PIN_DISP1_DAT18 = _MXC_BUILD_GPIO_PIN(2, 14, 4, 0x1E0, 0x43C), + MX37_PIN_DISP1_DAT19 = _MXC_BUILD_GPIO_PIN(2, 15, 4, 0x1E4, 0x440), + MX37_PIN_DISP1_DAT20 = _MXC_BUILD_GPIO_PIN(2, 16, 4, 0x1E8, 0x444), + MX37_PIN_DISP1_DAT21 = _MXC_BUILD_GPIO_PIN(2, 17, 4, 0x1EC, 0x448), + MX37_PIN_DISP1_DAT22 = _MXC_BUILD_GPIO_PIN(2, 18, 4, 0x1F0, 0x44C), + MX37_PIN_DISP1_DAT23 = _MXC_BUILD_GPIO_PIN(2, 18, 4, 0x1F4, 0x450), + MX37_PIN_PAD_DI1_PIN3 = _MXC_BUILD_GPIO_PIN(2, 29, 4, 0x1F8, 0), + MX37_PIN_DISP_CLK = _MXC_BUILD_GPIO_PIN(2, 30, 4, 0x1FC, 0), + MX37_PIN_DI1_PIN2 = _MXC_BUILD_GPIO_PIN(2, 31, 4, 0x200, 0), + MX37_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(0x204, 0x454), + MX37_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(0x208, 0x458), + MX37_PIN_WDOG_RST = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x20C, 0x464), + MX37_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 0, 0x210, 0x468), + MX37_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 0, 0x214, 0x46C), + MX37_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x218, 0x470), + MX37_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x21C, 0x474), + MX37_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x220, 0x478), + MX37_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x224, 0x47C), + MX37_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x228, 0x480), + MX37_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x22C, 0x484), + MX37_PIN_GRP_H10 = _MXC_BUILD_NON_GPIO_PIN(0x230, 0x490), + MX37_PIN_GRP_H9 = _MXC_BUILD_NON_GPIO_PIN(0x230, 0x494), + MX37_PIN_GRP_H3 = _MXC_BUILD_NON_GPIO_PIN(0x230, 0x4D0), + MX37_PIN_GRP_H5 = _MXC_BUILD_NON_GPIO_PIN(0x230, 0x4EC), +}; + +#endif /* */ +#endif /* */ diff -urN linux-2.6.26/arch/arm/mach-mx37/pm.c linux-2.6.26-lab126/arch/arm/mach-mx37/pm.c --- linux-2.6.26/arch/arm/mach-mx37/pm.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/pm.c 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,72 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include + +static int mx37_suspend_enter(suspend_state_t state) +{ + if (tzic_enable_wake(0) != 0) + return -EAGAIN; + + switch (state) { + case PM_SUSPEND_MEM: + mxc_cpu_lp_set(STOP_POWER_OFF); + break; + case PM_SUSPEND_STANDBY: + mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); + break; + default: + return -EINVAL; + } + cpu_do_idle(); + + return 0; +} + +/* + * Called after processes are frozen, but before we shut down devices. + */ +static int mx37_suspend_prepare(void) +{ + return 0; +} + +/* + * Called after devices are re-setup, but before processes are thawed. + */ +static void mx37_suspend_finish(void) +{ +} + +static int mx37_pm_valid(suspend_state_t state) +{ + return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); +} + +struct platform_suspend_ops mx37_suspend_ops = { + .valid = mx37_pm_valid, + .prepare = mx37_suspend_prepare, + .enter = mx37_suspend_enter, + .finish = mx37_suspend_finish, +}; + +static int __init mx37_pm_init(void) +{ + pr_info("Static Power Management for Freescale i.MX37\n"); + suspend_set_ops(&mx37_suspend_ops); + + return 0; +} + +late_initcall(mx37_pm_init); diff -urN linux-2.6.26/arch/arm/mach-mx37/sdma_script_code.h linux-2.6.26-lab126/arch/arm/mach-mx37/sdma_script_code.h --- linux-2.6.26/arch/arm/mach-mx37/sdma_script_code.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/sdma_script_code.h 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,203 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + +/*! + * @file sdma_script_code.h + * @brief This file contains functions of SDMA scripts code initialization + * + * The file was generated automatically. Based on sdma scripts library. + * + * @ingroup SDMA + */ +/******************************************************************************* + + SDMA RELEASE LABEL: "SS15_MARLEY" + +*******************************************************************************/ + +#ifndef __SDMA_SCRIPT_CODE_H__ +#define __SDMA_SCRIPT_CODE_H__ + +/*! +* SDMA ROM scripts start addresses and sizes +*/ + +#define start_ADDR 0 +#define start_SIZE 20 + +#define core_ADDR 80 +#define core_SIZE 232 + +#define common_ADDR 312 +#define common_SIZE 330 + +#define ap_2_ap_ADDR 642 +#define ap_2_ap_SIZE 41 + +#define app_2_mcu_ADDR 683 +#define app_2_mcu_SIZE 64 + +#define mcu_2_app_ADDR 747 +#define mcu_2_app_SIZE 70 + +#define uart_2_mcu_ADDR 817 +#define uart_2_mcu_SIZE 75 + +#define shp_2_mcu_ADDR 892 +#define shp_2_mcu_SIZE 69 + +#define mcu_2_shp_ADDR 961 +#define mcu_2_shp_SIZE 72 + +#define uartsh_2_mcu_ADDR 1033 +#define uartsh_2_mcu_SIZE 69 + +#define mcu_2_ata_ADDR 1102 +#define mcu_2_ata_SIZE 81 + +#define ata_2_mcu_ADDR 1183 +#define ata_2_mcu_SIZE 96 + +#define burstDMA__2__burstDMA_routine_ADDR 1279 +#define burstDMA__2__burstDMA_routine_SIZE 227 + +#define test_ADDR 1506 +#define test_SIZE 63 + +#define signature_ADDR 1023 +#define signature_SIZE 1 + +/*! +* SDMA RAM scripts start addresses and sizes +*/ + +#define dptc_dvfs_ADDR 6144 +#define dptc_dvfs_SIZE 270 + +#define ext_mem__ipu_ram_ADDR 6414 +#define ext_mem__ipu_ram_SIZE 123 + +#define mcu_2_mshc_ADDR 6537 +#define mcu_2_mshc_SIZE 54 + +#define mcu_2_spdif_marley_ADDR 6591 +#define mcu_2_spdif_marley_SIZE 161 + +#define mshc_2_mcu_ADDR 6752 +#define mshc_2_mcu_SIZE 54 + +/*! +* SDMA RAM image start address and size +*/ + +#define RAM_CODE_START_ADDR 6144 +#define RAM_CODE_SIZE 662 + +/*! +* Buffer that holds the SDMA RAM image +*/ +__attribute__ ((__aligned__(4))) +#ifndef CONFIG_XIP_KERNEL +const +#endif +static const short sdma_code[] = { + 0xc13c, 0x7d70, 0x0800, 0x0970, 0x0111, 0x5111, 0x5ac1, 0x5bc9, + 0x028e, 0xc14e, 0x068a, 0x7c66, 0x5dd9, 0x5ce1, 0x0bff, 0x0311, + 0x1bff, 0x03bc, 0x5bd1, 0x1a5c, 0x6ac3, 0x63c8, 0x0363, 0x7c05, + 0x036f, 0x7d27, 0x0374, 0x7c76, 0x9874, 0xd907, 0x3c06, 0x4c00, + 0x7df7, 0x028f, 0x1a04, 0x6a20, 0x620b, 0x6f20, 0x301f, 0x00aa, + 0x0462, 0x7c04, 0x4a00, 0x7d0b, 0x2001, 0x9837, 0x048a, 0x620b, + 0x2201, 0x1c01, 0x1801, 0x02dc, 0x7d02, 0x301f, 0x00aa, 0x048f, + 0x1c04, 0x6c04, 0x0488, 0x3c1f, 0x6c2b, 0x0045, 0x028e, 0x1a5c, + 0x9818, 0x058f, 0x1d0c, 0x6d20, 0x650b, 0x007d, 0x7c01, 0x1d08, + 0x007c, 0x7c01, 0x1d04, 0x6d20, 0x650b, 0x0488, 0x3c1f, 0x0417, + 0x0417, 0x0417, 0x0417, 0x059c, 0x6d20, 0x028e, 0x1a34, 0x6ad7, + 0x0488, 0x0804, 0x7802, 0x650b, 0x6dc8, 0x008c, 0x1a28, 0x6ad7, + 0x63c8, 0x034c, 0x6bc8, 0x54d1, 0x4c00, 0x7d06, 0x0065, 0x7c02, + 0x0101, 0x0025, 0x0400, 0x9814, 0x52c1, 0x53c9, 0x54e1, 0x0453, + 0xc159, 0x7d95, 0x0200, 0x9800, 0x55d9, 0x6d04, 0x54d1, 0x058a, + 0x2508, 0x6dc7, 0x0373, 0x7c03, 0x65c8, 0x6d0b, 0x2408, 0x0372, + 0x7c04, 0x65c8, 0x6d0b, 0x2408, 0x9889, 0x6cce, 0x65c8, 0x6d0a, + 0x2404, 0x6d28, 0x6504, 0x5dd9, 0x5cd1, 0x6ad7, 0x6ae3, 0x63c8, + 0x0334, 0x6bc8, 0x0370, 0x7cad, 0x0c60, 0x0411, 0x04bb, 0x4c00, + 0x7da8, 0x0410, 0x1c30, 0x0410, 0x04bb, 0x046d, 0x7d0a, 0x047d, + 0x7c03, 0x047c, 0x7c01, 0x9841, 0x003b, 0x003a, 0x0039, 0x0058, + 0x98b8, 0x047d, 0x7d03, 0x047c, 0x7d01, 0x9841, 0x005b, 0xd8fc, + 0x1d18, 0x6d20, 0x650b, 0x0510, 0x003a, 0x0039, 0x0038, 0x00ad, + 0xd907, 0x0c30, 0x0410, 0x04bb, 0x003c, 0x003d, 0x00ac, 0xd8fc, + 0x007b, 0x7c04, 0x003d, 0x003c, 0x1d0c, 0x98d9, 0x048f, 0x1c14, + 0x6c20, 0x640b, 0x4401, 0x7d04, 0x005d, 0x005c, 0x1d0c, 0x98d9, + 0x0310, 0x3b30, 0x4b30, 0x7d01, 0x1b10, 0x0310, 0x003d, 0x003c, + 0x00ab, 0x6ad7, 0x63c8, 0x6d20, 0x650b, 0x0560, 0x7d03, 0x005e, + 0xd8f0, 0x9841, 0x003e, 0x0c80, 0x0410, 0x0394, 0xd8f0, 0x640b, + 0x037f, 0x7d02, 0x1a14, 0x98ed, 0x1a0c, 0x6ad7, 0x6cc8, 0x9841, + 0x0c7f, 0x0410, 0x03b4, 0x04b8, 0x03ac, 0x640b, 0x6bc8, 0x028e, + 0x1a04, 0x6ad7, 0x6cc8, 0x0006, 0x058f, 0x1d08, 0x6d20, 0x650b, + 0x007d, 0x7c01, 0x1d38, 0x007c, 0x7c01, 0x1d1c, 0x0006, 0x048b, + 0x042c, 0x0454, 0x042b, 0x6ad7, 0x6cc8, 0x0006, 0x0e70, 0x0611, + 0x5616, 0xc13c, 0x7d2a, 0x5ade, 0x008e, 0xc14e, 0x7c26, 0x5be0, + 0x5ef0, 0x5ce8, 0x0688, 0x08ff, 0x0011, 0x28ff, 0x00bc, 0x53f6, + 0x05df, 0x7d0b, 0x6dc5, 0x03df, 0x7d03, 0x6bd5, 0xd95d, 0x9939, + 0x6b05, 0xc55f, 0x7e27, 0x7f29, 0x9939, 0x6d01, 0x03df, 0x7d05, + 0x6bd5, 0xc589, 0x7e18, 0x7f1a, 0x9939, 0x6b05, 0xc4ff, 0x7e07, + 0x7f06, 0x52de, 0x53e6, 0xc159, 0x7dd7, 0x0200, 0x9911, 0x0007, + 0x6004, 0x680c, 0x53f6, 0x028e, 0x00a3, 0xc256, 0x048b, 0x0498, + 0x0454, 0x068a, 0x9939, 0x0207, 0x680c, 0x6ddf, 0x0107, 0x68ff, + 0x60d0, 0x9942, 0x0207, 0x68ff, 0x6d28, 0x0107, 0x6004, 0x680c, + 0x9942, 0x0007, 0x68ff, 0x60d0, 0x9942, 0x0288, 0x03a5, 0x3b03, + 0x3d03, 0x4d00, 0x7d0a, 0x0804, 0x00a5, 0x00da, 0x7d1a, 0x02a0, + 0x7b01, 0x65d8, 0x7eee, 0x65ff, 0x7eec, 0x0804, 0x02d0, 0x7d11, + 0x4b00, 0x7c0f, 0x008a, 0x3003, 0x6dcf, 0x6bdf, 0x0015, 0x0015, + 0x7b02, 0x65d8, 0x0000, 0x7edd, 0x63ff, 0x7edb, 0x3a03, 0x6dcd, + 0x6bdd, 0x008a, 0x7b02, 0x65d8, 0x0000, 0x7ed3, 0x65ff, 0x7ed1, + 0x0006, 0xc1d9, 0x0b70, 0x0311, 0x5313, 0x58d3, 0x008b, 0x5efb, + 0xc13c, 0x7d2b, 0x5ac0, 0x5bc8, 0xc14e, 0x7c27, 0x6d01, 0x0388, + 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d1a, 0x0e70, 0x0611, + 0x522e, 0x02b9, 0x4a00, 0x7c07, 0x52fe, 0x50d3, 0x02b8, 0x4a00, + 0x7c02, 0x0400, 0x999e, 0x56fb, 0x620b, 0x7e06, 0x5a06, 0x7f06, + 0x0000, 0x2504, 0x7d05, 0x999e, 0x0007, 0x680c, 0x0007, 0x0454, + 0x008b, 0x52c0, 0x53c8, 0xc159, 0x7dd6, 0x0200, 0x9990, 0xc1d9, + 0xc1e3, 0x0800, 0x005f, 0x00ac, 0x58e3, 0x0478, 0x7d5c, 0x0479, + 0x7d01, 0x0515, 0x0515, 0xda38, 0xda57, 0x0479, 0x7d26, 0x54e3, + 0x047f, 0x7d12, 0x50eb, 0x56fb, 0x0015, 0x52db, 0x7806, 0x5402, + 0x5c06, 0x1a01, 0x5402, 0x5c26, 0x1a01, 0x54e3, 0x043f, 0x5ce3, + 0x4d00, 0x7d4e, 0x0479, 0x7d14, 0x047f, 0x7d01, 0xda57, 0x52f3, + 0x6a21, 0x56db, 0x7803, 0x620b, 0x5a06, 0x1e01, 0x7f34, 0x7e33, + 0x6200, 0x5af3, 0x047f, 0x7dde, 0x9a20, 0x54e3, 0x047f, 0x7cda, + 0x54e3, 0x047f, 0x7d01, 0xda57, 0x54eb, 0x0fff, 0x0711, 0x1fff, + 0x56db, 0x52f3, 0x6a21, 0x630b, 0x028b, 0x03bf, 0xda32, 0x5b06, + 0x2401, 0x4c00, 0x7d0b, 0x1e01, 0x038a, 0x03b7, 0x0312, 0x0312, + 0xda32, 0x5b06, 0x1e01, 0x2401, 0x4c00, 0x7ced, 0x0b70, 0x0311, + 0x5313, 0x7f09, 0x7e08, 0x6200, 0x5af3, 0x54e3, 0x047f, 0x7db2, + 0x57db, 0xc1fa, 0x99cd, 0x0007, 0x680c, 0x54e3, 0x0478, 0x7c02, + 0x0800, 0x9a2e, 0x0479, 0x7d01, 0x0517, 0x0517, 0x5deb, 0xc213, + 0xc20a, 0x99c1, 0x0808, 0x7801, 0x0317, 0x0006, 0x020a, 0x0006, + 0x070a, 0xda36, 0x1a05, 0x0215, 0x5adb, 0x0708, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x080c, + 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x4800, 0x7dd2, 0x58eb, 0x0006, + 0xc1d9, 0x0b70, 0x0311, 0x5313, 0x58d3, 0x008b, 0x5efb, 0xc13c, + 0x7d2b, 0x5ac0, 0x5bc8, 0xc14e, 0x7c27, 0x0388, 0x6d05, 0x0dff, + 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d1a, 0x0e70, 0x0611, 0x522e, + 0x02b9, 0x4a00, 0x7c07, 0x52fe, 0x50d3, 0x02b8, 0x4a00, 0x7c02, + 0x0400, 0x9a75, 0x56fb, 0x5206, 0x7e08, 0x6a0b, 0x6a28, 0x7f04, + 0x0000, 0x2504, 0x7d04, 0x9a75, 0x680c, 0x0007, 0x0454, 0x008b, + 0x52c0, 0x53c8, 0xc159, 0x7dd6, 0x0200, 0x9a67 +}; +#endif diff -urN linux-2.6.26/arch/arm/mach-mx37/serial.c linux-2.6.26-lab126/arch/arm/mach-mx37/serial.c --- linux-2.6.26/arch/arm/mach-mx37/serial.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/serial.c 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,169 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @file mach-mx37/serial.c + * + * @brief This file contains the UART initiliazation. + * + * @ingroup MSL_MX37 + */ +#include +#include +#include +#include +#include +#include +#include "serial.h" +#include "board-mx37_3stack.h" + +#if defined(CONFIG_SERIAL_MXC) || defined(CONFIG_SERIAL_MXC_MODULE) + +/*! + * This is an array where each element holds information about a UART port, + * like base address of the UART, interrupt numbers etc. This structure is + * passed to the serial_core.c file. Based on which UART is used, the core file + * passes back the appropriate port structure as an argument to the control + * functions. + */ +static uart_mxc_port mxc_ports[] = { + [0] = { + .port = { + .membase = (void *)IO_ADDRESS(UART1_BASE_ADDR), + .mapbase = UART1_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART1_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 0, + }, + .ints_muxed = UART1_MUX_INTS, + .irqs = {UART1_INT2, UART1_INT3}, + .mode = UART1_MODE, + .ir_mode = UART1_IR, + .enabled = UART1_ENABLED, + .hardware_flow = UART1_HW_FLOW, + .cts_threshold = UART1_UCR4_CTSTL, + .dma_enabled = UART1_DMA_ENABLE, + .dma_rxbuf_size = UART1_DMA_RXBUFSIZE, + .rx_threshold = UART1_UFCR_RXTL, + .tx_threshold = UART1_UFCR_TXTL, + .shared = UART1_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART1_TX, + .dma_rx_id = MXC_DMA_UART1_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, + [1] = { + .port = { + .membase = (void *)IO_ADDRESS(UART2_BASE_ADDR), + .mapbase = UART2_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART2_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 1, + }, + .ints_muxed = UART2_MUX_INTS, + .irqs = {UART2_INT2, UART2_INT3}, + .mode = UART2_MODE, + .ir_mode = UART2_IR, + .enabled = UART2_ENABLED, + .hardware_flow = UART2_HW_FLOW, + .cts_threshold = UART2_UCR4_CTSTL, + .dma_enabled = UART2_DMA_ENABLE, + .dma_rxbuf_size = UART2_DMA_RXBUFSIZE, + .rx_threshold = UART2_UFCR_RXTL, + .tx_threshold = UART2_UFCR_TXTL, + .shared = UART2_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART2_TX, + .dma_rx_id = MXC_DMA_UART2_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, + [2] = { + .port = { + .membase = (void *)IO_ADDRESS(UART3_BASE_ADDR), + .mapbase = UART3_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART3_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 2, + }, + .ints_muxed = UART3_MUX_INTS, + .irqs = {UART3_INT2, UART3_INT3}, + .mode = UART3_MODE, + .ir_mode = UART3_IR, + .enabled = UART3_ENABLED, + .hardware_flow = UART3_HW_FLOW, + .cts_threshold = UART3_UCR4_CTSTL, + .dma_enabled = UART3_DMA_ENABLE, + .dma_rxbuf_size = UART3_DMA_RXBUFSIZE, + .rx_threshold = UART3_UFCR_RXTL, + .tx_threshold = UART3_UFCR_TXTL, + .shared = UART3_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART3_TX, + .dma_rx_id = MXC_DMA_UART3_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, +}; + +static struct platform_device mxc_uart_device1 = { + .name = "mxcintuart", + .id = 0, + .dev = { + .platform_data = &mxc_ports[0], + }, +}; + +static struct platform_device mxc_uart_device2 = { + .name = "mxcintuart", + .id = 1, + .dev = { + .platform_data = &mxc_ports[1], + }, +}; + +static struct platform_device mxc_uart_device3 = { + .name = "mxcintuart", + .id = 2, + .dev = { + .platform_data = &mxc_ports[2], + }, +}; + +static int __init mxc_init_uart(void) +{ + /* Register all the MXC UART platform device structures */ + platform_device_register(&mxc_uart_device1); + platform_device_register(&mxc_uart_device2); + + /* Grab ownership of shared UARTs 3 and 4, only when enabled */ +#if UART3_ENABLED == 1 +#if UART3_DMA_ENABLE == 1 + spba_take_ownership(UART3_SHARED_PERI, (SPBA_MASTER_A | SPBA_MASTER_C)); +#else + spba_take_ownership(UART3_SHARED_PERI, SPBA_MASTER_A); +#endif /* UART3_DMA_ENABLE */ + platform_device_register(&mxc_uart_device3); +#endif /* UART3_ENABLED */ + + return 0; +} + +#else +static int __init mxc_init_uart(void) +{ + return 0; +} +#endif + +arch_initcall(mxc_init_uart); diff -urN linux-2.6.26/arch/arm/mach-mx37/serial.h linux-2.6.26-lab126/arch/arm/mach-mx37/serial.h --- linux-2.6.26/arch/arm/mach-mx37/serial.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/serial.h 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,127 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ARCH_ARM_MACH_MX37_SERIAL_H__ +#define __ARCH_ARM_MACH_MX37_SERIAL_H__ + +#include + +/* UART 1 configuration */ +/*! + * This option allows to choose either an interrupt-driven software controlled + * hardware flow control (set this option to 0) or hardware-driven hardware + * flow control (set this option to 1). + */ +/* UART used as wakeup source */ +#define UART1_HW_FLOW 0 +/*! + * This specifies the threshold at which the CTS pin is deasserted by the + * RXFIFO. Set this value in Decimal to anything from 0 to 32 for + * hardware-driven hardware flow control. Read the HW spec while specifying + * this value. When using interrupt-driven software controlled hardware + * flow control set this option to -1. + */ +#define UART1_UCR4_CTSTL 16 +/*! + * This is option to enable (set this option to 1) or disable DMA data transfer + */ +#define UART1_DMA_ENABLE 0 +/*! + * Specify the size of the DMA receive buffer. The minimum buffer size is 512 + * bytes. The buffer size should be a multiple of 256. + */ +#define UART1_DMA_RXBUFSIZE 1024 +/*! + * Specify the MXC UART's Receive Trigger Level. This controls the threshold at + * which a maskable interrupt is generated by the RxFIFO. Set this value in + * Decimal to anything from 0 to 32. Read the HW spec while specifying this + * value. + */ +#define UART1_UFCR_RXTL 16 +/*! + * Specify the MXC UART's Transmit Trigger Level. This controls the threshold at + * which a maskable interrupt is generated by the TxFIFO. Set this value in + * Decimal to anything from 0 to 32. Read the HW spec while specifying this + * value. + */ +#define UART1_UFCR_TXTL 16 +/* UART 2 configuration */ +#define UART2_HW_FLOW 0 +#define UART2_UCR4_CTSTL -1 +#define UART2_DMA_ENABLE 0 +#define UART2_DMA_RXBUFSIZE 512 +#define UART2_UFCR_RXTL 16 +#define UART2_UFCR_TXTL 16 +/* UART 3 configuration */ +#define UART3_HW_FLOW 1 +#define UART3_UCR4_CTSTL 16 +#define UART3_DMA_ENABLE 0 +#define UART3_DMA_RXBUFSIZE 1024 +#define UART3_UFCR_RXTL 16 +#define UART3_UFCR_TXTL 16 +/* + * UART Chip level Configuration that a user may not have to edit. These + * configuration vary depending on how the UART module is integrated with + * the ARM core + */ +/* + * Is the MUXED interrupt output sent to the ARM core + */ +#define INTS_NOTMUXED 0 +#define INTS_MUXED 1 +/* UART 1 configuration */ +/*! + * This define specifies whether the muxed ANDed interrupt line or the + * individual interrupts from the UART port is integrated with the ARM core. + * There exists a define like this for each UART port. Valid values that can + * be used are \b INTS_NOTMUXED or \b INTS_MUXED. + */ +#define UART1_MUX_INTS INTS_MUXED +/*! + * This define specifies the transmitter interrupt number or the interrupt + * number of the ANDed interrupt in case the interrupts are muxed. There exists + * a define like this for each UART port. + */ +#define UART1_INT1 MXC_INT_UART1 +/*! + * This define specifies the receiver interrupt number. If the interrupts of + * the UART are muxed, then we specify here a dummy value -1. There exists a + * define like this for each UART port. + */ +#define UART1_INT2 -1 +/*! + * This specifies the master interrupt number. If the interrupts of the UART + * are muxed, then we specify here a dummy value of -1. There exists a define + * like this for each UART port. + */ +#define UART1_INT3 -1 +/*! + * This specifies if the UART is a shared peripheral. It holds the shared + * peripheral number if it is shared or -1 if it is not shared. There exists + * a define like this for each UART port. + */ +#define UART1_SHARED_PERI -1 +/* UART 2 configuration */ +#define UART2_MUX_INTS INTS_MUXED +#define UART2_INT1 MXC_INT_UART2 +#define UART2_INT2 -1 +#define UART2_INT3 -1 +#define UART2_SHARED_PERI -1 +/* UART 3 configuration */ +#define UART3_MUX_INTS INTS_MUXED +#define UART3_INT1 MXC_INT_UART3 +#define UART3_INT2 -1 +#define UART3_INT3 -1 +#define UART3_SHARED_PERI SPBA_UART3 + +#endif /* __ARCH_ARM_MACH_MX37_SERIAL_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx37/system.c linux-2.6.26-lab126/arch/arm/mach-mx37/system.c --- linux-2.6.26/arch/arm/mach-mx37/system.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/system.c 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,192 @@ +/* + * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "crm_regs.h" + +/*! + * @defgroup MSL_MX37 i.MX37 Machine Specific Layer (MSL) + */ + +/*! + * @file mach-mx37/system.c + * @brief This file contains idle and reset functions. + * + * @ingroup MSL_MX37 + */ + +extern int mxc_jtag_enabled; +extern int low_bus_freq_mode; + +static struct clk *pll1_main; +static struct clk *pll1_sw_clk; +static struct clk *lp_apm_clk; +static struct clk *gpc_dvfs_clk; + +/* set cpu low power mode before WFI instruction */ +void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) +{ + u32 plat_lpc, gpc_pgr, arm_srpgcr, empgcr0, empgcr1, ccm_clpcr; + /* always allow platform to issue a deep sleep mode request */ + plat_lpc = __raw_readl(MXC_ARM1176_PLAT_LPC) & + ~(MXC_ARM1176_PLAT_LPC_DSM); + + ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); + gpc_pgr = __raw_readl(MXC_GPC_PGR) & ~(MXC_GPC_PGR_ARMPG_MASK); + arm_srpgcr = __raw_readl(MXC_SRPGC_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR); + empgcr0 = __raw_readl(MXC_EMPGC0_ARM_EMPGCR) & ~(MXC_EMPGCR_PCR); + empgcr1 = __raw_readl(MXC_EMPGC1_ARM_EMPGCR) & ~(MXC_EMPGCR_PCR); + + switch (mode) { + case WAIT_CLOCKED: + break; + case WAIT_UNCLOCKED: + ccm_clpcr |= (0x1 << MXC_CCM_CLPCR_LPM_OFFSET); + break; + case WAIT_UNCLOCKED_POWER_OFF: + case STOP_POWER_OFF: + plat_lpc |= MXC_ARM1176_PLAT_LPC_DSM; + if (mode == WAIT_UNCLOCKED_POWER_OFF) + ccm_clpcr |= (0x1 << MXC_CCM_CLPCR_LPM_OFFSET); + else { + ccm_clpcr |= (0x2 << MXC_CCM_CLPCR_LPM_OFFSET); + ccm_clpcr |= (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET); + ccm_clpcr |= MXC_CCM_CLPCR_VSTBY; + ccm_clpcr |= MXC_CCM_CLPCR_SBYOS; + } + + gpc_pgr |= (0x1 << MXC_GPC_PGR_ARMPG_OFFSET); + arm_srpgcr |= MXC_SRPGCR_PCR; + empgcr0 |= MXC_EMPGCR_PCR; + empgcr1 |= MXC_EMPGCR_PCR; + + if (tzic_enable_wake(1) != 0) + return; + break; + case STOP_POWER_ON: + ccm_clpcr |= (0x2 << MXC_CCM_CLPCR_LPM_OFFSET); + break; + default: + printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode); + return; + } + + __raw_writel(plat_lpc, MXC_ARM1176_PLAT_LPC); + __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); + __raw_writel(gpc_pgr, MXC_GPC_PGR); + __raw_writel(arm_srpgcr, MXC_SRPGC_ARM_SRPGCR); + if ((mxc_cpu_is_rev(CHIP_REV_1_0)) != 1) + __raw_writel(empgcr0, MXC_EMPGC0_ARM_EMPGCR); + + __raw_writel(empgcr1, MXC_EMPGC1_ARM_EMPGCR); + + flush_cache_all(); + + if (gpc_dvfs_clk == NULL) + gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk"); + + /* gpc clock is needed for SRPG */ + clk_enable(gpc_dvfs_clk); + if (low_bus_freq_mode) { + if (pll1_sw_clk == NULL) + pll1_sw_clk = clk_get(NULL, "pll1_sw_clk"); + if (lp_apm_clk == NULL) + lp_apm_clk = clk_get(NULL, "lp_apm"); + if (pll1_main == NULL) + pll1_main = clk_get(NULL, "pll1_main_clk"); + + /* Move the ARM to run off the 24MHz clock. Shutdown the PLL1 */ + /* Change the source of pll1_sw_clk to be the step_clk */ + clk_set_parent(pll1_sw_clk, lp_apm_clk); + } +} + +void mxc_pg_enable(struct platform_device *pdev) +{ + if (pdev == NULL) + return; + + if (strcmp(pdev->name, "mxc_ipu") == 0) { + __raw_writel(MXC_PGCR_PCR, MXC_PGC_IPU_PGCR); + __raw_writel(MXC_PGSR_PSR, MXC_PGC_IPU_PGSR); + } else if (strcmp(pdev->name, "mxc_vpu") == 0) { + __raw_writel(MXC_PGCR_PCR, MXC_PGC_VPU_PGCR); + __raw_writel(MXC_PGSR_PSR, MXC_PGC_VPU_PGSR); + } +} + +EXPORT_SYMBOL(mxc_pg_enable); + +void mxc_pg_disable(struct platform_device *pdev) +{ + if (pdev == NULL) + return; + + if (strcmp(pdev->name, "mxc_ipu") == 0) { + __raw_writel(0x0, MXC_PGC_IPU_PGCR); + if (__raw_readl(MXC_PGC_IPU_PGSR) & MXC_PGSR_PSR) + dev_dbg(&pdev->dev, "power gating successful\n"); + __raw_writel(MXC_PGSR_PSR, MXC_PGC_IPU_PGSR); + } else if (strcmp(pdev->name, "mxc_vpu") == 0) { + __raw_writel(0x0, MXC_PGC_VPU_PGCR); + if (__raw_readl(MXC_PGC_VPU_PGSR) & MXC_PGSR_PSR) + dev_dbg(&pdev->dev, "power gating successful\n"); + __raw_writel(MXC_PGSR_PSR, MXC_PGC_VPU_PGSR); + } +} + +EXPORT_SYMBOL(mxc_pg_disable); + +/* To change the idle power mode, need to set arch_idle_mode to a different + * power mode as in enum mxc_cpu_pwr_mode. + * May allow dynamically changing the idle mode. + */ +static int arch_idle_mode = WAIT_UNCLOCKED_POWER_OFF; + +/*! + * This function puts the CPU into idle mode. It is called by default_idle() + * in process.c file. + */ +void arch_idle(void) +{ + if (likely(!mxc_jtag_enabled)) { + mxc_cpu_lp_set(arch_idle_mode); + cpu_do_idle(); + /* gpc clock is needed for SRPG */ + clk_disable(gpc_dvfs_clk); + if (low_bus_freq_mode) { + /* Move ARM back to PLL from step clk. */ + /* Move the PLL1 back to the pll1_main_clk */ + clk_set_parent(pll1_sw_clk, pll1_main); + } + } +} + +/* + * This function resets the system. It is called by machine_restart(). + * + * @param mode indicates different kinds of resets + */ +void arch_reset(char mode) +{ + /* Assert SRS signal */ + mxc_wd_reset(); +} diff -urN linux-2.6.26/arch/arm/mach-mx37/usb.h linux-2.6.26-lab126/arch/arm/mach-mx37/usb.h --- linux-2.6.26/arch/arm/mach-mx37/usb.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/usb.h 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,112 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +extern int usbotg_init(struct platform_device *pdev); +extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata); +extern int gpio_usbotg_hs_active(void); +extern void gpio_usbotg_hs_inactive(void); +extern struct platform_device *host_pdev_register(struct resource *res, + int n_res, struct fsl_usb2_platform_data *config); + +extern int gpio_usbotg_utmi_active(void); +extern void gpio_usbotg_utmi_inactive(void); +static int usbotg_init_ext(struct platform_device *pdev); +static void usbotg_uninit_ext(struct fsl_usb2_platform_data *pdata); + +/* + * Determine which platform_data struct to use for the DR controller, + * based on which transceiver is configured. + * PDATA is a pointer to it. + */ +#if defined(CONFIG_ISP1301_MXC) +static struct fsl_usb2_platform_data __maybe_unused dr_1301_config; +#define PDATA (&dr_1301_config) +#elif defined(CONFIG_MC13783_MXC) +static struct fsl_usb2_platform_data __maybe_unused dr_13783_config; +#define PDATA (&dr_13783_config) +#elif defined(CONFIG_UTMI_MXC) +static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config; +#define PDATA (&dr_utmi_config) +#endif + + +/* + * Used to set pdata->operating_mode before registering the platform_device. + * If OTG is configured, the controller operates in OTG mode, + * otherwise it's either host or device. + */ +#ifdef CONFIG_USB_OTG +#define DR_UDC_MODE FSL_USB2_DR_OTG +#define DR_HOST_MODE FSL_USB2_DR_OTG +#else +#define DR_UDC_MODE FSL_USB2_DR_DEVICE +#define DR_HOST_MODE FSL_USB2_DR_HOST +#endif + + +#ifdef CONFIG_USB_EHCI_ARC_OTG +static inline void dr_register_host(struct resource *r, int rs) +{ + PDATA->operating_mode = DR_HOST_MODE; + host_pdev_register(r, rs, PDATA); +} +#else +static inline void dr_register_host(struct resource *r, int rs) +{ +} +#endif + +#ifdef CONFIG_USB_GADGET_ARC +static struct platform_device dr_udc_device; + +static inline void dr_register_udc(void) +{ + PDATA->operating_mode = DR_UDC_MODE; + dr_udc_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_udc_device)) + printk(KERN_ERR "usb: can't register DR gadget\n"); + else + printk(KERN_INFO "usb: DR gadget (%s) registered\n", + PDATA->transceiver); +} +#else +static inline void dr_register_udc(void) +{ +} +#endif + +#ifdef CONFIG_USB_OTG +static struct platform_device dr_otg_device; + +/* + * set the proper operating_mode and + * platform_data pointer, then register the + * device. + */ +static inline void dr_register_otg(void) +{ + PDATA->operating_mode = FSL_USB2_DR_OTG; + dr_otg_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_otg_device)) + printk(KERN_ERR "usb: can't register otg device\n"); + else + printk(KERN_INFO "usb: DR OTG registered\n"); +} +#else +static inline void dr_register_otg(void) +{ +} +#endif diff -urN linux-2.6.26/arch/arm/mach-mx37/usb_dr.c linux-2.6.26-lab126/arch/arm/mach-mx37/usb_dr.c --- linux-2.6.26/arch/arm/mach-mx37/usb_dr.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx37/usb_dr.c 2010-08-10 04:14:15.000000000 -0400 @@ -0,0 +1,120 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include "usb.h" + +/* + * platform data structs + * - Which one to use is determined by CONFIG options in usb.h + * - operating_mode plugged at run time + */ +static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = { + .name = "DR", + .platform_init = usbotg_init_ext, + .platform_uninit = usbotg_uninit_ext, + .phy_mode = FSL_USB2_PHY_UTMI_WIDE, + .power_budget = 500, /* 500 mA max power */ + .gpio_usb_active = gpio_usbotg_hs_active, + .gpio_usb_inactive = gpio_usbotg_hs_inactive, + .transceiver = "utmi", +}; + + +/* + * resources + */ +static struct resource otg_resources[] = { + [0] = { + .start = (u32)(OTG_BASE_ADDR), + .end = (u32)(OTG_BASE_ADDR + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_USB_OTG, + .flags = IORESOURCE_IRQ, + }, +}; + + +static u64 dr_udc_dmamask = ~(u32) 0; +static void dr_udc_release(struct device *dev) +{ +} + +/* + * platform device structs + * dev.platform_data field plugged at run time + */ +static struct platform_device dr_udc_device = { + .name = "fsl-usb2-udc", + .id = -1, + .dev = { + .release = dr_udc_release, + .dma_mask = &dr_udc_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), +}; + +/* Notes: configure USB clock*/ +static int usbotg_init_ext(struct platform_device *pdev) +{ + struct clk *usb_clk, *usboh2_clk; + int ret; + + usboh2_clk = clk_get(NULL, "usboh2_clk"); + clk_enable(usboh2_clk); + + usb_clk = clk_get(NULL, "usb_phy_clk"); + clk_enable(usb_clk); + clk_put(usb_clk); + + ret = usbotg_init(pdev); + + /* this clock is no use after set portsc PTS bit */ + clk_disable(usboh2_clk); + clk_put(usboh2_clk); + + return ret; +} + +static void usbotg_uninit_ext(struct fsl_usb2_platform_data *pdata) +{ + struct clk *usb_clk; + + usb_clk = clk_get(NULL, "usb_phy_clk"); + clk_disable(usb_clk); + clk_put(usb_clk); + + usbotg_uninit(pdata); +} + +static int __init usb_dr_init(void) +{ + pr_debug("%s: \n", __func__); + + /* dr_register_otg(); */ + dr_register_host(otg_resources, ARRAY_SIZE(otg_resources)); + dr_register_udc(); + + return 0; +} + +module_init(usb_dr_init); diff -urN linux-2.6.26/arch/arm/mach-mx51/Kconfig linux-2.6.26-lab126/arch/arm/mach-mx51/Kconfig --- linux-2.6.26/arch/arm/mach-mx51/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/Kconfig 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,85 @@ +menu "MX51 Options" + depends on ARCH_MX51 + +config MX51_OPTIONS + bool + default y + select CPU_V7 + select USB_ARCH_HAS_EHCI + select MXC_TZIC + +config MACH_MX51_3DS + bool "Support MX51 3-Stack platforms" + default y + help + Include support for MX51 3-Stack platform. This includes specific + configurations for the board and its peripherals. + +config MXC_SDMA_API + bool "Use SDMA API" + default y + help + This selects the Freescale MXC SDMA API. + If unsure, say N. + +config ARCH_MXC_HAS_NFC_V3 + bool "MXC NFC Hardware Version 3" + depends on ARCH_MX51 + default y + help + This selects the Freescale MXC Nand Flash Controller Hardware Version 3 + If unsure, say N. + +config ARCH_MXC_HAS_NFC_V3_2 + bool "MXC NFC Hardware Version 3.2" + depends on ARCH_MXC_HAS_NFC_V3 + default y + help + This selects the Freescale MXC Nand Flash Controller Hardware Version 3.1 + If unsure, say N. + +menu "SDMA options" + depends on MXC_SDMA_API + +config SDMA_IRAM + bool "Use Internal RAM for SDMA transfer" + default n + help + Support Internal RAM as SDMA buffer or control structures + +config SDMA_IRAM_SIZE + hex "Reserved bytes of IRAM for SDMA (0x800-0x1000)" + range 0x800 0x1000 + depends on SDMA_IRAM + default "0x1000" + help + Set the size of IRAM for SDMA. It must be a multiple of 512bytes. +endmenu + +menu "Device options" + +config I2C_MXC_SELECT1 + bool "Enable I2C1 module" + default y + depends on I2C_MXC + help + Enable MX51 I2C1 module. + +config I2C_MXC_SELECT2 + bool "Enable I2C2 module" + default n + depends on I2C_MXC + help + Enable MX51 I2C2 module. + +config I2C_MXC_SELECT3 + bool "Enable I2C3 module" + default n + depends on I2C_MXC + help + Enable MX51 I2C3 module. + +endmenu + +endmenu + diff -urN linux-2.6.26/arch/arm/mach-mx51/Makefile linux-2.6.26-lab126/arch/arm/mach-mx51/Makefile --- linux-2.6.26/arch/arm/mach-mx51/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/Makefile 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,19 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. + + +obj-y := system.o iomux.o cpu.o mm.o clock.o devices.o serial.o dma.o lpmodes.o pm.o + +obj-$(CONFIG_CPU_V7) += wfi.o suspend.o + +obj-$(CONFIG_MACH_MX51_3DS) += mx51_3stack.o mx51_3stack_gpio.o + +obj-$(CONFIG_USB_EHCI_ARC_H1) += usb_h1.o + +ifneq ($(strip $(CONFIG_USB_GADGET_ARC) $(CONFIG_USB_EHCI_ARC_OTG)),) + obj-y += usb_dr.o +endif + diff -urN linux-2.6.26/arch/arm/mach-mx51/Makefile.boot linux-2.6.26-lab126/arch/arm/mach-mx51/Makefile.boot --- linux-2.6.26/arch/arm/mach-mx51/Makefile.boot 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/Makefile.boot 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,3 @@ + zreladdr-y := 0x90008000 +params_phys-y := 0x90000100 +initrd_phys-y := 0x90800000 diff -urN linux-2.6.26/arch/arm/mach-mx51/board-mx51_3stack.h linux-2.6.26-lab126/arch/arm/mach-mx51/board-mx51_3stack.h --- linux-2.6.26/arch/arm/mach-mx51/board-mx51_3stack.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/board-mx51_3stack.h 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,128 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX51_3STACK_H__ +#define __ASM_ARCH_MXC_BOARD_MX51_3STACK_H__ + +/*! + * @defgroup BRDCFG_MX51 Board Configuration Options + * @ingroup MSL_MX51 + */ + +/*! + * @file mach-mx51/board-mx51_3stack.h + * + * @brief This file contains all the board level configuration options. + * + * It currently hold the options defined for MX51 3Stack Platform. + * + * @ingroup BRDCFG_MX51 + */ + +/* + * Include Files + */ +#include + +/*! + * @name MXC UART board level configurations + */ +/*! @{ */ +/*! + * Specifies if the Irda transmit path is inverting + */ +#define MXC_IRDA_TX_INV 0 +/*! + * Specifies if the Irda receive path is inverting + */ +#define MXC_IRDA_RX_INV 0 + +/* UART 1 configuration */ +/*! + * This define specifies if the UART port is configured to be in DTE or + * DCE mode. There exists a define like this for each UART port. Valid + * values that can be used are \b MODE_DTE or \b MODE_DCE. + */ +#define UART1_MODE MODE_DCE +/*! + * This define specifies if the UART is to be used for IRDA. There exists a + * define like this for each UART port. Valid values that can be used are + * \b IRDA or \b NO_IRDA. + */ +#define UART1_IR NO_IRDA +/*! + * This define is used to enable or disable a particular UART port. If + * disabled, the UART will not be registered in the file system and the user + * will not be able to access it. There exists a define like this for each UART + * port. Specify a value of 1 to enable the UART and 0 to disable it. + */ +#define UART1_ENABLED 1 +/*! @} */ +/* UART 2 configuration */ +#define UART2_MODE MODE_DCE +#define UART2_IR NO_IRDA +#define UART2_ENABLED 1 +/* UART 3 configuration */ +#define UART3_MODE MODE_DTE +#define UART3_IR NO_IRDA +#define UART3_ENABLED 1 + +#define MXC_LL_UART_PADDR UART1_BASE_ADDR +#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) + +#define DEBUG_BOARD_BASE_ADDRESS(n) (n) +/* LAN9217 ethernet base address */ +#define LAN9217_BASE_ADDR(n) (DEBUG_BOARD_BASE_ADDRESS(n)) +/* External UART */ +#define UARTA_BASE_ADDR(n) (DEBUG_BOARD_BASE_ADDRESS(n) + 0x8000) +#define UARTB_BASE_ADDR(n) (DEBUG_BOARD_BASE_ADDRESS(n) + 0x10000) + +#define BOARD_IO_ADDR(n) (DEBUG_BOARD_BASE_ADDRESS(n) + 0x20000) +/* LED switchs */ +#define LED_SWITCH_REG 0x00 +/* buttons */ +#define SWITCH_BUTTONS_REG 0x08 +/* status, interrupt */ +#define INTR_STATUS_REG 0x10 +#define INTR_MASK_REG 0x38 +#define INTR_RESET_REG 0x20 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER1_REG 0x40 +#define MAGIC_NUMBER2_REG 0x48 +/* CPLD code version */ +#define CPLD_CODE_VER_REG 0x50 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER3_REG 0x58 +/* module reset register*/ +#define MODULE_RESET_REG 0x60 +/* CPU ID and Personality ID */ +#define MCU_BOARD_ID_REG 0x68 + +/* interrupts like external uart , external ethernet etc*/ +#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX51_PIN_GPIO1_6) + +#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0) +#define EXPIO_INT_XUART_A (MXC_EXP_IO_BASE + 1) +#define EXPIO_INT_XUART_B (MXC_EXP_IO_BASE + 2) +#define EXPIO_INT_BUTTON_A (MXC_EXP_IO_BASE + 3) +#define EXPIO_INT_BUTTON_B (MXC_EXP_IO_BASE + 4) + +/*! This is System IRQ used by LAN9217 */ +#define LAN9217_IRQ EXPIO_INT_ENET + +extern unsigned int sdhc_get_card_det_status(struct device *dev); +extern int sdhc_write_protect(struct device *dev); +extern int sdhc_init_card_det(int id); +extern int headphone_det_status(void); + +#endif /* __ASM_ARCH_MXC_BOARD_MX51_3STACK_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx51/clock.c linux-2.6.26-lab126/arch/arm/mach-mx51/clock.c --- linux-2.6.26/arch/arm/mach-mx51/clock.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/clock.c 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,3123 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "crm_regs.h" + +static unsigned long pll_base[] = { + (unsigned long)MXC_DPLL1_BASE, + (unsigned long)MXC_DPLL2_BASE, + (unsigned long)MXC_DPLL3_BASE, +}; + +static struct clk pll1_main_clk; +static struct clk pll1_sw_clk; +static struct clk pll2_sw_clk; +static struct clk pll3_sw_clk; +static struct clk lp_apm_clk; +static struct clk tve_clk; +static struct clk emi_fast_clk; +static struct clk emi_slow_clk; +static struct clk emi_intr_clk; +static struct clk ddr_clk; +static struct clk ipu_clk[]; +static struct clk axi_a_clk; +static struct clk axi_b_clk; +static struct clk ddr_hf_clk; +static int cpu_curr_wp; +static struct cpu_wp *cpu_wp_tbl; + +int cpu_wp_nr; + +extern int mxc_jtag_enabled; + +static int cpu_clk_set_wp(int wp); +extern void propagate_rate(struct clk *tclk); +extern void board_ref_clk_rate(unsigned long *ckil, unsigned long *osc, + unsigned long *ckih, unsigned long *ckih2); + +static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post) +{ + u32 min_pre, temp_pre, old_err, err; + + if (div >= 512) { + *pre = 8; + *post = 64; + } else if (div >= 8) { + min_pre = (div - 1) / 64 + 1; + old_err = 8; + for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) { + err = div % temp_pre; + if (err == 0) { + *pre = temp_pre; + break; + } + err = temp_pre - err; + if (err < old_err) { + old_err = err; + *pre = temp_pre; + } + } + *post = (div + *pre - 1) / *pre; + } else if (div < 8) { + *pre = div; + *post = 1; + } +} + +static int _clk_enable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + return 0; +} + +static void _clk_disable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); +} + +static void _clk_disable_inwait(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); +} + +/* + * For the 4-to-1 muxed input clock + */ +static inline u32 _get_mux(struct clk *parent, struct clk *m0, + struct clk *m1, struct clk *m2, struct clk *m3) +{ + if (parent == m0) + return 0; + else if (parent == m1) + return 1; + else if (parent == m2) + return 2; + else if (parent == m3) + return 3; + else + BUG(); + + return 0; +} + +/* + * For the ddr muxed input clock + */ +static inline u32 _get_mux_ddr(struct clk *parent, struct clk *m0, + struct clk *m1, struct clk *m2, struct clk *m3, struct clk *m4) +{ + if (parent == m0) + return 0; + else if (parent == m1) + return 1; + else if (parent == m2) + return 2; + else if (parent == m3) + return 3; + else if (parent == m4) + return 4; + else + BUG(); + + return 0; +} + +static inline unsigned long _get_pll_base(struct clk *pll) +{ + if (pll == &pll1_main_clk) + return pll_base[0]; + else if (pll == &pll2_sw_clk) + return pll_base[1]; + else if (pll == &pll3_sw_clk) + return pll_base[2]; + else + BUG(); + + return 0; +} + +static struct clk ckih_clk = { + .name = "ckih", + .flags = RATE_PROPAGATES, +}; + +static struct clk ckih2_clk = { + .name = "ckih2", + .flags = RATE_PROPAGATES, +}; + +static struct clk osc_clk = { + .name = "osc", + .flags = RATE_PROPAGATES, +}; + +static struct clk ckil_clk = { + .name = "ckil", + .flags = RATE_PROPAGATES, +}; + +static void _fpm_recalc(struct clk *clk) +{ + clk->rate = ckil_clk.rate * 512; + if ((__raw_readl(MXC_CCM_CCR) & MXC_CCM_CCR_FPM_MULT_MASK) != 0) + clk->rate *= 2; + +} + +static int _fpm_enable(struct clk *clk) +{ + u32 reg = __raw_readl(MXC_CCM_CCR); + reg |= MXC_CCM_CCR_FPM_EN; + __raw_writel(reg, MXC_CCM_CCR); + return 0; +} + +static void _fpm_disable(struct clk *clk) +{ + u32 reg = __raw_readl(MXC_CCM_CCR); + reg &= ~MXC_CCM_CCR_FPM_EN; + __raw_writel(reg, MXC_CCM_CCR); +} + +static struct clk fpm_clk = { + .name = "fpm_clk", + .parent = &ckil_clk, + .recalc = _fpm_recalc, + .enable = _fpm_enable, + .disable = _fpm_disable, + .flags = RATE_PROPAGATES, +}; + +static void _fpm_div2_recalc(struct clk *clk) +{ + clk->rate = clk->parent->rate / 2; +} + +static struct clk fpm_div2_clk = { + .name = "fpm_div2_clk", + .parent = &fpm_clk, + .recalc = _fpm_div2_recalc, + .flags = RATE_PROPAGATES, +}; + +static void _clk_pll_recalc(struct clk *clk) +{ + long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; + unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; + unsigned long pllbase; + s64 temp; + + pllbase = _get_pll_base(clk); + + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; + dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; + + if (pll_hfsm == 0) { + dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); + } else { + dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP); + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD); + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN); + } + pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; + mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; + mfi = (mfi <= 5) ? 5 : mfi; + mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; + mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; + /* Sign extend to 32-bits */ + if (mfn >= 0x04000000) { + mfn |= 0xFC000000; + mfn_abs = -mfn; + } + + ref_clk = 2 * clk->parent->rate; + if (dbl != 0) + ref_clk *= 2; + + ref_clk /= (pdf + 1); + temp = (u64) ref_clk * mfn_abs; + do_div(temp, mfd + 1); + if (mfn < 0) + temp = -temp; + temp = (ref_clk * mfi) + temp; + + clk->rate = temp; +} + +static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 pllbase; + + long mfi, pdf, mfn, mfd = 999999; + s64 temp64; + unsigned long quad_parent_rate; + unsigned long pll_hfsm, dp_ctl; + + pllbase = _get_pll_base(clk); + + quad_parent_rate = 4*clk->parent->rate; + pdf = mfi = -1; + while (++pdf < 16 && mfi < 5) + mfi = rate * (pdf+1) / quad_parent_rate; + if (mfi > 15) + return -1; + pdf--; + + temp64 = rate*(pdf+1) - quad_parent_rate*mfi; + do_div(temp64, quad_parent_rate/1000000); + mfn = (long)temp64; + + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); + /* use dpdck0_2 */ + __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; + if (pll_hfsm == 0) { + reg = mfi<<4 | pdf; + __raw_writel(reg, pllbase + MXC_PLL_DP_OP); + __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD); + __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN); + } else { + reg = mfi<<4 | pdf; + __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP); + __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD); + __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN); + } + + return 0; +} + +static int _clk_pll_enable(struct clk *clk) +{ + u32 reg; + u32 pllbase; + + pllbase = _get_pll_base(clk); + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); + + /* Wait for lock */ + while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF)) ; + + return 0; +} + +static void _clk_pll_disable(struct clk *clk) +{ + u32 reg; + u32 pllbase; + + pllbase = _get_pll_base(clk); + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); +} + +static struct clk pll1_main_clk = { + .name = "pll1_main_clk", + .parent = &osc_clk, + .recalc = _clk_pll_recalc, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .flags = RATE_PROPAGATES, +}; + +static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CCSR); + + if (parent == &pll1_main_clk) { + reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + } else { + if (parent == &lp_apm_clk) { + reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + reg = __raw_readl(MXC_CCM_CCSR); + mux = _get_mux(parent, &lp_apm_clk, NULL, &pll2_sw_clk, + &pll3_sw_clk); + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | + (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET); + } else { + mux = _get_mux(parent, &lp_apm_clk, NULL, &pll2_sw_clk, + &pll3_sw_clk); + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | + (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CCSR); + reg = __raw_readl(MXC_CCM_CCSR); + reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + + } + } + __raw_writel(reg, MXC_CCM_CCSR); + return 0; +} + +static void _clk_pll1_sw_recalc(struct clk *clk) +{ + u32 reg, div; + div = 1; + reg = __raw_readl(MXC_CCM_CCSR); + + if (clk->parent == &pll2_sw_clk) { + div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >> + MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1; + } else if (clk->parent == &pll3_sw_clk) { + div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >> + MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1; + } + clk->rate = clk->parent->rate / div; +} + +/* pll1 switch clock */ +static struct clk pll1_sw_clk = { + .name = "pll1_sw_clk", + .parent = &pll1_main_clk, + .set_parent = _clk_pll1_sw_set_parent, + .recalc = _clk_pll1_sw_recalc, + .flags = RATE_PROPAGATES, +}; + +/* same as pll2_main_clk. These two clocks should always be the same */ +static struct clk pll2_sw_clk = { + .name = "pll2", + .parent = &osc_clk, + .recalc = _clk_pll_recalc, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .flags = RATE_PROPAGATES, +}; + +/* same as pll3_main_clk. These two clocks should always be the same */ +static struct clk pll3_sw_clk = { + .name = "pll3", + .parent = &osc_clk, + .set_rate = _clk_pll_set_rate, + .recalc = _clk_pll_recalc, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .flags = RATE_PROPAGATES, +}; + +static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + if (parent == &osc_clk) + reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL; + else if (parent == &fpm_clk) + reg = __raw_readl(MXC_CCM_CCSR) | MXC_CCM_CCSR_LP_APM_SEL; + else + return -EINVAL; + + __raw_writel(reg, MXC_CCM_CCSR); + + return 0; +} + +static struct clk lp_apm_clk = { + .name = "lp_apm", + .parent = &osc_clk, + .set_parent = _clk_lp_apm_set_parent, + .flags = RATE_PROPAGATES, +}; + +static void _clk_arm_recalc(struct clk *clk) +{ + u32 cacrr, div; + + cacrr = __raw_readl(MXC_CCM_CACRR); + div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1; + clk->rate = clk->parent->rate / div; +} + +static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate) +{ + u32 i; + for (i = 0; i < cpu_wp_nr; i++) { + if (rate == cpu_wp_tbl[i].cpu_rate) + break; + } + if (i > cpu_wp_nr) + return -EINVAL; + cpu_clk_set_wp(i); + + return 0; +} + +static unsigned long _clk_cpu_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 i; + u32 wp; + + for (i = 0; i < cpu_wp_nr; i++) { + if (rate == cpu_wp_tbl[i].cpu_rate) + break; + } + + if (i > cpu_wp_nr) + wp = 0; + + return cpu_wp_tbl[wp].cpu_rate; +} + + +static struct clk cpu_clk = { + .name = "cpu_clk", + .parent = &pll1_sw_clk, + .recalc = _clk_arm_recalc, + .set_rate = _clk_cpu_set_rate, + .round_rate = _clk_cpu_round_rate, +}; + +static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL); + + reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CBCMR); + + return 0; +} + +static struct clk periph_apm_clk = { + .name = "periph_apm_clk", + .parent = &pll1_sw_clk, + .set_parent = _clk_periph_apm_set_parent, + .flags = RATE_PROPAGATES, +}; + +/* TODO: Need to sync with GPC to determine if DVFS is in place so that + * the DVFS_PODF divider can be applied in CDCR register. + */ +static void _clk_main_bus_recalc(struct clk *clk) +{ + clk->rate = clk->parent->rate; +} + +static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + if (emi_fast_clk.usecount == 0) + emi_fast_clk.enable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.enable(&emi_slow_clk); + if (emi_intr_clk.usecount == 0) + emi_intr_clk.enable(&emi_intr_clk); + + if (parent == &pll2_sw_clk) { + reg = __raw_readl(MXC_CCM_CBCDR) & + ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; + } else if (parent == &periph_apm_clk) { + reg = __raw_readl(MXC_CCM_CBCDR) | MXC_CCM_CBCDR_PERIPH_CLK_SEL; + } else { + return -EINVAL; + } + __raw_writel(reg, MXC_CCM_CBCDR); + + if (emi_fast_clk.usecount == 0) + emi_fast_clk.disable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.disable(&emi_slow_clk); + if (emi_intr_clk.usecount == 0) + emi_intr_clk.disable(&emi_intr_clk); + + return 0; +} + +static struct clk main_bus_clk = { + .name = "main_bus_clk", + .parent = &pll2_sw_clk, + .set_parent = _clk_main_bus_set_parent, + .recalc = _clk_main_bus_recalc, + .flags = RATE_PROPAGATES, +}; + +static void _clk_axi_a_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_AXI_A_PODF_MASK) >> + MXC_CCM_CBCDR_AXI_A_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + +static struct clk axi_a_clk = { + .name = "axi_a_clk", + .parent = &main_bus_clk, + .recalc = _clk_axi_a_recalc, + .flags = RATE_PROPAGATES, +}; + +static void _clk_ddr_hf_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >> + MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + +static struct clk ddr_hf_clk = { + .name = "ddr_hf_clk", + .parent = &pll1_sw_clk, + .recalc = _clk_ddr_hf_recalc, + .flags = RATE_PROPAGATES, +}; + +static void _clk_axi_b_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_AXI_B_PODF_MASK) >> + MXC_CCM_CBCDR_AXI_B_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + +static struct clk axi_b_clk = { + .name = "axi_b_clk", + .parent = &main_bus_clk, + .recalc = _clk_axi_b_recalc, + .flags = RATE_PROPAGATES, +}; + +static void _clk_ahb_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >> + MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + +static struct clk ahb_clk = { + .name = "ahb_clk", + .parent = &main_bus_clk, + .recalc = _clk_ahb_recalc, + .flags = RATE_PROPAGATES, +}; + +static int _clk_max_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + + /* Handshake with MAX when LPM is entered. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + + return 0; +} + + +static void _clk_max_disable(struct clk *clk) +{ + u32 reg; + + _clk_disable_inwait(clk); + + /* No Handshake with MAX when LPM is entered as its disabled. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); +} + + +static struct clk ahb_max_clk = { + .name = "max_clk", + .parent = &ahb_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGR0_CG14_OFFSET, + .enable = _clk_max_enable, + .disable = _clk_max_disable, +}; + +static int _clk_emi_slow_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CBCDR); + if (parent == &ahb_clk) { + reg |= MXC_CCM_CBCDR_EMI_CLK_SEL; + } else if (parent == &main_bus_clk) { + reg &= ~MXC_CCM_CBCDR_EMI_CLK_SEL; + } else { + BUG(); + } + __raw_writel(reg, MXC_CCM_CBCDR); + + return 0; +} + +static void _clk_emi_slow_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >> + MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + +static int _clk_emi_slow_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + + div = clk->parent->rate / rate; + if (div == 0) + div++; + if (((clk->parent->rate / div) != rate) || (div > 8)) + return -EINVAL; + + if (emi_fast_clk.usecount == 0) + emi_fast_clk.enable(&emi_fast_clk); + if (emi_intr_clk.usecount == 0) + emi_intr_clk.enable(&emi_intr_clk); + + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_EMI_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_EMI_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + + clk->rate = rate; + + if (emi_fast_clk.usecount == 0) + emi_fast_clk.disable(&emi_fast_clk); + if (emi_intr_clk.usecount == 0) + emi_intr_clk.disable(&emi_intr_clk); + + return 0; +} + +static unsigned long _clk_emi_slow_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return clk->parent->rate / div; +} + + +static struct clk emi_slow_clk = { + .name = "emi_slow_clk", + .parent = &main_bus_clk, + .set_parent = _clk_emi_slow_set_parent, + .recalc = _clk_emi_slow_recalc, + .set_rate = _clk_emi_slow_set_rate, + .round_rate = _clk_emi_slow_round_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG8_OFFSET, + .disable = _clk_disable_inwait, + .flags = RATE_PROPAGATES, +}; + +static struct clk ahbmux1_clk = { + .name = "ahbmux1_clk", + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGR0_CG8_OFFSET, + .disable = _clk_disable_inwait, +}; + +static struct clk ahbmux2_clk = { + .name = "ahbmux2_clk", + .id = 0, + .parent = &ahb_clk, + .secondary = &emi_intr_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGR0_CG9_OFFSET, + .disable = _clk_disable_inwait, +}; + + +static struct clk emi_fast_clk = { + .name = "emi_fast_clk", + .parent = &ddr_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG7_OFFSET, + .disable = _clk_disable_inwait, +}; + +static struct clk emi_intr_clk = { + .name = "emi_intr_clk", + .parent = &ahb_clk, + .secondary = &ahbmux2_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG9_OFFSET, + .disable = _clk_disable_inwait, +}; + +static void _clk_ipg_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >> + MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + +static struct clk ipg_clk = { + .name = "ipg_clk", + .parent = &ahb_clk, + .recalc = _clk_ipg_recalc, + .flags = RATE_PROPAGATES, +}; + +static void _clk_ipg_per_recalc(struct clk *clk) +{ + u32 reg, prediv1, prediv2, podf; + + if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) { + /* the main_bus_clk is the one before the DVFS engine */ + reg = __raw_readl(MXC_CCM_CBCDR); + prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1; + prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1; + podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> + MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / (prediv1 * prediv2 * podf); + } else if (clk->parent == &ipg_clk) { + clk->rate = ipg_clk.rate; + } else { + BUG(); + } +} + +static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CBCMR); + mux = _get_mux(parent, &main_bus_clk, &lp_apm_clk, &ipg_clk, NULL); + if (mux == 2) { + reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; + } else { + reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; + if (mux == 0) + reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; + else + reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; + } + __raw_writel(reg, MXC_CCM_CBCMR); + + return 0; +} + +static struct clk ipg_perclk = { + .name = "ipg_perclk", + .parent = &lp_apm_clk, + .recalc = _clk_ipg_per_recalc, + .set_parent = _clk_ipg_per_set_parent, + .flags = RATE_PROPAGATES, +}; + +static struct clk aips_tz1_clk = { + .name = "aips_tz1_clk", + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGR0_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, +}; + +static struct clk aips_tz2_clk = { + .name = "aips_tz2_clk", + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGR0_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, +}; + +static struct clk gpc_dvfs_clk = { + .name = "gpc_dvfs_clk", + .parent = &aips_tz1_clk, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static int _clk_sdma_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + + /* Handshake with SDMA when LPM is entered. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg &= ~MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + + return 0; +} + +static void _clk_sdma_disable(struct clk *clk) +{ + u32 reg; + + _clk_disable(clk); + /* No handshake with SDMA as its not enabled. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); +} + + +static struct clk sdma_clk[] = { + { + .name = "sdma_ahb_clk", + .parent = &ahb_clk, + .secondary = &emi_fast_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG15_OFFSET, + .enable = _clk_sdma_enable, + .disable = _clk_sdma_disable, + }, + { + .name = "sdma_ipg_clk", + .parent = &ipg_clk, +#ifdef CONFIG_SDMA_IRAM + .secondary = &emi_intr_clk, +#endif + }, +}; + +static int _clk_ipu_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + /* Handshake with IPU when certain clock rates are changed. */ + reg = __raw_readl(MXC_CCM_CCDR); + reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; + __raw_writel(reg, MXC_CCM_CCDR); + + /* Handshake with IPU when LPM is entered as its enabled. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + + + return 0; +} + +static void _clk_ipu_disable(struct clk *clk) +{ + u32 reg; + _clk_disable(clk); + + /* No handshake with IPU whe dividers are changed + * as its not enabled. */ + reg = __raw_readl(MXC_CCM_CCDR); + reg |= MXC_CCM_CCDR_IPU_HS_MASK; + __raw_writel(reg, MXC_CCM_CCDR); + + /* No handshake with IPU when LPM is entered as its not enabled. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + +} + + +static struct clk ipu_clk[] = { + { + .name = "ipu_clk", + .parent = &ahb_clk, + .secondary = &ipu_clk[1], + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG5_OFFSET, + .enable = _clk_ipu_enable, + .disable = _clk_ipu_disable, + }, + { + .name = "ipu_sec_clk", + .parent = &emi_fast_clk, + .secondary = &ahbmux1_clk, + } +}; + +static int _clk_ipu_di_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR2); + reg &= ~MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(clk->id); + if (parent == &pll3_sw_clk) + ; + else if (parent == &osc_clk) + reg |= 1 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); + else if (parent == &ckih_clk) + reg |= 2 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); + else if (parent == &tve_clk) + reg |= 3 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); + else /* Assume any other clock is external clock pin */ + reg |= 4 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static void _clk_ipu_di_recalc(struct clk *clk) +{ + u32 reg, div, mux; + + reg = __raw_readl(MXC_CCM_CSCMR2); + mux = (reg & MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(clk->id)) >> + MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); + if (mux == 0) { + reg = __raw_readl(MXC_CCM_CDCDR) & + MXC_CCM_CDCDR_DI_CLK_PRED_MASK; + div = (reg >> MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET) + 1; + clk->rate = clk->parent->rate / div; + } else if (mux == 3) { + clk->rate = clk->parent->rate / 8; + } else { + clk->rate = clk->parent->rate; + } +} + +static struct clk ipu_di_clk[] = { + { + .name = "ipu_di0_clk", + .id = 0, + .parent = &pll3_sw_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG5_OFFSET, + .recalc = _clk_ipu_di_recalc, + .set_parent = _clk_ipu_di_set_parent, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "ipu_di1_clk", + .id = 1, + .parent = &pll3_sw_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG6_OFFSET, + .recalc = _clk_ipu_di_recalc, + .set_parent = _clk_ipu_di_set_parent, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static int _clk_csi0_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR2); + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, NULL); + reg = (reg & ~MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static void _clk_csi0_recalc(struct clk *clk) +{ + u32 reg, pred, podf; + + reg = __raw_readl(MXC_CCM_CSCDR4); + pred = ((reg & MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK) >> + MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK) >> + MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / (pred * podf); +} + +static unsigned long _clk_csi0_round_rate(struct clk *clk, unsigned long rate) +{ + u32 pre, post; + u32 div = clk->parent->rate / rate; + if (clk->parent->rate % rate) + div++; + + __calc_pre_post_dividers(div, &pre, &post); + + return clk->parent->rate / (pre * post); +} + +static int _clk_csi0_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 pre, post; + + div = clk->parent->rate / rate; + + if ((clk->parent->rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + /* Set CSI clock divider */ + reg = __raw_readl(MXC_CCM_CSCDR4) & + ~(MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK | + MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR4); + + clk->rate = rate; + return 0; +} + +static struct clk csi0_clk = { + .name = "csi_mclk1", + .parent = &pll3_sw_clk, + .set_parent = _clk_csi0_set_parent, + .recalc = _clk_csi0_recalc, + .round_rate = _clk_csi0_round_rate, + .set_rate = _clk_csi0_set_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG2_OFFSET, + .disable = _clk_disable, +}; + +static int _clk_csi1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR2); + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, NULL); + reg = (reg & ~MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static void _clk_csi1_recalc(struct clk *clk) +{ + u32 reg, pred, podf; + + reg = __raw_readl(MXC_CCM_CSCDR4); + pred = ((reg & MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK) >> + MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK) >> + MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / (pred * podf); +} + +static unsigned long _clk_csi1_round_rate(struct clk *clk, unsigned long rate) +{ + u32 pre, post; + u32 div = clk->parent->rate / rate; + if (clk->parent->rate % rate) + div++; + + __calc_pre_post_dividers(div, &pre, &post); + + return clk->parent->rate / (pre * post); +} + +static int _clk_csi1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 pre, post; + + div = clk->parent->rate / rate; + + if ((clk->parent->rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + /* Set CSI clock divider */ + reg = __raw_readl(MXC_CCM_CSCDR4) & + ~(MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK | + MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR4); + + clk->rate = rate; + return 0; +} + +static struct clk csi1_clk = { + .name = "csi_mclk2", + .parent = &pll3_sw_clk, + .set_parent = _clk_csi1_set_parent, + .recalc = _clk_csi1_recalc, + .round_rate = _clk_csi1_round_rate, + .set_rate = _clk_csi1_set_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG3_OFFSET, + .disable = _clk_disable, +}; + + +static int _clk_hsc_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + /* Handshake with IPU when certain clock rates are changed. */ + reg = __raw_readl(MXC_CCM_CCDR); + reg &= ~MXC_CCM_CCDR_HSC_HS_MASK; + __raw_writel(reg, MXC_CCM_CCDR); + + reg = __raw_readl(MXC_CCM_CLPCR); + reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + + return 0; +} + +static void _clk_hsc_disable(struct clk *clk) +{ + u32 reg; + + _clk_disable(clk); + /* No handshake with HSC as its not enabled. */ + reg = __raw_readl(MXC_CCM_CCDR); + reg |= MXC_CCM_CCDR_IPU_HS_MASK; + __raw_writel(reg, MXC_CCM_CCDR); + + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); +} + +static struct clk mipi_esc_clk = { + .name = "mipi_esc_clk", + .parent = &pll2_sw_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG5_OFFSET, +}; + +static struct clk mipi_hsc2_clk = { + .name = "mipi_hsc2_clk", + .parent = &pll2_sw_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG4_OFFSET, + .secondary = &mipi_esc_clk, +}; + +static struct clk mipi_hsc1_clk = { + .name = "mipi_hsc1_clk", + .parent = &pll2_sw_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG3_OFFSET, + .secondary = &mipi_hsc2_clk, +}; + +static struct clk mipi_hsp_clk = { + .name = "mipi_hsp_clk", + .parent = &ipu_clk[0], + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG6_OFFSET, + .enable = _clk_hsc_enable, + .disable = _clk_hsc_disable, + .secondary = &mipi_hsc1_clk, +}; + +static int _clk_tve_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + + if (parent == &pll3_sw_clk) { + reg &= ~(MXC_CCM_CSCMR1_TVE_CLK_SEL); + } else if (parent == &osc_clk) { + reg |= MXC_CCM_CSCMR1_TVE_CLK_SEL; + reg &= MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL; + } else if (parent == &ckih_clk) { + reg |= MXC_CCM_CSCMR1_TVE_CLK_SEL; + reg |= MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL; + } else { + BUG(); + } + + __raw_writel(reg, MXC_CCM_CSCMR1); + return 0; +} + +static void _clk_tve_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if ((reg & MXC_CCM_CSCMR1_TVE_CLK_SEL) == 0) { + reg = __raw_readl(MXC_CCM_CDCDR) & + MXC_CCM_CDCDR_TVE_CLK_PRED_MASK; + div = (reg >> MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET) + 1; + clk->rate = clk->parent->rate / div; + } else { + clk->rate = clk->parent->rate; + } +} + +static unsigned long _clk_tve_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (reg & MXC_CCM_CSCMR1_TVE_CLK_SEL) + return -EINVAL; + + div = clk->parent->rate / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return clk->parent->rate / div; +} + +static int _clk_tve_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (reg & MXC_CCM_CSCMR1_TVE_CLK_SEL) + return -EINVAL; + + div = clk->parent->rate / rate; + if (div == 0) + div++; + if (((clk->parent->rate / div) != rate) || (div > 8)) + return -EINVAL; + + div--; + reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_TVE_CLK_PRED_MASK; + reg |= div << MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CDCDR); + clk->rate = rate; + return 0; +} + +static struct clk tve_clk = { + .name = "tve_clk", + .parent = &pll3_sw_clk, + .set_parent = _clk_tve_set_parent, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG15_OFFSET, + .recalc = _clk_tve_recalc, + .round_rate = _clk_tve_round_rate, + .set_rate = _clk_tve_set_rate, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk spba_clk = { + .name = "spba_clk", + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG0_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static void _clk_uart_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk uart_main_clk = { + .name = "uart_main_clk", + .parent = &pll2_sw_clk, + .recalc = _clk_uart_recalc, + .set_parent = _clk_uart_set_parent, + .flags = RATE_PROPAGATES, +}; + +static struct clk uart1_clk[] = { + { + .name = "uart_clk", + .id = 0, + .parent = &uart_main_clk, + .secondary = &uart1_clk[1], + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG4_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "uart_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .secondary = &aips_tz1_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG3_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk uart2_clk[] = { + { + .name = "uart_clk", + .id = 1, + .parent = &uart_main_clk, + .secondary = &uart2_clk[1], + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "uart_ipg_clk", + .id = 1, + .parent = &ipg_clk, + .secondary = &aips_tz1_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG5_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk uart3_clk[] = { + { + .name = "uart_clk", + .id = 2, + .parent = &uart_main_clk, + .secondary = &uart3_clk[1], + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "uart_ipg_clk", + .id = 2, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk gpt_clk[] = { + { + .name = "gpt_clk", + .parent = &ipg_clk, + .id = 0, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "gpt_ipg_clk", + .id = 0, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "gpt_32k_clk", + .id = 0, + .parent = &ckil_clk, + }, +}; + +static struct clk pwm1_clk[] = { + { + .name = "pwm_clk", + .parent = &ipg_perclk, + .id = 0, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &pwm1_clk[1], + }, + { + .name = "pwm_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG5_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "pwm_32k_clk", + .id = 0, + .parent = &ckil_clk, + }, +}; + +static struct clk pwm2_clk[] = { + { + .name = "pwm_clk", + .parent = &ipg_perclk, + .id = 1, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &pwm2_clk[1], + }, + { + .name = "pwm_ipg_clk", + .id = 1, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "pwm_32k_clk", + .id = 1, + .parent = &ckil_clk, + }, +}; + +static struct clk i2c_clk[] = { + { + .name = "i2c_clk", + .id = 0, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "i2c_clk", + .id = 1, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static void _clk_hsi2c_serial_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR3); + prediv = ((reg & MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK) >> + MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK) >> + MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static struct clk hsi2c_serial_clk = { + .name = "hsi2c_serial_clk", + .id = 0, + .parent = &pll3_sw_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG11_OFFSET, + .recalc = _clk_hsi2c_serial_recalc, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk hsi2c_clk = { + .name = "hsi2c_clk", + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static void _clk_cspi_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR2); + prediv = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >> + MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >> + MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static int _clk_cspi_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk cspi_main_clk = { + .name = "cspi_main_clk", + .parent = &pll3_sw_clk, + .recalc = _clk_cspi_recalc, + .set_parent = _clk_cspi_set_parent, + .flags = RATE_PROPAGATES, +}; + +static struct clk cspi1_clk[] = { + { + .name = "cspi_clk", + .id = 0, + .parent = &cspi_main_clk, + .secondary = &cspi1_clk[1], + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "cspi_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk cspi2_clk[] = { + { + .name = "cspi_clk", + .id = 1, + .parent = &cspi_main_clk, + .secondary = &cspi2_clk[1], + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "cspi_ipg_clk", + .id = 1, + .parent = &ipg_clk, + .secondary = &aips_tz2_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk cspi3_clk[] = { + { + .name = "cspi_clk", + .id = 2, + .parent = &cspi_main_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &cspi3_clk[1], + }, + { + .name = "cspi_ipg_clk", + .id = 2, + .parent = &ipg_clk, + .secondary = &aips_tz2_clk, + }, +}; + +static int _clk_ssi_lp_apm_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &ckih_clk, &lp_apm_clk, &ckih2_clk, NULL); + reg = __raw_readl(MXC_CCM_CSCMR1) & + ~MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi_lp_apm_clk = { + .name = "ssi_lp_apm_clk", + .parent = &ckih_clk, + .set_parent = _clk_ssi_lp_apm_set_parent, +}; + +static void _clk_ssi1_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CS1CDR); + prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK) >> + MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK) >> + MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} +static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, + &pll3_sw_clk, &ssi_lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi1_clk[] = { + { + .name = "ssi_clk", + .id = 0, + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi1_set_parent, + .secondary = &ssi1_clk[1], + .recalc = _clk_ssi1_recalc, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "ssi_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .secondary = &ssi1_clk[2], + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "ssi_dep_clk", + .id = 0, + .parent = &aips_tz2_clk, +#ifdef CONFIG_SND_MXC_SOC_IRAM + .secondary = &emi_intr_clk, +#else + .secondary = &emi_fast_clk, +#endif + }, +}; + +static void _clk_ssi2_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CS2CDR); + prediv = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK) >> + MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK) >> + MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, + &pll3_sw_clk, &ssi_lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi2_clk[] = { + { + .name = "ssi_clk", + .id = 1, + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi2_set_parent, + .secondary = &ssi2_clk[1], + .recalc = _clk_ssi2_recalc, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "ssi_ipg_clk", + .id = 1, + .parent = &ipg_clk, + .secondary = &ssi2_clk[2], + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "ssi_dep_clk", + .id = 1, + .parent = &spba_clk, +#ifdef CONFIG_SND_MXC_SOC_IRAM + .secondary = &emi_intr_clk, +#else + .secondary = &emi_fast_clk, +#endif + }, +}; + +static void _clk_ssi_ext1_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + clk->rate = clk->parent->rate; + reg = __raw_readl(MXC_CCM_CSCMR1); + if ((reg & MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL) == 0) { + reg = __raw_readl(MXC_CCM_CS1CDR); + prediv = ((reg & MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK) >> + MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK) >> + MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / (prediv * podf); + } +} + +static int _clk_ssi_ext1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &ssi1_clk[0]) { + reg |= MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL; + } else { + reg &= ~MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL; + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &ssi_lp_apm_clk); + reg = (reg & ~MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET); + } + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi_ext1_clk = { + .name = "ssi_ext1_clk", + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi_ext1_set_parent, + .recalc = _clk_ssi_ext1_recalc, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG14_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static void _clk_ssi_ext2_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + clk->rate = clk->parent->rate; + reg = __raw_readl(MXC_CCM_CSCMR1); + if ((reg & MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL) == 0) { + reg = __raw_readl(MXC_CCM_CS2CDR); + prediv = ((reg & MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK) >> + MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK) >> + MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / (prediv * podf); + } +} + +static int _clk_ssi_ext2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &ssi2_clk[0]) { + reg |= MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL; + } else { + reg &= ~MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL; + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &ssi_lp_apm_clk); + reg = (reg & ~MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET); + } + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi_ext2_clk = { + .name = "ssi_ext2_clk", + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi_ext2_set_parent, + .recalc = _clk_ssi_ext2_recalc, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG15_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk iim_clk = { + .name = "iim_clk", + .parent = &ipg_clk, + .secondary = &aips_tz2_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGR0_CG15_OFFSET, + .disable = _clk_disable, +}; + +static struct clk tmax1_clk = { + .name = "tmax1_clk", + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG0_OFFSET, + .disable = _clk_disable, + }; + +static struct clk tmax2_clk = { + .name = "tmax2_clk", + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG1_OFFSET, + .disable = _clk_disable, +}; + +static struct clk tmax3_clk = { + .name = "tmax3_clk", + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG2_OFFSET, + .disable = _clk_disable, +}; + +static void _clk_usboh3_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk usboh3_clk[] = { + { + .name = "usboh3_clk", + .parent = &pll3_sw_clk, + .set_parent = _clk_usboh3_set_parent, + .recalc = _clk_usboh3_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG14_OFFSET, + .disable = _clk_disable, + .secondary = &usboh3_clk[1], + }, + { + .name = "usb_ahb_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG13_OFFSET, + .disable = _clk_disable, + .secondary = &usboh3_clk[2], + }, + { + .name = "usb_sec_clk", + .parent = &tmax2_clk, + .secondary = &emi_fast_clk, + }, +}; + +static void _clk_usb_phy_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + if (clk->parent == &pll3_sw_clk) { + reg = __raw_readl(MXC_CCM_CDCDR); + prediv = ((reg & MXC_CCM_CDCDR_USB_PHY_PRED_MASK) >> + MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CDCDR_USB_PHY_PODF_MASK) >> + MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); + } else + clk->rate = clk->parent->rate; +} + +static int _clk_usb_phy_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &osc_clk) + reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; + else if (parent == &pll3_sw_clk) + reg |= MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; + else + BUG(); + + __raw_writel(reg, MXC_CCM_CSCMR1); + return 0; +} + +static struct clk usb_phy_clk = { + .name = "usb_phy_clk", + .parent = &pll3_sw_clk, + .secondary = &tmax3_clk, + .set_parent = _clk_usb_phy_set_parent, + .recalc = _clk_usb_phy_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG0_OFFSET, + .disable = _clk_disable, +}; + +static struct clk esdhc_dep_clks = { + .name = "sd_dep_clk", + .parent = &spba_clk, + .secondary = &emi_fast_clk, +}; + + +static void _clk_esdhc1_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static int _clk_esdhc1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & + ~MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk esdhc1_clk[] = { + { + .name = "esdhc_clk", + .id = 0, + .parent = &pll3_sw_clk, + .set_parent = _clk_esdhc1_set_parent, + .recalc = _clk_esdhc1_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG1_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc1_clk[1], + }, + { + .name = "esdhc_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .secondary = &esdhc1_clk[2], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG0_OFFSET, + .disable = _clk_disable, + }, + { + .name = "esdhc_sec_clk", + .id = 0, + .parent = &tmax3_clk, + .secondary = &esdhc_dep_clks, + }, + +}; + +static void _clk_esdhc2_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static int _clk_esdhc2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & + ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk esdhc2_clk[] = { + { + .name = "esdhc_clk", + .id = 1, + .parent = &pll3_sw_clk, + .set_parent = _clk_esdhc2_set_parent, + .recalc = _clk_esdhc2_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG3_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc2_clk[1], + }, + { + .name = "esdhc_ipg_clk", + .id = 1, + .parent = &ipg_clk, + .secondary = &esdhc2_clk[2], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG2_OFFSET, + .disable = _clk_disable, + }, + { + .name = "esdhc_sec_clk", + .id = 0, + .parent = &tmax2_clk, + .secondary = &esdhc_dep_clks, + }, +}; + +static int _clk_esdhc3_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &esdhc1_clk[0]) + reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL; + else if (parent == &esdhc2_clk[0]) + reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL; + else + BUG(); + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk esdhc3_clk[] = { + { + .name = "esdhc_clk", + .id = 2, + .parent = &esdhc1_clk[0], + .set_parent = _clk_esdhc3_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG5_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc3_clk[1], + }, + { + .name = "esdhc_ipg_clk", + .id = 2, + .parent = &ipg_clk, + .secondary = &esdhc3_clk[2], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG4_OFFSET, + .disable = _clk_disable, + }, + { + .name = "esdhc_sec_clk", + .id = 0, + .parent = &ahb_max_clk, + .secondary = &esdhc_dep_clks, + }, +}; + + +static int _clk_esdhc4_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &esdhc1_clk[0]) + reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; + else if (parent == &esdhc2_clk[0]) + reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; + else + BUG(); + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk esdhc4_clk[] = { + { + .name = "esdhc_clk", + .id = 3, + .parent = &esdhc1_clk[0], + .set_parent = _clk_esdhc4_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG7_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc3_clk[1], + }, + { + .name = "esdhc_ipg_clk", + .id = 3, + .parent = &ipg_clk, + .secondary = &esdhc3_clk[2], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGR3_CG6_OFFSET, + .disable = _clk_disable, + }, + { + .name = "esdhc_sec_clk", + .id = 0, + .parent = &tmax3_clk, + .secondary = &esdhc_dep_clks, + }, +}; + +static void _clk_nfc_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >> + MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + +static struct clk emi_enfc_clk = { + .name = "nfc_clk", + .parent = &emi_slow_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG10_OFFSET, + .disable = _clk_disable_inwait, + .recalc = _clk_nfc_recalc, +}; + +static int _clk_spdif_xtal_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &osc_clk, &ckih_clk, &ckih2_clk, NULL); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk spdif_xtal_clk = { + .name = "spdif_xtal_clk", + .parent = &osc_clk, + .set_parent = _clk_spdif_xtal_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG15_OFFSET, + .disable = _clk_disable, +}; + +static int _clk_spdif0_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR2); + reg |= MXC_CCM_CSCMR2_SPDIF0_COM; + if (parent != &ssi1_clk[0]) { + reg &= ~MXC_CCM_CSCMR2_SPDIF0_COM; + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &spdif_xtal_clk); + reg = (reg & ~MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET); + } + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static void _clk_spdif0_recalc(struct clk *clk) +{ + u32 reg, pred, podf; + + if (clk->parent == &ssi1_clk[0]) { + clk->rate = clk->parent->rate; + } else { + reg = __raw_readl(MXC_CCM_CDCDR); + pred = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK) >> + MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK) >> + MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / (pred * podf); + } +} + +static struct clk spdif0_clk[] = { + { + .name = "spdif_clk", + .id = 0, + .parent = &pll3_sw_clk, + .set_parent = _clk_spdif0_set_parent, + .recalc = _clk_spdif0_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG13_OFFSET, + .disable = _clk_disable, + }, + { + .name = "spdif_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG15_OFFSET, + .disable = _clk_disable, + }, +}; + +static int _clk_spdif1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR2); + reg |= MXC_CCM_CSCMR2_SPDIF1_COM; + if (parent != &ssi2_clk[0]) { + reg &= ~MXC_CCM_CSCMR2_SPDIF1_COM; + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &spdif_xtal_clk); + reg = (reg & ~MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET); + } + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static void _clk_spdif1_recalc(struct clk *clk) +{ + u32 reg, pred, podf; + + if (clk->parent == &ssi2_clk[0]) { + clk->rate = clk->parent->rate; + } else { + reg = __raw_readl(MXC_CCM_CDCDR); + pred = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK) >> + MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK) >> + MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / (pred * podf); + } +} + +static struct clk spdif1_clk[] = { + { + .name = "spdif_clk", + .id = 1, + .parent = &pll3_sw_clk, + .set_parent = _clk_spdif1_set_parent, + .recalc = _clk_spdif1_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG14_OFFSET, + .disable = _clk_disable, + }, + { + .name = "spdif_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG15_OFFSET, + .disable = _clk_disable, + }, +}; + +static int _clk_ddr_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, reg2, mux; + reg = __raw_readl(MXC_CCM_CBCMR); + reg2 = __raw_readl(MXC_CCM_CBCDR); + mux = _get_mux_ddr(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk, &ddr_hf_clk); + if (mux < 4) { + reg = (reg & ~MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) | + (mux << MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CBCMR); + } else { + reg2 = (reg2 & ~MXC_CCM_CBCDR_DDR_HF_SEL) | + (MXC_CCM_CBCDR_DDR_HF_SEL); + __raw_writel(reg2, MXC_CCM_CBCDR); + } + + return 0; +} + +static struct clk ddr_clk = { + .name = "ddr_clk", + .parent = &ddr_hf_clk, + .set_parent = _clk_ddr_set_parent, + .flags = RATE_PROPAGATES, +}; + +static int _clk_arm_axi_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + reg = __raw_readl(MXC_CCM_CBCMR); + mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk); + reg = (reg & ~MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK) | + (mux << MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CBCMR); + + return 0; +} + +static struct clk arm_axi_clk = { + .name = "arm_axi_clk", + .parent = &axi_a_clk, + .set_parent = _clk_arm_axi_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGR0_CG1_OFFSET, + .disable = _clk_disable, +}; + +static int _clk_vpu_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + reg = __raw_readl(MXC_CCM_CBCMR); + mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk); + reg = (reg & ~MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK) | + (mux << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CBCMR); + + return 0; +} + +static struct clk vpu_clk[] = { + { + .name = "vpu_clk", + .set_parent = _clk_vpu_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG4_OFFSET, + .disable = _clk_disable, + .secondary = &vpu_clk[1], + }, + { + .name = "vpu_core_clk", + .set_parent = _clk_vpu_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG3_OFFSET, + .disable = _clk_disable, + .secondary = &vpu_clk[2], + }, + { + .name = "vpu_emi_clk", + .parent = &emi_fast_clk, +#ifdef CONFIG_MXC_VPU_IRAM + .secondary = &emi_intr_clk, +#endif + } +}; + +static int _clk_lpsr_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + reg = __raw_readl(MXC_CCM_CLPCR); + mux = _get_mux(parent, &ckil_clk, &fpm_clk, &fpm_div2_clk, NULL); + reg = (reg & ~MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK) | + (mux << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CLPCR); + + return 0; +} + +static struct clk lpsr_clk = { + .name = "lpsr_clk", + .parent = &ckil_clk, + .set_parent = _clk_lpsr_set_parent, +}; + +static void _clk_pgc_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCDR1); + div = (reg & MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET; + div = 1 >> div; + clk->rate = clk->parent->rate / div; +} + +static struct clk pgc_clk = { + .name = "pgc_clk", + .parent = &ipg_clk, + .recalc = _clk_pgc_recalc, +}; + +/*usb OTG clock */ + +static struct clk usb_clk = { + .name = "usb_clk", + .rate = 60000000, +}; + +static struct clk usb_utmi_clk = { + .name = "usb_utmi_clk", + .enable = _clk_enable, + .enable_reg = MXC_CCM_CSCMR1, + .enable_shift = MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET, + .disable = _clk_disable, +}; + +static struct clk rtc_clk = { + .name = "rtc_clk", + .parent = &ckil_clk, + .secondary = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG14_OFFSET, + .disable = _clk_disable, +}; + +static struct clk ata_clk = { + .name = "ata_clk", + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG0_OFFSET, + .disable = _clk_disable, +}; + +static struct clk owire_clk = { + .name = "owire_clk", + .parent = &ipg_perclk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG11_OFFSET, + .disable = _clk_disable, +}; + + +static struct clk fec_clk[] = { + { + .name = "fec_clk", + .parent = &ipg_clk, + .secondary = &fec_clk[1], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGR2_CG12_OFFSET, + .disable = _clk_disable, + }, + { + .name = "fec_sec1_clk", + .parent = &tmax2_clk, + .secondary = &fec_clk[2], + }, + { + .name = "fec_sec2_clk", + .parent = &aips_tz2_clk, + .secondary = &emi_fast_clk, + }, +}; + +static struct clk sahara_clk[] = { + { + .name = "sahara_clk", + .parent = &ahb_clk, + .secondary = &sahara_clk[1], + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "sahara_sec_clk", + .parent = &tmax1_clk, + .secondary = &emi_fast_clk, + } +}; + +static int _clk_gpu3d_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CBCMR); + mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk); + reg = (reg & ~MXC_CCM_CBCMR_GPU_CLK_SEL_MASK) | + (mux << MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CBCMR); + + return 0; +} + +static struct clk gpu3d_clk = { + .name = "gpu3d_clk", + .parent = &axi_a_clk, + .set_parent = _clk_gpu3d_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG1_OFFSET, + .disable = _clk_disable, +}; + +static struct clk garb_clk = { + .name = "garb_clk", + .parent = &axi_a_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG2_OFFSET, + .disable = _clk_disable, +}; + +static struct clk emi_garb_clk = { + .name = "emi_garb_clk", + .parent = &axi_a_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG4_OFFSET, + .disable = _clk_disable, +}; + +static struct clk *mxc_clks[] = { + &osc_clk, + &ckih_clk, + &ckih2_clk, + &ckil_clk, + &fpm_clk, + &fpm_div2_clk, + &pll1_main_clk, + &pll1_sw_clk, + &pll2_sw_clk, + &pll3_sw_clk, + &gpc_dvfs_clk, + &lp_apm_clk, + &cpu_clk, + &periph_apm_clk, + &main_bus_clk, + &axi_a_clk, + &axi_b_clk, + &ahb_clk, + &ahb_max_clk, + &ipg_clk, + &ipg_perclk, + &ahbmux1_clk, + &ahbmux2_clk, + &aips_tz1_clk, + &aips_tz2_clk, + &sdma_clk[0], + &sdma_clk[1], + &ipu_clk[0], + &ipu_clk[1], + &ipu_di_clk[0], + &ipu_di_clk[1], + &tve_clk, + &csi0_clk, + &csi1_clk, + &uart_main_clk, + &uart1_clk[0], + &uart1_clk[1], + &uart2_clk[0], + &uart2_clk[1], + &uart3_clk[0], + &uart3_clk[1], + &spba_clk, + &i2c_clk[0], + &i2c_clk[1], + &hsi2c_clk, + &hsi2c_serial_clk, + &gpt_clk[0], + &gpt_clk[1], + &gpt_clk[2], + &pwm1_clk[0], + &pwm1_clk[1], + &pwm1_clk[2], + &pwm2_clk[0], + &pwm2_clk[1], + &pwm2_clk[2], + &cspi_main_clk, + &cspi1_clk[0], + &cspi1_clk[1], + &cspi2_clk[0], + &cspi2_clk[1], + &cspi3_clk[0], + &cspi3_clk[1], + &ssi_lp_apm_clk, + &ssi1_clk[0], + &ssi1_clk[1], + &ssi1_clk[2], + &ssi2_clk[0], + &ssi2_clk[1], + &ssi2_clk[2], + &ssi_ext1_clk, + &ssi_ext2_clk, + &iim_clk, + &tmax1_clk, + &tmax2_clk, + &tmax3_clk, + &usboh3_clk[0], + &usboh3_clk[1], + &usboh3_clk[2], + &usb_phy_clk, + &usb_utmi_clk, + &usb_clk, + &esdhc1_clk[0], + &esdhc1_clk[1], + &esdhc2_clk[0], + &esdhc2_clk[1], + &esdhc3_clk[0], + &esdhc3_clk[1], + &esdhc4_clk[0], + &esdhc4_clk[1], + &esdhc_dep_clks, + &emi_slow_clk, + &ddr_clk, + &emi_enfc_clk, + &emi_fast_clk, + &emi_intr_clk, + &spdif_xtal_clk, + &spdif0_clk[0], + &spdif0_clk[1], + &spdif1_clk[0], + &spdif1_clk[1], + &arm_axi_clk, + &vpu_clk[0], + &vpu_clk[1], + &vpu_clk[2], + &lpsr_clk, + &pgc_clk, + &rtc_clk, + &ata_clk, + &owire_clk, + &fec_clk[0], + &fec_clk[1], + &fec_clk[2], + &mipi_hsc1_clk, + &mipi_hsc2_clk, + &mipi_esc_clk, + &mipi_hsp_clk, + &sahara_clk[0], + &sahara_clk[1], + &gpu3d_clk, + &garb_clk, + &emi_garb_clk, + &ddr_hf_clk, +}; + +static void clk_tree_init(void) +{ + u32 reg, reg2, dp_ctl; + + /* set pll1_main_clk parent */ + pll1_main_clk.parent = &osc_clk; + dp_ctl = __raw_readl(pll_base[0] + MXC_PLL_DP_CTL); + if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) + pll1_main_clk.parent = &fpm_clk; + /* set pll2_sw_clk parent */ + pll2_sw_clk.parent = &osc_clk; + dp_ctl = __raw_readl(pll_base[1] + MXC_PLL_DP_CTL); + if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) + pll2_sw_clk.parent = &fpm_clk; + /* set pll3_clk parent */ + pll3_sw_clk.parent = &osc_clk; + dp_ctl = __raw_readl(pll_base[2] + MXC_PLL_DP_CTL); + if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) + pll3_sw_clk.parent = &fpm_clk; + + /* set emi_slow_clk parent */ + emi_slow_clk.parent = &main_bus_clk; + reg = __raw_readl(MXC_CCM_CBCDR); + if ((reg & MXC_CCM_CBCDR_EMI_CLK_SEL) != 0) + emi_slow_clk.parent = &ahb_clk; + + /* set ipg_perclk parent */ + ipg_perclk.parent = &lp_apm_clk; + reg = __raw_readl(MXC_CCM_CBCMR); + if ((reg & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) != 0) { + ipg_perclk.parent = &ipg_clk; + } else { + if ((reg & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL) == 0) + ipg_perclk.parent = &main_bus_clk; + } + + /* set DDR clock parent */ + reg = __raw_readl(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK; + reg >>= MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET; + reg2 = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_DDR_HF_SEL; + reg2 >>= MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET; + + if (reg2) { + ddr_clk.parent = &ddr_hf_clk; + } else { + if (reg == 0) { + ddr_clk.parent = &axi_a_clk; + } else if (reg == 1) { + ddr_clk.parent = &axi_b_clk; + } else if (reg == 2) { + ddr_clk.parent = &emi_slow_clk; + } else { + ddr_clk.parent = &ahb_clk; + } + } +} + +int __init mxc_clocks_init(void) +{ + struct clk **clkp; + int i, reg; + + for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) + clk_register(*clkp); + + /* Turn off all possible clocks */ + if (mxc_jtag_enabled) { + __raw_writel(1 << MXC_CCM_CCGR0_CG0_OFFSET | + 1 << MXC_CCM_CCGR0_CG1_OFFSET | + 1 << MXC_CCM_CCGR0_CG2_OFFSET | + 1 << MXC_CCM_CCGR0_CG3_OFFSET | + 1 << MXC_CCM_CCGR0_CG4_OFFSET | + 1 << MXC_CCM_CCGR0_CG8_OFFSET | + 1 << MXC_CCM_CCGR0_CG9_OFFSET | + 1 << MXC_CCM_CCGR0_CG12_OFFSET | + 1 << MXC_CCM_CCGR0_CG13_OFFSET | + 1 << MXC_CCM_CCGR0_CG14_OFFSET, MXC_CCM_CCGR0); + } else { + __raw_writel(1 << MXC_CCM_CCGR0_CG0_OFFSET | + 1 << MXC_CCM_CCGR0_CG1_OFFSET | + 1 << MXC_CCM_CCGR0_CG2_OFFSET | + 1 << MXC_CCM_CCGR0_CG3_OFFSET | + 1 << MXC_CCM_CCGR0_CG8_OFFSET | + 1 << MXC_CCM_CCGR0_CG9_OFFSET | + 1 << MXC_CCM_CCGR0_CG12_OFFSET | + 1 << MXC_CCM_CCGR0_CG13_OFFSET | + 1 << MXC_CCM_CCGR0_CG14_OFFSET, MXC_CCM_CCGR0); + } + __raw_writel(0, MXC_CCM_CCGR1); + __raw_writel(0, MXC_CCM_CCGR2); + __raw_writel(0, MXC_CCM_CCGR3); + __raw_writel(3 << MXC_CCM_CCGR4_CG8_OFFSET, MXC_CCM_CCGR4); + __raw_writel(1 << MXC_CCM_CCGR5_CG2_OFFSET | + 1 << MXC_CCM_CCGR5_CG7_OFFSET | + 1 << MXC_CCM_CCGR5_CG8_OFFSET | + 1 << MXC_CCM_CCGR5_CG9_OFFSET | + 1 << MXC_CCM_CCGR5_CG10_OFFSET | + 3 << MXC_CCM_CCGR5_CG11_OFFSET, MXC_CCM_CCGR5); + __raw_writel(1 << MXC_CCM_CCGR6_CG4_OFFSET, MXC_CCM_CCGR6); + + /*Setup the LPM bypass bits */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS + | MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS + | MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS + | MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS + | MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + + /* This will propagate to all children and init all the clock rates */ + propagate_rate(&osc_clk); + propagate_rate(&ckih_clk); + propagate_rate(&ckih2_clk); + propagate_rate(&ckil_clk); + propagate_rate(&pll1_sw_clk); + propagate_rate(&pll2_sw_clk); + + clk_enable(&cpu_clk); + clk_enable(&main_bus_clk); + clk_enable(&gpt_clk[1]); + + reg = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_DDR_HF_SEL; + reg >>= MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET; + + if (reg) + clk_set_parent(&ddr_clk, &ddr_hf_clk); + else + clk_set_parent(&ddr_clk, &axi_a_clk); + + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) { + clk_set_parent(&vpu_clk[0], &ahb_clk); + clk_set_parent(&vpu_clk[1], &ahb_clk); + } else { + clk_set_parent(&vpu_clk[0], &axi_a_clk); + clk_set_parent(&vpu_clk[1], &axi_a_clk); + } + + /* Set the current working point. */ + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + for (i = 0; i < cpu_wp_nr; i++) { + if (clk_get_rate(&cpu_clk) == cpu_wp_tbl[i].cpu_rate) { + cpu_curr_wp = i; + break; + } + } + if (i > cpu_wp_nr) + BUG(); + + return 0; +} + +/*! + * Setup cpu clock based on working point. + * @param wp cpu freq working point + * @return 0 on success or error code on failure. + */ +static int cpu_clk_set_wp(int wp) +{ + struct cpu_wp *p; + u32 reg; + u32 stat; + + if (wp == cpu_curr_wp) + return 0; + + p = &cpu_wp_tbl[wp]; + + /* + * If DDR clock is sourced from PLL1, we cannot drop PLL1 freq. + * Use the ARM_PODF to change the freq of the core, leave the PLL1 + * freq unchanged. + */ + if (ddr_clk.parent == &ddr_hf_clk) { + reg = __raw_readl(MXC_CCM_CACRR); + reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK; + reg |= cpu_wp_tbl[wp].cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CACRR); + cpu_curr_wp = wp; + cpu_clk.rate = cpu_wp_tbl[wp].cpu_rate; + } else { + /* Change the ARM clock to requested frequency */ + /* First move the ARM clock to step clock which is running + * at 24MHz. + */ + + /* Change the source of pll1_sw_clk to be the step_clk */ + reg = __raw_readl(MXC_CCM_CCSR); + reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + __raw_writel(reg, MXC_CCM_CCSR); + + /* Stop the PLL */ + reg = __raw_readl(MXC_DPLL1_BASE + MXC_PLL_DP_CTL); + reg &= ~MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, MXC_DPLL1_BASE + MXC_PLL_DP_CTL); + + /* PDF and MFI */ + reg = p->pdf | p->mfi << MXC_PLL_DP_OP_MFI_OFFSET; + __raw_writel(reg, MXC_DPLL1_BASE + MXC_PLL_DP_OP); + + /* MFD */ + __raw_writel(p->mfd, MXC_DPLL1_BASE + MXC_PLL_DP_MFD); + + /* MFI */ + __raw_writel(p->mfn, MXC_DPLL1_BASE + MXC_PLL_DP_MFN); + + reg = __raw_readl(MXC_DPLL1_BASE + MXC_PLL_DP_CTL); + reg |= MXC_PLL_DP_CTL_UPEN; + /* Set the UPEN bits */ + __raw_writel(reg, MXC_DPLL1_BASE + MXC_PLL_DP_CTL); + /* Forcefully restart the PLL */ + reg |= MXC_PLL_DP_CTL_RST; + __raw_writel(reg, MXC_DPLL1_BASE + MXC_PLL_DP_CTL); + + /* Wait for the PLL to lock */ + do { + stat = __raw_readl(MXC_DPLL1_BASE + MXC_PLL_DP_CTL) & + MXC_PLL_DP_CTL_LRF; + } while (!stat); + + reg = __raw_readl(MXC_CCM_CCSR); + /* Move the PLL1 back to the pll1_main_clk */ + reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + __raw_writel(reg, MXC_CCM_CCSR); + + cpu_curr_wp = wp; + + pll1_sw_clk.rate = cpu_wp_tbl[wp].cpu_rate; + pll1_main_clk.rate = pll1_sw_clk.rate; + cpu_clk.rate = pll1_sw_clk.rate; + } + return 0; +} + +/*! + * Function to get timer clock rate early in boot process before clock tree is + * initialized. + * + * @return Clock rate for timer + */ +unsigned long __init clk_early_get_timer_rate(void) +{ + u32 reg; + + ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk); + + /* + *Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at + * 8MHz, its derived from lp_apm. + */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK; + reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK; + reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK; + reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + board_ref_clk_rate(&ckil_clk.rate, &osc_clk.rate, &ckih_clk.rate, + &ckih2_clk.rate); + clk_tree_init(); + + lp_apm_clk.rate = lp_apm_clk.parent->rate; + ipg_perclk.recalc(&ipg_perclk); + clk_enable(&ipg_perclk); + gpt_clk[1].enable(&gpt_clk[1]); + + return ipg_perclk.rate; +} diff -urN linux-2.6.26/arch/arm/mach-mx51/cpu.c linux-2.6.26-lab126/arch/arm/mach-mx51/cpu.c --- linux-2.6.26/arch/arm/mach-mx51/cpu.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/cpu.c 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,60 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mach-mx51/cpu.c + * + * @brief This file contains the CPU initialization code. + * + * @ingroup MSL_MX51 + */ + +#include +#include +#include +#include +#include + +/*! + * CPU initialization. It is called by fixup_mxc_board() + */ +void __init mxc_cpu_init(void) +{ + if (!system_rev) + mxc_set_system_rev(0x51, CHIP_REV_1_0); +} + +static int __init post_cpu_init(void) +{ + unsigned int base, reg; + + base = IO_ADDRESS(AIPS1_BASE_ADDR); + __raw_writel(0x0, base + 0x40); + __raw_writel(0x0, base + 0x44); + __raw_writel(0x0, base + 0x48); + __raw_writel(0x0, base + 0x4C); + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; + __raw_writel(reg, base + 0x50); + + base = IO_ADDRESS(AIPS2_BASE_ADDR); + __raw_writel(0x0, base + 0x40); + __raw_writel(0x0, base + 0x44); + __raw_writel(0x0, base + 0x48); + __raw_writel(0x0, base + 0x4C); + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; + __raw_writel(reg, base + 0x50); + + return 0; +} + +postcore_initcall(post_cpu_init); diff -urN linux-2.6.26/arch/arm/mach-mx51/crm_regs.h linux-2.6.26-lab126/arch/arm/mach-mx51/crm_regs.h --- linux-2.6.26/arch/arm/mach-mx51/crm_regs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/crm_regs.h 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,677 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ + +#define MXC_CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) +#define MXC_DPLL1_BASE IO_ADDRESS(PLL1_BASE_ADDR) +#define MXC_DPLL2_BASE IO_ADDRESS(PLL2_BASE_ADDR) +#define MXC_DPLL3_BASE IO_ADDRESS(PLL3_BASE_ADDR) + +/* PLL Register Offsets */ +#define MXC_PLL_DP_CTL 0x00 +#define MXC_PLL_DP_CONFIG 0x04 +#define MXC_PLL_DP_OP 0x08 +#define MXC_PLL_DP_MFD 0x0C +#define MXC_PLL_DP_MFN 0x10 +#define MXC_PLL_DP_MFNMINUS 0x14 +#define MXC_PLL_DP_MFNPLUS 0x18 +#define MXC_PLL_DP_HFS_OP 0x1C +#define MXC_PLL_DP_HFS_MFD 0x20 +#define MXC_PLL_DP_HFS_MFN 0x24 +#define MXC_PLL_DP_MFN_TOGC 0x28 +#define MXC_PLL_DP_DESTAT 0x2c + +/* PLL Register Bit definitions */ +#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 +#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 +#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 +#define MXC_PLL_DP_CTL_ADE 0x800 +#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 +#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) +#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 +#define MXC_PLL_DP_CTL_HFSM 0x80 +#define MXC_PLL_DP_CTL_PRE 0x40 +#define MXC_PLL_DP_CTL_UPEN 0x20 +#define MXC_PLL_DP_CTL_RST 0x10 +#define MXC_PLL_DP_CTL_RCP 0x8 +#define MXC_PLL_DP_CTL_PLM 0x4 +#define MXC_PLL_DP_CTL_BRM0 0x2 +#define MXC_PLL_DP_CTL_LRF 0x1 + +#define MXC_PLL_DP_CONFIG_BIST 0x8 +#define MXC_PLL_DP_CONFIG_SJC_CE 0x4 +#define MXC_PLL_DP_CONFIG_AREN 0x2 +#define MXC_PLL_DP_CONFIG_LDREQ 0x1 + +#define MXC_PLL_DP_OP_MFI_OFFSET 4 +#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) +#define MXC_PLL_DP_OP_PDF_OFFSET 0 +#define MXC_PLL_DP_OP_PDF_MASK 0xF + +#define MXC_PLL_DP_MFD_OFFSET 0 +#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF + +#define MXC_PLL_DP_MFN_OFFSET 0x0 +#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF + +#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) +#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) +#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 +#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF + +#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) +#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF + +/* Register addresses of CCM*/ +#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00) +#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04) +#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08) +#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C) +#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10) +#define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14) +#define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18) +#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C) +#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20) +#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24) +#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28) +#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C) +#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30) +#define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34) +#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38) +#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C) +#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40) +#define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44) +#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48) +#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C) +#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50) +#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54) +#define MXC_CCM_CISR (MXC_CCM_BASE + 0x58) +#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C) +#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60) +#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64) +#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68) +#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C) +#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70) +#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74) +#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78) +#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C) +#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80) +#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x84) + +/* Define the bits in register CCR */ +#define MXC_CCM_CCR_COSC_EN (1 << 12) +#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11) +#define MXC_CCM_CCR_CAMP2_EN (1 << 10) +#define MXC_CCM_CCR_CAMP1_EN (1 << 9) +#define MXC_CCM_CCR_FPM_EN (1 << 8) +#define MXC_CCM_CCR_OSCNT_OFFSET (0) +#define MXC_CCM_CCR_OSCNT_MASK (0xFF) + +/* Define the bits in register CCDR */ +#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18) +#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) +#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16) + +/* Define the bits in register CSR */ +#define MXC_CCM_CSR_COSR_READY (1 << 5) +#define MXC_CCM_CSR_LVS_VALUE (1 << 4) +#define MXC_CCM_CSR_CAMP2_READY (1 << 3) +#define MXC_CCM_CSR_CAMP1_READY (1 << 2) +#define MXC_CCM_CSR_FPM_READY (1 << 1) +#define MXC_CCM_CSR_REF_EN_B (1 << 0) + +/* Define the bits in register CCSR */ +#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9) +#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7) +#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) +#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5) +#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5) +#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3) +#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3) +#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) +#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) +#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) + +/* Define the bits in register CACRR */ +#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0) +#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7) + +/* Define the bits in register CBCDR */ +#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) +#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) +#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30) +#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30) +#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27) +#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) +#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22) +#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) +#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19) +#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) +#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16) +#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) +#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13) +#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) +#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10) +#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) +#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8) +#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) +#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6) +#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) +#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3) +#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) +#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0) +#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7) + +/* Define the bits in register CBCMR */ +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14) +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12) +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10) +#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8) +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6) +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4) +#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) + +/* Define the bits in register CSCMR1 */ +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30) +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26) +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) +#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) +#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) +#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1) + +/* Define the bits in register CSCMR2 */ +#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3) +#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3)) +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24) +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22) +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20) +#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18) +#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18) +#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16) +#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14) +#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12) +#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10) +#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9) +#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6) +#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6) +#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5) +#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4) +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2) +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0) +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3) + +/* Define the bits in register CSCDR1 */ +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7) + +/* Define the bits in register CS1CDR and CS2CDR */ +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6) +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0) +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F) + +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6) +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0) +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F) + +/* Define the bits in register CDCDR */ +#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28) +#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6) +#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3) +#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3) +#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0) +#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7) + +/* Define the bits in register CHSCCDR */ +#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12) +#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12) +#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6) +#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6) +#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3) +#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3) +#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0) +#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7) + +/* Define the bits in register CSCDR2 */ +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9) +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0) +#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F) + +/* Define the bits in register CSCDR3 */ +#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9) +#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F) + +/* Define the bits in register CSCDR4 */ +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9) +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F) + +/* Define the bits in register CDHIPR */ +#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) +#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6) +#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) +#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4) +#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3) +#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2) +#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1) +#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0) + +/* Define the bits in register CDCR */ +#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2) +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0) +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3) + +/* Define the bits in register CLPCR */ +#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) +#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) +#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) +#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) +#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) +#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) +#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17) +#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16) +#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11) +#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9) +#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) +#define MXC_CCM_CLPCR_VSTBY (0x1 << 8) +#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7) +#define MXC_CCM_CLPCR_SBYOS (0x1 << 6) +#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3) +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) +#define MXC_CCM_CLPCR_LPM_OFFSET (0) +#define MXC_CCM_CLPCR_LPM_MASK (0x3) + +/* Define the bits in register CISR */ +#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25) +#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) +#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20) +#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19) +#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18) +#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17) +#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16) +#define MXC_CCM_CISR_COSC_READY (0x1 << 6) +#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5) +#define MXC_CCM_CISR_CKIH_READY (0x1 << 4) +#define MXC_CCM_CISR_FPM_READY (0x1 << 3) +#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2) +#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1) +#define MXC_CCM_CISR_LRF_PLL1 (0x1) + +/* Define the bits in register CIMR */ +#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25) +#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) +#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20) +#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19) +#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18) +#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17) +#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16) +#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5) +#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4) +#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3) +#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2) +#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1) +#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1) + +/* Define the bits in register CCOSR */ +#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24) +#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21) +#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) +#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16) +#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) +#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) +#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4) +#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) +#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0) +#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF) + +/* Define the bits in registers CGPR */ +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4) +#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3) +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0) +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7) + +/* Define the bits in registers CCGRx */ +#define MXC_CCM_CCGR_CG_MASK 0x3 + +#define MXC_CCM_CCGR0_CG15_OFFSET 30 +#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30) +#define MXC_CCM_CCGR0_CG14_OFFSET 28 +#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGR0_CG13_OFFSET 26 +#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGR0_CG12_OFFSET 24 +#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGR0_CG11_OFFSET 22 +#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGR0_CG10_OFFSET 20 +#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20) +#define MXC_CCM_CCGR0_CG9_OFFSET 18 +#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18) +#define MXC_CCM_CCGR0_CG8_OFFSET 16 +#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16) +#define MXC_CCM_CCGR0_CG7_OFFSET 14 +#define MXC_CCM_CCGR0_CG6_OFFSET 12 +#define MXC_CCM_CCGR0_CG5_OFFSET 10 +#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10) +#define MXC_CCM_CCGR0_CG4_OFFSET 8 +#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8) +#define MXC_CCM_CCGR0_CG3_OFFSET 6 +#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6) +#define MXC_CCM_CCGR0_CG2_OFFSET 4 +#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4) +#define MXC_CCM_CCGR0_CG1_OFFSET 2 +#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2) +#define MXC_CCM_CCGR0_CG0_OFFSET 0 +#define MXC_CCM_CCGR0_CG0_MASK 0x3 + +#define MXC_CCM_CCGR1_CG15_OFFSET 30 +#define MXC_CCM_CCGR1_CG14_OFFSET 28 +#define MXC_CCM_CCGR1_CG13_OFFSET 26 +#define MXC_CCM_CCGR1_CG12_OFFSET 24 +#define MXC_CCM_CCGR1_CG11_OFFSET 22 +#define MXC_CCM_CCGR1_CG10_OFFSET 20 +#define MXC_CCM_CCGR1_CG9_OFFSET 18 +#define MXC_CCM_CCGR1_CG8_OFFSET 16 +#define MXC_CCM_CCGR1_CG7_OFFSET 14 +#define MXC_CCM_CCGR1_CG6_OFFSET 12 +#define MXC_CCM_CCGR1_CG5_OFFSET 10 +#define MXC_CCM_CCGR1_CG4_OFFSET 8 +#define MXC_CCM_CCGR1_CG3_OFFSET 6 +#define MXC_CCM_CCGR1_CG2_OFFSET 4 +#define MXC_CCM_CCGR1_CG1_OFFSET 2 +#define MXC_CCM_CCGR1_CG0_OFFSET 0 + +#define MXC_CCM_CCGR2_CG15_OFFSET 30 +#define MXC_CCM_CCGR2_CG14_OFFSET 28 +#define MXC_CCM_CCGR2_CG13_OFFSET 26 +#define MXC_CCM_CCGR2_CG12_OFFSET 24 +#define MXC_CCM_CCGR2_CG11_OFFSET 22 +#define MXC_CCM_CCGR2_CG10_OFFSET 20 +#define MXC_CCM_CCGR2_CG9_OFFSET 18 +#define MXC_CCM_CCGR2_CG8_OFFSET 16 +#define MXC_CCM_CCGR2_CG7_OFFSET 14 +#define MXC_CCM_CCGR2_CG6_OFFSET 12 +#define MXC_CCM_CCGR2_CG5_OFFSET 10 +#define MXC_CCM_CCGR2_CG4_OFFSET 8 +#define MXC_CCM_CCGR2_CG3_OFFSET 6 +#define MXC_CCM_CCGR2_CG2_OFFSET 4 +#define MXC_CCM_CCGR2_CG1_OFFSET 2 +#define MXC_CCM_CCGR2_CG0_OFFSET 0 + +#define MXC_CCM_CCGR3_CG15_OFFSET 30 +#define MXC_CCM_CCGR3_CG14_OFFSET 28 +#define MXC_CCM_CCGR3_CG13_OFFSET 26 +#define MXC_CCM_CCGR3_CG12_OFFSET 24 +#define MXC_CCM_CCGR3_CG11_OFFSET 22 +#define MXC_CCM_CCGR3_CG10_OFFSET 20 +#define MXC_CCM_CCGR3_CG9_OFFSET 18 +#define MXC_CCM_CCGR3_CG8_OFFSET 16 +#define MXC_CCM_CCGR3_CG7_OFFSET 14 +#define MXC_CCM_CCGR3_CG6_OFFSET 12 +#define MXC_CCM_CCGR3_CG5_OFFSET 10 +#define MXC_CCM_CCGR3_CG4_OFFSET 8 +#define MXC_CCM_CCGR3_CG3_OFFSET 6 +#define MXC_CCM_CCGR3_CG2_OFFSET 4 +#define MXC_CCM_CCGR3_CG1_OFFSET 2 +#define MXC_CCM_CCGR3_CG0_OFFSET 0 + +#define MXC_CCM_CCGR4_CG15_OFFSET 30 +#define MXC_CCM_CCGR4_CG14_OFFSET 28 +#define MXC_CCM_CCGR4_CG13_OFFSET 26 +#define MXC_CCM_CCGR4_CG12_OFFSET 24 +#define MXC_CCM_CCGR4_CG11_OFFSET 22 +#define MXC_CCM_CCGR4_CG10_OFFSET 20 +#define MXC_CCM_CCGR4_CG9_OFFSET 18 +#define MXC_CCM_CCGR4_CG8_OFFSET 16 +#define MXC_CCM_CCGR4_CG7_OFFSET 14 +#define MXC_CCM_CCGR4_CG6_OFFSET 12 +#define MXC_CCM_CCGR4_CG5_OFFSET 10 +#define MXC_CCM_CCGR4_CG4_OFFSET 8 +#define MXC_CCM_CCGR4_CG3_OFFSET 6 +#define MXC_CCM_CCGR4_CG2_OFFSET 4 +#define MXC_CCM_CCGR4_CG1_OFFSET 2 +#define MXC_CCM_CCGR4_CG0_OFFSET 0 + +#define MXC_CCM_CCGR5_CG15_OFFSET 30 +#define MXC_CCM_CCGR5_CG14_OFFSET 28 +#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGR5_CG13_OFFSET 26 +#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGR5_CG12_OFFSET 24 +#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGR5_CG11_OFFSET 22 +#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGR5_CG10_OFFSET 20 +#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20) +#define MXC_CCM_CCGR5_CG9_OFFSET 18 +#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18) +#define MXC_CCM_CCGR5_CG8_OFFSET 16 +#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16) +#define MXC_CCM_CCGR5_CG7_OFFSET 14 +#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14) +#define MXC_CCM_CCGR5_CG6_OFFSET 12 +#define MXC_CCM_CCGR5_CG5_OFFSET 10 +#define MXC_CCM_CCGR5_CG4_OFFSET 8 +#define MXC_CCM_CCGR5_CG3_OFFSET 6 +#define MXC_CCM_CCGR5_CG2_OFFSET 4 +#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4) +#define MXC_CCM_CCGR5_CG1_OFFSET 2 +#define MXC_CCM_CCGR5_CG0_OFFSET 0 +#define MXC_CCM_CCGR6_CG6_OFFSET 12 + +#define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12) +#define MXC_CCM_CCGR6_CG5_OFFSET 10 +#define MXC_CCM_CCGR6_CG5_MASK (0x3 << 10) +#define MXC_CCM_CCGR6_CG4_OFFSET 8 +#define MXC_CCM_CCGR6_CG4_MASK (0x3 << 8) +#define MXC_CCM_CCGR6_CG3_OFFSET 6 +#define MXC_CCM_CCGR6_CG2_OFFSET 4 +#define MXC_CCM_CCGR6_CG1_OFFSET 2 +#define MXC_CCM_CCGR6_CG0_OFFSET 0 + +#define MXC_CORTEXA8_BASE IO_ADDRESS(ARM_BASE_ADDR) +#define MXC_GPC_BASE IO_ADDRESS(GPC_BASE_ADDR) +#define MXC_DPTC_LP_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x80) +#define MXC_DPTC_GP_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x100) +#define MXC_DVFS_CORE_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x180) +#define MXC_DPTC_PER_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x1C0) +#define MXC_PGC_IPU_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x220) +#define MXC_PGC_VPU_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x240) +#define MXC_PGC_GPU_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x260) +#define MXC_SRPG_NEON_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x280) +#define MXC_SRPG_ARM_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x2A0) +#define MXC_SRPG_EMPGC0_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x2C0) +#define MXC_SRPG_EMPGC1_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x2D0) +#define MXC_SRPG_MEGAMIX_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x2E0) +#define MXC_SRPG_EMI_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x300) + +/* CORTEXA8 platform */ +#define MXC_CORTEXA8_PLAT_PVID (MXC_CORTEXA8_BASE + 0x0) +#define MXC_CORTEXA8_PLAT_GPC (MXC_CORTEXA8_BASE + 0x4) +#define MXC_CORTEXA8_PLAT_PIC (MXC_CORTEXA8_BASE + 0x8) +#define MXC_CORTEXA8_PLAT_LPC (MXC_CORTEXA8_BASE + 0xC) +#define MXC_CORTEXA8_PLAT_NEON_LPC (MXC_CORTEXA8_BASE + 0x10) +#define MXC_CORTEXA8_PLAT_ICGC (MXC_CORTEXA8_BASE + 0x14) +#define MXC_CORTEXA8_PLAT_AMC (MXC_CORTEXA8_BASE + 0x18) +#define MXC_CORTEXA8_PLAT_NMC (MXC_CORTEXA8_BASE + 0x20) +#define MXC_CORTEXA8_PLAT_NMS (MXC_CORTEXA8_BASE + 0x24) + +/* DVFS CORE */ +#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) +#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04) +#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08) +#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C) +#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10) +#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14) +#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18) +#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C) +#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20) +#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24) +#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28) +#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C) +#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30) +#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34) +#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38) +#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C) +#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40) + +/* GPC */ +#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0) +#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4) +#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8) +#define MXC_GPC_ALL_PU (MXC_GPC_BASE + 0xC) +#define MXC_GPC_NEON (MXC_GPC_BASE + 0x10) +#define MXC_GPC_PGR_ARMPG_OFFSET 8 +#define MXC_GPC_PGR_ARMPG_MASK (3 << 8) + +/* PGC */ +#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0) +#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC) +#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0) +#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC) +#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0) +#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC) + +#define MXC_PGCR_PCR 1 +#define MXC_SRPGCR_PCR 1 +#define MXC_EMPGCR_PCR 1 +#define MXC_PGSR_PSR 1 + + +#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0) +#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1) + +/* SRPG */ +#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0) +#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4) +#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8) + +#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0) +#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4) +#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8) + +#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0) +#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4) +#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8) + +#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0) +#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4) +#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8) + +#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0) +#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4) +#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8) + +#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0) +#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4) +#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8) + +#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx51/devices.c linux-2.6.26-lab126/arch/arm/mach-mx51/devices.c --- linux-2.6.26/arch/arm/mach-mx51/devices.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/devices.c 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,916 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "iomux.h" +#include "crm_regs.h" +#include +#include "sdma_script_code.h" +#include + +/* Flag used to indicate when IRAM has been initialized */ +int iram_ready; + +void mxc_sdma_get_script_info(sdma_script_start_addrs * sdma_script_addr) +{ + /* AP<->BP */ + sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR; + sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1; + sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1; + sdma_script_addr->mxc_sdma_ap_2_ap_fixed_addr = -1; + + /*misc */ + sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1; + sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1; + + /* firi */ + sdma_script_addr->mxc_sdma_firi_2_per_addr = -1; + sdma_script_addr->mxc_sdma_firi_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_per_2_firi_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_firi_addr = -1; + + /* uart */ + sdma_script_addr->mxc_sdma_uart_2_per_addr = uart_2_per_ADDR; + sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR; + + /* UART SH */ + sdma_script_addr->mxc_sdma_uartsh_2_per_addr = uartsh_2_per_ADDR; + sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr = uartsh_2_mcu_ADDR; + + /* SHP */ + sdma_script_addr->mxc_sdma_per_2_shp_addr = per_2_shp_ADDR; + sdma_script_addr->mxc_sdma_shp_2_per_addr = shp_2_per_ADDR; + sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR; + sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR; + + /* ATA */ + sdma_script_addr->mxc_sdma_mcu_2_ata_addr = mcu_2_ata_ADDR; + sdma_script_addr->mxc_sdma_ata_2_mcu_addr = ata_2_mcu_ADDR; + + /* app */ + sdma_script_addr->mxc_sdma_app_2_per_addr = app_2_per_ADDR; + sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_per_2_app_addr = per_2_app_ADDR; + sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR; + + /* MSHC */ + sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = -1; + + /* spdif */ + sdma_script_addr->mxc_sdma_spdif_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_spdif_addr = mcu_2_spdif_ADDR; + + /* IPU */ + sdma_script_addr->mxc_sdma_ext_mem_2_ipu_addr = ext_mem__ipu_ram_ADDR; + + /* DVFS */ + sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1; + + /* core */ + sdma_script_addr->mxc_sdma_start_addr = (unsigned short *)sdma_code; + sdma_script_addr->mxc_sdma_ram_code_start_addr = RAM_CODE_START_ADDR; + sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE; +} + +static void mxc_nop_release(struct device *dev) +{ + /* Nothing */ +} + +#if defined(CONFIG_W1_MASTER_MXC) || defined(CONFIG_W1_MASTER_MXC_MODULE) +static struct resource w1_resources[] = { + { + .start = MXC_INT_OWIRE, + .flags = IORESOURCE_IRQ, + } +}; + +static struct mxc_w1_config mxc_w1_data = { + .search_rom_accelerator = 1, +}; + +static struct platform_device mxc_w1_devices = { + .name = "mxc_w1", + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_w1_data, + }, + .num_resources = ARRAY_SIZE(w1_resources), + .resource = w1_resources, + .id = 0 +}; + +static void mxc_init_owire(void) +{ + (void)platform_device_register(&mxc_w1_devices); +} +#else +static inline void mxc_init_owire(void) +{ +} +#endif + +#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE) +static struct mxc_srtc_platform_data srtc_data = { + .srtc_sec_mode_addr = 0x83F98840, +}; + +static struct resource rtc_resources[] = { + { + .start = SRTC_BASE_ADDR, + .end = SRTC_BASE_ADDR + 0x40, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_SRTC_NTZ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct platform_device mxc_rtc_device = { + .name = "mxc_rtc", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &srtc_data, + }, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, +}; +static void mxc_init_rtc(void) +{ + (void)platform_device_register(&mxc_rtc_device); +} +#else +static inline void mxc_init_rtc(void) +{ +} +#endif + +#if defined(CONFIG_MXC_WATCHDOG) || defined(CONFIG_MXC_WATCHDOG_MODULE) + +static struct resource wdt_resources[] = { + { + .start = WDOG1_BASE_ADDR, + .end = WDOG1_BASE_ADDR + 0x30, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mxc_wdt_device = { + .name = "mxc_wdt", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(wdt_resources), + .resource = wdt_resources, +}; + +static void mxc_init_wdt(void) +{ + (void)platform_device_register(&mxc_wdt_device); +} +#else +static inline void mxc_init_wdt(void) +{ +} +#endif + +#if defined(CONFIG_MXC_IPU_V3) || defined(CONFIG_MXC_IPU_V3_MODULE) +static struct mxc_ipu_config mxc_ipu_data = { + .rev = 1, +}; + +static struct resource ipu_resources[] = { + { + .start = IPU_CTRL_BASE_ADDR, + .end = IPU_CTRL_BASE_ADDR + SZ_512M, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_IPU_SYN, + .flags = IORESOURCE_IRQ, + }, + { + .start = MXC_INT_IPU_ERR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxc_ipu_device = { + .name = "mxc_ipu", + .id = -1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_ipu_data, + }, + .num_resources = ARRAY_SIZE(ipu_resources), + .resource = ipu_resources, +}; + +static void mxc_init_ipu(void) +{ + u32 reg_hsc_mcd = IO_ADDRESS(MIPI_HSC_BASE_ADDR); + u32 reg_hsc_mxt_conf = IO_ADDRESS(MIPI_HSC_BASE_ADDR + 0x800); + struct clk *clk; + uint32_t temp; + + /* Select IPUv3 h/w version */ + if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0) + mxc_ipu_data.rev = 2; + + mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk"); + clk = clk_get(NULL, "tve_clk"); + clk_set_parent(mxc_ipu_data.di_clk[1], clk); + clk_put(clk); + + /* Temporarily setup MIPI module to legacy mode */ + clk = clk_get(NULL, "mipi_hsp_clk"); + if (!IS_ERR(clk)) { + clk_enable(clk); + + /* Temporarily setup MIPI module to legacy mode */ + __raw_writel(0xF00, reg_hsc_mcd); + + /* CSI mode reserved*/ + temp = __raw_readl(reg_hsc_mxt_conf); + __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf); + + if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0) { + temp = __raw_readl(reg_hsc_mxt_conf); + __raw_writel(temp | 0x10000, reg_hsc_mxt_conf); + } + + clk_disable(clk); + clk_put(clk); + } + platform_device_register(&mxc_ipu_device); +} +#else +static inline void mxc_init_ipu(void) +{ +} +#endif + +#if defined(CONFIG_MXC_VPU) || defined(CONFIG_MXC_VPU_MODULE) +static struct resource vpu_resources[] = { + { + .start = VPU_IRAM_BASE_ADDR, + .end = VPU_IRAM_BASE_ADDR + VPU_IRAM_SIZE, + .flags = IORESOURCE_MEM, + }, +}; + +/*! Platform Data for MXC VPU */ +static struct platform_device mxcvpu_device = { + .name = "mxc_vpu", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(vpu_resources), + .resource = vpu_resources, +}; + +static inline void mxc_init_vpu(void) +{ + if (platform_device_register(&mxcvpu_device) < 0) + printk(KERN_ERR "Error: Registering the VPU.\n"); +} +#else +static inline void mxc_init_vpu(void) +{ +} +#endif + +/*! + * This is platform device structure for adding SCC + */ +#if defined(CONFIG_MXC_SECURITY_SCC) || defined(CONFIG_MXC_SECURITY_SCC_MODULE) +static struct platform_device mxc_scc_device = { + .name = "mxc_scc", + .id = 0, +}; + +static void mxc_init_scc(void) +{ + platform_device_register(&mxc_scc_device); +} +#else +static inline void mxc_init_scc(void) +{ + uint32_t reg_value; + uint32_t reg_mask = 0; + uint8_t *UMID_base; + uint32_t *MAP_base; + uint8_t i; + uint32_t partition_no; + uint32_t scc_partno; + void *scm_ram_base; + void *scc_base; + uint8_t iram_partitions = 16; + + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) + iram_partitions = 12; + + scc_base = ioremap((uint32_t) SCC_BASE_ADDR, 0x140); + if (scc_base == NULL) { + printk(KERN_ERR "FAILED TO MAP IRAM REGS\n"); + return; + } + scm_ram_base = ioremap((uint32_t) IRAM_BASE_ADDR, IRAM_SIZE); + if (scm_ram_base == NULL) { + printk(KERN_ERR "FAILED TO MAP IRAM\n"); + return; + } + + for (partition_no = 0; partition_no < iram_partitions; partition_no++) { + /*De-allocate a Partition*/ + reg_value = ((partition_no << SCM_ZCMD_PART_SHIFT) & + SCM_ZCMD_PART_MASK) | ((0x03 << + SCM_ZCMD_CCMD_SHIFT) + & SCM_ZCMD_CCMD_MASK); + __raw_writel(reg_value, scc_base + SCM_ZCMD_REG); + msleep(1); + while ((__raw_readl(scc_base + SCM_STATUS_REG) & + SCM_STATUS_SRS_READY) != SCM_STATUS_SRS_READY) ; + + /*In Supervisor mode claims a partition for it's own use + by writing zero to SMID register.*/ + __raw_writel(0, scc_base + (SCM_SMID0_REG + 8 * partition_no)); + + reg_mask |= (3 << (2 * (partition_no))); + } + + msleep(1); + reg_value = __raw_readl(scc_base + SCM_PART_OWNERS_REG); + + if ((reg_value & reg_mask) != reg_mask) { + printk(KERN_ERR "FAILED TO ACQUIRE IRAM PARTITION\n"); + iounmap(scm_ram_base); + iounmap(scc_base); + return; + } + + for (partition_no = 0; partition_no < iram_partitions; partition_no++) { + MAP_base = scm_ram_base + (partition_no * 0x2000); + UMID_base = (uint8_t *) MAP_base + 0x10; + + for (i = 0; i < 16; i++) + UMID_base[i] = 0; + + MAP_base[0] = SCM_PERM_NO_ZEROIZE | SCM_PERM_HD_SUP_DISABLE | + SCM_PERM_HD_READ | SCM_PERM_HD_WRITE | + SCM_PERM_TH_READ | SCM_PERM_TH_WRITE; + + } + + /* Freeing 2 partitions for SCC2 */ + scc_partno = iram_partitions - (SCC_IRAM_SIZE / SZ_8K); + for (partition_no = scc_partno; partition_no < iram_partitions; + partition_no++) { + reg_value = ((partition_no << SCM_ZCMD_PART_SHIFT) & + SCM_ZCMD_PART_MASK) | ((0x03 << + SCM_ZCMD_CCMD_SHIFT) + & SCM_ZCMD_CCMD_MASK); + __raw_writel(reg_value, scc_base + SCM_ZCMD_REG); + msleep(1); + while ((__raw_readl(scc_base + SCM_STATUS_REG) & + SCM_STATUS_SRS_READY) != SCM_STATUS_SRS_READY) ; + } + iounmap(scm_ram_base); + iounmap(scc_base); + printk(KERN_INFO "IRAM READY\n"); + iram_ready = 1; +} +#endif + +/* SPI controller and device data */ +#if defined(CONFIG_SPI_MXC) || defined(CONFIG_SPI_MXC_MODULE) + +#ifdef CONFIG_SPI_MXC_SELECT1 +/*! + * Resource definition for the CSPI1 + */ +static struct resource mxcspi1_resources[] = { + [0] = { + .start = CSPI1_BASE_ADDR, + .end = CSPI1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_CSPI1, + .end = MXC_INT_CSPI1, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC CSPI1 */ +static struct mxc_spi_master mxcspi1_data = { + .maxchipselect = 4, + .spi_version = 23, +}; + +/*! Device Definition for MXC CSPI1 */ +static struct platform_device mxcspi1_device = { + .name = "mxc_spi", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxcspi1_data, + }, + .num_resources = ARRAY_SIZE(mxcspi1_resources), + .resource = mxcspi1_resources, +}; + +#endif /* CONFIG_SPI_MXC_SELECT1 */ + +#ifdef CONFIG_SPI_MXC_SELECT2 +/*! + * Resource definition for the CSPI2 + */ +static struct resource mxcspi2_resources[] = { + [0] = { + .start = CSPI2_BASE_ADDR, + .end = CSPI2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_CSPI2, + .end = MXC_INT_CSPI2, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC CSPI2 */ +static struct mxc_spi_master mxcspi2_data = { + .maxchipselect = 4, + .spi_version = 23, +}; + +/*! Device Definition for MXC CSPI2 */ +static struct platform_device mxcspi2_device = { + .name = "mxc_spi", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxcspi2_data, + }, + .num_resources = ARRAY_SIZE(mxcspi2_resources), + .resource = mxcspi2_resources, +}; +#endif /* CONFIG_SPI_MXC_SELECT2 */ + +#ifdef CONFIG_SPI_MXC_SELECT3 +/*! + * Resource definition for the CSPI3 + */ +static struct resource mxcspi3_resources[] = { + [0] = { + .start = CSPI3_BASE_ADDR, + .end = CSPI3_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_CSPI, + .end = MXC_INT_CSPI, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC CSPI3 */ +static struct mxc_spi_master mxcspi3_data = { + .maxchipselect = 4, + .spi_version = 7, +}; + +/*! Device Definition for MXC CSPI3 */ +static struct platform_device mxcspi3_device = { + .name = "mxc_spi", + .id = 2, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxcspi3_data, + }, + .num_resources = ARRAY_SIZE(mxcspi3_resources), + .resource = mxcspi3_resources, +}; +#endif /* CONFIG_SPI_MXC_SELECT3 */ + +void __init mxc_init_spi(void) +{ + /* SPBA configuration for CSPI2 - MCU is set */ + spba_take_ownership(SPBA_CSPI1, SPBA_MASTER_A); +#ifdef CONFIG_SPI_MXC_SELECT1 + if (platform_device_register(&mxcspi1_device) < 0) + printk(KERN_ERR "Error: Registering the SPI Controller_1\n"); +#endif /* CONFIG_SPI_MXC_SELECT1 */ +#ifdef CONFIG_SPI_MXC_SELECT2 + if (platform_device_register(&mxcspi2_device) < 0) + printk(KERN_ERR "Error: Registering the SPI Controller_2\n"); +#endif /* CONFIG_SPI_MXC_SELECT2 */ +#ifdef CONFIG_SPI_MXC_SELECT3 + if (platform_device_register(&mxcspi3_device) < 0) + printk(KERN_ERR "Error: Registering the SPI Controller_3\n"); +#endif /* CONFIG_SPI_MXC_SELECT3 */ +} +#else +void __init mxc_init_spi(void) +{ +} +#endif + +/* I2C controller and device data */ +#if defined(CONFIG_I2C_MXC) || defined(CONFIG_I2C_MXC_MODULE) + +#ifdef CONFIG_I2C_MXC_SELECT1 +/*! + * Resource definition for the I2C1 + */ +static struct resource mxci2c1_resources[] = { + [0] = { + .start = I2C1_BASE_ADDR, + .end = I2C1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_I2C1, + .end = MXC_INT_I2C1, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC I2C */ +static struct mxc_i2c_platform_data mxci2c1_data = { + .i2c_clk = 100000, +}; +#endif + +#ifdef CONFIG_I2C_MXC_SELECT2 +/*! + * Resource definition for the I2C2 + */ +static struct resource mxci2c2_resources[] = { + [0] = { + .start = I2C2_BASE_ADDR, + .end = I2C2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_I2C2, + .end = MXC_INT_I2C2, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC I2C */ +static struct mxc_i2c_platform_data mxci2c2_data = { + .i2c_clk = 100000, +}; +#endif + +#ifdef CONFIG_I2C_MXC_SELECT3 +/*! + * Resource definition for the I2C3 + */ +static struct resource mxci2c3_resources[] = { + [0] = { + .start = I2C3_BASE_ADDR, + .end = I2C3_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_I2C3, + .end = MXC_INT_I2C3, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC I2C */ +static struct mxc_i2c_platform_data mxci2c3_data = { + .i2c_clk = 100000, +}; +#endif + +/*! Device Definition for MXC I2C1 */ +static struct platform_device mxci2c_devices[] = { +#ifdef CONFIG_I2C_MXC_SELECT1 + { + .name = "mxc_i2c", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxci2c1_data, + }, + .num_resources = ARRAY_SIZE(mxci2c1_resources), + .resource = mxci2c1_resources,}, +#endif +#ifdef CONFIG_I2C_MXC_SELECT2 + { + .name = "mxc_i2c", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxci2c2_data, + }, + .num_resources = ARRAY_SIZE(mxci2c2_resources), + .resource = mxci2c2_resources,}, +#endif +#ifdef CONFIG_I2C_MXC_SELECT3 + { + .name = "mxc_i2c", + .id = 2, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxci2c3_data, + }, + .num_resources = ARRAY_SIZE(mxci2c3_resources), + .resource = mxci2c3_resources,}, +#endif +}; + +static inline void mxc_init_i2c(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mxci2c_devices); i++) { + if (platform_device_register(&mxci2c_devices[i]) < 0) + dev_err(&mxci2c_devices[i].dev, + "Unable to register I2C device\n"); + } +} +#else +static inline void mxc_init_i2c(void) +{ +} +#endif + +#if defined(CONFIG_I2C_MXC_HS) || defined(CONFIG_I2C_MXC_HS_MODULE) +static struct resource mxci2c_hs_resources[] = { + [0] = { + .start = HSI2C_DMA_BASE_ADDR, + .end = HSI2C_DMA_BASE_ADDR + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_HS_I2C, + .end = MXC_INT_HS_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for MXC I2C */ +static struct mxc_i2c_platform_data mxci2c_hs_data = { + .i2c_clk = 400000, +}; + +static struct platform_device mxci2c_hs_device = { + .name = "mxc_i2c_hs", + .id = 3, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxci2c_hs_data, + }, + .num_resources = ARRAY_SIZE(mxci2c_hs_resources), + .resource = mxci2c_hs_resources +}; + +static inline void mxc_init_i2c_hs(void) +{ + if (platform_device_register(&mxci2c_hs_device) < 0) + dev_err(&mxci2c_hs_device.dev, + "Unable to register High Speed I2C device\n"); +} +#else +static inline void mxc_init_i2c_hs(void) +{ +} +#endif + +#if defined(CONFIG_FB_MXC_TVOUT_TVE) || defined(CONFIG_FB_MXC_TVOUT_TVE_MODULE) +static struct resource tve_resources[] = { + { + .start = TVE_BASE_ADDR, + .end = TVE_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_TVE, + .flags = IORESOURCE_IRQ, + }, +}; +static struct tve_platform_data tve_data = { + .dac_reg = "VVIDEO", + .dig_reg = "VDIG", +}; + +static struct platform_device mxc_tve_device = { + .name = "tve", + .dev = { + .platform_data = &tve_data, + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(tve_resources), + .resource = tve_resources, +}; + +void __init mxc_init_tve(void) +{ + platform_device_register(&mxc_tve_device); +} +#else +static inline void mxc_init_tve(void) +{ +} +#endif + +/*! + * Resource definition for the DVFS CORE + */ +static struct resource dvfs_core_resources[] = { + [0] = { + .start = MXC_DVFS_CORE_BASE, + .end = MXC_DVFS_CORE_BASE + 4 * SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_GPC1, + .end = MXC_INT_GPC1, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Platform Data for DVFS CORE */ +struct mxc_dvfs_platform_data dvfs_core_data = { + .reg_id = "SW1", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_reg_addr = MXC_GPC_CNTR, + .gpc_vcr_reg_addr = MXC_GPC_VCR, + .dvfs_thrs_reg_addr = MXC_DVFSTHRS, + .dvfs_coun_reg_addr = MXC_DVFSCOUN, + .dvfs_emac_reg_addr = MXC_DVFSEMAC, + .dvfs_cntr_reg_addr = MXC_DVFSCNTR, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x10, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 3, + .dncnt_val = 3, + .delay_time = 30, + .num_wp = 2, +}; + +/*! Device Definition for MXC DVFS core */ +static struct platform_device mxc_dvfs_core_device = { + .name = "mxc_dvfs_core", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &dvfs_core_data, + }, + .num_resources = ARRAY_SIZE(dvfs_core_resources), + .resource = dvfs_core_resources, +}; + +static inline void mxc_init_dvfs(void) +{ + if (platform_device_register(&mxc_dvfs_core_device) < 0) + dev_err(&mxc_dvfs_core_device.dev, + "Unable to register DVFS core device\n"); +} + +struct mxc_gpio_port mxc_gpio_ports[GPIO_PORT_NUM] = { + { + .num = 0, + .base = IO_ADDRESS(GPIO1_BASE_ADDR), + .irq_0_15 = MXC_INT_GPIO1_LOW, + .irq_16_31 = MXC_INT_GPIO1_HIGH, + .virtual_irq_start = MXC_GPIO_INT_BASE, + }, + { + .num = 1, + .base = IO_ADDRESS(GPIO2_BASE_ADDR), + .irq_0_15 = MXC_INT_GPIO2_LOW, + .irq_16_31 = MXC_INT_GPIO2_HIGH, + .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 1, + }, + { + .num = 2, + .base = IO_ADDRESS(GPIO3_BASE_ADDR), + .irq_0_15 = MXC_INT_GPIO3_LOW, + .irq_16_31 = MXC_INT_GPIO3_HIGH, + .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 2, + }, + { + .num = 3, + .base = IO_ADDRESS(GPIO4_BASE_ADDR), + .irq_0_15 = MXC_INT_GPIO4_LOW, + .irq_16_31 = MXC_INT_GPIO4_HIGH, + .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 3, + }, +}; + +static struct platform_device mxc_dma_device = { + .name = "mxc_dma", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, +}; + +static inline void mxc_init_dma(void) +{ + (void)platform_device_register(&mxc_dma_device); +} + +static struct resource spdif_resources[] = { + { + .start = SPDIF_BASE_ADDR, + .end = SPDIF_BASE_ADDR + 0x50, + .flags = IORESOURCE_MEM, + }, +}; + +static struct mxc_spdif_platform_data mxc_spdif_data = { + .spdif_tx = 1, + .spdif_rx = 0, + .spdif_clk_44100 = 0, /* spdif_ext_clk source for 44.1KHz */ + .spdif_clk_48000 = 7, /* audio osc source */ + .spdif_clkid = 0, + .spdif_clk = NULL, /* spdif bus clk */ +}; + +static struct platform_device mxc_alsa_spdif_device = { + .name = "mxc_alsa_spdif", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_spdif_data, + }, + .num_resources = ARRAY_SIZE(spdif_resources), + .resource = spdif_resources, +}; + +static inline void mxc_init_spdif(void) +{ + mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk"); + clk_put(mxc_spdif_data.spdif_core_clk); + platform_device_register(&mxc_alsa_spdif_device); +} + +static struct platform_device mx51_lpmode_device = { + .name = "mx51_lpmode", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, +}; + +static inline void mx51_init_lpmode(void) +{ + (void)platform_device_register(&mx51_lpmode_device); +} + +int __init mxc_init_devices(void) +{ + mxc_init_wdt(); + mxc_init_spi(); + mxc_init_i2c(); + mxc_init_i2c_hs(); + mxc_init_rtc(); + mxc_init_scc(); + mxc_init_dma(); + mxc_init_owire(); + mxc_init_ipu(); + mxc_init_vpu(); + mxc_init_spdif(); + mxc_init_tve(); + mx51_init_lpmode(); + mxc_init_dvfs(); + return 0; +} diff -urN linux-2.6.26/arch/arm/mach-mx51/dma.c linux-2.6.26-lab126/arch/arm/mach-mx51/dma.c --- linux-2.6.26/arch/arm/mach-mx51/dma.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/dma.c 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,666 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include + +#include "serial.h" + +#define MXC_MMC_BUFFER_ACCESS 0x20 +#define MXC_SDHC_MMC_WML 64 +#define MXC_SDHC_SD_WML 256 +#define MXC_SSI_TX0_REG 0x0 +#define MXC_SSI_TX1_REG 0x4 +#define MXC_SSI_RX0_REG 0x8 +#define MXC_SSI_RX1_REG 0xC +#define MXC_SSI_TXFIFO_WML 0x4 +#define MXC_SSI_RXFIFO_WML 0x6 +#define MXC_SPDIF_TXFIFO_WML 0x8 +#define MXC_SPDIF_TX_REG 0x2C + +typedef struct mxc_sdma_info_entry_s { + mxc_dma_device_t device; + mxc_sdma_channel_params_t *chnl_info; +} mxc_sdma_info_entry_t; + +static mxc_sdma_channel_params_t mxc_sdma_uart1_rx_params = { + .chnl_params = { + .watermark_level = UART1_UFCR_RXTL, + .per_address = UART1_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART1_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART1_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart1_tx_params = { + .chnl_params = { + .watermark_level = UART1_UFCR_TXTL, + .per_address = UART1_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART1_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART1_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart2_rx_params = { + .chnl_params = { + .watermark_level = UART2_UFCR_RXTL, + .per_address = UART2_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART2_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART2_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart2_tx_params = { + .chnl_params = { + .watermark_level = UART2_UFCR_TXTL, + .per_address = UART2_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART2_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART2_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart3_rx_params = { + .chnl_params = { + .watermark_level = UART3_UFCR_RXTL, + .per_address = UART3_BASE_ADDR, + .peripheral_type = UART_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART3_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART3_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart3_tx_params = { + .chnl_params = { + .watermark_level = UART3_UFCR_TXTL, + .per_address = UART3_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART3_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART3_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc1_width1_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_MMC_WML, + .per_address = + MMC_SDHC1_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SDHC1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MMC1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc1_width4_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_SD_WML, + .per_address = + MMC_SDHC1_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SDHC1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MMC1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc2_width1_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_MMC_WML, + .per_address = + MMC_SDHC2_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SDHC2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MMC2, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc2_width4_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_SD_WML, + .per_address = + MMC_SDHC2_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SDHC2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MMC2, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_memory_params = { + .chnl_params = { + .peripheral_type = MEMORY, + .transfer_type = emi_2_emi, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MEMORY, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ata_rx_params = { + .chnl_params = { + .watermark_level = MXC_IDE_DMA_WATERMARK, + .per_address = ATA_DMA_BASE_ADDR, + .peripheral_type = ATA, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ATA_TX_END, + .event_id2 = DMA_REQ_ATA_RX, + .bd_number = MXC_IDE_DMA_BD_NR, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ATA_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ata_tx_params = { + .chnl_params = { + .watermark_level = MXC_IDE_DMA_WATERMARK, + .per_address = ATA_DMA_BASE_ADDR + 0x18, + .peripheral_type = ATA, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_ATA_TX_END, + .event_id2 = DMA_REQ_ATA_TX, + .bd_number = MXC_IDE_DMA_BD_NR, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ATA_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_spdif_16bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_SPDIF_TXFIFO_WML, + .per_address = SPDIF_BASE_ADDR + MXC_SPDIF_TX_REG, + .peripheral_type = SPDIF, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SPDIF, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SPDIF_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_spdif_32bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_SPDIF_TXFIFO_WML, + .per_address = SPDIF_BASE_ADDR + MXC_SPDIF_TX_REG, + .peripheral_type = SPDIF, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SPDIF, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SPDIF_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_info_entry_t mxc_sdma_active_dma_info[] = { + {MXC_DMA_UART1_RX, &mxc_sdma_uart1_rx_params}, + {MXC_DMA_UART1_TX, &mxc_sdma_uart1_tx_params}, + {MXC_DMA_UART2_RX, &mxc_sdma_uart2_rx_params}, + {MXC_DMA_UART2_TX, &mxc_sdma_uart2_tx_params}, + {MXC_DMA_UART3_RX, &mxc_sdma_uart3_rx_params}, + {MXC_DMA_UART3_TX, &mxc_sdma_uart3_tx_params}, + {MXC_DMA_MMC1_WIDTH_1, &mxc_sdma_mmc1_width1_params}, + {MXC_DMA_MMC1_WIDTH_4, &mxc_sdma_mmc1_width4_params}, + {MXC_DMA_MMC2_WIDTH_1, &mxc_sdma_mmc2_width1_params}, + {MXC_DMA_MMC2_WIDTH_4, &mxc_sdma_mmc2_width4_params}, + {MXC_DMA_SSI1_8BIT_RX0, &mxc_sdma_ssi1_8bit_rx0_params}, + {MXC_DMA_SSI1_8BIT_TX0, &mxc_sdma_ssi1_8bit_tx0_params}, + {MXC_DMA_SSI1_16BIT_RX0, &mxc_sdma_ssi1_16bit_rx0_params}, + {MXC_DMA_SSI1_16BIT_TX0, &mxc_sdma_ssi1_16bit_tx0_params}, + {MXC_DMA_SSI1_24BIT_RX0, &mxc_sdma_ssi1_24bit_rx0_params}, + {MXC_DMA_SSI1_24BIT_TX0, &mxc_sdma_ssi1_24bit_tx0_params}, + {MXC_DMA_SSI1_8BIT_RX1, &mxc_sdma_ssi1_8bit_rx1_params}, + {MXC_DMA_SSI1_8BIT_TX1, &mxc_sdma_ssi1_8bit_tx1_params}, + {MXC_DMA_SSI1_16BIT_RX1, &mxc_sdma_ssi1_16bit_rx1_params}, + {MXC_DMA_SSI1_16BIT_TX1, &mxc_sdma_ssi1_16bit_tx1_params}, + {MXC_DMA_SSI1_24BIT_RX1, &mxc_sdma_ssi1_24bit_rx1_params}, + {MXC_DMA_SSI1_24BIT_TX1, &mxc_sdma_ssi1_24bit_tx1_params}, + {MXC_DMA_SSI2_8BIT_RX0, &mxc_sdma_ssi2_8bit_rx0_params}, + {MXC_DMA_SSI2_8BIT_TX0, &mxc_sdma_ssi2_8bit_tx0_params}, + {MXC_DMA_SSI2_16BIT_RX0, &mxc_sdma_ssi2_16bit_rx0_params}, + {MXC_DMA_SSI2_16BIT_TX0, &mxc_sdma_ssi2_16bit_tx0_params}, + {MXC_DMA_SSI2_24BIT_RX0, &mxc_sdma_ssi2_24bit_rx0_params}, + {MXC_DMA_SSI2_24BIT_TX0, &mxc_sdma_ssi2_24bit_tx0_params}, + {MXC_DMA_SSI2_8BIT_RX1, &mxc_sdma_ssi2_8bit_rx1_params}, + {MXC_DMA_SSI2_8BIT_TX1, &mxc_sdma_ssi2_8bit_tx1_params}, + {MXC_DMA_SSI2_16BIT_RX1, &mxc_sdma_ssi2_16bit_rx1_params}, + {MXC_DMA_SSI2_16BIT_TX1, &mxc_sdma_ssi2_16bit_tx1_params}, + {MXC_DMA_SSI2_24BIT_RX1, &mxc_sdma_ssi2_24bit_rx1_params}, + {MXC_DMA_SSI2_24BIT_TX1, &mxc_sdma_ssi2_24bit_tx1_params}, + {MXC_DMA_MEMORY, &mxc_sdma_memory_params}, + {MXC_DMA_ATA_RX, &mxc_sdma_ata_rx_params}, + {MXC_DMA_ATA_TX, &mxc_sdma_ata_tx_params}, + {MXC_DMA_SPDIF_16BIT_TX, &mxc_sdma_spdif_16bit_tx_params}, + {MXC_DMA_SPDIF_32BIT_TX, &mxc_sdma_spdif_32bit_tx_params}, +}; + +static int mxc_sdma_info_entrys = + sizeof(mxc_sdma_active_dma_info) / sizeof(mxc_sdma_active_dma_info[0]); + +/*! + * This functions Returns the SDMA paramaters associated for a module + * + * @param channel_id the ID of the module requesting DMA + * @return returns the sdma parameters structure for the device + */ +mxc_sdma_channel_params_t *mxc_sdma_get_channel_params(mxc_dma_device_t + channel_id) +{ + mxc_sdma_info_entry_t *p = mxc_sdma_active_dma_info; + int i; + + for (i = 0; i < mxc_sdma_info_entrys; i++, p++) { + if (p->device == channel_id) + return p->chnl_info; + + } + return NULL; +} + +/*! + * This functions marks the SDMA channels that are statically allocated + * + * @param chnl the channel array used to store channel information + */ +void mxc_get_static_channels(mxc_dma_channel_t *chnl) +{ +#ifdef CONFIG_SDMA_IRAM + int i; + for (i = MXC_DMA_CHANNEL_IRAM; i < MAX_DMA_CHANNELS; i++) + chnl[i].dynamic = 0; +#endif +} + +EXPORT_SYMBOL(mxc_sdma_get_channel_params); +EXPORT_SYMBOL(mxc_get_static_channels); diff -urN linux-2.6.26/arch/arm/mach-mx51/iomux.c linux-2.6.26-lab126/arch/arm/mach-mx51/iomux.c --- linux-2.6.26/arch/arm/mach-mx51/iomux.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/iomux.c 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,248 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup GPIO_MX51 Board GPIO and Muxing Setup + * @ingroup MSL_MX51 + */ +/*! + * @file mach-mx51/iomux.c + * + * @brief I/O Muxing control functions + * + * @ingroup GPIO_MX51 + */ + +#include +#include +#include +#include +#include "iomux.h" + +/*! + * IOMUX register (base) addresses + */ +enum iomux_reg_addr { + IOMUXGPR0 = IO_ADDRESS(IOMUXC_BASE_ADDR), + IOMUXGPR1 = IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x004, + IOMUXSW_MUX_CTL = IO_ADDRESS(IOMUXC_BASE_ADDR), + IOMUXSW_MUX_END = IO_ADDRESS(IOMUXC_BASE_ADDR) + MUX_I_END, + IOMUXSW_PAD_CTL = IO_ADDRESS(IOMUXC_BASE_ADDR) + PAD_I_START, + IOMUXSW_INPUT_CTL = IO_ADDRESS(IOMUXC_BASE_ADDR), +}; + +#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1) + +static u8 iomux_pin_res_table[MUX_PIN_NUM_MAX]; +static DEFINE_SPINLOCK(gpio_mux_lock); + +static inline u32 _get_mux_reg(iomux_pin_name_t pin) +{ + u32 mux_reg = PIN_TO_IOMUX_MUX(pin); + + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) { + if ((pin == MX51_PIN_NANDF_RB5) || + (pin == MX51_PIN_NANDF_RB6) || + (pin == MX51_PIN_NANDF_RB7)) + ; /* Do nothing */ + else if (mux_reg >= 0x2FC) + mux_reg += 8; + else if (mux_reg >= 0x130) + mux_reg += 0xC; + } + mux_reg += IOMUXSW_MUX_CTL; + return mux_reg; +} + +static inline u32 _get_pad_reg(iomux_pin_name_t pin) +{ + u32 pad_reg = PIN_TO_IOMUX_PAD(pin); + + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) { + if ((pin == MX51_PIN_NANDF_RB5) || + (pin == MX51_PIN_NANDF_RB6) || + (pin == MX51_PIN_NANDF_RB7)) + ; /* Do nothing */ + else if (pad_reg == 0x4D0 - PAD_I_START) + pad_reg += 0x4C; + else if (pad_reg == 0x860 - PAD_I_START) + pad_reg += 0x9C; + else if (pad_reg >= 0x804 - PAD_I_START) + pad_reg += 0xB0; + else if (pad_reg >= 0x7FC - PAD_I_START) + pad_reg += 0xB4; + else if (pad_reg >= 0x4E4 - PAD_I_START) + pad_reg += 0xCC; + else + pad_reg += 8; + } + pad_reg += IOMUXSW_PAD_CTL; + return pad_reg; +} + +static inline u32 _get_mux_end() +{ + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) + return(IO_ADDRESS(IOMUXC_BASE_ADDR) + (0x3F8 - 4)); + else + return(IO_ADDRESS(IOMUXC_BASE_ADDR) + (0x3F0 - 4)); +} + +/*! + * This function is used to configure a pin through the IOMUX module. + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config a configuration as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t config) +{ + u32 ret = 0; + u32 pin_index = PIN_TO_IOMUX_INDEX(pin); + u32 mux_reg = _get_mux_reg(pin); + u32 mux_data = 0; + u8 *rp; + + BUG_ON((mux_reg > _get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL)); + spin_lock(&gpio_mux_lock); + + if (config == IOMUX_CONFIG_GPIO) + mux_data = PIN_TO_ALT_GPIO(pin); + else + mux_data = config; + + __raw_writel(mux_data, mux_reg); + + /* + * Log a warning if a pin changes ownership + */ + rp = iomux_pin_res_table + pin_index; + if ((mux_data & *rp) && (*rp != mux_data)) { + /* + * Don't call printk if we're tweaking the console uart or + * we'll deadlock. + */ + printk(KERN_ERR "iomux_config_mux: Warning: iomux pin" + " config changed, pin=%d, " + " prev=0x%x new=0x%x\n", mux_reg, *rp, mux_data); + ret = -EINVAL; + } + *rp = mux_data; + spin_unlock(&gpio_mux_lock); + return ret; +} + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param config a configuration as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config) +{ + int ret = iomux_config_mux(pin, config); + int gpio_port = GPIO_TO_PORT(IOMUX_TO_GPIO(pin)); + + if (!ret && (gpio_port != NON_GPIO_PORT) + && ((config == IOMUX_CONFIG_GPIO) + || (config == PIN_TO_ALT_GPIO(pin)))) + ret |= mxc_request_gpio(pin); + + return ret; +} +EXPORT_SYMBOL(mxc_request_iomux); + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param config config as defined in \b #iomux_pin_ocfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config) +{ + u32 pin_index = PIN_TO_IOMUX_INDEX(pin); + u8 *rp = iomux_pin_res_table + pin_index; + int gpio_port = GPIO_TO_PORT(IOMUX_TO_GPIO(pin)); + + *rp = 0; + if ((gpio_port != NON_GPIO_PORT) + && ((config == IOMUX_CONFIG_GPIO) + || (config == PIN_TO_ALT_GPIO(pin)))) + mxc_free_gpio(pin); + +} +EXPORT_SYMBOL(mxc_free_iomux); + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) +{ + u32 pad_reg = _get_pad_reg(pin); + + BUG_ON(pad_reg < IOMUXSW_PAD_CTL); + __raw_writel(config, pad_reg); +} +EXPORT_SYMBOL(mxc_iomux_set_pad); + +unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin) +{ + u32 pad_reg = _get_pad_reg(pin); + + return __raw_readl(pad_reg); +} +EXPORT_SYMBOL(mxc_iomux_get_pad); + +/*! + * This function configures input path. + * + * @param input index of input select register as defined in \b #iomux_input_select_t + * @param config the binary value of elements defined in \b #iomux_input_config_t + * */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config) +{ + u32 reg = IOMUXSW_INPUT_CTL + (input << 2); + + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) { + if (input == MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT) + input -= 4; + else if (input == MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT) + input -= 3; + else if (input >= MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT) + input -= 2; + else if (input >= MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT) + input -= 5; + else if (input >= MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT) + input -= 3; + else if (input >= MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT) + input -= 2; + else if (input >= MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT) + input -= 1; + + reg += INPUT_CTL_START_TO1; + } else { + reg += INPUT_CTL_START; + } + + + BUG_ON(input >= MUX_INPUT_NUM_MUX); + __raw_writel(config, reg); +} +EXPORT_SYMBOL(mxc_iomux_set_input); diff -urN linux-2.6.26/arch/arm/mach-mx51/iomux.h linux-2.6.26-lab126/arch/arm/mach-mx51/iomux.h --- linux-2.6.26/arch/arm/mach-mx51/iomux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/iomux.h 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,236 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MACH_MX51_IOMUX_H__ +#define __MACH_MX51_IOMUX_H__ + +#include +#include +#include "mx51_pins.h" + +/*! + * @file mach-mx51/iomux.h + * + * @brief I/O Muxing control definitions and functions + * + * @ingroup GPIO_MX51 + */ + +/*! + * various IOMUX output functions + */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */ + IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */ + IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */ + IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */ + IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */ + IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */ + IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */ + IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */ + IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +/*! + * various IOMUX pad functions + */ +typedef enum iomux_pad_config { + PAD_CTL_SRE_SLOW = 0x0 << 0, + PAD_CTL_SRE_FAST = 0x1 << 0, + PAD_CTL_DRV_LOW = 0x0 << 1, + PAD_CTL_DRV_MEDIUM = 0x1 << 1, + PAD_CTL_DRV_HIGH = 0x2 << 1, + PAD_CTL_DRV_MAX = 0x3 << 1, + PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, + PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3, + PAD_CTL_100K_PD = 0x0 << 4, + PAD_CTL_47K_PU = 0x1 << 4, + PAD_CTL_100K_PU = 0x2 << 4, + PAD_CTL_22K_PU = 0x3 << 4, + PAD_CTL_PUE_KEEPER = 0x0 << 6, + PAD_CTL_PUE_PULL = 0x1 << 6, + PAD_CTL_PKE_NONE = 0x0 << 7, + PAD_CTL_PKE_ENABLE = 0x1 << 7, + PAD_CTL_HYS_NONE = 0x0 << 8, + PAD_CTL_HYS_ENABLE = 0x1 << 8, + PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9, + PAD_CTL_DDR_INPUT_DDR = 0x1 << 9, + PAD_CTL_DRV_VOT_LOW = 0x0 << 13, + PAD_CTL_DRV_VOT_HIGH = 0x1 << 13, +} iomux_pad_config_t; + +/*! + * various IOMUX input select register index + */ +typedef enum iomux_input_select { + MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, + MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, + MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT, + MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT, + /* TO2 */ + MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, + MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT, + /* TO2 */ + MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, + MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT, + MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT, + MUX_IN_FEC_FEC_COL_SELECT_INPUT, + MUX_IN_FEC_FEC_CRS_SELECT_INPUT, + MUX_IN_FEC_FEC_MDI_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, + MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT, + /* TO2 */ + MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT, + MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT, + MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT, + /* TO2 */ + MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT, + /* TO2 */ + MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT, + MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT, + MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, + MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, + MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, + MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, + + MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT, + + MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT, + + MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT, + MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT, + MUX_INPUT_NUM_MUX, +} iomux_input_select_t; + +/*! + * various IOMUX input functions + */ +typedef enum iomux_input_config { + INPUT_CTL_PATH0 = 0x0, + INPUT_CTL_PATH1, + INPUT_CTL_PATH2, + INPUT_CTL_PATH3, + INPUT_CTL_PATH4, + INPUT_CTL_PATH5, + INPUT_CTL_PATH6, + INPUT_CTL_PATH7, +} iomux_input_config_t; + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param config config as defined in \b #iomux_pin_ocfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param config config as defined in \b #iomux_pin_ocfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in + * \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); + +/*! + * This function gets the current pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @return current pad value + */ +unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin); + +/*! + * This function configures input path. + * + * @param input index of input select register as defined in + * \b #iomux_input_select_t + * @param config the binary value of elements defined in \b #iomux_input_config_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config); + +#endif /* __MACH_MX51_IOMUX_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx51/lpmodes.c linux-2.6.26-lab126/arch/arm/mach-mx51/lpmodes.c --- linux-2.6.26/arch/arm/mach-mx51/lpmodes.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/lpmodes.c 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,204 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mx51_lpmodes.c + * + * @brief Driver for the Freescale Semiconductor MXC low power modes setup. + * + * MX51 is designed to play and video with minimal power consumption. + * This driver enables the platform to enter and exit audio and video low + * power modes. + * + * @ingroup PM + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "crm_regs.h" + +#define ARM_LP_CLK 200000000 +#define GP_LPM_VOLTAGE 775000 +#define GP_NORMAL_VOLTAGE 1050000 + +static int org_cpu_rate; +int lp_video_mode; +int lp_audio_mode; +static struct device *lpmode_dev; +struct regulator *gp_core; + +void enter_lp_video_mode(void) +{ +} + +void exit_lp_video_mode(void) +{ +} + +void enter_lp_audio_mode(void) +{ + struct clk *tclk; + int ret; + + tclk = clk_get(NULL, "cpu_clk"); + org_cpu_rate = clk_get_rate(tclk); + + ret = clk_set_rate(tclk, ARM_LP_CLK); + if (ret != 0) + printk(KERN_DEBUG "cannot set CPU clock rate\n"); + clk_put(tclk); + + /* Set the voltage to 0.775v for the GP domain. */ + ret = regulator_set_voltage(gp_core, GP_LPM_VOLTAGE); + if (ret < 0) + printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!\n"); + + lp_audio_mode = 1; +} + +void exit_lp_audio_mode(void) +{ + struct clk *tclk; + int ret; + + /* Set the voltage to 1.05v for the GP domain. */ + ret = regulator_set_voltage(gp_core, GP_NORMAL_VOLTAGE); + if (ret < 0) + printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!\n"); + + tclk = clk_get(NULL, "cpu_clk"); + ret = clk_set_rate(tclk, org_cpu_rate); + if (ret != 0) + printk(KERN_DEBUG "cannot set CPU clock rate\n"); + clk_put(tclk); + + lp_audio_mode = 0; + +} + +static ssize_t lp_curr_mode(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (lp_video_mode) + return sprintf(buf, "in lp_video_mode\n"); + else if (lp_audio_mode) + return sprintf(buf, "in lp_audio_mode\n"); + else + return sprintf(buf, "in normal mode\n"); +} + +static ssize_t set_lp_mode(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + printk(KERN_DEBUG "In set_lp_mode() \n"); + + if (strstr(buf, "enable_lp_video") != NULL) { + if (!lp_video_mode) + enter_lp_video_mode(); + } else if (strstr(buf, "disable_lp_video") != NULL) { + if (lp_video_mode) + exit_lp_video_mode(); + } else if (strstr(buf, "enable_lp_audio") != NULL) { + if (!lp_audio_mode) + enter_lp_audio_mode(); + } else if (strstr(buf, "disable_lp_audio") != NULL) { + if (lp_audio_mode) + exit_lp_audio_mode(); + } + return size; +} + +static DEVICE_ATTR(lp_modes, 0644, lp_curr_mode, set_lp_mode); + +/*! + * This is the probe routine for the lp_mode driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + * + */ +static int __devinit mx51_lpmode_probe(struct platform_device *pdev) +{ + u32 res = 0; + lpmode_dev = &pdev->dev; + + res = sysfs_create_file(&lpmode_dev->kobj, &dev_attr_lp_modes.attr); + if (res) { + printk(KERN_ERR + "lpmode_dev: Unable to register sysdev entry for lpmode_dev"); + return res; + } + + if (res != 0) { + printk(KERN_ERR "lpmode_dev: Unable to start"); + return res; + } + gp_core = regulator_get(NULL, "SW1"); + lp_video_mode = 0; + lp_audio_mode = 0; + + return 0; +} + +static struct platform_driver mx51_lpmode_driver = { + .driver = { + .name = "mx51_lpmode", + }, + .probe = mx51_lpmode_probe, +}; + +/*! + * Initialise the mx51_lpmode_driver. + * + * @return The function always returns 0. + */ + +static int __init lpmode_init(void) +{ + if (platform_driver_register(&mx51_lpmode_driver) != 0) { + printk(KERN_ERR "mx37_lpmode_driver register failed\n"); + return -ENODEV; + } + + printk(KERN_INFO "LPMode driver module loaded\n"); + return 0; +} + +static void __exit lpmode_cleanup(void) +{ + sysfs_remove_file(&lpmode_dev->kobj, &dev_attr_lp_modes.attr); + + /* Unregister the device structure */ + platform_driver_unregister(&mx51_lpmode_driver); +} + +module_init(lpmode_init); +module_exit(lpmode_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("LPMode driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/mach-mx51/mm.c linux-2.6.26-lab126/arch/arm/mach-mx51/mm.c --- linux-2.6.26/arch/arm/mach-mx51/mm.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/mm.c 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,84 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include + +/*! + * @file mach-mx51/mm.c + * + * @brief This file creates static mapping between physical to virtual memory. + * + * @ingroup Memory_MX51 + */ + +/*! + * This structure defines the MX51 memory map. + */ +static struct map_desc mxc_io_desc[] __initdata = { + { + .virtual = IRAM_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(IRAM_BASE_ADDR), + .length = IRAM_SIZE, + .type = MT_DEVICE}, + { + .virtual = DEBUG_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(DEBUG_BASE_ADDR), + .length = DEBUG_SIZE, + .type = MT_DEVICE}, + { + .virtual = TZIC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(TZIC_BASE_ADDR), + .length = TZIC_SIZE, + .type = MT_DEVICE}, + { + .virtual = AIPS1_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), + .length = AIPS1_SIZE, + .type = MT_DEVICE}, + { + .virtual = SPBA0_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), + .length = SPBA0_SIZE, + .type = MT_DEVICE}, + { + .virtual = AIPS2_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), + .length = AIPS2_SIZE, + .type = MT_DEVICE}, + { + .virtual = NFC_BASE_ADDR_AXI_VIRT, + .pfn = __phys_to_pfn(NFC_BASE_ADDR_AXI), + .length = NFC_AXI_SIZE, + .type = MT_DEVICE}, +}; + +/*! + * This function initializes the memory map. It is called during the + * system startup to create static physical to virtual memory map for + * the IO modules. + */ +void __init mxc_map_io(void) +{ + u32 tzic_addr; + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) + tzic_addr = 0x8FFFC000; + else + tzic_addr = 0xE0003000; + + mxc_io_desc[2].pfn = __phys_to_pfn(tzic_addr); + iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); +} diff -urN linux-2.6.26/arch/arm/mach-mx51/mx51_3stack.c linux-2.6.26-lab126/arch/arm/mach-mx51/mx51_3stack.c --- linux-2.6.26/arch/arm/mach-mx51/mx51_3stack.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/mx51_3stack.c 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,1207 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE) +#include +#include +#include + +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "board-mx51_3stack.h" +#include "iomux.h" +#include "crm_regs.h" + +/*! + * @file mach-mx51/mx51_3stack.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX51 + */ +extern void mxc_map_io(void); +extern void mxc_init_irq(void); +extern void mxc_cpu_init(void) __init; +extern struct sys_timer mxc_timer; +extern void mxc_cpu_common_init(void); +extern int mxc_clocks_init(void); +extern void __init early_console_setup(char *); +extern int mxc_init_devices(void); + +/* working point(wp): 0 - 800MHz; 1 - 200MHz; */ +static struct cpu_wp cpu_wp_auto[] = { + { + .pll_rate = 800000000, + .cpu_rate = 800000000, + .pdf = 0, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 0, + .cpu_voltage = 1050000,}, + { + .pll_rate = 800000000, + .cpu_rate = 200000000, + .pdf = 3, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 3, + .cpu_voltage = 775000,}, +}; + +struct cpu_wp *get_cpu_wp(int *wp) +{ + *wp = 2; + return cpu_wp_auto; +} + +/*! + * the event handler for power on event + */ +static void power_on_evt_handler(void) +{ + pr_info("pwr on event1 is received \n"); +} + +static int __init mc13892_reg_int(void) +{ + int i = 0; + unsigned int value; + struct regulator *regulator; + struct regulator *gp; + struct regulator *lp; + char *reg_name[] = { + "SW1", + "SW2", + "SW3", + "SW4", + "SW1_STBY", + "SW2_STBY", + "SW3_STBY", + "SW4_STBY", + "SW1_DVS", + "SW2_DVS", + "SWBST", + "VIOHI", + "VPLL", + "VDIG", + "VSD", + "VUSB2", + "VVIDEO", + "VAUDIO", + "VCAM", + "VGEN1", + "VGEN2", + "VGEN3", + "USB", + "GPO1", + "GPO2", + "GPO3", + "GPO4", + }; + pmic_event_callback_t power_key_event; + + for (i = 0; i < ARRAY_SIZE(reg_name); i++) { + regulator = regulator_get(NULL, reg_name[i]); + if (regulator != ERR_PTR(-ENOENT)) { + regulator_enable(regulator); + regulator_put(regulator, NULL); + } + } + for (i = 0; i < ARRAY_SIZE(reg_name); i++) { + if ((strcmp(reg_name[i], "VIOHI") == 0) || + (strcmp(reg_name[i], "VPLL") == 0) || + (strcmp(reg_name[i], "VDIG") == 0) || + (strcmp(reg_name[i], "VGEN2") == 0)) + continue; + regulator = regulator_get(NULL, reg_name[i]); + if (regulator != ERR_PTR(-ENOENT)) { + regulator_disable(regulator); + regulator_put(regulator, NULL); + } + } + + gp = regulator_get(NULL, "SW1_STBY"); + lp = regulator_get(NULL, "SW2_STBY"); + if (gp != NULL) { + regulator_enable(gp); + if (regulator_set_voltage(gp, 700000)) + printk(KERN_INFO "cannot set GP STBY voltage\n"); + regulator_disable(gp); + regulator_put(gp, NULL); + } + + if (lp != NULL) { + regulator_enable(lp); + if ((mxc_cpu_is_rev(CHIP_REV_2_0)) < 0) { + if (regulator_set_voltage(lp, 1100000)) + printk(KERN_INFO + "cannot set LP STBY voltage\n"); + } else { + /* Cannot drop voltage for TO2.0 */ + if (regulator_set_voltage(lp, 1200000)) + printk(KERN_INFO + "cannot set LP STBY voltage\n"); + } + regulator_disable(lp); + regulator_put(lp, NULL); + } + + /* subscribe PWRON1 event to enable ON_OFF key */ + power_key_event.param = NULL; + power_key_event.func = (void *)power_on_evt_handler; + pmic_event_subscribe(EVENT_PWRONI, power_key_event); + + /* Bit 4 DRM: keep VSRTC and CLK32KMCU on for all states */ + pmic_read_reg(REG_POWER_CTL0, &value, 0xffffff); + value |= 0x000010; + pmic_write_reg(REG_POWER_CTL0, value, 0xffffff); + + return 0; +} + +late_initcall(mc13892_reg_int); + +static void mxc_nop_release(struct device *dev) +{ + /* Nothing */ +} + +/* Get reference input clocks */ +void board_ref_clk_rate(unsigned long *ckil, unsigned long *osc, + unsigned long *ckih, unsigned long *ckih2) +{ + *ckil = 32768; + *osc = 24000000; + *ckih = 22579200; + *ckih2 = 24576000; +} + +#if defined(CONFIG_KEYBOARD_MXC) || defined(CONFIG_KEYBOARD_MXC_MODULE) +static u16 keymapping[24] = { + KEY_1, KEY_2, KEY_3, KEY_F1, KEY_UP, KEY_F2, + KEY_4, KEY_5, KEY_6, KEY_LEFT, KEY_SELECT, KEY_RIGHT, + KEY_7, KEY_8, KEY_9, KEY_F3, KEY_DOWN, KEY_F4, + KEY_0, KEY_OK, KEY_ESC, KEY_ENTER, KEY_MENU, KEY_BACK, +}; + +static struct resource mxc_kpp_resources[] = { + [0] = { + .start = MXC_INT_KPP, + .end = MXC_INT_KPP, + .flags = IORESOURCE_IRQ, + } +}; + +static struct keypad_data keypad_plat_data = { + .rowmax = 4, + .colmax = 6, + .irq = MXC_INT_KPP, + .learning = 0, + .delay = 2, + .matrix = keymapping, +}; + +/* mxc keypad driver */ +static struct platform_device mxc_keypad_device = { + .name = "mxc_keypad", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_kpp_resources), + .resource = mxc_kpp_resources, + .dev = { + .release = mxc_nop_release, + .platform_data = &keypad_plat_data, + }, +}; + +static void mxc_init_keypad(void) +{ + (void)platform_device_register(&mxc_keypad_device); +} +#else +static inline void mxc_init_keypad(void) +{ +} +#endif + +/* MTD NAND flash */ +#if defined(CONFIG_MTD_NAND_MXC) \ + || defined(CONFIG_MTD_NAND_MXC_MODULE) \ + || defined(CONFIG_MTD_NAND_MXC_V2) \ + || defined(CONFIG_MTD_NAND_MXC_V2_MODULE) \ + || defined(CONFIG_MTD_NAND_MXC_V3) \ + || defined(CONFIG_MTD_NAND_MXC_V3_MODULE) + +static struct mtd_partition mxc_nand_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = 3 * 1024 * 1024}, + { + .name = "nand.kernel", + .offset = MTDPART_OFS_APPEND, + .size = 5 * 1024 * 1024}, + { + .name = "nand.rootfs", + .offset = MTDPART_OFS_APPEND, + .size = 128 * 1024 * 1024}, + { + .name = "nand.userfs1", + .offset = MTDPART_OFS_APPEND, + .size = 256 * 1024 * 1024}, + { + .name = "nand.userfs2", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL}, +}; + +extern void gpio_nand_active(void); +extern void gpio_nand_inactive(void); + +static int nand_init(void) +{ + /* Configure the pins */ + gpio_nand_active(); + return 0; +} + +static void nand_exit(void) +{ + /* Free the pins */ + gpio_nand_inactive(); +} + +static struct flash_platform_data mxc_nand_data = { + .parts = mxc_nand_partitions, + .nr_parts = ARRAY_SIZE(mxc_nand_partitions), + .width = 1, + .init = nand_init, + .exit = nand_exit, +}; + +static struct platform_device mxc_nandv2_mtd_device = { + .name = "mxc_nandv2_flash", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_nand_data, + }, +}; + +static void mxc_init_nand_mtd(void) +{ + (void)platform_device_register(&mxc_nandv2_mtd_device); +} +#else +static inline void mxc_init_nand_mtd(void) +{ +} +#endif + +#if defined(CONFIG_FB_MXC_SYNC_PANEL) || \ + defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) +static struct platform_device mxc_fb_device[] = { + { + .name = "mxc_sdc_fb", + .id = 0, + .dev = { + .release = mxc_nop_release, + .coherent_dma_mask = 0xFFFFFFFF, + }, + }, + { + .name = "mxc_sdc_fb", + .id = 1, + .dev = { + .release = mxc_nop_release, + .coherent_dma_mask = 0xFFFFFFFF, + }, + }, + { + .name = "mxc_sdc_fb", + .id = 2, + .dev = { + .release = mxc_nop_release, + .coherent_dma_mask = 0xFFFFFFFF, + }, + }, +}; + +static void lcd_reset_to2(void) +{ + ipu_reset_disp_panel(); + + return; +} + +static void lcd_reset(void) +{ + static int first; + + /* ensure that LCDIO(1.8V) has been turn on */ + /* active reset line GPIO */ + if (!first) { + mxc_request_iomux(MX51_PIN_DISPB2_SER_RS, IOMUX_CONFIG_GPIO); + first = 1; + } + mxc_set_gpio_dataout(MX51_PIN_DISPB2_SER_RS, 0); + mxc_set_gpio_direction(MX51_PIN_DISPB2_SER_RS, 0); + /* do reset */ + msleep(10); /* tRES >= 100us */ + mxc_set_gpio_dataout(MX51_PIN_DISPB2_SER_RS, 1); + msleep(60); +} + +static struct mxc_lcd_platform_data lcd_data = { + .core_reg = "VIOHI", + .io_reg = "SW4", + .reset = lcd_reset, +}; + +static struct platform_device mxc_lcd_device = { + .name = "lcd_spi", + .dev = { + .release = mxc_nop_release, + .platform_data = &lcd_data, + }, +}; + +static struct mxc_lcd_platform_data lcd_wvga_data; + +static struct platform_device lcd_wvga_device = { + .name = "lcd_claa", + .dev = { + .release = mxc_nop_release, + .platform_data = &lcd_wvga_data, + }, +}; + +extern void gpio_lcd_active(void); + +static void mxc_init_fb(void) +{ + gpio_lcd_active(); + + if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0) + lcd_data.reset = lcd_reset_to2; + + (void)platform_device_register(&mxc_lcd_device); + (void)platform_device_register(&lcd_wvga_device); + + (void)platform_device_register(&mxc_fb_device[0]); + (void)platform_device_register(&mxc_fb_device[1]); + (void)platform_device_register(&mxc_fb_device[2]); +} +#else +static inline void mxc_init_fb(void) +{ +} +#endif + +static struct platform_device mxcbl_device = { + .name = "mxc_mc13892_bl", +}; + +static inline void mxc_init_bl(void) +{ + platform_device_register(&mxcbl_device); +} + +void si4702_reset(void) +{ + mxc_set_gpio_dataout(MX51_PIN_EIM_DTACK, 0); + msleep(100); + mxc_set_gpio_dataout(MX51_PIN_EIM_DTACK, 1); + msleep(100); +} + +void si4702_clock_ctl(int flag) +{ +} + +static void si4702_gpio_get(void) +{ + /* reset pin */ + mxc_request_iomux(MX51_PIN_EIM_DTACK, IOMUX_CONFIG_GPIO); + mxc_set_gpio_direction(MX51_PIN_EIM_DTACK, 0); +} + +static void si4702_gpio_put(void) +{ + mxc_free_iomux(MX51_PIN_EIM_DTACK, IOMUX_CONFIG_GPIO); +} + +static struct mxc_fm_platform_data si4702_data = { + .reg_vio = "SW4", + .reg_vdd = "VIOHI", + .gpio_get = si4702_gpio_get, + .gpio_put = si4702_gpio_put, + .reset = si4702_reset, + .clock_ctl = si4702_clock_ctl, + .sksnr = 0, + .skcnt = 0, + .band = 0, + .space = 100, + .seekth = 0xa, +}; + +#if defined(CONFIG_I2C_MXC) || defined(CONFIG_I2C_MXC_MODULE) + +#ifdef CONFIG_I2C_MXC_SELECT1 +static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { +}; +#endif +#ifdef CONFIG_I2C_MXC_SELECT2 +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { + { + .type = "mc13892", + .addr = 0x08, + .platform_data = (void *)MX51_PIN_GPIO1_5, + }, + { + .type = "wm8903-i2c", + .addr = 0x1a, + }, + { + .type = "sgtl5000-i2c", + .addr = 0x0a, + }, + { + .type = "tsc2007", + .addr = 0x48, + .irq = IOMUX_TO_IRQ(MX51_PIN_GPIO1_5), + }, + { + .type = "si4702", + .addr = 0x10, + .platform_data = (void *)&si4702_data, + }, +}; +#endif +#if defined(CONFIG_I2C_MXC_HS) || defined(CONFIG_I2C_MXC_HS_MODULE) +static struct mxc_camera_platform_data camera_data = { + .io_regulator = "SW4", + .analog_regulator = "VIOHI", + .mclk = 24000000, + .csi = 0, +}; +static struct mxc_lightsensor_platform_data ls_data = { + .vdd_reg = NULL, + .rext = 100, +}; + +static struct i2c_board_info mxc_i2c_hs_board_info[] __initdata = { + { + .type = "ov3640", + .addr = 0x3C, + .platform_data = (void *)&camera_data, + }, + { + .type = "isl29003", + .addr = 0x44, + .platform_data = &ls_data, + }, +}; +#endif + +#endif + +static u32 cpld_base_addr; + +/*lan9217 device*/ +#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) +static struct resource smsc911x_resources[] = { + { + .flags = IORESOURCE_MEM, + }, + { + .start = LAN9217_IRQ, + .end = LAN9217_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct platform_device smsc_lan9217_device = { + .name = "smsc911x", + .id = 0, + .dev = { + .release = mxc_nop_release, + }, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, +}; +static void mxc_init_enet(void) +{ + smsc_lan9217_device.resource[0].start = + LAN9217_BASE_ADDR(cpld_base_addr); + smsc_lan9217_device.resource[0].end = LAN9217_BASE_ADDR(cpld_base_addr) + + 0x100; + (void)platform_device_register(&smsc_lan9217_device); +} +#else +static inline void mxc_init_enet(void) +{ +} +#endif + +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) +unsigned int expio_intr_fec; + +EXPORT_SYMBOL(expio_intr_fec); +#endif + +#if defined(CONFIG_MMC_IMX_ESDHCI) || defined(CONFIG_MMC_IMX_ESDHCI_MODULE) +static struct mxc_mmc_platform_data mmc_data = { + .ocr_mask = MMC_VDD_32_33, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 150000, + .max_clk = 52000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", + .power_mmc = NULL, +}; + +/*! + * Resource definition for the SDHC1 + */ +static struct resource mxcsdhc1_resources[] = { + [0] = { + .start = MMC_SDHC1_BASE_ADDR, + .end = MMC_SDHC1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_MMC_SDHC1, + .end = MXC_INT_MMC_SDHC1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! + * Resource definition for the SDHC2 + */ +static struct resource mxcsdhc2_resources[] = { + [0] = { + .start = MMC_SDHC2_BASE_ADDR, + .end = MMC_SDHC2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_MMC_SDHC2, + .end = MXC_INT_MMC_SDHC2, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Device Definition for MXC SDHC1 */ +static struct platform_device mxcsdhc1_device = { + .name = "mxsdhci", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc_data, + }, + .num_resources = ARRAY_SIZE(mxcsdhc1_resources), + .resource = mxcsdhc1_resources, +}; + +/*! Device Definition for MXC SDHC2 */ +static struct platform_device mxcsdhc2_device = { + .name = "mxsdhci", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc_data, + }, + .num_resources = ARRAY_SIZE(mxcsdhc2_resources), + .resource = mxcsdhc2_resources, +}; + +static inline void mxc_init_mmc(void) +{ + int cd_irq; + + cd_irq = sdhc_init_card_det(0); + if (cd_irq) { + mxcsdhc1_device.resource[2].start = cd_irq; + mxcsdhc1_device.resource[2].end = cd_irq; + } + + cd_irq = sdhc_init_card_det(1); + if (cd_irq) { + mxcsdhc2_device.resource[2].start = cd_irq; + mxcsdhc2_device.resource[2].end = cd_irq; + } + + (void)platform_device_register(&mxcsdhc1_device); + (void)platform_device_register(&mxcsdhc2_device); +} +#else +static inline void mxc_init_mmc(void) +{ +} +#endif + +static u32 brd_io; +static void expio_ack_irq(u32 irq); + +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) +{ + u32 imr_val; + u32 int_valid; + u32 expio_irq; + + desc->chip->mask(irq); /* irq = gpio irq number */ + + imr_val = __raw_readw(brd_io + INTR_MASK_REG); + int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val; + + if (unlikely(!int_valid)) + goto out; + + expio_irq = MXC_EXP_IO_BASE; + for (; int_valid != 0; int_valid >>= 1, expio_irq++) { + struct irq_desc *d; + if ((int_valid & 1) == 0) + continue; + d = irq_desc + expio_irq; + if (unlikely(!(d->handle_irq))) { + printk(KERN_ERR "\nEXPIO irq: %d unhandled\n", + expio_irq); + BUG(); /* oops */ + } + d->handle_irq(expio_irq, d); + } + + out: + desc->chip->ack(irq); + desc->chip->unmask(irq); +} + +/* + * Disable an expio pin's interrupt by setting the bit in the imr. + * @param irq an expio virtual irq number + */ +static void expio_mask_irq(u32 irq) +{ + u16 reg; + u32 expio = MXC_IRQ_TO_EXPIO(irq); + /* mask the interrupt */ + reg = __raw_readw(brd_io + INTR_MASK_REG); + reg |= (1 << expio); + __raw_writew(reg, brd_io + INTR_MASK_REG); +} + +/* + * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. + * @param irq an expanded io virtual irq number + */ +static void expio_ack_irq(u32 irq) +{ + u32 expio = MXC_IRQ_TO_EXPIO(irq); + /* clear the interrupt status */ + __raw_writew(1 << expio, brd_io + INTR_RESET_REG); + __raw_writew(0, brd_io + INTR_RESET_REG); + /* mask the interrupt */ + expio_mask_irq(irq); +} + +/* + * Enable a expio pin's interrupt by clearing the bit in the imr. + * @param irq a expio virtual irq number + */ +static void expio_unmask_irq(u32 irq) +{ + u16 reg; + u32 expio = MXC_IRQ_TO_EXPIO(irq); + /* unmask the interrupt */ + reg = __raw_readw(brd_io + INTR_MASK_REG); + reg &= ~(1 << expio); + __raw_writew(reg, brd_io + INTR_MASK_REG); +} + +static struct irq_chip expio_irq_chip = { + .ack = expio_ack_irq, + .mask = expio_mask_irq, + .unmask = expio_unmask_irq, +}; + +static int __init mxc_expio_init(void) +{ + int i; + + brd_io = (u32) ioremap(BOARD_IO_ADDR(CS5_BASE_ADDR), SZ_4K); + if (brd_io == 0) + return -ENOMEM; + + if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) || + (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) || + (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) { + iounmap((void *)brd_io); + brd_io = (u32) ioremap(BOARD_IO_ADDR(CS1_BASE_ADDR), SZ_4K); + if (brd_io == 0) + return -ENOMEM; + + if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) || + (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) || + (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) { + iounmap((void *)brd_io); + brd_io = 0; + return -ENODEV; + } + cpld_base_addr = CS1_BASE_ADDR; + } else { + cpld_base_addr = CS5_BASE_ADDR; + } + + pr_info("3-Stack Debug board detected, rev = 0x%04X\n", + readw(brd_io + CPLD_CODE_VER_REG)); + + /* + * Configure INT line as GPIO input + */ + mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_GPIO); + mxc_set_gpio_direction(MX51_PIN_GPIO1_6, 1); + + /* disable the interrupt and clear the status */ + __raw_writew(0, brd_io + INTR_MASK_REG); + __raw_writew(0xFFFF, brd_io + INTR_RESET_REG); + __raw_writew(0, brd_io + INTR_RESET_REG); + __raw_writew(0x1F, brd_io + INTR_MASK_REG); + for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); + i++) { + set_irq_chip(i, &expio_irq_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + set_irq_type(EXPIO_PARENT_INT, IRQT_LOW); + set_irq_chained_handler(EXPIO_PARENT_INT, mxc_expio_irq_handler); + + return 0; +} + +#if defined(CONFIG_PATA_FSL) || defined(CONFIG_PATA_FSL_MODULE) +extern void gpio_ata_active(void); +extern void gpio_ata_inactive(void); + +static int ata_init(struct platform_device *pdev) +{ + /* Configure the pins */ + gpio_ata_active(); + return 0; +} + +static void ata_exit(void) +{ + /* Free the pins */ + gpio_ata_inactive(); +} + +static struct fsl_ata_platform_data ata_data = { + .udma_mask = ATA_UDMA3, + .mwdma_mask = ATA_MWDMA2, + .pio_mask = ATA_PIO4, + .fifo_alarm = MXC_IDE_DMA_WATERMARK / 2, + .max_sg = MXC_IDE_DMA_BD_NR, + .init = ata_init, + .exit = ata_exit, + .core_reg = NULL, + .io_reg = NULL, +}; + +static struct resource pata_fsl_resources[] = { + [0] = { + .start = ATA_BASE_ADDR, + .end = ATA_BASE_ADDR + 0x000000C8, + .flags = IORESOURCE_MEM,}, + [2] = { + .start = MXC_INT_ATA, + .end = MXC_INT_ATA, + .flags = IORESOURCE_IRQ,}, +}; + +static struct platform_device pata_fsl_device = { + .name = "pata_fsl", + .id = -1, + .num_resources = ARRAY_SIZE(pata_fsl_resources), + .resource = pata_fsl_resources, + .dev = { + .platform_data = &ata_data, + .coherent_dma_mask = ~0,}, +}; + +static void __init mxc_init_pata(void) +{ + (void)platform_device_register(&pata_fsl_device); +} +#else /* CONFIG_PATA_FSL */ +static void __init mxc_init_pata(void) +{ +} +#endif /* CONFIG_PATA_FSL */ + +#if defined(CONFIG_TOUCHSCREEN_TSC2007) \ + || defined(CONFIG_TOUCHSCREEN_TSC2007_MODULE) + +static int __init mxc_init_touchscreen(void) +{ + int pad_val; + + mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_GPIO); + pad_val = PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU; + mxc_iomux_set_pad(MX51_PIN_GPIO1_5, pad_val); + mxc_set_gpio_direction(MX51_PIN_GPIO1_5, 1); + + return 0; +} +#else +static int __init mxc_init_touchscreen(void) +{ + return 0; +} +#endif + +static int __init mxc_init_srpgconfig(void) +{ + struct clk *gpcclk = clk_get(NULL, "gpc_dvfs_clk"); + clk_enable(gpcclk); + + /* Setup the number of clock cycles to wait for SRPG + * power up and power down requests. + */ + __raw_writel(0x010F0201, MXC_SRPG_ARM_PUPSCR); + __raw_writel(0x010F0201, MXC_SRPG_NEON_PUPSCR); + __raw_writel(0x00000008, MXC_SRPG_EMPGC0_PUPSCR); + __raw_writel(0x00000008, MXC_SRPG_EMPGC1_PUPSCR); + + __raw_writel(0x01010101, MXC_SRPG_ARM_PDNSCR); + __raw_writel(0x01010101, MXC_SRPG_NEON_PDNSCR); + __raw_writel(0x00000018, MXC_SRPG_EMPGC0_PDNSCR); + __raw_writel(0x00000018, MXC_SRPG_EMPGC1_PDNSCR); + + clk_disable(gpcclk); + clk_put(gpcclk); + + return 0; +} + +#if defined(CONFIG_SND_SOC_IMX_3STACK_WM8903) \ + || defined(CONFIG_SND_SOC_IMX_3STACK_WM8903_MODULE) +static struct mxc_audio_platform_data mxc_audio_data; + +static struct platform_device mxc_alsa_device = { + .name = "imx-3stack-wm8903", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_audio_data, + }, +}; + +static void __init mxc_init_audio(void) +{ + mxc_audio_data.ssi_clk[0] = clk_get(NULL, "ssi_clk.0"); + clk_put(mxc_audio_data.ssi_clk[0]); + + mxc_audio_data.ssi_clk[1] = clk_get(NULL, "ssi_clk.1"); + clk_put(mxc_audio_data.ssi_clk[1]); + + mxc_audio_data.ssi_num = 1; + mxc_audio_data.src_port = 2; + mxc_audio_data.ext_port = 3; + + (void)platform_device_register(&mxc_alsa_device); +} +#else +static void __init mxc_init_audio(void) +{ +} +#endif + +#if defined(CONFIG_SND_SOC_IMX_3STACK_SGTL5000) \ + || defined(CONFIG_SND_SOC_IMX_3STACK_SGTL5000_MODULE) +static int mxc_sgtl5000_plat_init(void); +static int mxc_sgtl5000_plat_finit(void); +static int mxc_sgtl5000_amp_enable(int enable); + +static struct mxc_sgtl5000_platform_data sgtl5000_data = { + .ssi_num = 1, + .src_port = 2, + .ext_port = 3, + .hp_irq = IOMUX_TO_IRQ(MX51_PIN_EIM_A26), + .hp_status = headphone_det_status, + .amp_enable = mxc_sgtl5000_amp_enable, + .vddio = 1800000, + .vdda = 1800000, + .vddd = 12000000, + .sysclk = 12000000, + .init = mxc_sgtl5000_plat_init, + .finit = mxc_sgtl5000_plat_finit, +}; + +static struct platform_device sgtl5000_device = { + .name = "sgtl5000-imx", + .dev = { + .release = mxc_nop_release, + .platform_data = &sgtl5000_data, + }, +}; + +static int mxc_sgtl5000_plat_init(void) +{ + struct regulator *reg; + reg = regulator_get(&sgtl5000_device.dev, "GPO2"); + if (IS_ERR(reg)) + return -EINVAL; + sgtl5000_data.priv = reg; + return 0; +} + +static int mxc_sgtl5000_plat_finit(void) +{ + struct regulator *reg; + reg = sgtl5000_data.priv; + if (reg) { + regulator_put(reg, &sgtl5000_device.dev); + sgtl5000_data.priv = NULL; + } + return 0; +} + +static int mxc_sgtl5000_amp_enable(int enable) +{ + struct regulator *reg; + reg = sgtl5000_data.priv; + + if (!reg) + return -EINVAL; + if (enable) + regulator_enable(reg); + else + regulator_disable(reg); + return 0; +} + +static void mxc_sgtl5000_init(void) +{ + int err, pin; + + pin = MX51_PIN_EIM_A26; + err = mxc_request_iomux(pin, IOMUX_CONFIG_GPIO); + if (err) { + sgtl5000_data.hp_irq = -1; + printk(KERN_ERR "Error: sgtl5000_init request gpio failed!\n"); + return; + } + mxc_iomux_set_pad(pin, PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU); + mxc_set_gpio_direction(pin, 1); + + platform_device_register(&sgtl5000_device); +} +#else +static inline void mxc_sgtl5000_init(void) +{ +} +#endif + +static void bt_reset(void) +{ + mxc_set_gpio_dataout(MX51_PIN_EIM_D19, 1); +} + +static struct mxc_bt_platform_data mxc_bt_data = { + .bt_vdd = NULL, + .bt_vdd_parent = NULL, + .bt_vusb = "SW4", + .bt_vusb_parent = NULL, + .bt_reset = bt_reset, +}; + +static struct platform_device mxc_bt_device = { + .name = "mxc_bt", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_bt_data, + }, +}; + +static void mxc_init_bluetooth(void) +{ + (void)platform_device_register(&mxc_bt_device); +} + +#if defined(CONFIG_SDIO_UNIFI_FS) || defined(CONFIG_SDIO_UNIFI_FS_MODULE) +static void mxc_unifi_hardreset(void) +{ + mxc_set_gpio_dataout(MX51_PIN_EIM_D19, 0); + msleep(100); + mxc_set_gpio_dataout(MX51_PIN_EIM_D19, 1); +} + +static struct mxc_unifi_platform_data unifi_data = { + .hardreset = mxc_unifi_hardreset, + .reg_vdd_vpa = "VSD", + .reg_1v5_dd = "VGEN1", + .host_id = 1, +}; + +struct mxc_unifi_platform_data *get_unifi_plat_data(void) +{ + return &unifi_data; +} +#else +struct mxc_unifi_platform_data *get_unifi_plat_data(void) +{ + return NULL; +} +#endif + +EXPORT_SYMBOL(get_unifi_plat_data); + +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mxc_cpu_init(); + +#ifdef CONFIG_DISCONTIGMEM + do { + int nid; + mi->nr_banks = MXC_NUMNODES; + for (nid = 0; nid < mi->nr_banks; nid++) + SET_NODE(mi, nid); + + } while (0); +#endif +} + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + int err; + + mxc_cpu_common_init(); + mxc_clocks_init(); + mxc_gpio_init(); + early_console_setup(saved_command_line); + mxc_init_devices(); + + mxc_expio_init(); + mxc_init_enet(); + mxc_init_pata(); + mxc_init_fb(); + mxc_init_bl(); + mxc_init_keypad(); + mxc_init_nand_mtd(); + mxc_init_mmc(); + mxc_init_srpgconfig(); + +#if defined(CONFIG_I2C_MXC) || defined(CONFIG_I2C_MXC_MODULE) + +#ifdef CONFIG_I2C_MXC_SELECT1 + i2c_register_board_info(0, mxc_i2c0_board_info, + ARRAY_SIZE(mxc_i2c0_board_info)); +#endif +#ifdef CONFIG_I2C_MXC_SELECT2 + i2c_register_board_info(1, mxc_i2c1_board_info, + ARRAY_SIZE(mxc_i2c1_board_info)); +#endif +#if defined(CONFIG_I2C_MXC_HS) || defined(CONFIG_I2C_MXC_HS_MODULE) + i2c_register_board_info(3, mxc_i2c_hs_board_info, + ARRAY_SIZE(mxc_i2c_hs_board_info)); +#endif + +#endif + mxc_init_touchscreen(); + mxc_init_audio(); + + mxc_sgtl5000_init(); + mxc_init_bluetooth(); + + err = mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_GPIO); + if (err) + printk(KERN_ERR "Error: bt reset request gpio failed!\n"); + else + mxc_set_gpio_direction(MX51_PIN_EIM_D19, 0); +} + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX51_3STACK data structure. + */ +/* *INDENT-OFF* */ +MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") + /* Maintainer: Freescale Semiconductor, Inc. */ + .phys_io = AIPS1_BASE_ADDR, + .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .fixup = fixup_mxc_board, + .map_io = mxc_map_io, + .init_irq = mxc_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff -urN linux-2.6.26/arch/arm/mach-mx51/mx51_3stack_gpio.c linux-2.6.26-lab126/arch/arm/mach-mx51/mx51_3stack_gpio.c --- linux-2.6.26/arch/arm/mach-mx51/mx51_3stack_gpio.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/mx51_3stack_gpio.c 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,1926 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "iomux.h" + +/*! + * @file mach-mx51/mx51_3stack_gpio.c + * + * @brief This file contains all the GPIO setup functions for the board. + * + * @ingroup GPIO + */ + +void gpio_activate_audio_ports(void); + +/*! + * Setup GPIO for a UART port to be active + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_active(int port, int no_irda) +{ + /* + * Configure the IOMUX control registers for the UART signals + * and enable the UART transceivers + */ + switch (port) { + /* UART 1 IOMUX Configs */ + case 0: + mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_RXD, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_TXD, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_RTS, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH); + mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_CTS, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH); + break; + /* UART 2 IOMUX Configs */ + case 1: + mxc_request_iomux(MX51_PIN_UART2_RXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART2_RXD, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_input(MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, + INPUT_CTL_PATH2); + mxc_request_iomux(MX51_PIN_UART2_TXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART2_TXD, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + /* UART2_RTS */ + mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_EIM_D26, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_input(MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, + INPUT_CTL_PATH3); + /* UART2_CTS */ + mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_EIM_D25, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + break; + case 2: + /* UART 3 IOMUX Configs */ + mxc_request_iomux(MX51_PIN_UART3_RXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART3_RXD, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_input(MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_request_iomux(MX51_PIN_UART3_TXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART3_TXD, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + /* UART3_RTS */ + mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_input(MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, + INPUT_CTL_PATH2); + /* UART3_CTS */ + mxc_request_iomux(MX51_PIN_EIM_D24, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_D24, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_uart_active); + +/*! + * Setup GPIO for a UART port to be inactive + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_inactive(int port, int no_irda) +{ + switch (port) { + /* UART 1 */ + case 0: + mxc_request_gpio(MX51_PIN_UART1_RXD); + mxc_request_gpio(MX51_PIN_UART1_TXD); + mxc_request_gpio(MX51_PIN_UART1_RTS); + mxc_request_gpio(MX51_PIN_UART1_CTS); + + mxc_free_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_GPIO); + break; + /* UART 2 */ + case 1: + mxc_request_gpio(MX51_PIN_UART2_RXD); + mxc_request_gpio(MX51_PIN_UART2_TXD); + + mxc_free_iomux(MX51_PIN_UART2_RXD, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_UART2_TXD, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT4); + mxc_free_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT4); + break; + case 2: + /* UART 3 */ + mxc_request_gpio(MX51_PIN_UART3_RXD); + mxc_request_gpio(MX51_PIN_UART3_TXD); + mxc_request_gpio(MX51_PIN_EIM_D27); + mxc_request_gpio(MX51_PIN_EIM_D24); + + mxc_free_iomux(MX51_PIN_UART3_RXD, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_UART3_TXD, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_EIM_D24, IOMUX_CONFIG_GPIO); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_uart_inactive); + +/*! + * Configure the IOMUX GPR register to receive shared SDMA UART events + * + * @param port a UART port + */ +void config_uartdma_event(int port) +{ + +} + +EXPORT_SYMBOL(config_uartdma_event); + +/*! + * Setup GPIO for a CSPI device to be active + * + * @param cspi_mod an CSPI device + */ +void gpio_spi_active(int cspi_mod) +{ + switch (cspi_mod) { + case 0: + /* SPI1 */ + mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_SRE_FAST); + break; + case 1: + /* SPI2 */ + mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE); + + mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE); + + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) { + mxc_request_iomux(MX51_PIN_NANDF_RB4, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB4, PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE); + + mxc_request_iomux(MX51_PIN_NANDF_RB7, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB7, PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_HIGH); + } else { + mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE); + + mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D15, PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_KEEPER); + + mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D12, PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE); + } + break; + case 2: + /* SPI3 */ + mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_spi_active); + +/*! + * Setup GPIO for a CSPI device to be inactive + * + * @param cspi_mod a CSPI device + */ +void gpio_spi_inactive(int cspi_mod) +{ + switch (cspi_mod) { + case 0: + /* SPI1 */ + mxc_free_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT0); + break; + case 1: + /* SPI2 */ + mxc_free_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT2); + mxc_free_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT2); + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) { + mxc_free_iomux(MX51_PIN_NANDF_RB4, IOMUX_CONFIG_ALT2); + mxc_free_iomux(MX51_PIN_NANDF_RB7, IOMUX_CONFIG_ALT2); + } else { + mxc_free_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT2); + mxc_free_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT2); + mxc_free_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT2); + } + break; + case 2: + /* SPI3 */ + mxc_free_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT1); + mxc_free_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT1); + mxc_free_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT1); + mxc_free_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT1); + break; + default: + break; + } + +} + +EXPORT_SYMBOL(gpio_spi_inactive); + +/*! + * Setup 1-Wire to be active + */ +void gpio_owire_active(void) +{ + mxc_request_iomux(MX51_PIN_OWIRE_LINE, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_OWIRE_LINE, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); +} + +EXPORT_SYMBOL(gpio_owire_active); + +/*! + * Setup 1-Wire to be active + */ +void gpio_owire_inactive(void) +{ + mxc_free_iomux(MX51_PIN_OWIRE_LINE, IOMUX_CONFIG_ALT0); +} + +EXPORT_SYMBOL(gpio_owire_inactive); + +/*! + * Setup GPIO for an I2C device to be active + * + * @param i2c_num an I2C device + */ +void gpio_i2c_active(int i2c_num) +{ + switch (i2c_num) { + case 0: + /*i2c1 sda */ + mxc_request_iomux(MX51_PIN_CSPI1_MOSI, + IOMUX_CONFIG_ALT1 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH1); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_VOT_LOW | PAD_CTL_DDR_INPUT_CMOS); + + /*i2c1 scl */ + mxc_request_iomux(MX51_PIN_CSPI1_SCLK, + IOMUX_CONFIG_ALT1 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH1); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_VOT_LOW | PAD_CTL_DDR_INPUT_CMOS); + break; + + case 1: + mxc_request_iomux(MX51_PIN_GPIO1_2, + IOMUX_CONFIG_ALT2 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_GPIO1_3, + IOMUX_CONFIG_ALT2 | IOMUX_CONFIG_SION); + + mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH3); + mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH3); + + mxc_iomux_set_pad(MX51_PIN_GPIO1_2, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_VOT_LOW | PAD_CTL_DDR_INPUT_CMOS); + mxc_iomux_set_pad(MX51_PIN_GPIO1_3, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_VOT_LOW | PAD_CTL_DDR_INPUT_CMOS); + break; + case 2: + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_i2c_active); + +/*! + * Setup GPIO for an I2C device to be inactive + * + * @param i2c_num an I2C device + */ +void gpio_i2c_inactive(int i2c_num) +{ + switch (i2c_num) { + case 0: + /*i2c1 sda */ + mxc_free_iomux(MX51_PIN_CSPI1_MOSI, + IOMUX_CONFIG_ALT1 | IOMUX_CONFIG_SION); + /*i2c1 scl */ + mxc_free_iomux(MX51_PIN_CSPI1_SCLK, + IOMUX_CONFIG_ALT1 | IOMUX_CONFIG_SION); + break; + case 1: + mxc_free_iomux(MX51_PIN_GPIO1_2, + IOMUX_CONFIG_ALT2 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX51_PIN_GPIO1_3, + IOMUX_CONFIG_ALT2 | IOMUX_CONFIG_SION); + break; + case 2: + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_i2c_inactive); + +void gpio_i2c_hs_active(void) +{ + mxc_request_iomux(MX51_PIN_I2C1_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_I2C1_CLK, 0x1E4); + + mxc_request_iomux(MX51_PIN_I2C1_DAT, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_I2C1_DAT, 0x1E4); +} + +EXPORT_SYMBOL(gpio_i2c_hs_active); + +void gpio_i2c_hs_inactive(void) +{ + mxc_free_iomux(MX51_PIN_I2C1_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX51_PIN_I2C1_DAT, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); +} + +EXPORT_SYMBOL(gpio_i2c_hs_inactive); + +void gpio_pmic_active(void) +{ + mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_GPIO + | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_SRE_SLOW | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_MEDIUM | + PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DDR_INPUT_CMOS); + mxc_set_gpio_direction(MX51_PIN_GPIO1_5, 1); +} + +EXPORT_SYMBOL(gpio_pmic_active); + +/*! + * This function activates DAM port 3 to enable audio I/O. + */ +void gpio_activate_audio_ports(void) +{ + unsigned int pad_val; + + pad_val = PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_100K_PU | + PAD_CTL_HYS_NONE | PAD_CTL_DDR_INPUT_CMOS | PAD_CTL_DRV_VOT_LOW; + + /* AUD3_TXD */ + mxc_request_iomux(MX51_PIN_AUD3_BB_TXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_AUD3_BB_TXD, pad_val); + + /* AUD3_RXD */ + mxc_request_iomux(MX51_PIN_AUD3_BB_RXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_AUD3_BB_RXD, pad_val); + + /* AUD3_CLK */ + mxc_request_iomux(MX51_PIN_AUD3_BB_CK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_AUD3_BB_CK, pad_val); + + /* AUD3_FS */ + mxc_request_iomux(MX51_PIN_AUD3_BB_FS, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_AUD3_BB_FS, pad_val); + + /* EIM_D16 */ + /* osc_en is shared by SPDIF */ + mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_EIM_D16, + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_set_gpio_direction(MX51_PIN_EIM_D16, 0); + mxc_set_gpio_dataout(MX51_PIN_EIM_D16, 1); + +} + +EXPORT_SYMBOL(gpio_activate_audio_ports); + +/*! + * Setup GPIO for SDHC to be active + * + * @param module SDHC module number + */ +void gpio_sdhc_active(int module) +{ + switch (module) { + case 0: + mxc_request_iomux(MX51_PIN_SD1_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + + mxc_request_iomux(MX51_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_SD1_CMD, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_CLK, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + /* Write Protected Pin */ + mxc_request_iomux(MX51_PIN_GPIO1_1, IOMUX_CONFIG_ALT0 | + IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_1, PAD_CTL_DRV_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_SRE_FAST); + mxc_set_gpio_direction(MX51_PIN_GPIO1_1, 1); + break; + case 1: + mxc_request_iomux(MX51_PIN_SD2_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD2_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + + mxc_request_iomux(MX51_PIN_SD2_DATA0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD2_DATA1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD2_DATA2, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD2_DATA3, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_SD2_CMD, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_CLK, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_sdhc_active); + +/*! + * Setup GPIO for SDHC1 to be inactive + * + * @param module SDHC module number + */ +void gpio_sdhc_inactive(int module) +{ + switch (module) { + case 0: + mxc_free_iomux(MX51_PIN_SD1_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX51_PIN_SD1_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX51_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX51_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX51_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX51_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + + mxc_iomux_set_pad(MX51_PIN_SD1_CLK, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX51_PIN_SD1_CMD, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + + /* Free Write Protected Pin */ + mxc_free_iomux(MX51_PIN_GPIO1_1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_GPIO1_1, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + break; + case 1: + mxc_free_iomux(MX51_PIN_SD2_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX51_PIN_SD2_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX51_PIN_SD2_DATA0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX51_PIN_SD2_DATA1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX51_PIN_SD2_DATA2, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_free_iomux(MX51_PIN_SD2_DATA3, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + + mxc_iomux_set_pad(MX51_PIN_SD2_CLK, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX51_PIN_SD2_CMD, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, + (PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW)); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_sdhc_inactive); + +/* + * Probe for the card. If present the GPIO data would be set. + */ +int sdhc_get_card_det_status(struct device *dev) +{ + int ret; + + if (to_platform_device(dev)->id == 0) { + ret = mxc_get_gpio_datain(MX51_PIN_GPIO1_0); + return ret; + } else { /* config the det pin for SDHC2 */ + return 0; + } +} + +EXPORT_SYMBOL(sdhc_get_card_det_status); + +/* + * Return the card detect pin. + */ +int sdhc_init_card_det(int id) +{ + if (id == 0) { + mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT0 | + IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_0, PAD_CTL_DRV_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_set_gpio_direction(MX51_PIN_GPIO1_0, 1); + return IOMUX_TO_IRQ(MX51_PIN_GPIO1_0); + } else { /* config the det pin for SDHC2 */ + return 0; + + } +} + +EXPORT_SYMBOL(sdhc_init_card_det); + +/*! + * Get WP pin value to detect write protection + */ +int sdhc_write_protect(struct device *dev) +{ + unsigned short rc = 0; + + if (to_platform_device(dev)->id == 0) + rc = mxc_get_gpio_datain(MX51_PIN_GPIO1_1); + else + rc = 0; + if (rc > 0) + return 1; + else + return 0; +} + +EXPORT_SYMBOL(sdhc_write_protect); + +/*! + * Setup GPIO for LCD to be active + * + */ +void gpio_lcd_active(void) +{ + if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0) { +#ifndef CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL + mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4); + mxc_set_gpio_direction(MX51_PIN_DI1_D1_CS, 0); +#endif + mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT1); + mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT1); + mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT1); + mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT1); + } else { + mxc_request_iomux(MX51_PIN_DISP2_DAT15, IOMUX_CONFIG_ALT5); + mxc_request_iomux(MX51_PIN_DI_GP2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_DI_GP3, IOMUX_CONFIG_ALT0); + } +#ifdef CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL + mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4); + mxc_set_gpio_direction(MX51_PIN_DI1_D1_CS, 0); + mxc_set_gpio_dataout(MX51_PIN_DI1_D1_CS, 1); + mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4); + mxc_set_gpio_direction(MX51_PIN_DISPB2_SER_DIO, 0); + mxc_set_gpio_dataout(MX51_PIN_DISPB2_SER_DIO, 0); +#endif +} + +/*! + * Setup GPIO for LCD to be inactive + * + */ +void gpio_lcd_inactive(void) +{ +} + +/*! + * Setup pins for SLCD to be active + * + */ +void slcd_gpio_config(void) +{ +} + +/*! + * Switch to the specified sensor + * + */ +void gpio_sensor_select(int sensor) +{ +} + +/*! + * Setup GPIO for sensor to be active + * + * @param csi csi 0 or csi 1 + * + */ +void gpio_sensor_active(unsigned int csi) +{ + switch (csi) { + case 0: + mxc_iomux_set_pad(MX51_PIN_CSI1_D10, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CSI1_D11, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CSI1_D12, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CSI1_D13, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CSI1_D14, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CSI1_D15, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CSI1_D16, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CSI1_D17, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CSI1_D18, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CSI1_D19, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CSI1_PKE0, PAD_CTL_PKE_ENABLE); + + mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSI1_VSYNC, PAD_CTL_HYS_NONE | + PAD_CTL_SRE_SLOW); + + mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSI1_HSYNC, PAD_CTL_HYS_NONE | + PAD_CTL_SRE_SLOW); + + mxc_iomux_set_pad(MX51_PIN_CSI1_PIXCLK, PAD_CTL_HYS_NONE); + + if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0) { + /* Camera low power */ + mxc_request_iomux(MX51_PIN_CSI1_D8, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_CSI1_D8, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_LOW | + PAD_CTL_SRE_SLOW); + mxc_iomux_set_input + (MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT, + INPUT_CTL_PATH1); + mxc_set_gpio_direction(MX51_PIN_CSI1_D8, 0); + mxc_set_gpio_dataout(MX51_PIN_CSI1_D8, 0); + + /* Camera reset */ + mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_CSI1_D9, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_LOW | + PAD_CTL_SRE_SLOW); + mxc_set_gpio_direction(MX51_PIN_CSI1_D9, 0); + mxc_set_gpio_dataout(MX51_PIN_CSI1_D9, 1); + } else { + mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_EIM_EB2, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_100K_PD | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW); + mxc_set_gpio_direction(MX51_PIN_EIM_EB2, 0); + mxc_set_gpio_dataout(MX51_PIN_EIM_EB2, 0); + } + + mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT5); + mxc_iomux_set_input + (MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX51_PIN_EIM_A26, + PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL); + break; + case 1: + mxc_iomux_set_pad(MX51_PIN_CSI2_PKE0, PAD_CTL_PKE_ENABLE); + + mxc_request_iomux(MX51_PIN_CSI2_D12, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSI2_D12, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_LOW | + PAD_CTL_SRE_SLOW); + + mxc_request_iomux(MX51_PIN_CSI2_D13, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSI2_D13, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_LOW | + PAD_CTL_SRE_SLOW); + + mxc_request_iomux(MX51_PIN_CSI2_D18, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSI2_D18, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_LOW | + PAD_CTL_SRE_SLOW); + + mxc_request_iomux(MX51_PIN_CSI2_D19, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSI2_D19, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_LOW | + PAD_CTL_SRE_SLOW); + + mxc_request_iomux(MX51_PIN_CSI2_VSYNC, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSI2_VSYNC, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_LOW | + PAD_CTL_SRE_SLOW); + + mxc_request_iomux(MX51_PIN_CSI2_HSYNC, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSI2_HSYNC, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_LOW | + PAD_CTL_SRE_SLOW); + + mxc_request_iomux(MX51_PIN_CSI2_PIXCLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSI2_PIXCLK, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_LOW | + PAD_CTL_SRE_SLOW); + + mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT6); + mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_LOW | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_SRE_SLOW); + + mxc_request_iomux(MX51_PIN_DI2_PIN4, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_DI2_PIN4, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_LOW | + PAD_CTL_SRE_SLOW); + mxc_iomux_set_input(MUX_IN_FEC_FEC_COL_SELECT_INPUT, + INPUT_CTL_PATH1); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_sensor_active); + +/*! + * Setup GPIO for sensor to be inactive + * + * @param csi csi 0 or csi 1 + * + */ +void gpio_sensor_inactive(unsigned int csi) +{ + switch (csi) { + case 0: + if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0) { + mxc_free_iomux(MX51_PIN_CSI1_D8, IOMUX_CONFIG_GPIO); + mxc_request_iomux(MX51_PIN_CSI1_D8, IOMUX_CONFIG_ALT0); + + mxc_free_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_GPIO); + mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT0); + } else { + mxc_free_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_GPIO); + mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT0); + } + mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT0); + break; + case 1: + mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_DI2_PIN4, IOMUX_CONFIG_ALT0); + break; + default: + break; + } +} + +EXPORT_SYMBOL(gpio_sensor_inactive); + +/*! + * Setup GPIO for ATA interface + * + */ +void gpio_ata_active(void) +{ +#define ATA_PAD_CONFIG PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH + + /*BUFFER_EN */ + mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG); + + /*PATA_CS_0 */ + mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG); + + /*PATA_CS_1 */ + mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG); + + /*PATA_DA0 */ + mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG); + + /*PATA_DA1 */ + mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG); + + /*PATA_DA2 */ + mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG); + + /*PATA_DIOR */ + mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG); + + /*PATA_DIOW */ + mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG); + + /*PATA_RESET */ + mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG); + + /*PATA_DMARQ */ + mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG); + + /*PATA_DMACK */ + mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG); + + /*PATA_INTRQ */ + if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0) { + mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG); + } else { + mxc_request_iomux(MX51_PIN_NANDF_RB5, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB5, ATA_PAD_CONFIG); + } + + /*PATA_IORDY */ + mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG); + + /*PATA_D0 */ + mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG); + + /*PATA_D1 */ + mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG); + + /*PATA_D2 */ + mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG); + + /*PATA_D3 */ + mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG); + + /*PATA_D4 */ + mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG); + + /*PATA_D5 */ + mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG); + + /*PATA_D6 */ + mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG); + + /*PATA_D7 */ + mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG); + + /*PATA_D8 */ + mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG); + + /*PATA_D9 */ + mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG); + + /*PATA_D10 */ + mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG); + + /*PATA_D11 */ + mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG); + + /*PATA_D12 */ + mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG); + + /*PATA_D13 */ + mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG); + + /*PATA_D14 */ + mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG); + + /*PATA_D15 */ + mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG); + +} + +EXPORT_SYMBOL(gpio_ata_active); + +/*! + * Restore ATA interface pins to reset values + * + */ +void gpio_ata_inactive(void) +{ + /*BUFFER_EN */ + mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0); + + /*PATA_CS_0 */ + mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0); + + /*PATA_CS_1 */ + mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0); + + /*PATA_DA0 */ + mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT0); + + /*PATA_DA1 */ + mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT0); + + /*PATA_DA2 */ + mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT0); + + /*PATA_DIOR */ + mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0); + + /*PATA_DIOW */ + mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0); + + /*PATA_DMARQ */ + mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0); + + /*PATA_DMACK */ + mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0); + + /*PATA_INTRQ */ + if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0) { + mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT0); + } else { + mxc_request_iomux(MX51_PIN_NANDF_RB5, IOMUX_CONFIG_ALT0); + } + + /*PATA_IORDY */ + mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT0); + + /*PATA_D0 */ + mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT0); + + /*PATA_D1 */ + mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT0); + + /*PATA_D2 */ + mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT0); + + /*PATA_D3 */ + mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT0); + + /*PATA_D4 */ + mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT0); + + /*PATA_D5 */ + mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT0); + + /*PATA_D6 */ + mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT0); + + /*PATA_D7 */ + mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT0); + + /*PATA_D8 */ + mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT0); + + /*PATA_D9 */ + mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT0); + + /*PATA_D10 */ + mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT0); + + /*PATA_D11 */ + mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT0); + + /*PATA_D12 */ + mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT0); + + /*PATA_D13 */ + mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT0); + + /*PATA_D14 */ + mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT0); + + /*PATA_D15 */ + mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT0); + + /*PATA_RESET */ + mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0); + +} + +EXPORT_SYMBOL(gpio_ata_inactive); + +void gpio_nand_active(void) +{ + mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT0); +} + +EXPORT_SYMBOL(gpio_nand_active); + +void gpio_nand_inactive(void) +{ + mxc_free_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT0); +} + +EXPORT_SYMBOL(gpio_nand_inactive); +/*! + * Setup GPIO for Keypad to be active + * + */ +void gpio_keypad_active(void) +{ + /* + * Configure the IOMUX control register for keypad signals. + */ + mxc_request_iomux(MX51_PIN_KEY_COL0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_COL1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_COL2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_COL3, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_COL4, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_COL5, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_ROW0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_ROW1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_ROW2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_KEY_ROW3, IOMUX_CONFIG_ALT0); +} + +EXPORT_SYMBOL(gpio_keypad_active); + +/*! + * Setup GPIO for Keypad to be inactive + * + */ +void gpio_keypad_inactive(void) +{ + mxc_request_gpio(MX51_PIN_KEY_COL0); + mxc_request_gpio(MX51_PIN_KEY_COL1); + mxc_request_gpio(MX51_PIN_KEY_COL2); + mxc_request_gpio(MX51_PIN_KEY_COL3); + mxc_request_gpio(MX51_PIN_KEY_COL4); + mxc_request_gpio(MX51_PIN_KEY_COL5); + mxc_request_gpio(MX51_PIN_KEY_ROW0); + mxc_request_gpio(MX51_PIN_KEY_ROW1); + mxc_request_gpio(MX51_PIN_KEY_ROW2); + mxc_request_gpio(MX51_PIN_KEY_ROW3); + + mxc_free_iomux(MX51_PIN_KEY_COL0, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_KEY_COL1, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_KEY_COL2, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_KEY_COL3, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_KEY_COL4, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_KEY_COL5, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_KEY_ROW0, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_KEY_ROW1, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_KEY_ROW2, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_KEY_ROW3, IOMUX_CONFIG_GPIO); +} + +EXPORT_SYMBOL(gpio_keypad_inactive); + +/* + * USB OTG HS port + */ +int gpio_usbotg_hs_active(void) +{ + /* USB_PWR */ + mxc_request_iomux(MX51_PIN_GPIO1_8, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_GPIO1_8, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_NONE | PAD_CTL_HYS_ENABLE); + + /* USB_OC */ + mxc_request_iomux(MX51_PIN_GPIO1_9, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_GPIO1_9, PAD_CTL_SRE_SLOW | + PAD_CTL_DRV_LOW | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE); + return 0; +} + +EXPORT_SYMBOL(gpio_usbotg_hs_active); + +void gpio_usbotg_hs_inactive(void) +{ + mxc_request_gpio(MX51_PIN_GPIO1_8); + mxc_request_gpio(MX51_PIN_GPIO1_9); + + mxc_free_iomux(MX51_PIN_GPIO1_8, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_GPIO1_9, IOMUX_CONFIG_GPIO); +} + +EXPORT_SYMBOL(gpio_usbotg_hs_inactive); + +/* + * USB Host1 HS port + */ +int gpio_usbh1_active(void) +{ + /* Set USBH1_STP to GPIO and toggle it */ + mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO | + IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS | + PAD_CTL_DRV_VOT_LOW); + mxc_set_gpio_direction(MX51_PIN_USBH1_STP, 0); + mxc_set_gpio_dataout(MX51_PIN_USBH1_STP, 1); + + msleep(100); + + /* USBH1_CLK */ + mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_NONE | + PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS | + PAD_CTL_DRV_VOT_LOW); + + /* USBH1_DIR */ + mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS | + PAD_CTL_DRV_VOT_LOW); + + /* USBH1_NXT */ + mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS | + PAD_CTL_DRV_VOT_LOW); + + /* USBH1_DATA0 */ + mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_100K_PU | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + + /* USBH1_DATA1 */ + mxc_request_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_USBH1_DATA1, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_100K_PU | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + + /* USBH1_DATA2 */ + mxc_request_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_USBH1_DATA2, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_100K_PU | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + + /* USBH1_DATA3 */ + mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_100K_PU | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + + /* USBH1_DATA4 */ + mxc_request_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_USBH1_DATA4, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_100K_PU | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + + /* USBH1_DATA5 */ + mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_100K_PU | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + + /* USBH1_DATA6 */ + mxc_request_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_USBH1_DATA6, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_100K_PU | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + + /* USBH1_DATA7 */ + mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_100K_PU | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + + /* USB_PWR */ + mxc_request_iomux(MX51_PIN_GPIO1_8, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_GPIO1_8, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_NONE | PAD_CTL_HYS_ENABLE); + + /* USB_OC */ + mxc_request_iomux(MX51_PIN_GPIO1_9, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_GPIO1_9, PAD_CTL_SRE_SLOW | + PAD_CTL_DRV_LOW | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE); + + /* FPGA_USBOTG_RST_B */ + mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_EIM_D17, PAD_CTL_DRV_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_PUE_KEEPER | + PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_set_gpio_direction(MX51_PIN_EIM_D17, 0); + mxc_set_gpio_dataout(MX51_PIN_EIM_D17, 1); + + msleep(100); + + return 0; +} + +EXPORT_SYMBOL(gpio_usbh1_active); + +void gpio_usbh1_setback_stp(void) +{ + /* setback USBH1_STP to be function */ + mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS | + PAD_CTL_DRV_VOT_LOW); +} + +EXPORT_SYMBOL(gpio_usbh1_setback_stp); + +void gpio_usbh1_inactive(void) +{ + mxc_request_gpio(MX51_PIN_USBH1_CLK); + mxc_request_gpio(MX51_PIN_USBH1_DIR); + mxc_request_gpio(MX51_PIN_USBH1_NXT); + mxc_request_gpio(MX51_PIN_USBH1_STP); + mxc_request_gpio(MX51_PIN_USBH1_DATA0); + mxc_request_gpio(MX51_PIN_USBH1_DATA1); + mxc_request_gpio(MX51_PIN_USBH1_DATA2); + mxc_request_gpio(MX51_PIN_USBH1_DATA3); + mxc_request_gpio(MX51_PIN_USBH1_DATA4); + mxc_request_gpio(MX51_PIN_USBH1_DATA5); + mxc_request_gpio(MX51_PIN_USBH1_DATA6); + mxc_request_gpio(MX51_PIN_USBH1_DATA7); + mxc_request_gpio(MX51_PIN_GPIO1_8); + mxc_request_gpio(MX51_PIN_GPIO1_9); + + mxc_free_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_GPIO1_8, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_GPIO1_9, IOMUX_CONFIG_GPIO); + + mxc_free_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_GPIO); +} + +EXPORT_SYMBOL(gpio_usbh1_inactive); + +int gpio_usbh2_active(void) +{ + /* Set USBH2_STP to GPIO and toggle it */ + mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_EIM_A26, PAD_CTL_DRV_HIGH | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_set_gpio_direction(MX51_PIN_EIM_A26, 0); + mxc_set_gpio_dataout(MX51_PIN_EIM_A26, 1); + + msleep(100); + + /* USBH2_CLK */ + mxc_request_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_EIM_A24, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS | + PAD_CTL_DRV_VOT_LOW); + + /* USBH2_DIR */ + mxc_request_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_EIM_A25, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS | + PAD_CTL_DRV_VOT_LOW); + + /* USBH2_NXT */ + mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_EIM_A27, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS | + PAD_CTL_DRV_VOT_LOW); + + /* USBH2_DATA0 */ + mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_EIM_D16, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_100K_PU | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + + /* USBH2_DATA1 */ + mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_EIM_D17, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_100K_PU | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + + /* USBH2_DATA2 */ + mxc_request_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_EIM_D18, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_100K_PU | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + + /* USBH2_DATA3 */ + mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_EIM_D19, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_100K_PU | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + + /* USBH2_DATA4 */ + mxc_request_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_EIM_D20, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_100K_PU | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + + /* USBH2_DATA5 */ + mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_EIM_D21, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_100K_PU | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + + /* USBH2_DATA6 */ + mxc_request_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_EIM_D22, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_100K_PU | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + + /* USBH2_DATA7 */ + mxc_request_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_EIM_D23, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_100K_PU | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + + msleep(100); + return 0; +} + +EXPORT_SYMBOL(gpio_usbh2_active); + +void gpio_usbh2_inactive(void) +{ + mxc_request_gpio(MX51_PIN_EIM_D16); + mxc_request_gpio(MX51_PIN_EIM_D17); + mxc_request_gpio(MX51_PIN_EIM_D18); + mxc_request_gpio(MX51_PIN_EIM_D19); + mxc_request_gpio(MX51_PIN_EIM_D20); + mxc_request_gpio(MX51_PIN_EIM_D21); + mxc_request_gpio(MX51_PIN_EIM_D22); + mxc_request_gpio(MX51_PIN_EIM_D23); + mxc_request_gpio(MX51_PIN_EIM_A24); + mxc_request_gpio(MX51_PIN_EIM_A25); + mxc_request_gpio(MX51_PIN_EIM_A26); + mxc_request_gpio(MX51_PIN_EIM_A27); + + + + mxc_free_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT0); +} + +EXPORT_SYMBOL(gpio_usbh2_inactive); + +void gpio_usbh2_setback_stp(void) +{ + /* setback USBH2_STP to be function */ + mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_EIM_A26, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS | + PAD_CTL_DRV_VOT_LOW); +} + +EXPORT_SYMBOL(gpio_usbh2_setback_stp); + +/*! + * Setup GPIO for PCMCIA interface + * + */ +void gpio_pcmcia_active(void) +{ +} + +EXPORT_SYMBOL(gpio_pcmcia_active); + +/*! + * Setup GPIO for pcmcia to be inactive + */ +void gpio_pcmcia_inactive(void) +{ +} + +EXPORT_SYMBOL(gpio_pcmcia_inactive); + +/*! + * Setup GPIO for fec to be active + */ +void gpio_fec_active(void) +{ + /*TX_ER */ + mxc_request_iomux(MX51_PIN_DI_GP3, IOMUX_CONFIG_ALT2); + /*CRS */ + mxc_request_iomux(MX51_PIN_DI2_PIN4, IOMUX_CONFIG_ALT2); + /*MDC */ + mxc_request_iomux(MX51_PIN_DI2_PIN2, IOMUX_CONFIG_ALT2); + /*MDIO */ + mxc_request_iomux(MX51_PIN_DI2_PIN3, IOMUX_CONFIG_ALT2); + /*RDATA[1] */ + mxc_request_iomux(MX51_PIN_DI2_DISP_CLK, IOMUX_CONFIG_ALT2); + /*RDATA[2] */ + mxc_request_iomux(MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT2); + /*RDATA[3] */ + mxc_request_iomux(MX51_PIN_DISP2_DAT0, IOMUX_CONFIG_ALT2); + /*RX_ER */ + mxc_request_iomux(MX51_PIN_DISP2_DAT1, IOMUX_CONFIG_ALT2); + /*TDATA[1] */ + mxc_request_iomux(MX51_PIN_DISP2_DAT6, IOMUX_CONFIG_ALT2); + /*TDATA[2] */ + mxc_request_iomux(MX51_PIN_DISP2_DAT7, IOMUX_CONFIG_ALT2); + /*TDATA[3] */ + mxc_request_iomux(MX51_PIN_DISP2_DAT8, IOMUX_CONFIG_ALT2); + /*TX_EN */ + mxc_request_iomux(MX51_PIN_DISP2_DAT9, IOMUX_CONFIG_ALT2); + /*COL */ + mxc_request_iomux(MX51_PIN_DISP2_DAT10, IOMUX_CONFIG_ALT2); + /*RX_CLK */ + mxc_request_iomux(MX51_PIN_DISP2_DAT11, IOMUX_CONFIG_ALT2); + /*RX_DV */ + mxc_request_iomux(MX51_PIN_DISP2_DAT12, IOMUX_CONFIG_ALT2); + /*TX_CLK */ + mxc_request_iomux(MX51_PIN_DISP2_DAT13, IOMUX_CONFIG_ALT2); + /*RDATA[0] */ + mxc_request_iomux(MX51_PIN_DISP2_DAT14, IOMUX_CONFIG_ALT2); + /*TDATA[0] */ + mxc_request_iomux(MX51_PIN_DISP2_DAT15, IOMUX_CONFIG_ALT2); + + /*TX_ER */ + mxc_iomux_set_pad(MX51_PIN_DI_GP3, + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH | + PAD_CTL_DRV_VOT_HIGH); + /*CRS */ + mxc_iomux_set_pad(MX51_PIN_DI2_PIN4, + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_VOT_HIGH); + /*MDC */ + mxc_iomux_set_pad(MX51_PIN_DI2_PIN2, + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH | + PAD_CTL_DRV_VOT_HIGH); + /*MDIO */ + mxc_iomux_set_pad(MX51_PIN_DI2_PIN3, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_22K_PU | + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_VOT_HIGH); + /*RDATA[1] */ + mxc_iomux_set_pad(MX51_PIN_DI2_DISP_CLK, + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_VOT_HIGH); + /*RDATA[2] */ + mxc_iomux_set_pad(MX51_PIN_DI_GP4, + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_VOT_HIGH); + /*RDATA[3] */ + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT0, + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_VOT_HIGH); + /*RX_ER */ + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT1, + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_VOT_HIGH); + /*TDATA[1] */ + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT6, + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH | + PAD_CTL_DRV_VOT_HIGH); + /*TDATA[2] */ + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT7, + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH | + PAD_CTL_DRV_VOT_HIGH); + /*TDATA[3] */ + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT8, + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH | + PAD_CTL_DRV_VOT_HIGH); + /*TX_EN */ + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT9, + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH | + PAD_CTL_DRV_VOT_HIGH); + /*COL */ + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT10, + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_VOT_HIGH); + /*RX_CLK */ + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT11, + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_VOT_HIGH); + /*RX_DV */ + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT12, + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_VOT_HIGH); + /*TX_CLK */ + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT13, + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_VOT_HIGH); + /*RDATA[0] */ + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT14, + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_VOT_HIGH); + /*TDATA[0] */ + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT15, + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH | + PAD_CTL_DRV_VOT_HIGH); + + /*COL */ + mxc_iomux_set_input(MUX_IN_FEC_FEC_COL_SELECT_INPUT, INPUT_CTL_PATH1); + /*CRS */ + mxc_iomux_set_input(MUX_IN_FEC_FEC_CRS_SELECT_INPUT, INPUT_CTL_PATH1); + /*MDIO */ + mxc_iomux_set_input(MUX_IN_FEC_FEC_MDI_SELECT_INPUT, INPUT_CTL_PATH1); + /*RDATA[0] */ + mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, + INPUT_CTL_PATH1); + /*RDATA[1] */ + mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, + INPUT_CTL_PATH1); + /*RDATA[2] */ + mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT, + INPUT_CTL_PATH1); + /*RDATA[3] */ + mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT, + INPUT_CTL_PATH1); + /*RX_CLK */ + mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, + INPUT_CTL_PATH1); + /*RX_DV */ + mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, INPUT_CTL_PATH1); + /*RX_ER */ + mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, INPUT_CTL_PATH1); + /*TX_CLK */ + mxc_iomux_set_input(MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, + INPUT_CTL_PATH1); + + /*reset */ + mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU + | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_VOT_HIGH); + mxc_set_gpio_direction(MX51_PIN_DISPB2_SER_DIO, 0); + mxc_set_gpio_dataout(MX51_PIN_DISPB2_SER_DIO, 0); + msleep(10); + mxc_set_gpio_dataout(MX51_PIN_DISPB2_SER_DIO, 1); + msleep(100); +} + +EXPORT_SYMBOL(gpio_fec_active); + +/*! + * Setup GPIO for fec to be inactive + */ +void gpio_fec_inactive(void) +{ + /*TX_ER */ + mxc_free_iomux(MX51_PIN_DI_GP3, IOMUX_CONFIG_ALT2); + /*CRS */ + mxc_free_iomux(MX51_PIN_DI2_PIN4, IOMUX_CONFIG_ALT2); + /*MDC */ + mxc_free_iomux(MX51_PIN_DI2_PIN2, IOMUX_CONFIG_ALT2); + /*MDIO */ + mxc_free_iomux(MX51_PIN_DI2_PIN3, IOMUX_CONFIG_ALT2); + /*RDATA[1] */ + mxc_free_iomux(MX51_PIN_DI2_DISP_CLK, IOMUX_CONFIG_ALT2); + /*RDATA[2] */ + mxc_free_iomux(MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT2); + /*RDATA[3] */ + mxc_free_iomux(MX51_PIN_DISP2_DAT0, IOMUX_CONFIG_ALT2); + /*RX_ER */ + mxc_free_iomux(MX51_PIN_DISP2_DAT1, IOMUX_CONFIG_ALT2); + /*TDATA[1] */ + mxc_free_iomux(MX51_PIN_DISP2_DAT6, IOMUX_CONFIG_ALT2); + /*TDATA[2] */ + mxc_free_iomux(MX51_PIN_DISP2_DAT7, IOMUX_CONFIG_ALT2); + /*TDATA[3] */ + mxc_free_iomux(MX51_PIN_DISP2_DAT8, IOMUX_CONFIG_ALT2); + /*TX_EN */ + mxc_free_iomux(MX51_PIN_DISP2_DAT9, IOMUX_CONFIG_ALT2); + /*COL */ + mxc_free_iomux(MX51_PIN_DISP2_DAT10, IOMUX_CONFIG_ALT2); + /*RX_CLK */ + mxc_free_iomux(MX51_PIN_DISP2_DAT11, IOMUX_CONFIG_ALT2); + /*RX_DV */ + mxc_free_iomux(MX51_PIN_DISP2_DAT12, IOMUX_CONFIG_ALT2); + /*TX_CLK */ + mxc_free_iomux(MX51_PIN_DISP2_DAT13, IOMUX_CONFIG_ALT2); + /*RDATA[0] */ + mxc_free_iomux(MX51_PIN_DISP2_DAT14, IOMUX_CONFIG_ALT2); + /*TDATA[0] */ + mxc_free_iomux(MX51_PIN_DISP2_DAT15, IOMUX_CONFIG_ALT2); + /*reset */ + mxc_free_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_GPIO); + +} + +EXPORT_SYMBOL(gpio_fec_inactive); + +void gpio_spdif_active(void) +{ + mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_GPIO1_7, + PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | + PAD_CTL_SRE_FAST); +} + +EXPORT_SYMBOL(gpio_spdif_active); + +void gpio_spdif_inactive(void) +{ + mxc_free_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT2); + +} + +EXPORT_SYMBOL(gpio_spdif_inactive); + +int headphone_det_status(void) +{ + return mxc_get_gpio_datain(MX51_PIN_EIM_A26); +} + +EXPORT_SYMBOL(headphone_det_status); diff -urN linux-2.6.26/arch/arm/mach-mx51/mx51_pins.h linux-2.6.26-lab126/arch/arm/mach-mx51/mx51_pins.h --- linux-2.6.26/arch/arm/mach-mx51/mx51_pins.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/mx51_pins.h 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,361 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_MX51_PINS_H__ +#define __ASM_ARCH_MXC_MX51_PINS_H__ + +/*! + * @file arch-mxc/mx51_pins.h + * + * @brief MX51 I/O Pin List + * + * @ingroup GPIO_MX51 + */ + +#ifndef __ASSEMBLY__ + +/*! + * @name IOMUX/PAD Bit field definitions + */ + +/*! @{ */ + +/*! + * In order to identify pins more effectively, each mux-controlled pin's + * enumerated value is constructed in the following way: + * + * ------------------------------------------------------------------- + * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0 + * ------------------------------------------------------------------- + * IO_P | IO_I | GPIO_I | PAD_I | MUX_I + * ------------------------------------------------------------------- + * + * Bit 0 to 9 contains MUX_I used to identify the register + * offset (0-based. base is IOMUX_module_base) defined in the Section + * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The + * similar field definitions are used for the pad control register. + * For example, the MX51_PIN_ETM_D0 is defined in the enumeration: + * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I) + * It means the mux control register is at register offset 0x28. The pad control + * register offset is: 0x250 and also occupy the least significant bits + * within the register. + */ + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * MUX control register offset + */ +#define MUX_I 0 +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * PAD control register offset + */ +#define PAD_I 10 +/*! + * Starting bit position within each entry of \b iomux_pins to represent which + * mux mode is for GPIO (0-based) + */ +#define GPIO_I 21 + +#define NON_GPIO_PORT 0x7 +#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1) +#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1) +#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1) + +#define NON_MUX_I PIN_TO_MUX_MASK +#define MUX_I_START 0x001C +#define PAD_I_START 0x3F0 +#define INPUT_CTL_START 0x8C4 +#define INPUT_CTL_START_TO1 0x928 +#define MUX_I_END (PAD_I_START - 4) + +#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \ + (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ + ((mi) << MUX_I) | \ + ((pi - PAD_I_START) << PAD_I) | \ + ((ga) << GPIO_I)) + +#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \ + _MXC_BUILD_PIN(gp, gi, ga, mi, pi) + +#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \ + _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi) + +#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) +#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) +#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK) +#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2) + +/*! @} End IOMUX/PAD Bit field definitions */ + +/*! + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ +enum iomux_pins { + MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8), + MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8), + MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8), + MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8), + MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC), + MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC), + MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC), + MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC), + MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0), + MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0), + MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0), + MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0), + MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC), + MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC), + MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC), + MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC), + MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0), + MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4), + MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8), + MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC), + MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400), + MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404), + MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408), + MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C), + MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410), + MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414), + MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418), + MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C), + MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420), + MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424), + MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428), + MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C), + MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430), + MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434), + MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438), + MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C), + MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440), + MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444), + MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448), + MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C), + MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450), + MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454), + MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458), + MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C), + MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460), + MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464), + MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468), + MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C), + MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470), + MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474), + MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478), + MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C), + MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480), + MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484), + MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488), + MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C), + MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494), + MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0), + MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0), + MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4), + MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8), + MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC), + MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0), + MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4), + MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8), + MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC), + MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500), + MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504), + MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514), + MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND, + MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8), + MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC), + MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0), + MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518), + MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C), + MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520), + MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524), + MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528), + MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C), + MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530), + MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534), + MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538), + MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C), + MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540), + MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544), + MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548), + MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C), + MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550), + MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554), + MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558), + MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C), + MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560), + MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564), + MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568), + MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C), + MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570), + MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574), + MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578), + MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C), + MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580), + MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584), + MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588), + MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C), + MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590), + MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594), + MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598), + MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C), + MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0), + MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4), + MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8), + MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC), + MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0), + MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4), + MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8), + MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860), + MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC), + MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0), + MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4), + MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8), + MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC), + MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0), + MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4), + MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8), + MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC), + MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0), + MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4), + MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C), + MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8), + MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC), + MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0), + MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4), + MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8), + MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC), + MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600), + MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604), + MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608), + MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C), + MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610), + MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614), + MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618), + MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C), + MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620), + MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624), + MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628), + MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C), + MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630), + MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634), + MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638), + MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C), + MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640), + MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644), + MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648), + MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C), + MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650), + MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654), + MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658), + MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C), + MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660), + MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678), + MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C), + MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680), + MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684), + MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688), + MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C), + MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690), + MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694), + MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698), + MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C), + MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0), + MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4), + MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8), + MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC), + MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0), + MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4), + MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8), + MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC), + MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0), + MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4), + MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8), + MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC), + MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0), + MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4), + MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8), + MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC), + MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0), + MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4), + MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8), + MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC), + MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0), + MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4), + MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8), + MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC), + MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700), + MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704), + MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708), + MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C), + MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710), + MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714), + MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718), + MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C), + MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720), + MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724), + MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728), + MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C), + MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734), + MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C), + MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740), + MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744), + MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748), + MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C), + MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750), + MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754), + MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758), + MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C), + MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760), + MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764), + MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768), + MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C), + MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770), + MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774), + MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778), + MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C), + MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780), + MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784), + MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788), + MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C), + MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790), + MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794), + MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798), + MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C), + MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0), + MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4), + MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8), + MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC), + MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0), + MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4), + MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8), + MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC), + MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0), + MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4), + MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8), + MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC), + MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0), + MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4), + MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8), + MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC), + MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804), + MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808), + MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C), + MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810), + MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814), + MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818), +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_MXC_MX51_PINS_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx51/pm.c linux-2.6.26-lab126/arch/arm/mach-mx51/pm.c --- linux-2.6.26/arch/arm/mach-mx51/pm.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/pm.c 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,146 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include "crm_regs.h" + +static struct device *pm_dev; +struct clk *gpc_dvfs_clk; +extern void cpu_do_suspend_workaround(void); +extern void cpu_cortexa8_do_idle(u32); + +extern int iram_ready; + +static int mx51_suspend_enter(suspend_state_t state) +{ + if (tzic_enable_wake(0) != 0) + return -EAGAIN; + + if (gpc_dvfs_clk == NULL) + gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk"); + /* gpc clock is needed for SRPG */ + clk_enable(gpc_dvfs_clk); + switch (state) { + case PM_SUSPEND_MEM: + mxc_cpu_lp_set(STOP_POWER_OFF); + break; + case PM_SUSPEND_STANDBY: + mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); + break; + default: + return -EINVAL; + } + if (state == PM_SUSPEND_MEM) { + cpu_do_suspend_workaround(); + /*clear the EMPGC0/1 bits */ + __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); + __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); + } else { + if ((mxc_cpu_is_rev(CHIP_REV_2_0)) < 0) { + /* do cpu_idle_workaround */ + u32 l2_iram_addr = IDLE_IRAM_BASE_ADDR; + if (!iram_ready) + return; + if (l2_iram_addr > 0x1FFE8000) + cpu_cortexa8_do_idle(IO_ADDRESS(l2_iram_addr)); + } else { + cpu_do_idle(); + } + } + clk_disable(gpc_dvfs_clk); + + return 0; +} + +/* + * Called after processes are frozen, but before we shut down devices. + */ +static int mx51_suspend_prepare(void) +{ + return 0; +} + +/* + * Called before devices are re-setup. + */ +static void mx51_suspend_finish(void) +{ +} + +/* + * Called after devices are re-setup, but before processes are thawed. + */ +static void mx51_suspend_end(void) +{ +} + +static int mx51_pm_valid(suspend_state_t state) +{ + return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); +} + +struct platform_suspend_ops mx51_suspend_ops = { + .valid = mx51_pm_valid, + .prepare = mx51_suspend_prepare, + .enter = mx51_suspend_enter, + .finish = mx51_suspend_finish, + .end = mx51_suspend_end, +}; + + +static int __devinit mx51_pm_probe(struct platform_device *pdev) +{ + pm_dev = &pdev->dev; + return 0; +} + +static struct platform_driver mx51_pm_driver = { + .driver = { + .name = "mx51_pm", + }, + .probe = mx51_pm_probe, +}; + +static int __init pm_init(void) +{ + pr_info("Static Power Management for Freescale i.MX51\n"); + if (platform_driver_register(&mx51_pm_driver) != 0) { + printk(KERN_ERR "mx51_pm_driver register failed\n"); + return -ENODEV; + } + suspend_set_ops(&mx51_suspend_ops); + + printk(KERN_INFO "PM driver module loaded\n"); + + return 0; +} + + +static void __exit pm_cleanup(void) +{ + /* Unregister the device structure */ + platform_driver_unregister(&mx51_pm_driver); +} + +module_init(pm_init); +module_exit(pm_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("PM driver"); +MODULE_LICENSE("GPL"); + diff -urN linux-2.6.26/arch/arm/mach-mx51/sdma_script_code.h linux-2.6.26-lab126/arch/arm/mach-mx51/sdma_script_code.h --- linux-2.6.26/arch/arm/mach-mx51/sdma_script_code.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/sdma_script_code.h 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,170 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + +/*! + * @file sdma_script_code.h + * @brief This file contains functions of SDMA scripts code initialization + * + * The file was generated automatically. Based on sdma scripts library. + * + * @ingroup SDMA + */ +/******************************************************************************* + + SDMA RELEASE LABEL: "SS15_ELVIS" + +*******************************************************************************/ + +#ifndef __SDMA_SCRIPT_CODE_H__ +#define __SDMA_SCRIPT_CODE_H__ + +/*! +* SDMA ROM scripts start addresses and sizes +*/ + +#define start_ADDR 0 +#define start_SIZE 24 + +#define core_ADDR 80 +#define core_SIZE 232 + +#define common_ADDR 312 +#define common_SIZE 330 + +#define ap_2_ap_ADDR 642 +#define ap_2_ap_SIZE 41 + +#define app_2_mcu_ADDR 683 +#define app_2_mcu_SIZE 64 + +#define mcu_2_app_ADDR 747 +#define mcu_2_app_SIZE 70 + +#define uart_2_mcu_ADDR 817 +#define uart_2_mcu_SIZE 75 + +#define shp_2_mcu_ADDR 892 +#define shp_2_mcu_SIZE 69 + +#define mcu_2_shp_ADDR 961 +#define mcu_2_shp_SIZE 72 + +#define app_2_per_ADDR 1033 +#define app_2_per_SIZE 66 + +#define per_2_app_ADDR 1099 +#define per_2_app_SIZE 74 + +#define per_2_shp_ADDR 1173 +#define per_2_shp_SIZE 78 + +#define shp_2_per_ADDR 1251 +#define shp_2_per_SIZE 72 + +#define uartsh_2_mcu_ADDR 1323 +#define uartsh_2_mcu_SIZE 69 + +#define mcu_2_ata_ADDR 1392 +#define mcu_2_ata_SIZE 81 + +#define ata_2_mcu_ADDR 1473 +#define ata_2_mcu_SIZE 96 + +#define loop_DMAs_routines_ADDR 1569 +#define loop_DMAs_routines_SIZE 227 + +#define test_ADDR 1796 +#define test_SIZE 63 + +#define signature_ADDR 1023 +#define signature_SIZE 1 + +/*! +* SDMA RAM scripts start addresses and sizes +*/ + +#define ext_mem__ipu_ram_ADDR 6144 +#define ext_mem__ipu_ram_SIZE 123 + +#define mcu_2_spdif_ADDR 6267 +#define mcu_2_spdif_SIZE 59 + +#define uart_2_per_ADDR 6326 +#define uart_2_per_SIZE 73 + +#define uartsh_2_per_ADDR 6399 +#define uartsh_2_per_SIZE 67 + +/*! +* SDMA RAM image start address and size +*/ + +#define RAM_CODE_START_ADDR 6144 +#define RAM_CODE_SIZE 322 + +/*! +* Buffer that holds the SDMA RAM image +*/ +__attribute__ ((__aligned__(4))) +#ifndef CONFIG_XIP_KERNEL +const +#endif +static const short sdma_code[] = { + 0x0e70, 0x0611, 0x5616, 0xc13c, 0x7d2a, 0x5ade, 0x008e, 0xc14e, + 0x7c26, 0x5be0, 0x5ef0, 0x5ce8, 0x0688, 0x08ff, 0x0011, 0x28ff, + 0x00bc, 0x53f6, 0x05df, 0x7d0b, 0x6dc5, 0x03df, 0x7d03, 0x6bd5, + 0xd84f, 0x982b, 0x6b05, 0xc681, 0x7e27, 0x7f29, 0x982b, 0x6d01, + 0x03df, 0x7d05, 0x6bd5, 0xc6ab, 0x7e18, 0x7f1a, 0x982b, 0x6b05, + 0xc621, 0x7e07, 0x7f06, 0x52de, 0x53e6, 0xc159, 0x7dd7, 0x0200, + 0x9803, 0x0007, 0x6004, 0x680c, 0x53f6, 0x028e, 0x00a3, 0xc256, + 0x048b, 0x0498, 0x0454, 0x068a, 0x982b, 0x0207, 0x680c, 0x6ddf, + 0x0107, 0x68ff, 0x60d0, 0x9834, 0x0207, 0x68ff, 0x6d28, 0x0107, + 0x6004, 0x680c, 0x9834, 0x0007, 0x68ff, 0x60d0, 0x9834, 0x0288, + 0x03a5, 0x3b03, 0x3d03, 0x4d00, 0x7d0a, 0x0804, 0x00a5, 0x00da, + 0x7d1a, 0x02a0, 0x7b01, 0x65d8, 0x7eee, 0x65ff, 0x7eec, 0x0804, + 0x02d0, 0x7d11, 0x4b00, 0x7c0f, 0x008a, 0x3003, 0x6dcf, 0x6bdf, + 0x0015, 0x0015, 0x7b02, 0x65d8, 0x0000, 0x7edd, 0x63ff, 0x7edb, + 0x3a03, 0x6dcd, 0x6bdd, 0x008a, 0x7b02, 0x65d8, 0x0000, 0x7ed3, + 0x65ff, 0x7ed1, 0x0006, 0xc1d9, 0xc1e3, 0x57db, 0x52f3, 0x6a01, + 0x008f, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5deb, 0x56fb, 0x0478, + 0x7d28, 0x0479, 0x7c16, 0x0015, 0x0015, 0x0388, 0x620a, 0x0808, + 0x7801, 0x0217, 0x5a06, 0x7f1d, 0x620a, 0x0808, 0x7801, 0x0217, + 0x5a26, 0x7f17, 0x2301, 0x4b00, 0x7cf1, 0x0b70, 0x0311, 0x5313, + 0x98aa, 0x0015, 0x0015, 0x0015, 0x7804, 0x620b, 0x5a06, 0x620b, + 0x5a26, 0x7c07, 0x0000, 0x55eb, 0x4d00, 0x7d06, 0xc1fa, 0x57db, + 0x9880, 0x0007, 0x680c, 0xc213, 0xc20a, 0x987d, 0xc1e3, 0x57db, + 0x52f3, 0x6ad5, 0x56fb, 0x028e, 0x1a94, 0x6ac3, 0x62c8, 0x0269, + 0x7d1e, 0x1e94, 0x6ee3, 0x62d0, 0x5aeb, 0x62c8, 0x0248, 0x6ed3, + 0x6ac8, 0x2694, 0x52eb, 0x6ad5, 0x6ee3, 0x62c8, 0x026e, 0x7d27, + 0x6ac8, 0x7f23, 0x2501, 0x4d00, 0x7d26, 0x028e, 0x1a98, 0x6ac3, + 0x62c8, 0x6ec3, 0x0260, 0x7df1, 0x62d0, 0xc27a, 0x98fb, 0x6ee3, + 0x008f, 0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x62c8, 0x026e, + 0x7d0e, 0x6ac8, 0x7f0a, 0x2001, 0x7cf9, 0x6add, 0x7f06, 0x0000, + 0x4d00, 0x7d09, 0xc1fa, 0x57db, 0x98ba, 0x0007, 0x6aff, 0x62d0, + 0xc27a, 0x0458, 0x0454, 0x6add, 0x7ff8, 0xc20a, 0x98b7, 0xc1d9, + 0xc1e3, 0x57db, 0x52f3, 0x6ad5, 0x56fb, 0x028e, 0x1a94, 0x5202, + 0x0269, 0x7d17, 0x1e94, 0x5206, 0x0248, 0x5a06, 0x2694, 0x5206, + 0x026e, 0x7d26, 0x6ac8, 0x7f22, 0x2501, 0x4d00, 0x7d27, 0x028e, + 0x1a98, 0x5202, 0x0260, 0x7df3, 0x6add, 0x7f18, 0x62d0, 0xc27a, + 0x993e, 0x008f, 0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5206, + 0x026e, 0x7d0e, 0x6ac8, 0x7f0a, 0x2001, 0x7cf9, 0x6add, 0x7f06, + 0x0000, 0x4d00, 0x7d0b, 0xc1fa, 0x57db, 0x9904, 0x0007, 0x6aff, + 0x6add, 0x7ffc, 0x62d0, 0xc27a, 0x0458, 0x0454, 0x6add, 0x7ff6, + 0xc20a, 0x9901 +}; +#endif diff -urN linux-2.6.26/arch/arm/mach-mx51/serial.c linux-2.6.26-lab126/arch/arm/mach-mx51/serial.c --- linux-2.6.26/arch/arm/mach-mx51/serial.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/serial.c 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,169 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @file mach-mx51/serial.c + * + * @brief This file contains the UART initiliazation. + * + * @ingroup MSL_MX51 + */ +#include +#include +#include +#include +#include +#include +#include "serial.h" +#include "board-mx51_3stack.h" + +#if defined(CONFIG_SERIAL_MXC) || defined(CONFIG_SERIAL_MXC_MODULE) + +/*! + * This is an array where each element holds information about a UART port, + * like base address of the UART, interrupt numbers etc. This structure is + * passed to the serial_core.c file. Based on which UART is used, the core file + * passes back the appropriate port structure as an argument to the control + * functions. + */ +static uart_mxc_port mxc_ports[] = { + [0] = { + .port = { + .membase = (void *)IO_ADDRESS(UART1_BASE_ADDR), + .mapbase = UART1_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART1_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 0, + }, + .ints_muxed = UART1_MUX_INTS, + .irqs = {UART1_INT2, UART1_INT3}, + .mode = UART1_MODE, + .ir_mode = UART1_IR, + .enabled = UART1_ENABLED, + .hardware_flow = UART1_HW_FLOW, + .cts_threshold = UART1_UCR4_CTSTL, + .dma_enabled = UART1_DMA_ENABLE, + .dma_rxbuf_size = UART1_DMA_RXBUFSIZE, + .rx_threshold = UART1_UFCR_RXTL, + .tx_threshold = UART1_UFCR_TXTL, + .shared = UART1_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART1_TX, + .dma_rx_id = MXC_DMA_UART1_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, + [1] = { + .port = { + .membase = (void *)IO_ADDRESS(UART2_BASE_ADDR), + .mapbase = UART2_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART2_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 1, + }, + .ints_muxed = UART2_MUX_INTS, + .irqs = {UART2_INT2, UART2_INT3}, + .mode = UART2_MODE, + .ir_mode = UART2_IR, + .enabled = UART2_ENABLED, + .hardware_flow = UART2_HW_FLOW, + .cts_threshold = UART2_UCR4_CTSTL, + .dma_enabled = UART2_DMA_ENABLE, + .dma_rxbuf_size = UART2_DMA_RXBUFSIZE, + .rx_threshold = UART2_UFCR_RXTL, + .tx_threshold = UART2_UFCR_TXTL, + .shared = UART2_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART2_TX, + .dma_rx_id = MXC_DMA_UART2_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, + [2] = { + .port = { + .membase = (void *)IO_ADDRESS(UART3_BASE_ADDR), + .mapbase = UART3_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART3_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 2, + }, + .ints_muxed = UART3_MUX_INTS, + .irqs = {UART3_INT2, UART3_INT3}, + .mode = UART3_MODE, + .ir_mode = UART3_IR, + .enabled = UART3_ENABLED, + .hardware_flow = UART3_HW_FLOW, + .cts_threshold = UART3_UCR4_CTSTL, + .dma_enabled = UART3_DMA_ENABLE, + .dma_rxbuf_size = UART3_DMA_RXBUFSIZE, + .rx_threshold = UART3_UFCR_RXTL, + .tx_threshold = UART3_UFCR_TXTL, + .shared = UART3_SHARED_PERI, + .dma_tx_id = MXC_DMA_UART3_TX, + .dma_rx_id = MXC_DMA_UART3_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, +}; + +static struct platform_device mxc_uart_device1 = { + .name = "mxcintuart", + .id = 0, + .dev = { + .platform_data = &mxc_ports[0], + }, +}; + +static struct platform_device mxc_uart_device2 = { + .name = "mxcintuart", + .id = 1, + .dev = { + .platform_data = &mxc_ports[1], + }, +}; + +static struct platform_device mxc_uart_device3 = { + .name = "mxcintuart", + .id = 2, + .dev = { + .platform_data = &mxc_ports[2], + }, +}; + +static int __init mxc_init_uart(void) +{ + /* Register all the MXC UART platform device structures */ + platform_device_register(&mxc_uart_device1); + platform_device_register(&mxc_uart_device2); + + /* Grab ownership of shared UARTs 3 and 4, only when enabled */ +#if UART3_ENABLED == 1 +#if UART3_DMA_ENABLE == 1 + spba_take_ownership(UART3_SHARED_PERI, (SPBA_MASTER_A | SPBA_MASTER_C)); +#else + spba_take_ownership(UART3_SHARED_PERI, SPBA_MASTER_A); +#endif /* UART3_DMA_ENABLE */ + platform_device_register(&mxc_uart_device3); +#endif /* UART3_ENABLED */ + + return 0; +} + +#else +static int __init mxc_init_uart(void) +{ + return 0; +} +#endif + +arch_initcall(mxc_init_uart); diff -urN linux-2.6.26/arch/arm/mach-mx51/serial.h linux-2.6.26-lab126/arch/arm/mach-mx51/serial.h --- linux-2.6.26/arch/arm/mach-mx51/serial.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/serial.h 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,127 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ARCH_ARM_MACH_MX51_SERIAL_H__ +#define __ARCH_ARM_MACH_MX51_SERIAL_H__ + +#include + +/* UART 1 configuration */ +/*! + * This option allows to choose either an interrupt-driven software controlled + * hardware flow control (set this option to 0) or hardware-driven hardware + * flow control (set this option to 1). + */ +/* UART used as wakeup source */ +#define UART1_HW_FLOW 0 +/*! + * This specifies the threshold at which the CTS pin is deasserted by the + * RXFIFO. Set this value in Decimal to anything from 0 to 32 for + * hardware-driven hardware flow control. Read the HW spec while specifying + * this value. When using interrupt-driven software controlled hardware + * flow control set this option to -1. + */ +#define UART1_UCR4_CTSTL 16 +/*! + * This is option to enable (set this option to 1) or disable DMA data transfer + */ +#define UART1_DMA_ENABLE 0 +/*! + * Specify the size of the DMA receive buffer. The minimum buffer size is 512 + * bytes. The buffer size should be a multiple of 256. + */ +#define UART1_DMA_RXBUFSIZE 1024 +/*! + * Specify the MXC UART's Receive Trigger Level. This controls the threshold at + * which a maskable interrupt is generated by the RxFIFO. Set this value in + * Decimal to anything from 0 to 32. Read the HW spec while specifying this + * value. + */ +#define UART1_UFCR_RXTL 16 +/*! + * Specify the MXC UART's Transmit Trigger Level. This controls the threshold at + * which a maskable interrupt is generated by the TxFIFO. Set this value in + * Decimal to anything from 0 to 32. Read the HW spec while specifying this + * value. + */ +#define UART1_UFCR_TXTL 16 +/* UART 2 configuration */ +#define UART2_HW_FLOW 0 +#define UART2_UCR4_CTSTL -1 +#define UART2_DMA_ENABLE 0 +#define UART2_DMA_RXBUFSIZE 512 +#define UART2_UFCR_RXTL 16 +#define UART2_UFCR_TXTL 16 +/* UART 3 configuration */ +#define UART3_HW_FLOW 1 +#define UART3_UCR4_CTSTL 16 +#define UART3_DMA_ENABLE 1 +#define UART3_DMA_RXBUFSIZE 1024 +#define UART3_UFCR_RXTL 16 +#define UART3_UFCR_TXTL 16 +/* + * UART Chip level Configuration that a user may not have to edit. These + * configuration vary depending on how the UART module is integrated with + * the ARM core + */ +/* + * Is the MUXED interrupt output sent to the ARM core + */ +#define INTS_NOTMUXED 0 +#define INTS_MUXED 1 +/* UART 1 configuration */ +/*! + * This define specifies whether the muxed ANDed interrupt line or the + * individual interrupts from the UART port is integrated with the ARM core. + * There exists a define like this for each UART port. Valid values that can + * be used are \b INTS_NOTMUXED or \b INTS_MUXED. + */ +#define UART1_MUX_INTS INTS_MUXED +/*! + * This define specifies the transmitter interrupt number or the interrupt + * number of the ANDed interrupt in case the interrupts are muxed. There exists + * a define like this for each UART port. + */ +#define UART1_INT1 MXC_INT_UART1 +/*! + * This define specifies the receiver interrupt number. If the interrupts of + * the UART are muxed, then we specify here a dummy value -1. There exists a + * define like this for each UART port. + */ +#define UART1_INT2 -1 +/*! + * This specifies the master interrupt number. If the interrupts of the UART + * are muxed, then we specify here a dummy value of -1. There exists a define + * like this for each UART port. + */ +#define UART1_INT3 -1 +/*! + * This specifies if the UART is a shared peripheral. It holds the shared + * peripheral number if it is shared or -1 if it is not shared. There exists + * a define like this for each UART port. + */ +#define UART1_SHARED_PERI -1 +/* UART 2 configuration */ +#define UART2_MUX_INTS INTS_MUXED +#define UART2_INT1 MXC_INT_UART2 +#define UART2_INT2 -1 +#define UART2_INT3 -1 +#define UART2_SHARED_PERI -1 +/* UART 3 configuration */ +#define UART3_MUX_INTS INTS_MUXED +#define UART3_INT1 MXC_INT_UART3 +#define UART3_INT2 -1 +#define UART3_INT3 -1 +#define UART3_SHARED_PERI SPBA_UART3 + +#endif /* __ARCH_ARM_MACH_MX51_SERIAL_H__ */ diff -urN linux-2.6.26/arch/arm/mach-mx51/suspend.S linux-2.6.26-lab126/arch/arm/mach-mx51/suspend.S --- linux-2.6.26/arch/arm/mach-mx51/suspend.S 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/suspend.S 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,152 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +#include +#include +#include +#include +#include +#include +#include + +#define ARM_CTRL_DCACHE 1 << 2 +#define ARM_CTRL_ICACHE 1 << 12 +#define ARM_AUXCR_L2EN 1 << 1 + + +/* + * cpu_do_suspend_workaround() + * + * Suspend the processor (eg, wait for interrupt). + * + * IRQs are already disabled. + */ +ENTRY(cpu_do_suspend_workaround) + stmfd sp!, {r4,r5,r7,r9,r10,r11} @ Save registers + + /* Disable L1 caches */ + mrc p15, 0, r0, c1, c0, 0 @ R0 = system control reg + bic r0, r0, #ARM_CTRL_ICACHE @ Disable ICache + bic r0, r0, #ARM_CTRL_DCACHE @ Disable DCache + mcr p15, 0, r0, c1, c0, 0 @ Update system control reg + + mrc p15, 1, r0, c0, c0, 1 @ Read CLIDR + ands r3, r0, #0x7000000 @ Isolate level of coherency + mov r3, r3, lsr #23 @ Cache level value (naturally aligned) + beq FinishedClean + mov r10, #0 +Loop1Clean: + add r2, r10, r10, lsr #1 @ Work out cache level + mov r1, r0, lsr r2 @ R0 bottom 3 bits = Cache Type for this level + and r1, r1, #7 @ Get those 3 bits alone + cmp r1, #2 + blt SkipClean @ No cache or only instruction cache at this level + mcr p15, 2, r10, c0, c0, 0 @ Write the Cache Size selection register + mov r1, #0 + .long 0xF57FF06F @ ISB + mrc p15, 1, r1, c0, c0, 0 @ Reads current Cache Size ID register + and r2, r1, #7 @ Extract the line length field + add r2, r2, #4 @ Add 4 for the line length offset (log2 16 bytes) + ldr r4, =0x3FF + ands r4, r4, r1, lsr #3 @ R4 is the max number on the way size (right aligned) + clz r5, r4 @ R5 is the bit position of the way size increment + ldr r7, =0x00007FFF + ands r7, r7, r1, lsr #13 @ R7 is the max number of the index size (right aligned) +Loop2Clean: + mov r9, r4 @ R9 working copy of the max way size (right aligned) +Loop3Clean: + orr r11, r10, r9, lsl r5 @ Factor in the way number and cache number into R11 + orr r11, r11, r7, lsl r2 @ Factor in the index number + mcr p15, 0, r11, c7, c14, 2 @ Clean and invalidate by set/way + subs r9, r9, #1 @ Decrement the way number + bge Loop3Clean + subs r7, r7, #1 @ Decrement the index + bge Loop2Clean +SkipClean: + add r10, r10, #2 @ Increment the cache number + cmp r3, r10 + bgt Loop1Clean + +FinishedClean: + + /* Disable L2 cache */ + mrc p15, 0, r0, c1, c0, 1 @ R0 = auxiliary control reg + bic r0, r0, #ARM_AUXCR_L2EN @ Disable L2 cache + mcr p15, 0, r0, c1, c0, 1 @ Update aux control reg + + .long 0xe320f003 @ Opcode for WFI + + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ Invalidate inst cache + + /* Invalidate data caches */ + mrc p15, 1, r0, c0, c0, 1 @ Read CLIDR + ands r3, r0, #0x7000000 @ Isolate level of coherency + mov r3, r3, lsr #23 @ Cache level value (naturally aligned) + beq FinishedInvalidate + mov r10, #0 +Loop1Invalidate: + add r2, r10, r10, lsr #1 @ Work out cache level + mov r1, r0, lsr r2 @ R0 bottom 3 bits = Cache Type for this level + and r1, r1, #7 @ Get those 3 bits alone + cmp r1, #2 + blt SkipInvalidate @ No cache or only instruction cache at this level + mcr p15, 2, r10, c0, c0, 0 @ Write the Cache Size selection register + mov r1, #0 + .long 0xF57FF06F @ ISB + mrc p15, 1, r1, c0, c0, 0 @ Reads current Cache Size ID register + and r2, r1, #7 @ Extract the line length field + add r2, r2, #4 @ Add 4 for the line length offset (log2 16 bytes) + ldr r4, =0x3FF + ands r4, r4, r1, lsr #3 @ R4 is the max number on the way size (right aligned) + clz r5, r4 @ R5 is the bit position of the way size increment + ldr r7, =0x00007FFF + ands r7, r7, r1, lsr #13 @ R7 is the max number of the index size (right aligned) +Loop2Invalidate: + mov r9, r4 @ R9 working copy of the max way size (right aligned) +Loop3Invalidate: + orr r11, r10, r9, lsl r5 @ Factor in the way number and cache number into R11 + orr r11, r11, r7, lsl r2 @ Factor in the index number + mcr p15, 0, r11, c7, c6, 2 @ Invalidate by set/way + subs r9, r9, #1 @ Decrement the way number + bge Loop3Invalidate + subs r7, r7, #1 @ Decrement the index + bge Loop2Invalidate +SkipInvalidate: + add r10, r10, #2 @ Increment the cache number + cmp r3, r10 + bgt Loop1Invalidate + +FinishedInvalidate: + + /* Enable L2 cache */ + mrc p15, 0, r0, c1, c0, 1 @ R0 = auxiliary control reg + orr r0, r0, #ARM_AUXCR_L2EN @ Enable L2 cache + mcr p15, 0, r0, c1, c0, 1 @ Update aux control reg + + /* Enable L1 caches */ + mrc p15, 0, r0, c1, c0, 0 @ R0 = system control reg + orr r0, r0, #ARM_CTRL_ICACHE @ Enable ICache + orr r0, r0, #ARM_CTRL_DCACHE @ Enable DCache + mcr p15, 0, r0, c1, c0, 0 @ Update system control reg + + /* Restore registers */ + ldmfd sp!, {r4,r5,r7,r9,r10,r11} + mov pc, lr + + .type cpu_do_suspend, #object +ENTRY(cpu_do_suspend) + .word cpu_do_suspend_workaround + .size cpu_do_suspend_workaround, . - cpu_do_suspend_workaround + + diff -urN linux-2.6.26/arch/arm/mach-mx51/system.c linux-2.6.26-lab126/arch/arm/mach-mx51/system.c --- linux-2.6.26/arch/arm/mach-mx51/system.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/system.c 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,191 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include "crm_regs.h" + +/*! + * @defgroup MSL_MX51 i.MX51 Machine Specific Layer (MSL) + */ + +/*! + * @file mach-mx51/system.c + * @brief This file contains idle and reset functions. + * + * @ingroup MSL_MX51 + */ + +extern int mxc_jtag_enabled; +extern int iram_ready; +static struct clk *gpc_dvfs_clk; + +extern void cpu_cortexa8_do_idle(u32 addr); + + +/* set cpu low power mode before WFI instruction */ +void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) +{ + u32 plat_lpc, gpc_pgr, arm_srpgcr, ccm_clpcr; + u32 empgc0, empgc1; + int stop_mode; + + /* always allow platform to issue a deep sleep mode request */ + plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) & + ~(MXC_CORTEXA8_PLAT_LPC_DSM); + ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); + arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR); + empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR); + empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR); + + gpc_pgr = __raw_readl(MXC_GPC_PGR) & ~(MXC_GPC_PGR_ARMPG_MASK); + + switch (mode) { + case WAIT_CLOCKED: + break; + case WAIT_UNCLOCKED: + ccm_clpcr |= (0x1 << MXC_CCM_CLPCR_LPM_OFFSET); + break; + case WAIT_UNCLOCKED_POWER_OFF: + case STOP_POWER_OFF: + plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM + | MXC_CORTEXA8_PLAT_LPC_DBG_DSM; + if (mode == WAIT_UNCLOCKED_POWER_OFF) { + ccm_clpcr |= (0x1 << MXC_CCM_CLPCR_LPM_OFFSET); + ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY; + stop_mode = 0; + } else { + ccm_clpcr |= (0x2 << MXC_CCM_CLPCR_LPM_OFFSET); + ccm_clpcr |= (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET); + ccm_clpcr |= MXC_CCM_CLPCR_VSTBY; + ccm_clpcr |= MXC_CCM_CLPCR_SBYOS; + stop_mode = 1; + } + + arm_srpgcr |= MXC_SRPGCR_PCR; + gpc_pgr |= (0x1 << MXC_GPC_PGR_ARMPG_OFFSET); + if (stop_mode) { + empgc0 |= MXC_SRPGCR_PCR; + empgc1 |= MXC_SRPGCR_PCR; + } + + if (tzic_enable_wake(1) != 0) + return; + break; + case STOP_POWER_ON: + ccm_clpcr |= (0x2 << MXC_CCM_CLPCR_LPM_OFFSET); + break; + default: + printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode); + return; + } + + __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC); + __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); + __raw_writel(gpc_pgr, MXC_GPC_PGR); + __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); + __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); + if (stop_mode) { + __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR); + __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR); + } +} + +void mxc_pg_enable(struct platform_device *pdev) +{ + if (pdev == NULL) + return; + + if (strcmp(pdev->name, "mxc_ipu") == 0) { + __raw_writel(MXC_PGCR_PCR, MXC_PGC_IPU_PGCR); + __raw_writel(MXC_PGSR_PSR, MXC_PGC_IPU_PGSR); + } else if (strcmp(pdev->name, "mxc_vpu") == 0) { + __raw_writel(MXC_PGCR_PCR, MXC_PGC_VPU_PGCR); + __raw_writel(MXC_PGSR_PSR, MXC_PGC_VPU_PGSR); + } +} + +EXPORT_SYMBOL(mxc_pg_enable); + +void mxc_pg_disable(struct platform_device *pdev) +{ + if (pdev == NULL) + return; + + if (strcmp(pdev->name, "mxc_ipu") == 0) { + __raw_writel(0x0, MXC_PGC_IPU_PGCR); + if (__raw_readl(MXC_PGC_IPU_PGSR) & MXC_PGSR_PSR) + dev_dbg(&pdev->dev, "power gating successful\n"); + __raw_writel(MXC_PGSR_PSR, MXC_PGC_IPU_PGSR); + } else if (strcmp(pdev->name, "mxc_vpu") == 0) { + __raw_writel(0x0, MXC_PGC_VPU_PGCR); + if (__raw_readl(MXC_PGC_VPU_PGSR) & MXC_PGSR_PSR) + dev_dbg(&pdev->dev, "power gating successful\n"); + __raw_writel(MXC_PGSR_PSR, MXC_PGC_VPU_PGSR); + } +} + +EXPORT_SYMBOL(mxc_pg_disable); + +/* To change the idle power mode, need to set arch_idle_mode to a different + * power mode as in enum mxc_cpu_pwr_mode. + * May allow dynamically changing the idle mode. + */ +static int arch_idle_mode = WAIT_UNCLOCKED_POWER_OFF; +/*! + * This function puts the CPU into idle mode. It is called by default_idle() + * in process.c file. + */ +void arch_idle(void) +{ + if (likely(!mxc_jtag_enabled)) { + if (gpc_dvfs_clk == NULL) + gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk"); + /* gpc clock is needed for SRPG */ + clk_enable(gpc_dvfs_clk); + mxc_cpu_lp_set(arch_idle_mode); + if ((mxc_cpu_is_rev(CHIP_REV_2_0)) < 0) { + u32 l2_iram_addr = IDLE_IRAM_BASE_ADDR; + + if (!iram_ready) + return; + + if (l2_iram_addr > 0x1FFE8000) + cpu_cortexa8_do_idle(IO_ADDRESS(l2_iram_addr)); + } else { + cpu_do_idle(); + } + clk_disable(gpc_dvfs_clk); + } +} + +/* + * This function resets the system. It is called by machine_restart(). + * + * @param mode indicates different kinds of resets + */ +void arch_reset(char mode) +{ + /* Workaround to reset NFC_CONFIG3 register + * due to the chip warm reset does not reset it + */ + __raw_writel(0x20600, IO_ADDRESS(NFC_BASE_ADDR) + 0x28); + + /* Assert SRS signal */ + mxc_wd_reset(); +} diff -urN linux-2.6.26/arch/arm/mach-mx51/usb.h linux-2.6.26-lab126/arch/arm/mach-mx51/usb.h --- linux-2.6.26/arch/arm/mach-mx51/usb.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/usb.h 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,116 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +extern int usbotg_init(struct platform_device *pdev); +extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata); +extern int gpio_usbotg_hs_active(void); +extern void gpio_usbotg_hs_inactive(void); +extern struct platform_device *host_pdev_register(struct resource *res, + int n_res, struct fsl_usb2_platform_data *config); + +extern int fsl_usb_host_init(struct platform_device *pdev); +extern void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata); +extern int gpio_usbh1_active(void); +extern void gpio_usbh1_inactive(void); +extern int gpio_usbotg_utmi_active(void); +extern void gpio_usbotg_utmi_inactive(void); +static int usbotg_init_ext(struct platform_device *pdev); +static void usbotg_uninit_ext(struct fsl_usb2_platform_data *pdata); + +/* + * Determine which platform_data struct to use for the DR controller, + * based on which transceiver is configured. + * PDATA is a pointer to it. + */ +#if defined(CONFIG_ISP1301_MXC) +static struct fsl_usb2_platform_data __maybe_unused dr_1301_config; +#define PDATA (&dr_1301_config) +#elif defined(CONFIG_MC13783_MXC) +static struct fsl_usb2_platform_data __maybe_unused dr_13783_config; +#define PDATA (&dr_13783_config) +#elif defined(CONFIG_UTMI_MXC) +static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config; +#define PDATA (&dr_utmi_config) +#endif + + +/* + * Used to set pdata->operating_mode before registering the platform_device. + * If OTG is configured, the controller operates in OTG mode, + * otherwise it's either host or device. + */ +#ifdef CONFIG_USB_OTG +#define DR_UDC_MODE FSL_USB2_DR_OTG +#define DR_HOST_MODE FSL_USB2_DR_OTG +#else +#define DR_UDC_MODE FSL_USB2_DR_DEVICE +#define DR_HOST_MODE FSL_USB2_DR_HOST +#endif + + +#ifdef CONFIG_USB_EHCI_ARC_OTG +static inline void dr_register_host(struct resource *r, int rs) +{ + PDATA->operating_mode = DR_HOST_MODE; + host_pdev_register(r, rs, PDATA); +} +#else +static inline void dr_register_host(struct resource *r, int rs) +{ +} +#endif + +#ifdef CONFIG_USB_GADGET_ARC +static struct platform_device dr_udc_device; + +static inline void dr_register_udc(void) +{ + PDATA->operating_mode = DR_UDC_MODE; + dr_udc_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_udc_device)) + printk(KERN_ERR "usb: can't register DR gadget\n"); + else + printk(KERN_INFO "usb: DR gadget (%s) registered\n", + PDATA->transceiver); +} +#else +static inline void dr_register_udc(void) +{ +} +#endif + +#ifdef CONFIG_USB_OTG +static struct platform_device dr_otg_device; + +/* + * set the proper operating_mode and + * platform_data pointer, then register the + * device. + */ +static inline void dr_register_otg(void) +{ + PDATA->operating_mode = FSL_USB2_DR_OTG; + dr_otg_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_otg_device)) + printk(KERN_ERR "usb: can't register otg device\n"); + else + printk(KERN_INFO "usb: DR OTG registered\n"); +} +#else +static inline void dr_register_otg(void) +{ +} +#endif diff -urN linux-2.6.26/arch/arm/mach-mx51/usb_dr.c linux-2.6.26-lab126/arch/arm/mach-mx51/usb_dr.c --- linux-2.6.26/arch/arm/mach-mx51/usb_dr.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/usb_dr.c 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,140 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include "usb.h" + +/* + * platform data structs + * - Which one to use is determined by CONFIG options in usb.h + * - operating_mode plugged at run time + */ +static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = { + .name = "DR", + .platform_init = usbotg_init_ext, + .platform_uninit = usbotg_uninit_ext, + .phy_mode = FSL_USB2_PHY_UTMI_WIDE, + .power_budget = 500, /* 500 mA max power */ + .gpio_usb_active = gpio_usbotg_hs_active, + .gpio_usb_inactive = gpio_usbotg_hs_inactive, + .transceiver = "utmi", +}; + + +/* + * resources + */ +static struct resource otg_resources[] = { + [0] = { + .start = (u32)(USB_OTGREGS_BASE), + .end = (u32)(USB_OTGREGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_USB_OTG, + .flags = IORESOURCE_IRQ, + }, +}; + + +static u64 dr_udc_dmamask = ~(u32) 0; +static void dr_udc_release(struct device *dev) +{ +} + +static u64 dr_otg_dmamask = ~(u32) 0; +static void dr_otg_release(struct device *dev) +{ +} + +/* + * platform device structs + * dev.platform_data field plugged at run time + */ +static struct platform_device dr_udc_device = { + .name = "fsl-usb2-udc", + .id = -1, + .dev = { + .release = dr_udc_release, + .dma_mask = &dr_udc_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), +}; + +static struct platform_device __maybe_unused dr_otg_device = { + .name = "fsl-usb2-otg", + .id = -1, + .dev = { + .release = dr_otg_release, + .dma_mask = &dr_otg_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), +}; + +/* Notes: configure USB clock*/ +static int usbotg_init_ext(struct platform_device *pdev) +{ + struct clk *usb_clk; + + usb_clk = clk_get(NULL, "usboh3_clk"); + clk_enable(usb_clk); + clk_put(usb_clk); + + usb_clk = clk_get(NULL, "usb_phy_clk"); + clk_enable(usb_clk); + clk_put(usb_clk); + + /*derive clock from oscillator */ + usb_clk = clk_get(NULL, "usb_utmi_clk"); + clk_disable(usb_clk); + clk_put(usb_clk); + + return usbotg_init(pdev); +} + +static void usbotg_uninit_ext(struct fsl_usb2_platform_data *pdata) +{ + struct clk *usb_clk; + + usb_clk = clk_get(NULL, "usboh3_clk"); + clk_disable(usb_clk); + clk_put(usb_clk); + + usb_clk = clk_get(NULL, "usb_phy_clk"); + clk_disable(usb_clk); + clk_put(usb_clk); + + usbotg_uninit(pdata); +} + +static int __init usb_dr_init(void) +{ + pr_debug("%s: \n", __func__); + + dr_register_otg(); + dr_register_host(otg_resources, ARRAY_SIZE(otg_resources)); + dr_register_udc(); + + return 0; +} + +module_init(usb_dr_init); diff -urN linux-2.6.26/arch/arm/mach-mx51/usb_h1.c linux-2.6.26-lab126/arch/arm/mach-mx51/usb_h1.c --- linux-2.6.26/arch/arm/mach-mx51/usb_h1.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/usb_h1.c 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,54 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include "usb.h" + +static struct fsl_usb2_platform_data usbh1_config = { + .name = "Host 1", + .platform_init = fsl_usb_host_init, + .platform_uninit = fsl_usb_host_uninit, + .operating_mode = FSL_USB2_MPH_HOST, + .phy_mode = FSL_USB2_PHY_ULPI, + .power_budget = 500, /* 500 mA max power */ + .gpio_usb_active = gpio_usbh1_active, + .gpio_usb_inactive = gpio_usbh1_inactive, + .transceiver = "isp1504", +}; + +static struct resource usbh1_resources[] = { + [0] = { + .start = (u32) (USB_H1REGS_BASE), + .end = (u32) (USB_H1REGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_USB_H1, + .flags = IORESOURCE_IRQ, + }, +}; + +static int __init usbh1_init(void) +{ + pr_debug("%s: \n", __func__); + + host_pdev_register(usbh1_resources, ARRAY_SIZE(usbh1_resources), + &usbh1_config); + return 0; +} + +module_init(usbh1_init); diff -urN linux-2.6.26/arch/arm/mach-mx51/usb_h2.c linux-2.6.26-lab126/arch/arm/mach-mx51/usb_h2.c --- linux-2.6.26/arch/arm/mach-mx51/usb_h2.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/usb_h2.c 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,57 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include "usb.h" +#include "iomux.h" + +static struct fsl_usb2_platform_data usbh2_config = { + .name = "Host 2", + .platform_init = fsl_usb_host_init, + .platform_uninit = fsl_usb_host_uninit, + .operating_mode = FSL_USB2_MPH_HOST, + .phy_mode = FSL_USB2_PHY_ULPI, + .power_budget = 500, /* 500 mA max power */ + .gpio_usb_active = gpio_usbh2_active, + .gpio_usb_inactive = gpio_usbh2_inactive, + .transceiver = "isp1504", +}; + +static struct resource usbh2_resources[] = { + [0] = { + .start = (u32) (USB_H2REGS_BASE), + .end = (u32) (USB_H2REGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_USB_H2, + .flags = IORESOURCE_IRQ, + }, +}; + +static int __init usbh2_init(void) +{ + pr_debug("%s: \n", __func__); + + host_pdev_register(usbh2_resources, ARRAY_SIZE(usbh2_resources), + &usbh2_config); + return 0; +} + +module_init(usbh2_init); + diff -urN linux-2.6.26/arch/arm/mach-mx51/wfi.S linux-2.6.26-lab126/arch/arm/mach-mx51/wfi.S --- linux-2.6.26/arch/arm/mach-mx51/wfi.S 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/mach-mx51/wfi.S 2010-08-10 04:14:04.000000000 -0400 @@ -0,0 +1,434 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +#include +#include +#include +#include +#include +#include +#include + +#define ARM_CTRL_DCACHE 1 << 2 +#define ARM_AUXCR_L2EN 1 << 1 +/* + * cpu_cortexa8_do_idle() + * + * Idle the processor (eg, wait for interrupt). + * + * IRQs are already disabled. + */ +ENTRY(cpu_cortexa8_do_idle) + + mrc p15, 0, r1, c1, c0, 1 @ R1 = auxiliary control reg + ands r2, r1, #ARM_AUXCR_L2EN @ Check if L2 is disabled + beq SkipL2Access + + mrc p15, 0, r2, c1, c0, 0 @ R2 = system control reg + bic r2, r2, #ARM_CTRL_DCACHE @ Disable DCache + mcr p15, 0, r2, c1, c0, 0 @ Update system control reg + + bic r1, r1, #ARM_AUXCR_L2EN @ Disable L2 cache + mcr p15, 0, r1, c1, c0, 1 @ Update aux control reg + + ldr r1, =(0x0 << 6) @ A[6] = 0 + mcr p15, 0, r1, c15, c9, 2 @ Read L2 tag RAM into L2 data 0 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x00] @ Save tag info + + ldr r1, =(0x1 << 6) @ A[6] = 1 + mcr p15, 0, r1, c15, c9, 2 @ Read L2 tag RAM into L2 data 0 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x04] @ Save tag info + + ldr r1, =(0x0 << 3) @ A[6:3] = b0000 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x08] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x0C] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x10] @ Store data info + + ldr r1, =(0x1 << 3) @ A[6:3] = b0001 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x14] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x18] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x1C] @ Store data info + + ldr r1, =(0x2 << 3) @ A[6:3] = b0010 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x20] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x24] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x28] @ Store data info + + ldr r1, =(0x3 << 3) @ A[6:3] = b0011 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x2C] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x30] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x34] @ Store data info + + ldr r1, =(0x4 << 3) @ A[6:3] = b0100 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x38] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x3C] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x40] @ Store data info + + ldr r1, =(0x5 << 3) @ A[6:3] = b0101 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x44] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x48] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x4C] @ Store data info + + ldr r1, =(0x6 << 3) @ A[6:3] = b0110 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x50] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x54] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x58] @ Store data info + + ldr r1, =(0x7 << 3) @ A[6:3] = b0111 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x5C] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x60] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x64] @ Store data info + + ldr r1, =(0x8 << 3) @ A[6:3] = b1000 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x68] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x6C] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x70] @ Store data info + + ldr r1, =(0x9 << 3) @ A[6:3] = b1001 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x74] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x78] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x7C] @ Store data info + + ldr r1, =(0xA << 3) @ A[6:3] = b1010 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x80] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x84] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x88] @ Store data info + + ldr r1, =(0xB << 3) @ A[6:3] = b1011 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x8C] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x90] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x94] @ Store data info + + ldr r1, =(0xC << 3) @ A[6:3] = b1100 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x98] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x9C] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0xA0] @ Store data info + + ldr r1, =(0xD << 3) @ A[6:3] = b1101 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0xA4] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0xA8] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0xAC] @ Store data info + + ldr r1, =(0xE << 3) @ A[6:3] = b1110 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0xB0] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0xB4] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0xB8] @ Store data info + + ldr r1, =(0xF << 3) @ A[6:3] = b1111 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0xBC] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0xC0] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0xC4] @ Store data info + + ldr r1, =(0x2 << 29) | (0x0 << 6) @ WAY = A[31:29] = 2, A[6] = 0 + mcr p15, 0, r1, c15, c9, 2 @ Read L2 tag RAM into L2 data 0 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0xC8] @ Save tag info + + ldr r1, =(0x2 << 29) | (0x1 << 6) @ WAY = A[31:29] = 2, A[6] = 1 + mcr p15, 0, r1, c15, c9, 2 @ Read L2 tag RAM into L2 data 0 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0xCC] @ Save tag info + + ldr r1, =(0x4 << 29) | (0x0 << 6) @ WAY = A[31:29] = 4, A[6] = 0 + mcr p15, 0, r1, c15, c9, 2 @ Read L2 tag RAM into L2 data 0 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0xD0] @ Save tag info + + ldr r1, =(0x4 << 29) | (0x1 << 6) @ WAY = A[31:29] = 4, A[6] = 1 + mcr p15, 0, r1, c15, c9, 2 @ Read L2 tag RAM into L2 data 0 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0xD4] @ Save tag info + + ldr r1, =(0x6 << 29) | (0x0 << 6) @ WAY = A[31:29] = 6, A[6] = 0 + mcr p15, 0, r1, c15, c9, 2 @ Read L2 tag RAM into L2 data 0 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0xD8] @ Save tag info + + ldr r1, =(0x6 << 29) | (0x1 << 6) @ WAY = A[31:29] = 6, A[6] = 1 + mcr p15, 0, r1, c15, c9, 2 @ Read L2 tag RAM into L2 data 0 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0xDC] @ Save tag info + + .long 0xe320f003 @ Opcode for WFI + + ldr r1, =(0x0 << 6) @ A[6] = 0 + ldr r2, [r0, #0x00] @ Load tag info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + mcr p15, 0, r1, c15, c8, 2 @ Write L2 data 0 register to L2 tag RAM + + ldr r1, =(0x1 << 6) @ A[6] = 1 + ldr r2, [r0, #0x04] @ Load tag info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + mcr p15, 0, r1, c15, c8, 2 @ Write L2 data 0 register to L2 tag RAM + + ldr r1, =(0x0 << 3) @ A[6:3] = b0000 + ldr r2, [r0, #0x08] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x0C] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x10] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x1 << 3) @ A[6:3] = b0001 + ldr r2, [r0, #0x14] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x18] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x1C] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x2 << 3) @ A[6:3] = b0010 + ldr r2, [r0, #0x20] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x24] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x28] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x3 << 3) @ A[6:3] = b0011 + ldr r2, [r0, #0x2C] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x30] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x34] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x4 << 3) @ A[6:3] = b0100 + ldr r2, [r0, #0x38] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x3C] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x40] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x5 << 3) @ A[6:3] = b0101 + ldr r2, [r0, #0x44] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x48] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x4C] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x6 << 3) @ A[6:3] = b0110 + ldr r2, [r0, #0x50] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x54] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x58] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x7 << 3) @ A[6:3] = b0111 + ldr r2, [r0, #0x5C] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x60] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x64] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x8 << 3) @ A[6:3] = b1000 + ldr r2, [r0, #0x68] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x6C] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x70] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x9 << 3) @ A[6:3] = b1001 + ldr r2, [r0, #0x74] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x78] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x7C] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0xA << 3) @ A[6:3] = b1010 + ldr r2, [r0, #0x80] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x84] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x88] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0xB << 3) @ A[6:3] = b1011 + ldr r2, [r0, #0x8C] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x90] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x94] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0xC << 3) @ A[6:3] = b1100 + ldr r2, [r0, #0x98] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x9C] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0xA0] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0xD << 3) @ A[6:3] = b1101 + ldr r2, [r0, #0xA4] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0xA8] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0xAC] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0xE << 3) @ A[6:3] = b1110 + ldr r2, [r0, #0xB0] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0xB4] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0xB8] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0xF << 3) @ A[6:3] = b1111 + ldr r2, [r0, #0xBC] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0xC0] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0xC4] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x2 << 29) | (0x0 << 6) @ WAY = A[31:29] = 2, A[6] = 0 + ldr r2, [r0, #0xC8] @ Load tag info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + mcr p15, 0, r1, c15, c8, 2 @ Write L2 data 0 register to L2 tag RAM + + ldr r1, =(0x2 << 29) | (0x1 << 6) @ WAY = A[31:29] = 2, A[6] = 1 + ldr r2, [r0, #0xCC] @ Load tag info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + mcr p15, 0, r1, c15, c8, 2 @ Write L2 data 0 register to L2 tag RAM + + ldr r1, =(0x4 << 29) | (0x0 << 6) @ WAY = A[31:29] = 4, A[6] = 0 + ldr r2, [r0, #0xD0] @ Load tag info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + mcr p15, 0, r1, c15, c8, 2 @ Write L2 data 0 register to L2 tag RAM + + ldr r1, =(0x4 << 29) | (0x1 << 6) @ WAY = A[31:29] = 4, A[6] = 1 + ldr r2, [r0, #0xD4] @ Load tag info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + mcr p15, 0, r1, c15, c8, 2 @ Write L2 data 0 register to L2 tag RAM + + ldr r1, =(0x6 << 29) | (0x0 << 6) @ WAY = A[31:29] = 6, A[6] = 0 + ldr r2, [r0, #0xD8] @ Load tag info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + mcr p15, 0, r1, c15, c8, 2 @ Write L2 data 0 register to L2 tag RAM + + ldr r1, =(0x6 << 29) | (0x1 << 6) @ WAY = A[31:29] = 6, A[6] = 1 + ldr r2, [r0, #0xDC] @ Load tag info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + mcr p15, 0, r1, c15, c8, 2 @ Write L2 data 0 register to L2 tag RAM + + mrc p15, 0, r1, c1, c0, 1 @ R1 = auxiliary control reg + orr r1, r1, #ARM_AUXCR_L2EN @ Enable L2 cache + mcr p15, 0, r1, c1, c0, 1 @ Update aux control reg + + mrc p15, 0, r2, c1, c0, 0 @ R2 = system control reg + orr r2, r2, #ARM_CTRL_DCACHE @ Enable DCache + mcr p15, 0, r2, c1, c0, 0 @ Update system control reg + + b Done + +SkipL2Access: + .long 0xe320f003 @ Opcode for WFI + +Done: + mov pc, lr + + .type cortexa8_idle_workaround, #object +ENTRY(cortexa8_idle_workaround) + .word cpu_cortexa8_do_idle + .size cortexa8_idle_workaround, . - cortexa8_idle_workaround + diff -urN linux-2.6.26/arch/arm/mach-sa1100/badge4.c linux-2.6.26-lab126/arch/arm/mach-sa1100/badge4.c --- linux-2.6.26/arch/arm/mach-sa1100/badge4.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mach-sa1100/badge4.c 2010-08-10 04:14:16.000000000 -0400 @@ -240,15 +240,22 @@ /* detect on->off and off->on transitions */ if ((!old_5V_bitmap) && (badge4_5V_bitmap)) { /* was off, now on */ - printk(KERN_INFO "%s: enabling 5V supply rail\n", __func__); GPSR = BADGE4_GPIO_PCMEN5V; } else if ((old_5V_bitmap) && (!badge4_5V_bitmap)) { /* was on, now off */ - printk(KERN_INFO "%s: disabling 5V supply rail\n", __func__); GPCR = BADGE4_GPIO_PCMEN5V; } local_irq_restore(flags); + + /* detect on->off and off->on transitions */ + if ((!old_5V_bitmap) && (badge4_5V_bitmap)) { + /* was off, now on */ + printk(KERN_INFO "%s: enabling 5V supply rail\n", __FUNCTION__); + } else if ((old_5V_bitmap) && (!badge4_5V_bitmap)) { + /* was on, now off */ + printk(KERN_INFO "%s: disabling 5V supply rail\n", __FUNCTION__); + } } EXPORT_SYMBOL(badge4_set_5V); diff -urN linux-2.6.26/arch/arm/mach-shark/leds.c linux-2.6.26-lab126/arch/arm/mach-shark/leds.c --- linux-2.6.26/arch/arm/mach-shark/leds.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mach-shark/leds.c 2010-08-10 04:14:05.000000000 -0400 @@ -32,7 +32,7 @@ static short hw_led_state; static short saved_state; -static DEFINE_SPINLOCK(leds_lock); +static DEFINE_RAW_SPINLOCK(leds_lock); short sequoia_read(int addr) { outw(addr,0x24); diff -urN linux-2.6.26/arch/arm/mm/Kconfig linux-2.6.26-lab126/arch/arm/mm/Kconfig --- linux-2.6.26/arch/arm/mm/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mm/Kconfig 2010-08-10 04:14:15.000000000 -0400 @@ -180,7 +180,7 @@ # ARM926T config CPU_ARM926T bool "Support ARM926T processor" - depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI + depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MXC default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI select CPU_32v5 select CPU_ABRT_EV5TJ @@ -387,7 +387,7 @@ # ARMv6 config CPU_V6 bool "Support ARM V6 processor" - depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 + depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || ARCH_MXC default y if ARCH_MX3 default y if ARCH_MSM7X00A select CPU_32v6 @@ -415,7 +415,7 @@ # ARMv7 config CPU_V7 bool "Support ARM V7 processor" - depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB + depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_MXC select CPU_32v6K select CPU_32v7 select CPU_ABRT_EV7 diff -urN linux-2.6.26/arch/arm/mm/abort-ev6.S linux-2.6.26-lab126/arch/arm/mm/abort-ev6.S --- linux-2.6.26/arch/arm/mm/abort-ev6.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mm/abort-ev6.S 2010-08-10 04:14:15.000000000 -0400 @@ -23,6 +23,7 @@ #ifdef CONFIG_CPU_32v6K clrex #else + sub r1, sp, #4 strex r0, r1, [sp] @ Clear the exclusive monitor #endif mrc p15, 0, r1, c5, c0, 0 @ get FSR @@ -31,7 +32,7 @@ * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR. * The test below covers all the write situations, including Java bytecodes */ - bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR + bic r1, r1, #1 << 11 @ clear bits 11 of FSR tst r3, #PSR_J_BIT @ Java? movne pc, lr do_thumb_abort @@ -40,5 +41,3 @@ tst r3, #1 << 20 @ L = 0 -> write orreq r1, r1, #1 << 11 @ yes. mov pc, lr - - diff -urN linux-2.6.26/arch/arm/mm/cache-l2x0.c linux-2.6.26-lab126/arch/arm/mm/cache-l2x0.c --- linux-2.6.26/arch/arm/mm/cache-l2x0.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mm/cache-l2x0.c 2010-08-10 04:14:15.000000000 -0400 @@ -18,27 +18,33 @@ */ #include #include +#include #include #include #include #define CACHE_LINE_SIZE 32 +#ifdef CONFIG_OPROFILE_ARM11_EVTMON +#include +#define L2_ENABLE_BIT 0x1 +#define L2_EVTBUS_BIT 0x100000 +#define L2_CTL_REG (l2x0_base + L2X0_CTRL) +#define L2_AUX_REG (l2x0_base + L2X0_AUX_CTRL) +#endif static void __iomem *l2x0_base; -static DEFINE_SPINLOCK(l2x0_lock); +static unsigned long l2x0_aux; +static DEFINE_RAW_SPINLOCK(l2x0_lock); +bool l2x0_disabled; static inline void sync_writel(unsigned long val, unsigned long reg, unsigned long complete_mask) { - unsigned long flags; - - spin_lock_irqsave(&l2x0_lock, flags); writel(val, l2x0_base + reg); /* wait for the operation to complete */ while (readl(l2x0_base + reg) & complete_mask) ; - spin_unlock_irqrestore(&l2x0_lock, flags); } static inline void cache_sync(void) @@ -48,15 +54,27 @@ static inline void l2x0_inv_all(void) { + unsigned long flags; + /* invalidate all ways */ + spin_lock_irqsave(&l2x0_lock, flags); sync_writel(0xff, L2X0_INV_WAY, 0xff); cache_sync(); + spin_unlock_irqrestore(&l2x0_lock, flags); +} + +static void l2x0_flush_all(void) +{ + /* clean and invalidate all ways */ + sync_writel(0xff, L2X0_CLEAN_INV_WAY, 0xff); + cache_sync(); } static void l2x0_inv_range(unsigned long start, unsigned long end) { - unsigned long addr; + unsigned long flags; + spin_lock_irqsave(&l2x0_lock, flags); if (start & (CACHE_LINE_SIZE - 1)) { start &= ~(CACHE_LINE_SIZE - 1); sync_writel(start, L2X0_CLEAN_INV_LINE_PA, 1); @@ -68,53 +86,169 @@ sync_writel(end, L2X0_CLEAN_INV_LINE_PA, 1); } - for (addr = start; addr < end; addr += CACHE_LINE_SIZE) - sync_writel(addr, L2X0_INV_LINE_PA, 1); + while (start < end) { + unsigned long blk_end = start + min(end - start, 4096UL); + + while (start < blk_end) { + sync_writel(start, L2X0_INV_LINE_PA, 1); + start += CACHE_LINE_SIZE; + } + + if (blk_end < end) { + spin_unlock_irqrestore(&l2x0_lock, flags); + spin_lock_irqsave(&l2x0_lock, flags); + } + } + cache_sync(); + spin_unlock_irqrestore(&l2x0_lock, flags); } static void l2x0_clean_range(unsigned long start, unsigned long end) { - unsigned long addr; + unsigned long flags; + spin_lock_irqsave(&l2x0_lock, flags); start &= ~(CACHE_LINE_SIZE - 1); - for (addr = start; addr < end; addr += CACHE_LINE_SIZE) - sync_writel(addr, L2X0_CLEAN_LINE_PA, 1); + while (start < end) { + unsigned long blk_end = start + min(end - start, 4096UL); + + while (start < blk_end) { + sync_writel(start, L2X0_CLEAN_LINE_PA, 1); + start += CACHE_LINE_SIZE; + } + + if (blk_end < end) { + spin_unlock_irqrestore(&l2x0_lock, flags); + spin_lock_irqsave(&l2x0_lock, flags); + } + } cache_sync(); + spin_unlock_irqrestore(&l2x0_lock, flags); } static void l2x0_flush_range(unsigned long start, unsigned long end) { - unsigned long addr; + unsigned long flags; + spin_lock_irqsave(&l2x0_lock, flags); start &= ~(CACHE_LINE_SIZE - 1); - for (addr = start; addr < end; addr += CACHE_LINE_SIZE) - sync_writel(addr, L2X0_CLEAN_INV_LINE_PA, 1); + while (start < end) { + unsigned long blk_end = start + min(end - start, 4096UL); + + while (start < blk_end) { + sync_writel(start, L2X0_CLEAN_INV_LINE_PA, 1); + start += CACHE_LINE_SIZE; + } + + if (blk_end < end) { + spin_unlock_irqrestore(&l2x0_lock, flags); + spin_lock_irqsave(&l2x0_lock, flags); + } + } cache_sync(); + spin_unlock_irqrestore(&l2x0_lock, flags); } -void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) +#ifdef CONFIG_OPROFILE_ARM11_EVTMON +/*! + * Enable the EVTBUS to monitor L2 cache events + */ +void l2x0_evtbus_enable(void) { - __u32 aux; + unsigned int flags; - l2x0_base = base; + local_irq_save(flags); + /* If L2 cache is enabled then disable L2 cache, enable L2 evtbus, + re-enable L2 cache */ + if ((readl(L2_CTL_REG) & L2_ENABLE_BIT) != 0) { + writel(0, L2_CTL_REG); + writel((readl(L2_AUX_REG)| L2_EVTBUS_BIT), L2_AUX_REG); + writel(L2_ENABLE_BIT, L2_CTL_REG); + } else { + writel((readl(L2_AUX_REG)| L2_EVTBUS_BIT), L2_AUX_REG); + } + local_irq_restore(flags); +} - /* disable L2X0 */ - writel(0, l2x0_base + L2X0_CTRL); +/*! + * Disable the EVTBUS + */ +void l2x0_evtbus_disable(void) +{ + unsigned int flags; - aux = readl(l2x0_base + L2X0_AUX_CTRL); - aux &= aux_mask; - aux |= aux_val; - writel(aux, l2x0_base + L2X0_AUX_CTRL); + local_irq_save(flags); + /* If L2 cache is enabled then disable L2 cache, disable L2 evtbus, + re-enable L2 cache */ + if ((readl(L2_CTL_REG) & L2_ENABLE_BIT) != 0) { + writel(0, L2_CTL_REG); + writel((readl(L2_AUX_REG)& ~L2_EVTBUS_BIT), L2_AUX_REG); + writel(L2_ENABLE_BIT, L2_CTL_REG); + } else { + writel((readl(L2_AUX_REG)& ~L2_EVTBUS_BIT), L2_AUX_REG); + } + local_irq_restore(flags); +} +EXPORT_SYMBOL(l2x0_evtbus_enable); +EXPORT_SYMBOL(l2x0_evtbus_disable); +#endif +void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) +{ + __u32 aux; - l2x0_inv_all(); + if (l2x0_disabled) { + printk(KERN_INFO "L2X0 cache controller disabled\n"); + return; + } + + l2x0_base = base; - /* enable L2X0 */ - writel(1, l2x0_base + L2X0_CTRL); + if (!(readl(l2x0_base + L2X0_CTRL) & 1)) { + /* l2x0 controller is disabled */ + aux = readl(l2x0_base + L2X0_AUX_CTRL); + aux &= aux_mask; + aux |= aux_val; + writel(aux, l2x0_base + L2X0_AUX_CTRL); + + l2x0_inv_all(); + + /* enable L2X0 */ + writel(1, l2x0_base + L2X0_CTRL); + } outer_cache.inv_range = l2x0_inv_range; outer_cache.clean_range = l2x0_clean_range; outer_cache.flush_range = l2x0_flush_range; + outer_cache.flush_all = l2x0_flush_all; printk(KERN_INFO "L2X0 cache controller enabled\n"); } +EXPORT_SYMBOL(outer_cache); + +void l2x0_disable(void) +{ + if (readl(l2x0_base + L2X0_CTRL) + && !(readl(l2x0_base + L2X0_DEBUG_CTRL) & 0x2)) { + l2x0_flush_all(); + writel(0, l2x0_base + L2X0_CTRL); + l2x0_flush_all(); + } +} + +void l2x0_enable(void) +{ + if (!readl(l2x0_base + L2X0_CTRL)) { + writel(l2x0_aux, l2x0_base + L2X0_AUX_CTRL); + l2x0_inv_all(); + /* enable L2X0 */ + writel(1, l2x0_base + L2X0_CTRL); + } +} + +static int __init l2x0_disable_cmdline(char *unused) +{ + l2x0_disabled = 1; + return 0; +} +early_param("nol2x0", l2x0_disable_cmdline); diff -urN linux-2.6.26/arch/arm/mm/cache-v6.S linux-2.6.26-lab126/arch/arm/mm/cache-v6.S --- linux-2.6.26/arch/arm/mm/cache-v6.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mm/cache-v6.S 2010-08-10 04:14:15.000000000 -0400 @@ -20,6 +20,39 @@ #define D_CACHE_LINE_SIZE 32 #define BTB_FLUSH_SIZE 8 +#ifndef CONFIG_SMP +/* + * Invalidate the entire I cache (this code is a workaround for the ARM1136 + * Errata 411920 - Invalidate Instruction Cache operation can fail. This + * Errata is present in 1136, 1156 and 1176. It does not affect the MPCore + * + * Registers: + * r0 - set to 0 + * r1 - corrupted + */ +ENTRY(v6_icache_inval_all) + mov r0, #0 + mrs r1, cpsr + cpsid ifa @ disable interrupts + mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache + mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache + mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache + mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache + msr cpsr_cx, r1 @ restore interrupts + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + mov pc, lr +#endif + /* * v6_flush_cache_all() * @@ -31,8 +64,12 @@ mov r0, #0 #ifdef HARVARD_CACHE mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate +#ifdef CONFIG_SMP mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate #else + b v6_icache_inval_all +#endif +#else mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate #endif mov pc, lr @@ -95,21 +132,39 @@ #ifdef HARVARD_CACHE bic r0, r0, #CACHE_LINE_SIZE - 1 -1: mcr p15, 0, r0, c7, c10, 1 @ clean D line +1: +USER( mcr p15, 0, r0, c7, c10, 1) @ clean D line add r0, r0, #CACHE_LINE_SIZE +2: cmp r0, r1 blo 1b #endif mov r0, #0 #ifdef HARVARD_CACHE mcr p15, 0, r0, c7, c10, 4 @ drain write buffer +#ifdef CONFIG_SMP mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate #else + b v6_icache_inval_all +#endif +#else mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB #endif mov pc, lr /* + * For unmapped addresses, go to the next page. If the virtual + * address is not mapped, pick the next page + */ +9001: + mov r0, r0, lsr #12 + mov r0, r0, lsl #12 + add r0, r0, #4096 + b 2b +ENDPROC(v6_coherent_user_range) +ENDPROC(v6_coherent_kern_range) + +/* * v6_flush_kern_dcache_page(kaddr) * * Ensure that the data held in the page kaddr is written back diff -urN linux-2.6.26/arch/arm/mm/consistent.c linux-2.6.26-lab126/arch/arm/mm/consistent.c --- linux-2.6.26/arch/arm/mm/consistent.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mm/consistent.c 2010-08-10 04:14:15.000000000 -0400 @@ -40,7 +40,7 @@ * These are the page tables (2MB each) covering uncached, DMA consistent allocations */ static pte_t *consistent_pte[NUM_CONSISTENT_PTES]; -static DEFINE_SPINLOCK(consistent_lock); +static DEFINE_RAW_SPINLOCK(consistent_lock); /* * VM region handling support. diff -urN linux-2.6.26/arch/arm/mm/context.c linux-2.6.26-lab126/arch/arm/mm/context.c --- linux-2.6.26/arch/arm/mm/context.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mm/context.c 2010-08-10 04:14:15.000000000 -0400 @@ -14,7 +14,7 @@ #include #include -static DEFINE_SPINLOCK(cpu_asid_lock); +static DEFINE_RAW_SPINLOCK(cpu_asid_lock); unsigned int cpu_last_asid = ASID_FIRST_VERSION; /* diff -urN linux-2.6.26/arch/arm/mm/copypage-v4mc.c linux-2.6.26-lab126/arch/arm/mm/copypage-v4mc.c --- linux-2.6.26/arch/arm/mm/copypage-v4mc.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mm/copypage-v4mc.c 2010-08-10 04:14:15.000000000 -0400 @@ -30,7 +30,7 @@ #define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \ L_PTE_CACHEABLE) -static DEFINE_SPINLOCK(minicache_lock); +static DEFINE_RAW_SPINLOCK(minicache_lock); /* * ARMv4 mini-dcache optimised copy_user_page @@ -44,7 +44,7 @@ * instruction. If your processor does not supply this, you have to write your * own copy_user_page that does the right thing. */ -static void __attribute__((naked)) +static void notrace __attribute__((naked)) mc_copy_user_page(void *from, void *to) { asm volatile( @@ -88,7 +88,7 @@ /* * ARMv4 optimised clear_user_page */ -void __attribute__((naked)) +void notrace __attribute__((naked)) v4_mc_clear_user_page(void *kaddr, unsigned long vaddr) { asm volatile( diff -urN linux-2.6.26/arch/arm/mm/copypage-v6.c linux-2.6.26-lab126/arch/arm/mm/copypage-v6.c --- linux-2.6.26/arch/arm/mm/copypage-v6.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mm/copypage-v6.c 2010-08-10 04:14:15.000000000 -0400 @@ -26,7 +26,7 @@ #define from_address (0xffff8000) #define to_address (0xffffc000) -static DEFINE_SPINLOCK(v6_lock); +static DEFINE_RAW_SPINLOCK(v6_lock); /* * Copy the user page. No aliasing to deal with so we can just diff -urN linux-2.6.26/arch/arm/mm/copypage-xscale.c linux-2.6.26-lab126/arch/arm/mm/copypage-xscale.c --- linux-2.6.26/arch/arm/mm/copypage-xscale.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mm/copypage-xscale.c 2010-08-10 04:14:15.000000000 -0400 @@ -32,7 +32,7 @@ #define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \ L_PTE_CACHEABLE) -static DEFINE_SPINLOCK(minicache_lock); +static DEFINE_RAW_SPINLOCK(minicache_lock); /* * XScale mini-dcache optimised copy_user_page @@ -42,7 +42,7 @@ * Dcache aliasing issue. The writes will be forwarded to the write buffer, * and merged as appropriate. */ -static void __attribute__((naked)) +static void notrace __attribute__((naked)) mc_copy_user_page(void *from, void *to) { /* @@ -110,7 +110,7 @@ /* * XScale optimised clear_user_page */ -void __attribute__((naked)) +void notrace __attribute__((naked)) xscale_mc_clear_user_page(void *kaddr, unsigned long vaddr) { asm volatile( diff -urN linux-2.6.26/arch/arm/mm/fault.c linux-2.6.26-lab126/arch/arm/mm/fault.c --- linux-2.6.26/arch/arm/mm/fault.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mm/fault.c 2010-08-10 04:14:15.000000000 -0400 @@ -21,6 +21,8 @@ #include "fault.h" +/* Fault status register encodings */ +#define FSR_WRITE (1 << 11) #ifdef CONFIG_KPROBES static inline int notify_page_fault(struct pt_regs *regs, unsigned int fsr) @@ -172,18 +174,33 @@ #define VM_FAULT_BADMAP 0x010000 #define VM_FAULT_BADACCESS 0x020000 +/* + * Check that the permissions on the VMA allow for the fault which occurred. + * If we encountered a write fault, we must have write permission, otherwise + * we allow any permission. + */ +static inline bool access_error(unsigned int fsr, struct vm_area_struct *vma) +{ + unsigned int mask = VM_READ | VM_WRITE | VM_EXEC; + + if (fsr & FSR_WRITE) + mask = VM_WRITE; + + return vma->vm_flags & mask ? false : true; +} + static int __do_page_fault(struct mm_struct *mm, unsigned long addr, unsigned int fsr, struct task_struct *tsk) { struct vm_area_struct *vma; - int fault, mask; + int fault; vma = find_vma(mm, addr); fault = VM_FAULT_BADMAP; - if (!vma) + if (unlikely(!vma)) goto out; - if (vma->vm_start > addr) + if (unlikely(vma->vm_start > addr)) goto check_stack; /* @@ -191,14 +208,10 @@ * memory access, so we can handle it. */ good_area: - if (fsr & (1 << 11)) /* write? */ - mask = VM_WRITE; - else - mask = VM_READ|VM_EXEC|VM_WRITE; - - fault = VM_FAULT_BADACCESS; - if (!(vma->vm_flags & mask)) + if (access_error(fsr, vma)) { + fault = VM_FAULT_BADACCESS; goto out; + } /* * If for any reason at all we couldn't handle @@ -239,7 +252,7 @@ return fault; } -static int __kprobes +static int notrace __kprobes do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) { struct task_struct *tsk; @@ -256,7 +269,7 @@ * If we're in an interrupt or have no user * context, we must not take the fault.. */ - if (in_atomic() || !mm) + if (in_atomic() || !mm || current->pagefault_disabled) goto no_context; /* @@ -338,7 +351,7 @@ * interrupt or a critical region, and should only copy the information * from the master page table, nothing more. */ -static int __kprobes +static int notrace __kprobes do_translation_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) { @@ -381,7 +394,7 @@ * Some section permission faults need to be handled gracefully. * They can happen due to a __{get,put}_user during an oops. */ -static int +static notrace int do_sect_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) { do_bad_area(addr, fsr, regs); @@ -391,7 +404,7 @@ /* * This abort handler always returns "fault". */ -static int +static notrace int do_bad(unsigned long addr, unsigned int fsr, struct pt_regs *regs) { return 1; @@ -446,7 +459,7 @@ { do_bad, SIGBUS, 0, "unknown 31" } }; -void __init +void __init notrace hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *), int sig, const char *name) { @@ -460,7 +473,7 @@ /* * Dispatch a data abort to the relevant handler. */ -asmlinkage void __exception +asmlinkage void __exception notrace do_DataAbort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) { const struct fsr_info *inf = fsr_info + (fsr & 15) + ((fsr & (1 << 10)) >> 6); @@ -479,7 +492,7 @@ arm_notify_die("", regs, &info, fsr, 0); } -asmlinkage void __exception +asmlinkage void __exception notrace do_PrefetchAbort(unsigned long addr, struct pt_regs *regs) { do_translation_fault(addr, 0, regs); diff -urN linux-2.6.26/arch/arm/mm/flush.c linux-2.6.26-lab126/arch/arm/mm/flush.c --- linux-2.6.26/arch/arm/mm/flush.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mm/flush.c 2010-08-10 04:14:15.000000000 -0400 @@ -31,10 +31,14 @@ asm( "mcrr p15, 0, %1, %0, c14\n" " mcr p15, 0, %2, c7, c10, 4\n" +#if __LINUX_ARM_ARCH__ != 6 || defined(CONFIG_SMP) " mcr p15, 0, %2, c7, c5, 0\n" +#else + " bl v6_icache_inval_all\n" +#endif : : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero) - : "cc"); + : "r0", "r1", "lr"); } void flush_cache_mm(struct mm_struct *mm) @@ -47,11 +51,15 @@ if (cache_is_vipt_aliasing()) { asm( "mcr p15, 0, %0, c7, c14, 0\n" + " mcr p15, 0, %0, c7, c10, 4\n" +#if __LINUX_ARM_ARCH__ != 6 || defined(CONFIG_SMP) " mcr p15, 0, %0, c7, c5, 0\n" - " mcr p15, 0, %0, c7, c10, 4" +#else + " bl v6_icache_inval_all\n" +#endif : : "r" (0) - : "cc"); + : "r0", "r1", "lr", "cc"); } } @@ -66,11 +74,15 @@ if (cache_is_vipt_aliasing()) { asm( "mcr p15, 0, %0, c7, c14, 0\n" + " mcr p15, 0, %0, c7, c10, 4\n" +#if __LINUX_ARM_ARCH__ != 6 || defined(CONFIG_SMP) " mcr p15, 0, %0, c7, c5, 0\n" - " mcr p15, 0, %0, c7, c10, 4" +#else + " bl v6_icache_inval_all\n" +#endif : : "r" (0) - : "cc"); + : "r0", "r1", "lr", "cc"); } } @@ -119,12 +131,17 @@ void __flush_dcache_page(struct address_space *mapping, struct page *page) { + void *addr = page_address(page); + /* * Writeback any data associated with the kernel mapping of this * page. This ensures that data in the physical page is mutually * coherent with the kernels mapping. */ - __cpuc_flush_dcache_page(page_address(page)); +#ifdef CONFIG_HIGHMEM + if (addr) +#endif + __cpuc_flush_dcache_page(addr); /* * If this is a page cache page, and we have an aliasing VIPT cache, diff -urN linux-2.6.26/arch/arm/mm/mmu.c linux-2.6.26-lab126/arch/arm/mm/mmu.c --- linux-2.6.26/arch/arm/mm/mmu.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mm/mmu.c 2010-08-10 04:14:15.000000000 -0400 @@ -25,7 +25,7 @@ #include "mm.h" -DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); +DEFINE_PER_CPU_LOCKED(struct mmu_gather, mmu_gathers); extern void _stext, _etext, __data_start, _end; extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; @@ -797,4 +797,5 @@ pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1))); flush_pmd_entry(pmd); } + local_flush_tlb_all(); } diff -urN linux-2.6.26/arch/arm/mm/proc-v6.S linux-2.6.26-lab126/arch/arm/mm/proc-v6.S --- linux-2.6.26/arch/arm/mm/proc-v6.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mm/proc-v6.S 2010-08-10 04:14:15.000000000 -0400 @@ -10,6 +10,7 @@ * * This is the "shell" of the ARMv6 processor support. */ +#include #include #include #include @@ -71,8 +72,21 @@ * IRQs are already disabled. */ ENTRY(cpu_v6_do_idle) - mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt - mov pc, lr + mrc p15, 0, r0, c1, c0, 0 @Read system control reg + bic r0, r0, #0x00001000 @Disable I-cache + bic r0, r0, #0x00000004 @Disable D-cache + mcr p15, 0, r0, c1, c0, 0 @Update system control reg + mov r0, #0 @Invalidate entire I-cache (also + mcr p15, 0, r0, c7, c5, 0 @flushes branch target cache) + mov r0, #0 @Clean and invalidate entire + mcr p15, 0, r0, c7, c14, 0 @D-cache + mov r0, #0 + mcr p15, 0, r0, c7, c0, 4 @Enter WFI + mrc p15, 0, r0, c1, c0, 0 @Read system control reg + orr r0, r0, #0x00001000 @Enable I-cache + orr r0, r0, #0x00000004 @Enable D-cache + mcr p15, 0, r0, c1, c0, 0 @Update system control reg + mov pc, lr ENTRY(cpu_v6_dcache_clean_area) #ifndef TLB_CAN_READ_FROM_L1_CACHE @@ -124,6 +138,14 @@ * 110x 0 1 0 r/w r/o * 11x0 0 1 0 r/w r/o * 1111 0 1 1 r/w r/w + * + * Extended PTE mapping encoding (L_PTE_EXTENDED=1): + * ECB + * 0xx - standard C and B encoding + * 101 - inner WB, outer WB, write-allocate + * 110 - inner WB, outer WT + * 100 - inner WB, outer non-cacheable, non-bufferable + * 111 - non-shared device (accesses go thru peripheral bus) */ ENTRY(cpu_v6_set_pte_ext) #ifdef CONFIG_MMU @@ -134,6 +156,24 @@ orr r3, r3, r2 orr r3, r3, #PTE_EXT_AP0 | 2 + tst r1, #L_PTE_EXTENDED + beq 1f + /* If CB = 11, set PTE to non-shared device */ + tst r1, #L_PTE_CACHEABLE + tstne r1, #L_PTE_BUFFERABLE + orrne r3, r3, #PTE_EXT_TEX(2) + bicne r3, r3, #L_PTE_CACHEABLE | L_PTE_BUFFERABLE + bne 1f + + /* Set outer cache according to C and B bits */ + orr r3, r3, #PTE_EXT_TEX(4) + tst r1, #L_PTE_CACHEABLE + orrne r3, r3, #PTE_EXT_TEX(2) + tst r1, #L_PTE_BUFFERABLE + orrne r3, r3, #PTE_EXT_TEX(1) + /* Set inner cache to writeback */ + orr r3, r3, #PTE_BUFFERABLE | PTE_CACHEABLE +1: tst r1, #L_PTE_WRITE tstne r1, #L_PTE_DIRTY orreq r3, r3, #PTE_EXT_APX @@ -164,8 +204,7 @@ .asciz "ARMv6-compatible processor" .align - .section ".text.init", #alloc, #execinstr - + __INIT /* * __v6_setup * @@ -204,6 +243,22 @@ mrc p15, 0, r0, c1, c0, 0 @ read control register bic r0, r0, r5 @ clear bits them orr r0, r0, r6 @ set them + + /* Workaround for the 364296 ARM1136 r0pX errata (possible cache data + * corruption with hit-under-miss enabled). The conditional code below + * (setting the undocumented bit 31 in the auxiliary control register + * and the FI bit in the control register) disables hit-under-miss + * without putting the processor into full low interrupt latency mode. + */ + ldr r6, =0x4107b360 @ id for ARM1136 r0pX + mrc p15, 0, r5, c0, c0, 0 @ get processor id + bic r5, r5, #0xf @ mask out part bits [3:0] + teq r5, r6 @ check for the faulty core + mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg + orreq r5, r5, #(1 << 31) @ set the undocumented bit 31 + mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg + orreq r0, r0, #(1 << 21) @ low interrupt latency configuration + mov pc, lr @ return to head.S:__ret /* diff -urN linux-2.6.26/arch/arm/mm/tlb-v6.S linux-2.6.26-lab126/arch/arm/mm/tlb-v6.S --- linux-2.6.26/arch/arm/mm/tlb-v6.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/mm/tlb-v6.S 2010-08-10 04:14:15.000000000 -0400 @@ -10,6 +10,7 @@ * ARM architecture version 6 TLB handling functions. * These assume a split I/D TLB. */ +#include #include #include #include @@ -87,7 +88,7 @@ mcr p15, 0, r2, c7, c5, 4 @ prefetch flush mov pc, lr - .section ".text.init", #alloc, #execinstr + __INIT .type v6wbi_tlb_fns, #object ENTRY(v6wbi_tlb_fns) diff -urN linux-2.6.26/arch/arm/oprofile/Makefile linux-2.6.26-lab126/arch/arm/oprofile/Makefile --- linux-2.6.26/arch/arm/oprofile/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/oprofile/Makefile 2010-08-10 04:14:05.000000000 -0400 @@ -9,5 +9,6 @@ oprofile-y := $(DRIVER_OBJS) common.o backtrace.o oprofile-$(CONFIG_CPU_XSCALE) += op_model_xscale.o oprofile-$(CONFIG_OPROFILE_ARM11_CORE) += op_model_arm11_core.o +oprofile-$(CONFIG_OPROFILE_ARM11_EVTMON) += op_model_arm11_evtmon.o oprofile-$(CONFIG_OPROFILE_ARMV6) += op_model_v6.o oprofile-$(CONFIG_OPROFILE_MPCORE) += op_model_mpcore.o diff -urN linux-2.6.26/arch/arm/oprofile/common.c linux-2.6.26-lab126/arch/arm/oprofile/common.c --- linux-2.6.26/arch/arm/oprofile/common.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/oprofile/common.c 2010-08-10 04:14:05.000000000 -0400 @@ -11,7 +11,8 @@ #include #include #include -#include +#include +#include #include #include "op_counter.h" @@ -77,7 +78,7 @@ } #ifdef CONFIG_PM -static int op_arm_suspend(struct sys_device *dev, pm_message_t state) +static int op_arm_suspend(struct platform_device *dev, pm_message_t state) { mutex_lock(&op_arm_mutex); if (op_arm_enabled) @@ -86,7 +87,7 @@ return 0; } -static int op_arm_resume(struct sys_device *dev) +static int op_arm_resume(struct platform_device *dev) { mutex_lock(&op_arm_mutex); if (op_arm_enabled && op_arm_model->start()) @@ -95,34 +96,40 @@ return 0; } -static struct sysdev_class oprofile_sysclass = { - .name = "oprofile", +static struct platform_driver oprofile_driver = { + .driver = { + .name = "arm-oprofile", + }, .resume = op_arm_resume, .suspend = op_arm_suspend, }; -static struct sys_device device_oprofile = { - .id = 0, - .cls = &oprofile_sysclass, -}; +static struct platform_device *oprofile_pdev; static int __init init_driverfs(void) { int ret; - if (!(ret = sysdev_class_register(&oprofile_sysclass))) - ret = sysdev_register(&device_oprofile); - + ret = platform_driver_register(&oprofile_driver); + if (ret) + return ret; + + oprofile_pdev = + platform_device_register_simple("arm-oprofile", 0, NULL, 0); + if (IS_ERR(oprofile_pdev)) { + ret = PTR_ERR(oprofile_pdev); + platform_driver_unregister(&oprofile_driver); + } return ret; } static void exit_driverfs(void) { - sysdev_unregister(&device_oprofile); - sysdev_class_unregister(&oprofile_sysclass); + platform_device_unregister(oprofile_pdev); + platform_driver_unregister(&oprofile_driver); } #else -#define init_driverfs() do { } while (0) +static int __init init_driverfs(void) { return 0; } #define exit_driverfs() do { } while (0) #endif /* CONFIG_PM */ @@ -155,8 +162,12 @@ if (!counter_config) return -ENOMEM; + ret = init_driverfs(); + if (ret) { + kfree(counter_config); + return ret; + } op_arm_model = spec; - init_driverfs(); ops->create_files = op_arm_create_files; ops->setup = op_arm_setup; ops->shutdown = op_arm_stop; @@ -174,6 +185,6 @@ if (op_arm_model) { exit_driverfs(); op_arm_model = NULL; + kfree(counter_config); } - kfree(counter_config); } diff -urN linux-2.6.26/arch/arm/oprofile/evtmon_regs.h linux-2.6.26-lab126/arch/arm/oprofile/evtmon_regs.h --- linux-2.6.26/arch/arm/oprofile/evtmon_regs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/oprofile/evtmon_regs.h 2010-08-10 04:14:05.000000000 -0400 @@ -0,0 +1,84 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * @file evtmon_regs.h + * + * @brief EVTMON Register definitions + * + * @ingroup MXC_Oprofile + */ +#ifndef _EVTMON_REGS_INCLUDED_ +#define _EVTMON_REGS_INCLUDED_ + +#define MXC_CRM_AP_BASE (IO_ADDRESS(CRM_AP_BASE_ADDR)) +#define ECT_CTI_BASE (IO_ADDRESS(ECT_CTIO_BASE_ADDR)) +#define CLKCTR_BASE_ADDR (IO_ADDRESS(CLKCTL_BASE_ADDR)) +#define L2CC_BASE_ADDRESS (IO_ADDRESS(L2CC_BASE_ADDR)) +#define L2EM_BASE_ADDRESS (IO_ADDRESS(EVTMON_BASE_ADDR)) + +/* L2 INT settings */ +#define L2EM_ENABLE_OVERFLOWINT 0x1 +#define L2EM_ENABLE_CNTINCRINT 0x3 +#define L2EM_ENABLE_MASK 0x1 +#define L2EM_INT_EDGE 0x2 +#define L2EM_INT_HIGH 0x4 +#define L2EM_INT_CLK_CYCLES (0x0 << 3) + +/* Reg definitions for EVTMON */ +#define L2EM_CTRL (L2EM_BASE_ADDRESS + 0x0) +#define L2EM_STAT (L2EM_BASE_ADDRESS + 0x4) +#define L2EM_CC(nr) (L2EM_BASE_ADDRESS + 0x8 +(4*nr)) +#define L2EM_CNT(nr) (L2EM_BASE_ADDRESS + 0x20 +(4*nr)) + +/* Reg definitions for CLK_CTL */ +#define CLKCTL_SET_CTRL (CLKCTR_BASE_ADDR + 0x04) + +/* Reg definitions for ECT */ +#define ECT_CTI_CONTROL (ECT_CTI_BASE + 0x0) +#define ECT_CTI_LOCK (ECT_CTI_BASE + 0x8) +#define ECT_CTI_INEN(nr) (ECT_CTI_BASE + 0x20 + (4*nr)) +#define ECT_CTI_OUTEN(nr) (ECT_CTI_BASE + 0xA0 + (4*nr)) +#define ECT_CTI_INTACK (ECT_CTI_BASE + 0x10) +#define ECT_CTI_TRIGOUTSTATUS (ECT_CTI_BASE + 0x134) + +#define ENABLE_L2CACHE 0x1 +#define EVTMON_ENABLE 0x001 /* Enable EVTMON */ +#define EVT_UNUSED 0x100 +#define MAX_PMUCOUNTERS 3 + +#ifdef CONFIG_OPROFILE_ARM11_EVTMON +#define ECT_WORKAROUND +#endif + +#ifdef ECT_WORKAROUND +#define ENABLE_CTI_CLOCK 0x00000020 +#define UNLOCK_ECT_CODE 0x0ACCE550 +#define ECT_CTI_CHAN_2 0x4 +#define ECT_CTI_CHAN_3 0x8 +#define ECT_CTI_TRIGIN_1 1 +#define ECT_CTI_TRIGIN_7 7 +#define ECT_CTI_TRIGOUT_2 2 +#define ECT_CTI_TRIGOUT_6 6 +#define ENABLE_ECT 0x1 +#define ACK_TRIG_OUT_2 0x4 +#define EM_SET_INT L2EM_ENABLE_CNTINCRINT +#define EVENT_OVERFLOW_INT MXC_INT_ECT +#else +#define EVENT_OVERFLOW_INT ARM11_PMU_IRQ +#define EM_SET_INT L2EM_ENABLE_OVERFLOWINT +#endif + +int l2em_configure_counter(int nr, int type); +void write_l2counter(int nr, u32 val); +#endif diff -urN linux-2.6.26/arch/arm/oprofile/op_model_arm11.c linux-2.6.26-lab126/arch/arm/oprofile/op_model_arm11.c --- linux-2.6.26/arch/arm/oprofile/op_model_arm11.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/oprofile/op_model_arm11.c 2010-08-10 04:14:05.000000000 -0400 @@ -0,0 +1,477 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup MXC_Oprofile ARM11 Driver for Oprofile + */ + +/*! + * @file op_model_arm11.c + * + *Based on the op_model_xscale.c driver by author Zwane Mwaikambo + * + * @ingroup MXC_Oprofile + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "op_counter.h" +#include "op_arm_model.h" +#include "evtmon_regs.h" + +/*! + * defines used in ARM11 performance unit + */ +#define PMU_ENABLE 0x001 /* Enable counters */ +#define EVTMON_ENABLE 0x001 /* Enable EVTMON */ +#define PMN_RESET 0x002 /* Reset event counters */ +#define CCNT_RESET 0x004 /* Reset clock counter */ +#define PMU_RESET (CCNT_RESET | PMN_RESET) +#define PMU_CNT64 0x008 /* Make CCNT count every 64th cycle */ + +#define PMU_FLAG_CR0 0x080 +#define PMU_FLAG_CR1 0x100 +#define PMU_FLAG_CC 0x200 + +/*! + * Different types of events that can be counted by the ARM11 PMU + * as used by Oprofile userspace. + */ +#define EVT_ICACHE_MISS 0x00 +#define EVT_STALL_INSTR 0x01 +#define EVT_DATA_STALL 0x02 +#define EVT_ITLB_MISS 0x03 +#define EVT_DTLB_MISS 0x04 +#define EVT_BRANCH 0x05 +#define EVT_BRANCH_MISS 0x06 +#define EVT_INSTRUCTION 0x07 +#define EVT_DCACHE_FULL_STALL_CONTIG 0x09 +#define EVT_DCACHE_ACCESS 0x0A +#define EVT_DCACHE_MISS 0x0B +#define EVT_DCACE_WRITE_BACK 0x0C +#define EVT_PC_CHANGED 0x0D +#define EVT_TLB_MISS 0x0F +#define EVT_BCU_REQUEST 0x10 +#define EVT_BCU_FULL 0x11 +#define EVT_BCU_DRAIN 0x12 +#define EVT_ETMEXTOT0 0x20 +#define EVT_ETMEXTOT1 0x21 +/* EVT_CCNT is not hardware defined */ +#define EVT_CCNT 0xFE +#define EVT_INCREMENT 0xFF +#define EVT_UNUSED 0x100 + +#define ECT_WORKAROUND + +#define COUNTER_MSB 0x80000000 +#define ENABLE_L2CACHE 0x1 +#define ENABLE_EVTBUS 0x100000 +#define PMU_OVERFLOWBIT_MASK 0x700 +#define VAR_NUM 0x0 +#define REV_NUM 0x2 + +#ifdef ECT_WORKAROUND +#define ENABLE_CTI_CLOCK 0x00000020 +#define UNLOCK_ECT_CODE 0x0ACCE550 +#define ECT_CTI_CHAN_2 0x4 +#define ECT_CTI_CHAN_3 0x8 +#define ECT_CTI_TRIGIN_1 1 +#define ECT_CTI_TRIGIN_7 7 +#define ECT_CTI_TRIGOUT_2 2 +#define ECT_CTI_TRIGOUT_6 6 +#define ENABLE_ECT 0x1 +#define ACK_TRIG_OUT_2 0x4 +#define EM_SET_INT L2EM_ENABLE_CNTINCRINT +#define EVENT_OVERFLOW_INT INT_ECT +#else +#define EVENT_OVERFLOW_INT ARM11_PMU_IRQ +#define EM_SET_INT L2EM_ENABLE_OVERFLOWINT +#endif + +struct pmu_counter { + volatile unsigned long ovf; + unsigned long reset_counter; +}; + +static unsigned int r0p2_or_older_core; +enum { CCNT, PMN0, PMN1, MAX_PMUCOUNTERS }; +enum { EMC0 = MAX_PMUCOUNTERS, EMC1, EMC2, EMC3, MAX_L2COUNTERS }; + +static struct pmu_counter results[MAX_L2COUNTERS]; + +struct pmu_type { + int id; + char *name; + int num_counters; + unsigned int int_enable; + unsigned int cnt_ovf[MAX_L2COUNTERS]; + unsigned int int_mask[MAX_L2COUNTERS]; +}; + +static struct pmu_type pmu_parms[] = { + { + .id = 0, + .name = "arm/arm11", + .num_counters = MAX_L2COUNTERS, + .int_mask = {[PMN0] = 0x10,[PMN1] = 0x20, + [CCNT] = 0x40,[EMC0] = 0x800,[EMC1] = 0x400,[EMC2] = + 0x200,[EMC3] = 0x100}, + .cnt_ovf = {[CCNT] = 0x400,[PMN0] = 0x100, + [PMN1] = 0x200,[EMC0] = 0x1,[EMC1] = 0x2,[EMC2] = + 0x4,[EMC3] = 0x8}, + }, +}; + +static struct pmu_type *pmu; + +extern void l2_evtbus_enable(void); +extern void l2_evtbus_disable(void); + +/*! + * function is used to write the EVTMON counter configuration register. + */ +static int l2em_configure_counter(int nr, int type) +{ + /* Configure the counter event source */ + __raw_writel(((type << 2) & 0x7c), L2EM_CC(nr)); + if (type) + __raw_writel((__raw_readl(L2EM_CC(nr)) | EM_SET_INT), + L2EM_CC(nr)); + + return 0; +} + +/*! + * function is used to write the EVTMON counters + */ +static void write_l2counter(int nr, u32 val) +{ + __raw_writel(val, L2EM_CNT(nr)); +} + +/*! + * function is used to write the control register for the ARM11 performance counters + */ +static void write_pmnc(u32 val) +{ + pr_debug("PMC value written is %#08x\n", val); + __asm__ __volatile__("mcr p15, 0, %0, c15, c12, 0"::"r"(val)); +} + +/*! + * function is used to read the control register for the ARM11 performance counters + */ +static u32 read_pmnc(void) +{ + u32 val; + pr_debug("In function %s\n", __FUNCTION__); + __asm__ __volatile__("mrc p15, 0, %0, c15, c12, 0":"=r"(val)); + pr_debug("PMC value read is %#08x\n", val); + return val; +} + +/*! + * function is used to read the ARM11 performance counters + */ +static u32 read_counter(int counter) +{ + u32 val = 0; + pr_debug("In function %s\n", __FUNCTION__); + + switch (counter) { + case CCNT: + __asm__ __volatile__("mrc p15, 0, %0, c15, c12, 1":"=r"(val)); + break; + case PMN0: + __asm__ __volatile__("mrc p15, 0, %0, c15, c12, 2":"=r"(val)); + break; + case PMN1: + __asm__ __volatile__("mrc p15, 0, %0, c15, c12, 3":"=r"(val)); + break; + } + + pr_debug("counter %d value read is %#08x\n", counter, val); + return val; +} + +/*! + * function is used to write to the ARM11 performance counters + */ +static void write_counter(int counter, u32 val) +{ + pr_debug("counter %d value written is %#08x\n", counter, val); + + switch (counter) { + case CCNT: + __asm__ __volatile__("mcr p15, 0, %0, c15, c12, 1": :"r"(val)); + break; + case PMN0: + __asm__ __volatile__("mcr p15, 0, %0, c15, c12, 2": :"r"(val)); + break; + case PMN1: + __asm__ __volatile__("mcr p15, 0, %0, c15, c12, 3": :"r"(val)); + break; + } +} + +/*! + * function is used to check the status of the ARM11 performance counters + */ +static int arm11_setup_ctrs(void) +{ + u32 pmnc = 0; + int i; + + for (i = CCNT; i < MAX_L2COUNTERS; i++) { + if (counter_config[i].enabled) + continue; + counter_config[i].event = EVT_UNUSED; + } + + if (counter_config[PMN0].enabled) + pmnc |= (counter_config[PMN0].event << 20); + + if (counter_config[PMN1].enabled) + pmnc |= (counter_config[PMN1].event << 12); + + pr_debug("arm11_setup_ctrs: pmnc: %#08x\n", pmnc); + write_pmnc(pmnc); + + for (i = CCNT; i < MAX_L2COUNTERS; i++) { + if (counter_config[i].event == EVT_UNUSED) { + counter_config[i].event = 0; + pmu->int_enable &= ~pmu->int_mask[i]; + pr_debug + ("arm11_setup_ctrs: The counter event is %d for counter%d\n", + counter_config[i].event, i); + continue; + } + + results[i].reset_counter = counter_config[i].count; + if (i < MAX_PMUCOUNTERS) + write_counter(i, -(u32) counter_config[i].count); + else { + write_l2counter(i - EMC0, + -(u32) counter_config[i].count); + l2em_configure_counter(i - EMC0, + counter_config[i].event); + } + pmu->int_enable |= pmu->int_mask[i]; + pr_debug + ("arm11_setup_ctrs: The values of int mask and enables are %x, %x\n", + pmu->int_mask[i], pmu->int_enable); + + pr_debug("arm11_setup_ctrs: counter%d %#08x from %#08lx\n", i, + read_counter(i), counter_config[i].count); + } + + return 0; +} + +/*! + * function is the interrupt service handler for the ARM11 performance counters + */ +static irqreturn_t arm11_pmu_interrupt(int irq, void *arg, struct pt_regs *regs) +{ + int i; + u32 pmnc, emcs; + + /* Disable L2_EVTMON */ + emcs = __raw_readl(L2EM_STAT); + __raw_writel((__raw_readl(L2EM_CTRL) & ~EVTMON_ENABLE), L2EM_CTRL); + + /* Disable ARM11 PMU while retaining interrupts and overflow bits */ + pmnc = read_pmnc(); + pmnc &= ~(PMU_ENABLE | PMU_OVERFLOWBIT_MASK); + write_pmnc(pmnc); + + /* Read the overflow flag bits */ + pmnc = read_pmnc(); + +#ifdef ECT_WORKAROUND + for (i = CCNT; i < MAX_PMUCOUNTERS; i++) { +#else + for (i = CCNT; i < MAX_L2COUNTERS; i++) { +#endif + /* Process the counters only if respective overflow interrupt is enabled */ + if (!(pmu->int_mask[i] & pmu->int_enable)) { + continue; + } + + /* As per ARM11 errata ARM11 cores with revision less than or equal to R0P2 + * have known bug i.e., missing overflow interrupt for two events(event + * no 0x7 and 0x22) due to double increament for cycle. In this case we will + * discard the sample as the pc value belongs to different interrupt. + */ + if (r0p2_or_older_core && !(pmnc & pmu->cnt_ovf[i]) + && !(read_counter(i) & COUNTER_MSB)) { + write_counter(i, -(u32) (results[i].reset_counter)); + } + + /* Check for the overflowed counter by checking set overflow flag bits */ + if (!(pmnc & pmu->cnt_ovf[i]) && !(emcs & pmu->cnt_ovf[i])) { + continue; + } + + /* Reload the overflowed counter with preset value and + * add the sample for respective event. + */ + pr_debug("arm11_pmu_interrupt: writing to file\n"); + if (i < MAX_PMUCOUNTERS) + write_counter(i, -(u32) results[i].reset_counter); + else + write_l2counter(i - EMC0, + -(u32) counter_config[i].count); + + oprofile_add_sample(regs, i); + } + + /* Clear overflow flags */ + write_pmnc(pmnc); + +#ifdef ECT_WORKAROUND + /* + * If ECTTRIGOUT signal is interrupt it should be acknowledged + * until trigger is off. + */ + while (__raw_readl(ECT_CTI_TRIGOUTSTATUS) & ECT_CTI_CHAN_2) + __raw_writel(ACK_TRIG_OUT_2, ECT_CTI_INTACK); +#endif + + /* Re-enable ARM11 PMU */ + pmnc |= PMU_ENABLE; + write_pmnc(pmnc); + + /* Re-enable L2_EVTMON */ + __raw_writel((__raw_readl(L2EM_CTRL) | L2EM_ENABLE_MASK), L2EM_CTRL); + + return IRQ_HANDLED; +} + +/*! + * function used to start the ARM11 performance counters + */ +static void arm11_pmu_stop(void) +{ + u32 pmnc = read_pmnc(); + + pmnc &= ~PMU_ENABLE; + write_pmnc(pmnc); + /* Disable the EVTMON */ + __raw_writel((__raw_readl(L2EM_CTRL) & ~EVTMON_ENABLE), L2EM_CTRL); + + /* Disable the EVTBUS */ + l2_evtbus_disable(); + + free_irq(EVENT_OVERFLOW_INT, results); +} + +/*! + * function used to start the ARM11 performance counters + */ +static int arm11_pmu_start(void) +{ + int ret; + u32 pmnc = read_pmnc(); + + ret = request_irq(EVENT_OVERFLOW_INT, arm11_pmu_interrupt, SA_INTERRUPT, + "ARM11 PMU", (void *)results); + pr_debug("requested IRQ\n"); + + if (ret < 0) { + printk(KERN_ERR + "oprofile: unable to request IRQ%d for ARM11 PMU\n", + ARM11_PMU_IRQ); + return ret; + } + + /* Enable the EVTBUS */ + l2_evtbus_enable(); + +#ifdef ECT_WORKAROUND + __raw_writel(ENABLE_CTI_CLOCK, CLKCTL_SET_CTRL); + /* Unlock the AHB Interface */ + __raw_writel(UNLOCK_ECT_CODE, ECT_CTI_LOCK); + /* Trigger to Channel Mapping */ + __raw_writel(ECT_CTI_CHAN_2, ECT_CTI_INEN(ECT_CTI_TRIGIN_1)); + /* Channel to triggers mapping */ + __raw_writel(ECT_CTI_CHAN_2, ECT_CTI_OUTEN(ECT_CTI_TRIGOUT_2)); + /* Trigger to Channel Mapping */ + __raw_writel(ECT_CTI_CHAN_3, ECT_CTI_INEN(ECT_CTI_TRIGIN_7)); + /* Channel to triggers mapping */ + __raw_writel(ECT_CTI_CHAN_3, ECT_CTI_OUTEN(ECT_CTI_TRIGOUT_6)); + /* Enable CTI Logic */ + __raw_writel(ENABLE_ECT, ECT_CTI_CONTROL); +#endif + pmnc |= pmu->int_enable; + pmnc |= PMU_ENABLE; + + write_pmnc(pmnc); + pr_debug("arm11_pmu_start: pmnc: %#08x mask: %08x\n", pmnc, + pmu->int_enable); + + /* Enable EVTMON with Edge triggered interrupt of one Clock Cycle */ + __raw_writel((__raw_readl(L2EM_CTRL) | + (L2EM_INT_EDGE | L2EM_INT_CLK_CYCLES)), L2EM_CTRL); + __raw_writel((__raw_readl(L2EM_CTRL) | L2EM_ENABLE_MASK), L2EM_CTRL); + + return 0; +} + +/*! + * function detect the ARM11 performance counters + */ +static int arm11_detect_pmu(void) +{ + int ret = 0; + u32 id, rev; + + id = (read_cpuid(CPUID_ID) >> 0x10) & 0xF; + + switch (id) { + case 7: + pmu = &pmu_parms[0]; + rev = read_cpuid(CPUID_ID); + /* Check if the ARM11 core is less than or equal to R0P2 */ + if ((((rev >> 0x14) & 0xF) == VAR_NUM) + && (((rev & 0xF) <= REV_NUM))) { + r0p2_or_older_core = 1; + } + break; + default: + ret = -ENODEV; + break; + } + + if (!ret) { + op_arm_spec.name = pmu->name; + op_arm_spec.num_counters = pmu->num_counters; + pr_debug("arm11_detect_pmu: detected %s PMU\n", pmu->name); + } + + return ret; +} + +struct op_arm_model_spec op_arm_spec = { + .init = arm11_detect_pmu, + .setup_ctrs = arm11_setup_ctrs, + .start = arm11_pmu_start, + .stop = arm11_pmu_stop, +}; diff -urN linux-2.6.26/arch/arm/oprofile/op_model_arm11_core.c linux-2.6.26-lab126/arch/arm/oprofile/op_model_arm11_core.c --- linux-2.6.26/arch/arm/oprofile/op_model_arm11_core.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/oprofile/op_model_arm11_core.c 2010-08-10 04:14:05.000000000 -0400 @@ -13,7 +13,12 @@ #include "op_counter.h" #include "op_arm_model.h" #include "op_model_arm11_core.h" +#include "evtmon_regs.h" +#define NEED_OPROFILE_CCNT_FIX +#ifdef NEED_OPROFILE_CCNT_FIX /* Workaround to correctly map from user space counters to kernel space counters */ +struct op_counter_config tmp; +#endif /* * ARM11 PMU support */ @@ -63,6 +68,12 @@ arm11_write_pmnc(PMCR_OFL_PMN0 | PMCR_OFL_PMN1 | PMCR_OFL_CCNT | PMCR_C | PMCR_P); +#ifdef NEED_OPROFILE_CCNT_FIX /* Workaround to correctly map from user space counters to kernel space counters */ + tmp = counter_config[PMN0]; + counter_config[PMN0] = counter_config[PMN1]; + counter_config[PMN1] = counter_config[CCNT]; + counter_config[CCNT] = tmp; +#endif for (pmnc = 0, cnt = PMN0; cnt <= CCNT; cnt++) { unsigned long event; @@ -119,16 +130,49 @@ unsigned int cnt; u32 pmnc; +#ifdef ECT_WORKAROUND + /* Disable L2_EVTMON */ + __raw_writel((__raw_readl(L2EM_CTRL) & ~EVTMON_ENABLE), L2EM_CTRL); + + /* Disable ARM11 PMU while retaining interrupts and overflow bits */ + pmnc = arm11_read_pmnc(); + pmnc &= ~(PMU_ENABLE | PMU_OVERFLOWBIT_MASK); + arm11_write_pmnc(pmnc); + + while (__raw_readl(ECT_CTI_TRIGOUTSTATUS) & ECT_CTI_CHAN_2) + __raw_writel(ACK_TRIG_OUT_2, ECT_CTI_INTACK); + + pmnc = arm11_read_pmnc(); + + /* Re-enable ARM11 PMU */ + pmnc |= PMU_ENABLE; + arm11_write_pmnc(pmnc); + + /* Re-enable L2_EVTMON */ + __raw_writel((__raw_readl(L2EM_CTRL) | L2EM_ENABLE_MASK), L2EM_CTRL); +#else pmnc = arm11_read_pmnc(); +#endif for (cnt = PMN0; cnt <= CCNT; cnt++) { if ((pmnc & (PMCR_OFL_PMN0 << cnt)) && (pmnc & (PMCR_IEN_PMN0 << cnt))) { arm11_reset_counter(cnt); +#ifdef NEED_OPROFILE_CCNT_FIX /* Workaround to correctly map from user space counters to kernel space counters */ + if (cnt == PMN0) + oprofile_add_sample(regs, CPU_COUNTER(smp_processor_id(), PMN1)); + else if (cnt == PMN1) + oprofile_add_sample(regs, CPU_COUNTER(smp_processor_id(), CCNT)); + else if (cnt == CCNT) + oprofile_add_sample(regs, CPU_COUNTER(smp_processor_id(), PMN0)); +#else oprofile_add_sample(regs, CPU_COUNTER(smp_processor_id(), cnt)); +#endif } } +#ifndef ECT_WORKAROUND /* Clear counter flag(s) */ arm11_write_pmnc(pmnc); +#endif return IRQ_HANDLED; } diff -urN linux-2.6.26/arch/arm/oprofile/op_model_arm11_core.h linux-2.6.26-lab126/arch/arm/oprofile/op_model_arm11_core.h --- linux-2.6.26/arch/arm/oprofile/op_model_arm11_core.h 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/oprofile/op_model_arm11_core.h 2010-08-10 04:14:05.000000000 -0400 @@ -35,6 +35,8 @@ #define CCNT 2 #define CPU_COUNTER(cpu, counter) ((cpu) * 3 + (counter)) +#define PMU_ENABLE 0x001 /* Enable counters */ +#define PMU_OVERFLOWBIT_MASK 0x700 int arm11_setup_pmu(void); int arm11_start_pmu(void); @@ -42,4 +44,15 @@ int arm11_request_interrupts(int *, int); void arm11_release_interrupts(int *, int); +#ifdef CONFIG_OPROFILE_ARM11_EVTMON +extern int arm11_evtmon_setup_ctrs(void); +extern void arm11_evtmon_stop(void); +extern int arm11_evtmon_start(void); +extern int arm11_evtmon_detect(void); +#else +#define arm11_evtmon_setup_ctrs() do {} while(0) +#define arm11_evtmon_stop() do {} while(0) +#define arm11_evtmon_start() do {} while(0) +#define arm11_evtmon_detect() do {} while(0) +#endif #endif diff -urN linux-2.6.26/arch/arm/oprofile/op_model_arm11_evtmon.c linux-2.6.26-lab126/arch/arm/oprofile/op_model_arm11_evtmon.c --- linux-2.6.26/arch/arm/oprofile/op_model_arm11_evtmon.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/oprofile/op_model_arm11_evtmon.c 2010-08-10 04:14:05.000000000 -0400 @@ -0,0 +1,188 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup MXC_Oprofile ARM11 EVTMON Driver for Oprofile + */ + +/*! + * @file op_model_arm11_evtmon.c + * + *Based on the op_model_xscale.c driver by author Zwane Mwaikambo + * + * @ingroup MXC_Oprofile + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "op_counter.h" +#include "op_arm_model.h" +#include "evtmon_regs.h" + +struct pmu_counter { + volatile unsigned long ovf; + unsigned long reset_counter; +}; + +enum { EMC0 = MAX_PMUCOUNTERS, EMC1, EMC2, EMC3, MAX_L2COUNTERS }; + +static struct pmu_counter results[MAX_L2COUNTERS]; + +struct pmu_type { + int id; + char *name; + int num_counters; + unsigned int int_enable; + unsigned int cnt_ovf[MAX_L2COUNTERS]; + unsigned int int_mask[MAX_L2COUNTERS]; +}; + +static struct pmu_type pmu_parms[] = { + { + .id = 0, + .int_mask = {[EMC0] = 0x800,[EMC1] = 0x400,[EMC2] = + 0x200,[EMC3] = 0x100}, + .cnt_ovf = {[EMC0] = 0x1,[EMC1] = 0x2,[EMC2] = 0x4,[EMC3] = 0x8}, + }, +}; + +static struct pmu_type *pmu; + +extern void l2x0_evtbus_enable(void); +extern void l2x0_evtbus_disable(void); + +/*! + * function is used to write the EVTMON counter configuration register. + */ +int l2em_configure_counter(int nr, int type) +{ + /* Configure the counter event source */ + __raw_writel(((type << 2) & 0x7c), L2EM_CC(nr)); + if (type) + __raw_writel((__raw_readl(L2EM_CC(nr)) | EM_SET_INT), + L2EM_CC(nr)); + + return 0; +} + +/*! + * function is used to write the EVTMON counters + */ +void write_l2counter(int nr, u32 val) +{ + __raw_writel(val, L2EM_CNT(nr)); +} + +/*! + * function is used to check the status of the ARM11 evtmon counters + */ +int arm11_evtmon_setup_ctrs(void) +{ + int i; + + for (i = EMC0; i < MAX_L2COUNTERS; i++) { + if (counter_config[i].enabled) + continue; + counter_config[i].event = EVT_UNUSED; + } + + for (i = EMC0; i < MAX_L2COUNTERS; i++) { + if (counter_config[i].event == EVT_UNUSED) { + counter_config[i].event = 0; + pmu->int_enable &= ~pmu->int_mask[i]; + pr_debug + ("arm11_setup_ctrs: The counter event is %lu for counter%d\n", + counter_config[i].event, i); + continue; + } + + results[i].reset_counter = counter_config[i].count; + write_l2counter(i - EMC0, -(u32) counter_config[i].count); + l2em_configure_counter(i - EMC0, counter_config[i].event); + + pmu->int_enable |= pmu->int_mask[i]; + pr_debug + ("arm11_setup_ctrs: The values of int mask and enables are %x, %x\n", + pmu->int_mask[i], pmu->int_enable); + + } + + return 0; +} + +/*! + * function used to start the ARM11 evtmon counters + */ +void arm11_evtmon_stop(void) +{ + + /* Disable the EVTMON */ + __raw_writel((__raw_readl(L2EM_CTRL) & ~EVTMON_ENABLE), L2EM_CTRL); + + /* Disable the EVTBUS */ + l2x0_evtbus_disable(); + +} + +/*! + * function used to start the ARM11 evtmon counters + */ +int arm11_evtmon_start(void) +{ + + /* Enable the EVTBUS */ + l2x0_evtbus_enable(); + +#ifdef ECT_WORKAROUND + __raw_writel(ENABLE_CTI_CLOCK, CLKCTL_SET_CTRL); + /* Unlock the AHB Interface */ + __raw_writel(UNLOCK_ECT_CODE, ECT_CTI_LOCK); + /* Trigger to Channel Mapping */ + __raw_writel(ECT_CTI_CHAN_2, ECT_CTI_INEN(ECT_CTI_TRIGIN_1)); + /* Channel to triggers mapping */ + __raw_writel(ECT_CTI_CHAN_2, ECT_CTI_OUTEN(ECT_CTI_TRIGOUT_2)); + /* Trigger to Channel Mapping */ + __raw_writel(ECT_CTI_CHAN_3, ECT_CTI_INEN(ECT_CTI_TRIGIN_7)); + /* Channel to triggers mapping */ + __raw_writel(ECT_CTI_CHAN_3, ECT_CTI_OUTEN(ECT_CTI_TRIGOUT_6)); + /* Enable CTI Logic */ + __raw_writel(ENABLE_ECT, ECT_CTI_CONTROL); +#endif + + /* Enable EVTMON with Edge triggered interrupt of one Clock Cycle */ + __raw_writel((__raw_readl(L2EM_CTRL) | + (L2EM_INT_EDGE | L2EM_INT_CLK_CYCLES)), L2EM_CTRL); + __raw_writel((__raw_readl(L2EM_CTRL) | L2EM_ENABLE_MASK), L2EM_CTRL); + + return 0; +} + +/*! + * function detect the ARM11 evtmon counters + */ +int arm11_evtmon_detect(void) +{ + int ret = 0; + + pmu = &pmu_parms[0]; + op_armv6_spec.num_counters = MAX_L2COUNTERS; + + return ret; +} diff -urN linux-2.6.26/arch/arm/oprofile/op_model_v6.c linux-2.6.26-lab126/arch/arm/oprofile/op_model_v6.c --- linux-2.6.26/arch/arm/oprofile/op_model_v6.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/oprofile/op_model_v6.c 2010-08-10 04:14:05.000000000 -0400 @@ -28,16 +28,21 @@ #include "op_counter.h" #include "op_arm_model.h" #include "op_model_arm11_core.h" +#include "evtmon_regs.h" static int irqs[] = { #ifdef CONFIG_ARCH_OMAP2 3, #endif +#ifdef CONFIG_ARCH_MXC + EVENT_OVERFLOW_INT, +#endif }; static void armv6_pmu_stop(void) { arm11_stop_pmu(); + arm11_evtmon_stop(); arm11_release_interrupts(irqs, ARRAY_SIZE(irqs)); } @@ -46,21 +51,31 @@ int ret; ret = arm11_request_interrupts(irqs, ARRAY_SIZE(irqs)); - if (ret >= 0) + if (ret >= 0){ ret = arm11_start_pmu(); + arm11_evtmon_start(); + } return ret; } +static int armv6_setup_pmu(void) +{ + arm11_setup_pmu(); + arm11_evtmon_setup_ctrs(); + return 0; +} + static int armv6_detect_pmu(void) { + arm11_evtmon_detect(); return 0; } struct op_arm_model_spec op_armv6_spec = { .init = armv6_detect_pmu, .num_counters = 3, - .setup_ctrs = arm11_setup_pmu, + .setup_ctrs = armv6_setup_pmu, .start = armv6_pmu_start, .stop = armv6_pmu_stop, .name = "arm/armv6", diff -urN linux-2.6.26/arch/arm/oprofile/op_model_xscale.c linux-2.6.26-lab126/arch/arm/oprofile/op_model_xscale.c --- linux-2.6.26/arch/arm/oprofile/op_model_xscale.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/oprofile/op_model_xscale.c 2010-08-10 04:14:05.000000000 -0400 @@ -381,8 +381,9 @@ { int ret; u32 pmnc = read_pmnc(); + int irq_flags = IRQF_DISABLED | IRQF_NODELAY; - ret = request_irq(XSCALE_PMU_IRQ, xscale_pmu_interrupt, IRQF_DISABLED, + ret = request_irq(XSCALE_PMU_IRQ, xscale_pmu_interrupt, irq_flags, "XScale PMU", (void *)results); if (ret < 0) { diff -urN linux-2.6.26/arch/arm/plat-mxc/Kconfig linux-2.6.26-lab126/arch/arm/plat-mxc/Kconfig --- linux-2.6.26/arch/arm/plat-mxc/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/Kconfig 2010-08-10 04:14:11.000000000 -0400 @@ -6,15 +6,158 @@ prompt "MXC/iMX System Type" default ARCH_MX3 +config ARCH_MX37 + bool "MX37-based" + help + This enables support for systems based on Freescale i.MX37 + +config ARCH_MX35 + bool "MX35-based" + help + This enables support for systems based on Freescale i.MX35 + +config ARCH_MX51 + bool "MX51-based" + help + This enables support for systems based on Freescale i.MX51 + config ARCH_MX3 bool "MX3-based" help - This enables support for systems based on the Freescale i.MX3 family + This enables support for systems based on the Freescale i.MX31 and i.MX32 + +config ARCH_MX27 + bool "MX27-based" + help + This enables support for systems based on the Freescale i.MX27 + +config ARCH_MX21 + bool "MX21-based" + help + This enables support for systems based on the Freescale i.MX21 endchoice +source "arch/arm/mach-mx27/Kconfig" + +source "arch/arm/mach-mx21/Kconfig" + source "arch/arm/mach-mx3/Kconfig" +source "arch/arm/mach-mx35/Kconfig" + +source "arch/arm/mach-mx37/Kconfig" + +source "arch/arm/mach-mx51/Kconfig" + endmenu +config MXC_TZIC + bool + depends on ARCH_MXC + +config ARCH_HAS_RNGA + bool + depends on ARCH_MXC + +config ARCH_HAS_RNGC + bool + depends on ARCH_MXC + +config MXC_DSP_BRINGUP + bool + depends on ARCH_MXC + +config ARCH_HAS_EVTMON + bool + depends on ARCH_MXC + +config MXC_EMMA + bool + depends on ARCH_MXC + +config MXC_FB_IRAM + bool + depends on ARCH_MXC + +config DMA_ZONE_SIZE + int "DMA memory zone size" + range 0 64 + default 24 + help + This is the size in MB for the DMA zone. The DMA zone is used for + dedicated memory for large contiguous video buffers + +# set iff we need the 1504 transceiver code +config ISP1504_MXC + bool + select ISP1504_MXC_OTG if USB_GADGET && USB_EHCI_HCD && USB_OTG + default y if USB_EHCI_FSL_1504 || USB_GADGET_FSL_1504 + +config ISP1504_MXC_OTG + tristate + help + Support for USB OTG pin detect using the ISP1504 transceiver on MXC platforms. + +# set iff we need the UTMI transceiver code +config UTMI_MXC + bool + select UTMI_MXC_OTG if ARCH_MX25 && USB_GADGET && USB_EHCI_HCD && USB_OTG + default y if USB_EHCI_FSL_UTMI || USB_GADGET_FSL_UTMI + depends on ARCH_MX25 || ARCH_MX35 || ARCH_MX37 || ARCH_MX51 + +config UTMI_MXC_OTG + tristate + help + Support for USB OTG pin detect using the UTMI transceiver on MXC platforms. + +# set iff we need the 1301 transceiver code +config ISP1301_MXC + bool + default y if USB_EHCI_FSL_1301 || USB_GADGET_FSL_1301 + select I2C_MXC + +# set iff we need the mx13783 transceiver code +config MC13783_MXC + bool + default y if USB_EHCI_FSL_MC13783 || USB_GADGET_FSL_MC13783 + select SPI_MXC + +choice + prompt "Select serial USB transceiver mode" + depends on ISP1301_MXC || MC13783_MXC + default MXC_USB_SU6 + +config MXC_USB_SU6 + bool "Single Ended Unidirectional Mode" + help + If you say yes to this option, the serial tranceiver operates in SU6 mode. + This option will work for either the Freescale MC13783 or Philips ISP1301 + transceiver. + +config MXC_USB_SB3 + bool "Single Ended Bidirectional Mode" + help + If you say yes to this option, the serial tranceiver operates in SB3 mode. + Not recommended for the Freescale MC13783. + +config MXC_USB_DU6 + bool "Differential Unidirectional Mode" + help + If you say yes to this option, the serial tranceiver operates in DU6 mode. + +config MXC_USB_DB4 + bool "Differential Bidirectional Mode" + help + If you say yes to this option, the serial tranceiver operates in DB4 mode. + +endchoice + +config MXC_PWM + tristate "Enable PWM driver" + depends on ARCH_MXC + select HAVE_PWM + help + Enable support for MXC PWM controller + endif diff -urN linux-2.6.26/arch/arm/plat-mxc/Makefile linux-2.6.26-lab126/arch/arm/plat-mxc/Makefile --- linux-2.6.26/arch/arm/plat-mxc/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/Makefile 2010-08-10 04:14:11.000000000 -0400 @@ -3,4 +3,57 @@ # # Common support -obj-y := irq.o +obj-y := cpu_common.o gpio.o clock.o wdog.o snoop.o io.o + +ifneq ($(CONFIG_ARCH_MX21)$(CONFIG_ARCH_MX27),y) +obj-y += time.o spba.o sdma/ +endif + +ifeq ($(CONFIG_MXC_TZIC),y) +obj-y += tzic.o +else +obj-y += irq.o +endif + +obj-$(CONFIG_ARCH_MX21) += dma_mx2.o +obj-$(CONFIG_ARCH_MX27) += dma_mx2.o usb_common.o +obj-$(CONFIG_ARCH_MX3) += dptc.o usb_common.o entry-pm.o +obj-$(CONFIG_ARCH_MX35) += usb_common.o serialxc.o +obj-$(CONFIG_ARCH_MX37) += usb_common.o utmixc.o dptc.o dvfs_core.o +obj-$(CONFIG_ARCH_MX51) += usb_common.o utmixc.o dvfs_core.o + +# LEDs support +obj-$(CONFIG_LEDS) += leds.o + +# CPU FREQ support +obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o + +# USB support +obj-$(CONFIG_ISP1504_MXC) += isp1504xc.o +obj-$(CONFIG_ISP1301_MXC) += isp1301xc.o +obj-$(CONFIG_MC13783_MXC) += mc13783_xc.o + +# obj-$(CONFIG_USB_EHCI_FSL_UTMI) += utmixc.o +ifneq ($(strip $(CONFIG_USB_EHCI_FSL_UTMI) $(CONFIG_USB_GADGET_FSL_UTMI)),) +obj-y += utmixc.o +endif + +ifneq ($(CONFIG_USB_EHCI_ARC_H1)$(CONFIG_USB_EHCI_ARC_H2),) +ifneq ($(CONFIG_ARCH_MX51),y) +obj-y += serialxc.o +else +obj-y += isp1504xc.o +endif +endif + +ifneq ($(CONFIG_ARCH_MX25)$(CONFIG_USB),) +obj-y += usb_common.o +endif + +ifeq ($(CONFIG_ARCH_MX25),y) +ifneq ($(CONFIG_USB_EHCI_ARC_H2),) +obj-y += serialxc.o +endif +endif + +obj-$(CONFIG_MXC_PWM) += pwm.o diff -urN linux-2.6.26/arch/arm/plat-mxc/clock.c linux-2.6.26-lab126/arch/arm/plat-mxc/clock.c --- linux-2.6.26/arch/arm/plat-mxc/clock.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/clock.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,683 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/* + * Based on arch/arm/plat-omap/clock.c + * + * Copyright (C) 2004 - 2005 Nokia corporation + * Written by Tuukka Tikkanen + * Modified for omap shared clock framework by Tony Lindgren + */ +/*! + * @file plat-mxc/clock.c + * + * @brief clk API implementation for MXC clocks. + * + * This file contains API defined in include/linux/clk.h for setting up and + * retrieving clocks. + * + * @ingroup CLOCKS + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +static LIST_HEAD(clocks); +static DEFINE_MUTEX(clocks_mutex); +static DEFINE_RAW_SPINLOCK(clockfw_lock); + +/*------------------------------------------------------------------------- + * Standard clock functions defined in include/linux/clk.h + *-------------------------------------------------------------------------*/ + +/*! + * @brief Function to retrieve a clock by name. + * + * Note that we first try to use device id on the bus + * and clock name. If this fails, we try to use ".". If this fails, + * we try to use clock name only. + * + * The reference count to the clock's module owner ref count is incremented. + * + * @param dev Device structure to get bus device id. + * @param id Clock name string + * + * @return Returns handle to clock on success or -ENOENT on failure. + */ +struct clk *clk_get(struct device *dev, const char *id) +{ + struct clk *p, *clk = ERR_PTR(-ENOENT); + int idno, len; + char *str; + + if (id == NULL) + return clk; + + if (dev == NULL || dev->bus != &platform_bus_type) + idno = -1; + else + idno = to_platform_device(dev)->id; + + mutex_lock(&clocks_mutex); + + list_for_each_entry(p, &clocks, node) { + if (p->id == idno && + strcmp(id, p->name) == 0 && try_module_get(p->owner)) { + clk = p; + goto found; + } + } + + str = strrchr(id, '.'); + if (str) { + len = str - id; + str++; + idno = simple_strtol(str, NULL, 10); + list_for_each_entry(p, &clocks, node) { + if (p->id == idno && (strlen(p->name) == len) && + strncmp(id, p->name, len) == 0 && + try_module_get(p->owner)) { + clk = p; + goto found; + } + } + } + + list_for_each_entry(p, &clocks, node) { + if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { + clk = p; + goto found; + } + } + + printk(KERN_WARNING "clk: Unable to get requested clock: %s\n", id); + + found: + mutex_unlock(&clocks_mutex); + + return clk; +} + +EXPORT_SYMBOL(clk_get); + +static void __clk_disable(struct clk *clk) +{ + if (clk->usecount > 0 && !(--clk->usecount)) { + if (clk->disable != NULL) { + clk->disable(clk); + } + if (likely((u32) clk->parent)) + __clk_disable(clk->parent); + if (unlikely((u32) clk->secondary)) + __clk_disable(clk->secondary); + } +} + +static int __clk_enable(struct clk *clk) +{ + int ret = 0; + + if (clk->usecount++ == 0) { + if (likely((u32) clk->parent)) { + ret = __clk_enable(clk->parent); + + if (unlikely(ret != 0)) { + goto err1; + } + } + + if (unlikely((u32) clk->secondary)) { + ret = __clk_enable(clk->secondary); + + if (unlikely(ret != 0)) { + goto err2; + } + } + + if (clk->enable) { + ret = clk->enable(clk); + } + + if (unlikely(ret != 0)) { + goto err3; + } + } + return 0; + + err3: + if (clk->secondary) + __clk_disable(clk->secondary); + err2: + if (clk->parent) + __clk_disable(clk->parent); + err1: + clk->usecount--; + return ret; +} + +/*! + * @brief Function to enable a clock. + * + * This function increments the reference count on the clock and enables the + * clock if not already enabled. The parent clock tree is recursively enabled. + * + * @param clk Handle to clock to enable. + * + * @return Returns 0 on success or error code on failure. + */ +int clk_enable(struct clk *clk) +{ + unsigned long flags; + int ret = 0; + + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + spin_lock_irqsave(&clockfw_lock, flags); + + ret = __clk_enable(clk); + + spin_unlock_irqrestore(&clockfw_lock, flags); + +#if defined(CONFIG_CPU_FREQ) + if ((clk->flags & CPU_FREQ_TRIG_UPDATE) + && (clk_get_usecount(clk) == 1)) + cpufreq_update_policy(0); +#endif + return ret; +} + +EXPORT_SYMBOL(clk_enable); + +/*! + * @brief Function to disable a clock. + * + * This function decrements the reference count on the clock and disables the + * clock when reference count is 0. The parent clock tree is recursively + * disabled. + * + * @param clk Handle to clock to disable. + * + */ +void clk_disable(struct clk *clk) +{ + unsigned long flags; + + if (clk == NULL || IS_ERR(clk)) + return; + + spin_lock_irqsave(&clockfw_lock, flags); + + __clk_disable(clk); + + spin_unlock_irqrestore(&clockfw_lock, flags); + +#if defined(CONFIG_CPU_FREQ) + if ((clk->flags & CPU_FREQ_TRIG_UPDATE) + && (clk_get_usecount(clk) == 0)) + cpufreq_update_policy(0); +#endif +} + +EXPORT_SYMBOL(clk_disable); + +/*! + * @brief Function to get the usage count for the requested clock. + * + * This function returns the reference count for the clock. + * + * @param clk Handle to clock to disable. + * + * @return Returns the usage count for the requested clock. + */ +int clk_get_usecount(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return 0; + + return clk->usecount; +} + +EXPORT_SYMBOL(clk_get_usecount); + +/*! + * @brief Function to retrieve the clock rate for a clock. + * + * @param clk Handle to clock to retrieve. + * + * @return Returns the clock's rate in Hz. + * + */ +unsigned long clk_get_rate(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return 0; + + return clk->rate; +} + +EXPORT_SYMBOL(clk_get_rate); + +/*! + * @brief Function to decrement the clock's module reference count. + * + * @param clk Handle to clock to put. + * + */ +void clk_put(struct clk *clk) +{ + if (clk && !IS_ERR(clk)) + module_put(clk->owner); +} + +EXPORT_SYMBOL(clk_put); + +/*! + * @brief Function to round the requested clock rate to the nearest supported + * rate that is less than or equal to the requested rate. This is dependent on + * the clock's current parent. + * + * @param clk Handle to clock to retrieve. + * @param rate Desired clock rate in Hz. + * + * @return Returns the nearest supported rate in Hz. + * + */ +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (clk == NULL || IS_ERR(clk) || !clk->round_rate) + return 0; + + return clk->round_rate(clk, rate); +} + +EXPORT_SYMBOL(clk_round_rate); + +/* Propagate rate to children */ +void propagate_rate(struct clk *tclk) +{ + struct clk *clkp; + + if (tclk == NULL || IS_ERR(tclk)) + return; + + pr_debug("mxc clock: finding children of %s-%d\n", tclk->name, + tclk->id); + list_for_each_entry(clkp, &clocks, node) { + if (likely(clkp->parent != tclk)) + continue; + pr_debug("mxc clock: %s-%d: recalculating rate: old = %lu, ", + clkp->name, clkp->id, clkp->rate); + if (likely((u32) clkp->recalc)) + clkp->recalc(clkp); + else + clkp->rate = tclk->rate; + pr_debug("new = %lu\n", clkp->rate); + propagate_rate(clkp); + } +} + +/*! + * @brief Function to set the clock to the requested clock rate. The rate must + * match a supported rate exactly based on what clk_round_rate returns. + * + * @param clk Handle to clock to retrieve. + * @param rate Desired clock rate in Hz. + * + * @return Returns 0 on success, negative error code on failure. + * + */ +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long flags; + int ret = -EINVAL; + + if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0) + return ret; + + spin_lock_irqsave(&clockfw_lock, flags); + + ret = clk->set_rate(clk, rate); + if (unlikely((ret == 0) && (clk->flags & RATE_PROPAGATES))) + propagate_rate(clk); + + spin_unlock_irqrestore(&clockfw_lock, flags); + + return ret; +} + +EXPORT_SYMBOL(clk_set_rate); + +/*! + * @brief Function to set the clock's parent to another clock source. + * + * @param clk Handle to clock to retrieve. + * @param parent Desired parent clock input for the clock. + * + * @return Returns 0 on success, negative error code on failure. + * + */ +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + unsigned long flags; + int ret = -EINVAL; + struct clk *prev_parent = clk->parent; + + if (clk == NULL || IS_ERR(clk) || parent == NULL || + IS_ERR(parent) || clk->set_parent == NULL) + return ret; + + if (clk->usecount != 0) { + clk_enable(parent); + } + + spin_lock_irqsave(&clockfw_lock, flags); + ret = clk->set_parent(clk, parent); + if (ret == 0) { + clk->parent = parent; + if (clk->recalc) { + clk->recalc(clk); + } else { + clk->rate = parent->rate; + } + if (unlikely(clk->flags & RATE_PROPAGATES)) + propagate_rate(clk); + } + spin_unlock_irqrestore(&clockfw_lock, flags); + + if (clk->usecount != 0) { + clk_disable(prev_parent); + } + + return ret; +} + +EXPORT_SYMBOL(clk_set_parent); + +/*! + * @brief Function to retrieve the clock's parent clock source. + * + * @param clk Handle to clock to retrieve. + * + * @return Returns parent clk on success, NULL on failure. + * + */ +struct clk *clk_get_parent(struct clk *clk) +{ + struct clk *ret = NULL; + + if (clk == NULL || IS_ERR(clk)) + return ret; + + return clk->parent; +} + +EXPORT_SYMBOL(clk_get_parent); + +/*! + * @brief Function to add a new clock to the clock tree. + * + * @param clk Handle to clock to add. + * + * @return Returns 0 on success, negative error code on failure. + * + */ +int clk_register(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + mutex_lock(&clocks_mutex); + list_add(&clk->node, &clocks); + mutex_unlock(&clocks_mutex); + + return 0; +} + +EXPORT_SYMBOL(clk_register); + +/*! + * @brief Function to remove a clock from the clock tree. + * + * @param clk Handle to clock to add. + * + */ +void clk_unregister(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return; + + mutex_lock(&clocks_mutex); + list_del(&clk->node); + mutex_unlock(&clocks_mutex); +} + +EXPORT_SYMBOL(clk_unregister); + +void mxc_dump_clocks(void) +{ + struct clk *clkp; + list_for_each_entry(clkp, &clocks, node) { + printk("name:\t%s-%d\n", clkp->name, clkp->id); + printk("count:\t%d\n", clkp->usecount); + printk("rate:\t%lu\n", clkp->rate); + if (clkp->parent) + printk("parent:\t%s-%d\n\n", clkp->parent->name, + clkp->parent->id); + else + printk("parent:\tnone\n\n"); + } +} + +#ifdef CONFIG_PROC_FS +static int mxc_clock_read_proc(char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + struct clk *clkp; + char *p = page; + int len; + + list_for_each_entry(clkp, &clocks, node) { + p += sprintf(p, "%s-%d:\t\t%lu, %d", + clkp->name, clkp->id, clkp->rate, clkp->usecount); + if (clkp->parent) + p += sprintf(p, ", %s-%d\n", clkp->parent->name, + clkp->parent->id); + else + p += sprintf(p, "\n"); + } + + len = (p - page) - off; + if (len < 0) + len = 0; + + *eof = (len <= count) ? 1 : 0; + *start = page + off; + + return len; +} + +static int __init mxc_setup_proc_entry(void) +{ + struct proc_dir_entry *res; + + res = create_proc_read_entry("cpu/clocks", 0, NULL, + mxc_clock_read_proc, NULL); + if (!res) { + printk(KERN_ERR "Failed to create proc/cpu/clocks\n"); + return -ENOMEM; + } + return 0; +} + +late_initcall(mxc_setup_proc_entry); +#endif + +#ifdef CONFIG_DEBUG_FS + +/*------------------------------------------------------------------------- + Debug filesystem +-------------------------------------------------------------------------*/ +#include +#include + +static struct dentry *debugfs_root; +static struct dentry *debugfs_state; +static struct dentry *debugfs_state1; +static struct dentry *debugfs_state2; + +extern void mx35_show_pins(struct seq_file *s); + +static int mxc_clocks_show(struct seq_file *s, void *p) +{ + int t; + struct clk *clkp; + + list_for_each_entry(clkp, &clocks, node) { + t += seq_printf(s, "%s-%d:\t\t%lu, %d", + clkp->name, clkp->id, clkp->rate, clkp->usecount); + + if (clkp->parent) { + t += seq_printf(s, ", %s-%d\n", clkp->parent->name, + clkp->parent->id); + } + else + t += seq_printf(s, "\n"); + } + return 0; +} + +static int mxc_clocks_open(struct inode *inode, struct file *file) +{ + return single_open(file, mxc_clocks_show, inode->i_private); +} + +static const struct file_operations mxc_clocks_fops = { + .owner = THIS_MODULE, + .open = mxc_clocks_open, + .llseek = seq_lseek, + .read = seq_read, + .release = single_release, +}; + +static int mxc_pins_show(struct seq_file *s, void *p) +{ + mx35_show_pins(s); + return 0; +} + +static int mxc_pins_open(struct inode *inode, struct file *file) +{ + return single_open(file, mxc_pins_show, inode->i_private); +} + +static const struct file_operations mxc_pins_fops = { + .owner = THIS_MODULE, + .open = mxc_pins_open, + .llseek = seq_lseek, + .read = seq_read, + .release = single_release, +}; + +extern int mx35_show_registers(struct seq_file *s); + +static int mxc_regs_show(struct seq_file *s, void *p) +{ + mx35_show_registers(s); + return 0; +} + +static int mxc_regs_open(struct inode *inode, struct file *file) +{ + return single_open(file, mxc_regs_show, inode->i_private); +} + +static const struct file_operations mxc_regs_fops = { + .owner = THIS_MODULE, + .open = mxc_regs_open, + .llseek = seq_lseek, + .read = seq_read, + .release = single_release, +}; + +static int mxc_clocks_debugfs_init(void) +{ + struct dentry *root, *state, *state1, *state2; + int ret = -1; + + root = debugfs_create_dir("MX35", NULL); + if (IS_ERR(root) || !root) + goto err_root; + + state = debugfs_create_file("mxc_clock_tree", 0400, root, (void *)0, + &mxc_clocks_fops); + + if (!state) + goto err_state; + + state1 = debugfs_create_file("mxc_iomux_pins", 0400, root, (void *)0, + &mxc_pins_fops); + + if (!state1) + goto err_state; + + state2 = debugfs_create_file("mxc_cpu_registers", 0400, root, (void *)0, + &mxc_regs_fops); + + if (!state2) + goto err_state; + + debugfs_root = root; + debugfs_state = state; + debugfs_state1 = state1; + debugfs_state2 = state2; + + return 0; +err_state: + debugfs_remove(root); +err_root: + printk(KERN_ERR "mxc_clocks: debugfs is not available\n"); + return ret; +} +late_initcall(mxc_clocks_debugfs_init); + +static void __exit mxc_clocks_cleanup_debugfs(void) +{ + debugfs_remove(debugfs_state); + debugfs_remove(debugfs_state1); + debugfs_remove(debugfs_state2); + debugfs_remove(debugfs_root); + + debugfs_state = NULL; + debugfs_state1 = NULL; + debugfs_state2 = NULL; + debugfs_root = NULL; +} + +module_exit(mxc_clocks_cleanup_debugfs); + +#endif diff -urN linux-2.6.26/arch/arm/plat-mxc/cpu_common.c linux-2.6.26-lab126/arch/arm/plat-mxc/cpu_common.c --- linux-2.6.26/arch/arm/plat-mxc/cpu_common.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/cpu_common.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,85 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +extern int mxc_early_serial_console_init(char *); + +/*! + * @file plat-mxc/cpu_common.c + * + * @brief This file contains the common CPU initialization code. + * + * @ingroup MSL_MX31 MSL_MXC91321 + */ + +static void __init system_rev_setup(char **p) +{ + system_rev = simple_strtoul(*p, NULL, 16); +} + +__early_param("system_rev=", system_rev_setup); + +int mxc_jtag_enabled; /* OFF: 0 (default), ON: 1 */ + +/* + * Here are the JTAG options from the command line. By default JTAG + * is OFF which means JTAG is not connected and WFI is enabled + * + * "on" -- JTAG is connected, so WFI is disabled + * "off" -- JTAG is disconnected, so WFI is enabled + */ + +static void __init jtag_wfi_setup(char **p) +{ + if (memcmp(*p, "on", 2) == 0) { + mxc_jtag_enabled = 1; + *p += 2; + } else if (memcmp(*p, "off", 3) == 0) { + mxc_jtag_enabled = 0; + *p += 3; + } +} + +__early_param("jtag=", jtag_wfi_setup); + +void __init mxc_cpu_common_init(void) +{ + pr_info("CPU is %s%x Revision %u.%u\n", + (mxc_cpu() < 0x100) ? "i.MX" : "MXC", + mxc_cpu(), mxc_cpu_rev_major(), mxc_cpu_rev_minor()); +} + +/** + * early_console_setup - setup debugging console + * + * Consoles started here require little enough setup that we can start using + * them very early in the boot process, either right after the machine + * vector initialization, or even before if the drivers can detect their hw. + * + * Returns non-zero if a console couldn't be setup. + * This function is developed based on + * early_console_setup function as defined in arch/ia64/kernel/setup.c + */ +int __init early_console_setup(char *cmdline) +{ + int earlycons = 0; + +#ifdef CONFIG_SERIAL_MXC_CONSOLE + if (!mxc_early_serial_console_init(cmdline)) + earlycons++; +#endif + + return (earlycons) ? 0 : -1; +} diff -urN linux-2.6.26/arch/arm/plat-mxc/cpufreq.c linux-2.6.26-lab126/arch/arm/plat-mxc/cpufreq.c --- linux-2.6.26/arch/arm/plat-mxc/cpufreq.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/cpufreq.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,595 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file cpufreq.c + * + * @brief A driver for the Freescale Semiconductor i.MXC CPUfreq module. + * + * The CPUFREQ driver is for controling CPU frequency. It allows you to change + * the CPU clock speed on the fly. + * + * @ingroup PM + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int low_bus_freq_mode; +int high_bus_freq_mode; +int cpu_freq_khz_min; +int cpu_freq_khz_max; +int arm_lpm_clk; +int arm_normal_clk; +char *gp_reg_id = "SW1"; +char *lp_reg_id = "SW2"; +int axi_c_clk_support; + +static struct clk *cpu_clk; +static struct clk *main_bus_clk; +static struct clk *pll2; +static struct clk *axi_a_clk; +static struct clk *axi_b_clk; +static struct clk *axi_c_clk; +static struct clk *emi_core_clk; +static struct clk *nfc_clk; +static struct clk *ahb_clk; +static struct clk *vpu_clk; +static struct clk *vpu_core_clk; +static struct clk *arm_axi_clk; +static struct clk *ddr_clk; +static struct clk *ipu_clk; +static struct clk *periph_apm_clk; +static struct clk *lp_apm; +static struct clk *osc; +static struct regulator *gp_regulator; +static struct regulator *lp_regulator; +static struct cpu_wp *cpu_wp_tbl; +static struct cpufreq_frequency_table imx_freq_table[4]; + +extern int dvfs_core_is_active; +extern int cpu_wp_nr; + +static int set_cpu_freq(int freq) +{ + int ret = 0; + int org_cpu_rate; + int gp_volt = 0; + int i; + + org_cpu_rate = clk_get_rate(cpu_clk); + + if (org_cpu_rate == freq) + return ret; + + for (i = 0; i < cpu_wp_nr; i++) { + if (freq == cpu_wp_tbl[i].cpu_rate) + gp_volt = cpu_wp_tbl[i].cpu_voltage; + } + + if (gp_volt == 0) + return ret; + + /*Set the voltage for the GP domain. */ + if (freq > org_cpu_rate) { + ret = regulator_set_voltage(gp_regulator, gp_volt); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!\n"); + return ret; + } + } + + ret = clk_set_rate(cpu_clk, freq); + if (ret != 0) { + printk(KERN_DEBUG "cannot set CPU clock rate\n"); + return ret; + } + + if (freq < org_cpu_rate) { + ret = regulator_set_voltage(gp_regulator, gp_volt); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!\n"); + return ret; + } + } + + return ret; +} + +static int set_low_bus_freq(void) +{ + int ret = 0; + unsigned long lp_lpm_clk; + + struct clk *p_clk; + struct clk *amode_parent_clk; + + if (axi_c_clk_support == 0) + return 0; + + lp_lpm_clk = clk_get_rate(lp_apm); + amode_parent_clk = lp_apm; + p_clk = clk_get_parent(periph_apm_clk); + + /* Make sure osc_clk is the parent of lp_apm. */ + if (clk_get_parent(amode_parent_clk) != osc) + clk_set_parent(amode_parent_clk, osc); + + /* Set the parent of periph_apm_clk to be lp_apm */ + clk_set_parent(periph_apm_clk, amode_parent_clk); + amode_parent_clk = periph_apm_clk; + + p_clk = clk_get_parent(main_bus_clk); + /* Set the parent of main_bus_clk to be periph_apm_clk */ + clk_set_parent(main_bus_clk, amode_parent_clk); + + clk_set_rate(axi_a_clk, lp_lpm_clk); + clk_set_rate(axi_b_clk, lp_lpm_clk); + clk_set_rate(axi_c_clk, lp_lpm_clk); + clk_set_rate(emi_core_clk, lp_lpm_clk); + clk_set_rate(nfc_clk, 4800000); + clk_set_rate(ahb_clk, lp_lpm_clk); + + amode_parent_clk = emi_core_clk; + + p_clk = clk_get_parent(arm_axi_clk); + if (p_clk != amode_parent_clk) + clk_set_parent(arm_axi_clk, amode_parent_clk); + + p_clk = clk_get_parent(vpu_clk); + if (p_clk != amode_parent_clk) + clk_set_parent(vpu_clk, amode_parent_clk); + + p_clk = clk_get_parent(vpu_core_clk); + if (p_clk != amode_parent_clk) + clk_set_parent(vpu_core_clk, amode_parent_clk); + + /* Set the voltage to 1.0v for the LP domain. */ + ret = regulator_set_voltage(lp_regulator, 1000000); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!!!\n"); + return ret; + } + + low_bus_freq_mode = 1; + high_bus_freq_mode = 0; + return ret; +} + +static int set_high_bus_freq(void) +{ + struct clk *p_clk; + struct clk *rmode_parent_clk; + int ret = 0; + + if (axi_c_clk_support == 0) + return 0; + + if (!low_bus_freq_mode) + return ret; + + low_bus_freq_mode = 0; + + /* Set the voltage to 1.2v for the LP domain. */ + ret = regulator_set_voltage(lp_regulator, 1200000); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT SET LP VOLTAGE!!!!!!\n"); + return ret; + } + + rmode_parent_clk = pll2; + + /* Set the dividers before setting the parent clock. */ + clk_set_rate(axi_a_clk, 4800000); + clk_set_rate(axi_b_clk, 4000000); + clk_set_rate(axi_c_clk, 6000000); + + clk_set_rate(emi_core_clk, 4800000); + clk_set_rate(ahb_clk, 4800000); + + /* Set the parent of main_bus_clk to be pll2 */ + p_clk = clk_get_parent(main_bus_clk); + clk_set_parent(main_bus_clk, rmode_parent_clk); + udelay(5); + high_bus_freq_mode = 1; + return ret; +} + +static int low_freq_bus_used(void) +{ + if (axi_c_clk_support == 0) + return 0; + + if ((clk_get_usecount(ipu_clk) == 0) + && (clk_get_usecount(vpu_clk) == 0)) + return 1; + else + return 0; +} + +static int mxc_verify_speed(struct cpufreq_policy *policy) +{ + if (policy->cpu != 0) + return -EINVAL; + + return cpufreq_frequency_table_verify(policy, imx_freq_table); +} + +static unsigned int mxc_get_speed(unsigned int cpu) +{ + if (cpu) + return 0; + + return clk_get_rate(cpu_clk) / 1000; +} + +static int calc_frequency_khz(int target, unsigned int relation) +{ + int i; + + if (relation == CPUFREQ_RELATION_H) { + for (i = ARRAY_SIZE(imx_freq_table) - 1; i > 0; i--) { + if (imx_freq_table[i].frequency <= target) + return imx_freq_table[i].frequency; + } + } else if (relation == CPUFREQ_RELATION_L) { + for (i = 0; i < ARRAY_SIZE(imx_freq_table) - 1; i++) { + if (imx_freq_table[i].frequency >= target) + return imx_freq_table[i].frequency; + } + } + printk(KERN_ERR "Error: No valid cpufreq relation\n"); + return cpu_freq_khz_max; +} + +static int mxc_set_target(struct cpufreq_policy *policy, + unsigned int target_freq, unsigned int relation) +{ + struct cpufreq_freqs freqs; + long freq_Hz; + int low_freq_bus_ready = 0; + int ret = 0; + + /* + * Some governors do not respects CPU and policy lower limits + * which leads to bad things (division by zero etc), ensure + * that such things do not happen. + */ + if (target_freq < policy->cpuinfo.min_freq) + target_freq = policy->cpuinfo.min_freq; + + if (target_freq < policy->min) + target_freq = policy->min; + + freq_Hz = calc_frequency_khz(target_freq, relation) * 1000; + + freqs.old = clk_get_rate(cpu_clk) / 1000; + freqs.new = freq_Hz / 1000; + freqs.cpu = 0; + freqs.flags = 0; + + if ((freqs.old == freqs.new) && (freqs.new != cpu_freq_khz_min)) + return 0; + + low_freq_bus_ready = low_freq_bus_used(); + + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + + if ((freq_Hz == arm_lpm_clk) && (!low_bus_freq_mode) + && (low_freq_bus_ready)) { + set_low_bus_freq(); + if (!dvfs_core_is_active) + ret = set_cpu_freq(freq_Hz); + } else { + if (!high_bus_freq_mode) + set_high_bus_freq(); + + if (!dvfs_core_is_active) + ret = set_cpu_freq(freq_Hz); + if (low_bus_freq_mode) { + if (ret == 0) + set_high_bus_freq(); + } + } + + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + return ret; +} + +static int __init mxc_cpufreq_driver_init(struct cpufreq_policy *policy) +{ + int ret; + int i; + + printk(KERN_INFO "i.MXC CPU frequency driver\n"); + + if (policy->cpu != 0) + return -EINVAL; + + cpu_clk = clk_get(NULL, "cpu_clk"); + if (IS_ERR(cpu_clk)) { + printk(KERN_ERR "%s: failed to get cpu clock\n", __func__); + return PTR_ERR(cpu_clk); + } + + axi_c_clk = clk_get(NULL, "axi_c_clk"); + if (IS_ERR(axi_c_clk)) { + axi_c_clk_support = 0; + printk(KERN_ERR "%s: failed to get axi_c_clk\n", __func__); + } else { + axi_c_clk_support = 1; + main_bus_clk = clk_get(NULL, "main_bus_clk"); + if (IS_ERR(main_bus_clk)) { + printk(KERN_ERR "%s: failed to get main_bus_clk\n", + __func__); + return PTR_ERR(main_bus_clk); + } + + pll2 = clk_get(NULL, "pll2"); + if (IS_ERR(pll2)) { + printk(KERN_ERR "%s: failed to get pll2\n", __func__); + return PTR_ERR(pll2); + } + + axi_a_clk = clk_get(NULL, "axi_a_clk"); + if (IS_ERR(axi_a_clk)) { + printk(KERN_ERR "%s: failed to get axi_a_clk\n", + __func__); + return PTR_ERR(axi_a_clk); + } + + axi_b_clk = clk_get(NULL, "axi_b_clk"); + if (IS_ERR(axi_b_clk)) { + printk(KERN_ERR "%s: failed to get axi_b_clk\n", + __func__); + return PTR_ERR(axi_b_clk); + } + + emi_core_clk = clk_get(NULL, "emi_core_clk"); + if (IS_ERR(emi_core_clk)) { + printk(KERN_ERR "%s: failed to get emi_core_clk\n", + __func__); + return PTR_ERR(emi_core_clk); + } + + nfc_clk = clk_get(NULL, "nfc_clk"); + if (IS_ERR(nfc_clk)) { + printk(KERN_ERR "%s: failed to get nfc_clk\n", + __func__); + return PTR_ERR(nfc_clk); + } + + ahb_clk = clk_get(NULL, "ahb_clk"); + if (IS_ERR(ahb_clk)) { + printk(KERN_ERR "%s: failed to get ahb_clk\n", + __func__); + return PTR_ERR(ahb_clk); + } + + vpu_core_clk = clk_get(NULL, "vpu_core_clk"); + if (IS_ERR(vpu_core_clk)) { + printk(KERN_ERR "%s: failed to get vpu_core_clk\n", + __func__); + return PTR_ERR(vpu_core_clk); + } + + arm_axi_clk = clk_get(NULL, "arm_axi_clk"); + if (IS_ERR(arm_axi_clk)) { + printk(KERN_ERR "%s: failed to get arm_axi_clk\n", + __func__); + return PTR_ERR(arm_axi_clk); + } + + ddr_clk = clk_get(NULL, "ddr_clk"); + if (IS_ERR(ddr_clk)) { + printk(KERN_ERR "%s: failed to get ddr_clk\n", + __func__); + return PTR_ERR(ddr_clk); + } + + ipu_clk = clk_get(NULL, "ipu_clk"); + if (IS_ERR(ipu_clk)) { + printk(KERN_ERR "%s: failed to get ipu_clk\n", + __func__); + return PTR_ERR(ipu_clk); + } + + vpu_clk = clk_get(NULL, "vpu_clk"); + if (IS_ERR(vpu_clk)) { + printk(KERN_ERR "%s: failed to get vpu_clk\n", + __func__); + return PTR_ERR(vpu_clk); + } + + periph_apm_clk = clk_get(NULL, "periph_apm_clk"); + if (IS_ERR(periph_apm_clk)) { + printk(KERN_ERR "%s: failed to get periph_apm_clk\n", + __func__); + return PTR_ERR(periph_apm_clk); + } + + lp_apm = clk_get(NULL, "lp_apm"); + if (IS_ERR(lp_apm)) { + printk(KERN_ERR "%s: failed to get lp_apm\n", __func__); + return PTR_ERR(lp_apm); + } + + osc = clk_get(NULL, "osc"); + if (IS_ERR(osc)) { + printk(KERN_ERR "%s: failed to get osc\n", __func__); + return PTR_ERR(osc); + } + } + + gp_regulator = regulator_get(NULL, gp_reg_id); + if (IS_ERR(gp_regulator)) { + clk_put(cpu_clk); + printk(KERN_ERR "%s: failed to get gp regulator\n", __func__); + return PTR_ERR(gp_regulator); + } + + lp_regulator = regulator_get(NULL, lp_reg_id); + if (IS_ERR(lp_regulator)) { + clk_put(ahb_clk); + printk(KERN_ERR "%s: failed to get lp regulator\n", __func__); + return PTR_ERR(lp_regulator); + } + + /* Set the current working point. */ + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + + cpu_freq_khz_min = cpu_wp_tbl[0].cpu_rate / 1000; + cpu_freq_khz_max = cpu_wp_tbl[0].cpu_rate / 1000; + + for (i = 0; i < cpu_wp_nr; i++) { + imx_freq_table[cpu_wp_nr - 1 - i].index = cpu_wp_nr - i; + imx_freq_table[cpu_wp_nr - 1 - i].frequency = + cpu_wp_tbl[i].cpu_rate / 1000; + + if ((cpu_wp_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min) + cpu_freq_khz_min = cpu_wp_tbl[i].cpu_rate / 1000; + + if ((cpu_wp_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max) + cpu_freq_khz_max = cpu_wp_tbl[i].cpu_rate / 1000; + } + + imx_freq_table[i].index = i + 1; + imx_freq_table[i].frequency = cpu_wp_tbl[i].cpu_rate / 1000; + + if ((cpu_wp_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min) + cpu_freq_khz_min = cpu_wp_tbl[i].cpu_rate / 1000; + + if ((cpu_wp_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max) + cpu_freq_khz_max = cpu_wp_tbl[i].cpu_rate / 1000; + + imx_freq_table[i].index = 0; + imx_freq_table[i].frequency = CPUFREQ_TABLE_END; + + policy->cur = policy->min = policy->max = clk_get_rate(cpu_clk) / 1000; + policy->governor = CPUFREQ_DEFAULT_GOVERNOR; + policy->cpuinfo.min_freq = cpu_freq_khz_min; + policy->cpuinfo.max_freq = cpu_freq_khz_max; + + arm_lpm_clk = cpu_freq_khz_min * 1000; + arm_normal_clk = cpu_freq_khz_max * 1000; + + /* Manual states, that PLL stabilizes in two CLK32 periods */ + policy->cpuinfo.transition_latency = 10; + + ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table); + if (ret < 0) { + clk_put(cpu_clk); + if (axi_c_clk_support != 0) { + clk_put(main_bus_clk); + clk_put(pll2); + clk_put(axi_a_clk); + clk_put(axi_b_clk); + clk_put(axi_c_clk); + clk_put(emi_core_clk); + clk_put(nfc_clk); + clk_put(ahb_clk); + clk_put(vpu_core_clk); + clk_put(arm_axi_clk); + clk_put(ddr_clk); + clk_put(ipu_clk); + clk_put(vpu_clk); + clk_put(periph_apm_clk); + clk_put(lp_apm); + clk_put(osc); + } + + regulator_put(gp_regulator, NULL); + regulator_put(lp_regulator, NULL); + printk(KERN_ERR "%s: failed to register i.MXC CPUfreq\n", + __func__); + return ret; + } + cpufreq_frequency_table_get_attr(imx_freq_table, policy->cpu); + + low_bus_freq_mode = 0; + high_bus_freq_mode = 0; + return 0; +} + +static int mxc_cpufreq_driver_exit(struct cpufreq_policy *policy) +{ + cpufreq_frequency_table_put_attr(policy->cpu); + + /* Reset CPU to 665MHz */ + if (!dvfs_core_is_active) + set_cpu_freq(arm_normal_clk); + + if (low_bus_freq_mode) + set_high_bus_freq(); + + clk_put(cpu_clk); + if (axi_c_clk_support != 0) { + clk_put(main_bus_clk); + clk_put(pll2); + clk_put(axi_a_clk); + clk_put(axi_b_clk); + clk_put(axi_c_clk); + clk_put(emi_core_clk); + clk_put(nfc_clk); + clk_put(ahb_clk); + clk_put(vpu_core_clk); + clk_put(arm_axi_clk); + clk_put(ddr_clk); + clk_put(ipu_clk); + clk_put(periph_apm_clk); + clk_put(lp_apm); + clk_put(osc); + } + regulator_put(gp_regulator, NULL); + regulator_put(lp_regulator, NULL); + return 0; +} + +static struct cpufreq_driver mxc_driver = { + .flags = CPUFREQ_STICKY, + .verify = mxc_verify_speed, + .target = mxc_set_target, + .get = mxc_get_speed, + .init = mxc_cpufreq_driver_init, + .exit = mxc_cpufreq_driver_exit, + .name = "imx", +}; + +static int __devinit mxc_cpufreq_init(void) +{ + return cpufreq_register_driver(&mxc_driver); +} + +static void mxc_cpufreq_exit(void) +{ + cpufreq_unregister_driver(&mxc_driver); +} + +module_init(mxc_cpufreq_init); +module_exit(mxc_cpufreq_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("CPUfreq driver for i.MX"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/plat-mxc/dma_mx2.c linux-2.6.26-lab126/arch/arm/plat-mxc/dma_mx2.c --- linux-2.6.26/arch/arm/plat-mxc/dma_mx2.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/dma_mx2.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,1316 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* Front-end to the DMA handling. This handles the allocation/freeing + * of DMA channels, and provides a unified interface to the machines + * DMA facilities. + */ + +/*! + * @file plat-mxc/dma_mx2.c + * @brief This file contains functions for DMA API + * + * @ingroup DMA_MX27 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include + +/* commented temperily for mx27 compilation +#define DMA_PM +*/ +#ifdef DMA_PM +#include +#include +struct apmc_user *dma_apmc_user; +struct pm_dev *dma_pm; +#define DMA_PMST_RESUME 0 +#define DMA_PMST_STANDBY 1 +#define DMA_PMST_SUSPEND 2 +static unsigned int dma_pm_status = DMA_PMST_RESUME; +#endif + +/*! + * This variable is used to controll the clock of DMA. + * It counts the number of actived channels + */ +static atomic_t g_dma_actived = ATOMIC_INIT(0); + +/*! + * This variable point a proc file which contains the information + * of DMA channels + */ +static struct proc_dir_entry *g_proc_dir; + +/*! + * The dma channels + */ +static mxc_dma_channel_t g_dma_channels[MAX_DMA_CHANNELS]; +static mx2_dma_priv_t g_dma_privates[MXC_DMA_CHANNELS]; +static mx2_dma_bd_t g_dma_bd_table[MXC_DMA_CHANNELS][MAX_BD_SIZE]; + +static DEFINE_SPINLOCK(dma_list_lock); + +static struct clk *dma_clk; + +/*!@brief flush buffer descriptor ring*/ +#define flush_dma_bd(private) \ + { \ + atomic_set(&(private->bd_used), 0); \ + private->bd_rd = private->bd_wr;\ + } + +/*!@brief get next buffer discriptor */ +#define next_dma_bd(private) \ + ({ \ + int bd_next = (private->bd_rd+1)%MAX_BD_SIZE; \ + (bd_next == private->bd_wr) ? NULL: private->bd_ring+bd_next;\ + }) + +static inline int consume_dma_bd(mxc_dma_channel_t * dma, int error); +/*! + *@brief allocate a dma channel. + * + *@param idx Requested channel NO. + * @li MXC_INVLAID_CHANNEL System allocates a free channel which is not statically allocated. + * @li Others User requests a specific channel + *@return @li MXC_INVLAID_CHANNEL Failure + * @li Others Success + */ +static inline int get_dma_channel(int idx) +{ + int i; + mxc_dma_channel_t *p; + + if ((idx >= MAX_DMA_CHANNELS) && (idx != MXC_DMA_DYNAMIC_CHANNEL)) { + return -1; + } + if (idx != MXC_DMA_DYNAMIC_CHANNEL) { + p = g_dma_channels + idx; + BUG_ON(p->dynamic != 0); + if (xchg(&p->lock, 1) != 0) { + return -1; + } + return idx; + } + + p = g_dma_channels; + for (i = 0; (i < MAX_DMA_CHANNELS); i++, p++) { + if (p->dynamic && (xchg(&p->lock, 1) == 0)) { + return i; + } + } + return -1; +} + +/*! + *@brief release a dma channel. + * + *@param idx channel number + *@return none; + */ +static inline void put_dma_channel(int idx) +{ + mxc_dma_channel_t *p; + + if ((idx < MAX_DMA_CHANNELS) && (idx >= 0)) { + p = g_dma_channels + idx; + (void)xchg(&p->lock, 0); + } +} + +/*! + *@brief Get dma list for /proc/dma + */ +static int mxc_get_dma_list(char *buf) +{ + mxc_dma_channel_t *dma; + char *p = buf; + int i; + + for (i = 0, dma = g_dma_channels; i < MAX_DMA_CHANNELS; i++, dma++) { + if (dma->lock) { + p += sprintf(p, "dma channel %2d: %s\n", i, + dma->dev_name ? dma->dev_name : "unknown"); + } else { + p += sprintf(p, "dma channel %2d: unused\n", i); + } + } + + return p - buf; +} + +/*!@brief save the mask of dma interrupts*/ +#define save_dma_interrupt(flags) \ + flags = __raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_DIMR) + +/*!@brief restore the mask of dma interrupts*/ +#define restore_dma_interrupt(flags) \ + __raw_writel(flags, IO_ADDRESS(DMA_BASE_ADDR) + DMA_DIMR) + +/*!@brief disable interrupt of dma channel*/ +static inline void mask_dma_interrupt(int channel) +{ + unsigned long reg; + save_dma_interrupt(reg); + reg |= 1 << channel; /*mask interrupt; */ + restore_dma_interrupt(reg); +} + +/*!@brief enable interrupt of dma channel */ +static inline void unmask_dma_interrupt(int channel) +{ + unsigned long reg; + save_dma_interrupt(reg); + reg &= ~(1 << channel); /*unmask interrupt; */ + restore_dma_interrupt(reg); +} + +/*!@brief get interrupt event of dma channel */ +static unsigned long inline __get_dma_interrupt(int channel) +{ + unsigned long mode; + mode = 0; + if (__raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_DISR) & (1 << channel)) + mode |= DMA_DONE; + + if (__raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_DBTOSR) & + (1 << channel)) + mode |= DMA_BURST_TIMEOUT; + if (__raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_DSESR) & (1 << channel)) + mode |= DMA_TRANSFER_ERROR; + + if (__raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_DBOSR) & (1 << channel)) + mode |= DMA_BUFFER_OVERFLOW; + if (__raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_DRTOSR) & + (1 << channel)) + mode |= DMA_REQUEST_TIMEOUT; + return mode; +} + +/*! + *@brief clean all event of dma interrupt and return the valid event. + */ +static unsigned long inline __clear_dma_interrupt(int channel) +{ + unsigned long mode; + mode = __get_dma_interrupt(channel); + __raw_writel(1 << channel, IO_ADDRESS(DMA_BASE_ADDR) + DMA_DISR); + __raw_writel(1 << channel, IO_ADDRESS(DMA_BASE_ADDR) + DMA_DBTOSR); + __raw_writel(1 << channel, IO_ADDRESS(DMA_BASE_ADDR) + DMA_DRTOSR); + __raw_writel(1 << channel, IO_ADDRESS(DMA_BASE_ADDR) + DMA_DSESR); + __raw_writel(1 << channel, IO_ADDRESS(DMA_BASE_ADDR) + DMA_DBOSR); + + return mode; +} + +/*!@brief This function enables dma clocks without lock */ +static void inline __enable_dma_clk(void) +{ + unsigned long reg; + clk_enable(dma_clk); + reg = __raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_DCR); + reg |= 0x1; + __raw_writel(reg, IO_ADDRESS(DMA_BASE_ADDR) + DMA_DCR); +} + +/*!@brief This function disables dma clocks without lock */ +static void inline __disable_dma_clk(void) +{ + unsigned long reg; + reg = __raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_DCR); + reg &= ~0x1; + __raw_writel(reg, IO_ADDRESS(DMA_BASE_ADDR) + DMA_DCR); + clk_disable(dma_clk); +} + +/*!@brief This function enables dma clocks with lock */ +static void inline enable_dma_clk(void) +{ + unsigned long flags; + spin_lock_irqsave(&dma_list_lock, flags); + if (atomic_read(&g_dma_actived) == 0) { + __enable_dma_clk(); + } + spin_unlock_irqrestore(&dma_list_lock, flags); + return; +} + +/*!@brief This function disables dma clocks without locked */ +static void inline disable_dma_clk(void) +{ + unsigned long flags; + spin_lock_irqsave(&dma_list_lock, flags); + if (atomic_read(&g_dma_actived) == 0) { + __disable_dma_clk(); + } + spin_unlock_irqrestore(&dma_list_lock, flags); + return; +} + +/*!@brief select a buffer to transfer and + * setup dma channel for current transfer + */ +static void setup_dmac(mxc_dma_channel_t * dma) +{ + mx2_dma_priv_t *priv = (mx2_dma_priv_t *) dma->private; + dma_regs_t *dma_base = (dma_regs_t *) (priv->dma_base); + mx2_dma_bd_t *p, *q; + unsigned long ctrl_val; + + if (dma->active == 0) { + printk(KERN_ERR + "dma channel %d is not enabled, when receiving this channel 's interrupt\n", + dma->channel); + return; + } + if (atomic_read(&(priv->bd_used)) <= 0) { + printk(KERN_ERR "dma channel %d is empty\n", dma->channel); + dma->active = 0; + atomic_dec(&g_dma_actived); + return; + } + /* BUSY: transfering + * PEND: Wait for set to DMAC. + * s1: no transfering: + * set first(one BUSY). if there are more than one tranfer. set second &repeat is enabled(two BUSY). + * + * s2: transfering & just on transfer + * one BUSY. set the tranesfer and set repeat bit(two BUSY) + * s3: transfering & repeat has set + * has two BUSY. + */ + p = priv->bd_ring + priv->bd_rd; + q = next_dma_bd(priv); + if (!(p->state & DMA_BD_ST_BUSY)) { + /*NOTICE:: This is first buffer or dma chain does not support chain-buffer. So CEN must clear & set again */ + ctrl_val = + __raw_readl(&(dma_base->Ctl)) & + (~(DMA_CTL_ACRPT | DMA_CTL_RPT | DMA_CTL_CEN)); + __raw_writel(ctrl_val, &(dma_base->Ctl)); + if (p->mode != dma->mode) { + dma->mode = p->mode; /* bi-dir channel do mode change */ + if (dma->mode == MXC_DMA_MODE_READ) { + DMA_CTL_SET_SMOD(ctrl_val, + priv->dma_info->sourceType); + DMA_CTL_SET_SSIZ(ctrl_val, + priv->dma_info->sourcePort); + DMA_CTL_SET_DMOD(ctrl_val, + priv->dma_info->destType); + DMA_CTL_SET_DSIZ(ctrl_val, + priv->dma_info->destPort); + } else { + DMA_CTL_SET_SMOD(ctrl_val, + priv->dma_info->destType); + DMA_CTL_SET_SSIZ(ctrl_val, + priv->dma_info->destPort); + DMA_CTL_SET_DMOD(ctrl_val, + priv->dma_info->sourceType); + DMA_CTL_SET_DSIZ(ctrl_val, + priv->dma_info->sourcePort); + } + } + __raw_writel(p->src_addr, &(dma_base->SourceAddr)); + __raw_writel(p->dst_addr, &(dma_base->DestAddr)); + __raw_writel(p->count, &(dma_base->Count)); + p->state |= DMA_BD_ST_BUSY; + p->state &= ~(DMA_BD_ST_PEND); + ctrl_val |= DMA_CTL_CEN; + __raw_writel(ctrl_val, &(dma_base->Ctl)); + if (q && priv->dma_chaining) { /*DO chain-buffer */ + __raw_writel(q->src_addr, &(dma_base->SourceAddr)); + __raw_writel(q->dst_addr, &(dma_base->DestAddr)); + __raw_writel(q->count, &(dma_base->Count)); + q->state |= DMA_BD_ST_BUSY; + q->state &= ~(DMA_BD_ST_PEND); + ctrl_val |= DMA_CTL_ACRPT | DMA_CTL_RPT | DMA_CTL_CEN; + __raw_writel(ctrl_val, &(dma_base->Ctl)); + } + } else { /* Just dma channel which supports dma buffer can run to there */ + BUG_ON(!priv->dma_chaining); + if (q) { /* p is tranfering, then q must be set into dma controller */ + /*WARNING:: [1] dangerous area begin. + * If the p is completed during MCU run in this erea, the dma channel is crashed. + */ + __raw_writel(q->src_addr, &(dma_base->SourceAddr)); + __raw_writel(q->dst_addr, &(dma_base->DestAddr)); + __raw_writel(q->count, &(dma_base->Count)); + /*WARNING:: [2] dangerous area end */ + ctrl_val = + __raw_readl(&(dma_base->Ctl)) | (DMA_CTL_ACRPT | + DMA_CTL_RPT | + DMA_CTL_CEN); + __raw_writel(ctrl_val, &(dma_base->Ctl)); + + /* WARNING:: This is workaround and it is dangerous: + * the judgement is not safety. + */ + if (!__get_dma_interrupt(dma->channel)) { + q->state |= DMA_BD_ST_BUSY; + q->state &= ~(DMA_BD_ST_PEND); + } else { + /*Waiting re-enable is in ISR */ + printk(KERN_ERR + "Warning:: The privous transfer is completed. Maybe the chain buffer is stopped."); + } + } else { /* Last buffer is transfering: just clear RPT bit */ + ctrl_val = + __raw_readl(&(dma_base->Ctl)) & + (~(DMA_CTL_ACRPT | DMA_CTL_RPT)); + __raw_writel(ctrl_val, &(dma_base->Ctl)); + } + } +} + +/*! + * @brief interrupt handler of dma channel + */ +static irqreturn_t dma_irq_handler(int irq, void *dev_id) +{ + mxc_dma_channel_t *dma = (mxc_dma_channel_t *) dev_id; + mx2_dma_priv_t *priv = (mx2_dma_priv_t *) (dma ? dma->private : NULL); + dma_regs_t *dma_base; + int state, error = MXC_DMA_DONE; + + BUG_ON(priv == NULL); + + dma_base = (dma_regs_t *) priv->dma_base; + + state = __clear_dma_interrupt(dma->channel); + + priv->trans_bytes += dma_base->transferd; + if (state != DMA_DONE) { + if (state & DMA_REQUEST_TIMEOUT) { + error = MXC_DMA_REQUEST_TIMEOUT; + } else { + error = MXC_DMA_TRANSFER_ERROR; + } + } + if (consume_dma_bd(dma, error)) { + disable_dma_clk(); + if (dma->cb_fn) { + dma->cb_fn(dma->cb_args, error, priv->trans_bytes); + } + priv->trans_bytes = 0; + } else { + disable_dma_clk(); + } + return IRQ_HANDLED; +} + +/*! + *@brief Set DMA channel parameters + * + *@param dma Requested channel NO. + *@param dma_info Channel configuration + *@return @li 0 Success + * @li others Failure + */ +static int setup_dma_channel(mxc_dma_channel_t * dma, mx2_dma_info_t * dma_info) +{ + mx2_dma_priv_t *priv = (mx2_dma_priv_t *) (dma ? dma->private : NULL); + dma_regs_t *dma_base; + unsigned long reg; + + if (!dma_info || !priv) { + return -1; + } + + if (dma_info->sourceType > 3) { + return -1; + } + if (dma_info->destType > 3) { + return -1; + } + if (dma_info->destPort > 3) { + return -1; + } + if (dma_info->sourcePort > 3) { + return -1; + } + if (dma_info->M2D_Valid) { + /*add for second dma */ + if (dma_info->W < dma_info->X) { + return -1; + } + } + + priv->dma_chaining = dma_info->dma_chaining; + priv->ren = dma_info->ren; + + if (dma_info->sourceType != DMA_TYPE_FIFO + && dma_info->destType != DMA_TYPE_FIFO) { + if (dma_info->ren) { + printk(KERN_INFO + "Warning:request enable just affect source or destination port is FIFO !\n"); + priv->ren = 0; + } + } + + if (dma_info->M2D_Valid) { + if (dma_info->msel) { + __raw_writel(dma_info->W, + IO_ADDRESS(DMA_BASE_ADDR) + DMA_WSRB); + __raw_writel(dma_info->X, + IO_ADDRESS(DMA_BASE_ADDR) + DMA_XSRB); + __raw_writel(dma_info->Y, + IO_ADDRESS(DMA_BASE_ADDR) + DMA_YSRB); + + } else { + __raw_writel(dma_info->W, + IO_ADDRESS(DMA_BASE_ADDR) + DMA_WSRA); + __raw_writel(dma_info->X, + IO_ADDRESS(DMA_BASE_ADDR) + DMA_XSRA); + __raw_writel(dma_info->Y, + IO_ADDRESS(DMA_BASE_ADDR) + DMA_YSRA); + } + } + + dma_base = (dma_regs_t *) (priv->dma_base); + + __raw_writel(dma_info->burstLength, &(dma_base->BurstLength)); + __raw_writel(dma_info->request, &(dma_base->RequestSource)); + + if (dma_info->ren) { + reg = dma_info->busuntils & 0x1FFFF; + if (dma_info->rto_en) { + reg |= 0xE000; + } + __raw_writel(reg, &(dma_base->BusUtilt)); + } else { + __raw_writel(dma_info->busuntils, &(dma_base->BusUtilt)); + } + + reg = __raw_readl(&(dma_base->Ctl)) & (~(DMA_CTL_ACRPT | DMA_CTL_RPT)); + + if (dma_info->dir) { + reg |= DMA_CTL_MDIR; + } else { + reg &= ~DMA_CTL_MDIR; + } + + if (priv->ren) { + reg |= DMA_CTL_REN; + } else { + reg &= ~DMA_CTL_REN; + } + + if ((dma_info->M2D_Valid) && (dma_info->msel)) { + reg |= DMA_CTL_MSEL; + } else { + reg &= ~DMA_CTL_MSEL; + } + + if (dma_info->mode) { + DMA_CTL_SET_SMOD(reg, dma_info->destType); + DMA_CTL_SET_SSIZ(reg, dma_info->destPort); + DMA_CTL_SET_DMOD(reg, dma_info->sourceType); + DMA_CTL_SET_DSIZ(reg, dma_info->sourcePort); + } else { + DMA_CTL_SET_SMOD(reg, dma_info->sourceType); + DMA_CTL_SET_SSIZ(reg, dma_info->sourcePort); + DMA_CTL_SET_DMOD(reg, dma_info->destType); + DMA_CTL_SET_DSIZ(reg, dma_info->destPort); + } + + __raw_writel(reg, &(dma_base->Ctl)); + + __clear_dma_interrupt(dma->channel); + unmask_dma_interrupt(dma->channel); + + disable_dma_clk(); + return 0; +} + +/*!@brief setup interrupt and setup dma channel by dma parameter */ +static inline int __init_dma_channel(mxc_dma_channel_t * chan, + mx2_dma_info_t * dma_info) +{ + mx2_dma_priv_t *dma_private = (mx2_dma_priv_t *) chan->private; + dma_regs_t *dma_base; + int ret; + + mask_dma_interrupt(chan->channel); + ret = + request_irq(dma_private->dma_irq, dma_irq_handler, + IRQF_DISABLED | IRQF_SHARED, chan->dev_name, + (void *)chan); + if (ret) { + printk(KERN_ERR + "%s: unable to request IRQ %d for DMA channel\n", + chan->dev_name, dma_private->dma_irq); + return ret; + } + + enable_dma_clk(); + + dma_base = (dma_regs_t *) (dma_private->dma_base); + __raw_writel(0, &(dma_base->Ctl)); + + ret = 0; + if ((ret = setup_dma_channel(chan, dma_info))) { + free_irq(dma_private->dma_irq, (void *)chan); + } + disable_dma_clk(); + return 0; +} + +/*!@brief initialize buffer descriptor ring.*/ +static inline void init_dma_bd(mx2_dma_priv_t * private) +{ + int i; + mx2_dma_bd_t *pbd; + private->bd_rd = private->bd_wr = 0; + atomic_set(&(private->bd_used), 0); + for (i = 0, pbd = private->bd_ring; i < MAX_BD_SIZE; i++, pbd++) { + pbd->state = 0; + } +} + +/*!@brief add dma buffer into buffer descriptor ring */ +static inline int fill_dma_bd(mxc_dma_channel_t * dma, + mxc_dma_requestbuf_t * buf, int num, + mxc_dma_mode_t mode) +{ + int i, wr; + unsigned long flags, mask; + mx2_dma_priv_t *priv = dma->private; + mx2_dma_bd_t *p, *q; + + if ((atomic_read(&(priv->bd_used)) + num) > MAX_BD_SIZE) { + return -EBUSY; + } + + for (i = 0; i < num; i++) { + wr = priv->bd_wr; + p = priv->bd_ring + wr; + p->mode = mode; + p->count = buf[i].num_of_bytes; + p->src_addr = buf[i].src_addr; + p->dst_addr = buf[i].dst_addr; + if (i == num - 1) { + p->state = DMA_BD_ST_LAST | DMA_BD_ST_PEND; + } else { + p->state = DMA_BD_ST_PEND; + } + priv->bd_wr = (wr + 1) % MAX_BD_SIZE; + atomic_inc(&(priv->bd_used)); + + if (atomic_read(&(priv->bd_used)) != 2) + continue; + /* Disable interrupt of this channel */ + local_irq_save(flags); + local_irq_disable(); + save_dma_interrupt(mask); + mask_dma_interrupt(dma->channel); + local_irq_restore(flags); + /*TODO :: + * If channel is transfering and supports chain_buffer, + * when the new buffer is 2st buffer , repeat must be enabled + */ + if (priv->dma_chaining && dma->active) { + q = priv->bd_ring + priv->bd_rd; + if (q && (q->state & DMA_BD_ST_BUSY)) { + if (atomic_read(&(priv->bd_used)) == 2) { + setup_dmac(dma); + } + } + } + restore_dma_interrupt(mask); + } + return 0; +} + +/*!@brief add sg-list into buffer descriptor ring */ +static inline int fill_dma_bd_by_sg(mxc_dma_channel_t * dma, + struct scatterlist *sg, int num, + int real_bytes, mxc_dma_mode_t mode) +{ + int i, wr, total_bytes = real_bytes; + unsigned long flags, mask; + mx2_dma_priv_t *priv = dma->private; + mx2_dma_bd_t *p, *q; + if ((atomic_read(&(priv->bd_used)) + num) > MAX_BD_SIZE) { + return -EBUSY; + } + + for (i = 0; i < num && ((real_bytes <= 0) || (total_bytes > 0)); i++) { + wr = priv->bd_wr; + p = priv->bd_ring + wr; + p->mode = mode; + if (real_bytes > 0) { + if (sg[i].length >= total_bytes) { + p->count = total_bytes; + } else { + p->count = sg[i].length; + } + total_bytes -= p->count; + } else { + p->count = sg[i].length; + } + if (mode == MXC_DMA_MODE_READ) { + p->src_addr = priv->dma_info->per_address; + p->dst_addr = sg[i].dma_address; + } else { + p->dst_addr = priv->dma_info->per_address; + p->src_addr = sg[i].dma_address; + } + if ((i == num - 1) || ((real_bytes > 0) && (total_bytes == 0))) { + p->state = DMA_BD_ST_LAST | DMA_BD_ST_PEND; + } else { + p->state = DMA_BD_ST_PEND; + } + priv->bd_wr = (wr + 1) % MAX_BD_SIZE; + atomic_inc(&(priv->bd_used)); + + if (atomic_read(&(priv->bd_used)) != 2) + continue; + /* Disable interrupt of this channel */ + local_irq_save(flags); + local_irq_disable(); + save_dma_interrupt(mask); + mask_dma_interrupt(dma->channel); + local_irq_restore(flags); + /*TODO :: + * If channel is transfering and supports chain_buffer, + * when the new buffer is 2st buffer , repeat must be enabled + */ + if (priv->dma_chaining && dma->active) { + q = next_dma_bd(priv); + if (q && (q->state & DMA_BD_ST_BUSY)) { + if ((atomic_read(&(priv->bd_used))) == 2) { + setup_dmac(dma); + } + } + } + restore_dma_interrupt(mask); + } + return 0; +} + +/*!@brief select next buffer descripter to transfer. + * return 1: need call call-back function. 0: Not need call call-back. + * it just is called in ISR + */ +static inline int consume_dma_bd(mxc_dma_channel_t * dma, int error) +{ + mx2_dma_priv_t *priv = dma->private; + mx2_dma_bd_t *p; + int notify = 0; + if (priv == NULL) { + printk(KERN_ERR + "request dma channel %d which is not initialize completed.!\n", + dma->channel); + return 1; + } + if (error != MXC_DMA_DONE) { + for (p = priv->bd_ring + priv->bd_rd; + atomic_read(&(priv->bd_used)) > 0;) { + priv->bd_rd = (priv->bd_rd + 1) % MAX_BD_SIZE; + atomic_dec(&(priv->bd_used)); + if (p->state & DMA_BD_ST_LAST) { + p->state = 0; + break; + } + p->state = 0; + } + notify = 1; + } else { + p = priv->bd_ring + priv->bd_rd; + priv->bd_rd = (priv->bd_rd + 1) % MAX_BD_SIZE; + atomic_dec(&(priv->bd_used)); + notify = (p->state & DMA_BD_ST_LAST) == DMA_BD_ST_LAST; + } + if (atomic_read(&(priv->bd_used)) <= 0) { + dma->active = 0; + atomic_dec(&g_dma_actived); + } else { + setup_dmac(dma); + } + return notify; +} + +/*! + * This function is generally called by the driver at open time. + * The DMA driver would do any initialization steps that is required + * to get the channel ready for data transfer. + * + * @param channel_id a pre-defined id. The peripheral driver would specify + * the id associated with its peripheral. This would be + * used by the DMA driver to identify the peripheral + * requesting DMA and do the necessary setup on the + * channel associated with the particular peripheral. + * The DMA driver could use static or dynamic DMA channel + * allocation. + * @param dev_name module name or device name + * @return returns a negative number on error if request for a DMA channel did not + * succeed, returns the channel number to be used on success. + */ +int mxc_dma_request_ext(mxc_dma_device_t channel_id, char *dev_name, + unsigned long data) +{ + mxc_dma_channel_t *dma; + mx2_dma_priv_t *dma_private = NULL; + mx2_dma_info_t *dma_info = mxc_dma_get_info(channel_id); + int index; + int ret; + + if (dma_info == NULL) { + return -EINVAL; + } + + if ((index = get_dma_channel(dma_info->dma_chan)) < 0) { + return -ENODEV; + } + + dma = g_dma_channels + index; + dma_private = (mx2_dma_priv_t *) dma->private; + if (dma_private == NULL) { + printk(KERN_ERR + "request dma channel %d which is not initialize completed.!\n", + index); + ret = -EFAULT; + goto exit; + } + + dma->active = 0; + dma_private->dma_info = NULL; + dma->cb_fn = NULL; + dma->cb_args = NULL; + dma->dev_name = dev_name; + dma->mode = dma_info->mode ? MXC_DMA_MODE_WRITE : MXC_DMA_MODE_READ; + init_dma_bd(dma_private); + + if (!(ret = __init_dma_channel(dma, dma_info))) { + dma_private->dma_info = dma_info; + return index; + } + exit: + put_dma_channel(index); + return ret; +} + +/*! + * This function is generally called by the driver at close time. The DMA + * driver would do any cleanup associated with this channel. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @return returns a negative number on error or 0 on success + */ +int mxc_dma_free(int channel_num) +{ + mxc_dma_channel_t *dma; + mx2_dma_priv_t *dma_private; + + if ((channel_num >= MAX_DMA_CHANNELS) || (channel_num < 0)) { + return -EINVAL; + } + + dma = g_dma_channels + channel_num; + dma_private = (mx2_dma_priv_t *) dma->private; + if (dma_private == NULL) { + printk(KERN_ERR + "Free dma %d which is not completed initialization \n", + channel_num); + return -EFAULT; + } + if (dma->lock) { + if (dma->active) { /*Channel is busy */ + mxc_dma_disable(channel_num); + } + + dma_private = (mx2_dma_priv_t *) dma->private; + + enable_dma_clk(); + mask_dma_interrupt(channel_num); + disable_dma_clk(); + + free_irq(dma_private->dma_irq, (void *)dma); + put_dma_channel(channel_num); + } + return 0; +} + +/*! + * This function would just configure the buffers specified by the user into + * dma channel. The caller must call mxc_dma_enable to start this transfer. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @param dma_buf an array of physical addresses to the user defined + * buffers. The caller must guarantee the dma_buf is + * available until the transfer is completed. + * @param num_buf number of buffers in the array + * @param mode specifies whether this is READ or WRITE operation + * @return This function returns a negative number on error if buffer could not be + * added with DMA for transfer. On Success, it returns 0 + */ +int mxc_dma_config(int channel_num, mxc_dma_requestbuf_t * dma_buf, int num_buf, + mxc_dma_mode_t mode) +{ + mxc_dma_channel_t *dma; + mx2_dma_priv_t *dma_private; + + if ((dma_buf == NULL) || (num_buf < 1)) { + return -EINVAL; + } + + if ((channel_num >= MAX_DMA_CHANNELS) || (channel_num < 0)) { + return -EINVAL; + } + + dma = g_dma_channels + channel_num; + dma_private = (mx2_dma_priv_t *) dma->private; + if (dma_private == NULL) { + printk(KERN_ERR + "config dma %d which is not completed initialization \n", + channel_num); + return -EFAULT; + } + + if (dma->lock == 0) { + return -ENODEV; + } + + /*TODO: dma chainning can not support on bi-dir channel */ + if (dma_private->dma_chaining && (dma->mode != mode)) { + return -EINVAL; + } + + /*TODO: fill dma buffer into driver . + * If driver is no enought buffer to save them , it will return -EBUSY + */ + if (fill_dma_bd(dma, dma_buf, num_buf, mode)) { + return -EBUSY; + } + + return 0; +} + +/*! + * This function would just configure the scatterlist specified by the + * user into dma channel. This is a slight variation of mxc_dma_config(), + * it is provided for the convenience of drivers that have a scatterlist + * passed into them. It is the calling driver's responsibility to have the + * correct physical address filled in the "dma_address" field of the + * scatterlist. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @param sg a scatterlist of buffers. The caller must guarantee + * the dma_buf is available until the transfer is + * completed. + * @param num_buf number of buffers in the array + * @param num_of_bytes total number of bytes to transfer. If set to 0, this + * would imply to use the length field of the scatterlist + * for each DMA transfer. Else it would calculate the size + * for each DMA transfer. + * @param mode specifies whether this is READ or WRITE operation + * @return This function returns a negative number on error if buffer could not + * be added with DMA for transfer. On Success, it returns 0 + */ +int mxc_dma_sg_config(int channel_num, struct scatterlist *sg, + int num_buf, int num_of_bytes, mxc_dma_mode_t mode) +{ + mxc_dma_channel_t *dma; + mx2_dma_priv_t *dma_private; + + if ((sg == NULL) || (num_buf < 1) || (num_of_bytes < 0)) { + return -EINVAL; + } + + if ((channel_num >= MAX_DMA_CHANNELS) || (channel_num < 0)) { + return -EINVAL; + } + + dma = g_dma_channels + channel_num; + dma_private = (mx2_dma_priv_t *) dma->private; + if (dma_private == NULL) { + printk(KERN_ERR + "config_sg dma %d which is not completed initialization \n", + channel_num); + return -EFAULT; + } + + if (dma->lock == 0) { + return -ENODEV; + } + + /*TODO: dma chainning can not support on bi-dir channel */ + if (dma_private->dma_chaining && (dma->mode != mode)) { + return -EINVAL; + } + + /*TODO: fill dma buffer into driver . + * If driver is no enought buffer to save them , it will return -EBUSY + */ + if (fill_dma_bd_by_sg(dma, sg, num_buf, num_of_bytes, mode)) { + return -EBUSY; + } + return 0; +} + +/*! + * This function is provided if the driver would like to set/change its + * callback function. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @param callback a callback function to provide notification on transfer + * completion, user could specify NULL if he does not wish + * to be notified + * @param arg an argument that gets passed in to the callback + * function, used by the user to do any driver specific + * operations. + * @return this function returns an error if the callback could not be set + * for the channel + */ +int mxc_dma_callback_set(int channel_num, mxc_dma_callback_t callback, + void *arg) +{ + mxc_dma_channel_t *dma; + + if ((channel_num >= MAX_DMA_CHANNELS) || (channel_num < 0)) { + return -EINVAL; + } + dma = g_dma_channels + channel_num; + + if (!dma->lock) { + return -ENODEV; + } + + if (dma->active) { + return -EBUSY; + } + dma->cb_fn = callback; + dma->cb_args = arg; + return 0; + +} + +/*! + * This stops the DMA channel and any ongoing transfers. Subsequent use of + * mxc_dma_enable() will restart the channel and restart the transfer. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @return returns a negative number on error or 0 on success + */ +int mxc_dma_disable(int channel_num) +{ + mxc_dma_channel_t *dma; + mx2_dma_priv_t *priv; + unsigned long ctrl_val; + + if ((channel_num >= MAX_DMA_CHANNELS) || (channel_num < 0)) { + return -EINVAL; + } + + dma = g_dma_channels + channel_num; + + if (dma->lock == 0) { + return -EINVAL; + } + + if (!dma->active) { + return -EINVAL; + } + + priv = (mx2_dma_priv_t *) dma->private; + if (priv == NULL) { + printk(KERN_ERR "disable a uncompleted dma channel %d\n", + channel_num); + return -EFAULT; + } + + dma->active = 0; + enable_dma_clk(); + + __clear_dma_interrupt(channel_num); + ctrl_val = + __raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_CCR(channel_num)); + ctrl_val &= ~DMA_CTL_CEN; /* clear CEN bit */ + __raw_writel(ctrl_val, + IO_ADDRESS(DMA_BASE_ADDR) + DMA_CCR(channel_num)); + disable_dma_clk(); + atomic_dec(&g_dma_actived); + + /*TODO: Clear all request buffers */ + flush_dma_bd(priv); + return 0; +} + +/*! + * This starts DMA transfer. Or it restarts DMA on a stopped channel + * previously stopped with mxc_dma_disable(). + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @return returns a negative number on error or 0 on success + */ +int mxc_dma_enable(int channel_num) +{ + mxc_dma_channel_t *dma; + mx2_dma_priv_t *priv; + + if ((channel_num >= MAX_DMA_CHANNELS) || (channel_num < 0)) { + return -EINVAL; + } + + dma = g_dma_channels + channel_num; + + if (dma->lock == 0) { + return -EINVAL; + } + + priv = (mx2_dma_priv_t *) dma->private; + if (priv == NULL) { + printk(KERN_ERR "enable a uncompleted dma channel %d\n", + channel_num); + return -EFAULT; + } + + if (dma->active) { + return 0; + } + dma->active = 1; + priv->trans_bytes = 0; + + enable_dma_clk(); + + atomic_inc(&g_dma_actived); + __clear_dma_interrupt(channel_num); + + setup_dmac(dma); + disable_dma_clk(); + return 0; +} + +/*! +*@brief Dump DMA registers +* +*@param channel Requested channel NO. +*@return none +*/ + +void mxc_dump_dma_register(int channel) +{ + mxc_dma_channel_t *dma = &g_dma_channels[channel]; + mx2_dma_priv_t *priv = (mx2_dma_priv_t *) dma->private; + dma_regs_t *dma_base; + + printk(KERN_INFO "======== Dump dma channel %d \n", channel); + if ((unsigned)channel >= MXC_DMA_CHANNELS) { + printk(KERN_INFO "Channel number is invalid \n"); + return; + } + if (!dma->lock) { + printk(KERN_INFO "Channel is not allocated \n"); + return; + } + + printk(KERN_INFO "g_dma_actived = %d\n", atomic_read(&g_dma_actived)); + + enable_dma_clk(); + dma_base = (dma_regs_t *) (priv->dma_base); + printk(KERN_INFO "DMA COMMON REGISTER\n"); + printk(KERN_INFO "DMA CONTROL DMA_DCR: %08x\n", + __raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_DCR)); + printk(KERN_INFO "DMA Interrupt status DMA_DISR: %08x\n", + __raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_DISR)); + printk(KERN_INFO "DMA Interrupt Mask DMA_DIMR: %08x\n", + __raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_DIMR)); + printk(KERN_INFO "DMA Burst Time Out DMA_DBTOSR: %08x\n", + __raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_DBTOSR)); + printk(KERN_INFO "DMA request Time Out DMA_DRTOSR: %08x\n", + __raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_DRTOSR)); + printk(KERN_INFO "DMA Transfer Error DMA_DSESR: %08x\n", + __raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_DSESR)); + printk(KERN_INFO "DMA DMA_Overflow DMA_DBOSR: %08x\n", + __raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_DBOSR)); + printk(KERN_INFO "DMA Burst Time OutCtl DMA_BurstTOCtl: %08x\n", + __raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_DBTOCR)); + + printk(KERN_INFO "DMA 2D X size: %08x\n", + __raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_XSRA)); + printk(KERN_INFO "DMA 2D Y size: %08x\n", + __raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_YSRA)); + printk(KERN_INFO "DMA 2D Z size: %08x\n", + __raw_readl(IO_ADDRESS(DMA_BASE_ADDR) + DMA_WSRA)); + + printk(KERN_INFO "DMA Chan %2d Sourc SourceAddr: %08x\n", channel, + __raw_readl(&(dma_base->SourceAddr))); + printk(KERN_INFO "DMA Chan %2d dest DestAddr: %08x\n", channel, + __raw_readl(&(dma_base->DestAddr))); + printk(KERN_INFO "DMA Chan %2d count Count: %08x\n", channel, + __raw_readl(&(dma_base->Count))); + printk(KERN_INFO "DMA Chan %2d Ctl Ctl: %08x\n", channel, + __raw_readl(&(dma_base->Ctl))); + printk(KERN_INFO "DMA Chan %2d request RequestSource: %08x\n", + channel, __raw_readl(&(dma_base->RequestSource))); + printk(KERN_INFO "DMA Chan %2d burstL BurstLength: %08x\n", channel, + __raw_readl(&(dma_base->BurstLength))); + printk(KERN_INFO "DMA Chan %2d requestTO ReqTimeout: %08x\n", channel, + __raw_readl(&(dma_base->ReqTimeout))); + printk(KERN_INFO "DMA Chan %2d BusUtilt BusUtilt: %08x\n", channel, + __raw_readl(&(dma_base->BusUtilt))); + + disable_dma_clk(); +} + +#ifdef DMA_PM + +static int channel_in_use(void) +{ + int i; + for (i = 0; i < MXC_DMA_CHANNELS; i++) { + if (dma_chan[i].lock) + return 1; + } + return 0; +} + +int mxc_dma_pm_standby(void) +{ + unsigned long reg; + if (dma_pm_status == DMA_PMST_STANDBY) + return 0; + + if (!channel_in_use()) { + /*Disable DMA */ + __disable_dma_clk(); + dma_pm_status = DMA_PMST_STANDBY; + return 0; + } + return -1; +} + +int mxc_dma_pm_resume(void) +{ + unsigned long reg; + if (dma_pm_status == DMA_PMST_RESUME) + return 0; + + /*Enable HCLK_DMA and DMA(ipg clock) */ + dma_pm_status = DMA_PMST_RESUME; + return 0; +} + +int mxc_dma_pm_suspend(void) +{ + unsigned long reg; + if (dma_pm_status == DMA_PMST_SUSPEND) + return 0; + + if (!channel_in_use()) { + /*Disable DMA */ + __disable_dma_clk(); + dma_pm_status = DMA_PMST_SUSPEND; + return 0; + } + return -1; +} + +int mxc_dma_pm_handler(struct pm_dev *dev, pm_request_t rqst, void *data) +{ + int ret = 0; + switch (rqst) { + /*APM doesn't send PM_STANDBY and PM_STANDBY_RESUME request now. */ + case PM_SUSPEND: + ret = dma_pm_suspend(); + break; + case PM_RESUME: + ret = dma_pm_resume(); + break; + } + return ret; +} + +#endif /*DMA_PM */ + +int __init mxc_dma_init(void) +{ + int i; + mxc_dma_channel_t *dma = g_dma_channels; + mx2_dma_priv_t *private = g_dma_privates; + + memset(dma, 0, sizeof(mxc_dma_channel_t) * MXC_DMA_CHANNELS); + for (i = 0; i < MXC_DMA_CHANNELS; i++, dma++, private++) { + dma->channel = i; + dma->private = private; + private->dma_base = + (unsigned int)(IO_ADDRESS(DMA_BASE_ADDR + DMA_CH_BASE(i))); + private->dma_irq = i + MXC_DMA_INTR_0; /*Dma channel interrupt number */ + private->bd_ring = &g_dma_bd_table[i][0]; + } + + mxc_dma_load_info(g_dma_channels); + + dma_clk = clk_get(NULL, "dma_clk"); + clk_enable(dma_clk); + + __raw_writel(0x2, IO_ADDRESS(DMA_BASE_ADDR) + DMA_DCR); /*reset DMA; */ + + disable_dma_clk(); + + /*use module init because create_proc after init_dma */ + g_proc_dir = create_proc_entry("dma", 0, NULL); + g_proc_dir->read_proc = (read_proc_t *) mxc_get_dma_list; + g_proc_dir->data = NULL; + +#ifdef DMA_PM + /* Register the device with power management. */ + dma_pm = pm_register(PM_DMA_DEV, PM_SYS_UNKNOWN, dma_pm_handler); +#endif + + return 0; +} + +arch_initcall(mxc_dma_init); + +EXPORT_SYMBOL(mxc_dma_request_ext); +EXPORT_SYMBOL(mxc_dma_free); +EXPORT_SYMBOL(mxc_dma_callback_set); +EXPORT_SYMBOL(mxc_dma_enable); +EXPORT_SYMBOL(mxc_dma_disable); +EXPORT_SYMBOL(mxc_dma_config); +EXPORT_SYMBOL(mxc_dma_sg_config); +EXPORT_SYMBOL(mxc_dump_dma_register); diff -urN linux-2.6.26/arch/arm/plat-mxc/dptc.c linux-2.6.26-lab126/arch/arm/plat-mxc/dptc.c --- linux-2.6.26/arch/arm/plat-mxc/dptc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/dptc.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,610 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dptc.c + * + * @brief Driver for the Freescale Semiconductor MXC DPTC module. + * + * The DPTC driver is designed to control the MXC DPTC hardware. + * hardware. Upon initialization, the DPTC driver initializes the DPTC hardware + * sets up driver nodes attaches to the DPTC interrupt and initializes internal + * data structures. When the DPTC interrupt occurs the driver checks the cause + * of the interrupt (lower frequency, increase frequency or emergency) and changes + * the CPU voltage according to translation table that is loaded into the driver. + * The driver read method is used to read the log buffer. + * Driver ioctls are used to change driver parameters and enable/disable the + * DVFS operation. + * + * @ingroup PM + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +enum { + DPTC_PTVAI_NOCHANGE = 0x0, + DPTC_PTVAI_DECREASE, + DPTC_PTVAI_INCREASE, + DPTC_PTVAI_EMERG, +}; + +struct device *dev_data0; +struct device *dev_data1; + +/*! + * In case the MXC device has multiple DPTC modules, this structure is used to + * store information specific to each DPTC module. + */ +struct dptc_device { + /* DPTC delayed work */ + struct delayed_work dptc_work; + /* DPTC spinlock */ + spinlock_t lock; + /* DPTC regulator */ + struct regulator *dptc_reg; + /* DPTC clock */ + struct clk *dptc_clk; + /* DPTC is active flag */ + int dptc_is_active; + /* turbo mode active flag */ + int turbo_mode_active; + /* DPTC current working point */ + int curr_wp; + /* DPTC vai bits */ + u32 ptvai; + /* The interrupt number used by the DPTC device */ + int irq; + /* DPTC platform data pointer */ + struct mxc_dptc_data *dptc_platform_data; +}; + +static void update_dptc_wp(struct dptc_device *drv_data, u32 wp) +{ + struct mxc_dptc_data *dptc_data = drv_data->dptc_platform_data; + int voltage_uV; + int ret = 0; + + voltage_uV = mV_to_uV(dptc_data->dptc_wp_allfreq[wp].voltage); + + __raw_writel(dptc_data->dptc_wp_allfreq[wp].dcvr0, + dptc_data->dcvr0_reg_addr); + __raw_writel(dptc_data->dptc_wp_allfreq[wp].dcvr1, + dptc_data->dcvr0_reg_addr + 0x4); + __raw_writel(dptc_data->dptc_wp_allfreq[wp].dcvr2, + dptc_data->dcvr0_reg_addr + 0x8); + __raw_writel(dptc_data->dptc_wp_allfreq[wp].dcvr3, + dptc_data->dcvr0_reg_addr + 0xC); + + /* Set the voltage */ + ret = regulator_set_voltage(drv_data->dptc_reg, voltage_uV); + if (ret < 0) + printk(KERN_DEBUG "COULD NOT SET VOLTAGE!!!!!\n"); + + pr_debug("dcvr0-3: 0x%x, 0x%x, 0x%x, 0x%x; vol: %d\n", + dptc_data->dptc_wp_allfreq[wp].dcvr0, + dptc_data->dptc_wp_allfreq[wp].dcvr1, + dptc_data->dptc_wp_allfreq[wp].dcvr2, + dptc_data->dptc_wp_allfreq[wp].dcvr3, + dptc_data->dptc_wp_allfreq[wp].voltage); +} + +static irqreturn_t dptc_irq(int irq, void *dev_id) +{ + struct device *dev = dev_id; + struct dptc_device *drv_data = dev->driver_data; + struct mxc_dptc_data *dptc_data = dev->platform_data; + u32 dptccr = __raw_readl(dptc_data->dptccr_reg_addr); + u32 gpc_cntr = __raw_readl(dptc_data->gpc_cntr_reg_addr); + + gpc_cntr = (gpc_cntr & dptc_data->dptccr); + + if (gpc_cntr) { + drv_data->ptvai = + (dptccr & dptc_data->vai_mask) >> dptc_data->vai_offset; + pr_debug("dptc_irq: vai = 0x%x (0x%x)!!!!!!!\n", + drv_data->ptvai, dptccr); + + /* disable DPTC and mask its interrupt */ + dptccr = (dptccr & ~(dptc_data->dptc_enable_bit)) | + (dptc_data->irq_mask); + dptccr = (dptccr & ~(dptc_data->dptc_nvcr_bit)); + __raw_writel(dptccr, dptc_data->dptccr_reg_addr); + + if (drv_data->turbo_mode_active == 1) + schedule_delayed_work(&drv_data->dptc_work, 0); + return IRQ_HANDLED; + } + + return IRQ_NONE; +} + +static void dptc_workqueue_handler(struct work_struct *work1) +{ + struct delayed_work *dptc_work_tmp = + container_of(work1, struct delayed_work, work); + struct dptc_device *drv_data = + container_of(dptc_work_tmp, struct dptc_device, dptc_work); + struct mxc_dptc_data *dptc_data = drv_data->dptc_platform_data; + u32 dptccr = __raw_readl(dptc_data->dptccr_reg_addr); + + switch (drv_data->ptvai) { + case DPTC_PTVAI_DECREASE: + drv_data->curr_wp++; + break; + case DPTC_PTVAI_INCREASE: + case DPTC_PTVAI_EMERG: + drv_data->curr_wp--; + if (drv_data->curr_wp < 0) { + /* already max voltage */ + drv_data->curr_wp = 0; + printk(KERN_WARNING "dptc: already maximum voltage\n"); + } + break; + + /* Unknown interrupt cause */ + default: + BUG(); + } + + if (drv_data->curr_wp > dptc_data->dptc_wp_supported + || drv_data->curr_wp < 0) { + panic("Can't support this working point: %d\n", + drv_data->curr_wp); + } + update_dptc_wp(drv_data, drv_data->curr_wp); + + /* Enable DPTC and unmask its interrupt */ + dptccr = (dptccr & ~(dptc_data->irq_mask)) | + dptc_data->dptc_nvcr_bit | dptc_data->dptc_enable_bit; + __raw_writel(dptccr, dptc_data->dptccr_reg_addr); +} + +/* Start DPTC unconditionally */ +static int start_dptc(struct device *dev) +{ + struct mxc_dptc_data *dptc_data = dev->platform_data; + struct dptc_device *drv_data = dev->driver_data; + u32 dptccr, flags; + unsigned long clk_rate; + int voltage_mV; + + /* Get the voltage */ + voltage_mV = uV_to_mV(regulator_get_voltage(drv_data->dptc_reg)); + drv_data->curr_wp = + (dptc_data->dptc_wp_allfreq[0].voltage - voltage_mV) / 25; + + update_dptc_wp(drv_data, drv_data->curr_wp); + + /* Set the voltage */ + spin_lock_irqsave(&drv_data->lock, flags); + + clk_rate = clk_get_rate(drv_data->dptc_clk); + + if (clk_rate < dptc_data->clk_max_val) + goto err; + + if (dptc_data->gpc_irq_bit != 0x0) { + /* Enable ARM domain frequency and/or voltage update needed + and enable ARM IRQ */ + __raw_writel(dptc_data->gpc_irq_bit | dptc_data->gpc_adu, + dptc_data->gpc_cntr_reg_addr); + } + + dptccr = __raw_readl(dptc_data->dptccr_reg_addr); + + /* Enable DPTC and unmask its interrupt */ + dptccr = ((dptccr & ~(dptc_data->irq_mask)) | dptc_data->enable_config); + + __raw_writel(dptccr, dptc_data->dptccr_reg_addr); + + spin_unlock_irqrestore(&drv_data->lock, flags); + + drv_data->dptc_is_active = 1; + drv_data->turbo_mode_active = 1; + + pr_info("DPTC has been started \n"); + + return 0; + +err: + spin_unlock_irqrestore(&drv_data->lock, flags); + pr_info("DPTC is not enabled\n"); + return -1; +} + +/* Stop DPTC unconditionally */ +static void stop_dptc(struct device *dev) +{ + struct mxc_dptc_data *dptc_data = dev->platform_data; + struct dptc_device *drv_data = dev->driver_data; + u32 dptccr; + + dptccr = __raw_readl(dptc_data->dptccr_reg_addr); + + /* disable DPTC and mask its interrupt */ + dptccr = ((dptccr & ~(dptc_data->dptc_enable_bit)) | + dptc_data->irq_mask) & (~dptc_data->dptc_nvcr_bit); + + __raw_writel(dptccr, dptc_data->dptccr_reg_addr); + + /* Restore Turbo Mode voltage to highest wp */ + update_dptc_wp(drv_data, 0); + drv_data->curr_wp = 0; + + regulator_put(drv_data->dptc_reg, NULL); + + pr_info("DPTC has been stopped\n"); +} + +/* + This function does not change the working point. It can be + called from an interrupt context. +*/ +void dptc_suspend(int id) +{ + struct mxc_dptc_data *dptc_data; + struct dptc_device *drv_data; + u32 dptccr; + + switch (id) { + case DPTC_GP_ID: + dptc_data = dev_data0->platform_data; + drv_data = dev_data0->driver_data; + break; + case DPTC_LP_ID: + if (dev_data1 == NULL) + return; + + dptc_data = dev_data1->platform_data; + drv_data = dev_data1->driver_data; + break; + /* Unknown DPTC ID */ + default: + return; + } + + if (!drv_data->dptc_is_active) + return; + + dptccr = __raw_readl(dptc_data->dptccr_reg_addr); + + /* Disable DPTC and mask its interrupt */ + dptccr = (dptccr & ~(dptc_data->dptc_enable_bit)) | dptc_data->irq_mask; + + __raw_writel(dptccr, dptc_data->dptccr_reg_addr); +} +EXPORT_SYMBOL(dptc_suspend); + +/* + This function does not change the working point. It can be + called from an interrupt context. +*/ +void dptc_resume(int id) +{ + struct mxc_dptc_data *dptc_data; + struct dptc_device *drv_data; + u32 dptccr; + + switch (id) { + case DPTC_GP_ID: + dptc_data = dev_data0->platform_data; + drv_data = dev_data0->driver_data; + break; + case DPTC_LP_ID: + if (dev_data1 == NULL) + return; + + dptc_data = dev_data1->platform_data; + drv_data = dev_data1->driver_data; + break; + /* Unknown DPTC ID */ + default: + return; + } + + if (!drv_data->dptc_is_active) + return; + + __raw_writel(dptc_data->dptc_wp_allfreq[0].dcvr0, + dptc_data->dcvr0_reg_addr); + __raw_writel(dptc_data->dptc_wp_allfreq[0].dcvr1, + dptc_data->dcvr0_reg_addr + 0x4); + __raw_writel(dptc_data->dptc_wp_allfreq[0].dcvr2, + dptc_data->dcvr0_reg_addr + 0x8); + __raw_writel(dptc_data->dptc_wp_allfreq[0].dcvr3, + dptc_data->dcvr0_reg_addr + 0xC); + + dptccr = __raw_readl(dptc_data->dptccr_reg_addr); + + /* Enable DPTC and unmask its interrupt */ + dptccr = (dptccr & ~(dptc_data->irq_mask)) | dptc_data->dptc_enable_bit; + + __raw_writel(dptccr, dptc_data->dptccr_reg_addr); +} +EXPORT_SYMBOL(dptc_resume); + +/*! + * This function is called to put the DPTC in a low power state. + * + */ +void dptc_disable(struct device *dev) +{ + struct dptc_device *drv_data = dev->driver_data; + + if (!(drv_data->dptc_is_active)) + return; + + stop_dptc(dev); + drv_data->dptc_is_active = 0; + drv_data->turbo_mode_active = 0; +} + +/*! + * This function is called to resume the DPTC from a low power state. + * + */ +int dptc_enable(struct device *dev) +{ + struct dptc_device *drv_data = dev->driver_data; + + if (drv_data->dptc_is_active) + return 0; + + return start_dptc(dev); +} + +static ssize_t dptc_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct dptc_device *drv_data = dev->driver_data; + + if (drv_data->dptc_is_active) + return sprintf(buf, "DPTC is enabled\n"); + else + return sprintf(buf, "DPTC is disabled\n"); +} + +static ssize_t dptc_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + if (strstr(buf, "0") != NULL) { + dptc_disable(dev); + } else if (strstr(buf, "1") != NULL) { + dptc_enable(dev); + } + + return size; +} + +static DEVICE_ATTR(enable, 0644, dptc_show, dptc_store); + +/*! + * This is the probe routine for the DPTC driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + * + */ +static int __devinit mxc_dptc_probe(struct platform_device *pdev) +{ + struct dptc_device *dptc_device_data; + int ret = 0; + struct resource *res; + u32 dptccr = 0; + struct clk *ckih_clk; + struct mxc_dptc_data *dptc_data = pdev->dev.platform_data; + + if (dptc_data == NULL) { + printk(KERN_ERR "DPTC: Pointer to DPTC data is NULL\ + not started\n"); + return -1; + } + + dptc_device_data = kzalloc(sizeof(struct dptc_device), GFP_KERNEL); + if (!dptc_device_data) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + ret = -ENODEV; + goto err1; + } + + /* + * Request the DPTC interrupt + */ + dptc_device_data->irq = platform_get_irq(pdev, 0); + if (dptc_device_data->irq < 0) { + ret = dptc_device_data->irq; + goto err1; + } + + ret = + request_irq(dptc_device_data->irq, dptc_irq, IRQF_SHARED, + pdev->name, &pdev->dev); + if (ret) { + printk(KERN_ERR "DPTC: Unable to attach to DPTC interrupt\n"); + goto err1; + } + + dptc_device_data->curr_wp = 0; + dptc_device_data->dptc_is_active = 0; + dptc_device_data->turbo_mode_active = 0; + dptc_device_data->ptvai = 0; + + dptccr = __raw_readl(dptc_data->dptccr_reg_addr); + + printk(KERN_INFO "DPTC mxc_dptc_probe()\n"); + + spin_lock_init(&dptc_device_data->lock); + + if (dptc_data->dptc_wp_allfreq == NULL) { + ckih_clk = clk_get(NULL, "ckih"); + if (cpu_is_mx31() & + (mxc_cpu_is_rev(CHIP_REV_2_0) < 0) & + (clk_get_rate(ckih_clk) == 27000000)) + printk(KERN_ERR "DPTC: DPTC not supported on TO1.x \ + & ckih = 27M\n"); + else + printk(KERN_ERR "DPTC: Pointer to DPTC table is NULL\ + not started\n"); + goto err1; + } + + dptc_device_data->dptc_reg = regulator_get(NULL, dptc_data->reg_id); + if (IS_ERR(dptc_device_data->dptc_reg)) { + clk_put(dptc_device_data->dptc_clk); + printk(KERN_ERR "%s: failed to get regulator\n", __func__); + goto err1; + } + + INIT_DELAYED_WORK(&dptc_device_data->dptc_work, dptc_workqueue_handler); + + /* Enable Reference Circuits */ + dptccr = (dptccr & ~(dptc_data->dcr_mask)) | dptc_data->init_config; + __raw_writel(dptccr, dptc_data->dptccr_reg_addr); + + ret = sysfs_create_file(&pdev->dev.kobj, &dev_attr_enable.attr); + if (ret) { + printk(KERN_ERR + "DPTC: Unable to register sysdev entry for dptc"); + goto err1; + } + + if (ret != 0) { + printk(KERN_ERR "DPTC: Unable to start"); + goto err1; + } + + dptc_device_data->dptc_clk = clk_get(NULL, dptc_data->clk_id); + + if (pdev->id == 0) + dev_data0 = &pdev->dev; + else + dev_data1 = &pdev->dev; + + dptc_device_data->dptc_platform_data = pdev->dev.platform_data; + + /* Set driver data */ + platform_set_drvdata(pdev, dptc_device_data); + + return 0; + +err1: + dev_err(&pdev->dev, "Failed to probe DPTC\n"); + kfree(dptc_device_data); + return ret; +} + +/*! + * This function is called to put DPTC in a low power state. + * + * @param pdev the device structure + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int mxc_dptc_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct dptc_device *drv_data = pdev->dev.driver_data; + + if (drv_data->dptc_is_active) + stop_dptc(&pdev->dev); + + return 0; +} + +/*! + * This function is called to resume the MU from a low power state. + * + * @param dev the device structure + * @param level the stage in device suspension process that we want the + * device to be put in + * + * @return The function always returns 0. + */ +static int mxc_dptc_resume(struct platform_device *pdev) +{ + struct dptc_device *drv_data = pdev->dev.driver_data; + + if (drv_data->dptc_is_active) + return start_dptc(&pdev->dev); + + return 0; +} + +static struct platform_driver mxc_dptc_driver = { + .driver = { + .name = "mxc_dptc", + .owner = THIS_MODULE, + }, + .probe = mxc_dptc_probe, + .suspend = mxc_dptc_suspend, + .resume = mxc_dptc_resume, +}; + +/*! + * This function is called to resume the MU from a low power state. + * + * @param dev the device structure used to give information on which MU + * device (0 through 3 channels) to suspend + * @param level the stage in device suspension process that we want the + * device to be put in + * + * @return The function always returns 0. + */ + +static int __init dptc_init(void) +{ + if (platform_driver_register(&mxc_dptc_driver) != 0) { + printk(KERN_ERR "mxc_dptc_driver register failed\n"); + return -ENODEV; + } + + printk(KERN_INFO "DPTC driver module loaded\n"); + + return 0; +} + +static void __exit dptc_cleanup(void) +{ + /* Unregister the device structure */ + platform_driver_unregister(&mxc_dptc_driver); + + printk("DPTC driver module unloaded\n"); +} + +module_init(dptc_init); +module_exit(dptc_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("DPTC driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/plat-mxc/dvfs_core.c linux-2.6.26-lab126/arch/arm/plat-mxc/dvfs_core.c --- linux-2.6.26/arch/arm/plat-mxc/dvfs_core.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/dvfs_core.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,584 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dvfs_core.c + * + * @brief A simplied driver for the Freescale Semiconductor MXC DVFS module. + * + * Upon initialization, the DVFS driver initializes the DVFS hardware + * sets up driver nodes attaches to the DVFS interrupt and initializes internal + * data structures. When the DVFS interrupt occurs the driver checks the cause + * of the interrupt (lower frequency, increase frequency or emergency) and + * changes the CPU voltage according to translation table that is loaded into + * the driver. + * + * @ingroup PM + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MXC_DVFSTHRS_UPTHR_MASK 0x0FC00000 +#define MXC_DVFSTHRS_UPTHR_OFFSET 22 +#define MXC_DVFSTHRS_DNTHR_MASK 0x003F0000 +#define MXC_DVFSTHRS_DNTHR_OFFSET 16 +#define MXC_DVFSTHRS_PNCTHR_MASK 0x0000003F +#define MXC_DVFSTHRS_PNCTHR_OFFSET 0 + +#define MXC_DVFSCOUN_DNCNT_MASK 0x00FF0000 +#define MXC_DVFSCOUN_DNCNT_OFFSET 16 +#define MXC_DVFSCOUN_UPCNT_MASK 0x000000FF +#define MXC_DVFSCOUN_UPCNT_OFFSET 0 + +#define MXC_DVFSEMAC_EMAC_MASK 0x000001FF +#define MXC_DVFSEMAC_EMAC_OFFSET 0 + +#define MXC_DVFSCNTR_DVFEV 0x10000000 +#define MXC_DVFSCNTR_LBMI 0x08000000 +#define MXC_DVFSCNTR_LBFL 0x06000000 +#define MXC_DVFSCNTR_DVFIS 0x01000000 +#define MXC_DVFSCNTR_FSVAIM 0x00400000 +#define MXC_DVFSCNTR_FSVAI_MASK 0x00300000 +#define MXC_DVFSCNTR_FSVAI_OFFSET 20 +#define MXC_DVFSCNTR_WFIM 0x00080000 +#define MXC_DVFSCNTR_WFIM_OFFSET 19 +#define MXC_DVFSCNTR_MAXF_MASK 0x00040000 +#define MXC_DVFSCNTR_MAXF_OFFSET 18 +#define MXC_DVFSCNTR_MINF_MASK 0x00020000 +#define MXC_DVFSCNTR_MINF_OFFSET 17 +#define MXC_DVFSCNTR_LTBRSR_MASK 0x00000018 +#define MXC_DVFSCNTR_LTBRSR_OFFSET 3 +#define MXC_DVFSCNTR_DVFEN 0x00000001 + +#define MXC_GPCCNTR_GPCIRQ 0x00100000 +#define MXC_GPCCNTR_DVFS0CR 0x00010000 +#define MXC_GPCCNTR_ADU 0x00008000 +#define MXC_GPCCNTR_STRT 0x00004000 +#define MXC_GPCCNTR_FUPD 0x00002000 +#define MXC_GPCCNTR_HTRI_MASK 0x0000000F +#define MXC_GPCCNTR_HTRI_OFFSET 0 + +#define MXC_GPCVCR_VINC_MASK 0x00020000 +#define MXC_GPCVCR_VINC_OFFSET 17 +#define MXC_GPCVCR_VCNTU_MASK 0x00010000 +#define MXC_GPCVCR_VCNTU_OFFSET 16 +#define MXC_GPCVCR_VCNT_MASK 0x00007FFF +#define MXC_GPCVCR_VCNT_OFFSET 0 + +static struct delayed_work dvfs_core_work; +static struct mxc_dvfs_platform_data *dvfs_data; +static struct device *dvfs_dev; +static struct cpu_wp *cpu_wp_tbl; +int dvfs_core_resume; +int curr_wp; +int dvfs_core_is_active; + +/* + * Clock structures + */ +static struct clk *cpu_clk; +static struct clk *dvfs_clk; +static struct regulator *core_regulator; + +enum { + FSVAI_FREQ_NOCHANGE = 0x0, + FSVAI_FREQ_INCREASE, + FSVAI_FREQ_DECREASE, + FSVAI_FREQ_EMERG, +}; + +/* + * Load tracking buffer source: 1 for ld_add; 0 for pre_ld_add; 2 for after EMA + */ +#define DVFS_LTBRSR (2 << MXC_DVFSCNTR_LTBRSR_OFFSET) + +DEFINE_SPINLOCK(mxc_dvfs_core_lock); + +static void dvfs_load_config(void) +{ + u32 reg; + + reg = 0; + reg |= dvfs_data->upthr_val << MXC_DVFSTHRS_UPTHR_OFFSET; + reg |= dvfs_data->dnthr_val << MXC_DVFSTHRS_DNTHR_OFFSET; + reg |= dvfs_data->pncthr_val; + __raw_writel(reg, dvfs_data->dvfs_thrs_reg_addr); + + reg = 0; + reg |= dvfs_data->dncnt_val << MXC_DVFSCOUN_DNCNT_OFFSET; + reg |= dvfs_data->upcnt_val << MXC_DVFSCOUN_UPCNT_OFFSET; + __raw_writel(reg, dvfs_data->dvfs_coun_reg_addr); +} + +static int start_dvfs(void) +{ + u32 reg, flags; + + if (dvfs_core_is_active) + return 0; + + spin_lock_irqsave(&mxc_dvfs_core_lock, flags); + + clk_enable(dvfs_clk); + + /* config reg GPC_CNTR */ + reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr); + + /* GPCIRQ=1, select ARM IRQ */ + reg |= MXC_GPCCNTR_GPCIRQ; + /* ADU=1, select ARM domain */ + reg |= MXC_GPCCNTR_ADU; + __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr); + + /* Enable DVFS interrupt */ + reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr); + /* FSVAIM=0 */ + reg = (reg & ~MXC_DVFSCNTR_FSVAIM); + /* Set MAXF, MINF */ + reg = (reg & ~(MXC_DVFSCNTR_MAXF_MASK | MXC_DVFSCNTR_MINF_MASK)); + reg |= 1 << MXC_DVFSCNTR_MAXF_OFFSET; + /* Select ARM domain */ + reg |= MXC_DVFSCNTR_DVFIS; + /* Enable DVFS frequency adjustment interrupt */ + reg = (reg & ~MXC_DVFSCNTR_FSVAIM); + /* Set load tracking buffer register source */ + reg = (reg & ~MXC_DVFSCNTR_LTBRSR_MASK); + reg |= DVFS_LTBRSR; + /* Set DIV3CK */ + reg = (reg & ~(dvfs_data->div3ck_mask)); + reg |= (dvfs_data->div3ck_val) << (dvfs_data->div3ck_offset); + /* Enable DVFS */ + reg |= MXC_DVFSCNTR_DVFEN; + __raw_writel(reg, dvfs_data->dvfs_cntr_reg_addr); + + dvfs_core_is_active = 1; + + spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags); + + printk(KERN_DEBUG "DVFS is started\n"); + + return 0; +} + +/*! + * This function is called for module initialization. + * It sets up the DVFS hardware. + * It sets default values for DVFS thresholds and counters. The default + * values was chosen from a set of different reasonable values. They was tested + * and the default values in the driver gave the best results. + * More work should be done to find optimal values. + * + * @return 0 if successful; non-zero otherwise. + * + */ +static int init_dvfs_controller(void) +{ + /* DVFS loading config */ + dvfs_load_config(); + + /* Set EMAC value */ + __raw_writel((dvfs_data->emac_val << MXC_DVFSEMAC_EMAC_OFFSET), + dvfs_data->dvfs_emac_reg_addr); + + return 0; +} + +static irqreturn_t dvfs_irq(int irq, void *dev_id) +{ + u32 reg; + + /* Check if DVFS0 (ARM) id requesting for freqency/voltage update */ + if ((__raw_readl(dvfs_data->gpc_cntr_reg_addr) & MXC_GPCCNTR_DVFS0CR) == + 0) + return IRQ_NONE; + + /* Mask DVFS irq */ + reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr); + /* FSVAIM=1 */ + reg |= MXC_DVFSCNTR_FSVAIM; + __raw_writel(reg, dvfs_data->dvfs_cntr_reg_addr); + + schedule_delayed_work(&dvfs_core_work, 0); + + return IRQ_HANDLED; +} + +static void dvfs_core_workqueue_handler(struct work_struct *work) +{ + u32 fsvai; + u32 reg; + u32 curr_cpu; + unsigned long rate = 0; + int ret = 0; + int uvol; + int maxf = 0, minf = 0; + + /* Check DVFS frequency adjustment interrupt status */ + reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr); + fsvai = (reg & MXC_DVFSCNTR_FSVAI_MASK) >> MXC_DVFSCNTR_FSVAI_OFFSET; + + /* Check FSVAI, FSVAI=0 is error */ + if (fsvai == FSVAI_FREQ_NOCHANGE) { + /* Do nothing. Freq change is not required */ + goto END; + } + + curr_cpu = clk_get_rate(cpu_clk); + + /* If FSVAI indicate freq down, + check arm-clk is not in lowest frequency 200 MHz */ + if (fsvai == FSVAI_FREQ_DECREASE) { + if (curr_cpu == cpu_wp_tbl[dvfs_data->num_wp - 1].cpu_rate) { + minf = 1; + goto END; + } else { + /* freq down */ + curr_wp++; + if (curr_wp >= dvfs_data->num_wp) { + curr_wp = dvfs_data->num_wp - 1; + goto END; + } + + rate = cpu_wp_tbl[curr_wp].cpu_rate; + uvol = cpu_wp_tbl[curr_wp].cpu_voltage; + if (curr_wp == dvfs_data->num_wp - 1) + minf = 1; + + ret = clk_set_rate(cpu_clk, rate); + if (ret != 0) { + printk(KERN_DEBUG + "cannot set CPU clock rate\n"); + goto END; + } + + /* START the GPC main control FSM */ + /* set VINC */ + reg = __raw_readl(dvfs_data->gpc_vcr_reg_addr); + reg &= + ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK | + MXC_GPCVCR_VCNT_MASK); + reg |= + (1 << MXC_GPCVCR_VCNTU_OFFSET) | + (100 << MXC_GPCVCR_VCNT_OFFSET); + __raw_writel(reg, dvfs_data->gpc_vcr_reg_addr); + + /* Set the voltage for the GP domain. */ + ret = regulator_set_voltage(core_regulator, uvol); + if (ret < 0) { + printk(KERN_DEBUG + "COULD NOT SET CORE VOLTAGE!!!!!\n"); + goto END; + } + udelay(dvfs_data->delay_time); + } + } else { + if (curr_cpu == cpu_wp_tbl[0].cpu_rate) { + maxf = 1; + goto END; + } else { + /* freq up */ + curr_wp = 0; + rate = cpu_wp_tbl[curr_wp].cpu_rate; + /* START the GPC main control FSM */ + /* set VINC */ + reg = __raw_readl(dvfs_data->gpc_vcr_reg_addr); + reg &= + ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK | + MXC_GPCVCR_VCNT_MASK); + reg |= + (1 << MXC_GPCVCR_VCNTU_OFFSET) | + (100 << MXC_GPCVCR_VCNT_OFFSET); + __raw_writel(reg, dvfs_data->gpc_vcr_reg_addr); + + ret = regulator_set_voltage(core_regulator, + cpu_wp_tbl[curr_wp]. + cpu_voltage); + if (ret < 0) { + printk(KERN_DEBUG + "COULD NOT SET CORE VOLTAGE!!!!\n"); + goto END; + } + udelay(dvfs_data->delay_time); + + ret = + clk_set_rate(cpu_clk, cpu_wp_tbl[curr_wp].cpu_rate); + if (ret != 0) + printk(KERN_DEBUG + "cannot set CPU clock rate\n"); + maxf = 1; + } + } + +END: /* Set MAXF, MINF */ + reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr); + reg = (reg & ~(MXC_DVFSCNTR_MAXF_MASK | MXC_DVFSCNTR_MINF_MASK)); + reg |= maxf << MXC_DVFSCNTR_MAXF_OFFSET; + reg |= minf << MXC_DVFSCNTR_MINF_OFFSET; + + /* Enable DVFS interrupt */ + /* FSVAIM=0 */ + reg = (reg & ~MXC_DVFSCNTR_FSVAIM); + /* LBFL=1 */ + reg = (reg & ~MXC_DVFSCNTR_LBFL); + reg |= MXC_DVFSCNTR_LBFL; + __raw_writel(reg, dvfs_data->dvfs_cntr_reg_addr); +} + +/*! + * This function disables the DVFS module. + */ +static void stop_dvfs(void) +{ + u32 reg = 0; + u32 flags; + u32 curr_cpu; + + if (dvfs_core_is_active) { + spin_lock_irqsave(&mxc_dvfs_core_lock, flags); + + /* Mask dvfs irq, disable DVFS */ + reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr); + /* FSVAIM=1 */ + reg |= MXC_DVFSCNTR_FSVAIM; + reg = (reg & ~MXC_DVFSCNTR_DVFEN); + __raw_writel(reg, dvfs_data->dvfs_cntr_reg_addr); + + dvfs_core_is_active = 0; + spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags); + + curr_wp = 0; + curr_cpu = clk_get_rate(cpu_clk); + if (curr_cpu != cpu_wp_tbl[curr_wp].cpu_rate) { + if (regulator_set_voltage(core_regulator, + cpu_wp_tbl[curr_wp]. + cpu_voltage) == 0) + clk_set_rate(cpu_clk, + cpu_wp_tbl[curr_wp].cpu_rate); + } + + clk_disable(dvfs_clk); + } + + printk(KERN_DEBUG "DVFS is stopped\n"); +} + +static ssize_t dvfs_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (dvfs_core_is_active) + return sprintf(buf, "DVFS is enabled\n"); + else + return sprintf(buf, "DVFS is disabled\n"); +} + + +static ssize_t dvfs_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + if (strstr(buf, "1") != NULL) { + if (start_dvfs() != 0) + printk(KERN_ERR "Failed to start DVFS\n"); + } else if (strstr(buf, "0") != NULL) + stop_dvfs(); + + return size; +} + +static DEVICE_ATTR(enable, 0644, dvfs_enable_show, dvfs_enable_store); + +/*! + * This is the probe routine for the DVFS driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + */ +static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev) +{ + int err = 0; + struct resource *res; + int cpu_wp_nr; + int irq; + + printk(KERN_INFO "mxc_dvfs_core_probe\n"); + dvfs_dev = &pdev->dev; + dvfs_data = pdev->dev.platform_data; + + INIT_DELAYED_WORK(&dvfs_core_work, dvfs_core_workqueue_handler); + + cpu_clk = clk_get(NULL, dvfs_data->clk1_id); + if (IS_ERR(cpu_clk)) { + printk(KERN_ERR "%s: failed to get cpu clock\n", __func__); + return PTR_ERR(cpu_clk); + } + + dvfs_clk = clk_get(NULL, dvfs_data->clk2_id); + if (IS_ERR(dvfs_clk)) { + printk(KERN_ERR "%s: failed to get dvfs clock\n", __func__); + return PTR_ERR(dvfs_clk); + } + + core_regulator = regulator_get(NULL, dvfs_data->reg_id); + if (IS_ERR(core_regulator)) { + clk_put(cpu_clk); + clk_put(dvfs_clk); + printk(KERN_ERR "%s: failed to get gp regulator\n", __func__); + return PTR_ERR(core_regulator); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + err = -ENODEV; + goto err1; + } + + /* + * Request the DVFS interrupt + */ + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + err = irq; + goto err1; + } + + /* request the DVFS interrupt */ + err = request_irq(irq, dvfs_irq, IRQF_SHARED, "dvfs", dvfs_dev); + if (err) + printk(KERN_ERR + "DVFS: Unable to attach to DVFS interrupt,err = %d", + err); + + clk_enable(dvfs_clk); + err = init_dvfs_controller(); + if (err) { + printk(KERN_ERR "DVFS: Unable to initialize DVFS"); + return err; + } + clk_disable(dvfs_clk); + + err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_enable.attr); + if (err) { + printk(KERN_ERR + "DVFS: Unable to register sysdev entry for DVFS"); + return err; + } + + /* Set the current working point. */ + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + curr_wp = 0; + dvfs_core_resume = 0; + + return err; + +err1: + dev_err(&pdev->dev, "Failed to probe DVFS CORE\n"); + return err; +} + +/*! + * This function is called to put DVFS in a low power state. + * + * @param pdev the device structure + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int mxc_dvfs_core_suspend(struct platform_device *pdev, + pm_message_t state) +{ + if (dvfs_core_is_active) { + dvfs_core_resume = 1; + stop_dvfs(); + } + + return 0; +} + +/*! + * This function is called to resume the MU from a low power state. + * + * @param dev the device structure + * @param level the stage in device suspension process that we want the + * device to be put in + * + * @return The function always returns 0. + */ +static int mxc_dvfs_core_resume(struct platform_device *pdev) +{ + if (dvfs_core_resume) { + dvfs_core_resume = 0; + start_dvfs(); + } + + return 0; +} + +static struct platform_driver mxc_dvfs_core_driver = { + .driver = { + .name = "mxc_dvfs_core", + }, + .probe = mxc_dvfs_core_probe, + .suspend = mxc_dvfs_core_suspend, + .resume = mxc_dvfs_core_resume, +}; + +static int __init dvfs_init(void) +{ + if (platform_driver_register(&mxc_dvfs_core_driver) != 0) { + printk(KERN_ERR "mxc_dvfs_core_driver register failed\n"); + return -ENODEV; + } + + printk(KERN_INFO "DVFS driver module loaded\n"); + + return 0; +} + +static void __exit dvfs_cleanup(void) +{ + stop_dvfs(); + + /* release the DVFS interrupt */ + free_irq(MXC_INT_GPC1, NULL); + + sysfs_remove_file(&dvfs_dev->kobj, &dev_attr_enable.attr); + + /* Unregister the device structure */ + platform_driver_unregister(&mxc_dvfs_core_driver); + + clk_put(cpu_clk); + clk_put(dvfs_clk); + + printk(KERN_INFO "DVFS driver module unloaded\n"); + +} + +module_init(dvfs_init); +module_exit(dvfs_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("DVFS driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/plat-mxc/entry-pm.S linux-2.6.26-lab126/arch/arm/plat-mxc/entry-pm.S --- linux-2.6.26/arch/arm/plat-mxc/entry-pm.S 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/entry-pm.S 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,315 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file plat-mxc/entry-pm.S + * + * @brief This file contains common pm entry . + * + * @ingroup MXC_PM + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define WAIT_MODE 111 +#define DOZE_MODE 112 +#define STOP_MODE 113 +#define DSM_MODE 114 + +#define PM_XLOAD_SIZE 0x04 +#define PM_XLOAD_ENTRY 0x08 +#define PM_XLOAD_SUSPEND_MODE 0x0C +#define PM_XLOAD_CORE_SP 0x10 + +#define PROCINFO_PROC_FNS 36 +#define PROC_FIN_FN 12 +#define PROC_IDLE_FN 20 + +#ifdef CONFIG_FIQ +#define ARM_CONTEXT_SIZE 12 +#else +#define ARM_CONTEXT_SIZE 8 +#endif + +#ifdef CONFIG_PM_VERBOSE +resume_str: + .string "Resume from DSM..." + .size resume_str, . - resume_str + +.macro show_resume_str + ldr r0, =resume_str + bl printk +.endm + +#else +.macro show_resume_str +.endm +#endif + + .data + .align 3 +arm_core_context: + .rept ARM_CONTEXT_SIZE + .long 0 + .endr + +#ifdef CONFIG_VFP + .text + .align 5 +arm_vfp_save: + mov ip, sp + stmdb sp!, {r0-r8, fp, ip, lr, pc} + sub fp, ip, #4 + mov r1, #THREAD_SIZE + sub r1, r1, #1 + bic r0, sp, r1 + ldr r8, [r0, #TI_CPU] + add r4, r0, #TI_VFPSTATE + + ldr r3, =last_VFP_context + VFPFMRX r2, FPEXC + tst r2, #FPEXC_EN + bne 1f + + ldr r4, [r3, r8, lsl #2] + cmp r4, #0 + beq dead_vfp +1: + bic r1, r2, #FPEXC_EN + VFPFMXR FPEXC, r1 + /*TODO: SMP */ + VFPFSTMIA r4, r1 + VFPFMRX r5, FPSCR + tst r2, #FPEXC_EX + VFPFMRX r6, FPINST, NE + tstne r2, #FPEXC_FP2V + VFPFMRX r7, FPINST2, NE + stmia r4, {r2, r5, r6, r7} + + mov r1, #0 + str r1, [r3, r8, lsl #2] +dead_vfp: + ldmia sp, {r0-r8, fp, sp, pc} +#endif +/* + * The function just be called in this file + * Current r0 ~r4 are not saved. + * Otherwise, the working registers should be saved + */ + .text + .align 5 +arm_core_save: + mov ip, sp + stmdb sp!, {r8, r9, sl, fp, ip, lr, pc} + sub fp, ip, #4 + ldr r0, =arm_core_context + mov r3, r0 + /* SVC mode */ + mrs r1, spsr @Save spsr + mrs r2, cpsr @Save cpsr + stmia r0!, {r1, r2} + /* Abort mode */ + msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | ABT_MODE + stmia r0!, {sp} @Save stack pointer for abort mode + msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | UND_MODE + stmia r0!, {sp} @Save stack pointer for undefine mode + msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | IRQ_MODE + stmia r0!, {sp} @Save stack pointer for irq mode +#ifdef CONFIG_FIQ + msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | FIQ_MODE + /*Save general register and sp for fiq mode*/ + stmia r0!, {r8-r9, sl, fp, ip, sp} +#endif + ldr r0, [r3, #4] + msr cpsr_c, r0 + ldmia sp, {r8-r9, sl, fp, sp, pc} + +/* + * The function just be called in this file + * Current r0 ~r4 are not saved. + * Otherwise, the working registers should be saved + */ +arm_core_restore: + mov ip, sp + stmdb sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r0, =arm_core_context + mov r3, r0 + /* SVC mode */ + add r0, r0, #8 @skip svc mode + /* Abort mode */ + msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | ABT_MODE + ldmia r0!, {sp} @restore stack pointer for abort mode + msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | UND_MODE + ldmia r0!, {sp} @restore stack pointer for undefine mode + msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | IRQ_MODE + ldmia r0!, {sp} @restore stack pointer for irq mode +#ifdef CONFIG_FIQ + msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | FIQ_MODE + /*Save general register and sp for fiq mode*/ + ldmia r0!, {r8-r9, sl, fp, ip, sp} +#endif + ldmia r3!, {r1, r2} + msr cpsr, r2 @restore cpsr + msr spsr, r1 @restore spsr + ldmia sp, {fp, sp, pc} + +mxc_cp15_context: + .rept 16 + .long 0 + .endr + + .align 5 +mxc_cp15_restore: + /* Physical address */ + adr r0, mxc_cp15_context + ldmia r0, {r1-r9} +#ifndef CONFIG_PM_DEBUG + @Add dynamic check to skip this block when debug + sub lr, lr, #PHYS_OFFSET + add lr, lr, #PAGE_OFFSET +#endif + mcr p15, 0, r3, c1, c0, 2 @CP Access Register + mcr p15, 0, r2, c1, c0, 1 @Aux Control register + +#ifndef CONFIG_PM_DEBUG + mcr p15, 0, r0, c7, c5, 6 @flush BTAC/BTB + mcr p15, 0, r0, c7, c7, 0 @invalidate both caches + mcr p15, 0, r0, c8, c7, 0 @Inval TLBs +#endif + + mcr p15, 0, r4, c13, c0, 0 @PID + mcr p15, 0, r5, c13, c0, 1 @Context ID + + mcr p15, 0, r6, c3, c0, 0 @Domain Access Register + mcr p15, 0, r7, c2, c0, 0 @TTB0 + mcr p15, 0, r8, c2, c0, 1 @TTB1 + mcr p15, 0, r9, c2, c0, 2 @TTBC + + mcr p15, 0, r1, c1, c0, 0 @Control Register + /* mcu enabled */ + mrc p15, 0, r0, c2, c0, 0 + + mov pc, lr + nop + nop + nop + nop + nop + nop + nop + nop + +mxc_cp15_save: + mov ip, sp + stmdb sp!, {r8-r9, fp, ip, lr, pc} + sub fp, ip, #4 + ldr r0, =mxc_cp15_context +/* System Control Registers */ + mrc p15, 0, r1, c1, c0, 0 @Control Register + mrc p15, 0, r2, c1, c0, 1 @Aux Control Register + mrc p15, 0, r3, c1, c0, 2 @CP access Register + +/* Memory management Registers */ + mrc p15, 0, r4, c13, c0, 0 @PID + mrc p15, 0, r5, c13, c0, 1 @Context ID + + mrc p15, 0, r6, c3, c0, 0 @Domain Access Register + + mrc p15, 0, r7, c2, c0, 0 @TTB0 + mrc p15, 0, r8, c2, c0, 1 @TTB1 + mrc p15, 0, r9, c2, c0, 2 @TTBC + stmia r0, {r1-r9} + ldmia sp, {r8, r9, fp, sp, pc} + +/* + * int __mxc_pm_arch_entry(u32 entry, u32 size) + */ + .align 5 + .globl mxc_pm_arch_entry +mxc_pm_arch_entry: + mov ip, sp + stmdb sp!, {r4-r9, sl, fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + mov r8, r0 @save entry + mov r9, r1 @save entry size +#ifdef CONFIG_VFP + bl arm_vfp_save +#endif + /* r0 ~r3, ip is dirty*/ + bl arm_core_save @save arm context + bl mxc_cp15_save + mov r0, sp + mov r1, r8 @restore entry + mov r2, r9 @restore entry size + bl __mxc_pm_xload_setup +1: bl cpu_v6_proc_fin + bl cpu_v6_do_idle + nop + nop + nop + nop +__mxc_pm_arch_leave: + adr r0, __mxc_pm_xload_info + ldr sp, [r0, #PM_XLOAD_CORE_SP] + +#ifndef CONFIG_PM_DEBUG + sub sp, sp, #PAGE_OFFSET + add sp, sp, #PHYS_OFFSET +#endif + bl mxc_cp15_restore +#ifndef CONFIG_PM_DEBUG + sub sp, sp, #PHYS_OFFSET + add sp, sp, #PAGE_OFFSET +#endif + show_resume_str + bl arm_core_restore + ldmib sp, {r4-r9, sl, fp, sp, pc} + +__mxc_pm_xload_info: + adr pc, __mxc_pm_xload_entry @Jump instruction + .long __mxc_pm_xload_end - __mxc_pm_xload_info @loader size + .long (__mxc_pm_arch_leave - PAGE_OFFSET + PHYS_OFFSET) @resume entry + .long 0 @suspend state + .long 0 @Core Stack pointer +__mxc_pm_xload_entry: + adr r0, __mxc_pm_xload_info + ldr pc, [r0, #PM_XLOAD_ENTRY] +__mxc_pm_xload_end: + +/* + * __mxc_pm_xload_setup(u32 sp, u32 entry, u32 size) + * r0~r6 is dirty + */ +__mxc_pm_xload_setup: + ldr r3, =__mxc_pm_xload_info + str r0, [r3, #PM_XLOAD_CORE_SP] + ldr r4, [r3, #PM_XLOAD_SIZE] + cmp r2, r4 + blo 2f +1: ldr r5, [r3], #4 + str r5, [r1], #4 + subs r4, r4, #4 + bhi 1b + b 3f +2: str r3, [r1] +3: mov pc, lr diff -urN linux-2.6.26/arch/arm/plat-mxc/gpio.c linux-2.6.26-lab126/arch/arm/plat-mxc/gpio.c --- linux-2.6.26/arch/arm/plat-mxc/gpio.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/gpio.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,909 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * Implementation based on omap gpio.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*! + * @file plat-mxc/gpio.c + * + * @brief This file contains the GPIO implementation details. + * + * @ingroup GPIO + */ + +/* GPIO related defines */ +#if defined(CONFIG_ARCH_MX27) || defined(CONFIG_ARCH_MX21) +enum gpio_reg { + GPIO_DR = 0x1C, + GPIO_GDIR = 0x00, + GPIO_PSR = 0x24, + GPIO_ICR1 = 0x028, + GPIO_ICR2 = 0x2C, + GPIO_IMR = 0x30, + GPIO_ISR = 0x34, +}; +#else +enum gpio_reg { + GPIO_DR = 0x00, + GPIO_GDIR = 0x04, + GPIO_PSR = 0x08, + GPIO_ICR1 = 0x0C, + GPIO_ICR2 = 0x10, + GPIO_IMR = 0x14, + GPIO_ISR = 0x18, +}; +#endif + +extern struct mxc_gpio_port mxc_gpio_ports[]; + +struct gpio_port { + u32 num; /*!< gpio port number */ + u32 base; /*!< gpio port base VA */ +#ifdef MXC_GPIO_SPLIT_IRQ_2 + u16 irq_0_15, irq_16_31; +#else + u16 irq; /*!< irq number to the core */ +#endif + u16 virtual_irq_start; /*!< virtual irq start number */ + u32 reserved_map; /*!< keep track of which pins are in use */ + u32 irq_is_level_map; /*!< if a pin's irq is level sensitive. default is edge */ + u32 suspend_wakeup; + u32 saved_wakeup; + raw_spinlock_t lock; /*!< lock when operating on the port */ +}; +static struct gpio_port gpio_port[GPIO_PORT_NUM]; + +/* + * Find the pointer to the gpio_port for a given pin. + * @param gpio a gpio pin number + * @return pointer to \b struc \b gpio_port + */ +static inline struct gpio_port *get_gpio_port(u32 gpio) +{ + return &gpio_port[GPIO_TO_PORT(gpio)]; +} + +/* + * Check if a gpio pin is within [0, MXC_MAX_GPIO_LINES -1]. + * @param gpio a gpio pin number + * @return 0 if the pin number is valid; -1 otherwise + */ +static int check_gpio(u32 gpio) +{ + if (gpio >= MXC_MAX_GPIO_LINES) { + printk(KERN_ERR "mxc-gpio: invalid GPIO %d\n", gpio); +#ifdef CONFIG_MXC_GPIO_DEBUG + dump_stack(); +#endif + return -1; + } + return 0; +} + +/* + * Set a GPIO pin's direction + * @param port pointer to a gpio_port + * @param index gpio pin index value (0~31) + * @param is_input 0 for output; non-zero for input + */ +static void _set_gpio_direction(struct gpio_port *port, u32 index, int is_input) +{ + u32 reg = port->base + GPIO_GDIR; + u32 l; + + l = __raw_readl(reg); + if (is_input) + l &= ~(1 << index); + else + l |= 1 << index; + __raw_writel(l, reg); +} + +/*! + * Exported function to set a GPIO pin's direction + * @param pin a name defined by \b iomux_pin_name_t + * @param is_input 1 (or non-zero) for input; 0 for output + */ +void mxc_set_gpio_direction(iomux_pin_name_t pin, int is_input) +{ + struct gpio_port *port; + u32 gpio = IOMUX_TO_GPIO(pin); + + if (check_gpio(gpio) < 0) + return; + port = get_gpio_port(gpio); + spin_lock(&port->lock); + _set_gpio_direction(port, GPIO_TO_INDEX(gpio), is_input); + spin_unlock(&port->lock); +} + +/* + * Set a GPIO pin's data output + * @param port pointer to a gpio_port + * @param index gpio pin index value (0~31) + * @param data value to be set (only 0 or 1 is valid) + */ +static void _set_gpio_dataout(struct gpio_port *port, u32 index, u32 data) +{ + u32 reg = port->base + GPIO_DR; + u32 l = 0; + + l = (__raw_readl(reg) & (~(1 << index))) | (data << index); + __raw_writel(l, reg); +} + +/*! + * Exported function to set a GPIO pin's data output + * @param pin a name defined by \b iomux_pin_name_t + * @param data value to be set (only 0 or 1 is valid) + */ +void mxc_set_gpio_dataout(iomux_pin_name_t pin, u32 data) +{ + struct gpio_port *port; + u32 gpio = IOMUX_TO_GPIO(pin); + + if (check_gpio(gpio) < 0) + return; + + port = get_gpio_port(gpio); + spin_lock(&port->lock); + _set_gpio_dataout(port, GPIO_TO_INDEX(gpio), (data == 0) ? 0 : 1); + spin_unlock(&port->lock); +} + +/*! + * Return the data value of a GPIO signal. + * @param pin a name defined by \b iomux_pin_name_t + * + * @return value (0 or 1) of the GPIO signal; -1 if pass in invalid pin + */ +int mxc_get_gpio_datain(iomux_pin_name_t pin) +{ + struct gpio_port *port; + u32 gpio = IOMUX_TO_GPIO(pin); + + if (check_gpio(gpio) < 0) + return -1; + + port = get_gpio_port(gpio); + + /* + * SW workaround for the eSDHC1 Write Protected feature + * The PSR of CSPI1_SS0 (GPIO3_2) should be read. + */ + if (machine_is_mx37_3ds() && (gpio == ((32 * 2) + 2))) + return (__raw_readl(port->base + GPIO_PSR) >> + GPIO_TO_INDEX(gpio)) & 1; + else + return (__raw_readl(port->base + GPIO_DR) >> + GPIO_TO_INDEX(gpio)) & 1; +} + +/* + * Clear a GPIO signal's interrupt status + * + * @param port pointer to a gpio_port + * @param index gpio pin index value (0~31) + */ +static inline void _clear_gpio_irqstatus(struct gpio_port *port, u32 index) +{ + __raw_writel(1 << index, port->base + GPIO_ISR); +} + +/* + * Set a GPIO pin's interrupt edge + * @param port pointer to a gpio_port + * @param index gpio pin index value (0~31) + * @param icr one of the values defined in \b gpio_edge_t + * to indicate how to generate an interrupt + */ +static void _set_gpio_edge_ctrl(struct gpio_port *port, u32 index, + gpio_edge_t edge) +{ + u32 reg = port->base; + u32 l, sig; + + reg += (index <= 15) ? GPIO_ICR1 : GPIO_ICR2; + sig = (index <= 15) ? index : (index - 16); + l = __raw_readl(reg); + l = (l & (~(0x3 << (sig * 2)))) | (edge << (sig * 2)); + __raw_writel(l, reg); + _clear_gpio_irqstatus(port, index); +} + +/* + * Enable/disable a GPIO signal's interrupt. + * + * @param port pointer to a gpio_port + * @param index gpio pin index value (0~31) + * @param enable \b #true for enabling the interrupt; \b #false otherwise + */ +static inline void _set_gpio_irqenable(struct gpio_port *port, u32 index, + bool enable) +{ + u32 reg = port->base + GPIO_IMR; + u32 mask = (!enable) ? 0 : 1; + u32 l; + + l = __raw_readl(reg); + l = (l & (~(1 << index))) | (mask << index); + __raw_writel(l, reg); +} + +static inline int _request_gpio(struct gpio_port *port, u32 index) +{ + spin_lock(&port->lock); + if (port->reserved_map & (1 << index)) { + printk(KERN_ERR + "GPIO port %d (0-based), pin %d is already reserved!\n", + port->num, index); + spin_unlock(&port->lock); +#ifdef CONFIG_MXC_GPIO_DEBUG + dump_stack(); +#endif + return -1; + } + port->reserved_map |= (1 << index); + spin_unlock(&port->lock); + return 0; +} + +/*! + * Request ownership for a GPIO pin. The caller has to check the return value + * of this function to make sure it returns 0 before make use of that pin. + * @param pin a name defined by \b iomux_pin_name_t + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_gpio(iomux_pin_name_t pin) +{ + struct gpio_port *port; + u32 index, gpio = IOMUX_TO_GPIO(pin); + + if (check_gpio(gpio) < 0) + return -EINVAL; + + port = get_gpio_port(gpio); + index = GPIO_TO_INDEX(gpio); + + return _request_gpio(port, index); +} + +/*! + * Release ownership for a GPIO pin + * @param pin a name defined by \b iomux_pin_name_t + */ +void mxc_free_gpio(iomux_pin_name_t pin) +{ + struct gpio_port *port; + u32 index, gpio = IOMUX_TO_GPIO(pin); + + if (check_gpio(gpio) < 0) + return; + + port = get_gpio_port(gpio); + index = GPIO_TO_INDEX(gpio); + + spin_lock(&port->lock); + if ((!(port->reserved_map & (1 << index)))) { + printk(KERN_ERR "GPIO port %d, pin %d wasn't reserved!\n", + port->num, index); + spin_unlock(&port->lock); +#ifdef CONFIG_MXC_GPIO_DEBUG + dump_stack(); +#endif + return; + } + port->reserved_map &= ~(1 << index); + port->irq_is_level_map &= ~(1 << index); + _set_gpio_direction(port, index, 1); + _set_gpio_irqenable(port, index, 0); + _clear_gpio_irqstatus(port, index); + spin_unlock(&port->lock); +} + +/* + * We need to unmask the GPIO port interrupt as soon as possible to + * avoid missing GPIO interrupts for other lines in the port. + * Then we need to mask-read-clear-unmask the triggered GPIO lines + * in the port to avoid missing nested interrupts for a GPIO line. + * If we wait to unmask individual GPIO lines in the port after the + * line's interrupt handler has been run, we may miss some nested + * interrupts. + */ +static void mxc_gpio_irq_handler(u32 irq, struct irq_desc *desc) +{ + u32 isr_reg = 0, imr_reg = 0, imr_val; + u32 int_valid; + u32 gpio_irq, mask = 0xFFFFFFFF; + struct gpio_port *port; + + port = (struct gpio_port *)get_irq_data(irq); + isr_reg = port->base + GPIO_ISR; + imr_reg = port->base + GPIO_IMR; + +#ifdef MXC_GPIO_SPLIT_IRQ_2 + if (irq == port->irq_0_15) { + mask = 0x0000FFFF; + } else { + mask = 0xFFFF0000; + } +#endif + + imr_val = __raw_readl(imr_reg) & mask; + int_valid = __raw_readl(isr_reg) & imr_val; + + if (unlikely(!int_valid)) { + return; + } + + gpio_irq = port->virtual_irq_start; + for (; int_valid != 0; int_valid >>= 1, gpio_irq++) { + struct irq_desc *d; + + if ((int_valid & 1) == 0) + continue; + d = irq_desc + gpio_irq; + if (unlikely(!(d->handle_irq))) { + printk(KERN_ERR "\nGPIO port: %d irq: %d unhandeled\n", + port->num, gpio_irq); + BUG(); /* oops */ + } + d->handle_irq(gpio_irq, d); + } +} + +#ifdef MXC_MUX_GPIO_INTERRUPTS +static void mxc_gpio_mux_irq_handler(u32 irq, struct irq_desc *desc) +{ + int i; + u32 isr_reg = 0, imr_reg = 0, imr_val; + u32 int_valid; + struct gpio_port *port; + + for (i = 0; i < GPIO_PORT_NUM; i++) { + port = &gpio_port[i]; + isr_reg = port->base + GPIO_ISR; + imr_reg = port->base + GPIO_IMR; + + imr_val = __raw_readl(imr_reg); + int_valid = __raw_readl(isr_reg) & imr_val; + + if (int_valid) { + set_irq_data(irq, (void *)port); + mxc_gpio_irq_handler(irq, desc); + } + } +} +#endif + +/* + * Disable a gpio pin's interrupt by setting the bit in the imr. + * @param irq a gpio virtual irq number + */ +static void gpio_mask_irq(u32 irq) +{ + u32 gpio = MXC_IRQ_TO_GPIO(irq); + struct gpio_port *port = get_gpio_port(gpio); + + _set_gpio_irqenable(port, GPIO_TO_INDEX(gpio), 0); +} + +/* + * Acknowledge a gpio pin's interrupt by clearing the bit in the isr. + * If the GPIO interrupt is level triggered, it also disables the interrupt. + * @param irq a gpio virtual irq number + */ +static void gpio_ack_irq(u32 irq) +{ + u32 gpio = MXC_IRQ_TO_GPIO(irq); + u32 index = GPIO_TO_INDEX(gpio); + struct gpio_port *port = get_gpio_port(gpio); + + _clear_gpio_irqstatus(port, GPIO_TO_INDEX(gpio)); + if (port->irq_is_level_map & (1 << index)) { + gpio_mask_irq(irq); + } +} + +/* + * Enable a gpio pin's interrupt by clearing the bit in the imr. + * @param irq a gpio virtual irq number + */ +static void gpio_unmask_irq(u32 irq) +{ + u32 gpio = MXC_IRQ_TO_GPIO(irq); + struct gpio_port *port = get_gpio_port(gpio); + + _set_gpio_irqenable(port, GPIO_TO_INDEX(gpio), 1); +} + +/* + * Enable a gpio pin's interrupt by clearing the bit in the imr. + * @param irq a gpio virtual irq number + */ +static int gpio_set_irq_type(u32 irq, u32 type) +{ + u32 gpio = MXC_IRQ_TO_GPIO(irq); + struct gpio_port *port = get_gpio_port(gpio); + + switch (type) { + case IRQT_RISING: + _set_gpio_edge_ctrl(port, GPIO_TO_INDEX(gpio), + GPIO_INT_RISE_EDGE); + set_irq_handler(irq, handle_edge_irq); + port->irq_is_level_map &= ~(1 << GPIO_TO_INDEX(gpio)); + break; + case IRQT_FALLING: + _set_gpio_edge_ctrl(port, GPIO_TO_INDEX(gpio), + GPIO_INT_FALL_EDGE); + set_irq_handler(irq, handle_edge_irq); + port->irq_is_level_map &= ~(1 << GPIO_TO_INDEX(gpio)); + break; + case IRQT_LOW: + _set_gpio_edge_ctrl(port, GPIO_TO_INDEX(gpio), + GPIO_INT_LOW_LEV); + set_irq_handler(irq, handle_level_irq); + port->irq_is_level_map |= 1 << GPIO_TO_INDEX(gpio); + break; + case IRQT_HIGH: + _set_gpio_edge_ctrl(port, GPIO_TO_INDEX(gpio), + GPIO_INT_HIGH_LEV); + set_irq_handler(irq, handle_level_irq); + port->irq_is_level_map |= 1 << GPIO_TO_INDEX(gpio); + break; + case IRQT_BOTHEDGE: + default: + return -EINVAL; + break; + } + return 0; +} + +/* + * Set interrupt number "irq" in the GPIO as a wake-up source. + * While system is running all registered GPIO interrupts need to have + * wake-up enabled. When system is suspended, only selected GPIO interrupts + * need to have wake-up enabled. + * @param irq interrupt source number + * @param enable enable as wake-up if equal to non-zero + * @return This function returns 0 on success. + */ +static int gpio_set_wake_irq(u32 irq, u32 enable) +{ + u32 gpio = MXC_IRQ_TO_GPIO(irq); + u32 gpio_idx = GPIO_TO_INDEX(gpio); + struct gpio_port *port = get_gpio_port(gpio); + + if (check_gpio(gpio) < 0) + return -ENODEV; + + if (enable) { + port->suspend_wakeup |= (1 << gpio_idx); +#ifdef MXC_GPIO_SPLIT_IRQ_2 + if (gpio_idx < 16) + enable_irq_wake(port->irq_0_15); + else + enable_irq_wake(port->irq_16_31); +#else + enable_irq_wake(port->irq); +#endif + } else { + port->suspend_wakeup &= ~(1 << gpio_idx); +#ifdef MXC_GPIO_SPLIT_IRQ_2 + if (gpio_idx < 16) + disable_irq_wake(port->irq_0_15); + else + disable_irq_wake(port->irq_16_31); +#else + disable_irq_wake(port->irq); +#endif + } + return 0; +} + +static struct irq_chip gpio_irq_chip = { + .name = "MXC_GPIO", + .ack = gpio_ack_irq, + .mask = gpio_mask_irq, + .unmask = gpio_unmask_irq, + .set_type = gpio_set_irq_type, + .set_wake = gpio_set_wake_irq, +}; + +/*! + * This function initializes the GPIO hardware and disables all the + * interrupts. It registers functions for core interrupt handling code, + * for irq-chip based architectures for each interrupt source. + */ +static int __init _mxc_gpio_init(void) +{ + int i; + struct gpio_port *port; + + printk(KERN_INFO "MXC GPIO hardware\n"); + + for (i = 0; i < GPIO_PORT_NUM; i++) { + int j, gpio_count = GPIO_NUM_PIN; + + port = &gpio_port[i]; + port->base = mxc_gpio_ports[i].base; + port->num = mxc_gpio_ports[i].num; +#ifdef MXC_GPIO_SPLIT_IRQ_2 + port->irq_0_15 = mxc_gpio_ports[i].irq_0_15; + port->irq_16_31 = mxc_gpio_ports[i].irq_16_31; +#else + port->irq = mxc_gpio_ports[i].irq; +#endif + port->virtual_irq_start = mxc_gpio_ports[i].virtual_irq_start; + + port->reserved_map = 0; + spin_lock_init(&port->lock); + + /* disable the interrupt and clear the status */ + __raw_writel(0, port->base + GPIO_IMR); + __raw_writel(0xFFFFFFFF, port->base + GPIO_ISR); + for (j = port->virtual_irq_start; + j < port->virtual_irq_start + gpio_count; j++) { + set_irq_chip(j, &gpio_irq_chip); + set_irq_handler(j, handle_edge_irq); + set_irq_flags(j, IRQF_VALID); + } +#ifndef MXC_MUX_GPIO_INTERRUPTS +#ifdef MXC_GPIO_SPLIT_IRQ_2 + set_irq_chained_handler(port->irq_0_15, mxc_gpio_irq_handler); + set_irq_data(port->irq_0_15, port); + set_irq_chained_handler(port->irq_16_31, mxc_gpio_irq_handler); + set_irq_data(port->irq_16_31, port); +#else + set_irq_chained_handler(port->irq, mxc_gpio_irq_handler); + set_irq_data(port->irq, port); +#endif +#endif + } + +#ifdef MXC_MUX_GPIO_INTERRUPTS + set_irq_chained_handler(port->irq, mxc_gpio_mux_irq_handler); + set_irq_data(mxc_gpio_ports[0].irq, gpio_port); +#endif + + return 0; +} + +#ifdef CONFIG_PM +/*! + * This function puts the GPIO in low-power mode/state. + * All the interrupts that are enabled are first saved. + * Only those interrupts which registers as a wake source by calling + * enable_irq_wake are enabled. All other interrupts are disabled. + * + * @param dev the system device structure used to give information + * on GPIO to suspend + * @param mesg the power state the device is entering + * + * @return The function always returns 0. + */ +static int mxc_gpio_suspend(struct sys_device *dev, pm_message_t mesg) +{ + int i; + + for (i = 0; i < GPIO_PORT_NUM; i++) { + struct gpio_port *port = &gpio_port[i]; + u32 isr_reg; + u32 imr_reg; + + isr_reg = port->base + GPIO_ISR; + imr_reg = port->base + GPIO_IMR; + + if (__raw_readl(isr_reg) & port->suspend_wakeup) { + return -EPERM; + } + port->saved_wakeup = __raw_readl(imr_reg); + __raw_writel(port->suspend_wakeup, imr_reg); + } + + return 0; +} + +/*! + * This function brings the GPIO back from low-power state. + * All the interrupts enabled before suspension are re-enabled from + * the saved information. + * + * @param dev the system device structure used to give information + * on GPIO to resume + * + * @return The function always returns 0. + */ +static int mxc_gpio_resume(struct sys_device *dev) +{ + int i; + + for (i = 0; i < GPIO_PORT_NUM; i++) { + struct gpio_port *port = &gpio_port[i]; + u32 isr_reg; + u32 imr_reg; + + isr_reg = port->base + GPIO_ISR; + imr_reg = port->base + GPIO_IMR; + + __raw_writel(port->saved_wakeup, imr_reg); + } + + return 0; +} +#else +#define mxc_gpio_suspend NULL +#define mxc_gpio_resume NULL +#endif /* CONFIG_PM */ + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct sysdev_class mxc_gpio_sysclass = { + .name = "mxc_gpio", + .suspend = mxc_gpio_suspend, + .resume = mxc_gpio_resume, +}; + +/*! + * This structure represents GPIO as a system device. + * System devices follow a slightly different driver model. + * They don't need to do dynammic driver binding, can't be probed, + * and don't reside on any type of peripheral bus. + * So, it is represented and treated a little differently. + */ +static struct sys_device mxc_gpio_device = { + .id = 0, + .cls = &mxc_gpio_sysclass, +}; + +/*! + * This function registers GPIO hardware as a system device and + * intializes all the GPIO ports if not already done. + * System devices will only be suspended with interrupts disabled, and + * after all other devices have been suspended. On resume, they will be + * resumed before any other devices, and also with interrupts disabled. + * This may get called early from board specific init + * + * @return This function returns 0 on success. + */ +int __init mxc_gpio_init(void) +{ + int ret = 0; + + ret = _mxc_gpio_init(); + + if (ret == 0) { + ret = sysdev_class_register(&mxc_gpio_sysclass); + if (ret == 0) + ret = sysdev_register(&mxc_gpio_device); + } + + return ret; +} + +/* + * FIXME: The following functions are for backward-compatible. + * They will be removed at a future release. + */ +#define PORT_SIG_TO_GPIO(p, s) (p * 32 + s) + +/*! + * This function configures the GPIO signal to be either input or output. For + * input signals used for generating interrupts for the ARM core, how the + * interrupts being triggered is also passed in via \a icr. For output signals, + * the \a icr value doesn't matter. + * FIXED ME: for backward compatible. to be removed! + * + * @param port specified port with 0-GPIO port 1; 1-GPIO port 2 + * @param sig_no specified GPIO signal (0 based) + * @param out #true for output, #false for input + * @param icr value defined in \b #gpio_edge_t + */ +void gpio_config(u32 port, u32 sig_no, bool out, gpio_edge_t icr) +{ + u32 gpio = PORT_SIG_TO_GPIO(port, sig_no); + struct gpio_port *port_p; + + if (check_gpio(gpio) < 0) + return; + + port_p = get_gpio_port(gpio); + + if (!(port_p->reserved_map & (1 << sig_no))) + _request_gpio(port_p, sig_no); + + if (!out) { + /* input */ + _set_gpio_direction(port_p, sig_no, 1); + _set_gpio_edge_ctrl(port_p, sig_no, icr); + } else { /* output */ + _set_gpio_direction(port_p, sig_no, 0); + } +} + +/*! + * This function sets a GPIO signal value. + * FIXED ME: for backward compatible. to be removed! + * + * @param port specified port with 0 for GPIO port 1 and 1 for GPIO port 2 + * @param sig_no specified GPIO signal (0 based) + * @param data value to be set (only 0 or 1 is valid) + */ +void gpio_set_data(u32 port, u32 sig_no, u32 data) +{ + u32 gpio = PORT_SIG_TO_GPIO(port, sig_no); + struct gpio_port *port_p; + + if (check_gpio(gpio) < 0) + return; + + port_p = get_gpio_port(gpio); + + if (!(port_p->reserved_map & (1 << sig_no))) + _request_gpio(port_p, sig_no); + + spin_lock(&port_p->lock); + _set_gpio_dataout(port_p, sig_no, (data == 0) ? 0 : 1); + spin_unlock(&port_p->lock); +} + +/*! + * This function returns the value of the GPIO signal. + * FIXED ME: for backward compatible. to be removed! + * + * @param port specified port with 0 for GPIO port 1 and 1 for GPIO port 2 + * @param sig_no specified GPIO signal (0 based) + * + * @return Value of the GPIO signal + */ +u32 gpio_get_data(u32 port, u32 sig_no) +{ + u32 gpio = PORT_SIG_TO_GPIO(port, sig_no); + struct gpio_port *port_p; + + if (check_gpio(gpio) < 0) + BUG(); + + port_p = get_gpio_port(gpio); + + if (!(port_p->reserved_map & (1 << sig_no))) + _request_gpio(port_p, sig_no); + + return (__raw_readl(port_p->base + GPIO_DR) >> sig_no) & 1; +} + +/*! + * This function clears the GPIO interrupt for a signal on a port. + * FIXED ME: for backward compatible. to be removed! + * + * @param port specified port with 0 for GPIO port 1 and 1 for GPIO port 2 + * @param sig_no specified GPIO signal (0 based) to clear + */ +void gpio_clear_int(u32 port, u32 sig_no) +{ + u32 gpio = PORT_SIG_TO_GPIO(port, sig_no); + struct gpio_port *port_p; + + if (check_gpio(gpio) < 0) + return; + + port_p = get_gpio_port(gpio); + + if (!(port_p->reserved_map & (1 << sig_no))) + _request_gpio(port_p, sig_no); + + _clear_gpio_irqstatus(port_p, sig_no); +} + +/*! + * This function is responsible for registering a GPIO signal's ISR. + * FIXED ME: for backward compatible. to be removed! + * + * @param port specified port with 0 for GPIO port 1 and 1 for GPIO port 2 + * @param sig_no specified GPIO signal (0 based) + * @param prio priority as defined in \b enum \b #gpio_prio + * @param handler GPIO ISR function pointer for the GPIO signal + * @param irq_flags irq flags (not used) + * @param devname device name associated with the interrupt + * @param dev_id some unique information for the ISR + * + * @return 0 if successful; non-zero otherwise. + */ +int gpio_request_irq(u32 port, u32 sig_no, enum gpio_prio prio, + gpio_irq_handler handler, u32 irq_flags, + const char *devname, void *dev_id) +{ + u32 gpio = PORT_SIG_TO_GPIO(port, sig_no), ret; + struct gpio_port *port_p; + + if (check_gpio(gpio) < 0) + return -1; + + port_p = get_gpio_port(gpio); + + if (!(port_p->reserved_map & (1 << sig_no))) + _request_gpio(port_p, sig_no); + + ret = request_irq(MXC_GPIO_TO_IRQ(gpio), handler, 0, "gpio", dev_id); + if (ret) { + printk(KERN_ERR "gpio: IRQ%d already in use.\n", + MXC_GPIO_TO_IRQ(gpio)); + return ret; + } + return 0; +} + +/*! + * This function un-registers an ISR with the GPIO interrupt module. + * FIXED ME: for backward compatible. to be removed! + * + * @param port specified port with 0 for GPIO port 1 and 1 for GPIO port 2 + * @param sig_no specified GPIO signal (0 based) + * @param prio priority as defined in \b enum \b #gpio_prio + */ +void gpio_free_irq(u32 port, u32 sig_no, enum gpio_prio prio) +{ + u32 gpio = PORT_SIG_TO_GPIO(port, sig_no); + struct gpio_port *port_p; + + if (check_gpio(gpio) < 0) + return; + + port_p = get_gpio_port(gpio); + + free_irq(MXC_GPIO_TO_IRQ(gpio), NULL); + + spin_lock(&port_p->lock); + if ((!(port_p->reserved_map & (1 << sig_no)))) { + printk(KERN_ERR "GPIO port %d, pin %d wasn't reserved!\n", + port_p->num, sig_no); + spin_unlock(&port_p->lock); + return; + } + port_p->reserved_map &= ~(1 << sig_no); + _set_gpio_direction(port_p, sig_no, 1); + _set_gpio_irqenable(port_p, sig_no, 0); + _clear_gpio_irqstatus(port_p, sig_no); + spin_unlock(&port_p->lock); +} + +EXPORT_SYMBOL(mxc_request_gpio); +EXPORT_SYMBOL(mxc_free_gpio); +EXPORT_SYMBOL(mxc_set_gpio_direction); +EXPORT_SYMBOL(mxc_set_gpio_dataout); +EXPORT_SYMBOL(mxc_get_gpio_datain); + +/* For backward compatible */ +EXPORT_SYMBOL(gpio_config); +EXPORT_SYMBOL(gpio_set_data); +EXPORT_SYMBOL(gpio_get_data); +EXPORT_SYMBOL(gpio_clear_int); +EXPORT_SYMBOL(gpio_request_irq); +EXPORT_SYMBOL(gpio_free_irq); diff -urN linux-2.6.26/arch/arm/plat-mxc/io.c linux-2.6.26-lab126/arch/arm/plat-mxc/io.c --- linux-2.6.26/arch/arm/plat-mxc/io.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/io.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,41 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * mxc custom ioremap implementation. + */ + +#include +#include +#include +#include + +void *__iomem __mxc_ioremap(unsigned long cookie, size_t size, + unsigned int mtype) +{ + if (mtype == MT_DEVICE && IS_MEM_DEVICE_NONSHARED(cookie)) { + mtype = MT_DEVICE_NONSHARED; + } + return __arm_ioremap(cookie, size, mtype); +} + +EXPORT_SYMBOL(__mxc_ioremap); + +void __mxc_iounmap(void __iomem * addr) +{ + extern void __iounmap(volatile void __iomem * addr); + + __iounmap(addr); +} + +EXPORT_SYMBOL(__mxc_iounmap); diff -urN linux-2.6.26/arch/arm/plat-mxc/irq.c linux-2.6.26-lab126/arch/arm/plat-mxc/irq.c --- linux-2.6.26/arch/arm/plat-mxc/irq.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/irq.c 2010-08-10 04:14:11.000000000 -0400 @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -19,6 +20,103 @@ #include #include +#define IRQ_BIT(irq) (1 << (irq)) + +static uint32_t saved_wakeup_low, saved_wakeup_high; +static uint32_t suspend_wakeup_low, suspend_wakeup_high; + +/* + ***************************************** + * EDIO Registers * + ***************************************** + */ +#ifdef EDIO_BASE_ADDR + +static const int mxc_edio_irq_map[] = { + MXC_INT_EXT_INT0, + MXC_INT_EXT_INT1, + MXC_INT_EXT_INT2, + MXC_INT_EXT_INT3, + MXC_INT_EXT_INT4, + MXC_INT_EXT_INT5, + MXC_INT_EXT_INT6, + MXC_INT_EXT_INT7, +}; + +static u32 edio_irq_type[MXC_MAX_EXT_LINES] = { + IRQT_LOW, + IRQT_LOW, + IRQT_LOW, + IRQT_LOW, + IRQT_LOW, + IRQT_LOW, + IRQT_LOW, + IRQT_LOW, +}; + +static int irq_to_edio(int irq) +{ + int i; + int edio = -1; + + for (i = 0; i < MXC_MAX_EXT_LINES; i++) { + if (mxc_edio_irq_map[i] == irq) { + edio = i; + break; + } + } + return edio; +} + +static void mxc_irq_set_edio_level(int irq, int trigger) +{ + int edio; + unsigned short rval; + + edio = irq_to_edio(irq); + rval = __raw_readw(EDIO_EPPAR); + rval = (rval & (~(0x3 << (edio * 2)))) | (trigger << (edio * 2)); + __raw_writew(rval, EDIO_EPPAR); +} + +static void mxc_irq_set_edio_dir(int irq, int dir) +{ + int edio; + unsigned short rval; + + edio = irq_to_edio(irq); + + rval = __raw_readw(EDIO_EPDR); + rval &= ~(1 << edio); + rval |= (0 << edio); + __raw_writew(rval, (EDIO_EPDR)); + + /* set direction */ + rval = __raw_readw(EDIO_EPDDR); + + if (dir) + /* out */ + rval |= (1 << edio); + else + /* in */ + rval &= ~(1 << edio); + + __raw_writew(rval, EDIO_EPDDR); + +} + +/* + * Allows tuning the IRQ type , trigger and priority + */ +static void mxc_irq_set_edio(int irq, int fiq, int priority, int trigger) +{ + + mxc_irq_set_edio_dir(irq, 0); + /* set level */ + mxc_irq_set_edio_level(irq, trigger); +} +#endif + /* Disable interrupt number "irq" in the AVIC */ static void mxc_mask_irq(unsigned int irq) { @@ -31,12 +129,212 @@ __raw_writel(irq, AVIC_INTENNUM); } +#ifdef CONFIG_FIQ +int imx_set_irq_fiq(unsigned int irq, unsigned int type) +{ + unsigned int irqt; + + if (irq >= NR_IRQS) + return -EINVAL; + + if (irq < NR_IRQS / 2) { + irqt = __raw_readl(AVIC_INTENABLEL) & ~(1 << irq); + __raw_writel(irqt | (!!type << irq), AVIC_INTENABLEL); + } else { + irq -= NR_IRQS / 2; + irqt = __raw_readl(AVIC_INTENABLEH) & ~(1 << irq); + __raw_writel(irqt | (!!type << irq), AVIC_INTENABLEH); + } + + return 0; +} +EXPORT_SYMBOL(imx_set_irq_fiq); +#endif /* CONFIG_FIQ */ + +/*! + * Set interrupt number "irq" in the AVIC as a wake-up source. + * + * @param irq interrupt source number + * @param enable enable as wake-up if equal to non-zero + * disble as wake-up if equal to zero + * + * @return This function returns 0 on success. + */ +static int mxc_set_wake_irq(unsigned int irq, unsigned int enable) +{ + uint32_t *wakeup_intr; + uint32_t irq_bit; + + if (irq < 32) { + wakeup_intr = &suspend_wakeup_low; + irq_bit = IRQ_BIT(irq); + } else { + wakeup_intr = &suspend_wakeup_high; + irq_bit = IRQ_BIT(irq - 32); + } + + if (enable) { + *wakeup_intr |= irq_bit; + } else { + *wakeup_intr &= ~irq_bit; + } + + return 0; +} + static struct irq_chip mxc_avic_chip = { .mask_ack = mxc_mask_irq, .mask = mxc_mask_irq, .unmask = mxc_unmask_irq, + .set_wake = mxc_set_wake_irq, }; +#ifdef EDIO_BASE_ADDR +static void mxc_ack_edio(u32 irq) +{ + u16 edio = (u16) irq_to_edio(irq); + if (edio_irq_type[edio] == IRQT_LOW) { + /* Mask interrupt for level sensitive */ + mxc_mask_irq(irq); + } else if (edio_irq_type[edio] == IRQT_HIGH) { + /* clear edio interrupt */ + __raw_writew((1 << edio), EDIO_EPFR); + /* dummy read for edio workaround */ + __raw_readw(EDIO_EPFR); + /* Mask interrupt for level sensitive */ + mxc_mask_irq(irq); + } else { + /* clear edio interrupt */ + __raw_writew((1 << edio), EDIO_EPFR); + /* dummy read for edio workaround */ + __raw_readw(EDIO_EPFR); + } +} + +static int mxc_edio_set_type(u32 irq, u32 type) +{ + edio_irq_type[irq_to_edio(irq)] = type; + + switch (type) { + case IRQT_RISING: + mxc_irq_set_edio_level(irq, 1); + set_irq_handler(irq, handle_edge_irq); + break; + case IRQT_FALLING: + mxc_irq_set_edio_level(irq, 2); + set_irq_handler(irq, handle_edge_irq); + break; + case IRQT_BOTHEDGE: + mxc_irq_set_edio_level(irq, 3); + set_irq_handler(irq, handle_edge_irq); + break; + case IRQT_LOW: + mxc_irq_set_edio_level(irq, 0); + set_irq_handler(irq, handle_level_irq); + break; + case IRQT_HIGH: + /* EDIO doesn't really support high-level interrupts, + * so we're faking it + */ + mxc_irq_set_edio_level(irq, 1); + set_irq_handler(irq, handle_level_irq); + break; + default: + return -EINVAL; + break; + } + return 0; +} + +static struct irq_chip mxc_edio_chip = { + .name = "MXC_EDIO", + .ack = mxc_ack_edio, + .mask = mxc_mask_irq, + .unmask = mxc_unmask_irq, + .set_type = mxc_edio_set_type, + .set_wake = mxc_set_wake_irq, +}; + +#endif + +#ifdef CONFIG_PM +/*! + * This function puts the AVIC in low-power mode/state. + * All the interrupts that are enabled are first saved. + * Only those interrupts which registers as a wake source by calling + * enable_irq_wake are enabled. All other interrupts are disabled. + * + * @param dev the system device structure used to give information + * on AVIC to suspend + * @param mesg the power state the device is entering + * + * @return The function always returns 0. + */ +static int mxc_avic_suspend(struct sys_device *dev, pm_message_t mesg) +{ + saved_wakeup_high = __raw_readl(AVIC_INTENABLEH); + saved_wakeup_low = __raw_readl(AVIC_INTENABLEL); + + __raw_writel(suspend_wakeup_high, AVIC_INTENABLEH); + __raw_writel(suspend_wakeup_low, AVIC_INTENABLEL); + + return 0; +} + +/*! + * This function brings the AVIC back from low-power state. + * All the interrupts enabled before suspension are re-enabled from + * the saved information. + * + * @param dev the system device structure used to give information + * on AVIC to resume + * + * @return The function always returns 0. + */ +static int mxc_avic_resume(struct sys_device *dev) +{ + __raw_writel(saved_wakeup_high, AVIC_INTENABLEH); + __raw_writel(saved_wakeup_low, AVIC_INTENABLEL); + + return 0; +} + +#else +#define mxc_avic_suspend NULL +#define mxc_avic_resume NULL +#endif /* CONFIG_PM */ + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct sysdev_class mxc_avic_sysclass = { + .name = "mxc_irq", + .suspend = mxc_avic_suspend, + .resume = mxc_avic_resume, +}; + +/*! + * This structure represents AVIC as a system device. + * System devices follow a slightly different driver model. + * They don't need to do dynammic driver binding, can't be probed, + * and don't reside on any type of peripheral bus. + * So, it is represented and treated a little differently. + */ +static struct sys_device mxc_avic_device = { + .id = 0, + .cls = &mxc_avic_sysclass, +}; + +/* + * This function is used to get the AVIC Lo and Hi interrupts + * that are enabled as wake up sources to wake up the core from suspend + */ +void mxc_get_wake_irq(u32 * wake_src[]) +{ + *wake_src[0] = __raw_readl(AVIC_INTENABLEL); + *wake_src[1] = __raw_readl(AVIC_INTENABLEH); +} + /* * This function initializes the AVIC hardware and disables all the * interrupts. It registers the interrupt enable and disable functions @@ -46,6 +344,7 @@ { int i; u32 reg; + static int initialized; /* put the AVIC into the reset value with * all interrupts disabled @@ -60,16 +359,66 @@ /* all IRQ no FIQ */ __raw_writel(0, AVIC_INTTYPEH); __raw_writel(0, AVIC_INTTYPEL); - for (i = 0; i < MXC_MAX_INT_LINES; i++) { - set_irq_chip(i, &mxc_avic_chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID); + if (!initialized) { + for (i = 0; i < MXC_MAX_INT_LINES; i++) { +#ifdef EDIO_BASE_ADDR + if (irq_to_edio(i) != -1) { + mxc_irq_set_edio(i, 0, 0, 0); + set_irq_chip(i, &mxc_edio_chip); + } else +#endif + { + set_irq_chip(i, &mxc_avic_chip); + } + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } } - /* Set WDOG2's interrupt the highest priority level (bit 28-31) */ reg = __raw_readl(AVIC_NIPRIORITY6); reg |= (0xF << 28); __raw_writel(reg, AVIC_NIPRIORITY6); + /* + * Make the SDMA IRQ as a higher priority IRQ + */ + reg = __raw_readl(AVIC_NIPRIORITY4); + reg |= (0xF << 8); + __raw_writel(reg, AVIC_NIPRIORITY4); + + if (MXC_INT_FORCE >= 32) + __raw_writel(1 << (MXC_INT_FORCE & 31), AVIC_INTFRCH); + else if (MXC_INT_FORCE >= 0) + __raw_writel(1 << MXC_INT_FORCE, AVIC_INTFRCL); + + initialized = 1; + +#ifdef CONFIG_FIQ + /* Initialize FIQ */ + init_FIQ(); +#endif + printk(KERN_INFO "MXC IRQ initialized\n"); } + +/*! + * This function registers AVIC hardware as a system device. + * System devices will only be suspended with interrupts disabled, and + * after all other devices have been suspended. On resume, they will be + * resumed before any other devices, and also with interrupts disabled. + * + * @return This function returns 0 on success. + */ +static int __init mxc_avic_sysinit(void) +{ + int ret = 0; + + ret = sysdev_class_register(&mxc_avic_sysclass); + if (ret == 0) { + ret = sysdev_register(&mxc_avic_device); + } + + return ret; +} + +arch_initcall(mxc_avic_sysinit); diff -urN linux-2.6.26/arch/arm/plat-mxc/isp1301xc.c linux-2.6.26-lab126/arch/arm/plat-mxc/isp1301xc.c --- linux-2.6.26/arch/arm/plat-mxc/isp1301xc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/isp1301xc.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,290 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * ISP1301 register addresses,all register of ISP1301 + * is one-byte length register + */ + +/* ISP1301: I2C device address */ +#define ISP1301_DEV_ADDR 0x2D + +/* ISP 1301 register set*/ +#define ISP1301_MODE_REG1_SET 0x04 +#define ISP1301_MODE_REG1_CLR 0x05 + +#define ISP1301_CTRL_REG1_SET 0x06 +#define ISP1301_CTRL_REG1_CLR 0x07 + +#define ISP1301_INT_SRC_REG 0x08 +#define ISP1301_INT_LAT_REG_SET 0x0a +#define ISP1301_INT_LAT_REG_CLR 0x0b +#define ISP1301_INT_FALSE_REG_SET 0x0c +#define ISP1301_INT_FALSE_REG_CLR 0x0d +#define ISP1301_INT_TRUE_REG_SET 0x0e +#define ISP1301_INT_TRUE_REG_CLR 0x0f + +#define ISP1301_CTRL_REG2_SET 0x10 +#define ISP1301_CTRL_REG2_CLR 0x11 + +#define ISP1301_MODE_REG2_SET 0x12 +#define ISP1301_MODE_REG2_CLR 0x13 + +#define ISP1301_BCD_DEV_REG0 0x14 +#define ISP1301_BCD_DEV_REG1 0x15 + +/* OTG Control register bit description */ +#define DP_PULLUP 0x01 +#define DM_PULLUP 0x02 +#define DP_PULLDOWN 0x04 +#define DM_PULLDOWN 0x08 +#define ID_PULLDOWN 0x10 +#define VBUS_DRV 0x20 +#define VBUS_DISCHRG 0x40 +#define VBUS_CHRG 0x80 + +/* Mode Control 1 register bit description */ +#define SPEED_REG 0x01 +#define SUSPEND_REG 0x02 +#define DAT_SE0 0x04 +#define TRANSP_EN 0x08 +#define BDIS_ACON_EN 0x10 +#define OE_INT_EN 0x20 +#define UART_EN 0x40 + +/* Mode Control 2 register bit description */ +#define SPD_SUSP_CTRL 0x02 +#define BI_DI 0x04 + +static int isp1301_attach(struct i2c_adapter *adapter); +static int isp1301_detach(struct i2c_client *client); + +static struct i2c_driver isp1301_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "isp1301 Client", + }, + .attach_adapter = isp1301_attach, + .detach_client = isp1301_detach, +}; + +static struct i2c_client isp1301_i2c_client = { + .name = "isp1301 I2C dev", + .addr = ISP1301_DEV_ADDR, + .driver = &isp1301_i2c_driver, +}; + +static unsigned short normal_i2c[] = { ISP1301_DEV_ADDR, I2C_CLIENT_END }; + +/* Magic definition of all other variables and things */ +I2C_CLIENT_INSMOD; + +static int isp1301_detect_client(struct i2c_adapter *adapter, int address, + int kind) +{ + isp1301_i2c_client.adapter = adapter; + if (i2c_attach_client(&isp1301_i2c_client)) { + isp1301_i2c_client.adapter = NULL; + printk(KERN_ERR "isp1301_attach: i2c_attach_client failed\n"); + return -1; + } + + printk(KERN_INFO "isp1301 Detected\n"); + return 0; +} + +/*! + * isp1301 I2C attach function + * + * @param adapter struct i2c_adapter * + * @return Error code indicating success or failure + */ +static int isp1301_attach(struct i2c_adapter *adapter) +{ + return i2c_probe(adapter, &addr_data, &isp1301_detect_client); +} + +/*! + * isp1301 I2C detach function + * + * @param client struct i2c_client * + * @return Error code indicating success or failure + */ +static int isp1301_detach(struct i2c_client *client) +{ + int err; + + if (!isp1301_i2c_client.adapter) + return -1; + + err = i2c_detach_client(&isp1301_i2c_client); + isp1301_i2c_client.adapter = NULL; + + return err; +} + +static void isp1301_init(struct fsl_xcvr_ops *this) +{ + pr_debug("%s\n", __FUNCTION__); + + i2c_add_driver(&isp1301_i2c_driver); +} + +static void isp1301_uninit(struct fsl_xcvr_ops *this) +{ + // DDD do this for host only: + /* disable OTG VBUS */ + i2c_del_driver(&isp1301_i2c_driver); +} + +/* Write ISP1301 register*/ +static inline void isp1301_write_reg(char reg, char data) +{ + i2c_smbus_write_byte_data(&isp1301_i2c_client, reg, data); +} + +/* read ISP1301 register*/ +static inline char isp1301_read_reg(char reg) +{ + return i2c_smbus_read_byte_data(&isp1301_i2c_client, reg); +} + +/* set ISP1301 as USB host*/ +static inline void isp1301_set_serial_host(void) +{ + pr_debug("%s\n", __FUNCTION__); + + isp1301_write_reg(ISP1301_MODE_REG2_CLR, 0xFF); +#if defined(CONFIG_MXC_USB_SB3) || defined(CONFIG_MXC_USB_DB4) + isp1301_write_reg(ISP1301_MODE_REG2_SET, SPD_SUSP_CTRL | BI_DI); +#else + isp1301_write_reg(ISP1301_MODE_REG2_SET, SPD_SUSP_CTRL); +#endif + + isp1301_write_reg(ISP1301_MODE_REG1_CLR, 0xFF); +#if defined(CONFIG_MXC_USB_SB3) || defined(CONFIG_MXC_USB_SU6) + isp1301_write_reg(ISP1301_MODE_REG1_SET, DAT_SE0 | SPEED_REG); +#else + isp1301_write_reg(ISP1301_MODE_REG1_SET, SPEED_REG); +#endif + + /* configure transceiver for host mode */ + isp1301_write_reg(ISP1301_CTRL_REG1_SET, + (VBUS_DRV | DP_PULLDOWN | DM_PULLDOWN)); +} + +/* set ISP1301 as USB device */ +static inline void isp1301_set_serial_dev(void) +{ + pr_debug("%s\n", __FUNCTION__); + + isp1301_write_reg(ISP1301_MODE_REG2_CLR, 0xFF); +#if defined(CONFIG_MXC_USB_SB3) || defined(CONFIG_MXC_USB_DB4) + isp1301_write_reg(ISP1301_MODE_REG2_SET, SPD_SUSP_CTRL | BI_DI); +#else + isp1301_write_reg(ISP1301_MODE_REG2_SET, SPD_SUSP_CTRL); +#endif + + isp1301_write_reg(ISP1301_MODE_REG1_CLR, 0xFF); +#if defined(CONFIG_MXC_USB_SB3) || defined(CONFIG_MXC_USB_SU6) + isp1301_write_reg(ISP1301_MODE_REG1_SET, DAT_SE0 | SPEED_REG); +#else + isp1301_write_reg(ISP1301_MODE_REG1_SET, SPEED_REG); +#endif + + /* FS mode, DP pull down, DM pull down */ + isp1301_write_reg(ISP1301_CTRL_REG1_SET, + (DP_PULLDOWN | DM_PULLDOWN | DP_PULLUP)); +} + +static void isp1301_set_vbus_power(struct fsl_xcvr_ops *this, + struct fsl_usb2_platform_data *pdata, int on) +{ + pr_debug("%s(on=%d)\n", __FUNCTION__, on); + if (on) { + /* disable D+ pull-up */ + isp1301_write_reg(ISP1301_CTRL_REG1_CLR, DP_PULLUP); + /* enable D+ pull-down */ + isp1301_write_reg(ISP1301_CTRL_REG1_SET, DP_PULLDOWN); + /* turn on Vbus */ + isp1301_write_reg(ISP1301_CTRL_REG1_SET, VBUS_DRV); + } else { + /* D+ pull up, D- pull down */ + isp1301_write_reg(ISP1301_CTRL_REG1_SET, + (DP_PULLUP | DM_PULLDOWN)); + /* disable D- pull up, disable D+ pull down */ + isp1301_write_reg(ISP1301_CTRL_REG1_CLR, + (DM_PULLUP | DP_PULLDOWN)); + } +} + +/* + * Enable or disable the D+ pullup. + */ +static void isp1301_pullup(int on) +{ + pr_debug("%s(%d)\n", __func__, on); + + if (on) + isp1301_write_reg(ISP1301_CTRL_REG1_SET, DP_PULLUP); + else + isp1301_write_reg(ISP1301_CTRL_REG1_CLR, DP_PULLUP); +} + +static struct fsl_xcvr_ops isp1301_ops_otg = { + .name = "isp1301", + .xcvr_type = PORTSC_PTS_SERIAL, + .init = isp1301_init, + .uninit = isp1301_uninit, + .set_host = isp1301_set_serial_host, + .set_device = isp1301_set_serial_dev, + .set_vbus_power = isp1301_set_vbus_power, + .pullup = isp1301_pullup, +}; + +extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops); + +static int __init isp1301xc_init(void) +{ + pr_debug("%s\n", __FUNCTION__); + + fsl_usb_xcvr_register(&isp1301_ops_otg); + + return 0; +} + +extern void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops); + +static void __exit isp1301xc_exit(void) +{ + fsl_usb_xcvr_unregister(&isp1301_ops_otg); +} + +module_init(isp1301xc_init); +module_exit(isp1301xc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("isp1301"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/plat-mxc/isp1504xc.c linux-2.6.26-lab126/arch/arm/plat-mxc/isp1504xc.c --- linux-2.6.26/arch/arm/plat-mxc/isp1504xc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/isp1504xc.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,278 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* ISP 1504 register addresses */ +#define ISP1504_VID_LOW 0x00 /* Vendor ID low */ +#define ISP1504_VID_HIGH 0x01 /* Vendor ID high */ +#define ISP1504_PID_LOW 0x02 /* Product ID low */ +#define ISP1504_PID_HIGH 0x03 /* Product ID high */ +#define ISP1504_FUNC 0x04 /* Function Control */ +#define ISP1504_ITFCTL 0x07 /* Interface Control */ +#define ISP1504_OTGCTL 0x0A /* OTG Control */ + +/* add to above register address to access Set/Clear functions */ +#define ISP1504_REG_SET 0x01 +#define ISP1504_REG_CLEAR 0x02 + +/* 1504 OTG Control Register bits */ +#define USE_EXT_VBUS_IND (1 << 7) /* Use ext. Vbus indicator */ +#define DRV_VBUS_EXT (1 << 6) /* Drive Vbus external */ +#define DRV_VBUS (1 << 5) /* Drive Vbus */ +#define CHRG_VBUS (1 << 4) /* Charge Vbus */ +#define DISCHRG_VBUS (1 << 3) /* Discharge Vbus */ +#define DM_PULL_DOWN (1 << 2) /* enable DM Pull Down */ +#define DP_PULL_DOWN (1 << 1) /* enable DP Pull Down */ +#define ID_PULL_UP (1 << 0) /* enable ID Pull Up */ + +/* 1504 OTG Function Control Register bits */ +#define SUSPENDM (1 << 6) /* places the PHY into + low-power mode */ +#define DRV_RESET (1 << 5) /* Active HIGH transceiver + reset */ + +/*! + * read ULPI register 'reg' thru VIEWPORT register 'view' + * + * @param reg register to read + * @param view the ULPI VIEWPORT register address + * @return return isp1504 register value + */ +static u8 isp1504_read(int reg, volatile u32 *view) +{ + u32 data; + + /* make sure interface is running */ + if (!(__raw_readl(view) && ULPIVW_SS)) { + __raw_writel(ULPIVW_WU, view); + do { /* wait for wakeup */ + data = __raw_readl(view); + } while (data & ULPIVW_WU); + } + + /* read the register */ + __raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view); + + do { /* wait for completion */ + data = __raw_readl(view); + } while (data & ULPIVW_RUN); + + return (u8) (data >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK; +} + +/*! + * set bits into OTG ISP1504 register 'reg' thru VIEWPORT register 'view' + * + * @param bits set value + * @param reg which register + * @param view the ULPI VIEWPORT register address + */ +static void isp1504_set(u8 bits, int reg, volatile u32 *view) +{ + u32 data; + + /* make sure interface is running */ + if (!(__raw_readl(view) && ULPIVW_SS)) { + __raw_writel(ULPIVW_WU, view); + do { /* wait for wakeup */ + data = __raw_readl(view); + } while (data & ULPIVW_WU); + } + + __raw_writel((ULPIVW_RUN | ULPIVW_WRITE | + ((reg + ISP1504_REG_SET) << ULPIVW_ADDR_SHIFT) | + ((bits & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), + view); + + while (__raw_readl(view) & ULPIVW_RUN) /* wait for completion */ + continue; +} + +/*! + * clear bits in OTG ISP1504 register 'reg' thru VIEWPORT register 'view' + * + * @param bits bits to clear + * @param reg in this register + * @param view the ULPI VIEWPORT register address + */ +static void isp1504_clear(u8 bits, int reg, volatile u32 *view) +{ + __raw_writel((ULPIVW_RUN | ULPIVW_WRITE | + ((reg + ISP1504_REG_CLEAR) << ULPIVW_ADDR_SHIFT) | + ((bits & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), + view); + + while (__raw_readl(view) & ULPIVW_RUN) /* wait for completion */ + continue; +} + +extern int gpio_usbotg_hs_active(void); + +static void isp1508_fix(u32 *view) +{ + if (!machine_is_mx31_3ds()) + gpio_usbotg_hs_active(); + + /* Set bits IND_PASS_THRU and IND_COMPL */ + isp1504_set(0x60, ISP1504_ITFCTL, view); + + /* Set bit USE_EXT_VBUS_IND */ + isp1504_set(USE_EXT_VBUS_IND, ISP1504_OTGCTL, view); +} + +/*! + * set vbus power + * + * @param view viewport register + * @param on power on or off + */ +static void isp1504_set_vbus_power(struct fsl_xcvr_ops *this, + struct fsl_usb2_platform_data *pdata, int on) +{ + u32 *view = pdata->regs + ULPIVW_OFF; + + pr_debug("real %s(on=%d) view=0x%p\n", __FUNCTION__, on, view); + + pr_debug("ULPI Vendor ID 0x%x Product ID 0x%x\n", + (isp1504_read(ISP1504_VID_HIGH, view) << 8) | + isp1504_read(ISP1504_VID_LOW, view), + (isp1504_read(ISP1504_PID_HIGH, view) << 8) | + isp1504_read(ISP1504_PID_LOW, view)); + + pr_debug("OTG Control before=0x%x\n", + isp1504_read(ISP1504_OTGCTL, view)); + + if (on) { + isp1504_set(DRV_VBUS_EXT | /* enable external Vbus */ + DRV_VBUS | /* enable internal Vbus */ + USE_EXT_VBUS_IND | /* use external indicator */ + CHRG_VBUS, /* charge Vbus */ + ISP1504_OTGCTL, view); + + } else { + isp1508_fix(view); + + isp1504_clear(DRV_VBUS_EXT | /* disable external Vbus */ + DRV_VBUS, /* disable internal Vbus */ + ISP1504_OTGCTL, view); + + isp1504_set(USE_EXT_VBUS_IND | /* use external indicator */ + DISCHRG_VBUS, /* discharge Vbus */ + ISP1504_OTGCTL, view); + } + + pr_debug("OTG Control after = 0x%x\n", + isp1504_read(ISP1504_OTGCTL, view)); +} + +/*! + * set remote wakeup + * + * @param view viewport register + */ +static void isp1504_set_remote_wakeup(u32 * view) +{ + __raw_writel(~ULPIVW_WRITE & __raw_readl(view), view); + __raw_writel((1 << ULPIVW_PORT_SHIFT) | __raw_readl(view), view); + __raw_writel(ULPIVW_RUN | __raw_readl(view), view); + + while (__raw_readl(view) & ULPIVW_RUN) /* wait for completion */ + continue; +} + +static void isp1504_init(struct fsl_xcvr_ops *this) +{ + pr_debug("%s:\n", __FUNCTION__); +} + +static void isp1504_uninit(struct fsl_xcvr_ops *this) +{ + pr_debug("%s:\n", __FUNCTION__); +} + +static void isp1504_suspend(struct fsl_xcvr_ops *this) +{ + pr_debug("%s\n", __func__); + + /* send suspend command */ + isp1504_clear(SUSPENDM, ISP1504_FUNC, &UOG_ULPIVIEW); + pr_debug("%s.\n", __func__); +} + +/*! + * Set the 1504 transceiver to the proper mode for testing purposes. + * + * @param view the ULPI VIEWPORT register address + * @param test_mode Set the 1504 transceiver to disable bit stuffing and NRZI + */ + static void isp1504_set_test_mode(volatile u32 *view, enum usb_test_mode test_mode) +{ + if (test_mode == USB_TEST_J || test_mode == USB_TEST_K) { + printk(KERN_INFO "udc: disable bit stuffing and NRZI\n"); + /* Disable bit-stuffing and NRZI encoding. */ + isp1504_set(0x10, 0x04, view); + } +} + +static struct fsl_xcvr_ops isp1504_ops = { + .name = "isp1504", + .xcvr_type = PORTSC_PTS_ULPI, + .init = isp1504_init, + .uninit = isp1504_uninit, + .suspend = isp1504_suspend, + .set_vbus_power = isp1504_set_vbus_power, + .set_remote_wakeup = isp1504_set_remote_wakeup, + .set_test_mode = isp1504_set_test_mode, +}; + +extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops); +extern int fsl_usb_xcvr_suspend(struct fsl_xcvr_ops *xcvr_ops); + +static int __init isp1504xc_init(void) +{ + pr_debug("%s\n", __FUNCTION__); + + fsl_usb_xcvr_register(&isp1504_ops); + + /* suspend isp1504 */ + if (fsl_usb_xcvr_suspend(&isp1504_ops)) + pr_debug("%s: failed to suspend isp1504\n", __func__); + + return 0; +} + +extern void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops); + +static void __exit isp1504xc_exit(void) +{ + fsl_usb_xcvr_unregister(&isp1504_ops); +} + +module_init(isp1504xc_init); +module_exit(isp1504xc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("isp1504 xcvr driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/plat-mxc/leds.c linux-2.6.26-lab126/arch/arm/plat-mxc/leds.c --- linux-2.6.26/arch/arm/plat-mxc/leds.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/leds.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,111 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * The LED can be used for debugging purpose. To enalbe the LEDs, in the + * config file, select: + * CONFIG_LEDS + * CONFIG_LEDS_TIMER --- enable the OS tick LED once every 50 ticks (.5sec) + * CONFIG_LEDS_CPU --- enable the cpu idle in/out LED (blink fast) + * + * The two LEDs can be disabled through user space by issuing: + * echo "claim" > /sys/devices/system/leds/leds0/event + * To release the LEDs back to the normal operation, do: + * echo "release" > /sys/devices/system/leds/leds0/event + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LED_STATE_ENABLED (1 << 0) +#define LED_STATE_CLAIMED (1 << 1) + +static unsigned int led_state; +static unsigned int hw_led_state; + +static void mxc_leds_event(led_event_t evt) +{ + unsigned long flags; + + local_irq_save(flags); + + switch (evt) { + case led_start: + hw_led_state = MXC_BD_LED1 | MXC_BD_LED2; + led_state = LED_STATE_ENABLED; + break; + + case led_stop: + case led_halted: + hw_led_state = 0; + led_state &= ~LED_STATE_ENABLED; + MXC_BD_LED_OFF(MXC_BD_LED1 | MXC_BD_LED2); + break; + + case led_claim: + led_state |= LED_STATE_CLAIMED; + hw_led_state = 0; + break; + + case led_release: + led_state &= ~LED_STATE_CLAIMED; + hw_led_state = 0; + break; + +#ifdef CONFIG_LEDS_TIMER + case led_timer: + if (!(led_state & LED_STATE_CLAIMED)) + hw_led_state ^= MXC_BD_LED1; + break; +#endif + +#ifdef CONFIG_LEDS_CPU + case led_idle_start: + if (!(led_state & LED_STATE_CLAIMED)) + hw_led_state &= ~MXC_BD_LED2; + break; + + case led_idle_end: + if (!(led_state & LED_STATE_CLAIMED)) + hw_led_state |= MXC_BD_LED2; + break; +#endif + + default: + break; + } + + if (led_state & LED_STATE_ENABLED) { + MXC_BD_LED_OFF(~hw_led_state); + MXC_BD_LED_ON(hw_led_state); + } + + local_irq_restore(flags); +} + +static int __init mxc_leds_init(void) +{ + led_state = LED_STATE_ENABLED; + leds_event = mxc_leds_event; + return 0; +} + +core_initcall(mxc_leds_init); diff -urN linux-2.6.26/arch/arm/plat-mxc/mc13783_xc.c linux-2.6.26-lab126/arch/arm/plat-mxc/mc13783_xc.c --- linux-2.6.26/arch/arm/plat-mxc/mc13783_xc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/mc13783_xc.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,299 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Events to be passed to the thread */ +#define MC13783_USB_VBUS_ON 0x0001 +#define MC13783_USB_VBUS_OFF 0x0002 +#define MC13783_USB_DETECT_MINI_A 0x0004 +#define MC13783_USB_DETECT_MINI_B 0x0008 + +extern void otg_set_serial_peripheral(void); +extern void otg_set_serial_host(void); + +static unsigned int p_event; +static PMIC_CONVITY_EVENTS g_event; +static PMIC_CONVITY_HANDLE pmic_handle = (PMIC_CONVITY_HANDLE) NULL; + +static void xc_workqueue_handler(struct work_struct *work); + +DECLARE_WORK(xc_work, xc_workqueue_handler); + +DECLARE_MUTEX(pmic_mx); + +static void pmic_event_handler(const PMIC_CONVITY_EVENTS event) +{ + if (event & USB_DETECT_4V4_RISE) + pr_debug("%s: USB_DETECT_4V4_RISE\n", __func__); + + if (event & USB_DETECT_4V4_FALL) + pr_debug("%s: USB_DETECT_4V4_FALL\n", __func__); + + if (event & USB_DETECT_2V0_RISE) + pr_debug("%s: USB_DETECT_2V0_RISE\n", __func__); + + if (event & USB_DETECT_2V0_FALL) + pr_debug("%s: USB_DETECT_2V0_FALL\n", __func__); + + if (event & USB_DETECT_0V8_RISE) + pr_debug("%s: USB_DETECT_0V8_RISE\n", __func__); + + if (event & USB_DETECT_0V8_FALL) + pr_debug("%s: USB_DETECT_0V8_FALL\n", __func__); + + if (event & USB_DETECT_MINI_B) { + pr_debug("%s: USB_DETECT_MINI_B\n", __func__); + otg_set_serial_peripheral(); + g_event = USB_DETECT_MINI_B; + p_event = MC13783_USB_DETECT_MINI_B; + schedule_work(&xc_work); + } + if (event & USB_DETECT_MINI_A) { + pr_debug("%s: USB_DETECT_MINI_A\n", __func__); + otg_set_serial_host(); + g_event = USB_DETECT_MINI_A; + p_event = MC13783_USB_DETECT_MINI_A; + schedule_work(&xc_work); + } + + /* + * Mini-B cable insertion/removal does not generate cable-detect + * event, so we rely on the VBUS changes to identify a mini-b cable + * connect. This logic is only used if mini-b is the first cable that + * is connected after bootup. At all other times, removal of mini-a + * cable is used to initialize peripheral. + */ + if (g_event != USB_DETECT_MINI_A && g_event != USB_DETECT_MINI_B) { + if ((event & USB_DETECT_0V8_RISE) && + (event & USB_DETECT_2V0_RISE) && + (event & USB_DETECT_4V4_RISE)) { + otg_set_serial_peripheral(); + g_event = USB_DETECT_MINI_B; + p_event = MC13783_USB_DETECT_MINI_B; + schedule_work(&xc_work); + } + } +} + +static int usb_pmic_mod_init(void) +{ + PMIC_STATUS rs = PMIC_ERROR; + + init_MUTEX_LOCKED(&pmic_mx); + + rs = pmic_convity_open(&pmic_handle, USB); + if (rs != PMIC_SUCCESS) { + printk(KERN_ERR "pmic_convity_open returned error %d\n", rs); + return rs; + } + + rs = pmic_convity_set_callback(pmic_handle, pmic_event_handler, + USB_DETECT_4V4_RISE | USB_DETECT_4V4_FALL + | USB_DETECT_2V0_RISE | + USB_DETECT_2V0_FALL | USB_DETECT_0V8_RISE + | USB_DETECT_0V8_FALL | USB_DETECT_MINI_A + | USB_DETECT_MINI_B); + + if (rs != PMIC_SUCCESS) { + printk(KERN_ERR + "pmic_convity_set_callback returned error %d\n", rs); + return rs; + } + + return rs; +} + +static void usb_pmic_mod_exit(void) +{ + PMIC_STATUS rs; + + pmic_convity_set_mode(pmic_handle, RS232_1); + pmic_convity_clear_callback(pmic_handle); + + if (pmic_handle != (PMIC_CONVITY_HANDLE) NULL) { + rs = pmic_convity_close(pmic_handle); + if (rs != PMIC_SUCCESS) { + printk(KERN_ERR + "pmic_convity_close() returned error %d", rs); + } else { + pmic_handle = (PMIC_CONVITY_HANDLE) NULL; + } + } +} + +static inline void mc13783_set_host(void) +{ + PMIC_STATUS rs = PMIC_ERROR; + + rs = pmic_convity_usb_otg_clear_config(pmic_handle, USB_OTG_SE0CONN); + rs |= pmic_convity_usb_otg_clear_config(pmic_handle, USB_PU); + + rs |= pmic_convity_usb_otg_set_config(pmic_handle, USB_UDM_PD); + rs |= pmic_convity_usb_otg_set_config(pmic_handle, USB_UDP_PD); + + if (rs != PMIC_SUCCESS) + printk(KERN_ERR "mc13783_set_host failed\n"); + +} + +static inline void mc13783_set_peripheral(void) +{ + PMIC_STATUS rs = PMIC_ERROR; + + rs = pmic_convity_usb_otg_clear_config(pmic_handle, USB_UDM_PD); + rs |= pmic_convity_usb_otg_clear_config(pmic_handle, USB_UDP_PD); + + rs |= pmic_convity_usb_set_speed(pmic_handle, USB_FULL_SPEED); + rs |= pmic_convity_usb_otg_set_config(pmic_handle, USB_OTG_SE0CONN); + rs |= pmic_convity_usb_otg_set_config(pmic_handle, USB_PU); + + if (rs != PMIC_SUCCESS) + printk(KERN_ERR "mc13783_set_peripheral failed\n"); +} + +void mc13783_set_vbus_power(struct fsl_xcvr_ops *this, + struct fsl_usb2_platform_data *pdata, int on) +{ + if (on) { + p_event = MC13783_USB_VBUS_ON; + schedule_work(&xc_work); + } +} + +static struct fsl_xcvr_ops mc13783_ops_otg = { + .name = "mc13783", + .xcvr_type = PORTSC_PTS_SERIAL, + .set_host = mc13783_set_host, + .set_device = mc13783_set_peripheral, + .set_vbus_power = mc13783_set_vbus_power, +}; + +extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops); + +static void xc_workqueue_handler(struct work_struct *work) +{ + PMIC_STATUS rs = PMIC_ERROR; + + down(&pmic_mx); + + switch (p_event) { + case MC13783_USB_VBUS_OFF: + mc13783_set_peripheral(); + break; + case MC13783_USB_VBUS_ON: + mc13783_set_host(); + break; + case MC13783_USB_DETECT_MINI_B: + rs = pmic_convity_set_output(pmic_handle, true, false); + rs |= + pmic_convity_usb_otg_clear_config(pmic_handle, + USB_VBUS_CURRENT_LIMIT_LOW_30MS); + + if (rs != PMIC_SUCCESS) + printk(KERN_ERR "MC13783_USB_VBUS_OFF failed\n"); + break; + case MC13783_USB_DETECT_MINI_A: + rs = pmic_convity_set_output(pmic_handle, true, true); + rs |= + pmic_convity_usb_otg_set_config(pmic_handle, + USB_VBUS_CURRENT_LIMIT_LOW_30MS); + + if (rs != PMIC_SUCCESS) + printk(KERN_ERR "MC13783_USB_VBUS_ON failed\n"); + break; + default: + break; + } + up(&pmic_mx); +} + +int mc13783xc_init(void) +{ + PMIC_STATUS rs = PMIC_ERROR; + +#if defined(CONFIG_MXC_USB_SB3) + int xc_mode = USB_SINGLE_ENDED_BIDIR; +#elif defined(CONFIG_MXC_USB_SU6) + int xc_mode = USB_SINGLE_ENDED_UNIDIR; +#elif defined(CONFIG_MXC_USB_DB4) + int xc_mode = USB_DIFFERENTIAL_BIDIR; +#else + int xc_mode = USB_DIFFERENTIAL_UNIDIR; +#endif + + rs = usb_pmic_mod_init(); + if (rs != PMIC_SUCCESS) { + usb_pmic_mod_exit(); + printk(KERN_ERR "usb_pmic_mod_init failed\n"); + return rs; + } + + rs = pmic_convity_usb_set_xcvr(pmic_handle, xc_mode); + rs |= pmic_convity_usb_otg_set_config(pmic_handle, USB_OTG_SE0CONN); + rs |= pmic_convity_usb_otg_set_config(pmic_handle, USBXCVREN); + rs |= pmic_convity_set_output(pmic_handle, false, true); + + rs |= pmic_convity_usb_otg_set_config(pmic_handle, USB_PULL_OVERRIDE); + rs |= pmic_convity_usb_otg_clear_config(pmic_handle, USB_USBCNTRL); + rs |= pmic_convity_usb_otg_clear_config(pmic_handle, USB_DP150K_PU); + + if (rs != PMIC_SUCCESS) + printk(KERN_ERR "pmic configuration failed\n"); + + fsl_usb_xcvr_register(&mc13783_ops_otg); + + mc13783_set_peripheral(); + + return rs; +} + +extern void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops); + +void mc13783xc_uninit(void) +{ + /* Clear stuff from init */ + pmic_convity_usb_otg_clear_config(pmic_handle, USB_OTG_SE0CONN); + pmic_convity_usb_otg_clear_config(pmic_handle, USBXCVREN); + pmic_convity_set_output(pmic_handle, false, false); + pmic_convity_usb_otg_clear_config(pmic_handle, USB_PULL_OVERRIDE); + + /* Clear host mode */ + pmic_convity_usb_otg_clear_config(pmic_handle, USB_UDP_PD); + pmic_convity_usb_otg_clear_config(pmic_handle, USB_UDM_PD); + + /* Clear peripheral mode */ + pmic_convity_usb_otg_clear_config(pmic_handle, USB_PU); + + /* Vbus off */ + pmic_convity_set_output(pmic_handle, true, false); + pmic_convity_usb_otg_clear_config(pmic_handle, + USB_VBUS_CURRENT_LIMIT_LOW_30MS); + + usb_pmic_mod_exit(); + + fsl_usb_xcvr_unregister(&mc13783_ops_otg); +} + +module_init(mc13783xc_init); +module_exit(mc13783xc_uninit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("mc13783xc"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/plat-mxc/pwm.c linux-2.6.26-lab126/arch/arm/plat-mxc/pwm.c --- linux-2.6.26/arch/arm/plat-mxc/pwm.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/pwm.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,282 @@ +/* + * simple driver for PWM (Pulse Width Modulator) controller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Derived from PXA PWM driver by Eric Miao + * + * Copyright 2009 Amazon Technologies, Inc. All Rights Reserved. + * Manish Lachwani (lachwani@lab126.com) + */ + +#include +#include +#include +#include +#include +#include +#include +#include + + +/* i.MX35 PWM function block: */ + +#define MX35_PWMCR 0x00 /* PWM Control Register */ +#define MX35_PWMSAR 0x0C /* PWM Sample Register */ +#define MX35_PWMPR 0x10 /* PWM Period Register */ +#define MX35_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) + +#define MX35_PWMCR_STOPEN (1 << 25) +#define MX35_PWMCR_DOZEEN (1 << 24) +#define MX35_PWMCR_WAITEN (1 << 23) +#define MX35_PWMCR_DBGEN (1 << 22) +#define MX35_PWMCR_CLKSRC_IPG (1 << 16) +#define MX35_PWMCR_CLKSRC_IPG_HIGH (2 << 16) +#define MX35_PWMCR_CLKSRC_IPG_32k (3 << 16) +#define MX35_PWMCR_EN (1 << 0) + +struct pwm_device { + struct list_head node; + struct platform_device *pdev; + + const char *label; + struct clk *clk; + + int clk_enabled; + void __iomem *mmio_base; + + unsigned int use_count; + unsigned int pwm_id; +}; + +int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +{ + unsigned long long c; + unsigned long period_cycles, duty_cycles, prescale; + + if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) + return -EINVAL; + + c = clk_get_rate(pwm->clk); + c = c * period_ns; + do_div(c, 1000000000); + period_cycles = c; + + prescale = period_cycles / 0x10000 + 1; + + period_cycles /= prescale; + c = (unsigned long long)period_cycles * duty_ns; + do_div(c, period_ns); + duty_cycles = c; + + writel(duty_cycles, pwm->mmio_base + MX35_PWMSAR); + writel(period_cycles, pwm->mmio_base + MX35_PWMPR); + writel(MX35_PWMCR_PRESCALER(prescale) | + MX35_PWMCR_CLKSRC_IPG_HIGH | + MX35_PWMCR_STOPEN | MX35_PWMCR_DOZEEN | + MX35_PWMCR_WAITEN | MX35_PWMCR_DBGEN, + pwm->mmio_base + MX35_PWMCR); + + return 0; +} +EXPORT_SYMBOL(pwm_config); + +int pwm_enable(struct pwm_device *pwm) +{ + unsigned long reg; + int rc = 0; + + if (!pwm->clk_enabled) { + rc = clk_enable(pwm->clk); + if (!rc) + pwm->clk_enabled = 1; + } + + reg = readl(pwm->mmio_base + MX35_PWMCR); + reg |= MX35_PWMCR_EN; + writel(reg, pwm->mmio_base + MX35_PWMCR); + return rc; +} +EXPORT_SYMBOL(pwm_enable); + +void pwm_disable(struct pwm_device *pwm) +{ + unsigned long reg; + + if (pwm->clk_enabled) { + clk_disable(pwm->clk); + pwm->clk_enabled = 0; + } + + reg = readl(pwm->mmio_base + MX35_PWMCR); + reg &= ~MX35_PWMCR_EN; + writel(reg, pwm->mmio_base + MX35_PWMCR); + +} +EXPORT_SYMBOL(pwm_disable); + +static DEFINE_MUTEX(pwm_lock); +static LIST_HEAD(pwm_list); + +struct pwm_device *pwm_request(int pwm_id, const char *label) +{ + struct pwm_device *pwm; + int found = 0; + + mutex_lock(&pwm_lock); + + list_for_each_entry(pwm, &pwm_list, node) { + if (pwm->pwm_id == pwm_id) { + found = 1; + break; + } + } + + if (found) { + if (pwm->use_count == 0) { + pwm->use_count++; + pwm->label = label; + } else + pwm = ERR_PTR(-EBUSY); + } else + pwm = ERR_PTR(-ENOENT); + + mutex_unlock(&pwm_lock); + return pwm; +} +EXPORT_SYMBOL(pwm_request); + +void pwm_free(struct pwm_device *pwm) +{ + mutex_lock(&pwm_lock); + + if (pwm->use_count) { + pwm->use_count--; + pwm->label = NULL; + } else + pr_warning("PWM device already freed\n"); + + mutex_unlock(&pwm_lock); +} +EXPORT_SYMBOL(pwm_free); + +static int __devinit mxc_pwm_probe(struct platform_device *pdev) +{ + struct pwm_device *pwm; + struct resource *r; + int ret = 0, irq = 0; + + pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); + if (pwm == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + + pwm->clk = clk_get(&pdev->dev, "pwm_clk"); + + if (IS_ERR(pwm->clk)) { + ret = PTR_ERR(pwm->clk); + goto err_free; + } + + pwm->clk_enabled = 0; + + pwm->use_count = 0; + pwm->pwm_id = pdev->id; + pwm->pdev = pdev; + + r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!r) { + dev_err(&pdev->dev, "no IRQ resource defined\n"); + return -ENODEV; + }; + + irq = r->start; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (r == NULL) { + dev_err(&pdev->dev, "no memory resource defined\n"); + ret = -ENODEV; + goto err_free_clk; + } + + r = request_mem_region(r->start, resource_size(r), pdev->name); + if (r == NULL) { + dev_err(&pdev->dev, "failed to request memory resource\n"); + ret = -EBUSY; + goto err_free_clk; + } + + pwm->mmio_base = ioremap(r->start, resource_size(r)); + if (pwm->mmio_base == NULL) { + dev_err(&pdev->dev, "failed to ioremap() registers\n"); + ret = -ENODEV; + goto err_free_mem; + } + + mutex_lock(&pwm_lock); + list_add_tail(&pwm->node, &pwm_list); + mutex_unlock(&pwm_lock); + + printk(KERN_INFO "MXC PWM Initialized\n"); + + platform_set_drvdata(pdev, pwm); + return 0; + +err_free_mem: + release_mem_region(r->start, resource_size(r)); +err_free_clk: + clk_put(pwm->clk); +err_free: + kfree(pwm); + return ret; +} + +static int __devexit mxc_pwm_remove(struct platform_device *pdev) +{ + struct pwm_device *pwm; + struct resource *r; + + pwm = platform_get_drvdata(pdev); + if (pwm == NULL) + return -ENODEV; + + mutex_lock(&pwm_lock); + list_del(&pwm->node); + mutex_unlock(&pwm_lock); + + iounmap(pwm->mmio_base); + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(r->start, resource_size(r)); + + clk_put(pwm->clk); + + kfree(pwm); + return 0; +} + +static struct platform_driver mxc_pwm_driver = { + .driver = { + .name = "mxc_pwm", + }, + .probe = mxc_pwm_probe, + .remove = __devexit_p(mxc_pwm_remove), +}; + +static int __init mxc_pwm_init(void) +{ + return platform_driver_register(&mxc_pwm_driver); +} +arch_initcall(mxc_pwm_init); + +static void __exit mxc_pwm_exit(void) +{ + platform_driver_unregister(&mxc_pwm_driver); +} +module_exit(mxc_pwm_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Sascha Hauer "); diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/Makefile linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/Makefile --- linux-2.6.26/arch/arm/plat-mxc/sdma/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/Makefile 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,18 @@ +ifneq ($(KBUILD_SRC),) +ccflags-y += -I$(KBUILD_SRC)/arch/arm/plat-mxc/sdma/iapi/include \ + -I$(KBUILD_SRC)/include/linux \ + -DMCU -DOS=LINUX \ + -DL_I_T_T_L_E_ENDIAN=0 -DB_I_G_ENDIAN=1 \ + -DENDIANNESS=L_I_T_T_L_E_ENDIAN +else +ccflags-y += -Iarch/arm/plat-mxc/sdma/iapi/include \ + -Iinclude/linux \ + -DMCU -DOS=LINUX \ + -DL_I_T_T_L_E_ENDIAN=0 -DB_I_G_ENDIAN=1 \ + -DENDIANNESS=L_I_T_T_L_E_ENDIAN +endif + +obj-y += dma_sdma.o +obj-$(CONFIG_MXC_SDMA_API) += sdma.o +obj-$(CONFIG_MXC_SDMA_API) += iapi/ +obj-$(CONFIG_MXC_SDMA_API) += sdma_malloc.o diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/dma_sdma.c linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/dma_sdma.c --- linux-2.6.26/arch/arm/plat-mxc/sdma/dma_sdma.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/dma_sdma.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,697 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file plat-mxc/sdma/dma_sdma.c + * @brief Front-end to the DMA handling. This handles the allocation/freeing + * of DMA channels, and provides a unified interface to the machines + * DMA facilities. This file contains functions for Smart DMA. + * + * @ingroup SDMA + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_MXC_SDMA_API + +static mxc_dma_channel_t mxc_sdma_channels[MAX_DMA_CHANNELS]; +static mxc_dma_channel_private_t mxc_sdma_private[MAX_DMA_CHANNELS]; + +extern struct clk *mxc_sdma_ahb_clk, *mxc_sdma_ipg_clk; + +/*! + * Tasket to handle processing the channel buffers + * + * @param arg channel id + */ +static void mxc_sdma_channeltasklet(unsigned long arg) +{ + dma_request_t request_t; + dma_channel_params chnl_param; + mxc_dma_channel_t *chnl_info; + mxc_dma_channel_private_t *data_priv; + int bd_intr = 0, error = MXC_DMA_DONE; + + chnl_info = &mxc_sdma_channels[arg]; + data_priv = chnl_info->private; + chnl_param = + mxc_sdma_get_channel_params(chnl_info->channel)->chnl_params; + + mxc_dma_get_config(arg, &request_t, data_priv->buf_tail); + + while (request_t.bd_done == 0) { + bd_intr = mxc_dma_get_bd_intr(arg, data_priv->buf_tail); + if ((data_priv->buf_tail += 1) >= chnl_param.bd_number) { + data_priv->buf_tail = 0; + } + chnl_info->active = 0; + if (request_t.bd_error) { + error = MXC_DMA_TRANSFER_ERROR; + } + + if (bd_intr != 0) { + chnl_info->cb_fn(chnl_info->cb_args, error, + request_t.count); + error = MXC_DMA_DONE; + } + + if (data_priv->buf_tail == chnl_info->curr_buf) { + break; + } + memset(&request_t, 0, sizeof(dma_request_t)); + mxc_dma_get_config(arg, &request_t, data_priv->buf_tail); + } +} + +/*! + * This function is generally called by the driver at open time. + * The DMA driver would do any initialization steps that is required + * to get the channel ready for data transfer. + * + * @param channel_id a pre-defined id. The peripheral driver would specify + * the id associated with its peripheral. This would be + * used by the DMA driver to identify the peripheral + * requesting DMA and do the necessary setup on the + * channel associated with the particular peripheral. + * The DMA driver could use static or dynamic DMA channel + * allocation. + * @param dev_name module name or device name + * @return returns a negative number on error if request for a DMA channel did not + * succeed, returns the channel number to be used on success. + */ +int mxc_dma_request_ext(mxc_dma_device_t channel_id, char *dev_name, + dma_channel_info_t *info) +{ + mxc_sdma_channel_params_t *chnl; + mxc_dma_channel_private_t *data_priv; + int ret = 0, i = 0, channel_num = 0; + mxc_sdma_channel_ext_params_t *p; + + chnl = mxc_sdma_get_channel_params(channel_id); + if (chnl == NULL) { + return -EINVAL; + } + + if (info) { + if (!chnl->chnl_params.ext) + return -EINVAL; + p = (mxc_sdma_channel_ext_params_t *)chnl; + memcpy(&p->chnl_ext_params.info, info, sizeof(info)); + } + + /* Enable the SDMA clock */ + clk_enable(mxc_sdma_ahb_clk); + clk_enable(mxc_sdma_ipg_clk); + + channel_num = chnl->channel_num; + if (chnl->channel_num == MXC_DMA_DYNAMIC_CHANNEL) { + /* Get the first free channel */ + for (i = (MAX_DMA_CHANNELS - 1); i > 0; i--) { + /* See if channel is available */ + if ((mxc_sdma_channels[i].dynamic != 1) + || (mxc_sdma_channels[i].lock != 0)) { + continue; + } + channel_num = i; + /* Check to see if we can get this channel */ + ret = mxc_request_dma(&channel_num, dev_name); + if (ret == 0) { + break; + } else { + continue; + } + } + if (ret != 0) { + /* No free channel */ + goto err_ret; + } + } else { + if (mxc_sdma_channels[chnl->channel_num].lock == 1) { + ret = -ENODEV; + goto err_ret; + } + ret = mxc_request_dma(&channel_num, dev_name); + if (ret != 0) { + goto err_ret; + } + } + + ret = mxc_dma_setup_channel(channel_num, &chnl->chnl_params); + + if (ret == 0) { + if (chnl->chnl_priority != MXC_SDMA_DEFAULT_PRIORITY) { + ret = + mxc_dma_set_channel_priority(channel_num, + chnl->chnl_priority); + if (ret != 0) { + pr_info("Failed to set channel prority,\ + continue with the existing \ + priority\n"); + goto err_ret; + } + } + mxc_sdma_channels[channel_num].lock = 1; + if ((chnl->chnl_params.transfer_type == per_2_emi) + || (chnl->chnl_params.transfer_type == dsp_2_emi)) { + mxc_sdma_channels[channel_num].mode = MXC_DMA_MODE_READ; + } else { + mxc_sdma_channels[channel_num].mode = + MXC_DMA_MODE_WRITE; + } + mxc_sdma_channels[channel_num].channel = channel_id; + data_priv = mxc_sdma_channels[channel_num].private; + tasklet_init(&data_priv->chnl_tasklet, + mxc_sdma_channeltasklet, channel_num); + if ((channel_id == MXC_DMA_ATA_RX) + || (channel_id == MXC_DMA_ATA_TX)) { + data_priv->intr_after_every_bd = 0; + } else { + data_priv->intr_after_every_bd = 1; + } + } + err_ret: + if (ret != 0) { + clk_disable(mxc_sdma_ahb_clk); + clk_disable(mxc_sdma_ipg_clk); + channel_num = -ENODEV; + } + + return channel_num; +} + +/*! + * This function is generally called by the driver at close time. The DMA + * driver would do any cleanup associated with this channel. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @return returns a negative number on error or 0 on success + */ +int mxc_dma_free(int channel_num) +{ + mxc_dma_channel_private_t *data_priv; + + if ((channel_num >= MAX_DMA_CHANNELS) || (channel_num < 0)) { + return -EINVAL; + } + + if (mxc_sdma_channels[channel_num].lock != 1) { + return -ENODEV; + } + + mxc_free_dma(channel_num); + + /* Disable the SDMA clock */ + clk_disable(mxc_sdma_ahb_clk); + clk_disable(mxc_sdma_ipg_clk); + + mxc_sdma_channels[channel_num].lock = 0; + mxc_sdma_channels[channel_num].active = 0; + mxc_sdma_channels[channel_num].curr_buf = 0; + data_priv = mxc_sdma_channels[channel_num].private; + data_priv->buf_tail = 0; + tasklet_kill(&data_priv->chnl_tasklet); + + return 0; +} + +/*! + * Callback function called from the SDMA Interrupt routine + * + * @param arg driver specific argument that was registered + */ +static void mxc_dma_chnl_callback(void *arg) +{ + int priv; + mxc_dma_channel_private_t *data_priv; + + priv = (int)arg; + data_priv = mxc_sdma_channels[priv].private; + + /* To avoid latencies, call the tasklet directly */ + mxc_sdma_channeltasklet(priv); +} + +/*! + * This function would just configure the buffers specified by the user into + * dma channel. The caller must call mxc_dma_enable to start this transfer. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @param dma_buf an array of physical addresses to the user defined + * buffers. The caller must guarantee the dma_buf is + * available until the transfer is completed. + * @param num_buf number of buffers in the array + * @param mode specifies whether this is READ or WRITE operation + * @return This function returns a negative number on error if buffer could not be + * added with DMA for transfer. On Success, it returns 0 + */ +int mxc_dma_config(int channel_num, mxc_dma_requestbuf_t * dma_buf, + int num_buf, mxc_dma_mode_t mode) +{ + int ret = 0, i = 0, prev_buf; + mxc_dma_channel_t *chnl_info; + mxc_dma_channel_private_t *data_priv; + mxc_sdma_channel_params_t *chnl; + dma_channel_params chnl_param; + dma_request_t request_t; + + if ((channel_num >= MAX_DMA_CHANNELS) || (channel_num < 0)) { + return -EINVAL; + } + + if (num_buf <= 0) { + return -EINVAL; + } + + chnl_info = &mxc_sdma_channels[channel_num]; + data_priv = chnl_info->private; + if (chnl_info->lock != 1) { + return -ENODEV; + } + + /* Check to see if all buffers are taken */ + if (chnl_info->active == 1) { + return -EBUSY; + } + + chnl = mxc_sdma_get_channel_params(chnl_info->channel); + chnl_param = chnl->chnl_params; + + /* Re-setup the SDMA channel if the transfer direction is changed */ + if ((chnl_param.peripheral_type != MEMORY) && (mode != chnl_info->mode)) { + if (chnl_param.peripheral_type == DSP) { + if (mode == MXC_DMA_MODE_READ) { + chnl_param.transfer_type = dsp_2_emi; + } else { + chnl_param.transfer_type = emi_2_dsp; + } + } else if (chnl_param.peripheral_type == FIFO_MEMORY) { + if (mode == MXC_DMA_MODE_READ) + chnl_param.per_address = MXC_FIFO_MEM_SRC_FIXED; + else + chnl_param.per_address = + MXC_FIFO_MEM_DEST_FIXED; + } else { + if (mode == MXC_DMA_MODE_READ) { + chnl_param.transfer_type = per_2_emi; + } else { + chnl_param.transfer_type = emi_2_per; + } + } + chnl_param.callback = mxc_dma_chnl_callback; + chnl_param.arg = (void *)channel_num; + ret = mxc_dma_setup_channel(channel_num, &chnl_param); + if (ret != 0) { + return ret; + } + if (chnl->chnl_priority != MXC_SDMA_DEFAULT_PRIORITY) { + ret = + mxc_dma_set_channel_priority(channel_num, + chnl->chnl_priority); + if (ret != 0) { + pr_info("Failed to set channel prority,\ + continue with the existing \ + priority\n"); + } + } + chnl_info->mode = mode; + } + + for (i = 0; i < num_buf; i++, dma_buf++) { + /* Check to see if all buffers are taken */ + if (chnl_info->active == 1) { + break; + } + request_t.destAddr = (__u8 *) dma_buf->dst_addr; + request_t.sourceAddr = (__u8 *) dma_buf->src_addr; + if (chnl_param.peripheral_type == ASRC) + request_t.count = dma_buf->num_of_bytes / 4; + else + request_t.count = dma_buf->num_of_bytes; + request_t.bd_cont = 1; + ret = mxc_dma_set_config(channel_num, &request_t, + chnl_info->curr_buf); + if (ret != 0) { + break; + } + if (data_priv->intr_after_every_bd == 0) { + if (i == num_buf - 1) { + mxc_dma_set_bd_intr(channel_num, + chnl_info->curr_buf, 1); + } else { + mxc_dma_set_bd_intr(channel_num, + chnl_info->curr_buf, 0); + } + } + + prev_buf = chnl_info->curr_buf; + if ((chnl_info->curr_buf += 1) >= chnl_param.bd_number) { + chnl_info->curr_buf = 0; + } + if (chnl_info->curr_buf == data_priv->buf_tail) { + if ((data_priv->intr_after_every_bd == 0) + && (i != num_buf - 1)) { + /* + * Set the BD_INTR flag on the last BD that + * was queued + */ + mxc_dma_set_bd_intr(channel_num, prev_buf, 1); + } + chnl_info->active = 1; + } + } + + if (i == 0) { + return -EBUSY; + } + return 0; +} + +/*! + * This function would just configure the scatterlist specified by the + * user into dma channel. This is a slight variation of mxc_dma_config(), + * it is provided for the convenience of drivers that have a scatterlist + * passed into them. It is the calling driver's responsibility to have the + * correct physical address filled in the "dma_address" field of the + * scatterlist. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @param sg a scatterlist of buffers. The caller must guarantee + * the dma_buf is available until the transfer is + * completed. + * @param num_buf number of buffers in the array + * @param num_of_bytes total number of bytes to transfer. If set to 0, this + * would imply to use the length field of the scatterlist + * for each DMA transfer. Else it would calculate the size + * for each DMA transfer. + * @param mode specifies whether this is READ or WRITE operation + * @return This function returns a negative number on error if buffer could not + * be added with DMA for transfer. On Success, it returns 0 + */ +int mxc_dma_sg_config(int channel_num, struct scatterlist *sg, + int num_buf, int num_of_bytes, mxc_dma_mode_t mode) +{ + int ret = 0, i = 0; + mxc_dma_requestbuf_t *dma_buf; + + if ((channel_num >= MAX_DMA_CHANNELS) || (channel_num < 0)) { + return -EINVAL; + } + + if (mxc_sdma_channels[channel_num].lock != 1) { + return -ENODEV; + } + + dma_buf = + (mxc_dma_requestbuf_t *) kmalloc(num_buf * + sizeof(mxc_dma_requestbuf_t), + GFP_KERNEL); + + if (dma_buf == NULL) { + return -EFAULT; + } + + for (i = 0; i < num_buf; i++) { + if (mode == MXC_DMA_MODE_READ) { + (dma_buf + i)->dst_addr = sg->dma_address; + } else { + (dma_buf + i)->src_addr = sg->dma_address; + } + + if ((num_of_bytes > sg->length) || (num_of_bytes == 0)) { + (dma_buf + i)->num_of_bytes = sg->length; + } else { + (dma_buf + i)->num_of_bytes = num_of_bytes; + } + sg++; + num_of_bytes -= (dma_buf + i)->num_of_bytes; + } + + ret = mxc_dma_config(channel_num, dma_buf, num_buf, mode); + kfree(dma_buf); + return ret; +} + +/*! + * This function is provided if the driver would like to set/change its + * callback function. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @param callback a callback function to provide notification on transfer + * completion, user could specify NULL if he does not wish + * to be notified + * @param arg an argument that gets passed in to the callback + * function, used by the user to do any driver specific + * operations. + * @return this function returns a negative number on error if the callback + * could not be set for the channel or 0 on success + */ +int mxc_dma_callback_set(int channel_num, + mxc_dma_callback_t callback, void *arg) +{ + if ((channel_num >= MAX_DMA_CHANNELS) || (channel_num < 0)) { + return -EINVAL; + } + + if (mxc_sdma_channels[channel_num].lock != 1) { + return -ENODEV; + } + + mxc_sdma_channels[channel_num].cb_fn = callback; + mxc_sdma_channels[channel_num].cb_args = arg; + + mxc_dma_set_callback(channel_num, mxc_dma_chnl_callback, + (void *)channel_num); + + return 0; +} + +/*! + * This stops the DMA channel and any ongoing transfers. Subsequent use of + * mxc_dma_enable() will restart the channel and restart the transfer. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @return returns a negative number on error or 0 on success + */ +int mxc_dma_disable(int channel_num) +{ + if ((channel_num >= MAX_DMA_CHANNELS) || (channel_num < 0)) { + return -EINVAL; + } + + if (mxc_sdma_channels[channel_num].lock != 1) { + return -ENODEV; + } + + mxc_dma_stop(channel_num); + return 0; +} + +/*! + * This starts DMA transfer. Or it restarts DMA on a stopped channel + * previously stopped with mxc_dma_disable(). + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @return returns a negative number on error or 0 on success + */ +int mxc_dma_enable(int channel_num) +{ + if ((channel_num >= MAX_DMA_CHANNELS) || (channel_num < 0)) { + return -EINVAL; + } + + if (mxc_sdma_channels[channel_num].lock != 1) { + return -ENODEV; + } + + mxc_dma_start(channel_num); + return 0; +} + +/*! + * Initializes dma structure with dma_operations + * + * @param dma dma structure + * @return returns 0 on success + */ +static int __init mxc_dma_init(void) +{ + int i; + for (i = 0; i < MAX_DMA_CHANNELS; i++) { + mxc_sdma_channels[i].active = 0; + mxc_sdma_channels[i].lock = 0; + mxc_sdma_channels[i].curr_buf = 0; + mxc_sdma_channels[i].dynamic = 1; + mxc_sdma_private[i].buf_tail = 0; + mxc_sdma_channels[i].private = &mxc_sdma_private[i]; + } + /* + * Make statically allocated channels unavailable for dynamic channel + * requests + */ + mxc_get_static_channels(mxc_sdma_channels); + + return 0; +} + +arch_initcall(mxc_dma_init); + +#else +int mxc_request_dma(int *channel, const char *devicename) +{ + return -ENODEV; +} + +int mxc_dma_setup_channel(int channel, dma_channel_params * p) +{ + return -ENODEV; +} + +int mxc_dma_set_channel_priority(unsigned int channel, unsigned int priority) +{ + return -ENODEV; +} + +int mxc_dma_set_config(int channel, dma_request_t * p, int bd_index) +{ + return -ENODEV; +} + +int mxc_dma_get_config(int channel, dma_request_t * p, int bd_index) +{ + return -ENODEV; +} + +int mxc_dma_start(int channel) +{ + return -ENODEV; +} + +int mxc_dma_stop(int channel) +{ + return -ENODEV; +} + +void mxc_free_dma(int channel) +{ +} + +void mxc_dma_set_callback(int channel, dma_callback_t callback, void *arg) +{ +} + +void *sdma_malloc(size_t size) +{ + return 0; +} + +void sdma_free(void *buf) +{ +} + +void *sdma_phys_to_virt(unsigned long buf) +{ + return 0; +} + +unsigned long sdma_virt_to_phys(void *buf) +{ + return 0; +} + +int mxc_dma_request(mxc_dma_device_t channel_id, char *dev_name) +{ + return -ENODEV; +} + +int mxc_dma_free(int channel_num) +{ + return -ENODEV; +} + +int mxc_dma_config(int channel_num, mxc_dma_requestbuf_t * dma_buf, + int num_buf, mxc_dma_mode_t mode) +{ + return -ENODEV; +} + +int mxc_dma_sg_config(int channel_num, struct scatterlist *sg, + int num_buf, int num_of_bytes, mxc_dma_mode_t mode) +{ + return -ENODEV; +} + +int mxc_dma_callback_set(int channel_num, mxc_dma_callback_t callback, + void *arg) +{ + return -ENODEV; +} + +int mxc_dma_disable(int channel_num) +{ + return -ENODEV; +} + +int mxc_dma_enable(int channel_num) +{ + return -ENODEV; +} + +EXPORT_SYMBOL(mxc_request_dma); +EXPORT_SYMBOL(mxc_dma_setup_channel); +EXPORT_SYMBOL(mxc_dma_set_channel_priority); +EXPORT_SYMBOL(mxc_dma_set_config); +EXPORT_SYMBOL(mxc_dma_get_config); +EXPORT_SYMBOL(mxc_dma_start); +EXPORT_SYMBOL(mxc_dma_stop); +EXPORT_SYMBOL(mxc_free_dma); +EXPORT_SYMBOL(mxc_dma_set_callback); +EXPORT_SYMBOL(sdma_malloc); +EXPORT_SYMBOL(sdma_free); +EXPORT_SYMBOL(sdma_phys_to_virt); +EXPORT_SYMBOL(sdma_virt_to_phys); + +#endif + +EXPORT_SYMBOL(mxc_dma_request_ext); +EXPORT_SYMBOL(mxc_dma_free); +EXPORT_SYMBOL(mxc_dma_config); +EXPORT_SYMBOL(mxc_dma_sg_config); +EXPORT_SYMBOL(mxc_dma_callback_set); +EXPORT_SYMBOL(mxc_dma_disable); +EXPORT_SYMBOL(mxc_dma_enable); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC Linux SDMA API"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/Makefile linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/Makefile --- linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/Makefile 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,5 @@ +# +# Makefile for I.API sources. +# + +obj-y := src/ \ No newline at end of file diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/epm.h linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/epm.h --- linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/epm.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/epm.h 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,187 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_SDMA_REGS_H__ +#define __ASM_ARCH_MXC_SDMA_REGS_H__ + +#include + +/* SDMA Reg definition */ +#define SDMA_BASE_IO_ADDR IO_ADDRESS(SDMA_BASE_ADDR) + +#define SDMA_H_C0PTR *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x000)) +#define SDMA_H_INTR *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x004)) +#define SDMA_H_STATSTOP *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x008)) +#define SDMA_H_START *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x00C)) +#define SDMA_H_EVTOVR *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x010)) +#define SDMA_H_DSPOVR *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x014)) +#define SDMA_H_HOSTOVR *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x018)) +#define SDMA_H_EVTPEND *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x01C)) +#define SDMA_H_DSPENBL *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x020)) +#define SDMA_H_RESET *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x024)) +#define SDMA_H_EVTERR *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x028)) +#define SDMA_H_INTRMSK *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x02C)) +#define SDMA_H_PSW *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x030)) +#define SDMA_H_EVTERRDBG *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x034)) +#define SDMA_H_CONFIG *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x038)) +#define SDMA_ONCE_ENB *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x040)) +#define SDMA_ONCE_DATA *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x044)) +#define SDMA_ONCE_INSTR *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x048)) +#define SDMA_ONCE_STAT *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x04C)) +#define SDMA_ONCE_CMD *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x050)) +#define SDMA_EVT_MIRROR *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x054)) +#define SDMA_ILLINSTADDR *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x058)) +#define SDMA_CHN0ADDR *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x05C)) +#define SDMA_ONCE_RTB *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x060)) +#define SDMA_XTRIG_CONF1 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x070)) +#define SDMA_XTRIG_CONF2 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x074)) + +#ifdef MXC_SDMA_V2 +#define SDMA_CHNENBL_0 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x200)) +#define SDMA_CHNENBL_1 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x204)) +#define SDMA_CHNENBL_2 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x208)) +#define SDMA_CHNENBL_3 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x20C)) +#define SDMA_CHNENBL_4 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x210)) +#define SDMA_CHNENBL_5 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x214)) +#define SDMA_CHNENBL_6 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x218)) +#define SDMA_CHNENBL_7 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x21C)) +#define SDMA_CHNENBL_8 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x220)) +#define SDMA_CHNENBL_9 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x224)) +#define SDMA_CHNENBL_10 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x228)) +#define SDMA_CHNENBL_11 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x22C)) +#define SDMA_CHNENBL_12 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x230)) +#define SDMA_CHNENBL_13 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x234)) +#define SDMA_CHNENBL_14 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x238)) +#define SDMA_CHNENBL_15 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x23C)) +#define SDMA_CHNENBL_16 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x240)) +#define SDMA_CHNENBL_17 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x244)) +#define SDMA_CHNENBL_18 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x248)) +#define SDMA_CHNENBL_19 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x24C)) +#define SDMA_CHNENBL_20 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x250)) +#define SDMA_CHNENBL_21 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x254)) +#define SDMA_CHNENBL_22 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x258)) +#define SDMA_CHNENBL_23 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x25C)) +#define SDMA_CHNENBL_24 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x260)) +#define SDMA_CHNENBL_25 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x264)) +#define SDMA_CHNENBL_26 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x268)) +#define SDMA_CHNENBL_27 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x26C)) +#define SDMA_CHNENBL_28 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x270)) +#define SDMA_CHNENBL_29 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x274)) +#define SDMA_CHNENBL_30 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x278)) +#define SDMA_CHNENBL_31 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x27C)) +#define SDMA_CHNENBL_32 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x280)) +#define SDMA_CHNENBL_33 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x284)) +#define SDMA_CHNENBL_34 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x288)) +#define SDMA_CHNENBL_35 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x28C)) +#define SDMA_CHNENBL_36 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x290)) +#define SDMA_CHNENBL_37 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x294)) +#define SDMA_CHNENBL_38 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x298)) +#define SDMA_CHNENBL_39 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x29C)) +#define SDMA_CHNENBL_40 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x2A0)) +#define SDMA_CHNENBL_41 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x2A4)) +#define SDMA_CHNENBL_42 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x2A8)) +#define SDMA_CHNENBL_43 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x2AC)) +#define SDMA_CHNENBL_44 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x2B0)) +#define SDMA_CHNENBL_45 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x2B4)) +#define SDMA_CHNENBL_46 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x2B8)) +#define SDMA_CHNENBL_47 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x2BC)) + +#define SDMA_ONCE_COUNT *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x300)) +#define SDMA_ONCE_ECTL *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x304)) +#define SDMA_ONCE_EAA *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x308)) +#define SDMA_ONCE_EAB *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x30C)) +#define SDMA_ONCE_EAM *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x310)) +#define SDMA_ONCE_ED *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x314)) +#define SDMA_ONCE_EDM *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x318)) +#define SDMA_ONCE_PCMATCH *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x31C)) + +#else + +#define SDMA_CHNENBL_0 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x080)) +#define SDMA_CHNENBL_1 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x084)) +#define SDMA_CHNENBL_2 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x088)) +#define SDMA_CHNENBL_3 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x08C)) +#define SDMA_CHNENBL_4 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x090)) +#define SDMA_CHNENBL_5 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x094)) +#define SDMA_CHNENBL_6 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x098)) +#define SDMA_CHNENBL_7 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x09C)) +#define SDMA_CHNENBL_8 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0A0)) +#define SDMA_CHNENBL_9 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0A4)) +#define SDMA_CHNENBL_10 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0A8)) +#define SDMA_CHNENBL_11 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0AC)) +#define SDMA_CHNENBL_12 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0B0)) +#define SDMA_CHNENBL_13 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0B4)) +#define SDMA_CHNENBL_14 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0B8)) +#define SDMA_CHNENBL_15 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0BC)) +#define SDMA_CHNENBL_16 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0C0)) +#define SDMA_CHNENBL_17 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0C4)) +#define SDMA_CHNENBL_18 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0C8)) +#define SDMA_CHNENBL_19 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0CC)) +#define SDMA_CHNENBL_20 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0D0)) +#define SDMA_CHNENBL_21 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0D4)) +#define SDMA_CHNENBL_22 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0D8)) +#define SDMA_CHNENBL_23 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0DC)) +#define SDMA_CHNENBL_24 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0E0)) +#define SDMA_CHNENBL_25 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0E4)) +#define SDMA_CHNENBL_26 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0E8)) +#define SDMA_CHNENBL_27 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0EC)) +#define SDMA_CHNENBL_28 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0F0)) +#define SDMA_CHNENBL_29 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0F4)) +#define SDMA_CHNENBL_30 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0F8)) +#define SDMA_CHNENBL_31 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0FC)) + +#define SDMA_ONCE_COUNT *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x200)) +#define SDMA_ONCE_ECTL *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x204)) +#define SDMA_ONCE_EAA *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x208)) +#define SDMA_ONCE_EAB *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x20C)) +#define SDMA_ONCE_EAM *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x210)) +#define SDMA_ONCE_ED *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x214)) +#define SDMA_ONCE_EDM *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x218)) +#define SDMA_ONCE_PCMATCH *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x21C)) + +#endif /* MXC_SDMA_V2 */ + +#define SDMA_CHNPRI_0 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x100)) +#define SDMA_CHNPRI_1 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x104)) +#define SDMA_CHNPRI_2 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x108)) +#define SDMA_CHNPRI_3 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x10C)) +#define SDMA_CHNPRI_4 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x110)) +#define SDMA_CHNPRI_5 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x114)) +#define SDMA_CHNPRI_6 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x118)) +#define SDMA_CHNPRI_7 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x11C)) +#define SDMA_CHNPRI_8 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x120)) +#define SDMA_CHNPRI_9 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x124)) +#define SDMA_CHNPRI_10 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x128)) +#define SDMA_CHNPRI_11 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x12C)) +#define SDMA_CHNPRI_12 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x130)) +#define SDMA_CHNPRI_13 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x134)) +#define SDMA_CHNPRI_14 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x138)) +#define SDMA_CHNPRI_15 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x13C)) +#define SDMA_CHNPRI_16 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x140)) +#define SDMA_CHNPRI_17 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x144)) +#define SDMA_CHNPRI_18 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x148)) +#define SDMA_CHNPRI_19 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x14C)) +#define SDMA_CHNPRI_20 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x150)) +#define SDMA_CHNPRI_21 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x154)) +#define SDMA_CHNPRI_22 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x158)) +#define SDMA_CHNPRI_23 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x15C)) +#define SDMA_CHNPRI_24 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x160)) +#define SDMA_CHNPRI_25 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x164)) +#define SDMA_CHNPRI_26 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x168)) +#define SDMA_CHNPRI_27 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x16C)) +#define SDMA_CHNPRI_28 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x170)) +#define SDMA_CHNPRI_29 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x174)) +#define SDMA_CHNPRI_30 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x178)) +#define SDMA_CHNPRI_31 *((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x17C)) + +#endif /* _mcuEpm_h */ diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/iapi.h linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/iapi.h --- linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/iapi.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/iapi.h 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,49 @@ +/****************************************************************************** + * + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapi.h + * + * $Id iapi.h $ + * + * Description: + * Unique include for the whole IAPI library. + * + * + * http//compass.mot.com/go/115342679 + * + * $Log iapi.h $ + * + * ***************************************************************************/ + +#ifndef _iapi_h +#define _iapi_h + +/* **************************************************************************** + * Include File Section + * ***************************************************************************/ + +#include "sdmaStruct.h" +#include "iapiDefaults.h" +#include "iapiLow.h" +#include "iapiMiddle.h" +#include "iapiHigh.h" + +#ifdef MCU +#include "iapiLowMcu.h" +#include "iapiMiddleMcu.h" +#endif /* MCU */ + + + +#endif /* _iapi_h */ diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/iapiDefaults.h linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/iapiDefaults.h --- linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/iapiDefaults.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/iapiDefaults.h 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,128 @@ +/****************************************************************************** + * + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiDefaults.h + * + * $Id iapiDefaults.h $ + * + * Description: + * This library is written in C to guarantee functionality and integrity in + * the usage of SDMA virtual DMA channels. This API (Application Programming + * Interface) allow SDMA channels' access in an OPEN, READ, WRITE, CLOSE + * fashion. + * + * + * + * + * $Log iapiDefaults.h $ + * + *****************************************************************************/ + + +#ifndef _iapi_defaults_h +#define _iapi_defaults_h + +/****************************************************************************** + * Include File Section + *****************************************************************************/ +#include "epm.h" +#include "sdmaStruct.h" + +/* **************************************************************************** + * Macro-command Section + * ***************************************************************************/ + +/** + * Error codes + * lower 5 bits free to include channel number when available + * and bit number 6 must be set when channel number is available + * + * Note : + * 1) Abbreviations / naming convention : + * - BD : Buffer Descriptor + * - CC : Channel Context + * - CCB : Channel Control Block + * - CD : Channel Descriptor + * - B : Buffer + * - CH : Channel + * + */ +#define IAPI_SUCCESS 0 +#define IAPI_FAILURE -1 +#define IAPI_ERR_CH_AVAILABLE 0x00020 +#define IAPI_ERR_NO_ERROR 0x00000 +#define IAPI_ERR_NO_CCB_DEFINED 0x01000 +#define IAPI_ERR_BD_UNINITIALIZED 0x02000 +#define IAPI_ERR_BD_ALLOCATED 0x03000 +#define IAPI_ERR_BD_ALLOCATION 0x04000 +#define IAPI_ERR_CCB_ALLOC_FAILED 0x05000 +#define IAPI_ERR_CCB_UNINITIALIZED 0x06000 +#define IAPI_ERR_CC_ALREADY_DEFINED 0x07000 +#define IAPI_ERR_CC_ALLOC_FAILED 0x08000 +#define IAPI_ERR_CD_ALREADY_DEFINED 0x09000 +#define IAPI_ERR_CD_ALLOC_FAILED 0x0A000 +#define IAPI_ERR_CD_CHANGE_CH_NUMBER 0x0B000 +#define IAPI_ERR_CD_CHANGE_CCB_PTR 0x0C000 +#define IAPI_ERR_CD_CHANGE_UNKNOWN 0x0D000 +#define IAPI_ERR_CD_CHANGE 0x0E000 +#define IAPI_ERR_CD_UNINITIALIZED 0x0F000 +#define IAPI_ERR_CLOSE 0x10000 +#define IAPI_ERR_B_ALLOC_FAILED 0x11000 +#define IAPI_ERR_CONFIG_OVERRIDE 0x12000 +#define IAPI_ERR_CH_IN_USE 0x13000 +#define IAPI_ERR_CALLBACKSYNCH_UNKNOWN 0x14000 +#define IAPI_ERR_INVALID_PARAMETER 0x15000 +#define IAPI_ERR_TRUST 0x16000 +#define IAPI_ERR_CHANNEL_UNINITIALIZED 0x17000 +#define IAPI_ERR_RROR_BIT_READ 0x18000 +#define IAPI_ERR_RROR_BIT_WRITE 0x19000 +#define IAPI_ERR_NOT_ALLOWED 0x1A000 +#define IAPI_ERR_NO_OS_FN 0x1B000 + + +/* + * Global Variable Section + */ + +/* + * Table to hold pointers to the callback functions registered by the users of + *I.API + */ +extern void (* callbackIsrTable[CH_NUM])(channelDescriptor * cd_p, void * arg); + +/* + * Table to hold user registered data pointers, to be privided in the callback + *function + */ +extern void * userArgTable[CH_NUM]; + +/* channelDescriptor data structure filled with default data*/ +extern channelDescriptor iapi_ChannelDefaults; + +/* Global variable to hold the last error encountered in I.API operations*/ +extern unsigned int iapi_errno; + +/* Used in synchronization, to mark started channels*/ +extern volatile unsigned long iapi_SDMAIntr; + +/* Hold a pointer to the start of the CCB array, to be used in the IRQ routine + *to find the channel descriptor for the channed sending the interrupt to the + *core. + */ +extern channelControlBlock * iapi_CCBHead; + +/* configs_data structure filled with default data*/ +extern configs_data iapi_ConfigDefaults; + +#endif /* iapiDefaults_h */ diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/iapiHigh.h linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/iapiHigh.h --- linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/iapiHigh.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/iapiHigh.h 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,136 @@ +/****************************************************************************** + * + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiHigh.h + * + * $Id iapiHigh.h $ + * + * Description: + * prototypes for high level function of I.API + * + * + * http://venerque.sps.mot.com/pjt/sfs/www/iapi/softsim_api.pdf + * + * $Log iapiHigh.h + * + * ***************************************************************************/ + +#ifndef _iapiHigh_h +#define _iapiHigh_h + +/* **************************************************************************** + * Include File Section + *****************************************************************************/ +#include "sdmaStruct.h" + +/* **************************************************************************** + * Macro-command Section + *****************************************************************************/ +enum { + IAPI_CHANGE_CHANDESC, + IAPI_CHANGE_BDNUM, + IAPI_CHANGE_BUFFSIZE, + IAPI_CHANGE_CHANBLOCK, + IAPI_CHANGE_INSTANCE, + IAPI_CHANGE_OWNERSHIP, + IAPI_CHANGE_SYNCH, + IAPI_CHANGE_TRUST, + IAPI_CHANGE_CALLBACKFUNC, + IAPI_CHANGE_CHANCCB, + IAPI_CHANGE_PRIORITY, + IAPI_CHANGE_BDWRAP, + IAPI_CHANGE_WATERMARK, + IAPI_CHANGE_SET_BDCONT, + IAPI_CHANGE_UNSET_BDCONT, + IAPI_CHANGE_SET_BDEXTD, + IAPI_CHANGE_UNSET_BDEXTD, + IAPI_CHANGE_EVTMASK1, + IAPI_CHANGE_EVTMASK2, + IAPI_CHANGE_PERIPHADDR, + IAPI_CHANGE_SET_BDINTR, + IAPI_CHANGE_UNSET_BDINTR, + IAPI_CHANGE_SET_TRANSFER_CD, + IAPI_CHANGE_FORCE_CLOSE, + IAPI_CHANGE_SET_TRANSFER, + IAPI_CHANGE_USER_ARG, + IAPI_CHANGE_SET_BUFFERADDR, + IAPI_CHANGE_SET_EXTDBUFFERADDR, + IAPI_CHANGE_SET_COMMAND, + IAPI_CHANGE_SET_COUNT, + IAPI_CHANGE_SET_STATUS, + IAPI_CHANGE_GET_BUFFERADDR, + IAPI_CHANGE_GET_EXTDBUFFERADDR, + IAPI_CHANGE_GET_COMMAND, + IAPI_CHANGE_GET_COUNT, + IAPI_CHANGE_GET_STATUS, + IAPI_CHANGE_SET_ENDIANNESS +}; + + +/* + * Public Function Prototype Section + */ +int iapi_Open ( channelDescriptor * cd_p, unsigned char channelNumber ); +int iapi_Close( channelDescriptor * cd_p ); +int iapi_Read ( channelDescriptor * cd_p, void * buf, unsigned short nbyte ); +int iapi_Write( channelDescriptor * cd_p, void * buf, unsigned short nbyte ); +int iapi_MemCopy(channelDescriptor * cd_p, void* dest, void* src, + unsigned long size); +int iapi_IoCtl( channelDescriptor * cd_p, unsigned long ctlRequest, + unsigned long param); + + +int iapi_Read_ipcv2( channelDescriptor * cd_p, void * data_control_struct_ipcv2); + +int iapi_Write_ipcv2( channelDescriptor * cd_p, void * data_control_struct_ipcv2); + +#ifdef MCU +int iapi_Init(channelDescriptor * cd_p, configs_data * config_p, + unsigned short* ram_image, unsigned short code_size, + unsigned long start_addr); +#endif /* MCU */ +#ifdef DSP +int iapi_Init(channelDescriptor * cd_p); +#endif /* DSP */ + +int iapi_StartChannel(unsigned char channel); +int iapi_StopChannel(unsigned char channel); +int iapi_SynchChannel(unsigned char channel); + +int iapi_GetChannelNumber(channelDescriptor * cd_p); +unsigned long iapi_GetError(channelDescriptor * cd_p); +int iapi_GetCount(channelDescriptor * cd_p); +int iapi_GetCountAll(channelDescriptor * cd_p); + +#ifndef IRQ_KEYWORD +#define IRQ_KEYWORD +#endif /* IRQ_KEYWORD */ + +IRQ_KEYWORD void IRQ_Handler(void); + +#ifdef MCU +int iapi_GetScript(channelDescriptor * cd_p, void * buf, unsigned short size, + unsigned long address); +int iapi_GetContext(channelDescriptor * cd_p, void * buf, + unsigned char channel); +int iapi_SetScript(channelDescriptor * cd_p, void * buf, unsigned short nbyte, + unsigned long destAddr); +int iapi_SetContext(channelDescriptor * cd_p, void * buf, + unsigned char channel); +int iapi_AssignScript(channelDescriptor * cd_p, script_data * data_p); + +int iapi_SetChannelEventMapping(unsigned char event, unsigned long channel_map); +#endif /* MCU */ + +#endif /* _iapiHigh_h */ diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/iapiLow.h linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/iapiLow.h --- linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/iapiLow.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/iapiLow.h 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,78 @@ +/****************************************************************************** + * + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiLow.h + * + * $Id iapiLow.h $ + * + * Description: + * prototypes for low level function of I.API + * + * + * + * + * $Log iapiLow.h + * + * ***************************************************************************/ + +#ifndef _iapiLow_h +#define _iapiLow_h + +/* **************************************************************************** + * Boolean identifiers + *****************************************************************************/ +#define NO_OS 0 +#define LINUX 1 +#define SYMBIAN 2 +#define WINCE 3 + +/* **************************************************************************** + * Include File Section + *****************************************************************************/ +#include "sdmaStruct.h" +#include "iapiDefaults.h" +#include "iapiOS.h" +#ifdef MCU +#include "iapiLowMcu.h" +#endif /*MCU*/ +#if OS == NO_OS +#include +#elif OS == LINUX +#include +#endif + + +/* **************************************************************************** + * Macro-command Section + *****************************************************************************/ + +#define GOTO_SLEEP(x) (iapi_GotoSleep)(x) +#define INIT_SLEEP(x) (iapi_InitSleep)(x) + +/* **************************************************************************** + * Public Function Prototype Section + *****************************************************************************/ +void iapi_lowStartChannel ( unsigned char channel ); +void iapi_lowStopChannel ( unsigned char channel ); +void iapi_AttachCallbackISR (channelDescriptor * cd_p, + void (* func_p)(channelDescriptor * cd_p, void * arg)); +void iapi_DetachCallbackISR (channelDescriptor * cd_p); +void iapi_ChangeCallbackISR (channelDescriptor * cd_p, + void (* func_p)(channelDescriptor * cd_p, void * arg)); +void iapi_lowSynchChannel ( unsigned char channel ); +void iapi_SetBufferDescriptor(bufferDescriptor *bd_p, unsigned char command, + unsigned char status, unsigned short count, + void * buffAddr, void * extBufferAddr); + +#endif /* _iapiLow_h */ diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/iapiLowDsp.h linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/iapiLowDsp.h --- linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/iapiLowDsp.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/iapiLowDsp.h 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,50 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* **************************************************************************** + * + * File: iapiLowDsp.h + * + * $Id iapiLowDsp.h $ + * + * Description: + * prototypes for low level function of I.API for DSP side only + * + * + * + * + * $Log iapiLowDsp.h + * + * ***************************************************************************/ + +#ifndef _iapiLowDsp_h +#define _iapiLowDsp_h + +/* **************************************************************************** + * Include File Section + *****************************************************************************/ + + +/* **************************************************************************** + * Public Function Prototype Section + *****************************************************************************/ +/* WARNING !!!!! + * This file is empty and it is normal, because there is no low level functions + * dedicated to the DSP but the file (iapi_LowDsp.h) must still exist because + * some project directly links the file. Previously, there were function + * iapi_EnableInterrupts,iapi_DisableInterrupts,iapi_WaitCore,iapi_StartChannel + * iapi_StopChannel but they are common to both MCU and DSP, so they have been + * moved to iapi_Low.h file. + */ + +#endif /* _iapiLowDsp_h */ diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/iapiLowMcu.h linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/iapiLowMcu.h --- linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/iapiLowMcu.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/iapiLowMcu.h 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,60 @@ +/****************************************************************************** + * + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiLowMcu.h + * + * $Id iapiLowMcu.h $ + * + * Description: + * prototypes for low level function of I.API of MCU side only + * + * + * + * + * $Log iapiLowMcu.h $ + * + * ***************************************************************************/ + +#ifndef _iapiLowMcu_h +#define _iapiLowMcu_h + +/****************************************************************************** + * Include File Section + *****************************************************************************/ +#include "sdmaStruct.h" +#include "iapiDefaults.h" + +/* **************************************************************************** + * Public Function Prototype Section + * ***************************************************************************/ + + +void iapi_InitChannelTables ( void ); +int iapi_ChannelConfig(unsigned char channel, unsigned eventOverride, + unsigned mcuOverride, unsigned dspOverride); +int iapi_Channel0Command(channelDescriptor * cd_p, void * buf, + unsigned short nbyte, unsigned char command); +void iapi_lowGetScript(channelDescriptor * cd_p, void * buf, unsigned short size, + unsigned long address); +void iapi_lowGetContext(channelDescriptor * cd_p, void * buf, + unsigned char channel); +void iapi_lowSetScript(channelDescriptor * cd_p, void * buf, unsigned short nbyte, + unsigned long destAddr); +void iapi_lowSetContext(channelDescriptor * cd_p, void * buf, + unsigned char channel); +int iapi_lowAssignScript(channelDescriptor * cd_p, script_data * data_p); + +int iapi_lowSetChannelEventMapping(unsigned char event, unsigned long channel_map); + +#endif /* _iapiLowMcu_h */ diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/iapiMiddle.h linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/iapiMiddle.h --- linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/iapiMiddle.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/iapiMiddle.h 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,52 @@ +/****************************************************************************** + * + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiMiddle.h + * + * $Id iapiMiddle.h $ + * + * Description: + * prototypes for middle level function of I.API + * + * + * + * + * $Log iapiMiddle.h + * + * ***************************************************************************/ + +#ifndef _iapiMiddle_h +#define _iapiMiddle_h + +/* **************************************************************************** + * Include File Section + ******************************************************************************/ +#include "sdmaStruct.h" +#ifdef MCU +#include "iapiMiddleMcu.h" +#endif /* MCU */ + +/* **************************************************************************** + * Public Function Prototype Section + ******************************************************************************/ +bufferDescriptor * iapi_AllocBD (channelControlBlock * ccb_p); +int iapi_AllocContext(contextData ** ctxd_p, unsigned char channel); +int iapi_AllocChannelDesc(channelDescriptor ** cd_p, unsigned char channel); +int iapi_ChangeChannelDesc (channelDescriptor * cd_p, + unsigned char whatToChange, unsigned long newval); +void iapi_InitializeCallbackISR (void (* func_p)(channelDescriptor * cd_p, + void * arg)); +int iapi_InitializeMemory (channelControlBlock * ccb_p); + +#endif /* iapiMiddle_h */ diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/iapiMiddleMcu.h linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/iapiMiddleMcu.h --- linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/iapiMiddleMcu.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/iapiMiddleMcu.h 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,41 @@ +/****************************************************************************** + * + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiMiddleMcu.h + * + * $Id iapiMiddleMcu.h $ + * + * Description: + * prototypes for middle level function of I.API + * + * + * + * + * $Log iapiMiddleMcu.h + * + * ***************************************************************************/ + +#ifndef _iapiMiddleMcu_h +#define _iapiMiddleMcu_h + +/* **************************************************************************** + * Include File Section + ******************************************************************************/ +#include "sdmaStruct.h" + +/* **************************************************************************** + * Public Function Prototype Section + ******************************************************************************/ + +#endif /* iapiMiddleMcu_h */ diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/iapiOS.h linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/iapiOS.h --- linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/iapiOS.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/iapiOS.h 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,96 @@ +/****************************************************************************** + * + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiOS.h + * + * $Id iapiOS.h $ + * + * Description: + * prototypes for OS level function of I.API + * + * + * + * + * $Log iapiOS.h + * + * ***************************************************************************/ + +#ifndef _iapiOS_h +#define _iapiOS_h + +/* **************************************************************************** + * Boolean identifiers + *****************************************************************************/ +#define NO_OS 0 +#define LINUX 1 +#define SYMBIAN 2 +#define WINCE 3 + +/* **************************************************************************** + * Include File Section + *****************************************************************************/ +#include "sdmaStruct.h" +#include "iapiDefaults.h" +#ifdef MCU +#include "iapiLowMcu.h" +#endif /*MCU*/ +#if OS == NO_OS +#include +#elif OS == LINUX +#include +#endif + +/* **************************************************************************** + * Macro-command Section + *****************************************************************************/ +#define SDMA_ERAM 0 +#define SDMA_IRAM 1 +#ifdef CONFIG_SDMA_IRAM +#define MALLOC(x, s) (s == SDMA_ERAM)? (* iapi_Malloc)(x):(* iapi_iram_Malloc)(x) +#else /*CONFIG_SDMA_IRAM */ +#define MALLOC(x, s) (* iapi_Malloc)(x) +#endif /*CONFIG_SDMA_IRAM */ +#define FREE(x) if (x!=NULL) (* iapi_Free)(x) + +#define GOTO_SLEEP(x) (iapi_GotoSleep)(x) +#define INIT_SLEEP(x) (iapi_InitSleep)(x) + +/* **************************************************************************** + * Public Function Prototype Section + *****************************************************************************/ + +#ifdef CONFIG_SDMA_IRAM +extern void*(* iapi_iram_Malloc) (size_t size); +#endif /*CONFIG_SDMA_IRAM*/ + +extern void*(* iapi_Malloc) (size_t size); +extern void (* iapi_Free) (void * ptr); + +extern void*(* iapi_Virt2Phys) (void * ptr); +extern void*(* iapi_Phys2Virt) (void * ptr); + +extern void (* iapi_WakeUp)(int); +extern void (* iapi_GotoSleep)(int); +extern void (* iapi_InitSleep)(int); + +extern void*(* iapi_memcpy)(void *dest, const void *src, size_t count); +extern void*(* iapi_memset)(void *dest, int c, size_t count); + +extern void (* iapi_EnableInterrupts)(void); +extern void (* iapi_DisableInterrupts)(void); + +extern int (* iapi_GetChannel)(int); +extern int (* iapi_ReleaseChannel)(int); + +#endif /* _iapiOS_h */ diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/sdmaStruct.h linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/sdmaStruct.h --- linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/include/sdmaStruct.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/include/sdmaStruct.h 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,426 @@ +/****************************************************************************** + * + * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: sdmaStruct.h + * + * $Id sdmaStruct.h $ + * + * Description: provides necessary definitions and inclusion for ipcmStruct.c + * + * $Log $ + * + *****************************************************************************/ +#ifndef _sdmaStruct_h +#define _sdmaStruct_h + +/* **************************************************************************** + * Include File Section + ******************************************************************************/ + +/* **************************************************************************** + * Macro-command Section + ******************************************************************************/ + +/** + * Identifier NULL + */ +#ifndef NULL +#define NULL 0 +#endif + +/** + * Boolean identifiers + */ +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + +/** + * Number of channels + */ +#define CH_NUM 32 +/** + * Number of events + */ +#ifdef MXC_SDMA_V2 +#define EVENTS_NUM 48 +#else +#define EVENTS_NUM 32 +#endif +/** + * Channel configuration + */ +#define DONT_OWN_CHANNEL 0 +#define OWN_CHANNEL 1 + +/** + * Ownership (value defined to computed decimal value) + */ +#define CH_OWNSHP_OFFSET_EVT 0 +#define CH_OWNSHP_OFFSET_MCU 1 +#define CH_OWNSHP_OFFSET_DSP 2 +/** + * Indexof the greg which holds address to start a script from when channel + * becomes current. + */ +#define SDMA_NUMBER_GREGS 8 + +/** + * Channel contexts management + */ + +#define CHANNEL_CONTEXT_BASE_ADDRESS 0x800 +/** + * Buffer descriptor status values. + */ +#define BD_DONE 0x01 +#define BD_WRAP 0x02 +#define BD_CONT 0x04 +#define BD_INTR 0x08 +#define BD_RROR 0x10 +#define BD_LAST 0x20 +#define BD_EXTD 0x80 + + +/** + * Data Node descriptor status values. + */ +#define DND_END_OF_FRAME 0x80 +#define DND_END_OF_XFER 0x40 +#define DND_DONE 0x20 +#define DND_UNUSED 0x01 + +/** + * IPCV2 descriptor status values. + */ +#define BD_IPCV2_END_OF_FRAME 0x40 + + +#define IPCV2_MAX_NODES 50 +/** + * Error bit set in the CCB status field by the SDMA, + * in setbd routine, in case of a transfer error + */ +#define DATA_ERROR 0x10000000 + +/** + * Buffer descriptor commands. + */ +#define C0_ADDR 0x01 +#define C0_LOAD 0x02 +#define C0_DUMP 0x03 +#define C0_SETCTX 0x07 +#define C0_GETCTX 0x03 +#define C0_SETDM 0x01 +#define C0_SETPM 0x04 +#define C0_GETDM 0x02 +#define C0_GETPM 0x08 +/** + * Transfer types, encoded in the BD command field + */ +#define TRANSFER_32BIT 0x00 +#define TRANSFER_8BIT 0x01 +#define TRANSFER_16BIT 0x02 +#define TRANSFER_24BIT 0x03 +/** + * Change endianness indicator in the BD command field + */ +#define CHANGE_ENDIANNESS 0x80 +/** + * Size in bytes + */ +#define SDMA_BD_SIZE 8 +#define SDMA_EXTENDED_BD_SIZE 12 +#define BD_NUMBER 4 +/** + * Channel interrupt policy + */ +#define DEFAULT_POLL 0 +#define CALLBACK_ISR 1 +/** + * Channel status + */ +#define UNINITIALIZED 0 +#define INITIALIZED 1 + +/** + * IoCtl particular values + */ +#define SET_BIT_ALL 0xFFFFFFFF +#define BD_NUM_OFFSET 16 +#define BD_NUM_MASK 0xFFFF0000 + +/** + * Maximum values for IoCtl calls, used in high or middle level calls + */ +#define MAX_BD_NUM 256 +#define MAX_BD_SIZE 65536 +#define MAX_BLOCKING 2 +#define MAX_SYNCH 2 +#define MAX_OWNERSHIP 8 +#define MAX_CH_PRIORITY 8 +#define MAX_TRUST 2 +#define MAX_WML 256 + + +/** + * Access to channelDescriptor fields + */ +enum { + IAPI_CHANNELNUMBER, + IAPI_BUFFERDESCNUMBER, + IAPI_BUFFERSIZE, + IAPI_BLOCKING, + IAPI_CALLBACKSYNCH, + IAPI_OWNERSHIP, + IAPI_PRIORITY, + IAPI_TRUST, + IAPI_UNUSED, + IAPI_CALLBACKISR_PTR, + IAPI_CCB_PTR, + IAPI_BDWRAP, + IAPI_WML +}; + +/** + * Default values for channel descriptor - nobody ownes the channel + */ +#define CD_DEFAULT_OWNERSHIP 7 + + +/** + * User Type Section + */ + +/** + * Command/Mode/Count of buffer descriptors + */ + +#if (ENDIANNESS==B_I_G_ENDIAN) +typedef struct iapi_modeCount_ipcv2 { + unsigned long status : 8; /**< L, E , D bits stored here */ + unsigned long reserved : 8; + unsigned long count : 16; /**< +#include + +#include "epm.h" +#include "iapi.h" + +#include +/* **************************************************************************** + * External Reference Section (for compatibility with already developed code) + *****************************************************************************/ +static void iapi_read_ipcv2_callback(struct iapi_channelDescriptor* cd_p, void* data); + +/* **************************************************************************** + * Global Variable Section + *****************************************************************************/ +#define MAX_CHANNEL 32 + +static dataNodeDescriptor* dnd_read_control_struct[MAX_CHANNEL]; + +/* MASK to get Nullify all the bits of Status in Data Node descriptor apart from L, E and D*/ + +#define GET_LED_MASK 0xE0 + +/*Table defines mapping of Data Node Descriptor to Buffer Descriptor status*/ + +static unsigned char dnd_2_bd_status[]= +{ +0x85, /*00 L = 0, E = 0, D = 0*/ +0x00, /*01*/ +0x00, /*02*/ +0x00, /*03*/ +0x00, /*04*/ +0x00, /*05*/ +0x00, /*06*/ +0x00, /*07*/ +0x00, /*08*/ +0x00, /*09*/ +0x00, /*0A*/ +0x00, /*0B*/ +0x00, /*0C*/ +0x00, /*0D*/ +0x00, /*0E*/ +0x00, /*0F*/ +0x00, /*10*/ +0x00,/*11*/ +0x00,/*12*/ +0x00,/*13*/ +0x00,/*14*/ +0x00,/*15*/ +0x00,/*16*/ +0x00,/*17*/ +0x00,/*18*/ +0x00,/*19*/ +0x00,/*1A*/ +0x00,/*1B*/ +0x00,/*1C*/ +0x00,/*1D*/ +0x00,/*1E*/ +0x00,/*1F*/ +0x84,/*20 L = 0, E = 0, D = 1 */ +0x00,/*21*/ +0x00,/*22*/ +0x00,/*23*/ +0x00,/*24*/ +0x00,/*25*/ +0x00,/*26*/ +0x00,/*27*/ +0x00,/*28*/ +0x00,/*29*/ +0x00,/*2A*/ +0x00,/*2B*/ +0x00,/*2C*/ +0x00,/*2D*/ +0x00,/*2E*/ +0x00,/*2F*/ +0x00,/*30*/ +0x00,/*31*/ +0x00,/*32*/ +0x00,/*33*/ +0x00,/*34*/ +0x00,/*35*/ +0x00,/*36*/ +0x00,/*37*/ +0x00,/*38*/ +0x00,/*39*/ +0x00,/*3A*/ +0x00,/*3B*/ +0x00,/*3C*/ +0x00,/*3D*/ +0x00,/*3E*/ +0x00,/*3F*/ +0xAB,/*40 L = 0, E = 1, D = 0*/ +0x00,/*41*/ +0x00,/*42*/ +0x00,/*43*/ +0x00,/*44*/ +0x00,/*45*/ +0x00,/*46*/ +0x00,/*47*/ +0x00,/*48*/ +0x00,/*49*/ +0x00,/*4A*/ +0x00,/*4B*/ +0x00,/*4C*/ +0x00,/*4D*/ +0x00,/*4E*/ +0x00,/*4F*/ +0x00,/*50*/ +0x00,/*51*/ +0x00,/*52*/ +0x00,/*53*/ +0x00,/*54*/ +0x00,/*55*/ +0x00,/*56*/ +0x00,/*57*/ +0x00,/*58*/ +0x00,/*59*/ +0x00,/*5A*/ +0x00,/*5B*/ +0x00,/*5C*/ +0x00,/*5D*/ +0x00,/*5E*/ +0x00,/*5F*/ +0xAA,/*60 L = 0, E = 1, D = 1*/ +0x00,/*61*/ +0x00,/*62*/ +0x00,/*63*/ +0x00,/*64*/ +0x00,/*65*/ +0x00,/*66*/ +0x00,/*67*/ +0x00,/*68*/ +0x00,/*69*/ +0x00,/*6A*/ +0x00,/*6B*/ +0x00,/*6C*/ +0x00,/*6D*/ +0x00,/*6E*/ +0x00,/*6F*/ +0x00,/*70*/ +0x00,/*71*/ +0x00,/*72*/ +0x00,/*73*/ +0x00,/*74*/ +0x00,/*75*/ +0x00,/*76*/ +0x00,/*77*/ +0x00,/*78*/ +0x00,/*79*/ +0x00,/*7A*/ +0x00,/*7B*/ +0x00,/*7C*/ +0x00,/*7D*/ +0x00,/*7E*/ +0x00,/*7F*/ +0xC5,/*80 L = 1, E = 0, D = 0*/ +0x00,/*81*/ +0x00,/*82*/ +0x00,/*83*/ +0x00,/*84*/ +0x00,/*85*/ +0x00,/*86*/ +0x00,/*87*/ +0x00,/*88*/ +0x00,/*89*/ +0x00,/*8A*/ +0x00,/*8B*/ +0x00,/*8C*/ +0x00,/*8D*/ +0x00,/*8E*/ +0x00,/*8F*/ +0x00,/*90*/ +0x00,/*91*/ +0x00,/*92*/ +0x00,/*93*/ +0x00,/*94*/ +0x00,/*95*/ +0x00,/*96*/ +0x00,/*97*/ +0x00,/*98*/ +0x00,/*99*/ +0x00,/*9A*/ +0x00,/*9B*/ +0x00,/*9C*/ +0x00,/*9D*/ +0x00,/*9E*/ +0x00,/*9F*/ +0xC4,/*A0 L = 1, E = 0, D = 1*/ +0x00,/*A1*/ +0x00,/*A2*/ +0x00,/*A3*/ +0x00,/*A4*/ +0x00,/*A5*/ +0x00,/*A6*/ +0x00,/*A7*/ +0x00,/*A8*/ +0x00,/*A9*/ +0x00,/*AA*/ +0x00,/*AB*/ +0x00,/*AC*/ +0x00,/*AD*/ +0x00,/*AE*/ +0x00,/*AF*/ +0x00,/*B0*/ +0x00,/*B1*/ +0x00,/*B2*/ +0x00,/*B3*/ +0x00,/*B4*/ +0x00,/*B5*/ +0x00,/*B6*/ +0x00,/*B7*/ +0x00,/*B8*/ +0x00,/*B9*/ +0x00,/*BA*/ +0x00,/*BB*/ +0x00,/*BC*/ +0x00,/*BD*/ +0x00,/*BE*/ +0x00,/*BF*/ +0xEB,/*C0 L = 1, E = 1, D = 0*/ +0x00,/*C1*/ +0x00,/*C2*/ +0x00,/*C3*/ +0x00,/*C4*/ +0x00,/*C5*/ +0x00,/*C6*/ +0x00,/*C7*/ +0x00,/*C8*/ +0x00,/*C9*/ +0x00,/*CA*/ +0x00,/*CB*/ +0x00,/*CC*/ +0x00,/*CD*/ +0x00,/*CE*/ +0x00,/*CF*/ +0x00,/*D0*/ +0x00,/*D1*/ +0x00,/*D2*/ +0x00,/*D3*/ +0x00,/*D4*/ +0x00,/*D5*/ +0x00,/*D6*/ +0x00,/*D7*/ +0x00,/*D8*/ +0x00,/*D9*/ +0x00,/*DA*/ +0x00,/*DB*/ +0x00,/*DC*/ +0x00,/*DD*/ +0x00,/*DE*/ +0x00,/*DF*/ +0xEA,/*E0 L = 1, E = 1, D = 1*/ +0x00,/*E1*/ +0x00,/*E2*/ +0x00,/*E3*/ +0x00,/*E4*/ +0x00,/*E5*/ +0x00,/*E6*/ +0x00,/*E7*/ +0x00,/*E8*/ +0x00,/*E9*/ +0x00,/*EA*/ +0x00,/*EB*/ +0x00,/*EC*/ +0x00,/*ED*/ +0x00,/*EE*/ +0x00,/*EF*/ +0x00,/*F0*/ +0x00,/*F1*/ +0x00,/*F2*/ +0x00,/*F3*/ +0x00,/*F4*/ +0x00,/*F5*/ +0x00,/*F6*/ +0x00,/*F7*/ +0x00,/*F8*/ +0x00,/*F9*/ +0x00,/*FA*/ +0x00,/*FB*/ +0x00,/*FC*/ +0x00,/*FD*/ +0x00,/*FE*/ +0x00/*FF*/ +}; +/* **************************************************************************** + * Function Section + *****************************************************************************/ + +/* ***************************************************************************/ +/**Opens an SDMA channel to be used by the library. + * + * Algorithm:\n + * + * - Check if initialization is necessary. + * - Check that user initialized OS dependant functions. + * - Test validity of input parameters + * - Check whole channel control block data structure + * - Finish initializations (tables with default values) + * - Initialize channel 0 is dedicated to communications with SDMA + * - Check channel control block definition + * - if the channel descriptor is not initialized, initialize it with + * the default value + * - If buffer descriptor already allocated, exit with iapi_errno filled + * complete the lowest bits with the number of 'D' bits set + * - Buffer Descriptors allocation + * - Channel's configuration properties (mcu side only) + * - read/write direction => enable/disable channel setting + * + * @param *cd_p -If channelNumber is 0, it is pointer to channel descriptor for the channnel 0 to be opened and + has default values. + * For other channels,this function should be called after channel 0 has been opened, and it is channel descriptor for + channel 0.Must be allocated. + * @param channelNumber channel to be opened + * + * @return + * - IAPI_SUCCESS : OK + * - -iapi_errno : close failed, return negated value of iapi_errno + */ +int +iapi_Open (channelDescriptor * cd_p, unsigned char channelNumber) +{ + channelControlBlock * ccb_p; + channelControlBlock * local_ccb_p; + channelDescriptor * local_cd_p; + bufferDescriptor * bd_p; + unsigned char index = 0; + int result = IAPI_SUCCESS; +#ifdef MCU + volatile unsigned long * channelPriorityMatx; +#endif /* MCU */ + + + /* + * 1. Check if initialization is necessary + */ + if (cd_p == NULL){ + result = IAPI_ERR_CD_UNINITIALIZED | + IAPI_ERR_CH_AVAILABLE | channelNumber; + iapi_errno = result; + return -result; + } + + /* Verify these functions every time*/ + if((iapi_GetChannel == NULL)||(iapi_ReleaseChannel == NULL)) + { + result = IAPI_ERR_NO_OS_FN | channelNumber; + iapi_errno = result; + return -result; + } + + /* Try to aquire channel*/ + if(iapi_GetChannel(channelNumber) != 0) + { + result = IAPI_ERR_CH_IN_USE | channelNumber; + iapi_errno = result; + return -result; + } + + if (channelNumber == 0 && cd_p->ccb_ptr == NULL){ + /* Verify that the user initialized all OS dependant functions required + * by the library. + */ + if((iapi_Malloc == NULL)||(iapi_Free == NULL)||(iapi_Virt2Phys == NULL)|| + (iapi_Phys2Virt == NULL)||(iapi_GotoSleep == NULL)|| + (iapi_WakeUp == NULL)||(iapi_InitSleep == NULL)||(iapi_memset == NULL)|| + (iapi_memcpy == NULL)) + { + result = IAPI_ERR_NO_OS_FN | channelNumber; + iapi_errno = result; + iapi_ReleaseChannel(channelNumber); + return -result; + } + /* Whole channel control block data structure */ + ccb_p = (channelControlBlock *) + MALLOC(CH_NUM*sizeof(channelControlBlock), SDMA_IRAM); + if (ccb_p == NULL){ + result = IAPI_ERR_CCB_ALLOC_FAILED | + IAPI_ERR_CH_AVAILABLE | channelNumber; + iapi_errno = result; + iapi_ReleaseChannel(channelNumber); + return -result; + } + /* Zero-out the CCB structures array just allocated*/ + iapi_memset(ccb_p, 0x00, CH_NUM*sizeof(channelControlBlock)); + /* Save the address of the CCB structures array*/ + iapi_CCBHead = ccb_p; + + cd_p->ccb_ptr = (struct iapi_channelControlBlock *)ccb_p; + ccb_p->channelDescriptor = cd_p; +#ifdef MCU + /* finish initializations */ + iapi_InitChannelTables(); +#endif /* MCU */ + /* Channel 0 is dedicated to communications with SDMA */ + cd_p->ownership = ((DONT_OWN_CHANNEL << CH_OWNSHP_OFFSET_EVT ) | + ( OWN_CHANNEL << CH_OWNSHP_OFFSET_MCU ) | + (DONT_OWN_CHANNEL << CH_OWNSHP_OFFSET_DSP )); + cd_p->bufferDescNumber = 1; + } + + /* + * 2. Check channel control block + */ + ccb_p = cd_p->ccb_ptr; + if (ccb_p == NULL){ + result = IAPI_ERR_NO_CCB_DEFINED | IAPI_ERR_CH_AVAILABLE|channelNumber; + iapi_errno = result; + iapi_ReleaseChannel(channelNumber); + return -result; + } + + /* Control block & Descriptor associated with the channel being worked on */ + local_ccb_p = &ccb_p[channelNumber]; + local_cd_p = ccb_p[channelNumber].channelDescriptor; + + /* If the channel is not initialized, initialize it with the default value */ + if (local_cd_p == NULL){ + result = iapi_AllocChannelDesc (&local_cd_p, channelNumber); + if ( result!= IAPI_SUCCESS) + { + iapi_ReleaseChannel(channelNumber); + return result; //is allready negated from iapi_AllocChannelDesc + } + + local_cd_p->ccb_ptr = (struct iapi_channelControlBlock *)local_ccb_p; + local_ccb_p->channelDescriptor = local_cd_p; + } + + /* + * 3. If buffer descriptor already allocated, exit with iapi_errno filled + */ + if ( local_ccb_p->baseBDptr != NULL ){ + bd_p = (bufferDescriptor *)iapi_Phys2Virt(local_ccb_p->baseBDptr); + result = IAPI_ERR_BD_ALLOCATED; + for (index=1 ; index< local_cd_p->bufferDescNumber ; index++){ + if ((bd_p->mode.status & BD_DONE) == BD_DONE){ + /* complete the lowest bits with the number of 'D' bits set */ + result++; + } + bd_p++; + } + iapi_errno = result; + iapi_ReleaseChannel(channelNumber); + return -result; + } + + /* + * 4. Buffer Descriptors allocation + */ + iapi_InitializeMemory(local_ccb_p); + +#ifdef MCU + /* + * 5. Channel's configuration properties (mcu side only) + */ + iapi_ChannelConfig( channelNumber, + ( local_cd_p->ownership >> CH_OWNSHP_OFFSET_EVT ) & 1UL, + ( local_cd_p->ownership >> CH_OWNSHP_OFFSET_MCU ) & 1UL, + ( local_cd_p->ownership >> CH_OWNSHP_OFFSET_DSP ) & 1UL); +#endif /* MCU */ + + /* Setting interrupt handling */ + iapi_ChangeCallbackISR(local_cd_p, local_cd_p->callbackISR_ptr); + + /* Call initialization fn for polling synch on this channel*/ + INIT_SLEEP(channelNumber); + + /* No user arg pointer yet*/ + userArgTable[cd_p->channelNumber]= NULL; + + /* + * 6. read/write direction => enable/disable channel + */ +#ifdef MCU + channelPriorityMatx = &SDMA_CHNPRI_0; + channelPriorityMatx[channelNumber] = 1; +#endif /* MCU */ + + local_ccb_p->status.openedInit = TRUE; + iapi_ReleaseChannel(channelNumber); + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/** Attempts to read nbyte from the data buffer descriptor associated with the + * channel channelNumber, into the user's data buffer pointed to by buf. + * + * Algorithm:\n + * - Check data structures are properly initialized: + * - Channel descriptor validity + * - Control block & Descriptor associated with the channel being worked on + * - Check initialization has been done for trusted channels + * - If transfer data size is used, check validity of combination transfer + * size/requested bytes + * - Set the 'D' done bits on all buffer descriptors + * - Starting of the channel + * - Synchronization mechanism handling: + * - for callback: just exit function + * - for polling: call the synchronization function then read data from + * buffer until either nbyte parameter is reached or all buffer descriptors + * have been processed. + * + * Notes:\n + * 1) Virtual DMA SDMA channels are unidirectional, an iapi_Read authorized + * on a channel means that we are expecting to receive from the SDMA. The + * meaning of an interrupt received from the SDMA is therefore that the + * data has been copied from the SDMA to the host's data buffers and is + * already passed on upper layers of the application.\n + * + * @param *cd_p chanenl descriptor for the channel to read from + * @param *buf buffer to receive the data + * @param nbyte number of bytes to read from channel + * + * @return + * - number of bytes read + * - -iapi_errno : in case of failure return negated value of iapi_errno + */ +int +iapi_Read (channelDescriptor * cd_p, void * buf, unsigned short nbyte) +{ + int index = 0; + int readBytes; + int toRead; + int result = IAPI_SUCCESS; + unsigned int copyFinished; + int bufsize; + bufferDescriptor * bd_p; + channelControlBlock * ccb_p; + unsigned char * local_buf; + unsigned char chNum; + unsigned char div; + + iapi_errno = IAPI_ERR_NO_ERROR; + + /* + * 1. Check data structures are properly initialized + */ + /* Channel descriptor validity */ + if (cd_p == NULL){ + result = IAPI_ERR_CD_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* Channel control block validity */ + if (cd_p->ccb_ptr == NULL){ + result = IAPI_ERR_CCB_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* Control block & Descriptor associated with the channel being worked on */ + chNum = cd_p->channelNumber; + ccb_p = cd_p->ccb_ptr; + + /* Try to aquire channel*/ + if(iapi_GetChannel(chNum) != 0) + { + result = IAPI_ERR_CH_IN_USE | chNum; + iapi_errno = result; + return -result; + } + + /* Check if channel is already opened/initialized */ + if (ccb_p->status.openedInit == FALSE) { + result = IAPI_ERR_CHANNEL_UNINITIALIZED | IAPI_ERR_CH_AVAILABLE | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + + /* Buffer descriptor validity */ + bd_p = (bufferDescriptor *)iapi_Phys2Virt(ccb_p->baseBDptr); + if (bd_p == NULL ){ + result = IAPI_ERR_BD_UNINITIALIZED | IAPI_ERR_CH_AVAILABLE | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + + + /* Check initialization has been done for trusted channels */ + if (cd_p->trust == TRUE) { + bd_p = (bufferDescriptor *)iapi_Phys2Virt(ccb_p->baseBDptr); + for(index=0 ; index < cd_p->bufferDescNumber ; index++){ + if ((bd_p->bufferAddr == NULL) || (bd_p->mode.count == 0)){ + result = IAPI_ERR_BD_UNINITIALIZED | IAPI_ERR_CH_AVAILABLE | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + bd_p++; + } + } + + bd_p = (bufferDescriptor *)iapi_Phys2Virt(ccb_p->baseBDptr); + /*If transfer data size is used, check that the required read length is + * divisible by transfer data size expressed in bytes + */ + if(cd_p->useDataSize) + { + /*Check for divisibility only if data size different then 8bit*/ + if(cd_p->dataSize != TRANSFER_8BIT) + { + switch(cd_p->dataSize) + { + case TRANSFER_32BIT: + div = 4; + break; + case TRANSFER_16BIT: + div = 2; + break; + case TRANSFER_24BIT: + div = 3; + break; + /*we should not get to default*/ + default: + result = IAPI_ERR_INVALID_PARAMETER | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + /*check the total number of bytes requested*/ + if((nbyte % div) != 0) + { + result = IAPI_ERR_INVALID_PARAMETER | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + /*now check the length of every BD*/ + for(index=0 ; index < cd_p->bufferDescNumber ; index++) + { + if((bd_p->mode.count % div) != 0) + { + result = IAPI_ERR_INVALID_PARAMETER | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + bd_p++; + } + } + } + + /* + * 2. Set the 'D' done bits on all buffer descriptors + */ + bd_p = (bufferDescriptor *)iapi_Phys2Virt(ccb_p->baseBDptr); + for (index=0 ; index < cd_p->bufferDescNumber ; index++) { + bd_p->mode.status |= BD_DONE; + bd_p++; + } + + /* + * 3. Starting of the channel + */ + iapi_lowStartChannel (chNum); + ccb_p->status.execute = TRUE; + readBytes = 0; + + /* + * 4. Synchronization mechanism handling + */ + if( cd_p->callbackSynch == DEFAULT_POLL){ + iapi_SynchChannel(chNum); + + bd_p = (bufferDescriptor *)iapi_Phys2Virt(ccb_p->baseBDptr); + toRead = nbyte; + copyFinished = FALSE; + local_buf = (unsigned char *)buf; + + /* + * Check the 'RROR' bit on all buffer descriptors, set error number + * and return IAPI_FAILURE if set. + */ + for (index=0 ; index < cd_p->bufferDescNumber ; index++) + { + if(bd_p->mode.status & BD_RROR) + { + result = IAPI_ERR_RROR_BIT_READ | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + bd_p++; + } + + + /* + * 5. Read loop + */ + + bd_p = (bufferDescriptor *)iapi_Phys2Virt(ccb_p->baseBDptr); + while (!copyFinished) + { + if (!(bd_p->mode.status & BD_DONE)) + { + if (cd_p->trust == FALSE) { + bufsize = cd_p->bufferSize; + } else { + bufsize = bd_p->mode.count; + } + /*if L bit is set, read only "count" bytes and exit the loop*/ + if(bd_p->mode.status & BD_LAST) + { + bufsize = bd_p->mode.count; + copyFinished = TRUE; + } + if (toRead > bufsize) + { + if (cd_p->trust == FALSE) + { + iapi_memcpy(local_buf, iapi_Phys2Virt(bd_p->bufferAddr), bufsize); + local_buf += bufsize; + } + readBytes += bufsize; + toRead -= bufsize; + /*advance bd_p only if bit L is not set. The loop will exit anyway.*/ + if(!(bd_p->mode.status & BD_LAST)) + { + if (bd_p->mode.status & BD_WRAP) + { + bd_p = (bufferDescriptor *)iapi_Phys2Virt(ccb_p->baseBDptr); + } + else if(((bufferDescriptor *)iapi_Phys2Virt(ccb_p->baseBDptr) + + (cd_p->bufferDescNumber - 1)*sizeof(bufferDescriptor)) != bd_p) + { + bd_p++; + } + else + { + /* finished here : end of buffer descriptors */ + copyFinished = TRUE; + } + } + } + else + { + if (cd_p->trust == FALSE) + { + iapi_memcpy(local_buf, iapi_Phys2Virt(bd_p->bufferAddr), toRead); + local_buf += toRead; + } + readBytes += toRead; + toRead = 0; + /* finished successfully : readBytes = nbytes */ + copyFinished = TRUE; + } + } + else + { + /* finished here : buffer not already done*/ + copyFinished = TRUE; + } + } + iapi_ReleaseChannel(chNum); + } + + /* + *If synchronization type is callback, the user of I.API must + *release the channel + */ + return readBytes; +} + +/* ***************************************************************************/ +/*Attempts to write nbyte from the buffer pointed to by buf to the channel + * data buffers associated with the opened channel number channelNumber + * + * Algorithm:\n + * + * - Check data structures are properly initialized: + * - Channel descriptor validity + * - Channel control block validity + * - Buffer descriptor validity + * - If transfer data size is used, check validity of combination transfer + * size/requested bytes + * - Write loop\n + * Write occurs in the buffer acceded form buffer descriptor and continues + * to the "next" buffer which can be:\n + * -# the last BD of the ring so re-start from beginning\n + * -# the last BD of the BD array but no ring so finish\n + * -# (general case) the next BD in the BD array\n + * And copy continues until data fit in the current buffer or the nbyte + * parameter is reached. + * - Starting of the channel + * + * Notes:\n + * 1) Virtual DMA SDMA channels are unidirectionnal, an iapi_Write authorized + * on a channel means that we are expecting to send to the SDMA. The + * meaning of an interrupt received from the SDMA is therfore that the + * data has been delivered to the SDMA. + * + * @param *cd_p chanenl descriptor for the channel to write to + * @param *buf buffer with data to be written + * @param nbyte number of bytes to write to channel + * + * @return + * - number of bytes written + * - -iapi_errno if failure + */ +int +iapi_Write (channelDescriptor * cd_p, void * buf, unsigned short nbyte) +{ + unsigned int writtenBytes = 0; + unsigned int toWrite; + int result = IAPI_SUCCESS; + unsigned int copyFinished; + unsigned int buffsize; + unsigned int index = 0; + bufferDescriptor * bd_p; + channelControlBlock * ccb_p; + unsigned char * local_buf; + unsigned char chNum; + unsigned char div; + + iapi_errno = IAPI_ERR_NO_ERROR; + + /* + * 1. Check data structures are properly initialized + */ + /* Channel descriptor validity */ + if (cd_p == NULL){ + result = IAPI_ERR_CD_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* Channel control block validity */ + if (cd_p->ccb_ptr == NULL){ + result = IAPI_ERR_CCB_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* Control block & Descriptpor associated with the channel being worked on */ + chNum = cd_p->channelNumber; + ccb_p = cd_p->ccb_ptr; + + /* Try to aquire channel*/ + if(iapi_GetChannel(chNum) != 0) + { + result = IAPI_ERR_CH_IN_USE | chNum; + iapi_errno = result; + return -result; + } + + /* Buffer descriptor validity */ + bd_p = (bufferDescriptor *)iapi_Phys2Virt(ccb_p->baseBDptr); + if (bd_p == NULL ){ + result = IAPI_ERR_BD_UNINITIALIZED | IAPI_ERR_CH_AVAILABLE | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + + /* Check initialization has been done for trusted channels */ + if (cd_p->trust == TRUE) { + bd_p = (bufferDescriptor *)iapi_Phys2Virt(ccb_p->baseBDptr); + for(index=0 ; index < cd_p->bufferDescNumber ; index++){ + if ((bd_p->bufferAddr == NULL) || (bd_p->mode.count == 0)){ + result = IAPI_ERR_BD_UNINITIALIZED | IAPI_ERR_CH_AVAILABLE | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + bd_p++; + } + } + + + bd_p = (bufferDescriptor *)iapi_Phys2Virt(ccb_p->baseBDptr); + /*If transfer data size is used, check that the required write length is + * divisible by transfer data size expressed in bytes + */ + if(cd_p->useDataSize) + { + /*Check for divisibility only if data size different then 8bit*/ + if(cd_p->dataSize != TRANSFER_8BIT) + { + switch(cd_p->dataSize) + { + case TRANSFER_32BIT: + div = 4; + break; + case TRANSFER_16BIT: + div = 2; + break; + case TRANSFER_24BIT: + div = 3; + break; + /*we should not get to default*/ + default: + result = IAPI_ERR_INVALID_PARAMETER | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + /*check the total number of bytes requested*/ + if((nbyte % div) != 0) + { + result = IAPI_ERR_INVALID_PARAMETER | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + /*now check the length of every BD*/ + for(index=0 ; index < cd_p->bufferDescNumber ; index++) + { + if((bd_p->mode.count % div) != 0) + { + result = IAPI_ERR_INVALID_PARAMETER | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + bd_p++; + } + } + } + + /* + * 2. Write loop + */ + + local_buf = (unsigned char *)buf; + toWrite = nbyte; + copyFinished = FALSE; + bd_p = (bufferDescriptor *)iapi_Phys2Virt(ccb_p->baseBDptr); + + while (!copyFinished){ + + /* variable buffsize contains the nb of bytes that the SDMA will transfer at each pass of the while loop*/ + + /* in NON trusted mode, buffsize is copied from Channel descriptor bufferSize (same size for all transfers) */ + if (cd_p->trust == FALSE) { + buffsize = cd_p->bufferSize; + } + /* in TRUSTED mode, it's up to the user to specify the size of each buffer thru an IoCtl call */ + /* This IoCtl has directly modified the bd_p->mode.count */ + /* therefore, buffersize is copied from the bd_p->mode.count */ + else { + buffsize = bd_p->mode.count; + } + + /* in any mode (trusted or non trusted), the transfer size must be overridden by */ + /* "toWrite" when there is less remaining bytes to transfer than the current buffer size */ + if (toWrite < buffsize) { + buffsize = toWrite; + } + + + if (!(bd_p->mode.status & BD_DONE)){ + /* More data to write than a single buffer can contain */ + if (cd_p->trust == FALSE ){ + iapi_memcpy(iapi_Phys2Virt(bd_p->bufferAddr), local_buf, buffsize); + local_buf += buffsize; + } + + /* update the BD count that will be used by the SDMA to transfer the proper nb of bytes */ + bd_p->mode.count = buffsize; + + bd_p->mode.status |= BD_DONE; + writtenBytes += buffsize; + toWrite -= buffsize; + /* Prepares access to the "next" buffer */ + /* - case 1 - finished successfully : writtenBytes = nbytes */ + if (toWrite == 0) { + copyFinished = TRUE; + } + /* - case 2 - Last BD and WRAP bit set so re-start from beginning */ + /*else if ((bd_p->mode.status & BD_WRAP)){ + bd_p = (bufferDescriptor *)iapi_Phys2Virt(ccb_p->baseBDptr); + }*/ + /* - case 3 - Last BD of the BD but nor ring*/ + else if (((bufferDescriptor *)iapi_Phys2Virt(ccb_p->baseBDptr) + + (cd_p->bufferDescNumber - 1) * sizeof(bufferDescriptor)) == bd_p){ + copyFinished = TRUE; + } + /* - case 4 - general : next BD in the BD array */ + else { + bd_p++; + } + + } else { + /* finished here : buffer not already done */ + copyFinished = TRUE; + } + } + + ccb_p->currentBDptr = ccb_p->baseBDptr; + + /* + * 3. Starting of the channel + */ + iapi_lowStartChannel(chNum); + ccb_p->status.execute = TRUE; + + if( cd_p->callbackSynch == DEFAULT_POLL) + { + iapi_SynchChannel(chNum); + /* + * Check the 'RROR' bit on all buffer descriptors, set error number + * and return IAPI_FAILURE if set. + */ + bd_p = (bufferDescriptor *)iapi_Phys2Virt(ccb_p->baseBDptr); + for (index=0 ; index < cd_p->bufferDescNumber ; index++) + { + if(bd_p->mode.status & BD_RROR) + { + result = IAPI_ERR_RROR_BIT_WRITE | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + bd_p++; + } + iapi_ReleaseChannel(chNum); + } + + /* + *If synchronization type is callback, the user of I.API must + *release the channel + */ + return writtenBytes; +} + + + + +/* ***************************************************************************/ +/* This function is used to receive data from the SDMA. + * + * Algorithm:\n + * + * The data control structure would be copied to IPCv1 complied Buffer + * Descriptor Array. This array shall be allocated from non cacheable memory. + * It would then provide this buffer descriptor array as an input to SDMA using + * channel control block and then configure the Host Enable (HE) or + * DSP enable (DE) bit of SDMA for the channel used for this transfer depending + * on the source. + * + * Notes:\n + * Virtual DMA channels are unidirectional, an iapi_Write_ipcv2 authorized + * on a channel means that source processor is expecting to send to the destination + * processor. The meaning of an interrupt received from the SDMA notifies that the + * data has been delivered to the destination processor. + * + * @param *cd_p chanenl descriptor for the channel to receive from + * @param *data_control_struct_ipcv2 + + * Data Control structure: + * ------------------------- + * | Data Node Descriptor 1| + * ------------------------- + * | Data Node Descriptor 2| + * ------------------------- + * | : | + * | : | + * ------------------------- + * |Data Node Descriptor n | + * ------------------------- + * + * Data Node Descriptor (Buffer Descriptor): + *------------------------------------------------------------------------------ + *| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 … 0| + *------------------------------------------------------------------------------ + *| L E D R R R R R |<---- Reserved ----> |<- Length-> | + *------------------------------------------------------------------------------ + *| <---------------------------- Data Ptr ----------------------------------->| + *------------------------------------------------------------------------------ + * + * L bit (LAST): If set, means that this buffer of data is the last buffer of the frame + * E bit (END): If set, we reached the end of the buffers passed to the function + * D bit (DONE): Only valid on the read callback. When set, means that the buffer has been + * filled by the SDMA. + * Length: Length of data pointed by this node in bytes + * Data Ptr: Pointer to the data pointed to by this node. + * The Function Shall not be called for the same channel unless the Read callback has been + * received for channel for which it has been called already. + * + * @return + * - IAPI_SUCCESS on success, IAPI_ERROR otherwise + * + *- -iapi_errno if failure + */ + +int iapi_Read_ipcv2( channelDescriptor * cd_p, void * data_control_struct_ipcv2) +{ + channelControlBlock * ccb_p; + + +/* The Parameters passed are considered to be validated by the upper layers*/ + + bufferDescriptor_ipcv1_v2 *bd_ipcv2_p; + dataNodeDescriptor *dnd_p = (dataNodeDescriptor*)data_control_struct_ipcv2; + + ccb_p = cd_p->ccb_ptr; + iapi_errno = IAPI_ERR_NO_ERROR; + + if(ccb_p->baseBDptr == NULL) +{ + iapi_errno = IAPI_ERR_BD_UNINITIALIZED; + return -(IAPI_ERR_BD_UNINITIALIZED); +} + + ccb_p->currentBDptr = ccb_p->baseBDptr; + + /* Copy the data Node descriptor information to new BDs */ + bd_ipcv2_p = (bufferDescriptor_ipcv1_v2*)iapi_Phys2Virt(ccb_p->baseBDptr); + + while(1) + { + bd_ipcv2_p->bufferAddr = dnd_p->bufferAddr; + bd_ipcv2_p->mode.count = dnd_p->mode.count; +#ifdef MCU + bd_ipcv2_p->mode.endianness = 1; +#endif +#ifdef DSP + bd_ipcv2_p->mode.endianness = 0; +#endif + + bd_ipcv2_p->mode.status = dnd_2_bd_status[dnd_p->mode.status & GET_LED_MASK]; + + if((dnd_p->mode.status & DND_END_OF_XFER) != 0) + { + /* Break the loop at End of Transfer */ + break; + + } + bd_ipcv2_p++; + dnd_p++; + + } + /* + * Store the buffer address + */ + dnd_read_control_struct[cd_p->channelNumber] = (dataNodeDescriptor*)data_control_struct_ipcv2; + /* + * Register the Call Back + */ + + iapi_AttachCallbackISR(cd_p, iapi_read_ipcv2_callback); + + /* + * Starting of the channel + */ + iapi_lowStartChannel(cd_p->channelNumber); + ccb_p->status.execute = TRUE; + + return IAPI_SUCCESS; + +} + + +/* ***************************************************************************/ +/* + * The function is used send a group of buffers to SDMA. + * Algorithm:\n + * + * The data control structure would be copied to IPCv1 complied Buffer + * Descriptor Array. This array shall be allocated from non cacheable memory. + * It would then provide this buffer descriptor array as an input to SDMA using + * channel control block and then configure the Host Enable (HE) or + * DSP enable (DE) bit of SDMA for the channel used for this transfer depending + * on the source. + * The Function Shall not be called for the same channel unless the Read callback has been + * received for channel for which it has been called already. + * + * Notes:\n + * Virtual DMA channels are unidirectional, an iapi_Write_ipcv2 authorized + * on a channel means that source processor is expecting to send to the destination + * processor. The meaning of an interrupt received from the SDMA notifies that the + * data has been delivered to the destination processor. + * + * @param *cd_p chanenl descriptor for the channel to write to + * @param *data_control_struct_ipcv2 + + * Data Control structure: + * ------------------------- + * | Data Node Descriptor 1| + * ------------------------- + * | Data Node Descriptor 2| + * ------------------------- + * | : | + * | : | + * ------------------------- + * |Data Node Descriptor n | + * ------------------------- + * + * Data Node Descriptor (Buffer Descriptor): + *------------------------------------------------------------------------------ + *| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 … 0| + *------------------------------------------------------------------------------ + *| L E D R R R R R |<---- Reserved ----> |<- Length-> | + *------------------------------------------------------------------------------ + *| <---------------------------- Data Ptr ----------------------------------->| + *------------------------------------------------------------------------------ + * + * L bit (LAST): If set, means that this buffer of data is the last buffer of the frame + * E bit (END): If set, we reached the end of the buffers passed to the function + * D bit (DONE): Only valid on the read callback. When set, means that the buffer has been + * filled by the SDMA. + * Length: Length of data pointed by this node in bytes + * Data Ptr: Pointer to the data pointed to by this node. + * + * + * @return + * - iapi sucess on success. + * - -iapi_errno if failure + */ + +int iapi_Write_ipcv2( channelDescriptor * cd_p, void * data_control_struct_ipcv2) +{ + + channelControlBlock * ccb_p; + +/* The Parameters passed are considered to be validated by the upper layers*/ + + bufferDescriptor_ipcv1_v2 *bd_ipcv2_p; + dataNodeDescriptor *dnd_p = (dataNodeDescriptor*)data_control_struct_ipcv2; + ccb_p = cd_p->ccb_ptr; + iapi_errno = IAPI_ERR_NO_ERROR; + + if(ccb_p->baseBDptr == NULL) +{ + iapi_errno = IAPI_ERR_BD_UNINITIALIZED; + return -(IAPI_ERR_BD_UNINITIALIZED); +} + + + ccb_p->currentBDptr = ccb_p->baseBDptr; + + bd_ipcv2_p = (bufferDescriptor_ipcv1_v2*)iapi_Phys2Virt(ccb_p->currentBDptr); + /* Copy the data Node descriptor information to new BDs */ + while(1) + { + bd_ipcv2_p->bufferAddr = dnd_p->bufferAddr; + bd_ipcv2_p->mode.count = dnd_p->mode.count; + +#ifdef MCU + bd_ipcv2_p->mode.endianness = 1; +#endif +#ifdef DSP + bd_ipcv2_p->mode.endianness = 0; +#endif + + bd_ipcv2_p->mode.status = dnd_2_bd_status[dnd_p->mode.status & GET_LED_MASK]; + + if((dnd_p->mode.status & DND_END_OF_XFER) != 0) + { + /* Break the loop at End of Transfer */ + break; + } + bd_ipcv2_p++; + dnd_p++; + + } + + /* + * Starting of the channel + */ + iapi_lowStartChannel(cd_p->channelNumber); + ccb_p->status.execute = TRUE; + + return IAPI_SUCCESS; + +} + +/* ***************************************************************************/ +/** Call back ISR for the IPCv2 Receive. + * + * Algorithm:\n + * - This would copy back the informationfrom IPCv1 BD to IPCv2 BD on + * the receiving processor + * + * @return + * - void + */ + +void iapi_read_ipcv2_callback(struct iapi_channelDescriptor* cd_p, void* data) +{ + dataNodeDescriptor *dnd_p = dnd_read_control_struct[cd_p->channelNumber];//cd_p->ccb_ptr->channelDNDBuffer; + bufferDescriptor_ipcv1_v2 *bd_ipcv2_p = (bufferDescriptor_ipcv1_v2*)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + int index = MAX_BD_NUM - 1; + + + do + { + dnd_p->mode.status = 0; + dnd_p->mode.count = bd_ipcv2_p->mode.count; + + dnd_p->mode.status |= bd_ipcv2_p->mode.status & BD_DONE ? 0x00 : DND_DONE ; + dnd_p->mode.status |= bd_ipcv2_p->mode.status & BD_IPCV2_END_OF_FRAME ? DND_END_OF_FRAME : 0x00; + dnd_p->mode.status |= bd_ipcv2_p->mode.status & BD_LAST ? DND_END_OF_XFER : 0x00; + cd_p->ccb_ptr->currentBDptr = (bufferDescriptor*)iapi_Virt2Phys(bd_ipcv2_p); + + if((bd_ipcv2_p->mode.status & BD_LAST) != 0 || + (bd_ipcv2_p->mode.status & BD_CONT) == 0 + ) + break; + dnd_p++; + bd_ipcv2_p++; + + }while(index--); + + /*Call back the Original ISR */ + cd_p->callbackISR_ptr(cd_p, data); +} + +/* ***************************************************************************/ +/**Terminates a channel. + * + * Algorithm:\n + * - Check input parameters ans data structures + * - Check that all buffes have been processed (test all 'D' bits) + * - Stop the channel execution + * - Free alocated memory structures + * - Re-instantiate default interrupt handling + * + * @param *cd_p chanenl descriptor for the channel to close + * + * @return + * - IAPI_SUCCESS : OK + * - -iapi_errno : close failed + */ +int +iapi_Close (channelDescriptor * cd_p) +{ + int index = 0; + int result = IAPI_SUCCESS; + unsigned char chNum; + bufferDescriptor * bd_p; + channelControlBlock * ccb_p; + + /* + * 1. Check input parameters ans data structures + */ + if (cd_p != NULL){ + if (cd_p->ccb_ptr != NULL) { + chNum = cd_p->channelNumber; + ccb_p = cd_p->ccb_ptr; + } else { + result = IAPI_ERR_NO_CCB_DEFINED | IAPI_ERR_CH_AVAILABLE; + iapi_errno = result; + return -result; + } + } else { + result = IAPI_ERR_CD_UNINITIALIZED | IAPI_ERR_CH_AVAILABLE; + iapi_errno = result; + return -result; + } + /* Try to aquire channel*/ + if(iapi_GetChannel(chNum) != 0) + { + result = IAPI_ERR_CH_IN_USE | chNum; + iapi_errno = result; + return -result; + } + + /* + * 2. Check that all buffes have been processed (test all 'D' bits), + * only if the forceClose bit in channel descriptor is set to FALSE + */ + bd_p = (bufferDescriptor *)iapi_Phys2Virt(ccb_p->baseBDptr); + if (bd_p == NULL){ + result = IAPI_ERR_BD_UNINITIALIZED | IAPI_ERR_CH_AVAILABLE | chNum; + iapi_errno = result; + return -result; + } + if(cd_p->forceClose == FALSE) + { + for (index=cd_p->bufferDescNumber ; index>0 ; index--){ + if (bd_p->mode.status & BD_DONE){ + result = IAPI_ERR_CLOSE | IAPI_ERR_CH_AVAILABLE | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + bd_p++; + } + } + /*if the closing is forced,mark channel unused,set BD ownership to processor*/ + else + { + ccb_p->status.execute = FALSE; + for (index=cd_p->bufferDescNumber ; index>0 ; index--) + { + bd_p->mode.status &= ~BD_DONE; + bd_p++; + } + } + + /* + * 3. Stop the channel execution + */ + iapi_lowStopChannel(chNum); + + /* + * 4. Free alocated memory structures + */ + if (cd_p->trust == FALSE ){ + bd_p = (bufferDescriptor *)iapi_Phys2Virt(ccb_p->baseBDptr); + for (index=cd_p->bufferDescNumber ; index>0 ; index--){ + FREE (iapi_Phys2Virt(bd_p->bufferAddr)); + bd_p++; + } + } + + /* + * 5. Re-instantiate default interrupt handling + */ + iapi_DetachCallbackISR (cd_p); + FREE ((bufferDescriptor *)iapi_Phys2Virt(ccb_p->baseBDptr)); + FREE (cd_p); + ccb_p->baseBDptr = NULL; + ccb_p->currentBDptr = NULL; + ccb_p->channelDescriptor = NULL; + ccb_p->status.openedInit = FALSE; + + iapi_ReleaseChannel(chNum); + + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/**The request argument selects the control function to be performed. + * + * Algorithm:\n + * + * - Check data structures are properly initialized: + * - Channel descriptor validity + * - Channel control block validity + * - The ctlRequest parameter contains in the lower 16 bits the control code of + * the change to be performed, and in the upper 16 bits, the BD to be + * modified if the change affects a BD od the channel. + * - Selection of the parameter to change and appropriate sanity checks: + * - Channel Descriptor: changes the pointer to the channel descriptor + * structure, the pointer to the new channel descriptor is given in the third + * argument call + * - Buffer Descriptor Number: changes the number of buffer descriptor for the + * channel + * - Buffer size: changes the size of the data buffers pointed to by the + * buffer descriptor; note that all buffer descriptors are assumed to have the + * same size for a given buffer descripotr chain + * - Blocking policy: changes the blocking policy for the read and write calls + * - Ownership: changes direction: turnaround + * - Synchronization method: changes the callback type, default or user. The* + * callback function table is set accordingly + * - Trust property: trust can only be changed through ChangeChannelDesc first + * request, this guarantees the close/open sequence for the channel + * - Callback Interrupt service routine pointer: changes the callback function + * pointer, when this method is used, to replace it with a new one + * - Channel control block pointer: not available + * - Priority: changes the channel priority directly in SDMA register + * - Watermark level: changes the value of the peripheral watermark level that + * passed to the script. The new value is passed in the third parameter call. + * - Wrap bit: changes to set to 1 the Wrap bit of the last buffer descriptor + * + * @param *cd_p channel descriptor for the channel to modify + * @param ctlRequest request control code and, if tha case, number of BD to be + * changed + * @param param parameter for the modification + * + * @return + * - IAPI_SUCCESS : OK + * - -iapi_errno : operation failed + */ +int +iapi_IoCtl (channelDescriptor * cd_p, unsigned long ctlRequest, + unsigned long param) +{ + int retvalue; + int result = IAPI_SUCCESS; + unsigned char chNum; + unsigned long clean_ctlRequest; /* lower 16 bits of the ctlRequest*/ + unsigned long bd_num; /* upper 16 bits of the ctlRequest*/ + + /* + * 1. Check data structures are properly initialized + */ + /* Channel descriptor validity */ + if (cd_p == NULL){ + result = IAPI_ERR_CD_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* Channel control block validity */ + if (cd_p->ccb_ptr == NULL){ + result = IAPI_ERR_CCB_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* Control block & Descriptor associated with the channel being worked on */ + chNum = cd_p->channelNumber; + + /* Remove, if exists, BD number specified in upper bits of ctlRequest*/ + clean_ctlRequest = ctlRequest & (~BD_NUM_MASK); + + /* Extract, if exists, BD number specified in upper bits of ctlRequest*/ + bd_num = (ctlRequest & BD_NUM_MASK) >> BD_NUM_OFFSET; + + /* Check that the bd_num is valid*/ + if(bd_num > cd_p->bufferDescNumber) + { + result = IAPI_ERR_INVALID_PARAMETER | chNum; + iapi_errno = result; + return -result; + } + + /*All checks OK, try to aquire channel*/ + if(iapi_GetChannel(chNum) != 0) + { + result = IAPI_ERR_CH_IN_USE | chNum; + iapi_errno = result; + return -result; + } + + /* + * 2. Selection of the parameter to change and appropriate sanity checks + */ + switch (clean_ctlRequest){ + + /* + * Channel Descriptor + * --- Changes the pointer to the channel descriptor structure: the pointer + * to the new channel descriptor is given in the third argument call. + */ + case IAPI_CHANGE_CHANDESC: + if ((void *) param == NULL) { + result = IAPI_ERR_INVALID_PARAMETER; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } else { + channelDescriptor * chParam = (channelDescriptor *)param; + if (chParam->channelNumber != chNum){ + /* Release ch so it can be aquired by the Close fn*/ + iapi_ReleaseChannel(chNum); + result = iapi_Close(cd_p); + if (result == IAPI_SUCCESS){ + FREE((void*)cd_p); + iapi_AllocChannelDesc (&cd_p, chParam->channelNumber); + iapi_memcpy((void*)cd_p, (void*)chParam, sizeof (channelDescriptor)); + /* Channel is released allready, so Open can get the channel*/ + result = iapi_Open(cd_p, chParam->channelNumber); + if(result != IAPI_SUCCESS) + { + return result; /* error code already set in iapi_Open*/ + } + } else { + return result; /* error code already set in iapi_Close*/ + } + } else { + result = IAPI_ERR_CD_CHANGE | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_ReleaseChannel(chNum); + iapi_errno = result; + return -result; + } + return IAPI_SUCCESS; + } + + /* + * Buffer Descriptor Number + * --- Changes the number of buffer descriptor for the channel. + */ + case IAPI_CHANGE_BDNUM: + result = iapi_ChangeChannelDesc(cd_p, IAPI_BUFFERDESCNUMBER, param); + iapi_ReleaseChannel(chNum); + return result; + + /* + * Buffer size + * --- Changes the size of the data buffers pointed to by the buffer + * descriptor; note that all buffer descriptors are assumed to have the + * same size for a given buffer descripotr chain. + */ + case IAPI_CHANGE_BUFFSIZE: + result = iapi_ChangeChannelDesc(cd_p, IAPI_BUFFERSIZE, param); + iapi_ReleaseChannel(chNum); + return result; + + /* + * Blocking policy + * --- Changes the blocking policy for the read and write calls. + */ + case IAPI_CHANGE_CHANBLOCK: + result = iapi_ChangeChannelDesc(cd_p, IAPI_BLOCKING, param); + iapi_ReleaseChannel(chNum); + return result; + + /* + * Ownership + * --- Changes direction: turnaround + */ + case IAPI_CHANGE_OWNERSHIP: + result = iapi_ChangeChannelDesc(cd_p, IAPI_OWNERSHIP, param); + iapi_ReleaseChannel(chNum); + return result; + + /* + * Synchronization method + * --- Changes the callback type, default or user. The callback function + * table is set accordingly. + */ + case IAPI_CHANGE_SYNCH: + result = iapi_ChangeChannelDesc(cd_p, IAPI_CALLBACKSYNCH, param); + iapi_ReleaseChannel(chNum); + return result; + + /* + * Trust property + * --- trust can only be changed through ChangeChannelDesc first request, + * this guarantees the close/open sequence for the channel. + */ + case IAPI_CHANGE_TRUST: + result = iapi_ChangeChannelDesc(cd_p, IAPI_TRUST, param); + iapi_ReleaseChannel(chNum); + return result; + + /* + * Callback Interrupt service routine pointer + * --- Cahnges the callback function pointer, when this method is used, to + * replace it with a new one. + */ + case IAPI_CHANGE_CALLBACKFUNC: + result = iapi_ChangeChannelDesc(cd_p, IAPI_CALLBACKISR_PTR, param); + iapi_ReleaseChannel(chNum); + return result; + + /* + * Channel control block pointer + * --- NA + */ + case IAPI_CHANGE_CHANCCB: + result = iapi_ChangeChannelDesc(cd_p, IAPI_CCB_PTR, param); + iapi_ReleaseChannel(chNum); + return result; + +#ifdef MCU + /* + * Priority + * --- Changes the channel priority directly in SDMA register + */ + case IAPI_CHANGE_PRIORITY: + { + volatile unsigned long * ChannelPriorities = &SDMA_CHNPRI_0; + if(param < MAX_CH_PRIORITY) + { + ChannelPriorities[ cd_p->channelNumber ] = param; + } + else + { + iapi_ReleaseChannel(chNum); + return IAPI_FAILURE; + } + } + break; +#endif /* MCU */ + + /* + * Wrap + * --- Set to 1 the wrap bit of the last buffer descriptor of the array. + * it provides the possibility to have a circular buffer structure. + */ + case IAPI_CHANGE_BDWRAP: + { + result = iapi_ChangeChannelDesc(cd_p,IAPI_BDWRAP , param); + iapi_ReleaseChannel(chNum); + return result; + } + + /* + * Watermark + * --- Changes the value of the peripheral watermark level that triggers + * a DMA request. It impacts context of the channel, therefore channel 0 + * must be started to update the context with this new value. + */ + case IAPI_CHANGE_WATERMARK: + { + result = iapi_ChangeChannelDesc(cd_p,IAPI_WML , param); + iapi_ReleaseChannel(chNum); + return result; + } + /* + * INTR + * --- Set the INTR bit on specified BD or on all BD's if SET_BIT_ALL + * is passed as parameter. + */ + case IAPI_CHANGE_SET_BDINTR: + { + bufferDescriptor * bde_p; + int j = 0; + + retvalue = IAPI_SUCCESS; + if(param == SET_BIT_ALL) + { + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for(j = 0; j < cd_p->bufferDescNumber; j++) + { + bde_p->mode.status |= BD_INTR; + bde_p++; + } + } + else if(param < cd_p->bufferDescNumber) + { + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr) + + param; + bde_p->mode.status |= BD_INTR; + } + else + { + retvalue = IAPI_FAILURE; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * INTR + * --- Unset the INTR bit on specified BD or on all BD's if SET_BIT_ALL + * is passed as parameter. + */ + case IAPI_CHANGE_UNSET_BDINTR: + { + bufferDescriptor * bde_p; + + int j = 0; + + retvalue = IAPI_SUCCESS; + if(param == SET_BIT_ALL) + { + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for(j = 0; j < cd_p->bufferDescNumber; j++) + { + bde_p->mode.status &= ~BD_INTR; + bde_p++; + } + } + else if(param < cd_p->bufferDescNumber) + { + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr) + + param; + bde_p->mode.status &= ~BD_INTR; + } + else + { + retvalue = IAPI_FAILURE; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } +/* + * EventMask1 + * --- Changes the value of the eventMask1 + */ + case IAPI_CHANGE_EVTMASK1: + { + cd_p->eventMask1 = param; + } + break; + /* + * EventMask2 + * --- Changes the value of the eventMask2 + */ + case IAPI_CHANGE_EVTMASK2: + { + cd_p->eventMask2 = param; + } + break; + /* + * Peripheral Address + * --- Changes the value of the peripheralAddr + */ + case IAPI_CHANGE_PERIPHADDR: + { + cd_p->peripheralAddr = param; + } + break; + /* + * Cont + * --- Set the CONT bit on specified BD on all BD's if SET_BIT_ALL + * is passed as parameter. + */ + case IAPI_CHANGE_SET_BDCONT: + { + bufferDescriptor * bde_p; + int j = 0; + + retvalue = IAPI_SUCCESS; + if(param == SET_BIT_ALL) + { + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for(j = 0; j < cd_p->bufferDescNumber; j++) + { + bde_p->mode.status |= BD_CONT; + bde_p++; + } + } + else if(param < cd_p->bufferDescNumber) + { + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr) + + param; + bde_p->mode.status |= BD_CONT; + } + else + { + retvalue = IAPI_FAILURE; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * Cont + * --- Unset the CONT bit on specified BD or on all BD's if SET_BIT_ALL + * is passed as parameter. + */ + case IAPI_CHANGE_UNSET_BDCONT: + { + bufferDescriptor * bde_p; + + int j = 0; + + retvalue = IAPI_SUCCESS; + if(param == SET_BIT_ALL) + { + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for(j = 0; j < cd_p->bufferDescNumber; j++) + { + bde_p->mode.status &= ~BD_CONT; + bde_p++; + } + } + else if(param < cd_p->bufferDescNumber) + { + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr) + + param; + bde_p->mode.status &= ~BD_CONT; + } + else + { + retvalue = IAPI_FAILURE; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } + + /* + * EXTD + * --- Set the EXTD bit on specified BD or on all BD's if SET_BIT_ALL + * is passed as parameter. + */ + case IAPI_CHANGE_SET_BDEXTD: + { + bufferDescriptor * bde_p; + int j = 0; + + retvalue = IAPI_SUCCESS; + if(param == SET_BIT_ALL) + { + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for(j = 0; j < cd_p->bufferDescNumber; j++) + { + bde_p->mode.status |= BD_EXTD; + bde_p++; + } + } + else if(param < cd_p->bufferDescNumber) + { + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr) + + param; + bde_p->mode.status |= BD_EXTD; + } + else + { + retvalue = IAPI_FAILURE; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * EXTD + * --- Unset the EXTD bit on specified BD or on all BD's if SET_BIT_ALL + * is passed as parameter. + */ + case IAPI_CHANGE_UNSET_BDEXTD: + { + bufferDescriptor * bde_p; + + int j = 0; + + retvalue = IAPI_SUCCESS; + if(param == SET_BIT_ALL) + { + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for(j = 0; j < cd_p->bufferDescNumber; j++) + { + bde_p->mode.status &= ~BD_EXTD; + bde_p++; + } + } + else if(param < cd_p->bufferDescNumber) + { + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr) + + param; + bde_p->mode.status &= ~BD_EXTD; + } + else + { + retvalue = IAPI_FAILURE; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } + + /* + * TRANSFER SIZE to be used for this channel + * --- Set the transfer size used indicator and code for transfer size in + * the CD + */ +case IAPI_CHANGE_SET_TRANSFER_CD: + { + bufferDescriptor * bde_p; + int j = 0; + retvalue = IAPI_SUCCESS; + if((param == TRANSFER_8BIT) || (param == TRANSFER_16BIT) || + (param == TRANSFER_24BIT) || (param == TRANSFER_32BIT)) + { + cd_p->useDataSize = TRUE; + cd_p->dataSize = param; + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for(j = 0; j < cd_p->bufferDescNumber; j++) + { + bde_p->mode.command = param; + bde_p++; + } + } + else + { + retvalue = IAPI_FAILURE; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } + + + /* + * USER_ARG + * --- Set the user selectable pointer to be received by the callback + * function, if IRQ synch is used + */ + case IAPI_CHANGE_USER_ARG: + { + userArgTable[cd_p->channelNumber]= (void*)param; + iapi_ReleaseChannel(chNum); + return IAPI_SUCCESS; + } + /* + * FORCE_CLOSE + * --- Set the forceClose bit in channelDescriptor to value passed in param. + * If this bit is TRUE, the channel in closed even if some BD are still + * owned by the SDMA. + */ + case IAPI_CHANGE_FORCE_CLOSE: + { + retvalue = IAPI_SUCCESS; + if((param == TRUE) || (param == FALSE)) + { + cd_p->forceClose = param; + } + else + { + iapi_errno = IAPI_ERR_INVALID_PARAMETER | cd_p->channelNumber; + retvalue = -iapi_errno; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * TRANSFER type + * --- Set the last 2 bits in the command field of the BD to specify the + * transfer type 8, 16, 24, or 32 bits on all BD's, allready set in the CD + */ + case IAPI_CHANGE_SET_TRANSFER: + { + bufferDescriptor * bde_p; + int j = 0; + + retvalue = IAPI_SUCCESS; + if((param == TRANSFER_8BIT)||(param == TRANSFER_16BIT)|| + (param == TRANSFER_24BIT)||(param == TRANSFER_32BIT)) + { + bde_p = cd_p->ccb_ptr->baseBDptr; + for(j = 0; j < cd_p->bufferDescNumber; j++) + { + bde_p->mode.command = param; + bde_p++; + } + } + else + { + retvalue = IAPI_FAILURE; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * BUFFER address + * --- Change buffer address in BD specified in the upper 16 bits of the + * ctlRequest. + */ + case IAPI_CHANGE_SET_BUFFERADDR: + { + bufferDescriptor * bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change*/ + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + bde_p+= bd_num; + + /* DO NOT translate address to physical */ + bde_p->bufferAddr = (void*)param; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * BUFFER address + * --- Get the buffer address from the BD specified in the upper 16 bits of the + * ctlRequest. + */ + case IAPI_CHANGE_GET_BUFFERADDR: + { + bufferDescriptor * bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change*/ + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + bde_p+= bd_num; + /* Translate to virtual*/ + *((unsigned long*)param) = (unsigned long)bde_p->bufferAddr; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * EXTENDED BUFFER address + * --- Change extended buffer address in BD specified in the upper 16 bits + * of the ctlRequest. + */ + case IAPI_CHANGE_SET_EXTDBUFFERADDR: + { + bufferDescriptor * bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change*/ + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + bde_p+= bd_num; + + /* DO NOT translate address to physical. The user might want something else + *here + */ + bde_p->extBufferAddr = (void*)param; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * EXTENDED BUFFER address + * --- Get extended buffer address from the BD specified in the upper 16 bits + * of the ctlRequest. + */ + case IAPI_CHANGE_GET_EXTDBUFFERADDR: + { + bufferDescriptor * bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change*/ + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + bde_p+= bd_num; + + /* DO NOT translate address to vitual - user knows what is here. + */ + *((unsigned long*)param) = (unsigned long)bde_p->extBufferAddr; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * COMMAND field + * --- Change command field in BD specified in the upper 16 bits of the + * ctlRequest. + */ + case IAPI_CHANGE_SET_COMMAND: + { + bufferDescriptor * bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change*/ + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + bde_p+= bd_num; + /* Update command field*/ + bde_p->mode.command = param; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * COMMAND field + * --- Get the command field from the BD specified in the upper 16 bits + * of the ctlRequest. + */ + case IAPI_CHANGE_GET_COMMAND: + { + bufferDescriptor * bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change*/ + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + bde_p+= bd_num; + /* Get the command field*/ + *((unsigned long*)param) = bde_p->mode.command; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * COUNT field + * --- Change count field in BD specified in the upper 16 bits of the + * ctlRequest. + */ + case IAPI_CHANGE_SET_COUNT: + { + bufferDescriptor * bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change*/ + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + bde_p+= bd_num; + /* Update count field*/ + bde_p->mode.count = param; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * COUNT field + * --- Get the count field of the BD specified in the upper 16 bits of the + * ctlRequest. + */ + case IAPI_CHANGE_GET_COUNT: + { + bufferDescriptor * bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change*/ + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + bde_p+= bd_num; + /* Update count field*/ + *((unsigned long*)param) = bde_p->mode.count; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * STATUS field + * --- Change status field in BD specified in the upper 16 bits of the + * ctlRequest. + */ + case IAPI_CHANGE_SET_STATUS: + { + bufferDescriptor * bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change*/ + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + bde_p+= bd_num; + /* Update status field*/ + bde_p->mode.status = param; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * STATUS field + * --- Get the status field of the BD specified in the upper 16 bits + * of the ctlRequest. + */ + case IAPI_CHANGE_GET_STATUS: + { + bufferDescriptor * bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change*/ + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + bde_p+= bd_num; + /* Update status field*/ + *((unsigned long*)param) = bde_p->mode.status; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + +#ifdef MCU + /* + * Endianness + * --- Set the ENDIANNESS indicator in the command filed of the specified BD + * or on all BD's if SET_BIT_ALL is passed as parameter. + */ + case IAPI_CHANGE_SET_ENDIANNESS: + { + bufferDescriptor * bde_p; + int j = 0; + + retvalue = IAPI_SUCCESS; + if(param == SET_BIT_ALL) + { + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for(j = 0; j < cd_p->bufferDescNumber; j++) + { + bde_p->mode.command = CHANGE_ENDIANNESS; + bde_p++; + } + } + else if(param < cd_p->bufferDescNumber) + { + bde_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr) + + param; + bde_p->mode.command = CHANGE_ENDIANNESS; + } + else + { + retvalue = IAPI_FAILURE; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } +#endif + +#ifdef SDMA_SKYE +#ifdef MCU + + /* + * SDMA State + * --- Enter the SDMA into LOCK Mode. No RAM updation allowed except same Context + * update with same PC Value. + */ + case IAPI_ENTER_LOCK_MODE: + { + if(param == RESET_CLEAR_LOCK) + { + SDMA_SDMA_LOCK = (1 << RESET_CLR_BIT_OFFSET); + SDMA_SDMA_LOCK = (1 << LOCK_BIT_OFFSET); + iapi_SdmaState = LOCK; + } + else if(param == RESET_NOCLEAR_LOCK) + { + SDMA_SDMA_LOCK = (1 << LOCK_BIT_OFFSET); + iapi_SdmaState = LOCK; + } + + } + break; + +#endif +#endif + default: + retvalue = IAPI_ERR_CD_CHANGE_UNKNOWN | IAPI_ERR_CH_AVAILABLE | chNum; + iapi_errno = retvalue; + iapi_ReleaseChannel(chNum); + return -retvalue; + } + + + iapi_ReleaseChannel(chNum); + return IAPI_SUCCESS; +} +/* ***************************************************************************/ +/**Initialization of the SDMA - opening of channel 0, download RAM image. + * + * Algorithm:\n + * - open channel 0 + * - if ram_image pointer passed is not NULL, download RAM image to SDMA + * + * @param + * - cd_p channel descriptor pointer for channel 0 + * - ram_image pointer to RAM image to download, or NULL if this operation + * is not required + * - code_size size of the RAM image, in bytes + * - start_addr start address for the RAM image + * + * @return + * - IAPI_SUCCESS if all operations were successful + * - negated I.API error code if any operation failed + */ +#ifdef MCU +int +iapi_Init(channelDescriptor * cd_p, configs_data * config_p, unsigned short* ram_image, + unsigned short code_size, unsigned long start_addr) +{ +#endif +#ifdef DSP +int +iapi_Init(channelDescriptor * cd_p) +{ +#endif + +int retvalue = IAPI_SUCCESS; /* Variable to store the results from I.API calls */ + + /* Check initialization not allredy done*/ + if(iapi_CCBHead != NULL) + { + retvalue = IAPI_ERR_NOT_ALLOWED; + iapi_errno = retvalue; + return -retvalue; + } + /* Be sure SDMA has not started yet */ +#ifdef MCU + SDMA_H_C0PTR = 0x0; +#endif +#ifdef DSP + SDMA_D_C0PTR = 0x0; +#endif + + /*Try to open channel 0*/ + retvalue = iapi_Open(cd_p, 0); + if(retvalue != IAPI_SUCCESS) + { + return retvalue; + } + +#ifdef MCU + /* Set Command Channel (Channel Zero) */ + SDMA_CHN0ADDR = 0x4050; + + /* Set bits of CONFIG register but with static context switching */ + SDMA_H_CONFIG = (config_p->dspdma << 12) | (config_p->rtdobs << 11) | + (config_p->acr << 4) | (0); + + /* Send the address for the host channel table to the SDMA*/ + SDMA_H_C0PTR = (unsigned long)iapi_Virt2Phys(iapi_CCBHead); + /* If required, download the RAM image for SDMA*/ + if(ram_image != NULL) + { + retvalue = iapi_SetScript(cd_p, (void*)ram_image, code_size, + start_addr); + } + + /* Set bits of CONFIG register with given context switching mode */ + SDMA_H_CONFIG = (config_p->dspdma << 12) | (config_p->rtdobs << 11) | + (config_p->acr << 4) | (config_p->csm); + +#endif +#ifdef DSP + /* Send the address for the host channel table to the SDMA*/ + SDMA_D_C0PTR = (unsigned long)iapi_Virt2Phys(iapi_CCBHead); +#endif + +#ifdef SDMA_SKYE + iapi_SdmaState = OPEN; +#endif + + return retvalue; +} + + +/* ***************************************************************************/ +/**High layer interface for starting a channel + * + * Algorithm:\n + * - call low layer function for starting a channel + * + * @return + * - IAPI_SUCCESS + */ +int +iapi_StartChannel(unsigned char channel) +{ + iapi_lowStartChannel(channel); + return IAPI_SUCCESS; +} +/* ***************************************************************************/ +/**High layer interface for stopping a channel + * + * Algorithm:\n + * - call low layer function for stopping a channel + * + * @return + * - IAPI_SUCCESS + */ +int +iapi_StopChannel(unsigned char channel) +{ + iapi_lowStopChannel(channel); + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/**High layer interface for synchronising a channel + * + * Algorithm:\n + * - call low layer function for stopping a channel + * + * @return + * - IAPI_SUCCESS + */ +int iapi_SynchChannel(unsigned char channel) +{ + iapi_lowSynchChannel(channel); + return IAPI_SUCCESS; +} + +#ifdef MCU +/* ***************************************************************************/ +/**High layer interface for getting program memory data from SDMA + * + * Algorithm:\n + * - call coresponding low layer function + * + * @return + * - IAPI_SUCCESS + */ +int +iapi_GetScript(channelDescriptor * cd_p, void * buf, unsigned short size, + unsigned long address) +{ + iapi_lowGetScript(cd_p, buf, size, address); + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/**High layer interface for getting data memory from SDMA + * + * Algorithm:\n + * - call coresponding low layer function + * + * @return + * - IAPI_SUCCESS + */ +int +iapi_GetContext(channelDescriptor * cd_p, void * buf, + unsigned char channel) +{ + iapi_lowGetContext(cd_p, buf, channel); + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/**High layer interface for set program memory data to SDMA - e.g. scripts + * + * Algorithm:\n + * - call coresponding low layer function + * + * @return + * - IAPI_SUCCESS + */ +int +iapi_SetScript(channelDescriptor * cd_p, void * buf, unsigned short nbyte, + unsigned long destAddr) +{ + iapi_lowSetScript(cd_p, buf, nbyte, destAddr); + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/**High layer interface for set data memory to SDMA - e.g. contexts. + * + * Algorithm:\n + * - call coresponding low layer function + * + * @return + * - IAPI_SUCCESS + */ +int +iapi_SetContext(channelDescriptor * cd_p, void * buf, + unsigned char channel) +{ + iapi_lowSetContext(cd_p, buf, channel); + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/**High layer interface used to associate specified channel with a script. + * + * Algorithm:\n + * - call coresponding low layer function + * + * @return + * - IAPI_SUCCESS + */ +int +iapi_AssignScript(channelDescriptor * cd_p, script_data * data_p) +{ + /* VERIFY THAT THE CHANNEL IT IS OPENED !!!!*/ + return iapi_lowAssignScript(cd_p, data_p); +} + +/* ***************************************************************************/ +/**High layer interface used to associate specified channel with a script. + * + * Algorithm:\n + * - call coresponding low layer function + * + * @return + * - IAPI_SUCCESS + */ +int +iapi_SetChannelEventMapping(unsigned char event, unsigned long channel_map) +{ + return iapi_lowSetChannelEventMapping(event, channel_map); +} +#endif + + + +#ifdef DSP +#define SDMA_DI SDMA_D_INTR +void IRQ_Handler(); +#pragma interrupt IRQ_Handler +#endif + +#ifdef MCU +#define SDMA_DI SDMA_H_INTR +#endif + +#ifndef IRQ_KEYWORD +#define IRQ_KEYWORD +#endif /* IRQ_KEYWORD */ + +/* ***************************************************************************/ +/** + *@brief Find the first set bit in data parameter. + * + * Find the first set bit in unsigned integer parameter data. Data is scanned + * from MSB to LSB, searching for the set bit. The value returned is the + * offset from the most significant bit of data. If bit 31 is set, the value + * returned is zero. If no bits are set, a value of 32 is returned. This is compliant + * with the MCore FF1 instruction. + * + * + * + * @param + * - data: variable to check + * + * @return + * - the offset of the most significant bit set from the MSB + */ +unsigned int +quartz_FF1( unsigned int data ) +{ + register unsigned int result = 0; + while ( (result <= 31 ) && !( data & 0x80000000U) ) + { + data <<= 1U; + result++; + } + + return result; +} + +IRQ_KEYWORD +void +IRQ_Handler(void) +{ + unsigned int intrReg;/* interrupt register mask for clearing the interrupt bit */ + unsigned char chNum; /* SDMA channel number generating the a IRQ*/ + + /* Disable interrupts */ + iapi_DisableInterrupts(); + /* + * Clear interrupt in SDMA DI register => ACK to the SDMA the IT request. + * Get each interrupt number, clear them one after the other. + */ + + if(SDMA_DI != 0) + { + chNum = (unsigned char)(CH_NUM - 1 - quartz_FF1(SDMA_DI)); + intrReg = (unsigned int)(1 << chNum); + } + else + { + chNum = 32; + intrReg = 0; + } + + while (intrReg != 0) + { + SDMA_DI &= intrReg; + iapi_SDMAIntr |= intrReg; + iapi_WakeUp(chNum); + if (callbackIsrTable[chNum] != NULL) + { + /* release channel before callback, so IoCtl's are available*/ + iapi_ReleaseChannel(chNum); + callbackIsrTable[chNum](iapi_CCBHead[chNum].channelDescriptor, + userArgTable[chNum]); + } + + chNum = (unsigned char)(CH_NUM - 1 - quartz_FF1(SDMA_DI)); + intrReg = (unsigned int)(1 << chNum); + } + + /* Enable interrupts */ + iapi_EnableInterrupts(); + +} + +/* ***************************************************************************/ +/** + *@brief Perform a memory copy operation, in the memory of the same processor + * + * Size bytes are copied from the src address to dest address. It is used + * the channel pointed by cd_p, which must be configured prior to this call: + * opened, associated with the script to perform the operation - DSP_2_DSP, + * or MCU_2_MCU - and have the synchronization option set. + * + * + * + * @param + * - cd_p: channel configured to perform DSP_2_DSP or MCU_2_MCU transfers + * - dest: destination memory address + * - src : source memory address + * - size: number of bytes to copy from src to dest + * + * @return + * - the offset of the most significant bit set from the MSB + */ + +int iapi_MemCopy(channelDescriptor * cd_p, void* dest, void* src, unsigned long size) +{ + int result = IAPI_SUCCESS; + bufferDescriptor * bd_p; + + /* Channel descriptor validity */ + if (cd_p == NULL) + { + result = IAPI_ERR_CD_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* Check and set correct parameter */ + if(cd_p->trust != TRUE) + { + result = iapi_ChangeChannelDesc(cd_p, IAPI_TRUST, TRUE); + } + + if(cd_p->bufferDescNumber != 1) + { + result = iapi_ChangeChannelDesc(cd_p, IAPI_BUFFERDESCNUMBER, 1); + if(result != IAPI_SUCCESS) + { + return result; + } + } + + if(cd_p->bufferSize != size) + { + result = iapi_ChangeChannelDesc(cd_p, IAPI_BUFFERSIZE, size); + if(result != IAPI_SUCCESS) + { + return result; + } + } + /* Set addresses*/ + bd_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + bd_p->bufferAddr = iapi_Virt2Phys(src); + bd_p->extBufferAddr = iapi_Virt2Phys(dest); + + /* Set mode*/ + bd_p->mode.count = size; + bd_p->mode.command = 0x00; + bd_p->mode.status = BD_INTR|BD_EXTD|BD_DONE|BD_WRAP; + + /*Decide if we sleep or not*/ + if(cd_p->callbackSynch == DEFAULT_POLL) + { + iapi_StartChannel(cd_p->channelNumber); + /* Call synchronization routine*/ + iapi_SynchChannel(cd_p->channelNumber); + } + else + { + /* Just start the channel*/ + iapi_StartChannel(cd_p->channelNumber); + } + + return result; +} + +/* ***************************************************************************/ +/**Return the channel number from the channel descriptor + * + * @param cd_p pointer to channel descriptor to obtain the channel number + * + * @return + * - the channel number + * + */ +int iapi_GetChannelNumber(channelDescriptor * cd_p) +{ + return cd_p->channelNumber; +} + +/* ***************************************************************************/ +/**Return the error bit from the current BD of the channel + * + * + * @param cd_p pointer to channel descriptor + * + * @return + * - 0 if no error detected + * - BD_RROR | DATA_ERROR if error detected + * + */ +unsigned long iapi_GetError(channelDescriptor * cd_p) +{ + return ((cd_p->ccb_ptr->currentBDptr->mode.status & BD_RROR) | + (*(unsigned long*)&cd_p->ccb_ptr->status & DATA_ERROR)); +} + +/* ***************************************************************************/ +/**Return the count from the current BD of the channel + * + * + * @param cd_p pointer to channel descriptor + * + * @return + * - count field of the current BD for the channel + * + */ +int iapi_GetCount(channelDescriptor * cd_p) +{ + return (int)(cd_p->ccb_ptr->currentBDptr->mode.count); +} + +/* ***************************************************************************/ +/**Return the sum of counts for all the BD's owned by the processor for + * the channel specified by the received parameter. + * + * + * @param cd_p pointer to channel descriptor + * + * @return + * - sum of count fields + * + */ +int iapi_GetCountAll(channelDescriptor * cd_p) +{ + int retval = 0; + int i = 0; + bufferDescriptor* bd_p; + + bd_p = cd_p->ccb_ptr->baseBDptr; + + while((i < cd_p->bufferDescNumber) && ((bd_p->mode.status & BD_DONE) == 0)) + { + retval += bd_p->mode.count; + i++; + bd_p++; + } + return retval; +} diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/src/iapiLow.c linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/src/iapiLow.c --- linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/src/iapiLow.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/src/iapiLow.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,150 @@ +/****************************************************************************** + * + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiLow.c + * + * $Id iapiLow.c $ + * + * Description: + * This library is written in C to guarantee functionality and integrity in + * the usage of SDMA virtual DMA channels. This API (Application Programming + * Interface) allow SDMA channels' access in an OPEN, READ, WRITE, CLOSE + * fashion. + * These are the LOW level functions of the I.API. + * + * + * / + * + * $Log iapiLow.c $ + * + *****************************************************************************/ + +/* **************************************************************************** + * Include File Section + *****************************************************************************/ +#include "epm.h" +#include "iapiLow.h" + +/** + * Function Section + */ + + +/* ***************************************************************************/ +/**Records an ISR callback function pointer into the ISR callback + * function table + * + * @param cd_p channel descriptor to attach callback to + * @param func_p pointer to the callback function to be registered + * + * @return none + */ +void +iapi_AttachCallbackISR (channelDescriptor * cd_p, + void (* func_p)(channelDescriptor * cd_p, void * arg)) + +{ + if (cd_p->callbackSynch == CALLBACK_ISR) { + iapi_DisableInterrupts(); + callbackIsrTable[cd_p->channelNumber] = func_p; + iapi_EnableInterrupts(); + } else if (cd_p->callbackSynch == DEFAULT_POLL) { + callbackIsrTable[cd_p->channelNumber] = NULL; + } else { + iapi_errno = IAPI_ERR_CALLBACKSYNCH_UNKNOWN | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + } +} + + +/* ***************************************************************************/ +/**Detaches (removes) an ISR callback function pointer from the ISR callback + * function table + * + * Algorithm:\n + * - Attach a null function to replace the original one. + * + * @param cd_p channel descriptor to detach callback from + * + * @return none + */ +void +iapi_DetachCallbackISR (channelDescriptor * cd_p) + +{ + iapi_AttachCallbackISR (cd_p, NULL); +} + +/* ***************************************************************************/ +/**Updates an ISR callback function pointer into the ISR callback function + * table + * + * Algorithm:\n + * - Detach the old function pointer (if any) and attach the new one + * + * @param cd_p channel descriptor to attach callback to + * @param func_p pointer to the callback function to be registered + * + * @return none + */ +void +iapi_ChangeCallbackISR (channelDescriptor * cd_p, + void (* func_p)(channelDescriptor * cd_p, void * arg)) +{ + iapi_DetachCallbackISR(cd_p); + iapi_AttachCallbackISR(cd_p, func_p); +} + +/* ***************************************************************************/ +/**Loop while the channel is not done on the SDMA + * + * Algorithm:\n + * - Loop doing nothing but checking the I.API global variable to indicate + * that the channel has been completed (interrupt from SDMA) + * + * Notes:\n + * - The ISR must update the I.API global variable iapi_SDMAIntr. + * + * @param channel channel number to poll on + * + * @return none + */ +void +iapi_lowSynchChannel (unsigned char channel) +{ + while (!((1UL << channel) & iapi_SDMAIntr)) ; + iapi_SDMAIntr &= ~(1UL << channel); +} + +/* ***************************************************************************/ +/**Fill the buffer descriptor with the values given in parameter. + * + * @return none + */ +void +iapi_SetBufferDescriptor( bufferDescriptor * bd_p, unsigned char command, + unsigned char status, unsigned short count, + void * buffAddr, void * extBufferAddr) +{ + bd_p->mode.command = command; + bd_p->mode.status = status; + bd_p->mode.count = count; + if (buffAddr != NULL) { + bd_p->bufferAddr = iapi_Virt2Phys(buffAddr); + } else { + bd_p->bufferAddr = buffAddr; + } + bd_p->extBufferAddr = extBufferAddr; +} + diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/src/iapiLowDsp.c linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/src/iapiLowDsp.c --- linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/src/iapiLowDsp.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/src/iapiLowDsp.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,79 @@ +/****************************************************************************** + * + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiLowDsp.c + * + * $Id iapiLowDsp.c $ + * + * Description: + * This library is written in C to guarantee functionality and integrity in + * the usage of SDMA virtual DMA channels. This API (Application Programming + * Interface) allow SDMA channels' access in an OPEN, READ, WRITE, CLOSE + * fashion. + * These are the LOW level functions of the I.API specific to MCU. + * + * + * + * + * $Log iapiLowDsp.c $ + * + *****************************************************************************/ + +/* **************************************************************************** + * Include File Section + *****************************************************************************/ +#include "epm.h" +#include "iapiLow.h" + +/* **************************************************************************** + * Function Section + *****************************************************************************/ +#ifdef DSP + +/* ***************************************************************************/ +/**Starts the channel (core specific register) + * + * Algorithm:\n + * - Bit numbered "channel" of DspEnStartReg register is set + * + * @param channel channel to start + * + * @return none + */ +void +iapi_lowStartChannel (unsigned char channel) +{ + SDMA_D_START |= (1 << channel); +} + +/* ***************************************************************************/ +/**Stops the channel (core specific register) + * + * Algorithm: + * - Bit numbered "channel" of DspEnStopReg register is cleared + * + * Notes:\n + * - This is a write one to clear register + * + * @param channel channel to stop + * + * @return none + */ +void +iapi_lowStopChannel (unsigned char channel) +{ + SDMA_D_STATSTOP &= (1 << channel); +} + +#endif /* DSP */ diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/src/iapiLowMcu.c linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/src/iapiLowMcu.c --- linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/src/iapiLowMcu.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/src/iapiLowMcu.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,519 @@ +/****************************************************************************** + * + * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiLowMcu.c + * + * $Id iapiLowMcu.c $ + * + * Description: + * This library is written in C to guarantee functionality and integrity in + * the usage of SDMA virtual DMA channels. This API (Application Programming + * Interface) allow SDMA channels' access in an OPEN, READ, WRITE, CLOSE + * fashion. + * These are the LOW level functions of the I.API specific to MCU. + * + * + * http://compass/mot.com/go/115342679 + * + * $Log iapiLowMcu.c $ + * + *****************************************************************************/ + +/* **************************************************************************** + * Include File Section + *****************************************************************************/ +#include + +#include "epm.h" +#include "iapiLow.h" + +/* **************************************************************************** + * Function Section + *****************************************************************************/ +#ifdef MCU + +/* ***************************************************************************/ +/**Send a command on SDMA's channel zero. + * Check if buffer descriptor is already used by the sdma, if yes return + * an error as c0BDNum is wrong. + * + * Notes\n + * There is an upgrade in the script on the Context load command and + * the fact that the context structure has a fixed length of 20 or 24 + * depending on SDMA versions. + * + * @return + * - IAPI_SUCCESS + * - -iapi_errno if failure + */ +int +iapi_Channel0Command( channelDescriptor * cd_p, void * buf, + unsigned short nbyte, unsigned char command) +{ + channelControlBlock * ccb_p; + bufferDescriptor * bd_p; + int result = IAPI_SUCCESS; + unsigned char chNum; + + + /* + * Check data structures are properly initialized + */ + /* Channel descriptor validity */ + if (cd_p == NULL){ + result = IAPI_ERR_CD_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* Channel control block validity */ + if (cd_p->ccb_ptr == NULL){ + result = IAPI_ERR_CCB_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* Control block & Descriptpor associated with the channel being worked on */ + chNum = cd_p->channelNumber; + ccb_p = cd_p->ccb_ptr; + + /* Is channel already in use ? */ + if (ccb_p->baseBDptr != NULL ) { + result = IAPI_ERR_BD_ALLOCATED | IAPI_ERR_CH_AVAILABLE | chNum; + iapi_errno = result; + return -result; + } + + /* Allocation of buffer descriptors */ + bd_p = (bufferDescriptor *)MALLOC(sizeof( bufferDescriptor ), SDMA_ERAM); + if (bd_p != NULL) { + ccb_p->baseBDptr = (bufferDescriptor *)iapi_Virt2Phys(bd_p); + } else { + result = IAPI_ERR_BD_ALLOCATION | IAPI_ERR_CH_AVAILABLE | chNum; + iapi_errno = result; + return -result; + } + + /* Buffer descriptor setting */ + iapi_SetBufferDescriptor( bd_p, command , BD_WRAP|BD_DONE|BD_INTR , nbyte, + buf,NULL); + + /* Actually the transfer */ + iapi_lowStartChannel( cd_p->channelNumber ); + iapi_lowSynchChannel( cd_p->channelNumber ); + + /* Cleaning of allocation */ + FREE( bd_p ); + ccb_p->baseBDptr = NULL; + + return IAPI_SUCCESS; + +} + +/* ***************************************************************************/ +/**Starts the channel (core specific register) + * + * Algorithm:\n + * - Bit numbered "channel" of HostEnStartReg register is set + * + * @param channel channel to start + * + * @return none + */ +void +iapi_lowStartChannel (unsigned char channel) +{ + SDMA_H_START |= 1 << channel; +} + +/* ***************************************************************************/ +/**Stops the channel (core specific register) + * + * Algorithm: + * - Bit numbered "channel" of HostEnStopReg register is cleared + * + * Notes:\n + * - This is a write one to clear register + * + * @param channel channel to stop + * + * @return none + */ +void +iapi_lowStopChannel (unsigned char channel) +{ + SDMA_H_STATSTOP &= 1 << channel; +} + +/* ***************************************************************************/ +/**Initialize the initial priority of registers and channel enable + * RAM from the MCU side. No channels are enabled, all priorities are set to 0. + * + * @return none + */ +void +iapi_InitChannelTables(void) +{ + + /* No channel is enabled*/ + iapi_memset((void *)&SDMA_CHNENBL_0, 0x00, sizeof(unsigned long)*EVENTS_NUM); + /* All channels have priority 0*/ + iapi_memset((void *)&SDMA_CHNPRI_0, 0x00, sizeof(unsigned long)*CH_NUM); +} + +/* ***************************************************************************/ +/** The host enable (HE), hosts override (HO), dsp enable (DE), dsp override + * (DO) registers are involved here. + * Host and Dsp enable registers are here to signify that the MCU or DSP side + * have prepared the appropriate buffers and are now ready. If the channel is + * owned by the MCU the override bit for that channel needs to be cleared : + * the host allows the channel to be used.\n + * + * Then the override bits can define (mcuOverride dspOverride):\n + * - 0 0 channel is public: transfer to/from MCU to DSP + * - 0 1 channel if owned by DSP + * - 1 0 channel if owned by MCU + * - 1 1 channel zero config + * + * See also :\n + * IAPI Table 1.1 "Channel configuration properties" + * + * @param channel channel to configure + * @param eventOverride event ownership + * @param mcuOverride ARM ownership + * @param dspOverride DSP ownership + * + * @return + * - -iapi_errno if the 3 override parameters are all set + * - IAPI_SUCCESS in other cases (valid cases) + */ +int +iapi_ChannelConfig (unsigned char channel, unsigned eventOverride, + unsigned mcuOverride, unsigned dspOverride) +{ + int result = IAPI_SUCCESS; + + if ( ( eventOverride == 1 ) && + ( mcuOverride == 1 ) && + ( dspOverride == 1 ) ){ + result = IAPI_ERR_CONFIG_OVERRIDE ; + iapi_errno = result; + return -result; + } else { + /* + * DSP side + */ + if ( dspOverride ){ + SDMA_H_DSPOVR &= ~( 1 << channel ); + } else { + SDMA_H_DSPOVR |= ( 1 << channel ); + } + /* + * Event + */ + if ( eventOverride ){ + SDMA_H_EVTOVR &= ~( 1 << channel ); + } else { + SDMA_H_EVTOVR |= ( 1 << channel ); + } + /* + * MCU side + */ + if ( mcuOverride ) { + SDMA_H_HOSTOVR &= ~( 1 << channel ); + } else { + SDMA_H_HOSTOVR |= ( 1 << channel ); + } + } + return IAPI_SUCCESS; +} +/* ***************************************************************************/ +/**Load the context data of a channel from SDMA + * + * Algorithm:\n + * - Setup BD with appropiate parameters + * - Start channel + * - Poll for answer + * + * @param *cd_p channel descriptor for channel 0 + * @param *buf pointer to receive context data + * @param channel channel for which the context data is requested + * + * @return none + */ +void +iapi_lowGetContext(channelDescriptor * cd_p, void * buf, unsigned char channel) +{ + bufferDescriptor * bd_p; + + bd_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + + /*Setup buffer descriptor with channel 0 command*/ + iapi_SetBufferDescriptor(&bd_p[0], + C0_GETDM, + (unsigned char)(BD_DONE | BD_INTR | BD_WRAP | BD_EXTD), + (unsigned short)sizeof(contextData)/4, + buf, + (void *)(CHANNEL_CONTEXT_BASE_ADDRESS + (sizeof(contextData)*channel/4))); + /* Receive, polling method*/ + iapi_lowStartChannel(cd_p->channelNumber); + iapi_lowSynchChannel(cd_p->channelNumber); +} +/* ***************************************************************************/ +/**Read "size" byte /2 at SDMA address (address) and write them in buf + * + * Algorithm:\n + * - Setup BD with appropiate parameters (C0_GETPM) + * - Start channel + * - Poll for answer + * + * Notes\n + * - Parameter "size" is in bytes, it represents the size of "buf", e.g. + * the size in bytes of the script to be loaded. + * - Parameter "address" denotes the RAM address for the script in SDMA + * + * @param *cd_p channel descriptor for channel 0 + * @param *buf pointer to receive the data + * @param size number of bytes to read + * @param address address in SDMA RAM to start reading from + * + * @return none + */ +void +iapi_lowGetScript(channelDescriptor * cd_p, void * buf, unsigned short size, + unsigned long address) +{ + bufferDescriptor * bd_p; + + bd_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + + /*Setup buffer descriptor with channel 0 command*/ + iapi_SetBufferDescriptor(&bd_p[0], + C0_GETPM, + (unsigned char)(BD_DONE | BD_INTR | BD_WRAP | BD_EXTD), + (unsigned short)size/2,/*count in shorts*/ + buf, + (void *)address); + /* Receive, polling method*/ + iapi_lowStartChannel(cd_p->channelNumber); + iapi_lowSynchChannel(cd_p->channelNumber); +} + +/* ***************************************************************************/ +/**Load a SDMA script to SDMA + * + * Algorithm:\n + * - Setup BD with appropiate parameters (C0_SETPM) + * - Start channel + * - Poll for answer + * + * Notes\b + * - Parameter "size" is in bytes, it represents the size of "buf", e.g. + * the size in bytes of the script to be uploaded. + * - Parameter "address" denotes the RAM address for the script in SDMA + * + * @param *cd_p channel descriptor for channel 0 + * @param *buf pointer to the script + * @param size size of the script, in bytes + * @param address address in SDMA RAM to place the script + * + * @return none + */ +void +iapi_lowSetScript(channelDescriptor * cd_p, void * buf, unsigned short size, + unsigned long address) +{ + bufferDescriptor * bd_p; + + bd_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + + /*Setup buffer descriptor with channel 0 command*/ + iapi_SetBufferDescriptor(&bd_p[0], + C0_SETPM, + (unsigned char)(BD_DONE | BD_INTR | BD_WRAP | BD_EXTD), + (unsigned short)size/2,/*count in shorts*/ + buf, + (void *)(address)); + /* Receive, polling method*/ + iapi_lowStartChannel(cd_p->channelNumber); + iapi_lowSynchChannel(cd_p->channelNumber); +} + + +/* ***************************************************************************/ +/**Load the context for a channel to SDMA + * + * Algorithm:\n + * - Send context and poll for answer. + * + * @param *cd_p channel descriptor for channel 0 + * @param *buf pointer to context data + * @param channel channel to place the context for + * + * @return none + */ +void +iapi_lowSetContext(channelDescriptor * cd_p, void * buf, unsigned char channel) +{ + + bufferDescriptor * local_bd_p; +#ifdef SDMA_SKYE + + unsigned char command =0; + + local_bd_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + + + command = channel <<3 ; + command = command | C0_SETCTX; + iapi_SetBufferDescriptor( &local_bd_p[0], + command, + (unsigned char)(BD_DONE | BD_INTR | BD_WRAP), + (unsigned short)(sizeof(contextData)/4), + buf, + NULL); +#else + + local_bd_p = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + + + + + iapi_SetBufferDescriptor( &local_bd_p[0], + C0_SETDM, + (unsigned char)(BD_DONE | BD_INTR | BD_WRAP|BD_EXTD), + (unsigned short)(sizeof(contextData)/4), + buf, + (void *)(2048+(sizeof(contextData)/4)*channel)); +#endif + /* Send */ + iapi_lowStartChannel( cd_p->channelNumber ); + iapi_lowSynchChannel( cd_p->channelNumber ); + +} + +/* ***************************************************************************/ +/**Associate specified channel with the script starting at the + * specified address. Channel 0 command is used to load the set-up context + * for the channel. The address used must be generated by the GUI tool + * used to create RAM images for SDMA. + * + * Algorithm:\n + * - Set-up and load the context. + * + * @param *cd_p pointer to the channel descriptor of the channel + * @param *data_p: pointer to the data identifying the script to be associated + * with the channel + * + * @return + * - IAPI_SUCCESS : OK + * - -iapi_errno : operation failed, return negated value of iapi_errno + */ + +int +iapi_lowAssignScript(channelDescriptor * cd_p, script_data * data_p) +{ + contextData * chContext; /* context to be loaded for the channel */ + channelDescriptor * cd0_p; /* pointer to channel descriptor of channel 0*/ + int result = IAPI_SUCCESS; + + /*Verify passed data*/ + if(cd_p == NULL || data_p == NULL) + { + result = IAPI_ERR_INVALID_PARAMETER; + iapi_errno = result; + return -result; + } + + /* Allocate context and initialize PC to required script start adress*/ + chContext = (contextData *) MALLOC(sizeof(contextData), SDMA_ERAM); + if (chContext == NULL) + { + result = IAPI_ERR_B_ALLOC_FAILED | cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + iapi_memset(chContext, 0x00, sizeof(contextData)); + chContext->channelState.pc = data_p->load_address; + + /* Send by context the event mask,base address for peripheral + * and watermark level + */ + chContext->gReg[0] = data_p->event_mask2; + chContext->gReg[1] = data_p->event_mask1; + chContext->gReg[6] = data_p->shp_addr; + chContext->gReg[7] = data_p->wml; + + if (data_p->per_addr) + chContext->gReg[2] = data_p->per_addr; + + /* Set transmited data to the CD*/ + cd_p->watermarkLevel = data_p->wml; + cd_p->eventMask1 = data_p->event_mask1; + cd_p->eventMask2 = data_p->event_mask2; + + /* Get the cd0_p*/ + cd0_p = (cd_p->ccb_ptr - cd_p->channelNumber)->channelDescriptor; + + /*load the context*/ + iapi_lowSetContext(cd0_p, chContext, cd_p->channelNumber); + + /* release allocated memory*/ + FREE(chContext); + + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/** Set the channels to be triggered by an event. The for every channel that + *must be triggered by the event, the corresponding bit from channel_map + *parameter must be set to 1. (e.g. for the event to trigger channels 31 and + *0 one must pass 0x80000001) + * + * + * Algorithm:\n + * - Update the register from Channel Enable RAM with the channel_map + * + * @param event event for which to set the channel association + * @param channel_map channels to be triggered by event. Put the corresponding + * bit from this 32-bit value to 1 for every channel that should be + * triggered by the event. + * + * @return + * - IAPI_SUCCESS : OK + * - -iapi_errno : operation failed, return negated value of iapi_errno + */ +int +iapi_lowSetChannelEventMapping(unsigned char event, unsigned long channel_map) +{ + volatile unsigned long * channelEnableMatx; + int result = IAPI_SUCCESS; + + /* Check validity of event*/ + if (event < EVENTS_NUM) + { + channelEnableMatx = &SDMA_CHNENBL_0; + channelEnableMatx[event] |= channel_map; + return result; + } + else + { + result = IAPI_ERR_INVALID_PARAMETER | event; + iapi_errno = result; + return -result; + } +} + +#endif /* MCU */ diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/src/iapiMiddle.c linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/src/iapiMiddle.c --- linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/src/iapiMiddle.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/src/iapiMiddle.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,623 @@ +/****************************************************************************** + * + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiMiddle.c + * + * $Id iapiMiddle.c $ + * + * Description: + * This library is written in C to guarantee functionality and integrity in + * the usage of SDMA virtual DMA channels. This API (Application Programming + * Interface) allow SDMA channels' access in an OPEN, READ, WRITE, CLOSE + * fashion. + * These are the MIDDLE level functions of the I.API. + * + * + * + * + * $Log iapiMiddle.c $ + * + *****************************************************************************/ + + +/* **************************************************************************** + * Include File Section + *****************************************************************************/ +#include "epm.h" +#include + +#include "iapiLow.h" +#include "iapiMiddle.h" + +/* **************************************************************************** + * Global Variable Section + *****************************************************************************/ + + +/* **************************************************************************** + * Function Section + *****************************************************************************/ + +/* ***************************************************************************/ +/**Allocates one Buffer Descriptor structure using information present in the + * channel descriptor. + * + * @param *ccb_p channel control block used to get the channel descriptor + * + * @return + * - pointer on the new Buffer Descriptor + * - NULL if allocation failed + * + */ +bufferDescriptor * +iapi_AllocBD (channelControlBlock * ccb_p) + +{ + bufferDescriptor * ptrBD = NULL; + + if (ccb_p->channelDescriptor->bufferDescNumber != 0){ +#ifdef CONFIG_SDMA_IRAM + channelDescriptor * cd_p = ccb_p->channelDescriptor; + if(cd_p->channelNumber >= MXC_DMA_CHANNEL_IRAM) { + ptrBD = (bufferDescriptor *) + MALLOC( ccb_p->channelDescriptor->bufferDescNumber * + sizeof(bufferDescriptor), SDMA_IRAM); + } else +#endif /*CONFIG_SDMA_IRAM*/ + { + ptrBD = (bufferDescriptor *) + MALLOC( ccb_p->channelDescriptor->bufferDescNumber * + sizeof(bufferDescriptor), SDMA_ERAM); + } + } + if (ptrBD != NULL) { + ptrBD->mode.command = 0; + ptrBD->mode.status = 0; + ptrBD->mode.count = 0; + ptrBD->bufferAddr = NULL; + } + + return ptrBD; +} + +/* ***************************************************************************/ +/**Allocate one channel context data structure. + * + * @param **ctxd_p pointer to context data to be allocated + * @param channel channel number of context data structure + * + * @return + * - IAPI_SUCCESS + * - -iapi_errno if allocation failed + */ +int +iapi_AllocContext(contextData ** ctxd_p, unsigned char channel) +{ + contextData * ctxData; + int result = IAPI_SUCCESS; + + if (*ctxd_p != NULL){ + result = IAPI_ERR_CC_ALREADY_DEFINED | IAPI_ERR_CH_AVAILABLE | channel; + iapi_errno = result; + return -result; + } + + ctxData = (contextData *)MALLOC(sizeof(contextData), SDMA_ERAM); + + if (ctxData !=NULL) { + *ctxd_p = ctxData; + return IAPI_SUCCESS; + + } else { + *ctxd_p = NULL; + result = IAPI_ERR_CC_ALLOC_FAILED | IAPI_ERR_CH_AVAILABLE | channel; + iapi_errno = result; + return -result; + } +} + +/* ***************************************************************************/ +/**Allocates channel description and fill in with default values. + * + * Algorithm:\n + * - Check channel properties. + * - Then modifies the properties of the channel description with default + * + * @param **cd_p pointer to channel descriptor to be allocated + * @param channel channel number of channel descriptor + * + * @return + * - IAPI_SUCCESS + * - -iapi_errno if allocation failed + * + */ +int +iapi_AllocChannelDesc (channelDescriptor ** cd_p, unsigned char channel) +{ +#ifdef MCU + volatile unsigned long * chPriorities = &SDMA_CHNPRI_0; +#endif /* MCU */ + channelDescriptor * tmpCDptr; + int result = IAPI_SUCCESS; + + + if (*cd_p != NULL){ + result = IAPI_ERR_CD_ALREADY_DEFINED | IAPI_ERR_CH_AVAILABLE | channel; + iapi_errno = result; + return -result; + } + + tmpCDptr = (channelDescriptor *)MALLOC(sizeof(channelDescriptor), SDMA_ERAM); + + if (tmpCDptr != NULL){ + iapi_memcpy(tmpCDptr, &iapi_ChannelDefaults, sizeof (channelDescriptor)); + tmpCDptr->channelNumber = channel; +#ifdef MCU + if (chPriorities[channel] != 0) { + tmpCDptr->priority = chPriorities[channel]; + } else { + chPriorities[channel] = tmpCDptr->priority; + } +#endif + * cd_p = tmpCDptr ; + return IAPI_SUCCESS; + } else { + * cd_p = NULL; + result = IAPI_ERR_CD_ALLOC_FAILED | IAPI_ERR_CH_AVAILABLE | channel; + iapi_errno = result; + return -result; + } +} + +/* ***************************************************************************/ +/**Changes channel description information after performing sanity checks. + * + * Algorithm:\n + * - Check channel properties. + * - Then modifies the properties of the channel description. + * + * @param *cd_p channel descriptor of the channel to change + * @param whatToChange control code indicating the desired change + * @param newval new value + * + * @return + * - IAPI_SUCCESS + * - IAPI_FAILURE if change failed + * + */ +int +iapi_ChangeChannelDesc (channelDescriptor * cd_p, unsigned char whatToChange, + unsigned long newval) +{ + bufferDescriptor * tmpBDptr; + unsigned char index = 0; + int result = IAPI_SUCCESS; + + /* verify parameter validity */ + if (cd_p == NULL) { + result = IAPI_ERR_CD_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* verify channel descriptor initialization */ + if (cd_p->ccb_ptr == NULL){ + result = IAPI_ERR_CCB_UNINITIALIZED | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + /* verify channel is not in use */ + tmpBDptr = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for (index=cd_p->bufferDescNumber ; index>0 ; index--){ + if (tmpBDptr->mode.status & BD_DONE){ + result = IAPI_ERR_CH_IN_USE | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + tmpBDptr++; + } + + /* Select the change accorded to the selector given in parameter */ + switch (whatToChange){ + + /* + * Channel Number + */ + case IAPI_CHANNELNUMBER: + /* Channel number can not be changed (description remains attached) */ + result = IAPI_ERR_CD_CHANGE_CH_NUMBER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + + /* + * Buffer Descriptor Number + */ + case IAPI_BUFFERDESCNUMBER: + if (newval < MAX_BD_NUM){ + if (newval != cd_p->bufferDescNumber){ + /* Free memory used for previous old data */ + if (cd_p->ccb_ptr->baseBDptr != NULL){ + tmpBDptr = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for (index=0 ; index < cd_p->bufferDescNumber ; index++){ + if (tmpBDptr->bufferAddr != NULL){ + if (cd_p->trust == FALSE) { + FREE(iapi_Phys2Virt(tmpBDptr->bufferAddr)); + } + } + tmpBDptr ++ ; + } + FREE((bufferDescriptor *)iapi_Phys2Virt((cd_p->ccb_ptr)->baseBDptr)); + } + (cd_p->ccb_ptr)->baseBDptr = NULL; + (cd_p->ccb_ptr)->currentBDptr = NULL; + /* Allocate and initialize structures */ + cd_p->bufferDescNumber = (unsigned char)newval; + cd_p->ccb_ptr->status.openedInit = FALSE; + if (IAPI_SUCCESS !=iapi_InitializeMemory (cd_p->ccb_ptr)) + { + result = IAPI_ERR_BD_ALLOCATION | cd_p->channelNumber; + iapi_errno = result; + return -result; + } + cd_p->ccb_ptr->status.openedInit = TRUE; + } + break; + } else { + result = IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + /* + * Buffer size + */ + case IAPI_BUFFERSIZE: + if (newval < MAX_BD_SIZE) + { + if (newval != cd_p->bufferSize) + { + /* Free memory used for previous old data */ + if (cd_p->ccb_ptr->baseBDptr != NULL) + { + tmpBDptr = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for (index=0 ; index < cd_p->bufferDescNumber ; index++) + { + if (cd_p->trust == FALSE) + { + FREE(iapi_Phys2Virt(tmpBDptr->bufferAddr)); + } + tmpBDptr ++ ; + } + FREE((bufferDescriptor *)iapi_Phys2Virt((cd_p->ccb_ptr)->baseBDptr)); + } + (cd_p->ccb_ptr)->baseBDptr = NULL; + (cd_p->ccb_ptr)->currentBDptr = NULL; + /* Allocate and initialize structures */ + cd_p->bufferSize = (unsigned short)newval; + cd_p->ccb_ptr->status.openedInit = FALSE; + if (IAPI_SUCCESS !=iapi_InitializeMemory (cd_p->ccb_ptr)) + { + result = IAPI_ERR_BD_ALLOCATION | cd_p->channelNumber; + iapi_errno = result; + return -result; + } + cd_p->ccb_ptr->status.openedInit = TRUE; + } + break; + } + else + { + result = IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + + /* + * Blocking / non blocking feature + */ + case IAPI_BLOCKING: + if (newval < MAX_BLOCKING){ + cd_p->blocking = newval; + break; + } else { + result = IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + /* + * Synchronization method + */ + case IAPI_CALLBACKSYNCH: + if (newval < MAX_SYNCH){ + cd_p->callbackSynch = newval; + iapi_ChangeCallbackISR( cd_p, cd_p->callbackISR_ptr); + break; + } else { + result = IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + + /* + * Ownership of the channel + */ + case IAPI_OWNERSHIP: +#ifdef DSP + result = IAPI_ERR_NOT_ALLOWED | cd_p->channelNumber; + iapi_errno = result; + return -result; +#endif /* DSP */ +#ifdef MCU + if (newval < MAX_OWNERSHIP){ + cd_p->ownership = newval; + iapi_ChannelConfig( cd_p->channelNumber, + ( newval >> CH_OWNSHP_OFFSET_EVT ) & 1, + ( newval >> CH_OWNSHP_OFFSET_MCU ) & 1, + ( newval >> CH_OWNSHP_OFFSET_DSP ) & 1); + break; + } else { + result = IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + +#endif /* MCU */ + + /* + * Priority + */ + case IAPI_PRIORITY: +#ifdef DSP + result = IAPI_ERR_NOT_ALLOWED | cd_p->channelNumber; + iapi_errno = result; + return -result; +#endif /* DSP */ + +#ifdef MCU + if (newval < MAX_CH_PRIORITY){ + volatile unsigned long * ChannelPriorities = &SDMA_CHNPRI_0; + ChannelPriorities[ cd_p->channelNumber ] = newval; + break; + } else { + result = IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } +#endif /* MCU */ + + + /* + * "Trust" property + */ + case IAPI_TRUST: + if (newval < MAX_TRUST){ + if (cd_p->trust != newval){ + cd_p->trust = newval; + if (newval == FALSE) { + if (IAPI_SUCCESS !=iapi_InitializeMemory (cd_p->ccb_ptr)) + { + result = IAPI_ERR_BD_ALLOCATION | cd_p->channelNumber; + iapi_errno = result; + return -result; + } + } + } + break; + } else { + result = IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + /* + * Callback function pointer + */ + case IAPI_CALLBACKISR_PTR: + if ( (void *)newval != NULL){ + { + union { + void * voidstar; + void (* funcptr)(channelDescriptor * cd_p, void * arg); + } value; + value.voidstar = (void*) newval; + cd_p->callbackISR_ptr = value.funcptr; + } + iapi_ChangeCallbackISR( cd_p, cd_p->callbackISR_ptr); + break; + } else { + result = IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + + /* + * Channel Control Block pointer + */ + case IAPI_CCB_PTR: + cd_p->ccb_ptr = (channelControlBlock *)newval; + cd_p->ccb_ptr->channelDescriptor = cd_p; + break; + + /* + * WRAP/UNWRAP + */ + case IAPI_BDWRAP: + /* point to first BD */ + tmpBDptr = (bufferDescriptor *)iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + /* to point to last BD */ + tmpBDptr += cd_p->bufferDescNumber - 1; + if (newval == TRUE){ + /* wrap last BD */ + tmpBDptr->mode.status |= BD_WRAP; + break; + } + else if (newval == FALSE){ + /* unwrap last BD */ + tmpBDptr->mode.status &= ~BD_WRAP; + break; + } + else { + result = IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + + /* + * Watermark level + */ + case IAPI_WML: +#ifdef DSP + result = IAPI_ERR_NOT_ALLOWED | cd_p->channelNumber; + iapi_errno = result; + return -result; +#endif /* DSP */ +#ifdef MCU + if (newval < MAX_WML){ + if (cd_p->watermarkLevel != newval){ + cd_p->watermarkLevel = newval; + } + break; + } + else { + result = IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } +#endif /* MCU */ + + /* + * Detect errors + */ + default: + result = IAPI_ERR_CD_CHANGE_UNKNOWN | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + return IAPI_SUCCESS; +} + + +/* ***************************************************************************/ +/**Initialize a table of function pointers that contain the interrupt Service + * Routine callback pointers for the SDMA channels with a default value + * + * Algorithm:\n + * - Loop on each element of the global IAPI variable callbackIsrTable + * + * @param *func_p default callback functon for all SDMA channels + * + * @return none + */ +void +iapi_InitializeCallbackISR(void(* func_p)(channelDescriptor * cd_p, void * arg)) +{ + unsigned long chCnt; + + for (chCnt = 0 ; chCnt < CH_NUM ; chCnt++){ + callbackIsrTable[chCnt] = func_p; + } +} + +/* ***************************************************************************/ +/**For the specified channel control block, attach the array of buffer + * descriptors, the channel description structure and initialize channel's + * status using information in the channel descriptor. + * + * @param *ccb_p pointer to channel control block + * + * @return none + * + */ +int +iapi_InitializeMemory (channelControlBlock * ccb_p) +{ + bufferDescriptor * bd_p; + unsigned char index; + int result = IAPI_SUCCESS; + + /* Attach the array of Buffer descriptors */ + bd_p = iapi_AllocBD( ccb_p ); + if (bd_p != NULL) + { + ccb_p->baseBDptr = (bufferDescriptor *)iapi_Virt2Phys(bd_p); + ccb_p->currentBDptr = ccb_p->baseBDptr; + for(index=0 ;index < ccb_p->channelDescriptor->bufferDescNumber-1 ; index++) + { + if (ccb_p->channelDescriptor->trust == TRUE) + { + iapi_SetBufferDescriptor(bd_p, + (unsigned char)ccb_p->channelDescriptor->dataSize, + BD_CONT|BD_EXTD, ccb_p->channelDescriptor->bufferSize, + NULL, NULL); + } + else + { + if (ccb_p->channelDescriptor->bufferSize != 0) + { + iapi_SetBufferDescriptor(bd_p, + (unsigned char)ccb_p->channelDescriptor->dataSize, + BD_CONT|BD_EXTD, ccb_p->channelDescriptor->bufferSize, + MALLOC(ccb_p->channelDescriptor->bufferSize, SDMA_ERAM), NULL); + } + } + bd_p++; + } + + if (ccb_p->channelDescriptor->trust == TRUE) + { + iapi_SetBufferDescriptor(bd_p, + (unsigned char)ccb_p->channelDescriptor->dataSize, + BD_EXTD|BD_WRAP|BD_INTR, ccb_p->channelDescriptor->bufferSize, + NULL, NULL); + } + else + { + if (ccb_p->channelDescriptor->bufferSize != 0) + { + iapi_SetBufferDescriptor(bd_p, + (unsigned char)ccb_p->channelDescriptor->dataSize, + BD_EXTD|BD_WRAP|BD_INTR, + ccb_p->channelDescriptor->bufferSize, + MALLOC(ccb_p->channelDescriptor->bufferSize, SDMA_ERAM), NULL); + } + } + } + else + { + result = IAPI_ERR_BD_ALLOCATION; + return -result; + } + return result; +} diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/src/iapiMiddleMcu.c linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/src/iapiMiddleMcu.c --- linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/src/iapiMiddleMcu.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/src/iapiMiddleMcu.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,52 @@ +/****************************************************************************** + * + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiMiddleMcu.c + * + * $Id iapiMiddleMcu.c $ + * + * Description: + * This library is written in C to guarantee functionality and integrity in + * the usage of SDMA virtual DMA channels. This API (Application Programming + * Interface) allow SDMA channels' access in an OPEN, READ, WRITE, CLOSE + * fashion. + * These are the MIDDLE level functions of the I.API specific to MCU. + * + * + * + * + * $Log iapiMiddleMcu.c $ + * + *****************************************************************************/ + +/* **************************************************************************** + * Include File Section + *****************************************************************************/ +#include "epm.h" +#include + +#include "iapiLow.h" +#include "iapiMiddle.h" + +/* **************************************************************************** + * Global Variable Section + *****************************************************************************/ + +/*extern void * __HEAP_START; +extern void * __HEAP_END; +*/ + +/* **************************************************************************** + * Function Section + *****************************************************************************/ diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/src/iapiOS.c linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/src/iapiOS.c --- linux-2.6.26/arch/arm/plat-mxc/sdma/iapi/src/iapiOS.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/iapi/src/iapiOS.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,64 @@ +/****************************************************************************** + * + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiOS.c + * + * $Id iapiOS.c $ + * + * Description: + * This library is written in C to guarantee functionality and integrity in + * the usage of SDMA virtual DMA channels. This API (Application Programming + * Interface) allow SDMA channels' access in an OPEN, READ, WRITE, CLOSE + * fashion. + * These are the OS level functions of the I.API - are OS dependant and must + * be provided by the user of I.API. + * + * + * / + * + * $Log iapiOS.c $ + * + *****************************************************************************/ + +/* **************************************************************************** + * Include File Section + *****************************************************************************/ +#include "epm.h" +#include "iapiLow.h" + +/** + * Function Section + */ +#ifdef CONFIG_SDMA_IRAM +void*(* iapi_iram_Malloc) (size_t size); +#endif /*CONFIG_SDMA_IRAM*/ + +void*(* iapi_Malloc) (size_t size); +void (* iapi_Free) (void * ptr); + +void*(* iapi_Virt2Phys) (void * ptr); +void*(* iapi_Phys2Virt) (void * ptr); + +void (* iapi_WakeUp)(int); +void (* iapi_GotoSleep)(int); +void (* iapi_InitSleep)(int); + +void*(* iapi_memcpy)(void *dest, const void *src, size_t count); +void*(* iapi_memset)(void *dest, int c, size_t count); + +void (* iapi_EnableInterrupts)(void); +void (* iapi_DisableInterrupts)(void); + +int (* iapi_GetChannel)(int); +int (* iapi_ReleaseChannel)(int); diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/sdma.c linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/sdma.c --- linux-2.6.26/arch/arm/plat-mxc/sdma/sdma.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/sdma.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,1484 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file plat-mxc/sdma/sdma.c + * @brief This file contains functions for Smart DMA API + * + * SDMA (Smart DMA) is used for transferring data between MCU and peripherals + * + * @ingroup SDMA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include + +#include "iapi.h" + +#define M3_BASE_ADDRESS CSD0_BASE_ADDR +#define CHAD(ch) sdma_data[0].cd->ccb_ptr[ch].channelDescriptor + +/*! + * SDMA status mutex + */ +static struct semaphore sdma_status_mutex; + +/*! + * SDMA channel sleep queues + */ +//static struct semaphore sdma_sleep_mutex[MAX_DMA_CHANNELS]; +static wait_queue_head_t sdma_sleep_queue[MAX_DMA_CHANNELS]; + +/*! + * SDMA channel synchronization + */ +static struct semaphore sdma_synch_mutex[MAX_DMA_CHANNELS]; + +/*! + * SDMA buffers pool initialization function + */ +extern void init_sdma_pool(void); + +/*! + * Flags are save and restored during interrupt handler + */ +unsigned long flags; + +struct clk *mxc_sdma_ahb_clk, *mxc_sdma_ipg_clk; + +/*! + * Structure containing sdma channels information. + */ +typedef struct { + /*! Channel number */ + int channel; + /*! Channel usage name */ + int in_use; + /*! Name of device using the channel */ + char devicename[MAX_DEVNAME_LENGTH]; + /*! Transfer type. Needed for setting SDMA script */ + sdma_transferT transfer_type; + /*! Peripheral type. Needed for setting SDMA script */ + sdma_periphT peripheral_type; + /*! Watermark level of device's fifo */ + __u32 watermark_level; + /*! Peripheral event id */ + int event_id; + /*! Peripheral event id2 (for channels that use 2 events) */ + int event_id2; + /*! Running status (boolean) */ + int running; + /*! buffer descriptors number */ + int bd_number; + /*! callback function */ + dma_callback_t callback; + /*! callback argument */ + void *arg; + /*! SDMA data access word size */ + unsigned long word_size:8; + /*! channel descriptor pointer */ + channelDescriptor *cd; +} sdma_struct; + +/*! + * Used to save the status of channels. + */ +static sdma_struct sdma_data[MAX_DMA_CHANNELS]; + +/*! + * Stores the start address of the SDMA scripts + */ +static sdma_script_start_addrs sdma_script_addrs; + +extern void mxc_sdma_get_script_info(sdma_script_start_addrs * sdma_script_add); + +/*! + * Init sleep mutex of the channel + * + * @param channel channel number + */ +static void sdma_init_sleep(int channel) +{ + init_waitqueue_head(&sdma_sleep_queue[channel]); +} + +/*! + * Puts channel to sleep + * + * @param channel channel number + */ +static void sdma_sleep_channel(int channel) +{ + while ((iapi_SDMAIntr & (1 << channel)) == 0) { + wait_event_interruptible(sdma_sleep_queue[channel], + ((iapi_SDMAIntr & (1 << channel)) != + 0)); + } +} + +/*! + * Wake up channel from sleep + * + * @param channel channel number + */ +static void sdma_wakeup_channel(int channel) +{ + wake_up_interruptible(&sdma_sleep_queue[channel]); +} + +/*! + * Sdma interrupt handler routine. + * Calls channels callback function + * + * @param irq the interrupt number + * @param dev_id driver private data + * @return the function returns \b IRQ_RETVAL(1) - interrupt was handled + */ +static irqreturn_t sdma_int_handler(int irq, void *dev_id) +{ + IRQ_Handler(); + return IRQ_RETVAL(1); +} + +/*! + * I.API channel callback function + * + * @param cd channel descriptor structure + * @param channel_data SDMA struct of the current channel + */ +static void iapi_interrupt_callback(channelDescriptor * cd, + sdma_struct * channel_data) +{ + int channel; + dma_callback_t callback; + void *arg; + + channel = channel_data->channel; + + channel_data->running = 0; + + arg = channel_data->arg; + + if (arg == 0) { + arg = (void *)&channel; + } + + callback = channel_data->callback; + + if (callback != 0) { + callback(arg); + } +} + +/*! + * Returns pc of SDMA script according to peripheral and transfer type + * + * @param peripheral_type peripheral type + * @param transfer_type transfer type + * + * @return PC of SDMA script +*/ +static unsigned short sdma_get_pc(sdma_periphT peripheral_type, + sdma_transferT transfer_type) +{ + int res = 0; + + if (peripheral_type == MEMORY) { + switch (transfer_type) { + case emi_2_int: + res = sdma_script_addrs.mxc_sdma_ap_2_ap_addr; + break; + case emi_2_emi: + res = sdma_script_addrs.mxc_sdma_ap_2_ap_addr; + break; + case int_2_emi: + res = sdma_script_addrs.mxc_sdma_ap_2_ap_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == DSP) { + switch (transfer_type) { + case emi_2_dsp: + res = sdma_script_addrs.mxc_sdma_ap_2_bp_addr; + break; + case dsp_2_emi: + res = sdma_script_addrs.mxc_sdma_bp_2_ap_addr; + break; + case dsp_2_emi_loop: + res = + sdma_script_addrs. + mxc_sdma_loopback_on_dsp_side_addr; + break; + case emi_2_dsp_loop: + res = + sdma_script_addrs.mxc_sdma_mcu_interrupt_only_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == FIRI) { + switch (transfer_type) { + case per_2_int: + res = sdma_script_addrs.mxc_sdma_firi_2_per_addr; + break; + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_firi_2_mcu_addr; + break; + case int_2_per: + res = sdma_script_addrs.mxc_sdma_per_2_firi_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_firi_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == UART) { + switch (transfer_type) { + case per_2_int: + res = sdma_script_addrs.mxc_sdma_uart_2_per_addr; + break; + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_uart_2_mcu_addr; + break; + case int_2_per: + res = sdma_script_addrs.mxc_sdma_per_2_app_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_app_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == UART_SP) { + switch (transfer_type) { + case per_2_int: + res = sdma_script_addrs.mxc_sdma_uartsh_2_per_addr; + break; + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_uartsh_2_mcu_addr; + break; + case int_2_per: + res = sdma_script_addrs.mxc_sdma_per_2_shp_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_shp_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == ATA) { + switch (transfer_type) { + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_ata_2_mcu_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_ata_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == CSPI || peripheral_type == EXT || + peripheral_type == SSI) { + switch (transfer_type) { + case per_2_int: + res = sdma_script_addrs.mxc_sdma_app_2_per_addr; + break; + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_app_2_mcu_addr; + break; + case int_2_per: + res = sdma_script_addrs.mxc_sdma_per_2_app_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_app_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == SSI_SP || peripheral_type == MMC || + peripheral_type == SDHC || peripheral_type == CSPI_SP || + peripheral_type == ESAI || peripheral_type == MSHC_SP) { + switch (transfer_type) { + case per_2_int: + res = sdma_script_addrs.mxc_sdma_shp_2_per_addr; + break; + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_shp_2_mcu_addr; + break; + case int_2_per: + res = sdma_script_addrs.mxc_sdma_per_2_shp_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_shp_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == ASRC) { + switch (transfer_type) { + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_asrc_2_mcu_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_asrc_2_mcu_addr; + break; + case per_2_per: + res = sdma_script_addrs.mxc_sdma_per_2_per_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == MSHC) { + switch (transfer_type) { + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_mshc_2_mcu_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_mshc_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == CCM) { + switch (transfer_type) { + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_dptc_dvfs_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == FIFO_MEMORY) { + res = sdma_script_addrs.mxc_sdma_ap_2_ap_fixed_addr; + } else if (peripheral_type == SPDIF) { + switch (transfer_type) { + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_spdif_2_mcu_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_spdif_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == IPU_MEMORY) { + if (transfer_type == emi_2_per) { + res = sdma_script_addrs.mxc_sdma_ext_mem_2_ipu_addr; + } else { + res = -EINVAL; + } + } + + if (res < 0) { + printk(KERN_ERR "SDMA script not found\n"); + } + + return res; + +} + +static inline int sdma_asrc_set_info(dma_channel_params *p, + script_data *pcontext, int eflags) +{ + dma_channel_ext_params *ep = (dma_channel_ext_params *)p; + unsigned int wml, tmp, wml1, wml2; + dma_channel_asrc_info_t *info = &(ep->info.asrc); + wml = 0; + if (p->transfer_type == per_2_per) { + if (!p->ext) + return wml; + wml1 = p->watermark_level; + wml2 = ep->watermark_level2; + if (info->channs) { + wml |= (info->channs & SDMA_ASRC_INFO_N_MASK) << + SDMA_ASRC_INFO_N_OFF; + if (ep->p2p_dir) + wml2 *= info->channs & SDMA_ASRC_INFO_N_MASK; + else + wml1 *= info->channs & SDMA_ASRC_INFO_N_MASK; + } + if (info->channs & 1) { + if (ep->p2p_dir) + wml |= SDMA_ASRC_P2P_INFO_PS; + else + wml |= SDMA_ASRC_P2P_INFO_PA; + } + if (wml1 > wml2) { + tmp = wml2 & SDMA_ASRC_P2P_INFO_LWML_MASK; + wml |= tmp << SDMA_ASRC_P2P_INFO_LWML_OFF; + tmp = wml1 & SDMA_ASRC_P2P_INFO_HWML_MASK; + wml |= tmp << SDMA_ASRC_P2P_INFO_HWML_OFF; + if (eflags & (1 << 31)) + wml |= SDMA_ASRC_P2P_INFO_LWE; + if (eflags & (1 << 30)) + wml |= SDMA_ASRC_P2P_INFO_HWE; + } else { + tmp = wml1 & SDMA_ASRC_P2P_INFO_LWML_MASK; + wml |= tmp << SDMA_ASRC_P2P_INFO_LWML_OFF; + tmp = wml2 & SDMA_ASRC_P2P_INFO_HWML_MASK; + wml |= tmp << SDMA_ASRC_P2P_INFO_HWML_OFF; + wml |= eflags >> 2; + tmp = pcontext->event_mask2; + pcontext->event_mask2 = pcontext->event_mask1; + pcontext->event_mask1 = tmp; + } + } else { + if (p->ext && info->channs) { + wml |= (info->channs & SDMA_ASRC_INFO_N_MASK) << + SDMA_ASRC_INFO_N_OFF; + tmp = (info->channs * p->watermark_level) & + SDMA_ASRC_INFO_WML_MASK; + wml |= tmp << SDMA_ASRC_INFO_WML_OFF; + } else { + tmp = (p->watermark_level & SDMA_ASRC_INFO_WML_MASK); + wml |= tmp << SDMA_ASRC_INFO_WML_OFF; + } + + if (p->transfer_type == per_2_emi) + wml |= SDMA_ASRC_INFO_TXFR_DIR; + + if (p->ext && (info->channs & 1)) { + if (p->transfer_type == per_2_emi) + wml |= SDMA_ASRC_INFO_PS; + else + wml |= SDMA_ASRC_INFO_PA; + } + wml |= eflags; + } + return wml; +} + +/*! + * Downloads channel context according to channel parameters + * + * @param channel channel number + * @param p channel parameters + */ +static int sdma_load_context(int channel, dma_channel_params * p) +{ + script_data context; + int res; + int event1_greater_than_32; + int event2_greater_than_32; + dma_channel_ext_params *ep = (dma_channel_ext_params *)p; + + res = 0; + + memset(&context, 0, sizeof(script_data)); + context.load_address = sdma_get_pc(p->peripheral_type, + p->transfer_type); + + if (context.load_address > 0) { + if ((p->peripheral_type != MEMORY) + && (p->peripheral_type != DSP)) { + /* Handle multiple event channels differently */ + if (p->event_id2) { + if (p->event_id2 < 32) { + context.event_mask2 = + 0x1 << p->event_id2; + event2_greater_than_32 = 0; + } else { + context.event_mask2 = + 0x1 << (p->event_id2 - 32); + event2_greater_than_32 = 1 << 31; + } + if (p->event_id < 32) { + context.event_mask1 = + 0x1 << p->event_id; + event1_greater_than_32 = 0; + } else { + context.event_mask1 = + 0x1 << (p->event_id - 32); + event1_greater_than_32 = 1 << 30; + } + } else { + event1_greater_than_32 = 0; + event2_greater_than_32 = 0; + if (p->event_id < 32) { + context.event_mask1 = + 0x1 << p->event_id; + context.event_mask2 = 0; + } else { + context.event_mask1 = 0; + context.event_mask2 = + 0x1 << (p->event_id - 32); + } + } + + if (p->ext) + context.wml = ep->info_bits; + /* Watermark Level */ + if (p->peripheral_type == ASRC) { + context.wml |= sdma_asrc_set_info(p, + &context, + event2_greater_than_32 + | + event1_greater_than_32 + ); + } else + context.wml |= event2_greater_than_32 | + event1_greater_than_32 | p->watermark_level; + + /* Address */ + context.shp_addr = (unsigned long)(p->per_address); + if (p->ext) + context.per_addr = ep->per_address2; + iapi_IoCtl(sdma_data[channel].cd, + IAPI_CHANGE_PERIPHADDR, p->per_address); + } else { + context.wml = M3_BASE_ADDRESS; + } + + sdma_data[channel].transfer_type = p->transfer_type; + sdma_data[channel].peripheral_type = p->peripheral_type; + sdma_data[channel].watermark_level = p->watermark_level; + iapi_AssignScript(sdma_data[channel].cd, &context); + } else { + res = context.load_address; + } + + return res; +} + +/*! + * Setup channel according to parameters. Must be called once after mxc_request_dma() + * + * @param channel channel number + * @param p channel parameters pointer + * @return 0 on success, error code on fail + */ +int mxc_dma_setup_channel(int channel, dma_channel_params * p) +{ + int err = 0; + int i; + + mxc_dma_stop(channel); + + for (i = 0; i < sdma_data[channel].bd_number; i++) { + iapi_IoCtl(sdma_data[channel].cd, + (i << BD_NUM_OFFSET) | + IAPI_CHANGE_SET_STATUS, (unsigned long)0); + } + + sdma_data[channel].bd_number = (p->bd_number <= 0) ? 1 : p->bd_number; + + sdma_data[channel].word_size = p->word_size; + + sdma_data[channel].event_id = p->event_id; + sdma_data[channel].event_id2 = p->event_id2; + + sdma_data[channel].callback = p->callback; + + sdma_data[channel].arg = p->arg; + + err = iapi_IoCtl(sdma_data[channel].cd, + IAPI_CHANGE_BDNUM, sdma_data[channel].bd_number); + + if (err < 0) { + printk(KERN_ERR "Failed allocating buffer \ +descriptors (0x%x)\n", err); + err = -ENOMEM; + goto setup_channel_fail; + } + + if (channel != 0) { + switch (p->transfer_type) { + case dsp_2_per: + break; + case emi_2_per: + case int_2_per: + case per_2_int: + case per_2_emi: + case per_2_per: + /* + * Peripheral <------> Memory + * evtOvr = 0 dspOvr = 1 + */ + iapi_IoCtl(sdma_data[channel].cd, IAPI_CHANGE_OWNERSHIP, + (OWN_CHANNEL << CH_OWNSHP_OFFSET_EVT) | + (OWN_CHANNEL << CH_OWNSHP_OFFSET_MCU) | + (DONT_OWN_CHANNEL << CH_OWNSHP_OFFSET_DSP)); + if (p->event_id) { + err = iapi_SetChannelEventMapping(p->event_id, + 0x1 << + channel); + } + if (!err && p->event_id2) { + err = iapi_SetChannelEventMapping(p->event_id2, + 0x1 << + channel); + } + break; + case emi_2_dsp: + case int_2_dsp: + case dsp_2_int: + case dsp_2_emi: + case dsp_2_dsp: + /* + * DSP <-----------> Memory + * evtOvr = 1 dspOvr = 0 + */ + iapi_IoCtl(sdma_data[channel].cd, IAPI_CHANGE_OWNERSHIP, + (DONT_OWN_CHANNEL << CH_OWNSHP_OFFSET_EVT) | + (OWN_CHANNEL << CH_OWNSHP_OFFSET_MCU) | + (OWN_CHANNEL << CH_OWNSHP_OFFSET_DSP)); + break; + case emi_2_int: + case emi_2_emi: + case int_2_int: + case int_2_emi: + case emi_2_dsp_loop: + case dsp_2_emi_loop: + /* evtOvr = 1 dspOvr = 1 */ + iapi_IoCtl(sdma_data[channel].cd, IAPI_CHANGE_OWNERSHIP, + (DONT_OWN_CHANNEL << CH_OWNSHP_OFFSET_EVT) | + (OWN_CHANNEL << CH_OWNSHP_OFFSET_MCU) | + (DONT_OWN_CHANNEL << CH_OWNSHP_OFFSET_DSP)); + break; + case per_2_dsp: + /* evtOvr = 0 dspOvr = 0 */ + iapi_IoCtl(sdma_data[channel].cd, IAPI_CHANGE_OWNERSHIP, + (OWN_CHANNEL << CH_OWNSHP_OFFSET_EVT) | + (DONT_OWN_CHANNEL << CH_OWNSHP_OFFSET_MCU) | + (OWN_CHANNEL << CH_OWNSHP_OFFSET_DSP)); + err = iapi_SetChannelEventMapping(p->event_id, + 0x1 << channel); + break; + default: + break; + printk(KERN_ERR "Wrong SDMA transfer type\n"); + err = -EINVAL; + } + if (err == 0) { + err = sdma_load_context(channel, p); + iapi_IoCtl(sdma_data[channel].cd, IAPI_CHANGE_PRIORITY, + MXC_SDMA_DEFAULT_PRIORITY); + } + } + setup_channel_fail: + return err; +} + +/*! + * Setup the channel priority. This can be used to change the default priority + * for the channel. + * + * @param channel channel number + * @param priority priority to be set for the channel + * + * @return 0 on success, error code on failure + */ +int mxc_dma_set_channel_priority(unsigned int channel, unsigned int priority) +{ + if (priority < MXC_SDMA_MIN_PRIORITY + || priority > MXC_SDMA_MAX_PRIORITY) { + return -EINVAL; + } + return iapi_IoCtl(sdma_data[channel].cd, IAPI_CHANGE_PRIORITY, + priority); +} + +/*! + * Allocates dma channel. + * If channel's value is 0, then the function allocates a free channel + * dynamically and sets its value to channel. + * Else allocates requested channel if it is free. + * If the channel is busy or no free channels (in dynamic allocation) -EBUSY returned. + * + * @param channel pointer to channel number + * @param devicename device name + * @return 0 on success, error code on fail + */ +int mxc_request_dma(int *channel, const char *devicename) +{ + int i, res; + + res = 0; + + down(&sdma_status_mutex); + + /* Dynamic allocation */ + if (*channel == 0) { + for (i = MAX_DMA_CHANNELS - 1; i > 0; i--) { +#ifdef CONFIG_SDMA_IRAM + /*TODO:It will be removed after DPTC used UDMA interface */ + if (i >= MXC_DMA_CHANNEL_IRAM) + continue; +#endif /*CONFIG_SDMA_IRAM */ + if (!sdma_data[i].in_use) { + *channel = i; + break; + } + } + } + + if (*channel > 0 && *channel < MAX_DMA_CHANNELS && + sdma_data[*channel].in_use == 0) { + res = iapi_Open(sdma_data[0].cd, *channel); + + if (res < 0) { + printk(KERN_ERR "Failed iapi_Open channel %d, 0x%x\n", + *channel, res); + } else { + sdma_data[*channel].in_use = 1; + strcpy(sdma_data[*channel].devicename, devicename); + sdma_data[*channel].cd = CHAD(*channel); + + iapi_IoCtl(sdma_data[*channel].cd, IAPI_CHANGE_SYNCH, + CALLBACK_ISR); + iapi_IoCtl(sdma_data[*channel].cd, + IAPI_CHANGE_CALLBACKFUNC, + (unsigned long)iapi_interrupt_callback); + iapi_IoCtl(sdma_data[*channel].cd, + IAPI_CHANGE_USER_ARG, + (unsigned long)&(sdma_data[*channel])); + } + } else { + res = -EBUSY; + } + + up(&sdma_status_mutex); + + return res; +} + +/*! + * Configures request parameters. Can be called multiple times after + * mxc_request_dma() and mxc_dma_setup_channel(). + * + * + * @param channel channel number + * @param p request parameters pointer + * @param bd_index index of buffer descriptor to set + * @return 0 on success, error code on fail + */ +int mxc_dma_set_config(int channel, dma_request_t * p, int bd_index) +{ + unsigned char param; + + if (!sdma_data[channel].in_use) { + return -EINVAL; + } + + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_SET_TRANSFER_CD, sdma_data[channel].word_size); + + param = BD_DONE | BD_INTR | BD_EXTD; + + if (sdma_data[channel].bd_number > 1 && p->bd_cont == 1) { + param |= BD_CONT; + } + + if (bd_index == sdma_data[channel].bd_number - 1) { + param |= BD_WRAP; + } + + switch (sdma_data[channel].transfer_type) { + case emi_2_per: + case dsp_2_per: + case int_2_per: + case emi_2_dsp: + case int_2_dsp: + case emi_2_dsp_loop: + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_SET_BUFFERADDR, + (unsigned long)p->sourceAddr); + break; + case per_2_int: + case per_2_emi: + case per_2_dsp: + case dsp_2_int: + case dsp_2_emi: + case dsp_2_dsp: + case dsp_2_emi_loop: + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_SET_BUFFERADDR, + (unsigned long)p->destAddr); + break; + case emi_2_int: + case emi_2_emi: + case int_2_int: + case int_2_emi: + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_SET_BUFFERADDR, + (unsigned long)p->sourceAddr); + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_SET_EXTDBUFFERADDR, + (unsigned long)p->destAddr); + break; + default: + break; + } + + /* Change the endianness for DSP to MCU Data transfers */ + if (sdma_data[channel].transfer_type == dsp_2_emi || + sdma_data[channel].transfer_type == emi_2_dsp) { + iapi_IoCtl(sdma_data[channel].cd, IAPI_CHANGE_SET_ENDIANNESS, + SET_BIT_ALL); + } + + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_SET_COUNT, p->count); + + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | IAPI_CHANGE_SET_STATUS, param); + + return 0; +} + +/*! + * Configures the BD_INTR bit on a buffer descriptor parameters. + * + * + * @param channel channel number + * @param bd_index index of buffer descriptor to set + * @param bd_intr flag to set or clear the BD_INTR bit + * @return 0 on success, error code on fail + */ +void mxc_dma_set_bd_intr(int channel, int bd_index, int bd_intr) +{ + unsigned long param; + + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_GET_STATUS, (unsigned long)¶m); + + if (bd_intr) { + param |= BD_INTR; + } else { + param &= ~BD_INTR; + } + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | IAPI_CHANGE_SET_STATUS, param); + +} + +/*! + * Gets the BD_INTR bit on a buffer descriptor. + * + * + * @param channel channel number + * @param bd_index index of buffer descriptor to set + * + * @return returns the BD_INTR bit status + */ +int mxc_dma_get_bd_intr(int channel, int bd_index) +{ + unsigned long bd_status = 0; + + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_GET_STATUS, (unsigned long)&bd_status); + + return (bd_status & BD_INTR); +} + +/*! + * Stop the current transfer + * + * @param channel channel number + * @param buffer_number number of buffers (beginning with 0), + * whose done bits should be reset to 0 + */ +int mxc_dma_reset(int channel, int buffer_number) +{ + unsigned char param = 0; + int i = 0; + + if (!sdma_data[channel].in_use) { + return -EINVAL; + } + + /* clear the BD_DONE bits for all the necessary buffers */ + for (i = 0; i < buffer_number; i++) { + + iapi_IoCtl(sdma_data[channel].cd, (i << BD_NUM_OFFSET) | + IAPI_CHANGE_GET_STATUS, (unsigned long)¶m); + + /* clear the BD_DONE bit of the buffer */ + param = param & (~BD_DONE); + + iapi_IoCtl(sdma_data[channel].cd, (i << BD_NUM_OFFSET) | + IAPI_CHANGE_SET_STATUS, param); + } + + return 0; +} + +/*! + * Returns request parameters. + * + * @param channel channel number + * @param p request parameters pointer + * @param bd_index index of buffer descriptor to get + * @return 0 on success, error code on fail + */ +int mxc_dma_get_config(int channel, dma_request_t * p, int bd_index) +{ + int err = 0; + unsigned long bd_status; + unsigned long bd_count; + __u8 *sourceAddr; + __u8 *destAddr; + + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_GET_STATUS, (unsigned long)&bd_status); + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_GET_COUNT, (unsigned long)&bd_count); + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_GET_BUFFERADDR, (unsigned long)&sourceAddr); + + switch (sdma_data[channel].transfer_type) { + case emi_2_per: + case dsp_2_per: + case int_2_per: + case emi_2_dsp: + case int_2_dsp: + case emi_2_dsp_loop: + p->sourceAddr = sourceAddr; + break; + case per_2_int: + case per_2_emi: + case per_2_dsp: + case dsp_2_int: + case dsp_2_emi: + case dsp_2_dsp: + case dsp_2_emi_loop: + p->destAddr = sourceAddr; + break; + case emi_2_int: + case emi_2_emi: + case int_2_int: + case int_2_emi: + p->sourceAddr = sourceAddr; + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_GET_EXTDBUFFERADDR, + (unsigned long)&destAddr); + p->destAddr = destAddr; + break; + default: + break; + } + + p->count = bd_count; + p->bd_done = bd_status & BD_DONE; + p->bd_cont = bd_status & BD_CONT; + p->bd_error = bd_status & BD_RROR; + + return err; +} + +/*! + * This function is used by MXC IPC's write_ex2. It passes the pointer to the + * data control structure to iapi_write_ipcv2() + * + * @param channel SDMA channel number + * @param ctrl_ptr Data Control structure pointer + */ +int mxc_sdma_write_ipcv2(int channel, void *ctrl_ptr) +{ + return iapi_Write_ipcv2(sdma_data[channel].cd, ctrl_ptr); +} + +/*! + * This function is used by MXC IPC's read_ex2. It passes the pointer to the + * data control structure to iapi_read_ipcv2() + * + * @param channel SDMA channel number + * @param ctrl_ptr Data Control structure pointer + */ +int mxc_sdma_read_ipcv2(int channel, void *ctrl_ptr) +{ + return iapi_Read_ipcv2(sdma_data[channel].cd, ctrl_ptr); +} + +/*! + * Starts dma channel. + * + * @param channel channel number + */ +int mxc_dma_start(int channel) +{ + if (sdma_data[channel].running == 0) { + sdma_data[channel].running = 1; + iapi_StartChannel(channel); + } + + return 0; +} + +/*! + * Stops dma channel. + * + * @param channel channel number + */ +int mxc_dma_stop(int channel) +{ + iapi_StopChannel(channel); + sdma_data[channel].running = 0; + + return 0; +} + +/*! + * Frees dma channel. + * + * @param channel channel number + */ +void mxc_free_dma(int channel) +{ + int i; + + mxc_dma_stop(channel); + + if (sdma_data[channel].event_id != 0) { + iapi_SetChannelEventMapping(sdma_data[channel].event_id, 0x0); + } + if (sdma_data[channel].event_id2 != 0) { + iapi_SetChannelEventMapping(sdma_data[channel].event_id2, 0x0); + } + + sdma_data[channel].event_id = 0; + + iapi_IoCtl(sdma_data[channel].cd, IAPI_CHANGE_PRIORITY, 0x0); + iapi_IoCtl(sdma_data[channel].cd, IAPI_CHANGE_OWNERSHIP, + (OWN_CHANNEL << CH_OWNSHP_OFFSET_EVT) | + (OWN_CHANNEL << CH_OWNSHP_OFFSET_MCU) | + (OWN_CHANNEL << CH_OWNSHP_OFFSET_DSP)); + + for (i = 0; i < sdma_data[channel].bd_number; i++) { + iapi_IoCtl(sdma_data[channel].cd, + (i << BD_NUM_OFFSET) | + IAPI_CHANGE_SET_STATUS, (unsigned long)0); + } + + iapi_Close(sdma_data[channel].cd); + + strcpy(sdma_data[channel].devicename, "not used"); + + sdma_data[channel].in_use = 0; +} + +/*! + * Initializes channel's priorities + * + */ +static void __init init_priorities(void) +{ + iapi_IoCtl(sdma_data[0].cd, IAPI_CHANGE_PRIORITY, 0x7); +} + +/*! + * Initializes events table + */ +static void __init init_event_table(void) +{ + int channel; + + for (channel = 0; channel < MAX_DMA_CHANNELS; channel++) { + iapi_SetChannelEventMapping(channel, 0); + } +} + +/*! + * Sets callback function. Used with standard dma api + * for supporting interrupts + * + * @param channel channel number + * @param callback callback function pointer + * @param arg argument for callback function + */ +void mxc_dma_set_callback(int channel, dma_callback_t callback, void *arg) +{ + sdma_data[channel].callback = callback; + sdma_data[channel].arg = arg; +} + +/*! + * Synchronization function used by I.API + * + * @param channel channel number + */ +static int getChannel(int channel) +{ + if (irqs_disabled() || in_atomic()) { + if (down_trylock(&sdma_synch_mutex[channel])) { + return -EBUSY; + } + } else { + if (down_interruptible(&sdma_synch_mutex[channel])) { + return -EBUSY; + } + } + + return 0; +} + +/*! + * Synchronization function used by I.API + * + * @param channel channel number + */ +static int releaseChannel(int channel) +{ + up(&sdma_synch_mutex[channel]); + return 0; +} + +/*! + * Unmask interrupt function. Used by I.API + * + */ +static void unmask_sdma_interrupt(void) +{ + /* Commented out tp take care of the PREEMPT_RT option + * local_irq_restore(flags); + */ +} + +/*! + * Mask interrupt function. Used by I.API + * + */ +static void mask_sdma_interrupt(void) +{ + /* Commented to take of the PREEMPT_RT option + * local_irq_save(flags); + */ +} + +/*! + * Initializes I.API + */ +static void __init init_iapi_struct(void) +{ + channelDescriptor *cd; + + printk(KERN_INFO "Using SDMA I.API\n"); + + iapi_Malloc = &sdma_malloc; +#ifdef CONFIG_SDMA_IRAM + iapi_iram_Malloc = &sdma_iram_malloc; +#endif /*CONFIG_SDMA_IRAM */ + + iapi_Free = &sdma_free; + iapi_Virt2Phys = (void *(*)(void *))&sdma_virt_to_phys; + iapi_Phys2Virt = (void *(*)(void *))&sdma_phys_to_virt; + iapi_memset = &memset; + iapi_memcpy = &memcpy; + + iapi_GotoSleep = &sdma_sleep_channel; + iapi_WakeUp = &sdma_wakeup_channel; + iapi_InitSleep = &sdma_init_sleep; + iapi_ReleaseChannel = &releaseChannel; + iapi_GetChannel = &getChannel; + + iapi_EnableInterrupts = &unmask_sdma_interrupt; + iapi_DisableInterrupts = &mask_sdma_interrupt; + + cd = kmalloc(sizeof(channelDescriptor), GFP_KERNEL); + + memset(cd, 0, sizeof(channelDescriptor)); + + sdma_data[0].cd = cd; +} + +/*! + * Initializes channel synchronization mutexes + */ +static void __init init_mutexes(void) +{ + int i; + + for (i = 0; i < MAX_DMA_CHANNELS; i++) { + init_MUTEX(&sdma_synch_mutex[i]); + } + + init_MUTEX(&sdma_status_mutex); +} + +/*! + * Channels status read proc file system function + * + * @param buf pointer to the buffer the data shuld be written to. + * @param start pointer to the pointer where the new data is + * written to. + * procedure should update the start pointer to point to + * where in the buffer the data was written. + * @param offset offset from start of the file + * @param count number of bytes to read. + * @param eof pointer to eof flag. sould be set to 1 when + * reaching eof. + * @param data driver specific data pointer. + * + * @return number byte read from the log buffer. + */ +static int proc_read_channels(char *buf, char **start, off_t offset, int count, + int *eof, void *data) +{ + char *log; + char *log_ptr; + char tmp[48]; + int i; + + log = kmalloc(4096, GFP_KERNEL); + memset(log, 0, 4096); + log_ptr = log; + + for (i = 0; i < MAX_DMA_CHANNELS; i++) { + if (sdma_data[i].in_use == 0) { + continue; + } + + memset(tmp, 0, 48); + sprintf(tmp, "Channel %d: %s\n", i, sdma_data[i].devicename); + + strcpy(log_ptr, tmp); + log_ptr += strlen(tmp); + } + + if (offset > strlen(log)) { + *eof = 1; + count = 0; + } else { + if (offset + count > strlen(log)) { + count = strlen(log) - offset; + *eof = 1; + } else { + *eof = 0; + } + + memcpy(buf, log, count); + *start = buf; + kfree(log); + } + + return count; +} + +/*! + * SDMA proc file system read function + */ +static int __init init_proc_fs(void) +{ + struct proc_dir_entry *sdma_proc_dir; + int res; + + res = 0; + + sdma_proc_dir = proc_mkdir("sdma", NULL); + create_proc_read_entry("channels", 0, sdma_proc_dir, + proc_read_channels, NULL); + + if (res < 0) { + printk(KERN_WARNING "Failed create SDMA proc entry\n"); + } + + return res; +} + +/*! + * Initializes SDMA private data + */ +static void __init init_sdma_data(void) +{ + int i; + + memset(sdma_data, 0, sizeof(sdma_struct) * MAX_DMA_CHANNELS); + sdma_data[0].in_use = 1; + strcpy(sdma_data[0].devicename, "MCU"); + + for (i = 0; i < MAX_DMA_CHANNELS; i++) { + sdma_data[i].channel = i; + } +} + +#if defined(CONFIG_MXC_SUPER_GEM) +/*! + * Initialize the Super GEM SDMA channel + * + * @return returns -1 on error, 0 on success. + */ +static int __init init_super_gem(void) +{ + channelDescriptor *cd; + script_data context; + int res = 0; + + res = iapi_Open(sdma_data[0].cd, MXC_DMA_CHANNEL_GEM); + if (res < 0) { + return -1; + } + sdma_data[MXC_DMA_CHANNEL_GEM].in_use = 1; + cd = CHAD(MXC_DMA_CHANNEL_GEM); + memset(&context, 0, sizeof(script_data)); + context.load_address = sdma_script_addrs.mxc_sdma_utra_addr; + context.wml = M3_BASE_ADDRESS; + res = iapi_AssignScript(cd, &context); + if (res < 0) { + iapi_Close(cd); + sdma_data[MXC_DMA_CHANNEL_GEM].in_use = 0; + return -1; + } + res = + iapi_IoCtl(cd, IAPI_CHANGE_OWNERSHIP, + (OWN_CHANNEL << CH_OWNSHP_OFFSET_EVT) | + (DONT_OWN_CHANNEL << CH_OWNSHP_OFFSET_MCU) | + (OWN_CHANNEL << CH_OWNSHP_OFFSET_DSP)); + if (res < 0) { + iapi_Close(cd); + sdma_data[MXC_DMA_CHANNEL_GEM].in_use = 0; + return -1; + } + /* Set EP=1, which is required to start SuperGem script the first time */ + /* This can be done only on the AP side */ + SDMA_H_EVTPEND |= 1 << MXC_DMA_CHANNEL_GEM; + + res = + iapi_SetChannelEventMapping(DMA_REQ_GEM, 1 << MXC_DMA_CHANNEL_GEM); + if (res < 0) { + iapi_Close(cd); + sdma_data[MXC_DMA_CHANNEL_GEM].in_use = 0; + return -1; + } + + return 0; +} +#endif + +/*! + * Initializes dma + */ +int __init sdma_init(void) +{ + int res = 0; + configs_data confreg_data; + + /* Initialize to the default values */ + confreg_data = iapi_ConfigDefaults; + + confreg_data.dspdma = MXC_SDMA_DSPDMA; + /* Set ACR bit */ + mxc_sdma_ahb_clk = clk_get(NULL, "sdma_ahb_clk"); + mxc_sdma_ipg_clk = clk_get(NULL, "sdma_ipg_clk"); + clk_enable(mxc_sdma_ahb_clk); + clk_enable(mxc_sdma_ipg_clk); + if (clk_get_rate(mxc_sdma_ahb_clk) / clk_get_rate(mxc_sdma_ipg_clk) < 2) { + printk(KERN_INFO "Setting SDMA ACR\n"); + confreg_data.acr = 1; + } + + init_sdma_data(); + + init_sdma_pool(); + + res = request_irq(MXC_INT_SDMA, sdma_int_handler, 0, "mxcsdma", 0); + + if (res < 0) { + goto sdma_init_fail; + } + + init_mutexes(); + + init_iapi_struct(); + + mxc_sdma_get_script_info(&sdma_script_addrs); + + res = iapi_Init(sdma_data[0].cd, &confreg_data, + sdma_script_addrs.mxc_sdma_start_addr, + sdma_script_addrs.mxc_sdma_ram_code_size * 2, + sdma_script_addrs.mxc_sdma_ram_code_start_addr); + + if (res < 0) { + free_irq(MXC_INT_SDMA, 0); + goto sdma_init_fail; + } + + init_priorities(); + + init_event_table(); + +#if defined(CONFIG_MXC_SUPER_GEM) + res = init_super_gem(); + if (res < 0) { + free_irq(MXC_INT_SDMA, 0); + goto sdma_init_fail; + } +#endif + + init_proc_fs(); + + printk(KERN_INFO "MXC DMA API initialized\n"); + + clk_disable(mxc_sdma_ahb_clk); + clk_disable(mxc_sdma_ipg_clk); + return res; + + sdma_init_fail: + printk(KERN_ERR "Error 0x%x in sdma_init\n", res); + clk_disable(mxc_sdma_ahb_clk); + clk_disable(mxc_sdma_ipg_clk); + return res; + +} + +arch_initcall(sdma_init); + +EXPORT_SYMBOL(mxc_request_dma); +EXPORT_SYMBOL(mxc_free_dma); +EXPORT_SYMBOL(mxc_dma_setup_channel); +EXPORT_SYMBOL(mxc_dma_set_channel_priority); +EXPORT_SYMBOL(mxc_dma_set_config); +EXPORT_SYMBOL(mxc_dma_get_config); +EXPORT_SYMBOL(mxc_dma_set_bd_intr); +EXPORT_SYMBOL(mxc_dma_get_bd_intr); +EXPORT_SYMBOL(mxc_dma_reset); +EXPORT_SYMBOL(mxc_sdma_write_ipcv2); +EXPORT_SYMBOL(mxc_sdma_read_ipcv2); +EXPORT_SYMBOL(mxc_dma_start); +EXPORT_SYMBOL(mxc_dma_stop); +EXPORT_SYMBOL(sdma_malloc); +EXPORT_SYMBOL(sdma_free); +EXPORT_SYMBOL(mxc_dma_set_callback); +EXPORT_SYMBOL(sdma_virt_to_phys); +EXPORT_SYMBOL(sdma_phys_to_virt); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC Linux SDMA API"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/plat-mxc/sdma/sdma_malloc.c linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/sdma_malloc.c --- linux-2.6.26/arch/arm/plat-mxc/sdma/sdma_malloc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/sdma/sdma_malloc.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,388 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file plat-mxc/sdma/sdma_malloc.c + * @brief This file contains functions for SDMA non-cacheable buffers allocation + * + * SDMA (Smart DMA) is used for transferring data between MCU and peripherals + * + * @ingroup SDMA + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define DEBUG 0 + +#if DEBUG +#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args) +#else +#define DPRINTK(fmt, args...) +#endif + +#ifdef CONFIG_SDMA_IRAM +#define IRAM_VIRT_BASE IRAM_BASE_ADDR_VIRT +#define IRAM_PHYS_BASE IRAM_BASE_ADDR +#if (CONFIG_SDMA_IRAM_SIZE&0x3FF) +#error "IRAM size of SDMA should be multiple of 1Kbytes" +#else +#define IRAM_SDMA_SIZE CONFIG_SDMA_IRAM_SIZE /* 4K */ +#endif +#define IRAM_UNIT_SIZE 512 +#define IRAM_POOL_SIZE (IRAM_SDMA_SIZE/IRAM_UNIT_SIZE) + +#define IS_IRAM_VIRT(x) (((x)IRAM_SDMA_SIZE)?0:1) + +#define IS_IRAM_PHYS(x) (((x)IRAM_SDMA_SIZE)?0:1) +#endif /*CONFIG_SDMA_IRAM */ + +/*! + * Defines SDMA non-cacheable buffers pool + */ +static struct dma_pool *pool; + +#ifdef CONFIG_SDMA_IRAM +typedef struct iram_head_s { + struct list_head list; +} iram_head_t; + +static spinlock_t iram_pool_lock = SPIN_LOCK_UNLOCKED; +static struct list_head iram_free_list; +static unsigned char iram_pool_flag[IRAM_POOL_SIZE]; + +static void sdma_iram_free(void *buf); +#endif /*CONFIG_SDMA_IRAM */ + +/*! + * SDMA memory conversion hashing structure + */ +typedef struct { + struct list_head node; + int use_count; + /*! Virtual address */ + void *virt; + /*! Physical address */ + unsigned long phys; +} virt_phys_struct; + +static struct list_head buf_map; + +/*! + * Defines the size of each buffer in SDMA pool. + * The size must be at least 512 bytes, because + * sdma channel control blocks array size is 512 bytes + */ +#define SDMA_POOL_SIZE 1024 + +/*! + * Adds new buffer structure into conversion hash tables + * + * @param vf SDMA memory conversion hashing structure + * + * @return 1 on success, 0 on fail + */ +static int add_entry(virt_phys_struct * vf) +{ + virt_phys_struct *p; + + vf->phys &= PAGE_MASK; + vf->virt = (void *)((u32) vf->virt & PAGE_MASK); + + list_for_each_entry(p, &buf_map, node) { + if (p->virt == vf->virt) { + p->use_count++; + return 0; + } + } + + p = kmalloc(sizeof(virt_phys_struct), GFP_KERNEL); + if (p == 0) { + return -ENOMEM; + } + + *p = *vf; + p->use_count = 1; + list_add_tail(&p->node, &buf_map); + + DPRINTK("added vaddr 0x%p, paddr 0x%08X to list\n", p->virt, p->phys); + + return 0; +} + +/*! + * Deletes buffer stracture from conversion hash tables + * + * @param buf SDMA memory buffer virtual addr + * + * @return 0 on success, -1 on fail + */ +static int delete_entry(void *buf) +{ + virt_phys_struct *p; + + buf = (void *)((u32) buf & PAGE_MASK); + + list_for_each_entry(p, &buf_map, node) { + if (p->virt == buf) { + p->use_count--; + break; + } + } + + if (p->use_count == 0) { + list_del(&p->node); + kfree(p); + } + + return 0; +} + +/*! + * Virtual to physical address conversion functio + * + * @param buf pointer to virtual address + * + * @return physical address + */ +unsigned long sdma_virt_to_phys(void *buf) +{ + u32 offset = (u32) buf & (~PAGE_MASK); + virt_phys_struct *p; + + DPRINTK("searching for vaddr 0x%p\n", buf); + +#ifdef CONFIG_SDMA_IRAM + if (IS_IRAM_VIRT((unsigned long)buf)) { + if ((unsigned long)buf & (IRAM_UNIT_SIZE - 1)) { + printk(KERN_WARNING "%s buffer offset = %ld\n", + __FUNCTION__, (unsigned long)buf); + } + return (unsigned long)buf + IRAM_PHYS_BASE - IRAM_VIRT_BASE; + } +#endif /*CONFIG_SDMA_IRAM */ + + list_for_each_entry(p, &buf_map, node) { + if ((u32) p->virt == ((u32) buf & PAGE_MASK)) { + return p->phys | offset; + } + } + + if (virt_addr_valid(buf)) { + return virt_to_phys(buf); + } + + printk(KERN_WARNING + "SDMA malloc: could not translate virt address 0x%p\n", buf); + return 0; +} + +/*! + * Physical to virtual address conversion functio + * + * @param buf pointer to physical address + * + * @return virtual address + */ +void *sdma_phys_to_virt(unsigned long buf) +{ + u32 offset = buf & (~PAGE_MASK); + virt_phys_struct *p; + +#ifdef CONFIG_SDMA_IRAM + if (IS_IRAM_PHYS((unsigned long)buf)) { + if (buf & (IRAM_UNIT_SIZE - 1)) { + printk(KERN_WARNING "%s buffer offset = %ld\n", + __FUNCTION__, (unsigned long)buf); + } + return (void *)buf + IRAM_VIRT_BASE - IRAM_PHYS_BASE; + } +#endif /*CONFIG_SDMA_IRAM */ + + list_for_each_entry(p, &buf_map, node) { + if (p->phys == (buf & PAGE_MASK)) { + return (void *)((u32) p->virt | offset); + } + } + + printk(KERN_WARNING + "SDMA malloc: could not translate phys address 0x%lx\n", buf); + return 0; +} + +/*! + * Allocates uncacheable buffer + * + * @param size size of allocated buffer + * @return pointer to buffer + */ +void *sdma_malloc(size_t size) +{ + void *buf; + dma_addr_t dma_addr; + virt_phys_struct vf; + + if (size > SDMA_POOL_SIZE) { + printk(KERN_WARNING + "size in sdma_malloc is more than %d bytes\n", + SDMA_POOL_SIZE); + buf = 0; + } else { + buf = dma_pool_alloc(pool, GFP_KERNEL, &dma_addr); + if (buf > 0) { + vf.virt = buf; + vf.phys = dma_addr; + + if (add_entry(&vf) < 0) { + dma_pool_free(pool, buf, dma_addr); + buf = 0; + } + } + } + + DPRINTK("allocated vaddr 0x%p\n", buf); + return buf; +} + +/*! + * Frees uncacheable buffer + * + * @param buf buffer pointer for deletion + */ +void sdma_free(void *buf) +{ +#ifdef CONFIG_SDMA_IRAM + if (IS_IRAM_VIRT((unsigned long)buf)) { + sdma_iram_free(buf); + return; + } +#endif /*CONFIG_SDMA_IRAM */ + + dma_pool_free(pool, buf, sdma_virt_to_phys(buf)); + delete_entry(buf); +} + +#ifdef CONFIG_SDMA_IRAM +/*! + * Allocates uncacheable buffer from IRAM + */ +void *sdma_iram_malloc(size_t size) +{ + void *buf; + int index = -1; + unsigned long flags; + if (size > IRAM_UNIT_SIZE) { + printk(KERN_WARNING + "size in sdma_iram_malloc is more than %d bytes\n", + IRAM_UNIT_SIZE); + } else { + spin_lock_irqsave(&iram_pool_lock, flags); + if (!list_empty(&iram_free_list)) { + buf = + list_entry(iram_free_list.next, iram_head_t, list); + list_del(iram_free_list.next); + index = + ((unsigned long)buf - + IRAM_VIRT_BASE) / IRAM_UNIT_SIZE; + if (index < 0 || index >= IRAM_POOL_SIZE) { + spin_unlock_irqrestore(&iram_pool_lock, flags); + printk(KERN_ERR "The iram pool has crashed\n"); + return NULL; + } + if (iram_pool_flag[index]) { + spin_unlock_irqrestore(&iram_pool_lock, flags); + printk(KERN_WARNING + "iram block %d already has been allocated \n", + index); + } + iram_pool_flag[index] = 1; + } + spin_unlock_irqrestore(&iram_pool_lock, flags); + if ((unsigned long)buf & (IRAM_UNIT_SIZE - 1)) { + printk(KERN_WARNING + "the start address is not align of %d, buffer offset %ld\n", + IRAM_UNIT_SIZE, (unsigned long)buf); + + buf = (unsigned long)buf & (~(IRAM_UNIT_SIZE - 1)); + } + } + return buf; +} + +/*! + * Free uncacheable buffer into IRAM. + */ +static void sdma_iram_free(void *buf) +{ + iram_head_t *p; + int index; + unsigned long flags; + /* The check of parameter will be done in sdma_free */ + index = ((unsigned long)buf - IRAM_VIRT_BASE) / IRAM_UNIT_SIZE; + spin_lock_irqsave(&iram_pool_lock, flags); + p = (iram_head_t *) ((unsigned long)buf & (~(IRAM_UNIT_SIZE - 1))); + list_add_tail(&(p->list), &iram_free_list); + if (iram_pool_flag[index]) { + iram_pool_flag[index] = 0; + spin_unlock_irqrestore(&iram_pool_lock, flags); + } else { + printk(KERN_WARNING + "Free %p which IRAM block %d is already freed\n", buf, + index); + spin_unlock_irqrestore(&iram_pool_lock, flags); + } +} + +/*! + * Initialized the free list of IRAM. + */ +static void iram_pool_init(void) +{ + int i; + iram_head_t *p; + memset(iram_pool_flag, 0, IRAM_POOL_SIZE); + INIT_LIST_HEAD(&iram_free_list); + for (i = 0; i < IRAM_POOL_SIZE; i++) { + p = (iram_head_t *) (IRAM_VIRT_BASE + i * IRAM_UNIT_SIZE); + list_add_tail(&(p->list), &iram_free_list); + } +} +#endif /*CONFIG_SDMA_IRAM */ + +/*! + * SDMA buffers pool initialization function + */ +void __init init_sdma_pool(void) +{ +#ifdef CONFIG_SDMA_IRAM + iram_pool_init(); +#endif /*CONFIG_SDMA_IRAM */ + + pool = dma_pool_create("SDMA", NULL, SDMA_POOL_SIZE, 0, 0); + + INIT_LIST_HEAD(&buf_map); +} + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC Linux SDMA API"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/plat-mxc/serialxc.c linux-2.6.26-lab126/arch/arm/plat-mxc/serialxc.c --- linux-2.6.26/arch/arm/plat-mxc/serialxc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/serialxc.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,64 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static void usb_serial_init(struct fsl_xcvr_ops *this) +{ +} + +static void usb_serial_uninit(struct fsl_xcvr_ops *this) +{ +} + +static struct fsl_xcvr_ops serial_ops = { + .name = "serial", + .xcvr_type = PORTSC_PTS_SERIAL, + .init = usb_serial_init, + .uninit = usb_serial_uninit, +}; + +extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops); + +static int __init serialxc_init(void) +{ + pr_debug("%s\n", __FUNCTION__); + + fsl_usb_xcvr_register(&serial_ops); + + return 0; +} + +extern void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops); + +static void __exit serialxc_exit(void) +{ + fsl_usb_xcvr_unregister(&serial_ops); +} + +module_init(serialxc_init); +module_exit(serialxc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("serial xcvr driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/plat-mxc/snoop.c linux-2.6.26-lab126/arch/arm/plat-mxc/snoop.c --- linux-2.6.26/arch/arm/plat-mxc/snoop.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/snoop.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,133 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include + +#ifdef M4IF_BASE_ADDR +#define SNOOP_V2 +#define MAX_SNOOP 2 +#define g_snoop_base (IO_ADDRESS(M4IF_BASE_ADDR) + 0x4C) +#elif defined(M3IF_BASE_ADDR) +#define MAX_SNOOP 1 +#define g_snoop_base (IO_ADDRESS(M3IF_BASE_ADDR) + 0x28) +#else +#define MAX_SNOOP 0 +#define g_snoop_base 0 +#endif + +/* M3IF Snooping Configuration Register 0 (M3IFSCFG0) READ/WRITE*/ +#define SBAR(x) (x * 0x14) +/* M3IF Snooping Configuration Register 1 (M3IFSCFG1) READ/WRITE*/ +#define SERL(x) ((x * 0x14) + 0x4) +/* M3IF Snooping Configuration Register 2 (M3IFSCFG2) READ/WRITE*/ +#define SERH(x) ((x * 0x14) + 0x8) +/* M3IF Snooping Status Register 0 (M3IFSSR0) READ/WRITE */ +#define SSRL(x) ((x * 0x14) + 0xC) +/* M3IF Snooping Status Register 1 (M3IFSSR1) */ +#define SSRH(x) ((x * 0x14) + 0x10) + +#if MAX_SNOOP + +int mxc_snoop_set_config(u32 num, unsigned long base, int size) +{ + u32 reg; + uint32_t msb; + uint32_t seg_size; + uint32_t window_size = 0; + int i; + + if (num >= MAX_SNOOP) { + return -EINVAL; + } + + /* Setup M3IF for snooping */ + if (size) { + + if (base == 0) { + return -EINVAL; + } + + msb = fls(size); + if (!(size & ((1UL << msb) - 1))) + msb--; /* Already aligned to power 2 */ + if (msb < 11) + msb = 11; + + window_size = (1UL << msb); + seg_size = window_size / 64; + + msb -= 11; + + reg = base & ~((1UL << msb) - 1); + reg |= msb << 1; + reg |= 1; /* enable snooping */ + reg |= 0x80; /* Set pulse width to default (M4IF only) */ + __raw_writel(reg, g_snoop_base + SBAR(num)); + + reg = 0; + for (i = 0; i < 32; i++) { + if (i * seg_size >= size) + break; + reg |= 1UL << i; + } + __raw_writel(reg, g_snoop_base + SERL(num)); + + reg = 0; + for (i = 32; i < 64; i++) { + if (i * seg_size >= size) + break; + reg |= 1UL << (i - 32); + } + __raw_writel(reg, g_snoop_base + SERH(num)); + + pr_debug + ("Snooping unit # %d enabled: window size = 0x%X, M3IFSCFG0=0x%08X, M3IFSCFG1=0x%08X, M3IFSCFG2=0x%08X\n", + num, window_size, __raw_readl(g_snoop_base + SBAR(num)), + __raw_readl(g_snoop_base + SERL(num)), + __raw_readl(g_snoop_base + SERH(num))); + } else { + __raw_writel(0, g_snoop_base + SBAR(num)); + } + + return window_size; +} + +EXPORT_SYMBOL(mxc_snoop_set_config); + +int mxc_snoop_get_status(u32 num, u32 * statl, u32 * stath) +{ + if (num >= MAX_SNOOP) { + return -EINVAL; + } + + *statl = __raw_readl(g_snoop_base + SSRL(num)); + *stath = __raw_readl(g_snoop_base + SSRH(num)); + /* DPRINTK("status = 0x%08X%08X\n", stat[1], stat[0]); */ + +#ifdef SNOOP_V2 + __raw_writel(*statl, g_snoop_base + SSRL(num)); + __raw_writel(*stath, g_snoop_base + SSRH(num)); +#else + __raw_writel(0x0, g_snoop_base + SSRL(num)); + __raw_writel(0x0, g_snoop_base + SSRH(num)); +#endif + return 0; +} + +EXPORT_SYMBOL(mxc_snoop_get_status); + +#endif /* MAX_SNOOP */ diff -urN linux-2.6.26/arch/arm/plat-mxc/spba.c linux-2.6.26-lab126/arch/arm/plat-mxc/spba.c --- linux-2.6.26/arch/arm/plat-mxc/spba.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/spba.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,133 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include + +/*! + * @file plat-mxc/spba.c + * + * @brief This file contains the SPBA API implementation details. + * + * @ingroup SPBA + */ + +static DEFINE_SPINLOCK(spba_lock); + +#define SPBA_MASTER_MIN 1 +#define SPBA_MASTER_MAX 7 + +/*! + * the base addresses for the SPBA modules + */ +static unsigned long spba_base = (unsigned long)IO_ADDRESS(SPBA_CTRL_BASE_ADDR); + +/*! + * SPBA clock + */ +static struct clk *spba_clk; +/*! + * This function allows the three masters (A, B, C) to take ownership of a + * shared peripheral. + * + * @param mod specified module as defined in \b enum \b #spba_module + * @param master one of more (or-ed together) masters as defined in \b enum \b #spba_masters + * + * @return 0 if successful; -1 otherwise. + */ +int spba_take_ownership(int mod, int master) +{ + unsigned long spba_flags; + __u32 rtn_val = -1; + + if (master < SPBA_MASTER_MIN || master > SPBA_MASTER_MAX) { + printk("spba_take_ownership() invalide master= %d\n", master); + BUG(); /* oops */ + } + + if (spba_clk == NULL) + spba_clk = clk_get(NULL, "spba_clk"); + + clk_enable(spba_clk); + + spin_lock_irqsave(&spba_lock, spba_flags); + __raw_writel(master, spba_base + mod); + + if ((__raw_readl(spba_base + mod) & MXC_SPBA_RAR_MASK) == master) { + rtn_val = 0; + } + + spin_unlock_irqrestore(&spba_lock, spba_flags); + + clk_disable(spba_clk); + return rtn_val; +} + +/*! + * This function releases the ownership for a shared peripheral. + * + * @param mod specified module as defined in \b enum \b #spba_module + * @param master one of more (or-ed together) masters as defined in \b enum \b #spba_masters + * + * @return 0 if successful; -1 otherwise. + */ +int spba_rel_ownership(int mod, int master) +{ + unsigned long spba_flags; + volatile unsigned long rar; + + if (master < SPBA_MASTER_MIN || master > SPBA_MASTER_MAX) { + printk("spba_take_ownership() invalide master= %d\n", master); + BUG(); /* oops */ + } + + if (spba_clk == NULL) + spba_clk = clk_get(NULL, "spba_clk"); + + clk_enable(spba_clk); + + if ((__raw_readl(spba_base + mod) & master) == 0) { + clk_disable(spba_clk); + return 0; /* does not own it */ + } + + spin_lock_irqsave(&spba_lock, spba_flags); + + /* Since only the last 3 bits are writeable, doesn't need to mask off + bits 31-3 */ + rar = __raw_readl(spba_base + mod) & (~master); + __raw_writel(rar, spba_base + mod); + + if ((__raw_readl(spba_base + mod) & master) != 0) { + spin_unlock_irqrestore(&spba_lock, spba_flags); + clk_disable(spba_clk); + return -1; + } + + spin_unlock_irqrestore(&spba_lock, spba_flags); + + clk_disable(spba_clk); + + return 0; +} + +EXPORT_SYMBOL(spba_take_ownership); +EXPORT_SYMBOL(spba_rel_ownership); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("SPBA"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/plat-mxc/time.c linux-2.6.26-lab126/arch/arm/plat-mxc/time.c --- linux-2.6.26/arch/arm/plat-mxc/time.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/time.c 2010-08-11 00:35:00.000000000 -0400 @@ -0,0 +1,265 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* System Timer Interrupt reconfigured to run in free-run mode. + * Author: Vitaly Wool + * Copyright 2004 MontaVista Software Inc. + */ + +/*! + * @defgroup Timers OS Tick Timer + */ +/*! + * @file plat-mxc/time.c + * @brief This file contains OS tick timer implementation. + * + * This file contains OS tick timer implementation. + * + * @ingroup Timers + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*! + * GPT register address definitions + */ +#define GPT_BASE_ADDR (IO_ADDRESS(GPT1_BASE_ADDR)) +#define MXC_GPT_GPTCR (GPT_BASE_ADDR + 0x00) +#define MXC_GPT_GPTPR (GPT_BASE_ADDR + 0x04) +#define MXC_GPT_GPTSR (GPT_BASE_ADDR + 0x08) +#define MXC_GPT_GPTIR (GPT_BASE_ADDR + 0x0C) +#define MXC_GPT_GPTOCR1 (GPT_BASE_ADDR + 0x10) +#define MXC_GPT_GPTOCR2 (GPT_BASE_ADDR + 0x14) +#define MXC_GPT_GPTOCR3 (GPT_BASE_ADDR + 0x18) +#define MXC_GPT_GPTICR1 (GPT_BASE_ADDR + 0x1C) +#define MXC_GPT_GPTICR2 (GPT_BASE_ADDR + 0x20) +#define MXC_GPT_GPTCNT (GPT_BASE_ADDR + 0x24) + +/*! + * GPT Control register bit definitions + */ +#define GPTCR_FO3 (1 << 31) +#define GPTCR_FO2 (1 << 30) +#define GPTCR_FO1 (1 << 29) + +#define GPTCR_SWR (1 << 15) +#define GPTCR_FRR (1 << 9) + +#define GPTCR_CLKSRC_SHIFT 6 +#define GPTCR_CLKSRC_MASK (7 << GPTCR_CLKSRC_SHIFT) +#define GPTCR_CLKSRC_NOCLOCK (0 << GPTCR_CLKSRC_SHIFT) +#define GPTCR_CLKSRC_HIGHFREQ (2 << GPTCR_CLKSRC_SHIFT) +#define GPTCR_CLKSRC_CLKIN (3 << GPTCR_CLKSRC_SHIFT) +#define GPTCR_CLKSRC_CLK32K (4 << GPTCR_CLKSRC_SHIFT) + +#define GPTCR_STOPEN (1 << 5) +#define GPTCR_DOZEN (1 << 4) +#define GPTCR_WAITEN (1 << 3) +#define GPTCR_DBGEN (1 << 2) +#define GPTCR_ENMOD (1 << 1) +#define GPTCR_ENABLE (1 << 0) + +#define GPTSR_OF1 (1 << 0) +#define GPTSR_OF2 (1 << 1) +#define GPTSR_OF3 (1 << 2) +#define GPTSR_IF1 (1 << 3) +#define GPTSR_IF2 (1 << 4) +#define GPTSR_ROV (1 << 5) + +#define GPTIR_OF1IE GPTSR_OF1 +#define GPTIR_OF2IE GPTSR_OF2 +#define GPTIR_OF3IE GPTSR_OF3 +#define GPTIR_IF1IE GPTSR_IF1 +#define GPTIR_IF2IE GPTSR_IF2 +#define GPTIR_ROVIE GPTSR_ROV + +extern unsigned long clk_early_get_timer_rate(void); + +static int mxc_gpt_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + unsigned long flags, expires, now; + + raw_local_irq_save(flags); + + now = __raw_readl(MXC_GPT_GPTCNT); + expires = now + cycles; + __raw_writel(expires, MXC_GPT_GPTOCR1); + + raw_local_irq_restore(flags); + + return 0; +} + +static void mxc_gpt_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + u32 reg; + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + panic("MXC GPT: CLOCK_EVT_MODE_PERIODIC not supported\n"); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* enable interrupt */ + reg = __raw_readl(MXC_GPT_GPTIR); + reg |= GPTIR_OF1IE; + __raw_writel(reg, MXC_GPT_GPTIR); + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + /* Disable interrupts */ + reg = __raw_readl(MXC_GPT_GPTIR); + reg &= ~GPTIR_OF1IE; + __raw_writel(reg, MXC_GPT_GPTIR); + break; + case CLOCK_EVT_MODE_RESUME: + break; + } +} + +static struct clock_event_device gpt_clockevent = { + .name = "mxc_gpt", + .features = CLOCK_EVT_FEAT_ONESHOT, + .rating = 300, + .shift = 32, + .set_next_event = mxc_gpt_set_next_event, + .set_mode = mxc_gpt_set_mode, +}; + +extern void mxc_kick_wd(void); + +/*! + * This is the timer interrupt service routine to do required tasks. + * It also services the WDOG timer at the frequency of twice per WDOG + * timeout value. For example, if the WDOG's timeout value is 4 (2 + * seconds since the WDOG runs at 0.5Hz), it will be serviced once + * every 2/2=1 second. + * + * @param irq GPT interrupt source number (not used) + * @param dev_id this parameter is not used + * @return always returns \b IRQ_HANDLED as defined in + * include/linux/interrupt.h. + */ +static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) +{ + unsigned int gptsr; + + gptsr = __raw_readl(MXC_GPT_GPTSR); + if (gptsr & GPTSR_OF1) { + /* Clear interrupt */ + __raw_writel(GPTSR_OF1, MXC_GPT_GPTSR); + + gpt_clockevent.event_handler(&gpt_clockevent); + } + + mxc_kick_wd(); + + return IRQ_HANDLED; +} + +/*! + * The clockevents timer interrupt structure. + */ +static struct irqaction timer_irq = { + .name = "gpt-irq", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = mxc_timer_interrupt, +}; + +static cycle_t __xipram mxc_gpt_read(void) +{ + return __raw_readl(MXC_GPT_GPTCNT); +} + +static struct clocksource gpt_clocksrc = { + .name = "mxc_gpt", + .rating = 300, + .read = mxc_gpt_read, + .mask = CLOCKSOURCE_MASK(32), + .shift = 24, + .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_VALID_FOR_HRES, +}; + +/*! + * This function is used to initialize the GPT as a clocksource and clockevent. + * It is called by the start_kernel() during system startup. + */ +void __init mxc_init_time(void) +{ + int ret; + unsigned long rate; + u32 reg, div; + + /* Reset GPT */ + __raw_writel(GPTCR_SWR, MXC_GPT_GPTCR); + while ((__raw_readl(MXC_GPT_GPTCR) & GPTCR_SWR) != 0) + mb(); + + /* Normal clk api are not yet initialized, so use early verion */ + rate = clk_early_get_timer_rate(); + if (rate == 0) + panic("MXC GPT: Can't get timer clock rate\n"); + +#ifdef CLOCK_TICK_RATE + div = rate / CLOCK_TICK_RATE; + WARN_ON((div * CLOCK_TICK_RATE) != rate); +#else /* Hopefully CLOCK_TICK_RATE will go away soon */ + div = 1; + while ((rate / div) > 20000000) { + div++; + } +#endif + rate /= div; + __raw_writel(div - 1, MXC_GPT_GPTPR); + + reg = GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ | GPTCR_STOPEN | + GPTCR_DOZEN | GPTCR_WAITEN | GPTCR_ENMOD | GPTCR_ENABLE; + __raw_writel(reg, MXC_GPT_GPTCR); + + gpt_clocksrc.mult = clocksource_hz2mult(rate, gpt_clocksrc.shift); + ret = clocksource_register(&gpt_clocksrc); + if (ret < 0) { + goto err; + } + + gpt_clockevent.mult = div_sc(rate, NSEC_PER_SEC, gpt_clockevent.shift); + gpt_clockevent.max_delta_ns = clockevent_delta2ns(-1, &gpt_clockevent); + gpt_clockevent.min_delta_ns = clockevent_delta2ns(1, &gpt_clockevent); + + gpt_clockevent.cpumask = cpumask_of_cpu(0); + clockevents_register_device(&gpt_clockevent); + + ret = setup_irq(MXC_INT_GPT, &timer_irq); + if (ret < 0) { + goto err; + } + + pr_info("MXC GPT timer initialized, rate = %lu\n", rate); + return; + err: + panic("Unable to initialize timer\n"); +} + +struct sys_timer mxc_timer = { + .init = mxc_init_time, +}; diff -urN linux-2.6.26/arch/arm/plat-mxc/tzic.c linux-2.6.26-lab126/arch/arm/plat-mxc/tzic.c --- linux-2.6.26/arch/arm/plat-mxc/tzic.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/tzic.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,179 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + ***************************************** + * TZIC Registers * + ***************************************** + */ +#define TZIC_BASE IO_ADDRESS(TZIC_BASE_ADDR) +#define TZIC_INTCNTL (TZIC_BASE + 0x0000) /* control register */ +#define TZIC_INTTYPE (TZIC_BASE + 0x0004) /* Controller type register */ +#define TZIC_IMPID (TZIC_BASE + 0x0008) /* Distributor Implementer Identification Register */ +#define TZIC_PRIOMASK (TZIC_BASE + 0x000C) /* Priority Mask Reg */ +#define TZIC_SYNCCTRL (TZIC_BASE + 0x0010) /* Synchronizer Control register */ +#define TZIC_DSMINT (TZIC_BASE + 0x0014) /* DSM interrupt Holdoffregister */ +#define TZIC_INTSEC0 (TZIC_BASE + 0x0080) /* interrupt security register 0 */ +#define TZIC_ENSET0 (TZIC_BASE + 0x0100) /* Enable Set Register 0 */ +#define TZIC_ENCLEAR0 (TZIC_BASE + 0x0180) /* Enable Clear Register 0 */ +#define TZIC_SRCSET0 (TZIC_BASE + 0x0200) /* Source Set Register 0 */ +#define TZIC_SRCCLAR0 (TZIC_BASE + 0x0280) /* Source Clear Register 0 */ +#define TZIC_PRIORITY0 (TZIC_BASE + 0x0400) /* Priority Register 0 */ +#define TZIC_PND0 (TZIC_BASE + 0x0D00) /* Pending Register 0 */ +#define TZIC_HIPND0 (TZIC_BASE + 0x0D80) /* High Priority Pending Register */ +#define TZIC_WAKEUP0 (TZIC_BASE + 0x0E00) /* Wakeup Config Register */ +#define TZIC_SWINT (TZIC_BASE + 0x0F00) /* Software Interrupt Rigger Register */ +#define TZIC_ID0 (TZIC_BASE + 0x0FD0) /* Indentification Register 0 */ + +/*! + * Disable interrupt number "irq" in the TZIC + * + * @param irq interrupt source number + */ +static void mxc_mask_irq(unsigned int irq) +{ + int index, off; + + index = irq >> 5; + off = irq & 0x1F; + __raw_writel(1 << off, TZIC_ENCLEAR0 + (index << 2)); +} + +/*! + * Enable interrupt number "irq" in the TZIC + * + * @param irq interrupt source number + */ +static void mxc_unmask_irq(unsigned int irq) +{ + int index, off; + + index = irq >> 5; + off = irq & 0x1F; + __raw_writel(1 << off, TZIC_ENSET0 + (index << 2)); +} + +static unsigned int wakeup_intr[4]; + +/*! + * Set interrupt number "irq" in the TZIC as a wake-up source. + * + * @param irq interrupt source number + * @param enable enable as wake-up if equal to non-zero + * disble as wake-up if equal to zero + * + * @return This function returns 0 on success. + */ +static int mxc_set_wake_irq(unsigned int irq, unsigned int enable) +{ + unsigned int index, off; + + index = irq >> 5; + off = irq & 0x1F; + + if (index > 3) + return -1; + + if (enable) + wakeup_intr[index] |= (1 << off); + else + wakeup_intr[index] &= ~(1 << off); + + return 0; +} + +static struct irq_chip mxc_tzic_chip = { + .name = "MXC_TZIC", + .ack = mxc_mask_irq, + .mask = mxc_mask_irq, + .unmask = mxc_unmask_irq, + .set_wake = mxc_set_wake_irq, +}; + +/*! + * This function initializes the TZIC hardware and disables all the + * interrupts. It registers the interrupt enable and disable functions + * to the kernel for each interrupt source. + */ +void __init mxc_init_irq(void) +{ + int i; + + /* put the TZIC into the reset value with + * all interrupts disabled + */ + i = __raw_readl(TZIC_INTCNTL); + + __raw_writel(0x80010001, TZIC_INTCNTL); + i = __raw_readl(TZIC_INTCNTL); + __raw_writel(0x1f, TZIC_PRIOMASK); + i = __raw_readl(TZIC_PRIOMASK); + __raw_writel(0x02, TZIC_SYNCCTRL); + i = __raw_readl(TZIC_SYNCCTRL); + for (i = 0; i < 4; i++) { + __raw_writel(0xFFFFFFFF, TZIC_INTSEC0 + i * 4); + } + /* disable all interrupts */ + for (i = 0; i < 4; i++) { + __raw_writel(0xFFFFFFFF, TZIC_ENCLEAR0 + i * 4); + } + + /* all IRQ no FIQ Warning :: No selection */ + + for (i = 0; i < MXC_MAX_INT_LINES; i++) { + set_irq_chip(i, &mxc_tzic_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + + printk(KERN_INFO "MXC IRQ initialized\n"); +} + +/*! + * enable wakeup interrupt + * + * @param is_idle 1 if called in idle loop (enset registers); + * 0 to be used when called from low power entry + * @return 0 if successful; non-zero otherwise + */ +int tzic_enable_wake(int is_idle) +{ + unsigned int i, v; + + __raw_writel(1, TZIC_DSMINT); + if (unlikely(__raw_readl(TZIC_DSMINT) == 0)) + return -EAGAIN; + + if (likely(is_idle)) { + for (i = 0; i < 4; i++) { + v = __raw_readl(TZIC_ENSET0 + i * 4); + __raw_writel(v, TZIC_WAKEUP0 + i * 4); + } + } else { + for (i = 0; i < 4; i++) { + v = wakeup_intr[i]; + __raw_writel(v, TZIC_WAKEUP0 + i * 4); + } + } + return 0; +} diff -urN linux-2.6.26/arch/arm/plat-mxc/usb_common.c linux-2.6.26-lab126/arch/arm/plat-mxc/usb_common.c --- linux-2.6.26/arch/arm/plat-mxc/usb_common.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/usb_common.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,867 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * otg_{get,set}_transceiver() are from arm/plat-omap/usb.c. + * which is Copyright (C) 2004 Texas Instruments, Inc. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + *@defgroup USB ARC OTG USB Driver + */ + +/*! + * @file usb_common.c + * + * @brief platform related part of usb driver. + * @ingroup USB + */ + +/*! + *Include files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MXC_NUMBER_USB_TRANSCEIVER 6 +struct fsl_xcvr_ops *g_xc_ops[MXC_NUMBER_USB_TRANSCEIVER] = { NULL }; + +static struct clk *usb_clk; +static struct clk *usb_ahb_clk; + +extern int gpio_usbotg_hs_active(void); +extern int gpio_usbotg_hs_inactive(void); + +/* + * make sure USB_CLK is running at 60 MHz +/- 1000 Hz + */ +static int fsl_check_usbclk(void) +{ + unsigned long freq; + + usb_ahb_clk = clk_get(NULL, "usb_ahb_clk"); + if (clk_enable(usb_ahb_clk)) { + printk(KERN_ERR "clk_enable(usb_ahb_clk) failed\n"); + return -EINVAL; + } + clk_put(usb_ahb_clk); + + usb_clk = clk_get(NULL, "usb_clk"); + freq = clk_get_rate(usb_clk); + clk_put(usb_clk); + if ((freq < 59999000) || (freq > 60001000)) { + printk(KERN_ERR "USB_CLK=%lu, should be 60MHz\n", freq); + return -1; + } + + return 0; +} + +void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops) +{ + int i; + + pr_debug("%s\n", __func__); + for (i = 0; i < MXC_NUMBER_USB_TRANSCEIVER; i++) { + if (g_xc_ops[i] == NULL) { + g_xc_ops[i] = xcvr_ops; + return; + } + } + + pr_debug("Failed %s\n", __func__); +} +EXPORT_SYMBOL(fsl_usb_xcvr_register); + +void fsl_platform_set_test_mode (struct fsl_usb2_platform_data *pdata, enum usb_test_mode mode) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->set_test_mode) + pdata->xcvr_ops->set_test_mode((u32 *)(pdata->regs + ULPIVW_OFF), mode); +} +EXPORT_SYMBOL(fsl_platform_set_test_mode); + +void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops) +{ + int i; + + pr_debug("%s\n", __func__); + for (i = 0; i < MXC_NUMBER_USB_TRANSCEIVER; i++) { + if (g_xc_ops[i] == xcvr_ops) { + g_xc_ops[i] = NULL; + return; + } + } + + pr_debug("Failed %s\n", __func__); +} +EXPORT_SYMBOL(fsl_usb_xcvr_unregister); + +static struct fsl_xcvr_ops *fsl_usb_get_xcvr(char *name) +{ + int i; + + pr_debug("%s\n", __func__); + if (name == NULL) { + printk(KERN_ERR "get_xcvr(): No tranceiver name\n"); + return NULL; + } + + for (i = 0; i < MXC_NUMBER_USB_TRANSCEIVER; i++) { + if (strcmp(g_xc_ops[i]->name, name) == 0) { + return g_xc_ops[i]; + } + } + pr_debug("Failed %s\n", __func__); + return NULL; +} + +/* The dmamask must be set for EHCI to work */ +static u64 ehci_dmamask = ~(u32) 0; + +/*! + * Register an instance of a USB host platform device. + * + * @param res: resource pointer + * @param n_res: number of resources + * @param config: config pointer + * + * @return newly-registered platform_device + * + * The USB controller supports 3 host interfaces, and the + * kernel can be configured to support some number of them. + * Each supported host interface is registered as an instance + * of the "fsl-ehci" device. Call this function multiple times + * to register each host interface. + */ +static int instance_id = 0; +struct platform_device *host_pdev_register(struct resource *res, int n_res, + struct fsl_usb2_platform_data *config) +{ + struct platform_device *pdev; + int rc; + + pr_debug("register host res=0x%p, size=%d\n", res, n_res); + + pdev = platform_device_register_simple("fsl-ehci", + instance_id, res, n_res); + if (IS_ERR(pdev)) { + pr_debug("can't register %s Host, %ld\n", + config->name, PTR_ERR(pdev)); + return NULL; + } + + pdev->dev.coherent_dma_mask = 0xffffffff; + pdev->dev.dma_mask = &ehci_dmamask; + + /* + * platform_device_add_data() makes a copy of + * the platform_data passed in. That makes it + * impossible to share the same config struct for + * all OTG devices (host,gadget,otg). So, just + * set the platorm_data pointer ourselves. + */ + rc = platform_device_add_data(pdev, config, + sizeof(struct fsl_usb2_platform_data)); + if (rc) { + platform_device_unregister(pdev); + return NULL; + } + + printk(KERN_INFO "usb: %s host (%s) registered\n", config->name, + config->transceiver); + pr_debug("pdev=0x%p dev=0x%p resources=0x%p pdata=0x%p\n", + pdev, &pdev->dev, pdev->resource, pdev->dev.platform_data); + + instance_id++; + + return pdev; +} + +/* DDD looks like this is needed by Belcarra code */ +void fsl_platform_set_vbus_power(struct fsl_usb2_platform_data *pdata, int on) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->set_vbus_power) + pdata->xcvr_ops->set_vbus_power(pdata->xcvr_ops, pdata, on); +} +EXPORT_SYMBOL(fsl_platform_set_vbus_power); + +/* DDD looks like this is needed by Belcarra code */ +void fsl_platform_perform_remote_wakeup(struct fsl_usb2_platform_data *pdata) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->set_remote_wakeup) + pdata->xcvr_ops->set_remote_wakeup( + (u32 *)(pdata->regs + ULPIVW_OFF)); +} +EXPORT_SYMBOL(fsl_platform_perform_remote_wakeup); + +#if defined(CONFIG_USB_OTG) +static struct otg_transceiver *xceiv; + +/** + * otg_get_transceiver - find the (single) OTG transceiver driver + * + * Returns the transceiver driver, after getting a refcount to it; or + * null if there is no such transceiver. The caller is responsible for + * releasing that count. + */ +struct otg_transceiver *otg_get_transceiver(void) +{ + pr_debug("%s xceiv=0x%p\n", __func__, xceiv); + if (xceiv) + get_device(xceiv->dev); + return xceiv; +} +EXPORT_SYMBOL(otg_get_transceiver); + +int otg_set_transceiver(struct otg_transceiver *x) +{ + pr_debug("%s xceiv=0x%p x=0x%p\n", __func__, xceiv, x); + if (xceiv && x) + return -EBUSY; + xceiv = x; + return 0; +} +EXPORT_SYMBOL(otg_set_transceiver); + +static struct resource *otg_resources; + +struct resource *otg_get_resources(void) +{ + return otg_resources; +} +EXPORT_SYMBOL(otg_get_resources); + +int otg_set_resources(struct resource *resources) +{ + otg_resources = resources; + return 0; +} +EXPORT_SYMBOL(otg_set_resources); +#endif + +static void usbh1_set_serial_xcvr(void) +{ + pr_debug("%s: \n", __func__); + USBCTRL &= ~(UCTRL_H1SIC_MASK | UCTRL_BPE); /* disable bypass mode */ + USBCTRL |= UCTRL_H1SIC_SU6 | /* single-ended / unidir. */ + UCTRL_H1WIE | UCTRL_H1DT | /* disable H1 TLL */ + UCTRL_H1PM; /* power mask */ +} + +static void usbh1_set_ulpi_xcvr(void) +{ + pr_debug("%s: \n", __func__); + + /* Stop then Reset */ + UH1_USBCMD &= ~UCMD_RUN_STOP; + while (UH1_USBCMD & UCMD_RUN_STOP) ; + + UH1_USBCMD |= UCMD_RESET; + while (UH1_USBCMD & UCMD_RESET) ; + + /* Select the clock from external PHY */ + USB_CTRL_1 |= USB_CTRL_UH1_EXT_CLK_EN; + + /* select ULPI PHY PTS=2 */ + UH1_PORTSC1 = (UH1_PORTSC1 & ~PORTSC_PTS_MASK) | PORTSC_PTS_ULPI; + + USBCTRL |= UCTRL_H1WIE; /* HOST1 wakeup intr enable */ + USBCTRL |= UCTRL_H1UIE; /* Host1 ULPI interrupt enable */ + USBCTRL &= ~UCTRL_H1PM; /* HOST1 power mask */ + + /* Interrupt Threshold Control:Immediate (no threshold) */ + UH1_USBCMD &= UCMD_ITC_NO_THRESHOLD; + + UH1_USBCMD |= UCMD_RESET; /* reset the controller */ + + /* allow controller to reset, and leave time for + * the ULPI transceiver to reset too. + */ + msleep(100); + + /* Turn off the usbpll for ulpi tranceivers */ + clk_disable(usb_clk); +} +static void usbh2_set_ulpi_xcvr(void) +{ + u32 tmp; + + pr_debug("%s\n", __func__); + USBCTRL &= ~(UCTRL_H2SIC_MASK | UCTRL_BPE); + USBCTRL |= UCTRL_H2WIE | /* wakeup intr enable */ + UCTRL_H2UIE | /* ULPI intr enable */ + UCTRL_H2DT | /* disable H2 TLL */ + UCTRL_H2PM; /* power mask */ + + /* must set ULPI phy before turning off clock */ + tmp = UH2_PORTSC1 & ~PORTSC_PTS_MASK; + tmp |= PORTSC_PTS_ULPI; + UH2_PORTSC1 = tmp; + + UH2_USBCMD |= UCMD_RESET; /* reset the controller */ + + /* allow controller to reset, and leave time for + * the ULPI transceiver to reset too. + */ + msleep(100); + + /* Turn off the usbpll for ulpi tranceivers */ + clk_disable(usb_clk); +} + +static void usbh2_set_serial_xcvr(void) +{ + pr_debug("%s: \n", __func__); + + /* Stop then Reset */ + UH2_USBCMD &= ~UCMD_RUN_STOP; + while (UH2_USBCMD & UCMD_RUN_STOP) ; + + UH2_USBCMD |= UCMD_RESET; + while (UH2_USBCMD & UCMD_RESET) ; + + USBCTRL &= ~(UCTRL_H2SIC_MASK); /* Disable bypass mode */ + USBCTRL |= UCTRL_H2PM | UCTRL_OPM; /* Power Mask */ + USBCTRL &= ~UCTRL_H2OCPOL; /* OverCurrent Polarity is Low Active */ + USBCTRL |= UCTRL_H2WIE | /* Wakeup intr enable */ + UCTRL_IP_PUE_DOWN | /* ipp_pue_pulldwn_dpdm */ + UCTRL_USBTE | /* USBT is enabled */ + UCTRL_H2DT; /* Disable H2 TLL */ + + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 0) { + /* Disable Host2 bus Lock for i.MX35 1.0 */ + USBCTRL |= UCTRL_H2LOCKD; + /* USBOTG_PWR low active */ + USBCTRL &= ~UCTRL_PP; + /* OverCurrent Polarity is Low Active */ + USBCTRL &= ~UCTRL_OCPOL; + } else if (cpu_is_mx35_rev(CHIP_REV_2_0) >= 1) { + /* i.MX35 2.0 OTG and Host2 have seperate OC/PWR polarity */ + USBCTRL &= ~UCTRL_H2PP; + USBCTRL &= ~UCTRL_H2OCPOL; + } else if (cpu_is_mx25()) { + /* + * USBH2_PWR and USBH2_OC are active high. + * Must force xcvr clock to "internal" so that + * we can write to PTS field after it's been + * cleared by ehci_turn_off_all_ports(). + */ + USBCTRL |= UCTRL_H2PP | UCTRL_H2OCPOL | UCTRL_XCSH2; + /* Disable Host2 bus Lock */ + USBCTRL |= UCTRL_H2LOCKD; + } + + USBCTRL &= ~(UCTRL_PP); + UH2_PORTSC1 = (UH2_PORTSC1 & (~PORTSC_PTS_MASK)) | PORTSC_PTS_SERIAL; + + if (UH2_HCSPARAMS & HCSPARAMS_PPC) + UH2_PORTSC1 |= PORTSC_PORT_POWER; + + /* Reset controller before set host mode */ + UH2_USBCMD |= UCMD_RESET; + while (UH2_USBCMD & UCMD_RESET) ; + + msleep(100); +} + +/*! + * Register remote wakeup by this usb controller + * + * @param pdev: platform_device for this usb controller + * + * @return 0 or negative error code in case not supportted. + */ +static int usb_register_remote_wakeup(struct platform_device *pdev) +{ + pr_debug("%s: pdev=0x%p \n", __func__, pdev); + + if (device_may_wakeup(&pdev->dev)) { + struct resource *res; + int irq; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_err(&pdev->dev, + "Found HC with no IRQ. Check %s setup!\n", + pdev->dev.bus_id); + return -ENODEV; + } + irq = res->start; + enable_irq_wake(irq); + + return 0; + } + + return -EINVAL; +} + +extern void gpio_usbh1_setback_stp(void); +extern void gpio_usbh2_setback_stp(void); + +int fsl_usb_host_init(struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + struct fsl_xcvr_ops *xops; + + pr_debug("%s: pdev=0x%p pdata=0x%p\n", __func__, pdev, pdata); + + xops = fsl_usb_get_xcvr(pdata->transceiver); + if (!xops) { + printk(KERN_ERR "%s transceiver ops missing\n", pdata->name); + return -EINVAL; + } + pdata->xcvr_ops = xops; + pdata->xcvr_type = xops->xcvr_type; + pdata->pdev = pdev; + + if (fsl_check_usbclk() != 0) + return -EINVAL; + + pr_debug("%s: grab pins\n", __func__); + if (pdata->gpio_usb_active()) + return -EINVAL; + + if (clk_enable(usb_clk)) { + printk(KERN_ERR "clk_enable(usb_clk) failed\n"); + return -EINVAL; + } + + if (cpu_is_mx51()) { + usb_clk = clk_get(NULL, "usboh3_clk"); + clk_enable(usb_clk); + clk_put(usb_clk); + } + + /* enable board power supply for xcvr */ + if (pdata->xcvr_pwr) { + if (pdata->xcvr_pwr->regu1) + regulator_enable(pdata->xcvr_pwr->regu1); + if (pdata->xcvr_pwr->regu2) + regulator_enable(pdata->xcvr_pwr->regu2); + } + + if (xops->init) + xops->init(xops); + + if (usb_register_remote_wakeup(pdev)) + pr_debug("Host is not a wakeup source.\n"); + + if (xops->xcvr_type == PORTSC_PTS_SERIAL) { + if (cpu_is_mx35()) { + usbh2_set_serial_xcvr(); + /* Close the internal 60Mhz */ + USBCTRL &= ~UCTRL_XCSH2; + } else if (cpu_is_mx25()) + usbh2_set_serial_xcvr(); + else + usbh1_set_serial_xcvr(); + } else if (xops->xcvr_type == PORTSC_PTS_ULPI) { + if (cpu_is_mx51()) { +#ifdef CONFIG_USB_EHCI_ARC_H1 + if (pdata->name == "Host 1") { + usbh1_set_ulpi_xcvr(); + if (cpu_is_mx51()) + gpio_usbh1_setback_stp(); + } +#endif +#ifdef CONFIG_USB_EHCI_ARC_H2 + if (pdata->name == "Host 2") { + usbh2_set_ulpi_xcvr(); + if (cpu_is_mx51()) + gpio_usbh2_setback_stp(); + } +#endif + } else + usbh2_set_ulpi_xcvr(); + } + + if (pdata->name == "Host 2") + /* disable remote wakeup irq */ + USBCTRL &= ~UCTRL_H2WIE; + + pr_debug("%s: %s success\n", __func__, pdata->name); + return 0; +} +EXPORT_SYMBOL(fsl_usb_host_init); + +void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata) +{ + pr_debug("%s\n", __func__); + + if (pdata->xcvr_ops && pdata->xcvr_ops->uninit) + pdata->xcvr_ops->uninit(pdata->xcvr_ops); + + pdata->regs = NULL; + + pdata->gpio_usb_inactive(); + if (pdata->xcvr_type == PORTSC_PTS_SERIAL) { + /* Workaround an IC issue for 2.6.26 kernal: + * when turn off root hub port power, EHCI set + * PORTSC reserved bits to be 0, but PTS with 0 + * means UTMI interface, so here force the Host2 + * port use the internal 60Mhz. + */ + if (cpu_is_mx35()) + USBCTRL |= UCTRL_XCSH2; + clk_disable(usb_clk); + } + + /* disable board power supply for xcvr */ + if (pdata->xcvr_pwr) { + if (pdata->xcvr_pwr->regu1) + regulator_disable(pdata->xcvr_pwr->regu1); + if (pdata->xcvr_pwr->regu2) + regulator_disable(pdata->xcvr_pwr->regu2); + } + + if (cpu_is_mx51()) { + usb_clk = clk_get(NULL, "usboh3_clk"); + clk_disable(usb_clk); + clk_put(usb_clk); + } + + clk_disable(usb_ahb_clk); +} +EXPORT_SYMBOL(fsl_usb_host_uninit); + +static void otg_set_serial_xcvr(void) +{ + pr_debug("%s\n", __func__); +} + +void otg_set_serial_host(void) +{ + pr_debug("%s\n", __func__); + /* set USBCTRL for host operation + * disable: bypass mode, + * set: single-ended/unidir/6 wire, OTG wakeup intr enable, + * power mask + */ + USBCTRL &= ~UCTRL_OSIC_MASK; +#if defined(CONFIG_ARCH_MX27) || defined(CONFIG_ARCH_MX3) + USBCTRL &= ~UCTRL_BPE; +#endif + +#if defined(CONFIG_MXC_USB_SB3) + USBCTRL |= UCTRL_OSIC_SB3 | UCTRL_OWIE | UCTRL_OPM; +#elif defined(CONFIG_MXC_USB_SU6) + USBCTRL |= UCTRL_OSIC_SU6 | UCTRL_OWIE | UCTRL_OPM; +#elif defined(CONFIG_MXC_USB_DB4) + USBCTRL |= UCTRL_OSIC_DB4 | UCTRL_OWIE | UCTRL_OPM; +#else + USBCTRL |= UCTRL_OSIC_DU6 | UCTRL_OWIE | UCTRL_OPM; +#endif + + USB_OTG_MIRROR = OTGM_VBUSVAL | OTGM_ASESVLD; /* 0xa */ +} +EXPORT_SYMBOL(otg_set_serial_host); + +void otg_set_serial_peripheral(void) +{ + /* set USBCTRL for device operation + * disable: bypass mode + * set: differential/unidir/6 wire, OTG wakeup intr enable, + * power mask + */ + USBCTRL &= ~UCTRL_OSIC_MASK; +#if defined(CONFIG_ARCH_MX27) || defined(CONFIG_ARCH_MX3) + USBCTRL &= ~UCTRL_BPE; +#endif + +#if defined(CONFIG_MXC_USB_SB3) + USBCTRL |= UCTRL_OSIC_SB3 | UCTRL_OWIE | UCTRL_OPM; +#elif defined(CONFIG_MXC_USB_SU6) + USBCTRL |= UCTRL_OSIC_SU6 | UCTRL_OWIE | UCTRL_OPM; +#elif defined(CONFIG_MXC_USB_DB4) + USBCTRL |= UCTRL_OSIC_DB4 | UCTRL_OWIE | UCTRL_OPM; +#else + USBCTRL |= UCTRL_OSIC_DU6 | UCTRL_OWIE | UCTRL_OPM; +#endif + + USB_OTG_MIRROR = OTGM_VBUSVAL | OTGM_BSESVLD | OTGM_IDIDG; /* oxd */ +} +EXPORT_SYMBOL(otg_set_serial_peripheral); + +static void otg_set_ulpi_xcvr(void) +{ + u32 tmp; + + pr_debug("%s\n", __func__); + USBCTRL &= ~UCTRL_OSIC_MASK; +#if defined(CONFIG_ARCH_MX27) || defined(CONFIG_ARCH_MX3) + USBCTRL &= ~UCTRL_BPE; +#endif + USBCTRL |= UCTRL_OUIE | /* ULPI intr enable */ + UCTRL_OWIE | /* OTG wakeup intr enable */ + UCTRL_OPM; /* power mask */ + + /* must set ULPI phy before turning off clock */ + tmp = UOG_PORTSC1 & ~PORTSC_PTS_MASK; + tmp |= PORTSC_PTS_ULPI; + UOG_PORTSC1 = tmp; + + /* need to reset the controller here so that the ID pin + * is correctly detected. + */ + UOG_USBCMD |= UCMD_RESET; + + /* allow controller to reset, and leave time for + * the ULPI transceiver to reset too. + */ + msleep(100); + + /* Turn off the usbpll for ulpi tranceivers */ + clk_disable(usb_clk); +} + +int fsl_usb_xcvr_suspend(struct fsl_xcvr_ops *xcvr_ops) +{ + if (!machine_is_mx31_3ds()) + return -ECANCELED; + + if (xcvr_ops->xcvr_type == PORTSC_PTS_ULPI) { + if (fsl_check_usbclk() != 0) + return -EINVAL; + if (gpio_usbotg_hs_active()) + return -EINVAL; + clk_enable(usb_clk); + + otg_set_ulpi_xcvr(); + + if (xcvr_ops->suspend) + /* suspend transceiver */ + xcvr_ops->suspend(xcvr_ops); + + gpio_usbotg_hs_inactive(); + clk_disable(usb_clk); + } + return 0; +} +EXPORT_SYMBOL(fsl_usb_xcvr_suspend); + +static void otg_set_utmi_xcvr(void) +{ + u32 tmp; + + /* Stop then Reset */ + UOG_USBCMD &= ~UCMD_RUN_STOP; + while (UOG_USBCMD & UCMD_RUN_STOP) ; + + UOG_USBCMD |= UCMD_RESET; + while ((UOG_USBCMD) & (UCMD_RESET)) ; + + if (cpu_is_mx51()) { + /* OTG Polarity of Overcurrent is Low active */ + USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_POL; + /* Enable OTG Overcurrent Event */ + USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_OC_DIS; + } else if (cpu_is_mx25()) { + USBCTRL |= UCTRL_OCPOL; + USBCTRL &= ~UCTRL_PP; + } else { + /* USBOTG_PWR low active */ + USBCTRL &= ~UCTRL_PP; + /* OverCurrent Polarity is Low Active */ + USBCTRL &= ~UCTRL_OCPOL; + + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 0) + /* OTG Lock Disable */ + USBCTRL |= UCTRL_OLOCKD; + } + + USBCTRL |= UCTRL_OPM; /* OTG Power Mask */ +#ifndef CONFIG_MACH_LUIGI_LAB126 + USBCTRL |= UCTRL_OWIE; /* OTG Wakeup Intr Enable */ +#endif + + /* set UTMI xcvr */ + tmp = UOG_PORTSC1 & ~PORTSC_PTS_MASK; + tmp |= PORTSC_PTS_UTMI; + UOG_PORTSC1 = tmp; + + if (cpu_is_mx51()) { + /* Set the PHY clock to 19.2MHz */ + USB_PHY_CTR_FUNC2 &= ~USB_UTMI_PHYCTRL2_PLLDIV_MASK; + USB_PHY_CTR_FUNC2 |= 0x01; + } + if (!cpu_is_mx25()) { + /* Workaround an IC issue for 2.6.26 kernal: + * when turn off root hub port power, EHCI set + * PORTSC reserved bits to be 0, but PTW with 0 + * means 8 bits tranceiver width, here change + * it back to be 16 bits and do PHY diable and + * then enable. + */ + UOG_PORTSC1 |= PORTSC_PTW; + + /* Enable UTMI interface in PHY control Reg */ + USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_UTMI_ENABLE; + USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_UTMI_ENABLE; + } + + if (UOG_HCSPARAMS & HCSPARAMS_PPC) + UOG_PORTSC1 |= PORTSC_PORT_POWER; + + /* need to reset the controller here so that the ID pin + * is correctly detected. + */ + /* Stop then Reset */ + UOG_USBCMD &= ~UCMD_RUN_STOP; + while (UOG_USBCMD & UCMD_RUN_STOP) ; + + UOG_USBCMD |= UCMD_RESET; + while ((UOG_USBCMD) & (UCMD_RESET)) ; + + /* allow controller to reset, and leave time for + * the ULPI transceiver to reset too. + */ + msleep(100); + + /* Turn off the usbpll for mx25 UTMI tranceivers */ + /* DDD: can we do this UTMI xcvrs on all boards? */ + if (cpu_is_mx25()) + clk_disable(usb_clk); +} + +static int otg_used = 0; + +int usbotg_init(struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + struct fsl_xcvr_ops *xops; + + pr_debug("%s: pdev=0x%p pdata=0x%p\n", __func__, pdev, pdata); + + xops = fsl_usb_get_xcvr(pdata->transceiver); + if (!xops) { + printk(KERN_ERR "DR transceiver ops missing\n"); + return -EINVAL; + } + pdata->xcvr_ops = xops; + pdata->xcvr_type = xops->xcvr_type; + pdata->pdev = pdev; + + if (!otg_used) { + if (fsl_check_usbclk() != 0) + return -EINVAL; + + pr_debug("%s: grab pins\n", __func__); + if (pdata->gpio_usb_active()) + return -EINVAL; + + if (clk_enable(usb_clk)) { + printk(KERN_ERR "clk_enable(usb_clk) failed\n"); + return -EINVAL; + } + + if (xops->init) + xops->init(xops); + + if (usb_register_remote_wakeup(pdev)) + pr_debug("DR is not a wakeup source.\n"); + + if (xops->xcvr_type == PORTSC_PTS_SERIAL) { + if (pdata->operating_mode == FSL_USB2_DR_HOST) { + otg_set_serial_host(); + /* need reset */ + UOG_USBCMD |= UCMD_RESET; + msleep(100); + } else if (pdata->operating_mode == FSL_USB2_DR_DEVICE) + otg_set_serial_peripheral(); + otg_set_serial_xcvr(); + } else if (xops->xcvr_type == PORTSC_PTS_ULPI) { + otg_set_ulpi_xcvr(); + } else if (xops->xcvr_type == PORTSC_PTS_UTMI) { + otg_set_utmi_xcvr(); + } + + /* disable remote wakeup irq */ + USBCTRL &= ~UCTRL_OWIE; + } + + otg_used++; + pr_debug("%s: success\n", __func__); + return 0; +} +EXPORT_SYMBOL(usbotg_init); + +void usbotg_uninit(struct fsl_usb2_platform_data *pdata) +{ + pr_debug("%s\n", __func__); + + otg_used--; + if (!otg_used) { + if (pdata->xcvr_ops && pdata->xcvr_ops->uninit) + pdata->xcvr_ops->uninit(pdata->xcvr_ops); + + pdata->regs = NULL; + + if (machine_is_mx31_3ds()) { + if (pdata->xcvr_ops && pdata->xcvr_ops->suspend) + pdata->xcvr_ops->suspend(pdata->xcvr_ops); + clk_disable(usb_clk); + } + + pdata->gpio_usb_inactive(); + if (pdata->xcvr_type == PORTSC_PTS_SERIAL) + clk_disable(usb_clk); + } +} +EXPORT_SYMBOL(usbotg_uninit); + +#if defined(CONFIG_USB_EHCI_ARC_H2_WAKE_UP) || \ + defined(CONFIG_USB_EHCI_ARC_OTG_WAKE_UP) +int usb_wakeup_irq(struct device *wkup_dev) +{ + int wakeup_req = 0; + struct fsl_usb2_platform_data *pdata = wkup_dev->platform_data; + + if (pdata->name == "Host 2") + wakeup_req = USBCTRL & UCTRL_H2WIR; + else if (pdata->name == "DR") + wakeup_req = USBCTRL & UCTRL_OWIR; + + return wakeup_req; +} +EXPORT_SYMBOL(usb_wakeup_irq); + +void usb_wakeup_set(struct device *wkup_dev, int para) +{ + struct fsl_usb2_platform_data *pdata = wkup_dev->platform_data; + + if (pdata->name == "Host 2") { + if (para) + USBCTRL |= UCTRL_H2WIE; + else + USBCTRL &= ~UCTRL_H2WIE; + } else if (pdata->name == "DR") { + if (para) + USBCTRL |= UCTRL_OWIE; + else + USBCTRL &= ~UCTRL_OWIE; + } +} +EXPORT_SYMBOL(usb_wakeup_set); +#endif diff -urN linux-2.6.26/arch/arm/plat-mxc/utmixc.c linux-2.6.26-lab126/arch/arm/plat-mxc/utmixc.c --- linux-2.6.26/arch/arm/plat-mxc/utmixc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/utmixc.c 2010-08-10 04:14:11.000000000 -0400 @@ -0,0 +1,120 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static void usb_utmi_init(struct fsl_xcvr_ops *this) +{ +} + +static void usb_utmi_uninit(struct fsl_xcvr_ops *this) +{ +} + +/*! + * set vbus power + * + * @param view viewport register + * @param on power on or off + */ +static void set_power(struct fsl_xcvr_ops *this, + struct fsl_usb2_platform_data *pdata, int on) +{ + struct device *dev = &pdata->pdev->dev; + struct regulator *usbotg_regux; + + pr_debug("real %s(on=%d) pdata=0x%p\n", __func__, on, pdata); + if (machine_is_mx37_3ds()) { + if (!board_is_mx37(BOARD_REV_2)) + usbotg_regux = regulator_get(dev, "DCDC2"); + else + usbotg_regux = regulator_get(dev, "SWBST"); + if (on) { + regulator_enable(usbotg_regux); + } else { + regulator_disable(usbotg_regux); + } + regulator_put(usbotg_regux, dev); +#if defined(CONFIG_MXC_PMIC_MC13892_MODULE) || defined(CONFIG_MXC_PMIC_MC13892) + } else if (machine_is_mx51_3ds()) { + unsigned int value; + + usbotg_regux = regulator_get(dev, "SWBST"); + if (on) + regulator_enable(usbotg_regux); + else + regulator_disable(usbotg_regux); + regulator_put(usbotg_regux, dev); + + /* VUSBIN */ + pmic_read_reg(REG_USB1, &value, 0xffffff); + if (on) + value |= 0x1; + else + value &= ~0x1; + pmic_write_reg(REG_USB1, value, 0xffffff); + + /* VUSBEN */ + usbotg_regux = regulator_get(dev, "USB"); + if (on) + regulator_enable(usbotg_regux); + else + regulator_disable(usbotg_regux); + regulator_put(usbotg_regux, dev); +#endif + } +} + +static struct fsl_xcvr_ops utmi_ops = { + .name = "utmi", + .xcvr_type = PORTSC_PTS_UTMI, + .init = usb_utmi_init, + .uninit = usb_utmi_uninit, + .set_vbus_power = set_power, +}; + +extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops); + +static int __init utmixc_init(void) +{ + fsl_usb_xcvr_register(&utmi_ops); + return 0; +} + +extern void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops); + +static void __exit utmixc_exit(void) +{ + fsl_usb_xcvr_unregister(&utmi_ops); +} + +module_init(utmixc_init); +module_exit(utmixc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("utmi xcvr driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/arch/arm/plat-mxc/wdog.c linux-2.6.26-lab126/arch/arm/plat-mxc/wdog.c --- linux-2.6.26/arch/arm/plat-mxc/wdog.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/arm/plat-mxc/wdog.c 2010-08-11 00:35:00.000000000 -0400 @@ -0,0 +1,153 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2010 Amazon Technologies Inc. + * Manish Lachwani (lachwani@lab126.com) + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file plat-mxc/wdog.c + * @brief This file contains watchdog timer implementations. + * + * This file contains watchdog timer implementations for timer tick. + * + * @ingroup WDOG + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define WDOG_WT 0x8 /* WDOG WT starting bit inside WCR */ +#define WCR_WOE_BIT (1 << 6) +#define WCR_WDA_BIT (1 << 5) +#define WCR_SRS_BIT (1 << 4) +#define WCR_WRE_BIT (1 << 3) +#define WCR_WDE_BIT (1 << 2) +#define WCR_WDBG_BIT (1 << 1) +#define WCR_WDZST_BIT (1 << 0) + +/* + * WatchDog + */ +#define WDOG_WCR 0 /* 16bit watchdog control reg */ +#define WDOG_WSR 2 /* 16bit watchdog service reg */ +#define WDOG_WRSR 4 /* 16bit watchdog reset status reg */ + +/* + * PROC entries + */ +#define PROC_WATCHDOG "watchdog" +#define PROC_WATCHDOG_RESET "reset" + +static struct proc_dir_entry *proc_watchdog_parent; +static struct proc_dir_entry *proc_watchdog_reset; + +/*! + * The base addresses for the WDOG modules + */ +static unsigned long wdog_base[2] = { + IO_ADDRESS(WDOG1_BASE_ADDR), +#ifdef WDOG2_BASE_ADDR + IO_ADDRESS(WDOG2_BASE_ADDR), +#endif +}; + +extern void arch_reset(char mode); +extern void doze_disable(void); + +void mxc_wd_reset(void) +{ + u16 reg; + struct clk *clk; + + clk = clk_get(NULL, "wdog_clk"); + clk_enable(clk); + reg = __raw_readw(wdog_base[0] + WDOG_WCR) & ~WCR_SRS_BIT; + reg |= WCR_WDE_BIT; + __raw_writew(reg, wdog_base[0] + WDOG_WCR); +} +EXPORT_SYMBOL(mxc_wd_reset); + +static void mxc_reset(void) +{ + arch_reset((char)1); +} + +static int g_wdog_count = 0; +#define WDOG_BASE_ADDR IO_ADDRESS(WDOG1_BASE_ADDR) + +/*! + * Kick the watchdog from the timer interrupt + */ +#define MXC_WDOG_PING_THRESHOLD 100 /* Every 100 timer interrupts */ + +void mxc_kick_wd(void) +{ + if (g_wdog_count++ >= MXC_WDOG_PING_THRESHOLD) { + g_wdog_count = 0; /* reset */ + + /* issue the service sequence instructions */ + __raw_writew(0x5555, WDOG_BASE_ADDR + WDOG_WSR); + __raw_writew(0xAAAA, WDOG_BASE_ADDR + WDOG_WSR); + } +} + +/*! + * Do a quick watchdog reset + */ +static int mxc_wdt_reset_write(struct file *file, const char __user *buf, + unsigned long count, void *data) +{ + char comm[TASK_COMM_LEN]; + + mxc_reset(); + + /* Point of no return */ + while (1) { + /* Do nothing */ + } + + return -EINVAL; +} + +static int __init mxc_watchdog_init(void) +{ + proc_watchdog_parent = create_proc_entry(PROC_WATCHDOG, S_IFDIR | S_IRUGO | S_IXUGO, NULL); + if (proc_watchdog_parent != NULL) { + proc_watchdog_reset = create_proc_entry(PROC_WATCHDOG_RESET, + S_IWUSR | S_IRUGO, proc_watchdog_parent); + if (proc_watchdog_reset != NULL) { + proc_watchdog_reset->data = NULL; + proc_watchdog_reset->read_proc = NULL; + proc_watchdog_reset->write_proc = mxc_wdt_reset_write; + } + } + return 0; +} + +static void __exit mxc_watchdog_exit(void) +{ + if (proc_watchdog_parent != NULL) { + remove_proc_entry(PROC_WATCHDOG_RESET, proc_watchdog_parent); + remove_proc_entry(PROC_WATCHDOG, NULL); + proc_watchdog_parent = proc_watchdog_reset = NULL; + } +} + +module_init(mxc_watchdog_init); +module_exit(mxc_watchdog_exit); + diff -urN linux-2.6.26/arch/arm/plat-omap/clock.c linux-2.6.26-lab126/arch/arm/plat-omap/clock.c --- linux-2.6.26/arch/arm/plat-omap/clock.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/plat-omap/clock.c 2010-08-10 04:14:07.000000000 -0400 @@ -168,15 +168,12 @@ unsigned long clk_get_rate(struct clk *clk) { - unsigned long flags; unsigned long ret = 0; if (clk == NULL || IS_ERR(clk)) return 0; - spin_lock_irqsave(&clockfw_lock, flags); ret = clk->rate; - spin_unlock_irqrestore(&clockfw_lock, flags); return ret; } diff -urN linux-2.6.26/arch/arm/tools/mach-types linux-2.6.26-lab126/arch/arm/tools/mach-types --- linux-2.6.26/arch/arm/tools/mach-types 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/tools/mach-types 2010-08-10 04:14:03.000000000 -0400 @@ -1640,7 +1640,8 @@ ase2 MACH_ASE2 ASE2 1642 mx35evb MACH_MX35EVB MX35EVB 1643 aml_m8050 MACH_AML_M8050 AML_M8050 1644 -mx35_3ds MACH_MX35_3DS MX35_3DS 1645 +#mx35_3ds MACH_MX35_3DS MX35_3DS 1645 +mx35_luigi MACH_MX35_LUIGI MX35_LUIGI 1645 mars MACH_MARS MARS 1646 ntosd_644xa MACH_NTOSD_644XA NTOSD_644XA 1647 badger MACH_BADGER BADGER 1648 @@ -1720,3 +1721,4 @@ lg_ks20 MACH_LG_KS20 LG_KS20 1725 hhgps MACH_HHGPS HHGPS 1726 nokia_n810_wimax MACH_NOKIA_N810_WIMAX NOKIA_N810_WIMAX 1727 +mx25_3ds MACH_MX25_3DS MX25_3DS 1771 diff -urN linux-2.6.26/arch/arm/vfp/entry.S linux-2.6.26-lab126/arch/arm/vfp/entry.S --- linux-2.6.26/arch/arm/vfp/entry.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/vfp/entry.S 2010-08-10 04:14:02.000000000 -0400 @@ -15,14 +15,17 @@ * r10 = thread_info structure * lr = failure return */ -#include -#include -#include -#include +#include #include +#include "../kernel/entry-header.S" .globl do_vfp do_vfp: +#ifdef CONFIG_PREEMPT + ldr r4, [r10, #TI_PREEMPT] @ get preempt count + add r11, r4, #1 @ increment it + str r11, [r10, #TI_PREEMPT] +#endif enable_irq ldr r4, .LCvfp ldr r11, [r10, #TI_CPU] @ CPU number @@ -30,6 +33,12 @@ ldr pc, [r4] @ call VFP entry point ENTRY(vfp_null_entry) +#ifdef CONFIG_PREEMPT + get_thread_info r10 + ldr r4, [r10, #TI_PREEMPT] @ get preempt count + sub r11, r4, #1 @ decrement it + str r11, [r10, #TI_PREEMPT] +#endif mov pc, lr ENDPROC(vfp_null_entry) @@ -42,6 +51,12 @@ __INIT .globl vfp_testing_entry vfp_testing_entry: +#ifdef CONFIG_PREEMPT + get_thread_info r10 + ldr r4, [r10, #TI_PREEMPT] @ get preempt count + sub r11, r4, #1 @ decrement it + str r11, [r10, #TI_PREEMPT] +#endif ldr r0, VFP_arch_address str r5, [r0] @ known non-zero value mov pc, r9 @ we have handled the fault diff -urN linux-2.6.26/arch/arm/vfp/vfp.h linux-2.6.26-lab126/arch/arm/vfp/vfp.h --- linux-2.6.26/arch/arm/vfp/vfp.h 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/vfp/vfp.h 2010-08-10 04:14:02.000000000 -0400 @@ -377,6 +377,4 @@ u32 flags; }; -#ifdef CONFIG_SMP extern void vfp_save_state(void *location, u32 fpexc); -#endif diff -urN linux-2.6.26/arch/arm/vfp/vfphw.S linux-2.6.26-lab126/arch/arm/vfp/vfphw.S --- linux-2.6.26/arch/arm/vfp/vfphw.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/vfp/vfphw.S 2010-08-10 04:14:02.000000000 -0400 @@ -132,6 +132,12 @@ VFPFMXR FPEXC, r1 @ restore FPEXC last sub r2, r2, #4 str r2, [sp, #S_PC] @ retry the instruction +#ifdef CONFIG_PREEMPT + get_thread_info r10 + ldr r4, [r10, #TI_PREEMPT] @ get preempt count + sub r11, r4, #1 @ decrement it + str r11, [r10, #TI_PREEMPT] +#endif mov pc, r9 @ we think we have handled things @@ -150,6 +156,12 @@ @ not recognised by VFP DBGSTR "not VFP" +#ifdef CONFIG_PREEMPT + get_thread_info r10 + ldr r4, [r10, #TI_PREEMPT] @ get preempt count + sub r11, r4, #1 @ decrement it + str r11, [r10, #TI_PREEMPT] +#endif mov pc, lr process_exception: @@ -166,7 +178,6 @@ @ required. If not, the user code will @ retry the faulted instruction -#ifdef CONFIG_SMP .globl vfp_save_state .type vfp_save_state, %function vfp_save_state: @@ -182,7 +193,6 @@ VFPFMRX r12, FPINST2, NE @ FPINST2 if needed (and present) stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2 mov pc, lr -#endif last_VFP_context_address: .word last_VFP_context diff -urN linux-2.6.26/arch/arm/vfp/vfpmodule.c linux-2.6.26-lab126/arch/arm/vfp/vfpmodule.c --- linux-2.6.26/arch/arm/vfp/vfpmodule.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/arm/vfp/vfpmodule.c 2010-08-10 04:14:02.000000000 -0400 @@ -15,6 +15,10 @@ #include #include +#ifdef CONFIG_PM +#include +#endif + #include #include @@ -157,6 +161,9 @@ * Comparison instructions always return at least one of * these flags set. */ + if (exceptions & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V)) + fpscr &= ~(FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V); + fpscr |= exceptions; fmxr(FPSCR, fpscr); @@ -266,7 +273,7 @@ * on VFP subarch 1. */ vfp_raise_exceptions(VFP_EXCEPTION_ERROR, trigger, fpscr, regs); - return; + goto exit; } /* @@ -297,7 +304,7 @@ * the FPEXC.FP2V bit is valid only if FPEXC.EX is 1. */ if (fpexc ^ (FPEXC_EX | FPEXC_FP2V)) - return; + goto exit; /* * The barrier() here prevents fpinst2 being read @@ -310,6 +317,8 @@ exceptions = vfp_emulate_instruction(trigger, orig_fpscr, regs); if (exceptions) vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs); + exit: + preempt_enable(); } static void vfp_enable(void *unused) @@ -322,8 +331,115 @@ set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11)); } +/* + * Synchronise the hardware VFP state of a thread other than current with the + * saved one. This function is used by the ptrace mechanism. + */ +#ifdef CONFIG_SMP +void vfp_sync_state(struct thread_info *thread) +{ + /* + * On SMP systems, the VFP state is automatically saved at every + * context switch. We mark the thread VFP state as belonging to a + * non-existent CPU so that the saved one will be reloaded when + * needed. + */ + thread->vfpstate.hard.cpu = NR_CPUS; +} +#else +void vfp_sync_state(struct thread_info *thread) +{ + unsigned int cpu = get_cpu(); + u32 fpexc = fmrx(FPEXC); + + /* + * If VFP is enabled, the previous state was already saved and + * last_VFP_context updated. + */ + if (fpexc & FPEXC_EN) + goto out; + + if (!last_VFP_context[cpu]) + goto out; + + /* + * Save the last VFP state on this CPU. + */ + fmxr(FPEXC, fpexc | FPEXC_EN); + vfp_save_state(last_VFP_context[cpu], fpexc); + fmxr(FPEXC, fpexc); + + /* + * Set the context to NULL to force a reload the next time the thread + * uses the VFP. + */ + last_VFP_context[cpu] = NULL; + +out: + put_cpu(); +} +#endif + #include +#ifdef CONFIG_PM + +/* Suspend the VFP after saving state */ +static int vfp_suspend(struct sys_device *dev, pm_message_t state) +{ + struct thread_info *ti = current_thread_info(); + + /* Read the floating point exception register */ + u32 fpexc = fmrx(FPEXC); + + printk(KERN_INFO "Suspending VFP ...\n"); + + /* Check if the VFP is enabled */ + if (fpexc & FPEXC_EN) { + /* Save state */ + vfp_save_state(&ti->vfpstate, fpexc); + + /* Disable the VFP */ + fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); + } + + /* Clear the last state */ + memset(last_VFP_context, 0, sizeof(last_VFP_context)); + return 0; +} + +/* Resume the VFP */ +static int vfp_resume(struct sys_device *dev) +{ + /* ensure we have access to the vfp */ + vfp_enable(NULL); + + /* and disable it to ensure the next usage restores the state */ + fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); + + return 0; +} + +static struct sysdev_class vfp_pm_sysclass = { + .name = "vfp", + .suspend = vfp_suspend, + .resume = vfp_resume, +}; + +static struct sys_device vfp_pm_sysdev = { + .cls = &vfp_pm_sysclass, +}; + +static void vfp_pm_init(void) +{ + sysdev_class_register(&vfp_pm_sysclass); + sysdev_register(&vfp_pm_sysdev); +} + +#else +static inline void vfp_pm_init(void) { } +#endif /* CONFIG_PM */ + /* * VFP support code initialisation. */ @@ -366,6 +482,9 @@ thread_register_notifier(&vfp_notifier_block); + /* Initialize the VFP pm */ + vfp_pm_init(); + /* * We detected VFP, and the support code is * in place; report VFP support to userspace. diff -urN linux-2.6.26/arch/avr32/kernel/process.c linux-2.6.26-lab126/arch/avr32/kernel/process.c --- linux-2.6.26/arch/avr32/kernel/process.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/avr32/kernel/process.c 2010-08-10 04:14:39.000000000 -0400 @@ -31,7 +31,7 @@ { /* endless idle loop with no priority at all */ while (1) { - tick_nohz_stop_sched_tick(); + tick_nohz_stop_sched_tick(1); while (!need_resched()) cpu_idle_sleep(); tick_nohz_restart_sched_tick(); diff -urN linux-2.6.26/arch/blackfin/boot/.gitignore linux-2.6.26-lab126/arch/blackfin/boot/.gitignore --- linux-2.6.26/arch/blackfin/boot/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/blackfin/boot/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1 +0,0 @@ -+vmImage diff -urN linux-2.6.26/arch/blackfin/kernel/process.c linux-2.6.26-lab126/arch/blackfin/kernel/process.c --- linux-2.6.26/arch/blackfin/kernel/process.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/blackfin/kernel/process.c 2010-08-10 04:15:06.000000000 -0400 @@ -105,7 +105,7 @@ #endif if (!idle) idle = default_idle; - tick_nohz_stop_sched_tick(); + tick_nohz_stop_sched_tick(1); while (!need_resched()) idle(); tick_nohz_restart_sched_tick(); diff -urN linux-2.6.26/arch/ia64/Kconfig linux-2.6.26-lab126/arch/ia64/Kconfig --- linux-2.6.26/arch/ia64/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ia64/Kconfig 2010-08-10 04:14:54.000000000 -0400 @@ -58,6 +58,7 @@ config RWSEM_XCHGADD_ALGORITHM bool + depends on !PREEMPT_RT default y config ARCH_HAS_ILOG2_U32 @@ -319,6 +320,69 @@ If you don't know what to do here, say N. + +config GENERIC_TIME + bool + default y + +config HIGH_RES_TIMERS + bool "High-Resolution Timers" + help + + POSIX timers are available by default. This option enables + high-resolution POSIX timers. With this option the resolution + is at least 1 microsecond. High resolution is not free. If + enabled this option will add a small overhead each time a + timer expires that is not on a 1/HZ tick boundary. If no such + timers are used the overhead is nil. + + This option enables two additional POSIX CLOCKS, + CLOCK_REALTIME_HR and CLOCK_MONOTONIC_HR. Note that this + option does not change the resolution of CLOCK_REALTIME or + CLOCK_MONOTONIC which remain at 1/HZ resolution. + +config HIGH_RES_RESOLUTION + int "High-Resolution-Timer resolution (nanoseconds)" + depends on HIGH_RES_TIMERS + default 1000 + help + + This sets the resolution of timers accessed with + CLOCK_REALTIME_HR and CLOCK_MONOTONIC_HR. Too + fine a resolution (small a number) will usually not + be observable due to normal system latencies. For an + 800 MHZ processor about 10,000 is the recommended maximum + (smallest number). If you don't need that sort of resolution, + higher numbers may generate less overhead. + +choice + prompt "Clock source" + depends on HIGH_RES_TIMERS + default HIGH_RES_TIMER_ITC + help + This option allows you to choose the hardware source in charge + of generating high precision interruptions on your system. + On IA-64 these are: + + + ITC Interval Time Counter 1/CPU clock + HPET High Precision Event Timer ~ (XXX:have to check the spec) + + The ITC timer is available on all the ia64 computers because + it is integrated directly into the processor. However it may not + give correct results on MP machines with processors running + at different clock rates. In this case you may want to use + the HPET if available on your machine. + + +config HIGH_RES_TIMER_ITC + bool "Interval Time Counter/ITC" + +config HIGH_RES_TIMER_HPET + bool "High Precision Event Timer/HPET" + +endchoice + config NR_CPUS int "Maximum number of CPUs (2-1024)" range 2 1024 diff -urN linux-2.6.26/arch/ia64/kernel/.gitignore linux-2.6.26-lab126/arch/ia64/kernel/.gitignore --- linux-2.6.26/arch/ia64/kernel/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ia64/kernel/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1 +0,0 @@ -gate.lds diff -urN linux-2.6.26/arch/ia64/kernel/asm-offsets.c linux-2.6.26-lab126/arch/ia64/kernel/asm-offsets.c --- linux-2.6.26/arch/ia64/kernel/asm-offsets.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ia64/kernel/asm-offsets.c 2010-08-10 04:14:52.000000000 -0400 @@ -265,6 +265,7 @@ offsetof (struct pal_min_state_area_s, pmsa_xip)); BLANK(); +#ifdef CONFIG_TIME_INTERPOLATION /* used by fsys_gettimeofday in arch/ia64/kernel/fsys.S */ DEFINE(IA64_GTOD_LOCK_OFFSET, offsetof (struct fsyscall_gtod_data_t, lock)); @@ -286,4 +287,5 @@ offsetof (struct itc_jitter_data_t, itc_jitter)); DEFINE(IA64_ITC_LASTCYCLE_OFFSET, offsetof (struct itc_jitter_data_t, itc_lastcycle)); +#endif } diff -urN linux-2.6.26/arch/ia64/kernel/entry.S linux-2.6.26-lab126/arch/ia64/kernel/entry.S --- linux-2.6.26/arch/ia64/kernel/entry.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ia64/kernel/entry.S 2010-08-10 04:14:52.000000000 -0400 @@ -1169,21 +1169,17 @@ .work_pending: tbit.z p6,p0=r31,TIF_NEED_RESCHED // is resched not needed? (p6) br.cond.sptk.few .notify -#ifdef CONFIG_PREEMPT -(pKStk) dep r21=-1,r0,PREEMPT_ACTIVE_BIT,1 +(pKStk) br.cond.sptk.many .fromkernel ;; -(pKStk) st4 [r20]=r21 -#endif ssm psr.i // enable interrupts br.call.spnt.many rp=schedule -.ret9: cmp.eq p6,p0=r0,r0 // p6 <- 1 (re-check) - rsm psr.i // disable interrupts +.ret9a: rsm psr.i // disable interrupts ;; -#ifdef CONFIG_PREEMPT -(pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13 - ;; -(pKStk) st4 [r20]=r0 // preempt_count() <- 0 -#endif + br.cond.sptk.many .endpreemptdep +.fromkernel: + br.call.spnt.many rp=preempt_schedule_irq +.ret9b: rsm psr.i // disable interrupts +.endpreemptdep: (pLvSys)br.cond.sptk.few .work_pending_syscall_end br.cond.sptk.many .work_processed_kernel diff -urN linux-2.6.26/arch/ia64/kernel/fsys.S linux-2.6.26-lab126/arch/ia64/kernel/fsys.S --- linux-2.6.26/arch/ia64/kernel/fsys.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ia64/kernel/fsys.S 2010-08-10 04:14:52.000000000 -0400 @@ -26,6 +26,7 @@ #include "entry.h" +#ifdef CONFIG_TIME_INTERPOLATION /* * See Documentation/ia64/fsys.txt for details on fsyscalls. * @@ -371,6 +372,26 @@ br.many .gettime END(fsys_clock_gettime) + +#else // !CONFIG_TIME_INTERPOLATION + +# define fsys_gettimeofday 0 +# define fsys_clock_gettime 0 + +.fail_einval: + mov r8 = EINVAL + mov r10 = -1 + FSYS_RETURN + +.fail_efault: + mov r8 = EFAULT + mov r10 = -1 + FSYS_RETURN + +#endif + + + /* * long fsys_rt_sigprocmask (int how, sigset_t *set, sigset_t *oset, size_t sigsetsize). */ diff -urN linux-2.6.26/arch/ia64/kernel/iosapic.c linux-2.6.26-lab126/arch/ia64/kernel/iosapic.c --- linux-2.6.26/arch/ia64/kernel/iosapic.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ia64/kernel/iosapic.c 2010-08-10 04:14:52.000000000 -0400 @@ -111,7 +111,7 @@ (PAGE_SIZE / sizeof(struct iosapic_rte_info)) #define RTE_PREALLOCATED (1) -static DEFINE_SPINLOCK(iosapic_lock); +static DEFINE_RAW_SPINLOCK(iosapic_lock); /* * These tables map IA-64 vectors to the IOSAPIC pin that generates this @@ -390,6 +390,34 @@ return 0; } +/* + * In the preemptible case mask the IRQ first then handle it and ack it. + */ +#ifdef CONFIG_PREEMPT_HARDIRQS + +static void +iosapic_ack_level_irq (unsigned int irq) +{ + ia64_vector vec = irq_to_vector(irq); + struct iosapic_rte_info *rte; + + move_irq(irq); + mask_irq(irq); + list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) + iosapic_eoi(rte->addr, vec); +} + +static void +iosapic_end_level_irq (unsigned int irq) +{ + if (!(irq_desc[irq].status & IRQ_INPROGRESS)) + unmask_irq(irq); +} + +#else /* !CONFIG_PREEMPT_HARDIRQS */ + +#define iosapic_ack_level_irq nop + static void iosapic_end_level_irq (unsigned int irq) { @@ -412,10 +440,11 @@ } } +#endif + #define iosapic_shutdown_level_irq mask_irq #define iosapic_enable_level_irq unmask_irq #define iosapic_disable_level_irq mask_irq -#define iosapic_ack_level_irq nop static struct irq_chip irq_type_iosapic_level = { .name = "IO-SAPIC-level", diff -urN linux-2.6.26/arch/ia64/kernel/mca.c linux-2.6.26-lab126/arch/ia64/kernel/mca.c --- linux-2.6.26/arch/ia64/kernel/mca.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ia64/kernel/mca.c 2010-08-10 04:14:52.000000000 -0400 @@ -349,7 +349,7 @@ typedef struct ia64_state_log_s { - spinlock_t isl_lock; + raw_spinlock_t isl_lock; int isl_index; unsigned long isl_count; ia64_err_rec_t *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */ diff -urN linux-2.6.26/arch/ia64/kernel/perfmon.c linux-2.6.26-lab126/arch/ia64/kernel/perfmon.c --- linux-2.6.26/arch/ia64/kernel/perfmon.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ia64/kernel/perfmon.c 2010-08-10 04:14:52.000000000 -0400 @@ -280,7 +280,7 @@ */ typedef struct pfm_context { - spinlock_t ctx_lock; /* context protection */ + raw_spinlock_t ctx_lock; /* context protection */ pfm_context_flags_t ctx_flags; /* bitmask of flags (block reason incl.) */ unsigned int ctx_state; /* state: active/inactive (no bitfield) */ @@ -369,7 +369,7 @@ * mostly used to synchronize between system wide and per-process */ typedef struct { - spinlock_t pfs_lock; /* lock the structure */ + raw_spinlock_t pfs_lock; /* lock the structure */ unsigned int pfs_task_sessions; /* number of per task sessions */ unsigned int pfs_sys_sessions; /* number of per system wide sessions */ @@ -510,7 +510,7 @@ static struct proc_dir_entry *perfmon_dir; static pfm_uuid_t pfm_null_uuid = {0,}; -static spinlock_t pfm_buffer_fmt_lock; +static raw_spinlock_t pfm_buffer_fmt_lock; static LIST_HEAD(pfm_buffer_fmt_list); static pmu_config_t *pmu_conf; diff -urN linux-2.6.26/arch/ia64/kernel/process.c linux-2.6.26-lab126/arch/ia64/kernel/process.c --- linux-2.6.26/arch/ia64/kernel/process.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ia64/kernel/process.c 2010-08-10 04:14:52.000000000 -0400 @@ -94,6 +94,9 @@ void dump_stack (void) { + if (irqs_disabled()) { + printk("Uh oh.. entering dump_stack() with irqs disabled.\n"); + } show_stack(NULL, NULL); } @@ -328,10 +331,11 @@ normal_xtp(); #endif } - preempt_enable_no_resched(); - schedule(); + __preempt_enable_no_resched(); + __schedule(); + preempt_disable(); - check_pgt_cache(); + if (cpu_is_offline(cpu)) play_dead(); } diff -urN linux-2.6.26/arch/ia64/kernel/sal.c linux-2.6.26-lab126/arch/ia64/kernel/sal.c --- linux-2.6.26/arch/ia64/kernel/sal.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ia64/kernel/sal.c 2010-08-10 04:14:52.000000000 -0400 @@ -18,7 +18,7 @@ #include #include - __cacheline_aligned DEFINE_SPINLOCK(sal_lock); + __cacheline_aligned DEFINE_RAW_SPINLOCK(sal_lock); unsigned long sal_platform_features; unsigned short sal_revision; diff -urN linux-2.6.26/arch/ia64/kernel/salinfo.c linux-2.6.26-lab126/arch/ia64/kernel/salinfo.c --- linux-2.6.26/arch/ia64/kernel/salinfo.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ia64/kernel/salinfo.c 2010-08-10 04:14:52.000000000 -0400 @@ -140,7 +140,7 @@ struct salinfo_data { cpumask_t cpu_event; /* which cpus have outstanding events */ - struct semaphore mutex; + struct compat_semaphore mutex; u8 *log_buffer; u64 log_size; u8 *oemdata; /* decoded oem data */ @@ -156,8 +156,8 @@ static struct salinfo_data salinfo_data[ARRAY_SIZE(salinfo_log_name)]; -static DEFINE_SPINLOCK(data_lock); -static DEFINE_SPINLOCK(data_saved_lock); +static DEFINE_RAW_SPINLOCK(data_lock); +static DEFINE_RAW_SPINLOCK(data_saved_lock); /** salinfo_platform_oemdata - optional callback to decode oemdata from an error * record. diff -urN linux-2.6.26/arch/ia64/kernel/signal.c linux-2.6.26-lab126/arch/ia64/kernel/signal.c --- linux-2.6.26/arch/ia64/kernel/signal.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ia64/kernel/signal.c 2010-08-10 04:14:52.000000000 -0400 @@ -456,6 +456,14 @@ long errno = scr->pt.r8; # define ERR_CODE(c) (IS_IA32_PROCESS(&scr->pt) ? -(c) : (c)) +#ifdef CONFIG_PREEMPT_RT + /* + * Fully-preemptible kernel does not need interrupts disabled: + */ + local_irq_enable(); + preempt_check_resched(); +#endif + /* * In the ia64_leave_kernel code path, we want the common case to go fast, which * is why we may in certain cases get here from kernel mode. Just return without diff -urN linux-2.6.26/arch/ia64/kernel/smp.c linux-2.6.26-lab126/arch/ia64/kernel/smp.c --- linux-2.6.26/arch/ia64/kernel/smp.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ia64/kernel/smp.c 2010-08-10 04:14:52.000000000 -0400 @@ -276,6 +276,22 @@ } /* + * this function sends a 'reschedule' IPI to all other CPUs. + * This is used when RT tasks are starving and other CPUs + * might be able to run them: + */ +void smp_send_reschedule_allbutself(void) +{ + unsigned int cpu; + + for_each_online_cpu(cpu) { + if (cpu != smp_processor_id()) + platform_send_ipi(cpu, IA64_IPI_RESCHEDULE, + IA64_IPI_DM_INT, 0); + } +} + +/* * Called with preemption disabled. */ static void diff -urN linux-2.6.26/arch/ia64/kernel/smpboot.c linux-2.6.26-lab126/arch/ia64/kernel/smpboot.c --- linux-2.6.26/arch/ia64/kernel/smpboot.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ia64/kernel/smpboot.c 2010-08-10 04:14:52.000000000 -0400 @@ -371,6 +371,8 @@ { } +extern void register_itc_clockevent(void); + static void __cpuinit smp_callin (void) { @@ -449,6 +451,7 @@ #ifdef CONFIG_IA32_SUPPORT ia32_gdt_init(); #endif + register_itc_clockevent(); /* * Allow the master to continue. diff -urN linux-2.6.26/arch/ia64/kernel/time.c linux-2.6.26-lab126/arch/ia64/kernel/time.c --- linux-2.6.26/arch/ia64/kernel/time.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ia64/kernel/time.c 2010-08-10 04:14:52.000000000 -0400 @@ -149,6 +149,7 @@ platform_timer_interrupt(irq, dev_id); +#if 0 new_itm = local_cpu_data->itm_next; if (!time_after(ia64_get_itc(), new_itm)) @@ -156,29 +157,48 @@ ia64_get_itc(), new_itm); profile_tick(CPU_PROFILING); +#endif + + if (time_after(ia64_get_itc(), local_cpu_data->itm_tick_next)) { - while (1) { - update_process_times(user_mode(get_irq_regs())); + unsigned long new_tick_itm; + new_tick_itm = local_cpu_data->itm_tick_next; - new_itm += local_cpu_data->itm_delta; + profile_tick(CPU_PROFILING, get_irq_regs()); - if (smp_processor_id() == time_keeper_id) { - /* - * Here we are in the timer irq handler. We have irqs locally - * disabled, but we don't know if the timer_bh is running on - * another CPU. We need to avoid to SMP race by acquiring the - * xtime_lock. - */ - write_seqlock(&xtime_lock); - do_timer(1); - local_cpu_data->itm_next = new_itm; - write_sequnlock(&xtime_lock); - } else - local_cpu_data->itm_next = new_itm; + while (1) { + update_process_times(user_mode(get_irq_regs())); + + new_tick_itm += local_cpu_data->itm_tick_delta; + + if (smp_processor_id() == time_keeper_id) { + /* + * Here we are in the timer irq handler. We have irqs locally + * disabled, but we don't know if the timer_bh is running on + * another CPU. We need to avoid to SMP race by acquiring the + * xtime_lock. + */ + write_seqlock(&xtime_lock); + do_timer(get_irq_regs()); + local_cpu_data->itm_tick_next = new_tick_itm; + write_sequnlock(&xtime_lock); + } else + local_cpu_data->itm_tick_next = new_tick_itm; + + if (time_after(new_tick_itm, ia64_get_itc())) + break; + } + } - if (time_after(new_itm, ia64_get_itc())) - break; + if (time_after(ia64_get_itc(), local_cpu_data->itm_timer_next)) { + if (itc_clockevent.event_handler) + itc_clockevent.event_handler(get_irq_regs()); + // FIXME, really, please + new_itm = local_cpu_data->itm_tick_next; + + if (time_after(new_itm, local_cpu_data->itm_timer_next)) + new_itm = local_cpu_data->itm_timer_next; /* * Allow IPIs to interrupt the timer loop. */ @@ -196,8 +216,8 @@ * too fast (with the potentially devastating effect * of losing monotony of time). */ - while (!time_after(new_itm, ia64_get_itc() + local_cpu_data->itm_delta/2)) - new_itm += local_cpu_data->itm_delta; + while (!time_after(new_itm, ia64_get_itc() + local_cpu_data->itm_tick_delta/2)) + new_itm += local_cpu_data->itm_tick_delta; ia64_set_itm(new_itm); /* double check, in case we got hit by a (slow) PMI: */ } while (time_after_eq(ia64_get_itc(), new_itm)); @@ -216,7 +236,7 @@ /* arrange for the cycle counter to generate a timer interrupt: */ ia64_set_itv(IA64_TIMER_VECTOR); - delta = local_cpu_data->itm_delta; + delta = local_cpu_data->itm_tick_delta; /* * Stagger the timer tick for each CPU so they don't occur all at (almost) the * same time: @@ -225,8 +245,8 @@ unsigned long hi = 1UL << ia64_fls(cpu); shift = (2*(cpu - hi) + 1) * delta/hi/2; } - local_cpu_data->itm_next = ia64_get_itc() + delta + shift; - ia64_set_itm(local_cpu_data->itm_next); + local_cpu_data->itm_tick_next = ia64_get_itc() + delta + shift; + ia64_set_itm(local_cpu_data->itm_tick_next); } static int nojitter; @@ -284,7 +304,7 @@ itc_freq = (platform_base_freq*itc_ratio.num)/itc_ratio.den; - local_cpu_data->itm_delta = (itc_freq + HZ/2) / HZ; + local_cpu_data->itm_tick_delta = (itc_freq + HZ/2) / HZ; printk(KERN_DEBUG "CPU %d: base freq=%lu.%03luMHz, ITC ratio=%u/%u, " "ITC freq=%lu.%03luMHz", smp_processor_id(), platform_base_freq / 1000000, (platform_base_freq / 1000) % 1000, @@ -304,6 +324,7 @@ local_cpu_data->nsec_per_cyc = ((NSEC_PER_SEC<mfh = 1; } - preempt_enable_no_resched(); + __preempt_enable_no_resched(); } static inline int diff -urN linux-2.6.26/arch/ia64/kernel/unwind.c linux-2.6.26-lab126/arch/ia64/kernel/unwind.c --- linux-2.6.26/arch/ia64/kernel/unwind.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ia64/kernel/unwind.c 2010-08-10 04:14:52.000000000 -0400 @@ -82,7 +82,7 @@ typedef unsigned char unw_hash_index_t; static struct { - spinlock_t lock; /* spinlock for unwind data */ + raw_spinlock_t lock; /* spinlock for unwind data */ /* list of unwind tables (one per load-module) */ struct unw_table *tables; @@ -146,7 +146,7 @@ # endif } unw = { .tables = &unw.kernel_table, - .lock = __SPIN_LOCK_UNLOCKED(unw.lock), + .lock = RAW_SPIN_LOCK_UNLOCKED(unw.lock), .save_order = { UNW_REG_RP, UNW_REG_PFS, UNW_REG_PSP, UNW_REG_PR, UNW_REG_UNAT, UNW_REG_LC, UNW_REG_FPSR, UNW_REG_PRI_UNAT_GR diff -urN linux-2.6.26/arch/ia64/kernel/unwind_i.h linux-2.6.26-lab126/arch/ia64/kernel/unwind_i.h --- linux-2.6.26/arch/ia64/kernel/unwind_i.h 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ia64/kernel/unwind_i.h 2010-08-10 04:14:52.000000000 -0400 @@ -154,7 +154,7 @@ unsigned long ip; /* ip this script is for */ unsigned long pr_mask; /* mask of predicates script depends on */ unsigned long pr_val; /* predicate values this script is for */ - rwlock_t lock; + raw_rwlock_t lock; unsigned int flags; /* see UNW_FLAG_* in unwind.h */ unsigned short lru_chain; /* used for least-recently-used chain */ unsigned short coll_chain; /* used for hash collisions */ diff -urN linux-2.6.26/arch/ia64/mm/init.c linux-2.6.26-lab126/arch/ia64/mm/init.c --- linux-2.6.26/arch/ia64/mm/init.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ia64/mm/init.c 2010-08-10 04:14:54.000000000 -0400 @@ -37,7 +37,7 @@ #include #include -DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); +DEFINE_PER_CPU_LOCKED(struct mmu_gather, mmu_gathers); extern void ia64_tlb_init (void); diff -urN linux-2.6.26/arch/ia64/mm/tlb.c linux-2.6.26-lab126/arch/ia64/mm/tlb.c --- linux-2.6.26/arch/ia64/mm/tlb.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ia64/mm/tlb.c 2010-08-10 04:14:54.000000000 -0400 @@ -39,7 +39,7 @@ } purge; struct ia64_ctx ia64_ctx = { - .lock = __SPIN_LOCK_UNLOCKED(ia64_ctx.lock), + .lock = RAW_SPIN_LOCK_UNLOCKED(ia64_ctx.lock), .next = 1, .max_ctx = ~0U }; diff -urN linux-2.6.26/arch/m68knommu/Kconfig linux-2.6.26-lab126/arch/m68knommu/Kconfig --- linux-2.6.26/arch/m68knommu/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/m68knommu/Kconfig 2010-08-10 04:14:48.000000000 -0400 @@ -58,10 +58,18 @@ bool default y +config GENERIC_CMOS_UPDATE + bool + default y + config TIME_LOW_RES bool default y +config GENERIC_CLOCKEVENTS + bool + default n + config NO_IOPORT def_bool y @@ -108,11 +116,14 @@ config M520x bool "MCF520x" + select GENERIC_CLOCKEVENTS help Freescale Coldfire 5207/5208 processor support. config M523x bool "MCF523x" + select GENERIC_CLOCKEVENTS + select GENERIC_HARDIRQS_NO__DO_IRQ help Freescale Coldfire 5230/1/2/4/5 processor support @@ -138,6 +149,7 @@ config M528x bool "MCF528x" + select GENERIC_CLOCKEVENTS help Motorola ColdFire 5280/5282 processor support. @@ -161,11 +173,13 @@ config M527x bool depends on (M5271 || M5275) + select GENERIC_CLOCKEVENTS default y config COLDFIRE bool depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407) + select HAVE_FTRACE default y config CLOCK_SET @@ -671,9 +685,15 @@ endchoice +config GENERIC_HARDIRQS_NO__DO_IRQ + bool "Force generic IRQ implementation" + if COLDFIRE source "kernel/Kconfig.preempt" endif + +source "kernel/time/Kconfig" + source "mm/Kconfig" endmenu diff -urN linux-2.6.26/arch/m68knommu/Makefile linux-2.6.26-lab126/arch/m68knommu/Makefile --- linux-2.6.26/arch/m68knommu/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/m68knommu/Makefile 2010-08-10 04:14:48.000000000 -0400 @@ -8,6 +8,8 @@ # (C) Copyright 2002, Greg Ungerer # +KBUILD_DEFCONFIG := m5208evb_defconfig + platform-$(CONFIG_M68328) := 68328 platform-$(CONFIG_M68EZ328) := 68EZ328 platform-$(CONFIG_M68VZ328) := 68VZ328 @@ -90,13 +92,14 @@ cflags-$(CONFIG_M5206) := -m5200 cflags-$(CONFIG_M5206e) := -m5200 cflags-$(CONFIG_M520x) := -m5307 -cflags-$(CONFIG_M523x) := -m5307 +cflags-$(CONFIG_M523x) := $(call cc-option,-mcpu=523x,-m5307) cflags-$(CONFIG_M5249) := -m5200 -cflags-$(CONFIG_M527x) := -m5307 +cflags-$(CONFIG_M5271) := $(call cc-option,-mcpu=5271,-m5307) cflags-$(CONFIG_M5272) := -m5307 -cflags-$(CONFIG_M528x) := -m5307 +cflags-$(CONFIG_M5275) := $(call cc-option,-mcpu=5275,-m5307) +cflags-$(CONFIG_M528x) := $(call cc-option,-m528x,-m5307) cflags-$(CONFIG_M5307) := -m5307 -cflags-$(CONFIG_M532x) := -m5307 +cflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307) cflags-$(CONFIG_M5407) := -m5200 cflags-$(CONFIG_M68328) := -m68000 cflags-$(CONFIG_M68EZ328) := -m68000 diff -urN linux-2.6.26/arch/m68knommu/configs/m5208evb_defconfig linux-2.6.26-lab126/arch/m68knommu/configs/m5208evb_defconfig --- linux-2.6.26/arch/m68knommu/configs/m5208evb_defconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/m68knommu/configs/m5208evb_defconfig 2010-08-10 04:14:47.000000000 -0400 @@ -0,0 +1,610 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.26-rc1 +# +CONFIG_M68K=y +# CONFIG_MMU is not set +# CONFIG_FPU is not set +CONFIG_ZONE_DMA=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_TIME=y +CONFIG_TIME_LOW_RES=y +CONFIG_NO_IOPORT=y +CONFIG_ARCH_SUPPORTS_AOUT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SYSVIPC is not set +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +# CONFIG_UID16 is not set +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_KALLSYMS is not set +# CONFIG_HOTPLUG is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +# CONFIG_COMPAT_BRK is not set +CONFIG_BASE_FULL=y +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +# CONFIG_HAVE_OPROFILE is not set +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +# CONFIG_HAVE_DMA_ATTRS is not set +CONFIG_SLABINFO=y +CONFIG_TINY_SHMEM=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_CLASSIC_RCU=y + +# +# Processor type and features +# +# CONFIG_M68328 is not set +# CONFIG_M68EZ328 is not set +# CONFIG_M68VZ328 is not set +# CONFIG_M68360 is not set +# CONFIG_M5206 is not set +# CONFIG_M5206e is not set +CONFIG_M520x=y +# CONFIG_M523x is not set +# CONFIG_M5249 is not set +# CONFIG_M5271 is not set +# CONFIG_M5272 is not set +# CONFIG_M5275 is not set +# CONFIG_M528x is not set +# CONFIG_M5307 is not set +# CONFIG_M532x is not set +# CONFIG_M5407 is not set +CONFIG_COLDFIRE=y +CONFIG_CLOCK_SET=y +CONFIG_CLOCK_FREQ=166666666 +CONFIG_CLOCK_DIV=2 + +# +# Platform +# +CONFIG_M5208EVB=y +CONFIG_FREESCALE=y +# CONFIG_4KSTACKS is not set +CONFIG_HZ=100 + +# +# RAM configuration +# +CONFIG_RAMBASE=0x40000000 +CONFIG_RAMSIZE=0x2000000 +CONFIG_VECTORBASE=0x40000000 +CONFIG_KERNELBASE=0x40020000 +# CONFIG_RAMAUTOBIT is not set +# CONFIG_RAM8BIT is not set +CONFIG_RAM16BIT=y +# CONFIG_RAM32BIT is not set + +# +# ROM configuration +# +# CONFIG_ROM is not set +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_VIRT_TO_BUS=y +CONFIG_ISA_DMA_API=y + +# +# Bus options (PCI, PCMCIA, EISA, MCA, ISA) +# +# CONFIG_PCI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_FLAT=y +# CONFIG_BINFMT_ZFLAT is not set +# CONFIG_BINFMT_SHARED_FLAT is not set +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_RAM=y +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_UCLINUX=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +CONFIG_FEC=y +# CONFIG_FEC2 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI is not set +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_COLDFIRE is not set +CONFIG_SERIAL_MCF=y +CONFIG_SERIAL_MCF_BAUDRATE=115200 +CONFIG_SERIAL_MCF_CONSOLE=y +# CONFIG_UNIX98_PTYS is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Sound +# +# CONFIG_SOUND is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +# CONFIG_SYSFS is not set +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_SAMPLES is not set +CONFIG_FULLDEBUG=y +# CONFIG_HIGHPROFILE is not set +# CONFIG_BOOTPARAM is not set +# CONFIG_NO_KERNEL_MSG is not set +# CONFIG_BDM_DISABLE is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y diff -urN linux-2.6.26/arch/m68knommu/configs/m5249evb_defconfig linux-2.6.26-lab126/arch/m68knommu/configs/m5249evb_defconfig --- linux-2.6.26/arch/m68knommu/configs/m5249evb_defconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/m68knommu/configs/m5249evb_defconfig 2010-08-10 04:14:47.000000000 -0400 @@ -0,0 +1,497 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.26-rc1 +# +CONFIG_M68K=y +# CONFIG_MMU is not set +# CONFIG_FPU is not set +CONFIG_ZONE_DMA=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_TIME=y +CONFIG_TIME_LOW_RES=y +CONFIG_NO_IOPORT=y +CONFIG_ARCH_SUPPORTS_AOUT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SYSVIPC is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +# CONFIG_UID16 is not set +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_KALLSYMS is not set +# CONFIG_HOTPLUG is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +# CONFIG_COMPAT_BRK is not set +CONFIG_BASE_FULL=y +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +# CONFIG_HAVE_OPROFILE is not set +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +# CONFIG_HAVE_DMA_ATTRS is not set +CONFIG_SLABINFO=y +CONFIG_TINY_SHMEM=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_CLASSIC_RCU=y + +# +# Processor type and features +# +# CONFIG_M68328 is not set +# CONFIG_M68EZ328 is not set +# CONFIG_M68VZ328 is not set +# CONFIG_M68360 is not set +# CONFIG_M5206 is not set +# CONFIG_M5206e is not set +# CONFIG_M520x is not set +# CONFIG_M523x is not set +CONFIG_M5249=y +# CONFIG_M5271 is not set +# CONFIG_M5272 is not set +# CONFIG_M5275 is not set +# CONFIG_M528x is not set +# CONFIG_M5307 is not set +# CONFIG_M532x is not set +# CONFIG_M5407 is not set +CONFIG_COLDFIRE=y +CONFIG_CLOCK_SET=y +CONFIG_CLOCK_FREQ=140000000 +CONFIG_CLOCK_DIV=2 + +# +# Platform +# +CONFIG_M5249C3=y +CONFIG_FREESCALE=y +CONFIG_4KSTACKS=y +CONFIG_HZ=100 + +# +# RAM configuration +# +CONFIG_RAMBASE=0x00000000 +CONFIG_RAMSIZE=0x00800000 +CONFIG_VECTORBASE=0x00000000 +CONFIG_KERNELBASE=0x00020000 +CONFIG_RAMAUTOBIT=y +# CONFIG_RAM8BIT is not set +# CONFIG_RAM16BIT is not set +# CONFIG_RAM32BIT is not set + +# +# ROM configuration +# +# CONFIG_ROM is not set +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_VIRT_TO_BUS=y +CONFIG_ISA_DMA_API=y + +# +# Bus options (PCI, PCMCIA, EISA, MCA, ISA) +# +# CONFIG_PCI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_FLAT=y +# CONFIG_BINFMT_ZFLAT is not set +# CONFIG_BINFMT_SHARED_FLAT is not set +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_RAM=y +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_UCLINUX=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_COLDFIRE is not set +CONFIG_SERIAL_MCF=y +CONFIG_SERIAL_MCF_BAUDRATE=19200 +CONFIG_SERIAL_MCF_CONSOLE=y +# CONFIG_UNIX98_PTYS is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Sound +# +# CONFIG_SOUND is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_SAMPLES is not set +# CONFIG_FULLDEBUG is not set +# CONFIG_HIGHPROFILE is not set +# CONFIG_BOOTPARAM is not set +# CONFIG_NO_KERNEL_MSG is not set +# CONFIG_BDM_DISABLE is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y diff -urN linux-2.6.26/arch/m68knommu/configs/m5275evb_defconfig linux-2.6.26-lab126/arch/m68knommu/configs/m5275evb_defconfig --- linux-2.6.26/arch/m68knommu/configs/m5275evb_defconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/m68knommu/configs/m5275evb_defconfig 2010-08-10 04:14:47.000000000 -0400 @@ -0,0 +1,627 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.26-rc1 +# +CONFIG_M68K=y +# CONFIG_MMU is not set +# CONFIG_FPU is not set +CONFIG_ZONE_DMA=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_TIME=y +CONFIG_TIME_LOW_RES=y +CONFIG_NO_IOPORT=y +CONFIG_ARCH_SUPPORTS_AOUT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SYSVIPC is not set +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +# CONFIG_UID16 is not set +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_KALLSYMS is not set +# CONFIG_HOTPLUG is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +# CONFIG_COMPAT_BRK is not set +CONFIG_BASE_FULL=y +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +# CONFIG_HAVE_OPROFILE is not set +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +# CONFIG_HAVE_DMA_ATTRS is not set +CONFIG_SLABINFO=y +CONFIG_TINY_SHMEM=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_CLASSIC_RCU=y + +# +# Processor type and features +# +# CONFIG_M68328 is not set +# CONFIG_M68EZ328 is not set +# CONFIG_M68VZ328 is not set +# CONFIG_M68360 is not set +# CONFIG_M5206 is not set +# CONFIG_M5206e is not set +# CONFIG_M520x is not set +# CONFIG_M523x is not set +# CONFIG_M5249 is not set +# CONFIG_M5271 is not set +# CONFIG_M5272 is not set +CONFIG_M5275=y +# CONFIG_M528x is not set +# CONFIG_M5307 is not set +# CONFIG_M532x is not set +# CONFIG_M5407 is not set +CONFIG_M527x=y +CONFIG_COLDFIRE=y +CONFIG_CLOCK_SET=y +CONFIG_CLOCK_FREQ=150000000 +CONFIG_CLOCK_DIV=2 + +# +# Platform +# +CONFIG_M5275EVB=y +CONFIG_FREESCALE=y +# CONFIG_4KSTACKS is not set +CONFIG_HZ=100 + +# +# RAM configuration +# +CONFIG_RAMBASE=0x00000000 +CONFIG_RAMSIZE=0x00000000 +CONFIG_VECTORBASE=0x00000000 +CONFIG_KERNELBASE=0x00020000 +CONFIG_RAMAUTOBIT=y +# CONFIG_RAM8BIT is not set +# CONFIG_RAM16BIT is not set +# CONFIG_RAM32BIT is not set + +# +# ROM configuration +# +# CONFIG_ROM is not set +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_VIRT_TO_BUS=y +CONFIG_ISA_DMA_API=y + +# +# Bus options (PCI, PCMCIA, EISA, MCA, ISA) +# +# CONFIG_PCI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_FLAT=y +# CONFIG_BINFMT_ZFLAT is not set +# CONFIG_BINFMT_SHARED_FLAT is not set +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_RAM=y +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_UCLINUX=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +CONFIG_FEC=y +CONFIG_FEC2=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI is not set +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_WAN is not set +CONFIG_PPP=y +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +# CONFIG_PPP_ASYNC is not set +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_PPP_DEFLATE is not set +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_MPPE is not set +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=y +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_COLDFIRE is not set +CONFIG_SERIAL_MCF=y +CONFIG_SERIAL_MCF_BAUDRATE=19200 +CONFIG_SERIAL_MCF_CONSOLE=y +# CONFIG_UNIX98_PTYS is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set + +# +# Multimedia drivers +# +CONFIG_DAB=y + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Sound +# +# CONFIG_SOUND is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_SAMPLES is not set +# CONFIG_FULLDEBUG is not set +# CONFIG_HIGHPROFILE is not set +# CONFIG_BOOTPARAM is not set +# CONFIG_NO_KERNEL_MSG is not set +# CONFIG_BDM_DISABLE is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y diff -urN linux-2.6.26/arch/m68knommu/configs/m5307c3_defconfig linux-2.6.26-lab126/arch/m68knommu/configs/m5307c3_defconfig --- linux-2.6.26/arch/m68knommu/configs/m5307c3_defconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/m68knommu/configs/m5307c3_defconfig 2010-08-10 04:14:47.000000000 -0400 @@ -0,0 +1,580 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.26-rc1 +# +CONFIG_M68K=y +# CONFIG_MMU is not set +# CONFIG_FPU is not set +CONFIG_ZONE_DMA=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_TIME=y +CONFIG_TIME_LOW_RES=y +CONFIG_NO_IOPORT=y +CONFIG_ARCH_SUPPORTS_AOUT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SYSVIPC is not set +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +# CONFIG_UID16 is not set +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_KALLSYMS is not set +# CONFIG_HOTPLUG is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +# CONFIG_COMPAT_BRK is not set +CONFIG_BASE_FULL=y +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +# CONFIG_HAVE_OPROFILE is not set +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +# CONFIG_HAVE_DMA_ATTRS is not set +CONFIG_SLABINFO=y +CONFIG_TINY_SHMEM=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_CLASSIC_RCU=y + +# +# Processor type and features +# +# CONFIG_M68328 is not set +# CONFIG_M68EZ328 is not set +# CONFIG_M68VZ328 is not set +# CONFIG_M68360 is not set +# CONFIG_M5206 is not set +# CONFIG_M5206e is not set +# CONFIG_M520x is not set +# CONFIG_M523x is not set +# CONFIG_M5249 is not set +# CONFIG_M5271 is not set +# CONFIG_M5272 is not set +# CONFIG_M5275 is not set +# CONFIG_M528x is not set +CONFIG_M5307=y +# CONFIG_M532x is not set +# CONFIG_M5407 is not set +CONFIG_COLDFIRE=y +CONFIG_CLOCK_SET=y +CONFIG_CLOCK_FREQ=90000000 +CONFIG_CLOCK_DIV=2 +# CONFIG_OLDMASK is not set + +# +# Platform +# +# CONFIG_ARN5307 is not set +CONFIG_M5307C3=y +# CONFIG_eLIA is not set +# CONFIG_SECUREEDGEMP3 is not set +# CONFIG_CLEOPATRA is not set +# CONFIG_NETtel is not set +CONFIG_FREESCALE=y +# CONFIG_4KSTACKS is not set +CONFIG_HZ=100 + +# +# RAM configuration +# +CONFIG_RAMBASE=0x00000000 +CONFIG_RAMSIZE=0x00800000 +CONFIG_VECTORBASE=0x00000000 +CONFIG_KERNELBASE=0x00020000 +CONFIG_RAMAUTOBIT=y +# CONFIG_RAM8BIT is not set +# CONFIG_RAM16BIT is not set +# CONFIG_RAM32BIT is not set + +# +# ROM configuration +# +# CONFIG_ROM is not set +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_VIRT_TO_BUS=y +CONFIG_ISA_DMA_API=y + +# +# Bus options (PCI, PCMCIA, EISA, MCA, ISA) +# +# CONFIG_PCI is not set +# CONFIG_COMEMPCI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_FLAT=y +# CONFIG_BINFMT_ZFLAT is not set +# CONFIG_BINFMT_SHARED_FLAT is not set +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI is not set +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_WAN is not set +CONFIG_PPP=y +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +# CONFIG_PPP_ASYNC is not set +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_PPP_DEFLATE is not set +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_MPPE is not set +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +CONFIG_SLIP=y +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLHC=y +# CONFIG_SLIP_SMART is not set +# CONFIG_SLIP_MODE_SLIP6 is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_COLDFIRE is not set +CONFIG_SERIAL_MCF=y +CONFIG_SERIAL_MCF_BAUDRATE=19200 +CONFIG_SERIAL_MCF_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set + +# +# Multimedia drivers +# +CONFIG_DAB=y + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Sound +# +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_SAMPLES is not set +CONFIG_FULLDEBUG=y +# CONFIG_HIGHPROFILE is not set +# CONFIG_BOOTPARAM is not set +# CONFIG_NO_KERNEL_MSG is not set +# CONFIG_BDM_DISABLE is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y diff -urN linux-2.6.26/arch/m68knommu/configs/m5407c3_defconfig linux-2.6.26-lab126/arch/m68knommu/configs/m5407c3_defconfig --- linux-2.6.26/arch/m68knommu/configs/m5407c3_defconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/m68knommu/configs/m5407c3_defconfig 2010-08-10 04:14:47.000000000 -0400 @@ -0,0 +1,641 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.26-rc1 +# Wed May 7 10:25:16 2008 +# +CONFIG_M68K=y +# CONFIG_MMU is not set +# CONFIG_FPU is not set +CONFIG_ZONE_DMA=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_TIME=y +CONFIG_TIME_LOW_RES=y +CONFIG_NO_IOPORT=y +CONFIG_ARCH_SUPPORTS_AOUT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SYSVIPC is not set +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +# CONFIG_UID16 is not set +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_KALLSYMS is not set +# CONFIG_HOTPLUG is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +# CONFIG_COMPAT_BRK is not set +CONFIG_BASE_FULL=y +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +# CONFIG_HAVE_OPROFILE is not set +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +# CONFIG_HAVE_DMA_ATTRS is not set +CONFIG_SLABINFO=y +CONFIG_TINY_SHMEM=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_CLASSIC_RCU=y + +# +# Processor type and features +# +# CONFIG_M68328 is not set +# CONFIG_M68EZ328 is not set +# CONFIG_M68VZ328 is not set +# CONFIG_M68360 is not set +# CONFIG_M5206 is not set +# CONFIG_M5206e is not set +# CONFIG_M520x is not set +# CONFIG_M523x is not set +# CONFIG_M5249 is not set +# CONFIG_M5271 is not set +# CONFIG_M5272 is not set +# CONFIG_M5275 is not set +# CONFIG_M528x is not set +# CONFIG_M5307 is not set +# CONFIG_M532x is not set +CONFIG_M5407=y +CONFIG_COLDFIRE=y +CONFIG_CLOCK_SET=y +CONFIG_CLOCK_FREQ=50000000 +CONFIG_CLOCK_DIV=1 + +# +# Platform +# +CONFIG_M5407C3=y +# CONFIG_CLEOPATRA is not set +CONFIG_FREESCALE=y +CONFIG_4KSTACKS=y +CONFIG_HZ=100 + +# +# RAM configuration +# +CONFIG_RAMBASE=0x00000000 +CONFIG_RAMSIZE=0x00000000 +CONFIG_VECTORBASE=0x00000000 +CONFIG_KERNELBASE=0x00020000 +CONFIG_RAMAUTOBIT=y +# CONFIG_RAM8BIT is not set +# CONFIG_RAM16BIT is not set +# CONFIG_RAM32BIT is not set + +# +# ROM configuration +# +# CONFIG_ROM is not set +CONFIG_RAMKERNEL=y +# CONFIG_ROMKERNEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_VIRT_TO_BUS=y +CONFIG_ISA_DMA_API=y + +# +# Bus options (PCI, PCMCIA, EISA, MCA, ISA) +# +# CONFIG_PCI is not set +# CONFIG_COMEMPCI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_FLAT=y +# CONFIG_BINFMT_ZFLAT is not set +# CONFIG_BINFMT_SHARED_FLAT is not set +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_RAM=y +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_UCLINUX=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI is not set +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_WAN is not set +CONFIG_PPP=y +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +# CONFIG_PPP_ASYNC is not set +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_PPP_DEFLATE is not set +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_MPPE is not set +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=y +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_COLDFIRE is not set +CONFIG_SERIAL_MCF=y +CONFIG_SERIAL_MCF_BAUDRATE=19200 +CONFIG_SERIAL_MCF_CONSOLE=y +# CONFIG_UNIX98_PTYS is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set + +# +# Multimedia drivers +# +CONFIG_DAB=y + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Sound +# +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_SAMPLES is not set +# CONFIG_FULLDEBUG is not set +# CONFIG_HIGHPROFILE is not set +# CONFIG_BOOTPARAM is not set +# CONFIG_NO_KERNEL_MSG is not set +# CONFIG_BDM_DISABLE is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y diff -urN linux-2.6.26/arch/m68knommu/kernel/Makefile linux-2.6.26-lab126/arch/m68knommu/kernel/Makefile --- linux-2.6.26/arch/m68knommu/kernel/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/m68knommu/kernel/Makefile 2010-08-10 04:14:47.000000000 -0400 @@ -7,5 +7,6 @@ obj-y += dma.o entry.o init_task.o irq.o m68k_ksyms.o process.o ptrace.o \ setup.o signal.o syscalltable.o sys_m68k.o time.o traps.o -obj-$(CONFIG_MODULES) += module.o -obj-$(CONFIG_COMEMPCI) += comempci.o +obj-$(CONFIG_MODULES) += module.o +obj-$(CONFIG_COMEMPCI) += comempci.o +obj-$(CONFIG_STACKTRACE) += stacktrace.o diff -urN linux-2.6.26/arch/m68knommu/kernel/irq.c linux-2.6.26-lab126/arch/m68knommu/kernel/irq.c --- linux-2.6.26/arch/m68knommu/kernel/irq.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/m68knommu/kernel/irq.c 2010-08-10 04:14:47.000000000 -0400 @@ -23,7 +23,7 @@ struct pt_regs *oldregs = set_irq_regs(regs); irq_enter(); - __do_IRQ(irq); + generic_handle_irq(irq); irq_exit(); set_irq_regs(oldregs); @@ -34,12 +34,16 @@ printk(KERN_ERR "IRQ: unexpected irq=%d\n", irq); } +#ifndef CONFIG_M523x static struct irq_chip m_irq_chip = { .name = "M68K-INTC", .enable = enable_vector, .disable = disable_vector, .ack = ack_vector, }; +#else +void coldfire_init_irq_chip(void); +#endif void __init init_IRQ(void) { @@ -47,12 +51,16 @@ init_vectors(); +#ifndef CONFIG_M523x for (irq = 0; (irq < NR_IRQS); irq++) { irq_desc[irq].status = IRQ_DISABLED; irq_desc[irq].action = NULL; irq_desc[irq].depth = 1; irq_desc[irq].chip = &m_irq_chip; } +#else + coldfire_init_irq_chip(); +#endif } int show_interrupts(struct seq_file *p, void *v) @@ -79,4 +87,3 @@ return 0; } - diff -urN linux-2.6.26/arch/m68knommu/kernel/process.c linux-2.6.26-lab126/arch/m68knommu/kernel/process.c --- linux-2.6.26/arch/m68knommu/kernel/process.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/m68knommu/kernel/process.c 2010-08-10 04:14:47.000000000 -0400 @@ -74,10 +74,14 @@ { /* endless idle loop with no priority at all */ while (1) { + stop_critical_timings(); idle(); - preempt_enable_no_resched(); - schedule(); + start_critical_timings(); + local_irq_disable(); + __preempt_enable_no_resched(); + __schedule(); preempt_disable(); + local_irq_enable(); } } diff -urN linux-2.6.26/arch/m68knommu/kernel/stacktrace.c linux-2.6.26-lab126/arch/m68knommu/kernel/stacktrace.c --- linux-2.6.26/arch/m68knommu/kernel/stacktrace.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/m68knommu/kernel/stacktrace.c 2010-08-10 04:14:47.000000000 -0400 @@ -0,0 +1,69 @@ +/* + * Quick & dirty stacktrace implementation. + */ +#include +#include + +typedef void (save_stack_addr_t)(void *data, unsigned long addr, int reliable); + +static void save_stack_address(void *data, unsigned long addr, int reliable) +{ + struct stack_trace *trace = data; + if (!reliable) + return; + if (trace->skip > 0) { + trace->skip--; + return; + } + if (trace->nr_entries < trace->max_entries) + trace->entries[trace->nr_entries++] = addr; +} + +static void print_context_stack(unsigned long *stack, + save_stack_addr_t *sstack_func, struct stack_trace *trace) +{ + unsigned long *last_stack; + unsigned long *endstack; + unsigned long addr; + + addr = (unsigned long) stack; + endstack = (unsigned long *) PAGE_ALIGN(addr); + + last_stack = stack - 1; + while (stack <= endstack && stack > last_stack) { + + addr = *(stack + 1); + sstack_func(trace, addr, 1); + + last_stack = stack; + stack = (unsigned long *)*stack; + } +} + +static noinline long *get_current_stack(void) +{ + unsigned long *stack; + + stack = (unsigned long *)&stack; + stack++; + return stack; +} + +static void save_current_stack(save_stack_addr_t *sstack_func, + struct stack_trace *trace) +{ + unsigned long *stack; + + stack = get_current_stack(); + print_context_stack(stack, save_stack_address, trace); +} + +/* + * Save stack-backtrace addresses into a stack_trace buffer. + */ +void save_stack_trace(struct stack_trace *trace) +{ + save_current_stack(save_stack_address, trace); + if (trace->nr_entries < trace->max_entries) + trace->entries[trace->nr_entries++] = ULONG_MAX; +} diff -urN linux-2.6.26/arch/m68knommu/kernel/time.c linux-2.6.26-lab126/arch/m68knommu/kernel/time.c --- linux-2.6.26/arch/m68knommu/kernel/time.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/m68knommu/kernel/time.c 2010-08-10 04:14:47.000000000 -0400 @@ -33,14 +33,13 @@ return -1; } +#ifndef CONFIG_GENERIC_CLOCKEVENTS /* * timer_interrupt() needs to keep up the real-time clock, * as well as call the "do_timer()" routine every clocktick */ irqreturn_t arch_timer_interrupt(int irq, void *dummy) { - /* last time the cmos clock got updated */ - static long last_rtc_update=0; if (current->pid) profile_tick(CPU_PROFILING); @@ -49,21 +48,6 @@ do_timer(1); - /* - * If we have an externally synchronized Linux clock, then update - * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be - * called as close as possible to 500 ms before the new second starts. - */ - if (ntp_synced() && - xtime.tv_sec > last_rtc_update + 660 && - (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && - (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) { - if (set_rtc_mmss(xtime.tv_sec) == 0) - last_rtc_update = xtime.tv_sec; - else - last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */ - } - write_sequnlock(&xtime_lock); #ifndef CONFIG_SMP @@ -71,8 +55,9 @@ #endif return(IRQ_HANDLED); } +#endif -void time_init(void) +static unsigned long read_rtc_mmss(void) { unsigned int year, mon, day, hour, min, sec; @@ -83,10 +68,21 @@ if ((year += 1900) < 1970) year += 100; - xtime.tv_sec = mktime(year, mon, day, hour, min, sec); - xtime.tv_nsec = 0; - wall_to_monotonic.tv_sec = -xtime.tv_sec; - hw_timer_init(); + return mktime(year, mon, day, hour, min, sec);; +} + +unsigned long read_persistent_clock(void) +{ + return read_rtc_mmss(); } +int update_persistent_clock(struct timespec now) +{ + return set_rtc_mmss(now.tv_sec); +} + +void time_init(void) +{ + hw_timer_init(); +} diff -urN linux-2.6.26/arch/m68knommu/kernel/traps.c linux-2.6.26-lab126/arch/m68knommu/kernel/traps.c --- linux-2.6.26/arch/m68knommu/kernel/traps.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/m68knommu/kernel/traps.c 2010-08-10 04:14:47.000000000 -0400 @@ -103,12 +103,28 @@ force_sig(SIGSEGV, current); } +static void print_this_address(unsigned long addr, int i) +{ +#ifdef CONFIG_KALLSYMS + printk(KERN_EMERG " [%08lx] ", addr); + print_symbol(KERN_CONT "%s\n", addr); +#else + if (i % 5) + printk(KERN_CONT " [%08lx] ", addr); + else + printk(KERN_CONT "\n" KERN_EMERG " [%08lx] ", addr); + i++; +#endif +} + int kstack_depth_to_print = 48; static void __show_stack(struct task_struct *task, unsigned long *stack) { unsigned long *endstack, addr; +#ifdef CONFIG_FRAME_POINTER unsigned long *last_stack; +#endif int i; if (!stack) @@ -126,6 +142,7 @@ printk(" %08lx", *(stack + i)); } printk("\n"); + i = 0; #ifdef CONFIG_FRAME_POINTER printk(KERN_EMERG "Call Trace:\n"); @@ -134,15 +151,30 @@ while (stack <= endstack && stack > last_stack) { addr = *(stack + 1); - printk(KERN_EMERG " [%08lx] ", addr); - print_symbol(KERN_CONT "%s\n", addr); + print_this_address(addr, i); + i++; last_stack = stack; stack = (unsigned long *)*stack; } printk("\n"); #else - printk(KERN_EMERG "CONFIG_FRAME_POINTER disabled, no symbolic call trace\n"); + printk(KERN_EMERG "Call Trace with CONFIG_FRAME_POINTER disabled:\n"); + while (stack <= endstack) { + addr = *stack++; + /* + * If the address is either in the text segment of the kernel, + * or in a region which is occupied by a module then it *may* + * be the address of a calling routine; if so, print it so that + * someone tracing down the cause of the crash will be able to + * figure out the call path that was taken. + */ + if (__kernel_text_address(addr)) { + print_this_address(addr, i); + i++; + } + } + printk(KERN_CONT "\n"); #endif } diff -urN linux-2.6.26/arch/m68knommu/platform/coldfire/Makefile linux-2.6.26-lab126/arch/m68knommu/platform/coldfire/Makefile --- linux-2.6.26/arch/m68knommu/platform/coldfire/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/m68knommu/platform/coldfire/Makefile 2010-08-10 04:14:47.000000000 -0400 @@ -18,7 +18,7 @@ obj-$(CONFIG_M5206) += timers.o obj-$(CONFIG_M5206e) += timers.o obj-$(CONFIG_M520x) += pit.o -obj-$(CONFIG_M523x) += pit.o +obj-$(CONFIG_M523x) += pit.o dma_timer.o irq_chip.o obj-$(CONFIG_M5249) += timers.o obj-$(CONFIG_M527x) += pit.o obj-$(CONFIG_M5272) += timers.o diff -urN linux-2.6.26/arch/m68knommu/platform/coldfire/dma_timer.c linux-2.6.26-lab126/arch/m68knommu/platform/coldfire/dma_timer.c --- linux-2.6.26/arch/m68knommu/platform/coldfire/dma_timer.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/m68knommu/platform/coldfire/dma_timer.c 2010-08-10 04:14:47.000000000 -0400 @@ -0,0 +1,84 @@ +/* + * dma_timer.c -- Freescale ColdFire DMA Timer. + * + * Copyright (C) 2007, Benedikt Spranger + * Copyright (C) 2008. Sebastian Siewior, Linutronix + * + */ + +#include +#include + +#include +#include +#include +#include + +#define DMA_TIMER_0 (0x00) +#define DMA_TIMER_1 (0x40) +#define DMA_TIMER_2 (0x80) +#define DMA_TIMER_3 (0xc0) + +#define DTMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x400) +#define DTXMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x402) +#define DTER0 (MCF_IPSBAR + DMA_TIMER_0 + 0x403) +#define DTRR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x404) +#define DTCR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x408) +#define DTCN0 (MCF_IPSBAR + DMA_TIMER_0 + 0x40c) + +#define DMA_FREQ ((MCF_CLK / 2) / 16) + +/* DTMR */ +#define DMA_DTMR_RESTART (1 << 3) +#define DMA_DTMR_CLK_DIV_1 (1 << 1) +#define DMA_DTMR_CLK_DIV_16 (2 << 1) +#define DMA_DTMR_ENABLE (1 << 0) + +static cycle_t cf_dt_get_cycles(void) +{ + return __raw_readl(DTCN0); +} + +static struct clocksource clocksource_cf_dt = { + .name = "coldfire_dma_timer", + .rating = 200, + .read = cf_dt_get_cycles, + .mask = CLOCKSOURCE_MASK(32), + .shift = 20, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static int __init init_cf_dt_clocksource(void) +{ + /* + * We setup DMA timer 0 in free run mode. This incrementing counter is + * used as a highly precious clock source. With MCF_CLOCK = 150 MHz we + * get a ~213 ns resolution and the 32bit register will overflow almost + * every 15 minutes. + */ + __raw_writeb(0x00, DTXMR0); + __raw_writeb(0x00, DTER0); + __raw_writel(0x00000000, DTRR0); + __raw_writew(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0); + clocksource_cf_dt.mult = clocksource_hz2mult(DMA_FREQ, + clocksource_cf_dt.shift); + return clocksource_register(&clocksource_cf_dt); +} + +arch_initcall(init_cf_dt_clocksource); + +#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */ +#define CYC2NS_SCALE ((1000000 << CYC2NS_SCALE_FACTOR) / (DMA_FREQ / 1000)) + +static unsigned long long cycles2ns(unsigned long cycl) +{ + return (unsigned long long) ((unsigned long long)cycl * + CYC2NS_SCALE) >> CYC2NS_SCALE_FACTOR; +} + +unsigned long long sched_clock(void) +{ + unsigned long cycl = __raw_readl(DTCN0); + + return cycles2ns(cycl); +} diff -urN linux-2.6.26/arch/m68knommu/platform/coldfire/entry.S linux-2.6.26-lab126/arch/m68knommu/platform/coldfire/entry.S --- linux-2.6.26/arch/m68knommu/platform/coldfire/entry.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/m68knommu/platform/coldfire/entry.S 2010-08-10 04:14:47.000000000 -0400 @@ -55,6 +55,39 @@ .globl inthandler .globl fasthandler +#ifdef CONFIG_FTRACE +ENTRY(_mcount) + linkw %fp, #0 + + moveal ftrace_trace_function, %a0 + movel #ftrace_stub, %d0 + cmpl %a0@, %d0 + + bnew do_mcount + + unlk %fp + rts + +do_mcount: + + movel %fp, %d0 + moveal %d0, %a1 + + moveal %a1@, %a0 + movel %a0@(4), %sp@- /* push parent ip */ + movel %a1@(4), %sp@- /* push ip */ + + moveal ftrace_trace_function, %a0 + jsr %a0@ + + unlk %fp + +.globl ftrace_stub +ftrace_stub: + rts +END(mcount) +#endif + enosys: mov.l #sys_ni_syscall,%d3 bra 1f @@ -215,19 +248,8 @@ RESTORE_LOCAL ENTRY(ret_from_interrupt) - moveb %sp@(PT_SR),%d0 - andl #0x7,%d0 - jeq 1f - - RESTORE_ALL - -1: - /* check if we need to do software interrupts */ - movel irq_stat+CPUSTAT_SOFTIRQ_PENDING,%d0 - jeq ret_from_exception - - pea ret_from_exception - jmp do_softirq + /* the fasthandler is confusing me, haven't seen any user */ + jmp ret_from_exception /* * Beware - when entering resume, prev (the current task) is diff -urN linux-2.6.26/arch/m68knommu/platform/coldfire/irq_chip.c linux-2.6.26-lab126/arch/m68knommu/platform/coldfire/irq_chip.c --- linux-2.6.26/arch/m68knommu/platform/coldfire/irq_chip.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/m68knommu/platform/coldfire/irq_chip.c 2010-08-10 04:14:47.000000000 -0400 @@ -0,0 +1,110 @@ +/* + * IRQ-Chip implementation for Coldfire + * + * Author: Sebastian Siewior + */ + +#include +#include +#include +#include + +static inline void *coldfire_irqnum_to_mem(unsigned int irq) +{ + u32 imrp; + + imrp = MCF_IPSBAR; +#if defined(MCFINT_INTC1_VECBASE) + if (irq > MCFINT_INTC1_VECBASE) { + imrp += MCFICM_INTC1; + irq -= MCFINT_PER_INTC; + } else +#endif + imrp += MCFICM_INTC0; + + irq -= MCFINT_VECBASE; + + if (irq > 32) + imrp += MCFINTC_IMRH; + else + imrp += MCFINTC_IMRL; + + return (void *)imrp; +} + +static inline unsigned int coldfire_irqnum_to_bit(unsigned int irq) +{ + irq -= MCFINT_VECBASE; + + if (irq > 32) + irq -= 32; + + return irq; +} + +static void coldfire_mask(unsigned int irq) +{ + volatile unsigned long *imrp; + u32 mask; + u32 irq_bit; + + imrp = coldfire_irqnum_to_mem(irq); + irq_bit = coldfire_irqnum_to_bit(irq); + + mask = 1 << irq_bit; + *imrp |= mask; +} + +static void coldfire_unmask(unsigned int irq) +{ + volatile unsigned long *imrp; + u32 mask; + u32 irq_bit; + + imrp = coldfire_irqnum_to_mem(irq); + irq_bit = coldfire_irqnum_to_bit(irq); + + mask = 1 << irq_bit; + *imrp &= ~mask; +} + +static void coldfire_nop(unsigned int irq) +{ +} + +static struct irq_chip m_irq_chip = { + .name = "M68K-INTC", + .ack = coldfire_nop, + .mask = coldfire_mask, + .unmask = coldfire_unmask, +}; + +void __init coldfire_init_irq_chip(void) +{ + volatile u32 *imrp; + volatile u8 *icrp; + u32 irq; + u32 i; + + for (irq = 0; irq < NR_IRQS; irq++) + set_irq_chip_and_handler_name(irq, &m_irq_chip, + handle_level_irq, m_irq_chip.name); + + /* setup prios for interrupt sources (first field is reserved) */ + icrp = (u8 *)MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0; + for (i = 1; i <= 63; i++) + icrp[i] = i; + + /* remove the disable all flag, disable all interrupt sources */ + imrp = coldfire_irqnum_to_mem(MCFINT_VECBASE); + *imrp = 0xfffffffe; + +#if defined(MCFINT_INTC1_VECBASE) + icrp = (u8 *)MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_ICR0; + for (i = 1; i <= 63; i++) + icrp[i] = i; + + imrp = coldfire_irqnum_to_mem(MCFINT_INTC1_VECBASE); + *imrp = 0xfffffffe; +#endif +} diff -urN linux-2.6.26/arch/m68knommu/platform/coldfire/pit.c linux-2.6.26-lab126/arch/m68knommu/platform/coldfire/pit.c --- linux-2.6.26/arch/m68knommu/platform/coldfire/pit.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/m68knommu/platform/coldfire/pit.c 2010-08-10 04:14:47.000000000 -0400 @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include @@ -33,29 +33,93 @@ #define FREQ ((MCF_CLK / 2) / 64) #define TA(a) (MCF_IPSBAR + MCFPIT_BASE1 + (a)) #define INTC0 (MCF_IPSBAR + MCFICM_INTC0) +#define PIT_CYCLES_PER_JIFFY (FREQ / HZ) -static u32 pit_cycles_per_jiffy; static u32 pit_cnt; +/* + * Initialize the PIT timer. + * + * This is also called after resume to bring the PIT into operation again. + */ + +static void init_cf_pit_timer(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + + __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); + __raw_writew(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR)); + __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | \ + MCFPIT_PCSR_OVW | MCFPIT_PCSR_RLD | \ + MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR)); + break; + + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + + __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); + break; + + case CLOCK_EVT_MODE_ONESHOT: + + __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); + __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | \ + MCFPIT_PCSR_OVW | MCFPIT_PCSR_CLK64, \ + TA(MCFPIT_PCSR)); + break; + + case CLOCK_EVT_MODE_RESUME: + /* Nothing to do here */ + break; + } +} + +/* + * Program the next event in oneshot mode + * + * Delta is given in PIT ticks + */ +static int cf_pit_next_event(unsigned long delta, + struct clock_event_device *evt) +{ + __raw_writew(delta, TA(MCFPIT_PMR)); + return 0; +} + +struct clock_event_device cf_pit_clockevent = { + .name = "pit", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = init_cf_pit_timer, + .set_next_event = cf_pit_next_event, + .shift = 32, + .irq = MCFINT_VECBASE + MCFINT_PIT1, +}; + + + /***************************************************************************/ static irqreturn_t pit_tick(int irq, void *dummy) { + struct clock_event_device *evt = &cf_pit_clockevent; u16 pcsr; /* Reset the ColdFire timer */ pcsr = __raw_readw(TA(MCFPIT_PCSR)); __raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR)); - pit_cnt += pit_cycles_per_jiffy; - return arch_timer_interrupt(irq, dummy); + pit_cnt += PIT_CYCLES_PER_JIFFY; + evt->event_handler(evt); + return IRQ_HANDLED; } /***************************************************************************/ static struct irqaction pit_irq = { .name = "timer", - .flags = IRQF_DISABLED | IRQF_TIMER, + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_NODELAY, .handler = pit_tick, }; @@ -72,14 +136,14 @@ cycles = pit_cnt; local_irq_restore(flags); - return cycles + pit_cycles_per_jiffy - pcntr; + return cycles + PIT_CYCLES_PER_JIFFY - pcntr; } /***************************************************************************/ static struct clocksource pit_clk = { .name = "pit", - .rating = 250, + .rating = 100, .read = pit_read_clk, .shift = 20, .mask = CLOCKSOURCE_MASK(32), @@ -92,20 +156,23 @@ { u32 imr; + cf_pit_clockevent.cpumask = cpumask_of_cpu(smp_processor_id()); + cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32); + cf_pit_clockevent.max_delta_ns = + clockevent_delta2ns(0xFFFF, &cf_pit_clockevent); + cf_pit_clockevent.min_delta_ns = + clockevent_delta2ns(0x3f, &cf_pit_clockevent); + clockevents_register_device(&cf_pit_clockevent); + setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq); +#if !defined(CONFIG_M523x) __raw_writeb(ICR_INTRCONF, INTC0 + MCFINTC_ICR0 + MCFINT_PIT1); imr = __raw_readl(INTC0 + MCFPIT_IMR); imr &= ~MCFPIT_IMR_IBIT; __raw_writel(imr, INTC0 + MCFPIT_IMR); - /* Set up PIT timer 1 as poll clock */ - pit_cycles_per_jiffy = FREQ / HZ; - __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); - __raw_writew(pit_cycles_per_jiffy, TA(MCFPIT_PMR)); - __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | MCFPIT_PCSR_OVW | - MCFPIT_PCSR_RLD | MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR)); - +#endif pit_clk.mult = clocksource_hz2mult(FREQ, pit_clk.shift); clocksource_register(&pit_clk); } diff -urN linux-2.6.26/arch/mips/Kconfig linux-2.6.26-lab126/arch/mips/Kconfig --- linux-2.6.26/arch/mips/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/Kconfig 2010-08-10 04:15:04.000000000 -0400 @@ -44,6 +44,7 @@ select CEVT_R4K select CSRC_R4K select DMA_NONCOHERENT + select NO_SPINLOCK select HW_HAS_PCI select IRQ_CPU select SYS_HAS_CPU_MIPS32_R1 @@ -712,6 +713,10 @@ config RWSEM_XCHGADD_ALGORITHM bool +config ASM_SEMAPHORES + bool + default y + config ARCH_HAS_ILOG2_U32 bool default n @@ -819,6 +824,9 @@ config DMA_NEED_PCI_MAP_STATE bool +config NO_SPINLOCK + bool + config EARLY_PRINTK bool "Early printk" if EMBEDDED && DEBUG_KERNEL depends on SYS_HAS_EARLY_PRINTK @@ -1843,8 +1851,6 @@ This is a placeholder option for the GCMP work. It will need to be handled differently... -source "kernel/time/Kconfig" - # # Timer Interrupt Frequency Configuration # @@ -1962,12 +1968,17 @@ If unsure, say Y. Only embedded should say N here. -endmenu - -config RWSEM_GENERIC_SPINLOCK +config GENERIC_TIME bool default y +source "kernel/time/Kconfig" + +config CPU_SPEED + int "CPU speed used for clocksource/clockevent calculations" + default 600 +endmenu + config LOCKDEP_SUPPORT bool default y diff -urN linux-2.6.26/arch/mips/boot/.gitignore linux-2.6.26-lab126/arch/mips/boot/.gitignore --- linux-2.6.26/arch/mips/boot/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/boot/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,4 +0,0 @@ -mkboot -elf2ecoff -zImage -zImage.tmp diff -urN linux-2.6.26/arch/mips/kernel/asm-offsets.c linux-2.6.26-lab126/arch/mips/kernel/asm-offsets.c --- linux-2.6.26/arch/mips/kernel/asm-offsets.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/kernel/asm-offsets.c 2010-08-10 04:14:57.000000000 -0400 @@ -10,10 +10,13 @@ */ #include #include +#include #include #include #include #include +#include + #include #include diff -urN linux-2.6.26/arch/mips/kernel/entry.S linux-2.6.26-lab126/arch/mips/kernel/entry.S --- linux-2.6.26/arch/mips/kernel/entry.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/kernel/entry.S 2010-08-10 04:14:57.000000000 -0400 @@ -30,7 +30,7 @@ .align 5 #ifndef CONFIG_PREEMPT FEXPORT(ret_from_exception) - local_irq_disable # preempt stop + raw_local_irq_disable # preempt stop b __ret_from_irq #endif FEXPORT(ret_from_irq) @@ -41,7 +41,7 @@ beqz t0, resume_kernel resume_userspace: - local_irq_disable # make sure we dont miss an + raw_local_irq_disable # make sure we dont miss an # interrupt setting need_resched # between sampling and return LONG_L a2, TI_FLAGS($28) # current->work @@ -51,7 +51,9 @@ #ifdef CONFIG_PREEMPT resume_kernel: - local_irq_disable + raw_local_irq_disable + lw t0, kernel_preemption + beqz t0, restore_all lw t0, TI_PRE_COUNT($28) bnez t0, restore_all need_resched: @@ -61,7 +63,9 @@ LONG_L t0, PT_STATUS(sp) # Interrupts off? andi t0, 1 beqz t0, restore_all + raw_local_irq_disable jal preempt_schedule_irq + sw zero, TI_PRE_COUNT($28) b need_resched #endif @@ -69,7 +73,7 @@ jal schedule_tail # a0 = struct task_struct *prev FEXPORT(syscall_exit) - local_irq_disable # make sure need_resched and + raw_local_irq_disable # make sure need_resched and # signals dont change between # sampling and return LONG_L a2, TI_FLAGS($28) # current->work @@ -142,12 +146,14 @@ .set at work_pending: - andi t0, a2, _TIF_NEED_RESCHED # a2 is preloaded with TI_FLAGS + # a2 is preloaded with TI_FLAGS + andi t0, a2, _TIF_NEED_RESCHED beqz t0, work_notifysig work_resched: + raw_local_irq_enable t0 jal schedule - local_irq_disable # make sure need_resched and + raw_local_irq_disable # make sure need_resched and # signals dont change between # sampling and return LONG_L a2, TI_FLAGS($28) @@ -170,7 +176,7 @@ li t0, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT and t0, a2 # a2 is preloaded with TI_FLAGS beqz t0, work_pending # trace bit set? - local_irq_enable # could let do_syscall_trace() + raw_local_irq_enable # could let do_syscall_trace() # call schedule() instead move a0, sp li a1, 1 diff -urN linux-2.6.26/arch/mips/kernel/gdb-stub.c linux-2.6.26-lab126/arch/mips/kernel/gdb-stub.c --- linux-2.6.26/arch/mips/kernel/gdb-stub.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/kernel/gdb-stub.c 2010-08-10 04:14:57.000000000 -0400 @@ -176,7 +176,7 @@ * spin locks for smp case */ static DEFINE_SPINLOCK(kgdb_lock); -static raw_spinlock_t kgdb_cpulock[NR_CPUS] = { +static __raw_spinlock_t kgdb_cpulock[NR_CPUS] = { [0 ... NR_CPUS-1] = __RAW_SPIN_LOCK_UNLOCKED, }; diff -urN linux-2.6.26/arch/mips/kernel/i8253.c linux-2.6.26-lab126/arch/mips/kernel/i8253.c --- linux-2.6.26/arch/mips/kernel/i8253.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/kernel/i8253.c 2010-08-10 04:14:57.000000000 -0400 @@ -97,7 +97,7 @@ static struct irqaction irq0 = { .handler = timer_interrupt, - .flags = IRQF_DISABLED | IRQF_NOBALANCING, + .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_NODELAY, .mask = CPU_MASK_NONE, .name = "timer" }; diff -urN linux-2.6.26/arch/mips/kernel/i8259.c linux-2.6.26-lab126/arch/mips/kernel/i8259.c --- linux-2.6.26/arch/mips/kernel/i8259.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/kernel/i8259.c 2010-08-10 04:14:57.000000000 -0400 @@ -29,7 +29,7 @@ */ static int i8259A_auto_eoi = -1; -DEFINE_SPINLOCK(i8259A_lock); +DEFINE_RAW_SPINLOCK(i8259A_lock); static void disable_8259A_irq(unsigned int irq); static void enable_8259A_irq(unsigned int irq); static void mask_and_ack_8259A(unsigned int irq); diff -urN linux-2.6.26/arch/mips/kernel/module.c linux-2.6.26-lab126/arch/mips/kernel/module.c --- linux-2.6.26/arch/mips/kernel/module.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/kernel/module.c 2010-08-10 04:14:57.000000000 -0400 @@ -40,7 +40,7 @@ static struct mips_hi16 *mips_hi16_list; static LIST_HEAD(dbe_list); -static DEFINE_SPINLOCK(dbe_lock); +static DEFINE_RAW_SPINLOCK(dbe_lock); void *module_alloc(unsigned long size) { diff -urN linux-2.6.26/arch/mips/kernel/process.c linux-2.6.26-lab126/arch/mips/kernel/process.c --- linux-2.6.26/arch/mips/kernel/process.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/kernel/process.c 2010-08-10 04:14:57.000000000 -0400 @@ -53,7 +53,7 @@ { /* endless idle loop with no priority at all */ while (1) { - tick_nohz_stop_sched_tick(); + tick_nohz_stop_sched_tick(1); while (!need_resched()) { #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG extern void smtc_idle_loop_hook(void); diff -urN linux-2.6.26/arch/mips/kernel/scall32-o32.S linux-2.6.26-lab126/arch/mips/kernel/scall32-o32.S --- linux-2.6.26/arch/mips/kernel/scall32-o32.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/kernel/scall32-o32.S 2010-08-10 04:14:57.000000000 -0400 @@ -73,7 +73,7 @@ 1: sw v0, PT_R2(sp) # result o32_syscall_exit: - local_irq_disable # make sure need_resched and + raw_local_irq_disable # make sure need_resched and # signals dont change between # sampling and return lw a2, TI_FLAGS($28) # current->work diff -urN linux-2.6.26/arch/mips/kernel/scall64-64.S linux-2.6.26-lab126/arch/mips/kernel/scall64-64.S --- linux-2.6.26/arch/mips/kernel/scall64-64.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/kernel/scall64-64.S 2010-08-10 04:14:57.000000000 -0400 @@ -72,7 +72,7 @@ 1: sd v0, PT_R2(sp) # result n64_syscall_exit: - local_irq_disable # make sure need_resched and + raw_local_irq_disable # make sure need_resched and # signals dont change between # sampling and return LONG_L a2, TI_FLAGS($28) # current->work diff -urN linux-2.6.26/arch/mips/kernel/scall64-n32.S linux-2.6.26-lab126/arch/mips/kernel/scall64-n32.S --- linux-2.6.26/arch/mips/kernel/scall64-n32.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/kernel/scall64-n32.S 2010-08-10 04:14:57.000000000 -0400 @@ -69,7 +69,7 @@ sd v0, PT_R0(sp) # set flag for syscall restarting 1: sd v0, PT_R2(sp) # result - local_irq_disable # make sure need_resched and + raw_local_irq_disable # make sure need_resched and # signals dont change between # sampling and return LONG_L a2, TI_FLAGS($28) # current->work diff -urN linux-2.6.26/arch/mips/kernel/scall64-o32.S linux-2.6.26-lab126/arch/mips/kernel/scall64-o32.S --- linux-2.6.26/arch/mips/kernel/scall64-o32.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/kernel/scall64-o32.S 2010-08-10 04:14:57.000000000 -0400 @@ -98,7 +98,7 @@ 1: sd v0, PT_R2(sp) # result o32_syscall_exit: - local_irq_disable # make need_resched and + raw_local_irq_disable # make need_resched and # signals dont change between # sampling and return LONG_L a2, TI_FLAGS($28) diff -urN linux-2.6.26/arch/mips/kernel/signal.c linux-2.6.26-lab126/arch/mips/kernel/signal.c --- linux-2.6.26/arch/mips/kernel/signal.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/kernel/signal.c 2010-08-10 04:14:57.000000000 -0400 @@ -629,6 +629,10 @@ siginfo_t info; int signr; +#ifdef CONFIG_PREEMPT_RT + local_irq_enable(); + preempt_check_resched(); +#endif /* * We want the common case to go fast, which is why we may in certain * cases get here from kernel mode. Just return without doing anything diff -urN linux-2.6.26/arch/mips/kernel/signal32.c linux-2.6.26-lab126/arch/mips/kernel/signal32.c --- linux-2.6.26/arch/mips/kernel/signal32.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/kernel/signal32.c 2010-08-10 04:14:57.000000000 -0400 @@ -655,6 +655,10 @@ if (err) goto give_sigsegv; +#ifdef CONFIG_PREEMPT_RT + local_irq_enable(); + preempt_check_resched(); +#endif /* * Arguments to signal handler: * diff -urN linux-2.6.26/arch/mips/kernel/smp.c linux-2.6.26-lab126/arch/mips/kernel/smp.c --- linux-2.6.26/arch/mips/kernel/smp.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/kernel/smp.c 2010-08-10 04:14:57.000000000 -0400 @@ -131,7 +131,22 @@ cpu_idle(); } -DEFINE_SPINLOCK(smp_call_lock); +DEFINE_RAW_SPINLOCK(smp_call_lock); + +/* + * this function sends a 'reschedule' IPI to all other CPUs. + * This is used when RT tasks are starving and other CPUs + * might be able to run them. + */ +void smp_send_reschedule_allbutself(void) +{ + int cpu = smp_processor_id(); + int i; + + for (i = 0; i < NR_CPUS; i++) + if (cpu_online(i) && i != cpu) + core_send_ipi(i, SMP_RESCHEDULE_YOURSELF); +} struct call_data_struct *call_data; @@ -358,6 +373,8 @@ return 0; } +static DEFINE_RAW_SPINLOCK(tlbstate_lock); + static void flush_tlb_all_ipi(void *info) { local_flush_tlb_all(); @@ -415,6 +432,7 @@ void flush_tlb_mm(struct mm_struct *mm) { preempt_disable(); + spin_lock(&tlbstate_lock); if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { smp_on_other_tlbs(flush_tlb_mm_ipi, mm); @@ -427,6 +445,7 @@ if (cpu_context(cpu, mm)) cpu_context(cpu, mm) = 0; } + spin_unlock(&tlbstate_lock); local_flush_tlb_mm(mm); preempt_enable(); @@ -450,6 +469,8 @@ struct mm_struct *mm = vma->vm_mm; preempt_disable(); + spin_lock(&tlbstate_lock); + if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { struct flush_tlb_data fd = { .vma = vma, @@ -467,6 +488,7 @@ if (cpu_context(cpu, mm)) cpu_context(cpu, mm) = 0; } + spin_unlock(&tlbstate_lock); local_flush_tlb_range(vma, start, end); preempt_enable(); } @@ -498,6 +520,8 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) { preempt_disable(); + spin_lock(&tlbstate_lock); + if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) { struct flush_tlb_data fd = { .vma = vma, @@ -514,6 +538,7 @@ if (cpu_context(cpu, vma->vm_mm)) cpu_context(cpu, vma->vm_mm) = 0; } + spin_unlock(&tlbstate_lock); local_flush_tlb_page(vma, page); preempt_enable(); } diff -urN linux-2.6.26/arch/mips/kernel/traps.c linux-2.6.26-lab126/arch/mips/kernel/traps.c --- linux-2.6.26/arch/mips/kernel/traps.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/kernel/traps.c 2010-08-10 04:14:57.000000000 -0400 @@ -340,7 +340,7 @@ printk("\n"); } -static DEFINE_SPINLOCK(die_lock); +static DEFINE_RAW_SPINLOCK(die_lock); void __noreturn die(const char * str, const struct pt_regs * regs) { diff -urN linux-2.6.26/arch/mips/mm/fault.c linux-2.6.26-lab126/arch/mips/mm/fault.c --- linux-2.6.26/arch/mips/mm/fault.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/mm/fault.c 2010-08-10 04:15:04.000000000 -0400 @@ -69,7 +69,7 @@ * If we're in an interrupt or have no user * context, we must not take the fault.. */ - if (in_atomic() || !mm) + if (in_atomic() || !mm || current->pagefault_disabled) goto bad_area_nosemaphore; down_read(&mm->mmap_sem); diff -urN linux-2.6.26/arch/mips/mm/highmem.c linux-2.6.26-lab126/arch/mips/mm/highmem.c --- linux-2.6.26/arch/mips/mm/highmem.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/mm/highmem.c 2010-08-10 04:15:04.000000000 -0400 @@ -38,7 +38,7 @@ enum fixed_addresses idx; unsigned long vaddr; - /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */ + preempt_disable(); pagefault_disable(); if (!PageHighMem(page)) return page_address(page); @@ -63,6 +63,7 @@ if (vaddr < FIXADDR_START) { // FIXME pagefault_enable(); + preempt_enable(); return; } @@ -78,6 +79,7 @@ #endif pagefault_enable(); + preempt_enable(); } /* @@ -89,6 +91,7 @@ enum fixed_addresses idx; unsigned long vaddr; + preempt_disable(); pagefault_disable(); idx = type + KM_TYPE_NR*smp_processor_id(); diff -urN linux-2.6.26/arch/mips/mm/init.c linux-2.6.26-lab126/arch/mips/mm/init.c --- linux-2.6.26/arch/mips/mm/init.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/mm/init.c 2010-08-10 04:15:04.000000000 -0400 @@ -61,7 +61,7 @@ #endif /* CONFIG_MIPS_MT_SMTC */ -DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); +DEFINE_PER_CPU_LOCKED(struct mmu_gather, mmu_gathers); /* * We have up to 8 empty zeroed pages so we can map one of the right colour diff -urN linux-2.6.26/arch/mips/sibyte/sb1250/irq.c linux-2.6.26-lab126/arch/mips/sibyte/sb1250/irq.c --- linux-2.6.26/arch/mips/sibyte/sb1250/irq.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/sibyte/sb1250/irq.c 2010-08-10 04:15:03.000000000 -0400 @@ -82,7 +82,7 @@ /* Store the CPU id (not the logical number) */ int sb1250_irq_owner[SB1250_NR_IRQS]; -DEFINE_SPINLOCK(sb1250_imr_lock); +DEFINE_RAW_SPINLOCK(sb1250_imr_lock); void sb1250_mask_irq(int cpu, int irq) { @@ -316,6 +316,10 @@ #ifdef CONFIG_KGDB imask |= STATUSF_IP6; #endif + +#ifdef CONFIG_HIGH_RES_TIMERS + imask |= STATUSF_IP7; +#endif /* Enable necessary IPs, disable the rest */ change_c0_status(ST0_IM, imask); diff -urN linux-2.6.26/arch/mips/sibyte/sb1250/smp.c linux-2.6.26-lab126/arch/mips/sibyte/sb1250/smp.c --- linux-2.6.26/arch/mips/sibyte/sb1250/smp.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/sibyte/sb1250/smp.c 2010-08-10 04:15:03.000000000 -0400 @@ -97,7 +97,7 @@ extern void sb1250_clockevent_init(void); sb1250_clockevent_init(); - local_irq_enable(); + raw_local_irq_enable(); } /* diff -urN linux-2.6.26/arch/mips/sibyte/swarm/setup.c linux-2.6.26-lab126/arch/mips/sibyte/swarm/setup.c --- linux-2.6.26/arch/mips/sibyte/swarm/setup.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mips/sibyte/swarm/setup.c 2010-08-10 04:15:03.000000000 -0400 @@ -136,6 +136,12 @@ if (m41t81_probe()) swarm_rtc_type = RTC_M4LT81; +#ifdef CONFIG_HIGH_RES_TIMERS + /* + * set the mips_hpt_frequency here + */ + mips_hpt_frequency = CONFIG_CPU_SPEED * 1000000; +#endif printk("This kernel optimized for " #ifdef CONFIG_SIMULATION "simulation" diff -urN linux-2.6.26/arch/mn10300/Kconfig linux-2.6.26-lab126/arch/mn10300/Kconfig --- linux-2.6.26/arch/mn10300/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mn10300/Kconfig 2010-08-10 04:14:42.000000000 -0400 @@ -186,6 +186,17 @@ Say Y here if you are building a kernel for a desktop, embedded or real-time system. Say N if you are unsure. +config PREEMPT_BKL + bool "Preempt The Big Kernel Lock" + depends on PREEMPT + default y + help + This option reduces the latency of the kernel by making the + big kernel lock preemptible. + + Say Y here if you are building a kernel for a desktop system. + Say N if you are unsure. + config MN10300_CURRENT_IN_E2 bool "Hold current task address in E2 register" default y diff -urN linux-2.6.26/arch/mn10300/boot/.gitignore linux-2.6.26-lab126/arch/mn10300/boot/.gitignore --- linux-2.6.26/arch/mn10300/boot/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/mn10300/boot/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1 +0,0 @@ -zImage diff -urN linux-2.6.26/arch/powerpc/.gitignore linux-2.6.26-lab126/arch/powerpc/.gitignore --- linux-2.6.26/arch/powerpc/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1 +0,0 @@ -include diff -urN linux-2.6.26/arch/powerpc/Kconfig linux-2.6.26-lab126/arch/powerpc/Kconfig --- linux-2.6.26/arch/powerpc/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/Kconfig 2010-08-10 04:14:02.000000000 -0400 @@ -62,13 +62,6 @@ bool default y -config RWSEM_GENERIC_SPINLOCK - bool - -config RWSEM_XCHGADD_ALGORITHM - bool - default y - config GENERIC_LOCKBREAK bool default y @@ -105,11 +98,13 @@ config PPC bool default y + select HAVE_DYNAMIC_FTRACE + select HAVE_FTRACE select HAVE_IDE - select HAVE_OPROFILE select HAVE_KPROBES select HAVE_KRETPROBES select HAVE_LMB + select HAVE_OPROFILE config EARLY_PRINTK bool @@ -227,6 +222,14 @@ source kernel/time/Kconfig source kernel/Kconfig.hz source kernel/Kconfig.preempt + +config RWSEM_GENERIC_SPINLOCK + bool + default y + +config RWSEM_XCHGADD_ALGORITHM + bool + source "fs/Kconfig.binfmt" config HUGETLB_PAGE_SIZE_VARIABLE diff -urN linux-2.6.26/arch/powerpc/Kconfig.debug linux-2.6.26-lab126/arch/powerpc/Kconfig.debug --- linux-2.6.26/arch/powerpc/Kconfig.debug 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/Kconfig.debug 2010-08-10 04:14:02.000000000 -0400 @@ -2,6 +2,10 @@ source "lib/Kconfig.debug" +config TRACE_IRQFLAGS_SUPPORT + bool + default y + config DEBUG_STACKOVERFLOW bool "Check for stack overflows" depends on DEBUG_KERNEL diff -urN linux-2.6.26/arch/powerpc/boot/.gitignore linux-2.6.26-lab126/arch/powerpc/boot/.gitignore --- linux-2.6.26/arch/powerpc/boot/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/boot/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,38 +0,0 @@ -addnote -dtc -empty.c -hack-coff -infblock.c -infblock.h -infcodes.c -infcodes.h -inffast.c -inffast.h -inffixed.h -inflate.c -inflate.h -inftrees.c -inftrees.h -infutil.c -infutil.h -kernel-vmlinux.strip.c -kernel-vmlinux.strip.gz -mktree -uImage -cuImage.* -dtbImage.* -treeImage.* -zImage -zImage.initrd -zImage.bin.* -zImage.chrp -zImage.coff -zImage.holly -zImage.iseries -zImage.*lds -zImage.miboot -zImage.pmac -zImage.pseries -zconf.h -zlib.h -zutil.h diff -urN linux-2.6.26/arch/powerpc/boot/dtc-src/.gitignore linux-2.6.26-lab126/arch/powerpc/boot/dtc-src/.gitignore --- linux-2.6.26/arch/powerpc/boot/dtc-src/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/boot/dtc-src/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,3 +0,0 @@ -dtc-lexer.lex.c -dtc-parser.tab.c -dtc-parser.tab.h diff -urN linux-2.6.26/arch/powerpc/kernel/Makefile linux-2.6.26-lab126/arch/powerpc/kernel/Makefile --- linux-2.6.26/arch/powerpc/kernel/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/kernel/Makefile 2010-08-10 04:13:54.000000000 -0400 @@ -12,6 +12,17 @@ CFLAGS_btext.o += -fPIC endif +ifdef CONFIG_FTRACE +# Do not trace early boot code +CFLAGS_REMOVE_cputable.o = -pg -mno-sched-epilog +CFLAGS_REMOVE_prom_init.o = -pg -mno-sched-epilog +CFLAGS_REMOVE_btext.o = -pg -mno-sched-epilog + +# dynamic ftrace setup. +CFLAGS_REMOVE_ftrace.o = -pg -mno-sched-epilog + +endif + obj-y := cputable.o ptrace.o syscalls.o \ irq.o align.o signal_32.o pmc.o vdso.o \ init_task.o process.o systbl.o idle.o \ @@ -78,6 +89,8 @@ obj-$(CONFIG_AUDIT) += audit.o obj64-$(CONFIG_AUDIT) += compat_audit.o +obj-$(CONFIG_FTRACE) += ftrace.o + obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o ifneq ($(CONFIG_PPC_INDIRECT_IO),y) diff -urN linux-2.6.26/arch/powerpc/kernel/cputable.c linux-2.6.26-lab126/arch/powerpc/kernel/cputable.c --- linux-2.6.26/arch/powerpc/kernel/cputable.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/kernel/cputable.c 2010-08-10 04:13:54.000000000 -0400 @@ -1541,7 +1541,7 @@ static struct cpu_spec the_cpu_spec; -struct cpu_spec * __init identify_cpu(unsigned long offset, unsigned int pvr) +notrace struct cpu_spec * __init identify_cpu(unsigned long offset, unsigned int pvr) { struct cpu_spec *s = cpu_specs; struct cpu_spec *t = &the_cpu_spec; @@ -1588,7 +1588,7 @@ return NULL; } -void do_feature_fixups(unsigned long value, void *fixup_start, void *fixup_end) +notrace void do_feature_fixups(unsigned long value, void *fixup_start, void *fixup_end) { struct fixup_entry { unsigned long mask; diff -urN linux-2.6.26/arch/powerpc/kernel/entry_32.S linux-2.6.26-lab126/arch/powerpc/kernel/entry_32.S --- linux-2.6.26/arch/powerpc/kernel/entry_32.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/kernel/entry_32.S 2010-08-10 04:13:54.000000000 -0400 @@ -30,6 +30,7 @@ #include #include #include +#include #undef SHOW_SYSCALLS #undef SHOW_SYSCALLS_TASK @@ -909,7 +910,7 @@ #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */ do_work: /* r10 contains MSR_KERNEL here */ - andi. r0,r9,_TIF_NEED_RESCHED + andi. r0,r9,(_TIF_NEED_RESCHED) beq do_user_signal do_resched: /* r10 contains MSR_KERNEL here */ @@ -923,7 +924,7 @@ MTMSRD(r10) /* disable interrupts */ rlwinm r9,r1,0,0,(31-THREAD_SHIFT) lwz r9,TI_FLAGS(r9) - andi. r0,r9,_TIF_NEED_RESCHED + andi. r0,r9,(_TIF_NEED_RESCHED) bne- do_resched andi. r0,r9,_TIF_SIGPENDING|_TIF_RESTORE_SIGMASK beq restore_user @@ -1035,3 +1036,129 @@ /* XXX load up BATs and panic */ #endif /* CONFIG_PPC_RTAS */ + +#ifdef CONFIG_FTRACE +#ifdef CONFIG_DYNAMIC_FTRACE +_GLOBAL(mcount) +_GLOBAL(_mcount) + stwu r1,-48(r1) + stw r3, 12(r1) + stw r4, 16(r1) + stw r5, 20(r1) + stw r6, 24(r1) + mflr r3 + stw r7, 28(r1) + mfcr r5 + stw r8, 32(r1) + stw r9, 36(r1) + stw r10,40(r1) + stw r3, 44(r1) + stw r5, 8(r1) + subi r3, r3, MCOUNT_INSN_SIZE + .globl mcount_call +mcount_call: + bl ftrace_stub + nop + lwz r6, 8(r1) + lwz r0, 44(r1) + lwz r3, 12(r1) + mtctr r0 + lwz r4, 16(r1) + mtcr r6 + lwz r5, 20(r1) + lwz r6, 24(r1) + lwz r0, 52(r1) + lwz r7, 28(r1) + lwz r8, 32(r1) + mtlr r0 + lwz r9, 36(r1) + lwz r10,40(r1) + addi r1, r1, 48 + bctr + +_GLOBAL(ftrace_caller) + /* Based off of objdump optput from glibc */ + stwu r1,-48(r1) + stw r3, 12(r1) + stw r4, 16(r1) + stw r5, 20(r1) + stw r6, 24(r1) + mflr r3 + lwz r4, 52(r1) + mfcr r5 + stw r7, 28(r1) + stw r8, 32(r1) + stw r9, 36(r1) + stw r10,40(r1) + stw r3, 44(r1) + stw r5, 8(r1) + subi r3, r3, MCOUNT_INSN_SIZE +.globl ftrace_call +ftrace_call: + bl ftrace_stub + nop + lwz r6, 8(r1) + lwz r0, 44(r1) + lwz r3, 12(r1) + mtctr r0 + lwz r4, 16(r1) + mtcr r6 + lwz r5, 20(r1) + lwz r6, 24(r1) + lwz r0, 52(r1) + lwz r7, 28(r1) + lwz r8, 32(r1) + mtlr r0 + lwz r9, 36(r1) + lwz r10,40(r1) + addi r1, r1, 48 + bctr +#else +_GLOBAL(mcount) +_GLOBAL(_mcount) + stwu r1,-48(r1) + stw r3, 12(r1) + stw r4, 16(r1) + stw r5, 20(r1) + stw r6, 24(r1) + mflr r3 + lwz r4, 52(r1) + mfcr r5 + stw r7, 28(r1) + stw r8, 32(r1) + stw r9, 36(r1) + stw r10,40(r1) + stw r3, 44(r1) + stw r5, 8(r1) + + subi r3, r3, MCOUNT_INSN_SIZE + LOAD_REG_ADDR(r5, ftrace_trace_function) + lwz r5,0(r5) + + mtctr r5 + bctrl + + nop + + lwz r6, 8(r1) + lwz r0, 44(r1) + lwz r3, 12(r1) + mtctr r0 + lwz r4, 16(r1) + mtcr r6 + lwz r5, 20(r1) + lwz r6, 24(r1) + lwz r0, 52(r1) + lwz r7, 28(r1) + lwz r8, 32(r1) + mtlr r0 + lwz r9, 36(r1) + lwz r10,40(r1) + addi r1, r1, 48 + bctr +#endif + +_GLOBAL(ftrace_stub) + blr + +#endif /* CONFIG_MCOUNT */ diff -urN linux-2.6.26/arch/powerpc/kernel/entry_64.S linux-2.6.26-lab126/arch/powerpc/kernel/entry_64.S --- linux-2.6.26/arch/powerpc/kernel/entry_64.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/kernel/entry_64.S 2010-08-10 04:13:54.000000000 -0400 @@ -31,6 +31,7 @@ #include #include #include +#include /* * System calls. @@ -594,44 +595,52 @@ bne restore /* here we are preempting the current task */ 1: + /* + * preempt_schedule_irq() expects interrupts disabled and returns + * with interrupts disabled. No need to check preemption again, + * preempt_schedule_irq just did that for us. + */ + bl .preempt_schedule_irq #ifdef CONFIG_TRACE_IRQFLAGS bl .trace_hardirqs_on +#endif /* CONFIG_TRACE_IRQFLAGS */ + /* Note: we just clobbered r10 which used to contain the previous * MSR before the hard-disabling done by the caller of do_work. * We don't have that value anymore, but it doesn't matter as * we will hard-enable unconditionally, we can just reload the * current MSR into r10 */ + bl .preempt_schedule_irq mfmsr r10 -#endif /* CONFIG_TRACE_IRQFLAGS */ - li r0,1 - stb r0,PACASOFTIRQEN(r13) - stb r0,PACAHARDIRQEN(r13) - ori r10,r10,MSR_EE - mtmsrd r10,1 /* reenable interrupts */ - bl .preempt_schedule - mfmsr r10 - clrrdi r9,r1,THREAD_SHIFT - rldicl r10,r10,48,1 /* disable interrupts again */ - rotldi r10,r10,16 - mtmsrd r10,1 - ld r4,TI_FLAGS(r9) - andi. r0,r4,_TIF_NEED_RESCHED - bne 1b + clrrdi r9,r1,THREAD_SHIFT + rldicl r10,r10,48,1 /* disable interrupts again */ + rotldi r10,r10,16 + mtmsrd r10,1 + ld r4,TI_FLAGS(r9) + andi. r0,r4,(_TIF_NEED_RESCHED) + bne 1b b restore user_work: #endif - /* Enable interrupts */ - ori r10,r10,MSR_EE - mtmsrd r10,1 - andi. r0,r4,_TIF_NEED_RESCHED beq 1f - bl .schedule + + /* preempt_schedule_irq() expects interrupts disabled. */ + bl .preempt_schedule_irq b .ret_from_except_lite -1: bl .save_nvgprs + /* here we are preempting the current task */ +1: li r0,1 + stb r0,PACASOFTIRQEN(r13) + stb r0,PACAHARDIRQEN(r13) + + /* Enable interrupts */ + ori r10,r10,MSR_EE + mtmsrd r10,1 + + bl .save_nvgprs li r3,0 addi r4,r1,STACK_FRAME_OVERHEAD bl .do_signal @@ -870,3 +879,67 @@ ld r0,16(r1) mtlr r0 blr + +#ifdef CONFIG_FTRACE +#ifdef CONFIG_DYNAMIC_FTRACE +_GLOBAL(mcount) +_GLOBAL(_mcount) + /* Taken from output of objdump from lib64/glibc */ + mflr r3 + stdu r1, -112(r1) + std r3, 128(r1) + subi r3, r3, MCOUNT_INSN_SIZE + .globl mcount_call +mcount_call: + bl ftrace_stub + nop + ld r0, 128(r1) + mtlr r0 + addi r1, r1, 112 + blr + +_GLOBAL(ftrace_caller) + /* Taken from output of objdump from lib64/glibc */ + mflr r3 + ld r11, 0(r1) + stdu r1, -112(r1) + std r3, 128(r1) + ld r4, 16(r11) + subi r3, r3, MCOUNT_INSN_SIZE +.globl ftrace_call +ftrace_call: + bl ftrace_stub + nop + ld r0, 128(r1) + mtlr r0 + addi r1, r1, 112 +_GLOBAL(ftrace_stub) + blr +#else +_GLOBAL(mcount) + blr + +_GLOBAL(_mcount) + /* Taken from output of objdump from lib64/glibc */ + mflr r3 + ld r11, 0(r1) + stdu r1, -112(r1) + std r3, 128(r1) + ld r4, 16(r11) + + subi r3, r3, MCOUNT_INSN_SIZE + LOAD_REG_ADDR(r5,ftrace_trace_function) + ld r5,0(r5) + ld r5,0(r5) + mtctr r5 + bctrl + + nop + ld r0, 128(r1) + mtlr r0 + addi r1, r1, 112 +_GLOBAL(ftrace_stub) + blr + +#endif +#endif diff -urN linux-2.6.26/arch/powerpc/kernel/ftrace.c linux-2.6.26-lab126/arch/powerpc/kernel/ftrace.c --- linux-2.6.26/arch/powerpc/kernel/ftrace.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/powerpc/kernel/ftrace.c 2010-08-10 04:13:54.000000000 -0400 @@ -0,0 +1,159 @@ +/* + * Code for replacing ftrace calls with jumps. + * + * Copyright (C) 2007-2008 Steven Rostedt + * + * Thanks goes out to P.A. Semi, Inc for supplying me with a PPC64 box. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +EXPORT_SYMBOL(_mcount); + +#ifdef CONFIG_DYNAMIC_FTRACE + +static unsigned int ftrace_nop = 0x60000000; + +#ifdef CONFIG_PPC32 +# define GET_ADDR(addr) addr +#else +/* PowerPC64's functions are data that points to the functions */ +# define GET_ADDR(addr) *(unsigned long *)addr +#endif + + +static unsigned int notrace ftrace_calc_offset(long ip, long addr) +{ + return (int)(addr - ip); +} + +notrace unsigned char *ftrace_nop_replace(void) +{ + return (char *)&ftrace_nop; +} + +notrace unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr) +{ + static unsigned int op; + + /* + * It would be nice to just use create_function_call, but that will + * update the code itself. Here we need to just return the + * instruction that is going to be modified, without modifying the + * code. + */ + addr = GET_ADDR(addr); + + /* Set to "bl addr" */ + op = 0x48000001 | (ftrace_calc_offset(ip, addr) & 0x03fffffc); + + /* + * No locking needed, this must be called via kstop_machine + * which in essence is like running on a uniprocessor machine. + */ + return (unsigned char *)&op; +} + +#ifdef CONFIG_PPC64 +# define _ASM_ALIGN " .align 3 " +# define _ASM_PTR " .llong " +#else +# define _ASM_ALIGN " .align 2 " +# define _ASM_PTR " .long " +#endif + +notrace int +ftrace_modify_code(unsigned long ip, unsigned char *old_code, + unsigned char *new_code) +{ + unsigned replaced; + unsigned old = *(unsigned *)old_code; + unsigned new = *(unsigned *)new_code; + int faulted = 0; + + /* + * Note: Due to modules and __init, code can + * disappear and change, we need to protect against faulting + * as well as code changing. + * + * No real locking needed, this code is run through + * kstop_machine. + */ + asm volatile ( + "1: lwz %1, 0(%2)\n" + " cmpw %1, %5\n" + " bne 2f\n" + " stwu %3, 0(%2)\n" + "2:\n" + ".section .fixup, \"ax\"\n" + "3: li %0, 1\n" + " b 2b\n" + ".previous\n" + ".section __ex_table,\"a\"\n" + _ASM_ALIGN "\n" + _ASM_PTR "1b, 3b\n" + ".previous" + : "=r"(faulted), "=r"(replaced) + : "r"(ip), "r"(new), + "0"(faulted), "r"(old) + : "memory"); + + if (replaced != old && replaced != new) + faulted = 2; + + if (!faulted) + flush_icache_range(ip, ip + 8); + + return faulted; +} + +notrace int ftrace_update_ftrace_func(ftrace_func_t func) +{ + unsigned long ip = (unsigned long)(&ftrace_call); + unsigned char old[MCOUNT_INSN_SIZE], *new; + int ret; + + memcpy(old, &ftrace_call, MCOUNT_INSN_SIZE); + new = ftrace_call_replace(ip, (unsigned long)func); + ret = ftrace_modify_code(ip, old, new); + + return ret; +} + +notrace int ftrace_mcount_set(unsigned long *data) +{ + unsigned long ip = (long)(&mcount_call); + unsigned long *addr = data; + unsigned char old[MCOUNT_INSN_SIZE], *new; + + /* + * Replace the mcount stub with a pointer to the + * ip recorder function. + */ + memcpy(old, &mcount_call, MCOUNT_INSN_SIZE); + new = ftrace_call_replace(ip, *addr); + *addr = ftrace_modify_code(ip, old, new); + + return 0; +} + +int __init ftrace_dyn_arch_init(void *data) +{ + /* This is running in kstop_machine */ + + ftrace_mcount_set(data); + + return 0; +} + +#endif /* CONFIG_DYNAMIC_FTRACE */ diff -urN linux-2.6.26/arch/powerpc/kernel/idle.c linux-2.6.26-lab126/arch/powerpc/kernel/idle.c --- linux-2.6.26/arch/powerpc/kernel/idle.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/kernel/idle.c 2010-08-10 04:13:54.000000000 -0400 @@ -60,7 +60,7 @@ set_thread_flag(TIF_POLLING_NRFLAG); while (1) { - tick_nohz_stop_sched_tick(); + tick_nohz_stop_sched_tick(1); while (!need_resched() && !cpu_should_die()) { ppc64_runlatch_off(); diff -urN linux-2.6.26/arch/powerpc/kernel/io.c linux-2.6.26-lab126/arch/powerpc/kernel/io.c --- linux-2.6.26/arch/powerpc/kernel/io.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/kernel/io.c 2010-08-10 04:13:54.000000000 -0400 @@ -120,7 +120,8 @@ #define IO_CHECK_ALIGN(v,a) ((((unsigned long)(v)) & ((a) - 1)) == 0) -void _memset_io(volatile void __iomem *addr, int c, unsigned long n) +notrace void +_memset_io(volatile void __iomem *addr, int c, unsigned long n) { void *p = (void __force *)addr; u32 lc = c; diff -urN linux-2.6.26/arch/powerpc/kernel/irq.c linux-2.6.26-lab126/arch/powerpc/kernel/irq.c --- linux-2.6.26/arch/powerpc/kernel/irq.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/kernel/irq.c 2010-08-10 04:13:54.000000000 -0400 @@ -94,11 +94,10 @@ #endif #ifdef CONFIG_PPC64 -EXPORT_SYMBOL(irq_desc); int distribute_irqs = 1; -static inline unsigned long get_hard_enabled(void) +static inline notrace unsigned long get_hard_enabled(void) { unsigned long enabled; @@ -108,13 +107,13 @@ return enabled; } -static inline void set_soft_enabled(unsigned long enable) +static inline notrace void set_soft_enabled(unsigned long enable) { __asm__ __volatile__("stb %0,%1(13)" : : "r" (enable), "i" (offsetof(struct paca_struct, soft_enabled))); } -void raw_local_irq_restore(unsigned long en) +notrace void raw_local_irq_restore(unsigned long en) { /* * get_paca()->soft_enabled = en; @@ -424,9 +423,8 @@ #ifdef CONFIG_PPC_MERGE static LIST_HEAD(irq_hosts); -static DEFINE_SPINLOCK(irq_big_lock); -static DEFINE_PER_CPU(unsigned int, irq_radix_reader); -static unsigned int irq_radix_writer; +static DEFINE_RAW_SPINLOCK(irq_big_lock); +static atomic_t revmap_trees_allocated = ATOMIC_INIT(0); struct irq_map_entry irq_map[NR_IRQS]; static unsigned int irq_virq_count = NR_IRQS; static struct irq_host *irq_default_host; @@ -569,57 +567,6 @@ irq_virq_count = count; } -/* radix tree not lockless safe ! we use a brlock-type mecanism - * for now, until we can use a lockless radix tree - */ -static void irq_radix_wrlock(unsigned long *flags) -{ - unsigned int cpu, ok; - - spin_lock_irqsave(&irq_big_lock, *flags); - irq_radix_writer = 1; - smp_mb(); - do { - barrier(); - ok = 1; - for_each_possible_cpu(cpu) { - if (per_cpu(irq_radix_reader, cpu)) { - ok = 0; - break; - } - } - if (!ok) - cpu_relax(); - } while(!ok); -} - -static void irq_radix_wrunlock(unsigned long flags) -{ - smp_wmb(); - irq_radix_writer = 0; - spin_unlock_irqrestore(&irq_big_lock, flags); -} - -static void irq_radix_rdlock(unsigned long *flags) -{ - local_irq_save(*flags); - __get_cpu_var(irq_radix_reader) = 1; - smp_mb(); - if (likely(irq_radix_writer == 0)) - return; - __get_cpu_var(irq_radix_reader) = 0; - smp_wmb(); - spin_lock(&irq_big_lock); - __get_cpu_var(irq_radix_reader) = 1; - spin_unlock(&irq_big_lock); -} - -static void irq_radix_rdunlock(unsigned long flags) -{ - __get_cpu_var(irq_radix_reader) = 0; - local_irq_restore(flags); -} - static int irq_setup_virq(struct irq_host *host, unsigned int virq, irq_hw_number_t hwirq) { @@ -774,7 +721,6 @@ { struct irq_host *host; irq_hw_number_t hwirq; - unsigned long flags; if (virq == NO_IRQ) return; @@ -808,11 +754,11 @@ break; case IRQ_HOST_MAP_TREE: /* Check if radix tree allocated yet */ - if (host->revmap_data.tree.gfp_mask == 0) + if (atomic_read(&revmap_trees_allocated) == 0) break; - irq_radix_wrlock(&flags); + spin_lock(&host->tree_lock); radix_tree_delete(&host->revmap_data.tree, hwirq); - irq_radix_wrunlock(flags); + spin_unlock(&host->tree_lock); break; } @@ -861,43 +807,55 @@ EXPORT_SYMBOL_GPL(irq_find_mapping); -unsigned int irq_radix_revmap(struct irq_host *host, - irq_hw_number_t hwirq) +unsigned int irq_radix_revmap_lookup(struct irq_host *host, + irq_hw_number_t hwirq) { - struct radix_tree_root *tree; struct irq_map_entry *ptr; - unsigned int virq; - unsigned long flags; + unsigned int virq = NO_IRQ; WARN_ON(host->revmap_type != IRQ_HOST_MAP_TREE); - /* Check if the radix tree exist yet. We test the value of - * the gfp_mask for that. Sneaky but saves another int in the - * structure. If not, we fallback to slow mode + /* + * Check if the radix tree exist yet. + * If not, we fallback to slow mode */ - tree = &host->revmap_data.tree; - if (tree->gfp_mask == 0) + if (atomic_read(&revmap_trees_allocated) == 0) return irq_find_mapping(host, hwirq); /* Now try to resolve */ - irq_radix_rdlock(&flags); - ptr = radix_tree_lookup(tree, hwirq); - irq_radix_rdunlock(flags); + /* + * No rcu_read_lock(ing) needed, the ptr returned can't go under us + * as it's referencing an entry in the static irq_map table. + */ + ptr = radix_tree_lookup(&host->revmap_data.tree, hwirq); /* Found it, return */ - if (ptr) { + if (ptr) virq = ptr - irq_map; - return virq; - } - /* If not there, try to insert it */ - virq = irq_find_mapping(host, hwirq); + return virq; +} + +void irq_radix_revmap_insert(struct irq_host *host, unsigned int virq, + irq_hw_number_t hwirq) +{ + + WARN_ON(host->revmap_type != IRQ_HOST_MAP_TREE); + + /* + * Check if the radix tree exist yet. + * If not, then the irq will be inserted into the tree when it gets + * initialized. + */ + if (atomic_read(&revmap_trees_allocated) == 0) + return; + if (virq != NO_IRQ) { - irq_radix_wrlock(&flags); - radix_tree_insert(tree, hwirq, &irq_map[virq]); - irq_radix_wrunlock(flags); + spin_lock(&host->tree_lock); + radix_tree_insert(&host->revmap_data.tree, hwirq, + &irq_map[virq]); + spin_unlock(&host->tree_lock); } - return virq; } unsigned int irq_linear_revmap(struct irq_host *host, @@ -1006,14 +964,37 @@ static int irq_late_init(void) { struct irq_host *h; - unsigned long flags; + unsigned int i; - irq_radix_wrlock(&flags); + /* + * No mutual exclusion with respect to accessors of the tree is needed + * here as the synchronization is done via the atomic variable + * revmap_trees_allocated. + */ list_for_each_entry(h, &irq_hosts, link) { - if (h->revmap_type == IRQ_HOST_MAP_TREE) + if (h->revmap_type == IRQ_HOST_MAP_TREE) { INIT_RADIX_TREE(&h->revmap_data.tree, GFP_ATOMIC); + spin_lock_init(&h->tree_lock); + } + } + + /* + * Insert the reverse mapping for those interrupts already present + * in irq_map[]. + */ + for (i = 0; i < irq_virq_count; i++) { + if (irq_map[i].host && + (irq_map[i].host->revmap_type == IRQ_HOST_MAP_TREE)) + radix_tree_insert(&irq_map[i].host->revmap_data.tree, + irq_map[i].hwirq, &irq_map[i]); } - irq_radix_wrunlock(flags); + + /* + * Make sure the radix trees inits are visible before setting + * the flag + */ + smp_mb(); + atomic_set(&revmap_trees_allocated, 1); return 0; } diff -urN linux-2.6.26/arch/powerpc/kernel/pmc.c linux-2.6.26-lab126/arch/powerpc/kernel/pmc.c --- linux-2.6.26/arch/powerpc/kernel/pmc.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/kernel/pmc.c 2010-08-10 04:13:54.000000000 -0400 @@ -37,7 +37,7 @@ } -static DEFINE_SPINLOCK(pmc_owner_lock); +static DEFINE_RAW_SPINLOCK(pmc_owner_lock); static void *pmc_owner_caller; /* mostly for debugging */ perf_irq_t perf_irq = dummy_perf; diff -urN linux-2.6.26/arch/powerpc/kernel/ppc_ksyms.c linux-2.6.26-lab126/arch/powerpc/kernel/ppc_ksyms.c --- linux-2.6.26/arch/powerpc/kernel/ppc_ksyms.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/kernel/ppc_ksyms.c 2010-08-10 04:13:54.000000000 -0400 @@ -157,7 +157,6 @@ #ifdef CONFIG_PPC32 EXPORT_SYMBOL(timer_interrupt); -EXPORT_SYMBOL(irq_desc); EXPORT_SYMBOL(tb_ticks_per_jiffy); EXPORT_SYMBOL(cacheable_memcpy); #endif diff -urN linux-2.6.26/arch/powerpc/kernel/process.c linux-2.6.26-lab126/arch/powerpc/kernel/process.c --- linux-2.6.26/arch/powerpc/kernel/process.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/kernel/process.c 2010-08-10 04:13:54.000000000 -0400 @@ -269,6 +269,10 @@ struct thread_struct *new_thread, *old_thread; unsigned long flags; struct task_struct *last; +#if defined(CONFIG_PPC64) && defined (CONFIG_PREEMPT_RT) + struct ppc64_tlb_batch *batch; + int hadbatch; +#endif #ifdef CONFIG_SMP /* avoid complexity of lazy save/restore of fpu @@ -345,6 +349,17 @@ old_thread->accum_tb += (current_tb - start_tb); new_thread->start_tb = current_tb; } + +#ifdef CONFIG_PREEMPT_RT + batch = &__get_cpu_var(ppc64_tlb_batch); + if (batch->active) { + hadbatch = 1; + if (batch->index) { + __flush_tlb_pending(batch); + } + batch->active = 0; + } +#endif /* #ifdef CONFIG_PREEMPT_RT */ #endif local_irq_save(flags); @@ -363,6 +378,13 @@ local_irq_restore(flags); +#if defined(CONFIG_PPC64) && defined(CONFIG_PREEMPT_RT) + if (hadbatch) { + batch = &__get_cpu_var(ppc64_tlb_batch); + batch->active = 1; + } +#endif + return last; } diff -urN linux-2.6.26/arch/powerpc/kernel/prom.c linux-2.6.26-lab126/arch/powerpc/kernel/prom.c --- linux-2.6.26/arch/powerpc/kernel/prom.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/kernel/prom.c 2010-08-10 04:13:54.000000000 -0400 @@ -81,7 +81,7 @@ extern struct device_node *allnodes; /* temporary while merging */ -extern rwlock_t devtree_lock; /* temporary while merging */ +extern raw_rwlock_t devtree_lock; /* temporary while merging */ /* export that to outside world */ struct device_node *of_chosen; diff -urN linux-2.6.26/arch/powerpc/kernel/rtas.c linux-2.6.26-lab126/arch/powerpc/kernel/rtas.c --- linux-2.6.26/arch/powerpc/kernel/rtas.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/kernel/rtas.c 2010-08-10 04:13:54.000000000 -0400 @@ -40,7 +40,7 @@ #include struct rtas_t rtas = { - .lock = SPIN_LOCK_UNLOCKED + .lock = RAW_SPIN_LOCK_UNLOCKED(lock) }; EXPORT_SYMBOL(rtas); diff -urN linux-2.6.26/arch/powerpc/kernel/setup_32.c linux-2.6.26-lab126/arch/powerpc/kernel/setup_32.c --- linux-2.6.26/arch/powerpc/kernel/setup_32.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/kernel/setup_32.c 2010-08-10 04:13:54.000000000 -0400 @@ -81,7 +81,7 @@ * from the address that it was linked at, so we must use RELOC/PTRRELOC * to access static data (including strings). -- paulus */ -unsigned long __init early_init(unsigned long dt_ptr) +notrace unsigned long __init early_init(unsigned long dt_ptr) { unsigned long offset = reloc_offset(); struct cpu_spec *spec; @@ -111,7 +111,7 @@ * This is called very early on the boot process, after a minimal * MMU environment has been set up but before MMU_init is called. */ -void __init machine_init(unsigned long dt_ptr, unsigned long phys) +notrace void __init machine_init(unsigned long dt_ptr, unsigned long phys) { /* Enable early debugging if any specified (see udbg.h) */ udbg_early_init(); @@ -133,7 +133,7 @@ #ifdef CONFIG_BOOKE_WDT /* Checks wdt=x and wdt_period=xx command-line option */ -int __init early_parse_wdt(char *p) +notrace int __init early_parse_wdt(char *p) { if (p && strncmp(p, "0", 1) != 0) booke_wdt_enabled = 1; @@ -321,3 +321,15 @@ paging_init(); } + +#ifdef CONFIG_EARLY_PRINTK +void notrace early_printk(const char *fmt, ...) +{ + BUG(); +} +#endif /* CONFIG_EARLY_PRINTK */ + +#ifdef CONFIG_MCOUNT +extern void _mcount(void); +EXPORT_SYMBOL(_mcount); +#endif /* CONFIG_MCOUNT */ diff -urN linux-2.6.26/arch/powerpc/kernel/smp.c linux-2.6.26-lab126/arch/powerpc/kernel/smp.c --- linux-2.6.26/arch/powerpc/kernel/smp.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/kernel/smp.c 2010-08-10 04:13:54.000000000 -0400 @@ -128,6 +128,16 @@ smp_ops->message_pass(cpu, PPC_MSG_RESCHEDULE); } +/* + * this function sends a 'reschedule' IPI to all other CPUs. + * This is used when RT tasks are starving and other CPUs + * might be able to run them: + */ +void smp_send_reschedule_allbutself(void) +{ + smp_ops->message_pass(MSG_ALL_BUT_SELF, PPC_MSG_RESCHEDULE); +} + #ifdef CONFIG_DEBUGGER void smp_send_debugger_break(int cpu) { @@ -159,7 +169,7 @@ * static memory requirements. It also looks cleaner. * Stolen from the i386 version. */ -static __cacheline_aligned_in_smp DEFINE_SPINLOCK(call_lock); +static __cacheline_aligned_in_smp DEFINE_RAW_SPINLOCK(call_lock); static struct call_data_struct { void (*func) (void *info); diff -urN linux-2.6.26/arch/powerpc/kernel/stacktrace.c linux-2.6.26-lab126/arch/powerpc/kernel/stacktrace.c --- linux-2.6.26/arch/powerpc/kernel/stacktrace.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/kernel/stacktrace.c 2010-08-10 04:13:54.000000000 -0400 @@ -10,33 +10,34 @@ * 2 of the License, or (at your option) any later version. */ +#include #include #include #include +#include /* * Save stack-backtrace addresses into a stack_trace buffer. */ -void save_stack_trace(struct stack_trace *trace) +static void save_context_stack(struct stack_trace *trace, unsigned long sp, + struct task_struct *tsk, int savesched) { - unsigned long sp; - - asm("mr %0,1" : "=r" (sp)); - for (;;) { unsigned long *stack = (unsigned long *) sp; unsigned long newsp, ip; - if (!validate_sp(sp, current, STACK_FRAME_OVERHEAD)) + if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) return; newsp = stack[0]; ip = stack[STACK_FRAME_LR_SAVE]; - if (!trace->skip) - trace->entries[trace->nr_entries++] = ip; - else - trace->skip--; + if (savesched || !in_sched_functions(ip)) { + if (!trace->skip) + trace->entries[trace->nr_entries++] = ip; + else + trace->skip--; + } if (trace->nr_entries >= trace->max_entries) return; @@ -44,3 +45,19 @@ sp = newsp; } } + +void save_stack_trace(struct stack_trace *trace) +{ + unsigned long sp; + + asm("mr %0,1" : "=r" (sp)); + + save_context_stack(trace, sp, current, 1); +} +EXPORT_SYMBOL_GPL(save_stack_trace); + +void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) +{ + save_context_stack(trace, tsk->thread.ksp, tsk, 0); +} +EXPORT_SYMBOL_GPL(save_stack_trace_tsk); diff -urN linux-2.6.26/arch/powerpc/kernel/time.c linux-2.6.26-lab126/arch/powerpc/kernel/time.c --- linux-2.6.26/arch/powerpc/kernel/time.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/kernel/time.c 2010-08-10 04:13:54.000000000 -0400 @@ -796,7 +796,7 @@ return (cycle_t)get_rtc(); } -static cycle_t timebase_read(void) +static cycle_t notrace timebase_read(void) { return (cycle_t)get_tb(); } diff -urN linux-2.6.26/arch/powerpc/kernel/traps.c linux-2.6.26-lab126/arch/powerpc/kernel/traps.c --- linux-2.6.26/arch/powerpc/kernel/traps.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/kernel/traps.c 2010-08-10 04:13:54.000000000 -0400 @@ -34,6 +34,7 @@ #include #include #include +#include #include #include @@ -97,11 +98,11 @@ int die(const char *str, struct pt_regs *regs, long err) { static struct { - spinlock_t lock; + raw_spinlock_t lock; u32 lock_owner; int lock_owner_depth; } die = { - .lock = __SPIN_LOCK_UNLOCKED(die.lock), + .lock = _RAW_SPIN_LOCK_UNLOCKED(die.lock), .lock_owner = -1, .lock_owner_depth = 0 }; @@ -111,6 +112,8 @@ if (debugger(regs)) return 1; + ftrace_halt(); + oops_enter(); if (die.lock_owner != raw_smp_processor_id()) { @@ -188,6 +191,11 @@ addr, regs->nip, regs->link, code); } +#ifdef CONFIG_PREEMPT_RT + local_irq_enable(); + preempt_check_resched(); +#endif + memset(&info, 0, sizeof(info)); info.si_signo = signr; info.si_code = code; diff -urN linux-2.6.26/arch/powerpc/kernel/vdso32/.gitignore linux-2.6.26-lab126/arch/powerpc/kernel/vdso32/.gitignore --- linux-2.6.26/arch/powerpc/kernel/vdso32/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/kernel/vdso32/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,2 +0,0 @@ -vdso32.lds -vdso32.so.dbg diff -urN linux-2.6.26/arch/powerpc/kernel/vdso64/.gitignore linux-2.6.26-lab126/arch/powerpc/kernel/vdso64/.gitignore --- linux-2.6.26/arch/powerpc/kernel/vdso64/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/kernel/vdso64/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,2 +0,0 @@ -vdso64.lds -vdso64.so.dbg diff -urN linux-2.6.26/arch/powerpc/lib/locks.c linux-2.6.26-lab126/arch/powerpc/lib/locks.c --- linux-2.6.26/arch/powerpc/lib/locks.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/lib/locks.c 2010-08-10 04:13:56.000000000 -0400 @@ -25,7 +25,7 @@ #include #include -void __spin_yield(raw_spinlock_t *lock) +void __spin_yield(__raw_spinlock_t *lock) { unsigned int lock_value, holder_cpu, yield_count; @@ -55,7 +55,7 @@ * This turns out to be the same for read and write locks, since * we only know the holder if it is write-locked. */ -void __rw_yield(raw_rwlock_t *rw) +void __rw_yield(__raw_rwlock_t *rw) { int lock_value; unsigned int holder_cpu, yield_count; @@ -82,7 +82,7 @@ } #endif -void __raw_spin_unlock_wait(raw_spinlock_t *lock) +void __raw_spin_unlock_wait(__raw_spinlock_t *lock) { while (lock->slock) { HMT_low(); diff -urN linux-2.6.26/arch/powerpc/mm/fault.c linux-2.6.26-lab126/arch/powerpc/mm/fault.c --- linux-2.6.26/arch/powerpc/mm/fault.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/mm/fault.c 2010-08-10 04:14:01.000000000 -0400 @@ -182,7 +182,7 @@ } #endif /* !(CONFIG_4xx || CONFIG_BOOKE)*/ - if (in_atomic() || mm == NULL) { + if (in_atomic() || mm == NULL || current->pagefault_disabled) { if (!user_mode(regs)) return SIGSEGV; /* in_atomic() in user mode is really bad, diff -urN linux-2.6.26/arch/powerpc/mm/hash_native_64.c linux-2.6.26-lab126/arch/powerpc/mm/hash_native_64.c --- linux-2.6.26/arch/powerpc/mm/hash_native_64.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/mm/hash_native_64.c 2010-08-10 04:14:01.000000000 -0400 @@ -36,7 +36,7 @@ #define HPTE_LOCK_BIT 3 -static DEFINE_SPINLOCK(native_tlbie_lock); +static DEFINE_RAW_SPINLOCK(native_tlbie_lock); static inline void __tlbie(unsigned long va, int psize, int ssize) { diff -urN linux-2.6.26/arch/powerpc/mm/init_32.c linux-2.6.26-lab126/arch/powerpc/mm/init_32.c --- linux-2.6.26/arch/powerpc/mm/init_32.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/mm/init_32.c 2010-08-10 04:14:01.000000000 -0400 @@ -54,7 +54,7 @@ #endif #define MAX_LOW_MEM CONFIG_LOWMEM_SIZE -DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); +DEFINE_PER_CPU_LOCKED(struct mmu_gather, mmu_gathers); unsigned long total_memory; unsigned long total_lowmem; diff -urN linux-2.6.26/arch/powerpc/mm/tlb_64.c linux-2.6.26-lab126/arch/powerpc/mm/tlb_64.c --- linux-2.6.26/arch/powerpc/mm/tlb_64.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/mm/tlb_64.c 2010-08-10 04:14:01.000000000 -0400 @@ -30,14 +30,14 @@ #include #include #include +#include DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch); /* This is declared as we are using the more or less generic * include/asm-powerpc/tlb.h file -- tgall */ -DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); -DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur); +DEFINE_PER_CPU_LOCKED(struct mmu_gather, mmu_gathers); unsigned long pte_freelist_forced_free; struct pte_freelist_batch @@ -47,7 +47,7 @@ pgtable_free_t tables[0]; }; -DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur); +DEFINE_PER_CPU_LOCKED(struct pte_freelist_batch *, pte_freelist_cur); unsigned long pte_freelist_forced_free; #define PTE_FREELIST_SIZE \ @@ -91,21 +91,21 @@ void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf) { - /* This is safe since tlb_gather_mmu has disabled preemption */ - cpumask_t local_cpumask = cpumask_of_cpu(smp_processor_id()); - struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur); + int cpu; + cpumask_t local_cpumask = cpumask_of_cpu(tlb->cpu); + struct pte_freelist_batch **batchp = &get_cpu_var_locked(pte_freelist_cur, &cpu); if (atomic_read(&tlb->mm->mm_users) < 2 || cpus_equal(tlb->mm->cpu_vm_mask, local_cpumask)) { pgtable_free(pgf); - return; + goto cleanup; } if (*batchp == NULL) { *batchp = (struct pte_freelist_batch *)__get_free_page(GFP_ATOMIC); if (*batchp == NULL) { pgtable_free_now(pgf); - return; + goto cleanup; } (*batchp)->index = 0; } @@ -114,6 +114,9 @@ pte_free_submit(*batchp); *batchp = NULL; } + + cleanup: + put_cpu_var_locked(pte_freelist_cur, cpu); } /* @@ -127,7 +130,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr, pte_t *ptep, unsigned long pte, int huge) { - struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch); + struct ppc64_tlb_batch *batch = &get_cpu_var(ppc64_tlb_batch); unsigned long vsid, vaddr; unsigned int psize; int ssize; @@ -178,6 +181,7 @@ */ if (!batch->active) { flush_hash_page(vaddr, rpte, psize, ssize, 0); + put_cpu_var(ppc64_tlb_batch); return; } @@ -204,8 +208,22 @@ batch->pte[i] = rpte; batch->vaddr[i] = vaddr; batch->index = ++i; + +#ifdef CONFIG_PREEMPT_RT + /* + * Since flushing tlb needs expensive hypervisor call(s) on celleb, + * always flush it on RT to reduce scheduling latency. + */ + if (machine_is(celleb)) { + __flush_tlb_pending(batch); + put_cpu_var(ppc64_tlb_batch); + return; + } +#endif /* CONFIG_PREEMPT_RT */ + if (i >= PPC64_TLB_BATCH_NR) __flush_tlb_pending(batch); + put_cpu_var(ppc64_tlb_batch); } /* @@ -234,13 +252,15 @@ void pte_free_finish(void) { - /* This is safe since tlb_gather_mmu has disabled preemption */ - struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur); + int cpu; + struct pte_freelist_batch **batchp = &get_cpu_var_locked(pte_freelist_cur, &cpu); - if (*batchp == NULL) - return; - pte_free_submit(*batchp); - *batchp = NULL; + if (*batchp) { + pte_free_submit(*batchp); + *batchp = NULL; + } + + put_cpu_var_locked(pte_freelist_cur, cpu); } /** diff -urN linux-2.6.26/arch/powerpc/platforms/cell/beat_htab.c linux-2.6.26-lab126/arch/powerpc/platforms/cell/beat_htab.c --- linux-2.6.26/arch/powerpc/platforms/cell/beat_htab.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/platforms/cell/beat_htab.c 2010-08-10 04:13:56.000000000 -0400 @@ -40,7 +40,7 @@ #define DBG_LOW(fmt...) do { } while (0) #endif -static DEFINE_SPINLOCK(beat_htab_lock); +static DEFINE_RAW_SPINLOCK(beat_htab_lock); static inline unsigned int beat_read_mask(unsigned hpte_group) { diff -urN linux-2.6.26/arch/powerpc/platforms/cell/beat_interrupt.c linux-2.6.26-lab126/arch/powerpc/platforms/cell/beat_interrupt.c --- linux-2.6.26/arch/powerpc/platforms/cell/beat_interrupt.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/platforms/cell/beat_interrupt.c 2010-08-10 04:13:56.000000000 -0400 @@ -30,7 +30,7 @@ #include "beat_wrapper.h" #define MAX_IRQS NR_IRQS -static DEFINE_SPINLOCK(beatic_irq_mask_lock); +static DEFINE_RAW_SPINLOCK(beatic_irq_mask_lock); static uint64_t beatic_irq_mask_enable[(MAX_IRQS+255)/64]; static uint64_t beatic_irq_mask_ack[(MAX_IRQS+255)/64]; diff -urN linux-2.6.26/arch/powerpc/platforms/cell/smp.c linux-2.6.26-lab126/arch/powerpc/platforms/cell/smp.c --- linux-2.6.26/arch/powerpc/platforms/cell/smp.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/platforms/cell/smp.c 2010-08-10 04:13:56.000000000 -0400 @@ -135,7 +135,7 @@ iic_setup_cpu(); } -static DEFINE_SPINLOCK(timebase_lock); +static DEFINE_RAW_SPINLOCK(timebase_lock); static unsigned long timebase = 0; static void __devinit cell_give_timebase(void) diff -urN linux-2.6.26/arch/powerpc/platforms/cell/spufs/.gitignore linux-2.6.26-lab126/arch/powerpc/platforms/cell/spufs/.gitignore --- linux-2.6.26/arch/powerpc/platforms/cell/spufs/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/platforms/cell/spufs/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,2 +0,0 @@ -spu_save_dump.h -spu_restore_dump.h diff -urN linux-2.6.26/arch/powerpc/platforms/chrp/smp.c linux-2.6.26-lab126/arch/powerpc/platforms/chrp/smp.c --- linux-2.6.26/arch/powerpc/platforms/chrp/smp.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/platforms/chrp/smp.c 2010-08-10 04:13:57.000000000 -0400 @@ -42,7 +42,7 @@ mpic_setup_this_cpu(); } -static DEFINE_SPINLOCK(timebase_lock); +static DEFINE_RAW_SPINLOCK(timebase_lock); static unsigned int timebase_upper = 0, timebase_lower = 0; void __devinit smp_chrp_give_timebase(void) diff -urN linux-2.6.26/arch/powerpc/platforms/chrp/time.c linux-2.6.26-lab126/arch/powerpc/platforms/chrp/time.c --- linux-2.6.26/arch/powerpc/platforms/chrp/time.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/platforms/chrp/time.c 2010-08-10 04:13:57.000000000 -0400 @@ -83,7 +83,12 @@ unsigned char save_control, save_freq_select; struct rtc_time tm = *tmarg; +#if CONFIG_PREEMPT_RT + if (!spin_trylock(&rtc_lock)) + return -1; +#else spin_lock(&rtc_lock); +#endif save_control = chrp_cmos_clock_read(RTC_CONTROL); /* tell the clock it's being set */ diff -urN linux-2.6.26/arch/powerpc/platforms/iseries/setup.c linux-2.6.26-lab126/arch/powerpc/platforms/iseries/setup.c --- linux-2.6.26/arch/powerpc/platforms/iseries/setup.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/platforms/iseries/setup.c 2010-08-10 04:13:57.000000000 -0400 @@ -561,7 +561,7 @@ static void iseries_shared_idle(void) { while (1) { - tick_nohz_stop_sched_tick(); + tick_nohz_stop_sched_tick(1); while (!need_resched() && !hvlpevent_is_pending()) { local_irq_disable(); ppc64_runlatch_off(); @@ -591,7 +591,7 @@ set_thread_flag(TIF_POLLING_NRFLAG); while (1) { - tick_nohz_stop_sched_tick(); + tick_nohz_stop_sched_tick(1); if (!need_resched()) { while (!need_resched()) { ppc64_runlatch_off(); diff -urN linux-2.6.26/arch/powerpc/platforms/powermac/Makefile linux-2.6.26-lab126/arch/powerpc/platforms/powermac/Makefile --- linux-2.6.26/arch/powerpc/platforms/powermac/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/platforms/powermac/Makefile 2010-08-10 04:13:59.000000000 -0400 @@ -1,5 +1,10 @@ CFLAGS_bootx_init.o += -fPIC +ifdef CONFIG_FTRACE +# Do not trace early boot code +CFLAGS_REMOVE_bootx_init.o = -pg -mno-sched-epilog +endif + obj-y += pic.o setup.o time.o feature.o pci.o \ sleep.o low_i2c.o cache.o pfunc_core.o \ pfunc_base.o diff -urN linux-2.6.26/arch/powerpc/platforms/powermac/feature.c linux-2.6.26-lab126/arch/powerpc/platforms/powermac/feature.c --- linux-2.6.26/arch/powerpc/platforms/powermac/feature.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/platforms/powermac/feature.c 2010-08-10 04:13:59.000000000 -0400 @@ -59,7 +59,7 @@ * We use a single global lock to protect accesses. Each driver has * to take care of its own locking */ -DEFINE_SPINLOCK(feature_lock); +DEFINE_RAW_SPINLOCK(feature_lock); #define LOCK(flags) spin_lock_irqsave(&feature_lock, flags); #define UNLOCK(flags) spin_unlock_irqrestore(&feature_lock, flags); diff -urN linux-2.6.26/arch/powerpc/platforms/powermac/nvram.c linux-2.6.26-lab126/arch/powerpc/platforms/powermac/nvram.c --- linux-2.6.26/arch/powerpc/platforms/powermac/nvram.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/platforms/powermac/nvram.c 2010-08-10 04:13:59.000000000 -0400 @@ -80,7 +80,7 @@ static int core99_bank = 0; static int nvram_partitions[3]; // XXX Turn that into a sem -static DEFINE_SPINLOCK(nv_lock); +static DEFINE_RAW_SPINLOCK(nv_lock); static int (*core99_write_bank)(int bank, u8* datas); static int (*core99_erase_bank)(int bank); diff -urN linux-2.6.26/arch/powerpc/platforms/powermac/pic.c linux-2.6.26-lab126/arch/powerpc/platforms/powermac/pic.c --- linux-2.6.26/arch/powerpc/platforms/powermac/pic.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/platforms/powermac/pic.c 2010-08-10 04:13:59.000000000 -0400 @@ -63,7 +63,7 @@ static int max_real_irqs; static u32 level_mask[4]; -static DEFINE_SPINLOCK(pmac_pic_lock); +static DEFINE_RAW_SPINLOCK(pmac_pic_lock); #define NR_MASK_WORDS ((NR_IRQS + 31) / 32) static unsigned long ppc_lost_interrupts[NR_MASK_WORDS]; diff -urN linux-2.6.26/arch/powerpc/platforms/pseries/eeh.c linux-2.6.26-lab126/arch/powerpc/platforms/pseries/eeh.c --- linux-2.6.26/arch/powerpc/platforms/pseries/eeh.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/platforms/pseries/eeh.c 2010-08-10 04:13:59.000000000 -0400 @@ -98,7 +98,7 @@ EXPORT_SYMBOL(eeh_subsystem_enabled); /* Lock to avoid races due to multiple reports of an error */ -static DEFINE_SPINLOCK(confirm_error_lock); +static DEFINE_RAW_SPINLOCK(confirm_error_lock); /* Buffer for reporting slot-error-detail rtas calls. Its here * in BSS, and not dynamically alloced, so that it ends up in diff -urN linux-2.6.26/arch/powerpc/platforms/pseries/iommu.c linux-2.6.26-lab126/arch/powerpc/platforms/pseries/iommu.c --- linux-2.6.26/arch/powerpc/platforms/pseries/iommu.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/platforms/pseries/iommu.c 2010-08-10 04:13:59.000000000 -0400 @@ -123,7 +123,7 @@ } } -static DEFINE_PER_CPU(u64 *, tce_page) = NULL; +static DEFINE_PER_CPU_LOCKED(u64 *, tce_page) = NULL; static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages, unsigned long uaddr, @@ -134,12 +134,13 @@ u64 *tcep; u64 rpn; long l, limit; + int cpu; if (npages == 1) return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, direction); - tcep = __get_cpu_var(tce_page); + tcep = get_cpu_var_locked(tce_page, &cpu); /* This is safe to do since interrupts are off when we're called * from iommu_alloc{,_sg}() @@ -147,10 +148,13 @@ if (!tcep) { tcep = (u64 *)__get_free_page(GFP_ATOMIC); /* If allocation fails, fall back to the loop implementation */ - if (!tcep) + if (!tcep) { + put_cpu_var_locked(tce_page, cpu); return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, direction); - __get_cpu_var(tce_page) = tcep; + } + + per_cpu_var_locked(tce_page, cpu) = tcep; } rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; @@ -187,6 +191,8 @@ printk("\ttce[0] val = 0x%lx\n", tcep[0]); show_stack(current, (unsigned long *)__get_SP()); } + + put_cpu_var_locked(tce_page, cpu); } static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) diff -urN linux-2.6.26/arch/powerpc/platforms/pseries/smp.c linux-2.6.26-lab126/arch/powerpc/platforms/pseries/smp.c --- linux-2.6.26/arch/powerpc/platforms/pseries/smp.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/platforms/pseries/smp.c 2010-08-10 04:13:59.000000000 -0400 @@ -148,7 +148,7 @@ } #endif /* CONFIG_XICS */ -static DEFINE_SPINLOCK(timebase_lock); +static DEFINE_RAW_SPINLOCK(timebase_lock); static unsigned long timebase = 0; static void __devinit pSeries_give_timebase(void) diff -urN linux-2.6.26/arch/powerpc/platforms/pseries/xics.c linux-2.6.26-lab126/arch/powerpc/platforms/pseries/xics.c --- linux-2.6.26/arch/powerpc/platforms/pseries/xics.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/platforms/pseries/xics.c 2010-08-10 04:13:59.000000000 -0400 @@ -310,12 +310,6 @@ static unsigned int xics_startup(unsigned int virq) { - unsigned int irq; - - /* force a reverse mapping of the interrupt so it gets in the cache */ - irq = (unsigned int)irq_map[virq].hwirq; - irq_radix_revmap(xics_host, irq); - /* unmask it */ xics_unmask_irq(virq); return 0; @@ -346,7 +340,7 @@ if (vec == XICS_IRQ_SPURIOUS) return NO_IRQ; - irq = irq_radix_revmap(xics_host, vec); + irq = irq_radix_revmap_lookup(xics_host, vec); if (likely(irq != NO_IRQ)) return irq; @@ -532,6 +526,9 @@ { pr_debug("xics: map virq %d, hwirq 0x%lx\n", virq, hw); + /* Insert the interrupt mapping into the radix tree for fast lookup */ + irq_radix_revmap_insert(xics_host, virq, hw); + get_irq_desc(virq)->status |= IRQ_LEVEL; set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq); return 0; diff -urN linux-2.6.26/arch/powerpc/sysdev/i8259.c linux-2.6.26-lab126/arch/powerpc/sysdev/i8259.c --- linux-2.6.26/arch/powerpc/sysdev/i8259.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/sysdev/i8259.c 2010-08-10 04:14:02.000000000 -0400 @@ -23,7 +23,7 @@ #define cached_A1 (cached_8259[0]) #define cached_21 (cached_8259[1]) -static DEFINE_SPINLOCK(i8259_lock); +static DEFINE_RAW_SPINLOCK(i8259_lock); static struct irq_host *i8259_host; diff -urN linux-2.6.26/arch/powerpc/sysdev/ipic.c linux-2.6.26-lab126/arch/powerpc/sysdev/ipic.c --- linux-2.6.26/arch/powerpc/sysdev/ipic.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/sysdev/ipic.c 2010-08-10 04:14:02.000000000 -0400 @@ -31,7 +31,7 @@ static struct ipic * primary_ipic; static struct irq_chip ipic_level_irq_chip, ipic_edge_irq_chip; -static DEFINE_SPINLOCK(ipic_lock); +static DEFINE_RAW_SPINLOCK(ipic_lock); static struct ipic_info ipic_info[] = { [1] = { diff -urN linux-2.6.26/arch/powerpc/sysdev/mpic.c linux-2.6.26-lab126/arch/powerpc/sysdev/mpic.c --- linux-2.6.26/arch/powerpc/sysdev/mpic.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/sysdev/mpic.c 2010-08-10 04:14:02.000000000 -0400 @@ -46,7 +46,7 @@ static struct mpic *mpics; static struct mpic *mpic_primary; -static DEFINE_SPINLOCK(mpic_lock); +static DEFINE_RAW_SPINLOCK(mpic_lock); #ifdef CONFIG_PPC32 /* XXX for now */ #ifdef CONFIG_IRQ_ALL_CPUS diff -urN linux-2.6.26/arch/powerpc/xmon/xmon.c linux-2.6.26-lab126/arch/powerpc/xmon/xmon.c --- linux-2.6.26/arch/powerpc/xmon/xmon.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/powerpc/xmon/xmon.c 2010-08-10 04:13:54.000000000 -0400 @@ -342,6 +342,7 @@ unsigned long timeout; #endif + preempt_disable(); local_irq_save(flags); bp = in_breakpoint_table(regs->nip, &offset); @@ -518,6 +519,7 @@ insert_cpu_bpts(); local_irq_restore(flags); + preempt_enable(); return cmd != 'X' && cmd != EOF; } diff -urN linux-2.6.26/arch/ppc/.gitignore linux-2.6.26-lab126/arch/ppc/.gitignore --- linux-2.6.26/arch/ppc/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1 +0,0 @@ -/include diff -urN linux-2.6.26/arch/ppc/8260_io/enet.c linux-2.6.26-lab126/arch/ppc/8260_io/enet.c --- linux-2.6.26/arch/ppc/8260_io/enet.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/8260_io/enet.c 2010-08-10 04:14:20.000000000 -0400 @@ -115,7 +115,7 @@ scc_t *sccp; struct net_device_stats stats; uint tx_full; - spinlock_t lock; + raw_spinlock_t lock; }; static int scc_enet_open(struct net_device *dev); diff -urN linux-2.6.26/arch/ppc/8260_io/fcc_enet.c linux-2.6.26-lab126/arch/ppc/8260_io/fcc_enet.c --- linux-2.6.26/arch/ppc/8260_io/fcc_enet.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/8260_io/fcc_enet.c 2010-08-10 04:14:20.000000000 -0400 @@ -364,7 +364,7 @@ volatile fcc_enet_t *ep; struct net_device_stats stats; uint tx_free; - spinlock_t lock; + raw_spinlock_t lock; #ifdef CONFIG_USE_MDIO uint phy_id; diff -urN linux-2.6.26/arch/ppc/8xx_io/commproc.c linux-2.6.26-lab126/arch/ppc/8xx_io/commproc.c --- linux-2.6.26/arch/ppc/8xx_io/commproc.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/8xx_io/commproc.c 2010-08-10 04:14:21.000000000 -0400 @@ -332,7 +332,7 @@ /* * dpalloc / dpfree bits. */ -static spinlock_t cpm_dpmem_lock; +static raw_spinlock_t cpm_dpmem_lock; /* * 16 blocks should be enough to satisfy all requests * until the memory subsystem goes up... diff -urN linux-2.6.26/arch/ppc/8xx_io/enet.c linux-2.6.26-lab126/arch/ppc/8xx_io/enet.c --- linux-2.6.26/arch/ppc/8xx_io/enet.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/8xx_io/enet.c 2010-08-10 04:14:21.000000000 -0400 @@ -143,7 +143,7 @@ unsigned char *rx_vaddr[RX_RING_SIZE]; struct net_device_stats stats; uint tx_full; - spinlock_t lock; + raw_spinlock_t lock; }; static int scc_enet_open(struct net_device *dev); diff -urN linux-2.6.26/arch/ppc/8xx_io/fec.c linux-2.6.26-lab126/arch/ppc/8xx_io/fec.c --- linux-2.6.26/arch/ppc/8xx_io/fec.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/8xx_io/fec.c 2010-08-10 04:14:21.000000000 -0400 @@ -164,7 +164,7 @@ struct net_device_stats stats; uint tx_full; - spinlock_t lock; + raw_spinlock_t lock; #ifdef CONFIG_USE_MDIO uint phy_id; diff -urN linux-2.6.26/arch/ppc/Kconfig linux-2.6.26-lab126/arch/ppc/Kconfig --- linux-2.6.26/arch/ppc/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/Kconfig 2010-08-10 04:14:21.000000000 -0400 @@ -16,13 +16,6 @@ bool default y -config RWSEM_GENERIC_SPINLOCK - bool - -config RWSEM_XCHGADD_ALGORITHM - bool - default y - config ARCH_HAS_ILOG2_U32 bool default y @@ -846,6 +839,18 @@ source kernel/Kconfig.hz source kernel/Kconfig.preempt + +config RWSEM_GENERIC_SPINLOCK + bool + default y + +config ASM_SEMAPHORES + bool + default y + +config RWSEM_XCHGADD_ALGORITHM + bool + source "mm/Kconfig" source "fs/Kconfig.binfmt" diff -urN linux-2.6.26/arch/ppc/boot/Makefile linux-2.6.26-lab126/arch/ppc/boot/Makefile --- linux-2.6.26/arch/ppc/boot/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/boot/Makefile 2010-08-10 04:14:20.000000000 -0400 @@ -15,6 +15,15 @@ # KBUILD_CFLAGS used when building rest of boot (takes effect recursively) KBUILD_CFLAGS += -fno-builtin -D__BOOTER__ -Iarch/$(ARCH)/boot/include + +ifdef CONFIG_MCOUNT +# do not trace the boot loader +nullstring := +space := $(nullstring) # end of the line +pg_flag = $(nullstring) -pg # end of the line +KBUILD_CFLAGS := $(subst ${pg_flag},${space},${KBUILD_CFLAGS}) +endif + HOSTCFLAGS += -Iarch/$(ARCH)/boot/include BOOT_TARGETS = zImage zImage.initrd znetboot znetboot.initrd diff -urN linux-2.6.26/arch/ppc/boot/images/.gitignore linux-2.6.26-lab126/arch/ppc/boot/images/.gitignore --- linux-2.6.26/arch/ppc/boot/images/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/boot/images/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,6 +0,0 @@ -sImage -vmapus -vmlinux* -miboot* -zImage* -uImage diff -urN linux-2.6.26/arch/ppc/boot/lib/.gitignore linux-2.6.26-lab126/arch/ppc/boot/lib/.gitignore --- linux-2.6.26/arch/ppc/boot/lib/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/boot/lib/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,3 +0,0 @@ -inffast.c -inflate.c -inftrees.c diff -urN linux-2.6.26/arch/ppc/boot/utils/.gitignore linux-2.6.26-lab126/arch/ppc/boot/utils/.gitignore --- linux-2.6.26/arch/ppc/boot/utils/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/boot/utils/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,3 +0,0 @@ -mkprep -mkbugboot -mktree diff -urN linux-2.6.26/arch/ppc/kernel/entry.S linux-2.6.26-lab126/arch/ppc/kernel/entry.S --- linux-2.6.26/arch/ppc/kernel/entry.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/kernel/entry.S 2010-08-10 04:14:19.000000000 -0400 @@ -882,7 +882,7 @@ #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */ do_work: /* r10 contains MSR_KERNEL here */ - andi. r0,r9,_TIF_NEED_RESCHED + andi. r0,r9,(_TIF_NEED_RESCHED) beq do_user_signal do_resched: /* r10 contains MSR_KERNEL here */ @@ -896,7 +896,7 @@ MTMSRD(r10) /* disable interrupts */ rlwinm r9,r1,0,0,18 lwz r9,TI_FLAGS(r9) - andi. r0,r9,_TIF_NEED_RESCHED + andi. r0,r9,(_TIF_NEED_RESCHED) bne- do_resched andi. r0,r9,_TIF_SIGPENDING beq restore_user diff -urN linux-2.6.26/arch/ppc/kernel/smp.c linux-2.6.26-lab126/arch/ppc/kernel/smp.c --- linux-2.6.26/arch/ppc/kernel/smp.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/kernel/smp.c 2010-08-10 04:14:19.000000000 -0400 @@ -136,6 +136,16 @@ smp_message_pass(cpu, PPC_MSG_RESCHEDULE); } +/* + * this function sends a 'reschedule' IPI to all other CPUs. + * This is used when RT tasks are starving and other CPUs + * might be able to run them: + */ +void smp_send_reschedule_allbutself(void) +{ + smp_message_pass(MSG_ALL_BUT_SELF, PPC_MSG_RESCHEDULE, 0, 0); +} + #ifdef CONFIG_XMON void smp_send_xmon_break(int cpu) { @@ -160,7 +170,7 @@ * static memory requirements. It also looks cleaner. * Stolen from the i386 version. */ -static DEFINE_SPINLOCK(call_lock); +static DEFINE_RAW_SPINLOCK(call_lock); static struct call_data_struct { void (*func) (void *info); diff -urN linux-2.6.26/arch/ppc/kernel/traps.c linux-2.6.26-lab126/arch/ppc/kernel/traps.c --- linux-2.6.26/arch/ppc/kernel/traps.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/kernel/traps.c 2010-08-10 04:14:19.000000000 -0400 @@ -72,7 +72,7 @@ * Trap & Exception support */ -DEFINE_SPINLOCK(die_lock); +DEFINE_RAW_SPINLOCK(die_lock); int die(const char * str, struct pt_regs * fp, long err) { @@ -108,6 +108,10 @@ debugger(regs); die("Exception in kernel mode", regs, signr); } +#ifdef CONFIG_PREEMPT_RT + local_irq_enable(); + preempt_check_resched(); +#endif info.si_signo = signr; info.si_errno = 0; info.si_code = code; diff -urN linux-2.6.26/arch/ppc/lib/locks.c linux-2.6.26-lab126/arch/ppc/lib/locks.c --- linux-2.6.26/arch/ppc/lib/locks.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/lib/locks.c 2010-08-10 04:14:20.000000000 -0400 @@ -42,7 +42,7 @@ return ret; } -void _raw_spin_lock(spinlock_t *lock) +void __raw_spin_lock(raw_spinlock_t *lock) { int cpu = smp_processor_id(); unsigned int stuck = INIT_STUCK; @@ -62,9 +62,9 @@ lock->owner_pc = (unsigned long)__builtin_return_address(0); lock->owner_cpu = cpu; } -EXPORT_SYMBOL(_raw_spin_lock); +EXPORT_SYMBOL(__raw_spin_lock); -int _raw_spin_trylock(spinlock_t *lock) +int __raw_spin_trylock(raw_spinlock_t *lock) { if (__spin_trylock(&lock->lock)) return 0; @@ -72,9 +72,9 @@ lock->owner_pc = (unsigned long)__builtin_return_address(0); return 1; } -EXPORT_SYMBOL(_raw_spin_trylock); +EXPORT_SYMBOL(__raw_spin_trylock); -void _raw_spin_unlock(spinlock_t *lp) +void __raw_spin_unlock(raw_spinlock_t *lp) { if ( !lp->lock ) printk("_spin_unlock(%p): no lock cpu %d curr PC %p %s/%d\n", @@ -88,13 +88,13 @@ wmb(); lp->lock = 0; } -EXPORT_SYMBOL(_raw_spin_unlock); +EXPORT_SYMBOL(__raw_spin_unlock); /* * For rwlocks, zero is unlocked, -1 is write-locked, * positive is read-locked. */ -static __inline__ int __read_trylock(rwlock_t *rw) +static __inline__ int __read_trylock(raw_rwlock_t *rw) { signed int tmp; @@ -114,13 +114,13 @@ return tmp; } -int _raw_read_trylock(rwlock_t *rw) +int __raw_read_trylock(raw_rwlock_t *rw) { return __read_trylock(rw) > 0; } -EXPORT_SYMBOL(_raw_read_trylock); +EXPORT_SYMBOL(__raw_read_trylock); -void _raw_read_lock(rwlock_t *rw) +void __raw_read_lock(rwlock_t *rw) { unsigned int stuck; @@ -135,9 +135,9 @@ } } } -EXPORT_SYMBOL(_raw_read_lock); +EXPORT_SYMBOL(__raw_read_lock); -void _raw_read_unlock(rwlock_t *rw) +void __raw_read_unlock(raw_rwlock_t *rw) { if ( rw->lock == 0 ) printk("_read_unlock(): %s/%d (nip %08lX) lock %d\n", @@ -146,9 +146,9 @@ wmb(); atomic_dec((atomic_t *) &(rw)->lock); } -EXPORT_SYMBOL(_raw_read_unlock); +EXPORT_SYMBOL(__raw_read_unlock); -void _raw_write_lock(rwlock_t *rw) +void __raw_write_lock(raw_rwlock_t *rw) { unsigned int stuck; @@ -164,18 +164,18 @@ } wmb(); } -EXPORT_SYMBOL(_raw_write_lock); +EXPORT_SYMBOL(__raw_write_lock); -int _raw_write_trylock(rwlock_t *rw) +int __raw_write_trylock(raw_rwlock_t *rw) { if (cmpxchg(&rw->lock, 0, -1) != 0) return 0; wmb(); return 1; } -EXPORT_SYMBOL(_raw_write_trylock); +EXPORT_SYMBOL(__raw_write_trylock); -void _raw_write_unlock(rwlock_t *rw) +void __raw_write_unlock(raw_rwlock_t *rw) { if (rw->lock >= 0) printk("_write_lock(): %s/%d (nip %08lX) lock %d\n", @@ -184,6 +184,6 @@ wmb(); rw->lock = 0; } -EXPORT_SYMBOL(_raw_write_unlock); +EXPORT_SYMBOL(__raw_write_unlock); #endif diff -urN linux-2.6.26/arch/ppc/mm/init.c linux-2.6.26-lab126/arch/ppc/mm/init.c --- linux-2.6.26/arch/ppc/mm/init.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/mm/init.c 2010-08-10 04:14:21.000000000 -0400 @@ -55,7 +55,7 @@ #endif #define MAX_LOW_MEM CONFIG_LOWMEM_SIZE -DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); +DEFINE_PER_CPU_LOCKED(struct mmu_gather, mmu_gathers); unsigned long total_memory; unsigned long total_lowmem; diff -urN linux-2.6.26/arch/ppc/platforms/hdpu.c linux-2.6.26-lab126/arch/ppc/platforms/hdpu.c --- linux-2.6.26/arch/ppc/platforms/hdpu.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/platforms/hdpu.c 2010-08-10 04:14:21.000000000 -0400 @@ -54,7 +54,7 @@ static void hdpu_set_l1pe(void); static void hdpu_cpustate_set(unsigned char new_state); #ifdef CONFIG_SMP -static DEFINE_SPINLOCK(timebase_lock); +static DEFINE_RAW_SPINLOCK(timebase_lock); static unsigned int timebase_upper = 0, timebase_lower = 0; extern int smp_tb_synchronized; diff -urN linux-2.6.26/arch/ppc/platforms/sbc82xx.c linux-2.6.26-lab126/arch/ppc/platforms/sbc82xx.c --- linux-2.6.26/arch/ppc/platforms/sbc82xx.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/platforms/sbc82xx.c 2010-08-10 04:14:21.000000000 -0400 @@ -63,7 +63,7 @@ static volatile char *sbc82xx_i8259_map; static char sbc82xx_i8259_mask = 0xff; -static DEFINE_SPINLOCK(sbc82xx_i8259_lock); +static DEFINE_RAW_SPINLOCK(sbc82xx_i8259_lock); static void sbc82xx_i8259_mask_and_ack_irq(unsigned int irq_nr) { diff -urN linux-2.6.26/arch/ppc/syslib/cpm2_common.c linux-2.6.26-lab126/arch/ppc/syslib/cpm2_common.c --- linux-2.6.26/arch/ppc/syslib/cpm2_common.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/syslib/cpm2_common.c 2010-08-10 04:14:20.000000000 -0400 @@ -114,7 +114,7 @@ /* * dpalloc / dpfree bits. */ -static spinlock_t cpm_dpmem_lock; +static raw_spinlock_t cpm_dpmem_lock; /* 16 blocks should be enough to satisfy all requests * until the memory subsystem goes up... */ static rh_block_t cpm_boot_dpmem_rh_block[16]; diff -urN linux-2.6.26/arch/ppc/syslib/open_pic.c linux-2.6.26-lab126/arch/ppc/syslib/open_pic.c --- linux-2.6.26/arch/ppc/syslib/open_pic.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/syslib/open_pic.c 2010-08-10 04:14:20.000000000 -0400 @@ -526,7 +526,7 @@ } #if defined(CONFIG_SMP) || defined(CONFIG_PM) -static DEFINE_SPINLOCK(openpic_setup_lock); +static DEFINE_RAW_SPINLOCK(openpic_setup_lock); #endif #ifdef CONFIG_SMP diff -urN linux-2.6.26/arch/ppc/syslib/open_pic2.c linux-2.6.26-lab126/arch/ppc/syslib/open_pic2.c --- linux-2.6.26/arch/ppc/syslib/open_pic2.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/ppc/syslib/open_pic2.c 2010-08-10 04:14:20.000000000 -0400 @@ -380,7 +380,7 @@ vec); } -static DEFINE_SPINLOCK(openpic2_setup_lock); +static DEFINE_RAW_SPINLOCK(openpic2_setup_lock); /* * Initialize a timer interrupt (and disable it) diff -urN linux-2.6.26/arch/s390/kernel/process.c linux-2.6.26-lab126/arch/s390/kernel/process.c --- linux-2.6.26/arch/s390/kernel/process.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/s390/kernel/process.c 2010-08-10 04:14:43.000000000 -0400 @@ -170,7 +170,7 @@ void cpu_idle(void) { for (;;) { - tick_nohz_stop_sched_tick(); + tick_nohz_stop_sched_tick(1); while (!need_resched()) default_idle(); tick_nohz_restart_sched_tick(); diff -urN linux-2.6.26/arch/sh/boot/.gitignore linux-2.6.26-lab126/arch/sh/boot/.gitignore --- linux-2.6.26/arch/sh/boot/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/sh/boot/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1 +0,0 @@ -zImage diff -urN linux-2.6.26/arch/sh/kernel/process_32.c linux-2.6.26-lab126/arch/sh/kernel/process_32.c --- linux-2.6.26/arch/sh/kernel/process_32.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/sh/kernel/process_32.c 2010-08-10 04:15:10.000000000 -0400 @@ -86,7 +86,7 @@ if (!idle) idle = default_idle; - tick_nohz_stop_sched_tick(); + tick_nohz_stop_sched_tick(1); while (!need_resched()) idle(); tick_nohz_restart_sched_tick(); diff -urN linux-2.6.26/arch/sh/kernel/vsyscall/.gitignore linux-2.6.26-lab126/arch/sh/kernel/vsyscall/.gitignore --- linux-2.6.26/arch/sh/kernel/vsyscall/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/sh/kernel/vsyscall/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1 +0,0 @@ -vsyscall.lds diff -urN linux-2.6.26/arch/sh/lib64/.gitignore linux-2.6.26-lab126/arch/sh/lib64/.gitignore --- linux-2.6.26/arch/sh/lib64/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/sh/lib64/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1 +0,0 @@ -syscalltab.h diff -urN linux-2.6.26/arch/sparc/mm/highmem.c linux-2.6.26-lab126/arch/sparc/mm/highmem.c --- linux-2.6.26/arch/sparc/mm/highmem.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/sparc/mm/highmem.c 2010-08-10 04:15:05.000000000 -0400 @@ -34,7 +34,7 @@ unsigned long idx; unsigned long vaddr; - /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */ + preempt_disable(); pagefault_disable(); if (!PageHighMem(page)) return page_address(page); @@ -71,6 +71,7 @@ if (vaddr < FIXADDR_START) { // FIXME pagefault_enable(); + preempt_enable(); return; } @@ -97,6 +98,7 @@ #endif pagefault_enable(); + preempt_enable(); } /* We may be fed a pagetable here by ptep_to_xxx and others. */ diff -urN linux-2.6.26/arch/sparc64/Kconfig linux-2.6.26-lab126/arch/sparc64/Kconfig --- linux-2.6.26/arch/sparc64/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/sparc64/Kconfig 2010-08-10 04:14:23.000000000 -0400 @@ -11,6 +11,8 @@ config SPARC64 bool default y + select HAVE_DYNAMIC_FTRACE + select HAVE_FTRACE select HAVE_IDE select HAVE_LMB select HAVE_ARCH_KGDB diff -urN linux-2.6.26/arch/sparc64/Kconfig.debug linux-2.6.26-lab126/arch/sparc64/Kconfig.debug --- linux-2.6.26/arch/sparc64/Kconfig.debug 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/sparc64/Kconfig.debug 2010-08-10 04:14:23.000000000 -0400 @@ -33,7 +33,7 @@ config MCOUNT bool - depends on STACK_DEBUG + depends on STACK_DEBUG || FTRACE default y config FRAME_POINTER diff -urN linux-2.6.26/arch/sparc64/boot/.gitignore linux-2.6.26-lab126/arch/sparc64/boot/.gitignore --- linux-2.6.26/arch/sparc64/boot/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/sparc64/boot/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,4 +0,0 @@ -image -tftpboot.img -vmlinux.aout -piggyback diff -urN linux-2.6.26/arch/sparc64/kernel/Makefile linux-2.6.26-lab126/arch/sparc64/kernel/Makefile --- linux-2.6.26/arch/sparc64/kernel/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/sparc64/kernel/Makefile 2010-08-10 04:14:22.000000000 -0400 @@ -14,6 +14,7 @@ power.o sbus.o sparc64_ksyms.o chmc.o \ visemul.o prom.o of_device.o hvapi.o sstate.o mdesc.o +obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-$(CONFIG_PCI) += ebus.o pci_common.o \ pci_psycho.o pci_sabre.o pci_schizo.o \ diff -urN linux-2.6.26/arch/sparc64/kernel/ftrace.c linux-2.6.26-lab126/arch/sparc64/kernel/ftrace.c --- linux-2.6.26/arch/sparc64/kernel/ftrace.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/sparc64/kernel/ftrace.c 2010-08-10 04:14:22.000000000 -0400 @@ -0,0 +1,94 @@ +#include +#include +#include +#include +#include +#include + +#include + +static const u32 ftrace_nop = 0x01000000; + +notrace unsigned char *ftrace_nop_replace(void) +{ + return (char *)&ftrace_nop; +} + +notrace unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr) +{ + static u32 call; + s32 off; + + off = ((s32)addr - (s32)ip); + call = 0x40000000 | ((u32)off >> 2); + + return (unsigned char *) &call; +} + +notrace int +ftrace_modify_code(unsigned long ip, unsigned char *old_code, + unsigned char *new_code) +{ + u32 old = *(u32 *)old_code; + u32 new = *(u32 *)new_code; + u32 replaced; + int faulted; + + __asm__ __volatile__( + "1: cas [%[ip]], %[old], %[new]\n" + " flush %[ip]\n" + " mov 0, %[faulted]\n" + "2:\n" + " .section .fixup,#alloc,#execinstr\n" + " .align 4\n" + "3: sethi %%hi(2b), %[faulted]\n" + " jmpl %[faulted] + %%lo(2b), %%g0\n" + " mov 1, %[faulted]\n" + " .previous\n" + " .section __ex_table,\"a\"\n" + " .align 4\n" + " .word 1b, 3b\n" + " .previous\n" + : "=r" (replaced), [faulted] "=r" (faulted) + : [new] "0" (new), [old] "r" (old), [ip] "r" (ip) + : "memory"); + + if (replaced != old && replaced != new) + faulted = 2; + + return faulted; +} + +notrace int ftrace_update_ftrace_func(ftrace_func_t func) +{ + unsigned long ip = (unsigned long)(&ftrace_call); + unsigned char old[MCOUNT_INSN_SIZE], *new; + + memcpy(old, &ftrace_call, MCOUNT_INSN_SIZE); + new = ftrace_call_replace(ip, (unsigned long)func); + return ftrace_modify_code(ip, old, new); +} + +notrace int ftrace_mcount_set(unsigned long *data) +{ + unsigned long ip = (long)(&mcount_call); + unsigned long *addr = data; + unsigned char old[MCOUNT_INSN_SIZE], *new; + + /* + * Replace the mcount stub with a pointer to the + * ip recorder function. + */ + memcpy(old, &mcount_call, MCOUNT_INSN_SIZE); + new = ftrace_call_replace(ip, *addr); + *addr = ftrace_modify_code(ip, old, new); + + return 0; +} + + +int __init ftrace_dyn_arch_init(void *data) +{ + ftrace_mcount_set(data); + return 0; +} diff -urN linux-2.6.26/arch/sparc64/kernel/process.c linux-2.6.26-lab126/arch/sparc64/kernel/process.c --- linux-2.6.26/arch/sparc64/kernel/process.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/sparc64/kernel/process.c 2010-08-10 04:14:22.000000000 -0400 @@ -97,7 +97,7 @@ set_thread_flag(TIF_POLLING_NRFLAG); while(1) { - tick_nohz_stop_sched_tick(); + tick_nohz_stop_sched_tick(1); while (!need_resched() && !cpu_is_offline(cpu)) sparc64_yield(cpu); diff -urN linux-2.6.26/arch/sparc64/lib/mcount.S linux-2.6.26-lab126/arch/sparc64/lib/mcount.S --- linux-2.6.26/arch/sparc64/lib/mcount.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/sparc64/lib/mcount.S 2010-08-10 04:14:22.000000000 -0400 @@ -28,10 +28,13 @@ .skip OVSTACKSIZE #endif .text - .align 32 - .globl mcount, _mcount -mcount: + .align 32 + .globl _mcount + .type _mcount,#function + .globl mcount + .type mcount,#function _mcount: +mcount: #ifdef CONFIG_STACK_DEBUG /* * Check whether %sp is dangerously low. @@ -55,6 +58,53 @@ or %g3, %lo(panicstring), %o0 call prom_halt nop +1: +#endif +#ifdef CONFIG_FTRACE +#ifdef CONFIG_DYNAMIC_FTRACE + mov %o7, %o0 + .globl mcount_call +mcount_call: + call ftrace_stub + mov %o0, %o7 +#else + sethi %hi(ftrace_trace_function), %g1 + sethi %hi(ftrace_stub), %g2 + ldx [%g1 + %lo(ftrace_trace_function)], %g1 + or %g2, %lo(ftrace_stub), %g2 + cmp %g1, %g2 + be,pn %icc, 1f + mov %i7, %o1 + jmpl %g1, %g0 + mov %o7, %o0 + /* not reached */ +1: +#endif #endif -1: retl + retl nop + .size _mcount,.-_mcount + .size mcount,.-mcount + +#ifdef CONFIG_FTRACE + .globl ftrace_stub + .type ftrace_stub,#function +ftrace_stub: + retl + nop + .size ftrace_stub,.-ftrace_stub +#ifdef CONFIG_DYNAMIC_FTRACE + .globl ftrace_caller + .type ftrace_caller,#function +ftrace_caller: + mov %i7, %o1 + mov %o7, %o0 + .globl ftrace_call +ftrace_call: + call ftrace_stub + mov %o0, %o7 + retl + nop + .size ftrace_caller,.-ftrace_caller +#endif +#endif diff -urN linux-2.6.26/arch/um/kernel/process.c linux-2.6.26-lab126/arch/um/kernel/process.c --- linux-2.6.26/arch/um/kernel/process.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/um/kernel/process.c 2010-08-10 04:14:17.000000000 -0400 @@ -243,7 +243,7 @@ if (need_resched()) schedule(); - tick_nohz_stop_sched_tick(); + tick_nohz_stop_sched_tick(1); nsecs = disable_timer(); idle_sleep(nsecs); tick_nohz_restart_sched_tick(); diff -urN linux-2.6.26/arch/x86/Kconfig linux-2.6.26-lab126/arch/x86/Kconfig --- linux-2.6.26/arch/x86/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/Kconfig 2010-08-10 04:14:38.000000000 -0400 @@ -23,6 +23,9 @@ select HAVE_OPROFILE select HAVE_KPROBES select HAVE_KRETPROBES + select HAVE_FTRACE_MCOUNT_RECORD + select HAVE_DYNAMIC_FTRACE + select HAVE_FTRACE select HAVE_KVM if ((X86_32 && !X86_VOYAGER && !X86_VISWS && !X86_NUMAQ) || X86_64) select HAVE_ARCH_KGDB if !X86_VOYAGER @@ -93,10 +96,18 @@ def_bool y config RWSEM_GENERIC_SPINLOCK - def_bool !X86_XADD + bool + depends on !X86_XADD || PREEMPT_RT + default y + +config ASM_SEMAPHORES + bool + default y config RWSEM_XCHGADD_ALGORITHM - def_bool X86_XADD + bool + depends on X86_XADD && !RWSEM_GENERIC_SPINLOCK && !PREEMPT_RT + default y config ARCH_HAS_ILOG2_U32 def_bool n @@ -1321,6 +1332,10 @@ def_bool X86_64 depends on NUMA +config HARDIRQS_SW_RESEND + bool + default y + menu "Power management options" depends on !X86_VOYAGER diff -urN linux-2.6.26/arch/x86/Kconfig.debug linux-2.6.26-lab126/arch/x86/Kconfig.debug --- linux-2.6.26/arch/x86/Kconfig.debug 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/Kconfig.debug 2010-08-10 04:14:38.000000000 -0400 @@ -122,6 +122,7 @@ config 4KSTACKS bool "Use 4Kb for kernel stacks instead of 8Kb" depends on X86_32 + default y help If you say Y here the kernel will use a 4Kb stacksize for the kernel stack attached to each process/thread. This facilitates diff -urN linux-2.6.26/arch/x86/boot/.gitignore linux-2.6.26-lab126/arch/x86/boot/.gitignore --- linux-2.6.26/arch/x86/boot/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/boot/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,8 +0,0 @@ -bootsect -bzImage -cpustr.h -mkcpustr -offsets.h -setup -setup.bin -setup.elf diff -urN linux-2.6.26/arch/x86/boot/compressed/.gitignore linux-2.6.26-lab126/arch/x86/boot/compressed/.gitignore --- linux-2.6.26/arch/x86/boot/compressed/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/boot/compressed/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1 +0,0 @@ -relocs diff -urN linux-2.6.26/arch/x86/boot/tools/.gitignore linux-2.6.26-lab126/arch/x86/boot/tools/.gitignore --- linux-2.6.26/arch/x86/boot/tools/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/boot/tools/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1 +0,0 @@ -build diff -urN linux-2.6.26/arch/x86/ia32/ia32entry.S linux-2.6.26-lab126/arch/x86/ia32/ia32entry.S --- linux-2.6.26/arch/x86/ia32/ia32entry.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/ia32/ia32entry.S 2010-08-10 04:14:36.000000000 -0400 @@ -131,7 +131,9 @@ cmpl $(IA32_NR_syscalls-1),%eax ja ia32_badsys IA32_ARG_FIXUP 1 + TRACE_SYS_IA32_CALL call *ia32_sys_call_table(,%rax,8) + TRACE_SYS_RET movq %rax,RAX-ARGOFFSET(%rsp) GET_THREAD_INFO(%r10) cli @@ -238,7 +240,9 @@ cmpl $IA32_NR_syscalls-1,%eax ja ia32_badsys IA32_ARG_FIXUP 1 + TRACE_SYS_IA32_CALL call *ia32_sys_call_table(,%rax,8) + TRACE_SYS_RET movq %rax,RAX-ARGOFFSET(%rsp) GET_THREAD_INFO(%r10) cli @@ -331,8 +335,10 @@ cmpl $(IA32_NR_syscalls-1),%eax ja int_ret_from_sys_call /* ia32_tracesys has set RAX(%rsp) */ IA32_ARG_FIXUP + TRACE_SYS_IA32_CALL call *ia32_sys_call_table(,%rax,8) # xxx: rip relative ia32_sysret: + TRACE_SYS_RET movq %rax,RAX-ARGOFFSET(%rsp) jmp int_ret_from_sys_call @@ -403,7 +409,7 @@ .section .rodata,"a" .align 8 -ia32_sys_call_table: +ENTRY(ia32_sys_call_table) .quad sys_restart_syscall .quad sys_exit .quad stub32_fork @@ -731,4 +737,5 @@ .quad sys32_fallocate .quad compat_sys_timerfd_settime /* 325 */ .quad compat_sys_timerfd_gettime +.globl ia32_syscall_end ia32_syscall_end: diff -urN linux-2.6.26/arch/x86/kernel/.gitignore linux-2.6.26-lab126/arch/x86/kernel/.gitignore --- linux-2.6.26/arch/x86/kernel/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,3 +0,0 @@ -vsyscall.lds -vsyscall_32.lds -vmlinux.lds diff -urN linux-2.6.26/arch/x86/kernel/Makefile linux-2.6.26-lab126/arch/x86/kernel/Makefile --- linux-2.6.26/arch/x86/kernel/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/Makefile 2010-08-10 04:14:34.000000000 -0400 @@ -6,6 +6,13 @@ CPPFLAGS_vmlinux.lds += -U$(UTS_MACHINE) +ifdef CONFIG_FTRACE +# Do not profile debug utilities +CFLAGS_REMOVE_tsc_64.o = -pg +CFLAGS_REMOVE_tsc_32.o = -pg +CFLAGS_REMOVE_rtc.o = -pg +endif + # # vsyscalls (which work on the user stack) should have # no stack-protector checks: @@ -56,6 +63,7 @@ obj-$(CONFIG_X86_LOCAL_APIC) += apic_$(BITS).o nmi_$(BITS).o obj-$(CONFIG_X86_IO_APIC) += io_apic_$(BITS).o obj-$(CONFIG_X86_REBOOTFIXUPS) += reboot_fixups_32.o +obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o obj-$(CONFIG_KEXEC) += machine_kexec_$(BITS).o obj-$(CONFIG_KEXEC) += relocate_kernel_$(BITS).o crash.o obj-$(CONFIG_CRASH_DUMP) += crash_dump_$(BITS).o diff -urN linux-2.6.26/arch/x86/kernel/acpi/realmode/.gitignore linux-2.6.26-lab126/arch/x86/kernel/acpi/realmode/.gitignore --- linux-2.6.26/arch/x86/kernel/acpi/realmode/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/acpi/realmode/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,3 +0,0 @@ -wakeup.bin -wakeup.elf -wakeup.lds diff -urN linux-2.6.26/arch/x86/kernel/alternative.c linux-2.6.26-lab126/arch/x86/kernel/alternative.c --- linux-2.6.26/arch/x86/kernel/alternative.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/alternative.c 2010-08-10 04:14:34.000000000 -0400 @@ -143,7 +143,7 @@ #ifdef CONFIG_X86_64 extern char __vsyscall_0; -static inline const unsigned char*const * find_nop_table(void) +const unsigned char *const *find_nop_table(void) { return boot_cpu_data.x86_vendor != X86_VENDOR_INTEL || boot_cpu_data.x86 < 6 ? k8_nops : p6_nops; @@ -162,7 +162,7 @@ { -1, NULL } }; -static const unsigned char*const * find_nop_table(void) +const unsigned char *const *find_nop_table(void) { const unsigned char *const *noptable = intel_nops; int i; diff -urN linux-2.6.26/arch/x86/kernel/apic_32.c linux-2.6.26-lab126/arch/x86/kernel/apic_32.c --- linux-2.6.26/arch/x86/kernel/apic_32.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/apic_32.c 2010-08-10 04:14:34.000000000 -0400 @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -604,6 +605,7 @@ { struct pt_regs *old_regs = set_irq_regs(regs); + trace_event_irq(-1, user_mode(regs), regs->ip); /* * NOTE! We'd better ACK the irq immediately, * because timer handling can be slow. @@ -1335,6 +1337,7 @@ */ printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n", smp_processor_id(), v , v1); + dump_stack(); irq_exit(); } diff -urN linux-2.6.26/arch/x86/kernel/apic_64.c linux-2.6.26-lab126/arch/x86/kernel/apic_64.c --- linux-2.6.26/arch/x86/kernel/apic_64.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/apic_64.c 2010-08-10 04:14:34.000000000 -0400 @@ -850,7 +850,6 @@ void __cpuinit end_local_APIC_setup(void) { lapic_setup_esr(); - nmi_watchdog_default(); setup_apic_nmi_watchdog(NULL); apic_pm_activate(); } diff -urN linux-2.6.26/arch/x86/kernel/cpu/mtrr/generic.c linux-2.6.26-lab126/arch/x86/kernel/cpu/mtrr/generic.c --- linux-2.6.26/arch/x86/kernel/cpu/mtrr/generic.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/cpu/mtrr/generic.c 2010-08-10 04:14:32.000000000 -0400 @@ -465,7 +465,7 @@ static unsigned long cr4 = 0; -static DEFINE_SPINLOCK(set_atomicity_lock); +static DEFINE_RAW_SPINLOCK(set_atomicity_lock); /* * Since we are disabling the cache don't allow any interrupts - they diff -urN linux-2.6.26/arch/x86/kernel/crash.c linux-2.6.26-lab126/arch/x86/kernel/crash.c --- linux-2.6.26/arch/x86/kernel/crash.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/crash.c 2010-08-10 04:14:34.000000000 -0400 @@ -75,14 +75,6 @@ return 1; } -static void smp_send_nmi_allbutself(void) -{ - cpumask_t mask = cpu_online_map; - cpu_clear(safe_smp_processor_id(), mask); - if (!cpus_empty(mask)) - send_IPI_mask(mask, NMI_VECTOR); -} - static struct notifier_block crash_nmi_nb = { .notifier_call = crash_nmi_callback, }; diff -urN linux-2.6.26/arch/x86/kernel/early_printk.c linux-2.6.26-lab126/arch/x86/kernel/early_printk.c --- linux-2.6.26/arch/x86/kernel/early_printk.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/early_printk.c 2010-08-10 04:14:34.000000000 -0400 @@ -51,7 +51,7 @@ static struct console early_vga_console = { .name = "earlyvga", .write = early_vga_write, - .flags = CON_PRINTBUFFER, + .flags = CON_PRINTBUFFER | CON_ATOMIC, .index = -1, }; @@ -147,7 +147,7 @@ static struct console early_serial_console = { .name = "earlyser", .write = early_serial_write, - .flags = CON_PRINTBUFFER, + .flags = CON_PRINTBUFFER | CON_ATOMIC, .index = -1, }; @@ -188,7 +188,7 @@ static struct console simnow_console = { .name = "simnow", .write = simnow_write, - .flags = CON_PRINTBUFFER, + .flags = CON_PRINTBUFFER | CON_ATOMIC, .index = -1, }; @@ -198,7 +198,7 @@ void early_printk(const char *fmt, ...) { - char buf[512]; + static char buf[512]; int n; va_list ap; diff -urN linux-2.6.26/arch/x86/kernel/entry_32.S linux-2.6.26-lab126/arch/x86/kernel/entry_32.S --- linux-2.6.26/arch/x86/kernel/entry_32.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/entry_32.S 2010-08-10 04:14:34.000000000 -0400 @@ -51,6 +51,7 @@ #include #include #include +#include #include "irq_vectors.h" /* @@ -259,14 +260,18 @@ #ifdef CONFIG_PREEMPT ENTRY(resume_kernel) DISABLE_INTERRUPTS(CLBR_ANY) + cmpl $0, kernel_preemption + jz restore_nocheck cmpl $0,TI_preempt_count(%ebp) # non-zero preempt_count ? jnz restore_nocheck need_resched: movl TI_flags(%ebp), %ecx # need_resched set ? testb $_TIF_NEED_RESCHED, %cl - jz restore_all + jz restore_nocheck testl $X86_EFLAGS_IF,PT_EFLAGS(%esp) # interrupts off (exception path) ? - jz restore_all + jz restore_nocheck + DISABLE_INTERRUPTS(CLBR_ANY) + call preempt_schedule_irq jmp need_resched END(resume_kernel) @@ -313,6 +318,11 @@ pushl %eax CFI_ADJUST_CFA_OFFSET 4 SAVE_ALL +#ifdef CONFIG_EVENT_TRACE + pushl %edx; pushl %ecx; pushl %ebx; pushl %eax + call sys_call + popl %eax; popl %ebx; popl %ecx; popl %edx +#endif ENABLE_INTERRUPTS(CLBR_NONE) /* @@ -343,6 +353,11 @@ movl TI_flags(%ebp), %ecx testw $_TIF_ALLWORK_MASK, %cx jne syscall_exit_work +#ifdef CONFIG_EVENT_TRACE + pushl %eax + call sys_ret + popl %eax +#endif /* if something modifies registers it must also disable sysexit */ movl PT_EIP(%esp), %edx movl PT_OLDESP(%esp), %ecx @@ -366,6 +381,11 @@ pushl %eax # save orig_eax CFI_ADJUST_CFA_OFFSET 4 SAVE_ALL +#ifdef CONFIG_EVENT_TRACE + pushl %edx; pushl %ecx; pushl %ebx; pushl %eax + call sys_call + popl %eax; popl %ebx; popl %ecx; popl %edx +#endif GET_THREAD_INFO(%ebp) # system call tracing in operation / emulation /* Note, _TIF_SECCOMP is bit number 8, and so it needs testw and not testb */ @@ -465,20 +485,19 @@ ALIGN RING0_PTREGS_FRAME # can't unwind into user space anyway work_pending: - testb $_TIF_NEED_RESCHED, %cl + testl $(_TIF_NEED_RESCHED), %ecx jz work_notifysig work_resched: - call schedule + call __schedule LOCKDEP_SYS_EXIT DISABLE_INTERRUPTS(CLBR_ANY) # make sure we don't miss an interrupt # setting need_resched or sigpending # between sampling and the iret - TRACE_IRQS_OFF movl TI_flags(%ebp), %ecx andl $_TIF_WORK_MASK, %ecx # is there any work to be done other # than syscall tracing? jz restore_all - testb $_TIF_NEED_RESCHED, %cl + testl $(_TIF_NEED_RESCHED), %ecx jnz work_resched work_notifysig: # deal with pending signals and @@ -1110,6 +1129,69 @@ #endif /* CONFIG_XEN */ +#ifdef CONFIG_FTRACE +#ifdef CONFIG_DYNAMIC_FTRACE + +ENTRY(mcount) + ret +END(mcount) + +ENTRY(ftrace_caller) + cmpl $0, function_trace_stop + jne ftrace_stub + + pushl %eax + pushl %ecx + pushl %edx + movl 0xc(%esp), %eax + movl 0x4(%ebp), %edx + subl $MCOUNT_INSN_SIZE, %eax + +.globl ftrace_call +ftrace_call: + call ftrace_stub + + popl %edx + popl %ecx + popl %eax + +.globl ftrace_stub +ftrace_stub: + ret +END(ftrace_caller) + +#else /* ! CONFIG_DYNAMIC_FTRACE */ + +ENTRY(mcount) + cmpl $0, function_trace_stop + jne ftrace_stub + + cmpl $ftrace_stub, ftrace_trace_function + jnz trace +.globl ftrace_stub +ftrace_stub: + ret + + /* taken from glibc */ +trace: + pushl %eax + pushl %ecx + pushl %edx + movl 0xc(%esp), %eax + movl 0x4(%ebp), %edx + subl $MCOUNT_INSN_SIZE, %eax + + call *ftrace_trace_function + + popl %edx + popl %ecx + popl %eax + + jmp ftrace_stub +END(mcount) +#endif /* CONFIG_DYNAMIC_FTRACE */ +#endif /* CONFIG_FTRACE */ + .section .rodata,"a" #include "syscall_table_32.S" diff -urN linux-2.6.26/arch/x86/kernel/entry_64.S linux-2.6.26-lab126/arch/x86/kernel/entry_64.S --- linux-2.6.26/arch/x86/kernel/entry_64.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/entry_64.S 2010-08-10 04:14:34.000000000 -0400 @@ -51,9 +51,96 @@ #include #include #include +#include .code64 +#ifdef CONFIG_FTRACE +#ifdef CONFIG_DYNAMIC_FTRACE +ENTRY(mcount) + retq +END(mcount) + +ENTRY(ftrace_caller) + cmpl $0, function_trace_stop + jne ftrace_stub + + /* taken from glibc */ + subq $0x38, %rsp + movq %rax, (%rsp) + movq %rcx, 8(%rsp) + movq %rdx, 16(%rsp) + movq %rsi, 24(%rsp) + movq %rdi, 32(%rsp) + movq %r8, 40(%rsp) + movq %r9, 48(%rsp) + + movq 0x38(%rsp), %rdi + movq 8(%rbp), %rsi + subq $MCOUNT_INSN_SIZE, %rdi + +.globl ftrace_call +ftrace_call: + call ftrace_stub + + movq 48(%rsp), %r9 + movq 40(%rsp), %r8 + movq 32(%rsp), %rdi + movq 24(%rsp), %rsi + movq 16(%rsp), %rdx + movq 8(%rsp), %rcx + movq (%rsp), %rax + addq $0x38, %rsp + +.globl ftrace_stub +ftrace_stub: + retq +END(ftrace_caller) + +#else /* ! CONFIG_DYNAMIC_FTRACE */ +ENTRY(mcount) + cmpl $0, function_trace_stop + jne ftrace_stub + + cmpq $ftrace_stub, ftrace_trace_function + jnz trace +.globl ftrace_stub +ftrace_stub: + retq + +trace: + /* taken from glibc */ + subq $0x38, %rsp + movq %rax, (%rsp) + movq %rcx, 8(%rsp) + movq %rdx, 16(%rsp) + movq %rsi, 24(%rsp) + movq %rdi, 32(%rsp) + movq %r8, 40(%rsp) + movq %r9, 48(%rsp) + + movq 0x38(%rsp), %rdi + movq 8(%rbp), %rsi + subq $MCOUNT_INSN_SIZE, %rdi + + call *ftrace_trace_function + + movq 48(%rsp), %r9 + movq 40(%rsp), %r8 + movq 32(%rsp), %rdi + movq 24(%rsp), %rsi + movq 16(%rsp), %rdx + movq 8(%rsp), %rcx + movq (%rsp), %rax + addq $0x38, %rsp + + jmp ftrace_stub +END(mcount) +#endif /* CONFIG_DYNAMIC_FTRACE */ +#endif /* CONFIG_FTRACE */ + +#define HARDNMI_MASK 0x40000000 + #ifndef CONFIG_PREEMPT #define retint_kernel retint_restore_args #endif @@ -249,7 +336,9 @@ cmpq $__NR_syscall_max,%rax ja badsys movq %r10,%rcx + TRACE_SYS_CALL call *sys_call_table(,%rax,8) # XXX: rip relative + TRACE_SYS_RET movq %rax,RAX-ARGOFFSET(%rsp) /* * Syscall return path ending with SYSRET (fast path) @@ -281,8 +370,8 @@ /* Handle reschedules */ /* edx: work, edi: workmask */ sysret_careful: - bt $TIF_NEED_RESCHED,%edx - jnc sysret_signal + testl $(_TIF_NEED_RESCHED),%edx + jz sysret_signal TRACE_IRQS_ON ENABLE_INTERRUPTS(CLBR_NONE) pushq %rdi @@ -305,7 +394,7 @@ leaq -ARGOFFSET(%rsp),%rdi # &pt_regs -> arg1 xorl %esi,%esi # oldset -> arg2 call ptregscall_common -1: movl $_TIF_NEED_RESCHED,%edi +1: movl $(_TIF_NEED_RESCHED),%edi /* Use IRET because user could have changed frame. This works because ptregscall_common has called FIXUP_TOP_OF_STACK. */ DISABLE_INTERRUPTS(CLBR_NONE) @@ -328,7 +417,9 @@ cmpq $__NR_syscall_max,%rax ja int_ret_from_sys_call /* RAX(%rsp) set to -ENOSYS above */ movq %r10,%rcx /* fixup for C */ + TRACE_SYS_CALL call *sys_call_table(,%rax,8) + TRACE_SYS_RET movq %rax,RAX-ARGOFFSET(%rsp) /* Use IRET because user could have changed frame */ @@ -357,8 +448,8 @@ /* First do a reschedule test. */ /* edx: work, edi: workmask */ int_careful: - bt $TIF_NEED_RESCHED,%edx - jnc int_very_careful + testl $(_TIF_NEED_RESCHED),%edx + jz int_very_careful TRACE_IRQS_ON ENABLE_INTERRUPTS(CLBR_NONE) pushq %rdi @@ -393,7 +484,7 @@ movq %rsp,%rdi # &ptregs -> arg1 xorl %esi,%esi # oldset -> arg2 call do_notify_resume -1: movl $_TIF_NEED_RESCHED,%edi +1: movl $(_TIF_NEED_RESCHED),%edi int_restore_rest: RESTORE_REST DISABLE_INTERRUPTS(CLBR_NONE) @@ -620,8 +711,8 @@ /* edi: workmask, edx: work */ retint_careful: CFI_RESTORE_STATE - bt $TIF_NEED_RESCHED,%edx - jnc retint_signal + testl $(_TIF_NEED_RESCHED),%edx + jz retint_signal TRACE_IRQS_ON ENABLE_INTERRUPTS(CLBR_NONE) pushq %rdi @@ -647,7 +738,7 @@ RESTORE_REST DISABLE_INTERRUPTS(CLBR_NONE) TRACE_IRQS_OFF - movl $_TIF_NEED_RESCHED,%edi + movl $(_TIF_NEED_RESCHED),%edi GET_THREAD_INFO(%rcx) jmp retint_check diff -urN linux-2.6.26/arch/x86/kernel/ftrace.c linux-2.6.26-lab126/arch/x86/kernel/ftrace.c --- linux-2.6.26/arch/x86/kernel/ftrace.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/x86/kernel/ftrace.c 2010-08-10 04:14:34.000000000 -0400 @@ -0,0 +1,173 @@ +/* + * Code for replacing ftrace calls with jumps. + * + * Copyright (C) 2007-2008 Steven Rostedt + * + * Thanks goes to Ingo Molnar, for suggesting the idea. + * Mathieu Desnoyers, for suggesting postponing the modifications. + * Arjan van de Ven, for keeping me straight, and explaining to me + * the dangers of modifying code on the run. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + + +/* Long is fine, even if it is only 4 bytes ;-) */ +static long *ftrace_nop; + +union ftrace_code_union { + char code[MCOUNT_INSN_SIZE]; + struct { + char e8; + int offset; + } __attribute__((packed)); +}; + + +static int notrace ftrace_calc_offset(long ip, long addr) +{ + return (int)(addr - ip); +} + +notrace unsigned char *ftrace_nop_replace(void) +{ + return (char *)ftrace_nop; +} + +notrace unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr) +{ + static union ftrace_code_union calc; + + calc.e8 = 0xe8; + calc.offset = ftrace_calc_offset(ip + MCOUNT_INSN_SIZE, addr); + + /* + * No locking needed, this must be called via kstop_machine + * which in essence is like running on a uniprocessor machine. + */ + return calc.code; +} + +notrace int +ftrace_modify_code(unsigned long ip, unsigned char *old_code, + unsigned char *new_code) +{ + unsigned char replaced[MCOUNT_INSN_SIZE]; + + /* + * Note: Due to modules and __init, code can + * disappear and change, we need to protect against faulting + * as well as code changing. + * + * No real locking needed, this code is run through + * kstop_machine, or before SMP starts. + */ + if (__copy_from_user(replaced, (char __user *)ip, MCOUNT_INSN_SIZE)) + return 1; + + if (memcmp(replaced, old_code, MCOUNT_INSN_SIZE) != 0) + return 2; + + WARN_ON_ONCE(__copy_to_user((char __user *)ip, new_code, + MCOUNT_INSN_SIZE)); + + sync_core(); + + return 0; +} + +notrace int ftrace_update_ftrace_func(ftrace_func_t func) +{ + unsigned long ip = (unsigned long)(&ftrace_call); + unsigned char old[MCOUNT_INSN_SIZE], *new; + int ret; + + memcpy(old, &ftrace_call, MCOUNT_INSN_SIZE); + new = ftrace_call_replace(ip, (unsigned long)func); + ret = ftrace_modify_code(ip, old, new); + + return ret; +} + +notrace int ftrace_mcount_set(unsigned long *data) +{ + /* mcount is initialized as a nop */ + *data = 0; + return 0; +} + +int __init ftrace_dyn_arch_init(void *data) +{ + extern const unsigned char ftrace_test_p6nop[]; + extern const unsigned char ftrace_test_nop5[]; + extern const unsigned char ftrace_test_jmp[]; + int faulted = 0; + + /* + * There is no good nop for all x86 archs. + * We will default to using the P6_NOP5, but first we + * will test to make sure that the nop will actually + * work on this CPU. If it faults, we will then + * go to a lesser efficient 5 byte nop. If that fails + * we then just use a jmp as our nop. This isn't the most + * efficient nop, but we can not use a multi part nop + * since we would then risk being preempted in the middle + * of that nop, and if we enabled tracing then, it might + * cause a system crash. + * + * TODO: check the cpuid to determine the best nop. + */ + asm volatile ( + "jmp ftrace_test_jmp\n" + /* This code needs to stay around */ + ".section .text, \"ax\"\n" + "ftrace_test_jmp:" + "jmp ftrace_test_p6nop\n" + ".byte 0x00,0x00,0x00\n" /* 2 byte jmp + 3 bytes */ + "ftrace_test_p6nop:" + P6_NOP5 + "jmp 1f\n" + "ftrace_test_nop5:" + ".byte 0x66,0x66,0x66,0x66,0x90\n" + "jmp 1f\n" + ".previous\n" + "1:" + ".section .fixup, \"ax\"\n" + "2: movl $1, %0\n" + " jmp ftrace_test_nop5\n" + "3: movl $2, %0\n" + " jmp 1b\n" + ".previous\n" + _ASM_EXTABLE(ftrace_test_p6nop, 2b) + _ASM_EXTABLE(ftrace_test_nop5, 3b) + : "=r"(faulted) : "0" (faulted)); + + switch (faulted) { + case 0: + pr_info("ftrace: converting mcount calls to 0f 1f 44 00 00\n"); + ftrace_nop = (unsigned long *)ftrace_test_p6nop; + break; + case 1: + pr_info("ftrace: converting mcount calls to 66 66 66 66 90\n"); + ftrace_nop = (unsigned long *)ftrace_test_nop5; + break; + case 2: + pr_info("ftrace: converting mcount calls to jmp 1f\n"); + ftrace_nop = (unsigned long *)ftrace_test_jmp; + break; + } + + /* The return code is retured via data */ + *(unsigned long *)data = 0; + + return 0; +} diff -urN linux-2.6.26/arch/x86/kernel/head64.c linux-2.6.26-lab126/arch/x86/kernel/head64.c --- linux-2.6.26/arch/x86/kernel/head64.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/head64.c 2010-08-10 04:14:34.000000000 -0400 @@ -29,7 +29,11 @@ { pgd_t *pgd = pgd_offset_k(0UL); pgd_clear(pgd); - __flush_tlb_all(); + /* + * preempt_disable/enable does not work this early in the + * bootup yet: + */ + write_cr3(read_cr3()); } /* Don't add a printk in there. printk relies on the PDA which is not initialized diff -urN linux-2.6.26/arch/x86/kernel/head_32.S linux-2.6.26-lab126/arch/x86/kernel/head_32.S --- linux-2.6.26/arch/x86/kernel/head_32.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/head_32.S 2010-08-10 04:14:34.000000000 -0400 @@ -584,6 +584,7 @@ call printk #endif addl $(5*4),%esp + call dump_stack popl %ds popl %es popl %edx diff -urN linux-2.6.26/arch/x86/kernel/i386_ksyms_32.c linux-2.6.26-lab126/arch/x86/kernel/i386_ksyms_32.c --- linux-2.6.26/arch/x86/kernel/i386_ksyms_32.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/i386_ksyms_32.c 2010-08-10 04:14:34.000000000 -0400 @@ -1,7 +1,13 @@ #include #include -#include #include +#include +#include + +#ifdef CONFIG_FTRACE +/* mcount is defined in assembly */ +EXPORT_SYMBOL(mcount); +#endif /* Networking helper routines. */ EXPORT_SYMBOL(csum_partial_copy_generic); diff -urN linux-2.6.26/arch/x86/kernel/i8253.c linux-2.6.26-lab126/arch/x86/kernel/i8253.c --- linux-2.6.26/arch/x86/kernel/i8253.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/i8253.c 2010-08-10 04:14:34.000000000 -0400 @@ -15,7 +15,7 @@ #include #include -DEFINE_SPINLOCK(i8253_lock); +DEFINE_RAW_SPINLOCK(i8253_lock); EXPORT_SYMBOL(i8253_lock); #ifdef CONFIG_X86_32 diff -urN linux-2.6.26/arch/x86/kernel/i8259_32.c linux-2.6.26-lab126/arch/x86/kernel/i8259_32.c --- linux-2.6.26/arch/x86/kernel/i8259_32.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/i8259_32.c 2010-08-10 04:14:34.000000000 -0400 @@ -29,7 +29,7 @@ */ static int i8259A_auto_eoi; -DEFINE_SPINLOCK(i8259A_lock); +DEFINE_RAW_SPINLOCK(i8259A_lock); static void mask_and_ack_8259A(unsigned int); static struct irq_chip i8259A_chip = { @@ -165,6 +165,8 @@ */ if (cached_irq_mask & irqmask) goto spurious_8259A_irq; + if (irq & 8) + outb(0x60+(irq&7),PIC_SLAVE_CMD); /* 'Specific EOI' to slave */ cached_irq_mask |= irqmask; handle_real_irq: @@ -292,10 +294,10 @@ outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */ outb_pic(0x20 + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */ outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */ - if (auto_eoi) /* master does Auto EOI */ - outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR); - else /* master expects normal EOI */ - outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR); + if (!auto_eoi) /* master expects normal EOI */ + outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR); + else /* master does Auto EOI */ + outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR); outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */ outb_pic(0x20 + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */ @@ -347,6 +349,7 @@ */ static struct irqaction fpu_irq = { .handler = math_error_irq, + .flags = IRQF_NODELAY, .mask = CPU_MASK_NONE, .name = "fpu", }; diff -urN linux-2.6.26/arch/x86/kernel/i8259_64.c linux-2.6.26-lab126/arch/x86/kernel/i8259_64.c --- linux-2.6.26/arch/x86/kernel/i8259_64.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/i8259_64.c 2010-08-10 04:14:34.000000000 -0400 @@ -97,8 +97,8 @@ */ static int i8259A_auto_eoi; -DEFINE_SPINLOCK(i8259A_lock); static void mask_and_ack_8259A(unsigned int); +DEFINE_RAW_SPINLOCK(i8259A_lock); static struct irq_chip i8259A_chip = { .name = "XT-PIC", @@ -405,6 +405,7 @@ static struct irqaction irq2 = { .handler = no_action, + .flags = IRQF_NODELAY, .mask = CPU_MASK_NONE, .name = "cascade", }; diff -urN linux-2.6.26/arch/x86/kernel/io_apic_32.c linux-2.6.26-lab126/arch/x86/kernel/io_apic_32.c --- linux-2.6.26/arch/x86/kernel/io_apic_32.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/io_apic_32.c 2010-08-10 04:14:34.000000000 -0400 @@ -55,8 +55,8 @@ /* Where if anywhere is the i8259 connect in external int mode */ static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; -static DEFINE_SPINLOCK(ioapic_lock); -static DEFINE_SPINLOCK(vector_lock); +static DEFINE_RAW_SPINLOCK(ioapic_lock); +static DEFINE_RAW_SPINLOCK(vector_lock); int timer_over_8254 __initdata = 1; @@ -270,14 +270,14 @@ __modify_IO_APIC_irq(irq, 0, 0x00010000); } -/* mask = 1, trigger = 0 */ -static void __mask_and_edge_IO_APIC_irq (unsigned int irq) +/* trigger = 0 (edge mode) */ +static void __pcix_mask_IO_APIC_irq (unsigned int irq) { - __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000); + __modify_IO_APIC_irq(irq, 0, 0x00008000); } -/* mask = 0, trigger = 1 */ -static void __unmask_and_level_IO_APIC_irq (unsigned int irq) +/* mask = 0, trigger = 1 (level mode) */ +static void __pcix_unmask_IO_APIC_irq (unsigned int irq) { __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000); } @@ -300,6 +300,24 @@ spin_unlock_irqrestore(&ioapic_lock, flags); } +static void pcix_mask_IO_APIC_irq (unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&ioapic_lock, flags); + __pcix_mask_IO_APIC_irq(irq); + spin_unlock_irqrestore(&ioapic_lock, flags); +} + +static void pcix_unmask_IO_APIC_irq (unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&ioapic_lock, flags); + __pcix_unmask_IO_APIC_irq(irq); + spin_unlock_irqrestore(&ioapic_lock, flags); +} + static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) { struct IO_APIC_route_entry entry; @@ -1203,23 +1221,28 @@ return vector; } + static struct irq_chip ioapic_chip; +static struct irq_chip pcix_ioapic_chip; #define IOAPIC_AUTO -1 #define IOAPIC_EDGE 0 #define IOAPIC_LEVEL 1 -static void ioapic_register_intr(int irq, int vector, unsigned long trigger) +static void ioapic_register_intr(int irq, int vector, unsigned long trigger, + int pcix) { + struct irq_chip *chip = pcix ? &pcix_ioapic_chip : &ioapic_chip; + if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || trigger == IOAPIC_LEVEL) { irq_desc[irq].status |= IRQ_LEVEL; - set_irq_chip_and_handler_name(irq, &ioapic_chip, - handle_fasteoi_irq, "fasteoi"); + set_irq_chip_and_handler_name(irq, chip, handle_fasteoi_irq, + pcix ? "pcix-fasteoi" : "fasteoi"); } else { irq_desc[irq].status &= ~IRQ_LEVEL; - set_irq_chip_and_handler_name(irq, &ioapic_chip, - handle_edge_irq, "edge"); + set_irq_chip_and_handler_name(irq, chip, handle_edge_irq, + pcix ? "pcix-edge" : "edge"); } set_intr_gate(vector, interrupt[irq]); } @@ -1288,7 +1311,8 @@ if (IO_APIC_IRQ(irq)) { vector = assign_irq_vector(irq); entry.vector = vector; - ioapic_register_intr(irq, vector, IOAPIC_AUTO); + ioapic_register_intr(irq, vector, IOAPIC_AUTO, + apic > 0); if (!apic && (irq < 16)) disable_8259A_irq(irq); @@ -1457,7 +1481,7 @@ return; } -#if 0 +#if 1 static void print_APIC_bitfield (int base) { @@ -1864,7 +1888,8 @@ * might have cached one ExtINT interrupt. Finally, at * least one tick may be lost due to delays. */ - if (time_after(jiffies, t1 + 4)) + if (time_after(jiffies, t1 + 4) && + time_before(jiffies, t1 + 16)) return 1; return 0; @@ -1953,8 +1978,10 @@ if (!(v & (1 << (i & 0x1f)))) { atomic_inc(&irq_mis_count); spin_lock(&ioapic_lock); - __mask_and_edge_IO_APIC_irq(irq); - __unmask_and_level_IO_APIC_irq(irq); + /* mask = 1, trigger = 0 */ + __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000); + /* mask = 0, trigger = 1 */ + __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000); spin_unlock(&ioapic_lock); } } @@ -1979,6 +2006,18 @@ .retrigger = ioapic_retrigger_irq, }; +static struct irq_chip pcix_ioapic_chip __read_mostly = { + .name = "IO-APIC", + .startup = startup_ioapic_irq, + .mask = pcix_mask_IO_APIC_irq, + .unmask = pcix_unmask_IO_APIC_irq, + .ack = ack_ioapic_irq, + .eoi = ack_ioapic_irq, +#ifdef CONFIG_SMP + .set_affinity = set_ioapic_affinity_irq, +#endif + .retrigger = ioapic_retrigger_irq, +}; static inline void init_IO_APIC_traps(void) { @@ -2784,7 +2823,7 @@ mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, edge_level, active_high_low); - ioapic_register_intr(irq, entry.vector, edge_level); + ioapic_register_intr(irq, entry.vector, edge_level, ioapic > 0); if (!ioapic && (irq < 16)) disable_8259A_irq(irq); diff -urN linux-2.6.26/arch/x86/kernel/io_apic_64.c linux-2.6.26-lab126/arch/x86/kernel/io_apic_64.c --- linux-2.6.26/arch/x86/kernel/io_apic_64.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/io_apic_64.c 2010-08-10 04:14:34.000000000 -0400 @@ -95,8 +95,8 @@ /* Where if anywhere is the i8259 connect in external int mode */ static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; -static DEFINE_SPINLOCK(ioapic_lock); -DEFINE_SPINLOCK(vector_lock); +static DEFINE_RAW_SPINLOCK(ioapic_lock); +DEFINE_RAW_SPINLOCK(vector_lock); /* * # of IRQ routing registers @@ -222,6 +222,9 @@ reg ACTION; \ io_apic_modify(entry->apic, reg); \ FINAL; \ + /* Force POST flush by reading: */ \ + reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \ + \ if (!entry->next) \ break; \ entry = irq_2_pin + entry->next; \ @@ -366,10 +369,11 @@ static void name##_IO_APIC_irq (unsigned int irq) \ __DO_ACTION(R, ACTION, FINAL) -DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) ) - /* mask = 1 */ -DO_ACTION( __unmask, 0, &= 0xfffeffff, ) - /* mask = 0 */ +DO_ACTION( __mask, 0, |= 0x00010000, ) /* mask = 1 */ +DO_ACTION( __unmask, 0, &= 0xfffeffff, ) /* mask = 0 */ + +DO_ACTION( __pcix_mask, 0, &= 0xffff7fff, ) /* edge */ +DO_ACTION( __pcix_unmask, 0, = (reg & 0xfffeffff) | 0x00008000, ) /* level */ static void mask_IO_APIC_irq (unsigned int irq) { @@ -388,6 +392,23 @@ __unmask_IO_APIC_irq(irq); spin_unlock_irqrestore(&ioapic_lock, flags); } +static void pcix_mask_IO_APIC_irq (unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&ioapic_lock, flags); + __pcix_mask_IO_APIC_irq(irq); + spin_unlock_irqrestore(&ioapic_lock, flags); +} + +static void pcix_unmask_IO_APIC_irq (unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&ioapic_lock, flags); + __pcix_unmask_IO_APIC_irq(irq); + spin_unlock_irqrestore(&ioapic_lock, flags); +} static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) { @@ -813,17 +834,20 @@ static struct irq_chip ioapic_chip; +static struct irq_chip pcix_ioapic_chip; -static void ioapic_register_intr(int irq, unsigned long trigger) +static void ioapic_register_intr(int irq, unsigned long trigger, int pcix) { + struct irq_chip *chip = pcix ? &pcix_ioapic_chip : &ioapic_chip; + if (trigger) { irq_desc[irq].status |= IRQ_LEVEL; - set_irq_chip_and_handler_name(irq, &ioapic_chip, - handle_fasteoi_irq, "fasteoi"); + set_irq_chip_and_handler_name(irq, chip, handle_fasteoi_irq, + pcix ? "pcix-fasteoi" : "fasteoi"); } else { irq_desc[irq].status &= ~IRQ_LEVEL; - set_irq_chip_and_handler_name(irq, &ioapic_chip, - handle_edge_irq, "edge"); + set_irq_chip_and_handler_name(irq, chip, handle_edge_irq, + pcix ? "pcix-edge" : "edge"); } } @@ -868,7 +892,7 @@ if (trigger) entry.mask = 1; - ioapic_register_intr(irq, trigger); + ioapic_register_intr(irq, trigger, apic > 0); if (irq < 16) disable_8259A_irq(irq); @@ -1450,7 +1474,8 @@ irq_complete_move(irq); #ifdef CONFIG_GENERIC_PENDING_IRQ /* If we are moving the irq we need to mask it */ - if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) { + if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING) && + !(irq_desc[irq].status & IRQ_INPROGRESS)) { do_unmask_irq = 1; mask_IO_APIC_irq(irq); } @@ -1494,17 +1519,39 @@ move_masked_irq(irq); unmask_IO_APIC_irq(irq); } +#if (defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)) && \ + defined(CONFIG_PREEMPT_HARDIRQS) + /* + * With threaded interrupts, we always have IRQ_INPROGRESS + * when acking. + */ + else if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) + move_masked_irq(irq); +#endif } static struct irq_chip ioapic_chip __read_mostly = { - .name = "IO-APIC", - .startup = startup_ioapic_irq, - .mask = mask_IO_APIC_irq, - .unmask = unmask_IO_APIC_irq, - .ack = ack_apic_edge, - .eoi = ack_apic_level, + .name = "IO-APIC", + .startup = startup_ioapic_irq, + .mask = mask_IO_APIC_irq, + .unmask = unmask_IO_APIC_irq, + .ack = ack_apic_edge, + .eoi = ack_apic_level, +#ifdef CONFIG_SMP + .set_affinity = set_ioapic_affinity_irq, +#endif + .retrigger = ioapic_retrigger_irq, +}; + +static struct irq_chip pcix_ioapic_chip __read_mostly = { + .name = "IO-APIC", + .startup = startup_ioapic_irq, + .mask = pcix_mask_IO_APIC_irq, + .unmask = pcix_unmask_IO_APIC_irq, + .ack = ack_apic_edge, + .eoi = ack_apic_level, #ifdef CONFIG_SMP - .set_affinity = set_ioapic_affinity_irq, + .set_affinity = set_ioapic_affinity_irq, #endif .retrigger = ioapic_retrigger_irq, }; @@ -1694,7 +1741,6 @@ */ unmask_IO_APIC_irq(0); if (!no_timer_check && timer_irq_works()) { - nmi_watchdog_default(); if (nmi_watchdog == NMI_IO_APIC) { disable_8259A_irq(0); setup_nmi(); @@ -1720,7 +1766,6 @@ setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector); if (timer_irq_works()) { apic_printk(APIC_VERBOSE," works.\n"); - nmi_watchdog_default(); if (nmi_watchdog == NMI_IO_APIC) { setup_nmi(); } diff -urN linux-2.6.26/arch/x86/kernel/irq_32.c linux-2.6.26-lab126/arch/x86/kernel/irq_32.c --- linux-2.6.26/arch/x86/kernel/irq_32.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/irq_32.c 2010-08-10 04:14:34.000000000 -0400 @@ -16,6 +16,8 @@ #include #include +#include + #include #include @@ -77,6 +79,10 @@ u32 *isp; #endif +#ifdef CONFIG_X86_LOCAL_APIC + irq_show_regs_callback(smp_processor_id(), regs); +#endif + if (unlikely((unsigned)irq >= NR_IRQS)) { printk(KERN_EMERG "%s: cannot handle IRQ %d\n", __func__, irq); @@ -85,6 +91,7 @@ old_regs = set_irq_regs(regs); irq_enter(); + trace_event_irq(irq, user_mode(regs), regs->ip); #ifdef CONFIG_DEBUG_STACKOVERFLOW /* Debugging check for stack overflow: is there less than 1KB free? */ { @@ -93,7 +100,7 @@ __asm__ __volatile__("andl %%esp,%0" : "=r" (sp) : "0" (THREAD_SIZE - 1)); if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) { - printk("do_IRQ: stack overflow: %ld\n", + printk("BUG: do_IRQ: stack overflow: %ld\n", sp - sizeof(struct thread_info)); dump_stack(); } diff -urN linux-2.6.26/arch/x86/kernel/irq_64.c linux-2.6.26-lab126/arch/x86/kernel/irq_64.c --- linux-2.6.26/arch/x86/kernel/irq_64.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/irq_64.c 2010-08-10 04:14:34.000000000 -0400 @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -165,10 +166,14 @@ unsigned vector = ~regs->orig_ax; unsigned irq; + irq_show_regs_callback(smp_processor_id(), regs); + exit_idle(); irq_enter(); irq = __get_cpu_var(vector_irq)[vector]; + trace_event_irq(irq, user_mode(regs), regs->ip); + #ifdef CONFIG_DEBUG_STACKOVERFLOW stack_overflow_check(regs); #endif diff -urN linux-2.6.26/arch/x86/kernel/kprobes.c linux-2.6.26-lab126/arch/x86/kernel/kprobes.c --- linux-2.6.26/arch/x86/kernel/kprobes.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/kprobes.c 2010-08-10 04:14:34.000000000 -0400 @@ -451,7 +451,7 @@ /* Boost up -- we can execute copied instructions directly */ reset_current_kprobe(); regs->ip = (unsigned long)p->ainsn.insn; - preempt_enable_no_resched(); + preempt_enable(); return; } #endif @@ -477,7 +477,7 @@ arch_disarm_kprobe(p); regs->ip = (unsigned long)p->addr; reset_current_kprobe(); - preempt_enable_no_resched(); + preempt_enable(); break; #endif case KPROBE_HIT_ACTIVE: @@ -573,7 +573,7 @@ } } /* else: not a kprobe fault; let the kernel handle it */ - preempt_enable_no_resched(); + preempt_enable(); return 0; } @@ -874,7 +874,7 @@ } reset_current_kprobe(); out: - preempt_enable_no_resched(); + preempt_enable(); /* * if somebody else is singlestepping across a probe point, flags @@ -908,7 +908,7 @@ restore_previous_kprobe(kcb); else reset_current_kprobe(); - preempt_enable_no_resched(); + preempt_enable(); break; case KPROBE_HIT_ACTIVE: case KPROBE_HIT_SSDONE: @@ -1049,7 +1049,7 @@ memcpy((kprobe_opcode_t *)(kcb->jprobe_saved_sp), kcb->jprobes_stack, MIN_STACK_SIZE(kcb->jprobe_saved_sp)); - preempt_enable_no_resched(); + preempt_enable(); return 1; } return 0; diff -urN linux-2.6.26/arch/x86/kernel/microcode.c linux-2.6.26-lab126/arch/x86/kernel/microcode.c --- linux-2.6.26/arch/x86/kernel/microcode.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/microcode.c 2010-08-10 04:14:34.000000000 -0400 @@ -117,7 +117,7 @@ #define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE) /* serialize access to the physical write to MSR 0x79 */ -static DEFINE_SPINLOCK(microcode_update_lock); +static DEFINE_RAW_SPINLOCK(microcode_update_lock); /* no concurrent ->write()s are allowed on /dev/cpu/microcode */ static DEFINE_MUTEX(microcode_mutex); diff -urN linux-2.6.26/arch/x86/kernel/nmi_32.c linux-2.6.26-lab126/arch/x86/kernel/nmi_32.c --- linux-2.6.26/arch/x86/kernel/nmi_32.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/nmi_32.c 2010-08-10 04:14:34.000000000 -0400 @@ -26,6 +26,7 @@ #include #include +#include #include "mach_traps.h" @@ -43,7 +44,7 @@ atomic_t nmi_active = ATOMIC_INIT(0); /* oprofile uses this */ unsigned int nmi_watchdog = NMI_DEFAULT; -static unsigned int nmi_hz = HZ; +static unsigned int nmi_hz = 1000; static DEFINE_PER_CPU(short, wd_enabled); @@ -56,7 +57,12 @@ */ static __init void nmi_cpu_busy(void *data) { + /* + * avoid a warning, on PREEMPT_RT this wont run in hardirq context: + */ +#ifndef CONFIG_PREEMPT_RT local_irq_enable_in_hardirq(); +#endif /* Intentionally don't use cpu_relax here. This is to make sure that the performance counter really ticks, even if there is a simulator or similar that catches the @@ -93,7 +99,7 @@ for_each_possible_cpu(cpu) prev_nmi_count[cpu] = nmi_count(cpu); local_irq_enable(); - mdelay((20*1000)/nmi_hz); // wait 20 ticks + mdelay((100*1000)/nmi_hz); // wait 100 ticks for_each_possible_cpu(cpu) { #ifdef CONFIG_SMP @@ -316,6 +322,58 @@ extern void die_nmi(struct pt_regs *, const char *msg); +int nmi_show_regs[NR_CPUS]; + +static DEFINE_RAW_SPINLOCK(nmi_print_lock); + +notrace int irq_show_regs_callback(int cpu, struct pt_regs *regs) +{ + if (!nmi_show_regs[cpu]) + return 0; + + spin_lock(&nmi_print_lock); + printk(KERN_WARNING "NMI show regs on CPU#%d:\n", cpu); + printk(KERN_WARNING "apic_timer_irqs: %d\n", + per_cpu(irq_stat, cpu).apic_timer_irqs); + show_regs(regs); + spin_unlock(&nmi_print_lock); + nmi_show_regs[cpu] = 0; + return 1; +} + +void nmi_show_all_regs(void) +{ + struct pt_regs *regs; + int i, cpu; + + if (system_state == SYSTEM_BOOTING) + return; + + preempt_disable(); + + regs = get_irq_regs(); + cpu = smp_processor_id(); + + printk(KERN_WARNING "nmi_show_all_regs(): start on CPU#%d.\n", cpu); + dump_stack(); + + for_each_online_cpu(i) + nmi_show_regs[i] = 1; + + if (regs) + irq_show_regs_callback(cpu, regs); + else + nmi_show_regs[cpu] = 0; + + smp_send_nmi_allbutself(); + preempt_enable(); + + for_each_online_cpu(i) { + while (nmi_show_regs[i] == 1) + barrier(); + } +} + notrace __kprobes int nmi_watchdog_tick(struct pt_regs *regs, unsigned reason) { @@ -328,7 +386,10 @@ unsigned int sum; int touched = 0; int cpu = smp_processor_id(); - int rc = 0; + int rc; + + rc = irq_show_regs_callback(cpu, regs); + __profile_tick(CPU_PROFILING, regs); /* check for other users first */ if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT) @@ -338,11 +399,11 @@ } if (cpu_isset(cpu, backtrace_mask)) { - static DEFINE_SPINLOCK(lock); /* Serialise the printks */ + static DEFINE_RAW_SPINLOCK(lock); /* Serialise the printks */ spin_lock(&lock); printk("NMI backtrace for cpu %d\n", cpu); - dump_stack(); + show_regs(regs); spin_unlock(&lock); cpu_clear(cpu, backtrace_mask); } @@ -354,6 +415,7 @@ sum = per_cpu(irq_stat, cpu).apic_timer_irqs + per_cpu(irq_stat, cpu).irq0_irqs; + /* if the apic timer isn't firing, this cpu isn't doing much */ /* if the none of the timers isn't firing, this cpu isn't doing much */ if (!touched && last_irq_sums[cpu] == sum) { /* @@ -361,11 +423,36 @@ * wait a few IRQs (5 seconds) before doing the oops ... */ alert_counter[cpu]++; - if (alert_counter[cpu] == 5*nmi_hz) - /* - * die_nmi will return ONLY if NOTIFY_STOP happens.. - */ - die_nmi(regs, "BUG: NMI Watchdog detected LOCKUP"); + if (alert_counter[cpu] && !(alert_counter[cpu] % (5*nmi_hz))) { + int i; + + spin_lock(&nmi_print_lock); + printk(KERN_WARNING "NMI watchdog detected lockup on " + "CPU#%d (%d/%d)\n", cpu, alert_counter[cpu], + 5*nmi_hz); + show_regs(regs); + spin_unlock(&nmi_print_lock); + + for_each_online_cpu(i) { + if (i == cpu) + continue; + nmi_show_regs[i] = 1; + } + + smp_send_nmi_allbutself(); + + for_each_online_cpu(i) { + if (i == cpu) + continue; + while (nmi_show_regs[i] == 1) + cpu_relax(); + } + printk(KERN_WARNING "NMI watchdog running again ...\n"); + for_each_online_cpu(i) + alert_counter[i] = 0; + + } + } else { last_irq_sums[cpu] = sum; alert_counter[cpu] = 0; @@ -463,5 +550,17 @@ } } +void smp_send_nmi_allbutself(void) +{ +#ifdef CONFIG_SMP + cpumask_t mask = cpu_online_map; + preempt_disable(); + cpu_clear(safe_smp_processor_id(), mask); + if (!cpus_empty(mask)) + send_IPI_mask(mask, NMI_VECTOR); + preempt_enable(); +#endif +} + EXPORT_SYMBOL(nmi_active); EXPORT_SYMBOL(nmi_watchdog); diff -urN linux-2.6.26/arch/x86/kernel/nmi_64.c linux-2.6.26-lab126/arch/x86/kernel/nmi_64.c --- linux-2.6.26/arch/x86/kernel/nmi_64.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/nmi_64.c 2010-08-10 04:14:34.000000000 -0400 @@ -20,11 +20,13 @@ #include #include #include +#include #include #include #include #include +#include #include @@ -44,12 +46,12 @@ static int panic_on_timeout; unsigned int nmi_watchdog = NMI_DEFAULT; -static unsigned int nmi_hz = HZ; +static unsigned int nmi_hz = 1000; static DEFINE_PER_CPU(short, wd_enabled); /* Run after command line and cpu_init init, but before all other checks */ -void nmi_watchdog_default(void) +static void nmi_watchdog_default(void) { if (nmi_watchdog != NMI_DEFAULT) return; @@ -65,7 +67,9 @@ */ static __init void nmi_cpu_busy(void *data) { +#ifndef CONFIG_PREEMPT_RT local_irq_enable_in_hardirq(); +#endif /* Intentionally don't use cpu_relax here. This is to make sure that the performance counter really ticks, even if there is a simulator or similar that catches the @@ -299,7 +303,7 @@ unsigned cpu; /* - * Tell other CPUs to reset their alert counters. We cannot + * Tell other CPUs to reset their alert counters. We cannot * do it ourselves because the alert count increase is not * atomic. */ @@ -313,13 +317,67 @@ } EXPORT_SYMBOL(touch_nmi_watchdog); +int nmi_show_regs[NR_CPUS]; + +static DEFINE_RAW_SPINLOCK(nmi_print_lock); + +notrace int irq_show_regs_callback(int cpu, struct pt_regs *regs) +{ + if (!nmi_show_regs[cpu]) + return 0; + + spin_lock(&nmi_print_lock); + printk(KERN_WARNING "NMI show regs on CPU#%d:\n", cpu); + printk(KERN_WARNING "apic_timer_irqs: %d\n", read_pda(apic_timer_irqs)); + show_regs(regs); + spin_unlock(&nmi_print_lock); + nmi_show_regs[cpu] = 0; + return 1; +} + +void nmi_show_all_regs(void) +{ + struct pt_regs *regs; + int i, cpu; + + if (system_state == SYSTEM_BOOTING) + return; + + preempt_disable(); + + regs = get_irq_regs(); + cpu = smp_processor_id(); + + printk(KERN_WARNING "nmi_show_all_regs(): start on CPU#%d.\n", cpu); + dump_stack(); + + for_each_online_cpu(i) + nmi_show_regs[i] = 1; + + if (regs) + irq_show_regs_callback(cpu, regs); + else + nmi_show_regs[cpu] = 0; + + smp_send_nmi_allbutself(); + preempt_enable(); + + for_each_online_cpu(i) { + while (nmi_show_regs[i] == 1) + barrier(); + } +} + notrace __kprobes int nmi_watchdog_tick(struct pt_regs *regs, unsigned reason) { int sum; int touched = 0; int cpu = smp_processor_id(); - int rc = 0; + int rc; + + rc = irq_show_regs_callback(cpu, regs); + __profile_tick(CPU_PROFILING, regs); /* check for other users first */ if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT) @@ -328,14 +386,13 @@ touched = 1; } - sum = read_pda(apic_timer_irqs) + read_pda(irq0_irqs); if (__get_cpu_var(nmi_touch)) { __get_cpu_var(nmi_touch) = 0; touched = 1; } if (cpu_isset(cpu, backtrace_mask)) { - static DEFINE_SPINLOCK(lock); /* Serialise the printks */ + static DEFINE_RAW_SPINLOCK(lock); /* Serialise the printks */ spin_lock(&lock); printk("NMI backtrace for cpu %d\n", cpu); @@ -344,6 +401,12 @@ cpu_clear(cpu, backtrace_mask); } + /* + * Take the local apic timer and PIT/HPET into account. We don't + * know which one is active, when we have highres/dyntick on + */ + sum = read_pda(apic_timer_irqs) + kstat_cpu(cpu).irqs[0]; + #ifdef CONFIG_X86_MCE /* Could check oops_in_progress here too, but it's safer not too */ @@ -357,9 +420,26 @@ * wait a few IRQs (5 seconds) before doing the oops ... */ local_inc(&__get_cpu_var(alert_counter)); - if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz) + if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz) { + int i; + + for_each_online_cpu(i) { + if (i == cpu) + continue; + nmi_show_regs[i] = 1; + } + + smp_send_nmi_allbutself(); + + for_each_online_cpu(i) { + if (i == cpu) + continue; + while (nmi_show_regs[i] == 1) + cpu_relax(); + } die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs, panic_on_timeout); + } } else { __get_cpu_var(last_irq_sum) = sum; local_set(&__get_cpu_var(alert_counter), 0); @@ -478,5 +558,14 @@ } } +void smp_send_nmi_allbutself(void) +{ +#ifdef CONFIG_SMP + preempt_disable(); + send_IPI_allbutself(NMI_VECTOR); + preempt_enable(); +#endif +} + EXPORT_SYMBOL(nmi_active); EXPORT_SYMBOL(nmi_watchdog); diff -urN linux-2.6.26/arch/x86/kernel/paravirt.c linux-2.6.26-lab126/arch/x86/kernel/paravirt.c --- linux-2.6.26/arch/x86/kernel/paravirt.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/paravirt.c 2010-08-10 04:14:34.000000000 -0400 @@ -350,6 +350,16 @@ #endif }; +#ifdef CONFIG_HIGHPTE +/* + * kmap_atomic() might be an inline or a macro: + */ +static void *kmap_atomic_func(struct page *page, enum km_type idx) +{ + return kmap_atomic(page, idx); +} +#endif + struct pv_mmu_ops pv_mmu_ops = { #ifndef CONFIG_X86_64 .pagetable_setup_start = native_pagetable_setup_start, @@ -381,7 +391,7 @@ .pte_update_defer = paravirt_nop, #ifdef CONFIG_HIGHPTE - .kmap_atomic_pte = kmap_atomic, + .kmap_atomic_pte = kmap_atomic_func, #endif #if PAGETABLE_LEVELS >= 3 diff -urN linux-2.6.26/arch/x86/kernel/process.c linux-2.6.26-lab126/arch/x86/kernel/process.c --- linux-2.6.26/arch/x86/kernel/process.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/process.c 2010-08-10 04:14:34.000000000 -0400 @@ -107,7 +107,9 @@ static void poll_idle(void) { local_irq_enable(); - cpu_relax(); + do { + cpu_relax(); + } while (!need_resched()); } /* diff -urN linux-2.6.26/arch/x86/kernel/process_32.c linux-2.6.26-lab126/arch/x86/kernel/process_32.c --- linux-2.6.26/arch/x86/kernel/process_32.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/process_32.c 2010-08-10 04:14:34.000000000 -0400 @@ -166,7 +166,7 @@ /* endless idle loop with no priority at all */ while (1) { - tick_nohz_stop_sched_tick(); + tick_nohz_stop_sched_tick(1); while (!need_resched()) { void (*idle)(void); @@ -185,12 +185,17 @@ local_irq_disable(); __get_cpu_var(irq_stat).idle_timestamp = jiffies; + /* Don't trace irqs off for idle */ + stop_critical_timings(); idle(); + start_critical_timings(); } + local_irq_disable(); tick_nohz_restart_sched_tick(); - preempt_enable_no_resched(); - schedule(); + __preempt_enable_no_resched(); + __schedule(); preempt_disable(); + local_irq_enable(); } } @@ -227,8 +232,10 @@ regs->ax, regs->bx, regs->cx, regs->dx); printk("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n", regs->si, regs->di, regs->bp, sp); - printk(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n", - (u16)regs->ds, (u16)regs->es, (u16)regs->fs, gs, ss); + printk(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x" + " preempt:%08x\n", + (u16)regs->ds, (u16)regs->es, (u16)regs->fs, gs, ss, + preempt_count()); if (!all) return; @@ -300,15 +307,23 @@ if (unlikely(test_thread_flag(TIF_IO_BITMAP))) { struct task_struct *tsk = current; struct thread_struct *t = &tsk->thread; - int cpu = get_cpu(); - struct tss_struct *tss = &per_cpu(init_tss, cpu); + void *io_bitmap_ptr = t->io_bitmap_ptr; + int cpu; + struct tss_struct *tss; - kfree(t->io_bitmap_ptr); + /* + * On PREEMPT_RT we must not call kfree() with + * preemption disabled, so we first zap the pointer: + */ t->io_bitmap_ptr = NULL; + kfree(io_bitmap_ptr); + clear_thread_flag(TIF_IO_BITMAP); /* * Careful, clear this in the TSS too: */ + cpu = get_cpu(); + tss = &per_cpu(init_tss, cpu); memset(tss->io_bitmap, 0xff, tss->io_bitmap_max); t->io_bitmap_max = 0; tss->io_bitmap_owner = NULL; diff -urN linux-2.6.26/arch/x86/kernel/process_64.c linux-2.6.26-lab126/arch/x86/kernel/process_64.c --- linux-2.6.26/arch/x86/kernel/process_64.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/process_64.c 2010-08-10 04:14:34.000000000 -0400 @@ -148,7 +148,7 @@ current_thread_info()->status |= TS_POLLING; /* endless idle loop with no priority at all */ while (1) { - tick_nohz_stop_sched_tick(); + tick_nohz_stop_sched_tick(1); while (!need_resched()) { void (*idle)(void); diff -urN linux-2.6.26/arch/x86/kernel/setup64.c linux-2.6.26-lab126/arch/x86/kernel/setup64.c --- linux-2.6.26/arch/x86/kernel/setup64.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/setup64.c 2010-08-10 04:14:34.000000000 -0400 @@ -222,7 +222,9 @@ for (v = 0; v < N_EXCEPTION_STACKS; v++) { static const unsigned int order[N_EXCEPTION_STACKS] = { [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER, +#if DEBUG_STACK > 0 [DEBUG_STACK - 1] = DEBUG_STACK_ORDER +#endif }; if (cpu) { estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]); diff -urN linux-2.6.26/arch/x86/kernel/setup_64.c linux-2.6.26-lab126/arch/x86/kernel/setup_64.c --- linux-2.6.26/arch/x86/kernel/setup_64.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/setup_64.c 2010-08-10 04:14:34.000000000 -0400 @@ -444,6 +444,12 @@ contig_initmem_init(0, end_pfn); #endif + /* + * dma32_reserve_bootmem() allocates bootmem which may conflict + * with the crashkernel command line, so do that before + */ + reserve_crashkernel(); + dma32_reserve_bootmem(); #ifdef CONFIG_ACPI_SLEEP @@ -484,7 +490,6 @@ } } #endif - reserve_crashkernel(); reserve_ibft_region(); diff -urN linux-2.6.26/arch/x86/kernel/signal_32.c linux-2.6.26-lab126/arch/x86/kernel/signal_32.c --- linux-2.6.26/arch/x86/kernel/signal_32.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/signal_32.c 2010-08-10 04:14:34.000000000 -0400 @@ -583,6 +583,13 @@ int signr; sigset_t *oldset; +#ifdef CONFIG_PREEMPT_RT + /* + * Fully-preemptible kernel does not need interrupts disabled: + */ + local_irq_enable(); + preempt_check_resched(); +#endif /* * We want the common case to go fast, which is why we may in certain * cases get here from kernel mode. Just return without doing anything diff -urN linux-2.6.26/arch/x86/kernel/signal_64.c linux-2.6.26-lab126/arch/x86/kernel/signal_64.c --- linux-2.6.26/arch/x86/kernel/signal_64.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/signal_64.c 2010-08-10 04:14:34.000000000 -0400 @@ -417,6 +417,13 @@ int signr; sigset_t *oldset; +#ifdef CONFIG_PREEMPT_RT + /* + * Fully-preemptible kernel does not need interrupts disabled: + */ + local_irq_enable(); + preempt_check_resched(); +#endif /* * We want the common case to go fast, which is why we may in certain * cases get here from kernel mode. Just return without doing anything diff -urN linux-2.6.26/arch/x86/kernel/smp.c linux-2.6.26-lab126/arch/x86/kernel/smp.c --- linux-2.6.26/arch/x86/kernel/smp.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/smp.c 2010-08-10 04:14:34.000000000 -0400 @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -122,10 +123,28 @@ } /* + * this function sends a 'reschedule' IPI to all other CPUs. + * This is used when RT tasks are starving and other CPUs + * might be able to run them: + */ +void smp_send_reschedule_allbutself(void) +{ + send_IPI_allbutself(RESCHEDULE_VECTOR); +} + +void smp_send_reschedule_allbutself_cpumask(cpumask_t mask) +{ + cpu_clear(smp_processor_id(), mask); + cpus_and(mask, mask, cpu_online_map); + if (!cpus_empty(mask)) + send_IPI_mask(mask, RESCHEDULE_VECTOR); +} + +/* * Structure and data for smp_call_function(). This is designed to minimise * static memory requirements. It also looks cleaner. */ -static DEFINE_SPINLOCK(call_lock); +static DEFINE_RAW_SPINLOCK(call_lock); struct call_data_struct { void (*func) (void *info); diff -urN linux-2.6.26/arch/x86/kernel/smpboot.c linux-2.6.26-lab126/arch/x86/kernel/smpboot.c --- linux-2.6.26/arch/x86/kernel/smpboot.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/smpboot.c 2010-08-10 04:14:34.000000000 -0400 @@ -1190,7 +1190,6 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus) { preempt_disable(); - nmi_watchdog_default(); smp_cpu_index_default(); current_cpu_data = boot_cpu_data; cpu_callin_map = cpumask_of_cpu(0); diff -urN linux-2.6.26/arch/x86/kernel/time_64.c linux-2.6.26-lab126/arch/x86/kernel/time_64.c --- linux-2.6.26/arch/x86/kernel/time_64.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/time_64.c 2010-08-10 04:14:34.000000000 -0400 @@ -101,7 +101,8 @@ static struct irqaction irq0 = { .handler = timer_event_interrupt, - .flags = IRQF_DISABLED | IRQF_IRQPOLL | IRQF_NOBALANCING, + .flags = IRQF_DISABLED | IRQF_IRQPOLL | IRQF_NOBALANCING | + IRQF_NODELAY, .mask = CPU_MASK_NONE, .name = "timer" }; diff -urN linux-2.6.26/arch/x86/kernel/tlb_32.c linux-2.6.26-lab126/arch/x86/kernel/tlb_32.c --- linux-2.6.26/arch/x86/kernel/tlb_32.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/tlb_32.c 2010-08-10 04:14:34.000000000 -0400 @@ -23,7 +23,7 @@ static cpumask_t flush_cpumask; static struct mm_struct *flush_mm; static unsigned long flush_va; -static DEFINE_SPINLOCK(tlbstate_lock); +static DEFINE_RAW_SPINLOCK(tlbstate_lock); /* * We cannot call mmdrop() because we are in interrupt context, diff -urN linux-2.6.26/arch/x86/kernel/tlb_64.c linux-2.6.26-lab126/arch/x86/kernel/tlb_64.c --- linux-2.6.26/arch/x86/kernel/tlb_64.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/tlb_64.c 2010-08-10 04:14:34.000000000 -0400 @@ -44,7 +44,7 @@ cpumask_t flush_cpumask; struct mm_struct *flush_mm; unsigned long flush_va; - spinlock_t tlbstate_lock; + raw_spinlock_t tlbstate_lock; }; char pad[SMP_CACHE_BYTES]; } ____cacheline_aligned; diff -urN linux-2.6.26/arch/x86/kernel/traps_32.c linux-2.6.26-lab126/arch/x86/kernel/traps_32.c --- linux-2.6.26/arch/x86/kernel/traps_32.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/traps_32.c 2010-08-10 04:14:34.000000000 -0400 @@ -31,6 +31,7 @@ #include #include #include +#include #ifdef CONFIG_EISA #include @@ -260,6 +261,8 @@ { dump_trace(task, regs, stack, bp, &print_trace_ops, log_lvl); printk("%s =======================\n", log_lvl); + print_preempt_trace(task); + debug_show_held_locks(task); } void show_trace(struct task_struct *task, struct pt_regs *regs, @@ -290,9 +293,15 @@ printk("\n%s ", log_lvl); printk("%08lx ", *stack++); } + + pause_on_oops_head(); + printk("\n%sCall Trace:\n", log_lvl); show_trace_log_lvl(task, regs, sp, bp, log_lvl); + + pause_on_oops_tail(); + } void show_stack(struct task_struct *task, unsigned long *sp) @@ -325,6 +334,12 @@ EXPORT_SYMBOL(dump_stack); +#if defined(CONFIG_DEBUG_STACKOVERFLOW) && defined(CONFIG_EVENT_TRACE) +extern unsigned long worst_stack_left; +#else +# define worst_stack_left -1L +#endif + void show_registers(struct pt_regs *regs) { int i; @@ -391,6 +406,8 @@ unsigned short ss; unsigned long sp; + ftrace_halt(); + printk(KERN_EMERG "%s: %04lx [#%d] ", str, err & 0xffff, ++die_counter); #ifdef CONFIG_PREEMPT printk("PREEMPT "); @@ -435,7 +452,7 @@ u32 lock_owner; int lock_owner_depth; } die = { - .lock = __RAW_SPIN_LOCK_UNLOCKED, + .lock = RAW_SPIN_LOCK_UNLOCKED(die.lock), .lock_owner = -1, .lock_owner_depth = 0 }; @@ -446,7 +463,7 @@ if (die.lock_owner != raw_smp_processor_id()) { console_verbose(); raw_local_irq_save(flags); - __raw_spin_lock(&die.lock); + spin_lock(&die.lock); die.lock_owner = smp_processor_id(); die.lock_owner_depth = 0; bust_spinlocks(1); @@ -466,7 +483,7 @@ bust_spinlocks(0); die.lock_owner = -1; add_taint(TAINT_DIE); - __raw_spin_unlock(&die.lock); + spin_unlock(&die.lock); raw_local_irq_restore(flags); if (!regs) @@ -507,6 +524,11 @@ if (!user_mode(regs)) goto kernel_trap; +#ifdef CONFIG_PREEMPT_RT + local_irq_enable(); + preempt_check_resched(); +#endif + trap_signal: /* * We want error_code and trap_no set for userspace faults and @@ -784,6 +806,7 @@ crash_kexec(regs); } + nmi_exit(); do_exit(SIGSEGV); } @@ -835,6 +858,8 @@ nmi_enter(); + trace_event_irq(-1, user_mode(regs), regs->ip); + cpu = smp_processor_id(); ++nmi_count(cpu); diff -urN linux-2.6.26/arch/x86/kernel/traps_64.c linux-2.6.26-lab126/arch/x86/kernel/traps_64.c --- linux-2.6.26/arch/x86/kernel/traps_64.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/traps_64.c 2010-08-10 04:14:34.000000000 -0400 @@ -32,6 +32,7 @@ #include #include #include +#include #include @@ -84,20 +85,22 @@ local_irq_enable(); } -static inline void preempt_conditional_sti(struct pt_regs *regs) +static inline void preempt_conditional_sti(struct pt_regs *regs, int stack) { - inc_preempt_count(); + if (stack) + inc_preempt_count(); if (regs->flags & X86_EFLAGS_IF) local_irq_enable(); } -static inline void preempt_conditional_cli(struct pt_regs *regs) +static inline void preempt_conditional_cli(struct pt_regs *regs, int stack) { if (regs->flags & X86_EFLAGS_IF) local_irq_disable(); /* Make sure to not schedule here because we could be running on an exception stack. */ - dec_preempt_count(); + if (stack) + dec_preempt_count(); } int kstack_depth_to_print = 12; @@ -134,10 +137,14 @@ unsigned *usedp, char **idp) { static char ids[][8] = { +#if DEBUG_STACK > 0 [DEBUG_STACK - 1] = "#DB", +#endif [NMI_STACK - 1] = "NMI", [DOUBLEFAULT_STACK - 1] = "#DF", +#if STACKFAULT_STACK > 0 [STACKFAULT_STACK - 1] = "#SS", +#endif [MCE_STACK - 1] = "#MC", #if DEBUG_STKSZ > EXCEPTION_STKSZ [N_EXCEPTION_STACKS ... N_EXCEPTION_STACKS + DEBUG_STKSZ / EXCEPTION_STKSZ - 2] = "#DB[?]" @@ -262,7 +269,7 @@ unsigned long *stack, unsigned long bp, const struct stacktrace_ops *ops, void *data) { - const unsigned cpu = get_cpu(); + const unsigned cpu = raw_smp_processor_id(); unsigned long *irqstack_end = (unsigned long*)cpu_pda(cpu)->irqstackptr; unsigned used = 0; struct thread_info *tinfo; @@ -346,7 +353,6 @@ * This handles the process stack: */ bp = print_context_stack(tinfo, stack, bp, ops, data, NULL); - put_cpu(); } EXPORT_SYMBOL(dump_trace); @@ -385,9 +391,13 @@ show_trace(struct task_struct *tsk, struct pt_regs *regs, unsigned long *stack, unsigned long bp) { + pause_on_oops_head(); printk("\nCall Trace:\n"); dump_trace(tsk, regs, stack, bp, &print_trace_ops, NULL); printk("\n"); + debug_show_held_locks(tsk); + pause_on_oops_tail(); + print_preempt_trace(tsk); } static void @@ -396,7 +406,7 @@ { unsigned long *stack; int i; - const int cpu = smp_processor_id(); + const int cpu = raw_smp_processor_id(); unsigned long *irqstack_end = (unsigned long *) (cpu_pda(cpu)->irqstackptr); unsigned long *irqstack = (unsigned long *) (cpu_pda(cpu)->irqstackptr - IRQSTACKSIZE); @@ -515,7 +525,7 @@ return ud2 == 0x0b0f; } -static raw_spinlock_t die_lock = __RAW_SPIN_LOCK_UNLOCKED; +static raw_spinlock_t die_lock = RAW_SPIN_LOCK_UNLOCKED(die_lock); static int die_owner = -1; static unsigned int die_nest_count; @@ -529,11 +539,11 @@ /* racy, but better than risking deadlock. */ raw_local_irq_save(flags); cpu = smp_processor_id(); - if (!__raw_spin_trylock(&die_lock)) { + if (!spin_trylock(&die_lock)) { if (cpu == die_owner) /* nested oops. should stop eventually */; else - __raw_spin_lock(&die_lock); + spin_lock(&die_lock); } die_nest_count++; die_owner = cpu; @@ -549,7 +559,7 @@ die_nest_count--; if (!die_nest_count) /* Nest count reaches zero, release the lock. */ - __raw_spin_unlock(&die_lock); + spin_unlock(&die_lock); raw_local_irq_restore(flags); if (!regs) { oops_exit(); @@ -564,6 +574,9 @@ int __kprobes __die(const char * str, struct pt_regs * regs, long err) { static int die_counter; + + ftrace_halt(); + printk(KERN_EMERG "%s: %04lx [%u] ", str, err & 0xffff,++die_counter); #ifdef CONFIG_PREEMPT printk("PREEMPT "); @@ -715,9 +728,9 @@ if (notify_die(DIE_TRAP, "stack segment", regs, error_code, 12, SIGBUS) == NOTIFY_STOP) return; - preempt_conditional_sti(regs); + preempt_conditional_sti(regs, STACKFAULT_STACK); do_trap(12, SIGBUS, "stack segment", regs, error_code, NULL); - preempt_conditional_cli(regs); + preempt_conditional_cli(regs, STACKFAULT_STACK); } asmlinkage void do_double_fault(struct pt_regs * regs, long error_code) @@ -835,6 +848,8 @@ cpu = smp_processor_id(); + trace_event_irq(-1, user_mode(regs), regs->ip); + /* Only the BSP gets external NMIs from the system. */ if (!cpu) reason = get_nmi_reason(); @@ -873,9 +888,9 @@ if (notify_die(DIE_INT3, "int3", regs, error_code, 3, SIGTRAP) == NOTIFY_STOP) { return; } - preempt_conditional_sti(regs); + preempt_conditional_sti(regs, DEBUG_STACK); do_trap(3, SIGTRAP, "int3", regs, error_code, NULL); - preempt_conditional_cli(regs); + preempt_conditional_cli(regs, DEBUG_STACK); } /* Help handler running on IST stack to switch back to user stack @@ -921,7 +936,7 @@ SIGTRAP) == NOTIFY_STOP) return; - preempt_conditional_sti(regs); + preempt_conditional_sti(regs, DEBUG_STACK); /* Mask out spurious debug traps due to lazy DR7 setting */ if (condition & (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3)) { @@ -953,13 +968,13 @@ clear_dr7: set_debugreg(0UL, 7); - preempt_conditional_cli(regs); + preempt_conditional_cli(regs, DEBUG_STACK); return; clear_TF_reenable: set_tsk_thread_flag(tsk, TIF_SINGLESTEP); regs->flags &= ~X86_EFLAGS_TF; - preempt_conditional_cli(regs); + preempt_conditional_cli(regs, DEBUG_STACK); } static int kernel_math_error(struct pt_regs *regs, const char *str, int trapnr) diff -urN linux-2.6.26/arch/x86/kernel/tsc_32.c linux-2.6.26-lab126/arch/x86/kernel/tsc_32.c --- linux-2.6.26/arch/x86/kernel/tsc_32.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/tsc_32.c 2010-08-10 04:14:34.000000000 -0400 @@ -111,7 +111,7 @@ /* * Scheduler clock - returns current time in nanosec units. */ -unsigned long long native_sched_clock(void) +unsigned long long notrace native_sched_clock(void) { unsigned long long this_offset; diff -urN linux-2.6.26/arch/x86/kernel/tsc_sync.c linux-2.6.26-lab126/arch/x86/kernel/tsc_sync.c --- linux-2.6.26/arch/x86/kernel/tsc_sync.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/tsc_sync.c 2010-08-10 04:14:34.000000000 -0400 @@ -33,7 +33,7 @@ * we want to have the fastest, inlined, non-debug version * of a critical section, to be able to prove TSC time-warps: */ -static __cpuinitdata raw_spinlock_t sync_lock = __RAW_SPIN_LOCK_UNLOCKED; +static __cpuinitdata __raw_spinlock_t sync_lock = __RAW_SPIN_LOCK_UNLOCKED; static __cpuinitdata cycles_t last_tsc; static __cpuinitdata cycles_t max_warp; static __cpuinitdata int nr_warps; @@ -101,6 +101,7 @@ */ void __cpuinit check_tsc_sync_source(int cpu) { + unsigned long flags; int cpus = 2; /* @@ -121,8 +122,11 @@ /* * Wait for the target to arrive: */ + local_save_flags(flags); + local_irq_enable(); while (atomic_read(&start_count) != cpus-1) cpu_relax(); + local_irq_restore(flags); /* * Trigger the target to continue into the measurement too: */ diff -urN linux-2.6.26/arch/x86/kernel/vm86_32.c linux-2.6.26-lab126/arch/x86/kernel/vm86_32.c --- linux-2.6.26/arch/x86/kernel/vm86_32.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/vm86_32.c 2010-08-10 04:14:34.000000000 -0400 @@ -136,6 +136,7 @@ local_irq_enable(); if (!current->thread.vm86_info) { + local_irq_disable(); printk("no vm86_info: BAD\n"); do_exit(SIGSEGV); } diff -urN linux-2.6.26/arch/x86/kernel/vsyscall_64.c linux-2.6.26-lab126/arch/x86/kernel/vsyscall_64.c --- linux-2.6.26/arch/x86/kernel/vsyscall_64.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/vsyscall_64.c 2010-08-10 04:14:34.000000000 -0400 @@ -42,7 +42,8 @@ #include #include -#define __vsyscall(nr) __attribute__ ((unused,__section__(".vsyscall_" #nr))) +#define __vsyscall(nr) \ + __attribute__ ((unused, __section__(".vsyscall_" #nr))) notrace #define __syscall_clobber "r11","cx","memory" /* @@ -55,7 +56,7 @@ struct vsyscall_gtod_data __vsyscall_gtod_data __section_vsyscall_gtod_data = { - .lock = SEQLOCK_UNLOCKED, + .lock = __RAW_SEQLOCK_UNLOCKED(__vsyscall_gtod_data.lock), .sysctl_enabled = 1, }; @@ -74,14 +75,40 @@ unsigned long flags; write_seqlock_irqsave(&vsyscall_gtod_data.lock, flags); + + if (likely(vsyscall_gtod_data.sysctl_enabled == 2)) { + struct timespec tmp = *(wall_time); + cycle_t (*vread)(void); + cycle_t now; + + vread = vsyscall_gtod_data.clock.vread; + if (likely(vread)) + now = vread(); + else + now = clock->read(); + + /* calculate interval: */ + now = (now - clock->cycle_last) & clock->mask; + /* convert to nsecs: */ + tmp.tv_nsec += ( now * clock->mult) >> clock->shift; + + while (tmp.tv_nsec >= NSEC_PER_SEC) { + tmp.tv_sec += 1; + tmp.tv_nsec -= NSEC_PER_SEC; + } + + vsyscall_gtod_data.wall_time_sec = tmp.tv_sec; + vsyscall_gtod_data.wall_time_nsec = tmp.tv_nsec; + } else { + vsyscall_gtod_data.wall_time_sec = wall_time->tv_sec; + vsyscall_gtod_data.wall_time_nsec = wall_time->tv_nsec; + } /* copy vsyscall data */ vsyscall_gtod_data.clock.vread = clock->vread; vsyscall_gtod_data.clock.cycle_last = clock->cycle_last; vsyscall_gtod_data.clock.mask = clock->mask; vsyscall_gtod_data.clock.mult = clock->mult; vsyscall_gtod_data.clock.shift = clock->shift; - vsyscall_gtod_data.wall_time_sec = wall_time->tv_sec; - vsyscall_gtod_data.wall_time_nsec = wall_time->tv_nsec; vsyscall_gtod_data.wall_to_monotonic = wall_to_monotonic; write_sequnlock_irqrestore(&vsyscall_gtod_data.lock, flags); } @@ -119,6 +146,26 @@ unsigned seq; unsigned long mult, shift, nsec; cycle_t (*vread)(void); + + if (likely(__vsyscall_gtod_data.sysctl_enabled == 2)) { + struct timeval tmp; + + do { + barrier(); + tv->tv_sec = __vsyscall_gtod_data.wall_time_sec; + tv->tv_usec = __vsyscall_gtod_data.wall_time_nsec; + barrier(); + tmp.tv_sec = __vsyscall_gtod_data.wall_time_sec; + tmp.tv_usec = __vsyscall_gtod_data.wall_time_nsec; + + } while (tmp.tv_usec != tv->tv_usec || + tmp.tv_sec != tv->tv_sec); + + tv->tv_usec /= NSEC_PER_MSEC; + tv->tv_usec *= USEC_PER_MSEC; + return; + } + do { seq = read_seqbegin(&__vsyscall_gtod_data.lock); @@ -127,7 +174,6 @@ gettimeofday(tv,NULL); return; } - now = vread(); base = __vsyscall_gtod_data.clock.cycle_last; mask = __vsyscall_gtod_data.clock.mask; mult = __vsyscall_gtod_data.clock.mult; @@ -137,6 +183,7 @@ nsec = __vsyscall_gtod_data.wall_time_nsec; } while (read_seqretry(&__vsyscall_gtod_data.lock, seq)); + now = vread(); /* calculate interval: */ cycle_delta = (now - base) & mask; /* convert to nsecs: */ diff -urN linux-2.6.26/arch/x86/kernel/x8664_ksyms_64.c linux-2.6.26-lab126/arch/x86/kernel/x8664_ksyms_64.c --- linux-2.6.26/arch/x86/kernel/x8664_ksyms_64.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/kernel/x8664_ksyms_64.c 2010-08-10 04:14:34.000000000 -0400 @@ -9,6 +9,12 @@ #include #include #include +#include + +#ifdef CONFIG_FTRACE +/* mcount is defined in assembly */ +EXPORT_SYMBOL(mcount); +#endif EXPORT_SYMBOL(kernel_thread); diff -urN linux-2.6.26/arch/x86/lib/Makefile linux-2.6.26-lab126/arch/x86/lib/Makefile --- linux-2.6.26/arch/x86/lib/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/lib/Makefile 2010-08-10 04:14:37.000000000 -0400 @@ -5,6 +5,7 @@ obj-$(CONFIG_SMP) := msr-on-cpu.o lib-y := delay_$(BITS).o +lib-y += thunk_$(BITS).o lib-y += usercopy_$(BITS).o getuser_$(BITS).o putuser_$(BITS).o lib-y += memcpy_$(BITS).o diff -urN linux-2.6.26/arch/x86/lib/thunk_32.S linux-2.6.26-lab126/arch/x86/lib/thunk_32.S --- linux-2.6.26/arch/x86/lib/thunk_32.S 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/arch/x86/lib/thunk_32.S 2010-08-10 04:14:37.000000000 -0400 @@ -0,0 +1,47 @@ +/* + * Trampoline to trace irqs off. (otherwise CALLER_ADDR1 might crash) + * Copyright 2008 by Steven Rostedt, Red Hat, Inc + * (inspired by Andi Kleen's thunk_64.S) + * Subject to the GNU public license, v.2. No warranty of any kind. + */ + + #include + +#define ARCH_TRACE_IRQS_ON \ + pushl %eax; \ + pushl %ecx; \ + pushl %edx; \ + call trace_hardirqs_on; \ + popl %edx; \ + popl %ecx; \ + popl %eax; + +#define ARCH_TRACE_IRQS_OFF \ + pushl %eax; \ + pushl %ecx; \ + pushl %edx; \ + call trace_hardirqs_off; \ + popl %edx; \ + popl %ecx; \ + popl %eax; + +#ifdef CONFIG_TRACE_IRQFLAGS + /* put return address in eax (arg1) */ + .macro thunk_ra name,func + .globl \name +\name: + pushl %eax + pushl %ecx + pushl %edx + /* Place EIP in the arg1 */ + movl 3*4(%esp), %eax + call \func + popl %edx + popl %ecx + popl %eax + ret + .endm + + thunk_ra trace_hardirqs_on_thunk,trace_hardirqs_on_caller + thunk_ra trace_hardirqs_off_thunk,trace_hardirqs_off_caller +#endif diff -urN linux-2.6.26/arch/x86/lib/thunk_64.S linux-2.6.26-lab126/arch/x86/lib/thunk_64.S --- linux-2.6.26/arch/x86/lib/thunk_64.S 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/lib/thunk_64.S 2010-08-10 04:14:37.000000000 -0400 @@ -2,6 +2,7 @@ * Save registers before calling assembly functions. This avoids * disturbance of register allocation in some inline assembly constructs. * Copyright 2001,2002 by Andi Kleen, SuSE Labs. + * Added trace_hardirqs callers - Copyright 2007 Steven Rostedt, Red Hat, Inc. * Subject to the GNU public license, v.2. No warranty of any kind. */ @@ -42,8 +43,22 @@ #endif #ifdef CONFIG_TRACE_IRQFLAGS - thunk trace_hardirqs_on_thunk,trace_hardirqs_on - thunk trace_hardirqs_off_thunk,trace_hardirqs_off + /* put return address in rdi (arg1) */ + .macro thunk_ra name,func + .globl \name +\name: + CFI_STARTPROC + SAVE_ARGS + /* SAVE_ARGS pushs 9 elements */ + /* the next element would be the rip */ + movq 9*8(%rsp), %rdi + call \func + jmp restore + CFI_ENDPROC + .endm + + thunk_ra trace_hardirqs_on_thunk,trace_hardirqs_on_caller + thunk_ra trace_hardirqs_off_thunk,trace_hardirqs_off_caller #endif #ifdef CONFIG_DEBUG_LOCK_ALLOC diff -urN linux-2.6.26/arch/x86/mach-default/setup.c linux-2.6.26-lab126/arch/x86/mach-default/setup.c --- linux-2.6.26/arch/x86/mach-default/setup.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/mach-default/setup.c 2010-08-10 04:14:35.000000000 -0400 @@ -37,6 +37,7 @@ */ static struct irqaction irq2 = { .handler = no_action, + .flags = IRQF_NODELAY, .mask = CPU_MASK_NONE, .name = "cascade", }; @@ -85,7 +86,7 @@ static struct irqaction irq0 = { .handler = timer_interrupt, - .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_IRQPOLL, + .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_IRQPOLL | IRQF_NODELAY, .mask = CPU_MASK_NONE, .name = "timer" }; diff -urN linux-2.6.26/arch/x86/mach-visws/visws_apic.c linux-2.6.26-lab126/arch/x86/mach-visws/visws_apic.c --- linux-2.6.26/arch/x86/mach-visws/visws_apic.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/mach-visws/visws_apic.c 2010-08-10 04:14:35.000000000 -0400 @@ -255,11 +255,13 @@ static struct irqaction master_action = { .handler = piix4_master_intr, .name = "PIIX4-8259", + .flags = IRQF_NODELAY, }; static struct irqaction cascade_action = { .handler = no_action, .name = "cascade", + .flags = IRQF_NODELAY, }; diff -urN linux-2.6.26/arch/x86/mach-voyager/setup.c linux-2.6.26-lab126/arch/x86/mach-voyager/setup.c --- linux-2.6.26/arch/x86/mach-voyager/setup.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/mach-voyager/setup.c 2010-08-10 04:14:35.000000000 -0400 @@ -20,6 +20,7 @@ */ static struct irqaction irq2 = { .handler = no_action, + .flags = IRQF_NODELAY, .mask = CPU_MASK_NONE, .name = "cascade", }; @@ -46,7 +47,7 @@ static struct irqaction irq0 = { .handler = timer_interrupt, - .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_IRQPOLL, + .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_IRQPOLL | IRQF_NODELAY, .mask = CPU_MASK_NONE, .name = "timer" }; diff -urN linux-2.6.26/arch/x86/mm/fault.c linux-2.6.26-lab126/arch/x86/mm/fault.c --- linux-2.6.26/arch/x86/mm/fault.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/mm/fault.c 2010-08-10 04:14:37.000000000 -0400 @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -363,6 +364,7 @@ nr = (address - idt_descr.address) >> 3; if (nr == 6) { + zap_rt_locks(); do_invalid_op(regs, 0); return 1; } @@ -602,6 +604,8 @@ /* get the address */ address = read_cr2(); + trace_event_fault(regs->ip, error_code, address); + si_code = SEGV_MAPERR; if (notify_page_fault(regs)) @@ -651,7 +655,7 @@ * If we're in an interrupt, have no user context or are running in an * atomic region then we must not take the fault. */ - if (in_atomic() || !mm) + if (unlikely(in_atomic() || !mm || current->pagefault_disabled)) goto bad_area_nosemaphore; #else /* CONFIG_X86_64 */ if (likely(regs->flags & X86_EFLAGS_IF)) diff -urN linux-2.6.26/arch/x86/mm/highmem_32.c linux-2.6.26-lab126/arch/x86/mm/highmem_32.c --- linux-2.6.26/arch/x86/mm/highmem_32.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/mm/highmem_32.c 2010-08-10 04:14:37.000000000 -0400 @@ -3,9 +3,9 @@ void *kmap(struct page *page) { - might_sleep(); if (!PageHighMem(page)) return page_address(page); + might_sleep(); return kmap_high(page); } @@ -18,6 +18,27 @@ kunmap_high(page); } +void kunmap_virt(void *ptr) +{ + struct page *page; + + if ((unsigned long)ptr < PKMAP_ADDR(0)) + return; + page = pte_page(pkmap_page_table[PKMAP_NR((unsigned long)ptr)]); + kunmap(page); +} + +struct page *kmap_to_page(void *ptr) +{ + struct page *page; + + if ((unsigned long)ptr < PKMAP_ADDR(0)) + return virt_to_page(ptr); + page = pte_page(pkmap_page_table[PKMAP_NR((unsigned long)ptr)]); + return page; +} +EXPORT_SYMBOL_GPL(kmap_to_page); /* PREEMPT_RT converts some modules to use this */ + static void debug_kmap_atomic_prot(enum km_type type) { #ifdef CONFIG_DEBUG_HIGHMEM @@ -69,12 +90,12 @@ * However when holding an atomic kmap is is not legal to sleep, so atomic * kmaps are appropriate for short, tight code paths only. */ -void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot) +void *__kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot) { enum fixed_addresses idx; unsigned long vaddr; - /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */ + preempt_disable(); pagefault_disable(); if (!PageHighMem(page)) @@ -84,19 +105,19 @@ idx = type + KM_TYPE_NR*smp_processor_id(); vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); - BUG_ON(!pte_none(*(kmap_pte-idx))); + WARN_ON_ONCE(!pte_none(*(kmap_pte-idx))); set_pte(kmap_pte-idx, mk_pte(page, prot)); arch_flush_lazy_mmu_mode(); return (void *)vaddr; } -void *kmap_atomic(struct page *page, enum km_type type) +void *__kmap_atomic(struct page *page, enum km_type type) { return kmap_atomic_prot(page, type, kmap_prot); } -void kunmap_atomic(void *kvaddr, enum km_type type) +void __kunmap_atomic(void *kvaddr, enum km_type type) { unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id(); @@ -118,16 +139,18 @@ arch_flush_lazy_mmu_mode(); pagefault_enable(); + preempt_enable(); } /* This is the same as kmap_atomic() but can map memory that doesn't * have a struct page associated with it. */ -void *kmap_atomic_pfn(unsigned long pfn, enum km_type type) +void *__kmap_atomic_pfn(unsigned long pfn, enum km_type type) { enum fixed_addresses idx; unsigned long vaddr; + preempt_disable(); pagefault_disable(); idx = type + KM_TYPE_NR*smp_processor_id(); @@ -138,7 +161,7 @@ return (void*) vaddr; } -struct page *kmap_atomic_to_page(void *ptr) +struct page *__kmap_atomic_to_page(void *ptr) { unsigned long idx, vaddr = (unsigned long)ptr; pte_t *pte; @@ -153,5 +176,6 @@ EXPORT_SYMBOL(kmap); EXPORT_SYMBOL(kunmap); -EXPORT_SYMBOL(kmap_atomic); -EXPORT_SYMBOL(kunmap_atomic); +EXPORT_SYMBOL(kunmap_virt); +EXPORT_SYMBOL(__kmap_atomic); +EXPORT_SYMBOL(__kunmap_atomic); diff -urN linux-2.6.26/arch/x86/mm/init_32.c linux-2.6.26-lab126/arch/x86/mm/init_32.c --- linux-2.6.26/arch/x86/mm/init_32.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/mm/init_32.c 2010-08-10 04:14:37.000000000 -0400 @@ -52,7 +52,7 @@ unsigned long max_pfn_mapped; -DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); +DEFINE_PER_CPU_LOCKED(struct mmu_gather, mmu_gathers); unsigned long highstart_pfn, highend_pfn; static noinline int do_test_wp_bit(void); @@ -710,6 +710,8 @@ unsigned long start = PFN_ALIGN(_text); unsigned long size = PFN_ALIGN(_etext) - start; +#ifndef CONFIG_DYNAMIC_FTRACE + /* Dynamic tracing modifies the kernel text section */ set_pages_ro(virt_to_page(start), size >> PAGE_SHIFT); printk(KERN_INFO "Write protecting the kernel text: %luk\n", size >> 10); @@ -722,6 +724,8 @@ printk(KERN_INFO "Testing CPA: write protecting again\n"); set_pages_ro(virt_to_page(start), size>>PAGE_SHIFT); #endif +#endif /* CONFIG_DYNAMIC_FTRACE */ + start += size; size = (unsigned long)__end_rodata - start; set_pages_ro(virt_to_page(start), size >> PAGE_SHIFT); diff -urN linux-2.6.26/arch/x86/mm/init_64.c linux-2.6.26-lab126/arch/x86/mm/init_64.c --- linux-2.6.26/arch/x86/mm/init_64.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/mm/init_64.c 2010-08-10 04:14:37.000000000 -0400 @@ -49,7 +49,7 @@ static unsigned long dma_reserve __initdata; -DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); +DEFINE_PER_CPU_LOCKED(struct mmu_gather, mmu_gathers); int direct_gbpages __meminitdata #ifdef CONFIG_DIRECT_GBPAGES @@ -767,6 +767,13 @@ void mark_rodata_ro(void) { unsigned long start = PFN_ALIGN(_stext), end = PFN_ALIGN(__end_rodata); + unsigned long rodata_start = + ((unsigned long)__start_rodata + PAGE_SIZE - 1) & PAGE_MASK; + +#ifdef CONFIG_DYNAMIC_FTRACE + /* Dynamic tracing modifies the kernel text section */ + start = rodata_start; +#endif printk(KERN_INFO "Write protecting the kernel read-only data: %luk\n", (end - start) >> 10); @@ -776,8 +783,7 @@ * The rodata section (but not the kernel text!) should also be * not-executable. */ - start = ((unsigned long)__start_rodata + PAGE_SIZE - 1) & PAGE_MASK; - set_memory_nx(start, (end - start) >> PAGE_SHIFT); + set_memory_nx(rodata_start, (end - rodata_start) >> PAGE_SHIFT); rodata_test(); diff -urN linux-2.6.26/arch/x86/pci/Makefile_32 linux-2.6.26-lab126/arch/x86/pci/Makefile_32 --- linux-2.6.26/arch/x86/pci/Makefile_32 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/pci/Makefile_32 2010-08-10 04:14:37.000000000 -0400 @@ -5,12 +5,13 @@ obj-$(CONFIG_PCI_DIRECT) += direct.o obj-$(CONFIG_PCI_OLPC) += olpc.o +obj-$(CONFIG_ACPI) += acpi.o + pci-y := fixup.o # Do not change the ordering here. There is a nasty init function # ordering dependency which breaks when you move acpi.o below # legacy/irq.o -pci-$(CONFIG_ACPI) += acpi.o pci-y += legacy.o irq.o # Careful: VISWS and NUMAQ overrule the pci-y above. The colons are diff -urN linux-2.6.26/arch/x86/pci/common.c linux-2.6.26-lab126/arch/x86/pci/common.c --- linux-2.6.26/arch/x86/pci/common.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/pci/common.c 2010-08-10 04:14:37.000000000 -0400 @@ -75,7 +75,7 @@ * This interrupt-safe spinlock protects all accesses to PCI * configuration space. */ -DEFINE_SPINLOCK(pci_config_lock); +DEFINE_RAW_SPINLOCK(pci_config_lock); static int __devinit can_skip_ioresource_align(const struct dmi_system_id *d) { diff -urN linux-2.6.26/arch/x86/pci/direct.c linux-2.6.26-lab126/arch/x86/pci/direct.c --- linux-2.6.26/arch/x86/pci/direct.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/pci/direct.c 2010-08-10 04:14:37.000000000 -0400 @@ -220,16 +220,23 @@ unsigned int tmp; int works = 0; - local_irq_save(flags); + spin_lock_irqsave(&pci_config_lock, flags); outb(0x01, 0xCFB); tmp = inl(0xCF8); outl(0x80000000, 0xCF8); - if (inl(0xCF8) == 0x80000000 && pci_sanity_check(&pci_direct_conf1)) { - works = 1; + + if (inl(0xCF8) == 0x80000000) { + spin_unlock_irqrestore(&pci_config_lock, flags); + + if (pci_sanity_check(&pci_direct_conf1)) + works = 1; + + spin_lock_irqsave(&pci_config_lock, flags); } outl(tmp, 0xCF8); - local_irq_restore(flags); + + spin_unlock_irqrestore(&pci_config_lock, flags); return works; } @@ -239,17 +246,19 @@ unsigned long flags; int works = 0; - local_irq_save(flags); + spin_lock_irqsave(&pci_config_lock, flags); outb(0x00, 0xCFB); outb(0x00, 0xCF8); outb(0x00, 0xCFA); - if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00 && - pci_sanity_check(&pci_direct_conf2)) { - works = 1; - } - local_irq_restore(flags); + if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00) { + spin_unlock_irqrestore(&pci_config_lock, flags); + + if (pci_sanity_check(&pci_direct_conf2)) + works = 1; + } else + spin_unlock_irqrestore(&pci_config_lock, flags); return works; } diff -urN linux-2.6.26/arch/x86/pci/pci.h linux-2.6.26-lab126/arch/x86/pci/pci.h --- linux-2.6.26/arch/x86/pci/pci.h 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/pci/pci.h 2010-08-10 04:14:37.000000000 -0400 @@ -81,7 +81,7 @@ extern unsigned int pcibios_irq_mask; extern int pcibios_scanned; -extern spinlock_t pci_config_lock; +extern raw_spinlock_t pci_config_lock; extern int (*pcibios_enable_irq)(struct pci_dev *dev); extern void (*pcibios_disable_irq)(struct pci_dev *dev); diff -urN linux-2.6.26/arch/x86/vdso/.gitignore linux-2.6.26-lab126/arch/x86/vdso/.gitignore --- linux-2.6.26/arch/x86/vdso/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/vdso/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,6 +0,0 @@ -vdso.lds -vdso-syms.lds -vdso32-syms.lds -vdso32-syscall-syms.lds -vdso32-sysenter-syms.lds -vdso32-int80-syms.lds diff -urN linux-2.6.26/arch/x86/vdso/vclock_gettime.c linux-2.6.26-lab126/arch/x86/vdso/vclock_gettime.c --- linux-2.6.26/arch/x86/vdso/vclock_gettime.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/vdso/vclock_gettime.c 2010-08-10 04:14:37.000000000 -0400 @@ -23,7 +23,7 @@ #define gtod vdso_vsyscall_gtod_data -static long vdso_fallback_gettime(long clock, struct timespec *ts) +notrace static long vdso_fallback_gettime(long clock, struct timespec *ts) { long ret; asm("syscall" : "=a" (ret) : @@ -31,7 +31,7 @@ return ret; } -static inline long vgetns(void) +notrace static inline long vgetns(void) { long v; cycles_t (*vread)(void); @@ -40,7 +40,7 @@ return (v * gtod->clock.mult) >> gtod->clock.shift; } -static noinline int do_realtime(struct timespec *ts) +notrace static noinline int do_realtime(struct timespec *ts) { unsigned long seq, ns; do { @@ -54,7 +54,8 @@ } /* Copy of the version in kernel/time.c which we cannot directly access */ -static void vset_normalized_timespec(struct timespec *ts, long sec, long nsec) +notrace static void +vset_normalized_timespec(struct timespec *ts, long sec, long nsec) { while (nsec >= NSEC_PER_SEC) { nsec -= NSEC_PER_SEC; @@ -68,7 +69,7 @@ ts->tv_nsec = nsec; } -static noinline int do_monotonic(struct timespec *ts) +notrace static noinline int do_monotonic(struct timespec *ts) { unsigned long seq, ns, secs; do { @@ -82,7 +83,7 @@ return 0; } -int __vdso_clock_gettime(clockid_t clock, struct timespec *ts) +notrace int __vdso_clock_gettime(clockid_t clock, struct timespec *ts) { if (likely(gtod->sysctl_enabled && gtod->clock.vread)) switch (clock) { @@ -96,7 +97,7 @@ int clock_gettime(clockid_t, struct timespec *) __attribute__((weak, alias("__vdso_clock_gettime"))); -int __vdso_gettimeofday(struct timeval *tv, struct timezone *tz) +notrace int __vdso_gettimeofday(struct timeval *tv, struct timezone *tz) { long ret; if (likely(gtod->sysctl_enabled && gtod->clock.vread)) { diff -urN linux-2.6.26/arch/x86/vdso/vdso32/.gitignore linux-2.6.26-lab126/arch/x86/vdso/vdso32/.gitignore --- linux-2.6.26/arch/x86/vdso/vdso32/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/vdso/vdso32/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1 +0,0 @@ -vdso32.lds diff -urN linux-2.6.26/arch/x86/vdso/vgetcpu.c linux-2.6.26-lab126/arch/x86/vdso/vgetcpu.c --- linux-2.6.26/arch/x86/vdso/vgetcpu.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/arch/x86/vdso/vgetcpu.c 2010-08-10 04:14:37.000000000 -0400 @@ -13,7 +13,8 @@ #include #include "vextern.h" -long __vdso_getcpu(unsigned *cpu, unsigned *node, struct getcpu_cache *unused) +notrace long +__vdso_getcpu(unsigned *cpu, unsigned *node, struct getcpu_cache *unused) { unsigned int p; diff -urN linux-2.6.26/block/blk-core.c linux-2.6.26-lab126/block/blk-core.c --- linux-2.6.26/block/blk-core.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/block/blk-core.c 2010-08-10 04:13:01.000000000 -0400 @@ -192,7 +192,7 @@ */ void blk_plug_device(struct request_queue *q) { - WARN_ON(!irqs_disabled()); + WARN_ON_NONRT(!irqs_disabled()); /* * don't plug a stopped queue, it must be paired with blk_start_queue() @@ -215,7 +215,7 @@ */ int blk_remove_plug(struct request_queue *q) { - WARN_ON(!irqs_disabled()); + WARN_ON_NONRT(!irqs_disabled()); if (!test_bit(QUEUE_FLAG_PLUGGED, &q->queue_flags)) return 0; @@ -316,7 +316,7 @@ **/ void blk_start_queue(struct request_queue *q) { - WARN_ON(!irqs_disabled()); + WARN_ON_NONRT(!irqs_disabled()); queue_flag_clear(QUEUE_FLAG_STOPPED, q); diff -urN linux-2.6.26/cpufreq.c linux-2.6.26-lab126/cpufreq.c --- linux-2.6.26/cpufreq.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/cpufreq.c 2010-08-10 04:17:28.000000000 -0400 @@ -0,0 +1,195 @@ +/* + * cpufreq.c -- MX35 CPUfreq driver. + * MX35 cpufreq driver + * + * Copyright 2009 Lab126, Inc. All rights reserved. + * Manish Lachwani (lachwani@lab126.com) + * + * Support for CPUFreq on the Luigi. It supports two operating points: + * 266MHz and 532MHz. Along with the CPU Frequency scaling, the voltage + * is also adjusted to be 1.2V (266MHz) or 1.4V (532MHz). + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "crm_regs.h" + +static struct clk *cpu_clk; +DEFINE_RAW_SPINLOCK(cpufreq_lock); + +#define MXC_PERCLK_DIVIDER 0x1000 + +/* + * turn debug on/off + */ +#undef MX3_CPU_FREQ_DEBUG + +static struct cpufreq_frequency_table mx35_freq_table_con[] = { + {0x01, 266000}, + {0x02, 532000}, + {0, CPUFREQ_TABLE_END}, +}; + +static int mx35_verify_speed(struct cpufreq_policy *policy) +{ + if (policy->cpu != 0) + return -EINVAL; + + return cpufreq_frequency_table_verify(policy, mx35_freq_table_con); +} + +static unsigned int mx35_get_speed(unsigned int cpu) +{ + if (cpu) + return 0; + return clk_get_rate(cpu_clk) / 1000; +} + +static int calc_frequency_con(int target, unsigned int relation) +{ + int i = 0; + + if (relation == CPUFREQ_RELATION_H) { + for (i = 1; i >= 0; i--) { + if (mx35_freq_table_con[i].frequency <= target) + return mx35_freq_table_con[i].frequency; + } + } else if (relation == CPUFREQ_RELATION_L) { + for (i = 0; i <= 1; i++) { + if (mx35_freq_table_con[i].frequency >= target) + return mx35_freq_table_con[i].frequency; + } + } + printk(KERN_ERR "Error: No valid cpufreq relation\n"); + return 532000; +} + +/* + * Set the destination CPU frequency target + */ +static int mx35_set_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + struct cpufreq_freqs freqs; + long freq; + unsigned long flags; + unsigned long pdr0; + int orig_cpu_rate = clk_get_rate(cpu_clk); + + if (target_freq < policy->cpuinfo.min_freq) + target_freq = policy->cpuinfo.min_freq; + + if (target_freq < policy->min) + target_freq = policy->min; + + freq = calc_frequency_con(target_freq, relation) * 1000; + freqs.old = clk_get_rate(cpu_clk) / 1000; + freqs.new = (freq + 500) / 1000; + freqs.cpu = 0; + freqs.flags = 0; + + if (freq == orig_cpu_rate) + return 0; + + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + +#ifdef MX3_CPU_FREQ_DEBUG + printk ("ARM frequency: %dHz\n", (int)clk_get_rate(cpu_clk)); +#endif + spin_lock_irqsave(&cpufreq_lock, flags); + /* + * MCU clk + */ + clk_set_rate(cpu_clk, freq); + + pdr0 = __raw_readl(MXC_CCM_PDR0); + pdr0 |= MXC_PERCLK_DIVIDER; + __raw_writel(pdr0, MXC_CCM_PDR0); + + spin_unlock_irqrestore(&cpufreq_lock, flags); + + +#ifdef MX3_CPU_FREQ_DEBUG + printk ("ARM frequency after change: %dHz\n", (int)clk_get_rate(cpu_clk)); +#endif + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + clk_put(cpu_clk); + return 0; +} + +/* + * Driver initialization + */ +static int __init mx35_cpufreq_driver_init(struct cpufreq_policy *policy) +{ + int ret = 0; + + printk("Luigi/Freescale MX35 CPUFREQ driver\n"); + + if (policy->cpu != 0) + return -EINVAL; + + cpu_clk = clk_get(NULL, "cpu_clk"); + + if (IS_ERR(cpu_clk)) + return PTR_ERR(cpu_clk); + + policy->cur = policy->min = policy->max = + clk_get_rate(cpu_clk) / 1000; + policy->governor = CPUFREQ_DEFAULT_GOVERNOR; + policy->cpuinfo.min_freq = 266000; + policy->cpuinfo.max_freq = 532000; + + /* Set the transition latency to 50 us */ + policy->cpuinfo.transition_latency = 5 * 10000; + + ret = cpufreq_frequency_table_cpuinfo(policy, mx35_freq_table_con); + + if (ret < 0) + return ret; + + clk_put(cpu_clk); + + cpufreq_frequency_table_get_attr(mx35_freq_table_con, policy->cpu); + return 0; +} + +static int mx35_cpufreq_driver_exit(struct cpufreq_policy *policy) +{ + cpufreq_frequency_table_put_attr(policy->cpu); + clk_set_rate(cpu_clk, 532000 * 1000); + + clk_put(cpu_clk); + return 0; +} + +static struct cpufreq_driver mx35_driver = { + .flags = CPUFREQ_STICKY, + .verify = mx35_verify_speed, + .target = mx35_set_target, + .get = mx35_get_speed, + .init = mx35_cpufreq_driver_init, + .exit = mx35_cpufreq_driver_exit, + .name = "MX31", +}; + +static int __init mx35_cpufreq_init(void) +{ + return cpufreq_register_driver(&mx35_driver); +} + +arch_initcall(mx35_cpufreq_init); diff -urN linux-2.6.26/drivers/Kconfig linux-2.6.26-lab126/drivers/Kconfig --- linux-2.6.26/drivers/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/Kconfig 2010-08-10 04:17:28.000000000 -0400 @@ -92,6 +92,8 @@ source "drivers/rtc/Kconfig" +source "drivers/regulator/Kconfig" + source "drivers/dma/Kconfig" source "drivers/dca/Kconfig" diff -urN linux-2.6.26/drivers/Makefile linux-2.6.26-lab126/drivers/Makefile --- linux-2.6.26/drivers/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/Makefile 2010-08-10 04:17:28.000000000 -0400 @@ -62,6 +62,7 @@ obj-$(CONFIG_I2O) += message/ obj-$(CONFIG_RTC_LIB) += rtc/ obj-y += i2c/ +obj-$(CONFIG_I2C_SLAVE) += i2c-slave/ obj-$(CONFIG_W1) += w1/ obj-$(CONFIG_POWER_SUPPLY) += power/ obj-$(CONFIG_HWMON) += hwmon/ @@ -78,6 +79,7 @@ obj-y += lguest/ obj-$(CONFIG_CPU_FREQ) += cpufreq/ obj-$(CONFIG_CPU_IDLE) += cpuidle/ +obj-$(CONFIG_ARCH_MXC) += mxc/ obj-$(CONFIG_MMC) += mmc/ obj-$(CONFIG_MEMSTICK) += memstick/ obj-$(CONFIG_NEW_LEDS) += leds/ @@ -92,5 +94,6 @@ obj-$(CONFIG_HID) += hid/ obj-$(CONFIG_PPC_PS3) += ps3/ obj-$(CONFIG_OF) += of/ +obj-$(CONFIG_REGULATOR) += regulator/ obj-$(CONFIG_SSB) += ssb/ obj-$(CONFIG_VIRTIO) += virtio/ diff -urN linux-2.6.26/drivers/acpi/ec.c linux-2.6.26-lab126/drivers/acpi/ec.c --- linux-2.6.26/drivers/acpi/ec.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/acpi/ec.c 2010-08-10 04:16:10.000000000 -0400 @@ -499,7 +499,19 @@ } clear_bit(EC_FLAGS_WAIT_GPE, &ec->flags); if (test_bit(EC_FLAGS_GPE_MODE, &ec->flags)) +#if 0 wake_up(&ec->wait); +#else + // hack ... + if (waitqueue_active(&ec->wait)) { + struct task_struct *task; + + task = list_entry(ec->wait.task_list.next, + wait_queue_t, task_list)->private; + if (task) + wake_up_process(task); + } +#endif if (state & ACPI_EC_FLAG_SCI) { if (!test_and_set_bit(EC_FLAGS_QUERY_PENDING, &ec->flags)) diff -urN linux-2.6.26/drivers/acpi/hardware/hwregs.c linux-2.6.26-lab126/drivers/acpi/hardware/hwregs.c --- linux-2.6.26/drivers/acpi/hardware/hwregs.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/acpi/hardware/hwregs.c 2010-08-10 04:16:09.000000000 -0400 @@ -73,7 +73,7 @@ ACPI_BITMASK_ALL_FIXED_STATUS, (u16) acpi_gbl_FADT.xpm1a_event_block.address)); - lock_flags = acpi_os_acquire_lock(acpi_gbl_hardware_lock); + spin_lock_irqsave(acpi_gbl_hardware_lock, lock_flags); status = acpi_hw_register_write(ACPI_REGISTER_PM1_STATUS, ACPI_BITMASK_ALL_FIXED_STATUS); @@ -97,7 +97,7 @@ status = acpi_ev_walk_gpe_list(acpi_hw_clear_gpe_block); unlock_and_exit: - acpi_os_release_lock(acpi_gbl_hardware_lock, lock_flags); + spin_unlock_irqrestore(acpi_gbl_hardware_lock, lock_flags); return_ACPI_STATUS(status); } @@ -300,9 +300,9 @@ { acpi_status status; acpi_cpu_flags flags; - flags = acpi_os_acquire_lock(acpi_gbl_hardware_lock); + spin_lock_irqsave(acpi_gbl_hardware_lock, flags); status = acpi_get_register_unlocked(register_id, return_value); - acpi_os_release_lock(acpi_gbl_hardware_lock, flags); + spin_unlock_irqrestore(acpi_gbl_hardware_lock, flags); return status; } @@ -339,7 +339,7 @@ return_ACPI_STATUS(AE_BAD_PARAMETER); } - lock_flags = acpi_os_acquire_lock(acpi_gbl_hardware_lock); + spin_lock_irqsave(acpi_gbl_hardware_lock, lock_flags); /* Always do a register read first so we can insert the new bits */ @@ -443,7 +443,7 @@ unlock_and_exit: - acpi_os_release_lock(acpi_gbl_hardware_lock, lock_flags); + spin_unlock_irqrestore(acpi_gbl_hardware_lock, lock_flags); /* Normalize the value that was read */ diff -urN linux-2.6.26/drivers/acpi/osl.c linux-2.6.26-lab126/drivers/acpi/osl.c --- linux-2.6.26/drivers/acpi/osl.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/acpi/osl.c 2010-08-10 04:16:10.000000000 -0400 @@ -768,12 +768,12 @@ acpi_status acpi_os_create_semaphore(u32 max_units, u32 initial_units, acpi_handle * handle) { - struct semaphore *sem = NULL; + struct compat_semaphore *sem = NULL; - sem = acpi_os_allocate(sizeof(struct semaphore)); + sem = acpi_os_allocate(sizeof(struct compat_semaphore)); if (!sem) return AE_NO_MEMORY; - memset(sem, 0, sizeof(struct semaphore)); + memset(sem, 0, sizeof(struct compat_semaphore)); sema_init(sem, initial_units); @@ -794,7 +794,7 @@ acpi_status acpi_os_delete_semaphore(acpi_handle handle) { - struct semaphore *sem = (struct semaphore *)handle; + struct compat_semaphore *sem = (struct compat_semaphore *)handle; if (!sem) return AE_BAD_PARAMETER; @@ -814,7 +814,7 @@ acpi_status acpi_os_wait_semaphore(acpi_handle handle, u32 units, u16 timeout) { acpi_status status = AE_OK; - struct semaphore *sem = (struct semaphore *)handle; + struct compat_semaphore *sem = (struct compat_semaphore *)handle; long jiffies; int ret = 0; @@ -855,7 +855,7 @@ */ acpi_status acpi_os_signal_semaphore(acpi_handle handle, u32 units) { - struct semaphore *sem = (struct semaphore *)handle; + struct compat_semaphore *sem = (struct compat_semaphore *)handle; if (!sem || (units < 1)) return AE_BAD_PARAMETER; diff -urN linux-2.6.26/drivers/acpi/processor_idle.c linux-2.6.26-lab126/drivers/acpi/processor_idle.c --- linux-2.6.26/drivers/acpi/processor_idle.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/acpi/processor_idle.c 2010-08-10 04:16:10.000000000 -0400 @@ -1532,7 +1532,7 @@ } static int c3_cpu_count; -static DEFINE_SPINLOCK(c3_lock); +static DEFINE_RAW_SPINLOCK(c3_lock); /** * acpi_idle_enter_bm - enters C3 with proper BM handling diff -urN linux-2.6.26/drivers/acpi/utilities/utmutex.c linux-2.6.26-lab126/drivers/acpi/utilities/utmutex.c --- linux-2.6.26/drivers/acpi/utilities/utmutex.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/acpi/utilities/utmutex.c 2010-08-10 04:16:10.000000000 -0400 @@ -116,7 +116,7 @@ /* Delete the spinlocks */ acpi_os_delete_lock(acpi_gbl_gpe_lock); - acpi_os_delete_lock(acpi_gbl_hardware_lock); +// acpi_os_delete_lock(acpi_gbl_hardware_lock); return_VOID; } diff -urN linux-2.6.26/drivers/ata/Kconfig linux-2.6.26-lab126/drivers/ata/Kconfig --- linux-2.6.26/drivers/ata/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/ata/Kconfig 2010-08-10 04:17:24.000000000 -0400 @@ -723,5 +723,14 @@ If unsure, say N. +config PATA_FSL + tristate "Freescale on-chip PATA support" + depends on (ARCH_MX51 || ARCH_MX37 || ARCH_MX35 || ARCH_MX3 || ARCH_MX27) + help + On Freescale processors, say Y here if you wish to use the on-chip + ATA interface. + If you are unsure, say N to this. + endif # ATA_SFF + endif # ATA diff -urN linux-2.6.26/drivers/ata/Makefile linux-2.6.26-lab126/drivers/ata/Makefile --- linux-2.6.26/drivers/ata/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/ata/Makefile 2010-08-10 04:17:24.000000000 -0400 @@ -72,6 +72,7 @@ obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o obj-$(CONFIG_PATA_ICSIDE) += pata_icside.o +obj-$(CONFIG_PATA_FSL) += pata_fsl.o # Should be last but two libata driver obj-$(CONFIG_PATA_ACPI) += pata_acpi.o # Should be last but one libata driver diff -urN linux-2.6.26/drivers/ata/libata-sff.c linux-2.6.26-lab126/drivers/ata/libata-sff.c --- linux-2.6.26/drivers/ata/libata-sff.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/ata/libata-sff.c 2010-08-10 04:17:24.000000000 -0400 @@ -740,9 +740,9 @@ unsigned long flags; unsigned int consumed; - local_irq_save(flags); + local_irq_save_nort(flags); consumed = ata_sff_data_xfer(dev, buf, buflen, rw); - local_irq_restore(flags); + local_irq_restore_nort(flags); return consumed; } @@ -780,7 +780,7 @@ unsigned long flags; /* FIXME: use a bounce buffer */ - local_irq_save(flags); + local_irq_save_nort(flags); buf = kmap_atomic(page, KM_IRQ0); /* do the actual data transfer */ @@ -788,7 +788,7 @@ do_write); kunmap_atomic(buf, KM_IRQ0); - local_irq_restore(flags); + local_irq_restore_nort(flags); } else { buf = page_address(page); ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, @@ -918,14 +918,14 @@ unsigned long flags; /* FIXME: use bounce buffer */ - local_irq_save(flags); + local_irq_save_nort(flags); buf = kmap_atomic(page, KM_IRQ0); /* do the actual data transfer */ consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw); kunmap_atomic(buf, KM_IRQ0); - local_irq_restore(flags); + local_irq_restore_nort(flags); } else { buf = page_address(page); consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw); diff -urN linux-2.6.26/drivers/ata/pata_fsl.c linux-2.6.26-lab126/drivers/ata/pata_fsl.c --- linux-2.6.26/drivers/ata/pata_fsl.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/ata/pata_fsl.c 2010-08-10 04:17:24.000000000 -0400 @@ -0,0 +1,1042 @@ +/* + * Freescale integrated PATA driver + */ + +/* + * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "pata_fsl" + +struct pata_fsl_priv { + int ultra; + u8 *fsl_ata_regs; + struct clk *clk; + int dma_rchan; + int dma_wchan; + int dma_done; + int dma_dir; + unsigned int adma_des_paddr; + unsigned int *adma_des_tp; +}; + +struct adma_bd { + unsigned char *sg_buf; + unsigned char *work_buf; + unsigned int dma_address; + int length; +}; + +struct adma_bulk { + struct adma_bd adma_bd_table[MXC_IDE_DMA_BD_NR]; + struct ata_queued_cmd *qc; + int sg_ents; + int reserved[2]; +}; + +enum { + /* various constants */ + FSL_ATA_MAX_SG_LEN = ATA_DMA_BOUNDARY << 1, + + /* offsets to registers */ + FSL_ATA_TIMING_REGS = 0x00, + FSL_ATA_FIFO_FILL = 0x20, + FSL_ATA_CONTROL = 0x24, + FSL_ATA_INT_PEND = 0x28, + FSL_ATA_INT_EN = 0x2C, + FSL_ATA_INT_CLEAR = 0x30, + FSL_ATA_FIFO_ALARM = 0x34, + FSL_ATA_ADMA_ERROR_STATUS = 0x38, + FSL_ATA_SYS_DMA_BADDR = 0x3C, + FSL_ATA_ADMA_SYS_ADDR = 0x40, + FSL_ATA_BLOCK_COUNT = 0x48, + FSL_ATA_BURST_LENGTH = 0x4C, + FSL_ATA_SECTOR_SIZE = 0x50, + FSL_ATA_DRIVE_DATA = 0xA0, + FSL_ATA_DRIVE_CONTROL = 0xD8, + + /* bits within FSL_ATA_CONTROL */ + FSL_ATA_CTRL_DMA_SRST = 0x1000, + FSL_ATA_CTRL_DMA_64ADMA = 0x800, + FSL_ATA_CTRL_DMA_32ADMA = 0x400, + FSL_ATA_CTRL_DMA_STAT_STOP = 0x200, + FSL_ATA_CTRL_DMA_ENABLE = 0x100, + FSL_ATA_CTRL_FIFO_RST_B = 0x80, + FSL_ATA_CTRL_ATA_RST_B = 0x40, + FSL_ATA_CTRL_FIFO_TX_EN = 0x20, + FSL_ATA_CTRL_FIFO_RCV_EN = 0x10, + FSL_ATA_CTRL_DMA_PENDING = 0x08, + FSL_ATA_CTRL_DMA_ULTRA = 0x04, + FSL_ATA_CTRL_DMA_WRITE = 0x02, + FSL_ATA_CTRL_IORDY_EN = 0x01, + + /* bits within the interrupt control registers */ + FSL_ATA_INTR_ATA_INTRQ1 = 0x80, + FSL_ATA_INTR_FIFO_UNDERFLOW = 0x40, + FSL_ATA_INTR_FIFO_OVERFLOW = 0x20, + FSL_ATA_INTR_CTRL_IDLE = 0x10, + FSL_ATA_INTR_ATA_INTRQ2 = 0x08, + FSL_ATA_INTR_DMA_ERR = 0x04, + FSL_ATA_INTR_DMA_TRANS_OVER = 0x02, + + /* ADMA Addr Descriptor Attribute Filed */ + FSL_ADMA_DES_ATTR_VALID = 0x01, + FSL_ADMA_DES_ATTR_END = 0x02, + FSL_ADMA_DES_ATTR_INT = 0x04, + FSL_ADMA_DES_ATTR_SET = 0x10, + FSL_ADMA_DES_ATTR_TRAN = 0x20, + FSL_ADMA_DES_ATTR_LINK = 0x30, +}; + +/* + * This structure contains the timing parameters for + * ATA bus timing in the 5 PIO modes. The timings + * are in nanoseconds, and are converted to clock + * cycles before being stored in the ATA controller + * timing registers. + */ +static struct { + short t0, t1, t2_8, t2_16, t2i, t4, t9, tA; +} pio_specs[] = { + [0] = { + .t0 = 600, .t1 = 70, .t2_8 = 290, .t2_16 = 165, .t2i = 0, .t4 = + 30, .t9 = 20, .tA = 50,}, + [1] = { + .t0 = 383, .t1 = 50, .t2_8 = 290, .t2_16 = 125, .t2i = 0, .t4 = + 20, .t9 = 15, .tA = 50,}, + [2] = { + .t0 = 240, .t1 = 30, .t2_8 = 290, .t2_16 = 100, .t2i = 0, .t4 = + 15, .t9 = 10, .tA = 50,}, + [3] = { + .t0 = 180, .t1 = 30, .t2_8 = 80, .t2_16 = 80, .t2i = 0, .t4 = + 10, .t9 = 10, .tA = 50,}, + [4] = { + .t0 = 120, .t1 = 25, .t2_8 = 70, .t2_16 = 70, .t2i = 0, .t4 = + 10, .t9 = 10, .tA = 50,}, + }; + +#define NR_PIO_SPECS (sizeof pio_specs / sizeof pio_specs[0]) + +/* + * This structure contains the timing parameters for + * ATA bus timing in the 3 MDMA modes. The timings + * are in nanoseconds, and are converted to clock + * cycles before being stored in the ATA controller + * timing registers. + */ +static struct { + short t0M, tD, tH, tJ, tKW, tM, tN, tJNH; +} mdma_specs[] = { + [0] = { + .t0M = 480, .tD = 215, .tH = 20, .tJ = 20, .tKW = 215, .tM = 50, .tN = + 15, .tJNH = 20,}, + [1] = { + .t0M = 150, .tD = 80, .tH = 15, .tJ = 5, .tKW = 50, .tM = 30, .tN = + 10, .tJNH = 15,}, + [2] = { + .t0M = 120, .tD = 70, .tH = 10, .tJ = 5, .tKW = 25, .tM = 25, .tN = + 10, .tJNH = 10,}, + }; + +#define NR_MDMA_SPECS (sizeof mdma_specs / sizeof mdma_specs[0]) + +/* + * This structure contains the timing parameters for + * ATA bus timing in the 6 UDMA modes. The timings + * are in nanoseconds, and are converted to clock + * cycles before being stored in the ATA controller + * timing registers. + */ +static struct { + short t2CYC, tCYC, tDS, tDH, tDVS, tDVH, tCVS, tCVH, tFS_min, tLI_max, + tMLI, tAZ, tZAH, tENV_min, tSR, tRFS, tRP, tACK, tSS, tDZFS; +} udma_specs[] = { + [0] = { + .t2CYC = 235, .tCYC = 114, .tDS = 15, .tDH = 5, .tDVS = 70, .tDVH = + 6, .tCVS = 70, .tCVH = 6, .tFS_min = 0, .tLI_max = + 100, .tMLI = 20, .tAZ = 10, .tZAH = 20, .tENV_min = + 20, .tSR = 50, .tRFS = 75, .tRP = 160, .tACK = 20, .tSS = + 50, .tDZFS = 80,}, + [1] = { + .t2CYC = 156, .tCYC = 75, .tDS = 10, .tDH = 5, .tDVS = 48, .tDVH = + 6, .tCVS = 48, .tCVH = 6, .tFS_min = 0, .tLI_max = + 100, .tMLI = 20, .tAZ = 10, .tZAH = 20, .tENV_min = + 20, .tSR = 30, .tRFS = 70, .tRP = 125, .tACK = 20, .tSS = + 50, .tDZFS = 63,}, + [2] = { + .t2CYC = 117, .tCYC = 55, .tDS = 7, .tDH = 5, .tDVS = 34, .tDVH = + 6, .tCVS = 34, .tCVH = 6, .tFS_min = 0, .tLI_max = + 100, .tMLI = 20, .tAZ = 10, .tZAH = 20, .tENV_min = + 20, .tSR = 20, .tRFS = 60, .tRP = 100, .tACK = 20, .tSS = + 50, .tDZFS = 47,}, + [3] = { + .t2CYC = 86, .tCYC = 39, .tDS = 7, .tDH = 5, .tDVS = 20, .tDVH = + 6, .tCVS = 20, .tCVH = 6, .tFS_min = 0, .tLI_max = + 100, .tMLI = 20, .tAZ = 10, .tZAH = 20, .tENV_min = + 20, .tSR = 20, .tRFS = 60, .tRP = 100, .tACK = 20, .tSS = + 50, .tDZFS = 35,}, + [4] = { + .t2CYC = 57, .tCYC = 25, .tDS = 5, .tDH = 5, .tDVS = 7, .tDVH = + 6, .tCVS = 7, .tCVH = 6, .tFS_min = 0, .tLI_max = + 100, .tMLI = 20, .tAZ = 10, .tZAH = 20, .tENV_min = + 20, .tSR = 50, .tRFS = 60, .tRP = 100, .tACK = 20, .tSS = + 50, .tDZFS = 25,}, + [5] = { + .t2CYC = 38, .tCYC = 17, .tDS = 4, .tDH = 5, .tDVS = 5, .tDVH = + 6, .tCVS = 10, .tCVH = 10, .tFS_min = + 0, .tLI_max = 75, .tMLI = 20, .tAZ = 10, .tZAH = + 20, .tENV_min = 20, .tSR = 20, .tRFS = + 50, .tRP = 85, .tACK = 20, .tSS = 50, .tDZFS = 40,}, +}; + +#define NR_UDMA_SPECS (sizeof udma_specs / sizeof udma_specs[0]) + +struct fsl_ata_time_regs { + u8 time_off, time_on, time_1, time_2w; + u8 time_2r, time_ax, time_pio_rdx, time_4; + u8 time_9, time_m, time_jn, time_d; + u8 time_k, time_ack, time_env, time_rpx; + u8 time_zah, time_mlix, time_dvh, time_dzfs; + u8 time_dvs, time_cvh, time_ss, time_cyc; +}; + +static struct regulator *io_reg; +static struct regulator *core_reg; +static struct adma_bulk adma_info; + +static void +update_timing_config(struct fsl_ata_time_regs *tp, struct ata_host *host) +{ + u32 *lp = (u32 *) tp; + struct pata_fsl_priv *priv = host->private_data; + u32 *ctlp = (u32 *) priv->fsl_ata_regs; + int i; + + for (i = 0; i < 5; i++) { + __raw_writel(*lp, ctlp); + lp++; + ctlp++; + } +} + +/*! + * Calculate values for the ATA bus timing registers and store + * them into the hardware. + * + * @param xfer_mode specifies XFER xfer_mode + * @param pdev specifies platform_device + * + * @return EINVAL speed out of range, or illegal mode + */ +static int set_ata_bus_timing(u8 xfer_mode, struct platform_device *pdev) +{ + struct ata_host *host = dev_get_drvdata(&pdev->dev); + struct pata_fsl_priv *priv = host->private_data; + + /* get the bus clock cycle time, in ns */ + int T = 1 * 1000 * 1000 * 1000 / clk_get_rate(priv->clk); + struct fsl_ata_time_regs tr = { 0 }; + + /* + * every mode gets the same t_off and t_on + */ + tr.time_off = 3; + tr.time_on = 3; + + if (xfer_mode >= XFER_UDMA_0) { + int speed = xfer_mode - XFER_UDMA_0; + if (speed >= NR_UDMA_SPECS) + return -EINVAL; + + tr.time_ack = (udma_specs[speed].tACK + T) / T; + tr.time_env = (udma_specs[speed].tENV_min + T) / T; + tr.time_rpx = (udma_specs[speed].tRP + T) / T + 2; + tr.time_zah = (udma_specs[speed].tZAH + T) / T; + tr.time_mlix = (udma_specs[speed].tMLI + T) / T; + tr.time_dvh = (udma_specs[speed].tDVH + T) / T + 1; + tr.time_dzfs = (udma_specs[speed].tDZFS + T) / T; + + tr.time_dvs = (udma_specs[speed].tDVS + T) / T; + tr.time_cvh = (udma_specs[speed].tCVH + T) / T; + tr.time_ss = (udma_specs[speed].tSS + T) / T; + tr.time_cyc = (udma_specs[speed].tCYC + T) / T; + } else if (xfer_mode >= XFER_MW_DMA_0) { + int speed = xfer_mode - XFER_MW_DMA_0; + if (speed >= NR_MDMA_SPECS) + return -EINVAL; + + tr.time_m = (mdma_specs[speed].tM + T) / T; + tr.time_jn = (mdma_specs[speed].tJNH + T) / T; + tr.time_d = (mdma_specs[speed].tD + T) / T; + + tr.time_k = (mdma_specs[speed].tKW + T) / T; + } else { + int speed = xfer_mode - XFER_PIO_0; + if (speed >= NR_PIO_SPECS) + return -EINVAL; + + tr.time_1 = (pio_specs[speed].t1 + T) / T; + tr.time_2w = (pio_specs[speed].t2_8 + T) / T; + + tr.time_2r = (pio_specs[speed].t2_8 + T) / T; + tr.time_ax = (pio_specs[speed].tA + T) / T + 2; + tr.time_pio_rdx = 1; + tr.time_4 = (pio_specs[speed].t4 + T) / T; + + tr.time_9 = (pio_specs[speed].t9 + T) / T; + } + + update_timing_config(&tr, host); + + return 0; +} + +static void pata_fsl_set_piomode(struct ata_port *ap, struct ata_device *adev) +{ + set_ata_bus_timing(adev->pio_mode, to_platform_device(ap->dev)); +} + +static void pata_fsl_set_dmamode(struct ata_port *ap, struct ata_device *adev) +{ + struct pata_fsl_priv *priv = ap->host->private_data; + + priv->ultra = adev->dma_mode >= XFER_UDMA_0; + + set_ata_bus_timing(adev->dma_mode, to_platform_device(ap->dev)); +} + +static int pata_fsl_port_start(struct ata_port *ap) +{ + return 0; +} + +static void pata_adma_bulk_unmap(struct ata_queued_cmd *qc) +{ + int i; + struct adma_bd *bdp = adma_info.adma_bd_table; + if (adma_info.qc == NULL) + return; + BUG_ON(adma_info.qc != qc); + + adma_info.qc = NULL; + + for (i = 0; i < adma_info.sg_ents; i++) { + if (bdp->work_buf != bdp->sg_buf) { + if (qc->dma_dir == DMA_FROM_DEVICE) { + memcpy(bdp->sg_buf, bdp->work_buf, bdp->length); + dma_cache_maint(bdp->sg_buf, bdp->length, + DMA_FROM_DEVICE); + } + dma_free_coherent(qc->ap->dev, bdp->length, + bdp->work_buf, bdp->dma_address); + } + bdp->work_buf = bdp->sg_buf = NULL; + bdp++; + } +} + +static int pata_adma_bulk_map(struct ata_queued_cmd *qc) +{ + unsigned int si; + struct scatterlist *sg; + struct adma_bd *bdp = adma_info.adma_bd_table; + + BUG_ON(adma_info.qc); + + adma_info.qc = qc; + adma_info.sg_ents = 0; + + for_each_sg(qc->sg, sg, qc->n_elem, si) { + /* + * The ADMA mode is used setup the ADMA descriptor table + */ + bdp->sg_buf = sg_virt(sg); + bdp->length = sg->length; + if (sg->dma_address & 0xFFF) { + bdp->work_buf = + dma_alloc_coherent(qc->ap->dev, bdp->length, + &bdp->dma_address, GFP_KERNEL); + if (!bdp->work_buf) { + printk(KERN_WARNING + "can not allocate aligned buffer\n"); + goto fail; + } + if (qc->dma_dir == DMA_TO_DEVICE) + memcpy(bdp->work_buf, bdp->sg_buf, bdp->length); + } else { + bdp->work_buf = bdp->sg_buf; + bdp->dma_address = sg->dma_address; + } + + adma_info.sg_ents++; + bdp++; + } + return 0; + fail: + pata_adma_bulk_unmap(qc); + return -1; +} + +static void dma_callback(void *arg, int error_status, unsigned int count) +{ + struct ata_port *ap = arg; + struct pata_fsl_priv *priv = ap->host->private_data; + u8 *ata_regs = priv->fsl_ata_regs; + + priv->dma_done = 1; + /* + * DMA is finished, so unmask INTRQ from the drive to allow the + * normal ISR to fire. + */ + __raw_writel(FSL_ATA_INTR_ATA_INTRQ2, ata_regs + FSL_ATA_INT_EN); +} + +static irqreturn_t pata_fsl_adma_intr(int irq, void *dev_instance) +{ + struct ata_host *host = dev_instance; + struct pata_fsl_priv *priv = host->private_data; + u8 *ata_regs = priv->fsl_ata_regs; + unsigned int handled = 0; + unsigned int i; + unsigned long flags; + unsigned int pending = __raw_readl(ata_regs + FSL_ATA_INT_PEND); + + if (FSL_ATA_INTR_DMA_TRANS_OVER & pending) { + priv->dma_done = 1; + __raw_writel(pending, ata_regs + FSL_ATA_INT_CLEAR); + handled = 1; + } else if (FSL_ATA_INTR_DMA_ERR & pending) { + printk(KERN_ERR "dma err status 0x%x ...\n", + __raw_readl(ata_regs + FSL_ATA_ADMA_ERROR_STATUS)); + __raw_writel(pending, ata_regs + FSL_ATA_INT_CLEAR); + handled = 1; + i = __raw_readl(ata_regs + FSL_ATA_CONTROL) && 0xFF; + i |= FSL_ATA_CTRL_DMA_SRST | FSL_ATA_CTRL_DMA_32ADMA | + FSL_ATA_CTRL_DMA_ENABLE; + __raw_writel(i, ata_regs + FSL_ATA_CONTROL); + } + + spin_lock_irqsave(&host->lock, flags); + + for (i = 0; i < host->n_ports; i++) { + struct ata_port *ap; + + ap = host->ports[i]; + if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { + struct ata_queued_cmd *qc; + + qc = ata_qc_from_tag(ap, ap->link.active_tag); + raw_local_irq_restore(flags); + pata_adma_bulk_unmap(qc); + raw_local_irq_save(flags); + if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) && + (qc->flags & ATA_QCFLAG_ACTIVE)) + handled |= ata_sff_host_intr(ap, qc); + } + } + + spin_unlock_irqrestore(&host->lock, flags); + + return IRQ_RETVAL(handled); +} + +static int pata_fsl_check_atapi_dma(struct ata_queued_cmd *qc) +{ + return 1; /* ATAPI DMA not yet supported */ +} + +unsigned long pata_fsl_bmdma_mode_filter(struct ata_device *adev, + unsigned long xfer_mask) +{ + /* Capability of the controller has been specified in the + * platform data. Do not filter any modes, just return + * the xfer_mask */ + return xfer_mask; +} + +static void pata_fsl_bmdma_setup(struct ata_queued_cmd *qc) +{ + int chan, i; + int dma_mode = 0, dma_ultra; + u32 ata_control; + struct ata_port *ap = qc->ap; + struct pata_fsl_priv *priv = ap->host->private_data; + u8 *ata_regs = priv->fsl_ata_regs; + struct fsl_ata_platform_data *plat = ap->dev->platform_data; + int err; + unsigned int si; + + priv->dma_dir = qc->dma_dir; + + /* + * Configure the on-chip ATA interface hardware. + */ + dma_ultra = priv->ultra ? FSL_ATA_CTRL_DMA_ULTRA : 0; + + ata_control = FSL_ATA_CTRL_FIFO_RST_B | + FSL_ATA_CTRL_ATA_RST_B | FSL_ATA_CTRL_DMA_PENDING | dma_ultra; + if (plat->adma_flag) + ata_control |= FSL_ATA_CTRL_DMA_32ADMA | + FSL_ATA_CTRL_DMA_ENABLE; + + if (qc->dma_dir == DMA_TO_DEVICE) { + chan = priv->dma_wchan; + ata_control |= FSL_ATA_CTRL_FIFO_TX_EN | FSL_ATA_CTRL_DMA_WRITE; + dma_mode = DMA_MODE_WRITE; + } else { + chan = priv->dma_rchan; + ata_control |= FSL_ATA_CTRL_FIFO_RCV_EN; + dma_mode = DMA_MODE_READ; + } + + __raw_writel(ata_control, ata_regs + FSL_ATA_CONTROL); + __raw_writel(plat->fifo_alarm, ata_regs + FSL_ATA_FIFO_ALARM); + + if (plat->adma_flag) { + i = FSL_ATA_INTR_DMA_TRANS_OVER | FSL_ATA_INTR_DMA_ERR; + __raw_writel(FSL_ATA_INTR_ATA_INTRQ2 | i, + ata_regs + FSL_ATA_INT_EN); + } else { + __raw_writel(FSL_ATA_INTR_ATA_INTRQ1, + ata_regs + FSL_ATA_INT_EN); + /* + * Set up the DMA completion callback. + */ + mxc_dma_callback_set(chan, dma_callback, (void *)ap); + } + + /* + * Copy the sg list to an array. + */ + if (plat->adma_flag) { + struct adma_bd *bdp = adma_info.adma_bd_table; + pata_adma_bulk_map(qc); + for (i = 0; i < adma_info.sg_ents; i++) { + priv->adma_des_tp[i << 1] = bdp->length << 12; + priv->adma_des_tp[i << 1] |= FSL_ADMA_DES_ATTR_SET; + priv->adma_des_tp[i << 1] |= FSL_ADMA_DES_ATTR_VALID; + priv->adma_des_tp[(i << 1) + 1] = bdp->dma_address; + priv->adma_des_tp[(i << 1) + 1] |= + FSL_ADMA_DES_ATTR_TRAN; + priv->adma_des_tp[(i << 1) + 1] |= + FSL_ADMA_DES_ATTR_VALID; + if (adma_info.sg_ents == (i + 1)) + priv->adma_des_tp[(i << 1) + 1] |= + FSL_ADMA_DES_ATTR_END; + bdp++; + } + __raw_writel((qc->nbytes / qc->sect_size), ata_regs + + FSL_ATA_BLOCK_COUNT); + __raw_writel(plat->fifo_alarm, ata_regs + FSL_ATA_BURST_LENGTH); + __raw_writel(priv->adma_des_paddr, + ata_regs + FSL_ATA_ADMA_SYS_ADDR); + } else { + int nr_sg = 0; + struct scatterlist tmp[MXC_IDE_DMA_BD_NR], *tsg, *sg; + tsg = tmp; + for_each_sg(qc->sg, sg, qc->n_elem, si) { + memcpy(tsg, sg, sizeof(*sg)); + tsg++; + nr_sg++; + } + err = mxc_dma_sg_config(chan, tmp, nr_sg, 0, dma_mode); + if (err) + printk(KERN_ERR "pata_fsl_bmdma_setup: error %d\n", + err); + } +} + +static void pata_fsl_bmdma_start(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + struct pata_fsl_priv *priv = ap->host->private_data; + u8 *ata_regs = priv->fsl_ata_regs; + struct fsl_ata_platform_data *plat = ap->dev->platform_data; + int chan; + int err; + unsigned i; + + if (1 == plat->adma_flag) { + i = FSL_ATA_CTRL_DMA_32ADMA | FSL_ATA_CTRL_DMA_ENABLE; + /* The adma mode is used, set dma_start_stop to 1 */ + __raw_writel(i | __raw_readl(ata_regs + FSL_ATA_CONTROL) | + FSL_ATA_CTRL_DMA_STAT_STOP, + ata_regs + FSL_ATA_CONTROL); + } else { + /* + * Start the channel. + */ + chan = qc->dma_dir == DMA_TO_DEVICE ? priv->dma_wchan : + priv->dma_rchan; + + err = mxc_dma_enable(chan); + if (err) + printk(KERN_ERR "%s: : error %d\n", __func__, err); + } + + priv->dma_done = 0; + + ata_sff_exec_command(ap, &qc->tf); +} + +static void pata_fsl_bmdma_stop(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + struct pata_fsl_priv *priv = ap->host->private_data; + u8 *ata_regs = priv->fsl_ata_regs; + struct fsl_ata_platform_data *plat = ap->dev->platform_data; + unsigned i; + + if (plat->adma_flag) { + /* The adma mode is used, set dma_start_stop to 0 */ + i = FSL_ATA_CTRL_DMA_32ADMA | FSL_ATA_CTRL_DMA_ENABLE; + __raw_writel((i | __raw_readl(ata_regs + FSL_ATA_CONTROL)) & + (~FSL_ATA_CTRL_DMA_STAT_STOP), + ata_regs + FSL_ATA_CONTROL); + } + + /* do a dummy read as in ata_bmdma_stop */ +#if 0 + ata_sff_dma_pause(ap); +#endif +} + +static u8 pata_fsl_bmdma_status(struct ata_port *ap) +{ + struct pata_fsl_priv *priv = ap->host->private_data; + + return priv->dma_done ? ATA_DMA_INTR : 0; +} + +static void pata_fsl_dma_init(struct ata_port *ap) +{ + struct pata_fsl_priv *priv = ap->host->private_data; + + priv->dma_rchan = -1; + priv->dma_wchan = -1; + + priv->dma_rchan = mxc_dma_request(MXC_DMA_ATA_RX, "MXC ATA RX"); + if (priv->dma_rchan < 0) { + dev_printk(KERN_ERR, ap->dev, "couldn't get RX DMA channel\n"); + goto err_out; + } + + priv->dma_wchan = mxc_dma_request(MXC_DMA_ATA_TX, "MXC ATA TX"); + if (priv->dma_wchan < 0) { + dev_printk(KERN_ERR, ap->dev, "couldn't get TX DMA channel\n"); + goto err_out; + } + + dev_printk(KERN_ERR, ap->dev, "rchan=%d wchan=%d\n", priv->dma_rchan, + priv->dma_wchan); + return; + + err_out: + ap->mwdma_mask = 0; + ap->udma_mask = 0; + mxc_dma_free(priv->dma_rchan); + mxc_dma_free(priv->dma_wchan); + kfree(priv); +} + +#if 0 +static u8 pata_fsl_irq_ack(struct ata_port *ap, unsigned int chk_drq) +{ + unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY; + u8 status; + + status = ata_sff_busy_wait(ap, bits, 1000); + if (status & bits) + if (ata_msg_err(ap)) + printk(KERN_ERR "abnormal status 0x%X\n", status); + + return status; +} +#endif + +static void ata_dummy_noret(struct ata_port *ap) +{ + return; +} + +static struct scsi_host_template pata_fsl_sht = { + .module = THIS_MODULE, + .name = DRV_NAME, + .ioctl = ata_scsi_ioctl, + .queuecommand = ata_scsi_queuecmd, + .can_queue = ATA_DEF_QUEUE, + .this_id = ATA_SHT_THIS_ID, + .sg_tablesize = LIBATA_MAX_PRD, + .cmd_per_lun = ATA_SHT_CMD_PER_LUN, + .emulated = ATA_SHT_EMULATED, + .use_clustering = ATA_SHT_USE_CLUSTERING, + .proc_name = DRV_NAME, + .dma_boundary = FSL_ATA_MAX_SG_LEN, + .slave_configure = ata_scsi_slave_config, + .slave_destroy = ata_scsi_slave_destroy, + .bios_param = ata_std_bios_param, +}; + +static struct ata_port_operations pata_fsl_port_ops = { + .inherits = &ata_bmdma_port_ops, + .set_piomode = pata_fsl_set_piomode, + .set_dmamode = pata_fsl_set_dmamode, + + .check_atapi_dma = pata_fsl_check_atapi_dma, + .cable_detect = ata_cable_unknown, + .mode_filter = pata_fsl_bmdma_mode_filter, + + .bmdma_setup = pata_fsl_bmdma_setup, + .bmdma_start = pata_fsl_bmdma_start, + .bmdma_stop = pata_fsl_bmdma_stop, + .bmdma_status = pata_fsl_bmdma_status, + + .qc_prep = ata_noop_qc_prep, + + .sff_data_xfer = ata_sff_data_xfer_noirq, + .sff_irq_clear = ata_dummy_noret, + .sff_irq_on = ata_sff_irq_on, + + .port_start = pata_fsl_port_start, +}; + +static void fsl_setup_port(struct ata_ioports *ioaddr) +{ + unsigned int shift = 2; + + ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << shift); + ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << shift); + ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << shift); + ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << shift); + ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << shift); + ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << shift); + ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << shift); + ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << shift); + ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << shift); + ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << shift); +} + +/** + * pata_fsl_probe - attach a platform interface + * @pdev: platform device + * + * Register a platform bus integrated ATA host controller + * + * The 3 platform device resources are used as follows: + * + * - I/O Base (IORESOURCE_MEM) virt. addr. of ATA controller regs + * - CTL Base (IORESOURCE_MEM) unused + * - IRQ (IORESOURCE_IRQ) platform IRQ assigned to ATA + * + */ +static int __devinit pata_fsl_probe(struct platform_device *pdev) +{ + int ret = 0; + struct resource *io_res; + struct ata_host *host; + struct ata_port *ap; + struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *) + pdev->dev.platform_data; + struct pata_fsl_priv *priv; + u8 *ata_regs; + unsigned int int_enable; + + /* + * Set up resources + */ + if (unlikely(pdev->num_resources != 3)) { + dev_err(&pdev->dev, "invalid number of resources\n"); + return -EINVAL; + } + /* + * Get an ata_host structure for this device + */ + host = ata_host_alloc(&pdev->dev, 1); + if (!host) + return -ENOMEM; + ap = host->ports[0]; + + /* + * Allocate private data + */ + priv = kzalloc(sizeof(struct pata_fsl_priv), GFP_KERNEL); + if (priv == NULL) { + ret = -ENOMEM; + goto err0; + } + host->private_data = priv; + + /* + * Set up resources + */ + io_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + ata_regs = + (u8 *) ioremap(io_res->start, io_res->end - io_res->start + 1); + priv->fsl_ata_regs = ata_regs; + ap->ioaddr.cmd_addr = (void *)(ata_regs + FSL_ATA_DRIVE_DATA); + ap->ioaddr.ctl_addr = (void *)(ata_regs + FSL_ATA_DRIVE_CONTROL); + ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr; + ap->ops = &pata_fsl_port_ops; + ap->pio_mask = plat->pio_mask; /* support pio 0~4 */ + ap->mwdma_mask = plat->mwdma_mask; /* support mdma 0~2 */ + ap->udma_mask = plat->udma_mask; + pata_fsl_sht.sg_tablesize = plat->max_sg; + fsl_setup_port(&ap->ioaddr); + + if (plat->adma_flag) { + priv->adma_des_tp = + dma_alloc_coherent(&(pdev->dev), + (2 * MXC_IDE_DMA_BD_NR) * + sizeof(unsigned int), + &(priv->adma_des_paddr), GFP_DMA); + if (priv->adma_des_tp == NULL) { + ret = -ENOMEM; + goto err1; + } + } + /* + * Do platform-specific initialization (e.g. allocate pins, + * turn on clock). After this call it is assumed that + * plat->get_clk_rate() can be called to calculate + * timing. + */ + if (plat->init && plat->init(pdev)) { + ret = -ENODEV; + goto err2; + } + + priv->clk = clk_get(&pdev->dev, "ata_clk"); + clk_enable(priv->clk); + + /* Deassert the reset bit to enable the interface */ + __raw_writel(FSL_ATA_CTRL_ATA_RST_B, ata_regs + FSL_ATA_CONTROL); + + /* Enable Core regulator & IO Regulator */ + if (plat->core_reg != NULL) { + core_reg = regulator_get(&pdev->dev, plat->core_reg); + if (regulator_enable(core_reg)) + printk(KERN_INFO "enable core regulator error.\n"); + msleep(100); + + } else + core_reg = NULL; + + if (plat->io_reg != NULL) { + io_reg = regulator_get(&pdev->dev, plat->io_reg); + if (regulator_enable(io_reg)) + printk(KERN_INFO "enable io regulator error.\n"); + msleep(100); + + } else + io_reg = NULL; + + /* Set initial timing and mode */ + set_ata_bus_timing(XFER_PIO_4, pdev); + + /* get DMA ready */ + if (plat->adma_flag == 0) + pata_fsl_dma_init(ap); + + /* + * Enable the ATA INTRQ interrupt from the bus, but + * only allow the CPU to see it (INTRQ2) at this point. + * INTRQ1, which goes to the DMA, will be enabled later. + */ + int_enable = FSL_ATA_INTR_DMA_TRANS_OVER | FSL_ATA_INTR_DMA_ERR | + FSL_ATA_INTR_ATA_INTRQ2; + if (plat->adma_flag) + __raw_writel(int_enable, ata_regs + FSL_ATA_INT_EN); + else + __raw_writel(FSL_ATA_INTR_ATA_INTRQ2, + ata_regs + FSL_ATA_INT_EN); + + /* activate */ + if (plat->adma_flag) + ret = ata_host_activate(host, platform_get_irq(pdev, 0), + pata_fsl_adma_intr, 0, &pata_fsl_sht); + else + ret = ata_host_activate(host, platform_get_irq(pdev, 0), + ata_sff_interrupt, 0, &pata_fsl_sht); + + if (!ret) + return ret; + + clk_disable(priv->clk); + regulator_disable(core_reg); + regulator_disable(io_reg); + err2: + if (plat->adma_flag && priv->adma_des_tp) + dma_free_coherent(&(pdev->dev), + (2 * MXC_IDE_DMA_BD_NR + + 1) * sizeof(unsigned int), priv->adma_des_tp, + priv->adma_des_paddr); + err1: + iounmap(ata_regs); + kfree(priv); + err0: + ata_host_detach(host); + return ret; + +} + +/** + * pata_fsl_remove - unplug a platform interface + * @pdev: platform device + * + * A platform bus ATA device has been unplugged. Perform the needed + * cleanup. Also called on module unload for any active devices. + */ +static int __devexit pata_fsl_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ata_host *host = dev_get_drvdata(dev); + struct pata_fsl_priv *priv = host->private_data; + struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *) + pdev->dev.platform_data; + u8 *ata_regs = priv->fsl_ata_regs; + + __raw_writel(0, ata_regs + FSL_ATA_INT_EN); /* Disable interrupts */ + + ata_host_detach(host); + + clk_disable(priv->clk); + clk_put(priv->clk); + priv->clk = NULL; + + /* Disable Core regulator & IO Regulator */ + if (plat->core_reg != NULL) { + regulator_disable(core_reg); + regulator_put(core_reg, &pdev->dev); + } + if (plat->io_reg != NULL) { + regulator_disable(io_reg); + regulator_put(io_reg, &pdev->dev); + } + + if (plat->exit) + plat->exit(); + + if (plat->adma_flag && priv->adma_des_tp) + dma_free_coherent(&(pdev->dev), + (2 * MXC_IDE_DMA_BD_NR) * + sizeof(unsigned int), priv->adma_des_tp, + priv->adma_des_paddr); + iounmap(ata_regs); + + kfree(priv); + + return 0; +} + +#ifdef CONFIG_PM +static int pata_fsl_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct ata_host *host = dev_get_drvdata(&pdev->dev); + struct pata_fsl_priv *priv = host->private_data; + struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *) + pdev->dev.platform_data; + u8 *ata_regs = priv->fsl_ata_regs; + + ata_host_suspend(host, state); + + /* Disable interrupts. */ + __raw_writel(0, ata_regs + FSL_ATA_INT_EN); + + clk_disable(priv->clk); + + if (plat->exit) + plat->exit(); + + return 0; +} + +static int pata_fsl_resume(struct platform_device *pdev) +{ + struct ata_host *host = dev_get_drvdata(&pdev->dev); + struct pata_fsl_priv *priv = host->private_data; + struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *) + pdev->dev.platform_data; + u8 *ata_regs = priv->fsl_ata_regs; + unsigned char int_enable; + + if (plat->init && plat->init(pdev)) + return -ENODEV; + + clk_enable(priv->clk); + + /* Deassert the reset bit to enable the interface */ + __raw_writel(FSL_ATA_CTRL_ATA_RST_B, ata_regs + FSL_ATA_CONTROL); + + /* Set initial timing and mode */ + set_ata_bus_timing(XFER_PIO_4, pdev); + + /* + * Enable hardware interrupts. + */ + int_enable = FSL_ATA_INTR_DMA_TRANS_OVER | FSL_ATA_INTR_DMA_ERR | + FSL_ATA_INTR_ATA_INTRQ2; + if (1 == plat->adma_flag) + __raw_writel(int_enable, ata_regs + FSL_ATA_INT_EN); + else + __raw_writel(FSL_ATA_INTR_ATA_INTRQ2, + ata_regs + FSL_ATA_INT_EN); + + ata_host_resume(host); + + return 0; +} +#endif + +static struct platform_driver pata_fsl_driver = { + .probe = pata_fsl_probe, + .remove = __devexit_p(pata_fsl_remove), +#ifdef CONFIG_PM + .suspend = pata_fsl_suspend, + .resume = pata_fsl_resume, +#endif + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init pata_fsl_init(void) +{ + return platform_driver_register(&pata_fsl_driver); + + return 0; +} + +static void __exit pata_fsl_exit(void) +{ + platform_driver_unregister(&pata_fsl_driver); +} + +module_init(pata_fsl_init); +module_exit(pata_fsl_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("low-level driver for Freescale ATA"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/atm/.gitignore linux-2.6.26-lab126/drivers/atm/.gitignore --- linux-2.6.26/drivers/atm/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/atm/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,5 +0,0 @@ -# Ignore generated files -fore200e_mkfirm -fore200e_pca_fw.c -pca200e.bin -pca200e_ecd.bin2 diff -urN linux-2.6.26/drivers/block/floppy.c linux-2.6.26-lab126/drivers/block/floppy.c --- linux-2.6.26/drivers/block/floppy.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/block/floppy.c 2010-08-10 04:16:02.000000000 -0400 @@ -4145,6 +4145,28 @@ { } +static int floppy_suspend(struct platform_device *dev, pm_message_t state) +{ + floppy_release_irq_and_dma(); + + return 0; +} + +static int floppy_resume(struct platform_device *dev) +{ + floppy_grab_irq_and_dma(); + + return 0; +} + +static struct platform_driver floppy_driver = { + .suspend = floppy_suspend, + .resume = floppy_resume, + .driver = { + .name = "floppy", + }, +}; + static struct platform_device floppy_device[N_DRIVE]; static struct kobject *floppy_find(dev_t dev, int *part, void *data) @@ -4193,10 +4215,14 @@ if (err) goto out_put_disk; + err = platform_driver_register(&floppy_driver); + if (err) + goto out_unreg_blkdev; + floppy_queue = blk_init_queue(do_fd_request, &floppy_lock); if (!floppy_queue) { err = -ENOMEM; - goto out_unreg_blkdev; + goto out_unreg_driver; } blk_queue_max_sectors(floppy_queue, 64); @@ -4345,6 +4371,8 @@ out_unreg_region: blk_unregister_region(MKDEV(FLOPPY_MAJOR, 0), 256); blk_cleanup_queue(floppy_queue); +out_unreg_driver: + platform_driver_unregister(&floppy_driver); out_unreg_blkdev: unregister_blkdev(FLOPPY_MAJOR, "fd"); out_put_disk: @@ -4541,6 +4569,7 @@ blk_unregister_region(MKDEV(FLOPPY_MAJOR, 0), 256); unregister_blkdev(FLOPPY_MAJOR, "fd"); + platform_driver_unregister(&floppy_driver); for (drive = 0; drive < N_DRIVE; drive++) { del_timer_sync(&motor_off_timer[drive]); diff -urN linux-2.6.26/drivers/block/paride/pseudo.h linux-2.6.26-lab126/drivers/block/paride/pseudo.h --- linux-2.6.26/drivers/block/paride/pseudo.h 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/block/paride/pseudo.h 2010-08-10 04:16:02.000000000 -0400 @@ -43,7 +43,7 @@ static int ps_tq_active = 0; static int ps_nice = 0; -static DEFINE_SPINLOCK(ps_spinlock __attribute__((unused))); +static __attribute__((unused)) DEFINE_SPINLOCK(ps_spinlock); static DECLARE_DELAYED_WORK(ps_tq, ps_tq_int); diff -urN linux-2.6.26/drivers/char/.gitignore linux-2.6.26-lab126/drivers/char/.gitignore --- linux-2.6.26/drivers/char/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/char/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,2 +0,0 @@ -consolemap_deftbl.c -defkeymap.c diff -urN linux-2.6.26/drivers/char/Kconfig linux-2.6.26-lab126/drivers/char/Kconfig --- linux-2.6.26/drivers/char/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/char/Kconfig 2010-08-10 04:16:24.000000000 -0400 @@ -420,6 +420,17 @@ If you have an SGI Altix with an attached SABrick say Y or M here, otherwise say N. +config FM_SI4702 + tristate "SI4702 FM device driver" + depends on (MACH_MX31_3DS || MACH_MX35_3DS || MACH_MX37_3DS || MACH_MX51_3DS) + default n + +config MXC_IIM + tristate "MXC IIM device driver" + depends on ARCH_MXC + help + Support for access to MXC IIM device. + source "drivers/serial/Kconfig" config UNIX98_PTYS @@ -663,6 +674,26 @@ It is recommended to be used on a NetWinder, but it is not a necessity. +config LUIGI_POWER_BUTTON + tristate "MX35 LUIGI Power Button" + depends on MACH_MX35_LUIGI + ---help--- + If you say Y here and create a character device node /dev/luigibutton + with major and minor numbers 10 and 158 ("man mknod"). + + If this button is held for less than 2 seconds including a momentary + slide, then the device will enter standby mode. + + If this button is held for 2 or more seconds, the device will enter + shutdown mode. + + If the device is hung, then the PMIC has been configured by the + startup code to reset the device if the button is held for 4 or + more seconds. + + To compile this driver as a module, choose M here: the module will + be called luigibutton. + config NWBUTTON tristate "NetWinder Button" depends on ARCH_NETWINDER @@ -797,6 +828,46 @@ To compile this driver as a module, choose M here: the module will be called js-rtc. +config RTC_HISTOGRAM + bool "Real Time Clock Histogram Support" + default n + depends on RTC + ---help--- + If you say Y here then the kernel will track the delivery and + wakeup latency of /dev/rtc using tasks and will report a + histogram to the kernel log when the application closes /dev/rtc. + +config BLOCKER + tristate "Priority Inheritance Debugging (Blocker) Device Support" + depends on X86 + default y + ---help--- + If you say Y here then a device will be created that the userspace + pi_test suite uses to test and measure kernel locking primitives. + +config LPPTEST + tristate "Parallel Port Based Latency Measurement Device" + depends on !PARPORT && X86 + default y + ---help--- + If you say Y here then a device will be created that the userspace + testlpp utility uses to measure IRQ latencies of a target system + from an independent measurement system. + + NOTE: this code assumes x86 PCs and that the parallel port is + bidirectional and is on IRQ 7. + + to use the device, both the target and the source system needs to + run a kernel with CONFIG_LPPTEST enabled. To measure latencies, + use the scripts/testlpp utility in your kernel source directory, + and run it (as root) on the source system - it will start printing + out the latencies it took to get a response from the target system: + + Latency of response: 12.2 usecs (121265 cycles) + + then generate various workloads on the target system to see how + (worst-case-) latencies are impacted. + config SGI_DS1286 tristate "SGI DS1286 RTC support" depends on SGI_HAS_DS1286 @@ -1088,6 +1159,24 @@ /sys/devices/platform/telco_clock, with a number of files for controlling the behavior of this hardware. +config RMEM + tristate "Access to physical memory via /dev/rmem" + default m + help + The /dev/mem device only allows mmap() memory available to + I/O mapped memory; it does not allow access to "real" + physical memory. The /dev/rmem device is a hack which does + allow access to physical memory. We use this instead of + patching /dev/mem because we don't expect this functionality + to ever be accepted into mainline. + +config ALLOC_RTSJ_MEM + tristate "RTSJ-specific hack to reserve memory" + default m + help + The RTSJ TCK conformance test requires reserving some physical + memory for testing /dev/rmem. + config DEVPORT bool depends on !M68K diff -urN linux-2.6.26/drivers/char/Makefile linux-2.6.26-lab126/drivers/char/Makefile --- linux-2.6.26/drivers/char/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/char/Makefile 2010-08-10 04:16:25.000000000 -0400 @@ -9,6 +9,9 @@ obj-y += mem.o random.o tty_io.o n_tty.o tty_ioctl.o +obj-$(CONFIG_FM_SI4702) += mxc_si4702.o +obj-$(CONFIG_MXC_IIM) += mxc_iim.o + obj-$(CONFIG_LEGACY_PTYS) += pty.o obj-$(CONFIG_UNIX98_PTYS) += pty.o obj-y += misc.o @@ -87,8 +90,11 @@ obj-$(CONFIG_I8K) += i8k.o obj-$(CONFIG_DS1620) += ds1620.o obj-$(CONFIG_HW_RANDOM) += hw_random/ +obj-$(CONFIG_BLOCKER) += blocker.o +obj-$(CONFIG_LPPTEST) += lpptest.o obj-$(CONFIG_COBALT_LCD) += lcd.o obj-$(CONFIG_PPDEV) += ppdev.o +obj-$(CONFIG_LUIGI_POWER_BUTTON) += luigi_button.o obj-$(CONFIG_NWBUTTON) += nwbutton.o obj-$(CONFIG_NWFLASH) += nwflash.o obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o @@ -98,7 +104,6 @@ obj-$(CONFIG_GPIO_VR41XX) += vr41xx_giu.o obj-$(CONFIG_GPIO_TB0219) += tb0219.o obj-$(CONFIG_TELCLOCK) += tlclk.o - obj-$(CONFIG_MWAVE) += mwave/ obj-$(CONFIG_AGP) += agp/ obj-$(CONFIG_DRM) += drm/ @@ -113,6 +118,8 @@ obj-$(CONFIG_JS_RTC) += js-rtc.o js-rtc-y = rtc.o +obj-$(CONFIG_ALLOC_RTSJ_MEM) += alloc_rtsj_mem.o + # Files generated that shall be removed upon make clean clean-files := consolemap_deftbl.c defkeymap.c diff -urN linux-2.6.26/drivers/char/alloc_rtsj_mem.c linux-2.6.26-lab126/drivers/char/alloc_rtsj_mem.c --- linux-2.6.26/drivers/char/alloc_rtsj_mem.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/char/alloc_rtsj_mem.c 2010-08-10 04:16:24.000000000 -0400 @@ -0,0 +1,88 @@ +/* + * alloc_rtsj_mem.c -- Hack to allocate some memory + * + * Copyright (C) 2005 by Theodore Ts'o + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +MODULE_AUTHOR("Theodore Tso"); +MODULE_DESCRIPTION("RTSJ alloc memory"); +MODULE_LICENSE("GPL"); + +static void *mem = 0; +int size = 0, addr = 0; + +module_param(size, int, 0444); +module_param(addr, int, 0444); + +static void __exit shutdown_module(void) +{ + kfree(mem); +} + +#ifndef MODULE +void __init alloc_rtsj_mem_early_setup(void) +{ + if (size > PAGE_SIZE*2) { + mem = alloc_bootmem(size); + if (mem) { + printk(KERN_INFO "alloc_rtsj_mem: got %d bytes " + "using alloc_bootmem\n", size); + } else { + printk(KERN_INFO "alloc_rtsj_mem: failed to " + "get %d bytes from alloc_bootmem\n", size); + } + } +} +#endif + +static int __init startup_module(void) +{ + static char test_string[] = "The BOFH: Servicing users the way the " + "military\n\tservices targets for 15 years.\n"; + + if (!size) + return 0; + + if (!mem) { + mem = kmalloc(size, GFP_KERNEL); + if (mem) { + printk(KERN_INFO "alloc_rtsj_mem: got %d bytes " + "using kmalloc\n", size); + } else { + printk(KERN_ERR "alloc_rtsj_mem: failed to get " + "%d bytes using kmalloc\n", size); + return -ENOMEM; + } + } + memcpy(mem, test_string, min(sizeof(test_string), (size_t) size)); + addr = virt_to_phys(mem); + return 0; +} + +module_init(startup_module); +module_exit(shutdown_module); + diff -urN linux-2.6.26/drivers/char/blocker.c linux-2.6.26-lab126/drivers/char/blocker.c --- linux-2.6.26/drivers/char/blocker.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/char/blocker.c 2010-08-10 04:16:25.000000000 -0400 @@ -0,0 +1,109 @@ +/* + * priority inheritance testing device + */ + +#include +#include +#include +#include + +#define BLOCKER_MINOR 221 + +#define BLOCK_IOCTL 4245 +#define BLOCK_SET_DEPTH 4246 + +#define BLOCKER_MAX_LOCK_DEPTH 10 + +void loop(int loops) +{ + int i; + + for (i = 0; i < loops; i++) + get_cycles(); +} + +static spinlock_t blocker_lock[BLOCKER_MAX_LOCK_DEPTH]; + +static unsigned int lock_depth = 1; + +void do_the_lock_and_loop(unsigned int args) +{ + int i, max; + + if (rt_task(current)) + max = lock_depth; + else if (lock_depth > 1) + max = (current->pid % lock_depth) + 1; + else + max = 1; + + /* Always lock from the top down */ + for (i = max-1; i >= 0; i--) + spin_lock(&blocker_lock[i]); + loop(args); + for (i = 0; i < max; i++) + spin_unlock(&blocker_lock[i]); +} + +static int blocker_open(struct inode *in, struct file *file) +{ + printk(KERN_INFO "blocker_open called\n"); + + return 0; +} + +static long blocker_ioctl(struct file *file, + unsigned int cmd, unsigned long args) +{ + switch(cmd) { + case BLOCK_IOCTL: + do_the_lock_and_loop(args); + return 0; + case BLOCK_SET_DEPTH: + if (args >= BLOCKER_MAX_LOCK_DEPTH) + return -EINVAL; + lock_depth = args; + return 0; + default: + return -EINVAL; + } +} + +static struct file_operations blocker_fops = { + .owner = THIS_MODULE, + .llseek = no_llseek, + .unlocked_ioctl = blocker_ioctl, + .open = blocker_open, +}; + +static struct miscdevice blocker_dev = +{ + BLOCKER_MINOR, + "blocker", + &blocker_fops +}; + +static int __init blocker_init(void) +{ + int i; + + if (misc_register(&blocker_dev)) + return -ENODEV; + + for (i = 0; i < BLOCKER_MAX_LOCK_DEPTH; i++) + spin_lock_init(blocker_lock + i); + + return 0; +} + +void __exit blocker_exit(void) +{ + printk(KERN_INFO "blocker device uninstalled\n"); + misc_deregister(&blocker_dev); +} + +module_init(blocker_init); +module_exit(blocker_exit); + +MODULE_LICENSE("GPL"); + diff -urN linux-2.6.26/drivers/char/hw_random/Kconfig linux-2.6.26-lab126/drivers/char/hw_random/Kconfig --- linux-2.6.26/drivers/char/hw_random/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/char/hw_random/Kconfig 2010-08-10 04:16:24.000000000 -0400 @@ -46,6 +46,30 @@ If unsure, say Y. +config HW_RANDOM_FSL_RNGA + tristate "Freescale RNGA Random Number Generator" + depends on HW_RANDOM && ARCH_HAS_RNGA && !MXC_SECURITY_RNG + ---help--- + This driver provides kernel-side support for the Random Number + Generator hardware found on Freescale i.MX processors. + + To compile this driver as a module, choose M here: the + module will be called fsl-rnga. + + If unsure, say Y. + +config HW_RANDOM_FSL_RNGC + tristate "Freescale RNGC Random Number Generator" + depends on HW_RANDOM && ARCH_HAS_RNGC && !MXC_SECURITY_RNG + ---help--- + This driver provides kernel-side support for the Random Number + Generator hardware found on Freescale i.MX processors. + + To compile this driver as a module, choose M here: the + module will be called fsl-rngc. + + If unsure, say Y. + config HW_RANDOM_GEODE tristate "AMD Geode HW Random Number Generator support" depends on HW_RANDOM && X86_32 && PCI diff -urN linux-2.6.26/drivers/char/hw_random/Makefile linux-2.6.26-lab126/drivers/char/hw_random/Makefile --- linux-2.6.26/drivers/char/hw_random/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/char/hw_random/Makefile 2010-08-10 04:16:24.000000000 -0400 @@ -6,6 +6,8 @@ rng-core-y := core.o obj-$(CONFIG_HW_RANDOM_INTEL) += intel-rng.o obj-$(CONFIG_HW_RANDOM_AMD) += amd-rng.o +obj-$(CONFIG_HW_RANDOM_FSL_RNGA) += fsl-rnga.o +obj-$(CONFIG_HW_RANDOM_FSL_RNGC) += fsl-rngc.o obj-$(CONFIG_HW_RANDOM_GEODE) += geode-rng.o obj-$(CONFIG_HW_RANDOM_VIA) += via-rng.o obj-$(CONFIG_HW_RANDOM_IXP4XX) += ixp4xx-rng.o diff -urN linux-2.6.26/drivers/char/hw_random/fsl-rnga.c linux-2.6.26-lab126/drivers/char/hw_random/fsl-rnga.c --- linux-2.6.26/drivers/char/hw_random/fsl-rnga.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/char/hw_random/fsl-rnga.c 2010-08-10 04:16:24.000000000 -0400 @@ -0,0 +1,238 @@ +/* + * RNG driver for Freescale RNGA + * + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG) + * (c) Copyright 2003 Red Hat Inc + * + * derived from + * + * Hardware driver for the AMD 768 Random Number Generator (RNG) + * (c) Copyright 2001 Red Hat Inc + * + * derived from + * + * Hardware driver for Intel i810 Random Number Generator (RNG) + * Copyright 2000,2001 Jeff Garzik + * Copyright 2000,2001 Philipp Rumpf + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* RNGA Registers */ +#define RNGA_CONTROL 0x00 +#define RNGA_STATUS 0x04 +#define RNGA_ENTROPY 0x08 +#define RNGA_OUTPUT_FIFO 0x0c +#define RNGA_MODE 0x10 +#define RNGA_VERIFICATION_CONTROL 0x14 +#define RNGA_OSC_CONTROL_COUNTER 0x18 +#define RNGA_OSC1_COUNTER 0x1c +#define RNGA_OSC2_COUNTER 0x20 +#define RNGA_OSC_COUNTER_STATUS 0x24 + +/* RNGA Registers Range */ +#define RNG_ADDR_RANGE 0x28 + +/* RNGA Control Register */ +#define RNGA_CONTROL_SLEEP 0x00000010 +#define RNGA_CONTROL_CLEAR_INT 0x00000008 +#define RNGA_CONTROL_MASK_INTS 0x00000004 +#define RNGA_CONTROL_HIGH_ASSURANCE 0x00000002 +#define RNGA_CONTROL_GO 0x00000001 + +#define RNGA_STATUS_LEVEL_MASK 0x0000ff00 + +/* RNGA Status Register */ +#define RNGA_STATUS_OSC_DEAD 0x80000000 +#define RNGA_STATUS_SLEEP 0x00000010 +#define RNGA_STATUS_ERROR_INT 0x00000008 +#define RNGA_STATUS_FIFO_UNDERFLOW 0x00000004 +#define RNGA_STATUS_LAST_READ_STATUS 0x00000002 +#define RNGA_STATUS_SECURITY_VIOLATION 0x00000001 + +static struct platform_device *rng_dev; + +static int fsl_rnga_data_present(struct hwrng *rng) +{ + int level; + u32 rng_base = (u32) rng->priv; + + /* how many random numbers is in FIFO? [0-16] */ + level = ((__raw_readl(rng_base + RNGA_STATUS) & + RNGA_STATUS_LEVEL_MASK) >> 8); + + return level > 0 ? 1 : 0; +} + +static int fsl_rnga_data_read(struct hwrng *rng, u32 * data) +{ + int err; + u32 ctrl, rng_base = (u32) rng->priv; + + /* retrieve a random number from FIFO */ + *data = __raw_readl(rng_base + RNGA_OUTPUT_FIFO); + + /* some error while reading this random number? */ + err = __raw_readl(rng_base + RNGA_STATUS) & RNGA_STATUS_ERROR_INT; + + /* if error: clear error interrupt, but doesn't return random number */ + if (err) { + dev_dbg(&rng_dev->dev, "Error while reading random number!\n"); + ctrl = __raw_readl(rng_base + RNGA_CONTROL); + __raw_writel(ctrl | RNGA_CONTROL_CLEAR_INT, + rng_base + RNGA_CONTROL); + return 0; + } else + return 4; +} + +static int fsl_rnga_init(struct hwrng *rng) +{ + u32 ctrl, osc, rng_base = (u32) rng->priv; + + /* wake up */ + ctrl = __raw_readl(rng_base + RNGA_CONTROL); + __raw_writel(ctrl & ~RNGA_CONTROL_SLEEP, rng_base + RNGA_CONTROL); + + /* verify if oscillator is working */ + osc = __raw_readl(rng_base + RNGA_STATUS); + if (osc & RNGA_STATUS_OSC_DEAD) { + dev_err(&rng_dev->dev, "RNGA Oscillator is dead!\n"); + return -ENODEV; + } + + /* go running */ + ctrl = __raw_readl(rng_base + RNGA_CONTROL); + __raw_writel(ctrl | RNGA_CONTROL_GO, rng_base + RNGA_CONTROL); + + return 0; +} + +static void fsl_rnga_cleanup(struct hwrng *rng) +{ + u32 ctrl, rng_base = (u32) rng->priv; + + ctrl = __raw_readl(rng_base + RNGA_CONTROL); + + /* stop rnga */ + __raw_writel(ctrl & ~RNGA_CONTROL_GO, rng_base + RNGA_CONTROL); +} + +static struct hwrng fsl_rnga = { + .name = "fsl-rnga", + .init = fsl_rnga_init, + .cleanup = fsl_rnga_cleanup, + .data_present = fsl_rnga_data_present, + .data_read = fsl_rnga_data_read +}; + +static int __init fsl_rnga_probe(struct platform_device *pdev) +{ + int err = -ENODEV; + struct clk *clk; + struct resource *res, *mem; + void __iomem *rng_base = NULL; + + if (rng_dev) + return -EBUSY; + + clk = clk_get(NULL, "rng_clk"); + + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Could not get rng_clk!\n"); + err = PTR_ERR(clk); + return err; + } + + clk_enable(clk); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (!res) + return -ENOENT; + + mem = request_mem_region(res->start, res->end - res->start, pdev->name); + + if (mem == NULL) + return -EBUSY; + + dev_set_drvdata(&pdev->dev, mem); + rng_base = ioremap(res->start, res->end - res->start); + + fsl_rnga.priv = (unsigned long)rng_base; + + err = hwrng_register(&fsl_rnga); + if (err) { + dev_err(&pdev->dev, "FSL RNGA registering failed (%d)\n", err); + return err; + } + + rng_dev = pdev; + + dev_info(&pdev->dev, "FSL RNGA Registered.\n"); + + return 0; +} + +static int __exit fsl_rnga_remove(struct platform_device *pdev) +{ + struct resource *mem = dev_get_drvdata(&pdev->dev); + void __iomem *rng_base = (void __iomem *)fsl_rnga.priv; + + hwrng_unregister(&fsl_rnga); + + release_resource(mem); + + iounmap(rng_base); + + return 0; +} + +static struct platform_driver fsl_rnga_driver = { + .driver = { + .name = "fsl_rnga", + .owner = THIS_MODULE, + }, + .remove = __exit_p(fsl_rnga_remove), +}; + +static int __init mod_init(void) +{ + return platform_driver_probe(&fsl_rnga_driver, fsl_rnga_probe); +} + +static void __exit mod_exit(void) +{ + platform_driver_unregister(&fsl_rnga_driver); +} + +module_init(mod_init); +module_exit(mod_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("H/W RNGA driver for i.MX"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/char/hw_random/fsl-rngc.c linux-2.6.26-lab126/drivers/char/hw_random/fsl-rngc.c --- linux-2.6.26/drivers/char/hw_random/fsl-rngc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/char/hw_random/fsl-rngc.c 2010-08-10 04:16:24.000000000 -0400 @@ -0,0 +1,372 @@ +/* + * RNG driver for Freescale RNGC + * + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG) + * (c) Copyright 2003 Red Hat Inc + * + * derived from + * + * Hardware driver for the AMD 768 Random Number Generator (RNG) + * (c) Copyright 2001 Red Hat Inc + * + * derived from + * + * Hardware driver for Intel i810 Random Number Generator (RNG) + * Copyright 2000,2001 Jeff Garzik + * Copyright 2000,2001 Philipp Rumpf + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RNGC_VERSION_MAJOR3 3 + +#define RNGC_VERSION_ID 0x0000 +#define RNGC_COMMAND 0x0004 +#define RNGC_CONTROL 0x0008 +#define RNGC_STATUS 0x000C +#define RNGC_ERROR 0x0010 +#define RNGC_FIFO 0x0014 +#define RNGC_VERIF_CTRL 0x0020 +#define RNGC_OSC_CTRL_COUNT 0x0028 +#define RNGC_OSC_COUNT 0x002C +#define RNGC_OSC_COUNT_STATUS 0x0030 + +#define RNGC_VERID_ZEROS_MASK 0x0f000000 +#define RNGC_VERID_RNG_TYPE_MASK 0xf0000000 +#define RNGC_VERID_RNG_TYPE_SHIFT 28 +#define RNGC_VERID_CHIP_VERSION_MASK 0x00ff0000 +#define RNGC_VERID_CHIP_VERSION_SHIFT 16 +#define RNGC_VERID_VERSION_MAJOR_MASK 0x0000ff00 +#define RNGC_VERID_VERSION_MAJOR_SHIFT 8 +#define RNGC_VERID_VERSION_MINOR_MASK 0x000000ff +#define RNGC_VERID_VERSION_MINOR_SHIFT 0 + +#define RNGC_CMD_ZEROS_MASK 0xffffff8c +#define RNGC_CMD_SW_RST 0x00000040 +#define RNGC_CMD_CLR_ERR 0x00000020 +#define RNGC_CMD_CLR_INT 0x00000010 +#define RNGC_CMD_SEED 0x00000002 +#define RNGC_CMD_SELF_TEST 0x00000001 + +#define RNGC_CTRL_ZEROS_MASK 0xfffffc8c +#define RNGC_CTRL_CTL_ACC 0x00000200 +#define RNGC_CTRL_VERIF_MODE 0x00000100 +#define RNGC_CTRL_MASK_ERROR 0x00000040 + +#define RNGC_CTRL_MASK_DONE 0x00000020 +#define RNGC_CTRL_AUTO_SEED 0x00000010 +#define RNGC_CTRL_FIFO_UFLOW_MASK 0x00000003 +#define RNGC_CTRL_FIFO_UFLOW_SHIFT 0 + +#define RNGC_CTRL_FIFO_UFLOW_ZEROS_ERROR 0 +#define RNGC_CTRL_FIFO_UFLOW_ZEROS_ERROR2 1 +#define RNGC_CTRL_FIFO_UFLOW_BUS_XFR 2 +#define RNGC_CTRL_FIFO_UFLOW_ZEROS_INTR 3 + +#define RNGC_STATUS_ST_PF_MASK 0x00c00000 +#define RNGC_STATUS_ST_PF_SHIFT 22 +#define RNGC_STATUS_ST_PF_TRNG 0x00800000 +#define RNGC_STATUS_ST_PF_PRNG 0x00400000 +#define RNGC_STATUS_ERROR 0x00010000 +#define RNGC_STATUS_FIFO_SIZE_MASK 0x0000f000 +#define RNGC_STATUS_FIFO_SIZE_SHIFT 12 +#define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00 +#define RNGC_STATUS_FIFO_LEVEL_SHIFT 8 +#define RNGC_STATUS_NEXT_SEED_DONE 0x00000040 +#define RNGC_STATUS_SEED_DONE 0x00000020 +#define RNGC_STATUS_ST_DONE 0x00000010 +#define RNGC_STATUS_RESEED 0x00000008 +#define RNGC_STATUS_SLEEP 0x00000004 +#define RNGC_STATUS_BUSY 0x00000002 +#define RNGC_STATUS_SEC_STATE 0x00000001 + +#define RNGC_ERROR_STATUS_ZEROS_MASK 0xffffffc0 +#define RNGC_ERROR_STATUS_BAD_KEY 0x00000040 +#define RNGC_ERROR_STATUS_RAND_ERR 0x00000020 +#define RNGC_ERROR_STATUS_FIFO_ERR 0x00000010 +#define RNGC_ERROR_STATUS_STAT_ERR 0x00000008 +#define RNGC_ERROR_STATUS_ST_ERR 0x00000004 +#define RNGC_ERROR_STATUS_OSC_ERR 0x00000002 +#define RNGC_ERROR_STATUS_LFSR_ERR 0x00000001 + +#define RNG_ADDR_RANGE 0x34 + +static DECLARE_COMPLETION(rng_self_testing); +static DECLARE_COMPLETION(rng_seed_done); + +static struct platform_device *rng_dev; + +int irq_rng; + +static int fsl_rngc_data_present(struct hwrng *rng) +{ + int level; + u32 rngc_base = (u32) rng->priv; + + /* how many random numbers are in FIFO? [0-16] */ + level = (__raw_readl(rngc_base + RNGC_STATUS) & + RNGC_STATUS_FIFO_LEVEL_MASK) >> RNGC_STATUS_FIFO_LEVEL_SHIFT; + + return level > 0 ? 1 : 0; +} + +static int fsl_rngc_data_read(struct hwrng *rng, u32 * data) +{ + int err; + u32 rngc_base = (u32) rng->priv; + + /* retrieve a random number from FIFO */ + *data = __raw_readl(rngc_base + RNGC_FIFO); + + /* is there some error while reading this random number? */ + err = __raw_readl(rngc_base + RNGC_STATUS) & RNGC_STATUS_ERROR; + + /* if error happened doesn't return random number */ + return err ? 0 : 4; +} + +static irqreturn_t rngc_irq(int irq, void *dev) +{ + int handled = 0; + u32 rngc_base = (u32) dev; + + /* is the seed creation done? */ + if (__raw_readl(rngc_base + RNGC_STATUS) & RNGC_STATUS_SEED_DONE) { + complete(&rng_seed_done); + __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR, + rngc_base + RNGC_COMMAND); + handled = 1; + } + + /* is the self test done? */ + if (__raw_readl(rngc_base + RNGC_STATUS) & RNGC_STATUS_ST_DONE) { + complete(&rng_self_testing); + __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR, + rngc_base + RNGC_COMMAND); + handled = 1; + } + + /* is there any error? */ + if (__raw_readl(rngc_base + RNGC_STATUS) & RNGC_STATUS_ERROR) { + /* clear interrupt */ + __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR, + rngc_base + RNGC_COMMAND); + handled = 1; + } + + return handled; +} + +static int fsl_rngc_init(struct hwrng *rng) +{ + int err; + u32 cmd, ctrl, osc, rngc_base = (u32) rng->priv; + + INIT_COMPLETION(rng_self_testing); + INIT_COMPLETION(rng_seed_done); + + err = __raw_readl(rngc_base + RNGC_STATUS) & RNGC_STATUS_ERROR; + if (err) { + /* is this a bad keys error ? */ + if (__raw_readl(rngc_base + RNGC_ERROR) & + RNGC_ERROR_STATUS_BAD_KEY) { + dev_err(&rng_dev->dev, "Can't start, Bad Keys.\n"); + return -EIO; + } + } + + /* mask all interrupts, will be unmasked soon */ + ctrl = __raw_readl(rngc_base + RNGC_CONTROL); + __raw_writel(ctrl | RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR, + rngc_base + RNGC_CONTROL); + + /* verify if oscillator is working */ + osc = __raw_readl(rngc_base + RNGC_ERROR); + if (osc & RNGC_ERROR_STATUS_OSC_ERR) { + dev_err(&rng_dev->dev, "RNGC Oscillator is dead!\n"); + return -EIO; + } + + err = request_irq(irq_rng, rngc_irq, 0, "fsl_rngc", (void *)rng->priv); + if (err) { + dev_err(&rng_dev->dev, "Can't get interrupt working.\n"); + return -EIO; + } + + /* do self test, repeat until get success */ + do { + /* clear error */ + cmd = __raw_readl(rngc_base + RNGC_COMMAND); + __raw_writel(cmd | RNGC_CMD_CLR_ERR, rngc_base + RNGC_COMMAND); + + /* unmask all interrupt */ + ctrl = __raw_readl(rngc_base + RNGC_CONTROL); + __raw_writel(ctrl & ~(RNGC_CTRL_MASK_DONE | + RNGC_CTRL_MASK_ERROR), rngc_base + RNGC_CONTROL); + + /* run self test */ + cmd = __raw_readl(rngc_base + RNGC_COMMAND); + __raw_writel(cmd | RNGC_CMD_SELF_TEST, + rngc_base + RNGC_COMMAND); + + wait_for_completion(&rng_self_testing); + + } while (__raw_readl(rngc_base + RNGC_ERROR) & + RNGC_ERROR_STATUS_ST_ERR); + + /* clear interrupt. Is it really necessary here? */ + __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR, + rngc_base + RNGC_COMMAND); + + /* create seed, repeat while there is some statistical error */ + do { + /* clear error */ + cmd = __raw_readl(rngc_base + RNGC_COMMAND); + __raw_writel(cmd | RNGC_CMD_CLR_ERR, rngc_base + RNGC_COMMAND); + + /* seed creation */ + cmd = __raw_readl(rngc_base + RNGC_COMMAND); + __raw_writel(cmd | RNGC_CMD_SEED, rngc_base + RNGC_COMMAND); + + wait_for_completion(&rng_seed_done); + + } while (__raw_readl(rngc_base + RNGC_ERROR) & + RNGC_ERROR_STATUS_STAT_ERR); + + err = __raw_readl(rngc_base + RNGC_ERROR) & + (RNGC_ERROR_STATUS_STAT_ERR | + RNGC_ERROR_STATUS_RAND_ERR | + RNGC_ERROR_STATUS_FIFO_ERR | + RNGC_ERROR_STATUS_ST_ERR | + RNGC_ERROR_STATUS_OSC_ERR | + RNGC_ERROR_STATUS_LFSR_ERR); + + if (err) { + dev_err(&rng_dev->dev, "FSL RNGC appears inoperable.\n"); + return -EIO; + } + + return 0; +} + +static struct hwrng fsl_rngc = { + .name = "fsl-rngc", + .init = fsl_rngc_init, + .data_present = fsl_rngc_data_present, + .data_read = fsl_rngc_data_read +}; + +static int __init fsl_rngc_probe(struct platform_device *pdev) +{ + int err = -ENODEV; + struct clk *clk; + struct resource *res, *mem; + void __iomem *rngc_base = NULL; + + if (rng_dev) + return -EBUSY; + + clk = clk_get(NULL, "rng_clk"); + + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Can not get rng_clk\n"); + err = PTR_ERR(clk); + return err; + } + + clk_enable(clk); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (!res) + return -ENOENT; + + mem = request_mem_region(res->start, res->end - res->start, pdev->name); + + if (mem == NULL) + return -EBUSY; + + dev_set_drvdata(&pdev->dev, mem); + rngc_base = ioremap(res->start, res->end - res->start); + + fsl_rngc.priv = (unsigned long)rngc_base; + + irq_rng = platform_get_irq(pdev, 0); + + err = hwrng_register(&fsl_rngc); + if (err) { + dev_err(&pdev->dev, "FSL RNGC registering failed (%d)\n", err); + return err; + } + + rng_dev = pdev; + + dev_info(&pdev->dev, "FSL RNGC Registered.\n"); + + return 0; +} + +static int __exit fsl_rngc_remove(struct platform_device *pdev) +{ + struct resource *mem = dev_get_drvdata(&pdev->dev); + void __iomem *rngc_base = (void __iomem *)fsl_rngc.priv; + + hwrng_unregister(&fsl_rngc); + + release_resource(mem); + + iounmap(rngc_base); + + return 0; +} + +static struct platform_driver fsl_rngc_driver = { + .driver = { + .name = "fsl_rngc", + .owner = THIS_MODULE, + }, + .remove = __exit_p(fsl_rngc_remove), +}; + +static int __init mod_init(void) +{ + return platform_driver_probe(&fsl_rngc_driver, fsl_rngc_probe); +} + +static void __exit mod_exit(void) +{ + platform_driver_unregister(&fsl_rngc_driver); +} + +module_init(mod_init); +module_exit(mod_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("H/W RNGC driver for i.MX"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/char/lpptest.c linux-2.6.26-lab126/drivers/char/lpptest.c --- linux-2.6.26/drivers/char/lpptest.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/char/lpptest.c 2010-08-10 04:16:24.000000000 -0400 @@ -0,0 +1,178 @@ +/* + * /dev/lpptest device: test IRQ handling latencies over parallel port + * + * Copyright (C) 2005 Thomas Gleixner, Ingo Molnar + * + * licensed under the GPL + * + * You need to have CONFIG_PARPORT disabled for this device, it is a + * completely self-contained device that assumes sole ownership of the + * parallel port. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * API wrappers so that the code can be shared with the -rt tree: + */ +#ifndef local_irq_disable +# define local_irq_disable local_irq_disable +# define local_irq_enable local_irq_enable +#endif + +#ifndef IRQ_NODELAY +# define IRQ_NODELAY 0 +# define IRQF_NODELAY 0 +#endif + +/* + * Driver: + */ +#define LPPTEST_CHAR_MAJOR 245 +#define LPPTEST_DEVICE_NAME "lpptest" + +#define LPPTEST_IRQ 7 + +#define LPPTEST_TEST _IOR (LPPTEST_CHAR_MAJOR, 1, unsigned long long) +#define LPPTEST_DISABLE _IOR (LPPTEST_CHAR_MAJOR, 2, unsigned long long) +#define LPPTEST_ENABLE _IOR (LPPTEST_CHAR_MAJOR, 3, unsigned long long) + +static char dev_id[] = "lpptest"; + +#define INIT_PORT() outb(0x04, 0x37a) +#define ENABLE_IRQ() outb(0x10, 0x37a) +#define DISABLE_IRQ() outb(0, 0x37a) + +static unsigned char out = 0x5a; + +/** + * Interrupt handler. Flip a bit in the reply. + */ +static int lpptest_irq (int irq, void *dev_id) +{ + out ^= 0xff; + outb(out, 0x378); + + return IRQ_HANDLED; +} + +static cycles_t test_response(void) +{ + cycles_t now, end; + unsigned char in; + int timeout = 0; + + local_irq_disable(); + in = inb(0x379); + inb(0x378); + outb(0x08, 0x378); + now = get_cycles(); + while(1) { + if (inb(0x379) != in) + break; + if (timeout++ > 1000000) { + outb(0x00, 0x378); + local_irq_enable(); + + return 0; + } + } + end = get_cycles(); + outb(0x00, 0x378); + local_irq_enable(); + + return end - now; +} + +static int lpptest_open(struct inode *inode, struct file *file) +{ + return 0; +} + +static int lpptest_close(struct inode *inode, struct file *file) +{ + return 0; +} + +int lpptest_ioctl(struct inode *inode, struct file *file, unsigned int ioctl_num, unsigned long ioctl_param) +{ + int retval = 0; + + switch (ioctl_num) { + + case LPPTEST_DISABLE: + DISABLE_IRQ(); + break; + + case LPPTEST_ENABLE: + ENABLE_IRQ(); + break; + + case LPPTEST_TEST: { + + cycles_t diff = test_response(); + if (copy_to_user((void *)ioctl_param, (void*) &diff, sizeof(diff))) + goto errcpy; + break; + } + default: retval = -EINVAL; + } + + return retval; + + errcpy: + return -EFAULT; +} + +static struct file_operations lpptest_dev_fops = { + .ioctl = lpptest_ioctl, + .open = lpptest_open, + .release = lpptest_close, +}; + +static int __init lpptest_init (void) +{ + if (register_chrdev(LPPTEST_CHAR_MAJOR, LPPTEST_DEVICE_NAME, &lpptest_dev_fops)) + { + printk(KERN_NOTICE "Can't allocate major number %d for lpptest.\n", + LPPTEST_CHAR_MAJOR); + return -EAGAIN; + } + + if (request_irq (LPPTEST_IRQ, lpptest_irq, 0, "lpptest", dev_id)) { + printk (KERN_WARNING "lpptest: irq %d in use. Unload parport module!\n", LPPTEST_IRQ); + unregister_chrdev(LPPTEST_CHAR_MAJOR, LPPTEST_DEVICE_NAME); + return -EAGAIN; + } + irq_desc[LPPTEST_IRQ].status |= IRQ_NODELAY; + irq_desc[LPPTEST_IRQ].action->flags |= IRQF_NODELAY | IRQF_DISABLED; + + INIT_PORT(); + ENABLE_IRQ(); + + return 0; +} +module_init (lpptest_init); + +static void __exit lpptest_exit (void) +{ + DISABLE_IRQ(); + + free_irq(LPPTEST_IRQ, dev_id); + unregister_chrdev(LPPTEST_CHAR_MAJOR, LPPTEST_DEVICE_NAME); +} +module_exit (lpptest_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("lpp test module"); + diff -urN linux-2.6.26/drivers/char/luigi_button.c linux-2.6.26-lab126/drivers/char/luigi_button.c --- linux-2.6.26/drivers/char/luigi_button.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/char/luigi_button.c 2010-08-11 00:35:01.000000000 -0400 @@ -0,0 +1,234 @@ +/* + * Amazon MX35 Luigi Power Button + * Copyright (C) 2008 Manish Lachwani + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* There are 3 buttons on the Atlas PMIC and we use ONOFD1 */ +#define LUIGI_BUTTON_MINOR 158 /* Major 10, Minor 158, /dev/luigibutton */ + +/* + * Uses Atlas PMIC + */ +#include +#include + +static int mb_evt[2] = {KOBJ_OFFLINE, KOBJ_ONLINE}; + +static struct miscdevice button_misc_device = { + LUIGI_BUTTON_MINOR, + "luigibutton", + NULL, +}; + +/* Wakeup the UART on power button */ +extern void mxcuart_enable_clk(void); + +#define LED_BLINK_THRESHOLD 2000 /* Blink for 2 seconds only */ +#define CHGDETS 0x40 +#define GREEN_LED_MASK 0x3f +#define GREEN_LED_LSH 15 + +extern int luigi_button_green_led; + +/* + * Is a charger connected? + */ +static int charger_connected(void) +{ + int sense_0 = 0; + int ret = 0; /* Default: no charger */ + + pmic_read_reg(REG_INT_SENSE0, &sense_0, 0xffffff); + if (sense_0 & CHGDETS) + ret = 1; + + return ret; +} + +static void pmic_enable_green_led(int enable) +{ + if (enable) { + mc13892_bklit_set_current(LIT_GREEN, 0x7); + mc13892_bklit_set_ramp(LIT_GREEN, 0); + mc13892_bklit_set_dutycycle(LIT_GREEN, 0x3f); + } + else { + mc13892_bklit_set_current(LIT_GREEN, 0); + mc13892_bklit_set_dutycycle(LIT_GREEN, 0); + } +} + +static int bp_pressed = 0; + +static void led_timer_handle_work(struct work_struct *work); +static DECLARE_DELAYED_WORK(led_timer_work, led_timer_handle_work); + +static void led_timer_handle_work(struct work_struct *work) +{ + unsigned int sense; + + pmic_read_reg(REG_INT_SENSE1, &sense, (1 << 3)); + + /* Check if button still pressed after 4 seconds */ + if (bp_pressed) { + /* If button still pressed, blink LED twice */ + if (!(sense & (1 << 3)) ) { + pmic_enable_green_led(0); + mdelay(200); + pmic_enable_green_led(1); + mdelay(200); + pmic_enable_green_led(0); + mdelay(200); + pmic_enable_green_led(1); + mdelay(200); + pmic_enable_green_led(0); + } + else + pmic_enable_green_led(0); + + /* Clear the state */ + bp_pressed = 0; + luigi_button_green_led = 0; + + return; + } + + if (!(sense & (1 << 3))) { + /* Still pressed after 2 seconds, reschedule workqueue after 2 seconds */ + bp_pressed = 1; + schedule_delayed_work(&led_timer_work, msecs_to_jiffies(LED_BLINK_THRESHOLD)); + } + else { + pmic_enable_green_led(0); + luigi_button_green_led = 0; + } +} + +/* + * Interrupt triggered when button pressed + */ +static void luigi_button_handler(void *param) +{ + unsigned int sense; + unsigned int press_event = 0; + int i; + int pb_counter = 100; /* Monitor 15 second battery cut */ + + if (!charger_connected()) { + /* Set the green LED only if charger not connected */ + pmic_enable_green_led(1); + luigi_button_green_led = 1; + schedule_delayed_work(&led_timer_work, msecs_to_jiffies(LED_BLINK_THRESHOLD)); + } + + /* + * reset button - restart + */ + pmic_power_set_auto_reset_en(0); + pmic_power_set_conf_button(BT_ON1B, 0, 2); + + pmic_read_reg(REG_INT_SENSE1, &sense, (1 << 3)); + + if (!(sense & (1 << 3))) { + /* Delay of about 2sec */ + for (i = 0; i < 100; i++) { + pmic_read_reg(REG_INT_SENSE1, &sense, (1 << 3)); + + if (sense & (1 << 3)) { + press_event = 1; + break; + } + + msleep(35); + } + } else { + pmic_power_set_auto_reset_en(1); + pmic_power_set_conf_button(BT_ON1B, 1, 2); + press_event = 1; + } + + if (kobject_uevent(&button_misc_device.this_device->kobj, + mb_evt[press_event])) + printk(KERN_WARNING "luigibutton: can't send uevent\n"); + + if (!press_event) + do { + msleep(50); + if (--pb_counter == 0) + printk(KERN_EMERG "bcut: C def:pcut:pending 15 second battery cut:\n"); + pmic_read_reg(REG_INT_SENSE1, &sense, (1 << 3)); + } while (!(sense & (1 << 3))); + + /* Atlas N1B interrupt line debouce is 30 ms */ + msleep(40); + + /* ignore release interrupts */ + pmic_write_reg(REG_INT_STATUS1, (1 << 3), (1 << 3)); + + pmic_write_reg(REG_INT_MASK1, 0, (1 << 3)); + + mxcuart_enable_clk(); +} + +static int __init luigi_power_button_init(void) +{ + printk (KERN_INFO "Amazon MX35 Luigi Power Button Driver\n"); + + if (misc_register (&button_misc_device)) { + printk (KERN_WARNING "luigibutton: Couldn't register device 10, " + "%d.\n", LUIGI_BUTTON_MINOR); + return -EBUSY; + } + + if (pmic_power_set_conf_button(BT_ON1B, 0, 2)) { + printk(KERN_WARNING "luigibutton: can't configure debounce " + "time\n"); + misc_deregister(&button_misc_device); + return -EIO; + } + + if (pmic_power_event_sub(PWR_IT_ONOFD1I, luigi_button_handler)) { + printk(KERN_WARNING "luigibutton: can't subscribe to IRQ\n"); + misc_deregister(&button_misc_device); + return -EIO; + } + + /* Success */ + return 0; +} + +static void __exit luigi_power_button_exit(void) +{ + pmic_power_event_unsub(PWR_IT_ONOFD1I, luigi_button_handler); + misc_deregister (&button_misc_device); +} + +MODULE_AUTHOR("Manish Lachwani"); +MODULE_LICENSE("GPL"); + +module_init(luigi_power_button_init); +module_exit(luigi_power_button_exit); + diff -urN linux-2.6.26/drivers/char/mxc_iim.c linux-2.6.26-lab126/drivers/char/mxc_iim.c --- linux-2.6.26/drivers/char/mxc_iim.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/char/mxc_iim.c 2010-08-10 04:16:25.000000000 -0400 @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2010 Amazon Technologies, Inc. All Rights Reserved. + * Manish Lachwani (lachwani@lab126.com). + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include + +static unsigned long iim_reg_base, iim_reg_end, iim_reg_size; +static struct clk *iim_clk; +static struct device *iim_dev; + +/*! + * MXC IIM interface - memory map function + * This function maps 4KB IIM registers from IIM base address. + * + * @param file struct file * + * @param vma structure vm_area_struct * + * + * @return Return 0 on success or negative error code on error + */ +static int mxc_iim_mmap(struct file *file, struct vm_area_struct *vma) +{ + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + /* Remap-pfn-range will mark the range VM_IO and VM_RESERVED */ + if (remap_pfn_range(vma, + vma->vm_start, + iim_reg_base >> PAGE_SHIFT, + iim_reg_size, + vma->vm_page_prot)) + return -EAGAIN; + + return 0; +} + +/*! + * MXC IIM interface - open function + * + * @param inode struct inode * + * @param filp struct file * + * + * @return Return 0 on success or negative error code on error + */ +static int mxc_iim_open(struct inode *inode, struct file *filp) +{ + iim_clk = clk_get(NULL, "iim_clk"); + if (IS_ERR(iim_clk)) { + dev_err(iim_dev, "No IIM clock defined\n"); + return -ENODEV; + } + clk_enable(iim_clk); + + return 0; +} + +/*! + * MXC IIM interface - release function + * + * @param inode struct inode * + * @param filp struct file * + * + * @return Return 0 on success or negative error code on error + */ +static int mxc_iim_release(struct inode *inode, struct file *filp) +{ + clk_disable(iim_clk); + clk_put(iim_clk); + return 0; +} + +static const struct file_operations mxc_iim_fops = { + .mmap = mxc_iim_mmap, + .open = mxc_iim_open, + .release = mxc_iim_release, +}; + +static struct miscdevice mxc_iim_miscdev = { + .minor = MISC_DYNAMIC_MINOR, + .name = "mxc_iim", + .fops = &mxc_iim_fops, +}; + +/*! + * This function is called by the driver framework to get iim base/end address + * and register iim misc device. + * + * @param dev The device structure for IIM passed in by the driver + * framework. + * + * @return Returns 0 on success or negative error code on error + */ +static int mxc_iim_probe(struct platform_device *pdev) +{ + struct resource *res; + int ret; + + iim_dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (IS_ERR(res)) { + dev_err(iim_dev, "Unable to get IIM resource\n"); + return -ENODEV; + } + + iim_reg_base = res->start; + iim_reg_end = res->end; + iim_reg_size = iim_reg_end - iim_reg_base + 1; + + ret = misc_register(&mxc_iim_miscdev); + if (ret) + return ret; + + return 0; +} + +static int mxc_iim_remove(struct platform_device *pdev) +{ + misc_deregister(&mxc_iim_miscdev); + return 0; +} + +static struct platform_driver mxc_iim_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "mxc_iim", + }, + .probe = mxc_iim_probe, + .remove = mxc_iim_remove, +}; + +static int __init mxc_iim_dev_init(void) +{ + return platform_driver_register(&mxc_iim_driver); +} + +static void __exit mxc_iim_dev_cleanup(void) +{ + platform_driver_unregister(&mxc_iim_driver); +} + +module_init(mxc_iim_dev_init); +module_exit(mxc_iim_dev_cleanup); + +MODULE_AUTHOR("Manish Lachwani"); +MODULE_DESCRIPTION("MXC IIM driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS_MISCDEV(MISC_DYNAMIC_MINOR); diff -urN linux-2.6.26/drivers/char/mxc_si4702.c linux-2.6.26-lab126/drivers/char/mxc_si4702.c --- linux-2.6.26/drivers/char/mxc_si4702.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/char/mxc_si4702.c 2010-08-10 04:16:25.000000000 -0400 @@ -0,0 +1,1220 @@ +/* + * linux/drivers/char/mxc_si4702.c + * + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SI4702_DEV_NAME "si4702" +#define DEV_MAJOR 0 /* this could be module param */ +#define DEV_MINOR 0 +#define DEV_BASE_MINOR 0 +#define DEV_MINOR_COUNT 256 +#define SI4702_I2C_ADDR 0x10 /* 7bits I2C address */ +#define DELAY_WAIT 0xffff /* loop_counter max value */ +/* register define */ +#define SI4702_DEVICEID 0x00 +#define SI4702_CHIPID 0x01 +#define SI4702_POWERCFG 0x02 +#define SI4702_CHANNEL 0x03 +#define SI4702_SYSCONFIG1 0x04 +#define SI4702_SYSCONFIG2 0x05 +#define SI4702_SYSCONFIG3 0x06 +#define SI4702_TEST1 0x07 +#define SI4702_TEST2 0x08 +#define SI4702_B00TCONFIG 0x09 +#define SI4702_STATUSRSSI 0x0A +#define SI4702_READCHAN 0x0B +#define SI4702_REG_NUM 0x10 +#define SI4702_REG_BYTE (SI4702_REG_NUM * 2) +#define SI4702_DEVICE_ID 0x1242 +#define SI4702_RW_REG_NUM (SI4702_STATUSRSSI - SI4702_POWERCFG) +#define SI4702_RW_OFFSET \ + (SI4702_REG_NUM - SI4702_STATUSRSSI + SI4702_POWERCFG) + +#define SI4702_SPACE_MASK 0x0030 +#define SI4702_SPACE_200K 0x0 +#define SI4702_SPACE_100K 0x10 +#define SI4702_SPACE_50K 0x20 + +#define SI4702_BAND_MASK 0x00c0 +#define SI4702_BAND_LSB 6 + +#define SI4702_SEEKTH_MASK 0xff00 +#define SI4702_SEEKTH_LSB 8 + +#define SI4702_SNR_MASK 0x00f0 +#define SI4702_SNR_LSB 4 + +#define SI4702_CNT_MASK 0x000f +#define SI4702_CNT_LSB 0 + +#define SI4702_VOL_MASK 0x000f +#define SI4702_VOL_LSB 0 + +#define SI4702_CHAN_MASK 0x03ff +#define SI4702_TUNE_BIT 0x8000 +#define SI4702_STC_BIT 0x4000 +#define SI4702_DMUTE_BIT 0x4000 +#define SI4702_SEEKUP_BIT 0x0200 +#define SI4702_SEEK_BIT 0x0100 +#define SI4702_SF_BIT 0x2000 +#define SI4702_ENABLE_BIT 0x0001 +#define SI4702_DISABLE_BIT 0x0040 + +enum { + BAND_USA = 0, + BAND_JAP_W, + BAND_JAP +}; + +struct si4702_info { + int min_band; + int max_band; + int space; + int volume; + int channel; + int mute; +}; + +struct si4702_drvdata { + struct regulator *vio; + struct regulator *vdd; + struct class *radio_class; + struct si4702_info info; + /*by default, dev major is zero, and it's alloc dynamicaly. */ + int major; + int minor; + struct cdev *cdev; + int count; /* open count */ + struct i2c_client *client; + unsigned char reg_rw_buf[SI4702_REG_BYTE]; + struct mxc_fm_platform_data *plat_data; +}; + +static struct si4702_drvdata *si4702_drvdata; + +DEFINE_SPINLOCK(count_lock); + +#ifdef DEBUG +static void si4702_dump_reg(void) +{ + int i, j; + unsigned char *reg_rw_buf; + + if (NULL == si4702_drvdata) + return; + + reg_rw_buf = si4702_drvdata->reg_rw_buf; + + for (i = 0; i < 10; i++) { + j = i * 2 + 12; + pr_debug("reg[%02d] = %04x\n", i, + ((reg_rw_buf[j] << 8) & 0xFF00) + + (reg_rw_buf[j + 1] & 0x00FF)); + } + for (; i < 16; i++) { + j = (i - 10) * 2; + pr_debug("reg[%02d] = %04x\n", i, + ((reg_rw_buf[j] << 8) & 0xFF00) + + (reg_rw_buf[j + 1] & 0x00FF)); + } +} +#else +static void si4702_dump_reg(void) +{ +} +#endif /* DEBUG */ + +/* + *check the si4702 spec for the read/write concequence. + * + *0 2 A F0 A F + *------------------------------- + * buf:0 2 A F + */ +#define REG_to_BUF(reg) (((reg >= 0) && (reg < SI4702_STATUSRSSI))?\ + (reg - SI4702_STATUSRSSI + SI4702_REG_NUM):\ + ((reg >= SI4702_STATUSRSSI) && (reg < SI4702_REG_NUM))?\ + (reg - SI4702_STATUSRSSI) : -1) + +static int si4702_read_reg(const int reg, u16 *value) +{ + int ret, index; + unsigned char *reg_rw_buf; + + if (NULL == si4702_drvdata) + return -1; + + reg_rw_buf = si4702_drvdata->reg_rw_buf; + + index = REG_to_BUF(reg); + + if (-1 == index) + return -1; + + ret = + i2c_master_recv(si4702_drvdata->client, reg_rw_buf, + SI4702_REG_BYTE); + + *value = (reg_rw_buf[index * 2] << 8) & 0xFF00; + *value |= reg_rw_buf[index * 2 + 1] & 0x00FF; + + return ret < 0 ? ret : 0; +} + +static int si4702_write_reg(const int reg, const u16 value) +{ + int index, ret; + unsigned char *reg_rw_buf; + + if (NULL == si4702_drvdata) + return -1; + + reg_rw_buf = si4702_drvdata->reg_rw_buf; + + index = REG_to_BUF(reg); + + if (-1 == index) + return -1; + + reg_rw_buf[index * 2] = (value & 0xFF00) >> 8; + reg_rw_buf[index * 2 + 1] = value & 0x00FF; + + ret = i2c_master_send(si4702_drvdata->client, + ®_rw_buf[SI4702_RW_OFFSET * 2], + (SI4702_STATUSRSSI - SI4702_POWERCFG) * 2); + return ret < 0 ? ret : 0; +} + +static void si4702_gpio_get(void) +{ + if (NULL == si4702_drvdata) + return; + + si4702_drvdata->plat_data->gpio_get(); +} + +static void si4702_gpio_put(void) +{ + if (NULL == si4702_drvdata) + return; + + si4702_drvdata->plat_data->gpio_put(); +} + +static void si4702_reset(void) +{ + if (NULL == si4702_drvdata) + return; + + si4702_drvdata->plat_data->reset(); +} + +static void si4702_clock_en(int flag) +{ + if (NULL == si4702_drvdata) + return; + + si4702_drvdata->plat_data->clock_ctl(flag); +} + +static int si4702_id_detect(struct i2c_client *client) +{ + int ret, index; + unsigned int ID = 0; + unsigned char reg_rw_buf[SI4702_REG_BYTE]; + + si4702_gpio_get(); + si4702_reset(); + si4702_clock_en(1); + + ret = i2c_master_recv(client, (char *)reg_rw_buf, SI4702_REG_BYTE); + + si4702_gpio_put(); + + if (ret < 0) + return ret; + + index = REG_to_BUF(SI4702_DEVICEID); + if (index < 0) + return index; + + ID = (reg_rw_buf[index * 2] << 8) & 0xFF00; + ID |= reg_rw_buf[index * 2 + 1] & 0x00FF; + + return ID; +} + +/* valid args 50/100/200 */ +static int si4702_set_space(int space) +{ + u16 reg; + int ret; + struct si4702_info *info; + + if (NULL == si4702_drvdata) + return -1; + + ret = si4702_read_reg(SI4702_SYSCONFIG2, ®); + if (ret == -1) + return ret; + + reg &= ~SI4702_SPACE_MASK; + switch (space) { + case 50: + reg |= SI4702_SPACE_50K; + break; + case 100: + reg |= SI4702_SPACE_100K; + break; + case 200: + ret |= SI4702_SPACE_200K; + break; + default: + return -1; + } + + ret = si4702_write_reg(SI4702_SYSCONFIG2, reg); + if (ret == -1) + return ret; + + info = &si4702_drvdata->info; + info->space = space; + return 0; +} + +static int si4702_set_band_range(int band) +{ + u16 reg; + int ret, band_min, band_max; + struct si4702_info *info; + + if (NULL == si4702_drvdata) + return -1; + + switch (band) { + case BAND_USA: + band_min = 87500; + band_max = 108000; + break; + case BAND_JAP_W: + band_min = 76000; + band_max = 108000; + break; + case BAND_JAP: + band_min = 76000; + band_max = 90000; + break; + default: + return -1; + } + + ret = si4702_read_reg(SI4702_SYSCONFIG2, ®); + if (ret == -1) + return ret; + + reg = (reg & ~SI4702_BAND_MASK) + | ((band << SI4702_BAND_LSB) & SI4702_BAND_MASK); + ret = si4702_write_reg(SI4702_SYSCONFIG2, reg); + if (ret == -1) + return ret; + + info = &si4702_drvdata->info; + info->min_band = band_min; + info->max_band = band_max; + return 0; +} + +static int si4702_set_seekth(u8 seekth) +{ + u16 reg; + int ret; + + if (NULL == si4702_drvdata) + return -1; + + ret = si4702_read_reg(SI4702_SYSCONFIG2, ®); + if (ret == -1) + return ret; + + reg = + (reg & ~SI4702_SEEKTH_MASK) | ((seekth << SI4702_SEEKTH_LSB) & + SI4702_SEEKTH_MASK); + ret = si4702_write_reg(SI4702_SYSCONFIG2, reg); + if (ret == -1) + return ret; + + return 0; +} + +static int si4702_set_sksnr(u8 sksnr) +{ + u16 reg; + int ret; + + if (NULL == si4702_drvdata) + return -1; + + ret = si4702_read_reg(SI4702_SYSCONFIG3, ®); + if (ret == -1) + return ret; + + reg = + (reg & ~SI4702_SNR_MASK) | ((sksnr << SI4702_SNR_LSB) & + SI4702_SNR_MASK); + ret = si4702_write_reg(SI4702_SYSCONFIG3, reg); + if (ret == -1) + return ret; + + return 0; +} + +static int si4702_set_skcnt(u8 skcnt) +{ + u16 reg; + int ret; + + if (NULL == si4702_drvdata) + return -1; + + ret = si4702_read_reg(SI4702_SYSCONFIG3, ®); + if (ret == -1) + return ret; + + reg = (reg & ~SI4702_CNT_MASK) | (skcnt & SI4702_CNT_MASK); + ret = si4702_write_reg(SI4702_SYSCONFIG3, reg); + if (ret == -1) + return ret; + + return 0; +} + +static int si4702_set_vol(int vol) +{ + u16 reg; + int ret; + struct si4702_info *info; + + if (NULL == si4702_drvdata) + return -1; + + ret = si4702_read_reg(SI4702_SYSCONFIG2, ®); + if (ret == -1) + return ret; + + reg = (reg & ~SI4702_VOL_MASK) | (vol & SI4702_VOL_MASK); + ret = si4702_write_reg(SI4702_SYSCONFIG2, reg); + if (ret == -1) + return ret; + + info = &si4702_drvdata->info; + info->volume = vol; + + return 0; +} + +static u8 si4702_channel_select(u32 freq) +{ + u16 loop_counter = 0; + s16 channel; + u16 si4702_reg_data; + u8 error_ind = 0; + struct i2c_client *client; + struct si4702_info *info; + + if (NULL == si4702_drvdata) + return -1; + + info = &si4702_drvdata->info; + client = si4702_drvdata->client; + + dev_info(&client->dev, "Input frequnce is %d\n", freq); + if (freq < 76000 || freq > 108000) { + dev_err(&client->dev, "Input frequnce is invalid\n"); + return -1; + } + /* convert freq to channel */ + channel = (freq - info->min_band) / info->space; + + si4702_reg_data = SI4702_TUNE_BIT | (channel & SI4702_CHAN_MASK); + /* set channel */ + error_ind = si4702_write_reg(SI4702_CHANNEL, si4702_reg_data); + if (error_ind) { + dev_err(&client->dev, "Failed to set channel\n"); + return -1; + } + dev_info(&client->dev, "Set channel to %d\n", channel); + + /* wait for STC == 1 */ + do { + error_ind = + si4702_read_reg(SI4702_STATUSRSSI, &si4702_reg_data); + + if (error_ind) { + dev_err(&client->dev, "Failed to read setted STC\n"); + return -1; + } + if ((si4702_reg_data & SI4702_STC_BIT) != 0) + break; + } while (++loop_counter < DELAY_WAIT); + + /* check loop_counter */ + if (loop_counter >= DELAY_WAIT) { + dev_err(&client->dev, "Can't wait for STC bit set"); + return -1; + } + dev_info(&client->dev, "loop counter %d\n", loop_counter); + + loop_counter = 0; + /* clear tune bit */ + error_ind = si4702_write_reg(SI4702_CHANNEL, 0); + + if (error_ind) { + dev_err(&client->dev, "Failed to set stop tune\n"); + return -1; + } + + /* wait for STC == 0 */ + do { + error_ind = + si4702_read_reg(SI4702_STATUSRSSI, &si4702_reg_data); + + if (error_ind) { + dev_err(&client->dev, "Failed to set read STC\n"); + return -1; + } + if ((si4702_reg_data & SI4702_STC_BIT) == 0) + break; + } while (++loop_counter < DELAY_WAIT); + + /* check loop_counter */ + if (loop_counter >= DELAY_WAIT) { + dev_err(&client->dev, "Can't wait for STC bit clean"); + return -1; + } + dev_info(&client->dev, "loop counter %d\n", loop_counter); + + /* read RSSI */ + error_ind = si4702_read_reg(SI4702_READCHAN, &si4702_reg_data); + + if (error_ind) { + dev_err(&client->dev, "Failed to read RSSI\n"); + return -1; + } + + channel = si4702_reg_data & SI4702_CHAN_MASK; + dev_info(&client->dev, "seek finish: channel(%d)\n", channel); + + return 0; +} + +static s32 si4702_channel_seek(s16 dir) +{ + u16 loop_counter = 0; + u16 si4702_reg_data, reg_power_cfg; + u8 error_ind = 0; + u32 channel, freq; + struct i2c_client *client; + struct si4702_info *info; + + if (NULL == si4702_drvdata) + return -1; + + info = &si4702_drvdata->info; + client = si4702_drvdata->client; + + error_ind = si4702_read_reg(SI4702_POWERCFG, ®_power_cfg); + + if (info->mute) { + /* check disable mute */ + reg_power_cfg &= ~SI4702_DMUTE_BIT; + } else { + reg_power_cfg |= SI4702_DMUTE_BIT; + } + + if (dir) { + reg_power_cfg |= SI4702_SEEKUP_BIT; + } else { + reg_power_cfg &= ~SI4702_SEEKUP_BIT; + } + /* start seek */ + reg_power_cfg |= SI4702_SEEK_BIT; + error_ind = si4702_write_reg(SI4702_POWERCFG, reg_power_cfg); + + if (error_ind) { + dev_err(&client->dev, "Failed to set seek start bit\n"); + return -1; + } + + /* wait STC == 1 */ + do { + error_ind = + si4702_read_reg(SI4702_STATUSRSSI, &si4702_reg_data); + if (error_ind) { + dev_err(&client->dev, "Failed to read STC bit\n"); + return -1; + } + + if ((si4702_reg_data & SI4702_STC_BIT) != 0) + break; + } while (++loop_counter < DELAY_WAIT); + + /* clear seek bit */ + reg_power_cfg &= ~SI4702_SEEK_BIT; + error_ind = si4702_write_reg(SI4702_POWERCFG, reg_power_cfg); + if (error_ind) { + dev_err(&client->dev, "Failed to stop seek\n"); + return -1; + } + + if (loop_counter >= DELAY_WAIT) { + dev_err(&client->dev, "Can't wait for STC bit set\n"); + return -1; + } + + /* check whether SF==1 (seek failed bit) */ + if ((si4702_reg_data & SI4702_SF_BIT) != 0) { + dev_err(&client->dev, "Failed to seek any channel\n"); + return -1; + } + + loop_counter = 0; + /* wait STC == 0 */ + do { + error_ind = + si4702_read_reg(SI4702_STATUSRSSI, &si4702_reg_data); + + if (error_ind) { + dev_err(&client->dev, + "Failed to wait STC bit to clear\n"); + return -1; + } + if ((si4702_reg_data & SI4702_STC_BIT) == 0) + break; + } while (++loop_counter < DELAY_WAIT); + + /* check loop_counter */ + if (loop_counter >= DELAY_WAIT) { + dev_err(&client->dev, "Can't wait for STC bit clean"); + return -1; + } + + error_ind = si4702_read_reg(SI4702_READCHAN, &si4702_reg_data); + + if (error_ind) { + dev_err(&client->dev, "I2C simulate failed\n"); + return -1; + } + + channel = si4702_reg_data & SI4702_CHAN_MASK; + freq = channel * info->space + info->min_band; + dev_err(&client->dev, + "seek finish: channel(%d), freq(%dKHz)\n", channel, freq); + + return 0; +} + +static int si4702_startup(void) +{ + u16 magic = 0, id; + struct i2c_client *client; + struct mxc_fm_platform_data *data; + + if (NULL == si4702_drvdata) + return -1; + + if (si4702_drvdata->vio) + regulator_enable(si4702_drvdata->vio); + if (si4702_drvdata->vdd) + regulator_enable(si4702_drvdata->vdd); + data = si4702_drvdata->plat_data; + client = si4702_drvdata->client; + + /* read prior to write, otherwise write op will fail */ + si4702_read_reg(SI4702_DEVICEID, &id); + dev_err(&client->dev, "si4702: DEVICEID: 0x%x\n", id); + + si4702_clock_en(1); + msleep(100); + + /* disable mute, stereo, seek down, powerup */ + si4702_write_reg(SI4702_POWERCFG, SI4702_DMUTE_BIT | SI4702_ENABLE_BIT); + msleep(500); + si4702_read_reg(SI4702_TEST1, &magic); + if (magic != 0x3C04) + dev_err(&client->dev, "magic number 0x%x.\n", magic); + /* close tune, set channel to 0 */ + si4702_write_reg(SI4702_CHANNEL, 0); + /* disable interrupt, disable GPIO */ + si4702_write_reg(SI4702_SYSCONFIG1, 0); + /* set volume to middle level */ + si4702_set_vol(0xf); + + si4702_set_space(data->space); + si4702_set_band_range(data->band); + si4702_set_seekth(data->seekth); + si4702_set_skcnt(data->skcnt); + si4702_set_sksnr(data->sksnr); + + return 0; +} + +static void si4702_shutdown(void) +{ + if (NULL == si4702_drvdata) + return; + + si4702_write_reg(SI4702_POWERCFG, SI4702_DMUTE_BIT | + SI4702_ENABLE_BIT | SI4702_DISABLE_BIT); + msleep(100); + si4702_clock_en(0); + + if (si4702_drvdata->vdd) + regulator_disable(si4702_drvdata->vdd); + if (si4702_drvdata->vio) + regulator_disable(si4702_drvdata->vio); +} + +enum { + FM_STARTUP = 0, + FM_SHUTDOWN, + FM_RESET, + FM_VOLUP, + FM_VOLDOWN, + FM_SEEK_UP, + FM_SEEK_DOWN, + FM_MUTEON, + FM_MUTEDIS, + FM_SEL, + FM_SEEKTH, + FM_DL, + FM_CTL_MAX +}; + +static const char *const fm_control[FM_CTL_MAX] = { + [FM_STARTUP] = "start", + [FM_SHUTDOWN] = "halt", + [FM_RESET] = "reset", + [FM_VOLUP] = "volup", + [FM_VOLDOWN] = "voldown", + [FM_SEEK_UP] = "seeku", + [FM_SEEK_DOWN] = "seekd", + [FM_MUTEON] = "mute", + [FM_MUTEDIS] = "muted", + [FM_SEL] = "select", + [FM_SEEKTH] = "seekth", + [FM_DL] = "delay" +}; + +static int cmd(unsigned int index, int arg) +{ + struct i2c_client *client; + struct mxc_fm_platform_data *plat_data; + + if (NULL == si4702_drvdata) + return -1; + + client = si4702_drvdata->client; + plat_data = si4702_drvdata->plat_data; + + switch (index) { + case FM_SHUTDOWN: + dev_err(&client->dev, "FM_SHUTDOWN\n"); + si4702_shutdown(); + break; + case FM_STARTUP: + dev_err(&client->dev, "FM_STARTUP\n"); + si4702_reset(); + si4702_startup(); + break; + case FM_RESET: + dev_err(&client->dev, "FM_RESET\n"); + si4702_reset(); + break; + case FM_SEEK_DOWN: + dev_err(&client->dev, "SEEK DOWN\n"); + si4702_channel_seek(0); + break; + case FM_SEEK_UP: + dev_err(&client->dev, "SEEK UP\n"); + si4702_channel_seek(1); + break; + case FM_SEL: + dev_err(&client->dev, "select %d\n", arg * 100); + si4702_channel_select(arg * 100); + break; + case FM_SEEKTH: + dev_err(&client->dev, "seekth = %d\n", arg); + si4702_set_seekth(arg); + break; + case FM_DL: + dev_err(&client->dev, "delay = %d\n", arg); + break; + default: + dev_err(&client->dev, "error command\n"); + break; + } + return 0; +} + +static ssize_t si4702_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct si4702_drvdata *drv_data = dev_get_drvdata(dev); + u16 device_id; + + dev_err(&(drv_data->client->dev), "si4702 show\n"); + si4702_read_reg(SI4702_DEVICEID, &device_id); + pr_info("device id %x\n", device_id); + si4702_dump_reg(); + return 0; +} + +static ssize_t si4702_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + int state = 0; + const char *const *s; + char *p = NULL; + int error; + int len, arg = 0; + struct si4702_drvdata *drv_data = dev_get_drvdata(dev); + struct i2c_client *client = drv_data->client; + + dev_err(&client->dev, "si4702 store %d\n", count); + + p = memchr(buf, ' ', count); + if (p) { + len = p - buf; + *p = '\0'; + } else + len = count; + + len -= 1; + dev_err(&client->dev, "cmd %s\n", buf); + + for (s = &fm_control[state]; state < FM_CTL_MAX; s++, state++) { + if (*s && !strncmp(buf, *s, len)) { + break; + } + } + if (state < FM_CTL_MAX && *s) { + if (p) + arg = simple_strtoul(p + 1, NULL, 0); + dev_err(&client->dev, "arg = %d\n", arg); + error = cmd(state, arg); + } else { + dev_err(&client->dev, "error cmd\n"); + error = -EINVAL; + } + + return error ? error : count; +} + +static int ioctl_si4702(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + void __user *argp = (void __user *)arg; + int mute = 0; + u16 data; + int error; + u8 volume; + unsigned int freq; + int dir; + struct i2c_client *client; + struct si4702_info *info; + + if (NULL == si4702_drvdata) + return -1; + + info = &si4702_drvdata->info; + client = si4702_drvdata->client; + + dev_err(&client->dev, "ioctl, cmd: 0x%x, arg: 0x%lx\n", cmd, arg); + + switch (cmd) { + case SI4702_SETVOLUME: + /* get volume from user */ + if (copy_from_user(&volume, argp, sizeof(u8))) { + + dev_err(&client->dev, + "ioctl, copy volume value from user failed\n"); + return -EFAULT; + } + dev_err(&client->dev, "volume %d\n", volume); + /* refill the register value */ + volume &= 0x0f; + if (info->mute) + error = si4702_write_reg(SI4702_POWERCFG, 0x0001); + else + error = si4702_write_reg(SI4702_POWERCFG, 0x4001); + + error = si4702_write_reg(SI4702_CHANNEL, 0); + error = si4702_write_reg(SI4702_SYSCONFIG1, 0); + error = si4702_write_reg(SI4702_SYSCONFIG2, 0x0f10 | volume); + if (error) { + dev_err(&client->dev, "ioctl, set volume failed\n"); + return -EFAULT; + } + /* renew the device info */ + info->volume = volume; + + break; + case SI4702_GETVOLUME: + /* just copy volume value to user */ + if (copy_to_user(argp, &(info->volume), sizeof(unsigned int))) { + dev_err(&client->dev, "ioctl, copy to user failed\n"); + return -EFAULT; + } + break; + case SI4702_MUTEON: + mute = 1; + case SI4702_MUTEOFF: + if (mute) { + /* enable mute */ + si4702_read_reg(SI4702_POWERCFG, &data); + data &= 0x00FF; + error = si4702_write_reg(SI4702_POWERCFG, data); + } else { + si4702_read_reg(SI4702_POWERCFG, &data); + data &= 0x00FF; + data |= 0x4000; + error = si4702_write_reg(SI4702_POWERCFG, data); + } + if (error) { + dev_err(&client->dev, "ioctl, set mute failed\n"); + return -EFAULT; + } + break; + case SI4702_SELECT: + if (copy_from_user(&freq, argp, sizeof(unsigned int))) { + + dev_err(&client->dev, + "ioctl, copy frequence from user failed\n"); + return -EFAULT; + } + /* check frequence */ + if (freq > info->max_band || freq < info->min_band) { + dev_err(&client->dev, + "the frequence select is out of band\n"); + return -EINVAL; + } + if (si4702_channel_select(freq)) { + dev_err(&client->dev, + "ioctl, failed to select channel\n"); + return -EFAULT; + } + break; + case SI4702_SEEK: + if (copy_from_user(&dir, argp, sizeof(int))) { + + dev_err(&client->dev, "ioctl, copy from user failed\n"); + return -EFAULT; + } + /* get seeked channel */ + dir = si4702_channel_seek(dir); + if (dir == -1) { + return -EAGAIN; + } else if (dir == -2) { + return -EFAULT; + } + if (copy_to_user(argp, &dir, sizeof(int))) { + + dev_err(&client->dev, + "ioctl, copy seek frequnce to user failed\n"); + return -EFAULT; + } + break; + default: + dev_err(&client->dev, "SI4702: Invalid ioctl command\n"); + return -EINVAL; + + } + return 0; +} + +static int open_si4702(struct inode *inode, struct file *file) +{ + struct i2c_client *client; + + if (NULL == si4702_drvdata) + return -1; + + client = si4702_drvdata->client; + + spin_lock(&count_lock); + if (si4702_drvdata->count != 0) { + dev_err(&client->dev, "device has been open already\n"); + spin_unlock(&count_lock); + return -EBUSY; + } + si4702_drvdata->count++; + spin_unlock(&count_lock); + + /* request and active GPIO */ + si4702_gpio_get(); + /* reset the si4702 from it's reset pin */ + si4702_reset(); + + /* startup si4702 */ + if (si4702_startup()) { + spin_lock(&count_lock); + si4702_drvdata->count--; + spin_unlock(&count_lock); + return -ENODEV; + } + + return 0; +} + +static int release_si4702(struct inode *inode, struct file *file) +{ + struct i2c_client *client; + + if (NULL == si4702_drvdata) + return -1; + + client = si4702_drvdata->client; + + dev_err(&client->dev, "release\n"); + /* software shutdown */ + si4702_shutdown(); + /* inactive, free GPIO, cut power */ + si4702_gpio_put(); + + spin_lock(&count_lock); + si4702_drvdata->count--; + spin_unlock(&count_lock); + + return 0; +} + +static int si4702_suspend(struct i2c_client *client, pm_message_t state) +{ + return 0; +} + +static int si4702_resume(struct i2c_client *client) +{ + return 0; +} + +static struct device_attribute si4702_dev_attr = { + .attr = { + .name = "si4702_ctl", + .mode = S_IRUSR | S_IWUSR, + }, + .show = si4702_show, + .store = si4702_store, +}; + +static struct file_operations si4702_fops = { + .owner = THIS_MODULE, + .open = open_si4702, + .release = release_si4702, + .ioctl = ioctl_si4702, +}; + +static int __devinit si4702_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret = 0; + struct mxc_fm_platform_data *plat_data; + struct si4702_drvdata *drv_data; + struct device *dev; + + dev_info(&client->dev, "si4702 device probe process start.\n"); + + plat_data = (struct mxc_fm_platform_data *)client->dev.platform_data; + if (plat_data == NULL) { + dev_err(&client->dev, "lack of platform data!\n"); + return -ENODEV; + } + + drv_data = kmalloc(sizeof(struct si4702_drvdata), GFP_KERNEL); + if (drv_data == NULL) { + dev_err(&client->dev, "lack of kernel memory!\n"); + return -ENOMEM; + } + memset(drv_data, 0, sizeof(struct si4702_drvdata)); + drv_data->plat_data = plat_data; + drv_data->major = DEV_MAJOR; + drv_data->minor = DEV_MINOR; + drv_data->count = 0; + + /*enable power supply */ + if (plat_data->reg_vio != NULL) { + drv_data->vio = regulator_get(&client->dev, plat_data->reg_vio); + if (drv_data->vio == ERR_PTR(-ENOENT)) + goto free_drv_data; + regulator_enable(drv_data->vio); + } + + /* here, we assume that vio and vdd are not the same */ + if (plat_data->reg_vdd != NULL) { + drv_data->vdd = regulator_get(&client->dev, plat_data->reg_vdd); + if (drv_data->vdd == ERR_PTR(-ENOENT)) + goto disable_vio; + regulator_enable(drv_data->vdd); + } + + /*attach client and check device id */ + if (SI4702_DEVICE_ID != si4702_id_detect(client)) { + dev_err(&client->dev, "id wrong.\n"); + goto disable_vdd; + } + dev_info(&client->dev, "chip id %x detect.\n", SI4702_DEVICE_ID); + drv_data->client = client; + + /*user interface begain */ + /*create device file in sysfs as a user interface, + * also for debug support */ + ret = device_create_file(&client->dev, &si4702_dev_attr); + if (ret) { + dev_err(&client->dev, "create device file failed!\n"); + goto gpio_put; /* shall i use some meanful error code? */ + } + + /*create a char dev for application code access */ + if (drv_data->major) { + ret = register_chrdev(drv_data->major, "si4702", &si4702_fops);; + } else { + ret = register_chrdev(0, "si4702", &si4702_fops); + } + + if (drv_data->major == 0) + drv_data->major = ret; + + /* create class and device for udev information */ + drv_data->radio_class = class_create(THIS_MODULE, "radio"); + if (IS_ERR(drv_data->radio_class)) { + dev_err(&client->dev, "SI4702: failed to create radio class\n"); + goto char_dev_remove; + } + + dev = device_create(drv_data->radio_class, NULL, + MKDEV(drv_data->major, drv_data->minor), "si4702"); + if (IS_ERR(dev)) { + dev_err(&client->dev, + "SI4702: failed to create radio class device\n"); + goto class_remove; + } + /*User interface end */ + dev_set_drvdata(&client->dev, drv_data); + si4702_drvdata = drv_data; + + si4702_gpio_get(); + dev_info(&client->dev, "si4702 device probe successfully.\n"); + si4702_shutdown(); + + return 0; + +class_remove: + class_destroy(drv_data->radio_class); +char_dev_remove: + unregister_chrdev(drv_data->major, "si4702"); + device_remove_file(&client->dev, &si4702_dev_attr); +gpio_put: + si4702_gpio_put(); +disable_vdd: + if (plat_data->reg_vdd) { + regulator_disable(drv_data->vdd); + regulator_put(drv_data->vdd, &client->dev); + } +disable_vio: + if (plat_data->reg_vio) { + regulator_disable(drv_data->vio); + regulator_put(drv_data->vio, &client->dev); + } + +free_drv_data: + kfree(drv_data); + + return -ENODEV; +} + +static int __devexit si4702_remove(struct i2c_client *client) +{ + struct mxc_fm_platform_data *plat_data; + struct si4702_drvdata *drv_data = dev_get_drvdata(&client->dev); + + plat_data = (struct mxc_fm_platform_data *)client->dev.platform_data; + + device_destroy(drv_data->radio_class, MKDEV(drv_data->major, 0)); + class_destroy(drv_data->radio_class); + + unregister_chrdev(drv_data->major, "si4702"); + device_remove_file(&client->dev, &si4702_dev_attr); + si4702_gpio_put(); + + if (plat_data->reg_vdd) + regulator_put(drv_data->vdd, &client->dev); + + if (plat_data->reg_vio) + regulator_put(drv_data->vio, &client->dev); + + kfree(si4702_drvdata); + si4702_drvdata = NULL; + + return 0; +} + +static const struct i2c_device_id si4702_id[] = { + {"si4702", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, si4702_id); + +static struct i2c_driver i2c_si4702_driver = { + .driver = { + .name = "si4702", + }, + .probe = si4702_probe, + .remove = si4702_remove, + .suspend = si4702_suspend, + .resume = si4702_resume, + .id_table = si4702_id, +}; + +static int __init init_si4702(void) +{ + /*add to i2c driver */ + pr_info("add si4702 i2c driver\n"); + return i2c_add_driver(&i2c_si4702_driver); +} + +static void __exit exit_si4702(void) +{ + i2c_del_driver(&i2c_si4702_driver); +} + +module_init(init_si4702); +module_exit(exit_si4702); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("SI4702 FM driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/char/random.c linux-2.6.26-lab126/drivers/char/random.c --- linux-2.6.26/drivers/char/random.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/char/random.c 2010-08-10 04:16:25.000000000 -0400 @@ -581,8 +581,11 @@ preempt_disable(); /* if over the trickle threshold, use only 1 in 4096 samples */ if (input_pool.entropy_count > trickle_thresh && - (__get_cpu_var(trickle_count)++ & 0xfff)) - goto out; + (__get_cpu_var(trickle_count)++ & 0xfff)) { + preempt_enable(); + return; + } + preempt_enable(); sample.jiffies = jiffies; sample.cycles = get_cycles(); @@ -624,8 +627,6 @@ credit_entropy_bits(&input_pool, min_t(int, fls(delta>>1), 11)); } -out: - preempt_enable(); } void add_input_randomness(unsigned int type, unsigned int code, diff -urN linux-2.6.26/drivers/char/rmem.c linux-2.6.26-lab126/drivers/char/rmem.c --- linux-2.6.26/drivers/char/rmem.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/char/rmem.c 2010-08-10 04:16:25.000000000 -0400 @@ -0,0 +1,135 @@ +/* + * Rmem - REALLY simple memory mapping demonstration. + * + * Copyright (C) 2005 by Theodore Ts'o + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int rmem_major = 0; +module_param(rmem_major, int, 0444); + +static struct class *rmem_class; + +MODULE_AUTHOR("Theodore Ts'o"); +MODULE_LICENSE("GPL"); + +unsigned long rmem_vma_nopage(struct vm_area_struct *vma, + unsigned long address) +{ + struct page *pageptr; + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; + unsigned long physaddr = address - vma->vm_start + offset; + unsigned long pageframe = physaddr >> PAGE_SHIFT; + + if (!pfn_valid(pageframe)) + return NOPFN_SIGBUS; + pageptr = pfn_to_page(pageframe); + get_page(pageptr); + + return pageframe; +} + +static struct vm_operations_struct rmem_nopage_vm_ops = { + .nopfn = rmem_vma_nopage, +}; + +static int rmem_nopage_mmap(struct file *filp, struct vm_area_struct *vma) +{ + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; + + if (offset >= __pa(high_memory) || (filp->f_flags & O_SYNC)) + vma->vm_flags |= VM_IO; + vma->vm_flags |= VM_RESERVED; + vma->vm_ops = &rmem_nopage_vm_ops; +#ifdef TAINT_USER + add_taint(TAINT_USER); +#endif + return 0; +} + +static struct file_operations rmem_nopage_ops = { + .owner = THIS_MODULE, + .mmap = rmem_nopage_mmap, +}; + +static struct cdev rmem_cdev = { + .kobj = {.name = "rmem", }, + .owner = THIS_MODULE, +}; + +static int __init rmem_init(void) +{ + int result; + dev_t dev = MKDEV(rmem_major, 0); + + /* Figure out our device number. */ + if (rmem_major) + result = register_chrdev_region(dev, 1, "rmem"); + else { + result = alloc_chrdev_region(&dev, 0, 1, "rmem"); + rmem_major = MAJOR(dev); + } + if (result < 0) { + printk(KERN_WARNING "rmem: unable to get major %d\n", rmem_major); + return result; + } + if (rmem_major == 0) + rmem_major = result; + + cdev_init(&rmem_cdev, &rmem_nopage_ops); + result = cdev_add(&rmem_cdev, dev, 1); + if (result) { + printk (KERN_NOTICE "Error %d adding /dev/rmem", result); + kobject_put(&rmem_cdev.kobj); + unregister_chrdev_region(dev, 1); + return 1; + } + + rmem_class = class_create(THIS_MODULE, "rmem"); + device_create(rmem_class, NULL, dev, "rmem"); + + return 0; +} + + +static void __exit rmem_cleanup(void) +{ + dev_t dev = MKDEV(rmem_major, 0); + + cdev_del(&rmem_cdev); + unregister_chrdev_region(MKDEV(rmem_major, 0), 1); + device_destroy(rmem_class, dev); +} + + +module_init(rmem_init); +module_exit(rmem_cleanup); diff -urN linux-2.6.26/drivers/char/rtc.c linux-2.6.26-lab126/drivers/char/rtc.c --- linux-2.6.26/drivers/char/rtc.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/char/rtc.c 2010-08-10 04:16:25.000000000 -0400 @@ -95,6 +95,32 @@ static int rtc_irq = PCI_IRQ_NONE; #endif +#ifdef CONFIG_MIPS +# include +#endif + +#ifdef CONFIG_RTC_HISTOGRAM + +static cycles_t last_interrupt_time; + +#include + +#define CPU_MHZ (cpu_khz / 1000) + +#define HISTSIZE 10000 +static int histogram[HISTSIZE]; + +static int rtc_state; + +enum rtc_states { + S_STARTUP, /* First round - let the application start */ + S_IDLE, /* Waiting for an interrupt */ + S_WAITING_FOR_READ, /* Signal delivered. waiting for rtc_read() */ + S_READ_MISSED, /* Signal delivered, read() deadline missed */ +}; + +#endif + #ifdef CONFIG_HPET_RTC_IRQ #undef RTC_IRQ #endif @@ -225,7 +251,146 @@ return uip; } +#ifndef RTC_IRQ +# undef CONFIG_RTC_HISTOGRAM +#endif + +static inline void rtc_open_event(void) +{ +#ifdef CONFIG_RTC_HISTOGRAM + int i; + + last_interrupt_time = 0; + rtc_state = S_STARTUP; + rtc_irq_data = 0; + + for (i = 0; i < HISTSIZE; i++) + histogram[i] = 0; +#endif +} + +static inline void rtc_wake_event(void) +{ +#ifndef CONFIG_RTC_HISTOGRAM + kill_fasync (&rtc_async_queue, SIGIO, POLL_IN); +#else + if (!(rtc_status & RTC_IS_OPEN)) + return; + + switch (rtc_state) { + /* Startup */ + case S_STARTUP: + kill_fasync (&rtc_async_queue, SIGIO, POLL_IN); + break; + /* Waiting for an interrupt */ + case S_IDLE: + kill_fasync (&rtc_async_queue, SIGIO, POLL_IN); + last_interrupt_time = get_cycles(); + rtc_state = S_WAITING_FOR_READ; + break; + + /* Signal has been delivered. waiting for rtc_read() */ + case S_WAITING_FOR_READ: + /* + * Well foo. The usermode application didn't + * schedule and read in time. + */ + last_interrupt_time = get_cycles(); + rtc_state = S_READ_MISSED; + printk("Read missed before next interrupt\n"); + break; + /* Signal has been delivered, read() deadline was missed */ + case S_READ_MISSED: + /* + * Not much we can do here. We're waiting for the usermode + * application to read the rtc + */ + last_interrupt_time = get_cycles(); + break; + } +#endif +} + +static inline void rtc_read_event(void) +{ +#ifdef CONFIG_RTC_HISTOGRAM + cycles_t now = get_cycles(); + + switch (rtc_state) { + /* Startup */ + case S_STARTUP: + rtc_state = S_IDLE; + break; + + /* Waiting for an interrupt */ + case S_IDLE: + printk("bug in rtc_read(): called in state S_IDLE!\n"); + break; + case S_WAITING_FOR_READ: /* + * Signal has been delivered. + * waiting for rtc_read() + */ + /* + * Well done + */ + case S_READ_MISSED: /* + * Signal has been delivered, read() + * deadline was missed + */ + /* + * So, you finally got here. + */ + if (!last_interrupt_time) + printk("bug in rtc_read(): last_interrupt_time = 0\n"); + rtc_state = S_IDLE; + { + cycles_t latency = now - last_interrupt_time; + unsigned long delta; /* Microseconds */ + + delta = latency; + delta /= CPU_MHZ; + + if (delta > 1000 * 1000) { + printk("rtc: eek\n"); + } else { + unsigned long slot = delta; + if (slot >= HISTSIZE) + slot = HISTSIZE - 1; + histogram[slot]++; + if (delta > 2000) + printk("wow! That was a " + "%ld millisec bump\n", + delta / 1000); + } + } + rtc_state = S_IDLE; + break; + } +#endif +} + +static inline void rtc_close_event(void) +{ +#ifdef CONFIG_RTC_HISTOGRAM + int i = 0; + unsigned long total = 0; + + for (i = 0; i < HISTSIZE; i++) + total += histogram[i]; + if (!total) + return; + + printk("\nrtc latency histogram of {%s/%d, %lu samples}:\n", + current->comm, current->pid, total); + for (i = 0; i < HISTSIZE; i++) { + if (histogram[i]) + printk("%d %d\n", i, histogram[i]); + } +#endif +} + #ifdef RTC_IRQ + /* * A very tiny interrupt handler. It runs with IRQF_DISABLED set, * but there is possibility of conflicting with the set_rtc_mmss() @@ -269,9 +434,9 @@ if (rtc_callback) rtc_callback->func(rtc_callback->private_data); spin_unlock(&rtc_task_lock); - wake_up_interruptible(&rtc_wait); - kill_fasync(&rtc_async_queue, SIGIO, POLL_IN); + rtc_wake_event(); + wake_up_interruptible(&rtc_wait); return IRQ_HANDLED; } @@ -381,6 +546,8 @@ schedule(); } while (1); + rtc_read_event(); + if (count == sizeof(unsigned int)) { retval = put_user(data, (unsigned int __user *)buf) ?: sizeof(int); @@ -628,6 +795,11 @@ save_freq_select = CMOS_READ(RTC_FREQ_SELECT); CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT); + /* + * Make CMOS date writes nonpreemptible even on PREEMPT_RT. + * There's a limit to everything! =B-) + */ + preempt_disable(); #ifdef CONFIG_MACH_DECSTATION CMOS_WRITE(real_yrs, RTC_DEC_YEAR); #endif @@ -637,6 +809,7 @@ CMOS_WRITE(hrs, RTC_HOURS); CMOS_WRITE(min, RTC_MINUTES); CMOS_WRITE(sec, RTC_SECONDS); + preempt_enable(); CMOS_WRITE(save_control, RTC_CONTROL); CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); @@ -739,6 +912,7 @@ if (rtc_status & RTC_IS_OPEN) goto out_busy; + rtc_open_event(); rtc_status |= RTC_IS_OPEN; rtc_irq_data = 0; @@ -792,6 +966,7 @@ rtc_irq_data = 0; rtc_status &= ~RTC_IS_OPEN; spin_unlock_irq(&rtc_lock); + rtc_close_event(); return 0; } @@ -1199,10 +1374,12 @@ spin_unlock_irq(&rtc_lock); +#ifndef CONFIG_PREEMPT_RT if (printk_ratelimit()) { printk(KERN_WARNING "rtc: lost some interrupts at %ldHz.\n", freq); } +#endif /* Now we have new data */ wake_up_interruptible(&rtc_wait); diff -urN linux-2.6.26/drivers/char/sysrq.c linux-2.6.26-lab126/drivers/char/sysrq.c --- linux-2.6.26/drivers/char/sysrq.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/char/sysrq.c 2010-08-10 04:16:25.000000000 -0400 @@ -251,6 +251,22 @@ .enable_mask = SYSRQ_ENABLE_DUMP, }; +#if defined(__i386__) || defined(__x86_64__) + +static void sysrq_handle_showallregs(int key, struct tty_struct *tty) +{ + nmi_show_all_regs(); +} + +static struct sysrq_key_op sysrq_showallregs_op = { + .handler = sysrq_handle_showallregs, + .help_msg = "showalLcpupc", + .action_msg = "Show Regs On All CPUs", +}; +#else +#define sysrq_showallregs_op (*(struct sysrq_key_op *)0) +#endif + static void sysrq_handle_showstate(int key, struct tty_struct *tty) { show_state(); @@ -404,7 +420,7 @@ NULL, /* x */ /* y: May be registered on sparc64 for global register dump */ NULL, /* y */ - NULL /* z */ + &sysrq_showallregs_op, /* l */ }; /* key2index calculation, -1 on invalid index */ diff -urN linux-2.6.26/drivers/char/tty_io.c linux-2.6.26-lab126/drivers/char/tty_io.c --- linux-2.6.26/drivers/char/tty_io.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/char/tty_io.c 2010-08-10 04:16:25.000000000 -0400 @@ -240,14 +240,13 @@ static int check_tty_count(struct tty_struct *tty, const char *routine) { #ifdef CHECK_TTY_COUNT - struct list_head *p; + struct file *filp; int count = 0; - file_list_lock(); - list_for_each(p, &tty->tty_files) { + percpu_list_fold(&tty->tty_files); + lock_list_for_each_entry(filp, percpu_list_head(&tty->tty_files), f_u.fu_llist) count++; - } - file_list_unlock(); + if (tty->driver->type == TTY_DRIVER_TYPE_PTY && tty->driver->subtype == PTY_TYPE_SLAVE && tty->link && tty->link->count) @@ -256,6 +255,7 @@ printk(KERN_WARNING "Warning: dev (%s) tty->count(%d) " "!= #fd's(%d) in %s\n", tty->name, tty->count, count, routine); + dump_stack(); return count; } #endif @@ -1429,9 +1429,8 @@ spin_unlock(&redirect_lock); check_tty_count(tty, "do_tty_hangup"); - file_list_lock(); /* This breaks for file handles being sent over AF_UNIX sockets ? */ - list_for_each_entry(filp, &tty->tty_files, f_u.fu_list) { + lock_list_for_each_entry(filp, percpu_list_head(&tty->tty_files), f_u.fu_llist) { if (filp->f_op->write == redirected_tty_write) cons_filp = filp; if (filp->f_op->write != tty_write) @@ -1440,7 +1439,6 @@ tty_fasync(-1, filp, 0); /* can't block */ filp->f_op = &hung_up_tty_fops; } - file_list_unlock(); /* * FIXME! What are the locking issues here? This may me overdoing * things... This question is especially important now that we've @@ -2338,9 +2336,9 @@ tty->magic = 0; tty->driver->refcount--; - file_list_lock(); - list_del_init(&tty->tty_files); - file_list_unlock(); + percpu_list_fold(&tty->tty_files); + lock_list_del_init(percpu_list_head(&tty->tty_files)); + percpu_list_destroy(&tty->tty_files); free_tty_struct(tty); } @@ -3795,10 +3793,14 @@ tty->buf.tail->commit = tty->buf.tail->used; spin_unlock_irqrestore(&tty->buf.lock, flags); +#ifndef CONFIG_PREEMPT_RT if (tty->low_latency) flush_to_ldisc(&tty->buf.work.work); else schedule_delayed_work(&tty->buf.work, 1); +#else + flush_to_ldisc(&tty->buf.work.work); +#endif } EXPORT_SYMBOL(tty_flip_buffer_push); @@ -3833,7 +3835,7 @@ mutex_init(&tty->atomic_write_lock); spin_lock_init(&tty->read_lock); spin_lock_init(&tty->ctrl_lock); - INIT_LIST_HEAD(&tty->tty_files); + percpu_list_init(&tty->tty_files); INIT_WORK(&tty->SAK_work, do_SAK_work); } diff -urN linux-2.6.26/drivers/char/vt.c linux-2.6.26-lab126/drivers/char/vt.c --- linux-2.6.26/drivers/char/vt.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/char/vt.c 2010-08-10 04:16:24.000000000 -0400 @@ -2516,7 +2516,7 @@ .write = vt_console_print, .device = vt_console_device, .unblank = unblank_screen, - .flags = CON_PRINTBUFFER, + .flags = CON_PRINTBUFFER | CON_ATOMIC, .index = -1, }; #endif diff -urN linux-2.6.26/drivers/clocksource/acpi_pm.c linux-2.6.26-lab126/drivers/clocksource/acpi_pm.c --- linux-2.6.26/drivers/clocksource/acpi_pm.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/clocksource/acpi_pm.c 2010-08-10 04:16:19.000000000 -0400 @@ -215,3 +215,22 @@ * but we still need to load before device_initcall */ fs_initcall(init_acpi_pm_clocksource); + +/* + * Allow an override of the IOPort. Stupid BIOSes do not tell us about + * the PMTimer, but we might know where it is. + */ +static int __init parse_pmtmr(char *arg) +{ + unsigned long base; + char *e; + + base = simple_strtoul(arg, &e, 16); + + printk(KERN_INFO "PMTMR IOPort override: 0x%04lx -> 0x%04lx\n", + (unsigned long) pmtmr_ioport, base); + pmtmr_ioport = base; + + return 0; +} +__setup("pmtmr=", parse_pmtmr); diff -urN linux-2.6.26/drivers/cpufreq/cpufreq.c linux-2.6.26-lab126/drivers/cpufreq/cpufreq.c --- linux-2.6.26/drivers/cpufreq/cpufreq.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/cpufreq/cpufreq.c 2010-08-10 04:15:46.000000000 -0400 @@ -455,6 +455,7 @@ show_one(cpuinfo_min_freq, cpuinfo.min_freq); show_one(cpuinfo_max_freq, cpuinfo.max_freq); +show_one(cpuinfo_transition_latency, cpuinfo.transition_latency); show_one(scaling_min_freq, min); show_one(scaling_max_freq, max); show_one(scaling_cur_freq, cur); @@ -660,6 +661,7 @@ define_one_ro0400(cpuinfo_cur_freq); define_one_ro(cpuinfo_min_freq); define_one_ro(cpuinfo_max_freq); +define_one_ro(cpuinfo_transition_latency); define_one_ro(scaling_available_governors); define_one_ro(scaling_driver); define_one_ro(scaling_cur_freq); @@ -673,6 +675,7 @@ static struct attribute *default_attrs[] = { &cpuinfo_min_freq.attr, &cpuinfo_max_freq.attr, + &cpuinfo_transition_latency.attr, &scaling_min_freq.attr, &scaling_max_freq.attr, &affected_cpus.attr, diff -urN linux-2.6.26/drivers/cpufreq/cpufreq_ondemand.c linux-2.6.26-lab126/drivers/cpufreq/cpufreq_ondemand.c --- linux-2.6.26/drivers/cpufreq/cpufreq_ondemand.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/cpufreq/cpufreq_ondemand.c 2010-08-10 04:15:46.000000000 -0400 @@ -89,7 +89,7 @@ unsigned int ignore_nice; unsigned int powersave_bias; } dbs_tuners_ins = { - .up_threshold = DEF_FREQUENCY_UP_THRESHOLD, + .up_threshold = MIN_FREQUENCY_UP_THRESHOLD, .ignore_nice = 0, .powersave_bias = 0, }; @@ -245,7 +245,6 @@ return -EINVAL; } - dbs_tuners_ins.up_threshold = input; mutex_unlock(&dbs_mutex); return count; @@ -547,6 +546,7 @@ if (def_sampling_rate < MIN_STAT_SAMPLING_RATE) def_sampling_rate = MIN_STAT_SAMPLING_RATE; + def_sampling_rate = MIN_SAMPLING_RATE; dbs_tuners_ins.sampling_rate = def_sampling_rate; } dbs_timer_init(this_dbs_info); diff -urN linux-2.6.26/drivers/dma/ioat_dma.c linux-2.6.26-lab126/drivers/dma/ioat_dma.c --- linux-2.6.26/drivers/dma/ioat_dma.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/dma/ioat_dma.c 2010-08-10 04:16:18.000000000 -0400 @@ -283,7 +283,7 @@ /* write address into NextDescriptor field of last desc in chain */ to_ioat_desc(ioat_chan->used_desc.prev)->hw->next = first->async_tx.phys; - __list_splice(&new_chain, ioat_chan->used_desc.prev); + list_splice_tail(&new_chain, &ioat_chan->used_desc); ioat_chan->dmacount += desc_count; ioat_chan->pending += desc_count; diff -urN linux-2.6.26/drivers/eisa/.gitignore linux-2.6.26-lab126/drivers/eisa/.gitignore --- linux-2.6.26/drivers/eisa/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/eisa/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1 +0,0 @@ -devlist.h diff -urN linux-2.6.26/drivers/hwmon/Kconfig linux-2.6.26-lab126/drivers/hwmon/Kconfig --- linux-2.6.26/drivers/hwmon/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/hwmon/Kconfig 2010-08-10 04:17:04.000000000 -0400 @@ -808,4 +808,14 @@ a problem with I2C support and want to see more of what is going on. +config MXC_MMA7450 + tristate "MMA7450 device driver" + depends on MACH_MX31_3DS + default n + +config SENSORS_ISL29003 + tristate "ISL29003 Light Sensor" + depends on MACH_MX37_3DS || MACH_MX51_3DS + default y + endif # HWMON diff -urN linux-2.6.26/drivers/hwmon/Makefile linux-2.6.26-lab126/drivers/hwmon/Makefile --- linux-2.6.26/drivers/hwmon/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/hwmon/Makefile 2010-08-10 04:17:04.000000000 -0400 @@ -71,7 +71,9 @@ obj-$(CONFIG_SENSORS_VT8231) += vt8231.o obj-$(CONFIG_SENSORS_W83627EHF) += w83627ehf.o obj-$(CONFIG_SENSORS_W83L785TS) += w83l785ts.o +obj-$(CONFIG_MXC_MMA7450) += mxc_mma7450.o obj-$(CONFIG_SENSORS_W83L786NG) += w83l786ng.o +obj-$(CONFIG_SENSORS_ISL29003) += isl29003.o ifeq ($(CONFIG_HWMON_DEBUG_CHIP),y) EXTRA_CFLAGS += -DDEBUG diff -urN linux-2.6.26/drivers/hwmon/isl29003.c linux-2.6.26-lab126/drivers/hwmon/isl29003.c --- linux-2.6.26/drivers/hwmon/isl29003.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/hwmon/isl29003.c 2010-08-10 04:17:04.000000000 -0400 @@ -0,0 +1,441 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file drivers/hwmon/isl29003.c + * + * @brief ISL29003 light sensor Driver + * + * @ingroup + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum isl29003_width { + ISL29003_WIDTH_16 = 0, + ISL29003_WIDTH_12, + ISL29003_WIDTH_8, + ISL29003_WIDTH_4, +}; + +enum isl29003_gain { + ISL29003_GAIN_1000 = 0, + ISL29003_GAIN_4000, + ISL29003_GAIN_16000, + ISL29003_GAIN_64000, +}; + +enum isl29003_mode { + ISL29003_MODE_DIODE1 = 0, + ISL29003_MODE_DIODE2, + ISL29003_MODE_DIODE1_2, +}; + +struct isl29003_param { + enum isl29003_width width; + enum isl29003_gain gain; + enum isl29003_mode mode; +}; + +/* bit definition for ISL29003_CMD reg */ +#define ENABLE 7 +#define ADCPD 6 +#define TIMEING_MODE 5 +#define MODE 2 +#define WIDTH 0 + +/* bit definition for ISL29003_CTRL reg */ +#define INT_FLAG 5 +#define GAIN 2 +#define INT_PERSIST 0 + +enum isl29003_reg { + ISL29003_CMD = 0, + ISL29003_CTRL, + ISL29003_THRS_HI, + ISL29003_THRS_LO, + ISL29003_LSB_S, + ISL29003_MSB_S, + ISL29003_LSB_T, + ISL29003_MSB_T, + ISL29003_SYNC_IIC = 0x80, + ISL29003_CLAR_INT = 0x40 +}; + +/* default configure for ISL29003 */ +#define ISL29003_WIDTH_DEFAULT ISL29003_WIDTH_16 +#define ISL29003_GAIN_DEFAULT ISL29003_GAIN_16000 +#define ISL29003_MODE_DEFAULT ISL29003_MODE_DIODE1 + +/* range table for different GAIN settings */ +int range[4] = { 973, 3892, 15568, 62272 }; + +/* width table for different WIDTH settings */ +int width[4] = { 16, 1, 256, 16 }; + +struct isl29003_data { + struct i2c_client *client; + struct device *hwmon_dev; + struct regulator *vdd_reg; + struct isl29003_param param; + int lux_coeff; + unsigned char enable; +}; + +static struct i2c_client *isl29003_client; + +/*! + * This function do the isl29003 register read. + */ +int isl29003_read(struct i2c_client *client, u8 reg) +{ + return i2c_smbus_read_byte_data(client, reg); +} + +/*! + * This function do the isl29003 register write. + */ +int isl29003_write(struct i2c_client *client, u8 reg, char value) +{ + return i2c_smbus_write_byte_data(client, reg, value); +} + +/*! + * This function do the isl29003 config and enable. + */ +static int isl29003_on(void) +{ + unsigned char cmd; + int err = 0; + struct mxc_lightsensor_platform_data *ls_data; + struct isl29003_data *data = i2c_get_clientdata(isl29003_client); + + if (data->enable) + goto exit; + + ls_data = (struct mxc_lightsensor_platform_data *) + (isl29003_client->dev).platform_data; + + /* coeff=range*100k/rext/2^n */ + data->lux_coeff = range[data->param.gain] * 100 / + ls_data->rext / width[data->param.width]; + + if (data->vdd_reg) + regulator_enable(data->vdd_reg); + msleep(100); + + cmd = data->param.gain << GAIN; + if (isl29003_write(isl29003_client, ISL29003_CTRL, cmd)) { + err = -ENODEV; + goto exit; + } + + cmd = (data->param.width << WIDTH) | (data->param.mode << MODE) | + (1 << ENABLE); + if (isl29003_write(isl29003_client, ISL29003_CMD, cmd)) { + err = -ENODEV; + goto exit; + } + + data->enable = 1; + + pr_info("isl29003 on\n"); + return 0; +exit: + return err; +} + +/*! + * This function shut down the isl29003. + */ +static int isl29003_off(void) +{ + struct isl29003_data *data = i2c_get_clientdata(isl29003_client); + int cmd; + + if (!data->enable) + return 0; + + cmd = isl29003_read(isl29003_client, ISL29003_CMD); + if (cmd < 0) + return -ENODEV; + + cmd = ((cmd | (1 << ADCPD)) & (~(1 << ENABLE))); + if (isl29003_write(isl29003_client, ISL29003_CMD, (char)cmd)) + return -ENODEV; + + if (data->vdd_reg) + regulator_disable(data->vdd_reg); + + data->enable = 0; + + pr_info("isl29003 off\n"); + return 0; +} + +/*! + * This function read the isl29003 lux registers and convert them to the lux + * value. + * + * @output buffer this param holds the lux value, when =-1, read fail + * + * @return 0 + */ +static int isl29003_read_lux(void) +{ + int d; + int lux; + struct isl29003_data *data = i2c_get_clientdata(isl29003_client); + + d = isl29003_read(isl29003_client, ISL29003_MSB_S); + if (d < 0) + goto err; + + lux = d; + d = isl29003_read(isl29003_client, ISL29003_LSB_S); + if (d < 0) + goto err; + + lux = (lux << 8) + d; + + if (data->param.width < ISL29003_WIDTH_8) + lux = (data->lux_coeff * lux) >> 12; + else + lux = data->lux_coeff * lux; + + return lux; +err: + return -1; +} + +static ssize_t ls_enable(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + char *endp; + int enable = simple_strtoul(buf, &endp, 0); + size_t size = endp - buf; + + if (*endp && isspace(*endp)) + size++; + if (size != count) + return -EINVAL; + + if (enable == 1) { + if (isl29003_on()) + pr_info("device open fail\n"); + } + if (enable == 0) { + if (isl29003_off()) + pr_info("device powerdown fail\n"); + } + + return count; +} + +static SENSOR_DEVICE_ATTR(enable, S_IWUGO, NULL, ls_enable, 0); + +static ssize_t show_lux(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%u\n", isl29003_read_lux()); +} + +static SENSOR_DEVICE_ATTR(lux, S_IRUGO, show_lux, NULL, 0); + +static int isl29003_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *did) +{ + int err = 0; + struct isl29003_data *data; + struct regulator *vdd_reg; + struct mxc_lightsensor_platform_data *ls_data; + + ls_data = (struct mxc_lightsensor_platform_data *) + (client->dev).platform_data; + + if (ls_data && ls_data->vdd_reg) + vdd_reg = regulator_get(&client->dev, ls_data->vdd_reg); + else + vdd_reg = NULL; + + /* check the existence of the device */ + if (vdd_reg) + regulator_enable(vdd_reg); + msleep(100); + + if (isl29003_write(client, ISL29003_CMD, 0)) + err = -ENODEV; + + if (!err) + if (isl29003_read(client, ISL29003_CMD)) + err = -ENODEV; + + if (vdd_reg) + regulator_disable(vdd_reg); + if (err < 0) + goto exit1; + + isl29003_client = client; + data = kzalloc(sizeof(struct isl29003_data), GFP_KERNEL); + if (data == NULL) { + err = -ENOMEM; + goto exit1; + } + + i2c_set_clientdata(client, data); + data->client = client; + + data->param.width = ISL29003_WIDTH_DEFAULT; + data->param.gain = ISL29003_GAIN_DEFAULT; + data->param.mode = ISL29003_MODE_DEFAULT; + + data->enable = 0; + + err = device_create_file(&client->dev, + &sensor_dev_attr_enable.dev_attr); + if (err) + goto exit2; + + err = device_create_file(&client->dev, &sensor_dev_attr_lux.dev_attr); + if (err) + goto exit_remove1; + + /* Register sysfs hooks */ + data->hwmon_dev = hwmon_device_register(&client->dev); + if (IS_ERR(data->hwmon_dev)) { + err = PTR_ERR(data->hwmon_dev); + goto exit_remove2; + } + + data->vdd_reg = vdd_reg; + return 0; + +exit_remove2: + device_remove_file(&client->dev, &sensor_dev_attr_lux.dev_attr); +exit_remove1: + device_remove_file(&client->dev, &sensor_dev_attr_enable.dev_attr); +exit2: + kfree(data); +exit1: + if (vdd_reg) { + regulator_put(vdd_reg, &client->dev); + vdd_reg = NULL; + } + isl29003_client = NULL; + return err; +} + +static int isl29003_i2c_remove(struct i2c_client *client) +{ + int err; + struct isl29003_data *data = i2c_get_clientdata(client); + + if (data->vdd_reg) { + regulator_put(data->vdd_reg, &isl29003_client->dev); + data->vdd_reg = NULL; + } + hwmon_device_unregister(data->hwmon_dev); + device_remove_file(&client->dev, &sensor_dev_attr_enable.dev_attr); + device_remove_file(&client->dev, &sensor_dev_attr_lux.dev_attr); + err = i2c_detach_client(client); + if (err) + return err; + kfree(client); + return 0; +} + +static int isl29003_suspend(struct i2c_client *client, pm_message_t message) +{ + int cmd; + + struct isl29003_data *data = i2c_get_clientdata(client); + + if (!data->enable) + goto exit; + + cmd = isl29003_read(client, ISL29003_CMD); + if (cmd < 0) + goto err; + + cmd = (cmd | (1 << ADCPD)); + if (isl29003_write(client, ISL29003_CMD, (char)cmd)) + goto err; +exit: + return 0; +err: + return -ENODEV; +} + +static int isl29003_resume(struct i2c_client *client) +{ + int cmd; + + struct isl29003_data *data = i2c_get_clientdata(client); + + if (!data->enable) + goto exit; + + cmd = isl29003_read(client, ISL29003_CMD); + if (cmd < 0) + goto err; + + cmd = (cmd & (~(1 << ADCPD))); + if (isl29003_write(client, ISL29003_CMD, (char)cmd)) + goto err; +exit: + return 0; +err: + return -ENODEV; +} + +static const struct i2c_device_id isl29003_id[] = { + {"isl29003", 0}, + {} +}; +MODULE_DEVICE_TABLE(i2c, isl29003_id); + +static struct i2c_driver isl29003_driver = { + .driver = { + .name = "isl29003", + }, + .probe = isl29003_i2c_probe, + .remove = isl29003_i2c_remove, + .suspend = isl29003_suspend, + .resume = isl29003_resume, + .id_table = isl29003_id, +}; + +static int __init isl29003_init(void) +{ + return i2c_add_driver(&isl29003_driver);; +} + +static void __exit isl29003_cleanup(void) +{ + i2c_del_driver(&isl29003_driver); +} + +module_init(isl29003_init); +module_exit(isl29003_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("ISL29003 light sensor driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/hwmon/mxc_mma7450.c linux-2.6.26-lab126/drivers/hwmon/mxc_mma7450.c --- linux-2.6.26/drivers/hwmon/mxc_mma7450.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/hwmon/mxc_mma7450.c 2010-08-10 04:17:04.000000000 -0400 @@ -0,0 +1,788 @@ +/* + * linux/drivers/hwmon/mma7450.c + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*include file*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*macro define*/ +#define MMA7450_I2C_ADDR 0x1D +#define DEVICE_NAME "mma7450" +#define POLL_INTERVAL 50 +#define DEBUG + +#define INPUT_FUZZ 4 +#define INPUT_FLAT 4 + +enum { + REG_XOUTL = 0x00, + REG_XOUTH, + REG_YOUTL, + REG_YOUTH, + REG_ZOUTL, + REG_ZOUTH, + REG_XOUT8, + REG_YOUT8, + REG_ZOUT8, + REG_STATUS, + REG_DETSRC, + REG_TOUT, + REG_RESERVED_0, + REG_I2CAD, + REG_USRINF, + REG_WHOAMI, + REG_XOFFL, + REG_XOFFH, + REG_YOFFL, + REG_YOFFH, + REG_ZOFFL, + REG_ZOFFH, + REG_MCTL, + REG_INTRST, + REG_CTL1, + REG_CTL2, + REG_LDTH, + REG_PDTH, + REG_PD, + REG_LT, + REG_TW, + REG_REVERVED_1, +}; + +enum { + MOD_STANDBY = 0, + MOD_MEASURE, + MOD_LEVEL_D, + MOD_PULSE_D, +}; + +enum { + INT_1L_2P = 0, + INT_1P_2L, + INT_1SP_2P, +}; + +struct mma7450_status { + u8 mod; + u8 ctl1; + u8 ctl2; +}; + +/*forward declear*/ +static ssize_t mma7450_show(struct device *dev, + struct device_attribute *attr, char *buf); +static ssize_t mma7450_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count); +static int mma7450_probe(struct i2c_client *client, + const struct i2c_device_id *id); +static int mma7450_remove(struct i2c_client *client); +static int mma7450_suspend(struct i2c_client *client, pm_message_t state); +static int mma7450_resume(struct i2c_client *client); +static void mma_bh_handler(struct work_struct *work); + +/*definition*/ +static struct regulator *reg_dvdd_io; +static struct regulator *reg_avdd; +static struct i2c_client *mma7450_client; +static struct device *hwmon_dev; +static struct input_polled_dev *mma7450_idev; +static struct mxc_mma7450_platform_data *plat_data; +static u8 mma7450_mode; +static struct device_attribute mma7450_dev_attr = { + .attr = { + .name = "mma7450_ctl", + .mode = S_IRUSR | S_IWUSR, + }, + .show = mma7450_show, + .store = mma7450_store, +}; + +static const struct i2c_device_id mma7450_id[] = { + {"mma7450", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, mma7450_id); + +static struct i2c_driver i2c_mma7450_driver = { + .driver = { + .name = "mma7450", + }, + .probe = mma7450_probe, + .remove = mma7450_remove, + .suspend = mma7450_suspend, + .resume = mma7450_resume, + .id_table = mma7450_id, +}; + +static struct mma7450_status mma_status = { + .mod = 0, + .ctl1 = 0, + .ctl2 = 0, +}; + +DECLARE_WORK(mma_work, mma_bh_handler); + +#ifdef DEBUG +enum { + MMA_REG_R = 0, + MMA_REG_W, + MMA_SET_MOD, + MMA_SET_L_THR, + MMA_SET_P_THR, + MMA_SET_INTP, + MMA_SET_INTB, + MMA_SET_G, + MMA_I2C_EABLE, + MMA_OFF_X, + MMA_OFF_Y, + MMA_OFF_Z, + MMA_SELF_TEST, + MMA_SET_LDPL, + MMA_SET_PDPL, + MMA_SET_PDV, + MMA_SET_LTV, + MMA_SET_TW, + MMA_CMD_MAX +}; + +static char *command[MMA_CMD_MAX] = { + [MMA_REG_R] = "readreg", + [MMA_REG_W] = "writereg", + [MMA_SET_MOD] = "setmod", + [MMA_SET_L_THR] = "setlt", + [MMA_SET_P_THR] = "setpt", + [MMA_SET_INTP] = "setintp", + [MMA_SET_INTB] = "setintb", + [MMA_SET_G] = "setg", + [MMA_I2C_EABLE] = "setie", + [MMA_OFF_X] = "setxo", + [MMA_OFF_Y] = "setyo", + [MMA_OFF_Z] = "setzo", + [MMA_SELF_TEST] = "selft", + [MMA_SET_LDPL] = "setldp", + [MMA_SET_PDPL] = "setpdp", + [MMA_SET_PDV] = "setpdv", + [MMA_SET_LTV] = "setltv", + [MMA_SET_TW] = "settw", +}; + +static void set_mod(u8 mode) +{ + int ret; + + ret = i2c_smbus_read_byte_data(mma7450_client, REG_MCTL); + /* shall I test the ret value? */ + ret = (ret & ~0x3) | (mode & 0x3); + mma_status.mod = ret; + i2c_smbus_write_byte_data(mma7450_client, REG_MCTL, ret); +} + +static void set_level_thr(u8 lth) +{ + i2c_smbus_write_byte_data(mma7450_client, REG_LDTH, lth); +} + +static void set_pulse_thr(u8 pth) +{ + i2c_smbus_write_byte_data(mma7450_client, REG_PDTH, pth); +} + +static void set_int_pin(u8 pin) +{ + int ret; + + ret = i2c_smbus_read_byte_data(mma7450_client, REG_CTL1); + ret = (ret & ~0x1) | (pin & 0x1); + mma_status.ctl1 = ret; + i2c_smbus_write_byte_data(mma7450_client, REG_CTL1, ret); +} + +static void set_int_bit(u8 bit) +{ + int ret; + + ret = i2c_smbus_read_byte_data(mma7450_client, REG_CTL1); + ret = (ret & ~0x6) | ((bit << 1) & 0x6); + mma_status.ctl1 = ret; + i2c_smbus_write_byte_data(mma7450_client, REG_CTL1, ret); +} + +static void set_g_level(u8 gl) +{ + int ret; + + ret = i2c_smbus_read_byte_data(mma7450_client, REG_MCTL); + ret = (ret & ~0xC) | ((gl << 2) & 0xC); + i2c_smbus_write_byte_data(mma7450_client, REG_MCTL, ret); +} + +static void set_i2c_enable(u8 i2c_e) +{ + int ret; + + ret = i2c_smbus_read_byte_data(mma7450_client, REG_I2CAD); + ret = (ret & ~0x80) | ((i2c_e << 7) & 0x80); + i2c_smbus_write_byte_data(mma7450_client, REG_I2CAD, ret); +} + +static void set_x_offset(u16 xo) +{ + u8 data; + + data = (xo & 0xFF); + i2c_smbus_write_byte_data(mma7450_client, REG_XOFFL, data); + data = (xo & 0xFF00) >> 8; + i2c_smbus_write_byte_data(mma7450_client, REG_XOFFH, data); +} + +static void set_y_offset(u16 yo) +{ + u8 data; + + data = (yo & 0xFF); + i2c_smbus_write_byte_data(mma7450_client, REG_YOFFL, data); + data = (yo & 0xFF00) >> 8; + i2c_smbus_write_byte_data(mma7450_client, REG_YOFFH, data); +} + +static void set_z_offset(u16 zo) +{ + u8 data; + + data = (zo & 0xFF); + i2c_smbus_write_byte_data(mma7450_client, REG_ZOFFL, data); + data = (zo & 0xFF00) >> 8; + i2c_smbus_write_byte_data(mma7450_client, REG_ZOFFH, data); +} + +static void selftest(u8 st) +{ + int ret; + + ret = i2c_smbus_read_byte_data(mma7450_client, REG_MCTL); + ret = (ret & ~0x10) | ((st << 4) & 0x10); + i2c_smbus_write_byte_data(mma7450_client, REG_MCTL, ret); +} + +static void set_level_det_p(u8 ldp) +{ + int ret; + + ret = i2c_smbus_read_byte_data(mma7450_client, REG_CTL2); + ret = (ret & ~0x1) | ((ldp << 0) & 0x1); + mma_status.ctl2 = ret; + i2c_smbus_write_byte_data(mma7450_client, REG_CTL2, ret); +} + +static void set_pulse_det_p(u8 pdp) +{ + int ret; + + ret = i2c_smbus_read_byte_data(mma7450_client, REG_CTL2); + ret = (ret & ~0x2) | ((pdp << 1) & 0x2); + mma_status.ctl2 = ret; + i2c_smbus_write_byte_data(mma7450_client, REG_CTL2, ret); +} + +static void set_pulse_duration(u8 pd) +{ + i2c_smbus_write_byte_data(mma7450_client, REG_PD, pd); +} + +static void set_latency_time(u8 lt) +{ + i2c_smbus_write_byte_data(mma7450_client, REG_LT, lt); +} + +static void set_time_window(u8 tw) +{ + i2c_smbus_write_byte_data(mma7450_client, REG_TW, tw); +} + +static void parse_arg(const char *arg, int *reg, int *value) +{ + const char *p; + + for (p = arg;; p++) { + if (*p == ' ' || *p == '\0') + break; + } + + p++; + + *reg = simple_strtoul(arg, NULL, 16); + *value = simple_strtoul(p, NULL, 16); +} + +static void cmd_read_reg(const char *arg) +{ + int reg, value, ret; + + parse_arg(arg, ®, &value); + ret = i2c_smbus_read_byte_data(mma7450_client, reg); + dev_info(&mma7450_client->dev, "read reg0x%x = %x\n", reg, ret); +} + +static void cmd_write_reg(const char *arg) +{ + int reg, value, ret; + + parse_arg(arg, ®, &value); + ret = i2c_smbus_write_byte_data(mma7450_client, reg, value); + dev_info(&mma7450_client->dev, "write reg result %s\n", + ret ? "failed" : "success"); +} + +static int exec_command(const char *buf, size_t count) +{ + const char *p, *s; + const char *arg; + int i, value = 0; + + for (p = buf;; p++) { + if (*p == ' ' || *p == '\0' || p - buf >= count) + break; + } + arg = p + 1; + + for (i = MMA_REG_R; i < MMA_CMD_MAX; i++) { + s = command[i]; + if (s && !strncmp(buf, s, p - buf)) { + dev_info(&mma7450_client->dev, "command %s\n", s); + goto mma_exec_command; + } + } + + dev_err(&mma7450_client->dev, "command is not found\n"); + return -1; + + mma_exec_command: + if (i != MMA_REG_R && i != MMA_REG_W) + value = simple_strtoul(arg, NULL, 16); + + switch (i) { + case MMA_REG_R: + cmd_read_reg(arg); + break; + case MMA_REG_W: + cmd_write_reg(arg); + break; + case MMA_SET_MOD: + set_mod(value); + break; + case MMA_SET_L_THR: + set_level_thr(value); + break; + case MMA_SET_P_THR: + set_pulse_thr(value); + break; + case MMA_SET_INTP: + set_int_pin(value); + break; + case MMA_SET_INTB: + set_int_bit(value); + break; + case MMA_SET_G: + set_g_level(value); + break; + case MMA_I2C_EABLE: + set_i2c_enable(value); + break; + case MMA_OFF_X: + set_x_offset(value); + break; + case MMA_OFF_Y: + set_y_offset(value); + break; + case MMA_OFF_Z: + set_z_offset(value); + break; + case MMA_SELF_TEST: + selftest(value); + break; + case MMA_SET_LDPL: + set_level_det_p(value); + break; + case MMA_SET_PDPL: + set_pulse_det_p(value); + break; + case MMA_SET_PDV: + set_pulse_duration(value); + break; + case MMA_SET_LTV: + set_latency_time(value); + break; + case MMA_SET_TW: + set_time_window(value); + break; + default: + dev_err(&mma7450_client->dev, "command is not found\n"); + break; + } + + return 0; +} + +static ssize_t mma7450_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret, reg; + + for (reg = REG_XOUTL; reg < REG_REVERVED_1; reg++) { + ret = i2c_smbus_read_byte_data(mma7450_client, reg); + dev_info(&mma7450_client->dev, "reg0x%02x:\t%03d\t0x%02x\n", + reg, (s8) ret, ret); + } + + return 0; +} + +static ssize_t mma7450_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + exec_command(buf, count); + + return count; +} + +#else + +static ssize_t mma7450_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return 0; +} + +static ssize_t mma7450_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + return count; +} + +#endif + +static void report_abs(void) +{ + u8 status, mod = mma_status.mod; + s16 x, y, z, tmp; + + status = i2c_smbus_read_byte_data(mma7450_client, REG_STATUS); + if (!(status & 0x01)) { /* data ready in measurement mode? */ + return; + } + if ((mod & 0x0c) == 0) { /* 8g range */ + x = 0xFF & i2c_smbus_read_byte_data(mma7450_client, REG_XOUTL); + x |= 0xFF00 & + (i2c_smbus_read_byte_data(mma7450_client, REG_XOUTH) << 8); + y = 0xFF & i2c_smbus_read_byte_data(mma7450_client, REG_YOUTL); + y |= 0xFF00 & + (i2c_smbus_read_byte_data(mma7450_client, REG_YOUTH) << 8); + z = 0xFF & i2c_smbus_read_byte_data(mma7450_client, REG_ZOUTL); + z |= 0xFF00 & + (i2c_smbus_read_byte_data(mma7450_client, REG_ZOUTH) << 8); + } else { /* 2g/4g range */ + x = 0xFF & i2c_smbus_read_byte_data(mma7450_client, REG_XOUT8); + y = 0xFF & i2c_smbus_read_byte_data(mma7450_client, REG_YOUT8); + z = 0xFF & i2c_smbus_read_byte_data(mma7450_client, REG_ZOUT8); + } + + status = i2c_smbus_read_byte_data(mma7450_client, REG_STATUS); + if (status & 0x02) { /* data is overwrite */ + return; + } + + /* convert signed 10bits to signed 16bits */ + x = (short)(x << 6) >> 6; + y = (short)(y << 6) >> 6; + z = (short)(z << 6) >> 6; + + input_report_abs(mma7450_idev->input, ABS_X, x); + input_report_abs(mma7450_idev->input, ABS_Y, y); + input_report_abs(mma7450_idev->input, ABS_Z, z); + input_sync(mma7450_idev->input); +} + +static void mma_bh_handler(struct work_struct *work) +{ + report_abs(); +} + +static void mma7450_dev_poll(struct input_polled_dev *dev) +{ + report_abs(); +} + +static irqreturn_t mma7450_interrupt(int irq, void *dev_id) +{ + struct input_dev *input_dev = dev_id; + u8 int_bit, int_pin; + + int_bit = mma_status.ctl1 & 0x6; + int_pin = mma_status.ctl1 & 0x1; + + switch (mma_status.mod & 0x03) { + case 1: + /*only int1 report data ready int */ + if (plat_data->int1 != irq) + goto error_bad_int; + schedule_work(&mma_work); + break; + case 2: + /* for level and pulse detection mode, + * choice tasklet to handle interrupt quickly. + * Currently, leave it doing nothing*/ + if (plat_data->int1 == irq) { + if ((int_bit == 0) && (int_pin != 0)) + goto error_bad_int; + if ((int_bit == 0x2) && (int_pin != 0x1)) + goto error_bad_int; + if (int_bit == 0x4) + goto error_bad_int; + } + if (plat_data->int2 == irq) { + if ((int_bit == 0) && (int_pin != 0x1)) + goto error_bad_int; + if ((int_bit == 0x2) && (int_pin != 0)) + goto error_bad_int; + if (int_bit == 0x4) + goto error_bad_int; + } + + dev_info(&input_dev->dev, "motion detected in level mod\n"); + + break; + case 3: + if (plat_data->int1 == irq) { + if ((int_bit == 0) && (int_pin != 0x1)) + goto error_bad_int; + if ((int_bit == 0x2) && (int_pin != 0)) + goto error_bad_int; + if ((int_bit == 0x4) && (int_pin != 0x1)) + goto error_bad_int; + } + if (plat_data->int2 == irq) { + if ((int_bit == 0) && (int_pin != 0)) + goto error_bad_int; + if ((int_bit == 0x2) && (int_pin != 0x1)) + goto error_bad_int; + if ((int_bit == 0x4) && (int_pin != 0)) + goto error_bad_int; + } + + if (mma_status.ctl2 & 0x02) + dev_info(&input_dev->dev, + "freefall detected in pulse mod\n"); + else + dev_info(&input_dev->dev, + "motion detected in pulse mod\n"); + + break; + case 0: + default: + break; + } + error_bad_int: + return IRQ_RETVAL(1); +} + +static int mma7450_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret; + struct input_dev *idev; + + plat_data = + (struct mxc_mma7450_platform_data *)client->dev.platform_data; + if (plat_data == NULL) { + dev_err(&client->dev, "lack of platform data!\n"); + return -ENODEV; + } + + /*enable power supply */ + /*when to power on/off the power is to be considered later */ + /*shall I check the return value */ + reg_dvdd_io = regulator_get(&client->dev, plat_data->reg_dvdd_io); + if (reg_dvdd_io != ERR_PTR(-ENOENT)) + regulator_enable(reg_dvdd_io); + else + return -EINVAL; + + reg_avdd = regulator_get(&client->dev, plat_data->reg_avdd); + if (reg_avdd != ERR_PTR(-ENOENT)) + regulator_enable(reg_avdd); + else { + regulator_put(reg_dvdd_io, &client->dev); + return -EINVAL; + } + + /*bind the right device to the driver */ + ret = i2c_smbus_read_byte_data(client, REG_I2CAD); + if (MMA7450_I2C_ADDR != (0x7F & ret)) { /*compare the address value */ + dev_err(&client->dev, + "read chip ID 0x%x is not equal to 0x%x!\n", ret, + MMA7450_I2C_ADDR); + goto error_disable_power; + } + mma7450_client = client; + + /*interrupt register */ + /*when to register interrupt is to be considered later */ + + /*create device file in sysfs as user interface */ + ret = device_create_file(&client->dev, &mma7450_dev_attr); + if (ret) { + dev_err(&client->dev, "create device file failed!\n"); + goto error_disable_power; + } + + /*register to hwmon device */ + hwmon_dev = hwmon_device_register(&client->dev); + if (IS_ERR(hwmon_dev)) { + dev_err(&client->dev, "hwmon register failed!\n"); + ret = PTR_ERR(hwmon_dev); + goto error_rm_dev_file; + } + + /*input poll device register */ + mma7450_idev = input_allocate_polled_device(); + if (!mma7450_idev) { + dev_err(&client->dev, "alloc poll device failed!\n"); + ret = -ENOMEM; + goto error_rm_hwmon_dev; + } + mma7450_idev->poll = mma7450_dev_poll; + mma7450_idev->poll_interval = POLL_INTERVAL; + idev = mma7450_idev->input; + idev->name = DEVICE_NAME; + idev->id.bustype = BUS_I2C; + idev->dev.parent = &client->dev; + idev->evbit[0] = BIT_MASK(EV_ABS); + + input_set_abs_params(idev, ABS_X, -512, 512, INPUT_FUZZ, INPUT_FLAT); + input_set_abs_params(idev, ABS_Y, -512, 512, INPUT_FUZZ, INPUT_FLAT); + input_set_abs_params(idev, ABS_Z, -512, 512, INPUT_FUZZ, INPUT_FLAT); + ret = input_register_polled_device(mma7450_idev); + if (ret) { + dev_err(&client->dev, "register poll device failed!\n"); + goto error_free_poll_dev; + } + + /* configure gpio as input for interrupt monitor */ + plat_data->gpio_pin_get(); + + set_irq_type(plat_data->int1, IRQF_TRIGGER_RISING); + /* register interrupt handle */ + ret = request_irq(plat_data->int1, mma7450_interrupt, + IRQF_TRIGGER_RISING, DEVICE_NAME, idev); + + if (ret) { + dev_err(&client->dev, "request_irq(%d) returned error %d\n", + plat_data->int1, ret); + goto error_rm_poll_dev; + } + + set_irq_type(plat_data->int2, IRQF_TRIGGER_RISING); + ret = request_irq(plat_data->int2, mma7450_interrupt, + IRQF_TRIGGER_RISING, DEVICE_NAME, idev); + if (ret) { + dev_err(&client->dev, "request_irq(%d) returned error %d\n", + plat_data->int2, ret); + goto error_free_irq1; + } + + dev_info(&client->dev, "mma7450 device is probed successfully.\n"); + + return 0; /*what value shall be return */ + + /*error handle */ + error_free_irq1: + free_irq(plat_data->int1, 0); + error_rm_poll_dev: + input_unregister_polled_device(mma7450_idev); + error_free_poll_dev: + input_free_polled_device(mma7450_idev); + error_rm_hwmon_dev: + hwmon_device_unregister(hwmon_dev); + error_rm_dev_file: + device_remove_file(&client->dev, &mma7450_dev_attr); + error_disable_power: + regulator_disable(reg_dvdd_io); /*shall I check the return value */ + regulator_disable(reg_avdd); + regulator_put(reg_dvdd_io, &client->dev); + regulator_put(reg_avdd, &client->dev); + + return ret; +} + +static int mma7450_remove(struct i2c_client *client) +{ + free_irq(plat_data->int2, mma7450_idev->input); + free_irq(plat_data->int1, mma7450_idev->input); + plat_data->gpio_pin_put(); + input_unregister_polled_device(mma7450_idev); + input_free_polled_device(mma7450_idev); + hwmon_device_unregister(hwmon_dev); + device_remove_file(&client->dev, &mma7450_dev_attr); + regulator_disable(reg_dvdd_io); /*shall I check the return value */ + regulator_disable(reg_avdd); + regulator_put(reg_dvdd_io, &client->dev); + regulator_put(reg_avdd, &client->dev); + return 0; +} + +static int mma7450_suspend(struct i2c_client *client, pm_message_t state) +{ + mma7450_mode = i2c_smbus_read_byte_data(mma7450_client, REG_MCTL); + i2c_smbus_write_byte_data(mma7450_client, REG_MCTL, + mma7450_mode & ~0x3); + return 0; +} + +static int mma7450_resume(struct i2c_client *client) +{ + i2c_smbus_write_byte_data(mma7450_client, REG_MCTL, mma7450_mode); + return 0; +} + +static int __init init_mma7450(void) +{ + /*register driver */ + printk(KERN_INFO "add mma i2c driver\n"); + return i2c_add_driver(&i2c_mma7450_driver); +} + +static void __exit exit_mma7450(void) +{ + printk(KERN_INFO "del mma i2c driver.\n"); + return i2c_del_driver(&i2c_mma7450_driver); +} + +module_init(init_mma7450); +module_exit(exit_mma7450); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MMA7450 sensor driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/i2c/busses/Kconfig linux-2.6.26-lab126/drivers/i2c/busses/Kconfig --- linux-2.6.26/drivers/i2c/busses/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/i2c/busses/Kconfig 2010-08-10 04:17:27.000000000 -0400 @@ -305,6 +305,57 @@ This driver can also be built as a module. If so, the module will be called i2c-mpc. +config I2C_MXC + tristate "MXC I2C support" + depends on I2C && ARCH_MXC + help + If you say yes to this option, support will be included for Freescale + MXC I2C modules. + + This driver can also be built as a module. + +config I2C_MXC_FAST_MODE_BUS_0 + tristate "MXC I2C Fast Mode Support Bus 0" + depends on I2C && ARCH_MXC + default n + help + If you say yes to this option, support will be included for Freescale + MXC I2C Fast Mode for Bus 0. This drives the i2c bus at 400Kb/s as + against the normal mode of 100Kb/s + + This driver can also be built as a module. + +config I2C_MXC_FAST_MODE_BUS_1 + tristate "MXC I2C Fast Mode Support Bus 1" + depends on I2C && ARCH_MXC + default n + help + If you say yes to this option, support will be included for Freescale + MXC I2C Fast Mode for Bus 1. This drives the i2c bus at 400Kb/s as + against the normal mode of 100Kb/s + + This driver can also be built as a module. + +config I2C_MXC_FAST_MODE_BUS_2 + tristate "MXC I2C Fast Mode Support Bus 2" + depends on I2C && ARCH_MXC + default n + help + If you say yes to this option, support will be included for Freescale + MXC I2C Fast Mode for Bus 2. This drives the i2c bus at 400Kb/s as + against the normal mode of 100Kb/s + + This driver can also be built as a module. + +config I2C_MXC_HS + tristate "MXC HIGH SPEED I2C support" + depends on I2C && ARCH_MXC + help + If you say yes to this option, support will be included for Freescale + MXC HIGH SPEED I2C modules. + + This driver can also be built as a module. + config I2C_NFORCE2 tristate "Nvidia nForce2, nForce3 and nForce4" depends on PCI diff -urN linux-2.6.26/drivers/i2c/busses/Makefile linux-2.6.26-lab126/drivers/i2c/busses/Makefile --- linux-2.6.26/drivers/i2c/busses/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/i2c/busses/Makefile 2010-08-10 04:17:27.000000000 -0400 @@ -55,6 +55,8 @@ obj-$(CONFIG_I2C_VOODOO3) += i2c-voodoo3.o obj-$(CONFIG_SCx200_ACB) += scx200_acb.o obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o +obj-$(CONFIG_I2C_MXC) += mxc_i2c.o +obj-$(CONFIG_I2C_MXC_HS) += mxc_i2c_hs.o ifeq ($(CONFIG_I2C_DEBUG_BUS),y) EXTRA_CFLAGS += -DDEBUG diff -urN linux-2.6.26/drivers/i2c/busses/mxc_i2c.c linux-2.6.26-lab126/drivers/i2c/busses/mxc_i2c.c --- linux-2.6.26/drivers/i2c/busses/mxc_i2c.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/i2c/busses/mxc_i2c.c 2010-08-10 04:17:27.000000000 -0400 @@ -0,0 +1,828 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2009 Amazon Technologies, Inc. All Rights Reserved. + * Manish Lachwani (lachwani@lab126.com) + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_i2c.c + * + * @brief Driver for the Freescale Semiconductor MXC I2C buses. + * + * Based on i2c driver algorithm for PCF8584 adapters + * + * @ingroup MXCI2C + */ + +/* + * Include Files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_i2c_reg.h" + +/*! + * In case the MXC device has multiple I2C modules, this structure is used to + * store information specific to each I2C module. + */ +typedef struct { + /*! + * This structure is used to identify the physical i2c bus along with + * the access algorithms necessary to access it. + */ + struct i2c_adapter adap; + + /*! + * This waitqueue is used to wait for the data transfer to complete. + */ + wait_queue_head_t wq; + + /*! + * The base address of the I2C device. + */ + unsigned long membase; + + /*! + * The interrupt number used by the I2C device. + */ + int irq; + + /*! + * The default clock divider value to be used. + */ + unsigned int clkdiv; + + /*! + * The clock source for the device. + */ + struct clk *clk; + + /*! + * The current power state of the device + */ + bool low_power; + + /*! + * Boolean to indicate if data was transferred + */ + bool transfer_done; + + /*! + * Boolean to indicate if we received an ACK for the data transmitted + */ + bool tx_success; +} mxc_i2c_device; + +struct clk_div_table { + int reg_value; + int div; +}; + +static const struct clk_div_table i2c_clk_table[] = { + {0x20, 22}, {0x21, 24}, {0x22, 26}, {0x23, 28}, + {0, 30}, {1, 32}, {0x24, 32}, {2, 36}, + {0x25, 36}, {0x26, 40}, {3, 42}, {0x27, 44}, + {4, 48}, {0x28, 48}, {5, 52}, {0x29, 56}, + {6, 60}, {0x2A, 64}, {7, 72}, {0x2B, 72}, + {8, 80}, {0x2C, 80}, {9, 88}, {0x2D, 96}, + {0xA, 104}, {0x2E, 112}, {0xB, 128}, {0x2F, 128}, + {0xC, 144}, {0xD, 160}, {0x30, 160}, {0xE, 192}, + {0x31, 192}, {0x32, 224}, {0xF, 240}, {0x33, 256}, + {0x10, 288}, {0x11, 320}, {0x34, 320}, {0x12, 384}, + {0x35, 384}, {0x36, 448}, {0x13, 480}, {0x37, 512}, + {0x14, 576}, {0x15, 640}, {0x38, 640}, {0x16, 768}, + {0x39, 768}, {0x3A, 896}, {0x17, 960}, {0x3B, 1024}, + {0x18, 1152}, {0x19, 1280}, {0x3C, 1280}, {0x1A, 1536}, + {0x3D, 1536}, {0x3E, 1792}, {0x1B, 1920}, {0x3F, 2048}, + {0x1C, 2304}, {0x1D, 2560}, {0x1E, 3072}, {0x1F, 3840}, + {0, 0} +}; + +extern void gpio_i2c_active(int i2c_num); +extern void gpio_i2c_inactive(int i2c_num); + +int mxc_i2c_suspended = 0; +EXPORT_SYMBOL(mxc_i2c_suspended); + +extern void luigi_battery_suspend(void); +extern void luigi_battery_resume(void); +extern void luigi_battery_resume_stats(void); + +/*! + * Transmit a \b STOP signal to the slave device. + * + * @param dev the mxc i2c structure used to get to the right i2c device + */ +static void mxc_i2c_stop(mxc_i2c_device * dev) +{ + unsigned int cr, sr; + int retry = 16; + raw_spinlock_t lock; + + spin_lock(&lock); + + cr = readw(dev->membase + MXC_I2CR); + cr &= ~(MXC_I2CR_MSTA | MXC_I2CR_MTX); + udelay(10); + writew(cr, dev->membase + MXC_I2CR); + + /* Wait till the Bus Busy bit is reset */ + sr = readw(dev->membase + MXC_I2SR); + while (retry-- && ((sr & MXC_I2SR_IBB))) { + udelay(10); + sr = readw(dev->membase + MXC_I2SR); + } + + spin_unlock(&lock); + + if (retry <= 0) { + dev_dbg(&dev->adap.dev, "mxc_i2c_stop: Could not set I2C Bus Busy bit" + " to zero.\n"); + } +} + +/*! + * Wait for the transmission of the data byte to complete. This function waits + * till we get a signal from the interrupt service routine indicating completion + * of the address cycle or we time out. + * + * @param dev the mxc i2c structure used to get to the right i2c device + * @param trans_flag transfer flag + * + * + * @return The function returns 0 on success or -1 if an ack was not received + */ + +static int mxc_i2c_wait_for_tc(mxc_i2c_device * dev, int trans_flag) +{ + int retry = 16; + + while (retry-- && !dev->transfer_done) { + wait_event_interruptible_timeout(dev->wq, + dev->transfer_done, + dev->adap.timeout); + } + dev->transfer_done = false; + + if (retry <= 0) { + /* Unable to send data */ + dev_dbg(&dev->adap.dev, "mxc_i2c_wait_for_tc: Data not transmitted\n"); + return -1; + } + + if (!dev->tx_success) { + /* An ACK was not received for transmitted byte */ + dev_dbg(&dev->adap.dev, "mxc_i2c_wait_for_tc: ACK not received \n"); + return -1; + } + + return 0; +} + +/*! + * Transmit a \b START signal to the slave device. + * + * @param dev the mxc i2c structure used to get to the right i2c device + * @param *msg pointer to a message structure that contains the slave + * address + * + * @return The function returns EBUSY on failure, 0 on success. + */ +static int mxc_i2c_start(mxc_i2c_device *dev, struct i2c_msg *msg) +{ + volatile unsigned int cr, sr; + unsigned int addr_trans; + int retry = 16; + + /* + * Set the slave address and the requested transfer mode + * in the data register + */ + addr_trans = msg->addr << 1; + if (msg->flags & I2C_M_RD) { + addr_trans |= 0x01; + } + + /* Set the Master bit */ + cr = readw(dev->membase + MXC_I2CR); + cr |= MXC_I2CR_MSTA; + writew(cr, dev->membase + MXC_I2CR); + + /* Wait till the Bus Busy bit is set */ + sr = readw(dev->membase + MXC_I2SR); + while (retry-- && (!(sr & MXC_I2SR_IBB))) { + udelay(10); + sr = readw(dev->membase + MXC_I2SR); + } + if (retry <= 0) { + dev_dbg(&dev->adap.dev, "mxc_i2c_start: Could not grab Bus ownership\n"); + return -EBUSY; + } + + /* Set the Transmit bit */ + cr = readw(dev->membase + MXC_I2CR); + cr |= MXC_I2CR_MTX; + writew(cr, dev->membase + MXC_I2CR); + + writew(addr_trans, dev->membase + MXC_I2DR); + return 0; +} + +/*! + * Transmit a \b REPEAT START to the slave device + * + * @param dev the mxc i2c structure used to get to the right i2c device + * @param *msg pointer to a message structure that contains the slave + * address + */ +static void mxc_i2c_repstart(mxc_i2c_device * dev, struct i2c_msg *msg) +{ + volatile unsigned int cr; + unsigned int addr_trans; + + /* + * Set the slave address and the requested transfer mode + * in the data register + */ + addr_trans = msg->addr << 1; + if (msg->flags & I2C_M_RD) { + addr_trans |= 0x01; + } + cr = readw(dev->membase + MXC_I2CR); + cr |= MXC_I2CR_RSTA; + writew(cr, dev->membase + MXC_I2CR); + udelay(3); + writew(addr_trans, dev->membase + MXC_I2DR); +} + +/*! + * Read the received data. The function waits till data is available or times + * out. Generates a stop signal if this is the last message to be received. + * Sends an ack for all the bytes received except the last byte. + * + * @param dev the mxc i2c structure used to get to the right i2c device + * @param *msg pointer to a message structure that contains the slave + * address and a pointer to the receive buffer + * @param last indicates that this is the last message to be received + * @param addr_comp flag indicates that we just finished the address cycle + * + * @return The function returns the number of bytes read or -1 on time out. + */ +static int mxc_i2c_readbytes(mxc_i2c_device * dev, struct i2c_msg *msg, + int last, int addr_comp) +{ + int i; + char *buf = msg->buf; + int len = msg->len; + volatile unsigned int cr; + + cr = readw(dev->membase + MXC_I2CR); + /* + * Clear MTX to switch to receive mode. + */ + cr &= ~MXC_I2CR_MTX; + /* + * Clear the TXAK bit to gen an ack when receiving only one byte. + */ + if (len == 1) { + cr |= MXC_I2CR_TXAK; + } else { + cr &= ~MXC_I2CR_TXAK; + } + writew(cr, dev->membase + MXC_I2CR); + /* + * Dummy read only at the end of an address cycle + */ + if (addr_comp > 0) { + readw(dev->membase + MXC_I2DR); + } + + for (i = 0; i < len; i++) { + /* + * Wait for data transmission to complete + */ + if (mxc_i2c_wait_for_tc(dev, msg->flags)) { + mxc_i2c_stop(dev); + return -1; + } + /* + * Do not generate an ACK for the last byte + */ + if (i == (len - 2)) { + cr = readw(dev->membase + MXC_I2CR); + cr |= MXC_I2CR_TXAK; + writew(cr, dev->membase + MXC_I2CR); + } else if (i == (len - 1)) { + if (last) { + mxc_i2c_stop(dev); + } + } + /* Read the data */ + *buf++ = readw(dev->membase + MXC_I2DR); + } + + return i; +} + +/*! + * Write the data to the data register. Generates a stop signal if this is + * the last message to be sent or if no ack was received for the data sent. + * + * @param dev the mxc i2c structure used to get to the right i2c device + * @param *msg pointer to a message structure that contains the slave + * address and data to be sent + * @param last indicates that this is the last message to be received + * + * @return The function returns the number of bytes written or -1 on time out + * or if no ack was received for the data that was sent. + */ +static int mxc_i2c_writebytes(mxc_i2c_device * dev, struct i2c_msg *msg, + int last) +{ + int i; + char *buf = msg->buf; + int len = msg->len; + volatile unsigned int cr; + + cr = readw(dev->membase + MXC_I2CR); + /* Set MTX to switch to transmit mode */ + cr |= MXC_I2CR_MTX; + writew(cr, dev->membase + MXC_I2CR); + + for (i = 0; i < len; i++) { + /* + * Write the data + */ + writew(*buf++, dev->membase + MXC_I2DR); + if (mxc_i2c_wait_for_tc(dev, msg->flags)) { + mxc_i2c_stop(dev); + return -1; + } + } + if (last > 0) { + mxc_i2c_stop(dev); + } + + return i; +} + +/*! + * Function enables the I2C module and initializes the registers. + * + * @param dev the mxc i2c structure used to get to the right i2c device + * @param trans_flag transfer flag + */ +static void mxc_i2c_module_en(mxc_i2c_device * dev, int trans_flag) +{ + clk_enable(dev->clk); + /* Set the frequency divider */ + writew(dev->clkdiv, dev->membase + MXC_IFDR); + /* Clear the status register */ + writew(0x0, dev->membase + MXC_I2SR); + /* Enable I2C and its interrupts */ + writew(MXC_I2CR_IEN, dev->membase + MXC_I2CR); + writew(MXC_I2CR_IEN | MXC_I2CR_IIEN, dev->membase + MXC_I2CR); +} + +/*! + * Disables the I2C module. + * + * @param dev the mxc i2c structure used to get to the right i2c device + */ +static void mxc_i2c_module_dis(mxc_i2c_device * dev) +{ + writew(0x0, dev->membase + MXC_I2CR); + clk_disable(dev->clk); +} + +/*! + * The function is registered in the adapter structure. It is called when an MXC + * driver wishes to transfer data to a device connected to the I2C device. + * + * @param adap adapter structure for the MXC i2c device + * @param msgs[] array of messages to be transferred to the device + * @param num number of messages to be transferred to the device + * + * @return The function returns the number of messages transferred, + * \b -EREMOTEIO on I2C failure and a 0 if the num argument is + * less than 0. + */ +static int mxc_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], + int num) +{ + mxc_i2c_device *dev = (mxc_i2c_device *) (i2c_get_adapdata(adap)); + int i, ret = 0, addr_comp = 0; + volatile unsigned int sr; + int retry = 5; + + if (dev->low_power) { + dev_err(&dev->adap.dev, "mxc_i2c_xfer: I2C Device in low power mode\n"); + return -EREMOTEIO; + } + + if (num < 1) { + return 0; + } + + mxc_i2c_module_en(dev, msgs[0].flags); + sr = readw(dev->membase + MXC_I2SR); + /* + * Check bus state + */ + + while ((sr & MXC_I2SR_IBB) && retry--) { + udelay(5); + sr = readw(dev->membase + MXC_I2SR); + } + + if ((sr & MXC_I2SR_IBB) && retry < 0) { + mxc_i2c_module_dis(dev); + dev_err(&dev->adap.dev, "mxc_i2c_xfer: Bus busy\n"); + return -EREMOTEIO; + } + + //gpio_i2c_active(dev->adap.id); + dev->transfer_done = false; + dev->tx_success = false; + for (i = 0; i < num && ret >= 0; i++) { + addr_comp = 0; + /* + * Send the slave address and transfer direction in the + * address cycle + */ + if (i == 0) { + /* + * Send a start or repeat start signal + */ + if (mxc_i2c_start(dev, &msgs[0])) + return -EREMOTEIO; + /* Wait for the address cycle to complete */ + if (mxc_i2c_wait_for_tc(dev, msgs[0].flags)) { + mxc_i2c_stop(dev); + //gpio_i2c_inactive(dev->adap.id); + mxc_i2c_module_dis(dev); + return -EREMOTEIO; + } + addr_comp = 1; + } else { + /* + * Generate repeat start only if required i.e the address + * changed or the transfer direction changed + */ + if ((msgs[i].addr != msgs[i - 1].addr) || + ((msgs[i].flags & I2C_M_RD) != + (msgs[i - 1].flags & I2C_M_RD))) { + mxc_i2c_repstart(dev, &msgs[i]); + /* Wait for the address cycle to complete */ + if (mxc_i2c_wait_for_tc(dev, msgs[i].flags)) { + mxc_i2c_stop(dev); + //gpio_i2c_inactive(dev->adap.id); + mxc_i2c_module_dis(dev); + return -EREMOTEIO; + } + addr_comp = 1; + } + } + + /* Transfer the data */ + if (msgs[i].flags & I2C_M_RD) { + /* Read the data */ + ret = mxc_i2c_readbytes(dev, &msgs[i], (i + 1 == num), + addr_comp); + if (ret < 0) { + dev_dbg(&dev->adap.dev, "mxc_i2c_readbytes: fail.\n"); + break; + } + } else { + /* Write the data */ + ret = mxc_i2c_writebytes(dev, &msgs[i], (i + 1 == num)); + if (ret < 0) { + dev_dbg(&dev->adap.dev, "mxc_i2c_writebytes:" + " fail.\n"); + break; + } + } + } + + //gpio_i2c_inactive(dev->adap.id); + mxc_i2c_module_dis(dev); + /* + * Decrease by 1 as we do not want Start message to be included in + * the count + */ + return (i < 0 ? ret : i); +} + +/*! + * Returns the i2c functionality supported by this driver. + * + * @param adap adapter structure for this i2c device + * + * @return Returns the functionality that is supported. + */ +static u32 mxc_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +/*! + * Stores the pointers for the i2c algorithm functions. The algorithm functions + * is used by the i2c bus driver to talk to the i2c bus + */ +static struct i2c_algorithm mxc_i2c_algorithm = { + .master_xfer = mxc_i2c_xfer, + .functionality = mxc_i2c_func +}; + +/*! + * Interrupt Service Routine. It signals to the process about the data transfer + * completion. Also sets a flag if bus arbitration is lost. + * @param irq the interrupt number + * @param dev_id driver private data + * + * @return The function returns \b IRQ_HANDLED. + */ +static irqreturn_t mxc_i2c_handler(int irq, void *dev_id) +{ + mxc_i2c_device *dev = dev_id; + volatile unsigned int sr, cr; + + sr = readw(dev->membase + MXC_I2SR); + cr = readw(dev->membase + MXC_I2CR); + + /* + * Clear the interrupt bit + */ + + writew(0x0, dev->membase + MXC_I2SR); + + if (sr & MXC_I2SR_IAL) { + dev_dbg(&dev->adap.dev, "mxc_i2c_handler: Bus Arbitration lost\n"); + + /* disable IEN, then re-enable as per RM 28.5.7 Note */ + cr &= ~MXC_I2CR_IEN; + writew(cr, dev->membase + MXC_I2CR); + + udelay(10); + + cr |= MXC_I2CR_IEN; + writew(cr, dev->membase + MXC_I2CR); + + udelay(10); + + } else { + /* Interrupt due byte transfer completion */ + dev->tx_success = true; + /* Check if RXAK is received in Transmit mode */ + if ((cr & MXC_I2CR_MTX) && (sr & MXC_I2SR_RXAK)) { + dev->tx_success = false; + } + dev->transfer_done = true; + wake_up_interruptible(&dev->wq); + } + + return IRQ_HANDLED; +} + +/*! + * This function is called to put the I2C adapter in a low power state. Refer to the + * document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which I2C + * to suspend + * @param state the power state the device is entering + * + * @return The function returns 0 on success and -1 on failure. + */ +static int mxci2c_suspend(struct platform_device *pdev, pm_message_t state) +{ + mxc_i2c_device *mxcdev = platform_get_drvdata(pdev); + volatile unsigned int sr = 0; + + if (mxcdev == NULL) { + return -1; + } + + mxc_i2c_suspended = 1; + + /* Prevent further calls to be processed */ + mxcdev->low_power = true; + /* Wait till we finish the current transfer */ + sr = readw(mxcdev->membase + MXC_I2SR); + while (sr & MXC_I2SR_IBB) { + msleep(10); + sr = readw(mxcdev->membase + MXC_I2SR); + } + clk_disable(mxcdev->clk); + + if (pdev->id == 0) + luigi_battery_suspend(); + + return 0; +} + +/*! + * This function is called to bring the I2C adapter back from a low power state. Refer + * to the document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which I2C + * to resume + * + * @return The function returns 0 on success and -1 on failure + */ +static int mxci2c_resume(struct platform_device *pdev) +{ + mxc_i2c_device *mxcdev = platform_get_drvdata(pdev); + + if (mxcdev == NULL) + return -1; + + mxcdev->low_power = false; + clk_enable(mxcdev->clk); + + mxc_i2c_suspended = 0; + + if (pdev->id == 0) { + luigi_battery_resume(); + luigi_battery_resume_stats(); + } + + return 0; +} + +/*! + * This function is called during the driver binding process. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions + * + * @return The function always returns 0. + */ +static int mxci2c_probe(struct platform_device *pdev) +{ + mxc_i2c_device *mxc_i2c; + struct mxc_i2c_platform_data *i2c_plat_data = pdev->dev.platform_data; + struct resource *res; + int id = pdev->id; + u32 clk_freq; + int ret = 0; + int i = 0; + + mxc_i2c = kzalloc(sizeof(mxc_i2c_device), GFP_KERNEL); + if (!mxc_i2c) { + return -ENOMEM; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + ret = -ENODEV; + goto err1; + } + mxc_i2c->membase = IO_ADDRESS(res->start); + + /* + * Request the I2C interrupt + */ + mxc_i2c->irq = platform_get_irq(pdev, 0); + if (mxc_i2c->irq < 0) { + ret = mxc_i2c->irq; + goto err1; + } + + ret = request_irq(mxc_i2c->irq, mxc_i2c_handler, + 0, pdev->name, mxc_i2c); + if (ret < 0) { + goto err1; + } + + init_waitqueue_head(&mxc_i2c->wq); + + mxc_i2c->low_power = false; + + gpio_i2c_active(id); + + mxc_i2c->clk = clk_get(&pdev->dev, "i2c_clk"); + clk_freq = clk_get_rate(mxc_i2c->clk); + mxc_i2c->clkdiv = -1; + if (i2c_plat_data->i2c_clk) { + /* Calculate divider and round up any fractional part */ + int div = (clk_freq + i2c_plat_data->i2c_clk - 1) / + i2c_plat_data->i2c_clk; + for (i = 0; i2c_clk_table[i].div != 0; i++) { + if (i2c_clk_table[i].div >= div) { + mxc_i2c->clkdiv = i2c_clk_table[i].reg_value; + break; + } + } + } + if (mxc_i2c->clkdiv == -1) { + i--; + mxc_i2c->clkdiv = 0x1F; /* Use max divider */ + } + + /* + * Set the adapter information + */ + strlcpy(mxc_i2c->adap.name, pdev->name, 48); + mxc_i2c->adap.id = mxc_i2c->adap.nr = id; + mxc_i2c->adap.algo = &mxc_i2c_algorithm; + mxc_i2c->adap.timeout = 1; + platform_set_drvdata(pdev, mxc_i2c); + i2c_set_adapdata(&mxc_i2c->adap, mxc_i2c); + if ((ret = i2c_add_numbered_adapter(&mxc_i2c->adap)) < 0) { + goto err2; + } + + printk(KERN_INFO "MXC I2C driver\n"); + return 0; + + err2: + free_irq(mxc_i2c->irq, mxc_i2c); + gpio_i2c_inactive(id); + err1: + dev_err(&pdev->dev, "failed to probe i2c adapter\n"); + kfree(mxc_i2c); + return ret; +} + +/*! + * Dissociates the driver from the I2C device. + * + * @param pdev the device structure used to give information on which I2C + * to remove + * + * @return The function always returns 0. + */ +static int mxci2c_remove(struct platform_device *pdev) +{ + mxc_i2c_device *mxc_i2c = platform_get_drvdata(pdev); + int id = pdev->id; + + free_irq(mxc_i2c->irq, mxc_i2c); + i2c_del_adapter(&mxc_i2c->adap); + gpio_i2c_inactive(id); + clk_put(mxc_i2c->clk); + platform_set_drvdata(pdev, NULL); + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxci2c_driver = { + .driver = { + .name = "mxc_i2c", + .owner = THIS_MODULE, + }, + .probe = mxci2c_probe, + .remove = mxci2c_remove, + .suspend = mxci2c_suspend, + .resume = mxci2c_resume, +}; + +/*! + * Function requests the interrupts and registers the i2c adapter structures. + * + * @return The function returns 0 on success and a non-zero value on failure. + */ +static int __init mxc_i2c_init(void) +{ + /* Register the device driver structure. */ + return platform_driver_register(&mxci2c_driver); +} + +/*! + * This function is used to cleanup all resources before the driver exits. + */ +static void __exit mxc_i2c_exit(void) +{ + platform_driver_unregister(&mxci2c_driver); +} + +subsys_initcall(mxc_i2c_init); +module_exit(mxc_i2c_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC I2C driver"); +MODULE_LICENSE("GPL"); + diff -urN linux-2.6.26/drivers/i2c/busses/mxc_i2c_hs.c linux-2.6.26-lab126/drivers/i2c/busses/mxc_i2c_hs.c --- linux-2.6.26/drivers/i2c/busses/mxc_i2c_hs.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/i2c/busses/mxc_i2c_hs.c 2010-08-10 04:17:27.000000000 -0400 @@ -0,0 +1,549 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_i2c_hs_reg.h" + +typedef struct { + struct device *dev; + + unsigned long reg_base_virt; + unsigned long reg_base_phy; + int irq; + unsigned int speed; + struct clk *ipg_clk; + struct clk *serial_clk; + bool low_power; + + struct i2c_msg *msg; + int index; +} mxc_i2c_hs; + +struct clk_div_table { + int reg_value; + int div; +}; + +static const struct clk_div_table i2c_clk_table[] = { + {0x0, 16}, {0x1, 18}, {0x2, 20}, {0x3, 22}, + {0x20, 24}, {0x21, 26}, {0x22, 28}, {0x23, 30}, + {0x4, 32}, {0x5, 36}, {0x6, 40}, {0x7, 44}, + {0x24, 48}, {0x25, 52}, {0x26, 56}, {0x27, 60}, + {0x8, 64}, {0x9, 72}, {0xa, 80}, {0xb, 88}, + {0x28, 96}, {0x29, 104}, {0x2a, 112}, {0x2b, 120}, + {0xc, 128}, {0xd, 144}, {0xe, 160}, {0xf, 176}, + {0x2c, 192}, {0x2d, 208}, {0x2e, 224}, {0x2f, 240}, + {0x10, 256}, {0x11, 288}, {0x12, 320}, {0x13, 352}, + {0x30, 384}, {0x31, 416}, {0x32, 448}, {0x33, 480}, + {0x14, 512}, {0x15, 576}, {0x16, 640}, {0x17, 704}, + {0x34, 768}, {0x35, 832}, {0x36, 896}, {0x37, 960}, + {0x18, 1024}, {0x19, 1152}, {0x1a, 1280}, {0x1b, 1408}, + {0x38, 1536}, {0x39, 1664}, {0x3a, 1792}, {0x3b, 1920}, + {0x1c, 2048}, {0x1d, 2304}, {0x1e, 2560}, {0x1f, 2816}, + {0x3c, 3072}, {0x3d, 3328}, {0x3E, 3584}, {0x3F, 3840}, + {-1, -1} +}; + +static struct i2c_adapter *adap; + +extern void gpio_i2c_hs_inactive(void); +extern void gpio_i2c_hs_active(void); + +static u16 reg_read(mxc_i2c_hs *i2c_hs, u32 reg_offset) +{ + return __raw_readw(i2c_hs->reg_base_virt + reg_offset); +} + +static void reg_write(mxc_i2c_hs *i2c_hs, u32 reg_offset, u16 data) +{ + __raw_writew(data, i2c_hs->reg_base_virt + reg_offset); +} + +static void reg_set_mask(mxc_i2c_hs *i2c_hs, u32 reg_offset, u16 mask) +{ + u16 value; + + value = reg_read(i2c_hs, reg_offset); + value |= mask; + reg_write(i2c_hs, reg_offset, value); +} +static void reg_clear_mask(mxc_i2c_hs *i2c_hs, u32 reg_offset, u16 mask) +{ + u16 value; + + value = reg_read(i2c_hs, reg_offset); + value &= ~mask; + reg_write(i2c_hs, reg_offset, value); +} + +static void mxci2c_hs_set_div(mxc_i2c_hs *i2c_hs) +{ + unsigned long clk_freq; + int i; + int div = -1;; + + clk_freq = clk_get_rate(i2c_hs->serial_clk); + if (i2c_hs->speed) { + div = (clk_freq + i2c_hs->speed - 1) / i2c_hs->speed; + for (i = 0; i2c_clk_table[i].div >= 0; i++) { + if (i2c_clk_table[i].div >= div) { + div = i2c_clk_table[i].reg_value; + reg_write(i2c_hs, HIFSFDR, div); + break; + } + } + } +} + +static int mxci2c_hs_enable(mxc_i2c_hs *i2c_hs) +{ + gpio_i2c_hs_active(); + clk_enable(i2c_hs->ipg_clk); + clk_enable(i2c_hs->serial_clk); + mxci2c_hs_set_div(i2c_hs); + reg_write(i2c_hs, HICR, reg_read(i2c_hs, HICR) | HICR_HIEN); + + return 0; +} + +static int mxci2c_hs_disable(mxc_i2c_hs *i2c_hs) +{ + reg_write(i2c_hs, HICR, reg_read(i2c_hs, HICR) & (~HICR_HIEN)); + clk_disable(i2c_hs->ipg_clk); + clk_disable(i2c_hs->serial_clk); + + return 0; +} + +static int mxci2c_hs_bus_busy(mxc_i2c_hs *i2c_hs) +{ + u16 value; + int retry = 1000; + + while (retry--) { + value = reg_read(i2c_hs, HISR); + if (value & HISR_HIBB) { + udelay(1); + } else { + break; + } + } + + if (retry <= 0) { + dev_dbg(NULL, "%s: Bus Busy!\n", __func__); + return 1; + } else { + return 0; + } +} + +static int mxci2c_hs_start(mxc_i2c_hs *i2c_hs, int repeat_start, u16 address) +{ + u16 mask; + int ret = 0; + + mxci2c_hs_bus_busy(i2c_hs); + + /*7 bit address */ + reg_clear_mask(i2c_hs, HICR, HICR_ADDR_MODE); + + /*send start */ + if (repeat_start) + mask = HICR_RSTA; + else + mask = HICR_MSTA; + reg_set_mask(i2c_hs, HICR, mask); + + return ret; +} + +static int mxci2c_hs_stop(mxc_i2c_hs *i2c_hs) +{ + reg_clear_mask(i2c_hs, HICR, HICR_MSTA); + reg_clear_mask(i2c_hs, HICR, HICR_HIIEN); + + return 0; +} + +static int mxci2c_wait_writefifo(mxc_i2c_hs *i2c_hs) +{ + int i, num, left; + int retry, ret = 0; + + retry = 10000; + while (retry--) { + udelay(10); + if (reg_read(i2c_hs, HISR) & (HISR_TDE | HISR_TDC_ZERO)) { + if (i2c_hs->index < i2c_hs->msg->len) { + left = i2c_hs->msg->len - i2c_hs->index; + num = + (left > + HITFR_MAX_COUNT) ? HITFR_MAX_COUNT : left; + for (i = 0; i < num; i++) { + reg_write(i2c_hs, HITDR, + i2c_hs->msg->buf[i2c_hs-> + index + i]); + } + i2c_hs->index += num; + } else { + if (reg_read(i2c_hs, HISR) & HISR_TDC_ZERO) { + msleep(1); + break; + } + } + } + } + + if (retry <= 0) { + printk(KERN_ERR "%s:wait error\n", __func__); + ret = -1; + } + + return ret; +} + +static int mxci2c_wait_readfifo(mxc_i2c_hs *i2c_hs) +{ + int i, num, left; + int retry, ret = 0; + u16 value; + + retry = 10000; + while (retry--) { + udelay(10); + value = reg_read(i2c_hs, HISR); + if (value & (HISR_RDF | HISR_RDC_ZERO)) { + if (i2c_hs->index < i2c_hs->msg->len) { + left = i2c_hs->msg->len - i2c_hs->index; + num = + (left > + HITFR_MAX_COUNT) ? HITFR_MAX_COUNT : left; + for (i = 0; i < num; i++) { + i2c_hs->msg->buf[i2c_hs->index + i] = + reg_read(i2c_hs, HIRDR); + } + i2c_hs->index += num; + } else { + if (value & HISR_RDC_ZERO) { + break; + } + } + } + } + + if (retry <= 0) { + printk(KERN_ERR "%s:wait error\n", __func__); + ret = -1; + } + + return ret; +} + +static int mxci2c_hs_read(mxc_i2c_hs *i2c_hs, int repeat_start, + struct i2c_msg *msg) +{ + int ret; + + if (msg->len > HIRDCR_MAX_COUNT) { + printk(KERN_ERR "%s: error: msg too long, max longth 256\n", + __func__); + return -1; + } + + ret = 0; + i2c_hs->msg = msg; + i2c_hs->index = 0; + + /*set address */ + reg_write(i2c_hs, HIMADR, HIMADR_LSB_ADR(msg->addr)); + + /*receive mode */ + reg_clear_mask(i2c_hs, HICR, HICR_MTX); + + reg_clear_mask(i2c_hs, HICR, HICR_HIIEN); + + /*FIFO*/ reg_set_mask(i2c_hs, HIRFR, HIRFR_RFEN | HIRFR_RFWM(7)); + reg_set_mask(i2c_hs, HIRFR, HIRFR_RFLSH); + + /*TDCR*/ + reg_write(i2c_hs, HIRDCR, HIRDCR_RDC_EN | HIRDCR_RDC(msg->len)); + + mxci2c_hs_start(i2c_hs, repeat_start, msg->addr); + + ret = mxci2c_wait_readfifo(i2c_hs); + + if (ret < 0) + return ret; + else + return msg->len; +} + +static int mxci2c_hs_write(mxc_i2c_hs *i2c_hs, int repeat_start, + struct i2c_msg *msg) +{ + int ret, i; + + if (msg->len > HITDCR_MAX_COUNT) { + printk(KERN_ERR "%s: error: msg too long, max longth 256\n", + __func__); + return -1; + } + + ret = 0; + i2c_hs->msg = msg; + i2c_hs->index = 0; + + /*set address */ + reg_write(i2c_hs, HIMADR, HIMADR_LSB_ADR(msg->addr)); + + /*transmit mode */ + reg_set_mask(i2c_hs, HICR, HICR_MTX); + + reg_clear_mask(i2c_hs, HICR, HICR_HIIEN); + + /* TDCR */ + reg_write(i2c_hs, HITDCR, HITDCR_TDC_EN | HITDCR_TDC(msg->len)); + + /* FIFO */ + reg_set_mask(i2c_hs, HITFR, HITFR_TFEN); + reg_set_mask(i2c_hs, HITFR, HITFR_TFLSH); + + if (msg->len > HITFR_MAX_COUNT) + i2c_hs->index = HITFR_MAX_COUNT; + else { + i2c_hs->index = msg->len; + } + + for (i = 0; i < i2c_hs->index; i++) { + reg_write(i2c_hs, HITDR, msg->buf[i]); + } + + mxci2c_hs_start(i2c_hs, repeat_start, msg->addr); + + ret = mxci2c_wait_writefifo(i2c_hs); + + if (ret < 0) + return ret; + else + return msg->len; +} + +static int mxci2c_hs_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], + int num) +{ + int i; + int ret = -EIO; + + mxc_i2c_hs *i2c_hs = (mxc_i2c_hs *) (i2c_get_adapdata(adap)); + + if (i2c_hs->low_power) { + dev_err(&adap->dev, "I2C Device in low power mode\n"); + return -EREMOTEIO; + } + + if (num < 1) { + return 0; + } + + mxci2c_hs_enable(i2c_hs); + + for (i = 0; i < num; i++) { + if (msgs[i].flags & I2C_M_RD) { + ret = mxci2c_hs_read(i2c_hs, 0, &msgs[i]); + if (ret < 0) + break; + } else { + ret = mxci2c_hs_write(i2c_hs, 0, &msgs[i]); + if (ret < 0) + break; + } + mxci2c_hs_stop(i2c_hs); + } + mxci2c_hs_stop(i2c_hs); + + mxci2c_hs_disable(i2c_hs); + + if (ret < 0) + return ret; + + return i; +} + +static u32 mxci2c_hs_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +/*! + * Stores the pointers for the i2c algorithm functions. The algorithm functions + * is used by the i2c bus driver to talk to the i2c bus + */ +static struct i2c_algorithm mxci2c_hs_algorithm = { + .master_xfer = mxci2c_hs_xfer, + .functionality = mxci2c_hs_func +}; + +static int mxci2c_hs_probe(struct platform_device *pdev) +{ + mxc_i2c_hs *i2c_hs; + struct mxc_i2c_platform_data *i2c_plat_data = pdev->dev.platform_data; + struct resource *res; + int id = pdev->id; + int ret = 0; + + i2c_hs = kzalloc(sizeof(mxc_i2c_hs), GFP_KERNEL); + if (!i2c_hs) { + return -ENOMEM; + } + + i2c_hs->dev = &pdev->dev; + + i2c_hs->speed = i2c_plat_data->i2c_clk; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + ret = -ENODEV; + goto err1; + } + i2c_hs->reg_base_virt = IO_ADDRESS(res->start); + i2c_hs->reg_base_phy = res->start; + + i2c_hs->ipg_clk = clk_get(&pdev->dev, "hsi2c_clk"); + i2c_hs->serial_clk = clk_get(&pdev->dev, "hsi2c_serial_clk"); + + /* + * Request the I2C interrupt + */ + i2c_hs->irq = platform_get_irq(pdev, 0); + if (i2c_hs->irq < 0) { + ret = i2c_hs->irq; + goto err1; + } + + i2c_hs->low_power = false; + + /* + * Set the adapter information + */ + adap = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL); + if (!adap) { + ret = -ENODEV; + goto err1; + } + strlcpy(adap->name, pdev->name, 48); + adap->id = adap->nr = id; + adap->algo = &mxci2c_hs_algorithm; + adap->timeout = 1; + platform_set_drvdata(pdev, i2c_hs); + i2c_set_adapdata(adap, i2c_hs); + ret = i2c_add_numbered_adapter(adap); + if (ret < 0) { + goto err2; + } + + printk(KERN_INFO "MXC HS I2C driver\n"); + return 0; + + err2: + kfree(adap); + err1: + dev_err(&pdev->dev, "failed to probe high speed i2c adapter\n"); + kfree(i2c_hs); + return ret; +} + +static int mxci2c_hs_suspend(struct platform_device *pdev, pm_message_t state) +{ + mxc_i2c_hs *i2c_hs = platform_get_drvdata(pdev); + + if (i2c_hs == NULL) { + return -1; + } + + /* Prevent further calls to be processed */ + i2c_hs->low_power = true; + + gpio_i2c_hs_inactive(); + + return 0; +} + +static int mxci2c_hs_resume(struct platform_device *pdev) +{ + mxc_i2c_hs *i2c_hs = platform_get_drvdata(pdev); + + if (i2c_hs == NULL) + return -1; + + i2c_hs->low_power = false; + gpio_i2c_hs_active(); + + return 0; +} + +static int mxci2c_hs_remove(struct platform_device *pdev) +{ + mxc_i2c_hs *i2c_hs = platform_get_drvdata(pdev); + + i2c_del_adapter(adap); + gpio_i2c_hs_inactive(); + platform_set_drvdata(pdev, NULL); + kfree(i2c_hs); + return 0; +} + +static struct platform_driver mxci2c_hs_driver = { + .driver = { + .name = "mxc_i2c_hs", + .owner = THIS_MODULE, + }, + .probe = mxci2c_hs_probe, + .remove = mxci2c_hs_remove, + .suspend = mxci2c_hs_suspend, + .resume = mxci2c_hs_resume, +}; + +/*! + * Function requests the interrupts and registers the i2c adapter structures. + * + * @return The function returns 0 on success and a non-zero value on failure. + */ +static int __init mxci2c_hs_init(void) +{ + /* Register the device driver structure. */ + return platform_driver_register(&mxci2c_hs_driver); +} + +/*! + * This function is used to cleanup all resources before the driver exits. + */ +static void __exit mxci2c_hs_exit(void) +{ + platform_driver_unregister(&mxci2c_hs_driver); +} + +subsys_initcall(mxci2c_hs_init); +module_exit(mxci2c_hs_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC HIGH SPEED I2C driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/i2c/busses/mxc_i2c_hs_reg.h linux-2.6.26-lab126/drivers/i2c/busses/mxc_i2c_hs_reg.h --- linux-2.6.26/drivers/i2c/busses/mxc_i2c_hs_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/i2c/busses/mxc_i2c_hs_reg.h 2010-08-10 04:17:27.000000000 -0400 @@ -0,0 +1,97 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MXC_I2C_HS_REG_H__ +#define __MXC_I2C_HS_REG_H__ + +#define HISADR 0x00 + +#define HIMADR 0x04 +#define HIMADR_LSB_ADR(x) ((x) << 1) +#define HIMADR_MSB_ADR(x) (((x) & 0x7) << 8) + +#define HICR 0x08 +#define HICR_HIEN 0x1 +#define HICR_DMA_EN_RX 0x2 +#define HICR_DMA_EN_TR 0x4 +#define HICR_RSTA 0x8 +#define HICR_TXAK 0x10 +#define HICR_MTX 0x20 +#define HICR_MSTA 0x40 +#define HICR_HIIEN 0x80 +#define HICR_ADDR_MODE 0x100 +#define HICR_MST_CODE(x) (((x)&0x7) << 9) +#define HICR_HSM_EN 0x1000 +#define HICR_SAMC(x) (((x)&0x3) << 13) +#define SAMC_7_10 0 +#define SMAC_7 1 +#define SMAC_10 2 + +#define HISR 0x0c +#define HISR_RDF 0x1 +#define HISR_TDE 0x2 +#define HISR_HIAAS 0x4 +#define HISR_HIAL 0x8 +#define HISR_BTD 0x10 +#define HISR_RDC_ZERO 0x20 +#define HISR_TDC_ZERO 0x40 +#define HISR_RXAK 0x80 +#define HISR_HIBB 0x100 +#define HISR_SRW 0x200 +#define HISR_SADDR_MODE 0x400 +#define HISR_SHS_MODE 0x800 + +#define HIIMR 0x10 +#define HIIMR_RDF 0x1 +#define HIIMR_TDE 0x2 +#define HIIMR_AAS 0x4 +#define HIIMR_AL 0x8 +#define HIIMR_BTD 0x10 +#define HIIMR_RDC 0x20 +#define HIIMR_TDC 0x40 +#define HIIMR_RXAK 0x80 + +#define HITDR 0x14 + +#define HIRDR 0x18 + +#define HIFSFDR 0x1c + +#define HIHSFDR 0x20 + +#define HITFR 0x24 +#define HITFR_TFEN 0x1 +#define HITFR_TFLSH 0x2 +#define HITFR_TFWM(x) (((x) & 0x7) << 2) +#define HITFR_TFC(x) (((x) >> 8) & 0xF) +#define HITFR_MAX_COUNT 8 + +#define HIRFR 0x28 +#define HIRFR_RFEN 0x1 +#define HIRFR_RFLSH 0x2 +#define HIRFR_RFWM(x) (((x) & 0x7) << 2) +#define HIRFR_RFC(x) (((x) >> 8) & 0xF) +#define HIRFR_MAX_COUNT 8 + +#define HITDCR 0x2c +#define HITDCR_TDC(x) ((x) & 0xFF) +#define HITDCR_TDC_EN 0x100 +#define HITDCR_TDC_RSTA 0x200 +#define HITDCR_MAX_COUNT 0xFF + +#define HIRDCR 0x30 +#define HIRDCR_RDC(x) ((x) & 0xFF) +#define HIRDCR_RDC_EN 0x100 +#define HIRDCR_RDC_RSTA 0x200 +#define HIRDCR_MAX_COUNT 0xFF + +#endif diff -urN linux-2.6.26/drivers/i2c/busses/mxc_i2c_reg.h linux-2.6.26-lab126/drivers/i2c/busses/mxc_i2c_reg.h --- linux-2.6.26/drivers/i2c/busses/mxc_i2c_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/i2c/busses/mxc_i2c_reg.h 2010-08-10 04:17:27.000000000 -0400 @@ -0,0 +1,40 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MXC_I2C_REG_H__ +#define __MXC_I2C_REG_H__ + +/* Address offsets of the I2C registers */ +#define MXC_IADR 0x00 /* Address Register */ +#define MXC_IFDR 0x04 /* Freq div register */ +#define MXC_I2CR 0x08 /* Control regsiter */ +#define MXC_I2SR 0x0C /* Status register */ +#define MXC_I2DR 0x10 /* Data I/O register */ + +/* Bit definitions of I2CR */ +#define MXC_I2CR_IEN 0x0080 +#define MXC_I2CR_IIEN 0x0040 +#define MXC_I2CR_MSTA 0x0020 +#define MXC_I2CR_MTX 0x0010 +#define MXC_I2CR_TXAK 0x0008 +#define MXC_I2CR_RSTA 0x0004 + +/* Bit definitions of I2SR */ +#define MXC_I2SR_ICF 0x0080 +#define MXC_I2SR_IAAS 0x0040 +#define MXC_I2SR_IBB 0x0020 +#define MXC_I2SR_IAL 0x0010 +#define MXC_I2SR_SRW 0x0004 +#define MXC_I2SR_IIF 0x0002 +#define MXC_I2SR_RXAK 0x0001 + +#endif /* __MXC_I2C_REG_H__ */ diff -urN linux-2.6.26/drivers/i2c-slave/Kconfig linux-2.6.26-lab126/drivers/i2c-slave/Kconfig --- linux-2.6.26/drivers/i2c-slave/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/i2c-slave/Kconfig 2010-08-10 04:16:25.000000000 -0400 @@ -0,0 +1,40 @@ +# +# I2C slave subsystem configuration +# + +menuconfig I2C_SLAVE + bool "I2C Slave support" + depends on HAS_IOMEM + ---help--- + I2C (pronounce: I-square-C) is a slow serial bus protocol used in + many micro controller applications and developed by Philips. + + If you want I2C Slave support, you should say Y here. + + This I2C Slave support can also be built as a module. If so, the module + will be called i2c-slave. + +if I2C_SLAVE + +config I2C_SLAVE_CORE + tristate "I2C SLAVE CORE" + default y + ---help--- + i2c slave core. + +config MXC_I2C_SLAVE + tristate "MXC I2C SLAVE" + depends on I2C_SLAVE_CORE + default y + ---help--- + mxc i2c slave support. + +config I2C_SLAVE_CLIENT + tristate "I2C SLAVE CLIENT" + default y + ---help--- + i2c slave client that used when the master is on the same board. + this is for i2c master which is on the same board with the slave. + +endif # I2C_SLAVE + diff -urN linux-2.6.26/drivers/i2c-slave/Makefile linux-2.6.26-lab126/drivers/i2c-slave/Makefile --- linux-2.6.26/drivers/i2c-slave/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/i2c-slave/Makefile 2010-08-10 04:16:25.000000000 -0400 @@ -0,0 +1,10 @@ +# +# Makefile for the i2c slave. +# + +i2c_slave-objs := i2c_slave_ring_buffer.o i2c_slave_device.o i2c_slave_core.o +obj-$(CONFIG_I2C_SLAVE_CORE) += i2c_slave.o +obj-$(CONFIG_MXC_I2C_SLAVE) += mxc_i2c_slave.o +obj-$(CONFIG_I2C_SLAVE_CLIENT) += i2c_slave_client.o + + diff -urN linux-2.6.26/drivers/i2c-slave/i2c_slave_client.c linux-2.6.26-lab126/drivers/i2c-slave/i2c_slave_client.c --- linux-2.6.26/drivers/i2c-slave/i2c_slave_client.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/i2c-slave/i2c_slave_client.c 2010-08-10 04:16:25.000000000 -0400 @@ -0,0 +1,81 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include + +struct i2c_client *i2c_slave_client; +static int i2c_slave_client_probe(struct i2c_client *adapter); +static int i2c_slave_client_remove(struct i2c_client *client); +static struct i2c_driver i2c_slave_client_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "i2c-slave-client", + }, + .probe = i2c_slave_client_probe, + .remove = i2c_slave_client_remove, +}; + +/*! + * ov2640 I2C attach function + * + * @param adapter struct i2c_adapter * + * @return Error code indicating success or failure + */ +static int i2c_slave_client_probe(struct i2c_client *client) +{ + i2c_slave_client = client; + return 0; +} + +/*! + * ov2640 I2C detach function + * + * @param client struct i2c_client * + * @return Error code indicating success or failure + */ +static int i2c_slave_client_remove(struct i2c_client *client) +{ + return 0; +} + +/*! + * ov2640 init function + * + * @return Error code indicating success or failure + */ +static __init int i2c_slave_client_init(void) +{ + return i2c_add_driver(&i2c_slave_client_driver); +} + +/*! + * OV2640 cleanup function + * + * @return Error code indicating success or failure + */ +static void __exit i2c_slave_client_clean(void) +{ + i2c_del_driver(&i2c_slave_client_driver); +} + +module_init(i2c_slave_client_init); +module_exit(i2c_slave_client_clean); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("I2c Slave Client Driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/i2c-slave/i2c_slave_core.c linux-2.6.26-lab126/drivers/i2c-slave/i2c_slave_core.c --- linux-2.6.26/drivers/i2c-slave/i2c_slave_core.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/i2c-slave/i2c_slave_core.c 2010-08-10 04:16:25.000000000 -0400 @@ -0,0 +1,355 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include "i2c_slave_device.h" + +int i2c_slave_major; + +static ssize_t i2c_slave_read(struct file *fd, char __user *buf, size_t len, + loff_t *ptr) +{ + i2c_slave_device_t *dev; + void *kbuf; + int ret; + + if (len == 0) + return 0; + + kbuf = kmalloc(len, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + goto error0; + } + + dev = (i2c_slave_device_t *) fd->private_data; + if (!dev) { + ret = -ENODEV; + goto error1; + } + + ret = i2c_slave_device_read(dev, len, kbuf); + if (ret <= 0 || copy_to_user(buf, kbuf, len)) { + ret = -EFAULT; + } + + error1: + kfree(kbuf); + error0: + return ret; +} + +static ssize_t i2c_slave_write(struct file *fd, const char __user *buf, + size_t len, loff_t *ptr) +{ + i2c_slave_device_t *dev; + void *kbuf; + int ret; + + if (len == 0) + return 0; + + kbuf = kmalloc(len, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + goto error0; + } + if (copy_from_user(kbuf, buf, len)) { + ret = -EFAULT; + goto error1; + } + + dev = (i2c_slave_device_t *) fd->private_data; + if (!dev) { + ret = -ENODEV; + goto error1; + } + + ret = i2c_slave_device_write(dev, len, (u8 *) buf); + + error1: + kfree(kbuf); + error0: + return ret; +} + +static int i2c_slave_ioctl(struct inode *inode, struct file *fd, + unsigned code, unsigned long value) +{ + /*todo */ + return 0; +} + +static int i2c_slave_open(struct inode *inode, struct file *fd) +{ + int ret; + unsigned int id; + i2c_slave_device_t *dev; + id = iminor(inode); + + if (id >= I2C_SLAVE_DEVICE_MAX) { + ret = -ENODEV; + goto error; + } + + dev = i2c_slave_device_find(id); + if (!dev) { + ret = -ENODEV; + goto error; + } + + if (i2c_slave_device_start(dev)) { + ret = -EBUSY; + goto error; + } + + fd->private_data = (void *)dev; + ret = 0; + + error: + return ret; +} + +static int i2c_slave_release(struct inode *inode, struct file *fd) +{ + int ret; + unsigned int id; + i2c_slave_device_t *dev; + id = iminor(inode); + + if (id >= I2C_SLAVE_DEVICE_MAX) { + ret = -ENODEV; + goto error; + } + + dev = i2c_slave_device_find(id); + if (!dev) { + ret = -ENODEV; + goto error; + } + + if (i2c_slave_device_stop(dev)) { + ret = -EBUSY; + goto error; + } + + ret = 0; + + error: + return ret; +} + +static const struct file_operations i2c_slave_fops = { + .owner = THIS_MODULE, + .llseek = no_llseek, + .read = i2c_slave_read, + .write = i2c_slave_write, + .ioctl = i2c_slave_ioctl, + .open = i2c_slave_open, + .release = i2c_slave_release, +}; + +static int i2c_slave_bus_match(struct device *dev, struct device_driver *drv) +{ + return 0; +} + +/* +static int i2c_slave_bus_probe(struct device *dev) +{ + struct device_driver *driver = dev->driver; + + if (driver) { + return driver->probe(dev); + } else { + dev_err(dev, "%s: no driver\n", __func__); + return -ENODEV; + } +} +*/ + +static int i2c_slave_bus_remove(struct device *dev) +{ + struct device_driver *driver = dev->driver; + + if (driver) { + if (!driver->remove) { + return 0; + } else { + return driver->remove(dev); + } + } else { + + dev_err(dev, "%s: no driver\n", __func__); + return -ENODEV; + } +} + +static void i2c_slave_bus_shutdown(struct device *dev) +{ + struct device_driver *driver = dev->driver; + + if (driver) { + + driver->shutdown(dev); + } else { + + dev_err(dev, "%s: no driver\n", __func__); + return; + } +} +static int i2c_slave_bus_suspend(struct device *dev, pm_message_t state) +{ + struct device_driver *driver = dev->driver; + + if (driver) { + + if (!driver->suspend) { + return 0; + } else { + return driver->suspend(dev, state); + } + } else { + + dev_err(dev, "%s: no driver\n", __func__); + return -ENODEV; + } +} + +static int i2c_slave_bus_resume(struct device *dev) +{ + struct device_driver *driver = dev->driver; + + if (driver) { + + if (!driver->resume) { + return 0; + } else { + return driver->resume(dev); + } + } else { + + dev_err(dev, "%s: no driver\n", __func__); + return -ENODEV; + } +} + +struct bus_type i2c_slave_bus_type = { + .name = "i2c-slave", + .match = i2c_slave_bus_match, + .remove = i2c_slave_bus_remove, + .shutdown = i2c_slave_bus_shutdown, + .suspend = i2c_slave_bus_suspend, + .resume = i2c_slave_bus_resume, +}; + +EXPORT_SYMBOL_GPL(i2c_slave_bus_type); + +static int i2c_slave_driver_probe(struct device *dev) +{ + return 0; +} + +static int i2c_slave_driver_remove(struct device *dev) +{ + return 0; +} + +static int i2c_slave_driver_shutdown(struct device *dev) +{ + return 0; +} + +static int i2c_slave_driver_suspend(struct device *dev, pm_message_t state) +{ + return 0; +} + +static int i2c_slave_driver_resume(struct device *dev) +{ + return 0; +} + +extern struct class *i2c_slave_class; + +static struct device_driver i2c_slave_driver = { + .name = "i2c-slave", + .owner = THIS_MODULE, + .bus = &i2c_slave_bus_type, + .probe = i2c_slave_driver_probe, + .remove = i2c_slave_driver_remove, + .shutdown = i2c_slave_driver_shutdown, + .suspend = i2c_slave_driver_suspend, + .resume = i2c_slave_driver_resume, +}; + +static int __init i2c_slave_dev_init(void) +{ + int ret; + + printk(KERN_INFO "i2c slave /dev entries driver\n"); + + ret = bus_register(&i2c_slave_bus_type); + if (ret) { + printk(KERN_ERR "%s: bus_register error\n", __func__); + goto out; + } + + i2c_slave_class = class_create(THIS_MODULE, "i2c-slave"); + if (IS_ERR(i2c_slave_class)) { + pr_err("%s: class_create error\n", __func__); + goto out_unreg_bus; + } + + i2c_slave_major = register_chrdev(0, "i2c-slave", &i2c_slave_fops); + if (i2c_slave_major <= 0) { + pr_err("%s: register_chrdev error\n", __func__); + goto out_unreg_class; + } + + ret = driver_register(&i2c_slave_driver); + if (ret) { + pr_err("%s: driver_register error\n", __func__); + goto out_unreg_chrdev; + } + + return 0; + + out_unreg_chrdev: + unregister_chrdev(i2c_slave_major, "i2c-slave"); + out_unreg_class: + class_destroy(i2c_slave_class); + out_unreg_bus: + bus_unregister(&i2c_slave_bus_type); + out: + pr_err("%s: init error\n", __func__); + return ret; +} + +static void __exit i2c_dev_exit(void) +{ + driver_unregister(&i2c_slave_driver); + class_destroy(i2c_slave_class); + unregister_chrdev(i2c_slave_major, "i2c-slave"); + bus_unregister(&i2c_slave_bus_type); +} + +module_init(i2c_slave_dev_init); +module_exit(i2c_dev_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("I2C Slave Driver Core"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/i2c-slave/i2c_slave_device.c linux-2.6.26-lab126/drivers/i2c-slave/i2c_slave_device.c --- linux-2.6.26/drivers/i2c-slave/i2c_slave_device.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/i2c-slave/i2c_slave_device.c 2010-08-10 04:16:25.000000000 -0400 @@ -0,0 +1,269 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include "i2c_slave_device.h" +static i2c_slave_device_t *i2c_slave_devices[I2C_SLAVE_DEVICE_MAX]; +struct class *i2c_slave_class; +static int i2c_slave_device_get_id(void) +{ + int i; + for (i = 0; i < I2C_SLAVE_DEVICE_MAX; i++) { + if (!i2c_slave_devices[i]) + return i; + } + return -1; +} + +i2c_slave_device_t *i2c_slave_device_find(int id) +{ + if (id >= 0 && id < I2C_SLAVE_DEVICE_MAX) + return i2c_slave_devices[id]; + + else + return NULL; +} +void i2c_slave_device_set_name(i2c_slave_device_t *device, char *name) +{ + device->name = name; +} + +void i2c_slave_device_set_address(i2c_slave_device_t *device, u8 address) +{ + device->address = address; +} + +u8 i2c_slave_device_get_addr(i2c_slave_device_t *device) +{ + return device->address; +} + +int i2c_slave_device_set_freq(i2c_slave_device_t *device, u32 freq) +{ + /*TODO: freq check */ + device->scl_freq = freq; + return 0; +} + +u32 i2c_slave_device_get_freq(i2c_slave_device_t *device) +{ + return device->scl_freq; +} + +/*used by the specific i2c device to register itself to the core.*/ +i2c_slave_device_t *i2c_slave_device_alloc(void) +{ + int id; + i2c_slave_device_t *device; + id = i2c_slave_device_get_id(); + if (id < 0) { + goto error; + } + device = + (i2c_slave_device_t *) kzalloc(sizeof(i2c_slave_device_t), + GFP_KERNEL); + if (!device) { + printk(KERN_ERR "%s: alloc device error\n", __func__); + goto error_device; + } + device->receive_buffer = i2c_slave_rb_alloc(PAGE_SIZE); + if (!device->receive_buffer) { + printk(KERN_ERR "%s: alloc receive buffer error\n", __func__); + goto error_receive_buffer; + } + device->send_buffer = i2c_slave_rb_alloc(PAGE_SIZE); + if (!device->send_buffer) { + printk(KERN_ERR "%s: alloc send buffer error\n", __func__); + goto error_send_buffer; + } + device->id = id; + return device; + + error_send_buffer: + kfree(device->receive_buffer); + error_receive_buffer: + kfree((void *)device); + error_device: + pr_debug(KERN_ERR "%s: no memory\n", __func__); + error: + return 0; +} + +void i2c_slave_device_free(i2c_slave_device_t *dev) +{ + i2c_slave_rb_release(dev->receive_buffer); + i2c_slave_rb_release(dev->send_buffer); + kfree(dev); +} + +int i2c_slave_device_register(i2c_slave_device_t *device) +{ + device->dev = device_create(i2c_slave_class, NULL, + MKDEV(i2c_slave_major, device->id), + "slave-i2c-%d", device->id); + if (!device->dev) { + return -1; + } + i2c_slave_devices[device->id] = device; + return 0; +} + +void i2c_slave_device_unregister(i2c_slave_device_t *device) +{ + device_destroy(i2c_slave_class, MKDEV(i2c_slave_major, device->id)); + i2c_slave_devices[device->id] = 0; + i2c_slave_device_free(device); +} + +/* + this two functions are used by i2c slave core to start or stop the specific i2c device. +*/ +int i2c_slave_device_start(i2c_slave_device_t *device) +{ + return device->start(device); +} + +int i2c_slave_device_stop(i2c_slave_device_t *device) +{ + return device->stop(device); +} + +/* + this two functions are used by i2c slave core to get data by the specific i2c slave device + or send data to it to feed i2c master's need. + + @mod: async(1) or sync(0) mode. +*/ +int i2c_slave_device_read(i2c_slave_device_t *device, int num, u8 *data) +{ + int read_num, read_total = 0; + int step = 1000; + u8 *read_buf = data; + printk(KERN_INFO "%s: device id=%d, num=%d\n", __func__, device->id, + num); + read_num = i2c_slave_rb_consume(device->receive_buffer, num, read_buf); + read_total += read_num; + read_buf += read_num; + step--; + while ((read_total < num) && step) { + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(HZ / 10); + if (!signal_pending(current)) { + } else { + /*TODO*/ break; + } + read_num = + i2c_slave_rb_consume(device->receive_buffer, + num - read_total, read_buf); + num -= read_num; + read_buf += read_num; + step--; + } + return read_total; +} +int i2c_slave_device_write(i2c_slave_device_t *device, int num, u8 *data) +{ + int write_num, write_total = 0; + int step = 1000; + u8 *buf_index = data; + write_num = i2c_slave_rb_produce(device->send_buffer, num, buf_index); + write_total += write_num; + buf_index += write_num; + step--; + while (write_total < num && step) { + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(HZ / 10); + if (!signal_pending(current)) { + } else { + /*TODO*/ step = 0; + break; + } + write_num = + i2c_slave_rb_produce(device->send_buffer, num - write_total, + buf_index); + write_total += write_num; + buf_index += write_num; + step--; + } + while (step && i2c_slave_rb_num(device->send_buffer)) { + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(HZ / 10); + if (!signal_pending(current)) { + step--; + } else { + /*TODO*/ step = 0; + break; + } + } + if (!step) { + write_total -= i2c_slave_rb_num(device->send_buffer); + i2c_slave_rb_clear(device->send_buffer); + } + return write_total; +} + +/* + * this 2 functions used by the specific i2c slave device when they got data from master(produce), + * or is request by master(consume). + */ +int i2c_slave_device_produce(i2c_slave_device_t *device, int num, u8 *data) +{ + int ret; + ret = i2c_slave_rb_produce(device->receive_buffer, num, data); + return ret; +} +int i2c_slave_device_consume(i2c_slave_device_t *device, int num, u8 *data) +{ + return i2c_slave_rb_consume(device->send_buffer, num, data); +} + +EXPORT_SYMBOL(i2c_slave_device_set_name); +EXPORT_SYMBOL(i2c_slave_device_set_address); +EXPORT_SYMBOL(i2c_slave_device_get_addr); +EXPORT_SYMBOL(i2c_slave_device_find); +EXPORT_SYMBOL(i2c_slave_device_set_freq); +EXPORT_SYMBOL(i2c_slave_device_get_freq); + +/* +* used by the specific i2c device to register itself to the core. +*/ +EXPORT_SYMBOL(i2c_slave_device_alloc); +EXPORT_SYMBOL(i2c_slave_device_free); +EXPORT_SYMBOL(i2c_slave_device_register); +EXPORT_SYMBOL(i2c_slave_device_unregister); + +/* + this two functions are used by i2c slave core to start or stop the specific i2c device. +*/ +EXPORT_SYMBOL(i2c_slave_device_start); +EXPORT_SYMBOL(i2c_slave_device_stop); + +/* + this two functions are used by i2c slave core to get data by the specific i2c slave device + or send data to it for it to feed i2c master's need. + + @mod: async(1) or sync(0) mode. +*/ +EXPORT_SYMBOL(i2c_slave_device_read); +EXPORT_SYMBOL(i2c_slave_device_write); + +/* +* this 2 functions used by the specific i2c slave device when they got data from master, +* or is request by master. +*/ +EXPORT_SYMBOL(i2c_slave_device_produce); +EXPORT_SYMBOL(i2c_slave_device_consume); diff -urN linux-2.6.26/drivers/i2c-slave/i2c_slave_device.h linux-2.6.26-lab126/drivers/i2c-slave/i2c_slave_device.h --- linux-2.6.26/drivers/i2c-slave/i2c_slave_device.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/i2c-slave/i2c_slave_device.h 2010-08-10 04:16:25.000000000 -0400 @@ -0,0 +1,79 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __I2C_SLAVE_H__ +#define __I2C_SLAVE_H__ + +#include +#include "i2c_slave_ring_buffer.h" + +#define I2C_SLAVE_DEVICE_MAX 256 +extern int i2c_slave_major; + +typedef struct i2c_slave_device { + struct list_head list; + u8 address; + u32 scl_freq; + char *name; + i2c_slave_ring_buffer_t *receive_buffer; + i2c_slave_ring_buffer_t *send_buffer; + int (*start) (struct i2c_slave_device *); + int (*stop) (struct i2c_slave_device *); + /*int (*set_freq)(struct i2c_slave_device*); + int (*set_addr)(struct i2c_slave_device*);*/ + void *private_data; + struct device *dev; + int id; +} i2c_slave_device_t; + +/* + used by the specific device to set some infomations. +*/ +void i2c_slave_device_set_name(i2c_slave_device_t *device, char *name); +void i2c_slave_device_set_address(i2c_slave_device_t *device, u8 address); +i2c_slave_device_t *i2c_slave_device_find(int id); +u8 i2c_slave_device_get_addr(i2c_slave_device_t *device); +int i2c_slave_device_set_freq(i2c_slave_device_t *device, u32 freq); +u32 i2c_slave_device_get_freq(i2c_slave_device_t *device); + +/* +**used by the specific i2c device to register itself to the core. +*/ +i2c_slave_device_t *i2c_slave_device_alloc(void); +void i2c_slave_device_free(i2c_slave_device_t *); +int i2c_slave_device_register(i2c_slave_device_t *device); +void i2c_slave_device_unregister(i2c_slave_device_t *device); + +/* + this two functions are used by i2c slave core to start or stop the specific i2c device. +*/ +int i2c_slave_device_start(i2c_slave_device_t *device); +int i2c_slave_device_stop(i2c_slave_device_t *device); + +/* + this two functions are used by i2c slave core to get data by the specific i2c slave device + or send data to it for it to feed i2c master's need. + + @mod: async(1) or sync(0) mode. +*/ +int i2c_slave_device_read(i2c_slave_device_t *device, int num, u8 *data); +int i2c_slave_device_write(i2c_slave_device_t *device, int num, u8 *data); + +/* +*this 2 functions used by the specific i2c slave device when they got data from master, +*or is requested by master. +*/ +int i2c_slave_device_produce(i2c_slave_device_t *device, int num, u8 *data); +int i2c_slave_device_consume(i2c_slave_device_t *device, int num, u8 *data); + +#endif diff -urN linux-2.6.26/drivers/i2c-slave/i2c_slave_ring_buffer.c linux-2.6.26-lab126/drivers/i2c-slave/i2c_slave_ring_buffer.c --- linux-2.6.26/drivers/i2c-slave/i2c_slave_ring_buffer.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/i2c-slave/i2c_slave_ring_buffer.c 2010-08-10 04:16:25.000000000 -0400 @@ -0,0 +1,185 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include "i2c_slave_ring_buffer.h" + +i2c_slave_ring_buffer_t *i2c_slave_rb_alloc(int size) +{ + i2c_slave_ring_buffer_t *ring_buf; + + ring_buf = + (i2c_slave_ring_buffer_t *) kzalloc(sizeof(i2c_slave_ring_buffer_t), + GFP_KERNEL); + if (!ring_buf) { + pr_debug("%s: alloc ring_buf error\n", __func__); + goto error; + } + + ring_buf->buffer = kmalloc(size, GFP_KERNEL); + if (!ring_buf->buffer) { + pr_debug("%s: alloc buffer error\n", __func__); + goto error1; + } + + ring_buf->total = size; + + ring_buf->lock = __SPIN_LOCK_UNLOCKED(ring_buf->lock); + return ring_buf; + + error1: + kfree(ring_buf); + error: + return NULL; +} + +void i2c_slave_rb_release(i2c_slave_ring_buffer_t *ring) +{ + unsigned long flags; + + spin_lock_irqsave(ring->lock, flags); + kfree(ring->buffer); + spin_unlock_irqrestore(ring->lock, flags); + kfree(ring); +} + +int i2c_slave_rb_produce(i2c_slave_ring_buffer_t *ring, int num, char *data) +{ + int ret = 0; + unsigned long flags; + + spin_lock_irqsave(ring->lock, flags); + + if (ring->start < ring->end) { + if ((ring->start + num) < ring->end) { /*have enough space */ + memcpy(&ring->buffer[ring->start], data, num); + ring->start += num; + ret = num; + } else { /*space not enough, just copy part of it. */ + ret = ring->end - ring->start; + memcpy(&ring->buffer[ring->start], data, ret); + ring->start += ret; + ring->full = 1; + } + } else if (ring->start >= ring->end && !ring->full) { + if (ring->start + num <= ring->total) { /*space enough */ + ret = num; + memcpy(&ring->buffer[ring->start], data, ret); + ring->start += ret; + } else { /*turn ring->start around */ + ret = ring->total - ring->start; + memcpy(&ring->buffer[ring->start], data, ret); + ring->start = 0; + num -= ret; + data += ret; + if (num < ring->end) { /*space enough */ + ret += num; + memcpy(&ring->buffer[ring->start], data, num); + } else { /*space not enough, just copy part of it. */ + ret += ring->end; + memcpy(&ring->buffer[ring->start], data, + ring->end); + ring->start = ring->end; + ring->full = 1; + } + } + } else { /*(ring->data == ring->end) && ring->full ) : full */ + ret = 0; + } + + spin_unlock_irqrestore(ring->lock, flags); + return ret; +} + +int i2c_slave_rb_consume(i2c_slave_ring_buffer_t *ring, int num, char *data) +{ + int ret; + unsigned long flags; + spin_lock_irqsave(ring->lock, flags); + if (num <= 0) { + ret = 0; + goto out; + } + + if (ring->start > ring->end) { + if (num <= ring->start - ring->end) { /*enough */ + ret = num; + memcpy(data, &ring->buffer[ring->end], ret); + ring->end += ret; + } else { /*not enough */ + ret = ring->start - ring->end; + memcpy(data, &ring->buffer[ring->end], ret); + ring->end += ret; + } + } else if (ring->start < ring->end || ring->full) { + if (num <= ring->total - ring->end) { + ret = ring->total - ring->end; + memcpy(data, &ring->buffer[ring->end], ret); + ring->end += ret; + } else if (num <= ring->total - ring->end + ring->start) { + ret = ring->total - ring->end; + memcpy(data, &ring->buffer[ring->end], ret); + ring->end = 0; + data += ret; + num -= ret; + memcpy(data, &ring->buffer[ring->end], num); + ring->end = num; + ret += num; + } else { + ret = ring->total - ring->end; + memcpy(data, &ring->buffer[ring->end], ret); + ring->end = 0; + data += ret; + num -= ret; + memcpy(data, &ring->buffer[ring->end], ring->start); + ring->end = ring->start; + ret += ring->start; + } + ring->full = 0; + } else { /*empty */ + ret = 0; + } + + out: + spin_unlock_irqrestore(ring->lock, flags); + + return ret; +} + +int i2c_slave_rb_num(i2c_slave_ring_buffer_t *ring) +{ + int ret; + unsigned long flags; + spin_lock_irqsave(ring->lock, flags); + if (ring->start > ring->end) { + ret = ring->start - ring->end; + } else if (ring->start < ring->end) { + ret = ring->total - ring->end + ring->start; + } else if (ring->full) { + ret = ring->total; + } else { + ret = 0; + } + spin_unlock_irqrestore(ring->lock, flags); + return ret; +} + +void i2c_slave_rb_clear(i2c_slave_ring_buffer_t *ring) +{ + unsigned long flags; + spin_lock_irqsave(ring->lock, flags); + + ring->start = ring->end = 0; + ring->full = 0; + spin_unlock_irqrestore(ring->lock, flags); +} diff -urN linux-2.6.26/drivers/i2c-slave/i2c_slave_ring_buffer.h linux-2.6.26-lab126/drivers/i2c-slave/i2c_slave_ring_buffer.h --- linux-2.6.26/drivers/i2c-slave/i2c_slave_ring_buffer.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/i2c-slave/i2c_slave_ring_buffer.h 2010-08-10 04:16:25.000000000 -0400 @@ -0,0 +1,39 @@ +#ifndef __BUFFER_MANAGER_H__ +#define __BUFFER_MANAGER_H__ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +typedef struct i2c_slave_ring_buffer { + int start; + int end; + int total; + bool full; + char *buffer; + spinlock_t lock; +} i2c_slave_ring_buffer_t; + +i2c_slave_ring_buffer_t *i2c_slave_rb_alloc(int size); + +void i2c_slave_rb_release(i2c_slave_ring_buffer_t *ring); + +int i2c_slave_rb_produce(i2c_slave_ring_buffer_t *ring, int num, char *data); + +int i2c_slave_rb_consume(i2c_slave_ring_buffer_t *ring, int num, char *data); + +int i2c_slave_rb_num(i2c_slave_ring_buffer_t *ring); + +void i2c_slave_rb_clear(i2c_slave_ring_buffer_t *ring); + +#endif diff -urN linux-2.6.26/drivers/i2c-slave/mxc_i2c_slave.c linux-2.6.26-lab126/drivers/i2c-slave/mxc_i2c_slave.c --- linux-2.6.26/drivers/i2c-slave/mxc_i2c_slave.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/i2c-slave/mxc_i2c_slave.c 2010-08-10 04:16:25.000000000 -0400 @@ -0,0 +1,329 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "i2c_slave_device.h" +#include "mxc_i2c_slave.h" +#include "mxc_i2c_slave_reg.h" + +struct mxc_i2c_slave_clk { + int reg_value; + int div; +}; + +static const struct mxc_i2c_slave_clk i2c_clk_table[] = { + {0x20, 22}, {0x21, 24}, {0x22, 26}, {0x23, 28}, + {0, 30}, {1, 32}, {0x24, 32}, {2, 36}, + {0x25, 36}, {0x26, 40}, {3, 42}, {0x27, 44}, + {4, 48}, {0x28, 48}, {5, 52}, {0x29, 56}, + {6, 60}, {0x2A, 64}, {7, 72}, {0x2B, 72}, + {8, 80}, {0x2C, 80}, {9, 88}, {0x2D, 96}, + {0xA, 104}, {0x2E, 112}, {0xB, 128}, {0x2F, 128}, + {0xC, 144}, {0xD, 160}, {0x30, 160}, {0xE, 192}, + {0x31, 192}, {0x32, 224}, {0xF, 240}, {0x33, 256}, + {0x10, 288}, {0x11, 320}, {0x34, 320}, {0x12, 384}, + {0x35, 384}, {0x36, 448}, {0x13, 480}, {0x37, 512}, + {0x14, 576}, {0x15, 640}, {0x38, 640}, {0x16, 768}, + {0x39, 768}, {0x3A, 896}, {0x17, 960}, {0x3B, 1024}, + {0x18, 1152}, {0x19, 1280}, {0x3C, 1280}, {0x1A, 1536}, + {0x3D, 1536}, {0x3E, 1792}, {0x1B, 1920}, {0x3F, 2048}, + {0x1C, 2304}, {0x1D, 2560}, {0x1E, 3072}, {0x1F, 3840}, + {0, 0} +}; + +extern void gpio_i2c_active(int i2c_num); +extern void gpio_i2c_inactive(int i2c_num); + +static irqreturn_t interrupt_handler(int irq, void *dev_id) +{ + u16 status, ctl; + int num; + u16 data; + struct mxc_i2c_slave_device *mxc_i2c = + (struct mxc_i2c_slave_device *)dev_id; + + status = readw(mxc_i2c->reg_base + MXC_I2SR); + ctl = readw(mxc_i2c->reg_base + MXC_I2CR); + + dev_dbg(mxc_i2c->dev->dev, "status=%x, ctl=%x\n", status, ctl); + + if (status & MXC_I2SR_IAAS) { + if (status & MXC_I2SR_SRW) { + /*slave send */ + num = + i2c_slave_device_consume(mxc_i2c->dev, 1, + (u8 *) &data); + if (num < 1) { + /*FIXME:not ready to send data */ + printk(KERN_ERR + " i2c-slave:%s:data not ready\n", + __func__); + } else { + ctl |= MXC_I2CR_MTX; + writew(ctl, mxc_i2c->reg_base + MXC_I2CR); + /*send data */ + writew(data, mxc_i2c->reg_base + MXC_I2DR); + } + + } else { + /*slave receive */ + ctl &= ~MXC_I2CR_MTX; + writew(ctl, mxc_i2c->reg_base + MXC_I2CR); + + /*dummy read */ + data = readw(mxc_i2c->reg_base + MXC_I2DR); + } + } else { + /*slave send */ + if (ctl & MXC_I2CR_MTX) { + if (!(status & MXC_I2SR_RXAK)) { /*ACK received */ + num = + i2c_slave_device_consume(mxc_i2c->dev, 1, + (u8 *) &data); + if (num < 1) { + /*FIXME:not ready to send data */ + printk(KERN_ERR + " i2c-slave:%s:data not ready\n", + __func__); + } else { + ctl |= MXC_I2CR_MTX; + writew(ctl, + mxc_i2c->reg_base + MXC_I2CR); + writew(data, + mxc_i2c->reg_base + MXC_I2DR); + } + } else { + /*no ACK. */ + /*dummy read */ + ctl &= ~MXC_I2CR_MTX; + writew(ctl, mxc_i2c->reg_base + MXC_I2CR); + data = readw(mxc_i2c->reg_base + MXC_I2DR); + } + } else { /*read */ + ctl &= ~MXC_I2CR_MTX; + writew(ctl, mxc_i2c->reg_base + MXC_I2CR); + + /*read */ + data = readw(mxc_i2c->reg_base + MXC_I2DR); + i2c_slave_device_produce(mxc_i2c->dev, 1, + (u8 *) &data); + } + + } + + writew(0x0, mxc_i2c->reg_base + MXC_I2SR); + + return IRQ_HANDLED; +} + +static int start(i2c_slave_device_t *device) +{ + volatile unsigned int cr; + unsigned int addr; + struct mxc_i2c_slave_device *mxc_dev; + + mxc_dev = (struct mxc_i2c_slave_device *)device->private_data; + if (!mxc_dev) { + dev_err(device->dev, "%s: get mxc_dev error\n", __func__); + return -ENODEV; + } + + clk_enable(mxc_dev->clk); + /* Set the frequency divider */ + writew(mxc_dev->clkdiv, mxc_dev->reg_base + MXC_IFDR); + + /* Set the Slave bit */ + cr = readw(mxc_dev->reg_base + MXC_I2CR); + cr &= (!MXC_I2CR_MSTA); + writew(cr, mxc_dev->reg_base + MXC_I2CR); + + /*Set Slave Address */ + addr = mxc_dev->dev->address << 1; + writew(addr, mxc_dev->reg_base + MXC_IADR); + + /* Clear the status register */ + writew(0x0, mxc_dev->reg_base + MXC_I2SR); + + /* Enable I2C and its interrupts */ + writew(MXC_I2CR_IEN, mxc_dev->reg_base + MXC_I2CR); + writew(MXC_I2CR_IEN | MXC_I2CR_IIEN, mxc_dev->reg_base + MXC_I2CR); + + return 0; + +} + +static int stop(i2c_slave_device_t *device) +{ + struct mxc_i2c_slave_device *mxc_dev; + + mxc_dev = (struct mxc_i2c_slave_device *)device->private_data; + + writew(0x0, mxc_dev->reg_base + MXC_I2CR); + clk_disable(mxc_dev->clk); + + return 0; +} + +static int mxc_i2c_slave_probe(struct platform_device *pdev) +{ + int i; + u32 clk_freq; + struct resource *res; + struct mxc_i2c_slave_device *mxc_dev; + + mxc_dev = kzalloc(sizeof(struct mxc_i2c_slave_device), GFP_KERNEL); + if (!mxc_dev) { + goto error0; + } + mxc_dev->dev = i2c_slave_device_alloc(); + if (mxc_dev->dev == 0) { + dev_err(&pdev->dev, "%s: i2c_slave_device_alloc error\n", + __func__); + goto error1; + } + + i2c_slave_device_set_address(mxc_dev->dev, MXC_I2C_SLAVE_ADDRESS); + i2c_slave_device_set_freq(mxc_dev->dev, MXC_I2C_SLAVE_FREQ); + i2c_slave_device_set_name(mxc_dev->dev, MXC_I2C_SLAVE_NAME); + mxc_dev->dev->start = start; + mxc_dev->dev->stop = stop; + + mxc_dev->dev->private_data = mxc_dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "%s: get resource error\n", __func__); + goto error2; + } + mxc_dev->reg_base = IO_ADDRESS(res->start); + + mxc_dev->irq = platform_get_irq(pdev, 0); + if (mxc_dev->irq < 0) { + dev_err(&pdev->dev, "%s: get irq error\n", __func__); + goto error2; + } + if (request_irq(mxc_dev->irq, interrupt_handler, + 0, mxc_dev->dev->name, mxc_dev) < 0) { + dev_err(&pdev->dev, "%s: request_irq error\n", __func__); + goto error2; + } + + /*i2c id on soc */ + mxc_dev->id = pdev->id; + + gpio_i2c_active(mxc_dev->id); + + /*clock */ + mxc_dev->clk = clk_get(&pdev->dev, "i2c_clk"); + clk_freq = clk_get_rate(mxc_dev->clk); + mxc_dev->clkdiv = -1; + if (mxc_dev->dev->scl_freq) { + /* Calculate divider and round up any fractional part */ + int div = (clk_freq + mxc_dev->dev->scl_freq - 1) / + mxc_dev->dev->scl_freq; + for (i = 0; i2c_clk_table[i].div != 0; i++) { + if (i2c_clk_table[i].div >= div) { + mxc_dev->clkdiv = i2c_clk_table[i].reg_value; + break; + } + } + } + if (mxc_dev->clkdiv == -1) { + i--; + mxc_dev->clkdiv = 0x1F; /* Use max divider */ + } + dev_dbg(&pdev->dev, + "i2c slave speed is %d/%d = %d bps, reg val = 0x%02X\n", + clk_freq, i2c_clk_table[i].div, clk_freq / i2c_clk_table[i].div, + mxc_dev->clkdiv); + + if (i2c_slave_device_register(mxc_dev->dev) < 0) { + dev_err(&pdev->dev, "%s: i2c_slave_device_register error\n", + __func__); + goto error3; + } + + platform_set_drvdata(pdev, (void *)mxc_dev); + + /*start(mxc_dev->dev); */ + return 0; + + error3: + error2: + i2c_slave_device_free(mxc_dev->dev); + error1: + kfree(mxc_dev); + error0: + return -ENODEV; +} + +static int mxc_i2c_slave_remove(struct platform_device *pdev) +{ + struct mxc_i2c_slave_device *mxc_dev; + mxc_dev = (struct mxc_i2c_slave_device *)platform_get_drvdata(pdev); + + i2c_slave_device_unregister(mxc_dev->dev); + kfree((void *)mxc_dev); + + return 0; +} + +static int mxc_i2c_slave_suspend(struct platform_device *pdev, + pm_message_t state) +{ + return 0; +} + +static int mxc_i2c_slave_resume(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver mxci2c_slave_driver = { + .driver = { + .name = "mxc_i2c_slave", + .owner = THIS_MODULE, + }, + .probe = mxc_i2c_slave_probe, + .remove = mxc_i2c_slave_remove, + .suspend = mxc_i2c_slave_suspend, + .resume = mxc_i2c_slave_resume, +}; + +static int __init mxc_i2c_slave_init(void) +{ + /* Register the device driver structure. */ + return platform_driver_register(&mxci2c_slave_driver); +} + +/*! + * This function is used to cleanup all resources before the driver exits. + */ +static void __exit mxc_i2c_slave_exit(void) +{ + platform_driver_unregister(&mxci2c_slave_driver); +} + +module_init(mxc_i2c_slave_init); +module_exit(mxc_i2c_slave_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC I2C Slave Driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/i2c-slave/mxc_i2c_slave.h linux-2.6.26-lab126/drivers/i2c-slave/mxc_i2c_slave.h --- linux-2.6.26/drivers/i2c-slave/mxc_i2c_slave.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/i2c-slave/mxc_i2c_slave.h 2010-08-10 04:16:25.000000000 -0400 @@ -0,0 +1,44 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MXC_I2C_SLAVE_H__ +#define __MXC_I2C_SLAVE_H__ + +#include +#include "i2c_slave_device.h" + +#define MXC_I2C_SLAVE_NAME "MXC_I2C_SLAVE" +#define MXC_I2C_SLAVE_ADDRESS 0x55 +#define MXC_I2C_SLAVE_FREQ 1000*100 + +struct mxc_i2c_slave_device { + /*! + * The default clock divider value to be used. + */ + unsigned int clkdiv; + + /*! + * The clock source for the device. + */ + struct clk *clk; + + /*i2c id on soc */ + int id; + + int irq; + unsigned long reg_base; + bool state; /*0:stop, 1:start */ + i2c_slave_device_t *dev; +}; + +#endif diff -urN linux-2.6.26/drivers/i2c-slave/mxc_i2c_slave_reg.h linux-2.6.26-lab126/drivers/i2c-slave/mxc_i2c_slave_reg.h --- linux-2.6.26/drivers/i2c-slave/mxc_i2c_slave_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/i2c-slave/mxc_i2c_slave_reg.h 2010-08-10 04:16:25.000000000 -0400 @@ -0,0 +1,41 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MXC_I2C_SLAVE_REG_H__ +#define __MXC_I2C_SLAVE_REG_H__ + +/* Address offsets of the I2C registers */ +#define MXC_IADR 0x00 /* Address Register */ +#define MXC_IFDR 0x04 /* Freq div register */ +#define MXC_I2CR 0x08 /* Control regsiter */ +#define MXC_I2SR 0x0C /* Status register */ +#define MXC_I2DR 0x10 /* Data I/O register */ + +/* Bit definitions of I2CR */ +#define MXC_I2CR_IEN 0x0080 +#define MXC_I2CR_IIEN 0x0040 +#define MXC_I2CR_MSTA 0x0020 +#define MXC_I2CR_MTX 0x0010 +#define MXC_I2CR_TXAK 0x0008 +#define MXC_I2CR_RSTA 0x0004 + +/* Bit definitions of I2SR */ +#define MXC_I2SR_ICF 0x0080 +#define MXC_I2SR_IAAS 0x0040 +#define MXC_I2SR_IBB 0x0020 +#define MXC_I2SR_IAL 0x0010 +#define MXC_I2SR_SRW 0x0004 +#define MXC_I2SR_IIF 0x0002 +#define MXC_I2SR_RXAK 0x0001 + +#endif /* __MXC_I2C_REG_H__ */ diff -urN linux-2.6.26/drivers/ide/Kconfig linux-2.6.26-lab126/drivers/ide/Kconfig --- linux-2.6.26/drivers/ide/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/ide/Kconfig 2010-08-10 04:17:14.000000000 -0400 @@ -830,6 +830,14 @@ Say Y here if you want to support the onboard IDE channels on the Simtec BAST or the Thorcom VR1000 +config BLK_DEV_IDE_MXC + tristate "Freescale MXC IDE support" + depends on ARM && ( ARCH_MX3 || ARCH_MX27 || ARCH_MX37) + select BLK_DEV_IDEDMA + help + Say Y here if you want to support the IDE controller on the + Freescale iMX3 processor. + config IDE_H8300 tristate "H8300 IDE support" depends on H8300 diff -urN linux-2.6.26/drivers/ide/arm/Makefile linux-2.6.26-lab126/drivers/ide/arm/Makefile --- linux-2.6.26/drivers/ide/arm/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/ide/arm/Makefile 2010-08-10 04:17:13.000000000 -0400 @@ -2,6 +2,7 @@ obj-$(CONFIG_BLK_DEV_IDE_ICSIDE) += icside.o obj-$(CONFIG_BLK_DEV_IDE_RAPIDE) += rapide.o obj-$(CONFIG_BLK_DEV_IDE_BAST) += bast-ide.o +obj-$(CONFIG_BLK_DEV_IDE_MXC) += mxc_ide.o obj-$(CONFIG_BLK_DEV_PALMCHIP_BK3710) += palm_bk3710.o ifeq ($(CONFIG_IDE_ARM), m) diff -urN linux-2.6.26/drivers/ide/arm/mxc_ide.c linux-2.6.26-lab126/drivers/ide/arm/mxc_ide.c --- linux-2.6.26/drivers/ide/arm/mxc_ide.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/ide/arm/mxc_ide.c 2010-08-10 04:17:13.000000000 -0400 @@ -0,0 +1,1350 @@ +/* + * linux/drivers/ide/arm/mxc_ide.c + * + * Based on Simtec BAST IDE driver + * Copyright (c) 2003-2004 Simtec Electronics + * Ben Dooks + * + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/*! + * @file mxc_ide.c + * + * @brief ATA driver + * + * @ingroup ATA + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "mxc_ide.h" + +extern void gpio_ata_active(void); +extern void gpio_ata_inactive(void); +static int mxc_ide_config_drive(ide_drive_t * drive, u8 xfer_mode); +static void mxc_ide_dma_callback(void *arg, int error, unsigned int count); + +static struct clk *ata_clk; + +/* List of registered interfaces */ +static ide_hwif_t *ifs[1]; + +/* + * This structure contains the timing parameters for + * ATA bus timing in the 5 PIO modes. The timings + * are in nanoseconds, and are converted to clock + * cycles before being stored in the ATA controller + * timing registers. + */ +static struct { + short t0, t1, t2_8, t2_16, t2i, t4, t9, tA; +} pio_specs[] = { + [0] = { + .t0 = 600,.t1 = 70,.t2_8 = 290,.t2_16 = 165,.t2i = 0,.t4 = + 30,.t9 = 20,.tA = 50},[1] = { + .t0 = 383,.t1 = 50,.t2_8 = 290,.t2_16 = 125,.t2i = 0,.t4 = + 20,.t9 = 15,.tA = 50},[2] = { + .t0 = 240,.t1 = 30,.t2_8 = 290,.t2_16 = 100,.t2i = 0,.t4 = + 15,.t9 = 10,.tA = 50},[3] = { + .t0 = 180,.t1 = 30,.t2_8 = 80,.t2_16 = 80,.t2i = 0,.t4 = + 10,.t9 = 10,.tA = 50},[4] = { + .t0 = 120,.t1 = 25,.t2_8 = 70,.t2_16 = 70,.t2i = 0,.t4 = + 10,.t9 = 10,.tA = 50} +}; + +#define NR_PIO_SPECS (sizeof pio_specs / sizeof pio_specs[0]) + +/* + * This structure contains the timing parameters for + * ATA bus timing in the 3 MDMA modes. The timings + * are in nanoseconds, and are converted to clock + * cycles before being stored in the ATA controller + * timing registers. + */ +static struct { + short t0M, tD, tH, tJ, tKW, tM, tN, tJNH; +} mdma_specs[] = { + [0] = { + .t0M = 480,.tD = 215,.tH = 20,.tJ = 20,.tKW = 215,.tM = 50,.tN = + 15,.tJNH = 20},[1] = { + .t0M = 150,.tD = 80,.tH = 15,.tJ = 5,.tKW = 50,.tM = 30,.tN = + 10,.tJNH = 15},[2] = { + .t0M = 120,.tD = 70,.tH = 10,.tJ = 5,.tKW = 25,.tM = 25,.tN = + 10,.tJNH = 10} +}; + +#define NR_MDMA_SPECS (sizeof mdma_specs / sizeof mdma_specs[0]) + +/* + * This structure contains the timing parameters for + * ATA bus timing in the 6 UDMA modes. The timings + * are in nanoseconds, and are converted to clock + * cycles before being stored in the ATA controller + * timing registers. + */ +static struct { + short t2CYC, tCYC, tDS, tDH, tDVS, tDVH, tCVS, tCVH, tFS_min, tLI_max, + tMLI, tAZ, tZAH, tENV_min, tSR, tRFS, tRP, tACK, tSS, tDZFS; +} udma_specs[] = { + [0] = { + .t2CYC = 235,.tCYC = 114,.tDS = 15,.tDH = 5,.tDVS = 70,.tDVH = + 6,.tCVS = 70,.tCVH = 6,.tFS_min = 0,.tLI_max = + 100,.tMLI = 20,.tAZ = 10,.tZAH = 20,.tENV_min = + 20,.tSR = 50,.tRFS = 75,.tRP = 160,.tACK = 20,.tSS = + 50,.tDZFS = 80},[1] = { + .t2CYC = 156,.tCYC = 75,.tDS = 10,.tDH = 5,.tDVS = 48,.tDVH = + 6,.tCVS = 48,.tCVH = 6,.tFS_min = 0,.tLI_max = + 100,.tMLI = 20,.tAZ = 10,.tZAH = 20,.tENV_min = + 20,.tSR = 30,.tRFS = 70,.tRP = 125,.tACK = 20,.tSS = + 50,.tDZFS = 63},[2] = { + .t2CYC = 117,.tCYC = 55,.tDS = 7,.tDH = 5,.tDVS = 34,.tDVH = + 6,.tCVS = 34,.tCVH = 6,.tFS_min = 0,.tLI_max = + 100,.tMLI = 20,.tAZ = 10,.tZAH = 20,.tENV_min = + 20,.tSR = 20,.tRFS = 60,.tRP = 100,.tACK = 20,.tSS = + 50,.tDZFS = 47},[3] = { + /* + * change tDVS from 20 to 30 since the "drive ready, + * seek complete, bad crc error" + */ + .t2CYC = 86, .tCYC = 39, .tDS = 7, .tDH = 5, .tDVS = 30, .tDVH = + 6,.tCVS = 20,.tCVH = 6,.tFS_min = 0,.tLI_max = + 100,.tMLI = 20,.tAZ = 10,.tZAH = 20,.tENV_min = + 20,.tSR = 20,.tRFS = 60,.tRP = 100,.tACK = 20,.tSS = + 50,.tDZFS = 35},[4] = { + .t2CYC = 57,.tCYC = 25,.tDS = 5,.tDH = 5,.tDVS = 7,.tDVH = + 6,.tCVS = 7,.tCVH = 6,.tFS_min = 0,.tLI_max = + 100,.tMLI = 20,.tAZ = 10,.tZAH = 20,.tENV_min = + 20,.tSR = 50,.tRFS = 60,.tRP = 100,.tACK = 20,.tSS = + 50,.tDZFS = 25},[5] = { + .t2CYC = 38,.tCYC = 17,.tDS = 4,.tDH = 5,.tDVS = 5,.tDVH = + 6,.tCVS = 10,.tCVH = 10,.tFS_min = 0,.tLI_max = + 75,.tMLI = 20,.tAZ = 10,.tZAH = 20,.tENV_min = + 20,.tSR = 20,.tRFS = 50,.tRP = 85,.tACK = 20,.tSS = + 50,.tDZFS = 40} +}; + +#define NR_UDMA_SPECS (sizeof udma_specs / sizeof udma_specs[0]) + +/*! + * Calculate values for the ATA bus timing registers and store + * them into the hardware. + * + * @param mode Selects PIO, MDMA or UDMA modes + * + * @param speed Specifies the sub-mode number + * + * @return EINVAL speed out of range, or illegal mode + */ +static int set_ata_bus_timing(int speed, enum ata_mode mode) +{ + /* get the bus clock cycle time, in ns */ + int T = 1 * 1000 * 1000 * 1000 / clk_get_rate(ata_clk); + mxc_ide_time_cfg_t cfg0, cfg1, cfg2, cfg3, cfg4, cfg5; + /* every mode gets the same t_off and t_on */ + + GET_TIME_CFG(&cfg0, MXC_IDE_TIME_OFF); + cfg0.bytes.field1 = 3; + cfg0.bytes.field2 = 3; + SET_TIME_CFG(&cfg0, 3, MXC_IDE_TIME_OFF); + + switch (mode) { + case PIO: + if (speed < 0 || speed >= NR_PIO_SPECS) { + return -EINVAL; + } + cfg0.bytes.field3 = (pio_specs[speed].t1 + T) / T; + cfg0.bytes.field4 = (pio_specs[speed].t2_8 + T) / T; + + cfg1.bytes.field1 = (pio_specs[speed].t2_8 + T) / T; + cfg1.bytes.field2 = (pio_specs[speed].tA + T) / T + 2; + cfg1.bytes.field3 = 1; + cfg1.bytes.field4 = (pio_specs[speed].t4 + T) / T; + + GET_TIME_CFG(&cfg2, MXC_IDE_TIME_9); + cfg2.bytes.field1 = (pio_specs[speed].t9 + T) / T; + + SET_TIME_CFG(&cfg0, 0x0C, MXC_IDE_TIME_OFF); + SET_TIME_CFG(&cfg1, 0x0F, MXC_IDE_TIME_2r); + SET_TIME_CFG(&cfg2, 0x01, MXC_IDE_TIME_9); + break; + case MDMA: + if (speed < 0 || speed >= NR_MDMA_SPECS) { + return -EINVAL; + } + GET_TIME_CFG(&cfg2, MXC_IDE_TIME_9); + GET_TIME_CFG(&cfg3, MXC_IDE_TIME_K); + + cfg2.bytes.field2 = (mdma_specs[speed].tM + T) / T; + cfg2.bytes.field3 = (mdma_specs[speed].tJNH + T) / T; + cfg2.bytes.field4 = (mdma_specs[speed].tD + T) / T; + + cfg3.bytes.field1 = (mdma_specs[speed].tKW + T) / T; + + SET_TIME_CFG(&cfg2, 0x0E, MXC_IDE_TIME_9); + SET_TIME_CFG(&cfg3, 0x01, MXC_IDE_TIME_K); + break; + case UDMA: + if (speed < 0 || speed >= NR_UDMA_SPECS) { + return -EINVAL; + } + + GET_TIME_CFG(&cfg3, MXC_IDE_TIME_K); + + cfg3.bytes.field2 = (udma_specs[speed].tACK + T) / T; + cfg3.bytes.field3 = (udma_specs[speed].tENV_min + T) / T; + cfg3.bytes.field4 = (udma_specs[speed].tRP + T) / T + 2; + + cfg4.bytes.field1 = (udma_specs[speed].tZAH + T) / T; + cfg4.bytes.field2 = (udma_specs[speed].tMLI + T) / T; + cfg4.bytes.field3 = (udma_specs[speed].tDVH + T) / T + 1; + cfg4.bytes.field4 = (udma_specs[speed].tDZFS + T) / T; + + cfg5.bytes.field1 = (udma_specs[speed].tDVS + T) / T; + cfg5.bytes.field2 = (udma_specs[speed].tCVH + T) / T; + cfg5.bytes.field3 = (udma_specs[speed].tSS + T) / T; + cfg5.bytes.field4 = (udma_specs[speed].tCYC + T) / T; + + SET_TIME_CFG(&cfg3, 0x0E, MXC_IDE_TIME_K); + SET_TIME_CFG(&cfg4, 0x0F, MXC_IDE_TIME_ZAH); + SET_TIME_CFG(&cfg5, 0x0F, MXC_IDE_TIME_DVS); + break; + default: + return -EINVAL; + } + return 0; +} + +/*! + * Placeholder for code to make any hardware tweaks + * necessary to select a drive. Currently we are + * not aware of any. + */ +static void mxc_ide_selectproc(ide_drive_t * drive) +{ +} + +/*! + * Hardware-specific interrupt service routine for the ATA driver, + * called mainly just to dismiss the interrupt at the hardware, and + * to indicate whether there actually was an interrupt pending. + * + * The generic IDE related interrupt handling is done by the IDE layer. + */ +static int mxc_ide_ack_intr(struct hwif_s *hw) +{ + unsigned char status = ATA_RAW_READ(MXC_IDE_INTR_PENDING); + unsigned char enable = ATA_RAW_READ(MXC_IDE_INTR_ENABLE); + + /* + * The only interrupts we can actually dismiss are the FIFO conditions. + * INTRQ comes from the bus, and must be dismissed according to IDE + * protocol, which will be done by the IDE layer, even when DMA + * is invovled (DMA can see it, but can't dismiss it). + */ + ATA_RAW_WRITE(status, MXC_IDE_INTR_CLEAR); + + if (status & enable & ~MXC_IDE_INTR_ATA_INTRQ2) { + printk(KERN_ERR "mxc_ide_ack_intr: unexpected interrupt, " + "status=0x%02X\n", status); + } + + return status ? 1 : 0; +} + +/*! + * Decodes the specified transfer mode and sets both timing and ultra modes + * + * @param drive Specifies the drive + * + * @param xfer_mode Specifies the desired transfer mode + * + * @return EINVAL Illegal mode specified + */ +static void mxc_ide_set_speed(ide_drive_t *drive, u8 xfer_mode) +{ + mxc_ide_private_t *priv = (mxc_ide_private_t *) HWIF(drive)->hwif_data; + + switch (xfer_mode) { + case XFER_UDMA_7: + case XFER_UDMA_6: + case XFER_UDMA_5: + case XFER_UDMA_4: + case XFER_UDMA_3: + case XFER_UDMA_2: + case XFER_UDMA_1: + case XFER_UDMA_0: + priv->ultra = 1; + set_ata_bus_timing(xfer_mode - XFER_UDMA_0, UDMA); + break; + case XFER_MW_DMA_2: + case XFER_MW_DMA_1: + case XFER_MW_DMA_0: + priv->ultra = 0; + set_ata_bus_timing(xfer_mode - XFER_MW_DMA_0, MDMA); + break; + case XFER_PIO_4: + case XFER_PIO_3: + case XFER_PIO_2: + case XFER_PIO_1: + case XFER_PIO_0: + set_ata_bus_timing(xfer_mode - XFER_PIO_0, PIO); + break; + } + + return; +} + +/*! + * Called when the IDE layer is disabling DMA on a drive. + * + * @param drive Specifies the drive + */ +static void mxc_ide_dma_off_quietly(ide_drive_t * drive) +{ + drive->using_dma = 0; +} + +/*! + * Called by the IDE layer when something goes wrong + * + * @param drive Specifies the drive + * + */ +static void mxc_ide_resetproc(ide_drive_t * drive) +{ + pr_info("%s: resetting ATA controller\n", __func__); + + ATA_RAW_WRITE(0x00, MXC_IDE_ATA_CONTROL); + udelay(100); + ATA_RAW_WRITE(MXC_IDE_CTRL_ATA_RST_B, MXC_IDE_ATA_CONTROL); + udelay(100); +} + +/*! + * Turn on DMA for a drive. + * + * @param drive Specifies the drive + * + * @return 0 if successful + */ +static int mxc_ide_dma_on(ide_drive_t * drive) +{ + int rc = 0; + + /* consult the list of known "bad" drives */ + if (__ide_dma_bad_drive(drive)) + return 1; + + /* + * Go to UDMA3 mode. Beyond that you'll no doubt + * need an Ultra-100 cable (the 80 pin type with + * ground leads between all the signals) + */ + rc = mxc_ide_config_drive(drive, XFER_UDMA_3); + pr_info("%s: enabling UDMA3 mode %s\n", drive->name, + rc == 0 ? "success" : "failed"); + drive->using_dma = 1; + + blk_queue_max_hw_segments(drive->queue, MXC_IDE_DMA_BD_NR); + blk_queue_max_hw_segments(drive->queue, MXC_IDE_DMA_BD_NR); + blk_queue_max_segment_size(drive->queue, MXC_IDE_DMA_BD_SIZE_MAX); + + HWIF(drive)->dma_host_on(drive); + return 0; +} + +/*! + * Turn on DMA if the drive can handle it. + * + * @param drive Specifies the drive + * + * @return 0 if successful + */ +static int mxc_ide_dma_check(ide_drive_t * drive) +{ + struct hd_driveid *id = drive->id; + if (id && (id->capability & 1)) { + /* + * Enable DMA on any drive that has + * UltraDMA (mode 0/1/2/3/4/5/6) enabled + */ + if ((id->field_valid & 4) && ((id->dma_ultra >> 8) & 0x7f)) + return HWIF(drive)->ide_dma_on(drive); + /* + * Enable DMA on any drive that has mode2 DMA + * (multi or single) enabled + */ + if (id->field_valid & 2) /* regular DMA */ + if ((id->dma_mword & 0x404) == 0x404 || + (id->dma_1word & 0x404) == 0x404) + return HWIF(drive)->ide_dma_on(drive); + + /* Consult the list of known "good" drives */ + return HWIF(drive)->ide_dma_on(drive); + } + HWIF(drive)->dma_off_quietly(drive); + return 0; +} + +/*! + * The DMA is done, and the drive is done. We'll check the BD array for + * errors, and unmap the scatter-gather list. + * + * @param drive The drive we're servicing + * + * @return 0 means all is well, others means DMA signalled an error , + */ +static int mxc_ide_dma_end(ide_drive_t * drive) +{ + ide_hwif_t *hwif = HWIF(drive); + mxc_ide_private_t *priv = (mxc_ide_private_t *) hwif->hwif_data; + int dma_stat = priv->dma_stat; + + BUG_ON(drive->waiting_for_dma == 0); + drive->waiting_for_dma = 0; + + /* + * We'll unmap the sg table regardless of status. + */ + dma_unmap_sg(priv->dev, hwif->sg_table, hwif->sg_nents, + hwif->sg_dma_direction); + + return dma_stat; +} + +/*! + * The end-of-DMA interrupt handler + * + * @param drive Specifies the drive + * + * @return ide_stopped or ide_started + */ +static ide_startstop_t mxc_ide_dma_intr(ide_drive_t * drive) +{ + u8 stat, dma_stat; + struct request *rq = HWGROUP(drive)->rq; + ide_hwif_t *hwif = HWIF(drive); + u8 fifo_fill; + + if (!rq) + return ide_stopped; + + fifo_fill = ATA_RAW_READ(MXC_IDE_FIFO_FILL); + BUG_ON(fifo_fill); + + dma_stat = hwif->ide_dma_end(drive); + stat = hwif->INB(IDE_STATUS_REG); /* get drive status */ + if (OK_STAT(stat, DRIVE_READY, drive->bad_wstat | DRQ_STAT)) { + if (dma_stat == MXC_DMA_DONE) { + ide_end_request(drive, 1, rq->nr_sectors); + return ide_stopped; + } + printk(KERN_ERR "%s: mxc_ide_dma_intr: bad DMA status (0x%x)\n", + drive->name, dma_stat); + } + + return ide_error(drive, "mxc_ide_dma_intr", stat); +} + +/*! + * Directs the IDE INTRQ signal to DMA or to the CPU + * + * @param hwif Specifies the IDE controller + * + * @param which \b INTRQ_DMA or \b INTRQ_MCU + * + */ +static void mxc_ide_set_intrq(ide_hwif_t * hwif, intrq_which_t which) +{ + mxc_ide_private_t *priv = (mxc_ide_private_t *) hwif->hwif_data; + unsigned char enable = ATA_RAW_READ(MXC_IDE_INTR_ENABLE); + + switch (which) { + case INTRQ_DMA: + enable &= ~MXC_IDE_INTR_ATA_INTRQ2; + enable |= MXC_IDE_INTR_ATA_INTRQ1; + break; + case INTRQ_MCU: + enable &= ~MXC_IDE_INTR_ATA_INTRQ1; + enable |= MXC_IDE_INTR_ATA_INTRQ2; + break; + } + priv->enable = enable; + + ATA_RAW_WRITE(enable, MXC_IDE_INTR_ENABLE); +} + +/*! + * Helper routine to configure drive speed + * + * @param drive Specifies the drive + * + * @param xfer_mode Specifies the desired transfer mode + * + * @return 0 = success, non-zero otherwise + */ +static int mxc_ide_config_drive(ide_drive_t * drive, u8 xfer_mode) +{ + int err; + ide_hwif_t *hwif = HWIF(drive); + mxc_ide_private_t *priv = (mxc_ide_private_t *) (hwif->hwif_data); + u8 prev = priv->enable; + + mxc_ide_set_speed(drive, xfer_mode); + + /* + * Work around an ADS hardware bug: + * + * OK, ide_config_drive_speed() is the right thing to call but it's + * going to leave an interrupt pending. We have to jump through hoops + * because the ADS board doesn't correctly terminate INTRQ. Instead + * of pulling it low, it pulls it high (asserted), so when the drive + * tri-states it, the MX31 sees it as an interrupt. So we'll disable + * the hardware interrupt here, and restore it a bit later, after we've + * selected the drive again and let it drive INTRQ low for a bit. + * + * On later ADS boards, when presumably the correct INTRQ termination + * is in place, these extra hoops won't be necessary, but they + * shouldn't hurt, either. + */ + priv->enable = 0; + ATA_RAW_WRITE(0, MXC_IDE_INTR_ENABLE); + + err = ide_config_drive_speed(drive, xfer_mode); + + if (ATA_RAW_READ(MXC_IDE_INTR_PENDING) & + (MXC_IDE_INTR_ATA_INTRQ2 | MXC_IDE_INTR_ATA_INTRQ1)) { + /* + * OK, the 'bad thing' is happening, so we'll clear nIEN to + * get the drive to drive INTRQ, then we'll read status to + * clear any pending interrupt. This sequence gets us by + * the spurious and stuck interrupt we see otherwise. + */ + SELECT_DRIVE(drive); + udelay(2); + hwif->OUTB(0, IDE_CONTROL_REG); + udelay(2); + hwif->INB(IDE_STATUS_REG); + udelay(2); + } + + priv->enable = prev; + ATA_RAW_WRITE(prev, MXC_IDE_INTR_ENABLE); + + return err; +} + +/*! + * Masks drive interrupts temporarily at the hardware level + * + * @param drive Specifies the drive + * + * @param mask 1 = disable interrupts, 0 = re-enable + * + */ +static void mxc_ide_maskproc(ide_drive_t * drive, int mask) +{ + mxc_ide_private_t *priv = + (mxc_ide_private_t *) (HWIF(drive)->hwif_data); + BUG_ON(!priv); + + if (mask) { + ATA_RAW_WRITE(0, MXC_IDE_INTR_ENABLE); + } else { + ATA_RAW_WRITE(priv->enable, MXC_IDE_INTR_ENABLE); + } +} + +/*! + * DMA completion callback routine. This gets called after the DMA request + * has completed or aborted.All we need to do here is return ownership of + * the drive's INTRQ signal back to the CPU, which will immediately raise + * the interrupt to the IDE layer. + * + * @param arg The drive we're servicing + * @param error The error number of DMA transfer. + * @param count The transfered length. + */ +static void mxc_ide_dma_callback(void *arg, int error, unsigned int count) +{ + ide_hwif_t *hwif = HWIF((ide_drive_t *) arg); + mxc_ide_private_t *priv = (mxc_ide_private_t *) (hwif->hwif_data); + unsigned long fifo_fill; + + /* + * clean the fifo if the fill register is non-zero. + * If the fill register is non-zero, it is incorrect state. + */ + fifo_fill = ATA_RAW_READ(MXC_IDE_FIFO_FILL); + while (fifo_fill) { + ATA_RAW_READ(MXC_IDE_FIFO_DATA_32); + fifo_fill = ATA_RAW_READ(MXC_IDE_FIFO_FILL); + } + + priv->dma_stat = error; + /* + * Redirect ata_intrq back to us instead of the DMA. + */ + mxc_ide_set_intrq(hwif, INTRQ_MCU); +} + +/*! + * DMA set up. This is called once per DMA request to the drive. It delivers + * the scatter-gather list into the DMA channel and prepares both the ATA + * controller and the DMA engine for the DMA + * transfer. + * + * @param drive The drive we're servicing + * + * @return 0 on success, non-zero otherwise + */ +static int mxc_ide_dma_setup(ide_drive_t * drive) +{ + struct request *rq = HWGROUP(drive)->rq; + ide_hwif_t *hwif = HWIF(drive); + struct scatterlist *sg = hwif->sg_table; + mxc_ide_private_t *priv = (mxc_ide_private_t *) hwif->hwif_data; + int dma_ultra = priv->ultra ? MXC_IDE_CTRL_DMA_ULTRA : 0; + int dma_mode = 0; + int chan; + u8 ata_control; + u8 fifo_fill; + + BUG_ON(!rq); + BUG_ON(!priv); + BUG_ON(drive->waiting_for_dma); + + /*Initialize the dma state */ + priv->dma_stat = MXC_DMA_TRANSFER_ERROR; + + /* + * Prepare the ATA controller for the DMA + */ + if (rq_data_dir(rq)) { + chan = priv->dma_write_chan; + ata_control = MXC_IDE_CTRL_FIFO_RST_B | + MXC_IDE_CTRL_ATA_RST_B | + MXC_IDE_CTRL_FIFO_TX_EN | + MXC_IDE_CTRL_DMA_PENDING | + dma_ultra | MXC_IDE_CTRL_DMA_WRITE; + + dma_mode = DMA_MODE_WRITE; + } else { + chan = priv->dma_read_chan; + ata_control = MXC_IDE_CTRL_FIFO_RST_B | + MXC_IDE_CTRL_ATA_RST_B | + MXC_IDE_CTRL_FIFO_RCV_EN | + MXC_IDE_CTRL_DMA_PENDING | dma_ultra; + + dma_mode = DMA_MODE_READ; + } + + /* + * Set up the DMA interrupt callback + */ + mxc_dma_callback_set(chan, mxc_ide_dma_callback, (void *)drive); + + /* + * If the ATA FIFO isn't empty, we shouldn't even be here + */ + fifo_fill = ATA_RAW_READ(MXC_IDE_FIFO_FILL); + BUG_ON(fifo_fill); // $$$ TODO: need better recovery here + + ide_map_sg(drive, rq); + + hwif->sg_dma_direction = rq_data_dir(rq) ? DMA_TO_DEVICE : + DMA_FROM_DEVICE; + + hwif->sg_nents = dma_map_sg(priv->dev, sg, hwif->sg_nents, + hwif->sg_dma_direction); + BUG_ON(!hwif->sg_nents); + BUG_ON(hwif->sg_nents > MXC_IDE_DMA_BD_NR); + + mxc_dma_sg_config(chan, sg, hwif->sg_nents, 0, dma_mode); + + ATA_RAW_WRITE(ata_control, MXC_IDE_ATA_CONTROL); + ATA_RAW_WRITE(MXC_IDE_DMA_WATERMARK / 2, MXC_IDE_FIFO_ALARM); + + /* + * Route ata_intrq to the DMA engine, and not to us. + */ + mxc_ide_set_intrq(hwif, INTRQ_DMA); + + /* + * The DMA and ATA controller are ready to go. + * mxc_ide_dma_start() will start the DMA transfer, + * and mxc_ide_dma_exec_cmd() will tickle the drive, which + * actually initiates the DMA transfer on the ATA bus. + * The ATA controller is DMA slave for both read and write. + */ + BUG_ON(drive->waiting_for_dma); + drive->waiting_for_dma = 1; + + return 0; +} + +/*! + * DMA timeout notification. This gets called when the IDE layer above + * us times out waiting for a request. + * + * @param drive The drive we're servicing + * + * @return 0 to attempt recovery, otherwise, an additional tick count + * to keep waiting + */ +static int mxc_ide_dma_timer_expiry(ide_drive_t * drive) +{ + printk(KERN_ERR "%s: fifo_fill=%d\n", drive->name, + readb(MXC_IDE_FIFO_FILL)); + + mxc_ide_resetproc(NULL); + + if (drive->waiting_for_dma) { + HWIF(drive)->ide_dma_end(drive); + } + + return 0; +} + +/*! + * Called by the IDE layer to start a DMA request on the specified drive. + * The request has already been prepared by \b mxc_ide_dma_setup(). All + * we need to do is pass the command through while specifying our timeout + * handler. + * + * @param drive The drive we're servicing + * + * @param cmd The IDE command for the drive + * + */ +static void mxc_ide_dma_exec_cmd(ide_drive_t * drive, u8 cmd) +{ + ide_execute_command(drive, cmd, mxc_ide_dma_intr, 2 * WAIT_CMD, + mxc_ide_dma_timer_expiry); +} + +/*! + * Called by the IDE layer to start the DMA controller. The request has + * already been prepared by \b mxc_ide_dma_setup(). All we do here + * is tickle the DMA channel. + * + * @param drive The drive we're servicing + * + */ +static void mxc_ide_dma_start(ide_drive_t * drive) +{ + struct request *rq = HWGROUP(drive)->rq; + ide_hwif_t *hwif = HWIF(drive); + mxc_ide_private_t *priv = (mxc_ide_private_t *) hwif->hwif_data; + int chan = rq_data_dir(rq) ? priv->dma_write_chan : priv->dma_read_chan; + + BUG_ON(chan < 0); + + /* + * Tickle the DMA channel. This starts the channel, but it is likely + * that DMA will yield and go idle before the DMA request arrives from + * the drive. Nonetheless, at least the context will be hot. + */ + mxc_dma_enable(chan); +} + +/*! + * There is a race between the DMA interrupt and the timeout interrupt. This + * gets called during the IDE layer's timeout interrupt to see if the DMA + * interrupt has also occured or is pending. + * + * @param drive The drive we're servicing + * + * @return 1 means there is a DMA interrupt pending, 0 otherwise + */ +static int mxc_ide_dma_test_irq(ide_drive_t * drive) +{ + unsigned char status = ATA_RAW_READ(MXC_IDE_INTR_PENDING); + + /* + * We need to test the interrupt status without dismissing any. + */ + + return status & (MXC_IDE_INTR_ATA_INTRQ1 + | MXC_IDE_INTR_ATA_INTRQ2) ? 1 : 0; +} + +/*! + * Called to turn off DMA on this drive's controller, such as when a DMA error + * occured and the IDE layer wants to fail back to PIO mode. We won't do + * anything special, leaving the DMA channel allocated for future attempts. + * + * @param drive The drive we're servicing + */ +static void mxc_ide_dma_host_off(ide_drive_t * drive) +{ +} + +/*! + * Called to turn on DMA on this drive's controller. + * + * @param drive The drive we're servicing + */ +static void mxc_ide_dma_host_on(ide_drive_t * drive) +{ +} + +/*! + * Called for special handling on timeouts. + * + * @param drive The drive we're servicing + * + * @return 0 if successful, non-zero otherwise + */ +static void mxc_ide_dma_timeout(ide_drive_t *drive) +{ + return; +} + +/*! + * Called for special handling on lost irq's. + * + * @param drive The drive we're servicing + * + * @return 0 if successful, non-zero otherwise + */ +static void mxc_ide_dma_lost_irq(ide_drive_t *drive) +{ + return; +} + +/*! + * Called once per controller to set up DMA + * + * @param hwif Specifies the IDE controller + * + */ +static void mxc_ide_dma_init(ide_hwif_t * hwif) +{ + mxc_ide_private_t *priv = (mxc_ide_private_t *) hwif->hwif_data; + + hwif->dmatable_cpu = NULL; + hwif->dmatable_dma = 0; + hwif->set_dma_mode = mxc_ide_set_speed; + hwif->set_pio_mode = mxc_ide_set_speed; + hwif->resetproc = mxc_ide_resetproc; + + /* + * Allocate and setup the DMA channels + */ + priv->dma_read_chan = mxc_dma_request(MXC_DMA_ATA_RX, "MXC ATA RX"); + if (priv->dma_read_chan < 0) { + printk(KERN_ERR "%s: couldn't get RX DMA channel\n", + hwif->name); + goto err_out; + } + + priv->dma_write_chan = mxc_dma_request(MXC_DMA_ATA_TX, "MXC ATA TX"); + if (priv->dma_write_chan < 0) { + printk(KERN_ERR "%s: couldn't get TX DMA channel\n", + hwif->name); + goto err_out; + } + + pr_info("%s: read chan=%d , write chan=%d \n", + hwif->name, priv->dma_read_chan, priv->dma_write_chan); + + set_ata_bus_timing(0, UDMA); + + /* + * All ready now + */ + hwif->ultra_mask = 0x7f; + hwif->mwdma_mask = 0x07; + hwif->swdma_mask = 0x07; + + hwif->dma_off_quietly = mxc_ide_dma_off_quietly; + hwif->ide_dma_on = mxc_ide_dma_on; + hwif->dma_setup = mxc_ide_dma_setup; + hwif->dma_exec_cmd = mxc_ide_dma_exec_cmd; + hwif->dma_start = mxc_ide_dma_start; + hwif->ide_dma_end = mxc_ide_dma_end; + hwif->ide_dma_test_irq = mxc_ide_dma_test_irq; + hwif->dma_host_off = mxc_ide_dma_host_off; + hwif->dma_host_on = mxc_ide_dma_host_on; + hwif->dma_timeout = mxc_ide_dma_timeout; + hwif->dma_lost_irq = mxc_ide_dma_lost_irq; + + hwif->hwif_data = (void *)priv; + return; + + err_out: + if (priv->dma_read_chan >= 0) + mxc_dma_free(priv->dma_read_chan); + if (priv->dma_write_chan >= 0) + mxc_dma_free(priv->dma_write_chan); + kfree(priv); + return; +} + +/*! + * MXC-specific IDE registration helper routine. Among other things, + * we tell the IDE layer where our standard IDE drive registers are, + * through the \b io_ports array. The IDE layer sends commands to and + * reads status directly from attached IDE drives through these drive + * registers. + * + * @param base Base address of memory mapped IDE standard drive registers + * + * @param aux Address of the auxilliary ATA control register + * + * @param irq IRQ number for our hardware + * + * @param hwifp Pointer to hwif structure to be updated by the IDE layer + * + * @param priv Pointer to private structure + * + * @return ENODEV if no drives are present, 0 otherwise + */ +static int __init +mxc_ide_register(unsigned long base, unsigned int aux, int irq, + ide_hwif_t ** hwifp, mxc_ide_private_t * priv) +{ + int i = 0; + hw_regs_t hw; + ide_hwif_t *hwif = &ide_hwifs[0]; + const int regsize = 4; + + memset(&hw, 0, sizeof(hw)); + + for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { + hw.io_ports[i] = (unsigned long)base; + base += regsize; + } + hw.io_ports[IDE_CONTROL_OFFSET] = aux; + hw.irq = irq; + hw.ack_intr = &mxc_ide_ack_intr; + + *hwifp = hwif; + ide_register_hw(&hw, NULL, 0, hwifp); + + hwif->selectproc = &mxc_ide_selectproc; + hwif->maskproc = &mxc_ide_maskproc; + hwif->hwif_data = (void *)priv; + hwif->pio_mask = ATA_PIO4; + mxc_ide_set_intrq(hwif, INTRQ_MCU); + + /* + * The IDE layer will set hwif->present if we have devices attached, + * if we don't, discard the interface reset the ports. + */ + if (!hwif->present) { + pr_info("ide%d: Bus empty, interface released.\n", hwif->index); + for (i = IDE_DATA_OFFSET; i <= IDE_CONTROL_OFFSET; ++i) + hwif->io_ports[i] = 0; + hwif->chipset = ide_unknown; + hwif->noprobe = 1; + return -ENODEV; + } + + mxc_ide_dma_init(hwif); + + for (i = 0; i < MAX_DRIVES; i++) { + mxc_ide_dma_check(hwif->drives + i); + } + + return 0; +} + +/*! + * This function is called to put the ATA in a low power state. Refer to the + * document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which ATA + * device to suspend + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int mxc_ide_suspend(struct platform_device *pdev, pm_message_t state) +{ + ide_hwif_t *hwif = &ide_hwifs[0]; + mxc_ide_private_t *priv = (mxc_ide_private_t *) (hwif->hwif_data); + + /* + * Disable hardware interrupts. + * Be carefully, the system would halt if there is no pwr supply + */ + if (priv->attached == 1) + ATA_RAW_WRITE(0, MXC_IDE_INTR_ENABLE); + + if (priv->dma_read_chan >= 0) { + mxc_dma_disable(priv->dma_read_chan); + mxc_dma_free(priv->dma_read_chan); + } + if (priv->dma_write_chan >= 0) { + mxc_dma_disable(priv->dma_write_chan); + mxc_dma_free(priv->dma_write_chan); + } + + /* + * Turn off the power + */ + /* There is a HDD disk attached on the ata bus */ + if (priv->attached == 1) { + /* power off the ATA pwr supply */ + if (priv->regulator_drive) + regulator_disable(priv->regulator_drive); + if (priv->regulator_io) + regulator_disable(priv->regulator_io); + gpio_ata_inactive(); + } + + return 0; +} + +static int mxc_ide_resume(struct platform_device *pdev) +{ + ide_hwif_t *hwif = &ide_hwifs[0]; + mxc_ide_private_t *priv = (mxc_ide_private_t *) (hwif->hwif_data); + + /* There is a HDD disk attached on the ata bus */ + if (priv->attached == 1) { + /* Select group B pins, and enable the interface */ + gpio_ata_active(); + /* power up the ATA pwr supply */ + if (priv->regulator_drive) { + if (regulator_enable(priv->regulator_drive)) + printk(KERN_ERR "enable power_drive error.\n"); + } + if (priv->regulator_io) { + if (regulator_enable(priv->regulator_io)) + printk(KERN_ERR "enable power_io error.\n"); + } + + /* Deassert the reset bit to enable the interface */ + ATA_RAW_WRITE(MXC_IDE_CTRL_ATA_RST_B, MXC_IDE_ATA_CONTROL); + + /* Set initial timing and mode */ + set_ata_bus_timing(4, PIO); + + /* Reset the interface */ + mxc_ide_resetproc(NULL); + } + + priv->dma_read_chan = mxc_dma_request(MXC_DMA_ATA_RX, "MXC ATA RX"); + if (priv->dma_read_chan < 0) { + printk(KERN_ERR "%s: couldn't get RX DMA channel\n", + hwif->name); + return -EAGAIN; + } + priv->dma_write_chan = mxc_dma_request(MXC_DMA_ATA_TX, "MXC ATA TX"); + if (priv->dma_write_chan < 0) { + if (priv->dma_read_chan > 0) + mxc_dma_free(priv->dma_read_chan); + + printk(KERN_ERR "%s: couldn't get TX DMA channel\n", + hwif->name); + return -EAGAIN; + } + + return 0; +} + +/*! + * Driver initialization routine. Prepares the hardware for ATA activity. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions. + * + * @return The function returns 0 on successful. + * Otherwise returns specific error code. + */ +static int mxc_ide_probe(struct platform_device *pdev) +{ + int index = 0; + mxc_ide_private_t *priv; + struct mxc_ide_platform_data *ide_plat = pdev->dev.platform_data; + struct regulator *regulator_drive, *regulator_io; + + pr_info("MXC: IDE driver, (c) 2004-2008 Freescale Semiconductor\n"); + + if (!ide_plat) + return -EINVAL; + + ata_clk = clk_get(NULL, "ata_clk"); + if (ata_clk) { + if (clk_enable(ata_clk)) { + printk(KERN_ERR "enable clk error.\n"); + goto ERR_NODEV; + } + } else { + printk(KERN_ERR "MXC: IDE driver, can't get clk\n"); + goto ERR_NODEV; + } + + ATA_RAW_WRITE(MXC_IDE_CTRL_ATA_RST_B, MXC_IDE_ATA_CONTROL); + + /* Select group B pins, and enable the interface */ + gpio_ata_active(); + + /* + * Enable the power to HDD + */ + if (ide_plat->power_drive != NULL) { + regulator_drive = regulator_get(&pdev->dev, + ide_plat->power_drive); + if (IS_ERR(regulator_drive)) { + printk(KERN_ERR "MXC: IDE driver, can't get power\n"); + goto ERR_NODEV; + } else { + if (regulator_enable(regulator_drive)) { + printk(KERN_ERR "enable regulator error.\n"); + goto ERR_NODEV; + } + msleep(100); + } + } else + regulator_drive = NULL; + + if (ide_plat->power_io != NULL) { + regulator_io = regulator_get(&pdev->dev, ide_plat->power_io); + if (IS_ERR(regulator_io)) { + printk(KERN_ERR "MXC: IDE driver, can't get power\n"); + goto ERR_NODEV; + } else { + if (regulator_enable(regulator_io)) { + printk(KERN_ERR "enable regulator error.\n"); + goto ERR_NODEV; + } + msleep(100); + } + } else + regulator_io = NULL; + + /* Set initial timing and mode */ + + set_ata_bus_timing(4, PIO); + + /* Reset the interface */ + + mxc_ide_resetproc(NULL); + + /* + * Enable hardware interrupts. + * INTRQ2 goes to us, so we enable it here, but we'll need to ignore + * it when DMA is doing the transfer. + */ + ATA_RAW_WRITE(MXC_IDE_INTR_ATA_INTRQ2, MXC_IDE_INTR_ENABLE); + + /* + * Allocate a private structure + */ + priv = (mxc_ide_private_t *) kmalloc(sizeof *priv, GFP_KERNEL); + if (priv == NULL) { + ATA_RAW_WRITE(0, MXC_IDE_INTR_ENABLE); + if (regulator_drive) { + regulator_disable(regulator_drive); + regulator_put(regulator_drive, &pdev->dev); + } + if (regulator_io) { + regulator_disable(regulator_io); + regulator_put(regulator_io, &pdev->dev); + } + gpio_ata_inactive(); + goto ERR_NOMEM; + } + + memset(priv, 0, sizeof *priv); + priv->dev = NULL; // dma_map_sg() ignores it anyway + priv->dma_read_chan = -1; + priv->dma_write_chan = -1; + priv->attached = 1; + + /* + * Now register + */ + + index = + mxc_ide_register(IDE_ARM_IO, IDE_ARM_CTL, IDE_ARM_IRQ, &ifs[0], + priv); + if (index < 0) { + printk(KERN_ERR "Unable to register the MXC IDE driver\n"); + ATA_RAW_WRITE(0, MXC_IDE_INTR_ENABLE); + + /* + * If there is no hdd disk, turn off the clock and power + */ + /* Poweroff the HDD */ + clk_disable(ata_clk); + clk_put(ata_clk); + priv->attached = 0; + if (regulator_drive) { + regulator_disable(regulator_drive); + regulator_put(regulator_drive, &pdev->dev); + } + if (regulator_io) { + regulator_disable(regulator_io); + regulator_put(regulator_io, &pdev->dev); + } + gpio_ata_inactive(); + kfree(priv); + goto ERR_NODEV; + } +#ifdef ATA_USE_IORDY + /* turn on IORDY protocol */ + + udelay(25); + ATA_RAW_WRITE(MXC_IDE_CTRL_ATA_RST_B | MXC_IDE_CTRL_IORDY_EN, + MXC_IDE_ATA_CONTROL); +#endif + priv->regulator_drive = regulator_drive; + priv->regulator_io = regulator_io; + return 0; + + ERR_NODEV: + return -ENODEV; + ERR_NOMEM: + return -ENOMEM; + +} + +/*! + * Driver exit routine. Clean up. + * + * @param pdev the device structure used to give information on which ATA + * to remove + * + * @return The function always returns 0. + */ +static int mxc_ide_remove(struct platform_device *pdev) +{ + ide_hwif_t *hwif = ifs[0]; + mxc_ide_private_t *priv; + + BUG_ON(!hwif); + priv = (mxc_ide_private_t *) hwif->hwif_data; + BUG_ON(!priv); + + ide_unregister(hwif->index); + + /* + * Disable hardware interrupts. + */ + if (priv->attached) + ATA_RAW_WRITE(0, MXC_IDE_INTR_ENABLE); + /* + * Deallocate DMA channels. Free's BDs and everything. + */ + if (priv->dma_read_chan >= 0) + mxc_dma_free(priv->dma_read_chan); + if (priv->dma_write_chan >= 0) + mxc_dma_free(priv->dma_write_chan); + + /* + * Turn off the clock + */ + clk_disable(ata_clk); + clk_put(ata_clk); + + /* + * Disable the interface + * Free the pins + */ + gpio_ata_inactive(); + + /* + * Turn off the power + */ + /* Disable power supply */ + if (priv->attached) { + priv->attached = 0; + if (priv->regulator_drive) { + regulator_disable(priv->regulator_drive); + regulator_put((priv->regulator_drive), &pdev->dev); + } + if (priv->regulator_io) { + regulator_disable(priv->regulator_io); + regulator_put((priv->regulator_io), &pdev->dev); + } + } + + /* + * Free the private structure. + */ + kfree(priv); + hwif->hwif_data = NULL; + + return 0; +} + +/*! + * MXC IDE host operations structure. + * These functions are registered with IDE/ATA Bus protocol driver. + */ +static struct platform_driver mxc_ide_driver = { + .driver = { + .name = "mxc_ide", + }, + .probe = mxc_ide_probe, + .remove = mxc_ide_remove, + .suspend = mxc_ide_suspend, + .resume = mxc_ide_resume, +}; + +/*! + * This function is used to initialize the IDE driver module. The function + * registers the power management callback functions with the kernel and also + * registers the IDE callback functions with the core ATA driver. + * + * @return The function returns 0 on success and a non-zero value on failure. + */ +static int __init mxc_ide_init(void) +{ + return platform_driver_register(&mxc_ide_driver); +} + +/*! + * This function is used to cleanup all resources before the driver exits. + */ +static void __exit mxc_ide_exit(void) +{ + platform_driver_unregister(&mxc_ide_driver); +} + +module_init(mxc_ide_init); +module_exit(mxc_ide_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION + ("Freescale MXC IDE (based on Simtec BAST IDE driver by Ben Dooks )"); diff -urN linux-2.6.26/drivers/ide/arm/mxc_ide.h linux-2.6.26-lab126/drivers/ide/arm/mxc_ide.h --- linux-2.6.26/drivers/ide/arm/mxc_ide.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/ide/arm/mxc_ide.h 2010-08-10 04:17:13.000000000 -0400 @@ -0,0 +1,198 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef _MXC_IDE_H_ +#define _MXC_IDE_H_ + +/*! + * @defgroup ATA ATA/IDE Driver + */ + +/*! + * @file mxc_ide.h + * + * @brief MXC ATA/IDE hardware register and bit definitions. + * + * @ingroup ATA + */ + +#define IDE_ARM_IO IO_ADDRESS((ATA_BASE_ADDR + 0xA0) ) +#define IDE_ARM_CTL IO_ADDRESS((ATA_BASE_ADDR + 0xD8) ) +#define IDE_ARM_IRQ MXC_INT_ATA + +/* + * Interface control registers + */ + +#define MXC_IDE_FIFO_DATA_32 IO_ADDRESS((ATA_BASE_ADDR + 0x18) ) +#define MXC_IDE_FIFO_DATA_16 IO_ADDRESS((ATA_BASE_ADDR + 0x1C) ) +#define MXC_IDE_FIFO_FILL IO_ADDRESS((ATA_BASE_ADDR + 0x20) ) +#define MXC_IDE_ATA_CONTROL IO_ADDRESS((ATA_BASE_ADDR + 0x24) ) +#define MXC_IDE_INTR_PENDING IO_ADDRESS((ATA_BASE_ADDR + 0x28) ) +#define MXC_IDE_INTR_ENABLE IO_ADDRESS((ATA_BASE_ADDR + 0x2C) ) +#define MXC_IDE_INTR_CLEAR IO_ADDRESS((ATA_BASE_ADDR + 0x30) ) +#define MXC_IDE_FIFO_ALARM IO_ADDRESS((ATA_BASE_ADDR + 0x34) ) + +/* + * Control register bit definitions + */ + +#define MXC_IDE_CTRL_FIFO_RST_B 0x80 +#define MXC_IDE_CTRL_ATA_RST_B 0x40 +#define MXC_IDE_CTRL_FIFO_TX_EN 0x20 +#define MXC_IDE_CTRL_FIFO_RCV_EN 0x10 +#define MXC_IDE_CTRL_DMA_PENDING 0x08 +#define MXC_IDE_CTRL_DMA_ULTRA 0x04 +#define MXC_IDE_CTRL_DMA_WRITE 0x02 +#define MXC_IDE_CTRL_IORDY_EN 0x01 + +/* + * Interrupt registers bit definitions + */ + +#define MXC_IDE_INTR_ATA_INTRQ1 0x80 +#define MXC_IDE_INTR_FIFO_UNDERFLOW 0x40 +#define MXC_IDE_INTR_FIFO_OVERFLOW 0x20 +#define MXC_IDE_INTR_CTRL_IDLE 0x10 +#define MXC_IDE_INTR_ATA_INTRQ2 0x08 + +/* + * timing registers + */ + +#define MXC_IDE_TIME_OFF IO_ADDRESS((ATA_BASE_ADDR + 0x00) ) +#define MXC_IDE_TIME_ON IO_ADDRESS((ATA_BASE_ADDR + 0x01) ) +#define MXC_IDE_TIME_1 IO_ADDRESS((ATA_BASE_ADDR + 0x02) ) +#define MXC_IDE_TIME_2w IO_ADDRESS((ATA_BASE_ADDR + 0x03) ) + +#define MXC_IDE_TIME_2r IO_ADDRESS((ATA_BASE_ADDR + 0x04) ) +#define MXC_IDE_TIME_AX IO_ADDRESS((ATA_BASE_ADDR + 0x05) ) +#define MXC_IDE_TIME_PIO_RDX IO_ADDRESS((ATA_BASE_ADDR + 0x06) ) +#define MXC_IDE_TIME_4 IO_ADDRESS((ATA_BASE_ADDR + 0x07) ) + +#define MXC_IDE_TIME_9 IO_ADDRESS((ATA_BASE_ADDR + 0x08) ) +#define MXC_IDE_TIME_M IO_ADDRESS((ATA_BASE_ADDR + 0x09) ) +#define MXC_IDE_TIME_JN IO_ADDRESS((ATA_BASE_ADDR + 0x0A) ) +#define MXC_IDE_TIME_D IO_ADDRESS((ATA_BASE_ADDR + 0x0B) ) + +#define MXC_IDE_TIME_K IO_ADDRESS((ATA_BASE_ADDR + 0x0C) ) +#define MXC_IDE_TIME_ACK IO_ADDRESS((ATA_BASE_ADDR + 0x0D) ) +#define MXC_IDE_TIME_ENV IO_ADDRESS((ATA_BASE_ADDR + 0x0E) ) +#define MXC_IDE_TIME_RPX IO_ADDRESS((ATA_BASE_ADDR + 0x0F) ) + +#define MXC_IDE_TIME_ZAH IO_ADDRESS((ATA_BASE_ADDR + 0x10) ) +#define MXC_IDE_TIME_MLIX IO_ADDRESS((ATA_BASE_ADDR + 0x11) ) +#define MXC_IDE_TIME_DVH IO_ADDRESS((ATA_BASE_ADDR + 0x12) ) +#define MXC_IDE_TIME_DZFS IO_ADDRESS((ATA_BASE_ADDR + 0x13) ) + +#define MXC_IDE_TIME_DVS IO_ADDRESS((ATA_BASE_ADDR + 0x14) ) +#define MXC_IDE_TIME_CVH IO_ADDRESS((ATA_BASE_ADDR + 0x15) ) +#define MXC_IDE_TIME_SS IO_ADDRESS((ATA_BASE_ADDR + 0x16) ) +#define MXC_IDE_TIME_CYC IO_ADDRESS((ATA_BASE_ADDR + 0x17) ) + +/* + * other facts + */ +#define MXC_IDE_FIFO_SIZE 64 /* DMA FIFO size in halfwords */ +#define MXC_IDE_DMA_BD_SIZE_MAX 0xFC00 /* max size of scatterlist segment */ + +/*! Private data for the drive structure. */ +typedef struct { + struct device *dev; /*!< The device */ + int dma_read_chan; /*!< DMA channel sdma api gave us for reads */ + int dma_write_chan; /*!< DMA channel sdma api gave us for writes */ + int ultra; /*!< Remember when we're in ultra mode */ + int dma_stat; /*!< the state of DMA request */ + u8 enable; /*!< Current hardware interrupt mask */ + u8 attached; /*!< device attached or not */ + struct regulator *regulator_drive; + struct regulator *regulator_io; +} mxc_ide_private_t; + +/*! ATA transfer mode for set_ata_bus_timing() */ +enum ata_mode { + PIO, /*!< Specifies PIO mode */ + MDMA, /*!< Specifies MDMA mode */ + UDMA /*!< Specifies UDMA mode */ +}; + +/*! + * The struct defines the interrupt type which will issued by interrupt singal. + */ +typedef enum { + /*! Enable ATA_INTRQ on the CPU */ + INTRQ_MCU, + + /*! Enable ATA_INTRQ on the DMA engine */ + INTRQ_DMA +} intrq_which_t; + +/*! defines the structure for timing configurations */ + +/*! + * This structure defines the bits in the ATA TIME_CONFIGx + */ +typedef union { + unsigned long config; /* the 32bits fields in TIME_CONFIGx */ + struct { + unsigned char field1; /* the 8bits field for 8bits accessing */ + unsigned char field2; /* the 8bits field for 8bits accessing */ + unsigned char field3; /* the 8bits field for 8bits accessing */ + unsigned char field4; /* the 8bits field for 8bits accessing */ + } bytes; /* the 8bits fields in TIME_CONFIGx */ +} mxc_ide_time_cfg_t; + +#ifdef MXC_ATA_USE_8_BIT_ACCESS /* use 8 bit access */ + +/*!defines the macro for accessing the register */ +#define ATA_RAW_WRITE(v, addr) __raw_writeb(v, addr) +#define ATA_RAW_READ(addr) __raw_readb(addr) + +/*! Get the configuration of TIME_CONFIG0 */ +#define GET_TIME_CFG(t, base) +/*! Set the configuration of TIME_CONFIG0. + * And mask is the mask of valid fields. + * base is the start address of this cofniguration. + */ +#define SET_TIME_CFG(t, mask, base) \ + { \ + if ((mask) & 1) \ + ATA_RAW_WRITE((t)->bytes.field1, (unsigned long)(base)); \ + if ((mask) & 2) \ + ATA_RAW_WRITE((t)->bytes.field2, (unsigned long)(base) + 1); \ + if ((mask) & 4) \ + ATA_RAW_WRITE((t)->bytes.field3, (unsigned long)(base) + 2); \ + if ((mask) & 8) \ + ATA_RAW_WRITE((t)->bytes.field4, (unsigned long)(base) + 3); \ + } + +#else /*MXC_ATA_USE_8_BIT_ACCESS */ + +/*!defines the macro for accessing the register */ +#define ATA_RAW_WRITE(v, addr) __raw_writel(v, addr) +#define ATA_RAW_READ(addr) __raw_readl(addr) +/*! Get the configuration of TIME_CONFIG0 */ +#define GET_TIME_CFG(t, base) \ + { \ + (t)->config = ATA_RAW_READ(base); \ + } + +/*! Set the configuration of TIME_CONFIG0. + * And mask is ignored. base is the start address of this configuration. + */ +#define SET_TIME_CFG(t, mask, base) \ + { \ + ATA_RAW_WRITE((t)->config, base); \ + } +#endif /*MXC_ATA_USE_8_BIT_ACCESS */ + +#endif /* !_MXC_IDE_H_ */ diff -urN linux-2.6.26/drivers/ide/ide-floppy.c linux-2.6.26-lab126/drivers/ide/ide-floppy.c --- linux-2.6.26/drivers/ide/ide-floppy.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/ide/ide-floppy.c 2010-08-10 04:17:14.000000000 -0400 @@ -1171,9 +1171,9 @@ unsigned long flags; u8 stat; - local_irq_save(flags); + local_irq_save_nort(flags); stat = ide_read_status(drive); - local_irq_restore(flags); + local_irq_restore_nort(flags); progress_indication = ((stat & SEEK_STAT) == 0) ? 0 : 0x10000; } diff -urN linux-2.6.26/drivers/ide/ide-io.c linux-2.6.26-lab126/drivers/ide/ide-io.c --- linux-2.6.26/drivers/ide/ide-io.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/ide/ide-io.c 2010-08-10 04:17:14.000000000 -0400 @@ -1036,7 +1036,7 @@ ide_get_lock(ide_intr, hwgroup); /* caller must own ide_lock */ - BUG_ON(!irqs_disabled()); + BUG_ON_NONRT(!irqs_disabled()); while (!hwgroup->busy) { hwgroup->busy = 1; @@ -1302,7 +1302,7 @@ disable_irq(hwif->irq); /* local CPU only, * as if we were handling an interrupt */ - local_irq_disable(); + local_irq_disable_nort(); if (hwgroup->polling) { startstop = handler(drive); } else if (drive_is_ready(drive)) { diff -urN linux-2.6.26/drivers/ide/ide-iops.c linux-2.6.26-lab126/drivers/ide/ide-iops.c --- linux-2.6.26/drivers/ide/ide-iops.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/ide/ide-iops.c 2010-08-10 04:17:14.000000000 -0400 @@ -256,7 +256,7 @@ unsigned long uninitialized_var(flags); if ((io_32bit & 2) && !mmio) { - local_irq_save(flags); + local_irq_save_nort(flags); ata_vlb_sync(io_ports->nsect_addr); } @@ -266,7 +266,7 @@ insl(data_addr, buf, len / 4); if ((io_32bit & 2) && !mmio) - local_irq_restore(flags); + local_irq_restore_nort(flags); if ((len & 3) >= 2) { if (mmio) @@ -299,7 +299,7 @@ unsigned long uninitialized_var(flags); if ((io_32bit & 2) && !mmio) { - local_irq_save(flags); + local_irq_save_nort(flags); ata_vlb_sync(io_ports->nsect_addr); } @@ -309,7 +309,7 @@ outsl(data_addr, buf, len / 4); if ((io_32bit & 2) && !mmio) - local_irq_restore(flags); + local_irq_restore_nort(flags); if ((len & 3) >= 2) { if (mmio) @@ -537,12 +537,12 @@ if (!(stat & BUSY_STAT)) break; - local_irq_restore(flags); + local_irq_restore_nort(flags); *rstat = stat; return -EBUSY; } } - local_irq_restore(flags); + local_irq_restore_nort(flags); } /* * Allow status to settle, then read it again. @@ -711,17 +711,17 @@ printk("%s: CHECK for good STATUS\n", drive->name); return 0; } - local_irq_save(flags); + local_irq_save_nort(flags); SELECT_MASK(drive, 0); id = kmalloc(SECTOR_WORDS*4, GFP_ATOMIC); if (!id) { - local_irq_restore(flags); + local_irq_restore_nort(flags); return 0; } hwif->input_data(drive, NULL, id, SECTOR_SIZE); (void)ide_read_status(drive); /* clear drive IRQ */ - local_irq_enable(); - local_irq_restore(flags); + local_irq_enable_nort(); + local_irq_restore_nort(flags); ide_fix_driveid(id); if (id) { drive->id->dma_ultra = id->dma_ultra; @@ -834,6 +834,8 @@ return error; } +EXPORT_SYMBOL(ide_config_drive_speed); + /* * This should get invoked any time we exit the driver to * wait for an interrupt response from a drive. handler() points diff -urN linux-2.6.26/drivers/ide/ide-lib.c linux-2.6.26-lab126/drivers/ide/ide-lib.c --- linux-2.6.26/drivers/ide/ide-lib.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/ide/ide-lib.c 2010-08-10 04:17:14.000000000 -0400 @@ -438,14 +438,15 @@ static void ide_dump_opcode(ide_drive_t *drive) { + unsigned long flags; struct request *rq; ide_task_t *task = NULL; - spin_lock(&ide_lock); + spin_lock_irqsave(&ide_lock, flags); rq = NULL; if (HWGROUP(drive)) rq = HWGROUP(drive)->rq; - spin_unlock(&ide_lock); + spin_unlock_irqrestore(&ide_lock, flags); if (!rq) return; @@ -543,10 +544,8 @@ u8 ide_dump_status(ide_drive_t *drive, const char *msg, u8 stat) { - unsigned long flags; u8 err = 0; - local_irq_save(flags); printk("%s: %s: status=0x%02x { ", drive->name, msg, stat); if (stat & BUSY_STAT) printk("Busy "); @@ -569,7 +568,6 @@ ide_dump_atapi_error(drive, err); } ide_dump_opcode(drive); - local_irq_restore(flags); return err; } diff -urN linux-2.6.26/drivers/ide/ide-probe.c linux-2.6.26-lab126/drivers/ide/ide-probe.c --- linux-2.6.26/drivers/ide/ide-probe.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/ide/ide-probe.c 2010-08-10 04:17:14.000000000 -0400 @@ -127,7 +127,7 @@ hwif->input_data(drive, NULL, id, SECTOR_SIZE); drive->id_read = 1; - local_irq_enable(); + local_irq_enable_nort(); #ifdef DEBUG printk(KERN_INFO "%s: dumping identify data\n", drive->name); ide_dump_identify((u8 *)id); @@ -316,14 +316,14 @@ unsigned long flags; /* local CPU only; some systems need this */ - local_irq_save(flags); + local_irq_save_nort(flags); /* drive returned ID */ do_identify(drive, cmd); /* drive responded with ID */ rc = 0; /* clear drive IRQ */ (void)ide_read_status(drive); - local_irq_restore(flags); + local_irq_restore_nort(flags); } else { /* drive refused ID */ rc = 2; @@ -796,7 +796,7 @@ rc = 0; } - local_irq_restore(flags); + local_irq_restore_nort(flags); /* * Use cached IRQ number. It might be (and is...) changed by probe diff -urN linux-2.6.26/drivers/ide/ide-taskfile.c linux-2.6.26-lab126/drivers/ide/ide-taskfile.c --- linux-2.6.26/drivers/ide/ide-taskfile.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/ide/ide-taskfile.c 2010-08-10 04:17:14.000000000 -0400 @@ -270,7 +270,7 @@ offset %= PAGE_SIZE; #ifdef CONFIG_HIGHMEM - local_irq_save(flags); + local_irq_save_nort(flags); #endif buf = kmap_atomic(page, KM_BIO_SRC_IRQ) + offset; @@ -290,7 +290,7 @@ kunmap_atomic(buf, KM_BIO_SRC_IRQ); #ifdef CONFIG_HIGHMEM - local_irq_restore(flags); + local_irq_restore_nort(flags); #endif } @@ -482,7 +482,7 @@ } if (!drive->unmask) - local_irq_disable(); + local_irq_disable_nort(); ide_set_handler(drive, &task_out_intr, WAIT_WORSTCASE, NULL); ide_pio_datablock(drive, rq, 1); diff -urN linux-2.6.26/drivers/ide/pci/alim15x3.c linux-2.6.26-lab126/drivers/ide/pci/alim15x3.c --- linux-2.6.26/drivers/ide/pci/alim15x3.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/ide/pci/alim15x3.c 2010-08-10 04:17:14.000000000 -0400 @@ -92,7 +92,7 @@ if (r_clc >= 16) r_clc = 0; } - local_irq_save(flags); + local_irq_save_nort(flags); /* * PIO mode => ATA FIFO on, ATAPI FIFO off @@ -114,7 +114,7 @@ pci_write_config_byte(dev, port, s_clc); pci_write_config_byte(dev, port+drive->select.b.unit+2, (a_clc << 4) | r_clc); - local_irq_restore(flags); + local_irq_restore_nort(flags); } /** @@ -225,7 +225,7 @@ isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL); - local_irq_save(flags); + local_irq_save_nort(flags); if (m5229_revision < 0xC2) { /* @@ -316,7 +316,7 @@ } pci_dev_put(north); pci_dev_put(isa_dev); - local_irq_restore(flags); + local_irq_restore_nort(flags); return 0; } @@ -378,7 +378,7 @@ unsigned long flags; u8 cbl = ATA_CBL_PATA40, tmpbyte; - local_irq_save(flags); + local_irq_save_nort(flags); if (m5229_revision >= 0xC2) { /* @@ -399,7 +399,7 @@ } } - local_irq_restore(flags); + local_irq_restore_nort(flags); return cbl; } diff -urN linux-2.6.26/drivers/ide/pci/hpt366.c linux-2.6.26-lab126/drivers/ide/pci/hpt366.c --- linux-2.6.26/drivers/ide/pci/hpt366.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/ide/pci/hpt366.c 2010-08-10 04:17:14.000000000 -0400 @@ -1326,7 +1326,7 @@ dma_old = inb(base + 2); - local_irq_save(flags); + local_irq_save_nort(flags); dma_new = dma_old; pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma); @@ -1337,7 +1337,7 @@ if (dma_new != dma_old) outb(dma_new, base + 2); - local_irq_restore(flags); + local_irq_restore_nort(flags); printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n", hwif->name, base, base + 7); diff -urN linux-2.6.26/drivers/infiniband/hw/ipath/ipath_verbs.c linux-2.6.26-lab126/drivers/infiniband/hw/ipath/ipath_verbs.c --- linux-2.6.26/drivers/infiniband/hw/ipath/ipath_verbs.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/infiniband/hw/ipath/ipath_verbs.c 2010-08-10 04:16:06.000000000 -0400 @@ -1020,7 +1020,7 @@ struct ipath_verbs_txreq *tx = cookie; struct ipath_qp *qp = tx->qp; struct ipath_ibdev *dev = to_idev(qp->ibqp.device); - unsigned int flags; + unsigned long flags; enum ib_wc_status ibs = status == IPATH_SDMA_TXREQ_S_OK ? IB_WC_SUCCESS : IB_WC_WR_FLUSH_ERR; @@ -1050,7 +1050,7 @@ static void decrement_dma_busy(struct ipath_qp *qp) { - unsigned int flags; + unsigned long flags; if (atomic_dec_and_test(&qp->s_dma_busy)) { spin_lock_irqsave(&qp->s_lock, flags); @@ -1220,7 +1220,7 @@ unsigned flush_wc; u32 control; int ret; - unsigned int flags; + unsigned long flags; piobuf = ipath_getpiobuf(dd, plen, NULL); if (unlikely(piobuf == NULL)) { diff -urN linux-2.6.26/drivers/infiniband/ulp/ipoib/ipoib_multicast.c linux-2.6.26-lab126/drivers/infiniband/ulp/ipoib/ipoib_multicast.c --- linux-2.6.26/drivers/infiniband/ulp/ipoib/ipoib_multicast.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/infiniband/ulp/ipoib/ipoib_multicast.c 2010-08-10 04:16:04.000000000 -0400 @@ -773,7 +773,7 @@ ipoib_mcast_stop_thread(dev, 0); - local_irq_save(flags); + local_irq_save_nort(flags); netif_tx_lock(dev); spin_lock(&priv->lock); @@ -852,7 +852,7 @@ spin_unlock(&priv->lock); netif_tx_unlock(dev); - local_irq_restore(flags); + local_irq_restore_nort(flags); /* We have to cancel outside of the spinlock */ list_for_each_entry_safe(mcast, tmcast, &remove_list, list) { diff -urN linux-2.6.26/drivers/input/Kconfig linux-2.6.26-lab126/drivers/input/Kconfig --- linux-2.6.26/drivers/input/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/input/Kconfig 2010-08-10 04:15:44.000000000 -0400 @@ -162,6 +162,10 @@ source "drivers/input/keyboard/Kconfig" +source "drivers/input/fiveway/Kconfig" + +source "drivers/input/volume/Kconfig" + source "drivers/input/mouse/Kconfig" source "drivers/input/joystick/Kconfig" diff -urN linux-2.6.26/drivers/input/Makefile linux-2.6.26-lab126/drivers/input/Makefile --- linux-2.6.26/drivers/input/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/input/Makefile 2010-08-10 04:15:44.000000000 -0400 @@ -16,6 +16,8 @@ obj-$(CONFIG_INPUT_EVBUG) += evbug.o obj-$(CONFIG_INPUT_KEYBOARD) += keyboard/ +obj-$(CONFIG_INPUT_FIVEWAY) += fiveway/ +obj-$(CONFIG_INPUT_VOLUME) += volume/ obj-$(CONFIG_INPUT_MOUSE) += mouse/ obj-$(CONFIG_INPUT_JOYSTICK) += joystick/ obj-$(CONFIG_INPUT_TABLET) += tablet/ diff -urN linux-2.6.26/drivers/input/ff-memless.c linux-2.6.26-lab126/drivers/input/ff-memless.c --- linux-2.6.26/drivers/input/ff-memless.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/input/ff-memless.c 2010-08-10 04:15:44.000000000 -0400 @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff -urN linux-2.6.26/drivers/input/fiveway/Kconfig linux-2.6.26-lab126/drivers/input/fiveway/Kconfig --- linux-2.6.26/drivers/input/fiveway/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/input/fiveway/Kconfig 2010-08-10 04:15:44.000000000 -0400 @@ -0,0 +1,14 @@ +# +# 5-Way Switch driver configuration +# +config INPUT_FIVEWAY + tristate "5-Way Switch" + depends on INPUT + help + Say Y here if you have a 5-Way switch connected to your system. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called fiveway. + diff -urN linux-2.6.26/drivers/input/fiveway/Makefile linux-2.6.26-lab126/drivers/input/fiveway/Makefile --- linux-2.6.26/drivers/input/fiveway/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/input/fiveway/Makefile 2010-08-10 04:15:44.000000000 -0400 @@ -0,0 +1,5 @@ +# +# 5-Way Switch controller driver +# +obj-$(CONFIG_INPUT_FIVEWAY) += fiveway.o + diff -urN linux-2.6.26/drivers/input/fiveway/fiveway.c linux-2.6.26-lab126/drivers/input/fiveway/fiveway.c --- linux-2.6.26/drivers/input/fiveway/fiveway.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/input/fiveway/fiveway.c 2010-09-02 21:21:01.000000000 -0400 @@ -0,0 +1,1245 @@ +/* +** 5-Way Switch driver routine for Luigi. +** Copyright (C) 2010 Amazon Technologies, Inc. All Rights Reserved. +** Manish Lachwani (lachwani@lab126.com). +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +// Logging +static unsigned int logging_mask; +#define LLOG_G_LOG_MASK logging_mask +#define LLOG_KERNEL_COMP "fiveway" +#include + +#include "fiveway.h" + +// Input device structure +static struct input_dev *fiveway_dev = NULL; + +// Global variables + +static char line_state[NUM_OF_LINES]; + +// Workqueue +static struct delayed_work fiveway_up_debounce_tq_d; +static struct delayed_work fiveway_left_debounce_tq_d; +static struct delayed_work fiveway_down_debounce_tq_d; +static struct delayed_work fiveway_right_debounce_tq_d; +static struct delayed_work fiveway_select_debounce_tq_d; + +static struct delayed_work fiveway_repeat_up_tq_d; +static struct delayed_work fiveway_repeat_select_tq_d; +static struct delayed_work fiveway_repeat_right_tq_d; +static struct delayed_work fiveway_repeat_left_tq_d; +static struct delayed_work fiveway_repeat_down_tq_d; + +static void fiveway_up_debounce_wk(struct work_struct *); +static void fiveway_down_debounce_wk(struct work_struct *); +static void fiveway_right_debounce_wk(struct work_struct *); +static void fiveway_left_debounce_wk(struct work_struct *); +static void fiveway_select_debounce_wk(struct work_struct *); + +static void fiveway_repeat_up_work(struct work_struct *); +static void fiveway_repeat_left_work(struct work_struct *); +static void fiveway_repeat_select_work(struct work_struct *); +static void fiveway_repeat_right_work(struct work_struct *); +static void fiveway_repeat_down_work(struct work_struct *); + +DEFINE_RAW_SPINLOCK(fiveway_spinlock); + +// Proc entry structure and global variable. +#define FIVEWAY_PROC_FILE "fiveway" +#define PROC_CMD_LEN 50 +static struct proc_dir_entry *proc_entry; +static int fiveway_lock = 0; // 0=unlocked; non-zero=locked + + +// Module parameters + +#define FIVEWAY_REV_DEFAULT 0 +static int fiveway_rev = FIVEWAY_REV_DEFAULT; +module_param(fiveway_rev, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(fiveway_rev, "5-Way hardware revision; 0=Mario, 1=Turing prototype build, 2=Turing v1 (default is 0)"); + +#define DEBOUNCE_TIMEOUT_DEFAULT 60 +static int debounce_timeout = DEBOUNCE_TIMEOUT_DEFAULT; +module_param(debounce_timeout, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(debounce_timeout, "Time for debouncing the fiveway switch, in msec; MUST be a multiple of 10 (default is 60)"); + +#define HOLD_TIMEOUT_DEFAULT 200 +static int UP_hold_timeout = HOLD_TIMEOUT_DEFAULT; +module_param(UP_hold_timeout, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(UP_hold_timeout, "Time before holding UP starts auto-repeat mode, in msec; MUST be a multiple of 10 (default is 500; 0 = no auto-repeat)"); + +static int DOWN_hold_timeout = HOLD_TIMEOUT_DEFAULT; +module_param(DOWN_hold_timeout, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(DOWN_hold_timeout, "Time before holding DOWN starts auto-repeat mode, in msec; MUST be a multiple of 10 (default is 500; 0 = no auto-repeat)"); + +static int LEFT_hold_timeout = HOLD_TIMEOUT_DEFAULT; +module_param(LEFT_hold_timeout, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(LEFT_hold_timeout, "Time before holding LEFT starts auto-repeat mode, in msec; MUST be a multiple of 10 (default is 500; 0 = no auto-repeat)"); + +static int RIGHT_hold_timeout = HOLD_TIMEOUT_DEFAULT; +module_param(RIGHT_hold_timeout, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(RIGHT_hold_timeout, "Time before holding RIGHT starts auto-repeat mode, in msec; MUST be a multiple of 10 (default is 500; 0 = no auto-repeat)"); + +static int SELECT_hold_timeout = 500; +module_param(SELECT_hold_timeout, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(SELECT_hold_timeout, "Time before holding SELECT generates HOLD event or starts auto-repeat mode, in msec; MUST be a multiple of 10 (default is 1000)"); + +#define AUTO_REPEAT_TIMEOUT_DEFAULT 100 +static int UP_auto_repeat_time = AUTO_REPEAT_TIMEOUT_DEFAULT; +module_param(UP_auto_repeat_time, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(UP_auto_repeat_time, "Time between UP key auto-repeat events; MUST be a multiple of 10 (default is 100; 0 = no auto-repeat)"); + +static int DOWN_auto_repeat_time = AUTO_REPEAT_TIMEOUT_DEFAULT; +module_param(DOWN_auto_repeat_time, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(DOWN_auto_repeat_time, "Time between DOWN key auto-repeat events; MUST be a multiple of 10 (default is 100; 0 = no auto-repeat)"); + +static int LEFT_auto_repeat_time = AUTO_REPEAT_TIMEOUT_DEFAULT; +module_param(LEFT_auto_repeat_time, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(LEFT_auto_repeat_time, "Time between LEFT key auto-repeat events; MUST be a multiple of 10 (default is 100; 0 = no auto-repeat)"); + +static int RIGHT_auto_repeat_time = AUTO_REPEAT_TIMEOUT_DEFAULT; +module_param(RIGHT_auto_repeat_time, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(RIGHT_auto_repeat_time, "Time between RIGHT key auto-repeat events; MUST be a multiple of 10 (default is 100; 0 = no auto-repeat)"); + +static int SELECT_auto_repeat_time = AUTO_REPEAT_TIMEOUT_DEFAULT; +module_param(SELECT_auto_repeat_time, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(SELECT_auto_repeat_time, "Time between SELECT key auto-repeat events; MUST be a multiple of 10 (default is 100; 0 = no auto-repeat)"); + +static int debug = 0; +module_param(debug, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(debug, "Enable debugging; 0=off, any other value=on (default is off)"); + + +/* + * Set the log mask depending on the debug level + */ +static void set_debug_log_mask(int debug_level) +{ + logging_mask = LLOG_LEVEL_MASK_INFO | LLOG_LEVEL_MASK_EXCEPTIONS; + switch (debug_level) { + case 10: logging_mask |= LLOG_LEVEL_DEBUG9; + case 9: logging_mask |= LLOG_LEVEL_DEBUG8; + case 8: logging_mask |= LLOG_LEVEL_DEBUG7; + case 7: logging_mask |= LLOG_LEVEL_DEBUG6; + case 6: logging_mask |= LLOG_LEVEL_DEBUG5; + case 5: logging_mask |= LLOG_LEVEL_DEBUG4; + case 4: logging_mask |= LLOG_LEVEL_DEBUG3; + case 3: logging_mask |= LLOG_LEVEL_DEBUG2; + case 2: logging_mask |= LLOG_LEVEL_DEBUG1; + case 1: logging_mask |= LLOG_LEVEL_DEBUG0; + + case 0: + default: ; // No logging if debug_level <= 0 or > 10 + } +} + +static atomic_t fiveway_is_locked = ATOMIC_INIT(0); + +/* + * Report the fiveway event. In addition to calling + * input_event, this function sends a uevent for any + * processes listening in the userspace + */ +static void report_event(struct input_dev *dev, unsigned int type, unsigned int code, int value) +{ + if (atomic_read(&fiveway_is_locked)) + return; + + input_event( dev, type, code, value ); + + // Send uevent so userspace power daemon can monitor + // fiveway activity + // NOTE: only sending uevent on key down as per Manish + + if (value == 1) { + if( kobject_uevent_atomic( &dev->dev.kobj, KOBJ_CHANGE ) ) + { + LLOG_ERROR("uevent", "", "Fiveway driver failed to send uevent\n" ); + } + } +} + +#define AUTO_RPT(dbgstr, keycode, time, line) \ + LLOG_DEBUG0("Got 5-Way Switch repeat timeout: %s\n", dbgstr); \ + report_event(fiveway_dev, EV_KEY, keycode, 2); \ + line_state[line] = LINE_HELD; + +extern int fiveway_datain(int); + +static void fiveway_repeat_up_work(struct work_struct *work) +{ + LLOG_DEBUG0("Got auto-repeat timeout\n"); + + if (fiveway_lock == 1) + return; + + // Send appropriate event, depending on button held + if ( fiveway_datain(UP_LINE) == 0) { + AUTO_RPT("UP", FIVEWAY_KEYCODE_UP, UP_auto_repeat_time, UP_LINE); + schedule_delayed_work(&fiveway_repeat_up_tq_d, ((UP_auto_repeat_time * HZ) / 1000)); + } +} + +static void fiveway_repeat_select_work(struct work_struct *work) +{ + LLOG_DEBUG0("Got auto-repeat timeout\n"); + + /* Do not send a select auto repeat */ + return; + + // Send appropriate event, depending on button held + if ( fiveway_datain(SELECT_LINE) == 0) { + AUTO_RPT("SELECT", FIVEWAY_KEYCODE_SELECT, SELECT_auto_repeat_time, SELECT_LINE); + schedule_delayed_work(&fiveway_repeat_select_tq_d, ((SELECT_auto_repeat_time * HZ) / 1000)); + } +} + +static void fiveway_repeat_right_work(struct work_struct *work) +{ + LLOG_DEBUG0("Got auto-repeat timeout\n"); + + if (fiveway_lock == 1) + return; + + // Send appropriate event, depending on button held + if ( fiveway_datain(RIGHT_LINE) == 0) { + AUTO_RPT("RIGHT", FIVEWAY_KEYCODE_RIGHT, RIGHT_auto_repeat_time, RIGHT_LINE); + schedule_delayed_work(&fiveway_repeat_right_tq_d, ((RIGHT_auto_repeat_time * HZ) / 1000)); + } +} + +static void fiveway_repeat_left_work(struct work_struct *work) +{ + LLOG_DEBUG0("Got auto-repeat timeout\n"); + + if (fiveway_lock == 1) + return; + + // Send appropriate event, depending on button held + if ( fiveway_datain(LEFT_LINE) == 0) { + AUTO_RPT("LEFT", FIVEWAY_KEYCODE_LEFT, LEFT_auto_repeat_time, LEFT_LINE); + schedule_delayed_work(&fiveway_repeat_left_tq_d, ((LEFT_auto_repeat_time * HZ) / 1000)); + } +} + +static void fiveway_repeat_down_work(struct work_struct *work) +{ + LLOG_DEBUG0("Got auto-repeat timeout\n"); + + if (fiveway_lock == 1) + return; + + // Send appropriate event, depending on button held + if ( fiveway_datain(DOWN_LINE) == 0) { + AUTO_RPT("DOWN", FIVEWAY_KEYCODE_DOWN, DOWN_auto_repeat_time, DOWN_LINE); + schedule_delayed_work(&fiveway_repeat_down_tq_d, ((DOWN_auto_repeat_time * HZ) / 1000)); + } +} + +static void enable_other_irqs(int irq, int enable); + +/* Called from the IRQ handler */ +#define PUSHED1(dbgstr, keycode, time, irq, line) \ + LLOG_DEBUG0("Got 5-Way Switch signal push: %s\n", dbgstr); \ + line_state[line] = LINE_ASSERTED; \ + report_event(fiveway_dev, EV_KEY, keycode, 1); \ + set_irq_type(irq, IRQF_TRIGGER_RISING); \ + + +#define PUSHED(dbgstr, keycode, time, irq, line) \ + LLOG_DEBUG0("Got 5-Way Switch signal push: %s\n", dbgstr); \ + timeout = time; \ + set_irq_type(irq, IRQF_TRIGGER_RISING); \ + line_state[line] = LINE_ASSERTED; + +#define RELEASED(dbgstr, keycode, line, irq) \ + LLOG_DEBUG0("Got 5-Way Switch signal release: %s\n", dbgstr); \ + report_event(fiveway_dev, EV_KEY, keycode, 0); \ + set_irq_type(irq, IRQF_TRIGGER_FALLING); + +#define RELEASED1(dbgstr, keycode, line, irq) \ + LLOG_DEBUG0("Got 5-Way Switch signal release: %s\n", dbgstr); \ + report_event(fiveway_dev, EV_KEY, keycode, 0); \ + line_state[line] = LINE_DEASSERTED; \ + set_irq_type(irq, IRQF_TRIGGER_FALLING); + + +static int disabled_up_irq = 0; +static int disabled_select_irq = 0; +static int disabled_right_irq = 0; +static int disabled_left_irq = 0; +static int disabled_down_irq = 0; + +static int ignore_up_line = 0; +static int ignore_select_line = 0; +static int ignore_right_line = 0; +static int ignore_down_line = 0; +static int ignore_left_line = 0; + +static int disabled_up = 0; +static int disabled_select = 0; +static int disabled_right = 0; +static int disabled_left = 0; +static int disabled_down = 0; + +static void fiveway_up_debounce_wk(struct work_struct *work) +{ + int timeout = 0; + int flag = 0; + + LLOG_DEBUG1("Debounce period expired\n"); + // Send appropriate event, depending on button held + if (!ignore_up_line && fiveway_datain(UP_LINE) == 0 ) { + PUSHED("UP", FIVEWAY_KEYCODE_UP, UP_hold_timeout, + FIVEWAY_UP_IRQ, UP_LINE); + schedule_delayed_work(&fiveway_repeat_up_tq_d, ((timeout * HZ) / 1000)); + } + + if (( fiveway_datain(UP_LINE) == 1 ) && + ( line_state[UP_LINE] != LINE_DEASSERTED )) { + cancel_delayed_work_sync(&fiveway_repeat_up_tq_d); + RELEASED1("UP", FIVEWAY_KEYCODE_UP, UP_LINE, FIVEWAY_UP_IRQ); + ignore_up_line = 0; + flag = 1; + } + + if (( fiveway_datain(UP_LINE) == 1 ) && + ( line_state[UP_LINE] == LINE_DEASSERTED )) { + flag = 1; + } + + if (disabled_up == 1) { + disabled_up = 0; + enable_irq(FIVEWAY_UP_IRQ); + if (flag == 1 && !timeout) + enable_other_irqs(FIVEWAY_UP_IRQ, 1); + } +} + +static void fiveway_down_debounce_wk(struct work_struct *work) +{ + int timeout = 0; + int flag = 0; + + LLOG_DEBUG1("Debounce period expired\n"); + // Send appropriate event, depending on button held + if (!ignore_down_line && fiveway_datain(DOWN_LINE) == 0 ) { + PUSHED("DOWN", FIVEWAY_KEYCODE_DOWN, DOWN_hold_timeout, + FIVEWAY_DOWN_IRQ, DOWN_LINE); + schedule_delayed_work(&fiveway_repeat_down_tq_d, ((timeout * HZ) / 1000)); + } + + if (( fiveway_datain(DOWN_LINE) == 1 ) && + ( line_state[DOWN_LINE] != LINE_DEASSERTED )) { + cancel_delayed_work_sync(&fiveway_repeat_down_tq_d); + RELEASED1("DOWN", FIVEWAY_KEYCODE_DOWN, DOWN_LINE, FIVEWAY_DOWN_IRQ); + ignore_down_line = 0; + flag = 1; + } + + if (( fiveway_datain(DOWN_LINE) == 1 ) && + ( line_state[DOWN_LINE] == LINE_DEASSERTED )) { + flag = 1; + } + + if (disabled_down == 1) { + disabled_down = 0; + enable_irq(FIVEWAY_DOWN_IRQ); + if (flag == 1 && !timeout) + enable_other_irqs(FIVEWAY_DOWN_IRQ, 1); + } + +} + +static void fiveway_right_debounce_wk(struct work_struct *work) +{ + int timeout = 0; + int flag = 0; + + LLOG_DEBUG1("Debounce period expired\n"); + // Send appropriate event, depending on button held + + if (!ignore_right_line && fiveway_datain(RIGHT_LINE) == 0 ) { + PUSHED("RIGHT", FIVEWAY_KEYCODE_RIGHT, RIGHT_hold_timeout, + FIVEWAY_RIGHT_IRQ, RIGHT_LINE); + schedule_delayed_work(&fiveway_repeat_right_tq_d, ((timeout * HZ) / 1000)); + } + + if (( fiveway_datain(RIGHT_LINE) == 1 ) && + ( line_state[RIGHT_LINE] != LINE_DEASSERTED )) { + cancel_delayed_work_sync(&fiveway_repeat_right_tq_d); + RELEASED1("RIGHT", FIVEWAY_KEYCODE_RIGHT, RIGHT_LINE, FIVEWAY_RIGHT_IRQ); + ignore_right_line = 0; + flag = 1; + } + + if (( fiveway_datain(RIGHT_LINE) == 1 ) && + ( line_state[RIGHT_LINE] == LINE_DEASSERTED )) { + flag = 1; + } + + if (disabled_right == 1) { + disabled_right = 0; + enable_irq(FIVEWAY_RIGHT_IRQ); + if (flag == 1 && !timeout) + enable_other_irqs(FIVEWAY_RIGHT_IRQ, 1); + } +} + +static void fiveway_left_debounce_wk(struct work_struct *work) +{ + int timeout = 0; + int flag = 0; + + LLOG_DEBUG1("Debounce period expired\n"); + // Send appropriate event, depending on button held + + if (!ignore_left_line && fiveway_datain(LEFT_LINE) == 0 ) { + PUSHED("LEFT", FIVEWAY_KEYCODE_LEFT, LEFT_hold_timeout, + FIVEWAY_LEFT_IRQ, LEFT_LINE); + schedule_delayed_work(&fiveway_repeat_left_tq_d, ((timeout * HZ) / 1000)); + } + + if (( fiveway_datain(LEFT_LINE) == 1 ) && + ( line_state[LEFT_LINE] != LINE_DEASSERTED )) { + cancel_delayed_work_sync(&fiveway_repeat_left_tq_d); + RELEASED1("LEFT", FIVEWAY_KEYCODE_LEFT, LEFT_LINE, FIVEWAY_LEFT_IRQ); + ignore_left_line = 0; + flag = 1; + } + + if (( fiveway_datain(LEFT_LINE) == 1 ) && + ( line_state[LEFT_LINE] == LINE_DEASSERTED )) { + flag = 1; + } + + if (disabled_left == 1) { + disabled_left = 0; + enable_irq(FIVEWAY_LEFT_IRQ); + if (flag == 1 && !timeout) + enable_other_irqs(FIVEWAY_LEFT_IRQ, 1); + } + +} + +static void fiveway_select_debounce_wk(struct work_struct *work) +{ + int timeout = 0; + int flag = 0; + + LLOG_DEBUG1("Debounce period expired\n"); + // Send appropriate event, depending on button held + + if (!ignore_select_line && fiveway_datain(SELECT_LINE) == 0 ) { + PUSHED("SELECT", FIVEWAY_KEYCODE_SELECT, SELECT_hold_timeout, + FIVEWAY_SELECT_IRQ, SELECT_LINE); + schedule_delayed_work(&fiveway_repeat_select_tq_d, ((timeout * HZ) / 1000)); + } + + if (( fiveway_datain(SELECT_LINE) == 1 ) && + ( line_state[SELECT_LINE] != LINE_DEASSERTED )) { + cancel_delayed_work_sync(&fiveway_repeat_select_tq_d); + RELEASED1("SELECT", FIVEWAY_KEYCODE_SELECT, SELECT_LINE, FIVEWAY_SELECT_IRQ); + ignore_select_line = 0; + flag = 1; + } + + if (( fiveway_datain(SELECT_LINE) == 1 ) && + ( line_state[SELECT_LINE] == LINE_DEASSERTED )) { + flag = 1; + } + + if (disabled_select == 1) { + disabled_select = 0; + enable_irq(FIVEWAY_SELECT_IRQ); + if (flag == 1 && !timeout) + enable_other_irqs(FIVEWAY_SELECT_IRQ, 1); + } + +} + +static int fiveway_irq_disabled(int irq) +{ + if ( (irq == FIVEWAY_UP_IRQ) && disabled_up_irq) + return 1; + + if ( (irq == FIVEWAY_DOWN_IRQ) && disabled_down_irq) + return 1; + + if ( (irq == FIVEWAY_LEFT_IRQ) && disabled_left_irq) + return 1; + + if ( (irq == FIVEWAY_RIGHT_IRQ) && disabled_right_irq) + return 1; + + if ( (irq == FIVEWAY_SELECT_IRQ) && disabled_select_irq) + return 1; + + return 0; +} + +static void enable_other_irqs(int irq, int enable) +{ + unsigned long flags; + + if (fiveway_irq_disabled(irq)) + return; + + spin_lock_irqsave(&fiveway_spinlock, flags); + + if (enable == 0) { + if (irq != FIVEWAY_UP_IRQ) { + disabled_up_irq = 1; + } + + if (irq != FIVEWAY_DOWN_IRQ) { + disabled_down_irq = 1; + } + + if (irq != FIVEWAY_LEFT_IRQ) { + disabled_left_irq = 1; + } + + if (irq != FIVEWAY_RIGHT_IRQ) { + disabled_right_irq = 1; + } + + if (irq != FIVEWAY_SELECT_IRQ) { + disabled_select_irq = 1; + } + } + else { + if (irq != FIVEWAY_UP_IRQ) { + if (fiveway_datain(UP_LINE) == 0) + ignore_up_line = 1; + + disabled_up_irq = 0; + } + + if (irq != FIVEWAY_DOWN_IRQ) { + if (fiveway_datain(DOWN_LINE) == 0) + ignore_down_line = 1; + + disabled_down_irq = 0; + } + + if (irq != FIVEWAY_LEFT_IRQ) { + if (fiveway_datain(LEFT_LINE) == 0) + ignore_left_line = 1; + + disabled_left_irq = 0; + } + + if (irq != FIVEWAY_RIGHT_IRQ) { + if (fiveway_datain(RIGHT_LINE) == 0) + ignore_right_line = 1; + + disabled_right_irq = 0; + } + + if (irq != FIVEWAY_SELECT_IRQ) { + if (fiveway_datain(SELECT_LINE) == 0) + ignore_select_line = 1; + + disabled_select_irq = 0; + } + } + spin_unlock_irqrestore(&fiveway_spinlock, flags); +} + +static int fiveway_initialized = 0; + +static irqreturn_t fiveway_irq (int irq, void *data, struct pt_regs *r) +{ + if (fiveway_irq_disabled(irq)) + return IRQ_HANDLED; + + if (!fiveway_initialized) + return IRQ_HANDLED; + + if ( !disabled_up_irq && (fiveway_datain(UP_LINE) == 0) && (irq == FIVEWAY_UP_IRQ)) { + if (ignore_up_line && (line_state[UP_LINE] == LINE_ASSERTED)) { + goto out; + } else { + ignore_up_line = 0; + PUSHED1("UP", FIVEWAY_KEYCODE_UP, UP_hold_timeout, + FIVEWAY_UP_IRQ, UP_LINE); + enable_other_irqs(irq, 0); + } + } + else if ( !disabled_down_irq && (fiveway_datain(DOWN_LINE) == 0) && (irq == FIVEWAY_DOWN_IRQ)) { + if (ignore_down_line && (line_state[DOWN_LINE] == LINE_ASSERTED)) { + goto out; + } else { + ignore_down_line = 0; + PUSHED1("DOWN", FIVEWAY_KEYCODE_DOWN, DOWN_hold_timeout, + FIVEWAY_DOWN_IRQ, DOWN_LINE); + enable_other_irqs(irq, 0); + } + } + else if ( !disabled_left_irq && (fiveway_datain(LEFT_LINE) == 0) && (irq == FIVEWAY_LEFT_IRQ)) { + if (ignore_left_line && (line_state[LEFT_LINE] == LINE_ASSERTED)) { + goto out; + } else { + ignore_left_line = 0; + PUSHED1("LEFT", FIVEWAY_KEYCODE_LEFT, LEFT_hold_timeout, + FIVEWAY_LEFT_IRQ, LEFT_LINE); + enable_other_irqs(irq, 0); + } + } + else if ( !disabled_right_irq && (fiveway_datain(RIGHT_LINE) == 0) && (irq == FIVEWAY_RIGHT_IRQ)) { + if (ignore_right_line && (line_state[RIGHT_LINE] == LINE_ASSERTED)) { + goto out; + } else { + ignore_right_line = 0; + PUSHED1("RIGHT", FIVEWAY_KEYCODE_RIGHT, RIGHT_hold_timeout, + FIVEWAY_RIGHT_IRQ, RIGHT_LINE); + enable_other_irqs(irq, 0); + } + } + else if ( !disabled_select_irq && (fiveway_datain(SELECT_LINE) == 0) && (irq == FIVEWAY_SELECT_IRQ)) { + if (ignore_select_line && (line_state[SELECT_LINE] == LINE_ASSERTED)) { + goto out; + } else { + ignore_select_line = 0; + PUSHED1("SELECT", FIVEWAY_KEYCODE_SELECT, SELECT_hold_timeout, + FIVEWAY_SELECT_IRQ, SELECT_LINE) + enable_other_irqs(irq, 0); + } + } + + if (( fiveway_datain(UP_LINE) == 1 ) && + ( line_state[UP_LINE] != LINE_DEASSERTED ) && (irq == FIVEWAY_UP_IRQ)) { + cancel_delayed_work(&fiveway_repeat_up_tq_d); + RELEASED("UP", FIVEWAY_KEYCODE_UP, UP_LINE, FIVEWAY_UP_IRQ); + enable_other_irqs(irq, 1); + ignore_up_line = 0; + } + else if (( fiveway_datain(DOWN_LINE) == 1 ) && + ( line_state[DOWN_LINE] != LINE_DEASSERTED ) && (irq == FIVEWAY_DOWN_IRQ)) { + cancel_delayed_work(&fiveway_repeat_down_tq_d); + RELEASED("DOWN", FIVEWAY_KEYCODE_DOWN, DOWN_LINE, FIVEWAY_DOWN_IRQ); + enable_other_irqs(irq, 1); + ignore_down_line = 0; + } + else if (( fiveway_datain(LEFT_LINE) == 1 ) && + ( line_state[LEFT_LINE] != LINE_DEASSERTED ) && (irq == FIVEWAY_LEFT_IRQ)) { + cancel_delayed_work(&fiveway_repeat_left_tq_d); + RELEASED("LEFT", FIVEWAY_KEYCODE_LEFT, LEFT_LINE, FIVEWAY_LEFT_IRQ); + enable_other_irqs(irq, 1); + ignore_left_line = 0; + } + else if (( fiveway_datain(RIGHT_LINE) == 1 ) && + ( line_state[RIGHT_LINE] != LINE_DEASSERTED ) && (irq == FIVEWAY_RIGHT_IRQ)) { + cancel_delayed_work(&fiveway_repeat_right_tq_d); + RELEASED("RIGHT", FIVEWAY_KEYCODE_RIGHT, RIGHT_LINE, FIVEWAY_RIGHT_IRQ); + enable_other_irqs(irq, 1); + ignore_right_line = 0; + } + else if (( fiveway_datain(SELECT_LINE) == 1 ) && + ( line_state[SELECT_LINE] != LINE_DEASSERTED ) && (irq == FIVEWAY_SELECT_IRQ)) { + cancel_delayed_work(&fiveway_repeat_select_tq_d); + RELEASED("SELECT", FIVEWAY_KEYCODE_SELECT, SELECT_LINE, FIVEWAY_SELECT_IRQ); + enable_other_irqs(irq, 1); + ignore_select_line = 0; + } + + // Start the debounce delayed work item, to avoid spurious signals + LLOG_DEBUG1("Starting debounce delayed work item...\n"); + + disable_irq(irq); + + if (irq == FIVEWAY_UP_IRQ) { + schedule_delayed_work(&fiveway_up_debounce_tq_d, ((debounce_timeout * HZ) / 1000)); + disabled_up = 1; + } + + if (irq == FIVEWAY_DOWN_IRQ) { + schedule_delayed_work(&fiveway_down_debounce_tq_d, ((debounce_timeout * HZ) / 1000)); + disabled_down = 1; + } + + if (irq == FIVEWAY_LEFT_IRQ) { + schedule_delayed_work(&fiveway_left_debounce_tq_d, ((debounce_timeout * HZ) / 1000)); + disabled_left = 1; + } + + if (irq == FIVEWAY_RIGHT_IRQ) { + schedule_delayed_work(&fiveway_right_debounce_tq_d, ((debounce_timeout * HZ) / 1000)); + disabled_right = 1; + } + + if (irq == FIVEWAY_SELECT_IRQ) { + schedule_delayed_work(&fiveway_select_debounce_tq_d, ((debounce_timeout * HZ) / 1000)); + disabled_select = 1; + } + +out: + return IRQ_HANDLED; +} + +/*! + * This function puts the 5-Way driver in off state + */ +void fiveway_off(void) +{ + LLOG_DEBUG0("Stopping work items; disabling IRQs and pullups...\n"); + atomic_set(&fiveway_is_locked, 1); + + disable_irq(FIVEWAY_RIGHT_IRQ); + disable_irq(FIVEWAY_SELECT_IRQ); + disable_irq(FIVEWAY_UP_IRQ); + disable_irq(FIVEWAY_DOWN_IRQ); + disable_irq(FIVEWAY_LEFT_IRQ); + + gpio_fiveway_inactive(); +} + + +/*! + * Suspend function + * @param pdev the device structure used to give information on 5-Way + * to suspend + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int fiveway_suspend(struct platform_device *pdev, pm_message_t state) +{ + /* + * NOTE: in the Lab126 platform architecture, we always go to + * the "locked" state before going to suspend; therefore, all + * fiveway locking actions are in the fiveway_off function, above. + */ + + return 0; +} + + +/*! + * This function brings the 5-Way driver back from low-power state, + * by re-enabling the line interrupts. + * + * @return The function always returns 0. + */ +void fiveway_on(void) +{ + LLOG_DEBUG0("Enabling GPIOs and IRQs...\n"); + + gpio_fiveway_active(); + + if (fiveway_datain(UP_LINE) == 0) { + line_state[UP_LINE] = LINE_ASSERTED; + set_irq_type(FIVEWAY_UP_IRQ, IRQF_TRIGGER_RISING); + } + else { + line_state[UP_LINE] = LINE_DEASSERTED; + set_irq_type(FIVEWAY_UP_IRQ, IRQF_TRIGGER_FALLING); + } + + if (fiveway_datain(DOWN_LINE) == 0) { + line_state[DOWN_LINE] = LINE_ASSERTED; + set_irq_type(FIVEWAY_DOWN_IRQ, IRQF_TRIGGER_RISING); + } + else { + line_state[DOWN_LINE] = LINE_DEASSERTED; + set_irq_type(FIVEWAY_DOWN_IRQ, IRQF_TRIGGER_FALLING); + } + + if (fiveway_datain(LEFT_LINE) == 0) { + line_state[LEFT_LINE] = LINE_ASSERTED; + set_irq_type(FIVEWAY_LEFT_IRQ, IRQF_TRIGGER_RISING); + } + else { + line_state[LEFT_LINE] = LINE_DEASSERTED; + set_irq_type(FIVEWAY_LEFT_IRQ, IRQF_TRIGGER_FALLING); + } + + if (fiveway_datain(RIGHT_LINE) == 0) { + line_state[RIGHT_LINE] = LINE_ASSERTED; + set_irq_type(FIVEWAY_RIGHT_IRQ, IRQF_TRIGGER_RISING); + } + else { + line_state[RIGHT_LINE] = LINE_DEASSERTED; + set_irq_type(FIVEWAY_RIGHT_IRQ, IRQF_TRIGGER_FALLING); + } + + if (fiveway_datain(SELECT_LINE) == 0) { + line_state[SELECT_LINE] = LINE_ASSERTED; + set_irq_type(FIVEWAY_SELECT_IRQ, IRQF_TRIGGER_RISING); + } + else { + line_state[SELECT_LINE] = LINE_DEASSERTED; + set_irq_type(FIVEWAY_SELECT_IRQ, IRQF_TRIGGER_FALLING); + } + + enable_irq(FIVEWAY_UP_IRQ); + enable_irq(FIVEWAY_DOWN_IRQ); + enable_irq(FIVEWAY_LEFT_IRQ); + enable_irq(FIVEWAY_RIGHT_IRQ); + enable_irq(FIVEWAY_SELECT_IRQ); + + atomic_set(&fiveway_is_locked, 0); + return; +} + + +/*! + * This function brings the 5-Way driver back from low-power state, + * by re-enabling the line interrupts. + * + * @param pdev the device structure used to give information on Keypad + * to resume + * + * @return The function always returns 0. + */ +static int fiveway_resume(struct platform_device *pdev) +{ + /* + * NOTE: in the Lab126 platform architecture, we resume functionality + * by going to the "unlocked" state, not automatically on system resume. + * Therefore, the fiveway unlocking actions are in the fiveway_on function, + * above. + */ + + return 0; +} + + +/*! + * This function is called when the fiveway driver is opened. + * Since fiveway initialization is done in __init, nothing is done in open. + * + * @param dev Pointer to device inode + * + * @result The function always returns 0 + */ +static int fiveway_open(struct input_dev *dev) +{ + return 0; +} + + +/*! + * This function is called close the fiveway device. + * Nothing is done in this function, since every thing is taken care in + * __exit function. + * + * @param dev Pointer to device inode + * + */ +static void fiveway_close(struct input_dev *dev) +{ +} + + +/* + * This function returns the current state of the fiveway device + */ +int fiveway_proc_read( char *page, char **start, off_t off, + int count, int *eof, void *data ) +{ + int len; + + if (off > 0) { + *eof = 1; + return 0; + } + if (fiveway_lock == 0) { + len = sprintf(page, "fiveway is unlocked\n"); + } + else { + len = sprintf(page, "fiveway is locked\n"); + } + + return len; +} + + +/* + * This function executes fiveway control commands based on the input string. + * unlock = unlock the fiveway + * lock = lock the fiveway + * send = send a fiveway event, simulating a line detection + * debug = set the debug level for logging messages (0=off) + */ +ssize_t fiveway_proc_write( struct file *filp, const char __user *buff, + unsigned long len, void *data ) + +{ + char command[PROC_CMD_LEN]; + int keycode; + + if (len > PROC_CMD_LEN) { + LLOG_ERROR("proc_len", "", "Fiveway command is too long!\n"); + return -ENOSPC; + } + + if (copy_from_user(command, buff, len)) { + return -EFAULT; + } + + if ( !strncmp(command, "unlock", 6) ) { + // Requested to unlock fiveway + if (fiveway_lock == 0) { + // Fiveway was already unlocked; do nothing + LLOG_INFO("unlock1", "status=unlocked", "\n"); + } + else { + // Unlock fiveway + fiveway_on(); + fiveway_lock = 0; + LLOG_INFO("unlock2", "status=unlocked", "\n"); + } + } + else if ( !strncmp(command, "lock", 4) ) { + // Requested to lock fiveway + if (fiveway_lock != 0) { + // Fiveway was already locked; do nothing + LLOG_INFO("locked1", "status=locked", "\n"); + } + else { + // Lock fiveway + fiveway_lock = 1; + fiveway_off(); + LLOG_INFO("locked2", "status=locked", "\n"); + } + } + else if ( !strncmp(command, "send", 4) ) { + // Requested to send a keycode + if (fiveway_lock != 0) { + // Keypad is locked; do nothing + LLOG_WARN("locked3", "", "The fiveway device is locked! Unlock before sending keycodes.\n"); + } + else { + // Read keycode and send + sscanf(command, "send %d", &keycode); + LLOG_INFO("send_key", "", "Sending keycode %d\n", keycode); + report_event(fiveway_dev, EV_KEY, keycode, 1); + report_event(fiveway_dev, EV_KEY, keycode, 0); + } + } + else if ( !strncmp(command, "debug", 5) ) { + // Requested to set debug level + sscanf(command, "debug %d", &debug); + LLOG_INFO("debug", "", "Setting debug level to %d\n", debug); + set_debug_log_mask(debug); + } + else { + LLOG_ERROR("proc_cmd", "", "Unrecognized fiveway command\n"); + } + + return len; +} + +static int show_fiveway_dbg_state(struct device *dev, struct device_attribute *attr, char *buf) +{ + char *curr = buf; + + curr += sprintf(curr, "fiveway interrupt state: left-%d, right-%d, up-%d, down-%d, select-%d\n", + disabled_left_irq, disabled_right_irq, disabled_up_irq, disabled_down_irq, disabled_select_irq); + + curr+= sprintf(curr, "fiveway ignore state: left-%d, right-%d, up-%d, down-%d, select-%d\n", + ignore_left_line, ignore_right_line, ignore_up_line, ignore_down_line, ignore_select_line); + + curr+= sprintf(curr, "fiveway pin state: left-%d, right-%d, up-%d, down-%d, select-%d\n", + fiveway_datain(LEFT_LINE), fiveway_datain(RIGHT_LINE), fiveway_datain(UP_LINE), + fiveway_datain(DOWN_LINE), fiveway_datain(SELECT_LINE)); + + curr+= sprintf(curr, "fiveway assert/de-assert state: left-%d, right-%d, up-%d, down-%d, select-%d\n", + line_state[LEFT_LINE], line_state[RIGHT_LINE], line_state[UP_LINE], line_state[DOWN_LINE], + line_state[SELECT_LINE]); + + curr += sprintf(curr, "\n"); + + return curr - buf; +} +static DEVICE_ATTR(fiveway_dbg_state, 0666, show_fiveway_dbg_state, NULL); + +/*! + * This function is called during the driver binding process. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions. + * + * @return The function returns 0 on successful registration. Otherwise returns + * specific error code. + */ +static int __devinit fiveway_probe(struct platform_device *pdev) +{ + int err = 0; + int i; + + LLOG_INFO("probe0", "", "Starting...\n"); + + /* Create proc entry */ + proc_entry = create_proc_entry(FIVEWAY_PROC_FILE, 0644, NULL); + if (proc_entry == NULL) { + LLOG_ERROR("probe1", "", "Fiveway could not create proc entry\n"); + err = -ENOMEM; + goto exit_probe; + } else { + proc_entry->read_proc = fiveway_proc_read; + proc_entry->write_proc = fiveway_proc_write; + proc_entry->owner = THIS_MODULE; + } + + // Set up the necessary GPIO lines for the 5-Way inputs + err = gpio_fiveway_active(); + if (err) { + LLOG_ERROR("gpio_fail", "", "Failed to set GPIO lines\n"); + goto del_proc_entry; + } + + // Initialize the line state array + for (i = 0; i < NUM_OF_LINES; i++) { + line_state[i] = LINE_DEASSERTED; + } + + // Set IRQ for fiveway GPIO lines; trigger on falling edges + // and register the IRQ service routines + + // UP IRQ + set_irq_type(FIVEWAY_UP_IRQ, IRQF_TRIGGER_FALLING); + err = request_irq(FIVEWAY_UP_IRQ, (irq_handler_t) fiveway_irq, 0, "fiveway", NULL); + if (err != 0) { + LLOG_ERROR("up_irq", "", "UP IRQ line = 0x%X; request status = %d\n", FIVEWAY_UP_IRQ, err); + goto release_gpios; + } + + // DOWN IRQ + set_irq_type(FIVEWAY_DOWN_IRQ, IRQF_TRIGGER_FALLING); + err = request_irq(FIVEWAY_DOWN_IRQ, (irq_handler_t) fiveway_irq, 0, "fiveway", NULL); + if (err != 0) { + LLOG_ERROR("down_irq", "", "DOWN IRQ line = 0x%X; request status = %d\n", FIVEWAY_DOWN_IRQ, err); + goto release_up_irq; + } + + // LEFT IRQ + set_irq_type(FIVEWAY_LEFT_IRQ, IRQF_TRIGGER_FALLING); + err = request_irq(FIVEWAY_LEFT_IRQ, (irq_handler_t) fiveway_irq, 0, "fiveway", NULL); + if (err != 0) { + LLOG_ERROR("left_irq", "", "LEFT IRQ line = 0x%X; request status = %d\n", FIVEWAY_LEFT_IRQ, err); + goto release_down_irq; + } + + // RIGHT IRQ + set_irq_type(FIVEWAY_RIGHT_IRQ, IRQF_TRIGGER_FALLING); + err = request_irq(FIVEWAY_RIGHT_IRQ, (irq_handler_t) fiveway_irq, 0, "fiveway", NULL); + if (err != 0) { + LLOG_ERROR("right_irq", "", "RIGHT IRQ line = 0x%X; request status = %d\n", FIVEWAY_RIGHT_IRQ, err); + goto release_left_irq; + } + + // SELECT IRQ + set_irq_type(FIVEWAY_SELECT_IRQ, IRQF_TRIGGER_FALLING); + err = request_irq(FIVEWAY_SELECT_IRQ, (irq_handler_t) fiveway_irq, 0, "fiveway", NULL); + if (err != 0) { + LLOG_ERROR("select_irq", "", "SELECT IRQ line = 0x%X; request status = %d\n", FIVEWAY_SELECT_IRQ, err); + goto release_right_irq; + } + + LLOG_INFO("probe_done", "", "GPIOs and IRQs have been set up\n"); + + // Set up the device file + fiveway_dev = input_allocate_device(); + if (!fiveway_dev) { + LLOG_ERROR("allocate_dev", "", "Not enough memory for input device\n"); + err = -ENOMEM; + goto release_select_irq; + } + fiveway_dev->name = "fiveway"; + fiveway_dev->id.bustype = BUS_HOST; + fiveway_dev->open = fiveway_open; + fiveway_dev->close = fiveway_close; + fiveway_dev->evbit[0] = BIT(EV_KEY); + // Set up the keycodes sent by each of the 5-Way lines + set_bit(FIVEWAY_KEYCODE_UP, fiveway_dev->keybit); + set_bit(FIVEWAY_KEYCODE_DOWN, fiveway_dev->keybit); + set_bit(FIVEWAY_KEYCODE_LEFT, fiveway_dev->keybit); + set_bit(FIVEWAY_KEYCODE_RIGHT, fiveway_dev->keybit); + set_bit(FIVEWAY_KEYCODE_SELECT, fiveway_dev->keybit); + + // Initialize work items + INIT_DELAYED_WORK(&fiveway_up_debounce_tq_d, fiveway_up_debounce_wk); + INIT_DELAYED_WORK(&fiveway_select_debounce_tq_d, fiveway_select_debounce_wk); + INIT_DELAYED_WORK(&fiveway_right_debounce_tq_d, fiveway_right_debounce_wk); + INIT_DELAYED_WORK(&fiveway_left_debounce_tq_d, fiveway_left_debounce_wk); + INIT_DELAYED_WORK(&fiveway_down_debounce_tq_d, fiveway_down_debounce_wk); + INIT_DELAYED_WORK(&fiveway_repeat_up_tq_d, fiveway_repeat_up_work); + INIT_DELAYED_WORK(&fiveway_repeat_select_tq_d, fiveway_repeat_select_work); + INIT_DELAYED_WORK(&fiveway_repeat_right_tq_d, fiveway_repeat_right_work); + INIT_DELAYED_WORK(&fiveway_repeat_left_tq_d, fiveway_repeat_left_work); + INIT_DELAYED_WORK(&fiveway_repeat_down_tq_d, fiveway_repeat_down_work); + + err = input_register_device(fiveway_dev); + if (err) { + LLOG_ERROR("reg_dev", "", "Failed to register device\n"); + goto free_input_dev; + } + + if (device_create_file(&pdev->dev, &dev_attr_fiveway_dbg_state) < 0) + printk(KERN_ERR "Error - could not create fiveway_dbg_state file\n"); + + fiveway_initialized = 1; + + return 0; // Success! + + +free_input_dev: + input_free_device(fiveway_dev); +release_select_irq: + free_irq(FIVEWAY_SELECT_IRQ, NULL); +release_right_irq: + free_irq(FIVEWAY_RIGHT_IRQ, NULL); +release_left_irq: + free_irq(FIVEWAY_LEFT_IRQ, NULL); +release_down_irq: + free_irq(FIVEWAY_DOWN_IRQ, NULL); +release_up_irq: + free_irq(FIVEWAY_UP_IRQ, NULL); +release_gpios: + gpio_fiveway_inactive(); +del_proc_entry: + remove_proc_entry(FIVEWAY_PROC_FILE, NULL); +exit_probe: + return err; +} + + +/*! + * Dissociates the driver from the fiveway device. + * + * @param pdev the device structure used to give information on which SDHC + * to remove + * + * @return The function always returns 0. + */ +static int __devexit fiveway_remove(struct platform_device *pdev) +{ + // Release IRQs and GPIO pins; disable pullups on output GPIOs + free_irq(FIVEWAY_UP_IRQ, NULL); + free_irq(FIVEWAY_DOWN_IRQ, NULL); + free_irq(FIVEWAY_LEFT_IRQ, NULL); + free_irq(FIVEWAY_RIGHT_IRQ, NULL); + free_irq(FIVEWAY_SELECT_IRQ, NULL); + gpio_fiveway_inactive(); + + device_remove_file(&pdev->dev, &dev_attr_fiveway_dbg_state); + + // Stop any pending delayed work items + cancel_delayed_work_sync(&fiveway_up_debounce_tq_d); + cancel_delayed_work_sync(&fiveway_right_debounce_tq_d); + cancel_delayed_work_sync(&fiveway_left_debounce_tq_d); + cancel_delayed_work_sync(&fiveway_select_debounce_tq_d); + cancel_delayed_work_sync(&fiveway_down_debounce_tq_d); + cancel_delayed_work_sync(&fiveway_repeat_up_tq_d); + cancel_delayed_work_sync(&fiveway_repeat_left_tq_d); + cancel_delayed_work_sync(&fiveway_repeat_right_tq_d); + cancel_delayed_work_sync(&fiveway_repeat_select_tq_d); + cancel_delayed_work_sync(&fiveway_repeat_down_tq_d); + + remove_proc_entry(FIVEWAY_PROC_FILE, NULL); + input_unregister_device(fiveway_dev); + + LLOG_INFO("exit", "", "IRQs released and work functions stopped.\n"); + + return 0; +} + + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver fiveway_driver = { + .driver = { + .name = "fiveway", + .owner = THIS_MODULE, + }, + .suspend = fiveway_suspend, + .resume = fiveway_resume, + .probe = fiveway_probe, + .remove = fiveway_remove, +}; + +static void fiveway_device_release (struct device *dev) +{ + /* Do Nothing */ +} + +static struct platform_device fiveway_device = { + .name = "fiveway", + .id = -1, + .dev = { + .release = fiveway_device_release, + }, +}; + +/*! + * This function is called for module initialization. + * It registers the fiveway char driver. + * + * @return 0 on success and a non-zero value on failure. + */ +static int __init fiveway_init(void) +{ + LLOG_INIT(); + set_debug_log_mask(debug); + platform_device_register(&fiveway_device); + platform_driver_register(&fiveway_driver); + LLOG_INFO("drv", "", "Fiveway driver loaded\n"); + return 0; +} + +/*! + * This function is called whenever the module is removed from the kernel. It + * unregisters the fiveway driver from kernel. + */ +static void __exit fiveway_exit(void) +{ + platform_driver_unregister(&fiveway_driver); + platform_device_unregister(&fiveway_device); +} + +module_init(fiveway_init); +module_exit(fiveway_exit); + +MODULE_AUTHOR("Lab126"); +MODULE_DESCRIPTION("5-Way Input Device Driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/input/fiveway/fiveway.h linux-2.6.26-lab126/drivers/input/fiveway/fiveway.h --- linux-2.6.26/drivers/input/fiveway/fiveway.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/input/fiveway/fiveway.h 2010-08-10 04:15:44.000000000 -0400 @@ -0,0 +1,47 @@ +// +// Definitions for 5-Way Switch 5-way driver +// + +#include + +// 5-Way line enumeration +enum { + UP_LINE, + DOWN_LINE, + LEFT_LINE, + RIGHT_LINE, + SELECT_LINE +}; + +// Function that returns the IRQ number for a given 5-Way line +extern int fiveway_get_irq(int); + +// IRQ definitions, only for those inputs that generate interrupts +#define FIVEWAY_UP_IRQ fiveway_get_irq(UP_LINE) +#define FIVEWAY_DOWN_IRQ fiveway_get_irq(DOWN_LINE) +#define FIVEWAY_LEFT_IRQ fiveway_get_irq(LEFT_LINE) +#define FIVEWAY_RIGHT_IRQ fiveway_get_irq(RIGHT_LINE) +#define FIVEWAY_SELECT_IRQ fiveway_get_irq(SELECT_LINE) + +// Keycodes generated by fiveway events +#define FIVEWAY_KEYCODE_UP KEY_UP +#define FIVEWAY_KEYCODE_DOWN KEY_DOWN +#define FIVEWAY_KEYCODE_LEFT KEY_LEFT +#define FIVEWAY_KEYCODE_RIGHT KEY_RIGHT +#define FIVEWAY_KEYCODE_SELECT KEY_F24 + +// Line states +#define NUM_OF_LINES 5 +enum { + LINE_ASSERTED, + LINE_DEASSERTED, + LINE_HELD, +}; + +// External function definitions +static int __init fiveway_init(void); +static void __exit fiveway_exit(void); +static irqreturn_t fiveway_irq(int irq, void *data, struct pt_regs *r); + +extern int gpio_fiveway_active(void); +extern void gpio_fiveway_inactive(void); diff -urN linux-2.6.26/drivers/input/gameport/gameport.c linux-2.6.26-lab126/drivers/input/gameport/gameport.c --- linux-2.6.26/drivers/input/gameport/gameport.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/input/gameport/gameport.c 2010-08-10 04:15:44.000000000 -0400 @@ -20,6 +20,7 @@ #include #include #include +#include #include /* HZ */ #include #include @@ -99,12 +100,12 @@ tx = 1 << 30; for(i = 0; i < 50; i++) { - local_irq_save(flags); + local_irq_save_nort(flags); GET_TIME(t1); for (t = 0; t < 50; t++) gameport_read(gameport); GET_TIME(t2); GET_TIME(t3); - local_irq_restore(flags); + local_irq_restore_nort(flags); udelay(i * 10); if ((t = DELTA(t2,t1) - DELTA(t3,t2)) < tx) tx = t; } @@ -123,11 +124,11 @@ tx = 1 << 30; for(i = 0; i < 50; i++) { - local_irq_save(flags); + local_irq_save_nort(flags); rdtscl(t1); for (t = 0; t < 50; t++) gameport_read(gameport); rdtscl(t2); - local_irq_restore(flags); + local_irq_restore_nort(flags); udelay(i * 10); if (t2 - t1 < tx) tx = t2 - t1; } diff -urN linux-2.6.26/drivers/input/input.c linux-2.6.26-lab126/drivers/input/input.c --- linux-2.6.26/drivers/input/input.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/input/input.c 2010-08-10 04:15:44.000000000 -0400 @@ -11,6 +11,7 @@ */ #include +#include #include #include #include @@ -28,6 +29,25 @@ #define INPUT_DEVICES 256 +/* + * EV_ABS events which should not be cached are listed here. + */ +static unsigned int input_abs_bypass_init_data[] __initdata = { + ABS_MT_TOUCH_MAJOR, + ABS_MT_TOUCH_MINOR, + ABS_MT_WIDTH_MAJOR, + ABS_MT_WIDTH_MINOR, + ABS_MT_ORIENTATION, + ABS_MT_POSITION_X, + ABS_MT_POSITION_Y, + ABS_MT_TOOL_TYPE, + ABS_MT_BLOB_ID, + ABS_MT_TRACKING_ID, + 0 +}; +static unsigned long input_abs_bypass[BITS_TO_LONGS(ABS_CNT)]; + + static LIST_HEAD(input_dev_list); static LIST_HEAD(input_handler_list); @@ -131,6 +151,11 @@ } } +static void input_stop_autorepeat(struct input_dev *dev) +{ + del_timer(&dev->timer); +} + #define INPUT_IGNORE_EVENT 0 #define INPUT_PASS_TO_HANDLERS 1 #define INPUT_PASS_TO_DEVICE 2 @@ -155,6 +180,10 @@ disposition = INPUT_PASS_TO_HANDLERS; } break; + case SYN_MT_REPORT: + dev->sync = 0; + disposition = INPUT_PASS_TO_HANDLERS; + break; } break; @@ -166,6 +195,8 @@ __change_bit(code, dev->key); if (value) input_start_autorepeat(dev, code); + else + input_stop_autorepeat(dev); } disposition = INPUT_PASS_TO_HANDLERS; @@ -183,6 +214,11 @@ case EV_ABS: if (is_event_supported(code, dev->absbit, ABS_MAX)) { + + if (test_bit(code, input_abs_bypass)) { + disposition = INPUT_PASS_TO_HANDLERS; + break; + } value = input_defuzz_abs_event(value, dev->abs[code], dev->absfuzz[code]); @@ -479,7 +515,7 @@ * that there are no threads in the middle of input_open_device() */ mutex_lock(&dev->mutex); - dev->going_away = 1; + dev->going_away = true; mutex_unlock(&dev->mutex); spin_lock_irq(&dev->event_lock); @@ -1226,10 +1262,66 @@ return 0; } +#define INPUT_DO_TOGGLE(dev, type, bits, on) \ + do { \ + int i; \ + if (!test_bit(EV_##type, dev->evbit)) \ + break; \ + for (i = 0; i < type##_MAX; i++) { \ + if (!test_bit(i, dev->bits##bit) || \ + !test_bit(i, dev->bits)) \ + continue; \ + dev->event(dev, EV_##type, i, on); \ + } \ + } while (0) + +static void input_dev_reset(struct input_dev *dev, bool activate) +{ + if (!dev->event) + return; + + INPUT_DO_TOGGLE(dev, LED, led, activate); + INPUT_DO_TOGGLE(dev, SND, snd, activate); + + if (activate && test_bit(EV_REP, dev->evbit)) { + dev->event(dev, EV_REP, REP_PERIOD, dev->rep[REP_PERIOD]); + dev->event(dev, EV_REP, REP_DELAY, dev->rep[REP_DELAY]); + } +} + +#ifdef CONFIG_PM +static int input_dev_suspend(struct device *dev, pm_message_t state) +{ + struct input_dev *input_dev = to_input_dev(dev); + + mutex_lock(&input_dev->mutex); + input_dev_reset(input_dev, false); + mutex_unlock(&input_dev->mutex); + + return 0; +} + +static int input_dev_resume(struct device *dev) +{ + struct input_dev *input_dev = to_input_dev(dev); + + mutex_lock(&input_dev->mutex); + input_dev_reset(input_dev, true); + mutex_unlock(&input_dev->mutex); + + return 0; +} + +#endif /* CONFIG_PM */ + static struct device_type input_dev_type = { .groups = input_dev_attr_groups, .release = input_dev_release, .uevent = input_dev_uevent, +#ifdef CONFIG_PM + .suspend = input_dev_suspend, + .resume = input_dev_resume, +#endif }; struct class input_class = { @@ -1622,10 +1714,20 @@ .open = input_open_file, }; +static void __init input_init_abs_bypass(void) +{ + const unsigned int *p; + + for (p = input_abs_bypass_init_data; *p; p++) + input_abs_bypass[BIT_WORD(*p)] |= BIT_MASK(*p); +} + static int __init input_init(void) { int err; + input_init_abs_bypass(); + err = class_register(&input_class); if (err) { printk(KERN_ERR "input: unable to register input_dev class\n"); diff -urN linux-2.6.26/drivers/input/keyboard/Kconfig linux-2.6.26-lab126/drivers/input/keyboard/Kconfig --- linux-2.6.26/drivers/input/keyboard/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/input/keyboard/Kconfig 2010-08-10 04:15:44.000000000 -0400 @@ -268,6 +268,13 @@ To compile this driver as a module, choose M here: the module will be called pxa27x_keypad. +config KEYBOARD_MXC + tristate "MXC Keypad Driver" + depends on ARCH_MXC + help + This is the Keypad driver for the Freescale MXC application + processors. + config KEYBOARD_AAED2000 tristate "AAED-2000 keyboard" depends on MACH_AAED2000 @@ -314,6 +321,13 @@ To compile this driver as a module, choose M here: the module will be called bf54x-keys. +config KEYBOARD_MPR084 + tristate "Freescale MPR084 Touch Keypad Driver" + depends on ARCH_MX37 + help + This is the Keypad driver for the Freescale Proximity Capacitive + Touch Sensor controller chip. + config KEYBOARD_SH_KEYSC tristate "SuperH KEYSC keypad support" depends on SUPERH @@ -321,6 +335,7 @@ Say Y here if you want to use a keypad attached to the KEYSC block on SuperH processors such as sh7722 and sh7343. + To compile this driver as a module, choose M here: the module will be called sh_keysc. endif diff -urN linux-2.6.26/drivers/input/keyboard/Makefile linux-2.6.26-lab126/drivers/input/keyboard/Makefile --- linux-2.6.26/drivers/input/keyboard/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/input/keyboard/Makefile 2010-08-10 04:15:44.000000000 -0400 @@ -18,6 +18,7 @@ obj-$(CONFIG_KEYBOARD_TOSA) += tosakbd.o obj-$(CONFIG_KEYBOARD_HIL) += hil_kbd.o obj-$(CONFIG_KEYBOARD_HIL_OLD) += hilkbd.o +obj-$(CONFIG_KEYBOARD_MXC) += mxc_keyb.o obj-$(CONFIG_KEYBOARD_OMAP) += omap-keypad.o obj-$(CONFIG_KEYBOARD_PXA27x) += pxa27x_keypad.o obj-$(CONFIG_KEYBOARD_AAED2000) += aaed2000_kbd.o @@ -26,4 +27,5 @@ obj-$(CONFIG_KEYBOARD_HP7XX) += jornada720_kbd.o obj-$(CONFIG_KEYBOARD_MAPLE) += maple_keyb.o obj-$(CONFIG_KEYBOARD_BFIN) += bf54x-keys.o -obj-$(CONFIG_KEYBOARD_SH_KEYSC) += sh_keysc.o +obj-$(CONFIG_KEYBOARD_MPR084) += mpr084.o +obj-$(CONFIG_KEYBOARD_SH_KEYSC) += sh_keysc.o \ No newline at end of file diff -urN linux-2.6.26/drivers/input/keyboard/atkbd.c linux-2.6.26-lab126/drivers/input/keyboard/atkbd.c --- linux-2.6.26/drivers/input/keyboard/atkbd.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/input/keyboard/atkbd.c 2010-08-10 04:15:44.000000000 -0400 @@ -1455,8 +1455,23 @@ { } }; +static int __read_mostly noatkbd; + +static int __init noatkbd_setup(char *str) +{ + noatkbd = 1; + printk(KERN_INFO "debug: not setting up AT keyboard.\n"); + + return 1; +} + +__setup("noatkbd", noatkbd_setup); + static int __init atkbd_init(void) { + if (noatkbd) + return 0; + dmi_check_system(atkbd_dmi_quirk_table); return serio_register_driver(&atkbd_drv); diff -urN linux-2.6.26/drivers/input/keyboard/mpr084.c linux-2.6.26-lab126/drivers/input/keyboard/mpr084.c --- linux-2.6.26/drivers/input/keyboard/mpr084.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/input/keyboard/mpr084.c 2010-08-10 04:15:44.000000000 -0400 @@ -0,0 +1,508 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file linux/drivers/input/keyboard/mpr084.c + * + * @brief Driver for the Freescale MPR084 I2C Touch Sensor KeyPad module. + * + * + * + * @ingroup Keypad + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Definitions + */ +#define DEBUG 0 + +#define KEY_COUNT 8 + +/* + *Registers in MPR084 + */ +#define MPR084_FIFO_ADDR 0x00 +#define MPR084_FAULT_ADDR 0x01 +#define MPR084_TPS_ADDR 0x02 +#define MPR084_TPC_ADDR 0x03 +#define MPR084_STR1_ADDR 0x04 +#define MPR084_STR2_ADDR 0x05 +#define MPR084_STR3_ADDR 0x06 +#define MPR084_STR4_ADDR 0x07 +#define MPR084_STR5_ADDR 0x08 +#define MPR084_STR6_ADDR 0x09 +#define MPR084_STR7_ADDR 0x0A +#define MPR084_STR8_ADDR 0x0B +#define MPR084_ECEM_ADDR 0x0C +#define MPR084_MNTP_ADDR 0x0D +#define MPR084_MTC_ADDR 0x0E +#define MPR084_TASP_ADDR 0x0F +#define MPR084_SC_ADDR 0x10 +#define MPR084_LPC_ADDR 0x11 +#define MPR084_SKT_ADDR 0x12 +#define MPR084_CONFIG_ADDR 0x13 +#define MPR084_SI_ADDR 0x14 +#define MPR084_ADDR_MINI MPR084_FIFO_ADDR +#define MPR084_ADDR_MAX MPR084_SI_ADDR + +/* FIFO registers */ +#define MPR084_FIFO_MORE_DATA_FLAG 0x80 +#define MPR084_FIFO_NO_DATA_FLAG 0x40 +#define MPR084_FIFO_OVERFLOW_FLAG 0x20 +#define MPR084_FIFO_PAD_IS_TOUCHED 0x10 +#define MPR084_FIFO_POSITION_MASK 0x0F + +#define DRIVER_NAME "mpr084" + +struct mpr084_data { + struct i2c_client *client; + struct device_driver driver; + struct input_dev *idev; + struct task_struct *tstask; + struct completion kpirq_completion; + int kpirq; + int kp_thread_cnt; + int opened; +}; + +static int kpstatus[KEY_COUNT]; +static struct mxc_keyp_platform_data *keypad; +static const unsigned short *mxckpd_keycodes; +static struct regulator *vdd_reg; + +static int mpr084_read_register(struct mpr084_data *data, + unsigned char regaddr, int *value) +{ + int ret = 0; + unsigned char regvalue; + + ret = i2c_master_send(data->client, ®addr, 1); + if (ret < 0) + goto err; + udelay(20); + ret = i2c_master_recv(data->client, ®value, 1); + if (ret < 0) + goto err; + *value = regvalue; + + return ret; +err: + return -ENODEV; +} + +static int mpr084_write_register(struct mpr084_data *data, + u8 regaddr, u8 regvalue) +{ + int ret = 0; + unsigned char msgbuf[2]; + + msgbuf[0] = regaddr; + msgbuf[1] = regvalue; + ret = i2c_master_send(data->client, msgbuf, 2); + if (ret < 0) { + printk(KERN_ERR "%s - Error in writing to I2C Register %d \n", + __func__, regaddr); + return ret; + } + + return ret; +} + + +static irqreturn_t mpr084_keypadirq(int irq, void *v) +{ + struct mpr084_data *d = v; + + disable_irq(d->kpirq); + complete(&d->kpirq_completion); + return IRQ_HANDLED; +} + +static int mpr084ts_thread(void *v) +{ + struct mpr084_data *d = v; + int ret = 0, fifo = 0; + int index = 0, currentstatus = 0; + + if (d->kp_thread_cnt) + return -EINVAL; + d->kp_thread_cnt = 1; + while (1) { + + if (kthread_should_stop()) + break; + /* Wait for keypad interrupt */ + if (wait_for_completion_interruptible_timeout + (&d->kpirq_completion, HZ) <= 0) + continue; + + ret = mpr084_read_register(d, MPR084_FIFO_ADDR, &fifo); + if (ret < 0) { + printk(KERN_ERR + "%s: Err in reading keypad FIFO register \n\n", + __func__); + } else { + if (fifo & MPR084_FIFO_OVERFLOW_FLAG) + printk(KERN_ERR + "%s: FIFO overflow \n\n", __func__); + while (!(fifo & MPR084_FIFO_NO_DATA_FLAG)) { + index = fifo & MPR084_FIFO_POSITION_MASK; + currentstatus = + fifo & MPR084_FIFO_PAD_IS_TOUCHED; + /*Scan key map for changes */ + if ((currentstatus) ^ (kpstatus[index])) { + if (!(currentstatus)) { + /*Key released. */ + input_event(d->idev, EV_KEY, + mxckpd_keycodes + [index], 0); + } else { + /* Key pressed. */ + input_event(d->idev, EV_KEY, + mxckpd_keycodes + [index], 1); + } + /*Store current keypad status */ + kpstatus[index] = currentstatus; + } + mpr084_read_register(d, MPR084_FIFO_ADDR, + &fifo); + if (fifo & MPR084_FIFO_OVERFLOW_FLAG) + printk(KERN_ERR + "%s: FIFO overflow \n\n", + __func__); + } + } + /* Re-enable interrupts */ + enable_irq(d->kpirq); + } + + d->kp_thread_cnt = 0; + return 0; +} + +/*! + * This function puts the Keypad controller in low-power mode/state. + * + * @param pdev the device structure used to give information on Keypad + * to suspend + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int mpr084_suspend(struct i2c_client *client, pm_message_t state) +{ + struct mpr084_data *d = i2c_get_clientdata(client); + + if (!IS_ERR(d->tstask) && d->opened) + kthread_stop(d->tstask); + + return 0; +} + +/*! + * This function brings the Keypad controller back from low-power state. + * + * @param pdev the device structure used to give information on Keypad + * to resume + * + * @return The function always returns 0. + */ +static int mpr084_resume(struct i2c_client *client) +{ + struct mpr084_data *d = i2c_get_clientdata(client); + + if (d->opened) + d->tstask = kthread_run(mpr084ts_thread, d, DRIVER_NAME "kpd"); + + return 0; +} + +static int mpr084_idev_open(struct input_dev *idev) +{ + struct mpr084_data *d = input_get_drvdata(idev); + int ret = 0; + + d->tstask = kthread_run(mpr084ts_thread, d, DRIVER_NAME "kpd"); + if (IS_ERR(d->tstask)) + ret = PTR_ERR(d->tstask); + else + d->opened++; + return ret; +} + +static void mpr084_idev_close(struct input_dev *idev) +{ + struct mpr084_data *d = input_get_drvdata(idev); + + if (!IS_ERR(d->tstask)) + kthread_stop(d->tstask); + if (d->opened > 0) + d->opened--; +} + +static int mpr084_driver_register(struct mpr084_data *data) +{ + struct input_dev *idev; + int ret = 0; + + if (data->kpirq) { + ret = + request_irq(data->kpirq, mpr084_keypadirq, + IRQF_TRIGGER_FALLING, DRIVER_NAME, data); + if (!ret) { + init_completion(&data->kpirq_completion); + set_irq_wake(data->kpirq, 1); + } else { + printk(KERN_ERR "%s: cannot grab irq %d\n", + __func__, data->kpirq); + } + + } + idev = input_allocate_device(); + data->idev = idev; + input_set_drvdata(idev, data); + idev->name = DRIVER_NAME; + idev->open = mpr084_idev_open; + idev->close = mpr084_idev_close; + if (!ret) + ret = input_register_device(idev); + + return ret; +} + +static int mpr084_i2c_remove(struct i2c_client *client) +{ + int err; + struct mpr084_data *d = i2c_get_clientdata(client); + + free_irq(d->kpirq, d); + input_unregister_device(d->idev); + if (keypad->inactive) + keypad->inactive(); + + /*Disable the Regulator*/ + if (keypad->vdd_reg) { + regulator_disable(vdd_reg); + regulator_put(vdd_reg, &client->dev); + } + + err = i2c_detach_client(client); + if (err) { + dev_err(&client->dev, "Client deregistration failed, " + "client not detached.\n"); + return err; + } + + return 0; +} + +static int mpr084_configure(struct mpr084_data *data) +{ + int ret = 0, regValue = 0; + + ret = mpr084_write_register(data, MPR084_TPC_ADDR, 0x1d); + if (ret < 0) + goto err; + ret = mpr084_write_register(data, MPR084_STR1_ADDR, 0x10); + if (ret < 0) + goto err; + ret = mpr084_write_register(data, MPR084_STR2_ADDR, 0x10); + if (ret < 0) + goto err; + ret = mpr084_write_register(data, MPR084_STR3_ADDR, 0x10); + if (ret < 0) + goto err; + ret = mpr084_write_register(data, MPR084_STR4_ADDR, 0x10); + if (ret < 0) + goto err; + ret = mpr084_write_register(data, MPR084_STR5_ADDR, 0x10); + if (ret < 0) + goto err; + ret = mpr084_write_register(data, MPR084_STR6_ADDR, 0x10); + if (ret < 0) + goto err; + ret = mpr084_write_register(data, MPR084_STR7_ADDR, 0x10); + if (ret < 0) + goto err; + ret = mpr084_write_register(data, MPR084_STR8_ADDR, 0x10); + if (ret < 0) + goto err; + /* channel enable mask: enable all */ + ret = mpr084_write_register(data, MPR084_ECEM_ADDR, 0xff); + if (ret < 0) + goto err; + /*two conccurrent touch position allowed */ + ret = mpr084_write_register(data, MPR084_MNTP_ADDR, 0x02); + if (ret < 0) + goto err; + + /* master tick period*/ + ret = mpr084_write_register(data, MPR084_MTC_ADDR, 0x05); + if (ret < 0) + goto err; + + + /*Sample period */ + ret = mpr084_write_register(data, MPR084_TASP_ADDR, 0x02); + if (ret < 0) + goto err; + + + /* disable sournder*/ + ret = mpr084_write_register(data, MPR084_SC_ADDR, 0x00); + if (ret < 0) + goto err; + + /* stuck key timeout */ + ret = mpr084_write_register(data, MPR084_SKT_ADDR, 0x01); + if (ret < 0) + goto err; + + /*enabled IRQEN, RUNE, IRQR */ + ret = mpr084_read_register(data, MPR084_CONFIG_ADDR, ®Value); + if (ret < 0) { + printk(KERN_ERR + "%s: Err in reading keypad CONFIGADDR register \n\n", + __func__); + goto err; + } + regValue |= 0x03; + ret = mpr084_write_register(data, MPR084_CONFIG_ADDR, regValue); + if (ret < 0) + goto err; + return ret; +err: + return -ENODEV; +} + +static int mpr084_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + struct mpr084_data *data; + int err = 0, i = 0; +#if DEBUG + int regValue = 0; +#endif + data = kzalloc(sizeof(struct mpr084_data), GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + i2c_set_clientdata(client, data); + data->client = client; + data->kpirq = client->irq; + err = mpr084_driver_register(data); + if (err < 0) + goto exit_free; + keypad = (struct mxc_keyp_platform_data *)(client->dev).platform_data; + if (keypad->active) + keypad->active(); + + /*Enable the Regulator*/ + if (keypad && keypad->vdd_reg) { + vdd_reg = regulator_get(&client->dev, keypad->vdd_reg); + if (!IS_ERR(vdd_reg)) + regulator_enable(vdd_reg); + else + vdd_reg = NULL; + } else + vdd_reg = NULL; + + mxckpd_keycodes = keypad->matrix; + data->idev->keycode = &mxckpd_keycodes; + data->idev->keycodesize = sizeof(unsigned char); + data->idev->keycodemax = KEY_COUNT; + data->idev->id.bustype = BUS_I2C; + __set_bit(EV_KEY, data->idev->evbit); + for (i = 0; i < 8; i++) + __set_bit(mxckpd_keycodes[i], data->idev->keybit); + err = mpr084_configure(data); + if (err == -ENODEV) { + free_irq(data->kpirq, data); + input_unregister_device(data->idev); + goto exit_free; + } + +#if DEBUG + for (i = MPR084_ADDR_MINI; i <= MPR084_ADDR_MAX; i++) { + err = mpr084_read_register(data, i, ®Value); + if (err < 0) { + printk(KERN_ERR + "%s: Err in reading keypad CONFIGADDR register \n\n", + __func__); + goto exit_free; + } + printk("MPR084 Register id: %d, Value:%d \n", i, regValue); + + } +#endif + memset(kpstatus, 0, sizeof(kpstatus)); + printk(KERN_INFO "%s: Device Attached\n", __func__); + return 0; +exit_free: + /*disable the Regulator*/ + if (vdd_reg) { + regulator_disable(vdd_reg); + regulator_put(vdd_reg, &client->dev); + vdd_reg = NULL; + } + kfree(data); + return err; +} + +static const struct i2c_device_id mpr084_id[] = { + { "mpr084", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, mpr084_id); + +static struct i2c_driver mpr084_driver = { + .driver = { + .name = DRIVER_NAME, + }, + .probe = mpr084_i2c_probe, + .remove = mpr084_i2c_remove, + .suspend = mpr084_suspend, + .resume = mpr084_resume, + .command = NULL, + .id_table = mpr084_id, +}; +static int __init mpr084_init(void) +{ + return i2c_add_driver(&mpr084_driver); +} + +static void __exit mpr084_exit(void) +{ + i2c_del_driver(&mpr084_driver); +} + +MODULE_AUTHOR("Freescale Semiconductor Inc"); +MODULE_DESCRIPTION("MPR084 Touch KeyPad Controller driver"); +MODULE_LICENSE("GPL"); +module_init(mpr084_init); +module_exit(mpr084_exit); diff -urN linux-2.6.26/drivers/input/keyboard/mxc_keyb.c linux-2.6.26-lab126/drivers/input/keyboard/mxc_keyb.c --- linux-2.6.26/drivers/input/keyboard/mxc_keyb.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/input/keyboard/mxc_keyb.c 2010-08-10 04:15:44.000000000 -0400 @@ -0,0 +1,1470 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2009 Amazon Technologies, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_keyb.c + * + * @brief Driver for the Freescale Semiconductor MXC keypad port. + * + * The keypad driver is designed as a standard Input driver which interacts + * with low level keypad port hardware. Upon opening, the Keypad driver + * initializes the keypad port. When the keypad interrupt happens the driver + * calles keypad polling timer and scans the keypad matrix for key + * press/release. If all key press/release happened it comes out of timer and + * waits for key press interrupt. The scancode for key press and release events + * are passed to Input subsytem. + * + * @ingroup keypad + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// Logging +static unsigned int logging_mask; +#define LLOG_G_LOG_MASK logging_mask +#define LLOG_KERNEL_COMP "mxc_keyb" +#include + + +/* + * Module header file + */ +#include "mxc_keyb.h" + +/*! + * This structure holds the keypad private data structure. + */ +static struct keypad_priv kpp_dev; + +/*! Input device structure. */ +static struct input_dev *mxckbd_dev = NULL; + +/*! Proc entry structure and global variable. */ +#define KEYPAD_PROC_FILE "keypad" +#define PROC_CMD_LEN 50 +static struct proc_dir_entry *proc_entry; +static bool keypad_lock = false; // Is the keypad locked or not + +/*! KPP clock handle. */ +static struct clk *kpp_clk; + +/*! This static variable indicates whether a key event is pressed/released. */ +static unsigned short KPress; + +/*! This static variable is used for the ALT key state machine. */ +enum AltState ALT_state = AltStateStart; + +/*! ALT stickiness timeout in milliseconds. */ +static atomic_t alt_sticky_timeout = ATOMIC_INIT(2000); + +static unsigned long sticky_alt_jiffies; + +/*! cur_rcmap and prev_rcmap array is used to detect key press and release. */ +static unsigned short *cur_rcmap; /* max 64 bits (8x8 matrix) */ +static unsigned short *prev_rcmap; + +/*! + * Debounce polling period(10ms) in system ticks. + */ +static unsigned short KScanRate = (10 * HZ) / 1000; + +static struct keypad_data *keypad; + +static void mxc_kp_tq(struct work_struct *); + +static ssize_t +show_alt_timer(struct device *dev, struct device_attribute *attr, char *buf); +static ssize_t +store_alt_timer(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); +static DEVICE_ATTR(alt_timer, 0644, show_alt_timer, store_alt_timer); + +/*! + * These arrays are used to store press and release scancodes. + */ +static short **press_scancode; +static short **release_scancode; + +static const unsigned short *mxckpd_keycodes; +static unsigned short mxckpd_keycodes_size; + +/*! + * Keycode press counters + */ +#define MAX_CODES 256 +static int keycode_count[MAX_CODES]; + + +#define press_left_code 30 +#define press_right_code 29 +#define press_up_code 28 +#define press_down_code 27 + +#define rel_left_code 158 +#define rel_right_code 157 +#define rel_up_code 156 +#define rel_down_code 155 + +// Module parameters + +#define REPEAT_DELAY_DEFAULT 1000 +static int repeat_delay = REPEAT_DELAY_DEFAULT; +module_param(repeat_delay, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(repeat_delay, "Delay between key press and start of repeat functionality, in msec (default is 1000)"); + +#define REPEAT_PERIOD_DEFAULT 200 +static int repeat_period = REPEAT_PERIOD_DEFAULT; +module_param(repeat_period, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(repeat_period, "Delay between repeat-key events, in msec (default is 200)"); + +static int debug = 0; +module_param(debug, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(debug, "Enable debugging; 0=off, any other value=on (default is off)"); + + +/* + * Set the log mask depending on the debug level + */ +static void set_debug_log_mask(int debug_level) +{ + logging_mask = LLOG_LEVEL_MASK_INFO | LLOG_LEVEL_MASK_EXCEPTIONS; + switch (debug_level) { + case 10: logging_mask |= LLOG_LEVEL_DEBUG9; + case 9: logging_mask |= LLOG_LEVEL_DEBUG8; + case 8: logging_mask |= LLOG_LEVEL_DEBUG7; + case 7: logging_mask |= LLOG_LEVEL_DEBUG6; + case 6: logging_mask |= LLOG_LEVEL_DEBUG5; + case 5: logging_mask |= LLOG_LEVEL_DEBUG4; + case 4: logging_mask |= LLOG_LEVEL_DEBUG3; + case 3: logging_mask |= LLOG_LEVEL_DEBUG2; + case 2: logging_mask |= LLOG_LEVEL_DEBUG1; + case 1: logging_mask |= LLOG_LEVEL_DEBUG0; + + case 0: + default: ; // No logging if debug_level <= 0 or > 10 + } +} + + +/*! + * These functions are used to configure and the GPIO pins for keypad to + * activate and deactivate it. + */ +extern int gpio_keypad_active(void); +extern void gpio_keypad_inactive(void); + + +/** +* This is a wrapper for input_event. In addition to calling +* input_event, this function also sends a uevent for any +* processes listening in the userspace +*/ +void report_event(struct input_dev *dev, unsigned int type, unsigned int code, int value ) +{ + // Send key input event + input_event( dev, type, code, value ); + + // Send uevent so userspace power daemon can monitor + // keyboard activity. NOTE - the keycode is not sent through + // this medium; only the fact that a key event has happened. + // NOTE: only sending uevent on key down. + if (value == 1) { + if( kobject_uevent_atomic( &dev->dev.kobj, KOBJ_CHANGE ) ) + { + LLOG_ERROR("uevent", "", "Keyboard failed to send uevent\n" ); + } + // Increment keycode counter + if ((code >= 0) && (code < MAX_CODES)) { + keycode_count[code]++; + } + } +} + +/* + * Send the repeat key events + */ + +static void input_repeat_key(unsigned long data) +{ + struct input_dev *dev = (void *) data; + + if (!test_bit(dev->repeat_key, dev->key)) + return; + + report_event(dev, EV_KEY, dev->repeat_key, 2); + + // Make sure we have the most recent repeat period - this way + // it could be changed dynamically during a repeat sequence + mxckbd_dev->rep[REP_PERIOD] = repeat_period; + if (dev->rep[REP_PERIOD]) { + mod_timer(&dev->timer, jiffies + msecs_to_jiffies(dev->rep[REP_PERIOD])); + } +} + + +/*! + * For now, do mapping for top-row keys which are numeric when ALT is pressed. + */ +unsigned int alt_convert(unsigned int keycode) { + switch (keycode) { + case KEY_Q: + return KEY_1; + break; + case KEY_W: + return KEY_2; + break; + case KEY_E: + return KEY_3; + break; + case KEY_R: + return KEY_4; + break; + case KEY_T: + return KEY_5; + break; + case KEY_Y: + return KEY_6; + break; + case KEY_U: + return KEY_7; + break; + case KEY_I: + return KEY_8; + break; + case KEY_O: + return KEY_9; + break; + case KEY_P: + return KEY_0; + break; + default: + return keycode; + break; + } +} + + +/*! + * This function is called to scan the keypad matrix to find out the key press + * and key release events. Make scancode and break scancode are generated for + * key press and key release events. + * + * The following scanning sequence are done for + * keypad row and column scanning, + * -# Write 1's to KPDR[15:8], setting column data to 1's + * -# Configure columns as totem pole outputs(for quick discharging of keypad + * capacitance) + * -# Configure columns as open-drain + * -# Write a single column to 0, others to 1. + * -# Sample row inputs and save data. Multiple key presses can be detected on + * a single column. + * -# Repeat steps the above steps for remaining columns. + * -# Return all columns to 0 in preparation for standby mode. + * -# Clear KPKD and KPKR status bit(s) by writing to a 1, + * Set the KPKR synchronizer chain by writing "1" to KRSS register, + * Clear the KPKD synchronizer chain by writing "1" to KDSC register + * + * @result Number of key pressed/released. + */ +static int mxc_kpp_scan_matrix(void) +{ + unsigned short reg_val; + int col, row; + short scancode = 0; + unsigned int keycode = 0; + unsigned int alt_keycode = 0; + int keycnt = 0; /* How many keys are still pressed */ + + /* + * wmb() linux kernel function which guarantees orderings in write + * operations + */ + wmb(); + + /* save cur keypad matrix to prev */ + + memcpy(prev_rcmap, cur_rcmap, kpp_dev.kpp_rows * sizeof(prev_rcmap[0])); + memset(cur_rcmap, 0, kpp_dev.kpp_rows * sizeof(cur_rcmap[0])); + + for (col = 0; col < kpp_dev.kpp_cols; col++) { /* Col */ + /* 2. Write 1.s to KPDR[15:8] setting column data to 1.s */ + reg_val = __raw_readw(KPDR); + reg_val |= 0xff00; + __raw_writew(reg_val, KPDR); + + /* + * 3. Configure columns as totem pole outputs(for quick + * discharging of keypad capacitance) + */ + reg_val = __raw_readw(KPCR); + reg_val &= 0x00ff; + __raw_writew(reg_val, KPCR); + + udelay(2); + + /* + * 4. Configure columns as open-drain + */ + reg_val = __raw_readw(KPCR); + reg_val |= ((1 << kpp_dev.kpp_cols) - 1) << 8; + __raw_writew(reg_val, KPCR); + + /* + * 5. Write a single column to 0, others to 1. + * 6. Sample row inputs and save data. Multiple key presses + * can be detected on a single column. + * 7. Repeat steps 2 - 6 for remaining columns. + */ + + /* Col bit starts at 8th bit in KPDR */ + reg_val = __raw_readw(KPDR); + reg_val &= ~(1 << (8 + col)); + __raw_writew(reg_val, KPDR); + + /* Delay added to avoid propagating the 0 from column to row + * when scanning. */ + + udelay(5); + + /* Read row input */ + reg_val = __raw_readw(KPDR); + for (row = 0; row < kpp_dev.kpp_rows; row++) { /* sample row */ + if (TEST_BIT(reg_val, row) == 0) { + cur_rcmap[row] = BITSET(cur_rcmap[row], col); + keycnt++; + } + } + } + + /* + * 8. Return all columns to 0 in preparation for standby mode. + * 9. Clear KPKD and KPKR status bit(s) by writing to a .1., + * set the KPKR synchronizer chain by writing "1" to KRSS register, + * clear the KPKD synchronizer chain by writing "1" to KDSC register + */ + reg_val = 0x00; + __raw_writew(reg_val, KPDR); + reg_val = __raw_readw(KPDR); + reg_val = __raw_readw(KPSR); + reg_val |= KBD_STAT_KPKD | KBD_STAT_KPKR | KBD_STAT_KRSS | + KBD_STAT_KDSC; + __raw_writew(reg_val, KPSR); + + /* Check key press status change */ + + /* + * prev_rcmap array will contain the previous status of the keypad + * matrix. cur_rcmap array will contains the present status of the + * keypad matrix. If a bit is set in the array, that (row, col) bit is + * pressed, else it is not pressed. + * + * XORing these two variables will give us the change in bit for + * particular row and column. If a bit is set in XOR output, then that + * (row, col) has a change of status from the previous state. From + * the diff variable the key press and key release of row and column + * are found out. + * + * If the key press is determined then scancode for key pressed + * can be generated using the following statement: + * scancode = ((row * 8) + col); + * + * If the key release is determined then scancode for key release + * can be generated using the following statement: + * scancode = ((row * 8) + col) + MXC_KEYRELEASE; + */ + for (row = 0; row < kpp_dev.kpp_rows; row++) { + unsigned char diff; + + /* + * Calculate the change in the keypad row status + */ + diff = prev_rcmap[row] ^ cur_rcmap[row]; + + for (col = 0; col < kpp_dev.kpp_cols; col++) { + if ((diff >> col) & 0x1) { + /* There is a status change on col */ + if ((prev_rcmap[row] & BITSET(0, col)) == 0) { + /* + * Previous state is 0, so now a key is pressed + */ + scancode = ((row * kpp_dev.kpp_cols) + col); + KPress = 1; + kpp_dev.iKeyState = KStateUp; + LLOG_DEBUG0("Press (%d, %d) scan=%d Kpress=%d\n", + row, col, scancode, KPress); + press_scancode[row][col] = (short)scancode; + } + else { + /* + * Previous state is not 0, so now a key is released + */ + scancode = (row*kpp_dev.kpp_cols) + col + MXC_KEYRELEASE; + KPress = 0; + kpp_dev.iKeyState = KStateDown; + LLOG_DEBUG0("Release (%d, %d) scan=%d Kpress=%d\n", + row, col, scancode, KPress); + release_scancode[row][col] = (short)scancode; + keycnt++; + } + } + } + } + + /* + * This switch case statement is the implementation of state machine + * of debounce logic for key press/release. The explaination of + * state machine is as follows: + * + * KStateUp State: + * This is in intial state of the state machine this state it checks + * for any key presses. The key press can be checked using the + * variable KPress. If KPress is set, then key press is identified + * and switches the to KStateFirstDown state for key press to debounce. + * + * KStateFirstDown: + * After debounce delay(10ms), if the KPress is still set then pass + * scancode generated to input device and change the state to + * KStateDown, else key press debounce is not satisfied so change + * the state to KStateUp. + * + * KStateDown: + * In this state it checks for any key release. If KPress variable + * is cleared, then key release is indicated and so, switch the + * state to KStateFirstUp else to state KStateDown. + * + * KStateFirstUp: + * After debounce delay(10ms), if the KPress is still reset then pass + * the key release scancode to input device and change the state to + * KStateUp else key release is not satisfied so change the state to + * KStateDown. + */ + switch (kpp_dev.iKeyState) { + case KStateUp: + if (KPress) { + /* First Down (must debounce). */ + kpp_dev.iKeyState = KStateFirstDown; + } + else { + /* Still UP.(NO Changes) */ + kpp_dev.iKeyState = KStateUp; + } + break; + + case KStateFirstDown: + if (KPress) { + for (row = 0; row < kpp_dev.kpp_rows; row++) { + for (col = 0; col < kpp_dev.kpp_cols; col++) { + if ((press_scancode[row][col] != -1)) { + unsigned long end_sticky = msecs_to_jiffies(atomic_read(&alt_sticky_timeout)) + sticky_alt_jiffies; + + /* Still Down, so add scancode */ + scancode = press_scancode[row][col]; + // Make sure we have the latest repeat delay + mxckbd_dev->rep[REP_DELAY] = repeat_delay; + // Get the keycode from the mapping + keycode = mxckpd_keycodes[scancode]; + alt_keycode = alt_convert(keycode); + + //Did the timer expire and we are still in the "Sticky ALT" state? + if (ALT_state == AltStateSticky && end_sticky != sticky_alt_jiffies && time_after(jiffies, end_sticky)) { + ALT_state = AltStateStart; + } + + // ALT key state machine - press + switch (ALT_state) { + case AltStateStart: + if (keycode == KEY_LEFTALT) { + // First press of ALT; no codes sent; change state + ALT_state = AltStateFirstDown; + } + else { + // Not ALT; send the appropriate keycode + report_event(mxckbd_dev, EV_KEY, keycode, 1); + } + break; + case AltStateFirstDown: + if (keycode == alt_keycode) { + // Not a special numeric ALT+key + // Send the ALT key we had previously detected + report_event(mxckbd_dev, EV_KEY, KEY_LEFTALT, 1); + } + keycode = alt_keycode; + // Send the appropriate keycode + report_event(mxckbd_dev, EV_KEY, keycode, 1); + // Go to next state + ALT_state = AltStateDown; + break; + case AltStateDown: + if (keycode != alt_keycode) { + // This is a special numeric ALT+key + // Send a fake ALT release before sending + report_event(mxckbd_dev, EV_KEY, KEY_LEFTALT, 0); + // Send the appropriate keycode + keycode = alt_keycode; + report_event(mxckbd_dev, EV_KEY, keycode, 1); + } + else { + // Send a fake ALT down in case the + // ALT number processing cleared it + report_event(mxckbd_dev, EV_KEY, KEY_LEFTALT, 1); + // Send the keycode + report_event(mxckbd_dev, EV_KEY, keycode, 1); + } + // We stay in the same state; only ALT release + // can take us out of this state + break; + case AltStateSticky: + if (keycode == KEY_LEFTALT) { + // ALT was pushed, released, and pushed again + ALT_state = AltStateFirstDown; + } + else { + if (keycode == alt_keycode) { + // Not a special numeric ALT+key + // Send the ALT key we had previously detected + report_event(mxckbd_dev, EV_KEY, KEY_LEFTALT, 1); + // Send the appropriate keycode and release both + report_event(mxckbd_dev, EV_KEY, keycode, 1); + report_event(mxckbd_dev, EV_KEY, keycode, 0); + report_event(mxckbd_dev, EV_KEY, KEY_LEFTALT, 0); + } + else { + // Send the appropriate numeric keycode + // and release it (this avoids a new state) + keycode = alt_keycode; + report_event(mxckbd_dev, EV_KEY, keycode, 1); + report_event(mxckbd_dev, EV_KEY, keycode, 0); + } + // Go back to Start - end of stickyness + ALT_state = AltStateStart; + } + break; + default: + // Invalid state; reset + ALT_state = AltStateStart; + // Send the keycode + report_event(mxckbd_dev, EV_KEY, keycode, 1); + break; + } + kpp_dev.iKeyState = KStateDown; + press_scancode[row][col] = -1; + } + } + } + } + else { + /* Just a bounce */ + kpp_dev.iKeyState = KStateUp; + } + break; + + case KStateDown: + if (KPress) { + /* Still down (no change) */ + kpp_dev.iKeyState = KStateDown; + } + else { + /* First Up. Must debounce */ + kpp_dev.iKeyState = KStateFirstUp; + } + break; + + case KStateFirstUp: + if (KPress) { + /* Just a bounce */ + kpp_dev.iKeyState = KStateDown; + } + else { + for (row = 0; row < kpp_dev.kpp_rows; row++) { + for (col = 0; col < kpp_dev.kpp_cols; col++) { + if ((release_scancode[row][col] != -1)) { + scancode = release_scancode[row][col]- MXC_KEYRELEASE; + // Get the keycode from the mapping + keycode = mxckpd_keycodes [scancode]; + alt_keycode = alt_convert(keycode); + + // ALT key state machine - release + switch (ALT_state) { + case AltStateStart: + // Send the key release event; no state change + report_event(mxckbd_dev, EV_KEY, keycode, 0); + report_event(mxckbd_dev, EV_KEY, alt_keycode, 0); + break; + case AltStateFirstDown: + if (keycode == KEY_LEFTALT) { + // Going into ALT sticky state; send nothing + ALT_state = AltStateSticky; + sticky_alt_jiffies = jiffies; + } + else { + // Send the appropriate release keycode + report_event(mxckbd_dev, EV_KEY, keycode, 0); + // Go to next state + ALT_state = AltStateDown; + } + break; + case AltStateDown: + if (keycode == KEY_LEFTALT) { + // Released ALT key + report_event(mxckbd_dev, EV_KEY, KEY_LEFTALT, 0); + ALT_state = AltStateStart; + } + else if (keycode != alt_keycode) { + // This is a special numeric ALT+key + // Send a fake ALT release before sending + report_event(mxckbd_dev, EV_KEY, KEY_LEFTALT, 0); + // Send the appropriate keycode + keycode = alt_keycode; + report_event(mxckbd_dev, EV_KEY, keycode, 0); + } + else { + // Send the keycode release + report_event(mxckbd_dev, EV_KEY, keycode, 0); + } + // We stay in the same state; only ALT release + // can take us out of this state + break; + case AltStateSticky: + // We only get to this state if the sequence is: + // key down - ALT down - ALT up - key up + // We do no special ALT treatment; just ignore it + // Send the keycode release + report_event(mxckbd_dev, EV_KEY, keycode, 0); + // Go back to Start + ALT_state = AltStateStart; + break; + default: + // Invalid state; reset + ALT_state = AltStateStart; + // Send the keycode + report_event(mxckbd_dev, EV_KEY, keycode, 0); + break; + } + kpp_dev.iKeyState = KStateUp; + release_scancode[row][col] = -1; + } + } + } + } + break; + + default: + return -EBADRQC; + break; + } + + return keycnt; +} + +static void mxc_kp_tq(struct work_struct *work); + +/*! + * This function is called to start the timer for scanning the keypad if there + * is any key press. Currently this interval is set to 10 ms. When there are + * no keys pressed on the keypad we return back, waiting for a keypad key + * press interrupt. + * + * @param data Opaque data passed back by kernel. Not used. + */ +static void mxc_kpp_handle_timer(unsigned long data) +{ + mxc_kp_tq((struct work_struct *)data); +} + +static void mxc_kp_tq(struct work_struct *work) +{ + unsigned short reg_val; + int i; + + if (keypad_lock) { + LLOG_DEBUG1("mxc_kp_tq: returning because keypad is locked\n"); + return; + } + + if (mxc_kpp_scan_matrix() == 0) { + /* + * Stop scanning and wait for interrupt. + * Enable press interrupt and disable release interrupt. + */ + __raw_writew(0x00FF, KPDR); + reg_val = __raw_readw(KPSR); + reg_val |= (KBD_STAT_KPKR | KBD_STAT_KPKD); + reg_val |= KBD_STAT_KRSS | KBD_STAT_KDSC; + __raw_writew(reg_val, KPSR); + reg_val |= KBD_STAT_KDIE; + reg_val &= ~KBD_STAT_KRIE; + __raw_writew(reg_val, KPSR); + + /* + * No more keys pressed... make sure unwanted key codes are + * not given upstairs + */ + for (i = 0; i < kpp_dev.kpp_rows; i++) { + memset(press_scancode[i], -1, + sizeof(press_scancode[0][0]) * kpp_dev.kpp_cols); + memset(release_scancode[i], -1, + sizeof(release_scancode[0][0]) * + kpp_dev.kpp_cols); + + } + return; + } + + /* + * There are still some keys pressed, continue to scan. + * We shall scan again in 10 ms. This has to be tuned according + * to the requirement. + */ + kpp_dev.poll_timer.expires = jiffies + KScanRate; + kpp_dev.poll_timer.function = mxc_kpp_handle_timer; + //add_timer(&kpp_dev.poll_timer); + mod_timer(&kpp_dev.poll_timer, kpp_dev.poll_timer.expires); +} + +/*! + * This function is the keypad Interrupt handler. + * This function checks for keypad status register (KPSR) for key press + * and interrupt. If key press interrupt has occurred, then the key + * press interrupt in the KPSR are disabled. + * It then calls mxc_kpp_scan_matrix to check for any key pressed/released. + * If any key is found to be pressed, then a timer is set to call + * mxc_kpp_scan_matrix function for every 10 ms. + * + * @param irq The Interrupt number + * @param dev_id Driver private data + * + * @result The function returns \b IRQ_RETVAL(1) if interrupt was handled, + * returns \b IRQ_RETVAL(0) if the interrupt was not handled. + * \b IRQ_RETVAL is defined in include/linux/interrupt.h. + */ +static irqreturn_t mxc_kpp_interrupt(int irq, void *dev_id) +{ + unsigned short reg_val; + + /* Delete the polling timer */ + //del_timer(&kpp_dev.poll_timer); + reg_val = __raw_readw(KPSR); + + /* Check if it is key press interrupt */ + if (reg_val & KBD_STAT_KPKD) { + /* + * Disable key press(KDIE status bit) interrupt + */ + reg_val &= ~KBD_STAT_KDIE; + __raw_writew(reg_val, KPSR); +#ifdef CONFIG_PM + } + else if (reg_val & KBD_STAT_KPKR) { + /* + * Disable key release(KRIE status bit) interrupt - only caused + * by _suspend setting the bit IF a key is down while the system + * is being suspended. + */ + reg_val &= ~KBD_STAT_KRIE; + __raw_writew(reg_val, KPSR); +#endif + } + else { + /* spurious interrupt */ + return IRQ_RETVAL(0); + } + /* + * Check if any keys are pressed, if so start polling. + */ + mxc_kpp_handle_timer(0); + return IRQ_HANDLED; +} + +/*! + * This function is called when the keypad driver is opened. + * Since keypad initialization is done in __init, nothing is done in open. + * + * @param dev Pointer to device inode + * + * @result The function always return 0 + */ +static int mxc_kpp_open(struct input_dev *dev) +{ + return 0; +} + +/*! + * This function is called close the keypad device. + * Nothing is done in this function, since every thing is taken care in + * __exit function. + * + * @param dev Pointer to device inode + * + */ +static void mxc_kpp_close(struct input_dev *dev) +{ +} + + +/*! + * This function locks the keypad + */ +static void lock_keypad(void) +{ + LLOG_DEBUG3("Entering lock_keypad\n"); + del_timer_sync(&kpp_dev.poll_timer); + del_timer_sync(&mxckbd_dev->timer); + disable_irq(keypad->irq); + cancel_work_sync(&kpp_dev.tq); + keypad_lock = true; + clk_disable(kpp_clk); + gpio_keypad_inactive(); +} + + +/*! + * This function unlocks the keypad + */ +static void unlock_keypad(void) +{ + LLOG_DEBUG3("Entering unlock_keypad\n"); + del_timer_sync(&kpp_dev.poll_timer); + del_timer_sync(&mxckbd_dev->timer); + gpio_keypad_active(); + clk_enable(kpp_clk); + enable_irq(keypad->irq); + keypad_lock = false; + + /* + * Check keyboard status and process any key changes that + * happened during lock + */ + schedule_work (&kpp_dev.tq); +} + + +#ifdef CONFIG_PM +/*! + * This function puts the Keypad controller in low-power mode/state. + * If Keypad is enabled as a wake source(i.e. it can resume the system + * from suspend mode), the Keypad controller doesn't enter low-power state. + * + * @param pdev the device structure used to give information on Keypad + * to suspend + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int mxc_kpp_suspend(struct platform_device *pdev, pm_message_t state) +{ + unsigned short reg_val; + + /* + * NOTE: in the Lab126 platform architecture, we always go to + * the "locked" state before going to suspend; therefore, all + * keyboard locking actions are in the lock_keypad function, above. + */ + + if (device_may_wakeup(&pdev->dev)) { + reg_val = __raw_readw(KPSR); + if ((reg_val & KBD_STAT_KDIE) == 0) { + /* if no depress interrupt enable the release interrupt */ + reg_val |= KBD_STAT_KRIE; + __raw_writew(reg_val, KPSR); + } + enable_irq_wake(keypad->irq); + } + return 0; +} + +/*! + * This function brings the Keypad controller back from low-power state. + * If Keypad is enabled as a wake source(i.e. it can resume the system + * from suspend mode), the Keypad controller doesn't enter low-power state. + * + * @param pdev the device structure used to give information on Keypad + * to resume + * + * @return The function always returns 0. + */ +static int mxc_kpp_resume(struct platform_device *pdev) +{ + /* + * NOTE: in the Lab126 platform architecture, we always execute + * unlock_keypad after mxc_kpp_resume; therefore, all + * keyboard unlocking actions are in the unlock_keypad function, above. + */ + LLOG_DEBUG3("Entering mxc_kpp_resume\n"); + if (device_may_wakeup(&pdev->dev)) { + /* the irq routine already cleared KRIE if it was set */ + disable_irq_wake(keypad->irq); + } + return 0; +} + +#else +#define mxc_kpp_suspend NULL +#define mxc_kpp_resume NULL +#endif /* CONFIG_PM */ + +static ssize_t +show_alt_timer(struct device *dev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", atomic_read(&alt_sticky_timeout)); +} + +static ssize_t +store_alt_timer(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +{ + int i; + + if (sscanf(buf, "%d", &i) != 1) + return -EINVAL; + + atomic_set(&alt_sticky_timeout, i <= 0 ? 0 : i); + return count; +} + +/*! + * This function returns the current state of the keyboard + */ +int keypad_proc_read( char *page, char **start, off_t off, + int count, int *eof, void *data ) +{ + int len; + + if (off > 0) { + *eof = 1; + return 0; + } + if (keypad_lock) { + len = sprintf(page, "keypad is locked\n"); + } + else { + len = sprintf(page, "keypad is unlocked\n"); + } + return len; +} + +extern char *mxc_get_task_comm(char *buf, struct task_struct *tsk); + +/** Prints out info about the current process + * + * @param str The prefix to tack on to the info + */ +static void printk_process_info(const char *str) +{ + char comm[TASK_COMM_LEN]; + mxc_get_task_comm(comm, current); + printk(KERN_ERR " %s pid:%d, name:'%s'\n", + str, current->pid, comm); +} + +/*! + * This function executes keypad control commands based on the input string. + * unlock = unlock the keypad + * lock = lock the keypad + */ +ssize_t keypad_proc_write( struct file *filp, const char __user *buff, + unsigned long len, void *data ) + +{ + char command[PROC_CMD_LEN]; + int keycode = 0; + + if (len > PROC_CMD_LEN) { + LLOG_ERROR("proc_len", "", "keypad command is too long!\n"); + return -ENOSPC; + } + + if (copy_from_user(command, buff, len)) { + return -EFAULT; + } + + if ( !strncmp(command, "unlock", 6) ) { + // Requested to unlock keypad + if (!keypad_lock) { + // Keypad was already unlocked; do nothing + LLOG_INFO("unlocked1", "status=unlocked", "\n"); + } + else { + // Unlock keypad + unlock_keypad(); + LLOG_INFO("unlocked2", "status=unlocked", "\n"); + } + } + else if ( !strncmp(command, "lock", 4) ) { + // Requested to lock keypad + if (keypad_lock) { + // Keypad was already locked; do nothing + LLOG_INFO("locked1", "status=locked", "\n"); + } + else { + // Lock keypad + lock_keypad(); + LLOG_INFO("locked2", "status=locked", "\n"); + } + } + else if ( !strncmp(command, "sendalt", 7) ) { + // Requested to send an ALT+keycode sequence + if (keypad_lock) { + // Keypad is locked; do nothing + LLOG_WARN("locked3a", "", "The keypad is locked! Unlock before sending keycodes.\n"); + } + else { + // Read keycode and send + sscanf(command, "sendalt %d", &keycode); + LLOG_INFO("send_alt_plus_key", "", "Sending ALT plus keycode %d\n", keycode); + report_event(mxckbd_dev, EV_KEY, KEY_LEFTALT, 1); + report_event(mxckbd_dev, EV_KEY, keycode, 1); + report_event(mxckbd_dev, EV_KEY, keycode, 0); + report_event(mxckbd_dev, EV_KEY, KEY_LEFTALT, 0); + } + } + else if ( !strncmp(command, "sendshift", 9) ) { + // Requested to send an SHIFT+keycode sequence + if (keypad_lock) { + // Keypad is locked; do nothing + LLOG_WARN("locked3b", "", "The keypad is locked! Unlock before sending keycodes.\n"); + } + else { + // Read keycode and send + sscanf(command, "sendshift %d", &keycode); + LLOG_INFO("send_shift_plus_key", "", "Sending SHIFT plus keycode %d\n", keycode); + report_event(mxckbd_dev, EV_KEY, KEY_LEFTSHIFT, 1); + report_event(mxckbd_dev, EV_KEY, keycode, 1); + report_event(mxckbd_dev, EV_KEY, keycode, 0); + report_event(mxckbd_dev, EV_KEY, KEY_LEFTSHIFT, 0); + } + } + else if ( !strncmp(command, "send", 4) ) { + // Requested to send a keycode + if (keypad_lock) { + // Keypad is locked; do nothing + LLOG_WARN("locked3", "", "The keypad is locked! Unlock before sending keycodes.\n"); + } + else { + // Read keycode and send + sscanf(command, "send %d", &keycode); + LLOG_INFO("send_key", "", "Sending keycode %d\n", keycode); + report_event(mxckbd_dev, EV_KEY, keycode, 1); + report_event(mxckbd_dev, EV_KEY, keycode, 0); + } + } + else if ( !strncmp(command, "keycnt", 6) ) { + printk_process_info("rogue process wrote 'keycnt' to /proc/keypad: "); + } + else if ( !strncmp(command, "dokeycnt", 8) ) { + // Requested the key-pressed count for selected keycodes + LLOG_INFO("keycnt_home", "HOME_keycount=%d", "\n", keycode_count[KEY_KPSLASH]); + LLOG_INFO("keycnt_menu", "MENU_keycount=%d", "\n", keycode_count[KEY_MENU]); + LLOG_INFO("keycnt_back", "BACK_keycount=%d", "\n", keycode_count[KEY_HIRAGANA]); + LLOG_INFO("keycnt_next_left", "NEXT_LEFT_keycount=%d", "\n", keycode_count[KEY_PAGEUP]); + LLOG_INFO("keycnt_next_right", "NEXT_RIGHT_keycount=%d", "\n", keycode_count[KEY_YEN]); + LLOG_INFO("keycnt_prev", "PREV_keycount=%d", "\n", keycode_count[KEY_PAGEDOWN]); + LLOG_INFO("keycnt_font", "FONT_keycount=%d", "\n", keycode_count[KEY_KATAKANA]); + LLOG_INFO("keycnt_sym", "SYM_keycount=%d", "\n", keycode_count[KEY_MUHENKAN]); + } + else if ( !strncmp(command, "debug", 5) ) { + // Requested to set debug level + sscanf(command, "debug %d", &debug); + LLOG_INFO("debug", "", "Setting debug level to %d\n", debug); + set_debug_log_mask(debug); + } + else { + LLOG_ERROR("proc_cmd", "", "Unrecognized keypad command\n"); + } + + return len; +} + + +/*! + * This function is called to free the allocated memory for local arrays + */ +static void mxc_kpp_free_allocated(void) +{ + + int i; + + if (press_scancode) { + for (i = 0; i < kpp_dev.kpp_rows; i++) { + if (press_scancode[i]) + kfree(press_scancode[i]); + } + kfree(press_scancode); + } + + if (release_scancode) { + for (i = 0; i < kpp_dev.kpp_rows; i++) { + if (release_scancode[i]) + kfree(release_scancode[i]); + } + kfree(release_scancode); + } + + if (cur_rcmap) + kfree(cur_rcmap); + + if (prev_rcmap) + kfree(prev_rcmap); + + if (mxckbd_dev) + input_free_device(mxckbd_dev); +} + +/*! + * This function is called during the driver binding process. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions. + * + * @return The function returns 0 on successful registration. Otherwise returns + * specific error code. + */ +static int mxc_kpp_probe(struct platform_device *pdev) +{ + int i, irq; + int retval; + unsigned int reg_val; + int junk; + + /* Create proc entry */ + proc_entry = create_proc_entry( KEYPAD_PROC_FILE, 0644, NULL ); + if (proc_entry == NULL) { + LLOG_ERROR("create_proc", "", "Keyboard could not create proc entry\n"); + return -ENOMEM; + } + else { + proc_entry->read_proc = keypad_proc_read; + proc_entry->write_proc = keypad_proc_write; + proc_entry->owner = THIS_MODULE; + } + + keypad = (struct keypad_data *)pdev->dev.platform_data; + + kpp_dev.kpp_cols = keypad->colmax; + kpp_dev.kpp_rows = keypad->rowmax; + keypad_lock = true; + + /* + * Request for IRQ number for keypad port. The Interrupt handler + * function (mxc_kpp_interrupt) is called when ever interrupt occurs on + * keypad port. + */ + irq = platform_get_irq(pdev, 0); + keypad->irq = irq; + retval = request_irq(irq, mxc_kpp_interrupt, 0, MOD_NAME, MOD_NAME); + if (retval) { + LLOG_ERROR("req_irq", "", "request_irq(%d) returned error %d\n", irq, retval); + goto del_proc_entry; + } + + /* Enable keypad clock */ + kpp_clk = clk_get(&pdev->dev, "kpp_clk"); + clk_enable(kpp_clk); + + /* IOMUX configuration for keypad */ + retval = gpio_keypad_active(); + if (retval) { + LLOG_ERROR("set_gpio", "", "gpio_keypad_active returned error %d\n", retval); + goto free_irq; + } + + /* Configure keypad */ + + /* Enable number of rows in keypad (KPCR[7:0]) + * Configure keypad columns as open-drain (KPCR[15:8]) + * + * Configure the rows/cols in KPP + * LSB nibble in KPP is for 8 rows + * MSB nibble in KPP is for 8 cols + */ + reg_val = __raw_readw(KPCR); + reg_val |= (1 << keypad->rowmax) - 1; /* LSB */ + reg_val |= ((1 << keypad->colmax) - 1) << 8; /* MSB */ + __raw_writew(reg_val, KPCR); + + /* Write 0's to KPDR[15:8] */ + reg_val = __raw_readw(KPDR); + reg_val &= 0x00ff; + __raw_writew(reg_val, KPDR); + + /* Configure columns as output, rows as input (KDDR[15:0]) */ + reg_val = __raw_readw(KDDR); + reg_val |= 0xff00; + reg_val &= 0xff00; + __raw_writew(reg_val, KDDR); + + reg_val = __raw_readw(KPSR); + reg_val &= ~(KBD_STAT_KPKR | KBD_STAT_KPKD); + reg_val |= KBD_STAT_KPKD; + reg_val |= KBD_STAT_KRSS | KBD_STAT_KDSC; + __raw_writew(reg_val, KPSR); + reg_val |= KBD_STAT_KDIE; + reg_val &= ~KBD_STAT_KRIE; + __raw_writew(reg_val, KPSR); + + mxckpd_keycodes_size = keypad->rowmax * keypad->colmax; + mxckpd_keycodes = keypad->matrix; + + // This logic may have to get more complicated if/when we have more boards to + // support. But the idea here is that, if it's a Luigi3, then just use + // the first (zeroth) keypad matrix in the array. Otherwise, use the second + // one. + // + mxckpd_keycodes += (mxckpd_keycodes_size * + ((IS_LUIGI() && (3 == GET_BOARD_HW_VERSION())) ? 0 : 1)); + + if ((keypad->matrix == (void *)0) + || (mxckpd_keycodes_size == 0)) { + retval = -ENODEV; + goto free_irq; + } + + mxckbd_dev = input_allocate_device(); + if (!mxckbd_dev) { + LLOG_ERROR("mxckbd_dev", "", "Not enough memory for input device\n"); + retval = -ENOMEM; + goto free_irq; + } + + mxckbd_dev->keycode = &mxckpd_keycodes; + mxckbd_dev->keycodesize = sizeof(unsigned char); + mxckbd_dev->keycodemax = mxckpd_keycodes_size; + + // Parameters related to key-repeat functionality + mxckbd_dev->timer.data = (long) mxckbd_dev; + mxckbd_dev->timer.function = input_repeat_key; + mxckbd_dev->rep[REP_DELAY] = repeat_delay; + mxckbd_dev->rep[REP_PERIOD] = repeat_period; + + mxckbd_dev->name = "mxckpd"; + mxckbd_dev->id.bustype = BUS_HOST; + mxckbd_dev->open = mxc_kpp_open; + mxckbd_dev->close = mxc_kpp_close; + + /* allocate required memory */ + press_scancode = kmalloc(kpp_dev.kpp_rows * sizeof(press_scancode[0]), + GFP_KERNEL); + release_scancode = + kmalloc(kpp_dev.kpp_rows * sizeof(release_scancode[0]), GFP_KERNEL); + + if (!press_scancode || !release_scancode) { + retval = -ENOMEM; + goto kpp_free; + } + + for (i = 0; i < kpp_dev.kpp_rows; i++) { + press_scancode[i] = kmalloc(kpp_dev.kpp_cols + * sizeof(press_scancode[0][0]), + GFP_KERNEL); + release_scancode[i] = + kmalloc(kpp_dev.kpp_cols * sizeof(release_scancode[0][0]), + GFP_KERNEL); + + if (!press_scancode[i] || !release_scancode[i]) { + retval = -ENOMEM; + goto kpp_free; + } + } + + cur_rcmap = + kmalloc(kpp_dev.kpp_rows * sizeof(cur_rcmap[0]), GFP_KERNEL); + prev_rcmap = + kmalloc(kpp_dev.kpp_rows * sizeof(prev_rcmap[0]), GFP_KERNEL); + + if (!cur_rcmap || !prev_rcmap) { + retval = -ENOMEM; + goto kpp_free; + } + + __set_bit(EV_KEY, mxckbd_dev->evbit); + __set_bit(EV_REP, mxckbd_dev->evbit); + + for (i = 0; i < mxckpd_keycodes_size; i++) + __set_bit(mxckpd_keycodes[i], mxckbd_dev->keybit); + + for (i = 0; i < kpp_dev.kpp_rows; i++) { + memset(press_scancode[i], -1, + sizeof(press_scancode[0][0]) * kpp_dev.kpp_cols); + memset(release_scancode[i], -1, + sizeof(release_scancode[0][0]) * kpp_dev.kpp_cols); + } + memset(cur_rcmap, 0, kpp_dev.kpp_rows * sizeof(cur_rcmap[0])); + memset(prev_rcmap, 0, kpp_dev.kpp_rows * sizeof(prev_rcmap[0])); + + // Initialize key press counters + for (i = 0; i < MAX_CODES; i++) { + keycode_count[i] = 0; + } + + keypad_lock = false; + /* Initialize the polling timer and the work item */ + init_timer(&kpp_dev.poll_timer); + + INIT_WORK (&kpp_dev.tq, mxc_kp_tq); + + retval = input_register_device(mxckbd_dev); + if (retval < 0) { + goto kpp_free; + } + + + /* By default, devices should wakeup if they can */ + /* HOWEVER, the keypad is NOT set as "should wakeup" in our platform */ + device_init_wakeup(&pdev->dev, 0); + + junk = device_create_file(&pdev->dev, &dev_attr_alt_timer); + return 0; // Success! + +kpp_free: + mxc_kpp_free_allocated(); + input_free_device(mxckbd_dev); +free_irq: + free_irq(irq, MOD_NAME); + clk_disable(kpp_clk); + clk_put(kpp_clk); +del_proc_entry: + remove_proc_entry(KEYPAD_PROC_FILE, NULL); + + + return retval; +} + +/*! + * Dissociates the driver from the kpp device. + * + * @param pdev the device structure used to give information on which SDHC + * to remove + * + * @return The function always returns 0. + */ +static int mxc_kpp_remove(struct platform_device *pdev) +{ + unsigned short reg_val; + + device_remove_file(&pdev->dev, &dev_attr_alt_timer); + + /* + * Clear the KPKD status flag (write 1 to it) and synchronizer chain. + * Set KDIE control bit, clear KRIE control bit (avoid false release + * events. Disable the keypad GPIO pins. + */ + __raw_writew(0x00, KPCR); + __raw_writew(0x00, KPDR); + __raw_writew(0x00, KDDR); + + reg_val = __raw_readw(KPSR); + reg_val |= KBD_STAT_KPKD; + reg_val &= ~KBD_STAT_KRSS; + reg_val |= KBD_STAT_KDIE; + reg_val &= ~KBD_STAT_KRIE; + __raw_writew(reg_val, KPSR); + + gpio_keypad_inactive(); + clk_disable(kpp_clk); + clk_put(kpp_clk); + + KPress = 0; + + del_timer_sync(&kpp_dev.poll_timer); + del_timer_sync(&mxckbd_dev->timer); + + free_irq(keypad->irq, MOD_NAME); + remove_proc_entry(KEYPAD_PROC_FILE, NULL); + input_unregister_device(mxckbd_dev); + + mxc_kpp_free_allocated(); + + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxc_kpd_driver = { + .driver = { + .name = "mxc_keypad", + .bus = &platform_bus_type, + }, + .suspend = mxc_kpp_suspend, + .resume = mxc_kpp_resume, + .probe = mxc_kpp_probe, + .remove = mxc_kpp_remove +}; + +/*! + * This function is called for module initialization. + * It registers keypad char driver and requests for KPP irq number. This + * function does the initialization of the keypad device. + * + * The following steps are used for keypad configuration,\n + * -# Enable number of rows in the keypad control register (KPCR[7:0}).\n + * -# Write 0's to KPDR[15:8]\n + * -# Configure keypad columns as open-drain (KPCR[15:8])\n + * -# Configure columns as output, rows as input (KDDR[15:0])\n + * -# Clear the KPKD status flag (write 1 to it) and synchronizer chain\n + * -# Set KDIE control bit, clear KRIE control bit\n + * In this function the keypad queue initialization is done. + * The keypad IOMUX configuration are done here.* + + * + * @return 0 on success and a non-zero value on failure. + */ +static int __init mxc_kpp_init(void) +{ + LLOG_INIT(); + set_debug_log_mask(debug); + LLOG_INFO("drv", "", "Keypad driver loaded\n"); + platform_driver_register(&mxc_kpd_driver); + return 0; +} + +/*! + * This function is called whenever the module is removed from the kernel. It + * unregisters the keypad driver from kernel and frees the irq number. + * This function puts the keypad to standby mode. The keypad interrupts are + * disabled. It calls gpio_keypad_inactive function to switch gpio + * configuration into default state. + * + */ +static void __exit mxc_kpp_cleanup(void) +{ + platform_driver_unregister(&mxc_kpd_driver); +} + +module_init(mxc_kpp_init); +module_exit(mxc_kpp_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC Keypad Controller Driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/input/keyboard/mxc_keyb.h linux-2.6.26-lab126/drivers/input/keyboard/mxc_keyb.h --- linux-2.6.26/drivers/input/keyboard/mxc_keyb.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/input/keyboard/mxc_keyb.h 2010-08-10 04:15:44.000000000 -0400 @@ -0,0 +1,220 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup keypad Keypad Driver + */ + +/*! + * @file mxc_keyb.h + * + * @brief MXC keypad header file. + * + * @ingroup keypad + */ +#ifndef __MXC_KEYB_H__ +#define __MXC_KEYB_H__ + +/*! + * Keypad Module Name + */ +#define MOD_NAME "mxckpd" + +/*! + * Keypad irq number + */ +#define KPP_IRQ MXC_INT_KPP + +/*! + * XLATE mode selection + */ +#define KEYPAD_XLATE 0 + +/*! + * RAW mode selection + */ +#define KEYPAD_RAW 1 + +/*! + * Maximum number of keys. + */ +#define MAXROW 8 +#define MAXCOL 8 +#define MXC_MAXKEY (MAXROW * MAXCOL) + +/*! + * This define indicates break scancode for every key release. A constant + * of 128 is added to the key press scancode. + */ +#define MXC_KEYRELEASE 128 + +/* + * _reg_KPP_KPCR _reg_KPP_KPSR _reg_KPP_KDDR _reg_KPP_KPDR + * Keypad Control Register Address + */ +#define KPCR IO_ADDRESS(KPP_BASE_ADDR + 0x00) + +/* + * Keypad Status Register Address + */ +#define KPSR IO_ADDRESS(KPP_BASE_ADDR + 0x02) + +/* + * Keypad Data Direction Address + */ +#define KDDR IO_ADDRESS(KPP_BASE_ADDR + 0x04) + +/* + * Keypad Data Register + */ +#define KPDR IO_ADDRESS(KPP_BASE_ADDR + 0x06) + +/* + * Key Press Interrupt Status bit + */ +#define KBD_STAT_KPKD 0x01 + +/* + * Key Release Interrupt Status bit + */ +#define KBD_STAT_KPKR 0x02 + +/* + * Key Depress Synchronizer Chain Status bit + */ +#define KBD_STAT_KDSC 0x04 + +/* + * Key Release Synchronizer Status bit + */ +#define KBD_STAT_KRSS 0x08 + +/* + * Key Depress Interrupt Enable Status bit + */ +#define KBD_STAT_KDIE 0x100 + +/* + * Key Release Interrupt Enable + */ +#define KBD_STAT_KRIE 0x200 + +/* + * Keypad Clock Enable + */ +#define KBD_STAT_KPPEN 0x400 + +/*! + * Buffer size of keypad queue. Should be a power of 2. + */ +#define KPP_BUF_SIZE 128 + +/*! + * Test whether bit is set for integer c + */ +#define TEST_BIT(c, n) ((c) & (0x1 << (n))) + +/*! + * Set nth bit in the integer c + */ +#define BITSET(c, n) ((c) | (1 << (n))) + +/*! + * Reset nth bit in the integer c + */ +#define BITRESET(c, n) ((c) & ~(1 << (n))) + +/*! + * This enum represents the keypad state machine to maintain debounce logic + * for key press/release. + */ +enum KeyState { + + /*! + * Key press state. + */ + KStateUp, + + /*! + * Key press debounce state. + */ + KStateFirstDown, + + /*! + * Key release state. + */ + KStateDown, + + /*! + * Key release debounce state. + */ + KStateFirstUp +}; + +/*! + * This enum represents the ALT state machine to process the special + * ALT+key mappings. + */ +enum AltState { + + /*! + * ALT is up and nothing is pending + */ + AltStateStart, + + /*! + * ALT has just been pushed down + */ + AltStateFirstDown, + + /*! + * ALT is being held down + */ + AltStateDown, + + /*! + * ALT is up after being down with no other keys pressed in between + */ + AltStateSticky +}; + +/*! + * Keypad Private Data Structure + */ +typedef struct keypad_priv { + + /*! + * Keypad state machine. + */ + enum KeyState iKeyState; + + /*! + * Number of rows configured in the keypad matrix + */ + unsigned long kpp_rows; + + /*! + * Number of Columns configured in the keypad matrix + */ + unsigned long kpp_cols; + + /*! + * Timer used for Keypad polling. + */ + struct timer_list poll_timer; + + struct work_struct tq; + +} keypad_priv; + +#endif /* __MXC_KEYB_H__ */ diff -urN linux-2.6.26/drivers/input/mouse/psmouse-base.c linux-2.6.26-lab126/drivers/input/mouse/psmouse-base.c --- linux-2.6.26/drivers/input/mouse/psmouse-base.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/input/mouse/psmouse-base.c 2010-08-10 04:15:42.000000000 -0400 @@ -1597,10 +1597,25 @@ return sprintf(buffer, "%s\n", psmouse_protocol_by_type(type)->name); } +static int __read_mostly nopsmouse; + +static int __init nopsmouse_setup(char *str) +{ + nopsmouse = 1; + printk(KERN_INFO "debug: not setting up psmouse.\n"); + + return 1; +} + +__setup("nopsmouse", nopsmouse_setup); + static int __init psmouse_init(void) { int err; + if (nopsmouse) + return 0; + kpsmoused_wq = create_singlethread_workqueue("kpsmoused"); if (!kpsmoused_wq) { printk(KERN_ERR "psmouse: failed to create kpsmoused workqueue\n"); diff -urN linux-2.6.26/drivers/input/touchscreen/Kconfig linux-2.6.26-lab126/drivers/input/touchscreen/Kconfig --- linux-2.6.26/drivers/input/touchscreen/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/input/touchscreen/Kconfig 2010-08-10 04:15:42.000000000 -0400 @@ -29,6 +29,16 @@ To compile this driver as a module, choose M here: the module will be called ads7846. +config TOUCHSCREEN_STANTUM + tristate "Support for Stantum touch" + depends on USB + help + +config TOUCHSCREEN_MC13892 + tristate "Support for Atlas Lite MC13892 4-wire Resistive Touch" + depends on SPI && MXC_PMIC_MC13892 + help + config TOUCHSCREEN_BITSY tristate "Compaq iPAQ H3600 (Bitsy) touchscreen" depends on SA1100_BITSY @@ -134,6 +144,30 @@ To compile this driver as a module, choose M here: the module will be called jornada720_ts. +config TOUCHSCREEN_MXC + tristate "MXC touchscreen input driver" + depends on MXC_MC13783_ADC || MXC_MC13892_ADC + help + Say Y here if you have an MXC based board with touchscreen + attached to it. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called mxc_ts. + +config TOUCHSCREEN_IMX_ADC + tristate "Freescale i.MX ADC touchscreen input driver" + depends on IMX_ADC + help + Say Y here if you have a Freescale i.MX based board with a + touchscreen interfaced to the processor's integrated ADC. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called imx_adc_ts. + config TOUCHSCREEN_PENMOUNT tristate "Penmount serial touchscreen" select SERIO @@ -316,4 +350,12 @@ bool "GoTop Super_Q2/GogoPen/PenPower tablet device support" if EMBEDDED depends on TOUCHSCREEN_USB_COMPOSITE +config TOUCHSCREEN_TSC2007 + tristate "TI Touch Screen Controller Chip TSC2007" + depends on ARCH_MX51 || ARCH_MX37 || MACH_MX35_3DS + help + If you say yes here you get support for TSC2007 touch screen controller chip. + + This driver can also be built as a module. If so, the module + will be called tsc2007. endif diff -urN linux-2.6.26/drivers/input/touchscreen/Makefile linux-2.6.26-lab126/drivers/input/touchscreen/Makefile --- linux-2.6.26/drivers/input/touchscreen/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/input/touchscreen/Makefile 2010-08-10 04:15:42.000000000 -0400 @@ -16,13 +16,18 @@ obj-$(CONFIG_TOUCHSCREEN_MK712) += mk712.o obj-$(CONFIG_TOUCHSCREEN_HP600) += hp680_ts_input.o obj-$(CONFIG_TOUCHSCREEN_HP7XX) += jornada720_ts.o +obj-$(CONFIG_TOUCHSCREEN_MXC) += mxc_ts.o +obj-$(CONFIG_TOUCHSCREEN_IMX_ADC) += imx_adc_ts.o obj-$(CONFIG_TOUCHSCREEN_USB_COMPOSITE) += usbtouchscreen.o obj-$(CONFIG_TOUCHSCREEN_PENMOUNT) += penmount.o obj-$(CONFIG_TOUCHSCREEN_TOUCHRIGHT) += touchright.o obj-$(CONFIG_TOUCHSCREEN_TOUCHWIN) += touchwin.o obj-$(CONFIG_TOUCHSCREEN_UCB1400) += ucb1400_ts.o +obj-$(CONFIG_TOUCHSCREEN_TSC2007) += tsc2007.o obj-$(CONFIG_TOUCHSCREEN_WM97XX) += wm97xx-ts.o wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9705) += wm9705.o wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9712) += wm9712.o wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9713) += wm9713.o obj-$(CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE) += mainstone-wm97xx.o +obj-$(CONFIG_TOUCHSCREEN_STANTUM) += smk.o +obj-$(CONFIG_TOUCHSCREEN_MC13892) += mc13892_ts.o diff -urN linux-2.6.26/drivers/input/touchscreen/imx_adc_ts.c linux-2.6.26-lab126/drivers/input/touchscreen/imx_adc_ts.c --- linux-2.6.26/drivers/input/touchscreen/imx_adc_ts.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/input/touchscreen/imx_adc_ts.c 2010-08-10 04:15:42.000000000 -0400 @@ -0,0 +1,114 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file imx_adc_ts.c + * + * @brief Driver for the Freescale Semiconductor i.MX ADC touchscreen. + * + * This touchscreen driver is designed as a standard input driver. It is a + * wrapper around the low level ADC driver. Much of the hardware configuration + * and touchscreen functionality is implemented in the low level ADC driver. + * During initialization, this driver creates a kernel thread. This thread + * then calls the ADC driver to obtain touchscreen values continously. These + * values are then passed to the input susbsystem. + * + * @ingroup touchscreen + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IMX_ADC_TS_NAME "imx_adc_ts" + +static struct input_dev *imx_inputdev; +static u32 input_ts_installed; + +static int ts_thread(void *arg) +{ + struct t_touch_screen ts_sample; + int wait = 0; + daemonize("imx_adc_ts"); + while (input_ts_installed) { + try_to_freeze(); + + memset(&ts_sample, 0, sizeof(ts_sample)); + if (0 != imx_adc_get_touch_sample(&ts_sample, !wait)) + continue; + + input_report_abs(imx_inputdev, ABS_X, ts_sample.x_position); + input_report_abs(imx_inputdev, ABS_Y, ts_sample.y_position); + input_report_abs(imx_inputdev, ABS_PRESSURE, + ts_sample.contact_resistance); + input_sync(imx_inputdev); + wait = ts_sample.contact_resistance; + msleep(10); + } + + return 0; +} + +static int __init imx_adc_ts_init(void) +{ + int retval; + + if (!is_imx_adc_ready()) + return -ENODEV; + + imx_inputdev = input_allocate_device(); + if (!imx_inputdev) { + pr_err("imx_ts_init: not enough memory for input device\n"); + return -ENOMEM; + } + + imx_inputdev->name = IMX_ADC_TS_NAME; + imx_inputdev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); + imx_inputdev->keybit[BIT_WORD(BTN_TOUCH)] |= BIT_MASK(BTN_TOUCH); + imx_inputdev->absbit[0] = + BIT_MASK(ABS_X) | BIT_MASK(ABS_Y) | BIT_MASK(ABS_PRESSURE); + retval = input_register_device(imx_inputdev); + if (retval < 0) { + input_free_device(imx_inputdev); + return retval; + } + + input_ts_installed = 1; + kthread_run(ts_thread, NULL, "ts_thread"); + pr_info("i.MX ADC input touchscreen loaded.\n"); + return 0; +} + +static void __exit imx_adc_ts_exit(void) +{ + input_ts_installed = 0; + input_unregister_device(imx_inputdev); + + if (imx_inputdev) { + input_free_device(imx_inputdev); + imx_inputdev = NULL; + } +} + +late_initcall(imx_adc_ts_init); +module_exit(imx_adc_ts_exit); + +MODULE_DESCRIPTION("i.MX ADC input touchscreen driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/input/touchscreen/mc13892_ts.c linux-2.6.26-lab126/drivers/input/touchscreen/mc13892_ts.c --- linux-2.6.26/drivers/input/touchscreen/mc13892_ts.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/input/touchscreen/mc13892_ts.c 2010-08-10 04:15:42.000000000 -0400 @@ -0,0 +1,119 @@ +/* + * Copyright 2009 Amazon.com, Inc. All Rights Reserved. + * Manish Lachwani (lachwani@lab126.com) + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file m13892_ts.c + * + * @brief Driver for the Freescale Semiconductor MXC touchscreen. + * + * The touchscreen driver is designed as a standard input driver which is a + * wrapper over low level PMIC driver. Most of the hardware configuration and + * touchscreen functionality is implemented in the low level PMIC driver. During + * initialization, this driver creates a kernel thread. This thread then calls + * PMIC driver to obtain touchscreen values continously. These values are then + * passed to the input susbsystem. + * + * @ingroup touchscreen + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MXC_TS_NAME "mc13892_ts" + +static struct input_dev *mxc_inputdev = NULL; +static u32 input_ts_installed; + +static int ts_thread(void *arg) +{ + t_touch_screen ts_sample; + s32 wait = 0; + + daemonize("mxc_ts"); + while (input_ts_installed) { + try_to_freeze(); + memset(&ts_sample, 0, sizeof(t_touch_screen)); + if (0 != pmic_adc_get_touch_sample(&ts_sample, !wait)) + continue; + if (!(ts_sample.contact_resistance || wait)) + continue; + + input_report_abs(mxc_inputdev, ABS_X, ts_sample.x_position); + input_report_abs(mxc_inputdev, ABS_Y, ts_sample.y_position); + input_report_abs(mxc_inputdev, ABS_PRESSURE, + ts_sample.contact_resistance); + input_sync(mxc_inputdev); + + wait = ts_sample.contact_resistance; + msleep(20); + } + + return 0; +} + +static int __init mc13892_ts_init(void) +{ + int retval; + + if (!is_pmic_adc_ready()) + return -ENODEV; + + mxc_inputdev = input_allocate_device(); + if (!mxc_inputdev) { + printk(KERN_ERR + "mxc_ts_init: not enough memory for input device\n"); + return -ENOMEM; + } + + mxc_inputdev->name = MXC_TS_NAME; + mxc_inputdev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); + mxc_inputdev->keybit[BIT_WORD(BTN_TOUCH)] |= BIT_MASK(BTN_TOUCH); + mxc_inputdev->absbit[0] = + BIT_MASK(ABS_X) | BIT_MASK(ABS_Y) | BIT_MASK(ABS_PRESSURE); + retval = input_register_device(mxc_inputdev); + if (retval < 0) { + input_free_device(mxc_inputdev); + return retval; + } + + input_ts_installed = 1; + kernel_thread(ts_thread, NULL, CLONE_VM | CLONE_FS); + printk("mxc input touchscreen loaded\n"); + return 0; +} + +static void __exit mc13892_ts_exit(void) +{ + input_ts_installed = 0; + input_unregister_device(mxc_inputdev); + + if (mxc_inputdev) { + input_free_device(mxc_inputdev); + mxc_inputdev = NULL; + } +} + +late_initcall(mc13892_ts_init); +module_exit(mc13892_ts_exit); + +MODULE_DESCRIPTION("Atlas MC13892 touchscreen driver"); +MODULE_AUTHOR("Manish Lachwani"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/input/touchscreen/mxc_ts.c linux-2.6.26-lab126/drivers/input/touchscreen/mxc_ts.c --- linux-2.6.26/drivers/input/touchscreen/mxc_ts.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/input/touchscreen/mxc_ts.c 2010-08-10 04:15:42.000000000 -0400 @@ -0,0 +1,118 @@ +/* + * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_ts.c + * + * @brief Driver for the Freescale Semiconductor MXC touchscreen. + * + * The touchscreen driver is designed as a standard input driver which is a + * wrapper over low level PMIC driver. Most of the hardware configuration and + * touchscreen functionality is implemented in the low level PMIC driver. During + * initialization, this driver creates a kernel thread. This thread then calls + * PMIC driver to obtain touchscreen values continously. These values are then + * passed to the input susbsystem. + * + * @ingroup touchscreen + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MXC_TS_NAME "mxc_ts" + +static struct input_dev *mxc_inputdev = NULL; +static u32 input_ts_installed; + +static int ts_thread(void *arg) +{ + t_touch_screen ts_sample; + s32 wait = 0; + + daemonize("mxc_ts"); + while (input_ts_installed) { + try_to_freeze(); + memset(&ts_sample, 0, sizeof(t_touch_screen)); + if (0 != pmic_adc_get_touch_sample(&ts_sample, !wait)) + continue; + if (!(ts_sample.contact_resistance || wait)) + continue; + + input_report_abs(mxc_inputdev, ABS_X, ts_sample.x_position); + input_report_abs(mxc_inputdev, ABS_Y, ts_sample.y_position); + input_report_abs(mxc_inputdev, ABS_PRESSURE, + ts_sample.contact_resistance); + input_sync(mxc_inputdev); + + wait = ts_sample.contact_resistance; + msleep(20); + } + + return 0; +} + +static int __init mxc_ts_init(void) +{ + int retval; + + if (!is_pmic_adc_ready()) + return -ENODEV; + + mxc_inputdev = input_allocate_device(); + if (!mxc_inputdev) { + printk(KERN_ERR + "mxc_ts_init: not enough memory for input device\n"); + return -ENOMEM; + } + + mxc_inputdev->name = MXC_TS_NAME; + mxc_inputdev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); + mxc_inputdev->keybit[BIT_WORD(BTN_TOUCH)] |= BIT_MASK(BTN_TOUCH); + mxc_inputdev->absbit[0] = + BIT_MASK(ABS_X) | BIT_MASK(ABS_Y) | BIT_MASK(ABS_PRESSURE); + retval = input_register_device(mxc_inputdev); + if (retval < 0) { + input_free_device(mxc_inputdev); + return retval; + } + + input_ts_installed = 1; + kernel_thread(ts_thread, NULL, CLONE_VM | CLONE_FS); + printk("mxc input touchscreen loaded\n"); + return 0; +} + +static void __exit mxc_ts_exit(void) +{ + input_ts_installed = 0; + input_unregister_device(mxc_inputdev); + + if (mxc_inputdev) { + input_free_device(mxc_inputdev); + mxc_inputdev = NULL; + } +} + +late_initcall(mxc_ts_init); +module_exit(mxc_ts_exit); + +MODULE_DESCRIPTION("MXC input touchscreen driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/input/touchscreen/smk.c linux-2.6.26-lab126/drivers/input/touchscreen/smk.c --- linux-2.6.26/drivers/input/touchscreen/smk.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/input/touchscreen/smk.c 2010-08-10 04:15:42.000000000 -0400 @@ -0,0 +1,436 @@ +/* + * Linux kernel driver for the Stantum Multitouch Kit 15.4 + * + * The copyright holders for the contents of this file are: + * Ecole Nationale de l'Aviation Civile, France (2008-2009) + * + * You can use this file, redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * Contributors: + * Sebastien Hamdani + * Stephane Chatty + * + */ +#include +#include +#include +#include +#include + +#define DRIVER_VERSION "v1.0" +#define DRIVER_AUTHOR "Sebastien Hamdani , Stephane Chatty " +#define DRIVER_DESC "Stantum MultiTouch Kit 15.4" +#define VENDOR_ID 0x1f87 +#define PRODUCT_ID 0x0002 + +struct point { + __u16 x; + __u16 y; + __u16 id; + __u8 status; + __u8 padding; +}; + +struct header { + __u8 ctrl1; + __u8 nbpoints; + __u8 len; + __u8 ctrl2; +}; + +struct smk { + char phys[64]; + struct usb_device *usbdev; + struct input_dev *tdev; + struct input_dev *mdev; + struct usb_interface *interface; + __u8 bulk_in; + __u8 bulk_out; + struct urb *rq_urb; + struct header header; + unsigned char buf[1024]; + unsigned char* read_head; +}; + +static void smk_send_rq(struct smk *smk); + +char *data; +int mouse_emulation = 1; +module_param(mouse_emulation, int, 0644); + + +/* the function called once we have a well formed set of contact points */ +static void report_pos(struct smk *smk) +{ + struct point *p = (struct point *) &smk->buf; + struct point *oldest_p = p + smk->header.nbpoints-1; + + data = smk->buf; + data[1023] = smk->header.nbpoints; + + /* emit all raw positions (multitouch output)*/ + while (p <= oldest_p) { + input_report_abs(smk->mdev, ABS_MT_TRACKING_ID, p->id); + input_report_abs(smk->mdev, ABS_MT_POSITION_X, p->x); + input_report_abs(smk->mdev, ABS_MT_POSITION_Y, p->y); + input_mt_sync(smk->mdev); + p++; + } + input_sync(smk->mdev); + + if (smk->header.nbpoints > 1 ) + return; + + /* emit oldest contact point as single touch */ + if (oldest_p->status) { + + if(mouse_emulation == 1) + input_report_key(smk->tdev, BTN_LEFT, 1); + else if(mouse_emulation > 1) + input_report_key(smk->tdev, BTN_TOUCH, 1); + else + return; + + input_report_abs(smk->tdev, ABS_X, oldest_p->x); + input_report_abs(smk->tdev, ABS_Y, oldest_p->y); + input_sync(smk->tdev); + + } else { + + if(mouse_emulation == 1) + input_report_key(smk->tdev, BTN_LEFT, 0); + else if(mouse_emulation >1) + input_report_key(smk->tdev, BTN_TOUCH, 0); + + input_sync(smk->tdev); + } +} + + +/* send an init to the hardware */ +static int smk_send_init(struct smk *smk) +{ + struct usb_device *udev = smk->usbdev; + unsigned char vers_msg[4] = {1,0,4,0}; + unsigned char init_msg[4] = {2,0,4,0}; + unsigned int len; + + usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 9, 0, 1, 0, NULL, 0, HZ*10); + usb_bulk_msg(udev, usb_sndbulkpipe(udev, smk->bulk_out), + vers_msg, 4, &len, HZ*10); + usb_bulk_msg(udev, usb_rcvbulkpipe(udev, smk->bulk_in), + &smk->buf, 4, &len, HZ*10); + if(smk->buf[1] != 2) + err("Warning ! Firmware version is v%d, this driver is made for v2", smk->buf[1]); + + usb_bulk_msg(udev, usb_sndbulkpipe(udev, smk->bulk_out), + init_msg, 4, &len, HZ*10); + usb_bulk_msg(udev, usb_rcvbulkpipe(udev, smk->bulk_in), + &smk->buf, 18, &len, HZ*10); + if (len != 18 || smk->buf[0] != 2) { + err("init failed"); + return 0; + } + return 1; +} + + +/* Part of the payload is available, read it and decide what to do */ +static void smk_payload_ready(struct urb *urb) +{ + struct smk *smk = (struct smk*) urb->context; + struct usb_device *udev = smk->usbdev; + struct header* h = &smk->header; + + smk->read_head += urb->actual_length; + h->len -= urb->actual_length; + if (h->len > 0) { + usb_fill_bulk_urb(smk->rq_urb, udev, + usb_rcvbulkpipe(udev, smk->bulk_in), + smk->read_head, h->len, + smk_payload_ready, smk); + if (usb_submit_urb(smk->rq_urb, GFP_ATOMIC) < 0) + err("re-asking payload failed"); + return; + } + report_pos(smk); + + /* start over */ + smk_send_rq(smk); +} + + +/* A header is available, read it then decide what to do */ +static void smk_header_ready(struct urb *urb) +{ + struct smk *smk = (struct smk*) urb->context; + struct usb_device *udev = smk->usbdev; + struct header* h = &smk->header; + + if (urb->status) { + err("asking header failed with status %d", urb->status); + return; + } + if (h->ctrl1 != 3 || h->ctrl2 != 0 || h->len != h->nbpoints*8 + 4) { + goto next; + } + + h->len -= 4; + if (h->nbpoints > 0) { + smk->read_head = smk->buf; + usb_fill_bulk_urb(smk->rq_urb, udev, + usb_rcvbulkpipe(udev, smk->bulk_in), + &smk->buf, h->len, + smk_payload_ready, smk); + if (usb_submit_urb(smk->rq_urb, GFP_ATOMIC) < 0) + err("asking payload failed"); + return; + } else + report_pos(smk); +next: + smk_send_rq (smk); +} + + +/* A request was properly sent, time to read the header of the response */ +static void smk_rq_sent(struct urb *urb) +{ + struct smk *smk = (struct smk*) urb->context; + struct usb_device *udev = smk->usbdev; + + usb_fill_bulk_urb(smk->rq_urb, udev, + usb_rcvbulkpipe(udev, smk->bulk_in), + &smk->header, 4, + smk_header_ready, smk); + if (usb_submit_urb(smk->rq_urb, GFP_ATOMIC) < 0) + err("asking response failed"); +} + +/* send a request to the hardware */ +static void smk_send_rq(struct smk *smk) +{ + struct usb_device *udev = smk->usbdev; + unsigned char msg[4] = {3,0,4,0}; + + usb_fill_bulk_urb(smk->rq_urb, udev, + usb_sndbulkpipe(udev, smk->bulk_out), + msg, 4, + smk_rq_sent, smk); + if (usb_submit_urb(smk->rq_urb, GFP_ATOMIC) < 0) + err("sending rq failed"); +} + +static int smk_open(struct input_dev *dev) +{ + struct smk *smk = input_get_drvdata(dev); + + smk_send_rq(smk); + return 0; +} + +static void smk_close(struct input_dev *dev) +{ + struct smk *smk = input_get_drvdata(dev); + + usb_kill_urb(smk->rq_urb); +} + +static void smk_free(struct smk *smk) +{ + usb_put_dev(smk->usbdev); + kfree(smk); +} + +static int open(struct inode *inode, struct file *file) +{ + return 0; +} + +static ssize_t smk_read(struct file *file, char *buf, size_t count, loff_t *ppos) +{ + if(data) + if (copy_to_user(buf, data, count)) + return -EFAULT; + return count; +} + +static const struct file_operations smk_fops = { + .open = open, + .read = smk_read, +}; + +static struct usb_class_driver smk_class = { + .name = "smk%d", + .fops = &smk_fops, +}; + + +static int smk_probe(struct usb_interface *interface, const struct usb_device_id *id) +{ + int retval = -ENOMEM; + int i; + struct usb_host_interface *idesc = interface->cur_altsetting; + struct usb_device *udev = usb_get_dev(interface_to_usbdev(interface)); + struct usb_device_descriptor *udesc = &udev->descriptor; + + /* 1. allocate an internal structure, and two input devices */ + struct smk *smk = kzalloc(sizeof(struct smk), GFP_KERNEL); + struct input_dev *tdev = input_allocate_device(); + struct input_dev *mdev = input_allocate_device(); + if (!smk || !tdev || !mdev) + goto error; + + /* 2. establish cross-references */ + smk->interface = interface; + smk->usbdev = udev; + smk->tdev = tdev; + smk->mdev = mdev; + usb_set_intfdata(interface, smk); + input_set_drvdata(mdev, smk); + input_set_drvdata(tdev, smk); + + /* 3. set up the endpoint information */ + for (i = 0; i < idesc->desc.bNumEndpoints; ++i) { + struct usb_endpoint_descriptor *ep = &idesc->endpoint[i].desc; + + if (!smk->bulk_in && + usb_endpoint_is_bulk_in(ep)) + smk->bulk_in = ep->bEndpointAddress; + + if (!smk->bulk_out && + usb_endpoint_is_bulk_out(ep)) + smk->bulk_out = ep->bEndpointAddress; + } + if (!(smk->bulk_in && smk->bulk_out)) { + err("Could not find both bulk-in and bulk-out endpoints"); + goto error; + } + + + /* 4. prepare the URB periodically used for requesting data */ + smk->rq_urb = usb_alloc_urb (0, GFP_ATOMIC); + if (!smk->rq_urb) { + retval = -ENOMEM; + goto error; + } + + /* 5. set physical path of the device */ + usb_make_path(udev, smk->phys, sizeof(smk->phys)); + strlcat(smk->phys, "/input0", sizeof(smk->phys)); + + /* 6. Register the device */ + retval = usb_register_dev(interface, &smk_class); + if (retval) { + err("Not able to get a minor for this device."); + usb_set_intfdata(interface, NULL); + goto error; + } + + /* 7. initialize the hardware device */ + if (! smk_send_init (smk)) { + retval = -EFAULT; + goto error; + } + + /* 8. initialise the two input devices */ + + /* 8.1 use the same id data */ + mdev->name = tdev->name = "Stantum Multitouch Kit"; + mdev->phys = tdev->phys = smk->phys; + mdev->id.bustype = tdev->id.bustype = BUS_USB; + mdev->id.vendor = tdev->id.vendor = le16_to_cpu(udesc->idVendor); + mdev->id.product = tdev->id.product = le16_to_cpu(udesc->idProduct); + mdev->id.version = tdev->id.version = le16_to_cpu(udesc->bcdDevice); + mdev->dev.parent = tdev->dev.parent = &interface->dev; + + /* 8.2 a touchscreen emulation */ + tdev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); + if(mouse_emulation == 1) + tdev->keybit[BIT_WORD(BTN_LEFT)] = BIT_MASK(BTN_LEFT); + else if(mouse_emulation >1) + tdev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH); + input_set_abs_params(tdev, ABS_X, 0, 65535, 0, 0); + input_set_abs_params(tdev, ABS_Y, 0, 65535, 0, 0); + + /* 8.3 the mutitouch device, designed not to be seen as a mouse */ + mdev->evbit[0] = BIT_MASK(EV_KEY) + | BIT_MASK(EV_ABS) | BIT_MASK(EV_MSC); + mdev->mscbit[BIT_WORD(EV_MSC)] = BIT_MASK(MSC_SERIAL); + mdev->keybit[BIT_WORD(BTN_TOOL_FINGER)] = BIT_MASK(BTN_TOOL_FINGER); + input_set_abs_params(mdev, ABS_MT_POSITION_X, 0, 65535, 0, 0); + input_set_abs_params(mdev, ABS_MT_POSITION_Y, 0, 65535, 0, 0); + input_set_abs_params(mdev, ABS_MT_TRACKING_ID, 0, 65535, 0, 0); + + + /* 8.4 use the same open and close functions */ + tdev->open = smk_open; + tdev->close = smk_close; + + + /* 9. register the input devices with the input subsystem */ + if (input_register_device(tdev) != 0) + goto error; + if (input_register_device(mdev) != 0) + goto error; + + return 0; + +error: + if (smk) + smk_free(smk); + return retval; +} + +static void smk_disconnect(struct usb_interface *intf) +{ + struct smk *smk = usb_get_intfdata(intf); + + usb_set_intfdata(intf, 0); + usb_deregister_dev(intf, &smk_class); + + if (smk) { + usb_kill_urb(smk->rq_urb); + input_unregister_device(smk->mdev); + input_unregister_device(smk->tdev); + smk_free(smk); + } +} + +static struct usb_device_id smk_id_table [] = { + { USB_DEVICE( VENDOR_ID, PRODUCT_ID) }, + { } +}; + +static struct usb_driver smk_driver = { + .name = "Stantum Multitouch Kit", + .id_table = smk_id_table, + .probe = smk_probe, + .disconnect = smk_disconnect, + .no_dynamic_id = 1, +}; + + +MODULE_DEVICE_TABLE (usb, smk_id_table); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_PARM_DESC(mouse_emulation, "<=0 to disable, 1 to send BTN_LEFT events, >1 to send BTN_TOUCH events (not always supported by the X-server)"); + +static int __init smk_module_init (void) +{ + int retval = usb_register(&smk_driver); + /*if (retval == 0) + info(DRIVER_VERSION ":" DRIVER_DESC);*/ + return retval; +} + +static void __exit smk_module_exit (void) +{ + usb_deregister(&smk_driver); +} + +module_init(smk_module_init); +module_exit(smk_module_exit); diff -urN linux-2.6.26/drivers/input/touchscreen/tsc2007.c linux-2.6.26-lab126/drivers/input/touchscreen/tsc2007.c --- linux-2.6.26/drivers/input/touchscreen/tsc2007.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/input/touchscreen/tsc2007.c 2010-08-10 04:15:42.000000000 -0400 @@ -0,0 +1,443 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file tsc2007.c + * + * @brief Driver for TI's tsc2007 I2C Touch Screen Controller. + * + * This driver is based on the driver written by Bill Gatliff + * Copyright (C) 2005 Bill Gatliff + * Changes for 2.6.20 kernel by Nicholas Chen + * + * @ingroup touchscreen + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "tsc2007" + +enum tsc2007_pd { + PD_POWERDOWN = 0, /* penirq */ + PD_IREFOFF_ADCON = 1, /* no penirq */ + PD_IREFON_ADCOFF = 2, /* penirq */ + PD_IREFON_ADCON = 3, /* no penirq */ + PD_PENIRQ_ARM = PD_IREFON_ADCOFF, + PD_PENIRQ_DISARM = PD_IREFON_ADCON, +}; + +enum tsc2007_m { + M_12BIT = 0, + M_8BIT = 1 +}; + +enum tsc2007_cmd { + MEAS_TEMP0 = 0, + MEAS_IN1 = 2, + MEAS_XPOS = 12, + MEAS_YPOS = 13, + MEAS_Z1POS = 14, + MEAS_Z2POS = 15 +}; + +#define tsc2007_CMD(cn, pdn, m) (((cn) << 4) | ((pdn) << 2) | ((m) << 1)) + +#define ADC_MAX ((1 << 12) - 1) + +struct tsc2007_data { + struct i2c_client *client; + struct input_dev *idev; + struct timer_list penirq_timer; + struct task_struct *tstask; + u32 ts_thread_cnt; + struct completion penirq_completion; + struct completion penup_completion; + enum tsc2007_m m; + int penirq; + int penup_threshold; + struct regulator *vdd_reg; + int opened; +}; + +static int tsc2007_read(struct tsc2007_data *data, + enum tsc2007_cmd cmd, enum tsc2007_pd pd, int *val) +{ + unsigned char c; + unsigned char d[2]; + int ret; + + c = tsc2007_CMD(cmd, pd, data->m); + + ret = i2c_master_send(data->client, &c, 1); + + if (ret < 0) + goto err; + + udelay(20); + ret = i2c_master_recv(data->client, d, data->m == M_12BIT ? 2 : 1); + if (ret < 0) + goto err; + + if (val) { + *val = d[0]; + *val <<= 4; + if (data->m == M_12BIT) + *val += (d[1] >> 4); + } + + return 0; + err: + return -ENODEV; +} + +static inline int tsc2007_read_xpos(struct tsc2007_data *d, enum + tsc2007_pd pd, int *x) +{ + return tsc2007_read(d, MEAS_XPOS, pd, x); +} + +static inline int tsc2007_read_ypos(struct tsc2007_data *d, enum + tsc2007_pd pd, int *y) +{ + return tsc2007_read(d, MEAS_YPOS, pd, y); +} + +static inline int tsc2007_read_pressure(struct tsc2007_data *d, enum + tsc2007_pd pd, int *p) +{ + return tsc2007_read(d, MEAS_Z1POS, pd, p); +} + +static inline int tsc2007_powerdown(struct tsc2007_data *d) +{ + /* we don't have a distinct powerdown command, + so do a benign read with the PD bits cleared */ + return tsc2007_read(d, MEAS_IN1, PD_POWERDOWN, 0); +} + +#define PENUP_TIMEOUT 10 + +static irqreturn_t tsc2007_penirq(int irq, void *v) +{ + struct tsc2007_data *d = v; + + disable_irq(d->penirq); + complete(&d->penirq_completion); + return IRQ_HANDLED; +} + +static void tsc2007_pen_up(unsigned long v) +{ + struct tsc2007_data *d = (struct tsc2007_data *)v; + + complete(&d->penup_completion); + return; +} + +static inline void tsc2007_restart_pen_up_timer(struct tsc2007_data *d) +{ + mod_timer(&d->penirq_timer, jiffies + (PENUP_TIMEOUT * HZ) / 1000); +} + +static int tsc2007ts_thread(void *v) +{ + struct tsc2007_data *d = v; + + if (d->ts_thread_cnt) + return -EINVAL; + d->ts_thread_cnt = 1; + + while (1) { + unsigned int x = 0, y = 0, p = 0; + + if (kthread_should_stop()) + break; + /* Wait for an Pen down interrupt */ + if (wait_for_completion_interruptible_timeout + (&d->penirq_completion, HZ) <= 0) + continue; + + tsc2007_read_xpos(d, PD_PENIRQ_DISARM, &x); + tsc2007_read_ypos(d, PD_PENIRQ_DISARM, &y); + tsc2007_read_pressure(d, PD_PENIRQ_DISARM, &p); + input_report_abs(d->idev, ABS_X, 4096 - x); + input_report_abs(d->idev, ABS_Y, 4096 - y); + input_report_abs(d->idev, ABS_PRESSURE, p); + input_sync(d->idev); + + while (p > d->penup_threshold) { + tsc2007_restart_pen_up_timer(d); + wait_for_completion_interruptible(&d->penup_completion); + /* Pen Down */ + tsc2007_read_xpos(d, PD_PENIRQ_DISARM, &x); + tsc2007_read_ypos(d, PD_PENIRQ_DISARM, &y); + tsc2007_read_pressure(d, PD_PENIRQ_DISARM, &p); + if (p <= d->penup_threshold) + break; + + input_report_abs(d->idev, ABS_X, 4096 - x); + input_report_abs(d->idev, ABS_Y, 4096 - y); + input_report_abs(d->idev, ABS_PRESSURE, p); + input_sync(d->idev); + }; + + /* Pen Up */ + input_report_abs(d->idev, ABS_X, 4096 - x); + input_report_abs(d->idev, ABS_Y, 4096 - y); + input_report_abs(d->idev, ABS_PRESSURE, 0); + input_sync(d->idev); + + tsc2007_read(d, MEAS_TEMP0, PD_PENIRQ_ARM, 0); + enable_irq(d->penirq); + + } + + d->ts_thread_cnt = 0; + return 0; +} + +/*! + * This function puts the touch screen controller in low-power mode/state. + * + * @param pdev the device structure used to give information on touch screen + * to suspend + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int tsc2007_suspend(struct i2c_client *client, pm_message_t state) +{ + struct tsc2007_data *d = i2c_get_clientdata(client); + + if (!IS_ERR(d->tstask) && d->opened) + kthread_stop(d->tstask); + + return 0; +} + +/*! + * This function brings the touch screen controller back from low-power state. + * + * @param pdev the device structure used to give information on touch screen + * to resume + * + * @return The function always returns 0. + */ +static int tsc2007_resume(struct i2c_client *client) +{ + struct tsc2007_data *d = i2c_get_clientdata(client); + + if (d->opened) + d->tstask = kthread_run(tsc2007ts_thread, d, DRIVER_NAME "tsd"); + + return 0; +} + +static int tsc2007_idev_open(struct input_dev *idev) +{ + struct tsc2007_data *d = input_get_drvdata(idev); + int ret = 0; + + d->penirq_timer.data = (unsigned long)d; + d->penirq_timer.function = tsc2007_pen_up; + + init_completion(&d->penup_completion); + + d->tstask = kthread_run(tsc2007ts_thread, d, DRIVER_NAME "tsd"); + if (IS_ERR(d->tstask)) + ret = PTR_ERR(d->tstask); + else + d->opened++; + + return ret; +} + +static void tsc2007_idev_close(struct input_dev *idev) +{ + struct tsc2007_data *d = input_get_drvdata(idev); + if (!IS_ERR(d->tstask)) + kthread_stop(d->tstask); + + del_timer_sync(&d->penirq_timer); + + if (d->opened > 0) + d->opened--; +} + +static int tsc2007_driver_register(struct tsc2007_data *data) +{ + struct input_dev *idev; + int ret = 0; + + init_timer(&data->penirq_timer); + data->penirq_timer.data = (unsigned long)data; + data->penirq_timer.function = tsc2007_pen_up; + + init_completion(&data->penirq_completion); + + if (data->penirq) { + ret = + request_irq(data->penirq, tsc2007_penirq, IRQT_LOW, + DRIVER_NAME, data); + if (!ret) { + printk(KERN_INFO "%s: Registering Touchscreen device\n", + __func__); + set_irq_wake(data->penirq, 1); + } else { + printk(KERN_ERR "%s: Cannot grab irq %d\n", + __func__, data->penirq); + } + } + idev = input_allocate_device(); + data->idev = idev; + input_set_drvdata(idev, data); + idev->name = DRIVER_NAME; + idev->evbit[0] = BIT(EV_ABS); + idev->open = tsc2007_idev_open; + idev->close = tsc2007_idev_close; + idev->absbit[0] = BIT(ABS_X) | BIT(ABS_Y) | BIT(ABS_PRESSURE); + input_set_abs_params(idev, ABS_X, 0, ADC_MAX, 0, 0); + input_set_abs_params(idev, ABS_Y, 0, ADC_MAX, 0, 0); + input_set_abs_params(idev, ABS_PRESSURE, 0, 0, 0, 0); + + if (!ret) + ret = input_register_device(idev); + + return ret; +} + +static int tsc2007_i2c_remove(struct i2c_client *client) +{ + int err; + struct tsc2007_data *d = i2c_get_clientdata(client); + struct mxc_tsc_platform_data *tsc_data; + + free_irq(d->penirq, d); + input_unregister_device(d->idev); + + err = i2c_detach_client(client); + if (err) { + dev_err(&client->dev, "Client deregistration failed, " + "client not detached.\n"); + return err; + } + + tsc_data = (struct mxc_tsc_platform_data *)(client->dev).platform_data; + if (tsc_data && tsc_data->inactive) + tsc_data->inactive(); + + if (d->vdd_reg) { + regulator_disable(d->vdd_reg); + regulator_put(d->vdd_reg, &client->dev); + d->vdd_reg = NULL; + } + return 0; +} + +static int tsc2007_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + struct tsc2007_data *data; + struct mxc_tsc_platform_data *tsc_data; + int err = 0; + + data = kzalloc(sizeof(struct tsc2007_data), GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + + i2c_set_clientdata(client, data); + data->client = client; + data->penirq = client->irq; + + tsc_data = (struct mxc_tsc_platform_data *)(client->dev).platform_data; + if (tsc_data && tsc_data->vdd_reg) { + if (tsc_data->penup_threshold > (ADC_MAX >> 3)) + data->penup_threshold = (ADC_MAX >> 3); + else if (tsc_data->penup_threshold > 0) + data->penup_threshold = tsc_data->penup_threshold; + else + data->penup_threshold = 10; + + data->vdd_reg = regulator_get(&client->dev, tsc_data->vdd_reg); + if (!IS_ERR(data->vdd_reg)) + regulator_enable(data->vdd_reg); + else + data->vdd_reg = NULL; + if (tsc_data->active) + tsc_data->active(); + } else { + data->vdd_reg = NULL; + data->penup_threshold = 10; + } + + err = tsc2007_powerdown(data); + if (err >= 0) { + data->m = M_12BIT; + + err = tsc2007_driver_register(data); + if (err < 0) + goto exit; + + return 0; + } + + exit: + return err; +} + +static const struct i2c_device_id tsc2007_id[] = { + { "tsc2007", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, tsc2007_id); + +static struct i2c_driver tsc2007_driver = { + .driver = { + .name = DRIVER_NAME, + }, + .probe = tsc2007_i2c_probe, + .remove = tsc2007_i2c_remove, + .suspend = tsc2007_suspend, + .resume = tsc2007_resume, + .command = NULL, + .id_table = tsc2007_id, +}; + +static int __init tsc2007_init(void) +{ + return i2c_add_driver(&tsc2007_driver); +} + +static void __exit tsc2007_exit(void) +{ + i2c_del_driver(&tsc2007_driver); +} + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("tsc2007 Touch Screen Controller driver"); +MODULE_LICENSE("GPL"); + +module_init(tsc2007_init); +module_exit(tsc2007_exit); diff -urN linux-2.6.26/drivers/input/volume/Kconfig linux-2.6.26-lab126/drivers/input/volume/Kconfig --- linux-2.6.26/drivers/input/volume/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/input/volume/Kconfig 2010-08-10 04:15:44.000000000 -0400 @@ -0,0 +1,14 @@ +# +# Volume keys driver configuration +# +config INPUT_VOLUME + tristate "Volume Keys" + depends on INPUT + help + Say Y here if you have volume keys connected to your system. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called volume. + diff -urN linux-2.6.26/drivers/input/volume/Makefile linux-2.6.26-lab126/drivers/input/volume/Makefile --- linux-2.6.26/drivers/input/volume/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/input/volume/Makefile 2010-08-10 04:15:44.000000000 -0400 @@ -0,0 +1,5 @@ +# +# Volume keys controller driver +# +obj-$(CONFIG_INPUT_VOLUME) += volume.o + diff -urN linux-2.6.26/drivers/input/volume/volume.c linux-2.6.26-lab126/drivers/input/volume/volume.c --- linux-2.6.26/drivers/input/volume/volume.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/input/volume/volume.c 2010-08-10 04:15:44.000000000 -0400 @@ -0,0 +1,567 @@ +/* +** Volume Keys driver routine for Luigi. +** Copyright (C) 2009 Amazon Technologies, Inc. All Rights Reserved. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +// Logging +static unsigned int logging_mask; +#define LLOG_G_LOG_MASK logging_mask +#define LLOG_KERNEL_COMP "volume" +#include + +#include "volume.h" + +// Input device structure +static struct input_dev *volume_dev = NULL; + +// Global variables + +static char line_state[NUM_OF_LINES]; + +// Workqueue +static struct delayed_work volume_debounce_tq_d; +static struct delayed_work volume_auto_repeat_tq_d; +static void volume_debounce_wk(struct work_struct *); +static void volume_auto_repeat_wk(struct work_struct *); + +// Proc entry structure and global variable. +#define VOLUME_PROC_FILE "volume" +#define PROC_CMD_LEN 50 +static struct proc_dir_entry *proc_entry; + + +// Module parameters + +#define DEBOUNCE_TIMEOUT_DEFAULT 60 +static int debounce_timeout = DEBOUNCE_TIMEOUT_DEFAULT; +module_param(debounce_timeout, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(debounce_timeout, "Time for debouncing the volume switch, in msec; MUST be a multiple of 10 (default is 60)"); + +#define HOLD_TIMEOUT_DEFAULT 500 +static int volume_hold_timeout = HOLD_TIMEOUT_DEFAULT; +module_param(volume_hold_timeout, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(volume_hold_timeout, "Time before holding volume key starts auto-repeat mode, in msec; MUST be a multiple of 10 (default is 500; 0 = no auto-repeat)"); + +#define AUTO_REPEAT_TIMEOUT_DEFAULT 300 +static int volume_auto_repeat_time = AUTO_REPEAT_TIMEOUT_DEFAULT; +module_param(volume_auto_repeat_time, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(volume_auto_repeat_time, "Time between volume key auto-repeat events; MUST be a multiple of 10 (default is 300; 0 = no auto-repeat)"); + +static int debug = 0; +module_param(debug, int, S_IRUGO|S_IWUSR); +MODULE_PARM_DESC(debug, "Enable debugging; 0=off, any other value=on (default is off)"); + + +/* + * Set the log mask depending on the debug level + */ +static void set_debug_log_mask(int debug_level) +{ + logging_mask = LLOG_LEVEL_MASK_INFO | LLOG_LEVEL_MASK_EXCEPTIONS; + switch (debug_level) { + case 10: logging_mask |= LLOG_LEVEL_DEBUG9; + case 9: logging_mask |= LLOG_LEVEL_DEBUG8; + case 8: logging_mask |= LLOG_LEVEL_DEBUG7; + case 7: logging_mask |= LLOG_LEVEL_DEBUG6; + case 6: logging_mask |= LLOG_LEVEL_DEBUG5; + case 5: logging_mask |= LLOG_LEVEL_DEBUG4; + case 4: logging_mask |= LLOG_LEVEL_DEBUG3; + case 3: logging_mask |= LLOG_LEVEL_DEBUG2; + case 2: logging_mask |= LLOG_LEVEL_DEBUG1; + case 1: logging_mask |= LLOG_LEVEL_DEBUG0; + + case 0: + default: ; // No logging if debug_level <= 0 or > 10 + } +} + + +/* + * Report the volume event. In addition to calling + * input_event, this function sends a uevent for any + * processes listening in the userspace + */ +static void report_event(struct input_dev *dev, unsigned int type, unsigned int code, int value) +{ + input_event( dev, type, code, value ); + + // Send uevent so userspace power daemon can monitor + // volume activity + // NOTE: only sending uevent on key down as per Manish + + if (value == 1) { + schedule(); + if( kobject_uevent( &dev->dev.kobj, KOBJ_CHANGE ) ) + { + LLOG_ERROR("uevent", "", "Volume driver failed to send uevent\n" ); + } + } +} + +#define AUTO_RPT(dbgstr, keycode, time, line) \ + LLOG_DEBUG0("Got Volume Key repeat timeout: %s\n", dbgstr); \ + report_event(volume_dev, EV_KEY, keycode, 2); \ + timeout = time; \ + line_state[line] = LINE_HELD; \ + done = false; + +extern int volume_datain(int); + +static void volume_auto_repeat_wk(struct work_struct *work) +{ + int timeout = 0; + bool done = true; + + LLOG_DEBUG0("Got auto-repeat timeout\n"); + // Send appropriate event, depending on button held + if ( volume_datain(VOL_UP_LINE) == 0 ) { + AUTO_RPT("VOL_UP", VOL_UP_KEYCODE, volume_auto_repeat_time, VOL_UP_LINE); + } + if ( volume_datain(VOL_DOWN_LINE) == 0 ) { + AUTO_RPT("VOL_DOWN", VOL_DOWN_KEYCODE, volume_auto_repeat_time, VOL_DOWN_LINE); + } + if (done) { + // Do not restart the auto-repeat work because no more buttons are pressed + return; + } + + // Start the auto-repeat work item again, with the repeat-key parameter + // Convert from ms to jiffies + schedule_delayed_work(&volume_auto_repeat_tq_d, ((timeout * HZ) / 1000)); +} + + +#define PUSHED(dbgstr, keycode, time, irq, line) \ + LLOG_DEBUG0("Got Volume signal push: %s\n", dbgstr); \ + report_event(volume_dev, EV_KEY, keycode, 1); \ + timeout = time; \ + set_irq_type(irq, IRQF_TRIGGER_RISING); \ + line_state[line] = LINE_ASSERTED; + +#define RELEASED(dbgstr, keycode, line, irq) \ + LLOG_DEBUG0("Got Volume signal release: %s\n", dbgstr); \ + report_event(volume_dev, EV_KEY, keycode, 0); \ + line_state[line] = LINE_DEASSERTED; \ + set_irq_type(irq, IRQF_TRIGGER_FALLING); + + +static void volume_debounce_wk(struct work_struct *work) +{ + int timeout = 0; + + LLOG_DEBUG1("Debounce period expired\n"); + // Send appropriate event, depending on button held + if ( volume_datain(VOL_UP_LINE) == 0 ) { + PUSHED("VOL_UP", VOL_UP_KEYCODE, volume_hold_timeout, + VOL_UP_IRQ, VOL_UP_LINE); + } + if ( volume_datain(VOL_DOWN_LINE) == 0 ) { + PUSHED("VOL_DOWN", VOL_DOWN_KEYCODE, volume_hold_timeout, + VOL_DOWN_IRQ, VOL_DOWN_LINE); + } + + // Check if any key was released + if (( volume_datain(VOL_UP_LINE) == 1 ) && + ( line_state[VOL_UP_LINE] != LINE_DEASSERTED )) { + RELEASED("VOL_UP", VOL_UP_KEYCODE, VOL_UP_LINE, VOL_UP_IRQ); + } + if (( volume_datain(VOL_DOWN_LINE) == 1 ) && + ( line_state[VOL_DOWN_LINE] != LINE_DEASSERTED )) { + RELEASED("VOL_DOWN", VOL_DOWN_KEYCODE, VOL_DOWN_LINE, VOL_DOWN_IRQ); + } + + if (timeout > 0) { + // Start the auto-repeat work item, with the repeat-key parameter + // Convert from ms to jiffies + schedule_delayed_work(&volume_auto_repeat_tq_d, ((timeout * HZ) / 1000)); + } +} + + +static irqreturn_t volume_irq (int irq, void *data, struct pt_regs *r) +{ + // If the debounce work item is pending, ignore the input signal + if (delayed_work_pending(&volume_debounce_tq_d)) { + LLOG_DEBUG0("Ignoring Volume Switch signal while debouncing switch\n"); + return IRQ_HANDLED; + } + + // Start the debounce delayed work item, to avoid spurious signals + LLOG_DEBUG1("Starting debounce delayed work item...\n"); + // To schedule debouncing work item, convert from ms to jiffies + schedule_delayed_work(&volume_debounce_tq_d, ((debounce_timeout * HZ) / 1000)); + + return IRQ_HANDLED; +} + + +/*! + * This function puts the Volume key driver in low-power mode/state, + * by disabling interrupts from the input lines. + */ +void volume_off(void) +{ + LLOG_DEBUG0("Stopping work items; disabling IRQs and pullups...\n"); + + // Disable IRQs and GPIOs + disable_irq(VOL_UP_IRQ); + disable_irq(VOL_DOWN_IRQ); + gpio_volume_inactive(); + + // Stop any pending delayed work items + cancel_delayed_work_sync(&volume_debounce_tq_d); + cancel_delayed_work_sync(&volume_auto_repeat_tq_d); +} + + +/*! + * Suspend function + * @param pdev the device structure used to give information on Volume drv + * to suspend + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int volume_suspend(struct platform_device *pdev, pm_message_t state) +{ + volume_off(); + + return 0; +} + + +/*! + * This function brings the Volume key driver back from low-power state, + * by re-enabling the line interrupts. + * + * @return The function always returns 0. + */ +void volume_on(void) +{ + LLOG_DEBUG0("Enabling GPIOs and IRQs...\n"); + + // Enable GPIOs and IRQs + gpio_volume_active(); + enable_irq(VOL_UP_IRQ); + enable_irq(VOL_DOWN_IRQ); +} + + +/*! + * This function brings the Volume key driver back from low-power state, + * by re-enabling the line interrupts. + * + * @param pdev the device structure used to give information on Keypad + * to resume + * + * @return The function always returns 0. + */ +static int volume_resume(struct platform_device *pdev) +{ + volume_on(); + + return 0; +} + + +/*! + * This function is called when the volume driver is opened. + * Since volume initialization is done in __init, nothing is done in open. + * + * @param dev Pointer to device inode + * + * @result The function always returns 0 + */ +static int volume_open(struct input_dev *dev) +{ + return 0; +} + + +/*! + * This function is called close the volume device. + * Nothing is done in this function, since every thing is taken care in + * __exit function. + * + * @param dev Pointer to device inode + * + */ +static void volume_close(struct input_dev *dev) +{ +} + + +/* + * This function returns the current state of the volume device + */ +int volume_proc_read( char *page, char **start, off_t off, + int count, int *eof, void *data ) +{ + int len; + + if (off > 0) { + *eof = 1; + return 0; + } + len = sprintf(page, "volume key driver is active\n"); + return len; +} + + +/* + * This function executes volume control commands based on the input string. + * unlock = unlock the volume + * lock = lock the volume + * send = send a volume event, simulating a line detection + * debug = set the debug level for logging messages (0=off) + */ +ssize_t volume_proc_write( struct file *filp, const char __user *buff, + unsigned long len, void *data ) + +{ + char command[PROC_CMD_LEN]; + int keycode; + + if (len > PROC_CMD_LEN) { + LLOG_ERROR("proc_len", "", "Volume command is too long!\n"); + return -ENOSPC; + } + + if (copy_from_user(command, buff, len)) { + return -EFAULT; + } + + if ( !strncmp(command, "send", 4) ) { + // Requested to send a keycode + sscanf(command, "send %d", &keycode); + LLOG_INFO("send_key", "", "Sending keycode %d\n", keycode); + report_event(volume_dev, EV_KEY, keycode, 1); + report_event(volume_dev, EV_KEY, keycode, 0); + } + else if ( !strncmp(command, "debug", 5) ) { + // Requested to set debug level + sscanf(command, "debug %d", &debug); + LLOG_INFO("debug", "", "Setting debug level to %d\n", debug); + set_debug_log_mask(debug); + } + else { + LLOG_ERROR("proc_cmd", "", "Unrecognized volume command\n"); + } + + return len; +} + + +/*! + * This function is called during the driver binding process. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions. + * + * @return The function returns 0 on successful registration. Otherwise returns + * specific error code. + */ +static int __devinit volume_probe(struct platform_device *pdev) +{ + int err = 0; + int i; + + LLOG_INFO("probe0", "", "Starting...\n"); + + /* Create proc entry */ + proc_entry = create_proc_entry(VOLUME_PROC_FILE, 0644, NULL); + if (proc_entry == NULL) { + LLOG_ERROR("probe1", "", "Volume could not create proc entry\n"); + err = -ENOMEM; + goto exit_probe; + } else { + proc_entry->read_proc = volume_proc_read; + proc_entry->write_proc = volume_proc_write; + proc_entry->owner = THIS_MODULE; + } + + // Set up the necessary GPIO lines for the 5-Way inputs + err = gpio_volume_active(); + if (err) { + LLOG_ERROR("gpio_fail", "", "Failed to set GPIO lines\n"); + goto del_proc_entry; + } + + // Initialize the line state array + for (i = 0; i < NUM_OF_LINES; i++) { + line_state[i] = LINE_DEASSERTED; + } + + // Set IRQ for volume GPIO lines; trigger on falling edges + // and register the IRQ service routines +#define SET_IRQ(irq) \ + set_irq_type(irq, IRQF_TRIGGER_FALLING); \ + err = request_irq(irq, (irq_handler_t) volume_irq, 0, "volume", NULL); + + SET_IRQ(VOL_UP_IRQ); + if (err != 0) { + LLOG_ERROR("vol_up_irq", "", "VOL_UP IRQ line = 0x%X; request status = %d\n", VOL_UP_IRQ, err); + goto release_gpios; + } + SET_IRQ(VOL_DOWN_IRQ); + if (err != 0) { + LLOG_ERROR("vol_down_irq", "", "VOL_DOWN IRQ line = 0x%X; request status = %d\n", VOL_DOWN_IRQ, err); + goto release_vol_up_irq; + } + + LLOG_INFO("probe_done", "", "GPIOs and IRQs have been set up\n"); + + // Set up the device file + volume_dev = input_allocate_device(); + if (!volume_dev) { + LLOG_ERROR("allocate_dev", "", "Not enough memory for input device\n"); + err = -ENOMEM; + goto release_vol_down_irq; + } + volume_dev->name = "volume"; + volume_dev->id.bustype = BUS_HOST; + volume_dev->open = volume_open; + volume_dev->close = volume_close; + volume_dev->evbit[0] = BIT(EV_KEY); + // Set up the keycodes sent by each of the Volume lines + set_bit(VOL_UP_KEYCODE, volume_dev->keybit); + set_bit(VOL_DOWN_KEYCODE, volume_dev->keybit); + + // Initialize work items + INIT_DELAYED_WORK(&volume_debounce_tq_d, volume_debounce_wk); + INIT_DELAYED_WORK(&volume_auto_repeat_tq_d, volume_auto_repeat_wk); + + err = input_register_device(volume_dev); + if (err) { + LLOG_ERROR("reg_dev", "", "Failed to register device\n"); + goto free_input_dev; + } + return 0; // Success! + + +free_input_dev: + input_free_device(volume_dev); +release_vol_down_irq: + free_irq(VOL_DOWN_IRQ, NULL); +release_vol_up_irq: + free_irq(VOL_UP_IRQ, NULL); +release_gpios: + gpio_volume_inactive(); +del_proc_entry: + remove_proc_entry(VOLUME_PROC_FILE, NULL); +exit_probe: + return err; +} + + +/*! + * Dissociates the driver from the volume device. + * + * @param pdev the device structure used to give information on which SDHC + * to remove + * + * @return The function always returns 0. + */ +static int __devexit volume_remove(struct platform_device *pdev) +{ + // Release IRQs and GPIO pins; disable pullups on output GPIOs + free_irq(VOL_UP_IRQ, NULL); + free_irq(VOL_DOWN_IRQ, NULL); + gpio_volume_inactive(); + + // Stop any pending delayed work items + cancel_delayed_work_sync(&volume_debounce_tq_d); + cancel_delayed_work_sync(&volume_auto_repeat_tq_d); + + remove_proc_entry(VOLUME_PROC_FILE, NULL); + input_unregister_device(volume_dev); + + LLOG_INFO("exit", "", "IRQs released and work functions stopped.\n"); + + return 0; +} + + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver volume_driver = { + .driver = { + .name = "volume", + .owner = THIS_MODULE, + //.bus = &platform_bus_type, + }, + .suspend = volume_suspend, + .resume = volume_resume, + .probe = volume_probe, + .remove = __devexit_p(volume_remove), +}; + +/*! + * This function is called for module initialization. + * It registers the volume char driver. + * + * @return 0 on success and a non-zero value on failure. + */ +static int __init volume_init(void) +{ + LLOG_INIT(); + set_debug_log_mask(debug); + platform_driver_register(&volume_driver); + volume_probe(NULL); + LLOG_INFO("drv", "", "Volume key driver loaded\n"); + return 0; +} + +/*! + * This function is called whenever the module is removed from the kernel. It + * unregisters the volume driver from kernel. + */ +static void __exit volume_exit(void) +{ + volume_remove(NULL); + platform_driver_unregister(&volume_driver); +} + + + +module_init(volume_init); +module_exit(volume_exit); + +MODULE_AUTHOR("Lab126"); +MODULE_DESCRIPTION("Volume Key Input Device Driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/input/volume/volume.h linux-2.6.26-lab126/drivers/input/volume/volume.h --- linux-2.6.26/drivers/input/volume/volume.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/input/volume/volume.h 2010-08-10 04:15:44.000000000 -0400 @@ -0,0 +1,38 @@ +// +// Definitions for volume keys driver +// + +#include + +// Volume line enumeration +enum { + VOL_UP_LINE, + VOL_DOWN_LINE, +}; + +// Function that returns the IRQ number for a given 5-Way line +extern int volume_get_irq(int); + +// IRQ definitions, only for those inputs that generate interrupts +#define VOL_UP_IRQ volume_get_irq(VOL_UP_LINE) +#define VOL_DOWN_IRQ volume_get_irq(VOL_DOWN_LINE) + +// Keycodes generated by volume events +#define VOL_UP_KEYCODE KEY_VOLUMEUP +#define VOL_DOWN_KEYCODE KEY_VOLUMEDOWN + +// Line states +#define NUM_OF_LINES 2 +enum { + LINE_ASSERTED, + LINE_DEASSERTED, + LINE_HELD, +}; + +// External function definitions +static int __init volume_init(void); +static void __exit volume_exit(void); +static irqreturn_t volume_irq(int irq, void *data, struct pt_regs *r); + +extern int gpio_volume_active(void); +extern void gpio_volume_inactive(void); diff -urN linux-2.6.26/drivers/leds/Kconfig linux-2.6.26-lab126/drivers/leds/Kconfig --- linux-2.6.26/drivers/leds/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/leds/Kconfig 2010-08-10 04:17:02.000000000 -0400 @@ -24,6 +24,10 @@ This option enables support for LEDs driven using outputs of the dedicated PWM controller found on newer Atmel SOCs. +config LEDS_MC13892 + tristate "LED Support for mc13892 pmic" + depends on LEDS_CLASS && MXC_MC13892_LIGHT + config LEDS_CORGI tristate "LED Support for the Sharp SL-C7x0 series" depends on LEDS_CLASS && PXA_SHARP_C7xx diff -urN linux-2.6.26/drivers/leds/Makefile linux-2.6.26-lab126/drivers/leds/Makefile --- linux-2.6.26/drivers/leds/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/leds/Makefile 2010-08-10 04:17:02.000000000 -0400 @@ -6,6 +6,7 @@ # LED Platform Drivers obj-$(CONFIG_LEDS_ATMEL_PWM) += leds-atmel-pwm.o +obj-$(CONFIG_LEDS_MC13892) += leds-mc13892.o obj-$(CONFIG_LEDS_CORGI) += leds-corgi.o obj-$(CONFIG_LEDS_LOCOMO) += leds-locomo.o obj-$(CONFIG_LEDS_SPITZ) += leds-spitz.o diff -urN linux-2.6.26/drivers/leds/leds-mc13892.c linux-2.6.26-lab126/drivers/leds/leds-mc13892.c --- linux-2.6.26/drivers/leds/leds-mc13892.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/leds/leds-mc13892.c 2010-08-10 04:17:02.000000000 -0400 @@ -0,0 +1,162 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_MACH_LUIGI_LAB126 + +extern int luigi_button_green_led; + +#endif + +static void mc13892_led_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + struct platform_device *dev = to_platform_device(led_cdev->dev->parent); + int led_ch; + +#ifdef CONFIG_MACH_LUIGI_LAB126 + if (luigi_button_green_led) + return; +#endif + switch (dev->id) { + case 'r': + led_ch = LIT_RED; + break; + case 'g': + led_ch = LIT_GREEN; + break; + case 'b': + led_ch = LIT_BLUE; + break; + default: + return; + } + + /* set current with medium value, in case current is too large */ + mc13892_bklit_set_current(led_ch, LIT_CURR_12); + /* max duty cycle is 63, brightness needs to be divided by 4 */ + mc13892_bklit_set_dutycycle(led_ch, value / 4); + +} + +static int mc13892_led_remove(struct platform_device *dev) +{ + struct led_classdev *led_cdev = platform_get_drvdata(dev); + + led_classdev_unregister(led_cdev); + kfree(led_cdev->name); + kfree(led_cdev); + + return 0; +} + +#define LED_NAME_LEN 16 + +static int mc13892_led_probe(struct platform_device *dev) +{ + int ret; + struct led_classdev *led_cdev; + char *name; + + led_cdev = kzalloc(sizeof(struct led_classdev), GFP_KERNEL); + if (led_cdev == NULL) { + dev_err(&dev->dev, "No memory for device\n"); + return -ENOMEM; + } + name = kzalloc(LED_NAME_LEN, GFP_KERNEL); + if (name == NULL) { + dev_err(&dev->dev, "No memory for device\n"); + ret = -ENOMEM; + goto exit_err; + } + + strcpy(name, dev->name); + ret = strlen(dev->name); + if (ret > LED_NAME_LEN - 2) { + dev_err(&dev->dev, "led name is too long\n"); + goto exit_err1; + } + name[ret] = dev->id; + name[ret + 1] = '\0'; + led_cdev->name = name; + led_cdev->brightness_set = mc13892_led_set; + + ret = led_classdev_register(&dev->dev, led_cdev); + if (ret < 0) { + dev_err(&dev->dev, "led_classdev_register failed\n"); + goto exit_err1; + } + + platform_set_drvdata(dev, led_cdev); + + return 0; + exit_err1: + kfree(led_cdev->name); + exit_err: + kfree(led_cdev); + return ret; +} + +#ifdef CONFIG_PM +static int mc13892_led_suspend(struct platform_device *dev, pm_message_t state) +{ + struct led_classdev *led_cdev = platform_get_drvdata(dev); + + led_classdev_suspend(led_cdev); + return 0; +} + +static int mc13892_led_resume(struct platform_device *dev) +{ + struct led_classdev *led_cdev = platform_get_drvdata(dev); + + led_classdev_resume(led_cdev); + return 0; +} +#else +#define mc13892_led_suspend NULL +#define mc13892_led_resume NULL +#endif + +static struct platform_driver mc13892_led_driver = { + .probe = mc13892_led_probe, + .remove = mc13892_led_remove, + .suspend = mc13892_led_suspend, + .resume = mc13892_led_resume, + .driver = { + .name = "pmic_leds", + .owner = THIS_MODULE, + }, +}; + +static int __init mc13892_led_init(void) +{ + return platform_driver_register(&mc13892_led_driver); +} + +static void __exit mc13892_led_exit(void) +{ + platform_driver_unregister(&mc13892_led_driver); +} + +module_init(mc13892_led_init); +module_exit(mc13892_led_exit); + +MODULE_DESCRIPTION("Led driver for PMIC mc13892"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/macintosh/adb.c linux-2.6.26-lab126/drivers/macintosh/adb.c --- linux-2.6.26/drivers/macintosh/adb.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/macintosh/adb.c 2010-08-10 04:16:00.000000000 -0400 @@ -84,7 +84,7 @@ BLOCKING_NOTIFIER_HEAD(adb_client_list); static int adb_got_sleep; static int adb_inited; -static DECLARE_MUTEX(adb_probe_mutex); +static COMPAT_DECLARE_MUTEX(adb_probe_mutex); static int sleepy_trackpad; static int autopoll_devs; int __adb_probe_sync; diff -urN linux-2.6.26/drivers/md/.gitignore linux-2.6.26-lab126/drivers/md/.gitignore --- linux-2.6.26/drivers/md/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/md/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,4 +0,0 @@ -mktables -raid6altivec*.c -raid6int*.c -raid6tables.c diff -urN linux-2.6.26/drivers/media/dvb/dvb-core/dvb_frontend.c linux-2.6.26-lab126/drivers/media/dvb/dvb-core/dvb_frontend.c --- linux-2.6.26/drivers/media/dvb/dvb-core/dvb_frontend.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/media/dvb/dvb-core/dvb_frontend.c 2010-08-10 04:15:25.000000000 -0400 @@ -97,7 +97,7 @@ struct dvb_device *dvbdev; struct dvb_frontend_parameters parameters; struct dvb_fe_events events; - struct semaphore sem; + struct compat_semaphore sem; struct list_head list_head; wait_queue_head_t wait_queue; struct task_struct *thread; diff -urN linux-2.6.26/drivers/media/video/Kconfig linux-2.6.26-lab126/drivers/media/video/Kconfig --- linux-2.6.26/drivers/media/video/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/media/video/Kconfig 2010-08-10 04:15:24.000000000 -0400 @@ -519,6 +519,33 @@ Check out for more information. +config VIDEO_MXC_CAMERA + tristate "MXC Video For Linux Camera" + depends on VIDEO_DEV && ARCH_MXC + default y + ---help--- + This is the video4linux2 capture driver based on MXC IPU/eMMA module. + +source "drivers/media/video/mxc/capture/Kconfig" + +config VIDEO_MXC_OUTPUT + tristate "MXC Video For Linux Video Output" + depends on VIDEO_DEV && ARCH_MXC + default y + ---help--- + This is the video4linux2 output driver based on MXC IPU/eMMA module. + +source "drivers/media/video/mxc/output/Kconfig" + +config VIDEO_MXC_OPL + tristate + depends on VIDEO_DEV && ARCH_MXC + default n + ---help--- + This is the ARM9-optimized OPL (Open Primitives Library) software + rotation/mirroring implementation. It may be used by eMMA video + capture or output device. + config VIDEO_CPIA tristate "CPiA Video For Linux" depends on VIDEO_V4L1 diff -urN linux-2.6.26/drivers/media/video/Makefile linux-2.6.26-lab126/drivers/media/video/Makefile --- linux-2.6.26/drivers/media/video/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/media/video/Makefile 2010-08-10 04:15:24.000000000 -0400 @@ -58,6 +58,12 @@ obj-$(CONFIG_VIDEO_PLANB) += planb.o obj-$(CONFIG_VIDEO_VINO) += vino.o indycam.o obj-$(CONFIG_VIDEO_STRADIS) += stradis.o +obj-$(CONFIG_VIDEO_MXC_IPU_CAMERA) += mxc/capture/ +obj-$(CONFIG_VIDEO_MXC_EMMA_CAMERA) += mxc/capture/ +obj-$(CONFIG_VIDEO_MXC_IPU_OUTPUT) += mxc/output/ +obj-$(CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT) += mxc/output/ +obj-$(CONFIG_VIDEO_MXC_EMMA_OUTPUT) += mxc/output/ +obj-$(CONFIG_VIDEO_MXC_OPL) += mxc/opl/ obj-$(CONFIG_VIDEO_CPIA) += cpia.o obj-$(CONFIG_VIDEO_CPIA_PP) += cpia_pp.o obj-$(CONFIG_VIDEO_CPIA_USB) += cpia_usb.o diff -urN linux-2.6.26/drivers/media/video/mxc/capture/Kconfig linux-2.6.26-lab126/drivers/media/video/mxc/capture/Kconfig --- linux-2.6.26/drivers/media/video/mxc/capture/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/Kconfig 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,111 @@ +if VIDEO_MXC_CAMERA + +menu "MXC Camera/V4L2 PRP Features support" +config VIDEO_MXC_IPU_CAMERA + bool + depends on VIDEO_MXC_CAMERA && MXC_IPU + default y + +config VIDEO_MXC_EMMA_CAMERA + tristate "MX27 eMMA support" + depends on VIDEO_MXC_CAMERA && MXC_EMMA && FB_MXC_SYNC_PANEL + select VIDEO_MXC_OPL + default y + +config VIDEO_MXC_CSI_DMA + bool "CSI-DMA Still Image Capture support" + depends on VIDEO_MXC_EMMA_CAMERA + default n + ---help--- + Use CSI-DMA method instead of CSI-PrP link to capture still image. This allows + to use less physical contiguous memory to capture big resolution still image. But + with this method the CSC (Color Space Conversion) and resize are not supported. + If unsure, say N. + +choice + prompt "Select Camera/TV Decoder" + default MXC_CAMERA_OV3640 + depends on VIDEO_MXC_CAMERA + +config MXC_CAMERA_MC521DA + tristate "Magnachip mc521da camera support" + select I2C_MXC + depends on VIDEO_MXC_EMMA_CAMERA + ---help--- + If you plan to use the mc521da Camera with your MXC system, say Y here. + +config MXC_EMMA_CAMERA_MICRON111 + tristate "Micron mt9v111 camera support with eMMA" + select I2C_MXC + depends on VIDEO_MXC_EMMA_CAMERA + ---help--- + If you plan to use the mt9v111 Camera with your MXC system, say Y here. + +config MXC_CAMERA_OV2640_EMMA + tristate "OmniVision ov2640 camera support with eMMA" + depends on VIDEO_MXC_EMMA_CAMERA + ---help--- + If you plan to use the ov2640 Camera with your MXC system, say Y here. + +config MXC_CAMERA_MICRON111 + tristate "Micron mt9v111 camera support" + select I2C_MXC + depends on ! VIDEO_MXC_EMMA_CAMERA + ---help--- + If you plan to use the mt9v111 Camera with your MXC system, say Y here. + +config MXC_CAMERA_OV2640 + tristate "OmniVision ov2640 camera support" + depends on !VIDEO_MXC_EMMA_CAMERA + ---help--- + If you plan to use the ov2640 Camera with your MXC system, say Y here. + +config MXC_CAMERA_OV3640 + tristate "OmniVision ov3640 camera support" + depends on !VIDEO_MXC_EMMA_CAMERA + ---help--- + If you plan to use the ov3640 Camera with your MXC system, say Y here. + +config MXC_TVIN_ADV7180 + tristate "Analog Device adv7180 TV Decoder Input support" + depends on MACH_MX35_3DS + ---help--- + If you plan to use the adv7180 video decoder with your MXC system, say Y here. + +endchoice + +config MXC_IPU_PRP_VF_SDC + tristate "Pre-Processor VF SDC library" + depends on VIDEO_MXC_IPU_CAMERA && FB_MXC_SYNC_PANEL + default y + ---help--- + Use case PRP_VF_SDC: + Preprocessing image from smart sensor for viewfinder and + displaying it on synchronous display with SDC use case. + If SDC BG is selected, Rotation will not be supported. + CSI -> IC (PRP VF) -> MEM + MEM -> IC (ROT) -> MEM + MEM -> SDC (FG/BG) + +config MXC_IPU_PRP_VF_ADC + tristate "Pre-Processor VF ADC library" + depends on VIDEO_MXC_IPU_CAMERA && FB_MXC_ASYNC_PANEL + default y + ---help--- + Use case PRP_VF_ADC: + Preprocessing image from smart sensor for viewfinder and + displaying it on asynchronous display. + CSI -> IC (PRP VF) -> ADC2 + +config MXC_IPU_PRP_ENC + tristate "Pre-processor Encoder library" + depends on VIDEO_MXC_IPU_CAMERA + default y + ---help--- + Use case PRP_ENC: + Preprocessing image from smart sensor for encoder. + CSI -> IC (PRP ENC) -> MEM + +endmenu + +endif diff -urN linux-2.6.26/drivers/media/video/mxc/capture/Makefile linux-2.6.26-lab126/drivers/media/video/mxc/capture/Makefile --- linux-2.6.26/drivers/media/video/mxc/capture/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/Makefile 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,36 @@ +ifeq ($(CONFIG_VIDEO_MXC_IPU_CAMERA),y) + obj-$(CONFIG_VIDEO_MXC_CAMERA) += mxc_v4l2_capture.o + obj-$(CONFIG_MXC_IPU_PRP_VF_ADC) += ipu_prp_vf_adc.o + obj-$(CONFIG_MXC_IPU_PRP_VF_SDC) += ipu_prp_vf_sdc.o ipu_prp_vf_sdc_bg.o + obj-$(CONFIG_MXC_IPU_PRP_ENC) += ipu_prp_enc.o ipu_still.o +endif + +mx27_capture-objs := mx27_prphw.o mx27_prpsw.o emma_v4l2_capture.o +obj-$(CONFIG_VIDEO_MXC_EMMA_CAMERA) += mx27_csi.o mx27_capture.o + +mc521da_camera-objs := mc521da.o sensor_clock.o +obj-$(CONFIG_MXC_CAMERA_MC521DA) += mc521da_camera.o + +emma_mt9v111_camera-objs := emma_mt9v111.o sensor_clock.o +obj-$(CONFIG_MXC_EMMA_CAMERA_MICRON111) += emma_mt9v111_camera.o + +mt9v111_camera-objs := mt9v111.o sensor_clock.o +obj-$(CONFIG_MXC_CAMERA_MICRON111) += mt9v111_camera.o + +hv7161_camera-objs := hv7161.o sensor_clock.o +obj-$(CONFIG_MXC_CAMERA_HV7161) += hv7161_camera.o + +s5k3aaex_camera-objs := s5k3aaex.o sensor_clock.o +obj-$(CONFIG_MXC_CAMERA_S5K3AAEX) += s5k3aaex_camera.o + +emma_ov2640_camera-objs := emma_ov2640.o sensor_clock.o +obj-$(CONFIG_MXC_CAMERA_OV2640_EMMA) += emma_ov2640_camera.o + +ov2640_camera-objs := ov2640.o sensor_clock.o +obj-$(CONFIG_MXC_CAMERA_OV2640) += ov2640_camera.o + +ov3640_camera-objs := ov3640.o sensor_clock.o +obj-$(CONFIG_MXC_CAMERA_OV3640) += ov3640_camera.o + +adv7180_tvin-objs := adv7180.o sensor_clock.o +obj-$(CONFIG_MXC_TVIN_ADV7180) += adv7180_tvin.o diff -urN linux-2.6.26/drivers/media/video/mxc/capture/adv7180.c linux-2.6.26-lab126/drivers/media/video/mxc/capture/adv7180.c --- linux-2.6.26/drivers/media/video/mxc/capture/adv7180.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/adv7180.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,975 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file adv7180.c + * + * @brief Analog Device ADV7180 video decoder functions + * + * @ingroup Camera + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_v4l2_capture.h" + +static struct regulator *dvddio_regulator; +static struct regulator *dvdd_regulator; +static struct regulator *avdd_regulator; +static struct regulator *pvdd_regulator; + +extern void gpio_sensor_active(void); +extern void gpio_sensor_inactive(void); + +static int adv7180_probe(struct i2c_client *adapter, + const struct i2c_device_id *id); +static int adv7180_detach(struct i2c_client *client); + +static const struct i2c_device_id adv7180_id[] = { + {"adv7180", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, adv7180_id); + +static struct i2c_driver adv7180_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "adv7180", + }, + .probe = adv7180_probe, + .remove = adv7180_detach, + .id_table = adv7180_id, +}; + +/*! + * Maintains the information on the current state of the sesor. + */ +struct sensor { + struct v4l2_int_device *v4l2_int_device; + struct i2c_client *i2c_client; + struct v4l2_pix_format pix; + struct v4l2_captureparm streamcap; + bool on; + + /* control settings */ + int brightness; + int hue; + int contrast; + int saturation; + int red; + int green; + int blue; + int ae_mode; + + v4l2_std_id std_id; +} adv7180_data; + +/*! List of input video formats supported. The video formats is corresponding + * with v4l2 id in video_fmt_t + */ +typedef enum { + ADV7180_NTSC = 0, /*!< Locked on (M) NTSC video signal. */ + ADV7180_PAL, /*!< (B, G, H, I, N)PAL video signal. */ + ADV7180_NOT_LOCKED, /*!< Not locked on a signal. */ +} video_fmt_idx; + +/*! Number of video standards supported (including 'not locked' signal). */ +#define ADV7180_STD_MAX (ADV7180_PAL + 1) + +/*! Video format structure. */ +typedef struct { + int v4l2_id; /*!< Video for linux ID. */ + char name[16]; /*!< Name (e.g., "NTSC", "PAL", etc.) */ + u16 raw_width; /*!< Raw width. */ + u16 raw_height; /*!< Raw height. */ + u16 active_width; /*!< Active width. */ + u16 active_height; /*!< Active height. */ +} video_fmt_t; + +/*! Description of video formats supported. + * + * PAL: raw=720x625, active=720x576. + * NTSC: raw=720x525, active=720x480. + */ +static video_fmt_t video_fmts[] = { + { /*! NTSC */ + .v4l2_id = V4L2_STD_NTSC, + .name = "NTSC", + .raw_width = 720, /* SENS_FRM_WIDTH */ + .raw_height = 288, /* SENS_FRM_HEIGHT */ + .active_width = 720, /* ACT_FRM_WIDTH */ + .active_height = (480 / 2), /* ACT_FRM_WIDTH */ + }, + { /*! (B, G, H, I, N) PAL */ + .v4l2_id = V4L2_STD_PAL, + .name = "PAL", + .raw_width = 720, + .raw_height = (576 / 2) + 24 * 2, + .active_width = 720, + .active_height = (576 / 2), + }, + { /*! Unlocked standard */ + .v4l2_id = V4L2_STD_ALL, + .name = "Autodetect", + .raw_width = 720, + .raw_height = (576 / 2) + 24 * 2, + .active_width = 720, + .active_height = (576 / 2), + }, +}; + +/*!* Standard index of ADV7180. */ +static video_fmt_idx video_idx = ADV7180_PAL; + +/*! @brief This mutex is used to provide mutual exclusion. + * + * Create a mutex that can be used to provide mutually exclusive + * read/write access to the globally accessible data structures + * and variables that were defined above. + */ +static DECLARE_MUTEX(mutex); + +#define IF_NAME "adv7180" +#define ADV7180_INPUT_CTL 0x00 /* Input Control */ +#define ADV7180_STATUS_1 0x10 /* Status #1 */ +#define ADV7180_BRIGHTNESS 0x0a /* Brightness */ +#define ADV7180_IDENT 0x11 /* IDENT */ +#define ADV7180_VSYNC_FIELD_CTL_1 0x31 /* VSYNC Field Control #1 */ +#define ADV7180_MANUAL_WIN_CTL 0x3d /* Manual Window Control */ +#define ADV7180_SD_SATURATION_CB 0xe3 /* SD Saturation Cb */ +#define ADV7180_SD_SATURATION_CR 0xe4 /* SD Saturation Cr */ + +/* supported controls */ +/* This hasn't been fully implemented yet. + * This is how it should work, though. */ +static struct v4l2_queryctrl adv7180_qctrl[] = { + { + .id = V4L2_CID_BRIGHTNESS, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Brightness", + .minimum = 0, /* check this value */ + .maximum = 255, /* check this value */ + .step = 1, /* check this value */ + .default_value = 127, /* check this value */ + .flags = 0, + }, { + .id = V4L2_CID_SATURATION, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Saturation", + .minimum = 0, /* check this value */ + .maximum = 255, /* check this value */ + .step = 0x1, /* check this value */ + .default_value = 127, /* check this value */ + .flags = 0, + } +}; + +/*********************************************************************** + * I2C transfert. + ***********************************************************************/ + +/*! Read one register from a ADV7180 i2c slave device. + * + * @param *reg register in the device we wish to access. + * + * @return 0 if success, an error code otherwise. + */ +static inline int adv7180_read(u8 reg) +{ + int val; + val = i2c_smbus_read_byte_data(adv7180_data.i2c_client, reg); + if (val < 0) { + dev_dbg(&adv7180_data.i2c_client->dev, + "%s:read reg error: reg=%2x \n", __func__, reg); + return -1; + } + return val; +} + +/*! Write one register of a ADV7180 i2c slave device. + * + * @param *reg register in the device we wish to access. + * + * @return 0 if success, an error code otherwise. + */ +static int adv7180_write_reg(u8 reg, u8 val) +{ + if (i2c_smbus_write_byte_data(adv7180_data.i2c_client, reg, val) < 0) { + dev_dbg(&adv7180_data.i2c_client->dev, + "%s:write reg error:reg=%2x,val=%2x\n", __func__, + reg, val); + return -1; + } + return 0; +} + +/*********************************************************************** + * mxc_v4l2_capture interface. + ***********************************************************************/ + +/*! + * Return attributes of current video standard. + * Since this device autodetects the current standard, this function also + * sets the values that need to be changed if the standard changes. + * There is no set std equivalent function. + * + * @return None. + */ +static void adv7180_get_std(v4l2_std_id *std) +{ + int tmp; + int idx; + + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180_get_std\n"); + + /* Read the AD_RESULT to get the detect output video standard */ + tmp = adv7180_read(ADV7180_STATUS_1) & 0x70; + + down(&mutex); + if (tmp == 0x40) { + /* PAL */ + *std = V4L2_STD_PAL; + idx = ADV7180_PAL; + } else if (tmp == 0) { + /*NTSC*/ + *std = V4L2_STD_NTSC; + idx = ADV7180_NTSC; + } else { + *std = V4L2_STD_ALL; + idx = ADV7180_NOT_LOCKED; + dev_dbg(&adv7180_data.i2c_client->dev, + "Got invalid video standard! \n"); + } + up(&mutex); + + /* This assumes autodetect which this device uses. */ + if (*std != adv7180_data.std_id) { + video_idx = idx; + adv7180_data.std_id = *std; + adv7180_data.pix.width = video_fmts[video_idx].raw_width; + adv7180_data.pix.height = video_fmts[video_idx].raw_height; + } +} + +/*********************************************************************** + * IOCTL Functions from v4l2_int_ioctl_desc. + ***********************************************************************/ + +/*! + * ioctl_g_ifparm - V4L2 sensor interface handler for vidioc_int_g_ifparm_num + * s: pointer to standard V4L2 device structure + * p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure + * + * Gets slave interface parameters. + * Calculates the required xclk value to support the requested + * clock parameters in p. This value is returned in the p + * parameter. + * + * vidioc_int_g_ifparm returns platform-specific information about the + * interface settings used by the sensor. + * + * Called on open. + */ +static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) +{ + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_g_ifparm\n"); + + if (s == NULL) { + pr_err(" ERROR!! no slave device set!\n"); + return -1; + } + + /* Initialize structure to 0s then set any non-0 values. */ + memset(p, 0, sizeof(*p)); + p->if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility. */ + p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; + p->u.bt656.nobt_hs_inv = 1; + + /* ADV7180 has a dedicated clock so no clock settings needed. */ + + return 0; +} + +/*! + * Sets the camera power. + * + * s pointer to the camera device + * on if 1, power is to be turned on. 0 means power is to be turned off + * + * ioctl_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num + * @s: pointer to standard V4L2 device structure + * @on: power state to which device is to be set + * + * Sets devices power state to requrested state, if possible. + * This is called on open, close, suspend and resume. + */ +static int ioctl_s_power(struct v4l2_int_device *s, int on) +{ + struct sensor *sensor = s->priv; + + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_s_power\n"); + + sensor->on = on; + + if (on) + gpio_sensor_active(); + else + gpio_sensor_inactive(); + + return 0; +} + +/*! + * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure + * + * Returns the sensor's video CAPTURE parameters. + */ +static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor *sensor = s->priv; + struct v4l2_captureparm *cparm = &a->parm.capture; + + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_g_parm\n"); + + switch (a->type) { + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); + memset(a, 0, sizeof(*a)); + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cparm->capability = sensor->streamcap.capability; + cparm->timeperframe = sensor->streamcap.timeperframe; + cparm->capturemode = sensor->streamcap.capturemode; + break; + + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + break; + + default: + pr_debug("ioctl_g_parm:type is unknown %d\n", a->type); + break; + } + + return 0; +} + +/*! + * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure + * + * Configures the sensor to use the input parameters, if possible. If + * not possible, reverts to the old parameters and returns the + * appropriate error code. + * + * This driver cannot change these settings. + */ +static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_s_parm\n"); + + switch (a->type) { + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + break; + } + + return 0; +} + +/*! + * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap + * @s: pointer to standard V4L2 device structure + * @f: pointer to standard V4L2 v4l2_format structure + * + * Returns the sensor's current pixel format in the v4l2_format + * parameter. + */ +static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) +{ + struct sensor *sensor = s->priv; + + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_g_fmt_cap\n"); + + switch (f->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" Returning size of %dx%d\n", + sensor->pix.width, sensor->pix.height); + f->fmt.pix = sensor->pix; + break; + + case V4L2_BUF_TYPE_PRIVATE: { + v4l2_std_id std; + adv7180_get_std(&std); + f->fmt.pix.pixelformat = (u32)std; + } + break; + + default: + f->fmt.pix = sensor->pix; + break; + } + + return 0; +} + +/*! + * ioctl_queryctrl - V4L2 sensor interface handler for VIDIOC_QUERYCTRL ioctl + * @s: pointer to standard V4L2 device structure + * @qc: standard V4L2 VIDIOC_QUERYCTRL ioctl structure + * + * If the requested control is supported, returns the control information + * from the video_control[] array. Otherwise, returns -EINVAL if the + * control is not supported. + */ +static int ioctl_queryctrl(struct v4l2_int_device *s, + struct v4l2_queryctrl *qc) +{ + int i; + + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_queryctrl\n"); + + for (i = 0; i < ARRAY_SIZE(adv7180_qctrl); i++) + if (qc->id && qc->id == adv7180_qctrl[i].id) { + memcpy(qc, &(adv7180_qctrl[i]), + sizeof(*qc)); + return (0); + } + + return -EINVAL; +} + +/*! + * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure + * + * If the requested control is supported, returns the control's current + * value from the video_control[] array. Otherwise, returns -EINVAL + * if the control is not supported. + */ +static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int ret = 0; + + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_g_ctrl\n"); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_BRIGHTNESS\n"); + adv7180_data.brightness = adv7180_read(ADV7180_BRIGHTNESS); + vc->value = adv7180_data.brightness; + break; + case V4L2_CID_CONTRAST: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_CONTRAST\n"); + vc->value = adv7180_data.contrast; + break; + case V4L2_CID_SATURATION: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_SATURATION\n"); + adv7180_data.saturation = adv7180_read(ADV7180_SD_SATURATION_CB); + vc->value = adv7180_data.saturation; + break; + case V4L2_CID_HUE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_HUE\n"); + vc->value = adv7180_data.hue; + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_AUTO_WHITE_BALANCE\n"); + break; + case V4L2_CID_DO_WHITE_BALANCE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_DO_WHITE_BALANCE\n"); + break; + case V4L2_CID_RED_BALANCE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_RED_BALANCE\n"); + vc->value = adv7180_data.red; + break; + case V4L2_CID_BLUE_BALANCE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_BLUE_BALANCE\n"); + vc->value = adv7180_data.blue; + break; + case V4L2_CID_GAMMA: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_GAMMA\n"); + break; + case V4L2_CID_EXPOSURE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_EXPOSURE\n"); + vc->value = adv7180_data.ae_mode; + break; + case V4L2_CID_AUTOGAIN: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_AUTOGAIN\n"); + break; + case V4L2_CID_GAIN: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_GAIN\n"); + break; + case V4L2_CID_HFLIP: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_HFLIP\n"); + break; + case V4L2_CID_VFLIP: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_VFLIP\n"); + break; + default: + dev_dbg(&adv7180_data.i2c_client->dev, + " Default case\n"); + vc->value = 0; + ret = -EPERM; + break; + } + + return ret; +} + +/*! + * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure + * + * If the requested control is supported, sets the control's current + * value in HW (and updates the video_control[] array). Otherwise, + * returns -EINVAL if the control is not supported. + */ +static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int retval = 0; + u8 tmp; + + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_s_ctrl\n"); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_BRIGHTNESS\n"); + tmp = vc->value; + adv7180_write_reg(ADV7180_BRIGHTNESS, tmp); + adv7180_data.brightness = vc->value; + break; + case V4L2_CID_CONTRAST: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_CONTRAST\n"); + break; + case V4L2_CID_SATURATION: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_SATURATION\n"); + tmp = vc->value; + adv7180_write_reg(ADV7180_SD_SATURATION_CB, tmp); + adv7180_write_reg(ADV7180_SD_SATURATION_CR, tmp); + adv7180_data.saturation = vc->value; + break; + case V4L2_CID_HUE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_HUE\n"); + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_AUTO_WHITE_BALANCE\n"); + break; + case V4L2_CID_DO_WHITE_BALANCE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_DO_WHITE_BALANCE\n"); + break; + case V4L2_CID_RED_BALANCE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_RED_BALANCE\n"); + break; + case V4L2_CID_BLUE_BALANCE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_BLUE_BALANCE\n"); + break; + case V4L2_CID_GAMMA: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_GAMMA\n"); + break; + case V4L2_CID_EXPOSURE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_EXPOSURE\n"); + break; + case V4L2_CID_AUTOGAIN: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_AUTOGAIN\n"); + break; + case V4L2_CID_GAIN: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_GAIN\n"); + break; + case V4L2_CID_HFLIP: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_HFLIP\n"); + break; + case V4L2_CID_VFLIP: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_VFLIP\n"); + break; + default: + dev_dbg(&adv7180_data.i2c_client->dev, + " Default case\n"); + retval = -EPERM; + break; + } + + return retval; +} + +/*! + * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT + * @s: pointer to standard V4L2 device structure + */ +static int ioctl_init(struct v4l2_int_device *s) +{ + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_init\n"); + return 0; +} + +/*! + * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num + * @s: pointer to standard V4L2 device structure + * + * Initialise the device when slave attaches to the master. + */ +static int ioctl_dev_init(struct v4l2_int_device *s) +{ + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_dev_init\n"); + return 0; +} + +/*! + * This structure defines all the ioctls for this module. + */ +static struct v4l2_int_ioctl_desc adv7180_ioctl_desc[] = { + + {vidioc_int_dev_init_num, (v4l2_int_ioctl_func *)ioctl_dev_init}, + + /*! + * Delinitialise the dev. at slave detach. + * The complement of ioctl_dev_init. + */ +/* {vidioc_int_dev_exit_num, (v4l2_int_ioctl_func *)ioctl_dev_exit}, */ + + {vidioc_int_s_power_num, (v4l2_int_ioctl_func *)ioctl_s_power}, + {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func *)ioctl_g_ifparm}, +/* {vidioc_int_g_needs_reset_num, + (v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */ +/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */ + {vidioc_int_init_num, (v4l2_int_ioctl_func *)ioctl_init}, + + /*! + * VIDIOC_ENUM_FMT ioctl for the CAPTURE buffer type. + */ +/* {vidioc_int_enum_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap}, */ + + /*! + * VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type. + * This ioctl is used to negotiate the image capture size and + * pixel format without actually making it take effect. + */ +/* {vidioc_int_try_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */ + + {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_g_fmt_cap}, + + /*! + * If the requested format is supported, configures the HW to use that + * format, returns error code if format not supported or HW can't be + * correctly configured. + */ +/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap}, */ + + {vidioc_int_g_parm_num, (v4l2_int_ioctl_func *)ioctl_g_parm}, + {vidioc_int_s_parm_num, (v4l2_int_ioctl_func *)ioctl_s_parm}, + {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func *)ioctl_queryctrl}, + {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *)ioctl_g_ctrl}, + {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *)ioctl_s_ctrl}, +}; + +static struct v4l2_int_slave adv7180_slave = { + .ioctls = adv7180_ioctl_desc, + .num_ioctls = ARRAY_SIZE(adv7180_ioctl_desc), +}; + +static struct v4l2_int_device adv7180_int_device = { + .module = THIS_MODULE, + .name = "adv7180", + .type = v4l2_int_type_slave, + .u = { + .slave = &adv7180_slave, + }, +}; + + +/*********************************************************************** + * I2C client and driver. + ***********************************************************************/ + +/*! ADV7180 Reset function. + * + * @return None. + */ +static void adv7180_hard_reset(void) +{ + dev_dbg(&adv7180_data.i2c_client->dev, + "In adv7180:adv7180_hard_reset\n"); + + /*! Driver works fine without explicit register + * initialization. Furthermore, initializations takes about 2 seconds + * at startup... + */ + + /*! Set YPbPr input on AIN1,4,5 and normal + * operations(autodection of all stds). + */ + adv7180_write_reg(ADV7180_INPUT_CTL, 0x09); + + /*! Datasheet recommends: */ + adv7180_write_reg(ADV7180_VSYNC_FIELD_CTL_1, 0x02); + adv7180_write_reg(ADV7180_MANUAL_WIN_CTL, 0xa2); +} + +/*! ADV7180 I2C attach function. + * + * @param *adapter struct i2c_adapter *. + * + * @return Error code indicating success or failure. + */ + +/*! + * ADV7180 I2C probe function. + * Function set in i2c_driver struct. + * Called by insmod. + * + * @param *adapter I2C adapter descriptor. + * + * @return Error code indicating success or failure. + */ +static int adv7180_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int rev_id; + int ret = 0; + struct mxc_tvin_platform_data *plat_data = client->dev.platform_data; + + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180_probe\n"); + + if (plat_data->dvddio_reg) { + dvddio_regulator = + regulator_get(&client->dev, plat_data->dvddio_reg); + if (!IS_ERR_VALUE((unsigned long)dvddio_regulator)) { + regulator_set_voltage(dvddio_regulator, 3300000); + if (regulator_enable(dvddio_regulator) != 0) + return -ENODEV; + } + } + + if (plat_data->dvdd_reg) { + dvdd_regulator = + regulator_get(&client->dev, plat_data->dvdd_reg); + if (!IS_ERR_VALUE((unsigned long)dvdd_regulator)) { + regulator_set_voltage(dvdd_regulator, 1800000); + if (regulator_enable(dvdd_regulator) != 0) + return -ENODEV; + } + } + + if (plat_data->avdd_reg) { + avdd_regulator = + regulator_get(&client->dev, plat_data->avdd_reg); + if (!IS_ERR_VALUE((unsigned long)avdd_regulator)) { + regulator_set_voltage(avdd_regulator, 1800000); + if (regulator_enable(avdd_regulator) != 0) + return -ENODEV; + } + } + + if (plat_data->pvdd_reg) { + pvdd_regulator = + regulator_get(&client->dev, plat_data->pvdd_reg); + if (!IS_ERR_VALUE((unsigned long)pvdd_regulator)) { + regulator_set_voltage(pvdd_regulator, 1800000); + if (regulator_enable(pvdd_regulator) != 0) + return -ENODEV; + } + } + + if (plat_data->reset) + plat_data->reset(); + + if (plat_data->pwdn) + plat_data->pwdn(1); + + msleep(1); + + /* Set initial values for the sensor struct. */ + memset(&adv7180_data, 0, sizeof(adv7180_data)); + adv7180_data.i2c_client = client; + adv7180_data.streamcap.timeperframe.denominator = 30; + adv7180_data.streamcap.timeperframe.numerator = 1; + adv7180_data.std_id = V4L2_STD_ALL; + video_idx = ADV7180_NOT_LOCKED; + adv7180_data.pix.width = video_fmts[video_idx].raw_width; + adv7180_data.pix.height = video_fmts[video_idx].raw_height; + adv7180_data.pix.pixelformat = V4L2_PIX_FMT_UYVY; /* YUV422 */ + adv7180_data.pix.priv = 1; /* 1 is used to indicate TV in */ + + gpio_sensor_active(); + + dev_dbg(&adv7180_data.i2c_client->dev, + "%s:adv7180 probe i2c address is 0x%02X \n", + __func__, adv7180_data.i2c_client->addr); + + /*! Read the revision ID of the tvin chip */ + rev_id = adv7180_read(ADV7180_IDENT); + dev_dbg(&adv7180_data.i2c_client->dev, + "%s:Analog Device adv7%2X0 detected! \n", __func__, + rev_id); + + /*! ADV7180 initialization. */ + adv7180_hard_reset(); + + pr_debug(" type is %d (expect %d)\n", + adv7180_int_device.type, v4l2_int_type_slave); + pr_debug(" num ioctls is %d\n", + adv7180_int_device.u.slave->num_ioctls); + + /* This function attaches this structure to the /dev/video0 device. + * The pointer in priv points to the mt9v111_data structure here.*/ + adv7180_int_device.priv = &adv7180_data; + ret = v4l2_int_device_register(&adv7180_int_device); + + return ret; +} + +/*! + * ADV7180 I2C detach function. + * Called on rmmod. + * + * @param *client struct i2c_client*. + * + * @return Error code indicating success or failure. + */ +static int adv7180_detach(struct i2c_client *client) +{ + struct mxc_tvin_platform_data *plat_data = client->dev.platform_data; + + dev_dbg(&adv7180_data.i2c_client->dev, + "%s:Removing %s video decoder @ 0x%02X from adapter %s \n", + __func__, IF_NAME, client->addr << 1, client->adapter->name); + + if (plat_data->pwdn) + plat_data->pwdn(0); + + if (dvddio_regulator) { + regulator_disable(dvddio_regulator); + regulator_put(dvddio_regulator, &client->dev); + } + + if (dvdd_regulator) { + regulator_disable(dvdd_regulator); + regulator_put(dvdd_regulator, &client->dev); + } + + if (avdd_regulator) { + regulator_disable(avdd_regulator); + regulator_put(avdd_regulator, &client->dev); + } + + if (pvdd_regulator) { + regulator_disable(pvdd_regulator); + regulator_put(pvdd_regulator, &client->dev); + } + + v4l2_int_device_unregister(&adv7180_int_device); + + return 0; +} + +/*! + * ADV7180 init function. + * Called on insmod. + * + * @return Error code indicating success or failure. + */ +static __init int adv7180_init(void) +{ + u8 err = 0; + + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180_init\n"); + + /* Tells the i2c driver what functions to call for this driver. */ + err = i2c_add_driver(&adv7180_i2c_driver); + if (err != 0) + pr_err("%s:driver registration failed, error=%d \n", + __func__, err); + + return err; +} + +/*! + * ADV7180 cleanup function. + * Called on rmmod. + * + * @return Error code indicating success or failure. + */ +static void __exit adv7180_clean(void) +{ + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180_clean\n"); + i2c_del_driver(&adv7180_i2c_driver); + gpio_sensor_inactive(); +} + +module_init(adv7180_init); +module_exit(adv7180_clean); + +MODULE_AUTHOR("Freescale Semiconductor"); +MODULE_DESCRIPTION("Anolog Device ADV7180 video decoder driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/media/video/mxc/capture/emma_mt9v111.c linux-2.6.26-lab126/drivers/media/video/mxc/capture/emma_mt9v111.c --- linux-2.6.26/drivers/media/video/mxc/capture/emma_mt9v111.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/emma_mt9v111.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,679 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mt9v111.c + * + * @brief mt9v111 camera driver functions + * + * @ingroup Camera + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_v4l2_capture.h" +#include "mt9v111.h" + +#ifdef MT9V111_DEBUG +static u16 testpattern; +#endif + +static sensor_interface *interface_param; +static mt9v111_conf mt9v111_device; +static int reset_frame_rate = 30; + +#define MT9V111_FRAME_RATE_NUM 20 + +static mt9v111_image_format format[2] = { + { + .index = 0, + .width = 640, + .height = 480, + }, + { + .index = 1, + .width = 352, + .height = 288, + }, +}; + +static int mt9v111_attach(struct i2c_adapter *adapter); +static int mt9v111_detach(struct i2c_client *client); + +static struct i2c_driver mt9v111_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "MT9V111 Client", + }, + .attach_adapter = mt9v111_attach, + .detach_client = mt9v111_detach, +}; + +static struct i2c_client mt9v111_i2c_client = { + .name = "mt9v111 I2C dev", + .addr = MT9V111_I2C_ADDRESS, + .driver = &mt9v111_i2c_driver, +}; + +/* + * Function definitions + */ + +#ifdef MT9V111_DEBUG +static inline int mt9v111_read_reg(u8 reg) +{ + int val = i2c_smbus_read_word_data(&mt9v111_i2c_client, reg); + if (val != -1) + val = cpu_to_be16(val); + return val; +} +#endif + +static inline int mt9v111_write_reg(u8 reg, u16 val) +{ + pr_debug("write reg %x val %x.\n", reg, val); + return i2c_smbus_write_word_data(&mt9v111_i2c_client, reg, + cpu_to_be16(val)); +} + +/*! + * Initialize mt9v111_sensor_lib + * Libarary for Sensor configuration through I2C + * + * @param coreReg Core Registers + * @param ifpReg IFP Register + * + * @return status + */ +static u8 mt9v111_sensor_lib(mt9v111_coreReg * coreReg, mt9v111_IFPReg * ifpReg) +{ + u8 reg; + u16 data; + u8 error = 0; + + /* + * setup to IFP registers + */ + reg = MT9V111I_ADDR_SPACE_SEL; + data = ifpReg->addrSpaceSel; + mt9v111_write_reg(reg, data); + + /* Operation Mode Control */ + reg = MT9V111I_MODE_CONTROL; + data = ifpReg->modeControl; + mt9v111_write_reg(reg, data); + + /* Output format */ + reg = MT9V111I_FORMAT_CONTROL; + data = ifpReg->formatControl; /* Set bit 12 */ + mt9v111_write_reg(reg, data); + + /* AE limit 4 */ + reg = MT9V111I_SHUTTER_WIDTH_LIMIT_AE; + data = ifpReg->gainLimitAE; + mt9v111_write_reg(reg, data); + + reg = MT9V111I_OUTPUT_FORMAT_CTRL2; + data = ifpReg->outputFormatCtrl2; + mt9v111_write_reg(reg, data); + + reg = MT9V111I_AE_SPEED; + data = ifpReg->AESpeed; + mt9v111_write_reg(reg, data); + + /* output image size */ + reg = MT9V111i_H_PAN; + data = 0x8000 | ifpReg->HPan; + mt9v111_write_reg(reg, data); + + reg = MT9V111i_H_ZOOM; + data = 0x8000 | ifpReg->HZoom; + mt9v111_write_reg(reg, data); + + reg = MT9V111i_H_SIZE; + data = 0x8000 | ifpReg->HSize; + mt9v111_write_reg(reg, data); + + reg = MT9V111i_V_PAN; + data = 0x8000 | ifpReg->VPan; + mt9v111_write_reg(reg, data); + + reg = MT9V111i_V_ZOOM; + data = 0x8000 | ifpReg->VZoom; + mt9v111_write_reg(reg, data); + + reg = MT9V111i_V_SIZE; + data = 0x8000 | ifpReg->VSize; + mt9v111_write_reg(reg, data); + + reg = MT9V111i_H_PAN; + data = ~0x8000 & ifpReg->HPan; + mt9v111_write_reg(reg, data); +#if 0 + reg = MT9V111I_UPPER_SHUTTER_DELAY_LIM; + data = ifpReg->upperShutterDelayLi; + mt9v111_write_reg(reg, data); + + reg = MT9V111I_SHUTTER_60; + data = ifpReg->shutter_width_60; + mt9v111_write_reg(reg, data); + + reg = MT9V111I_SEARCH_FLICK_60; + data = ifpReg->search_flicker_60; + mt9v111_write_reg(reg, data); +#endif + + /* + * setup to sensor core registers + */ + reg = MT9V111I_ADDR_SPACE_SEL; + data = coreReg->addressSelect; + mt9v111_write_reg(reg, data); + + /* enable changes and put the Sync bit on */ + reg = MT9V111S_OUTPUT_CTRL; + data = MT9V111S_OUTCTRL_SYNC | MT9V111S_OUTCTRL_CHIP_ENABLE | 0x3000; + mt9v111_write_reg(reg, data); + + /* min PIXCLK - Default */ + reg = MT9V111S_PIXEL_CLOCK_SPEED; + data = coreReg->pixelClockSpeed; + mt9v111_write_reg(reg, data); + + /* Setup image flipping / Dark rows / row/column skip */ + reg = MT9V111S_READ_MODE; + data = coreReg->readMode; + mt9v111_write_reg(reg, data); + + /*zoom 0 */ + reg = MT9V111S_DIGITAL_ZOOM; + data = coreReg->digitalZoom; + mt9v111_write_reg(reg, data); + + /* min H-blank */ + reg = MT9V111S_HOR_BLANKING; + data = coreReg->horizontalBlanking; + mt9v111_write_reg(reg, data); + + /* min V-blank */ + reg = MT9V111S_VER_BLANKING; + data = coreReg->verticalBlanking; + mt9v111_write_reg(reg, data); + + reg = MT9V111S_SHUTTER_WIDTH; + data = coreReg->shutterWidth; + mt9v111_write_reg(reg, data); + + reg = MT9V111S_SHUTTER_DELAY; + data = ifpReg->upperShutterDelayLi; + mt9v111_write_reg(reg, data); + + /* changes become effective */ + reg = MT9V111S_OUTPUT_CTRL; + data = MT9V111S_OUTCTRL_CHIP_ENABLE | 0x3000; + mt9v111_write_reg(reg, data); + + return error; +} + +/*! + * mt9v111 sensor interface Initialization + * @param param sensor_interface * + * @param width u32 + * @param height u32 + * @return None + */ +static void mt9v111_interface(sensor_interface *param, u32 width, u32 height) +{ + param->Vsync_pol = 0x0; + param->clk_mode = 0x0; /*gated */ + param->pixclk_pol = 0x0; + param->data_width = 0x1; + param->data_pol = 0x0; + param->ext_vsync = 0x0; + param->Vsync_pol = 0x0; + param->Hsync_pol = 0x0; + param->width = width - 1; + param->height = height - 1; + param->active_width = width; + param->active_height = height; + param->pixel_fmt = IPU_PIX_FMT_UYVY; + param->mclk = 27000000; +} + +/*! + * MT9V111 frame rate calculate + * + * @param frame_rate int * + * @param mclk int + * @return None + */ +static void mt9v111_rate_cal(int *frame_rate, int mclk) +{ + int num_clock_per_row; + int max_rate = 0; + + mt9v111_device.coreReg->horizontalBlanking = MT9V111_HORZBLANK_MIN; + + num_clock_per_row = (format[0].width + 114 + MT9V111_HORZBLANK_MIN) * 2; + max_rate = mclk / (num_clock_per_row * + (format[0].height + MT9V111_VERTBLANK_DEFAULT)); + + if ((*frame_rate > max_rate) || (*frame_rate == 0)) { + *frame_rate = max_rate; + } + + mt9v111_device.coreReg->verticalBlanking + = mclk / (*frame_rate * num_clock_per_row) - format[0].height; + + reset_frame_rate = *frame_rate; +} + +/*! + * MT9V111 sensor configuration + * + * @param frame_rate int * + * @param high_quality int + * @return sensor_interface * + */ +sensor_interface *mt9v111_config(int *frame_rate, int high_quality) +{ + u32 out_width, out_height; + + if (interface_param == NULL) + return NULL; + + mt9v111_device.coreReg->addressSelect = MT9V111I_SEL_SCA; + mt9v111_device.ifpReg->addrSpaceSel = MT9V111I_SEL_IFP; + + mt9v111_device.coreReg->windowHeight = MT9V111_WINHEIGHT; + mt9v111_device.coreReg->windowWidth = MT9V111_WINWIDTH; + mt9v111_device.coreReg->zoomColStart = 0; + mt9v111_device.coreReg->zomRowStart = 0; + mt9v111_device.coreReg->digitalZoom = 0x0; + + mt9v111_device.coreReg->verticalBlanking = MT9V111_VERTBLANK_DEFAULT; + mt9v111_device.coreReg->horizontalBlanking = MT9V111_HORZBLANK_MIN; + mt9v111_device.coreReg->pixelClockSpeed = 0; + mt9v111_device.coreReg->readMode = 0xd0a1; + + mt9v111_device.ifpReg->outputFormatCtrl2 = 0; + mt9v111_device.ifpReg->gainLimitAE = 0x300; + mt9v111_device.ifpReg->AESpeed = 0x80; + + /* here is the default value */ + mt9v111_device.ifpReg->formatControl = 0xc800; + mt9v111_device.ifpReg->modeControl = 0x708e; + mt9v111_device.ifpReg->awbSpeed = 0x4514; + mt9v111_device.coreReg->shutterWidth = 0xf8; + + out_width = 640; + out_height = 480; + + /*output size */ + mt9v111_device.ifpReg->HPan = 0; + mt9v111_device.ifpReg->HZoom = 640; + mt9v111_device.ifpReg->HSize = out_width; + mt9v111_device.ifpReg->VPan = 0; + mt9v111_device.ifpReg->VZoom = 480; + mt9v111_device.ifpReg->VSize = out_height; + + mt9v111_interface(interface_param, out_width, out_height); + set_mclk_rate(&interface_param->mclk); + mt9v111_rate_cal(frame_rate, interface_param->mclk); + mt9v111_sensor_lib(mt9v111_device.coreReg, mt9v111_device.ifpReg); + + return interface_param; +} + +/*! + * mt9v111 sensor set color configuration + * + * @param bright int + * @param saturation int + * @param red int + * @param green int + * @param blue int + * @return None + */ +static void +mt9v111_set_color(int bright, int saturation, int red, int green, int blue) +{ + u8 reg; + u16 data; + + switch (saturation) { + case 100: + mt9v111_device.ifpReg->awbSpeed = 0x4514; + break; + case 150: + mt9v111_device.ifpReg->awbSpeed = 0x6D14; + break; + case 75: + mt9v111_device.ifpReg->awbSpeed = 0x4D14; + break; + case 50: + mt9v111_device.ifpReg->awbSpeed = 0x5514; + break; + case 37: + mt9v111_device.ifpReg->awbSpeed = 0x5D14; + break; + case 25: + mt9v111_device.ifpReg->awbSpeed = 0x6514; + break; + default: + mt9v111_device.ifpReg->awbSpeed = 0x4514; + break; + } + + reg = MT9V111I_ADDR_SPACE_SEL; + data = mt9v111_device.ifpReg->addrSpaceSel; + mt9v111_write_reg(reg, data); + + /* Operation Mode Control */ + reg = MT9V111I_AWB_SPEED; + data = mt9v111_device.ifpReg->awbSpeed; + mt9v111_write_reg(reg, data); +} + +/*! + * mt9v111 sensor get color configuration + * + * @param bright int * + * @param saturation int * + * @param red int * + * @param green int * + * @param blue int * + * @return None + */ +static void +mt9v111_get_color(int *bright, int *saturation, int *red, int *green, int *blue) +{ + *saturation = (mt9v111_device.ifpReg->awbSpeed & 0x3800) >> 11; + switch (*saturation) { + case 0: + *saturation = 100; + break; + case 1: + *saturation = 75; + break; + case 2: + *saturation = 50; + break; + case 3: + *saturation = 37; + break; + case 4: + *saturation = 25; + break; + case 5: + *saturation = 150; + break; + case 6: + *saturation = 0; + break; + default: + *saturation = 0; + break; + } +} + +/*! + * mt9v111 sensor set AE measurement window mode configuration + * + * @param ae_mode int + * @return None + */ +static void mt9v111_set_ae_mode(int ae_mode) +{ + u8 reg; + u16 data; + + mt9v111_device.ifpReg->modeControl &= 0xfff3; + mt9v111_device.ifpReg->modeControl |= (ae_mode & 0x03) << 2; + + reg = MT9V111I_ADDR_SPACE_SEL; + data = mt9v111_device.ifpReg->addrSpaceSel; + mt9v111_write_reg(reg, data); + + reg = MT9V111I_MODE_CONTROL; + data = mt9v111_device.ifpReg->modeControl; + mt9v111_write_reg(reg, data); +} + +/*! + * mt9v111 sensor get AE measurement window mode configuration + * + * @param ae_mode int * + * @return None + */ +static void mt9v111_get_ae_mode(int *ae_mode) +{ + if (ae_mode != NULL) { + *ae_mode = (mt9v111_device.ifpReg->modeControl & 0xc) >> 2; + } +} + +/*! + * mt9v111 Reset function + * + * @return None + */ +static sensor_interface *mt9v111_reset(void) +{ + return mt9v111_config(&reset_frame_rate, 0); +} + +struct camera_sensor camera_sensor_if = { + .set_color = mt9v111_set_color, + .get_color = mt9v111_get_color, + .set_ae_mode = mt9v111_set_ae_mode, + .get_ae_mode = mt9v111_get_ae_mode, + .config = mt9v111_config, + .reset = mt9v111_reset, +}; + +#ifdef MT9V111_DEBUG +/*! + * Set sensor to test mode, which will generate test pattern. + * + * @return none + */ +static void mt9v111_test_pattern(bool flag) +{ + u16 data; + + /* switch to sensor registers */ + mt9v111_write_reg(MT9V111I_ADDR_SPACE_SEL, MT9V111I_SEL_SCA); + + if (flag == true) { + testpattern = MT9V111S_OUTCTRL_TEST_MODE; + + data = mt9v111_read_reg(MT9V111S_ROW_NOISE_CTRL) & 0xBF; + mt9v111_write_reg(MT9V111S_ROW_NOISE_CTRL, data); + + mt9v111_write_reg(MT9V111S_TEST_DATA, 0); + + /* changes take effect */ + data = MT9V111S_OUTCTRL_CHIP_ENABLE | testpattern | 0x3000; + mt9v111_write_reg(MT9V111S_OUTPUT_CTRL, data); + } else { + testpattern = 0; + + data = mt9v111_read_reg(MT9V111S_ROW_NOISE_CTRL) | 0x40; + mt9v111_write_reg(MT9V111S_ROW_NOISE_CTRL, data); + + /* changes take effect */ + data = MT9V111S_OUTCTRL_CHIP_ENABLE | testpattern | 0x3000; + mt9v111_write_reg(MT9V111S_OUTPUT_CTRL, data); + } +} +#endif + +/*! + * mt9v111 I2C detect_client function + * + * @param adapter struct i2c_adapter * + * @param address int + * @param kind int + * + * @return Error code indicating success or failure + */ +static int mt9v111_detect_client(struct i2c_adapter *adapter, int address, + int kind) +{ + mt9v111_i2c_client.adapter = adapter; + if (i2c_attach_client(&mt9v111_i2c_client)) { + mt9v111_i2c_client.adapter = NULL; + printk(KERN_ERR "mt9v111_attach: i2c_attach_client failed\n"); + return -1; + } + + interface_param = (sensor_interface *) + kmalloc(sizeof(sensor_interface), GFP_KERNEL); + if (!interface_param) { + printk(KERN_ERR "mt9v111_attach: kmalloc failed \n"); + return -1; + } + + printk(KERN_INFO "MT9V111 Detected\n"); + + return 0; +} + +static unsigned short normal_i2c[] = { MT9V111_I2C_ADDRESS, I2C_CLIENT_END }; + +/* Magic definition of all other variables and things */ +I2C_CLIENT_INSMOD; + +/*! + * mt9v111 I2C attach function + * + * @param adapter struct i2c_adapter * + * @return Error code indicating success or failure + */ +static int mt9v111_attach(struct i2c_adapter *adap) +{ + uint32_t mclk = 27000000; + struct clk *clk; + int err; + + clk = clk_get(NULL, "csi_clk"); + clk_enable(clk); + set_mclk_rate(&mclk); + + err = i2c_probe(adap, &addr_data, &mt9v111_detect_client); + + clk_disable(clk); + clk_put(clk); + + return err; +} + +/*! + * mt9v111 I2C detach function + * + * @param client struct i2c_client * + * @return Error code indicating success or failure + */ +static int mt9v111_detach(struct i2c_client *client) +{ + int err; + + if (!mt9v111_i2c_client.adapter) + return -1; + + err = i2c_detach_client(&mt9v111_i2c_client); + mt9v111_i2c_client.adapter = NULL; + + if (interface_param) + kfree(interface_param); + interface_param = NULL; + + return err; +} + +extern void gpio_sensor_active(void); + +/*! + * MT9V111 init function + * + * @return Error code indicating success or failure + */ +static __init int mt9v111_init(void) +{ + u8 err; + + gpio_sensor_active(); + + mt9v111_device.coreReg = (mt9v111_coreReg *) + kmalloc(sizeof(mt9v111_coreReg), GFP_KERNEL); + if (!mt9v111_device.coreReg) + return -1; + + memset(mt9v111_device.coreReg, 0, sizeof(mt9v111_coreReg)); + + mt9v111_device.ifpReg = (mt9v111_IFPReg *) + kmalloc(sizeof(mt9v111_IFPReg), GFP_KERNEL); + if (!mt9v111_device.ifpReg) { + kfree(mt9v111_device.coreReg); + mt9v111_device.coreReg = NULL; + return -1; + } + + memset(mt9v111_device.ifpReg, 0, sizeof(mt9v111_IFPReg)); + + err = i2c_add_driver(&mt9v111_i2c_driver); + + return err; +} + +extern void gpio_sensor_inactive(void); +/*! + * MT9V111 cleanup function + * + * @return Error code indicating success or failure + */ +static void __exit mt9v111_clean(void) +{ + if (mt9v111_device.coreReg) { + kfree(mt9v111_device.coreReg); + mt9v111_device.coreReg = NULL; + } + + if (mt9v111_device.ifpReg) { + kfree(mt9v111_device.ifpReg); + mt9v111_device.ifpReg = NULL; + } + + i2c_del_driver(&mt9v111_i2c_driver); + + gpio_sensor_inactive(); +} + +module_init(mt9v111_init); +module_exit(mt9v111_clean); + +/* Exported symbols for modules. */ +EXPORT_SYMBOL(camera_sensor_if); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Mt9v111 Camera Driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/media/video/mxc/capture/emma_ov2640.c linux-2.6.26-lab126/drivers/media/video/mxc/capture/emma_ov2640.c --- linux-2.6.26/drivers/media/video/mxc/capture/emma_ov2640.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/emma_ov2640.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,444 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mxc_v4l2_capture.h" + +enum ov2640_mode { + ov2640_mode_1600_1120, + ov2640_mode_800_600 +}; + +struct reg_value { + u8 reg; + u8 value; + int delay_ms; +}; + +static struct reg_value ov2640_setting_1600_1120[] = { + {0xff, 0x1, 0}, {0x12, 0x80, 1}, {0xff, 0, 0}, {0x2c, 0xff, 0}, + {0x2e, 0xdf, 0}, {0xff, 0x1, 0}, {0x3c, 0x32, 0}, {0x11, 0x01, 0}, + {0x09, 0x00, 0}, {0x04, 0x28, 0}, {0x13, 0xe5, 0}, {0x14, 0x48, 0}, + {0x2c, 0x0c, 0}, {0x33, 0x78, 0}, {0x3a, 0x33, 0}, {0x3b, 0xfb, 0}, + {0x3e, 0x00, 0}, {0x43, 0x11, 0}, {0x16, 0x10, 0}, {0x39, 0x82, 0}, + {0x35, 0x88, 0}, {0x22, 0x0a, 0}, {0x37, 0x40, 0}, {0x23, 0x00, 0}, + {0x34, 0xa0, 0}, {0x36, 0x1a, 0}, {0x06, 0x02, 0}, {0x07, 0xc0, 0}, + {0x0d, 0xb7, 0}, {0x0e, 0x01, 0}, {0x4c, 0x00, 0}, {0x4a, 0x81, 0}, + {0x21, 0x99, 0}, {0x24, 0x40, 0}, {0x25, 0x38, 0}, {0x26, 0x82, 0}, + {0x5c, 0x00, 0}, {0x63, 0x00, 0}, {0x46, 0x3f, 0}, {0x0c, 0x3c, 0}, + {0x5d, 0x55, 0}, {0x5e, 0x7d, 0}, {0x5f, 0x7d, 0}, {0x60, 0x55, 0}, + {0x61, 0x70, 0}, {0x62, 0x80, 0}, {0x7c, 0x05, 0}, {0x20, 0x80, 0}, + {0x28, 0x30, 0}, {0x6c, 0x00, 0}, {0x6d, 0x80, 0}, {0x6e, 00, 0}, + {0x70, 0x02, 0}, {0x71, 0x94, 0}, {0x73, 0xc1, 0}, {0x3d, 0x34, 0}, + {0x5a, 0x57, 0}, {0x4f, 0xbb, 0}, {0x50, 0x9c, 0}, {0xff, 0x00, 0}, + {0xe5, 0x7f, 0}, {0xf9, 0xc0, 0}, {0x41, 0x24, 0}, {0x44, 0x06, 0}, + {0xe0, 0x14, 0}, {0x76, 0xff, 0}, {0x33, 0xa0, 0}, {0x42, 0x20, 0}, + {0x43, 0x18, 0}, {0x4c, 0x00, 0}, {0x87, 0xd0, 0}, {0xd7, 0x03, 0}, + {0xd9, 0x10, 0}, {0xd3, 0x82, 0}, {0xc8, 0x08, 0}, {0xc9, 0x80, 0}, + {0x7c, 0x00, 0}, {0x7d, 0x00, 0}, {0x7c, 0x03, 0}, {0x7d, 0x48, 0}, + {0x7d, 0x48, 0}, {0x7c, 0x08, 0}, {0x7d, 0x20, 0}, {0x7d, 0x10, 0}, + {0x7d, 0x0e, 0}, {0x90, 0x00, 0}, {0x91, 0x0e, 0}, {0x91, 0x1a, 0}, + {0x91, 0x31, 0}, {0x91, 0x5a, 0}, {0x91, 0x69, 0}, {0x91, 0x75, 0}, + {0x91, 0x7e, 0}, {0x91, 0x88, 0}, {0x91, 0x8f, 0}, {0x91, 0x96, 0}, + {0x91, 0xa3, 0}, {0x91, 0xaf, 0}, {0x91, 0xc4, 0}, {0x91, 0xd7, 0}, + {0x91, 0xe8, 0}, {0x91, 0x20, 0}, {0x92, 0x00, 0}, {0x93, 0x06, 0}, + {0x93, 0xe3, 0}, {0x93, 0x03, 0}, {0x93, 0x03, 0}, {0x93, 0x00, 0}, + {0x93, 0x02, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, + {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, + {0x96, 0x00, 0}, {0x97, 0x08, 0}, {0x97, 0x19, 0}, {0x97, 0x02, 0}, + {0x97, 0x0c, 0}, {0x97, 0x24, 0}, {0x97, 0x30, 0}, {0x97, 0x28, 0}, + {0x97, 0x26, 0}, {0x97, 0x02, 0}, {0x97, 0x98, 0}, {0x97, 0x80, 0}, + {0x97, 0x00, 0}, {0x97, 0x00, 0}, {0xa4, 0x00, 0}, {0xa8, 0x00, 0}, + {0xc5, 0x11, 0}, {0xc6, 0x51, 0}, {0xbf, 0x80, 0}, {0xc7, 0x10, 0}, + {0xb6, 0x66, 0}, {0xb8, 0xa5, 0}, {0xb7, 0x64, 0}, {0xb9, 0x7c, 0}, + {0xb3, 0xaf, 0}, {0xb4, 0x97, 0}, {0xb5, 0xff, 0}, {0xb0, 0xc5, 0}, + {0xb1, 0x94, 0}, {0xb2, 0x0f, 0}, {0xc4, 0x5c, 0}, {0xa6, 0x00, 0}, + {0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x1b, 0}, {0xa7, 0x31, 0}, + {0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, + {0xa7, 0x19, 0}, {0xa7, 0x31, 0}, {0xa7, 0x00, 0}, {0xa7, 0x18, 0}, + {0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x19, 0}, {0xa7, 0x31, 0}, + {0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xc0, 0xc8, 0}, {0xc1, 0x96, 0}, + {0x86, 0x3d, 0}, {0x50, 0x00, 0}, {0x51, 0x90, 0}, {0x52, 0x18, 0}, + {0x53, 0x00, 0}, {0x54, 0x00, 0}, {0x55, 0x88, 0}, {0x57, 0x00, 0}, + {0x5a, 0x90, 0}, {0x5b, 0x18, 0}, {0x5c, 0x05, 0}, {0xc3, 0xef, 0}, + {0x7f, 0x00, 0}, {0xda, 0x01, 0}, {0xe5, 0x1f, 0}, {0xe1, 0x67, 0}, + {0xe0, 0x00, 0}, {0xdd, 0x7f, 0}, {0x05, 0x00, 0} +}; + +static struct reg_value ov2640_setting_800_600[] = { + {0xff, 0, 0}, {0xff, 1, 0}, {0x12, 0x80, 1}, {0xff, 00, 0}, + {0x2c, 0xff, 0}, {0x2e, 0xdf, 0}, {0xff, 0x1, 0}, {0x3c, 0x32, 0}, + {0x11, 0x01, 0}, {0x09, 0x00, 0}, {0x04, 0x28, 0}, {0x13, 0xe5, 0}, + {0x14, 0x48, 0}, {0x2c, 0x0c, 0}, {0x33, 0x78, 0}, {0x3a, 0x33, 0}, + {0x3b, 0xfb, 0}, {0x3e, 0x00, 0}, {0x43, 0x11, 0}, {0x16, 0x10, 0}, + {0x39, 0x92, 0}, {0x35, 0xda, 0}, {0x22, 0x1a, 0}, {0x37, 0xc3, 0}, + {0x23, 0x00, 0}, {0x34, 0xc0, 0}, {0x36, 0x1a, 0}, {0x06, 0x88, 0}, + {0x07, 0xc0, 0}, {0x0d, 0x87, 0}, {0x0e, 0x41, 0}, {0x4c, 0x00, 0}, + {0x4a, 0x81, 0}, {0x21, 0x99, 0}, {0x24, 0x40, 0}, {0x25, 0x38, 0}, + {0x26, 0x82, 0}, {0x5c, 0x00, 0}, {0x63, 0x00, 0}, {0x46, 0x22, 0}, + {0x0c, 0x3c, 0}, {0x5d, 0x55, 0}, {0x5e, 0x7d, 0}, {0x5f, 0x7d, 0}, + {0x60, 0x55, 0}, {0x61, 0x70, 0}, {0x62, 0x80, 0}, {0x7c, 0x05, 0}, + {0x20, 0x80, 0}, {0x28, 0x30, 0}, {0x6c, 0x00, 0}, {0x6d, 0x80, 0}, + {0x6e, 00, 0}, {0x70, 0x02, 0}, {0x71, 0x94, 0}, {0x73, 0xc1, 0}, + {0x12, 0x40, 0}, {0x17, 0x11, 0}, {0x18, 0x43, 0}, {0x19, 0x00, 0}, + {0x1a, 0x4b, 0}, {0x32, 0x09, 0}, {0x37, 0xc0, 0}, {0x4f, 0xca, 0}, + {0x50, 0xa8, 0}, {0x6d, 0x00, 0}, {0x3d, 0x38, 0}, {0xff, 0x00, 0}, + {0xe5, 0x7f, 0}, {0xf9, 0xc0, 0}, {0x41, 0x24, 0}, {0x44, 0x06, 0}, + {0xe0, 0x14, 0}, {0x76, 0xff, 0}, {0x33, 0xa0, 0}, {0x42, 0x20, 0}, + {0x43, 0x18, 0}, {0x4c, 0x00, 0}, {0x87, 0xd0, 0}, {0x88, 0x3f, 0}, + {0xd7, 0x03, 0}, {0xd9, 0x10, 0}, {0xd3, 0x82, 0}, {0xc8, 0x08, 0}, + {0xc9, 0x80, 0}, {0x7c, 0x00, 0}, {0x7d, 0x00, 0}, {0x7c, 0x03, 0}, + {0x7d, 0x48, 0}, {0x7d, 0x48, 0}, {0x7c, 0x08, 0}, {0x7d, 0x20, 0}, + {0x7d, 0x10, 0}, {0x7d, 0x0e, 0}, {0x90, 0x00, 0}, {0x91, 0x0e, 0}, + {0x91, 0x1a, 0}, {0x91, 0x31, 0}, {0x91, 0x5a, 0}, {0x91, 0x69, 0}, + {0x91, 0x75, 0}, {0x91, 0x7e, 0}, {0x91, 0x88, 0}, {0x91, 0x8f, 0}, + {0x91, 0x96, 0}, {0x91, 0xa3, 0}, {0x91, 0xaf, 0}, {0x91, 0xc4, 0}, + {0x91, 0xd7, 0}, {0x91, 0xe8, 0}, {0x91, 0x20, 0}, {0x92, 0x00, 0}, + {0x93, 0x06, 0}, {0x93, 0xe3, 0}, {0x93, 0x03, 0}, {0x93, 0x03, 0}, + {0x93, 0x00, 0}, {0x93, 0x02, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, + {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, + {0x93, 0x00, 0}, {0x96, 0x00, 0}, {0x97, 0x08, 0}, {0x97, 0x19, 0}, + {0x97, 0x02, 0}, {0x97, 0x0c, 0}, {0x97, 0x24, 0}, {0x97, 0x30, 0}, + {0x97, 0x28, 0}, {0x97, 0x26, 0}, {0x97, 0x02, 0}, {0x97, 0x98, 0}, + {0x97, 0x80, 0}, {0x97, 0x00, 0}, {0x97, 0x00, 0}, {0xa4, 0x00, 0}, + {0xa8, 0x00, 0}, {0xc5, 0x11, 0}, {0xc6, 0x51, 0}, {0xbf, 0x80, 0}, + {0xc7, 0x10, 0}, {0xb6, 0x66, 0}, {0xb8, 0xa5, 0}, {0xb7, 0x64, 0}, + {0xb9, 0x7c, 0}, {0xb3, 0xaf, 0}, {0xb4, 0x97, 0}, {0xb5, 0xff, 0}, + {0xb0, 0xc5, 0}, {0xb1, 0x94, 0}, {0xb2, 0x0f, 0}, {0xc4, 0x5c, 0}, + {0xa6, 0x00, 0}, {0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x1b, 0}, + {0xa7, 0x31, 0}, {0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xa7, 0x20, 0}, + {0xa7, 0xd8, 0}, {0xa7, 0x19, 0}, {0xa7, 0x31, 0}, {0xa7, 0x00, 0}, + {0xa7, 0x18, 0}, {0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x19, 0}, + {0xa7, 0x31, 0}, {0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xc0, 0x64, 0}, + {0xc1, 0x4b, 0}, {0x86, 0x1d, 0}, {0x50, 0x00, 0}, {0x51, 0xc8, 0}, + {0x52, 0x96, 0}, {0x53, 0x00, 0}, {0x54, 0x00, 0}, {0x55, 0x00, 0}, + {0x57, 0x00, 0}, {0x5a, 0xc8, 0}, {0x5b, 0x96, 0}, {0x5c, 0x00, 0}, + {0xc3, 0xef, 0}, {0x7f, 0x00, 0}, {0xda, 0x01, 0}, {0xe5, 0x1f, 0}, + {0xe1, 0x67, 0}, {0xe0, 0x00, 0}, {0xdd, 0x7f, 0}, {0x05, 0x00, 0} +}; + +static struct regulator *io_regulator; +static struct regulator *core_regulator; +static struct regulator *analog_regulator; +static struct regulator *gpo_regulator; +u32 mclk = 24000000; + +struct i2c_client *ov2640_i2c_client; + +static sensor_interface *interface_param; +static int reset_frame_rate = 30; +static int ov2640_probe(struct i2c_client *adapter, + const struct i2c_device_id *id); +static int ov2640_remove(struct i2c_client *client); + +static const struct i2c_device_id ov2640_id[] = { + {"ov2640", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, ov2640_id); + +static struct i2c_driver ov2640_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "ov2640", + }, + .probe = ov2640_probe, + .remove = ov2640_remove, + .id_table = ov2640_id, +}; + +/*! + * ov2640 I2C attach function + * + * @param adapter struct i2c_adapter * + * @return Error code indicating success or failure + */ +static int ov2640_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct mxc_camera_platform_data *plat_data = client->dev.platform_data; + + ov2640_i2c_client = client; + mclk = plat_data->mclk; + + io_regulator = regulator_get(&client->dev, plat_data->io_regulator); + core_regulator = regulator_get(&client->dev, plat_data->core_regulator); + analog_regulator = + regulator_get(&client->dev, plat_data->analog_regulator); + gpo_regulator = regulator_get(&client->dev, plat_data->gpo_regulator); + + interface_param = (sensor_interface *) + kmalloc(sizeof(sensor_interface), GFP_KERNEL); + if (!interface_param) { + dev_dbg(&ov2640_i2c_client->dev, + "ov2640_probe: kmalloc failed \n"); + return -1; + } + + return 0; +} + +/*! + * ov2640 I2C detach function + * + * @param client struct i2c_client * + * @return Error code indicating success or failure + */ +static int ov2640_remove(struct i2c_client *client) +{ + kfree(interface_param); + interface_param = NULL; + + if (!IS_ERR_VALUE((unsigned long)io_regulator)) { + regulator_disable(io_regulator); + regulator_put(io_regulator, NULL); + } + + if (!IS_ERR_VALUE((unsigned long)core_regulator)) { + regulator_disable(core_regulator); + regulator_put(core_regulator, NULL); + } + + if (!IS_ERR_VALUE((unsigned long)gpo_regulator)) { + regulator_disable(gpo_regulator); + regulator_put(gpo_regulator, NULL); + } + + if (!IS_ERR_VALUE((unsigned long)analog_regulator)) { + regulator_disable(analog_regulator); + regulator_put(analog_regulator, NULL); + } + + return 0; +} + +static int ov2640_write_reg(u8 reg, u8 val) +{ + if (i2c_smbus_write_byte_data(ov2640_i2c_client, reg, val) < 0) { + dev_dbg(&ov2640_i2c_client->dev, + "%s:write reg errorr:reg=%x,val=%x\n", __func__, reg, + val); + return -1; + } + return 0; +} + +static int ov2640_init_mode(enum ov2640_mode mode) +{ + struct reg_value *setting; + int i, num; + + switch (mode) { + case ov2640_mode_1600_1120: + setting = ov2640_setting_1600_1120; + num = ARRAY_SIZE(ov2640_setting_1600_1120); + break; + case ov2640_mode_800_600: + setting = ov2640_setting_800_600; + num = ARRAY_SIZE(ov2640_setting_800_600); + break; + default: + return 0; + } + + for (i = 0; i < num; i++) { + ov2640_write_reg(setting[i].reg, setting[i].value); + if (setting[i].delay_ms > 0) + msleep(setting[i].delay_ms); + } + + return 0; +} + +/*! + * ov2640 sensor interface Initialization + * @param param sensor_interface * + * @param width u32 + * @param height u32 + * @return None + */ +static void ov2640_interface(sensor_interface *param, u32 width, u32 height) +{ + param->Vsync_pol = 0x0; + param->clk_mode = 0x0; /*gated */ + param->pixclk_pol = 0x0; + param->data_width = 0x1; + param->data_pol = 0x0; + param->ext_vsync = 0x0; + param->Vsync_pol = 0x0; + param->Hsync_pol = 0x0; + param->width = width - 1; + param->height = height - 1; + param->active_width = width; + param->active_height = height; + param->pixel_fmt = IPU_PIX_FMT_UYVY; + param->mclk = mclk; +} + +static void ov2640_set_color(int bright, int saturation, int red, int green, + int blue) +{ + +} + +static void ov2640_get_color(int *bright, int *saturation, int *red, int *green, + int *blue) +{ + +} +static void ov2640_set_ae_mode(int ae_mode) +{ + +} +static void ov2640_get_ae_mode(int *ae_mode) +{ + +} + +extern void gpio_sensor_active(void); + +static sensor_interface *ov2640_config(int *frame_rate, int high_quality) +{ + + u32 out_width, out_height; + + /*set io votage */ + if (!IS_ERR_VALUE((unsigned long)io_regulator)) { + regulator_set_voltage(io_regulator, 2800000); + if (regulator_enable(io_regulator) != 0) { + dev_dbg(&ov2640_i2c_client->dev, + "%s:io set voltage error\n", __func__); + return NULL; + } else { + dev_dbg(&ov2640_i2c_client->dev, + "%s:io set voltage ok\n", __func__); + } + } + + /*core votage */ + if (!IS_ERR_VALUE((unsigned long)core_regulator)) { + regulator_set_voltage(core_regulator, 1300000); + if (regulator_enable(core_regulator) != 0) { + dev_dbg(&ov2640_i2c_client->dev, + "%s:core set voltage error\n", __func__); + return NULL; + } else { + dev_dbg(&ov2640_i2c_client->dev, + "%s:core set voltage ok\n", __func__); + } + } + + /*GPO 3 */ + if (!IS_ERR_VALUE((unsigned long)gpo_regulator)) { + if (regulator_enable(gpo_regulator) != 0) { + dev_dbg(&ov2640_i2c_client->dev, + "%s:gpo3 enable error\n", __func__); + return NULL; + } else { + dev_dbg(&ov2640_i2c_client->dev, "%s:gpo3 enable ok\n", + __func__); + } + } + + if (!IS_ERR_VALUE((unsigned long)analog_regulator)) { + regulator_set_voltage(analog_regulator, 2000000); + if (regulator_enable(analog_regulator) != 0) { + dev_dbg(&ov2640_i2c_client->dev, + "%s:analog set voltage error\n", __func__); + return NULL; + } else { + dev_dbg(&ov2640_i2c_client->dev, + "%s:analog set voltage ok\n", __func__); + } + } + + gpio_sensor_active(); + + if (high_quality) { + out_width = 1600; + out_height = 1120; + } else { + out_width = 800; + out_height = 600; + } + ov2640_interface(interface_param, out_width, out_height); + set_mclk_rate(&interface_param->mclk); + + if (high_quality) + ov2640_init_mode(ov2640_mode_1600_1120); + else + ov2640_init_mode(ov2640_mode_800_600); + + msleep(300); + + return interface_param; +} + +static sensor_interface *ov2640_reset(void) +{ + return ov2640_config(&reset_frame_rate, 0); +} + +struct camera_sensor camera_sensor_if = { + .set_color = ov2640_set_color, + .get_color = ov2640_get_color, + .set_ae_mode = ov2640_set_ae_mode, + .get_ae_mode = ov2640_get_ae_mode, + .config = ov2640_config, + .reset = ov2640_reset, +}; + +EXPORT_SYMBOL(camera_sensor_if); + +/*! + * ov2640 init function + * + * @return Error code indicating success or failure + */ +static __init int ov2640_init(void) +{ + u8 err; + + err = i2c_add_driver(&ov2640_i2c_driver); + + return err; +} + +extern void gpio_sensor_inactive(void); +/*! + * OV2640 cleanup function + * + * @return Error code indicating success or failure + */ +static void __exit ov2640_clean(void) +{ + i2c_del_driver(&ov2640_i2c_driver); + + gpio_sensor_inactive(); +} + +module_init(ov2640_init); +module_exit(ov2640_clean); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("OV2640 Camera Driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/media/video/mxc/capture/emma_v4l2_capture.c linux-2.6.26-lab126/drivers/media/video/mxc/capture/emma_v4l2_capture.c --- linux-2.6.26/drivers/media/video/mxc/capture/emma_v4l2_capture.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/emma_v4l2_capture.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,2075 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mx27_v4l2_capture.c + * + * @brief MX27 Video For Linux 2 driver + * + * @ingroup MXC_V4L2_CAPTURE + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mxc_v4l2_capture.h" +#include "mx27_prp.h" +#include "mx27_csi.h" + +static int csi_mclk_flag_backup; +static int video_nr = -1; +static cam_data *g_cam; + +/*! + * Free frame buffers + * + * @param cam Structure cam_data * + * + * @return status 0 success. + */ +static int mxc_free_frame_buf(cam_data *cam) +{ + int i; + + for (i = 0; i < FRAME_NUM; i++) { + if (cam->frame[i].vaddress != 0) { + dma_free_coherent(0, + cam->frame[i].buffer.length, + cam->frame[i].vaddress, + cam->frame[i].paddress); + cam->frame[i].vaddress = 0; + } + } + + return 0; +} + +/*! + * Allocate frame buffers + * + * @param cam Structure cam_data * + * + * @param count int number of buffer need to allocated + * + * @return status -0 Successfully allocated a buffer, -ENOBUFS failed. + */ +static int mxc_allocate_frame_buf(cam_data *cam, int count) +{ + int i; + + for (i = 0; i < count; i++) { + cam->frame[i].vaddress = + dma_alloc_coherent(0, + PAGE_ALIGN(cam->v2f. fmt.pix.sizeimage), + &cam->frame[i].paddress, + GFP_DMA | GFP_KERNEL); + if (cam->frame[i].vaddress == 0) { + pr_debug("mxc_allocate_frame_buf failed.\n"); + mxc_free_frame_buf(cam); + return -ENOBUFS; + } + cam->frame[i].buffer.index = i; + cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED; + cam->frame[i].buffer.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cam->frame[i].buffer.length = + PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage); + cam->frame[i].buffer.memory = V4L2_MEMORY_MMAP; + cam->frame[i].buffer.m.offset = cam->frame[i].paddress; + cam->frame[i].index = i; + } + + return 0; +} + +/*! + * Free frame buffers status + * + * @param cam Structure cam_data * + * + * @return none + */ +static void mxc_free_frames(cam_data *cam) +{ + int i; + + for (i = 0; i < FRAME_NUM; i++) { + cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED; + } + + cam->enc_counter = 0; + cam->skip_frame = 0; + INIT_LIST_HEAD(&cam->ready_q); + INIT_LIST_HEAD(&cam->working_q); + INIT_LIST_HEAD(&cam->done_q); +} + +/*! + * Return the buffer status + * + * @param cam Structure cam_data * + * @param buf Structure v4l2_buffer * + * + * @return status 0 success, EINVAL failed. + */ +static int mxc_v4l2_buffer_status(cam_data *cam, struct v4l2_buffer *buf) +{ + /* check range */ + if (buf->index < 0 || buf->index >= FRAME_NUM) { + pr_debug("mxc_v4l2_buffer_status buffers not allocated\n"); + return -EINVAL; + } + + memcpy(buf, &(cam->frame[buf->index].buffer), sizeof(*buf)); + return 0; +} + +/*! + * start the encoder job + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static int mxc_streamon(cam_data *cam) +{ + struct mxc_v4l_frame *frame; + int err = 0; + + if (!cam) + return -EIO; + + if (list_empty(&cam->ready_q)) { + printk(KERN_ERR "mxc_streamon buffer not been queued yet\n"); + return -EINVAL; + } + + cam->capture_pid = current->pid; + + if (cam->enc_enable) { + err = cam->enc_enable(cam); + if (err != 0) { + return err; + } + } + + cam->ping_pong_csi = 0; + if (cam->enc_update_eba) { + frame = + list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue); + list_del(cam->ready_q.next); + list_add_tail(&frame->queue, &cam->working_q); + err = cam->enc_update_eba(frame->paddress, &cam->ping_pong_csi); + + frame = + list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue); + list_del(cam->ready_q.next); + list_add_tail(&frame->queue, &cam->working_q); + err |= + cam->enc_update_eba(frame->paddress, &cam->ping_pong_csi); + } else { + return -EINVAL; + } + + return err; +} + +/*! + * Shut down the encoder job + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static int mxc_streamoff(cam_data *cam) +{ + int err = 0; + + if (!cam) + return -EIO; + + if (cam->enc_disable) { + err = cam->enc_disable(cam); + } + mxc_free_frames(cam); + return err; +} + +/*! + * Valid whether the palette is supported + * + * @param palette pixel format + * + * @return 0 if failed + */ +static inline int valid_mode(u32 palette) +{ + /* + * MX27 PrP channel 2 supports YUV444, but YUV444 is not + * defined by V4L2 :( + */ + return ((palette == V4L2_PIX_FMT_YUYV) || + (palette == V4L2_PIX_FMT_YUV420)); +} + +/*! + * Valid and adjust the overlay window size, position + * + * @param cam structure cam_data * + * @param win struct v4l2_window * + * + * @return 0 + */ +static int verify_preview(cam_data *cam, struct v4l2_window *win) +{ + if (cam->output >= num_registered_fb) { + pr_debug("verify_preview No matched.\n"); + return -1; + } + cam->overlay_fb = (struct fb_info *)registered_fb[cam->output]; + + /* TODO: suppose 16bpp, 4 bytes alignment */ + win->w.left &= ~0x1; + + if (win->w.width + win->w.left > cam->overlay_fb->var.xres) + win->w.width = cam->overlay_fb->var.xres - win->w.left; + if (win->w.height + win->w.top > cam->overlay_fb->var.yres) + win->w.height = cam->overlay_fb->var.yres - win->w.top; + + /* + * TODO: suppose 16bpp. Rounded down to a multiple of 2 pixels for + * width according to PrP limitations. + */ + if ((cam->rotation == V4L2_MXC_ROTATE_90_RIGHT) + || (cam->rotation == V4L2_MXC_ROTATE_90_RIGHT_VFLIP) + || (cam->rotation == V4L2_MXC_ROTATE_90_RIGHT_HFLIP) + || (cam->rotation == V4L2_MXC_ROTATE_90_LEFT)) + win->w.height &= ~0x1; + else + win->w.width &= ~0x1; + + return 0; +} + +/*! + * start the viewfinder job + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static int start_preview(cam_data *cam) +{ + int err = 0; + + err = prp_vf_select(cam); + if (err != 0) + return err; + + cam->overlay_pid = current->pid; + err = cam->vf_start_sdc(cam); + + return err; +} + +/*! + * shut down the viewfinder job + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static int stop_preview(cam_data *cam) +{ + int err = 0; + + err = prp_vf_deselect(cam); + return err; +} + +/*! + * V4L2 - mxc_v4l2_g_fmt function + * + * @param cam structure cam_data * + * + * @param f structure v4l2_format * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2_g_fmt(cam_data *cam, struct v4l2_format *f) +{ + int retval = 0; + + switch (f->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + f->fmt.pix.width = cam->v2f.fmt.pix.width; + f->fmt.pix.height = cam->v2f.fmt.pix.height; + f->fmt.pix.sizeimage = cam->v2f.fmt.pix.sizeimage; + f->fmt.pix.pixelformat = cam->v2f.fmt.pix.pixelformat; + f->fmt.pix.bytesperline = cam->v2f.fmt.pix.bytesperline; + f->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG; + retval = 0; + break; + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + f->fmt.win = cam->win; + break; + default: + retval = -EINVAL; + } + return retval; +} + +/*! + * V4L2 - mxc_v4l2_s_fmt function + * + * @param cam structure cam_data * + * + * @param f structure v4l2_format * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2_s_fmt(cam_data *cam, struct v4l2_format *f) +{ + int retval = 0; + int size = 0; + int bytesperline = 0; + + switch (f->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + if (!valid_mode(f->fmt.pix.pixelformat)) { + pr_debug("mxc_v4l2_s_fmt: format not supported\n"); + retval = -EINVAL; + } + + if (cam->rotation != V4L2_MXC_ROTATE_NONE) + pr_debug("mxc_v4l2_s_fmt: capture rotation ignored\n"); + + switch (f->fmt.pix.pixelformat) { + case V4L2_PIX_FMT_YUYV: + f->fmt.pix.width &= ~0x1; /* Multiple of 2 */ + size = f->fmt.pix.width * f->fmt.pix.height * 2; + bytesperline = f->fmt.pix.width * 2; + break; + case V4L2_PIX_FMT_YUV420: + f->fmt.pix.width &= ~0x7; /* Multiple of 8 */ + f->fmt.pix.height &= ~0x1; /* Multiple of 2 */ + size = f->fmt.pix.width * f->fmt.pix.height * 3 / 2; + bytesperline = f->fmt.pix.width * 3 / 2; + break; + default: + /* Suppose it's YUV444 or 32bpp */ + size = f->fmt.pix.width * f->fmt.pix.height * 4; + bytesperline = f->fmt.pix.width * 4; + pr_info("mxc_v4l2_s_fmt: default assume" + " to be YUV444 interleaved.\n"); + break; + } + + if (f->fmt.pix.bytesperline < bytesperline) { + f->fmt.pix.bytesperline = bytesperline; + } else { + bytesperline = f->fmt.pix.bytesperline; + } + + if (f->fmt.pix.sizeimage > size) { + pr_debug("mxc_v4l2_s_fmt: sizeimage bigger than" + " needed.\n"); + size = f->fmt.pix.sizeimage; + } + f->fmt.pix.sizeimage = size; + + cam->v2f.fmt.pix.sizeimage = size; + cam->v2f.fmt.pix.bytesperline = bytesperline; + cam->v2f.fmt.pix.width = f->fmt.pix.width; + cam->v2f.fmt.pix.height = f->fmt.pix.height; + cam->v2f.fmt.pix.pixelformat = f->fmt.pix.pixelformat; + retval = 0; + break; + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + retval = verify_preview(cam, &f->fmt.win); + cam->win = f->fmt.win; + break; + default: + retval = -EINVAL; + } + return retval; +} + +/*! + * get control param + * + * @param cam structure cam_data * + * + * @param c structure v4l2_control * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_get_v42l_control(cam_data *cam, struct v4l2_control *c) +{ + int status = 0; + + switch (c->id) { + case V4L2_CID_HFLIP: + c->value = cam->rotation; + break; + case V4L2_CID_VFLIP: + c->value = cam->rotation; + break; + case V4L2_CID_MXC_ROT: + c->value = cam->rotation; + break; + case V4L2_CID_BRIGHTNESS: + c->value = cam->bright; + break; + case V4L2_CID_HUE: + c->value = cam->hue; + break; + case V4L2_CID_CONTRAST: + c->value = cam->contrast; + break; + case V4L2_CID_SATURATION: + c->value = cam->saturation; + break; + case V4L2_CID_RED_BALANCE: + c->value = cam->red; + break; + case V4L2_CID_BLUE_BALANCE: + c->value = cam->blue; + break; + case V4L2_CID_BLACK_LEVEL: + c->value = cam->ae_mode; + break; + default: + status = -EINVAL; + } + return status; +} + +/*! + * V4L2 - set_control function + * V4L2_CID_MXC_ROT is the extention for rotation/mirroring. + * + * @param cam structure cam_data * + * + * @param c structure v4l2_control * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_set_v42l_control(cam_data *cam, struct v4l2_control *c) +{ + switch (c->id) { + case V4L2_CID_HFLIP: + if (c->value == 1) { + if ((cam->rotation != V4L2_MXC_ROTATE_VERT_FLIP) && + (cam->rotation != V4L2_MXC_ROTATE_180)) + cam->rotation = V4L2_MXC_ROTATE_HORIZ_FLIP; + else + cam->rotation = V4L2_MXC_ROTATE_180; + } else { + if (cam->rotation == V4L2_MXC_ROTATE_HORIZ_FLIP) + cam->rotation = V4L2_MXC_ROTATE_NONE; + else if (cam->rotation == V4L2_MXC_ROTATE_180) + cam->rotation = V4L2_MXC_ROTATE_VERT_FLIP; + } + break; + case V4L2_CID_VFLIP: + if (c->value == 1) { + if ((cam->rotation != V4L2_MXC_ROTATE_HORIZ_FLIP) && + (cam->rotation != V4L2_MXC_ROTATE_180)) + cam->rotation = V4L2_MXC_ROTATE_VERT_FLIP; + else + cam->rotation = V4L2_MXC_ROTATE_180; + } else { + if (cam->rotation == V4L2_MXC_ROTATE_VERT_FLIP) + cam->rotation = V4L2_MXC_ROTATE_NONE; + if (cam->rotation == V4L2_MXC_ROTATE_180) + cam->rotation = V4L2_MXC_ROTATE_HORIZ_FLIP; + } + break; + case V4L2_CID_MXC_ROT: + switch (c->value) { + case V4L2_MXC_ROTATE_NONE: + case V4L2_MXC_ROTATE_VERT_FLIP: + case V4L2_MXC_ROTATE_HORIZ_FLIP: + case V4L2_MXC_ROTATE_180: + case V4L2_MXC_ROTATE_90_RIGHT: + case V4L2_MXC_ROTATE_90_RIGHT_VFLIP: + case V4L2_MXC_ROTATE_90_RIGHT_HFLIP: + case V4L2_MXC_ROTATE_90_LEFT: + cam->rotation = c->value; + break; + default: + return -EINVAL; + } + break; + case V4L2_CID_HUE: + cam->hue = c->value; + break; + case V4L2_CID_CONTRAST: + cam->contrast = c->value; + break; + case V4L2_CID_BRIGHTNESS: + cam->bright = c->value; + case V4L2_CID_SATURATION: + cam->saturation = c->value; + case V4L2_CID_RED_BALANCE: + cam->red = c->value; + case V4L2_CID_BLUE_BALANCE: + cam->blue = c->value; + csi_enable_mclk(CSI_MCLK_I2C, true, true); + cam->cam_sensor->set_color(cam->bright, cam->saturation, + cam->red, cam->green, cam->blue); + csi_enable_mclk(CSI_MCLK_I2C, false, false); + break; + case V4L2_CID_BLACK_LEVEL: + cam->ae_mode = c->value & 0x03; + csi_enable_mclk(CSI_MCLK_I2C, true, true); + if (cam->cam_sensor->set_ae_mode) + cam->cam_sensor->set_ae_mode(cam->ae_mode); + csi_enable_mclk(CSI_MCLK_I2C, false, false); + break; + case V4L2_CID_MXC_FLASH: + break; + default: + return -EINVAL; + } + return 0; +} + +/*! + * V4L2 - mxc_v4l2_s_param function + * + * @param cam structure cam_data * + * + * @param parm structure v4l2_streamparm * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm) +{ + sensor_interface *param; + csi_signal_cfg_t csi_param; + + if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + pr_debug("mxc_v4l2_s_param invalid type\n"); + return -EINVAL; + } + + if (parm->parm.capture.timeperframe.denominator > + cam->standard.frameperiod.denominator) { + pr_debug("mxc_v4l2_s_param frame rate %d larger " + "than standard supported %d\n", + parm->parm.capture.timeperframe.denominator, + cam->standard.frameperiod.denominator); + return -EINVAL; + } + + cam->streamparm.parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + + csi_enable_mclk(CSI_MCLK_I2C, true, true); + param = cam->cam_sensor->config + (&parm->parm.capture.timeperframe.denominator, + parm->parm.capture.capturemode); + csi_enable_mclk(CSI_MCLK_I2C, false, false); + + cam->streamparm.parm.capture.timeperframe = + parm->parm.capture.timeperframe; + + if ((parm->parm.capture.capturemode != 0) && + (parm->parm.capture.capturemode != V4L2_MODE_HIGHQUALITY)) { + pr_debug("mxc_v4l2_s_param frame un-supported capture mode\n"); + return -EINVAL; + } + + if (parm->parm.capture.capturemode == + cam->streamparm.parm.capture.capturemode) { + return 0; + } + + /* resolution changed, so need to re-program the CSI */ + csi_param.sens_clksrc = 0; + csi_param.clk_mode = param->clk_mode; + csi_param.pixclk_pol = param->pixclk_pol; + csi_param.data_width = param->data_width; + csi_param.data_pol = param->data_pol; + csi_param.ext_vsync = param->ext_vsync; + csi_param.Vsync_pol = param->Vsync_pol; + csi_param.Hsync_pol = param->Hsync_pol; + csi_init_interface(param->width, param->height, param->pixel_fmt, + csi_param); + + if (parm->parm.capture.capturemode != V4L2_MODE_HIGHQUALITY) { + cam->streamparm.parm.capture.capturemode = 0; + } else { + cam->streamparm.parm.capture.capturemode = + V4L2_MODE_HIGHQUALITY; + cam->streamparm.parm.capture.extendedmode = + parm->parm.capture.extendedmode; + cam->streamparm.parm.capture.readbuffers = 1; + } + return 0; +} + +/*! + * Dequeue one V4L capture buffer + * + * @param cam structure cam_data * + * @param buf structure v4l2_buffer * + * + * @return status 0 success, EINVAL invalid frame number, + * ETIME timeout, ERESTARTSYS interrupted by user + */ +static int mxc_v4l_dqueue(cam_data *cam, struct v4l2_buffer *buf) +{ + int retval = 0; + struct mxc_v4l_frame *frame; + + if (!wait_event_interruptible_timeout(cam->enc_queue, + cam->enc_counter != 0, 10 * HZ)) { + printk(KERN_ERR "mxc_v4l_dqueue timeout enc_counter %x\n", + cam->enc_counter); + return -ETIME; + } else if (signal_pending(current)) { + printk(KERN_ERR "mxc_v4l_dqueue() interrupt received\n"); + return -ERESTARTSYS; + } + + cam->enc_counter--; + + frame = list_entry(cam->done_q.next, struct mxc_v4l_frame, queue); + list_del(cam->done_q.next); + if (frame->buffer.flags & V4L2_BUF_FLAG_DONE) { + frame->buffer.flags &= ~V4L2_BUF_FLAG_DONE; + } else if (frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) { + printk(KERN_ERR "VIDIOC_DQBUF: Buffer not filled.\n"); + frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED; + retval = -EINVAL; + } else if ((frame->buffer.flags & 0x7) == V4L2_BUF_FLAG_MAPPED) { + printk(KERN_ERR "VIDIOC_DQBUF: Buffer not queued.\n"); + retval = -EINVAL; + } + + buf->bytesused = cam->v2f.fmt.pix.sizeimage; + buf->index = frame->index; + buf->flags = frame->buffer.flags; + + return retval; +} + +/*! + * V4L interface - open function + * + * @param inode structure inode * + * @param file structure file * + * + * @return status 0 success, ENODEV invalid device instance, + * ENODEV timeout, ERESTARTSYS interrupted by user + */ +static int mxc_v4l_open(struct inode *inode, struct file *file) +{ + sensor_interface *param; + csi_signal_cfg_t csi_param; + struct video_device *dev = video_devdata(file); + cam_data *cam = dev->priv; + int err = 0; + + if (!cam) { + pr_info("Internal error, cam_data not found!\n"); + return -ENODEV; + } + + if (down_interruptible(&cam->busy_lock)) + return -EINTR; + + if (signal_pending(current)) + goto oops; + + if (cam->open_count++ == 0) { + wait_event_interruptible(cam->power_queue, + cam->low_power == false); + + err = prp_enc_select(cam); + + cam->enc_counter = 0; + cam->skip_frame = 0; + INIT_LIST_HEAD(&cam->ready_q); + INIT_LIST_HEAD(&cam->working_q); + INIT_LIST_HEAD(&cam->done_q); + + csi_enable_mclk(CSI_MCLK_I2C, true, true); + param = cam->cam_sensor->reset(); + if (param == NULL) { + cam->open_count--; + csi_enable_mclk(CSI_MCLK_I2C, false, false); + err = -ENODEV; + goto oops; + } + csi_param.sens_clksrc = 0; + csi_param.clk_mode = param->clk_mode; + csi_param.pixclk_pol = param->pixclk_pol; + csi_param.data_width = param->data_width; + csi_param.data_pol = param->data_pol; + csi_param.ext_vsync = param->ext_vsync; + csi_param.Vsync_pol = param->Vsync_pol; + csi_param.Hsync_pol = param->Hsync_pol; + csi_init_interface(param->width, param->height, + param->pixel_fmt, csi_param); + cam->cam_sensor->get_color(&cam->bright, &cam->saturation, + &cam->red, &cam->green, &cam->blue); + if (cam->cam_sensor->get_ae_mode) + cam->cam_sensor->get_ae_mode(&cam->ae_mode); + csi_enable_mclk(CSI_MCLK_I2C, false, false); + prp_init(cam); + + } + + file->private_data = dev; + oops: + up(&cam->busy_lock); + return err; +} + +/*! + * V4L interface - close function + * + * @param inode struct inode * + * @param file struct file * + * + * @return 0 success + */ +static int mxc_v4l_close(struct inode *inode, struct file *file) +{ + struct video_device *dev = video_devdata(file); + int err = 0; + cam_data *cam = dev->priv; + + /* for the case somebody hit the ctrl C */ + if (cam->overlay_pid == current->pid) { + err = stop_preview(cam); + cam->overlay_on = false; + } + if (cam->capture_pid == current->pid) { + err |= mxc_streamoff(cam); + cam->capture_on = false; + wake_up_interruptible(&cam->enc_queue); + } + + if (--cam->open_count == 0) { + wait_event_interruptible(cam->power_queue, + cam->low_power == false); + pr_debug("mxc_v4l_close: release resource\n"); + + err |= prp_enc_deselect(cam); + + mxc_free_frame_buf(cam); + file->private_data = NULL; + + /* capture off */ + wake_up_interruptible(&cam->enc_queue); + mxc_free_frames(cam); + cam->enc_counter++; + prp_exit(cam); + } + + return err; +} + +#ifdef CONFIG_VIDEO_MXC_CSI_DMA +#include + +#define CSI_DMA_STATUS_IDLE 0 /* DMA is not started */ +#define CSI_DMA_STATUS_WORKING 1 /* DMA is transfering the data */ +#define CSI_DMA_STATUS_DONE 2 /* One frame completes successfully */ +#define CSI_DMA_STATUS_ERROR 3 /* Error occurs during the DMA */ + +/* + * Sometimes the start of the DMA is not synchronized with the CSI + * SOF (Start of Frame) interrupt which will lead to incorrect + * captured image. In this case the driver will re-try capturing + * another frame. The following macro defines the maximum re-try + * times. + */ +#define CSI_DMA_RETRY 8 + +/* + * Size of the physical contiguous memory area used to hold image data + * transfered by DMA. It can be less than the size of the image data. + */ +#define CSI_MEM_SIZE (1024 * 600) + +/* Number of bytes for one DMA transfer */ +#define CSI_DMA_LENGTH (1024 * 200) + +static int g_dma_channel; +static int g_dma_status = CSI_DMA_STATUS_DONE; +static volatile int g_dma_completed; /* number of completed DMA transfers */ +static volatile int g_dma_copied; /* number of copied DMA transfers */ +static struct tasklet_struct g_dma_tasklet; +static char *g_user_buf; /* represents the buf passed by read() */ +static int g_user_count; /* represents the count passed by read() */ + +/*! + * @brief setup the DMA to transfer data + * There may be more than one DMA to transfer the whole image. Those + * DMAs work like chain. This function is used to setup the DMA in + * case there is enough space to hold the data. + * @param data pointer to the cam structure + */ +static void mxc_csi_dma_chaining(void *data) +{ + cam_data *cam = (cam_data *) data; + int count, chained = 0; + int max_dma = CSI_MEM_SIZE / CSI_DMA_LENGTH; + mxc_dma_requestbuf_t dma_request; + + while (chained * CSI_DMA_LENGTH < g_user_count) { + /* + * Calculate how many bytes the DMA should transfer. It may + * be less than CSI_DMA_LENGTH if the DMA is the last one. + */ + if ((chained + 1) * CSI_DMA_LENGTH > g_user_count) + count = g_user_count - chained * CSI_DMA_LENGTH; + else + count = CSI_DMA_LENGTH; + pr_debug("%s() DMA chained count = %d\n", __FUNCTION__, count); + + /* Config DMA */ + memset(&dma_request, 0, sizeof(mxc_dma_requestbuf_t)); + dma_request.dst_addr = cam->still_buf + + (chained % max_dma) * CSI_DMA_LENGTH; + dma_request.src_addr = (dma_addr_t) CSI_CSIRXFIFO_PHYADDR; + dma_request.num_of_bytes = count; + mxc_dma_config(g_dma_channel, &dma_request, 1, + MXC_DMA_MODE_READ); + + chained++; + } +} + +/*! + * @brief Copy image data from physical contiguous memory to user space buffer + * Once the data are copied, there will be more spare space in the + * physical contiguous memory to receive data from DMA. + * @param data pointer to the cam structure + */ +static void mxc_csi_dma_task(unsigned long data) +{ + cam_data *cam = (cam_data *) data; + int count; + int max_dma = CSI_MEM_SIZE / CSI_DMA_LENGTH; + + while (g_dma_copied < g_dma_completed) { + /* + * Calculate how many bytes the DMA has transfered. It may + * be less than CSI_DMA_LENGTH if the DMA is the last one. + */ + if ((g_dma_copied + 1) * CSI_DMA_LENGTH > g_user_count) + count = g_user_count - g_dma_copied * CSI_DMA_LENGTH; + else + count = CSI_DMA_LENGTH; + if (copy_to_user(g_user_buf + g_dma_copied * CSI_DMA_LENGTH, + cam->still_buf_vaddr + (g_dma_copied % max_dma) + * CSI_DMA_LENGTH, count)) + pr_debug("Warning: some bytes not copied\n"); + + g_dma_copied++; + } + + /* If the whole image has been captured */ + if (g_dma_copied * CSI_DMA_LENGTH >= g_user_count) { + cam->still_counter++; + wake_up_interruptible(&cam->still_queue); + } + + pr_debug("%s() DMA completed = %d copied = %d\n", + __FUNCTION__, g_dma_completed, g_dma_copied); +} + +/*! + * @brief DMA interrupt callback function + * @param data pointer to the cam structure + * @param error DMA error flag + * @param count number of bytes transfered by the DMA + */ +static void mxc_csi_dma_callback(void *data, int error, unsigned int count) +{ + cam_data *cam = (cam_data *) data; + int max_dma = CSI_MEM_SIZE / CSI_DMA_LENGTH; + unsigned long lock_flags; + + spin_lock_irqsave(&cam->int_lock, lock_flags); + + g_dma_completed++; + + if (error != MXC_DMA_DONE) { + g_dma_status = CSI_DMA_STATUS_ERROR; + pr_debug("%s() DMA error\n", __FUNCTION__); + } + + /* If the whole image has been captured */ + if ((g_dma_status != CSI_DMA_STATUS_ERROR) + && (g_dma_completed * CSI_DMA_LENGTH >= g_user_count)) + g_dma_status = CSI_DMA_STATUS_DONE; + + if ((g_dma_status == CSI_DMA_STATUS_WORKING) && + (g_dma_completed >= g_dma_copied + max_dma)) { + g_dma_status = CSI_DMA_STATUS_ERROR; + pr_debug("%s() Previous buffer over written\n", __FUNCTION__); + } + + /* Schedule the tasklet */ + tasklet_schedule(&g_dma_tasklet); + + spin_unlock_irqrestore(&cam->int_lock, lock_flags); + + pr_debug("%s() count = %d bytes\n", __FUNCTION__, count); +} + +/*! + * @brief CSI interrupt callback function + * @param data pointer to the cam structure + * @param status CSI interrupt status + */ +static void mxc_csi_irq_callback(void *data, unsigned long status) +{ + cam_data *cam = (cam_data *) data; + unsigned long lock_flags; + + spin_lock_irqsave(&cam->int_lock, lock_flags); + + /* Wait for SOF (Start of Frame) interrupt to sync the image */ + if (status & BIT_SOF_INT) { + if (g_dma_status == CSI_DMA_STATUS_IDLE) { + /* Start DMA transfer to capture image */ + mxc_dma_enable(g_dma_channel); + g_dma_status = CSI_DMA_STATUS_WORKING; + pr_debug("%s() DMA started.\n", __FUNCTION__); + } else if (g_dma_status == CSI_DMA_STATUS_WORKING) { + /* + * Another SOF occurs during DMA transfer. In this + * case the image is not synchronized so need to + * report error and probably try again. + */ + g_dma_status = CSI_DMA_STATUS_ERROR; + pr_debug("%s() Image is not synchronized with DMA - " + "SOF before DMA completes\n", __FUNCTION__); + } + } + + spin_unlock_irqrestore(&cam->int_lock, lock_flags); + + pr_debug("%s() g_dma_status = %d\n", __FUNCTION__, g_dma_status); +} + +/*! + * V4L interface - read function + * + * @param file struct file * + * @param read buf char * + * @param count size_t + * @param ppos structure loff_t * + * + * @return bytes read + */ +static ssize_t +mxc_v4l_read(struct file *file, char *buf, size_t count, loff_t *ppos) +{ + int err = 0; + struct video_device *dev = video_devdata(file); + cam_data *cam = dev->priv; + int retry = CSI_DMA_RETRY; + + g_user_buf = buf; + + if (down_interruptible(&cam->busy_lock)) + return -EINTR; + + /* Video capture and still image capture are exclusive */ + if (cam->capture_on == true) { + err = -EBUSY; + goto exit0; + } + + /* The CSI-DMA can not do CSC */ + if (cam->v2f.fmt.pix.pixelformat != V4L2_PIX_FMT_YUYV) { + pr_info("mxc_v4l_read support YUYV pixel format only\n"); + err = -EINVAL; + goto exit0; + } + + /* The CSI-DMA can not do resize or crop */ + if ((cam->v2f.fmt.pix.width != cam->crop_bounds.width) + || (cam->v2f.fmt.pix.height != cam->crop_bounds.height)) { + pr_info("mxc_v4l_read resize is not supported\n"); + pr_info("supported image size width = %d height = %d\n", + cam->crop_bounds.width, cam->crop_bounds.height); + err = -EINVAL; + goto exit0; + } + if ((cam->crop_current.left != cam->crop_bounds.left) + || (cam->crop_current.width != cam->crop_bounds.width) + || (cam->crop_current.top != cam->crop_bounds.top) + || (cam->crop_current.height != cam->crop_bounds.height)) { + pr_info("mxc_v4l_read cropping is not supported\n"); + err = -EINVAL; + goto exit0; + } + + cam->still_buf_vaddr = dma_alloc_coherent(0, + PAGE_ALIGN(CSI_MEM_SIZE), + &cam->still_buf, + GFP_DMA | GFP_KERNEL); + + if (!cam->still_buf_vaddr) { + pr_info("mxc_v4l_read failed at allocate still_buf\n"); + err = -ENOBUFS; + goto exit0; + } + + /* Initialize DMA */ + g_dma_channel = mxc_dma_request(MXC_DMA_CSI_RX, "CSI RX DMA"); + if (g_dma_channel < 0) { + pr_debug("mxc_v4l_read failed to request DMA channel\n"); + err = -EIO; + goto exit1; + } + + err = mxc_dma_callback_set(g_dma_channel, + (mxc_dma_callback_t) mxc_csi_dma_callback, + (void *)cam); + if (err != 0) { + pr_debug("mxc_v4l_read failed to set DMA callback\n"); + err = -EIO; + goto exit2; + } + + g_user_buf = buf; + if (cam->v2f.fmt.pix.sizeimage < count) + g_user_count = cam->v2f.fmt.pix.sizeimage; + else + g_user_count = count & ~0x3; + + tasklet_init(&g_dma_tasklet, mxc_csi_dma_task, (unsigned long)cam); + g_dma_status = CSI_DMA_STATUS_DONE; + csi_set_callback(mxc_csi_irq_callback, cam); + csi_enable_prpif(0); + + /* clear current SOF first */ + csi_clear_status(BIT_SOF_INT); + csi_enable_mclk(CSI_MCLK_RAW, true, true); + + do { + g_dma_completed = g_dma_copied = 0; + mxc_csi_dma_chaining(cam); + cam->still_counter = 0; + g_dma_status = CSI_DMA_STATUS_IDLE; + + if (!wait_event_interruptible_timeout(cam->still_queue, + cam->still_counter != 0, + 10 * HZ)) { + pr_info("mxc_v4l_read timeout counter %x\n", + cam->still_counter); + err = -ETIME; + goto exit3; + } + + if (g_dma_status == CSI_DMA_STATUS_DONE) + break; + + if (retry-- == 0) + break; + + pr_debug("Now retry image capture\n"); + } while (1); + + if (g_dma_status != CSI_DMA_STATUS_DONE) + err = -EIO; + + exit3: + csi_enable_prpif(1); + g_dma_status = CSI_DMA_STATUS_DONE; + csi_set_callback(0, 0); + csi_enable_mclk(CSI_MCLK_RAW, false, false); + tasklet_kill(&g_dma_tasklet); + + exit2: + mxc_dma_free(g_dma_channel); + + exit1: + dma_free_coherent(0, PAGE_ALIGN(CSI_MEM_SIZE), + cam->still_buf_vaddr, cam->still_buf); + cam->still_buf = 0; + + exit0: + up(&cam->busy_lock); + if (err < 0) + return err; + else + return g_user_count; +} +#else +/*! + * V4L interface - read function + * + * @param file struct file * + * @param read buf char * + * @param count size_t + * @param ppos structure loff_t * + * + * @return bytes read + */ +static ssize_t +mxc_v4l_read(struct file *file, char *buf, size_t count, loff_t *ppos) +{ + int err = 0; + u8 *v_address; + struct video_device *dev = video_devdata(file); + cam_data *cam = dev->priv; + + if (down_interruptible(&cam->busy_lock)) + return -EINTR; + + /* Video capture and still image capture are exclusive */ + if (cam->capture_on == true) { + err = -EBUSY; + goto exit0; + } + + v_address = dma_alloc_coherent(0, + PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage), + &cam->still_buf, GFP_DMA | GFP_KERNEL); + + if (!v_address) { + pr_info("mxc_v4l_read failed at allocate still_buf\n"); + err = -ENOBUFS; + goto exit0; + } + + if (prp_still_select(cam)) { + err = -EIO; + goto exit1; + } + + cam->still_counter = 0; + if (cam->csi_start(cam)) { + err = -EIO; + goto exit2; + } + + if (!wait_event_interruptible_timeout(cam->still_queue, + cam->still_counter != 0, + 10 * HZ)) { + pr_info("mxc_v4l_read timeout counter %x\n", + cam->still_counter); + err = -ETIME; + goto exit2; + } + err = copy_to_user(buf, v_address, cam->v2f.fmt.pix.sizeimage); + + exit2: + prp_still_deselect(cam); + + exit1: + dma_free_coherent(0, cam->v2f.fmt.pix.sizeimage, v_address, + cam->still_buf); + cam->still_buf = 0; + + exit0: + up(&cam->busy_lock); + if (err < 0) + return err; + else + return (cam->v2f.fmt.pix.sizeimage - err); +} +#endif /* CONFIG_VIDEO_MXC_CSI_DMA */ + +/*! + * V4L interface - ioctl function + * + * @param inode struct inode * + * + * @param file struct file * + * + * @param ioctlnr unsigned int + * + * @param arg void * + * + * @return 0 success, ENODEV for invalid device instance, + * -1 for other errors. + */ +static int +mxc_v4l_do_ioctl(struct inode *inode, struct file *file, + unsigned int ioctlnr, void *arg) +{ + struct video_device *dev = video_devdata(file); + cam_data *cam = dev->priv; + int retval = 0; + unsigned long lock_flags; + + if (!cam) + return -EBADF; + + wait_event_interruptible(cam->power_queue, cam->low_power == false); + /* make this _really_ smp-safe */ + if (down_interruptible(&cam->busy_lock)) + return -EBUSY; + + switch (ioctlnr) { + /*! + * V4l2 VIDIOC_QUERYCAP ioctl + */ + case VIDIOC_QUERYCAP:{ + struct v4l2_capability *cap = arg; + strcpy(cap->driver, "mxc_v4l2"); + cap->version = KERNEL_VERSION(0, 1, 11); + cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | + V4L2_CAP_VIDEO_OVERLAY | V4L2_CAP_STREAMING + | V4L2_CAP_READWRITE; + cap->card[0] = '\0'; + cap->bus_info[0] = '\0'; + retval = 0; + break; + } + + /*! + * V4l2 VIDIOC_G_FMT ioctl + */ + case VIDIOC_G_FMT:{ + struct v4l2_format *gf = arg; + retval = mxc_v4l2_g_fmt(cam, gf); + break; + } + + /*! + * V4l2 VIDIOC_S_FMT ioctl + */ + case VIDIOC_S_FMT:{ + struct v4l2_format *sf = arg; + retval = mxc_v4l2_s_fmt(cam, sf); + break; + } + + /*! + * V4l2 VIDIOC_REQBUFS ioctl + */ + case VIDIOC_REQBUFS:{ + struct v4l2_requestbuffers *req = arg; + if (req->count > FRAME_NUM) { + pr_info("VIDIOC_REQBUFS: not enough buffer\n"); + req->count = FRAME_NUM; + } + + if ((req->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) || + (req->memory != V4L2_MEMORY_MMAP)) { + pr_debug("VIDIOC_REQBUFS: wrong buffer type\n"); + retval = -EINVAL; + break; + } + + mxc_streamoff(cam); + mxc_free_frame_buf(cam); + + retval = mxc_allocate_frame_buf(cam, req->count); + break; + } + + /*! + * V4l2 VIDIOC_QUERYBUF ioctl + */ + case VIDIOC_QUERYBUF:{ + struct v4l2_buffer *buf = arg; + int index = buf->index; + + if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + pr_debug + ("VIDIOC_QUERYBUFS: wrong buffer type\n"); + retval = -EINVAL; + break; + } + + memset(buf, 0, sizeof(buf)); + buf->index = index; + + down(&cam->param_lock); + retval = mxc_v4l2_buffer_status(cam, buf); + up(&cam->param_lock); + break; + } + + /*! + * V4l2 VIDIOC_QBUF ioctl + */ + case VIDIOC_QBUF:{ + struct v4l2_buffer *buf = arg; + int index = buf->index; + + pr_debug("VIDIOC_QBUF: %d\n", buf->index); + + spin_lock_irqsave(&cam->int_lock, lock_flags); + if ((cam->frame[index].buffer.flags & 0x7) == + V4L2_BUF_FLAG_MAPPED) { + cam->frame[index].buffer.flags |= + V4L2_BUF_FLAG_QUEUED; + if (cam->skip_frame > 0) { + list_add_tail(&cam->frame[index].queue, + &cam->working_q); + retval = + cam->enc_update_eba(cam-> + frame[index]. + paddress, + &cam-> + ping_pong_csi); + cam->skip_frame = 0; + } else { + list_add_tail(&cam->frame[index].queue, + &cam->ready_q); + } + } else if (cam->frame[index].buffer.flags & + V4L2_BUF_FLAG_QUEUED) { + pr_debug + ("VIDIOC_QBUF: buffer already queued\n"); + } else if (cam->frame[index].buffer. + flags & V4L2_BUF_FLAG_DONE) { + pr_debug + ("VIDIOC_QBUF: overwrite done buffer.\n"); + cam->frame[index].buffer.flags &= + ~V4L2_BUF_FLAG_DONE; + cam->frame[index].buffer.flags |= + V4L2_BUF_FLAG_QUEUED; + } + buf->flags = cam->frame[index].buffer.flags; + spin_unlock_irqrestore(&cam->int_lock, lock_flags); + break; + } + + /*! + * V4l2 VIDIOC_DQBUF ioctl + */ + case VIDIOC_DQBUF:{ + struct v4l2_buffer *buf = arg; + + retval = mxc_v4l_dqueue(cam, buf); + + break; + } + + /*! + * V4l2 VIDIOC_STREAMON ioctl + */ + case VIDIOC_STREAMON:{ + cam->capture_on = true; + retval = mxc_streamon(cam); + break; + } + + /*! + * V4l2 VIDIOC_STREAMOFF ioctl + */ + case VIDIOC_STREAMOFF:{ + retval = mxc_streamoff(cam); + cam->capture_on = false; + break; + } + + /*! + * V4l2 VIDIOC_G_CTRL ioctl + */ + case VIDIOC_G_CTRL:{ + retval = mxc_get_v42l_control(cam, arg); + break; + } + + /*! + * V4l2 VIDIOC_S_CTRL ioctl + */ + case VIDIOC_S_CTRL:{ + retval = mxc_set_v42l_control(cam, arg); + break; + } + + /*! + * V4l2 VIDIOC_CROPCAP ioctl + */ + case VIDIOC_CROPCAP:{ + struct v4l2_cropcap *cap = arg; + + if (cap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && + cap->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) { + retval = -EINVAL; + break; + } + cap->bounds = cam->crop_bounds; + cap->defrect = cam->crop_defrect; + break; + } + + /*! + * V4l2 VIDIOC_G_CROP ioctl + */ + case VIDIOC_G_CROP:{ + struct v4l2_crop *crop = arg; + + if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && + crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) { + retval = -EINVAL; + break; + } + crop->c = cam->crop_current; + break; + } + + /*! + * V4l2 VIDIOC_S_CROP ioctl + */ + case VIDIOC_S_CROP:{ + struct v4l2_crop *crop = arg; + struct v4l2_rect *b = &cam->crop_bounds; + int i; + + if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && + crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) { + retval = -EINVAL; + break; + } + + crop->c.top = (crop->c.top < b->top) ? b->top + : crop->c.top; + if (crop->c.top > b->top + b->height) + crop->c.top = b->top + b->height - 1; + if (crop->c.height > b->top + b->height - crop->c.top) + crop->c.height = + b->top + b->height - crop->c.top; + + crop->c.left = (crop->c.left < b->left) ? b->left + : crop->c.left; + if (crop->c.left > b->left + b->width) + crop->c.left = b->left + b->width - 1; + if (crop->c.width > b->left - crop->c.left + b->width) + crop->c.width = + b->left - crop->c.left + b->width; + + crop->c.width &= ~0x1; + + /* + * MX27 PrP limitation: + * The right spare space (CSI_FRAME_X_SIZE + * - SOURCE_LINE_STRIDE - PICTURE_X_SIZE)) must be + * multiple of 32. + * So we tune the crop->c.left value to the closest + * desired cropping value and meet the PrP requirement. + */ + i = ((b->left + b->width) + - (crop->c.left + crop->c.width)) % 32; + if (i <= 16) { + if (crop->c.left + crop->c.width + i + <= b->left + b->width) + crop->c.left += i; + else if (crop->c.left - (32 - i) >= b->left) + crop->c.left -= 32 - i; + else { + retval = -EINVAL; + break; + } + } else { + if (crop->c.left - (32 - i) >= b->left) + crop->c.left -= 32 - i; + else if (crop->c.left + crop->c.width + i + <= b->left + b->width) + crop->c.left += i; + else { + retval = -EINVAL; + break; + } + } + + cam->crop_current = crop->c; + + break; + } + + /*! + * V4l2 VIDIOC_OVERLAY ioctl + */ + case VIDIOC_OVERLAY:{ + int *on = arg; + if (*on) { + cam->overlay_on = true; + retval = start_preview(cam); + } + if (!*on) { + retval = stop_preview(cam); + cam->overlay_on = false; + } + break; + } + + /*! + * V4l2 VIDIOC_G_FBUF ioctl + */ + case VIDIOC_G_FBUF:{ + struct v4l2_framebuffer *fb = arg; + struct fb_var_screeninfo *var; + + if (cam->output >= num_registered_fb) { + retval = -EINVAL; + break; + } + + var = ®istered_fb[cam->output]->var; + cam->v4l2_fb.fmt.width = var->xres; + cam->v4l2_fb.fmt.height = var->yres; + cam->v4l2_fb.fmt.bytesperline = + var->xres_virtual * var->bits_per_pixel; + cam->v4l2_fb.fmt.colorspace = V4L2_COLORSPACE_SRGB; + *fb = cam->v4l2_fb; + break; + } + + /*! + * V4l2 VIDIOC_S_FBUF ioctl + */ + case VIDIOC_S_FBUF:{ + struct v4l2_framebuffer *fb = arg; + cam->v4l2_fb.flags = fb->flags; + cam->v4l2_fb.fmt.pixelformat = fb->fmt.pixelformat; + break; + } + + case VIDIOC_G_PARM:{ + struct v4l2_streamparm *parm = arg; + if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + pr_debug("VIDIOC_G_PARM invalid type\n"); + retval = -EINVAL; + break; + } + parm->parm.capture = cam->streamparm.parm.capture; + break; + } + case VIDIOC_S_PARM:{ + struct v4l2_streamparm *parm = arg; + retval = mxc_v4l2_s_param(cam, parm); + break; + } + + /* linux v4l2 bug, kernel c0485619 user c0405619 */ + case VIDIOC_ENUMSTD:{ + struct v4l2_standard *e = arg; + *e = cam->standard; + pr_debug("VIDIOC_ENUMSTD call\n"); + retval = 0; + break; + } + + case VIDIOC_G_STD:{ + v4l2_std_id *e = arg; + *e = cam->standard.id; + break; + } + + case VIDIOC_S_STD:{ + break; + } + + case VIDIOC_ENUMOUTPUT: + { + struct v4l2_output *output = arg; + + if (output->index >= num_registered_fb) { + retval = -EINVAL; + break; + } + + strncpy(output->name, + registered_fb[output->index]->fix.id, 31); + output->type = V4L2_OUTPUT_TYPE_ANALOG; + output->audioset = 0; + output->modulator = 0; + output->std = V4L2_STD_UNKNOWN; + + break; + } + case VIDIOC_G_OUTPUT: + { + int *p_output_num = arg; + + *p_output_num = cam->output; + break; + } + case VIDIOC_S_OUTPUT: + { + int *p_output_num = arg; + + if (*p_output_num >= num_registered_fb) { + retval = -EINVAL; + break; + } + + cam->output = *p_output_num; + break; + } + + case VIDIOC_ENUM_FMT: + case VIDIOC_TRY_FMT: + case VIDIOC_QUERYCTRL: + case VIDIOC_ENUMINPUT: + case VIDIOC_G_INPUT: + case VIDIOC_S_INPUT: + case VIDIOC_G_TUNER: + case VIDIOC_S_TUNER: + case VIDIOC_G_FREQUENCY: + case VIDIOC_S_FREQUENCY: + default: + retval = -EINVAL; + break; + } + + up(&cam->busy_lock); + return retval; +} + +/* + * V4L interface - ioctl function + * + * @return None + */ +static int +mxc_v4l_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + return video_usercopy(inode, file, cmd, arg, mxc_v4l_do_ioctl); +} + +/*! + * V4L interface - mmap function + * + * @param file structure file * + * + * @param vma structure vm_area_struct * + * + * @return status 0 Success, EINTR busy lock error, ENOBUFS remap_page error + */ +static int mxc_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct video_device *dev = video_devdata(file); + unsigned long size; + int res = 0; + cam_data *cam = dev->priv; + + pr_debug("pgoff=0x%lx, start=0x%lx, end=0x%lx\n", + vma->vm_pgoff, vma->vm_start, vma->vm_end); + + /* make this _really_ smp-safe */ + if (down_interruptible(&cam->busy_lock)) + return -EINTR; + + size = vma->vm_end - vma->vm_start; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + if (remap_pfn_range(vma, vma->vm_start, + vma->vm_pgoff, size, vma->vm_page_prot)) { + pr_debug("mxc_mmap: remap_pfn_range failed\n"); + res = -ENOBUFS; + goto mxc_mmap_exit; + } + + vma->vm_flags &= ~VM_IO; /* using shared anonymous pages */ + + mxc_mmap_exit: + up(&cam->busy_lock); + return res; +} + +/*! + * V4L interface - poll function + * + * @param file structure file * + * + * @param wait structure poll_table * + * + * @return status POLLIN | POLLRDNORM + */ +static unsigned int mxc_poll(struct file *file, poll_table * wait) +{ + struct video_device *dev = video_devdata(file); + cam_data *cam = dev->priv; + wait_queue_head_t *queue = NULL; + int res = POLLIN | POLLRDNORM; + + if (down_interruptible(&cam->busy_lock)) + return -EINTR; + + queue = &cam->enc_queue; + poll_wait(file, queue, wait); + + up(&cam->busy_lock); + return res; +} + +static struct +file_operations mxc_v4l_fops = { + .owner = THIS_MODULE, + .open = mxc_v4l_open, + .release = mxc_v4l_close, + .read = mxc_v4l_read, + .ioctl = mxc_v4l_ioctl, + .mmap = mxc_mmap, + .poll = mxc_poll, +}; + +static struct video_device mxc_v4l_template = { + .owner = THIS_MODULE, + .name = "Mxc Camera", + .type = 0, + .type2 = VID_TYPE_CAPTURE, + .fops = &mxc_v4l_fops, + .release = video_device_release, +}; + +static void camera_platform_release(struct device *device) +{ +} + +/*! Device Definition for Mt9v111 devices */ +static struct platform_device mxc_v4l2_devices = { + .name = "mxc_v4l2", + .dev = { + .release = camera_platform_release, + }, + .id = 0, +}; + +extern struct camera_sensor camera_sensor_if; + +/*! +* Camera V4l2 callback function. +* +* @return status +*/ +static void camera_callback(u32 mask, void *dev) +{ + struct mxc_v4l_frame *done_frame; + struct mxc_v4l_frame *ready_frame; + + cam_data *cam = (cam_data *) dev; + if (cam == NULL) + return; + + if (list_empty(&cam->working_q)) { + printk(KERN_ERR "camera_callback: working queue empty\n"); + return; + } + + done_frame = + list_entry(cam->working_q.next, struct mxc_v4l_frame, queue); + if (done_frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) { + done_frame->buffer.flags |= V4L2_BUF_FLAG_DONE; + done_frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED; + + if (list_empty(&cam->ready_q)) { + cam->skip_frame++; + } else { + ready_frame = + list_entry(cam->ready_q.next, struct mxc_v4l_frame, + queue); + list_del(cam->ready_q.next); + list_add_tail(&ready_frame->queue, &cam->working_q); + cam->enc_update_eba(ready_frame->paddress, + &cam->ping_pong_csi); + } + + /* Added to the done queue */ + list_del(cam->working_q.next); + list_add_tail(&done_frame->queue, &cam->done_q); + + /* Wake up the queue */ + cam->enc_counter++; + wake_up_interruptible(&cam->enc_queue); + } else { + printk(KERN_ERR "camera_callback :buffer not queued\n"); + } +} + +/*! + * initialize cam_data structure + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static void init_camera_struct(cam_data *cam) +{ + int i; + + /* Default everything to 0 */ + memset(cam, 0, sizeof(cam_data)); + + init_MUTEX(&cam->param_lock); + init_MUTEX(&cam->busy_lock); + + cam->video_dev = video_device_alloc(); + if (cam->video_dev == NULL) + return; + + *(cam->video_dev) = mxc_v4l_template; + + video_set_drvdata(cam->video_dev, cam); + dev_set_drvdata(&mxc_v4l2_devices.dev, (void *)cam); + cam->video_dev->minor = -1; + + for (i = 0; i < FRAME_NUM; i++) { + cam->frame[i].width = 0; + cam->frame[i].height = 0; + cam->frame[i].paddress = 0; + } + + init_waitqueue_head(&cam->enc_queue); + init_waitqueue_head(&cam->still_queue); + + /* setup cropping */ + cam->crop_bounds.left = 0; + cam->crop_bounds.width = 640; + cam->crop_bounds.top = 0; + cam->crop_bounds.height = 480; + cam->crop_current = cam->crop_defrect = cam->crop_bounds; + cam->streamparm.parm.capture.capturemode = 0; + + cam->standard.index = 0; + cam->standard.id = V4L2_STD_UNKNOWN; + cam->standard.frameperiod.denominator = 30; + cam->standard.frameperiod.numerator = 1; + cam->standard.framelines = 480; + cam->streamparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cam->streamparm.parm.capture.timeperframe = cam->standard.frameperiod; + cam->streamparm.parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + cam->overlay_on = false; + cam->capture_on = false; + cam->skip_frame = 0; + cam->v4l2_fb.capability = V4L2_FBUF_CAP_EXTERNOVERLAY; + cam->v4l2_fb.flags = V4L2_FBUF_FLAG_PRIMARY; + + cam->v2f.fmt.pix.sizeimage = 352 * 288 * 3 / 2; + cam->v2f.fmt.pix.bytesperline = 288 * 3 / 2; + cam->v2f.fmt.pix.width = 288; + cam->v2f.fmt.pix.height = 352; + cam->v2f.fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420; + cam->win.w.width = 160; + cam->win.w.height = 160; + cam->win.w.left = 0; + cam->win.w.top = 0; + + cam->cam_sensor = &camera_sensor_if; + cam->enc_callback = camera_callback; + + init_waitqueue_head(&cam->power_queue); + cam->int_lock = __SPIN_LOCK_UNLOCKED(cam->int_lock); + spin_lock_init(&cam->int_lock); +} + +extern void gpio_sensor_active(void); +extern void gpio_sensor_inactive(void); + +/*! + * camera_power function + * Turn Sensor power On/Off + * + * @param cameraOn true to turn camera on, otherwise shut down + * + * @return status + */ +static u8 camera_power(bool cameraOn) +{ + if (cameraOn == true) { + gpio_sensor_active(); + csi_enable_mclk(csi_mclk_flag_backup, true, true); + } else { + csi_mclk_flag_backup = csi_read_mclk_flag(); + csi_enable_mclk(csi_mclk_flag_backup, false, false); + gpio_sensor_inactive(); + } + return 0; +} + +/*! + * This function is called to put the sensor in a low power state. Refer to the + * document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which I2C + * to suspend + * @param state the power state the device is entering + * + * @return The function returns 0 on success and -1 on failure. + */ +static int mxc_v4l2_suspend(struct platform_device *pdev, pm_message_t state) +{ + cam_data *cam = platform_get_drvdata(pdev); + + if (cam == NULL) { + return -1; + } + + cam->low_power = true; + + if (cam->overlay_on == true) + stop_preview(cam); + if ((cam->capture_on == true) && cam->enc_disable) { + cam->enc_disable(cam); + } + camera_power(false); + + return 0; +} + +/*! + * This function is called to bring the sensor back from a low power state.Refer + * to the document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure + * + * @return The function returns 0 on success and -1 on failure + */ +static int mxc_v4l2_resume(struct platform_device *pdev) +{ + cam_data *cam = platform_get_drvdata(pdev); + + if (cam == NULL) { + return -1; + } + + cam->low_power = false; + wake_up_interruptible(&cam->power_queue); + + if (cam->overlay_on == true) + start_preview(cam); + if (cam->capture_on == true) + mxc_streamon(cam); + camera_power(true); + + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxc_v4l2_driver = { + .driver = { + .name = "mxc_v4l2", + .owner = THIS_MODULE, + .bus = &platform_bus_type, + }, + .probe = NULL, + .remove = NULL, + .suspend = mxc_v4l2_suspend, + .resume = mxc_v4l2_resume, + .shutdown = NULL, +}; + +/*! + * Entry point for the V4L2 + * + * @return Error code indicating success or failure + */ +static __init int camera_init(void) +{ + u8 err = 0; + cam_data *cam; + + g_cam = kmalloc(sizeof(cam_data), GFP_KERNEL); + if (g_cam == NULL) { + pr_debug("failed to mxc_v4l_register_camera\n"); + return -1; + } + + cam = &g_cam; + init_camera_struct(cam); + + /* Register the I2C device */ + err = platform_device_register(&mxc_v4l2_devices); + if (err != 0) { + pr_debug("camera_init: platform_device_register failed.\n"); + video_device_release(cam->video_dev); + kfree(cam); + g_cam = NULL; + } + + /* Register the device driver structure. */ + err = platform_driver_register(&mxc_v4l2_driver); + if (err != 0) { + platform_device_unregister(&mxc_v4l2_devices); + pr_debug("camera_init: driver_register failed.\n"); + video_device_release(cam->video_dev); + kfree(cam); + g_cam = NULL; + return err; + } + + /* register v4l device */ + if (video_register_device(cam->video_dev, VFL_TYPE_GRABBER, video_nr) + == -1) { + platform_driver_unregister(&mxc_v4l2_driver); + platform_device_unregister(&mxc_v4l2_devices); + video_device_release(cam->video_dev); + kfree(cam); + g_cam = NULL; + pr_debug("video_register_device failed\n"); + return -1; + } + + return err; +} + +/*! + * Exit and cleanup for the V4L2 + * + */ +static void __exit camera_exit(void) +{ + pr_debug("unregistering video\n"); + + video_unregister_device(g_cam->video_dev); + + platform_driver_unregister(&mxc_v4l2_driver); + platform_device_unregister(&mxc_v4l2_devices); + + if (g_cam->open_count) { + pr_debug("camera open -- setting ops to NULL\n"); + } else { + pr_debug("freeing camera\n"); + mxc_free_frame_buf(g_cam); + kfree(g_cam); + g_cam = NULL; + } +} + +module_init(camera_init); +module_exit(camera_exit); + +module_param(video_nr, int, 0444); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("V4L2 capture driver for Mxc based cameras"); +MODULE_LICENSE("GPL"); +MODULE_SUPPORTED_DEVICE("video"); diff -urN linux-2.6.26/drivers/media/video/mxc/capture/ipu_prp_enc.c linux-2.6.26-lab126/drivers/media/video/mxc/capture/ipu_prp_enc.c --- linux-2.6.26/drivers/media/video/mxc/capture/ipu_prp_enc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/ipu_prp_enc.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,455 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_prp_enc.c + * + * @brief IPU Use case for PRP-ENC + * + * @ingroup IPU + */ + +#include +#include +#include "mxc_v4l2_capture.h" +#include "ipu_prp_sw.h" + +#ifdef CAMERA_DBG + #define CAMERA_TRACE(x) (printk)x +#else + #define CAMERA_TRACE(x) +#endif + +static ipu_rotate_mode_t grotation = IPU_ROTATE_NONE; + +/* + * Function definitions + */ + +/*! + * IPU ENC callback function. + * + * @param irq int irq line + * @param dev_id void * device id + * + * @return status IRQ_HANDLED for handled + */ +static irqreturn_t prp_enc_callback(int irq, void *dev_id) +{ + cam_data *cam = (cam_data *) dev_id; + + if (cam->enc_callback == NULL) + return IRQ_HANDLED; + + cam->enc_callback(irq, dev_id); + + return IRQ_HANDLED; +} + +/*! + * PrpENC enable channel setup function + * + * @param cam struct cam_data * mxc capture instance + * + * @return status + */ +static int prp_enc_setup(cam_data * cam) +{ + ipu_channel_params_t enc; + int err = 0; + dma_addr_t dummy = 0xdeadbeaf; + + CAMERA_TRACE("In prp_enc_setup\n"); + if (!cam) { + printk(KERN_ERR "cam private is NULL\n"); + return -ENXIO; + } + memset(&enc, 0, sizeof(ipu_channel_params_t)); + + ipu_csi_get_window_size(&enc.csi_prp_enc_mem.in_width, + &enc.csi_prp_enc_mem.in_height, cam->csi); + + enc.csi_prp_enc_mem.in_pixel_fmt = IPU_PIX_FMT_UYVY; + enc.csi_prp_enc_mem.out_width = cam->v2f.fmt.pix.width; + enc.csi_prp_enc_mem.out_height = cam->v2f.fmt.pix.height; + enc.csi_prp_enc_mem.csi = cam->csi; + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + enc.csi_prp_enc_mem.out_width = cam->v2f.fmt.pix.height; + enc.csi_prp_enc_mem.out_height = cam->v2f.fmt.pix.width; + } + + if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) { + enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YUV420P; + pr_info("YUV420\n"); + } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P) { + enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YUV422P; + pr_info("YUV422P\n"); + } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12) { + enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_NV12; + pr_info("NV12\n"); + } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR24) { + enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_BGR24; + pr_info("BGR24\n"); + } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24) { + enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_RGB24; + pr_info("RGB24\n"); + } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565) { + enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_RGB565; + pr_info("RGB565\n"); + } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR32) { + enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_BGR32; + pr_info("BGR32\n"); + } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB32) { + enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_RGB32; + pr_info("RGB32\n"); + } else { + printk(KERN_ERR "format not supported\n"); + return -EINVAL; + } + + err = ipu_init_channel(CSI_PRP_ENC_MEM, &enc); + if (err != 0) { + printk(KERN_ERR "ipu_init_channel %d\n", err); + return err; + } + + ipu_csi_enable_mclk_if(CSI_MCLK_ENC, cam->csi, true, true); + + grotation = cam->rotation; + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + if (cam->rot_enc_bufs_vaddr[0]) { + dma_free_coherent(0, cam->rot_enc_buf_size[0], + cam->rot_enc_bufs_vaddr[0], + cam->rot_enc_bufs[0]); + } + if (cam->rot_enc_bufs_vaddr[1]) { + dma_free_coherent(0, cam->rot_enc_buf_size[1], + cam->rot_enc_bufs_vaddr[1], + cam->rot_enc_bufs[1]); + } + cam->rot_enc_buf_size[0] = + PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage); + cam->rot_enc_bufs_vaddr[0] = + (void *)dma_alloc_coherent(0, cam->rot_enc_buf_size[0], + &cam->rot_enc_bufs[0], + GFP_DMA | GFP_KERNEL); + if (!cam->rot_enc_bufs_vaddr[0]) { + printk(KERN_ERR "alloc enc_bufs0\n"); + return -ENOMEM; + } + cam->rot_enc_buf_size[1] = + PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage); + cam->rot_enc_bufs_vaddr[1] = + (void *)dma_alloc_coherent(0, cam->rot_enc_buf_size[1], + &cam->rot_enc_bufs[1], + GFP_DMA | GFP_KERNEL); + if (!cam->rot_enc_bufs_vaddr[1]) { + dma_free_coherent(0, cam->rot_enc_buf_size[0], + cam->rot_enc_bufs_vaddr[0], + cam->rot_enc_bufs[0]); + cam->rot_enc_bufs_vaddr[0] = NULL; + cam->rot_enc_bufs[0] = 0; + printk(KERN_ERR "alloc enc_bufs1\n"); + return -ENOMEM; + } + + err = ipu_init_channel_buffer(CSI_PRP_ENC_MEM, + IPU_OUTPUT_BUFFER, + enc.csi_prp_enc_mem.out_pixel_fmt, + enc.csi_prp_enc_mem.out_width, + enc.csi_prp_enc_mem.out_height, + enc.csi_prp_enc_mem.out_width, + IPU_ROTATE_NONE, + cam->rot_enc_bufs[0], + cam->rot_enc_bufs[1], 0, 0); + if (err != 0) { + printk(KERN_ERR "CSI_PRP_ENC_MEM err\n"); + return err; + } + + err = ipu_init_channel(MEM_ROT_ENC_MEM, NULL); + if (err != 0) { + printk(KERN_ERR "MEM_ROT_ENC_MEM channel err\n"); + return err; + } + + err = ipu_init_channel_buffer(MEM_ROT_ENC_MEM, IPU_INPUT_BUFFER, + enc.csi_prp_enc_mem.out_pixel_fmt, + enc.csi_prp_enc_mem.out_width, + enc.csi_prp_enc_mem.out_height, + enc.csi_prp_enc_mem.out_width, + cam->rotation, + cam->rot_enc_bufs[0], + cam->rot_enc_bufs[1], 0, 0); + if (err != 0) { + printk(KERN_ERR "MEM_ROT_ENC_MEM input buffer\n"); + return err; + } + + err = + ipu_init_channel_buffer(MEM_ROT_ENC_MEM, IPU_OUTPUT_BUFFER, + enc.csi_prp_enc_mem.out_pixel_fmt, + enc.csi_prp_enc_mem.out_height, + enc.csi_prp_enc_mem.out_width, + cam->v2f.fmt.pix.bytesperline / + bytes_per_pixel(enc.csi_prp_enc_mem. + out_pixel_fmt), + IPU_ROTATE_NONE, dummy, dummy, + cam->offset.u_offset, + cam->offset.v_offset); + if (err != 0) { + printk(KERN_ERR "MEM_ROT_ENC_MEM output buffer\n"); + return err; + } + + err = ipu_link_channels(CSI_PRP_ENC_MEM, MEM_ROT_ENC_MEM); + if (err < 0) { + printk(KERN_ERR + "link CSI_PRP_ENC_MEM-MEM_ROT_ENC_MEM\n"); + return err; + } + + err = ipu_enable_channel(CSI_PRP_ENC_MEM); + if (err < 0) { + printk(KERN_ERR "ipu_enable_channel CSI_PRP_ENC_MEM\n"); + return err; + } + err = ipu_enable_channel(MEM_ROT_ENC_MEM); + if (err < 0) { + printk(KERN_ERR "ipu_enable_channel MEM_ROT_ENC_MEM\n"); + return err; + } + + ipu_select_buffer(CSI_PRP_ENC_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(CSI_PRP_ENC_MEM, IPU_OUTPUT_BUFFER, 1); + } else { + err = + ipu_init_channel_buffer(CSI_PRP_ENC_MEM, IPU_OUTPUT_BUFFER, + enc.csi_prp_enc_mem.out_pixel_fmt, + enc.csi_prp_enc_mem.out_width, + enc.csi_prp_enc_mem.out_height, + cam->v2f.fmt.pix.bytesperline / + bytes_per_pixel(enc.csi_prp_enc_mem. + out_pixel_fmt), + cam->rotation, dummy, dummy, + cam->offset.u_offset, + cam->offset.v_offset); + if (err != 0) { + printk(KERN_ERR "CSI_PRP_ENC_MEM output buffer\n"); + return err; + } + err = ipu_enable_channel(CSI_PRP_ENC_MEM); + if (err < 0) { + printk(KERN_ERR "ipu_enable_channel CSI_PRP_ENC_MEM\n"); + return err; + } + } + + return err; +} + +/*! + * function to update physical buffer address for encorder IDMA channel + * + * @param eba physical buffer address for encorder IDMA channel + * @param buffer_num int buffer 0 or buffer 1 + * + * @return status + */ +static int prp_enc_eba_update(dma_addr_t eba, int *buffer_num) +{ + int err = 0; + + pr_debug("eba %x\n", eba); + if (grotation >= IPU_ROTATE_90_RIGHT) { + err = ipu_update_channel_buffer(MEM_ROT_ENC_MEM, + IPU_OUTPUT_BUFFER, *buffer_num, + eba); + } else { + err = ipu_update_channel_buffer(CSI_PRP_ENC_MEM, + IPU_OUTPUT_BUFFER, *buffer_num, + eba); + } + if (err != 0) { + printk(KERN_ERR "err %d buffer_num %d\n", err, *buffer_num); + return err; + } + + if (grotation >= IPU_ROTATE_90_RIGHT) { + ipu_select_buffer(MEM_ROT_ENC_MEM, IPU_OUTPUT_BUFFER, + *buffer_num); + } else { + ipu_select_buffer(CSI_PRP_ENC_MEM, IPU_OUTPUT_BUFFER, + *buffer_num); + } + + *buffer_num = (*buffer_num == 0) ? 1 : 0; + return 0; +} + +/*! + * Enable encoder task + * @param private struct cam_data * mxc capture instance + * + * @return status + */ +static int prp_enc_enabling_tasks(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + CAMERA_TRACE("IPU:In prp_enc_enabling_tasks\n"); + + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + err = ipu_request_irq(IPU_IRQ_PRP_ENC_ROT_OUT_EOF, + prp_enc_callback, 0, "Mxc Camera", cam); + } else { + err = ipu_request_irq(IPU_IRQ_PRP_ENC_OUT_EOF, + prp_enc_callback, 0, "Mxc Camera", cam); + } + if (err != 0) { + printk(KERN_ERR "Error registering rot irq\n"); + return err; + } + + err = prp_enc_setup(cam); + if (err != 0) { + printk(KERN_ERR "prp_enc_setup %d\n", err); + return err; + } + + return err; +} + +/*! + * Disable encoder task + * @param private struct cam_data * mxc capture instance + * + * @return int + */ +static int prp_enc_disabling_tasks(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + ipu_free_irq(IPU_IRQ_PRP_ENC_ROT_OUT_EOF, cam); + } else { + ipu_free_irq(IPU_IRQ_PRP_ENC_OUT_EOF, cam); + } + + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + ipu_unlink_channels(CSI_PRP_ENC_MEM, MEM_ROT_ENC_MEM); + } + + err = ipu_disable_channel(CSI_PRP_ENC_MEM, true); + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + err |= ipu_disable_channel(MEM_ROT_ENC_MEM, true); + } + + ipu_uninit_channel(CSI_PRP_ENC_MEM); + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + ipu_uninit_channel(MEM_ROT_ENC_MEM); + } + + ipu_csi_enable_mclk_if(CSI_MCLK_ENC, cam->csi, false, false); + + return err; +} + +/*! + * function to select PRP-ENC as the working path + * + * @param private struct cam_data * mxc capture instance + * + * @return int + */ +int prp_enc_select(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + + if (cam) { + cam->enc_update_eba = prp_enc_eba_update; + cam->enc_enable = prp_enc_enabling_tasks; + cam->enc_disable = prp_enc_disabling_tasks; + } else { + err = -EIO; + } + + return err; +} + +/*! + * function to de-select PRP-ENC as the working path + * + * @param private struct cam_data * mxc capture instance + * + * @return int + */ +int prp_enc_deselect(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + + //err = prp_enc_disabling_tasks(cam); + + if (cam) { + cam->enc_update_eba = NULL; + cam->enc_enable = NULL; + cam->enc_disable = NULL; + if (cam->rot_enc_bufs_vaddr[0]) { + dma_free_coherent(0, cam->rot_enc_buf_size[0], + cam->rot_enc_bufs_vaddr[0], + cam->rot_enc_bufs[0]); + cam->rot_enc_bufs_vaddr[0] = NULL; + cam->rot_enc_bufs[0] = 0; + } + if (cam->rot_enc_bufs_vaddr[1]) { + dma_free_coherent(0, cam->rot_enc_buf_size[1], + cam->rot_enc_bufs_vaddr[1], + cam->rot_enc_bufs[1]); + cam->rot_enc_bufs_vaddr[1] = NULL; + cam->rot_enc_bufs[1] = 0; + } + } + + return err; +} + +/*! + * Init the Encorder channels + * + * @return Error code indicating success or failure + */ +__init int prp_enc_init(void) +{ + return 0; +} + +/*! + * Deinit the Encorder channels + * + */ +void __exit prp_enc_exit(void) +{ +} + +module_init(prp_enc_init); +module_exit(prp_enc_exit); + +EXPORT_SYMBOL(prp_enc_select); +EXPORT_SYMBOL(prp_enc_deselect); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("IPU PRP ENC Driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/media/video/mxc/capture/ipu_prp_sw.h linux-2.6.26-lab126/drivers/media/video/mxc/capture/ipu_prp_sw.h --- linux-2.6.26/drivers/media/video/mxc/capture/ipu_prp_sw.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/ipu_prp_sw.h 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,36 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_prp_sw.h + * + * @brief This file contains the IPU PRP use case driver header. + * + * @ingroup IPU + */ + +#ifndef _INCLUDE_IPU__PRP_SW_H_ +#define _INCLUDE_IPU__PRP_SW_H_ + +int prp_enc_select(void *private); +int prp_enc_deselect(void *private); +int prp_vf_adc_select(void *private); +int prp_vf_sdc_select(void *private); +int prp_vf_sdc_select_bg(void *private); +int prp_vf_adc_deselect(void *private); +int prp_vf_sdc_deselect(void *private); +int prp_vf_sdc_deselect_bg(void *private); +int prp_still_select(void *private); +int prp_still_deselect(void *private); + +#endif diff -urN linux-2.6.26/drivers/media/video/mxc/capture/ipu_prp_vf_adc.c linux-2.6.26-lab126/drivers/media/video/mxc/capture/ipu_prp_vf_adc.c --- linux-2.6.26/drivers/media/video/mxc/capture/ipu_prp_vf_adc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/ipu_prp_vf_adc.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,601 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_prp_vf_adc.c + * + * @brief IPU Use case for PRP-VF + * + * @ingroup IPU + */ + +#include "mxc_v4l2_capture.h" +#include "ipu_prp_sw.h" +#include +#include +#include + +/* + * Function definitions + */ + +/*! + * prpvf_start - start the vf task + * + * @param private cam_data * mxc v4l2 main structure + * + */ +static int prpvf_start(void *private) +{ + cam_data *cam = (cam_data *) private; + ipu_channel_params_t vf; + ipu_channel_params_t params; + u32 format = IPU_PIX_FMT_RGB565; + u32 size = 2; + int err = 0; + + if (!cam) { + printk(KERN_ERR "prpvf_start private is NULL\n"); + return -ENXIO; + } + + if (cam->overlay_active == true) { + printk(KERN_ERR "prpvf_start already start.\n"); + return 0; + } + + mxcfb_set_refresh_mode(cam->overlay_fb, MXCFB_REFRESH_OFF, 0); + + memset(&vf, 0, sizeof(ipu_channel_params_t)); + ipu_csi_get_window_size(&vf.csi_prp_vf_adc.in_width, + &vf.csi_prp_vf_adc.in_height); + vf.csi_prp_vf_adc.in_pixel_fmt = IPU_PIX_FMT_UYVY; + vf.csi_prp_vf_adc.out_width = cam->win.w.width; + vf.csi_prp_vf_adc.out_height = cam->win.w.height; + vf.csi_prp_vf_adc.graphics_combine_en = 0; + vf.csi_prp_vf_adc.out_left = cam->win.w.left; + + /* hope to be removed when those offset taken cared by adc driver. */ +#ifdef CONFIG_FB_MXC_EPSON_QVGA_PANEL + vf.csi_prp_vf_adc.out_left += 12; +#endif +#ifdef CONFIG_FB_MXC_EPSON_PANEL + vf.csi_prp_vf_adc.out_left += 2; +#endif + + vf.csi_prp_vf_adc.out_top = cam->win.w.top; + + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + vf.csi_prp_vf_adc.out_width = cam->win.w.height; + vf.csi_prp_vf_adc.out_height = cam->win.w.width; + + size = cam->win.w.width * cam->win.w.height * size; + vf.csi_prp_vf_adc.out_pixel_fmt = format; + err = ipu_init_channel(CSI_PRP_VF_MEM, &vf); + if (err != 0) + return err; + + ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, true, true); + + if (cam->vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->vf_bufs_size[0], + cam->vf_bufs_vaddr[0], + cam->vf_bufs[0]); + } + if (cam->vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->vf_bufs_size[1], + cam->vf_bufs_vaddr[1], + cam->vf_bufs[1]); + } + cam->vf_bufs_size[0] = size; + cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0, + cam-> + vf_bufs_size + [0], + &cam-> + vf_bufs[0], + GFP_DMA | + GFP_KERNEL); + if (cam->vf_bufs_vaddr[0] == NULL) { + printk(KERN_ERR + "prpvf_start: Error to allocate vf buffer\n"); + err = -ENOMEM; + goto out_3; + } + cam->vf_bufs_size[1] = size; + cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0, + cam-> + vf_bufs_size + [1], + &cam-> + vf_bufs[1], + GFP_DMA | + GFP_KERNEL); + if (cam->vf_bufs_vaddr[1] == NULL) { + printk(KERN_ERR + "prpvf_start: Error to allocate vf buffer\n"); + err = -ENOMEM; + goto out_3; + } + + err = ipu_init_channel_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, + format, + vf.csi_prp_vf_mem.out_width, + vf.csi_prp_vf_mem.out_height, + vf.csi_prp_vf_mem.out_width, + IPU_ROTATE_NONE, + cam->vf_bufs[0], cam->vf_bufs[1], + 0, 0); + if (err != 0) + goto out_3; + + if (cam->rot_vf_bufs[0]) { + dma_free_coherent(0, cam->rot_vf_buf_size[0], + cam->rot_vf_bufs_vaddr[0], + cam->rot_vf_bufs[0]); + } + if (cam->rot_vf_bufs[1]) { + dma_free_coherent(0, cam->rot_vf_buf_size[1], + cam->rot_vf_bufs_vaddr[1], + cam->rot_vf_bufs[1]); + } + cam->rot_vf_buf_size[0] = PAGE_ALIGN(size); + cam->rot_vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0, + cam-> + rot_vf_buf_size + [0], + &cam-> + rot_vf_bufs + [0], + GFP_DMA | + GFP_KERNEL); + if (cam->rot_vf_bufs_vaddr[0] == NULL) { + printk(KERN_ERR + "prpvf_start: Error to allocate rot_vf_bufs\n"); + err = -ENOMEM; + goto out_3; + } + cam->rot_vf_buf_size[1] = PAGE_ALIGN(size); + cam->rot_vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0, + cam-> + rot_vf_buf_size + [1], + &cam-> + rot_vf_bufs + [1], + GFP_DMA | + GFP_KERNEL); + if (cam->rot_vf_bufs_vaddr[1] == NULL) { + printk(KERN_ERR + "prpvf_start: Error to allocate rot_vf_bufs\n"); + err = -ENOMEM; + goto out_3; + } + err = ipu_init_channel(MEM_ROT_VF_MEM, NULL); + if (err != 0) { + printk(KERN_ERR "prpvf_start :Error " + "MEM_ROT_VF_MEM channel\n"); + goto out_3; + } + + err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_INPUT_BUFFER, + format, + vf.csi_prp_vf_mem.out_width, + vf.csi_prp_vf_mem.out_height, + vf.csi_prp_vf_mem.out_width, + cam->rotation, cam->vf_bufs[0], + cam->vf_bufs[1], 0, 0); + if (err != 0) { + printk(KERN_ERR "prpvf_start: Error " + "MEM_ROT_VF_MEM input buffer\n"); + goto out_2; + } + + err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, + format, + vf.csi_prp_vf_mem.out_height, + vf.csi_prp_vf_mem.out_width, + vf.csi_prp_vf_mem.out_height, + IPU_ROTATE_NONE, + cam->rot_vf_bufs[0], + cam->rot_vf_bufs[1], 0, 0); + if (err != 0) { + printk(KERN_ERR "prpvf_start: Error " + "MEM_ROT_VF_MEM output buffer\n"); + goto out_2; + } + + err = ipu_link_channels(CSI_PRP_VF_MEM, MEM_ROT_VF_MEM); + if (err < 0) { + printk(KERN_ERR "prpvf_start: Error " + "linking CSI_PRP_VF_MEM-MEM_ROT_VF_MEM\n"); + goto out_2; + } + + ipu_disable_channel(ADC_SYS2, false); + ipu_uninit_channel(ADC_SYS2); + + params.adc_sys2.disp = DISP0; + params.adc_sys2.ch_mode = WriteTemplateNonSeq; + params.adc_sys2.out_left = cam->win.w.left; + /* going to be removed when those offset taken cared by adc driver. */ +#ifdef CONFIG_FB_MXC_EPSON_QVGA_PANEL + params.adc_sys2.out_left += 12; +#endif +#ifdef CONFIG_FB_MXC_EPSON_PANEL + params.adc_sys2.out_left += 2; +#endif + params.adc_sys2.out_top = cam->win.w.top; + err = ipu_init_channel(ADC_SYS2, ¶ms); + if (err != 0) { + printk(KERN_ERR + "prpvf_start: Error initializing ADC SYS1\n"); + goto out_2; + } + + err = ipu_init_channel_buffer(ADC_SYS2, IPU_INPUT_BUFFER, + format, + vf.csi_prp_vf_mem.out_height, + vf.csi_prp_vf_mem.out_width, + vf.csi_prp_vf_mem.out_height, + IPU_ROTATE_NONE, + cam->rot_vf_bufs[0], + cam->rot_vf_bufs[1], 0, 0); + if (err != 0) { + printk(KERN_ERR "Error initializing ADC SYS1 buffer\n"); + goto out_1; + } + + err = ipu_link_channels(MEM_ROT_VF_MEM, ADC_SYS2); + if (err < 0) { + printk(KERN_ERR + "Error linking MEM_ROT_VF_MEM-ADC_SYS2\n"); + goto out_1; + } + + ipu_enable_channel(CSI_PRP_VF_MEM); + ipu_enable_channel(MEM_ROT_VF_MEM); + ipu_enable_channel(ADC_SYS2); + + ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 1); + ipu_select_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, 1); + } +#ifndef CONFIG_MXC_IPU_PRP_VF_SDC + else if (cam->rotation == IPU_ROTATE_NONE) { + vf.csi_prp_vf_adc.out_pixel_fmt = IPU_PIX_FMT_BGR32; + err = ipu_init_channel(CSI_PRP_VF_ADC, &vf); + if (err != 0) { + printk(KERN_ERR "prpvf_start: Error " + "initializing CSI_PRP_VF_ADC\n"); + return err; + } + ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, true, true); + err = ipu_init_channel_buffer(CSI_PRP_VF_ADC, IPU_OUTPUT_BUFFER, + format, cam->win.w.width, + cam->win.w.height, + cam->win.w.width, IPU_ROTATE_NONE, + 0, 0, 0, 0); + if (err != 0) { + printk(KERN_ERR "prpvf_start: Error " + "initializing CSI_PRP_VF_MEM\n"); + return err; + } + ipu_enable_channel(CSI_PRP_VF_ADC); + } +#endif + else { + size = cam->win.w.width * cam->win.w.height * size; + vf.csi_prp_vf_adc.out_pixel_fmt = format; + err = ipu_init_channel(CSI_PRP_VF_MEM, &vf); + if (err != 0) { + printk(KERN_ERR "prpvf_start: Error " + "initializing CSI_PRP_VF_MEM\n"); + return err; + } + + ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, true, true); + + if (cam->vf_bufs[0]) { + dma_free_coherent(0, cam->vf_bufs_size[0], + cam->vf_bufs_vaddr[0], + cam->vf_bufs[0]); + } + if (cam->vf_bufs[1]) { + dma_free_coherent(0, cam->vf_bufs_size[1], + cam->vf_bufs_vaddr[1], + cam->vf_bufs[1]); + } + cam->vf_bufs_size[0] = PAGE_ALIGN(size); + cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0, + cam-> + vf_bufs_size + [0], + &cam-> + vf_bufs[0], + GFP_DMA | + GFP_KERNEL); + if (cam->vf_bufs_vaddr[0] == NULL) { + printk(KERN_ERR + "prpvf_start: Error to allocate vf_bufs\n"); + err = -ENOMEM; + goto out_3; + } + cam->vf_bufs_size[1] = PAGE_ALIGN(size); + cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0, + cam-> + vf_bufs_size + [1], + &cam-> + vf_bufs[1], + GFP_DMA | + GFP_KERNEL); + if (cam->vf_bufs_vaddr[1] == NULL) { + printk(KERN_ERR + "prpvf_start: Error to allocate vf_bufs\n"); + err = -ENOMEM; + goto out_3; + } + err = ipu_init_channel_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, + format, + vf.csi_prp_vf_mem.out_width, + vf.csi_prp_vf_mem.out_height, + vf.csi_prp_vf_mem.out_width, + cam->rotation, + cam->vf_bufs[0], cam->vf_bufs[1], + 0, 0); + if (err != 0) { + printk(KERN_ERR "prpvf_start: Error " + "initializing CSI_PRP_VF_MEM\n"); + goto out_3; + } + + ipu_disable_channel(ADC_SYS2, false); + ipu_uninit_channel(ADC_SYS2); + + params.adc_sys2.disp = DISP0; + params.adc_sys2.ch_mode = WriteTemplateNonSeq; + params.adc_sys2.out_left = cam->win.w.left; + // going to be removed when those offset taken cared by adc driver. +#ifdef CONFIG_FB_MXC_EPSON_QVGA_PANEL + params.adc_sys2.out_left += 12; +#endif +#ifdef CONFIG_FB_MXC_EPSON_PANEL + params.adc_sys2.out_left += 2; +#endif + params.adc_sys2.out_top = cam->win.w.top; + err = ipu_init_channel(ADC_SYS2, ¶ms); + if (err != 0) { + printk(KERN_ERR "prpvf_start: Error " + "initializing ADC_SYS2\n"); + goto out_3; + } + + err = ipu_init_channel_buffer(ADC_SYS2, IPU_INPUT_BUFFER, + format, + vf.csi_prp_vf_mem.out_width, + vf.csi_prp_vf_mem.out_height, + vf.csi_prp_vf_mem.out_width, + IPU_ROTATE_NONE, cam->vf_bufs[0], + cam->vf_bufs[1], 0, 0); + if (err != 0) { + printk(KERN_ERR "prpvf_start: Error " + "initializing ADC SYS1 buffer\n"); + goto out_1; + } + + err = ipu_link_channels(CSI_PRP_VF_MEM, ADC_SYS2); + if (err < 0) { + printk(KERN_ERR "prpvf_start: Error " + "linking MEM_ROT_VF_MEM-ADC_SYS2\n"); + goto out_1; + } + + ipu_enable_channel(CSI_PRP_VF_MEM); + ipu_enable_channel(ADC_SYS2); + + ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 1); + } + + cam->overlay_active = true; + return err; + + out_1: + ipu_uninit_channel(ADC_SYS2); + out_2: + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + ipu_uninit_channel(MEM_ROT_VF_MEM); + } + out_3: + ipu_uninit_channel(CSI_PRP_VF_MEM); + if (cam->rot_vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->rot_vf_buf_size[0], + cam->rot_vf_bufs_vaddr[0], + cam->rot_vf_bufs[0]); + cam->rot_vf_bufs_vaddr[0] = NULL; + cam->rot_vf_bufs[0] = 0; + } + if (cam->rot_vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->rot_vf_buf_size[1], + cam->rot_vf_bufs_vaddr[1], + cam->rot_vf_bufs[1]); + cam->rot_vf_bufs_vaddr[1] = NULL; + cam->rot_vf_bufs[1] = 0; + } + if (cam->vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->vf_bufs_size[0], + cam->vf_bufs_vaddr[0], cam->vf_bufs[0]); + cam->vf_bufs_vaddr[0] = NULL; + cam->vf_bufs[0] = 0; + } + if (cam->vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->vf_bufs_size[1], + cam->vf_bufs_vaddr[1], cam->vf_bufs[1]); + cam->vf_bufs_vaddr[1] = NULL; + cam->vf_bufs[1] = 0; + } + return err; +} + +/*! + * prpvf_stop - stop the vf task + * + * @param private cam_data * mxc v4l2 main structure + * + */ +static int prpvf_stop(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + + if (cam->overlay_active == false) + return 0; + + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + ipu_unlink_channels(CSI_PRP_VF_MEM, MEM_ROT_VF_MEM); + ipu_unlink_channels(MEM_ROT_VF_MEM, ADC_SYS2); + + ipu_disable_channel(CSI_PRP_VF_MEM, true); + ipu_disable_channel(MEM_ROT_VF_MEM, true); + ipu_disable_channel(ADC_SYS2, true); + + ipu_uninit_channel(CSI_PRP_VF_MEM); + ipu_uninit_channel(MEM_ROT_VF_MEM); + ipu_uninit_channel(ADC_SYS2); + + ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, false, false); + } +#ifndef CONFIG_MXC_IPU_PRP_VF_SDC + else if (cam->rotation == IPU_ROTATE_NONE) { + ipu_disable_channel(CSI_PRP_VF_ADC, false); + ipu_uninit_channel(CSI_PRP_VF_ADC); + ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, false, false); + } +#endif + else { + ipu_unlink_channels(CSI_PRP_VF_MEM, ADC_SYS2); + + ipu_disable_channel(CSI_PRP_VF_MEM, true); + ipu_disable_channel(ADC_SYS2, true); + + ipu_uninit_channel(CSI_PRP_VF_MEM); + ipu_uninit_channel(ADC_SYS2); + + ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, false, false); + } + + if (cam->vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->vf_bufs_size[0], + cam->vf_bufs_vaddr[0], cam->vf_bufs[0]); + cam->vf_bufs_vaddr[0] = NULL; + cam->vf_bufs[0] = 0; + } + if (cam->vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->vf_bufs_size[1], + cam->vf_bufs_vaddr[1], cam->vf_bufs[1]); + cam->vf_bufs_vaddr[1] = NULL; + cam->vf_bufs[1] = 0; + } + if (cam->rot_vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->rot_vf_buf_size[0], + cam->rot_vf_bufs_vaddr[0], + cam->rot_vf_bufs[0]); + cam->rot_vf_bufs_vaddr[0] = NULL; + cam->rot_vf_bufs[0] = 0; + } + if (cam->rot_vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->rot_vf_buf_size[1], + cam->rot_vf_bufs_vaddr[1], + cam->rot_vf_bufs[1]); + cam->rot_vf_bufs_vaddr[1] = NULL; + cam->rot_vf_bufs[1] = 0; + } + + cam->overlay_active = false; + + mxcfb_set_refresh_mode(cam->overlay_fb, MXCFB_REFRESH_PARTIAL, 0); + return err; +} + +/*! + * function to select PRP-VF as the working path + * + * @param private cam_data * mxc v4l2 main structure + * + * @return status + */ +int prp_vf_adc_select(void *private) +{ + cam_data *cam; + if (private) { + cam = (cam_data *) private; + cam->vf_start_adc = prpvf_start; + cam->vf_stop_adc = prpvf_stop; + cam->overlay_active = false; + } else { + return -EIO; + } + return 0; +} + +/*! + * function to de-select PRP-VF as the working path + * + * @param private cam_data * mxc v4l2 main structure + * + * @return status + */ +int prp_vf_adc_deselect(void *private) +{ + cam_data *cam; + int err = 0; + err = prpvf_stop(private); + + if (private) { + cam = (cam_data *) private; + cam->vf_start_adc = NULL; + cam->vf_stop_adc = NULL; + } + return err; +} + +/*! + * Init viewfinder task. + * + * @return Error code indicating success or failure + */ +__init int prp_vf_adc_init(void) +{ + return 0; +} + +/*! + * Deinit viewfinder task. + * + * @return Error code indicating success or failure + */ +void __exit prp_vf_adc_exit(void) +{ +} + +module_init(prp_vf_adc_init); +module_exit(prp_vf_adc_exit); + +EXPORT_SYMBOL(prp_vf_adc_select); +EXPORT_SYMBOL(prp_vf_adc_deselect); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("IPU PRP VF ADC Driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/media/video/mxc/capture/ipu_prp_vf_sdc.c linux-2.6.26-lab126/drivers/media/video/mxc/capture/ipu_prp_vf_sdc.c --- linux-2.6.26/drivers/media/video/mxc/capture/ipu_prp_vf_sdc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/ipu_prp_vf_sdc.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,472 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_prp_vf_sdc.c + * + * @brief IPU Use case for PRP-VF + * + * @ingroup IPU + */ + +#include +#include +#include "mxc_v4l2_capture.h" +#include "ipu_prp_sw.h" + +/* + * Function definitions + */ + +/*! + * prpvf_start - start the vf task + * + * @param private cam_data * mxc v4l2 main structure + * + */ +static int prpvf_start(void *private) +{ + cam_data *cam = (cam_data *) private; + ipu_channel_params_t vf, params; + u32 format = IPU_PIX_FMT_RGB565; + u32 size = 2; + int err = 0; + + if (!cam) { + printk(KERN_ERR "private is NULL\n"); + return -EIO; + } + + if (cam->overlay_active == true) { + pr_debug("already started.\n"); + return 0; + } + + memset(&vf, 0, sizeof(ipu_channel_params_t)); + ipu_csi_get_window_size(&vf.csi_prp_vf_mem.in_width, + &vf.csi_prp_vf_mem.in_height, cam->csi); + vf.csi_prp_vf_mem.in_pixel_fmt = IPU_PIX_FMT_UYVY; + vf.csi_prp_vf_mem.out_width = cam->win.w.width; + vf.csi_prp_vf_mem.out_height = cam->win.w.height; + vf.csi_prp_vf_mem.csi = cam->csi; + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + vf.csi_prp_vf_mem.out_width = cam->win.w.height; + vf.csi_prp_vf_mem.out_height = cam->win.w.width; + } + vf.csi_prp_vf_mem.out_pixel_fmt = format; + size = cam->win.w.width * cam->win.w.height * size; + + err = ipu_init_channel(CSI_PRP_VF_MEM, &vf); + if (err != 0) + goto out_4; + + ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, true, true); + + if (cam->vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->vf_bufs_size[0], + cam->vf_bufs_vaddr[0], + (dma_addr_t) cam->vf_bufs[0]); + } + if (cam->vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->vf_bufs_size[1], + cam->vf_bufs_vaddr[1], + (dma_addr_t) cam->vf_bufs[1]); + } + cam->vf_bufs_size[0] = PAGE_ALIGN(size); + cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0, + cam->vf_bufs_size[0], + (dma_addr_t *) & + cam->vf_bufs[0], + GFP_DMA | + GFP_KERNEL); + if (cam->vf_bufs_vaddr[0] == NULL) { + printk(KERN_ERR "Error to allocate vf buffer\n"); + err = -ENOMEM; + goto out_3; + } + cam->vf_bufs_size[1] = PAGE_ALIGN(size); + cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0, + cam->vf_bufs_size[1], + (dma_addr_t *) & + cam->vf_bufs[1], + GFP_DMA | + GFP_KERNEL); + if (cam->vf_bufs_vaddr[1] == NULL) { + printk(KERN_ERR "Error to allocate vf buffer\n"); + err = -ENOMEM; + goto out_3; + } + pr_debug("vf_bufs %x %x\n", cam->vf_bufs[0], cam->vf_bufs[1]); + + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + err = ipu_init_channel_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, + format, + vf.csi_prp_vf_mem.out_width, + vf.csi_prp_vf_mem.out_height, + vf.csi_prp_vf_mem.out_width, + IPU_ROTATE_NONE, cam->vf_bufs[0], + cam->vf_bufs[1], 0, 0); + if (err != 0) { + goto out_3; + } + + if (cam->rot_vf_bufs[0]) { + dma_free_coherent(0, cam->rot_vf_buf_size[0], + cam->rot_vf_bufs_vaddr[0], + (dma_addr_t) cam->rot_vf_bufs[0]); + cam->rot_vf_bufs_vaddr[0] = NULL; + cam->rot_vf_bufs[0] = 0; + } + if (cam->rot_vf_bufs[1]) { + dma_free_coherent(0, cam->rot_vf_buf_size[1], + cam->rot_vf_bufs_vaddr[1], + (dma_addr_t) cam->rot_vf_bufs[1]); + cam->rot_vf_bufs_vaddr[1] = NULL; + cam->rot_vf_bufs[1] = 0; + } + cam->rot_vf_buf_size[0] = PAGE_ALIGN(size); + cam->rot_vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0, + cam-> + rot_vf_buf_size + [0], + &cam-> + rot_vf_bufs + [0], + GFP_DMA | + GFP_KERNEL); + if (cam->rot_vf_bufs_vaddr[0] == NULL) { + printk(KERN_ERR "alloc rot_vf_bufs.\n"); + err = -ENOMEM; + goto out_3; + } + cam->rot_vf_buf_size[1] = PAGE_ALIGN(size); + cam->rot_vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0, + cam-> + rot_vf_buf_size + [0], + &cam-> + rot_vf_bufs + [1], + GFP_DMA | + GFP_KERNEL); + if (cam->rot_vf_bufs_vaddr[1] == NULL) { + printk(KERN_ERR "alloc rot_vf_bufs.\n"); + err = -ENOMEM; + goto out_3; + } + pr_debug("rot_vf_bufs %x %x\n", cam->rot_vf_bufs[0], + cam->rot_vf_bufs[1]); + + err = ipu_init_channel(MEM_ROT_VF_MEM, NULL); + if (err != 0) { + printk(KERN_ERR "Error MEM_ROT_VF_MEM channel\n"); + goto out_3; + } + + err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_INPUT_BUFFER, + format, + vf.csi_prp_vf_mem.out_width, + vf.csi_prp_vf_mem.out_height, + vf.csi_prp_vf_mem.out_width, + cam->rotation, cam->vf_bufs[0], + cam->vf_bufs[1], 0, 0); + if (err != 0) { + printk(KERN_ERR "Error MEM_ROT_VF_MEM input buffer\n"); + goto out_3; + } + + err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, + format, + vf.csi_prp_vf_mem.out_height, + vf.csi_prp_vf_mem.out_width, + vf.csi_prp_vf_mem.out_height, + IPU_ROTATE_NONE, + cam->rot_vf_bufs[0], + cam->rot_vf_bufs[1], 0, 0); + if (err != 0) { + printk(KERN_ERR "Error MEM_ROT_VF_MEM output buffer\n"); + goto out_2; + } + + err = ipu_link_channels(CSI_PRP_VF_MEM, MEM_ROT_VF_MEM); + if (err < 0) { + printk(KERN_ERR + "Error link CSI_PRP_VF_MEM-MEM_ROT_VF_MEM\n"); + goto out_2; + } + + memset(¶ms, 0, sizeof(ipu_channel_params_t)); + params.mem_dp_fg_sync.in_pixel_fmt = format; + params.mem_dp_fg_sync.out_pixel_fmt = IPU_PIX_FMT_RGB24; + err = ipu_init_channel(MEM_FG_SYNC, ¶ms); + if (err != 0) + goto out_2; + + ipu_disp_set_window_pos(MEM_FG_SYNC, cam->win.w.left, + cam->win.w.top); + + err = ipu_init_channel_buffer(MEM_FG_SYNC, IPU_INPUT_BUFFER, + format, + vf.csi_prp_vf_mem.out_height, + vf.csi_prp_vf_mem.out_width, + vf.csi_prp_vf_mem.out_height, + IPU_ROTATE_NONE, + cam->rot_vf_bufs[0], + cam->rot_vf_bufs[1], 0, 0); + if (err != 0) { + printk(KERN_ERR "Error initializing SDC FG buffer\n"); + goto out_2; + } + + err = ipu_link_channels(MEM_ROT_VF_MEM, MEM_FG_SYNC); + if (err < 0) { + printk(KERN_ERR + "Error link MEM_ROT_VF_MEM-MEM_FG_SYNC\n"); + goto out_1; + } + + ipu_enable_channel(CSI_PRP_VF_MEM); + ipu_enable_channel(MEM_ROT_VF_MEM); + ipu_enable_channel(MEM_FG_SYNC); + + ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 1); + ipu_select_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, 1); + } else { + err = ipu_init_channel_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, + format, cam->win.w.width, + cam->win.w.height, + cam->win.w.width, cam->rotation, + cam->vf_bufs[0], cam->vf_bufs[1], + 0, 0); + if (err != 0) { + printk(KERN_ERR "Error initializing CSI_PRP_VF_MEM\n"); + goto out_4; + } + memset(¶ms, 0, sizeof(ipu_channel_params_t)); + params.mem_dp_fg_sync.in_pixel_fmt = format; + params.mem_dp_fg_sync.out_pixel_fmt = IPU_PIX_FMT_RGB24; + err = ipu_init_channel(MEM_FG_SYNC, ¶ms); + if (err != 0) + goto out_3; + + ipu_disp_set_window_pos(MEM_FG_SYNC, cam->win.w.left, + cam->win.w.top); + err = ipu_init_channel_buffer(MEM_FG_SYNC, + IPU_INPUT_BUFFER, format, + cam->win.w.width, + cam->win.w.height, + cam->win.w.width, IPU_ROTATE_NONE, + cam->vf_bufs[0], cam->vf_bufs[1], + 0, 0); + if (err != 0) { + printk(KERN_ERR "Error initializing SDC FG buffer\n"); + goto out_1; + } + + err = ipu_link_channels(CSI_PRP_VF_MEM, MEM_FG_SYNC); + if (err < 0) { + printk(KERN_ERR "Error linking ipu channels\n"); + goto out_1; + } + + ipu_enable_channel(CSI_PRP_VF_MEM); + ipu_enable_channel(MEM_FG_SYNC); + + ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 1); + } + + cam->overlay_active = true; + return err; + + out_1: + ipu_uninit_channel(MEM_FG_SYNC); + out_2: + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + ipu_uninit_channel(MEM_ROT_VF_MEM); + } + out_3: + ipu_uninit_channel(CSI_PRP_VF_MEM); + out_4: + if (cam->vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->vf_bufs_size[0], + cam->vf_bufs_vaddr[0], + (dma_addr_t) cam->vf_bufs[0]); + cam->vf_bufs_vaddr[0] = NULL; + cam->vf_bufs[0] = 0; + } + if (cam->vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->vf_bufs_size[1], + cam->vf_bufs_vaddr[1], + (dma_addr_t) cam->vf_bufs[1]); + cam->vf_bufs_vaddr[1] = NULL; + cam->vf_bufs[1] = 0; + } + if (cam->rot_vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->rot_vf_buf_size[0], + cam->rot_vf_bufs_vaddr[0], + (dma_addr_t) cam->rot_vf_bufs[0]); + cam->rot_vf_bufs_vaddr[0] = NULL; + cam->rot_vf_bufs[0] = 0; + } + if (cam->rot_vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->rot_vf_buf_size[1], + cam->rot_vf_bufs_vaddr[1], + (dma_addr_t) cam->rot_vf_bufs[1]); + cam->rot_vf_bufs_vaddr[1] = NULL; + cam->rot_vf_bufs[1] = 0; + } + return err; +} + +/*! + * prpvf_stop - stop the vf task + * + * @param private cam_data * mxc v4l2 main structure + * + */ +static int prpvf_stop(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + + if (cam->overlay_active == false) + return 0; + + ipu_disp_set_window_pos(MEM_FG_SYNC, 0, 0); + + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + ipu_unlink_channels(CSI_PRP_VF_MEM, MEM_ROT_VF_MEM); + ipu_unlink_channels(MEM_ROT_VF_MEM, MEM_FG_SYNC); + } else { + ipu_unlink_channels(CSI_PRP_VF_MEM, MEM_FG_SYNC); + } + + ipu_disable_channel(MEM_FG_SYNC, true); + ipu_disable_channel(CSI_PRP_VF_MEM, true); + + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + ipu_disable_channel(MEM_ROT_VF_MEM, true); + ipu_uninit_channel(MEM_ROT_VF_MEM); + } + ipu_uninit_channel(MEM_FG_SYNC); + ipu_uninit_channel(CSI_PRP_VF_MEM); + + ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, false, false); + + if (cam->vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->vf_bufs_size[0], + cam->vf_bufs_vaddr[0], + (dma_addr_t) cam->vf_bufs[0]); + cam->vf_bufs_vaddr[0] = NULL; + cam->vf_bufs[0] = 0; + } + if (cam->vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->vf_bufs_size[1], + cam->vf_bufs_vaddr[1], + (dma_addr_t) cam->vf_bufs[1]); + cam->vf_bufs_vaddr[1] = NULL; + cam->vf_bufs[1] = 0; + } + if (cam->rot_vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->rot_vf_buf_size[0], + cam->rot_vf_bufs_vaddr[0], + (dma_addr_t) cam->rot_vf_bufs[0]); + cam->rot_vf_bufs_vaddr[0] = NULL; + cam->rot_vf_bufs[0] = 0; + } + if (cam->rot_vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->rot_vf_buf_size[1], + cam->rot_vf_bufs_vaddr[1], + (dma_addr_t) cam->rot_vf_bufs[1]); + cam->rot_vf_bufs_vaddr[1] = NULL; + cam->rot_vf_bufs[1] = 0; + } + + cam->overlay_active = false; + return err; +} + +/*! + * function to select PRP-VF as the working path + * + * @param private cam_data * mxc v4l2 main structure + * + * @return status + */ +int prp_vf_sdc_select(void *private) +{ + cam_data *cam; + int err = 0; + if (private) { + cam = (cam_data *) private; + cam->vf_start_sdc = prpvf_start; + cam->vf_stop_sdc = prpvf_stop; + cam->overlay_active = false; + } else + err = -EIO; + + return err; +} + +/*! + * function to de-select PRP-VF as the working path + * + * @param private cam_data * mxc v4l2 main structure + * + * @return int + */ +int prp_vf_sdc_deselect(void *private) +{ + cam_data *cam; + int err = 0; + err = prpvf_stop(private); + + if (private) { + cam = (cam_data *) private; + cam->vf_start_sdc = NULL; + cam->vf_stop_sdc = NULL; + } + return err; +} + +/*! + * Init viewfinder task. + * + * @return Error code indicating success or failure + */ +__init int prp_vf_sdc_init(void) +{ + return 0; +} + +/*! + * Deinit viewfinder task. + * + * @return Error code indicating success or failure + */ +void __exit prp_vf_sdc_exit(void) +{ +} + +module_init(prp_vf_sdc_init); +module_exit(prp_vf_sdc_exit); + +EXPORT_SYMBOL(prp_vf_sdc_select); +EXPORT_SYMBOL(prp_vf_sdc_deselect); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("IPU PRP VF SDC Driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/media/video/mxc/capture/ipu_prp_vf_sdc_bg.c linux-2.6.26-lab126/drivers/media/video/mxc/capture/ipu_prp_vf_sdc_bg.c --- linux-2.6.26/drivers/media/video/mxc/capture/ipu_prp_vf_sdc_bg.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/ipu_prp_vf_sdc_bg.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,411 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_prp_vf_sdc_bg.c + * + * @brief IPU Use case for PRP-VF back-ground + * + * @ingroup IPU + */ +#include +#include +#include +#include "mxc_v4l2_capture.h" +#include "ipu_prp_sw.h" + +static int buffer_num = 0; +static int buffer_ready = 0; + +/* + * Function definitions + */ + +/*! + * SDC V-Sync callback function. + * + * @param irq int irq line + * @param dev_id void * device id + * + * @return status IRQ_HANDLED for handled + */ +static irqreturn_t prpvf_sdc_vsync_callback(int irq, void *dev_id) +{ + pr_debug("buffer_ready %d buffer_num %d\n", buffer_ready, buffer_num); + if (buffer_ready > 0) { + ipu_select_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, 0); + buffer_ready--; + } + + return IRQ_HANDLED; +} + +/*! + * VF EOF callback function. + * + * @param irq int irq line + * @param dev_id void * device id + * + * @return status IRQ_HANDLED for handled + */ +static irqreturn_t prpvf_vf_eof_callback(int irq, void *dev_id) +{ + pr_debug("buffer_ready %d buffer_num %d\n", buffer_ready, buffer_num); + + ipu_select_buffer(MEM_ROT_VF_MEM, IPU_INPUT_BUFFER, buffer_num); + + buffer_num = (buffer_num == 0) ? 1 : 0; + + ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, buffer_num); + buffer_ready++; + return IRQ_HANDLED; +} + +/*! + * prpvf_start - start the vf task + * + * @param private cam_data * mxc v4l2 main structure + * + */ +static int prpvf_start(void *private) +{ + cam_data *cam = (cam_data *) private; + ipu_channel_params_t vf; + u32 format; + u32 offset; + u32 bpp, size = 3; + int err = 0; + + if (!cam) { + printk(KERN_ERR "private is NULL\n"); + return -EIO; + } + + if (cam->overlay_active == true) { + pr_debug("already start.\n"); + return 0; + } + + format = cam->v4l2_fb.fmt.pixelformat; + if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR24) { + bpp = 3, size = 3; + pr_info("BGR24\n"); + } else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_RGB565) { + bpp = 2, size = 2; + pr_info("RGB565\n"); + } else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR32) { + bpp = 4, size = 4; + pr_info("BGR32\n"); + } else { + printk(KERN_ERR + "unsupported fix format from the framebuffer.\n"); + return -EINVAL; + } + + offset = cam->v4l2_fb.fmt.bytesperline * cam->win.w.top + + size * cam->win.w.left; + + if (cam->v4l2_fb.base == 0) { + printk(KERN_ERR "invalid frame buffer address.\n"); + } else { + offset += (u32) cam->v4l2_fb.base; + } + + memset(&vf, 0, sizeof(ipu_channel_params_t)); + ipu_csi_get_window_size(&vf.csi_prp_vf_mem.in_width, + &vf.csi_prp_vf_mem.in_height, cam->csi); + vf.csi_prp_vf_mem.in_pixel_fmt = IPU_PIX_FMT_UYVY; + vf.csi_prp_vf_mem.out_width = cam->win.w.width; + vf.csi_prp_vf_mem.out_height = cam->win.w.height; + vf.csi_prp_vf_mem.csi = cam->csi; + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + vf.csi_prp_vf_mem.out_width = cam->win.w.height; + vf.csi_prp_vf_mem.out_height = cam->win.w.width; + } + vf.csi_prp_vf_mem.out_pixel_fmt = format; + size = cam->win.w.width * cam->win.w.height * size; + + err = ipu_init_channel(CSI_PRP_VF_MEM, &vf); + if (err != 0) + goto out_4; + + ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, true, true); + + if (cam->vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->vf_bufs_size[0], + cam->vf_bufs_vaddr[0], cam->vf_bufs[0]); + } + if (cam->vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->vf_bufs_size[1], + cam->vf_bufs_vaddr[1], cam->vf_bufs[1]); + } + cam->vf_bufs_size[0] = PAGE_ALIGN(size); + cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0, + cam->vf_bufs_size[0], + &cam->vf_bufs[0], + GFP_DMA | + GFP_KERNEL); + if (cam->vf_bufs_vaddr[0] == NULL) { + printk(KERN_ERR "Error to allocate vf buffer\n"); + err = -ENOMEM; + goto out_3; + } + cam->vf_bufs_size[1] = PAGE_ALIGN(size); + cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0, + cam->vf_bufs_size[1], + &cam->vf_bufs[1], + GFP_DMA | + GFP_KERNEL); + if (cam->vf_bufs_vaddr[1] == NULL) { + printk(KERN_ERR "Error to allocate vf buffer\n"); + err = -ENOMEM; + goto out_3; + } + + err = ipu_init_channel_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, + format, vf.csi_prp_vf_mem.out_width, + vf.csi_prp_vf_mem.out_height, + vf.csi_prp_vf_mem.out_width, + IPU_ROTATE_NONE, cam->vf_bufs[0], + cam->vf_bufs[1], 0, 0); + if (err != 0) { + printk(KERN_ERR "Error initializing CSI_PRP_VF_MEM\n"); + goto out_3; + } + err = ipu_init_channel(MEM_ROT_VF_MEM, NULL); + if (err != 0) { + printk(KERN_ERR "Error MEM_ROT_VF_MEM channel\n"); + goto out_3; + } + + err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_INPUT_BUFFER, + format, vf.csi_prp_vf_mem.out_width, + vf.csi_prp_vf_mem.out_height, + vf.csi_prp_vf_mem.out_width, + cam->rotation, cam->vf_bufs[0], + cam->vf_bufs[1], 0, 0); + if (err != 0) { + printk(KERN_ERR "Error MEM_ROT_VF_MEM input buffer\n"); + goto out_2; + } + + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, + format, + vf.csi_prp_vf_mem.out_height, + vf.csi_prp_vf_mem.out_width, + cam->overlay_fb->var.xres * bpp, + IPU_ROTATE_NONE, offset, 0, 0, 0); + + if (err != 0) { + printk(KERN_ERR "Error MEM_ROT_VF_MEM output buffer\n"); + goto out_2; + } + } else { + err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, + format, + vf.csi_prp_vf_mem.out_width, + vf.csi_prp_vf_mem.out_height, + cam->overlay_fb->var.xres * bpp, + IPU_ROTATE_NONE, offset, 0, 0, 0); + if (err != 0) { + printk(KERN_ERR "Error MEM_ROT_VF_MEM output buffer\n"); + goto out_2; + } + } + + err = ipu_request_irq(IPU_IRQ_PRP_VF_OUT_EOF, prpvf_vf_eof_callback, + 0, "Mxc Camera", cam); + if (err != 0) { + printk(KERN_ERR + "Error registering IPU_IRQ_PRP_VF_OUT_EOF irq.\n"); + goto out_2; + } + + err = ipu_request_irq(IPU_IRQ_BG_SF_END, prpvf_sdc_vsync_callback, + 0, "Mxc Camera", NULL); + if (err != 0) { + printk(KERN_ERR "Error registering IPU_IRQ_BG_SF_END irq.\n"); + goto out_1; + } + + ipu_enable_channel(CSI_PRP_VF_MEM); + ipu_enable_channel(MEM_ROT_VF_MEM); + + buffer_num = 0; + buffer_ready = 0; + ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 0); + + cam->overlay_active = true; + return err; + + out_1: + ipu_free_irq(IPU_IRQ_PRP_VF_OUT_EOF, NULL); + out_2: + ipu_uninit_channel(MEM_ROT_VF_MEM); + out_3: + ipu_uninit_channel(CSI_PRP_VF_MEM); + out_4: + if (cam->vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->vf_bufs_size[0], + cam->vf_bufs_vaddr[0], cam->vf_bufs[0]); + cam->vf_bufs_vaddr[0] = NULL; + cam->vf_bufs[0] = 0; + } + if (cam->vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->vf_bufs_size[1], + cam->vf_bufs_vaddr[1], cam->vf_bufs[1]); + cam->vf_bufs_vaddr[1] = NULL; + cam->vf_bufs[1] = 0; + } + if (cam->rot_vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->rot_vf_buf_size[0], + cam->rot_vf_bufs_vaddr[0], + cam->rot_vf_bufs[0]); + cam->rot_vf_bufs_vaddr[0] = NULL; + cam->rot_vf_bufs[0] = 0; + } + if (cam->rot_vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->rot_vf_buf_size[1], + cam->rot_vf_bufs_vaddr[1], + cam->rot_vf_bufs[1]); + cam->rot_vf_bufs_vaddr[1] = NULL; + cam->rot_vf_bufs[1] = 0; + } + return err; +} + +/*! + * prpvf_stop - stop the vf task + * + * @param private cam_data * mxc v4l2 main structure + * + */ +static int prpvf_stop(void *private) +{ + cam_data *cam = (cam_data *) private; + + if (cam->overlay_active == false) + return 0; + + ipu_free_irq(IPU_IRQ_BG_SF_END, NULL); + + ipu_free_irq(IPU_IRQ_PRP_VF_OUT_EOF, cam); + + ipu_disable_channel(CSI_PRP_VF_MEM, true); + ipu_disable_channel(MEM_ROT_VF_MEM, true); + ipu_uninit_channel(CSI_PRP_VF_MEM); + ipu_uninit_channel(MEM_ROT_VF_MEM); + ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, false, false); + + if (cam->vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->vf_bufs_size[0], + cam->vf_bufs_vaddr[0], cam->vf_bufs[0]); + cam->vf_bufs_vaddr[0] = NULL; + cam->vf_bufs[0] = 0; + } + if (cam->vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->vf_bufs_size[1], + cam->vf_bufs_vaddr[1], cam->vf_bufs[1]); + cam->vf_bufs_vaddr[1] = NULL; + cam->vf_bufs[1] = 0; + } + if (cam->rot_vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->rot_vf_buf_size[0], + cam->rot_vf_bufs_vaddr[0], + cam->rot_vf_bufs[0]); + cam->rot_vf_bufs_vaddr[0] = NULL; + cam->rot_vf_bufs[0] = 0; + } + if (cam->rot_vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->rot_vf_buf_size[1], + cam->rot_vf_bufs_vaddr[1], + cam->rot_vf_bufs[1]); + cam->rot_vf_bufs_vaddr[1] = NULL; + cam->rot_vf_bufs[1] = 0; + } + + buffer_num = 0; + buffer_ready = 0; + cam->overlay_active = false; + return 0; +} + +/*! + * function to select PRP-VF as the working path + * + * @param private cam_data * mxc v4l2 main structure + * + * @return status + */ +int prp_vf_sdc_select_bg(void *private) +{ + cam_data *cam = (cam_data *) private; + + if (cam) { + cam->vf_start_sdc = prpvf_start; + cam->vf_stop_sdc = prpvf_stop; + cam->overlay_active = false; + } + + return 0; +} + +/*! + * function to de-select PRP-VF as the working path + * + * @param private cam_data * mxc v4l2 main structure + * + * @return status + */ +int prp_vf_sdc_deselect_bg(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + err = prpvf_stop(private); + + if (cam) { + cam->vf_start_sdc = NULL; + cam->vf_stop_sdc = NULL; + } + return err; +} + +/*! + * Init viewfinder task. + * + * @return Error code indicating success or failure + */ +__init int prp_vf_sdc_init_bg(void) +{ + return 0; +} + +/*! + * Deinit viewfinder task. + * + * @return Error code indicating success or failure + */ +void __exit prp_vf_sdc_exit_bg(void) +{ +} + +module_init(prp_vf_sdc_init_bg); +module_exit(prp_vf_sdc_exit_bg); + +EXPORT_SYMBOL(prp_vf_sdc_select_bg); +EXPORT_SYMBOL(prp_vf_sdc_deselect_bg); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("IPU PRP VF SDC Backgroud Driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/media/video/mxc/capture/ipu_still.c linux-2.6.26-lab126/drivers/media/video/mxc/capture/ipu_still.c --- linux-2.6.26/drivers/media/video/mxc/capture/ipu_still.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/ipu_still.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,250 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_still.c + * + * @brief IPU Use case for still image capture + * + * @ingroup IPU + */ + +#include +#include +#include "mxc_v4l2_capture.h" +#include "ipu_prp_sw.h" + +static int callback_eof_flag; + +#ifdef CONFIG_MXC_IPU_V1 +static int callback_flag; +/* + * Function definitions + */ +/*! + * CSI EOF callback function. + * + * @param irq int irq line + * @param dev_id void * device id + * + * @return status IRQ_HANDLED for handled + */ +static irqreturn_t prp_csi_eof_callback(int irq, void *dev_id) +{ + if (callback_flag == 2) { + ipu_select_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_enable_channel(CSI_MEM); + } + + callback_flag++; + return IRQ_HANDLED; +} +#endif + +/*! + * CSI callback function. + * + * @param irq int irq line + * @param dev_id void * device id + * + * @return status IRQ_HANDLED for handled + */ +static irqreturn_t prp_still_callback(int irq, void *dev_id) +{ + cam_data *cam = (cam_data *) dev_id; + + callback_eof_flag++; + if (callback_eof_flag < 5) + ipu_select_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, 0); + else { + cam->still_counter++; + wake_up_interruptible(&cam->still_queue); + } + + return IRQ_HANDLED; +} + +/*! + * start csi->mem task + * @param private struct cam_data * mxc capture instance + * + * @return status + */ +static int prp_still_start(void *private) +{ + cam_data *cam = (cam_data *) private; + u32 pixel_fmt; + int err; + ipu_channel_params_t params; + + if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) + pixel_fmt = IPU_PIX_FMT_YUV420P; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P) + pixel_fmt = IPU_PIX_FMT_YUV422P; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY) + pixel_fmt = IPU_PIX_FMT_UYVY; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR24) + pixel_fmt = IPU_PIX_FMT_BGR24; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24) + pixel_fmt = IPU_PIX_FMT_RGB24; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565) + pixel_fmt = IPU_PIX_FMT_RGB565; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR32) + pixel_fmt = IPU_PIX_FMT_BGR32; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB32) + pixel_fmt = IPU_PIX_FMT_RGB32; + else { + printk(KERN_ERR "format not supported\n"); + return -EINVAL; + } + + ipu_csi_enable_mclk_if(CSI_MCLK_RAW, cam->csi, true, true); + + memset(¶ms, 0, sizeof(params)); + err = ipu_init_channel(CSI_MEM, ¶ms); + if (err != 0) + return err; + + err = ipu_init_channel_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, + pixel_fmt, cam->v2f.fmt.pix.width, + cam->v2f.fmt.pix.height, + cam->v2f.fmt.pix.width, IPU_ROTATE_NONE, + cam->still_buf, 0, 0, 0); + if (err != 0) + return err; + +#ifdef CONFIG_MXC_IPU_V1 + err = ipu_request_irq(IPU_IRQ_SENSOR_OUT_EOF, prp_still_callback, + 0, "Mxc Camera", cam); + if (err != 0) { + printk(KERN_ERR "Error registering irq.\n"); + return err; + } + callback_flag = 0; + callback_eof_flag = 0; + err = ipu_request_irq(IPU_IRQ_SENSOR_EOF, prp_csi_eof_callback, + 0, "Mxc Camera", NULL); + if (err != 0) { + printk(KERN_ERR "Error IPU_IRQ_SENSOR_EOF \n"); + return err; + } +#else + err = ipu_request_irq(IPU_IRQ_CSI0_OUT_EOF, prp_still_callback, + 0, "Mxc Camera", cam); + if (err != 0) { + printk(KERN_ERR "Error registering irq.\n"); + return err; + } + + callback_eof_flag = 0; + + ipu_select_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_enable_channel(CSI_MEM); +#endif + + return err; +} + +/*! + * stop csi->mem encoder task + * @param private struct cam_data * mxc capture instance + * + * @return status + */ +static int prp_still_stop(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + +#ifdef CONFIG_MXC_IPU_V1 + ipu_free_irq(IPU_IRQ_SENSOR_EOF, NULL); + ipu_free_irq(IPU_IRQ_SENSOR_OUT_EOF, cam); +#else + ipu_free_irq(IPU_IRQ_CSI0_OUT_EOF, cam); +#endif + + ipu_disable_channel(CSI_MEM, true); + ipu_uninit_channel(CSI_MEM); + ipu_csi_enable_mclk_if(CSI_MCLK_RAW, cam->csi, false, false); + + return err; +} + +/*! + * function to select CSI_MEM as the working path + * + * @param private struct cam_data * mxc capture instance + * + * @return status + */ +int prp_still_select(void *private) +{ + cam_data *cam = (cam_data *) private; + + if (cam) { + cam->csi_start = prp_still_start; + cam->csi_stop = prp_still_stop; + } + + return 0; +} + +/*! + * function to de-select CSI_MEM as the working path + * + * @param private struct cam_data * mxc capture instance + * + * @return status + */ +int prp_still_deselect(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + + err = prp_still_stop(cam); + + if (cam) { + cam->csi_start = NULL; + cam->csi_stop = NULL; + } + + return err; +} + +/*! + * Init the Encorder channels + * + * @return Error code indicating success or failure + */ +__init int prp_still_init(void) +{ + return 0; +} + +/*! + * Deinit the Encorder channels + * + */ +void __exit prp_still_exit(void) +{ +} + +module_init(prp_still_init); +module_exit(prp_still_exit); + +EXPORT_SYMBOL(prp_still_select); +EXPORT_SYMBOL(prp_still_deselect); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("IPU PRP STILL IMAGE Driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/media/video/mxc/capture/mc521da.c linux-2.6.26-lab126/drivers/media/video/mxc/capture/mc521da.c --- linux-2.6.26/drivers/media/video/mxc/capture/mc521da.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/mc521da.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,648 @@ +/* + * Copyright 2006-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc521da.c + * + * @brief MC521DA camera driver functions + * + * @ingroup Camera + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_v4l2_capture.h" + +#define MC521DA_I2C_ADDRESS 0x22 +#define MC521DA_TERM 0xFF + +typedef struct { + u16 width; + u16 height; +} mc521da_image_format; + +struct mc521da_reg { + u8 reg; + u8 val; +}; + +static sensor_interface *interface_param = NULL; + +static mc521da_image_format format[2] = { + { + .width = 1600, + .height = 1200, + }, + { + .width = 640, + .height = 480, + }, +}; + +const static struct mc521da_reg mc521da_initial[] = { + /*---------------------------------------------------------- + * Sensor Setting Start + *---------------------------------------------------------- + */ + {0xff, 0x01}, /* Sensor setting start */ + {0x01, 0x10}, /* Wavetable script, generated by waveman */ + {0x10, 0x64}, + {0x03, 0x00}, {0x04, 0x06}, {0x05, 0x30}, {0x06, 0x02}, {0x08, 0x00}, + {0x03, 0x01}, {0x04, 0x41}, {0x05, 0x70}, {0x06, 0x03}, {0x08, 0x00}, + {0x03, 0x02}, {0x04, 0x55}, {0x05, 0x30}, {0x06, 0x03}, {0x08, 0x00}, + {0x03, 0x03}, {0x04, 0x5A}, {0x05, 0x30}, {0x06, 0x02}, {0x08, 0x00}, + {0x03, 0x04}, {0x04, 0x7A}, {0x05, 0x30}, {0x06, 0x06}, {0x08, 0x00}, + {0x03, 0x05}, {0x04, 0x9C}, {0x05, 0x30}, {0x06, 0x0F}, {0x08, 0x00}, + {0x03, 0x06}, {0x04, 0x73}, {0x05, 0x31}, {0x06, 0x06}, {0x08, 0x00}, + {0x03, 0x07}, {0x04, 0x2D}, {0x05, 0x3B}, {0x06, 0x06}, {0x08, 0x00}, + {0x03, 0x08}, {0x04, 0x32}, {0x05, 0x33}, {0x06, 0x06}, {0x08, 0x00}, + {0x03, 0x09}, {0x04, 0x67}, {0x05, 0x63}, {0x06, 0x06}, {0x08, 0x00}, + {0x03, 0x0a}, {0x04, 0x6C}, {0x05, 0x23}, {0x06, 0x0E}, {0x08, 0x00}, + {0x03, 0x0b}, {0x04, 0x71}, {0x05, 0x23}, {0x06, 0x06}, {0x08, 0x00}, + {0x03, 0x0c}, {0x04, 0x30}, {0x05, 0x2F}, {0x06, 0x06}, {0x08, 0x00}, + {0x03, 0x0d}, {0x04, 0x00}, {0x05, 0x00}, {0x06, 0x06}, {0x08, 0x00}, + {0x07, 0x0e}, + + /* Start Address */ + {0x10, 0x64}, {0x14, 0x10}, {0x15, 0x00}, + + /* SYNC */ + {0x18, 0x40}, {0x19, 0x00}, {0x1A, 0x03}, {0x1B, 0x00}, + + /* X-Y Mirror */ + {0x11, 0x00}, {0xda, 0x00}, /* X mirror OFF, Y Mirror OFF */ + + /* Frame height */ + {0x1c, 0x13}, {0x1d, 0x04}, {0x0e, 0x4b}, {0x0f, 0x05}, + {0x9e, 0x04}, {0x9d, 0xc6}, {0xcc, 0x14}, {0xcd, 0x05}, + + /* Frame width */ + {0x0c, 0x35}, {0x0d, 0x07}, {0x9b, 0x10}, {0x9c, 0x07}, + {0x93, 0x21}, + + {0x01, 0x01}, {0x40, 0x00}, {0x41, 0x00}, {0x42, 0xf0}, + {0x43, 0x03}, {0x44, 0x0a}, {0x45, 0x00}, {0x3b, 0x40}, + {0x38, 0x18}, {0x3c, 0x00}, {0x20, 0x00}, {0x21, 0x01}, + {0x22, 0x00}, {0x23, 0x01}, {0x24, 0x00}, {0x25, 0x01}, + {0x26, 0x00}, {0x27, 0x01}, {0xb9, 0x04}, {0xb8, 0xc3}, + {0xbb, 0x04}, {0xba, 0xc3}, {0xbf, 0x04}, {0xbe, 0xc3}, + + /* Ramp */ + {0x57, 0x07}, {0x56, 0xd6}, {0x55, 0x03}, {0x54, 0x74}, + {0x9f, 0x99}, {0x94, 0x80}, {0x91, 0x78}, {0x92, 0x8b}, + + /* Output Mode */ + {0x52, 0x10}, {0x51, 0x00}, + + /* Analog Gain and Output driver */ + {0x28, 0x00}, {0xdd, 0x82}, {0xdb, 0x00}, {0xdc, 0x00}, + + /* Update */ + {0x00, 0x84}, + + /* PLL ADC clock = 75 MHz */ + {0xb5, 0x60}, {0xb4, 0x02}, {0xb5, 0x20}, + + /*----------------------------------------------*/ + /* ISP Setting Start */ + /*----------------------------------------------*/ + {0xff, 0x02}, + {0x01, 0xbd}, {0x02, 0xf8}, {0x03, 0x3a}, {0x04, 0x00}, {0x0e, 0x00}, + + /* Output mode */ + {0x88, 0x00}, {0x87, 0x11}, + + /* Threshold */ + {0xb6, 0x1b}, {0x0d, 0xc0}, {0x24, 0x00}, {0x25, 0x00}, {0x26, 0x00}, + + /* Image Effect */ + {0x3f, 0x80}, {0x40, 0x00}, {0x41, 0x00}, {0x42, 0x80}, {0x43, 0x00}, + {0x44, 0x00}, {0x45, 0x00}, {0x46, 0x00}, {0x56, 0x80}, {0x57, 0x20}, + {0x58, 0x20}, {0x59, 0x02}, {0x5a, 0x00}, {0x5b, 0x78}, {0x5c, 0x7c}, + {0x5d, 0x84}, {0x5e, 0x85}, {0x5f, 0x78}, {0x60, 0x7e}, {0x61, 0x82}, + {0x62, 0x85}, {0x63, 0x00}, {0x64, 0x80}, {0x65, 0x00}, {0x66, 0x80}, + {0x67, 0x80}, {0x68, 0x80}, + + /* Auto Focus */ + {0x6e, 0x02}, {0x6f, 0xe5}, {0x70, 0x08}, {0x71, 0x01}, {0x72, 0x00}, + + /* Decimator */ + {0x78, 0xff}, {0x79, 0xff}, {0x7a, 0x70}, {0x7b, 0x00}, {0x7c, 0x00}, + {0x7d, 0x00}, {0x7e, 0xc8}, {0x7f, 0xc8}, {0x80, 0x96}, {0x81, 0x96}, + {0x82, 0x00}, {0x83, 0x00}, {0x84, 0x00}, {0x85, 0x00}, {0x86, 0x00}, + + /* Luminance Info */ + {0xf9, 0x20}, {0xb7, 0x7f}, {0xb8, 0x28}, {0xb9, 0x08}, + {0xf9, 0xa0}, {0xb7, 0x10}, {0xb9, 0x00}, + {0xf9, 0x40}, {0xb7, 0x7f}, {0xb8, 0x28}, {0xb9, 0x08}, + {0xf9, 0xc0}, {0xb7, 0x08}, {0xb9, 0x00}, + {0xf9, 0x60}, {0xb7, 0x7f}, {0xb8, 0x28}, {0xb9, 0x08}, + {0xf9, 0xe0}, {0xb7, 0x05}, {0xb9, 0x00}, + {0xf9, 0x00}, {0xb7, 0x03}, {0xb8, 0x2d}, {0xb9, 0xcd}, + {0xf9, 0x80}, {0xb7, 0x02}, {0xb9, 0x00}, + + /* AE */ + {0x8a, 0x00}, {0x89, 0xc0}, {0x8c, 0x32}, {0x8d, 0x96}, {0x8e, 0x25}, + {0x8f, 0x70}, {0x90, 0x12}, {0x91, 0x41}, {0x9e, 0x2e}, {0x9f, 0x2e}, + {0xa0, 0x0b}, {0xa1, 0x71}, {0xa2, 0xb0}, {0xa3, 0x09}, {0xa4, 0x89}, + {0xa5, 0x68}, {0xa6, 0x1a}, {0xa7, 0xb3}, {0xa8, 0xf0}, {0xa9, 0x19}, + {0xaa, 0x6a}, {0xab, 0x6b}, {0xac, 0x01}, {0xad, 0xe8}, {0xae, 0x48}, + {0xaf, 0x01}, {0xb0, 0x96}, {0xb1, 0xe6}, {0xb2, 0x03}, {0xb3, 0x00}, + {0xb4, 0x10}, {0xb5, 0x00}, {0xb6, 0x04}, {0xba, 0x44}, {0xbb, 0x3a}, + {0xbc, 0x01}, {0xbd, 0x08}, {0xbe, 0xa0}, {0xbf, 0x01}, {0xc0, 0x82}, + {0x8a, 0xe1}, {0x8b, 0x8c}, + + /* AWB */ + {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x40}, {0xcb, 0xB0}, {0xcc, 0x40}, + {0xcd, 0xff}, {0xce, 0x19}, {0xcf, 0x40}, {0xd0, 0x01}, {0xd1, 0x43}, + {0xd2, 0x80}, {0xd3, 0x80}, {0xd4, 0xf1}, {0xdf, 0x00}, {0xe0, 0x8f}, + {0xe1, 0x8f}, {0xe2, 0x53}, {0xe3, 0x97}, {0xe4, 0x1f}, {0xe5, 0x3b}, + {0xe6, 0x9c}, {0xe7, 0x2e}, {0xe8, 0x03}, {0xe9, 0x02}, + + /* Neutral CCM */ + {0xfa, 0x00}, {0xd5, 0x3f}, {0xd6, 0x8c}, {0xd7, 0x43}, {0xd8, 0x08}, + {0xd9, 0x27}, {0xda, 0x7e}, {0xdb, 0x17}, {0xdc, 0x1a}, {0xdd, 0x47}, + {0xde, 0xa1}, + + /* Blue CCM */ + {0xfa, 0x01}, {0xd5, 0x3f}, {0xd6, 0x77}, {0xd7, 0x34}, {0xd8, 0x03}, + {0xd9, 0x18}, {0xda, 0x6e}, {0xdb, 0x16}, {0xdc, 0x0f}, {0xdd, 0x29}, + {0xde, 0x77}, + + /* Red CCM */ + {0xfa, 0x02}, {0xd5, 0x3f}, {0xd6, 0x7d}, {0xd7, 0x2f}, {0xd8, 0x0e}, + {0xd9, 0x1e}, {0xda, 0x76}, {0xdb, 0x18}, {0xdc, 0x29}, {0xdd, 0x51}, + {0xde, 0xba}, + + /* AWB */ + {0xea, 0x00}, {0xeb, 0x1a}, {0xc8, 0x33}, {0xc9, 0xc2}, + + {0xed, 0x02}, {0xee, 0x02}, + + /* AFD */ + {0xf0, 0x11}, {0xf1, 0x03}, {0xf2, 0x05}, {0xf5, 0x05}, {0xf6, 0x32}, + {0xf7, 0x32}, + + /* Lens Shading */ + {0xf9, 0x00}, {0x05, 0x04}, {0x06, 0xff}, {0x07, 0xf2}, {0x08, 0x00}, + {0x09, 0x00}, {0x0a, 0xf2}, {0x0b, 0xff}, {0x0c, 0xff}, + {0xf9, 0x01}, {0x05, 0x04}, {0x06, 0xff}, {0x07, 0x8b}, {0x08, 0x16}, + {0x09, 0x16}, {0x0a, 0x8b}, {0x0b, 0xff}, {0x0c, 0xe0}, + {0xf9, 0x02}, {0x05, 0x04}, {0x06, 0xff}, {0x07, 0x8b}, {0x08, 0x16}, + {0x09, 0x16}, {0x0a, 0x8b}, {0x0b, 0xff}, {0x0c, 0xe0}, + {0xf9, 0x03}, {0x05, 0x04}, {0x06, 0xff}, {0x07, 0x7c}, {0x08, 0x26}, + {0x09, 0x26}, {0x0a, 0x7c}, {0x0b, 0xd0}, {0x0c, 0xe0}, + {0xf9, 0x04}, {0x05, 0x0d}, {0x06, 0x40}, {0x07, 0xa0}, {0x08, 0x00}, + {0x09, 0x00}, {0x0a, 0xa0}, {0x0b, 0x40}, {0x0c, 0xe0}, + {0xf9, 0x05}, {0x05, 0x0d}, {0x06, 0x40}, {0x07, 0xa0}, {0x08, 0x00}, + {0x09, 0x00}, {0x0a, 0xa0}, {0x0b, 0x40}, {0x0c, 0xa0}, + {0xf9, 0x06}, {0x05, 0x0d}, {0x06, 0x40}, {0x07, 0xa0}, {0x08, 0x00}, + {0x09, 0x00}, {0x0a, 0xa0}, {0x0b, 0x40}, {0x0c, 0xa0}, + {0xf9, 0x07}, {0x05, 0x0d}, {0x06, 0x40}, {0x07, 0xa0}, {0x08, 0x00}, + {0x09, 0x00}, {0x0a, 0xa0}, {0x0b, 0x40}, {0x0c, 0xa0}, + + /* Edge setting */ + {0x73, 0x68}, {0x74, 0x40}, {0x75, 0x00}, {0x76, 0xff}, {0x77, 0x80}, + {0x4f, 0x80}, {0x50, 0x82}, {0x51, 0x82}, {0x52, 0x08}, + + /* Interpolation Setting */ + {0x23, 0x7f}, {0x22, 0x08}, {0x18, 0xff}, {0x19, 0x00}, + {0x40, 0x00}, {0x53, 0xff}, {0x54, 0x0a}, {0x55, 0xc2}, + {0x1b, 0x18}, + + {0xfa, 0x00}, {0x15, 0x0c}, {0x22, 0x00}, {0x0e, 0xef}, {0x1f, 0x1d}, + {0x20, 0x2d}, {0x1c, 0x01}, {0x1d, 0x02}, {0x1e, 0x03}, {0x0e, 0xee}, + {0x12, 0x10}, {0x16, 0x10}, {0x17, 0x02}, {0x1a, 0x01}, + {0xfa, 0x04}, {0x0e, 0xef}, {0x1c, 0x01}, {0x1d, 0x02}, {0x1e, 0x03}, + {0x1f, 0x11}, {0x20, 0x11}, {0x0e, 0xee}, {0x12, 0x03}, {0x16, 0x10}, + {0x17, 0x02}, {0x1a, 0xee}, + {0xfa, 0x08}, {0x0e, 0xef}, {0x1c, 0x01}, {0x1d, 0x02}, {0x1e, 0x03}, + {0x1f, 0x00}, {0x20, 0x00}, {0x0e, 0xee}, {0x12, 0x03}, {0x16, 0x10}, + {0x17, 0x02}, {0x1a, 0x22}, + + /* Gamma Correction */ + {0x27, 0x62}, {0x28, 0x00}, {0x27, 0x62}, {0x28, 0x00}, {0x29, 0x00}, + {0x2a, 0x00}, {0x2f, 0x03}, {0x30, 0x10}, {0x31, 0x2b}, {0x32, 0x50}, + {0x33, 0x70}, {0x34, 0x90}, {0x35, 0xB0}, {0x36, 0xD0}, {0x37, 0x00}, + {0x38, 0x18}, {0x39, 0x57}, {0x3a, 0x89}, {0x3b, 0xac}, {0x3c, 0xc9}, + {0x3d, 0xde}, {0x3e, 0xef}, {0x2b, 0x00}, {0x2c, 0x00}, {0x2d, 0x40}, + {0x2e, 0xab}, + + /* Contrast */ + {0x47, 0x10}, {0x48, 0x1f}, {0x49, 0xe3}, {0x4a, 0xf0}, {0x4b, 0x08}, + {0x4c, 0x14}, {0x4d, 0xe9}, {0x4e, 0xf5}, {0x98, 0x8a}, + + {0xfa, 0x00}, + {MC521DA_TERM, MC521DA_TERM} +}; + +static int mc521da_attach(struct i2c_adapter *adapter); +static int mc521da_detach(struct i2c_client *client); + +static struct i2c_driver mc521da_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "MC521DA Client", + }, + .attach_adapter = mc521da_attach, + .detach_client = mc521da_detach, +}; + +static struct i2c_client mc521da_i2c_client = { + .name = "MC521DA I2C dev", + .addr = MC521DA_I2C_ADDRESS, + .driver = &mc521da_i2c_driver, +}; + +static inline int mc521da_read_reg(u8 reg) +{ + return i2c_smbus_read_byte_data(&mc521da_i2c_client, reg); +} + +static inline int mc521da_write_reg(u8 reg, u8 val) +{ + return i2c_smbus_write_byte_data(&mc521da_i2c_client, reg, val); +} + +static int mc521da_write_regs(const struct mc521da_reg reglist[]) +{ + int err; + const struct mc521da_reg *next = reglist; + + while (!((next->reg == MC521DA_TERM) && (next->val == MC521DA_TERM))) { + err = mc521da_write_reg(next->reg, next->val); + if (err) { + return err; + } + next++; + } + return 0; +} + +/*! + * mc521da sensor downscale function + * @param downscale bool + * @return Error code indicating success or failure + */ +static u8 mc521da_sensor_downscale(bool downscale) +{ + u8 data; + u32 i = 0; + + if (downscale == true) { + // VGA + mc521da_write_reg(0xff, 0x01); + + mc521da_write_reg(0x52, 0x30); + mc521da_write_reg(0x51, 0x00); + + mc521da_write_reg(0xda, 0x01); + mc521da_write_reg(0x00, 0x8C); + + /* Wait for changes to take effect */ + while (i < 256) { + i++; + data = mc521da_read_reg(0x00); + if ((data & 0x80) == 0) + break; + msleep(5); + } + + /* ISP */ + mc521da_write_reg(0xff, 0x02); + + mc521da_write_reg(0x03, 0x3b); /* Enable Decimator */ + + mc521da_write_reg(0x7a, 0x74); + mc521da_write_reg(0x7b, 0x01); + mc521da_write_reg(0x7e, 0x50); + mc521da_write_reg(0x7f, 0x50); + mc521da_write_reg(0x80, 0x3c); + mc521da_write_reg(0x81, 0x3c); + } else { + //UXGA + mc521da_write_reg(0xff, 0x01); + mc521da_write_reg(0x52, 0x10); + mc521da_write_reg(0x51, 0x00); + mc521da_write_reg(0xda, 0x00); + + /* update */ + mc521da_write_reg(0x00, 0x84); + + /* Wait for changes to take effect */ + while (i < 256) { + i++; + data = mc521da_read_reg(0x00); + if ((data & 0x80) == 0) + break; + msleep(5); + } + + /* ISP */ + mc521da_write_reg(0xff, 0x02); + + mc521da_write_reg(0x03, 0x3a); + + mc521da_write_reg(0x7a, 0x70); + mc521da_write_reg(0x7b, 0x00); + mc521da_write_reg(0x7e, 0xc8); + mc521da_write_reg(0x7f, 0xc8); + mc521da_write_reg(0x80, 0x96); + mc521da_write_reg(0x81, 0x96); + } + + return 0; +} + +/*! + * mc521da sensor interface Initialization + * @param param sensor_interface * + * @param width u32 + * @param height u32 + * @return None + */ +static void mc521da_interface(sensor_interface * param, u32 width, u32 height) +{ + param->clk_mode = 0x0; //gated + param->pixclk_pol = 0x0; + param->data_width = 0x1; + param->data_pol = 0x0; + param->ext_vsync = 0x0; + param->Vsync_pol = 0x0; + param->Hsync_pol = 0x0; + param->width = width - 1; + param->height = height - 1; + param->active_width = width; + param->active_height = height; + param->pixel_fmt = IPU_PIX_FMT_UYVY; +} + +extern void gpio_sensor_reset(bool flag); + +/*! + * mc521da Reset function + * + * @return None + */ +static sensor_interface *mc521da_reset(void) +{ + if (interface_param == NULL) + return NULL; + + mc521da_interface(interface_param, format[1].width, format[1].height); + set_mclk_rate(&interface_param->mclk); + + gpio_sensor_reset(true); + msleep(10); + gpio_sensor_reset(false); + msleep(50); + + return interface_param; +} + +/*! + * mc521da sensor configuration + * + * @param frame_rate int * + * @param high_quality int + * @return sensor_interface * + */ +static sensor_interface *mc521da_config(int *frame_rate, int high_quality) +{ + int num_clock_per_row, err; + int max_rate = 0; + int index = 1; + u16 frame_height; + + if (high_quality == 1) + index = 0; + + err = mc521da_write_regs(mc521da_initial); + if (err) { + /* Reduce the MCLK */ + interface_param->mclk = 20000000; + mc521da_reset(); + + printk(KERN_INFO "mc521da: mclk reduced\n"); + mc521da_write_regs(mc521da_initial); + } + + mc521da_interface(interface_param, format[index].width, + format[index].height); + + if (index == 0) { + mc521da_sensor_downscale(false); + } else { + mc521da_sensor_downscale(true); + } + + num_clock_per_row = 1845; + max_rate = interface_param->mclk * 3 * (index + 1) + / (2 * num_clock_per_row * 1300); + + if ((*frame_rate > max_rate) || (*frame_rate == 0)) { + *frame_rate = max_rate; + } + + frame_height = 1300 * max_rate / (*frame_rate); + + *frame_rate = interface_param->mclk * 3 * (index + 1) + / (2 * num_clock_per_row * frame_height); + + mc521da_write_reg(0xff, 0x01); + mc521da_write_reg(0xE, frame_height & 0xFF); + mc521da_write_reg(0xF, (frame_height & 0xFF00) >> 8); + mc521da_write_reg(0xCC, frame_height & 0xFF); + mc521da_write_reg(0xCD, (frame_height & 0xFF00) >> 8); + + return interface_param; +} + +/*! + * mc521da sensor set color configuration + * + * @param bright int + * @param saturation int + * @param red int + * @param green int + * @param blue int + * @return None + */ +static void +mc521da_set_color(int bright, int saturation, int red, int green, int blue) +{ + /* Select ISP */ + mc521da_write_reg(0xff, 0x02); + + mc521da_write_reg(0x41, bright); + mc521da_write_reg(0xca, red); + mc521da_write_reg(0xcb, green); + mc521da_write_reg(0xcc, blue); +} + +/*! + * mc521da sensor get color configuration + * + * @param bright int * + * @param saturation int * + * @param red int * + * @param green int * + * @param blue int * + * @return None + */ +static void +mc521da_get_color(int *bright, int *saturation, int *red, int *green, int *blue) +{ + *saturation = 0; + + /* Select ISP */ + mc521da_write_reg(0xff, 0x02); + + *bright = mc521da_read_reg(0x41); + *red = mc521da_read_reg(0xCA); + *green = mc521da_read_reg(0xCB); + *blue = mc521da_read_reg(0xCC); +} + +struct camera_sensor camera_sensor_if = { + set_color:mc521da_set_color, + get_color:mc521da_get_color, + config:mc521da_config, + reset:mc521da_reset, +}; + +/*! + * mc521da I2C detect_client function + * + * @param adapter struct i2c_adapter * + * @param address int + * @param kind int + * + * @return Error code indicating success or failure + */ +static int mc521da_detect_client(struct i2c_adapter *adapter, int address, + int kind) +{ + mc521da_i2c_client.adapter = adapter; + if (i2c_attach_client(&mc521da_i2c_client)) { + mc521da_i2c_client.adapter = NULL; + printk(KERN_ERR "mc521da_attach: i2c_attach_client failed\n"); + return -1; + } + + interface_param = (sensor_interface *) + kmalloc(sizeof(sensor_interface), GFP_KERNEL); + if (!interface_param) { + printk(KERN_ERR "mc521da_attach: kmalloc failed \n"); + return -1; + } + + interface_param->mclk = 25000000; + + printk(KERN_INFO "mc521da Detected\n"); + + return 0; +} + +static unsigned short normal_i2c[] = { MC521DA_I2C_ADDRESS, I2C_CLIENT_END }; + +/* Magic definition of all other variables and things */ +I2C_CLIENT_INSMOD; + +static int mc521da_attach(struct i2c_adapter *adap) +{ + uint32_t mclk = 25000000; + struct clk *clk; + int err; + + clk = clk_get(NULL, "csi_clk"); + clk_enable(clk); + set_mclk_rate(&mclk); + + gpio_sensor_reset(true); + msleep(10); + gpio_sensor_reset(false); + msleep(100); + + err = i2c_probe(adap, &addr_data, &mc521da_detect_client); + + clk_disable(clk); + clk_put(clk); + + return err; +} + +/*! + * mc521da I2C detach function + * + * @param client struct i2c_client * + * @return Error code indicating success or failure + */ +static int mc521da_detach(struct i2c_client *client) +{ + int err; + + if (!mc521da_i2c_client.adapter) + return -1; + + err = i2c_detach_client(&mc521da_i2c_client); + mc521da_i2c_client.adapter = NULL; + + if (interface_param) + kfree(interface_param); + interface_param = NULL; + + return err; +} + +extern void gpio_sensor_active(void); +extern void gpio_sensor_inactive(void); + +/*! + * mc521da init function + * + * @return Error code indicating success or failure + */ +static __init int mc521da_init(void) +{ + gpio_sensor_active(); + return i2c_add_driver(&mc521da_i2c_driver); +} + +/*! + * mc521da cleanup function + * + * @return Error code indicating success or failure + */ +static void __exit mc521da_clean(void) +{ + i2c_del_driver(&mc521da_i2c_driver); + gpio_sensor_inactive(); +} + +module_init(mc521da_init); +module_exit(mc521da_clean); + +/* Exported symbols for modules. */ +EXPORT_SYMBOL(camera_sensor_if); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MC521DA Camera Driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/media/video/mxc/capture/mt9v111.c linux-2.6.26-lab126/drivers/media/video/mxc/capture/mt9v111.c --- linux-2.6.26/drivers/media/video/mxc/capture/mt9v111.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/mt9v111.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,1076 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mt9v111.c + * + * @brief mt9v111 camera driver functions + * + * @ingroup Camera + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_v4l2_capture.h" +#include "mt9v111.h" + +#ifdef MT9V111_DEBUG +static u16 testpattern = 0; +#endif + +static mt9v111_conf mt9v111_device; + +/*! + * Holds the current frame rate. + */ +static int reset_frame_rate = MT9V111_FRAME_RATE; + +struct sensor { + const struct mt9v111_platform_data *platform_data; + struct v4l2_int_device *v4l2_int_device; + struct i2c_client *i2c_client; + struct v4l2_pix_format pix; + struct v4l2_captureparm streamcap; + bool on; + + /* control settings */ + int brightness; + int hue; + int contrast; + int saturation; + int red; + int green; + int blue; + int ae_mode; + +} mt9v111_data; + +extern void gpio_sensor_active(void); +extern void gpio_sensor_inactive(void); + +static int mt9v111_probe(struct i2c_client *client, + const struct i2c_device_id *id); +static int mt9v111_remove(struct i2c_client *client); + +static const struct i2c_device_id mt9v111_id[] = { + {"mt9v111", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, mt9v111_id); + +static struct i2c_driver mt9v111_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "mt9v111", + }, + .probe = mt9v111_probe, + .remove = mt9v111_remove, + .id_table = mt9v111_id, +/* To add power management add .suspend and .resume functions */ +}; + +/* + * Function definitions + */ + +#ifdef MT9V111_DEBUG +static inline int mt9v111_read_reg(u8 reg) +{ + int val = i2c_smbus_read_word_data(mt9v111_data.i2c_client, reg); + if (val != -1) + val = cpu_to_be16(val); + return val; +} +#endif + +/*! + * Writes to the register via I2C. + */ +static inline int mt9v111_write_reg(u8 reg, u16 val) +{ + pr_debug("In mt9v111_write_reg (0x%x, 0x%x)\n", reg, val); + pr_debug(" write reg %x val %x.\n", reg, val); + + return i2c_smbus_write_word_data(mt9v111_data.i2c_client, + reg, cpu_to_be16(val)); +} + +/*! + * Initialize mt9v111_sensor_lib + * Libarary for Sensor configuration through I2C + * + * @param coreReg Core Registers + * @param ifpReg IFP Register + * + * @return status + */ +static u8 mt9v111_sensor_lib(mt9v111_coreReg * coreReg, mt9v111_IFPReg * ifpReg) +{ + u8 reg; + u16 data; + u8 error = 0; + + pr_debug("In mt9v111_sensor_lib\n"); + + /* + * setup to IFP registers + */ + reg = MT9V111I_ADDR_SPACE_SEL; + data = ifpReg->addrSpaceSel; + mt9v111_write_reg(reg, data); + + /* Operation Mode Control */ + reg = MT9V111I_MODE_CONTROL; + data = ifpReg->modeControl; + mt9v111_write_reg(reg, data); + + /* Output format */ + reg = MT9V111I_FORMAT_CONTROL; + data = ifpReg->formatControl; /* Set bit 12 */ + mt9v111_write_reg(reg, data); + + /* AE limit 4 */ + reg = MT9V111I_SHUTTER_WIDTH_LIMIT_AE; + data = ifpReg->gainLimitAE; + mt9v111_write_reg(reg, data); + + reg = MT9V111I_OUTPUT_FORMAT_CTRL2; + data = ifpReg->outputFormatCtrl2; + mt9v111_write_reg(reg, data); + + reg = MT9V111I_AE_SPEED; + data = ifpReg->AESpeed; + mt9v111_write_reg(reg, data); + + /* output image size */ + reg = MT9V111i_H_PAN; + data = 0x8000 | ifpReg->HPan; + mt9v111_write_reg(reg, data); + + reg = MT9V111i_H_ZOOM; + data = 0x8000 | ifpReg->HZoom; + mt9v111_write_reg(reg, data); + + reg = MT9V111i_H_SIZE; + data = 0x8000 | ifpReg->HSize; + mt9v111_write_reg(reg, data); + + reg = MT9V111i_V_PAN; + data = 0x8000 | ifpReg->VPan; + mt9v111_write_reg(reg, data); + + reg = MT9V111i_V_ZOOM; + data = 0x8000 | ifpReg->VZoom; + mt9v111_write_reg(reg, data); + + reg = MT9V111i_V_SIZE; + data = 0x8000 | ifpReg->VSize; + mt9v111_write_reg(reg, data); + + reg = MT9V111i_H_PAN; + data = ~0x8000 & ifpReg->HPan; + mt9v111_write_reg(reg, data); +#if 0 + reg = MT9V111I_UPPER_SHUTTER_DELAY_LIM; + data = ifpReg->upperShutterDelayLi; + mt9v111_write_reg(reg, data); + + reg = MT9V111I_SHUTTER_60; + data = ifpReg->shutter_width_60; + mt9v111_write_reg(reg, data); + + reg = MT9V111I_SEARCH_FLICK_60; + data = ifpReg->search_flicker_60; + mt9v111_write_reg(reg, data); +#endif + + /* + * setup to sensor core registers + */ + reg = MT9V111I_ADDR_SPACE_SEL; + data = coreReg->addressSelect; + mt9v111_write_reg(reg, data); + + /* enable changes and put the Sync bit on */ + reg = MT9V111S_OUTPUT_CTRL; + data = MT9V111S_OUTCTRL_SYNC | MT9V111S_OUTCTRL_CHIP_ENABLE | 0x3000; + mt9v111_write_reg(reg, data); + + /* min PIXCLK - Default */ + reg = MT9V111S_PIXEL_CLOCK_SPEED; + data = coreReg->pixelClockSpeed; + mt9v111_write_reg(reg, data); + + /* Setup image flipping / Dark rows / row/column skip */ + reg = MT9V111S_READ_MODE; + data = coreReg->readMode; + mt9v111_write_reg(reg, data); + + /* zoom 0 */ + reg = MT9V111S_DIGITAL_ZOOM; + data = coreReg->digitalZoom; + mt9v111_write_reg(reg, data); + + /* min H-blank */ + reg = MT9V111S_HOR_BLANKING; + data = coreReg->horizontalBlanking; + mt9v111_write_reg(reg, data); + + /* min V-blank */ + reg = MT9V111S_VER_BLANKING; + data = coreReg->verticalBlanking; + mt9v111_write_reg(reg, data); + + reg = MT9V111S_SHUTTER_WIDTH; + data = coreReg->shutterWidth; + mt9v111_write_reg(reg, data); + + reg = MT9V111S_SHUTTER_DELAY; + data = ifpReg->upperShutterDelayLi; + mt9v111_write_reg(reg, data); + + /* changes become effective */ + reg = MT9V111S_OUTPUT_CTRL; + data = MT9V111S_OUTCTRL_CHIP_ENABLE | 0x3000; + mt9v111_write_reg(reg, data); + + return error; +} + +/*! + * MT9V111 frame rate calculate + * + * @param frame_rate int * + * @param mclk int + * @return None + */ +static void mt9v111_rate_cal(int *frame_rate, int mclk) +{ + int num_clock_per_row; + int max_rate = 0; + + pr_debug("In mt9v111_rate_cal\n"); + + num_clock_per_row = (MT9V111_MAX_WIDTH + 114 + MT9V111_HORZBLANK_MIN) + * 2; + max_rate = mclk / (num_clock_per_row * + (MT9V111_MAX_HEIGHT + MT9V111_VERTBLANK_DEFAULT)); + + if ((*frame_rate > max_rate) || (*frame_rate == 0)) { + *frame_rate = max_rate; + } + + mt9v111_device.coreReg->verticalBlanking + = mclk / (*frame_rate * num_clock_per_row) - MT9V111_MAX_HEIGHT; + + reset_frame_rate = *frame_rate; +} + +/*! + * MT9V111 sensor configuration + */ +void mt9v111_config(void) +{ + pr_debug("In mt9v111_config\n"); + + mt9v111_device.coreReg->addressSelect = MT9V111I_SEL_SCA; + mt9v111_device.ifpReg->addrSpaceSel = MT9V111I_SEL_IFP; + + mt9v111_device.coreReg->windowHeight = MT9V111_WINHEIGHT; + mt9v111_device.coreReg->windowWidth = MT9V111_WINWIDTH; + mt9v111_device.coreReg->zoomColStart = 0; + mt9v111_device.coreReg->zomRowStart = 0; + mt9v111_device.coreReg->digitalZoom = 0x0; + + mt9v111_device.coreReg->verticalBlanking = MT9V111_VERTBLANK_DEFAULT; + mt9v111_device.coreReg->horizontalBlanking = MT9V111_HORZBLANK_MIN; + mt9v111_device.coreReg->pixelClockSpeed = 0; + mt9v111_device.coreReg->readMode = 0xd0a1; + + mt9v111_device.ifpReg->outputFormatCtrl2 = 0; + mt9v111_device.ifpReg->gainLimitAE = 0x300; + mt9v111_device.ifpReg->AESpeed = 0x80; + + /* here is the default value */ + mt9v111_device.ifpReg->formatControl = 0xc800; + mt9v111_device.ifpReg->modeControl = 0x708e; + mt9v111_device.ifpReg->awbSpeed = 0x4514; + mt9v111_device.coreReg->shutterWidth = 0xf8; + + /* output size */ + mt9v111_device.ifpReg->HPan = 0; + mt9v111_device.ifpReg->HZoom = MT9V111_MAX_WIDTH; + mt9v111_device.ifpReg->HSize = MT9V111_MAX_WIDTH; + mt9v111_device.ifpReg->VPan = 0; + mt9v111_device.ifpReg->VZoom = MT9V111_MAX_HEIGHT; + mt9v111_device.ifpReg->VSize = MT9V111_MAX_HEIGHT; +} + +/*! + * mt9v111 sensor set saturtionn + * + * @param saturation int + + * @return Error code of 0. + */ +static int mt9v111_set_saturation(int saturation) +{ + u8 reg; + u16 data; + pr_debug("In mt9v111_set_saturation(%d)\n", + saturation); + + switch (saturation) { + case 150: + mt9v111_device.ifpReg->awbSpeed = 0x6D14; + break; + case 100: + mt9v111_device.ifpReg->awbSpeed = 0x4514; + break; + case 75: + mt9v111_device.ifpReg->awbSpeed = 0x4D14; + break; + case 50: + mt9v111_device.ifpReg->awbSpeed = 0x5514; + break; + case 37: + mt9v111_device.ifpReg->awbSpeed = 0x5D14; + break; + case 25: + mt9v111_device.ifpReg->awbSpeed = 0x6514; + break; + default: + mt9v111_device.ifpReg->awbSpeed = 0x4514; + break; + } + + reg = MT9V111I_ADDR_SPACE_SEL; + data = mt9v111_device.ifpReg->addrSpaceSel; + mt9v111_write_reg(reg, data); + + /* Operation Mode Control */ + reg = MT9V111I_AWB_SPEED; + data = mt9v111_device.ifpReg->awbSpeed; + mt9v111_write_reg(reg, data); + + return 0; +} + +/*! + * mt9v111 sensor set Auto Exposure measurement window mode configuration + * + * @param ae_mode int + * @return Error code of 0 (no Error) + */ +static int mt9v111_set_ae_mode(int ae_mode) +{ + u8 reg; + u16 data; + + pr_debug("In mt9v111_set_ae_mode(%d)\n", + ae_mode); + + /* Currently this driver only supports auto and manual exposure + * modes. */ + if ((ae_mode > 1) || (ae_mode << 0)) + return -EPERM; + + /* + * The auto exposure is set in bit 14. + * Other values are set for: + * -on the fly defect correction is on (bit 13). + * -aperature correction knee enabled (bit 12). + * -ITU_R BT656 synchronization codes are embedded in the image (bit 7) + * -AE measurement window is weighted sum of large and center windows + * (bits 2-3). + * -auto white balance is on (bit 1). + * -normal color processing (bit 4 = 0). + */ + /* V4L2_EXPOSURE_AUTO = 0; needs register setting of 0x708E */ + /* V4L2_EXPOSURE_MANUAL = 1 needs register setting of 0x308E */ + mt9v111_device.ifpReg->modeControl &= 0x3fff; + mt9v111_device.ifpReg->modeControl |= (ae_mode & 0x03) << 14; + mt9v111_data.ae_mode = ae_mode; + + reg = MT9V111I_ADDR_SPACE_SEL; + data = mt9v111_device.ifpReg->addrSpaceSel; + mt9v111_write_reg(reg, data); + + reg = MT9V111I_MODE_CONTROL; + data = mt9v111_device.ifpReg->modeControl; + mt9v111_write_reg(reg, data); + + return 0; +} + +/*! + * mt9v111 sensor get AE measurement window mode configuration + * + * @param ae_mode int * + * @return None + */ +static void mt9v111_get_ae_mode(int *ae_mode) +{ + pr_debug("In mt9v111_get_ae_mode(%d)\n", *ae_mode); + + if (ae_mode != NULL) { + *ae_mode = (mt9v111_device.ifpReg->modeControl & 0xc) >> 2; + } +} + +#ifdef MT9V111_DEBUG +/*! + * Set sensor to test mode, which will generate test pattern. + * + * @return none + */ +static void mt9v111_test_pattern(bool flag) +{ + u16 data; + + /* switch to sensor registers */ + mt9v111_write_reg(MT9V111I_ADDR_SPACE_SEL, MT9V111I_SEL_SCA); + + if (flag == true) { + testpattern = MT9V111S_OUTCTRL_TEST_MODE; + + data = mt9v111_read_reg(MT9V111S_ROW_NOISE_CTRL) & 0xBF; + mt9v111_write_reg(MT9V111S_ROW_NOISE_CTRL, data); + + mt9v111_write_reg(MT9V111S_TEST_DATA, 0); + + /* changes take effect */ + data = MT9V111S_OUTCTRL_CHIP_ENABLE | testpattern | 0x3000; + mt9v111_write_reg(MT9V111S_OUTPUT_CTRL, data); + } else { + testpattern = 0; + + data = mt9v111_read_reg(MT9V111S_ROW_NOISE_CTRL) | 0x40; + mt9v111_write_reg(MT9V111S_ROW_NOISE_CTRL, data); + + /* changes take effect */ + data = MT9V111S_OUTCTRL_CHIP_ENABLE | testpattern | 0x3000; + mt9v111_write_reg(MT9V111S_OUTPUT_CTRL, data); + } +} +#endif + + +/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */ + +/*! + * ioctl_g_ifparm - V4L2 sensor interface handler for vidioc_int_g_ifparm_num + * s: pointer to standard V4L2 device structure + * p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure + * + * Gets slave interface parameters. + * Calculates the required xclk value to support the requested + * clock parameters in p. This value is returned in the p + * parameter. + * + * vidioc_int_g_ifparm returns platform-specific information about the + * interface settings used by the sensor. + * + * Given the image capture format in pix, the nominal frame period in + * timeperframe, calculate the required xclk frequency. + * + * Called on open. + */ +static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) +{ + pr_debug("In mt9v111:ioctl_g_ifparm\n"); + + if (s == NULL) { + pr_err(" ERROR!! no slave device set!\n"); + return -1; + } + + memset(p, 0, sizeof(*p)); + p->u.bt656.clock_curr = MT9V111_MCLK; + p->if_type = V4L2_IF_TYPE_BT656; + p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; + p->u.bt656.clock_min = MT9V111_CLK_MIN; + p->u.bt656.clock_max = MT9V111_CLK_MAX; + + return 0; +} + +/*! + * Sets the camera power. + * + * s pointer to the camera device + * on if 1, power is to be turned on. 0 means power is to be turned off + * + * ioctl_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num + * @s: pointer to standard V4L2 device structure + * @on: power state to which device is to be set + * + * Sets devices power state to requrested state, if possible. + * This is called on suspend and resume. + */ +static int ioctl_s_power(struct v4l2_int_device *s, int on) +{ + struct sensor *sensor = s->priv; + + pr_debug("In mt9v111:ioctl_s_power\n"); + + sensor->on = on; + + if (on) + gpio_sensor_active(); + else + gpio_sensor_inactive(); + + return 0; +} + +/*! + * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure + * + * Returns the sensor's video CAPTURE parameters. + */ +static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + int ret = 0; + struct v4l2_captureparm *cparm = &a->parm.capture; + /* s->priv points to mt9v111_data */ + + pr_debug("In mt9v111:ioctl_g_parm\n"); + + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); + memset(a, 0, sizeof(*a)); + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cparm->capability = mt9v111_data.streamcap.capability; + cparm->timeperframe = + mt9v111_data.streamcap.timeperframe; + cparm->capturemode = mt9v111_data.streamcap.capturemode; + ret = 0; + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + pr_err(" type is not V4L2_BUF_TYPE_VIDEO_CAPTURE " \ + "but %d\n", a->type); + ret = -EINVAL; + break; + + default: + pr_err(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure + * + * Configures the sensor to use the input parameters, if possible. If + * not possible, reverts to the old parameters and returns the + * appropriate error code. + */ +static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + int ret = 0; + struct v4l2_captureparm *cparm = &a->parm.capture; + /* s->priv points to mt9v111_data */ + + pr_debug("In mt9v111:ioctl_s_parm\n"); + + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); + + /* Check that the new frame rate is allowed. + * Changing the frame rate is not allowed on this + *camera. */ + if (cparm->timeperframe.denominator != + mt9v111_data.streamcap.timeperframe.denominator) { + pr_err("ERROR: mt9v111: ioctl_s_parm: " \ + "This camera does not allow frame rate " + "changes.\n"); + ret = -EINVAL; + } else { + mt9v111_data.streamcap.timeperframe = + cparm->timeperframe; + /* Call any camera functions to match settings. */ + } + + /* Check that new capture mode is supported. */ + if ((cparm->capturemode != 0) && + !(cparm->capturemode & V4L2_MODE_HIGHQUALITY)) { + pr_err("ERROR: mt9v111: ioctl_s_parm: " \ + "unsupported capture mode\n"); + ret = -EINVAL; + } else { + mt9v111_data.streamcap.capturemode = + cparm->capturemode; + /* Call any camera functions to match settings. */ + /* Right now this camera only supports 1 mode. */ + } + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + pr_err(" type is not V4L2_BUF_TYPE_VIDEO_CAPTURE " \ + "but %d\n", a->type); + ret = -EINVAL; + break; + + default: + pr_err(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return 0; +} + +/*! + * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap + * @s: pointer to standard V4L2 device structure + * @f: pointer to standard V4L2 v4l2_format structure + * + * Returns the sensor's current pixel format in the v4l2_format + * parameter. + */ +static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) +{ + struct sensor *sensor = s->priv; + /* s->priv points to mt9v111_data */ + + pr_debug("In mt9v111:ioctl_g_fmt_cap.\n"); + pr_debug(" Returning size of %dx%d\n", + sensor->pix.width, sensor->pix.height); + + f->fmt.pix = sensor->pix; + + return 0; +} + +/*! + * ioctl_queryctrl - V4L2 sensor interface handler for VIDIOC_QUERYCTRL ioctl + * @s: pointer to standard V4L2 device structure + * @qc: standard V4L2 VIDIOC_QUERYCTRL ioctl structure + * + * If the requested control is supported, returns the control information + * from the video_control[] array. Otherwise, returns -EINVAL if the + * control is not supported. + */ +static int ioctl_queryctrl(struct v4l2_int_device *s, struct v4l2_queryctrl *qc) +{ + pr_debug("In mt9v111:ioctl_queryctrl\n"); + + return 0; +} + +/*! + * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure + * + * If the requested control is supported, returns the control's current + * value from the video_control[] array. Otherwise, returns -EINVAL + * if the control is not supported. + */ +static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + pr_debug("In mt9v111:ioctl_g_ctrl\n"); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + pr_debug(" V4L2_CID_BRIGHTNESS\n"); + vc->value = mt9v111_data.brightness; + break; + case V4L2_CID_CONTRAST: + pr_debug(" V4L2_CID_CONTRAST\n"); + vc->value = mt9v111_data.contrast; + break; + case V4L2_CID_SATURATION: + pr_debug(" V4L2_CID_SATURATION\n"); + vc->value = mt9v111_data.saturation; + break; + case V4L2_CID_HUE: + pr_debug(" V4L2_CID_HUE\n"); + vc->value = mt9v111_data.hue; + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + pr_debug( + " V4L2_CID_AUTO_WHITE_BALANCE\n"); + vc->value = 0; + break; + case V4L2_CID_DO_WHITE_BALANCE: + pr_debug( + " V4L2_CID_DO_WHITE_BALANCE\n"); + vc->value = 0; + break; + case V4L2_CID_RED_BALANCE: + pr_debug(" V4L2_CID_RED_BALANCE\n"); + vc->value = mt9v111_data.red; + break; + case V4L2_CID_BLUE_BALANCE: + pr_debug(" V4L2_CID_BLUE_BALANCE\n"); + vc->value = mt9v111_data.blue; + break; + case V4L2_CID_GAMMA: + pr_debug(" V4L2_CID_GAMMA\n"); + vc->value = 0; + break; + case V4L2_CID_EXPOSURE: + pr_debug(" V4L2_CID_EXPOSURE\n"); + vc->value = mt9v111_data.ae_mode; + break; + case V4L2_CID_AUTOGAIN: + pr_debug(" V4L2_CID_AUTOGAIN\n"); + vc->value = 0; + break; + case V4L2_CID_GAIN: + pr_debug(" V4L2_CID_GAIN\n"); + vc->value = 0; + break; + case V4L2_CID_HFLIP: + pr_debug(" V4L2_CID_HFLIP\n"); + vc->value = 0; + break; + case V4L2_CID_VFLIP: + pr_debug(" V4L2_CID_VFLIP\n"); + vc->value = 0; + break; + default: + pr_debug(" Default case\n"); + return -EPERM; + break; + } + + return 0; +} + +/*! + * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure + * + * If the requested control is supported, sets the control's current + * value in HW (and updates the video_control[] array). Otherwise, + * returns -EINVAL if the control is not supported. + */ +static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int retval = 0; + + pr_debug("In mt9v111:ioctl_s_ctrl %d\n", + vc->id); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + pr_debug(" V4L2_CID_BRIGHTNESS\n"); + break; + case V4L2_CID_CONTRAST: + pr_debug(" V4L2_CID_CONTRAST\n"); + break; + case V4L2_CID_SATURATION: + pr_debug(" V4L2_CID_SATURATION\n"); + retval = mt9v111_set_saturation(vc->value); + break; + case V4L2_CID_HUE: + pr_debug(" V4L2_CID_HUE\n"); + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + pr_debug( + " V4L2_CID_AUTO_WHITE_BALANCE\n"); + break; + case V4L2_CID_DO_WHITE_BALANCE: + pr_debug( + " V4L2_CID_DO_WHITE_BALANCE\n"); + break; + case V4L2_CID_RED_BALANCE: + pr_debug(" V4L2_CID_RED_BALANCE\n"); + break; + case V4L2_CID_BLUE_BALANCE: + pr_debug(" V4L2_CID_BLUE_BALANCE\n"); + break; + case V4L2_CID_GAMMA: + pr_debug(" V4L2_CID_GAMMA\n"); + break; + case V4L2_CID_EXPOSURE: + pr_debug(" V4L2_CID_EXPOSURE\n"); + retval = mt9v111_set_ae_mode(vc->value); + break; + case V4L2_CID_AUTOGAIN: + pr_debug(" V4L2_CID_AUTOGAIN\n"); + break; + case V4L2_CID_GAIN: + pr_debug(" V4L2_CID_GAIN\n"); + break; + case V4L2_CID_HFLIP: + pr_debug(" V4L2_CID_HFLIP\n"); + break; + case V4L2_CID_VFLIP: + pr_debug(" V4L2_CID_VFLIP\n"); + break; + default: + pr_debug(" Default case\n"); + retval = -EPERM; + break; + } + + return retval; +} + +/*! + * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT + * @s: pointer to standard V4L2 device structure + */ +static int ioctl_init(struct v4l2_int_device *s) +{ + pr_debug("In mt9v111:ioctl_init\n"); + + return 0; +} + +/*! + * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num + * @s: pointer to standard V4L2 device structure + * + * Initialise the device when slave attaches to the master. + */ +static int ioctl_dev_init(struct v4l2_int_device *s) +{ + uint32_t clock_rate = MT9V111_MCLK; + + pr_debug("In mt9v111:ioctl_dev_init\n"); + + gpio_sensor_active(); + + set_mclk_rate(&clock_rate); + mt9v111_rate_cal(&reset_frame_rate, clock_rate); + mt9v111_sensor_lib(mt9v111_device.coreReg, mt9v111_device.ifpReg); + + return 0; +} + +/*! + * This structure defines all the ioctls for this module and links them to the + * enumeration. + */ +static struct v4l2_int_ioctl_desc mt9v111_ioctl_desc[] = { + + {vidioc_int_dev_init_num, (v4l2_int_ioctl_func *)ioctl_dev_init}, + + /*! + * Delinitialise the dev. at slave detach. + * The complement of ioctl_dev_init. + */ +/* {vidioc_int_dev_exit_num, (v4l2_int_ioctl_func *) ioctl_dev_exit}, */ + + {vidioc_int_s_power_num, (v4l2_int_ioctl_func *) ioctl_s_power}, + {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func *) ioctl_g_ifparm}, +/* {vidioc_int_g_needs_reset_num, + (v4l2_int_ioctl_func *) ioctl_g_needs_reset}, */ +/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *) ioctl_reset}, */ + {vidioc_int_init_num, (v4l2_int_ioctl_func *) ioctl_init}, + + /*! + * VIDIOC_ENUM_FMT ioctl for the CAPTURE buffer type. + */ +/* {vidioc_int_enum_fmt_cap_num, + (v4l2_int_ioctl_func *) ioctl_enum_fmt_cap}, */ + + /*! + * VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type. + * This ioctl is used to negotiate the image capture size and + * pixel format without actually making it take effect. + */ +/* {vidioc_int_try_fmt_cap_num, + (v4l2_int_ioctl_func *) ioctl_try_fmt_cap}, */ + + {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *) ioctl_g_fmt_cap}, + + /*! + * If the requested format is supported, configures the HW to use that + * format, returns error code if format not supported or HW can't be + * correctly configured. + */ +/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap}, */ + + {vidioc_int_g_parm_num, (v4l2_int_ioctl_func *) ioctl_g_parm}, + {vidioc_int_s_parm_num, (v4l2_int_ioctl_func *) ioctl_s_parm}, +/* {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func *) ioctl_queryctrl}, */ + {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *) ioctl_g_ctrl}, + {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *) ioctl_s_ctrl}, +}; + +static struct v4l2_int_slave mt9v111_slave = { + .ioctls = mt9v111_ioctl_desc, + .num_ioctls = ARRAY_SIZE(mt9v111_ioctl_desc), +}; + +static struct v4l2_int_device mt9v111_int_device = { + .module = THIS_MODULE, + .name = "mt9v111", + .type = v4l2_int_type_slave, + .u = { + .slave = &mt9v111_slave, + }, +}; + +/*! + * mt9v111 I2C probe function + * Function set in i2c_driver struct. + * Called by insmod mt9v111_camera.ko. + * + * @return Error code indicating success or failure + */ +static int mt9v111_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int retval; + + pr_debug("In mt9v111_probe device id is %s\n", id->name); + + /* Set initial values for the sensor struct. */ + memset(&mt9v111_data, 0, sizeof(mt9v111_data)); + mt9v111_data.i2c_client = client; + pr_debug(" client name is %s\n", client->name); + mt9v111_data.pix.pixelformat = V4L2_PIX_FMT_UYVY; + mt9v111_data.pix.width = MT9V111_MAX_WIDTH; + mt9v111_data.pix.height = MT9V111_MAX_HEIGHT; + mt9v111_data.streamcap.capability = 0; /* No higher resolution or frame + * frame rate changes supported. + */ + mt9v111_data.streamcap.timeperframe.denominator = MT9V111_FRAME_RATE; + mt9v111_data.streamcap.timeperframe.numerator = 1; + + mt9v111_int_device.priv = &mt9v111_data; + + pr_debug(" type is %d (expect %d)\n", + mt9v111_int_device.type, v4l2_int_type_slave); + pr_debug(" num ioctls is %d\n", + mt9v111_int_device.u.slave->num_ioctls); + + /* This function attaches this structure to the /dev/video0 device. + * The pointer in priv points to the mt9v111_data structure here.*/ + retval = v4l2_int_device_register(&mt9v111_int_device); + + return retval; +} + +/*! + * Function set in i2c_driver struct. + * Called on rmmod mt9v111_camera.ko + */ +static int mt9v111_remove(struct i2c_client *client) +{ + pr_debug("In mt9v111_remove\n"); + + v4l2_int_device_unregister(&mt9v111_int_device); + return 0; +} + +/*! + * MT9V111 init function. + * Called by insmod mt9v111_camera.ko. + * + * @return Error code indicating success or failure + */ +static __init int mt9v111_init(void) +{ + u8 err; + + pr_debug("In mt9v111_init\n"); + + /* Allocate memory for state structures. */ + mt9v111_device.coreReg = (mt9v111_coreReg *) + kmalloc(sizeof(mt9v111_coreReg), GFP_KERNEL); + if (!mt9v111_device.coreReg) + return -1; + memset(mt9v111_device.coreReg, 0, sizeof(mt9v111_coreReg)); + + mt9v111_device.ifpReg = (mt9v111_IFPReg *) + kmalloc(sizeof(mt9v111_IFPReg), GFP_KERNEL); + if (!mt9v111_device.ifpReg) { + kfree(mt9v111_device.coreReg); + mt9v111_device.coreReg = NULL; + return -1; + } + memset(mt9v111_device.ifpReg, 0, sizeof(mt9v111_IFPReg)); + + /* Set contents of the just created structures. */ + mt9v111_config(); + + /* Tells the i2c driver what functions to call for this driver. */ + err = i2c_add_driver(&mt9v111_i2c_driver); + if (err != 0) + pr_err("%s:driver registration failed, error=%d \n", + __func__, err); + + return err; +} + +/*! + * MT9V111 cleanup function. + * Called on rmmod mt9v111_camera.ko + * + * @return Error code indicating success or failure + */ +static void __exit mt9v111_clean(void) +{ + pr_debug("In mt9v111_clean()\n"); + + i2c_del_driver(&mt9v111_i2c_driver); + gpio_sensor_inactive(); + + if (mt9v111_device.coreReg) { + kfree(mt9v111_device.coreReg); + mt9v111_device.coreReg = NULL; + } + + if (mt9v111_device.ifpReg) { + kfree(mt9v111_device.ifpReg); + mt9v111_device.ifpReg = NULL; + } +} + +module_init(mt9v111_init); +module_exit(mt9v111_clean); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Mt9v111 Camera Driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/media/video/mxc/capture/mt9v111.h linux-2.6.26-lab126/drivers/media/video/mxc/capture/mt9v111.h --- linux-2.6.26/drivers/media/video/mxc/capture/mt9v111.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/mt9v111.h 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,431 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup Camera Sensor Drivers + */ + +/*! + * @file mt9v111.h + * + * @brief MT9V111 Camera Header file + * + * This header file contains defines and structures for the iMagic mi8012 + * aka the Micron mt9v111 camera. + * + * @ingroup Camera + */ + +#ifndef MT9V111_H_ +#define MT9V111_H_ + +/*! + * Basic camera values + */ +#define MT9V111_FRAME_RATE 30 +#define MT9V111_MCLK 27000000 /* Desired clock rate */ +#define MT9V111_CLK_MIN 12000000 /* This clock rate yields 15 fps */ +#define MT9V111_CLK_MAX 27000000 +#define MT9V111_MAX_WIDTH 640 /* Max width for this camera */ +#define MT9V111_MAX_HEIGHT 480 /* Max height for this camera */ + +/*! + * mt9v111 IFP REGISTER BANK MAP + */ +#define MT9V111I_ADDR_SPACE_SEL 0x1 +#define MT9V111I_BASE_MAXTRIX_SIGN 0x2 +#define MT9V111I_BASE_MAXTRIX_SCALE15 0x3 +#define MT9V111I_BASE_MAXTRIX_SCALE69 0x4 +#define MT9V111I_APERTURE_GAIN 0x5 +#define MT9V111I_MODE_CONTROL 0x6 +#define MT9V111I_SOFT_RESET 0x7 +#define MT9V111I_FORMAT_CONTROL 0x8 +#define MT9V111I_BASE_MATRIX_CFK1 0x9 +#define MT9V111I_BASE_MATRIX_CFK2 0xa +#define MT9V111I_BASE_MATRIX_CFK3 0xb +#define MT9V111I_BASE_MATRIX_CFK4 0xc +#define MT9V111I_BASE_MATRIX_CFK5 0xd +#define MT9V111I_BASE_MATRIX_CFK6 0xe +#define MT9V111I_BASE_MATRIX_CFK7 0xf +#define MT9V111I_BASE_MATRIX_CFK8 0x10 +#define MT9V111I_BASE_MATRIX_CFK9 0x11 +#define MT9V111I_AWB_POSITION 0x12 +#define MT9V111I_AWB_RED_GAIN 0x13 +#define MT9V111I_AWB_BLUE_GAIN 0x14 +#define MT9V111I_DELTA_MATRIX_CF_SIGN 0x15 +#define MT9V111I_DELTA_MATRIX_CF_D1 0x16 +#define MT9V111I_DELTA_MATRIX_CF_D2 0x17 +#define MT9V111I_DELTA_MATRIX_CF_D3 0x18 +#define MT9V111I_DELTA_MATRIX_CF_D4 0x19 +#define MT9V111I_DELTA_MATRIX_CF_D5 0x1a +#define MT9V111I_DELTA_MATRIX_CF_D6 0x1b +#define MT9V111I_DELTA_MATRIX_CF_D7 0x1c +#define MT9V111I_DELTA_MATRIX_CF_D8 0x1d +#define MT9V111I_DELTA_MATRIX_CF_D9 0x1e +#define MT9V111I_LUMINANCE_LIMIT_WB 0x20 +#define MT9V111I_RBG_MANUUAL_WB 0x21 +#define MT9V111I_AWB_RED_LIMIT 0x22 +#define MT9V111I_AWB_BLUE_LIMIT 0x23 +#define MT9V111I_MATRIX_ADJUST_LIMIT 0x24 +#define MT9V111I_AWB_SPEED 0x25 +#define MT9V111I_H_BOUND_AE 0x26 +#define MT9V111I_V_BOUND_AE 0x27 +#define MT9V111I_H_BOUND_AE_CEN_WIN 0x2b +#define MT9V111I_V_BOUND_AE_CEN_WIN 0x2c +#define MT9V111I_BOUND_AWB_WIN 0x2d +#define MT9V111I_AE_PRECISION_TARGET 0x2e +#define MT9V111I_AE_SPEED 0x2f +#define MT9V111I_RED_AWB_MEASURE 0x30 +#define MT9V111I_LUMA_AWB_MEASURE 0x31 +#define MT9V111I_BLUE_AWB_MEASURE 0x32 +#define MT9V111I_LIMIT_SHARP_SATU_CTRL 0x33 +#define MT9V111I_LUMA_OFFSET 0x34 +#define MT9V111I_CLIP_LIMIT_OUTPUT_LUMI 0x35 +#define MT9V111I_GAIN_LIMIT_AE 0x36 +#define MT9V111I_SHUTTER_WIDTH_LIMIT_AE 0x37 +#define MT9V111I_UPPER_SHUTTER_DELAY_LIM 0x39 +#define MT9V111I_OUTPUT_FORMAT_CTRL2 0x3a +#define MT9V111I_IPF_BLACK_LEVEL_SUB 0x3b +#define MT9V111I_IPF_BLACK_LEVEL_ADD 0x3c +#define MT9V111I_ADC_LIMIT_AE_ADJ 0x3d +#define MT9V111I_GAIN_THRE_CCAM_ADJ 0x3e +#define MT9V111I_LINEAR_AE 0x3f +#define MT9V111I_THRESHOLD_EDGE_DEFECT 0x47 +#define MT9V111I_LUMA_SUM_MEASURE 0x4c +#define MT9V111I_TIME_ADV_SUM_LUMA 0x4d +#define MT9V111I_MOTION 0x52 +#define MT9V111I_GAMMA_KNEE_Y12 0x53 +#define MT9V111I_GAMMA_KNEE_Y34 0x54 +#define MT9V111I_GAMMA_KNEE_Y56 0x55 +#define MT9V111I_GAMMA_KNEE_Y78 0x56 +#define MT9V111I_GAMMA_KNEE_Y90 0x57 +#define MT9V111I_GAMMA_VALUE_Y0 0x58 +#define MT9V111I_SHUTTER_60 0x59 +#define MT9V111I_SEARCH_FLICK_60 0x5c +#define MT9V111I_RATIO_IMAGE_GAIN_BASE 0x5e +#define MT9V111I_RATIO_IMAGE_GAIN_DELTA 0x5f +#define MT9V111I_SIGN_VALUE_REG5F 0x60 +#define MT9V111I_AE_GAIN 0x62 +#define MT9V111I_MAX_GAIN_AE 0x67 +#define MT9V111I_LENS_CORRECT_CTRL 0x80 +#define MT9V111I_SHADING_PARAMETER1 0x81 +#define MT9V111I_SHADING_PARAMETER2 0x82 +#define MT9V111I_SHADING_PARAMETER3 0x83 +#define MT9V111I_SHADING_PARAMETER4 0x84 +#define MT9V111I_SHADING_PARAMETER5 0x85 +#define MT9V111I_SHADING_PARAMETER6 0x86 +#define MT9V111I_SHADING_PARAMETER7 0x87 +#define MT9V111I_SHADING_PARAMETER8 0x88 +#define MT9V111I_SHADING_PARAMETER9 0x89 +#define MT9V111I_SHADING_PARAMETER10 0x8A +#define MT9V111I_SHADING_PARAMETER11 0x8B +#define MT9V111I_SHADING_PARAMETER12 0x8C +#define MT9V111I_SHADING_PARAMETER13 0x8D +#define MT9V111I_SHADING_PARAMETER14 0x8E +#define MT9V111I_SHADING_PARAMETER15 0x8F +#define MT9V111I_SHADING_PARAMETER16 0x90 +#define MT9V111I_SHADING_PARAMETER17 0x91 +#define MT9V111I_SHADING_PARAMETER18 0x92 +#define MT9V111I_SHADING_PARAMETER19 0x93 +#define MT9V111I_SHADING_PARAMETER20 0x94 +#define MT9V111I_SHADING_PARAMETER21 0x95 +#define MT9V111i_FLASH_CTRL 0x98 +#define MT9V111i_LINE_COUNTER 0x99 +#define MT9V111i_FRAME_COUNTER 0x9A +#define MT9V111i_H_PAN 0xA5 +#define MT9V111i_H_ZOOM 0xA6 +#define MT9V111i_H_SIZE 0xA7 +#define MT9V111i_V_PAN 0xA8 +#define MT9V111i_V_ZOOM 0xA9 +#define MT9V111i_V_SIZE 0xAA + +#define MT9V111I_SEL_IFP 0x1 +#define MT9V111I_SEL_SCA 0x4 +#define MT9V111I_FC_RGB_OR_YUV 0x1000 + +/*! + * Mt9v111 SENSOR CORE REGISTER BANK MAP + */ +#define MT9V111S_ADDR_SPACE_SEL 0x1 +#define MT9V111S_COLUMN_START 0x2 +#define MT9V111S_WIN_HEIGHT 0x3 +#define MT9V111S_WIN_WIDTH 0x4 +#define MT9V111S_HOR_BLANKING 0x5 +#define MT9V111S_VER_BLANKING 0x6 +#define MT9V111S_OUTPUT_CTRL 0x7 +#define MT9V111S_ROW_START 0x8 +#define MT9V111S_SHUTTER_WIDTH 0x9 +#define MT9V111S_PIXEL_CLOCK_SPEED 0xa +#define MT9V111S_RESTART 0xb +#define MT9V111S_SHUTTER_DELAY 0xc +#define MT9V111S_RESET 0xd +#define MT9V111S_COLUMN_START_IN_ZOOM 0x12 +#define MT9V111S_ROW_START_IN_ZOOM 0x13 +#define MT9V111S_DIGITAL_ZOOM 0x1e +#define MT9V111S_READ_MODE 0x20 +#define MT9V111S_DAC_CTRL 0x27 +#define MT9V111S_GREEN1_GAIN 0x2b +#define MT9V111S_BLUE_GAIN 0x2c +#define MT9V111S_READ_GAIN 0x2d +#define MT9V111S_GREEN2_GAIN 0x2e +#define MT9V111S_ROW_NOISE_CTRL 0x30 +#define MT9V111S_DARK_TARGET_W 0x31 +#define MT9V111S_TEST_DATA 0x32 +#define MT9V111S_GLOBAL_GAIN 0x35 +#define MT9V111S_SENSOR_CORE_VERSION 0x36 +#define MT9V111S_DARK_TARGET_WO 0x37 +#define MT9V111S_VERF_DAC 0x41 +#define MT9V111S_VCM_VCL 0x42 +#define MT9V111S_DISABLE_BYPASS 0x58 +#define MT9V111S_CALIB_MEAN_TEST 0x59 +#define MT9V111S_DARK_G1_AVE 0x5B +#define MT9V111S_DARK_G2_AVE 0x5C +#define MT9V111S_DARK_R_AVE 0x5D +#define MT9V111S_DARK_B_AVE 0x5E +#define MT9V111S_CAL_THRESHOLD 0x5f +#define MT9V111S_CAL_G1 0x60 +#define MT9V111S_CAL_G2 0x61 +#define MT9V111S_CAL_CTRL 0x62 +#define MT9V111S_CAL_R 0x63 +#define MT9V111S_CAL_B 0x64 +#define MT9V111S_CHIP_ENABLE 0xF1 +#define MT9V111S_CHIP_VERSION 0xFF + +/* OUTPUT_CTRL */ +#define MT9V111S_OUTCTRL_SYNC 0x1 +#define MT9V111S_OUTCTRL_CHIP_ENABLE 0x2 +#define MT9V111S_OUTCTRL_TEST_MODE 0x40 + +/* READ_MODE */ +#define MT9V111S_RM_NOBADFRAME 0x1 +#define MT9V111S_RM_NODESTRUCT 0x2 +#define MT9V111S_RM_COLUMNSKIP 0x4 +#define MT9V111S_RM_ROWSKIP 0x8 +#define MT9V111S_RM_BOOSTEDRESET 0x1000 +#define MT9V111S_RM_COLUMN_LATE 0x10 +#define MT9V111S_RM_ROW_LATE 0x80 +#define MT9V111S_RM_RIGTH_TO_LEFT 0x4000 +#define MT9V111S_RM_BOTTOM_TO_TOP 0x8000 + +/*! I2C Slave Address */ +#define MT9V111_I2C_ADDRESS 0x48 + +/*! + * The image resolution enum for the mt9v111 sensor + */ +typedef enum { + MT9V111_OutputResolution_VGA = 0, /*!< VGA size */ + MT9V111_OutputResolution_QVGA, /*!< QVGA size */ + MT9V111_OutputResolution_CIF, /*!< CIF size */ + MT9V111_OutputResolution_QCIF, /*!< QCIF size */ + MT9V111_OutputResolution_QQVGA, /*!< QQVGA size */ + MT9V111_OutputResolution_SXGA /*!< SXGA size */ +} MT9V111_OutputResolution; + +enum { + MT9V111_WINWIDTH = 0x287, + MT9V111_WINWIDTH_DEFAULT = 0x287, + MT9V111_WINWIDTH_MIN = 0x9, + + MT9V111_WINHEIGHT = 0x1E7, + MT9V111_WINHEIGHT_DEFAULT = 0x1E7, + + MT9V111_HORZBLANK_DEFAULT = 0x26, + MT9V111_HORZBLANK_MIN = 0x9, + MT9V111_HORZBLANK_MAX = 0x3FF, + + MT9V111_VERTBLANK_DEFAULT = 0x4, + MT9V111_VERTBLANK_MIN = 0x3, + MT9V111_VERTBLANK_MAX = 0xFFF, +}; + +/*! + * Mt9v111 Core Register structure. + */ +typedef struct { + u32 addressSelect; /*!< select address bank for Core Register 0x4 */ + u32 columnStart; /*!< Starting Column */ + u32 windowHeight; /*!< Window Height */ + u32 windowWidth; /*!< Window Width */ + u32 horizontalBlanking; /*!< Horizontal Blank time, in pixels */ + u32 verticalBlanking; /*!< Vertical Blank time, in pixels */ + u32 outputControl; /*!< Register to control sensor output */ + u32 rowStart; /*!< Starting Row */ + u32 shutterWidth; + u32 pixelClockSpeed; /*!< pixel date rate */ + u32 restart; /*!< Abandon the readout of current frame */ + u32 shutterDelay; + u32 reset; /*!< reset the sensor to the default mode */ + u32 zoomColStart; /*!< Column start in the Zoom mode */ + u32 zomRowStart; /*!< Row start in the Zoom mode */ + u32 digitalZoom; /*!< 1 means zoom by 2 */ + u32 readMode; /*!< Readmode: aspects of the readout of the sensor */ + u32 dACStandbyControl; + u32 green1Gain; /*!< Gain Settings */ + u32 blueGain; + u32 redGain; + u32 green2Gain; + u32 rowNoiseControl; + u32 darkTargetwNC; + u32 testData; /*!< test mode */ + u32 globalGain; + u32 chipVersion; + u32 darkTargetwoNC; + u32 vREFDACs; + u32 vCMandVCL; + u32 disableBypass; + u32 calibMeanTest; + u32 darkG1average; + u32 darkG2average; + u32 darkRaverage; + u32 darkBaverage; + u32 calibThreshold; + u32 calibGreen1; + u32 calibGreen2; + u32 calibControl; + u32 calibRed; + u32 calibBlue; + u32 chipEnable; /*!< Image core Registers written by image flow processor */ +} mt9v111_coreReg; + +/*! + * Mt9v111 IFP Register structure. + */ +typedef struct { + u32 addrSpaceSel; /*!< select address bank for Core Register 0x1 */ + u32 baseMaxtrixSign; /*!< sign of coefficient for base color correction matrix */ + u32 baseMaxtrixScale15; /*!< scaling of color correction coefficient K1-5 */ + u32 baseMaxtrixScale69; /*!< scaling of color correction coefficient K6-9 */ + u32 apertureGain; /*!< sharpening */ + u32 modeControl; /*!< bit 7 CCIR656 sync codes are embedded in the image */ + u32 softReset; /*!< Image processing mode: 1 reset mode, 0 operational mode */ + u32 formatControl; /*!< bit12 1 for RGB565, 0 for YcrCb */ + u32 baseMatrixCfk1; /*!< K1 Color correction coefficient */ + u32 baseMatrixCfk2; /*!< K2 Color correction coefficient */ + u32 baseMatrixCfk3; /*!< K3 Color correction coefficient */ + u32 baseMatrixCfk4; /*!< K4 Color correction coefficient */ + u32 baseMatrixCfk5; /*!< K5 Color correction coefficient */ + u32 baseMatrixCfk6; /*!< K6 Color correction coefficient */ + u32 baseMatrixCfk7; /*!< K7 Color correction coefficient */ + u32 baseMatrixCfk8; /*!< K8 Color correction coefficient */ + u32 baseMatrixCfk9; /*!< K9 Color correction coefficient */ + u32 awbPosition; /*!< Current position of AWB color correction matrix */ + u32 awbRedGain; /*!< Current value of AWB red channel gain */ + u32 awbBlueGain; /*!< Current value of AWB blue channel gain */ + u32 deltaMatrixCFSign; /*!< Sign of coefficients of delta color correction matrix register */ + u32 deltaMatrixCFD1; /*!< D1 Delta coefficient */ + u32 deltaMatrixCFD2; /*!< D2 Delta coefficient */ + u32 deltaMatrixCFD3; /*!< D3 Delta coefficient */ + u32 deltaMatrixCFD4; /*!< D4 Delta coefficient */ + u32 deltaMatrixCFD5; /*!< D5 Delta coefficient */ + u32 deltaMatrixCFD6; /*!< D6 Delta coefficient */ + u32 deltaMatrixCFD7; /*!< D7 Delta coefficient */ + u32 deltaMatrixCFD8; /*!< D8 Delta coefficient */ + u32 deltaMatrixCFD9; /*!< D9 Delta coefficient */ + u32 lumLimitWB; /*!< Luminance range of pixels considered in WB statistics */ + u32 RBGManualWB; /*!< Red and Blue color channel gains for manual white balance */ + u32 awbRedLimit; /*!< Limits on Red channel gain adjustment through AWB */ + u32 awbBlueLimit; /*!< Limits on Blue channel gain adjustment through AWB */ + u32 matrixAdjLimit; /*!< Limits on color correction matrix adjustment through AWB */ + u32 awbSpeed; /*!< AWB speed and color saturation control */ + u32 HBoundAE; /*!< Horizontal boundaries of AWB measurement window */ + u32 VBoundAE; /*!< Vertical boundaries of AWB measurement window */ + u32 HBoundAECenWin; /*!< Horizontal boundaries of AE measurement window for backlight compensation */ + u32 VBoundAECenWin; /*!< Vertical boundaries of AE measurement window for backlight compensation */ + u32 boundAwbWin; /*!< Boundaries of AWB measurement window */ + u32 AEPrecisionTarget; /*!< Auto exposure target and precision control */ + u32 AESpeed; /*!< AE speed and sensitivity control register */ + u32 redAWBMeasure; /*!< Measure of the red channel value used by AWB */ + u32 lumaAWBMeasure; /*!< Measure of the luminance channel value used by AWB */ + u32 blueAWBMeasure; /*!< Measure of the blue channel value used by AWB */ + u32 limitSharpSatuCtrl; /*!< Automatic control of sharpness and color saturation */ + u32 lumaOffset; /*!< Luminance offset control (brightness control) */ + u32 clipLimitOutputLumi; /*!< Clipping limits for output luminance */ + u32 gainLimitAE; /*!< Imager gain limits for AE adjustment */ + u32 shutterWidthLimitAE; /*!< Shutter width (exposure time) limits for AE adjustment */ + u32 upperShutterDelayLi; /*!< Upper Shutter Delay Limit */ + u32 outputFormatCtrl2; /*!< Output Format Control 2 + 00 = 16-bit RGB565. + 01 = 15-bit RGB555. + 10 = 12-bit RGB444x. + 11 = 12-bit RGBx444. */ + u32 ipfBlackLevelSub; /*!< IFP black level subtraction */ + u32 ipfBlackLevelAdd; /*!< IFP black level addition */ + u32 adcLimitAEAdj; /*!< ADC limits for AE adjustment */ + u32 agimnThreCamAdj; /*!< Gain threshold for CCM adjustment */ + u32 linearAE; + u32 thresholdEdgeDefect; /*!< Edge threshold for interpolation and defect correction */ + u32 lumaSumMeasure; /*!< Luma measured by AE engine */ + u32 timeAdvSumLuma; /*!< Time-averaged luminance value tracked by auto exposure */ + u32 motion; /*!< 1 when motion is detected */ + u32 gammaKneeY12; /*!< Gamma knee points Y1 and Y2 */ + u32 gammaKneeY34; /*!< Gamma knee points Y3 and Y4 */ + u32 gammaKneeY56; /*!< Gamma knee points Y5 and Y6 */ + u32 gammaKneeY78; /*!< Gamma knee points Y7 and Y8 */ + u32 gammaKneeY90; /*!< Gamma knee points Y9 and Y10 */ + u32 gammaKneeY0; /*!< Gamma knee point Y0 */ + u32 shutter_width_60; + u32 search_flicker_60; + u32 ratioImageGainBase; + u32 ratioImageGainDelta; + u32 signValueReg5F; + u32 aeGain; + u32 maxGainAE; + u32 lensCorrectCtrl; + u32 shadingParameter1; /*!< Shade Parameters */ + u32 shadingParameter2; + u32 shadingParameter3; + u32 shadingParameter4; + u32 shadingParameter5; + u32 shadingParameter6; + u32 shadingParameter7; + u32 shadingParameter8; + u32 shadingParameter9; + u32 shadingParameter10; + u32 shadingParameter11; + u32 shadingParameter12; + u32 shadingParameter13; + u32 shadingParameter14; + u32 shadingParameter15; + u32 shadingParameter16; + u32 shadingParameter17; + u32 shadingParameter18; + u32 shadingParameter19; + u32 shadingParameter20; + u32 shadingParameter21; + u32 flashCtrl; /*!< Flash control */ + u32 lineCounter; /*!< Line counter */ + u32 frameCounter; /*!< Frame counter */ + u32 HPan; /*!< Horizontal pan in decimation */ + u32 HZoom; /*!< Horizontal zoom in decimation */ + u32 HSize; /*!< Horizontal output size iIn decimation */ + u32 VPan; /*!< Vertical pan in decimation */ + u32 VZoom; /*!< Vertical zoom in decimation */ + u32 VSize; /*!< Vertical output size in decimation */ +} mt9v111_IFPReg; + +/*! + * mt9v111 Config structure + */ +typedef struct { + mt9v111_coreReg *coreReg; /*!< Sensor Core Register Bank */ + mt9v111_IFPReg *ifpReg; /*!< IFP Register Bank */ +} mt9v111_conf; + +typedef struct { + u8 index; + u16 width; + u16 height; +} mt9v111_image_format; + +#endif /* MT9V111_H_ */ diff -urN linux-2.6.26/drivers/media/video/mxc/capture/mx27_csi.c linux-2.6.26-lab126/drivers/media/video/mxc/capture/mx27_csi.c --- linux-2.6.26/drivers/media/video/mxc/capture/mx27_csi.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/mx27_csi.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,332 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mx27_csi.c + * + * @brief CMOS Sensor interface functions + * + * @ingroup CSI + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mx27_csi.h" + +static csi_config_t g_csi_cfg; /* csi hardware configuration */ +static bool gcsi_mclk_on = false; +static csi_irq_callback_t g_callback = 0; +static void *g_callback_data = 0; +static struct clk csi_mclk; + +static irqreturn_t csi_irq_handler(int irq, void *data) +{ + unsigned long status = __raw_readl(CSI_CSISR); + + __raw_writel(status, CSI_CSISR); + if (g_callback) + g_callback(g_callback_data, status); + + pr_debug("CSI status = 0x%08lX\n", status); + + return IRQ_HANDLED; +} + +static void csihw_set_config(csi_config_t * cfg) +{ + unsigned val = 0; + + /* control reg 1 */ + val |= cfg->swap16_en ? BIT_SWAP16_EN : 0; + val |= cfg->ext_vsync ? BIT_EXT_VSYNC : 0; + val |= cfg->eof_int_en ? BIT_EOF_INT_EN : 0; + val |= cfg->prp_if_en ? BIT_PRP_IF_EN : 0; + val |= cfg->ccir_mode ? BIT_CCIR_MODE : 0; + val |= cfg->cof_int_en ? BIT_COF_INT_EN : 0; + val |= cfg->sf_or_inten ? BIT_SF_OR_INTEN : 0; + val |= cfg->rf_or_inten ? BIT_RF_OR_INTEN : 0; + val |= cfg->statff_level << SHIFT_STATFF_LEVEL; + val |= cfg->staff_inten ? BIT_STATFF_INTEN : 0; + val |= cfg->rxff_level << SHIFT_RXFF_LEVEL; + val |= cfg->rxff_inten ? BIT_RXFF_INTEN : 0; + val |= cfg->sof_pol ? BIT_SOF_POL : 0; + val |= cfg->sof_inten ? BIT_SOF_INTEN : 0; + val |= cfg->mclkdiv << SHIFT_MCLKDIV; + val |= cfg->hsync_pol ? BIT_HSYNC_POL : 0; + val |= cfg->ccir_en ? BIT_CCIR_EN : 0; + val |= cfg->mclken ? BIT_MCLKEN : 0; + val |= cfg->fcc ? BIT_FCC : 0; + val |= cfg->pack_dir ? BIT_PACK_DIR : 0; + val |= cfg->gclk_mode ? BIT_GCLK_MODE : 0; + val |= cfg->inv_data ? BIT_INV_DATA : 0; + val |= cfg->inv_pclk ? BIT_INV_PCLK : 0; + val |= cfg->redge ? BIT_REDGE : 0; + + __raw_writel(val, CSI_CSICR1); + + /* control reg 3 */ + val = 0x0; + val |= cfg->csi_sup ? BIT_CSI_SUP : 0; + val |= cfg->zero_pack_en ? BIT_ZERO_PACK_EN : 0; + val |= cfg->ecc_int_en ? BIT_ECC_INT_EN : 0; + val |= cfg->ecc_auto_en ? BIT_ECC_AUTO_EN : 0; + + __raw_writel(val, CSI_CSICR3); + + /* rxfifo counter */ + __raw_writel(cfg->rxcnt, CSI_CSIRXCNT); + + /* update global config */ + memcpy(&g_csi_cfg, cfg, sizeof(csi_config_t)); +} + +static void csihw_reset_frame_count(void) +{ + __raw_writel(__raw_readl(CSI_CSICR3) | BIT_FRMCNT_RST, CSI_CSICR3); +} + +static void csihw_reset(void) +{ + csihw_reset_frame_count(); + __raw_writel(CSICR1_RESET_VAL, CSI_CSICR1); + __raw_writel(CSICR2_RESET_VAL, CSI_CSICR2); + __raw_writel(CSICR3_RESET_VAL, CSI_CSICR3); +} + +/*! + * csi_init_interface + * Sets initial values for the CSI registers. + * The width and height of the sensor and the actual frame size will be + * set to the same values. + * @param width Sensor width + * @param height Sensor height + * @param pixel_fmt pixel format + * @param sig csi_signal_cfg_t + * + * @return 0 for success, -EINVAL for error + */ +int32_t csi_init_interface(uint16_t width, uint16_t height, + uint32_t pixel_fmt, csi_signal_cfg_t sig) +{ + csi_config_t cfg; + + /* Set the CSI_SENS_CONF register remaining fields */ + cfg.swap16_en = 1; + cfg.ext_vsync = sig.ext_vsync; + cfg.eof_int_en = 0; + cfg.prp_if_en = 1; + cfg.ccir_mode = 0; + cfg.cof_int_en = 0; + cfg.sf_or_inten = 0; + cfg.rf_or_inten = 0; + cfg.statff_level = 0; + cfg.staff_inten = 0; + cfg.rxff_level = 2; + cfg.rxff_inten = 0; + cfg.sof_pol = 1; + cfg.sof_inten = 0; + cfg.mclkdiv = 0; + cfg.hsync_pol = 1; + cfg.ccir_en = 0; + cfg.mclken = gcsi_mclk_on ? 1 : 0; + cfg.fcc = 1; + cfg.pack_dir = 0; + cfg.gclk_mode = 1; + cfg.inv_data = sig.data_pol; + cfg.inv_pclk = sig.pixclk_pol; + cfg.redge = 1; + cfg.csicnt1_rsv = 0; + + /* control reg 3 */ + cfg.frmcnt = 0; + cfg.frame_reset = 0; + cfg.csi_sup = 0; + cfg.zero_pack_en = 0; + cfg.ecc_int_en = 0; + cfg.ecc_auto_en = 0; + + csihw_set_config(&cfg); + + return 0; +} + +/*! + * csi_enable_prpif + * Enable or disable CSI-PrP interface + * @param enable Non-zero to enable, zero to disable + */ +void csi_enable_prpif(uint32_t enable) +{ + if (enable) { + g_csi_cfg.prp_if_en = 1; + g_csi_cfg.sof_inten = 0; + g_csi_cfg.pack_dir = 0; + } else { + g_csi_cfg.prp_if_en = 0; + g_csi_cfg.sof_inten = 1; + g_csi_cfg.pack_dir = 1; + } + + csihw_set_config(&g_csi_cfg); +} + +/*! + * csi_enable_mclk + * + * @param src enum define which source to control the clk + * CSI_MCLK_VF CSI_MCLK_ENC CSI_MCLK_RAW CSI_MCLK_I2C + * @param flag true to enable mclk, false to disable mclk + * @param wait true to wait 100ms make clock stable, false not wait + * + * @return 0 for success + */ +int32_t csi_enable_mclk(int src, bool flag, bool wait) +{ + if (flag == true) { + clk_enable(&csi_mclk); + if (wait == true) + msleep(10); + pr_debug("Enable csi clock from source %d\n", src); + gcsi_mclk_on = true; + } else { + clk_disable(&csi_mclk); + pr_debug("Disable csi clock from source %d\n", src); + gcsi_mclk_on = false; + } + + return 0; +} + +/*! + * csi_read_mclk_flag + * + * @return gcsi_mclk_source + */ +int csi_read_mclk_flag(void) +{ + return 0; +} + +void csi_set_callback(csi_irq_callback_t callback, void *data) +{ + g_callback = callback; + g_callback_data = data; +} + +static void _mclk_recalc(struct clk *clk) +{ + u32 div; + + div = (__raw_readl(CSI_CSICR1) & BIT_MCLKDIV) >> SHIFT_MCLKDIV; + div = (div + 1) * 2; + + clk->rate = clk->parent->rate / div; +} + +static unsigned long _mclk_round_rate(struct clk *clk, unsigned long rate) +{ + /* Keep CSI divider and change parent clock */ + if (clk->parent->round_rate) { + return clk->parent->round_rate(clk->parent, rate * 2); + } + return 0; +} + +static int _mclk_set_rate(struct clk *clk, unsigned long rate) +{ + int ret = -EINVAL; + + /* Keep CSI divider and change parent clock */ + if (clk->parent->set_rate) { + ret = clk->parent->set_rate(clk->parent, rate * 2); + if (ret == 0) { + clk->rate = clk->parent->rate / 2; + } + } + + return ret; +} + +static int _mclk_enable(struct clk *clk) +{ + __raw_writel(__raw_readl(CSI_CSICR1) | BIT_MCLKEN, CSI_CSICR1); + return 0; +} + +static void _mclk_disable(struct clk *clk) +{ + __raw_writel(__raw_readl(CSI_CSICR1) & ~BIT_MCLKEN, CSI_CSICR1); +} + +static struct clk csi_mclk = { + .name = "csi_clk", + .recalc = _mclk_recalc, + .round_rate = _mclk_round_rate, + .set_rate = _mclk_set_rate, + .enable = _mclk_enable, + .disable = _mclk_disable, +}; + +int32_t __init csi_init_module(void) +{ + int ret = 0; + struct clk *per_clk; + + per_clk = clk_get(NULL, "csi_perclk"); + if (IS_ERR(per_clk)) + return PTR_ERR(per_clk); + clk_put(per_clk); + csi_mclk.parent = per_clk; + clk_register(&csi_mclk); + clk_enable(per_clk); + csi_mclk.recalc(&csi_mclk); + + csihw_reset(); + + /* interrupt enable */ + ret = request_irq(MXC_INT_CSI, csi_irq_handler, 0, "csi", 0); + if (ret) + pr_debug("CSI error: irq request fail\n"); + + return ret; +} + +void __exit csi_cleanup_module(void) +{ + /* free irq */ + free_irq(MXC_INT_CSI, 0); + + clk_disable(&csi_mclk); +} + +module_init(csi_init_module); +module_exit(csi_cleanup_module); + +EXPORT_SYMBOL(csi_init_interface); +EXPORT_SYMBOL(csi_enable_mclk); +EXPORT_SYMBOL(csi_read_mclk_flag); +EXPORT_SYMBOL(csi_set_callback); +EXPORT_SYMBOL(csi_enable_prpif); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MX27 CSI driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/media/video/mxc/capture/mx27_csi.h linux-2.6.26-lab126/drivers/media/video/mxc/capture/mx27_csi.h --- linux-2.6.26/drivers/media/video/mxc/capture/mx27_csi.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/mx27_csi.h 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,165 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mx27_csi.h + * + * @brief CMOS Sensor interface functions + * + * @ingroup CSI + */ + +#ifndef MX27_CSI_H +#define MX27_CSI_H + +/* reset values */ +#define CSICR1_RESET_VAL 0x40000800 +#define CSICR2_RESET_VAL 0x0 +#define CSICR3_RESET_VAL 0x0 + +/* csi control reg 1 */ +#define BIT_SWAP16_EN (0x1 << 31) +#define BIT_EXT_VSYNC (0x1 << 30) +#define BIT_EOF_INT_EN (0x1 << 29) +#define BIT_PRP_IF_EN (0x1 << 28) +#define BIT_CCIR_MODE (0x1 << 27) +#define BIT_COF_INT_EN (0x1 << 26) +#define BIT_SF_OR_INTEN (0x1 << 25) +#define BIT_RF_OR_INTEN (0x1 << 24) +#define BIT_STATFF_LEVEL (0x3 << 22) +#define BIT_STATFF_INTEN (0x1 << 21) +#define BIT_RXFF_LEVEL (0x3 << 19) +#define BIT_RXFF_INTEN (0x1 << 18) +#define BIT_SOF_POL (0x1 << 17) +#define BIT_SOF_INTEN (0x1 << 16) +#define BIT_MCLKDIV (0xF << 12) +#define BIT_HSYNC_POL (0x1 << 11) +#define BIT_CCIR_EN (0x1 << 10) +#define BIT_MCLKEN (0x1 << 9) +#define BIT_FCC (0x1 << 8) +#define BIT_PACK_DIR (0x1 << 7) +#define BIT_CLR_STATFIFO (0x1 << 6) +#define BIT_CLR_RXFIFO (0x1 << 5) +#define BIT_GCLK_MODE (0x1 << 4) +#define BIT_INV_DATA (0x1 << 3) +#define BIT_INV_PCLK (0x1 << 2) +#define BIT_REDGE (0x1 << 1) + +#define SHIFT_STATFF_LEVEL 22 +#define SHIFT_RXFF_LEVEL 19 +#define SHIFT_MCLKDIV 12 + +/* control reg 3 */ +#define BIT_FRMCNT (0xFFFF << 16) +#define BIT_FRMCNT_RST (0x1 << 15) +#define BIT_CSI_SUP (0x1 << 3) +#define BIT_ZERO_PACK_EN (0x1 << 2) +#define BIT_ECC_INT_EN (0x1 << 1) +#define BIT_ECC_AUTO_EN (0x1) + +#define SHIFT_FRMCNT 16 + +/* csi status reg */ +#define BIT_SFF_OR_INT (0x1 << 25) +#define BIT_RFF_OR_INT (0x1 << 24) +#define BIT_STATFF_INT (0x1 << 21) +#define BIT_RXFF_INT (0x1 << 18) +#define BIT_EOF_INT (0x1 << 17) +#define BIT_SOF_INT (0x1 << 16) +#define BIT_F2_INT (0x1 << 15) +#define BIT_F1_INT (0x1 << 14) +#define BIT_COF_INT (0x1 << 13) +#define BIT_ECC_INT (0x1 << 1) +#define BIT_DRDY (0x1 << 0) + +#define CSI_MCLK_VF 1 +#define CSI_MCLK_ENC 2 +#define CSI_MCLK_RAW 4 +#define CSI_MCLK_I2C 8 + +#define CSI_CSICR1 (IO_ADDRESS(CSI_BASE_ADDR)) +#define CSI_CSICR2 (IO_ADDRESS(CSI_BASE_ADDR + 0x4)) +#define CSI_CSISR (IO_ADDRESS(CSI_BASE_ADDR + 0x8)) +#define CSI_STATFIFO (IO_ADDRESS(CSI_BASE_ADDR + 0xC)) +#define CSI_CSIRXFIFO (IO_ADDRESS(CSI_BASE_ADDR + 0x10)) +#define CSI_CSIRXCNT (IO_ADDRESS(CSI_BASE_ADDR + 0x14)) +#define CSI_CSICR3 (IO_ADDRESS(CSI_BASE_ADDR + 0x1C)) + +#define CSI_CSIRXFIFO_PHYADDR (CSI_BASE_ADDR + 0x10) + +static __inline void csi_clear_status(unsigned long status) +{ + __raw_writel(status, CSI_CSISR); +} + +typedef struct { + unsigned data_width:3; + unsigned clk_mode:2; + unsigned ext_vsync:1; + unsigned Vsync_pol:1; + unsigned Hsync_pol:1; + unsigned pixclk_pol:1; + unsigned data_pol:1; + unsigned sens_clksrc:1; +} csi_signal_cfg_t; + +typedef struct { + /* control reg 1 */ + unsigned int swap16_en:1; + unsigned int ext_vsync:1; + unsigned int eof_int_en:1; + unsigned int prp_if_en:1; + unsigned int ccir_mode:1; + unsigned int cof_int_en:1; + unsigned int sf_or_inten:1; + unsigned int rf_or_inten:1; + unsigned int statff_level:2; + unsigned int staff_inten:1; + unsigned int rxff_level:2; + unsigned int rxff_inten:1; + unsigned int sof_pol:1; + unsigned int sof_inten:1; + unsigned int mclkdiv:4; + unsigned int hsync_pol:1; + unsigned int ccir_en:1; + unsigned int mclken:1; + unsigned int fcc:1; + unsigned int pack_dir:1; + unsigned int gclk_mode:1; + unsigned int inv_data:1; + unsigned int inv_pclk:1; + unsigned int redge:1; + unsigned int csicnt1_rsv:1; + + /* control reg 3 */ + unsigned int frmcnt:16; + unsigned int frame_reset:1; + unsigned int csi_sup:1; + unsigned int zero_pack_en:1; + unsigned int ecc_int_en:1; + unsigned int ecc_auto_en:1; + + /* fifo counter */ + unsigned int rxcnt; +} csi_config_t; + +typedef void (*csi_irq_callback_t) (void *data, unsigned long status); + +int32_t csi_enable_mclk(int src, bool flag, bool wait); +int32_t csi_init_interface(uint16_t width, uint16_t height, + uint32_t pixel_fmt, csi_signal_cfg_t sig); +int csi_read_mclk_flag(void); +void csi_set_callback(csi_irq_callback_t callback, void *data); +void csi_enable_prpif(uint32_t enable); + +#endif diff -urN linux-2.6.26/drivers/media/video/mxc/capture/mx27_prp.h linux-2.6.26-lab126/drivers/media/video/mxc/capture/mx27_prp.h --- linux-2.6.26/drivers/media/video/mxc/capture/mx27_prp.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/mx27_prp.h 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,310 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mx27_prp.h + * + * @brief Header file for MX27 V4L2 capture driver + * + * @ingroup MXC_V4L2_CAPTURE + */ +#ifndef __MX27_PRP_H__ +#define __MX27_PRP_H__ + +#define PRP_REG(ofs) (IO_ADDRESS(EMMA_BASE_ADDR) + ofs) + +/* Register definitions of PrP */ +#define PRP_CNTL PRP_REG(0x00) +#define PRP_INTRCNTL PRP_REG(0x04) +#define PRP_INTRSTATUS PRP_REG(0x08) +#define PRP_SOURCE_Y_PTR PRP_REG(0x0C) +#define PRP_SOURCE_CB_PTR PRP_REG(0x10) +#define PRP_SOURCE_CR_PTR PRP_REG(0x14) +#define PRP_DEST_RGB1_PTR PRP_REG(0x18) +#define PRP_DEST_RGB2_PTR PRP_REG(0x1C) +#define PRP_DEST_Y_PTR PRP_REG(0x20) +#define PRP_DEST_CB_PTR PRP_REG(0x24) +#define PRP_DEST_CR_PTR PRP_REG(0x28) +#define PRP_SOURCE_FRAME_SIZE PRP_REG(0x2C) +#define PRP_CH1_LINE_STRIDE PRP_REG(0x30) +#define PRP_SRC_PIXEL_FORMAT_CNTL PRP_REG(0x34) +#define PRP_CH1_PIXEL_FORMAT_CNTL PRP_REG(0x38) +#define PRP_CH1_OUT_IMAGE_SIZE PRP_REG(0x3C) +#define PRP_CH2_OUT_IMAGE_SIZE PRP_REG(0x40) +#define PRP_SOURCE_LINE_STRIDE PRP_REG(0x44) +#define PRP_CSC_COEF_012 PRP_REG(0x48) +#define PRP_CSC_COEF_345 PRP_REG(0x4C) +#define PRP_CSC_COEF_678 PRP_REG(0x50) +#define PRP_CH1_RZ_HORI_COEF1 PRP_REG(0x54) +#define PRP_CH1_RZ_HORI_COEF2 PRP_REG(0x58) +#define PRP_CH1_RZ_HORI_VALID PRP_REG(0x5C) +#define PRP_CH1_RZ_VERT_COEF1 PRP_REG(0x60) +#define PRP_CH1_RZ_VERT_COEF2 PRP_REG(0x64) +#define PRP_CH1_RZ_VERT_VALID PRP_REG(0x68) +#define PRP_CH2_RZ_HORI_COEF1 PRP_REG(0x6C) +#define PRP_CH2_RZ_HORI_COEF2 PRP_REG(0x70) +#define PRP_CH2_RZ_HORI_VALID PRP_REG(0x74) +#define PRP_CH2_RZ_VERT_COEF1 PRP_REG(0x78) +#define PRP_CH2_RZ_VERT_COEF2 PRP_REG(0x7C) +#define PRP_CH2_RZ_VERT_VALID PRP_REG(0x80) + +#define B_SET(b) (1 << (b)) + +/* Bit definitions for PrP control register */ +#define PRP_CNTL_RSTVAL 0x28 +#define PRP_CNTL_CH1EN B_SET(0) +#define PRP_CNTL_CH2EN B_SET(1) +#define PRP_CNTL_CSI B_SET(2) +#define PRP_CNTL_IN_32 B_SET(3) +#define PRP_CNTL_IN_RGB B_SET(4) +#define PRP_CNTL_IN_YUV420 0 +#define PRP_CNTL_IN_YUV422 PRP_CNTL_IN_32 +#define PRP_CNTL_IN_RGB16 PRP_CNTL_IN_RGB +#define PRP_CNTL_IN_RGB32 (PRP_CNTL_IN_RGB | PRP_CNTL_IN_32) +#define PRP_CNTL_CH1_RGB8 0 +#define PRP_CNTL_CH1_RGB16 B_SET(5) +#define PRP_CNTL_CH1_RGB32 B_SET(6) +#define PRP_CNTL_CH1_YUV422 (B_SET(5) | B_SET(6)) +#define PRP_CNTL_CH2_YUV420 0 +#define PRP_CNTL_CH2_YUV422 B_SET(7) +#define PRP_CNTL_CH2_YUV444 B_SET(8) +#define PRP_CNTL_CH1_LOOP B_SET(9) +#define PRP_CNTL_CH2_LOOP B_SET(10) +#define PRP_CNTL_AUTODROP B_SET(11) +#define PRP_CNTL_RST B_SET(12) +#define PRP_CNTL_CNTREN B_SET(13) +#define PRP_CNTL_WINEN B_SET(14) +#define PRP_CNTL_UNCHAIN B_SET(15) +#define PRP_CNTL_IN_SKIP_NONE 0 +#define PRP_CNTL_IN_SKIP_1_2 B_SET(16) +#define PRP_CNTL_IN_SKIP_1_3 B_SET(17) +#define PRP_CNTL_IN_SKIP_2_3 (B_SET(16) | B_SET(17)) +#define PRP_CNTL_IN_SKIP_1_4 B_SET(18) +#define PRP_CNTL_IN_SKIP_3_4 (B_SET(16) | B_SET(18)) +#define PRP_CNTL_IN_SKIP_2_5 (B_SET(17) | B_SET(18)) +#define PRP_CNTL_IN_SKIP_3_5 (B_SET(16) | B_SET(17) | B_SET(18)) +#define PRP_CNTL_CH1_SKIP_NONE 0 +#define PRP_CNTL_CH1_SKIP_1_2 B_SET(19) +#define PRP_CNTL_CH1_SKIP_1_3 B_SET(20) +#define PRP_CNTL_CH1_SKIP_2_3 (B_SET(19) | B_SET(20)) +#define PRP_CNTL_CH1_SKIP_1_4 B_SET(21) +#define PRP_CNTL_CH1_SKIP_3_4 (B_SET(19) | B_SET(21)) +#define PRP_CNTL_CH1_SKIP_2_5 (B_SET(20) | B_SET(21)) +#define PRP_CNTL_CH1_SKIP_3_5 (B_SET(19) | B_SET(20) | B_SET(21)) +#define PRP_CNTL_CH2_SKIP_NONE 0 +#define PRP_CNTL_CH2_SKIP_1_2 B_SET(22) +#define PRP_CNTL_CH2_SKIP_1_3 B_SET(23) +#define PRP_CNTL_CH2_SKIP_2_3 (B_SET(22) | B_SET(23)) +#define PRP_CNTL_CH2_SKIP_1_4 B_SET(24) +#define PRP_CNTL_CH2_SKIP_3_4 (B_SET(22) | B_SET(24)) +#define PRP_CNTL_CH2_SKIP_2_5 (B_SET(23) | B_SET(24)) +#define PRP_CNTL_CH2_SKIP_3_5 (B_SET(22) | B_SET(23) | B_SET(24)) +#define PRP_CNTL_FIFO_I128 0 +#define PRP_CNTL_FIFO_I96 B_SET(25) +#define PRP_CNTL_FIFO_I64 B_SET(26) +#define PRP_CNTL_FIFO_I32 (B_SET(25) | B_SET(26)) +#define PRP_CNTL_FIFO_O64 0 +#define PRP_CNTL_FIFO_O48 B_SET(27) +#define PRP_CNTL_FIFO_O32 B_SET(28) +#define PRP_CNTL_FIFO_O16 (B_SET(27) | B_SET(28)) +#define PRP_CNTL_CH2B1 B_SET(29) +#define PRP_CNTL_CH2B2 B_SET(30) +#define PRP_CNTL_CH2_FLOWEN B_SET(31) + +/* Bit definitions for PrP interrupt control register */ +#define PRP_INTRCNTL_RDERR B_SET(0) +#define PRP_INTRCNTL_CH1WERR B_SET(1) +#define PRP_INTRCNTL_CH2WERR B_SET(2) +#define PRP_INTRCNTL_CH1FC B_SET(3) +#define PRP_INTRCNTL_CH2FC B_SET(5) +#define PRP_INTRCNTL_LBOVF B_SET(7) +#define PRP_INTRCNTL_CH2OVF B_SET(8) + +/* Bit definitions for PrP interrupt status register */ +#define PRP_INTRSTAT_RDERR B_SET(0) +#define PRP_INTRSTAT_CH1WERR B_SET(1) +#define PRP_INTRSTAT_CH2WERR B_SET(2) +#define PRP_INTRSTAT_CH2BUF2 B_SET(3) +#define PRP_INTRSTAT_CH2BUF1 B_SET(4) +#define PRP_INTRSTAT_CH1BUF2 B_SET(5) +#define PRP_INTRSTAT_CH1BUF1 B_SET(6) +#define PRP_INTRSTAT_LBOVF B_SET(7) +#define PRP_INTRSTAT_CH2OVF B_SET(8) + +#define PRP_CHANNEL_1 0x1 +#define PRP_CHANNEL_2 0x2 + +/* PRP-CSI config */ +#define PRP_CSI_EN 0x80 +#define PRP_CSI_LOOP (0x40 | PRP_CSI_EN) +#define PRP_CSI_IRQ_FRM (0x08 | PRP_CSI_LOOP) +#define PRP_CSI_IRQ_CH1ERR (0x10 | PRP_CSI_LOOP) +#define PRP_CSI_IRQ_CH2ERR (0x20 | PRP_CSI_LOOP) +#define PRP_CSI_IRQ_ALL (0x38 | PRP_CSI_LOOP) +#define PRP_CSI_SKIP_NONE 0 +#define PRP_CSI_SKIP_1OF2 1 +#define PRP_CSI_SKIP_1OF3 2 +#define PRP_CSI_SKIP_2OF3 3 +#define PRP_CSI_SKIP_1OF4 4 +#define PRP_CSI_SKIP_3OF4 5 +#define PRP_CSI_SKIP_2OF5 6 +#define PRP_CSI_SKIP_4OF5 7 + +#define PRP_PIXIN_RGB565 0x2CA00565 +#define PRP_PIXIN_RGB888 0x41000888 +#define PRP_PIXIN_YUV420 0 +#define PRP_PIXIN_YUYV 0x22000888 +#define PRP_PIXIN_YVYU 0x20100888 +#define PRP_PIXIN_UYVY 0x03080888 +#define PRP_PIXIN_VYUY 0x01180888 +#define PRP_PIXIN_YUV422 0x62080888 + +#define PRP_PIX1_RGB332 0x14400322 +#define PRP_PIX1_RGB565 0x2CA00565 +#define PRP_PIX1_RGB888 0x41000888 +#define PRP_PIX1_YUYV 0x62000888 +#define PRP_PIX1_YVYU 0x60100888 +#define PRP_PIX1_UYVY 0x43080888 +#define PRP_PIX1_VYUY 0x41180888 +#define PRP_PIX1_UNUSED 0 + +#define PRP_PIX2_YUV420 0 +#define PRP_PIX2_YUV422 1 +#define PRP_PIX2_YUV444 4 +#define PRP_PIX2_UNUSED 8 + +#define PRP_ALGO_WIDTH_ANY 0 +#define PRP_ALGO_HEIGHT_ANY 0 +#define PRP_ALGO_WIDTH_BIL 1 +#define PRP_ALGO_WIDTH_AVG 2 +#define PRP_ALGO_HEIGHT_BIL 4 +#define PRP_ALGO_HEIGHT_AVG 8 +#define PRP_ALGO_BYPASS 0x10 + +typedef struct _emma_prp_ratio { + unsigned short num; + unsigned short den; +} emma_prp_ratio; + +/* + * The following definitions are for resizing. Definition values must not + * be changed otherwise decision logic will be wrong. + */ +#define SCALE_RETRY 16 /* retry times if ratio is not supported */ + +#define BC_COEF 3 +#define MAX_TBL 20 +#define SZ_COEF (1 << BC_COEF) + +#define ALGO_AUTO 0 +#define ALGO_BIL 1 +#define ALGO_AVG 2 + +typedef struct { + char tbl[20]; /* table entries */ + char len; /* table length used */ + char algo; /* ALGO_xxx */ + char ratio[20]; /* ratios used */ +} scale_t; + +/* + * structure for prp scaling. + * algorithm - bilinear or averaging for each axis + * PRP_ALGO_WIDTH_x | PRP_ALGO_HEIGHT_x | PRP_ALGO_BYPASS + * PRP_ALGO_BYPASS - Ch1 will not use Ch2 scaling with this flag + */ +typedef struct _emma_prp_scale { + unsigned char algo; + emma_prp_ratio width; + emma_prp_ratio height; +} emma_prp_scale; + +typedef struct emma_prp_cfg { + unsigned int in_pix; /* PRP_PIXIN_xxx */ + unsigned short in_width; /* image width, 32 - 2044 */ + unsigned short in_height; /* image height, 32 - 2044 */ + unsigned char in_csi; /* PRP_CSI_SKIP_x | PRP_CSI_LOOP */ + unsigned short in_line_stride; /* in_line_stride and in_line_skip */ + unsigned short in_line_skip; /* allow cropping from CSI */ + unsigned int in_ptr; /* bus address */ + /* + * in_csc[9] = 1 -> Y-16 + * if in_csc[1..9] == 0 + * in_csc[0] represents YUV range 0-3 = A0,A1,B0,B1; + * else + * in_csc[0..9] represents either format + */ + unsigned short in_csc[10]; + + unsigned char ch2_pix; /* PRP_PIX2_xxx */ + emma_prp_scale ch2_scale; /* resizing paramters */ + unsigned short ch2_width; /* 4-2044, 0 = scaled */ + unsigned short ch2_height; /* 4-2044, 0 = scaled */ + unsigned int ch2_ptr; /* bus addr */ + unsigned int ch2_ptr2; /* bus addr for 2nd buf (loop mode) */ + unsigned char ch2_csi; /* PRP_CSI_SKIP_x | PRP_CSI_LOOP */ + + unsigned int ch1_pix; /* PRP_PIX1_xxx */ + emma_prp_scale ch1_scale; /* resizing parameters */ + unsigned short ch1_width; /* 4-2044, 0 = scaled */ + unsigned short ch1_height; /* 4-2044, 0 = scaled */ + unsigned short ch1_stride; /* 4-4088, 0 = ch1_width */ + unsigned int ch1_ptr; /* bus addr */ + unsigned int ch1_ptr2; /* bus addr for 2nd buf (loop mode) */ + unsigned char ch1_csi; /* PRP_CSI_SKIP_x | PRP_CSI_LOOP */ + + /* + * channel resizing coefficients + * scale[0] for channel 1 width + * scale[1] for channel 1 height + * scale[2] for channel 2 width + * scale[3] for channel 2 height + */ + scale_t scale[4]; +} emma_prp_cfg; + +int prphw_reset(void); +int prphw_enable(int channel); +int prphw_disable(int channel); +int prphw_inptr(emma_prp_cfg *); +int prphw_ch1ptr(emma_prp_cfg *); +int prphw_ch1ptr2(emma_prp_cfg *); +int prphw_ch2ptr(emma_prp_cfg *); +int prphw_ch2ptr2(emma_prp_cfg *); +int prphw_cfg(emma_prp_cfg *); +int prphw_isr(void); +void prphw_init(void); +void prphw_exit(void); + +/* + * scale out coefficient table + * din in scale numerator + * dout in scale denominator + * inv in pre-scale dimension + * vout in/out post-scale output dimension + * pout out post-scale internal dimension [opt] + * retry in retry times (round the output length) when need + */ +int prp_scale(scale_t * pscale, int din, int dout, int inv, + unsigned short *vout, unsigned short *pout, int retry); + +int prp_init(void *dev_id); +void prp_exit(void *dev_id); +int prp_enc_select(void *data); +int prp_enc_deselect(void *data); +int prp_vf_select(void *data); +int prp_vf_deselect(void *data); +int prp_still_select(void *data); +int prp_still_deselect(void *data); + +#endif /* __MX27_PRP_H__ */ diff -urN linux-2.6.26/drivers/media/video/mxc/capture/mx27_prphw.c linux-2.6.26-lab126/drivers/media/video/mxc/capture/mx27_prphw.c --- linux-2.6.26/drivers/media/video/mxc/capture/mx27_prphw.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/mx27_prphw.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,1099 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mx27_prphw.c + * + * @brief MX27 Video For Linux 2 capture driver + * + * @ingroup MXC_V4L2_CAPTURE + */ +#include +#include +#include +#include +#include +#include + +#include "mx27_prp.h" + +#define PRP_MIN_IN_WIDTH 32 +#define PRP_MAX_IN_WIDTH 2044 +#define PRP_MIN_IN_HEIGHT 32 +#define PRP_MAX_IN_HEIGHT 2044 + +typedef struct _coeff_t { + unsigned long coeff[2]; + unsigned long cntl; +} coeff_t[2][2]; + +static coeff_t *PRP_RSZ_COEFF = (coeff_t *) PRP_CH1_RZ_HORI_COEF1; + +static unsigned char scale_get(scale_t * t, + unsigned char *i, unsigned char *out); +static int gcd(int x, int y); +static int ratio(int x, int y, int *den); +static int prp_scale_bilinear(scale_t * t, int coeff, int base, int nxt); +static int prp_scale_ave(scale_t * t, unsigned char base); +static int ave_scale(scale_t * t, int inv, int outv); +static int scale(scale_t * t, int inv, int outv); + +/*! + * @param t table + * @param i table index + * @param out bilinear # input pixels to advance + * average whether result is ready for output + * @return coefficient +*/ +static unsigned char scale_get(scale_t * t, unsigned char *i, + unsigned char *out) +{ + unsigned char c; + + c = t->tbl[*i]; + (*i)++; + *i %= t->len; + + if (out) { + if (t->algo == ALGO_BIL) { + for ((*out) = 1; + (*i) && ((*i) < t->len) && !t->tbl[(*i)]; (*i)++) { + (*out)++; + } + if ((*i) == t->len) + (*i) = 0; + } else + *out = c >> BC_COEF; + } + + c &= SZ_COEF - 1; + + if (c == SZ_COEF - 1) + c = SZ_COEF; + + return c; +} + +/*! + * @brief Get maximum common divisor. + * @param x First input value + * @param y Second input value + * @return Maximum common divisor of x and y + */ +static int gcd(int x, int y) +{ + int k; + + if (x < y) { + k = x; + x = y; + y = k; + } + + while ((k = x % y)) { + x = y; + y = k; + } + + return y; +} + +/*! + * @brief Get ratio. + * @param x First input value + * @param y Second input value + * @param den Denominator of the ratio (corresponding to y) + * @return Numerator of the ratio (corresponding to x) + */ +static int ratio(int x, int y, int *den) +{ + int g; + + if (!x || !y) + return 0; + + g = gcd(x, y); + *den = y / g; + + return x / g; +} + +/*! + * @brief Build PrP coefficient entry based on bilinear algorithm + * + * @param t The pointer to scale_t structure + * @param coeff The weighting coefficient + * @param base The base of the coefficient + * @param nxt Number of pixels to be read + * + * @return The length of current coefficient table on success + * -1 on failure + */ +static int prp_scale_bilinear(scale_t * t, int coeff, int base, int nxt) +{ + int i; + + if (t->len >= sizeof(t->tbl)) + return -1; + + coeff = ((coeff << BC_COEF) + (base >> 1)) / base; + if (coeff >= SZ_COEF - 1) + coeff--; + + coeff |= SZ_COEF; + t->tbl[(int)t->len++] = (unsigned char)coeff; + + for (i = 1; i < nxt; i++) { + if (t->len >= MAX_TBL) + return -1; + + t->tbl[(int)t->len++] = 0; + } + + return t->len; +} + +#define _bary(name) static const unsigned char name[] + +_bary(c1) = { +7}; + +_bary(c2) = { +4, 4}; + +_bary(c3) = { +2, 4, 2}; + +_bary(c4) = { +2, 2, 2, 2}; + +_bary(c5) = { +1, 2, 2, 2, 1}; + +_bary(c6) = { +1, 1, 2, 2, 1, 1}; + +_bary(c7) = { +1, 1, 1, 2, 1, 1, 1}; + +_bary(c8) = { +1, 1, 1, 1, 1, 1, 1, 1}; + +_bary(c9) = { +1, 1, 1, 1, 1, 1, 1, 1, 0}; + +_bary(c10) = { +0, 1, 1, 1, 1, 1, 1, 1, 1, 0}; + +_bary(c11) = { +0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0}; + +_bary(c12) = { +0, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 0}; + +_bary(c13) = { +0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0}; + +_bary(c14) = { +0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 0, 1, 0}; + +_bary(c15) = { +0, 1, 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 0, 1, 0}; + +_bary(c16) = { +1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0}; + +_bary(c17) = { +0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0}; + +_bary(c18) = { +0, 1, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 1, 0, 1, 0}; + +_bary(c19) = { +0, 1, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0}; + +_bary(c20) = { +0, 1, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0}; + +static const unsigned char *ave_coeff[] = { + c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, + c11, c12, c13, c14, c15, c16, c17, c18, c19, c20 +}; + +/*! + * @brief Build PrP coefficient table based on average algorithm + * + * @param t The pointer to scale_t structure + * @param base The base of the coefficient + * + * @return The length of current coefficient table on success + * -1 on failure + */ +static int prp_scale_ave(scale_t * t, unsigned char base) +{ + if (t->len + base > sizeof(t->tbl)) + return -1; + + memcpy(&t->tbl[(int)t->len], ave_coeff[(int)base - 1], base); + t->len = (unsigned char)(t->len + base); + t->tbl[t->len - 1] |= SZ_COEF; + + return t->len; +} + +/*! + * @brief Build PrP coefficient table based on average algorithm + * + * @param t The pointer to scale_t structure + * @param inv Input resolution + * @param outv Output resolution + * + * @return The length of current coefficient table on success + * -1 on failure + */ +static int ave_scale(scale_t * t, int inv, int outv) +{ + int ratio_count; + + ratio_count = 0; + if (outv != 1) { + unsigned char a[20]; + int v; + + /* split n:m into multiple n[i]:1 */ + for (v = 0; v < outv; v++) + a[v] = (unsigned char)(inv / outv); + + inv %= outv; + if (inv) { + /* find start of next layer */ + v = (outv - inv) >> 1; + inv += v; + for (; v < inv; v++) + a[v]++; + } + + for (v = 0; v < outv; v++) { + if (prp_scale_ave(t, a[v]) < 0) + return -1; + + t->ratio[ratio_count] = a[v]; + ratio_count++; + } + } else if (prp_scale_ave(t, inv) < 0) { + return -1; + } else { + t->ratio[ratio_count++] = (char)inv; + ratio_count++; + } + + return t->len; +} + +/*! + * @brief Build PrP coefficient table + * + * @param t The pointer to scale_t structure + * @param inv input resolution reduced ratio + * @param outv output resolution reduced ratio + * + * @return The length of current coefficient table on success + * -1 on failure + */ +static int scale(scale_t * t, int inv, int outv) +{ + int v; /* overflow counter */ + int coeff, nxt; /* table output */ + + t->len = 0; + if (t->algo == ALGO_AUTO) { + /* automatic choice - bilinear for shrinking less than 2:1 */ + t->algo = ((outv != inv) && ((2 * outv) > inv)) ? + ALGO_BIL : ALGO_AVG; + } + + /* 1:1 resize must use averaging, bilinear will hang */ + if ((inv == outv) && (t->algo == ALGO_BIL)) { + pr_debug("Warning: 1:1 resize must use averaging algo\n"); + t->algo = ALGO_AVG; + } + + memset(t->tbl, 0, sizeof(t->tbl)); + if (t->algo == ALGO_BIL) { + t->ratio[0] = (char)inv; + t->ratio[1] = (char)outv; + } else + memset(t->ratio, 0, sizeof(t->ratio)); + + if (inv == outv) { + /* force scaling */ + t->ratio[0] = 1; + if (t->algo == ALGO_BIL) + t->ratio[1] = 1; + + return prp_scale_ave(t, 1); + } + + if (inv < outv) { + pr_debug("Upscaling not supported %d:%d\n", inv, outv); + return -1; + } + + if (t->algo != ALGO_BIL) + return ave_scale(t, inv, outv); + + v = 0; + if (inv >= 2 * outv) { + /* downscale: >=2:1 bilinear approximation */ + coeff = inv - 2 * outv; + v = 0; + nxt = 0; + do { + v += coeff; + nxt = 2; + while (v >= outv) { + v -= outv; + nxt++; + } + + if (prp_scale_bilinear(t, 1, 2, nxt) < 0) + return -1; + } while (v); + } else { + /* downscale: bilinear */ + int in_pos_inc = 2 * outv; + int out_pos = inv; + int out_pos_inc = 2 * inv; + int init_carry = inv - outv; + int carry = init_carry; + + v = outv + in_pos_inc; + do { + coeff = v - out_pos; + out_pos += out_pos_inc; + carry += out_pos_inc; + for (nxt = 0; v < out_pos; nxt++) { + v += in_pos_inc; + carry -= in_pos_inc; + } + if (prp_scale_bilinear(t, coeff, in_pos_inc, nxt) < 0) + return -1; + } while (carry != init_carry); + } + return t->len; +} + +/*! + * @brief Build PrP coefficient table + * + * @param pscale The pointer to scale_t structure which holdes + * coefficient tables + * @param din Scale ratio numerator + * @param dout Scale ratio denominator + * @param inv Input resolution + * @param vout Output resolution + * @param pout Internal output resolution + * @param retry Retry times (round the output length) when need + * + * @return Zero on success, others on failure + */ +int prp_scale(scale_t * pscale, int din, int dout, int inv, + unsigned short *vout, unsigned short *pout, int retry) +{ + int num; + int den; + unsigned short outv; + + /* auto-generation of values */ + if (!(dout && din)) { + if (!*vout) + dout = din = 1; + else { + din = inv; + dout = *vout; + } + } + + if (din < dout) { + pr_debug("Scale err, unsupported ratio %d : %d\n", din, dout); + return -1; + } + + lp_retry: + num = ratio(din, dout, &den); + if (!num) { + pr_debug("Scale err, unsupported ratio %d : %d\n", din, dout); + return -1; + } + + if (num > MAX_TBL || scale(pscale, num, den) < 0) { + dout++; + if (retry--) + goto lp_retry; + + pr_debug("Scale err, unsupported ratio %d : %d\n", num, den); + return -1; + } + + if (pscale->algo == ALGO_BIL) { + unsigned char i, j, k; + + outv = + (unsigned short)(inv / pscale->ratio[0] * pscale->ratio[1]); + inv %= pscale->ratio[0]; + for (i = j = 0; inv > 0; j++) { + unsigned char nxt; + + k = scale_get(pscale, &i, &nxt); + if (inv == 1 && k < SZ_COEF) { + /* needs 2 pixels for this output */ + break; + } + inv -= nxt; + } + outv = outv + j; + } else { + unsigned char i, tot; + + for (tot = i = 0; pscale->ratio[i]; i++) + tot = tot + pscale->ratio[i]; + + outv = (unsigned short)(inv / tot) * i; + inv %= tot; + for (i = 0; inv > 0; i++, outv++) + inv -= pscale->ratio[i]; + } + + if (!(*vout) || ((*vout) > outv)) + *vout = outv; + + if (pout) + *pout = outv; + + return 0; +} + +/*! + * @brief Reset PrP block + */ +int prphw_reset(void) +{ + unsigned long val; + unsigned long flag; + int i; + + flag = PRP_CNTL_RST; + val = PRP_CNTL_RSTVAL; + + __raw_writel(flag, PRP_CNTL); + + /* timeout */ + for (i = 0; i < 1000; i++) { + if (!(__raw_readl(PRP_CNTL) & flag)) { + pr_debug("PrP reset over\n"); + break; + } + msleep(1); + } + + /* verify reset value */ + if (__raw_readl(PRP_CNTL) != val) { + pr_info("PrP reset err, val = 0x%08X\n", __raw_readl(PRP_CNTL)); + return -1; + } + + return 0; +} + +/*! + * @brief Enable PrP channel. + * @param channel Channel number to be enabled + * @return Zero on success, others on failure + */ +int prphw_enable(int channel) +{ + unsigned long val; + + val = __raw_readl(PRP_CNTL); + if (channel & PRP_CHANNEL_1) + val |= PRP_CNTL_CH1EN; + if (channel & PRP_CHANNEL_2) + val |= (PRP_CNTL_CH2EN | PRP_CNTL_CH2_FLOWEN); + + __raw_writel(val, PRP_CNTL); + + return 0; +} + +/*! + * @brief Disable PrP channel. + * @param channel Channel number to be disable + * @return Zero on success, others on failure + */ +int prphw_disable(int channel) +{ + unsigned long val; + + val = __raw_readl(PRP_CNTL); + if (channel & PRP_CHANNEL_1) + val &= ~PRP_CNTL_CH1EN; + if (channel & PRP_CHANNEL_2) + val &= ~(PRP_CNTL_CH2EN | PRP_CNTL_CH2_FLOWEN); + + __raw_writel(val, PRP_CNTL); + + return 0; +} + +/*! + * @brief Set PrP input buffer address. + * @param cfg Pointer to PrP configuration parameter + * @return Zero on success, others on failure + */ +int prphw_inptr(emma_prp_cfg * cfg) +{ + if (cfg->in_csi & PRP_CSI_EN) + return -1; + + __raw_writel(cfg->in_ptr, PRP_SOURCE_Y_PTR); + if (cfg->in_pix == PRP_PIXIN_YUV420) { + u32 size; + + size = cfg->in_line_stride * cfg->in_height; + __raw_writel(cfg->in_ptr + size, PRP_SOURCE_CB_PTR); + __raw_writel(cfg->in_ptr + size + (size >> 2), + PRP_SOURCE_CR_PTR); + } + return 0; +} + +/*! + * @brief Set PrP channel 1 output buffer 1 address. + * @param cfg Pointer to PrP configuration parameter + * @return Zero on success, others on failure + */ +int prphw_ch1ptr(emma_prp_cfg * cfg) +{ + if (cfg->ch1_pix == PRP_PIX1_UNUSED) + return -1; + + __raw_writel(cfg->ch1_ptr, PRP_DEST_RGB1_PTR); + + /* support double buffer in loop mode only */ + if ((cfg->in_csi & PRP_CSI_LOOP) == PRP_CSI_LOOP) { + if (cfg->ch1_ptr2) + __raw_writel(cfg->ch1_ptr2, PRP_DEST_RGB2_PTR); + else + __raw_writel(cfg->ch1_ptr, PRP_DEST_RGB2_PTR); + } + + return 0; +} + +/*! + * @brief Set PrP channel 1 output buffer 2 address. + * @param cfg Pointer to PrP configuration parameter + * @return Zero on success, others on failure + */ +int prphw_ch1ptr2(emma_prp_cfg * cfg) +{ + if (cfg->ch1_pix == PRP_PIX1_UNUSED || + (cfg->in_csi & PRP_CSI_LOOP) != PRP_CSI_LOOP) + return -1; + + if (cfg->ch1_ptr2) + __raw_writel(cfg->ch1_ptr2, PRP_DEST_RGB2_PTR); + else + return -1; + + return 0; +} + +/*! + * @brief Set PrP channel 2 output buffer 1 address. + * @param cfg Pointer to PrP configuration parameter + * @return Zero on success, others on failure + */ +int prphw_ch2ptr(emma_prp_cfg * cfg) +{ + u32 size; + + if (cfg->ch2_pix == PRP_PIX2_UNUSED) + return -1; + + __raw_writel(cfg->ch2_ptr, PRP_DEST_Y_PTR); + + if (cfg->ch2_pix == PRP_PIX2_YUV420) { + size = cfg->ch2_width * cfg->ch2_height; + __raw_writel(cfg->ch2_ptr + size, PRP_DEST_CB_PTR); + __raw_writel(cfg->ch2_ptr + size + (size >> 2), + PRP_DEST_CR_PTR); + } + + __raw_writel(__raw_readl(PRP_CNTL) | PRP_CNTL_CH2B1, PRP_CNTL); + return 0; +} + +/*! + * @brief Set PrP channel 2 output buffer 2 address. + * @param cfg Pointer to PrP configuration parameter + * @return Zero on success, others on failure + */ +int prphw_ch2ptr2(emma_prp_cfg * cfg) +{ + u32 size; + + if (cfg->ch2_pix == PRP_PIX2_UNUSED || + (cfg->in_csi & PRP_CSI_LOOP) != PRP_CSI_LOOP) + return -1; + + __raw_writel(cfg->ch2_ptr2, PRP_SOURCE_Y_PTR); + if (cfg->ch2_pix == PRP_PIX2_YUV420) { + size = cfg->ch2_width * cfg->ch2_height; + __raw_writel(cfg->ch2_ptr2 + size, PRP_SOURCE_CB_PTR); + __raw_writel(cfg->ch2_ptr2 + size + (size >> 2), + PRP_SOURCE_CR_PTR); + } + + __raw_writel(__raw_readl(PRP_CNTL) | PRP_CNTL_CH2B2, PRP_CNTL); + return 0; +} + +/*! + * @brief Build CSC table + * @param csc CSC table + * in csc[0]=index 0..3 : A.1 A.0 B.1 B.0 + * csc[1]=direction 0 : YUV2RGB 1 : RGB2YUV + * out csc[0..4] are coefficients c[9] is offset + * csc[0..8] are coefficients c[9] is offset + */ +void csc_tbl(short csc[10]) +{ + static const unsigned short _r2y[][9] = { + {0x4D, 0x4B, 0x3A, 0x57, 0x55, 0x40, 0x40, 0x6B, 0x29}, + {0x42, 0x41, 0x32, 0x4C, 0x4A, 0x38, 0x38, 0x5E, 0x24}, + {0x36, 0x5C, 0x25, 0x3B, 0x63, 0x40, 0x40, 0x74, 0x18}, + {0x2F, 0x4F, 0x20, 0x34, 0x57, 0x38, 0x38, 0x66, 0x15}, + }; + static const unsigned short _y2r[][5] = { + {0x80, 0xb4, 0x2c, 0x5b, 0x0e4}, + {0x95, 0xcc, 0x32, 0x68, 0x104}, + {0x80, 0xca, 0x18, 0x3c, 0x0ec}, + {0x95, 0xe5, 0x1b, 0x44, 0x1e0}, + }; + unsigned short *_csc; + int _csclen; + + csc[9] = csc[0] & 1; + _csclen = csc[0] & 3; + + if (csc[1]) { + _csc = (unsigned short *)_r2y[_csclen]; + _csclen = sizeof(_r2y[0]); + } else { + _csc = (unsigned short *)_y2r[_csclen]; + _csclen = sizeof(_y2r[0]); + memset(csc + 5, 0, sizeof(short) * 4); + } + memcpy(csc, _csc, _csclen); +} + +/*! + * @brief Setup PrP resize coefficient registers + * + * @param ch PrP channel number + * @param dir Direction, 0 - horizontal, 1 - vertical + * @param scale The pointer to scale_t structure + */ +static void prp_set_scaler(int ch, int dir, scale_t * scale) +{ + int i; + unsigned int coeff[2]; + unsigned int valid; + + for (coeff[0] = coeff[1] = valid = 0, i = 19; i >= 0; i--) { + int j; + + j = i > 9 ? 1 : 0; + coeff[j] = (coeff[j] << BC_COEF) | + (scale->tbl[i] & (SZ_COEF - 1)); + + if (i == 5 || i == 15) + coeff[j] <<= 1; + + valid = (valid << 1) | (scale->tbl[i] >> BC_COEF); + } + + valid |= (scale->len << 24) | ((2 - scale->algo) << 31); + + for (i = 0; i < 2; i++) + (*PRP_RSZ_COEFF)[1 - ch][dir].coeff[i] = coeff[i]; + + (*PRP_RSZ_COEFF)[1 - ch][dir].cntl = valid; +} + +/*! + * @brief Setup PrP registers relevant to input. + * @param cfg Pointer to PrP configuration parameter + * @param prp_cntl Holds the value for PrP control register + * @return Zero on success, others on failure + */ +static int prphw_input_cfg(emma_prp_cfg * cfg, unsigned long *prp_cntl) +{ + unsigned long mask; + + switch (cfg->in_pix) { + case PRP_PIXIN_YUV420: + *prp_cntl |= PRP_CNTL_IN_YUV420; + mask = 0x7; + break; + case PRP_PIXIN_YUYV: + case PRP_PIXIN_YVYU: + case PRP_PIXIN_UYVY: + case PRP_PIXIN_VYUY: + *prp_cntl |= PRP_CNTL_IN_YUV422; + mask = 0x1; + break; + case PRP_PIXIN_RGB565: + *prp_cntl |= PRP_CNTL_IN_RGB16; + mask = 0x1; + break; + case PRP_PIXIN_RGB888: + *prp_cntl |= PRP_CNTL_IN_RGB32; + mask = 0; + break; + default: + pr_debug("Unsupported input pix format 0x%08X\n", cfg->in_pix); + return -1; + } + + /* align the input image width */ + if (cfg->in_width & mask) { + pr_debug("in_width misaligned. in_width=%d\n", cfg->in_width); + return -1; + } + + if ((cfg->in_width < PRP_MIN_IN_WIDTH) + || (cfg->in_width > PRP_MAX_IN_WIDTH)) { + pr_debug("Unsupported input width %d\n", cfg->in_width); + return -1; + } + + cfg->in_height &= ~1; /* truncate to make even */ + + if ((cfg->in_height < PRP_MIN_IN_HEIGHT) + || (cfg->in_height > PRP_MAX_IN_HEIGHT)) { + pr_debug("Unsupported input height %d\n", cfg->in_height); + return -1; + } + + if (!(cfg->in_csi & PRP_CSI_EN)) + if (!cfg->in_line_stride) + cfg->in_line_stride = cfg->in_width; + + __raw_writel(cfg->in_pix, PRP_SRC_PIXEL_FORMAT_CNTL); + __raw_writel((cfg->in_width << 16) | cfg->in_height, + PRP_SOURCE_FRAME_SIZE); + __raw_writel((cfg->in_line_skip << 16) | cfg->in_line_stride, + PRP_SOURCE_LINE_STRIDE); + + if (!(cfg->in_csi & PRP_CSI_EN)) { + __raw_writel(cfg->in_ptr, PRP_SOURCE_Y_PTR); + if (cfg->in_pix == PRP_PIXIN_YUV420) { + unsigned int size; + + size = cfg->in_line_stride * cfg->in_height; + __raw_writel(cfg->in_ptr + size, PRP_SOURCE_CB_PTR); + __raw_writel(cfg->in_ptr + size + (size >> 2), + PRP_SOURCE_CR_PTR); + } + } + + /* always cropping */ + *prp_cntl |= PRP_CNTL_WINEN; + + /* color space conversion */ + if (!cfg->in_csc[1]) { + if (cfg->in_csc[0] > 3) { + pr_debug("in_csc invalid 0x%X\n", cfg->in_csc[0]); + return -1; + } + if ((cfg->in_pix == PRP_PIXIN_RGB565) + || (cfg->in_pix == PRP_PIXIN_RGB888)) + cfg->in_csc[1] = 1; + else + cfg->in_csc[0] = 0; + csc_tbl(cfg->in_csc); + } + + __raw_writel((cfg->in_csc[0] << 21) | (cfg->in_csc[1] << 11) + | cfg->in_csc[2], PRP_CSC_COEF_012); + __raw_writel((cfg->in_csc[3] << 21) | (cfg->in_csc[4] << 11) + | cfg->in_csc[5], PRP_CSC_COEF_345); + __raw_writel((cfg->in_csc[6] << 21) | (cfg->in_csc[7] << 11) + | cfg->in_csc[8] | (cfg->in_csc[9] << 31), + PRP_CSC_COEF_678); + + if (cfg->in_csi & PRP_CSI_EN) { + *prp_cntl |= PRP_CNTL_CSI; + + /* loop mode enable, ch1 ch2 together */ + if ((cfg->in_csi & PRP_CSI_LOOP) == PRP_CSI_LOOP) + *prp_cntl |= (PRP_CNTL_CH1_LOOP | PRP_CNTL_CH2_LOOP); + } + + return 0; +} + +/*! + * @brief Setup PrP registers relevant to channel 2. + * @param cfg Pointer to PrP configuration parameter + * @param prp_cntl Holds the value for PrP control register + * @return Zero on success, others on failure + */ +static int prphw_ch2_cfg(emma_prp_cfg * cfg, unsigned long *prp_cntl) +{ + switch (cfg->ch2_pix) { + case PRP_PIX2_YUV420: + *prp_cntl |= PRP_CNTL_CH2_YUV420; + break; + case PRP_PIX2_YUV422: + *prp_cntl |= PRP_CNTL_CH2_YUV422; + break; + case PRP_PIX2_YUV444: + *prp_cntl |= PRP_CNTL_CH2_YUV444; + break; + case PRP_PIX2_UNUSED: + return 0; + default: + pr_debug("Unsupported channel 2 pix format 0x%08X\n", + cfg->ch2_pix); + return -1; + } + + if (cfg->ch2_pix == PRP_PIX2_YUV420) { + cfg->ch2_height &= ~1; /* ensure U/V presence */ + cfg->ch2_width &= ~7; /* ensure U/V word aligned */ + } else if (cfg->ch2_pix == PRP_PIX2_YUV422) { + cfg->ch2_width &= ~1; /* word aligned */ + } + + __raw_writel((cfg->ch2_width << 16) | cfg->ch2_height, + PRP_CH2_OUT_IMAGE_SIZE); + + if (cfg->ch2_pix == PRP_PIX2_YUV420) { + u32 size; + + /* Luminanance band start address */ + __raw_writel(cfg->ch2_ptr, PRP_DEST_Y_PTR); + + if ((cfg->in_csi & PRP_CSI_LOOP) == PRP_CSI_LOOP) { + if (!cfg->ch2_ptr2) + __raw_writel(cfg->ch2_ptr, PRP_SOURCE_Y_PTR); + else + __raw_writel(cfg->ch2_ptr2, PRP_SOURCE_Y_PTR); + } + + /* Cb and Cr band start address */ + size = cfg->ch2_width * cfg->ch2_height; + __raw_writel(cfg->ch2_ptr + size, PRP_DEST_CB_PTR); + __raw_writel(cfg->ch2_ptr + size + (size >> 2), + PRP_DEST_CR_PTR); + + if ((cfg->in_csi & PRP_CSI_LOOP) == PRP_CSI_LOOP) { + if (!cfg->ch2_ptr2) { + __raw_writel(cfg->ch2_ptr + size, + PRP_SOURCE_CB_PTR); + __raw_writel(cfg->ch2_ptr + size + (size >> 2), + PRP_SOURCE_CR_PTR); + } else { + __raw_writel(cfg->ch2_ptr2 + size, + PRP_SOURCE_CB_PTR); + __raw_writel(cfg->ch2_ptr2 + size + (size >> 2), + PRP_SOURCE_CR_PTR); + } + } + } else { /* Pixel interleaved YUV422 or YUV444 */ + __raw_writel(cfg->ch2_ptr, PRP_DEST_Y_PTR); + + if ((cfg->in_csi & PRP_CSI_LOOP) == PRP_CSI_LOOP) { + if (!cfg->ch2_ptr2) + __raw_writel(cfg->ch2_ptr, PRP_SOURCE_Y_PTR); + else + __raw_writel(cfg->ch2_ptr2, PRP_SOURCE_Y_PTR); + } + } + *prp_cntl |= PRP_CNTL_CH2B1 | PRP_CNTL_CH2B2; + + return 0; +} + +/*! + * @brief Setup PrP registers relevant to channel 1. + * @param cfg Pointer to PrP configuration parameter + * @param prp_cntl Holds the value for PrP control register + * @return Zero on success, others on failure + */ +static int prphw_ch1_cfg(emma_prp_cfg * cfg, unsigned long *prp_cntl) +{ + int ch1_bpp = 0; + + switch (cfg->ch1_pix) { + case PRP_PIX1_RGB332: + *prp_cntl |= PRP_CNTL_CH1_RGB8; + ch1_bpp = 1; + break; + case PRP_PIX1_RGB565: + *prp_cntl |= PRP_CNTL_CH1_RGB16; + ch1_bpp = 2; + break; + case PRP_PIX1_RGB888: + *prp_cntl |= PRP_CNTL_CH1_RGB32; + ch1_bpp = 4; + break; + case PRP_PIX1_YUYV: + case PRP_PIX1_YVYU: + case PRP_PIX1_UYVY: + case PRP_PIX1_VYUY: + *prp_cntl |= PRP_CNTL_CH1_YUV422; + ch1_bpp = 2; + break; + case PRP_PIX1_UNUSED: + return 0; + default: + pr_debug("Unsupported channel 1 pix format 0x%08X\n", + cfg->ch1_pix); + return -1; + } + + /* parallel or cascade resize */ + if (cfg->ch1_scale.algo & PRP_ALGO_BYPASS) + *prp_cntl |= PRP_CNTL_UNCHAIN; + + /* word align */ + if (ch1_bpp == 2) + cfg->ch1_width &= ~1; + else if (ch1_bpp == 1) + cfg->ch1_width &= ~3; + + if (!cfg->ch1_stride) + cfg->ch1_stride = cfg->ch1_width; + + __raw_writel(cfg->ch1_pix, PRP_CH1_PIXEL_FORMAT_CNTL); + __raw_writel((cfg->ch1_width << 16) | cfg->ch1_height, + PRP_CH1_OUT_IMAGE_SIZE); + __raw_writel(cfg->ch1_stride * ch1_bpp, PRP_CH1_LINE_STRIDE); + __raw_writel(cfg->ch1_ptr, PRP_DEST_RGB1_PTR); + + /* double buffer for loop mode */ + if ((cfg->in_csi & PRP_CSI_LOOP) == PRP_CSI_LOOP) { + if (cfg->ch1_ptr2) + __raw_writel(cfg->ch1_ptr2, PRP_DEST_RGB2_PTR); + else + __raw_writel(cfg->ch1_ptr, PRP_DEST_RGB2_PTR); + } + + return 0; +} + +/*! + * @brief Setup PrP registers. + * @param cfg Pointer to PrP configuration parameter + * @return Zero on success, others on failure + */ +int prphw_cfg(emma_prp_cfg * cfg) +{ + unsigned long prp_cntl = 0; + unsigned long val; + + /* input pixel format checking */ + if (prphw_input_cfg(cfg, &prp_cntl)) + return -1; + + if (prphw_ch2_cfg(cfg, &prp_cntl)) + return -1; + + if (prphw_ch1_cfg(cfg, &prp_cntl)) + return -1; + + /* register setting */ + __raw_writel(prp_cntl, PRP_CNTL); + + /* interrupt configuration */ + val = PRP_INTRCNTL_RDERR | PRP_INTRCNTL_LBOVF; + if (cfg->ch1_pix != PRP_PIX1_UNUSED) + val |= PRP_INTRCNTL_CH1FC | PRP_INTRCNTL_CH1WERR; + if (cfg->ch2_pix != PRP_PIX2_UNUSED) + val |= + PRP_INTRCNTL_CH2FC | PRP_INTRCNTL_CH2WERR | + PRP_INTRCNTL_CH2OVF; + __raw_writel(val, PRP_INTRCNTL); + + prp_set_scaler(1, 0, &cfg->scale[0]); /* Channel 1 width */ + prp_set_scaler(1, 1, &cfg->scale[1]); /* Channel 1 height */ + prp_set_scaler(0, 0, &cfg->scale[2]); /* Channel 2 width */ + prp_set_scaler(0, 1, &cfg->scale[3]); /* Channel 2 height */ + + return 0; +} + +/*! + * @brief Check PrP interrupt status. + * @return PrP interrupt status + */ +int prphw_isr(void) +{ + int status; + + status = __raw_readl(PRP_INTRSTATUS) & 0x1FF; + + if (status & (PRP_INTRSTAT_RDERR | PRP_INTRSTAT_CH1WERR | + PRP_INTRSTAT_CH2WERR)) + pr_debug("isr bus error. status= 0x%08X\n", status); + else if (status & PRP_INTRSTAT_CH2OVF) + pr_debug("isr ch 2 buffer overflow. status= 0x%08X\n", status); + else if (status & PRP_INTRSTAT_LBOVF) + pr_debug("isr line buffer overflow. status= 0x%08X\n", status); + + /* silicon bug?? enable bit does not self clear? */ + if (!(__raw_readl(PRP_CNTL) & PRP_CNTL_CH1_LOOP)) + __raw_writel(__raw_readl(PRP_CNTL) & (~PRP_CNTL_CH1EN), + PRP_CNTL); + if (!(__raw_readl(PRP_CNTL) & PRP_CNTL_CH2_LOOP)) + __raw_writel(__raw_readl(PRP_CNTL) & (~PRP_CNTL_CH2EN), + PRP_CNTL); + + __raw_writel(status, PRP_INTRSTATUS); /* clr irq */ + + return status; +} + +static struct clk *emma_clk; + +/*! + * @brief PrP module clock enable + */ +void prphw_init(void) +{ + emma_clk = clk_get(NULL, "emma_clk"); + clk_enable(emma_clk); +} + +/*! + * @brief PrP module clock disable + */ +void prphw_exit(void) +{ + clk_disable(emma_clk); + clk_put(emma_clk); +} diff -urN linux-2.6.26/drivers/media/video/mxc/capture/mx27_prpsw.c linux-2.6.26-lab126/drivers/media/video/mxc/capture/mx27_prpsw.c --- linux-2.6.26/drivers/media/video/mxc/capture/mx27_prpsw.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/mx27_prpsw.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,1042 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mx27_prpsw.c + * + * @brief MX27 Video For Linux 2 capture driver + * + * @ingroup MXC_V4L2_CAPTURE + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mxc_v4l2_capture.h" +#include "mx27_prp.h" +#include "mx27_csi.h" +#include "../drivers/video/mxc/mx2fb.h" +#include "../opl/opl.h" + +#define MEAN_COEF (SZ_COEF >> 1) + +static char prp_dev[] = "emma_prp"; +static int g_still_on = 0; +static emma_prp_cfg g_prp_cfg; +static int g_vfbuf, g_rotbuf; +static struct tasklet_struct prp_vf_tasklet; + +/* + * The following variables represents the virtual address for the cacheable + * buffers accessed by SW rotation/mirroring. The rotation/mirroring in + * cacheable buffers has significant performance improvement than it in + * non-cacheable buffers. + */ +static char *g_vaddr_vfbuf[2] = { 0, 0 }; +static char *g_vaddr_rotbuf[2] = { 0, 0 }; +static char *g_vaddr_fb = 0; + +static int set_ch1_addr(emma_prp_cfg * cfg, cam_data * cam); +static int prp_v4l2_cfg(emma_prp_cfg * cfg, cam_data * cam); +static int prp_vf_mem_alloc(cam_data * cam); +static void prp_vf_mem_free(cam_data * cam); +static int prp_rot_mem_alloc(cam_data * cam); +static void prp_rot_mem_free(cam_data * cam); +static int prp_enc_update_eba(u32 eba, int *buffer_num); +static int prp_enc_enable(void *private); +static int prp_enc_disable(void *private); +static int prp_vf_start(void *private); +static int prp_vf_stop(void *private); +static int prp_still_start(void *private); +static int prp_still_stop(void *private); +static irqreturn_t prp_isr(int irq, void *dev_id); +static void rotation(unsigned long private); +static int prp_resize_check_ch1(emma_prp_cfg * cfg); +static int prp_resize_check_ch2(emma_prp_cfg * cfg); + +#define PRP_DUMP(val) pr_debug("%s\t = 0x%08X\t%d\n", #val, val, val) + +/*! + * @brief Dump PrP configuration parameters. + * @param cfg The pointer to PrP configuration parameter + */ +static void prp_cfg_dump(emma_prp_cfg * cfg) +{ + PRP_DUMP(cfg->in_pix); + PRP_DUMP(cfg->in_width); + PRP_DUMP(cfg->in_height); + PRP_DUMP(cfg->in_csi); + PRP_DUMP(cfg->in_line_stride); + PRP_DUMP(cfg->in_line_skip); + PRP_DUMP(cfg->in_ptr); + + PRP_DUMP(cfg->ch1_pix); + PRP_DUMP(cfg->ch1_width); + PRP_DUMP(cfg->ch1_height); + PRP_DUMP(cfg->ch1_scale.algo); + PRP_DUMP(cfg->ch1_scale.width.num); + PRP_DUMP(cfg->ch1_scale.width.den); + PRP_DUMP(cfg->ch1_scale.height.num); + PRP_DUMP(cfg->ch1_scale.height.den); + PRP_DUMP(cfg->ch1_stride); + PRP_DUMP(cfg->ch1_ptr); + PRP_DUMP(cfg->ch1_ptr2); + PRP_DUMP(cfg->ch1_csi); + + PRP_DUMP(cfg->ch2_pix); + PRP_DUMP(cfg->ch2_width); + PRP_DUMP(cfg->ch2_height); + PRP_DUMP(cfg->ch2_scale.algo); + PRP_DUMP(cfg->ch2_scale.width.num); + PRP_DUMP(cfg->ch2_scale.width.den); + PRP_DUMP(cfg->ch2_scale.height.num); + PRP_DUMP(cfg->ch2_scale.height.den); + PRP_DUMP(cfg->ch2_ptr); + PRP_DUMP(cfg->ch2_ptr2); + PRP_DUMP(cfg->ch2_csi); +} + +/*! + * @brief Set PrP channel 1 output address. + * @param cfg Pointer to emma_prp_cfg structure + * @param cam Pointer to cam_data structure + * @return Zero on success, others on failure + */ +static int set_ch1_addr(emma_prp_cfg * cfg, cam_data * cam) +{ + if (cam->rotation != V4L2_MXC_ROTATE_NONE) { + cfg->ch1_ptr = (unsigned int)cam->rot_vf_bufs[0]; + cfg->ch1_ptr2 = (unsigned int)cam->rot_vf_bufs[1]; + if ((cam->rotation == V4L2_MXC_ROTATE_90_RIGHT) + || (cam->rotation == V4L2_MXC_ROTATE_90_RIGHT_VFLIP) + || (cam->rotation == V4L2_MXC_ROTATE_90_RIGHT_HFLIP) + || (cam->rotation == V4L2_MXC_ROTATE_90_LEFT)) + cfg->ch1_stride = cam->win.w.height; + else + cfg->ch1_stride = cam->win.w.width; + + if (cam->v4l2_fb.flags != V4L2_FBUF_FLAG_OVERLAY) { + struct fb_info *fb = cam->overlay_fb; + if (!fb) + return -1; + if (g_vaddr_fb) + iounmap(g_vaddr_fb); + g_vaddr_fb = ioremap_cached(fb->fix.smem_start, + fb->fix.smem_len); + if (!g_vaddr_fb) + return -1; + } + } else if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) { + cfg->ch1_ptr = (unsigned int)cam->vf_bufs[0]; + cfg->ch1_ptr2 = (unsigned int)cam->vf_bufs[1]; + cfg->ch1_stride = cam->win.w.width; + } else { + struct fb_info *fb = cam->overlay_fb; + + if (!fb) + return -1; + + cfg->ch1_ptr = fb->fix.smem_start; + cfg->ch1_ptr += cam->win.w.top * fb->var.xres_virtual + * (fb->var.bits_per_pixel >> 3) + + cam->win.w.left * (fb->var.bits_per_pixel >> 3); + cfg->ch1_ptr2 = cfg->ch1_ptr; + cfg->ch1_stride = fb->var.xres_virtual; + } + + return 0; +} + +/*! + * @brief Setup PrP configuration parameters. + * @param cfg Pointer to emma_prp_cfg structure + * @param cam Pointer to cam_data structure + * @return Zero on success, others on failure + */ +static int prp_v4l2_cfg(emma_prp_cfg * cfg, cam_data * cam) +{ + cfg->in_pix = PRP_PIXIN_YUYV; + cfg->in_width = cam->crop_current.width; + cfg->in_height = cam->crop_current.height; + cfg->in_line_stride = cam->crop_current.left; + cfg->in_line_skip = cam->crop_current.top; + cfg->in_ptr = 0; + cfg->in_csi = PRP_CSI_LOOP; + memset(cfg->in_csc, 0, sizeof(cfg->in_csc)); + + if (cam->overlay_on) { + /* Convert V4L2 pixel format to PrP pixel format */ + switch (cam->v4l2_fb.fmt.pixelformat) { + case V4L2_PIX_FMT_RGB332: + cfg->ch1_pix = PRP_PIX1_RGB332; + break; + case V4L2_PIX_FMT_RGB32: + case V4L2_PIX_FMT_BGR32: + cfg->ch1_pix = PRP_PIX1_RGB888; + break; + case V4L2_PIX_FMT_YUYV: + cfg->ch1_pix = PRP_PIX1_YUYV; + break; + case V4L2_PIX_FMT_UYVY: + cfg->ch1_pix = PRP_PIX1_UYVY; + break; + case V4L2_PIX_FMT_RGB565: + default: + cfg->ch1_pix = PRP_PIX1_RGB565; + break; + } + if ((cam->rotation == V4L2_MXC_ROTATE_90_RIGHT) + || (cam->rotation == V4L2_MXC_ROTATE_90_RIGHT_VFLIP) + || (cam->rotation == V4L2_MXC_ROTATE_90_RIGHT_HFLIP) + || (cam->rotation == V4L2_MXC_ROTATE_90_LEFT)) { + cfg->ch1_width = cam->win.w.height; + cfg->ch1_height = cam->win.w.width; + } else { + cfg->ch1_width = cam->win.w.width; + cfg->ch1_height = cam->win.w.height; + } + + if (set_ch1_addr(cfg, cam)) + return -1; + } else { + cfg->ch1_pix = PRP_PIX1_UNUSED; + cfg->ch1_width = cfg->in_width; + cfg->ch1_height = cfg->in_height; + } + cfg->ch1_scale.algo = 0; + cfg->ch1_scale.width.num = cfg->in_width; + cfg->ch1_scale.width.den = cfg->ch1_width; + cfg->ch1_scale.height.num = cfg->in_height; + cfg->ch1_scale.height.den = cfg->ch1_height; + cfg->ch1_csi = PRP_CSI_EN; + + if (cam->capture_on || g_still_on) { + switch (cam->v2f.fmt.pix.pixelformat) { + case V4L2_PIX_FMT_YUYV: + cfg->ch2_pix = PRP_PIX2_YUV422; + break; + case V4L2_PIX_FMT_YUV420: + cfg->ch2_pix = PRP_PIX2_YUV420; + break; + /* + * YUV444 is not defined by V4L2. + * We support it in default case. + */ + default: + cfg->ch2_pix = PRP_PIX2_YUV444; + break; + } + cfg->ch2_width = cam->v2f.fmt.pix.width; + cfg->ch2_height = cam->v2f.fmt.pix.height; + } else { + cfg->ch2_pix = PRP_PIX2_UNUSED; + cfg->ch2_width = cfg->in_width; + cfg->ch2_height = cfg->in_height; + } + cfg->ch2_scale.algo = 0; + cfg->ch2_scale.width.num = cfg->in_width; + cfg->ch2_scale.width.den = cfg->ch2_width; + cfg->ch2_scale.height.num = cfg->in_height; + cfg->ch2_scale.height.den = cfg->ch2_height; + cfg->ch2_csi = PRP_CSI_EN; + + memset(cfg->scale, 0, sizeof(cfg->scale)); + cfg->scale[0].algo = cfg->ch1_scale.algo & 3; + cfg->scale[1].algo = (cfg->ch1_scale.algo >> 2) & 3; + cfg->scale[2].algo = cfg->ch2_scale.algo & 3; + cfg->scale[3].algo = (cfg->ch2_scale.algo >> 2) & 3; + + prp_cfg_dump(cfg); + + if (prp_resize_check_ch2(cfg)) + return -1; + + if (prp_resize_check_ch1(cfg)) + return -1; + + return 0; +} + +/*! + * @brief PrP interrupt handler + */ +static irqreturn_t prp_isr(int irq, void *dev_id) +{ + int status; + cam_data *cam = (cam_data *) dev_id; + + status = prphw_isr(); + + if (g_still_on && (status & PRP_INTRSTAT_CH2BUF1)) { + prp_still_stop(cam); + cam->still_counter++; + wake_up_interruptible(&cam->still_queue); + /* + * Still & video capture use the same PrP channel 2. + * They are execlusive. + */ + } else if (cam->capture_on) { + if (status & (PRP_INTRSTAT_CH2BUF1 | PRP_INTRSTAT_CH2BUF2)) { + cam->enc_callback(0, cam); + } + } + if (cam->overlay_on + && (status & (PRP_INTRSTAT_CH1BUF1 | PRP_INTRSTAT_CH1BUF2))) { + if (cam->rotation != V4L2_MXC_ROTATE_NONE) { + g_rotbuf = (status & PRP_INTRSTAT_CH1BUF1) ? 0 : 1; + tasklet_schedule(&prp_vf_tasklet); + } else if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) { + struct fb_gwinfo gwinfo; + + gwinfo.enabled = 1; + gwinfo.alpha_value = 255; + gwinfo.ck_enabled = 0; + gwinfo.xpos = cam->win.w.left; + gwinfo.ypos = cam->win.w.top; + gwinfo.xres = cam->win.w.width; + gwinfo.yres = cam->win.w.height; + gwinfo.xres_virtual = cam->win.w.width; + gwinfo.vs_reversed = 0; + if (status & PRP_INTRSTAT_CH1BUF1) + gwinfo.base = (unsigned long)cam->vf_bufs[0]; + else + gwinfo.base = (unsigned long)cam->vf_bufs[1]; + + mx2_gw_set(&gwinfo); + } + } + + return IRQ_HANDLED; +} + +/*! + * @brief PrP initialization. + * @param dev_id Pointer to cam_data structure + * @return Zero on success, others on failure + */ +int prp_init(void *dev_id) +{ + enable_irq(MXC_INT_EMMAPRP); + if (request_irq(MXC_INT_EMMAPRP, prp_isr, 0, prp_dev, dev_id)) + return -1; + prphw_init(); + + return 0; +} + +/*! + * @brief PrP initialization. + * @param dev_id Pointer to cam_data structure + */ +void prp_exit(void *dev_id) +{ + prphw_exit(); + disable_irq(MXC_INT_EMMAPRP); + free_irq(MXC_INT_EMMAPRP, dev_id); +} + +/*! + * @brief Update PrP channel 2 output buffer address. + * @param eba Physical address for PrP output buffer + * @param buffer_num The PrP channel 2 buffer number to be updated + * @return Zero on success, others on failure + */ +static int prp_enc_update_eba(u32 eba, int *buffer_num) +{ + if (*buffer_num) { + g_prp_cfg.ch2_ptr2 = eba; + prphw_ch2ptr2(&g_prp_cfg); + *buffer_num = 0; + } else { + g_prp_cfg.ch2_ptr = eba; + prphw_ch2ptr(&g_prp_cfg); + *buffer_num = 1; + } + + return 0; +} + +/*! + * @brief Enable PrP for encoding. + * @param private Pointer to cam_data structure + * @return Zero on success, others on failure + */ +static int prp_enc_enable(void *private) +{ + cam_data *cam = (cam_data *) private; + + if (prp_v4l2_cfg(&g_prp_cfg, cam)) + return -1; + + csi_enable_mclk(CSI_MCLK_ENC, true, true); + prphw_reset(); + + if (prphw_cfg(&g_prp_cfg)) + return -1; + + prphw_enable(cam->overlay_on ? (PRP_CHANNEL_1 | PRP_CHANNEL_2) + : PRP_CHANNEL_2); + + return 0; +} + +/*! + * @brief Disable PrP for encoding. + * @param private Pointer to cam_data structure + * @return Zero on success, others on failure + */ +static int prp_enc_disable(void *private) +{ + prphw_disable(PRP_CHANNEL_2); + csi_enable_mclk(CSI_MCLK_ENC, false, false); + + return 0; +} + +/*! + * @brief Setup encoding functions. + * @param private Pointer to cam_data structure + * @return Zero on success, others on failure + */ +int prp_enc_select(void *private) +{ + int ret = 0; + cam_data *cam = (cam_data *) private; + + if (cam) { + cam->enc_update_eba = prp_enc_update_eba; + cam->enc_enable = prp_enc_enable; + cam->enc_disable = prp_enc_disable; + } else + ret = -EIO; + + return ret; +} + +/*! + * @brief Uninstall encoding functions. + * @param private Pointer to cam_data structure + * @return Zero on success, others on failure + */ +int prp_enc_deselect(void *private) +{ + int ret = 0; + cam_data *cam = (cam_data *) private; + + ret = prp_enc_disable(private); + + if (cam) { + cam->enc_update_eba = NULL; + cam->enc_enable = NULL; + cam->enc_disable = NULL; + } + + return ret; +} + +/*! + * @brief Allocate memory for overlay. + * @param cam Pointer to cam_data structure + * @return Zero on success, others on failure + */ +static int prp_vf_mem_alloc(cam_data * cam) +{ + int i; + + for (i = 0; i < 2; i++) { + cam->vf_bufs_size[i] = cam->win.w.width * cam->win.w.height * 2; + cam->vf_bufs_vaddr[i] = dma_alloc_coherent(0, + cam->vf_bufs_size[i], + &cam->vf_bufs[i], + GFP_DMA | + GFP_KERNEL); + if (!cam->vf_bufs_vaddr[i]) { + pr_debug("Failed to alloc memory for vf.\n"); + prp_vf_mem_free(cam); + return -1; + } + + g_vaddr_vfbuf[i] = + ioremap_cached(cam->vf_bufs[i], cam->vf_bufs_size[i]); + if (!g_vaddr_vfbuf[i]) { + pr_debug("Failed to ioremap_cached() for vf.\n"); + prp_vf_mem_free(cam); + return -1; + } + } + + return 0; +} + +/*! + * @brief Free memory for overlay. + * @param cam Pointer to cam_data structure + * @return Zero on success, others on failure + */ +static void prp_vf_mem_free(cam_data * cam) +{ + int i; + + for (i = 0; i < 2; i++) { + if (cam->vf_bufs_vaddr[i]) { + dma_free_coherent(0, + cam->vf_bufs_size[i], + cam->vf_bufs_vaddr[i], + cam->vf_bufs[i]); + } + cam->vf_bufs[i] = 0; + cam->vf_bufs_vaddr[i] = 0; + cam->vf_bufs_size[i] = 0; + if (g_vaddr_vfbuf[i]) { + iounmap(g_vaddr_vfbuf[i]); + g_vaddr_vfbuf[i] = 0; + } + } +} + +/*! + * @brief Allocate intermediate memory for overlay rotation/mirroring. + * @param cam Pointer to cam_data structure + * @return Zero on success, others on failure + */ +static int prp_rot_mem_alloc(cam_data * cam) +{ + int i; + + for (i = 0; i < 2; i++) { + cam->rot_vf_buf_size[i] = + cam->win.w.width * cam->win.w.height * 2; + cam->rot_vf_bufs_vaddr[i] = + dma_alloc_coherent(0, cam->rot_vf_buf_size[i], + &cam->rot_vf_bufs[i], + GFP_DMA | GFP_KERNEL); + if (!cam->rot_vf_bufs_vaddr[i]) { + pr_debug("Failed to alloc memory for vf rotation.\n"); + prp_rot_mem_free(cam); + return -1; + } + + g_vaddr_rotbuf[i] = + ioremap_cached(cam->rot_vf_bufs[i], + cam->rot_vf_buf_size[i]); + if (!g_vaddr_rotbuf[i]) { + pr_debug + ("Failed to ioremap_cached() for rotation buffer.\n"); + prp_rot_mem_free(cam); + return -1; + } + } + + return 0; +} + +/*! + * @brief Free intermedaite memory for overlay rotation/mirroring. + * @param cam Pointer to cam_data structure + * @return Zero on success, others on failure + */ +static void prp_rot_mem_free(cam_data * cam) +{ + int i; + + for (i = 0; i < 2; i++) { + if (cam->rot_vf_bufs_vaddr[i]) { + dma_free_coherent(0, + cam->rot_vf_buf_size[i], + cam->rot_vf_bufs_vaddr[i], + cam->rot_vf_bufs[i]); + } + cam->rot_vf_bufs[i] = 0; + cam->rot_vf_bufs_vaddr[i] = 0; + cam->rot_vf_buf_size[i] = 0; + if (g_vaddr_rotbuf[i]) { + iounmap(g_vaddr_rotbuf[i]); + g_vaddr_rotbuf[i] = 0; + } + } +} + +/*! + * @brief Start overlay (view finder). + * @param private Pointer to cam_data structure + * @return Zero on success, others on failure + */ +static int prp_vf_start(void *private) +{ + cam_data *cam = (cam_data *) private; + + if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) { + prp_vf_mem_free(cam); + if (prp_vf_mem_alloc(cam)) { + pr_info("Error to allocate vf buffer\n"); + return -ENOMEM; + } + } + + if (cam->rotation != V4L2_MXC_ROTATE_NONE) { + prp_rot_mem_free(cam); + if (prp_rot_mem_alloc(cam)) { + pr_info("Error to allocate rotation buffer\n"); + prp_vf_mem_free(cam); + return -ENOMEM; + } + } + + if (prp_v4l2_cfg(&g_prp_cfg, cam)) { + prp_vf_mem_free(cam); + prp_rot_mem_free(cam); + return -1; + } + + csi_enable_mclk(CSI_MCLK_VF, true, true); + prphw_reset(); + + if (prphw_cfg(&g_prp_cfg)) { + prp_vf_mem_free(cam); + prp_rot_mem_free(cam); + return -1; + } + g_vfbuf = g_rotbuf = 0; + tasklet_init(&prp_vf_tasklet, rotation, (unsigned long)private); + + prphw_enable(cam->capture_on ? (PRP_CHANNEL_1 | PRP_CHANNEL_2) + : PRP_CHANNEL_1); + + return 0; +} + +/*! + * @brief Stop overlay (view finder). + * @param private Pointer to cam_data structure + * @return Zero on success, others on failure + */ +static int prp_vf_stop(void *private) +{ + cam_data *cam = (cam_data *) private; + + prphw_disable(PRP_CHANNEL_1); + + csi_enable_mclk(CSI_MCLK_VF, false, false); + tasklet_kill(&prp_vf_tasklet); + + if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) { + struct fb_gwinfo gwinfo; + + /* Disable graphic window */ + gwinfo.enabled = 0; + mx2_gw_set(&gwinfo); + + prp_vf_mem_free(cam); + } + prp_rot_mem_free(cam); + if (g_vaddr_fb) { + iounmap(g_vaddr_fb); + g_vaddr_fb = 0; + } + + return 0; +} + +/*! + * @brief Setup overlay functions. + * @param private Pointer to cam_data structure + * @return Zero on success, others on failure + */ +int prp_vf_select(void *private) +{ + int ret = 0; + cam_data *cam = (cam_data *) private; + + if (cam) { + cam->vf_start_sdc = prp_vf_start; + cam->vf_stop_sdc = prp_vf_stop; + cam->overlay_active = false; + } else + ret = -EIO; + + return ret; +} + +/*! + * @brief Uninstall overlay functions. + * @param private Pointer to cam_data structure + * @return Zero on success, others on failure + */ +int prp_vf_deselect(void *private) +{ + int ret = 0; + cam_data *cam = (cam_data *) private; + + ret = prp_vf_stop(private); + + if (cam) { + cam->vf_start_sdc = NULL; + cam->vf_stop_sdc = NULL; + } + + return ret; +} + +/*! + * @brief Start still picture capture. + * @param private Pointer to cam_data structure + * @return Zero on success, others on failure + */ +static int prp_still_start(void *private) +{ + cam_data *cam = (cam_data *) private; + + g_still_on = 1; + g_prp_cfg.ch2_ptr = (unsigned int)cam->still_buf; + g_prp_cfg.ch2_ptr2 = 0; + + if (prp_v4l2_cfg(&g_prp_cfg, cam)) + return -1; + + csi_enable_mclk(CSI_MCLK_RAW, true, true); + prphw_reset(); + + if (prphw_cfg(&g_prp_cfg)) { + g_still_on = 0; + return -1; + } + + prphw_enable(cam->overlay_on ? (PRP_CHANNEL_1 | PRP_CHANNEL_2) + : PRP_CHANNEL_2); + + return 0; +} + +/*! + * @brief Stop still picture capture. + * @param private Pointer to cam_data structure + * @return Zero on success, others on failure + */ +static int prp_still_stop(void *private) +{ + prphw_disable(PRP_CHANNEL_2); + + csi_enable_mclk(CSI_MCLK_RAW, false, false); + + g_still_on = 0; + + return 0; +} + +/*! + * @brief Setup functions for still picture capture. + * @param private Pointer to cam_data structure + * @return Zero on success, others on failure + */ +int prp_still_select(void *private) +{ + cam_data *cam = (cam_data *) private; + + if (cam) { + cam->csi_start = prp_still_start; + cam->csi_stop = prp_still_stop; + } + + return 0; +} + +/*! + * @brief Uninstall functions for still picture capture. + * @param private Pointer to cam_data structure + * @return Zero on success, others on failure + */ +int prp_still_deselect(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + + err = prp_still_stop(cam); + + if (cam) { + cam->csi_start = NULL; + cam->csi_stop = NULL; + } + + return err; +} + +/*! + * @brief Perform software rotation or mirroring + * @param private Argument passed to the tasklet + */ +static void rotation(unsigned long private) +{ + char *src, *dst; + int width, height, s_stride, d_stride; + int size; + cam_data *cam = (cam_data *) private; + + src = g_vaddr_rotbuf[g_rotbuf]; + size = cam->rot_vf_buf_size[g_rotbuf]; + + if ((cam->rotation == V4L2_MXC_ROTATE_90_RIGHT) + || (cam->rotation == V4L2_MXC_ROTATE_90_RIGHT_VFLIP) + || (cam->rotation == V4L2_MXC_ROTATE_90_RIGHT_HFLIP) + || (cam->rotation == V4L2_MXC_ROTATE_90_LEFT)) { + width = cam->win.w.height; + height = cam->win.w.width; + s_stride = cam->win.w.height << 1; + } else { + width = cam->win.w.width; + height = cam->win.w.height; + s_stride = cam->win.w.width << 1; + } + + if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) { + dst = g_vaddr_vfbuf[g_vfbuf]; + d_stride = cam->win.w.width << 1; + } else { /* The destination is the framebuffer */ + struct fb_info *fb = cam->overlay_fb; + if (!fb) + return; + dst = g_vaddr_fb; + dst += cam->win.w.top * fb->var.xres_virtual + * (fb->var.bits_per_pixel >> 3) + + cam->win.w.left * (fb->var.bits_per_pixel >> 3); + d_stride = fb->var.xres_virtual << 1; + } + + /* + * Invalidate the data in cache before performing the SW rotaion + * or mirroring in case the image size is less than QVGA. For image + * larger than QVGA it is not invalidated becase the invalidation + * will consume much time while we don't see any artifacts on the + * output if we don't perform invalidation for them. + * Similarly we don't flush the data after SW rotation/mirroring. + */ + if (size < 320 * 240 * 2) + dmac_inv_range(src, src + size); + switch (cam->rotation) { + case V4L2_MXC_ROTATE_VERT_FLIP: + opl_vmirror_u16(src, s_stride, width, height, dst, d_stride); + break; + case V4L2_MXC_ROTATE_HORIZ_FLIP: + opl_hmirror_u16(src, s_stride, width, height, dst, d_stride); + break; + case V4L2_MXC_ROTATE_180: + opl_rotate180_u16(src, s_stride, width, height, dst, d_stride); + break; + case V4L2_MXC_ROTATE_90_RIGHT: + opl_rotate90_u16(src, s_stride, width, height, dst, d_stride); + break; + case V4L2_MXC_ROTATE_90_RIGHT_VFLIP: + opl_rotate90_vmirror_u16(src, s_stride, width, height, dst, + d_stride); + break; + case V4L2_MXC_ROTATE_90_RIGHT_HFLIP: + /* ROTATE_90_RIGHT_HFLIP = ROTATE_270_RIGHT_VFLIP */ + opl_rotate270_vmirror_u16(src, s_stride, width, height, dst, + d_stride); + break; + case V4L2_MXC_ROTATE_90_LEFT: + opl_rotate270_u16(src, s_stride, width, height, dst, d_stride); + break; + default: + return; + } + + /* Config and display the graphic window */ + if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) { + struct fb_gwinfo gwinfo; + + gwinfo.enabled = 1; + gwinfo.alpha_value = 255; + gwinfo.ck_enabled = 0; + gwinfo.xpos = cam->win.w.left; + gwinfo.ypos = cam->win.w.top; + gwinfo.xres = cam->win.w.width; + gwinfo.yres = cam->win.w.height; + gwinfo.xres_virtual = cam->win.w.width; + gwinfo.vs_reversed = 0; + gwinfo.base = (unsigned long)cam->vf_bufs[g_vfbuf]; + mx2_gw_set(&gwinfo); + + g_vfbuf = g_vfbuf ? 0 : 1; + } +} + +/* + * @brief Check if the resize ratio is supported based on the input and output + * dimension + * @param input input dimension + * @param output output dimension + * @return output dimension (should equal the parameter *output*) + * -1 on failure + */ +static int check_simple(scale_t * scale, int input, int output) +{ + unsigned short int_out; /* PrP internel width or height */ + unsigned short orig_out = output; + + if (prp_scale(scale, input, output, input, &orig_out, &int_out, 0)) + return -1; /* resize failed */ + else + return int_out; +} + +/* + * @brief Check if the resize ratio is supported based on the input and output + * dimension + * @param input input dimension + * @param output output dimension + * @return output dimension, may be rounded. + * -1 on failure + */ +static int check_simple_retry(scale_t * scale, int input, int output) +{ + unsigned short int_out; /* PrP internel width or height */ + unsigned short orig_out = output; + + if (prp_scale(scale, input, output, input, &orig_out, &int_out, + SCALE_RETRY)) + return -1; /* resize failed */ + else + return int_out; +} + +/*! + * @brief Check if the resize ratio is supported by PrP channel 1 + * @param cfg Pointer to emma_prp_cfg structure + * @return Zero on success, others on failure + */ +static int prp_resize_check_ch1(emma_prp_cfg * cfg) +{ + int in_w, in_h, ch1_w, ch1_h, ch2_w, ch2_h, w, h; + scale_t *pscale = &cfg->scale[0]; /* Ch1 width resize coeff */ + + if (cfg->ch1_pix == PRP_PIX1_UNUSED) + return 0; + + in_w = cfg->in_width; + in_h = cfg->in_height; + ch1_w = cfg->ch1_width; + ch1_h = cfg->ch1_height; + ch2_w = cfg->ch2_width; + ch2_h = cfg->ch2_height; + + /* + * For channel 1, try parallel resize first. If the resize + * ratio is not exactly supported, try cascade resize. If it + * still fails, use parallel resize but with rounded value. + */ + w = check_simple(pscale, in_w, ch1_w); + h = check_simple(pscale + 1, in_h, ch1_h); + if ((w == ch1_w) && (h == ch1_h)) + goto exit_parallel; + + if (cfg->ch2_pix != PRP_PIX2_UNUSED) { + /* + * Channel 2 is already used. The pscale is still pointing + * to ch1 resize coeff for temporary use. + */ + w = check_simple(pscale, in_w, ch2_w); + h = check_simple(pscale + 1, in_h, ch2_h); + if ((w == ch2_w) && (h == ch2_h)) { + /* Try cascade resize now */ + w = check_simple(pscale, ch2_w, ch1_w); + h = check_simple(pscale + 1, ch2_h, ch1_h); + if ((w == ch1_w) && (h == ch1_h)) + goto exit_cascade; + } + } else { + /* + * Try cascade resize for width, width is multiple of 2. + * Channel 2 is not used. So we have more values to pick + * for channel 2 resize. + */ + for (w = in_w - 2; w > ch1_w; w -= 2) { + /* Ch2 width resize */ + if (check_simple(pscale + 2, in_w, w) != w) + continue; + /* Ch1 width resize */ + if (check_simple(pscale, w, ch1_w) != ch1_w) + continue; + break; + } + if ((ch2_w = w) > ch1_w) { + /* try cascade resize for height */ + for (h = in_h - 1; h > ch1_h; h--) { + /* Ch2 height resize */ + if (check_simple(pscale + 3, in_h, h) != h) + continue; + /* Ch1 height resize */ + if (check_simple(pscale + 1, h, ch1_h) != ch1_h) + continue; + break; + } + if ((ch2_h = h) > ch1_h) + goto exit_cascade; + } + } + + /* Have to try parallel resize again and round the dimensions */ + w = check_simple_retry(pscale, in_w, ch1_w); + h = check_simple_retry(pscale + 1, in_h, ch1_h); + if ((w != -1) && (h != -1)) + goto exit_parallel; + + pr_debug("Ch1 resize error.\n"); + return -1; + + exit_parallel: + cfg->ch1_scale.algo |= PRP_ALGO_BYPASS; + pr_debug("ch1 parallel resize.\n"); + pr_debug("original width = %d internel width = %d\n", ch1_w, w); + pr_debug("original height = %d internel height = %d\n", ch1_h, h); + return 0; + + exit_cascade: + cfg->ch1_scale.algo &= ~PRP_ALGO_BYPASS; + pr_debug("ch1 cascade resize.\n"); + pr_debug("[width] in : ch2 : ch1=%d : %d : %d\n", in_w, ch2_w, ch1_w); + pr_debug("[height] in : ch2 : ch1=%d : %d : %d\n", in_h, ch2_h, ch1_h); + return 0; +} + +/*! + * @brief Check if the resize ratio is supported by PrP channel 2 + * @param cfg Pointer to emma_prp_cfg structure + * @return Zero on success, others on failure + */ +static int prp_resize_check_ch2(emma_prp_cfg * cfg) +{ + int w, h; + scale_t *pscale = &cfg->scale[2]; /* Ch2 width resize coeff */ + + if (cfg->ch2_pix == PRP_PIX2_UNUSED) + return 0; + + w = check_simple_retry(pscale, cfg->in_width, cfg->ch2_width); + h = check_simple_retry(pscale + 1, cfg->in_height, cfg->ch2_height); + if ((w != -1) && (h != -1)) { + pr_debug("Ch2 resize.\n"); + pr_debug("Original width = %d internel width = %d\n", + cfg->ch2_width, w); + pr_debug("Original height = %d internel height = %d\n", + cfg->ch2_height, h); + return 0; + } else { + pr_debug("Ch2 resize error.\n"); + return -1; + } +} diff -urN linux-2.6.26/drivers/media/video/mxc/capture/mxc_v4l2_capture.c linux-2.6.26-lab126/drivers/media/video/mxc/capture/mxc_v4l2_capture.c --- linux-2.6.26/drivers/media/video/mxc/capture/mxc_v4l2_capture.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/mxc_v4l2_capture.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,2443 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file drivers/media/video/mxc/capture/mxc_v4l2_capture.c + * + * @brief Mxc Video For Linux 2 driver + * + * @ingroup MXC_V4L2_CAPTURE + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_v4l2_capture.h" +#include "ipu_prp_sw.h" + +static int video_nr = -1; +static cam_data *g_cam; + +/*! This data is used for the output to the display. */ +#define MXC_V4L2_CAPTURE_NUM_OUTPUTS 2 +static struct v4l2_output mxc_capture_outputs[MXC_V4L2_CAPTURE_NUM_OUTPUTS] = { + { + .index = 0, + .name = "DISP3", + .type = V4L2_OUTPUT_TYPE_ANALOG, + .audioset = 0, + .modulator = 0, + .std = V4L2_STD_UNKNOWN, + }, + { + .index = 1, + .name = "DISP0", + .type = V4L2_OUTPUT_TYPE_ANALOG, + .audioset = 0, + .modulator = 0, + .std = V4L2_STD_UNKNOWN, + } +}; + +/*! List of TV input video formats supported. The video formats is corresponding + * to the v4l2_id in video_fmt_t. + * Currently, only PAL and NTSC is supported. Needs to be expanded in the + * future. + */ +typedef enum { + TV_NTSC = 0, /*!< Locked on (M) NTSC video signal. */ + TV_PAL, /*!< (B, G, H, I, N)PAL video signal. */ + TV_NOT_LOCKED, /*!< Not locked on a signal. */ +} video_fmt_idx; + +/*! Number of video standards supported (including 'not locked' signal). */ +#define TV_STD_MAX (TV_NOT_LOCKED + 1) + +/*! Video format structure. */ +typedef struct { + int v4l2_id; /*!< Video for linux ID. */ + char name[16]; /*!< Name (e.g., "NTSC", "PAL", etc.) */ + u16 raw_width; /*!< Raw width. */ + u16 raw_height; /*!< Raw height. */ + u16 active_width; /*!< Active width. */ + u16 active_height; /*!< Active height. */ + u16 active_top; /*!< Active top. */ + u16 active_left; /*!< Active left. */ +} video_fmt_t; + +/*! + * Description of video formats supported. + * + * PAL: raw=720x625, active=720x576. + * NTSC: raw=720x525, active=720x480. + */ +static video_fmt_t video_fmts[] = { + { /*! NTSC */ + .v4l2_id = V4L2_STD_NTSC, + .name = "NTSC", + .raw_width = 720, /* SENS_FRM_WIDTH */ + .raw_height = 288, /* SENS_FRM_HEIGHT */ + .active_width = 720, /* ACT_FRM_WIDTH */ + .active_height = (480 / 2), /* ACT_FRM_HEIGHT */ + .active_top = 12, + .active_left = 0, + }, + { /*! (B, G, H, I, N) PAL */ + .v4l2_id = V4L2_STD_PAL, + .name = "PAL", + .raw_width = 720, + .raw_height = (576 / 2) + 24 * 2, + .active_width = 720, + .active_height = (576 / 2), + .active_top = 0, + .active_left = 0, + }, + { /*! Unlocked standard */ + .v4l2_id = V4L2_STD_ALL, + .name = "Autodetect", + .raw_width = 720, + .raw_height = (576 / 2) + 24 * 2, + .active_width = 720, + .active_height = (576 / 2), + .active_top = 0, + .active_left = 0, + }, +}; + +/*!* Standard index of TV. */ +static video_fmt_idx video_index = TV_NOT_LOCKED; + +static int mxc_v4l2_master_attach(struct v4l2_int_device *slave); +static void mxc_v4l2_master_detach(struct v4l2_int_device *slave); +static u8 camera_power(cam_data *cam, bool cameraOn); + +/*! Information about this driver. */ +static struct v4l2_int_master mxc_v4l2_master = { + .attach = mxc_v4l2_master_attach, + .detach = mxc_v4l2_master_detach, +}; + +static struct v4l2_int_device mxc_v4l2_int_device = { + .module = THIS_MODULE, + .name = "mxc_v4l2_cap", + .type = v4l2_int_type_master, + .u = { + .master = &mxc_v4l2_master, + }, +}; + +/*************************************************************************** + * Functions for handling Frame buffers. + **************************************************************************/ + +/*! + * Free frame buffers + * + * @param cam Structure cam_data * + * + * @return status 0 success. + */ +static int mxc_free_frame_buf(cam_data *cam) +{ + int i; + + pr_debug("MVC: In mxc_free_frame_buf\n"); + + for (i = 0; i < FRAME_NUM; i++) { + if (cam->frame[i].vaddress != 0) { + dma_free_coherent(0, cam->frame[i].buffer.length, + cam->frame[i].vaddress, + cam->frame[i].paddress); + cam->frame[i].vaddress = 0; + } + } + + return 0; +} + +/*! + * Allocate frame buffers + * + * @param cam Structure cam_data* + * @param count int number of buffer need to allocated + * + * @return status -0 Successfully allocated a buffer, -ENOBUFS failed. + */ +static int mxc_allocate_frame_buf(cam_data *cam, int count) +{ + int i; + + pr_debug("In MVC:mxc_allocate_frame_buf - size=%d\n", + cam->v2f.fmt.pix.sizeimage); + + for (i = 0; i < count; i++) { + cam->frame[i].vaddress = + dma_alloc_coherent(0, + PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage), + &cam->frame[i].paddress, + GFP_DMA | GFP_KERNEL); + if (cam->frame[i].vaddress == 0) { + pr_err("ERROR: v4l2 capture: " + "mxc_allocate_frame_buf failed.\n"); + mxc_free_frame_buf(cam); + return -ENOBUFS; + } + cam->frame[i].buffer.index = i; + cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED; + cam->frame[i].buffer.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cam->frame[i].buffer.length = + PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage); + cam->frame[i].buffer.memory = V4L2_MEMORY_MMAP; + cam->frame[i].buffer.m.offset = cam->frame[i].paddress; + cam->frame[i].index = i; + } + + return 0; +} + +/*! + * Free frame buffers status + * + * @param cam Structure cam_data * + * + * @return none + */ +static void mxc_free_frames(cam_data *cam) +{ + int i; + + pr_debug("In MVC:mxc_free_frames\n"); + + for (i = 0; i < FRAME_NUM; i++) { + cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED; + } + + cam->enc_counter = 0; + cam->skip_frame = 0; + INIT_LIST_HEAD(&cam->ready_q); + INIT_LIST_HEAD(&cam->working_q); + INIT_LIST_HEAD(&cam->done_q); +} + +/*! + * Return the buffer status + * + * @param cam Structure cam_data * + * @param buf Structure v4l2_buffer * + * + * @return status 0 success, EINVAL failed. + */ +static int mxc_v4l2_buffer_status(cam_data *cam, struct v4l2_buffer *buf) +{ + pr_debug("In MVC:mxc_v4l2_buffer_status\n"); + + if (buf->index < 0 || buf->index >= FRAME_NUM) { + pr_err("ERROR: v4l2 capture: mxc_v4l2_buffer_status buffers " + "not allocated\n"); + return -EINVAL; + } + + memcpy(buf, &(cam->frame[buf->index].buffer), sizeof(*buf)); + return 0; +} + +/*************************************************************************** + * Functions for handling the video stream. + **************************************************************************/ + +/*! + * Indicates whether the palette is supported. + * + * @param palette V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32 + * + * @return 0 if failed + */ +static inline int valid_mode(u32 palette) +{ + return ((palette == V4L2_PIX_FMT_RGB565) || + (palette == V4L2_PIX_FMT_BGR24) || + (palette == V4L2_PIX_FMT_RGB24) || + (palette == V4L2_PIX_FMT_BGR32) || + (palette == V4L2_PIX_FMT_RGB32) || + (palette == V4L2_PIX_FMT_YUV422P) || + (palette == V4L2_PIX_FMT_UYVY) || + (palette == V4L2_PIX_FMT_YUV420) || + (palette == V4L2_PIX_FMT_NV12)); +} + +/*! + * Start the encoder job + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static int mxc_streamon(cam_data *cam) +{ + struct mxc_v4l_frame *frame; + int err = 0; + + pr_debug("In MVC:mxc_streamon\n"); + + if (NULL == cam) { + pr_err("ERROR! cam parameter is NULL\n"); + return -1; + } + + if (list_empty(&cam->ready_q)) { + pr_err("ERROR: v4l2 capture: mxc_streamon buffer has not been " + "queued yet\n"); + return -EINVAL; + } + + cam->capture_pid = current->pid; + + if (cam->enc_enable) { + err = cam->enc_enable(cam); + if (err != 0) { + return err; + } + } + + cam->ping_pong_csi = 0; + if (cam->enc_update_eba) { + frame = + list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue); + list_del(cam->ready_q.next); + list_add_tail(&frame->queue, &cam->working_q); + err = cam->enc_update_eba(frame->buffer.m.offset, + &cam->ping_pong_csi); + + frame = + list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue); + list_del(cam->ready_q.next); + list_add_tail(&frame->queue, &cam->working_q); + err |= cam->enc_update_eba(frame->buffer.m.offset, + &cam->ping_pong_csi); + } else { + return -EINVAL; + } + + cam->capture_on = true; + + return err; +} + +/*! + * Shut down the encoder job + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static int mxc_streamoff(cam_data *cam) +{ + int err = 0; + + pr_debug("In MVC:mxc_streamoff\n"); + + if (cam->capture_on == false) + return 0; + + if (cam->enc_disable) { + err = cam->enc_disable(cam); + } + mxc_free_frames(cam); + cam->capture_on = false; + return err; +} + +/*! + * Valid and adjust the overlay window size, position + * + * @param cam structure cam_data * + * @param win struct v4l2_window * + * + * @return 0 + */ +static int verify_preview(cam_data *cam, struct v4l2_window *win) +{ + int i = 0; + int *width, *height; + + pr_debug("In MVC: verify_preview\n"); + + do { + cam->overlay_fb = (struct fb_info *)registered_fb[i]; + if (cam->overlay_fb == NULL) { + pr_err("ERROR: verify_preview frame buffer NULL.\n"); + return -1; + } + if (strncmp(cam->overlay_fb->fix.id, + mxc_capture_outputs[cam->output].name, 5) == 0) { + break; + } + } while (++i < FB_MAX); + + /* 4 bytes alignment for both FG and BG */ + if (cam->overlay_fb->var.bits_per_pixel == 24) { + win->w.left -= win->w.left % 4; + } else if (cam->overlay_fb->var.bits_per_pixel == 16) { + win->w.left -= win->w.left % 2; + } + + if (win->w.width + win->w.left > cam->overlay_fb->var.xres) + win->w.width = cam->overlay_fb->var.xres - win->w.left; + if (win->w.height + win->w.top > cam->overlay_fb->var.yres) + win->w.height = cam->overlay_fb->var.yres - win->w.top; + + /* stride line limitation */ + win->w.height -= win->w.height % 8; + win->w.width -= win->w.width % 8; + + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + height = &win->w.width; + width = &win->w.height; + } else { + width = &win->w.width; + height = &win->w.height; + } + + if ((cam->crop_bounds.width / *width > 8) || + ((cam->crop_bounds.width / *width == 8) && + (cam->crop_bounds.width % *width))) { + *width = cam->crop_bounds.width / 8; + if (*width % 8) + *width += 8 - *width % 8; + if (*width + win->w.left > cam->overlay_fb->var.xres) { + pr_err("ERROR: v4l2 capture: width exceeds " + "resize limit.\n"); + return -1; + } + pr_err("ERROR: v4l2 capture: width exceeds limit. " + "Resize to %d.\n", + *width); + } + + if ((cam->crop_bounds.height / *height > 8) || + ((cam->crop_bounds.height / *height == 8) && + (cam->crop_bounds.height % *height))) { + *height = cam->crop_bounds.height / 8; + if (*height % 8) + *height += 8 - *height % 8; + if (*height + win->w.top > cam->overlay_fb->var.yres) { + pr_err("ERROR: v4l2 capture: height exceeds " + "resize limit.\n"); + return -1; + } + pr_err("ERROR: v4l2 capture: height exceeds limit " + "resize to %d.\n", + *height); + } + + return 0; +} + +/*! + * start the viewfinder job + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static int start_preview(cam_data *cam) +{ + int err = 0; + + pr_debug("MVC: start_preview\n"); + +#if defined(CONFIG_MXC_IPU_PRP_VF_SDC) || defined(CONFIG_MXC_IPU_PRP_VF_SDC_MODULE) + pr_debug(" This is an SDC display\n"); + if (cam->output == 0) { + if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) + err = prp_vf_sdc_select(cam); + else if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_PRIMARY) + err = prp_vf_sdc_select_bg(cam); + if (err != 0) + return err; + + err = cam->vf_start_sdc(cam); + } +#endif + +#if defined(CONFIG_MXC_IPU_PRP_VF_ADC) || defined(CONFIG_MXC_IPU_PRP_VF_ADC_MODULE) + pr_debug(" This is an ADC display\n"); + if (cam->output == 1) { + err = prp_vf_adc_select(cam); + if (err != 0) + return err; + + err = cam->vf_start_adc(cam); + } +#endif + + pr_debug("End of %s: v2f pix widthxheight %d x %d\n", + __func__, + cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); + pr_debug("End of %s: crop_bounds widthxheight %d x %d\n", + __func__, + cam->crop_bounds.width, cam->crop_bounds.height); + pr_debug("End of %s: crop_defrect widthxheight %d x %d\n", + __func__, + cam->crop_defrect.width, cam->crop_defrect.height); + pr_debug("End of %s: crop_current widthxheight %d x %d\n", + __func__, + cam->crop_current.width, cam->crop_current.height); + + return err; +} + +/*! + * shut down the viewfinder job + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static int stop_preview(cam_data *cam) +{ + int err = 0; + + pr_debug("MVC: stop preview\n"); + +#if defined(CONFIG_MXC_IPU_PRP_VF_ADC) || defined(CONFIG_MXC_IPU_PRP_VF_ADC_MODULE) + if (cam->output == 1) { + err = prp_vf_adc_deselect(cam); + } +#endif + +#if defined(CONFIG_MXC_IPU_PRP_VF_SDC) || defined(CONFIG_MXC_IPU_PRP_VF_SDC_MODULE) + if (cam->output == 0) { + if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) + err = prp_vf_sdc_deselect(cam); + else if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_PRIMARY) + err = prp_vf_sdc_deselect_bg(cam); + } +#endif + + return err; +} + +/*************************************************************************** + * VIDIOC Functions. + **************************************************************************/ + +/*! + * V4L2 - mxc_v4l2_g_fmt function + * + * @param cam structure cam_data * + * + * @param f structure v4l2_format * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2_g_fmt(cam_data *cam, struct v4l2_format *f) +{ + int retval = 0; + + pr_debug("In MVC: mxc_v4l2_g_fmt type=%d\n", f->type); + + switch (f->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); + f->fmt.pix = cam->v2f.fmt.pix; + break; + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + pr_debug(" type is V4L2_BUF_TYPE_VIDEO_OVERLAY\n"); + f->fmt.win = cam->win; + break; + default: + pr_debug(" type is invalid\n"); + retval = -EINVAL; + } + + pr_debug("End of %s: v2f pix widthxheight %d x %d\n", + __func__, + cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); + pr_debug("End of %s: crop_bounds widthxheight %d x %d\n", + __func__, + cam->crop_bounds.width, cam->crop_bounds.height); + pr_debug("End of %s: crop_defrect widthxheight %d x %d\n", + __func__, + cam->crop_defrect.width, cam->crop_defrect.height); + pr_debug("End of %s: crop_current widthxheight %d x %d\n", + __func__, + cam->crop_current.width, cam->crop_current.height); + + return retval; +} + +/*! + * V4L2 - mxc_v4l2_s_fmt function + * + * @param cam structure cam_data * + * + * @param f structure v4l2_format * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2_s_fmt(cam_data *cam, struct v4l2_format *f) +{ + int retval = 0; + int size = 0; + int bytesperline = 0; + int *width, *height; + + pr_debug("In MVC: mxc_v4l2_s_fmt\n"); + + switch (f->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" type=V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); + if (!valid_mode(f->fmt.pix.pixelformat)) { + pr_err("ERROR: v4l2 capture: mxc_v4l2_s_fmt: format " + "not supported\n"); + return -EINVAL; + } + + /* Handle case where size requested is larger than cuurent + * camera setting. */ + if ((f->fmt.pix.width > cam->crop_bounds.width) + || (f->fmt.pix.height > cam->crop_bounds.height)) { + /* Need the logic here, calling vidioc_s_param if + * camera can change. */ + /* For the moment, just return an error. */ + return -EINVAL; + } + + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + height = &f->fmt.pix.width; + width = &f->fmt.pix.height; + } else { + width = &f->fmt.pix.width; + height = &f->fmt.pix.height; + } + + /* stride line limitation */ + *width -= *width % 8; + *height -= *height % 8; + + if ((cam->crop_bounds.width / *width > 8) || + ((cam->crop_bounds.width / *width == 8) && + (cam->crop_bounds.width % *width))) { + *width = cam->crop_bounds.width / 8; + if (*width % 8) + *width += 8 - *width % 8; + pr_err("ERROR: v4l2 capture: width exceeds limit " + "resize to %d.\n", + *width); + } + + if ((cam->crop_bounds.height / *height > 8) || + ((cam->crop_bounds.height / *height == 8) && + (cam->crop_bounds.height % *height))) { + *height = cam->crop_bounds.height / 8; + if (*height % 8) + *height += 8 - *height % 8; + pr_err("ERROR: v4l2 capture: height exceeds limit " + "resize to %d.\n", + *height); + } + + switch (f->fmt.pix.pixelformat) { + case V4L2_PIX_FMT_RGB565: + size = f->fmt.pix.width * f->fmt.pix.height * 2; + bytesperline = f->fmt.pix.width * 2; + break; + case V4L2_PIX_FMT_BGR24: + size = f->fmt.pix.width * f->fmt.pix.height * 3; + bytesperline = f->fmt.pix.width * 3; + break; + case V4L2_PIX_FMT_RGB24: + size = f->fmt.pix.width * f->fmt.pix.height * 3; + bytesperline = f->fmt.pix.width * 3; + break; + case V4L2_PIX_FMT_BGR32: + size = f->fmt.pix.width * f->fmt.pix.height * 4; + bytesperline = f->fmt.pix.width * 4; + break; + case V4L2_PIX_FMT_RGB32: + size = f->fmt.pix.width * f->fmt.pix.height * 4; + bytesperline = f->fmt.pix.width * 4; + break; + case V4L2_PIX_FMT_YUV422P: + size = f->fmt.pix.width * f->fmt.pix.height * 2; + bytesperline = f->fmt.pix.width; + break; + case V4L2_PIX_FMT_UYVY: + size = f->fmt.pix.width * f->fmt.pix.height * 2; + bytesperline = f->fmt.pix.width * 2; + break; + case V4L2_PIX_FMT_YUV420: + size = f->fmt.pix.width * f->fmt.pix.height * 3 / 2; + bytesperline = f->fmt.pix.width; + break; + case V4L2_PIX_FMT_NV12: + size = f->fmt.pix.width * f->fmt.pix.height * 3 / 2; + bytesperline = f->fmt.pix.width; + break; + default: + break; + } + + if (f->fmt.pix.bytesperline < bytesperline) { + f->fmt.pix.bytesperline = bytesperline; + } else { + bytesperline = f->fmt.pix.bytesperline; + } + + if (f->fmt.pix.sizeimage < size) { + f->fmt.pix.sizeimage = size; + } else { + size = f->fmt.pix.sizeimage; + } + + cam->v2f.fmt.pix = f->fmt.pix; + + if (cam->v2f.fmt.pix.priv != 0) { + if (copy_from_user(&cam->offset, + (void *)cam->v2f.fmt.pix.priv, + sizeof(cam->offset))) { + retval = -EFAULT; + break; + } + } + break; + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + pr_debug(" type=V4L2_BUF_TYPE_VIDEO_OVERLAY\n"); + retval = verify_preview(cam, &f->fmt.win); + cam->win = f->fmt.win; + break; + default: + retval = -EINVAL; + } + + pr_debug("End of %s: v2f pix widthxheight %d x %d\n", + __func__, + cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); + pr_debug("End of %s: crop_bounds widthxheight %d x %d\n", + __func__, + cam->crop_bounds.width, cam->crop_bounds.height); + pr_debug("End of %s: crop_defrect widthxheight %d x %d\n", + __func__, + cam->crop_defrect.width, cam->crop_defrect.height); + pr_debug("End of %s: crop_current widthxheight %d x %d\n", + __func__, + cam->crop_current.width, cam->crop_current.height); + + return retval; +} + +/*! + * get control param + * + * @param cam structure cam_data * + * + * @param c structure v4l2_control * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c) +{ + int status = 0; + + pr_debug("In MVC:mxc_v4l2_g_ctrl\n"); + + /* probably don't need to store the values that can be retrieved, + * locally, but they are for now. */ + switch (c->id) { + case V4L2_CID_HFLIP: + /* This is handled in the ipu. */ + if (cam->rotation == IPU_ROTATE_HORIZ_FLIP) + c->value = 1; + break; + case V4L2_CID_VFLIP: + /* This is handled in the ipu. */ + if (cam->rotation == IPU_ROTATE_VERT_FLIP) + c->value = 1; + break; + case V4L2_CID_MXC_ROT: + /* This is handled in the ipu. */ + c->value = cam->rotation; + break; + case V4L2_CID_BRIGHTNESS: + c->value = cam->bright; + status = vidioc_int_g_ctrl(cam->sensor, c); + cam->bright = c->value; + break; + case V4L2_CID_HUE: + c->value = cam->hue; + status = vidioc_int_g_ctrl(cam->sensor, c); + cam->hue = c->value; + break; + case V4L2_CID_CONTRAST: + c->value = cam->contrast; + status = vidioc_int_g_ctrl(cam->sensor, c); + cam->contrast = c->value; + break; + case V4L2_CID_SATURATION: + c->value = cam->saturation; + status = vidioc_int_g_ctrl(cam->sensor, c); + cam->saturation = c->value; + break; + case V4L2_CID_RED_BALANCE: + c->value = cam->red; + status = vidioc_int_g_ctrl(cam->sensor, c); + cam->red = c->value; + break; + case V4L2_CID_BLUE_BALANCE: + c->value = cam->blue; + status = vidioc_int_g_ctrl(cam->sensor, c); + cam->blue = c->value; + break; + case V4L2_CID_BLACK_LEVEL: + c->value = cam->ae_mode; + status = vidioc_int_g_ctrl(cam->sensor, c); + cam->ae_mode = c->value; + break; + default: + status = vidioc_int_g_ctrl(cam->sensor, c); + } + + return status; +} + +/*! + * V4L2 - set_control function + * V4L2_CID_PRIVATE_BASE is the extention for IPU preprocessing. + * 0 for normal operation + * 1 for vertical flip + * 2 for horizontal flip + * 3 for horizontal and vertical flip + * 4 for 90 degree rotation + * @param cam structure cam_data * + * + * @param c structure v4l2_control * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c) +{ + int ret = 0; + + pr_debug("In MVC:mxc_v4l2_s_ctrl\n"); + + switch (c->id) { + case V4L2_CID_HFLIP: + /* This is done by the IPU */ + if (c->value == 1) { + if ((cam->rotation != IPU_ROTATE_VERT_FLIP) && + (cam->rotation != IPU_ROTATE_180)) + cam->rotation = IPU_ROTATE_HORIZ_FLIP; + else + cam->rotation = IPU_ROTATE_180; + } else { + if (cam->rotation == IPU_ROTATE_HORIZ_FLIP) + cam->rotation = IPU_ROTATE_NONE; + if (cam->rotation == IPU_ROTATE_180) + cam->rotation = IPU_ROTATE_VERT_FLIP; + } + break; + case V4L2_CID_VFLIP: + /* This is done by the IPU */ + if (c->value == 1) { + if ((cam->rotation != IPU_ROTATE_HORIZ_FLIP) && + (cam->rotation != IPU_ROTATE_180)) + cam->rotation = IPU_ROTATE_VERT_FLIP; + else + cam->rotation = IPU_ROTATE_180; + } else { + if (cam->rotation == IPU_ROTATE_VERT_FLIP) + cam->rotation = IPU_ROTATE_NONE; + if (cam->rotation == IPU_ROTATE_180) + cam->rotation = IPU_ROTATE_HORIZ_FLIP; + } + break; + case V4L2_CID_MXC_ROT: + /* This is done by the IPU */ + switch (c->value) { + case V4L2_MXC_ROTATE_NONE: + cam->rotation = IPU_ROTATE_NONE; + break; + case V4L2_MXC_ROTATE_VERT_FLIP: + cam->rotation = IPU_ROTATE_VERT_FLIP; + break; + case V4L2_MXC_ROTATE_HORIZ_FLIP: + cam->rotation = IPU_ROTATE_HORIZ_FLIP; + break; + case V4L2_MXC_ROTATE_180: + cam->rotation = IPU_ROTATE_180; + break; + case V4L2_MXC_ROTATE_90_RIGHT: + cam->rotation = IPU_ROTATE_90_RIGHT; + break; + case V4L2_MXC_ROTATE_90_RIGHT_VFLIP: + cam->rotation = IPU_ROTATE_90_RIGHT_VFLIP; + break; + case V4L2_MXC_ROTATE_90_RIGHT_HFLIP: + cam->rotation = IPU_ROTATE_90_RIGHT_HFLIP; + break; + case V4L2_MXC_ROTATE_90_LEFT: + cam->rotation = IPU_ROTATE_90_LEFT; + break; + default: + ret = -EINVAL; + } + break; + case V4L2_CID_HUE: + cam->hue = c->value; + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true); + ret = vidioc_int_s_ctrl(cam->sensor, c); + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false); + break; + case V4L2_CID_CONTRAST: + cam->contrast = c->value; + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true); + ret = vidioc_int_s_ctrl(cam->sensor, c); + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false); + break; + case V4L2_CID_BRIGHTNESS: + cam->bright = c->value; + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true); + ret = vidioc_int_s_ctrl(cam->sensor, c); + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false); + break; + case V4L2_CID_SATURATION: + cam->saturation = c->value; + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true); + ret = vidioc_int_s_ctrl(cam->sensor, c); + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false); + break; + case V4L2_CID_RED_BALANCE: + cam->red = c->value; + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true); + ret = vidioc_int_s_ctrl(cam->sensor, c); + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false); + break; + case V4L2_CID_BLUE_BALANCE: + cam->blue = c->value; + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true); + ret = vidioc_int_s_ctrl(cam->sensor, c); + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false); + break; + case V4L2_CID_EXPOSURE: + cam->ae_mode = c->value; + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true); + ret = vidioc_int_s_ctrl(cam->sensor, c); + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false); + break; + case V4L2_CID_MXC_FLASH: +#ifdef CONFIG_MXC_IPU_V1 + ipu_csi_flash_strobe(true); +#endif + break; + default: + pr_debug(" default case\n"); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * V4L2 - mxc_v4l2_s_param function + * Allows setting of capturemode and frame rate. + * + * @param cam structure cam_data * + * @param parm structure v4l2_streamparm * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm) +{ + struct v4l2_ifparm ifparm; + struct v4l2_format cam_fmt; + struct v4l2_streamparm currentparm; + ipu_csi_signal_cfg_t csi_param; + int err = 0; + + pr_debug("In mxc_v4l2_s_param\n"); + + if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + pr_err(KERN_ERR "mxc_v4l2_s_param invalid type\n"); + return -EINVAL; + } + + /* Stop the viewfinder */ + if (cam->overlay_on == true) { + stop_preview(cam); + } + + currentparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + /* First check that this device can support the changes requested. */ + err = vidioc_int_g_parm(cam->sensor, ¤tparm); + if (err) { + pr_err("%s: vidioc_int_g_parm returned an error %d\n", + __func__, err); + goto exit; + } + + pr_debug(" Current capabilities are %x\n", + currentparm.parm.capture.capability); + pr_debug(" Current capturemode is %d change to %d\n", + currentparm.parm.capture.capturemode, + parm->parm.capture.capturemode); + pr_debug(" Current framerate is %d change to %d\n", + currentparm.parm.capture.timeperframe.denominator, + parm->parm.capture.timeperframe.denominator); + + /* This will change any camera settings needed. */ + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true); + err = vidioc_int_s_parm(cam->sensor, parm); + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false); + if (err) { + pr_err("%s: vidioc_int_s_parm returned an error %d\n", + __func__, err); + goto exit; + } + + /* If resolution changed, need to re-program the CSI */ + /* Get new values. */ + vidioc_int_g_ifparm(cam->sensor, &ifparm); + + csi_param.data_width = 0; + csi_param.clk_mode = 0; + csi_param.ext_vsync = 0; + csi_param.Vsync_pol = 0; + csi_param.Hsync_pol = 0; + csi_param.pixclk_pol = 0; + csi_param.data_pol = 0; + csi_param.sens_clksrc = 0; + csi_param.pack_tight = 0; + csi_param.force_eof = 0; + csi_param.data_en_pol = 0; + csi_param.data_fmt = 0; + csi_param.csi = 0; + csi_param.mclk = 0; + + /* This may not work on other platforms. Check when adding a new one.*/ + pr_debug(" clock_curr=mclk=%d\n", ifparm.u.bt656.clock_curr); + if (ifparm.u.bt656.clock_curr == 0) { + csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE; + } else { + csi_param.clk_mode = IPU_CSI_CLK_MODE_GATED_CLK; + } + + csi_param.pixclk_pol = ifparm.u.bt656.latch_clk_inv; + + if (ifparm.u.bt656.mode == V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT) { + csi_param.data_width = IPU_CSI_DATA_WIDTH_8; + } else if (ifparm.u.bt656.mode + == V4L2_IF_TYPE_BT656_MODE_NOBT_10BIT) { + csi_param.data_width = IPU_CSI_DATA_WIDTH_10; + } else { + csi_param.data_width = IPU_CSI_DATA_WIDTH_8; + } + + csi_param.Vsync_pol = ifparm.u.bt656.nobt_vs_inv; + csi_param.Hsync_pol = ifparm.u.bt656.nobt_hs_inv; + csi_param.ext_vsync = ifparm.u.bt656.bt_sync_correct; + + /* if the capturemode changed, the size bounds will have changed. */ + cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt); + pr_debug(" g_fmt_cap returns widthxheight of input as %d x %d\n", + cam_fmt.fmt.pix.width, cam_fmt.fmt.pix.height); + + csi_param.data_fmt = cam_fmt.fmt.pix.pixelformat; + + cam->crop_bounds.top = cam->crop_bounds.left = 0; + cam->crop_bounds.width = cam_fmt.fmt.pix.width; + cam->crop_bounds.height = cam_fmt.fmt.pix.height; + + /* This essentially loses the data at the left and bottom of the image + * giving a digital zoom image, if crop_current is less than the full + * size of the image. */ + ipu_csi_set_window_size(cam->crop_current.width, + cam->crop_current.height, cam->csi); + ipu_csi_set_window_pos(cam->crop_current.left, + cam->crop_current.top, + cam->csi); + ipu_csi_init_interface(cam->crop_bounds.width, + cam->crop_bounds.height, + cam_fmt.fmt.pix.pixelformat, csi_param); + + +exit: + if (cam->overlay_on == true) + start_preview(cam); + + return err; +} + +/*! + * V4L2 - mxc_v4l2_s_std function + * + * Sets the TV standard to be used. + * + * @param cam structure cam_data * + * @param parm structure v4l2_streamparm * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2_s_std(cam_data *cam, v4l2_std_id e) +{ + bool change = false; + + if (e != cam->standard.id) { + change = true; + } + + pr_debug("In mxc_v4l2_s_std %Lx\n", e); + if (e == V4L2_STD_PAL) { + pr_debug(" Setting standard to PAL %Lx\n", V4L2_STD_PAL); + cam->standard.id = V4L2_STD_PAL; + video_index = TV_PAL; + cam->crop_current.top = 0; + } else if (e == V4L2_STD_NTSC) { + pr_debug(" Setting standard to NTSC %Lx\n", + V4L2_STD_NTSC); + /* Get rid of the white dot line in NTSC signal input */ + cam->standard.id = V4L2_STD_NTSC; + video_index = TV_NTSC; + cam->crop_current.top = 12; + } else { + cam->standard.id = V4L2_STD_ALL; + video_index = TV_NOT_LOCKED; + cam->crop_current.top = 0; + pr_err("ERROR: unrecognized std! %Lx (PAL=%Lx, NTSC=%Lx\n", + e, V4L2_STD_PAL, V4L2_STD_NTSC); + } + + cam->standard.index = video_index; + strcpy(cam->standard.name, video_fmts[video_index].name); + cam->crop_bounds.width = video_fmts[video_index].raw_width; + cam->crop_bounds.height = video_fmts[video_index].raw_height; + cam->crop_current.width = video_fmts[video_index].active_width; + cam->crop_current.height = video_fmts[video_index].active_height; + cam->crop_current.left = 0; + + return 0; +} + +/*! + * V4L2 - mxc_v4l2_g_std function + * + * Gets the TV standard from the TV input device. + * + * @param cam structure cam_data * + * + * @param e structure v4l2_streamparm * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2_g_std(cam_data *cam, v4l2_std_id *e) +{ + struct v4l2_format tv_fmt; + + pr_debug("In mxc_v4l2_g_std\n"); + + if (cam->device_type == 1) { + /* Use this function to get what the TV-In device detects the + * format to be. pixelformat is used to return the std value + * since the interface has no vidioc_g_std.*/ + tv_fmt.type = V4L2_BUF_TYPE_PRIVATE; + vidioc_int_g_fmt_cap(cam->sensor, &tv_fmt); + + /* If the TV-in automatically detects the standard, then if it + * changes, the settings need to change. */ + if (cam->standard_autodetect) { + if (cam->standard.id != tv_fmt.fmt.pix.pixelformat) { + pr_debug("MVC: mxc_v4l2_g_std: " + "Changing standard\n"); + mxc_v4l2_s_std(cam, tv_fmt.fmt.pix.pixelformat); + } + } + + *e = tv_fmt.fmt.pix.pixelformat; + } + + return 0; +} + +/*! + * Dequeue one V4L capture buffer + * + * @param cam structure cam_data * + * @param buf structure v4l2_buffer * + * + * @return status 0 success, EINVAL invalid frame number, + * ETIME timeout, ERESTARTSYS interrupted by user + */ +static int mxc_v4l_dqueue(cam_data *cam, struct v4l2_buffer *buf) +{ + int retval = 0; + struct mxc_v4l_frame *frame; + + pr_debug("In MVC:mxc_v4l_dqueue\n"); + + if (!wait_event_interruptible_timeout(cam->enc_queue, + cam->enc_counter != 0, 10 * HZ)) { + pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue timeout " + "enc_counter %x\n", + cam->enc_counter); + return -ETIME; + } else if (signal_pending(current)) { + pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue() " + "interrupt received\n"); + return -ERESTARTSYS; + } + + cam->enc_counter--; + + frame = list_entry(cam->done_q.next, struct mxc_v4l_frame, queue); + list_del(cam->done_q.next); + if (frame->buffer.flags & V4L2_BUF_FLAG_DONE) { + frame->buffer.flags &= ~V4L2_BUF_FLAG_DONE; + } else if (frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) { + pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: " + "Buffer not filled.\n"); + frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED; + retval = -EINVAL; + } else if ((frame->buffer.flags & 0x7) == V4L2_BUF_FLAG_MAPPED) { + pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: " + "Buffer not queued.\n"); + retval = -EINVAL; + } + + buf->bytesused = cam->v2f.fmt.pix.sizeimage; + buf->index = frame->index; + buf->flags = frame->buffer.flags; + buf->m = cam->frame[frame->index].buffer.m; + + return retval; +} + +/*! + * V4L interface - open function + * + * @param inode structure inode * + * @param file structure file * + * + * @return status 0 success, ENODEV invalid device instance, + * ENODEV timeout, ERESTARTSYS interrupted by user + */ +static int mxc_v4l_open(struct inode *inode, struct file *file) +{ + struct v4l2_ifparm ifparm; + struct v4l2_format cam_fmt; + ipu_csi_signal_cfg_t csi_param; + struct video_device *dev = video_devdata(file); + cam_data *cam = dev->priv; + int err = 0; + + pr_debug("\nIn MVC: mxc_v4l_open\n"); + pr_debug(" device name is %s\n", dev->name); + + if (!cam) { + pr_err("ERROR: v4l2 capture: Internal error, " + "cam_data not found!\n"); + return -EBADF; + } + + down(&cam->busy_lock); + err = 0; + if (signal_pending(current)) + goto oops; + + if (cam->open_count++ == 0) { + wait_event_interruptible(cam->power_queue, + cam->low_power == false); + +#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_PRP_ENC_MODULE) + err = prp_enc_select(cam); +#endif + + cam->enc_counter = 0; + cam->skip_frame = 0; + INIT_LIST_HEAD(&cam->ready_q); + INIT_LIST_HEAD(&cam->working_q); + INIT_LIST_HEAD(&cam->done_q); + + vidioc_int_g_ifparm(cam->sensor, &ifparm); + + csi_param.sens_clksrc = 0; + + csi_param.clk_mode = 0; + csi_param.data_pol = 0; + csi_param.ext_vsync = 0; + + csi_param.pack_tight = 0; + csi_param.force_eof = 0; + csi_param.data_en_pol = 0; + csi_param.mclk = ifparm.u.bt656.clock_curr; + + csi_param.pixclk_pol = ifparm.u.bt656.latch_clk_inv; + + /* Once we handle multiple inputs this will need to change. */ + csi_param.csi = 0; + + if (ifparm.u.bt656.mode + == V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT) + csi_param.data_width = IPU_CSI_DATA_WIDTH_8; + else if (ifparm.u.bt656.mode + == V4L2_IF_TYPE_BT656_MODE_NOBT_10BIT) + csi_param.data_width = IPU_CSI_DATA_WIDTH_10; + else + csi_param.data_width = IPU_CSI_DATA_WIDTH_8; + + + csi_param.Vsync_pol = ifparm.u.bt656.nobt_vs_inv; + csi_param.Hsync_pol = ifparm.u.bt656.nobt_hs_inv; + + csi_param.csi = cam->csi; + + cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt); + + /* Reset the sizes. Needed to prevent carryover of last + * operation.*/ + cam->crop_bounds.top = cam->crop_bounds.left = 0; + cam->crop_bounds.width = cam_fmt.fmt.pix.width; + cam->crop_bounds.height = cam_fmt.fmt.pix.height; + + /* This also is the max crop size for this device. */ + cam->crop_defrect.top = cam->crop_defrect.left = 0; + cam->crop_defrect.width = cam_fmt.fmt.pix.width; + cam->crop_defrect.height = cam_fmt.fmt.pix.height; + + /* At this point, this is also the current image size. */ + cam->crop_current.top = cam->crop_current.left = 0; + cam->crop_current.width = cam_fmt.fmt.pix.width; + cam->crop_current.height = cam_fmt.fmt.pix.height; + + pr_debug("End of %s: v2f pix widthxheight %d x %d\n", + __func__, + cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); + pr_debug("End of %s: crop_bounds widthxheight %d x %d\n", + __func__, + cam->crop_bounds.width, cam->crop_bounds.height); + pr_debug("End of %s: crop_defrect widthxheight %d x %d\n", + __func__, + cam->crop_defrect.width, cam->crop_defrect.height); + pr_debug("End of %s: crop_current widthxheight %d x %d\n", + __func__, + cam->crop_current.width, cam->crop_current.height); + + csi_param.data_fmt = cam_fmt.fmt.pix.pixelformat; + pr_debug("On Open: Input to ipu size is %d x %d\n", + cam_fmt.fmt.pix.width, cam_fmt.fmt.pix.height); + ipu_csi_set_window_size(cam->crop_current.width, + cam->crop_current.width, + cam->csi); + ipu_csi_set_window_pos(cam->crop_current.left, + cam->crop_current.top, + cam->csi); + ipu_csi_init_interface(cam->crop_bounds.width, + cam->crop_bounds.height, + cam_fmt.fmt.pix.pixelformat, + csi_param); + + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, + true, true); + vidioc_int_init(cam->sensor); + + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, + false, false); +} + + file->private_data = dev; + + oops: + up(&cam->busy_lock); + return err; +} + +/*! + * V4L interface - close function + * + * @param inode struct inode * + * @param file struct file * + * + * @return 0 success + */ +static int mxc_v4l_close(struct inode *inode, struct file *file) +{ + struct video_device *dev = video_devdata(file); + int err = 0; + cam_data *cam = dev->priv; + + pr_debug("In MVC:mxc_v4l_close\n"); + + if (!cam) { + pr_err("ERROR: v4l2 capture: Internal error, " + "cam_data not found!\n"); + return -EBADF; + } + + /* for the case somebody hit the ctrl C */ + if (cam->overlay_pid == current->pid) { + err = stop_preview(cam); + cam->overlay_on = false; + } + if (cam->capture_pid == current->pid) { + err |= mxc_streamoff(cam); + wake_up_interruptible(&cam->enc_queue); + } + + if (--cam->open_count == 0) { + wait_event_interruptible(cam->power_queue, + cam->low_power == false); + pr_info("mxc_v4l_close: release resource\n"); + +#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_PRP_ENC_MODULE) + err |= prp_enc_deselect(cam); +#endif + mxc_free_frame_buf(cam); + file->private_data = NULL; + + /* capture off */ + wake_up_interruptible(&cam->enc_queue); + mxc_free_frames(cam); + cam->enc_counter++; + } + + return err; +} + +#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_PRP_ENC_MODULE) +/* + * V4L interface - read function + * + * @param file struct file * + * @param read buf char * + * @param count size_t + * @param ppos structure loff_t * + * + * @return bytes read + */ +static ssize_t mxc_v4l_read(struct file *file, char *buf, size_t count, + loff_t *ppos) +{ + int err = 0; + u8 *v_address; + struct video_device *dev = video_devdata(file); + cam_data *cam = dev->priv; + + if (down_interruptible(&cam->busy_lock)) + return -EINTR; + + /* Stop the viewfinder */ + if (cam->overlay_on == true) + stop_preview(cam); + + v_address = dma_alloc_coherent(0, + PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage), + &cam->still_buf, GFP_DMA | GFP_KERNEL); + + if (!v_address) { + err = -ENOBUFS; + goto exit0; + } + + err = prp_still_select(cam); + if (err != 0) { + err = -EIO; + goto exit1; + } + + cam->still_counter = 0; + err = cam->csi_start(cam); + if (err != 0) { + err = -EIO; + goto exit2; + } + + if (!wait_event_interruptible_timeout(cam->still_queue, + cam->still_counter != 0, + 10 * HZ)) { + pr_err("ERROR: v4l2 capture: mxc_v4l_read timeout counter %x\n", + cam->still_counter); + err = -ETIME; + goto exit2; + } + err = copy_to_user(buf, v_address, cam->v2f.fmt.pix.sizeimage); + + exit2: + prp_still_deselect(cam); + + exit1: + dma_free_coherent(0, cam->v2f.fmt.pix.sizeimage, v_address, + cam->still_buf); + cam->still_buf = 0; + + exit0: + if (cam->overlay_on == true) { + start_preview(cam); + } + + up(&cam->busy_lock); + if (err < 0) + return err; + + return (cam->v2f.fmt.pix.sizeimage - err); +} +#endif + +/*! + * V4L interface - ioctl function + * + * @param inode struct inode* + * + * @param file struct file* + * + * @param ioctlnr unsigned int + * + * @param arg void* + * + * @return 0 success, ENODEV for invalid device instance, + * -1 for other errors. + */ +static int mxc_v4l_do_ioctl(struct inode *inode, struct file *file, + unsigned int ioctlnr, void *arg) +{ + struct video_device *dev = video_devdata(file); + cam_data *cam = dev->priv; + int retval = 0; + unsigned long lock_flags; + + pr_debug("In MVC: mxc_v4l_do_ioctl %x\n", ioctlnr); + wait_event_interruptible(cam->power_queue, cam->low_power == false); + /* make this _really_ smp-safe */ + if (down_interruptible(&cam->busy_lock)) + return -EBUSY; + + switch (ioctlnr) { + /*! + * V4l2 VIDIOC_QUERYCAP ioctl + */ + case VIDIOC_QUERYCAP: { + struct v4l2_capability *cap = arg; + pr_debug(" case VIDIOC_QUERYCAP\n"); + strcpy(cap->driver, "mxc_v4l2"); + cap->version = KERNEL_VERSION(0, 1, 11); + cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | + V4L2_CAP_VIDEO_OVERLAY | + V4L2_CAP_STREAMING | + V4L2_CAP_READWRITE; + cap->card[0] = '\0'; + cap->bus_info[0] = '\0'; + break; + } + + /*! + * V4l2 VIDIOC_G_FMT ioctl + */ + case VIDIOC_G_FMT: { + struct v4l2_format *gf = arg; + pr_debug(" case VIDIOC_G_FMT\n"); + retval = mxc_v4l2_g_fmt(cam, gf); + break; + } + + /*! + * V4l2 VIDIOC_S_FMT ioctl + */ + case VIDIOC_S_FMT: { + struct v4l2_format *sf = arg; + pr_debug(" case VIDIOC_S_FMT\n"); + retval = mxc_v4l2_s_fmt(cam, sf); + break; + } + + /*! + * V4l2 VIDIOC_REQBUFS ioctl + */ + case VIDIOC_REQBUFS: { + struct v4l2_requestbuffers *req = arg; + pr_debug(" case VIDIOC_REQBUFS\n"); + + if (req->count > FRAME_NUM) { + pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: " + "not enough buffers\n"); + req->count = FRAME_NUM; + } + + if ((req->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) || + (req->memory != V4L2_MEMORY_MMAP)) { + pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: " + "wrong buffer type\n"); + retval = -EINVAL; + break; + } + + mxc_streamoff(cam); + mxc_free_frame_buf(cam); + cam->enc_counter = 0; + cam->skip_frame = 0; + INIT_LIST_HEAD(&cam->ready_q); + INIT_LIST_HEAD(&cam->working_q); + INIT_LIST_HEAD(&cam->done_q); + + retval = mxc_allocate_frame_buf(cam, req->count); + break; + } + + /*! + * V4l2 VIDIOC_QUERYBUF ioctl + */ + case VIDIOC_QUERYBUF: { + struct v4l2_buffer *buf = arg; + int index = buf->index; + pr_debug(" case VIDIOC_QUERYBUF\n"); + + if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + pr_err("ERROR: v4l2 capture: " + "VIDIOC_QUERYBUFS: " + "wrong buffer type\n"); + retval = -EINVAL; + break; + } + + memset(buf, 0, sizeof(buf)); + buf->index = index; + + down(&cam->param_lock); + retval = mxc_v4l2_buffer_status(cam, buf); + up(&cam->param_lock); + break; + } + + /*! + * V4l2 VIDIOC_QBUF ioctl + */ + case VIDIOC_QBUF: { + struct v4l2_buffer *buf = arg; + int index = buf->index; + pr_debug(" case VIDIOC_QBUF\n"); + + spin_lock_irqsave(&cam->int_lock, lock_flags); + cam->frame[index].buffer.m.offset = buf->m.offset; + if ((cam->frame[index].buffer.flags & 0x7) == + V4L2_BUF_FLAG_MAPPED) { + cam->frame[index].buffer.flags |= + V4L2_BUF_FLAG_QUEUED; + if (cam->skip_frame > 0) { + list_add_tail(&cam->frame[index].queue, + &cam->working_q); + retval = + cam->enc_update_eba(cam-> + frame[index]. + buffer.m.offset, + &cam-> + ping_pong_csi); + cam->skip_frame = 0; + } else { + list_add_tail(&cam->frame[index].queue, + &cam->ready_q); + } + } else if (cam->frame[index].buffer. + flags & V4L2_BUF_FLAG_QUEUED) { + pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: " + "buffer already queued\n"); + } else if (cam->frame[index].buffer. + flags & V4L2_BUF_FLAG_DONE) { + pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: " + "overwrite done buffer.\n"); + cam->frame[index].buffer.flags &= + ~V4L2_BUF_FLAG_DONE; + cam->frame[index].buffer.flags |= + V4L2_BUF_FLAG_QUEUED; + } + + buf->flags = cam->frame[index].buffer.flags; + spin_unlock_irqrestore(&cam->int_lock, lock_flags); + break; + } + + /*! + * V4l2 VIDIOC_DQBUF ioctl + */ + case VIDIOC_DQBUF: { + struct v4l2_buffer *buf = arg; + pr_debug(" case VIDIOC_DQBUF\n"); + + retval = mxc_v4l_dqueue(cam, buf); + + break; + } + + /*! + * V4l2 VIDIOC_STREAMON ioctl + */ + case VIDIOC_STREAMON: { + pr_debug(" case VIDIOC_STREAMON\n"); + retval = mxc_streamon(cam); + break; + } + + /*! + * V4l2 VIDIOC_STREAMOFF ioctl + */ + case VIDIOC_STREAMOFF: { + pr_debug(" case VIDIOC_STREAMOFF\n"); + retval = mxc_streamoff(cam); + break; + } + + /*! + * V4l2 VIDIOC_G_CTRL ioctl + */ + case VIDIOC_G_CTRL: { + pr_debug(" case VIDIOC_G_CTRL\n"); + retval = mxc_v4l2_g_ctrl(cam, arg); + break; + } + + /*! + * V4l2 VIDIOC_S_CTRL ioctl + */ + case VIDIOC_S_CTRL: { + pr_debug(" case VIDIOC_S_CTRL\n"); + retval = mxc_v4l2_s_ctrl(cam, arg); + break; + } + + /*! + * V4l2 VIDIOC_CROPCAP ioctl + */ + case VIDIOC_CROPCAP: { + struct v4l2_cropcap *cap = arg; + pr_debug(" case VIDIOC_CROPCAP\n"); + if (cap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && + cap->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) { + retval = -EINVAL; + break; + } + cap->bounds = cam->crop_bounds; + cap->defrect = cam->crop_defrect; + break; + } + + /*! + * V4l2 VIDIOC_G_CROP ioctl + */ + case VIDIOC_G_CROP: { + struct v4l2_crop *crop = arg; + pr_debug(" case VIDIOC_G_CROP\n"); + + if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && + crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) { + retval = -EINVAL; + break; + } + crop->c = cam->crop_current; + break; + } + + /*! + * V4l2 VIDIOC_S_CROP ioctl + */ + case VIDIOC_S_CROP: { + struct v4l2_crop *crop = arg; + struct v4l2_rect *b = &cam->crop_bounds; + pr_debug(" case VIDIOC_S_CROP\n"); + + if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && + crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) { + retval = -EINVAL; + break; + } + + crop->c.top = (crop->c.top < b->top) ? b->top + : crop->c.top; + if (crop->c.top > b->top + b->height) + crop->c.top = b->top + b->height - 1; + if (crop->c.height > b->top + b->height - crop->c.top) + crop->c.height = + b->top + b->height - crop->c.top; + + crop->c.left = (crop->c.left < b->left) ? b->left + : crop->c.left; + if (crop->c.left > b->left + b->width) + crop->c.left = b->left + b->width - 1; + if (crop->c.width > b->left - crop->c.left + b->width) + crop->c.width = + b->left - crop->c.left + b->width; + + crop->c.width -= crop->c.width % 8; + crop->c.left -= crop->c.left % 4; + cam->crop_current = crop->c; + + pr_debug(" Cropping Input to ipu size %d x %d\n", + cam->crop_current.width, + cam->crop_current.height); + ipu_csi_set_window_size(cam->crop_current.width, + cam->crop_current.height, + cam->csi); + ipu_csi_set_window_pos(cam->crop_current.left, + cam->crop_current.top, + cam->csi); + break; + } + + /*! + * V4l2 VIDIOC_OVERLAY ioctl + */ + case VIDIOC_OVERLAY: { + int *on = arg; + pr_debug(" VIDIOC_OVERLAY on=%d\n", *on); + if (*on) { + cam->overlay_on = true; + cam->overlay_pid = current->pid; + retval = start_preview(cam); + } + if (!*on) { + retval = stop_preview(cam); + cam->overlay_on = false; + } + break; + } + + /*! + * V4l2 VIDIOC_G_FBUF ioctl + */ + case VIDIOC_G_FBUF: { + struct v4l2_framebuffer *fb = arg; + pr_debug(" case VIDIOC_G_FBUF\n"); + *fb = cam->v4l2_fb; + fb->capability = V4L2_FBUF_CAP_EXTERNOVERLAY; + break; + } + + /*! + * V4l2 VIDIOC_S_FBUF ioctl + */ + case VIDIOC_S_FBUF: { + struct v4l2_framebuffer *fb = arg; + pr_debug(" case VIDIOC_S_FBUF\n"); + cam->v4l2_fb = *fb; + break; + } + + case VIDIOC_G_PARM: { + struct v4l2_streamparm *parm = arg; + pr_debug(" case VIDIOC_G_PARM\n"); + vidioc_int_g_parm(cam->sensor, parm); + break; + } + + case VIDIOC_S_PARM: { + struct v4l2_streamparm *parm = arg; + pr_debug(" case VIDIOC_S_PARM\n"); + retval = mxc_v4l2_s_param(cam, parm); + break; + } + + /* linux v4l2 bug, kernel c0485619 user c0405619 */ + case VIDIOC_ENUMSTD: { + struct v4l2_standard *e = arg; + pr_debug(" case VIDIOC_ENUMSTD\n"); + *e = cam->standard; + break; + } + + case VIDIOC_G_STD: { + v4l2_std_id *e = arg; + pr_debug(" case VIDIOC_G_STD\n"); + retval = mxc_v4l2_g_std(cam, e); + break; + } + + case VIDIOC_S_STD: { + v4l2_std_id *e = arg; + pr_debug(" case VIDIOC_S_STD\n"); + retval = mxc_v4l2_s_std(cam, *e); + + break; + } + + case VIDIOC_ENUMOUTPUT: { + struct v4l2_output *output = arg; + pr_debug(" case VIDIOC_ENUMOUTPUT\n"); + if (output->index >= MXC_V4L2_CAPTURE_NUM_OUTPUTS) { + retval = -EINVAL; + break; + } + *output = mxc_capture_outputs[output->index]; + + break; + } + case VIDIOC_G_OUTPUT: { + int *p_output_num = arg; + pr_debug(" case VIDIOC_G_OUTPUT\n"); + *p_output_num = cam->output; + break; + } + + case VIDIOC_S_OUTPUT: { + int *p_output_num = arg; + pr_debug(" case VIDIOC_S_OUTPUT\n"); + if (*p_output_num >= MXC_V4L2_CAPTURE_NUM_OUTPUTS) { + retval = -EINVAL; + break; + } + cam->output = *p_output_num; + break; + } + + case VIDIOC_ENUM_FMT: + case VIDIOC_TRY_FMT: + case VIDIOC_QUERYCTRL: + case VIDIOC_ENUMINPUT: + case VIDIOC_G_INPUT: + case VIDIOC_S_INPUT: + case VIDIOC_G_TUNER: + case VIDIOC_S_TUNER: + case VIDIOC_G_FREQUENCY: + case VIDIOC_S_FREQUENCY: + default: + pr_debug(" case default or not supported\n"); + retval = -EINVAL; + break; + } + + up(&cam->busy_lock); + return retval; +} + +/* + * V4L interface - ioctl function + * + * @return None + */ +static int mxc_v4l_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + pr_debug("In MVC:mxc_v4l_ioctl\n"); + return video_usercopy(inode, file, cmd, arg, mxc_v4l_do_ioctl); +} + +/*! + * V4L interface - mmap function + * + * @param file structure file * + * + * @param vma structure vm_area_struct * + * + * @return status 0 Success, EINTR busy lock error, ENOBUFS remap_page error + */ +static int mxc_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct video_device *dev = video_devdata(file); + unsigned long size; + int res = 0; + cam_data *cam = dev->priv; + + pr_debug("In MVC:mxc_mmap\n"); + pr_debug(" pgoff=0x%lx, start=0x%lx, end=0x%lx\n", + vma->vm_pgoff, vma->vm_start, vma->vm_end); + + /* make this _really_ smp-safe */ + if (down_interruptible(&cam->busy_lock)) + return -EINTR; + + size = vma->vm_end - vma->vm_start; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + if (remap_pfn_range(vma, vma->vm_start, + vma->vm_pgoff, size, vma->vm_page_prot)) { + pr_err("ERROR: v4l2 capture: mxc_mmap: " + "remap_pfn_range failed\n"); + res = -ENOBUFS; + goto mxc_mmap_exit; + } + + vma->vm_flags &= ~VM_IO; /* using shared anonymous pages */ + + mxc_mmap_exit: + up(&cam->busy_lock); + return res; +} + +/*! + * V4L interface - poll function + * + * @param file structure file * + * + * @param wait structure poll_table * + * + * @return status POLLIN | POLLRDNORM + */ +static unsigned int mxc_poll(struct file *file, poll_table *wait) +{ + struct video_device *dev = video_devdata(file); + cam_data *cam = dev->priv; + wait_queue_head_t *queue = NULL; + int res = POLLIN | POLLRDNORM; + + pr_debug("In MVC:mxc_poll\n"); + + if (down_interruptible(&cam->busy_lock)) + return -EINTR; + + queue = &cam->enc_queue; + poll_wait(file, queue, wait); + + up(&cam->busy_lock); + + return res; +} + +/*! + * This structure defines the functions to be called in this driver. + */ +static struct file_operations mxc_v4l_fops = { + .owner = THIS_MODULE, + .open = mxc_v4l_open, + .release = mxc_v4l_close, + .read = mxc_v4l_read, + .ioctl = mxc_v4l_ioctl, + .mmap = mxc_mmap, + .poll = mxc_poll, +}; + +static struct video_device mxc_v4l_template = { + .owner = THIS_MODULE, + .name = "Mxc Camera", + .type = 0, + .type2 = VID_TYPE_CAPTURE, + .fops = &mxc_v4l_fops, + .release = video_device_release, +}; + +/*! + * This function can be used to release any platform data on closing. + */ +static void camera_platform_release(struct device *device) +{ +} + +/*! Device Definition for Mt9v111 devices */ +static struct platform_device mxc_v4l2_devices = { + .name = "mxc_v4l2", + .dev = { + .release = camera_platform_release, + }, + .id = 0, +}; + +/*! + * Camera V4l2 callback function. + * + * @param mask u32 + * + * @param dev void device structure + * + * @return status + */ +static void camera_callback(u32 mask, void *dev) +{ + struct mxc_v4l_frame *done_frame; + struct mxc_v4l_frame *ready_frame; + + cam_data *cam = (cam_data *) dev; + if (cam == NULL) + return; + + pr_debug("In MVC:camera_callback\n"); + + if (list_empty(&cam->working_q)) { + pr_err("ERROR: v4l2 capture: camera_callback: " + "working queue empty\n"); + return; + } + + done_frame = + list_entry(cam->working_q.next, struct mxc_v4l_frame, queue); + if (done_frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) { + done_frame->buffer.flags |= V4L2_BUF_FLAG_DONE; + done_frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED; + + if (list_empty(&cam->ready_q)) { + cam->skip_frame++; + } else { + ready_frame = list_entry(cam->ready_q.next, + struct mxc_v4l_frame, + queue); + list_del(cam->ready_q.next); + list_add_tail(&ready_frame->queue, &cam->working_q); + cam->enc_update_eba(ready_frame->buffer.m.offset, + &cam->ping_pong_csi); + } + + /* Added to the done queue */ + list_del(cam->working_q.next); + list_add_tail(&done_frame->queue, &cam->done_q); + + /* Wake up the queue */ + cam->enc_counter++; + wake_up_interruptible(&cam->enc_queue); + } else { + pr_err("ERROR: v4l2 capture: camera_callback: " + "buffer not queued\n"); + } +} + +/*! + * initialize cam_data structure + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static void init_camera_struct(cam_data *cam) +{ + pr_debug("In MVC: init_camera_struct\n"); + + /* Default everything to 0 */ + memset(cam, 0, sizeof(cam_data)); + + init_MUTEX(&cam->param_lock); + init_MUTEX(&cam->busy_lock); + + cam->video_dev = video_device_alloc(); + if (cam->video_dev == NULL) + return; + + *(cam->video_dev) = mxc_v4l_template; + + video_set_drvdata(cam->video_dev, cam); + dev_set_drvdata(&mxc_v4l2_devices.dev, (void *)cam); + cam->video_dev->minor = -1; + + init_waitqueue_head(&cam->enc_queue); + init_waitqueue_head(&cam->still_queue); + + /* setup cropping */ + cam->crop_bounds.left = 0; + cam->crop_bounds.width = 640; + cam->crop_bounds.top = 0; + cam->crop_bounds.height = 480; + cam->crop_current = cam->crop_defrect = cam->crop_bounds; + ipu_csi_set_window_size(cam->crop_current.width, + cam->crop_current.height, cam->csi); + ipu_csi_set_window_pos(cam->crop_current.left, + cam->crop_current.top, cam->csi); + cam->streamparm.parm.capture.capturemode = 0; + + cam->standard.index = 0; + cam->standard.id = V4L2_STD_UNKNOWN; + cam->standard.frameperiod.denominator = 30; + cam->standard.frameperiod.numerator = 1; + cam->standard.framelines = 480; + cam->standard_autodetect = true; + cam->streamparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cam->streamparm.parm.capture.timeperframe = cam->standard.frameperiod; + cam->streamparm.parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + cam->overlay_on = false; + cam->capture_on = false; + cam->skip_frame = 0; + cam->v4l2_fb.flags = V4L2_FBUF_FLAG_OVERLAY; + + cam->v2f.fmt.pix.sizeimage = 352 * 288 * 3 / 2; + cam->v2f.fmt.pix.bytesperline = 288 * 3 / 2; + cam->v2f.fmt.pix.width = 288; + cam->v2f.fmt.pix.height = 352; + cam->v2f.fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420; + cam->win.w.width = 160; + cam->win.w.height = 160; + cam->win.w.left = 0; + cam->win.w.top = 0; + + cam->csi = 0; /* Need to determine how to set this correctly with + * multiple video input devices. */ + + cam->enc_callback = camera_callback; + init_waitqueue_head(&cam->power_queue); + spin_lock_init(&cam->int_lock); +} + +/*! + * camera_power function + * Turns Sensor power On/Off + * + * @param cam cam data struct + * @param cameraOn true to turn camera on, false to turn off power. + * + * @return status + */ +static u8 camera_power(cam_data *cam, bool cameraOn) +{ + pr_debug("In MVC:camera_power on=%d\n", cameraOn); + + if (cameraOn == true) { + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true); + vidioc_int_s_power(cam->sensor, 1); + } else { + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false); + vidioc_int_s_power(cam->sensor, 0); + } + return 0; +} + +/*! + * This function is called to put the sensor in a low power state. + * Refer to the document driver-model/driver.txt in the kernel source tree + * for more information. + * + * @param pdev the device structure used to give information on which I2C + * to suspend + * @param state the power state the device is entering + * + * @return The function returns 0 on success and -1 on failure. + */ +static int mxc_v4l2_suspend(struct platform_device *pdev, pm_message_t state) +{ + cam_data *cam = platform_get_drvdata(pdev); + + pr_debug("In MVC:mxc_v4l2_suspend\n"); + + if (cam == NULL) { + return -1; + } + + cam->low_power = true; + + if (cam->overlay_on == true) + stop_preview(cam); + if ((cam->capture_on == true) && cam->enc_disable) { + cam->enc_disable(cam); + } + camera_power(cam, false); + + return 0; +} + +/*! + * This function is called to bring the sensor back from a low power state. + * Refer to the document driver-model/driver.txt in the kernel source tree + * for more information. + * + * @param pdev the device structure + * + * @return The function returns 0 on success and -1 on failure + */ +static int mxc_v4l2_resume(struct platform_device *pdev) +{ + cam_data *cam = platform_get_drvdata(pdev); + + pr_debug("In MVC:mxc_v4l2_resume\n"); + + if (cam == NULL) { + return -1; + } + + cam->low_power = false; + wake_up_interruptible(&cam->power_queue); + + if (cam->overlay_on == true) + start_preview(cam); + if (cam->capture_on == true) + mxc_streamon(cam); + camera_power(cam, true); + + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxc_v4l2_driver = { + .driver = { + .name = "mxc_v4l2", + }, + .probe = NULL, + .remove = NULL, + .suspend = mxc_v4l2_suspend, + .resume = mxc_v4l2_resume, + .shutdown = NULL, +}; + +/*! + * Initializes the camera driver. + */ +static int mxc_v4l2_master_attach(struct v4l2_int_device *slave) +{ + cam_data *cam = slave->u.slave->master->priv; + struct v4l2_format cam_fmt; + + pr_debug("In MVC: mxc_v4l2_master_attach\n"); + pr_debug(" slave.name = %s\n", slave->name); + pr_debug(" master.name = %s\n", slave->u.slave->master->name); + + cam->sensor = slave; + if (slave == NULL) { + pr_err("ERROR: v4l2 capture: slave parameter not valid.\n"); + return -1; + } + + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true); + vidioc_int_dev_init(slave); + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false); + cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt); + + /* Used to detect TV in (type 1) vs. camera (type 0)*/ + cam->device_type = cam_fmt.fmt.pix.priv; + + /* Set the input size to the ipu for this device */ + cam->crop_bounds.top = cam->crop_bounds.left = 0; + cam->crop_bounds.width = cam_fmt.fmt.pix.width; + cam->crop_bounds.height = cam_fmt.fmt.pix.height; + + /* This also is the max crop size for this device. */ + cam->crop_defrect.top = cam->crop_defrect.left = 0; + cam->crop_defrect.width = cam_fmt.fmt.pix.width; + cam->crop_defrect.height = cam_fmt.fmt.pix.height; + + /* At this point, this is also the current image size. */ + cam->crop_current.top = cam->crop_current.left = 0; + cam->crop_current.width = cam_fmt.fmt.pix.width; + cam->crop_current.height = cam_fmt.fmt.pix.height; + + pr_debug("End of %s: v2f pix widthxheight %d x %d\n", + __func__, + cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); + pr_debug("End of %s: crop_bounds widthxheight %d x %d\n", + __func__, + cam->crop_bounds.width, cam->crop_bounds.height); + pr_debug("End of %s: crop_defrect widthxheight %d x %d\n", + __func__, + cam->crop_defrect.width, cam->crop_defrect.height); + pr_debug("End of %s: crop_current widthxheight %d x %d\n", + __func__, + cam->crop_current.width, cam->crop_current.height); + + return 0; +} + +/*! + * Disconnects the camera driver. + */ +static void mxc_v4l2_master_detach(struct v4l2_int_device *slave) +{ + pr_debug("In MVC:mxc_v4l2_master_detach\n"); + /* vidioc_int_dev_exit(slave); */ +} + +/*! + * Entry point for the V4L2 + * + * @return Error code indicating success or failure + */ +static __init int camera_init(void) +{ + u8 err = 0; + + pr_debug("In MVC:camera_init\n"); + + /* Register the device driver structure. */ + err = platform_driver_register(&mxc_v4l2_driver); + if (err != 0) { + pr_err("ERROR: v4l2 capture:camera_init: " + "platform_driver_register failed.\n"); + return err; + } + + /* Create g_cam and initialize it. */ + if ((g_cam = kmalloc(sizeof(cam_data), GFP_KERNEL)) == NULL) { + pr_err("ERROR: v4l2 capture: failed to register camera\n"); + platform_driver_unregister(&mxc_v4l2_driver); + return -1; + } + init_camera_struct(g_cam); + + /* Set up the v4l2 device and register it*/ + mxc_v4l2_int_device.priv = g_cam; + /* This function contains a bug that won't let this be rmmod'd. */ + v4l2_int_device_register(&mxc_v4l2_int_device); + + /* Register the I2C device */ + err = platform_device_register(&mxc_v4l2_devices); + if (err != 0) { + pr_err("ERROR: v4l2 capture: camera_init: " + "platform_device_register failed.\n"); + platform_driver_unregister(&mxc_v4l2_driver); + kfree(g_cam); + g_cam = NULL; + return err; + } + + /* register v4l video device */ + if (video_register_device(g_cam->video_dev, VFL_TYPE_GRABBER, video_nr) + == -1) { + platform_device_unregister(&mxc_v4l2_devices); + platform_driver_unregister(&mxc_v4l2_driver); + kfree(g_cam); + g_cam = NULL; + pr_err("ERROR: v4l2 capture: video_register_device failed\n"); + return -1; + } + pr_debug(" Video device registered: %s #%d\n", + g_cam->video_dev->name, g_cam->video_dev->minor); + + return err; +} + +/*! + * Exit and cleanup for the V4L2 + */ +static void __exit camera_exit(void) +{ + pr_debug("In MVC: camera_exit\n"); + + pr_info("V4L2 unregistering video\n"); + + if (g_cam->open_count) { + pr_err("ERROR: v4l2 capture:camera open " + "-- setting ops to NULL\n"); + } else { + pr_info("V4L2 freeing image input device\n"); + v4l2_int_device_unregister(&mxc_v4l2_int_device); + video_unregister_device(g_cam->video_dev); + platform_driver_unregister(&mxc_v4l2_driver); + platform_device_unregister(&mxc_v4l2_devices); + + mxc_free_frame_buf(g_cam); + kfree(g_cam); + g_cam = NULL; + } +} + +module_init(camera_init); +module_exit(camera_exit); + +module_param(video_nr, int, 0444); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("V4L2 capture driver for Mxc based cameras"); +MODULE_LICENSE("GPL"); +MODULE_SUPPORTED_DEVICE("video"); diff -urN linux-2.6.26/drivers/media/video/mxc/capture/mxc_v4l2_capture.h linux-2.6.26-lab126/drivers/media/video/mxc/capture/mxc_v4l2_capture.h --- linux-2.6.26/drivers/media/video/mxc/capture/mxc_v4l2_capture.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/mxc_v4l2_capture.h 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,195 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup MXC_V4L2_CAPTURE MXC V4L2 Video Capture Driver + */ +/*! + * @file mxc_v4l2_capture.h + * + * @brief mxc V4L2 capture device API Header file + * + * It include all the defines for frame operations, also three structure defines + * use case ops structure, common v4l2 driver structure and frame structure. + * + * @ingroup MXC_V4L2_CAPTURE + */ +#ifndef __MXC_V4L2_CAPTURE_H__ +#define __MXC_V4L2_CAPTURE_H__ + +#include +#include +#include + +#include +#include +#include + +#define FRAME_NUM 3 + +/*! + * v4l2 frame structure. + */ +struct mxc_v4l_frame { + u32 paddress; + void *vaddress; + int count; + int width; + int height; + + struct v4l2_buffer buffer; + struct list_head queue; + int index; +}; + +/* Only for old version. Will go away soon. */ +typedef struct { + u8 clk_mode; + u8 ext_vsync; + u8 Vsync_pol; + u8 Hsync_pol; + u8 pixclk_pol; + u8 data_pol; + u8 data_width; + u8 pack_tight; + u8 force_eof; + u8 data_en_pol; + u16 width; + u16 height; + u32 pixel_fmt; + u32 mclk; + u16 active_width; + u16 active_height; +} sensor_interface; + +/* Sensor control function */ +/* Only for old version. Will go away soon. */ +struct camera_sensor { + void (*set_color) (int bright, int saturation, int red, int green, + int blue); + void (*get_color) (int *bright, int *saturation, int *red, int *green, + int *blue); + void (*set_ae_mode) (int ae_mode); + void (*get_ae_mode) (int *ae_mode); + sensor_interface *(*config) (int *frame_rate, int high_quality); + sensor_interface *(*reset) (void); + void (*get_std) (v4l2_std_id *std); + void (*set_std) (v4l2_std_id std); + unsigned int csi; +}; + +/*! + * common v4l2 driver structure. + */ +typedef struct _cam_data { + struct video_device *video_dev; + int device_type; + + /* semaphore guard against SMP multithreading */ + struct semaphore busy_lock; + + int open_count; + + /* params lock for this camera */ + struct semaphore param_lock; + + /* Encoder */ + struct list_head ready_q; + struct list_head done_q; + struct list_head working_q; + int ping_pong_csi; + spinlock_t int_lock; + struct mxc_v4l_frame frame[FRAME_NUM]; + int skip_frame; + wait_queue_head_t enc_queue; + int enc_counter; + dma_addr_t rot_enc_bufs[2]; + void *rot_enc_bufs_vaddr[2]; + int rot_enc_buf_size[2]; + enum v4l2_buf_type type; + + /* still image capture */ + wait_queue_head_t still_queue; + int still_counter; + dma_addr_t still_buf; + void *still_buf_vaddr; + + /* overlay */ + struct v4l2_window win; + struct v4l2_framebuffer v4l2_fb; + dma_addr_t vf_bufs[2]; + void *vf_bufs_vaddr[2]; + int vf_bufs_size[2]; + dma_addr_t rot_vf_bufs[2]; + void *rot_vf_bufs_vaddr[2]; + int rot_vf_buf_size[2]; + bool overlay_active; + int output; + struct fb_info *overlay_fb; + + /* v4l2 format */ + struct v4l2_format v2f; + int rotation; + struct v4l2_mxc_offset offset; + + /* V4l2 control bit */ + int bright; + int hue; + int contrast; + int saturation; + int red; + int green; + int blue; + int ae_mode; + + /* standard */ + struct v4l2_streamparm streamparm; + struct v4l2_standard standard; + bool standard_autodetect; + + /* crop */ + struct v4l2_rect crop_bounds; + struct v4l2_rect crop_defrect; + struct v4l2_rect crop_current; + + int (*enc_update_eba) (dma_addr_t eba, int *bufferNum); + int (*enc_enable) (void *private); + int (*enc_disable) (void *private); + void (*enc_callback) (u32 mask, void *dev); + int (*vf_start_adc) (void *private); + int (*vf_stop_adc) (void *private); + int (*vf_start_sdc) (void *private); + int (*vf_stop_sdc) (void *private); + int (*csi_start) (void *private); + int (*csi_stop) (void *private); + + /* misc status flag */ + bool overlay_on; + bool capture_on; + int overlay_pid; + int capture_pid; + bool low_power; + wait_queue_head_t power_queue; + unsigned int csi; + + /* camera sensor interface */ + struct camera_sensor *cam_sensor; /* old version */ + struct v4l2_int_device *sensor; +} cam_data; + +#if defined(CONFIG_MXC_IPU_V1) || defined(CONFIG_VIDEO_MXC_EMMA_CAMERA) +void set_mclk_rate(uint32_t *p_mclk_freq); +#else +void set_mclk_rate(uint32_t *p_mclk_freq, uint32_t csi); +#endif +#endif /* __MXC_V4L2_CAPTURE_H__ */ diff -urN linux-2.6.26/drivers/media/video/mxc/capture/ov2640.c linux-2.6.26-lab126/drivers/media/video/mxc/capture/ov2640.c --- linux-2.6.26/drivers/media/video/mxc/capture/ov2640.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/ov2640.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,811 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ov2640.c + * + * @brief ov2640 camera driver functions + * + * @ingroup Camera + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "mxc_v4l2_capture.h" + +#define MIN_FPS 5 +#define MAX_FPS 30 +#define DEFAULT_FPS 30 + +#define OV2640_XCLK_MIN 6000000 +#define OV2640_XCLK_MAX 27000000 + +/* +enum ov2640_mode { + ov2640_mode_1600_1120, + ov2640_mode_800_600 +}; +*/ + +struct reg_value { + u8 reg; + u8 value; + int delay_ms; +}; + +static struct reg_value ov2640_setting_1600_1120[] = { + {0xff, 0x1, 0}, {0x12, 0x80, 1}, {0xff, 0, 0}, {0x2c, 0xff, 0}, + {0x2e, 0xdf, 0}, {0xff, 0x1, 0}, {0x3c, 0x32, 0}, {0x11, 0x01, 0}, + {0x09, 0x00, 0}, {0x04, 0x28, 0}, {0x13, 0xe5, 0}, {0x14, 0x48, 0}, + {0x2c, 0x0c, 0}, {0x33, 0x78, 0}, {0x3a, 0x33, 0}, {0x3b, 0xfb, 0}, + {0x3e, 0x00, 0}, {0x43, 0x11, 0}, {0x16, 0x10, 0}, {0x39, 0x82, 0}, + {0x35, 0x88, 0}, {0x22, 0x0a, 0}, {0x37, 0x40, 0}, {0x23, 0x00, 0}, + {0x34, 0xa0, 0}, {0x36, 0x1a, 0}, {0x06, 0x02, 0}, {0x07, 0xc0, 0}, + {0x0d, 0xb7, 0}, {0x0e, 0x01, 0}, {0x4c, 0x00, 0}, {0x4a, 0x81, 0}, + {0x21, 0x99, 0}, {0x24, 0x40, 0}, {0x25, 0x38, 0}, {0x26, 0x82, 0}, + {0x5c, 0x00, 0}, {0x63, 0x00, 0}, {0x46, 0x3f, 0}, {0x0c, 0x3c, 0}, + {0x5d, 0x55, 0}, {0x5e, 0x7d, 0}, {0x5f, 0x7d, 0}, {0x60, 0x55, 0}, + {0x61, 0x70, 0}, {0x62, 0x80, 0}, {0x7c, 0x05, 0}, {0x20, 0x80, 0}, + {0x28, 0x30, 0}, {0x6c, 0x00, 0}, {0x6d, 0x80, 0}, {0x6e, 00, 0}, + {0x70, 0x02, 0}, {0x71, 0x94, 0}, {0x73, 0xc1, 0}, {0x3d, 0x34, 0}, + {0x5a, 0x57, 0}, {0x4f, 0xbb, 0}, {0x50, 0x9c, 0}, {0xff, 0x00, 0}, + {0xe5, 0x7f, 0}, {0xf9, 0xc0, 0}, {0x41, 0x24, 0}, {0x44, 0x06, 0}, + {0xe0, 0x14, 0}, {0x76, 0xff, 0}, {0x33, 0xa0, 0}, {0x42, 0x20, 0}, + {0x43, 0x18, 0}, {0x4c, 0x00, 0}, {0x87, 0xd0, 0}, {0xd7, 0x03, 0}, + {0xd9, 0x10, 0}, {0xd3, 0x82, 0}, {0xc8, 0x08, 0}, {0xc9, 0x80, 0}, + {0x7c, 0x00, 0}, {0x7d, 0x00, 0}, {0x7c, 0x03, 0}, {0x7d, 0x48, 0}, + {0x7d, 0x48, 0}, {0x7c, 0x08, 0}, {0x7d, 0x20, 0}, {0x7d, 0x10, 0}, + {0x7d, 0x0e, 0}, {0x90, 0x00, 0}, {0x91, 0x0e, 0}, {0x91, 0x1a, 0}, + {0x91, 0x31, 0}, {0x91, 0x5a, 0}, {0x91, 0x69, 0}, {0x91, 0x75, 0}, + {0x91, 0x7e, 0}, {0x91, 0x88, 0}, {0x91, 0x8f, 0}, {0x91, 0x96, 0}, + {0x91, 0xa3, 0}, {0x91, 0xaf, 0}, {0x91, 0xc4, 0}, {0x91, 0xd7, 0}, + {0x91, 0xe8, 0}, {0x91, 0x20, 0}, {0x92, 0x00, 0}, {0x93, 0x06, 0}, + {0x93, 0xe3, 0}, {0x93, 0x03, 0}, {0x93, 0x03, 0}, {0x93, 0x00, 0}, + {0x93, 0x02, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, + {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, + {0x96, 0x00, 0}, {0x97, 0x08, 0}, {0x97, 0x19, 0}, {0x97, 0x02, 0}, + {0x97, 0x0c, 0}, {0x97, 0x24, 0}, {0x97, 0x30, 0}, {0x97, 0x28, 0}, + {0x97, 0x26, 0}, {0x97, 0x02, 0}, {0x97, 0x98, 0}, {0x97, 0x80, 0}, + {0x97, 0x00, 0}, {0x97, 0x00, 0}, {0xa4, 0x00, 0}, {0xa8, 0x00, 0}, + {0xc5, 0x11, 0}, {0xc6, 0x51, 0}, {0xbf, 0x80, 0}, {0xc7, 0x10, 0}, + {0xb6, 0x66, 0}, {0xb8, 0xa5, 0}, {0xb7, 0x64, 0}, {0xb9, 0x7c, 0}, + {0xb3, 0xaf, 0}, {0xb4, 0x97, 0}, {0xb5, 0xff, 0}, {0xb0, 0xc5, 0}, + {0xb1, 0x94, 0}, {0xb2, 0x0f, 0}, {0xc4, 0x5c, 0}, {0xa6, 0x00, 0}, + {0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x1b, 0}, {0xa7, 0x31, 0}, + {0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, + {0xa7, 0x19, 0}, {0xa7, 0x31, 0}, {0xa7, 0x00, 0}, {0xa7, 0x18, 0}, + {0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x19, 0}, {0xa7, 0x31, 0}, + {0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xc0, 0xc8, 0}, {0xc1, 0x96, 0}, + {0x86, 0x3d, 0}, {0x50, 0x00, 0}, {0x51, 0x90, 0}, {0x52, 0x18, 0}, + {0x53, 0x00, 0}, {0x54, 0x00, 0}, {0x55, 0x88, 0}, {0x57, 0x00, 0}, + {0x5a, 0x90, 0}, {0x5b, 0x18, 0}, {0x5c, 0x05, 0}, {0xc3, 0xef, 0}, + {0x7f, 0x00, 0}, {0xda, 0x01, 0}, {0xe5, 0x1f, 0}, {0xe1, 0x67, 0}, + {0xe0, 0x00, 0}, {0xdd, 0x7f, 0}, {0x05, 0x00, 0} +}; + +static struct reg_value ov2640_setting_800_600[] = { + {0xff, 0, 0}, {0xff, 1, 0}, {0x12, 0x80, 1}, {0xff, 00, 0}, + {0x2c, 0xff, 0}, {0x2e, 0xdf, 0}, {0xff, 0x1, 0}, {0x3c, 0x32, 0}, + {0x11, 0x01, 0}, {0x09, 0x00, 0}, {0x04, 0x28, 0}, {0x13, 0xe5, 0}, + {0x14, 0x48, 0}, {0x2c, 0x0c, 0}, {0x33, 0x78, 0}, {0x3a, 0x33, 0}, + {0x3b, 0xfb, 0}, {0x3e, 0x00, 0}, {0x43, 0x11, 0}, {0x16, 0x10, 0}, + {0x39, 0x92, 0}, {0x35, 0xda, 0}, {0x22, 0x1a, 0}, {0x37, 0xc3, 0}, + {0x23, 0x00, 0}, {0x34, 0xc0, 0}, {0x36, 0x1a, 0}, {0x06, 0x88, 0}, + {0x07, 0xc0, 0}, {0x0d, 0x87, 0}, {0x0e, 0x41, 0}, {0x4c, 0x00, 0}, + {0x4a, 0x81, 0}, {0x21, 0x99, 0}, {0x24, 0x40, 0}, {0x25, 0x38, 0}, + {0x26, 0x82, 0}, {0x5c, 0x00, 0}, {0x63, 0x00, 0}, {0x46, 0x22, 0}, + {0x0c, 0x3c, 0}, {0x5d, 0x55, 0}, {0x5e, 0x7d, 0}, {0x5f, 0x7d, 0}, + {0x60, 0x55, 0}, {0x61, 0x70, 0}, {0x62, 0x80, 0}, {0x7c, 0x05, 0}, + {0x20, 0x80, 0}, {0x28, 0x30, 0}, {0x6c, 0x00, 0}, {0x6d, 0x80, 0}, + {0x6e, 00, 0}, {0x70, 0x02, 0}, {0x71, 0x94, 0}, {0x73, 0xc1, 0}, + {0x12, 0x40, 0}, {0x17, 0x11, 0}, {0x18, 0x43, 0}, {0x19, 0x00, 0}, + {0x1a, 0x4b, 0}, {0x32, 0x09, 0}, {0x37, 0xc0, 0}, {0x4f, 0xca, 0}, + {0x50, 0xa8, 0}, {0x6d, 0x00, 0}, {0x3d, 0x38, 0}, {0xff, 0x00, 0}, + {0xe5, 0x7f, 0}, {0xf9, 0xc0, 0}, {0x41, 0x24, 0}, {0x44, 0x06, 0}, + {0xe0, 0x14, 0}, {0x76, 0xff, 0}, {0x33, 0xa0, 0}, {0x42, 0x20, 0}, + {0x43, 0x18, 0}, {0x4c, 0x00, 0}, {0x87, 0xd0, 0}, {0x88, 0x3f, 0}, + {0xd7, 0x03, 0}, {0xd9, 0x10, 0}, {0xd3, 0x82, 0}, {0xc8, 0x08, 0}, + {0xc9, 0x80, 0}, {0x7c, 0x00, 0}, {0x7d, 0x00, 0}, {0x7c, 0x03, 0}, + {0x7d, 0x48, 0}, {0x7d, 0x48, 0}, {0x7c, 0x08, 0}, {0x7d, 0x20, 0}, + {0x7d, 0x10, 0}, {0x7d, 0x0e, 0}, {0x90, 0x00, 0}, {0x91, 0x0e, 0}, + {0x91, 0x1a, 0}, {0x91, 0x31, 0}, {0x91, 0x5a, 0}, {0x91, 0x69, 0}, + {0x91, 0x75, 0}, {0x91, 0x7e, 0}, {0x91, 0x88, 0}, {0x91, 0x8f, 0}, + {0x91, 0x96, 0}, {0x91, 0xa3, 0}, {0x91, 0xaf, 0}, {0x91, 0xc4, 0}, + {0x91, 0xd7, 0}, {0x91, 0xe8, 0}, {0x91, 0x20, 0}, {0x92, 0x00, 0}, + {0x93, 0x06, 0}, {0x93, 0xe3, 0}, {0x93, 0x03, 0}, {0x93, 0x03, 0}, + {0x93, 0x00, 0}, {0x93, 0x02, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, + {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, + {0x93, 0x00, 0}, {0x96, 0x00, 0}, {0x97, 0x08, 0}, {0x97, 0x19, 0}, + {0x97, 0x02, 0}, {0x97, 0x0c, 0}, {0x97, 0x24, 0}, {0x97, 0x30, 0}, + {0x97, 0x28, 0}, {0x97, 0x26, 0}, {0x97, 0x02, 0}, {0x97, 0x98, 0}, + {0x97, 0x80, 0}, {0x97, 0x00, 0}, {0x97, 0x00, 0}, {0xa4, 0x00, 0}, + {0xa8, 0x00, 0}, {0xc5, 0x11, 0}, {0xc6, 0x51, 0}, {0xbf, 0x80, 0}, + {0xc7, 0x10, 0}, {0xb6, 0x66, 0}, {0xb8, 0xa5, 0}, {0xb7, 0x64, 0}, + {0xb9, 0x7c, 0}, {0xb3, 0xaf, 0}, {0xb4, 0x97, 0}, {0xb5, 0xff, 0}, + {0xb0, 0xc5, 0}, {0xb1, 0x94, 0}, {0xb2, 0x0f, 0}, {0xc4, 0x5c, 0}, + {0xa6, 0x00, 0}, {0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x1b, 0}, + {0xa7, 0x31, 0}, {0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xa7, 0x20, 0}, + {0xa7, 0xd8, 0}, {0xa7, 0x19, 0}, {0xa7, 0x31, 0}, {0xa7, 0x00, 0}, + {0xa7, 0x18, 0}, {0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x19, 0}, + {0xa7, 0x31, 0}, {0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xc0, 0x64, 0}, + {0xc1, 0x4b, 0}, {0x86, 0x1d, 0}, {0x50, 0x00, 0}, {0x51, 0xc8, 0}, + {0x52, 0x96, 0}, {0x53, 0x00, 0}, {0x54, 0x00, 0}, {0x55, 0x00, 0}, + {0x57, 0x00, 0}, {0x5a, 0xc8, 0}, {0x5b, 0x96, 0}, {0x5c, 0x00, 0}, + {0xc3, 0xef, 0}, {0x7f, 0x00, 0}, {0xda, 0x01, 0}, {0xe5, 0x1f, 0}, + {0xe1, 0x67, 0}, {0xe0, 0x00, 0}, {0xdd, 0x7f, 0}, {0x05, 0x00, 0} +}; + +/*! + * Maintains the information on the current state of the sesor. + */ +struct sensor { + const struct ov2640_platform_data *platform_data; + struct v4l2_int_device *v4l2_int_device; + struct i2c_client *i2c_client; + struct v4l2_pix_format pix; + struct v4l2_captureparm streamcap; + bool on; + + /* control settings */ + int brightness; + int hue; + int contrast; + int saturation; + int red; + int green; + int blue; + int ae_mode; + + u32 csi; + u32 mclk; + +} ov2640_data; + +static struct regulator *io_regulator; +static struct regulator *core_regulator; +static struct regulator *analog_regulator; +static struct regulator *gpo_regulator; + +extern void gpio_sensor_active(void); +extern void gpio_sensor_inactive(void); + +/* list of image formats supported by this sensor */ +/* +const static struct v4l2_fmtdesc ov2640_formats[] = { + { + .description = "YUYV (YUV 4:2:2), packed", + .pixelformat = V4L2_PIX_FMT_UYVY, + }, +}; + */ + +static int ov2640_init_mode(struct sensor *s) +{ + int ret; + struct reg_value *setting; + int i, num; + + pr_debug("In ov2640:ov2640_init_mode capturemode is %d\n", + s->streamcap.capturemode); + + if (s->streamcap.capturemode & V4L2_MODE_HIGHQUALITY) { + s->pix.width = 1600; + s->pix.height = 1120; + setting = ov2640_setting_1600_1120; + num = ARRAY_SIZE(ov2640_setting_1600_1120); + } else { + s->pix.width = 800; + s->pix.height = 600; + setting = ov2640_setting_800_600; + num = ARRAY_SIZE(ov2640_setting_800_600); + } + + for (i = 0; i < num; i++) { + ret = i2c_smbus_write_byte_data(s->i2c_client, + setting[i].reg, + setting[i].value); + if (ret < 0) { + pr_err("write reg error: reg=%x, val=%x\n", + setting[i].reg, setting[i].value); + return ret; + } + if (setting[i].delay_ms > 0) + msleep(setting[i].delay_ms); + } + + return ret; +} + +/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */ + +/*! + * ioctl_g_ifparm - V4L2 sensor interface handler for vidioc_int_g_ifparm_num + * s: pointer to standard V4L2 device structure + * p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure + * + * Gets slave interface parameters. + * Calculates the required xclk value to support the requested + * clock parameters in p. This value is returned in the p + * parameter. + * + * vidioc_int_g_ifparm returns platform-specific information about the + * interface settings used by the sensor. + * + * Given the image capture format in pix, the nominal frame period in + * timeperframe, calculate the required xclk frequency. + * + * Called on open. + */ +static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) +{ + pr_debug("In ov2640:ioctl_g_ifparm\n"); + + if (s == NULL) { + pr_err(" ERROR!! no slave device set!\n"); + return -1; + } + + memset(p, 0, sizeof(*p)); + p->u.bt656.clock_curr = ov2640_data.mclk; + p->if_type = V4L2_IF_TYPE_BT656; + p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; + p->u.bt656.clock_min = OV2640_XCLK_MIN; + p->u.bt656.clock_max = OV2640_XCLK_MAX; + + return 0; +} + +/*! + * Sets the camera power. + * + * s pointer to the camera device + * on if 1, power is to be turned on. 0 means power is to be turned off + * + * ioctl_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num + * @s: pointer to standard V4L2 device structure + * @on: power state to which device is to be set + * + * Sets devices power state to requrested state, if possible. + * This is called on open, close, suspend and resume. + */ +static int ioctl_s_power(struct v4l2_int_device *s, int on) +{ + struct sensor *sensor = s->priv; + + pr_debug("In ov2640:ioctl_s_power\n"); + + if (on && !sensor->on) { + gpio_sensor_active(); + if (!IS_ERR_VALUE((unsigned long)io_regulator)) + if (regulator_enable(io_regulator) != 0) + return -EIO; + if (!IS_ERR_VALUE((unsigned long)core_regulator)) + if (regulator_enable(core_regulator) != 0) + return -EIO; + if (!IS_ERR_VALUE((unsigned long)gpo_regulator)) + if (regulator_enable(gpo_regulator) != 0) + return -EIO; + if (!IS_ERR_VALUE((unsigned long)analog_regulator)) + if (regulator_enable(analog_regulator) != 0) + return -EIO; + } else if (!on && sensor->on) { + if (!IS_ERR_VALUE((unsigned long)analog_regulator)) + regulator_disable(analog_regulator); + if (!IS_ERR_VALUE((unsigned long)core_regulator)) + regulator_disable(core_regulator); + if (!IS_ERR_VALUE((unsigned long)io_regulator)) + regulator_disable(io_regulator); + if (!IS_ERR_VALUE((unsigned long)gpo_regulator)) + regulator_disable(gpo_regulator); + gpio_sensor_inactive(); + } + + sensor->on = on; + + return 0; +} + +/*! + * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure + * + * Returns the sensor's video CAPTURE parameters. + */ +static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor *sensor = s->priv; + struct v4l2_captureparm *cparm = &a->parm.capture; + int ret = 0; + + pr_debug("In ov2640:ioctl_g_parm\n"); + + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); + memset(a, 0, sizeof(*a)); + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cparm->capability = sensor->streamcap.capability; + cparm->timeperframe = sensor->streamcap.timeperframe; + cparm->capturemode = sensor->streamcap.capturemode; + ret = 0; + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + pr_err(" type is not V4L2_BUF_TYPE_VIDEO_CAPTURE " \ + "but %d\n", a->type); + ret = -EINVAL; + break; + + default: + pr_err(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure + * + * Configures the sensor to use the input parameters, if possible. If + * not possible, reverts to the old parameters and returns the + * appropriate error code. + */ +static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor *sensor = s->priv; + struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe; + u32 tgt_fps; /* target frames per secound */ + int ret = 0; + + pr_debug("In ov2640:ioctl_s_parm\n"); + + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); + + /* Check that the new frame rate is allowed. */ + if ((timeperframe->numerator == 0) + || (timeperframe->denominator == 0)) { + timeperframe->denominator = DEFAULT_FPS; + timeperframe->numerator = 1; + } + tgt_fps = timeperframe->denominator + / timeperframe->numerator; + + if (tgt_fps > MAX_FPS) { + timeperframe->denominator = MAX_FPS; + timeperframe->numerator = 1; + } else if (tgt_fps < MIN_FPS) { + timeperframe->denominator = MIN_FPS; + timeperframe->numerator = 1; + } + sensor->streamcap.timeperframe = *timeperframe; + sensor->streamcap.capturemode = + (u32)a->parm.capture.capturemode; + + ret = ov2640_init_mode(sensor); + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + pr_err(" type is not V4L2_BUF_TYPE_VIDEO_CAPTURE " \ + "but %d\n", a->type); + ret = -EINVAL; + break; + + default: + pr_err(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap + * @s: pointer to standard V4L2 device structure + * @f: pointer to standard V4L2 v4l2_format structure + * + * Returns the sensor's current pixel format in the v4l2_format + * parameter. + */ +static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) +{ + struct sensor *sensor = s->priv; + + pr_debug("In ov2640:ioctl_g_fmt_cap.\n"); + + f->fmt.pix = sensor->pix; + + return 0; +} + +/*! + * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure + * + * If the requested control is supported, returns the control's current + * value from the video_control[] array. Otherwise, returns -EINVAL + * if the control is not supported. + */ +static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int ret = 0; + + pr_debug("In ov2640:ioctl_g_ctrl\n"); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + vc->value = ov2640_data.brightness; + break; + case V4L2_CID_HUE: + vc->value = ov2640_data.hue; + break; + case V4L2_CID_CONTRAST: + vc->value = ov2640_data.contrast; + break; + case V4L2_CID_SATURATION: + vc->value = ov2640_data.saturation; + break; + case V4L2_CID_RED_BALANCE: + vc->value = ov2640_data.red; + break; + case V4L2_CID_BLUE_BALANCE: + vc->value = ov2640_data.blue; + break; + case V4L2_CID_EXPOSURE: + vc->value = ov2640_data.ae_mode; + break; + default: + ret = -EINVAL; + } + + return ret; +} + +/*! + * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure + * + * If the requested control is supported, sets the control's current + * value in HW (and updates the video_control[] array). Otherwise, + * returns -EINVAL if the control is not supported. + */ +static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int retval = 0; + + pr_debug("In ov2640:ioctl_s_ctrl %d\n", vc->id); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + pr_debug(" V4L2_CID_BRIGHTNESS\n"); + break; + case V4L2_CID_CONTRAST: + pr_debug(" V4L2_CID_CONTRAST\n"); + break; + case V4L2_CID_SATURATION: + pr_debug(" V4L2_CID_SATURATION\n"); + break; + case V4L2_CID_HUE: + pr_debug(" V4L2_CID_HUE\n"); + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + pr_debug( + " V4L2_CID_AUTO_WHITE_BALANCE\n"); + break; + case V4L2_CID_DO_WHITE_BALANCE: + pr_debug( + " V4L2_CID_DO_WHITE_BALANCE\n"); + break; + case V4L2_CID_RED_BALANCE: + pr_debug(" V4L2_CID_RED_BALANCE\n"); + break; + case V4L2_CID_BLUE_BALANCE: + pr_debug(" V4L2_CID_BLUE_BALANCE\n"); + break; + case V4L2_CID_GAMMA: + pr_debug(" V4L2_CID_GAMMA\n"); + break; + case V4L2_CID_EXPOSURE: + pr_debug(" V4L2_CID_EXPOSURE\n"); + break; + case V4L2_CID_AUTOGAIN: + pr_debug(" V4L2_CID_AUTOGAIN\n"); + break; + case V4L2_CID_GAIN: + pr_debug(" V4L2_CID_GAIN\n"); + break; + case V4L2_CID_HFLIP: + pr_debug(" V4L2_CID_HFLIP\n"); + break; + case V4L2_CID_VFLIP: + pr_debug(" V4L2_CID_VFLIP\n"); + break; + default: + pr_debug(" Default case\n"); + retval = -EPERM; + break; + } + + return retval; +} + +/*! + * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT + * @s: pointer to standard V4L2 device structure + */ +static int ioctl_init(struct v4l2_int_device *s) +{ + pr_debug("In ov2640:ioctl_init\n"); + + return 0; +} + +/*! + * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num + * @s: pointer to standard V4L2 device structure + * + * Initialise the device when slave attaches to the master. + */ +static int ioctl_dev_init(struct v4l2_int_device *s) +{ + struct sensor *sensor = s->priv; + u32 tgt_xclk; /* target xclk */ + + pr_debug("In ov2640:ioctl_dev_init\n"); + + gpio_sensor_active(); + ov2640_data.on = true; + + if (!IS_ERR_VALUE((unsigned long)io_regulator)) { + regulator_set_voltage(io_regulator, 2800000); + if (regulator_enable(io_regulator) != 0) + return -EIO; + } + if (!IS_ERR_VALUE((unsigned long)core_regulator)) { + regulator_set_voltage(core_regulator, 1300000); + if (regulator_enable(core_regulator) != 0) + return -EIO; + } + /*GPO 3 */ + if (!IS_ERR_VALUE((unsigned long)gpo_regulator)) { + if (regulator_enable(gpo_regulator) != 0) { + return -EIO; + } + } + if (!IS_ERR_VALUE((unsigned long)analog_regulator)) { + /* regulator_set_voltage(analog_regulator, 2800000); */ + regulator_set_voltage(analog_regulator, 2000000); + if (regulator_enable(analog_regulator) != 0) + return -EIO; + } + + tgt_xclk = ov2640_data.mclk; + tgt_xclk = min(tgt_xclk, (u32)OV2640_XCLK_MAX); + tgt_xclk = max(tgt_xclk, (u32)OV2640_XCLK_MIN); + ov2640_data.mclk = tgt_xclk; + + pr_debug(" Setting mclk to %d MHz\n", + tgt_xclk / 1000000); + set_mclk_rate(&ov2640_data.mclk); + + return ov2640_init_mode(sensor); +} + +/*! + * This structure defines all the ioctls for this module and links them to the + * enumeration. + */ +static struct v4l2_int_ioctl_desc ov2640_ioctl_desc[] = { + {vidioc_int_dev_init_num, (v4l2_int_ioctl_func *)ioctl_dev_init}, +/* {vidioc_int_dev_exit_num, (v4l2_int_ioctl_func *)ioctl_dev_exit}, */ + {vidioc_int_s_power_num, (v4l2_int_ioctl_func *)ioctl_s_power}, + {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func *)ioctl_g_ifparm}, +/* {vidioc_int_g_needs_reset_num, + (v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */ +/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */ + {vidioc_int_init_num, (v4l2_int_ioctl_func *)ioctl_init}, +/* {vidioc_int_enum_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap}, */ +/* {vidioc_int_try_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */ + {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_g_fmt_cap}, +/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap}, */ + {vidioc_int_g_parm_num, (v4l2_int_ioctl_func *)ioctl_g_parm}, + {vidioc_int_s_parm_num, (v4l2_int_ioctl_func *)ioctl_s_parm}, +/* {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func *)ioctl_queryctrl}, */ + {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *)ioctl_g_ctrl}, + {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *)ioctl_s_ctrl}, +}; + +static struct v4l2_int_slave ov2640_slave = { + .ioctls = ov2640_ioctl_desc, + .num_ioctls = ARRAY_SIZE(ov2640_ioctl_desc), +}; + +static struct v4l2_int_device ov2640_int_device = { + .module = THIS_MODULE, + .name = "ov2640", + .type = v4l2_int_type_slave, + .u = { + .slave = &ov2640_slave, + }, +}; + +/*! + * ov2640 I2C attach function + * Function set in i2c_driver struct. + * Called by insmod ov2640_camera.ko. + * + * @param client struct i2c_client* + * @return Error code indicating success or failure + */ +static int ov2640_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int retval; + struct mxc_camera_platform_data *plat_data = client->dev.platform_data; + + pr_debug("In ov2640_probe (RH_BT565)\n"); + + /* Set initial values for the sensor struct. */ + memset(&ov2640_data, 0, sizeof(ov2640_data)); + ov2640_data.i2c_client = client; + ov2640_data.mclk = 24000000; + ov2640_data.mclk = plat_data->mclk; + ov2640_data.pix.pixelformat = V4L2_PIX_FMT_UYVY; + ov2640_data.pix.width = 800; + ov2640_data.pix.height = 600; + ov2640_data.streamcap.capability = V4L2_MODE_HIGHQUALITY + | V4L2_CAP_TIMEPERFRAME; + ov2640_data.streamcap.capturemode = 0; + ov2640_data.streamcap.timeperframe.denominator = DEFAULT_FPS; + ov2640_data.streamcap.timeperframe.numerator = 1; + + io_regulator = regulator_get(&client->dev, plat_data->io_regulator); + core_regulator = regulator_get(&client->dev, plat_data->core_regulator); + analog_regulator = + regulator_get(&client->dev, plat_data->analog_regulator); + gpo_regulator = regulator_get(&client->dev, plat_data->gpo_regulator); + + /* This function attaches this structure to the /dev/video0 device. + * The pointer in priv points to the mt9v111_data structure here.*/ + ov2640_int_device.priv = &ov2640_data; + retval = v4l2_int_device_register(&ov2640_int_device); + + return retval; +} + +/*! + * ov2640 I2C detach function + * Called on rmmod ov2640_camera.ko + * + * @param client struct i2c_client* + * @return Error code indicating success or failure + */ +static int ov2640_remove(struct i2c_client *client) +{ + pr_debug("In ov2640_remove\n"); + + v4l2_int_device_unregister(&ov2640_int_device); + + if (!IS_ERR_VALUE((unsigned long)gpo_regulator)) { + regulator_disable(gpo_regulator); + regulator_put(gpo_regulator, &client->dev); + } + + if (!IS_ERR_VALUE((unsigned long)analog_regulator)) { + regulator_disable(analog_regulator); + regulator_put(analog_regulator, &client->dev); + } + + if (!IS_ERR_VALUE((unsigned long)core_regulator)) { + regulator_disable(core_regulator); + regulator_put(core_regulator, &client->dev); + } + + if (!IS_ERR_VALUE((unsigned long)io_regulator)) { + regulator_disable(io_regulator); + regulator_put(io_regulator, &client->dev); + } + + return 0; +} + +static const struct i2c_device_id ov2640_id[] = { + {"ov2640", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, ov2640_id); + +static struct i2c_driver ov2640_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "ov2640", + }, + .probe = ov2640_probe, + .remove = ov2640_remove, + .id_table = ov2640_id, +/* To add power management add .suspend and .resume functions */ +}; + +/*! + * ov2640 init function + * Called by insmod ov2640_camera.ko. + * + * @return Error code indicating success or failure + */ +static __init int ov2640_init(void) +{ + u8 err; + + pr_debug("In ov2640_init\n"); + + err = i2c_add_driver(&ov2640_i2c_driver); + if (err != 0) + pr_err("%s:driver registration failed, error=%d \n", + __func__, err); + + return err; +} + +/*! + * OV2640 cleanup function + * Called on rmmod ov2640_camera.ko + * + * @return Error code indicating success or failure + */ +static void __exit ov2640_clean(void) +{ + pr_debug("In ov2640_clean\n"); + i2c_del_driver(&ov2640_i2c_driver); + gpio_sensor_inactive(); +} + +module_init(ov2640_init); +module_exit(ov2640_clean); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("OV2640 Camera Driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/media/video/mxc/capture/ov3640.c linux-2.6.26-lab126/drivers/media/video/mxc/capture/ov3640.c --- linux-2.6.26/drivers/media/video/mxc/capture/ov3640.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/ov3640.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,1109 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_v4l2_capture.h" + +#define CAMERA_DBG + +#ifdef CAMERA_DBG + #define CAMERA_TRACE(x) (printk)x +#else + #define CAMERA_TRACE(x) +#endif + +#define OV3640_VOLTAGE_ANALOG 2800000 +#define OV3640_VOLTAGE_DIGITAL_CORE 1500000 +#define OV3640_VOLTAGE_DIGITAL_IO 1800000 + + +/* Check these values! */ +#define MIN_FPS 15 +#define MAX_FPS 30 +#define DEFAULT_FPS 30 + +#define OV3640_XCLK_MIN 6000000 +#define OV3640_XCLK_MAX 24000000 + +enum ov3640_mode { + ov3640_mode_MIN = 0, + ov3640_mode_VGA_640_480 = 0, + ov3640_mode_QVGA_320_240 = 1, + ov3640_mode_QXGA_2048_1536 = 2, + ov3640_mode_XGA_1024_768 = 3, + ov3640_mode_MAX = 3 +}; + +enum ov3640_frame_rate { + ov3640_15_fps, + ov3640_30_fps +}; + +struct reg_value { + u16 u16RegAddr; + u8 u8Val; + u8 u8Mask; + u32 u32Delay_ms; +}; + +struct ov3640_mode_info { + enum ov3640_mode mode; + u32 width; + u32 height; + struct reg_value *init_data_ptr; + u32 init_data_size; +}; + +/*! + * Maintains the information on the current state of the sesor. + */ +struct sensor { + const struct ov3640_platform_data *platform_data; + struct v4l2_int_device *v4l2_int_device; + struct i2c_client *i2c_client; + struct v4l2_pix_format pix; + struct v4l2_captureparm streamcap; + bool on; + + /* control settings */ + int brightness; + int hue; + int contrast; + int saturation; + int red; + int green; + int blue; + int ae_mode; + + u32 mclk; + int csi; +} ov3640_data; + +static struct reg_value ov3640_setting_15fps_QXGA_2048_1536[] = { + {0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0}, + {0x3087, 0x16, 0, 0}, {0x309c, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0}, + {0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0}, + {0x30b2, 0x10, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x3011, 0x00, 0, 0}, {0x304c, 0x81, 0, 0}, + {0x30d7, 0x10, 0, 0}, {0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0}, + {0x3016, 0x82, 0, 0}, {0x3018, 0x38, 0, 0}, {0x3019, 0x30, 0, 0}, + {0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, + {0x3082, 0x20, 0, 0}, {0x3015, 0x12, 0, 0}, {0x3014, 0x04, 0, 0}, + {0x3013, 0xf7, 0, 0}, {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, + {0x303e, 0x06, 0, 0}, {0x303f, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, + {0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, + {0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, + {0x3037, 0x6a, 0, 0}, {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, + {0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0}, {0x3300, 0x12, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, + {0x3314, 0x42, 0, 0}, {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, + {0x3310, 0xd0, 0, 0}, {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, + {0x330d, 0x18, 0, 0}, {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, + {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, + {0x336a, 0x52, 0, 0}, {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, + {0x30b8, 0x20, 0, 0}, {0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0}, + {0x30bb, 0x08, 0, 0}, {0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0}, + {0x3100, 0x02, 0, 0}, {0x3301, 0xde, 0, 0}, {0x3304, 0x00, 0, 0}, + {0x3400, 0x00, 0, 0}, {0x3404, 0x02, 0, 0}, {0x3600, 0xc4, 0, 0}, + {0x3302, 0xef, 0, 0}, {0x3020, 0x01, 0, 0}, {0x3021, 0x1d, 0, 0}, + {0x3022, 0x00, 0, 0}, {0x3023, 0x0a, 0, 0}, {0x3024, 0x08, 0, 0}, + {0x3025, 0x00, 0, 0}, {0x3026, 0x06, 0, 0}, {0x3027, 0x00, 0, 0}, + {0x335f, 0x68, 0, 0}, {0x3360, 0x00, 0, 0}, {0x3361, 0x00, 0, 0}, + {0x3362, 0x68, 0, 0}, {0x3363, 0x00, 0, 0}, {0x3364, 0x00, 0, 0}, + {0x3403, 0x00, 0, 0}, {0x3088, 0x08, 0, 0}, {0x3089, 0x00, 0, 0}, + {0x308a, 0x06, 0, 0}, {0x308b, 0x00, 0, 0}, {0x307c, 0x10, 0, 0}, + {0x3090, 0xc0, 0, 0}, {0x304c, 0x84, 0, 0}, {0x308d, 0x04, 0, 0}, + {0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, {0x3012, 0x00, 0, 0}, + {0x3020, 0x01, 0, 0}, {0x3021, 0x1d, 0, 0}, {0x3022, 0x00, 0, 0}, + {0x3023, 0x0a, 0, 0}, {0x3024, 0x08, 0, 0}, {0x3025, 0x18, 0, 0}, + {0x3026, 0x06, 0, 0}, {0x3027, 0x0c, 0, 0}, {0x302a, 0x06, 0, 0}, + {0x302b, 0x20, 0, 0}, {0x3075, 0x44, 0, 0}, {0x300d, 0x00, 0, 0}, + {0x30d7, 0x00, 0, 0}, {0x3069, 0x40, 0, 0}, {0x303e, 0x01, 0, 0}, + {0x303f, 0x80, 0, 0}, {0x3302, 0x20, 0, 0}, {0x335f, 0x68, 0, 0}, + {0x3360, 0x18, 0, 0}, {0x3361, 0x0c, 0, 0}, {0x3362, 0x68, 0, 0}, + {0x3363, 0x08, 0, 0}, {0x3364, 0x04, 0, 0}, {0x3403, 0x42, 0, 0}, + {0x3088, 0x08, 0, 0}, {0x3089, 0x00, 0, 0}, {0x308a, 0x06, 0, 0}, + {0x308b, 0x00, 0, 0}, +}; + +static struct reg_value ov3640_setting_15fps_XGA_1024_768[] = { + {0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0}, + {0x3087, 0x16, 0, 0}, {0x309c, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0}, + {0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0}, + {0x30b2, 0x10, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x3011, 0x00, 0, 0}, {0x304c, 0x81, 0, 0}, + {0x3016, 0x82, 0, 0}, {0x3018, 0x38, 0, 0}, {0x3019, 0x30, 0, 0}, + {0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, + {0x3082, 0x20, 0, 0}, {0x3015, 0x12, 0, 0}, {0x3014, 0x04, 0, 0}, + {0x3013, 0xf7, 0, 0}, {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, + {0x303e, 0x06, 0, 0}, {0x303f, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, + {0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, + {0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, + {0x3037, 0x6a, 0, 0}, {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, + {0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0}, {0x3300, 0x12, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, + {0x3314, 0x42, 0, 0}, {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, + {0x3310, 0xd0, 0, 0}, {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, + {0x330d, 0x18, 0, 0}, {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, + {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, + {0x336a, 0x52, 0, 0}, {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, + {0x30b8, 0x20, 0, 0}, {0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0}, + {0x30bb, 0x08, 0, 0}, {0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0}, + {0x3100, 0x02, 0, 0}, {0x3301, 0xde, 0, 0}, {0x3304, 0x00, 0, 0}, + {0x3400, 0x01, 0, 0}, {0x3404, 0x1d, 0, 0}, {0x3600, 0xc4, 0, 0}, + {0x3302, 0xef, 0, 0}, {0x3020, 0x01, 0, 0}, {0x3021, 0x1d, 0, 0}, + {0x3022, 0x00, 0, 0}, {0x3023, 0x0a, 0, 0}, {0x3024, 0x08, 0, 0}, + {0x3025, 0x00, 0, 0}, {0x3026, 0x06, 0, 0}, {0x3027, 0x00, 0, 0}, + {0x335f, 0x68, 0, 0}, {0x3360, 0x00, 0, 0}, {0x3361, 0x00, 0, 0}, + {0x3362, 0x34, 0, 0}, {0x3363, 0x00, 0, 0}, {0x3364, 0x00, 0, 0}, + {0x3403, 0x00, 0, 0}, {0x3088, 0x04, 0, 0}, {0x3089, 0x00, 0, 0}, + {0x308a, 0x03, 0, 0}, {0x308b, 0x00, 0, 0}, {0x307c, 0x10, 0, 0}, + {0x3090, 0xc0, 0, 0}, {0x304c, 0x84, 0, 0}, {0x308d, 0x04, 0, 0}, + {0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, {0x3011, 0x01, 0, 0}, +}; + +static struct reg_value ov3640_setting_30fps_XGA_1024_768[] = { + {0x0, 0x0, 0} +}; + +static struct reg_value ov3640_setting_15fps_VGA_640_480[] = { + {0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0}, + {0x3087, 0x16, 0, 0}, {0x309c, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0}, + {0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0}, + {0x30b2, 0x10, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x3011, 0x00, 0, 0}, {0x304c, 0x81, 0, 0}, + {0x30d7, 0x10, 0, 0}, {0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0}, + {0x3016, 0x82, 0, 0}, {0x3018, 0x38, 0, 0}, {0x3019, 0x30, 0, 0}, + {0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, + {0x3082, 0x20, 0, 0}, {0x3015, 0x12, 0, 0}, {0x3014, 0x04, 0, 0}, + {0x3013, 0xf7, 0, 0}, {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, + {0x303e, 0x06, 0, 0}, {0x303f, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, + {0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, + {0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, + {0x3037, 0x6a, 0, 0}, {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, + {0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0}, {0x3300, 0x12, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, + {0x3314, 0x42, 0, 0}, {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, + {0x3310, 0xd0, 0, 0}, {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, + {0x330d, 0x18, 0, 0}, {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, + {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, + {0x336a, 0x52, 0, 0}, {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, + {0x30b8, 0x20, 0, 0}, {0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0}, + {0x30bb, 0x08, 0, 0}, {0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0}, + {0x3100, 0x02, 0, 0}, {0x3301, 0xde, 0, 0}, {0x3304, 0x00, 0, 0}, + {0x3400, 0x00, 0, 0}, {0x3404, 0x42, 0, 0}, {0x3600, 0xc4, 0, 0}, + {0x3302, 0xef, 0, 0}, {0x3020, 0x01, 0, 0}, {0x3021, 0x1d, 0, 0}, + {0x3022, 0x00, 0, 0}, {0x3023, 0x0a, 0, 0}, {0x3024, 0x08, 0, 0}, + {0x3025, 0x00, 0, 0}, {0x3026, 0x06, 0, 0}, {0x3027, 0x00, 0, 0}, + {0x335f, 0x68, 0, 0}, {0x3360, 0x00, 0, 0}, {0x3361, 0x00, 0, 0}, + {0x3362, 0x12, 0, 0}, {0x3363, 0x80, 0, 0}, {0x3364, 0xe0, 0, 0}, + {0x3403, 0x00, 0, 0}, {0x3088, 0x02, 0, 0}, {0x3089, 0x80, 0, 0}, + {0x308a, 0x01, 0, 0}, {0x308b, 0xe0, 0, 0}, {0x307c, 0x10, 0, 0}, + {0x3090, 0xc0, 0, 0}, {0x304c, 0x84, 0, 0}, {0x308d, 0x04, 0, 0}, + {0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, {0x3011, 0x00, 0, 0}, +}; + +static struct reg_value ov3640_setting_30fps_VGA_640_480[] = { + {0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0}, + {0x3087, 0x16, 0, 0}, {0x309c, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0}, + {0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0}, + {0x30b2, 0x10, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x82, 0, 0}, + {0x30d7, 0x10, 0, 0}, {0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0}, + {0x3016, 0x82, 0, 0}, {0x3018, 0x38, 0, 0}, {0x3019, 0x30, 0, 0}, + {0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, + {0x3082, 0x20, 0, 0}, {0x3015, 0x12, 0, 0}, {0x3014, 0x0c, 0, 0}, + {0x3013, 0xf7, 0, 0}, {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, + {0x303e, 0x06, 0, 0}, {0x303f, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, + {0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, + {0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, + {0x3037, 0x6a, 0, 0}, {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, + {0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0}, {0x3300, 0x12, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, + {0x3314, 0x42, 0, 0}, {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, + {0x3310, 0xd0, 0, 0}, {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, + {0x330d, 0x18, 0, 0}, {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, + {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, + {0x336a, 0x52, 0, 0}, {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, + {0x3300, 0x13, 0, 0}, {0x30b8, 0x20, 0, 0}, {0x30b9, 0x17, 0, 0}, + {0x30ba, 0x04, 0, 0}, {0x30bb, 0x08, 0, 0}, {0x3100, 0x02, 0, 0}, + {0x3301, 0x10, 0x30, 0}, {0x3304, 0x00, 0x03, 0}, {0x3400, 0x00, 0, 0}, + {0x3404, 0x02, 0, 0}, {0x3600, 0xc0, 0, 0}, {0x308d, 0x04, 0, 0}, + {0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, {0x3012, 0x10, 0, 0}, + {0x3023, 0x06, 0, 0}, {0x3026, 0x03, 0, 0}, {0x3027, 0x04, 0, 0}, + {0x302a, 0x03, 0, 0}, {0x302b, 0x10, 0, 0}, {0x3075, 0x24, 0, 0}, + {0x300d, 0x01, 0, 0}, {0x30d7, 0x80, 0x80, 0}, {0x3069, 0x00, 0x40, 0}, + {0x303e, 0x00, 0, 0}, {0x303f, 0xc0, 0, 0}, {0x3302, 0x20, 0x20, 0}, + {0x335f, 0x34, 0, 0}, {0x3360, 0x0c, 0, 0}, {0x3361, 0x04, 0, 0}, + {0x3362, 0x12, 0, 0}, {0x3363, 0x88, 0, 0}, {0x3364, 0xe4, 0, 0}, + {0x3403, 0x42, 0, 0}, {0x3088, 0x02, 0, 0}, {0x3089, 0x80, 0, 0}, + {0x308a, 0x01, 0, 0}, {0x308b, 0xe0, 0, 0}, {0x3362, 0x12, 0, 0}, + {0x3363, 0x88, 0, 0}, {0x3364, 0xe4, 0, 0}, {0x3403, 0x42, 0, 0}, + {0x3088, 0x02, 0, 0}, {0x3089, 0x80, 0, 0}, {0x308a, 0x01, 0, 0}, + {0x308b, 0xe0, 0, 0}, {0x300e, 0x37, 0, 0}, {0x300f, 0xe1, 0, 0}, + {0x3010, 0x22, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x84, 0, 0}, + {0x3014, 0x04, 0, 0}, {0x3015, 0x02, 0, 0}, {0x302e, 0x00, 0, 0}, + {0x302d, 0x00, 0, 0}, +}; + +static struct reg_value ov3640_setting_15fps_QVGA_320_240[] = { + {0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0}, + {0x3087, 0x16, 0, 0}, {0x309c, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0}, + {0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0}, + {0x30b2, 0x10, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x3011, 0x00, 0, 0}, {0x304c, 0x81, 0, 0}, + {0x30d7, 0x10, 0, 0}, {0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0}, + {0x3016, 0x82, 0, 0}, {0x3018, 0x38, 0, 0}, {0x3019, 0x30, 0, 0}, + {0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, + {0x3082, 0x20, 0, 0}, {0x3015, 0x12, 0, 0}, {0x3014, 0x04, 0, 0}, + {0x3013, 0xf7, 0, 0}, {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, + {0x303e, 0x06, 0, 0}, {0x303f, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, + {0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, + {0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, + {0x3037, 0x6a, 0, 0}, {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, + {0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0}, {0x3300, 0x12, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, + {0x3314, 0x42, 0, 0}, {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, + {0x3310, 0xd0, 0, 0}, {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, + {0x330d, 0x18, 0, 0}, {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, + {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, + {0x336a, 0x52, 0, 0}, {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, + {0x30b8, 0x20, 0, 0}, {0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0}, + {0x30bb, 0x08, 0, 0}, {0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0}, + {0x3100, 0x02, 0, 0}, {0x3301, 0xde, 0, 0}, {0x3304, 0x00, 0, 0}, + {0x3400, 0x00, 0, 0}, {0x3404, 0x42, 0, 0}, {0x3600, 0xc4, 0, 0}, + {0x3302, 0xef, 0, 0}, {0x3020, 0x01, 0, 0}, {0x3021, 0x1d, 0, 0}, + {0x3022, 0x00, 0, 0}, {0x3023, 0x0a, 0, 0}, {0x3024, 0x08, 0, 0}, + {0x3025, 0x00, 0, 0}, {0x3026, 0x06, 0, 0}, {0x3027, 0x00, 0, 0}, + {0x335f, 0x68, 0, 0}, {0x3360, 0x00, 0, 0}, {0x3361, 0x00, 0, 0}, + {0x3362, 0x01, 0, 0}, {0x3363, 0x40, 0, 0}, {0x3364, 0xf0, 0, 0}, + {0x3403, 0x00, 0, 0}, {0x3088, 0x01, 0, 0}, {0x3089, 0x40, 0, 0}, + {0x308a, 0x00, 0, 0}, {0x308b, 0xf0, 0, 0}, {0x307c, 0x10, 0, 0}, + {0x3090, 0xc0, 0, 0}, {0x304c, 0x84, 0, 0}, {0x308d, 0x04, 0, 0}, + {0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, {0x3011, 0x01, 0, 0}, +}; + +static struct reg_value ov3640_setting_30fps_QVGA_320_240[] = { + {0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0}, + {0x3087, 0x16, 0, 0}, {0x309c, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0}, + {0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0}, + {0x30b2, 0x10, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x82, 0, 0}, + {0x30d7, 0x10, 0, 0}, {0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0}, + {0x3016, 0x82, 0, 0}, {0x3018, 0x38, 0, 0}, {0x3019, 0x30, 0, 0}, + {0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, + {0x3082, 0x20, 0, 0}, {0x3015, 0x12, 0, 0}, {0x3014, 0x0c, 0, 0}, + {0x3013, 0xf7, 0, 0}, {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, + {0x303e, 0x06, 0, 0}, {0x303f, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, + {0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, + {0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, + {0x3037, 0x6a, 0, 0}, {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, + {0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0}, {0x3300, 0x12, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, + {0x3314, 0x42, 0, 0}, {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, + {0x3310, 0xd0, 0, 0}, {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, + {0x330d, 0x18, 0, 0}, {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, + {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, + {0x336a, 0x52, 0, 0}, {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, + {0x3300, 0x13, 0, 0}, {0x30b8, 0x20, 0, 0}, {0x30b9, 0x17, 0, 0}, + {0x30ba, 0x04, 0, 0}, {0x30bb, 0x08, 0, 0}, {0x3100, 0x02, 0, 0}, + {0x3301, 0x10, 0x30, 0}, {0x3304, 0x00, 0x03, 0}, {0x3400, 0x00, 0, 0}, + {0x3404, 0x02, 0, 0}, {0x3600, 0xc0, 0, 0}, {0x308d, 0x04, 0, 0}, + {0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, {0x3012, 0x10, 0, 0}, + {0x3023, 0x06, 0, 0}, {0x3026, 0x03, 0, 0}, {0x3027, 0x04, 0, 0}, + {0x302a, 0x03, 0, 0}, {0x302b, 0x10, 0, 0}, {0x3075, 0x24, 0, 0}, + {0x300d, 0x01, 0, 0}, {0x30d7, 0x80, 0x80, 0}, {0x3069, 0x00, 0x40, 0}, + {0x303e, 0x00, 0, 0}, {0x303f, 0xc0, 0, 0}, {0x3302, 0x20, 0x20, 0}, + {0x335f, 0x34, 0, 0}, {0x3360, 0x0c, 0, 0}, {0x3361, 0x04, 0, 0}, + {0x3362, 0x34, 0, 0}, {0x3363, 0x08, 0, 0}, {0x3364, 0x04, 0, 0}, + {0x3403, 0x42, 0, 0}, {0x3088, 0x04, 0, 0}, {0x3089, 0x00, 0, 0}, + {0x308a, 0x03, 0, 0}, {0x308b, 0x00, 0, 0}, {0x3362, 0x12, 0, 0}, + {0x3363, 0x88, 0, 0}, {0x3364, 0xe4, 0, 0}, {0x3403, 0x42, 0, 0}, + {0x3088, 0x02, 0, 0}, {0x3089, 0x80, 0, 0}, {0x308a, 0x01, 0, 0}, + {0x308b, 0xe0, 0, 0}, {0x300e, 0x37, 0, 0}, {0x300f, 0xe1, 0, 0}, + {0x3010, 0x22, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x84, 0, 0}, +}; + +static struct ov3640_mode_info ov3640_mode_info_data[2][ov3640_mode_MAX + 1] = { + { + {ov3640_mode_VGA_640_480, 640, 480, + ov3640_setting_15fps_VGA_640_480, + ARRAY_SIZE(ov3640_setting_15fps_VGA_640_480)}, + {ov3640_mode_QVGA_320_240, 320, 240, + ov3640_setting_15fps_QVGA_320_240, + ARRAY_SIZE(ov3640_setting_15fps_QVGA_320_240)}, + {ov3640_mode_XGA_1024_768, 1024, 768, + ov3640_setting_15fps_XGA_1024_768, + ARRAY_SIZE(ov3640_setting_15fps_XGA_1024_768)}, + {ov3640_mode_QXGA_2048_1536, 2048, 1536, + ov3640_setting_15fps_QXGA_2048_1536, + ARRAY_SIZE(ov3640_setting_15fps_QXGA_2048_1536)}, + }, + { + {ov3640_mode_VGA_640_480, 640, 480, + ov3640_setting_30fps_VGA_640_480, + ARRAY_SIZE(ov3640_setting_30fps_VGA_640_480)}, + {ov3640_mode_QVGA_320_240, 320, 240, + ov3640_setting_30fps_QVGA_320_240, + ARRAY_SIZE(ov3640_setting_30fps_QVGA_320_240)}, + {ov3640_mode_XGA_1024_768, 1024, 768, + ov3640_setting_30fps_XGA_1024_768, + ARRAY_SIZE(ov3640_setting_30fps_XGA_1024_768)}, + {ov3640_mode_QXGA_2048_1536, 0, 0, NULL, 0}, + }, +}; + +static struct regulator *io_regulator; +static struct regulator *core_regulator; +static struct regulator *analog_regulator; +static struct regulator *gpo_regulator; + +static int ov3640_probe(struct i2c_client *adapter, + const struct i2c_device_id *device_id); +static int ov3640_remove(struct i2c_client *client); + +static s32 ov3640_read_reg(u16 reg, u8 *val); +static s32 ov3640_write_reg(u16 reg, u8 val); + +static const struct i2c_device_id ov3640_id[] = { + {"ov3640", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, ov3640_id); + +static struct i2c_driver ov3640_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "ov3640", + }, + .probe = ov3640_probe, + .remove = ov3640_remove, + .id_table = ov3640_id, +}; + +extern void gpio_sensor_active(unsigned int csi_index); +extern void gpio_sensor_inactive(unsigned int csi); + +static s32 ov3640_write_reg(u16 reg, u8 val) +{ + u8 au8Buf[3] = {0}; + + au8Buf[0] = reg >> 8; + au8Buf[1] = reg & 0xff; + au8Buf[2] = val; + + if (i2c_master_send(ov3640_data.i2c_client, au8Buf, 3) < 0) { + pr_err("%s:write reg error:reg=%x,val=%x\n", + __func__, reg, val); + return -1; + } + + return 0; +} + +static s32 ov3640_read_reg(u16 reg, u8 *val) +{ + u8 au8RegBuf[2] = {0}; + u8 u8RdVal = 0; + + au8RegBuf[0] = reg >> 8; + au8RegBuf[1] = reg & 0xff; + + if (2 != i2c_master_send(ov3640_data.i2c_client, au8RegBuf, 2)) { + pr_err("%s:write reg error:reg=%x\n", + __func__, reg); + return -1; + } + + if (1 != i2c_master_recv(ov3640_data.i2c_client, &u8RdVal, 1)) { + pr_err("%s:read reg error:reg=%x,val=%x\n", + __func__, reg, u8RdVal); + return -1; + } + + *val = u8RdVal; + + return u8RdVal; +} + +static int ov3640_init_mode(enum ov3640_frame_rate frame_rate, + enum ov3640_mode mode) +{ + struct reg_value *pModeSetting = NULL; + s32 i = 0; + s32 iModeSettingArySize = 0; + register u32 Delay_ms = 0; + register u16 RegAddr = 0; + register u8 Mask = 0; + register u8 Val = 0; + u8 RegVal = 0; + int retval = 0; + + CAMERA_TRACE(("CAMERA_DBG Entry: ov3640_init_mode\n")); + + if (mode > ov3640_mode_MAX || mode < ov3640_mode_MIN) { + pr_err("Wrong ov3640 mode detected!\n"); + return -1; + } + + pModeSetting = ov3640_mode_info_data[frame_rate][mode].init_data_ptr; + iModeSettingArySize = + ov3640_mode_info_data[frame_rate][mode].init_data_size; + + ov3640_data.pix.width = ov3640_mode_info_data[frame_rate][mode].width; + ov3640_data.pix.height = ov3640_mode_info_data[frame_rate][mode].height; + + for (i = 0; i < iModeSettingArySize; ++i, ++pModeSetting) { + Delay_ms = pModeSetting->u32Delay_ms; + RegAddr = pModeSetting->u16RegAddr; + Val = pModeSetting->u8Val; + Mask = pModeSetting->u8Mask; + + if (Mask) { + retval = ov3640_read_reg(RegAddr, &RegVal); + if (retval < 0) + goto err; + + RegVal &= ~(u8)Mask; + Val &= Mask; + Val |= RegVal; + } + + retval = ov3640_write_reg(RegAddr, Val); + if (retval < 0) + goto err; + + if (Delay_ms) + msleep(Delay_ms); + } +err: + CAMERA_TRACE(("CAMERA_DBG Exit: ov3640_init_mode\n")); + + return retval; +} + +/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */ + +static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) +{ + CAMERA_TRACE(("In ov3640:ioctl_g_ifparm\n")); + if (s == NULL) { + pr_err(" ERROR!! no slave device set!\n"); + return -1; + } + + memset(p, 0, sizeof(*p)); + p->u.bt656.clock_curr = ov3640_data.mclk; + pr_debug(" clock_curr=mclk=%d\n", ov3640_data.mclk); + p->if_type = V4L2_IF_TYPE_BT656; + p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; + p->u.bt656.clock_min = OV3640_XCLK_MIN; + p->u.bt656.clock_max = OV3640_XCLK_MAX; + p->u.bt656.bt_sync_correct = 1; /* Indicate external vsync */ + + return 0; +} + +/*! + * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl + * @s: pointer to standard V4L2 device structure + * @on: indicates power mode (on or off) + * + * Turns the power on or off, depending on the value of on and returns the + * appropriate error code. + */ +static int ioctl_s_power(struct v4l2_int_device *s, int on) +{ + struct sensor *sensor = s->priv; + + CAMERA_TRACE(("In ov3640:ioctl_s_power\n")); + + if (on && !sensor->on) { + gpio_sensor_active(ov3640_data.csi); + if (!IS_ERR_VALUE((unsigned long)io_regulator)) + if (regulator_enable(io_regulator) != 0) + return -EIO; + if (!IS_ERR_VALUE((unsigned long)core_regulator)) + if (regulator_enable(core_regulator) != 0) + return -EIO; + if (!IS_ERR_VALUE((unsigned long)gpo_regulator)) + if (regulator_enable(gpo_regulator) != 0) + return -EIO; + if (!IS_ERR_VALUE((unsigned long)analog_regulator)) + if (regulator_enable(analog_regulator) != 0) + return -EIO; + } else if (!on && sensor->on) { + if (!IS_ERR_VALUE((unsigned long)analog_regulator)) + regulator_disable(analog_regulator); + if (!IS_ERR_VALUE((unsigned long)core_regulator)) + regulator_disable(core_regulator); + if (!IS_ERR_VALUE((unsigned long)io_regulator)) + regulator_disable(io_regulator); + if (!IS_ERR_VALUE((unsigned long)gpo_regulator)) + regulator_disable(gpo_regulator); + gpio_sensor_inactive(ov3640_data.csi); + } + + sensor->on = on; + + return 0; +} + +/*! + * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure + * + * Returns the sensor's video CAPTURE parameters. + */ +static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor *sensor = s->priv; + struct v4l2_captureparm *cparm = &a->parm.capture; + int ret = 0; + + CAMERA_TRACE(("In ov3640:ioctl_g_parm\n")); + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + CAMERA_TRACE((" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n")); + memset(a, 0, sizeof(*a)); + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cparm->capability = sensor->streamcap.capability; + cparm->timeperframe = sensor->streamcap.timeperframe; + cparm->capturemode = sensor->streamcap.capturemode; + ret = 0; + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + CAMERA_TRACE((" type is not " \ + "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n", + a->type)); + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure + * + * Configures the sensor to use the input parameters, if possible. If + * not possible, reverts to the old parameters and returns the + * appropriate error code. + */ +static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor *sensor = s->priv; + struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe; + u32 tgt_fps; /* target frames per secound */ + enum ov3640_frame_rate frame_rate; + int ret = 0; + + CAMERA_TRACE(("In ov3640:ioctl_s_parm\n")); + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + CAMERA_TRACE((" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n")); + + /* Check that the new frame rate is allowed. */ + if ((timeperframe->numerator == 0) || + (timeperframe->denominator == 0)) { + timeperframe->denominator = DEFAULT_FPS; + timeperframe->numerator = 1; + } + + tgt_fps = timeperframe->denominator / + timeperframe->numerator; + + if (tgt_fps > MAX_FPS) { + timeperframe->denominator = MAX_FPS; + timeperframe->numerator = 1; + } else if (tgt_fps < MIN_FPS) { + timeperframe->denominator = MIN_FPS; + timeperframe->numerator = 1; + } + + /* Actual frame rate we use */ + tgt_fps = timeperframe->denominator / + timeperframe->numerator; + + if (tgt_fps == 15) + frame_rate = ov3640_15_fps; + else if (tgt_fps == 30) + frame_rate = ov3640_30_fps; + else { + pr_err(" The camera frame rate is not supported!\n"); + return -EINVAL; + } + + sensor->streamcap.timeperframe = *timeperframe; + sensor->streamcap.capturemode = + (u32)a->parm.capture.capturemode; + + ret = ov3640_init_mode(frame_rate, + sensor->streamcap.capturemode); + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + pr_debug(" type is not " \ + "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n", + a->type); + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap + * @s: pointer to standard V4L2 device structure + * @f: pointer to standard V4L2 v4l2_format structure + * + * Returns the sensor's current pixel format in the v4l2_format + * parameter. + */ +static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) +{ + struct sensor *sensor = s->priv; + + CAMERA_TRACE(("In ov3640:ioctl_g_fmt_cap.\n")); + + f->fmt.pix = sensor->pix; + + return 0; +} + +/*! + * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure + * + * If the requested control is supported, returns the control's current + * value from the video_control[] array. Otherwise, returns -EINVAL + * if the control is not supported. + */ +static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int ret = 0; + + CAMERA_TRACE(("In ov3640:ioctl_g_ctrl\n")); + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + vc->value = ov3640_data.brightness; + break; + case V4L2_CID_HUE: + vc->value = ov3640_data.hue; + break; + case V4L2_CID_CONTRAST: + vc->value = ov3640_data.contrast; + break; + case V4L2_CID_SATURATION: + vc->value = ov3640_data.saturation; + break; + case V4L2_CID_RED_BALANCE: + vc->value = ov3640_data.red; + break; + case V4L2_CID_BLUE_BALANCE: + vc->value = ov3640_data.blue; + break; + case V4L2_CID_EXPOSURE: + vc->value = ov3640_data.ae_mode; + break; + default: + ret = -EINVAL; + } + + return ret; +} + +/*! + * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure + * + * If the requested control is supported, sets the control's current + * value in HW (and updates the video_control[] array). Otherwise, + * returns -EINVAL if the control is not supported. + */ +static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int retval = 0; + + pr_debug("In ov3640:ioctl_s_ctrl %d\n", + vc->id); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + CAMERA_TRACE((" V4L2_CID_BRIGHTNESS\n")); + break; + case V4L2_CID_CONTRAST: + CAMERA_TRACE((" V4L2_CID_CONTRAST\n")); + break; + case V4L2_CID_SATURATION: + CAMERA_TRACE((" V4L2_CID_SATURATION\n")); + break; + case V4L2_CID_HUE: + CAMERA_TRACE((" V4L2_CID_HUE\n")); + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + CAMERA_TRACE((" V4L2_CID_AUTO_WHITE_BALANCE\n")); + break; + case V4L2_CID_DO_WHITE_BALANCE: + CAMERA_TRACE((" V4L2_CID_DO_WHITE_BALANCE\n")); + break; + case V4L2_CID_RED_BALANCE: + CAMERA_TRACE((" V4L2_CID_RED_BALANCE\n")); + break; + case V4L2_CID_BLUE_BALANCE: + CAMERA_TRACE((" V4L2_CID_BLUE_BALANCE\n")); + break; + case V4L2_CID_GAMMA: + CAMERA_TRACE((" V4L2_CID_GAMMA\n")); + break; + case V4L2_CID_EXPOSURE: + CAMERA_TRACE((" V4L2_CID_EXPOSURE\n")); + break; + case V4L2_CID_AUTOGAIN: + CAMERA_TRACE((" V4L2_CID_AUTOGAIN\n")); + break; + case V4L2_CID_GAIN: + CAMERA_TRACE((" V4L2_CID_GAIN\n")); + break; + case V4L2_CID_HFLIP: + CAMERA_TRACE((" V4L2_CID_HFLIP\n")); + break; + case V4L2_CID_VFLIP: + CAMERA_TRACE((" V4L2_CID_VFLIP\n")); + break; + default: + CAMERA_TRACE((" Default case\n")); + retval = -EPERM; + break; + } + + return retval; +} + +/*! + * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT + * @s: pointer to standard V4L2 device structure + */ +static int ioctl_init(struct v4l2_int_device *s) +{ + CAMERA_TRACE(("In ov3640:ioctl_init\n")); + + return 0; +} + +/*! + * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num + * @s: pointer to standard V4L2 device structure + * + * Initialise the device when slave attaches to the master. + */ +static int ioctl_dev_init(struct v4l2_int_device *s) +{ + struct sensor *sensor = s->priv; + u32 tgt_xclk; /* target xclk */ + u32 tgt_fps; /* target frames per secound */ + enum ov3640_frame_rate frame_rate; + + CAMERA_TRACE(("In ov3640:ioctl_dev_init\n")); + + gpio_sensor_active(ov3640_data.csi); + ov3640_data.on = true; + + /* mclk */ + tgt_xclk = ov3640_data.mclk; + tgt_xclk = min(tgt_xclk, (u32)OV3640_XCLK_MAX); + tgt_xclk = max(tgt_xclk, (u32)OV3640_XCLK_MIN); + ov3640_data.mclk = tgt_xclk; + + pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000); + set_mclk_rate(&ov3640_data.mclk, ov3640_data.csi); + + /* Default camera frame rate is set in probe */ + tgt_fps = sensor->streamcap.timeperframe.denominator / + sensor->streamcap.timeperframe.numerator; + + if (tgt_fps == 15) + frame_rate = ov3640_15_fps; + else if (tgt_fps == 30) + frame_rate = ov3640_30_fps; + else + return -EINVAL; /* Only support 15fps or 30fps now. */ + + return ov3640_init_mode(frame_rate, + sensor->streamcap.capturemode); +} + +/*! + * This structure defines all the ioctls for this module and links them to the + * enumeration. + */ +static struct v4l2_int_ioctl_desc ov3640_ioctl_desc[] = { + {vidioc_int_dev_init_num, (v4l2_int_ioctl_func *)ioctl_dev_init}, +/* {vidioc_int_dev_exit_num, (v4l2_int_ioctl_func *)ioctl_dev_exit}, */ + {vidioc_int_s_power_num, (v4l2_int_ioctl_func *)ioctl_s_power}, + {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func *)ioctl_g_ifparm}, +/* {vidioc_int_g_needs_reset_num, + (v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */ +/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */ + {vidioc_int_init_num, (v4l2_int_ioctl_func *)ioctl_init}, +/* {vidioc_int_enum_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap}, */ +/* {vidioc_int_try_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */ + {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_g_fmt_cap}, +/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap}, */ + {vidioc_int_g_parm_num, (v4l2_int_ioctl_func *)ioctl_g_parm}, + {vidioc_int_s_parm_num, (v4l2_int_ioctl_func *)ioctl_s_parm}, +/* {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func *)ioctl_queryctrl}, */ + {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *)ioctl_g_ctrl}, + {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *)ioctl_s_ctrl}, +}; + +static struct v4l2_int_slave ov3640_slave = { + .ioctls = ov3640_ioctl_desc, + .num_ioctls = ARRAY_SIZE(ov3640_ioctl_desc), +}; + +static struct v4l2_int_device ov3640_int_device = { + .module = THIS_MODULE, + .name = "ov3640", + .type = v4l2_int_type_slave, + .u = { + .slave = &ov3640_slave, + }, +}; + +/*! + * ov3640 I2C probe function + * + * @param adapter struct i2c_adapter * + * @return Error code indicating success or failure + */ +static int ov3640_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int retval; + struct mxc_camera_platform_data *plat_data = client->dev.platform_data; + + CAMERA_TRACE(("CAMERA_DBG Entry: ov3640_probe\n")); + + /* Set initial values for the sensor struct. */ + memset(&ov3640_data, 0, sizeof(ov3640_data)); + ov3640_data.mclk = 24000000; /* 6 - 54 MHz, typical 24MHz */ + ov3640_data.mclk = plat_data->mclk; + ov3640_data.csi = plat_data->csi; + + ov3640_data.i2c_client = client; + ov3640_data.pix.pixelformat = V4L2_PIX_FMT_UYVY; + ov3640_data.pix.width = 640; + ov3640_data.pix.height = 480; + ov3640_data.streamcap.capability = V4L2_MODE_HIGHQUALITY | + V4L2_CAP_TIMEPERFRAME; + ov3640_data.streamcap.capturemode = 0; + ov3640_data.streamcap.timeperframe.denominator = DEFAULT_FPS; + ov3640_data.streamcap.timeperframe.numerator = 1; + + io_regulator = regulator_get(&client->dev, plat_data->io_regulator); + if (!IS_ERR_VALUE((u32)io_regulator)) { + regulator_set_voltage(io_regulator, OV3640_VOLTAGE_DIGITAL_IO); + if (regulator_enable(io_regulator) != 0) { + pr_err("%s:io set voltage error\n", __func__); + goto err1; + } else { + dev_dbg(&client->dev, + "%s:io set voltage ok\n", __func__); + } + } + + core_regulator = regulator_get(&client->dev, plat_data->core_regulator); + if (!IS_ERR_VALUE((u32)core_regulator)) { + regulator_set_voltage(core_regulator, + OV3640_VOLTAGE_DIGITAL_CORE); + if (regulator_enable(core_regulator) != 0) { + pr_err("%s:core set voltage error\n", __func__); + goto err2; + } else { + dev_dbg(&client->dev, + "%s:core set voltage ok\n", __func__); + } + } + + analog_regulator = + regulator_get(&client->dev, plat_data->analog_regulator); + if (!IS_ERR_VALUE((u32)analog_regulator)) { + regulator_set_voltage(analog_regulator, OV3640_VOLTAGE_ANALOG); + if (regulator_enable(analog_regulator) != 0) { + pr_err("%s:analog set voltage error\n", __func__); + goto err3; + } else { + dev_dbg(&client->dev, + "%s:analog set voltage ok\n", __func__); + } + } + + gpo_regulator = regulator_get(&client->dev, plat_data->gpo_regulator); + if (!IS_ERR_VALUE((u32)gpo_regulator)) { + if (regulator_enable(gpo_regulator) != 0) { + pr_err("%s:gpo3 enable error\n", __func__); + goto err4; + } else { + dev_dbg(&client->dev, + "%s:gpo3 enable ok\n", __func__); + } + } + + ov3640_int_device.priv = &ov3640_data; + retval = v4l2_int_device_register(&ov3640_int_device); + + return retval; + +err4: + if (!IS_ERR_VALUE((u32)analog_regulator)) { + regulator_disable(analog_regulator); + regulator_put(analog_regulator, &client->dev); + } +err3: + if (!IS_ERR_VALUE((u32)core_regulator)) { + regulator_disable(core_regulator); + regulator_put(core_regulator, &client->dev); + } +err2: + if (!IS_ERR_VALUE((u32)io_regulator)) { + regulator_disable(io_regulator); + regulator_put(io_regulator, &client->dev); + } +err1: + return -1; +} + +/*! + * ov3640 I2C detach function + * + * @param client struct i2c_client * + * @return Error code indicating success or failure + */ +static int ov3640_remove(struct i2c_client *client) +{ + CAMERA_TRACE(("In ov3640_remove\n")); + + v4l2_int_device_unregister(&ov3640_int_device); + + if (!IS_ERR_VALUE((unsigned long)gpo_regulator)) { + regulator_disable(gpo_regulator); + regulator_put(gpo_regulator, &client->dev); + } + + if (!IS_ERR_VALUE((unsigned long)analog_regulator)) { + regulator_disable(analog_regulator); + regulator_put(analog_regulator, &client->dev); + } + + if (!IS_ERR_VALUE((unsigned long)core_regulator)) { + regulator_disable(core_regulator); + regulator_put(core_regulator, &client->dev); + } + + if (!IS_ERR_VALUE((unsigned long)io_regulator)) { + regulator_disable(io_regulator); + regulator_put(io_regulator, &client->dev); + } + + return 0; +} + +/*! + * ov3640 init function + * Called by insmod ov3640_camera.ko. + * + * @return Error code indicating success or failure + */ +static __init int ov3640_init(void) +{ + u8 err; + + CAMERA_TRACE(("CAMERA_DBG Entry: ov3640_init\n")); + + err = i2c_add_driver(&ov3640_i2c_driver); + if (err != 0) + pr_err("%s:driver registration failed, error=%d \n", + __func__, err); + + CAMERA_TRACE(("CAMERA_DBG Exit: ov3640_init\n")); + + return err; +} + +/*! + * OV3640 cleanup function + * Called on rmmod ov3640_camera.ko + * + * @return Error code indicating success or failure + */ +static void __exit ov3640_clean(void) +{ + CAMERA_TRACE(("CAMERA_DBG Entry: ov3640_clean\n")); + + i2c_del_driver(&ov3640_i2c_driver); + gpio_sensor_inactive(ov3640_data.csi); + + CAMERA_TRACE(("CAMERA_DBG Exit: ov3640_clean\n")); +} + +module_init(ov3640_init); +module_exit(ov3640_clean); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("OV3640 Camera Driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0"); +MODULE_ALIAS("CSI"); diff -urN linux-2.6.26/drivers/media/video/mxc/capture/sensor_clock.c linux-2.6.26-lab126/drivers/media/video/mxc/capture/sensor_clock.c --- linux-2.6.26/drivers/media/video/mxc/capture/sensor_clock.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/capture/sensor_clock.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,85 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file sensor_clock.c + * + * @brief camera clock function + * + * @ingroup Camera + */ +#include +#include +#include +#include +#include + +#if defined(CONFIG_MXC_IPU_V1) || defined(CONFIG_VIDEO_MXC_EMMA_CAMERA) +/* + * set_mclk_rate + * + * @param p_mclk_freq mclk frequence + * + */ +void set_mclk_rate(uint32_t * p_mclk_freq) +{ + struct clk *clk; + uint32_t freq = 0; + + clk = clk_get(NULL, "csi_clk"); + + freq = clk_round_rate(clk, *p_mclk_freq); + clk_set_rate(clk, freq); + + *p_mclk_freq = freq; + + clk_put(clk); + pr_debug("mclk frequency = %d\n", *p_mclk_freq); +} +#else +/* + * set_mclk_rate + * + * @param p_mclk_freq mclk frequence + * @param csi csi 0 or csi 1 + * + */ +void set_mclk_rate(uint32_t *p_mclk_freq, uint32_t csi) +{ + struct clk *clk; + uint32_t freq = 0; + char *mclk; + + if (csi == 0) { + mclk = "csi_mclk1"; + } else if (csi == 1) { + mclk = "csi_mclk2"; + } else { + pr_debug("invalid csi num %d\n", csi); + return; + } + + clk = clk_get(NULL, mclk); + + freq = clk_round_rate(clk, *p_mclk_freq); + clk_set_rate(clk, freq); + + *p_mclk_freq = freq; + + clk_put(clk); + pr_debug("%s frequency = %d\n", mclk, *p_mclk_freq); +} +#endif + +/* Exported symbols for modules. */ +EXPORT_SYMBOL(set_mclk_rate); diff -urN linux-2.6.26/drivers/media/video/mxc/opl/Makefile linux-2.6.26-lab126/drivers/media/video/mxc/opl/Makefile --- linux-2.6.26/drivers/media/video/mxc/opl/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/opl/Makefile 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,5 @@ +opl-objs := opl_mod.o rotate90_u16.o rotate270_u16.o \ + rotate90_u16_qcif.o rotate270_u16_qcif.o \ + vmirror_u16.o hmirror_rotate180_u16.o + +obj-$(CONFIG_VIDEO_MXC_OPL) += opl.o diff -urN linux-2.6.26/drivers/media/video/mxc/opl/hmirror_rotate180_u16.c linux-2.6.26-lab126/drivers/media/video/mxc/opl/hmirror_rotate180_u16.c --- linux-2.6.26/drivers/media/video/mxc/opl/hmirror_rotate180_u16.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/opl/hmirror_rotate180_u16.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,259 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include "opl.h" + +static inline u32 rot_left_u16(u16 x, unsigned int n) +{ + return (x << n) | (x >> (16 - n)); +} + +static inline u32 rot_left_u32(u32 x, unsigned int n) +{ + return (x << n) | (x >> (32 - n)); +} + +static inline u32 byte_swap_u32(u32 x) +{ + u32 t1, t2, t3; + + t1 = x ^ ((x << 16) | x >> 16); + t2 = t1 & 0xff00ffff; + t3 = (x >> 8) | (x << 24); + return t3 ^ (t2 >> 8); +} + +static int opl_hmirror_u16_by1(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride, + int vmirror); +static int opl_hmirror_u16_by2(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride, + int vmirror); +static int opl_hmirror_u16_by4(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride, + int vmirror); +static int opl_hmirror_u16_by8(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride, + int vmirror); + +int opl_hmirror_u16(const u8 * src, int src_line_stride, int width, int height, + u8 * dst, int dst_line_stride) +{ + if (!src || !dst) + return OPLERR_NULL_PTR; + + if (width == 0 || height == 0 || src_line_stride == 0 + || dst_line_stride == 0) + return OPLERR_BAD_ARG; + + if (width % 8 == 0) + return opl_hmirror_u16_by8(src, src_line_stride, width, height, + dst, dst_line_stride, 0); + else if (width % 4 == 0) + return opl_hmirror_u16_by4(src, src_line_stride, width, height, + dst, dst_line_stride, 0); + else if (width % 2 == 0) + return opl_hmirror_u16_by2(src, src_line_stride, width, height, + dst, dst_line_stride, 0); + else /* (width % 1) */ + return opl_hmirror_u16_by1(src, src_line_stride, width, height, + dst, dst_line_stride, 0); +} + +int opl_rotate180_u16(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride) +{ + if (!src || !dst) + return OPLERR_NULL_PTR; + + if (width == 0 || height == 0 || src_line_stride == 0 + || dst_line_stride == 0) + return OPLERR_BAD_ARG; + + if (width % 8 == 0) + return opl_hmirror_u16_by8(src, src_line_stride, width, height, + dst, dst_line_stride, 1); + else if (width % 4 == 0) + return opl_hmirror_u16_by4(src, src_line_stride, width, height, + dst, dst_line_stride, 1); + else if (width % 2 == 0) + return opl_hmirror_u16_by2(src, src_line_stride, width, height, + dst, dst_line_stride, 1); + else /* (width % 1) */ + return opl_hmirror_u16_by1(src, src_line_stride, width, height, + dst, dst_line_stride, 1); +} + +static int opl_hmirror_u16_by1(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride, + int vmirror) +{ + const u8 *src_row_addr; + const u8 *psrc; + u8 *dst_row_addr, *pdst; + int i, j; + u16 pixel; + + src_row_addr = src; + if (vmirror) { + dst_row_addr = dst + dst_line_stride * (height - 1); + dst_line_stride = -dst_line_stride; + } else + dst_row_addr = dst; + + /* Loop over all rows */ + for (i = 0; i < height; i++) { + /* Loop over each pixel */ + psrc = src_row_addr; + pdst = dst_row_addr + (width - 1) * BYTES_PER_PIXEL + - (BYTES_PER_PIXEL - BYTES_PER_PIXEL); + for (j = 0; j < width; j++) { + pixel = *(u16 *) psrc; + *(u16 *) pdst = pixel; + psrc += BYTES_PER_PIXEL; + pdst -= BYTES_PER_PIXEL; + } + src_row_addr += src_line_stride; + dst_row_addr += dst_line_stride; + } + + return OPLERR_SUCCESS; +} + +static int opl_hmirror_u16_by2(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride, + int vmirror) +{ + const u8 *src_row_addr; + const u8 *psrc; + u8 *dst_row_addr, *pdst; + int i, j; + u32 pixelsin, pixelsout; + + src_row_addr = src; + if (vmirror) { + dst_row_addr = dst + dst_line_stride * (height - 1); + dst_line_stride = -dst_line_stride; + } else + dst_row_addr = dst; + + /* Loop over all rows */ + for (i = 0; i < height; i++) { + /* Loop over each pixel */ + psrc = src_row_addr; + pdst = dst_row_addr + (width - 2) * BYTES_PER_PIXEL; + for (j = 0; j < (width >> 1); j++) { + pixelsin = *(u32 *) psrc; + pixelsout = rot_left_u32(pixelsin, 16); + *(u32 *) pdst = pixelsout; + psrc += BYTES_PER_2PIXEL; + pdst -= BYTES_PER_2PIXEL; + } + src_row_addr += src_line_stride; + dst_row_addr += dst_line_stride; + } + + return OPLERR_SUCCESS; +} + +static int opl_hmirror_u16_by4(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride, + int vmirror) +{ + const u8 *src_row_addr; + const u8 *psrc; + u8 *dst_row_addr, *pdst; + int i, j; + + union doubleword { + u64 dw; + u32 w[2]; + }; + + union doubleword inbuf; + union doubleword outbuf; + + src_row_addr = src; + if (vmirror) { + dst_row_addr = dst + dst_line_stride * (height - 1); + dst_line_stride = -dst_line_stride; + } else + dst_row_addr = dst; + + /* Loop over all rows */ + for (i = 0; i < height; i++) { + /* Loop over each pixel */ + psrc = src_row_addr; + pdst = dst_row_addr + (width - 4) * BYTES_PER_PIXEL; + for (j = 0; j < (width >> 2); j++) { + inbuf.dw = *(u64 *) psrc; + outbuf.w[0] = rot_left_u32(inbuf.w[1], 16); + outbuf.w[1] = rot_left_u32(inbuf.w[0], 16); + *(u64 *) pdst = outbuf.dw; + psrc += BYTES_PER_4PIXEL; + pdst -= BYTES_PER_4PIXEL; + } + src_row_addr += src_line_stride; + dst_row_addr += dst_line_stride; + } + return OPLERR_SUCCESS; +} + +static int opl_hmirror_u16_by8(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride, + int vmirror) +{ + const u8 *src_row_addr; + const u8 *psrc; + u8 *dst_row_addr, *pdst; + int i, j; + + src_row_addr = src; + if (vmirror) { + dst_row_addr = dst + dst_line_stride * (height - 1); + dst_line_stride = -dst_line_stride; + } else + dst_row_addr = dst; + + /* Loop over all rows */ + for (i = 0; i < height; i++) { + /* Loop over each pixel */ + psrc = src_row_addr; + pdst = dst_row_addr + (width - 1) * BYTES_PER_PIXEL - 2; + for (j = (width >> 3); j > 0; j--) { + __asm__ volatile ( + "ldmia %0!,{r2-r5}\n\t" + "mov r6, r2\n\t" + "mov r7, r3\n\t" + "mov r2, r5, ROR #16\n\t" + "mov r3, r4, ROR #16\n\t" + "mov r4, r7, ROR #16\n\t" + "mov r5, r6, ROR #16\n\t" + "stmda %1!,{r2-r5}\n\t" + + :"+r"(psrc), "+r"(pdst) + :"0"(psrc), "1"(pdst) + :"r2", "r3", "r4", "r5", "r6", "r7", + "memory" + ); + } + src_row_addr += src_line_stride; + dst_row_addr += dst_line_stride; + } + + return OPLERR_SUCCESS; +} + +EXPORT_SYMBOL(opl_hmirror_u16); +EXPORT_SYMBOL(opl_rotate180_u16); diff -urN linux-2.6.26/drivers/media/video/mxc/opl/opl.h linux-2.6.26-lab126/drivers/media/video/mxc/opl/opl.h --- linux-2.6.26/drivers/media/video/mxc/opl/opl.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/opl/opl.h 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,162 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup OPLIP OPL Image Processing + */ +/*! + * @file opl.h + * + * @brief The OPL (Open Primitives Library) Image Processing library defines + * efficient functions for rotation and mirroring. + * + * It includes ARM9-optimized rotation and mirroring functions. It is derived + * from the original OPL project which is found at sourceforge.freescale.net. + * + * @ingroup OPLIP + */ +#ifndef __OPL_H__ +#define __OPL_H__ + +#include + +#define BYTES_PER_PIXEL 2 +#define CACHE_LINE_WORDS 8 +#define BYTES_PER_WORD 4 + +#define BYTES_PER_2PIXEL (BYTES_PER_PIXEL * 2) +#define BYTES_PER_4PIXEL (BYTES_PER_PIXEL * 4) +#define BYTES_PER_8PIXEL (BYTES_PER_PIXEL * 8) + +#define QCIF_Y_WIDTH 176 +#define QCIF_Y_HEIGHT 144 + +/*! Enumerations of opl error code */ +enum opl_error { + OPLERR_SUCCESS = 0, + OPLERR_NULL_PTR, + OPLERR_BAD_ARG, + OPLERR_DIV_BY_ZERO, + OPLERR_OVER_FLOW, + OPLERR_UNDER_FLOW, + OPLERR_MISALIGNED, +}; + +/*! + * @brief Rotate a 16bbp buffer 90 degrees clockwise. + * + * @param src Pointer to the input buffer + * @param src_line_stride Length in bytes of a raster line of the input buffer + * @param width Width in pixels of the region in the input buffer + * @param height Height in pixels of the region in the input buffer + * @param dst Pointer to the output buffer + * @param dst_line_stride Length in bytes of a raster line of the output buffer + * + * @return Standard OPL error code. See enumeration for possible result codes. + */ +int opl_rotate90_u16(const u8 * src, int src_line_stride, int width, int height, + u8 * dst, int dst_line_stride); + +/*! + * @brief Rotate a 16bbp buffer 180 degrees clockwise. + * + * @param src Pointer to the input buffer + * @param src_line_stride Length in bytes of a raster line of the input buffer + * @param width Width in pixels of the region in the input buffer + * @param height Height in pixels of the region in the input buffer + * @param dst Pointer to the output buffer + * @param dst_line_stride Length in bytes of a raster line of the output buffer + * + * @return Standard OPL error code. See enumeration for possible result codes. + */ +int opl_rotate180_u16(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride); + +/*! + * @brief Rotate a 16bbp buffer 270 degrees clockwise + * + * @param src Pointer to the input buffer + * @param src_line_stride Length in bytes of a raster line of the input buffer + * @param width Width in pixels of the region in the input buffer + * @param height Height in pixels of the region in the input buffer + * @param dst Pointer to the output buffer + * @param dst_line_stride Length in bytes of a raster line of the output buffer + * + * @return Standard OPL error code. See enumeration for possible result codes. + */ +int opl_rotate270_u16(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride); + +/*! + * @brief Mirror a 16bpp buffer horizontally + * + * @param src Pointer to the input buffer + * @param src_line_stride Length in bytes of a raster line of the input buffer + * @param width Width in pixels of the region in the input buffer + * @param height Height in pixels of the region in the input buffer + * @param dst Pointer to the output buffer + * @param dst_line_stride Length in bytes of a raster line of the output buffer + * + * @return Standard OPL error code. See enumeration for possible result codes. + */ +int opl_hmirror_u16(const u8 * src, int src_line_stride, int width, int height, + u8 * dst, int dst_line_stride); + +/*! + * @brief Mirror a 16bpp buffer vertically + * + * @param src Pointer to the input buffer + * @param src_line_stride Length in bytes of a raster line of the input buffer + * @param width Width in pixels of the region in the input buffer + * @param height Height in pixels of the region in the input buffer + * @param dst Pointer to the output buffer + * @param dst_line_stride Length in bytes of a raster line of the output buffer + * + * @return Standard OPL error code. See enumeration for possible result codes. + */ +int opl_vmirror_u16(const u8 * src, int src_line_stride, int width, int height, + u8 * dst, int dst_line_stride); + +/*! + * @brief Rotate a 16bbp buffer 90 degrees clockwise and mirror vertically + * It is equivalent to rotate 270 degree and mirror horizontally + * + * @param src Pointer to the input buffer + * @param src_line_stride Length in bytes of a raster line of the input buffer + * @param width Width in pixels of the region in the input buffer + * @param height Height in pixels of the region in the input buffer + * @param dst Pointer to the output buffer + * @param dst_line_stride Length in bytes of a raster line of the output buffer + * + * @return Standard OPL error code. See enumeration for possible result codes. + */ +int opl_rotate90_vmirror_u16(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride); + +/*! + * @brief Rotate a 16bbp buffer 270 degrees clockwise and mirror vertically + * It is equivalent to rotate 90 degree and mirror horizontally + * + * @param src Pointer to the input buffer + * @param src_line_stride Length in bytes of a raster line of the input buffer + * @param width Width in pixels of the region in the input buffer + * @param height Height in pixels of the region in the input buffer + * @param dst Pointer to the output buffer + * @param dst_line_stride Length in bytes of a raster line of the output buffer + * + * @return Standard OPL error code. See enumeration for possible result codes. + */ +int opl_rotate270_vmirror_u16(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride); + +#endif /* __OPL_H__ */ diff -urN linux-2.6.26/drivers/media/video/mxc/opl/opl_mod.c linux-2.6.26-lab126/drivers/media/video/mxc/opl/opl_mod.c --- linux-2.6.26/drivers/media/video/mxc/opl/opl_mod.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/opl/opl_mod.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,30 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include + +static __init int opl_init(void) +{ + return 0; +} + +static void __exit opl_exit(void) +{ +} + +module_init(opl_init); +module_exit(opl_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("OPL Software Rotation/Mirroring"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/media/video/mxc/opl/rotate270_u16.c linux-2.6.26-lab126/drivers/media/video/mxc/opl/rotate270_u16.c --- linux-2.6.26/drivers/media/video/mxc/opl/rotate270_u16.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/opl/rotate270_u16.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,285 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include "opl.h" + +static int opl_rotate270_u16_by16(const u8 * src, int src_line_stride, + int width, int height, u8 * dst, + int dst_line_stride, int vmirror); +static int opl_rotate270_u16_by4(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride, + int vmirror); +static int opl_rotate270_vmirror_u16_both(const u8 * src, int src_line_stride, + int width, int height, u8 * dst, + int dst_line_stride, int vmirror); +int opl_rotate270_u16_qcif(const u8 * src, u8 * dst); + +int opl_rotate270_u16(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride) +{ + return opl_rotate270_vmirror_u16_both(src, src_line_stride, width, + height, dst, dst_line_stride, 0); +} + +int opl_rotate270_vmirror_u16(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride) +{ + return opl_rotate270_vmirror_u16_both(src, src_line_stride, width, + height, dst, dst_line_stride, 1); +} + +static int opl_rotate270_vmirror_u16_both(const u8 * src, int src_line_stride, + int width, int height, u8 * dst, + int dst_line_stride, int vmirror) +{ + const int BLOCK_SIZE_PIXELS = CACHE_LINE_WORDS * BYTES_PER_WORD + / BYTES_PER_PIXEL; + const int BLOCK_SIZE_PIXELS_BY4 = CACHE_LINE_WORDS * BYTES_PER_WORD + / BYTES_PER_PIXEL / 4; + + if (!src || !dst) + return OPLERR_NULL_PTR; + + if (width == 0 || height == 0 || src_line_stride == 0 + || dst_line_stride == 0) + return OPLERR_BAD_ARG; + + /* The QCIF algorithm doesn't support vertical mirroring */ + if (vmirror == 0 && width == QCIF_Y_WIDTH && height == QCIF_Y_HEIGHT + && src_line_stride == QCIF_Y_WIDTH * 2 + && src_line_stride == QCIF_Y_HEIGHT * 2) + return opl_rotate270_u16_qcif(src, dst); + else if (width % BLOCK_SIZE_PIXELS == 0 + && height % BLOCK_SIZE_PIXELS == 0) + return opl_rotate270_u16_by16(src, src_line_stride, width, + height, dst, dst_line_stride, + vmirror); + else if (width % BLOCK_SIZE_PIXELS_BY4 == 0 + && height % BLOCK_SIZE_PIXELS_BY4 == 0) + return opl_rotate270_u16_by4(src, src_line_stride, width, + height, dst, dst_line_stride, + vmirror); + else + return OPLERR_BAD_ARG; +} + +/* + * Rotate Counter Clockwise, divide RGB component into 16 row strips, read + * non sequentially and write sequentially. This is done in 16 line strips + * so that the cache is used better. Cachelines are 8 words = 32 bytes. Pixels + * are 2 bytes. The 16 reads will be cache misses, but the next 240 should + * be from cache. The writes to the output buffer will be sequential for 16 + * writes. + * + * Example: + * Input data matrix: output matrix + * + * 0 | 1 | 2 | 3 | 4 | 4 | 0 | 0 | 3 | + * 4 | 3 | 2 | 1 | 0 | 3 | 1 | 9 | 6 | + * 6 | 7 | 8 | 9 | 0 | 2 | 2 | 8 | 2 | + * 5 | 3 | 2 | 6 | 3 | 1 | 3 | 7 | 3 | + * ^ 0 | 4 | 6 | 5 | < Write the input data sequentially + * Read first column + * Start at the bottom + * Move to next column and repeat + * + * Loop over k decreasing (blocks) + * in_block_ptr = src + (((RGB_HEIGHT_PIXELS / BLOCK_SIZE_PIXELS) - k) + * * BLOCK_SIZE_PIXELS) * (RGB_WIDTH_BYTES) + * out_block_ptr = dst + (((RGB_HEIGHT_PIXELS / BLOCK_SIZE_PIXELS) - k) + * * BLOCK_SIZE_BYTES) + (RGB_WIDTH_PIXELS - 1) + * * RGB_HEIGHT_PIXELS * BYTES_PER_PIXEL + * + * Loop over i decreasing (width) + * Each pix: + * in_block_ptr += RGB_WIDTH_BYTES + * out_block_ptr += 4 + * + * Each row of block: + * in_block_ptr -= RGB_WIDTH_BYTES * BLOCK_SIZE_PIXELS - 2 + * out_block_ptr -= RGB_HEIGHT_PIXELS * BYTES_PER_PIXEL + 2 * BLOCK_SIZE_PIXELS; + * + * It may perform vertical mirroring too depending on the vmirror flag. + */ +static int opl_rotate270_u16_by16(const u8 * src, int src_line_stride, + int width, int height, u8 * dst, + int dst_line_stride, int vmirror) +{ + const int BLOCK_SIZE_PIXELS = CACHE_LINE_WORDS * BYTES_PER_WORD + / BYTES_PER_PIXEL; + const int IN_INDEX = src_line_stride * BLOCK_SIZE_PIXELS + - BYTES_PER_PIXEL; + const int OUT_INDEX = vmirror ? + -dst_line_stride + BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS + : dst_line_stride + BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS; + const u8 *in_block_ptr; + u8 *out_block_ptr; + int i, k; + + for (k = height / BLOCK_SIZE_PIXELS; k > 0; k--) { + in_block_ptr = src + (((height / BLOCK_SIZE_PIXELS) - k) + * BLOCK_SIZE_PIXELS) * src_line_stride; + out_block_ptr = dst + (((height / BLOCK_SIZE_PIXELS) - k) + * BLOCK_SIZE_PIXELS * BYTES_PER_PIXEL) + + (width - 1) * dst_line_stride; + + /* + * For vertical mirroring the writing starts from the + * first line + */ + if (vmirror) + out_block_ptr -= dst_line_stride * (width - 1); + + for (i = width; i > 0; i--) { + __asm__ volatile ( + "ldrh r2, [%0], %4\n\t" + "ldrh r3, [%0], %4\n\t" + "ldrh r4, [%0], %4\n\t" + "ldrh r5, [%0], %4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + "ldrh r2, [%0], %4\n\t" + "ldrh r3, [%0], %4\n\t" + "ldrh r4, [%0], %4\n\t" + "ldrh r5, [%0], %4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + "ldrh r2, [%0], %4\n\t" + "ldrh r3, [%0], %4\n\t" + "ldrh r4, [%0], %4\n\t" + "ldrh r5, [%0], %4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + "ldrh r2, [%0], %4\n\t" + "ldrh r3, [%0], %4\n\t" + "ldrh r4, [%0], %4\n\t" + "ldrh r5, [%0], %4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + :"+r" (in_block_ptr), "+r"(out_block_ptr) /* output */ + :"0"(in_block_ptr), "1"(out_block_ptr), "r"(src_line_stride) /* input */ + :"r2", "r3", "r4", "r5", "memory" /* modify */ + ); + in_block_ptr -= IN_INDEX; + out_block_ptr -= OUT_INDEX; + } + } + + return OPLERR_SUCCESS; +} + +/* + * Rotate Counter Clockwise, divide RGB component into 4 row strips, read + * non sequentially and write sequentially. This is done in 4 line strips + * so that the cache is used better. Cachelines are 8 words = 32 bytes. Pixels + * are 2 bytes. The 4 reads will be cache misses, but the next 60 should + * be from cache. The writes to the output buffer will be sequential for 4 + * writes. + * + * Example: + * Input data matrix: output matrix + * + * 0 | 1 | 2 | 3 | 4 | 4 | 0 | 0 | 3 | + * 4 | 3 | 2 | 1 | 0 | 3 | 1 | 9 | 6 | + * 6 | 7 | 8 | 9 | 0 | 2 | 2 | 8 | 2 | + * 5 | 3 | 2 | 6 | 3 | 1 | 3 | 7 | 3 | + * ^ 0 | 4 | 6 | 5 | < Write the input data sequentially + * Read first column + * Start at the bottom + * Move to next column and repeat + * + * Loop over k decreasing (blocks) + * in_block_ptr = src + (((RGB_HEIGHT_PIXELS / BLOCK_SIZE_PIXELS) - k) + * * BLOCK_SIZE_PIXELS) * (RGB_WIDTH_BYTES) + * out_block_ptr = dst + (((RGB_HEIGHT_PIXELS / BLOCK_SIZE_PIXELS) - k) + * * BLOCK_SIZE_BYTES) + (RGB_WIDTH_PIXELS - 1) + * * RGB_HEIGHT_PIXELS * BYTES_PER_PIXEL + * + * Loop over i decreasing (width) + * Each pix: + * in_block_ptr += RGB_WIDTH_BYTES + * out_block_ptr += 4 + * + * Each row of block: + * in_block_ptr -= RGB_WIDTH_BYTES * BLOCK_SIZE_PIXELS - 2 + * out_block_ptr -= RGB_HEIGHT_PIXELS * BYTES_PER_PIXEL + 2 * BLOCK_SIZE_PIXELS; + * + * It may perform vertical mirroring too depending on the vmirror flag. + */ +static int opl_rotate270_u16_by4(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride, + int vmirror) +{ + const int BLOCK_SIZE_PIXELS = CACHE_LINE_WORDS * BYTES_PER_WORD + / BYTES_PER_PIXEL / 4; + const int IN_INDEX = src_line_stride * BLOCK_SIZE_PIXELS + - BYTES_PER_PIXEL; + const int OUT_INDEX = vmirror ? + -dst_line_stride + BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS + : dst_line_stride + BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS; + const u8 *in_block_ptr; + u8 *out_block_ptr; + int i, k; + + for (k = height / BLOCK_SIZE_PIXELS; k > 0; k--) { + in_block_ptr = src + (((height / BLOCK_SIZE_PIXELS) - k) + * BLOCK_SIZE_PIXELS) * src_line_stride; + out_block_ptr = dst + (((height / BLOCK_SIZE_PIXELS) - k) + * BLOCK_SIZE_PIXELS * BYTES_PER_PIXEL) + + (width - 1) * dst_line_stride; + + /* + * For vertical mirroring the writing starts from the + * first line + */ + if (vmirror) + out_block_ptr -= dst_line_stride * (width - 1); + + for (i = width; i > 0; i--) { + __asm__ volatile ( + "ldrh r2, [%0], %4\n\t" + "ldrh r3, [%0], %4\n\t" + "ldrh r4, [%0], %4\n\t" + "ldrh r5, [%0], %4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + :"+r" (in_block_ptr), "+r"(out_block_ptr) /* output */ + :"0"(in_block_ptr), "1"(out_block_ptr), "r"(src_line_stride) /* input */ + :"r2", "r3", "r4", "r5", "memory" /* modify */ + ); + in_block_ptr -= IN_INDEX; + out_block_ptr -= OUT_INDEX; + } + } + + return OPLERR_SUCCESS; +} + +EXPORT_SYMBOL(opl_rotate270_u16); +EXPORT_SYMBOL(opl_rotate270_vmirror_u16); diff -urN linux-2.6.26/drivers/media/video/mxc/opl/rotate270_u16_qcif.S linux-2.6.26-lab126/drivers/media/video/mxc/opl/rotate270_u16_qcif.S --- linux-2.6.26/drivers/media/video/mxc/opl/rotate270_u16_qcif.S 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/opl/rotate270_u16_qcif.S 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,70 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include + + .text + .align 2 +ENTRY(opl_rotate270_u16_qcif) + STMFD sp!,{r4-r10} + MOV r12,#0x160 + MOV r10,#0x90 + MOV r3,r10,LSR #4 +.L1.16: + RSB r2,r3,r10,LSR #4 + MOV r5,r2,LSL #5 + MOV r4,r12,LSR #1 + SMULBB r4,r5,r4 + ADD r2,r1,r2,LSL #5 + ADD r5,r2,#0xc000 + ADD r5,r5,#0x4e0 + MOV r2,r12,LSR #1 + ADD r4,r0,r4 +.L1.52: + LDRH r6,[r4],r12 + LDRH r7,[r4],r12 + LDRH r8,[r4],r12 + LDRH r9,[r4],r12 + ORR r6,r6,r7,LSL #16 + ORR r7,r8,r9,LSL #16 + STMIA r5!,{r6,r7} + SUBS r2,r2,#1 + LDRH r6,[r4],r12 + LDRH r7,[r4],r12 + LDRH r8,[r4],r12 + LDRH r9,[r4],r12 + ORR r6,r6,r7,LSL #16 + ORR r7,r8,r9,LSL #16 + STMIA r5!,{r6,r7} + LDRH r6,[r4],r12 + LDRH r7,[r4],r12 + LDRH r8,[r4],r12 + LDRH r9,[r4],r12 + ORR r6,r6,r7,LSL #16 + ORR r7,r8,r9,LSL #16 + STMIA r5!,{r6,r7} + LDRH r6,[r4],r12 + LDRH r7,[r4],r12 + LDRH r8,[r4],r12 + LDRH r9,[r4],r12 + ORR r6,r6,r7,LSL #16 + ORR r7,r8,r9,LSL #16 + SUB r4,r4,#0x1500 + STMIA r5,{r6,r7} + SUB r5,r5,#0x138 + SUB r4,r4,#0xfe + BGT .L1.52 + SUBS r3,r3,#1 + BGT .L1.16 + LDMFD sp!,{r4-r10} + BX lr + .size opl_rotate270_u16_qcif, . - opl_rotate270_u16_qcif diff -urN linux-2.6.26/drivers/media/video/mxc/opl/rotate90_u16.c linux-2.6.26-lab126/drivers/media/video/mxc/opl/rotate90_u16.c --- linux-2.6.26/drivers/media/video/mxc/opl/rotate90_u16.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/opl/rotate90_u16.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,220 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include "opl.h" + +static int opl_rotate90_u16_by16(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride, + int vmirror); +static int opl_rotate90_u16_by4(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride, + int vmirror); +static int opl_rotate90_vmirror_u16_both(const u8 * src, int src_line_stride, + int width, int height, u8 * dst, + int dst_line_stride, int vmirror); +int opl_rotate90_u16_qcif(const u8 * src, u8 * dst); + +int opl_rotate90_u16(const u8 * src, int src_line_stride, int width, int height, + u8 * dst, int dst_line_stride) +{ + return opl_rotate90_vmirror_u16_both(src, src_line_stride, width, + height, dst, dst_line_stride, 0); +} + +int opl_rotate90_vmirror_u16(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride) +{ + return opl_rotate90_vmirror_u16_both(src, src_line_stride, width, + height, dst, dst_line_stride, 1); +} + +static int opl_rotate90_vmirror_u16_both(const u8 * src, int src_line_stride, + int width, int height, u8 * dst, + int dst_line_stride, int vmirror) +{ + const int BLOCK_SIZE_PIXELS = CACHE_LINE_WORDS * BYTES_PER_WORD + / BYTES_PER_PIXEL; + const int BLOCK_SIZE_PIXELS_BY4 = CACHE_LINE_WORDS * BYTES_PER_WORD + / BYTES_PER_PIXEL / 4; + + if (!src || !dst) + return OPLERR_NULL_PTR; + + if (width == 0 || height == 0 || src_line_stride == 0 + || dst_line_stride == 0) + return OPLERR_BAD_ARG; + + /* The QCIF algorithm doesn't support vertical mirroring */ + if (vmirror == 0 && width == QCIF_Y_WIDTH && height == QCIF_Y_HEIGHT + && src_line_stride == QCIF_Y_WIDTH * 2 + && src_line_stride == QCIF_Y_HEIGHT * 2) + return opl_rotate90_u16_qcif(src, dst); + else if (width % BLOCK_SIZE_PIXELS == 0 + && height % BLOCK_SIZE_PIXELS == 0) + return opl_rotate90_u16_by16(src, src_line_stride, width, + height, dst, dst_line_stride, + vmirror); + else if (width % BLOCK_SIZE_PIXELS_BY4 == 0 + && height % BLOCK_SIZE_PIXELS_BY4 == 0) + return opl_rotate90_u16_by4(src, src_line_stride, width, height, + dst, dst_line_stride, vmirror); + else + return OPLERR_BAD_ARG; +} + +/* + * Performs clockwise rotation (and possibly vertical mirroring depending + * on the vmirror flag) using block sizes of 16x16 + * The algorithm is similar to 270 degree clockwise rotation algorithm + */ +static int opl_rotate90_u16_by16(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride, + int vmirror) +{ + const int BLOCK_SIZE_PIXELS = CACHE_LINE_WORDS * BYTES_PER_WORD + / BYTES_PER_PIXEL; + const int BLOCK_SIZE_BYTES = BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS; + const int IN_INDEX = src_line_stride * BLOCK_SIZE_PIXELS + + BYTES_PER_PIXEL; + const int OUT_INDEX = vmirror ? + -dst_line_stride - BLOCK_SIZE_BYTES + : dst_line_stride - BLOCK_SIZE_BYTES; + const u8 *in_block_ptr; + u8 *out_block_ptr; + int i, k; + + for (k = height / BLOCK_SIZE_PIXELS; k > 0; k--) { + in_block_ptr = src + src_line_stride * (height - 1) + - (src_line_stride * BLOCK_SIZE_PIXELS * + (height / BLOCK_SIZE_PIXELS - k)); + out_block_ptr = dst + BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS * + ((height / BLOCK_SIZE_PIXELS) - k); + + /* + * For vertical mirroring the writing starts from the + * bottom line + */ + if (vmirror) + out_block_ptr += dst_line_stride * (width - 1); + + for (i = width; i > 0; i--) { + __asm__ volatile ( + "ldrh r2, [%0], -%4\n\t" + "ldrh r3, [%0], -%4\n\t" + "ldrh r4, [%0], -%4\n\t" + "ldrh r5, [%0], -%4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + "ldrh r2, [%0], -%4\n\t" + "ldrh r3, [%0], -%4\n\t" + "ldrh r4, [%0], -%4\n\t" + "ldrh r5, [%0], -%4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + "ldrh r2, [%0], -%4\n\t" + "ldrh r3, [%0], -%4\n\t" + "ldrh r4, [%0], -%4\n\t" + "ldrh r5, [%0], -%4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + "ldrh r2, [%0], -%4\n\t" + "ldrh r3, [%0], -%4\n\t" + "ldrh r4, [%0], -%4\n\t" + "ldrh r5, [%0], -%4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + :"+r" (in_block_ptr), "+r"(out_block_ptr) /* output */ + :"0"(in_block_ptr), "1"(out_block_ptr), "r"(src_line_stride) /* input */ + :"r2", "r3", "r4", "r5", "memory" /* modify */ + ); + in_block_ptr += IN_INDEX; + out_block_ptr += OUT_INDEX; + } + } + + return OPLERR_SUCCESS; +} + +/* + * Performs clockwise rotation (and possibly vertical mirroring depending + * on the vmirror flag) using block sizes of 4x4 + * The algorithm is similar to 270 degree clockwise rotation algorithm + */ +static int opl_rotate90_u16_by4(const u8 * src, int src_line_stride, int width, + int height, u8 * dst, int dst_line_stride, + int vmirror) +{ + const int BLOCK_SIZE_PIXELS = CACHE_LINE_WORDS * BYTES_PER_WORD + / BYTES_PER_PIXEL / 4; + const int BLOCK_SIZE_BYTES = BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS; + const int IN_INDEX = src_line_stride * BLOCK_SIZE_PIXELS + + BYTES_PER_PIXEL; + const int OUT_INDEX = vmirror ? + -dst_line_stride - BLOCK_SIZE_BYTES + : dst_line_stride - BLOCK_SIZE_BYTES; + const u8 *in_block_ptr; + u8 *out_block_ptr; + int i, k; + + for (k = height / BLOCK_SIZE_PIXELS; k > 0; k--) { + in_block_ptr = src + src_line_stride * (height - 1) + - (src_line_stride * BLOCK_SIZE_PIXELS * + (height / BLOCK_SIZE_PIXELS - k)); + out_block_ptr = dst + BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS + * ((height / BLOCK_SIZE_PIXELS) - k); + + /* + * For horizontal mirroring the writing starts from the + * bottom line + */ + if (vmirror) + out_block_ptr += dst_line_stride * (width - 1); + + for (i = width; i > 0; i--) { + __asm__ volatile ( + "ldrh r2, [%0], -%4\n\t" + "ldrh r3, [%0], -%4\n\t" + "ldrh r4, [%0], -%4\n\t" + "ldrh r5, [%0], -%4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + :"+r" (in_block_ptr), "+r"(out_block_ptr) /* output */ + :"0"(in_block_ptr), "1"(out_block_ptr), "r"(src_line_stride) /* input */ + :"r2", "r3", "r4", "r5", "memory" /* modify */ + ); + in_block_ptr += IN_INDEX; + out_block_ptr += OUT_INDEX; + } + } + + return OPLERR_SUCCESS; +} + +EXPORT_SYMBOL(opl_rotate90_u16); +EXPORT_SYMBOL(opl_rotate90_vmirror_u16); diff -urN linux-2.6.26/drivers/media/video/mxc/opl/rotate90_u16_qcif.S linux-2.6.26-lab126/drivers/media/video/mxc/opl/rotate90_u16_qcif.S --- linux-2.6.26/drivers/media/video/mxc/opl/rotate90_u16_qcif.S 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/opl/rotate90_u16_qcif.S 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,71 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include + + .text + .align 2 +ENTRY(opl_rotate90_u16_qcif) + STMFD sp!,{r4-r10} + MOV r12,#0x160 + MOV r10,#0x90 + MOV r3,r10,LSR #4 +.L1.216: + RSB r2,r3,r10,LSR #4 + MOV r4,#0x20 + SMULBB r5,r4,r2 + MOV r4,#0x1600 + SMULBB r2,r4,r2 + ADD r4,r0,#0xc000 + ADD r4,r4,#0x4a0 + SUB r4,r4,r2 + MOV r2,r12,LSR #1 + ADD r5,r1,r5 +.L1.256: + LDRH r6,[r4],-r12 + LDRH r7,[r4],-r12 + LDRH r8,[r4],-r12 + LDRH r9,[r4],-r12 + ORR r6,r6,r7,LSL #16 + ORR r7,r8,r9,LSL #16 + STMIA r5!,{r6,r7} + SUBS r2,r2,#1 + LDRH r6,[r4],-r12 + LDRH r7,[r4],-r12 + LDRH r8,[r4],-r12 + LDRH r9,[r4],-r12 + ORR r6,r6,r7,LSL #16 + ORR r7,r8,r9,LSL #16 + STMIA r5!,{r6,r7} + LDRH r6,[r4],-r12 + LDRH r7,[r4],-r12 + LDRH r8,[r4],-r12 + LDRH r9,[r4],-r12 + ORR r6,r6,r7,LSL #16 + ORR r7,r8,r9,LSL #16 + STMIA r5!,{r6,r7} + LDRH r6,[r4],-r12 + LDRH r7,[r4],-r12 + LDRH r8,[r4],-r12 + LDRH r9,[r4],-r12 + ORR r6,r6,r7,LSL #16 + ORR r7,r8,r9,LSL #16 + ADD r4,r4,#0x1600 + STMIA r5!,{r6,r7} + ADD r5,r5,#0x100 + ADD r4,r4,#2 + BGT .L1.256 + SUBS r3,r3,#1 + BGT .L1.216 + LDMFD sp!,{r4-r10} + BX lr + .size opl_rotate90_u16_qcif, . - opl_rotate90_u16_qcif diff -urN linux-2.6.26/drivers/media/video/mxc/opl/vmirror_u16.c linux-2.6.26-lab126/drivers/media/video/mxc/opl/vmirror_u16.c --- linux-2.6.26/drivers/media/video/mxc/opl/vmirror_u16.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/opl/vmirror_u16.c 2010-08-10 04:15:22.000000000 -0400 @@ -0,0 +1,46 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include "opl.h" + +int opl_vmirror_u16(const u8 * src, int src_line_stride, int width, int height, + u8 * dst, int dst_line_stride) +{ + const u8 *src_row_addr; + u8 *dst_row_addr; + int i; + + if (!src || !dst) + return OPLERR_NULL_PTR; + + if (width == 0 || height == 0 || src_line_stride == 0 + || dst_line_stride == 0) + return OPLERR_BAD_ARG; + + src_row_addr = src; + dst_row_addr = dst + (height - 1) * dst_line_stride; + + /* Loop over all rows */ + for (i = 0; i < height; i++) { + /* memcpy each row */ + memcpy(dst_row_addr, src_row_addr, BYTES_PER_PIXEL * width); + src_row_addr += src_line_stride; + dst_row_addr -= dst_line_stride; + } + + return OPLERR_SUCCESS; +} + +EXPORT_SYMBOL(opl_vmirror_u16); diff -urN linux-2.6.26/drivers/media/video/mxc/output/Kconfig linux-2.6.26-lab126/drivers/media/video/mxc/output/Kconfig --- linux-2.6.26/drivers/media/video/mxc/output/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/output/Kconfig 2010-08-10 04:15:21.000000000 -0400 @@ -0,0 +1,28 @@ +config VIDEO_MXC_IPU_OUTPUT + bool "IPU v4l2 support" + depends on VIDEO_MXC_OUTPUT && MXC_IPU + default y + ---help--- + This is the video4linux2 driver for IPU post processing video output. + +config VIDEO_MXC_IPUV1_WVGA_OUTPUT + bool "IPUv1 WVGA v4l2 display support" + depends on VIDEO_MXC_OUTPUT && MXC_IPU + default n + ---help--- + This is the video4linux2 driver for IPUv1 WVGA post processing video output. + +config VIDEO_MXC_EMMA_OUTPUT + bool + depends on VIDEO_MXC_OUTPUT && MXC_EMMA && FB_MXC_SYNC_PANEL + default y + ---help--- + This is the video4linux2 driver for EMMA post processing video output. + +config VIDEO_MXC_OUTPUT_FBSYNC + bool "Synchronize the output with LCDC refresh" + depends on VIDEO_MXC_EMMA_OUTPUT + default y + ---help--- + Synchronize the post-processing with LCDC EOF (End of Frame) to + prevent tearing issue. If unsure, say Y. diff -urN linux-2.6.26/drivers/media/video/mxc/output/Makefile linux-2.6.26-lab126/drivers/media/video/mxc/output/Makefile --- linux-2.6.26/drivers/media/video/mxc/output/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/output/Makefile 2010-08-10 04:15:21.000000000 -0400 @@ -0,0 +1,11 @@ +ifeq ($(CONFIG_VIDEO_MXC_EMMA_OUTPUT),y) + mx27_output-objs := mx27_v4l2_output.o mx27_pp.o + obj-$(CONFIG_VIDEO_MXC_OUTPUT) += mx27_output.o +endif + +ifeq ($(CONFIG_VIDEO_MXC_IPU_OUTPUT),y) + obj-$(CONFIG_VIDEO_MXC_OUTPUT) += mxc_v4l2_output.o +endif +ifeq ($(CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT),y) + obj-$(CONFIG_VIDEO_MXC_OUTPUT) += mx31_v4l2_wvga_output.o +endif diff -urN linux-2.6.26/drivers/media/video/mxc/output/mx27_pp.c linux-2.6.26-lab126/drivers/media/video/mxc/output/mx27_pp.c --- linux-2.6.26/drivers/media/video/mxc/output/mx27_pp.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/output/mx27_pp.c 2010-08-10 04:15:21.000000000 -0400 @@ -0,0 +1,904 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mx27_pp.c + * + * @brief MX27 V4L2 Video Output Driver + * + * Video4Linux2 Output Device using MX27 eMMA Post-processing functionality. + * + * @ingroup MXC_V4L2_OUTPUT + */ +#include +#include +#include +#include +#include +#include +#include + +#include "mx27_pp.h" +#include "mxc_v4l2_output.h" + +#define SCALE_RETRY 32 /* to be more relax, less precise */ +#define PP_SKIP 1 +#define PP_TBL_MAX 40 + +static unsigned short scale_tbl[PP_TBL_MAX]; +static int g_hlen, g_vlen; + +static emma_pp_cfg g_pp_cfg; +static int g_disp_num = 0; +static char pp_dev[] = "emma_pp"; + +/*! + * @brief PP resizing routines + */ +static int gcd(int x, int y); +static int ratio(int x, int y, int *den); +static int scale_0d(int k, int coeff, int base, int nxt); +static int scale_1d(int inv, int outv, int k); +static int scale_1d_smart(int *inv, int *outv, int index); +static int scale_2d(emma_pp_scale * sz); + +static irqreturn_t pp_isr(int irq, void *dev_id); +static int set_output_addr(emma_pp_cfg * cfg, vout_data * vout); +static int pphw_reset(void); +static int pphw_enable(int flag); +static int pphw_ptr(emma_pp_cfg * cfg); +static int pphw_outptr(emma_pp_cfg * cfg); +static int pphw_cfg(emma_pp_cfg * cfg); +static int pphw_isr(void); +static void pphw_init(void); +static void pphw_exit(void); + +#define PP_DUMP(reg) pr_debug("%s\t = 0x%08X\n", #reg, __raw_readl(reg)) +void pp_dump(void) +{ + PP_DUMP(PP_CNTL); + PP_DUMP(PP_INTRCNTL); + PP_DUMP(PP_INTRSTATUS); + PP_DUMP(PP_SOURCE_Y_PTR); + PP_DUMP(PP_SOURCE_CB_PTR); + PP_DUMP(PP_SOURCE_CR_PTR); + PP_DUMP(PP_DEST_RGB_PTR); + PP_DUMP(PP_QUANTIZER_PTR); + PP_DUMP(PP_PROCESS_FRAME_PARA); + PP_DUMP(PP_SOURCE_FRAME_WIDTH); + PP_DUMP(PP_DEST_DISPLAY_WIDTH); + PP_DUMP(PP_DEST_IMAGE_SIZE); + PP_DUMP(PP_DEST_FRAME_FMT_CNTL); + PP_DUMP(PP_RESIZE_INDEX); + PP_DUMP(PP_CSC_COEF_0123); + PP_DUMP(PP_CSC_COEF_4); +} + +/*! + * @brief Set PP input address. + * @param ptr The pointer to the Y value of input + * @return Zero on success, others on failure + */ +int pp_ptr(unsigned long ptr) +{ + g_pp_cfg.ptr.y = ptr; + g_pp_cfg.ptr.u = g_pp_cfg.ptr.v = g_pp_cfg.ptr.qp = 0; + + return pphw_ptr(&g_pp_cfg); +} + +/*! + * @brief Enable or disable PP. + * @param flag Zero to disable PP, others to enable PP + * @return Zero on success, others on failure + */ +int pp_enable(int flag) +{ + return pphw_enable(flag); +} + +/*! + * @brief Get the display No. of last completed PP frame. + * @return The display No. of last completed PP frame. + */ +int pp_num_last(void) +{ + return (g_disp_num ? 0 : 1); +} + +/*! + * @brief Initialize PP. + * @param vout Pointer to _vout_data structure + * @return Zero on success, others on failure + */ +int pp_init(vout_data * vout) +{ + pphw_init(); + pphw_enable(0); + enable_irq(MXC_INT_EMMAPP); + return request_irq(MXC_INT_EMMAPP, pp_isr, 0, pp_dev, vout); +} + +/*! + * @brief Deinitialize PP. + * @param vout Pointer to _vout_data structure + */ +void pp_exit(vout_data * vout) +{ + disable_irq(MXC_INT_EMMAPP); + free_irq(MXC_INT_EMMAPP, vout); + pphw_enable(0); + pphw_exit(); +} + +/*! + * @brief Configure PP. + * @param vout Pointer to _vout_data structure + * @return Zero on success, others on failure + */ +int pp_cfg(vout_data * vout) +{ + if (!vout) + return -1; + + /* PP accepts YUV420 input only */ + if (vout->v2f.fmt.pix.pixelformat != V4L2_PIX_FMT_YUV420) { + pr_debug("unsupported pixel format.\n"); + return -1; + } + + g_pp_cfg.operation = 0; + + memset(g_pp_cfg.csc_table, 0, sizeof(g_pp_cfg.csc_table)); + + /* Convert output pixel format to PP required format */ + switch (vout->v4l2_fb.fmt.pixelformat) { + case V4L2_PIX_FMT_BGR32: + g_pp_cfg.red_width = 8; + g_pp_cfg.green_width = 8; + g_pp_cfg.blue_width = 8; + g_pp_cfg.red_offset = 8; + g_pp_cfg.green_offset = 16; + g_pp_cfg.blue_offset = 24; + g_pp_cfg.rgb_resolution = 32; + break; + case V4L2_PIX_FMT_RGB32: + g_pp_cfg.red_width = 8; + g_pp_cfg.green_width = 8; + g_pp_cfg.blue_width = 8; + g_pp_cfg.red_offset = 24; + g_pp_cfg.green_offset = 16; + g_pp_cfg.blue_offset = 8; + g_pp_cfg.rgb_resolution = 32; + break; + case V4L2_PIX_FMT_YUYV: + g_pp_cfg.red_width = 0; + g_pp_cfg.green_width = 0; + g_pp_cfg.blue_width = 0; + g_pp_cfg.red_offset = 0; + g_pp_cfg.green_offset = 0; + g_pp_cfg.blue_offset = PP_PIX_YUYV; + g_pp_cfg.rgb_resolution = 16; + break; + case V4L2_PIX_FMT_UYVY: + g_pp_cfg.red_width = 0; + g_pp_cfg.green_width = 0; + g_pp_cfg.blue_width = 0; + g_pp_cfg.red_offset = 0; + g_pp_cfg.green_offset = 0; + g_pp_cfg.blue_offset = PP_PIX_UYVY; + g_pp_cfg.rgb_resolution = 16; + break; + case V4L2_PIX_FMT_RGB565: + default: + g_pp_cfg.red_width = 5; + g_pp_cfg.green_width = 6; + g_pp_cfg.blue_width = 5; + g_pp_cfg.red_offset = 11; + g_pp_cfg.green_offset = 5; + g_pp_cfg.blue_offset = 0; + g_pp_cfg.rgb_resolution = 16; + break; + } + + if (vout->ipu_buf[0] != -1) + g_pp_cfg.ptr.y = + (unsigned int)vout->queue_buf_paddr[vout->ipu_buf[0]]; + else + g_pp_cfg.ptr.y = 0; + + g_pp_cfg.ptr.u = g_pp_cfg.ptr.v = g_pp_cfg.ptr.qp = 0; + + g_pp_cfg.dim.in.width = vout->v2f.fmt.pix.width; + g_pp_cfg.dim.in.height = vout->v2f.fmt.pix.height; + g_pp_cfg.dim.out.width = vout->crop_current.width; + g_pp_cfg.dim.out.height = vout->crop_current.height; + g_pp_cfg.dim.num.width = 0; + g_pp_cfg.dim.num.height = 0; + g_pp_cfg.dim.den.width = 0; + g_pp_cfg.dim.den.height = 0; + + if (scale_2d(&g_pp_cfg.dim)) { + pr_debug("unsupported resize ratio.\n"); + return -1; + } + + g_pp_cfg.dim.out.width = vout->crop_current.width; + g_pp_cfg.dim.out.height = vout->crop_current.height; + + g_pp_cfg.in_y_stride = 0; + if (set_output_addr(&g_pp_cfg, vout)) { + pr_debug("failed to set pp output address.\n"); + return -1; + } + + return pphw_cfg(&g_pp_cfg); +} + +irqreturn_t mxc_v4l2out_pp_in_irq_handler(int irq, void *dev_id); + +/*! + * @brief PP IRQ handler. + */ +static irqreturn_t pp_isr(int irq, void *dev_id) +{ + int status; + vout_data *vout = dev_id; + + status = pphw_isr(); + if ((status & 0x1) == 0) { /* Not frame complete interrupt */ + pr_debug("not pp frame complete interrupt\n"); + return IRQ_HANDLED; + } + + if (vout->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) { + g_disp_num = g_disp_num ? 0 : 1; + g_pp_cfg.outptr = (unsigned int)vout->display_bufs[g_disp_num]; + pphw_outptr(&g_pp_cfg); + } + + return mxc_v4l2out_pp_in_irq_handler(irq, dev_id); +} + +/*! + * @brief Set PP output address. + * @param cfg Pointer to emma_pp_cfg structure + * @param vout Pointer to _vout_data structure + * @return Zero on success, others on failure + */ +static int set_output_addr(emma_pp_cfg * cfg, vout_data * vout) +{ + if (vout->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) { + g_disp_num = 0; + cfg->outptr = (unsigned int)vout->display_bufs[g_disp_num]; + cfg->out_stride = vout->crop_current.width; + return 0; + } else { + struct fb_info *fb; + + fb = registered_fb[vout->output_fb_num[vout->cur_disp_output]]; + if (!fb) + return -1; + + cfg->outptr = fb->fix.smem_start; + cfg->outptr += vout->crop_current.top * fb->var.xres_virtual + * (fb->var.bits_per_pixel >> 3) + + vout->crop_current.left * (fb->var.bits_per_pixel >> 3); + cfg->out_stride = fb->var.xres_virtual; + + return 0; + } +} + +/*! + * @brief Get maximum common divisor. + * @param x First input value + * @param y Second input value + * @return Maximum common divisor of x and y + */ +static int gcd(int x, int y) +{ + int k; + + if (x < y) { + k = x; + x = y; + y = k; + } + + while ((k = x % y)) { + x = y; + y = k; + } + + return y; +} + +/*! + * @brief Get ratio. + * @param x First input value + * @param y Second input value + * @param den Denominator of the ratio (corresponding to y) + * @return Numerator of the ratio (corresponding to x) + */ +static int ratio(int x, int y, int *den) +{ + int g; + + if (!x || !y) + return 0; + + g = gcd(x, y); + *den = y / g; + + return x / g; +} + +/*! + * @brief Build PP coefficient entry + * Build one or more coefficient entries for PP coefficient table based + * on given coefficient. + * + * @param k The index of the coefficient in coefficient table + * @param coeff The weighting coefficient + * @param base The base of the coefficient + * @param nxt Number of pixels to be read + * + * @return The index of the next coefficient entry on success + * -1 on failure + */ +static int scale_0d(int k, int coeff, int base, int nxt) +{ + if (k >= PP_TBL_MAX) { + /* no more space in table */ + pr_debug("no space in scale table, k = %d\n", k); + return -1; + } + + coeff = ((coeff << BC_COEF) + (base >> 1)) / base; + + /* + * Valid values for weighting coefficient are 0, 2 to 30, and 31. + * A value of 31 is treated as 32 and therefore 31 is an + * invalid co-efficient. + */ + if (coeff >= SZ_COEF - 1) + coeff--; + else if (coeff == 1) + coeff++; + coeff = coeff << BC_NXT; + + if (nxt < SZ_NXT) { + coeff |= nxt; + coeff <<= 1; + coeff |= 1; + } else { + /* + * src inc field is 2 bit wide, for 4+, use special + * code 0:0:1 to prevent dest inc + */ + coeff |= PP_SKIP; + coeff <<= 1; + coeff |= 1; + nxt -= PP_SKIP; + do { + pr_debug("tbl = %03X\n", coeff); + scale_tbl[k++] = coeff; + coeff = (nxt > PP_SKIP) ? PP_SKIP : nxt; + coeff <<= 1; + } while ((nxt -= PP_SKIP) > 0); + } + pr_debug("tbl = %03X\n", coeff); + scale_tbl[k++] = coeff; + + return k; +} + +/* + * @brief Build PP coefficient table + * Build PP coefficient table for one dimension (width or height) + * based on given input and output resolution + * + * @param inv input resolution + * @param outv output resolution + * @param k index of free table entry + * + * @return The index of the next free coefficient entry on success + * -1 on failure + */ +static int scale_1d(int inv, int outv, int k) +{ + int v; /* overflow counter */ + int coeff, nxt; /* table output */ + + if (inv == outv) + return scale_0d(k, 1, 1, 1); /* force scaling */ + + if (inv * 4 < outv) { + pr_debug("upscale err: ratio should be in range 1:1 to 1:4\n"); + return -1; + } + + v = 0; + if (inv < outv) { + /* upscale: mix <= 2 input pixels per output pixel */ + do { + coeff = outv - v; + v += inv; + if (v >= outv) { + v -= outv; + nxt = 1; + } else + nxt = 0; + pr_debug("upscale: coeff = %d/%d nxt = %d\n", coeff, + outv, nxt); + k = scale_0d(k, coeff, outv, nxt); + if (k < 0) + return -1; + } while (v); + } else if (inv >= 2 * outv) { + /* PP doesn't support resize ratio > 2:1 except 4:1. */ + if ((inv != 2 * outv) && (inv != 4 * outv)) + return -1; + /* downscale: >=2:1 bilinear approximation */ + coeff = inv - 2 * outv; + v = 0; + nxt = 0; + do { + v += coeff; + nxt = 2; + while (v >= outv) { + v -= outv; + nxt++; + } + pr_debug("downscale: coeff = 1/2 nxt = %d\n", nxt); + k = scale_0d(k, 1, 2, nxt); + if (k < 0) + return -1; + } while (v); + } else { + /* downscale: bilinear */ + int in_pos_inc = 2 * outv; + int out_pos = inv; + int out_pos_inc = 2 * inv; + int init_carry = inv - outv; + int carry = init_carry; + + v = outv + in_pos_inc; + do { + coeff = v - out_pos; + out_pos += out_pos_inc; + carry += out_pos_inc; + for (nxt = 0; v < out_pos; nxt++) { + v += in_pos_inc; + carry -= in_pos_inc; + } + pr_debug("downscale: coeff = %d/%d nxt = %d\n", coeff, + in_pos_inc, nxt); + k = scale_0d(k, coeff, in_pos_inc, nxt); + if (k < 0) + return -1; + } while (carry != init_carry); + } + return k; +} + +/* + * @brief Build PP coefficient table + * Build PP coefficient table for one dimension (width or height) + * based on given input and output resolution. The given input + * and output resolution might be not supported due to hardware + * limits. In this case this functin rounds the input and output + * to closest possible values and return them to caller. + * + * @param inv input resolution, might be modified after the call + * @param outv output resolution, might be modified after the call + * @param k index of free table entry + * + * @return The index of the next free coefficient entry on success + * -1 on failure + */ +static int scale_1d_smart(int *inv, int *outv, int index) +{ + int len, num, den, retry; + static int num1, den1; + + if (!inv || !outv) + return -1; + + /* Both should be non-zero */ + if (!(*inv) || !(*outv)) + return -1; + + retry = SCALE_RETRY; + + do { + num = ratio(*inv, *outv, &den); + pr_debug("num = %d, den = %d\n", num, den); + if (!num) + continue; + + if (index != 0) { + /* + * We are now resizing height. Check to see if the + * resize ratio for width can be reused by height + */ + if ((num == num1) && (den == den1)) + return index; + } + + if ((len = scale_1d(num, den, index)) < 0) + /* increase output dimension to try another ratio */ + (*outv)++; + else { + if (index == 0) { + /* + * We are now resizing width. The same resize + * ratio may be reused by height, so save the + * ratio. + */ + num1 = num; + den1 = den; + } + return len; + } + } while (retry--); + + pr_debug("pp scale err\n"); + return -1; +} + +/* + * @brief Build PP coefficient table for both width and height + * Build PP coefficient table for both width and height based on + * given resizing ratios. + * + * @param sz Structure contains resizing ratio informations + * + * @return 0 on success, others on failure + */ +static int scale_2d(emma_pp_scale * sz) +{ + int inv, outv; + + /* horizontal resizing. parameter check - must provide in size */ + if (!sz->in.width) + return -1; + + /* Resizing based on num:den */ + inv = sz->num.width; + outv = sz->den.width; + + if ((g_hlen = scale_1d_smart(&inv, &outv, 0)) > 0) { + /* Resizing succeeded */ + sz->den.width = outv; + sz->out.width = (sz->in.width * outv) / inv; + } else { + /* Resizing based on in:out */ + inv = sz->in.width; + outv = sz->out.width; + + if ((g_hlen = scale_1d_smart(&inv, &outv, 0)) > 0) { + /* Resizing succeeded */ + sz->out.width = outv; + sz->num.width = ratio(sz->in.width, sz->out.width, + &sz->den.width); + } else + return -1; + } + + sz->out.width &= ~1; + + /* vertical resizing. parameter check - must provide in size */ + if (!sz->in.height) + return -1; + + /* Resizing based on num:den */ + inv = sz->num.height; + outv = sz->den.height; + + if ((g_vlen = scale_1d_smart(&inv, &outv, g_hlen)) > 0) { + /* Resizing succeeded */ + sz->den.height = outv; + sz->out.height = (sz->in.height * outv) / inv; + } else { + /* Resizing based on in:out */ + inv = sz->in.height; + outv = sz->out.height; + + if ((g_vlen = scale_1d_smart(&inv, &outv, g_hlen)) > 0) { + /* Resizing succeeded */ + sz->out.height = outv; + sz->num.height = ratio(sz->in.height, sz->out.height, + &sz->den.height); + } else + return -1; + } + + return 0; +} + +/*! + * @brief Set PP resizing registers. + * @param sz Pointer to pp scaling structure + * @return Zero on success, others on failure + */ +static int pphw_scale(emma_pp_scale * sz) +{ + __raw_writel((sz->out.width << 16) | sz->out.height, + PP_DEST_IMAGE_SIZE); + __raw_writel(((g_hlen - 1) << 16) | (g_vlen == + g_hlen ? 0 : (g_hlen << 8)) | + (g_vlen - 1), PP_RESIZE_INDEX); + for (g_hlen = 0; g_hlen < g_vlen; g_hlen++) + __raw_writel(scale_tbl[g_hlen], + PP_RESIZE_COEF_TBL + g_hlen * 4); + + return 0; +} + +/*! + * @brief Reset PP. + * @return Zero on success, others on failure + */ +static int pphw_reset(void) +{ + int i; + + __raw_writel(0x100, PP_CNTL); + + /* timeout */ + for (i = 0; i < 1000; i++) { + if (!(__raw_readl(PP_CNTL) & 0x100)) { + pr_debug("pp reset over\n"); + break; + } + } + + /* check reset value */ + if (__raw_readl(PP_CNTL) != 0x876) { + pr_debug("pp reset value err = 0x%08X\n", __raw_readl(PP_CNTL)); + return -1; + } + + return 0; +} + +/*! + * @brief Enable or disable PP. + * @param flag Zero to disable PP, others to enable PP + * @return Zero on success, others on failure + */ +static int pphw_enable(int flag) +{ + int ret = 0; + + if (flag) + __raw_writel(__raw_readl(PP_CNTL) | 1, PP_CNTL); + else + ret = pphw_reset(); + + return ret; +} + +/*! + * @brief Set PP input address. + * @param cfg The pointer to PP configuration parameter + * @return Zero on success, others on failure + */ +static int pphw_ptr(emma_pp_cfg * cfg) +{ + if (!cfg->ptr.u) { + int size; + + /* yuv - packed */ + size = PP_CALC_Y_SIZE(cfg); + cfg->ptr.u = cfg->ptr.y + size; + cfg->ptr.v = cfg->ptr.u + (size >> 2); + + /* yuv packed with qp appended */ + if (!cfg->ptr.qp) + cfg->ptr.qp = cfg->ptr.v + (size >> 2); + } + __raw_writel(cfg->ptr.y, PP_SOURCE_Y_PTR); + __raw_writel(cfg->ptr.u, PP_SOURCE_CB_PTR); + __raw_writel(cfg->ptr.v, PP_SOURCE_CR_PTR); + __raw_writel(cfg->ptr.qp, PP_QUANTIZER_PTR); + + return 0; +} + +/*! + * @brief Set PP output address. + * @param cfg The pointer to PP configuration parameter + * @return Zero on success, others on failure + */ +static int pphw_outptr(emma_pp_cfg * cfg) +{ + __raw_writel(cfg->outptr, PP_DEST_RGB_PTR); + return 0; +} + +/*! + * @brief Configuration PP. + * @param cfg The pointer to PP configuration parameter + * @return Zero on success, others on failure + */ +static int pphw_cfg(emma_pp_cfg * cfg) +{ + int rt; + register int r; + + pphw_scale(&cfg->dim); + + if (!cfg->in_y_stride) + cfg->in_y_stride = cfg->dim.in.width; + + if (!cfg->out_stride) + cfg->out_stride = cfg->dim.out.width; + + r = __raw_readl(PP_CNTL) & ~EN_MASK; + + /* config parms */ + r |= cfg->operation & EN_MASK; + if (cfg->operation & EN_MACROBLOCK) { + /* Macroblock Mode */ + r |= 0x0200; + __raw_writel(0x06, PP_INTRCNTL); + } else { + /* Frame mode */ + __raw_writel(0x05, PP_INTRCNTL); + } + + if (cfg->red_width | cfg->green_width | cfg->blue_width) { + /* color conversion to be performed */ + r |= EN_CSC; + if (!(cfg->red_offset | cfg->green_offset)) { + /* auto offset B:G:R LSb to Msb */ + cfg->green_offset = cfg->blue_offset + cfg->blue_width; + cfg->red_offset = cfg->green_offset + cfg->green_width; + } + if (!cfg->rgb_resolution) { + /* derive minimum resolution required */ + int w, w2; + + w = cfg->red_offset + cfg->red_width; + w2 = cfg->blue_offset + cfg->blue_width; + if (w < w2) + w = w2; + w2 = cfg->green_offset + cfg->green_width; + if (w < w2) + w = w2; + if (w > 16) + w = 24; + else if (w > 8) + w = 16; + else + w = 8; + cfg->rgb_resolution = w; + } + /* 00,11 - 32 bpp, 10 - 16 bpp, 01 - 8 bpp */ + r &= ~0xC00; + if (cfg->rgb_resolution < 32) + r |= (cfg->rgb_resolution << 7); + __raw_writel((cfg->red_offset << 26) | + (cfg->green_offset << 21) | + (cfg->blue_offset << 16) | + (cfg->red_width << 8) | + (cfg->green_width << 4) | + cfg->blue_width, PP_DEST_FRAME_FMT_CNTL); + } else { + /* add YUV422 formatting */ + static const unsigned int _422[] = { + 0x62000888, + 0x60100888, + 0x43080888, + 0x41180888 + }; + + __raw_writel(_422[(cfg->blue_offset >> 3) & 3], + PP_DEST_FRAME_FMT_CNTL); + cfg->rgb_resolution = 16; + r &= ~0xC00; + r |= (cfg->rgb_resolution << 7); + } + + /* add csc formatting */ + if (!cfg->csc_table[1]) { + static const unsigned short _csc[][6] = { + {0x80, 0xb4, 0x2c, 0x5b, 0x0e4, 0}, + {0x95, 0xcc, 0x32, 0x68, 0x104, 1}, + {0x80, 0xca, 0x18, 0x3c, 0x0ec, 0}, + {0x95, 0xe5, 0x1b, 0x44, 0x10e, 1}, + }; + memcpy(cfg->csc_table, _csc[cfg->csc_table[0]], + sizeof(_csc[0])); + } + __raw_writel((cfg->csc_table[0] << 24) | + (cfg->csc_table[1] << 16) | + (cfg->csc_table[2] << 8) | + cfg->csc_table[3], PP_CSC_COEF_0123); + __raw_writel((cfg->csc_table[5] ? (1 << 9) : 0) | cfg->csc_table[4], + PP_CSC_COEF_4); + + __raw_writel(r, PP_CNTL); + + pphw_ptr(cfg); + pphw_outptr(cfg); + + /* + * #MB in a row = input_width / 16pix + * 1 byte per QP per MB + * QP must be formatted to be 4-byte aligned + * YUV lines are to be 4-byte aligned as well + * So Y is 8 byte aligned, as U = V = Y/2 for 420 + * MPEG MBs are 16x16 anyway + */ + __raw_writel((cfg->dim.in.width << 16) | cfg->dim.in.height, + PP_PROCESS_FRAME_PARA); + __raw_writel(cfg->in_y_stride | (PP_CALC_QP_WIDTH(cfg) << 16), + PP_SOURCE_FRAME_WIDTH); + + /* in bytes */ + rt = cfg->rgb_resolution >> 3; + if (rt == 3) + rt = 4; + __raw_writel(cfg->out_stride * rt, PP_DEST_DISPLAY_WIDTH); + + pp_dump(); + return 0; +} + +/*! + * @brief Check PP interrupt status. + * @return PP interrupt status + */ +static int pphw_isr(void) +{ + unsigned long status; + + pr_debug("pp: in isr.\n"); + status = __raw_readl(PP_INTRSTATUS) & 7; + if (!status) { + pr_debug("pp: not my isr err.\n"); + return status; + } + + if (status & 4) + pr_debug("pp: isr state error.\n"); + + /* clear interrupt status */ + __raw_writel(status, PP_INTRSTATUS); + + return status; +} + +static struct clk *emma_clk; + +/*! + * @brief PP module clock enable + */ +static void pphw_init(void) +{ + emma_clk = clk_get(NULL, "emma_clk"); + clk_enable(emma_clk); +} + +/*! + * @brief PP module clock disable + */ +static void pphw_exit(void) +{ + clk_disable(emma_clk); + clk_put(emma_clk); +} diff -urN linux-2.6.26/drivers/media/video/mxc/output/mx27_pp.h linux-2.6.26-lab126/drivers/media/video/mxc/output/mx27_pp.h --- linux-2.6.26/drivers/media/video/mxc/output/mx27_pp.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/output/mx27_pp.h 2010-08-10 04:15:21.000000000 -0400 @@ -0,0 +1,180 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mx27_pp.h + * + * @brief Header file for MX27 V4L2 Video Output Driver + * + * @ingroup MXC_V4L2_OUTPUT + */ +#ifndef __MX27_PP_H__ +#define __MX27_PP_H__ + +#include "mxc_v4l2_output.h" + +/* PP register definitions */ +#define PP_REG(ofs) (IO_ADDRESS(EMMA_BASE_ADDR) - 0x400 + ofs) + +/* Register offsets */ +#define PP_CNTL PP_REG(0x00) +#define PP_INTRCNTL PP_REG(0x04) +#define PP_INTRSTATUS PP_REG(0x08) +#define PP_SOURCE_Y_PTR PP_REG(0x0C) +#define PP_SOURCE_CB_PTR PP_REG(0x10) +#define PP_SOURCE_CR_PTR PP_REG(0x14) +#define PP_DEST_RGB_PTR PP_REG(0x18) +#define PP_QUANTIZER_PTR PP_REG(0x1C) +#define PP_PROCESS_FRAME_PARA PP_REG(0x20) +#define PP_SOURCE_FRAME_WIDTH PP_REG(0x24) +#define PP_DEST_DISPLAY_WIDTH PP_REG(0x28) +#define PP_DEST_IMAGE_SIZE PP_REG(0x2C) +#define PP_DEST_FRAME_FMT_CNTL PP_REG(0x30) +#define PP_RESIZE_INDEX PP_REG(0x34) +#define PP_CSC_COEF_0123 PP_REG(0x38) +#define PP_CSC_COEF_4 PP_REG(0x3C) +#define PP_RESIZE_COEF_TBL PP_REG(0x100) + +/* resize table dimensions + dest pixel index left/32 right/32 #src pixels to read + 0 [BC_COEF] [BC_COEF] [BC_NXT] + : + pp_tbl_max-1 +*/ +#define BC_NXT 2 +#define BC_COEF 5 +#define SZ_COEF (1 << BC_COEF) +#define SZ_NXT (1 << BC_NXT) + +/* PP operations */ +#define EN_DEBLOCK 0x02 +#define EN_DERING 0x04 +#define EN_CSC 0x10 +#define EN_MACROBLOCK 0x20 +#define EN_DEF 0x16 +#define EN_MASK 0x36 +#define EN_BIGDATA 0x1000 +#define EN_BIGQP 0x2000 + +/* PP CSC tables */ +#define CSC_TBL_NONE 0x80 +#define CSC_TBL_REUSE 0x81 +#define CSC_TBL_A1 0x00 +#define CSC_TBL_A0 0x20 +#define CSC_TBL_B1 0x40 +#define CSC_TBL_B0 0x60 +/* converts from 4 decimal fixed point to hw setting & vice versa */ +#define PP_CSC_FP4_2_HW(coeff) ((((coeff) << 7) + 5000) / 10000) +#define PP_CSC_HW_2_FP4(coeff) ((((coeff) * 10000) + 64) >> 7) + +#define PP_PIX_YUYV 0 +#define PP_PIX_YVYU 8 +#define PP_PIX_UYVY 16 +#define PP_PIX_VYUY 24 + +/* PP size & width calculation macros */ +#define PP_CALC_QP_WIDTH(cfg) \ + (!((cfg)->operation & (EN_DEBLOCK | EN_DERING)) ? 0 : \ + (((((cfg)->dim.in.width + 15) >> 4) + 3) & ~3)) +#define PP_CALC_Y_SIZE(cfg) \ + ((cfg)->in_y_stride * (cfg)->dim.in.height) +#define PP_CALC_CH_SIZE(cfg) (PP_CALC_Y_SIZE(cfg) >> 2) +#define PP_CALC_BPP(cfg) \ + ((cfg)->rgb_resolution > 16 ? 4 : ((cfg)->rgb_resolution >> 3)) +#define PP_CALC_YUV_SIZE(cfg) \ + ((PP_CALC_Y_SIZE(cfg) * 3) >> 1) +#define PP_CALC_QP_SIZE(cfg) \ + (PP_CALC_QP_WIDTH(cfg) * (((cfg)->dim.in.height + 15) >> 4)) +#define PP_CALC_DEST_WIDTH(cfg) \ + (((cfg)->out_stride & ~1) * PP_CALC_BPP(cfg)) +#define PP_CALC_DEST_SIZE(cfg) \ + ((cfg)->dim.out.height * PP_CALC_DEST_WIDTH(cfg)) + +/* + * physical addresses for bus mastering + * v=0 -> yuv packed + * v=0 & qp=0 -> yuv packed with qp appended + */ +typedef struct _emma_pp_ptr { + unsigned int y; /* Y data (line align8) */ + unsigned int u; /* U data (line align4) */ + unsigned int v; /* V data (line align4) */ + unsigned int qp; /* Quantization (line align4) */ +} emma_pp_ptr; + +typedef struct _emma_pp_size { + int width; + int height; +} emma_pp_size; + +/* + * if num.width != 0 + * resize ratio = num.width : den.width + * else + * resize ratio = in.width : out.width + * same for height + */ +typedef struct _emma_pp_scale { + emma_pp_size num; + emma_pp_size den; + emma_pp_size in; /* clip */ + emma_pp_size out; /* 0 -> same as in */ +} emma_pp_scale; + +typedef struct _emma_pp_cfg { + unsigned char operation; /* OR of EN_xx defines */ + + /* + * input color coeff + * fixed pt 8 bits, steps of 1/128 + * csc[5] is 1 or 0 to indicate Y + 16 + * csc[0] is matrix id 0-3 while csc[1-5]=0 + */ + unsigned short csc_table[6]; + + /* + * Output color (shade width, shade offset, pixel resolution) + * Eg. 16bpp RGB565 resolution, the values could be: + * red_width = 5, green_width = 6, blue_width = 6 + * red_offset = 11, green_offset = 5, blue_offset = 0 (defaults) + * rgb_resolution = 16 (default) + * For YUV422: xxx_width=0, blue_offset=PP_PIX_xxx + */ + unsigned short red_width; + unsigned short green_width; + unsigned short blue_width; + /* if offsets are 0, the offsets are by width LSb to MSb B:G:R */ + unsigned short red_offset; + unsigned short blue_offset; + unsigned short green_offset; + /* if resolution is 0, the minimum for the sum of widths is chosen */ + short rgb_resolution; /* 8,16,24 bpp only */ + + emma_pp_ptr ptr; /* dma buffer pointers */ + unsigned int outptr; /* RGB/YUV output */ + emma_pp_scale dim; /* in/out dimensions */ + + /* pixels between two adjacent input Y rows */ + unsigned short in_y_stride; /* 0 = in_width */ + /* PIXELS between two adjacent output rows */ + unsigned short out_stride; /* 0 = out_width */ +} emma_pp_cfg; + +int pp_ptr(unsigned long ptr); +int pp_enable(int flag); +int pp_cfg(vout_data * vout); +int pp_init(vout_data * vout); +int pp_num_last(void); +void pp_exit(vout_data * vout); + +#endif /* __MX27_PP_H__ */ diff -urN linux-2.6.26/drivers/media/video/mxc/output/mx27_v4l2_output.c linux-2.6.26-lab126/drivers/media/video/mxc/output/mx27_v4l2_output.c --- linux-2.6.26/drivers/media/video/mxc/output/mx27_v4l2_output.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/output/mx27_v4l2_output.c 2010-08-10 04:15:21.000000000 -0400 @@ -0,0 +1,1445 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mx27_v4l2_output.c + * + * @brief MX27 V4L2 Video Output Driver + * + * Video4Linux2 Output Device using MX27 eMMA Post-processing functionality. + * + * @ingroup MXC_V4L2_OUTPUT + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mxc_v4l2_output.h" +#include "mx27_pp.h" +#include "../drivers/video/mxc/mx2fb.h" + +#define SDC_FG_FB_FORMAT V4L2_PIX_FMT_RGB565 + +struct v4l2_output mxc_outputs[1] = { + { + .index = 0, + .name = "DISP0 Video Out", + .type = V4L2_OUTPUT_TYPE_ANALOG, /* not really correct, + but no other choice */ + .audioset = 0, + .modulator = 0, + .std = V4L2_STD_UNKNOWN}, +}; + +static int video_nr = 16; +static spinlock_t g_lock = SPIN_LOCK_UNLOCKED; +vout_data *g_vout; + +/* debug counters */ +uint32_t g_irq_cnt; +uint32_t g_buf_output_cnt; +uint32_t g_buf_q_cnt; +uint32_t g_buf_dq_cnt; + +#ifdef CONFIG_VIDEO_MXC_OUTPUT_FBSYNC +static uint32_t g_output_fb = -1; +static uint32_t g_fb_enabled = 0; +static uint32_t g_pp_ready = 0; + +static int fb_event_notify(struct notifier_block *self, + unsigned long action, void *data) +{ + struct fb_event *event = data; + struct fb_info *info = event->info; + unsigned long lock_flags; + int blank, i; + + for (i = 0; i < num_registered_fb; i++) + if (registered_fb[i] == info) + break; + + /* + * Check if the event is sent by the framebuffer in which + * the video is displayed. + */ + if (i != g_output_fb) + return 0; + + switch (action) { + case FB_EVENT_BLANK: + blank = *(int *)event->data; + spin_lock_irqsave(&g_lock, lock_flags); + g_fb_enabled = !blank; + if (blank && g_pp_ready) { + if (pp_enable(1)) + pr_debug("unable to enable PP\n"); + g_pp_ready = 0; + } + spin_unlock_irqrestore(&g_lock, lock_flags); + break; + case FB_EVENT_MXC_EOF: + spin_lock_irqsave(&g_lock, lock_flags); + g_fb_enabled = 1; + if (g_pp_ready) { + if (pp_enable(1)) + pr_debug("unable to enable PP\n"); + g_pp_ready = 0; + } + spin_unlock_irqrestore(&g_lock, lock_flags); + break; + } + + return 0; +} + +static struct notifier_block fb_event_notifier = { + .notifier_call = fb_event_notify, +}; + +static struct notifier_block mx2fb_event_notifier = { + .notifier_call = fb_event_notify, +}; +#endif + +#define QUEUE_SIZE (MAX_FRAME_NUM + 1) +static __inline int queue_size(v4l_queue * q) +{ + if (q->tail >= q->head) + return (q->tail - q->head); + else + return ((q->tail + QUEUE_SIZE) - q->head); +} + +static __inline int queue_buf(v4l_queue * q, int idx) +{ + if (((q->tail + 1) % QUEUE_SIZE) == q->head) + return -1; /* queue full */ + q->list[q->tail] = idx; + q->tail = (q->tail + 1) % QUEUE_SIZE; + return 0; +} + +static __inline int dequeue_buf(v4l_queue * q) +{ + int ret; + if (q->tail == q->head) + return -1; /* queue empty */ + ret = q->list[q->head]; + q->head = (q->head + 1) % QUEUE_SIZE; + return ret; +} + +static __inline int peek_next_buf(v4l_queue * q) +{ + if (q->tail == q->head) + return -1; /* queue empty */ + return q->list[q->head]; +} + +static __inline unsigned long get_jiffies(struct timeval *t) +{ + struct timeval cur; + + if (t->tv_usec >= 1000000) { + t->tv_sec += t->tv_usec / 1000000; + t->tv_usec = t->tv_usec % 1000000; + } + + do_gettimeofday(&cur); + if ((t->tv_sec < cur.tv_sec) + || ((t->tv_sec == cur.tv_sec) && (t->tv_usec < cur.tv_usec))) + return jiffies; + + if (t->tv_usec < cur.tv_usec) { + cur.tv_sec = t->tv_sec - cur.tv_sec - 1; + cur.tv_usec = t->tv_usec + 1000000 - cur.tv_usec; + } else { + cur.tv_sec = t->tv_sec - cur.tv_sec; + cur.tv_usec = t->tv_usec - cur.tv_usec; + } + + return jiffies + timeval_to_jiffies(&cur); +} + +/*! + * Private function to free buffers + * + * @param bufs_paddr Array of physical address of buffers to be freed + * + * @param bufs_vaddr Array of virtual address of buffers to be freed + * + * @param num_buf Number of buffers to be freed + * + * @param size Size for each buffer to be free + * + * @return status 0 success. + */ +static int mxc_free_buffers(dma_addr_t bufs_paddr[], void *bufs_vaddr[], + int num_buf, int size) +{ + int i; + + for (i = 0; i < num_buf; i++) { + if (bufs_vaddr[i] != 0) { + dma_free_coherent(0, size, bufs_vaddr[i], + bufs_paddr[i]); + pr_debug("freed @ paddr=0x%08X\n", (u32) bufs_paddr[i]); + bufs_paddr[i] = 0; + bufs_vaddr[i] = NULL; + } + } + return 0; +} + +/*! + * Private function to allocate buffers + * + * @param bufs_paddr Output array of physical address of buffers allocated + * + * @param bufs_vaddr Output array of virtual address of buffers allocated + * + * @param num_buf Input number of buffers to allocate + * + * @param size Input size for each buffer to allocate + * + * @return status -0 Successfully allocated a buffer, -ENOBUFS failed. + */ +static int mxc_allocate_buffers(dma_addr_t bufs_paddr[], void *bufs_vaddr[], + int num_buf, int size) +{ + int i; + + for (i = 0; i < num_buf; i++) { + bufs_vaddr[i] = dma_alloc_coherent(0, size, + &bufs_paddr[i], + GFP_DMA | GFP_KERNEL); + + if (bufs_vaddr[i] == 0) { + mxc_free_buffers(bufs_paddr, bufs_vaddr, i, size); + pr_debug("dma_alloc_coherent failed.\n"); + return -ENOBUFS; + } + pr_debug("allocated @ paddr=0x%08X, size=%d.\n", + (u32) bufs_paddr[i], size); + } + + return 0; +} + +static void mxc_v4l2out_timer_handler(unsigned long arg) +{ + int index; + unsigned long timeout; + unsigned long lock_flags; + vout_data *vout = (vout_data *) arg; + + pr_debug("timer handler: %lu\n", jiffies); + + spin_lock_irqsave(&g_lock, lock_flags); + + if ((vout->state == STATE_STREAM_OFF) + || (vout->state == STATE_STREAM_STOPPING)) { + pr_debug("stream has stopped\n"); + goto exit0; + } + + /* + * If timer occurs before PP h/w is ready, then set the state to + * paused and the timer will be set again when next buffer is queued + * or PP completes. + */ + if (vout->ipu_buf[0] != -1) { + pr_debug("buffer is busy\n"); + vout->state = STATE_STREAM_PAUSED; + goto exit0; + } + + /* Dequeue buffer and pass to PP */ + index = dequeue_buf(&vout->ready_q); + if (index == -1) { /* no buffers ready, should never occur */ + pr_debug("mxc_v4l2out: timer - no queued buffers ready\n"); + goto exit0; + } + + g_buf_dq_cnt++; + vout->frame_count++; + vout->ipu_buf[0] = index; + + if (pp_ptr((unsigned int)vout->queue_buf_paddr[index])) { + pr_debug("unable to update buffer\n"); + goto exit0; + } +#ifdef CONFIG_VIDEO_MXC_OUTPUT_FBSYNC + if (g_fb_enabled && (vout->v4l2_fb.flags != V4L2_FBUF_FLAG_OVERLAY)) + g_pp_ready = 1; + else if (pp_enable(1)) { + pr_debug("unable to enable PP\n"); + goto exit0; + } +#else + if (pp_enable(1)) { + pr_debug("unable to enable PP\n"); + goto exit0; + } +#endif + pr_debug("enabled index %d\n", index); + + /* Setup timer for next buffer */ + index = peek_next_buf(&vout->ready_q); + pr_debug("next index %d\n", index); + if (index != -1) { + /* if timestamp is 0, then default to 30fps */ + if ((vout->v4l2_bufs[index].timestamp.tv_sec == 0) + && (vout->v4l2_bufs[index].timestamp.tv_usec == 0)) + timeout = + vout->start_jiffies + vout->frame_count * HZ / 30; + else + timeout = + get_jiffies(&vout->v4l2_bufs[index].timestamp); + + if (jiffies >= timeout) { + pr_debug("warning: timer timeout already expired.\n"); + } + + if (mod_timer(&vout->output_timer, timeout)) + pr_debug("warning: timer was already set\n"); + + pr_debug("timer handler next schedule: %lu\n", timeout); + } else { + vout->state = STATE_STREAM_PAUSED; + pr_debug("timer handler paused\n"); + } + + exit0: + spin_unlock_irqrestore(&g_lock, lock_flags); +} + +irqreturn_t mxc_v4l2out_pp_in_irq_handler(int irq, void *dev_id) +{ + int last_buf; + int index; + unsigned long timeout; + unsigned long lock_flags; + vout_data *vout = dev_id; + + spin_lock_irqsave(&g_lock, lock_flags); + + g_irq_cnt++; + + if ((vout->state == STATE_STREAM_OFF) + || (vout->state == STATE_STREAM_STOPPING)) { + spin_unlock_irqrestore(&g_lock, lock_flags); + return IRQ_HANDLED; + } + + if (vout->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) { + struct fb_gwinfo gwinfo; + + gwinfo.enabled = 1; + gwinfo.alpha_value = 255; + gwinfo.ck_enabled = 0; + gwinfo.xpos = vout->crop_current.left; + gwinfo.ypos = vout->crop_current.top; + gwinfo.base = (unsigned long)vout->display_bufs[pp_num_last()]; + gwinfo.xres = vout->crop_current.width; + gwinfo.yres = vout->crop_current.height; + gwinfo.xres_virtual = vout->crop_current.width; + gwinfo.vs_reversed = 0; + + mx2_gw_set(&gwinfo); + } + + /* Process previous buffer */ + last_buf = vout->ipu_buf[0]; + pr_debug("last_buf %d g_irq_cnt %d\n", last_buf, g_irq_cnt); + if (last_buf != -1) { + g_buf_output_cnt++; + vout->v4l2_bufs[last_buf].flags = V4L2_BUF_FLAG_DONE; + queue_buf(&vout->done_q, last_buf); + vout->ipu_buf[0] = -1; + wake_up_interruptible(&vout->v4l_bufq); + } + + /* Setup timer for next buffer, when stream has been paused */ + if ((vout->state == STATE_STREAM_PAUSED) + && ((index = peek_next_buf(&vout->ready_q)) != -1)) { + pr_debug("next index %d\n", index); + /* if timestamp is 0, then default to 30fps */ + if ((vout->v4l2_bufs[index].timestamp.tv_sec == 0) + && (vout->v4l2_bufs[index].timestamp.tv_usec == 0)) + timeout = + vout->start_jiffies + vout->frame_count * HZ / 30; + else + timeout = + get_jiffies(&vout->v4l2_bufs[index].timestamp); + + if (jiffies >= timeout) { + pr_debug("warning: timer timeout already expired.\n"); + } + + vout->state = STATE_STREAM_ON; + + if (mod_timer(&vout->output_timer, timeout)) + pr_debug("warning: timer was already set\n"); + + pr_debug("timer handler next schedule: %lu\n", timeout); + } + + spin_unlock_irqrestore(&g_lock, lock_flags); + + return IRQ_HANDLED; +} + +/*! + * Start the output stream + * + * @param vout structure vout_data * + * + * @return status 0 Success + */ +static int mxc_v4l2out_streamon(vout_data * vout) +{ + unsigned long timeout; + int index; + + if (!vout) + return -EINVAL; + + if (vout->state != STATE_STREAM_OFF) + return -EBUSY; + + if (queue_size(&vout->ready_q) < 1) { + pr_debug("no buffers queued yet!\n"); + return -EINVAL; + } + + vout->ipu_buf[0] = -1; + + if (vout->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) { + /* Free previously allocated buffer */ + mxc_free_buffers(vout->display_bufs, vout->display_bufs_vaddr, + 2, vout->display_buf_size); + /* Allocate buffers for foreground */ + if (mxc_allocate_buffers(vout->display_bufs, + vout->display_bufs_vaddr, 2, + vout->display_buf_size) < 0) { + pr_debug("unable to allocate SDC FG buffers\n"); + return -ENOMEM; + } + } + + /* Configure PP */ + if (pp_cfg(vout)) { + /* Free previously allocated buffer */ + mxc_free_buffers(vout->display_bufs, vout->display_bufs_vaddr, + 2, vout->display_buf_size); + pr_debug("failed to config PP.\n"); + return -EINVAL; + } +#ifdef CONFIG_VIDEO_MXC_OUTPUT_FBSYNC + g_output_fb = vout->output_fb_num[vout->cur_disp_output]; + g_fb_enabled = 0; + g_pp_ready = 0; + fb_register_client(&fb_event_notifier); + mx2fb_register_client(&mx2fb_event_notifier); +#endif + vout->frame_count = 0; + vout->state = STATE_STREAM_ON; + index = peek_next_buf(&vout->ready_q); + + /* if timestamp is 0, then default to 30fps */ + if ((vout->v4l2_bufs[index].timestamp.tv_sec == 0) + && (vout->v4l2_bufs[index].timestamp.tv_usec == 0)) + timeout = jiffies; + else + timeout = get_jiffies(&vout->v4l2_bufs[index].timestamp); + + if (jiffies >= timeout) { + pr_debug("warning: timer timeout already expired.\n"); + } + + vout->start_jiffies = vout->output_timer.expires = timeout; + pr_debug("STREAMON:Add timer %d timeout @ %lu jiffies, current = %lu\n", + index, timeout, jiffies); + add_timer(&vout->output_timer); + + return 0; +} + +/*! + * Shut down the voutera + * + * @param vout structure vout_data * + * + * @return status 0 Success + */ +static int mxc_v4l2out_streamoff(vout_data * vout) +{ + int i, retval = 0; + unsigned long lock_flag = 0; + + if (!vout) + return -EINVAL; + + if (vout->state == STATE_STREAM_OFF) { + return 0; + } + + spin_lock_irqsave(&g_lock, lock_flag); + + del_timer(&vout->output_timer); + pp_enable(0); /* Disable PP */ + + if (vout->state == STATE_STREAM_ON) { + vout->state = STATE_STREAM_STOPPING; + } + + spin_unlock_irqrestore(&g_lock, lock_flag); + + vout->ready_q.head = vout->ready_q.tail = 0; + vout->done_q.head = vout->done_q.tail = 0; + for (i = 0; i < vout->buffer_cnt; i++) { + vout->v4l2_bufs[i].flags = 0; + vout->v4l2_bufs[i].timestamp.tv_sec = 0; + vout->v4l2_bufs[i].timestamp.tv_usec = 0; + } + + vout->state = STATE_STREAM_OFF; + + if (vout->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) { + struct fb_gwinfo gwinfo; + + /* Disable graphic window */ + gwinfo.enabled = 0; + mx2_gw_set(&gwinfo); + } +#ifdef CONFIG_VIDEO_MXC_OUTPUT_FBSYNC + g_output_fb = -1; + g_fb_enabled = 0; + g_pp_ready = 0; + fb_unregister_client(&fb_event_notifier); + mx2fb_unregister_client(&mx2fb_event_notifier); +#endif + + mxc_free_buffers(vout->display_bufs, vout->display_bufs_vaddr, + 2, vout->display_buf_size); + + return retval; +} + +/* + * Valid whether the palette is supported + * + * @param palette V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32 + * + * @return 1 if supported, 0 if failed + */ +static inline int valid_mode(u32 palette) +{ + return (palette == V4L2_PIX_FMT_YUV420); +} + +/* + * Returns bits per pixel for given pixel format + * + * @param pixelformat V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32 + * + * @return bits per pixel of pixelformat + */ +static u32 fmt_to_bpp(u32 pixelformat) +{ + u32 bpp; + + switch (pixelformat) { + case V4L2_PIX_FMT_RGB565: + bpp = 16; + break; + case V4L2_PIX_FMT_BGR24: + case V4L2_PIX_FMT_RGB24: + bpp = 24; + break; + case V4L2_PIX_FMT_BGR32: + case V4L2_PIX_FMT_RGB32: + bpp = 32; + break; + default: + bpp = 8; + break; + } + return bpp; +} + +/* + * V4L2 - Handles VIDIOC_G_FMT Ioctl + * + * @param vout structure vout_data * + * + * @param v4l2_format structure v4l2_format * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2out_g_fmt(vout_data * vout, struct v4l2_format *f) +{ + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + return -EINVAL; + } + *f = vout->v2f; + return 0; +} + +/* + * V4L2 - Handles VIDIOC_S_FMT Ioctl + * + * @param vout structure vout_data * + * + * @param v4l2_format structure v4l2_format * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2out_s_fmt(vout_data * vout, struct v4l2_format *f) +{ + int retval = 0; + u32 size = 0; + u32 bytesperline; + + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + goto err0; + } + if (!valid_mode(f->fmt.pix.pixelformat)) { + pr_debug("pixel format not supported\n"); + retval = -EINVAL; + goto err0; + } + + bytesperline = (f->fmt.pix.width * fmt_to_bpp(f->fmt.pix.pixelformat)) / + 8; + if (f->fmt.pix.bytesperline < bytesperline) { + f->fmt.pix.bytesperline = bytesperline; + } else { + bytesperline = f->fmt.pix.bytesperline; + } + + switch (f->fmt.pix.pixelformat) { + case V4L2_PIX_FMT_YUV422P: + /* byteperline for YUV planar formats is for + Y plane only */ + size = bytesperline * f->fmt.pix.height * 2; + break; + case V4L2_PIX_FMT_YUV420: + size = (bytesperline * f->fmt.pix.height * 3) / 2; + break; + default: + size = bytesperline * f->fmt.pix.height; + break; + } + + /* Return the actual size of the image to the app */ + f->fmt.pix.sizeimage = size; + + vout->v2f.fmt.pix.sizeimage = size; + vout->v2f.fmt.pix.width = f->fmt.pix.width; + vout->v2f.fmt.pix.height = f->fmt.pix.height; + vout->v2f.fmt.pix.pixelformat = f->fmt.pix.pixelformat; + vout->v2f.fmt.pix.bytesperline = f->fmt.pix.bytesperline; + + retval = 0; + err0: + return retval; +} + +/* + * V4L2 - Handles VIDIOC_G_CTRL Ioctl + * + * @param vout structure vout_data * + * + * @param c structure v4l2_control * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_get_v42lout_control(vout_data * vout, struct v4l2_control *c) +{ + switch (c->id) { + case V4L2_CID_HFLIP: + return (vout->rotate & IPU_ROTATE_HORIZ_FLIP) ? 1 : 0; + case V4L2_CID_VFLIP: + return (vout->rotate & IPU_ROTATE_VERT_FLIP) ? 1 : 0; + case (V4L2_CID_PRIVATE_BASE + 1): + return vout->rotate; + default: + return -EINVAL; + } +} + +/* + * V4L2 - Handles VIDIOC_S_CTRL Ioctl + * + * @param vout structure vout_data * + * + * @param c structure v4l2_control * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_set_v42lout_control(vout_data * vout, struct v4l2_control *c) +{ + switch (c->id) { + case V4L2_CID_HFLIP: + case V4L2_CID_VFLIP: + case V4L2_CID_MXC_ROT: + return 0; + default: + return -EINVAL; + } + return 0; +} + +/*! + * V4L2 interface - open function + * + * @param inode structure inode * + * + * @param file structure file * + * + * @return status 0 success, ENODEV invalid device instance, + * ENODEV timeout, ERESTARTSYS interrupted by user + */ +static int mxc_v4l2out_open(struct inode *inode, struct file *file) +{ + struct video_device *dev = video_devdata(file); + vout_data *vout = video_get_drvdata(dev); + int err; + + if (!vout) { + pr_info("Internal error, vout_data not found!\n"); + return -ENODEV; + } + + down(&vout->busy_lock); + + err = -EINTR; + if (signal_pending(current)) + goto oops; + + if (vout->open_count++ == 0) { + pp_init(vout); + + init_waitqueue_head(&vout->v4l_bufq); + + init_timer(&vout->output_timer); + vout->output_timer.function = mxc_v4l2out_timer_handler; + vout->output_timer.data = (unsigned long)vout; + + vout->state = STATE_STREAM_OFF; + g_irq_cnt = g_buf_output_cnt = g_buf_q_cnt = g_buf_dq_cnt = 0; + + } + + file->private_data = dev; + up(&vout->busy_lock); + return 0; + + oops: + up(&vout->busy_lock); + return err; +} + +/*! + * V4L2 interface - close function + * + * @param inode struct inode * + * + * @param file struct file * + * + * @return 0 success + */ +static int mxc_v4l2out_close(struct inode *inode, struct file *file) +{ + struct video_device *dev = file->private_data; + vout_data *vout = video_get_drvdata(dev); + + if (--vout->open_count == 0) { + pr_debug("release resource\n"); + + pp_exit(vout); + if (vout->state != STATE_STREAM_OFF) + mxc_v4l2out_streamoff(vout); + + file->private_data = NULL; + + mxc_free_buffers(vout->queue_buf_paddr, + vout->queue_buf_vaddr, + vout->buffer_cnt, vout->queue_buf_size); + vout->buffer_cnt = 0; + mxc_free_buffers(vout->display_bufs, + vout->display_bufs_vaddr, + 2, vout->display_buf_size); + + /* capture off */ + wake_up_interruptible(&vout->v4l_bufq); + } + + return 0; +} + +/*! + * V4L2 interface - ioctl function + * + * @param inode struct inode * + * + * @param file struct file * + * + * @param ioctlnr unsigned int + * + * @param arg void * + * + * @return 0 success, ENODEV for invalid device instance, + * -1 for other errors. + */ +static int +mxc_v4l2out_do_ioctl(struct inode *inode, struct file *file, + unsigned int ioctlnr, void *arg) +{ + struct video_device *dev = file->private_data; + vout_data *vout = video_get_drvdata(dev); + int retval = 0; + int i = 0; + + if (!vout) + return -EBADF; + + /* make this _really_ smp-safe */ + if (down_interruptible(&vout->busy_lock)) + return -EBUSY; + + switch (ioctlnr) { + case VIDIOC_QUERYCAP: + { + struct v4l2_capability *cap = arg; + strcpy(cap->driver, "mxc_v4l2_output"); + cap->version = 0; + cap->capabilities = + V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING; + cap->card[0] = '\0'; + cap->bus_info[0] = '\0'; + retval = 0; + break; + } + case VIDIOC_G_FMT: + { + struct v4l2_format *gf = arg; + retval = mxc_v4l2out_g_fmt(vout, gf); + break; + } + case VIDIOC_S_FMT: + { + struct v4l2_format *sf = arg; + if (vout->state != STATE_STREAM_OFF) { + retval = -EBUSY; + break; + } + retval = mxc_v4l2out_s_fmt(vout, sf); + break; + } + case VIDIOC_REQBUFS: + { + struct v4l2_requestbuffers *req = arg; + if ((req->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) || + (req->memory != V4L2_MEMORY_MMAP)) { + pr_debug + ("VIDIOC_REQBUFS: incorrect buffer type\n"); + retval = -EINVAL; + break; + } + + if (req->count == 0) + mxc_v4l2out_streamoff(vout); + + if (vout->state == STATE_STREAM_OFF) { + if (vout->queue_buf_paddr[0] != 0) { + mxc_free_buffers(vout->queue_buf_paddr, + vout->queue_buf_vaddr, + vout->buffer_cnt, + vout->queue_buf_size); + pr_debug + ("VIDIOC_REQBUFS: freed buffers\n"); + } + vout->buffer_cnt = 0; + } else { + pr_debug("VIDIOC_REQBUFS: Buffer is in use\n"); + retval = -EBUSY; + break; + } + + if (req->count == 0) + break; + + if (req->count < MIN_FRAME_NUM) { + req->count = MIN_FRAME_NUM; + } else if (req->count > MAX_FRAME_NUM) { + req->count = MAX_FRAME_NUM; + } + vout->buffer_cnt = req->count; + vout->queue_buf_size = + PAGE_ALIGN(vout->v2f.fmt.pix.sizeimage); + + retval = mxc_allocate_buffers(vout->queue_buf_paddr, + vout->queue_buf_vaddr, + vout->buffer_cnt, + vout->queue_buf_size); + if (retval < 0) + break; + + /* Init buffer queues */ + vout->done_q.head = 0; + vout->done_q.tail = 0; + vout->ready_q.head = 0; + vout->ready_q.tail = 0; + + for (i = 0; i < vout->buffer_cnt; i++) { + memset(&(vout->v4l2_bufs[i]), 0, + sizeof(vout->v4l2_bufs[i])); + vout->v4l2_bufs[i].flags = 0; + vout->v4l2_bufs[i].memory = V4L2_MEMORY_MMAP; + vout->v4l2_bufs[i].index = i; + vout->v4l2_bufs[i].type = + V4L2_BUF_TYPE_VIDEO_OUTPUT; + vout->v4l2_bufs[i].length = + PAGE_ALIGN(vout->v2f.fmt.pix.sizeimage); + vout->v4l2_bufs[i].m.offset = + (unsigned long)vout->queue_buf_paddr[i]; + vout->v4l2_bufs[i].timestamp.tv_sec = 0; + vout->v4l2_bufs[i].timestamp.tv_usec = 0; + } + break; + } + case VIDIOC_QUERYBUF: + { + struct v4l2_buffer *buf = arg; + u32 type = buf->type; + int index = buf->index; + + if ((type != V4L2_BUF_TYPE_VIDEO_OUTPUT) || + (index >= vout->buffer_cnt)) { + pr_debug + ("VIDIOC_QUERYBUFS: incorrect buffer type\n"); + retval = -EINVAL; + break; + } + down(&vout->param_lock); + memcpy(buf, &(vout->v4l2_bufs[index]), sizeof(*buf)); + up(&vout->param_lock); + break; + } + case VIDIOC_QBUF: + { + struct v4l2_buffer *buf = arg; + int index = buf->index; + unsigned long lock_flags; + unsigned long timeout; + + if ((buf->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) || + (index >= vout->buffer_cnt) || (buf->flags != 0)) { + retval = -EINVAL; + break; + } + + pr_debug("VIDIOC_QBUF: %d\n", buf->index); + + spin_lock_irqsave(&g_lock, lock_flags); + + memcpy(&(vout->v4l2_bufs[index]), buf, sizeof(*buf)); + vout->v4l2_bufs[index].flags |= V4L2_BUF_FLAG_QUEUED; + + g_buf_q_cnt++; + queue_buf(&vout->ready_q, index); + + if (vout->state == STATE_STREAM_PAUSED) { + index = peek_next_buf(&vout->ready_q); + + /* if timestamp is 0, then default to 30fps */ + if ((vout->v4l2_bufs[index].timestamp.tv_sec == + 0) + && (vout->v4l2_bufs[index].timestamp. + tv_usec == 0)) + timeout = + vout->start_jiffies + + vout->frame_count * HZ / 30; + else + timeout = + get_jiffies(&vout->v4l2_bufs[index]. + timestamp); + + if (jiffies >= timeout) { + pr_debug + ("warning: timer timeout already expired.\n"); + } + + vout->output_timer.expires = timeout; + pr_debug + ("QBUF:Add timer %d timeout @ %lu jiffies, " + "current = %lu\n", index, timeout, + jiffies); + add_timer(&vout->output_timer); + vout->state = STATE_STREAM_ON; + } + + spin_unlock_irqrestore(&g_lock, lock_flags); + break; + } + case VIDIOC_DQBUF: + { + struct v4l2_buffer *buf = arg; + int idx; + + pr_debug("VIDIOC_DQBUF: q size = %d\n", + queue_size(&vout->done_q)); + + if ((queue_size(&vout->done_q) == 0) && + (file->f_flags & O_NONBLOCK)) { + retval = -EAGAIN; + break; + } + + if (!wait_event_interruptible_timeout(vout->v4l_bufq, + queue_size(&vout-> + done_q) + != 0, 10 * HZ)) { + pr_debug("VIDIOC_DQBUF: timeout\n"); + retval = -ETIME; + break; + } else if (signal_pending(current)) { + pr_debug("VIDIOC_DQBUF: interrupt received\n"); + retval = -ERESTARTSYS; + break; + } + idx = dequeue_buf(&vout->done_q); + if (idx == -1) { /* No frame free */ + pr_debug + ("VIDIOC_DQBUF: no free buffers, returning\n"); + retval = -EAGAIN; + break; + } + if ((vout->v4l2_bufs[idx].flags & V4L2_BUF_FLAG_DONE) == + 0) + pr_debug + ("VIDIOC_DQBUF: buffer in done q, but not " + "flagged as done\n"); + + vout->v4l2_bufs[idx].flags = 0; + memcpy(buf, &(vout->v4l2_bufs[idx]), sizeof(*buf)); + pr_debug("VIDIOC_DQBUF: %d\n", buf->index); + break; + } + case VIDIOC_STREAMON: + { + retval = mxc_v4l2out_streamon(vout); + break; + } + case VIDIOC_STREAMOFF: + { + retval = mxc_v4l2out_streamoff(vout); + break; + } + case VIDIOC_G_CTRL: + { + retval = mxc_get_v42lout_control(vout, arg); + break; + } + case VIDIOC_S_CTRL: + { + retval = mxc_set_v42lout_control(vout, arg); + break; + } + case VIDIOC_CROPCAP: + { + struct v4l2_cropcap *cap = arg; + + if (cap->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + break; + } + cap->bounds = vout->crop_bounds[vout->cur_disp_output]; + cap->defrect = vout->crop_bounds[vout->cur_disp_output]; + retval = 0; + break; + } + case VIDIOC_G_CROP: + { + struct v4l2_crop *crop = arg; + + if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + break; + } + crop->c = vout->crop_current; + break; + } + case VIDIOC_S_CROP: + { + struct v4l2_crop *crop = arg; + struct v4l2_rect *b = + &(vout->crop_bounds[vout->cur_disp_output]); + + if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + break; + } + if (crop->c.height < 0) { + retval = -EINVAL; + break; + } + if (crop->c.width < 0) { + retval = -EINVAL; + break; + } + + if (crop->c.top < b->top) + crop->c.top = b->top; + if (crop->c.top > b->top + b->height) + crop->c.top = b->top + b->height; + if (crop->c.height > b->top - crop->c.top + b->height) + crop->c.height = + b->top - crop->c.top + b->height; + + if (crop->c.left < b->left) + crop->c.top = b->left; + if (crop->c.left > b->left + b->width) + crop->c.top = b->left + b->width; + if (crop->c.width > b->left - crop->c.left + b->width) + crop->c.width = + b->left - crop->c.left + b->width; + + /* stride line limitation */ + crop->c.height -= crop->c.height % 8; + crop->c.width -= crop->c.width % 8; + + vout->crop_current = crop->c; + + vout->display_buf_size = vout->crop_current.width * + vout->crop_current.height; + vout->display_buf_size *= + fmt_to_bpp(SDC_FG_FB_FORMAT) / 8; + break; + } + case VIDIOC_ENUMOUTPUT: + { + struct v4l2_output *output = arg; + + if ((output->index >= 2) || + (vout->output_enabled[output->index] == false)) { + retval = -EINVAL; + break; + } + + *output = mxc_outputs[0]; + output->name[4] = '0' + output->index; + break; + } + case VIDIOC_G_OUTPUT: + { + int *p_output_num = arg; + + *p_output_num = vout->cur_disp_output; + break; + } + case VIDIOC_S_OUTPUT: + { + int *p_output_num = arg; + + if ((*p_output_num >= 2) || + (vout->output_enabled[*p_output_num] == false)) { + retval = -EINVAL; + break; + } + + if (vout->state != STATE_STREAM_OFF) { + retval = -EBUSY; + break; + } + + vout->cur_disp_output = *p_output_num; + break; + } + case VIDIOC_G_FBUF: + { + struct v4l2_framebuffer *fb = arg; + *fb = vout->v4l2_fb; + break; + } + case VIDIOC_S_FBUF: + { + struct v4l2_framebuffer *fb = arg; + vout->v4l2_fb = *fb; + vout->v4l2_fb.capability = V4L2_FBUF_CAP_EXTERNOVERLAY; + break; + } + case VIDIOC_ENUM_FMT: + case VIDIOC_TRY_FMT: + case VIDIOC_QUERYCTRL: + case VIDIOC_G_PARM: + case VIDIOC_ENUMSTD: + case VIDIOC_G_STD: + case VIDIOC_S_STD: + case VIDIOC_G_TUNER: + case VIDIOC_S_TUNER: + case VIDIOC_G_FREQUENCY: + case VIDIOC_S_FREQUENCY: + default: + retval = -EINVAL; + break; + } + + up(&vout->busy_lock); + return retval; +} + +/* + * V4L2 interface - ioctl function + * + * @return None + */ +static int +mxc_v4l2out_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + return video_usercopy(inode, file, cmd, arg, mxc_v4l2out_do_ioctl); +} + +/*! + * V4L2 interface - mmap function + * + * @param file structure file * + * + * @param vma structure vm_area_struct * + * + * @return status 0 Success, EINTR busy lock error, + * ENOBUFS remap_page error + */ +static int mxc_v4l2out_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct video_device *dev = file->private_data; + unsigned long start = vma->vm_start; + unsigned long size = vma->vm_end - vma->vm_start; + int res = 0; + vout_data *vout = video_get_drvdata(dev); + + /* make this _really_ smp-safe */ + if (down_interruptible(&vout->busy_lock)) + return -EINTR; + + /* make buffers write-thru cacheable */ + vma->vm_page_prot = __pgprot(pgprot_val(vma->vm_page_prot) & + ~L_PTE_BUFFERABLE); + + if (remap_pfn_range(vma, start, vma->vm_pgoff, size, vma->vm_page_prot)) { + pr_debug("mxc_mmap(V4L)i - remap_pfn_range failed\n"); + res = -ENOBUFS; + goto mxc_mmap_exit; + } + + mxc_mmap_exit: + up(&vout->busy_lock); + return res; +} + +/*! + * V4L2 interface - poll function + * + * @param file structure file * + * + * @param wait structure poll_table * + * + * @return status POLLIN | POLLRDNORM + */ +static unsigned int mxc_v4l2out_poll(struct file *file, poll_table * wait) +{ + struct video_device *dev = file->private_data; + vout_data *vout = video_get_drvdata(dev); + + wait_queue_head_t *queue = NULL; + int res = POLLIN | POLLRDNORM; + + if (down_interruptible(&vout->busy_lock)) + return -EINTR; + + queue = &vout->v4l_bufq; + poll_wait(file, queue, wait); + + up(&vout->busy_lock); + return res; +} + +static struct file_operations mxc_v4l2out_fops = { + .owner = THIS_MODULE, + .open = mxc_v4l2out_open, + .release = mxc_v4l2out_close, + .ioctl = mxc_v4l2out_ioctl, + .mmap = mxc_v4l2out_mmap, + .poll = mxc_v4l2out_poll, +}; + +static struct video_device mxc_v4l2out_template = { + .owner = THIS_MODULE, + .name = "MXC Video Output", + .type = 0, + .type2 = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING, + .fops = &mxc_v4l2out_fops, + .release = video_device_release, +}; + +/*! + * Probe routine for the framebuffer driver. It is called during the + * driver binding process. The following functions are performed in + * this routine: Framebuffer initialization, Memory allocation and + * mapping, Framebuffer registration, IPU initialization. + * + * @return Appropriate error code to the kernel common code + */ +static int mxc_v4l2out_probe(struct platform_device *pdev) +{ + int i; + vout_data *vout; + + /* + * Allocate sufficient memory for the fb structure + */ + g_vout = vout = kmalloc(sizeof(vout_data), GFP_KERNEL); + + if (!vout) + return 0; + + memset(vout, 0, sizeof(vout_data)); + + vout->video_dev = video_device_alloc(); + if (vout->video_dev == NULL) + return -1; + vout->video_dev->dev = &pdev->dev; + vout->video_dev->minor = -1; + + *(vout->video_dev) = mxc_v4l2out_template; + + /* register v4l device */ + if (video_register_device(vout->video_dev, + VFL_TYPE_GRABBER, video_nr) == -1) { + pr_debug("video_register_device failed\n"); + return 0; + } + pr_debug("mxc_v4l2out: registered device video%d\n", + vout->video_dev->minor & 0x1f); + + video_set_drvdata(vout->video_dev, vout); + + init_MUTEX(&vout->param_lock); + init_MUTEX(&vout->busy_lock); + + /* setup outputs and cropping */ + vout->cur_disp_output = -1; + for (i = 0; i < num_registered_fb; i++) { + char *idstr = registered_fb[i]->fix.id; + if (strncmp(idstr, "DISP", 4) == 0) { + int disp_num = i; + vout->crop_bounds[disp_num].left = 0; + vout->crop_bounds[disp_num].top = 0; + vout->crop_bounds[disp_num].width = + registered_fb[i]->var.xres; + vout->crop_bounds[disp_num].height = + registered_fb[i]->var.yres; + vout->output_enabled[disp_num] = true; + vout->output_fb_num[disp_num] = i; + if (vout->cur_disp_output == -1) + vout->cur_disp_output = disp_num; + } + + } + vout->crop_current = vout->crop_bounds[vout->cur_disp_output]; + + /* Setup framebuffer parameters */ + vout->v4l2_fb.capability = V4L2_FBUF_CAP_EXTERNOVERLAY; + vout->v4l2_fb.flags = V4L2_FBUF_FLAG_PRIMARY; + + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxc_v4l2out_driver = { + .driver = { + .name = "MXC Video Output", + .owner = THIS_MODULE, + .bus = &platform_bus_type, + }, + .probe = mxc_v4l2out_probe, + .remove = NULL, +}; + +static void camera_platform_release(struct device *device) +{ +} + +static struct platform_device mxc_v4l2out_device = { + .name = "MXC Video Output", + .dev = { + .release = camera_platform_release, + }, + .id = 0, +}; + +/*! + * mxc v4l2 init function + * + */ +static int mxc_v4l2out_init(void) +{ + u8 err = 0; + + err = platform_driver_register(&mxc_v4l2out_driver); + if (err == 0) { + platform_device_register(&mxc_v4l2out_device); + } + return err; +} + +/*! + * mxc v4l2 cleanup function + * + */ +static void mxc_v4l2out_clean(void) +{ + pr_debug("unregistering video\n"); + + video_unregister_device(g_vout->video_dev); + + platform_driver_unregister(&mxc_v4l2out_driver); + platform_device_unregister(&mxc_v4l2out_device); + kfree(g_vout); + g_vout = NULL; +} + +module_init(mxc_v4l2out_init); +module_exit(mxc_v4l2out_clean); + +module_param(video_nr, int, 0444); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("V4L2-driver for MXC video output"); +MODULE_LICENSE("GPL"); +MODULE_SUPPORTED_DEVICE("video"); diff -urN linux-2.6.26/drivers/media/video/mxc/output/mx31_v4l2_wvga_output.c linux-2.6.26-lab126/drivers/media/video/mxc/output/mx31_v4l2_wvga_output.c --- linux-2.6.26/drivers/media/video/mxc/output/mx31_v4l2_wvga_output.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/output/mx31_v4l2_wvga_output.c 2010-08-10 04:15:21.000000000 -0400 @@ -0,0 +1,1926 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file drivers/media/video/mxc/output/mxc_v4l2_output.c + * + * @brief MXC V4L2 Video Output Driver + * + * Video4Linux2 Output Device using MXC IPU Post-processing functionality. + * + * @ingroup MXC_V4L2_OUTPUT + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "mxc_v4l2_output.h" + +vout_data *g_vout; +#define SDC_FG_FB_FORMAT IPU_PIX_FMT_RGB565 + +struct v4l2_output mxc_outputs[2] = { + { + .index = MXC_V4L2_OUT_2_SDC, + .name = "DISP3 Video Out", + .type = V4L2_OUTPUT_TYPE_ANALOG, /* not really correct, + but no other choice */ + .audioset = 0, + .modulator = 0, + .std = V4L2_STD_UNKNOWN}, + { + .index = MXC_V4L2_OUT_2_ADC, + .name = "DISPx Video Out", + .type = V4L2_OUTPUT_TYPE_ANALOG, /* not really correct, + but no other choice */ + .audioset = 0, + .modulator = 0, + .std = V4L2_STD_UNKNOWN} +}; + +static int video_nr = 16; +static DEFINE_SPINLOCK(g_lock); +static unsigned int g_pp_out_number; +static unsigned int g_pp_in_number; + +/* debug counters */ +uint32_t g_irq_cnt; +uint32_t g_buf_output_cnt; +uint32_t g_buf_q_cnt; +uint32_t g_buf_dq_cnt; + +static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type) +{ + return ((type == IPU_INPUT_BUFFER) ? ((uint32_t) ch & 0xFF) : + ((type == IPU_OUTPUT_BUFFER) ? (((uint32_t) ch >> 8) & 0xFF) + : (((uint32_t) ch >> 16) & 0xFF))); +}; + +static inline uint32_t DMAParamAddr(uint32_t dma_ch) +{ + return (0x10000 | (dma_ch << 4)); +}; + +#define QUEUE_SIZE (MAX_FRAME_NUM + 1) +static inline int queue_size(v4l_queue * q) +{ + if (q->tail >= q->head) + return (q->tail - q->head); + else + return ((q->tail + QUEUE_SIZE) - q->head); +} + +static inline int queue_buf(v4l_queue * q, int idx) +{ + if (((q->tail + 1) % QUEUE_SIZE) == q->head) + return -1; /* queue full */ + q->list[q->tail] = idx; + q->tail = (q->tail + 1) % QUEUE_SIZE; + return 0; +} + +static inline int dequeue_buf(v4l_queue * q) +{ + int ret; + if (q->tail == q->head) + return -1; /* queue empty */ + ret = q->list[q->head]; + q->head = (q->head + 1) % QUEUE_SIZE; + return ret; +} + +static inline int peek_next_buf(v4l_queue * q) +{ + if (q->tail == q->head) + return -1; /* queue empty */ + return q->list[q->head]; +} + +static inline unsigned long get_jiffies(struct timeval *t) +{ + struct timeval cur; + + if (t->tv_usec >= 1000000) { + t->tv_sec += t->tv_usec / 1000000; + t->tv_usec = t->tv_usec % 1000000; + } + + do_gettimeofday(&cur); + if ((t->tv_sec < cur.tv_sec) + || ((t->tv_sec == cur.tv_sec) && (t->tv_usec < cur.tv_usec))) + return jiffies; + + if (t->tv_usec < cur.tv_usec) { + cur.tv_sec = t->tv_sec - cur.tv_sec - 1; + cur.tv_usec = t->tv_usec + 1000000 - cur.tv_usec; + } else { + cur.tv_sec = t->tv_sec - cur.tv_sec; + cur.tv_usec = t->tv_usec - cur.tv_usec; + } + + return jiffies + timeval_to_jiffies(&cur); +} + +/*! + * Private function to free buffers + * + * @param bufs_paddr Array of physical address of buffers to be freed + * + * @param bufs_vaddr Array of virtual address of buffers to be freed + * + * @param num_buf Number of buffers to be freed + * + * @param size Size for each buffer to be free + * + * @return status 0 success. + */ +static int mxc_free_buffers(dma_addr_t bufs_paddr[], void *bufs_vaddr[], + int num_buf, int size) +{ + int i; + + for (i = 0; i < num_buf; i++) { + if (bufs_vaddr[i] != 0) { + dma_free_coherent(0, size, bufs_vaddr[i], + bufs_paddr[i]); + pr_debug("freed @ paddr=0x%08X\n", (u32) bufs_paddr[i]); + bufs_paddr[i] = 0; + bufs_vaddr[i] = NULL; + } + } + return 0; +} + +/*! + * Private function to allocate buffers + * + * @param bufs_paddr Output array of physical address of buffers allocated + * + * @param bufs_vaddr Output array of virtual address of buffers allocated + * + * @param num_buf Input number of buffers to allocate + * + * @param size Input size for each buffer to allocate + * + * @return status -0 Successfully allocated a buffer, -ENOBUFS failed. + */ +static int mxc_allocate_buffers(dma_addr_t bufs_paddr[], void *bufs_vaddr[], + int num_buf, int size) +{ + int i; + + for (i = 0; i < num_buf; i++) { + bufs_vaddr[i] = dma_alloc_coherent(0, size, + &bufs_paddr[i], + GFP_DMA | GFP_KERNEL); + + if (bufs_vaddr[i] == 0) { + mxc_free_buffers(bufs_paddr, bufs_vaddr, i, size); + printk(KERN_ERR "dma_alloc_coherent failed.\n"); + return -ENOBUFS; + } + pr_debug("allocated @ paddr=0x%08X, size=%d.\n", + (u32) bufs_paddr[i], size); + } + + return 0; +} + +/* + * Returns bits per pixel for given pixel format + * + * @param pixelformat V4L2_PIX_FMT_RGB565, + * V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32 + * + * @return bits per pixel of pixelformat + */ +static u32 fmt_to_bpp(u32 pixelformat) +{ + u32 bpp; + + switch (pixelformat) { + case V4L2_PIX_FMT_RGB565: + bpp = 16; + break; + case V4L2_PIX_FMT_BGR24: + case V4L2_PIX_FMT_RGB24: + bpp = 24; + break; + case V4L2_PIX_FMT_BGR32: + case V4L2_PIX_FMT_RGB32: + bpp = 32; + break; + default: + bpp = 8; + break; + } + return bpp; +} + +static u32 bpp_to_fmt(struct fb_info *fbi) +{ + if (fbi->var.nonstd) + return fbi->var.nonstd; + + if (fbi->var.bits_per_pixel == 24) + return V4L2_PIX_FMT_BGR24; + else if (fbi->var.bits_per_pixel == 32) + return V4L2_PIX_FMT_BGR32; + else if (fbi->var.bits_per_pixel == 16) + return V4L2_PIX_FMT_RGB565; + + return 0; +} + +static void mxc_v4l2out_timer_handler(unsigned long arg) +{ + int index; + unsigned long timeout; + unsigned long lock_flags = 0; + vout_data *vout = (vout_data *) arg; + + dev_dbg(vout->video_dev->dev, "timer handler: %lu\n", jiffies); + + spin_lock_irqsave(&g_lock, lock_flags); + + if ((vout->state == STATE_STREAM_STOPPING) + || (vout->state == STATE_STREAM_OFF)) + goto exit0; + /* + * If timer occurs before IPU h/w is ready, then set the state to + * paused and the timer will be set again when next buffer is queued + * or PP comletes + */ + if (vout->ipu_buf[0] != -1) { + dev_dbg(vout->video_dev->dev, "IPU buffer busy\n"); + vout->state = STATE_STREAM_PAUSED; + goto exit0; + } + + /* One frame buffer should be ready here */ + if (vout->frame_count % 2 == 1) { + /* set BUF0 rdy */ + if (ipu_select_buffer(vout->display_ch, IPU_INPUT_BUFFER, 0) < + 0) + pr_debug("error selecting display buf 0"); + } else { + if (ipu_select_buffer(vout->display_ch, IPU_INPUT_BUFFER, 1) < + 0) + pr_debug("error selecting display buf 1"); + } + + /* Dequeue buffer and pass to IPU */ + index = dequeue_buf(&vout->ready_q); + if (index == -1) { /* no buffers ready, should never occur */ + dev_err(vout->video_dev->dev, + "mxc_v4l2out: timer - no queued buffers ready\n"); + goto exit0; + } + + g_buf_dq_cnt++; + vout->frame_count++; + vout->ipu_buf[1] = vout->ipu_buf[0] = index; + + if (ipu_update_channel_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, + 0, + vout->v4l2_bufs[vout->ipu_buf[0]].m. + offset) < 0) + goto exit0; + + if (ipu_update_channel_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, + 1, + vout->v4l2_bufs[vout->ipu_buf[0]].m. + offset + vout->v2f.fmt.pix.width / 2) < 0) + goto exit0; + + /* All buffer should now ready in IPU out, tranfer to display buf */ + if (ipu_update_channel_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, + 0, + vout-> + display_bufs[(vout->frame_count - + 1) % 2]) < 0) { + dev_err(vout->video_dev->dev, + "unable to update buffer %d address\n", + vout->next_rdy_ipu_buf); + goto exit0; + } + if (ipu_update_channel_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, + 1, + vout-> + display_bufs[(vout->frame_count - + 1) % 2] + + vout->crop_current.width / 2 * + bytes_per_pixel(SDC_FG_FB_FORMAT)) < 0) { + dev_err(vout->video_dev->dev, + "unable to update buffer %d address\n", + vout->next_rdy_ipu_buf); + goto exit0; + } + + if (ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 0) < 0) { + dev_err(vout->video_dev->dev, + "unable to set IPU buffer ready\n"); + goto exit0; + } + + if (ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, 0) < 0) { + dev_err(vout->video_dev->dev, + "unable to set IPU buffer ready\n"); + goto exit0; + } + + /* Setup timer for next buffer */ + index = peek_next_buf(&vout->ready_q); + if (index != -1) { + /* if timestamp is 0, then default to 30fps */ + if ((vout->v4l2_bufs[index].timestamp.tv_sec == 0) + && (vout->v4l2_bufs[index].timestamp.tv_usec == 0)) + timeout = + vout->start_jiffies + vout->frame_count * HZ / 30; + else + timeout = + get_jiffies(&vout->v4l2_bufs[index].timestamp); + + if (jiffies >= timeout) { + dev_dbg(vout->video_dev->dev, + "warning: timer timeout already expired.\n"); + } + if (mod_timer(&vout->output_timer, timeout)) + dev_dbg(vout->video_dev->dev, + "warning: timer was already set\n"); + + dev_dbg(vout->video_dev->dev, + "timer handler next schedule: %lu\n", timeout); + } else { + vout->state = STATE_STREAM_PAUSED; + } + +exit0: + spin_unlock_irqrestore(&g_lock, lock_flags); +} + +extern void _ipu_write_param_mem(uint32_t addr, uint32_t *data, + uint32_t numWords); + +static irqreturn_t mxc_v4l2out_pp_in_irq_handler(int irq, void *dev_id) +{ + unsigned long lock_flags = 0; + vout_data *vout = dev_id; + uint32_t u_offset; + uint32_t v_offset; + uint32_t local_params[4]; + uint32_t width, height; + uint32_t dma_chan; + + spin_lock_irqsave(&g_lock, lock_flags); + g_irq_cnt++; + + dma_chan = channel_2_dma(vout->post_proc_ch, IPU_INPUT_BUFFER); + memset(&local_params, 0, sizeof(local_params)); + + if (g_pp_in_number % 2 == 1) { + u_offset = vout->offset.u_offset - vout->v2f.fmt.pix.width / 4; + v_offset = vout->offset.v_offset - vout->v2f.fmt.pix.width / 4; + width = vout->v2f.fmt.pix.width / 2; + height = vout->v2f.fmt.pix.height; + local_params[3] = + (uint32_t) ((width - 1) << 12) | ((uint32_t) (height - + 1) << 24); + local_params[1] = (1UL << (46 - 32)) | (u_offset << (53 - 32)); + local_params[2] = u_offset >> (64 - 53); + local_params[2] |= v_offset << (79 - 64); + local_params[3] |= v_offset >> (96 - 79); + _ipu_write_param_mem(DMAParamAddr(dma_chan), local_params, 4); + + if (ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 1) < + 0) { + dev_err(vout->video_dev->dev, + "unable to set IPU buffer ready\n"); + } + } else { + u_offset = vout->offset.u_offset; + v_offset = vout->offset.v_offset; + width = vout->v2f.fmt.pix.width / 2; + height = vout->v2f.fmt.pix.height; + local_params[3] = + (uint32_t) ((width - 1) << 12) | ((uint32_t) (height - + 1) << 24); + local_params[1] = (1UL << (46 - 32)) | (u_offset << (53 - 32)); + local_params[2] = u_offset >> (64 - 53); + local_params[2] |= v_offset << (79 - 64); + local_params[3] |= v_offset >> (96 - 79); + _ipu_write_param_mem(DMAParamAddr(dma_chan), local_params, 4); + } + g_pp_in_number++; + + spin_unlock_irqrestore(&g_lock, lock_flags); + + return IRQ_HANDLED; +} + +static irqreturn_t mxc_v4l2out_pp_out_irq_handler(int irq, void *dev_id) +{ + vout_data *vout = dev_id; + int index; + unsigned long timeout; + u32 lock_flags = 0; + + spin_lock_irqsave(&g_lock, lock_flags); + + if (g_pp_out_number % 2 == 1) { + if (ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, 1) + < 0) { + dev_err(vout->video_dev->dev, + "unable to set IPU buffer ready\n"); + } + } else { + if (vout->ipu_buf[0] != -1) { + vout->v4l2_bufs[vout->ipu_buf[0]].flags = + V4L2_BUF_FLAG_DONE; + queue_buf(&vout->done_q, vout->ipu_buf[0]); + wake_up_interruptible(&vout->v4l_bufq); + vout->ipu_buf[0] = -1; + } + if (vout->state == STATE_STREAM_STOPPING) { + if ((vout->ipu_buf[0] == -1) + && (vout->ipu_buf[1] == -1)) + vout->state = STATE_STREAM_OFF; + } else if ((vout->state == STATE_STREAM_PAUSED) + && ((index = peek_next_buf(&vout->ready_q)) != -1)) { + /*! + * Setup timer for next buffer, + * when stream has been paused + */ + pr_debug("next index %d\n", index); + + /* if timestamp is 0, then default to 30fps */ + if ((vout->v4l2_bufs[index].timestamp.tv_sec == 0) + && (vout->v4l2_bufs[index].timestamp.tv_usec == 0)) + timeout = + vout->start_jiffies + + vout->frame_count * HZ / 30; + else + timeout = + get_jiffies(&vout->v4l2_bufs[index]. + timestamp); + + if (jiffies >= timeout) { + pr_debug + ("warning: timer timeout" + "already expired.\n"); + } + + vout->state = STATE_STREAM_ON; + + if (mod_timer(&vout->output_timer, timeout)) + pr_debug("warning: timer was already set\n"); + + pr_debug("timer handler next schedule: %lu\n", timeout); + } + } + g_pp_out_number++; + + spin_unlock_irqrestore(&g_lock, lock_flags); + return IRQ_HANDLED; +} + +/*! + * Start the output stream + * + * @param vout structure vout_data * + * + * @return status 0 Success + */ +static int mxc_v4l2out_streamon(vout_data *vout) +{ + struct device *dev = vout->video_dev->dev; + ipu_channel_params_t params; + struct mxcfb_pos fb_pos; + struct fb_var_screeninfo fbvar; + struct fb_info *fbi = + registered_fb[vout->output_fb_num[vout->cur_disp_output]]; + int pp_in_buf[2]; + u16 out_width; + u16 out_height; + ipu_channel_t display_input_ch = MEM_PP_MEM; + bool use_direct_adc = false; + mm_segment_t old_fs; + + if (!vout) + return -EINVAL; + + if (vout->state != STATE_STREAM_OFF) + return -EBUSY; + + if (queue_size(&vout->ready_q) < 2) { + dev_err(dev, "2 buffers not been queued yet!\n"); + return -EINVAL; + } + + out_width = vout->crop_current.width; + out_height = vout->crop_current.height; + + vout->next_done_ipu_buf = vout->next_rdy_ipu_buf = 0; + vout->ipu_buf[0] = pp_in_buf[0] = dequeue_buf(&vout->ready_q); + vout->ipu_buf[1] = pp_in_buf[1] = vout->ipu_buf[0]; + vout->frame_count = 1; + g_pp_out_number = 1; + g_pp_in_number = 1; + + ipu_enable_irq(IPU_IRQ_PP_IN_EOF); + ipu_enable_irq(IPU_IRQ_PP_OUT_EOF); + + /* Init Display Channel */ +#ifdef CONFIG_FB_MXC_ASYNC_PANEL + if (vout->cur_disp_output < DISP3) { + mxcfb_set_refresh_mode(fbi, MXCFB_REFRESH_OFF, 0); + fbi = NULL; + if (ipu_can_rotate_in_place(vout->rotate)) { + dev_dbg(dev, "Using PP direct to ADC channel\n"); + use_direct_adc = true; + vout->display_ch = MEM_PP_ADC; + vout->post_proc_ch = MEM_PP_ADC; + + memset(¶ms, 0, sizeof(params)); + params.mem_pp_adc.in_width = vout->v2f.fmt.pix.width; + params.mem_pp_adc.in_height = vout->v2f.fmt.pix.height; + params.mem_pp_adc.in_pixel_fmt = + vout->v2f.fmt.pix.pixelformat; + params.mem_pp_adc.out_width = out_width; + params.mem_pp_adc.out_height = out_height; + params.mem_pp_adc.out_pixel_fmt = SDC_FG_FB_FORMAT; +#ifdef CONFIG_FB_MXC_EPSON_PANEL + params.mem_pp_adc.out_left = + 2 + vout->crop_current.left; +#else + params.mem_pp_adc.out_left = + 12 + vout->crop_current.left; +#endif + params.mem_pp_adc.out_top = vout->crop_current.top; + if (ipu_init_channel( + vout->post_proc_ch, ¶ms) != 0) { + dev_err(dev, "Error initializing PP chan\n"); + return -EINVAL; + } + + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_INPUT_BUFFER, + params.mem_pp_adc. + in_pixel_fmt, + params.mem_pp_adc.in_width, + params.mem_pp_adc.in_height, + vout->v2f.fmt.pix. + bytesperline / + bytes_per_pixel(params. + mem_pp_adc. + in_pixel_fmt), + vout->rotate, + vout-> + v4l2_bufs[pp_in_buf[0]].m. + offset, + vout-> + v4l2_bufs[pp_in_buf[1]].m. + offset, + vout->offset.u_offset, + vout->offset.v_offset) != + 0) { + dev_err(dev, "Error initializing PP in buf\n"); + return -EINVAL; + } + + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_OUTPUT_BUFFER, + params.mem_pp_adc. + out_pixel_fmt, out_width, + out_height, out_width, + vout->rotate, 0, 0, 0, + 0) != 0) { + dev_err(dev, + "Error initializing PP" + "output buffer\n"); + return -EINVAL; + } + + } else { + dev_dbg(dev, "Using ADC SYS2 channel\n"); + vout->display_ch = ADC_SYS2; + vout->post_proc_ch = MEM_PP_MEM; + + if (vout->display_bufs[0]) { + mxc_free_buffers(vout->display_bufs, + vout->display_bufs_vaddr, + 2, vout->display_buf_size); + } + + vout->display_buf_size = vout->crop_current.width * + vout->crop_current.height * + fmt_to_bpp(SDC_FG_FB_FORMAT) / 8; + mxc_allocate_buffers(vout->display_bufs, + vout->display_bufs_vaddr, + 2, vout->display_buf_size); + + memset(¶ms, 0, sizeof(params)); + params.adc_sys2.disp = vout->cur_disp_output; + params.adc_sys2.ch_mode = WriteTemplateNonSeq; +#ifdef CONFIG_FB_MXC_EPSON_PANEL + params.adc_sys2.out_left = 2 + vout->crop_current.left; +#else + params.adc_sys2.out_left = 12 + vout->crop_current.left; +#endif + params.adc_sys2.out_top = vout->crop_current.top; + if (ipu_init_channel(ADC_SYS2, ¶ms) < 0) + return -EINVAL; + + if (ipu_init_channel_buffer(vout->display_ch, + IPU_INPUT_BUFFER, + SDC_FG_FB_FORMAT, + out_width, out_height, + out_width, IPU_ROTATE_NONE, + vout->display_bufs[0], + vout->display_bufs[1], 0, + 0) != 0) { + dev_err(dev, + "Error initializing SDC FG buffer\n"); + return -EINVAL; + } + } + } else +#endif + { /* Use SDC */ + dev_dbg(dev, "Using SDC channel\n"); + + fbvar = fbi->var; + if (vout->cur_disp_output == 3) { + vout->display_ch = MEM_FG_SYNC; + fbvar.bits_per_pixel = 16; + fbvar.nonstd = IPU_PIX_FMT_UYVY; + + fbvar.xres = fbvar.xres_virtual = out_width; + fbvar.yres = out_height; + fbvar.yres_virtual = out_height * 2; + } else if (vout->cur_disp_output == 5) { + vout->display_ch = MEM_DC_SYNC; + fbvar.bits_per_pixel = 16; + fbvar.nonstd = IPU_PIX_FMT_UYVY; + + fbvar.xres = fbvar.xres_virtual = out_width; + fbvar.yres = out_height; + fbvar.yres_virtual = out_height * 2; + } else { + vout->display_ch = MEM_BG_SYNC; + } + + fbvar.activate |= FB_ACTIVATE_FORCE; + fb_set_var(fbi, &fbvar); + + fb_pos.x = vout->crop_current.left; + fb_pos.y = vout->crop_current.top; + if (fbi->fbops->fb_ioctl) { + old_fs = get_fs(); + set_fs(KERNEL_DS); + fbi->fbops->fb_ioctl(fbi, MXCFB_SET_OVERLAY_POS, + (unsigned long)&fb_pos); + set_fs(old_fs); + } + + vout->display_bufs[1] = fbi->fix.smem_start; + vout->display_bufs[0] = fbi->fix.smem_start + + (fbi->fix.line_length * fbi->var.yres); + vout->display_buf_size = vout->crop_current.width * + vout->crop_current.height * fbi->var.bits_per_pixel / 8; + + vout->post_proc_ch = MEM_PP_MEM; + } + + /* Init PP */ + if (use_direct_adc == false) { + if (vout->rotate >= IPU_ROTATE_90_RIGHT) { + out_width = vout->crop_current.height; + out_height = vout->crop_current.width; + } + memset(¶ms, 0, sizeof(params)); + params.mem_pp_mem.in_width = vout->v2f.fmt.pix.width / 2; + params.mem_pp_mem.in_height = vout->v2f.fmt.pix.height; + params.mem_pp_mem.in_pixel_fmt = vout->v2f.fmt.pix.pixelformat; + params.mem_pp_mem.out_width = out_width / 2; + params.mem_pp_mem.out_height = out_height; + if (vout->display_ch == ADC_SYS2) + params.mem_pp_mem.out_pixel_fmt = SDC_FG_FB_FORMAT; + else + params.mem_pp_mem.out_pixel_fmt = bpp_to_fmt(fbi); + if (ipu_init_channel(vout->post_proc_ch, ¶ms) != 0) { + dev_err(dev, "Error initializing PP channel\n"); + return -EINVAL; + } + + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_INPUT_BUFFER, + params.mem_pp_mem.in_pixel_fmt, + params.mem_pp_mem.in_width, + params.mem_pp_mem.in_height, + vout->v2f.fmt.pix.bytesperline / + bytes_per_pixel(params.mem_pp_mem. + in_pixel_fmt), + IPU_ROTATE_NONE, + vout->v4l2_bufs[pp_in_buf[0]].m. + offset, + vout->v4l2_bufs[pp_in_buf[0]].m. + offset + params.mem_pp_mem.in_width, + vout->offset.u_offset, + vout->offset.v_offset) != 0) { + dev_err(dev, "Error initializing PP input buffer\n"); + return -EINVAL; + } + + if (!ipu_can_rotate_in_place(vout->rotate)) { + if (vout->rot_pp_bufs[0]) { + mxc_free_buffers(vout->rot_pp_bufs, + vout->rot_pp_bufs_vaddr, 2, + vout->display_buf_size); + } + if (mxc_allocate_buffers + (vout->rot_pp_bufs, vout->rot_pp_bufs_vaddr, 2, + vout->display_buf_size) < 0) + return -ENOBUFS; + + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_OUTPUT_BUFFER, + params.mem_pp_mem. + out_pixel_fmt, out_width, + out_height, out_width, + IPU_ROTATE_NONE, + vout->rot_pp_bufs[0], + vout->rot_pp_bufs[1], 0, + 0) != 0) { + dev_err(dev, + "Error initializing" + "PP output buffer\n"); + return -EINVAL; + } + + if (ipu_init_channel(MEM_ROT_PP_MEM, NULL) != 0) { + dev_err(dev, + "Error initializing PP ROT channel\n"); + return -EINVAL; + } + + if (ipu_init_channel_buffer(MEM_ROT_PP_MEM, + IPU_INPUT_BUFFER, + params.mem_pp_mem. + out_pixel_fmt, out_width, + out_height, out_width, + vout->rotate, + vout->rot_pp_bufs[0], + vout->rot_pp_bufs[1], 0, + 0) != 0) { + dev_err(dev, + "Error initializing PP ROT" + "input buffer\n"); + return -EINVAL; + } + + /* swap width and height */ + if (vout->rotate >= IPU_ROTATE_90_RIGHT) { + out_width = vout->crop_current.width; + out_height = vout->crop_current.height; + } + + if (ipu_init_channel_buffer(MEM_ROT_PP_MEM, + IPU_OUTPUT_BUFFER, + params.mem_pp_mem. + out_pixel_fmt, out_width, + out_height, out_width, + IPU_ROTATE_NONE, + vout->display_bufs[0], + vout->display_bufs[1], 0, + 0) != 0) { + dev_err(dev, + "Error initializing PP" + "output buffer\n"); + return -EINVAL; + } + + if (ipu_link_channels(vout->post_proc_ch, + MEM_ROT_PP_MEM) < 0) + return -EINVAL; + + ipu_select_buffer(MEM_ROT_PP_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(MEM_ROT_PP_MEM, IPU_OUTPUT_BUFFER, 1); + + ipu_enable_channel(MEM_ROT_PP_MEM); + + display_input_ch = MEM_ROT_PP_MEM; + } else { + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_OUTPUT_BUFFER, + params.mem_pp_mem. + out_pixel_fmt, + out_width / 2, + out_height, + out_width, + vout->rotate, + vout->display_bufs[0], + vout->display_bufs[0] + + + out_width / 2 * + bytes_per_pixel + (SDC_FG_FB_FORMAT), 0, + 0) != 0) { + dev_err(dev, + "Error initializing PP" + "output buffer\n"); + return -EINVAL; + } + } + if (ipu_unlink_channels( + display_input_ch, vout->display_ch) < 0) { + dev_err(dev, "Error linking ipu channels\n"); + return -EINVAL; + } + } + + vout->state = STATE_STREAM_PAUSED; + + ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 0); + + if (use_direct_adc == false) { + ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, 0); + ipu_enable_channel(vout->post_proc_ch); + + if (fbi) { + acquire_console_sem(); + fb_blank(fbi, FB_BLANK_UNBLANK); + release_console_sem(); + } else { + ipu_enable_channel(vout->display_ch); + } + } else { + ipu_enable_channel(vout->post_proc_ch); + } + + vout->start_jiffies = jiffies; + dev_dbg(dev, + "streamon: start time = %lu jiffies\n", vout->start_jiffies); + + return 0; +} + +/*! + * Shut down the voutera + * + * @param vout structure vout_data * + * + * @return status 0 Success + */ +static int mxc_v4l2out_streamoff(vout_data *vout) +{ + struct fb_info *fbi = + registered_fb[vout->output_fb_num[vout->cur_disp_output]]; + int i, retval = 0; + unsigned long lockflag = 0; + + if (!vout) + return -EINVAL; + + if (vout->state == STATE_STREAM_OFF) + return 0; + + spin_lock_irqsave(&g_lock, lockflag); + + del_timer(&vout->output_timer); + + if (vout->state == STATE_STREAM_ON) + vout->state = STATE_STREAM_STOPPING; + + ipu_disable_irq(IPU_IRQ_PP_IN_EOF); + ipu_disable_irq(IPU_IRQ_PP_OUT_EOF); + + spin_unlock_irqrestore(&g_lock, lockflag); + + if (vout->post_proc_ch == MEM_PP_MEM) { /* SDC or ADC with Rotation */ + if (!ipu_can_rotate_in_place(vout->rotate)) { + ipu_unlink_channels(MEM_PP_MEM, MEM_ROT_PP_MEM); + ipu_unlink_channels(MEM_ROT_PP_MEM, vout->display_ch); + ipu_disable_channel(MEM_ROT_PP_MEM, true); + + if (vout->rot_pp_bufs[0]) { + mxc_free_buffers(vout->rot_pp_bufs, + vout->rot_pp_bufs_vaddr, 2, + vout->display_buf_size); + } + } else { + ipu_unlink_channels(MEM_PP_MEM, vout->display_ch); + } + ipu_disable_channel(MEM_PP_MEM, true); + + if (vout->display_ch == ADC_SYS2) { + ipu_disable_channel(vout->display_ch, true); + ipu_uninit_channel(vout->display_ch); + } else { + fbi->var.activate |= FB_ACTIVATE_FORCE; + fb_set_var(fbi, &fbi->var); + + if (vout->display_ch == MEM_FG_SYNC) { + acquire_console_sem(); + fb_blank(fbi, FB_BLANK_POWERDOWN); + release_console_sem(); + } + + vout->display_bufs[0] = 0; + vout->display_bufs[1] = 0; + } + + ipu_uninit_channel(MEM_PP_MEM); + if (!ipu_can_rotate_in_place(vout->rotate)) + ipu_uninit_channel(MEM_ROT_PP_MEM); + } else { /* ADC Direct */ + ipu_disable_channel(MEM_PP_ADC, true); + ipu_uninit_channel(MEM_PP_ADC); + } + vout->ready_q.head = vout->ready_q.tail = 0; + vout->done_q.head = vout->done_q.tail = 0; + for (i = 0; i < vout->buffer_cnt; i++) { + vout->v4l2_bufs[i].flags = 0; + vout->v4l2_bufs[i].timestamp.tv_sec = 0; + vout->v4l2_bufs[i].timestamp.tv_usec = 0; + } + + vout->state = STATE_STREAM_OFF; + +#ifdef CONFIG_FB_MXC_ASYNC_PANEL + if (vout->cur_disp_output < DISP3) { + if (vout->display_bufs[0] != 0) { + mxc_free_buffers(vout->display_bufs, + vout->display_bufs_vaddr, 2, + vout->display_buf_size); + } + + mxcfb_set_refresh_mode(registered_fb + [vout-> + output_fb_num[vout->cur_disp_output]], + MXCFB_REFRESH_PARTIAL, 0); + } +#endif + + return retval; +} + +/* + * Valid whether the palette is supported + * + * @param palette V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32 + * + * @return 1 if supported, 0 if failed + */ +static inline int valid_mode(u32 palette) +{ + return ((palette == V4L2_PIX_FMT_RGB565) || + (palette == V4L2_PIX_FMT_BGR24) || + (palette == V4L2_PIX_FMT_RGB24) || + (palette == V4L2_PIX_FMT_BGR32) || + (palette == V4L2_PIX_FMT_RGB32) || + (palette == V4L2_PIX_FMT_NV12) || + (palette == V4L2_PIX_FMT_YUV422P) || + (palette == V4L2_PIX_FMT_YUV420)); +} + +/* + * V4L2 - Handles VIDIOC_G_FMT Ioctl + * + * @param vout structure vout_data * + * + * @param v4l2_format structure v4l2_format * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2out_g_fmt(vout_data *vout, struct v4l2_format *f) +{ + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) + return -EINVAL; + *f = vout->v2f; + return 0; +} + +/* + * V4L2 - Handles VIDIOC_S_FMT Ioctl + * + * @param vout structure vout_data * + * + * @param v4l2_format structure v4l2_format * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2out_s_fmt(vout_data *vout, struct v4l2_format *f) +{ + int retval = 0; + u32 size = 0; + u32 bytesperline; + + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + goto err0; + } + if (!valid_mode(f->fmt.pix.pixelformat)) { + dev_err(vout->video_dev->dev, "pixel format not supported\n"); + retval = -EINVAL; + goto err0; + } + + bytesperline = (f->fmt.pix.width * fmt_to_bpp(f->fmt.pix.pixelformat)) / + 8; + if (f->fmt.pix.bytesperline < bytesperline) { + f->fmt.pix.bytesperline = bytesperline; + } else { + bytesperline = f->fmt.pix.bytesperline; + } + + switch (f->fmt.pix.pixelformat) { + case V4L2_PIX_FMT_YUV422P: + /* byteperline for YUV planar formats is for + Y plane only */ + size = bytesperline * f->fmt.pix.height * 2; + break; + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_NV12: + size = (bytesperline * f->fmt.pix.height * 3) / 2; + break; + default: + size = bytesperline * f->fmt.pix.height; + break; + } + + /* Return the actual size of the image to the app */ + if (f->fmt.pix.sizeimage < size) + f->fmt.pix.sizeimage = size; + else + size = f->fmt.pix.sizeimage; + + vout->v2f.fmt.pix = f->fmt.pix; + if (vout->v2f.fmt.pix.priv != 0) { + if (copy_from_user(&vout->offset, + (void *)vout->v2f.fmt.pix.priv, + sizeof(vout->offset))) { + retval = -EFAULT; + goto err0; + } + } else { + vout->offset.u_offset = 0; + vout->offset.v_offset = 0; + } + + retval = 0; +err0: + return retval; +} + +/* + * V4L2 - Handles VIDIOC_G_CTRL Ioctl + * + * @param vout structure vout_data * + * + * @param c structure v4l2_control * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_get_v42lout_control(vout_data *vout, struct v4l2_control *c) +{ + switch (c->id) { + case V4L2_CID_HFLIP: + return (vout->rotate & IPU_ROTATE_HORIZ_FLIP) ? 1 : 0; + case V4L2_CID_VFLIP: + return (vout->rotate & IPU_ROTATE_VERT_FLIP) ? 1 : 0; + case (V4L2_CID_PRIVATE_BASE + 1): + return vout->rotate; + default: + return -EINVAL; + } +} + +/* + * V4L2 - Handles VIDIOC_S_CTRL Ioctl + * + * @param vout structure vout_data * + * + * @param c structure v4l2_control * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_set_v42lout_control(vout_data *vout, struct v4l2_control *c) +{ + switch (c->id) { + case V4L2_CID_HFLIP: + vout->rotate |= c->value ? IPU_ROTATE_HORIZ_FLIP : + IPU_ROTATE_NONE; + break; + case V4L2_CID_VFLIP: + vout->rotate |= c->value ? IPU_ROTATE_VERT_FLIP : + IPU_ROTATE_NONE; + break; + case V4L2_CID_MXC_ROT: + vout->rotate = c->value; + break; + default: + return -EINVAL; + } + return 0; +} + +/*! + * V4L2 interface - open function + * + * @param inode structure inode * + * + * @param file structure file * + * + * @return status 0 success, ENODEV invalid device instance, + * ENODEV timeout, ERESTARTSYS interrupted by user + */ +static int mxc_v4l2out_open(struct inode *inode, struct file *file) +{ + struct video_device *dev = video_devdata(file); + vout_data *vout = video_get_drvdata(dev); + int err; + + if (!vout) + return -ENODEV; + + down(&vout->busy_lock); + + err = -EINTR; + if (signal_pending(current)) + goto oops; + + if (vout->open_count++ == 0) { + ipu_request_irq(IPU_IRQ_PP_IN_EOF, + mxc_v4l2out_pp_in_irq_handler, + 0, dev->name, vout); + ipu_request_irq(IPU_IRQ_PP_OUT_EOF, + mxc_v4l2out_pp_out_irq_handler, + 0, dev->name, vout); + + init_waitqueue_head(&vout->v4l_bufq); + + init_timer(&vout->output_timer); + vout->output_timer.function = mxc_v4l2out_timer_handler; + vout->output_timer.data = (unsigned long)vout; + + vout->state = STATE_STREAM_OFF; + vout->rotate = IPU_ROTATE_NONE; + g_irq_cnt = g_buf_output_cnt = g_buf_q_cnt = g_buf_dq_cnt = 0; + + } + + file->private_data = dev; + + up(&vout->busy_lock); + + return 0; + +oops: + up(&vout->busy_lock); + return err; +} + +/*! + * V4L2 interface - close function + * + * @param inode struct inode * + * + * @param file struct file * + * + * @return 0 success + */ +static int mxc_v4l2out_close(struct inode *inode, struct file *file) +{ + struct video_device *dev = video_devdata(file); + vout_data *vout = video_get_drvdata(dev); + + if (--vout->open_count == 0) { + if (vout->state != STATE_STREAM_OFF) + mxc_v4l2out_streamoff(vout); + + ipu_free_irq(IPU_IRQ_PP_IN_EOF, vout); + ipu_free_irq(IPU_IRQ_PP_OUT_EOF, vout); + + file->private_data = NULL; + + mxc_free_buffers(vout->queue_buf_paddr, vout->queue_buf_vaddr, + vout->buffer_cnt, vout->queue_buf_size); + vout->buffer_cnt = 0; + mxc_free_buffers(vout->rot_pp_bufs, vout->rot_pp_bufs_vaddr, 2, + vout->display_buf_size); + + /* capture off */ + wake_up_interruptible(&vout->v4l_bufq); + } + + return 0; +} + +/*! + * V4L2 interface - ioctl function + * + * @param inode struct inode * + * + * @param file struct file * + * + * @param ioctlnr unsigned int + * + * @param arg void * + * + * @return 0 success, ENODEV for invalid device instance, + * -1 for other errors. + */ +static int +mxc_v4l2out_do_ioctl(struct inode *inode, struct file *file, + unsigned int ioctlnr, void *arg) +{ + struct video_device *vdev = file->private_data; + vout_data *vout = video_get_drvdata(vdev); + int retval = 0; + int i = 0; + + if (!vout) + return -EBADF; + + /* make this _really_ smp-safe */ + if (down_interruptible(&vout->busy_lock)) + return -EBUSY; + + switch (ioctlnr) { + case VIDIOC_QUERYCAP: + { + struct v4l2_capability *cap = arg; + strcpy(cap->driver, "mxc_v4l2_output"); + cap->version = 0; + cap->capabilities = + V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING; + cap->card[0] = '\0'; + cap->bus_info[0] = '\0'; + retval = 0; + break; + } + case VIDIOC_G_FMT: + { + struct v4l2_format *gf = arg; + retval = mxc_v4l2out_g_fmt(vout, gf); + break; + } + case VIDIOC_S_FMT: + { + struct v4l2_format *sf = arg; + if (vout->state != STATE_STREAM_OFF) { + retval = -EBUSY; + break; + } + retval = mxc_v4l2out_s_fmt(vout, sf); + break; + } + case VIDIOC_REQBUFS: + { + struct v4l2_requestbuffers *req = arg; + if ((req->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) || + (req->memory != V4L2_MEMORY_MMAP)) { + dev_dbg(vdev->dev, + "VIDIOC_REQBUFS: incorrect" + "buffer type\n"); + retval = -EINVAL; + break; + } + + if (req->count == 0) + mxc_v4l2out_streamoff(vout); + + if (vout->state == STATE_STREAM_OFF) { + if (vout->queue_buf_paddr[0] != 0) { + mxc_free_buffers(vout->queue_buf_paddr, + vout->queue_buf_vaddr, + vout->buffer_cnt, + vout->queue_buf_size); + dev_dbg(vdev->dev, + "VIDIOC_REQBUFS:" + "freed buffers\n"); + } + vout->buffer_cnt = 0; + } else { + dev_dbg(vdev->dev, + "VIDIOC_REQBUFS: Buffer is in use\n"); + retval = -EBUSY; + break; + } + + if (req->count == 0) + break; + + if (req->count < MIN_FRAME_NUM) + req->count = MIN_FRAME_NUM; + else if (req->count > MAX_FRAME_NUM) + req->count = MAX_FRAME_NUM; + vout->buffer_cnt = req->count; + vout->queue_buf_size = + PAGE_ALIGN(vout->v2f.fmt.pix.sizeimage); + + retval = mxc_allocate_buffers(vout->queue_buf_paddr, + vout->queue_buf_vaddr, + vout->buffer_cnt, + vout->queue_buf_size); + if (retval < 0) + break; + + /* Init buffer queues */ + vout->done_q.head = 0; + vout->done_q.tail = 0; + vout->ready_q.head = 0; + vout->ready_q.tail = 0; + + for (i = 0; i < vout->buffer_cnt; i++) { + memset(&(vout->v4l2_bufs[i]), 0, + sizeof(vout->v4l2_bufs[i])); + vout->v4l2_bufs[i].flags = 0; + vout->v4l2_bufs[i].memory = V4L2_MEMORY_MMAP; + vout->v4l2_bufs[i].index = i; + vout->v4l2_bufs[i].type = + V4L2_BUF_TYPE_VIDEO_OUTPUT; + vout->v4l2_bufs[i].length = + PAGE_ALIGN(vout->v2f.fmt.pix.sizeimage); + vout->v4l2_bufs[i].m.offset = + (unsigned long)vout->queue_buf_paddr[i]; + vout->v4l2_bufs[i].timestamp.tv_sec = 0; + vout->v4l2_bufs[i].timestamp.tv_usec = 0; + } + break; + } + case VIDIOC_QUERYBUF: + { + struct v4l2_buffer *buf = arg; + u32 type = buf->type; + int index = buf->index; + + if ((type != V4L2_BUF_TYPE_VIDEO_OUTPUT) || + (index >= vout->buffer_cnt)) { + dev_dbg(vdev->dev, + "VIDIOC_QUERYBUFS: incorrect" + "buffer type\n"); + retval = -EINVAL; + break; + } + down(&vout->param_lock); + memcpy(buf, &(vout->v4l2_bufs[index]), sizeof(*buf)); + up(&vout->param_lock); + break; + } + case VIDIOC_QBUF: + { + struct v4l2_buffer *buf = arg; + int index = buf->index; + unsigned long lock_flags; + + if ((buf->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) || + (index >= vout->buffer_cnt)) { + retval = -EINVAL; + break; + } + + dev_dbg(vdev->dev, "VIDIOC_QBUF: %d\n", buf->index); + + /* mmapped buffers are L1 WB cached, + * so we need to clean them */ + if (buf->flags & V4L2_BUF_FLAG_MAPPED) + flush_cache_all(); + + spin_lock_irqsave(&g_lock, lock_flags); + + memcpy(&(vout->v4l2_bufs[index]), buf, sizeof(*buf)); + vout->v4l2_bufs[index].flags |= V4L2_BUF_FLAG_QUEUED; + + g_buf_q_cnt++; + queue_buf(&vout->ready_q, index); + if (vout->state == STATE_STREAM_PAUSED) { + unsigned long timeout; + + index = peek_next_buf(&vout->ready_q); + + /* if timestamp is 0, then default to 30fps */ + if ((vout->v4l2_bufs[index].timestamp.tv_sec == + 0) + && (vout->v4l2_bufs[index].timestamp. + tv_usec == 0)) + timeout = + vout->start_jiffies + + vout->frame_count * HZ / 30; + else + timeout = + get_jiffies(&vout->v4l2_bufs[index]. + timestamp); + + if (jiffies >= timeout) { + dev_dbg(vout->video_dev->dev, + "warning: timer timeout" + "already expired.\n"); + } + vout->output_timer.expires = timeout; + dev_dbg(vdev->dev, + "QBUF: frame #%u timeout @" + " %lu jiffies, current = %lu\n", + vout->frame_count, timeout, jiffies); + add_timer(&vout->output_timer); + vout->state = STATE_STREAM_ON; + } + + spin_unlock_irqrestore(&g_lock, lock_flags); + break; + } + case VIDIOC_DQBUF: + { + struct v4l2_buffer *buf = arg; + int idx; + + if ((queue_size(&vout->done_q) == 0) && + (file->f_flags & O_NONBLOCK)) { + retval = -EAGAIN; + break; + } + + if (!wait_event_interruptible_timeout(vout->v4l_bufq, + queue_size(&vout-> + done_q) + != 0, 10 * HZ)) { + dev_dbg(vdev->dev, "VIDIOC_DQBUF: timeout\n"); + retval = -ETIME; + break; + } else if (signal_pending(current)) { + dev_dbg(vdev->dev, + "VIDIOC_DQBUF: interrupt received\n"); + retval = -ERESTARTSYS; + break; + } + idx = dequeue_buf(&vout->done_q); + if (idx == -1) { /* No frame free */ + dev_dbg(vdev->dev, + "VIDIOC_DQBUF: no free buffers\n"); + retval = -EAGAIN; + break; + } + if ((vout->v4l2_bufs[idx].flags & V4L2_BUF_FLAG_DONE) == + 0) + dev_dbg(vdev->dev, + "VIDIOC_DQBUF: buffer in done q, " + "but not flagged as done\n"); + + vout->v4l2_bufs[idx].flags = 0; + memcpy(buf, &(vout->v4l2_bufs[idx]), sizeof(*buf)); + dev_dbg(vdev->dev, "VIDIOC_DQBUF: %d\n", buf->index); + break; + } + case VIDIOC_STREAMON: + { + retval = mxc_v4l2out_streamon(vout); + break; + } + case VIDIOC_STREAMOFF: + { + retval = mxc_v4l2out_streamoff(vout); + break; + } + case VIDIOC_G_CTRL: + { + retval = mxc_get_v42lout_control(vout, arg); + break; + } + case VIDIOC_S_CTRL: + { + retval = mxc_set_v42lout_control(vout, arg); + break; + } + case VIDIOC_CROPCAP: + { + struct v4l2_cropcap *cap = arg; + + if (cap->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + break; + } + + cap->bounds = vout->crop_bounds[vout->cur_disp_output]; + cap->defrect = vout->crop_bounds[vout->cur_disp_output]; + retval = 0; + break; + } + case VIDIOC_G_CROP: + { + struct v4l2_crop *crop = arg; + + if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + break; + } + crop->c = vout->crop_current; + break; + } + case VIDIOC_S_CROP: + { + struct v4l2_crop *crop = arg; + struct v4l2_rect *b = + &(vout->crop_bounds[vout->cur_disp_output]); + + if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + break; + } + if (crop->c.height < 0) { + retval = -EINVAL; + break; + } + if (crop->c.width < 0) { + retval = -EINVAL; + break; + } + + /* only full screen supported for SDC BG */ + if (vout->cur_disp_output == 4) { + crop->c = vout->crop_current; + break; + } + + if (crop->c.top < b->top) + crop->c.top = b->top; + if (crop->c.top >= b->top + b->height) + crop->c.top = b->top + b->height - 1; + if (crop->c.height > b->top - crop->c.top + b->height) + crop->c.height = + b->top - crop->c.top + b->height; + + if (crop->c.left < b->left) + crop->c.left = b->left; + if (crop->c.left >= b->left + b->width) + crop->c.left = b->left + b->width - 1; + if (crop->c.width > b->left - crop->c.left + b->width) + crop->c.width = + b->left - crop->c.left + b->width; + + /* stride line limitation */ + crop->c.height -= crop->c.height % 8; + crop->c.width -= crop->c.width % 8; + + vout->crop_current = crop->c; + break; + } + case VIDIOC_ENUMOUTPUT: + { + struct v4l2_output *output = arg; + + if ((output->index >= 5) || + (vout->output_enabled[output->index] == false)) { + retval = -EINVAL; + break; + } + + if (output->index < 3) { + *output = mxc_outputs[MXC_V4L2_OUT_2_ADC]; + output->name[4] = '0' + output->index; + } else { + *output = mxc_outputs[MXC_V4L2_OUT_2_SDC]; + } + break; + } + case VIDIOC_G_OUTPUT: + { + int *p_output_num = arg; + + *p_output_num = vout->cur_disp_output; + break; + } + case VIDIOC_S_OUTPUT: + { + int *p_output_num = arg; + int fbnum; + struct v4l2_rect *b; + + if ((*p_output_num >= MXC_V4L2_OUT_NUM_OUTPUTS) || + (vout->output_enabled[*p_output_num] == false)) { + retval = -EINVAL; + break; + } + + if (vout->state != STATE_STREAM_OFF) { + retval = -EBUSY; + break; + } + + vout->cur_disp_output = *p_output_num; + + /* Update bounds in case they have changed */ + b = &vout->crop_bounds[vout->cur_disp_output]; + + fbnum = vout->output_fb_num[vout->cur_disp_output]; + if (vout->cur_disp_output == 3) + fbnum = vout->output_fb_num[4]; + + b->width = registered_fb[fbnum]->var.xres; + b->height = registered_fb[fbnum]->var.yres; + + vout->crop_current = *b; + break; + } + case VIDIOC_ENUM_FMT: + case VIDIOC_TRY_FMT: + case VIDIOC_QUERYCTRL: + case VIDIOC_G_PARM: + case VIDIOC_ENUMSTD: + case VIDIOC_G_STD: + case VIDIOC_S_STD: + case VIDIOC_G_TUNER: + case VIDIOC_S_TUNER: + case VIDIOC_G_FREQUENCY: + case VIDIOC_S_FREQUENCY: + default: + retval = -EINVAL; + break; + } + + up(&vout->busy_lock); + return retval; +} + +/* + * V4L2 interface - ioctl function + * + * @return None + */ +static int +mxc_v4l2out_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + return video_usercopy(inode, file, cmd, arg, mxc_v4l2out_do_ioctl); +} + +/*! + * V4L2 interface - mmap function + * + * @param file structure file * + * + * @param vma structure vm_area_struct * + * + * @return status 0 Success, EINTR busy lock error, + * ENOBUFS remap_page error + */ +static int mxc_v4l2out_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct video_device *vdev = video_devdata(file); + unsigned long size = vma->vm_end - vma->vm_start; + int res = 0; + int i; + vout_data *vout = video_get_drvdata(vdev); + + dev_dbg(vdev->dev, "pgoff=0x%lx, start=0x%lx, end=0x%lx\n", + vma->vm_pgoff, vma->vm_start, vma->vm_end); + + /* make this _really_ smp-safe */ + if (down_interruptible(&vout->busy_lock)) + return -EINTR; + + for (i = 0; i < vout->buffer_cnt; i++) { + if ((vout->v4l2_bufs[i].m.offset == + (vma->vm_pgoff << PAGE_SHIFT)) && + (vout->v4l2_bufs[i].length >= size)) { + vout->v4l2_bufs[i].flags |= V4L2_BUF_FLAG_MAPPED; + break; + } + } + if (i == vout->buffer_cnt) { + res = -ENOBUFS; + goto mxc_mmap_exit; + } + + /* make buffers inner write-back, outer write-thru cacheable */ + vma->vm_page_prot = pgprot_outer_wrthru(vma->vm_page_prot); + + if (remap_pfn_range(vma, vma->vm_start, + vma->vm_pgoff, size, vma->vm_page_prot)) { + dev_dbg(vdev->dev, "mmap remap_pfn_range failed\n"); + res = -ENOBUFS; + goto mxc_mmap_exit; + } + + vma->vm_flags &= ~VM_IO; /* using shared anonymous pages */ + +mxc_mmap_exit: + up(&vout->busy_lock); + return res; +} + +/*! + * V4L2 interface - poll function + * + * @param file structure file * + * + * @param wait structure poll_table * + * + * @return status POLLIN | POLLRDNORM + */ +static unsigned int mxc_v4l2out_poll(struct file *file, poll_table * wait) +{ + struct video_device *dev = video_devdata(file); + vout_data *vout = video_get_drvdata(dev); + + wait_queue_head_t *queue = NULL; + int res = POLLIN | POLLRDNORM; + + if (down_interruptible(&vout->busy_lock)) + return -EINTR; + + queue = &vout->v4l_bufq; + poll_wait(file, queue, wait); + + up(&vout->busy_lock); + return res; +} + +static struct +file_operations mxc_v4l2out_fops = { + .owner = THIS_MODULE, + .open = mxc_v4l2out_open, + .release = mxc_v4l2out_close, + .ioctl = mxc_v4l2out_ioctl, + .mmap = mxc_v4l2out_mmap, + .poll = mxc_v4l2out_poll, +}; + +static struct video_device mxc_v4l2out_template = { + .owner = THIS_MODULE, + .name = "MXC Video Output", + .type = 0, + .type2 = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING, + .fops = &mxc_v4l2out_fops, + .release = video_device_release, +}; + +/*! + * Probe routine for the framebuffer driver. It is called during the + * driver binding process. The following functions are performed in + * this routine: Framebuffer initialization, Memory allocation and + * mapping, Framebuffer registration, IPU initialization. + * + * @return Appropriate error code to the kernel common code + */ +static int mxc_v4l2out_probe(struct platform_device *pdev) +{ + int i; + vout_data *vout; + + /* + * Allocate sufficient memory for the fb structure + */ + g_vout = vout = kmalloc(sizeof(vout_data), GFP_KERNEL); + + if (!vout) + return 0; + + memset(vout, 0, sizeof(vout_data)); + + vout->video_dev = video_device_alloc(); + if (vout->video_dev == NULL) + return -1; + vout->video_dev->dev = &pdev->dev; + vout->video_dev->minor = -1; + + *(vout->video_dev) = mxc_v4l2out_template; + + /* register v4l device */ + if (video_register_device(vout->video_dev, + VFL_TYPE_GRABBER, video_nr) == -1) { + dev_dbg(&pdev->dev, "video_register_device failed\n"); + return 0; + } + dev_info(&pdev->dev, "Registered device video%d\n", + vout->video_dev->minor & 0x1f); + vout->video_dev->dev = &pdev->dev; + + video_set_drvdata(vout->video_dev, vout); + + init_MUTEX(&vout->param_lock); + init_MUTEX(&vout->busy_lock); + + /* setup outputs and cropping */ + vout->cur_disp_output = -1; + for (i = 0; i < num_registered_fb; i++) { + char *idstr = registered_fb[i]->fix.id; + if (strncmp(idstr, "DISP", 4) == 0) { + int disp_num = idstr[4] - '0'; + if (disp_num == 3) { + if (strcmp(idstr, "DISP3 BG - DI1") == 0) + disp_num = 5; + else if (strncmp(idstr, "DISP3 BG", 8) == 0) + disp_num = 4; + } + vout->crop_bounds[disp_num].left = 0; + vout->crop_bounds[disp_num].top = 0; + vout->crop_bounds[disp_num].width = + registered_fb[i]->var.xres; + vout->crop_bounds[disp_num].height = + registered_fb[i]->var.yres; + vout->output_enabled[disp_num] = true; + vout->output_fb_num[disp_num] = i; + if (vout->cur_disp_output == -1) + vout->cur_disp_output = disp_num; + } + + } + vout->crop_current = vout->crop_bounds[vout->cur_disp_output]; + + platform_set_drvdata(pdev, vout); + + return 0; +} + +static int mxc_v4l2out_remove(struct platform_device *pdev) +{ + vout_data *vout = platform_get_drvdata(pdev); + + if (vout->video_dev) { + if (-1 != vout->video_dev->minor) + video_unregister_device(vout->video_dev); + else + video_device_release(vout->video_dev); + vout->video_dev = NULL; + } + + platform_set_drvdata(pdev, NULL); + + kfree(vout); + + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxc_v4l2out_driver = { + .driver = { + .name = "MXC Video Output", + }, + .probe = mxc_v4l2out_probe, + .remove = mxc_v4l2out_remove, +}; + +static struct platform_device mxc_v4l2out_device = { + .name = "MXC Video Output", + .id = 0, +}; + +/*! + * mxc v4l2 init function + * + */ +static int mxc_v4l2out_init(void) +{ + u8 err = 0; + + err = platform_driver_register(&mxc_v4l2out_driver); + if (err == 0) + platform_device_register(&mxc_v4l2out_device); + return err; +} + +/*! + * mxc v4l2 cleanup function + * + */ +static void mxc_v4l2out_clean(void) +{ + video_unregister_device(g_vout->video_dev); + + platform_driver_unregister(&mxc_v4l2out_driver); + platform_device_unregister(&mxc_v4l2out_device); + kfree(g_vout); + g_vout = NULL; +} + +module_init(mxc_v4l2out_init); +module_exit(mxc_v4l2out_clean); + +module_param(video_nr, int, 0444); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("V4L2-driver for MXC video output"); +MODULE_LICENSE("GPL"); +MODULE_SUPPORTED_DEVICE("video"); diff -urN linux-2.6.26/drivers/media/video/mxc/output/mxc_v4l2_output.c linux-2.6.26-lab126/drivers/media/video/mxc/output/mxc_v4l2_output.c --- linux-2.6.26/drivers/media/video/mxc/output/mxc_v4l2_output.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/output/mxc_v4l2_output.c 2010-08-10 04:15:21.000000000 -0400 @@ -0,0 +1,1884 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file drivers/media/video/mxc/output/mxc_v4l2_output.c + * + * @brief MXC V4L2 Video Output Driver + * + * Video4Linux2 Output Device using MXC IPU Post-processing functionality. + * + * @ingroup MXC_V4L2_OUTPUT + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "mxc_v4l2_output.h" + +vout_data *g_vout; +#define SDC_FG_FB_FORMAT IPU_PIX_FMT_RGB565 + +struct v4l2_output mxc_outputs[2] = { + { + .index = MXC_V4L2_OUT_2_SDC, + .name = "DISP3 Video Out", + .type = V4L2_OUTPUT_TYPE_ANALOG, /* not really correct, + but no other choice */ + .audioset = 0, + .modulator = 0, + .std = V4L2_STD_UNKNOWN}, + { + .index = MXC_V4L2_OUT_2_ADC, + .name = "DISPx Video Out", + .type = V4L2_OUTPUT_TYPE_ANALOG, /* not really correct, + but no other choice */ + .audioset = 0, + .modulator = 0, + .std = V4L2_STD_UNKNOWN} +}; + +static int video_nr = 16; +static spinlock_t g_lock = SPIN_LOCK_UNLOCKED; + +/* debug counters */ +uint32_t g_irq_cnt; +uint32_t g_buf_output_cnt; +uint32_t g_buf_q_cnt; +uint32_t g_buf_dq_cnt; + +#define QUEUE_SIZE (MAX_FRAME_NUM + 1) +static __inline int queue_size(v4l_queue * q) +{ + if (q->tail >= q->head) + return (q->tail - q->head); + else + return ((q->tail + QUEUE_SIZE) - q->head); +} + +static __inline int queue_buf(v4l_queue * q, int idx) +{ + if (((q->tail + 1) % QUEUE_SIZE) == q->head) + return -1; /* queue full */ + q->list[q->tail] = idx; + q->tail = (q->tail + 1) % QUEUE_SIZE; + return 0; +} + +static __inline int dequeue_buf(v4l_queue * q) +{ + int ret; + if (q->tail == q->head) + return -1; /* queue empty */ + ret = q->list[q->head]; + q->head = (q->head + 1) % QUEUE_SIZE; + return ret; +} + +static __inline int peek_next_buf(v4l_queue * q) +{ + if (q->tail == q->head) + return -1; /* queue empty */ + return q->list[q->head]; +} + +static __inline unsigned long get_jiffies(struct timeval *t) +{ + struct timeval cur; + + if (t->tv_usec >= 1000000) { + t->tv_sec += t->tv_usec / 1000000; + t->tv_usec = t->tv_usec % 1000000; + } + + do_gettimeofday(&cur); + if ((t->tv_sec < cur.tv_sec) + || ((t->tv_sec == cur.tv_sec) && (t->tv_usec < cur.tv_usec))) + return jiffies; + + if (t->tv_usec < cur.tv_usec) { + cur.tv_sec = t->tv_sec - cur.tv_sec - 1; + cur.tv_usec = t->tv_usec + 1000000 - cur.tv_usec; + } else { + cur.tv_sec = t->tv_sec - cur.tv_sec; + cur.tv_usec = t->tv_usec - cur.tv_usec; + } + + return jiffies + timeval_to_jiffies(&cur); +} + +/*! + * Private function to free buffers + * + * @param bufs_paddr Array of physical address of buffers to be freed + * + * @param bufs_vaddr Array of virtual address of buffers to be freed + * + * @param num_buf Number of buffers to be freed + * + * @param size Size for each buffer to be free + * + * @return status 0 success. + */ +static int mxc_free_buffers(dma_addr_t bufs_paddr[], void *bufs_vaddr[], + int num_buf, int size) +{ + int i; + + for (i = 0; i < num_buf; i++) { + if (bufs_vaddr[i] != 0) { + dma_free_coherent(0, size, bufs_vaddr[i], + bufs_paddr[i]); + pr_debug("freed @ paddr=0x%08X\n", (u32) bufs_paddr[i]); + bufs_paddr[i] = 0; + bufs_vaddr[i] = NULL; + } + } + return 0; +} + +/*! + * Private function to allocate buffers + * + * @param bufs_paddr Output array of physical address of buffers allocated + * + * @param bufs_vaddr Output array of virtual address of buffers allocated + * + * @param num_buf Input number of buffers to allocate + * + * @param size Input size for each buffer to allocate + * + * @return status -0 Successfully allocated a buffer, -ENOBUFS failed. + */ +static int mxc_allocate_buffers(dma_addr_t bufs_paddr[], void *bufs_vaddr[], + int num_buf, int size) +{ + int i; + + for (i = 0; i < num_buf; i++) { + bufs_vaddr[i] = dma_alloc_coherent(0, size, + &bufs_paddr[i], + GFP_DMA | GFP_KERNEL); + + if (bufs_vaddr[i] == 0) { + mxc_free_buffers(bufs_paddr, bufs_vaddr, i, size); + printk(KERN_ERR "dma_alloc_coherent failed.\n"); + return -ENOBUFS; + } + pr_debug("allocated @ paddr=0x%08X, size=%d.\n", + (u32) bufs_paddr[i], size); + } + + return 0; +} + +/* + * Returns bits per pixel for given pixel format + * + * @param pixelformat V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32 + * + * @return bits per pixel of pixelformat + */ +static u32 fmt_to_bpp(u32 pixelformat) +{ + u32 bpp; + + switch (pixelformat) { + case V4L2_PIX_FMT_RGB565: + bpp = 16; + break; + case V4L2_PIX_FMT_BGR24: + case V4L2_PIX_FMT_RGB24: + bpp = 24; + break; + case V4L2_PIX_FMT_BGR32: + case V4L2_PIX_FMT_RGB32: + bpp = 32; + break; + default: + bpp = 8; + break; + } + return bpp; +} + +static bool format_is_yuv(u32 pixelformat) +{ + u32 bpp; + + switch (pixelformat) { + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_YUV422P: + case V4L2_PIX_FMT_YVU420: + case V4L2_PIX_FMT_NV12: + return true; + break; + } + return false; +} + +static u32 bpp_to_fmt(struct fb_info *fbi) +{ + if (fbi->var.nonstd) + return fbi->var.nonstd; + + if (fbi->var.bits_per_pixel == 24) + return V4L2_PIX_FMT_BGR24; + else if (fbi->var.bits_per_pixel == 32) + return V4L2_PIX_FMT_BGR32; + else if (fbi->var.bits_per_pixel == 16) + return V4L2_PIX_FMT_RGB565; + + return 0; +} + +static irqreturn_t mxc_v4l2out_disp_refresh_irq_handler(int irq, void *dev_id) +{ + struct completion *comp = dev_id; + + complete(comp); + return IRQ_HANDLED; +} + +static void timer_work_func(struct work_struct *work) +{ + int index, ret, disp_irq = 0; + unsigned long timeout; + unsigned long lock_flags = 0; + vout_data *vout = + container_of(work, vout_data, timer_work); + DECLARE_COMPLETION_ONSTACK(disp_comp); + + switch (vout->display_ch) { + case MEM_FG_SYNC: + case MEM_BG_SYNC: + disp_irq = IPU_IRQ_BG_SF_END; + break; + case MEM_DC_SYNC: + disp_irq = IPU_IRQ_DC_FC_1; + break; + default: + dev_err(vout->video_dev->dev, + "not support display channel\n"); + } + + ipu_clear_irq(disp_irq); + ret = ipu_request_irq(disp_irq, mxc_v4l2out_disp_refresh_irq_handler, 0, NULL, &disp_comp); + if (ret < 0) { + dev_err(vout->video_dev->dev, + "Disp irq %d in use\n", disp_irq); + return; + } + wait_for_completion_timeout(&disp_comp, msecs_to_jiffies(40)); + ipu_free_irq(disp_irq, &disp_comp); + + spin_lock_irqsave(&g_lock, lock_flags); + + if (ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, + vout->next_rdy_ipu_buf) < 0) { + dev_err(vout->video_dev->dev, + "unable to set IPU buffer ready\n"); + } + vout->next_rdy_ipu_buf = !vout->next_rdy_ipu_buf; + + /* Setup timer for next buffer */ + index = peek_next_buf(&vout->ready_q); + if (index != -1) { + /* if timestamp is 0, then default to 30fps */ + if ((vout->v4l2_bufs[index].timestamp.tv_sec == 0) + && (vout->v4l2_bufs[index].timestamp.tv_usec == 0)) + timeout = + vout->start_jiffies + vout->frame_count * HZ / 30; + else + timeout = + get_jiffies(&vout->v4l2_bufs[index].timestamp); + + if (jiffies >= timeout) { + dev_dbg(vout->video_dev->dev, + "warning: timer timeout already expired.\n"); + } + if (mod_timer(&vout->output_timer, timeout)) + dev_dbg(vout->video_dev->dev, + "warning: timer was already set\n"); + + dev_dbg(vout->video_dev->dev, + "timer handler next schedule: %lu\n", timeout); + } else { + vout->state = STATE_STREAM_PAUSED; + } + + spin_unlock_irqrestore(&g_lock, lock_flags); +} + +static void mxc_v4l2out_timer_handler(unsigned long arg) +{ + int index; + unsigned long lock_flags = 0; + vout_data *vout = (vout_data *) arg; + + dev_dbg(vout->video_dev->dev, "timer handler: %lu\n", jiffies); + + spin_lock_irqsave(&g_lock, lock_flags); + + if ((vout->state == STATE_STREAM_STOPPING) + || (vout->state == STATE_STREAM_OFF)) + goto exit0; + /* + * If timer occurs before IPU h/w is ready, then set the state to + * paused and the timer will be set again when next buffer is queued + * or PP comletes + */ + if (vout->ipu_buf[vout->next_rdy_ipu_buf] != -1) { + dev_dbg(vout->video_dev->dev, "IPU buffer busy\n"); + vout->state = STATE_STREAM_PAUSED; + goto exit0; + } + + /* Dequeue buffer and pass to IPU */ + index = dequeue_buf(&vout->ready_q); + if (index == -1) { /* no buffers ready, should never occur */ + dev_err(vout->video_dev->dev, + "mxc_v4l2out: timer - no queued buffers ready\n"); + goto exit0; + } + + g_buf_dq_cnt++; + vout->frame_count++; + vout->ipu_buf[vout->next_rdy_ipu_buf] = index; + if (ipu_update_channel_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, + vout->next_rdy_ipu_buf, + vout->v4l2_bufs[index].m.offset) < 0) { + dev_err(vout->video_dev->dev, + "unable to update buffer %d address\n", + vout->next_rdy_ipu_buf); + goto exit0; + } + + spin_unlock_irqrestore(&g_lock, lock_flags); + schedule_work(&vout->timer_work); + return; + + exit0: + spin_unlock_irqrestore(&g_lock, lock_flags); +} + +static irqreturn_t mxc_v4l2out_pp_in_irq_handler(int irq, void *dev_id) +{ + int last_buf; + int index; + unsigned long timeout; + unsigned long lock_flags = 0; + vout_data *vout = dev_id; + + spin_lock_irqsave(&g_lock, lock_flags); + + g_irq_cnt++; + + /* Process previous buffer */ + last_buf = vout->ipu_buf[vout->next_done_ipu_buf]; + if (last_buf != -1) { + g_buf_output_cnt++; + vout->v4l2_bufs[last_buf].flags = V4L2_BUF_FLAG_DONE; + queue_buf(&vout->done_q, last_buf); + vout->ipu_buf[vout->next_done_ipu_buf] = -1; + wake_up_interruptible(&vout->v4l_bufq); + /* printk("pp_irq: buf %d done\n", vout->next_done_ipu_buf); */ + vout->next_done_ipu_buf = !vout->next_done_ipu_buf; + } + + if (vout->state == STATE_STREAM_STOPPING) { + if ((vout->ipu_buf[0] == -1) && (vout->ipu_buf[1] == -1)) { + vout->state = STATE_STREAM_OFF; + } + } else if ((vout->state == STATE_STREAM_PAUSED) + && ((index = peek_next_buf(&vout->ready_q)) != -1)) { + /* Setup timer for next buffer, when stream has been paused */ + pr_debug("next index %d\n", index); + + /* if timestamp is 0, then default to 30fps */ + if ((vout->v4l2_bufs[index].timestamp.tv_sec == 0) + && (vout->v4l2_bufs[index].timestamp.tv_usec == 0)) + timeout = + vout->start_jiffies + vout->frame_count * HZ / 30; + else + timeout = + get_jiffies(&vout->v4l2_bufs[index].timestamp); + + if (jiffies >= timeout) { + pr_debug("warning: timer timeout already expired.\n"); + } + + vout->state = STATE_STREAM_ON; + + if (mod_timer(&vout->output_timer, timeout)) + pr_debug("warning: timer was already set\n"); + + pr_debug("timer handler next schedule: %lu\n", timeout); + } + + spin_unlock_irqrestore(&g_lock, lock_flags); + + return IRQ_HANDLED; +} + +/*! + * Start the output stream + * + * @param vout structure vout_data * + * + * @return status 0 Success + */ +static int mxc_v4l2out_streamon(vout_data * vout) +{ + struct device *dev = vout->video_dev->dev; + ipu_channel_params_t params; + struct mxcfb_pos fb_pos; + struct fb_var_screeninfo fbvar; + struct fb_info *fbi = + registered_fb[vout->output_fb_num[vout->cur_disp_output]]; + int pp_in_buf[2]; + u16 out_width; + u16 out_height; + ipu_channel_t display_input_ch = MEM_PP_MEM; + bool use_direct_adc = false; + mm_segment_t old_fs; + + if (!vout) + return -EINVAL; + + if (vout->state != STATE_STREAM_OFF) + return -EBUSY; + + if (queue_size(&vout->ready_q) < 2) { + dev_err(dev, "2 buffers not been queued yet!\n"); + return -EINVAL; + } + + out_width = vout->crop_current.width; + out_height = vout->crop_current.height; + + vout->next_done_ipu_buf = vout->next_rdy_ipu_buf = 0; + vout->ipu_buf[0] = pp_in_buf[0] = dequeue_buf(&vout->ready_q); + vout->ipu_buf[1] = pp_in_buf[1] = dequeue_buf(&vout->ready_q); + vout->frame_count = 2; + + ipu_enable_irq(IPU_IRQ_PP_IN_EOF); + + /* Init Display Channel */ +#ifdef CONFIG_FB_MXC_ASYNC_PANEL + if (vout->cur_disp_output < DISP3) { + mxcfb_set_refresh_mode(fbi, MXCFB_REFRESH_OFF, 0); + fbi = NULL; + if (ipu_can_rotate_in_place(vout->rotate)) { + dev_dbg(dev, "Using PP direct to ADC channel\n"); + use_direct_adc = true; + vout->display_ch = MEM_PP_ADC; + vout->post_proc_ch = MEM_PP_ADC; + + memset(¶ms, 0, sizeof(params)); + params.mem_pp_adc.in_width = vout->v2f.fmt.pix.width; + params.mem_pp_adc.in_height = vout->v2f.fmt.pix.height; + params.mem_pp_adc.in_pixel_fmt = + vout->v2f.fmt.pix.pixelformat; + params.mem_pp_adc.out_width = out_width; + params.mem_pp_adc.out_height = out_height; + params.mem_pp_adc.out_pixel_fmt = SDC_FG_FB_FORMAT; +#ifdef CONFIG_FB_MXC_EPSON_PANEL + params.mem_pp_adc.out_left = + 2 + vout->crop_current.left; +#else + params.mem_pp_adc.out_left = + 12 + vout->crop_current.left; +#endif + params.mem_pp_adc.out_top = vout->crop_current.top; + if (ipu_init_channel(vout->post_proc_ch, ¶ms) != 0) { + dev_err(dev, "Error initializing PP chan\n"); + return -EINVAL; + } + + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_INPUT_BUFFER, + params.mem_pp_adc. + in_pixel_fmt, + params.mem_pp_adc.in_width, + params.mem_pp_adc.in_height, + vout->v2f.fmt.pix. + bytesperline / + bytes_per_pixel(params. + mem_pp_adc. + in_pixel_fmt), + vout->rotate, + vout-> + v4l2_bufs[pp_in_buf[0]].m. + offset, + vout-> + v4l2_bufs[pp_in_buf[1]].m. + offset, + vout->offset.u_offset, + vout->offset.v_offset) != + 0) { + dev_err(dev, "Error initializing PP in buf\n"); + return -EINVAL; + } + + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_OUTPUT_BUFFER, + params.mem_pp_adc. + out_pixel_fmt, out_width, + out_height, out_width, + vout->rotate, 0, 0, 0, + 0) != 0) { + dev_err(dev, + "Error initializing PP output buffer\n"); + return -EINVAL; + } + + } else { + dev_dbg(dev, "Using ADC SYS2 channel\n"); + vout->display_ch = ADC_SYS2; + vout->post_proc_ch = MEM_PP_MEM; + + if (vout->display_bufs[0]) { + mxc_free_buffers(vout->display_bufs, + vout->display_bufs_vaddr, + 2, vout->display_buf_size); + } + + vout->display_buf_size = vout->crop_current.width * + vout->crop_current.height * + fmt_to_bpp(SDC_FG_FB_FORMAT) / 8; + mxc_allocate_buffers(vout->display_bufs, + vout->display_bufs_vaddr, + 2, vout->display_buf_size); + + memset(¶ms, 0, sizeof(params)); + params.adc_sys2.disp = vout->cur_disp_output; + params.adc_sys2.ch_mode = WriteTemplateNonSeq; +#ifdef CONFIG_FB_MXC_EPSON_PANEL + params.adc_sys2.out_left = 2 + vout->crop_current.left; +#else + params.adc_sys2.out_left = 12 + vout->crop_current.left; +#endif + params.adc_sys2.out_top = vout->crop_current.top; + if (ipu_init_channel(ADC_SYS2, ¶ms) < 0) + return -EINVAL; + + if (ipu_init_channel_buffer(vout->display_ch, + IPU_INPUT_BUFFER, + SDC_FG_FB_FORMAT, + out_width, out_height, + out_width, IPU_ROTATE_NONE, + vout->display_bufs[0], + vout->display_bufs[1], 0, + 0) != 0) { + dev_err(dev, + "Error initializing SDC FG buffer\n"); + return -EINVAL; + } + } + } else +#endif + { /* Use SDC */ + dev_dbg(dev, "Using SDC channel\n"); + + fbvar = fbi->var; + + if (vout->cur_disp_output == 3) { + vout->display_ch = MEM_FG_SYNC; + fbvar.bits_per_pixel = 16; + if (format_is_yuv(vout->v2f.fmt.pix.pixelformat)) + fbvar.nonstd = IPU_PIX_FMT_UYVY; + else + fbvar.nonstd = 0; + + fbvar.xres = fbvar.xres_virtual = out_width; + fbvar.yres = out_height; + fbvar.yres_virtual = out_height * 2; + } else if (vout->cur_disp_output == 5) { + vout->display_ch = MEM_DC_SYNC; + fbvar.bits_per_pixel = 16; + fbvar.nonstd = IPU_PIX_FMT_UYVY; + + fbvar.xres = fbvar.xres_virtual = out_width; + fbvar.yres = out_height; + fbvar.yres_virtual = out_height * 2; + } else { + vout->display_ch = MEM_BG_SYNC; + } + + fbvar.activate |= FB_ACTIVATE_FORCE; + fb_set_var(fbi, &fbvar); + + fb_pos.x = vout->crop_current.left; + fb_pos.y = vout->crop_current.top; + if (fbi->fbops->fb_ioctl) { + old_fs = get_fs(); + set_fs(KERNEL_DS); + fbi->fbops->fb_ioctl(fbi, MXCFB_SET_OVERLAY_POS, + (unsigned long)&fb_pos); + set_fs(old_fs); + } + + vout->display_bufs[1] = fbi->fix.smem_start; + vout->display_bufs[0] = fbi->fix.smem_start + + (fbi->fix.line_length * fbi->var.yres); + vout->display_buf_size = vout->crop_current.width * + vout->crop_current.height * fbi->var.bits_per_pixel / 8; + + vout->post_proc_ch = MEM_PP_MEM; + } + + /* Init PP */ + if (use_direct_adc == false) { + if (vout->rotate >= IPU_ROTATE_90_RIGHT) { + out_width = vout->crop_current.height; + out_height = vout->crop_current.width; + } + memset(¶ms, 0, sizeof(params)); + params.mem_pp_mem.in_width = vout->v2f.fmt.pix.width; + params.mem_pp_mem.in_height = vout->v2f.fmt.pix.height; + params.mem_pp_mem.in_pixel_fmt = vout->v2f.fmt.pix.pixelformat; + params.mem_pp_mem.out_width = out_width; + params.mem_pp_mem.out_height = out_height; + if (vout->display_ch == ADC_SYS2) + params.mem_pp_mem.out_pixel_fmt = SDC_FG_FB_FORMAT; + else + params.mem_pp_mem.out_pixel_fmt = bpp_to_fmt(fbi); + if (ipu_init_channel(vout->post_proc_ch, ¶ms) != 0) { + dev_err(dev, "Error initializing PP channel\n"); + return -EINVAL; + } + + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_INPUT_BUFFER, + params.mem_pp_mem.in_pixel_fmt, + params.mem_pp_mem.in_width, + params.mem_pp_mem.in_height, + vout->v2f.fmt.pix.bytesperline / + bytes_per_pixel(params.mem_pp_mem. + in_pixel_fmt), + IPU_ROTATE_NONE, + vout->v4l2_bufs[pp_in_buf[0]].m. + offset, + vout->v4l2_bufs[pp_in_buf[1]].m. + offset, vout->offset.u_offset, + vout->offset.v_offset) != 0) { + dev_err(dev, "Error initializing PP input buffer\n"); + return -EINVAL; + } + + if (!ipu_can_rotate_in_place(vout->rotate)) { + if (vout->rot_pp_bufs[0]) { + mxc_free_buffers(vout->rot_pp_bufs, + vout->rot_pp_bufs_vaddr, 2, + vout->display_buf_size); + } + if (mxc_allocate_buffers + (vout->rot_pp_bufs, vout->rot_pp_bufs_vaddr, 2, + vout->display_buf_size) < 0) { + return -ENOBUFS; + } + + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_OUTPUT_BUFFER, + params.mem_pp_mem. + out_pixel_fmt, out_width, + out_height, out_width, + IPU_ROTATE_NONE, + vout->rot_pp_bufs[0], + vout->rot_pp_bufs[1], 0, + 0) != 0) { + dev_err(dev, + "Error initializing PP output buffer\n"); + return -EINVAL; + } + + if (ipu_init_channel(MEM_ROT_PP_MEM, NULL) != 0) { + dev_err(dev, + "Error initializing PP ROT channel\n"); + return -EINVAL; + } + + if (ipu_init_channel_buffer(MEM_ROT_PP_MEM, + IPU_INPUT_BUFFER, + params.mem_pp_mem. + out_pixel_fmt, out_width, + out_height, out_width, + vout->rotate, + vout->rot_pp_bufs[0], + vout->rot_pp_bufs[1], 0, + 0) != 0) { + dev_err(dev, + "Error initializing PP ROT input buffer\n"); + return -EINVAL; + } + + /* swap width and height */ + if (vout->rotate >= IPU_ROTATE_90_RIGHT) { + out_width = vout->crop_current.width; + out_height = vout->crop_current.height; + } + + if (ipu_init_channel_buffer(MEM_ROT_PP_MEM, + IPU_OUTPUT_BUFFER, + params.mem_pp_mem. + out_pixel_fmt, out_width, + out_height, out_width, + IPU_ROTATE_NONE, + vout->display_bufs[0], + vout->display_bufs[1], 0, + 0) != 0) { + dev_err(dev, + "Error initializing PP output buffer\n"); + return -EINVAL; + } + + if (ipu_link_channels(vout->post_proc_ch, + MEM_ROT_PP_MEM) < 0) { + return -EINVAL; + } + ipu_select_buffer(MEM_ROT_PP_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(MEM_ROT_PP_MEM, IPU_OUTPUT_BUFFER, 1); + + ipu_enable_channel(MEM_ROT_PP_MEM); + + display_input_ch = MEM_ROT_PP_MEM; + } else { + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_OUTPUT_BUFFER, + params.mem_pp_mem. + out_pixel_fmt, out_width, + out_height, out_width, + vout->rotate, + vout->display_bufs[0], + vout->display_bufs[1], 0, + 0) != 0) { + dev_err(dev, + "Error initializing PP output buffer\n"); + return -EINVAL; + } + } + if (ipu_link_channels(display_input_ch, vout->display_ch) < 0) { + dev_err(dev, "Error linking ipu channels\n"); + return -EINVAL; + } + } + + vout->state = STATE_STREAM_PAUSED; + + ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 0); + ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 1); + + if (use_direct_adc == false) { + ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, 1); + + ipu_enable_channel(vout->post_proc_ch); + + if (fbi) { + acquire_console_sem(); + fb_blank(fbi, FB_BLANK_UNBLANK); + release_console_sem(); + } else { + ipu_enable_channel(vout->display_ch); + } + } else { + ipu_enable_channel(vout->post_proc_ch); + } + + vout->start_jiffies = jiffies; + dev_dbg(dev, + "streamon: start time = %lu jiffies\n", vout->start_jiffies); + + return 0; +} + +/*! + * Shut down the voutera + * + * @param vout structure vout_data * + * + * @return status 0 Success + */ +static int mxc_v4l2out_streamoff(vout_data * vout) +{ + struct fb_info *fbi = + registered_fb[vout->output_fb_num[vout->cur_disp_output]]; + int i, retval = 0; + unsigned long lockflag = 0; + + if (!vout) + return -EINVAL; + + if (vout->state == STATE_STREAM_OFF) { + return 0; + } + + cancel_work_sync(&vout->timer_work); + + spin_lock_irqsave(&g_lock, lockflag); + + del_timer(&vout->output_timer); + + if (vout->state == STATE_STREAM_ON) { + vout->state = STATE_STREAM_STOPPING; + } + + ipu_disable_irq(IPU_IRQ_PP_IN_EOF); + + spin_unlock_irqrestore(&g_lock, lockflag); + + if (vout->display_ch == MEM_FG_SYNC) { + struct mxcfb_pos fb_pos; + mm_segment_t old_fs; + + fb_pos.x = 0; + fb_pos.y = 0; + if (fbi->fbops->fb_ioctl) { + old_fs = get_fs(); + set_fs(KERNEL_DS); + fbi->fbops->fb_ioctl(fbi, MXCFB_SET_OVERLAY_POS, + (unsigned long)&fb_pos); + set_fs(old_fs); + } + } + + if (vout->post_proc_ch == MEM_PP_MEM) { /* SDC or ADC with Rotation */ + if (!ipu_can_rotate_in_place(vout->rotate)) { + ipu_unlink_channels(MEM_PP_MEM, MEM_ROT_PP_MEM); + ipu_unlink_channels(MEM_ROT_PP_MEM, vout->display_ch); + ipu_disable_channel(MEM_ROT_PP_MEM, true); + + if (vout->rot_pp_bufs[0]) { + mxc_free_buffers(vout->rot_pp_bufs, + vout->rot_pp_bufs_vaddr, 2, + vout->display_buf_size); + } + } else { + ipu_unlink_channels(MEM_PP_MEM, vout->display_ch); + } + ipu_disable_channel(MEM_PP_MEM, true); + + if (vout->display_ch == ADC_SYS2) { + ipu_disable_channel(vout->display_ch, true); + ipu_uninit_channel(vout->display_ch); + } else { + fbi->var.activate |= FB_ACTIVATE_FORCE; + fb_set_var(fbi, &fbi->var); + + if (vout->display_ch == MEM_FG_SYNC) { + acquire_console_sem(); + fb_blank(fbi, FB_BLANK_POWERDOWN); + release_console_sem(); + } + + vout->display_bufs[0] = 0; + vout->display_bufs[1] = 0; + } + + ipu_uninit_channel(MEM_PP_MEM); + if (!ipu_can_rotate_in_place(vout->rotate)) + ipu_uninit_channel(MEM_ROT_PP_MEM); + } else { /* ADC Direct */ + ipu_disable_channel(MEM_PP_ADC, true); + ipu_uninit_channel(MEM_PP_ADC); + } + vout->ready_q.head = vout->ready_q.tail = 0; + vout->done_q.head = vout->done_q.tail = 0; + for (i = 0; i < vout->buffer_cnt; i++) { + vout->v4l2_bufs[i].flags = 0; + vout->v4l2_bufs[i].timestamp.tv_sec = 0; + vout->v4l2_bufs[i].timestamp.tv_usec = 0; + } + + vout->state = STATE_STREAM_OFF; + +#ifdef CONFIG_FB_MXC_ASYNC_PANEL + if (vout->cur_disp_output < DISP3) { + if (vout->display_bufs[0] != 0) { + mxc_free_buffers(vout->display_bufs, + vout->display_bufs_vaddr, 2, + vout->display_buf_size); + } + + mxcfb_set_refresh_mode(registered_fb + [vout-> + output_fb_num[vout->cur_disp_output]], + MXCFB_REFRESH_PARTIAL, 0); + } +#endif + + return retval; +} + +/* + * Valid whether the palette is supported + * + * @param palette V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32 + * + * @return 1 if supported, 0 if failed + */ +static inline int valid_mode(u32 palette) +{ + return ((palette == V4L2_PIX_FMT_RGB565) || + (palette == V4L2_PIX_FMT_BGR24) || + (palette == V4L2_PIX_FMT_RGB24) || + (palette == V4L2_PIX_FMT_BGR32) || + (palette == V4L2_PIX_FMT_RGB32) || + (palette == V4L2_PIX_FMT_NV12) || + (palette == V4L2_PIX_FMT_YUV422P) || + (palette == V4L2_PIX_FMT_YUV420)); +} + +/* + * V4L2 - Handles VIDIOC_G_FMT Ioctl + * + * @param vout structure vout_data * + * + * @param v4l2_format structure v4l2_format * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2out_g_fmt(vout_data * vout, struct v4l2_format *f) +{ + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + return -EINVAL; + } + *f = vout->v2f; + return 0; +} + +/* + * V4L2 - Handles VIDIOC_S_FMT Ioctl + * + * @param vout structure vout_data * + * + * @param v4l2_format structure v4l2_format * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2out_s_fmt(vout_data * vout, struct v4l2_format *f) +{ + int retval = 0; + u32 size = 0; + u32 bytesperline; + + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + goto err0; + } + if (!valid_mode(f->fmt.pix.pixelformat)) { + dev_err(vout->video_dev->dev, "pixel format not supported\n"); + retval = -EINVAL; + goto err0; + } + + bytesperline = (f->fmt.pix.width * fmt_to_bpp(f->fmt.pix.pixelformat)) / + 8; + if (f->fmt.pix.bytesperline < bytesperline) { + f->fmt.pix.bytesperline = bytesperline; + } else { + bytesperline = f->fmt.pix.bytesperline; + } + + switch (f->fmt.pix.pixelformat) { + case V4L2_PIX_FMT_YUV422P: + /* byteperline for YUV planar formats is for + Y plane only */ + size = bytesperline * f->fmt.pix.height * 2; + break; + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_NV12: + size = (bytesperline * f->fmt.pix.height * 3) / 2; + break; + default: + size = bytesperline * f->fmt.pix.height; + break; + } + + /* Return the actual size of the image to the app */ + if (f->fmt.pix.sizeimage < size) { + f->fmt.pix.sizeimage = size; + } else { + size = f->fmt.pix.sizeimage; + } + + vout->v2f.fmt.pix = f->fmt.pix; + if (vout->v2f.fmt.pix.priv != 0) { + if (copy_from_user(&vout->offset, + (void *)vout->v2f.fmt.pix.priv, + sizeof(vout->offset))) { + retval = -EFAULT; + goto err0; + } + } else { + vout->offset.u_offset = 0; + vout->offset.v_offset = 0; + } + + retval = 0; + err0: + return retval; +} + +/* + * V4L2 - Handles VIDIOC_G_CTRL Ioctl + * + * @param vout structure vout_data * + * + * @param c structure v4l2_control * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_get_v42lout_control(vout_data * vout, struct v4l2_control *c) +{ + switch (c->id) { + case V4L2_CID_HFLIP: + return (vout->rotate & IPU_ROTATE_HORIZ_FLIP) ? 1 : 0; + case V4L2_CID_VFLIP: + return (vout->rotate & IPU_ROTATE_VERT_FLIP) ? 1 : 0; + case (V4L2_CID_PRIVATE_BASE + 1): + return vout->rotate; + default: + return -EINVAL; + } +} + +/* + * V4L2 - Handles VIDIOC_S_CTRL Ioctl + * + * @param vout structure vout_data * + * + * @param c structure v4l2_control * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_set_v42lout_control(vout_data * vout, struct v4l2_control *c) +{ + switch (c->id) { + case V4L2_CID_HFLIP: + vout->rotate |= c->value ? IPU_ROTATE_HORIZ_FLIP : + IPU_ROTATE_NONE; + break; + case V4L2_CID_VFLIP: + vout->rotate |= c->value ? IPU_ROTATE_VERT_FLIP : + IPU_ROTATE_NONE; + break; + case V4L2_CID_MXC_ROT: + vout->rotate = c->value; + break; + default: + return -EINVAL; + } + return 0; +} + +/*! + * V4L2 interface - open function + * + * @param inode structure inode * + * + * @param file structure file * + * + * @return status 0 success, ENODEV invalid device instance, + * ENODEV timeout, ERESTARTSYS interrupted by user + */ +static int mxc_v4l2out_open(struct inode *inode, struct file *file) +{ + struct video_device *dev = video_devdata(file); + vout_data *vout = video_get_drvdata(dev); + int err; + + if (!vout) { + return -ENODEV; + } + + down(&vout->busy_lock); + + err = -EINTR; + if (signal_pending(current)) + goto oops; + + if (vout->open_count++ == 0) { + ipu_request_irq(IPU_IRQ_PP_IN_EOF, + mxc_v4l2out_pp_in_irq_handler, + 0, dev->name, vout); + + init_waitqueue_head(&vout->v4l_bufq); + + init_timer(&vout->output_timer); + vout->output_timer.function = mxc_v4l2out_timer_handler; + vout->output_timer.data = (unsigned long)vout; + + vout->state = STATE_STREAM_OFF; + vout->rotate = IPU_ROTATE_NONE; + g_irq_cnt = g_buf_output_cnt = g_buf_q_cnt = g_buf_dq_cnt = 0; + + INIT_WORK(&vout->timer_work, timer_work_func); + + } + + file->private_data = dev; + + up(&vout->busy_lock); + + return 0; + + oops: + up(&vout->busy_lock); + return err; +} + +/*! + * V4L2 interface - close function + * + * @param inode struct inode * + * + * @param file struct file * + * + * @return 0 success + */ +static int mxc_v4l2out_close(struct inode *inode, struct file *file) +{ + struct video_device *dev = video_devdata(file); + vout_data *vout = video_get_drvdata(dev); + + if (--vout->open_count == 0) { + if (vout->state != STATE_STREAM_OFF) + mxc_v4l2out_streamoff(vout); + + ipu_free_irq(IPU_IRQ_PP_IN_EOF, vout); + + file->private_data = NULL; + + mxc_free_buffers(vout->queue_buf_paddr, vout->queue_buf_vaddr, + vout->buffer_cnt, vout->queue_buf_size); + vout->buffer_cnt = 0; + mxc_free_buffers(vout->rot_pp_bufs, vout->rot_pp_bufs_vaddr, 2, + vout->display_buf_size); + + /* capture off */ + wake_up_interruptible(&vout->v4l_bufq); + + schedule_work(&vout->timer_work); + flush_scheduled_work(); + } + + return 0; +} + +/*! + * V4L2 interface - ioctl function + * + * @param inode struct inode * + * + * @param file struct file * + * + * @param ioctlnr unsigned int + * + * @param arg void * + * + * @return 0 success, ENODEV for invalid device instance, + * -1 for other errors. + */ +static int +mxc_v4l2out_do_ioctl(struct inode *inode, struct file *file, + unsigned int ioctlnr, void *arg) +{ + struct video_device *vdev = file->private_data; + vout_data *vout = video_get_drvdata(vdev); + int retval = 0; + int i = 0; + + if (!vout) + return -EBADF; + + /* make this _really_ smp-safe */ + if (down_interruptible(&vout->busy_lock)) + return -EBUSY; + + switch (ioctlnr) { + case VIDIOC_QUERYCAP: + { + struct v4l2_capability *cap = arg; + strcpy(cap->driver, "mxc_v4l2_output"); + cap->version = 0; + cap->capabilities = + V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING; + cap->card[0] = '\0'; + cap->bus_info[0] = '\0'; + retval = 0; + break; + } + case VIDIOC_G_FMT: + { + struct v4l2_format *gf = arg; + retval = mxc_v4l2out_g_fmt(vout, gf); + break; + } + case VIDIOC_S_FMT: + { + struct v4l2_format *sf = arg; + if (vout->state != STATE_STREAM_OFF) { + retval = -EBUSY; + break; + } + retval = mxc_v4l2out_s_fmt(vout, sf); + break; + } + case VIDIOC_REQBUFS: + { + struct v4l2_requestbuffers *req = arg; + if ((req->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) || + (req->memory != V4L2_MEMORY_MMAP)) { + dev_dbg(vdev->dev, + "VIDIOC_REQBUFS: incorrect buffer type\n"); + retval = -EINVAL; + break; + } + + if (req->count == 0) + mxc_v4l2out_streamoff(vout); + + if (vout->state == STATE_STREAM_OFF) { + if (vout->queue_buf_paddr[0] != 0) { + mxc_free_buffers(vout->queue_buf_paddr, + vout->queue_buf_vaddr, + vout->buffer_cnt, + vout->queue_buf_size); + dev_dbg(vdev->dev, + "VIDIOC_REQBUFS: freed buffers\n"); + } + vout->buffer_cnt = 0; + } else { + dev_dbg(vdev->dev, + "VIDIOC_REQBUFS: Buffer is in use\n"); + retval = -EBUSY; + break; + } + + if (req->count == 0) + break; + + if (req->count < MIN_FRAME_NUM) { + req->count = MIN_FRAME_NUM; + } else if (req->count > MAX_FRAME_NUM) { + req->count = MAX_FRAME_NUM; + } + vout->buffer_cnt = req->count; + vout->queue_buf_size = + PAGE_ALIGN(vout->v2f.fmt.pix.sizeimage); + + retval = mxc_allocate_buffers(vout->queue_buf_paddr, + vout->queue_buf_vaddr, + vout->buffer_cnt, + vout->queue_buf_size); + if (retval < 0) + break; + + /* Init buffer queues */ + vout->done_q.head = 0; + vout->done_q.tail = 0; + vout->ready_q.head = 0; + vout->ready_q.tail = 0; + + for (i = 0; i < vout->buffer_cnt; i++) { + memset(&(vout->v4l2_bufs[i]), 0, + sizeof(vout->v4l2_bufs[i])); + vout->v4l2_bufs[i].flags = 0; + vout->v4l2_bufs[i].memory = V4L2_MEMORY_MMAP; + vout->v4l2_bufs[i].index = i; + vout->v4l2_bufs[i].type = + V4L2_BUF_TYPE_VIDEO_OUTPUT; + vout->v4l2_bufs[i].length = + PAGE_ALIGN(vout->v2f.fmt.pix.sizeimage); + vout->v4l2_bufs[i].m.offset = + (unsigned long)vout->queue_buf_paddr[i]; + vout->v4l2_bufs[i].timestamp.tv_sec = 0; + vout->v4l2_bufs[i].timestamp.tv_usec = 0; + } + break; + } + case VIDIOC_QUERYBUF: + { + struct v4l2_buffer *buf = arg; + u32 type = buf->type; + int index = buf->index; + + if ((type != V4L2_BUF_TYPE_VIDEO_OUTPUT) || + (index >= vout->buffer_cnt)) { + dev_dbg(vdev->dev, + "VIDIOC_QUERYBUFS: incorrect buffer type\n"); + retval = -EINVAL; + break; + } + down(&vout->param_lock); + memcpy(buf, &(vout->v4l2_bufs[index]), sizeof(*buf)); + up(&vout->param_lock); + break; + } + case VIDIOC_QBUF: + { + struct v4l2_buffer *buf = arg; + int index = buf->index; + unsigned long lock_flags; + int param[5][3]; + + if ((buf->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) || + (index >= vout->buffer_cnt)) { + retval = -EINVAL; + break; + } + + dev_dbg(vdev->dev, "VIDIOC_QBUF: %d\n", buf->index); + + /* mmapped buffers are L1 WB cached, + * so we need to clean them */ + if (buf->memory & V4L2_MEMORY_MMAP) { + flush_cache_all(); + } + + spin_lock_irqsave(&g_lock, lock_flags); + + memcpy(&(vout->v4l2_bufs[index]), buf, sizeof(*buf)); + vout->v4l2_bufs[index].flags |= V4L2_BUF_FLAG_QUEUED; + + g_buf_q_cnt++; + if (vout->v4l2_bufs[index].reserved) + if (!copy_from_user(¶m[0][0], + (void *)vout-> + v4l2_bufs[index] + .reserved, sizeof(param))) + ipu_set_csc_coefficients(vout-> + display_ch, + param); + queue_buf(&vout->ready_q, index); + if (vout->state == STATE_STREAM_PAUSED) { + unsigned long timeout; + + index = peek_next_buf(&vout->ready_q); + + /* if timestamp is 0, then default to 30fps */ + if ((vout->v4l2_bufs[index].timestamp.tv_sec == + 0) + && (vout->v4l2_bufs[index].timestamp. + tv_usec == 0)) + timeout = + vout->start_jiffies + + vout->frame_count * HZ / 30; + else + timeout = + get_jiffies(&vout->v4l2_bufs[index]. + timestamp); + + if (jiffies >= timeout) { + dev_dbg(vout->video_dev->dev, + "warning: timer timeout already expired.\n"); + } + vout->output_timer.expires = timeout; + dev_dbg(vdev->dev, + "QBUF: frame #%u timeout @ %lu jiffies, current = %lu\n", + vout->frame_count, timeout, jiffies); + add_timer(&vout->output_timer); + vout->state = STATE_STREAM_ON; + } + + spin_unlock_irqrestore(&g_lock, lock_flags); + break; + } + case VIDIOC_DQBUF: + { + struct v4l2_buffer *buf = arg; + int idx; + + if ((queue_size(&vout->done_q) == 0) && + (file->f_flags & O_NONBLOCK)) { + retval = -EAGAIN; + break; + } + + if (!wait_event_interruptible_timeout(vout->v4l_bufq, + queue_size(&vout-> + done_q) + != 0, 10 * HZ)) { + dev_dbg(vdev->dev, "VIDIOC_DQBUF: timeout\n"); + retval = -ETIME; + break; + } else if (signal_pending(current)) { + dev_dbg(vdev->dev, + "VIDIOC_DQBUF: interrupt received\n"); + retval = -ERESTARTSYS; + break; + } + idx = dequeue_buf(&vout->done_q); + if (idx == -1) { /* No frame free */ + dev_dbg(vdev->dev, + "VIDIOC_DQBUF: no free buffers, returning\n"); + retval = -EAGAIN; + break; + } + if ((vout->v4l2_bufs[idx].flags & V4L2_BUF_FLAG_DONE) == + 0) + dev_dbg(vdev->dev, + "VIDIOC_DQBUF: buffer in done q, but not " + "flagged as done\n"); + + vout->v4l2_bufs[idx].flags = 0; + memcpy(buf, &(vout->v4l2_bufs[idx]), sizeof(*buf)); + dev_dbg(vdev->dev, "VIDIOC_DQBUF: %d\n", buf->index); + break; + } + case VIDIOC_STREAMON: + { + retval = mxc_v4l2out_streamon(vout); + break; + } + case VIDIOC_STREAMOFF: + { + retval = mxc_v4l2out_streamoff(vout); + break; + } + case VIDIOC_G_CTRL: + { + retval = mxc_get_v42lout_control(vout, arg); + break; + } + case VIDIOC_S_CTRL: + { + retval = mxc_set_v42lout_control(vout, arg); + break; + } + case VIDIOC_CROPCAP: + { + struct v4l2_cropcap *cap = arg; + + if (cap->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + break; + } + + cap->bounds = vout->crop_bounds[vout->cur_disp_output]; + cap->defrect = vout->crop_bounds[vout->cur_disp_output]; + retval = 0; + break; + } + case VIDIOC_G_CROP: + { + struct v4l2_crop *crop = arg; + + if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + break; + } + crop->c = vout->crop_current; + break; + } + case VIDIOC_S_CROP: + { + struct v4l2_crop *crop = arg; + struct v4l2_rect *b = + &(vout->crop_bounds[vout->cur_disp_output]); + + if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + break; + } + if (crop->c.height < 0) { + retval = -EINVAL; + break; + } + if (crop->c.width < 0) { + retval = -EINVAL; + break; + } + + /* only full screen supported for SDC BG */ + if (vout->cur_disp_output == 4) { + crop->c = vout->crop_current; + break; + } + + if (crop->c.top < b->top) + crop->c.top = b->top; + if (crop->c.top >= b->top + b->height) + crop->c.top = b->top + b->height - 1; + if (crop->c.height > b->top - crop->c.top + b->height) + crop->c.height = + b->top - crop->c.top + b->height; + + if (crop->c.left < b->left) + crop->c.left = b->left; + if (crop->c.left >= b->left + b->width) + crop->c.left = b->left + b->width - 1; + if (crop->c.width > b->left - crop->c.left + b->width) + crop->c.width = + b->left - crop->c.left + b->width; + + /* stride line limitation */ + crop->c.height -= crop->c.height % 8; + crop->c.width -= crop->c.width % 8; + + vout->crop_current = crop->c; + break; + } + case VIDIOC_ENUMOUTPUT: + { + struct v4l2_output *output = arg; + + if ((output->index >= 5) || + (vout->output_enabled[output->index] == false)) { + retval = -EINVAL; + break; + } + + if (output->index < 3) { + *output = mxc_outputs[MXC_V4L2_OUT_2_ADC]; + output->name[4] = '0' + output->index; + } else { + *output = mxc_outputs[MXC_V4L2_OUT_2_SDC]; + } + break; + } + case VIDIOC_G_OUTPUT: + { + int *p_output_num = arg; + + *p_output_num = vout->cur_disp_output; + break; + } + case VIDIOC_S_OUTPUT: + { + int *p_output_num = arg; + int fbnum; + struct v4l2_rect *b; + + if ((*p_output_num >= MXC_V4L2_OUT_NUM_OUTPUTS) || + (vout->output_enabled[*p_output_num] == false)) { + retval = -EINVAL; + break; + } + + if (vout->state != STATE_STREAM_OFF) { + retval = -EBUSY; + break; + } + + vout->cur_disp_output = *p_output_num; + + /* Update bounds in case they have changed */ + b = &vout->crop_bounds[vout->cur_disp_output]; + + fbnum = vout->output_fb_num[vout->cur_disp_output]; + if (vout->cur_disp_output == 3) + fbnum = vout->output_fb_num[4]; + + b->width = registered_fb[fbnum]->var.xres; + b->height = registered_fb[fbnum]->var.yres; + + vout->crop_current = *b; + break; + } + case VIDIOC_ENUM_FMT: + case VIDIOC_TRY_FMT: + case VIDIOC_QUERYCTRL: + case VIDIOC_G_PARM: + case VIDIOC_ENUMSTD: + case VIDIOC_G_STD: + case VIDIOC_S_STD: + case VIDIOC_G_TUNER: + case VIDIOC_S_TUNER: + case VIDIOC_G_FREQUENCY: + case VIDIOC_S_FREQUENCY: + default: + retval = -EINVAL; + break; + } + + up(&vout->busy_lock); + return retval; +} + +/* + * V4L2 interface - ioctl function + * + * @return None + */ +static int +mxc_v4l2out_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + return video_usercopy(inode, file, cmd, arg, mxc_v4l2out_do_ioctl); +} + +/*! + * V4L2 interface - mmap function + * + * @param file structure file * + * + * @param vma structure vm_area_struct * + * + * @return status 0 Success, EINTR busy lock error, + * ENOBUFS remap_page error + */ +static int mxc_v4l2out_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct video_device *vdev = video_devdata(file); + unsigned long size = vma->vm_end - vma->vm_start; + int res = 0; + int i; + vout_data *vout = video_get_drvdata(vdev); + + dev_dbg(vdev->dev, "pgoff=0x%lx, start=0x%lx, end=0x%lx\n", + vma->vm_pgoff, vma->vm_start, vma->vm_end); + + /* make this _really_ smp-safe */ + if (down_interruptible(&vout->busy_lock)) + return -EINTR; + + for (i = 0; i < vout->buffer_cnt; i++) { + if ((vout->v4l2_bufs[i].m.offset == + (vma->vm_pgoff << PAGE_SHIFT)) && + (vout->v4l2_bufs[i].length >= size)) { + vout->v4l2_bufs[i].flags |= V4L2_BUF_FLAG_MAPPED; + break; + } + } + if (i == vout->buffer_cnt) { + res = -ENOBUFS; + goto mxc_mmap_exit; + } + + /* make buffers inner write-back, outer write-thru cacheable */ + vma->vm_page_prot = pgprot_outer_wrthru(vma->vm_page_prot); + + if (remap_pfn_range(vma, vma->vm_start, + vma->vm_pgoff, size, vma->vm_page_prot)) { + dev_dbg(vdev->dev, "mmap remap_pfn_range failed\n"); + res = -ENOBUFS; + goto mxc_mmap_exit; + } + + vma->vm_flags &= ~VM_IO; /* using shared anonymous pages */ + + mxc_mmap_exit: + up(&vout->busy_lock); + return res; +} + +/*! + * V4L2 interface - poll function + * + * @param file structure file * + * + * @param wait structure poll_table * + * + * @return status POLLIN | POLLRDNORM + */ +static unsigned int mxc_v4l2out_poll(struct file *file, poll_table * wait) +{ + struct video_device *dev = video_devdata(file); + vout_data *vout = video_get_drvdata(dev); + + wait_queue_head_t *queue = NULL; + int res = POLLIN | POLLRDNORM; + + if (down_interruptible(&vout->busy_lock)) + return -EINTR; + + queue = &vout->v4l_bufq; + poll_wait(file, queue, wait); + + up(&vout->busy_lock); + return res; +} + +static struct +file_operations mxc_v4l2out_fops = { + .owner = THIS_MODULE, + .open = mxc_v4l2out_open, + .release = mxc_v4l2out_close, + .ioctl = mxc_v4l2out_ioctl, + .mmap = mxc_v4l2out_mmap, + .poll = mxc_v4l2out_poll, +}; + +static struct video_device mxc_v4l2out_template = { + .owner = THIS_MODULE, + .name = "MXC Video Output", + .type = 0, + .type2 = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING, + .fops = &mxc_v4l2out_fops, + .release = video_device_release, +}; + +/*! + * Probe routine for the framebuffer driver. It is called during the + * driver binding process. The following functions are performed in + * this routine: Framebuffer initialization, Memory allocation and + * mapping, Framebuffer registration, IPU initialization. + * + * @return Appropriate error code to the kernel common code + */ +static int mxc_v4l2out_probe(struct platform_device *pdev) +{ + int i; + vout_data *vout; + + /* + * Allocate sufficient memory for the fb structure + */ + g_vout = vout = kmalloc(sizeof(vout_data), GFP_KERNEL); + + if (!vout) + return 0; + + memset(vout, 0, sizeof(vout_data)); + + vout->video_dev = video_device_alloc(); + if (vout->video_dev == NULL) + return -1; + vout->video_dev->dev = &pdev->dev; + vout->video_dev->minor = -1; + + *(vout->video_dev) = mxc_v4l2out_template; + + /* register v4l device */ + if (video_register_device(vout->video_dev, + VFL_TYPE_GRABBER, video_nr) == -1) { + dev_dbg(&pdev->dev, "video_register_device failed\n"); + return 0; + } + dev_info(&pdev->dev, "Registered device video%d\n", + vout->video_dev->minor & 0x1f); + vout->video_dev->dev = &pdev->dev; + + video_set_drvdata(vout->video_dev, vout); + + init_MUTEX(&vout->param_lock); + init_MUTEX(&vout->busy_lock); + + /* setup outputs and cropping */ + vout->cur_disp_output = -1; + for (i = 0; i < num_registered_fb; i++) { + char *idstr = registered_fb[i]->fix.id; + if (strncmp(idstr, "DISP", 4) == 0) { + int disp_num = idstr[4] - '0'; + if (disp_num == 3) { + if (strcmp(idstr, "DISP3 BG - DI1") == 0) + disp_num = 5; + else if (strncmp(idstr, "DISP3 BG", 8) == 0) + disp_num = 4; + } + vout->crop_bounds[disp_num].left = 0; + vout->crop_bounds[disp_num].top = 0; + vout->crop_bounds[disp_num].width = + registered_fb[i]->var.xres; + vout->crop_bounds[disp_num].height = + registered_fb[i]->var.yres; + vout->output_enabled[disp_num] = true; + vout->output_fb_num[disp_num] = i; + if (vout->cur_disp_output == -1) { + vout->cur_disp_output = disp_num; + } + } + + } + vout->crop_current = vout->crop_bounds[vout->cur_disp_output]; + + platform_set_drvdata(pdev, vout); + + return 0; +} + +static int mxc_v4l2out_remove(struct platform_device *pdev) +{ + vout_data *vout = platform_get_drvdata(pdev); + + if (vout->video_dev) { + if (-1 != vout->video_dev->minor) + video_unregister_device(vout->video_dev); + else + video_device_release(vout->video_dev); + vout->video_dev = NULL; + } + + platform_set_drvdata(pdev, NULL); + + kfree(vout); + + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxc_v4l2out_driver = { + .driver = { + .name = "MXC Video Output", + }, + .probe = mxc_v4l2out_probe, + .remove = mxc_v4l2out_remove, +}; + +static struct platform_device mxc_v4l2out_device = { + .name = "MXC Video Output", + .id = 0, +}; + +/*! + * mxc v4l2 init function + * + */ +static int mxc_v4l2out_init(void) +{ + u8 err = 0; + + err = platform_driver_register(&mxc_v4l2out_driver); + if (err == 0) { + platform_device_register(&mxc_v4l2out_device); + } + return err; +} + +/*! + * mxc v4l2 cleanup function + * + */ +static void mxc_v4l2out_clean(void) +{ + video_unregister_device(g_vout->video_dev); + + platform_driver_unregister(&mxc_v4l2out_driver); + platform_device_unregister(&mxc_v4l2out_device); + kfree(g_vout); + g_vout = NULL; +} + +module_init(mxc_v4l2out_init); +module_exit(mxc_v4l2out_clean); + +module_param(video_nr, int, 0444); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("V4L2-driver for MXC video output"); +MODULE_LICENSE("GPL"); +MODULE_SUPPORTED_DEVICE("video"); diff -urN linux-2.6.26/drivers/media/video/mxc/output/mxc_v4l2_output.h linux-2.6.26-lab126/drivers/media/video/mxc/output/mxc_v4l2_output.h --- linux-2.6.26/drivers/media/video/mxc/output/mxc_v4l2_output.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/media/video/mxc/output/mxc_v4l2_output.h 2010-08-10 04:15:21.000000000 -0400 @@ -0,0 +1,132 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup MXC_V4L2_OUTPUT MXC V4L2 Video Output Driver + */ +/*! + * @file mxc_v4l2_output.h + * + * @brief MXC V4L2 Video Output Driver Header file + * + * Video4Linux2 Output Device using MXC IPU Post-processing functionality. + * + * @ingroup MXC_V4L2_OUTPUT + */ +#ifndef __MXC_V4L2_OUTPUT_H__ +#define __MXC_V4L2_OUTPUT_H__ + +#include + +#ifdef __KERNEL__ + +#include +#include + +#define MIN_FRAME_NUM 2 +#define MAX_FRAME_NUM 30 + +#define MXC_V4L2_OUT_NUM_OUTPUTS 6 +#define MXC_V4L2_OUT_2_SDC 0 +#define MXC_V4L2_OUT_2_ADC 1 + +typedef struct { + int list[MAX_FRAME_NUM + 1]; + int head; + int tail; +} v4l_queue; + +/*! + * States for the video stream + */ +typedef enum { + STATE_STREAM_OFF, + STATE_STREAM_ON, + STATE_STREAM_PAUSED, + STATE_STREAM_STOPPING, +} v4lout_state; + +/*! + * common v4l2 driver structure. + */ +typedef struct _vout_data { + struct video_device *video_dev; + /*! + * semaphore guard against SMP multithreading + */ + struct semaphore busy_lock; + + /*! + * number of process that have device open + */ + int open_count; + + /*! + * params lock for this camera + */ + struct semaphore param_lock; + + struct timer_list output_timer; + unsigned long start_jiffies; + u32 frame_count; + + v4l_queue ready_q; + v4l_queue done_q; + + s8 next_rdy_ipu_buf; + s8 next_done_ipu_buf; + s8 ipu_buf[2]; + volatile v4lout_state state; + + int cur_disp_output; + int output_fb_num[MXC_V4L2_OUT_NUM_OUTPUTS]; + int output_enabled[MXC_V4L2_OUT_NUM_OUTPUTS]; + struct v4l2_framebuffer v4l2_fb; + ipu_channel_t display_ch; + ipu_channel_t post_proc_ch; + + /*! + * FRAME_NUM-buffering, so we need a array + */ + int buffer_cnt; + dma_addr_t queue_buf_paddr[MAX_FRAME_NUM]; + void *queue_buf_vaddr[MAX_FRAME_NUM]; + u32 queue_buf_size; + struct v4l2_buffer v4l2_bufs[MAX_FRAME_NUM]; + u32 display_buf_size; + dma_addr_t display_bufs[2]; + void *display_bufs_vaddr[2]; + dma_addr_t rot_pp_bufs[2]; + void *rot_pp_bufs_vaddr[2]; + + /*! + * Poll wait queue + */ + wait_queue_head_t v4l_bufq; + + /*! + * v4l2 format + */ + struct v4l2_format v2f; + struct v4l2_mxc_offset offset; + ipu_rotate_mode_t rotate; + + /* crop */ + struct v4l2_rect crop_bounds[MXC_V4L2_OUT_NUM_OUTPUTS]; + struct v4l2_rect crop_current; + + struct work_struct timer_work; +} vout_data; + +#endif +#endif /* __MXC_V4L2_OUTPUT_H__ */ diff -urN linux-2.6.26/drivers/media/video/v4l2-int-device.c linux-2.6.26-lab126/drivers/media/video/v4l2-int-device.c --- linux-2.6.26/drivers/media/video/v4l2-int-device.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/media/video/v4l2-int-device.c 2010-08-10 04:15:24.000000000 -0400 @@ -145,6 +145,8 @@ (v4l2_int_ioctl_func *)no_such_ioctl_0))(d); } +EXPORT_SYMBOL(v4l2_int_ioctl_0); + static int no_such_ioctl_1(struct v4l2_int_device *d, void *arg) { return -ENOIOCTLCMD; @@ -157,4 +159,5 @@ (v4l2_int_ioctl_func *)no_such_ioctl_1))(d, arg); } -MODULE_LICENSE("GPL"); +EXPORT_SYMBOL(v4l2_int_ioctl_1); + diff -urN linux-2.6.26/drivers/mmc/card/Kconfig linux-2.6.26-lab126/drivers/mmc/card/Kconfig --- linux-2.6.26/drivers/mmc/card/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/card/Kconfig 2010-08-10 04:15:59.000000000 -0400 @@ -51,3 +51,15 @@ This driver is only of interest to those developing or testing a host driver. Most people should say N here. + +config SDIO_UNIFI_FS + tristate "UniFi SDIO glue for Freescale MMC/SDIO" + depends on (MMC_MXC || MMC_IMX_ESDHCI) + depends on (MACH_MX31_3DS || MACH_MX35_3DS || MACH_MX37_3DS || MACH_MX51_3DS) + help + This provides an interface between the CSR UniFi WiFi + driver and the Freescale MMC/SDIO interface. + If you have a MXC platform with a UniFi WiFi chip, + say M here. + + If unsure, say N. diff -urN linux-2.6.26/drivers/mmc/card/Makefile linux-2.6.26-lab126/drivers/mmc/card/Makefile --- linux-2.6.26/drivers/mmc/card/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/card/Makefile 2010-08-10 04:15:59.000000000 -0400 @@ -12,3 +12,4 @@ obj-$(CONFIG_SDIO_UART) += sdio_uart.o +obj-$(CONFIG_SDIO_UNIFI_FS) += unifi_fs/ diff -urN linux-2.6.26/drivers/mmc/card/block.c linux-2.6.26-lab126/drivers/mmc/card/block.c --- linux-2.6.26/drivers/mmc/card/block.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/card/block.c 2010-08-10 04:15:59.000000000 -0400 @@ -3,6 +3,8 @@ * * Copyright 2002 Hewlett-Packard Company * Copyright 2005-2007 Pierre Ossman + * Copyright 2009 Amazon Technologies Inc. + * Manish Lachwani (lachwani@lab126.com) * * Use consistent with the GNU GPL is permitted, * provided that this copyright notice is @@ -57,7 +59,6 @@ struct mmc_queue queue; unsigned int usage; - unsigned int block_bits; unsigned int read_only; }; @@ -208,18 +209,36 @@ return blocks; } +static u32 get_card_status(struct mmc_card *card, struct request *req) +{ + struct mmc_command cmd; + int err; + + memset(&cmd, 0, sizeof(struct mmc_command)); + cmd.opcode = MMC_SEND_STATUS; + if (!mmc_host_is_spi(card->host)) + cmd.arg = card->rca << 16; + cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC; + err = mmc_wait_for_cmd(card->host, &cmd, 0); + if (err) + printk(KERN_ERR "%s: error %d sending status comand", + req->rq_disk->disk_name, err); + return cmd.resp[0]; +} + static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req) { struct mmc_blk_data *md = mq->data; struct mmc_card *card = md->queue.card; struct mmc_blk_request brq; - int ret = 1, sg_pos, data_size; + int ret = 1; + int disable_multi = 0; mmc_claim_host(card->host); do { struct mmc_command cmd; - u32 readcmd, writecmd; + u32 readcmd, writecmd, status = 0; memset(&brq, 0, sizeof(struct mmc_blk_request)); brq.mrq.cmd = &brq.cmd; @@ -229,25 +248,28 @@ if (!mmc_card_blockaddr(card)) brq.cmd.arg <<= 9; brq.cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC; - brq.data.blksz = 1 << md->block_bits; + brq.data.blksz = 512; brq.stop.opcode = MMC_STOP_TRANSMISSION; brq.stop.arg = 0; brq.stop.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC; - brq.data.blocks = req->nr_sectors >> (md->block_bits - 9); + brq.data.blocks = req->nr_sectors; + +#ifdef CONFIG_MACH_MX35_LUIGI if (brq.data.blocks > card->host->max_blk_count) brq.data.blocks = card->host->max_blk_count; +#endif /* - * If the host doesn't support multiple block writes, force - * block writes to single block. SD cards are excepted from - * this rule as they support querying the number of - * successfully written sectors. + * After a read error, we redo the request one sector at a time + * in order to accurately determine which sectors can be read + * successfully. */ - if (rq_data_dir(req) != READ && - !(card->host->caps & MMC_CAP_MULTIWRITE) && - !mmc_card_sd(card)) + if (disable_multi && brq.data.blocks > 1) brq.data.blocks = 1; + if (brq.data.blocks > card->host->max_blk_count) + brq.data.blocks = card->host->max_blk_count; + if (brq.data.blocks > 1) { /* SPI multiblock writes terminate using a special * token, not a STOP_TRANSMISSION request. @@ -263,6 +285,36 @@ writecmd = MMC_WRITE_BLOCK; } +#ifdef CONFIG_MACH_LUIGI_LAB126 + /* + * Samsung moviNAND devices cannot work in + * open-ended mode. They can only work in + * predefined mode. However, all versions of the + * Samsung moviNAND firmware do not support + * predefined mode. Look at drivers/mmc/core/mmc.c + * for the mechanism to detect predefined mode. + * + * If predefined mode is set for the card, then + * Samsung moviNAND show failure if STOP_TRANSMISSION + * command is sent to the card. So, we have to prevent + * the STOP_TRANSMISSION command as well in predefined mode. + * + * Finally, Freescale MX35 MMC controller needs clock + * for setting the predefined mode using CMD23. This + * takes care of the clock as well. + * + * - Manish Lachwani (09/15/2009) + */ + if ( (brq.data.blocks > 1) && + (card->host->predefined == 1)) { + struct mmc_command cmd1; + cmd1.opcode = MMC_SET_BLOCK_COUNT; + cmd1.arg = brq.data.blocks; + cmd1.flags = MMC_RSP_R1 | MMC_CMD_AC; + mmc_wait_for_cmd(card->host, &cmd1, 5); + brq.mrq.stop = NULL; + } +#endif if (rq_data_dir(req) == READ) { brq.cmd.opcode = readcmd; brq.data.flags |= MMC_DATA_READ; @@ -276,42 +328,65 @@ brq.data.sg = mq->sg; brq.data.sg_len = mmc_queue_map_sg(mq); - mmc_queue_bounce_pre(mq); + /* + * Adjust the sg list so it is the same size as the + * request. + */ + if (brq.data.blocks != req->nr_sectors) { + int i, data_size = brq.data.blocks << 9; + struct scatterlist *sg; - if (brq.data.blocks != - (req->nr_sectors >> (md->block_bits - 9))) { - data_size = brq.data.blocks * brq.data.blksz; - for (sg_pos = 0; sg_pos < brq.data.sg_len; sg_pos++) { - data_size -= mq->sg[sg_pos].length; + for_each_sg(brq.data.sg, sg, brq.data.sg_len, i) { + data_size -= sg->length; if (data_size <= 0) { - mq->sg[sg_pos].length += data_size; - sg_pos++; + sg->length += data_size; + i++; break; } } - brq.data.sg_len = sg_pos; + brq.data.sg_len = i; } + mmc_queue_bounce_pre(mq); + mmc_wait_for_req(card->host, &brq.mrq); mmc_queue_bounce_post(mq); + if (brq.cmd.error || brq.data.error || brq.stop.error) { + if (brq.data.blocks > 1 && rq_data_dir(req) == READ) { + /* Redo read one sector at a time */ + printk(KERN_WARNING "%s: retrying using single " + "block read\n", req->rq_disk->disk_name); + disable_multi = 1; + continue; + } + status = get_card_status(card, req); + } + if (brq.cmd.error) { - printk(KERN_ERR "%s: error %d sending read/write command\n", - req->rq_disk->disk_name, brq.cmd.error); - goto cmd_err; + printk(KERN_ERR "%s: error %d sending read/write " + "command, response %#x, card status %#x\n", + req->rq_disk->disk_name, brq.cmd.error, + brq.cmd.resp[0], status); } if (brq.data.error) { - printk(KERN_ERR "%s: error %d transferring data\n", - req->rq_disk->disk_name, brq.data.error); - goto cmd_err; + if (brq.data.error == -ETIMEDOUT && brq.mrq.stop) + /* 'Stop' response contains card status */ + status = brq.mrq.stop->resp[0]; + printk(KERN_ERR "%s: error %d transferring data," + " sector %u, nr %u, card status %#x\n", + req->rq_disk->disk_name, brq.data.error, + (unsigned)req->sector, + (unsigned)req->nr_sectors, status); } if (brq.stop.error) { - printk(KERN_ERR "%s: error %d sending stop command\n", - req->rq_disk->disk_name, brq.stop.error); - goto cmd_err; + printk(KERN_ERR "%s: error %d sending stop command, " + "response %#x, card status %#x\n", + req->rq_disk->disk_name, brq.stop.error, + brq.stop.resp[0], status); } if (!mmc_host_is_spi(card->host) && rq_data_dir(req) != READ) { @@ -344,6 +419,21 @@ #endif } + if (brq.cmd.error || brq.stop.error || brq.data.error) { + if (rq_data_dir(req) == READ) { + /* + * After an error, we redo I/O one sector at a + * time, so we only reach here after trying to + * read a single sector. + */ + spin_lock_irq(&md->lock); + ret = __blk_end_request(req, -EIO, brq.data.blksz); + spin_unlock_irq(&md->lock); + continue; + } + goto cmd_err; + } + /* * A block was successfully transferred. */ @@ -356,33 +446,25 @@ return 1; - cmd_err: +cmd_err: /* * If this is an SD card and we're writing, we can first * mark the known good sectors as ok. * * If the card is not SD, we can still ok written sectors - * if the controller can do proper error reporting. - * - * For reads we just fail the entire chunk as that should - * be safe in all cases. + * as reported by the controller (which might be less than + * the real number of written sectors, but never more). */ - if (rq_data_dir(req) != READ && mmc_card_sd(card)) { + if (mmc_card_sd(card)) { u32 blocks; - unsigned int bytes; blocks = mmc_sd_num_wr_blocks(card); if (blocks != (u32)-1) { - if (card->csd.write_partial) - bytes = blocks << md->block_bits; - else - bytes = blocks << 9; spin_lock_irq(&md->lock); - ret = __blk_end_request(req, 0, bytes); + ret = __blk_end_request(req, 0, blocks << 9); spin_unlock_irq(&md->lock); } - } else if (rq_data_dir(req) != READ && - (card->host->caps & MMC_CAP_MULTIWRITE)) { + } else { spin_lock_irq(&md->lock); ret = __blk_end_request(req, 0, brq.data.bytes_xfered); spin_unlock_irq(&md->lock); @@ -428,13 +510,6 @@ */ md->read_only = mmc_blk_readonly(card); - /* - * Both SD and MMC specifications state (although a bit - * unclearly in the MMC case) that a block size of 512 - * bytes must always be supported by the card. - */ - md->block_bits = 9; - md->disk = alloc_disk(1 << MMC_SHIFT); if (md->disk == NULL) { ret = -ENOMEM; @@ -472,7 +547,7 @@ sprintf(md->disk->disk_name, "mmcblk%d", devidx); - blk_queue_hardsect_size(md->queue.queue, 1 << md->block_bits); + blk_queue_hardsect_size(md->queue.queue, 512); if (!mmc_card_sd(card) && mmc_card_blockaddr(card)) { /* @@ -510,7 +585,7 @@ mmc_claim_host(card->host); cmd.opcode = MMC_SET_BLOCKLEN; - cmd.arg = 1 << md->block_bits; + cmd.arg = 512; cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC; err = mmc_wait_for_cmd(card->host, &cmd, 5); mmc_release_host(card->host); @@ -553,6 +628,7 @@ return 0; out: + mmc_cleanup_queue(&md->queue); mmc_blk_put(md); return err; diff -urN linux-2.6.26/drivers/mmc/card/mmc_test.c linux-2.6.26-lab126/drivers/mmc/card/mmc_test.c --- linux-2.6.26/drivers/mmc/card/mmc_test.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/card/mmc_test.c 2010-08-10 04:15:59.000000000 -0400 @@ -26,13 +26,17 @@ struct mmc_test_card { struct mmc_card *card; + u8 scratch[BUFFER_SIZE]; u8 *buffer; }; /*******************************************************************/ -/* Helper functions */ +/* General helper functions */ /*******************************************************************/ +/* + * Configure correct block size in card + */ static int mmc_test_set_blksize(struct mmc_test_card *test, unsigned size) { struct mmc_command cmd; @@ -48,117 +52,65 @@ return 0; } -static int __mmc_test_transfer(struct mmc_test_card *test, int write, - unsigned broken_xfer, u8 *buffer, unsigned addr, - unsigned blocks, unsigned blksz) -{ - int ret, busy; - - struct mmc_request mrq; - struct mmc_command cmd; - struct mmc_command stop; - struct mmc_data data; - - struct scatterlist sg; - - memset(&mrq, 0, sizeof(struct mmc_request)); - - mrq.cmd = &cmd; - mrq.data = &data; - - memset(&cmd, 0, sizeof(struct mmc_command)); - - if (broken_xfer) { - if (blocks > 1) { - cmd.opcode = write ? - MMC_WRITE_BLOCK : MMC_READ_SINGLE_BLOCK; - } else { - cmd.opcode = MMC_SEND_STATUS; - } +/* + * Fill in the mmc_request structure given a set of transfer parameters. + */ +static void mmc_test_prepare_mrq(struct mmc_test_card *test, + struct mmc_request *mrq, struct scatterlist *sg, unsigned sg_len, + unsigned dev_addr, unsigned blocks, unsigned blksz, int write) +{ + BUG_ON(!mrq || !mrq->cmd || !mrq->data || !mrq->stop); + + if (blocks > 1) { + mrq->cmd->opcode = write ? + MMC_WRITE_MULTIPLE_BLOCK : MMC_READ_MULTIPLE_BLOCK; } else { - if (blocks > 1) { - cmd.opcode = write ? - MMC_WRITE_MULTIPLE_BLOCK : MMC_READ_MULTIPLE_BLOCK; - } else { - cmd.opcode = write ? - MMC_WRITE_BLOCK : MMC_READ_SINGLE_BLOCK; - } + mrq->cmd->opcode = write ? + MMC_WRITE_BLOCK : MMC_READ_SINGLE_BLOCK; } - if (broken_xfer && blocks == 1) - cmd.arg = test->card->rca << 16; - else - cmd.arg = addr; - cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; + mrq->cmd->arg = dev_addr; - memset(&stop, 0, sizeof(struct mmc_command)); + if (!mmc_card_blockaddr(test->card)) + mrq->cmd->arg <<= 9; - if (!broken_xfer && (blocks > 1)) { - stop.opcode = MMC_STOP_TRANSMISSION; - stop.arg = 0; - stop.flags = MMC_RSP_R1B | MMC_CMD_AC; + mrq->cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC; - mrq.stop = &stop; + if (blocks == 1) + mrq->stop = NULL; + else { + mrq->stop->opcode = MMC_STOP_TRANSMISSION; + mrq->stop->arg = 0; + mrq->stop->flags = MMC_RSP_R1B | MMC_CMD_AC; } - memset(&data, 0, sizeof(struct mmc_data)); - - data.blksz = blksz; - data.blocks = blocks; - data.flags = write ? MMC_DATA_WRITE : MMC_DATA_READ; - data.sg = &sg; - data.sg_len = 1; - - sg_init_one(&sg, buffer, blocks * blksz); - - mmc_set_data_timeout(&data, test->card); - - mmc_wait_for_req(test->card->host, &mrq); - - ret = 0; - - if (broken_xfer) { - if (!ret && cmd.error) - ret = cmd.error; - if (!ret && data.error == 0) - ret = RESULT_FAIL; - if (!ret && data.error != -ETIMEDOUT) - ret = data.error; - if (!ret && stop.error) - ret = stop.error; - if (blocks > 1) { - if (!ret && data.bytes_xfered > blksz) - ret = RESULT_FAIL; - } else { - if (!ret && data.bytes_xfered > 0) - ret = RESULT_FAIL; - } - } else { - if (!ret && cmd.error) - ret = cmd.error; - if (!ret && data.error) - ret = data.error; - if (!ret && stop.error) - ret = stop.error; - if (!ret && data.bytes_xfered != blocks * blksz) - ret = RESULT_FAIL; - } + mrq->data->blksz = blksz; + mrq->data->blocks = blocks; + mrq->data->flags = write ? MMC_DATA_WRITE : MMC_DATA_READ; + mrq->data->sg = sg; + mrq->data->sg_len = sg_len; + + mmc_set_data_timeout(mrq->data, test->card); +} - if (ret == -EINVAL) - ret = RESULT_UNSUP_HOST; +/* + * Wait for the card to finish the busy state + */ +static int mmc_test_wait_busy(struct mmc_test_card *test) +{ + int ret, busy; + struct mmc_command cmd; busy = 0; do { - int ret2; - memset(&cmd, 0, sizeof(struct mmc_command)); cmd.opcode = MMC_SEND_STATUS; cmd.arg = test->card->rca << 16; cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; - ret2 = mmc_wait_for_cmd(test->card->host, &cmd, 0); - if (ret2) + ret = mmc_wait_for_cmd(test->card->host, &cmd, 0); + if (ret) break; if (!busy && !(cmd.resp[0] & R1_READY_FOR_DATA)) { @@ -172,14 +124,57 @@ return ret; } -static int mmc_test_transfer(struct mmc_test_card *test, int write, - u8 *buffer, unsigned addr, unsigned blocks, unsigned blksz) +/* + * Transfer a single sector of kernel addressable data + */ +static int mmc_test_buffer_transfer(struct mmc_test_card *test, + u8 *buffer, unsigned addr, unsigned blksz, int write) { - return __mmc_test_transfer(test, write, 0, buffer, - addr, blocks, blksz); + int ret; + + struct mmc_request mrq; + struct mmc_command cmd; + struct mmc_command stop; + struct mmc_data data; + + struct scatterlist sg; + + memset(&mrq, 0, sizeof(struct mmc_request)); + memset(&cmd, 0, sizeof(struct mmc_command)); + memset(&data, 0, sizeof(struct mmc_data)); + memset(&stop, 0, sizeof(struct mmc_command)); + + mrq.cmd = &cmd; + mrq.data = &data; + mrq.stop = &stop; + + sg_init_one(&sg, buffer, blksz); + + mmc_test_prepare_mrq(test, &mrq, &sg, 1, addr, 1, blksz, write); + + mmc_wait_for_req(test->card->host, &mrq); + + if (cmd.error) + return cmd.error; + if (data.error) + return data.error; + + ret = mmc_test_wait_busy(test); + if (ret) + return ret; + + return 0; } -static int mmc_test_prepare_verify(struct mmc_test_card *test, int write) +/*******************************************************************/ +/* Test preparation and cleanup */ +/*******************************************************************/ + +/* + * Fill the first couple of sectors of the card with known data + * so that bad reads/writes can be detected + */ +static int __mmc_test_prepare(struct mmc_test_card *test, int write) { int ret, i; @@ -188,15 +183,43 @@ return ret; if (write) - memset(test->buffer, 0xDF, BUFFER_SIZE); + memset(test->buffer, 0xDF, 512); else { - for (i = 0;i < BUFFER_SIZE;i++) + for (i = 0;i < 512;i++) test->buffer[i] = i; } for (i = 0;i < BUFFER_SIZE / 512;i++) { - ret = mmc_test_transfer(test, 1, test->buffer + i * 512, - i * 512, 1, 512); + ret = mmc_test_buffer_transfer(test, test->buffer, i, 512, 1); + if (ret) + return ret; + } + + return 0; +} + +static int mmc_test_prepare_write(struct mmc_test_card *test) +{ + return __mmc_test_prepare(test, 1); +} + +static int mmc_test_prepare_read(struct mmc_test_card *test) +{ + return __mmc_test_prepare(test, 0); +} + +static int mmc_test_cleanup(struct mmc_test_card *test) +{ + int ret, i; + + ret = mmc_test_set_blksize(test, 512); + if (ret) + return ret; + + memset(test->buffer, 0, 512); + + for (i = 0;i < BUFFER_SIZE / 512;i++) { + ret = mmc_test_buffer_transfer(test, test->buffer, i, 512, 1); if (ret) return ret; } @@ -204,41 +227,189 @@ return 0; } -static int mmc_test_prepare_verify_write(struct mmc_test_card *test) +/*******************************************************************/ +/* Test execution helpers */ +/*******************************************************************/ + +/* + * Modifies the mmc_request to perform the "short transfer" tests + */ +static void mmc_test_prepare_broken_mrq(struct mmc_test_card *test, + struct mmc_request *mrq, int write) +{ + BUG_ON(!mrq || !mrq->cmd || !mrq->data); + + if (mrq->data->blocks > 1) { + mrq->cmd->opcode = write ? + MMC_WRITE_BLOCK : MMC_READ_SINGLE_BLOCK; + mrq->stop = NULL; + } else { + mrq->cmd->opcode = MMC_SEND_STATUS; + mrq->cmd->arg = test->card->rca << 16; + } +} + +/* + * Checks that a normal transfer didn't have any errors + */ +static int mmc_test_check_result(struct mmc_test_card *test, + struct mmc_request *mrq) +{ + int ret; + + BUG_ON(!mrq || !mrq->cmd || !mrq->data); + + ret = 0; + + if (!ret && mrq->cmd->error) + ret = mrq->cmd->error; + if (!ret && mrq->data->error) + ret = mrq->data->error; + if (!ret && mrq->stop && mrq->stop->error) + ret = mrq->stop->error; + if (!ret && mrq->data->bytes_xfered != + mrq->data->blocks * mrq->data->blksz) + ret = RESULT_FAIL; + + if (ret == -EINVAL) + ret = RESULT_UNSUP_HOST; + + return ret; +} + +/* + * Checks that a "short transfer" behaved as expected + */ +static int mmc_test_check_broken_result(struct mmc_test_card *test, + struct mmc_request *mrq) { - return mmc_test_prepare_verify(test, 1); + int ret; + + BUG_ON(!mrq || !mrq->cmd || !mrq->data); + + ret = 0; + + if (!ret && mrq->cmd->error) + ret = mrq->cmd->error; + if (!ret && mrq->data->error == 0) + ret = RESULT_FAIL; + if (!ret && mrq->data->error != -ETIMEDOUT) + ret = mrq->data->error; + if (!ret && mrq->stop && mrq->stop->error) + ret = mrq->stop->error; + if (mrq->data->blocks > 1) { + if (!ret && mrq->data->bytes_xfered > mrq->data->blksz) + ret = RESULT_FAIL; + } else { + if (!ret && mrq->data->bytes_xfered > 0) + ret = RESULT_FAIL; + } + + if (ret == -EINVAL) + ret = RESULT_UNSUP_HOST; + + return ret; } -static int mmc_test_prepare_verify_read(struct mmc_test_card *test) +/* + * Tests a basic transfer with certain parameters + */ +static int mmc_test_simple_transfer(struct mmc_test_card *test, + struct scatterlist *sg, unsigned sg_len, unsigned dev_addr, + unsigned blocks, unsigned blksz, int write) { - return mmc_test_prepare_verify(test, 0); + struct mmc_request mrq; + struct mmc_command cmd; + struct mmc_command stop; + struct mmc_data data; + + memset(&mrq, 0, sizeof(struct mmc_request)); + memset(&cmd, 0, sizeof(struct mmc_command)); + memset(&data, 0, sizeof(struct mmc_data)); + memset(&stop, 0, sizeof(struct mmc_command)); + + mrq.cmd = &cmd; + mrq.data = &data; + mrq.stop = &stop; + + mmc_test_prepare_mrq(test, &mrq, sg, sg_len, dev_addr, + blocks, blksz, write); + + mmc_wait_for_req(test->card->host, &mrq); + + mmc_test_wait_busy(test); + + return mmc_test_check_result(test, &mrq); } -static int mmc_test_verified_transfer(struct mmc_test_card *test, int write, - u8 *buffer, unsigned addr, unsigned blocks, unsigned blksz) +/* + * Tests a transfer where the card will fail completely or partly + */ +static int mmc_test_broken_transfer(struct mmc_test_card *test, + unsigned blocks, unsigned blksz, int write) { - int ret, i, sectors; + struct mmc_request mrq; + struct mmc_command cmd; + struct mmc_command stop; + struct mmc_data data; + + struct scatterlist sg; + + memset(&mrq, 0, sizeof(struct mmc_request)); + memset(&cmd, 0, sizeof(struct mmc_command)); + memset(&data, 0, sizeof(struct mmc_data)); + memset(&stop, 0, sizeof(struct mmc_command)); + + mrq.cmd = &cmd; + mrq.data = &data; + mrq.stop = &stop; - /* - * It is assumed that the above preparation has been done. - */ + sg_init_one(&sg, test->buffer, blocks * blksz); + + mmc_test_prepare_mrq(test, &mrq, &sg, 1, 0, blocks, blksz, write); + mmc_test_prepare_broken_mrq(test, &mrq, write); + + mmc_wait_for_req(test->card->host, &mrq); - memset(test->buffer, 0, BUFFER_SIZE); + mmc_test_wait_busy(test); + + return mmc_test_check_broken_result(test, &mrq); +} + +/* + * Does a complete transfer test where data is also validated + * + * Note: mmc_test_prepare() must have been done before this call + */ +static int mmc_test_transfer(struct mmc_test_card *test, + struct scatterlist *sg, unsigned sg_len, unsigned dev_addr, + unsigned blocks, unsigned blksz, int write) +{ + int ret, i; + unsigned long flags; if (write) { for (i = 0;i < blocks * blksz;i++) - buffer[i] = i; + test->scratch[i] = i; + } else { + memset(test->scratch, 0, BUFFER_SIZE); } + local_irq_save(flags); + sg_copy_from_buffer(sg, sg_len, test->scratch, BUFFER_SIZE); + local_irq_restore(flags); ret = mmc_test_set_blksize(test, blksz); if (ret) return ret; - ret = mmc_test_transfer(test, write, buffer, addr, blocks, blksz); + ret = mmc_test_simple_transfer(test, sg, sg_len, dev_addr, + blocks, blksz, write); if (ret) return ret; if (write) { + int sectors; + ret = mmc_test_set_blksize(test, 512); if (ret) return ret; @@ -253,9 +424,9 @@ memset(test->buffer, 0, sectors * 512); for (i = 0;i < sectors;i++) { - ret = mmc_test_transfer(test, 0, + ret = mmc_test_buffer_transfer(test, test->buffer + i * 512, - addr + i * 512, 1, 512); + dev_addr + i, 512, 0); if (ret) return ret; } @@ -270,8 +441,11 @@ return RESULT_FAIL; } } else { + local_irq_save(flags); + sg_copy_to_buffer(sg, sg_len, test->scratch, BUFFER_SIZE); + local_irq_restore(flags); for (i = 0;i < blocks * blksz;i++) { - if (buffer[i] != (u8)i) + if (test->scratch[i] != (u8)i) return RESULT_FAIL; } } @@ -279,26 +453,6 @@ return 0; } -static int mmc_test_cleanup_verify(struct mmc_test_card *test) -{ - int ret, i; - - ret = mmc_test_set_blksize(test, 512); - if (ret) - return ret; - - memset(test->buffer, 0, BUFFER_SIZE); - - for (i = 0;i < BUFFER_SIZE / 512;i++) { - ret = mmc_test_transfer(test, 1, test->buffer + i * 512, - i * 512, 1, 512); - if (ret) - return ret; - } - - return 0; -} - /*******************************************************************/ /* Tests */ /*******************************************************************/ @@ -314,12 +468,15 @@ static int mmc_test_basic_write(struct mmc_test_card *test) { int ret; + struct scatterlist sg; ret = mmc_test_set_blksize(test, 512); if (ret) return ret; - ret = mmc_test_transfer(test, 1, test->buffer, 0, 1, 512); + sg_init_one(&sg, test->buffer, 512); + + ret = mmc_test_simple_transfer(test, &sg, 1, 0, 1, 512, 1); if (ret) return ret; @@ -329,12 +486,15 @@ static int mmc_test_basic_read(struct mmc_test_card *test) { int ret; + struct scatterlist sg; ret = mmc_test_set_blksize(test, 512); if (ret) return ret; - ret = mmc_test_transfer(test, 0, test->buffer, 0, 1, 512); + sg_init_one(&sg, test->buffer, 512); + + ret = mmc_test_simple_transfer(test, &sg, 1, 0, 1, 512, 0); if (ret) return ret; @@ -344,8 +504,11 @@ static int mmc_test_verify_write(struct mmc_test_card *test) { int ret; + struct scatterlist sg; + + sg_init_one(&sg, test->buffer, 512); - ret = mmc_test_verified_transfer(test, 1, test->buffer, 0, 1, 512); + ret = mmc_test_transfer(test, &sg, 1, 0, 1, 512, 1); if (ret) return ret; @@ -355,8 +518,11 @@ static int mmc_test_verify_read(struct mmc_test_card *test) { int ret; + struct scatterlist sg; + + sg_init_one(&sg, test->buffer, 512); - ret = mmc_test_verified_transfer(test, 0, test->buffer, 0, 1, 512); + ret = mmc_test_transfer(test, &sg, 1, 0, 1, 512, 0); if (ret) return ret; @@ -367,6 +533,7 @@ { int ret; unsigned int size; + struct scatterlist sg; if (test->card->host->max_blk_count == 1) return RESULT_UNSUP_HOST; @@ -379,8 +546,9 @@ if (size < 1024) return RESULT_UNSUP_HOST; - ret = mmc_test_verified_transfer(test, 1, test->buffer, 0, - size / 512, 512); + sg_init_one(&sg, test->buffer, size); + + ret = mmc_test_transfer(test, &sg, 1, 0, size/512, 512, 1); if (ret) return ret; @@ -391,6 +559,7 @@ { int ret; unsigned int size; + struct scatterlist sg; if (test->card->host->max_blk_count == 1) return RESULT_UNSUP_HOST; @@ -403,8 +572,9 @@ if (size < 1024) return RESULT_UNSUP_HOST; - ret = mmc_test_verified_transfer(test, 0, test->buffer, 0, - size / 512, 512); + sg_init_one(&sg, test->buffer, size); + + ret = mmc_test_transfer(test, &sg, 1, 0, size/512, 512, 0); if (ret) return ret; @@ -414,13 +584,14 @@ static int mmc_test_pow2_write(struct mmc_test_card *test) { int ret, i; + struct scatterlist sg; if (!test->card->csd.write_partial) return RESULT_UNSUP_CARD; for (i = 1; i < 512;i <<= 1) { - ret = mmc_test_verified_transfer(test, 1, - test->buffer, 0, 1, i); + sg_init_one(&sg, test->buffer, i); + ret = mmc_test_transfer(test, &sg, 1, 0, 1, i, 1); if (ret) return ret; } @@ -431,13 +602,14 @@ static int mmc_test_pow2_read(struct mmc_test_card *test) { int ret, i; + struct scatterlist sg; if (!test->card->csd.read_partial) return RESULT_UNSUP_CARD; for (i = 1; i < 512;i <<= 1) { - ret = mmc_test_verified_transfer(test, 0, - test->buffer, 0, 1, i); + sg_init_one(&sg, test->buffer, i); + ret = mmc_test_transfer(test, &sg, 1, 0, 1, i, 0); if (ret) return ret; } @@ -448,13 +620,14 @@ static int mmc_test_weird_write(struct mmc_test_card *test) { int ret, i; + struct scatterlist sg; if (!test->card->csd.write_partial) return RESULT_UNSUP_CARD; for (i = 3; i < 512;i += 7) { - ret = mmc_test_verified_transfer(test, 1, - test->buffer, 0, 1, i); + sg_init_one(&sg, test->buffer, i); + ret = mmc_test_transfer(test, &sg, 1, 0, 1, i, 1); if (ret) return ret; } @@ -465,13 +638,14 @@ static int mmc_test_weird_read(struct mmc_test_card *test) { int ret, i; + struct scatterlist sg; if (!test->card->csd.read_partial) return RESULT_UNSUP_CARD; for (i = 3; i < 512;i += 7) { - ret = mmc_test_verified_transfer(test, 0, - test->buffer, 0, 1, i); + sg_init_one(&sg, test->buffer, i); + ret = mmc_test_transfer(test, &sg, 1, 0, 1, i, 0); if (ret) return ret; } @@ -482,10 +656,11 @@ static int mmc_test_align_write(struct mmc_test_card *test) { int ret, i; + struct scatterlist sg; for (i = 1;i < 4;i++) { - ret = mmc_test_verified_transfer(test, 1, test->buffer + i, - 0, 1, 512); + sg_init_one(&sg, test->buffer + i, 512); + ret = mmc_test_transfer(test, &sg, 1, 0, 1, 512, 1); if (ret) return ret; } @@ -496,10 +671,11 @@ static int mmc_test_align_read(struct mmc_test_card *test) { int ret, i; + struct scatterlist sg; for (i = 1;i < 4;i++) { - ret = mmc_test_verified_transfer(test, 0, test->buffer + i, - 0, 1, 512); + sg_init_one(&sg, test->buffer + i, 512); + ret = mmc_test_transfer(test, &sg, 1, 0, 1, 512, 0); if (ret) return ret; } @@ -511,6 +687,7 @@ { int ret, i; unsigned int size; + struct scatterlist sg; if (test->card->host->max_blk_count == 1) return RESULT_UNSUP_HOST; @@ -524,8 +701,8 @@ return RESULT_UNSUP_HOST; for (i = 1;i < 4;i++) { - ret = mmc_test_verified_transfer(test, 1, test->buffer + i, - 0, size / 512, 512); + sg_init_one(&sg, test->buffer + i, size); + ret = mmc_test_transfer(test, &sg, 1, 0, size/512, 512, 1); if (ret) return ret; } @@ -537,6 +714,7 @@ { int ret, i; unsigned int size; + struct scatterlist sg; if (test->card->host->max_blk_count == 1) return RESULT_UNSUP_HOST; @@ -550,8 +728,8 @@ return RESULT_UNSUP_HOST; for (i = 1;i < 4;i++) { - ret = mmc_test_verified_transfer(test, 0, test->buffer + i, - 0, size / 512, 512); + sg_init_one(&sg, test->buffer + i, size); + ret = mmc_test_transfer(test, &sg, 1, 0, size/512, 512, 0); if (ret) return ret; } @@ -567,7 +745,7 @@ if (ret) return ret; - ret = __mmc_test_transfer(test, 1, 1, test->buffer, 0, 1, 512); + ret = mmc_test_broken_transfer(test, 1, 512, 1); if (ret) return ret; @@ -582,7 +760,7 @@ if (ret) return ret; - ret = __mmc_test_transfer(test, 0, 1, test->buffer, 0, 1, 512); + ret = mmc_test_broken_transfer(test, 1, 512, 0); if (ret) return ret; @@ -600,7 +778,7 @@ if (ret) return ret; - ret = __mmc_test_transfer(test, 1, 1, test->buffer, 0, 2, 512); + ret = mmc_test_broken_transfer(test, 2, 512, 1); if (ret) return ret; @@ -618,7 +796,7 @@ if (ret) return ret; - ret = __mmc_test_transfer(test, 0, 1, test->buffer, 0, 2, 512); + ret = mmc_test_broken_transfer(test, 2, 512, 0); if (ret) return ret; @@ -638,86 +816,86 @@ { .name = "Basic write (with data verification)", - .prepare = mmc_test_prepare_verify_write, + .prepare = mmc_test_prepare_write, .run = mmc_test_verify_write, - .cleanup = mmc_test_cleanup_verify, + .cleanup = mmc_test_cleanup, }, { .name = "Basic read (with data verification)", - .prepare = mmc_test_prepare_verify_read, + .prepare = mmc_test_prepare_read, .run = mmc_test_verify_read, - .cleanup = mmc_test_cleanup_verify, + .cleanup = mmc_test_cleanup, }, { .name = "Multi-block write", - .prepare = mmc_test_prepare_verify_write, + .prepare = mmc_test_prepare_write, .run = mmc_test_multi_write, - .cleanup = mmc_test_cleanup_verify, + .cleanup = mmc_test_cleanup, }, { .name = "Multi-block read", - .prepare = mmc_test_prepare_verify_read, + .prepare = mmc_test_prepare_read, .run = mmc_test_multi_read, - .cleanup = mmc_test_cleanup_verify, + .cleanup = mmc_test_cleanup, }, { .name = "Power of two block writes", - .prepare = mmc_test_prepare_verify_write, + .prepare = mmc_test_prepare_write, .run = mmc_test_pow2_write, - .cleanup = mmc_test_cleanup_verify, + .cleanup = mmc_test_cleanup, }, { .name = "Power of two block reads", - .prepare = mmc_test_prepare_verify_read, + .prepare = mmc_test_prepare_read, .run = mmc_test_pow2_read, - .cleanup = mmc_test_cleanup_verify, + .cleanup = mmc_test_cleanup, }, { .name = "Weird sized block writes", - .prepare = mmc_test_prepare_verify_write, + .prepare = mmc_test_prepare_write, .run = mmc_test_weird_write, - .cleanup = mmc_test_cleanup_verify, + .cleanup = mmc_test_cleanup, }, { .name = "Weird sized block reads", - .prepare = mmc_test_prepare_verify_read, + .prepare = mmc_test_prepare_read, .run = mmc_test_weird_read, - .cleanup = mmc_test_cleanup_verify, + .cleanup = mmc_test_cleanup, }, { .name = "Badly aligned write", - .prepare = mmc_test_prepare_verify_write, + .prepare = mmc_test_prepare_write, .run = mmc_test_align_write, - .cleanup = mmc_test_cleanup_verify, + .cleanup = mmc_test_cleanup, }, { .name = "Badly aligned read", - .prepare = mmc_test_prepare_verify_read, + .prepare = mmc_test_prepare_read, .run = mmc_test_align_read, - .cleanup = mmc_test_cleanup_verify, + .cleanup = mmc_test_cleanup, }, { .name = "Badly aligned multi-block write", - .prepare = mmc_test_prepare_verify_write, + .prepare = mmc_test_prepare_write, .run = mmc_test_align_multi_write, - .cleanup = mmc_test_cleanup_verify, + .cleanup = mmc_test_cleanup, }, { .name = "Badly aligned multi-block read", - .prepare = mmc_test_prepare_verify_read, + .prepare = mmc_test_prepare_read, .run = mmc_test_align_multi_read, - .cleanup = mmc_test_cleanup_verify, + .cleanup = mmc_test_cleanup, }, { @@ -741,7 +919,7 @@ }, }; -static struct mutex mmc_test_lock; +static DEFINE_MUTEX(mmc_test_lock); static void mmc_test_run(struct mmc_test_card *test) { @@ -852,12 +1030,12 @@ { int ret; - mutex_init(&mmc_test_lock); - ret = device_create_file(&card->dev, &dev_attr_test); if (ret) return ret; + dev_info(&card->dev, "Card claimed for testing.\n"); + return 0; } diff -urN linux-2.6.26/drivers/mmc/card/queue.c linux-2.6.26-lab126/drivers/mmc/card/queue.c --- linux-2.6.26/drivers/mmc/card/queue.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/card/queue.c 2010-08-10 04:15:59.000000000 -0400 @@ -142,14 +142,22 @@ bouncesz = host->max_req_size; if (bouncesz > host->max_seg_size) bouncesz = host->max_seg_size; + if (bouncesz > (host->max_blk_count * 512)) + bouncesz = host->max_blk_count * 512; - mq->bounce_buf = kmalloc(bouncesz, GFP_KERNEL); - if (!mq->bounce_buf) { - printk(KERN_WARNING "%s: unable to allocate " - "bounce buffer\n", mmc_card_name(card)); - } else { + if (bouncesz > 512) { + mq->bounce_buf = kmalloc(bouncesz, GFP_KERNEL); + if (!mq->bounce_buf) { + printk(KERN_WARNING "%s: unable to " + "allocate bounce buffer\n", + mmc_card_name(card)); + } + } + + if (mq->bounce_buf) { blk_queue_bounce_limit(mq->queue, BLK_BOUNCE_HIGH); - blk_queue_max_sectors(mq->queue, bouncesz / 512); + blk_queue_max_sectors(mq->queue, + min(host->max_blk_count, host->max_req_size / 512)); blk_queue_max_phys_segments(mq->queue, bouncesz / 512); blk_queue_max_hw_segments(mq->queue, bouncesz / 512); blk_queue_max_segment_size(mq->queue, bouncesz); diff -urN linux-2.6.26/drivers/mmc/card/unifi_fs/Makefile linux-2.6.26-lab126/drivers/mmc/card/unifi_fs/Makefile --- linux-2.6.26/drivers/mmc/card/unifi_fs/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mmc/card/unifi_fs/Makefile 2010-08-10 04:15:59.000000000 -0400 @@ -0,0 +1,2 @@ +obj-$(CONFIG_SDIO_UNIFI_FS) = unifi_fs.o +unifi_fs-objs = fs_lx.o diff -urN linux-2.6.26/drivers/mmc/card/unifi_fs/fs_lx.c linux-2.6.26-lab126/drivers/mmc/card/unifi_fs/fs_lx.c --- linux-2.6.26/drivers/mmc/card/unifi_fs/fs_lx.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mmc/card/unifi_fs/fs_lx.c 2010-08-10 04:15:59.000000000 -0400 @@ -0,0 +1,684 @@ +/* + * fs_lx.c - Freescale SDIO glue module for UniFi. + * + * Copyright (C) 2008 Cambridge Silicon Radio Ltd. + * + * Important: + * This module does not support more than one device driver instances. + * + */ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include + +#include "fs_sdio_api.h" + +struct regulator_unifi { + struct regulator *reg_gpo1; + struct regulator *reg_gpo2; + struct regulator *reg_1v5_ana_bb; + struct regulator *reg_vdd_vpa; + struct regulator *reg_1v5_dd; +}; + +static struct sdio_driver sdio_unifi_driver; + +static int fs_sdio_probe(struct sdio_func *func, + const struct sdio_device_id *id); +static void fs_sdio_remove(struct sdio_func *func); +static void fs_sdio_irq(struct sdio_func *func); +static int fs_sdio_suspend(struct device *dev, pm_message_t state); +static int fs_sdio_resume(struct device *dev); +static int do_sdio_hard_reset(struct sdio_dev *fdev); + +/* Globals to store the context to this module and the device driver */ +static struct sdio_dev *available_sdio_dev; +static struct fs_driver *available_driver; +struct mxc_unifi_platform_data *plat_data; + +extern void mxc_mmc_force_detect(int id); + +enum sdio_cmd_direction { + CMD_READ, + CMD_WRITE, +}; + +static int fsl_io_rw_direct(struct mmc_card *card, int write, unsigned fn, + unsigned addr, u8 in, u8 *out) +{ + struct mmc_command cmd; + int err; + + BUG_ON(!card); + BUG_ON(fn > 7); + + memset(&cmd, 0, sizeof(struct mmc_command)); + + cmd.opcode = SD_IO_RW_DIRECT; + cmd.arg = write ? 0x80000000 : 0x00000000; + cmd.arg |= fn << 28; + cmd.arg |= (write && out) ? 0x08000000 : 0x00000000; + cmd.arg |= addr << 9; + cmd.arg |= in; + cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; + + err = mmc_wait_for_cmd(card->host, &cmd, 0); + if (err) + return err; + + if (mmc_host_is_spi(card->host)) { + /* host driver already reported errors */ + } else { + if (cmd.resp[0] & R5_ERROR) + return -EIO; + if (cmd.resp[0] & R5_FUNCTION_NUMBER) + return -EINVAL; + if (cmd.resp[0] & R5_OUT_OF_RANGE) + return -ERANGE; + } + + if (out) { + if (mmc_host_is_spi(card->host)) + *out = (cmd.resp[0] >> 8) & 0xFF; + else + *out = cmd.resp[0] & 0xFF; + } + + return 0; +} + + +int fs_sdio_readb(struct sdio_dev *fdev, int funcnum, unsigned long addr, + unsigned char *pdata) +{ + int err; + char val; + + sdio_claim_host(fdev->func); + if (funcnum == 0) + val = sdio_f0_readb(fdev->func, (unsigned int)addr, &err); + else + val = sdio_readb(fdev->func, (unsigned int)addr, &err); + sdio_release_host(fdev->func); + if (!err) + *pdata = val; + else + printk(KERN_ERR "fs_lx: readb error,fun=%d,addr=%d,data=%d," + "err=%d\n", funcnum, (int)addr, *pdata, err); + + return err; +} +EXPORT_SYMBOL(fs_sdio_readb); + +int fs_sdio_writeb(struct sdio_dev *fdev, int funcnum, unsigned long addr, + unsigned char data) +{ + int err; + + sdio_claim_host(fdev->func); + if (funcnum == 0) + err = fsl_io_rw_direct(fdev->func->card, 1, 0, addr, + data, NULL); + else + sdio_writeb(fdev->func, data, (unsigned int)addr, &err); + sdio_release_host(fdev->func); + + if (err) + printk(KERN_ERR "fs_lx: writeb error,fun=%d,addr=%d,data=%d," + "err=%d\n", funcnum, (int)addr, data, err); + return err; +} +EXPORT_SYMBOL(fs_sdio_writeb); + +int fs_sdio_block_rw(struct sdio_dev *fdev, int funcnum, unsigned long addr, + unsigned char *pdata, unsigned int count, int direction) +{ + int err; + + sdio_claim_host(fdev->func); + if (direction == CMD_READ) + err = sdio_memcpy_fromio(fdev->func, pdata, addr, count); + else + err = sdio_memcpy_toio(fdev->func, addr, pdata, count); + sdio_release_host(fdev->func); + + return err; +} +EXPORT_SYMBOL(fs_sdio_block_rw); + +int fs_sdio_enable_interrupt(struct sdio_dev *fdev, int enable) +{ + struct mmc_host *host = fdev->func->card->host; + unsigned flags; + + spin_lock_irqsave(&fdev->lock, flags); + if (enable) { + if (!fdev->int_enabled) { + fdev->int_enabled = 1; + host->ops->enable_sdio_irq(host, 1); + } + } else { + if (fdev->int_enabled) { + host->ops->enable_sdio_irq(host, 0); + fdev->int_enabled = 0; + } + } + spin_unlock_irqrestore(&fdev->lock, flags); + + return 0; +} +EXPORT_SYMBOL(fs_sdio_enable_interrupt); + +int fs_sdio_enable(struct sdio_dev *fdev) +{ + int err = 0; + + sdio_claim_host(fdev->func); + err = sdio_disable_func(fdev->func); + err = sdio_enable_func(fdev->func); + sdio_release_host(fdev->func); + if (err) + printk(KERN_ERR "fs_lx:fs_sdio_enable error,err=%d\n", err); + return err; +} +EXPORT_SYMBOL(fs_sdio_enable); + +int fs_sdio_set_max_clock_speed(struct sdio_dev *fdev, int max_khz) +{ + struct mmc_card *card = fdev->func->card; + + /* Respect the host controller's min-max. */ + max_khz *= 1000; + if (max_khz < card->host->f_min) + max_khz = card->host->f_min; + if (max_khz > card->host->f_max) + max_khz = card->host->f_max; + + card->host->ios.clock = max_khz; + card->host->ops->set_ios(card->host, &card->host->ios); + + return max_khz / 1000; +} +EXPORT_SYMBOL(fs_sdio_set_max_clock_speed); + +int fs_sdio_set_block_size(struct sdio_dev *fdev, int blksz) +{ + return 0; +} +EXPORT_SYMBOL(fs_sdio_set_block_size); + +/* + * --------------------------------------------------------------------------- + * + * Turn on the power of WIFI card + * + * --------------------------------------------------------------------------- + */ +static void fs_unifi_power_on(int check_card) +{ + struct regulator_unifi *reg_unifi; + unsigned int tmp; + + reg_unifi = plat_data->priv; + + if (reg_unifi->reg_gpo1) + regulator_enable(reg_unifi->reg_gpo1); + if (reg_unifi->reg_gpo2) + regulator_enable(reg_unifi->reg_gpo2); + + if (plat_data->enable) + plat_data->enable(1); + + if (reg_unifi->reg_1v5_ana_bb) { + tmp = regulator_get_voltage(reg_unifi->reg_1v5_ana_bb); + if (tmp < 1500000) + regulator_set_voltage(reg_unifi->reg_1v5_ana_bb, + 1500000); + regulator_enable(reg_unifi->reg_1v5_ana_bb); + } + if (reg_unifi->reg_vdd_vpa) { + tmp = regulator_get_voltage(reg_unifi->reg_vdd_vpa); + if (tmp < 3000000) + regulator_set_voltage(reg_unifi->reg_vdd_vpa, 3000000); + regulator_enable(reg_unifi->reg_vdd_vpa); + } + /* WL_1V5DD should come on last, 10ms after other supplies */ + msleep(10); + if (reg_unifi->reg_1v5_dd) { + tmp = regulator_get_voltage(reg_unifi->reg_1v5_dd); + if (tmp < 1500000) + regulator_set_voltage(reg_unifi->reg_1v5_dd, 1500000); + regulator_enable(reg_unifi->reg_1v5_dd); + } + msleep(10); + if (check_card) { + do_sdio_hard_reset(NULL); + msleep(500); + mxc_mmc_force_detect(plat_data->host_id); + } +} + +/* + * --------------------------------------------------------------------------- + * + * Turn off the power of WIFI card + * + * --------------------------------------------------------------------------- + */ +static void fs_unifi_power_off(int check_card) +{ + struct regulator_unifi *reg_unifi; + + reg_unifi = plat_data->priv; + if (reg_unifi->reg_1v5_dd) + regulator_disable(reg_unifi->reg_1v5_dd); + if (reg_unifi->reg_vdd_vpa) + regulator_disable(reg_unifi->reg_vdd_vpa); + + if (reg_unifi->reg_1v5_ana_bb) + regulator_disable(reg_unifi->reg_1v5_ana_bb); + + if (plat_data->enable) + plat_data->enable(0); + + if (reg_unifi->reg_gpo2) + regulator_disable(reg_unifi->reg_gpo2); + + if (reg_unifi->reg_gpo1) + regulator_disable(reg_unifi->reg_gpo1); + + if (check_card) + mxc_mmc_force_detect(plat_data->host_id); + +} + +/* This should be made conditional on being slot 2 too - so we can + * use a plug in card in slot 1 + */ +int fs_sdio_hard_reset(struct sdio_dev *fdev) +{ + return 0; +} +EXPORT_SYMBOL(fs_sdio_hard_reset); + +static int do_sdio_hard_reset(struct sdio_dev *fdev) +{ + plat_data->hardreset(); + return 0; +} + +static const struct sdio_device_id fs_sdio_ids[] = { + {SDIO_DEVICE(0x032a, 0x0001)}, + { /* end: all zeroes */ }, +}; + +static struct sdio_driver sdio_unifi_driver = { + .name = "fs_unifi", + .probe = fs_sdio_probe, + .remove = fs_sdio_remove, + .id_table = fs_sdio_ids, + .drv = { + .suspend = fs_sdio_suspend, + .resume = fs_sdio_resume, + } +}; + +int fs_sdio_register_driver(struct fs_driver *driver) +{ + int ret; + + /* Switch us on, sdio device may exist if power is on by default. */ + fs_unifi_power_on(available_sdio_dev ? 0 : 1); + + /* Store the context to the device driver to the global */ + available_driver = driver; + + /* + * If available_sdio_dev is not NULL, probe has been called, + * so pass the probe to the registered driver + */ + if (available_sdio_dev) { + /* Store the context to the new device driver */ + available_sdio_dev->driver = driver; + + printk(KERN_INFO "fs_sdio_register_driver: Glue exists, add " + "device driver and register IRQ\n"); + driver->probe(available_sdio_dev); + + /* Register the IRQ handler to the SDIO IRQ. */ + sdio_claim_host(available_sdio_dev->func); + ret = sdio_claim_irq(available_sdio_dev->func, fs_sdio_irq); + sdio_release_host(available_sdio_dev->func); + if (ret) + return ret; + } + + return 0; +} +EXPORT_SYMBOL(fs_sdio_register_driver); + +void fs_sdio_unregister_driver(struct fs_driver *driver) +{ + /* + * If available_sdio_dev is not NULL, probe has been called, + * so pass the remove to the registered driver to clean up. + */ + if (available_sdio_dev) { + struct mmc_host *host = available_sdio_dev->func->card->host; + + printk(KERN_INFO "fs_sdio_unregister_driver: Glue exists, " + "unregister IRQ and remove device driver\n"); + + /* Unregister the IRQ handler first. */ + sdio_claim_host(available_sdio_dev->func); + sdio_release_irq(available_sdio_dev->func); + sdio_release_host(available_sdio_dev->func); + + driver->remove(available_sdio_dev); + + if (!available_sdio_dev->int_enabled) { + available_sdio_dev->int_enabled = 1; + host->ops->enable_sdio_irq(host, 1); + } + + /* Invalidate the context to the device driver */ + available_sdio_dev->driver = NULL; + } + + /* invalidate the context to the device driver to the global */ + available_driver = NULL; + /* Power down the UniFi */ + fs_unifi_power_off(-1); + /* Wait for card removed */ + msleep(100); +} +EXPORT_SYMBOL(fs_sdio_unregister_driver); + +static void fs_sdio_irq(struct sdio_func *func) +{ + struct sdio_dev *fdev = (struct sdio_dev *)sdio_get_drvdata(func); + if (fdev->driver) { + if (fdev->driver->card_int_handler) + fdev->driver->card_int_handler(fdev); + } +} + +#ifdef CONFIG_PM +static int fs_sdio_suspend(struct device *dev, pm_message_t state) +{ + struct sdio_dev *fdev = available_sdio_dev; + + /* Pass event to the registered driver. */ + if (fdev->driver) + if (fdev->driver->suspend) + fdev->driver->suspend(fdev, state); + + return 0; +} + +static int fs_sdio_resume(struct device *dev) +{ + struct sdio_dev *fdev = available_sdio_dev; + + /* Pass event to the registered driver. */ + if (fdev->driver) + if (fdev->driver->resume) + fdev->driver->resume(fdev); + + return 0; +} +#else +#define fs_sdio_suspend NULL +#define fs_sdio_resume NULL +#endif + +static int fs_sdio_probe(struct sdio_func *func, + const struct sdio_device_id *id) +{ + struct sdio_dev *fdev; + int ret = 0; + + /* Allocate our private context */ + fdev = kmalloc(sizeof(struct sdio_dev), GFP_KERNEL); + if (!fdev) + return -ENOMEM; + available_sdio_dev = fdev; + memset(fdev, 0, sizeof(struct sdio_dev)); + fdev->func = func; + fdev->vendor_id = id->vendor; + fdev->device_id = id->device; + fdev->max_blocksize = func->max_blksize; + fdev->int_enabled = 1; + spin_lock_init(&fdev->lock); + + /* Store our context in the MMC driver */ + printk(KERN_INFO "fs_sdio_probe: Add glue driver\n"); + sdio_set_drvdata(func, fdev); + + /* TODO: If a device driver is registered, call it's probe here */ + if (available_driver) { + /* Store the context to the device driver */ + fdev->driver = available_driver; + + printk(KERN_INFO "fs_sdio_probe: Add device driver and " + "register IRQ\n"); + available_driver->probe(fdev); + + /* Register the IRQ handler to the SDIO IRQ. */ + sdio_claim_host(fdev->func); + ret = sdio_claim_irq(func, fs_sdio_irq); + sdio_release_host(fdev->func); + if (ret) + return ret; + } + + return 0; +} + +static void fs_sdio_remove(struct sdio_func *func) +{ + struct sdio_dev *fdev = (struct sdio_dev *)sdio_get_drvdata(func); + struct mmc_host *host = func->card->host; + + /* If there is a registered device driver, pass on the remove */ + if (fdev->driver) { + printk(KERN_INFO "fs_sdio_remove: Free IRQ and remove device " + "driver\n"); + /* Unregister the IRQ handler first. */ + sdio_claim_host(fdev->func); + sdio_release_irq(func); + sdio_release_host(fdev->func); + + fdev->driver->remove(fdev); + + if (!fdev->int_enabled) { + fdev->int_enabled = 1; + host->ops->enable_sdio_irq(host, 1); + } + } + + /* Unregister the card context from the MMC driver. */ + sdio_set_drvdata(func, NULL); + + /* Invalidate the global to our context. */ + available_sdio_dev = NULL; + kfree(fdev); +} + +static int fs_unifi_init(void) +{ + struct regulator_unifi *reg_unifi; + struct regulator *reg; + int err = 0; + + plat_data = get_unifi_plat_data(); + + if (!plat_data) + return -ENOENT; + + reg_unifi = kzalloc(sizeof(struct regulator_unifi), GFP_KERNEL); + if (!reg_unifi) + return -ENOMEM; + + if (plat_data->reg_gpo1) { + reg = regulator_get(NULL, plat_data->reg_gpo1); + if (!IS_ERR(reg)) + reg_unifi->reg_gpo1 = reg; + else { + err = -EINVAL; + goto err_reg_gpo1; + } + } + + if (plat_data->reg_gpo2) { + reg = regulator_get(NULL, plat_data->reg_gpo2); + if (!IS_ERR(reg)) + reg_unifi->reg_gpo2 = reg; + else { + err = -EINVAL; + goto err_reg_gpo2; + } + } + + if (plat_data->reg_1v5_ana_bb) { + reg = regulator_get(NULL, plat_data->reg_1v5_ana_bb); + if (!IS_ERR(reg)) + reg_unifi->reg_1v5_ana_bb = reg; + else { + err = -EINVAL; + goto err_reg_1v5_ana_bb; + } + } + + if (plat_data->reg_vdd_vpa) { + reg = regulator_get(NULL, plat_data->reg_vdd_vpa); + if (!IS_ERR(reg)) + reg_unifi->reg_vdd_vpa = reg; + else { + err = -EINVAL; + goto err_reg_vdd_vpa; + } + } + + if (plat_data->reg_1v5_dd) { + reg = regulator_get(NULL, plat_data->reg_1v5_dd); + if (!IS_ERR(reg)) + reg_unifi->reg_1v5_dd = reg; + else { + err = -EINVAL; + goto err_reg_1v5_dd; + } + } + plat_data->priv = reg_unifi; + return 0; + +err_reg_1v5_dd: + if (reg_unifi->reg_vdd_vpa) + regulator_put(reg_unifi->reg_vdd_vpa, NULL); +err_reg_vdd_vpa: + if (reg_unifi->reg_1v5_ana_bb) + regulator_put(reg_unifi->reg_1v5_ana_bb, NULL); +err_reg_1v5_ana_bb: + if (reg_unifi->reg_gpo2) + regulator_put(reg_unifi->reg_gpo2, NULL); +err_reg_gpo2: + if (reg_unifi->reg_gpo1) + regulator_put(reg_unifi->reg_gpo1, NULL); +err_reg_gpo1: + kfree(reg_unifi); + return err; +} + +int fs_unifi_remove(void) +{ + struct regulator_unifi *reg_unifi; + + reg_unifi = plat_data->priv; + plat_data->priv = NULL; + + if (reg_unifi->reg_1v5_dd) + regulator_put(reg_unifi->reg_1v5_dd, NULL); + if (reg_unifi->reg_vdd_vpa) + regulator_put(reg_unifi->reg_vdd_vpa, NULL); + + if (reg_unifi->reg_1v5_ana_bb) + regulator_put(reg_unifi->reg_1v5_ana_bb, NULL); + + if (reg_unifi->reg_gpo2) + regulator_put(reg_unifi->reg_gpo2, NULL); + + if (reg_unifi->reg_gpo1) + regulator_put(reg_unifi->reg_gpo1, NULL); + + kfree(reg_unifi); + return 0; +} + +/* Module init and exit, register and unregister to the SDIO/MMC driver */ +static int __init fs_sdio_init(void) +{ + int err; + + printk(KERN_INFO "Freescale: Register to MMC/SDIO driver\n"); + /* Sleep a bit - otherwise if the mmc subsystem has just started, it + * will allow us to register, then immediatly remove us! + */ + msleep(10); + err = fs_unifi_init(); + if (err) { + printk(KERN_ERR "Error: fs_unifi_init failed!\n"); + return err; + } + err = sdio_register_driver(&sdio_unifi_driver); + if (err) { + printk(KERN_ERR "Error: register sdio_unifi_driver failed!\n"); + fs_unifi_remove(); + } + return err; +} + +module_init(fs_sdio_init); + +static void __exit fs_sdio_exit(void) +{ + printk(KERN_INFO "Freescale: Unregister from MMC/SDIO driver\n"); + sdio_unregister_driver(&sdio_unifi_driver); + fs_unifi_remove(); +} + +module_exit(fs_sdio_exit); + +MODULE_DESCRIPTION("Freescale SDIO glue driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mmc/card/unifi_fs/fs_sdio_api.h linux-2.6.26-lab126/drivers/mmc/card/unifi_fs/fs_sdio_api.h --- linux-2.6.26/drivers/mmc/card/unifi_fs/fs_sdio_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mmc/card/unifi_fs/fs_sdio_api.h 2010-08-10 04:15:59.000000000 -0400 @@ -0,0 +1,68 @@ +/* + *fs_sdio_api.h - Freescale SDIO glue module API for UniFi. + * + * Copyright (C) 2008 Cambridge Silicon Radio Ltd. + * + */ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef _FS_SDIO_API_H +#define _FS_SDIO_API_H + +struct sdio_dev; + +struct fs_driver { + const char *name; + int (*probe)(struct sdio_dev *fdev); + void (*remove)(struct sdio_dev *fdev); + void (*card_int_handler)(struct sdio_dev *fdev); + void (*suspend)(struct sdio_dev *fdev, pm_message_t state); + void (*resume)(struct sdio_dev *fdev); +}; + +int fs_sdio_readb(struct sdio_dev *fdev, int funcnum, + unsigned long addr, unsigned char *pdata); +int fs_sdio_writeb(struct sdio_dev *fdev, int funcnum, + unsigned long addr, unsigned char data); +int fs_sdio_block_rw(struct sdio_dev *fdev, int funcnum, + unsigned long addr, unsigned char *pdata, + unsigned int count, int direction); + +int fs_sdio_register_driver(struct fs_driver *driver); +void fs_sdio_unregister_driver(struct fs_driver *driver); +int fs_sdio_set_block_size(struct sdio_dev *fdev, int blksz); +int fs_sdio_set_max_clock_speed(struct sdio_dev *fdev, int max_khz); +int fs_sdio_enable_interrupt(struct sdio_dev *fdev, int enable); +int fs_sdio_enable(struct sdio_dev *fdev); +int fs_sdio_hard_reset(struct sdio_dev *fdev); + +struct sdio_dev { + /**< Device driver for this module. */ + struct fs_driver *driver; + + struct sdio_func *func; + + /**< Data private to the device driver. */ + void *drv_data; + + int int_enabled; + spinlock_t lock; + + uint16_t vendor_id; /**< Vendor ID of the card. */ + uint16_t device_id; /**< Device ID of the card. */ + + /**< Maximum block size supported. */ + int max_blocksize; +}; + + +#endif /* #ifndef _FS_SDIO_API_H */ diff -urN linux-2.6.26/drivers/mmc/core/Makefile linux-2.6.26-lab126/drivers/mmc/core/Makefile --- linux-2.6.26/drivers/mmc/core/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/core/Makefile 2010-08-10 04:15:59.000000000 -0400 @@ -12,3 +12,4 @@ sdio.o sdio_ops.o sdio_bus.o \ sdio_cis.o sdio_io.o sdio_irq.o +mmc_core-$(CONFIG_DEBUG_FS) += mmc_debug.o diff -urN linux-2.6.26/drivers/mmc/core/bus.c linux-2.6.26-lab126/drivers/mmc/core/bus.c --- linux-2.6.26/drivers/mmc/core/bus.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/core/bus.c 2010-08-10 04:15:59.000000000 -0400 @@ -252,6 +252,10 @@ if (ret) return ret; +#ifdef CONFIG_DEBUG_FS + mmc_add_card_debugfs(card); +#endif + mmc_card_set_present(card); return 0; @@ -263,6 +267,10 @@ */ void mmc_remove_card(struct mmc_card *card) { +#ifdef CONFIG_DEBUG_FS + mmc_remove_card_debugfs(card); +#endif + if (mmc_card_present(card)) { if (mmc_host_is_spi(card->host)) { printk(KERN_INFO "%s: SPI card removed\n", diff -urN linux-2.6.26/drivers/mmc/core/core.c linux-2.6.26-lab126/drivers/mmc/core/core.c --- linux-2.6.26/drivers/mmc/core/core.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/core/core.c 2010-08-10 04:15:59.000000000 -0400 @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -279,7 +280,8 @@ (card->host->ios.clock / 1000); if (data->flags & MMC_DATA_WRITE) - limit_us = 250000; + /* Increase to 300ms for crappy cards */ + limit_us = 300000; else limit_us = 100000; @@ -416,6 +418,80 @@ mmc_set_ios(host); } +/** + * mmc_vdd_to_ocrbitnum - Convert a voltage to the OCR bit number + * @vdd: voltage (mV) + * @low_bits: prefer low bits in boundary cases + * + * This function returns the OCR bit number according to the provided @vdd + * value. If conversion is not possible a negative errno value returned. + * + * Depending on the @low_bits flag the function prefers low or high OCR bits + * on boundary voltages. For example, + * with @low_bits = true, 3300 mV translates to ilog2(MMC_VDD_32_33); + * with @low_bits = false, 3300 mV translates to ilog2(MMC_VDD_33_34); + * + * Any value in the [1951:1999] range translates to the ilog2(MMC_VDD_20_21). + */ +static int mmc_vdd_to_ocrbitnum(int vdd, bool low_bits) +{ + const int max_bit = ilog2(MMC_VDD_35_36); + int bit; + + if (vdd < 1650 || vdd > 3600) + return -EINVAL; + + if (vdd >= 1650 && vdd <= 1950) + return ilog2(MMC_VDD_165_195); + + if (low_bits) + vdd -= 1; + + /* Base 2000 mV, step 100 mV, bit's base 8. */ + bit = (vdd - 2000) / 100 + 8; + if (bit > max_bit) + return max_bit; + return bit; +} + +/** + * mmc_vdd_to_ocrmask - Convert a voltage range to the OCR mask + * @vdd_min: minimum voltage value (mV) + * @vdd_max: maximum voltage value (mV) + * + * This function returns the OCR mask bits according to the provided @vdd_min + * and @vdd_max values. If conversion is not possible the function returns 0. + * + * Notes wrt boundary cases: + * This function sets the OCR bits for all boundary voltages, for example + * [3300:3400] range is translated to MMC_VDD_32_33 | MMC_VDD_33_34 | + * MMC_VDD_34_35 mask. + */ +u32 mmc_vdd_to_ocrmask(int vdd_min, int vdd_max) +{ + u32 mask = 0; + + if (vdd_max < vdd_min) + return 0; + + /* Prefer high bits for the boundary vdd_max values. */ + vdd_max = mmc_vdd_to_ocrbitnum(vdd_max, false); + if (vdd_max < 0) + return 0; + + /* Prefer low bits for the boundary vdd_min values. */ + vdd_min = mmc_vdd_to_ocrbitnum(vdd_min, true); + if (vdd_min < 0) + return 0; + + /* Fill the mask, from max bit to min bit. */ + while (vdd_max >= vdd_min) + mask |= 1 << vdd_max--; + + return mask; +} +EXPORT_SYMBOL(mmc_vdd_to_ocrmask); + /* * Mask off any voltages we don't support and select * the lowest voltage @@ -638,9 +714,13 @@ */ mmc_bus_put(host); + if (host->ops->get_cd && host->ops->get_cd(host) == 0) + goto out; + mmc_claim_host(host); mmc_power_up(host); + sdio_reset(host); mmc_go_idle(host); mmc_send_if_cond(host, host->ocr_avail); @@ -652,7 +732,7 @@ if (!err) { if (mmc_attach_sdio(host, ocr)) mmc_power_off(host); - return; + goto out; } /* @@ -662,7 +742,7 @@ if (!err) { if (mmc_attach_sd(host, ocr)) mmc_power_off(host); - return; + goto out; } /* @@ -672,7 +752,7 @@ if (!err) { if (mmc_attach_mmc(host, ocr)) mmc_power_off(host); - return; + goto out; } mmc_release_host(host); @@ -683,6 +763,10 @@ mmc_bus_put(host); } + +out: + if (host->caps & MMC_CAP_NEEDS_POLL) + mmc_schedule_delayed_work(&host->detect, HZ); } void mmc_start_host(struct mmc_host *host) @@ -700,8 +784,12 @@ spin_unlock_irqrestore(&host->lock, flags); #endif + cancel_delayed_work(&host->detect); mmc_flush_scheduled_work(); + /* clear pm flags now and let card drivers set them as needed */ + host->pm_flags = 0; + mmc_bus_get(host); if (host->bus_ops && !host->bus_dead) { if (host->bus_ops->remove) @@ -727,6 +815,7 @@ */ int mmc_suspend_host(struct mmc_host *host, pm_message_t state) { + cancel_delayed_work(&host->detect); mmc_flush_scheduled_work(); mmc_bus_get(host); @@ -740,11 +829,13 @@ mmc_claim_host(host); mmc_detach_bus(host); mmc_release_host(host); + host->pm_flags = 0; } } mmc_bus_put(host); - mmc_power_off(host); + if (!(host->pm_flags & MMC_PM_KEEP_POWER)) + mmc_power_off(host); return 0; } @@ -759,7 +850,8 @@ { mmc_bus_get(host); if (host->bus_ops && !host->bus_dead) { - mmc_power_up(host); + if (!(host->pm_flags & MMC_PM_KEEP_POWER)) + mmc_power_up(host); BUG_ON(!host->bus_ops->resume); host->bus_ops->resume(host); } diff -urN linux-2.6.26/drivers/mmc/core/core.h linux-2.6.26-lab126/drivers/mmc/core/core.h --- linux-2.6.26/drivers/mmc/core/core.h 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/core/core.h 2010-08-10 04:15:59.000000000 -0400 @@ -52,5 +52,12 @@ extern int use_spi_crc; +/* Debugfs information for hosts and cards */ +void mmc_add_host_debugfs(struct mmc_host *host); +void mmc_remove_host_debugfs(struct mmc_host *host); + +void mmc_add_card_debugfs(struct mmc_card *card); +void mmc_remove_card_debugfs(struct mmc_card *card); + #endif diff -urN linux-2.6.26/drivers/mmc/core/host.c linux-2.6.26-lab126/drivers/mmc/core/host.c --- linux-2.6.26/drivers/mmc/core/host.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/core/host.c 2010-08-10 04:15:59.000000000 -0400 @@ -127,6 +127,10 @@ if (err) return err; +#ifdef CONFIG_DEBUG_FS + mmc_add_host_debugfs(host); +#endif + mmc_start_host(host); return 0; @@ -145,6 +149,9 @@ void mmc_remove_host(struct mmc_host *host) { mmc_stop_host(host); +#ifdef CONFIG_DEBUG_FS + mmc_remove_host_debugfs(host); +#endif device_del(&host->class_dev); diff -urN linux-2.6.26/drivers/mmc/core/mmc.c linux-2.6.26-lab126/drivers/mmc/core/mmc.c --- linux-2.6.26/drivers/mmc/core/mmc.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/core/mmc.c 2010-08-10 04:15:59.000000000 -0400 @@ -15,11 +15,17 @@ #include #include #include +#include #include "core.h" #include "bus.h" #include "mmc_ops.h" +#ifdef CONFIG_MACH_LUIGI_LAB126 +unsigned long manufacturer_id; +unsigned int card_capacity; +#endif + static const unsigned int tran_exp[] = { 10000, 100000, 1000000, 10000000, 0, 0, 0, 0 @@ -53,6 +59,15 @@ __res & __mask; \ }) +#ifdef CONFIG_MACH_LUIGI_LAB126 + +#define SAMSUNG_MANF_ID 0x15 /* Samsung manufacturer ID */ +#define SANDISK_MANF_ID 0x2 /* Sandisk manufacturer ID */ +#define TOSHIBA_MANF_ID 0x11 /* Toshiba manufacturer ID */ +#define HYNIX_MANF_ID 0x90 /* Hynix manufacturer ID */ + +#endif + /* * Given the decoded CSD structure, decode the raw CID to our CID structure. */ @@ -121,7 +136,7 @@ * v1.2 has extra information in bits 15, 11 and 10. */ csd_struct = UNSTUFF_BITS(resp, 126, 2); - if (csd_struct != 1 && csd_struct != 2) { + if (csd_struct != 1 && csd_struct != 2 && csd_struct != 3) { printk(KERN_ERR "%s: unrecognised CSD structure version %d\n", mmc_hostname(card->host), csd_struct); return -EINVAL; @@ -208,7 +223,7 @@ } ext_csd_struct = ext_csd[EXT_CSD_REV]; - if (ext_csd_struct > 2) { + if (ext_csd_struct > 5) { printk(KERN_ERR "%s: unrecognised EXT_CSD structure " "version %d\n", mmc_hostname(card->host), ext_csd_struct); @@ -222,8 +237,28 @@ ext_csd[EXT_CSD_SEC_CNT + 1] << 8 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; - if (card->ext_csd.sectors) - mmc_card_set_blockaddr(card); + /* + * EXT_CSD versions 3 or less should all support block addressing + * and not byte addressing + */ + if (card->ext_csd.sectors && (ext_csd_struct <= 5)) { + /* + * Toshiba 2GB cards support byte addressing mode only + */ + if (manufacturer_id == TOSHIBA_MANF_ID) { + if (card_capacity == 0xfff) { + printk(KERN_INFO "%s: Using block addressing\n", mmc_hostname(card->host)); + mmc_card_set_blockaddr(card); + } + else + printk(KERN_INFO "%s: Using byte addressing\n", mmc_hostname(card->host)); + } + else { + printk(KERN_INFO "%s: Using block addressing\n", mmc_hostname(card->host)); + mmc_card_set_blockaddr(card); + } + + } } switch (ext_csd[EXT_CSD_CARD_TYPE]) { @@ -354,6 +389,49 @@ card->type = MMC_TYPE_MMC; card->rca = 1; memcpy(card->raw_cid, cid, sizeof(card->raw_cid)); + +#ifdef CONFIG_MACH_LUIGI_LAB126 + /* + * Manufacturer ID: 127-120 + */ + manufacturer_id = UNSTUFF_BITS(card->raw_cid, 104, 24); + manufacturer_id = (manufacturer_id >> 16); + + switch (manufacturer_id) { + case SAMSUNG_MANF_ID: + if (IS_SHASTA() && (IS_DVT() || IS_PVT())) { + printk(KERN_INFO "%s: Using open-ended mode on Samsung eMMC\n", + mmc_hostname(host)); + host->predefined = 0; + } + else { + printk(KERN_INFO "%s: Using predefined mode on Samsung eMMC\n", + mmc_hostname(host)); + host->predefined = 1; + } + break; + case SANDISK_MANF_ID: + printk(KERN_INFO "%s: Using open-ended mode on Sandisk eMMC\n", + mmc_hostname(host)); + host->predefined = 0; + break; + case TOSHIBA_MANF_ID: + printk(KERN_INFO "%s: Using open-ended mode on Toshiba eMMC\n", + mmc_hostname(host)); + host->predefined = 0; + break; + case HYNIX_MANF_ID: + printk(KERN_INFO "%s: Using open-ended mode on Hynix eMMC\n", + mmc_hostname(host)); + host->predefined = 0; + break; + default: + printk(KERN_INFO "%s: Using open-ended mode on eMMC\n", + mmc_hostname(host)); + host->predefined = 0; + break; + } +#endif } /* @@ -383,6 +461,9 @@ goto free_card; } +#ifdef CONFIG_MACH_LUIGI_LAB126 + card_capacity = UNSTUFF_BITS(card->raw_csd, 62, 12); +#endif /* * Select card, as all following commands rely on that. */ @@ -408,12 +489,17 @@ (host->caps & MMC_CAP_MMC_HIGHSPEED)) { err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); - if (err) + if (err && err != -EBADMSG) goto free_card; - - mmc_card_set_highspeed(card); - - mmc_set_timing(card->host, MMC_TIMING_MMC_HS); + + if (err) { + printk(KERN_WARNING "%s: switch to highspeed failed\n", + mmc_hostname(card->host)); + err = 0; + } else { + mmc_card_set_highspeed(card); + mmc_set_timing(card->host, MMC_TIMING_MMC_HS); + } } /* @@ -434,13 +520,35 @@ * Activate wide bus (if supported). */ if ((card->csd.mmca_vsn >= CSD_SPEC_VER_4) && + (host->caps & MMC_CAP_8_BIT_DATA)) { + err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_8); + if (err && err != -EBADMSG) + goto free_card; + + if (err) { + printk(KERN_WARNING "%s: switch to bus width %d " + "failed\n", mmc_hostname(card->host), + 1 << MMC_BUS_WIDTH_8); + err = 0; + } else { + mmc_set_bus_width(card->host, MMC_BUS_WIDTH_8); + } + } else if ((card->csd.mmca_vsn >= CSD_SPEC_VER_4) && (host->caps & MMC_CAP_4_BIT_DATA)) { err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_4); - if (err) + if (err && err != -EBADMSG) goto free_card; - mmc_set_bus_width(card->host, MMC_BUS_WIDTH_4); + if (err) { + printk(KERN_WARNING "%s: switch to bus width %d " + "failed\n", mmc_hostname(card->host), + 1 << MMC_BUS_WIDTH_4); + err = 0; + } else { + mmc_set_bus_width(card->host, MMC_BUS_WIDTH_4); + } } if (!oldcard) @@ -496,8 +604,6 @@ } } -#ifdef CONFIG_MMC_UNSAFE_RESUME - /* * Suspend callback from host. */ @@ -540,20 +646,49 @@ } -#else +#ifdef CONFIG_MMC_UNSAFE_RESUME -#define mmc_suspend NULL -#define mmc_resume NULL +static const struct mmc_bus_ops mmc_ops = { + .remove = mmc_remove, + .detect = mmc_detect, + .suspend = mmc_suspend, + .resume = mmc_resume, +}; -#endif +static void mmc_attach_bus_ops(struct mmc_host *host) +{ + mmc_attach_bus(host, &mmc_ops); +} + +#else static const struct mmc_bus_ops mmc_ops = { .remove = mmc_remove, .detect = mmc_detect, + .suspend = NULL, + .resume = NULL, +}; + +static const struct mmc_bus_ops mmc_ops_unsafe = { + .remove = mmc_remove, + .detect = mmc_detect, .suspend = mmc_suspend, .resume = mmc_resume, }; +static void mmc_attach_bus_ops(struct mmc_host *host) +{ + const struct mmc_bus_ops *bus_ops; + + if (host->caps & MMC_CAP_NON_REMOVABLE) + bus_ops = &mmc_ops_unsafe; + else + bus_ops = &mmc_ops; + mmc_attach_bus(host, bus_ops); +} + +#endif + /* * Starting point for MMC card init. */ @@ -564,7 +699,7 @@ BUG_ON(!host); WARN_ON(!host->claimed); - mmc_attach_bus(host, &mmc_ops); + mmc_attach_bus_ops(host); /* * We need to get OCR a different way for SPI. diff -urN linux-2.6.26/drivers/mmc/core/mmc_debug.c linux-2.6.26-lab126/drivers/mmc/core/mmc_debug.c --- linux-2.6.26/drivers/mmc/core/mmc_debug.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mmc/core/mmc_debug.c 2010-08-10 04:15:59.000000000 -0400 @@ -0,0 +1,303 @@ +/* + * Debugfs support for hosts and cards + * + * Copyright (C) 2009 Amazon Inc., All rights reserved. + * Manish Lachwani (lachwani@lab126.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include + +#include "mmc_ops.h" +#include "core.h" + +/* The debugfs functions are optimized away when CONFIG_DEBUG_FS isn't set. */ +static int mmc_ios_show(struct seq_file *s, void *data) +{ + static const char *vdd_str[] = { + [8] = "2.0", + [9] = "2.1", + [10] = "2.2", + [11] = "2.3", + [12] = "2.4", + [13] = "2.5", + [14] = "2.6", + [15] = "2.7", + [16] = "2.8", + [17] = "2.9", + [18] = "3.0", + [19] = "3.1", + [20] = "3.2", + [21] = "3.3", + [22] = "3.4", + [23] = "3.5", + [24] = "3.6", + }; + struct mmc_host *host = s->private; + struct mmc_ios *ios = &host->ios; + const char *str; + + seq_printf(s, "clock:\t\t%u Hz\n", ios->clock); + seq_printf(s, "vdd:\t\t%u ", ios->vdd); + if ((1 << ios->vdd) & MMC_VDD_165_195) + seq_printf(s, "(1.65 - 1.95 V)\n"); + else if (ios->vdd < (ARRAY_SIZE(vdd_str) - 1) + && vdd_str[ios->vdd] && vdd_str[ios->vdd + 1]) + seq_printf(s, "(%s ~ %s V)\n", vdd_str[ios->vdd], + vdd_str[ios->vdd + 1]); + else + seq_printf(s, "(invalid)\n"); + + switch (ios->bus_mode) { + case MMC_BUSMODE_OPENDRAIN: + str = "open drain"; + break; + case MMC_BUSMODE_PUSHPULL: + str = "push-pull"; + break; + default: + str = "invalid"; + break; + } + seq_printf(s, "bus mode:\t%u (%s)\n", ios->bus_mode, str); + + switch (ios->chip_select) { + case MMC_CS_DONTCARE: + str = "don't care"; + break; + case MMC_CS_HIGH: + str = "active high"; + break; + case MMC_CS_LOW: + str = "active low"; + break; + default: + str = "invalid"; + break; + } + seq_printf(s, "chip select:\t%u (%s)\n", ios->chip_select, str); + + switch (ios->power_mode) { + case MMC_POWER_OFF: + str = "off"; + break; + case MMC_POWER_UP: + str = "up"; + break; + case MMC_POWER_ON: + str = "on"; + break; + default: + str = "invalid"; + break; + } + seq_printf(s, "power mode:\t%u (%s)\n", ios->power_mode, str); + seq_printf(s, "bus width:\t%u (%u bits)\n", + ios->bus_width, 1 << ios->bus_width); + + switch (ios->timing) { + case MMC_TIMING_LEGACY: + str = "legacy"; + break; + case MMC_TIMING_MMC_HS: + str = "mmc high-speed"; + break; + case MMC_TIMING_SD_HS: + str = "sd high-speed"; + break; + default: + str = "invalid"; + break; + } + seq_printf(s, "timing spec:\t%u (%s)\n", ios->timing, str); + +#ifdef CONFIG_MACH_LUIGI_LAB126 + seq_printf(s, "Predefined mode:\t%d\n", host->predefined); +#endif + seq_printf(s, "max_blk_size:\t%d\n", host->max_blk_size); + seq_printf(s, "max_seg_size:\t%d\n", host->max_seg_size); + seq_printf(s, "max_req_size:\t%d\n", host->max_req_size); + seq_printf(s, "max_phys_segs:\t%d\n", host->max_phys_segs); + seq_printf(s, "max_blk_count:\t%d\n", host->max_blk_count); + + return 0; +} + +static int mmc_ios_open(struct inode *inode, struct file *file) +{ + return single_open(file, mmc_ios_show, inode->i_private); +} + +static const struct file_operations mmc_ios_fops = { + .open = mmc_ios_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +void mmc_add_host_debugfs(struct mmc_host *host) +{ + struct dentry *root; + + root = debugfs_create_dir(mmc_hostname(host), NULL); + if (IS_ERR(root)) + /* Don't complain -- debugfs just isn't enabled */ + return; + if (!root) + /* Complain -- debugfs is enabled, but it failed to + * create the directory. */ + goto err_root; + + host->debugfs_root = root; + + if (!debugfs_create_file("ios", S_IRUSR, root, host, &mmc_ios_fops)) + goto err_ios; + + return; + +err_ios: + debugfs_remove_recursive(root); + host->debugfs_root = NULL; +err_root: + dev_err(&host->class_dev, "failed to initialize debugfs\n"); +} + +void mmc_remove_host_debugfs(struct mmc_host *host) +{ + debugfs_remove_recursive(host->debugfs_root); +} + + +static int mmc_dbg_card_status_get(void *data, u64 *val) +{ + struct mmc_card *card = data; + u32 status; + int ret; + + mmc_claim_host(card->host); + + ret = mmc_send_status(data, &status); + if (!ret) + *val = status; + + mmc_release_host(card->host); + + return ret; +} +DEFINE_SIMPLE_ATTRIBUTE(mmc_dbg_card_status_fops, mmc_dbg_card_status_get, + NULL, "%08llx\n"); + +#define EXT_CSD_STR_LEN 1025 + +static int mmc_ext_csd_open(struct inode *inode, struct file *filp) +{ + struct mmc_card *card = inode->i_private; + char *buf; + ssize_t n = 0; + u8 *ext_csd; + int err, i; + + buf = kmalloc(EXT_CSD_STR_LEN + 1, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + ext_csd = kmalloc(512, GFP_KERNEL); + if (!ext_csd) { + err = -ENOMEM; + goto out_free; + } + + mmc_claim_host(card->host); + err = mmc_send_ext_csd(card, ext_csd); + mmc_release_host(card->host); + if (err) + goto out_free; + + for (i = 511; i >= 0; i--) + n += sprintf(buf + n, "%02x", ext_csd[i]); + n += sprintf(buf + n, "\n"); + BUG_ON(n != EXT_CSD_STR_LEN); + + filp->private_data = buf; + kfree(ext_csd); + return 0; + +out_free: + kfree(buf); + kfree(ext_csd); + return err; +} + +static ssize_t mmc_ext_csd_read(struct file *filp, char __user *ubuf, + size_t cnt, loff_t *ppos) +{ + char *buf = filp->private_data; + + return simple_read_from_buffer(ubuf, cnt, ppos, + buf, EXT_CSD_STR_LEN); +} + +static int mmc_ext_csd_release(struct inode *inode, struct file *file) +{ + kfree(file->private_data); + return 0; +} + +static struct file_operations mmc_dbg_ext_csd_fops = { + .open = mmc_ext_csd_open, + .read = mmc_ext_csd_read, + .release = mmc_ext_csd_release, +}; + +void mmc_add_card_debugfs(struct mmc_card *card) +{ + struct mmc_host *host = card->host; + struct dentry *root; + + if (!host->debugfs_root) + return; + + root = debugfs_create_dir(mmc_card_id(card), host->debugfs_root); + if (IS_ERR(root)) + /* Don't complain -- debugfs just isn't enabled */ + return; + if (!root) + /* Complain -- debugfs is enabled, but it failed to + * create the directory. */ + goto err; + + card->debugfs_root = root; + + if (!debugfs_create_x32("state", S_IRUSR, root, &card->state)) + goto err; + + if (mmc_card_mmc(card) || mmc_card_sd(card)) + if (!debugfs_create_file("status", S_IRUSR, root, card, + &mmc_dbg_card_status_fops)) + goto err; + + if (mmc_card_mmc(card)) + if (!debugfs_create_file("ext_csd", S_IRUSR, root, card, + &mmc_dbg_ext_csd_fops)) + goto err; + + return; + +err: + debugfs_remove_recursive(root); + card->debugfs_root = NULL; + dev_err(&card->dev, "failed to initialize debugfs\n"); +} + +void mmc_remove_card_debugfs(struct mmc_card *card) +{ + debugfs_remove_recursive(card->debugfs_root); +} + diff -urN linux-2.6.26/drivers/mmc/core/mmc_ops.c linux-2.6.26-lab126/drivers/mmc/core/mmc_ops.c --- linux-2.6.26/drivers/mmc/core/mmc_ops.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/core/mmc_ops.c 2010-08-10 04:15:59.000000000 -0400 @@ -347,6 +347,7 @@ { int err; struct mmc_command cmd; + u32 status; BUG_ON(!card); BUG_ON(!card->host); @@ -364,6 +365,28 @@ if (err) return err; + /* Must check status to be sure of no errors */ + do { + err = mmc_send_status(card, &status); + if (err) + return err; + if (card->host->caps & MMC_CAP_WAIT_WHILE_BUSY) + break; + if (mmc_host_is_spi(card->host)) + break; + } while (R1_CURRENT_STATE(status) == 7); + + if (mmc_host_is_spi(card->host)) { + if (status & R1_SPI_ILLEGAL_COMMAND) + return -EBADMSG; + } else { + if (status & 0xFDFFA000) + printk(KERN_WARNING "%s: unexpected status %#x after " + "switch", mmc_hostname(card->host), status); + if (status & R1_SWITCH_ERROR) + return -EBADMSG; + } + return 0; } diff -urN linux-2.6.26/drivers/mmc/core/sd.c linux-2.6.26-lab126/drivers/mmc/core/sd.c --- linux-2.6.26/drivers/mmc/core/sd.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/core/sd.c 2010-08-10 04:15:59.000000000 -0400 @@ -558,8 +558,6 @@ } } -#ifdef CONFIG_MMC_UNSAFE_RESUME - /* * Suspend callback from host. */ @@ -602,20 +600,49 @@ } -#else +#ifdef CONFIG_MMC_UNSAFE_RESUME -#define mmc_sd_suspend NULL -#define mmc_sd_resume NULL +static const struct mmc_bus_ops mmc_sd_ops = { + .remove = mmc_sd_remove, + .detect = mmc_sd_detect, + .suspend = mmc_sd_suspend, + .resume = mmc_sd_resume, +}; -#endif +static void mmc_sd_attach_bus_ops(struct mmc_host *host) +{ + mmc_attach_bus(host, &mmc_sd_ops); +} + +#else static const struct mmc_bus_ops mmc_sd_ops = { .remove = mmc_sd_remove, .detect = mmc_sd_detect, + .suspend = NULL, + .resume = NULL, +}; + +static const struct mmc_bus_ops mmc_sd_ops_unsafe = { + .remove = mmc_sd_remove, + .detect = mmc_sd_detect, .suspend = mmc_sd_suspend, .resume = mmc_sd_resume, }; +static void mmc_sd_attach_bus_ops(struct mmc_host *host) +{ + const struct mmc_bus_ops *bus_ops; + + if (host->caps & MMC_CAP_NON_REMOVABLE) + bus_ops = &mmc_sd_ops_unsafe; + else + bus_ops = &mmc_sd_ops; + mmc_attach_bus(host, bus_ops); +} + +#endif + /* * Starting point for SD card init. */ @@ -626,7 +653,7 @@ BUG_ON(!host); WARN_ON(!host->claimed); - mmc_attach_bus(host, &mmc_sd_ops); + mmc_sd_attach_bus_ops(host); /* * We need to get OCR a different way for SPI. diff -urN linux-2.6.26/drivers/mmc/core/sdio.c linux-2.6.26-lab126/drivers/mmc/core/sdio.c --- linux-2.6.26/drivers/mmc/core/sdio.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/core/sdio.c 2010-08-10 04:15:59.000000000 -0400 @@ -164,6 +164,256 @@ return 0; } + /* + * Disconnect the pull-up resistor on CD/DAT[3] (pin 1) + * of the card. This may be required on certain setups of boards, + * controllers and embedded sdio device which do not need the card's + * pull-up. As a result, card detection is disabled and power is saved. + */ +static int sdio_disable_card_detection(struct mmc_card *card) +{ + int ret; + u8 ctrl; + + if (!card->cccr.disable_cd) + return 0; + + ret = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_IF, 0, &ctrl); + if (ret) + return ret; + + ctrl |= SDIO_BUS_CD_DISABLE; + + return mmc_io_rw_direct(card, 1, 0, SDIO_CCCR_IF, ctrl, NULL); +} + +/* + * Devices that remain active during a system suspend are + * put back into 1-bit mode. + */ +int sdio_disable_wide(struct mmc_card *card) +{ + int ret; + u8 ctrl; + + if (!(card->host->caps & MMC_CAP_4_BIT_DATA)) + return 0; + + if (card->cccr.low_speed && !card->cccr.wide_bus) + return 0; + + ret = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_IF, 0, &ctrl); + if (ret) + return ret; + + if (!(ctrl & SDIO_BUS_WIDTH_4BIT)) + return 0; + + ctrl &= ~SDIO_BUS_WIDTH_4BIT; + ctrl |= SDIO_BUS_ASYNC_INT; + + ret = mmc_io_rw_direct(card, 1, 0, SDIO_CCCR_IF, ctrl, NULL); + if (ret) + return ret; + + mmc_set_bus_width(card->host, MMC_BUS_WIDTH_1); + + return 0; +} +EXPORT_SYMBOL(sdio_disable_wide); + + /* + * Test if the card supports high-speed mode and, if so, switch to it. + */ +static int sdio_enable_hs(struct mmc_card *card) +{ + int ret; + u8 speed; + + if (!(card->host->caps & MMC_CAP_SDIO_HIGHSPEED)) + return 0; + + if (!card->cccr.high_speed) + return 0; + + ret = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_SPEED, 0, &speed); + if (ret) + return ret; + + speed |= SDIO_SPEED_EHS; + + ret = mmc_io_rw_direct(card, 1, 0, SDIO_CCCR_SPEED, speed, NULL); + if (ret) + return ret; + + mmc_card_set_highspeed(card); + mmc_set_timing(card->host, MMC_TIMING_SD_HS); + + return 0; +} + +int mmc_attach_reinit_sdio(struct mmc_host *host, u32 ocr); +static void mmc_sdio_remove(struct mmc_host *host); + +/* re-init the card on a resume */ +int mmc_sdio_reinit_card(struct mmc_host *host, u32 ocr) +{ + int err; + + BUG_ON(!host); + WARN_ON(!host->claimed); + + mmc_sdio_remove(host); + + sdio_reset(host); + + /* + * Inform the card of the voltage + */ + err = mmc_send_io_op_cond(host, host->ocr, &ocr); + if (!err) { + err = mmc_attach_reinit_sdio(host, ocr); + if (err) + goto err; + } + else + goto err; + + return 0; +err: + mmc_remove_card(host->card); + return err; +} +EXPORT_SYMBOL(mmc_sdio_reinit_card); + + +/* Handle the detection and initialisation of a card. + * + * In the case of a resume, "oldcard" will contain the card + * we're trying to reinitialise. + */ +static int mmc_sdio_init_card(struct mmc_host *host, u32 ocr, + struct mmc_card *oldcard) +{ + struct mmc_card *card; + int err; + + BUG_ON(!host); + WARN_ON(!host->claimed); + + /* + * Inform the card of the voltage + */ + err = mmc_send_io_op_cond(host, host->ocr, &ocr); + if (err) + goto err; + + /* + * For SPI, enable CRC as appropriate. + */ + if (mmc_host_is_spi(host)) { + err = mmc_spi_set_crc(host, use_spi_crc); + if (err) + goto err; + } + + /* + * Allocate card structure. + */ + card = mmc_alloc_card(host, NULL); + if (IS_ERR(card)) { + err = PTR_ERR(card); + goto err; + } + + card->type = MMC_TYPE_SDIO; + + /* + * For native busses: set card RCA and quit open drain mode. + */ + if (!mmc_host_is_spi(host)) { + err = mmc_send_relative_addr(host, &card->rca); + if (err) + goto remove; + + mmc_set_bus_mode(host, MMC_BUSMODE_PUSHPULL); + } + + /* + * Select card, as all following commands rely on that. + */ + if (!mmc_host_is_spi(host)) { + err = mmc_select_card(card); + if (err) + goto remove; + } + + /* + * Read the common registers. + */ + err = sdio_read_cccr(card); + if (err) + goto remove; + + /* + * Read the common CIS tuples. + */ + err = sdio_read_common_cis(card); + if (err) + goto remove; + + if (oldcard) { + int same = (card->cis.vendor == oldcard->cis.vendor && + card->cis.device == oldcard->cis.device); + mmc_remove_card(card); + if (!same) { + err = -ENOENT; + goto err; + } + card = oldcard; + } + + /* + * Switch to high-speed (if supported). + */ + err = sdio_enable_hs(card); + if (err) + goto remove; + + /* + * Change to the card's maximum speed. + */ + if (mmc_card_highspeed(card)) { + /* + * The SDIO specification doesn't mention how + * the CIS transfer speed register relates to + * high-speed, but it seems that 50 MHz is + * mandatory. + */ + mmc_set_clock(host, 50000000); + } else { + mmc_set_clock(host, card->cis.max_dtr); + } + + /* + * Switch to wider bus (if supported). + */ + err = sdio_enable_wide(card); + if (err) + goto remove; + + if (!oldcard) + host->card = card; + return 0; + +remove: + if (!oldcard) + mmc_remove_card(card); + +err: + return err; +} + /* * Host is being removed. Free up the current card. */ @@ -213,17 +463,82 @@ } } +/* + * SDIO suspend. We need to suspend all functions separately. + * Therefore all registered functions must have drivers with suspend + * and resume methods. Failing that we simply remove the whole card. + */ +static void mmc_sdio_suspend(struct mmc_host *host) +{ + int i; + + /* make sure all registered functions can suspend/resume */ + for (i = 0; i < host->card->sdio_funcs; i++) { + struct sdio_func *func = host->card->sdio_func[i]; + if (func && sdio_func_present(func) && func->dev.driver) { + if (func->dev.driver->suspend || func->dev.driver->resume) { + /* just remove the entire card in that case */ + mmc_sdio_remove(host); + mmc_claim_host(host); + mmc_detach_bus(host); + mmc_release_host(host); + return; + } + } + } + + /* now suspend them */ + for (i = 0; i < host->card->sdio_funcs; i++) { + struct sdio_func *func = host->card->sdio_func[i]; + if (func && sdio_func_present(func) && func->dev.driver) { + func->dev.driver->suspend(&func->dev, PMSG_SUSPEND); + mmc_claim_host(host); + sdio_disable_wide(host->card); + mmc_release_host(host); + } + } +} + +static void mmc_sdio_resume(struct mmc_host *host) +{ + int i, err; + + BUG_ON(!host); + BUG_ON(!host->card); + + mmc_claim_host(host); + err = mmc_sdio_init_card(host, host->ocr, host->card); + if (!err) + err = sdio_enable_wide(host->card); + if (!err && host->sdio_irqs) + mmc_signal_sdio_irq(host); + mmc_release_host(host); + if (err) { + mmc_sdio_remove(host); + mmc_claim_host(host); + mmc_detach_bus(host); + mmc_release_host(host); + return; + } + + /* resume all functions */ + for (i = 0; i < host->card->sdio_funcs; i++) { + struct sdio_func *func = host->card->sdio_func[i]; + if (func && sdio_func_present(func) && func->dev.driver) { + func->dev.driver->resume(&func->dev); + } + } +} static const struct mmc_bus_ops mmc_sdio_ops = { .remove = mmc_sdio_remove, .detect = mmc_sdio_detect, + .suspend = mmc_sdio_suspend, + .resume = mmc_sdio_resume, }; -/* - * Starting point for SDIO card init. - */ -int mmc_attach_sdio(struct mmc_host *host, u32 ocr) +int mmc_attach_reinit_sdio(struct mmc_host *host, u32 ocr) { int err; int i, funcs; @@ -232,8 +547,6 @@ BUG_ON(!host); WARN_ON(!host->claimed); - mmc_attach_bus(host, &mmc_sdio_ops); - /* * Sanity check the voltages that the card claims to * support. @@ -265,83 +578,142 @@ /* * Inform the card of the voltage */ - err = mmc_send_io_op_cond(host, host->ocr, &ocr); + err = mmc_sdio_init_card(host, host->ocr, NULL); if (err) goto err; - /* - * For SPI, enable CRC as appropriate. - */ - if (mmc_host_is_spi(host)) { - err = mmc_spi_set_crc(host, use_spi_crc); - if (err) - goto err; - } + card = host->card; /* * The number of functions on the card is encoded inside * the ocr. */ - funcs = (ocr & 0x70000000) >> 28; + card->sdio_funcs = funcs = (ocr & 0x70000000) >> 28; - /* - * Allocate card structure. - */ - card = mmc_alloc_card(host, NULL); - if (IS_ERR(card)) { - err = PTR_ERR(card); - goto err; - } + /* disconnect card detection pull-up resistor. */ + err = sdio_disable_card_detection(card); + if (err) + goto remove; - card->type = MMC_TYPE_SDIO; - card->sdio_funcs = funcs; + mmc_release_host(host); - host->card = card; + for (i = 0;i < host->card->sdio_funcs;i++) { + if (host->card->sdio_func[i]) { + sdio_remove_func(host->card->sdio_func[i]); + host->card->sdio_func[i] = NULL; + } + } + + mmc_claim_host(host); /* - * For native busses: set card RCA and quit open drain mode. + * Initialize (but don't add) all present functions. */ - if (!mmc_host_is_spi(host)) { - err = mmc_send_relative_addr(host, &card->rca); + for (i = 0;i < funcs;i++) { + err = sdio_init_func(host->card, i + 1); if (err) goto remove; - - mmc_set_bus_mode(host, MMC_BUSMODE_PUSHPULL); } + mmc_release_host(host); + /* - * Select card, as all following commands rely on that. + * First add the card to the driver model... + */ + err = mmc_add_card(host->card); + if (err) + goto remove_added; + + /* + * ...then the SDIO functions. */ - if (!mmc_host_is_spi(host)) { - err = mmc_select_card(card); + for (i = 0;i < funcs;i++) { + err = sdio_add_func(host->card->sdio_func[i]); if (err) - goto remove; + goto remove_added; } + mmc_claim_host(host); + + return 0; + +remove_added: + /* Remove without lock if the device has been added. */ + mmc_sdio_remove(host); + mmc_claim_host(host); +remove: + /* And with lock if it hasn't been added. */ + if (host->card) + mmc_sdio_remove(host); +err: + mmc_detach_bus(host); + mmc_release_host(host); + + printk(KERN_ERR "%s: error %d whilst initialising SDIO card\n", + mmc_hostname(host), err); + + return err; +} +/* + * Starting point for SDIO card init. + */ +int mmc_attach_sdio(struct mmc_host *host, u32 ocr) +{ + int err; + int i, funcs; + struct mmc_card *card; + + BUG_ON(!host); + WARN_ON(!host->claimed); + + if (!host->bus_ops) + mmc_attach_bus(host, &mmc_sdio_ops); + /* - * Read the common registers. + * Sanity check the voltages that the card claims to + * support. */ - err = sdio_read_cccr(card); - if (err) - goto remove; + if (ocr & 0x7F) { + printk(KERN_WARNING "%s: card claims to support voltages " + "below the defined range. These will be ignored.\n", + mmc_hostname(host)); + ocr &= ~0x7F; + } + + if (ocr & MMC_VDD_165_195) { + printk(KERN_WARNING "%s: SDIO card claims to support the " + "incompletely defined 'low voltage range'. This " + "will be ignored.\n", mmc_hostname(host)); + ocr &= ~MMC_VDD_165_195; + } + + host->ocr = mmc_select_voltage(host, ocr); /* - * Read the common CIS tuples. + * Can we support the voltage(s) of the card(s)? */ - err = sdio_read_common_cis(card); - if (err) - goto remove; + if (!host->ocr) { + err = -EINVAL; + goto err; + } /* - * No support for high-speed yet, so just set - * the card's maximum speed. + * Inform the card of the voltage */ - mmc_set_clock(host, card->cis.max_dtr); + err = mmc_sdio_init_card(host, host->ocr, NULL); + if (err) + goto err; + + card = host->card; /* - * Switch to wider bus (if supported). + * The number of functions on the card is encoded inside + * the ocr. */ - err = sdio_enable_wide(card); + card->sdio_funcs = funcs = (ocr & 0x70000000) >> 28; + + /* disconnect card detection pull-up resistor. */ + err = sdio_disable_card_detection(card); if (err) goto remove; diff -urN linux-2.6.26/drivers/mmc/core/sdio_cis.c linux-2.6.26-lab126/drivers/mmc/core/sdio_cis.c --- linux-2.6.26/drivers/mmc/core/sdio_cis.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/core/sdio_cis.c 2010-08-10 04:15:59.000000000 -0400 @@ -246,7 +246,7 @@ this->size = tpl_link; *prev = this; prev = &this->next; - printk(KERN_DEBUG + printk(KERN_INFO "%s: queuing CIS tuple 0x%02x length %u\n", mmc_hostname(card->host), tpl_code, tpl_link); } else { diff -urN linux-2.6.26/drivers/mmc/core/sdio_io.c linux-2.6.26-lab126/drivers/mmc/core/sdio_io.c --- linux-2.6.26/drivers/mmc/core/sdio_io.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/core/sdio_io.c 2010-08-10 04:15:59.000000000 -0400 @@ -546,3 +546,52 @@ *err_ret = ret; } EXPORT_SYMBOL_GPL(sdio_f0_writeb); + + +/** + * sdio_get_host_pm_caps - get host power management capabilities + * @func: SDIO function attached to host + * + * Returns a capability bitmask corresponding to power management + * features supported by the host controller that the card function + * might rely upon during a system suspend. The host doesn't need + * to be claimed, nor the function active, for this information to be + * obtained. + */ +mmc_pm_flag_t sdio_get_host_pm_caps(struct sdio_func *func) +{ + BUG_ON(!func); + BUG_ON(!func->card); + + return func->card->host->pm_caps; +} +EXPORT_SYMBOL_GPL(sdio_get_host_pm_caps); + +/** + * sdio_set_host_pm_flags - set wanted host power management capabilities + * @func: SDIO function attached to host + * + * Set a capability bitmask corresponding to wanted host controller + * power management features for the upcoming suspend state. + * This must be called, if needed, each time the suspend method of + * the function driver is called, and must contain only bits that + * were returned by sdio_get_host_pm_caps(). + * The host doesn't need to be claimed, nor the function active, + * for this information to be set. + */ +int sdio_set_host_pm_flags(struct sdio_func *func, mmc_pm_flag_t flags) +{ + struct mmc_host *host; + + BUG_ON(!func); + BUG_ON(!func->card); + + host = func->card->host; + + if (flags & ~host->pm_caps) + return -EINVAL; + + /* function suspend methods are serialized, hence no lock needed */ + host->pm_flags |= flags; + return 0; +} diff -urN linux-2.6.26/drivers/mmc/core/sdio_irq.c linux-2.6.26-lab126/drivers/mmc/core/sdio_irq.c --- linux-2.6.26/drivers/mmc/core/sdio_irq.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/core/sdio_irq.c 2010-09-02 21:21:01.000000000 -0400 @@ -32,7 +32,7 @@ ret = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_INTx, 0, &pending); if (ret) { - printk(KERN_DEBUG "%s: error %d reading SDIO_CCCR_INTx\n", + printk(KERN_ERR "%s: error %d reading SDIO_CCCR_INTx\n", mmc_card_id(card), ret); return ret; } @@ -78,9 +78,7 @@ * asynchronous notification of pending SDIO card interrupts * hence we poll for them in that case. */ - idle_period = msecs_to_jiffies(10); - period = (host->caps & MMC_CAP_SDIO_IRQ) ? - MAX_SCHEDULE_TIMEOUT : idle_period; + period = idle_period = MAX_SCHEDULE_TIMEOUT; pr_debug("%s: IRQ thread started (poll period = %lu jiffies)\n", mmc_hostname(host), period); @@ -107,25 +105,26 @@ /* * Give other threads a chance to run in the presence of - * errors. FIXME: determine if due to card removal and - * possibly exit this thread if so. + * errors. */ - if (ret < 0) - ssleep(1); + if (ret < 0) { + set_current_state(TASK_INTERRUPTIBLE); + if (!kthread_should_stop()) + schedule_timeout(HZ); + set_current_state(TASK_RUNNING); + } /* * Adaptive polling frequency based on the assumption * that an interrupt will be closely followed by more. * This has a substantial benefit for network devices. */ - if (!(host->caps & MMC_CAP_SDIO_IRQ)) { - if (ret > 0) - period /= 2; - else { - period++; - if (period > idle_period) - period = idle_period; - } + if (ret > 0) + period /= 2; + else { + period++; + if (period > idle_period) + period = idle_period; } set_current_state(TASK_INTERRUPTIBLE); @@ -205,6 +204,11 @@ return -EBUSY; } + func->irq_handler = handler; + ret = sdio_card_irq_get(func->card); + if (ret) + func->irq_handler = NULL; + ret = mmc_io_rw_direct(func->card, 0, 0, SDIO_CCCR_IENx, 0, ®); if (ret) return ret; @@ -217,11 +221,6 @@ if (ret) return ret; - func->irq_handler = handler; - ret = sdio_card_irq_get(func->card); - if (ret) - func->irq_handler = NULL; - return ret; } EXPORT_SYMBOL_GPL(sdio_claim_irq); @@ -242,11 +241,6 @@ pr_debug("SDIO: Disabling IRQ for %s...\n", sdio_func_id(func)); - if (func->irq_handler) { - func->irq_handler = NULL; - sdio_card_irq_put(func->card); - } - ret = mmc_io_rw_direct(func->card, 0, 0, SDIO_CCCR_IENx, 0, ®); if (ret) return ret; @@ -261,6 +255,10 @@ if (ret) return ret; + if (func->irq_handler) { + func->irq_handler = NULL; + sdio_card_irq_put(func->card); + } return 0; } EXPORT_SYMBOL_GPL(sdio_release_irq); diff -urN linux-2.6.26/drivers/mmc/core/sdio_ops.c linux-2.6.26-lab126/drivers/mmc/core/sdio_ops.c --- linux-2.6.26/drivers/mmc/core/sdio_ops.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/core/sdio_ops.c 2010-08-10 04:15:59.000000000 -0400 @@ -67,13 +67,13 @@ return err; } -int mmc_io_rw_direct(struct mmc_card *card, int write, unsigned fn, - unsigned addr, u8 in, u8* out) +static int mmc_io_rw_direct_host(struct mmc_host *host, int write, unsigned fn, + unsigned addr, u8 in, u8 *out) { struct mmc_command cmd; int err; - BUG_ON(!card); + BUG_ON(!host); BUG_ON(fn > 7); memset(&cmd, 0, sizeof(struct mmc_command)); @@ -86,11 +86,11 @@ cmd.arg |= in; cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; - err = mmc_wait_for_cmd(card->host, &cmd, 0); + err = mmc_wait_for_cmd(host, &cmd, 0); if (err) return err; - if (mmc_host_is_spi(card->host)) { + if (mmc_host_is_spi(host)) { /* host driver already reported errors */ } else { if (cmd.resp[0] & R5_ERROR) @@ -102,7 +102,7 @@ } if (out) { - if (mmc_host_is_spi(card->host)) + if (mmc_host_is_spi(host)) *out = (cmd.resp[0] >> 8) & 0xFF; else *out = cmd.resp[0] & 0xFF; @@ -111,6 +111,13 @@ return 0; } +int mmc_io_rw_direct(struct mmc_card *card, int write, unsigned fn, + unsigned addr, u8 in, u8 *out) +{ + BUG_ON(!card); + return mmc_io_rw_direct_host(card->host, write, fn, addr, in, out); +} + int mmc_io_rw_extended(struct mmc_card *card, int write, unsigned fn, unsigned addr, int incr_addr, u8 *buf, unsigned blocks, unsigned blksz) { @@ -174,3 +181,20 @@ return 0; } +int sdio_reset(struct mmc_host *host) +{ + int ret; + u8 abort; + + /* SDIO Simplified Specification V2.0, 4.4 Reset for SDIO */ + + ret = mmc_io_rw_direct_host(host, 0, 0, SDIO_CCCR_ABORT, 0, &abort); + if (ret) + abort = 0x08; + else + abort |= 0x08; + + ret = mmc_io_rw_direct_host(host, 1, 0, SDIO_CCCR_ABORT, abort, NULL); + return ret; +} + diff -urN linux-2.6.26/drivers/mmc/core/sdio_ops.h linux-2.6.26-lab126/drivers/mmc/core/sdio_ops.h --- linux-2.6.26/drivers/mmc/core/sdio_ops.h 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/core/sdio_ops.h 2010-08-10 04:15:59.000000000 -0400 @@ -17,6 +17,7 @@ unsigned addr, u8 in, u8* out); int mmc_io_rw_extended(struct mmc_card *card, int write, unsigned fn, unsigned addr, int incr_addr, u8 *buf, unsigned blocks, unsigned blksz); +int sdio_reset(struct mmc_host *host); #endif diff -urN linux-2.6.26/drivers/mmc/host/Kconfig linux-2.6.26-lab126/drivers/mmc/host/Kconfig --- linux-2.6.26/drivers/mmc/host/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/host/Kconfig 2010-08-10 04:16:00.000000000 -0400 @@ -130,3 +130,41 @@ If unsure, or if your system has no SPI master driver, say N. + If unsure, say N. + +config MMC_MXC + tristate "Freescale MXC Multimedia Card Interface support" + depends on ARCH_MXC && MMC + help + This selects the Freescale MXC Multimedia card Interface. + If you have a MXC platform with a Multimedia Card slot, + say Y or M here. + +config MMC_IMX_ESDHCI + tristate "Freescale i.MX Secure Digital Host Controller Interface support" + depends on ARCH_MXC && MMC + help + This selects the Freescale i.MX Multimedia card Interface. + If you have a i.MX platform with a Multimedia Card slot, + say Y or M here. + + If unsure, say N. + +config MMC_IMX_ESDHCI_SELECT2 + bool "Enable second ESDHCI port" + depends on MMC_IMX_ESDHCI && ARCH_MX25 + default n + help + Enable the second ESDHC port + +config MMC_IMX_ESDHCI_PIO_MODE + bool "Freescale i.MX Secure Digital Host Controller Interface PIO mode" + depends on MMC_IMX_ESDHC != n + default n + help + This set the Freescale i.MX Multimedia card Interface to PIO mode. + If you have a i.MX platform with a Multimedia Card slot, + and want test it with PIO mode. + say Y here. + + If unsure, say N. diff -urN linux-2.6.26/drivers/mmc/host/Makefile linux-2.6.26-lab126/drivers/mmc/host/Makefile --- linux-2.6.26/drivers/mmc/host/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mmc/host/Makefile 2010-08-10 04:16:00.000000000 -0400 @@ -10,6 +10,7 @@ obj-$(CONFIG_MMC_PXA) += pxamci.o obj-$(CONFIG_MMC_IMX) += imxmmc.o obj-$(CONFIG_MMC_SDHCI) += sdhci.o +obj-$(CONFIG_MMC_IMX_ESDHCI) += mx_sdhci.o obj-$(CONFIG_MMC_RICOH_MMC) += ricoh_mmc.o obj-$(CONFIG_MMC_WBSD) += wbsd.o obj-$(CONFIG_MMC_AU1X) += au1xmmc.o @@ -17,4 +18,5 @@ obj-$(CONFIG_MMC_AT91) += at91_mci.o obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o obj-$(CONFIG_MMC_SPI) += mmc_spi.o +obj-$(CONFIG_MMC_MXC) += mxc_mmc.o diff -urN linux-2.6.26/drivers/mmc/host/mx_sdhci.c linux-2.6.26-lab126/drivers/mmc/host/mx_sdhci.c --- linux-2.6.26/drivers/mmc/host/mx_sdhci.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mmc/host/mx_sdhci.c 2010-09-02 21:21:01.000000000 -0400 @@ -0,0 +1,2581 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2009-2010 Amazon Technologies, Inc. All Rights Reserved. + * Author: Manish Lachwani (lachwani@lab126.com) + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mx_sdhci.c + * + * @brief Driver for the Freescale Semiconductor MXC eSDHC modules. + * + * This driver code is based on sdhci.c, by Pierre Ossman "); + * This driver supports Enhanced Secure Digital Host Controller + * modules eSDHC of MXC. eSDHC is also referred as enhanced MMC/SD + * controller. + * + * @ingroup MMC_SD + */ + +/* + * On the Luigi board, the following is the MMC/SD layout: + * + * MMC Slot #1 - eMMC + * MMC Slot #2 - Atheros WiFi Ar6002 + * MMC Slot #3 - SD card + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mx_sdhci.h" + +#define DRIVER_NAME "mxsdhci" + +#define DBG(f, x...) \ + pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x) + +static unsigned int debug_quirks; +static int last_op_dir; + +/* + * Different quirks to handle when the hardware deviates from a strict + * interpretation of the SDHCI specification. + */ + +/* Controller doesn't honor resets unless we touch the clock register */ +#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) +/* Controller has bad caps bits, but really supports DMA */ +#define SDHCI_QUIRK_FORCE_DMA (1<<1) +/* Controller doesn't like to be reset when there is no card inserted. */ +#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) +/* Controller doesn't like clearing the power reg before a change */ +#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) +/* Controller has flaky internal state so reset it on each ios change */ +#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) +/* Controller has an unusable DMA engine */ +#define SDHCI_QUIRK_BROKEN_DMA (1<<5) +/* Controller can only DMA from 32-bit aligned addresses */ +#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<6) +/* Controller can only DMA chunk sizes that are a multiple of 32 bits */ +#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<7) +/* Controller needs to be reset after each request to stay stable */ +#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<8) +/* Controller needs voltage and power writes to happen separately */ +#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<9) +/* Controller has an off-by-one issue with timeout value */ +#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<10) +/* Controller only support the PIO */ +#define SDHCI_QUIRK_ONLY_PIO (1<<16) +/* Controller support the External DMA */ +#define SDHCI_QUIRK_EXTERNAL_DMA_MODE (1<<17) +/* Controller support the Internal Simple DMA */ +#define SDHCI_QUIRK_INTERNAL_SIMPLE_DMA (1<<18) +/* Controller support the Internal Advanced DMA */ +#define SDHCI_QUIRK_INTERNAL_ADVANCED_DMA (1<<19) + +/* Check if SDIO clock is in use - 20 seconds*/ +#define SDIO_CLK_RESUME_THRESHOLD 20000 + +/* + * defines the mxc flags refer to the special hw pre-conditons and behavior + */ +static unsigned int mxc_quirks; +#ifdef CONFIG_MMC_IMX_ESDHCI_PIO_MODE +static unsigned int debug_quirks = SDHCI_QUIRK_ONLY_PIO; +#else +static unsigned int debug_quirks; +#endif +static unsigned int mxc_wml_value = 512; +static unsigned int *adma_des_table; + +static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *); +static void sdhci_finish_data(struct sdhci_host *); + +static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); +static void sdhci_finish_command(struct sdhci_host *); + +/* Used to active the SD bus */ +extern void gpio_sdhc_active(int module); +extern void gpio_sdhc_inactive(int module); +static void sdhci_dma_irq(void *devid, int error, unsigned int cnt); + +int sd_turn_of_dma = 0; +EXPORT_SYMBOL(sd_turn_of_dma); + +static int sd1_turn_of_dma = 0; +static int sd2_turn_of_dma = 0; + +/* Keep track of small transfers */ +static int sdhci_pio_counter = 0; + +static struct regulator *vsd_reg; + +struct sdhci_host *sdio_host; + +/* Always follow the driver's idle pm model */ +static int sdio_mmc1_clock = 1; +extern int sdio_reset(struct mmc_host *host); +extern int mmc_go_idle(struct mmc_host *host); +atomic_t sdio_removed = ATOMIC_INIT(0); +EXPORT_SYMBOL(sdio_removed); + +extern int mmc_sdio_reinit_card(struct mmc_host *host, u32 ocr); + +void sdhci_reset_sdio(void) +{ + mmc_claim_host(sdio_host->mmc); + mmc_go_idle(sdio_host->mmc); + mdelay(20); + mmc_sdio_reinit_card(sdio_host->mmc, sdio_host->mmc->ocr); + mmc_release_host(sdio_host->mmc); +} +EXPORT_SYMBOL(sdhci_reset_sdio); + +/* Gate the mmc1 clock and set the variables correctly */ +static void sdio_mmc1_clk_work(struct work_struct *work) +{ + /* WiFi module is now gone */ + sdio_mmc1_clock = 1; + clk_disable(sdio_host->clk); + sdio_host->plat_data->clk_flg = 0; +} + +static void sdio_mmc1_resume_work(struct work_struct *work) +{ + if (sdio_mmc1_clock) { + if (sdio_host->plat_data->clk_flg) { + clk_disable(sdio_host->clk); + sdio_host->plat_data->clk_flg = 0; + } + } +} + +static DECLARE_DELAYED_WORK(sdio_mmc1_clk_wq, sdio_mmc1_clk_work); +static DECLARE_DELAYED_WORK(sdio_mmc1_resume_wq, sdio_mmc1_resume_work); + +static int sdio_lpm_threshold_level = 1000; /* After 1s */ + +DEFINE_SPINLOCK(sdio_lpm_mutex); + +static void sdio_lpm_func(struct work_struct *unused); +DECLARE_DELAYED_WORK(sdio_lpm_work, sdio_lpm_func); + +void sdhci_touch_mmc1_clk(int enable) +{ + if (enable) { + sdio_mmc1_clock = 0; + if (!sdio_host->plat_data->clk_flg) { + clk_enable(sdio_host->clk); + sdio_host->plat_data->clk_flg = 1; + } + } + else { + /* Gate clock after 100 ms */ + schedule_delayed_work(&sdio_mmc1_clk_wq, msecs_to_jiffies(1000)); + } +} +EXPORT_SYMBOL(sdhci_touch_mmc1_clk); + +static int cardint_sdio_irq = 0; +static int cardint_stat = 0; + +static int sdio_lpm_counter = 0; + +static void sdhci_sdio_clk(int enable); + +static int sdio_lpm_enabled = 0; + +static void sdio_lpm_func(struct work_struct *unused) +{ + u32 ctrl = 0; + + if (sdio_lpm_enabled) + return; + + disable_irq(sdio_host->irq); + spin_lock(&sdio_lpm_mutex); + + ctrl = readl(sdio_host->ioaddr + SDHCI_HOST_CONTROL); + if (!(ctrl & SDHCI_CTRL_4BITBUS)) { + /* Card is already in 1-bit mode, time to gate clock and disable IRQ */ + sdio_lpm_counter++; + sdhci_sdio_clk(0); + sdio_lpm_enabled = 1; + } + + spin_unlock(&sdio_lpm_mutex); + enable_irq(sdio_host->irq); +} + +static void sdhci_dumpregs(struct sdhci_host *host) +{ + printk(KERN_ERR DRIVER_NAME + ": ============== REGISTER DUMP ==============\n"); + + printk(KERN_ERR DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", + readl(host->ioaddr + SDHCI_DMA_ADDRESS), + readl(host->ioaddr + SDHCI_HOST_VERSION)); + printk(KERN_ERR DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", + (readl(host->ioaddr + SDHCI_BLOCK_SIZE) & 0xFFFF), + (readl(host->ioaddr + SDHCI_BLOCK_COUNT) >> 16)); + printk(KERN_ERR DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", + readl(host->ioaddr + SDHCI_ARGUMENT), + readl(host->ioaddr + SDHCI_TRANSFER_MODE)); + printk(KERN_ERR DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", + readl(host->ioaddr + SDHCI_PRESENT_STATE), + readl(host->ioaddr + SDHCI_HOST_CONTROL)); + printk(KERN_ERR DRIVER_NAME ": Clock: 0x%08x\n", + readl(host->ioaddr + SDHCI_CLOCK_CONTROL)); + printk(KERN_ERR DRIVER_NAME ": Int stat: 0x%08x\n", + readl(host->ioaddr + SDHCI_INT_STATUS)); + printk(KERN_ERR DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", + readl(host->ioaddr + SDHCI_INT_ENABLE), + readl(host->ioaddr + SDHCI_SIGNAL_ENABLE)); + printk(KERN_ERR DRIVER_NAME ": Caps: 0x%08x\n", + readl(host->ioaddr + SDHCI_CAPABILITIES)); + printk(KERN_ERR DRIVER_NAME ": Present: 0x%08x\n", + readl(host->ioaddr + SDHCI_PRESENT_STATE)); + + printk(KERN_ERR DRIVER_NAME "cardint_sdio_irq=%d, cardint_stat=%d\n", + cardint_sdio_irq, cardint_stat); + + printk(KERN_ERR DRIVER_NAME "sd1_turn_of_dma=%d, sd2_turn_of_dma=%d\n", + sd1_turn_of_dma, sd2_turn_of_dma); + + printk(KERN_ERR DRIVER_NAME "SDIO LPM Counter=%d\n",sdio_lpm_counter); + + printk(KERN_ERR DRIVER_NAME + ": ===========================================\n"); +} + +static int sdio_debug_level = 0; + +static ssize_t sdhci_registers_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + sdhci_dumpregs(sdio_host); + return sprintf(buf, "0\n"); +} + +static DEVICE_ATTR(sdhci_registers, 0644, sdhci_registers_show, NULL); + +static ssize_t sdio_pio_transfers_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", sdhci_pio_counter); +} +static DEVICE_ATTR(sdio_pio_transfers, 0644, sdio_pio_transfers_show, NULL); + +static ssize_t sdio_lpm_idle_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", sdio_lpm_counter); +} +static DEVICE_ATTR(sdio_lpm_idle, 0644, sdio_lpm_idle_show, NULL); + +static ssize_t sdio_debug_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", sdio_debug_level); +} + +static ssize_t sdio_debug_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + int value = 0; + + if (sscanf(buf, "%d", &value) <= 0) { + printk(KERN_ERR "Error reading debug_level\n"); + return -EINVAL; + } + + if (value >= 0) { + sdio_debug_level = value; + } + + return size; +} + +static DEVICE_ATTR(sdio_debug, 0644, sdio_debug_show, sdio_debug_store); + +static ssize_t sdio_lpm_threshold_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", sdio_lpm_threshold_level); +} + +static ssize_t sdio_lpm_threshold_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + int value = 0; + + if (sscanf(buf, "%d", &value) <= 0) { + printk(KERN_ERR "Error reading lpm threshold level\n"); + return -EINVAL; + } + + if (value > 0) { + sdio_lpm_threshold_level = value; + } + + return size; +} +static DEVICE_ATTR(sdio_lpm_threshold, 0644, sdio_lpm_threshold_show, sdio_lpm_threshold_store); + +/*****************************************************************************\ + * * + * Low level functions * + * * +\*****************************************************************************/ + +static void sdhci_reset(struct sdhci_host *host, u8 mask) +{ + unsigned long tmp; + unsigned long mask_u32; + unsigned long reg_save = 0; + + if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { + if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & + SDHCI_CARD_PRESENT)) + return; + } + + if (mask & SDHCI_RESET_ALL) + host->clock = 0; + else if (host->flags & SDHCI_CD_PRESENT) + reg_save = readl(host->ioaddr + SDHCI_HOST_CONTROL); + + tmp = readl(host->ioaddr + SDHCI_CLOCK_CONTROL) | (mask << 24); + mask_u32 = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE); + writel(tmp, host->ioaddr + SDHCI_CLOCK_CONTROL); + + /* Wait max 100 ms */ + tmp = 5000; + + /* hw clears the bit when it's done */ + while ((readl(host->ioaddr + SDHCI_CLOCK_CONTROL) >> 24) & mask) { + if (tmp == 0) { + printk(KERN_ERR "%s: Reset 0x%x never completed.\n", + mmc_hostname(host->mmc), (int)mask); + sdhci_dumpregs(host); + return; + } + tmp--; + udelay(20); + } + /* + * The INT_EN SIG_EN regs have been modified after reset. + * re-configure them ag. + */ + if (!(mask & SDHCI_RESET_ALL) && (host->flags & SDHCI_CD_PRESENT)) + writel(reg_save, host->ioaddr + SDHCI_HOST_CONTROL); + if (host->flags & SDHCI_USE_DMA) + mask_u32 &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL); + if (mxc_wml_value == 512) + writel(SDHCI_WML_128_WORDS, host->ioaddr + SDHCI_WML); + else + writel(SDHCI_WML_16_WORDS, host->ioaddr + SDHCI_WML); + writel(mask_u32, host->ioaddr + SDHCI_INT_ENABLE); + writel(mask_u32, host->ioaddr + SDHCI_SIGNAL_ENABLE); + last_op_dir = 0; +} + +static void sdhci_init(struct sdhci_host *host) +{ + u32 intmask; + + sdhci_reset(host, SDHCI_RESET_ALL); + + intmask = SDHCI_INT_ADMA_ERROR | SDHCI_INT_ACMD12ERR | + SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC | + SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | + SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | + SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | + SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE; + + if (host->flags & SDHCI_USE_DMA) + intmask &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL); + /* Configure the WML rege */ + if (mxc_wml_value == 512) + writel(SDHCI_WML_128_WORDS, host->ioaddr + SDHCI_WML); + else + writel(SDHCI_WML_16_WORDS, host->ioaddr + SDHCI_WML); + writel(intmask, host->ioaddr + SDHCI_INT_ENABLE); + writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE); + mdelay(10); +} + +static void sdhci_activate_led(struct sdhci_host *host) +{ + u32 ctrl; + + ctrl = readl(host->ioaddr + SDHCI_HOST_CONTROL); + ctrl |= SDHCI_CTRL_LED; + writel(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); +} + +static void sdhci_deactivate_led(struct sdhci_host *host) +{ + u32 ctrl; + + ctrl = readl(host->ioaddr + SDHCI_HOST_CONTROL); + ctrl &= ~SDHCI_CTRL_LED; + writel(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); +} + +static void sdhci_sdio_clk(int enable) +{ + /* No WiFi? */ + if (sdio_mmc1_clock) + return; + + if (enable) { + /* Enable the clock */ + if (!sdio_host->plat_data->clk_flg) { + sdio_host->plat_data->clk_flg = 1; + clk_enable(sdio_host->clk); + } + } + else { + /* Gate the sdio clock */ + if (sdio_host->plat_data->clk_flg) { + clk_disable(sdio_host->clk); + sdio_host->plat_data->clk_flg = 0; + } + } +} + +/* + * Handle bus case where controller cannot detect CIRQ reliably when in 4-bit mode. + * Only valid for SDIO since MMC supports 8-bit width + */ +static void sdhci_idle_bus_adjust(struct sdhci_host *host, u8 idle) +{ + u32 ctrl; + + if (host->flags & SDHCI_IN_4BIT_MODE) { + /* while bus is idle, leave it in 1-bit mode at the controller level */ + sdhci_sdio_clk(1); + ctrl = readl(host->ioaddr + SDHCI_HOST_CONTROL); + ctrl &= ~SDHCI_CTRL_4BITBUS; + if (!idle) { + ctrl |= SDHCI_CTRL_4BITBUS; + sdio_lpm_enabled = 0; + } + writel(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); + if (idle) { + schedule_delayed_work(&sdio_lpm_work, + msecs_to_jiffies(sdio_lpm_threshold_level)); + } + } +} + +/*****************************************************************************\ + * * + * Core functions * + * * +\*****************************************************************************/ + +static inline char *sdhci_sg_to_buffer(struct sdhci_host *host) +{ + return sg_virt(host->cur_sg); +} + +static inline int sdhci_next_sg(struct sdhci_host *host) +{ + /* + * Skip to next SG entry. + */ + host->cur_sg++; + host->num_sg--; + + /* + * Any entries left? + */ + if (host->num_sg > 0) { + host->offset = 0; + host->remain = host->cur_sg->length; + } + + return host->num_sg; +} + +static void sdhci_read_block_pio(struct sdhci_host *host) +{ + int blksize, chunk_remain; + u32 data; + char *buffer; + int size; + + DBG("PIO reading\n"); + + blksize = host->data->blksz; + chunk_remain = 0; + data = 0; + + buffer = sdhci_sg_to_buffer(host) + host->offset; + + while (blksize) { + if (chunk_remain == 0) { + data = readl(host->ioaddr + SDHCI_BUFFER); + chunk_remain = min(blksize, 4); + } + + size = min(host->remain, chunk_remain); + + chunk_remain -= size; + blksize -= size; + host->offset += size; + host->remain -= size; + + while (size) { + *buffer = data & 0xFF; + buffer++; + data >>= 8; + size--; + } + + if (host->remain == 0) { + if (sdhci_next_sg(host) == 0) { + BUG_ON(blksize != 0); + return; + } + buffer = sdhci_sg_to_buffer(host); + } + } +} + +static void sdhci_write_block_pio(struct sdhci_host *host) +{ + int blksize, chunk_remain; + u32 data; + char *buffer; + int bytes, size; + + DBG("PIO writing\n"); + + blksize = host->data->blksz; + chunk_remain = 4; + data = 0; + + bytes = 0; + buffer = sdhci_sg_to_buffer(host) + host->offset; + + while (blksize) { + size = min(host->remain, chunk_remain); + + chunk_remain -= size; + blksize -= size; + host->offset += size; + host->remain -= size; + + while (size) { + data >>= 8; + data |= (u32) *buffer << 24; + buffer++; + size--; + } + + if (chunk_remain == 0) { + writel(data, host->ioaddr + SDHCI_BUFFER); + chunk_remain = min(blksize, 4); + } + + if (host->remain == 0) { + if (sdhci_next_sg(host) == 0) { + BUG_ON(blksize != 0); + return; + } + buffer = sdhci_sg_to_buffer(host); + } + } +} + +static void sdhci_transfer_pio(struct sdhci_host *host) +{ + u32 mask; + + BUG_ON(!host->data); + + if (host->num_sg == 0) + return; + + if (host->data->flags & MMC_DATA_READ) + mask = SDHCI_DATA_AVAILABLE; + else + mask = SDHCI_SPACE_AVAILABLE; + + while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) { + if (host->data->flags & MMC_DATA_READ) + sdhci_read_block_pio(host); + else + sdhci_write_block_pio(host); + + if (host->num_sg == 0) + break; + } + + DBG("PIO transfer complete.\n"); +} + +static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) +{ + u32 count; + unsigned target_timeout, current_timeout; + + WARN_ON(host->data); + + if (data == NULL) + return; + + /* Sanity checks */ + BUG_ON(data->blksz * data->blocks > 524288); + BUG_ON(data->blksz > host->mmc->max_blk_size); + BUG_ON(data->blocks > 65535); + + host->data = data; + host->data_early = 0; + + if (host->data->flags & MMC_DATA_READ) + writel(readl(host->ioaddr + SDHCI_CLOCK_CONTROL) | + SDHCI_CLOCK_HLK_EN, + host->ioaddr + SDHCI_CLOCK_CONTROL); + + /* timeout in us */ + target_timeout = data->timeout_ns / 1000 + + data->timeout_clks / host->clock; + + /* + * Figure out needed cycles. + * We do this in steps in order to fit inside a 32 bit int. + * The first step is the minimum timeout, which will have a + * minimum resolution of 6 bits: + * (1) 2^13*1000 > 2^22, + * (2) host->timeout_clk < 2^16 + * => + * (1) / (2) > 2^6 + */ + count = 0; + current_timeout = (1 << 13) * 1000 / host->timeout_clk; + while (current_timeout < target_timeout) { + count++; + current_timeout <<= 1; + if (count >= 0xF) + break; + } + + /* + * Compensate for an off-by-one error in the CaFe hardware; otherwise, + * a too-small count gives us interrupt timeouts. + */ + if ((host->chip->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) + count++; + + if (count >= 0xF) { + DBG("%s: Too large timeout requested!\n", + mmc_hostname(host->mmc)); + count = 0xE; + } + + /* Set the max time-out value to level up the compatibility */ + count = 0xE; + + count = + (count << 16) | (readl(host->ioaddr + SDHCI_CLOCK_CONTROL) & + 0xFFF0FFFF); + writel(count, host->ioaddr + SDHCI_CLOCK_CONTROL); + + if (host->flags & SDHCI_USE_DMA) + host->flags |= SDHCI_REQ_USE_DMA; + + if (unlikely((host->flags & SDHCI_REQ_USE_DMA) && + (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && + ((data->blksz * data->blocks) & 0x3))) { + printk("Reverting to PIO because of transfer size (%d)\n", + data->blksz * data->blocks); + host->flags &= ~SDHCI_REQ_USE_DMA; + } + + /* + * The assumption here being that alignment is the same after + * translation to device address space. + */ + if (unlikely((host->flags & SDHCI_REQ_USE_DMA) && + (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && + (data->sg->offset & 0x3))) { + printk("Reverting to PIO because of bad alignment\n"); + host->flags &= ~SDHCI_REQ_USE_DMA; + } + + if (((data->blksz * data->blocks) <= 128)) { + host->flags &= ~SDHCI_REQ_USE_DMA; + DBG("Reverting to PIO in small data transfer.\n"); + writel(readl(host->ioaddr + SDHCI_INT_ENABLE) + | SDHCI_INT_DATA_AVAIL + | SDHCI_INT_SPACE_AVAIL, + host->ioaddr + SDHCI_INT_ENABLE); + writel(readl(host->ioaddr + SDHCI_SIGNAL_ENABLE) + | SDHCI_INT_DATA_AVAIL + | SDHCI_INT_SPACE_AVAIL, + host->ioaddr + SDHCI_SIGNAL_ENABLE); + + if (host->id == 1) + sdhci_pio_counter++; + } else if (host->flags & SDHCI_USE_DMA) { + host->flags |= SDHCI_REQ_USE_DMA; + DBG("Reverting to DMA in large data transfer.\n"); + writel(readl(host->ioaddr + SDHCI_INT_ENABLE) + & ~(SDHCI_INT_DATA_AVAIL + | SDHCI_INT_SPACE_AVAIL), + host->ioaddr + SDHCI_INT_ENABLE); + writel(readl(host->ioaddr + SDHCI_SIGNAL_ENABLE) + & ~(SDHCI_INT_DATA_AVAIL + | SDHCI_INT_SPACE_AVAIL), + host->ioaddr + SDHCI_SIGNAL_ENABLE); + } + + if (host->flags & SDHCI_REQ_USE_DMA) { + int i; + struct scatterlist *tsg; + + DBG("Configure the sg DMA, %s, len is 0x%x\n", + (data->flags & MMC_DATA_READ) + ? "DMA_FROM_DEIVCE" : "DMA_TO_DEVICE", data->sg_len); + count = + dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, + (data-> + flags & MMC_DATA_READ) ? DMA_FROM_DEVICE : + DMA_TO_DEVICE); + BUG_ON(count != data->sg_len); + + /* Make sure the ADMA mode is selected. */ + i = readl(host->ioaddr + SDHCI_HOST_CONTROL); + i |= SDHCI_CTRL_ADMA; + writel(i, host->ioaddr + SDHCI_HOST_CONTROL); + + tsg = data->sg; + /* ADMA mode is used, create the descriptor table */ + for (i = 0; i < count; i++) { + if (tsg->dma_address & 0xFFF) { + DBG("ADMA addr isn't 4K aligned.\n"); + DBG("0x%x\n", tsg->dma_address); + DBG("Changed to Single DMA mode %d\n", count); + goto Single_DMA; + } + + adma_des_table[2 * i] = tsg->length << 12; + adma_des_table[2 * i] |= FSL_ADMA_DES_ATTR_SET; + adma_des_table[2 * i] |= FSL_ADMA_DES_ATTR_VALID; + adma_des_table[2 * i + 1] = tsg->dma_address; + adma_des_table[2 * i + 1] |= FSL_ADMA_DES_ATTR_TRAN; + adma_des_table[2 * i + 1] |= FSL_ADMA_DES_ATTR_VALID; + if (count == (i + 1)) + adma_des_table[2 * i + 1] |= + FSL_ADMA_DES_ATTR_END; + tsg++; + } + + /* Write the physical address to ADMA address reg */ + writel(virt_to_phys(adma_des_table), + host->ioaddr + SDHCI_ADMA_ADDRESS); + Single_DMA: + /* Rollback to the Single DMA mode */ + i = readl(host->ioaddr + SDHCI_HOST_CONTROL); + i &= ~SDHCI_CTRL_ADMA; + writel(i, host->ioaddr + SDHCI_HOST_CONTROL); + /* Single DMA mode is used */ + writel(sg_dma_address(data->sg), + host->ioaddr + SDHCI_DMA_ADDRESS); + } else if ((host->flags & SDHCI_USE_EXTERNAL_DMA) && + (data->blocks * data->blksz >= mxc_wml_value)) { + host->dma_size = data->blocks * data->blksz; + printk("Configure the External DMA, %s, len is 0x%x\n", + (data->flags & MMC_DATA_READ) + ? "DMA_FROM_DEIVCE" : "DMA_TO_DEVICE", host->dma_size); + + if (data->blksz & 0x3) { + printk(KERN_ERR + "mxc_mci: block size not multiple of 4 bytes\n"); + } + + if (data->flags & MMC_DATA_READ) + host->dma_dir = DMA_FROM_DEVICE; + else + host->dma_dir = DMA_TO_DEVICE; + + host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, + data->sg_len, host->dma_dir); + + if (data->flags & MMC_DATA_READ) { + mxc_dma_sg_config(host->dma, data->sg, data->sg_len, + host->dma_size, MXC_DMA_MODE_READ); + } else { + mxc_dma_sg_config(host->dma, data->sg, data->sg_len, + host->dma_size, MXC_DMA_MODE_WRITE); + } + } else { + host->cur_sg = data->sg; + host->num_sg = data->sg_len; + + host->offset = 0; + host->remain = host->cur_sg->length; + } + + /* We do not handle DMA boundaries, so set it to max (512 KiB) */ + writel((data->blocks << 16) | SDHCI_MAKE_BLKSZ(0, data->blksz), + host->ioaddr + SDHCI_BLOCK_SIZE); +} + +static void sdhci_finish_data(struct sdhci_host *host) +{ + struct mmc_data *data; + u16 blocks; + + BUG_ON(!host->data); + + data = host->data; + host->data = NULL; + + if (host->flags & SDHCI_REQ_USE_DMA) { + dma_unmap_sg(&(host->chip->pdev)->dev, data->sg, data->sg_len, + (data->flags & MMC_DATA_READ) ? DMA_FROM_DEVICE : + DMA_TO_DEVICE); + } + if ((host->flags & SDHCI_USE_EXTERNAL_DMA) && + (host->dma_size >= mxc_wml_value)) { + dma_unmap_sg(mmc_dev(host->mmc), data->sg, + host->dma_len, host->dma_dir); + host->dma_size = 0; + } + + /* + * Controller doesn't count down when in single block mode. + */ + if (data->blocks == 1) + blocks = (data->error == 0) ? 0 : 1; + else + blocks = readl(host->ioaddr + SDHCI_BLOCK_COUNT) >> 16; + data->bytes_xfered = data->blksz * data->blocks; + + if (host->id == 0) + sd1_turn_of_dma--; + + if (host->id == 1) + sd2_turn_of_dma--; + + sd_turn_of_dma = sd2_turn_of_dma | sd1_turn_of_dma; + + tasklet_schedule(&host->finish_tasklet); +} + +static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) +{ + int flags, tmp=0; + u32 mask; + u32 mode = 0; + unsigned long timeout; + + if ( (sdio_debug_level > 0) && (host->id == 1)) { + printk("sdhci_send_command is starting...\n"); + } + + WARN_ON(host->cmd); + + mask = SDHCI_CMD_INHIBIT; + if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) + mask |= SDHCI_DATA_INHIBIT; + + /* We shouldn't wait for data inihibit for stop commands, even + though they might use busy signaling */ + if (host->mrq->data && (cmd == host->mrq->data->stop)) + mask &= ~SDHCI_DATA_INHIBIT; + + if (host->id == 1) + sdhci_idle_bus_adjust(host, 0); + + /* Wait max 10 ms */ + timeout = (10*256) + 255; + + while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) { + if (timeout == 0) { + printk(KERN_ERR "%s: Controller never released " + "inhibit bit(s).\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + cmd->error = -EIO; + tasklet_schedule(&host->finish_tasklet); + return; + } + timeout--; + if (!(timeout & 0xFF)) + mdelay(1); + } + + mod_timer(&host->timer, jiffies + 10 * HZ); + + host->cmd = cmd; + + if (cmd->data != NULL) { + if (host->id == 0) + sd1_turn_of_dma++; + + if (host->id == 1) + sd2_turn_of_dma++; + + sd_turn_of_dma = sd2_turn_of_dma | sd1_turn_of_dma; + } + + sdhci_prepare_data(host, cmd->data); + + writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT); + + /* Set up the transfer mode */ + if (cmd->data != NULL) { + mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_DPSEL; + if (cmd->data->blocks > 1) { + if (host->mmc->predefined == 0 && (host->id == 0)) + mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12; + else + mode |= SDHCI_TRNS_MULTI; + tmp = readl(host->ioaddr + SDHCI_INT_ENABLE); + tmp &= ~SDHCI_INT_ACMD12ERR; + writel(tmp, host->ioaddr + SDHCI_INT_ENABLE); + } + + if (cmd->data->flags & MMC_DATA_READ) + mode |= SDHCI_TRNS_READ; + else + mode &= ~SDHCI_TRNS_READ; + if (host->flags & SDHCI_REQ_USE_DMA) + mode |= SDHCI_TRNS_DMA; + if (host->flags & SDHCI_USE_EXTERNAL_DMA) + printk("Prepare data completely in %s transfer mode.\n", + "EXTTERNAL DMA"); + } + + if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { + printk(KERN_ERR "%s: Unsupported response type!\n", + mmc_hostname(host->mmc)); + cmd->error = -EINVAL; + tasklet_schedule(&host->finish_tasklet); + return; + } + + if (!(cmd->flags & MMC_RSP_PRESENT)) + flags = SDHCI_CMD_RESP_NONE; + else if (cmd->flags & MMC_RSP_136) + flags = SDHCI_CMD_RESP_LONG; + else if (cmd->flags & MMC_RSP_BUSY) + flags = SDHCI_CMD_RESP_SHORT_BUSY; + else + flags = SDHCI_CMD_RESP_SHORT; + + if (cmd->flags & MMC_RSP_CRC) + flags |= SDHCI_CMD_CRC; + if (cmd->flags & MMC_RSP_OPCODE) + flags |= SDHCI_CMD_INDEX; + if (cmd->data) + flags |= SDHCI_CMD_DATA; + + mode |= SDHCI_MAKE_CMD(cmd->opcode, flags); + + if ( (sdio_debug_level > 0) && (host->id == 1)) { + printk("Complete sending cmd, transfer mode would be 0x%x\n", mode); + } + + writel(mode, host->ioaddr + SDHCI_TRANSFER_MODE); + + mask = SDHCI_CMD_INHIBIT; + timeout = (10*256) + 255; + while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) { + if (timeout == 0) { + printk(KERN_ERR "%s: Controller never released(2) " + "inhibit bit(s).\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + cmd->error = -EIO; + tasklet_schedule(&host->finish_tasklet); + return; + } + timeout--; + if (!(timeout & 0xFF)) + mdelay(1); + } +} + +static void sdhci_finish_command(struct sdhci_host *host) +{ + int i; + + BUG_ON(host->cmd == NULL); + + if (host->cmd->flags & MMC_RSP_PRESENT) { + if (host->cmd->flags & MMC_RSP_136) { + /* CRC is stripped so we need to do some shifting. */ + for (i = 0; i < 4; i++) { + host->cmd->resp[i] = readl(host->ioaddr + + SDHCI_RESPONSE + (3 - + i) + * 4) << 8; + if (i != 3) + host->cmd->resp[i] |= + readb(host->ioaddr + + SDHCI_RESPONSE + (3 - i) * 4 - + 1); + } + } else { + host->cmd->resp[0] = + readl(host->ioaddr + SDHCI_RESPONSE); + } + } + + host->cmd->error = 0; + + if (host->data && host->data_early) + sdhci_finish_data(host); + + if (!host->cmd->data) + tasklet_schedule(&host->finish_tasklet); + + host->cmd = NULL; +} + +static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) +{ + /*This variable holds the value of clock divider, prescaler */ + int div = 0, prescaler = 0; + int clk_rate = clk_get_rate(host->clk); + u32 clk; + unsigned long timeout; + + if (clock == 0) { + goto out; + } else { + if (host->id != 1) { + /* Non-SDIO slot */ + if (!host->plat_data->clk_flg) { + clk_enable(host->clk); + host->plat_data->clk_flg = 1; + } + } + else { + /* MMC1 */ + if (sdio_mmc1_clock) { + if (!host->plat_data->clk_flg) { + clk_enable(host->clk); + host->plat_data->clk_flg = 1; + } + } + } + } + + if (clock == host->clock) + return; + + clk = readl(host->ioaddr + SDHCI_CLOCK_CONTROL) & ~SDHCI_CLOCK_MASK; + writel(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); + + if (clock == 0) + goto out; + if (clock == host->min_clk) + prescaler = 16; + else + prescaler = 0; + while (prescaler <= 0x80) { + for (div = 0; div <= 0xF; div++) { + int x; + if (prescaler != 0) + x = (clk_rate / (div + 1)) / (prescaler * 2); + else + x = clk_rate / (div + 1); + + DBG("x=%d, clock=%d %d\n", x, clock, div); + if (x <= clock) + break; + } + if (div < 0x10) + break; + if (prescaler == 0) + prescaler = 1; + else + prescaler <<= 1; + } + DBG("prescaler = 0x%x, divider = 0x%x\n", prescaler, div); + clk |= (prescaler << 8) | (div << 4); + + /* Configure the clock control register */ + clk |= + (readl(host->ioaddr + SDHCI_CLOCK_CONTROL) & (~SDHCI_CLOCK_MASK)); + + if (host->plat_data->vendor_ver < ESDHC_VENDOR_V22) + writel(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); + else + writel(clk | SDHCI_CLOCK_SD_EN, + host->ioaddr + SDHCI_CLOCK_CONTROL); + + /* Wait max 10 ms */ + timeout = 10; + while (timeout > 0) { + timeout--; + mdelay(1); + } + +out: + if (prescaler != 0) + host->clock = (clk_rate / (div + 1)) / (prescaler * 2); + else + host->clock = clk_rate / (div + 1); +} + +static void sdhci_set_power(struct sdhci_host *host, unsigned short power) +{ + int voltage = 0; + + /* There is no PWR CTL REG */ + if (host->power == power) + return; + + if (host->regulator_mmc) { + if (power == (unsigned short)-1) { + regulator_disable(host->regulator_mmc); + pr_debug("mmc power off\n"); + } else { + if (power == 7) + voltage = 1800000; + else if (power >= 8) + voltage = 2000000 + (power - 8) * 100000; + regulator_set_voltage(host->regulator_mmc, voltage); + + if (regulator_enable(host->regulator_mmc) == 0) { + DBG("mmc power on : %d\n",voltage); + msleep(300); + } + } + } + + host->power = power; +} + +/*****************************************************************************\ + * * + * MMC callbacks * + * * +\*****************************************************************************/ + +static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) +{ + struct sdhci_host *host; + unsigned long flags; + + host = mmc_priv(mmc); + + /* Enable the clock */ + if (host->id != 1) { + if (!host->plat_data->clk_flg) { + clk_enable(host->clk); + host->plat_data->clk_flg = 1; + } + } + else { + if (sdio_mmc1_clock) { + if (!host->plat_data->clk_flg) { + clk_enable(host->clk); + host->plat_data->clk_flg = 1; + } + } + } + + if ((host->id == 1) && !sdio_mmc1_clock) + sdhci_sdio_clk(1); + + spin_lock_irqsave(&host->lock, flags); + + WARN_ON(host->mrq != NULL); + + sdhci_activate_led(host); + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 0) { + if (mrq->cmd && mrq->data) { + if (mrq->data->flags & MMC_DATA_READ) + last_op_dir = 1; + else { + if (last_op_dir) + sdhci_reset(host, + SDHCI_RESET_CMD | + SDHCI_RESET_DATA); + } + } + } + spin_unlock_irqrestore(&host->lock, flags); + + host->mrq = mrq; + if (!(host->flags & SDHCI_CD_PRESENT)) { + host->mrq->cmd->error = -ENOMEDIUM; + tasklet_schedule(&host->finish_tasklet); + } else + sdhci_send_command(host, mrq->cmd); + + mmiowb(); +} + +static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct sdhci_host *host; + unsigned long flags; + u32 tmp = 0; + mxc_dma_device_t dev_id = 0; + + DBG("%s: clock %u, bus %lu, power %u, vdd %u\n", DRIVER_NAME, + ios->clock, 1UL << ios->bus_width, ios->power_mode, ios->vdd); + + host = mmc_priv(mmc); + + /* Configure the External DMA mode */ + if (host->flags & SDHCI_USE_EXTERNAL_DMA) { + host->dma_dir = DMA_NONE; + if (mmc->ios.bus_width != host->mode) { + mxc_dma_free(host->dma); + if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) { + if (host->id == 0) + dev_id = MXC_DMA_MMC1_WIDTH_4; + else + dev_id = MXC_DMA_MMC2_WIDTH_4; + } else { + if (host->id == 0) + dev_id = MXC_DMA_MMC1_WIDTH_1; + else + dev_id = MXC_DMA_MMC2_WIDTH_1; + } + host->dma = mxc_dma_request(dev_id, "MXC MMC"); + if (host->dma < 0) + printk("Cannot allocate MMC DMA channel\n"); + mxc_dma_callback_set(host->dma, sdhci_dma_irq, + (void *)host); + /* Configure the WML rege */ + if (mxc_wml_value == 512) + writel(SDHCI_WML_128_WORDS, + host->ioaddr + SDHCI_WML); + else + writel(SDHCI_WML_16_WORDS, + host->ioaddr + SDHCI_WML); + } + } + + host->mode = mmc->ios.bus_width; + + spin_lock_irqsave(&host->lock, flags); + + /* + * Reset the chip on each power off. + * Should clear out any weird states. + */ + if (ios->power_mode == MMC_POWER_OFF) { + writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE); + sdhci_init(host); + } + + sdhci_set_clock(host, ios->clock); + + if (ios->power_mode == MMC_POWER_OFF) + sdhci_set_power(host, -1); + else + sdhci_set_power(host, ios->vdd); + + tmp = readl(host->ioaddr + SDHCI_HOST_CONTROL); + + if (ios->bus_width == MMC_BUS_WIDTH_8) { + tmp &= ~SDHCI_CTRL_4BITBUS; + tmp |= SDHCI_CTRL_8BITBUS; + host->flags &= ~SDHCI_IN_4BIT_MODE; + } else if (ios->bus_width == MMC_BUS_WIDTH_4) { + tmp &= ~SDHCI_CTRL_8BITBUS; + tmp |= SDHCI_CTRL_4BITBUS; + host->flags |= SDHCI_IN_4BIT_MODE; + } else if (ios->bus_width == MMC_BUS_WIDTH_1) { + tmp &= ~SDHCI_CTRL_4BITBUS; + tmp &= ~SDHCI_CTRL_8BITBUS; + host->flags &= ~SDHCI_IN_4BIT_MODE; + } + if (host->flags & SDHCI_USE_DMA) + tmp |= SDHCI_CTRL_ADMA; + + writel(tmp, host->ioaddr + SDHCI_HOST_CONTROL); + + /* + * Some (ENE) controllers go apeshit on some ios operation, + * signalling timeout and CRC errors even on CMD0. Resetting + * it on each ios seems to solve the problem. + */ + if (host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) + sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); + + mmiowb(); + spin_unlock_irqrestore(&host->lock, flags); +} + +static int sdhci_get_ro(struct mmc_host *mmc) +{ + struct sdhci_host *host; + + host = mmc_priv(mmc); + + if (host->plat_data->wp_status) + return host->plat_data->wp_status(mmc->parent); + else + return 0; +} + +static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) +{ + struct sdhci_host *host; + unsigned long flags; + u32 ier, prot, clk, present; + + host = mmc_priv(mmc); + + spin_lock_irqsave(&host->lock, flags); + + /* Enable the clock */ + if (host->id != 1) { + if (!host->plat_data->clk_flg) { + clk_enable(host->clk); + host->plat_data->clk_flg = 1; + } + } + else { + if (sdio_mmc1_clock) { + if (!host->plat_data->clk_flg) { + clk_enable(host->clk); + host->plat_data->clk_flg = 1; + } + } + } + + ier = readl(host->ioaddr + SDHCI_INT_ENABLE); + ier &= ~SDHCI_INT_CARD_INT; + + prot = readl(host->ioaddr + SDHCI_HOST_CONTROL); + clk = readl(host->ioaddr + SDHCI_CLOCK_CONTROL); + + if (enable) { + ier |= SDHCI_INT_CARD_INT; + prot |= SDHCI_CTRL_D3CD; + clk |= SDHCI_CLOCK_PER_EN | SDHCI_CLOCK_IPG_EN; + present = readl(host->ioaddr + SDHCI_PRESENT_STATE); + if ((present & SDHCI_CARD_INT_MASK) != SDHCI_CARD_INT_ID) + writel(SDHCI_INT_CARD_INT, + host->ioaddr + SDHCI_INT_STATUS); + } + else { + ier &= ~SDHCI_INT_CARD_INT; + prot &= ~SDHCI_CTRL_D3CD; + clk &= ~(SDHCI_CLOCK_PER_EN | SDHCI_CLOCK_IPG_EN); + } + + writel(ier, host->ioaddr + SDHCI_INT_ENABLE); + writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE); + writel(prot, host->ioaddr + SDHCI_HOST_CONTROL); + writel(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); + + mmiowb(); + spin_unlock_irqrestore(&host->lock, flags); +} + +static const struct mmc_host_ops sdhci_ops = { + .request = sdhci_request, + .set_ios = sdhci_set_ios, + .get_ro = sdhci_get_ro, + .enable_sdio_irq = sdhci_enable_sdio_irq, +}; + +/*****************************************************************************\ + * * + * Tasklets * + * * +\*****************************************************************************/ + +static void sdhci_tasklet_card(unsigned long param) +{ + struct sdhci_host *host; + unsigned long flags; + unsigned int cd_status = 0; + + host = (struct sdhci_host *)param; + + if (host->flags & SDHCI_CD_PRESENT) + host->flags &= ~SDHCI_CD_PRESENT; + else + host->flags |= SDHCI_CD_PRESENT; + /* Detect there is a card in slot or not */ + DBG("cd_status=%d %s\n", cd_status, + (host->flags & SDHCI_CD_PRESENT) ? "inserted" : "removed"); + + if (cd_status) { + regulator_disable(vsd_reg); + } + else { + regulator_enable(vsd_reg); + regulator_set_voltage(vsd_reg, 3150000); + } + + spin_lock_irqsave(&host->lock, flags); + + if (!(host->flags & SDHCI_CD_PRESENT)) { + if (host->mrq) { + printk(KERN_ERR "%s: Card removed during transfer!\n", + mmc_hostname(host->mmc)); + printk(KERN_ERR "%s: Resetting controller.\n", + mmc_hostname(host->mmc)); + + sdhci_reset(host, SDHCI_RESET_CMD); + sdhci_reset(host, SDHCI_RESET_DATA); + + host->mrq->cmd->error = -ENOMEDIUM; + tasklet_schedule(&host->finish_tasklet); + } + } + + spin_unlock_irqrestore(&host->lock, flags); + + mmc_detect_change(host->mmc, msecs_to_jiffies(500)); +} + +static void sdhci_tasklet_finish(unsigned long param) +{ + struct sdhci_host *host; + unsigned long flags; + struct mmc_request *mrq; + + host = (struct sdhci_host *)param; + + spin_lock_irqsave(&host->lock, flags); + + del_timer(&host->timer); + + mrq = host->mrq; + + if (mrq->data && (mrq->data->error || + (mrq->data->stop && mrq->data->stop->error))) { + printk(KERN_ERR "Data error on %d: %d\n", host->id, mrq->data->error); + } + + /* + * The controller needs a reset of internal state machines + * upon error conditions. + */ + if (mrq->cmd->error || + (mrq->data && (mrq->data->error || + (mrq->data->stop && mrq->data->stop->error))) || + (host->chip->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { + + /* Some controllers need this kick or reset won't work here */ + if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) { + unsigned int clock; + + /* This is to force an update */ + clock = host->clock; + host->clock = 0; + sdhci_set_clock(host, clock); + } + + /* Spec says we should do both at the same time, but Ricoh + controllers do not like that. */ + sdhci_reset(host, SDHCI_RESET_CMD); + sdhci_reset(host, SDHCI_RESET_DATA); + } + + host->mrq = NULL; + host->cmd = NULL; + host->data = NULL; + + if (host->id == 1) + sdhci_idle_bus_adjust(host, 1); + sdhci_deactivate_led(host); + + mmiowb(); + + spin_unlock_irqrestore(&host->lock, flags); + + /* Stop the clock when the req is done */ + flags = SDHCI_DATA_ACTIVE | SDHCI_DOING_WRITE | SDHCI_DOING_READ; + if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & flags)) { + if (host->id != 1) { + if (host->plat_data->clk_flg) { + clk_disable(host->clk); + host->plat_data->clk_flg = 0; + } + } + else { + if (sdio_mmc1_clock) { + if (host->plat_data->clk_flg) { + clk_disable(host->clk); + host->plat_data->clk_flg = 0; + } + } + } + } + + mmc_request_done(host->mmc, mrq); +} + +static void sdhci_timeout_timer(unsigned long data) +{ + struct sdhci_host *host; + unsigned long flags; + + host = (struct sdhci_host *)data; + + spin_lock_irqsave(&host->lock, flags); + + if (host->mrq) { + printk(KERN_ERR "%s: Timeout waiting for hardware " + "interrupt.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + + if (host->data) { + host->data->error = -ETIMEDOUT; + sdhci_finish_data(host); + } else { + if (host->cmd) + host->cmd->error = -ETIMEDOUT; + else + host->mrq->cmd->error = -ETIMEDOUT; + + tasklet_schedule(&host->finish_tasklet); + } + } + + mmiowb(); + spin_unlock_irqrestore(&host->lock, flags); +} + +/*****************************************************************************\ + * * + * Interrupt handling * + * * +\*****************************************************************************/ + +static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) +{ + BUG_ON(intmask == 0); + + if (!host->cmd) { + printk(KERN_ERR "%s: Got command interrupt 0x%08x even " + "though no command operation was in progress.\n", + mmc_hostname(host->mmc), (unsigned)intmask); + sdhci_dumpregs(host); + return; + } + + if (intmask & SDHCI_INT_ACMD12ERR) { + int tmp = 0; + tmp = readl(host->ioaddr + SDHCI_ACMD12_ERR); + if (tmp & (SDHCI_ACMD12_ERR_CE | SDHCI_ACMD12_ERR_IE | + SDHCI_ACMD12_ERR_EBE)) + host->cmd->error = -EILSEQ; + else if (tmp & SDHCI_ACMD12_ERR_TOE) + host->cmd->error = -ETIMEDOUT; + } + + if (intmask & SDHCI_INT_TIMEOUT) + host->cmd->error = -ETIMEDOUT; + else if (intmask & SDHCI_INT_CRC) + host->cmd->error = -EILSEQ; + else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) + host->cmd->error = -EIO; + + if (host->cmd->error) + tasklet_schedule(&host->finish_tasklet); + else if (intmask & SDHCI_INT_RESPONSE) + sdhci_finish_command(host); +} + +static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) +{ + u32 intsave = 0; + + BUG_ON(intmask == 0); + + if (!host->data) { + /* + * A data end interrupt is sent together with the response + * for the stop command. + */ + if (intmask & SDHCI_INT_DATA_END) + return; + + printk(KERN_ERR "%s: Got data interrupt 0x%08x even " + "though no data operation was in progress.\n", + mmc_hostname(host->mmc), (unsigned)intmask); + sdhci_dumpregs(host); + return; + } + + /* Mask the INT */ + intsave = readl(host->ioaddr + SDHCI_INT_ENABLE); + writel(intsave & (~(intmask & SDHCI_INT_DATA_RE_MASK)), + host->ioaddr + SDHCI_INT_ENABLE); + + if (intmask & SDHCI_INT_DATA_TIMEOUT) + host->data->error = -ETIMEDOUT; + else if (intmask & SDHCI_INT_DATA_CRC) + host->data->error = -EILSEQ; + else if (intmask & SDHCI_INT_DATA_END_BIT) + host->data->error = -EIO; + + if (host->data->error) + sdhci_finish_data(host); + else { + if ((host->flags & SDHCI_USE_EXTERNAL_DMA) && + (host->dma_size >= mxc_wml_value)) { + /* Use DMA if transfer size is greater than fifo size */ + if (intmask & (SDHCI_INT_DATA_AVAIL | + SDHCI_INT_SPACE_AVAIL)) { + intsave &= ~SDHCI_INT_DATA_RE_MASK; + if (mxc_dma_enable(host->dma) < 0) { + printk(KERN_ERR "ENABLE SDMA ERR.\n"); + intsave |= SDHCI_INT_DATA_RE_MASK; + } + } + } else { + if (intmask & (SDHCI_INT_DATA_AVAIL | + SDHCI_INT_SPACE_AVAIL)) + sdhci_transfer_pio(host); + } + + /* + * We currently don't do anything fancy with DMA + * boundaries, but as we can't disable the feature + * we need to at least restart the transfer. + */ + if ((intmask & SDHCI_INT_DMA_END) && + (!(intmask & SDHCI_INT_DATA_END))) + writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS), + host->ioaddr + SDHCI_DMA_ADDRESS); + + if (intmask & SDHCI_INT_DATA_END) { + if ((host->id == 0) && (host->data->flags & MMC_DATA_READ)) + writel(readl(host->ioaddr + SDHCI_CLOCK_CONTROL) + & ~SDHCI_CLOCK_HLK_EN, + host->ioaddr + SDHCI_CLOCK_CONTROL); + + if (host->cmd) { + /* + * Data managed to finish before the + * command completed. Make sure we do + * things in the proper order. + */ + host->data_early = 1; + } else { + + if (host->plat_data->vendor_ver + < ESDHC_VENDOR_V22) { + /* + * There are the DATA END INT when + * writing is not complete. Double + * check on it. TO2 has been fixed it. + */ + intmask = readl(host->ioaddr + + SDHCI_PRESENT_STATE); + if (intmask & SDHCI_DATA_ACTIVE) + goto data_irq_out; + } + sdhci_finish_data(host); + } + } + } + data_irq_out: + /* Enable the INT */ + writel(intsave, host->ioaddr + SDHCI_INT_ENABLE); +} + +/*! +* This function is called by DMA Interrupt Service Routine to indicate +* requested DMA transfer is completed. +* +* @param devid pointer to device specific structure +* @param error any DMA error +* @param cnt amount of data that was transferred +*/ +static void sdhci_dma_irq(void *devid, int error, unsigned int cnt) +{ + u32 intsave = 0; + int ret; + struct sdhci_host *host = devid; + + printk("%s: error: %d Transferred bytes:%d\n", DRIVER_NAME, error, cnt); + if (host->flags & SDHCI_USE_EXTERNAL_DMA) { + /* + * Stop the DMA transfer here, the data_irq would be called + * to process the others + */ + ret = mxc_dma_disable(host->dma); + if (ret < 0) + printk(KERN_ERR "Disable dma channel err %d\n", ret); + + if (error) { + printk("Error in DMA transfer\n"); + return; + } + intsave = readl(host->ioaddr + SDHCI_INT_ENABLE); + intsave |= SDHCI_INT_DATA_RE_MASK; + writel(intsave, host->ioaddr + SDHCI_INT_ENABLE); + } +} + +/* woke queue handler func */ +static void esdhc_cd_callback(struct work_struct *work) +{ + unsigned long flags; + unsigned int cd_status = 0; + struct sdhci_host *host = container_of(work, struct sdhci_host, cd_wq); + + cd_status = host->plat_data->status(host->mmc->parent); + if (cd_status) + host->flags &= ~SDHCI_CD_PRESENT; + else + host->flags |= SDHCI_CD_PRESENT; + /* Detect there is a card in slot or not */ + printk("cd_status=%d %s\n", cd_status, + (host->flags & SDHCI_CD_PRESENT) ? "inserted" : "removed"); + + if (cd_status) { + regulator_disable(vsd_reg); + } + else { + regulator_enable(vsd_reg); + regulator_set_voltage(vsd_reg, 3150000); + mdelay(100); + } + + spin_lock_irqsave(&host->lock, flags); + + if (!(host->flags & SDHCI_CD_PRESENT)) { + printk(KERN_ERR + "%s: Card removed and resetting controller.\n", + mmc_hostname(host->mmc)); + sdhci_init(host); + if (host->mrq) { + printk(KERN_ERR + "%s: Card removed during transfer!\n", + mmc_hostname(host->mmc)); + printk(KERN_ERR + "%s: Resetting controller.\n", + mmc_hostname(host->mmc)); + + sdhci_reset(host, SDHCI_RESET_CMD); + sdhci_reset(host, SDHCI_RESET_DATA); + + host->mrq->cmd->error = -ENOMEDIUM; + tasklet_schedule(&host->finish_tasklet); + } + } + + spin_unlock_irqrestore(&host->lock, flags); + + mmc_detect_change(host->mmc, msecs_to_jiffies(500)); + + do { + cd_status = host->plat_data->status(host->mmc->parent); + if (cd_status) + set_irq_type(host->detect_irq, IRQT_FALLING); + else + set_irq_type(host->detect_irq, IRQT_RISING); + } while (cd_status != host->plat_data->status(host->mmc->parent)); +} + +/*! +* Card detection interrupt service routine registered to handle +* the SDHC interrupts. This interrupt routine handles card +* insertion and card removal interrupts. +* +* @param irq the interrupt number +* @param devid driver private data +* +* @return The function returns \b IRQ_RETVAL(1) +*/ +static irqreturn_t sdhci_cd_irq(int irq, void *dev_id) +{ + struct sdhci_host *host = dev_id; + + schedule_work(&host->cd_wq); + return IRQ_HANDLED; +} + +static irqreturn_t sdhci_irq(int irq, void *dev_id) +{ + irqreturn_t result; + struct sdhci_host *host = dev_id; + u32 intmask; + int cardint = 0; + + spin_lock(&host->lock); + + if (host->id == 1) + sdhci_sdio_clk(1); + + intmask = readl(host->ioaddr + SDHCI_INT_STATUS); + + if (!intmask || intmask == 0xffffffff) { + result = IRQ_NONE; + goto out; + } + + DBG("*** %s got interrupt: 0x%08x\n", mmc_hostname(host->mmc), intmask); + + if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { + writel(intmask & + (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE), + host->ioaddr + SDHCI_INT_STATUS); + tasklet_schedule(&host->card_tasklet); + } + + intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); + + if (intmask & SDHCI_INT_CMD_MASK) { + writel(intmask & SDHCI_INT_CMD_MASK, + host->ioaddr + SDHCI_INT_STATUS); + sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); + } + + if (intmask & SDHCI_INT_DATA_MASK) { + writel(intmask & SDHCI_INT_DATA_MASK, + host->ioaddr + SDHCI_INT_STATUS); + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 0) { + if (! + (readl(host->ioaddr + SDHCI_TRANSFER_MODE) & + SDHCI_TRNS_READ)) + intmask &= ~SDHCI_INT_DATA_END_BIT; + } + sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); + } + + intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); + + intmask &= ~SDHCI_INT_ERROR; + + if (intmask & SDHCI_INT_BUS_POWER) { + printk(KERN_ERR "%s: Card is consuming too much power!\n", + mmc_hostname(host->mmc)); + writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS); + } + + intmask &= ~SDHCI_INT_BUS_POWER; + + if (intmask & SDHCI_INT_CARD_INT) { + if (host->id == 1) + cardint_stat++; + if (readl(host->ioaddr + SDHCI_INT_ENABLE) & SDHCI_INT_CARD_INT) { + cardint = 1; + } + } + + intmask &= ~SDHCI_INT_CARD_INT; + + if (intmask) { + printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n", + mmc_hostname(host->mmc), intmask); + sdhci_dumpregs(host); + + writel(intmask, host->ioaddr + SDHCI_INT_STATUS); + } + + result = IRQ_HANDLED; + + mmiowb(); +out: + spin_unlock(&host->lock); + + /* + * We have to delay this as it calls back into the driver. + */ + if (cardint) { + cardint_sdio_irq++; + sdhci_sdio_clk(1); + mmc_signal_sdio_irq(host->mmc); + } + + return result; +} + +/*****************************************************************************\ + * * + * Suspend/resume * + * * +\*****************************************************************************/ + +#ifdef CONFIG_PM + +static int sdhci_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct sdhci_chip *chip; + int i, ret; + + chip = dev_get_drvdata(&pdev->dev); + if (!chip) + return 0; + + /* + * Bus #1 is the SDIO bus for the Atheros WiFi chip. Simply gate the clock + * and deactivate the GPIOs. We dont want to call mmc_suspend_host() as + * SDIO does not have a suspend/resume function. SDIO stack will simply + * remove the MMC1 card and try to re-attach. This is not acceptable to + * all cards. + */ + if (pdev->id == 1) { + clk_disable(chip->hosts[0]->clk); + goto out_suspend; + } + + for (i = 0; i < chip->num_slots; i++) { + if (!chip->hosts[i]) + continue; + ret = mmc_suspend_host(chip->hosts[i]->mmc, state); + if (ret) { + for (i--; i >= 0; i--) + mmc_resume_host(chip->hosts[i]->mmc); + return ret; + } + } + + for (i = 0; i < chip->num_slots; i++) { + if (!chip->hosts[i]) + continue; + + if (i == 2) + regulator_disable(vsd_reg); + + free_irq(chip->hosts[i]->detect_irq, chip->hosts[i]); + free_irq(chip->hosts[i]->irq, chip->hosts[i]); + clk_disable(chip->hosts[i]->clk); + } + +out_suspend: + gpio_sdhc_inactive(pdev->id); + + return 0; +} + +static int sdhci_resume(struct platform_device *pdev) +{ + struct sdhci_chip *chip; + int i, ret; + unsigned int cd_status = 0; + + chip = dev_get_drvdata(&pdev->dev); + if (!chip) + return 0; + + gpio_sdhc_active(pdev->id); + + /* + * MMC1 is the SDIO stack for Atheros chip + */ + if (pdev->id == 1) { + clk_enable(chip->hosts[0]->clk); + chip->hosts[0]->plat_data->clk_flg = 1; + schedule_delayed_work(&sdio_mmc1_resume_wq, msecs_to_jiffies(SDIO_CLK_RESUME_THRESHOLD)); + return 0; + } + + for (i = 0; i < chip->num_slots; i++) { + if (!chip->hosts[i]) + continue; + + if (i == 2) { + regulator_enable(vsd_reg); + regulator_set_voltage(vsd_reg, 3150000); + mdelay(10); + } + + ret = request_irq(chip->hosts[i]->detect_irq, sdhci_cd_irq, + IRQF_DISABLED, + mmc_hostname(chip->hosts[i]->mmc), + chip->hosts[i]); + + if (ret) + return ret; + + ret = request_irq(chip->hosts[i]->irq, sdhci_irq, + IRQF_SHARED, + mmc_hostname(chip->hosts[i]->mmc), + chip->hosts[i]); + if (ret) + return ret; + sdhci_init(chip->hosts[i]); + mmiowb(); + + cd_status = chip->hosts[i]->plat_data->status(chip->hosts[i]->mmc->parent); + if (cd_status) + chip->hosts[i]->flags &= ~SDHCI_CD_PRESENT; + else + chip->hosts[i]->flags |= SDHCI_CD_PRESENT; + + ret = mmc_resume_host(chip->hosts[i]->mmc); + if (ret) + return ret; + + if ((i == 2) && cd_status) { + ret = regulator_disable(vsd_reg); + if (ret < 0) + printk(KERN_ERR "Failed to turn off VSD regulator: %d\n", ret); + } + clk_disable(chip->hosts[i]->clk); + chip->hosts[i]->plat_data->clk_flg = 0; + } + + return 0; +} + +#else /* CONFIG_PM */ + +#define sdhci_suspend NULL +#define sdhci_resume NULL + +#endif /* CONFIG_PM */ + +/*****************************************************************************\ + * * + * Device probing/removal * + * * +\*****************************************************************************/ + +#ifdef CONFIG_FEC +#define HAS_8BIT_MMC() 0 +#else +#define HAS_8BIT_MMC() ((IS_LUIGI() && (GET_BOARD_HW_VERSION() >= 4)) || \ + (IS_SHASTA() && !(IS_EVT() && (GET_BOARD_HW_VERSION() == 1)))) +#endif + +static int __devinit sdhci_probe_slot(struct platform_device + *pdev, int slot) +{ + struct mxc_mmc_platform_data *mmc_plat = pdev->dev.platform_data; + int ret = 0; + unsigned int version, caps; + struct sdhci_chip *chip; + struct mmc_host *mmc; + struct sdhci_host *host; + mxc_dma_device_t dev_id = 0; + + if (!mmc_plat) + return -EINVAL; + + chip = dev_get_drvdata(&pdev->dev); + BUG_ON(!chip); + + mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev); + if (!mmc) + return -ENOMEM; + + host = mmc_priv(mmc); + host->mmc = mmc; + host->dma = -1; + host->plat_data = mmc_plat; + if (!host->plat_data) { + ret = -EINVAL; + goto out0; + } + + if (pdev->id == 1) + sdio_host = host; + + host->chip = chip; + chip->hosts[slot] = host; + + /* Active the eSDHC bus */ + gpio_sdhc_active(pdev->id); + + vsd_reg = regulator_get(NULL, "VSD"); + regulator_disable(vsd_reg); + if (IS_SHASTA()) + mdelay(5); + else + mdelay(500); + regulator_enable(vsd_reg); + regulator_set_voltage(vsd_reg, 3150000); + + host->id = pdev->id; + + if ((pdev->id == 2) && host->plat_data->status(host->mmc->parent)) { + regulator_disable(vsd_reg); + mdelay(10); + } + + /* Get the SDHC clock from clock system APIs */ + host->clk = clk_get(&pdev->dev, mmc_plat->clock_mmc); + if (NULL == host->clk) + printk(KERN_ERR "MXC MMC can't get clock.\n"); + DBG("SDHC:%d clock:%lu\n", pdev->id, clk_get_rate(host->clk)); + + host->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!host->res) { + ret = -ENOMEM; + goto out1; + } + host->irq = platform_get_irq(pdev, 0); + + if (!host->irq) { + ret = -ENOMEM; + goto out1; + } + + host->detect_irq = platform_get_irq(pdev, 1); + if (!host->detect_irq) { + ret = -ENOMEM; + goto out1; + } + + do { + ret = host->plat_data->status(host->mmc->parent); + if (ret) + set_irq_type(host->detect_irq, IRQT_FALLING); + else + set_irq_type(host->detect_irq, IRQT_RISING); + } while (ret != host->plat_data->status(host->mmc->parent)); + + ret = host->plat_data->status(host->mmc->parent); + if (ret) + host->flags &= ~SDHCI_CD_PRESENT; + else + host->flags |= SDHCI_CD_PRESENT; + + DBG("slot %d at 0x%x, irq %d\n", slot, host->res->start, host->irq); + + if (!request_mem_region(host->res->start, + resource_size(host->res), pdev->name)) { + printk(KERN_ERR "request_mem_region failed\n"); + ret = -ENOMEM; + goto out1; + } + host->ioaddr = (void *)ioremap(host->res->start, + resource_size(host->res)); + if (!host->ioaddr) { + ret = -ENOMEM; + goto out3; + } + + sdhci_reset(host, SDHCI_RESET_ALL); + + version = readl(host->ioaddr + SDHCI_HOST_VERSION); + host->plat_data->vendor_ver = (version & SDHCI_VENDOR_VER_MASK) >> + SDHCI_VENDOR_VER_SHIFT; + version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; + if (version != 1) { + printk(KERN_ERR "%s: Unknown controller version (%d). " + "You may experience problems.\n", mmc_hostname(mmc), + version); + } + + caps = readl(host->ioaddr + SDHCI_CAPABILITIES); + + if (chip->quirks & SDHCI_QUIRK_FORCE_DMA) + host->flags |= SDHCI_USE_DMA; + else if (!(caps & SDHCI_CAN_DO_DMA)) + printk("Controller doesn't have DMA capability\n"); + else if (chip-> + quirks & (SDHCI_QUIRK_INTERNAL_ADVANCED_DMA | + SDHCI_QUIRK_INTERNAL_SIMPLE_DMA)) + host->flags |= SDHCI_USE_DMA; + else if (chip->quirks & (SDHCI_QUIRK_EXTERNAL_DMA_MODE)) + host->flags |= SDHCI_USE_EXTERNAL_DMA; + else + host->flags &= ~SDHCI_USE_DMA; + + /* + * These definitions of eSDHC are not compatible with the SD Host + * Controller Spec v2.0 + */ + host->min_clk = mmc_plat->min_clk; + host->max_clk = mmc_plat->max_clk; + host->timeout_clk = 1024 * 1000; /* Just set the value temply. */ + + /* + * Set host parameters. + */ + mmc->ops = &sdhci_ops; + mmc->f_min = host->min_clk; + mmc->f_max = host->max_clk; + + /* Third slot is the SD card */ + if (host->id == 0) { + mmc->caps = MMC_CAP_MMC_HIGHSPEED; + + if ( HAS_8BIT_MMC() ) { + mmc->caps |= MMC_CAP_8_BIT_DATA; + printk(KERN_INFO "%s: Using 8-bit bus width\n", mmc_hostname(mmc)); + } + else { + mmc->caps |= MMC_CAP_4_BIT_DATA; + printk(KERN_INFO "%s: Using 4-bit bus width\n", mmc_hostname(mmc)); + } + } + else + mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ; + + mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NON_REMOVABLE; + + mmc->ocr_avail = 0; + + if (caps & SDHCI_CAN_VDD_330) + mmc->ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; + if (caps & SDHCI_CAN_VDD_300) + mmc->ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; + if (caps & SDHCI_CAN_VDD_180) + mmc->ocr_avail |= MMC_VDD_165_195; + + if (mmc->ocr_avail == 0) { + printk(KERN_ERR "%s: Hardware doesn't report any " + "support voltages.\n", mmc_hostname(mmc)); + ret = -ENODEV; + goto out3; + } + + spin_lock_init(&host->lock); + + /* + * Maximum number of segments. Hardware cannot do scatter lists. + */ + if (host->flags & SDHCI_USE_DMA) + mmc->max_hw_segs = 1; + else + mmc->max_hw_segs = 16; + mmc->max_phys_segs = 16; + + /* + * Maximum number of sectors in one transfer. Limited by DMA boundary + * size (512KiB). + */ + if (host->flags & SDHCI_USE_EXTERNAL_DMA) + mmc->max_req_size = 32 * 1024; + else + mmc->max_req_size = 64 * 1024; + + /* + * Maximum segment size. Could be one segment with the maximum number + * of bytes. + */ + mmc->max_seg_size = mmc->max_req_size; + + /* + * Maximum block size. This varies from controller to controller and + * is specified in the capabilities register. + */ + mmc->max_blk_size = + (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT; + if (mmc->max_blk_size > 3) { + printk(KERN_WARNING "%s: Invalid maximum block size, " + "assuming 512 bytes\n", mmc_hostname(mmc)); + mmc->max_blk_size = 512; + } else + mmc->max_blk_size = 512 << mmc->max_blk_size; + + /* + * Maximum block count: SD cards can take more blocks + */ + mmc->max_blk_count = 128; + + /* + * Apply a continous physical memory used for storing the ADMA + * descriptor table. + */ + if (host->flags & SDHCI_USE_DMA) { + adma_des_table = kcalloc((2 * (mmc->max_phys_segs) + 1), + sizeof(unsigned int), GFP_DMA); + if (adma_des_table == NULL) { + printk(KERN_ERR "Cannot allocate ADMA memory\n"); + ret = -ENOMEM; + goto out3; + } + } + + /* + * Init tasklets. + */ + tasklet_init(&host->card_tasklet, + sdhci_tasklet_card, (unsigned long)host); + tasklet_init(&host->finish_tasklet, + sdhci_tasklet_finish, (unsigned long)host); + + /* initialize the work queue */ + INIT_WORK(&host->cd_wq, esdhc_cd_callback); + + setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); + + ret = request_irq(host->detect_irq, sdhci_cd_irq, 0, pdev->name, host); + if (ret) + goto out4; + + ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, pdev->name, host); + if (ret) + goto out5; + + sdhci_init(host); + + if (host->flags & SDHCI_USE_EXTERNAL_DMA) { + /* Apply the 1-bit SDMA channel. */ + if (host->id == 0) + dev_id = MXC_DMA_MMC1_WIDTH_1; + else + dev_id = MXC_DMA_MMC2_WIDTH_1; + host->dma = mxc_dma_request(dev_id, "MXC MMC"); + if (host->dma < 0) { + printk("Cannot allocate MMC DMA channel\n"); + goto out6; + } + mxc_dma_callback_set(host->dma, sdhci_dma_irq, (void *)host); + } +#ifdef CONFIG_MMC_DEBUG + sdhci_dumpregs(host); +#endif + mmiowb(); + + if (mmc_add_host(mmc) < 0) + goto out6; + + if (host->flags & SDHCI_USE_EXTERNAL_DMA) + printk(KERN_INFO "%s: SDHCI detect irq %d irq %d %s\n", + mmc_hostname(mmc), host->detect_irq, host->irq, + "EXTERNAL DMA"); + else + printk(KERN_INFO "%s: SDHCI detect irq %d irq %d %s\n", + mmc_hostname(mmc), host->detect_irq, host->irq, + (host->flags & SDHCI_USE_DMA) ? "INTERNAL DMA" : "PIO"); + + if (device_create_file(&pdev->dev, &dev_attr_sdhci_registers) < 0) { + printk (KERN_ERR "mx_sdhci: could not create the sdhci_registers /sys\n"); + } + + if (device_create_file(&pdev->dev, &dev_attr_sdio_debug) < 0) { + printk (KERN_ERR "mx_sdhci: could not create the sdio_debug /sys\n"); + } + + if (device_create_file(&pdev->dev, &dev_attr_sdio_pio_transfers) < 0) { + printk (KERN_ERR "mx_sdhci: could not create the sdio_pio_transfers /sys\n"); + } + + if (device_create_file(&pdev->dev, &dev_attr_sdio_lpm_idle) < 0) { + printk (KERN_ERR "mx_sdhci: could not create the sdio_lpm_idle /sys\n"); + } + + if (device_create_file(&pdev->dev, &dev_attr_sdio_lpm_threshold) < 0) { + printk (KERN_ERR "mx_sdhci: could not create the dev_attr_sdio_lpm_threshold /sys\n"); + } + + return 0; + +out6: + free_irq(host->irq, host); +out5: + if (host->detect_irq) + free_irq(host->detect_irq, host); +out4: + del_timer_sync(&host->timer); + tasklet_kill(&host->card_tasklet); + tasklet_kill(&host->finish_tasklet); +out3: + if (host->flags & SDHCI_USE_DMA) + kfree(adma_des_table); + release_mem_region(host->res->start, + resource_size(host->res)); +out1: + clk_disable(host->clk); + host->plat_data->clk_flg = 0; + gpio_sdhc_inactive(pdev->id); +out0: + mmc_free_host(mmc); + return ret; +} + +static void sdhci_remove_slot(struct platform_device *pdev, int slot) +{ + struct sdhci_chip *chip; + struct mmc_host *mmc; + struct sdhci_host *host; + + chip = dev_get_drvdata(&pdev->dev); + host = chip->hosts[slot]; + mmc = host->mmc; + + mmc_remove_host(mmc); + + sdhci_reset(host, SDHCI_RESET_ALL); + + if (host->detect_irq) + free_irq(host->detect_irq, host); + free_irq(host->irq, host); + if (chip->quirks & SDHCI_QUIRK_EXTERNAL_DMA_MODE) { + host->flags &= ~SDHCI_USE_EXTERNAL_DMA; + mxc_dma_free(host->dma); + } + + del_timer_sync(&host->timer); + + tasklet_kill(&host->card_tasklet); + tasklet_kill(&host->finish_tasklet); + + if (host->flags & SDHCI_USE_DMA) + kfree(adma_des_table); + release_mem_region(host->res->start, resource_size(host->res)); + clk_disable(host->clk); + host->plat_data->clk_flg = 0; + mmc_free_host(mmc); + gpio_sdhc_inactive(pdev->id); + + if (pdev->id == 2) + regulator_disable(vsd_reg); + + device_remove_file(&pdev->dev, &dev_attr_sdhci_registers); + device_remove_file(&pdev->dev, &dev_attr_sdio_debug); + device_remove_file(&pdev->dev, &dev_attr_sdio_pio_transfers); + device_remove_file(&pdev->dev, &dev_attr_sdio_lpm_idle); + device_remove_file(&pdev->dev, &dev_attr_sdio_lpm_threshold); +} + +static int sdhci_probe(struct platform_device *pdev) +{ + int ret = 0, i; + u8 slots = 1; + struct sdhci_chip *chip; + + printk(KERN_INFO DRIVER_NAME ": MXC SDHCI Controller Driver. \n"); + BUG_ON(pdev == NULL); + + chip = kzalloc(sizeof(struct sdhci_chip) + + sizeof(struct sdhci_host *) * slots, GFP_KERNEL); + if (!chip) { + ret = -ENOMEM; + goto err; + } + + /* Distinguish different platform */ + if (machine_is_mx37_3ds()) { + mxc_quirks = SDHCI_QUIRK_EXTERNAL_DMA_MODE; + } else { + mxc_quirks = SDHCI_QUIRK_INTERNAL_ADVANCED_DMA | + SDHCI_QUIRK_INTERNAL_SIMPLE_DMA; + } + chip->pdev = pdev; + chip->quirks = mxc_quirks; + + if (debug_quirks) + chip->quirks = debug_quirks; + + chip->num_slots = slots; + dev_set_drvdata(&pdev->dev, chip); + + for (i = 0; i < slots; i++) { + ret = sdhci_probe_slot(pdev, i); + if (ret) { + for (i--; i >= 0; i--) + sdhci_remove_slot(pdev, i); + goto free; + } + } + + return 0; + + free: + dev_set_drvdata(&pdev->dev, NULL); + kfree(chip); + + err: + return ret; +} + +static int sdhci_remove(struct platform_device *pdev) +{ + int i; + struct sdhci_chip *chip; + + chip = dev_get_drvdata(&pdev->dev); + + if (chip) { + for (i = 0; i < chip->num_slots; i++) + sdhci_remove_slot(pdev, i); + + dev_set_drvdata(&pdev->dev, NULL); + + kfree(chip); + } + + return 0; +} + +/* Invoked on Shutdown */ +static void sdhci_shutdown(struct platform_device *pdev) +{ + sdhci_remove(pdev); +} + +static struct platform_driver sdhci_driver = { + .driver = { + .name = DRIVER_NAME, + }, + .probe = sdhci_probe, + .remove = sdhci_remove, + .suspend = sdhci_suspend, + .resume = sdhci_resume, + .shutdown = sdhci_shutdown, +}; + +/*****************************************************************************\ + * * + * Driver init/exit * + * * +\*****************************************************************************/ + +static int __init sdhci_drv_init(void) +{ + printk(KERN_INFO DRIVER_NAME + ": MXC Secure Digital Host Controller Interface driver\n"); + return platform_driver_register(&sdhci_driver); +} + +static void __exit sdhci_drv_exit(void) +{ + DBG("Exiting\n"); + + platform_driver_unregister(&sdhci_driver); +} + +module_init(sdhci_drv_init); +module_exit(sdhci_drv_exit); + +module_param(debug_quirks, uint, 0444); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC Secure Digital Host Controller Interface driver"); +MODULE_LICENSE("GPL"); + +MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); diff -urN linux-2.6.26/drivers/mmc/host/mx_sdhci.h linux-2.6.26-lab126/drivers/mmc/host/mx_sdhci.h --- linux-2.6.26/drivers/mmc/host/mx_sdhci.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mmc/host/mx_sdhci.h 2010-08-10 04:16:00.000000000 -0400 @@ -0,0 +1,281 @@ +/* + * linux/drivers/mmc/host/mx_sdhci.h - Secure Digital Host + * Controller Interface driver + * + * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved. + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +/* + * Controller registers + */ + +#define SDHCI_DMA_ADDRESS 0x00 + +#define SDHCI_BLOCK_SIZE 0x04 +#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 13) | (blksz & 0x1FFF)) + +#define SDHCI_BLOCK_COUNT 0x04 + +#define SDHCI_ARGUMENT 0x08 + +#define SDHCI_TRANSFER_MODE 0x0C +#define SDHCI_TRNS_DMA 0x00000001 +#define SDHCI_TRNS_BLK_CNT_EN 0x00000002 +#define SDHCI_TRNS_ACMD12 0x00000004 +#define SDHCI_TRNS_READ 0x00000010 +#define SDHCI_TRNS_MULTI 0x00000020 +#define SDHCI_TRNS_DPSEL 0x00200000 +#define SDHCI_TRNS_MASK 0xFFFF0000 + +#define SDHCI_COMMAND 0x0E +#define SDHCI_CMD_RESP_MASK 0x03 +#define SDHCI_CMD_CRC 0x08 +#define SDHCI_CMD_INDEX 0x10 +#define SDHCI_CMD_DATA 0x20 + +#define SDHCI_CMD_RESP_NONE 0x00 +#define SDHCI_CMD_RESP_LONG 0x01 +#define SDHCI_CMD_RESP_SHORT 0x02 +#define SDHCI_CMD_RESP_SHORT_BUSY 0x03 + +#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) << 16 + +#define SDHCI_RESPONSE 0x10 + +#define SDHCI_BUFFER 0x20 + +#define SDHCI_PRESENT_STATE 0x24 +#define SDHCI_CMD_INHIBIT 0x00000001 +#define SDHCI_DATA_INHIBIT 0x00000002 +#define SDHCI_DATA_ACTIVE 0x00000004 +#define SDHCI_DOING_WRITE 0x00000100 +#define SDHCI_DOING_READ 0x00000200 +#define SDHCI_SPACE_AVAILABLE 0x00000400 +#define SDHCI_DATA_AVAILABLE 0x00000800 +#define SDHCI_CARD_PRESENT 0x00010000 +#define SDHCI_WRITE_PROTECT 0x00080000 +#define SDHCI_DAT0_IDLE 0x01000000 +#define SDHCI_CARD_INT_MASK 0x0E000000 +#define SDHCI_CARD_INT_ID 0x0C000000 + +#define SDHCI_HOST_CONTROL 0x28 +#define SDHCI_CTRL_LED 0x00000001 +#define SDHCI_CTRL_4BITBUS 0x00000002 +#define SDHCI_CTRL_8BITBUS 0x00000004 +#define SDHCI_CTRL_HISPD 0x00000004 +#define SDHCI_CTRL_DMA_MASK 0x18 +#define SDHCI_CTRL_SDMA 0x00 +#define SDHCI_CTRL_ADMA1 0x08 +#define SDHCI_CTRL_ADMA32 0x10 +#define SDHCI_CTRL_ADMA64 0x18 +#define SDHCI_CTRL_D3CD 0x00000008 +#define SDHCI_CTRL_ADMA 0x00000100 +/* wake up control */ +#define SDHCI_CTRL_WECINS 0x04000000 + +#define SDHCI_POWER_CONTROL 0x29 +#define SDHCI_POWER_ON 0x01 +#define SDHCI_POWER_180 0x0A +#define SDHCI_POWER_300 0x0C +#define SDHCI_POWER_330 0x0E + +#define SDHCI_BLOCK_GAP_CONTROL 0x2A + +#define SDHCI_WAKE_UP_CONTROL 0x2B + +#define SDHCI_CLOCK_CONTROL 0x2C +#define SDHCI_DIVIDER_SHIFT 8 +#define SDHCI_CLOCK_SD_EN 0x00000008 +#define SDHCI_CLOCK_PER_EN 0x00000004 +#define SDHCI_CLOCK_HLK_EN 0x00000002 +#define SDHCI_CLOCK_IPG_EN 0x00000001 +#define SDHCI_CLOCK_MASK 0x0000FFFF + +#define SDHCI_TIMEOUT_CONTROL 0x2E + +#define SDHCI_SOFTWARE_RESET 0x2F +#define SDHCI_RESET_ALL 0x01 +#define SDHCI_RESET_CMD 0x02 +#define SDHCI_RESET_DATA 0x04 + +#define SDHCI_INT_STATUS 0x30 +#define SDHCI_INT_ENABLE 0x34 +#define SDHCI_SIGNAL_ENABLE 0x38 +#define SDHCI_INT_RESPONSE 0x00000001 +#define SDHCI_INT_DATA_END 0x00000002 +#define SDHCI_INT_DMA_END 0x00000008 +#define SDHCI_INT_SPACE_AVAIL 0x00000010 +#define SDHCI_INT_DATA_AVAIL 0x00000020 +#define SDHCI_INT_CARD_INSERT 0x00000040 +#define SDHCI_INT_CARD_REMOVE 0x00000080 +#define SDHCI_INT_CARD_INT 0x00000100 +#define SDHCI_INT_ERROR 0x00008000 +#define SDHCI_INT_TIMEOUT 0x00010000 +#define SDHCI_INT_CRC 0x00020000 +#define SDHCI_INT_END_BIT 0x00040000 +#define SDHCI_INT_INDEX 0x00080000 +#define SDHCI_INT_DATA_TIMEOUT 0x00100000 +#define SDHCI_INT_DATA_CRC 0x00200000 +#define SDHCI_INT_DATA_END_BIT 0x00400000 +#define SDHCI_INT_BUS_POWER 0x00800000 +#define SDHCI_INT_ACMD12ERR 0x01000000 +#define SDHCI_INT_ADMA_ERROR 0x10000000 + +#define SDHCI_INT_NORMAL_MASK 0x00007FFF +#define SDHCI_INT_ERROR_MASK 0xFFFF8000 + +#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ + SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \ + SDHCI_INT_ACMD12ERR) +#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ + SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ + SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ + SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR) +#define SDHCI_INT_DATA_RE_MASK (SDHCI_INT_DMA_END | \ + SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL) + +#define SDHCI_ACMD12_ERR 0x3C +#define SDHCI_ACMD12_ERR_NE 0x00000001 +#define SDHCI_ACMD12_ERR_TOE 0x00000002 +#define SDHCI_ACMD12_ERR_EBE 0x00000004 +#define SDHCI_ACMD12_ERR_CE 0x00000008 +#define SDHCI_ACMD12_ERR_IE 0x00000010 +#define SDHCI_ACMD12_ERR_CNIBE 0x00000080 + +/* 3E-3F reserved */ + +#define SDHCI_CAPABILITIES 0x40 +#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F +#define SDHCI_TIMEOUT_CLK_SHIFT 0 +#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 +#define SDHCI_CLOCK_BASE_MASK 0x00003F00 +#define SDHCI_CLOCK_BASE_SHIFT 8 +#define SDHCI_MAX_BLOCK_MASK 0x00030000 +#define SDHCI_MAX_BLOCK_SHIFT 16 +#define SDHCI_CAN_DO_ADMA2 0x00080000 +#define SDHCI_CAN_DO_ADMA1 0x00100000 +#define SDHCI_CAN_DO_HISPD 0x00200000 +#define SDHCI_CAN_DO_DMA 0x00400000 +#define SDHCI_CAN_VDD_330 0x01000000 +#define SDHCI_CAN_VDD_300 0x02000000 +#define SDHCI_CAN_VDD_180 0x04000000 +#define SDHCI_CAN_64BIT 0x10000000 + +/* 44-47 reserved for more caps */ +#define SDHCI_WML 0x44 +#define SDHCI_WML_4_WORDS 0x00040004 +#define SDHCI_WML_16_WORDS 0x00100010 +#define SDHCI_WML_64_WORDS 0x00400040 +#define SDHCI_WML_128_WORDS 0x00800080 + +#define SDHCI_MAX_CURRENT 0x48 + +/* 4C-4F reserved for more max current */ + +#define SDHCI_SET_ACMD12_ERROR 0x50 +#define SDHCI_SET_INT_ERROR 0x52 + +#define SDHCI_ADMA_ERROR 0x54 + +/* 55-57 reserved */ + +#define SDHCI_ADMA_ADDRESS 0x58 + +/* 60-FB reserved */ + +/* ADMA Addr Descriptor Attribute Filed */ +enum { + FSL_ADMA_DES_ATTR_VALID = 0x01, + FSL_ADMA_DES_ATTR_END = 0x02, + FSL_ADMA_DES_ATTR_INT = 0x04, + FSL_ADMA_DES_ATTR_SET = 0x10, + FSL_ADMA_DES_ATTR_TRAN = 0x20, + FSL_ADMA_DES_ATTR_LINK = 0x30, +}; + +#define SDHCI_HOST_VERSION 0xFC +#define SDHCI_VENDOR_VER_MASK 0xFF00 +#define SDHCI_VENDOR_VER_SHIFT 8 +#define SDHCI_SPEC_VER_MASK 0x00FF +#define SDHCI_SPEC_VER_SHIFT 0 +#define SDHCI_SPEC_100 0 +#define SDHCI_SPEC_200 1 +#define ESDHC_VENDOR_V22 0x12 + +struct sdhci_chip; + +struct sdhci_host { + struct sdhci_chip *chip; + struct mmc_host *mmc; /* MMC structure */ + +#ifdef CONFIG_LEDS_CLASS + struct led_classdev led; /* LED control */ +#endif + + spinlock_t lock; /* Mutex */ + + int flags; /* Host attributes */ +#define SDHCI_USE_DMA (1<<0) /* Host is DMA capable */ +#define SDHCI_REQ_USE_DMA (1<<1) /* Use DMA for this req. */ +#define SDHCI_USE_EXTERNAL_DMA (1<<2) /* Use the External DMA */ +#define SDHCI_CD_PRESENT (1<<8) /* CD present */ +#define SDHCI_WP_ENABLED (1<<9) /* Write protect */ +#define SDHCI_IN_4BIT_MODE (1<<4) /* bus is in 4-bit mode */ + + unsigned int max_clk; /* Max possible freq (MHz) */ + unsigned int min_clk; /* Min possible freq (MHz) */ + unsigned int timeout_clk; /* Timeout freq (KHz) */ + + unsigned int clock; /* Current clock (MHz) */ + unsigned short power; /* Current voltage */ + struct regulator *regulator_mmc; /*! Regulator */ + + struct mmc_request *mrq; /* Current request */ + struct mmc_command *cmd; /* Current command */ + struct mmc_data *data; /* Current data request */ + unsigned int data_early:1; /* Data finished before cmd */ + + unsigned int id; /* Id for SD/MMC block */ + int mode; /* SD/MMC mode */ + int dma; /* DMA channel number. */ + unsigned int dma_size; /* Number of Bytes in DMA */ + unsigned int dma_len; /* Length of the s-g list */ + unsigned int dma_dir; /* DMA transfer direction */ + + struct scatterlist *cur_sg; /* We're working on this */ + int num_sg; /* Entries left */ + int offset; /* Offset into current sg */ + int remain; /* Bytes left in current */ + + struct resource *res; /* IO map memory */ + int irq; /* Device IRQ */ + int detect_irq; /* Card Detect IRQ number. */ + int sdio_enable; /* sdio interrupt enable number. */ + struct clk *clk; /* Clock id */ + int bar; /* PCI BAR index */ + unsigned long addr; /* Bus address */ + void __iomem *ioaddr; /* Mapped address */ + + struct tasklet_struct card_tasklet; /* Tasklet structures */ + struct tasklet_struct finish_tasklet; + struct work_struct cd_wq; /* card detection work queue */ + /* Platform specific data */ + struct mxc_mmc_platform_data *plat_data; + + struct timer_list timer; /* Timer for timeouts */ +}; + +struct sdhci_chip { + struct platform_device *pdev; + + unsigned long quirks; + + int num_slots; /* Slots on controller */ + struct sdhci_host *hosts[0]; /* Pointers to hosts */ +}; diff -urN linux-2.6.26/drivers/mmc/host/mxc_mmc.c linux-2.6.26-lab126/drivers/mmc/host/mxc_mmc.c --- linux-2.6.26/drivers/mmc/host/mxc_mmc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mmc/host/mxc_mmc.c 2010-08-10 04:16:00.000000000 -0400 @@ -0,0 +1,1532 @@ +/* + * linux/drivers/mmc/host/mxc_mmc.c - Freescale MXC/i.MX MMC driver + * + * based on imxmmc.c + * Copyright (C) 2004 Sascha Hauer, Pengutronix + * + * derived from pxamci.c by Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_mmc.c + * + * @brief Driver for the Freescale Semiconductor MXC SDHC modules. + * + * This driver code is based on imxmmc.c, by Sascha Hauer, + * Pengutronix . This driver supports both Secure Digital + * Host Controller modules (SDHC1 and SDHC2) of MXC. SDHC is also referred as + * MMC/SD controller. This code is not tested for SD cards. + * + * @ingroup MMC_SD + */ + +/* + * Include Files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "mxc_mmc.h" + +#define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE)) + +/* + * This define is used to test the driver without using DMA + */ +#define MXC_MMC_DMA_ENABLE + +/*! + * Maxumum length of s/g list, only length of 1 is currently supported + */ +#define NR_SG 1 + +#ifdef CONFIG_MMC_DEBUG +static void dump_cmd(struct mmc_command *cmd) +{ + printk(KERN_INFO "%s: CMD: opcode: %d ", DRIVER_NAME, cmd->opcode); + printk(KERN_INFO "arg: 0x%08x ", cmd->arg); + printk(KERN_INFO "flags: 0x%08x\n", cmd->flags); +} + +static void dump_status(const char *func, int sts) +{ + unsigned int bitset; + printk(KERN_INFO "%s:status: ", func); + while (sts) { + /* Find the next bit set */ + bitset = sts & ~(sts - 1); + switch (bitset) { + case STATUS_CARD_INSERTION: + printk(KERN_INFO "CARD_INSERTION|"); + break; + case STATUS_CARD_REMOVAL: + printk(KERN_INFO "CARD_REMOVAL |"); + break; + case STATUS_YBUF_EMPTY: + printk(KERN_INFO "YBUF_EMPTY |"); + break; + case STATUS_XBUF_EMPTY: + printk(KERN_INFO "XBUF_EMPTY |"); + break; + case STATUS_YBUF_FULL: + printk(KERN_INFO "YBUF_FULL |"); + break; + case STATUS_XBUF_FULL: + printk(KERN_INFO "XBUF_FULL |"); + break; + case STATUS_BUF_UND_RUN: + printk(KERN_INFO "BUF_UND_RUN |"); + break; + case STATUS_BUF_OVFL: + printk(KERN_INFO "BUF_OVFL |"); + break; + case STATUS_READ_OP_DONE: + printk(KERN_INFO "READ_OP_DONE |"); + break; + case STATUS_WR_CRC_ERROR_CODE_MASK: + printk(KERN_INFO "WR_CRC_ERROR_CODE |"); + break; + case STATUS_READ_CRC_ERR: + printk(KERN_INFO "READ_CRC_ERR |"); + break; + case STATUS_WRITE_CRC_ERR: + printk(KERN_INFO "WRITE_CRC_ERR |"); + break; + case STATUS_SDIO_INT_ACTIVE: + printk(KERN_INFO "SDIO_INT_ACTIVE |"); + break; + case STATUS_END_CMD_RESP: + printk(KERN_INFO "END_CMD_RESP |"); + break; + case STATUS_WRITE_OP_DONE: + printk(KERN_INFO "WRITE_OP_DONE |"); + break; + case STATUS_CARD_BUS_CLK_RUN: + printk(KERN_INFO "CARD_BUS_CLK_RUN |"); + break; + case STATUS_BUF_READ_RDY: + printk(KERN_INFO "BUF_READ_RDY |"); + break; + case STATUS_BUF_WRITE_RDY: + printk(KERN_INFO "BUF_WRITE_RDY |"); + break; + case STATUS_RESP_CRC_ERR: + printk(KERN_INFO "RESP_CRC_ERR |"); + break; + case STATUS_TIME_OUT_RESP: + printk(KERN_INFO "TIME_OUT_RESP |"); + break; + case STATUS_TIME_OUT_READ: + printk(KERN_INFO "TIME_OUT_READ |"); + break; + default: + printk(KERN_INFO "Invalid Status Register value0x%x\n", + bitset); + break; + } + sts &= ~bitset; + } + printk(KERN_INFO "\n"); +} +#endif + +/*! + * This structure is a way for the low level driver to define their own + * \b mmc_host structure. This structure includes the core \b mmc_host + * structure that is provided by Linux MMC/SD Bus protocol driver as an + * element and has other elements that are specifically required by this + * low-level driver. + */ +struct mxcmci_host { + /*! + * The mmc structure holds all the information about the device + * structure, current SDHC io bus settings, the current OCR setting, + * devices attached to this host, and so on. + */ + struct mmc_host *mmc; + + /*! + * This variable is used for locking the host data structure from + * multiple access. + */ + spinlock_t lock; + + /*! + * Resource structure, which will maintain base addresses and IRQs. + */ + struct resource *res; + + /*! + * Base address of SDHC, used in readl and writel. + */ + void *base; + + /*! + * SDHC IRQ number. + */ + int irq; + + /*! + * Card Detect IRQ number. + */ + int detect_irq; + + /*! + * Clock id to hold ipg_perclk. + */ + struct clk *clk; + /*! + * MMC mode. + */ + int mode; + + /*! + * DMA channel number. + */ + int dma; + + /*! + * Pointer to hold MMC/SD request. + */ + struct mmc_request *req; + + /*! + * Pointer to hold MMC/SD command. + */ + struct mmc_command *cmd; + + /*! + * Pointer to hold MMC/SD data. + */ + struct mmc_data *data; + + /*! + * Holds the number of bytes to transfer using DMA. + */ + unsigned int dma_size; + + /*! + * Value to store in Command and Data Control Register + * - currently unused + */ + unsigned int cmdat; + + /*! + * Regulator + */ + struct regulator *regulator_mmc; + + /*! + * Current vdd settting + */ + int current_vdd; + + /*! + * Power mode - currently unused + */ + unsigned int power_mode; + + /*! + * DMA address for scatter-gather transfers + */ + dma_addr_t sg_dma; + + /*! + * Length of the scatter-gather list + */ + unsigned int dma_len; + + /*! + * Holds the direction of data transfer. + */ + unsigned int dma_dir; + + /*! + * Id for MMC block. + */ + unsigned int id; + + /*! + * Note whether this driver has been suspended. + */ + unsigned int mxc_mmc_suspend_flag; + + /*! + * sdio_irq enable/disable ref count + */ + int sdio_irq_cnt; + + /*! + * Platform specific data + */ + struct mxc_mmc_platform_data *plat_data; +}; + +extern void gpio_sdhc_active(int module); +extern void gpio_sdhc_inactive(int module); + +#ifdef MXC_MMC_DMA_ENABLE +static void mxcmci_dma_irq(void *devid, int error, unsigned int cnt); +#endif +static int mxcmci_data_done(struct mxcmci_host *host, unsigned int stat); + +/* Wait count to start the clock */ +#define CMD_WAIT_CNT 100 + +#define MAX_HOST 10 +static struct mmc_host *hosts[MAX_HOST]; + +void mxc_mmc_force_detect(int id) +{ + if (id < MAX_HOST) + mmc_detect_change(hosts[id], msecs_to_jiffies(100)); +} + +EXPORT_SYMBOL(mxc_mmc_force_detect); + +/*! + This function sets the SDHC register to stop the clock and waits for the + * clock stop indication. + */ +static void mxcmci_stop_clock(struct mxcmci_host *host, bool wait) +{ + int wait_cnt = 0; + while (1) { + __raw_writel(STR_STP_CLK_IPG_CLK_GATE_DIS | + STR_STP_CLK_IPG_PERCLK_GATE_DIS | + STR_STP_CLK_STOP_CLK, + host->base + MMC_STR_STP_CLK); + + if (!wait) + break; + + wait_cnt = CMD_WAIT_CNT; + while (wait_cnt--) { + if (!(__raw_readl(host->base + MMC_STATUS) & + STATUS_CARD_BUS_CLK_RUN)) + break; + } + + if (!(__raw_readl(host->base + MMC_STATUS) & + STATUS_CARD_BUS_CLK_RUN)) + break; + } +} + +/*! + * This function sets the SDHC register to start the clock and waits for the + * clock start indication. When the clock starts SDHC module starts processing + * the command in CMD Register with arguments in ARG Register. + * + * @param host Pointer to MMC/SD host structure + * @param wait Boolean value to indicate whether to wait for the clock to start or come out instantly + */ +static void mxcmci_start_clock(struct mxcmci_host *host, bool wait) +{ + int wait_cnt; + +#ifdef CONFIG_MMC_DEBUG + dump_status(__FUNCTION__, __raw_readl(host->base + MMC_STATUS)); +#endif + + while (1) { + __raw_writel(STR_STP_CLK_IPG_CLK_GATE_DIS | + STR_STP_CLK_IPG_PERCLK_GATE_DIS | + STR_STP_CLK_START_CLK, + host->base + MMC_STR_STP_CLK); + if (!wait) + break; + + wait_cnt = CMD_WAIT_CNT; + while (wait_cnt--) { + if (__raw_readl(host->base + MMC_STATUS) & + STATUS_CARD_BUS_CLK_RUN) { + break; + } + } + + if (__raw_readl(host->base + MMC_STATUS) & + STATUS_CARD_BUS_CLK_RUN) { + break; + } + } +#ifdef CONFIG_MMC_DEBUG + dump_status(__FUNCTION__, __raw_readl(host->base + MMC_STATUS)); +#endif + pr_debug("%s:CLK_RATE: 0x%08x\n", DRIVER_NAME, + __raw_readl(host->base + MMC_CLK_RATE)); +} + +/*! + * This function resets the SDHC host. + * + * @param host Pointer to MMC/SD host structure + */ +static void mxcmci_softreset(struct mxcmci_host *host) +{ + /* reset sequence */ + __raw_writel(0x8, host->base + MMC_STR_STP_CLK); + __raw_writel(0x9, host->base + MMC_STR_STP_CLK); + __raw_writel(0x1, host->base + MMC_STR_STP_CLK); + __raw_writel(0x1, host->base + MMC_STR_STP_CLK); + __raw_writel(0x1, host->base + MMC_STR_STP_CLK); + __raw_writel(0x1, host->base + MMC_STR_STP_CLK); + __raw_writel(0x1, host->base + MMC_STR_STP_CLK); + __raw_writel(0x1, host->base + MMC_STR_STP_CLK); + __raw_writel(0x1, host->base + MMC_STR_STP_CLK); + __raw_writel(0x1, host->base + MMC_STR_STP_CLK); + __raw_writel(0x3f, host->base + MMC_CLK_RATE); + + __raw_writel(0xff, host->base + MMC_RES_TO); + __raw_writel(512, host->base + MMC_BLK_LEN); + __raw_writel(1, host->base + MMC_NOB); +} + +/*! + * This function is called to setup SDHC register for data transfer. + * The function allocates DMA buffers, configures the DMA channel. + * Start the DMA channel to transfer data. When DMA is not enabled this + * function set ups only Number of Block and Block Length registers. + * + * @param host Pointer to MMC/SD host structure + * @param data Pointer to MMC/SD data structure + */ +static void mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) +{ + unsigned int nob = data->blocks; + + if (data->flags & MMC_DATA_STREAM) { + nob = 0xffff; + } + + host->data = data; + + __raw_writel(nob, host->base + MMC_NOB); + __raw_writel(data->blksz, host->base + MMC_BLK_LEN); + + host->dma_size = data->blocks * data->blksz; + pr_debug("%s:Request bytes to transfer:%d\n", DRIVER_NAME, + host->dma_size); + +#ifdef MXC_MMC_DMA_ENABLE + if (host->dma_size <= (16 << host->mmc->ios.bus_width)) { + return; + } + + if (data->blksz & 0x3) { + printk(KERN_ERR + "mxc_mci: block size not multiple of 4 bytes\n"); + } + + if (data->flags & MMC_DATA_READ) { + host->dma_dir = DMA_FROM_DEVICE; + } else { + host->dma_dir = DMA_TO_DEVICE; + } + host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, + host->dma_dir); + + if (data->flags & MMC_DATA_READ) { + mxc_dma_sg_config(host->dma, data->sg, data->sg_len, + host->dma_size, MXC_DMA_MODE_READ); + } else { + mxc_dma_sg_config(host->dma, data->sg, data->sg_len, + host->dma_size, MXC_DMA_MODE_WRITE); + } +#endif +} + +/*! + * This function is called by \b mxcmci_request() function to setup the SDHC + * register to issue command. This function disables the card insertion and + * removal detection interrupt. + * + * @param host Pointer to MMC/SD host structure + * @param cmd Pointer to MMC/SD command structure + * @param cmdat Value to store in Command and Data Control Register + */ +static void mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd, + unsigned int cmdat) +{ + WARN_ON(host->cmd != NULL); + host->cmd = cmd; + + switch (RSP_TYPE(mmc_resp_type(cmd))) { + case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6 */ + cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R1; + break; + case RSP_TYPE(MMC_RSP_R3): + cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R3; + break; + case RSP_TYPE(MMC_RSP_R2): + cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R2; + break; + default: + /* No Response required */ + break; + } + + if (cmd->opcode == MMC_GO_IDLE_STATE) { + cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */ + } + + if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) { + cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; + } + + __raw_writel(cmd->opcode, host->base + MMC_CMD); + __raw_writel(cmd->arg, host->base + MMC_ARG); + + __raw_writel(cmdat, host->base + MMC_CMD_DAT_CONT); + + if (!(cmdat & CMD_DAT_CONT_DATA_ENABLE) || (cmdat & CMD_DAT_CONT_WRITE)) { + mxcmci_start_clock(host, true); + } else { + __raw_writel(STR_STP_CLK_IPG_CLK_GATE_DIS | + STR_STP_CLK_IPG_PERCLK_GATE_DIS, + host->base + MMC_STR_STP_CLK); + } +} + +/*! + * This function is called to complete the command request. + * This function enables insertion or removal interrupt. + * + * @param host Pointer to MMC/SD host structure + * @param req Pointer to MMC/SD command request structure + */ +static void mxcmci_finish_request(struct mxcmci_host *host, + struct mmc_request *req) +{ + + host->req = NULL; + host->cmd = NULL; + host->data = NULL; + + if (!(req->cmd->flags & MMC_KEEP_CLK_RUN)) { + mxcmci_stop_clock(host, true); + } + mmc_request_done(host->mmc, req); +} + +/*! + * This function is called when the requested command is completed. + * This function reads the response from the card and data if the command is for + * data transfer. This function checks for CRC error in response FIFO or + * data FIFO. + * + * @param host Pointer to MMC/SD host structure + * @param stat Content of SDHC Status Register + * + * @return This function returns 0 if there is no pending command, otherwise 1 + * always. + */ +static int mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat) +{ + struct mmc_command *cmd = host->cmd; + struct mmc_data *data = host->data; + int i; + u32 a, b, c; + u32 temp_data; + unsigned int status; + unsigned long *buf; + u8 *buf8; + int no_of_bytes; + int no_of_words; + + if (!cmd) { + /* There is no command for completion */ + return 0; + } + + /* As this function finishes the command, initialize cmd to NULL */ + host->cmd = NULL; + + /* check for Time out errors */ + if (stat & STATUS_TIME_OUT_RESP) { + __raw_writel(STATUS_TIME_OUT_RESP, host->base + MMC_STATUS); + pr_debug("%s: CMD TIMEOUT\n", DRIVER_NAME); + cmd->error = -ETIMEDOUT; + /* + * Reinitialized the controller to clear the unknown + * error state. + */ + mxcmci_softreset(host); + __raw_writel(READ_TO_VALUE, host->base + MMC_READ_TO); + __raw_writel(INT_CNTR_END_CMD_RES, host->base + MMC_INT_CNTR); + } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) { + __raw_writel(STATUS_RESP_CRC_ERR, host->base + MMC_STATUS); + printk(KERN_ERR "%s: cmd crc error\n", DRIVER_NAME); + cmd->error = -EILSEQ; + /* + * Reinitialized the controller to clear the unknown + * error state. + */ + mxcmci_softreset(host); + __raw_writel(READ_TO_VALUE, host->base + MMC_READ_TO); + __raw_writel(INT_CNTR_END_CMD_RES, host->base + MMC_INT_CNTR); + } + + /* Read response from the card */ + switch (RSP_TYPE(mmc_resp_type(cmd))) { + case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6 */ + a = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff; + b = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff; + c = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff; + cmd->resp[0] = a << 24 | b << 8 | c >> 8; + break; + case RSP_TYPE(MMC_RSP_R3): /* r3, r4 */ + a = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff; + b = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff; + c = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff; + cmd->resp[0] = a << 24 | b << 8 | c >> 8; + break; + case RSP_TYPE(MMC_RSP_R2): + for (i = 0; i < 4; i++) { + a = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff; + b = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff; + cmd->resp[i] = a << 16 | b; + } + break; + default: + break; + } + + pr_debug("%s: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", DRIVER_NAME, + cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + + if (!host->data || cmd->error) { + /* complete the command */ + mxcmci_finish_request(host, host->req); + return 1; + } + + /* The command has a data transfer */ +#ifdef MXC_MMC_DMA_ENABLE + /* Use DMA if transfer size is greater than fifo size */ + if (host->dma_size > (16 << host->mmc->ios.bus_width)) { + mxc_dma_enable(host->dma); + return 1; + } +#endif + /* Use PIO tranfer of data */ + buf = (unsigned long *)sg_virt(data->sg); + buf8 = (u8 *) buf; + + /* calculate the number of bytes requested for transfer */ + no_of_bytes = data->blocks * data->blksz; + no_of_words = (no_of_bytes + 3) / 4; + pr_debug("no_of_words=%d\n", no_of_words); + + if (data->flags & MMC_DATA_READ) { + for (i = 0; i < no_of_words; i++) { + /* wait for buffers to be ready for read */ + while (!(__raw_readl(host->base + MMC_STATUS) & + (STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE))) ; + + pr_debug("status is 0x%x\n", + __raw_readl(host->base + MMC_STATUS)); + /* read 32 bit data */ + temp_data = __raw_readl(host->base + MMC_BUFFER_ACCESS); + if (SD_APP_SEND_SCR == cmd->opcode) { + pr_debug("CMD51 read out 0x%x\n", temp_data); + if (temp_data == 0xFFFFFFFF) + temp_data = 0; + } + if (no_of_bytes >= 4) { + *buf++ = temp_data; + no_of_bytes -= 4; + } else { + do { + *buf8++ = temp_data; + temp_data = temp_data >> 8; + } while (--no_of_bytes); + } + } + + /* wait for read operation completion bit */ + while (!(__raw_readl(host->base + MMC_STATUS) & + STATUS_READ_OP_DONE)) ; + + /* check for time out and CRC errors */ + status = __raw_readl(host->base + MMC_STATUS); + if (status & STATUS_TIME_OUT_READ) { + pr_debug("%s: Read time out occurred\n", DRIVER_NAME); + data->error = -ETIMEDOUT; + __raw_writel(STATUS_TIME_OUT_READ, + host->base + MMC_STATUS); + /* + * Reinitialized the controller to clear the unknown + * error state. + */ + mxcmci_softreset(host); + __raw_writel(READ_TO_VALUE, host->base + MMC_READ_TO); + __raw_writel(INT_CNTR_END_CMD_RES, + host->base + MMC_INT_CNTR); + } else if (status & STATUS_READ_CRC_ERR) { + pr_debug("%s: Read CRC error occurred\n", DRIVER_NAME); + if (SD_APP_SEND_SCR != cmd->opcode) + data->error = -EILSEQ; + __raw_writel(STATUS_READ_CRC_ERR, + host->base + MMC_STATUS); + /* + * Reinitialized the controller to clear the unknown + * error state. + */ + mxcmci_softreset(host); + __raw_writel(READ_TO_VALUE, host->base + MMC_READ_TO); + __raw_writel(INT_CNTR_END_CMD_RES, + host->base + MMC_INT_CNTR); + } + __raw_writel(STATUS_READ_OP_DONE, host->base + MMC_STATUS); + + pr_debug("%s: Read %u words\n", DRIVER_NAME, i); + } else { + for (i = 0; i < no_of_words; i++) { + + /* wait for buffers to be ready for write */ + while (!(__raw_readl(host->base + MMC_STATUS) & + STATUS_BUF_WRITE_RDY)) ; + + /* write 32 bit data */ + __raw_writel(*buf++, host->base + MMC_BUFFER_ACCESS); + if (__raw_readl(host->base + MMC_STATUS) & + STATUS_WRITE_OP_DONE) { + break; + } + } + + /* wait for write operation completion bit */ + while (!(__raw_readl(host->base + MMC_STATUS) & + STATUS_WRITE_OP_DONE)) ; + + /* check for CRC errors */ + status = __raw_readl(host->base + MMC_STATUS); + if (status & STATUS_WRITE_CRC_ERR) { + pr_debug("%s: Write CRC error occurred\n", DRIVER_NAME); + data->error = -EILSEQ; + __raw_writel(STATUS_WRITE_CRC_ERR, + host->base + MMC_STATUS); + } + __raw_writel(STATUS_WRITE_OP_DONE, host->base + MMC_STATUS); + pr_debug("%s: Written %u words\n", DRIVER_NAME, i); + } + + /* complete the data transfer request */ + mxcmci_data_done(host, status); + + return 1; +} + +/*! + * This function is called when the data transfer is completed either by DMA + * or by core. This function is called to clean up the DMA buffer and to send + * STOP transmission command for commands to transfer data. This function + * completes request issued by the MMC/SD core driver. + * + * @param host pointer to MMC/SD host structure. + * @param stat content of SDHC Status Register + * + * @return This function returns 0 if no data transfer otherwise return 1 + * always. + */ +static int mxcmci_data_done(struct mxcmci_host *host, unsigned int stat) +{ + struct mmc_data *data = host->data; + + if (!data) { + return 0; + } +#ifdef MXC_MMC_DMA_ENABLE + if (host->dma_size > (16 << host->mmc->ios.bus_width)) { + dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len, + host->dma_dir); + } +#endif + if (__raw_readl(host->base + MMC_STATUS) & STATUS_ERR_MASK) { + pr_debug("%s: request failed. status: 0x%08x\n", + DRIVER_NAME, __raw_readl(host->base + MMC_STATUS)); + } + + host->data = NULL; + data->bytes_xfered = host->dma_size; + + if (host->req->stop && !(data->error)) { + mxcmci_start_cmd(host, host->req->stop, 0); + } else { + mxcmci_finish_request(host, host->req); + } + + return 1; +} + +/*! + * GPIO interrupt service routine registered to handle the SDHC interrupts. + * This interrupt routine handles card insertion and card removal interrupts. + * + * @param irq the interrupt number + * @param devid driver private data + * @param regs holds a snapshot of the processor's context before the + * processor entered the interrupt code + * + * @return The function returns \b IRQ_RETVAL(1) + */ +static irqreturn_t mxcmci_gpio_irq(int irq, void *devid) +{ + struct mxcmci_host *host = devid; + int card_gpio_status = host->plat_data->status(host->mmc->parent); + + pr_debug("%s: MMC%d status=%d %s\n", DRIVER_NAME, host->id, + card_gpio_status, card_gpio_status ? "removed" : "inserted"); + + if (card_gpio_status == host->plat_data->card_inserted_state) { + /* + * Reinitialized the controller to clear the unknown + * error state when a card is inserted. + */ + mxcmci_softreset(host); + __raw_writel(READ_TO_VALUE, host->base + MMC_READ_TO); + __raw_writel(INT_CNTR_END_CMD_RES, host->base + MMC_INT_CNTR); + + mmc_detect_change(host->mmc, msecs_to_jiffies(100)); + } else { + mxcmci_cmd_done(host, STATUS_TIME_OUT_RESP); + mmc_detect_change(host->mmc, msecs_to_jiffies(50)); + } + + do { + card_gpio_status = host->plat_data->status(host->mmc->parent); + if (card_gpio_status) { + set_irq_type(host->detect_irq, IRQT_FALLING); + } else { + set_irq_type(host->detect_irq, IRQT_RISING); + } + } while (card_gpio_status != + host->plat_data->status(host->mmc->parent)); + + return IRQ_HANDLED; +} + +/*! + * Interrupt service routine registered to handle the SDHC interrupts. + * This interrupt routine handles end of command, card insertion and + * card removal interrupts. If the interrupt is card insertion or removal then + * inform the MMC/SD core driver to detect the change in physical connections. + * If the command is END_CMD_RESP read the Response FIFO. If DMA is not enabled + * and data transfer is associated with the command then read or write the data + * from or to the BUFFER_ACCESS FIFO. + * + * @param irq the interrupt number + * @param devid driver private data + * @param regs holds a snapshot of the processor's context before the + * processor entered the interrupt code + * + * @return The function returns \b IRQ_RETVAL(1) if interrupt was handled, + * returns \b IRQ_RETVAL(0) if the interrupt was not handled. + */ +static irqreturn_t mxcmci_irq(int irq, void *devid) +{ + struct mxcmci_host *host = devid; + struct mmc_data *data = host->data; + unsigned int status = 0; + u32 intctrl; + + if (host->mxc_mmc_suspend_flag == 1) { + clk_enable(host->clk); + } + + status = __raw_readl(host->base + MMC_STATUS); + pr_debug("MXC MMC IRQ status is 0x%x.\n", status); +#ifdef CONFIG_MMC_DEBUG + dump_status(__FUNCTION__, status); +#endif + if (status & STATUS_END_CMD_RESP) { + __raw_writel(STATUS_END_CMD_RESP, host->base + MMC_STATUS); + mxcmci_cmd_done(host, status); + } +#ifdef MXC_MMC_DMA_ENABLE + /* + * If read length < fifo length, STATUS_END_CMD_RESP and + * STATUS_READ_OP_DONE may come together. In this case, it's using PIO + * mode, we ignore STATUS_READ_OP_DONE. + */ + if ((status & (STATUS_WRITE_OP_DONE | STATUS_READ_OP_DONE)) && + !(status & STATUS_END_CMD_RESP)) { + pr_debug(KERN_INFO "MXC MMC IO OP DONE INT.\n"); + intctrl = __raw_readl(host->base + MMC_INT_CNTR); + __raw_writel((~(INT_CNTR_WRITE_OP_DONE | INT_CNTR_READ_OP_DONE) + & intctrl), host->base + MMC_INT_CNTR); + + pr_debug("%s:READ/WRITE OPERATION DONE\n", DRIVER_NAME); + /* check for time out and CRC errors */ + status = __raw_readl(host->base + MMC_STATUS); + if (status & STATUS_READ_OP_DONE) { + if (status & STATUS_TIME_OUT_READ) { + pr_debug("%s: Read time out occurred\n", + DRIVER_NAME); + data->error = -ETIMEDOUT; + __raw_writel(STATUS_TIME_OUT_READ, + host->base + MMC_STATUS); + } else if (status & STATUS_READ_CRC_ERR) { + pr_debug("%s: Read CRC error occurred\n", + DRIVER_NAME); + data->error = -EILSEQ; + __raw_writel(STATUS_READ_CRC_ERR, + host->base + MMC_STATUS); + } + __raw_writel(STATUS_READ_OP_DONE, + host->base + MMC_STATUS); + } + + /* check for CRC errors */ + if (status & STATUS_WRITE_OP_DONE) { + if (status & STATUS_WRITE_CRC_ERR) { + pr_debug("%s: Write CRC error occurred\n", + DRIVER_NAME); + data->error = -EILSEQ; + __raw_writel(STATUS_WRITE_CRC_ERR, + host->base + MMC_STATUS); + } + __raw_writel(STATUS_WRITE_OP_DONE, + host->base + MMC_STATUS); + } + + mxcmci_data_done(host, status); + } +#endif + status = __raw_readl(host->base + MMC_STATUS); + intctrl = __raw_readl(host->base + MMC_INT_CNTR); + if ((status & STATUS_SDIO_INT_ACTIVE) + && (intctrl & INT_CNTR_SDIO_IRQ_EN)) { + __raw_writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_STATUS); + + /*Here we do not handle the sdio interrupt to client driver + if the host is in suspend state */ + if (host->mxc_mmc_suspend_flag == 0) { + mmc_signal_sdio_irq(host->mmc); + } + } + return IRQ_HANDLED; +} + +/*! + * This function is called by MMC/SD Bus Protocol driver to issue a MMC + * and SD commands to the SDHC. + * + * @param mmc Pointer to MMC/SD host structure + * @param req Pointer to MMC/SD command request structure + */ +static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req) +{ + struct mxcmci_host *host = mmc_priv(mmc); + /* Holds the value of Command and Data Control Register */ + unsigned long cmdat; + + WARN_ON(host->req != NULL); + + host->req = req; +#ifdef CONFIG_MMC_DEBUG + dump_cmd(req->cmd); + dump_status(__FUNCTION__, __raw_readl(host->base + MMC_STATUS)); +#endif + + cmdat = 0; + if (req->data) { + mxcmci_setup_data(host, req->data); + + cmdat |= CMD_DAT_CONT_DATA_ENABLE; + + if (req->data->flags & MMC_DATA_WRITE) { + cmdat |= CMD_DAT_CONT_WRITE; + } + if (req->data->flags & MMC_DATA_STREAM) { + printk(KERN_ERR + "MXC MMC does not support stream mode\n"); + } + } + mxcmci_start_cmd(host, req->cmd, cmdat); +} + +/*! + * This function is called by MMC/SD Bus Protocol driver to change the clock + * speed of MMC or SD card + * + * @param mmc Pointer to MMC/SD host structure + * @param ios Pointer to MMC/SD I/O type structure + */ +static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct mxcmci_host *host = mmc_priv(mmc); + /*This variable holds the value of clock prescaler */ + int prescaler; + int clk_rate = clk_get_rate(host->clk); + int voltage = 0; +#ifdef MXC_MMC_DMA_ENABLE + mxc_dma_device_t dev_id = 0; +#endif + + pr_debug("%s: clock %u, bus %lu, power %u, vdd %u\n", DRIVER_NAME, + ios->clock, 1UL << ios->bus_width, ios->power_mode, ios->vdd); + + host->dma_dir = DMA_NONE; + +#ifdef MXC_MMC_DMA_ENABLE + if (mmc->ios.bus_width != host->mode) { + mxc_dma_free(host->dma); + if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) { + if (host->id == 0) { + dev_id = MXC_DMA_MMC1_WIDTH_4; + } else { + dev_id = MXC_DMA_MMC2_WIDTH_4; + } + } else { + if (host->id == 0) { + dev_id = MXC_DMA_MMC1_WIDTH_1; + } else { + dev_id = MXC_DMA_MMC2_WIDTH_1; + } + } + host->dma = mxc_dma_request(dev_id, "MXC MMC"); + if (host->dma < 0) { + pr_debug("Cannot allocate MMC DMA channel\n"); + } + host->mode = mmc->ios.bus_width; + mxc_dma_callback_set(host->dma, mxcmci_dma_irq, (void *)host); + } +#endif + + if ((ios->vdd != host->current_vdd) && host->regulator_mmc) { + if (ios->vdd == 7) + voltage = 1800000; + else if (ios->vdd >= 8) + voltage = 2000000 + (ios->vdd - 8) * 100000; + regulator_set_voltage(host->regulator_mmc, voltage); + } + host->current_vdd = ios->vdd; + + if (ios->power_mode != host->power_mode && host->regulator_mmc) { + if (ios->power_mode == MMC_POWER_UP) { + if (regulator_enable(host->regulator_mmc) == 0) { + pr_debug("mmc power on\n"); + msleep(1); + } + } else if (ios->power_mode == MMC_POWER_OFF) { + regulator_disable(host->regulator_mmc); + pr_debug("mmc power off\n"); + } + } + host->power_mode = ios->power_mode; + + /* + * Vary divider first, then prescaler. + **/ + if (ios->clock) { + unsigned int clk_dev = 0; + + /* + * when prescaler = 16, CLK_20M = CLK_DIV / 2 + */ + if (ios->clock == mmc->f_min) + prescaler = 16; + else + prescaler = 0; + + /* clk_dev =1, CLK_DIV = ipg_perclk/2 */ + while (prescaler <= 0x800) { + for (clk_dev = 1; clk_dev <= 0xF; clk_dev++) { + int x; + if (prescaler != 0) { + x = (clk_rate / (clk_dev + 1)) / + (prescaler * 2); + } else { + x = clk_rate / (clk_dev + 1); + } + + pr_debug("x=%d, clock=%d %d\n", x, ios->clock, + clk_dev); + if (x <= ios->clock) { + break; + } + } + if (clk_dev < 0x10) { + break; + } + if (prescaler == 0) + prescaler = 1; + else + prescaler <<= 1; + } + + pr_debug("prescaler = 0x%x, divider = 0x%x\n", prescaler, + clk_dev); + mxcmci_stop_clock(host, true); + __raw_writel((prescaler << 4) | clk_dev, + host->base + MMC_CLK_RATE); + mxcmci_start_clock(host, false); + } else { + mxcmci_stop_clock(host, true); + } +} + +static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable) +{ + struct mxcmci_host *host = mmc_priv(mmc); + u32 intctrl; + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + + if (enable) + host->sdio_irq_cnt++; + else + host->sdio_irq_cnt--; + + if (host->sdio_irq_cnt == 1 || host->sdio_irq_cnt == 0) { + intctrl = __raw_readl(host->base + MMC_INT_CNTR); + intctrl &= ~INT_CNTR_SDIO_IRQ_EN; + if (host->sdio_irq_cnt) + intctrl |= INT_CNTR_SDIO_IRQ_EN; + __raw_writel(intctrl, host->base + MMC_INT_CNTR); + } + + spin_unlock_irqrestore(&host->lock, flags); +} + +static int mxcmci_get_ro(struct mmc_host *mmc) +{ + struct mxcmci_host *host = mmc_priv(mmc); + + if (host->plat_data->wp_status) + return host->plat_data->wp_status(mmc->parent); + else + return 0; +} + +/*! + * MMC/SD host operations structure. + * These functions are registered with MMC/SD Bus protocol driver. + */ +static struct mmc_host_ops mxcmci_ops = { + .request = mxcmci_request, + .set_ios = mxcmci_set_ios, + .get_ro = mxcmci_get_ro, + .enable_sdio_irq = mxcmci_enable_sdio_irq, +}; + +#ifdef MXC_MMC_DMA_ENABLE +/*! + * This function is called by DMA Interrupt Service Routine to indicate + * requested DMA transfer is completed. + * + * @param devid pointer to device specific structure + * @param error any DMA error + * @param cnt amount of data that was transferred + */ +static void mxcmci_dma_irq(void *devid, int error, unsigned int cnt) +{ + struct mxcmci_host *host = devid; + u32 status; + ulong nob, blk_size, i, blk_len; + + mxc_dma_disable(host->dma); + + if (error) { + pr_debug("Error in DMA transfer\n"); + status = __raw_readl(host->base + MMC_STATUS); +#ifdef CONFIG_MMC_DEBUG + dump_status(__FUNCTION__, status); +#endif + mxcmci_data_done(host, status); + return; + } + pr_debug("%s: Transfered bytes:%d\n", DRIVER_NAME, cnt); + nob = __raw_readl(host->base + MMC_REM_NOB); + blk_size = __raw_readl(host->base + MMC_REM_BLK_SIZE); + blk_len = __raw_readl(host->base + MMC_BLK_LEN); + pr_debug("%s: REM_NOB:%lu REM_BLK_SIZE:%lu\n", DRIVER_NAME, nob, + blk_size); + i = 0; + + /* Enable the WRITE OP Done INT */ + status = __raw_readl(host->base + MMC_INT_CNTR); + __raw_writel((INT_CNTR_READ_OP_DONE | INT_CNTR_WRITE_OP_DONE | status), + host->base + MMC_INT_CNTR); +} +#endif + +/*! + * This function is called during the driver binding process. Based on the SDHC + * module that is being probed this function adds the appropriate SDHC module + * structure in the core driver. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions. + * + * @return The function returns 0 on successful registration and initialization + * of SDHC module. Otherwise returns specific error code. + */ +static int mxcmci_probe(struct platform_device *pdev) +{ + struct mxc_mmc_platform_data *mmc_plat = pdev->dev.platform_data; + struct mmc_host *mmc; + struct mxcmci_host *host = NULL; + int card_gpio_status; + int ret = -ENODEV; + + if (!mmc_plat) { + return -EINVAL; + } + + mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev); + if (!mmc) { + return -ENOMEM; + } + host = mmc_priv(mmc); + platform_set_drvdata(pdev, mmc); + + mmc->ops = &mxcmci_ops; + mmc->ocr_avail = mmc_plat->ocr_mask; + + /* Hack to work with LP1070 */ + if (mmc->ocr_avail && ~(MMC_VDD_31_32 - 1) == 0) + mmc->ocr_avail |= MMC_VDD_31_32; + + mmc->max_phys_segs = NR_SG; + mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; + + mmc->f_min = mmc_plat->min_clk; + mmc->f_max = mmc_plat->max_clk; + mmc->max_req_size = 32 * 1024; + mmc->max_seg_size = mmc->max_req_size; + mmc->max_blk_count = 65536; + + spin_lock_init(&host->lock); + host->mmc = mmc; + host->dma = -1; + host->dma_dir = DMA_NONE; + host->id = pdev->id; + host->mxc_mmc_suspend_flag = 0; + host->mode = -1; + host->plat_data = mmc_plat; + if (!host->plat_data) { + ret = -EINVAL; + goto out0; + } + + /* Get pwr supply for SDHC */ + if (NULL != mmc_plat->power_mmc) { + host->regulator_mmc = + regulator_get(&pdev->dev, mmc_plat->power_mmc); + if (IS_ERR(host->regulator_mmc)) { + ret = PTR_ERR(host->regulator_mmc); + goto out1; + } + if (regulator_enable(host->regulator_mmc) == 0) { + pr_debug("mmc power on\n"); + msleep(1); + } + } + + gpio_sdhc_active(pdev->id); + + host->clk = clk_get(&pdev->dev, "sdhc_clk"); + pr_debug("SDHC:%d clock:%lu\n", pdev->id, clk_get_rate(host->clk)); + clk_enable(host->clk); + + host->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!host->res) { + ret = -ENOMEM; + goto out2; + } + + if (!request_mem_region(host->res->start, + host->res->end - + host->res->start + 1, pdev->name)) { + printk(KERN_ERR "request_mem_region failed\n"); + ret = -ENOMEM; + goto out2; + } + host->base = (void *)IO_ADDRESS(host->res->start); + if (!host->base) { + ret = -ENOMEM; + goto out3; + } + + host->irq = platform_get_irq(pdev, 0); + if (!host->irq) { + ret = -ENOMEM; + goto out3; + } + + if (!host->plat_data->card_fixed) { + host->detect_irq = platform_get_irq(pdev, 1); + if (!host->detect_irq) + goto out3; + + do { + card_gpio_status = + host->plat_data->status(host->mmc->parent); + if (card_gpio_status) + set_irq_type(host->detect_irq, IRQT_FALLING); + else + set_irq_type(host->detect_irq, IRQT_RISING); + + } while (card_gpio_status != + host->plat_data->status(host->mmc->parent)); + + ret = request_irq(host->detect_irq, mxcmci_gpio_irq, 0, + pdev->name, host); + if (ret) + goto out3; + } + + mxcmci_softreset(host); + + if (__raw_readl(host->base + MMC_REV_NO) != SDHC_REV_NO) { + printk(KERN_ERR "%s: wrong rev.no. 0x%08x. aborting.\n", + pdev->name, MMC_REV_NO); + goto out3; + } + __raw_writel(READ_TO_VALUE, host->base + MMC_READ_TO); + + __raw_writel(INT_CNTR_END_CMD_RES, host->base + MMC_INT_CNTR); + + ret = request_irq(host->irq, mxcmci_irq, 0, pdev->name, host); + if (ret) { + goto out4; + } + + if ((ret = mmc_add_host(mmc)) < 0) { + goto out5; + } + + printk(KERN_INFO "%s-%d found\n", pdev->name, pdev->id); + if (host->id < MAX_HOST) + hosts[host->id] = host->mmc; + + return 0; + + out5: + free_irq(host->irq, host); + out4: + free_irq(host->detect_irq, host); + out3: + release_mem_region(pdev->resource[0].start, + pdev->resource[0].end - pdev->resource[0].start + 1); + out2: + clk_disable(host->clk); + regulator_disable(host->regulator_mmc); + regulator_put(host->regulator_mmc, &pdev->dev); + out1: + gpio_sdhc_inactive(pdev->id); + out0: + mmc_free_host(mmc); + platform_set_drvdata(pdev, NULL); + return ret; +} + +/*! + * Dissociates the driver from the SDHC device. Removes the appropriate SDHC + * module structure from the core driver. + * + * @param pdev the device structure used to give information on which SDHC + * to remove + * + * @return The function always returns 0. + */ +static int mxcmci_remove(struct platform_device *pdev) +{ + struct mmc_host *mmc = platform_get_drvdata(pdev); + + if (mmc) { + struct mxcmci_host *host = mmc_priv(mmc); + + hosts[host->id] = NULL; + mmc_remove_host(mmc); + free_irq(host->irq, host); + free_irq(host->detect_irq, host); +#ifdef MXC_MMC_DMA_ENABLE + mxc_dma_free(host->dma); +#endif + release_mem_region(host->res->start, + host->res->end - host->res->start + 1); + mmc_free_host(mmc); + if (NULL != host->regulator_mmc) + regulator_put(host->regulator_mmc, &pdev->dev); + gpio_sdhc_inactive(pdev->id); + } + platform_set_drvdata(pdev, NULL); + return 0; +} + +#ifdef CONFIG_PM + +/*! + * This function is called to put the SDHC in a low power state. Refer to the + * document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which SDHC + * to suspend + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int mxcmci_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct mmc_host *mmc = platform_get_drvdata(pdev); + struct mxcmci_host *host = mmc_priv(mmc); + int ret = 0; + + if (mmc) { + host->mxc_mmc_suspend_flag = 1; + ret = mmc_suspend_host(mmc, state); + } + + clk_disable(host->clk); + /* + * The CD INT should be disabled in the suspend + * and enabled in resumed. + * Otherwise, the system would be halt when wake + * up with the situation that there is a card + * insertion during the system is in suspend mode. + */ + disable_irq(host->detect_irq); + + gpio_sdhc_inactive(pdev->id); + + if (host->regulator_mmc) + regulator_disable(host->regulator_mmc); + + return ret; +} + +/*! + * This function is called to bring the SDHC back from a low power state. Refer + * to the document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which SDHC + * to resume + * + * @return The function always returns 0. + */ +static int mxcmci_resume(struct platform_device *pdev) +{ + struct mmc_host *mmc = platform_get_drvdata(pdev); + struct mxcmci_host *host = mmc_priv(mmc); + int ret = 0; + + /* + * Note that a card insertion interrupt will cause this + * driver to resume automatically. In that case we won't + * actually have to do any work here. Return success. + */ + if (!host->mxc_mmc_suspend_flag) { + return 0; + } + + /* enable pwr supply for SDHC */ + if (host->regulator_mmc) { + regulator_enable(host->regulator_mmc); + msleep(1); + } + + gpio_sdhc_active(pdev->id); + + clk_enable(host->clk); + + if (mmc) { + ret = mmc_resume_host(mmc); + host->mxc_mmc_suspend_flag = 0; + } + + enable_irq(host->detect_irq); + + return ret; +} +#else +#define mxcmci_suspend NULL +#define mxcmci_resume NULL +#endif /* CONFIG_PM */ + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxcmci_driver = { + .driver = { + .name = "mxcmci", + }, + .probe = mxcmci_probe, + .remove = mxcmci_remove, + .suspend = mxcmci_suspend, + .resume = mxcmci_resume, +}; + +/*! + * This function is used to initialize the MMC/SD driver module. The function + * registers the power management callback functions with the kernel and also + * registers the MMC/SD callback functions with the core MMC/SD driver. + * + * @return The function returns 0 on success and a non-zero value on failure. + */ +static int __init mxcmci_init(void) +{ + printk(KERN_INFO "MXC MMC/SD driver\n"); + return platform_driver_register(&mxcmci_driver); +} + +/*! + * This function is used to cleanup all resources before the driver exits. + */ +static void __exit mxcmci_exit(void) +{ + platform_driver_unregister(&mxcmci_driver); +} + +module_init(mxcmci_init); +module_exit(mxcmci_exit); + +MODULE_DESCRIPTION("MXC Multimedia Card Interface Driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mmc/host/mxc_mmc.h linux-2.6.26-lab126/drivers/mmc/host/mxc_mmc.h --- linux-2.6.26/drivers/mmc/host/mxc_mmc.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mmc/host/mxc_mmc.h 2010-08-10 04:16:00.000000000 -0400 @@ -0,0 +1,128 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MXC_MMC_REG_H__ +#define __MXC_MMC_REG_H__ + +#include + +/*! + * @defgroup MMC_SD MMC/SD Driver + */ + +/*! + * @file mxc_mmc.h + * + * @brief Driver for the Freescale Semiconductor MXC SDHC modules. + * + * This file defines offsets and bits of SDHC registers. SDHC is also referred as + * MMC/SD controller + * + * @ingroup MMC_SD + */ + +/*! + * Number of SDHC modules + */ + +#define SDHC_MMC_WML 16 +#define SDHC_SD_WML 64 +#define DRIVER_NAME "MXCMMC" +#define SDHC_MEM_SIZE 16384 +#define SDHC_REV_NO 0x400 +#define READ_TO_VALUE 0x2db4 + +/* Address offsets of the SDHC registers */ +#define MMC_STR_STP_CLK 0x00 /* Clock Control Reg */ +#define MMC_STATUS 0x04 /* Status Reg */ +#define MMC_CLK_RATE 0x08 /* Clock Rate Reg */ +#define MMC_CMD_DAT_CONT 0x0C /* Command and Data Control Reg */ +#define MMC_RES_TO 0x10 /* Response Time-out Reg */ +#define MMC_READ_TO 0x14 /* Read Time-out Reg */ +#define MMC_BLK_LEN 0x18 /* Block Length Reg */ +#define MMC_NOB 0x1C /* Number of Blocks Reg */ +#define MMC_REV_NO 0x20 /* Revision Number Reg */ +#define MMC_INT_CNTR 0x24 /* Interrupt Control Reg */ +#define MMC_CMD 0x28 /* Command Number Reg */ +#define MMC_ARG 0x2C /* Command Argument Reg */ +#define MMC_RES_FIFO 0x34 /* Command Response Reg */ +#define MMC_BUFFER_ACCESS 0x38 /* Data Buffer Access Reg */ +#define MMC_REM_NOB 0x40 /* Remaining NOB Reg */ +#define MMC_REM_BLK_SIZE 0x44 /* Remaining Block Size Reg */ + +/* Bit definitions for STR_STP_CLK */ +#define STR_STP_CLK_IPG_CLK_GATE_DIS (1<<15) +#define STR_STP_CLK_IPG_PERCLK_GATE_DIS (1<<14) +#define STR_STP_CLK_RESET (1<<3) +#define STR_STP_CLK_START_CLK (1<<1) +#define STR_STP_CLK_STOP_CLK (1<<0) + +/* Bit definitions for STATUS */ +#define STATUS_CARD_INSERTION (1<<31) +#define STATUS_CARD_REMOVAL (1<<30) +#define STATUS_YBUF_EMPTY (1<<29) +#define STATUS_XBUF_EMPTY (1<<28) +#define STATUS_YBUF_FULL (1<<27) +#define STATUS_XBUF_FULL (1<<26) +#define STATUS_BUF_UND_RUN (1<<25) +#define STATUS_BUF_OVFL (1<<24) +#define STATUS_SDIO_INT_ACTIVE (1<<14) +#define STATUS_END_CMD_RESP (1<<13) +#define STATUS_WRITE_OP_DONE (1<<12) +#define STATUS_READ_OP_DONE (1<<11) +#define STATUS_WR_CRC_ERROR_CODE_MASK (3<<9) +#define STATUS_CARD_BUS_CLK_RUN (1<<8) +#define STATUS_BUF_READ_RDY (1<<7) +#define STATUS_BUF_WRITE_RDY (1<<6) +#define STATUS_RESP_CRC_ERR (1<<5) +#define STATUS_READ_CRC_ERR (1<<3) +#define STATUS_WRITE_CRC_ERR (1<<2) +#define STATUS_TIME_OUT_RESP (1<<1) +#define STATUS_TIME_OUT_READ (1<<0) +#define STATUS_ERR_MASK 0x3f + +/* Clock rate definitions */ +#define CLK_RATE_PRESCALER(x) ((x) & 0xF) +#define CLK_RATE_CLK_DIVIDER(x) (((x) & 0xF) << 4) + +/* Bit definitions for CMD_DAT_CONT */ +#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1<<12) +#define CMD_DAT_CONT_STOP_READWAIT (1<<11) +#define CMD_DAT_CONT_START_READWAIT (1<<10) +#define CMD_DAT_CONT_BUS_WIDTH_1 (0<<8) +#define CMD_DAT_CONT_BUS_WIDTH_4 (2<<8) +#define CMD_DAT_CONT_INIT (1<<7) +#define CMD_DAT_CONT_WRITE (1<<4) +#define CMD_DAT_CONT_DATA_ENABLE (1<<3) +#define CMD_DAT_CONT_RESPONSE_FORMAT_R1 (1) +#define CMD_DAT_CONT_RESPONSE_FORMAT_R2 (2) +#define CMD_DAT_CONT_RESPONSE_FORMAT_R3 (3) +#define CMD_DAT_CONT_RESPONSE_FORMAT_R4 (4) +#define CMD_DAT_CONT_RESPONSE_FORMAT_R5 (5) +#define CMD_DAT_CONT_RESPONSE_FORMAT_R6 (6) + +/* Bit definitions for INT_CNTR */ +#define INT_CNTR_SDIO_INT_WKP_EN (1<<18) +#define INT_CNTR_CARD_INSERTION_WKP_EN (1<<17) +#define INT_CNTR_CARD_REMOVAL_WKP_EN (1<<16) +#define INT_CNTR_CARD_INSERTION_EN (1<<15) +#define INT_CNTR_CARD_REMOVAL_EN (1<<14) +#define INT_CNTR_SDIO_IRQ_EN (1<<13) +#define INT_CNTR_DAT0_EN (1<<12) +#define INT_CNTR_BUF_READ_EN (1<<4) +#define INT_CNTR_BUF_WRITE_EN (1<<3) +#define INT_CNTR_END_CMD_RES (1<<2) +#define INT_CNTR_WRITE_OP_DONE (1<<1) +#define INT_CNTR_READ_OP_DONE (1<<0) + +#endif /* __MXC_MMC_REG_H__ */ diff -urN linux-2.6.26/drivers/mtd/chips/cfi_probe.c linux-2.6.26-lab126/drivers/mtd/chips/cfi_probe.c --- linux-2.6.26/drivers/mtd/chips/cfi_probe.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/chips/cfi_probe.c 2010-08-10 04:15:34.000000000 -0400 @@ -27,7 +27,8 @@ static int cfi_probe_chip(struct map_info *map, __u32 base, unsigned long *chip_map, struct cfi_private *cfi); -static int cfi_chip_setup(struct map_info *map, struct cfi_private *cfi); +static int cfi_chip_setup(struct map_info *map, struct cfi_private *cfi, + int amd555); struct mtd_info *cfi_probe(struct map_info *map); @@ -50,12 +51,12 @@ xip_allowed(base, map); \ } while (0) -#define xip_disable_qry(base, map, cfi) \ +#define xip_disable_qry(base, map, cfi, amd555) \ do { \ xip_disable(); \ cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL); \ cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL); \ - cfi_send_gen_cmd(0x98, 0x55, base, map, cfi, cfi->device_type, NULL); \ + cfi_send_gen_cmd(0x98, amd555 ? 0x555 : 0x55, base, map, cfi, cfi->device_type, NULL);\ } while (0) #else @@ -63,7 +64,7 @@ #define xip_disable() do { } while (0) #define xip_allowed(base, map) do { } while (0) #define xip_enable(base, map, cfi) do { } while (0) -#define xip_disable_qry(base, map, cfi) do { } while (0) +#define xip_disable_qry(base, map, cfi, amd555) do { } while (0) #endif @@ -102,6 +103,7 @@ unsigned long *chip_map, struct cfi_private *cfi) { int i; + int amd555 = 0; if ((base + 0) >= map->size) { printk(KERN_NOTICE @@ -122,14 +124,20 @@ cfi_send_gen_cmd(0x98, 0x55, base, map, cfi, cfi->device_type, NULL); if (!qry_present(map,base,cfi)) { - xip_enable(base, map, cfi); - return 0; + cfi_send_gen_cmd(0x98, 0x555, base, map, cfi, cfi->device_type, + NULL); + if (!qry_present(map,base,cfi)) { + xip_enable(base, map, cfi); + return 0; + } + + amd555 = 1; } if (!cfi->numchips) { /* This is the first time we're called. Set up the CFI stuff accordingly and return */ - return cfi_chip_setup(map, cfi); + return cfi_chip_setup(map, cfi, amd555); } /* Check each previous chip to see if it's an alias */ @@ -189,7 +197,7 @@ } static int __xipram cfi_chip_setup(struct map_info *map, - struct cfi_private *cfi) + struct cfi_private *cfi, int amd555) { int ofs_factor = cfi->interleave*cfi->device_type; __u32 base = 0; @@ -214,7 +222,7 @@ cfi->cfi_mode = CFI_MODE_CFI; /* Read the CFI info structure */ - xip_disable_qry(base, map, cfi); + xip_disable_qry(base, map, cfi, amd555); for (i=0; i<(sizeof(struct cfi_ident) + num_erase_regions * 4); i++) ((unsigned char *)cfi->cfiq)[i] = cfi_read_query(map,base + (0x10 + i)*ofs_factor); diff -urN linux-2.6.26/drivers/mtd/chips/cfi_util.c linux-2.6.26-lab126/drivers/mtd/chips/cfi_util.c --- linux-2.6.26/drivers/mtd/chips/cfi_util.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/chips/cfi_util.c 2010-08-10 04:15:34.000000000 -0400 @@ -50,8 +50,15 @@ local_irq_disable(); #endif - /* Switch it into Query Mode */ - cfi_send_gen_cmd(0x98, 0x55, base, map, cfi, cfi->device_type, NULL); + /* Switch it into Query Mode. Some chips want address 0x55, some + * want 0x555. + */ + if ((cfi->mfr == CFI_MFR_AMD) && (cfi->id == 0x227E)) + cfi_send_gen_cmd(0x98, 0x555, base, map, cfi, cfi->device_type, + NULL); + else + cfi_send_gen_cmd(0x98, 0x55, base, map, cfi, cfi->device_type, + NULL); /* Read in the Extended Query Table */ for (i=0; i +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DVR_VER "2.0" + +#ifdef CONFIG_MTD_PARTITIONS +static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL }; +#endif + +struct clocksource *mtd_xip_clksrc; + +struct mxcflash_info { + struct mtd_partition *parts; + struct mtd_info *mtd; + struct map_info map; +}; + +/*! + * @defgroup NOR_MTD NOR Flash MTD Driver + */ + +/*! + * @file mxc_nor.c + * + * @brief This file contains the MTD Mapping information on the MXC. + * + * @ingroup NOR_MTD + */ + +static int __devinit mxcflash_probe(struct platform_device *pdev) +{ + int err, nr_parts = 0; + struct mxcflash_info *info; + struct flash_platform_data *flash = pdev->dev.platform_data; + struct resource *res = pdev->resource; + unsigned long size = res->end - res->start + 1; + + info = kzalloc(sizeof(struct mxcflash_info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + if (!request_mem_region(res->start, size, "flash")) { + err = -EBUSY; + goto out_free_info; + } + info->map.virt = ioremap(res->start, size); + if (!info->map.virt) { + err = -ENOMEM; + goto out_release_mem_region; + } + info->map.name = pdev->dev.bus_id; + info->map.phys = res->start; + info->map.size = size; + info->map.bankwidth = flash->width; + + mtd_xip_clksrc = clocksource_get_next(); + + simple_map_init(&info->map); + info->mtd = do_map_probe(flash->map_name, &info->map); + if (!info->mtd) { + err = -EIO; + goto out_iounmap; + } + info->mtd->owner = THIS_MODULE; + +#ifdef CONFIG_MTD_PARTITIONS + nr_parts = + parse_mtd_partitions(info->mtd, part_probes, &info->parts, 0); + if (nr_parts > 0) { + add_mtd_partitions(info->mtd, info->parts, nr_parts); + } else if (flash->parts) { + add_mtd_partitions(info->mtd, flash->parts, flash->nr_parts); + } else +#endif + { + printk(KERN_NOTICE "MXC flash: no partition info " + "available, registering whole flash\n"); + add_mtd_device(info->mtd); + } + + platform_set_drvdata(pdev, info); + return 0; + + out_iounmap: + iounmap(info->map.virt); + out_release_mem_region: + release_mem_region(res->start, size); + out_free_info: + kfree(info); + + return err; +} + +static int __devexit mxcflash_remove(struct platform_device *pdev) +{ + + struct mxcflash_info *info = platform_get_drvdata(pdev); + struct flash_platform_data *flash = pdev->dev.platform_data; + + platform_set_drvdata(pdev, NULL); + + if (info) { + if (info->parts) { + del_mtd_partitions(info->mtd); + kfree(info->parts); + } else if (flash->parts) + del_mtd_partitions(info->mtd); + else + del_mtd_device(info->mtd); + + map_destroy(info->mtd); + release_mem_region(info->map.phys, info->map.size); + iounmap((void __iomem *)info->map.virt); + kfree(info); + } + return 0; +} + +static struct platform_driver mxcflash_driver = { + .driver = { + .name = "mxc_nor_flash", + }, + .probe = mxcflash_probe, + .remove = __devexit_p(mxcflash_remove), +}; + +/*! + * This is the module's entry function. It passes board specific + * config details into the MTD physmap driver which then does the + * real work for us. After this function runs, our job is done. + * + * @return 0 if successful; non-zero otherwise + */ +static int __init mxc_mtd_init(void) +{ + pr_info("MXC MTD nor Driver %s\n", DVR_VER); + if (platform_driver_register(&mxcflash_driver) != 0) { + printk(KERN_ERR "Driver register failed for mxcflash_driver\n"); + return -ENODEV; + } + return 0; +} + +/*! + * This function is the module's exit function. It's empty because the + * MTD physmap driver is doing the real work and our job was done after + * mxc_mtd_init() runs. + */ +static void __exit mxc_mtd_exit(void) +{ + platform_driver_unregister(&mxcflash_driver); +} + +module_init(mxc_mtd_init); +module_exit(mxc_mtd_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MTD map and partitions for Freescale MXC boards"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mtd/nand/Kconfig linux-2.6.26-lab126/drivers/mtd/nand/Kconfig --- linux-2.6.26/drivers/mtd/nand/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/nand/Kconfig 2010-08-10 04:15:32.000000000 -0400 @@ -345,6 +345,56 @@ The simulator may simulate various NAND flash chips for the MTD nand layer. +config MTD_NAND_MXC + tristate "MXC NAND support" + depends on MTD_NAND && ARCH_MXC_HAS_NFC_V1 + help + This enables the driver for the NAND flash controller on the + MXC processors. + +config MTD_NAND_MXC_V2 + tristate "MXC NAND Version 2 support" + depends on MTD_NAND && ARCH_MXC_HAS_NFC_V2 + help + This enables the driver for the version 2 of NAND flash controller + on the MXC processors. + +config MTD_NAND_MXC_V3 + tristate "MXC NAND Version 3 support" + depends on MTD_NAND && ARCH_MXC_HAS_NFC_V3 + help + This enables the driver for the version 3 of NAND flash controller + on the MXC processors. + +config MTD_NAND_MXC_SWECC + bool "Software ECC support " + depends on MTD_NAND_MXC || MTD_NAND_MXC_V2 || MTD_NAND_MXC_V3 + help + This enables the support for Software ECC handling. By + default MXC NAND controller Hardware ECC is supported. + + +config MTD_NAND_MXC_FORCE_CE + bool "NAND chip select operation support" + depends on MTD_NAND_MXC || MTD_NAND_MXC_V2|| MTD_NAND_MXC_V3 + help + This enables the NAND chip select by using CE control line. By + default CE operation is disabled. + +config MTD_NAND_MXC_ECC_CORRECTION_OPTION2 + bool "ECC correction in S/W" + depends on MTD_NAND_MXC + help + This enables the Option2 NFC ECC correction in software. By + default Option 1 is selected. Enable if you need option2 ECC correction. + +config MXC_NAND_LOW_LEVEL_ERASE + bool "Low level NAND erase" + depends on MTD_NAND_MXC || MTD_NAND_MXC_V2 || MTD_NAND_MXC_V3 + help + This enables the erase of whole NAND flash. By + default low level erase operation is disabled. + config MTD_NAND_PLATFORM tristate "Support for generic platform NAND driver" depends on MTD_NAND diff -urN linux-2.6.26/drivers/mtd/nand/Makefile linux-2.6.26-lab126/drivers/mtd/nand/Makefile --- linux-2.6.26/drivers/mtd/nand/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/nand/Makefile 2010-08-10 04:15:32.000000000 -0400 @@ -24,6 +24,9 @@ obj-$(CONFIG_MTD_NAND_NANDSIM) += nandsim.o obj-$(CONFIG_MTD_NAND_CS553X) += cs553x_nand.o obj-$(CONFIG_MTD_NAND_NDFC) += ndfc.o +obj-$(CONFIG_MTD_NAND_MXC) += mxc_nd.o +obj-$(CONFIG_MTD_NAND_MXC_V2) += mxc_nd2.o +obj-$(CONFIG_MTD_NAND_MXC_V3) += mxc_nd2.o obj-$(CONFIG_MTD_NAND_AT91) += at91_nand.o obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += excite_nandflash.o diff -urN linux-2.6.26/drivers/mtd/nand/mxc_nd.c linux-2.6.26-lab126/drivers/mtd/nand/mxc_nd.c --- linux-2.6.26/drivers/mtd/nand/mxc_nd.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mtd/nand/mxc_nd.c 2010-08-10 04:15:32.000000000 -0400 @@ -0,0 +1,1413 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mxc_nd.h" + +#define DVR_VER "2.1" + +struct mxc_mtd_s { + struct mtd_info mtd; + struct nand_chip nand; + struct mtd_partition *parts; + struct device *dev; +}; + +static struct mxc_mtd_s *mxc_nand_data; + +/* + * Define delays in microsec for NAND device operations + */ +#define TROP_US_DELAY 2000 +/* + * Macros to get half word and bit positions of ECC + */ +#define COLPOS(x) ((x) >> 4) +#define BITPOS(x) ((x) & 0xf) + +/* Define single bit Error positions in Main & Spare area */ +#define MAIN_SINGLEBIT_ERROR 0x4 +#define SPARE_SINGLEBIT_ERROR 0x1 + +struct nand_info { + bool bSpareOnly; + bool bStatusRequest; + u16 colAddr; +}; + +static struct nand_info g_nandfc_info; + +#ifdef CONFIG_MTD_NAND_MXC_SWECC +static int hardware_ecc = 0; +#else +static int hardware_ecc = 1; +#endif + +#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 +static int Ecc_disabled; +#endif + +static int is2k_Pagesize = 0; + +static struct clk *nfc_clk; + +/* + * OOB placement block for use with hardware ecc generation + */ +static struct nand_ecclayout nand_hw_eccoob_8 = { + .eccbytes = 5, + .eccpos = {6, 7, 8, 9, 10}, + .oobfree = {{0, 5}, {11, 5}} +}; + +static struct nand_ecclayout nand_hw_eccoob_16 = { + .eccbytes = 5, + .eccpos = {6, 7, 8, 9, 10}, + .oobfree = {{0, 6}, {12, 4}} +}; + +static struct nand_ecclayout nand_hw_eccoob_2k = { + .eccbytes = 20, + .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26, + 38, 39, 40, 41, 42, 54, 55, 56, 57, 58}, + .oobfree = { + {.offset = 0, + .length = 5}, + + {.offset = 11, + .length = 10}, + + {.offset = 27, + .length = 10}, + + {.offset = 43, + .length = 10}, + + {.offset = 59, + .length = 5} + } +}; + +/*! + * @defgroup NAND_MTD NAND Flash MTD Driver for MXC processors + */ + +/*! + * @file mxc_nd.c + * + * @brief This file contains the hardware specific layer for NAND Flash on + * MXC processor + * + * @ingroup NAND_MTD + */ + +#ifdef CONFIG_MTD_PARTITIONS +static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL }; +#endif + +static wait_queue_head_t irq_waitq; + +static irqreturn_t mxc_nfc_irq(int irq, void *dev_id) +{ + NFC_CONFIG1 |= NFC_INT_MSK; /* Disable interrupt */ + wake_up(&irq_waitq); + + return IRQ_RETVAL(1); +} + +/*! + * This function polls the NANDFC to wait for the basic operation to complete by + * checking the INT bit of config2 register. + * + * @param maxRetries number of retry attempts (separated by 1 us) + * @param param parameter for debug + * @param useirq True if IRQ should be used rather than polling + */ +static void wait_op_done(int maxRetries, u16 param, bool useirq) +{ + if (useirq) { + if ((NFC_CONFIG2 & NFC_INT) == 0) { + NFC_CONFIG1 &= ~NFC_INT_MSK; /* Enable interrupt */ + wait_event(irq_waitq, NFC_CONFIG2 & NFC_INT); + } + NFC_CONFIG2 &= ~NFC_INT; + } else { + while (maxRetries-- > 0) { + if (NFC_CONFIG2 & NFC_INT) { + NFC_CONFIG2 &= ~NFC_INT; + break; + } + udelay(1); + } + if (maxRetries <= 0) + DEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n", + __FUNCTION__, param); + } +} + +/*! + * This function issues the specified command to the NAND device and + * waits for completion. + * + * @param cmd command for NAND Flash + * @param useirq True if IRQ should be used rather than polling + */ +static void send_cmd(u16 cmd, bool useirq) +{ + DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(0x%x, %d)\n", cmd, useirq); + + NFC_FLASH_CMD = (u16) cmd; + NFC_CONFIG2 = NFC_CMD; + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, cmd, useirq); +} + +/*! + * This function sends an address (or partial address) to the + * NAND device. The address is used to select the source/destination for + * a NAND command. + * + * @param addr address to be written to NFC. + * @param islast True if this is the last address cycle for command + */ +static void send_addr(u16 addr, bool islast) +{ + DEBUG(MTD_DEBUG_LEVEL3, "send_addr(0x%x %d)\n", addr, islast); + + NFC_FLASH_ADDR = addr; + NFC_CONFIG2 = NFC_ADDR; + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, addr, islast); +} + +/*! + * This function requests the NANDFC to initate the transfer + * of data currently in the NANDFC RAM buffer to the NAND device. + * + * @param buf_id Specify Internal RAM Buffer number (0-3) + * @param bSpareOnly set true if only the spare area is transferred + */ +static void send_prog_page(u8 buf_id, bool bSpareOnly) +{ + DEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", bSpareOnly); + + /* NANDFC buffer 0 is used for page read/write */ + + NFC_BUF_ADDR = buf_id; + + /* Configure spare or page+spare access */ + if (!is2k_Pagesize) { + if (bSpareOnly) { + NFC_CONFIG1 |= NFC_SP_EN; + } else { + NFC_CONFIG1 &= ~(NFC_SP_EN); + } + } + NFC_CONFIG2 = NFC_INPUT; + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, bSpareOnly, true); +} + +/*! + * This function will correct the single bit ECC error + * + * @param buf_id Specify Internal RAM Buffer number (0-3) + * @param eccpos Ecc byte and bit position + * @param bSpareOnly set to true if only spare area needs correction + */ + +static void mxc_nd_correct_error(u8 buf_id, u16 eccpos, bool bSpareOnly) +{ + u16 col; + u8 pos; + volatile u16 *buf; + + /* Get col & bit position of error + these macros works for both 8 & 16 bits */ + col = COLPOS(eccpos); /* Get half-word position */ + pos = BITPOS(eccpos); /* Get bit position */ + + DEBUG(MTD_DEBUG_LEVEL3, + "mxc_nd_correct_error (col=%d pos=%d)\n", col, pos); + + /* Set the pointer for main / spare area */ + if (!bSpareOnly) { + buf = (volatile u16 *)(MAIN_AREA0 + col + (256 * buf_id)); + } else { + buf = (volatile u16 *)(SPARE_AREA0 + col + (8 * buf_id)); + } + + /* Fix the data */ + *buf ^= (1 << pos); +} + +/*! + * This function will maintains state of single bit Error + * in Main & spare area + * + * @param buf_id Specify Internal RAM Buffer number (0-3) + * @param spare set to true if only spare area needs correction + */ +static void mxc_nd_correct_ecc(u8 buf_id, bool spare) +{ +#ifdef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 + static int lastErrMain = 0, lastErrSpare = 0; /* To maintain single bit + error in previous page */ +#endif + u16 value, ecc_status; + /* Read the ECC result */ + ecc_status = NFC_ECC_STATUS_RESULT; + DEBUG(MTD_DEBUG_LEVEL3, + "mxc_nd_correct_ecc (Ecc status=%x)\n", ecc_status); + +#ifdef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 + /* Check for Error in Mainarea */ + if ((ecc_status & 0xC) == MAIN_SINGLEBIT_ERROR) { + /* Check for error in previous page */ + if (lastErrMain && !spare) { + value = NFC_RSLTMAIN_AREA; + /* Correct single bit error in Mainarea + NFC will not correct the error in + current page */ + mxc_nd_correct_error(buf_id, value, false); + } else { + /* Set if single bit error in current page */ + lastErrMain = 1; + } + } else { + /* Reset if no single bit error in current page */ + lastErrMain = 0; + } + + /* Check for Error in Sparearea */ + if ((ecc_status & 0x3) == SPARE_SINGLEBIT_ERROR) { + /* Check for error in previous page */ + if (lastErrSpare) { + value = NFC_RSLTSPARE_AREA; + /* Correct single bit error in Mainarea + NFC will not correct the error in + current page */ + mxc_nd_correct_error(buf_id, value, true); + } else { + /* Set if single bit error in current page */ + lastErrSpare = 1; + } + } else { + /* Reset if no single bit error in current page */ + lastErrSpare = 0; + } +#else + if (((ecc_status & 0xC) == MAIN_SINGLEBIT_ERROR) + || ((ecc_status & 0x3) == SPARE_SINGLEBIT_ERROR)) { + if (Ecc_disabled) { + if ((ecc_status & 0xC) == MAIN_SINGLEBIT_ERROR) { + value = NFC_RSLTMAIN_AREA; + /* Correct single bit error in Mainarea + NFC will not correct the error in + current page */ + mxc_nd_correct_error(buf_id, value, false); + } + if ((ecc_status & 0x3) == SPARE_SINGLEBIT_ERROR) { + value = NFC_RSLTSPARE_AREA; + /* Correct single bit error in Mainarea + NFC will not correct the error in + current page */ + mxc_nd_correct_error(buf_id, value, true); + } + + } else { + /* Disable ECC */ + NFC_CONFIG1 &= ~(NFC_ECC_EN); + Ecc_disabled = 1; + } + } else if (ecc_status == 0) { + if (Ecc_disabled) { + /* Enable ECC */ + NFC_CONFIG1 |= NFC_ECC_EN; + Ecc_disabled = 0; + } + } else { + /* 2-bit Error Do nothing */ + } +#endif /* CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 */ + +} + +/*! + * This function requests the NANDFC to initated the transfer + * of data from the NAND device into in the NANDFC ram buffer. + * + * @param buf_id Specify Internal RAM Buffer number (0-3) + * @param bSpareOnly set true if only the spare area is transferred + */ +static void send_read_page(u8 buf_id, bool bSpareOnly) +{ + DEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", bSpareOnly); + + /* NANDFC buffer 0 is used for page read/write */ + NFC_BUF_ADDR = buf_id; + + /* Configure spare or page+spare access */ + if (!is2k_Pagesize) { + if (bSpareOnly) { + NFC_CONFIG1 |= NFC_SP_EN; + } else { + NFC_CONFIG1 &= ~(NFC_SP_EN); + } + } + + NFC_CONFIG2 = NFC_OUTPUT; + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, bSpareOnly, true); + + /* If there are single bit errors in + two consecutive page reads then + the error is not corrected by the + NFC for the second page. + Correct single bit error in driver */ + + mxc_nd_correct_ecc(buf_id, bSpareOnly); +} + +/*! + * This function requests the NANDFC to perform a read of the + * NAND device ID. + */ +static void send_read_id(void) +{ + struct nand_chip *this = &mxc_nand_data->nand; + + /* NANDFC buffer 0 is used for device ID output */ + NFC_BUF_ADDR = 0x0; + + /* Read ID into main buffer */ + NFC_CONFIG1 &= (~(NFC_SP_EN)); + NFC_CONFIG2 = NFC_ID; + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, 0, true); + + if (this->options & NAND_BUSWIDTH_16) { + volatile u16 *mainBuf = MAIN_AREA0; + + /* + * Pack the every-other-byte result for 16-bit ID reads + * into every-byte as the generic code expects and various + * chips implement. + */ + + mainBuf[0] = (mainBuf[0] & 0xff) | ((mainBuf[1] & 0xff) << 8); + mainBuf[1] = (mainBuf[2] & 0xff) | ((mainBuf[3] & 0xff) << 8); + mainBuf[2] = (mainBuf[4] & 0xff) | ((mainBuf[5] & 0xff) << 8); + } +} + +/*! + * This function requests the NANDFC to perform a read of the + * NAND device status and returns the current status. + * + * @return device status + */ +static u16 get_dev_status(void) +{ + volatile u16 *mainBuf = MAIN_AREA1; + u32 store; + u16 ret; + /* Issue status request to NAND device */ + + /* store the main area1 first word, later do recovery */ + store = *((u32 *) mainBuf); + /* + * NANDFC buffer 1 is used for device status to prevent + * corruption of read/write buffer on status requests. + */ + NFC_BUF_ADDR = 1; + + /* Read status into main buffer */ + NFC_CONFIG1 &= (~(NFC_SP_EN)); + NFC_CONFIG2 = NFC_STATUS; + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, 0, true); + + /* Status is placed in first word of main buffer */ + /* get status, then recovery area 1 data */ + ret = mainBuf[0]; + *((u32 *) mainBuf) = store; + + return ret; +} + +/*! + * This functions is used by upper layer to checks if device is ready + * + * @param mtd MTD structure for the NAND Flash + * + * @return 0 if device is busy else 1 + */ +static int mxc_nand_dev_ready(struct mtd_info *mtd) +{ + /* + * NFC handles R/B internally.Therefore,this function + * always returns status as ready. + */ + return 1; +} + +static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) +{ + /* + * If HW ECC is enabled, we turn it on during init. There is + * no need to enable again here. + */ +} + +static int mxc_nand_correct_data(struct mtd_info *mtd, u_char * dat, + u_char * read_ecc, u_char * calc_ecc) +{ + /* + * 1-Bit errors are automatically corrected in HW. No need for + * additional correction. 2-Bit errors cannot be corrected by + * HW ECC, so we need to return failure + */ + u16 ecc_status = NFC_ECC_STATUS_RESULT; + + if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { + DEBUG(MTD_DEBUG_LEVEL0, + "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n"); + return -1; + } + + return 0; +} + +static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char * dat, + u_char * ecc_code) +{ + /* + * Just return success. HW ECC does not read/write the NFC spare + * buffer. Only the FLASH spare area contains the calcuated ECC. + */ + return 0; +} + +/*! + * This function reads byte from the NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u_char mxc_nand_read_byte(struct mtd_info *mtd) +{ + u_char retVal = 0; + u16 col, rdWord; + volatile u16 *mainBuf = MAIN_AREA0; + volatile u16 *spareBuf = SPARE_AREA0; + + /* Check for status request */ + if (g_nandfc_info.bStatusRequest) { + return (get_dev_status() & 0xFF); + } + + /* Get column for 16-bit access */ + col = g_nandfc_info.colAddr >> 1; + + /* If we are accessing the spare region */ + if (g_nandfc_info.bSpareOnly) { + rdWord = spareBuf[col]; + } else { + rdWord = mainBuf[col]; + } + + /* Pick upper/lower byte of word from RAM buffer */ + if (g_nandfc_info.colAddr & 0x1) { + retVal = (rdWord >> 8) & 0xFF; + } else { + retVal = rdWord & 0xFF; + } + + /* Update saved column address */ + g_nandfc_info.colAddr++; + + return retVal; +} + +/*! + * This function reads word from the NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u16 mxc_nand_read_word(struct mtd_info *mtd) +{ + u16 col; + u16 rdWord, retVal; + volatile u16 *p; + + DEBUG(MTD_DEBUG_LEVEL3, + "mxc_nand_read_word(col = %d)\n", g_nandfc_info.colAddr); + + col = g_nandfc_info.colAddr; + /* Adjust saved column address */ + if (col < mtd->writesize && g_nandfc_info.bSpareOnly) + col += mtd->writesize; + + if (col < mtd->writesize) + p = (MAIN_AREA0) + (col >> 1); + else + p = (SPARE_AREA0) + ((col - mtd->writesize) >> 1); + + if (col & 1) { + rdWord = *p; + retVal = (rdWord >> 8) & 0xff; + rdWord = *(p + 1); + retVal |= (rdWord << 8) & 0xff00; + + } else { + retVal = *p; + + } + + /* Update saved column address */ + g_nandfc_info.colAddr = col + 2; + + return retVal; +} + +/*! + * This function writes data of length \b len to buffer \b buf. The data to be + * written on NAND Flash is first copied to RAMbuffer. After the Data Input + * Operation by the NFC, the data is written to NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * @param buf data to be written to NAND Flash + * @param len number of bytes to be written + */ +static void mxc_nand_write_buf(struct mtd_info *mtd, + const u_char * buf, int len) +{ + int n; + int col; + int i = 0; + + DEBUG(MTD_DEBUG_LEVEL3, + "mxc_nand_write_buf(col = %d, len = %d)\n", g_nandfc_info.colAddr, + len); + + col = g_nandfc_info.colAddr; + + /* Adjust saved column address */ + if (col < mtd->writesize && g_nandfc_info.bSpareOnly) + col += mtd->writesize; + + n = mtd->writesize + mtd->oobsize - col; + n = min(len, n); + + DEBUG(MTD_DEBUG_LEVEL3, + "%s:%d: col = %d, n = %d\n", __FUNCTION__, __LINE__, col, n); + + while (n) { + volatile u32 *p; + if (col < mtd->writesize) + p = (volatile u32 *)((ulong) (MAIN_AREA0) + (col & ~3)); + else + p = (volatile u32 *)((ulong) (SPARE_AREA0) - + mtd->writesize + (col & ~3)); + + DEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __FUNCTION__, + __LINE__, p); + + if (((col | (int)&buf[i]) & 3) || n < 16) { + u32 data = 0; + + if (col & 3 || n < 4) + data = *p; + + switch (col & 3) { + case 0: + if (n) { + data = (data & 0xffffff00) | + (buf[i++] << 0); + n--; + col++; + } + case 1: + if (n) { + data = (data & 0xffff00ff) | + (buf[i++] << 8); + n--; + col++; + } + case 2: + if (n) { + data = (data & 0xff00ffff) | + (buf[i++] << 16); + n--; + col++; + } + case 3: + if (n) { + data = (data & 0x00ffffff) | + (buf[i++] << 24); + n--; + col++; + } + } + + *p = data; + } else { + int m = mtd->writesize - col; + + if (col >= mtd->writesize) + m += mtd->oobsize; + + m = min(n, m) & ~3; + + DEBUG(MTD_DEBUG_LEVEL3, + "%s:%d: n = %d, m = %d, i = %d, col = %d\n", + __FUNCTION__, __LINE__, n, m, i, col); + + memcpy((void *)(p), &buf[i], m); + col += m; + i += m; + n -= m; + } + } + /* Update saved column address */ + g_nandfc_info.colAddr = col; + +} + +/*! + * This function id is used to read the data buffer from the NAND Flash. To + * read the data from NAND Flash first the data output cycle is initiated by + * the NFC, which copies the data to RAMbuffer. This data of length \b len is + * then copied to buffer \b buf. + * + * @param mtd MTD structure for the NAND Flash + * @param buf data to be read from NAND Flash + * @param len number of bytes to be read + */ +static void mxc_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len) +{ + + int n; + int col; + int i = 0; + + DEBUG(MTD_DEBUG_LEVEL3, + "mxc_nand_read_buf(col = %d, len = %d)\n", g_nandfc_info.colAddr, + len); + + col = g_nandfc_info.colAddr; + /* Adjust saved column address */ + if (col < mtd->writesize && g_nandfc_info.bSpareOnly) + col += mtd->writesize; + + n = mtd->writesize + mtd->oobsize - col; + n = min(len, n); + + while (n) { + volatile u32 *p; + + if (col < mtd->writesize) + p = (volatile u32 *)((ulong) (MAIN_AREA0) + (col & ~3)); + else + p = (volatile u32 *)((ulong) (SPARE_AREA0) - + mtd->writesize + (col & ~3)); + + if (((col | (int)&buf[i]) & 3) || n < 16) { + u32 data; + + data = *p; + switch (col & 3) { + case 0: + if (n) { + buf[i++] = (u8) (data); + n--; + col++; + } + case 1: + if (n) { + buf[i++] = (u8) (data >> 8); + n--; + col++; + } + case 2: + if (n) { + buf[i++] = (u8) (data >> 16); + n--; + col++; + } + case 3: + if (n) { + buf[i++] = (u8) (data >> 24); + n--; + col++; + } + } + } else { + int m = mtd->writesize - col; + + if (col >= mtd->writesize) + m += mtd->oobsize; + + m = min(n, m) & ~3; + memcpy(&buf[i], (void *)(p), m); + col += m; + i += m; + n -= m; + } + } + /* Update saved column address */ + g_nandfc_info.colAddr = col; + +} + +/*! + * This function is used by the upper layer to verify the data in NAND Flash + * with the data in the \b buf. + * + * @param mtd MTD structure for the NAND Flash + * @param buf data to be verified + * @param len length of the data to be verified + * + * @return -EFAULT if error else 0 + * + */ +static int +mxc_nand_verify_buf(struct mtd_info *mtd, const u_char * buf, int len) +{ + return -EFAULT; +} + +/*! + * This function is used by upper layer for select and deselect of the NAND + * chip + * + * @param mtd MTD structure for the NAND Flash + * @param chip val indicating select or deselect + */ +static void mxc_nand_select_chip(struct mtd_info *mtd, int chip) +{ +#ifdef CONFIG_MTD_NAND_MXC_FORCE_CE + if (chip > 0) { + DEBUG(MTD_DEBUG_LEVEL0, + "ERROR: Illegal chip select (chip = %d)\n", chip); + return; + } + + if (chip == -1) { + NFC_CONFIG1 &= (~(NFC_CE)); + return; + } + + NFC_CONFIG1 |= NFC_CE; +#endif + + switch (chip) { + case -1: + /* Disable the NFC clock */ + clk_disable(nfc_clk); + break; + case 0: + /* Enable the NFC clock */ + clk_enable(nfc_clk); + break; + + default: + break; + } +} + +/*! + * This function is used by the upper layer to write command to NAND Flash for + * different operations to be carried out on NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * @param command command for NAND Flash + * @param column column offset for the page read + * @param page_addr page to be read from NAND Flash + */ +static void mxc_nand_command(struct mtd_info *mtd, unsigned command, + int column, int page_addr) +{ + bool useirq = true; + + DEBUG(MTD_DEBUG_LEVEL3, + "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", + command, column, page_addr); + + /* + * Reset command state information + */ + g_nandfc_info.bStatusRequest = false; + + /* Reset column address to 0 */ + g_nandfc_info.colAddr = 0; + + /* + * Command pre-processing step + */ + switch (command) { + + case NAND_CMD_STATUS: + g_nandfc_info.bStatusRequest = true; + break; + + case NAND_CMD_READ0: + g_nandfc_info.colAddr = column; + g_nandfc_info.bSpareOnly = false; + useirq = false; + break; + + case NAND_CMD_READOOB: + g_nandfc_info.colAddr = column; + g_nandfc_info.bSpareOnly = true; + useirq = false; + if (is2k_Pagesize) + command = NAND_CMD_READ0; /* only READ0 is valid */ + break; + + case NAND_CMD_SEQIN: + if (column >= mtd->writesize) { + if (is2k_Pagesize) { + /** + * FIXME: before send SEQIN command for write OOB, + * We must read one page out. + * For K9F1GXX has no READ1 command to set current HW + * pointer to spare area, we must write the whole page including OOB together. + */ + /* call itself to read a page */ + mxc_nand_command(mtd, NAND_CMD_READ0, 0, + page_addr); + } + g_nandfc_info.colAddr = column - mtd->writesize; + g_nandfc_info.bSpareOnly = true; + /* Set program pointer to spare region */ + if (!is2k_Pagesize) + send_cmd(NAND_CMD_READOOB, false); + } else { + g_nandfc_info.bSpareOnly = false; + g_nandfc_info.colAddr = column; + /* Set program pointer to page start */ + if (!is2k_Pagesize) + send_cmd(NAND_CMD_READ0, false); + } + useirq = false; + break; + + case NAND_CMD_PAGEPROG: +#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 + if (Ecc_disabled) { + /* Enable Ecc for page writes */ + NFC_CONFIG1 |= NFC_ECC_EN; + } +#endif + + send_prog_page(0, g_nandfc_info.bSpareOnly); + + if (is2k_Pagesize) { + /* data in 4 areas datas */ + send_prog_page(1, g_nandfc_info.bSpareOnly); + send_prog_page(2, g_nandfc_info.bSpareOnly); + send_prog_page(3, g_nandfc_info.bSpareOnly); + } + + break; + + case NAND_CMD_ERASE1: + useirq = false; + break; + } + + /* + * Write out the command to the device. + */ + send_cmd(command, useirq); + + /* + * Write out column address, if necessary + */ + if (column != -1) { + /* + * MXC NANDFC can only perform full page+spare or + * spare-only read/write. When the upper layers + * layers perform a read/write buf operation, + * we will used the saved column adress to index into + * the full page. + */ + send_addr(0, page_addr == -1); + if (is2k_Pagesize) + /* another col addr cycle for 2k page */ + send_addr(0, false); + } + + /* + * Write out page address, if necessary + */ + if (page_addr != -1) { + send_addr((page_addr & 0xff), false); /* paddr_0 - p_addr_7 */ + + if (is2k_Pagesize) { + /* One more address cycle for higher density devices */ + if (mtd->size >= 0x10000000) { + /* paddr_8 - paddr_15 */ + send_addr((page_addr >> 8) & 0xff, false); + send_addr((page_addr >> 16) & 0xff, true); + } else + /* paddr_8 - paddr_15 */ + send_addr((page_addr >> 8) & 0xff, true); + } else { + /* One more address cycle for higher density devices */ + if (mtd->size >= 0x4000000) { + /* paddr_8 - paddr_15 */ + send_addr((page_addr >> 8) & 0xff, false); + send_addr((page_addr >> 16) & 0xff, true); + } else + /* paddr_8 - paddr_15 */ + send_addr((page_addr >> 8) & 0xff, true); + } + } + + /* + * Command post-processing step + */ + switch (command) { + + case NAND_CMD_RESET: + break; + + case NAND_CMD_READOOB: + case NAND_CMD_READ0: + if (is2k_Pagesize) { + /* send read confirm command */ + send_cmd(NAND_CMD_READSTART, true); + /* read for each AREA */ + send_read_page(0, g_nandfc_info.bSpareOnly); + send_read_page(1, g_nandfc_info.bSpareOnly); + send_read_page(2, g_nandfc_info.bSpareOnly); + send_read_page(3, g_nandfc_info.bSpareOnly); + } else { + send_read_page(0, g_nandfc_info.bSpareOnly); + } + break; + + case NAND_CMD_READID: + send_read_id(); + break; + + case NAND_CMD_PAGEPROG: +#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 + if (Ecc_disabled) { + /* Disble Ecc after page writes */ + NFC_CONFIG1 &= ~(NFC_ECC_EN); + } +#endif + break; + + case NAND_CMD_STATUS: + break; + + case NAND_CMD_ERASE2: + break; + } +} + +/* Define some generic bad / good block scan pattern which are used + * while scanning a device for factory marked good / bad blocks. */ +static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; + +static struct nand_bbt_descr smallpage_memorybased = { + .options = NAND_BBT_SCAN2NDPAGE, + .offs = 5, + .len = 1, + .pattern = scan_ff_pattern +}; + +static struct nand_bbt_descr largepage_memorybased = { + .options = 0, + .offs = 0, + .len = 2, + .pattern = scan_ff_pattern +}; + +/* Generic flash bbt decriptors +*/ +static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; +static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = bbt_pattern +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = mirror_pattern +}; + +static int mxc_nand_scan_bbt(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + + /* Config before scanning */ + /* Do not rely on NFMS_BIT, set/clear NFMS bit based on mtd->writesize */ + if (mtd->writesize == 2048) { + NFMS |= (1 << NFMS_BIT); + is2k_Pagesize = 1; + } else { + if ((NFMS >> NFMS_BIT) & 0x1) { /* This case strangly happened on MXC91321 P1.2.2 */ + printk(KERN_INFO + "Oops... NFMS Bit set for 512B Page, resetting it. [RCSR: 0x%08x]\n", + NFMS); + NFMS &= ~(1 << NFMS_BIT); + } + is2k_Pagesize = 0; + } + + if (is2k_Pagesize) + this->ecc.layout = &nand_hw_eccoob_2k; + + /* jffs2 not write oob */ + mtd->flags &= ~MTD_OOB_WRITEABLE; + + /* use flash based bbt */ + this->bbt_td = &bbt_main_descr; + this->bbt_md = &bbt_mirror_descr; + + /* update flash based bbt */ + this->options |= NAND_USE_FLASH_BBT; + + if (!this->badblock_pattern) { + if (mtd->writesize == 2048) + this->badblock_pattern = &smallpage_memorybased; + else + this->badblock_pattern = (mtd->writesize > 512) ? + &largepage_memorybased : &smallpage_memorybased; + } + /* Build bad block table */ + return nand_scan_bbt(mtd, this->badblock_pattern); +} + +#ifdef CONFIG_MXC_NAND_LOW_LEVEL_ERASE +static void mxc_low_erase(struct mtd_info *mtd) +{ + + struct nand_chip *this = mtd->priv; + unsigned int page_addr, addr; + u_char status; + + DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : mxc_low_erase:Erasing NAND\n"); + for (addr = 0; addr < this->chipsize; addr += mtd->erasesize) { + page_addr = addr / mtd->writesize; + mxc_nand_command(mtd, NAND_CMD_ERASE1, -1, page_addr); + mxc_nand_command(mtd, NAND_CMD_ERASE2, -1, -1); + mxc_nand_command(mtd, NAND_CMD_STATUS, -1, -1); + status = mxc_nand_read_byte(mtd); + if (status & NAND_STATUS_FAIL) { + printk(KERN_ERR + "ERASE FAILED(block = %d,status = 0x%x)\n", + addr / mtd->erasesize, status); + } + } + +} +#endif +/*! + * This function is called during the driver binding process. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and + * remove functions + * + * @return The function always returns 0. + */ +static int __init mxcnd_probe(struct platform_device *pdev) +{ + struct nand_chip *this; + struct mtd_info *mtd; + struct flash_platform_data *flash = pdev->dev.platform_data; + int nr_parts = 0; + + int err = 0; + /* Allocate memory for MTD device structure and private data */ + mxc_nand_data = kzalloc(sizeof(struct mxc_mtd_s), GFP_KERNEL); + if (!mxc_nand_data) { + printk(KERN_ERR "%s: failed to allocate mtd_info\n", + __FUNCTION__); + err = -ENOMEM; + goto out; + } + memset((char *)&g_nandfc_info, 0, sizeof(g_nandfc_info)); + + mxc_nand_data->dev = &pdev->dev; + /* structures must be linked */ + this = &mxc_nand_data->nand; + mtd = &mxc_nand_data->mtd; + mtd->priv = this; + mtd->owner = THIS_MODULE; + + /* 50 us command delay time */ + this->chip_delay = 5; + + this->priv = mxc_nand_data; + this->dev_ready = mxc_nand_dev_ready; + this->cmdfunc = mxc_nand_command; + this->select_chip = mxc_nand_select_chip; + this->read_byte = mxc_nand_read_byte; + this->read_word = mxc_nand_read_word; + this->write_buf = mxc_nand_write_buf; + this->read_buf = mxc_nand_read_buf; + this->verify_buf = mxc_nand_verify_buf; + this->scan_bbt = mxc_nand_scan_bbt; + + nfc_clk = clk_get(&pdev->dev, "nfc_clk"); + clk_enable(nfc_clk); + + NFC_CONFIG1 |= NFC_INT_MSK; + init_waitqueue_head(&irq_waitq); + err = request_irq(MXC_INT_NANDFC, mxc_nfc_irq, 0, "mxc_nd", NULL); + if (err) { + goto out_1; + } + + if (hardware_ecc) { + this->ecc.calculate = mxc_nand_calculate_ecc; + this->ecc.hwctl = mxc_nand_enable_hwecc; + this->ecc.correct = mxc_nand_correct_data; + this->ecc.mode = NAND_ECC_HW; + this->ecc.size = 512; + this->ecc.bytes = 3; + this->ecc.layout = &nand_hw_eccoob_8; + NFC_CONFIG1 |= NFC_ECC_EN; + } else { + this->ecc.mode = NAND_ECC_SOFT; + } + + /* Reset NAND */ + this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + + /* preset operation */ + /* Unlock the internal RAM Buffer */ + NFC_CONFIG = 0x2; + + /* Blocks to be unlocked */ + NFC_UNLOCKSTART_BLKADDR = 0x0; + NFC_UNLOCKEND_BLKADDR = 0x4000; + + /* Unlock Block Command for given address range */ + NFC_WRPROT = 0x4; + + /* NAND bus width determines access funtions used by upper layer */ + if (flash->width == 2) { + this->options |= NAND_BUSWIDTH_16; + this->ecc.layout = &nand_hw_eccoob_16; + } else { + this->options |= 0; + } + + is2k_Pagesize = 0; + + /* Scan to find existence of the device */ + if (nand_scan(mtd, 1)) { + DEBUG(MTD_DEBUG_LEVEL0, + "MXC_ND: Unable to find any NAND device.\n"); + err = -ENXIO; + goto out_1; + } + + /* Register the partitions */ +#ifdef CONFIG_MTD_PARTITIONS + nr_parts = + parse_mtd_partitions(mtd, part_probes, &mxc_nand_data->parts, 0); + if (nr_parts > 0) + add_mtd_partitions(mtd, mxc_nand_data->parts, nr_parts); + else if (flash->parts) + add_mtd_partitions(mtd, flash->parts, flash->nr_parts); + else +#endif + { + pr_info("Registering %s as whole device\n", mtd->name); + add_mtd_device(mtd); + } +#ifdef CONFIG_MXC_NAND_LOW_LEVEL_ERASE + /* Erase all the blocks of a NAND */ + mxc_low_erase(mtd); +#endif + + platform_set_drvdata(pdev, mtd); + return 0; + + out_1: + kfree(mxc_nand_data); + out: + return err; + +} + + /*! + * Dissociates the driver from the device. + * + * @param pdev the device structure used to give information on which + * + * @return The function always returns 0. + */ + +static int __exit mxcnd_remove(struct platform_device *pdev) +{ + struct mtd_info *mtd = platform_get_drvdata(pdev); + + clk_put(nfc_clk); + platform_set_drvdata(pdev, NULL); + + if (mxc_nand_data) { + nand_release(mtd); + free_irq(MXC_INT_NANDFC, NULL); + kfree(mxc_nand_data); + } + + return 0; +} + +#ifdef CONFIG_PM +/*! + * This function is called to put the NAND in a low power state. Refer to the + * document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device information structure + * + * @param state the power state the device is entering + * + * @return The function returns 0 on success and -1 on failure + */ + +static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct mtd_info *info = platform_get_drvdata(pdev); + int ret = 0; + + DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n"); + if (info) + ret = info->suspend(info); + + /* Disable the NFC clock */ + clk_disable(nfc_clk); + + return ret; +} + +/*! + * This function is called to bring the NAND back from a low power state. Refer + * to the document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device information structure + * + * @return The function returns 0 on success and -1 on failure + */ +static int mxcnd_resume(struct platform_device *pdev) +{ + struct mtd_info *info = platform_get_drvdata(pdev); + int ret = 0; + + DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n"); + /* Enable the NFC clock */ + clk_enable(nfc_clk); + + if (info) { + info->resume(info); + } + + return ret; +} + +#else +#define mxcnd_suspend NULL +#define mxcnd_resume NULL +#endif /* CONFIG_PM */ + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxcnd_driver = { + .driver = { + .name = "mxc_nand_flash", + }, + .probe = mxcnd_probe, + .remove = __exit_p(mxcnd_remove), + .suspend = mxcnd_suspend, + .resume = mxcnd_resume, +}; + +/*! + * Main initialization routine + * @return 0 if successful; non-zero otherwise + */ +static int __init mxc_nd_init(void) +{ + /* Register the device driver structure. */ + pr_info("MXC MTD nand Driver %s\n", DVR_VER); + if (platform_driver_register(&mxcnd_driver) != 0) { + printk(KERN_ERR "Driver register failed for mxcnd_driver\n"); + return -ENODEV; + } + return 0; +} + +/*! + * Clean up routine + */ +static void __exit mxc_nd_cleanup(void) +{ + /* Unregister the device structure */ + platform_driver_unregister(&mxcnd_driver); +} + +module_init(mxc_nd_init); +module_exit(mxc_nd_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC NAND MTD driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mtd/nand/mxc_nd.h linux-2.6.26-lab126/drivers/mtd/nand/mxc_nd.h --- linux-2.6.26/drivers/mtd/nand/mxc_nd.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mtd/nand/mxc_nd.h 2010-08-10 04:15:32.000000000 -0400 @@ -0,0 +1,112 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_nd.h + * + * @brief This file contains the NAND Flash Controller register information. + * + * + * @ingroup NAND_MTD + */ + +#ifndef __MXC_ND_H__ +#define __MXC_ND_H__ + +#include + +/* + * Addresses for NFC registers + */ +#define NFC_BUF_SIZE (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE00))) +#define NFC_BUF_ADDR (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE04))) +#define NFC_FLASH_ADDR (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE06))) +#define NFC_FLASH_CMD (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE08))) +#define NFC_CONFIG (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE0A))) +#define NFC_ECC_STATUS_RESULT (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE0C))) +#define NFC_RSLTMAIN_AREA (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE0E))) +#define NFC_RSLTSPARE_AREA (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE10))) +#define NFC_WRPROT (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE12))) +#define NFC_UNLOCKSTART_BLKADDR (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE14))) +#define NFC_UNLOCKEND_BLKADDR (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE16))) +#define NFC_NF_WRPRST (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE18))) +#define NFC_CONFIG1 (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE1A))) +#define NFC_CONFIG2 (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE1C))) + +/*! + * Addresses for NFC RAM BUFFER Main area 0 + */ +#define MAIN_AREA0 (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x000) +#define MAIN_AREA1 (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x200) +#define MAIN_AREA2 (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x400) +#define MAIN_AREA3 (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x600) + +/*! + * Addresses for NFC SPARE BUFFER Spare area 0 + */ +#define SPARE_AREA0 (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x800) +#define SPARE_AREA1 (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x810) +#define SPARE_AREA2 (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x820) +#define SPARE_AREA3 (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x830) + +/*! + * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command + * operation + */ +#define NFC_CMD 0x1 + +/*! + * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address + * operation + */ +#define NFC_ADDR 0x2 + +/*! + * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input + * operation + */ +#define NFC_INPUT 0x4 + +/*! + * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data Output + * operation + */ +#define NFC_OUTPUT 0x8 + +/*! + * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID + * operation + */ +#define NFC_ID 0x10 + +/*! + * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read Status + * operation + */ +#define NFC_STATUS 0x20 + +/*! + * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status + * operation + */ +#define NFC_INT 0x8000 + +#define NFC_SP_EN (1 << 2) +#define NFC_ECC_EN (1 << 3) +#define NFC_INT_MSK (1 << 4) +#define NFC_BIG (1 << 5) +#define NFC_RST (1 << 6) +#define NFC_CE (1 << 7) +#define NFC_ONE_CYCLE (1 << 8) + +#endif /* MXCND_H */ diff -urN linux-2.6.26/drivers/mtd/nand/mxc_nd2.c linux-2.6.26-lab126/drivers/mtd/nand/mxc_nd2.c --- linux-2.6.26/drivers/mtd/nand/mxc_nd2.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mtd/nand/mxc_nd2.c 2010-08-10 04:15:32.000000000 -0400 @@ -0,0 +1,1433 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_nd2.h" + +#define DVR_VER "2.5" + +/* Global address Variables */ +static u32 nfc_axi_base, nfc_ip_base; + +struct mxc_mtd_s { + struct mtd_info mtd; + struct nand_chip nand; + struct mtd_partition *parts; + struct device *dev; +}; + +static struct mxc_mtd_s *mxc_nand_data; + +/* + * Define delays in microsec for NAND device operations + */ +#define TROP_US_DELAY 2000 + +struct nand_info { + bool bStatusRequest; + u16 colAddr; +}; + +static struct nand_info g_nandfc_info; + +#ifdef CONFIG_MTD_NAND_MXC_SWECC +static int hardware_ecc = 0; +#else +static int hardware_ecc = 1; +#endif + +static u8 num_of_interleave = 1; + +static u8 *data_buf; +static u8 *oob_buf; + +static int g_page_mask; + +static struct clk *nfc_clk; + +/* + * OOB placement block for use with hardware ecc generation + */ +static struct nand_ecclayout nand_hw_eccoob_512 = { + .eccbytes = 9, + .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15}, + .oobavail = 4, + .oobfree = {{0, 4}} +}; + +static struct nand_ecclayout nand_hw_eccoob_2k = { + .eccbytes = 9, + .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15}, + .oobavail = 4, + .oobfree = {{2, 4}} +}; + +static struct nand_ecclayout nand_hw_eccoob_4k = { + .eccbytes = 9, + .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15}, + .oobavail = 4, + .oobfree = {{2, 4}} +}; + +/*! + * @defgroup NAND_MTD NAND Flash MTD Driver for MXC processors + */ + +/*! + * @file mxc_nd2.c + * + * @brief This file contains the hardware specific layer for NAND Flash on + * MXC processor + * + * @ingroup NAND_MTD + */ + +#ifdef CONFIG_MTD_PARTITIONS +static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL }; +#endif + +static wait_queue_head_t irq_waitq; + +static irqreturn_t mxc_nfc_irq(int irq, void *dev_id) +{ + /* Disable Interuupt */ + raw_write(raw_read(REG_NFC_INTRRUPT) | NFC_INT_MSK, REG_NFC_INTRRUPT); + wake_up(&irq_waitq); + + return IRQ_HANDLED; +} + +/* + * Functions to transfer data to/from spare erea. + */ +static void +copy_spare(struct mtd_info *mtd, void *pbuf, void *pspare, int len, bool bfrom) +{ + u16 i, j; + u16 m = mtd->oobsize; + u16 n = mtd->writesize >> 9; + u8 *d = (u8 *) pbuf; + u8 *s = (u8 *) pspare; + u16 t = SPARE_LEN; + + m /= num_of_interleave; + n /= num_of_interleave; + + j = (m / n >> 1) << 1; + + if (bfrom) { + for (i = 0; i < n - 1; i++) + memcpy(&d[i * j], &s[i * t], j); + + /* the last section */ + memcpy(&d[i * j], &s[i * t], len - i * j); + } else { + for (i = 0; i < n - 1; i++) + memcpy(&s[i * t], &d[i * j], j); + + /* the last section */ + memcpy(&s[i * t], &d[i * j], len - i * j); + } +} + +/*! + * This function polls the NFC to wait for the basic operation to complete by + * checking the INT bit of config2 register. + * + * @param maxRetries number of retry attempts (separated by 1 us) + * @param useirq True if IRQ should be used rather than polling + */ +static void wait_op_done(int maxRetries, bool useirq) +{ + if (useirq) { + if ((raw_read(REG_NFC_OPS_STAT) & NFC_OPS_STAT) == 0) { + /* Enable Interuupt */ + raw_write(raw_read(REG_NFC_INTRRUPT) & ~NFC_INT_MSK, + REG_NFC_INTRRUPT); + wait_event(irq_waitq, + (raw_read(REG_NFC_OPS_STAT) & NFC_OPS_STAT)); + } + WRITE_NFC_IP_REG((raw_read(REG_NFC_OPS_STAT) & + ~NFC_OPS_STAT), REG_NFC_OPS_STAT); + } else { + while (1) { + maxRetries--; + if (raw_read(REG_NFC_OPS_STAT) & NFC_OPS_STAT) { + WRITE_NFC_IP_REG((raw_read(REG_NFC_OPS_STAT) & + ~NFC_OPS_STAT), + REG_NFC_OPS_STAT); + break; + } + udelay(1); + if (maxRetries <= 0) { + DEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n", + __func__, __LINE__); + } + } + } +} + +static inline void send_atomic_cmd(u16 cmd, bool useirq) +{ + /* fill command */ + raw_write(cmd, REG_NFC_FLASH_CMD); + + /* clear status */ + ACK_OPS; + + /* send out command */ + raw_write(NFC_CMD, REG_NFC_OPS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, useirq); +} + +static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr); +static int mxc_check_ecc_status(struct mtd_info *mtd); + +#ifdef NFC_AUTO_MODE_ENABLE +/*! + * This function handle the interleave related work + * @param mtd mtd info + * @param cmd command + */ +static void auto_cmd_interleave(struct mtd_info *mtd, u16 cmd) +{ + u32 i; + u32 j = num_of_interleave; + struct nand_chip *this = mtd->priv; + u32 addr_low = raw_read(NFC_FLASH_ADDR0); + u32 addr_high = raw_read(NFC_FLASH_ADDR8); + u32 page_addr = addr_low >> 16 | addr_high << 16; + u8 *dbuf = data_buf; + u8 *obuf = oob_buf; + u32 dlen = mtd->writesize / j; + u32 olen = mtd->oobsize / j; + + /* adjust the addr value + * since ADD_OP mode is 01 + */ + if (j > 1) + page_addr *= j; + else + page_addr *= this->numchips; + + switch (cmd) { + case NAND_CMD_PAGEPROG: + for (i = 0; i < j; i++) { + /* reset addr cycle */ + if (j > 1) + mxc_do_addr_cycle(mtd, 0, page_addr++); + + /* data transfer */ + memcpy(MAIN_AREA0, dbuf, dlen); + copy_spare(mtd, obuf, SPARE_AREA0, olen, false); + + /* update the value */ + dbuf += dlen; + obuf += olen; + + NFC_SET_RBA(0); + ACK_OPS; + raw_write(NFC_AUTO_PROG, REG_NFC_OPS); + + /* wait auto_prog_done bit set */ + while (!(raw_read(REG_NFC_OPS_STAT) & NFC_OP_DONE)) ; + } + + wait_op_done(TROP_US_DELAY, false); + while (!(raw_read(REG_NFC_OPS_STAT) & NFC_RB)) ; + + break; + case NAND_CMD_READSTART: + for (i = 0; i < j; i++) { + /* reset addr cycle */ + if (j > 1) + mxc_do_addr_cycle(mtd, 0, page_addr++); + + NFC_SET_RBA(0); + ACK_OPS; + raw_write(NFC_AUTO_READ, REG_NFC_OPS); + wait_op_done(TROP_US_DELAY, false); + + /* check ecc error */ + mxc_check_ecc_status(mtd); + + /* data transfer */ + memcpy(dbuf, MAIN_AREA0, dlen); + copy_spare(mtd, obuf, SPARE_AREA0, olen, true); + + /* update the value */ + dbuf += dlen; + obuf += olen; + } + break; + case NAND_CMD_ERASE2: + for (i = 0; i < j; i++) { + if (!i) { + page_addr = addr_low; + page_addr *= (j > 1 ? j : this->numchips); + } + mxc_do_addr_cycle(mtd, -1, page_addr++); + ACK_OPS; + raw_write(NFC_AUTO_ERASE, REG_NFC_OPS); + wait_op_done(TROP_US_DELAY, true); + } + break; + case NAND_CMD_RESET: + for (i = 0; i < j; i++) { + if (j > 1) + NFC_SET_NFC_ACTIVE_CS(i); + send_atomic_cmd(cmd, false); + } + break; + default: + break; + } +} +#endif + +static void send_addr(u16 addr, bool useirq); + +/*! + * This function issues the specified command to the NAND device and + * waits for completion. + * + * @param cmd command for NAND Flash + * @param useirq True if IRQ should be used rather than polling + */ +static void send_cmd(struct mtd_info *mtd, u16 cmd, bool useirq) +{ + DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(0x%x, %d)\n", cmd, useirq); + +#ifdef NFC_AUTO_MODE_ENABLE + switch (cmd) { + case NAND_CMD_READ0: + case NAND_CMD_READOOB: + raw_write(NAND_CMD_READ0, REG_NFC_FLASH_CMD); + break; + case NAND_CMD_SEQIN: + case NAND_CMD_ERASE1: + raw_write(cmd, REG_NFC_FLASH_CMD); + break; + case NAND_CMD_PAGEPROG: + case NAND_CMD_ERASE2: + case NAND_CMD_READSTART: + raw_write(raw_read(REG_NFC_FLASH_CMD) | cmd << NFC_CMD_1_SHIFT, + REG_NFC_FLASH_CMD); + auto_cmd_interleave(mtd, cmd); + break; + case NAND_CMD_READID: + send_atomic_cmd(cmd, useirq); + send_addr(0, false); + break; + case NAND_CMD_RESET: + auto_cmd_interleave(mtd, cmd); + case NAND_CMD_STATUS: + break; + default: + break; + } +#else + send_atomic_cmd(cmd, useirq); +#endif +} + +/*! + * This function sends an address (or partial address) to the + * NAND device. The address is used to select the source/destination for + * a NAND command. + * + * @param addr address to be written to NFC. + * @param useirq True if IRQ should be used rather than polling + */ +static void send_addr(u16 addr, bool useirq) +{ + DEBUG(MTD_DEBUG_LEVEL3, "send_addr(0x%x %d)\n", addr, useirq); + + /* fill address */ + raw_write((addr << NFC_FLASH_ADDR_SHIFT), REG_NFC_FLASH_ADDR); + + /* clear status */ + ACK_OPS; + + /* send out address */ + raw_write(NFC_ADDR, REG_NFC_OPS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, useirq); +} + +/*! + * This function requests the NFC to initate the transfer + * of data currently in the NFC RAM buffer to the NAND device. + * + * @param buf_id Specify Internal RAM Buffer number + */ +static void send_prog_page(u8 buf_id) +{ +#ifndef NFC_AUTO_MODE_ENABLE + DEBUG(MTD_DEBUG_LEVEL3, "%s\n", __FUNCTION__); + + /* set ram buffer id */ + NFC_SET_RBA(buf_id); + + /* clear status */ + ACK_OPS; + + /* transfer data from NFC ram to nand */ + raw_write(NFC_INPUT, REG_NFC_OPS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, false); +#endif +} + +/*! + * This function requests the NFC to initated the transfer + * of data from the NAND device into in the NFC ram buffer. + * + * @param buf_id Specify Internal RAM Buffer number + */ +static void send_read_page(u8 buf_id) +{ +#ifndef NFC_AUTO_MODE_ENABLE + DEBUG(MTD_DEBUG_LEVEL3, "%s(%d)\n", __FUNCTION__, buf_id); + + /* set ram buffer id */ + NFC_SET_RBA(buf_id); + + /* clear status */ + ACK_OPS; + + /* transfer data from nand to NFC ram */ + raw_write(NFC_OUTPUT, REG_NFC_OPS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, false); +#endif +} + +/*! + * This function requests the NFC to perform a read of the + * NAND device ID. + */ +static void send_read_id(void) +{ + /* Set RBA bits for BUFFER0 */ + NFC_SET_RBA(0); + + /* clear status */ + ACK_OPS; + + /* Read ID into main buffer */ + raw_write(NFC_ID, REG_NFC_OPS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, false); + +} + +#ifdef NFC_AUTO_MODE_ENABLE +static inline void read_dev_status(u16 *status) +{ + u32 mask = 0xFF << 16; + + /* clear status */ + ACK_OPS; + + do { + /* send auto read status command */ + raw_write(NFC_AUTO_STATE, REG_NFC_OPS); + if (cpu_is_mx51_rev(CHIP_REV_2_0) == 1) + wait_op_done(TROP_US_DELAY, false); + *status = (raw_read(NFC_CONFIG1) & mask) >> 16; + } while ((*status & NAND_STATUS_READY) == 0); +} +#endif + +/*! + * This function requests the NFC to perform a read of the + * NAND device status and returns the current status. + * + * @return device status + */ +static u16 get_dev_status(void) +{ +#ifdef NFC_AUTO_MODE_ENABLE + int i; + u16 status = 0; + for (i = 0; i < num_of_interleave; i++) { + + /* set ative cs */ + NFC_SET_NFC_ACTIVE_CS(i); + + /* FIXME, NFC Auto erase may have + * problem, have to pollingit until + * the nand get idle, otherwise + * it may get error + */ + read_dev_status(&status); + if (status & NAND_STATUS_FAIL) + break; + } + + return status; +#else + volatile u16 *mainBuf = MAIN_AREA1; + u8 val = 1; + u16 ret; + + /* Set ram buffer id */ + NFC_SET_RBA(val); + + /* clear status */ + ACK_OPS; + + /* Read status into main buffer */ + raw_write(NFC_STATUS, REG_NFC_OPS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, false); + + /* Status is placed in first word of main buffer */ + /* get status, then recovery area 1 data */ + ret = *mainBuf; + + return ret; +#endif +} + +static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) +{ + raw_write((raw_read(REG_NFC_ECC_EN) | NFC_ECC_EN), REG_NFC_ECC_EN); + return; +} + +/* + * Function to record the ECC corrected/uncorrected errors resulted + * after a page read. This NFC detects and corrects upto to 4 symbols + * of 9-bits each. + */ +static int mxc_check_ecc_status(struct mtd_info *mtd) +{ + u32 ecc_stat, err; + int no_subpages = 1; + int ret = 0; + u8 ecc_bit_mask, err_limit; + + ecc_bit_mask = (IS_4BIT_ECC ? 0x7 : 0xf); + err_limit = (IS_4BIT_ECC ? 0x4 : 0x8); + + no_subpages = mtd->writesize >> 9; + + no_subpages /= num_of_interleave; + + ecc_stat = GET_NFC_ECC_STATUS(); + do { + err = ecc_stat & ecc_bit_mask; + if (err > err_limit) { + mtd->ecc_stats.failed++; + printk(KERN_WARNING "UnCorrectable RS-ECC Error\n"); + return -1; + } else { + ret += err; + } + ecc_stat >>= 4; + } while (--no_subpages); + + mtd->ecc_stats.corrected += ret; + pr_debug("%d Symbol Correctable RS-ECC Error\n", ret); + + return ret; +} + +/* + * Function to correct the detected errors. This NFC corrects all the errors + * detected. So this function just return 0. + */ +static int mxc_nand_correct_data(struct mtd_info *mtd, u_char * dat, + u_char * read_ecc, u_char * calc_ecc) +{ + return 0; +} + +/* + * Function to calculate the ECC for the data to be stored in the Nand device. + * This NFC has a hardware RS(511,503) ECC engine together with the RS ECC + * CONTROL blocks are responsible for detection and correction of up to + * 8 symbols of 9 bits each in 528 byte page. + * So this function is just return 0. + */ + +static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char * dat, + u_char * ecc_code) +{ + return 0; +} + +/*! + * This function id is used to read the data buffer from the NAND Flash. To + * read the data from NAND Flash first the data output cycle is initiated by + * the NFC, which copies the data to RAMbuffer. This data of length \b len is + * then copied to buffer \b buf. + * + * @param mtd MTD structure for the NAND Flash + * @param buf data to be read from NAND Flash + * @param len number of bytes to be read + */ +static void mxc_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len) +{ + u16 col = g_nandfc_info.colAddr; + + if (mtd->writesize) { + + int j = mtd->writesize - col; + int n = mtd->oobsize + j; + + n = min(n, len); + + if (j > 0) { + if (n > j) { + memcpy(buf, &data_buf[col], j); + memcpy(buf + j, &oob_buf[0], n - j); + } else { + memcpy(buf, &data_buf[col], n); + } + } else { + col -= mtd->writesize; + memcpy(buf, &oob_buf[col], len); + } + + /* update */ + g_nandfc_info.colAddr += n; + + } else { + /* At flash identify phase, + * mtd->writesize has not been + * set correctly, it should + * be zero.And len will less 2 + */ + memcpy(buf, &data_buf[col], len); + + /* update */ + g_nandfc_info.colAddr += len; + } + +} + +/*! + * This function reads byte from the NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static uint8_t mxc_nand_read_byte(struct mtd_info *mtd) +{ + uint8_t ret; + + /* Check for status request */ + if (g_nandfc_info.bStatusRequest) { + return (get_dev_status() & 0xFF); + } + + mxc_nand_read_buf(mtd, &ret, 1); + + return ret; +} + +/*! + * This function reads word from the NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u16 mxc_nand_read_word(struct mtd_info *mtd) +{ + u16 ret; + + mxc_nand_read_buf(mtd, (uint8_t *) &ret, sizeof(u16)); + + return ret; +} + +/*! + * This function reads byte from the NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u_char mxc_nand_read_byte16(struct mtd_info *mtd) +{ + /* Check for status request */ + if (g_nandfc_info.bStatusRequest) { + return (get_dev_status() & 0xFF); + } + + return mxc_nand_read_word(mtd) & 0xFF; +} + +/*! + * This function writes data of length \b len from buffer \b buf to the NAND + * internal RAM buffer's MAIN area 0. + * + * @param mtd MTD structure for the NAND Flash + * @param buf data to be written to NAND Flash + * @param len number of bytes to be written + */ +static void mxc_nand_write_buf(struct mtd_info *mtd, + const u_char * buf, int len) +{ + u16 col = g_nandfc_info.colAddr; + int j = mtd->writesize - col; + int n = mtd->oobsize + j; + + n = min(n, len); + + if (j > 0) { + if (n > j) { + memcpy(&data_buf[col], buf, j); + memcpy(&oob_buf[0], buf + j, n - j); + } else { + memcpy(&data_buf[col], buf, n); + } + } else { + col -= mtd->writesize; + memcpy(&oob_buf[col], buf, len); + } + + /* update */ + g_nandfc_info.colAddr += n; +} + +/*! + * This function is used by the upper layer to verify the data in NAND Flash + * with the data in the \b buf. + * + * @param mtd MTD structure for the NAND Flash + * @param buf data to be verified + * @param len length of the data to be verified + * + * @return -EFAULT if error else 0 + * + */ +static int mxc_nand_verify_buf(struct mtd_info *mtd, const u_char * buf, + int len) +{ + u_char *s = data_buf; + + const u_char *p = buf; + + for (; len > 0; len--) { + if (*p++ != *s++) + return -EFAULT; + } + + return 0; +} + +/*! + * This function is used by upper layer for select and deselect of the NAND + * chip + * + * @param mtd MTD structure for the NAND Flash + * @param chip val indicating select or deselect + */ +static void mxc_nand_select_chip(struct mtd_info *mtd, int chip) +{ + + switch (chip) { + case -1: + /* Disable the NFC clock */ + clk_disable(nfc_clk); + break; + case 0 ... 7: + /* Enable the NFC clock */ + clk_enable(nfc_clk); + + NFC_SET_NFC_ACTIVE_CS(chip); + break; + + default: + break; + } +} + +/* + * Function to perform the address cycles. + */ +static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr) +{ +#ifdef NFC_AUTO_MODE_ENABLE + + if (page_addr != -1 && column != -1) { + u32 mask = 0xFFFF; + /* the column address */ + raw_write(column & mask, NFC_FLASH_ADDR0); + raw_write((raw_read(NFC_FLASH_ADDR0) | + ((page_addr & mask) << 16)), NFC_FLASH_ADDR0); + /* the row address */ + raw_write(((raw_read(NFC_FLASH_ADDR8) & (mask << 16)) | + ((page_addr & (mask << 16)) >> 16)), + NFC_FLASH_ADDR8); + } else if (page_addr != -1) { + raw_write(page_addr, NFC_FLASH_ADDR0); + } + + DEBUG(MTD_DEBUG_LEVEL3, + "AutoMode:the ADDR REGS value is (0x%x, 0x%x)\n", + raw_read(NFC_FLASH_ADDR0), raw_read(NFC_FLASH_ADDR8)); +#else + + u32 page_mask = g_page_mask; + + if (column != -1) { + send_addr(column & 0xFF, false); + if (IS_2K_PAGE_NAND) { + /* another col addr cycle for 2k page */ + send_addr((column >> 8) & 0xF, false); + } else if (IS_4K_PAGE_NAND) { + /* another col addr cycle for 4k page */ + send_addr((column >> 8) & 0x1F, false); + } + } + if (page_addr != -1) { + do { + send_addr((page_addr & 0xff), false); + page_mask >>= 8; + page_addr >>= 8; + } while (page_mask != 0); + } +#endif +} + +/*! + * This function is used by the upper layer to write command to NAND Flash for + * different operations to be carried out on NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * @param command command for NAND Flash + * @param column column offset for the page read + * @param page_addr page to be read from NAND Flash + */ +static void mxc_nand_command(struct mtd_info *mtd, unsigned command, + int column, int page_addr) +{ + bool useirq = false; + + DEBUG(MTD_DEBUG_LEVEL3, + "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", + command, column, page_addr); + /* + * Reset command state information + */ + g_nandfc_info.bStatusRequest = false; + + /* + * Command pre-processing step + */ + switch (command) { + case NAND_CMD_STATUS: + g_nandfc_info.colAddr = 0; + g_nandfc_info.bStatusRequest = true; + break; + + case NAND_CMD_READ0: + g_nandfc_info.colAddr = column; + break; + + case NAND_CMD_READOOB: + g_nandfc_info.colAddr = column; + command = NAND_CMD_READ0; + break; + + case NAND_CMD_SEQIN: + if (column != 0) { + + /* FIXME: before send SEQIN command for + * partial write,We need read one page out. + * FSL NFC does not support partial write + * It alway send out 512+ecc+512+ecc ... + * for large page nand flash. But for small + * page nand flash, it did support SPARE + * ONLY operation. But to make driver + * simple. We take the same as large page,read + * whole page out and update. As for MLC nand + * NOP(num of operation) = 1. Partial written + * on one programed page is not allowed! We + * can't limit it on the driver, it need the + * upper layer applicaiton take care it + */ + + mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr); + } + + g_nandfc_info.colAddr = column; + break; + + case NAND_CMD_PAGEPROG: +#ifndef NFC_AUTO_MODE_ENABLE + /* FIXME:the NFC interal buffer + * access has some limitation, it + * does not allow byte access. To + * make the code simple and ease use + * not every time check the address + * alignment.Use the temp buffer + * to accomadate the data.since We + * know data_buf will be at leat 4 + * byte alignment, so we can use + * memcpy safely + */ + memcpy(MAIN_AREA0, data_buf, mtd->writesize); + copy_spare(mtd, oob_buf, SPARE_AREA0, mtd->oobsize, false); +#endif + + if (IS_LARGE_PAGE_NAND) + PROG_PAGE(); + else + send_prog_page(0); + + useirq = true; + + break; + + case NAND_CMD_ERASE1: + break; + case NAND_CMD_ERASE2: + useirq = true; + + break; + } + + /* + * Write out the command to the device. + */ + send_cmd(mtd, command, useirq); + + mxc_do_addr_cycle(mtd, column, page_addr); + + /* + * Command post-processing step + */ + switch (command) { + + case NAND_CMD_READOOB: + case NAND_CMD_READ0: + if (IS_LARGE_PAGE_NAND) { + /* send read confirm command */ + send_cmd(mtd, NAND_CMD_READSTART, false); + /* read for each AREA */ + READ_PAGE(); + } else { + send_read_page(0); + } + +#ifndef NFC_AUTO_MODE_ENABLE + /* FIXME, the NFC interal buffer + * access has some limitation, it + * does not allow byte access. To + * make the code simple and ease use + * not every time check the address + * alignment.Use the temp buffer + * to accomadate the data.since We + * know data_buf will be at leat 4 + * byte alignment, so we can use + * memcpy safely + */ + memcpy(data_buf, MAIN_AREA0, mtd->writesize); + copy_spare(mtd, oob_buf, SPARE_AREA0, mtd->oobsize, true); +#endif + + break; + + case NAND_CMD_READID: + send_read_id(); + g_nandfc_info.colAddr = column; + memcpy(data_buf, MAIN_AREA0, 2048); + + break; + } +} + +static int mxc_nand_read_oob(struct mtd_info *mtd, + struct nand_chip *chip, int page, int sndcmd) +{ + if (sndcmd) { + + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); + sndcmd = 0; + } + + memcpy(chip->oob_poi, oob_buf, mtd->oobsize); + + return sndcmd; +} + +static int mxc_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t * buf) +{ + +#ifndef NFC_AUTO_MODE_ENABLE + mxc_check_ecc_status(mtd); +#endif + + memcpy(buf, data_buf, mtd->writesize); + memcpy(chip->oob_poi, oob_buf, mtd->oobsize); + + return 0; +} + +static void mxc_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t * buf) +{ + memcpy(data_buf, buf, mtd->writesize); + memcpy(oob_buf, chip->oob_poi, mtd->oobsize); + +} + +/* Define some generic bad / good block scan pattern which are used + * while scanning a device for factory marked good / bad blocks. */ +static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; + +static struct nand_bbt_descr smallpage_memorybased = { + .options = NAND_BBT_SCAN2NDPAGE, + .offs = 5, + .len = 1, + .pattern = scan_ff_pattern +}; + +static struct nand_bbt_descr largepage_memorybased = { + .options = 0, + .offs = 0, + .len = 2, + .pattern = scan_ff_pattern +}; + +/* Generic flash bbt decriptors +*/ +static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; +static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = bbt_pattern +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = mirror_pattern +}; + +static int mxc_nand_scan_bbt(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + + g_page_mask = this->pagemask; + + if (IS_2K_PAGE_NAND) { + NFC_SET_NFMS(1 << NFMS_NF_PG_SZ); + this->ecc.layout = &nand_hw_eccoob_2k; + } else if (IS_4K_PAGE_NAND) { + NFC_SET_NFMS(1 << NFMS_NF_PG_SZ); + this->ecc.layout = &nand_hw_eccoob_4k; + } else { + this->ecc.layout = &nand_hw_eccoob_512; + } + + /* reconfig for interleave mode */ +#ifdef NFC_AUTO_MODE_ENABLE + if (this->numchips > 1) { + num_of_interleave = this->numchips; + this->numchips = 1; + + /* FIXEME:need remove it + * when kernel support + * 4G larger space + */ + mtd->size = this->chipsize; + mtd->erasesize *= num_of_interleave; + mtd->writesize *= num_of_interleave; + mtd->oobsize *= num_of_interleave; + this->page_shift = ffs(mtd->writesize) - 1; + this->bbt_erase_shift = + this->phys_erase_shift = ffs(mtd->erasesize) - 1; + this->chip_shift = ffs(this->chipsize) - 1; + this->oob_poi = this->buffers->databuf + mtd->writesize; + } +#endif + /* propagate ecc.layout to mtd_info */ + mtd->ecclayout = this->ecc.layout; + + /* jffs2 not write oob */ + mtd->flags &= ~MTD_OOB_WRITEABLE; + + /* use flash based bbt */ + this->bbt_td = &bbt_main_descr; + this->bbt_md = &bbt_mirror_descr; + + /* update flash based bbt */ + this->options |= NAND_USE_FLASH_BBT; + + if (!this->badblock_pattern) { + this->badblock_pattern = (mtd->writesize > 512) ? + &largepage_memorybased : &smallpage_memorybased; + } + + /* Build bad block table */ + return nand_scan_bbt(mtd, this->badblock_pattern); +} + +static void mxc_nfc_init(void) +{ + /* Disable interrupt */ + raw_write((raw_read(REG_NFC_INTRRUPT) | NFC_INT_MSK), REG_NFC_INTRRUPT); + + /* disable spare enable */ + raw_write(raw_read(REG_NFC_SP_EN) & ~NFC_SP_EN, REG_NFC_SP_EN); + + /* Unlock the internal RAM Buffer */ + raw_write(NFC_SET_BLS(NFC_BLS_UNLCOKED), REG_NFC_BLS); + + /* Blocks to be unlocked */ + UNLOCK_ADDR(0x0, 0xFFFF); + + /* Unlock Block Command for given address range */ + raw_write(NFC_SET_WPC(NFC_WPC_UNLOCK), REG_NFC_WPC); + + /* Enable symetric mode by default except mx37TO1.0 */ + if (!(cpu_is_mx37_rev(CHIP_REV_1_0) == 1)) + raw_write(raw_read(REG_NFC_ONE_CYCLE) | + NFC_ONE_CYCLE, REG_NFC_ONE_CYCLE); + +} + +static int mxc_alloc_buf(void) +{ + int err = 0; + + data_buf = kzalloc(NAND_MAX_PAGESIZE, GFP_KERNEL); + if (!data_buf) { + printk(KERN_ERR "%s: failed to allocate data_buf\n", __func__); + err = -ENOMEM; + goto out; + } + oob_buf = kzalloc(NAND_MAX_OOBSIZE, GFP_KERNEL); + if (!oob_buf) { + printk(KERN_ERR "%s: failed to allocate oob_buf\n", __func__); + err = -ENOMEM; + goto out; + } + + out: + return err; +} + +static void mxc_free_buf(void) +{ + kfree(data_buf); + kfree(oob_buf); +} + +/*! + * This function is called during the driver binding process. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and + * remove functions + * + * @return The function always returns 0. + */ +static int __init mxcnd_probe(struct platform_device *pdev) +{ + struct nand_chip *this; + struct mtd_info *mtd; + struct flash_platform_data *flash = pdev->dev.platform_data; + int nr_parts = 0, err = 0; + + nfc_axi_base = IO_ADDRESS(NFC_AXI_BASE_ADDR); + nfc_ip_base = IO_ADDRESS(NFC_BASE_ADDR); + + /* init the nfc */ + mxc_nfc_init(); + + /* init data buf */ + if (mxc_alloc_buf()) + goto out; + + /* Allocate memory for MTD device structure and private data */ + mxc_nand_data = kzalloc(sizeof(struct mxc_mtd_s), GFP_KERNEL); + if (!mxc_nand_data) { + printk(KERN_ERR "%s: failed to allocate mtd_info\n", + __FUNCTION__); + err = -ENOMEM; + goto out; + } + + memset((char *)&g_nandfc_info, 0, sizeof(g_nandfc_info)); + + mxc_nand_data->dev = &pdev->dev; + /* structures must be linked */ + this = &mxc_nand_data->nand; + mtd = &mxc_nand_data->mtd; + mtd->priv = this; + mtd->owner = THIS_MODULE; + + this->priv = mxc_nand_data; + this->cmdfunc = mxc_nand_command; + this->select_chip = mxc_nand_select_chip; + this->read_byte = mxc_nand_read_byte; + this->read_word = mxc_nand_read_word; + this->write_buf = mxc_nand_write_buf; + this->read_buf = mxc_nand_read_buf; + this->verify_buf = mxc_nand_verify_buf; + this->scan_bbt = mxc_nand_scan_bbt; + + /* NAND bus width determines access funtions used by upper layer */ + if (flash->width == 2) { + this->read_byte = mxc_nand_read_byte16; + this->options |= NAND_BUSWIDTH_16; + NFC_SET_NFMS(1 << NFMS_NF_DWIDTH); + } else { + NFC_SET_NFMS(0); + } + + nfc_clk = clk_get(&pdev->dev, "nfc_clk"); + clk_enable(nfc_clk); + + init_waitqueue_head(&irq_waitq); + err = request_irq(MXC_INT_NANDFC, mxc_nfc_irq, 0, "mxc_nd", NULL); + if (err) { + goto out_1; + } + + if (hardware_ecc) { + this->ecc.read_page = mxc_nand_read_page; + this->ecc.write_page = mxc_nand_write_page; + this->ecc.read_oob = mxc_nand_read_oob; + this->ecc.layout = &nand_hw_eccoob_512; + this->ecc.calculate = mxc_nand_calculate_ecc; + this->ecc.hwctl = mxc_nand_enable_hwecc; + this->ecc.correct = mxc_nand_correct_data; + this->ecc.mode = NAND_ECC_HW; + this->ecc.size = 512; + this->ecc.bytes = 9; + raw_write((raw_read(REG_NFC_ECC_EN) | NFC_ECC_EN), + REG_NFC_ECC_EN); + } else { + this->ecc.mode = NAND_ECC_SOFT; + raw_write((raw_read(REG_NFC_ECC_EN) & ~NFC_ECC_EN), + REG_NFC_ECC_EN); + } + + /* config the gpio */ + if (flash->init) + flash->init(); + + /* Reset NAND */ + this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + + /* Scan to find existence of the device */ + if (nand_scan(mtd, NFC_GET_MAXCHIP_SP())) { + DEBUG(MTD_DEBUG_LEVEL0, + "MXC_ND2: Unable to find any NAND device.\n"); + err = -ENXIO; + goto out_1; + } + + /* Register the partitions */ +#ifdef CONFIG_MTD_PARTITIONS + nr_parts = + parse_mtd_partitions(mtd, part_probes, &mxc_nand_data->parts, 0); + if (nr_parts > 0) + add_mtd_partitions(mtd, mxc_nand_data->parts, nr_parts); + else if (flash->parts) + add_mtd_partitions(mtd, flash->parts, flash->nr_parts); + else +#endif + { + pr_info("Registering %s as whole device\n", mtd->name); + add_mtd_device(mtd); + } + + platform_set_drvdata(pdev, mtd); + + return 0; + + out_1: + kfree(mxc_nand_data); + out: + return err; + +} + + /*! + * Dissociates the driver from the device. + * + * @param pdev the device structure used to give information on which + * + * @return The function always returns 0. + */ + +static int __exit mxcnd_remove(struct platform_device *pdev) +{ + struct mtd_info *mtd = platform_get_drvdata(pdev); + struct flash_platform_data *flash = pdev->dev.platform_data; + + if (flash->exit) + flash->exit(); + + mxc_free_buf(); + + clk_disable(nfc_clk); + clk_put(nfc_clk); + platform_set_drvdata(pdev, NULL); + + if (mxc_nand_data) { + nand_release(mtd); + free_irq(MXC_INT_NANDFC, NULL); + kfree(mxc_nand_data); + } + + return 0; +} + +#ifdef CONFIG_PM +/*! + * This function is called to put the NAND in a low power state. Refer to the + * document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device information structure + * + * @param state the power state the device is entering + * + * @return The function returns 0 on success and -1 on failure + */ + +static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct mtd_info *info = platform_get_drvdata(pdev); + int ret = 0; + + DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND2 : NAND suspend\n"); + if (info) + ret = info->suspend(info); + + /* Disable the NFC clock */ + clk_disable(nfc_clk); + + /* Disable the NFC clock */ + clk_disable(nfc_clk); + + return ret; +} + +/*! + * This function is called to bring the NAND back from a low power state. Refer + * to the document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device information structure + * + * @return The function returns 0 on success and -1 on failure + */ +static int mxcnd_resume(struct platform_device *pdev) +{ + struct mtd_info *info = platform_get_drvdata(pdev); + int ret = 0; + + DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND2 : NAND resume\n"); + /* Enable the NFC clock */ + clk_enable(nfc_clk); + + if (info) { + info->resume(info); + } + + return ret; +} + +#else +#define mxcnd_suspend NULL +#define mxcnd_resume NULL +#endif /* CONFIG_PM */ + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxcnd_driver = { + .driver = { + .name = "mxc_nandv2_flash", + }, + .probe = mxcnd_probe, + .remove = __exit_p(mxcnd_remove), + .suspend = mxcnd_suspend, + .resume = mxcnd_resume, +}; + +/*! + * Main initialization routine + * @return 0 if successful; non-zero otherwise + */ +static int __init mxc_nd_init(void) +{ + /* Register the device driver structure. */ + pr_info("MXC MTD nand Driver %s\n", DVR_VER); + if (platform_driver_register(&mxcnd_driver) != 0) { + printk(KERN_ERR "Driver register failed for mxcnd_driver\n"); + return -ENODEV; + } + return 0; +} + +/*! + * Clean up routine + */ +static void __exit mxc_nd_cleanup(void) +{ + /* Unregister the device structure */ + platform_driver_unregister(&mxcnd_driver); +} + +module_init(mxc_nd_init); +module_exit(mxc_nd_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC NAND MTD driver Version 2-5"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mtd/nand/mxc_nd2.h linux-2.6.26-lab126/drivers/mtd/nand/mxc_nd2.h --- linux-2.6.26/drivers/mtd/nand/mxc_nd2.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mtd/nand/mxc_nd2.h 2010-08-10 04:15:32.000000000 -0400 @@ -0,0 +1,675 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_nd2.h + * + * @brief This file contains the NAND Flash Controller register information. + * + * + * @ingroup NAND_MTD + */ + +#ifndef __MXC_ND2_H__ +#define __MXC_ND2_H__ + +#include + +#define IS_2K_PAGE_NAND ((mtd->writesize / num_of_interleave) \ + == NAND_PAGESIZE_2KB) +#define IS_4K_PAGE_NAND ((mtd->writesize / num_of_interleave) \ + == NAND_PAGESIZE_4KB) +#define IS_LARGE_PAGE_NAND ((mtd->writesize / num_of_interleave) > 512) + +#define GET_NAND_OOB_SIZE (mtd->oobsize / num_of_interleave) + +#define NAND_PAGESIZE_2KB 2048 +#define NAND_PAGESIZE_4KB 4096 + +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3 +/* + * For V3 NFC registers Definition + */ +/* AXI Bus Mapped */ +#define NFC_AXI_BASE_ADDR NFC_BASE_ADDR_AXI + +#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_1) /* mx37 */ +#define MXC_INT_NANDFC MXC_INT_EMI +#define NFC_FLASH_ADDR_CMD (nfc_axi_base + 0x1E00) +#define NFC_CONFIG1 (nfc_axi_base + 0x1E04) +#define NFC_ECC_STATUS_RESULT (nfc_axi_base + 0x1E08) +#define LAUNCH_NFC (nfc_axi_base + 0x1E0c) +#define NFC_WRPROT (nfc_ip_base + 0x00) +#define NFC_WRPROT_UNLOCK_BLK_ADD0 (nfc_ip_base + 0x04) +#define NFC_CONFIG2 (nfc_ip_base + 0x14) +#define NFC_IPC (nfc_ip_base + 0x18) +#elif defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2) /* mx51 */ +#define MXC_INT_NANDFC MXC_INT_NFC +#define NFC_AUTO_MODE_ENABLE +#define NFC_FLASH_CMD (nfc_axi_base + 0x1E00) +#define NFC_FLASH_ADDR0 (nfc_axi_base + 0x1E04) +#define NFC_FLASH_ADDR8 (nfc_axi_base + 0x1E24) +#define NFC_CONFIG1 (nfc_axi_base + 0x1E34) +#define NFC_ECC_STATUS_RESULT (nfc_axi_base + 0x1E38) +#define NFC_ECC_STATUS_SUM (nfc_axi_base + 0x1E3C) +#define LAUNCH_NFC (nfc_axi_base + 0x1E40) +#define NFC_WRPROT (nfc_ip_base + 0x00) +#define NFC_WRPROT_UNLOCK_BLK_ADD0 (nfc_ip_base + 0x04) +#define NFC_CONFIG2 (nfc_ip_base + 0x24) +#define NFC_CONFIG3 (nfc_ip_base + 0x28) +#define NFC_IPC (nfc_ip_base + 0x2C) +#else /* skye */ +#define NFC_FLASH_ADDR_CMD (nfc_axi_base + 0xE00) +#define NFC_CONFIG1 (nfc_axi_base + 0xE04) +#define NFC_ECC_STATUS_RESULT (nfc_axi_base + 0xE08) +#define LAUNCH_NFC (nfc_axi_base + 0xE0C) +#define NFC_WRPROT (nfc_ip_base + 0x00) +#define NFC_WRPROT_UNLOCK_BLK_ADD0 (nfc_ip_base + 0x04) +#define NFC_CONFIG2 (nfc_ip_base + 0x14) +#define NFC_IPC (nfc_ip_base + 0x18) +#endif +/*! + * Addresses for NFC RAM BUFFER Main area 0 + */ +#define MAIN_AREA0 ((u16 *)(nfc_axi_base + 0x000)) +#define MAIN_AREA1 ((u16 *)(nfc_axi_base + 0x200)) + +/*! + * Addresses for NFC SPARE BUFFER Spare area 0 + */ +#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_1) || \ + defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2) +#define SPARE_AREA0 ((u16 *)(nfc_axi_base + 0x1000)) +#define SPARE_LEN 64 +#define SPARE_COUNT 8 +#define SPARE_SIZE (SPARE_LEN * SPARE_COUNT) +#else +#define SPARE_AREA0 ((u16 *)(nfc_axi_base + 0x800)) +#define SPARE_LEN 16 +#define SPARE_COUNT 4 +#define SPARE_SIZE (SPARE_LEN * SPARE_COUNT) +#endif + +#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_1) || \ + defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2) +#define NFC_SPAS_WIDTH 8 +#define NFC_SPAS_SHIFT 16 + +#define IS_4BIT_ECC \ +( \ + cpu_is_mx51_rev(CHIP_REV_2_0) == 1 ? \ + !((raw_read(NFC_CONFIG2) & NFC_ECC_MODE_4) >> 6) : \ + ((raw_read(NFC_CONFIG2) & NFC_ECC_MODE_4) >> 6) \ +) + +#define NFC_SET_SPAS(v) \ + raw_write((((raw_read(NFC_CONFIG2) & \ + NFC_FIELD_RESET(NFC_SPAS_WIDTH, NFC_SPAS_SHIFT)) | ((v) << 16))), \ + NFC_CONFIG2) + +#define NFC_SET_ECC_MODE(v) \ +do { \ + if (cpu_is_mx51_rev(CHIP_REV_2_0) == 1) { \ + if ((v) == NFC_SPAS_218 || (v) == NFC_SPAS_112) \ + raw_write(((raw_read(NFC_CONFIG2) & \ + NFC_ECC_MODE_MASK) | \ + NFC_ECC_MODE_4), NFC_CONFIG2); \ + else \ + raw_write(((raw_read(NFC_CONFIG2) & \ + NFC_ECC_MODE_MASK) & \ + NFC_ECC_MODE_8), NFC_CONFIG2); \ + } else { \ + if ((v) == NFC_SPAS_218 || (v) == NFC_SPAS_112) \ + raw_write(((raw_read(NFC_CONFIG2) & \ + NFC_ECC_MODE_MASK) & \ + NFC_ECC_MODE_8), NFC_CONFIG2); \ + else \ + raw_write(((raw_read(NFC_CONFIG2) & \ + NFC_ECC_MODE_MASK) | \ + NFC_ECC_MODE_4), NFC_CONFIG2); \ + } \ +} while (0) + +#define WRITE_NFC_IP_REG(val,reg) \ + do { \ + raw_write(NFC_IPC_CREQ, NFC_IPC); \ + while (!((raw_read(NFC_IPC) & NFC_IPC_ACK)>>1));\ + raw_write(val, reg); \ + raw_write(0, NFC_IPC); \ + } while(0) + +#else +#define IS_4BIT_ECC 1 +#define NFC_SET_SPAS(v) +#define NFC_SET_ECC_MODE(v) +#define NFC_SET_NFMS(v) (NFMS |= (v)) + +#define WRITE_NFC_IP_REG(val,reg) \ + raw_write((raw_read(REG_NFC_OPS_STAT) & ~NFC_OPS_STAT), \ + REG_NFC_OPS_STAT) +#endif + +#define GET_NFC_ECC_STATUS() raw_read(REG_NFC_ECC_STATUS_RESULT); + +/*! + * Set 1 to specific operation bit, rest to 0 in LAUNCH_NFC Register for + * Specific operation + */ +#define NFC_CMD 0x1 +#define NFC_ADDR 0x2 +#define NFC_INPUT 0x4 +#define NFC_OUTPUT 0x8 +#define NFC_ID 0x10 +#define NFC_STATUS 0x20 + +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3_2 /* mx51 */ +#define NFC_AUTO_PROG 0x40 +#define NFC_AUTO_READ 0x80 +#define NFC_AUTO_ERASE 0x200 +#define NFC_COPY_BACK_0 0x400 +#define NFC_COPY_BACK_1 0x800 +#define NFC_AUTO_STATE 0x1000 +#endif + +/* Bit Definitions for NFC_IPC*/ +#define NFC_OPS_STAT (1 << 31) + +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3_2 /* mx51 */ +#define NFC_OP_DONE (1 << 30) +#define NFC_RB (1 << 28) +#define NFC_PS_WIDTH 2 +#define NFC_PS_SHIFT 0 +#define NFC_PS_512 0 +#define NFC_PS_2K 1 +#define NFC_PS_4K 2 +#else +#define NFC_RB (1 << 29) +#endif + +#define NFC_ONE_CYCLE (1 << 2) + +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3_2 /* mx51 */ +#define NFC_INT_MSK (1 << 15) +#define NFC_AUTO_PROG_DONE_MSK (1 << 14) +#define NFC_NUM_ADDR_PHASE1_WIDTH 2 +#define NFC_NUM_ADDR_PHASE1_SHIFT 12 + +#define NFC_NUM_ADDR_PHASE0_WIDTH 1 +#define NFC_NUM_ADDR_PHASE0_SHIFT 5 + +#define NFC_ONE_LESS_PHASE1 0 +#define NFC_TWO_LESS_PHASE1 1 + +#define NFC_FLASH_ADDR_SHIFT 0 +#else +#define NFC_INT_MSK (1 << 4) +#define NFC_BIG (1 << 5) +#define NFC_FLASH_ADDR_SHIFT 16 +#endif + +#define NFC_UNLOCK_END_ADDR_SHIFT 16 + +/* Bit definition for NFC_CONFIGRATION_1 */ +#define NFC_SP_EN (1 << 0) +#define NFC_CE (1 << 1) +#define NFC_RST (1 << 2) +#define NFC_ECC_EN (1 << 3) + +#define NFC_FIELD_RESET(width, shift) ~(((1 << (width)) - 1) << (shift)) + +#define NFC_RBA_SHIFT 4 + +#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_1) || \ + defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2) /* mx51 */ +#define NFC_RBA_WIDTH 3 +#else +#define NFC_RBA_WIDTH 2 +#endif + +#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2) /* mx51 */ +#define NFC_ITERATION_SHIFT 8 +#define NFC_ITERATION_WIDTH 4 +#define NFC_ACTIVE_CS_SHIFT 12 +#define NFC_ACTIVE_CS_WIDTH 3 +/* bit definition for CONFIGRATION3 */ +#define NFC_NO_SDMA (1 << 20) +#define NFC_FMP_SHIFT 16 +#define NFC_FMP_WIDTH 4 +#define NFC_RBB_MODE (1 << 15) +#define NFC_NUM_OF_DEVICES_SHIFT 12 +#define NFC_NUM_OF_DEVICES_WIDTH 4 +#define NFC_DMA_MODE_SHIFT 11 +#define NFC_DMA_MODE_WIDTH 1 +#define NFC_SBB_SHIFT 8 +#define NFC_SBB_WIDTH 3 +#define NFC_BIG (1 << 7) +#define NFC_SB2R_SHIFT 4 +#define NFC_SB2R_WIDTH 3 +#define NFC_FW_SHIFT 3 +#define NFC_FW_WIDTH 1 +#define NFC_TOO (1 << 2) +#define NFC_ADD_OP_SHIFT 0 +#define NFC_ADD_OP_WIDTH 2 +#define NFC_FW_8 1 +#define NFC_FW_16 0 +#define NFC_ST_CMD_SHITF 24 +#define NFC_ST_CMD_WIDTH 8 +#endif + +#define NFC_PPB_32 (0 << 7) +#define NFC_PPB_64 (1 << 7) +#define NFC_PPB_128 (2 << 7) +#define NFC_PPB_256 (3 << 7) +#define NFC_PPB_RESET ~(3 << 7) + +#define NFC_BLS_LOCKED (0 << 16) +#define NFC_BLS_LOCKED_DEFAULT (1 << 16) +#define NFC_BLS_UNLCOKED (2 << 16) +#define NFC_BLS_RESET ~(3 << 16) +#define NFC_WPC_LOCK_TIGHT 1 +#define NFC_WPC_LOCK (1 << 1) +#define NFC_WPC_UNLOCK (1 << 2) +#define NFC_WPC_RESET ~(7) +#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_1) || \ + defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2) +#define NFC_ECC_MODE_4 (1 << 6) +#define NFC_ECC_MODE_8 ~(1 << 6) +#define NFC_ECC_MODE_MASK ~(1 << 6) +#define NFC_SPAS_16 8 +#define NFC_SPAS_64 32 +#define NFC_SPAS_128 64 +#define NFC_SPAS_112 56 +#define NFC_SPAS_218 109 +#define NFC_IPC_CREQ (1 << 0) +#define NFC_IPC_ACK (1 << 1) +#endif + +#define REG_NFC_OPS_STAT NFC_IPC +#define REG_NFC_INTRRUPT NFC_CONFIG2 +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3_2 +#define REG_NFC_FLASH_ADDR NFC_FLASH_ADDR0 +#define REG_NFC_FLASH_CMD NFC_FLASH_CMD +#else +#define REG_NFC_FLASH_ADDR NFC_FLASH_ADDR_CMD +#define REG_NFC_FLASH_CMD NFC_FLASH_ADDR_CMD +#endif +#define REG_NFC_OPS LAUNCH_NFC +#define REG_NFC_SET_RBA NFC_CONFIG1 +#define REG_NFC_RB NFC_IPC +#define REG_NFC_ECC_EN NFC_CONFIG2 +#define REG_NFC_ECC_STATUS_RESULT NFC_ECC_STATUS_RESULT +#define REG_NFC_CE NFC_CONFIG1 +#define REG_NFC_RST NFC_CONFIG1 +#define REG_NFC_PPB NFC_CONFIG2 +#define REG_NFC_SP_EN NFC_CONFIG1 +#define REG_NFC_BLS NFC_WRPROT +#define REG_UNLOCK_BLK_ADD0 NFC_WRPROT_UNLOCK_BLK_ADD0 +#define REG_UNLOCK_BLK_ADD1 NFC_WRPROT_UNLOCK_BLK_ADD1 +#define REG_UNLOCK_BLK_ADD2 NFC_WRPROT_UNLOCK_BLK_ADD2 +#define REG_UNLOCK_BLK_ADD3 NFC_WRPROT_UNLOCK_BLK_ADD3 +#define REG_NFC_WPC NFC_WRPROT +#define REG_NFC_ONE_CYCLE NFC_CONFIG2 + +/* NFC V3 Specific MACRO functions definitions */ +#define raw_write(v,a) __raw_writel(v,a) +#define raw_read(a) __raw_readl(a) + +/* Explcit ack ops status (if any), before issue of any command */ +#define ACK_OPS \ + raw_write((raw_read(REG_NFC_OPS_STAT) & ~NFC_OPS_STAT), \ + REG_NFC_OPS_STAT); + +/* Set RBA buffer id*/ +#define NFC_SET_RBA(val) \ + raw_write((raw_read(REG_NFC_SET_RBA) & \ + (NFC_FIELD_RESET(NFC_RBA_WIDTH, NFC_RBA_SHIFT))) | \ + ((val) << NFC_RBA_SHIFT), REG_NFC_SET_RBA); + +#define NFC_SET_PS(val) \ + raw_write((raw_read(NFC_CONFIG2) & \ + (NFC_FIELD_RESET(NFC_PS_WIDTH, NFC_PS_SHIFT))) | \ + ((val) << NFC_PS_SHIFT), NFC_CONFIG2); + +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3_2 +#define UNLOCK_ADDR(start_addr,end_addr) \ +{ \ + int i = 0; \ + for (; i < NAND_MAX_CHIPS; i++) \ + raw_write(start_addr | \ + (end_addr << NFC_UNLOCK_END_ADDR_SHIFT), \ + REG_UNLOCK_BLK_ADD0 + (i << 2)); \ +} +#define NFC_SET_NFC_ACTIVE_CS(val) \ + raw_write((raw_read(NFC_CONFIG1) & \ + (NFC_FIELD_RESET(NFC_ACTIVE_CS_WIDTH, NFC_ACTIVE_CS_SHIFT))) | \ + ((val) << NFC_ACTIVE_CS_SHIFT), NFC_CONFIG1); + +#define NFC_GET_MAXCHIP_SP() 8 + +#else +#define UNLOCK_ADDR(start_addr,end_addr) \ + raw_write(start_addr | \ + (end_addr << NFC_UNLOCK_END_ADDR_SHIFT), REG_UNLOCK_BLK_ADD0); + +#define NFC_SET_NFC_ACTIVE_CS(val) +#define NFC_GET_MAXCHIP_SP() 1 +#endif + +#define NFC_SET_BLS(val) ((raw_read(REG_NFC_BLS) & NFC_BLS_RESET) | val ) +#define NFC_SET_WPC(val) ((raw_read(REG_NFC_WPC) & NFC_WPC_RESET) | val ) +#define CHECK_NFC_RB raw_read(REG_NFC_RB) & NFC_RB + +#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2) +#define NFC_SET_NFC_NUM_ADDR_PHASE1(val) \ + raw_write((raw_read(NFC_CONFIG2) & \ + (NFC_FIELD_RESET(NFC_NUM_ADDR_PHASE1_WIDTH, \ + NFC_NUM_ADDR_PHASE1_SHIFT))) | \ + ((val) << NFC_NUM_ADDR_PHASE1_SHIFT), NFC_CONFIG2); + +#define NFC_SET_NFC_NUM_ADDR_PHASE0(val) \ + raw_write((raw_read(NFC_CONFIG2) & \ + (NFC_FIELD_RESET(NFC_NUM_ADDR_PHASE0_WIDTH, \ + NFC_NUM_ADDR_PHASE0_SHIFT))) | \ + ((val) << NFC_NUM_ADDR_PHASE0_SHIFT), NFC_CONFIG2); + +#define NFC_SET_NFC_ITERATION(val) \ + raw_write((raw_read(NFC_CONFIG1) & \ + (NFC_FIELD_RESET(NFC_ITERATION_WIDTH, NFC_ITERATION_SHIFT))) | \ + ((val) << NFC_ITERATION_SHIFT), NFC_CONFIG1); + +#define NFC_SET_FW(val) \ + raw_write((raw_read(NFC_CONFIG3) & \ + (NFC_FIELD_RESET(NFC_FW_WIDTH, NFC_FW_SHIFT))) | \ + ((val) << NFC_FW_SHIFT), NFC_CONFIG3); + +#define NFC_SET_NUM_OF_DEVICE(val) \ + raw_write((raw_read(NFC_CONFIG3) & \ + (NFC_FIELD_RESET(NFC_NUM_OF_DEVICES_WIDTH, \ + NFC_NUM_OF_DEVICES_SHIFT))) | \ + ((val) << NFC_NUM_OF_DEVICES_SHIFT), NFC_CONFIG3); + +#define NFC_SET_ADD_OP_MODE(val) \ + raw_write((raw_read(NFC_CONFIG3) & \ + (NFC_FIELD_RESET(NFC_ADD_OP_WIDTH, NFC_ADD_OP_SHIFT))) | \ + ((val) << NFC_ADD_OP_SHIFT), NFC_CONFIG3); + +#define NFC_SET_ADD_CS_MODE(val) \ +{ \ + NFC_SET_ADD_OP_MODE(val); \ + NFC_SET_NUM_OF_DEVICE(this->numchips - 1); \ +} + +#define NFC_SET_ST_CMD(val) \ + raw_write((raw_read(NFC_CONFIG2) & \ + (NFC_FIELD_RESET(NFC_ST_CMD_WIDTH, \ + NFC_ST_CMD_SHITF))) | \ + ((val) << NFC_ST_CMD_SHITF), NFC_CONFIG2); + +#define NFMS_NF_DWIDTH 0 +#define NFMS_NF_PG_SZ 1 +#define NFC_CMD_1_SHIFT 8 + +#define NUM_OF_ADDR_CYCLE (fls(g_page_mask) >> 3) + +/*should set the fw,ps,spas,ppb*/ +#define NFC_SET_NFMS(v) \ +do { \ + NFC_SET_FW(NFC_FW_8); \ + if (((v) & (1 << NFMS_NF_DWIDTH))) \ + NFC_SET_FW(NFC_FW_16); \ + if (((v) & (1 << NFMS_NF_PG_SZ))) { \ + if (IS_2K_PAGE_NAND) { \ + NFC_SET_PS(NFC_PS_2K); \ + NFC_SET_NFC_NUM_ADDR_PHASE1(NUM_OF_ADDR_CYCLE); \ + NFC_SET_NFC_NUM_ADDR_PHASE0(NFC_TWO_LESS_PHASE1); \ + } else if (IS_4K_PAGE_NAND) { \ + NFC_SET_PS(NFC_PS_4K); \ + NFC_SET_NFC_NUM_ADDR_PHASE1(NUM_OF_ADDR_CYCLE); \ + NFC_SET_NFC_NUM_ADDR_PHASE0(NFC_TWO_LESS_PHASE1); \ + } else { \ + NFC_SET_PS(NFC_PS_512); \ + NFC_SET_NFC_NUM_ADDR_PHASE1(NUM_OF_ADDR_CYCLE - 1); \ + NFC_SET_NFC_NUM_ADDR_PHASE0(NFC_ONE_LESS_PHASE1); \ + } \ + NFC_SET_ADD_CS_MODE(1); \ + NFC_SET_SPAS(GET_NAND_OOB_SIZE >> 1); \ + NFC_SET_ECC_MODE(GET_NAND_OOB_SIZE >> 1); \ + NFC_SET_ST_CMD(0x70); \ + raw_write(raw_read(NFC_CONFIG3) | 1 << 20, NFC_CONFIG3); \ + } \ +} while (0) +#endif + +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3_1 +#define NFC_SET_NFMS(v) +#endif + +#define READ_PAGE() send_read_page(0) +#define PROG_PAGE() send_prog_page(0) + +#elif CONFIG_ARCH_MXC_HAS_NFC_V2 + +/* + * For V1/V2 NFC registers Definition + */ + +#define NFC_AXI_BASE_ADDR 0x00 +/* + * Addresses for NFC registers + */ +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1 +#define NFC_REG_BASE (nfc_ip_base + 0x1000) +#else +#define NFC_REG_BASE nfc_ip_base +#endif +#define NFC_BUF_SIZE (NFC_REG_BASE + 0xE00) +#define NFC_BUF_ADDR (NFC_REG_BASE + 0xE04) +#define NFC_FLASH_ADDR (NFC_REG_BASE + 0xE06) +#define NFC_FLASH_CMD (NFC_REG_BASE + 0xE08) +#define NFC_CONFIG (NFC_REG_BASE + 0xE0A) +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1 +#define NFC_ECC_STATUS_RESULT (NFC_REG_BASE + 0xE0C) +#define NFC_ECC_STATUS_RESULT_1 (NFC_REG_BASE + 0xE0C) +#define NFC_ECC_STATUS_RESULT_2 (NFC_REG_BASE + 0xE0E) +#define NFC_SPAS (NFC_REG_BASE + 0xE10) +#else +#define NFC_ECC_STATUS_RESULT (NFC_REG_BASE + 0xE0C) +#define NFC_RSLTMAIN_AREA (NFC_REG_BASE + 0xE0E) +#define NFC_RSLTSPARE_AREA (NFC_REG_BASE + 0xE10) +#endif +#define NFC_WRPROT (NFC_REG_BASE + 0xE12) +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1 +#define NFC_UNLOCKSTART_BLKADDR (NFC_REG_BASE + 0xE20) +#define NFC_UNLOCKEND_BLKADDR (NFC_REG_BASE + 0xE22) +#define NFC_UNLOCKSTART_BLKADDR1 (NFC_REG_BASE + 0xE24) +#define NFC_UNLOCKEND_BLKADDR1 (NFC_REG_BASE + 0xE26) +#define NFC_UNLOCKSTART_BLKADDR2 (NFC_REG_BASE + 0xE28) +#define NFC_UNLOCKEND_BLKADDR2 (NFC_REG_BASE + 0xE2A) +#define NFC_UNLOCKSTART_BLKADDR3 (NFC_REG_BASE + 0xE2C) +#define NFC_UNLOCKEND_BLKADDR3 (NFC_REG_BASE + 0xE2E) +#else +#define NFC_UNLOCKSTART_BLKADDR (NFC_REG_BASE + 0xE14) +#define NFC_UNLOCKEND_BLKADDR (NFC_REG_BASE + 0xE16) +#endif +#define NFC_NF_WRPRST (NFC_REG_BASE + 0xE18) +#define NFC_CONFIG1 (NFC_REG_BASE + 0xE1A) +#define NFC_CONFIG2 (NFC_REG_BASE + 0xE1C) + +/*! + * Addresses for NFC RAM BUFFER Main area 0 + */ +#define MAIN_AREA0 (u16 *)(nfc_ip_base + 0x000) +#define MAIN_AREA1 (u16 *)(nfc_ip_base + 0x200) + +/*! + * Addresses for NFC SPARE BUFFER Spare area 0 + */ +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1 +#define SPARE_AREA0 (u16 *)(nfc_ip_base + 0x1000) +#define SPARE_LEN 64 +#define SPARE_COUNT 8 +#else +#define SPARE_AREA0 (u16 *)(nfc_ip_base + 0x800) +#define SPARE_LEN 16 +#define SPARE_COUNT 4 +#endif +#define SPARE_SIZE (SPARE_LEN * SPARE_COUNT) + +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1 +#define REG_NFC_ECC_MODE NFC_CONFIG1 +#define SPAS_SHIFT (0) +#define REG_NFC_SPAS NFC_SPAS +#define SPAS_MASK (0xFF00) +#define IS_4BIT_ECC \ + ((raw_read(REG_NFC_ECC_MODE) & NFC_ECC_MODE_4) >> 0) + +#define NFC_SET_SPAS(v) \ + raw_write(((raw_read(REG_NFC_SPAS) & SPAS_MASK) | ((v<> 1); \ + NFC_SET_ECC_MODE(GET_NAND_OOB_SIZE >> 1); \ + } \ +} while (0) +#else +#define IS_4BIT_ECC (1) +#define NFC_SET_SPAS(v) +#define NFC_SET_ECC_MODE(v) +#define GET_ECC_STATUS() raw_read(REG_NFC_ECC_STATUS_RESULT); +#define NFC_SET_NFMS(v) (NFMS |= (v)) +#endif + +#define WRITE_NFC_IP_REG(val,reg) \ + raw_write((raw_read(REG_NFC_OPS_STAT) & ~NFC_OPS_STAT), \ + REG_NFC_OPS_STAT) + +#define GET_NFC_ECC_STATUS() raw_read(REG_NFC_ECC_STATUS_RESULT); + +/*! + * Set INT to 0, Set 1 to specific operation bit, rest to 0 in LAUNCH_NFC Register for + * Specific operation + */ +#define NFC_CMD 0x1 +#define NFC_ADDR 0x2 +#define NFC_INPUT 0x4 +#define NFC_OUTPUT 0x8 +#define NFC_ID 0x10 +#define NFC_STATUS 0x20 + +/* Bit Definitions */ +#define NFC_OPS_STAT (1 << 15) +#define NFC_SP_EN (1 << 2) +#define NFC_ECC_EN (1 << 3) +#define NFC_INT_MSK (1 << 4) +#define NFC_BIG (1 << 5) +#define NFC_RST (1 << 6) +#define NFC_CE (1 << 7) +#define NFC_ONE_CYCLE (1 << 8) +#define NFC_BLS_LOCKED 0 +#define NFC_BLS_LOCKED_DEFAULT 1 +#define NFC_BLS_UNLCOKED 2 +#define NFC_WPC_LOCK_TIGHT 1 +#define NFC_WPC_LOCK (1 << 1) +#define NFC_WPC_UNLOCK (1 << 2) +#define NFC_FLASH_ADDR_SHIFT 0 +#define NFC_UNLOCK_END_ADDR_SHIFT 0 + +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1 +#define NFC_ECC_MODE_4 (1<<0) +#define NFC_ECC_MODE_8 ~(1<<0) +#define NFC_SPAS_16 8 +#define NFC_SPAS_64 32 +#define NFC_SPAS_112 56 +#define NFC_SPAS_128 64 +#define NFC_SPAS_218 109 +#endif +/* NFC Register Mapping */ +#define REG_NFC_OPS_STAT NFC_CONFIG2 +#define REG_NFC_INTRRUPT NFC_CONFIG1 +#define REG_NFC_FLASH_ADDR NFC_FLASH_ADDR +#define REG_NFC_FLASH_CMD NFC_FLASH_CMD +#define REG_NFC_OPS NFC_CONFIG2 +#define REG_NFC_SET_RBA NFC_BUF_ADDR +#define REG_NFC_ECC_EN NFC_CONFIG1 +#define REG_NFC_ECC_STATUS_RESULT NFC_ECC_STATUS_RESULT +#define REG_NFC_CE NFC_CONFIG1 +#define REG_NFC_SP_EN NFC_CONFIG1 +#define REG_NFC_BLS NFC_CONFIG +#define REG_NFC_WPC NFC_WRPROT +#define REG_START_BLKADDR NFC_UNLOCKSTART_BLKADDR +#define REG_END_BLKADDR NFC_UNLOCKEND_BLKADDR +#define REG_NFC_RST NFC_CONFIG1 +#define REG_NFC_ONE_CYCLE NFC_CONFIG1 + +/* NFC V1/V2 Specific MACRO functions definitions */ + +#define raw_write(v,a) __raw_writew(v,a) +#define raw_read(a) __raw_readw(a) + +#define NFC_SET_BLS(val) val + +#define UNLOCK_ADDR(start_addr,end_addr) \ +{ \ + raw_write(start_addr,REG_START_BLKADDR); \ + raw_write(end_addr,REG_END_BLKADDR); \ +} + +#define NFC_SET_NFC_ACTIVE_CS(val) +#define NFC_GET_MAXCHIP_SP() 1 +#define NFC_SET_WPC(val) val + +/* NULL Definitions */ +#define ACK_OPS +#define NFC_SET_RBA(val) raw_write(val, REG_NFC_SET_RBA); + +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1 +#define READ_PAGE() send_read_page(0) +#define PROG_PAGE() send_prog_page(0) +#else +#define READ_PAGE() \ +do { \ + send_read_page(0); \ + send_read_page(1); \ + send_read_page(2); \ + send_read_page(3); \ +} while (0) + +#define PROG_PAGE() \ +do { \ + send_prog_page(0); \ + send_prog_page(1); \ + send_prog_page(2); \ + send_prog_page(3); \ +} while (0) +#endif +#define CHECK_NFC_RB 1 + +#endif + +#endif /* __MXC_ND2_H__ */ diff -urN linux-2.6.26/drivers/mtd/nand/nand_base.c linux-2.6.26-lab126/drivers/mtd/nand/nand_base.c --- linux-2.6.26/drivers/mtd/nand/nand_base.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/nand/nand_base.c 2010-08-10 04:15:32.000000000 -0400 @@ -2288,7 +2288,8 @@ mtd->writesize = 1024 << (extid & 0x3); extid >>= 2; /* Calc oobsize */ - mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9); + mtd->oobsize = (*maf_id == 0x2c && dev_id == 0xd5) ? + 218 : (8 << (extid & 0x01)) * (mtd->writesize >> 9); extid >>= 2; /* Calc blocksize. Blocksize is multiples of 64KiB */ mtd->erasesize = (64 * 1024) << (extid & 0x03); diff -urN linux-2.6.26/drivers/mtd/nand/nand_ids.c linux-2.6.26-lab126/drivers/mtd/nand/nand_ids.c --- linux-2.6.26/drivers/mtd/nand/nand_ids.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/nand/nand_ids.c 2010-08-10 04:15:32.000000000 -0400 @@ -111,6 +111,9 @@ {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16}, {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16}, + /* 32 Gigabit ,only use 2G due to the linux mtd limitation*/ + {"NAND 4GiB 3,3V 8-bit", 0xD7, 0, 2048, 0, LP_OPTIONS}, + /* * Renesas AND 1 Gigabit. Those chips do not support extended id and * have a strange page/block layout ! The chosen minimum erasesize is diff -urN linux-2.6.26/drivers/mtd/nand/nandsim.c linux-2.6.26-lab126/drivers/mtd/nand/nandsim.c --- linux-2.6.26/drivers/mtd/nand/nandsim.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/nand/nandsim.c 2010-08-10 04:15:32.000000000 -0400 @@ -39,6 +39,7 @@ #include #include #include +#include /* Default simulator parameters values */ #if !defined(CONFIG_NANDSIM_FIRST_ID_BYTE) || \ @@ -298,11 +299,11 @@ /* NAND flash "geometry" */ struct nandsin_geometry { - uint32_t totsz; /* total flash size, bytes */ + uint64_t totsz; /* total flash size, bytes */ uint32_t secsz; /* flash sector (erase block) size, bytes */ uint pgsz; /* NAND flash page size, bytes */ uint oobsz; /* page OOB area size, bytes */ - uint32_t totszoob; /* total flash size including OOB, bytes */ + uint64_t totszoob; /* total flash size including OOB, bytes */ uint pgszoob; /* page size including OOB , bytes*/ uint secszoob; /* sector size including OOB, bytes */ uint pgnum; /* total number of pages */ @@ -459,6 +460,12 @@ return kstrdup(buf, GFP_KERNEL); } +static u_int64_t divide(u_int64_t n, u_int32_t d) +{ + do_div(n, d); + return n; +} + /* * Initialize the nandsim structure. * @@ -469,8 +476,8 @@ struct nand_chip *chip = (struct nand_chip *)mtd->priv; struct nandsim *ns = (struct nandsim *)(chip->priv); int i, ret = 0; - u_int32_t remains; - u_int32_t next_offset; + u_int64_t remains; + u_int64_t next_offset; if (NS_IS_INITIALIZED(ns)) { NS_ERR("init_nandsim: nandsim is already initialized\n"); @@ -487,8 +494,8 @@ ns->geom.oobsz = mtd->oobsize; ns->geom.secsz = mtd->erasesize; ns->geom.pgszoob = ns->geom.pgsz + ns->geom.oobsz; - ns->geom.pgnum = ns->geom.totsz / ns->geom.pgsz; - ns->geom.totszoob = ns->geom.totsz + ns->geom.pgnum * ns->geom.oobsz; + ns->geom.pgnum = divide(ns->geom.totsz, ns->geom.pgsz); + ns->geom.totszoob = ns->geom.totsz + (uint64_t)ns->geom.pgnum * ns->geom.oobsz; ns->geom.secshift = ffs(ns->geom.secsz) - 1; ns->geom.pgshift = chip->page_shift; ns->geom.oobshift = ffs(ns->geom.oobsz) - 1; @@ -511,7 +518,7 @@ } if (ns->options & OPT_SMALLPAGE) { - if (ns->geom.totsz < (32 << 20)) { + if (ns->geom.totsz <= (32 << 20)) { ns->geom.pgaddrbytes = 3; ns->geom.secaddrbytes = 2; } else { @@ -537,15 +544,16 @@ remains = ns->geom.totsz; next_offset = 0; for (i = 0; i < parts_num; ++i) { - unsigned long part = parts[i]; - if (!part || part > remains / ns->geom.secsz) { + u_int64_t part_sz = (u_int64_t)parts[i] * ns->geom.secsz; + + if (!part_sz || part_sz > remains) { NS_ERR("bad partition size.\n"); ret = -EINVAL; goto error; } ns->partitions[i].name = get_partition_name(i); ns->partitions[i].offset = next_offset; - ns->partitions[i].size = part * ns->geom.secsz; + ns->partitions[i].size = part_sz; next_offset += ns->partitions[i].size; remains -= ns->partitions[i].size; } @@ -573,7 +581,8 @@ if (ns->busw == 16) NS_WARN("16-bit flashes support wasn't tested\n"); - printk("flash size: %u MiB\n", ns->geom.totsz >> 20); + printk("flash size: %llu MiB\n", + (unsigned long long)ns->geom.totsz >> 20); printk("page size: %u bytes\n", ns->geom.pgsz); printk("OOB area size: %u bytes\n", ns->geom.oobsz); printk("sector size: %u KiB\n", ns->geom.secsz >> 10); @@ -582,8 +591,9 @@ printk("bus width: %u\n", ns->busw); printk("bits in sector size: %u\n", ns->geom.secshift); printk("bits in page size: %u\n", ns->geom.pgshift); - printk("bits in OOB size: %u\n", ns->geom.oobshift); - printk("flash size with OOB: %u KiB\n", ns->geom.totszoob >> 10); + printk("bits in OOB size: %u\n", ns->geom.oobshift); + printk("flash size with OOB: %llu KiB\n", + (unsigned long long)ns->geom.totszoob >> 10); printk("page address bytes: %u\n", ns->geom.pgaddrbytes); printk("sector address bytes: %u\n", ns->geom.secaddrbytes); printk("options: %#x\n", ns->options); @@ -825,7 +835,7 @@ if (!rptwear) return 0; - wear_eb_count = mtd->size / mtd->erasesize; + wear_eb_count = divide(mtd->size, mtd->erasesize); mem = wear_eb_count * sizeof(unsigned long); if (mem / sizeof(unsigned long) != wear_eb_count) { NS_ERR("Too many erase blocks for wear reporting\n"); @@ -2013,7 +2023,7 @@ } if (overridesize) { - u_int32_t new_size = nsmtd->erasesize << overridesize; + u_int64_t new_size = (u_int64_t)nsmtd->erasesize << overridesize; if (new_size >> overridesize != nsmtd->erasesize) { NS_ERR("overridesize is too big\n"); goto err_exit; @@ -2021,7 +2031,8 @@ /* N.B. This relies on nand_scan not doing anything with the size before we change it */ nsmtd->size = new_size; chip->chipsize = new_size; - chip->chip_shift = ffs(new_size) - 1; + chip->chip_shift = ffs(nsmtd->erasesize) + overridesize - 1; + chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; } if ((retval = setup_wear_reporting(nsmtd)) != 0) diff -urN linux-2.6.26/drivers/mtd/ubi/build.c linux-2.6.26-lab126/drivers/mtd/ubi/build.c --- linux-2.6.26/drivers/mtd/ubi/build.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/ubi/build.c 2010-08-10 04:15:31.000000000 -0400 @@ -51,14 +51,13 @@ * @name: MTD device name or number string * @vid_hdr_offs: VID header offset */ -struct mtd_dev_param -{ +struct mtd_dev_param { char name[MTD_PARAM_LEN_MAX]; int vid_hdr_offs; }; /* Numbers of elements set in the @mtd_dev_param array */ -static int mtd_devs = 0; +static int mtd_devs; /* MTD devices specification parameters */ static struct mtd_dev_param mtd_dev_param[UBI_MAX_DEVICES]; @@ -160,8 +159,7 @@ } /** - * ubi_get_by_major - get UBI device description object by character device - * major number. + * ubi_get_by_major - get UBI device by character device major number. * @major: major number * * This function is similar to 'ubi_get_device()', but it searches the device @@ -355,15 +353,34 @@ } /** + * free_user_volumes - free all user volumes. + * @ubi: UBI device description object + * + * Normally the volumes are freed at the release function of the volume device + * objects. However, on error paths the volumes have to be freed before the + * device objects have been initialized. + */ +static void free_user_volumes(struct ubi_device *ubi) +{ + int i; + + for (i = 0; i < ubi->vtbl_slots; i++) + if (ubi->volumes[i]) { + kfree(ubi->volumes[i]->eba_tbl); + kfree(ubi->volumes[i]); + } +} + +/** * uif_init - initialize user interfaces for an UBI device. * @ubi: UBI device description object * * This function returns zero in case of success and a negative error code in - * case of failure. + * case of failure. Note, this function destroys all volumes if it failes. */ static int uif_init(struct ubi_device *ubi) { - int i, err; + int i, err, do_free = 0; dev_t dev; sprintf(ubi->ubi_name, UBI_NAME_STR "%d", ubi->ubi_num); @@ -384,7 +401,7 @@ ubi_assert(MINOR(dev) == 0); cdev_init(&ubi->cdev, &ubi_cdev_operations); - dbg_msg("%s major is %u", ubi->ubi_name, MAJOR(dev)); + dbg_gen("%s major is %u", ubi->ubi_name, MAJOR(dev)); ubi->cdev.owner = THIS_MODULE; err = cdev_add(&ubi->cdev, dev, 1); @@ -410,10 +427,13 @@ out_volumes: kill_volumes(ubi); + do_free = 0; out_sysfs: ubi_sysfs_close(ubi); cdev_del(&ubi->cdev); out_unreg: + if (do_free) + free_user_volumes(ubi); unregister_chrdev_region(ubi->cdev.dev, ubi->vtbl_slots + 1); ubi_err("cannot initialize UBI %s, error %d", ubi->ubi_name, err); return err; @@ -422,6 +442,10 @@ /** * uif_close - close user interfaces for an UBI device. * @ubi: UBI device description object + * + * Note, since this function un-registers UBI volume device objects (@vol->dev), + * the memory allocated voe the volumes is freed as well (in the release + * function). */ static void uif_close(struct ubi_device *ubi) { @@ -432,6 +456,21 @@ } /** + * free_internal_volumes - free internal volumes. + * @ubi: UBI device description object + */ +static void free_internal_volumes(struct ubi_device *ubi) +{ + int i; + + for (i = ubi->vtbl_slots; + i < ubi->vtbl_slots + UBI_INT_VOL_COUNT; i++) { + kfree(ubi->volumes[i]->eba_tbl); + kfree(ubi->volumes[i]); + } +} + +/** * attach_by_scanning - attach an MTD device using scanning method. * @ubi: UBI device descriptor * @@ -475,6 +514,7 @@ out_wl: ubi_wl_close(ubi); out_vtbl: + free_internal_volumes(ubi); vfree(ubi->vtbl); out_si: ubi_scan_destroy_si(si); @@ -482,7 +522,7 @@ } /** - * io_init - initialize I/O unit for a given UBI device. + * io_init - initialize I/O sub-system for a given UBI device. * @ubi: UBI device description object * * If @ubi->vid_hdr_offset or @ubi->leb_start is zero, default offsets are @@ -530,7 +570,11 @@ ubi->min_io_size = ubi->mtd->writesize; ubi->hdrs_min_io_size = ubi->mtd->writesize >> ubi->mtd->subpage_sft; - /* Make sure minimal I/O unit is power of 2 */ + /* + * Make sure minimal I/O unit is power of 2. Note, there is no + * fundamental reason for this assumption. It is just an optimization + * which allows us to avoid costly division operations. + */ if (!is_power_of_2(ubi->min_io_size)) { ubi_err("min. I/O unit (%d) is not power of 2", ubi->min_io_size); @@ -581,7 +625,7 @@ if (ubi->vid_hdr_offset < UBI_EC_HDR_SIZE || ubi->leb_start < ubi->vid_hdr_offset + UBI_VID_HDR_SIZE || ubi->leb_start > ubi->peb_size - UBI_VID_HDR_SIZE || - ubi->leb_start % ubi->min_io_size) { + ubi->leb_start & (ubi->min_io_size - 1)) { ubi_err("bad VID header (%d) or data offsets (%d)", ubi->vid_hdr_offset, ubi->leb_start); return -EINVAL; @@ -646,7 +690,7 @@ /* * Clear the auto-resize flag in the volume in-memory copy of the - * volume table, and 'ubi_resize_volume()' will propogate this change + * volume table, and 'ubi_resize_volume()' will propagate this change * to the flash. */ ubi->vtbl[vol_id].flags &= ~UBI_VTBL_AUTORESIZE_FLG; @@ -655,7 +699,7 @@ struct ubi_vtbl_record vtbl_rec; /* - * No avalilable PEBs to re-size the volume, clear the flag on + * No available PEBs to re-size the volume, clear the flag on * flash and exit. */ memcpy(&vtbl_rec, &ubi->vtbl[vol_id], @@ -682,13 +726,13 @@ /** * ubi_attach_mtd_dev - attach an MTD device. - * @mtd_dev: MTD device description object + * @mtd: MTD device description object * @ubi_num: number to assign to the new UBI device * @vid_hdr_offset: VID header offset * * This function attaches MTD device @mtd_dev to UBI and assign @ubi_num number * to the newly created UBI device, unless @ubi_num is %UBI_DEV_NUM_AUTO, in - * which case this function finds a vacant device nubert and assings it + * which case this function finds a vacant device number and assigns it * automatically. Returns the new UBI device number in case of success and a * negative error code in case of failure. * @@ -698,7 +742,7 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset) { struct ubi_device *ubi; - int i, err; + int i, err, do_free = 1; /* * Check if we already have the same MTD device attached. @@ -735,7 +779,8 @@ if (!ubi_devices[ubi_num]) break; if (ubi_num == UBI_MAX_DEVICES) { - dbg_err("only %d UBI devices may be created", UBI_MAX_DEVICES); + dbg_err("only %d UBI devices may be created", + UBI_MAX_DEVICES); return -ENFILE; } } else { @@ -760,6 +805,7 @@ mutex_init(&ubi->buf_mutex); mutex_init(&ubi->ckvol_mutex); + mutex_init(&ubi->mult_mutex); mutex_init(&ubi->volumes_mutex); spin_lock_init(&ubi->volumes_lock); @@ -798,7 +844,7 @@ err = uif_init(ubi); if (err) - goto out_detach; + goto out_nofree; ubi->bgt_thread = kthread_create(ubi_thread, ubi, ubi->bgt_name); if (IS_ERR(ubi->bgt_thread)) { @@ -824,20 +870,22 @@ ubi->beb_rsvd_pebs); ubi_msg("max/mean erase counter: %d/%d", ubi->max_ec, ubi->mean_ec); - /* Enable the background thread */ - if (!DBG_DISABLE_BGT) { + if (!DBG_DISABLE_BGT) ubi->thread_enabled = 1; - wake_up_process(ubi->bgt_thread); - } + wake_up_process(ubi->bgt_thread); ubi_devices[ubi_num] = ubi; return ubi_num; out_uif: uif_close(ubi); +out_nofree: + do_free = 0; out_detach: - ubi_eba_close(ubi); ubi_wl_close(ubi); + if (do_free) + free_user_volumes(ubi); + free_internal_volumes(ubi); vfree(ubi->vtbl); out_free: vfree(ubi->peb_buf1); @@ -899,8 +947,8 @@ kthread_stop(ubi->bgt_thread); uif_close(ubi); - ubi_eba_close(ubi); ubi_wl_close(ubi); + free_internal_volumes(ubi); vfree(ubi->vtbl); put_mtd_device(ubi->mtd); vfree(ubi->peb_buf1); @@ -1044,8 +1092,7 @@ module_exit(ubi_exit); /** - * bytes_str_to_int - convert a string representing number of bytes to an - * integer. + * bytes_str_to_int - convert a number of bytes string into an integer. * @str: the string to convert * * This function returns positive resulting integer in case of success and a diff -urN linux-2.6.26/drivers/mtd/ubi/cdev.c linux-2.6.26-lab126/drivers/mtd/ubi/cdev.c --- linux-2.6.26/drivers/mtd/ubi/cdev.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/ubi/cdev.c 2010-08-10 04:15:31.000000000 -0400 @@ -39,8 +39,8 @@ #include #include #include +#include #include -#include #include #include "ubi.h" @@ -112,7 +112,7 @@ else mode = UBI_READONLY; - dbg_msg("open volume %d, mode %d", vol_id, mode); + dbg_gen("open volume %d, mode %d", vol_id, mode); desc = ubi_open_volume(ubi_num, vol_id, mode); if (IS_ERR(desc)) @@ -127,7 +127,7 @@ struct ubi_volume_desc *desc = file->private_data; struct ubi_volume *vol = desc->vol; - dbg_msg("release volume %d, mode %d", vol->vol_id, desc->mode); + dbg_gen("release volume %d, mode %d", vol->vol_id, desc->mode); if (vol->updating) { ubi_warn("update of volume %d not finished, volume is damaged", @@ -136,7 +136,7 @@ vol->updating = 0; vfree(vol->upd_buf); } else if (vol->changing_leb) { - dbg_msg("only %lld of %lld bytes received for atomic LEB change" + dbg_gen("only %lld of %lld bytes received for atomic LEB change" " for volume %d:%d, cancel", vol->upd_received, vol->upd_bytes, vol->ubi->ubi_num, vol->vol_id); vol->changing_leb = 0; @@ -178,7 +178,7 @@ return -EINVAL; } - dbg_msg("seek volume %d, offset %lld, origin %d, new offset %lld", + dbg_gen("seek volume %d, offset %lld, origin %d, new offset %lld", vol->vol_id, offset, origin, new_offset); file->f_pos = new_offset; @@ -196,7 +196,7 @@ void *tbuf; uint64_t tmp; - dbg_msg("read %zd bytes from offset %lld of volume %d", + dbg_gen("read %zd bytes from offset %lld of volume %d", count, *offp, vol->vol_id); if (vol->updating) { @@ -211,7 +211,7 @@ return 0; if (vol->corrupted) - dbg_msg("read from corrupted volume %d", vol->vol_id); + dbg_gen("read from corrupted volume %d", vol->vol_id); if (*offp + count > vol->used_bytes) count_save = count = vol->used_bytes - *offp; @@ -280,7 +280,7 @@ char *tbuf; uint64_t tmp; - dbg_msg("requested: write %zd bytes to offset %lld of volume %u", + dbg_gen("requested: write %zd bytes to offset %lld of volume %u", count, *offp, vol->vol_id); if (vol->vol_type == UBI_STATIC_VOLUME) @@ -290,7 +290,7 @@ off = do_div(tmp, vol->usable_leb_size); lnum = tmp; - if (off % ubi->min_io_size) { + if (off & (ubi->min_io_size - 1)) { dbg_err("unaligned position"); return -EINVAL; } @@ -299,7 +299,7 @@ count_save = count = vol->used_bytes - *offp; /* We can write only in fractions of the minimum I/O unit */ - if (count % ubi->min_io_size) { + if (count & (ubi->min_io_size - 1)) { dbg_err("unaligned write length"); return -EINVAL; } @@ -347,7 +347,7 @@ } #else -#define vol_cdev_direct_write(file, buf, count, offp) -EPERM +#define vol_cdev_direct_write(file, buf, count, offp) (-EPERM) #endif /* CONFIG_MTD_UBI_DEBUG_USERSPACE_IO */ static ssize_t vol_cdev_write(struct file *file, const char __user *buf, @@ -432,7 +432,8 @@ break; } - rsvd_bytes = vol->reserved_pebs * (ubi->leb_size-vol->data_pad); + rsvd_bytes = (long long)vol->reserved_pebs * + ubi->leb_size-vol->data_pad; if (bytes < 0 || bytes > rsvd_bytes) { err = -EINVAL; break; @@ -508,7 +509,7 @@ break; } - dbg_msg("erase LEB %d:%d", vol->vol_id, lnum); + dbg_gen("erase LEB %d:%d", vol->vol_id, lnum); err = ubi_eba_unmap_leb(ubi, vol, lnum); if (err) break; @@ -559,7 +560,7 @@ if (req->alignment > ubi->leb_size) goto bad; - n = req->alignment % ubi->min_io_size; + n = req->alignment & (ubi->min_io_size - 1); if (req->alignment != 1 && n) goto bad; @@ -568,6 +569,10 @@ goto bad; } + n = strnlen(req->name, req->name_len + 1); + if (n != req->name_len) + goto bad; + return 0; bad: @@ -595,6 +600,166 @@ return 0; } +/** + * rename_volumes - rename UBI volumes. + * @ubi: UBI device description object + * @req: volumes re-name request + * + * This is a helper function for the volume re-name IOCTL which validates the + * the request, opens the volume and calls corresponding volumes management + * function. Returns zero in case of success and a negative error code in case + * of failure. + */ +static int rename_volumes(struct ubi_device *ubi, + struct ubi_rnvol_req *req) +{ + int i, n, err; + struct list_head rename_list; + struct ubi_rename_entry *re, *re1; + + if (req->count < 0 || req->count > UBI_MAX_RNVOL) + return -EINVAL; + + if (req->count == 0) + return 0; + + /* Validate volume IDs and names in the request */ + for (i = 0; i < req->count; i++) { + if (req->ents[i].vol_id < 0 || + req->ents[i].vol_id >= ubi->vtbl_slots) + return -EINVAL; + if (req->ents[i].name_len < 0) + return -EINVAL; + if (req->ents[i].name_len > UBI_VOL_NAME_MAX) + return -ENAMETOOLONG; + req->ents[i].name[req->ents[i].name_len] = '\0'; + n = strlen(req->ents[i].name); + if (n != req->ents[i].name_len) + err = -EINVAL; + } + + /* Make sure volume IDs and names are unique */ + for (i = 0; i < req->count - 1; i++) { + for (n = i + 1; n < req->count; n++) { + if (req->ents[i].vol_id == req->ents[n].vol_id) { + dbg_err("duplicated volume id %d", + req->ents[i].vol_id); + return -EINVAL; + } + if (!strcmp(req->ents[i].name, req->ents[n].name)) { + dbg_err("duplicated volume name \"%s\"", + req->ents[i].name); + return -EINVAL; + } + } + } + + /* Create the re-name list */ + INIT_LIST_HEAD(&rename_list); + for (i = 0; i < req->count; i++) { + int vol_id = req->ents[i].vol_id; + int name_len = req->ents[i].name_len; + const char *name = req->ents[i].name; + + re = kzalloc(sizeof(struct ubi_rename_entry), GFP_KERNEL); + if (!re) { + err = -ENOMEM; + goto out_free; + } + + re->desc = ubi_open_volume(ubi->ubi_num, vol_id, UBI_EXCLUSIVE); + if (IS_ERR(re->desc)) { + err = PTR_ERR(re->desc); + dbg_err("cannot open volume %d, error %d", vol_id, err); + kfree(re); + goto out_free; + } + + /* Skip this re-naming if the name does not really change */ + if (re->desc->vol->name_len == name_len && + !memcmp(re->desc->vol->name, name, name_len)) { + ubi_close_volume(re->desc); + kfree(re); + continue; + } + + re->new_name_len = name_len; + memcpy(re->new_name, name, name_len); + list_add_tail(&re->list, &rename_list); + dbg_msg("will rename volume %d from \"%s\" to \"%s\"", + vol_id, re->desc->vol->name, name); + } + + if (list_empty(&rename_list)) + return 0; + + /* Find out the volumes which have to be removed */ + list_for_each_entry(re, &rename_list, list) { + struct ubi_volume_desc *desc; + int no_remove_needed = 0; + + /* + * Volume @re->vol_id is going to be re-named to + * @re->new_name, while its current name is @name. If a volume + * with name @re->new_name currently exists, it has to be + * removed, unless it is also re-named in the request (@req). + */ + list_for_each_entry(re1, &rename_list, list) { + if (re->new_name_len == re1->desc->vol->name_len && + !memcmp(re->new_name, re1->desc->vol->name, + re1->desc->vol->name_len)) { + no_remove_needed = 1; + break; + } + } + + if (no_remove_needed) + continue; + + /* + * It seems we need to remove volume with name @re->new_name, + * if it exists. + */ + desc = ubi_open_volume_nm(ubi->ubi_num, re->new_name, UBI_EXCLUSIVE); + if (IS_ERR(desc)) { + err = PTR_ERR(desc); + if (err == -ENODEV) + /* Re-naming into a non-existing volume name */ + continue; + + /* The volume exists but busy, or an error occurred */ + dbg_err("cannot open volume \"%s\", error %d", + re->new_name, err); + goto out_free; + } + + re = kzalloc(sizeof(struct ubi_rename_entry), GFP_KERNEL); + if (!re) { + err = -ENOMEM; + ubi_close_volume(desc); + goto out_free; + } + + re->remove = 1; + re->desc = desc; + list_add(&re->list, &rename_list); + dbg_msg("will remove volume %d, name \"%s\"", + re->desc->vol->vol_id, re->desc->vol->name); + } + + mutex_lock(&ubi->volumes_mutex); + err = ubi_rename_volumes(ubi, &rename_list); + mutex_unlock(&ubi->volumes_mutex); + +out_free: + list_for_each_entry_safe(re, re1, &rename_list, list) { + ubi_close_volume(re->desc); + list_del(&re->list); + kfree(re); + } + return err; +} + static int ubi_cdev_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) { @@ -616,19 +781,18 @@ { struct ubi_mkvol_req req; - dbg_msg("create volume"); + dbg_gen("create volume"); err = copy_from_user(&req, argp, sizeof(struct ubi_mkvol_req)); if (err) { err = -EFAULT; break; } + req.name[req.name_len] = '\0'; err = verify_mkvol_req(ubi, &req); if (err) break; - req.name[req.name_len] = '\0'; - mutex_lock(&ubi->volumes_mutex); err = ubi_create_volume(ubi, &req); mutex_unlock(&ubi->volumes_mutex); @@ -647,7 +811,7 @@ { int vol_id; - dbg_msg("remove volume"); + dbg_gen("remove volume"); err = get_user(vol_id, (__user int32_t *)argp); if (err) { err = -EFAULT; @@ -661,7 +825,7 @@ } mutex_lock(&ubi->volumes_mutex); - err = ubi_remove_volume(desc); + err = ubi_remove_volume(desc, 0); mutex_unlock(&ubi->volumes_mutex); /* @@ -680,7 +844,7 @@ uint64_t tmp; struct ubi_rsvol_req req; - dbg_msg("re-size volume"); + dbg_gen("re-size volume"); err = copy_from_user(&req, argp, sizeof(struct ubi_rsvol_req)); if (err) { err = -EFAULT; @@ -708,6 +872,32 @@ break; } + /* Re-name volumes command */ + case UBI_IOCRNVOL: + { + struct ubi_rnvol_req *req; + + dbg_msg("re-name volumes"); + req = kmalloc(sizeof(struct ubi_rnvol_req), GFP_KERNEL); + if (!req) { + err = -ENOMEM; + break; + }; + + err = copy_from_user(req, argp, sizeof(struct ubi_rnvol_req)); + if (err) { + err = -EFAULT; + kfree(req); + break; + } + + mutex_lock(&ubi->mult_mutex); + err = rename_volumes(ubi, req); + mutex_unlock(&ubi->mult_mutex); + kfree(req); + break; + } + default: err = -ENOTTY; break; @@ -733,7 +923,7 @@ struct ubi_attach_req req; struct mtd_info *mtd; - dbg_msg("attach MTD device"); + dbg_gen("attach MTD device"); err = copy_from_user(&req, argp, sizeof(struct ubi_attach_req)); if (err) { err = -EFAULT; @@ -773,7 +963,7 @@ { int ubi_num; - dbg_msg("dettach MTD device"); + dbg_gen("dettach MTD device"); err = get_user(ubi_num, (__user int32_t *)argp); if (err) { err = -EFAULT; diff -urN linux-2.6.26/drivers/mtd/ubi/debug.c linux-2.6.26-lab126/drivers/mtd/ubi/debug.c --- linux-2.6.26/drivers/mtd/ubi/debug.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/ubi/debug.c 2010-08-10 04:15:31.000000000 -0400 @@ -24,7 +24,7 @@ * changes. */ -#ifdef CONFIG_MTD_UBI_DEBUG_MSG +#ifdef CONFIG_MTD_UBI_DEBUG #include "ubi.h" @@ -34,14 +34,19 @@ */ void ubi_dbg_dump_ec_hdr(const struct ubi_ec_hdr *ec_hdr) { - dbg_msg("erase counter header dump:"); - dbg_msg("magic %#08x", be32_to_cpu(ec_hdr->magic)); - dbg_msg("version %d", (int)ec_hdr->version); - dbg_msg("ec %llu", (long long)be64_to_cpu(ec_hdr->ec)); - dbg_msg("vid_hdr_offset %d", be32_to_cpu(ec_hdr->vid_hdr_offset)); - dbg_msg("data_offset %d", be32_to_cpu(ec_hdr->data_offset)); - dbg_msg("hdr_crc %#08x", be32_to_cpu(ec_hdr->hdr_crc)); - dbg_msg("erase counter header hexdump:"); + printk(KERN_DEBUG "Erase counter header dump:\n"); + printk(KERN_DEBUG "\tmagic %#08x\n", + be32_to_cpu(ec_hdr->magic)); + printk(KERN_DEBUG "\tversion %d\n", (int)ec_hdr->version); + printk(KERN_DEBUG "\tec %llu\n", + (long long)be64_to_cpu(ec_hdr->ec)); + printk(KERN_DEBUG "\tvid_hdr_offset %d\n", + be32_to_cpu(ec_hdr->vid_hdr_offset)); + printk(KERN_DEBUG "\tdata_offset %d\n", + be32_to_cpu(ec_hdr->data_offset)); + printk(KERN_DEBUG "\thdr_crc %#08x\n", + be32_to_cpu(ec_hdr->hdr_crc)); + printk(KERN_DEBUG "erase counter header hexdump:\n"); print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, ec_hdr, UBI_EC_HDR_SIZE, 1); } @@ -52,22 +57,23 @@ */ void ubi_dbg_dump_vid_hdr(const struct ubi_vid_hdr *vid_hdr) { - dbg_msg("volume identifier header dump:"); - dbg_msg("magic %08x", be32_to_cpu(vid_hdr->magic)); - dbg_msg("version %d", (int)vid_hdr->version); - dbg_msg("vol_type %d", (int)vid_hdr->vol_type); - dbg_msg("copy_flag %d", (int)vid_hdr->copy_flag); - dbg_msg("compat %d", (int)vid_hdr->compat); - dbg_msg("vol_id %d", be32_to_cpu(vid_hdr->vol_id)); - dbg_msg("lnum %d", be32_to_cpu(vid_hdr->lnum)); - dbg_msg("leb_ver %u", be32_to_cpu(vid_hdr->leb_ver)); - dbg_msg("data_size %d", be32_to_cpu(vid_hdr->data_size)); - dbg_msg("used_ebs %d", be32_to_cpu(vid_hdr->used_ebs)); - dbg_msg("data_pad %d", be32_to_cpu(vid_hdr->data_pad)); - dbg_msg("sqnum %llu", + printk(KERN_DEBUG "Volume identifier header dump:\n"); + printk(KERN_DEBUG "\tmagic %08x\n", be32_to_cpu(vid_hdr->magic)); + printk(KERN_DEBUG "\tversion %d\n", (int)vid_hdr->version); + printk(KERN_DEBUG "\tvol_type %d\n", (int)vid_hdr->vol_type); + printk(KERN_DEBUG "\tcopy_flag %d\n", (int)vid_hdr->copy_flag); + printk(KERN_DEBUG "\tcompat %d\n", (int)vid_hdr->compat); + printk(KERN_DEBUG "\tvol_id %d\n", be32_to_cpu(vid_hdr->vol_id)); + printk(KERN_DEBUG "\tlnum %d\n", be32_to_cpu(vid_hdr->lnum)); + printk(KERN_DEBUG "\tdata_size %d\n", be32_to_cpu(vid_hdr->data_size)); + printk(KERN_DEBUG "\tused_ebs %d\n", be32_to_cpu(vid_hdr->used_ebs)); + printk(KERN_DEBUG "\tdata_pad %d\n", be32_to_cpu(vid_hdr->data_pad)); + printk(KERN_DEBUG "\tsqnum %llu\n", (unsigned long long)be64_to_cpu(vid_hdr->sqnum)); - dbg_msg("hdr_crc %08x", be32_to_cpu(vid_hdr->hdr_crc)); - dbg_msg("volume identifier header hexdump:"); + printk(KERN_DEBUG "\thdr_crc %08x\n", be32_to_cpu(vid_hdr->hdr_crc)); + printk(KERN_DEBUG "Volume identifier header hexdump:\n"); + print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, + vid_hdr, UBI_VID_HDR_SIZE, 1); } /** @@ -76,27 +82,27 @@ */ void ubi_dbg_dump_vol_info(const struct ubi_volume *vol) { - dbg_msg("volume information dump:"); - dbg_msg("vol_id %d", vol->vol_id); - dbg_msg("reserved_pebs %d", vol->reserved_pebs); - dbg_msg("alignment %d", vol->alignment); - dbg_msg("data_pad %d", vol->data_pad); - dbg_msg("vol_type %d", vol->vol_type); - dbg_msg("name_len %d", vol->name_len); - dbg_msg("usable_leb_size %d", vol->usable_leb_size); - dbg_msg("used_ebs %d", vol->used_ebs); - dbg_msg("used_bytes %lld", vol->used_bytes); - dbg_msg("last_eb_bytes %d", vol->last_eb_bytes); - dbg_msg("corrupted %d", vol->corrupted); - dbg_msg("upd_marker %d", vol->upd_marker); + printk(KERN_DEBUG "Volume information dump:\n"); + printk(KERN_DEBUG "\tvol_id %d\n", vol->vol_id); + printk(KERN_DEBUG "\treserved_pebs %d\n", vol->reserved_pebs); + printk(KERN_DEBUG "\talignment %d\n", vol->alignment); + printk(KERN_DEBUG "\tdata_pad %d\n", vol->data_pad); + printk(KERN_DEBUG "\tvol_type %d\n", vol->vol_type); + printk(KERN_DEBUG "\tname_len %d\n", vol->name_len); + printk(KERN_DEBUG "\tusable_leb_size %d\n", vol->usable_leb_size); + printk(KERN_DEBUG "\tused_ebs %d\n", vol->used_ebs); + printk(KERN_DEBUG "\tused_bytes %lld\n", vol->used_bytes); + printk(KERN_DEBUG "\tlast_eb_bytes %d\n", vol->last_eb_bytes); + printk(KERN_DEBUG "\tcorrupted %d\n", vol->corrupted); + printk(KERN_DEBUG "\tupd_marker %d\n", vol->upd_marker); if (vol->name_len <= UBI_VOL_NAME_MAX && strnlen(vol->name, vol->name_len + 1) == vol->name_len) { - dbg_msg("name %s", vol->name); + printk(KERN_DEBUG "\tname %s\n", vol->name); } else { - dbg_msg("the 1st 5 characters of the name: %c%c%c%c%c", - vol->name[0], vol->name[1], vol->name[2], - vol->name[3], vol->name[4]); + printk(KERN_DEBUG "\t1st 5 characters of name: %c%c%c%c%c\n", + vol->name[0], vol->name[1], vol->name[2], + vol->name[3], vol->name[4]); } } @@ -109,28 +115,29 @@ { int name_len = be16_to_cpu(r->name_len); - dbg_msg("volume table record %d dump:", idx); - dbg_msg("reserved_pebs %d", be32_to_cpu(r->reserved_pebs)); - dbg_msg("alignment %d", be32_to_cpu(r->alignment)); - dbg_msg("data_pad %d", be32_to_cpu(r->data_pad)); - dbg_msg("vol_type %d", (int)r->vol_type); - dbg_msg("upd_marker %d", (int)r->upd_marker); - dbg_msg("name_len %d", name_len); + printk(KERN_DEBUG "Volume table record %d dump:\n", idx); + printk(KERN_DEBUG "\treserved_pebs %d\n", + be32_to_cpu(r->reserved_pebs)); + printk(KERN_DEBUG "\talignment %d\n", be32_to_cpu(r->alignment)); + printk(KERN_DEBUG "\tdata_pad %d\n", be32_to_cpu(r->data_pad)); + printk(KERN_DEBUG "\tvol_type %d\n", (int)r->vol_type); + printk(KERN_DEBUG "\tupd_marker %d\n", (int)r->upd_marker); + printk(KERN_DEBUG "\tname_len %d\n", name_len); if (r->name[0] == '\0') { - dbg_msg("name NULL"); + printk(KERN_DEBUG "\tname NULL\n"); return; } if (name_len <= UBI_VOL_NAME_MAX && strnlen(&r->name[0], name_len + 1) == name_len) { - dbg_msg("name %s", &r->name[0]); + printk(KERN_DEBUG "\tname %s\n", &r->name[0]); } else { - dbg_msg("1st 5 characters of the name: %c%c%c%c%c", + printk(KERN_DEBUG "\t1st 5 characters of name: %c%c%c%c%c\n", r->name[0], r->name[1], r->name[2], r->name[3], r->name[4]); } - dbg_msg("crc %#08x", be32_to_cpu(r->crc)); + printk(KERN_DEBUG "\tcrc %#08x\n", be32_to_cpu(r->crc)); } /** @@ -139,15 +146,15 @@ */ void ubi_dbg_dump_sv(const struct ubi_scan_volume *sv) { - dbg_msg("volume scanning information dump:"); - dbg_msg("vol_id %d", sv->vol_id); - dbg_msg("highest_lnum %d", sv->highest_lnum); - dbg_msg("leb_count %d", sv->leb_count); - dbg_msg("compat %d", sv->compat); - dbg_msg("vol_type %d", sv->vol_type); - dbg_msg("used_ebs %d", sv->used_ebs); - dbg_msg("last_data_size %d", sv->last_data_size); - dbg_msg("data_pad %d", sv->data_pad); + printk(KERN_DEBUG "Volume scanning information dump:\n"); + printk(KERN_DEBUG "\tvol_id %d\n", sv->vol_id); + printk(KERN_DEBUG "\thighest_lnum %d\n", sv->highest_lnum); + printk(KERN_DEBUG "\tleb_count %d\n", sv->leb_count); + printk(KERN_DEBUG "\tcompat %d\n", sv->compat); + printk(KERN_DEBUG "\tvol_type %d\n", sv->vol_type); + printk(KERN_DEBUG "\tused_ebs %d\n", sv->used_ebs); + printk(KERN_DEBUG "\tlast_data_size %d\n", sv->last_data_size); + printk(KERN_DEBUG "\tdata_pad %d\n", sv->data_pad); } /** @@ -157,14 +164,13 @@ */ void ubi_dbg_dump_seb(const struct ubi_scan_leb *seb, int type) { - dbg_msg("eraseblock scanning information dump:"); - dbg_msg("ec %d", seb->ec); - dbg_msg("pnum %d", seb->pnum); + printk(KERN_DEBUG "eraseblock scanning information dump:\n"); + printk(KERN_DEBUG "\tec %d\n", seb->ec); + printk(KERN_DEBUG "\tpnum %d\n", seb->pnum); if (type == 0) { - dbg_msg("lnum %d", seb->lnum); - dbg_msg("scrub %d", seb->scrub); - dbg_msg("sqnum %llu", seb->sqnum); - dbg_msg("leb_ver %u", seb->leb_ver); + printk(KERN_DEBUG "\tlnum %d\n", seb->lnum); + printk(KERN_DEBUG "\tscrub %d\n", seb->scrub); + printk(KERN_DEBUG "\tsqnum %llu\n", seb->sqnum); } } @@ -176,16 +182,16 @@ { char nm[17]; - dbg_msg("volume creation request dump:"); - dbg_msg("vol_id %d", req->vol_id); - dbg_msg("alignment %d", req->alignment); - dbg_msg("bytes %lld", (long long)req->bytes); - dbg_msg("vol_type %d", req->vol_type); - dbg_msg("name_len %d", req->name_len); + printk(KERN_DEBUG "Volume creation request dump:\n"); + printk(KERN_DEBUG "\tvol_id %d\n", req->vol_id); + printk(KERN_DEBUG "\talignment %d\n", req->alignment); + printk(KERN_DEBUG "\tbytes %lld\n", (long long)req->bytes); + printk(KERN_DEBUG "\tvol_type %d\n", req->vol_type); + printk(KERN_DEBUG "\tname_len %d\n", req->name_len); memcpy(nm, req->name, 16); nm[16] = 0; - dbg_msg("the 1st 16 characters of the name: %s", nm); + printk(KERN_DEBUG "\t1st 16 characters of name: %s\n", nm); } -#endif /* CONFIG_MTD_UBI_DEBUG_MSG */ +#endif /* CONFIG_MTD_UBI_DEBUG */ diff -urN linux-2.6.26/drivers/mtd/ubi/debug.h linux-2.6.26-lab126/drivers/mtd/ubi/debug.h --- linux-2.6.26/drivers/mtd/ubi/debug.h 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/ubi/debug.h 2010-08-10 04:15:31.000000000 -0400 @@ -24,21 +24,16 @@ #ifdef CONFIG_MTD_UBI_DEBUG #include -#define ubi_assert(expr) BUG_ON(!(expr)) #define dbg_err(fmt, ...) ubi_err(fmt, ##__VA_ARGS__) -#else -#define ubi_assert(expr) ({}) -#define dbg_err(fmt, ...) ({}) -#endif -#ifdef CONFIG_MTD_UBI_DEBUG_DISABLE_BGT -#define DBG_DISABLE_BGT 1 -#else -#define DBG_DISABLE_BGT 0 -#endif +#define ubi_assert(expr) do { \ + if (unlikely(!(expr))) { \ + printk(KERN_CRIT "UBI assert failed in %s at %u (pid %d)\n", \ + __func__, __LINE__, current->pid); \ + ubi_dbg_dump_stack(); \ + } \ +} while (0) -#ifdef CONFIG_MTD_UBI_DEBUG_MSG -/* Generic debugging message */ #define dbg_msg(fmt, ...) \ printk(KERN_DEBUG "UBI DBG (pid %d): %s: " fmt "\n", \ current->pid, __func__, ##__VA_ARGS__) @@ -61,36 +56,29 @@ void ubi_dbg_dump_seb(const struct ubi_scan_leb *seb, int type); void ubi_dbg_dump_mkvol_req(const struct ubi_mkvol_req *req); +#ifdef CONFIG_MTD_UBI_DEBUG_MSG +/* General debugging messages */ +#define dbg_gen(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) #else - -#define dbg_msg(fmt, ...) ({}) -#define ubi_dbg_dump_stack() ({}) -#define ubi_dbg_dump_ec_hdr(ec_hdr) ({}) -#define ubi_dbg_dump_vid_hdr(vid_hdr) ({}) -#define ubi_dbg_dump_vol_info(vol) ({}) -#define ubi_dbg_dump_vtbl_record(r, idx) ({}) -#define ubi_dbg_dump_sv(sv) ({}) -#define ubi_dbg_dump_seb(seb, type) ({}) -#define ubi_dbg_dump_mkvol_req(req) ({}) - -#endif /* CONFIG_MTD_UBI_DEBUG_MSG */ +#define dbg_gen(fmt, ...) ({}) +#endif #ifdef CONFIG_MTD_UBI_DEBUG_MSG_EBA -/* Messages from the eraseblock association unit */ +/* Messages from the eraseblock association sub-system */ #define dbg_eba(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) #else #define dbg_eba(fmt, ...) ({}) #endif #ifdef CONFIG_MTD_UBI_DEBUG_MSG_WL -/* Messages from the wear-leveling unit */ +/* Messages from the wear-leveling sub-system */ #define dbg_wl(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) #else #define dbg_wl(fmt, ...) ({}) #endif #ifdef CONFIG_MTD_UBI_DEBUG_MSG_IO -/* Messages from the input/output unit */ +/* Messages from the input/output sub-system */ #define dbg_io(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) #else #define dbg_io(fmt, ...) ({}) @@ -105,6 +93,12 @@ #define UBI_IO_DEBUG 0 #endif +#ifdef CONFIG_MTD_UBI_DEBUG_DISABLE_BGT +#define DBG_DISABLE_BGT 1 +#else +#define DBG_DISABLE_BGT 0 +#endif + #ifdef CONFIG_MTD_UBI_DEBUG_EMULATE_BITFLIPS /** * ubi_dbg_is_bitflip - if it is time to emulate a bit-flip. @@ -149,4 +143,30 @@ #define ubi_dbg_is_erase_failure() 0 #endif +#else + +#define ubi_assert(expr) ({}) +#define dbg_err(fmt, ...) ({}) +#define dbg_msg(fmt, ...) ({}) +#define dbg_gen(fmt, ...) ({}) +#define dbg_eba(fmt, ...) ({}) +#define dbg_wl(fmt, ...) ({}) +#define dbg_io(fmt, ...) ({}) +#define dbg_bld(fmt, ...) ({}) +#define ubi_dbg_dump_stack() ({}) +#define ubi_dbg_dump_ec_hdr(ec_hdr) ({}) +#define ubi_dbg_dump_vid_hdr(vid_hdr) ({}) +#define ubi_dbg_dump_vol_info(vol) ({}) +#define ubi_dbg_dump_vtbl_record(r, idx) ({}) +#define ubi_dbg_dump_sv(sv) ({}) +#define ubi_dbg_dump_seb(seb, type) ({}) +#define ubi_dbg_dump_mkvol_req(req) ({}) + +#define UBI_IO_DEBUG 0 +#define DBG_DISABLE_BGT 0 +#define ubi_dbg_is_bitflip() 0 +#define ubi_dbg_is_write_failure() 0 +#define ubi_dbg_is_erase_failure() 0 + +#endif /* !CONFIG_MTD_UBI_DEBUG */ #endif /* !__UBI_DEBUG_H__ */ diff -urN linux-2.6.26/drivers/mtd/ubi/eba.c linux-2.6.26-lab126/drivers/mtd/ubi/eba.c --- linux-2.6.26/drivers/mtd/ubi/eba.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/ubi/eba.c 2010-08-10 04:15:31.000000000 -0400 @@ -19,20 +19,20 @@ */ /* - * The UBI Eraseblock Association (EBA) unit. + * The UBI Eraseblock Association (EBA) sub-system. * - * This unit is responsible for I/O to/from logical eraseblock. + * This sub-system is responsible for I/O to/from logical eraseblock. * * Although in this implementation the EBA table is fully kept and managed in * RAM, which assumes poor scalability, it might be (partially) maintained on * flash in future implementations. * - * The EBA unit implements per-logical eraseblock locking. Before accessing a - * logical eraseblock it is locked for reading or writing. The per-logical - * eraseblock locking is implemented by means of the lock tree. The lock tree - * is an RB-tree which refers all the currently locked logical eraseblocks. The - * lock tree elements are &struct ubi_ltree_entry objects. They are indexed by - * (@vol_id, @lnum) pairs. + * The EBA sub-system implements per-logical eraseblock locking. Before + * accessing a logical eraseblock it is locked for reading or writing. The + * per-logical eraseblock locking is implemented by means of the lock tree. The + * lock tree is an RB-tree which refers all the currently locked logical + * eraseblocks. The lock tree elements are &struct ubi_ltree_entry objects. + * They are indexed by (@vol_id, @lnum) pairs. * * EBA also maintains the global sequence counter which is incremented each * time a logical eraseblock is mapped to a physical eraseblock and it is @@ -189,9 +189,7 @@ le->users += 1; spin_unlock(&ubi->ltree_lock); - if (le_free) - kfree(le_free); - + kfree(le_free); return le; } @@ -223,22 +221,18 @@ */ static void leb_read_unlock(struct ubi_device *ubi, int vol_id, int lnum) { - int free = 0; struct ubi_ltree_entry *le; spin_lock(&ubi->ltree_lock); le = ltree_lookup(ubi, vol_id, lnum); le->users -= 1; ubi_assert(le->users >= 0); + up_read(&le->mutex); if (le->users == 0) { rb_erase(&le->rb, &ubi->ltree); - free = 1; + kfree(le); } spin_unlock(&ubi->ltree_lock); - - up_read(&le->mutex); - if (free) - kfree(le); } /** @@ -274,7 +268,6 @@ */ static int leb_write_trylock(struct ubi_device *ubi, int vol_id, int lnum) { - int free; struct ubi_ltree_entry *le; le = ltree_add_entry(ubi, vol_id, lnum); @@ -289,12 +282,9 @@ ubi_assert(le->users >= 0); if (le->users == 0) { rb_erase(&le->rb, &ubi->ltree); - free = 1; - } else - free = 0; - spin_unlock(&ubi->ltree_lock); - if (free) kfree(le); + } + spin_unlock(&ubi->ltree_lock); return 1; } @@ -307,23 +297,18 @@ */ static void leb_write_unlock(struct ubi_device *ubi, int vol_id, int lnum) { - int free; struct ubi_ltree_entry *le; spin_lock(&ubi->ltree_lock); le = ltree_lookup(ubi, vol_id, lnum); le->users -= 1; ubi_assert(le->users >= 0); + up_write(&le->mutex); if (le->users == 0) { rb_erase(&le->rb, &ubi->ltree); - free = 1; - } else - free = 0; - spin_unlock(&ubi->ltree_lock); - - up_write(&le->mutex); - if (free) kfree(le); + } + spin_unlock(&ubi->ltree_lock); } /** @@ -516,9 +501,8 @@ struct ubi_vid_hdr *vid_hdr; vid_hdr = ubi_zalloc_vid_hdr(ubi, GFP_NOFS); - if (!vid_hdr) { + if (!vid_hdr) return -ENOMEM; - } mutex_lock(&ubi->buf_mutex); @@ -752,7 +736,7 @@ /* If this is the last LEB @len may be unaligned */ len = ALIGN(data_size, ubi->min_io_size); else - ubi_assert(len % ubi->min_io_size == 0); + ubi_assert(!(len & (ubi->min_io_size - 1))); vid_hdr = ubi_zalloc_vid_hdr(ubi, GFP_NOFS); if (!vid_hdr) @@ -919,7 +903,7 @@ } if (vol->eba_tbl[lnum] >= 0) { - err = ubi_wl_put_peb(ubi, vol->eba_tbl[lnum], 1); + err = ubi_wl_put_peb(ubi, vol->eba_tbl[lnum], 0); if (err) goto out_leb_unlock; } @@ -1038,7 +1022,7 @@ } /* - * OK, now the LEB is locked and we can safely start moving iy. Since + * OK, now the LEB is locked and we can safely start moving it. Since * this function utilizes thie @ubi->peb1_buf buffer which is shared * with some other functions, so lock the buffer by taking the * @ubi->buf_mutex. @@ -1141,7 +1125,7 @@ } /** - * ubi_eba_init_scan - initialize the EBA unit using scanning information. + * ubi_eba_init_scan - initialize the EBA sub-system using scanning information. * @ubi: UBI device description object * @si: scanning information * @@ -1156,7 +1140,7 @@ struct ubi_scan_leb *seb; struct rb_node *rb; - dbg_eba("initialize EBA unit"); + dbg_eba("initialize EBA sub-system"); spin_lock_init(&ubi->ltree_lock); mutex_init(&ubi->alc_mutex); @@ -1222,7 +1206,7 @@ ubi->rsvd_pebs += ubi->beb_rsvd_pebs; } - dbg_eba("EBA unit is initialized"); + dbg_eba("EBA sub-system is initialized"); return 0; out_free: @@ -1233,20 +1217,3 @@ } return err; } - -/** - * ubi_eba_close - close EBA unit. - * @ubi: UBI device description object - */ -void ubi_eba_close(const struct ubi_device *ubi) -{ - int i, num_volumes = ubi->vtbl_slots + UBI_INT_VOL_COUNT; - - dbg_eba("close EBA unit"); - - for (i = 0; i < num_volumes; i++) { - if (!ubi->volumes[i]) - continue; - kfree(ubi->volumes[i]->eba_tbl); - } -} diff -urN linux-2.6.26/drivers/mtd/ubi/gluebi.c linux-2.6.26-lab126/drivers/mtd/ubi/gluebi.c --- linux-2.6.26/drivers/mtd/ubi/gluebi.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/ubi/gluebi.c 2010-08-10 04:15:31.000000000 -0400 @@ -111,7 +111,7 @@ struct ubi_device *ubi; uint64_t tmp = from; - dbg_msg("read %zd bytes from offset %lld", len, from); + dbg_gen("read %zd bytes from offset %lld", len, from); if (len < 0 || from < 0 || from + len > mtd->size) return -EINVAL; @@ -162,7 +162,7 @@ struct ubi_device *ubi; uint64_t tmp = to; - dbg_msg("write %zd bytes to offset %lld", len, to); + dbg_gen("write %zd bytes to offset %lld", len, to); if (len < 0 || to < 0 || len + to > mtd->size) return -EINVAL; @@ -215,7 +215,7 @@ struct ubi_volume *vol; struct ubi_device *ubi; - dbg_msg("erase %u bytes at offset %u", instr->len, instr->addr); + dbg_gen("erase %u bytes at offset %u", instr->len, instr->addr); if (instr->addr < 0 || instr->addr > mtd->size - mtd->erasesize) return -EINVAL; @@ -249,8 +249,8 @@ if (err) goto out_err; - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); + instr->state = MTD_ERASE_DONE; + mtd_erase_callback(instr); return 0; out_err: @@ -299,12 +299,12 @@ mtd->size = vol->used_bytes; if (add_mtd_device(mtd)) { - ubi_err("cannot not add MTD device\n"); + ubi_err("cannot not add MTD device"); kfree(mtd->name); return -ENFILE; } - dbg_msg("added mtd%d (\"%s\"), size %u, EB size %u", + dbg_gen("added mtd%d (\"%s\"), size %u, EB size %u", mtd->index, mtd->name, mtd->size, mtd->erasesize); return 0; } @@ -322,7 +322,7 @@ int err; struct mtd_info *mtd = &vol->gluebi_mtd; - dbg_msg("remove mtd%d", mtd->index); + dbg_gen("remove mtd%d", mtd->index); err = del_mtd_device(mtd); if (err) return err; diff -urN linux-2.6.26/drivers/mtd/ubi/io.c linux-2.6.26-lab126/drivers/mtd/ubi/io.c --- linux-2.6.26/drivers/mtd/ubi/io.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/ubi/io.c 2010-08-10 04:15:31.000000000 -0400 @@ -20,15 +20,15 @@ */ /* - * UBI input/output unit. + * UBI input/output sub-system. * - * This unit provides a uniform way to work with all kinds of the underlying - * MTD devices. It also implements handy functions for reading and writing UBI - * headers. + * This sub-system provides a uniform way to work with all kinds of the + * underlying MTD devices. It also implements handy functions for reading and + * writing UBI headers. * * We are trying to have a paranoid mindset and not to trust to what we read - * from the flash media in order to be more secure and robust. So this unit - * validates every single header it reads from the flash media. + * from the flash media in order to be more secure and robust. So this + * sub-system validates every single header it reads from the flash media. * * Some words about how the eraseblock headers are stored. * @@ -79,11 +79,11 @@ * 512-byte chunks, we have to allocate one more buffer and copy our VID header * to offset 448 of this buffer. * - * The I/O unit does the following trick in order to avoid this extra copy. - * It always allocates a @ubi->vid_hdr_alsize bytes buffer for the VID header - * and returns a pointer to offset @ubi->vid_hdr_shift of this buffer. When the - * VID header is being written out, it shifts the VID header pointer back and - * writes the whole sub-page. + * The I/O sub-system does the following trick in order to avoid this extra + * copy. It always allocates a @ubi->vid_hdr_alsize bytes buffer for the VID + * header and returns a pointer to offset @ubi->vid_hdr_shift of this buffer. + * When the VID header is being written out, it shifts the VID header pointer + * back and writes the whole sub-page. */ #include @@ -156,15 +156,19 @@ /* * -EUCLEAN is reported if there was a bit-flip which * was corrected, so this is harmless. + * + * We do not report about it here unless debugging is + * enabled. A corresponding message will be printed + * later, when it is has been scrubbed. */ - ubi_msg("fixable bit-flip detected at PEB %d", pnum); + dbg_msg("fixable bit-flip detected at PEB %d", pnum); ubi_assert(len == read); return UBI_IO_BITFLIPS; } if (read != len && retries++ < UBI_IO_RETRIES) { - dbg_io("error %d while reading %d bytes from PEB %d:%d, " - "read only %zd bytes, retry", + dbg_io("error %d while reading %d bytes from PEB %d:%d," + " read only %zd bytes, retry", err, len, pnum, offset, read); yield(); goto retry; @@ -187,7 +191,7 @@ ubi_assert(len == read); if (ubi_dbg_is_bitflip()) { - dbg_msg("bit-flip (emulated)"); + dbg_gen("bit-flip (emulated)"); err = UBI_IO_BITFLIPS; } } @@ -391,6 +395,7 @@ { int err, i, patt_count; + ubi_msg("run torture test for PEB %d", pnum); patt_count = ARRAY_SIZE(patterns); ubi_assert(patt_count > 0); @@ -434,6 +439,7 @@ } err = patt_count; + ubi_msg("PEB %d passed torture test, do not mark it a bad", pnum); out: mutex_unlock(&ubi->buf_mutex); @@ -699,8 +705,8 @@ if (hdr_crc != crc) { if (verbose) { - ubi_warn("bad EC header CRC at PEB %d, calculated %#08x," - " read %#08x", pnum, crc, hdr_crc); + ubi_warn("bad EC header CRC at PEB %d, calculated " + "%#08x, read %#08x", pnum, crc, hdr_crc); ubi_dbg_dump_ec_hdr(ec_hdr); } return UBI_IO_BAD_EC_HDR; @@ -1095,8 +1101,7 @@ } /** - * paranoid_check_peb_ec_hdr - check that the erase counter header of a - * physical eraseblock is in-place and is all right. + * paranoid_check_peb_ec_hdr - check erase counter header. * @ubi: UBI device description object * @pnum: the physical eraseblock number to check * @@ -1174,8 +1179,7 @@ } /** - * paranoid_check_peb_vid_hdr - check that the volume identifier header of a - * physical eraseblock is in-place and is all right. + * paranoid_check_peb_vid_hdr - check volume identifier header. * @ubi: UBI device description object * @pnum: the physical eraseblock number to check * @@ -1256,7 +1260,7 @@ fail: ubi_err("paranoid check failed for PEB %d", pnum); - dbg_msg("hex dump of the %d-%d region", offset, offset + len); + ubi_msg("hex dump of the %d-%d region", offset, offset + len); print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, ubi->dbg_peb_buf, len, 1); err = 1; diff -urN linux-2.6.26/drivers/mtd/ubi/kapi.c linux-2.6.26-lab126/drivers/mtd/ubi/kapi.c --- linux-2.6.26/drivers/mtd/ubi/kapi.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/ubi/kapi.c 2010-08-10 04:15:31.000000000 -0400 @@ -106,7 +106,7 @@ struct ubi_device *ubi; struct ubi_volume *vol; - dbg_msg("open device %d volume %d, mode %d", ubi_num, vol_id, mode); + dbg_gen("open device %d volume %d, mode %d", ubi_num, vol_id, mode); if (ubi_num < 0 || ubi_num >= UBI_MAX_DEVICES) return ERR_PTR(-EINVAL); @@ -215,7 +215,7 @@ struct ubi_device *ubi; struct ubi_volume_desc *ret; - dbg_msg("open volume %s, mode %d", name, mode); + dbg_gen("open volume %s, mode %d", name, mode); if (!name) return ERR_PTR(-EINVAL); @@ -266,7 +266,7 @@ struct ubi_volume *vol = desc->vol; struct ubi_device *ubi = vol->ubi; - dbg_msg("close volume %d, mode %d", vol->vol_id, desc->mode); + dbg_gen("close volume %d, mode %d", vol->vol_id, desc->mode); spin_lock(&ubi->volumes_lock); switch (desc->mode) { @@ -323,7 +323,7 @@ struct ubi_device *ubi = vol->ubi; int err, vol_id = vol->vol_id; - dbg_msg("read %d bytes from LEB %d:%d:%d", len, vol_id, lnum, offset); + dbg_gen("read %d bytes from LEB %d:%d:%d", len, vol_id, lnum, offset); if (vol_id < 0 || vol_id >= ubi->vtbl_slots || lnum < 0 || lnum >= vol->used_ebs || offset < 0 || len < 0 || @@ -388,7 +388,7 @@ struct ubi_device *ubi = vol->ubi; int vol_id = vol->vol_id; - dbg_msg("write %d bytes to LEB %d:%d:%d", len, vol_id, lnum, offset); + dbg_gen("write %d bytes to LEB %d:%d:%d", len, vol_id, lnum, offset); if (vol_id < 0 || vol_id >= ubi->vtbl_slots) return -EINVAL; @@ -397,8 +397,8 @@ return -EROFS; if (lnum < 0 || lnum >= vol->reserved_pebs || offset < 0 || len < 0 || - offset + len > vol->usable_leb_size || offset % ubi->min_io_size || - len % ubi->min_io_size) + offset + len > vol->usable_leb_size || + offset & (ubi->min_io_size - 1) || len & (ubi->min_io_size - 1)) return -EINVAL; if (dtype != UBI_LONGTERM && dtype != UBI_SHORTTERM && @@ -438,7 +438,7 @@ struct ubi_device *ubi = vol->ubi; int vol_id = vol->vol_id; - dbg_msg("atomically write %d bytes to LEB %d:%d", len, vol_id, lnum); + dbg_gen("atomically write %d bytes to LEB %d:%d", len, vol_id, lnum); if (vol_id < 0 || vol_id >= ubi->vtbl_slots) return -EINVAL; @@ -447,7 +447,7 @@ return -EROFS; if (lnum < 0 || lnum >= vol->reserved_pebs || len < 0 || - len > vol->usable_leb_size || len % ubi->min_io_size) + len > vol->usable_leb_size || len & (ubi->min_io_size - 1)) return -EINVAL; if (dtype != UBI_LONGTERM && dtype != UBI_SHORTTERM && @@ -482,7 +482,7 @@ struct ubi_device *ubi = vol->ubi; int err; - dbg_msg("erase LEB %d:%d", vol->vol_id, lnum); + dbg_gen("erase LEB %d:%d", vol->vol_id, lnum); if (desc->mode == UBI_READONLY || vol->vol_type == UBI_STATIC_VOLUME) return -EROFS; @@ -542,7 +542,7 @@ struct ubi_volume *vol = desc->vol; struct ubi_device *ubi = vol->ubi; - dbg_msg("unmap LEB %d:%d", vol->vol_id, lnum); + dbg_gen("unmap LEB %d:%d", vol->vol_id, lnum); if (desc->mode == UBI_READONLY || vol->vol_type == UBI_STATIC_VOLUME) return -EROFS; @@ -579,7 +579,7 @@ struct ubi_volume *vol = desc->vol; struct ubi_device *ubi = vol->ubi; - dbg_msg("unmap LEB %d:%d", vol->vol_id, lnum); + dbg_gen("unmap LEB %d:%d", vol->vol_id, lnum); if (desc->mode == UBI_READONLY || vol->vol_type == UBI_STATIC_VOLUME) return -EROFS; @@ -621,7 +621,7 @@ { struct ubi_volume *vol = desc->vol; - dbg_msg("test LEB %d:%d", vol->vol_id, lnum); + dbg_gen("test LEB %d:%d", vol->vol_id, lnum); if (lnum < 0 || lnum >= vol->reserved_pebs) return -EINVAL; @@ -632,3 +632,27 @@ return vol->eba_tbl[lnum] >= 0; } EXPORT_SYMBOL_GPL(ubi_is_mapped); + +/** + * ubi_sync - synchronize UBI device buffers. + * @ubi_num: UBI device to synchronize + * + * The underlying MTD device may cache data in hardware or in software. This + * function ensures the caches are flushed. Returns zero in case of success and + * a negative error code in case of failure. + */ +int ubi_sync(int ubi_num) +{ + struct ubi_device *ubi; + + ubi = ubi_get_device(ubi_num); + if (!ubi) + return -ENODEV; + + if (ubi->mtd->sync) + ubi->mtd->sync(ubi->mtd); + + ubi_put_device(ubi); + return 0; +} +EXPORT_SYMBOL_GPL(ubi_sync); diff -urN linux-2.6.26/drivers/mtd/ubi/misc.c linux-2.6.26-lab126/drivers/mtd/ubi/misc.c --- linux-2.6.26/drivers/mtd/ubi/misc.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/ubi/misc.c 2010-08-10 04:15:31.000000000 -0400 @@ -37,7 +37,7 @@ { int i; - ubi_assert(length % ubi->min_io_size == 0); + ubi_assert(!(length & (ubi->min_io_size - 1))); for (i = length - 1; i >= 0; i--) if (((const uint8_t *)buf)[i] != 0xFF) diff -urN linux-2.6.26/drivers/mtd/ubi/scan.c linux-2.6.26-lab126/drivers/mtd/ubi/scan.c --- linux-2.6.26/drivers/mtd/ubi/scan.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/ubi/scan.c 2010-08-10 04:15:31.000000000 -0400 @@ -19,9 +19,9 @@ */ /* - * UBI scanning unit. + * UBI scanning sub-system. * - * This unit is responsible for scanning the flash media, checking UBI + * This sub-system is responsible for scanning the flash media, checking UBI * headers and providing complete information about the UBI flash image. * * The scanning information is represented by a &struct ubi_scan_info' object. @@ -93,8 +93,7 @@ } /** - * validate_vid_hdr - check that volume identifier header is correct and - * consistent. + * validate_vid_hdr - check volume identifier header. * @vid_hdr: the volume identifier header to check * @sv: information about the volume this logical eraseblock belongs to * @pnum: physical eraseblock number the VID header came from @@ -103,7 +102,7 @@ * non-zero if an inconsistency was found and zero if not. * * Note, UBI does sanity check of everything it reads from the flash media. - * Most of the checks are done in the I/O unit. Here we check that the + * Most of the checks are done in the I/O sub-system. Here we check that the * information in the VID header is consistent to the information in other VID * headers of the same volume. */ @@ -247,45 +246,21 @@ struct ubi_vid_hdr *vh = NULL; unsigned long long sqnum2 = be64_to_cpu(vid_hdr->sqnum); - if (seb->sqnum == 0 && sqnum2 == 0) { - long long abs, v1 = seb->leb_ver, v2 = be32_to_cpu(vid_hdr->leb_ver); - + if (sqnum2 == seb->sqnum) { /* - * UBI constantly increases the logical eraseblock version - * number and it can overflow. Thus, we have to bear in mind - * that versions that are close to %0xFFFFFFFF are less then - * versions that are close to %0. - * - * The UBI WL unit guarantees that the number of pending tasks - * is not greater then %0x7FFFFFFF. So, if the difference - * between any two versions is greater or equivalent to - * %0x7FFFFFFF, there was an overflow and the logical - * eraseblock with lower version is actually newer then the one - * with higher version. - * - * FIXME: but this is anyway obsolete and will be removed at - * some point. + * This must be a really ancient UBI image which has been + * created before sequence numbers support has been added. At + * that times we used 32-bit LEB versions stored in logical + * eraseblocks. That was before UBI got into mainline. We do not + * support these images anymore. Well, those images will work + * still work, but only if no unclean reboots happened. */ - dbg_bld("using old crappy leb_ver stuff"); - - if (v1 == v2) { - ubi_err("PEB %d and PEB %d have the same version %lld", - seb->pnum, pnum, v1); - return -EINVAL; - } + ubi_err("unsupported on-flash UBI format\n"); + return -EINVAL; + } - abs = v1 - v2; - if (abs < 0) - abs = -abs; - - if (abs < 0x7FFFFFFF) - /* Non-overflow situation */ - second_is_newer = (v2 > v1); - else - second_is_newer = (v2 < v1); - } else - /* Obviously the LEB with lower sequence counter is older */ - second_is_newer = sqnum2 > seb->sqnum; + /* Obviously the LEB with lower sequence counter is older */ + second_is_newer = !!(sqnum2 > seb->sqnum); /* * Now we know which copy is newer. If the copy flag of the PEB with @@ -293,7 +268,7 @@ * check data CRC. For the second PEB we already have the VID header, * for the first one - we'll need to re-read it from flash. * - * FIXME: this may be optimized so that we wouldn't read twice. + * Note: this may be optimized so that we wouldn't read twice. */ if (second_is_newer) { @@ -345,7 +320,7 @@ } err = ubi_io_read_data(ubi, buf, pnum, 0, len); - if (err && err != UBI_IO_BITFLIPS) + if (err && err != UBI_IO_BITFLIPS && err != -EBADMSG) goto out_free_buf; data_crc = be32_to_cpu(vid_hdr->data_crc); @@ -379,8 +354,7 @@ } /** - * ubi_scan_add_used - add information about a physical eraseblock to the - * scanning information. + * ubi_scan_add_used - add physical eraseblock to the scanning information. * @ubi: UBI device description object * @si: scanning information * @pnum: the physical eraseblock number @@ -400,7 +374,6 @@ int bitflips) { int err, vol_id, lnum; - uint32_t leb_ver; unsigned long long sqnum; struct ubi_scan_volume *sv; struct ubi_scan_leb *seb; @@ -409,13 +382,12 @@ vol_id = be32_to_cpu(vid_hdr->vol_id); lnum = be32_to_cpu(vid_hdr->lnum); sqnum = be64_to_cpu(vid_hdr->sqnum); - leb_ver = be32_to_cpu(vid_hdr->leb_ver); - dbg_bld("PEB %d, LEB %d:%d, EC %d, sqnum %llu, ver %u, bitflips %d", - pnum, vol_id, lnum, ec, sqnum, leb_ver, bitflips); + dbg_bld("PEB %d, LEB %d:%d, EC %d, sqnum %llu, bitflips %d", + pnum, vol_id, lnum, ec, sqnum, bitflips); sv = add_volume(si, vol_id, pnum, vid_hdr); - if (IS_ERR(sv) < 0) + if (IS_ERR(sv)) return PTR_ERR(sv); if (si->max_sqnum < sqnum) @@ -445,25 +417,20 @@ */ dbg_bld("this LEB already exists: PEB %d, sqnum %llu, " - "LEB ver %u, EC %d", seb->pnum, seb->sqnum, - seb->leb_ver, seb->ec); - - /* - * Make sure that the logical eraseblocks have different - * versions. Otherwise the image is bad. - */ - if (seb->leb_ver == leb_ver && leb_ver != 0) { - ubi_err("two LEBs with same version %u", leb_ver); - ubi_dbg_dump_seb(seb, 0); - ubi_dbg_dump_vid_hdr(vid_hdr); - return -EINVAL; - } + "EC %d", seb->pnum, seb->sqnum, seb->ec); /* * Make sure that the logical eraseblocks have different * sequence numbers. Otherwise the image is bad. * - * FIXME: remove 'sqnum != 0' check when leb_ver is removed. + * However, if the sequence number is zero, we assume it must + * be an ancient UBI image from the era when UBI did not have + * sequence numbers. We still can attach these images, unless + * there is a need to distinguish between old and new + * eraseblocks, in which case we'll refuse the image in + * 'compare_lebs()'. In other words, we attach old clean + * images, but refuse attaching old images with duplicated + * logical eraseblocks because there was an unclean reboot. */ if (seb->sqnum == sqnum && sqnum != 0) { ubi_err("two LEBs with same sequence number %llu", @@ -503,7 +470,6 @@ seb->pnum = pnum; seb->scrub = ((cmp_res & 2) || bitflips); seb->sqnum = sqnum; - seb->leb_ver = leb_ver; if (sv->highest_lnum == lnum) sv->last_data_size = @@ -540,7 +506,6 @@ seb->lnum = lnum; seb->sqnum = sqnum; seb->scrub = bitflips; - seb->leb_ver = leb_ver; if (sv->highest_lnum <= lnum) { sv->highest_lnum = lnum; @@ -554,8 +519,7 @@ } /** - * ubi_scan_find_sv - find information about a particular volume in the - * scanning information. + * ubi_scan_find_sv - find volume in the scanning information. * @si: scanning information * @vol_id: the requested volume ID * @@ -584,8 +548,7 @@ } /** - * ubi_scan_find_seb - find information about a particular logical - * eraseblock in the volume scanning information. + * ubi_scan_find_seb - find LEB in the volume scanning information. * @sv: a pointer to the volume scanning information * @lnum: the requested logical eraseblock * @@ -645,9 +608,9 @@ * * This function erases physical eraseblock 'pnum', and writes the erase * counter header to it. This function should only be used on UBI device - * initialization stages, when the EBA unit had not been yet initialized. This - * function returns zero in case of success and a negative error code in case - * of failure. + * initialization stages, when the EBA sub-system had not been yet initialized. + * This function returns zero in case of success and a negative error code in + * case of failure. */ int ubi_scan_erase_peb(struct ubi_device *ubi, const struct ubi_scan_info *si, int pnum, int ec) @@ -687,9 +650,10 @@ * @si: scanning information * * This function returns a free physical eraseblock. It is supposed to be - * called on the UBI initialization stages when the wear-leveling unit is not - * initialized yet. This function picks a physical eraseblocks from one of the - * lists, writes the EC header if it is needed, and removes it from the list. + * called on the UBI initialization stages when the wear-leveling sub-system is + * not initialized yet. This function picks a physical eraseblocks from one of + * the lists, writes the EC header if it is needed, and removes it from the + * list. * * This function returns scanning physical eraseblock information in case of * success and an error code in case of failure. @@ -742,8 +706,7 @@ } /** - * process_eb - read UBI headers, check them and add corresponding data - * to the scanning information. + * process_eb - read, check UBI headers, and add them to scanning information. * @ubi: UBI device description object * @si: scanning information * @pnum: the physical eraseblock number @@ -751,7 +714,8 @@ * This function returns a zero if the physical eraseblock was successfully * handled and a negative error code in case of failure. */ -static int process_eb(struct ubi_device *ubi, struct ubi_scan_info *si, int pnum) +static int process_eb(struct ubi_device *ubi, struct ubi_scan_info *si, + int pnum) { long long uninitialized_var(ec); int err, bitflips = 0, vol_id, ec_corr = 0; @@ -764,8 +728,9 @@ return err; else if (err) { /* - * FIXME: this is actually duty of the I/O unit to initialize - * this, but MTD does not provide enough information. + * FIXME: this is actually duty of the I/O sub-system to + * initialize this, but MTD does not provide enough + * information. */ si->bad_peb_count += 1; return 0; @@ -930,7 +895,7 @@ for (pnum = 0; pnum < ubi->peb_count; pnum++) { cond_resched(); - dbg_msg("process PEB %d", pnum); + dbg_gen("process PEB %d", pnum); err = process_eb(ubi, si, pnum); if (err < 0) goto out_vidh; @@ -1079,8 +1044,7 @@ #ifdef CONFIG_MTD_UBI_DEBUG_PARANOID /** - * paranoid_check_si - check if the scanning information is correct and - * consistent. + * paranoid_check_si - check the scanning information. * @ubi: UBI device description object * @si: scanning information * @@ -1265,11 +1229,6 @@ ubi_err("bad data_pad %d", sv->data_pad); goto bad_vid_hdr; } - - if (seb->leb_ver != be32_to_cpu(vidh->leb_ver)) { - ubi_err("bad leb_ver %u", seb->leb_ver); - goto bad_vid_hdr; - } } if (!last_seb) @@ -1299,8 +1258,7 @@ if (err < 0) { kfree(buf); return err; - } - else if (err) + } else if (err) buf[pnum] = 1; } diff -urN linux-2.6.26/drivers/mtd/ubi/scan.h linux-2.6.26-lab126/drivers/mtd/ubi/scan.h --- linux-2.6.26/drivers/mtd/ubi/scan.h 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/ubi/scan.h 2010-08-10 04:15:31.000000000 -0400 @@ -34,7 +34,6 @@ * @u: unions RB-tree or @list links * @u.rb: link in the per-volume RB-tree of &struct ubi_scan_leb objects * @u.list: link in one of the eraseblock lists - * @leb_ver: logical eraseblock version (obsolete) * * One object of this type is allocated for each physical eraseblock during * scanning. @@ -49,7 +48,6 @@ struct rb_node rb; struct list_head list; } u; - uint32_t leb_ver; }; /** @@ -59,16 +57,16 @@ * @leb_count: number of logical eraseblocks in this volume * @vol_type: volume type * @used_ebs: number of used logical eraseblocks in this volume (only for - * static volumes) + * static volumes) * @last_data_size: amount of data in the last logical eraseblock of this - * volume (always equivalent to the usable logical eraseblock size in case of - * dynamic volumes) + * volume (always equivalent to the usable logical eraseblock + * size in case of dynamic volumes) * @data_pad: how many bytes at the end of logical eraseblocks of this volume - * are not used (due to volume alignment) + * are not used (due to volume alignment) * @compat: compatibility flags of this volume * @rb: link in the volume RB-tree * @root: root of the RB-tree containing all the eraseblock belonging to this - * volume (&struct ubi_scan_leb objects) + * volume (&struct ubi_scan_leb objects) * * One object of this type is allocated for each volume during scanning. */ @@ -92,8 +90,8 @@ * @free: list of free physical eraseblocks * @erase: list of physical eraseblocks which have to be erased * @alien: list of physical eraseblocks which should not be used by UBI (e.g., + * those belonging to "preserve"-compatible internal volumes) * @bad_peb_count: count of bad physical eraseblocks - * those belonging to "preserve"-compatible internal volumes) * @vols_found: number of volumes found during scanning * @highest_vol_id: highest volume ID * @alien_peb_count: count of physical eraseblocks in the @alien list @@ -106,8 +104,8 @@ * @ec_count: a temporary variable used when calculating @mean_ec * * This data structure contains the result of scanning and may be used by other - * UBI units to build final UBI data structures, further error-recovery and so - * on. + * UBI sub-systems to build final UBI data structures, further error-recovery + * and so on. */ struct ubi_scan_info { struct rb_root volumes; @@ -132,8 +130,7 @@ struct ubi_vid_hdr; /* - * ubi_scan_move_to_list - move a physical eraseblock from the volume tree to a - * list. + * ubi_scan_move_to_list - move a PEB from the volume tree to a list. * * @sv: volume scanning information * @seb: scanning eraseblock infprmation diff -urN linux-2.6.26/drivers/mtd/ubi/ubi-media.h linux-2.6.26-lab126/drivers/mtd/ubi/ubi-media.h --- linux-2.6.26/drivers/mtd/ubi/ubi-media.h 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/ubi/ubi-media.h 2010-08-10 04:15:31.000000000 -0400 @@ -98,10 +98,11 @@ * Compatibility constants used by internal volumes. * * @UBI_COMPAT_DELETE: delete this internal volume before anything is written - * to the flash + * to the flash * @UBI_COMPAT_RO: attach this device in read-only mode * @UBI_COMPAT_PRESERVE: preserve this internal volume - do not touch its - * physical eraseblocks, don't allow the wear-leveling unit to move them + * physical eraseblocks, don't allow the wear-leveling + * sub-system to move them * @UBI_COMPAT_REJECT: reject this UBI image */ enum { @@ -123,7 +124,7 @@ * struct ubi_ec_hdr - UBI erase counter header. * @magic: erase counter header magic number (%UBI_EC_HDR_MAGIC) * @version: version of UBI implementation which is supposed to accept this - * UBI image + * UBI image * @padding1: reserved for future, zeroes * @ec: the erase counter * @vid_hdr_offset: where the VID header starts @@ -159,24 +160,23 @@ * struct ubi_vid_hdr - on-flash UBI volume identifier header. * @magic: volume identifier header magic number (%UBI_VID_HDR_MAGIC) * @version: UBI implementation version which is supposed to accept this UBI - * image (%UBI_VERSION) + * image (%UBI_VERSION) * @vol_type: volume type (%UBI_VID_DYNAMIC or %UBI_VID_STATIC) * @copy_flag: if this logical eraseblock was copied from another physical - * eraseblock (for wear-leveling reasons) + * eraseblock (for wear-leveling reasons) * @compat: compatibility of this volume (%0, %UBI_COMPAT_DELETE, - * %UBI_COMPAT_IGNORE, %UBI_COMPAT_PRESERVE, or %UBI_COMPAT_REJECT) + * %UBI_COMPAT_IGNORE, %UBI_COMPAT_PRESERVE, or %UBI_COMPAT_REJECT) * @vol_id: ID of this volume * @lnum: logical eraseblock number - * @leb_ver: version of this logical eraseblock (IMPORTANT: obsolete, to be - * removed, kept only for not breaking older UBI users) + * @padding1: reserved for future, zeroes * @data_size: how many bytes of data this logical eraseblock contains * @used_ebs: total number of used logical eraseblocks in this volume * @data_pad: how many bytes at the end of this physical eraseblock are not - * used + * used * @data_crc: CRC checksum of the data stored in this logical eraseblock - * @padding1: reserved for future, zeroes - * @sqnum: sequence number * @padding2: reserved for future, zeroes + * @sqnum: sequence number + * @padding3: reserved for future, zeroes * @hdr_crc: volume identifier header CRC checksum * * The @sqnum is the value of the global sequence counter at the time when this @@ -224,10 +224,6 @@ * checksum is correct, this physical eraseblock is selected (P1). Otherwise * the older one (P) is selected. * - * Note, there is an obsolete @leb_ver field which was used instead of @sqnum - * in the past. But it is not used anymore and we keep it in order to be able - * to deal with old UBI images. It will be removed at some point. - * * There are 2 sorts of volumes in UBI: user volumes and internal volumes. * Internal volumes are not seen from outside and are used for various internal * UBI purposes. In this implementation there is only one internal volume - the @@ -248,9 +244,9 @@ * The @data_crc field contains the CRC checksum of the contents of the logical * eraseblock if this is a static volume. In case of dynamic volumes, it does * not contain the CRC checksum as a rule. The only exception is when the - * data of the physical eraseblock was moved by the wear-leveling unit, then - * the wear-leveling unit calculates the data CRC and stores it in the - * @data_crc field. And of course, the @copy_flag is %in this case. + * data of the physical eraseblock was moved by the wear-leveling sub-system, + * then the wear-leveling sub-system calculates the data CRC and stores it in + * the @data_crc field. And of course, the @copy_flag is %in this case. * * The @data_size field is used only for static volumes because UBI has to know * how many bytes of data are stored in this eraseblock. For dynamic volumes, @@ -277,14 +273,14 @@ __u8 compat; __be32 vol_id; __be32 lnum; - __be32 leb_ver; /* obsolete, to be removed, don't use */ + __u8 padding1[4]; __be32 data_size; __be32 used_ebs; __be32 data_pad; __be32 data_crc; - __u8 padding1[4]; + __u8 padding2[4]; __be64 sqnum; - __u8 padding2[12]; + __u8 padding3[12]; __be32 hdr_crc; } __attribute__ ((packed)); diff -urN linux-2.6.26/drivers/mtd/ubi/ubi.h linux-2.6.26-lab126/drivers/mtd/ubi/ubi.h --- linux-2.6.26/drivers/mtd/ubi/ubi.h 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/ubi/ubi.h 2010-08-10 04:15:31.000000000 -0400 @@ -74,15 +74,15 @@ #define UBI_IO_RETRIES 3 /* - * Error codes returned by the I/O unit. + * Error codes returned by the I/O sub-system. * * UBI_IO_PEB_EMPTY: the physical eraseblock is empty, i.e. it contains only - * 0xFF bytes + * %0xFF bytes * UBI_IO_PEB_FREE: the physical eraseblock is free, i.e. it contains only a - * valid erase counter header, and the rest are %0xFF bytes + * valid erase counter header, and the rest are %0xFF bytes * UBI_IO_BAD_EC_HDR: the erase counter header is corrupted (bad magic or CRC) * UBI_IO_BAD_VID_HDR: the volume identifier header is corrupted (bad magic or - * CRC) + * CRC) * UBI_IO_BITFLIPS: bit-flips were detected and corrected */ enum { @@ -99,9 +99,9 @@ * @ec: erase counter * @pnum: physical eraseblock number * - * This data structure is used in the WL unit. Each physical eraseblock has a - * corresponding &struct wl_entry object which may be kept in different - * RB-trees. See WL unit for details. + * This data structure is used in the WL sub-system. Each physical eraseblock + * has a corresponding &struct wl_entry object which may be kept in different + * RB-trees. See WL sub-system for details. */ struct ubi_wl_entry { struct rb_node rb; @@ -118,10 +118,10 @@ * @mutex: read/write mutex to implement read/write access serialization to * the (@vol_id, @lnum) logical eraseblock * - * This data structure is used in the EBA unit to implement per-LEB locking. - * When a logical eraseblock is being locked - corresponding + * This data structure is used in the EBA sub-system to implement per-LEB + * locking. When a logical eraseblock is being locked - corresponding * &struct ubi_ltree_entry object is inserted to the lock tree (@ubi->ltree). - * See EBA unit for details. + * See EBA sub-system for details. */ struct ubi_ltree_entry { struct rb_node rb; @@ -131,6 +131,27 @@ struct rw_semaphore mutex; }; +/** + * struct ubi_rename_entry - volume re-name description data structure. + * @new_name_len: new volume name length + * @new_name: new volume name + * @remove: if not zero, this volume should be removed, not re-named + * @desc: descriptor of the volume + * @list: links re-name entries into a list + * + * This data structure is utilized in the multiple volume re-name code. Namely, + * UBI first creates a list of &struct ubi_rename_entry objects from the + * &struct ubi_rnvol_req request object, and then utilizes this list to do all + * the job. + */ +struct ubi_rename_entry { + int new_name_len; + char new_name[UBI_VOL_NAME_MAX + 1]; + int remove; + struct ubi_volume_desc *desc; + struct list_head list; +}; + struct ubi_volume_desc; /** @@ -206,7 +227,7 @@ int alignment; int data_pad; int name_len; - char name[UBI_VOL_NAME_MAX+1]; + char name[UBI_VOL_NAME_MAX + 1]; int upd_ebs; int ch_lnum; @@ -225,7 +246,7 @@ #ifdef CONFIG_MTD_UBI_GLUEBI /* * Gluebi-related stuff may be compiled out. - * TODO: this should not be built into UBI but should be a separate + * Note: this should not be built into UBI but should be a separate * ubimtd driver which works on top of UBI and emulates MTD devices. */ struct ubi_volume_desc *gluebi_desc; @@ -235,8 +256,7 @@ }; /** - * struct ubi_volume_desc - descriptor of the UBI volume returned when it is - * opened. + * struct ubi_volume_desc - UBI volume descriptor returned when it is opened. * @vol: reference to the corresponding volume description object * @mode: open mode (%UBI_READONLY, %UBI_READWRITE, or %UBI_EXCLUSIVE) */ @@ -273,7 +293,7 @@ * @vtbl_size: size of the volume table in bytes * @vtbl: in-RAM volume table copy * @volumes_mutex: protects on-flash volume table and serializes volume - * changes, like creation, deletion, update, resize + * changes, like creation, deletion, update, re-size and re-name * * @max_ec: current highest erase counter value * @mean_ec: current mean erase counter value @@ -293,6 +313,7 @@ * @move_to, @move_to_put @erase_pending, @wl_scheduled, and @works * fields * @move_mutex: serializes eraseblock moves + * @work_sem: sycnhronizes the WL worker with use tasks * @wl_scheduled: non-zero if the wear-leveling was scheduled * @lookuptbl: a table to quickly find a &struct ubi_wl_entry object for any * physical eraseblock @@ -316,11 +337,11 @@ * @ro_mode: if the UBI device is in read-only mode * @leb_size: logical eraseblock size * @leb_start: starting offset of logical eraseblocks within physical - * eraseblocks + * eraseblocks * @ec_hdr_alsize: size of the EC header aligned to @hdrs_min_io_size * @vid_hdr_alsize: size of the VID header aligned to @hdrs_min_io_size * @vid_hdr_offset: starting offset of the volume identifier header (might be - * unaligned) + * unaligned) * @vid_hdr_aloffset: starting offset of the VID header aligned to * @hdrs_min_io_size * @vid_hdr_shift: contains @vid_hdr_offset - @vid_hdr_aloffset @@ -331,6 +352,8 @@ * @peb_buf1: a buffer of PEB size used for different purposes * @peb_buf2: another buffer of PEB size used for different purposes * @buf_mutex: proptects @peb_buf1 and @peb_buf2 + * @ckvol_mutex: serializes static volume checking when opening + * @mult_mutex: serializes operations on multiple volumes, like re-nameing * @dbg_peb_buf: buffer of PEB size used for debugging * @dbg_buf_mutex: proptects @dbg_peb_buf */ @@ -356,16 +379,16 @@ struct mutex volumes_mutex; int max_ec; - /* TODO: mean_ec is not updated run-time, fix */ + /* Note, mean_ec is not updated run-time - should be fixed */ int mean_ec; - /* EBA unit's stuff */ + /* EBA sub-system's stuff */ unsigned long long global_sqnum; spinlock_t ltree_lock; struct rb_root ltree; struct mutex alc_mutex; - /* Wear-leveling unit's stuff */ + /* Wear-leveling sub-system's stuff */ struct rb_root used; struct rb_root free; struct rb_root scrub; @@ -388,7 +411,7 @@ int thread_enabled; char bgt_name[sizeof(UBI_BGT_NAME_PATTERN)+2]; - /* I/O unit's stuff */ + /* I/O sub-system's stuff */ long long flash_size; int peb_count; int peb_size; @@ -411,6 +434,7 @@ void *peb_buf2; struct mutex buf_mutex; struct mutex ckvol_mutex; + struct mutex mult_mutex; #ifdef CONFIG_MTD_UBI_DEBUG void *dbg_peb_buf; struct mutex dbg_buf_mutex; @@ -427,12 +451,15 @@ /* vtbl.c */ int ubi_change_vtbl_record(struct ubi_device *ubi, int idx, struct ubi_vtbl_record *vtbl_rec); +int ubi_vtbl_rename_volumes(struct ubi_device *ubi, + struct list_head *rename_list); int ubi_read_volume_table(struct ubi_device *ubi, struct ubi_scan_info *si); /* vmt.c */ int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req); -int ubi_remove_volume(struct ubi_volume_desc *desc); +int ubi_remove_volume(struct ubi_volume_desc *desc, int no_vtbl); int ubi_resize_volume(struct ubi_volume_desc *desc, int reserved_pebs); +int ubi_rename_volumes(struct ubi_device *ubi, struct list_head *rename_list); int ubi_add_volume(struct ubi_device *ubi, struct ubi_volume *vol); void ubi_free_volume(struct ubi_device *ubi, struct ubi_volume *vol); @@ -447,7 +474,8 @@ const void __user *buf, int count); /* misc.c */ -int ubi_calc_data_len(const struct ubi_device *ubi, const void *buf, int length); +int ubi_calc_data_len(const struct ubi_device *ubi, const void *buf, + int length); int ubi_check_volume(struct ubi_device *ubi, int vol_id); void ubi_calculate_reserved(struct ubi_device *ubi); @@ -477,7 +505,6 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to, struct ubi_vid_hdr *vid_hdr); int ubi_eba_init_scan(struct ubi_device *ubi, struct ubi_scan_info *si); -void ubi_eba_close(const struct ubi_device *ubi); /* wl.c */ int ubi_wl_get_peb(struct ubi_device *ubi, int dtype); diff -urN linux-2.6.26/drivers/mtd/ubi/upd.c linux-2.6.26-lab126/drivers/mtd/ubi/upd.c --- linux-2.6.26/drivers/mtd/ubi/upd.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/ubi/upd.c 2010-08-10 04:15:31.000000000 -0400 @@ -39,7 +39,7 @@ */ #include -#include +#include #include #include "ubi.h" @@ -56,11 +56,11 @@ int err; struct ubi_vtbl_record vtbl_rec; - dbg_msg("set update marker for volume %d", vol->vol_id); + dbg_gen("set update marker for volume %d", vol->vol_id); if (vol->upd_marker) { ubi_assert(ubi->vtbl[vol->vol_id].upd_marker); - dbg_msg("already set"); + dbg_gen("already set"); return 0; } @@ -92,7 +92,7 @@ uint64_t tmp; struct ubi_vtbl_record vtbl_rec; - dbg_msg("clear update marker for volume %d", vol->vol_id); + dbg_gen("clear update marker for volume %d", vol->vol_id); memcpy(&vtbl_rec, &ubi->vtbl[vol->vol_id], sizeof(struct ubi_vtbl_record)); @@ -133,7 +133,7 @@ int i, err; uint64_t tmp; - dbg_msg("start update of volume %d, %llu bytes", vol->vol_id, bytes); + dbg_gen("start update of volume %d, %llu bytes", vol->vol_id, bytes); ubi_assert(!vol->updating && !vol->changing_leb); vol->updating = 1; @@ -183,7 +183,7 @@ { ubi_assert(!vol->updating && !vol->changing_leb); - dbg_msg("start changing LEB %d:%d, %u bytes", + dbg_gen("start changing LEB %d:%d, %u bytes", vol->vol_id, req->lnum, req->bytes); if (req->bytes == 0) return ubi_eba_atomic_leb_change(ubi, vol, req->lnum, NULL, 0, @@ -237,16 +237,17 @@ int err; if (vol->vol_type == UBI_DYNAMIC_VOLUME) { - len = ALIGN(len, ubi->min_io_size); - memset(buf + len, 0xFF, len - len); + int l = ALIGN(len, ubi->min_io_size); - len = ubi_calc_data_len(ubi, buf, len); + memset(buf + len, 0xFF, l - len); + len = ubi_calc_data_len(ubi, buf, l); if (len == 0) { - dbg_msg("all %d bytes contain 0xFF - skip", len); + dbg_gen("all %d bytes contain 0xFF - skip", len); return 0; } - err = ubi_eba_write_leb(ubi, vol, lnum, buf, 0, len, UBI_UNKNOWN); + err = ubi_eba_write_leb(ubi, vol, lnum, buf, 0, len, + UBI_UNKNOWN); } else { /* * When writing static volume, and this is the last logical @@ -267,6 +268,7 @@ /** * ubi_more_update_data - write more update data. + * @ubi: UBI device description object * @vol: volume description object * @buf: write data (user-space memory buffer) * @count: how much bytes to write @@ -283,7 +285,7 @@ uint64_t tmp; int lnum, offs, err = 0, len, to_write = count; - dbg_msg("write %d of %lld bytes, %lld already passed", + dbg_gen("write %d of %lld bytes, %lld already passed", count, vol->upd_bytes, vol->upd_received); if (ubi->ro_mode) @@ -384,6 +386,7 @@ /** * ubi_more_leb_change_data - accept more data for atomic LEB change. + * @ubi: UBI device description object * @vol: volume description object * @buf: write data (user-space memory buffer) * @count: how much bytes to write @@ -400,7 +403,7 @@ { int err; - dbg_msg("write %d of %lld bytes, %lld already passed", + dbg_gen("write %d of %lld bytes, %lld already passed", count, vol->upd_bytes, vol->upd_received); if (ubi->ro_mode) @@ -418,7 +421,8 @@ if (vol->upd_received == vol->upd_bytes) { int len = ALIGN((int)vol->upd_bytes, ubi->min_io_size); - memset(vol->upd_buf + vol->upd_bytes, 0xFF, len - vol->upd_bytes); + memset(vol->upd_buf + vol->upd_bytes, 0xFF, + len - vol->upd_bytes); len = ubi_calc_data_len(ubi, vol->upd_buf, len); err = ubi_eba_atomic_leb_change(ubi, vol, vol->ch_lnum, vol->upd_buf, len, UBI_UNKNOWN); diff -urN linux-2.6.26/drivers/mtd/ubi/vmt.c linux-2.6.26-lab126/drivers/mtd/ubi/vmt.c --- linux-2.6.26/drivers/mtd/ubi/vmt.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/ubi/vmt.c 2010-08-10 04:15:31.000000000 -0400 @@ -28,9 +28,9 @@ #include "ubi.h" #ifdef CONFIG_MTD_UBI_DEBUG_PARANOID -static void paranoid_check_volumes(struct ubi_device *ubi); +static int paranoid_check_volumes(struct ubi_device *ubi); #else -#define paranoid_check_volumes(ubi) +#define paranoid_check_volumes(ubi) 0 #endif static ssize_t vol_attribute_show(struct device *dev, @@ -127,6 +127,7 @@ { struct ubi_volume *vol = container_of(dev, struct ubi_volume, dev); + kfree(vol->eba_tbl); kfree(vol); } @@ -201,7 +202,7 @@ */ int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req) { - int i, err, vol_id = req->vol_id, dont_free = 0; + int i, err, vol_id = req->vol_id, do_free = 1; struct ubi_volume *vol; struct ubi_vtbl_record vtbl_rec; uint64_t bytes; @@ -217,7 +218,7 @@ spin_lock(&ubi->volumes_lock); if (vol_id == UBI_VOL_NUM_AUTO) { /* Find unused volume ID */ - dbg_msg("search for vacant volume ID"); + dbg_gen("search for vacant volume ID"); for (i = 0; i < ubi->vtbl_slots; i++) if (!ubi->volumes[i]) { vol_id = i; @@ -232,7 +233,7 @@ req->vol_id = vol_id; } - dbg_msg("volume ID %d, %llu bytes, type %d, name %s", + dbg_gen("volume ID %d, %llu bytes, type %d, name %s", vol_id, (unsigned long long)req->bytes, (int)req->vol_type, req->name); @@ -252,7 +253,7 @@ goto out_unlock; } - /* Calculate how many eraseblocks are requested */ + /* Calculate how many eraseblocks are requested */ vol->usable_leb_size = ubi->leb_size - ubi->leb_size % req->alignment; bytes = req->bytes; if (do_div(bytes, vol->usable_leb_size)) @@ -274,7 +275,7 @@ vol->data_pad = ubi->leb_size % vol->alignment; vol->vol_type = req->vol_type; vol->name_len = req->name_len; - memcpy(vol->name, req->name, vol->name_len + 1); + memcpy(vol->name, req->name, vol->name_len); vol->ubi = ubi; /* @@ -349,7 +350,7 @@ vtbl_rec.vol_type = UBI_VID_DYNAMIC; else vtbl_rec.vol_type = UBI_VID_STATIC; - memcpy(vtbl_rec.name, vol->name, vol->name_len + 1); + memcpy(vtbl_rec.name, vol->name, vol->name_len); err = ubi_change_vtbl_record(ubi, vol_id, &vtbl_rec); if (err) @@ -360,19 +361,19 @@ ubi->vol_count += 1; spin_unlock(&ubi->volumes_lock); - paranoid_check_volumes(ubi); - return 0; + err = paranoid_check_volumes(ubi); + return err; out_sysfs: /* - * We have registered our device, we should not free the volume* + * We have registered our device, we should not free the volume * description object in this function in case of an error - it is * freed by the release function. * * Get device reference to prevent the release function from being * called just after sysfs has been closed. */ - dont_free = 1; + do_free = 0; get_device(&vol->dev); volume_sysfs_close(vol); out_gluebi: @@ -382,17 +383,18 @@ out_cdev: cdev_del(&vol->cdev); out_mapping: - kfree(vol->eba_tbl); + if (do_free) + kfree(vol->eba_tbl); out_acc: spin_lock(&ubi->volumes_lock); ubi->rsvd_pebs -= vol->reserved_pebs; ubi->avail_pebs += vol->reserved_pebs; out_unlock: spin_unlock(&ubi->volumes_lock); - if (dont_free) - put_device(&vol->dev); - else + if (do_free) kfree(vol); + else + put_device(&vol->dev); ubi_err("cannot create volume %d, error %d", vol_id, err); return err; } @@ -400,19 +402,20 @@ /** * ubi_remove_volume - remove volume. * @desc: volume descriptor + * @no_vtbl: do not change volume table if not zero * * This function removes volume described by @desc. The volume has to be opened * in "exclusive" mode. Returns zero in case of success and a negative error * code in case of failure. The caller has to have the @ubi->volumes_mutex * locked. */ -int ubi_remove_volume(struct ubi_volume_desc *desc) +int ubi_remove_volume(struct ubi_volume_desc *desc, int no_vtbl) { struct ubi_volume *vol = desc->vol; struct ubi_device *ubi = vol->ubi; int i, err, vol_id = vol->vol_id, reserved_pebs = vol->reserved_pebs; - dbg_msg("remove UBI volume %d", vol_id); + dbg_gen("remove UBI volume %d", vol_id); ubi_assert(desc->mode == UBI_EXCLUSIVE); ubi_assert(vol == ubi->volumes[vol_id]); @@ -435,9 +438,11 @@ if (err) goto out_err; - err = ubi_change_vtbl_record(ubi, vol_id, NULL); - if (err) - goto out_err; + if (!no_vtbl) { + err = ubi_change_vtbl_record(ubi, vol_id, NULL); + if (err) + goto out_err; + } for (i = 0; i < vol->reserved_pebs; i++) { err = ubi_eba_unmap_leb(ubi, vol, i); @@ -445,8 +450,6 @@ goto out_err; } - kfree(vol->eba_tbl); - vol->eba_tbl = NULL; cdev_del(&vol->cdev); volume_sysfs_close(vol); @@ -465,8 +468,9 @@ ubi->vol_count -= 1; spin_unlock(&ubi->volumes_lock); - paranoid_check_volumes(ubi); - return 0; + if (!no_vtbl) + err = paranoid_check_volumes(ubi); + return err; out_err: ubi_err("cannot remove volume %d, error %d", vol_id, err); @@ -497,7 +501,7 @@ if (ubi->ro_mode) return -EROFS; - dbg_msg("re-size volume %d to from %d to %d PEBs", + dbg_gen("re-size volume %d to from %d to %d PEBs", vol_id, vol->reserved_pebs, reserved_pebs); if (vol->vol_type == UBI_STATIC_VOLUME && @@ -586,8 +590,8 @@ (long long)vol->used_ebs * vol->usable_leb_size; } - paranoid_check_volumes(ubi); - return 0; + err = paranoid_check_volumes(ubi); + return err; out_acc: if (pebs > 0) { @@ -602,6 +606,44 @@ } /** + * ubi_rename_volumes - re-name UBI volumes. + * @ubi: UBI device description object + * @rename_list: list of &struct ubi_rename_entry objects + * + * This function re-names or removes volumes specified in the re-name list. + * Returns zero in case of success and a negative error code in case of + * failure. + */ +int ubi_rename_volumes(struct ubi_device *ubi, struct list_head *rename_list) +{ + int err; + struct ubi_rename_entry *re; + + err = ubi_vtbl_rename_volumes(ubi, rename_list); + if (err) + return err; + + list_for_each_entry(re, rename_list, list) { + if (re->remove) { + err = ubi_remove_volume(re->desc, 1); + if (err) + break; + } else { + struct ubi_volume *vol = re->desc->vol; + + spin_lock(&ubi->volumes_lock); + vol->name_len = re->new_name_len; + memcpy(vol->name, re->new_name, re->new_name_len + 1); + spin_unlock(&ubi->volumes_lock); + } + } + + if (!err) + err = paranoid_check_volumes(ubi); + return err; +} + +/** * ubi_add_volume - add volume. * @ubi: UBI device description object * @vol: volume description object @@ -615,8 +657,7 @@ int err, vol_id = vol->vol_id; dev_t dev; - dbg_msg("add volume %d", vol_id); - ubi_dbg_dump_vol_info(vol); + dbg_gen("add volume %d", vol_id); /* Register character device for the volume */ cdev_init(&vol->cdev, &ubi_vol_cdev_operations); @@ -650,8 +691,8 @@ return err; } - paranoid_check_volumes(ubi); - return 0; + err = paranoid_check_volumes(ubi); + return err; out_gluebi: err = ubi_destroy_gluebi(vol); @@ -672,7 +713,7 @@ { int err; - dbg_msg("free volume %d", vol->vol_id); + dbg_gen("free volume %d", vol->vol_id); ubi->volumes[vol->vol_id] = NULL; err = ubi_destroy_gluebi(vol); @@ -686,8 +727,10 @@ * paranoid_check_volume - check volume information. * @ubi: UBI device description object * @vol_id: volume ID + * + * Returns zero if volume is all right and a a negative error code if not. */ -static void paranoid_check_volume(struct ubi_device *ubi, int vol_id) +static int paranoid_check_volume(struct ubi_device *ubi, int vol_id) { int idx = vol_id2idx(ubi, vol_id); int reserved_pebs, alignment, data_pad, vol_type, name_len, upd_marker; @@ -705,16 +748,7 @@ goto fail; } spin_unlock(&ubi->volumes_lock); - return; - } - - if (vol->exclusive) { - /* - * The volume may be being created at the moment, do not check - * it (e.g., it may be in the middle of ubi_create_volume(). - */ - spin_unlock(&ubi->volumes_lock); - return; + return 0; } if (vol->reserved_pebs < 0 || vol->alignment < 0 || vol->data_pad < 0 || @@ -727,7 +761,7 @@ goto fail; } - n = vol->alignment % ubi->min_io_size; + n = vol->alignment & (ubi->min_io_size - 1); if (vol->alignment != 1 && n) { ubi_err("alignment is not multiple of min I/O unit"); goto fail; @@ -824,31 +858,39 @@ if (alignment != vol->alignment || data_pad != vol->data_pad || upd_marker != vol->upd_marker || vol_type != vol->vol_type || - name_len!= vol->name_len || strncmp(name, vol->name, name_len)) { + name_len != vol->name_len || strncmp(name, vol->name, name_len)) { ubi_err("volume info is different"); goto fail; } spin_unlock(&ubi->volumes_lock); - return; + return 0; fail: ubi_err("paranoid check failed for volume %d", vol_id); - ubi_dbg_dump_vol_info(vol); + if (vol) + ubi_dbg_dump_vol_info(vol); ubi_dbg_dump_vtbl_record(&ubi->vtbl[vol_id], vol_id); spin_unlock(&ubi->volumes_lock); - BUG(); + return -EINVAL; } /** * paranoid_check_volumes - check information about all volumes. * @ubi: UBI device description object + * + * Returns zero if volumes are all right and a a negative error code if not. */ -static void paranoid_check_volumes(struct ubi_device *ubi) +static int paranoid_check_volumes(struct ubi_device *ubi) { - int i; + int i, err = 0; - for (i = 0; i < ubi->vtbl_slots; i++) - paranoid_check_volume(ubi, i); + for (i = 0; i < ubi->vtbl_slots; i++) { + err = paranoid_check_volume(ubi, i); + if (err) + break; + } + + return err; } #endif diff -urN linux-2.6.26/drivers/mtd/ubi/vtbl.c linux-2.6.26-lab126/drivers/mtd/ubi/vtbl.c --- linux-2.6.26/drivers/mtd/ubi/vtbl.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/ubi/vtbl.c 2010-08-10 04:15:31.000000000 -0400 @@ -115,8 +115,58 @@ } /** - * vtbl_check - check if volume table is not corrupted and contains sensible - * data. + * ubi_vtbl_rename_volumes - rename UBI volumes in the volume table. + * @ubi: UBI device description object + * @rename_list: list of &struct ubi_rename_entry objects + * + * This function re-names multiple volumes specified in @req in the volume + * table. Returns zero in case of success and a negative error code in case of + * failure. + */ +int ubi_vtbl_rename_volumes(struct ubi_device *ubi, + struct list_head *rename_list) +{ + int i, err; + struct ubi_rename_entry *re; + struct ubi_volume *layout_vol; + + list_for_each_entry(re, rename_list, list) { + uint32_t crc; + struct ubi_volume *vol = re->desc->vol; + struct ubi_vtbl_record *vtbl_rec = &ubi->vtbl[vol->vol_id]; + + if (re->remove) { + memcpy(vtbl_rec, &empty_vtbl_record, + sizeof(struct ubi_vtbl_record)); + continue; + } + + vtbl_rec->name_len = cpu_to_be16(re->new_name_len); + memcpy(vtbl_rec->name, re->new_name, re->new_name_len); + memset(vtbl_rec->name + re->new_name_len, 0, + UBI_VOL_NAME_MAX + 1 - re->new_name_len); + crc = crc32(UBI_CRC32_INIT, vtbl_rec, + UBI_VTBL_RECORD_SIZE_CRC); + vtbl_rec->crc = cpu_to_be32(crc); + } + + layout_vol = ubi->volumes[vol_id2idx(ubi, UBI_LAYOUT_VOLUME_ID)]; + for (i = 0; i < UBI_LAYOUT_VOLUME_EBS; i++) { + err = ubi_eba_unmap_leb(ubi, layout_vol, i); + if (err) + return err; + + err = ubi_eba_write_leb(ubi, layout_vol, i, ubi->vtbl, 0, + ubi->vtbl_size, UBI_LONGTERM); + if (err) + return err; + } + + return 0; +} + +/** + * vtbl_check - check if volume table is not corrupted and sensible. * @ubi: UBI device description object * @vtbl: volume table * @@ -127,7 +177,7 @@ const struct ubi_vtbl_record *vtbl) { int i, n, reserved_pebs, alignment, data_pad, vol_type, name_len; - int upd_marker; + int upd_marker, err; uint32_t crc; const char *name; @@ -153,7 +203,7 @@ if (reserved_pebs == 0) { if (memcmp(&vtbl[i], &empty_vtbl_record, UBI_VTBL_RECORD_SIZE)) { - dbg_err("bad empty record"); + err = 2; goto bad; } continue; @@ -161,56 +211,57 @@ if (reserved_pebs < 0 || alignment < 0 || data_pad < 0 || name_len < 0) { - dbg_err("negative values"); + err = 3; goto bad; } if (alignment > ubi->leb_size || alignment == 0) { - dbg_err("bad alignment"); + err = 4; goto bad; } - n = alignment % ubi->min_io_size; + n = alignment & (ubi->min_io_size - 1); if (alignment != 1 && n) { - dbg_err("alignment is not multiple of min I/O unit"); + err = 5; goto bad; } n = ubi->leb_size % alignment; if (data_pad != n) { dbg_err("bad data_pad, has to be %d", n); + err = 6; goto bad; } if (vol_type != UBI_VID_DYNAMIC && vol_type != UBI_VID_STATIC) { - dbg_err("bad vol_type"); + err = 7; goto bad; } if (upd_marker != 0 && upd_marker != 1) { - dbg_err("bad upd_marker"); + err = 8; goto bad; } if (reserved_pebs > ubi->good_peb_count) { - dbg_err("too large reserved_pebs, good PEBs %d", - ubi->good_peb_count); + dbg_err("too large reserved_pebs %d, good PEBs %d", + reserved_pebs, ubi->good_peb_count); + err = 9; goto bad; } if (name_len > UBI_VOL_NAME_MAX) { - dbg_err("too long volume name, max %d", - UBI_VOL_NAME_MAX); + err = 10; goto bad; } if (name[0] == '\0') { - dbg_err("NULL volume name"); + err = 11; goto bad; } if (name_len != strnlen(name, name_len + 1)) { - dbg_err("bad name_len"); + err = 12; goto bad; } } @@ -235,7 +286,7 @@ return 0; bad: - ubi_err("volume table check failed, record %d", i); + ubi_err("volume table check failed: record %d, error %d", i, err); ubi_dbg_dump_vtbl_record(&vtbl[i], i); return -EINVAL; } @@ -287,7 +338,6 @@ vid_hdr->data_pad = cpu_to_be32(0); vid_hdr->lnum = cpu_to_be32(copy); vid_hdr->sqnum = cpu_to_be64(++si->max_sqnum); - vid_hdr->leb_ver = cpu_to_be32(old_seb ? old_seb->leb_ver + 1: 0); /* The EC header is already there, write the VID header */ err = ubi_io_write_vid_hdr(ubi, new_seb->pnum, vid_hdr); @@ -370,7 +420,7 @@ * to LEB 0. */ - dbg_msg("check layout volume"); + dbg_gen("check layout volume"); /* Read both LEB 0 and LEB 1 into memory */ ubi_rb_for_each_entry(rb, seb, &sv->root, u.rb) { @@ -384,7 +434,16 @@ err = ubi_io_read_data(ubi, leb[seb->lnum], seb->pnum, 0, ubi->vtbl_size); if (err == UBI_IO_BITFLIPS || err == -EBADMSG) - /* Scrub the PEB later */ + /* + * Scrub the PEB later. Note, -EBADMSG indicates an + * uncorrectable ECC error, but we have our own CRC and + * the data will be checked later. If the data is OK, + * the PEB will be scrubbed (because we set + * seb->scrub). If the data is not OK, the contents of + * the PEB will be recovered from the second copy, and + * seb->scrub will be cleared in + * 'ubi_scan_add_used()'. + */ seb->scrub = 1; else if (err) goto out_free; @@ -400,7 +459,8 @@ if (!leb_corrupted[0]) { /* LEB 0 is OK */ if (leb[1]) - leb_corrupted[1] = memcmp(leb[0], leb[1], ubi->vtbl_size); + leb_corrupted[1] = memcmp(leb[0], leb[1], + ubi->vtbl_size); if (leb_corrupted[1]) { ubi_warn("volume table copy #2 is corrupted"); err = create_vtbl(ubi, si, 1, leb[0]); @@ -620,30 +680,32 @@ static int check_sv(const struct ubi_volume *vol, const struct ubi_scan_volume *sv) { + int err; + if (sv->highest_lnum >= vol->reserved_pebs) { - dbg_err("bad highest_lnum"); + err = 1; goto bad; } if (sv->leb_count > vol->reserved_pebs) { - dbg_err("bad leb_count"); + err = 2; goto bad; } if (sv->vol_type != vol->vol_type) { - dbg_err("bad vol_type"); + err = 3; goto bad; } if (sv->used_ebs > vol->reserved_pebs) { - dbg_err("bad used_ebs"); + err = 4; goto bad; } if (sv->data_pad != vol->data_pad) { - dbg_err("bad data_pad"); + err = 5; goto bad; } return 0; bad: - ubi_err("bad scanning information"); + ubi_err("bad scanning information, error %d", err); ubi_dbg_dump_sv(sv); ubi_dbg_dump_vol_info(vol); return -EINVAL; @@ -672,14 +734,13 @@ return -EINVAL; } - if (si->highest_vol_id >= ubi->vtbl_slots + UBI_INT_VOL_COUNT&& + if (si->highest_vol_id >= ubi->vtbl_slots + UBI_INT_VOL_COUNT && si->highest_vol_id < UBI_INTERNAL_VOL_START) { ubi_err("too large volume ID %d found by scanning", si->highest_vol_id); return -EINVAL; } - for (i = 0; i < ubi->vtbl_slots + UBI_INT_VOL_COUNT; i++) { cond_resched(); @@ -717,8 +778,7 @@ } /** - * ubi_read_volume_table - read volume table. - * information. + * ubi_read_volume_table - read the volume table. * @ubi: UBI device description object * @si: scanning information * @@ -797,11 +857,10 @@ out_free: vfree(ubi->vtbl); - for (i = 0; i < ubi->vtbl_slots + UBI_INT_VOL_COUNT; i++) - if (ubi->volumes[i]) { - kfree(ubi->volumes[i]); - ubi->volumes[i] = NULL; - } + for (i = 0; i < ubi->vtbl_slots + UBI_INT_VOL_COUNT; i++) { + kfree(ubi->volumes[i]); + ubi->volumes[i] = NULL; + } return err; } diff -urN linux-2.6.26/drivers/mtd/ubi/wl.c linux-2.6.26-lab126/drivers/mtd/ubi/wl.c --- linux-2.6.26/drivers/mtd/ubi/wl.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/mtd/ubi/wl.c 2010-08-10 04:15:31.000000000 -0400 @@ -19,22 +19,22 @@ */ /* - * UBI wear-leveling unit. + * UBI wear-leveling sub-system. * - * This unit is responsible for wear-leveling. It works in terms of physical - * eraseblocks and erase counters and knows nothing about logical eraseblocks, - * volumes, etc. From this unit's perspective all physical eraseblocks are of - * two types - used and free. Used physical eraseblocks are those that were - * "get" by the 'ubi_wl_get_peb()' function, and free physical eraseblocks are - * those that were put by the 'ubi_wl_put_peb()' function. + * This sub-system is responsible for wear-leveling. It works in terms of + * physical* eraseblocks and erase counters and knows nothing about logical + * eraseblocks, volumes, etc. From this sub-system's perspective all physical + * eraseblocks are of two types - used and free. Used physical eraseblocks are + * those that were "get" by the 'ubi_wl_get_peb()' function, and free physical + * eraseblocks are those that were put by the 'ubi_wl_put_peb()' function. * * Physical eraseblocks returned by 'ubi_wl_get_peb()' have only erase counter - * header. The rest of the physical eraseblock contains only 0xFF bytes. + * header. The rest of the physical eraseblock contains only %0xFF bytes. * - * When physical eraseblocks are returned to the WL unit by means of the + * When physical eraseblocks are returned to the WL sub-system by means of the * 'ubi_wl_put_peb()' function, they are scheduled for erasure. The erasure is * done asynchronously in context of the per-UBI device background thread, - * which is also managed by the WL unit. + * which is also managed by the WL sub-system. * * The wear-leveling is ensured by means of moving the contents of used * physical eraseblocks with low erase counter to free physical eraseblocks @@ -43,34 +43,36 @@ * The 'ubi_wl_get_peb()' function accepts data type hints which help to pick * an "optimal" physical eraseblock. For example, when it is known that the * physical eraseblock will be "put" soon because it contains short-term data, - * the WL unit may pick a free physical eraseblock with low erase counter, and - * so forth. + * the WL sub-system may pick a free physical eraseblock with low erase + * counter, and so forth. * - * If the WL unit fails to erase a physical eraseblock, it marks it as bad. + * If the WL sub-system fails to erase a physical eraseblock, it marks it as + * bad. * - * This unit is also responsible for scrubbing. If a bit-flip is detected in a - * physical eraseblock, it has to be moved. Technically this is the same as - * moving it for wear-leveling reasons. - * - * As it was said, for the UBI unit all physical eraseblocks are either "free" - * or "used". Free eraseblock are kept in the @wl->free RB-tree, while used - * eraseblocks are kept in a set of different RB-trees: @wl->used, + * This sub-system is also responsible for scrubbing. If a bit-flip is detected + * in a physical eraseblock, it has to be moved. Technically this is the same + * as moving it for wear-leveling reasons. + * + * As it was said, for the UBI sub-system all physical eraseblocks are either + * "free" or "used". Free eraseblock are kept in the @wl->free RB-tree, while + * used eraseblocks are kept in a set of different RB-trees: @wl->used, * @wl->prot.pnum, @wl->prot.aec, and @wl->scrub. * * Note, in this implementation, we keep a small in-RAM object for each physical * eraseblock. This is surely not a scalable solution. But it appears to be good * enough for moderately large flashes and it is simple. In future, one may - * re-work this unit and make it more scalable. + * re-work this sub-system and make it more scalable. * - * At the moment this unit does not utilize the sequence number, which was - * introduced relatively recently. But it would be wise to do this because the - * sequence number of a logical eraseblock characterizes how old is it. For + * At the moment this sub-system does not utilize the sequence number, which + * was introduced relatively recently. But it would be wise to do this because + * the sequence number of a logical eraseblock characterizes how old is it. For * example, when we move a PEB with low erase counter, and we need to pick the * target PEB, we pick a PEB with the highest EC if our PEB is "old" and we * pick target PEB with an average EC if our PEB is not very "old". This is a - * room for future re-works of the WL unit. + * room for future re-works of the WL sub-system. * - * FIXME: looks too complex, should be simplified (later). + * Note: the stuff with protection trees looks too complex and is difficult to + * understand. Should be fixed. */ #include @@ -92,20 +94,21 @@ /* * Maximum difference between two erase counters. If this threshold is - * exceeded, the WL unit starts moving data from used physical eraseblocks with - * low erase counter to free physical eraseblocks with high erase counter. + * exceeded, the WL sub-system starts moving data from used physical + * eraseblocks with low erase counter to free physical eraseblocks with high + * erase counter. */ #define UBI_WL_THRESHOLD CONFIG_MTD_UBI_WL_THRESHOLD /* - * When a physical eraseblock is moved, the WL unit has to pick the target + * When a physical eraseblock is moved, the WL sub-system has to pick the target * physical eraseblock to move to. The simplest way would be just to pick the * one with the highest erase counter. But in certain workloads this could lead * to an unlimited wear of one or few physical eraseblock. Indeed, imagine a * situation when the picked physical eraseblock is constantly erased after the * data is written to it. So, we have a constant which limits the highest erase - * counter of the free physical eraseblock to pick. Namely, the WL unit does - * not pick eraseblocks with erase counter greater then the lowest erase + * counter of the free physical eraseblock to pick. Namely, the WL sub-system + * does not pick eraseblocks with erase counter greater then the lowest erase * counter plus %WL_FREE_MAX_DIFF. */ #define WL_FREE_MAX_DIFF (2*UBI_WL_THRESHOLD) @@ -123,11 +126,11 @@ * @abs_ec: the absolute erase counter value when the protection ends * @e: the wear-leveling entry of the physical eraseblock under protection * - * When the WL unit returns a physical eraseblock, the physical eraseblock is - * protected from being moved for some "time". For this reason, the physical - * eraseblock is not directly moved from the @wl->free tree to the @wl->used - * tree. There is one more tree in between where this physical eraseblock is - * temporarily stored (@wl->prot). + * When the WL sub-system returns a physical eraseblock, the physical + * eraseblock is protected from being moved for some "time". For this reason, + * the physical eraseblock is not directly moved from the @wl->free tree to the + * @wl->used tree. There is one more tree in between where this physical + * eraseblock is temporarily stored (@wl->prot). * * All this protection stuff is needed because: * o we don't want to move physical eraseblocks just after we have given them @@ -175,7 +178,6 @@ * @list: a link in the list of pending works * @func: worker function * @priv: private data of the worker function - * * @e: physical eraseblock to erase * @torture: if the physical eraseblock has to be tortured * @@ -473,52 +475,47 @@ } switch (dtype) { - case UBI_LONGTERM: - /* - * For long term data we pick a physical eraseblock - * with high erase counter. But the highest erase - * counter we can pick is bounded by the the lowest - * erase counter plus %WL_FREE_MAX_DIFF. - */ - e = find_wl_entry(&ubi->free, WL_FREE_MAX_DIFF); - protect = LT_PROTECTION; - break; - case UBI_UNKNOWN: - /* - * For unknown data we pick a physical eraseblock with - * medium erase counter. But we by no means can pick a - * physical eraseblock with erase counter greater or - * equivalent than the lowest erase counter plus - * %WL_FREE_MAX_DIFF. - */ - first = rb_entry(rb_first(&ubi->free), - struct ubi_wl_entry, rb); - last = rb_entry(rb_last(&ubi->free), - struct ubi_wl_entry, rb); + case UBI_LONGTERM: + /* + * For long term data we pick a physical eraseblock with high + * erase counter. But the highest erase counter we can pick is + * bounded by the the lowest erase counter plus + * %WL_FREE_MAX_DIFF. + */ + e = find_wl_entry(&ubi->free, WL_FREE_MAX_DIFF); + protect = LT_PROTECTION; + break; + case UBI_UNKNOWN: + /* + * For unknown data we pick a physical eraseblock with medium + * erase counter. But we by no means can pick a physical + * eraseblock with erase counter greater or equivalent than the + * lowest erase counter plus %WL_FREE_MAX_DIFF. + */ + first = rb_entry(rb_first(&ubi->free), struct ubi_wl_entry, rb); + last = rb_entry(rb_last(&ubi->free), struct ubi_wl_entry, rb); - if (last->ec - first->ec < WL_FREE_MAX_DIFF) - e = rb_entry(ubi->free.rb_node, - struct ubi_wl_entry, rb); - else { - medium_ec = (first->ec + WL_FREE_MAX_DIFF)/2; - e = find_wl_entry(&ubi->free, medium_ec); - } - protect = U_PROTECTION; - break; - case UBI_SHORTTERM: - /* - * For short term data we pick a physical eraseblock - * with the lowest erase counter as we expect it will - * be erased soon. - */ - e = rb_entry(rb_first(&ubi->free), - struct ubi_wl_entry, rb); - protect = ST_PROTECTION; - break; - default: - protect = 0; - e = NULL; - BUG(); + if (last->ec - first->ec < WL_FREE_MAX_DIFF) + e = rb_entry(ubi->free.rb_node, + struct ubi_wl_entry, rb); + else { + medium_ec = (first->ec + WL_FREE_MAX_DIFF)/2; + e = find_wl_entry(&ubi->free, medium_ec); + } + protect = U_PROTECTION; + break; + case UBI_SHORTTERM: + /* + * For short term data we pick a physical eraseblock with the + * lowest erase counter as we expect it will be erased soon. + */ + e = rb_entry(rb_first(&ubi->free), struct ubi_wl_entry, rb); + protect = ST_PROTECTION; + break; + default: + protect = 0; + e = NULL; + BUG(); } /* @@ -582,7 +579,8 @@ * This function returns zero in case of success and a negative error code in * case of failure. */ -static int sync_erase(struct ubi_device *ubi, struct ubi_wl_entry *e, int torture) +static int sync_erase(struct ubi_device *ubi, struct ubi_wl_entry *e, + int torture) { int err; struct ubi_ec_hdr *ec_hdr; @@ -634,8 +632,7 @@ } /** - * check_protection_over - check if it is time to stop protecting some - * physical eraseblocks. + * check_protection_over - check if it is time to stop protecting some PEBs. * @ubi: UBI device description object * * This function is called after each erase operation, when the absolute erase @@ -871,6 +868,10 @@ } ubi_free_vid_hdr(ubi, vid_hdr); + if (scrubbing && !protect) + ubi_msg("scrubbed PEB %d, data moved to PEB %d", + e1->pnum, e2->pnum); + spin_lock(&ubi->wl_lock); if (protect) prot_tree_add(ubi, e1, pe, protect); @@ -1054,8 +1055,8 @@ spin_unlock(&ubi->wl_lock); /* - * One more erase operation has happened, take care about protected - * physical eraseblocks. + * One more erase operation has happened, take care about + * protected physical eraseblocks. */ check_protection_over(ubi); @@ -1136,7 +1137,7 @@ } /** - * ubi_wl_put_peb - return a physical eraseblock to the wear-leveling unit. + * ubi_wl_put_peb - return a PEB to the wear-leveling sub-system. * @ubi: UBI device description object * @pnum: physical eraseblock to return * @torture: if this physical eraseblock has to be tortured @@ -1175,11 +1176,11 @@ /* * User is putting the physical eraseblock which was selected * as the target the data is moved to. It may happen if the EBA - * unit already re-mapped the LEB in 'ubi_eba_copy_leb()' but - * the WL unit has not put the PEB to the "used" tree yet, but - * it is about to do this. So we just set a flag which will - * tell the WL worker that the PEB is not needed anymore and - * should be scheduled for erasure. + * sub-system already re-mapped the LEB in 'ubi_eba_copy_leb()' + * but the WL sub-system has not put the PEB to the "used" tree + * yet, but it is about to do this. So we just set a flag which + * will tell the WL worker that the PEB is not needed anymore + * and should be scheduled for erasure. */ dbg_wl("PEB %d is the target of data moving", pnum); ubi_assert(!ubi->move_to_put); @@ -1229,7 +1230,7 @@ { struct ubi_wl_entry *e; - ubi_msg("schedule PEB %d for scrubbing", pnum); + dbg_msg("schedule PEB %d for scrubbing", pnum); retry: spin_lock(&ubi->wl_lock); @@ -1368,7 +1369,7 @@ int err; if (kthread_should_stop()) - goto out; + break; if (try_to_freeze()) continue; @@ -1395,7 +1396,8 @@ ubi_msg("%s: %d consecutive failures", ubi->bgt_name, WL_MAX_FAILURES); ubi_ro_mode(ubi); - break; + ubi->thread_enabled = 0; + continue; } } else failures = 0; @@ -1403,7 +1405,6 @@ cond_resched(); } -out: dbg_wl("background thread \"%s\" is killed", ubi->bgt_name); return 0; } @@ -1426,8 +1427,7 @@ } /** - * ubi_wl_init_scan - initialize the wear-leveling unit using scanning - * information. + * ubi_wl_init_scan - initialize the WL sub-system using scanning information. * @ubi: UBI device description object * @si: scanning information * @@ -1584,13 +1584,12 @@ } /** - * ubi_wl_close - close the wear-leveling unit. + * ubi_wl_close - close the wear-leveling sub-system. * @ubi: UBI device description object */ void ubi_wl_close(struct ubi_device *ubi) { - dbg_wl("close the UBI wear-leveling unit"); - + dbg_wl("close the WL sub-system"); cancel_pending(ubi); protection_trees_destroy(ubi); tree_destroy(&ubi->used); @@ -1602,8 +1601,7 @@ #ifdef CONFIG_MTD_UBI_DEBUG_PARANOID /** - * paranoid_check_ec - make sure that the erase counter of a physical eraseblock - * is correct. + * paranoid_check_ec - make sure that the erase counter of a PEB is correct. * @ubi: UBI device description object * @pnum: the physical eraseblock number to check * @ec: the erase counter to check @@ -1644,13 +1642,12 @@ } /** - * paranoid_check_in_wl_tree - make sure that a wear-leveling entry is present - * in a WL RB-tree. + * paranoid_check_in_wl_tree - check that wear-leveling entry is in WL RB-tree. * @e: the wear-leveling entry to check * @root: the root of the tree * - * This function returns zero if @e is in the @root RB-tree and %1 if it - * is not. + * This function returns zero if @e is in the @root RB-tree and %1 if it is + * not. */ static int paranoid_check_in_wl_tree(struct ubi_wl_entry *e, struct rb_root *root) diff -urN linux-2.6.26/drivers/mxc/Kconfig linux-2.6.26-lab126/drivers/mxc/Kconfig --- linux-2.6.26/drivers/mxc/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/Kconfig 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,39 @@ +# drivers/video/mxc/Kconfig + +if ARCH_MXC + +menu "MXC support drivers" + +config MXC_IPU + bool "Image Processing Unit Driver" + depends on !ARCH_MX21 + depends on !ARCH_MX27 + depends on !ARCH_MX25 + select MXC_IPU_V1 if !ARCH_MX37 && !ARCH_MX51 + select MXC_IPU_V3 if ARCH_MX37 || ARCH_MX51 + select MXC_IPU_V3D if ARCH_MX37 + help + If you plan to use the Image Processing unit, say + Y here. IPU is needed by Framebuffer and V4L2 drivers. + +source "drivers/mxc/ipu/Kconfig" +source "drivers/mxc/ipu3/Kconfig" + +source "drivers/mxc/ssi/Kconfig" +source "drivers/mxc/dam/Kconfig" +source "drivers/mxc/pmic/Kconfig" +source "drivers/mxc/mcu_pmic/Kconfig" +source "drivers/mxc/pm/Kconfig" +source "drivers/mxc/security/Kconfig" +source "drivers/mxc/hmp4e/Kconfig" +source "drivers/mxc/hw_event/Kconfig" +source "drivers/mxc/vpu/Kconfig" +source "drivers/mxc/asrc/Kconfig" +source "drivers/mxc/bt/Kconfig" +source "drivers/mxc/gps_ioctrl/Kconfig" +source "drivers/mxc/mlb/Kconfig" +source "drivers/mxc/adc/Kconfig" + +endmenu + +endif diff -urN linux-2.6.26/drivers/mxc/Makefile linux-2.6.26-lab126/drivers/mxc/Makefile --- linux-2.6.26/drivers/mxc/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/Makefile 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,19 @@ +obj-$(CONFIG_MXC_IPU_V1) += ipu/ +obj-$(CONFIG_MXC_IPU_V3) += ipu3/ +obj-$(CONFIG_MXC_SSI) += ssi/ +obj-$(CONFIG_MXC_DAM) += dam/ + +obj-$(CONFIG_MXC_PMIC_MC9SDZ60) += mcu_pmic/ +obj-$(CONFIG_MXC_PMIC) += pmic/ + +obj-$(CONFIG_MXC_DPTC) += pm/ +obj-$(CONFIG_MX27_DPTC) += pm/ +obj-$(CONFIG_MXC_HMP4E) += hmp4e/ +obj-y += security/ +obj-$(CONFIG_MXC_VPU) += vpu/ +obj-$(CONFIG_MXC_HWEVENT) += hw_event/ +obj-$(CONFIG_MXC_ASRC) += asrc/ +obj-$(CONFIG_MXC_BLUETOOTH) += bt/ +obj-$(CONFIG_GPS_IOCTRL) += gps_ioctrl/ +obj-$(CONFIG_MXC_MLB) += mlb/ +obj-$(CONFIG_IMX_ADC) += adc/ diff -urN linux-2.6.26/drivers/mxc/adc/Kconfig linux-2.6.26-lab126/drivers/mxc/adc/Kconfig --- linux-2.6.26/drivers/mxc/adc/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/adc/Kconfig 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,14 @@ +# +# i.MX ADC devices +# + +menu "i.MX ADC support" + +config IMX_ADC + tristate "i.MX ADC" + depends on ARCH_MXC + default n + help + This selects the Freescale i.MX on-chip ADC driver. + +endmenu diff -urN linux-2.6.26/drivers/mxc/adc/Makefile linux-2.6.26-lab126/drivers/mxc/adc/Makefile --- linux-2.6.26/drivers/mxc/adc/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/adc/Makefile 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,4 @@ +# +# Makefile for i.MX adc devices. +# +obj-$(CONFIG_IMX_ADC) += imx_adc.o diff -urN linux-2.6.26/drivers/mxc/adc/imx_adc.c linux-2.6.26-lab126/drivers/mxc/adc/imx_adc.c --- linux-2.6.26/drivers/mxc/adc/imx_adc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/adc/imx_adc.c 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,1036 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file adc/imx_adc.c + * @brief This is the main file of i.MX ADC driver. + * + * @ingroup IMX_ADC + */ + +/* + * Includes + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "imx_adc_reg.h" + +static int imx_adc_major; + +/*! + * Number of users waiting in suspendq + */ +static int swait; + +/*! + * To indicate whether any of the adc devices are suspending + */ +static int suspend_flag; + +/*! + * The suspendq is used by blocking application calls + */ +static wait_queue_head_t suspendq; +static wait_queue_head_t tsq; + +static bool imx_adc_ready; +static bool ts_data_ready; +static int tsi_data = TSI_DATA; +static unsigned short ts_data_buf[16]; + +static struct class *imx_adc_class; +static struct imx_adc_data *adc_data; + +static DECLARE_MUTEX(general_convert_mutex); +static DECLARE_MUTEX(ts_convert_mutex); + +unsigned long tsc_base; + +int is_imx_adc_ready(void) +{ + return imx_adc_ready; +} +EXPORT_SYMBOL(is_imx_adc_ready); + +void tsc_clk_enable(void) +{ + unsigned long reg; + + clk_enable(adc_data->adc_clk); + + reg = __raw_readl(tsc_base + TGCR); + reg |= TGCR_IPG_CLK_EN; + __raw_writel(reg, tsc_base + TGCR); +} + +void tsc_clk_disable(void) +{ + unsigned long reg; + + clk_disable(adc_data->adc_clk); + + reg = __raw_readl(tsc_base + TGCR); + reg &= ~TGCR_IPG_CLK_EN; + __raw_writel(reg, tsc_base + TGCR); +} + +void tsc_self_reset(void) +{ + unsigned long reg; + + reg = __raw_readl(tsc_base + TGCR); + reg |= TGCR_TSC_RST; + __raw_writel(reg, tsc_base + TGCR); + + while (__raw_readl(tsc_base + TGCR) & TGCR_TSC_RST) + continue; +} + +/* Internal reference */ +void tsc_intref_enable(void) +{ + unsigned long reg; + + reg = __raw_readl(tsc_base + TGCR); + reg |= TGCR_INTREFEN; + __raw_writel(reg, tsc_base + TGCR); +} + +/* initialize touchscreen */ +void imx_tsc_init(void) +{ + unsigned long reg; + int lastitemid; + int dbtime; + + /* Level sense */ + reg = __raw_readl(tsc_base + TCQCR); + reg |= CQCR_PD_CFG; + reg |= (0xf << CQCR_FIFOWATERMARK_SHIFT); /* watermark */ + __raw_writel(reg, tsc_base + TCQCR); + + /* Configure 4-wire */ + reg = TSC_4WIRE_PRECHARGE; + reg |= CC_IGS; + __raw_writel(reg, tsc_base + TCC0); + + reg = TSC_4WIRE_TOUCH_DETECT; + reg |= 3 << CC_NOS_SHIFT; /* 4 samples */ + reg |= 32 << CC_SETTLING_TIME_SHIFT; /* it's important! */ + __raw_writel(reg, tsc_base + TCC1); + + reg = TSC_4WIRE_X_MEASUMENT; + reg |= 3 << CC_NOS_SHIFT; /* 4 samples */ + reg |= 16 << CC_SETTLING_TIME_SHIFT; /* settling time */ + __raw_writel(reg, tsc_base + TCC2); + + reg = TSC_4WIRE_Y_MEASUMENT; + reg |= 3 << CC_NOS_SHIFT; /* 4 samples */ + reg |= 16 << CC_SETTLING_TIME_SHIFT; /* settling time */ + __raw_writel(reg, tsc_base + TCC3); + + reg = (TCQ_ITEM_TCC0 << TCQ_ITEM7_SHIFT) | + (TCQ_ITEM_TCC0 << TCQ_ITEM6_SHIFT) | + (TCQ_ITEM_TCC1 << TCQ_ITEM5_SHIFT) | + (TCQ_ITEM_TCC0 << TCQ_ITEM4_SHIFT) | + (TCQ_ITEM_TCC3 << TCQ_ITEM3_SHIFT) | + (TCQ_ITEM_TCC2 << TCQ_ITEM2_SHIFT) | + (TCQ_ITEM_TCC1 << TCQ_ITEM1_SHIFT) | + (TCQ_ITEM_TCC0 << TCQ_ITEM0_SHIFT); + __raw_writel(reg, tsc_base + TCQ_ITEM_7_0); + + lastitemid = 5; + reg = __raw_readl(tsc_base + TCQCR); + reg = (reg & ~CQCR_LAST_ITEM_ID_MASK) | + (lastitemid << CQCR_LAST_ITEM_ID_SHIFT); + __raw_writel(reg, tsc_base + TCQCR); + + /* pen down enable */ + reg = __raw_readl(tsc_base + TCQCR); + reg &= ~CQCR_PD_MSK; + __raw_writel(reg, tsc_base + TCQCR); + reg = __raw_readl(tsc_base + TCQMR); + reg &= ~TCQMR_PD_IRQ_MSK; + __raw_writel(reg, tsc_base + TCQMR); + + /* Debounce time = dbtime*8 adc clock cycles */ + reg = __raw_readl(tsc_base + TGCR); + dbtime = 3; + reg &= ~TGCR_PDBTIME_MASK; + reg |= dbtime << TGCR_PDBTIME_SHIFT; + reg |= TGCR_HSYNC_EN; + __raw_writel(reg, tsc_base + TGCR); + +} + +static irqreturn_t imx_adc_interrupt(int irq, void *dev_id) +{ + int reg; + + /* disable pen down detect */ + reg = __raw_readl(tsc_base + TGCR); + reg &= ~TGCR_PD_EN; + __raw_writel(reg, tsc_base + TGCR); + + ts_data_ready = 1; + wake_up_interruptible(&tsq); + return IRQ_HANDLED; +} + +enum IMX_ADC_STATUS imx_adc_read_general(unsigned short *result) +{ + unsigned long reg; + unsigned int data_num = 0; + + reg = __raw_readl(tsc_base + GCQCR); + reg |= CQCR_FQS; + __raw_writel(reg, tsc_base + GCQCR); + + while (!(__raw_readl(tsc_base + GCQSR) & CQSR_EOQ)) + continue; + reg = __raw_readl(tsc_base + GCQCR); + reg &= ~CQCR_FQS; + __raw_writel(reg, tsc_base + GCQCR); + reg = __raw_readl(tsc_base + GCQSR); + reg |= CQSR_EOQ; + __raw_writel(reg, tsc_base + GCQSR); + + while (!(__raw_readl(tsc_base + GCQSR) & CQSR_EMPT)) { + result[data_num] = __raw_readl(tsc_base + GCQFIFO) >> + GCQFIFO_ADCOUT_SHIFT; + data_num++; + } + return IMX_ADC_SUCCESS; +} + +/*! + * This function will get raw (X,Y) value by converting the voltage + * @param touch_sample Pointer to touch sample + * + * return This funciton returns 0 if successful. + * + * + */ +enum IMX_ADC_STATUS imx_adc_read_ts(struct t_touch_screen *touch_sample, + int wait_tsi) +{ + int reg; + int data_num = 0; + int detect_sample1, detect_sample2; + + memset(ts_data_buf, 0, sizeof ts_data_buf); + touch_sample->valid_flag = 1; + + if (wait_tsi) { + /* Config idle for 4-wire */ + reg = TSC_4WIRE_TOUCH_DETECT; + __raw_writel(reg, tsc_base + TICR); + + /* Pen interrupt starts new conversion queue */ + reg = __raw_readl(tsc_base + TCQCR); + reg &= ~CQCR_QSM_MASK; + reg |= CQCR_QSM_PEN; + __raw_writel(reg, tsc_base + TCQCR); + + /* PDEN and PDBEN */ + reg = __raw_readl(tsc_base + TGCR); + reg |= (TGCR_PDB_EN | TGCR_PD_EN); + __raw_writel(reg, tsc_base + TGCR); + + wait_event_interruptible(tsq, ts_data_ready); + while (!(__raw_readl(tsc_base + TCQSR) & CQSR_EOQ)) + continue; + /* stop the conversion */ + reg = __raw_readl(tsc_base + TCQCR); + reg &= ~CQCR_QSM_MASK; + __raw_writel(reg, tsc_base + TCQCR); + reg = CQSR_PD | CQSR_EOQ; + __raw_writel(reg, tsc_base + TCQSR); + + /* change configuration for FQS mode */ + tsi_data = TSI_DATA; + reg = (0x1 << CC_YPLLSW_SHIFT) | (0x1 << CC_XNURSW_SHIFT) | + CC_XPULSW; + __raw_writel(reg, tsc_base + TICR); + } else { + /* FQS semaphore */ + down(&ts_convert_mutex); + + reg = (0x1 << CC_YPLLSW_SHIFT) | (0x1 << CC_XNURSW_SHIFT) | + CC_XPULSW; + __raw_writel(reg, tsc_base + TICR); + + /* FQS */ + reg = __raw_readl(tsc_base + TCQCR); + reg &= ~CQCR_QSM_MASK; + reg |= CQCR_QSM_FQS; + __raw_writel(reg, tsc_base + TCQCR); + reg = __raw_readl(tsc_base + TCQCR); + reg |= CQCR_FQS; + __raw_writel(reg, tsc_base + TCQCR); + while (!(__raw_readl(tsc_base + TCQSR) & CQSR_EOQ)) + continue; + + /* stop FQS */ + reg = __raw_readl(tsc_base + TCQCR); + reg &= ~CQCR_QSM_MASK; + __raw_writel(reg, tsc_base + TCQCR); + reg = __raw_readl(tsc_base + TCQCR); + reg &= ~CQCR_FQS; + __raw_writel(reg, tsc_base + TCQCR); + + /* clear status bit */ + reg = __raw_readl(tsc_base + TCQSR); + reg |= CQSR_EOQ; + __raw_writel(reg, tsc_base + TCQSR); + tsi_data = FQS_DATA; + } + + while (!(__raw_readl(tsc_base + TCQSR) & CQSR_EMPT)) { + reg = __raw_readl(tsc_base + TCQFIFO); + ts_data_buf[data_num] = reg; + data_num++; + } + + touch_sample->x_position1 = ts_data_buf[4] >> 4; + touch_sample->x_position2 = ts_data_buf[5] >> 4; + touch_sample->x_position3 = ts_data_buf[6] >> 4; + touch_sample->y_position1 = ts_data_buf[9] >> 4; + touch_sample->y_position2 = ts_data_buf[10] >> 4; + touch_sample->y_position3 = ts_data_buf[11] >> 4; + + detect_sample1 = ts_data_buf[0]; + detect_sample2 = ts_data_buf[12]; + + if ((detect_sample1 > 0x6000) || (detect_sample2 > 0x6000)) + touch_sample->valid_flag = 0; + + ts_data_ready = 0; + + if (!(touch_sample->x_position1 || + touch_sample->x_position2 || touch_sample->x_position3)) + touch_sample->contact_resistance = 0; + else + touch_sample->contact_resistance = 1; + + if (tsi_data == FQS_DATA) + up(&ts_convert_mutex); + return IMX_ADC_SUCCESS; +} + +/*! + * This function performs filtering and rejection of excessive noise prone + * sampl. + * + * @param ts_curr Touch screen value + * + * @return This function returns 0 on success, -1 otherwise. + */ +static int imx_adc_filter(struct t_touch_screen *ts_curr) +{ + + unsigned int ydiff1, ydiff2, ydiff3, xdiff1, xdiff2, xdiff3; + unsigned int sample_sumx, sample_sumy; + static unsigned int prev_x[FILTLEN], prev_y[FILTLEN]; + int index = 0; + unsigned int y_curr, x_curr; + static int filt_count; + /* Added a variable filt_type to decide filtering at run-time */ + unsigned int filt_type = 0; + + /* ignore the data converted when pen down and up */ + if ((ts_curr->contact_resistance == 0) || tsi_data == TSI_DATA) { + ts_curr->x_position = 0; + ts_curr->y_position = 0; + filt_count = 0; + return 0; + } + /* ignore the data valid */ + if (ts_curr->valid_flag == 0) + return -1; + + ydiff1 = abs(ts_curr->y_position1 - ts_curr->y_position2); + ydiff2 = abs(ts_curr->y_position2 - ts_curr->y_position3); + ydiff3 = abs(ts_curr->y_position1 - ts_curr->y_position3); + if ((ydiff1 > DELTA_Y_MAX) || + (ydiff2 > DELTA_Y_MAX) || (ydiff3 > DELTA_Y_MAX)) { + pr_debug("imx_adc_filter: Ret pos 1\n"); + return -1; + } + + xdiff1 = abs(ts_curr->x_position1 - ts_curr->x_position2); + xdiff2 = abs(ts_curr->x_position2 - ts_curr->x_position3); + xdiff3 = abs(ts_curr->x_position1 - ts_curr->x_position3); + + if ((xdiff1 > DELTA_X_MAX) || + (xdiff2 > DELTA_X_MAX) || (xdiff3 > DELTA_X_MAX)) { + pr_debug("imx_adc_filter: Ret pos 2\n"); + return -1; + } + /* Compute two closer values among the three available Y readouts */ + + if (ydiff1 < ydiff2) { + if (ydiff1 < ydiff3) { + /* Sample 0 & 1 closest together */ + sample_sumy = ts_curr->y_position1 + + ts_curr->y_position2; + } else { + /* Sample 0 & 2 closest together */ + sample_sumy = ts_curr->y_position1 + + ts_curr->y_position3; + } + } else { + if (ydiff2 < ydiff3) { + /* Sample 1 & 2 closest together */ + sample_sumy = ts_curr->y_position2 + + ts_curr->y_position3; + } else { + /* Sample 0 & 2 closest together */ + sample_sumy = ts_curr->y_position1 + + ts_curr->y_position3; + } + } + + /* + * Compute two closer values among the three available X + * readouts + */ + if (xdiff1 < xdiff2) { + if (xdiff1 < xdiff3) { + /* Sample 0 & 1 closest together */ + sample_sumx = ts_curr->x_position1 + + ts_curr->x_position2; + } else { + /* Sample 0 & 2 closest together */ + sample_sumx = ts_curr->x_position1 + + ts_curr->x_position3; + } + } else { + if (xdiff2 < xdiff3) { + /* Sample 1 & 2 closest together */ + sample_sumx = ts_curr->x_position2 + + ts_curr->x_position3; + } else { + /* Sample 0 & 2 closest together */ + sample_sumx = ts_curr->x_position1 + + ts_curr->x_position3; + } + } + + /* + * Wait FILTER_MIN_DELAY number of samples to restart + * filtering + */ + if (filt_count < FILTER_MIN_DELAY) { + /* + * Current output is the average of the two closer + * values and no filtering is used + */ + y_curr = (sample_sumy / 2); + x_curr = (sample_sumx / 2); + ts_curr->y_position = y_curr; + ts_curr->x_position = x_curr; + filt_count++; + + } else { + if (abs(sample_sumx - (prev_x[0] + prev_x[1])) > + (DELTA_X_MAX * 16)) { + pr_debug("imx_adc_filter: : Ret pos 3\n"); + return -1; + } + if (abs(sample_sumy - (prev_y[0] + prev_y[1])) > + (DELTA_Y_MAX * 16)) { + pr_debug("imx_adc_filter: : Ret pos 4\n"); + return -1; + } + sample_sumy /= 2; + sample_sumx /= 2; + /* Use hard filtering if the sample difference < 10 */ + if ((abs(sample_sumy - prev_y[0]) > 10) || + (abs(sample_sumx - prev_x[0]) > 10)) + filt_type = 1; + + /* + * Current outputs are the average of three previous + * values and the present readout + */ + y_curr = sample_sumy; + for (index = 0; index < FILTLEN; index++) { + if (filt_type == 0) + y_curr = y_curr + (prev_y[index]); + else + y_curr = y_curr + (prev_y[index] / 3); + } + if (filt_type == 0) + y_curr = y_curr >> 2; + else + y_curr = y_curr >> 1; + ts_curr->y_position = y_curr; + + x_curr = sample_sumx; + for (index = 0; index < FILTLEN; index++) { + if (filt_type == 0) + x_curr = x_curr + (prev_x[index]); + else + x_curr = x_curr + (prev_x[index] / 3); + } + if (filt_type == 0) + x_curr = x_curr >> 2; + else + x_curr = x_curr >> 1; + ts_curr->x_position = x_curr; + + } + + /* Update previous X and Y values */ + for (index = (FILTLEN - 1); index > 0; index--) { + prev_x[index] = prev_x[index - 1]; + prev_y[index] = prev_y[index - 1]; + } + + /* + * Current output will be the most recent past for the + * next sample + */ + prev_y[0] = y_curr; + prev_x[0] = x_curr; + + return 0; + +} + +/*! + * This function retrieves the current touch screen (X,Y) coordinates. + * + * @param touch_sample Pointer to touch sample. + * + * @return This function returns IMX_ADC_SUCCESS if successful. + */ +enum IMX_ADC_STATUS imx_adc_get_touch_sample(struct t_touch_screen + *touch_sample, int wait_tsi) +{ + if (imx_adc_read_ts(touch_sample, wait_tsi)) + return IMX_ADC_ERROR; + if (!imx_adc_filter(touch_sample)) + return IMX_ADC_SUCCESS; + else + return IMX_ADC_ERROR; +} +EXPORT_SYMBOL(imx_adc_get_touch_sample); + +/*! + * This is the suspend of power management for the i.MX ADC API. + * It supports SAVE and POWER_DOWN state. + * + * @param pdev the device + * @param state the state + * + * @return This function returns 0 if successful. + */ +static int imx_adc_suspend(struct platform_device *pdev, pm_message_t state) +{ + suspend_flag = 1; + tsc_clk_disable(); + return 0; +}; + +/*! + * This is the resume of power management for the i.MX adc API. + * It supports RESTORE state. + * + * @param pdev the device + * + * @return This function returns 0 if successful. + */ +static int imx_adc_resume(struct platform_device *pdev) +{ + suspend_flag = 0; + + tsc_clk_enable(); + + while (swait > 0) { + swait--; + wake_up_interruptible(&suspendq); + } + + return 0; +} + +/*! + * This function implements the open method on an i.MX ADC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int imx_adc_open(struct inode *inode, struct file *file) +{ + while (suspend_flag) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, !suspend_flag)) + return -ERESTARTSYS; + } + pr_debug("imx_adc : imx_adc_open()\n"); + return 0; +} + +/*! + * This function implements the release method on an i.MX ADC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int imx_adc_free(struct inode *inode, struct file *file) +{ + pr_debug("imx_adc : imx_adc_free()\n"); + return 0; +} + +/*! + * This function initializes all ADC registers with default values. This + * function also registers the interrupt events. + * + * @return This function returns IMX_ADC_SUCCESS if successful. + */ +int imx_adc_init(void) +{ + int reg; + + pr_debug("imx_adc_init()\n"); + + if (suspend_flag) + return -EBUSY; + + tsc_clk_enable(); + + /* Reset */ + tsc_self_reset(); + + /* Internal reference */ + tsc_intref_enable(); + + /* Set power mode */ + reg = __raw_readl(tsc_base + TGCR) & ~TGCR_POWER_MASK; + reg |= TGCR_POWER_SAVE; + __raw_writel(reg, tsc_base + TGCR); + + imx_tsc_init(); + + return IMX_ADC_SUCCESS; +} +EXPORT_SYMBOL(imx_adc_init); + +/*! + * This function disables the ADC, de-registers the interrupt events. + * + * @return This function returns IMX_ADC_SUCCESS if successful. + */ +enum IMX_ADC_STATUS imx_adc_deinit(void) +{ + pr_debug("imx_adc_deinit()\n"); + + return IMX_ADC_SUCCESS; +} +EXPORT_SYMBOL(imx_adc_deinit); + +/*! + * This function triggers a conversion and returns one sampling result of one + * channel. + * + * @param channel The channel to be sampled + * @param result The pointer to the conversion result. The memory + * should be allocated by the caller of this function. + * + * @return This function returns IMX_ADC_SUCCESS if successful. + */ +enum IMX_ADC_STATUS imx_adc_convert(enum t_channel channel, + unsigned short *result) +{ + int reg; + int lastitemid; + struct t_touch_screen touch_sample; + + switch (channel) { + + case TS_X_POS: + imx_adc_get_touch_sample(&touch_sample, 0); + result[0] = touch_sample.x_position; + + /* if no pen down ,recover the register configuration */ + if (touch_sample.contact_resistance == 0) { + reg = __raw_readl(tsc_base + TCQCR); + reg &= ~CQCR_QSM_MASK; + reg |= CQCR_QSM_PEN; + __raw_writel(reg, tsc_base + TCQCR); + reg = __raw_readl(tsc_base + TGCR); + reg |= TGCR_PDB_EN | TGCR_PD_EN; + __raw_writel(reg, tsc_base + TGCR); + } + break; + + case TS_Y_POS: + imx_adc_get_touch_sample(&touch_sample, 0); + result[1] = touch_sample.y_position; + + /* if no pen down ,recover the register configuration */ + if (touch_sample.contact_resistance == 0) { + reg = __raw_readl(tsc_base + TCQCR); + reg &= ~CQCR_QSM_MASK; + reg |= CQCR_QSM_PEN; + __raw_writel(reg, tsc_base + TCQCR); + + reg = __raw_readl(tsc_base + TGCR); + reg |= TGCR_PDB_EN | TGCR_PD_EN; + __raw_writel(reg, tsc_base + TGCR); + } + break; + + case GER_PURPOSE_ADC0: + down(&general_convert_mutex); + + lastitemid = 0; + reg = (0xf << CQCR_FIFOWATERMARK_SHIFT) | + (lastitemid << CQCR_LAST_ITEM_ID_SHIFT) | CQCR_QSM_FQS; + __raw_writel(reg, tsc_base + GCQCR); + + reg = TSC_GENERAL_ADC_GCC0; + reg |= (3 << CC_NOS_SHIFT) | (16 << CC_SETTLING_TIME_SHIFT); + __raw_writel(reg, tsc_base + GCC0); + + imx_adc_read_general(result); + up(&general_convert_mutex); + break; + + case GER_PURPOSE_ADC1: + down(&general_convert_mutex); + + lastitemid = 0; + reg = (0xf << CQCR_FIFOWATERMARK_SHIFT) | + (lastitemid << CQCR_LAST_ITEM_ID_SHIFT) | CQCR_QSM_FQS; + __raw_writel(reg, tsc_base + GCQCR); + + reg = TSC_GENERAL_ADC_GCC1; + reg |= (3 << CC_NOS_SHIFT) | (16 << CC_SETTLING_TIME_SHIFT); + __raw_writel(reg, tsc_base + GCC0); + + imx_adc_read_general(result); + up(&general_convert_mutex); + break; + + case GER_PURPOSE_ADC2: + down(&general_convert_mutex); + + lastitemid = 0; + reg = (0xf << CQCR_FIFOWATERMARK_SHIFT) | + (lastitemid << CQCR_LAST_ITEM_ID_SHIFT) | CQCR_QSM_FQS; + __raw_writel(reg, tsc_base + GCQCR); + + reg = TSC_GENERAL_ADC_GCC2; + reg |= (3 << CC_NOS_SHIFT) | (16 << CC_SETTLING_TIME_SHIFT); + __raw_writel(reg, tsc_base + GCC0); + + imx_adc_read_general(result); + up(&general_convert_mutex); + break; + + case GER_PURPOSE_MULTICHNNEL: + down(&general_convert_mutex); + + reg = TSC_GENERAL_ADC_GCC0; + reg |= (3 << CC_NOS_SHIFT) | (16 << CC_SETTLING_TIME_SHIFT); + __raw_writel(reg, tsc_base + GCC0); + + reg = TSC_GENERAL_ADC_GCC1; + reg |= (3 << CC_NOS_SHIFT) | (16 << CC_SETTLING_TIME_SHIFT); + __raw_writel(reg, tsc_base + GCC1); + + reg = TSC_GENERAL_ADC_GCC2; + reg |= (3 << CC_NOS_SHIFT) | (16 << CC_SETTLING_TIME_SHIFT); + __raw_writel(reg, tsc_base + GCC2); + + reg = (GCQ_ITEM_GCC2 << GCQ_ITEM2_SHIFT) | + (GCQ_ITEM_GCC1 << GCQ_ITEM1_SHIFT) | + (GCQ_ITEM_GCC0 << GCQ_ITEM0_SHIFT); + __raw_writel(reg, tsc_base + GCQ_ITEM_7_0); + + lastitemid = 2; + reg = (0xf << CQCR_FIFOWATERMARK_SHIFT) | + (lastitemid << CQCR_LAST_ITEM_ID_SHIFT) | CQCR_QSM_FQS; + __raw_writel(reg, tsc_base + GCQCR); + + imx_adc_read_general(result); + up(&general_convert_mutex); + break; + default: + pr_debug("%s: bad channel number\n", __func__); + return IMX_ADC_ERROR; + } + + return IMX_ADC_SUCCESS; +} +EXPORT_SYMBOL(imx_adc_convert); + +/*! + * This function triggers a conversion and returns sampling results of each + * specified channel. + * + * @param channels This input parameter is bitmap to specify channels + * to be sampled. + * @param result The pointer to array to store sampling results. + * The memory should be allocated by the caller of this + * function. + * + * @return This function returns IMX_ADC_SUCCESS if successful. + */ +enum IMX_ADC_STATUS imx_adc_convert_multichnnel(enum t_channel channels, + unsigned short *result) +{ + imx_adc_convert(GER_PURPOSE_MULTICHNNEL, result); + return IMX_ADC_SUCCESS; +} +EXPORT_SYMBOL(imx_adc_convert_multichnnel); + +/*! + * This function implements IOCTL controls on an i.MX ADC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @param cmd the command + * @param arg the parameter + * @return This function returns 0 if successful. + */ +static int imx_adc_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + struct t_adc_convert_param *convert_param; + + if ((_IOC_TYPE(cmd) != 'p') && (_IOC_TYPE(cmd) != 'D')) + return -ENOTTY; + + while (suspend_flag) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, !suspend_flag)) + return -ERESTARTSYS; + } + + switch (cmd) { + case IMX_ADC_INIT: + pr_debug("init adc\n"); + CHECK_ERROR(imx_adc_init()); + break; + + case IMX_ADC_DEINIT: + pr_debug("deinit adc\n"); + CHECK_ERROR(imx_adc_deinit()); + break; + + case IMX_ADC_CONVERT: + convert_param = kmalloc(sizeof(*convert_param), GFP_KERNEL); + if (convert_param == NULL) + return -ENOMEM; + if (copy_from_user(convert_param, + (struct t_adc_convert_param *)arg, + sizeof(*convert_param))) { + kfree(convert_param); + return -EFAULT; + } + CHECK_ERROR_KFREE(imx_adc_convert(convert_param->channel, + convert_param->result), + (kfree(convert_param))); + + if (copy_to_user((struct t_adc_convert_param *)arg, + convert_param, sizeof(*convert_param))) { + kfree(convert_param); + return -EFAULT; + } + kfree(convert_param); + break; + + case IMX_ADC_CONVERT_MULTICHANNEL: + convert_param = kmalloc(sizeof(*convert_param), GFP_KERNEL); + if (convert_param == NULL) + return -ENOMEM; + if (copy_from_user(convert_param, + (struct t_adc_convert_param *)arg, + sizeof(*convert_param))) { + kfree(convert_param); + return -EFAULT; + } + CHECK_ERROR_KFREE(imx_adc_convert_multichnnel + (convert_param->channel, + convert_param->result), + (kfree(convert_param))); + + if (copy_to_user((struct t_adc_convert_param *)arg, + convert_param, sizeof(*convert_param))) { + kfree(convert_param); + return -EFAULT; + } + kfree(convert_param); + break; + + default: + pr_debug("imx_adc_ioctl: unsupported ioctl command 0x%x\n", + cmd); + return -EINVAL; + } + return 0; +} + +static struct file_operations imx_adc_fops = { + .owner = THIS_MODULE, + .ioctl = imx_adc_ioctl, + .open = imx_adc_open, + .release = imx_adc_free, +}; + +static int imx_adc_module_probe(struct platform_device *pdev) +{ + int ret = 0; + int retval; + struct device *temp_class; + struct resource *res; + void __iomem *base; + + /* ioremap the base address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "No TSC base address provided\n"); + goto err_out0; + } + base = ioremap(res->start, res->end - res->start); + if (base == NULL) { + dev_err(&pdev->dev, "failed to rebase TSC base address\n"); + goto err_out0; + } + tsc_base = (unsigned long)base; + + /* create the chrdev */ + imx_adc_major = register_chrdev(0, "imx_adc", &imx_adc_fops); + + if (imx_adc_major < 0) { + dev_err(&pdev->dev, "Unable to get a major for imx_adc\n"); + return imx_adc_major; + } + init_waitqueue_head(&suspendq); + init_waitqueue_head(&tsq); + + imx_adc_class = class_create(THIS_MODULE, "imx_adc"); + if (IS_ERR(imx_adc_class)) { + dev_err(&pdev->dev, "Error creating imx_adc class.\n"); + ret = PTR_ERR(imx_adc_class); + goto err_out1; + } + + temp_class = device_create(imx_adc_class, NULL, + MKDEV(imx_adc_major, 0), "imx_adc"); + if (IS_ERR(temp_class)) { + dev_err(&pdev->dev, "Error creating imx_adc class device.\n"); + ret = PTR_ERR(temp_class); + goto err_out2; + } + + adc_data = kmalloc(sizeof(struct imx_adc_data), GFP_KERNEL); + if (adc_data == NULL) + return -ENOMEM; + adc_data->irq = platform_get_irq(pdev, 0); + retval = request_irq(adc_data->irq, imx_adc_interrupt, + 0, MOD_NAME, MOD_NAME); + if (retval) { + dev_dbg(&pdev->dev, "ADC: request_irq(%d) returned error %d\n", + MXC_INT_TSC, retval); + return retval; + } + adc_data->adc_clk = clk_get(&pdev->dev, "tchscrn_clk"); + + ret = imx_adc_init(); + + if (ret != IMX_ADC_SUCCESS) { + dev_err(&pdev->dev, "Error in imx_adc_init.\n"); + goto err_out4; + } + imx_adc_ready = 1; + pr_info("i.MX ADC at 0x%x irq %d\n", (unsigned int)res->start, + adc_data->irq); + return ret; + +err_out4: + device_destroy(imx_adc_class, MKDEV(imx_adc_major, 0)); +err_out2: + class_destroy(imx_adc_class); +err_out1: + unregister_chrdev(imx_adc_major, "imx_adc"); +err_out0: + return ret; +} + +static int imx_adc_module_remove(struct platform_device *pdev) +{ + imx_adc_ready = 0; + imx_adc_deinit(); + device_destroy(imx_adc_class, MKDEV(imx_adc_major, 0)); + class_destroy(imx_adc_class); + unregister_chrdev(imx_adc_major, "imx_adc"); + free_irq(adc_data->irq, MOD_NAME); + kfree(adc_data); + pr_debug("i.MX ADC successfully removed\n"); + return 0; +} + +static struct platform_driver imx_adc_driver = { + .driver = { + .name = "imx_adc", + }, + .suspend = imx_adc_suspend, + .resume = imx_adc_resume, + .probe = imx_adc_module_probe, + .remove = imx_adc_module_remove, +}; + +/* + * Initialization and Exit + */ +static int __init imx_adc_module_init(void) +{ + pr_debug("i.MX ADC driver loading...\n"); + return platform_driver_register(&imx_adc_driver); +} + +static void __exit imx_adc_module_exit(void) +{ + platform_driver_unregister(&imx_adc_driver); + pr_debug("i.MX ADC driver successfully unloaded\n"); +} + +/* + * Module entry points + */ + +module_init(imx_adc_module_init); +module_exit(imx_adc_module_exit); + +MODULE_DESCRIPTION("i.MX ADC device driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/adc/imx_adc_reg.h linux-2.6.26-lab126/drivers/mxc/adc/imx_adc_reg.h --- linux-2.6.26/drivers/mxc/adc/imx_adc_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/adc/imx_adc_reg.h 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,242 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +#ifndef __IMX_ADC_H__ +#define __IMX_ADC_H__ + +/* TSC General Config Register */ +#define TGCR 0x000 +#define TGCR_IPG_CLK_EN (1 << 0) +#define TGCR_TSC_RST (1 << 1) +#define TGCR_FUNC_RST (1 << 2) +#define TGCR_SLPC (1 << 4) +#define TGCR_STLC (1 << 5) +#define TGCR_HSYNC_EN (1 << 6) +#define TGCR_HSYNC_POL (1 << 7) +#define TGCR_POWERMODE_SHIFT 8 +#define TGCR_POWER_OFF (0x0 << TGCR_POWERMODE_SHIFT) +#define TGCR_POWER_SAVE (0x1 << TGCR_POWERMODE_SHIFT) +#define TGCR_POWER_ON (0x3 << TGCR_POWERMODE_SHIFT) +#define TGCR_POWER_MASK (0x3 << TGCR_POWERMODE_SHIFT) +#define TGCR_INTREFEN (1 << 10) +#define TGCR_ADCCLKCFG_SHIFT 16 +#define TGCR_PD_EN (1 << 23) +#define TGCR_PDB_EN (1 << 24) +#define TGCR_PDBTIME_SHIFT 25 +#define TGCR_PDBTIME128 (0x3f << TGCR_PDBTIME_SHIFT) +#define TGCR_PDBTIME_MASK (0x7f << TGCR_PDBTIME_SHIFT) + +/* TSC General Status Register */ +#define TGSR 0x004 +#define TCQ_INT (1 << 0) +#define GCQ_INT (1 << 1) +#define SLP_INT (1 << 2) +#define TCQ_DMA (1 << 16) +#define GCQ_DMA (1 << 17) + +/* TSC IDLE Config Register */ +#define TICR 0x008 + +/* TouchScreen Convert Queue FIFO Register */ +#define TCQFIFO 0x400 +/* TouchScreen Convert Queue Control Register */ +#define TCQCR 0x404 +#define CQCR_QSM_SHIFT 0 +#define CQCR_QSM_STOP (0x0 << CQCR_QSM_SHIFT) +#define CQCR_QSM_PEN (0x1 << CQCR_QSM_SHIFT) +#define CQCR_QSM_FQS (0x2 << CQCR_QSM_SHIFT) +#define CQCR_QSM_FQS_PEN (0x3 << CQCR_QSM_SHIFT) +#define CQCR_QSM_MASK (0x3 << CQCR_QSM_SHIFT) +#define CQCR_FQS (1 << 2) +#define CQCR_RPT (1 << 3) +#define CQCR_LAST_ITEM_ID_SHIFT 4 +#define CQCR_LAST_ITEM_ID_MASK (0xf << CQCR_LAST_ITEM_ID_SHIFT) +#define CQCR_FIFOWATERMARK_SHIFT 8 +#define CQCR_FIFOWATERMARK_MASK (0xf << CQCR_FIFOWATERMARK_SHIFT) +#define CQCR_REPEATWAIT_SHIFT 12 +#define CQCR_REPEATWAIT_MASK (0xf << CQCR_REPEATWAIT_SHIFT) +#define CQCR_QRST (1 << 16) +#define CQCR_FRST (1 << 17) +#define CQCR_PD_MSK (1 << 18) +#define CQCR_PD_CFG (1 << 19) + +/* TouchScreen Convert Queue Status Register */ +#define TCQSR 0x408 +#define CQSR_PD (1 << 0) +#define CQSR_EOQ (1 << 1) +#define CQSR_FOR (1 << 4) +#define CQSR_FUR (1 << 5) +#define CQSR_FER (1 << 6) +#define CQSR_EMPT (1 << 13) +#define CQSR_FULL (1 << 14) +#define CQSR_FDRY (1 << 15) + +/* TouchScreen Convert Queue Mask Register */ +#define TCQMR 0x40c +#define TCQMR_PD_IRQ_MSK (1 << 0) +#define TCQMR_EOQ_IRQ_MSK (1 << 1) +#define TCQMR_FOR_IRQ_MSK (1 << 4) +#define TCQMR_FUR_IRQ_MSK (1 << 5) +#define TCQMR_FER_IRQ_MSK (1 << 6) +#define TCQMR_PD_DMA_MSK (1 << 16) +#define TCQMR_EOQ_DMA_MSK (1 << 17) +#define TCQMR_FOR_DMA_MSK (1 << 20) +#define TCQMR_FUR_DMA_MSK (1 << 21) +#define TCQMR_FER_DMA_MSK (1 << 22) +#define TCQMR_FDRY_DMA_MSK (1 << 31) + +/* TouchScreen Convert Queue ITEM 7~0 */ +#define TCQ_ITEM_7_0 0x420 + +/* TouchScreen Convert Queue ITEM 15~8 */ +#define TCQ_ITEM_15_8 0x424 + +#define TCQ_ITEM7_SHIFT 28 +#define TCQ_ITEM6_SHIFT 24 +#define TCQ_ITEM5_SHIFT 20 +#define TCQ_ITEM4_SHIFT 16 +#define TCQ_ITEM3_SHIFT 12 +#define TCQ_ITEM2_SHIFT 8 +#define TCQ_ITEM1_SHIFT 4 +#define TCQ_ITEM0_SHIFT 0 + +#define TCQ_ITEM_TCC0 0x0 +#define TCQ_ITEM_TCC1 0x1 +#define TCQ_ITEM_TCC2 0x2 +#define TCQ_ITEM_TCC3 0x3 +#define TCQ_ITEM_TCC4 0x4 +#define TCQ_ITEM_TCC5 0x5 +#define TCQ_ITEM_TCC6 0x6 +#define TCQ_ITEM_TCC7 0x7 +#define TCQ_ITEM_GCC7 0x8 +#define TCQ_ITEM_GCC6 0x9 +#define TCQ_ITEM_GCC5 0xa +#define TCQ_ITEM_GCC4 0xb +#define TCQ_ITEM_GCC3 0xc +#define TCQ_ITEM_GCC2 0xd +#define TCQ_ITEM_GCC1 0xe +#define TCQ_ITEM_GCC0 0xf + +/* TouchScreen Convert Config 0-7 */ +#define TCC0 0x440 +#define TCC1 0x444 +#define TCC2 0x448 +#define TCC3 0x44c +#define TCC4 0x450 +#define TCC5 0x454 +#define TCC6 0x458 +#define TCC7 0x45c +#define CC_PEN_IACK (1 << 1) +#define CC_SEL_REFN_SHIFT 2 +#define CC_SEL_REFN_YNLR (0x1 << CC_SEL_REFN_SHIFT) +#define CC_SEL_REFN_AGND (0x2 << CC_SEL_REFN_SHIFT) +#define CC_SEL_REFN_MASK (0x3 << CC_SEL_REFN_SHIFT) +#define CC_SELIN_SHIFT 4 +#define CC_SELIN_XPUL (0x0 << CC_SELIN_SHIFT) +#define CC_SELIN_YPLL (0x1 << CC_SELIN_SHIFT) +#define CC_SELIN_XNUR (0x2 << CC_SELIN_SHIFT) +#define CC_SELIN_YNLR (0x3 << CC_SELIN_SHIFT) +#define CC_SELIN_WIPER (0x4 << CC_SELIN_SHIFT) +#define CC_SELIN_INAUX0 (0x5 << CC_SELIN_SHIFT) +#define CC_SELIN_INAUX1 (0x6 << CC_SELIN_SHIFT) +#define CC_SELIN_INAUX2 (0x7 << CC_SELIN_SHIFT) +#define CC_SELIN_MASK (0x7 << CC_SELIN_SHIFT) +#define CC_SELREFP_SHIFT 7 +#define CC_SELREFP_YPLL (0x0 << CC_SELREFP_SHIFT) +#define CC_SELREFP_XPUL (0x1 << CC_SELREFP_SHIFT) +#define CC_SELREFP_EXT (0x2 << CC_SELREFP_SHIFT) +#define CC_SELREFP_INT (0x3 << CC_SELREFP_SHIFT) +#define CC_SELREFP_MASK (0x3 << CC_SELREFP_SHIFT) +#define CC_XPULSW (1 << 9) +#define CC_XNURSW_SHIFT 10 +#define CC_XNURSW_HIGH (0x0 << CC_XNURSW_SHIFT) +#define CC_XNURSW_OFF (0x1 << CC_XNURSW_SHIFT) +#define CC_XNURSW_LOW (0x3 << CC_XNURSW_SHIFT) +#define CC_XNURSW_MASK (0x3 << CC_XNURSW_SHIFT) +#define CC_YPLLSW_SHIFT 12 +#define CC_YPLLSW_MASK (0x3 << CC_YPLLSW_SHIFT) +#define CC_YNLRSW (1 << 14) +#define CC_WIPERSW (1 << 15) +#define CC_NOS_SHIFT 16 +#define CC_YPLLSW_HIGH (0x0 << CC_NOS_SHIFT) +#define CC_YPLLSW_OFF (0x1 << CC_NOS_SHIFT) +#define CC_YPLLSW_LOW (0x3 << CC_NOS_SHIFT +#define CC_NOS_MASK (0xf << CC_NOS_SHIFT) +#define CC_IGS (1 << 20) +#define CC_SETTLING_TIME_SHIFT 24 +#define CC_SETTLING_TIME_MASK (0xff << CC_SETTLING_TIME_SHIFT) + +#define TSC_4WIRE_PRECHARGE 0x158c +#define TSC_4WIRE_TOUCH_DETECT 0x578e + +#define TSC_4WIRE_X_MEASUMENT 0x1c90 +#define TSC_4WIRE_Y_MEASUMENT 0x4604 + +#define TSC_GENERAL_ADC_GCC0 0x17dc +#define TSC_GENERAL_ADC_GCC1 0x17ec +#define TSC_GENERAL_ADC_GCC2 0x17fc + +/* GeneralADC Convert Queue FIFO Register */ +#define GCQFIFO 0x800 +#define GCQFIFO_ADCOUT_SHIFT 4 +#define GCQFIFO_ADCOUT_MASK (0xfff << GCQFIFO_ADCOUT_SHIFT) +/* GeneralADC Convert Queue Control Register */ +#define GCQCR 0x804 +/* GeneralADC Convert Queue Status Register */ +#define GCQSR 0x808 +/* GeneralADC Convert Queue Mask Register */ +#define GCQMR 0x80c + +/* GeneralADC Convert Queue ITEM 7~0 */ +#define GCQ_ITEM_7_0 0x820 +/* GeneralADC Convert Queue ITEM 15~8 */ +#define GCQ_ITEM_15_8 0x824 + +#define GCQ_ITEM7_SHIFT 28 +#define GCQ_ITEM6_SHIFT 24 +#define GCQ_ITEM5_SHIFT 20 +#define GCQ_ITEM4_SHIFT 16 +#define GCQ_ITEM3_SHIFT 12 +#define GCQ_ITEM2_SHIFT 8 +#define GCQ_ITEM1_SHIFT 4 +#define GCQ_ITEM0_SHIFT 0 + +#define GCQ_ITEM_GCC0 0x0 +#define GCQ_ITEM_GCC1 0x1 +#define GCQ_ITEM_GCC2 0x2 +#define GCQ_ITEM_GCC3 0x3 + +/* GeneralADC Convert Config 0-7 */ +#define GCC0 0x840 +#define GCC1 0x844 +#define GCC2 0x848 +#define GCC3 0x84c +#define GCC4 0x850 +#define GCC5 0x854 +#define GCC6 0x858 +#define GCC7 0x85c + +/* TSC Test Register R/W */ +#define TTR 0xc00 +/* TSC Monitor Register 1, 2 */ +#define MNT1 0xc04 +#define MNT2 0xc04 + +#define DETECT_ITEM_ID_1 1 +#define DETECT_ITEM_ID_2 5 +#define TS_X_ITEM_ID 2 +#define TS_Y_ITEM_ID 3 +#define TSI_DATA 1 +#define FQS_DATA 0 + +#endif /* __IMX_ADC_H__ */ diff -urN linux-2.6.26/drivers/mxc/asrc/Kconfig linux-2.6.26-lab126/drivers/mxc/asrc/Kconfig --- linux-2.6.26/drivers/mxc/asrc/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/asrc/Kconfig 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,13 @@ +# +# ASRC configuration +# + +menu "MXC Asynchronous Sample Rate Converter support" + +config MXC_ASRC + tristate "ASRC support" + depends on ARCH_MX35 + ---help--- + Say Y to get the ASRC service. + +endmenu diff -urN linux-2.6.26/drivers/mxc/asrc/Makefile linux-2.6.26-lab126/drivers/mxc/asrc/Makefile --- linux-2.6.26/drivers/mxc/asrc/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/asrc/Makefile 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,7 @@ +# +# Makefile for the kernel Asynchronous Sample Rate Converter driver +# + +ifeq ($(CONFIG_ARCH_MX35),y) + obj-$(CONFIG_MXC_ASRC) += mxc_asrc.o +endif diff -urN linux-2.6.26/drivers/mxc/asrc/mxc_asrc.c linux-2.6.26-lab126/drivers/mxc/asrc/mxc_asrc.c --- linux-2.6.26/drivers/mxc/asrc/mxc_asrc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/asrc/mxc_asrc.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,1579 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_asrc.c + * + * @brief MXC Asynchronous Sample Rate Converter + * + * @ingroup SOUND + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int asrc_major; +static struct class *asrc_class; +#define ASRC_PROC_PATH "driver/asrc" + +#define ASRC_RATIO_DECIMAL_DEPTH 26 + +DEFINE_SPINLOCK(data_lock); +DEFINE_SPINLOCK(input_int_lock); +DEFINE_SPINLOCK(output_int_lock); + +char *asrc_pair_id[] = { + [0] = "ASRC RX PAIR A", + [1] = "ASRC TX PAIR A", + [2] = "ASRC RX PAIR B", + [3] = "ASRC TX PAIR B", + [4] = "ASRC RX PAIR C", + [5] = "ASRC TX PAIR C", +}; + +enum asrc_status { + ASRC_ASRSTR_AIDEA = 0x01, + ASRC_ASRSTR_AIDEB = 0x02, + ASRC_ASRSTR_AIDEC = 0x04, + ASRC_ASRSTR_AODFA = 0x08, + ASRC_ASRSTR_AODFB = 0x10, + ASRC_ASRSTR_AODFC = 0x20, + ASRC_ASRSTR_AOLE = 0x40, + ASRC_ASRSTR_FPWT = 0x80, + ASRC_ASRSTR_AIDUA = 0x100, + ASRC_ASRSTR_AIDUB = 0x200, + ASRC_ASRSTR_AIDUC = 0x400, + ASRC_ASRSTR_AODOA = 0x800, + ASRC_ASRSTR_AODOB = 0x1000, + ASRC_ASRSTR_AODOC = 0x2000, + ASRC_ASRSTR_AIOLA = 0x4000, + ASRC_ASRSTR_AIOLB = 0x8000, + ASRC_ASRSTR_AIOLC = 0x10000, + ASRC_ASRSTR_AOOLA = 0x20000, + ASRC_ASRSTR_AOOLB = 0x40000, + ASRC_ASRSTR_AOOLC = 0x80000, + ASRC_ASRSTR_ATQOL = 0x100000, + ASRC_ASRSTR_DSLCNT = 0x200000, +}; + +static const unsigned char asrc_process_table[][8][2] = { + /* 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 128kHz 192kHz */ +/*8kHz*/ + {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, +/*12kHz*/ + {{0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, +/*16kHz*/ + {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, +/*24kHz*/ + {{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, +/*32kHz*/ + {{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0},}, +/*44.1kHz*/ + {{0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, +/*48kHz*/ + {{0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},}, +/*64kHz*/ + {{0, 2}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},}, +/*88.2kHz*/ + {{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, +/*96kHz*/ + {{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, +/*128kHz*/ + {{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, +/*192kHz*/ + {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, +}; + +static const unsigned char asrc_divider_table[] = { +/*8kHz 12kHz 16kHz 24kHz 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 128kHz 192kHz*/ + 0x15, 0x06, 0x14, 0x05, 0x13, 0x04, 0x04, 0x12, 0x03, 0x03, 0x11, 0x02, +}; + +static struct asrc_data *g_asrc_data; +static struct proc_dir_entry *proc_asrc; +static unsigned long asrc_vrt_base_addr; +static struct mxc_asrc_platform_data *mxc_asrc_data; + +static int asrc_set_clock_ratio(enum asrc_pair_index index, + int input_sample_rate, int output_sample_rate) +{ + int i; + int integ = 0; + unsigned long reg_val = 0; + + if (output_sample_rate == 0) + return -1; + while (input_sample_rate >= output_sample_rate) { + input_sample_rate -= output_sample_rate; + integ++; + } + reg_val |= (integ << 26); + + for (i = 1; i <= ASRC_RATIO_DECIMAL_DEPTH; i++) { + if ((input_sample_rate * 2) >= output_sample_rate) { + reg_val |= (1 << (ASRC_RATIO_DECIMAL_DEPTH - i)); + input_sample_rate = + input_sample_rate * 2 - output_sample_rate; + } else + input_sample_rate = input_sample_rate << 1; + + if (input_sample_rate == 0) + break; + } + + __raw_writel(reg_val, + (asrc_vrt_base_addr + ASRC_ASRIDRLA_REG + (index << 3))); + __raw_writel((reg_val >> 24), + (asrc_vrt_base_addr + ASRC_ASRIDRHA_REG + (index << 3))); + return 0; +} + +static int asrc_set_process_configuration(enum asrc_pair_index index, + int input_sample_rate, + int output_sample_rate) +{ + int i = 0, j = 0; + unsigned long reg; + switch (input_sample_rate) { + case 8000: + i = 0; + break; + case 12000: + i = 1; + break; + case 16000: + i = 2; + break; + case 24000: + i = 3; + break; + case 32000: + i = 4; + break; + case 44100: + i = 5; + break; + case 48000: + i = 6; + break; + case 64000: + i = 7; + break; + case 88200: + i = 8; + break; + case 96000: + i = 9; + break; + case 128000: + i = 10; + break; + case 192000: + i = 11; + break; + default: + return -1; + } + + switch (output_sample_rate) { + case 32000: + j = 0; + break; + case 44100: + j = 1; + break; + case 48000: + j = 2; + break; + case 64000: + j = 3; + break; + case 88200: + j = 4; + break; + case 96000: + j = 5; + break; + case 128000: + j = 6; + break; + case 192000: + j = 7; + break; + default: + return -1; + } + + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCFG_REG); + reg &= ~(0x0f << (6 + (index << 2))); + reg |= + ((asrc_process_table[i][j][0] << (6 + (index << 2))) | + (asrc_process_table[i][j][1] << (8 + (index << 2)))); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCFG_REG); + + return 0; +} + +static int asrc_set_idealratio_clock_divider(enum asrc_pair_index index, + int input_sample_rate, + int output_sample_rate) +{ + int i = 0, j = 0; + unsigned long reg; + switch (input_sample_rate) { + case 8000: + i = 0; + break; + case 12000: + i = 1; + break; + case 16000: + i = 2; + break; + case 24000: + i = 3; + break; + case 32000: + i = 4; + break; + case 44100: + i = 5; + break; + case 48000: + i = 6; + break; + case 64000: + i = 7; + break; + case 88200: + i = 8; + break; + case 96000: + i = 9; + break; + case 128000: + i = 10; + break; + case 192000: + i = 11; + break; + default: + return -1; + } + + switch (output_sample_rate) { + case 32000: + j = 0; + break; + case 44100: + j = 1; + break; + case 48000: + j = 2; + break; + case 64000: + j = 3; + break; + case 88200: + j = 4; + break; + case 96000: + j = 5; + break; + case 128000: + j = 6; + break; + case 192000: + j = 7; + break; + default: + return -1; + } + if (index == ASRC_PAIR_A) { + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCDR1_REG); + reg &= 0xfc0fc0; + reg |= + (asrc_divider_table[i] | (asrc_divider_table[j + 4] << 12)); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCDR1_REG); + } else if (index == ASRC_PAIR_B) { + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCDR1_REG); + reg &= 0x3f03f; + reg |= + ((asrc_divider_table[i] << 6) | + (asrc_divider_table[j + 4] << 18)); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCDR1_REG); + } else { + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCDR2_REG); + reg = + (asrc_divider_table[i] | (asrc_divider_table[j + 4] << 6)); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCDR2_REG); + } + + return 0; +} + +int asrc_req_pair(int chn_num, enum asrc_pair_index *index) +{ + int err = 0; + unsigned long lock_flags; + spin_lock_irqsave(&data_lock, lock_flags); + if (chn_num > 2) { + if (g_asrc_data->asrc_pair[ASRC_PAIR_C].active + || (chn_num > g_asrc_data->asrc_pair[ASRC_PAIR_C].chn_max)) + err = -EBUSY; + else { + *index = ASRC_PAIR_C; + g_asrc_data->asrc_pair[ASRC_PAIR_C].chn_num = chn_num; + g_asrc_data->asrc_pair[ASRC_PAIR_C].active = 1; + } + } else { + if (g_asrc_data->asrc_pair[ASRC_PAIR_A].active || + (g_asrc_data->asrc_pair[ASRC_PAIR_A].chn_max == 0)) { + if (g_asrc_data->asrc_pair[ASRC_PAIR_B]. + active + || (g_asrc_data->asrc_pair[ASRC_PAIR_B]. + chn_max == 0)) + err = -EBUSY; + else { + *index = ASRC_PAIR_B; + g_asrc_data->asrc_pair[ASRC_PAIR_B].chn_num = 2; + g_asrc_data->asrc_pair[ASRC_PAIR_B].active = 1; + } + } else { + *index = ASRC_PAIR_A; + g_asrc_data->asrc_pair[ASRC_PAIR_A].chn_num = 2; + g_asrc_data->asrc_pair[ASRC_PAIR_A].active = 1; + } + } + spin_unlock_irqrestore(&data_lock, lock_flags); + return err; +} + +EXPORT_SYMBOL(asrc_req_pair); + +void asrc_release_pair(enum asrc_pair_index index) +{ + unsigned long reg; + unsigned long lock_flags; + + spin_lock_irqsave(&data_lock, lock_flags); + g_asrc_data->asrc_pair[index].active = 0; + g_asrc_data->asrc_pair[index].overload_error = 0; + /********Disable PAIR*************/ + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG); + reg &= ~(1 << (index + 1)); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG); + spin_unlock_irqrestore(&data_lock, lock_flags); +} + +EXPORT_SYMBOL(asrc_release_pair); + +int asrc_config_pair(struct asrc_config *config) +{ + int err = 0; + int reg, tmp, channel_num; + unsigned long lock_flags; + /* Set the channel number */ + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCNCR_REG); + spin_lock_irqsave(&data_lock, lock_flags); + g_asrc_data->asrc_pair[config->pair].chn_num = config->channel_num; + spin_unlock_irqrestore(&data_lock, lock_flags); + reg &= + ~((0xFFFFFFFF >> (32 - mxc_asrc_data->channel_bits)) << + (mxc_asrc_data->channel_bits * config->pair)); + if (mxc_asrc_data->channel_bits > 3) + channel_num = config->channel_num; + else + channel_num = (config->channel_num + 1) / 2; + tmp = channel_num << (mxc_asrc_data->channel_bits * config->pair); + reg |= tmp; + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCNCR_REG); + + /* Set the clock source */ + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCSR_REG); + tmp = ~(0x0f << (config->pair << 2)); + reg &= tmp; + tmp = ~(0x0f << (12 + (config->pair << 2))); + reg &= tmp; + reg |= + ((config->inclk << (config->pair << 2)) | (config-> + outclk << (12 + + (config-> + pair << + 2)))); + + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCSR_REG); + + /* default setting */ + /* automatic selection for processing mode */ + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG); + reg |= (1 << (20 + config->pair)); + reg &= ~(1 << (14 + (config->pair << 1))); + + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG); + + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRRA_REG); + reg &= 0xffbfffff; + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRRA_REG); + + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG); + reg = reg & (~(1 << 23)); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG); + + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCDR1_REG); + if (config->pair == ASRC_PAIR_A) { + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCDR1_REG); + reg &= 0xfc0fc0; + if (config->word_width == 16 || config->word_width == 8) + reg |= 0x005005; + else if (config->word_width == 32 || config->word_width == 24) + reg |= 0x006006; + else + err = -EFAULT; + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCDR1_REG); + } else if (config->pair == ASRC_PAIR_B) { + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCDR1_REG); + reg &= 0x03f03f; + if (config->word_width == 16 || config->word_width == 8) + reg |= 0x140140; + else if (config->word_width == 32 || config->word_width == 24) + reg |= 0x180180; + else + err = -EFAULT; + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCDR1_REG); + } else { + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCDR2_REG); + if (config->word_width == 16 || config->word_width == 8) + reg |= 0x145; + else if (config->word_width == 32 || config->word_width == 24) + reg |= 0x186; + else + err = -EFAULT; + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCDR2_REG); + } + + /* check whether ideal ratio is a must */ + if ((config->inclk & 0x0f) == INCLK_NONE) { + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG); + reg &= ~(1 << (20 + config->pair)); + reg |= (0x03 << (13 + (config->pair << 1))); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG); + err = asrc_set_clock_ratio(config->pair, + config->input_sample_rate, + config->output_sample_rate); + if (err < 0) + return err; + + err = asrc_set_process_configuration(config->pair, + config->input_sample_rate, + config-> + output_sample_rate); + if (err < 0) + return err; + + if ((config->outclk & 0xf) == OUTCLK_ASRCK1_CLK) { + err = asrc_set_idealratio_clock_divider(config->pair, + config-> + input_sample_rate, + config-> + output_sample_rate); + if (err < 0) + return err; + } + } else if ((config->inclk & 0x0f) == INCLK_ASRCK1_CLK) { + if (config->input_sample_rate == 44100 + || config->input_sample_rate == 88200) { + pr_info + ("ASRC core clock cann't support sample rate %d\n", + config->input_sample_rate); + err = -EFAULT; + } + } else if ((config->outclk & 0x0f) == OUTCLK_ASRCK1_CLK) { + if (config->output_sample_rate == 44100 + || config->output_sample_rate == 88200) { + pr_info + ("ASRC core clock cann't support sample rate %d\n", + config->input_sample_rate); + err = -EFAULT; + } + } + + return err; +} + +EXPORT_SYMBOL(asrc_config_pair); + +void asrc_start_conv(enum asrc_pair_index index) +{ + int reg, reg_1; + unsigned long lock_flags; + int i; + + spin_lock_irqsave(&data_lock, lock_flags); + + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRSTR_REG); + + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG); + if ((reg & 0x0E) == 0) + clk_enable(mxc_asrc_data->asrc_audio_clk); + reg |= (1 << (1 + index)); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG); + + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCFG_REG); + while (!(reg & (1 << (index + 21)))) + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCFG_REG); + reg_1 = __raw_readl(asrc_vrt_base_addr + ASRC_ASRSTR_REG); + for (i = 0; i < 20; i++) { + reg = 0; + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRDIA_REG); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRDIA_REG); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRDIA_REG); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRDIA_REG); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRDIA_REG); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRDIA_REG); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRDIA_REG); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRDIA_REG); + } + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRSTR_REG); + + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG); + __raw_writel(0x40, asrc_vrt_base_addr + ASRC_ASRIER_REG); + spin_unlock_irqrestore(&data_lock, lock_flags); + return; +} + +EXPORT_SYMBOL(asrc_start_conv); + +void asrc_stop_conv(enum asrc_pair_index index) +{ + int reg; + unsigned long lock_flags; + spin_lock_irqsave(&data_lock, lock_flags); + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG); + reg &= ~(1 << (1 + index)); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG); + if ((reg & 0x0E) == 0) + clk_disable(mxc_asrc_data->asrc_audio_clk); + spin_unlock_irqrestore(&data_lock, lock_flags); + return; +} + +EXPORT_SYMBOL(asrc_stop_conv); + +/*! + * @brief asrc interrupt handler + */ +static irqreturn_t asrc_isr(int irq, void *dev_id) +{ + unsigned long status; + int reg = 0x40; + + status = __raw_readl(asrc_vrt_base_addr + ASRC_ASRSTR_REG); + if (g_asrc_data->asrc_pair[ASRC_PAIR_A].active == 1) { + if (status & ASRC_ASRSTR_ATQOL) + g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |= + ASRC_TASK_Q_OVERLOAD; + if (status & ASRC_ASRSTR_AOOLA) + g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |= + ASRC_OUTPUT_TASK_OVERLOAD; + if (status & ASRC_ASRSTR_AIOLA) + g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |= + ASRC_INPUT_TASK_OVERLOAD; + if (status & ASRC_ASRSTR_AODOA) + g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |= + ASRC_OUTPUT_BUFFER_OVERFLOW; + if (status & ASRC_ASRSTR_AIDUA) + g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |= + ASRC_INPUT_BUFFER_UNDERRUN; + } else if (g_asrc_data->asrc_pair[ASRC_PAIR_B].active == 1) { + if (status & ASRC_ASRSTR_ATQOL) + g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |= + ASRC_TASK_Q_OVERLOAD; + if (status & ASRC_ASRSTR_AOOLB) + g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |= + ASRC_OUTPUT_TASK_OVERLOAD; + if (status & ASRC_ASRSTR_AIOLB) + g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |= + ASRC_INPUT_TASK_OVERLOAD; + if (status & ASRC_ASRSTR_AODOB) + g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |= + ASRC_OUTPUT_BUFFER_OVERFLOW; + if (status & ASRC_ASRSTR_AIDUB) + g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |= + ASRC_INPUT_BUFFER_UNDERRUN; + } else if (g_asrc_data->asrc_pair[ASRC_PAIR_C].active == 1) { + if (status & ASRC_ASRSTR_ATQOL) + g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |= + ASRC_TASK_Q_OVERLOAD; + if (status & ASRC_ASRSTR_AOOLC) + g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |= + ASRC_OUTPUT_TASK_OVERLOAD; + if (status & ASRC_ASRSTR_AIOLC) + g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |= + ASRC_INPUT_TASK_OVERLOAD; + if (status & ASRC_ASRSTR_AODOC) + g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |= + ASRC_OUTPUT_BUFFER_OVERFLOW; + if (status & ASRC_ASRSTR_AIDUC) + g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |= + ASRC_INPUT_BUFFER_UNDERRUN; + } + + /* try to clean the overload error */ + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRSTR_REG); + + return IRQ_HANDLED; +} + +void asrc_get_status(struct asrc_status_flags *flags) +{ + unsigned int reg; + unsigned long lock_flags; + enum asrc_pair_index index; + + spin_lock_irqsave(&data_lock, lock_flags); + index = flags->index; + flags->overload_error = g_asrc_data->asrc_pair[index].overload_error; + + spin_unlock_irqrestore(&data_lock, lock_flags); + return; +} + +EXPORT_SYMBOL(asrc_get_status); + +static int mxc_init_asrc(void) +{ + /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */ + __raw_writel(0x0001, asrc_vrt_base_addr + ASRC_ASRCTR_REG); + + /* Enable overflow interrupt */ + __raw_writel(0x00, asrc_vrt_base_addr + ASRC_ASRIER_REG); + + /* Default 6: 2: 2 channel assignment */ + __raw_writel((0x06 << mxc_asrc_data->channel_bits * + 2) | (0x02 << mxc_asrc_data->channel_bits) | 0x02, + asrc_vrt_base_addr + ASRC_ASRCNCR_REG); + + /* Parameter Registers recommended settings */ + __raw_writel(0x7fffff, asrc_vrt_base_addr + ASRC_ASRPM1_REG); + __raw_writel(0x255555, asrc_vrt_base_addr + ASRC_ASRPM2_REG); + __raw_writel(0xff7280, asrc_vrt_base_addr + ASRC_ASRPM3_REG); + __raw_writel(0xff7280, asrc_vrt_base_addr + ASRC_ASRPM4_REG); + __raw_writel(0xff7280, asrc_vrt_base_addr + ASRC_ASRPM5_REG); + + __raw_writel(0x001f00, asrc_vrt_base_addr + ASRC_ASRTFR1); + + /* Set the processing clock for 76KHz, 133M */ + __raw_writel(0x06D6, asrc_vrt_base_addr + ASRC_ASR76K_REG); + + /* Set the processing clock for 56KHz, 133M */ + __raw_writel(0x0947, asrc_vrt_base_addr + ASRC_ASR56K_REG); + + if (request_irq(MXC_INT_ASRC, asrc_isr, 0, "asrc", NULL)) + return -1; + + return 0; +} + +static int asrc_get_output_buffer_size(int input_buffer_size, + int input_sample_rate, + int output_sample_rate) +{ + int i = 0; + int outbuffer_size = 0; + int outsample = output_sample_rate; + while (outsample >= input_sample_rate) { + ++i; + outsample -= input_sample_rate; + } + outbuffer_size = i * input_buffer_size; + i = 1; + while (((input_buffer_size >> i) > 2) && (outsample != 0)) { + if (((outsample << 1) - input_sample_rate) >= 0) { + outsample = (outsample << 1) - input_sample_rate; + outbuffer_size += (input_buffer_size >> i); + } else { + outsample = outsample << 1; + } + i++; + } + outbuffer_size = (outbuffer_size >> 3) << 3; + return outbuffer_size; +} + +static void asrc_input_dma_callback(void *data, int error, unsigned int count) +{ + struct asrc_pair_params *params; + struct dma_block *block; + mxc_dma_requestbuf_t dma_request; + unsigned long lock_flags; + + params = data; + + spin_lock_irqsave(&input_int_lock, lock_flags); + params->input_queue_empty--; + if (!list_empty(¶ms->input_queue)) { + block = + list_entry(params->input_queue.next, + struct dma_block, queue); + dma_request.src_addr = (dma_addr_t) block->dma_paddr; + dma_request.dst_addr = + (ASRC_BASE_ADDR + ASRC_ASRDIA_REG + (params->index << 3)); + dma_request.num_of_bytes = block->length; + mxc_dma_config(params->input_dma_channel, &dma_request, + 1, MXC_DMA_MODE_WRITE); + mxc_dma_enable(params->input_dma_channel); + list_del(params->input_queue.next); + list_add_tail(&block->queue, ¶ms->input_done_queue); + params->input_queue_empty++; + } + params->input_counter++; + wake_up_interruptible(¶ms->input_wait_queue); + spin_unlock_irqrestore(&input_int_lock, lock_flags); + return; +} + +static void asrc_output_dma_callback(void *data, int error, unsigned int count) +{ + struct asrc_pair_params *params; + struct dma_block *block; + mxc_dma_requestbuf_t dma_request; + unsigned long lock_flags; + + params = data; + + spin_lock_irqsave(&output_int_lock, lock_flags); + params->output_queue_empty--; + + if (!list_empty(¶ms->output_queue)) { + block = + list_entry(params->output_queue.next, + struct dma_block, queue); + dma_request.src_addr = + (ASRC_BASE_ADDR + ASRC_ASRDOA_REG + (params->index << 3)); + dma_request.dst_addr = (dma_addr_t) block->dma_paddr; + dma_request.num_of_bytes = block->length; + mxc_dma_config(params->output_dma_channel, &dma_request, + 1, MXC_DMA_MODE_READ); + mxc_dma_enable(params->output_dma_channel); + list_del(params->output_queue.next); + list_add_tail(&block->queue, ¶ms->output_done_queue); + params->output_queue_empty++; + } + + params->output_counter++; + wake_up_interruptible(¶ms->output_wait_queue); + spin_unlock_irqrestore(&output_int_lock, lock_flags); + return; +} + +static void mxc_free_dma_buf(struct asrc_pair_params *params) +{ + int i; + for (i = 0; i < ASRC_DMA_BUFFER_NUM; i++) { + if (params->input_dma[i].dma_vaddr != NULL) { + dma_free_coherent(0, + params->input_buffer_size, + params->input_dma[i]. + dma_vaddr, + params->input_dma[i].dma_paddr); + params->input_dma[i].dma_vaddr = NULL; + } + if (params->output_dma[i].dma_vaddr != NULL) { + dma_free_coherent(0, + params->output_buffer_size, + params->output_dma[i]. + dma_vaddr, + params->output_dma[i].dma_paddr); + params->output_dma[i].dma_vaddr = NULL; + } + } + + return; +} + +static int mxc_allocate_dma_buf(struct asrc_pair_params *params) +{ + int i; + for (i = 0; i < ASRC_DMA_BUFFER_NUM; i++) { + params->input_dma[i].dma_vaddr = + dma_alloc_coherent(0, params->input_buffer_size, + ¶ms->input_dma[i].dma_paddr, + GFP_DMA | GFP_KERNEL); + if (params->input_dma[i].dma_vaddr == NULL) { + mxc_free_dma_buf(params); + pr_info("can't allocate buff\n"); + return -ENOBUFS; + } + } + for (i = 0; i < ASRC_DMA_BUFFER_NUM; i++) { + params->output_dma[i].dma_vaddr = + dma_alloc_coherent(0, + params->output_buffer_size, + ¶ms->output_dma[i].dma_paddr, + GFP_DMA | GFP_KERNEL); + if (params->output_dma[i].dma_vaddr == NULL) { + mxc_free_dma_buf(params); + return -ENOBUFS; + } + } + + return 0; +} + +/*! + * asrc interface - ioctl function + * + * @param inode struct inode * + * + * @param file struct file * + * + * @param cmd unsigned int + * + * @param arg unsigned long + * + * @return 0 success, ENODEV for invalid device instance, + * -1 for other errors. + */ +static int asrc_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + int err = 0; + struct asrc_pair_params *params; + params = file->private_data; + + if (down_interruptible(¶ms->busy_lock)) + return -EBUSY; + switch (cmd) { + case ASRC_REQ_PAIR: + { + struct asrc_req req; + if (copy_from_user(&req, (void __user *)arg, + sizeof(struct asrc_req))) { + err = -EFAULT; + break; + } + err = asrc_req_pair(req.chn_num, &req.index); + if (err < 0) + break; + params->pair_hold = 1; + if (copy_to_user + ((void __user *)arg, &req, sizeof(struct asrc_req))) + err = -EFAULT; + + break; + } + case ASRC_CONFIG_PAIR: + { + struct asrc_config config; + mxc_dma_device_t rx_id, tx_id; + char *rx_name, *tx_name; + int channel = -1; + if (copy_from_user + (&config, (void __user *)arg, + sizeof(struct asrc_config))) { + err = -EFAULT; + break; + } + err = asrc_config_pair(&config); + if (err < 0) + break; + params->output_buffer_size = + asrc_get_output_buffer_size(config. + dma_buffer_size, + config. + input_sample_rate, + config. + output_sample_rate); + params->input_buffer_size = config.dma_buffer_size; + if (config.buffer_num > ASRC_DMA_BUFFER_NUM) + params->buffer_num = ASRC_DMA_BUFFER_NUM; + else + params->buffer_num = config.buffer_num; + err = mxc_allocate_dma_buf(params); + if (err < 0) + break; + + /* TBD - need to update when new SDMA interface ready */ + if (config.pair == ASRC_PAIR_A) { + rx_id = MXC_DMA_ASRC_A_RX; + tx_id = MXC_DMA_ASRC_A_TX; + rx_name = asrc_pair_id[0]; + tx_name = asrc_pair_id[1]; + } else if (config.pair == ASRC_PAIR_B) { + rx_id = MXC_DMA_ASRC_B_RX; + tx_id = MXC_DMA_ASRC_B_TX; + rx_name = asrc_pair_id[2]; + tx_name = asrc_pair_id[3]; + } else { + rx_id = MXC_DMA_ASRC_C_RX; + tx_id = MXC_DMA_ASRC_C_TX; + rx_name = asrc_pair_id[4]; + tx_name = asrc_pair_id[5]; + } + channel = mxc_dma_request(rx_id, rx_name); + params->input_dma_channel = channel; + err = mxc_dma_callback_set(channel, (mxc_dma_callback_t) + asrc_input_dma_callback, + (void *)params); + channel = mxc_dma_request(tx_id, tx_name); + params->output_dma_channel = channel; + err = mxc_dma_callback_set(channel, (mxc_dma_callback_t) + asrc_output_dma_callback, + (void *)params); + /* TBD - need to update when new SDMA interface ready */ + params->input_queue_empty = 0; + params->output_queue_empty = 0; + INIT_LIST_HEAD(¶ms->input_queue); + INIT_LIST_HEAD(¶ms->input_done_queue); + INIT_LIST_HEAD(¶ms->output_queue); + INIT_LIST_HEAD(¶ms->output_done_queue); + init_waitqueue_head(¶ms->input_wait_queue); + init_waitqueue_head(¶ms->output_wait_queue); + + if (copy_to_user + ((void __user *)arg, &config, + sizeof(struct asrc_config))) + err = -EFAULT; + break; + } + case ASRC_QUERYBUF: + { + struct asrc_querybuf buffer; + if (copy_from_user + (&buffer, (void __user *)arg, + sizeof(struct asrc_querybuf))) { + err = -EFAULT; + break; + } + buffer.input_offset = + (unsigned long)params->input_dma[buffer. + buffer_index]. + dma_paddr; + buffer.input_length = params->input_buffer_size; + buffer.output_offset = + (unsigned long)params->output_dma[buffer. + buffer_index]. + dma_paddr; + buffer.output_length = params->output_buffer_size; + if (copy_to_user + ((void __user *)arg, &buffer, + sizeof(struct asrc_querybuf))) + err = -EFAULT; + break; + } + case ASRC_RELEASE_PAIR: + { + enum asrc_pair_index index; + if (copy_from_user + (&index, (void __user *)arg, + sizeof(enum asrc_pair_index))) { + err = -EFAULT; + break; + } + + mxc_dma_free(params->input_dma_channel); + mxc_dma_free(params->output_dma_channel); + mxc_free_dma_buf(params); + asrc_release_pair(index); + if (g_asrc_data->asrc_pair[ASRC_PAIR_A].active == 0 + && g_asrc_data->asrc_pair[ASRC_PAIR_A].active == 0 + && g_asrc_data->asrc_pair[ASRC_PAIR_A].active == 0) + params->pair_hold = 0; + break; + } + case ASRC_Q_INBUF: + { + struct asrc_buffer buf; + struct dma_block *block; + mxc_dma_requestbuf_t dma_request; + unsigned long lock_flags; + if (copy_from_user + (&buf, (void __user *)arg, + sizeof(struct asrc_buffer))) { + err = -EFAULT; + break; + } + spin_lock_irqsave(&input_int_lock, lock_flags); + params->input_dma[buf.index].index = buf.index; + params->input_dma[buf.index].length = buf.length; + list_add_tail(¶ms->input_dma[buf.index]. + queue, ¶ms->input_queue); + if (params->input_queue_empty == 0) { + block = + list_entry(params->input_queue.next, + struct dma_block, queue); + dma_request.src_addr = + (dma_addr_t) block->dma_paddr; + dma_request.dst_addr = + (ASRC_BASE_ADDR + ASRC_ASRDIA_REG + + (params->index << 3)); + dma_request.num_of_bytes = block->length; + mxc_dma_config(params-> + input_dma_channel, + &dma_request, 1, + MXC_DMA_MODE_WRITE); + params->input_queue_empty++; + list_del(params->input_queue.next); + list_add_tail(&block->queue, + ¶ms->input_done_queue); + } + spin_unlock_irqrestore(&input_int_lock, lock_flags); + break; + } + case ASRC_DQ_INBUF:{ + struct asrc_buffer buf; + struct dma_block *block; + unsigned long lock_flags; + if (copy_from_user + (&buf, (void __user *)arg, + sizeof(struct asrc_buffer))) { + err = -EFAULT; + break; + } + if (!wait_event_interruptible_timeout + (params->input_wait_queue, + params->input_counter != 0, 10 * HZ)) { + pr_info + ("ASRC_DQ_INBUF timeout counter %x\n", + params->input_counter); + err = -ETIME; + break; + } else if (signal_pending(current)) { + pr_info("ASRC_DQ_INBUF interrupt received\n"); + err = -ERESTARTSYS; + break; + } + spin_lock_irqsave(&input_int_lock, lock_flags); + params->input_counter--; + block = + list_entry(params->input_done_queue.next, + struct dma_block, queue); + list_del(params->input_done_queue.next); + spin_unlock_irqrestore(&input_int_lock, lock_flags); + buf.index = block->index; + buf.length = block->length; + if (copy_to_user + ((void __user *)arg, &buf, + sizeof(struct asrc_buffer))) + err = -EFAULT; + + break; + } + case ASRC_Q_OUTBUF:{ + struct asrc_buffer buf; + struct dma_block *block; + mxc_dma_requestbuf_t dma_request; + unsigned long lock_flags; + if (copy_from_user + (&buf, (void __user *)arg, + sizeof(struct asrc_buffer))) { + err = -EFAULT; + break; + } + spin_lock_irqsave(&output_int_lock, lock_flags); + params->output_dma[buf.index].index = buf.index; + params->output_dma[buf.index].length = buf.length; + list_add_tail(¶ms->output_dma[buf.index]. + queue, ¶ms->output_queue); + if (params->output_queue_empty == 0) { + block = + list_entry(params->output_queue. + next, struct dma_block, queue); + dma_request.src_addr = + (ASRC_BASE_ADDR + ASRC_ASRDOA_REG + + (params->index << 3)); + dma_request.dst_addr = + (dma_addr_t) block->dma_paddr; + dma_request.num_of_bytes = block->length; + mxc_dma_config(params-> + output_dma_channel, + &dma_request, 1, + MXC_DMA_MODE_READ); + list_del(params->output_queue.next); + list_add_tail(&block->queue, + ¶ms->output_done_queue); + params->output_queue_empty++; + } + spin_unlock_irqrestore(&output_int_lock, lock_flags); + break; + } + case ASRC_DQ_OUTBUF:{ + struct asrc_buffer buf; + struct dma_block *block; + unsigned long lock_flags; + if (copy_from_user + (&buf, (void __user *)arg, + sizeof(struct asrc_buffer))) { + err = -EFAULT; + break; + } + + if (!wait_event_interruptible_timeout + (params->output_wait_queue, + params->output_counter != 0, 10 * HZ)) { + pr_info + ("ASRC_DQ_OUTBUF timeout counter %x\n", + params->output_counter); + err = -ETIME; + break; + } else if (signal_pending(current)) { + pr_info("ASRC_DQ_INBUF interrupt received\n"); + err = -ERESTARTSYS; + break; + } + spin_lock_irqsave(&output_int_lock, lock_flags); + params->output_counter--; + block = + list_entry(params->output_done_queue.next, + struct dma_block, queue); + list_del(params->output_done_queue.next); + spin_unlock_irqrestore(&output_int_lock, lock_flags); + buf.index = block->index; + buf.length = block->length; + if (copy_to_user + ((void __user *)arg, &buf, + sizeof(struct asrc_buffer))) + err = -EFAULT; + + break; + } + case ASRC_START_CONV:{ + enum asrc_pair_index index; + struct dma_block *block; + mxc_dma_requestbuf_t dma_request; + if (copy_from_user + (&index, (void __user *)arg, + sizeof(enum asrc_pair_index))) { + err = -EFAULT; + break; + } + + if (list_empty(¶ms->input_queue)) { + err = -EFAULT; + pr_info + ("ASRC_START_CONV - no block available\n"); + break; + } + while (!list_empty(¶ms->input_queue)) { + block = + list_entry(params->input_queue.next, + struct dma_block, queue); + + dma_request.num_of_bytes = block->length; + dma_request.src_addr = + (dma_addr_t) block->dma_paddr; + dma_request.dst_addr = + (ASRC_BASE_ADDR + ASRC_ASRDIA_REG + + (index << 3)); + mxc_dma_config(params->input_dma_channel, + &dma_request, 1, + MXC_DMA_MODE_WRITE); + params->input_queue_empty++; + list_del(params->input_queue.next); + list_add_tail(&block->queue, + ¶ms->input_done_queue); + } + + while (!list_empty(¶ms->output_queue)) { + block = + list_entry(params->output_queue.next, + struct dma_block, queue); + dma_request.num_of_bytes = block->length; + dma_request.src_addr = + (ASRC_BASE_ADDR + ASRC_ASRDOA_REG + + (index << 3)); + dma_request.dst_addr = + (dma_addr_t) block->dma_paddr; + mxc_dma_config(params->output_dma_channel, + &dma_request, 1, + MXC_DMA_MODE_READ); + params->output_queue_empty++; + list_del(params->output_queue.next); + list_add_tail(&block->queue, + ¶ms->output_done_queue); + } + params->asrc_active = 1; + + asrc_start_conv(index); + mxc_dma_enable(params->input_dma_channel); + mxc_dma_enable(params->output_dma_channel); + break; + } + case ASRC_STOP_CONV:{ + enum asrc_pair_index index; + if (copy_from_user + (&index, (void __user *)arg, + sizeof(enum asrc_pair_index))) { + err = -EFAULT; + break; + } + + mxc_dma_disable(params->input_dma_channel); + mxc_dma_disable(params->output_dma_channel); + asrc_stop_conv(index); + if (g_asrc_data->asrc_pair[ASRC_PAIR_A].active == 0 + && g_asrc_data->asrc_pair[ASRC_PAIR_B].active == 0 + && g_asrc_data->asrc_pair[ASRC_PAIR_C].active == 0) + params->asrc_active = 0; + break; + } + case ASRC_STATUS:{ + struct asrc_status_flags flags; + if (copy_from_user + (&flags, (void __user *)arg, + sizeof(struct asrc_status_flags))) { + err = -EFAULT; + break; + } + asrc_get_status(&flags); + if (copy_to_user + ((void __user *)arg, &flags, + sizeof(struct asrc_status_flags))) + err = -EFAULT; + break; + } + default: + break; + } + + up(¶ms->busy_lock); + return err; +} + +/*! + * asrc interface - open function + * + * @param inode structure inode * + * + * @param file structure file * + * + * @return status 0 success, ENODEV invalid device instance, + * ENOBUFS failed to allocate buffer, ERESTARTSYS interrupted by user + */ +static int mxc_asrc_open(struct inode *inode, struct file *file) +{ + int err = 0; + struct asrc_pair_params *pair_params; + if (signal_pending(current)) + return -EINTR; + + pair_params = kzalloc(sizeof(struct asrc_pair_params), GFP_KERNEL); + if (pair_params == NULL) { + pr_debug("Failed to allocate pair_params\n"); + err = -ENOBUFS; + } + + init_MUTEX(&pair_params->busy_lock); + file->private_data = pair_params; + return err; +} + +/*! + * asrc interface - close function + * + * @param inode struct inode * + * @param file structure file * + * + * @return status 0 Success, EINTR busy lock error, ENOBUFS remap_page error + */ +static int mxc_asrc_close(struct inode *inode, struct file *file) +{ + struct asrc_pair_params *pair_params; + pair_params = file->private_data; + if (pair_params->asrc_active == 1) { + mxc_dma_disable(pair_params->input_dma_channel); + mxc_dma_disable(pair_params->output_dma_channel); + asrc_stop_conv(pair_params->index); + wake_up_interruptible(&pair_params->input_wait_queue); + wake_up_interruptible(&pair_params->output_wait_queue); + } + if (pair_params->pair_hold == 1) { + mxc_dma_free(pair_params->input_dma_channel); + mxc_dma_free(pair_params->output_dma_channel); + mxc_free_dma_buf(pair_params); + asrc_release_pair(pair_params->index); + } + kfree(pair_params); + file->private_data = NULL; + return 0; +} + +/*! + * asrc interface - mmap function + * + * @param file structure file * + * + * @param vma structure vm_area_struct * + * + * @return status 0 Success, EINTR busy lock error, ENOBUFS remap_page error + */ +static int mxc_asrc_mmap(struct file *file, struct vm_area_struct *vma) +{ + unsigned long size; + int res = 0; + size = vma->vm_end - vma->vm_start; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + if (remap_pfn_range(vma, vma->vm_start, + vma->vm_pgoff, size, vma->vm_page_prot)) + return -ENOBUFS; + + vma->vm_flags &= ~VM_IO; + return res; +} + +static struct file_operations asrc_fops = { + .owner = THIS_MODULE, + .ioctl = asrc_ioctl, + .mmap = mxc_asrc_mmap, + .open = mxc_asrc_open, + .release = mxc_asrc_close, +}; + +static int asrc_read_proc_attr(char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + unsigned long reg; + int len = 0; + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCNCR_REG); + + len += sprintf(page, "ANCA: %d\n", + (int)(reg & + (0xFFFFFFFF >> + (32 - mxc_asrc_data->channel_bits)))); + len += + sprintf(page + len, "ANCB: %d\n", + (int)((reg >> mxc_asrc_data-> + channel_bits) & (0xFFFFFFFF >> (32 - + mxc_asrc_data-> + channel_bits)))); + len += + sprintf(page + len, "ANCC: %d\n", + (int)((reg >> (mxc_asrc_data->channel_bits * 2)) & + (0xFFFFFFFF >> (32 - mxc_asrc_data->channel_bits)))); + + if (off > len) + return 0; + + *eof = (len <= count) ? 1 : 0; + *start = page + off; + + return min(count, len - (int)off); +} + +static int asrc_write_proc_attr(struct file *file, const char *buffer, + unsigned long count, void *data) +{ + char buf[50]; + unsigned long reg; + int na, nb, nc; + int total; + if (count > 48) + return -EINVAL; + if (copy_from_user(buf, buffer, count)) { + pr_debug("Attr proc write, Failed to copy buffer from user\n"); + return -EFAULT; + } + + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCNCR_REG); + sscanf(buf, "ANCA: %d\nANCB: %d\nANCC: %d", &na, &nb, &nc); + if (mxc_asrc_data->channel_bits > 3) + total = 10; + else + total = 5; + if ((na + nb + nc) != total) { + pr_info("Wrong ASRCNR settings\n"); + return -EFAULT; + } + reg = na | (nb << mxc_asrc_data-> + channel_bits) | (nc << (mxc_asrc_data->channel_bits * 2)); + + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCNCR_REG); + + return count; +} + +static void asrc_proc_create(void) +{ + struct proc_dir_entry *proc_attr; + proc_asrc = proc_mkdir(ASRC_PROC_PATH, NULL); + if (proc_asrc) { + proc_attr = create_proc_entry("ChSettings", + S_IFREG | S_IRUGO | + S_IWUSR, proc_asrc); + if (proc_attr) { + proc_attr->read_proc = asrc_read_proc_attr; + proc_attr->write_proc = asrc_write_proc_attr; + proc_attr->size = 48; + proc_attr->uid = proc_attr->gid = 0; + proc_attr->owner = THIS_MODULE; + } else { + remove_proc_entry(ASRC_PROC_PATH, NULL); + pr_info("Failed to create proc attribute entry \n"); + } + } else { + pr_info("ASRC: Failed to create proc entry %s\n", + ASRC_PROC_PATH); + } +} + +/*! + * Entry point for the asrc device + * + * @param pdev Pionter to the registered platform device + * @return Error code indicating success or failure + */ +static int mxc_asrc_probe(struct platform_device *pdev) +{ + int err = 0; + struct resource *res; + struct device *temp_class; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENOENT; + + g_asrc_data = kzalloc(sizeof(struct asrc_data), GFP_KERNEL); + + if (g_asrc_data == NULL) { + pr_info("Failed to allocate g_asrc_data\n"); + return -ENOMEM; + } + + g_asrc_data->asrc_pair[0].chn_max = 2; + g_asrc_data->asrc_pair[1].chn_max = 2; + g_asrc_data->asrc_pair[2].chn_max = 6; + g_asrc_data->asrc_pair[0].overload_error = 0; + g_asrc_data->asrc_pair[1].overload_error = 0; + g_asrc_data->asrc_pair[3].overload_error = 0; + + asrc_major = register_chrdev(asrc_major, "mxc_asrc", &asrc_fops); + if (asrc_major < 0) { + pr_info("Unable to register asrc device\n"); + err = -EBUSY; + goto error; + } + + asrc_class = class_create(THIS_MODULE, "mxc_asrc"); + if (IS_ERR(asrc_class)) { + err = PTR_ERR(asrc_class); + goto err_out_chrdev; + } + + temp_class = device_create(asrc_class, NULL, MKDEV(asrc_major, 0), + "mxc_asrc"); + if (IS_ERR(temp_class)) { + err = PTR_ERR(temp_class); + goto err_out_class; + } + + asrc_vrt_base_addr = + (unsigned long)ioremap(res->start, res->end - res->start + 1); + + mxc_asrc_data = + (struct mxc_asrc_platform_data *)pdev->dev.platform_data; + clk_enable(mxc_asrc_data->asrc_core_clk); + + asrc_proc_create(); + err = mxc_init_asrc(); + if (err < 0) + goto err_out_class; + + goto out; + + err_out_class: + clk_disable(mxc_asrc_data->asrc_core_clk); + device_destroy(asrc_class, MKDEV(asrc_major, 0)); + class_destroy(asrc_class); + err_out_chrdev: + unregister_chrdev(asrc_major, "mxc_asrc"); + error: + kfree(g_asrc_data); + out: + pr_info("mxc_asrc registered\n"); + return err; +} + +/*! + * Exit asrc device + * + * @param pdev Pionter to the registered platform device + * @return Error code indicating success or failure + */ +static int mxc_asrc_remove(struct platform_device *pdev) +{ + free_irq(MXC_INT_ASRC, NULL); + kfree(g_asrc_data); + clk_disable(mxc_asrc_data->asrc_core_clk); + mxc_asrc_data = NULL; + iounmap((unsigned long __iomem *)asrc_vrt_base_addr); + remove_proc_entry("ChSettings", proc_asrc); + remove_proc_entry(ASRC_PROC_PATH, NULL); + device_destroy(asrc_class, MKDEV(asrc_major, 0)); + class_destroy(asrc_class); + unregister_chrdev(asrc_major, "mxc_asrc"); + return 0; +} + +/*! mxc asrc driver definition + * + */ +static struct platform_driver mxc_asrc_driver = { + .driver = { + .name = "mxc_asrc", + }, + .probe = mxc_asrc_probe, + .remove = mxc_asrc_remove, +}; + +/*! + * Register asrc driver + * + */ +static __init int asrc_init(void) +{ + int ret; + ret = platform_driver_register(&mxc_asrc_driver); + return ret; +} + +/*! + * Exit and free the asrc data + * + */ static void __exit asrc_exit(void) +{ + platform_driver_unregister(&mxc_asrc_driver); + return; +} + +module_init(asrc_init); +module_exit(asrc_exit); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Asynchronous Sample Rate Converter"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/bt/Kconfig linux-2.6.26-lab126/drivers/mxc/bt/Kconfig --- linux-2.6.26/drivers/mxc/bt/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/bt/Kconfig 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,13 @@ +# +# Bluetooth configuration +# + +menu "MXC Bluetooth support" + +config MXC_BLUETOOTH + tristate "MXC Bluetooth support" + depends on MACH_MX31_3DS || MACH_MX35_3DS || MACH_MX37_3DS || MACH_MX51_3DS + ---help--- + Say Y to get the third party Bluetooth service. + +endmenu diff -urN linux-2.6.26/drivers/mxc/bt/Makefile linux-2.6.26-lab126/drivers/mxc/bt/Makefile --- linux-2.6.26/drivers/mxc/bt/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/bt/Makefile 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,4 @@ +# +# Makefile for the kernel Bluetooth power-on/reset +# +obj-$(CONFIG_MXC_BLUETOOTH) += mxc_bt.o diff -urN linux-2.6.26/drivers/mxc/bt/mxc_bt.c linux-2.6.26-lab126/drivers/mxc/bt/mxc_bt.c --- linux-2.6.26/drivers/mxc/bt/mxc_bt.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/bt/mxc_bt.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,127 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_bt.c + * + * @brief MXC Thirty party Bluetooth + * + */ + +#include +#include +#include +#include +#include + +static struct regulator *bt_vdd; +static struct regulator *bt_vdd_parent; +static struct regulator *bt_vusb; +static struct regulator *bt_vusb_parent; + +/*! + * This function poweron the bluetooth hardware module + * + * @param pdev Pointer to the platform device + * @return 0 on success, -1 otherwise. + */ +static int mxc_bt_probe(struct platform_device *pdev) +{ + struct mxc_bt_platform_data *platform_data; + platform_data = (struct mxc_bt_platform_data *)pdev->dev.platform_data; + if (platform_data->bt_vdd) { + bt_vdd = regulator_get(&pdev->dev, platform_data->bt_vdd); + regulator_enable(bt_vdd); + } + if (platform_data->bt_vdd_parent) { + bt_vdd_parent = + regulator_get(&pdev->dev, platform_data->bt_vdd_parent); + regulator_enable(bt_vdd_parent); + } + if (platform_data->bt_vusb) { + bt_vusb = regulator_get(&pdev->dev, platform_data->bt_vusb); + regulator_enable(bt_vusb); + } + if (platform_data->bt_vusb_parent) { + bt_vusb_parent = + regulator_get(&pdev->dev, platform_data->bt_vusb_parent); + regulator_enable(bt_vusb_parent); + } + + if (platform_data->bt_reset != NULL) + platform_data->bt_reset(); + return 0; + +} + +/*! + * This function poweroff the bluetooth hardware module + * + * @param pdev Pointer to the platform device + * @return 0 on success, -1 otherwise. + */ +static int mxc_bt_remove(struct platform_device *pdev) +{ + struct mxc_bt_platform_data *platform_data; + platform_data = (struct mxc_bt_platform_data *)pdev->dev.platform_data; + if (bt_vdd) { + regulator_disable(bt_vdd); + regulator_put(bt_vdd, &pdev->dev); + } + if (bt_vdd_parent) { + regulator_disable(bt_vdd_parent); + regulator_put(bt_vdd_parent, &pdev->dev); + } + if (bt_vusb) { + regulator_disable(bt_vusb); + regulator_put(bt_vusb, &pdev->dev); + } + if (bt_vusb_parent) { + regulator_disable(bt_vusb_parent); + regulator_put(bt_vusb_parent, &pdev->dev); + } + return 0; + +} + +static struct platform_driver bluetooth_driver = { + .driver = { + .name = "mxc_bt", + }, + .probe = mxc_bt_probe, + .remove = mxc_bt_remove, +}; + +/*! + * Register bluetooth driver module + * + */ +static __init int bluetooth_init(void) +{ + return platform_driver_register(&bluetooth_driver); +} + +/*! + * Exit and free the bluetooth module + * + */ +static void __exit bluetooth_exit(void) +{ + platform_driver_unregister(&bluetooth_driver); +} + +module_init(bluetooth_init); +module_exit(bluetooth_exit); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC Thirty party Bluetooth"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/dam/Kconfig linux-2.6.26-lab126/drivers/mxc/dam/Kconfig --- linux-2.6.26/drivers/mxc/dam/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/dam/Kconfig 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,13 @@ +# +# DAM API configuration +# + +menu "MXC Digital Audio Multiplexer support" + +config MXC_DAM + tristate "DAM support" + depends on ARCH_MXC + ---help--- + Say Y to get the Digital Audio Multiplexer services API available on MXC platform. + +endmenu diff -urN linux-2.6.26/drivers/mxc/dam/Makefile linux-2.6.26-lab126/drivers/mxc/dam/Makefile --- linux-2.6.26/drivers/mxc/dam/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/dam/Makefile 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,9 @@ +# +# Makefile for the kernel Digital Audio MUX (DAM) device driver. +# + +ifeq ($(CONFIG_ARCH_MX27),y) + obj-$(CONFIG_MXC_DAM) += dam_v1.o +else + obj-$(CONFIG_MXC_DAM) += dam.o +endif diff -urN linux-2.6.26/drivers/mxc/dam/dam.c linux-2.6.26-lab126/drivers/mxc/dam/dam.c --- linux-2.6.26/drivers/mxc/dam/dam.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/dam/dam.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,427 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dam.c + * @brief This is the brief documentation for this dam.c file. + * + * This file contains the implementation of the DAM driver main services + * + * @ingroup DAM + */ + +#include +#include +#include +#include +#include +#include "dam.h" + +/*! + * This include to define bool type, false and true definitions. + */ +#include + +#define ModifyRegister32(a,b,c) (c = ( ( (c)&(~(a)) ) | (b) )) + +#define DAM_VIRT_BASE_ADDR IO_ADDRESS(AUDMUX_BASE_ADDR) + +#ifndef _reg_DAM_PTCR1 +#define _reg_DAM_PTCR1 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x00))) +#endif + +#ifndef _reg_DAM_PDCR1 +#define _reg_DAM_PDCR1 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x04))) +#endif + +#ifndef _reg_DAM_PTCR2 +#define _reg_DAM_PTCR2 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x08))) +#endif + +#ifndef _reg_DAM_PDCR2 +#define _reg_DAM_PDCR2 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x0C))) +#endif + +#ifndef _reg_DAM_PTCR3 +#define _reg_DAM_PTCR3 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x10))) +#endif + +#ifndef _reg_DAM_PDCR3 +#define _reg_DAM_PDCR3 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x14))) +#endif + +#ifndef _reg_DAM_PTCR4 +#define _reg_DAM_PTCR4 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x18))) +#endif + +#ifndef _reg_DAM_PDCR4 +#define _reg_DAM_PDCR4 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x1C))) +#endif + +#ifndef _reg_DAM_PTCR5 +#define _reg_DAM_PTCR5 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x20))) +#endif + +#ifndef _reg_DAM_PDCR5 +#define _reg_DAM_PDCR5 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x24))) +#endif + +#ifndef _reg_DAM_PTCR6 +#define _reg_DAM_PTCR6 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x28))) +#endif + +#ifndef _reg_DAM_PDCR6 +#define _reg_DAM_PDCR6 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x2C))) +#endif + +#ifndef _reg_DAM_PTCR7 +#define _reg_DAM_PTCR7 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x30))) +#endif + +#ifndef _reg_DAM_PDCR7 +#define _reg_DAM_PDCR7 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x34))) +#endif + +#ifndef _reg_DAM_CNMCR +#define _reg_DAM_CNMCR (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x38))) +#endif + +#ifndef _reg_DAM_PTCR +#define _reg_DAM_PTCR(a) (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + a*8))) +#endif + +#ifndef _reg_DAM_PDCR +#define _reg_DAM_PDCR(a) (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 4 + a*8))) +#endif + +/*! + * PTCR Registers bit shift definitions + */ +#define dam_synchronous_mode_shift 11 +#define dam_receive_clock_select_shift 12 +#define dam_receive_clock_direction_shift 16 +#define dam_receive_frame_sync_select_shift 17 +#define dam_receive_frame_sync_direction_shift 21 +#define dam_transmit_clock_select_shift 22 +#define dam_transmit_clock_direction_shift 26 +#define dam_transmit_frame_sync_select_shift 27 +#define dam_transmit_frame_sync_direction_shift 31 +#define dam_selection_mask 0xF + +/*! + * HPDCR Register bit shift definitions + */ +#define dam_internal_network_mode_shift 0 +#define dam_mode_shift 8 +#define dam_transmit_receive_switch_shift 12 +#define dam_receive_data_select_shift 13 + +/*! + * HPDCR Register bit masq definitions + */ +#define dam_mode_masq 0x03 +#define dam_internal_network_mode_mask 0xFF + +/*! + * CNMCR Register bit shift definitions + */ +#define dam_ce_bus_port_cntlow_shift 0 +#define dam_ce_bus_port_cnthigh_shift 8 +#define dam_ce_bus_port_clkpol_shift 16 +#define dam_ce_bus_port_fspol_shift 17 +#define dam_ce_bus_port_enable_shift 18 + +#define DAM_NAME "dam" + +EXPORT_SYMBOL(dam_select_mode); +EXPORT_SYMBOL(dam_select_RxClk_direction); +EXPORT_SYMBOL(dam_select_RxClk_source); +EXPORT_SYMBOL(dam_select_RxD_source); +EXPORT_SYMBOL(dam_select_RxFS_direction); +EXPORT_SYMBOL(dam_select_RxFS_source); +EXPORT_SYMBOL(dam_select_TxClk_direction); +EXPORT_SYMBOL(dam_select_TxClk_source); +EXPORT_SYMBOL(dam_select_TxFS_direction); +EXPORT_SYMBOL(dam_select_TxFS_source); +EXPORT_SYMBOL(dam_set_internal_network_mode_mask); +EXPORT_SYMBOL(dam_set_synchronous); +EXPORT_SYMBOL(dam_switch_Tx_Rx); +EXPORT_SYMBOL(dam_reset_register); + +/*! + * This function selects the operation mode of the port. + * + * @param port the DAM port to configure + * @param the_mode the operation mode of the port + * + * @return This function returns the result of the operation + * (0 if successful, -1 otherwise). + */ +int dam_select_mode(dam_port port, dam_mode the_mode) +{ + int result; + result = 0; + + ModifyRegister32(dam_mode_masq << dam_mode_shift, + the_mode << dam_mode_shift, _reg_DAM_PDCR(port)); + + return result; +} + +/*! + * This function controls Receive clock signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Rx clock signal direction + */ +void dam_select_RxClk_direction(dam_port port, signal_direction direction) +{ + ModifyRegister32(1 << dam_receive_clock_direction_shift, + direction << dam_receive_clock_direction_shift, + _reg_DAM_PTCR(port)); +} + +/*! + * This function controls Receive clock signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxClk the signal comes from RxClk or TxClk of + * the source port + * @param p_source the source port + */ +void dam_select_RxClk_source(dam_port p_config, + bool from_RxClk, dam_port p_source) +{ + ModifyRegister32(dam_selection_mask << dam_receive_clock_select_shift, + ((from_RxClk << 3) | p_source) << + dam_receive_clock_select_shift, + _reg_DAM_PTCR(p_config)); +} + +/*! + * This function selects the source port for the RxD data. + * + * @param p_config the DAM port to configure + * @param p_source the source port + */ +void dam_select_RxD_source(dam_port p_config, dam_port p_source) +{ + ModifyRegister32(dam_selection_mask << dam_receive_data_select_shift, + p_source << dam_receive_data_select_shift, + _reg_DAM_PDCR(p_config)); +} + +/*! + * This function controls Receive Frame Sync signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Rx Frame Sync signal direction + */ +void dam_select_RxFS_direction(dam_port port, signal_direction direction) +{ + ModifyRegister32(1 << dam_receive_frame_sync_direction_shift, + direction << dam_receive_frame_sync_direction_shift, + _reg_DAM_PTCR(port)); +} + +/*! + * This function controls Receive Frame Sync signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxFS the signal comes from RxFS or TxFS of + * the source port + * @param p_source the source port + */ +void dam_select_RxFS_source(dam_port p_config, + bool from_RxFS, dam_port p_source) +{ + ModifyRegister32(dam_selection_mask << + dam_receive_frame_sync_select_shift, + ((from_RxFS << 3) | p_source) << + dam_receive_frame_sync_select_shift, + _reg_DAM_PTCR(p_config)); +} + +/*! + * This function controls Transmit clock signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Tx clock signal direction + */ +void dam_select_TxClk_direction(dam_port port, signal_direction direction) +{ + ModifyRegister32(1 << dam_transmit_clock_direction_shift, + direction << dam_transmit_clock_direction_shift, + _reg_DAM_PTCR(port)); +} + +/*! + * This function controls Transmit clock signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxClk the signal comes from RxClk or TxClk of + * the source port + * @param p_source the source port + */ +void dam_select_TxClk_source(dam_port p_config, + bool from_RxClk, dam_port p_source) +{ + ModifyRegister32(dam_selection_mask << dam_transmit_clock_select_shift, + ((from_RxClk << 3) | p_source) << + dam_transmit_clock_select_shift, + _reg_DAM_PTCR(p_config)); +} + +/*! + * This function controls Transmit Frame Sync signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Tx Frame Sync signal direction + */ +void dam_select_TxFS_direction(dam_port port, signal_direction direction) +{ + ModifyRegister32(1 << dam_transmit_frame_sync_direction_shift, + direction << dam_transmit_frame_sync_direction_shift, + _reg_DAM_PTCR(port)); +} + +/*! + * This function controls Transmit Frame Sync signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxFS the signal comes from RxFS or TxFS of + * the source port + * @param p_source the source port + */ +void dam_select_TxFS_source(dam_port p_config, + bool from_RxFS, dam_port p_source) +{ + ModifyRegister32(dam_selection_mask << + dam_transmit_frame_sync_select_shift, + ((from_RxFS << 3) | p_source) << + dam_transmit_frame_sync_select_shift, + _reg_DAM_PTCR(p_config)); +} + +/*! + * This function sets a bit mask that selects the port from which of the RxD + * signals are to be ANDed together for internal network mode. + * Bit 6 represents RxD from Port7 and bit0 represents RxD from Port1. + * 1 excludes RxDn from ANDing. 0 includes RxDn for ANDing. + * + * @param port the DAM port to configure + * @param bit_mask the bit mask + * + * @return This function returns the result of the operation + * (0 if successful, -1 otherwise). + */ +int dam_set_internal_network_mode_mask(dam_port port, unsigned char bit_mask) +{ + int result; + result = 0; + + ModifyRegister32(dam_internal_network_mode_mask << + dam_internal_network_mode_shift, + bit_mask << dam_internal_network_mode_shift, + _reg_DAM_PDCR(port)); + + return result; +} + +/*! + * This function controls whether or not the port is in synchronous mode. + * When the synchronous mode is selected, the receive and the transmit sections + * use common clock and frame sync signals. + * When the synchronous mode is not selected, separate clock and frame sync + * signals are used for the transmit and the receive sections. + * The defaut value is the synchronous mode selected. + * + * @param port the DAM port to configure + * @param synchronous the state to assign + */ +void dam_set_synchronous(dam_port port, bool synchronous) +{ + ModifyRegister32(1 << dam_synchronous_mode_shift, + synchronous << dam_synchronous_mode_shift, + _reg_DAM_PTCR(port)); +} + +/*! + * This function swaps the transmit and receive signals from (Da-TxD, Db-RxD) + * to (Da-RxD, Db-TxD). + * This default signal configuration is Da-TxD, Db-RxD. + * + * @param port the DAM port to configure + * @param value the switch state + */ +void dam_switch_Tx_Rx(dam_port port, bool value) +{ + ModifyRegister32(1 << dam_transmit_receive_switch_shift, + value << dam_transmit_receive_switch_shift, + _reg_DAM_PDCR(port)); +} + +/*! + * This function resets the two registers of the selected port. + * + * @param port the DAM port to reset + */ +void dam_reset_register(dam_port port) +{ + ModifyRegister32(0xFFFFFFFF, 0x00000000, _reg_DAM_PTCR(port)); + ModifyRegister32(0xFFFFFFFF, 0x00000000, _reg_DAM_PDCR(port)); +} + +/*! + * This function implements the init function of the DAM device. + * This function is called when the module is loaded. + * + * @return This function returns 0. + */ +static int __init dam_init(void) +{ + return 0; +} + +/*! + * This function implements the exit function of the SPI device. + * This function is called when the module is unloaded. + * + */ +static void __exit dam_exit(void) +{ +} + +module_init(dam_init); +module_exit(dam_exit); + +MODULE_DESCRIPTION("DAM char device driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/dam/dam.h linux-2.6.26-lab126/drivers/mxc/dam/dam.h --- linux-2.6.26/drivers/mxc/dam/dam.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/dam/dam.h 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,258 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + /*! + * @defgroup DAM Digital Audio Multiplexer (AUDMUX) Driver + */ + + /*! + * @file dam.h + * @brief This is the brief documentation for this dam.h file. + * + * This header file contains DAM driver functions prototypes. + * + * @ingroup DAM + */ + +#ifndef __MXC_DAM_H__ +#define __MXC_DAM_H__ + +/*! + * This enumeration describes the Digital Audio Multiplexer mode. + */ +typedef enum { + + /*! + * Normal mode + */ + normal_mode = 0, + + /*! + * Internal network mode + */ + internal_network_mode = 1, + + /*! + * CE bus network mode + */ + CE_bus_network_mode = 2 +} dam_mode; + +/*! + * This enumeration describes the port. + */ +typedef enum { + + /*! + * The port 1 + */ + port_1 = 0, + + /*! + * The port 2 + */ + port_2 = 1, + + /*! + * The port 3 + */ + port_3 = 2, + + /*! + * The port 4 + */ + port_4 = 3, + + /*! + * The port 5 + */ + port_5 = 4, + + /*! + * The port 6 + */ + port_6 = 5, + + /*! + * The port 7 + */ + port_7 = 6 +} dam_port; + +/*! + * This enumeration describes the signal direction. + */ +typedef enum { + + /*! + * Signal In + */ + signal_in = 0, + + /*! + * Signal Out + */ + signal_out = 1 +} signal_direction; + +/*! + * Test purpose definition + */ +#define TEST_DAM 1 + +#ifdef TEST_DAM + +#define DAM_IOCTL 0x55 +#define DAM_CONFIG_SSI1_MC13783 _IOWR(DAM_IOCTL, 1, int) +#define DAM_CONFIG_SSI2_MC13783 _IOWR(DAM_IOCTL, 2, int) +#define DAM_CONFIG_SSI_NETWORK_MODE_MC13783 _IOWR(DAM_IOCTL, 3, int) +#endif + +/*! + * This function selects the operation mode of the port. + * + * @param port the DAM port to configure + * @param the_mode the operation mode of the port + * @return This function returns the result of the operation + * (0 if successful, -1 otherwise). + */ +int dam_select_mode(dam_port port, dam_mode the_mode); + +/*! + * This function controls Receive clock signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Rx clock signal direction + */ +void dam_select_RxClk_direction(dam_port port, signal_direction direction); + +/*! + * This function controls Receive clock signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxClk the signal comes from RxClk or TxClk of + * the source port + * @param p_source the source port + */ +void dam_select_RxClk_source(dam_port p_config, bool from_RxClk, + dam_port p_source); + +/*! + * This function selects the source port for the RxD data. + * + * @param p_config the DAM port to configure + * @param p_source the source port + */ +void dam_select_RxD_source(dam_port p_config, dam_port p_source); + +/*! + * This function controls Receive Frame Sync signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Rx Frame Sync signal direction + */ +void dam_select_RxFS_direction(dam_port port, signal_direction direction); + +/*! + * This function controls Receive Frame Sync signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxFS the signal comes from RxFS or TxFS of + * the source port + * @param p_source the source port + */ +void dam_select_RxFS_source(dam_port p_config, bool from_RxFS, + dam_port p_source); + +/*! + * This function controls Transmit clock signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Tx clock signal direction + */ +void dam_select_TxClk_direction(dam_port port, signal_direction direction); + +/*! + * This function controls Transmit clock signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxClk the signal comes from RxClk or TxClk of + * the source port + * @param p_source the source port + */ +void dam_select_TxClk_source(dam_port p_config, bool from_RxClk, + dam_port p_source); + +/*! + * This function controls Transmit Frame Sync signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Tx Frame Sync signal direction + */ +void dam_select_TxFS_direction(dam_port port, signal_direction direction); + +/*! + * This function controls Transmit Frame Sync signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxFS the signal comes from RxFS or TxFS of + * the source port + * @param p_source the source port + */ +void dam_select_TxFS_source(dam_port p_config, bool from_RxFS, + dam_port p_source); + +/*! + * This function sets a bit mask that selects the port from which of + * the RxD signals are to be ANDed together for internal network mode. + * Bit 6 represents RxD from Port7 and bit0 represents RxD from Port1. + * 1 excludes RxDn from ANDing. 0 includes RxDn for ANDing. + * + * @param port the DAM port to configure + * @param bit_mask the bit mask + * @return This function returns the result of the operation + * (0 if successful, -1 otherwise). + */ +int dam_set_internal_network_mode_mask(dam_port port, unsigned char bit_mask); + +/*! + * This function controls whether or not the port is in synchronous mode. + * When the synchronous mode is selected, the receive and the transmit sections + * use common clock and frame sync signals. + * When the synchronous mode is not selected, separate clock and frame sync + * signals are used for the transmit and the receive sections. + * The defaut value is the synchronous mode selected. + * + * @param port the DAM port to configure + * @param synchronous the state to assign + */ +void dam_set_synchronous(dam_port port, bool synchronous); + +/*! + * This function swaps the transmit and receive signals from (Da-TxD, Db-RxD) to + * (Da-RxD, Db-TxD). + * This default signal configuration is Da-TxD, Db-RxD. + * + * @param port the DAM port to configure + * @param value the switch state + */ +void dam_switch_Tx_Rx(dam_port port, bool value); + +/*! + * This function resets the two registers of the selected port. + * + * @param port the DAM port to reset + */ +void dam_reset_register(dam_port port); + +#endif diff -urN linux-2.6.26/drivers/mxc/dam/dam_v1.c linux-2.6.26-lab126/drivers/mxc/dam/dam_v1.c --- linux-2.6.26/drivers/mxc/dam/dam_v1.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/dam/dam_v1.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,616 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dam_v1.c + * @brief This is the brief documentation for this dam_v1.c file. + * + * This file contains the implementation of the DAM driver main services + * + * @ingroup DAM + */ + +#include +#include +#include +#include +#include +#include +#include +#include "dam.h" + +/*! + * This include to define bool type, false and true definitions. + */ +#include + +#define DAM_VIRT_BASE_ADDR IO_ADDRESS(AUDMUX_BASE_ADDR) + +#define ModifyRegister32(a,b,c) do{\ + __raw_writel( ((__raw_readl(c)) & (~(a))) | (b),(c) );\ +}while(0) + +#ifndef _reg_DAM_HPCR1 +#define _reg_DAM_HPCR1 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x00))) +#endif + +#ifndef _reg_DAM_HPCR2 +#define _reg_DAM_HPCR2 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x04))) +#endif + +#ifndef _reg_DAM_HPCR3 +#define _reg_DAM_HPCR3 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x08))) +#endif + +#ifndef _reg_DAM_PPCR1 +#define _reg_DAM_PPCR1 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x10))) +#endif + +#ifndef _reg_DAM_PPCR2 +#define _reg_DAM_PPCR2 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x14))) +#endif + +#ifndef _reg_DAM_PPCR3 +#define _reg_DAM_PPCR3 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x1c))) +#endif + +#ifndef _reg_DAM_HPCR +#define _reg_DAM_HPCR(a) ((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + (a)*4)) +#endif + +#ifndef _reg_DAM_PPCR +#define _reg_DAM_PPCR(a) ((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x0c + (0x04 << (a-3)) )) +#endif + +/*! + * HPCR/PPCR Registers bit shift definitions + */ +#define dam_transmit_frame_sync_direction_shift 31 +#define dam_transmit_clock_direction_shift 30 +#define dam_transmit_frame_sync_select_shift 26 +#define dam_transmit_clock_select_shift 26 +#define dam_receive_frame_sync_direction_shift 25 +#define dam_receive_clock_direction_shift 24 +#define dam_receive_clock_select_shift 20 +#define dam_receive_frame_sync_select_shift 20 + +#define dam_receive_data_select_shift 13 +#define dam_synchronous_mode_shift 12 + +#define dam_transmit_receive_switch_shift 10 + +#define dam_mode_shift 8 +#define dam_internal_network_mode_shift 0 + +/*! + * HPCR/PPCR Register bit masq definitions + */ +//#define dam_selection_mask 0xF +#define dam_fs_selection_mask 0xF +#define dam_clk_selection_mask 0xF +#define dam_dat_selection_mask 0x7 +//#define dam_mode_masq 0x03 +#define dam_internal_network_mode_mask 0xFF + +/*! + * HPCR/PPCR Register reset value definitions + */ +#define dam_hpcr_default_value 0x00001000 +#define dam_ppcr_default_value 0x00001000 + +#define DAM_NAME "dam" +static struct class *mxc_dam_class; + +EXPORT_SYMBOL(dam_select_mode); +EXPORT_SYMBOL(dam_select_RxClk_direction); +EXPORT_SYMBOL(dam_select_RxClk_source); +EXPORT_SYMBOL(dam_select_RxD_source); +EXPORT_SYMBOL(dam_select_RxFS_direction); +EXPORT_SYMBOL(dam_select_RxFS_source); +EXPORT_SYMBOL(dam_select_TxClk_direction); +EXPORT_SYMBOL(dam_select_TxClk_source); +EXPORT_SYMBOL(dam_select_TxFS_direction); +EXPORT_SYMBOL(dam_select_TxFS_source); +EXPORT_SYMBOL(dam_set_internal_network_mode_mask); +EXPORT_SYMBOL(dam_set_synchronous); +EXPORT_SYMBOL(dam_switch_Tx_Rx); +EXPORT_SYMBOL(dam_reset_register); + +/*! + * DAM major + */ +#ifdef TEST_DAM +static int major_dam; + +typedef struct _mxc_cfg { + int reg; + int val; +} mxc_cfg; + +#endif + +/*! + * This function selects the operation mode of the port. + * + * @param port the DAM port to configure + * @param the_mode the operation mode of the port + * + * @return This function returns the result of the operation + * (0 if successful, -1 otherwise). + */ +int dam_select_mode(dam_port port, dam_mode the_mode) +{ + int result; + result = 0; + + if (port >= 3) + the_mode = normal_mode; + ModifyRegister32(1 << dam_mode_shift, + the_mode << dam_mode_shift, _reg_DAM_HPCR(port)); + + return result; +} + +/*! + * This function controls Receive clock signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Rx clock signal direction + */ +void dam_select_RxClk_direction(dam_port port, signal_direction direction) +{ + if (port < 3) { + ModifyRegister32(1 << dam_receive_clock_direction_shift, + direction << dam_receive_clock_direction_shift, + _reg_DAM_HPCR(port)); + } else { + ModifyRegister32(1 << dam_receive_clock_direction_shift, + direction << dam_receive_clock_direction_shift, + _reg_DAM_PPCR(port)); + } + return; +} + +/*! + * This function controls Receive clock signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxClk the signal comes from RxClk or TxClk of + * the source port + * @param p_source the source port + */ +void dam_select_RxClk_source(dam_port p_config, + bool from_RxClk, dam_port p_source) +{ + if (p_config < 3) { + ModifyRegister32(dam_clk_selection_mask << + dam_receive_clock_select_shift, + ((from_RxClk << 3) | p_source) << + dam_receive_clock_select_shift, + _reg_DAM_HPCR(p_config)); + } else { + ModifyRegister32(dam_clk_selection_mask << + dam_receive_clock_select_shift, + ((from_RxClk << 3) | p_source) << + dam_receive_clock_select_shift, + _reg_DAM_PPCR(p_config)); + } + return; +} + +/*! + * This function selects the source port for the RxD data. + * + * @param p_config the DAM port to configure + * @param p_source the source port + */ +void dam_select_RxD_source(dam_port p_config, dam_port p_source) +{ + if (p_config < 3) { + ModifyRegister32(dam_dat_selection_mask << + dam_receive_data_select_shift, + p_source << dam_receive_data_select_shift, + _reg_DAM_HPCR(p_config)); + } else { + ModifyRegister32(dam_dat_selection_mask << + dam_receive_data_select_shift, + p_source << dam_receive_data_select_shift, + _reg_DAM_PPCR(p_config)); + } + return; +} + +/*! + * This function controls Receive Frame Sync signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Rx Frame Sync signal direction + */ +void dam_select_RxFS_direction(dam_port port, signal_direction direction) +{ + if (port < 3) { + ModifyRegister32(1 << dam_receive_frame_sync_direction_shift, + direction << + dam_receive_frame_sync_direction_shift, + _reg_DAM_HPCR(port)); + } else { + ModifyRegister32(1 << dam_receive_frame_sync_direction_shift, + direction << + dam_receive_frame_sync_direction_shift, + _reg_DAM_PPCR(port)); + } + return; +} + +/*! + * This function controls Receive Frame Sync signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxFS the signal comes from RxFS or TxFS of + * the source port + * @param p_source the source port + */ +void dam_select_RxFS_source(dam_port p_config, + bool from_RxFS, dam_port p_source) +{ + if (p_config < 3) { + ModifyRegister32(dam_fs_selection_mask << + dam_receive_frame_sync_select_shift, + ((from_RxFS << 3) | p_source) << + dam_receive_frame_sync_select_shift, + _reg_DAM_HPCR(p_config)); + } else { + ModifyRegister32(dam_fs_selection_mask << + dam_receive_frame_sync_select_shift, + ((from_RxFS << 3) | p_source) << + dam_receive_frame_sync_select_shift, + _reg_DAM_PPCR(p_config)); + } + return; +} + +/*! + * This function controls Transmit clock signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Tx clock signal direction + */ +void dam_select_TxClk_direction(dam_port port, signal_direction direction) +{ + if (port < 3) { + ModifyRegister32(1 << dam_transmit_clock_direction_shift, + direction << + dam_transmit_clock_direction_shift, + _reg_DAM_HPCR(port)); + } else { + ModifyRegister32(1 << dam_transmit_clock_direction_shift, + direction << + dam_transmit_clock_direction_shift, + _reg_DAM_PPCR(port)); + } + return; +} + +/*! + * This function controls Transmit clock signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxClk the signal comes from RxClk or TxClk of + * the source port + * @param p_source the source port + */ +void dam_select_TxClk_source(dam_port p_config, + bool from_RxClk, dam_port p_source) +{ + if (p_config < 3) { + ModifyRegister32(dam_clk_selection_mask << + dam_transmit_clock_select_shift, + ((from_RxClk << 3) | p_source) << + dam_transmit_clock_select_shift, + _reg_DAM_HPCR(p_config)); + } else { + ModifyRegister32(dam_clk_selection_mask << + dam_transmit_clock_select_shift, + ((from_RxClk << 3) | p_source) << + dam_transmit_clock_select_shift, + _reg_DAM_PPCR(p_config)); + } + return; +} + +/*! + * This function controls Transmit Frame Sync signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Tx Frame Sync signal direction + */ +void dam_select_TxFS_direction(dam_port port, signal_direction direction) +{ + if (port < 3) { + ModifyRegister32(1 << dam_transmit_frame_sync_direction_shift, + direction << + dam_transmit_frame_sync_direction_shift, + _reg_DAM_HPCR(port)); + } else { + ModifyRegister32(1 << dam_transmit_frame_sync_direction_shift, + direction << + dam_transmit_frame_sync_direction_shift, + _reg_DAM_HPCR(port)); + } + return; +} + +/*! + * This function controls Transmit Frame Sync signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxFS the signal comes from RxFS or TxFS of + * the source port + * @param p_source the source port + */ +void dam_select_TxFS_source(dam_port p_config, + bool from_RxFS, dam_port p_source) +{ + if (p_config < 3) { + ModifyRegister32(dam_fs_selection_mask << + dam_transmit_frame_sync_select_shift, + ((from_RxFS << 3) | p_source) << + dam_transmit_frame_sync_select_shift, + _reg_DAM_HPCR(p_config)); + } else { + ModifyRegister32(dam_fs_selection_mask << + dam_transmit_frame_sync_select_shift, + ((from_RxFS << 3) | p_source) << + dam_transmit_frame_sync_select_shift, + _reg_DAM_PPCR(p_config)); + } + return; +} + +/*! + * This function sets a bit mask that selects the port from which of the RxD + * signals are to be ANDed together for internal network mode. + * Bit 6 represents RxD from Port7 and bit0 represents RxD from Port1. + * 1 excludes RxDn from ANDing. 0 includes RxDn for ANDing. + * + * @param port the DAM port to configure + * @param bit_mask the bit mask + * + * @return This function returns the result of the operation + * (0 if successful, -1 otherwise). + */ +int dam_set_internal_network_mode_mask(dam_port port, unsigned char bit_mask) +{ + int result; + result = 0; + + ModifyRegister32(dam_internal_network_mode_mask << + dam_internal_network_mode_shift, + bit_mask << dam_internal_network_mode_shift, + _reg_DAM_HPCR(port)); + return result; +} + +/*! + * This function controls whether or not the port is in synchronous mode. + * When the synchronous mode is selected, the receive and the transmit sections + * use common clock and frame sync signals. + * When the synchronous mode is not selected, separate clock and frame sync + * signals are used for the transmit and the receive sections. + * The defaut value is the synchronous mode selected. + * + * @param port the DAM port to configure + * @param synchronous the state to assign + */ +void dam_set_synchronous(dam_port port, bool synchronous) +{ + if (port < 3) { + ModifyRegister32(1 << dam_synchronous_mode_shift, + synchronous << dam_synchronous_mode_shift, + _reg_DAM_HPCR(port)); + } else { + ModifyRegister32(1 << dam_synchronous_mode_shift, + synchronous << dam_synchronous_mode_shift, + _reg_DAM_PPCR(port)); + } + return; +} + +/*! + * This function swaps the transmit and receive signals from (Da-TxD, Db-RxD) + * to (Da-RxD, Db-TxD). + * This default signal configuration is Da-TxD, Db-RxD. + * + * @param port the DAM port to configure + * @param value the switch state + */ +void dam_switch_Tx_Rx(dam_port port, bool value) +{ + if (port < 3) { + ModifyRegister32(1 << dam_transmit_receive_switch_shift, + value << dam_transmit_receive_switch_shift, + _reg_DAM_HPCR(port)); + } else { + ModifyRegister32(1 << dam_transmit_receive_switch_shift, + value << dam_transmit_receive_switch_shift, + _reg_DAM_PPCR(port)); + } + return; +} + +/*! + * This function resets the two registers of the selected port. + * + * @param port the DAM port to reset + */ +void dam_reset_register(dam_port port) +{ + if (port < 3) { + ModifyRegister32(0xFFFFFFFF, dam_hpcr_default_value, + _reg_DAM_HPCR(port)); + } else { + ModifyRegister32(0xFFFFFFFF, dam_ppcr_default_value, + _reg_DAM_PPCR(port)); + } + return; +} + +#ifdef TEST_DAM + +/*! + * This function implements IOCTL controls on a DAM device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @param cmd the command + * @param arg the parameter :\n + * DAM_CONFIG_SSI1:\n + * data from port 1 to port 4, clock and FS from port 1 (SSI1)\n + * DAM_CONFIG_SSI2:\n + * data from port 2 to port 5, clock and FS from port 2 (SSI2)\n + * DAM_CONFIG_SSI_NETWORK_MODE:\n + * network mode for mix digital with data from port 1 to port4,\n + * data from port 2 to port 4, clock and FS from port 1 (SSI1) + * + * @return This function returns 0 if successful. + */ +static int dam_ioctl(struct inode *inode, + struct file *file, unsigned int cmd, unsigned long arg) +{ + return 0; +} + +/*! + * This function implements the open method on a DAM device. + * + * @param inode pointer on the node + * @param file pointer on the file + * + * @return This function returns 0. + */ +static int dam_open(struct inode *inode, struct file *file) +{ + /* DBG_PRINTK("ssi : dam_open()\n"); */ + return 0; +} + +/*! + * This function implements the release method on a DAM device. + * + * @param inode pointer on the node + * @param file pointer on the file + * + * @return This function returns 0. + */ +static int dam_free(struct inode *inode, struct file *file) +{ + /* DBG_PRINTK("ssi : dam_free()\n"); */ + return 0; +} + +/*! + * This structure defines file operations for a DAM device. + */ +static struct file_operations dam_fops = { + + /*! + * the owner + */ + .owner = THIS_MODULE, + + /*! + * the ioctl operation + */ + .ioctl = dam_ioctl, + + /*! + * the open operation + */ + .open = dam_open, + + /*! + * the release operation + */ + .release = dam_free, +}; + +#endif + +/*! + * This function implements the init function of the DAM device. + * This function is called when the module is loaded. + * + * @return This function returns 0. + */ +static int __init dam_init(void) +{ +#ifdef TEST_DAM + struct device *temp_class; + printk(KERN_DEBUG "dam : dam_init(void) \n"); + + major_dam = register_chrdev(0, DAM_NAME, &dam_fops); + if (major_dam < 0) { + printk(KERN_WARNING "Unable to get a major for dam"); + return major_dam; + } + + mxc_dam_class = class_create(THIS_MODULE, DAM_NAME); + if (IS_ERR(mxc_dam_class)) { + goto err_out; + } + + temp_class = device_create(mxc_dam_class, NULL, + MKDEV(major_dam, 0), DAM_NAME); + if (IS_ERR(temp_class)) { + goto err_out; + } +#endif + return 0; + + err_out: + printk(KERN_ERR "Error creating dam class device.\n"); + device_destroy(mxc_dam_class, MKDEV(major_dam, 0)); + class_destroy(mxc_dam_class); + unregister_chrdev(major_dam, DAM_NAME); + return -1; +} + +/*! + * This function implements the exit function of the SPI device. + * This function is called when the module is unloaded. + * + */ +static void __exit dam_exit(void) +{ +#ifdef TEST_DAM + device_destroy(mxc_dam_class, MKDEV(major_dam, 0)); + class_destroy(mxc_dam_class); + unregister_chrdev(major_dam, DAM_NAME); + printk(KERN_DEBUG "dam : successfully unloaded\n"); +#endif +} + +module_init(dam_init); +module_exit(dam_exit); + +MODULE_DESCRIPTION("DAM char device driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/gps_ioctrl/Kconfig linux-2.6.26-lab126/drivers/mxc/gps_ioctrl/Kconfig --- linux-2.6.26/drivers/mxc/gps_ioctrl/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/gps_ioctrl/Kconfig 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,14 @@ +# +# BROADCOM GPS configuration +# + +menu "Broadcom GPS ioctrl support" + +config GPS_IOCTRL + tristate "GPS ioctrl support" + depends on MACH_MX31_3DS || MACH_MX35_3DS || MACH_MX37_3DS + default m + ---help--- + Say Y to enable Broadcom GPS ioctrl on MXC platform. + +endmenu diff -urN linux-2.6.26/drivers/mxc/gps_ioctrl/Makefile linux-2.6.26-lab126/drivers/mxc/gps_ioctrl/Makefile --- linux-2.6.26/drivers/mxc/gps_ioctrl/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/gps_ioctrl/Makefile 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,5 @@ +# +# Makefile for the GPIO device driver module. +# +obj-$(CONFIG_GPS_IOCTRL) += gps_gpiodrv.o +gps_gpiodrv-objs := agpsgpiodev.o diff -urN linux-2.6.26/drivers/mxc/gps_ioctrl/agpsgpiodev.c linux-2.6.26-lab126/drivers/mxc/gps_ioctrl/agpsgpiodev.c --- linux-2.6.26/drivers/mxc/gps_ioctrl/agpsgpiodev.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/gps_ioctrl/agpsgpiodev.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,299 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file agpsgpiodev.c + * + * @brief Main file for GPIO kernel module. Contains driver entry/exit + * + */ + +#include +#include /* Async notification */ +#include /* for get_user, put_user, access_ok */ +#include /* jiffies */ +#include +#include +#include +#include +#include "agpsgpiodev.h" + +extern void gpio_gps_active(void); +extern void gpio_gps_inactive(void); +extern int gpio_gps_access(int para); + +struct mxc_gps_platform_data *mxc_gps_ioctrl_data; +static int Device_Open; /* Only allow a single user of this device */ + +/* Write GPIO from user space */ +static int ioctl_writegpio(int arg) +{ + + /* Bit 0 of arg identifies the GPIO pin to write: + 0 = GPS_RESET_GPIO, 1 = GPS_POWER_GPIO. + Bit 1 of arg identifies the value to write (0 or 1). */ + + /* Bit 2 should be 0 to show this access is write */ + return gpio_gps_access(arg & (~0x4)); +} + +/* Read GPIO from user space */ +static int ioctl_readgpio(int arg) +{ + /* Bit 0 of arg identifies the GPIO pin to read: + 0 = GPS_RESET_GPIO. 1 = GPS_POWER_GPIO + Bit 2 should be 1 to show this access is read */ + return gpio_gps_access(arg | 0x4); +} + +static int device_open(struct inode *inode, struct file *fp) +{ + /* We don't want to talk to two processes at the same time. */ + if (Device_Open) { + printk(KERN_DEBUG "device_open() - Returning EBUSY. \ + Device already open... \n"); + return -EBUSY; + } + Device_Open++; /* BUGBUG : Not protected! */ + try_module_get(THIS_MODULE); + + return 0; +} + +static int device_release(struct inode *inode, struct file *fp) +{ + /* We're now ready for our next caller */ + Device_Open--; + module_put(THIS_MODULE); + + return 0; +} + +static int device_ioctl(struct inode *inode, struct file *fp, + unsigned int cmd, unsigned long arg) +{ + int err = 0; + + /* Extract the type and number bitfields, and don't decode wrong cmds. + Return ENOTTY (inappropriate ioctl) before access_ok() */ + if (_IOC_TYPE(cmd) != MAJOR_NUM) { + printk(KERN_ERR + "device_ioctl() - Error! IOC_TYPE = %d. Expected %d\n", + _IOC_TYPE(cmd), MAJOR_NUM); + return -ENOTTY; + } + if (_IOC_NR(cmd) > IOCTL_MAXNUMBER) { + printk(KERN_ERR + "device_ioctl() - Error!" + "IOC_NR = %d greater than max supported(%d)\n", + _IOC_NR(cmd), IOCTL_MAXNUMBER); + return -ENOTTY; + } + + /* The direction is a bitmask, and VERIFY_WRITE catches R/W transfers. + `Type' is user-oriented, while access_ok is kernel-oriented, so the + concept of "read" and "write" is reversed. I think this is primarily + for good coding practice. You can easily do any kind of R/W access + without these checks and IOCTL code can be implemented "randomly"! */ + if (_IOC_DIR(cmd) & _IOC_READ) + err = + !access_ok(VERIFY_WRITE, (void __user *)arg, + _IOC_SIZE(cmd)); + + else if (_IOC_DIR(cmd) & _IOC_WRITE) + err = + !access_ok(VERIFY_READ, (void __user *)arg, _IOC_SIZE(cmd)); + if (err) { + printk(KERN_ERR + "device_ioctl() - Error! User arg not valid" + "for selected access (R/W/RW). Cmd %d\n", + _IOC_TYPE(cmd)); + return -EFAULT; + } + + /* Note: Read and writing data to user buffer can be done using regular + pointer stuff but we may also use get_user() or put_user() */ + + /* Cmd and arg has been verified... */ + switch (cmd) { + case IOCTL_WRITEGPIO: + return ioctl_writegpio((int)arg); + case IOCTL_READGPIO: + return ioctl_readgpio((int)arg); + default: + printk(KERN_ERR "device_ioctl() - Invalid IOCTL (0x%x)\n", cmd); + return EINVAL; + } + return 0; +} + +struct file_operations Fops = { + .ioctl = device_ioctl, + .open = device_open, + .release = device_release, +}; + +/* Initialize the module - Register the character device */ +int init_chrdev(void) +{ + /* NOTE : THIS IS THE OLD-SCHOOL WAY TO REGISTER A CHAR DEVICE. + THE RECOMMENDED APPROACH IS TO USE cdev_alloc, cdev_init, cdev_add, + cdev_del. REFER TO CHAPTER 3 IN THE DEVICE DRIVER BOOK! */ + + /* Register the character device (at least try) */ + int ret_val = + register_chrdev(MAJOR_NUM, AGPSGPIO_DEVICE_FILE_NAME, &Fops); + + /* Negative values signify an error */ + if (ret_val < 0) { + printk(KERN_ERR + "init_chrdev() - Failed to register" + "char device (error %d)\n", ret_val); + return ret_val; + } + + return 0; +} + +/* Cleanup - unregister the appropriate file from /proc. */ +void cleanup_chrdev(void) +{ + /* Unregister the device + int ret = unregister_chrdev(MAJOR_NUM, AGPSGPIO_DEVICE_FILE_NAME); + change for 2.6.24 since its declarationis as below: + extern void unregister_chrdev(unsigned int, const char *); */ + unregister_chrdev(MAJOR_NUM, AGPSGPIO_DEVICE_FILE_NAME); +} + +/*! + * This function initializes the driver in terms of memory of the soundcard + * and some basic HW clock settings. + * + * @return 0 on success, -1 otherwise. + */ +static int __init gps_ioctrl_probe(struct platform_device *pdev) +{ + struct regulator *gps_regu; + + mxc_gps_ioctrl_data = + (struct mxc_gps_platform_data *)pdev->dev.platform_data; + + /* open GPS GPO3 1v8 for GL gps support */ + if (mxc_gps_ioctrl_data->core_reg != NULL) { + gps_regu = + regulator_get(&(pdev->dev), mxc_gps_ioctrl_data->core_reg); + if (!IS_ERR_VALUE((u32)gps_regu)) { + regulator_set_voltage(gps_regu, 1800000); + regulator_enable(gps_regu); + regulator_put(gps_regu, &(pdev->dev)); + } else { + return -1; + } + } + /* open GPS GPO1 2v8 for GL gps support */ + if (mxc_gps_ioctrl_data->analog_reg != NULL) { + gps_regu = + regulator_get(&(pdev->dev), + mxc_gps_ioctrl_data->analog_reg); + if (!IS_ERR_VALUE((u32)gps_regu)) { + regulator_set_voltage(gps_regu, 2800000); + regulator_enable(gps_regu); + regulator_put(gps_regu, &(pdev->dev)); + } else { + return -1; + } + } + gpio_gps_active(); + + /* Register character device */ + init_chrdev(); + return 0; +} + +static int gps_ioctrl_remove(struct platform_device *pdev) +{ + struct regulator *gps_regu; + + mxc_gps_ioctrl_data = + (struct mxc_gps_platform_data *)pdev->dev.platform_data; + + /* Character device cleanup.. */ + cleanup_chrdev(); + gpio_gps_inactive(); + + /* close GPS GPO3 1v8 for GL gps */ + if (mxc_gps_ioctrl_data->core_reg != NULL) { + gps_regu = + regulator_get(&(pdev->dev), mxc_gps_ioctrl_data->core_reg); + regulator_disable(gps_regu); + regulator_put(gps_regu, &(pdev->dev)); + } + /* close GPS GPO1 2v8 for GL gps */ + if (mxc_gps_ioctrl_data->analog_reg != NULL) { + gps_regu = + regulator_get(&(pdev->dev), + mxc_gps_ioctrl_data->analog_reg); + regulator_disable(gps_regu); + regulator_put(gps_regu, &(pdev->dev)); + } + + return 0; +} + +static int gps_ioctrl_suspend(struct platform_device *pdev, pm_message_t state) +{ + /* PowerEn toggle off */ + ioctl_writegpio(0x1); + return 0; +} + +static int gps_ioctrl_resume(struct platform_device *pdev) +{ + /* PowerEn pull up */ + ioctl_writegpio(0x3); + return 0; +} + +static struct platform_driver gps_ioctrl_driver = { + .probe = gps_ioctrl_probe, + .remove = gps_ioctrl_remove, + .suspend = gps_ioctrl_suspend, + .resume = gps_ioctrl_resume, + .driver = { + .name = "gps_ioctrl", + }, +}; + +/*! + * Entry point for GPS ioctrl module. + * + */ +static int __init gps_ioctrl_init(void) +{ + return platform_driver_register(&gps_ioctrl_driver); +} + +/*! + * unloading module. + * + */ +static void __exit gps_ioctrl_exit(void) +{ + platform_driver_unregister(&gps_ioctrl_driver); +} + +module_init(gps_ioctrl_init); +module_exit(gps_ioctrl_exit); +MODULE_DESCRIPTION("GPIO DEVICE DRIVER"); +MODULE_AUTHOR("Freescale Semiconductor"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/gps_ioctrl/agpsgpiodev.h linux-2.6.26-lab126/drivers/mxc/gps_ioctrl/agpsgpiodev.h --- linux-2.6.26/drivers/mxc/gps_ioctrl/agpsgpiodev.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/gps_ioctrl/agpsgpiodev.h 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,46 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file agpsgpiodev.h + * + * @brief head file of Simple character device interface for AGPS kernel module. + * + * @ingroup + */ + +#ifndef AGPSGPIODEV_H +#define AGPSGPIODEV_H + +#include + +#define USE_BLOCKING /* Test driver with blocking calls */ +#undef USE_FASYNC /* Test driver with async notification */ + +/* The major device number. We can't rely on dynamic registration any more + because ioctls need to know it */ +#define MAJOR_NUM 100 + +#define IOCTL_WRITEGPIO _IOWR(MAJOR_NUM, 1, char *) +#define IOCTL_READGPIO _IOR(MAJOR_NUM, 2, char *) +#define IOCTL_MAXNUMBER 2 + +/* The name of the device file */ +#define AGPSGPIO_DEVICE_FILE_NAME "agpsgpio" + +/* Exported prototypes */ +int init_chrdev(void); +void cleanup_chrdev(void); +void wakeup(void); + +#endif diff -urN linux-2.6.26/drivers/mxc/hmp4e/Kconfig linux-2.6.26-lab126/drivers/mxc/hmp4e/Kconfig --- linux-2.6.26/drivers/mxc/hmp4e/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/hmp4e/Kconfig 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,24 @@ +# +# MPEG4 Encoder kernel module configuration +# + +menu "MXC MPEG4 Encoder Kernel module support" + +config MXC_HMP4E + tristate "MPEG4 Encoder support" + depends on ARCH_MXC + depends on !ARCH_MX27 + default y + ---help--- + Say Y to get the MPEG4 Encoder kernel module available on + MXC platform. + +config MXC_HMP4E_DEBUG + bool "MXC MPEG4 Debug messages" + depends on MXC_HMP4E != n + default n + ---help--- + Say Y here if you need the Encoder driver to print debug messages. + This is an option for developers, most people should say N here. + +endmenu diff -urN linux-2.6.26/drivers/mxc/hmp4e/Makefile linux-2.6.26-lab126/drivers/mxc/hmp4e/Makefile --- linux-2.6.26/drivers/mxc/hmp4e/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/hmp4e/Makefile 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,8 @@ +# +# Makefile for the MPEG4 Encoder kernel module. + +obj-$(CONFIG_MXC_HMP4E) += mxc_hmp4e.o + +ifeq ($(CONFIG_MXC_HMP4E_DEBUG),y) +EXTRA_CFLAGS += -DDEBUG +endif diff -urN linux-2.6.26/drivers/mxc/hmp4e/mxc_hmp4e.c linux-2.6.26-lab126/drivers/mxc/hmp4e/mxc_hmp4e.c --- linux-2.6.26/drivers/mxc/hmp4e/mxc_hmp4e.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/hmp4e/mxc_hmp4e.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,811 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * Encoder device driver (kernel module) + * + * Copyright (C) 2005 Hantro Products Oy. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include +#include +#include /* __init,__exit directives */ +#include /* remap_page_range / remap_pfn_range */ +#include /* for struct file_operations */ +#include /* standard error codes */ +#include /* for device registeration for PM */ +#include /* for msleep_interruptible */ +#include +#include /* for dma_alloc_consistent */ +#include +#include /* for ioctl __get_user, __put_user */ +#include "mxc_hmp4e.h" /* MPEG4 encoder specific */ + +/* here's all the must remember stuff */ +typedef struct { + ulong buffaddr; + u32 buffsize; + ulong iobaseaddr; + u32 iosize; + volatile u32 *hwregs; + u32 irq; + u16 hwid_offset; + u16 intr_offset; + u16 busy_offset; + u16 type; /* Encoder type, CIF = 0, VGA = 1 */ + u16 clk_gate; + u16 busy_val; + struct fasync_struct *async_queue; +#ifdef CONFIG_PM + s32 suspend_state; + wait_queue_head_t power_queue; +#endif +} hmp4e_t; + +/* and this is our MAJOR; use 0 for dynamic allocation (recommended)*/ +static s32 hmp4e_major; + +static u32 hmp4e_phys; +static struct class *hmp4e_class; +static hmp4e_t hmp4e_data; + +/*! MPEG4 enc clock handle. */ +static struct clk *hmp4e_clk; + +/* + * avoid "enable_irq(x) unbalanced from ..." + * error messages from the kernel, since {ena,dis}able_irq() + * calls are stacked in kernel. + */ +static bool irq_enable = false; + +ulong base_port = MPEG4_ENC_BASE_ADDR; +u32 irq = MXC_INT_MPEG4_ENC; + +module_param(base_port, long, 000); +module_param(irq, int, 000); + +/*! + * These variables store the register values when HMP4E is in suspend mode. + */ +#ifdef CONFIG_PM +u32 io_regs[64]; +#endif + +static s32 hmp4e_map_buffer(struct file *filp, struct vm_area_struct *vma); +static s32 hmp4e_map_hwregs(struct file *filp, struct vm_area_struct *vma); +static void hmp4e_reset(hmp4e_t * dev); +irqreturn_t hmp4e_isr(s32 irq, void *dev_id); + +/*! + * This funtion is called to write h/w register. + * + * @param val value to be written into the register + * @param offset register offset + * + */ +static inline void hmp4e_write(u32 val, u32 offset) +{ + hmp4e_t *dev = &hmp4e_data; + __raw_writel(val, (dev->hwregs + offset)); +} + +/*! + * This funtion is called to read h/w register. + * + * @param offset register offset + * + * @return This function returns the value read from the register. + * + */ +static inline u32 hmp4e_read(u32 offset) +{ + hmp4e_t *dev = &hmp4e_data; + u32 val; + + val = __raw_readl(dev->hwregs + offset); + + return val; +} + +/*! + * The device's mmap method. The VFS has kindly prepared the process's + * vm_area_struct for us, so we examine this to see what was requested. + * + * @param filp pointer to struct file + * @param vma pointer to struct vma_area_struct + * + * @return This function returns 0 if successful or -ve value on error. + * + */ +static s32 hmp4e_mmap(struct file *filp, struct vm_area_struct *vma) +{ + s32 result; + ulong offset = vma->vm_pgoff << PAGE_SHIFT; + + pr_debug("hmp4e_mmap: size = %lu off = 0x%08lx\n", + (unsigned long)(vma->vm_end - vma->vm_start), offset); + + if (offset == 0) { + result = hmp4e_map_buffer(filp, vma); + } else if (offset == hmp4e_data.iobaseaddr) { + result = hmp4e_map_hwregs(filp, vma); + } else { + pr_debug("hmp4e: mmap invalid value\n"); + result = -EINVAL; + } + + return result; +} + +/*! + * This funtion is called to handle ioctls. + * + * @param inode pointer to struct inode + * @param filp pointer to struct file + * @param cmd ioctl command + * @param arg user data + * + * @return This function returns 0 if successful or -ve value on error. + * + */ +static s32 hmp4e_ioctl(struct inode *inode, struct file *filp, + u32 cmd, ulong arg) +{ + s32 err = 0, retval = 0; + ulong offset = 0; + hmp4e_t *dev = &hmp4e_data; + write_t bwrite; + +#ifdef CONFIG_PM + wait_event_interruptible(hmp4e_data.power_queue, + hmp4e_data.suspend_state == 0); +#endif + + /* + * extract the type and number bitfields, and don't decode + * wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok() + */ + if (_IOC_TYPE(cmd) != HMP4E_IOC_MAGIC) { + pr_debug("hmp4e: ioctl invalid magic\n"); + return -ENOTTY; + } + + if (_IOC_NR(cmd) > HMP4E_IOC_MAXNR) { + pr_debug("hmp4e: ioctl exceeds max ioctl\n"); + return -ENOTTY; + } + + /* + * the direction is a bitmask, and VERIFY_WRITE catches R/W + * transfers. `Type' is user-oriented, while + * access_ok is kernel-oriented, so the concept of "read" and + * "write" is reversed + */ + if (_IOC_DIR(cmd) & _IOC_READ) { + err = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd)); + } else if (_IOC_DIR(cmd) & _IOC_WRITE) { + err = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd)); + } + + if (err) { + pr_debug("hmp4e: ioctl invalid direction\n"); + return -EFAULT; + } + + switch (cmd) { + case HMP4E_IOCHARDRESET: + break; + + case HMP4E_IOCGBUFBUSADDRESS: + retval = __put_user((ulong) hmp4e_phys, (u32 *) arg); + break; + + case HMP4E_IOCGBUFSIZE: + retval = __put_user(hmp4e_data.buffsize, (u32 *) arg); + break; + + case HMP4E_IOCSREGWRITE: + if (dev->type != 1) { /* This ioctl only for VGA */ + pr_debug("hmp4e: HMP4E_IOCSREGWRITE invalid\n"); + retval = -EINVAL; + break; + } + + retval = __copy_from_user(&bwrite, (u32 *) arg, + sizeof(write_t)); + + if (bwrite.offset <= hmp4e_data.iosize - 4) { + hmp4e_write(bwrite.data, (bwrite.offset / 4)); + } else { + pr_debug("hmp4e: HMP4E_IOCSREGWRITE failed\n"); + retval = -EFAULT; + } + break; + + case HMP4E_IOCXREGREAD: + if (dev->type != 1) { /* This ioctl only for VGA */ + pr_debug("hmp4e: HMP4E_IOCSREGWRITE invalid\n"); + retval = -EINVAL; + break; + } + + retval = __get_user(offset, (ulong *) arg); + if (offset <= hmp4e_data.iosize - 4) { + __put_user(hmp4e_read((offset / 4)), (ulong *) arg); + } else { + pr_debug("hmp4e: HMP4E_IOCXREGREAD failed\n"); + retval = -EFAULT; + } + break; + + case HMP4E_IOCGHWOFFSET: + __put_user(hmp4e_data.iobaseaddr, (ulong *) arg); + break; + + case HMP4E_IOCGHWIOSIZE: + __put_user(hmp4e_data.iosize, (u32 *) arg); + break; + + case HMP4E_IOC_CLI: + if (irq_enable == true) { + disable_irq(hmp4e_data.irq); + irq_enable = false; + } + break; + + case HMP4E_IOC_STI: + if (irq_enable == false) { + enable_irq(hmp4e_data.irq); + irq_enable = true; + } + break; + + default: + pr_debug("unknown case %x\n", cmd); + } + + return retval; +} + +/*! + * This funtion is called when the device is opened. + * + * @param inode pointer to struct inode + * @param filp pointer to struct file + * + * @return This function returns 0 if successful or -ve value on error. + * + */ +static s32 hmp4e_open(struct inode *inode, struct file *filp) +{ + hmp4e_t *dev = &hmp4e_data; + + filp->private_data = (void *)dev; + + if (request_irq(dev->irq, hmp4e_isr, 0, "mxc_hmp4e", dev) != 0) { + pr_debug("hmp4e: request irq failed\n"); + return -EBUSY; + } + + if (irq_enable == false) { + irq_enable = true; + } + clk_enable(hmp4e_clk); + return 0; +} + +static s32 hmp4e_fasync(s32 fd, struct file *filp, s32 mode) +{ + hmp4e_t *dev = (hmp4e_t *) filp->private_data; + return fasync_helper(fd, filp, mode, &dev->async_queue); +} + +/*! + * This funtion is called when the device is closed. + * + * @param inode pointer to struct inode + * @param filp pointer to struct file + * + * @return This function returns 0. + * + */ +static s32 hmp4e_release(struct inode *inode, struct file *filp) +{ + hmp4e_t *dev = (hmp4e_t *) filp->private_data; + + /* this is necessary if user process exited asynchronously */ + if (irq_enable == true) { + disable_irq(dev->irq); + irq_enable = false; + } + + /* reset hardware */ + hmp4e_reset(&hmp4e_data); + + /* free the encoder IRQ */ + free_irq(dev->irq, (void *)dev); + + /* remove this filp from the asynchronusly notified filp's */ + hmp4e_fasync(-1, filp, 0); + clk_disable(hmp4e_clk); + return 0; +} + +/* VFS methods */ +static struct file_operations hmp4e_fops = { + .owner = THIS_MODULE, + .open = hmp4e_open, + .release = hmp4e_release, + .ioctl = hmp4e_ioctl, + .mmap = hmp4e_mmap, + .fasync = hmp4e_fasync, +}; + +/*! + * This funtion allocates physical contigous memory. + * + * @param size size of memory to be allocated + * + * @return This function returns 0 if successful or -ve value on error. + * + */ +static s32 hmp4e_alloc(u32 size) +{ + hmp4e_data.buffsize = PAGE_ALIGN(size); + hmp4e_data.buffaddr = + (ulong) dma_alloc_coherent(NULL, hmp4e_data.buffsize, + (dma_addr_t *) & hmp4e_phys, + GFP_DMA | GFP_KERNEL); + + if (hmp4e_data.buffaddr == 0) { + printk(KERN_ERR "hmp4e: couldn't allocate data buffer\n"); + return -ENOMEM; + } + + memset((s8 *) hmp4e_data.buffaddr, 0, hmp4e_data.buffsize); + return 0; +} + +/*! + * This funtion frees the DMAed memory. + */ +static void hmp4e_free(void) +{ + if (hmp4e_data.buffaddr != 0) { + dma_free_coherent(NULL, hmp4e_data.buffsize, + (void *)hmp4e_data.buffaddr, hmp4e_phys); + hmp4e_data.buffaddr = 0; + } +} + +/*! + * This funtion maps the shared buffer in memory. + * + * @param filp pointer to struct file + * @param vma pointer to struct vm_area_struct + * + * @return This function returns 0 if successful or -ve value on error. + * + */ +static s32 hmp4e_map_buffer(struct file *filp, struct vm_area_struct *vma) +{ + ulong phys; + ulong start = (u32) vma->vm_start; + ulong size = (u32) (vma->vm_end - vma->vm_start); + + /* if userspace tries to mmap beyond end of our buffer, fail */ + if (size > hmp4e_data.buffsize) { + pr_debug("hmp4e: hmp4e_map_buffer, invalid size\n"); + return -EINVAL; + } + + vma->vm_flags |= VM_RESERVED | VM_IO; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + phys = hmp4e_phys; + + if (remap_pfn_range(vma, start, phys >> PAGE_SHIFT, size, + vma->vm_page_prot)) { + pr_debug("hmp4e: failed mmapping shared buffer\n"); + return -EAGAIN; + } + + return 0; +} + +/*! + * This funtion maps the h/w register space in memory. + * + * @param filp pointer to struct file + * @param vma pointer to struct vm_area_struct + * + * @return This function returns 0 if successful or -ve value on error. + * + */ +static s32 hmp4e_map_hwregs(struct file *filp, struct vm_area_struct *vma) +{ + ulong phys; + ulong start = (unsigned long)vma->vm_start; + ulong size = (unsigned long)(vma->vm_end - vma->vm_start); + + /* if userspace tries to mmap beyond end of our buffer, fail */ + if (size > PAGE_SIZE) { + pr_debug("hmp4e: hmp4e_map_hwregs, invalid size\n"); + return -EINVAL; + } + + vma->vm_flags |= VM_RESERVED | VM_IO; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + /* Remember this won't work for vmalloc()d memory ! */ + phys = hmp4e_data.iobaseaddr; + + if (remap_pfn_range(vma, start, phys >> PAGE_SHIFT, hmp4e_data.iosize, + vma->vm_page_prot)) { + pr_debug("hmp4e: failed mmapping HW registers\n"); + return -EAGAIN; + } + + return 0; +} + +/*! + * This function is the interrupt service routine. + * + * @param irq the irq number + * @param dev_id driver data when ISR was regiatered + * + * @return The return value is IRQ_HANDLED. + * + */ +irqreturn_t hmp4e_isr(s32 irq, void *dev_id) +{ + hmp4e_t *dev = (hmp4e_t *) dev_id; + u32 offset = dev->intr_offset; + + u32 irq_status = hmp4e_read(offset); + + /* clear enc IRQ */ + hmp4e_write(irq_status & (~0x01), offset); + + if (dev->async_queue) + kill_fasync(&dev->async_queue, SIGIO, POLL_IN); + + return IRQ_HANDLED; +} + +/*! + * This function is called to reset the encoder. + * + * @param dev pointer to struct hmp4e_data + * + */ +static void hmp4e_reset(hmp4e_t * dev) +{ + s32 i; + + /* enable HCLK for register reset */ + hmp4e_write(dev->clk_gate, 0); + + /* Reset registers, except ECR0 (0x00) and ID (read-only) */ + for (i = 1; i < (dev->iosize / 4); i += 1) { + if (i == dev->hwid_offset) /* ID is read only */ + continue; + + /* Only for CIF, not used */ + if ((dev->type == 0) && (i == 14)) + continue; + + hmp4e_write(0, i); + } + + /* disable HCLK */ + hmp4e_write(0, 0); + return; +} + +/*! + * This function is called during the driver binding process. This function + * does the hardware initialization. + * + * @param dev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions + * + * @return The function returns 0 if successful. + */ +static s32 hmp4e_probe(struct platform_device *pdev) +{ + s32 result; + u32 hwid; + struct device *temp_class; + + hmp4e_data.iobaseaddr = base_port; + hmp4e_data.irq = irq; + hmp4e_data.buffaddr = 0; + + /* map hw i/o registers into kernel space */ + hmp4e_data.hwregs = (volatile void *)IO_ADDRESS(hmp4e_data.iobaseaddr); + + hmp4e_clk = clk_get(&pdev->dev, "mpeg4_clk"); + if (IS_ERR(hmp4e_clk)) { + printk(KERN_INFO "hmp4e: Unable to get clock\n"); + return -EIO; + } + + clk_enable(hmp4e_clk); + + /* check hw id for encoder signature */ + hwid = hmp4e_read(7); + if ((hwid & 0xffff) == 0x1882) { /* CIF first */ + hmp4e_data.type = 0; + hmp4e_data.iosize = (16 * 4); + hmp4e_data.hwid_offset = 7; + hmp4e_data.intr_offset = 5; + hmp4e_data.clk_gate = (1 << 1); + hmp4e_data.buffsize = 512000; + hmp4e_data.busy_offset = 0; + hmp4e_data.busy_val = 1; + } else { + hwid = hmp4e_read((0x88 / 4)); + if ((hwid & 0xffff0000) == 0x52510000) { /* VGA */ + hmp4e_data.type = 1; + hmp4e_data.iosize = (35 * 4); + hmp4e_data.hwid_offset = (0x88 / 4); + hmp4e_data.intr_offset = (0x10 / 4); + hmp4e_data.clk_gate = (1 << 12); + hmp4e_data.buffsize = 1048576; + hmp4e_data.busy_offset = (0x10 / 4); + hmp4e_data.busy_val = (1 << 1); + } else { + printk(KERN_INFO "hmp4e: HW ID not found\n"); + goto error1; + } + } + + /* Reset hardware */ + hmp4e_reset(&hmp4e_data); + + /* allocate memory shared with ewl */ + result = hmp4e_alloc(hmp4e_data.buffsize); + if (result < 0) + goto error1; + + result = register_chrdev(hmp4e_major, "hmp4e", &hmp4e_fops); + if (result <= 0) { + pr_debug("hmp4e: unable to get major %d\n", hmp4e_major); + goto error2; + } + + hmp4e_major = result; + + hmp4e_class = class_create(THIS_MODULE, "hmp4e"); + if (IS_ERR(hmp4e_class)) { + pr_debug("Error creating hmp4e class.\n"); + goto error3; + } + + temp_class = device_create(hmp4e_class, NULL, MKDEV(hmp4e_major, 0), + "hmp4e"); + if (IS_ERR(temp_class)) { + pr_debug("Error creating hmp4e class device.\n"); + goto error4; + } + + platform_set_drvdata(pdev, &hmp4e_data); + +#ifdef CONFIG_PM + hmp4e_data.async_queue = NULL; + hmp4e_data.suspend_state = 0; + init_waitqueue_head(&hmp4e_data.power_queue); +#endif + + printk(KERN_INFO "hmp4e: %s encoder initialized\n", + hmp4e_data.type ? "VGA" : "CIF"); + clk_disable(hmp4e_clk); + return 0; + + error4: + class_destroy(hmp4e_class); + error3: + unregister_chrdev(hmp4e_major, "hmp4e"); + error2: + hmp4e_free(); + error1: + clk_disable(hmp4e_clk); + clk_put(hmp4e_clk); + printk(KERN_INFO "hmp4e: module not inserted\n"); + return -EIO; +} + +/*! + * Dissociates the driver. + * + * @param dev the device structure + * + * @return The function always returns 0. + */ +static s32 hmp4e_remove(struct platform_device *pdev) +{ + device_destroy(hmp4e_class, MKDEV(hmp4e_major, 0)); + class_destroy(hmp4e_class); + unregister_chrdev(hmp4e_major, "hmp4e"); + hmp4e_free(); + clk_disable(hmp4e_clk); + clk_put(hmp4e_clk); + platform_set_drvdata(pdev, NULL); + return 0; +} + +#ifdef CONFIG_PM +/*! + * This is the suspend of power management for the Hantro MPEG4 module + * + * @param dev the device + * @param state the state + * + * @return This function always returns 0. + */ +static s32 hmp4e_suspend(struct platform_device *pdev, pm_message_t state) +{ + s32 i; + hmp4e_t *pdata = &hmp4e_data; + + /* + * how many times msleep_interruptible will be called before + * giving up + */ + s32 timeout = 10; + + pr_debug("hmp4e: Suspend\n"); + hmp4e_data.suspend_state = 1; + + /* check if encoder is currently running */ + while ((hmp4e_read(pdata->busy_offset) & (pdata->busy_val)) && + --timeout) { + pr_debug("hmp4e: encoder is running, going to sleep\n"); + msleep_interruptible((unsigned int)30); + } + + if (!timeout) { + pr_debug("hmp4e: timeout suspending, resetting encoder\n"); + hmp4e_write(hmp4e_read(pdata->busy_offset) & + (~pdata->busy_val), pdata->busy_offset); + } + + /* first read register 0 */ + io_regs[0] = hmp4e_read(0); + + /* then override HCLK to make sure other registers can be read */ + hmp4e_write(pdata->clk_gate, 0); + + /* read other registers */ + for (i = 1; i < (pdata->iosize / 4); i += 1) { + + /* Only for CIF, not used */ + if ((pdata->type == 0) && (i == 14)) + continue; + + io_regs[i] = hmp4e_read(i); + } + + /* restore value of register 0 */ + hmp4e_write(io_regs[0], 0); + + /* stop HCLK */ + hmp4e_write(0, 0); + clk_disable(hmp4e_clk); + return 0; +}; + +/*! + * This is the resume of power management for the Hantro MPEG4 module + * It suports RESTORE state. + * + * @param pdev the platform device + * + * @return This function always returns 0 + */ +static s32 hmp4e_resume(struct platform_device *pdev) +{ + s32 i; + u32 status; + hmp4e_t *pdata = &hmp4e_data; + + pr_debug("hmp4e: Resume\n"); + clk_enable(hmp4e_clk); + + /* override HCLK to make sure registers can be written */ + hmp4e_write(pdata->clk_gate, 0x00); + + for (i = 1; i < (pdata->iosize / 4); i += 1) { + if (i == pdata->hwid_offset) /* Read only */ + continue; + + /* Only for CIF, not used */ + if ((pdata->type == 0) && (i == 14)) + continue; + + hmp4e_write(io_regs[i], i); + } + + /* write register 0 last */ + hmp4e_write(io_regs[0], 0x00); + + /* Clear the suspend flag */ + hmp4e_data.suspend_state = 0; + + /* Unblock the wait queue */ + wake_up_interruptible(&hmp4e_data.power_queue); + + /* Continue operations */ + status = hmp4e_read(pdata->intr_offset); + if (status & 0x1) { + hmp4e_write(status & (~0x01), pdata->intr_offset); + if (hmp4e_data.async_queue) + kill_fasync(&hmp4e_data.async_queue, SIGIO, POLL_IN); + } + + return 0; +}; + +#endif + +static struct platform_driver hmp4e_driver = { + .driver = { + .name = "mxc_hmp4e", + }, + .probe = hmp4e_probe, + .remove = hmp4e_remove, +#ifdef CONFIG_PM + .suspend = hmp4e_suspend, + .resume = hmp4e_resume, +#endif +}; + +static s32 __init hmp4e_init(void) +{ + printk(KERN_INFO "hmp4e: init\n"); + platform_driver_register(&hmp4e_driver); + return 0; +} + +static void __exit hmp4e_cleanup(void) +{ + platform_driver_unregister(&hmp4e_driver); + printk(KERN_INFO "hmp4e: module removed\n"); +} + +module_init(hmp4e_init); +module_exit(hmp4e_cleanup); + +/* module description */ +MODULE_AUTHOR("Hantro Products Oy"); +MODULE_DESCRIPTION("Device driver for Hantro's hardware based MPEG4 encoder"); +MODULE_SUPPORTED_DEVICE("5251/4251 MPEG4 Encoder"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/hmp4e/mxc_hmp4e.h linux-2.6.26-lab126/drivers/mxc/hmp4e/mxc_hmp4e.h --- linux-2.6.26/drivers/mxc/hmp4e/mxc_hmp4e.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/hmp4e/mxc_hmp4e.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,70 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * Encoder device driver (kernel module headers) + * + * Copyright (C) 2005 Hantro Products Oy. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ +#ifndef _HMP4ENC_H_ +#define _HMP4ENC_H_ +#include /* needed for the _IOW etc stuff used later */ + +/* this is for writing data through ioctl to registers*/ +typedef struct { + unsigned long data; + unsigned long offset; +} write_t; + +/* + * Ioctl definitions + */ + +/* Use 'k' as magic number */ +#define HMP4E_IOC_MAGIC 'k' +/* + * S means "Set" through a ptr, + * T means "Tell" directly with the argument value + * G means "Get": reply by setting through a pointer + * Q means "Query": response is on the return value + * X means "eXchange": G and S atomically + * H means "sHift": T and Q atomically + */ +#define HMP4E_IOCGBUFBUSADDRESS _IOR(HMP4E_IOC_MAGIC, 1, unsigned long *) +#define HMP4E_IOCGBUFSIZE _IOR(HMP4E_IOC_MAGIC, 2, unsigned int *) +#define HMP4E_IOCGHWOFFSET _IOR(HMP4E_IOC_MAGIC, 3, unsigned long *) +#define HMP4E_IOCGHWIOSIZE _IOR(HMP4E_IOC_MAGIC, 4, unsigned int *) +#define HMP4E_IOC_CLI _IO(HMP4E_IOC_MAGIC, 5) +#define HMP4E_IOC_STI _IO(HMP4E_IOC_MAGIC, 6) +#define HMP4E_IOCHARDRESET _IO(HMP4E_IOC_MAGIC, 7) +#define HMP4E_IOCSREGWRITE _IOW(HMP4E_IOC_MAGIC, 8, write_t) +#define HMP4E_IOCXREGREAD _IOWR(HMP4E_IOC_MAGIC, 9, unsigned long) + +#define HMP4E_IOC_MAXNR 9 + +#endif /* !_HMP4ENC_H_ */ diff -urN linux-2.6.26/drivers/mxc/hw_event/Kconfig linux-2.6.26-lab126/drivers/mxc/hw_event/Kconfig --- linux-2.6.26/drivers/mxc/hw_event/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/hw_event/Kconfig 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,11 @@ +menu "MXC HARDWARE EVENT" + +config MXC_HWEVENT + bool "MXC Hardware Event Handler" + default y + depends on ARCH_MXC + help + If you plan to use the Hardware Event Handler in the MXC, say + Y here. If unsure, select Y. + +endmenu diff -urN linux-2.6.26/drivers/mxc/hw_event/Makefile linux-2.6.26-lab126/drivers/mxc/hw_event/Makefile --- linux-2.6.26/drivers/mxc/hw_event/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/hw_event/Makefile 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1 @@ +obj-$(CONFIG_MXC_HWEVENT) += mxc_hw_event.o diff -urN linux-2.6.26/drivers/mxc/hw_event/mxc_hw_event.c linux-2.6.26-lab126/drivers/mxc/hw_event/mxc_hw_event.c --- linux-2.6.26/drivers/mxc/hw_event/mxc_hw_event.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/hw_event/mxc_hw_event.c 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,265 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * mxc_hw_event.c + * Collect the hardware events, send to user by netlink + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define EVENT_POOL_SIZE 10 + +struct hw_event_elem { + struct mxc_hw_event event; + struct list_head list; +}; + +static struct sock *nl_event_sock; /* netlink socket */ +static struct list_head event_head; +static struct list_head free_head; +static struct hw_event_elem events_pool[EVENT_POOL_SIZE]; /* event pool */ +static DEFINE_SPINLOCK(list_lock); +static DECLARE_WAIT_QUEUE_HEAD(event_wq); +static unsigned int seq; /* send seq */ +static int initialized; +static struct task_struct *hwevent_kthread; + +/*! + * main HW event handler thread + */ +static int hw_event_thread(void *data) +{ + struct sk_buff *skb = NULL; + struct nlmsghdr *nlh = NULL; + unsigned int size; + struct hw_event_elem *event, *n; + LIST_HEAD(tmp_head); + DEFINE_WAIT(wait); + + while (1) { + + prepare_to_wait(&event_wq, &wait, TASK_INTERRUPTIBLE); + /* wait for event coming */ + if (!freezing(current) && !kthread_should_stop() && + list_empty(&event_head)) + schedule(); + finish_wait(&event_wq, &wait); + + try_to_freeze(); + + if (kthread_should_stop()) + break; + + /* fetch event from list */ + spin_lock_irq(&list_lock); + tmp_head = event_head; + tmp_head.prev->next = &tmp_head; + tmp_head.next->prev = &tmp_head; + /* clear the event list head */ + INIT_LIST_HEAD(&event_head); + spin_unlock_irq(&list_lock); + + list_for_each_entry_safe(event, n, &tmp_head, list) { + + size = NLMSG_SPACE(sizeof(struct mxc_hw_event)); + skb = alloc_skb(size, GFP_KERNEL); + if (!skb) { + /* if failed alloc skb, we drop this event */ + printk(KERN_WARNING + "mxc_hw_event: skb_alloc() failed\n"); + goto alloc_failure; + } + + /* put the netlink header struct to skb */ + nlh = + NLMSG_PUT(skb, 0, seq++, NLMSG_DONE, + size - sizeof(*nlh)); + + /* fill the netlink data */ + memcpy((struct mxc_hw_event *)NLMSG_DATA(nlh), + &event->event, sizeof(struct mxc_hw_event)); + + /* free the event node, set to unused */ + spin_lock_irq(&list_lock); + list_move(&event->list, &free_head); + spin_unlock_irq(&list_lock); + + /* send to all process that create this socket */ + NETLINK_CB(skb).pid = 0; /* sender pid */ + NETLINK_CB(skb).dst_group = HW_EVENT_GROUP; + /* broadcast the event */ + netlink_broadcast(nl_event_sock, skb, 0, HW_EVENT_GROUP, + GFP_KERNEL); + + continue; + nlmsg_failure: + printk(KERN_WARNING + "mxc_hw_event: No tailroom for NLMSG in skb\n"); + alloc_failure: + /* free the event node, set to unused */ + spin_lock_irq(&list_lock); + list_del(&event->list); + list_add_tail(&event->list, &free_head); + spin_unlock_irq(&list_lock); + } + } + + return 0; +} + +/*! + * + * @priority the event priority, REALTIME, EMERENCY, NORMAL + * @new_event event id to be send + */ +int hw_event_send(int priority, struct mxc_hw_event *new_event) +{ + unsigned int size; + struct sk_buff *skb = NULL; + struct nlmsghdr *nlh = NULL; + struct mxc_hw_event *event; + struct hw_event_elem *event_elem; + int ret; + unsigned long flag; + struct list_head *list_node; + + if (!initialized) { + pr_info("HW Event module has not been initialized\n"); + return -1; + } + + if (priority == HWE_HIGH_PRIORITY) { + /** + * the most high priority event, + * we send it immediatly. + */ + + size = NLMSG_SPACE(sizeof(struct mxc_hw_event)); + + /* alloc skb */ + if (in_interrupt()) { + skb = alloc_skb(size, GFP_ATOMIC); + } else { + skb = alloc_skb(size, GFP_KERNEL); + } + if (!skb) { + /* if failed alloc skb, we drop this event */ + printk(KERN_WARNING + "hw_event send: skb_alloc() failed\n"); + goto send_later; + } + + /* put the netlink header struct to skb */ + nlh = NLMSG_PUT(skb, 0, seq++, NLMSG_DONE, size - sizeof(*nlh)); + + /* fill the netlink data */ + event = (struct mxc_hw_event *)NLMSG_DATA(nlh); + memcpy(event, new_event, sizeof(struct mxc_hw_event)); + + /* send to all process that create this socket */ + NETLINK_CB(skb).pid = 0; /* sender pid */ + NETLINK_CB(skb).dst_group = HW_EVENT_GROUP; + /* broadcast the event */ + ret = netlink_broadcast(nl_event_sock, skb, 0, HW_EVENT_GROUP, + in_interrupt()? GFP_ATOMIC : + GFP_KERNEL); + if (ret) { + + nlmsg_failure: + /* send failed */ + kfree_skb(skb); + goto send_later; + } + + return 0; + } + + send_later: + spin_lock_irqsave(&list_lock, flag); + if (list_empty(&free_head)) { + spin_unlock_irqrestore(&list_lock, flag); + /* no more free event node */ + printk(KERN_WARNING "mxc_event send: no more free node\n"); + return -1; + } + + /* get a free node from free list, and added to event list */ + list_node = free_head.next; + /* fill event */ + event_elem = list_entry(list_node, struct hw_event_elem, list); + event_elem->event = *new_event; + list_move(list_node, &event_head); + spin_unlock_irqrestore(&list_lock, flag); + + wake_up(&event_wq); + + return 0; +} + +static int __init mxc_hw_event_init(void) +{ + int i; + + /* initial the list head for event and free */ + INIT_LIST_HEAD(&free_head); + INIT_LIST_HEAD(&event_head); + + /* initial the free list */ + for (i = 0; i < EVENT_POOL_SIZE; i++) + list_add_tail(&events_pool[i].list, &free_head); + + /* create netlink kernel sock */ + nl_event_sock = + netlink_kernel_create(&init_net, NETLINK_USERSOCK, 0, NULL, NULL, + THIS_MODULE); + if (!nl_event_sock) { + printk(KERN_WARNING + "mxc_hw_event: Fail to create netlink socket.\n"); + return 1; + } + + hwevent_kthread = kthread_run(hw_event_thread, NULL, "hwevent"); + if (IS_ERR(hwevent_kthread)) { + printk(KERN_WARNING + "mxc_hw_event: Fail to create hwevent thread.\n"); + return 1; + } + + initialized = 1; + + return 0; +} + +static void __exit mxc_hw_event_exit(void) +{ + kthread_stop(hwevent_kthread); + /* wait for thread completion */ + sock_release(nl_event_sock->sk_socket); +} + +module_init(mxc_hw_event_init); +module_exit(mxc_hw_event_exit); + +EXPORT_SYMBOL(hw_event_send); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/ipu/Kconfig linux-2.6.26-lab126/drivers/mxc/ipu/Kconfig --- linux-2.6.26/drivers/mxc/ipu/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu/Kconfig 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,5 @@ +config MXC_IPU_V1 + bool + +source "drivers/mxc/ipu/pf/Kconfig" + diff -urN linux-2.6.26/drivers/mxc/ipu/Makefile linux-2.6.26-lab126/drivers/mxc/ipu/Makefile --- linux-2.6.26/drivers/mxc/ipu/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu/Makefile 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,9 @@ +obj-$(CONFIG_MXC_IPU_V1) = mxc_ipu.o + +mxc_ipu-objs := ipu_common.o ipu_sdc.o ipu_adc.o ipu_ic.o ipu_csi.o ipu_device.o + +ifdef CONFIG_MACH_LUIGI_LAB126 +mxc_ipu-objs += ipu_l126_detect.o +endif + +obj-$(CONFIG_MXC_IPU_PF) += pf/ diff -urN linux-2.6.26/drivers/mxc/ipu/ipu_adc.c linux-2.6.26-lab126/drivers/mxc/ipu/ipu_adc.c --- linux-2.6.26/drivers/mxc/ipu/ipu_adc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu/ipu_adc.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,694 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * @file ipu_adc.c + * + * @brief IPU ADC functions + * + * @ingroup IPU + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "ipu_prv.h" +#include +#include "ipu_param_mem.h" + +/*#define ADC_CHAN1_SA_MASK 0xFF800000 */ + +static void _ipu_set_cmd_data_mappings(display_port_t disp, + uint32_t pixel_fmt, int ifc_width); + +int32_t _ipu_adc_init_channel(ipu_channel_t chan, display_port_t disp, + mcu_mode_t cmd, int16_t x_pos, int16_t y_pos) +{ + uint32_t reg; + uint32_t start_addr, stride; + unsigned long lock_flags; + uint32_t size; + + size = 0; + + switch (disp) { + case DISP0: + reg = __raw_readl(ADC_DISP0_CONF); + stride = reg & ADC_DISP_CONF_SL_MASK; + break; + case DISP1: + reg = __raw_readl(ADC_DISP1_CONF); + stride = reg & ADC_DISP_CONF_SL_MASK; + break; + case DISP2: + reg = __raw_readl(ADC_DISP2_CONF); + stride = reg & ADC_DISP_CONF_SL_MASK; + break; + default: + return -EINVAL; + } + + if (stride == 0) + return -EINVAL; + + stride++; + start_addr = (y_pos * stride) + x_pos; + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + reg = __raw_readl(ADC_CONF); + + switch (chan) { + case ADC_SYS1: + reg &= ~0x00FF4000; + reg |= + ((uint32_t) size << 21 | (uint32_t) disp << 19 | (uint32_t) + cmd << 16); + + __raw_writel(start_addr, ADC_SYSCHA1_SA); + break; + + case ADC_SYS2: + reg &= ~0xFF008000; + reg |= + ((uint32_t) size << 29 | (uint32_t) disp << 27 | (uint32_t) + cmd << 24); + + __raw_writel(start_addr, ADC_SYSCHA2_SA); + break; + + case CSI_PRP_VF_ADC: + case MEM_PRP_VF_ADC: + reg &= ~0x000000F9; + reg |= + ((uint32_t) size << 5 | (uint32_t) disp << 3 | + ADC_CONF_PRP_EN); + + __raw_writel(start_addr, ADC_PRPCHAN_SA); + break; + + case MEM_PP_ADC: + reg &= ~0x00003F02; + reg |= + ((uint32_t) size << 10 | (uint32_t) disp << 8 | + ADC_CONF_PP_EN); + + __raw_writel(start_addr, ADC_PPCHAN_SA); + break; + default: + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + return -1; + break; + } + __raw_writel(reg, ADC_CONF); + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + return 0; +} + +int32_t _ipu_adc_uninit_channel(ipu_channel_t chan) +{ + uint32_t reg; + unsigned long lock_flags; + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + reg = __raw_readl(ADC_CONF); + + switch (chan) { + case ADC_SYS1: + reg &= ~0x00FF4000; + break; + case ADC_SYS2: + reg &= ~0xFF008000; + break; + case CSI_PRP_VF_ADC: + case MEM_PRP_VF_ADC: + reg &= ~0x000000F9; + break; + case MEM_PP_ADC: + reg &= ~0x00003F02; + break; + default: + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + return -1; + break; + } + __raw_writel(reg, ADC_CONF); + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + return 0; +} + +int32_t ipu_adc_write_template(display_port_t disp, uint32_t * pCmd, bool write) +{ + uint32_t ima_addr = 0; + uint32_t row_nu; + int i; + + /* Set IPU_IMA_ADDR (IPU Internal Memory Access Address) */ + /* MEM_NU = 0x0001 (CPM) */ + /* ROW_NU = 2*N ( N is channel number) */ + /* WORD_NU = 0 */ + if (write) { + row_nu = (uint32_t) disp *2 * ATM_ADDR_RANGE; + } else { + row_nu = ((uint32_t) disp * 2 + 1) * ATM_ADDR_RANGE; + } + + /* form template addr for IPU_IMA_ADDR */ + ima_addr = (0x3 << 16 /*Template memory */ | row_nu << 3); + + __raw_writel(ima_addr, IPU_IMA_ADDR); + + /* write template data for IPU_IMA_DATA */ + for (i = 0; i < TEMPLATE_BUF_SIZE; i++) + /* only DATA field are needed */ + __raw_writel(pCmd[i], IPU_IMA_DATA); + + return 0; +} + +int32_t +ipu_adc_write_cmd(display_port_t disp, cmddata_t type, + uint32_t cmd, const uint32_t * params, uint16_t numParams) +{ +#ifndef CONFIG_MACH_LUIGI_LAB126 + uint16_t i; + int disable_di = 0; + u32 reg; + unsigned long lock_flags; + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + reg = __raw_readl(IPU_CONF); + if ((reg & IPU_CONF_DI_EN) == 0) { + disable_di = 1; + reg |= IPU_CONF_DI_EN; + __raw_writel(reg, IPU_CONF); + } + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); +#endif + + __raw_writel((uint32_t) ((type ? 0x0 : 0x1) | disp << 1 | 0x10), + DI_DISP_LLA_CONF); + __raw_writel(cmd, DI_DISP_LLA_DATA); + +#ifndef CONFIG_MACH_LUIGI_LAB126 + udelay(3); + + __raw_writel((uint32_t) (0x10 | disp << 1 | 0x11), DI_DISP_LLA_CONF); + for (i = 0; i < numParams; i++) { + __raw_writel(params[i], DI_DISP_LLA_DATA); + udelay(3); + } + + if (disable_di) { + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + reg = __raw_readl(IPU_CONF); + reg &= ~IPU_CONF_DI_EN; + __raw_writel(reg, IPU_CONF); + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + } +#endif + + return 0; +} + +#ifdef CONFIG_MACH_LUIGI_LAB126 +int32_t ipu_adc_read_data(display_port_t disp) +{ + __raw_writel((uint32_t) (disp << 1 | 0x11), DI_DISP_LLA_CONF); + return (uint32_t) __raw_readl(DI_DISP_LLA_DATA); +} +#endif + +int32_t ipu_adc_set_update_mode(ipu_channel_t channel, + ipu_adc_update_mode_t mode, + uint32_t refresh_rate, unsigned long addr, + uint32_t * size) +{ + int32_t err = 0; + uint32_t ref_per, reg, src = 0; + unsigned long lock_flags; + uint32_t ipu_freq; + + ipu_freq = clk_get_rate(g_ipu_clk); + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(IPU_FS_DISP_FLOW); + reg &= ~FS_AUTO_REF_PER_MASK; + switch (mode) { + case IPU_ADC_REFRESH_NONE: + src = 0; + break; + case IPU_ADC_AUTO_REFRESH: + if (refresh_rate == 0) { + err = -EINVAL; + goto err0; + } + ref_per = ipu_freq / ((1UL << 17) * refresh_rate); + ref_per--; + reg |= ref_per << FS_AUTO_REF_PER_OFFSET; + + src = FS_SRC_AUTOREF; + break; + case IPU_ADC_AUTO_REFRESH_SNOOP: + if (refresh_rate == 0) { + err = -EINVAL; + goto err0; + } + ref_per = ipu_freq / ((1UL << 17) * refresh_rate); + ref_per--; + reg |= ref_per << FS_AUTO_REF_PER_OFFSET; + + src = FS_SRC_AUTOREF_SNOOP; + break; + case IPU_ADC_SNOOPING: + src = FS_SRC_SNOOP; + break; + } + + switch (channel) { + case ADC_SYS1: + reg &= ~FS_ADC1_SRC_SEL_MASK; + reg |= src << FS_ADC1_SRC_SEL_OFFSET; + break; + case ADC_SYS2: + reg &= ~FS_ADC2_SRC_SEL_MASK; + reg |= src << FS_ADC2_SRC_SEL_OFFSET; + break; + default: + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + return -EINVAL; + } + __raw_writel(reg, IPU_FS_DISP_FLOW); + + /* Setup bus snooping */ + if ((mode == IPU_ADC_AUTO_REFRESH_SNOOP) || (mode == IPU_ADC_SNOOPING)) { + err = mxc_snoop_set_config(0, addr, *size); + if (err > 0) { + *size = err; + err = 0; + } + } else { + mxc_snoop_set_config(0, 0, 0); + } + + err0: + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + return err; +} + +int32_t ipu_adc_get_snooping_status(uint32_t * statl, uint32_t * stath) +{ + return mxc_snoop_get_status(0, statl, stath); +} + +int32_t ipu_adc_init_panel(display_port_t disp, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint32_t stride, + ipu_adc_sig_cfg_t sig, + display_addressing_t addr, + uint32_t vsync_width, vsync_t mode) +{ + uint32_t temp; + unsigned long lock_flags; + uint32_t ser_conf; + uint32_t disp_conf; + uint32_t adc_disp_conf; + uint32_t adc_disp_vsync; + uint32_t old_pol; + + if ((disp != DISP1) && (disp != DISP2) && + (sig.ifc_mode >= IPU_ADC_IFC_MODE_3WIRE_SERIAL)) { + return -EINVAL; + } +/* adc_disp_conf = ((uint32_t)((((size == 3)||(size == 2))?1:0)<<14) | */ +/* (uint32_t)addr<<12 | (stride-1)); */ + adc_disp_conf = (uint32_t) addr << 12 | (stride - 1); + + _ipu_set_cmd_data_mappings(disp, pixel_fmt, sig.ifc_width); + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + disp_conf = __raw_readl(DI_DISP_IF_CONF); + old_pol = __raw_readl(DI_DISP_SIG_POL); + adc_disp_vsync = __raw_readl(ADC_DISP_VSYNC); + + switch (disp) { + case DISP0: + __raw_writel(adc_disp_conf, ADC_DISP0_CONF); + __raw_writel((((height - 1) << 16) | (width - 1)), + ADC_DISP0_SS); + + adc_disp_vsync &= ~(ADC_DISP_VSYNC_D0_MODE_MASK | + ADC_DISP_VSYNC_D0_WIDTH_MASK); + adc_disp_vsync |= (vsync_width << 16) | (uint32_t) mode; + + old_pol &= ~0x2000003FL; + old_pol |= sig.data_pol | sig.cs_pol << 1 | + sig.addr_pol << 2 | sig.read_pol << 3 | + sig.write_pol << 4 | sig.Vsync_pol << 5 | + sig.burst_pol << 29; + __raw_writel(old_pol, DI_DISP_SIG_POL); + + disp_conf &= ~0x0000001FL; + disp_conf |= (sig.burst_mode << 3) | (sig.ifc_mode << 1) | + DI_CONF_DISP0_EN; + __raw_writel(disp_conf, DI_DISP_IF_CONF); + break; + case DISP1: + __raw_writel(adc_disp_conf, ADC_DISP1_CONF); + __raw_writel((((height - 1) << 16) | (width - 1)), + ADC_DISP12_SS); + + adc_disp_vsync &= ~(ADC_DISP_VSYNC_D12_MODE_MASK | + ADC_DISP_VSYNC_D12_WIDTH_MASK); + adc_disp_vsync |= (vsync_width << 16) | (uint32_t) mode; + + old_pol &= ~0x4000FF00L; + old_pol |= (sig.Vsync_pol << 6 | sig.data_pol << 8 | + sig.cs_pol << 9 | sig.addr_pol << 10 | + sig.read_pol << 11 | sig.write_pol << 12 | + sig.clk_pol << 14 | sig.burst_pol << 30); + __raw_writel(old_pol, DI_DISP_SIG_POL); + + disp_conf &= ~0x00003F00L; + if (sig.ifc_mode >= IPU_ADC_IFC_MODE_3WIRE_SERIAL) { + ser_conf = (sig.ifc_width - 1) << + DI_SER_DISPx_CONF_SER_BIT_NUM_OFFSET; + if (sig.ser_preamble_len) { + ser_conf |= DI_SER_DISPx_CONF_PREAMBLE_EN; + ser_conf |= sig.ser_preamble << + DI_SER_DISPx_CONF_PREAMBLE_OFFSET; + ser_conf |= (sig.ser_preamble_len - 1) << + DI_SER_DISPx_CONF_PREAMBLE_LEN_OFFSET; + } + + ser_conf |= + sig.ser_rw_mode << DI_SER_DISPx_CONF_RW_CFG_OFFSET; + + if (sig.burst_mode == IPU_ADC_BURST_SERIAL) + ser_conf |= DI_SER_DISPx_CONF_BURST_MODE_EN; + __raw_writel(ser_conf, DI_SER_DISP1_CONF); + } else { /* parallel interface */ + disp_conf |= (uint32_t) (sig.burst_mode << 12); + } + disp_conf |= (sig.ifc_mode << 9) | DI_CONF_DISP1_EN; + __raw_writel(disp_conf, DI_DISP_IF_CONF); + break; + case DISP2: + __raw_writel(adc_disp_conf, ADC_DISP2_CONF); + __raw_writel((((height - 1) << 16) | (width - 1)), + ADC_DISP12_SS); + + adc_disp_vsync &= ~(ADC_DISP_VSYNC_D12_MODE_MASK | + ADC_DISP_VSYNC_D12_WIDTH_MASK); + adc_disp_vsync |= (vsync_width << 16) | (uint32_t) mode; + + old_pol &= ~0x80FF0000L; + temp = (uint32_t) (sig.data_pol << 16 | sig.cs_pol << 17 | + sig.addr_pol << 18 | sig.read_pol << 19 | + sig.write_pol << 20 | sig.Vsync_pol << 6 | + sig.burst_pol << 31 | sig.clk_pol << 22); + __raw_writel(temp | old_pol, DI_DISP_SIG_POL); + + disp_conf &= ~0x003F0000L; + if (sig.ifc_mode >= IPU_ADC_IFC_MODE_3WIRE_SERIAL) { + ser_conf = (sig.ifc_width - 1) << + DI_SER_DISPx_CONF_SER_BIT_NUM_OFFSET; + if (sig.ser_preamble_len) { + ser_conf |= DI_SER_DISPx_CONF_PREAMBLE_EN; + ser_conf |= sig.ser_preamble << + DI_SER_DISPx_CONF_PREAMBLE_OFFSET; + ser_conf |= (sig.ser_preamble_len - 1) << + DI_SER_DISPx_CONF_PREAMBLE_LEN_OFFSET; + + } + + ser_conf |= + sig.ser_rw_mode << DI_SER_DISPx_CONF_RW_CFG_OFFSET; + + if (sig.burst_mode == IPU_ADC_BURST_SERIAL) + ser_conf |= DI_SER_DISPx_CONF_BURST_MODE_EN; + __raw_writel(ser_conf, DI_SER_DISP2_CONF); + } else { /* parallel interface */ + disp_conf |= (uint32_t) (sig.burst_mode << 20); + } + disp_conf |= (sig.ifc_mode << 17) | DI_CONF_DISP2_EN; + __raw_writel(disp_conf, DI_DISP_IF_CONF); + break; + default: + break; + } + + __raw_writel(adc_disp_vsync, ADC_DISP_VSYNC); + + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} + +int32_t ipu_adc_init_ifc_timing(display_port_t disp, bool read, + uint32_t cycle_time, + uint32_t up_time, + uint32_t down_time, + uint32_t read_latch_time, uint32_t pixel_clk) +{ + uint32_t reg; + uint32_t time_conf3 = 0; + uint32_t clk_per; + uint32_t up_per; + uint32_t down_per; + uint32_t read_per; + uint32_t pixclk_per = 0; + uint32_t ipu_freq; + + ipu_freq = clk_get_rate(g_ipu_clk); + + clk_per = (cycle_time * (ipu_freq / 1000L) * 16L) / 1000000L; + up_per = (up_time * (ipu_freq / 1000L) * 4L) / 1000000L; + down_per = (down_time * (ipu_freq / 1000L) * 4L) / 1000000L; + + reg = (clk_per << DISPx_IF_CLK_PER_OFFSET) | + (up_per << DISPx_IF_CLK_UP_OFFSET) | + (down_per << DISPx_IF_CLK_DOWN_OFFSET); + + if (read) { + read_per = + (read_latch_time * (ipu_freq / 1000L) * 4L) / 1000000L; + if (pixel_clk) + pixclk_per = (ipu_freq * 16L) / pixel_clk; + time_conf3 = (read_per << DISPx_IF_CLK_READ_EN_OFFSET) | + (pixclk_per << DISPx_PIX_CLK_PER_OFFSET); + } + + dev_dbg(g_ipu_dev, "DI_DISPx_TIME_CONF_1/2 = 0x%08X\n", reg); + dev_dbg(g_ipu_dev, "DI_DISPx_TIME_CONF_3 = 0x%08X\n", time_conf3); + + switch (disp) { + case DISP0: + if (read) { + __raw_writel(reg, DI_DISP0_TIME_CONF_2); + __raw_writel(time_conf3, DI_DISP0_TIME_CONF_3); + } else { + __raw_writel(reg, DI_DISP0_TIME_CONF_1); + } + break; + case DISP1: + if (read) { + __raw_writel(reg, DI_DISP1_TIME_CONF_2); + __raw_writel(time_conf3, DI_DISP1_TIME_CONF_3); + } else { + __raw_writel(reg, DI_DISP1_TIME_CONF_1); + } + break; + case DISP2: + if (read) { + __raw_writel(reg, DI_DISP2_TIME_CONF_2); + __raw_writel(time_conf3, DI_DISP2_TIME_CONF_3); + } else { + __raw_writel(reg, DI_DISP2_TIME_CONF_1); + } + break; + default: + return -EINVAL; + break; + } + + return 0; +} + +struct ipu_adc_di_map { + uint32_t map_byte1; + uint32_t map_byte2; + uint32_t map_byte3; + uint32_t cycle_cnt; +}; + +static const struct ipu_adc_di_map di_mappings[] = { + [0] = { + /* RGB888, 8-bit bus */ + .map_byte1 = 0x1600AAAA, + .map_byte2 = 0x00E05555, + .map_byte2 = 0x00070000, + .cycle_cnt = 3, + }, + [1] = { + /* RGB666, 8-bit bus */ + .map_byte1 = 0x1C00AAAF, + .map_byte2 = 0x00E0555F, + .map_byte3 = 0x0007000F, + .cycle_cnt = 3, + }, + [2] = { + /* RGB565, 8-bit bus */ + .map_byte1 = 0x008055BF, + .map_byte2 = 0x0142015F, + .map_byte3 = 0x0007003F, + .cycle_cnt = 2, + }, + [3] = { + /* RGB888, 24-bit bus */ + .map_byte1 = 0x0007000F, + .map_byte2 = 0x000F000F, + .map_byte3 = 0x0017000F, + .cycle_cnt = 1, + }, + [4] = { + /* RGB666, 18-bit bus */ + .map_byte1 = 0x0005000F, + .map_byte2 = 0x000B000F, + .map_byte3 = 0x0011000F, + .cycle_cnt = 1, + }, + [5] = { + /* RGB565, 16-bit bus */ + .map_byte1 = 0x0004003F, + .map_byte2 = 0x000A000F, + .map_byte3 = 0x000F003F, + .cycle_cnt = 1, + }, +}; + +/* Private methods */ +static void _ipu_set_cmd_data_mappings(display_port_t disp, + uint32_t pixel_fmt, int ifc_width) +{ + uint32_t reg; + u32 map = 0; + + if (ifc_width == 8) { + switch (pixel_fmt) { + case IPU_PIX_FMT_BGR24: + map = 0; + break; + case IPU_PIX_FMT_RGB666: + map = 1; + break; + case IPU_PIX_FMT_RGB565: + map = 2; + break; + default: + break; + } + } else if (ifc_width >= 16) { + switch (pixel_fmt) { + case IPU_PIX_FMT_GENERIC_16: + case IPU_PIX_FMT_BGR24: + map = 3; + break; + case IPU_PIX_FMT_RGB666: + map = 4; + break; + case IPU_PIX_FMT_RGB565: + map = 5; + break; + default: + break; + } + } + + switch (disp) { + case DISP0: + if (ifc_width == 8) { + __raw_writel(0x00070000, DI_DISP0_CB0_MAP); + __raw_writel(0x0000FFFF, DI_DISP0_CB1_MAP); + __raw_writel(0x0000FFFF, DI_DISP0_CB2_MAP); + } else { + __raw_writel(0x00070000, DI_DISP0_CB0_MAP); + __raw_writel(0x000F0000, DI_DISP0_CB1_MAP); + __raw_writel(0x0000FFFF, DI_DISP0_CB2_MAP); + } + __raw_writel(di_mappings[map].map_byte1, DI_DISP0_DB0_MAP); + __raw_writel(di_mappings[map].map_byte2, DI_DISP0_DB1_MAP); + __raw_writel(di_mappings[map].map_byte3, DI_DISP0_DB2_MAP); + reg = __raw_readl(DI_DISP_ACC_CC); + reg &= ~DISP0_IF_CLK_CNT_D_MASK; + reg |= (di_mappings[map].cycle_cnt - 1) << + DISP0_IF_CLK_CNT_D_OFFSET; + __raw_writel(reg, DI_DISP_ACC_CC); + break; + case DISP1: + if (ifc_width == 8) { + __raw_writel(0x00070000, DI_DISP1_CB0_MAP); + __raw_writel(0x0000FFFF, DI_DISP1_CB1_MAP); + __raw_writel(0x0000FFFF, DI_DISP1_CB2_MAP); + } else { + __raw_writel(0x00070000, DI_DISP1_CB0_MAP); + __raw_writel(0x000F0000, DI_DISP1_CB1_MAP); + __raw_writel(0x0000FFFF, DI_DISP1_CB2_MAP); + } + __raw_writel(di_mappings[map].map_byte1, DI_DISP1_DB0_MAP); + __raw_writel(di_mappings[map].map_byte2, DI_DISP1_DB1_MAP); + __raw_writel(di_mappings[map].map_byte3, DI_DISP1_DB2_MAP); + reg = __raw_readl(DI_DISP_ACC_CC); + reg &= ~DISP1_IF_CLK_CNT_D_MASK; + reg |= (di_mappings[map].cycle_cnt - 1) << + DISP1_IF_CLK_CNT_D_OFFSET; + __raw_writel(reg, DI_DISP_ACC_CC); + break; + case DISP2: + if (ifc_width == 8) { + __raw_writel(0x00070000, DI_DISP2_CB0_MAP); + __raw_writel(0x0000FFFF, DI_DISP2_CB1_MAP); + __raw_writel(0x0000FFFF, DI_DISP2_CB2_MAP); + } else { + __raw_writel(0x00070000, DI_DISP2_CB0_MAP); + __raw_writel(0x000F0000, DI_DISP2_CB1_MAP); + __raw_writel(0x0000FFFF, DI_DISP2_CB2_MAP); + } + __raw_writel(di_mappings[map].map_byte1, DI_DISP2_DB0_MAP); + __raw_writel(di_mappings[map].map_byte2, DI_DISP2_DB1_MAP); + __raw_writel(di_mappings[map].map_byte3, DI_DISP2_DB2_MAP); + reg = __raw_readl(DI_DISP_ACC_CC); + reg &= ~DISP2_IF_CLK_CNT_D_MASK; + reg |= (di_mappings[map].cycle_cnt - 1) << + DISP2_IF_CLK_CNT_D_OFFSET; + __raw_writel(reg, DI_DISP_ACC_CC); + break; + default: + break; + } +} + +EXPORT_SYMBOL(ipu_adc_write_template); +EXPORT_SYMBOL(ipu_adc_write_cmd); +#ifdef CONFIG_MACH_LUIGI_LAB126 +EXPORT_SYMBOL(ipu_adc_read_data); +#endif +EXPORT_SYMBOL(ipu_adc_set_update_mode); +EXPORT_SYMBOL(ipu_adc_init_panel); +EXPORT_SYMBOL(ipu_adc_init_ifc_timing); diff -urN linux-2.6.26/drivers/mxc/ipu/ipu_common.c linux-2.6.26-lab126/drivers/mxc/ipu/ipu_common.c --- linux-2.6.26/drivers/mxc/ipu/ipu_common.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu/ipu_common.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,1870 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_common.c + * + * @brief This file contains the IPU driver common API functions. + * + * @ingroup IPU + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ipu_prv.h" +#include +#include "ipu_param_mem.h" + +/* + * This type definition is used to define a node in the GPIO interrupt queue for + * registered interrupts for GPIO pins. Each node contains the GPIO signal number + * associated with the ISR and the actual ISR function pointer. + */ +struct ipu_irq_node { + irqreturn_t(*handler) (int, void *); /*!< the ISR */ + const char *name; /*!< device associated with the interrupt */ + void *dev_id; /*!< some unique information for the ISR */ + __u32 flags; /*!< not used */ +}; + +/* Globals */ +struct clk *g_ipu_clk; +struct clk *g_ipu_csi_clk; +static struct clk *dfm_clk; +int g_ipu_irq[2]; +int g_ipu_hw_rev; +bool g_sec_chan_en[21]; +uint32_t g_channel_init_mask; +DEFINE_SPINLOCK(ipu_lock); +struct device *g_ipu_dev; + +static struct ipu_irq_node ipu_irq_list[IPU_IRQ_COUNT]; +static const char driver_name[] = "mxc_ipu"; + +static uint32_t g_ipu_config = 0; +static uint32_t g_channel_init_mask_backup = 0; +static bool g_csi_used = false; + +/* Static functions */ +static irqreturn_t ipu_irq_handler(int irq, void *desc); +static void _ipu_pf_init(ipu_channel_params_t * params); +static void _ipu_pf_uninit(void); + +inline static uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type) +{ + return ((type == IPU_INPUT_BUFFER) ? ((uint32_t) ch & 0xFF) : + ((type == IPU_OUTPUT_BUFFER) ? (((uint32_t) ch >> 8) & 0xFF) + : (((uint32_t) ch >> 16) & 0xFF))); +}; + +inline static uint32_t DMAParamAddr(uint32_t dma_ch) +{ + return (0x10000 | (dma_ch << 4)); +}; + +/*! + * This function is called by the driver framework to initialize the IPU + * hardware. + * + * @param dev The device structure for the IPU passed in by the framework. + * + * @return This function returns 0 on success or negative error code on error + */ +static +int ipu_probe(struct platform_device *pdev) +{ +// struct platform_device *pdev = to_platform_device(dev); + struct mxc_ipu_config *ipu_conf = pdev->dev.platform_data; + + ipu_spin_lock_init(&ipu_lock); + + g_ipu_dev = &pdev->dev; + g_ipu_hw_rev = ipu_conf->rev; + + /* Register IPU interrupts */ + g_ipu_irq[0] = platform_get_irq(pdev, 0); + if (g_ipu_irq[0] < 0) + return -EINVAL; + + if (request_irq(g_ipu_irq[0], ipu_irq_handler, 0, driver_name, 0) != 0) { + dev_err(g_ipu_dev, "request SYNC interrupt failed\n"); + return -EBUSY; + } + /* Some platforms have 2 IPU interrupts */ + g_ipu_irq[1] = platform_get_irq(pdev, 1); + if (g_ipu_irq[1] >= 0) { + if (request_irq + (g_ipu_irq[1], ipu_irq_handler, 0, driver_name, 0) != 0) { + dev_err(g_ipu_dev, "request ERR interrupt failed\n"); + return -EBUSY; + } + } + + /* Enable IPU and CSI clocks */ + /* Get IPU clock freq */ + g_ipu_clk = clk_get(&pdev->dev, "ipu_clk"); + dev_dbg(g_ipu_dev, "ipu_clk = %lu\n", clk_get_rate(g_ipu_clk)); + + g_ipu_csi_clk = clk_get(&pdev->dev, "csi_clk"); + + dfm_clk = clk_get(NULL, "dfm_clk"); + + clk_enable(g_ipu_clk); + + /* resetting the CONF register of the IPU */ + __raw_writel(0x00000000, IPU_CONF); + + __raw_writel(0x00100010L, DI_HSP_CLK_PER); + + /* Set SDC refresh channels as high priority */ + __raw_writel(0x0000C000L, IDMAC_CHA_PRI); + + /* Set to max back to back burst requests */ + __raw_writel(0x00000000L, IDMAC_CONF); + + register_ipu_device(); + +#ifdef CONFIG_MACH_LUIGI_LAB126 + /* call the controller early detect init */ + _ipu_l126_detect_init(pdev); +#endif + + return 0; +} + +/*! + * This function is called to initialize a logical IPU channel. + * + * @param channel Input parameter for the logical channel ID to initalize. + * + * @param params Input parameter containing union of channel initialization + * parameters. + * + * @return This function returns 0 on success or negative error code on fail + */ +int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t * params) +{ + uint32_t ipu_conf; + uint32_t reg; + unsigned long lock_flags; + + dev_dbg(g_ipu_dev, "init channel = %d\n", IPU_CHAN_ID(channel)); + + if ((channel != MEM_SDC_BG) && (channel != MEM_SDC_FG) && + (channel != MEM_ROT_ENC_MEM) && (channel != MEM_ROT_VF_MEM) && + (channel != MEM_ROT_PP_MEM) && (channel != CSI_MEM) + && (params == NULL)) { + return -EINVAL; + } + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + + ipu_conf = __raw_readl(IPU_CONF); + if (ipu_conf == 0) { + clk_enable(g_ipu_clk); + } + + if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) { + dev_err(g_ipu_dev, "Warning: channel already initialized %d\n", + IPU_CHAN_ID(channel)); + } + + switch (channel) { + case CSI_PRP_VF_MEM: + reg = __raw_readl(IPU_FS_PROC_FLOW); + __raw_writel(reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW); + + if (params->mem_prp_vf_mem.graphics_combine_en) + g_sec_chan_en[IPU_CHAN_ID(channel)] = true; + + _ipu_ic_init_prpvf(params, true); + break; + case CSI_PRP_VF_ADC: + reg = __raw_readl(IPU_FS_PROC_FLOW); + __raw_writel(reg | (FS_DEST_ADC << FS_PRPVF_DEST_SEL_OFFSET), + IPU_FS_PROC_FLOW); + + _ipu_adc_init_channel(CSI_PRP_VF_ADC, + params->csi_prp_vf_adc.disp, + WriteTemplateNonSeq, + params->csi_prp_vf_adc.out_left, + params->csi_prp_vf_adc.out_top); + + _ipu_ic_init_prpvf(params, true); + break; + case MEM_PRP_VF_MEM: + reg = __raw_readl(IPU_FS_PROC_FLOW); + __raw_writel(reg | FS_VF_IN_VALID, IPU_FS_PROC_FLOW); + + if (params->mem_prp_vf_mem.graphics_combine_en) + g_sec_chan_en[IPU_CHAN_ID(channel)] = true; + + _ipu_ic_init_prpvf(params, false); + break; + case MEM_ROT_VF_MEM: + _ipu_ic_init_rotate_vf(params); + break; + case CSI_PRP_ENC_MEM: + reg = __raw_readl(IPU_FS_PROC_FLOW); + __raw_writel(reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW); + _ipu_ic_init_prpenc(params, true); + break; + case MEM_PRP_ENC_MEM: + reg = __raw_readl(IPU_FS_PROC_FLOW); + __raw_writel(reg | FS_ENC_IN_VALID, IPU_FS_PROC_FLOW); + _ipu_ic_init_prpenc(params, false); + break; + case MEM_ROT_ENC_MEM: + _ipu_ic_init_rotate_enc(params); + break; + case MEM_PP_ADC: + reg = __raw_readl(IPU_FS_PROC_FLOW); + __raw_writel(reg | (FS_DEST_ADC << FS_PP_DEST_SEL_OFFSET), + IPU_FS_PROC_FLOW); + + _ipu_adc_init_channel(MEM_PP_ADC, params->mem_pp_adc.disp, + WriteTemplateNonSeq, + params->mem_pp_adc.out_left, + params->mem_pp_adc.out_top); + + if (params->mem_pp_adc.graphics_combine_en) + g_sec_chan_en[IPU_CHAN_ID(channel)] = true; + + _ipu_ic_init_pp(params); + break; + case MEM_PP_MEM: + if (params->mem_pp_mem.graphics_combine_en) + g_sec_chan_en[IPU_CHAN_ID(channel)] = true; + + _ipu_ic_init_pp(params); + break; + case MEM_ROT_PP_MEM: + _ipu_ic_init_rotate_pp(params); + break; + case CSI_MEM: + _ipu_ic_init_csi(params); + break; + + case MEM_PF_Y_MEM: + case MEM_PF_U_MEM: + case MEM_PF_V_MEM: + /* Enable PF block */ + _ipu_pf_init(params); + break; + + case MEM_SDC_BG: + break; + case MEM_SDC_FG: + break; + case ADC_SYS1: + _ipu_adc_init_channel(ADC_SYS1, params->adc_sys1.disp, + params->adc_sys1.ch_mode, + params->adc_sys1.out_left, + params->adc_sys1.out_top); + break; + case ADC_SYS2: + _ipu_adc_init_channel(ADC_SYS2, params->adc_sys2.disp, + params->adc_sys2.ch_mode, + params->adc_sys2.out_left, + params->adc_sys2.out_top); + break; + default: + dev_err(g_ipu_dev, "Missing channel initialization\n"); + break; + } + + /* Enable IPU sub module */ + g_channel_init_mask |= 1L << IPU_CHAN_ID(channel); + + if (g_channel_init_mask & 0x00000066L) { /*CSI */ + ipu_conf |= IPU_CONF_CSI_EN; + if (cpu_is_mx31() || cpu_is_mx32()) { + g_csi_used = true; + } + } + if (g_channel_init_mask & 0x00001FFFL) { /*IC */ + ipu_conf |= IPU_CONF_IC_EN; + } + if (g_channel_init_mask & 0x00000A10L) { /*ROT */ + ipu_conf |= IPU_CONF_ROT_EN; + } + if (g_channel_init_mask & 0x0001C000L) { /*SDC */ + ipu_conf |= IPU_CONF_SDC_EN | IPU_CONF_DI_EN; + } + if (g_channel_init_mask & 0x00061140L) { /*ADC */ + ipu_conf |= IPU_CONF_ADC_EN | IPU_CONF_DI_EN; + } + if (g_channel_init_mask & 0x00380000L) { /*PF */ + ipu_conf |= IPU_CONF_PF_EN; + } + __raw_writel(ipu_conf, IPU_CONF); + + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} + +/*! + * This function is called to uninitialize a logical IPU channel. + * + * @param channel Input parameter for the logical channel ID to uninitalize. + */ +void ipu_uninit_channel(ipu_channel_t channel) +{ + unsigned long lock_flags; + uint32_t reg; + uint32_t dma, mask = 0; + uint32_t ipu_conf; + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + + if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) { + dev_err(g_ipu_dev, "Channel already uninitialized %d\n", + IPU_CHAN_ID(channel)); + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + return; + } + + /* Make sure channel is disabled */ + /* Get input and output dma channels */ + dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + if (dma != IDMA_CHAN_INVALID) + mask |= 1UL << dma; + dma = channel_2_dma(channel, IPU_INPUT_BUFFER); + if (dma != IDMA_CHAN_INVALID) + mask |= 1UL << dma; + /* Get secondary input dma channel */ + if (g_sec_chan_en[IPU_CHAN_ID(channel)]) { + dma = channel_2_dma(channel, IPU_SEC_INPUT_BUFFER); + if (dma != IDMA_CHAN_INVALID) { + mask |= 1UL << dma; + } + } + if (mask & __raw_readl(IDMAC_CHA_EN)) { + dev_err(g_ipu_dev, + "Channel %d is not disabled, disable first\n", + IPU_CHAN_ID(channel)); + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + return; + } + + /* Reset the double buffer */ + reg = __raw_readl(IPU_CHA_DB_MODE_SEL); + __raw_writel(reg & ~mask, IPU_CHA_DB_MODE_SEL); + + g_sec_chan_en[IPU_CHAN_ID(channel)] = false; + + switch (channel) { + case CSI_MEM: + _ipu_ic_uninit_csi(); + break; + case CSI_PRP_VF_ADC: + reg = __raw_readl(IPU_FS_PROC_FLOW); + __raw_writel(reg & ~FS_PRPVF_DEST_SEL_MASK, IPU_FS_PROC_FLOW); + + _ipu_adc_uninit_channel(CSI_PRP_VF_ADC); + + /* Fall thru */ + case CSI_PRP_VF_MEM: + case MEM_PRP_VF_MEM: + _ipu_ic_uninit_prpvf(); + break; + case MEM_PRP_VF_ADC: + break; + case MEM_ROT_VF_MEM: + _ipu_ic_uninit_rotate_vf(); + break; + case CSI_PRP_ENC_MEM: + case MEM_PRP_ENC_MEM: + _ipu_ic_uninit_prpenc(); + break; + case MEM_ROT_ENC_MEM: + _ipu_ic_uninit_rotate_enc(); + break; + case MEM_PP_ADC: + reg = __raw_readl(IPU_FS_PROC_FLOW); + __raw_writel(reg & ~FS_PP_DEST_SEL_MASK, IPU_FS_PROC_FLOW); + + _ipu_adc_uninit_channel(MEM_PP_ADC); + + /* Fall thru */ + case MEM_PP_MEM: + _ipu_ic_uninit_pp(); + break; + case MEM_ROT_PP_MEM: + _ipu_ic_uninit_rotate_pp(); + break; + + case MEM_PF_Y_MEM: + _ipu_pf_uninit(); + break; + case MEM_PF_U_MEM: + case MEM_PF_V_MEM: + break; + + case MEM_SDC_BG: + break; + case MEM_SDC_FG: + break; + case ADC_SYS1: + _ipu_adc_uninit_channel(ADC_SYS1); + break; + case ADC_SYS2: + _ipu_adc_uninit_channel(ADC_SYS2); + break; + case MEM_SDC_MASK: + case CHAN_NONE: + break; + } + + g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel)); + + ipu_conf = __raw_readl(IPU_CONF); + if ((g_channel_init_mask & 0x00000066L) == 0) { /*CSI */ + ipu_conf &= ~IPU_CONF_CSI_EN; + } + if ((g_channel_init_mask & 0x00001FFFL) == 0) { /*IC */ + ipu_conf &= ~IPU_CONF_IC_EN; + } + if ((g_channel_init_mask & 0x00000A10L) == 0) { /*ROT */ + ipu_conf &= ~IPU_CONF_ROT_EN; + } + if ((g_channel_init_mask & 0x0001C000L) == 0) { /*SDC */ + ipu_conf &= ~IPU_CONF_SDC_EN; + } + if ((g_channel_init_mask & 0x00061140L) == 0) { /*ADC */ + ipu_conf &= ~IPU_CONF_ADC_EN; + } + if ((g_channel_init_mask & 0x0007D140L) == 0) { /*DI */ + ipu_conf &= ~IPU_CONF_DI_EN; + } + if ((g_channel_init_mask & 0x00380000L) == 0) { /*PF */ + ipu_conf &= ~IPU_CONF_PF_EN; + } + __raw_writel(ipu_conf, IPU_CONF); + if (ipu_conf == 0) { + clk_disable(g_ipu_clk); + } + + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); +} + +/*! + * This function is called to initialize a buffer for logical IPU channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to initialize. + * + * @param pixel_fmt Input parameter for pixel format of buffer. Pixel + * format is a FOURCC ASCII code. + * + * @param width Input parameter for width of buffer in pixels. + * + * @param height Input parameter for height of buffer in pixels. + * + * @param stride Input parameter for stride length of buffer + * in pixels. + * + * @param rot_mode Input parameter for rotation setting of buffer. + * A rotation setting other than \b IPU_ROTATE_VERT_FLIP + * should only be used for input buffers of rotation + * channels. + * + * @param phyaddr_0 Input parameter buffer 0 physical address. + * + * @param phyaddr_1 Input parameter buffer 1 physical address. + * Setting this to a value other than NULL enables + * double buffering mode. + * + * @param u private u offset for additional cropping, + * zero if not used. + * + * @param v private v offset for additional cropping, + * zero if not used. + * + * @return This function returns 0 on success or negative error code on fail + */ +int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + ipu_rotate_mode_t rot_mode, + dma_addr_t phyaddr_0, dma_addr_t phyaddr_1, + uint32_t u, uint32_t v) +{ + uint32_t params[10]; + unsigned long lock_flags; + uint32_t reg; + uint32_t dma_chan; + uint32_t stride_bytes; + + dma_chan = channel_2_dma(channel, type); + stride_bytes = stride * bytes_per_pixel(pixel_fmt); + + if (dma_chan == IDMA_CHAN_INVALID) + return -EINVAL; + + if (stride_bytes % 4) { + dev_err(g_ipu_dev, + "Stride length must be 32-bit aligned, stride = %d, bytes = %d\n", + stride, stride_bytes); + return -EINVAL; + } + /* IC channels' stride must be multiple of 8 pixels */ + if ((dma_chan <= 13) && (stride % 8)) { + dev_err(g_ipu_dev, "Stride must be 8 pixel multiple\n"); + return -EINVAL; + } + /* Build parameter memory data for DMA channel */ + _ipu_ch_param_set_size(params, pixel_fmt, width, height, stride_bytes, + u, v); + _ipu_ch_param_set_buffer(params, phyaddr_0, phyaddr_1); + _ipu_ch_param_set_rotation(params, rot_mode); + /* Some channels (rotation) have restriction on burst length */ + if ((dma_chan == 10) || (dma_chan == 11) || (dma_chan == 13)) { + _ipu_ch_param_set_burst_size(params, 8); + } else if (dma_chan == 24) { /* PF QP channel */ + _ipu_ch_param_set_burst_size(params, 4); + } else if (dma_chan == 25) { /* PF H264 BS channel */ + _ipu_ch_param_set_burst_size(params, 16); + } else if (((dma_chan == 14) || (dma_chan == 15)) && + pixel_fmt == IPU_PIX_FMT_RGB565) { + _ipu_ch_param_set_burst_size(params, 16); + } + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + + _ipu_write_param_mem(DMAParamAddr(dma_chan), params, 10); + + reg = __raw_readl(IPU_CHA_DB_MODE_SEL); + if (phyaddr_1) { + reg |= 1UL << dma_chan; + } else { + reg &= ~(1UL << dma_chan); + } + __raw_writel(reg, IPU_CHA_DB_MODE_SEL); + + /* Reset to buffer 0 */ + __raw_writel(1UL << dma_chan, IPU_CHA_CUR_BUF); + + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} + +/*! + * This function is called to update the physical address of a buffer for + * a logical IPU channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to initialize. + * + * @param bufNum Input parameter for which buffer number to update. + * 0 or 1 are the only valid values. + * + * @param phyaddr Input parameter buffer physical address. + * + * @return This function returns 0 on success or negative error code on + * fail. This function will fail if the buffer is set to ready. + */ +int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum, dma_addr_t phyaddr) +{ + uint32_t reg; + unsigned long lock_flags; + uint32_t dma_chan = channel_2_dma(channel, type); + + if (dma_chan == IDMA_CHAN_INVALID) + return -EINVAL; + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + + if (bufNum == 0) { + reg = __raw_readl(IPU_CHA_BUF0_RDY); + if (reg & (1UL << dma_chan)) { + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + return -EACCES; + } + __raw_writel(DMAParamAddr(dma_chan) + 0x0008UL, IPU_IMA_ADDR); + __raw_writel(phyaddr, IPU_IMA_DATA); + } else { + reg = __raw_readl(IPU_CHA_BUF1_RDY); + if (reg & (1UL << dma_chan)) { + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + return -EACCES; + } + __raw_writel(DMAParamAddr(dma_chan) + 0x0009UL, IPU_IMA_ADDR); + __raw_writel(phyaddr, IPU_IMA_DATA); + } + + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + dev_dbg(g_ipu_dev, "IPU: update IDMA ch %d buf %d = 0x%08X\n", + dma_chan, bufNum, phyaddr); + return 0; +} + +/*! + * This function is called to set a channel's buffer as ready. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to initialize. + * + * @param bufNum Input parameter for which buffer number set to + * ready state. + * + * @return This function returns 0 on success or negative error code on fail + */ +int32_t ipu_select_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum) +{ + uint32_t dma_chan = channel_2_dma(channel, type); + + if (dma_chan == IDMA_CHAN_INVALID) + return -EINVAL; + + if (bufNum == 0) { + /*Mark buffer 0 as ready. */ + __raw_writel(1UL << dma_chan, IPU_CHA_BUF0_RDY); + } else { + /*Mark buffer 1 as ready. */ + __raw_writel(1UL << dma_chan, IPU_CHA_BUF1_RDY); + } + return 0; +} + +/*! + * This function links 2 channels together for automatic frame + * synchronization. The output of the source channel is linked to the input of + * the destination channel. + * + * @param src_ch Input parameter for the logical channel ID of + * the source channel. + * + * @param dest_ch Input parameter for the logical channel ID of + * the destination channel. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_link_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch) +{ + unsigned long lock_flags; + uint32_t out_dma; + uint32_t in_dma; + bool isProc; + uint32_t value; + uint32_t mask; + uint32_t offset; + uint32_t fs_proc_flow; + uint32_t fs_disp_flow; + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + + fs_proc_flow = __raw_readl(IPU_FS_PROC_FLOW); + fs_disp_flow = __raw_readl(IPU_FS_DISP_FLOW); + + out_dma = (1UL << channel_2_dma(src_ch, IPU_OUTPUT_BUFFER)); + in_dma = (1UL << channel_2_dma(dest_ch, IPU_INPUT_BUFFER)); + + /* PROCESS THE OUTPUT DMA CH */ + switch (out_dma) { + /*VF-> */ + case IDMA_IC_1: + pr_debug("Link VF->"); + isProc = true; + mask = FS_PRPVF_DEST_SEL_MASK; + offset = FS_PRPVF_DEST_SEL_OFFSET; + value = (in_dma == IDMA_IC_11) ? FS_DEST_ROT : /*->VF_ROT */ + (in_dma == IDMA_ADC_SYS1_WR) ? FS_DEST_ADC1 : /* ->ADC1 */ + (in_dma == IDMA_ADC_SYS2_WR) ? FS_DEST_ADC2 : /* ->ADC2 */ + (in_dma == IDMA_SDC_BG) ? FS_DEST_SDC_BG : /*->SDC_BG */ + (in_dma == IDMA_SDC_FG) ? FS_DEST_SDC_FG : /*->SDC_FG */ + (in_dma == IDMA_ADC_SYS1_WR) ? FS_DEST_ADC1 : /*->ADC1 */ + /* ->ADCDirect */ + 0; + break; + + /*VF_ROT-> */ + case IDMA_IC_9: + pr_debug("Link VF_ROT->"); + isProc = true; + mask = FS_PRPVF_ROT_DEST_SEL_MASK; + offset = FS_PRPVF_ROT_DEST_SEL_OFFSET; + value = (in_dma == IDMA_ADC_SYS1_WR) ? FS_DEST_ADC1 : /*->ADC1 */ + (in_dma == IDMA_ADC_SYS2_WR) ? FS_DEST_ADC2 : /* ->ADC2 */ + (in_dma == IDMA_SDC_BG) ? FS_DEST_SDC_BG : /*->SDC_BG */ + (in_dma == IDMA_SDC_FG) ? FS_DEST_SDC_FG : /*->SDC_FG */ + 0; + break; + + /*ENC-> */ + case IDMA_IC_0: + pr_debug("Link ENC->"); + isProc = true; + mask = 0; + offset = 0; + value = (in_dma == IDMA_IC_10) ? FS_PRPENC_DEST_SEL : /*->ENC_ROT */ + 0; + break; + + /*PP-> */ + case IDMA_IC_2: + pr_debug("Link PP->"); + isProc = true; + mask = FS_PP_DEST_SEL_MASK; + offset = FS_PP_DEST_SEL_OFFSET; + value = (in_dma == IDMA_IC_13) ? FS_DEST_ROT : /*->PP_ROT */ + (in_dma == IDMA_ADC_SYS1_WR) ? FS_DEST_ADC1 : /* ->ADC1 */ + (in_dma == IDMA_ADC_SYS2_WR) ? FS_DEST_ADC2 : /* ->ADC2 */ + (in_dma == IDMA_SDC_BG) ? FS_DEST_SDC_BG : /*->SDC_BG */ + (in_dma == IDMA_SDC_FG) ? FS_DEST_SDC_FG : /*->SDC_FG */ + /* ->ADCDirect */ + 0; + break; + + /*PP_ROT-> */ + case IDMA_IC_12: + pr_debug("Link PP_ROT->"); + isProc = true; + mask = FS_PP_ROT_DEST_SEL_MASK; + offset = FS_PP_ROT_DEST_SEL_OFFSET; + value = (in_dma == IDMA_IC_5) ? FS_DEST_ROT : /*->PP */ + (in_dma == IDMA_ADC_SYS1_WR) ? FS_DEST_ADC1 : /* ->ADC1 */ + (in_dma == IDMA_ADC_SYS2_WR) ? FS_DEST_ADC2 : /* ->ADC2 */ + (in_dma == IDMA_SDC_BG) ? FS_DEST_SDC_BG : /*->SDC_BG */ + (in_dma == IDMA_SDC_FG) ? FS_DEST_SDC_FG : /*->SDC_FG */ + 0; + break; + + /*PF-> */ + case IDMA_PF_Y_OUT: + case IDMA_PF_U_OUT: + case IDMA_PF_V_OUT: + pr_debug("Link PF->"); + isProc = true; + mask = FS_PF_DEST_SEL_MASK; + offset = FS_PF_DEST_SEL_OFFSET; + value = (in_dma == IDMA_IC_5) ? FS_PF_DEST_PP : + (in_dma == IDMA_IC_13) ? FS_PF_DEST_ROT : 0; + break; + + /* Invalid Chainings: ENC_ROT-> */ + default: + pr_debug("Link Invalid->"); + value = 0; + break; + + } + + if (value) { + if (isProc) { + fs_proc_flow &= ~mask; + fs_proc_flow |= (value << offset); + } else { + fs_disp_flow &= ~mask; + fs_disp_flow |= (value << offset); + } + } else { + dev_err(g_ipu_dev, "Invalid channel chaining %d -> %d\n", + out_dma, in_dma); + return -EINVAL; + } + + /* PROCESS THE INPUT DMA CH */ + switch (in_dma) { + /* ->VF_ROT */ + case IDMA_IC_11: + pr_debug("VF_ROT\n"); + isProc = true; + mask = 0; + offset = 0; + value = (out_dma == IDMA_IC_1) ? FS_PRPVF_ROT_SRC_SEL : /*VF-> */ + 0; + break; + + /* ->ENC_ROT */ + case IDMA_IC_10: + pr_debug("ENC_ROT\n"); + isProc = true; + mask = 0; + offset = 0; + value = (out_dma == IDMA_IC_0) ? FS_PRPENC_ROT_SRC_SEL : /*ENC-> */ + 0; + break; + + /* ->PP */ + case IDMA_IC_5: + pr_debug("PP\n"); + isProc = true; + mask = FS_PP_SRC_SEL_MASK; + offset = FS_PP_SRC_SEL_OFFSET; + value = (out_dma == IDMA_PF_Y_OUT) ? FS_PP_SRC_PF : /*PF-> */ + (out_dma == IDMA_PF_U_OUT) ? FS_PP_SRC_PF : /*PF-> */ + (out_dma == IDMA_PF_V_OUT) ? FS_PP_SRC_PF : /*PF-> */ + (out_dma == IDMA_IC_12) ? FS_PP_SRC_ROT : /*PP_ROT-> */ + 0; + break; + + /* ->PP_ROT */ + case IDMA_IC_13: + pr_debug("PP_ROT\n"); + isProc = true; + mask = FS_PP_ROT_SRC_SEL_MASK; + offset = FS_PP_ROT_SRC_SEL_OFFSET; + value = (out_dma == IDMA_PF_Y_OUT) ? FS_PP_SRC_PF : /*PF-> */ + (out_dma == IDMA_PF_U_OUT) ? FS_PP_SRC_PF : /*PF-> */ + (out_dma == IDMA_PF_V_OUT) ? FS_PP_SRC_PF : /*PF-> */ + (out_dma == IDMA_IC_2) ? FS_ROT_SRC_PP : /*PP-> */ + 0; + break; + + /* ->SDC_BG */ + case IDMA_SDC_BG: + pr_debug("SDC_BG\n"); + isProc = false; + mask = FS_SDC_BG_SRC_SEL_MASK; + offset = FS_SDC_BG_SRC_SEL_OFFSET; + value = (out_dma == IDMA_IC_9) ? FS_SRC_ROT_VF : /*VF_ROT-> */ + (out_dma == IDMA_IC_12) ? FS_SRC_ROT_PP : /*PP_ROT-> */ + (out_dma == IDMA_IC_1) ? FS_SRC_VF : /*VF-> */ + (out_dma == IDMA_IC_2) ? FS_SRC_PP : /*PP-> */ + 0; + break; + + /* ->SDC_FG */ + case IDMA_SDC_FG: + pr_debug("SDC_FG\n"); + isProc = false; + mask = FS_SDC_FG_SRC_SEL_MASK; + offset = FS_SDC_FG_SRC_SEL_OFFSET; + value = (out_dma == IDMA_IC_9) ? FS_SRC_ROT_VF : /*VF_ROT-> */ + (out_dma == IDMA_IC_12) ? FS_SRC_ROT_PP : /*PP_ROT-> */ + (out_dma == IDMA_IC_1) ? FS_SRC_VF : /*VF-> */ + (out_dma == IDMA_IC_2) ? FS_SRC_PP : /*PP-> */ + 0; + break; + + /* ->ADC1 */ + case IDMA_ADC_SYS1_WR: + pr_debug("ADC_SYS1\n"); + isProc = false; + mask = FS_ADC1_SRC_SEL_MASK; + offset = FS_ADC1_SRC_SEL_OFFSET; + value = (out_dma == IDMA_IC_9) ? FS_SRC_ROT_VF : /*VF_ROT-> */ + (out_dma == IDMA_IC_12) ? FS_SRC_ROT_PP : /*PP_ROT-> */ + (out_dma == IDMA_IC_1) ? FS_SRC_VF : /*VF-> */ + (out_dma == IDMA_IC_2) ? FS_SRC_PP : /*PP-> */ + 0; + break; + + /* ->ADC2 */ + case IDMA_ADC_SYS2_WR: + pr_debug("ADC_SYS2\n"); + isProc = false; + mask = FS_ADC2_SRC_SEL_MASK; + offset = FS_ADC2_SRC_SEL_OFFSET; + value = (out_dma == IDMA_IC_9) ? FS_SRC_ROT_VF : /*VF_ROT-> */ + (out_dma == IDMA_IC_12) ? FS_SRC_ROT_PP : /*PP_ROT-> */ + (out_dma == IDMA_IC_1) ? FS_SRC_VF : /*VF-> */ + (out_dma == IDMA_IC_2) ? FS_SRC_PP : /*PP-> */ + 0; + break; + + /*Invalid chains: */ + /* ->ENC, ->VF, ->PF, ->VF_COMBINE, ->PP_COMBINE */ + default: + pr_debug("Invalid\n"); + value = 0; + break; + + } + + if (value) { + if (isProc) { + fs_proc_flow &= ~mask; + fs_proc_flow |= (value << offset); + } else { + fs_disp_flow &= ~mask; + fs_disp_flow |= (value << offset); + } + } else { + dev_err(g_ipu_dev, "Invalid channel chaining %d -> %d\n", + out_dma, in_dma); + return -EINVAL; + } + + __raw_writel(fs_proc_flow, IPU_FS_PROC_FLOW); + __raw_writel(fs_disp_flow, IPU_FS_DISP_FLOW); + + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + return 0; +} + +/*! + * This function unlinks 2 channels and disables automatic frame + * synchronization. + * + * @param src_ch Input parameter for the logical channel ID of + * the source channel. + * + * @param dest_ch Input parameter for the logical channel ID of + * the destination channel. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_unlink_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch) +{ + unsigned long lock_flags; + uint32_t out_dma; + uint32_t in_dma; + uint32_t fs_proc_flow; + uint32_t fs_disp_flow; + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + + fs_proc_flow = __raw_readl(IPU_FS_PROC_FLOW); + fs_disp_flow = __raw_readl(IPU_FS_DISP_FLOW); + + out_dma = (1UL << channel_2_dma(src_ch, IPU_OUTPUT_BUFFER)); + in_dma = (1UL << channel_2_dma(dest_ch, IPU_INPUT_BUFFER)); + + /*clear the src_ch's output destination */ + switch (out_dma) { + /*VF-> */ + case IDMA_IC_1: + pr_debug("Unlink VF->"); + fs_proc_flow &= ~FS_PRPVF_DEST_SEL_MASK; + break; + + /*VF_ROT-> */ + case IDMA_IC_9: + pr_debug("Unlink VF_Rot->"); + fs_proc_flow &= ~FS_PRPVF_ROT_DEST_SEL_MASK; + break; + + /*ENC-> */ + case IDMA_IC_0: + pr_debug("Unlink ENC->"); + fs_proc_flow &= ~FS_PRPENC_DEST_SEL; + break; + + /*PP-> */ + case IDMA_IC_2: + pr_debug("Unlink PP->"); + fs_proc_flow &= ~FS_PP_DEST_SEL_MASK; + break; + + /*PP_ROT-> */ + case IDMA_IC_12: + pr_debug("Unlink PP_ROT->"); + fs_proc_flow &= ~FS_PP_ROT_DEST_SEL_MASK; + break; + + /*PF-> */ + case IDMA_PF_Y_OUT: + case IDMA_PF_U_OUT: + case IDMA_PF_V_OUT: + pr_debug("Unlink PF->"); + fs_proc_flow &= ~FS_PF_DEST_SEL_MASK; + break; + + default: /*ENC_ROT-> */ + pr_debug("Unlink Invalid->"); + break; + } + + /*clear the dest_ch's input source */ + switch (in_dma) { + /*->VF_ROT*/ + case IDMA_IC_11: + pr_debug("VF_ROT\n"); + fs_proc_flow &= ~FS_PRPVF_ROT_SRC_SEL; + break; + + /*->Enc_ROT*/ + case IDMA_IC_10: + pr_debug("ENC_ROT\n"); + fs_proc_flow &= ~FS_PRPENC_ROT_SRC_SEL; + break; + + /*->PP*/ + case IDMA_IC_5: + pr_debug("PP\n"); + fs_proc_flow &= ~FS_PP_SRC_SEL_MASK; + break; + + /*->PP_ROT*/ + case IDMA_IC_13: + pr_debug("PP_ROT\n"); + fs_proc_flow &= ~FS_PP_ROT_SRC_SEL_MASK; + break; + + /*->SDC_FG*/ + case IDMA_SDC_FG: + pr_debug("SDC_FG\n"); + fs_disp_flow &= ~FS_SDC_FG_SRC_SEL_MASK; + break; + + /*->SDC_BG*/ + case IDMA_SDC_BG: + pr_debug("SDC_BG\n"); + fs_disp_flow &= ~FS_SDC_BG_SRC_SEL_MASK; + break; + + /*->ADC1*/ + case IDMA_ADC_SYS1_WR: + pr_debug("ADC_SYS1\n"); + fs_disp_flow &= ~FS_ADC1_SRC_SEL_MASK; + break; + + /*->ADC2*/ + case IDMA_ADC_SYS2_WR: + pr_debug("ADC_SYS2\n"); + fs_disp_flow &= ~FS_ADC2_SRC_SEL_MASK; + break; + + default: /*->VF, ->ENC, ->VF_COMBINE, ->PP_COMBINE, ->PF*/ + pr_debug("Invalid\n"); + break; + } + + __raw_writel(fs_proc_flow, IPU_FS_PROC_FLOW); + __raw_writel(fs_disp_flow, IPU_FS_DISP_FLOW); + + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + return 0; +} + +/*! + * This function enables a logical channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_enable_channel(ipu_channel_t channel) +{ + uint32_t reg; + unsigned long lock_flags; + uint32_t in_dma; + uint32_t sec_dma; + uint32_t out_dma; + uint32_t chan_mask = 0; + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(IDMAC_CHA_EN); + + /* Get input and output dma channels */ + out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + if (out_dma != IDMA_CHAN_INVALID) + reg |= 1UL << out_dma; + in_dma = channel_2_dma(channel, IPU_INPUT_BUFFER); + if (in_dma != IDMA_CHAN_INVALID) + reg |= 1UL << in_dma; + + /* Get secondary input dma channel */ + if (g_sec_chan_en[IPU_CHAN_ID(channel)]) { + sec_dma = channel_2_dma(channel, IPU_SEC_INPUT_BUFFER); + if (sec_dma != IDMA_CHAN_INVALID) { + reg |= 1UL << sec_dma; + } + } + + __raw_writel(reg | chan_mask, IDMAC_CHA_EN); + + if (IPU_CHAN_ID(channel) <= IPU_CHAN_ID(MEM_PP_ADC)) { + _ipu_ic_enable_task(channel); + } else if (channel == MEM_SDC_BG) { + dev_dbg(g_ipu_dev, "Initializing SDC BG\n"); + _ipu_sdc_bg_init(NULL); + } else if (channel == MEM_SDC_FG) { + dev_dbg(g_ipu_dev, "Initializing SDC FG\n"); + _ipu_sdc_fg_init(NULL); + } + + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + return 0; +} + +/*! + * This function disables a logical channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param wait_for_stop Flag to set whether to wait for channel end + * of frame or return immediately. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_disable_channel(ipu_channel_t channel, bool wait_for_stop) +{ + uint32_t reg; + unsigned long lock_flags; + uint32_t sec_dma; + uint32_t in_dma; + uint32_t out_dma; + uint32_t chan_mask = 0; + uint32_t timeout; + uint32_t eof_intr; + uint32_t enabled; + + /* Get input and output dma channels */ + out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + if (out_dma != IDMA_CHAN_INVALID) + chan_mask = 1UL << out_dma; + in_dma = channel_2_dma(channel, IPU_INPUT_BUFFER); + if (in_dma != IDMA_CHAN_INVALID) + chan_mask |= 1UL << in_dma; + sec_dma = channel_2_dma(channel, IPU_SEC_INPUT_BUFFER); + if (sec_dma != IDMA_CHAN_INVALID) + chan_mask |= 1UL << sec_dma; + + if (wait_for_stop && channel != MEM_SDC_FG && channel != MEM_SDC_BG) { + timeout = 40; + while ((__raw_readl(IDMAC_CHA_BUSY) & chan_mask) || + (_ipu_channel_status(channel) == TASK_STAT_ACTIVE)) { + timeout--; + msleep(10); + if (timeout == 0) { + printk + (KERN_INFO + "MXC IPU: Warning - timeout waiting for channel to stop,\n" + "\tbuf0_rdy = 0x%08X, buf1_rdy = 0x%08X\n" + "\tbusy = 0x%08X, tstat = 0x%08X\n\tmask = 0x%08X\n", + __raw_readl(IPU_CHA_BUF0_RDY), + __raw_readl(IPU_CHA_BUF1_RDY), + __raw_readl(IDMAC_CHA_BUSY), + __raw_readl(IPU_TASKS_STAT), chan_mask); + break; + } + } + dev_dbg(g_ipu_dev, "timeout = %d * 10ms\n", 40 - timeout); + } + /* SDC BG and FG must be disabled before DMA is disabled */ + if ((channel == MEM_SDC_BG) || (channel == MEM_SDC_FG)) { + + if (channel == MEM_SDC_BG) + eof_intr = IPU_IRQ_SDC_BG_EOF; + else + eof_intr = IPU_IRQ_SDC_FG_EOF; + + /* Wait for any buffer flips to finsh */ + timeout = 4; + while (timeout && + ((__raw_readl(IPU_CHA_BUF0_RDY) & chan_mask) || + (__raw_readl(IPU_CHA_BUF1_RDY) & chan_mask))) { + msleep(10); + timeout--; + } + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + ipu_clear_irq(eof_intr); + if (channel == MEM_SDC_BG) + enabled = _ipu_sdc_bg_uninit(); + else + enabled = _ipu_sdc_fg_uninit(); + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + + if (enabled && wait_for_stop) { + timeout = 5; + } else { + timeout = 0; + } + while (timeout && !ipu_get_irq_status(eof_intr)) { + msleep(5); + timeout--; + } + } + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + + /* Disable IC task */ + if (IPU_CHAN_ID(channel) <= IPU_CHAN_ID(MEM_PP_ADC)) { + _ipu_ic_disable_task(channel); + } + + /* Disable DMA channel(s) */ + reg = __raw_readl(IDMAC_CHA_EN); + __raw_writel(reg & ~chan_mask, IDMAC_CHA_EN); + + /* Clear DMA related interrupts */ + __raw_writel(chan_mask, IPU_INT_STAT_1); + __raw_writel(chan_mask, IPU_INT_STAT_2); + __raw_writel(chan_mask, IPU_INT_STAT_4); + + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + return 0; +} + +static +irqreturn_t ipu_irq_handler(int irq, void *desc) +{ + uint32_t line_base = 0; + uint32_t line; + irqreturn_t result = IRQ_NONE; + uint32_t int_stat; + + if (g_ipu_irq[1]) { + disable_irq(g_ipu_irq[0]); + disable_irq(g_ipu_irq[1]); + } + + int_stat = __raw_readl(IPU_INT_STAT_1); + int_stat &= __raw_readl(IPU_INT_CTRL_1); + __raw_writel(int_stat, IPU_INT_STAT_1); + while ((line = ffs(int_stat)) != 0) { + int_stat &= ~(1UL << (line - 1)); + line += line_base - 1; + result |= + ipu_irq_list[line].handler(line, ipu_irq_list[line].dev_id); + } + + line_base = 32; + int_stat = __raw_readl(IPU_INT_STAT_2); + int_stat &= __raw_readl(IPU_INT_CTRL_2); + __raw_writel(int_stat, IPU_INT_STAT_2); + while ((line = ffs(int_stat)) != 0) { + int_stat &= ~(1UL << (line - 1)); + line += line_base - 1; + result |= + ipu_irq_list[line].handler(line, ipu_irq_list[line].dev_id); + } + + line_base = 64; + int_stat = __raw_readl(IPU_INT_STAT_3); + int_stat &= __raw_readl(IPU_INT_CTRL_3); + __raw_writel(int_stat, IPU_INT_STAT_3); + while ((line = ffs(int_stat)) != 0) { + int_stat &= ~(1UL << (line - 1)); + line += line_base - 1; + result |= + ipu_irq_list[line].handler(line, ipu_irq_list[line].dev_id); + } + + line_base = 96; + int_stat = __raw_readl(IPU_INT_STAT_4); + int_stat &= __raw_readl(IPU_INT_CTRL_4); + __raw_writel(int_stat, IPU_INT_STAT_4); + while ((line = ffs(int_stat)) != 0) { + int_stat &= ~(1UL << (line - 1)); + line += line_base - 1; + result |= + ipu_irq_list[line].handler(line, ipu_irq_list[line].dev_id); + } + + line_base = 128; + int_stat = __raw_readl(IPU_INT_STAT_5); + int_stat &= __raw_readl(IPU_INT_CTRL_5); + __raw_writel(int_stat, IPU_INT_STAT_5); + while ((line = ffs(int_stat)) != 0) { + int_stat &= ~(1UL << (line - 1)); + line += line_base - 1; + result |= + ipu_irq_list[line].handler(line, ipu_irq_list[line].dev_id); + } + + if (g_ipu_irq[1]) { + enable_irq(g_ipu_irq[0]); + enable_irq(g_ipu_irq[1]); + } + return result; +} + +/*! + * This function enables the interrupt for the specified interrupt line. + * The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to enable interrupt for. + * + */ +void ipu_enable_irq(uint32_t irq) +{ + uint32_t reg; + unsigned long lock_flags; + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(IPUIRQ_2_CTRLREG(irq)); + reg |= IPUIRQ_2_MASK(irq); + __raw_writel(reg, IPUIRQ_2_CTRLREG(irq)); + + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); +} + +/*! + * This function disables the interrupt for the specified interrupt line. + * The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to disable interrupt for. + * + */ +void ipu_disable_irq(uint32_t irq) +{ + uint32_t reg; + unsigned long lock_flags; + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(IPUIRQ_2_CTRLREG(irq)); + reg &= ~IPUIRQ_2_MASK(irq); + __raw_writel(reg, IPUIRQ_2_CTRLREG(irq)); + + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); +} + +/*! + * This function clears the interrupt for the specified interrupt line. + * The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to clear interrupt for. + * + */ +void ipu_clear_irq(uint32_t irq) +{ + __raw_writel(IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq)); +} + +/*! + * This function returns the current interrupt status for the specified interrupt + * line. The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to get status for. + * + * @return Returns true if the interrupt is pending/asserted or false if + * the interrupt is not pending. + */ +bool ipu_get_irq_status(uint32_t irq) +{ + uint32_t reg = __raw_readl(IPUIRQ_2_STATREG(irq)); + + if (reg & IPUIRQ_2_MASK(irq)) + return true; + else + return false; +} + +/*! + * This function registers an interrupt handler function for the specified + * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to get status for. + * + * @param handler Input parameter for address of the handler + * function. + * + * @param irq_flags Flags for interrupt mode. Currently not used. + * + * @param devname Input parameter for string name of driver + * registering the handler. + * + * @param dev_id Input parameter for pointer of data to be passed + * to the handler. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int ipu_request_irq(uint32_t irq, + irqreturn_t(*handler) (int, void *), + uint32_t irq_flags, const char *devname, void *dev_id) +{ + unsigned long lock_flags; + + BUG_ON(irq >= IPU_IRQ_COUNT); + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + + if (ipu_irq_list[irq].handler != NULL) { + dev_err(g_ipu_dev, + "ipu_request_irq - handler already installed on irq %d\n", + irq); + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + return -EINVAL; + } + + ipu_irq_list[irq].handler = handler; + ipu_irq_list[irq].flags = irq_flags; + ipu_irq_list[irq].dev_id = dev_id; + ipu_irq_list[irq].name = devname; + + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + + ipu_enable_irq(irq); /* enable the interrupt */ + + return 0; +} + +/*! + * This function unregisters an interrupt handler for the specified interrupt + * line. The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to get status for. + * + * @param dev_id Input parameter for pointer of data to be passed + * to the handler. This must match value passed to + * ipu_request_irq(). + * + */ +void ipu_free_irq(uint32_t irq, void *dev_id) +{ + ipu_disable_irq(irq); /* disable the interrupt */ + + if (ipu_irq_list[irq].dev_id == dev_id) { + ipu_irq_list[irq].handler = NULL; + } +} + +/*! + * This function sets the post-filter pause row for h.264 mode. + * + * @param pause_row The last row to process before pausing. + * + * @return This function returns 0 on success or negative error code on + * fail. + * + */ +int32_t ipu_pf_set_pause_row(uint32_t pause_row) +{ + int32_t retval = 0; + uint32_t timeout = 5; + unsigned long lock_flags; + uint32_t reg; + + reg = __raw_readl(IPU_TASKS_STAT); + while ((reg & TSTAT_PF_MASK) && ((reg & TSTAT_PF_H264_PAUSE) == 0)) { + timeout--; + msleep(5); + if (timeout == 0) { + dev_err(g_ipu_dev, "PF Timeout - tstat = 0x%08X\n", + __raw_readl(IPU_TASKS_STAT)); + retval = -ETIMEDOUT; + goto err0; + } + } + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(PF_CONF); + + /* Set the pause row */ + if (pause_row) { + reg &= ~PF_CONF_PAUSE_ROW_MASK; + reg |= PF_CONF_PAUSE_EN | pause_row << PF_CONF_PAUSE_ROW_SHIFT; + } else { + reg &= ~(PF_CONF_PAUSE_EN | PF_CONF_PAUSE_ROW_MASK); + } + __raw_writel(reg, PF_CONF); + + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + err0: + return retval; +} + +/* Private functions */ +void _ipu_write_param_mem(uint32_t addr, uint32_t * data, uint32_t numWords) +{ + for (; numWords > 0; numWords--) { + dev_dbg(g_ipu_dev, + "write param mem - addr = 0x%08X, data = 0x%08X\n", + addr, *data); + __raw_writel(addr, IPU_IMA_ADDR); + __raw_writel(*data++, IPU_IMA_DATA); + addr++; + if ((addr & 0x7) == 5) { + addr &= ~0x7; /* set to word 0 */ + addr += 8; /* increment to next row */ + } + } +} + +static void _ipu_pf_init(ipu_channel_params_t * params) +{ + uint32_t reg; + + /*Setup the type of filtering required */ + switch (params->mem_pf_mem.operation) { + case PF_MPEG4_DEBLOCK: + case PF_MPEG4_DERING: + case PF_MPEG4_DEBLOCK_DERING: + g_sec_chan_en[IPU_CHAN_ID(MEM_PF_Y_MEM)] = true; + g_sec_chan_en[IPU_CHAN_ID(MEM_PF_U_MEM)] = false; + break; + case PF_H264_DEBLOCK: + g_sec_chan_en[IPU_CHAN_ID(MEM_PF_Y_MEM)] = true; + g_sec_chan_en[IPU_CHAN_ID(MEM_PF_U_MEM)] = true; + break; + default: + g_sec_chan_en[IPU_CHAN_ID(MEM_PF_Y_MEM)] = false; + g_sec_chan_en[IPU_CHAN_ID(MEM_PF_U_MEM)] = false; + return; + break; + } + reg = params->mem_pf_mem.operation; + __raw_writel(reg, PF_CONF); +} + +static void _ipu_pf_uninit(void) +{ + __raw_writel(0x0L, PF_CONF); + g_sec_chan_en[IPU_CHAN_ID(MEM_PF_Y_MEM)] = false; + g_sec_chan_en[IPU_CHAN_ID(MEM_PF_U_MEM)] = false; +} + +uint32_t _ipu_channel_status(ipu_channel_t channel) +{ + uint32_t stat = 0; + uint32_t task_stat_reg = __raw_readl(IPU_TASKS_STAT); + + switch (channel) { + case CSI_MEM: + stat = + (task_stat_reg & TSTAT_CSI2MEM_MASK) >> + TSTAT_CSI2MEM_OFFSET; + break; + case CSI_PRP_VF_ADC: + case CSI_PRP_VF_MEM: + case MEM_PRP_VF_ADC: + case MEM_PRP_VF_MEM: + stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET; + break; + case MEM_ROT_VF_MEM: + stat = + (task_stat_reg & TSTAT_VF_ROT_MASK) >> TSTAT_VF_ROT_OFFSET; + break; + case CSI_PRP_ENC_MEM: + case MEM_PRP_ENC_MEM: + stat = (task_stat_reg & TSTAT_ENC_MASK) >> TSTAT_ENC_OFFSET; + break; + case MEM_ROT_ENC_MEM: + stat = + (task_stat_reg & TSTAT_ENC_ROT_MASK) >> + TSTAT_ENC_ROT_OFFSET; + break; + case MEM_PP_ADC: + case MEM_PP_MEM: + stat = (task_stat_reg & TSTAT_PP_MASK) >> TSTAT_PP_OFFSET; + break; + case MEM_ROT_PP_MEM: + stat = + (task_stat_reg & TSTAT_PP_ROT_MASK) >> TSTAT_PP_ROT_OFFSET; + break; + + case MEM_PF_Y_MEM: + case MEM_PF_U_MEM: + case MEM_PF_V_MEM: + stat = (task_stat_reg & TSTAT_PF_MASK) >> TSTAT_PF_OFFSET; + break; + case MEM_SDC_BG: + break; + case MEM_SDC_FG: + break; + case ADC_SYS1: + stat = + (task_stat_reg & TSTAT_ADCSYS1_MASK) >> + TSTAT_ADCSYS1_OFFSET; + break; + case ADC_SYS2: + stat = + (task_stat_reg & TSTAT_ADCSYS2_MASK) >> + TSTAT_ADCSYS2_OFFSET; + break; + case MEM_SDC_MASK: + default: + stat = TASK_STAT_IDLE; + break; + } + return stat; +} + +uint32_t bytes_per_pixel(uint32_t fmt) +{ + switch (fmt) { + case IPU_PIX_FMT_GENERIC: /*generic data */ + case IPU_PIX_FMT_RGB332: + case IPU_PIX_FMT_YUV420P: + case IPU_PIX_FMT_YUV422P: + return 1; + break; + case IPU_PIX_FMT_RGB565: + case IPU_PIX_FMT_YUYV: + case IPU_PIX_FMT_UYVY: +#ifdef CONFIG_MACH_LUIGI_LAB126 + case IPU_PIX_FMT_GENERIC_16: +#endif + return 2; + break; + case IPU_PIX_FMT_BGR24: + case IPU_PIX_FMT_RGB24: + return 3; + break; + case IPU_PIX_FMT_GENERIC_32: /*generic data */ + case IPU_PIX_FMT_BGR32: + case IPU_PIX_FMT_RGB32: + case IPU_PIX_FMT_ABGR32: + return 4; + break; + default: + return 1; + break; + } + return 0; +} + +ipu_color_space_t format_to_colorspace(uint32_t fmt) +{ + switch (fmt) { + case IPU_PIX_FMT_RGB565: + case IPU_PIX_FMT_BGR24: + case IPU_PIX_FMT_RGB24: + case IPU_PIX_FMT_BGR32: + case IPU_PIX_FMT_RGB32: + return RGB; + break; + + default: + return YCbCr; + break; + } + return RGB; + +} + +static u32 saved_disp3_time_conf; +static bool in_lpdr_mode; +static struct clk *default_ipu_parent_clk; + +int ipu_lowpwr_display_enable(void) +{ + unsigned long rate, div; + struct clk *parent_clk = g_ipu_clk; + + if (in_lpdr_mode || IS_ERR(dfm_clk)) { + return -EINVAL; + } + + if (g_channel_init_mask != (1L << IPU_CHAN_ID(MEM_SDC_BG))) { + dev_err(g_ipu_dev, "LPDR mode requires only SDC BG active.\n"); + return -EINVAL; + } + + default_ipu_parent_clk = clk_get_parent(g_ipu_clk); + in_lpdr_mode = true; + + /* Calculate current pixel clock rate */ + rate = clk_get_rate(g_ipu_clk) * 16; + saved_disp3_time_conf = __raw_readl(DI_DISP3_TIME_CONF); + div = saved_disp3_time_conf & 0xFFF; + rate /= div; + rate *= 4; /* min hsp clk is 4x pixel clk */ + + /* Initialize DFM clock */ + rate = clk_round_rate(dfm_clk, rate); + clk_set_rate(dfm_clk, rate); + clk_enable(dfm_clk); + + /* Wait for next VSYNC */ + __raw_writel(IPUIRQ_2_MASK(IPU_IRQ_SDC_DISP3_VSYNC), + IPUIRQ_2_STATREG(IPU_IRQ_SDC_DISP3_VSYNC)); + while ((__raw_readl(IPUIRQ_2_STATREG(IPU_IRQ_SDC_DISP3_VSYNC)) & + IPUIRQ_2_MASK(IPU_IRQ_SDC_DISP3_VSYNC)) == 0) + msleep_interruptible(1); + + /* Set display clock divider to divide by 4 */ + __raw_writel(((0x8) << 22) | 0x40, DI_DISP3_TIME_CONF); + + clk_set_parent(parent_clk, dfm_clk); + + return 0; +} + +int ipu_lowpwr_display_disable(void) +{ + struct clk *parent_clk = g_ipu_clk; + + if (!in_lpdr_mode || IS_ERR(dfm_clk)) { + return -EINVAL; + } + + if (g_channel_init_mask != (1L << IPU_CHAN_ID(MEM_SDC_BG))) { + dev_err(g_ipu_dev, "LPDR mode requires only SDC BG active.\n"); + return -EINVAL; + } + + in_lpdr_mode = false; + + /* Wait for next VSYNC */ + __raw_writel(IPUIRQ_2_MASK(IPU_IRQ_SDC_DISP3_VSYNC), + IPUIRQ_2_STATREG(IPU_IRQ_SDC_DISP3_VSYNC)); + while ((__raw_readl(IPUIRQ_2_STATREG(IPU_IRQ_SDC_DISP3_VSYNC)) & + IPUIRQ_2_MASK(IPU_IRQ_SDC_DISP3_VSYNC)) == 0) + msleep_interruptible(1); + + __raw_writel(saved_disp3_time_conf, DI_DISP3_TIME_CONF); + clk_set_parent(parent_clk, default_ipu_parent_clk); + clk_disable(dfm_clk); + + return 0; +} + +static int ipu_suspend(struct platform_device *pdev, pm_message_t state) +{ + if (cpu_is_mx31() || cpu_is_mx32()) { + /* work-around for i.Mx31 SR mode after camera related test */ + if (g_csi_used) { + g_ipu_config = __raw_readl(IPU_CONF); + clk_enable(g_ipu_csi_clk); + __raw_writel(0x51, IPU_CONF); + g_channel_init_mask_backup = g_channel_init_mask; + g_channel_init_mask |= 2; + } + } + return 0; +} + +static int ipu_resume(struct platform_device *pdev) +{ + if (cpu_is_mx31() || cpu_is_mx32()) { + /* work-around for i.Mx31 SR mode after camera related test */ + if (g_csi_used) { + __raw_writel(g_ipu_config, IPU_CONF); + clk_disable(g_ipu_csi_clk); + g_channel_init_mask = g_channel_init_mask_backup; + } + } + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxcipu_driver = { + .driver = { + .name = "mxc_ipu", + }, + .probe = ipu_probe, + .suspend = ipu_suspend, + .resume = ipu_resume, +}; + +int32_t __init ipu_gen_init(void) +{ + int32_t ret; + + ret = platform_driver_register(&mxcipu_driver); + return 0; +} + +subsys_initcall(ipu_gen_init); + +static void __exit ipu_gen_uninit(void) +{ + if (g_ipu_irq[0]) + free_irq(g_ipu_irq[0], 0); + if (g_ipu_irq[1]) + free_irq(g_ipu_irq[1], 0); + + platform_driver_unregister(&mxcipu_driver); +} + +module_exit(ipu_gen_uninit); + +#ifdef CONFIG_MACH_LUIGI_LAB126 +extern spinlock_t queue_lock; + +static atomic_t ipu_lock_count = ATOMIC_INIT(0); +static atomic_t queue_lock_count = ATOMIC_INIT(0); + +void ipu_spin_lock_init(spinlock_t *lock) +{ + if (lock == &ipu_lock) { + atomic_set(&ipu_lock_count, 0); + } else if (lock == &queue_lock) { + atomic_set(&queue_lock_count, 0); + } + + spin_lock_init(lock); +} + +void IPU_SPIN_LOCK_IRQSAVE(spinlock_t *lock, unsigned long *flags) +{ + int lock_it = 0; + + if (lock == &ipu_lock) { + if (1 == atomic_inc_return(&ipu_lock_count)) { + lock_it = 1; + } + } else if (lock == &queue_lock) { + if (1 == atomic_inc_return(&queue_lock_count)) { + lock_it = 1; + } + } + + if (lock_it) { + unsigned long local_flags; + spin_lock_irqsave(lock, local_flags); + *flags = local_flags; + } +} + +void IPU_SPIN_UNLOCK_IRQRESTORE(spinlock_t *lock, unsigned long *flags) +{ + int unlock_it = 0; + + if (lock == &ipu_lock) { + if (atomic_dec_and_test(&ipu_lock_count)) { + unlock_it = 1; + } + } else if (lock == &queue_lock) { + if (atomic_dec_and_test(&queue_lock_count)) { + unlock_it = 1; + } + } + + if (unlock_it) { + unsigned long local_flags = *flags; + spin_unlock_irqrestore(lock, local_flags); + } +} +#endif + +EXPORT_SYMBOL(ipu_init_channel); +EXPORT_SYMBOL(ipu_uninit_channel); +EXPORT_SYMBOL(ipu_init_channel_buffer); +EXPORT_SYMBOL(ipu_unlink_channels); +EXPORT_SYMBOL(ipu_update_channel_buffer); +EXPORT_SYMBOL(ipu_select_buffer); +EXPORT_SYMBOL(ipu_link_channels); +EXPORT_SYMBOL(ipu_enable_channel); +EXPORT_SYMBOL(ipu_disable_channel); +EXPORT_SYMBOL(ipu_enable_irq); +EXPORT_SYMBOL(ipu_disable_irq); +EXPORT_SYMBOL(ipu_clear_irq); +EXPORT_SYMBOL(ipu_get_irq_status); +EXPORT_SYMBOL(ipu_request_irq); +EXPORT_SYMBOL(ipu_free_irq); +EXPORT_SYMBOL(ipu_pf_set_pause_row); +EXPORT_SYMBOL(bytes_per_pixel); diff -urN linux-2.6.26/drivers/mxc/ipu/ipu_csi.c linux-2.6.26-lab126/drivers/mxc/ipu/ipu_csi.c --- linux-2.6.26/drivers/mxc/ipu/ipu_csi.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu/ipu_csi.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,217 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_csi.c + * + * @brief IPU CMOS Sensor interface functions + * + * @ingroup IPU + */ +#include +#include +#include +#include +#include +#include + +#include "ipu_prv.h" +#include + +static bool gipu_csi_get_mclk_flag = false; +static int csi_mclk_flag = 0; + +extern void gpio_sensor_suspend(bool flag); + +/*! + * ipu_csi_init_interface + * Sets initial values for the CSI registers. + * The width and height of the sensor and the actual frame size will be + * set to the same values. + * @param width Sensor width + * @param height Sensor height + * @param pixel_fmt pixel format + * @param sig ipu_csi_signal_cfg_t structure + * + * @return 0 for success, -EINVAL for error + */ +int32_t +ipu_csi_init_interface(uint16_t width, uint16_t height, uint32_t pixel_fmt, + ipu_csi_signal_cfg_t sig) +{ + uint32_t data = 0; + + /* Set SENS_DATA_FORMAT bits (8 and 9) + RGB or YUV444 is 0 which is current value in data so not set explicitly + This is also the default value if attempts are made to set it to + something invalid. */ + switch (pixel_fmt) { + case IPU_PIX_FMT_UYVY: + data = CSI_SENS_CONF_DATA_FMT_YUV422; + break; + case IPU_PIX_FMT_RGB24: + case IPU_PIX_FMT_BGR24: + data = CSI_SENS_CONF_DATA_FMT_RGB_YUV444; + break; + case IPU_PIX_FMT_GENERIC: + data = CSI_SENS_CONF_DATA_FMT_BAYER; + break; + default: + return -EINVAL; + } + + /* Set the CSI_SENS_CONF register remaining fields */ + data |= sig.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT | + sig.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT | + sig.Vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT | + sig.Hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT | + sig.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT | + sig.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT | + sig.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT | + sig.sens_clksrc << CSI_SENS_CONF_SENS_CLKSRC_SHIFT; + + __raw_writel(data, CSI_SENS_CONF); + + /* Setup frame size */ + __raw_writel(width | height << 16, CSI_SENS_FRM_SIZE); + + __raw_writel(width << 16, CSI_FLASH_STROBE_1); + __raw_writel(height << 16 | 0x22, CSI_FLASH_STROBE_2); + + /* Set CCIR registers */ + if ((sig.clk_mode == IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE) || + (sig.clk_mode == IPU_CSI_CLK_MODE_CCIR656_INTERLACED)) { + __raw_writel(0x40030, CSI_CCIR_CODE_1); + __raw_writel(0xFF0000, CSI_CCIR_CODE_3); + } + + dev_dbg(g_ipu_dev, "CSI_SENS_CONF = 0x%08X\n", + __raw_readl(CSI_SENS_CONF)); + dev_dbg(g_ipu_dev, "CSI_ACT_FRM_SIZE = 0x%08X\n", + __raw_readl(CSI_ACT_FRM_SIZE)); + + return 0; +} + +/*! + * ipu_csi_flash_strobe + * + * @param flag true to turn on flash strobe + * + * @return 0 for success + */ +void ipu_csi_flash_strobe(bool flag) +{ + if (flag == true) { + __raw_writel(__raw_readl(CSI_FLASH_STROBE_2) | 0x1, + CSI_FLASH_STROBE_2); + } +} + +/*! + * ipu_csi_enable_mclk + * + * @param src enum define which source to control the clk + * CSI_MCLK_VF CSI_MCLK_ENC CSI_MCLK_RAW CSI_MCLK_I2C + * @param flag true to enable mclk, false to disable mclk + * @param wait true to wait 100ms make clock stable, false not wait + * + * @return 0 for success + */ +int32_t ipu_csi_enable_mclk(int src, bool flag, bool wait) +{ + if (flag == true) { + csi_mclk_flag |= src; + } else { + csi_mclk_flag &= ~src; + } + + if (gipu_csi_get_mclk_flag == flag) + return 0; + + if (flag == true) { + clk_enable(g_ipu_csi_clk); + if (wait == true) + msleep(10); + /*printk("enable csi clock from source %d\n", src); */ + gipu_csi_get_mclk_flag = true; + } else if (csi_mclk_flag == 0) { + clk_disable(g_ipu_csi_clk); + /*printk("disable csi clock from source %d\n", src); */ + gipu_csi_get_mclk_flag = flag; + } + + return 0; +} + +/*! + * ipu_csi_read_mclk_flag + * + * @return csi_mclk_flag + */ +int ipu_csi_read_mclk_flag(void) +{ + return csi_mclk_flag; +} + +/*! + * ipu_csi_get_window_size + * + * @param width pointer to window width + * @param height pointer to window height + * + */ +void ipu_csi_get_window_size(uint32_t * width, uint32_t * height) +{ + uint32_t reg; + + reg = __raw_readl(CSI_ACT_FRM_SIZE); + *width = (reg & 0xFFFF) + 1; + *height = (reg >> 16 & 0xFFFF) + 1; +} + +/*! + * ipu_csi_set_window_size + * + * @param width window width + * @param height window height + * + */ +void ipu_csi_set_window_size(uint32_t width, uint32_t height) +{ + __raw_writel((width - 1) | (height - 1) << 16, CSI_ACT_FRM_SIZE); +} + +/*! + * ipu_csi_set_window_pos + * + * @param left uint32 window x start + * @param top uint32 window y start + * + */ +void ipu_csi_set_window_pos(uint32_t left, uint32_t top) +{ + uint32_t temp = __raw_readl(CSI_OUT_FRM_CTRL); + temp &= 0xffff0000; + temp = top | (left << 8) | temp; + __raw_writel(temp, CSI_OUT_FRM_CTRL); +} + +/* Exported symbols for modules. */ +EXPORT_SYMBOL(ipu_csi_set_window_pos); +EXPORT_SYMBOL(ipu_csi_set_window_size); +EXPORT_SYMBOL(ipu_csi_get_window_size); +EXPORT_SYMBOL(ipu_csi_read_mclk_flag); +EXPORT_SYMBOL(ipu_csi_enable_mclk); +EXPORT_SYMBOL(ipu_csi_flash_strobe); +EXPORT_SYMBOL(ipu_csi_init_interface); diff -urN linux-2.6.26/drivers/mxc/ipu/ipu_device.c linux-2.6.26-lab126/drivers/mxc/ipu/ipu_device.c --- linux-2.6.26/drivers/mxc/ipu/ipu_device.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu/ipu_device.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,599 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_device.c + * + * @brief This file contains the IPU driver device interface and fops functions. + * + * @ingroup IPU + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ipu_prv.h" +#include +#include "ipu_param_mem.h" + +/* Strucutures and variables for exporting MXC IPU as device*/ + +#define MAX_Q_SIZE 10 + +static int mxc_ipu_major; +static struct class *mxc_ipu_class; + +DEFINE_SPINLOCK(queue_lock); +static DECLARE_MUTEX(user_mutex); + +static wait_queue_head_t waitq; +static int pending_events = 0; +int read_ptr = 0; +int write_ptr = 0; + +typedef struct _event_type { + int irq; + void *dev; +} event_type; + +event_type events[MAX_Q_SIZE]; + +int register_ipu_device(void); + +/* Static functions */ + +int get_events(event_type * p) +{ + unsigned long flags; + int ret = 0; + ipu_spin_lock_irqsave(&queue_lock, flags); + if (pending_events != 0) { + *p = events[read_ptr]; + read_ptr++; + pending_events--; + if (read_ptr >= MAX_Q_SIZE) + read_ptr = 0; + } else { + ret = -1; + } + + ipu_spin_unlock_irqrestore(&queue_lock, flags); + return ret; +} + +static irqreturn_t mxc_ipu_generic_handler(int irq, void *dev_id) +{ + event_type e; + e.irq = irq; + e.dev = dev_id; + events[write_ptr] = e; + write_ptr++; + if (write_ptr >= MAX_Q_SIZE) + write_ptr = 0; + pending_events++; + /* Wakeup any blocking user context */ + wake_up_interruptible(&waitq); + return IRQ_HANDLED; +} + +static int mxc_ipu_open(struct inode *inode, struct file *file) +{ + int ret = 0; + return ret; +} +static int mxc_ipu_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + int ret = 0; + + switch (cmd) { + + case IPU_INIT_CHANNEL: + { + ipu_channel_parm parm; + if (copy_from_user + (&parm, (ipu_channel_parm *) arg, + sizeof(ipu_channel_parm))) { + return -EFAULT; + } + if (!parm.flag) { + ret = + ipu_init_channel(parm.channel, + &parm.params); + } else { + ret = ipu_init_channel(parm.channel, NULL); + } + } + break; + + case IPU_UNINIT_CHANNEL: + { + ipu_channel_t ch; + int __user *argp = (void __user *)arg; + if (get_user(ch, argp)) + return -EFAULT; + ipu_uninit_channel(ch); + } + break; + + case IPU_INIT_CHANNEL_BUFFER: + { + ipu_channel_buf_parm parm; + if (copy_from_user + (&parm, (ipu_channel_buf_parm *) arg, + sizeof(ipu_channel_buf_parm))) { + return -EFAULT; + } + ret = + ipu_init_channel_buffer(parm.channel, parm.type, + parm.pixel_fmt, + parm.width, parm.height, + parm.stride, + parm.rot_mode, + parm.phyaddr_0, + parm.phyaddr_1, + parm.u_offset, + parm.v_offset); + + } + break; + + case IPU_UPDATE_CHANNEL_BUFFER: + { + ipu_channel_buf_parm parm; + if (copy_from_user + (&parm, (ipu_channel_buf_parm *) arg, + sizeof(ipu_channel_buf_parm))) { + return -EFAULT; + } + if ((parm.phyaddr_0 != (dma_addr_t) NULL) + && (parm.phyaddr_1 == (dma_addr_t) NULL)) { + ret = + ipu_update_channel_buffer(parm.channel, + parm.type, + parm.bufNum, + parm.phyaddr_0); + } else if ((parm.phyaddr_0 == (dma_addr_t) NULL) + && (parm.phyaddr_1 != (dma_addr_t) NULL)) { + ret = + ipu_update_channel_buffer(parm.channel, + parm.type, + parm.bufNum, + parm.phyaddr_1); + } else { + ret = -1; + } + + } + break; + case IPU_SELECT_CHANNEL_BUFFER: + { + ipu_channel_buf_parm parm; + if (copy_from_user + (&parm, (ipu_channel_buf_parm *) arg, + sizeof(ipu_channel_buf_parm))) { + return -EFAULT; + } + ret = + ipu_select_buffer(parm.channel, parm.type, + parm.bufNum); + + } + break; + case IPU_LINK_CHANNELS: + { + ipu_channel_link link; + if (copy_from_user + (&link, (ipu_channel_link *) arg, + sizeof(ipu_channel_link))) { + return -EFAULT; + } + ret = ipu_link_channels(link.src_ch, link.dest_ch); + + } + break; + case IPU_UNLINK_CHANNELS: + { + ipu_channel_link link; + if (copy_from_user + (&link, (ipu_channel_link *) arg, + sizeof(ipu_channel_link))) { + return -EFAULT; + } + ret = ipu_unlink_channels(link.src_ch, link.dest_ch); + + } + break; + case IPU_ENABLE_CHANNEL: + { + ipu_channel_t ch; + int __user *argp = (void __user *)arg; + if (get_user(ch, argp)) + return -EFAULT; + ipu_enable_channel(ch); + } + break; + case IPU_DISABLE_CHANNEL: + { + ipu_channel_info info; + if (copy_from_user + (&info, (ipu_channel_info *) arg, + sizeof(ipu_channel_info))) { + return -EFAULT; + } + ret = ipu_disable_channel(info.channel, info.stop); + } + break; + case IPU_ENABLE_IRQ: + { + uint32_t irq; + int __user *argp = (void __user *)arg; + if (get_user(irq, argp)) + return -EFAULT; + ipu_enable_irq(irq); + } + break; + case IPU_DISABLE_IRQ: + { + uint32_t irq; + int __user *argp = (void __user *)arg; + if (get_user(irq, argp)) + return -EFAULT; + ipu_disable_irq(irq); + } + break; + case IPU_CLEAR_IRQ: + { + uint32_t irq; + int __user *argp = (void __user *)arg; + if (get_user(irq, argp)) + return -EFAULT; + ipu_clear_irq(irq); + } + break; + case IPU_FREE_IRQ: + { + ipu_irq_info info; + if (copy_from_user + (&info, (ipu_irq_info *) arg, + sizeof(ipu_irq_info))) { + return -EFAULT; + } + ipu_free_irq(info.irq, info.dev_id); + } + break; + case IPU_REQUEST_IRQ_STATUS: + { + uint32_t irq; + int __user *argp = (void __user *)arg; + if (get_user(irq, argp)) + return -EFAULT; + ret = ipu_get_irq_status(irq); + } + break; + case IPU_SDC_INIT_PANEL: + { + ipu_sdc_panel_info sinfo; + if (copy_from_user + (&sinfo, (ipu_sdc_panel_info *) arg, + sizeof(ipu_sdc_panel_info))) { + return -EFAULT; + } + ret = + ipu_sdc_init_panel(sinfo.panel, sinfo.pixel_clk, + sinfo.width, sinfo.height, + sinfo.pixel_fmt, + sinfo.hStartWidth, + sinfo.hSyncWidth, + sinfo.hEndWidth, + sinfo.vStartWidth, + sinfo.vSyncWidth, + sinfo.vEndWidth, sinfo.signal); + } + break; + case IPU_SDC_SET_WIN_POS: + { + ipu_sdc_window_pos pos; + if (copy_from_user + (&pos, (ipu_sdc_window_pos *) arg, + sizeof(ipu_sdc_window_pos))) { + return -EFAULT; + } + ret = + ipu_sdc_set_window_pos(pos.channel, pos.x_pos, + pos.y_pos); + + } + break; + case IPU_SDC_SET_GLOBAL_ALPHA: + { + ipu_sdc_global_alpha g; + if (copy_from_user + (&g, (ipu_sdc_global_alpha *) arg, + sizeof(ipu_sdc_global_alpha))) { + return -EFAULT; + } + ret = ipu_sdc_set_global_alpha(g.enable, g.alpha); + } + break; + case IPU_SDC_SET_COLOR_KEY: + { + ipu_sdc_color_key c; + if (copy_from_user + (&c, (ipu_sdc_color_key *) arg, + sizeof(ipu_sdc_color_key))) { + return -EFAULT; + } + ret = + ipu_sdc_set_color_key(c.channel, c.enable, + c.colorKey); + } + break; + case IPU_SDC_SET_BRIGHTNESS: + { + uint8_t b; + int __user *argp = (void __user *)arg; + if (get_user(b, argp)) + return -EFAULT; + ret = ipu_sdc_set_brightness(b); + + } + break; + case IPU_REGISTER_GENERIC_ISR: + { + ipu_event_info info; + if (copy_from_user + (&info, (ipu_event_info *) arg, + sizeof(ipu_event_info))) { + return -EFAULT; + } + ret = + ipu_request_irq(info.irq, mxc_ipu_generic_handler, + 0, "video_sink", info.dev); + } + break; + case IPU_GET_EVENT: + /* User will have to allocate event_type structure and pass the pointer in arg */ + { + event_type ev; + int r = -1; + r = get_events(&ev); + if (r == -1) { + wait_event_interruptible(waitq, + (pending_events != 0)); + r = get_events(&ev); + } + ret = -1; + if (r == 0) { + if (!copy_to_user((event_type *) arg, &ev, + sizeof(event_type))) { + ret = 0; + } + } + } + break; + case IPU_ADC_WRITE_TEMPLATE: + { + ipu_adc_template temp; + if (copy_from_user + (&temp, (ipu_adc_template *) arg, sizeof(temp))) { + return -EFAULT; + } + ret = + ipu_adc_write_template(temp.disp, temp.pCmd, + temp.write); + } + break; + case IPU_ADC_UPDATE: + { + ipu_adc_update update; + if (copy_from_user + (&update, (ipu_adc_update *) arg, sizeof(update))) { + return -EFAULT; + } + ret = + ipu_adc_set_update_mode(update.channel, update.mode, + update.refresh_rate, + update.addr, update.size); + } + break; + case IPU_ADC_SNOOP: + { + ipu_adc_snoop snoop; + if (copy_from_user + (&snoop, (ipu_adc_snoop *) arg, sizeof(snoop))) { + return -EFAULT; + } + ret = + ipu_adc_get_snooping_status(snoop.statl, + snoop.stath); + } + break; + case IPU_ADC_CMD: + { + ipu_adc_cmd cmd; + if (copy_from_user + (&cmd, (ipu_adc_cmd *) arg, sizeof(cmd))) { + return -EFAULT; + } + ret = + ipu_adc_write_cmd(cmd.disp, cmd.type, cmd.cmd, + cmd.params, cmd.numParams); + } + break; + case IPU_ADC_INIT_PANEL: + { + ipu_adc_panel panel; + if (copy_from_user + (&panel, (ipu_adc_panel *) arg, sizeof(panel))) { + return -EFAULT; + } + ret = + ipu_adc_init_panel(panel.disp, panel.width, + panel.height, panel.pixel_fmt, + panel.stride, panel.signal, + panel.addr, panel.vsync_width, + panel.mode); + } + break; + case IPU_ADC_IFC_TIMING: + { + ipu_adc_ifc_timing t; + if (copy_from_user + (&t, (ipu_adc_ifc_timing *) arg, sizeof(t))) { + return -EFAULT; + } + ret = + ipu_adc_init_ifc_timing(t.disp, t.read, + t.cycle_time, t.up_time, + t.down_time, + t.read_latch_time, + t.pixel_clk); + } + break; + case IPU_CSI_INIT_INTERFACE: + { + ipu_csi_interface c; + if (copy_from_user + (&c, (ipu_csi_interface *) arg, sizeof(c))) + return -EFAULT; + ret = + ipu_csi_init_interface(c.width, c.height, + c.pixel_fmt, c.signal); + } + break; + case IPU_CSI_ENABLE_MCLK: + { + ipu_csi_mclk m; + if (copy_from_user(&m, (ipu_csi_mclk *) arg, sizeof(m))) + return -EFAULT; + ret = ipu_csi_enable_mclk(m.src, m.flag, m.wait); + } + break; + case IPU_CSI_READ_MCLK_FLAG: + { + ret = ipu_csi_read_mclk_flag(); + } + break; + case IPU_CSI_FLASH_STROBE: + { + bool strobe; + int __user *argp = (void __user *)arg; + if (get_user(strobe, argp)) + return -EFAULT; + ipu_csi_flash_strobe(strobe); + } + break; + case IPU_CSI_GET_WIN_SIZE: + { + ipu_csi_window_size w; + ipu_csi_get_window_size(&w.width, &w.height); + if (copy_to_user + ((ipu_csi_window_size *) arg, &w, sizeof(w))) + return -EFAULT; + } + break; + case IPU_CSI_SET_WIN_SIZE: + { + ipu_csi_window_size w; + if (copy_from_user + (&w, (ipu_csi_window_size *) arg, sizeof(w))) + return -EFAULT; + ipu_csi_set_window_size(w.width, w.height); + } + break; + case IPU_CSI_SET_WINDOW: + { + ipu_csi_window p; + if (copy_from_user + (&p, (ipu_csi_window *) arg, sizeof(p))) + return -EFAULT; + ipu_csi_set_window_pos(p.left, p.top); + } + break; + case IPU_PF_SET_PAUSE_ROW: + { + uint32_t p; + int __user *argp = (void __user *)arg; + if (get_user(p, argp)) + return -EFAULT; + ret = ipu_pf_set_pause_row(p); + } + break; + default: + break; + + } + return ret; +} + +static int mxc_ipu_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static struct file_operations mxc_ipu_fops = { + .owner = THIS_MODULE, + .open = mxc_ipu_open, + .release = mxc_ipu_release, + .ioctl = mxc_ipu_ioctl +}; + +int register_ipu_device() +{ + int ret = 0; + struct device *temp; + mxc_ipu_major = register_chrdev(0, "mxc_ipu", &mxc_ipu_fops); + if (mxc_ipu_major < 0) { + printk(KERN_ERR + "Unable to register Mxc Ipu as a char device\n"); + return mxc_ipu_major; + } + + mxc_ipu_class = class_create(THIS_MODULE, "mxc_ipu"); + if (IS_ERR(mxc_ipu_class)) { + printk(KERN_ERR "Unable to create class for Mxc Ipu\n"); + ret = PTR_ERR(mxc_ipu_class); + goto err1; + } + + temp = device_create(mxc_ipu_class, NULL, MKDEV(mxc_ipu_major, 0), + "mxc_ipu"); + + if (IS_ERR(temp)) { + printk(KERN_ERR "Unable to create class device for Mxc Ipu\n"); + ret = PTR_ERR(temp); + goto err2; + } + ipu_spin_lock_init(&queue_lock); + init_waitqueue_head(&waitq); + return ret; + + err2: + class_destroy(mxc_ipu_class); + err1: + unregister_chrdev(mxc_ipu_major, "mxc_ipu"); + return ret; + +} diff -urN linux-2.6.26/drivers/mxc/ipu/ipu_ic.c linux-2.6.26-lab126/drivers/mxc/ipu/ipu_ic.c --- linux-2.6.26/drivers/mxc/ipu/ipu_ic.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu/ipu_ic.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,592 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * @file ipu_ic.c + * + * @brief IPU IC functions + * + * @ingroup IPU + */ +#include +#include +#include +#include +#include +#include + +#include "ipu_prv.h" +#include +#include "ipu_param_mem.h" + +enum { + IC_TASK_VIEWFINDER, + IC_TASK_ENCODER, + IC_TASK_POST_PROCESSOR +}; + +extern int g_ipu_hw_rev; +static void _init_csc(uint8_t ic_task, ipu_color_space_t in_format, + ipu_color_space_t out_format); +static bool _calc_resize_coeffs(uint32_t inSize, uint32_t outSize, + uint32_t * resizeCoeff, + uint32_t * downsizeCoeff); + +void _ipu_ic_enable_task(ipu_channel_t channel) +{ + uint32_t ic_conf; + + ic_conf = __raw_readl(IC_CONF); + switch (channel) { + case CSI_PRP_VF_ADC: + case MEM_PRP_VF_ADC: + case CSI_PRP_VF_MEM: + case MEM_PRP_VF_MEM: + ic_conf |= IC_CONF_PRPVF_EN; + break; + case MEM_ROT_VF_MEM: + ic_conf |= IC_CONF_PRPVF_ROT_EN; + break; + case CSI_PRP_ENC_MEM: + case MEM_PRP_ENC_MEM: + ic_conf |= IC_CONF_PRPENC_EN; + break; + case MEM_ROT_ENC_MEM: + ic_conf |= IC_CONF_PRPENC_ROT_EN; + break; + case MEM_PP_ADC: + case MEM_PP_MEM: + ic_conf |= IC_CONF_PP_EN; + break; + case MEM_ROT_PP_MEM: + ic_conf |= IC_CONF_PP_ROT_EN; + break; + case CSI_MEM: + // ??? + ic_conf |= IC_CONF_RWS_EN | IC_CONF_PRPENC_EN; + break; + default: + break; + } + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_ic_disable_task(ipu_channel_t channel) +{ + uint32_t ic_conf; + + ic_conf = __raw_readl(IC_CONF); + switch (channel) { + case CSI_PRP_VF_ADC: + case MEM_PRP_VF_ADC: + case CSI_PRP_VF_MEM: + case MEM_PRP_VF_MEM: + ic_conf &= ~IC_CONF_PRPVF_EN; + break; + case MEM_ROT_VF_MEM: + ic_conf &= ~IC_CONF_PRPVF_ROT_EN; + break; + case CSI_PRP_ENC_MEM: + case MEM_PRP_ENC_MEM: + ic_conf &= ~IC_CONF_PRPENC_EN; + break; + case MEM_ROT_ENC_MEM: + ic_conf &= ~IC_CONF_PRPENC_ROT_EN; + break; + case MEM_PP_ADC: + case MEM_PP_MEM: + ic_conf &= ~IC_CONF_PP_EN; + break; + case MEM_ROT_PP_MEM: + ic_conf &= ~IC_CONF_PP_ROT_EN; + break; + case CSI_MEM: + // ??? + ic_conf &= ~(IC_CONF_RWS_EN | IC_CONF_PRPENC_EN); + break; + default: + break; + } + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_ic_init_prpvf(ipu_channel_params_t * params, bool src_is_csi) +{ + uint32_t reg, ic_conf; + uint32_t downsizeCoeff, resizeCoeff; + ipu_color_space_t in_fmt, out_fmt; + + /* Setup vertical resizing */ + _calc_resize_coeffs(params->mem_prp_vf_mem.in_height, + params->mem_prp_vf_mem.out_height, + &resizeCoeff, &downsizeCoeff); + reg = (downsizeCoeff << 30) | (resizeCoeff << 16); + + /* Setup horizontal resizing */ + _calc_resize_coeffs(params->mem_prp_vf_mem.in_width, + params->mem_prp_vf_mem.out_width, + &resizeCoeff, &downsizeCoeff); + reg |= (downsizeCoeff << 14) | resizeCoeff; + + __raw_writel(reg, IC_PRP_VF_RSC); + + ic_conf = __raw_readl(IC_CONF); + + /* Setup color space conversion */ + in_fmt = format_to_colorspace(params->mem_prp_vf_mem.in_pixel_fmt); + out_fmt = format_to_colorspace(params->mem_prp_vf_mem.out_pixel_fmt); + if (in_fmt == RGB) { + if ((out_fmt == YCbCr) || (out_fmt == YUV)) { + _init_csc(IC_TASK_VIEWFINDER, RGB, out_fmt); + ic_conf |= IC_CONF_PRPVF_CSC1; /* Enable RGB->YCBCR CSC */ + } + } + if ((in_fmt == YCbCr) || (in_fmt == YUV)) { + if (out_fmt == RGB) { + _init_csc(IC_TASK_VIEWFINDER, YCbCr, RGB); + ic_conf |= IC_CONF_PRPVF_CSC1; /* Enable YCBCR->RGB CSC */ + } else { + /* TODO: Support YUV<->YCbCr conversion? */ + } + } + + if (params->mem_prp_vf_mem.graphics_combine_en) { + ic_conf |= IC_CONF_PRPVF_CMB; + + /* need transparent CSC1 conversion */ + _init_csc(IC_TASK_POST_PROCESSOR, RGB, RGB); + ic_conf |= IC_CONF_PRPVF_CSC1; /* Enable RGB->RGB CSC */ + + if (params->mem_prp_vf_mem.global_alpha_en) { + ic_conf |= IC_CONF_IC_GLB_LOC_A; + } else { + ic_conf &= ~IC_CONF_IC_GLB_LOC_A; + } + + if (params->mem_prp_vf_mem.key_color_en) { + ic_conf |= IC_CONF_KEY_COLOR_EN; + } else { + ic_conf &= ~IC_CONF_KEY_COLOR_EN; + } + } else { + ic_conf &= ~IC_CONF_PP_CMB; + } + +#ifndef CONFIG_VIRTIO_SUPPORT /* Setting RWS_EN doesn't work in Virtio */ + if (src_is_csi) { + ic_conf &= ~IC_CONF_RWS_EN; + } else { + ic_conf |= IC_CONF_RWS_EN; + } +#endif + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_ic_uninit_prpvf(void) +{ + uint32_t reg; + + reg = __raw_readl(IC_CONF); + reg &= ~(IC_CONF_PRPVF_EN | IC_CONF_PRPVF_CMB | + IC_CONF_PRPVF_CSC2 | IC_CONF_PRPVF_CSC1); + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_rotate_vf(ipu_channel_params_t * params) +{ +} + +void _ipu_ic_uninit_rotate_vf(void) +{ + uint32_t reg; + reg = __raw_readl(IC_CONF); + reg &= ~IC_CONF_PRPVF_ROT_EN; + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_csi(ipu_channel_params_t * params) +{ + uint32_t reg; + reg = __raw_readl(IC_CONF); + reg &= ~IC_CONF_CSI_MEM_WR_EN; + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_uninit_csi(void) +{ + uint32_t reg; + reg = __raw_readl(IC_CONF); + reg &= ~(IC_CONF_RWS_EN | IC_CONF_PRPENC_EN); + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_prpenc(ipu_channel_params_t * params, bool src_is_csi) +{ + uint32_t reg, ic_conf; + uint32_t downsizeCoeff, resizeCoeff; + ipu_color_space_t in_fmt, out_fmt; + + /* Setup vertical resizing */ + _calc_resize_coeffs(params->mem_prp_enc_mem.in_height, + params->mem_prp_enc_mem.out_height, + &resizeCoeff, &downsizeCoeff); + reg = (downsizeCoeff << 30) | (resizeCoeff << 16); + + /* Setup horizontal resizing */ + _calc_resize_coeffs(params->mem_prp_enc_mem.in_width, + params->mem_prp_enc_mem.out_width, + &resizeCoeff, &downsizeCoeff); + reg |= (downsizeCoeff << 14) | resizeCoeff; + + __raw_writel(reg, IC_PRP_ENC_RSC); + + ic_conf = __raw_readl(IC_CONF); + + /* Setup color space conversion */ + in_fmt = format_to_colorspace(params->mem_prp_enc_mem.in_pixel_fmt); + out_fmt = format_to_colorspace(params->mem_prp_enc_mem.out_pixel_fmt); + if (in_fmt == RGB) { + if ((out_fmt == YCbCr) || (out_fmt == YUV)) { + /* TODO: ERROR! */ + } + } + if ((in_fmt == YCbCr) || (in_fmt == YUV)) { + if (out_fmt == RGB) { + _init_csc(IC_TASK_ENCODER, YCbCr, RGB); + ic_conf |= IC_CONF_PRPENC_CSC1; /* Enable YCBCR->RGB CSC */ + } else { + /* TODO: Support YUV<->YCbCr conversion? */ + } + } + + if (src_is_csi) { + ic_conf &= ~IC_CONF_RWS_EN; + } else { + ic_conf |= IC_CONF_RWS_EN; + } + + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_ic_uninit_prpenc(void) +{ + uint32_t reg; + + reg = __raw_readl(IC_CONF); + reg &= ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1); + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_rotate_enc(ipu_channel_params_t * params) +{ +} + +void _ipu_ic_uninit_rotate_enc(void) +{ + uint32_t reg; + + reg = __raw_readl(IC_CONF); + reg &= ~(IC_CONF_PRPENC_ROT_EN); + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_pp(ipu_channel_params_t * params) +{ + uint32_t reg, ic_conf; + uint32_t downsizeCoeff, resizeCoeff; + ipu_color_space_t in_fmt, out_fmt; + + /* Setup vertical resizing */ + _calc_resize_coeffs(params->mem_pp_mem.in_height, + params->mem_pp_mem.out_height, + &resizeCoeff, &downsizeCoeff); + reg = (downsizeCoeff << 30) | (resizeCoeff << 16); + + /* Setup horizontal resizing */ + _calc_resize_coeffs(params->mem_pp_mem.in_width, + params->mem_pp_mem.out_width, + &resizeCoeff, &downsizeCoeff); + reg |= (downsizeCoeff << 14) | resizeCoeff; + + __raw_writel(reg, IC_PP_RSC); + + ic_conf = __raw_readl(IC_CONF); + + /* Setup color space conversion */ + in_fmt = format_to_colorspace(params->mem_pp_mem.in_pixel_fmt); + out_fmt = format_to_colorspace(params->mem_pp_mem.out_pixel_fmt); + if (in_fmt == RGB) { + if ((out_fmt == YCbCr) || (out_fmt == YUV)) { + _init_csc(IC_TASK_POST_PROCESSOR, RGB, out_fmt); + ic_conf |= IC_CONF_PP_CSC2; /* Enable RGB->YCBCR CSC */ + } + } + if ((in_fmt == YCbCr) || (in_fmt == YUV)) { + if (out_fmt == RGB) { + _init_csc(IC_TASK_POST_PROCESSOR, YCbCr, RGB); + ic_conf |= IC_CONF_PP_CSC1; /* Enable YCBCR->RGB CSC */ + } else { + /* TODO: Support YUV<->YCbCr conversion? */ + } + } + + if (params->mem_pp_mem.graphics_combine_en) { + ic_conf |= IC_CONF_PP_CMB; + + /* need transparent CSC1 conversion */ + _init_csc(IC_TASK_POST_PROCESSOR, RGB, RGB); + ic_conf |= IC_CONF_PP_CSC1; /* Enable RGB->RGB CSC */ + + if (params->mem_pp_mem.global_alpha_en) { + ic_conf |= IC_CONF_IC_GLB_LOC_A; + } else { + ic_conf &= ~IC_CONF_IC_GLB_LOC_A; + } + + if (params->mem_pp_mem.key_color_en) { + ic_conf |= IC_CONF_KEY_COLOR_EN; + } else { + ic_conf &= ~IC_CONF_KEY_COLOR_EN; + } + } else { + ic_conf &= ~IC_CONF_PP_CMB; + } + + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_ic_uninit_pp(void) +{ + uint32_t reg; + + reg = __raw_readl(IC_CONF); + reg &= ~(IC_CONF_PP_EN | IC_CONF_PP_CSC1 | IC_CONF_PP_CSC2 | + IC_CONF_PP_CMB); + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_rotate_pp(ipu_channel_params_t * params) +{ +} + +void _ipu_ic_uninit_rotate_pp(void) +{ + uint32_t reg; + reg = __raw_readl(IC_CONF); + reg &= ~IC_CONF_PP_ROT_EN; + __raw_writel(reg, IC_CONF); +} + +static void _init_csc(uint8_t ic_task, ipu_color_space_t in_format, + ipu_color_space_t out_format) +{ +/* Y = R * .299 + G * .587 + B * .114; + U = R * -.169 + G * -.332 + B * .500 + 128.; + V = R * .500 + G * -.419 + B * -.0813 + 128.;*/ + static const uint32_t rgb2ycbcr_coeff[4][3] = { + {0x004D, 0x0096, 0x001D}, + {0x01D5, 0x01AB, 0x0080}, + {0x0080, 0x0195, 0x01EB}, + {0x0000, 0x0200, 0x0200}, /* A0, A1, A2 */ + }; + + /* transparent RGB->RGB matrix for combining + */ + static const uint32_t rgb2rgb_coeff[4][3] = { + {0x0080, 0x0000, 0x0000}, + {0x0000, 0x0080, 0x0000}, + {0x0000, 0x0000, 0x0080}, + {0x0000, 0x0000, 0x0000}, /* A0, A1, A2 */ + }; + +/* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128)); + G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128)); + B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */ + static const uint32_t ycbcr2rgb_coeff[4][3] = { + {149, 0, 204}, + {149, 462, 408}, + {149, 255, 0}, + {8192 - 446, 266, 8192 - 554}, /* A0, A1, A2 */ + }; + + uint32_t param[2]; + uint32_t address = 0; + + if (g_ipu_hw_rev > 1) { + if (ic_task == IC_TASK_VIEWFINDER) { + address = 0x645 << 3; + } else if (ic_task == IC_TASK_ENCODER) { + address = 0x321 << 3; + } else if (ic_task == IC_TASK_POST_PROCESSOR) { + address = 0x96C << 3; + } else { + BUG(); + } + } else { + if (ic_task == IC_TASK_VIEWFINDER) { + address = 0x5a5 << 3; + } else if (ic_task == IC_TASK_ENCODER) { + address = 0x2d1 << 3; + } else if (ic_task == IC_TASK_POST_PROCESSOR) { + address = 0x87c << 3; + } else { + BUG(); + } + } + + if ((in_format == YCbCr) && (out_format == RGB)) { + /* Init CSC1 (YCbCr->RGB) */ + param[0] = + (ycbcr2rgb_coeff[3][0] << 27) | (ycbcr2rgb_coeff[0][0] << + 18) | + (ycbcr2rgb_coeff[1][1] << 9) | ycbcr2rgb_coeff[2][2]; + /* scale = 2, sat = 0 */ + param[1] = (ycbcr2rgb_coeff[3][0] >> 5) | (2L << (40 - 32)); + _ipu_write_param_mem(address, param, 2); + dev_dbg(g_ipu_dev, + "addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n", + address, param[0], param[1]); + + param[0] = + (ycbcr2rgb_coeff[3][1] << 27) | (ycbcr2rgb_coeff[0][1] << + 18) | + (ycbcr2rgb_coeff[1][0] << 9) | ycbcr2rgb_coeff[2][0]; + param[1] = (ycbcr2rgb_coeff[3][1] >> 5); + address += 1L << 3; + _ipu_write_param_mem(address, param, 2); + dev_dbg(g_ipu_dev, + "addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n", + address, param[0], param[1]); + + param[0] = + (ycbcr2rgb_coeff[3][2] << 27) | (ycbcr2rgb_coeff[0][2] << + 18) | + (ycbcr2rgb_coeff[1][2] << 9) | ycbcr2rgb_coeff[2][1]; + param[1] = (ycbcr2rgb_coeff[3][2] >> 5); + address += 1L << 3; + _ipu_write_param_mem(address, param, 2); + dev_dbg(g_ipu_dev, + "addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n", + address, param[0], param[1]); + } else if ((in_format == RGB) && (out_format == YCbCr)) { + /* Init CSC1 (RGB->YCbCr) */ + param[0] = + (rgb2ycbcr_coeff[3][0] << 27) | (rgb2ycbcr_coeff[0][0] << + 18) | + (rgb2ycbcr_coeff[1][1] << 9) | rgb2ycbcr_coeff[2][2]; + /* scale = 1, sat = 0 */ + param[1] = (rgb2ycbcr_coeff[3][0] >> 5) | (1UL << 8); + _ipu_write_param_mem(address, param, 2); + dev_dbg(g_ipu_dev, + "addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n", + address, param[0], param[1]); + + param[0] = + (rgb2ycbcr_coeff[3][1] << 27) | (rgb2ycbcr_coeff[0][1] << + 18) | + (rgb2ycbcr_coeff[1][0] << 9) | rgb2ycbcr_coeff[2][0]; + param[1] = (rgb2ycbcr_coeff[3][1] >> 5); + address += 1L << 3; + _ipu_write_param_mem(address, param, 2); + dev_dbg(g_ipu_dev, + "addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n", + address, param[0], param[1]); + + param[0] = + (rgb2ycbcr_coeff[3][2] << 27) | (rgb2ycbcr_coeff[0][2] << + 18) | + (rgb2ycbcr_coeff[1][2] << 9) | rgb2ycbcr_coeff[2][1]; + param[1] = (rgb2ycbcr_coeff[3][2] >> 5); + address += 1L << 3; + _ipu_write_param_mem(address, param, 2); + dev_dbg(g_ipu_dev, + "addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n", + address, param[0], param[1]); + } else if ((in_format == RGB) && (out_format == RGB)) { + /* Init CSC1 */ + param[0] = + (rgb2rgb_coeff[3][0] << 27) | (rgb2rgb_coeff[0][0] << 18) | + (rgb2rgb_coeff[1][1] << 9) | rgb2rgb_coeff[2][2]; + /* scale = 2, sat = 0 */ + param[1] = (rgb2rgb_coeff[3][0] >> 5) | (2UL << 8); + + _ipu_write_param_mem(address, param, 2); + + dev_dbg(g_ipu_dev, + "addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n", + address, param[0], param[1]); + + param[0] = + (rgb2rgb_coeff[3][1] << 27) | (rgb2rgb_coeff[0][1] << 18) | + (rgb2rgb_coeff[1][0] << 9) | rgb2rgb_coeff[2][0]; + param[1] = (rgb2rgb_coeff[3][1] >> 5); + + address += 1L << 3; + _ipu_write_param_mem(address, param, 2); + + dev_dbg(g_ipu_dev, + "addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n", + address, param[0], param[1]); + + param[0] = + (rgb2rgb_coeff[3][2] << 27) | (rgb2rgb_coeff[0][2] << 18) | + (rgb2rgb_coeff[1][2] << 9) | rgb2rgb_coeff[2][1]; + param[1] = (rgb2rgb_coeff[3][2] >> 5); + + address += 1L << 3; + _ipu_write_param_mem(address, param, 2); + + dev_dbg(g_ipu_dev, + "addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n", + address, param[0], param[1]); + } else { + dev_err(g_ipu_dev, "Unsupported color space conversion\n"); + } +} + +static bool _calc_resize_coeffs(uint32_t inSize, uint32_t outSize, + uint32_t * resizeCoeff, + uint32_t * downsizeCoeff) +{ + uint32_t tempSize; + uint32_t tempDownsize; + + /* Cannot downsize more than 8:1 */ + if ((outSize << 3) < inSize) { + return false; + } + /* compute downsizing coefficient */ + tempDownsize = 0; + tempSize = inSize; + while ((tempSize >= outSize * 2) && (tempDownsize < 2)) { + tempSize >>= 1; + tempDownsize++; + } + *downsizeCoeff = tempDownsize; + + /* compute resizing coefficient using the following equation: + resizeCoeff = M*(SI -1)/(SO - 1) + where M = 2^13, SI - input size, SO - output size */ + *resizeCoeff = (8192L * (tempSize - 1)) / (outSize - 1); + if (*resizeCoeff >= 16384L) { + dev_err(g_ipu_dev, "Warning! Overflow on resize coeff.\n"); + *resizeCoeff = 0x3FFF; + } + + dev_dbg(g_ipu_dev, "resizing from %u -> %u pixels, " + "downsize=%u, resize=%u.%lu (reg=%u)\n", inSize, outSize, + *downsizeCoeff, (*resizeCoeff >= 8192L) ? 1 : 0, + ((*resizeCoeff & 0x1FFF) * 10000L) / 8192L, *resizeCoeff); + + return true; +} diff -urN linux-2.6.26/drivers/mxc/ipu/ipu_l126_detect.c linux-2.6.26-lab126/drivers/mxc/ipu/ipu_l126_detect.c --- linux-2.6.26/drivers/mxc/ipu/ipu_l126_detect.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu/ipu_l126_detect.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,193 @@ +/* + * linux/drivers/mxc/ipu/ipu_l126_detect.c -- + * Lab126 specific controller early detection + * + * Copyright (C) 2005-2009 Amazon Technologies + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#include +#include +#include +#include +#include +#include +#include "../../video/eink/broadsheet/broadsheet_def.h" +#include "../../video/eink/auo/auo_def.h" + +/* Controller detect routines should be of the following type */ +typedef int (*ipu_controller_detect_t)(void); + +/* Forward declarations for all controller detect routines */ +static int ipu_test_broadsheet(void); +static int ipu_test_auo(void); + +/* Enum for controller type */ +enum ipu_controller_t { + IPU_CONTROLLER_UNINIT = -1, + IPU_CONTROLLER_UNKNOWN = 0, + IPU_CONTROLLER_BS = 1, + IPU_CONTROLLER_AUO = 2, + /* Add more controllers here */ + IPU_CONTROLLER_TOTAL , +}; + +/* Structure which stores all the controllers to check for */ +static struct { + char *controller_name; + ipu_controller_detect_t controller_detect; +} ipu_controllers[] = { + [IPU_CONTROLLER_UNKNOWN] = {"emu", NULL}, /* emu controller is the default + and should always be the at the + zero location */ + [IPU_CONTROLLER_BS] = {"broadsheet", ipu_test_broadsheet}, + [IPU_CONTROLLER_AUO] = {"auo", ipu_test_auo}, + /* add more controllers here */ +}; + +/* Variable which stores which controller is detected */ +static enum ipu_controller_t controller_type = IPU_CONTROLLER_UNINIT; + +/* All controller detection routines here */ +static int ipu_test_broadsheet(void) { + u16 product_id = 0; + int result = EINKFB_FAILURE; + + controller_properties_t broad_props; + + BROADSHEET_CONFIG_CONTROLLER_PROPS(broad_props, NULL, NULL); + + if (controller_hw_init(false, &broad_props)) { + // Read the product id + + // send the ipu read register command + result = controller_wr_cmd(bs_cmd_RD_REG, false); + // send the register to read + if (EINKFB_SUCCESS == result) { + u16 reg = BS_PRD_CODE_REG; + result = controller_wr_dat(CONTROLLER_COMMON_WR_DAT_ARGS, 1, ®); + } + // read product code + if (EINKFB_SUCCESS == result) { + result = controller_rd_one(&product_id); + } + + if (EINKFB_SUCCESS == result && + (BS_PRD_CODE_ISIS == product_id || BS_PRD_CODE == product_id)) { + // it's an isis / broadsheet + result = EINKFB_SUCCESS; + } else { + result = EINKFB_FAILURE; + } + } + + // uninit the controller and ipu + controller_hw_done(); + + return result; +} + +static int ipu_test_auo(void) { + u16 product_id = 0; + u16 temp = 0; + int result = EINKFB_FAILURE; + controller_properties_t auo_props; + AUO_CONFIG_CONTROLLER_PROPS(auo_props, + AUO_SCREEN_WIDTH, + AUO_SCREEN_HEIGHT, + AUO_SCREEN_BPP, + NULL, + NULL); + + if (controller_hw_init(false, &auo_props)) { + // Read the product id + + // send the AUO read version cmd + result = controller_wr_cmd(AUO_READ_VERSION, false); + + // read the 1st parameter temp (ignore) + if (EINKFB_SUCCESS == result) { + result = controller_rd_one(&temp); + } + + // read the 2nd parameter EPD type (ignore) + if (EINKFB_SUCCESS == result) { + result = controller_rd_one(&temp); + } + + // read the 3rd parameter Panel/Product type (save) + if (EINKFB_SUCCESS == result) { + result = controller_rd_one(&product_id); + } + + // read the 4th parameter LUT version (ignore) + if (EINKFB_SUCCESS == result) { + result = controller_rd_one(&temp); + } + + if (EINKFB_SUCCESS == result && + (0 == product_id || AUO_PRD_CODE_2 == product_id || AUO_PRD_CODE_3 == product_id)) { + // it's an auo + result = EINKFB_SUCCESS; + } else { + result = EINKFB_FAILURE; + } + } + + // uninit the controller and ipu + controller_hw_done(); + + return result; +} +/* End of controller detection routines */ + +static int ipu_controller_type(void) { + if (IPU_CONTROLLER_UNINIT == controller_type) { + // controller type is not detected yet + // do it. + int i; + + // Go through all the controllers + for (i = 1; i < IPU_CONTROLLER_TOTAL; ++i) { + if (ipu_controllers[i].controller_detect && + EINKFB_SUCCESS == ipu_controllers[i].controller_detect()) { + break; + } + } + + if (i == IPU_CONTROLLER_TOTAL) { + // set to emu controller + i = IPU_CONTROLLER_UNKNOWN; + } + + // If we could not find any controller i will be == 0, which is emu + // else i will be some number which denotes the controller detected. + controller_type = i; + einkfb_print_info("Detected %s controller\n", ipu_controllers[i].controller_name); + } + + return controller_type; +} + +// /sys/devices/platform/mxc_ipu/eink_controller_type (read) +// +static ssize_t show_eink_controller_type(struct device *dev, struct device_attribute *attr, char *buf) { + return ( sprintf(buf, "%d\n", ipu_controller_type()) ); +} +static DEVICE_ATTR(eink_controller_type, S_IRUGO, show_eink_controller_type, NULL); + +int _ipu_l126_detect_init(struct platform_device *dev) { + int unused; + // create sysfs entry + unused = device_create_file(&dev->dev, &dev_attr_eink_controller_type); + + return EINKFB_SUCCESS; +} + +void _ipu_l126_detect_done(struct platform_device *dev) { + device_remove_file(&dev->dev, &dev_attr_eink_controller_type); +} + diff -urN linux-2.6.26/drivers/mxc/ipu/ipu_param_mem.h linux-2.6.26-lab126/drivers/mxc/ipu/ipu_param_mem.h --- linux-2.6.26/drivers/mxc/ipu/ipu_param_mem.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu/ipu_param_mem.h 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,176 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __INCLUDE_IPU_PARAM_MEM_H__ +#define __INCLUDE_IPU_PARAM_MEM_H__ + +#include + +static __inline void _ipu_ch_param_set_size(uint32_t * params, + uint32_t pixel_fmt, uint16_t width, + uint16_t height, uint16_t stride, + uint32_t u, uint32_t v) +{ + uint32_t u_offset = 0; + uint32_t v_offset = 0; + memset(params, 0, 40); + + params[3] = + (uint32_t) ((width - 1) << 12) | ((uint32_t) (height - 1) << 24); + params[4] = (uint32_t) (height - 1) >> 8; + params[7] = (uint32_t) (stride - 1) << 3; + + switch (pixel_fmt) { + case IPU_PIX_FMT_GENERIC: + /*Represents 8-bit Generic data */ + params[7] |= 3 | (7UL << (81 - 64)) | (31L << (89 - 64)); /* BPP & PFS */ + params[8] = 2; /* SAT = use 32-bit access */ + break; + case IPU_PIX_FMT_GENERIC_32: + /*Represents 32-bit Generic data */ + params[7] |= (7UL << (81 - 64)) | (7L << (89 - 64)); /* BPP & PFS */ + params[8] = 2; /* SAT = use 32-bit access */ + break; + case IPU_PIX_FMT_RGB565: + params[7] |= 2L | (4UL << (81 - 64)) | (7L << (89 - 64)); /* BPP & PFS */ + params[8] = 2 | /* SAT = 32-bit access */ + (0UL << (99 - 96)) | /* Red bit offset */ + (5UL << (104 - 96)) | /* Green bit offset */ + (11UL << (109 - 96)) | /* Blue bit offset */ + (16UL << (114 - 96)) | /* Alpha bit offset */ + (4UL << (119 - 96)) | /* Red bit width - 1 */ + (5UL << (122 - 96)) | /* Green bit width - 1 */ + (4UL << (125 - 96)); /* Blue bit width - 1 */ + break; + case IPU_PIX_FMT_BGR24: /* 24 BPP & RGB PFS */ + params[7] |= 1 | (4UL << (81 - 64)) | (7L << (89 - 64)); + params[8] = 2 | /* SAT = 32-bit access */ + (8UL << (104 - 96)) | /* Green bit offset */ + (16UL << (109 - 96)) | /* Blue bit offset */ + (24UL << (114 - 96)) | /* Alpha bit offset */ + (7UL << (119 - 96)) | /* Red bit width - 1 */ + (7UL << (122 - 96)) | /* Green bit width - 1 */ + (uint32_t) (7UL << (125 - 96)); /* Blue bit width - 1 */ + break; + case IPU_PIX_FMT_RGB24: /* 24 BPP & RGB PFS */ + params[7] |= 1 | (4UL << (81 - 64)) | (7L << (89 - 64)); + params[8] = 2 | /* SAT = 32-bit access */ + (16UL << (99 - 96)) | /* Red bit offset */ + (8UL << (104 - 96)) | /* Green bit offset */ + (0UL << (109 - 96)) | /* Blue bit offset */ + (24UL << (114 - 96)) | /* Alpha bit offset */ + (7UL << (119 - 96)) | /* Red bit width - 1 */ + (7UL << (122 - 96)) | /* Green bit width - 1 */ + (uint32_t) (7UL << (125 - 96)); /* Blue bit width - 1 */ + break; + case IPU_PIX_FMT_BGRA32: + case IPU_PIX_FMT_BGR32: + /* BPP & pixel fmt */ + params[7] |= 0 | (4UL << (81 - 64)) | (7 << (89 - 64)); + params[8] = 2 | /* SAT = 32-bit access */ + (8UL << (99 - 96)) | /* Red bit offset */ + (16UL << (104 - 96)) | /* Green bit offset */ + (24UL << (109 - 96)) | /* Blue bit offset */ + (0UL << (114 - 96)) | /* Alpha bit offset */ + (7UL << (119 - 96)) | /* Red bit width - 1 */ + (7UL << (122 - 96)) | /* Green bit width - 1 */ + (uint32_t) (7UL << (125 - 96)); /* Blue bit width - 1 */ + params[9] = 7; /* Alpha bit width - 1 */ + break; + case IPU_PIX_FMT_RGBA32: + case IPU_PIX_FMT_RGB32: + /* BPP & pixel fmt */ + params[7] |= 0 | (4UL << (81 - 64)) | (7 << (89 - 64)); + params[8] = 2 | /* SAT = 32-bit access */ + (24UL << (99 - 96)) | /* Red bit offset */ + (16UL << (104 - 96)) | /* Green bit offset */ + (8UL << (109 - 96)) | /* Blue bit offset */ + (0UL << (114 - 96)) | /* Alpha bit offset */ + (7UL << (119 - 96)) | /* Red bit width - 1 */ + (7UL << (122 - 96)) | /* Green bit width - 1 */ + (uint32_t) (7UL << (125 - 96)); /* Blue bit width - 1 */ + params[9] = 7; /* Alpha bit width - 1 */ + break; + case IPU_PIX_FMT_ABGR32: + /* BPP & pixel fmt */ + params[7] |= 0 | (4UL << (81 - 64)) | (7 << (89 - 64)); + params[8] = 2 | /* SAT = 32-bit access */ + (0UL << (99 - 96)) | /* Alpha bit offset */ + (8UL << (104 - 96)) | /* Blue bit offset */ + (16UL << (109 - 96)) | /* Green bit offset */ + (24UL << (114 - 96)) | /* Red bit offset */ + (7UL << (119 - 96)) | /* Alpha bit width - 1 */ + (7UL << (122 - 96)) | /* Blue bit width - 1 */ + (uint32_t) (7UL << (125 - 96)); /* Green bit width - 1 */ + params[9] = 7; /* Red bit width - 1 */ + break; + case IPU_PIX_FMT_UYVY: + /* BPP & pixel format */ + params[7] |= 2 | (6UL << 17) | (7 << (89 - 64)); + params[8] = 2; /* SAT = 32-bit access */ + break; + case IPU_PIX_FMT_YUV420P2: + case IPU_PIX_FMT_YUV420P: + /* BPP & pixel format */ + params[7] |= 3 | (3UL << 17) | (7 << (89 - 64)); + params[8] = 2; /* SAT = 32-bit access */ + u_offset = (u == 0) ? stride * height : u; + v_offset = (v == 0) ? u_offset + u_offset / 4 : v; + break; + case IPU_PIX_FMT_YVU422P: + /* BPP & pixel format */ + params[7] |= 3 | (2UL << 17) | (7 << (89 - 64)); + params[8] = 2; /* SAT = 32-bit access */ + v_offset = (v == 0) ? stride * height : v; + u_offset = (u == 0) ? v_offset + v_offset / 2 : u; + break; + case IPU_PIX_FMT_YUV422P: + /* BPP & pixel format */ + params[7] |= 3 | (2UL << 17) | (7 << (89 - 64)); + params[8] = 2; /* SAT = 32-bit access */ + u_offset = (u == 0) ? stride * height : u; + v_offset = (v == 0) ? u_offset + u_offset / 2 : v; + break; + default: + dev_err(g_ipu_dev, "mxc ipu: unimplemented pixel format\n"); + break; + } + + params[1] = (1UL << (46 - 32)) | (u_offset << (53 - 32)); + params[2] = u_offset >> (64 - 53); + params[2] |= v_offset << (79 - 64); + params[3] |= v_offset >> (96 - 79); +} + +static __inline void _ipu_ch_param_set_burst_size(uint32_t * params, + uint16_t burst_pixels) +{ + params[7] &= ~(0x3FL << (89 - 64)); + params[7] |= (uint32_t) (burst_pixels - 1) << (89 - 64); +}; + +static __inline void _ipu_ch_param_set_buffer(uint32_t * params, + dma_addr_t buf0, dma_addr_t buf1) +{ + params[5] = buf0; + params[6] = buf1; +}; + +static __inline void _ipu_ch_param_set_rotation(uint32_t * params, + ipu_rotate_mode_t rot) +{ + params[7] |= (uint32_t) rot << (84 - 64); +}; + +void _ipu_write_param_mem(uint32_t addr, uint32_t * data, uint32_t numWords); + +#endif diff -urN linux-2.6.26/drivers/mxc/ipu/ipu_prv.h linux-2.6.26-lab126/drivers/mxc/ipu/ipu_prv.h --- linux-2.6.26/drivers/mxc/ipu/ipu_prv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu/ipu_prv.h 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,64 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __INCLUDE_IPU_PRV_H__ +#define __INCLUDE_IPU_PRV_H__ + +#include +#include +#include +#include +#include + +/* Globals */ +extern struct device *g_ipu_dev; +extern spinlock_t ipu_lock; +extern struct clk *g_ipu_clk; +extern struct clk *g_ipu_csi_clk; + +int register_ipu_device(void); +ipu_color_space_t format_to_colorspace(uint32_t fmt); + +uint32_t _ipu_channel_status(ipu_channel_t channel); + +void _ipu_sdc_fg_init(ipu_channel_params_t * params); +uint32_t _ipu_sdc_fg_uninit(void); +void _ipu_sdc_bg_init(ipu_channel_params_t * params); +uint32_t _ipu_sdc_bg_uninit(void); + +void _ipu_ic_enable_task(ipu_channel_t channel); +void _ipu_ic_disable_task(ipu_channel_t channel); +void _ipu_ic_init_prpvf(ipu_channel_params_t * params, bool src_is_csi); +void _ipu_ic_uninit_prpvf(void); +void _ipu_ic_init_rotate_vf(ipu_channel_params_t * params); +void _ipu_ic_uninit_rotate_vf(void); +void _ipu_ic_init_csi(ipu_channel_params_t * params); +void _ipu_ic_uninit_csi(void); +void _ipu_ic_init_prpenc(ipu_channel_params_t * params, bool src_is_csi); +void _ipu_ic_uninit_prpenc(void); +void _ipu_ic_init_rotate_enc(ipu_channel_params_t * params); +void _ipu_ic_uninit_rotate_enc(void); +void _ipu_ic_init_pp(ipu_channel_params_t * params); +void _ipu_ic_uninit_pp(void); +void _ipu_ic_init_rotate_pp(ipu_channel_params_t * params); +void _ipu_ic_uninit_rotate_pp(void); + +int32_t _ipu_adc_init_channel(ipu_channel_t chan, display_port_t disp, + mcu_mode_t cmd, int16_t x_pos, int16_t y_pos); +int32_t _ipu_adc_uninit_channel(ipu_channel_t chan); + +#ifdef CONFIG_MACH_LUIGI_LAB126 +int _ipu_l126_detect_init(struct platform_device *dev); +void _ipu_l126_detect_done(struct platform_device *dev); +#endif + +#endif /* __INCLUDE_IPU_PRV_H__ */ diff -urN linux-2.6.26/drivers/mxc/ipu/ipu_sdc.c linux-2.6.26-lab126/drivers/mxc/ipu/ipu_sdc.c --- linux-2.6.26/drivers/mxc/ipu/ipu_sdc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu/ipu_sdc.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,357 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_sdc.c + * + * @brief IPU SDC submodule API functions + * + * @ingroup IPU + */ +#include +#include +#include +#include +#include +#include "ipu_prv.h" +#include +#include "ipu_param_mem.h" + +static uint32_t g_h_start_width; +static uint32_t g_v_start_width; + +static const uint32_t di_mappings[] = { + 0x1600AAAA, 0x00E05555, 0x00070000, 3, /* RGB888 */ + 0x0005000F, 0x000B000F, 0x0011000F, 1, /* RGB666 */ + 0x0011000F, 0x000B000F, 0x0005000F, 1, /* BGR666 */ + 0x0004003F, 0x000A000F, 0x000F003F, 1 /* RGB565 */ +}; + +/*! + * This function is called to initialize a synchronous LCD panel. + * + * @param panel The type of panel. + * + * @param pixel_clk Desired pixel clock frequency in Hz. + * + * @param pixel_fmt Input parameter for pixel format of buffer. Pixel + * format is a FOURCC ASCII code. + * + * @param width The width of panel in pixels. + * + * @param height The height of panel in pixels. + * + * @param hStartWidth The number of pixel clocks between the HSYNC + * signal pulse and the start of valid data. + * + * @param hSyncWidth The width of the HSYNC signal in units of pixel + * clocks. + * + * @param hEndWidth The number of pixel clocks between the end of + * valid data and the HSYNC signal for next line. + * + * @param vStartWidth The number of lines between the VSYNC + * signal pulse and the start of valid data. + * + * @param vSyncWidth The width of the VSYNC signal in units of lines + * + * @param vEndWidth The number of lines between the end of valid + * data and the VSYNC signal for next frame. + * + * @param sig Bitfield of signal polarities for LCD interface. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_sdc_init_panel(ipu_panel_t panel, + uint32_t pixel_clk, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint16_t h_start_width, uint16_t h_sync_width, + uint16_t h_end_width, uint16_t v_start_width, + uint16_t v_sync_width, uint16_t v_end_width, + ipu_di_signal_cfg_t sig) +{ + unsigned long lock_flags; + uint32_t reg; + uint32_t old_conf; + uint32_t div; + + dev_dbg(g_ipu_dev, "panel size = %d x %d\n", width, height); + + if ((v_sync_width == 0) || (h_sync_width == 0)) + return EINVAL; + + /* Init panel size and blanking periods */ + reg = + ((uint32_t) (h_sync_width - 1) << 26) | + ((uint32_t) (width + h_sync_width + h_start_width + h_end_width - 1) + << 16); + __raw_writel(reg, SDC_HOR_CONF); + + reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L | + ((uint32_t) + (height + v_sync_width + v_start_width + v_end_width - 1) << 16); + __raw_writel(reg, SDC_VER_CONF); + + g_h_start_width = h_start_width + h_sync_width; + g_v_start_width = v_start_width + v_sync_width; + + switch (panel) { + case IPU_PANEL_SHARP_TFT: + __raw_writel(0x00FD0102L, SDC_SHARP_CONF_1); + __raw_writel(0x00F500F4L, SDC_SHARP_CONF_2); + __raw_writel(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF); + break; + case IPU_PANEL_TFT: + __raw_writel(SDC_COM_TFT_COLOR, SDC_COM_CONF); + break; + default: + return EINVAL; + } + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + + /* Init clocking */ + + /* Calculate divider */ + /* fractional part is 4 bits so simply multiple by 2^4 to get fractional part */ + dev_dbg(g_ipu_dev, "pixel clk = %d\n", pixel_clk); + div = (clk_get_rate(g_ipu_clk) * 16) / pixel_clk; + if (div < 0x40) { /* Divider less than 4 */ + dev_dbg(g_ipu_dev, + "InitPanel() - Pixel clock divider less than 1\n"); + div = 0x40; + } + /* DISP3_IF_CLK_DOWN_WR is half the divider value and 2 less fraction bits */ + /* Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing debug */ + /* DISP3_IF_CLK_UP_WR is 0 */ + __raw_writel((((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF); + + /* DI settings */ + old_conf = __raw_readl(DI_DISP_IF_CONF) & 0x78FFFFFF; + old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT | + sig.clksel_en << DI_D3_CLK_SEL_SHIFT | + sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT; + __raw_writel(old_conf, DI_DISP_IF_CONF); + + old_conf = __raw_readl(DI_DISP_SIG_POL) & 0xE0FFFFFF; + old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT | + sig.clk_pol << DI_D3_CLK_POL_SHIFT | + sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT | + sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT | + sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT; + __raw_writel(old_conf, DI_DISP_SIG_POL); + + switch (pixel_fmt) { + case IPU_PIX_FMT_RGB24: + __raw_writel(di_mappings[0], DI_DISP3_B0_MAP); + __raw_writel(di_mappings[1], DI_DISP3_B1_MAP); + __raw_writel(di_mappings[2], DI_DISP3_B2_MAP); + __raw_writel(__raw_readl(DI_DISP_ACC_CC) | + ((di_mappings[3] - 1) << 12), DI_DISP_ACC_CC); + break; + case IPU_PIX_FMT_RGB666: + __raw_writel(di_mappings[4], DI_DISP3_B0_MAP); + __raw_writel(di_mappings[5], DI_DISP3_B1_MAP); + __raw_writel(di_mappings[6], DI_DISP3_B2_MAP); + __raw_writel(__raw_readl(DI_DISP_ACC_CC) | + ((di_mappings[7] - 1) << 12), DI_DISP_ACC_CC); + break; + case IPU_PIX_FMT_BGR666: + __raw_writel(di_mappings[8], DI_DISP3_B0_MAP); + __raw_writel(di_mappings[9], DI_DISP3_B1_MAP); + __raw_writel(di_mappings[10], DI_DISP3_B2_MAP); + __raw_writel(__raw_readl(DI_DISP_ACC_CC) | + ((di_mappings[11] - 1) << 12), DI_DISP_ACC_CC); + break; + default: + __raw_writel(di_mappings[12], DI_DISP3_B0_MAP); + __raw_writel(di_mappings[13], DI_DISP3_B1_MAP); + __raw_writel(di_mappings[14], DI_DISP3_B2_MAP); + __raw_writel(__raw_readl(DI_DISP_ACC_CC) | + ((di_mappings[15] - 1) << 12), DI_DISP_ACC_CC); + break; + } + + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + + dev_dbg(g_ipu_dev, "DI_DISP_IF_CONF = 0x%08X\n", + __raw_readl(DI_DISP_IF_CONF)); + dev_dbg(g_ipu_dev, "DI_DISP_SIG_POL = 0x%08X\n", + __raw_readl(DI_DISP_SIG_POL)); + dev_dbg(g_ipu_dev, "DI_DISP3_TIME_CONF = 0x%08X\n", + __raw_readl(DI_DISP3_TIME_CONF)); + + return 0; +} + +/*! + * This function sets the foreground and background plane global alpha blending + * modes. + * + * @param enable Boolean to enable or disable global alpha + * blending. If disabled, per pixel blending is used. + * + * @param alpha Global alpha value. + * + * @return This function returns 0 on success or negative error code on fail + */ +int32_t ipu_sdc_set_global_alpha(bool enable, uint8_t alpha) +{ + uint32_t reg; + unsigned long lock_flags; + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + + if (enable) { + reg = __raw_readl(SDC_GW_CTRL) & 0x00FFFFFFL; + __raw_writel(reg | ((uint32_t) alpha << 24), SDC_GW_CTRL); + + reg = __raw_readl(SDC_COM_CONF); + __raw_writel(reg | SDC_COM_GLB_A, SDC_COM_CONF); + } else { + reg = __raw_readl(SDC_COM_CONF); + __raw_writel(reg & ~SDC_COM_GLB_A, SDC_COM_CONF); + } + + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} + +/*! + * This function sets the transparent color key for SDC graphic plane. + * + * @param channel Input parameter for the logical channel ID. + * + * @param enable Boolean to enable or disable color key + * + * @param colorKey 24-bit RGB color to use as transparent color key. + * + * @return This function returns 0 on success or negative error code on fail + */ +int32_t ipu_sdc_set_color_key(ipu_channel_t channel, bool enable, + uint32_t color_key) +{ + uint32_t reg, sdc_conf; + unsigned long lock_flags; + + ipu_spin_lock_irqsave(&ipu_lock, lock_flags); + + sdc_conf = __raw_readl(SDC_COM_CONF); + if (channel == MEM_SDC_BG) { + sdc_conf &= ~SDC_COM_GWSEL; + } else { + sdc_conf |= SDC_COM_GWSEL; + } + + if (enable) { + reg = __raw_readl(SDC_GW_CTRL) & 0xFF000000L; + __raw_writel(reg | (color_key & 0x00FFFFFFL), SDC_GW_CTRL); + + sdc_conf |= SDC_COM_KEY_COLOR_G; + } else { + sdc_conf &= ~SDC_COM_KEY_COLOR_G; + } + __raw_writel(sdc_conf, SDC_COM_CONF); + + ipu_spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} + +int32_t ipu_sdc_set_brightness(uint8_t value) +{ + __raw_writel(0x03000000UL | value << 16, SDC_PWM_CTRL); + return 0; +} + +/*! + * This function sets the window position of the foreground or background plane. + * modes. + * + * @param channel Input parameter for the logical channel ID. + * + * @param x_pos The X coordinate position to place window at. + * The position is relative to the top left corner. + * + * @param y_pos The Y coordinate position to place window at. + * The position is relative to the top left corner. + * + * @return This function returns 0 on success or negative error code on fail + */ +int32_t ipu_sdc_set_window_pos(ipu_channel_t channel, int16_t x_pos, + int16_t y_pos) +{ + x_pos += g_h_start_width; + y_pos += g_v_start_width; + + if (channel == MEM_SDC_BG) { + __raw_writel((x_pos << 16) | y_pos, SDC_BG_POS); + } else if (channel == MEM_SDC_FG) { + __raw_writel((x_pos << 16) | y_pos, SDC_FG_POS); + } else { + return EINVAL; + } + return 0; +} + +void _ipu_sdc_fg_init(ipu_channel_params_t * params) +{ + uint32_t reg; + (void)params; + + /* Enable FG channel */ + reg = __raw_readl(SDC_COM_CONF); + __raw_writel(reg | SDC_COM_FG_EN | SDC_COM_BG_EN, SDC_COM_CONF); +} + +uint32_t _ipu_sdc_fg_uninit(void) +{ + uint32_t reg; + + /* Disable FG channel */ + reg = __raw_readl(SDC_COM_CONF); + __raw_writel(reg & ~SDC_COM_FG_EN, SDC_COM_CONF); + + return (reg & SDC_COM_FG_EN); +} + +void _ipu_sdc_bg_init(ipu_channel_params_t * params) +{ + uint32_t reg; + (void)params; + + /* Enable FG channel */ + reg = __raw_readl(SDC_COM_CONF); + __raw_writel(reg | SDC_COM_BG_EN, SDC_COM_CONF); +} + +uint32_t _ipu_sdc_bg_uninit(void) +{ + uint32_t reg; + + /* Disable BG channel */ + reg = __raw_readl(SDC_COM_CONF); + __raw_writel(reg & ~SDC_COM_BG_EN, SDC_COM_CONF); + + return (reg & SDC_COM_BG_EN); +} + +/* Exported symbols for modules. */ +EXPORT_SYMBOL(ipu_sdc_init_panel); +EXPORT_SYMBOL(ipu_sdc_set_global_alpha); +EXPORT_SYMBOL(ipu_sdc_set_color_key); +EXPORT_SYMBOL(ipu_sdc_set_brightness); +EXPORT_SYMBOL(ipu_sdc_set_window_pos); diff -urN linux-2.6.26/drivers/mxc/ipu/pf/Kconfig linux-2.6.26-lab126/drivers/mxc/ipu/pf/Kconfig --- linux-2.6.26/drivers/mxc/ipu/pf/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu/pf/Kconfig 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,7 @@ +config MXC_IPU_PF + tristate "MXC MPEG4/H.264 Post Filter Driver" + depends on MXC_IPU_V1 + default y + help + Driver for MPEG4 dering and deblock and H.264 deblock + using MXC IPU h/w diff -urN linux-2.6.26/drivers/mxc/ipu/pf/Makefile linux-2.6.26-lab126/drivers/mxc/ipu/pf/Makefile --- linux-2.6.26/drivers/mxc/ipu/pf/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu/pf/Makefile 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1 @@ +obj-$(CONFIG_MXC_IPU_PF) += mxc_pf.o diff -urN linux-2.6.26/drivers/mxc/ipu/pf/mxc_pf.c linux-2.6.26-lab126/drivers/mxc/ipu/pf/mxc_pf.c --- linux-2.6.26/drivers/mxc/ipu/pf/mxc_pf.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu/pf/mxc_pf.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,993 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_pf.c + * + * @brief MXC IPU MPEG4/H.264 Post-filtering driver + * + * User-level API for IPU Hardware MPEG4/H.264 Post-filtering. + * + * @ingroup MXC_PF + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct mxc_pf_data { + pf_operation_t mode; + u32 pf_enabled; + u32 width; + u32 height; + u32 stride; + uint32_t qp_size; + dma_addr_t qp_paddr; + void *qp_vaddr; + pf_buf buf[PF_MAX_BUFFER_CNT]; + void *buf_vaddr[PF_MAX_BUFFER_CNT]; + wait_queue_head_t pf_wait; + volatile int done_mask; + volatile int wait_mask; + volatile int busy_flag; + struct semaphore busy_lock; +}; + +static struct mxc_pf_data pf_data; +static u8 open_count = 0; +static struct class *mxc_pf_class; + +/* + * Function definitions + */ + +static irqreturn_t mxc_pf_irq_handler(int irq, void *dev_id) +{ + struct mxc_pf_data *pf = dev_id; + + if (irq == IPU_IRQ_PF_Y_OUT_EOF) { + pf->done_mask |= PF_WAIT_Y; + } else if (irq == IPU_IRQ_PF_U_OUT_EOF) { + pf->done_mask |= PF_WAIT_U; + } else if (irq == IPU_IRQ_PF_V_OUT_EOF) { + pf->done_mask |= PF_WAIT_V; + } else { + return IRQ_NONE; + } + + if (pf->wait_mask && ((pf->done_mask & pf->wait_mask) == pf->wait_mask)) { + wake_up_interruptible(&pf->pf_wait); + } + return IRQ_HANDLED; +} + +/*! + * This function handles PF_IOCTL_INIT calls. It initializes the PF channels, + * interrupt handlers, and channel buffers. + * + * @return This function returns 0 on success or negative error code on + * error. + */ +static int mxc_pf_init(pf_init_params * pf_init) +{ + int err; + ipu_channel_params_t params; + u32 w; + u32 stride; + u32 h; + u32 qp_size = 0; + u32 qp_stride; + + if ((pf_init->pf_mode > 4) || (pf_init->width > 1024) || + (pf_init->height > 1024) || (pf_init->stride < pf_init->width)) { + return -EINVAL; + } + + pf_data.mode = pf_init->pf_mode; + w = pf_data.width = pf_init->width; + h = pf_data.height = pf_init->height; + stride = pf_data.stride = pf_init->stride; + pf_data.qp_size = pf_init->qp_size; + + memset(¶ms, 0, sizeof(params)); + params.mem_pf_mem.operation = pf_data.mode; + err = ipu_init_channel(MEM_PF_Y_MEM, ¶ms); + if (err < 0) { + printk(KERN_ERR "mxc_pf: error initializing channel\n"); + goto err0; + } + + err = ipu_init_channel_buffer(MEM_PF_Y_MEM, IPU_INPUT_BUFFER, + IPU_PIX_FMT_GENERIC, w, h, stride, + IPU_ROTATE_NONE, 0, 0, 0, 0); + if (err < 0) { + printk(KERN_ERR "mxc_pf: error initializing Y input buffer\n"); + goto err0; + } + + err = ipu_init_channel_buffer(MEM_PF_Y_MEM, IPU_OUTPUT_BUFFER, + IPU_PIX_FMT_GENERIC, w, h, stride, + IPU_ROTATE_NONE, 0, 0, 0, 0); + if (err < 0) { + printk(KERN_ERR "mxc_pf: error initializing Y output buffer\n"); + goto err0; + } + + w = w / 2; + h = h / 2; + stride = stride / 2; + + if (pf_data.mode != PF_MPEG4_DERING) { + err = ipu_init_channel_buffer(MEM_PF_U_MEM, IPU_INPUT_BUFFER, + IPU_PIX_FMT_GENERIC, w, h, stride, + IPU_ROTATE_NONE, 0, 0, 0, 0); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error initializing U input buffer\n"); + goto err0; + } + + err = ipu_init_channel_buffer(MEM_PF_U_MEM, IPU_OUTPUT_BUFFER, + IPU_PIX_FMT_GENERIC, w, h, stride, + IPU_ROTATE_NONE, 0, 0, 0, 0); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error initializing U output buffer\n"); + goto err0; + } + + err = ipu_init_channel_buffer(MEM_PF_V_MEM, IPU_INPUT_BUFFER, + IPU_PIX_FMT_GENERIC, w, h, stride, + IPU_ROTATE_NONE, 0, 0, 0, 0); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error initializing V input buffer\n"); + goto err0; + } + + err = ipu_init_channel_buffer(MEM_PF_V_MEM, IPU_OUTPUT_BUFFER, + IPU_PIX_FMT_GENERIC, w, h, stride, + IPU_ROTATE_NONE, 0, 0, 0, 0); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error initializing V output buffer\n"); + goto err0; + } + } + + /*Setup Channel QF and BSC Params */ + if (pf_data.mode == PF_H264_DEBLOCK) { + w = ((pf_data.width + 15) / 16); + h = (pf_data.height + 15) / 16; + qp_stride = w; + qp_size = 4 * qp_stride * h; + pr_debug("H264 QP width = %d, height = %d\n", w, h); + err = ipu_init_channel_buffer(MEM_PF_Y_MEM, + IPU_SEC_INPUT_BUFFER, + IPU_PIX_FMT_GENERIC_32, w, h, + qp_stride, IPU_ROTATE_NONE, 0, 0, + 0, 0); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error initializing H264 QP buffer\n"); + goto err0; + } +/* w = (pf_data.width + 3) / 4; */ + w *= 4; + h *= 4; + qp_stride = w; + err = ipu_init_channel_buffer(MEM_PF_U_MEM, + IPU_SEC_INPUT_BUFFER, + IPU_PIX_FMT_GENERIC, w, h, + qp_stride, IPU_ROTATE_NONE, 0, 0, + 0, 0); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error initializing H264 BSB buffer\n"); + goto err0; + } + qp_size += qp_stride * h; + } else { /* MPEG4 mode */ + + w = (pf_data.width + 15) / 16; + h = (pf_data.height + 15) / 16; + qp_stride = (w + 3) & ~0x3UL; + pr_debug("MPEG4 QP width = %d, height = %d, stride = %d\n", + w, h, qp_stride); + err = ipu_init_channel_buffer(MEM_PF_Y_MEM, + IPU_SEC_INPUT_BUFFER, + IPU_PIX_FMT_GENERIC, w, h, + qp_stride, IPU_ROTATE_NONE, 0, 0, + 0, 0); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error initializing MPEG4 QP buffer\n"); + goto err0; + } + qp_size = qp_stride * h; + } + + /* Support 2 QP buffers */ + qp_size *= 2; + + if (pf_data.qp_size > qp_size) + qp_size = pf_data.qp_size; + else + pf_data.qp_size = qp_size; + + pf_data.qp_vaddr = dma_alloc_coherent(NULL, pf_data.qp_size, + &pf_data.qp_paddr, + GFP_KERNEL | GFP_DMA); + if (!pf_data.qp_vaddr) + return -ENOMEM; + + pf_init->qp_paddr = pf_data.qp_paddr; + pf_init->qp_size = pf_data.qp_size; + + return 0; + + err0: + return err; +} + +/*! + * This function handles PF_IOCTL_UNINIT calls. It uninitializes the PF + * channels and interrupt handlers. + * + * @return This function returns 0 on success or negative error code + * on error. + */ +static int mxc_pf_uninit(void) +{ + pf_data.pf_enabled = 0; + ipu_disable_irq(IPU_IRQ_PF_Y_OUT_EOF); + ipu_disable_irq(IPU_IRQ_PF_U_OUT_EOF); + ipu_disable_irq(IPU_IRQ_PF_V_OUT_EOF); + + ipu_disable_channel(MEM_PF_Y_MEM, true); + ipu_disable_channel(MEM_PF_U_MEM, true); + ipu_disable_channel(MEM_PF_V_MEM, true); + ipu_uninit_channel(MEM_PF_Y_MEM); + ipu_uninit_channel(MEM_PF_U_MEM); + ipu_uninit_channel(MEM_PF_V_MEM); + + if (pf_data.qp_vaddr) { + dma_free_coherent(NULL, pf_data.qp_size, pf_data.qp_vaddr, + pf_data.qp_paddr); + pf_data.qp_vaddr = NULL; + } + + return 0; +} + +/*! + * This function handles PF_IOCTL_REQBUFS calls. It initializes the PF channels + * and channel buffers. + * + * @param reqbufs Input/Output Structure containing buffer mode, + * type, offset, and size. The offset and size of + * the buffer are returned for PF_MEMORY_MMAP mode. + * + * @return This function returns 0 on success or negative error code + * on error. + */ +static int mxc_pf_reqbufs(pf_reqbufs_params * reqbufs) +{ + int err; + uint32_t buf_size; + int i; + int alloc_cnt = 0; + pf_buf *buf = pf_data.buf; + if (reqbufs->count > PF_MAX_BUFFER_CNT) { + reqbufs->count = PF_MAX_BUFFER_CNT; + } + /* Deallocate mmapped buffers */ + if (reqbufs->count == 0) { + for (i = 0; i < PF_MAX_BUFFER_CNT; i++) { + if (buf[i].index != -1) { + dma_free_coherent(NULL, buf[i].size, + pf_data.buf_vaddr[i], + buf[i].offset); + pf_data.buf_vaddr[i] = NULL; + buf[i].index = -1; + buf[i].size = 0; + } + } + return 0; + } + + buf_size = (pf_data.stride * pf_data.height * 3) / 2; + if (reqbufs->req_size > buf_size) { + buf_size = reqbufs->req_size; + pr_debug("using requested buffer size of %d\n", buf_size); + } else { + reqbufs->req_size = buf_size; + pr_debug("using default buffer size of %d\n", buf_size); + } + + for (i = 0; alloc_cnt < reqbufs->count; i++) { + buf[i].index = i; + buf[i].size = buf_size; + pf_data.buf_vaddr[i] = dma_alloc_coherent(NULL, buf[i].size, + &buf[i].offset, + GFP_KERNEL | GFP_DMA); + if (!pf_data.buf_vaddr[i] || !buf[i].offset) { + printk(KERN_ERR + "mxc_pf: unable to allocate IPU buffers.\n"); + err = -ENOMEM; + goto err0; + } + pr_debug("Allocated buffer %d at paddr 0x%08X, vaddr %p\n", + i, buf[i].offset, pf_data.buf_vaddr[i]); + + alloc_cnt++; + } + + return 0; + err0: + for (i = 0; i < alloc_cnt; i++) { + dma_free_coherent(NULL, buf[i].size, pf_data.buf_vaddr[i], + buf[i].offset); + pf_data.buf_vaddr[i] = NULL; + buf[i].index = -1; + buf[i].size = 0; + } + return err; +} + +/*! + * This function handles PF_IOCTL_START calls. It sets the PF channel buffers + * addresses and starts the channels + * + * @return This function returns 0 on success or negative error code on + * error. + */ +static int mxc_pf_start(pf_buf * in, pf_buf * out, int qp_buf) +{ + int err; + dma_addr_t y_in_paddr; + dma_addr_t u_in_paddr; + dma_addr_t v_in_paddr; + dma_addr_t p1_in_paddr; + dma_addr_t p2_in_paddr; + dma_addr_t y_out_paddr; + dma_addr_t u_out_paddr; + dma_addr_t v_out_paddr; + + /* H.264 requires output buffer equal to input */ + if (pf_data.mode == PF_H264_DEBLOCK) + out = in; + + y_in_paddr = in->offset + in->y_offset; + if (in->u_offset) + u_in_paddr = in->offset + in->u_offset; + else + u_in_paddr = y_in_paddr + (pf_data.stride * pf_data.height); + if (in->v_offset) + v_in_paddr = in->offset + in->v_offset; + else + v_in_paddr = u_in_paddr + (pf_data.stride * pf_data.height) / 4; + p1_in_paddr = pf_data.qp_paddr; + if (qp_buf) + p1_in_paddr += pf_data.qp_size / 2; + + if (pf_data.mode == PF_H264_DEBLOCK) { + p2_in_paddr = p1_in_paddr + + ((pf_data.width + 15) / 16) * + ((pf_data.height + 15) / 16) * 4; + } else { + p2_in_paddr = 0; + } + + pr_debug("y_in_paddr = 0x%08X\nu_in_paddr = 0x%08X\n" + "v_in_paddr = 0x%08X\n" + "qp_paddr = 0x%08X\nbsb_paddr = 0x%08X\n", + y_in_paddr, u_in_paddr, v_in_paddr, p1_in_paddr, p2_in_paddr); + + y_out_paddr = out->offset + out->y_offset; + if (out->u_offset) + u_out_paddr = out->offset + out->u_offset; + else + u_out_paddr = y_out_paddr + (pf_data.stride * pf_data.height); + if (out->v_offset) + v_out_paddr = out->offset + out->v_offset; + else + v_out_paddr = + u_out_paddr + (pf_data.stride * pf_data.height) / 4; + + pr_debug("y_out_paddr = 0x%08X\nu_out_paddr = 0x%08X\n" + "v_out_paddr = 0x%08X\n", + y_out_paddr, u_out_paddr, v_out_paddr); + + pf_data.done_mask = 0; + + ipu_enable_irq(IPU_IRQ_PF_Y_OUT_EOF); + if (pf_data.mode != PF_MPEG4_DERING) { + ipu_enable_irq(IPU_IRQ_PF_U_OUT_EOF); + ipu_enable_irq(IPU_IRQ_PF_V_OUT_EOF); + } + + err = ipu_update_channel_buffer(MEM_PF_Y_MEM, IPU_INPUT_BUFFER, 0, + y_in_paddr); + if (err < 0) { + printk(KERN_ERR "mxc_pf: error setting Y input buffer\n"); + goto err0; + } + + err = ipu_update_channel_buffer(MEM_PF_Y_MEM, IPU_OUTPUT_BUFFER, 0, + y_out_paddr); + if (err < 0) { + printk(KERN_ERR "mxc_pf: error setting Y output buffer\n"); + goto err0; + } + + if (pf_data.mode != PF_MPEG4_DERING) { + err = + ipu_update_channel_buffer(MEM_PF_U_MEM, IPU_INPUT_BUFFER, 0, + u_in_paddr); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error setting U input buffer\n"); + goto err0; + } + + err = + ipu_update_channel_buffer(MEM_PF_U_MEM, IPU_OUTPUT_BUFFER, + 0, u_out_paddr); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error setting U output buffer\n"); + goto err0; + } + + err = + ipu_update_channel_buffer(MEM_PF_V_MEM, IPU_INPUT_BUFFER, 0, + v_in_paddr); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error setting V input buffer\n"); + goto err0; + } + + err = + ipu_update_channel_buffer(MEM_PF_V_MEM, IPU_OUTPUT_BUFFER, + 0, v_out_paddr); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error setting V output buffer\n"); + goto err0; + } + } + + err = ipu_update_channel_buffer(MEM_PF_Y_MEM, IPU_SEC_INPUT_BUFFER, 0, + p1_in_paddr); + if (err < 0) { + printk(KERN_ERR "mxc_pf: error setting QP buffer\n"); + goto err0; + } + + if (pf_data.mode == PF_H264_DEBLOCK) { + + err = ipu_update_channel_buffer(MEM_PF_U_MEM, + IPU_SEC_INPUT_BUFFER, 0, + p2_in_paddr); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error setting H264 BSB buffer\n"); + goto err0; + } + ipu_select_buffer(MEM_PF_U_MEM, IPU_SEC_INPUT_BUFFER, 0); + } + + ipu_select_buffer(MEM_PF_Y_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(MEM_PF_Y_MEM, IPU_SEC_INPUT_BUFFER, 0); + ipu_select_buffer(MEM_PF_Y_MEM, IPU_INPUT_BUFFER, 0); + if (pf_data.mode != PF_MPEG4_DERING) { + ipu_select_buffer(MEM_PF_U_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(MEM_PF_V_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(MEM_PF_U_MEM, IPU_INPUT_BUFFER, 0); + ipu_select_buffer(MEM_PF_V_MEM, IPU_INPUT_BUFFER, 0); + } + + if (!pf_data.pf_enabled) { + pf_data.pf_enabled = 1; + if (pf_data.mode != PF_MPEG4_DERING) { + ipu_enable_channel(MEM_PF_V_MEM); + ipu_enable_channel(MEM_PF_U_MEM); + } + ipu_enable_channel(MEM_PF_Y_MEM); + } + + return 0; + err0: + return err; +} + +/*! + * Post Filter driver open function. This function implements the Linux + * file_operations.open() API function. + * + * @param inode struct inode * + * + * @param filp struct file * + * + * @return This function returns 0 on success or negative error code on + * error. + */ +static int mxc_pf_open(struct inode *inode, struct file *filp) +{ + int i; + + if (open_count) { + return -EBUSY; + } + + open_count++; + + memset(&pf_data, 0, sizeof(pf_data)); + for (i = 0; i < PF_MAX_BUFFER_CNT; i++) { + pf_data.buf[i].index = -1; + } + init_waitqueue_head(&pf_data.pf_wait); + init_MUTEX(&pf_data.busy_lock); + + pf_data.busy_flag = 1; + + ipu_request_irq(IPU_IRQ_PF_Y_OUT_EOF, mxc_pf_irq_handler, + 0, "mxc_ipu_pf", &pf_data); + + ipu_request_irq(IPU_IRQ_PF_U_OUT_EOF, mxc_pf_irq_handler, + 0, "mxc_ipu_pf", &pf_data); + + ipu_request_irq(IPU_IRQ_PF_V_OUT_EOF, mxc_pf_irq_handler, + 0, "mxc_ipu_pf", &pf_data); + + ipu_disable_irq(IPU_IRQ_PF_Y_OUT_EOF); + ipu_disable_irq(IPU_IRQ_PF_U_OUT_EOF); + ipu_disable_irq(IPU_IRQ_PF_V_OUT_EOF); + + return 0; +} + +/*! + * Post Filter driver release function. This function implements the Linux + * file_operations.release() API function. + * + * @param inode struct inode * + * + * @param filp struct file * + * + * @return This function returns 0 on success or negative error code on + * error. + */ +static int mxc_pf_release(struct inode *inode, struct file *filp) +{ + pf_reqbufs_params req_buf; + + if (open_count) { + mxc_pf_uninit(); + + /* Free any allocated buffers */ + req_buf.count = 0; + mxc_pf_reqbufs(&req_buf); + + ipu_free_irq(IPU_IRQ_PF_V_OUT_EOF, &pf_data); + ipu_free_irq(IPU_IRQ_PF_U_OUT_EOF, &pf_data); + ipu_free_irq(IPU_IRQ_PF_Y_OUT_EOF, &pf_data); + open_count--; + } + return 0; +} + +/*! + * Post Filter driver ioctl function. This function implements the Linux + * file_operations.ioctl() API function. + * + * @param inode struct inode * + * + * @param filp struct file * + * + * @param cmd IOCTL command to handle + * + * @param arg Pointer to arguments for IOCTL + * + * @return This function returns 0 on success or negative error code on + * error. + */ +static int mxc_pf_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + int retval = 0; + + switch (cmd) { + case PF_IOCTL_INIT: + { + pf_init_params pf_init; + + pr_debug("PF_IOCTL_INIT\n"); + if (copy_from_user(&pf_init, (void *)arg, + _IOC_SIZE(cmd))) { + retval = -EFAULT; + break; + } + + retval = mxc_pf_init(&pf_init); + if (retval < 0) + break; + pf_init.qp_paddr = pf_data.qp_paddr; + pf_init.qp_size = pf_data.qp_size; + + /* Return size of memory allocated */ + if (copy_to_user((void *)arg, &pf_init, _IOC_SIZE(cmd))) { + retval = -EFAULT; + break; + } + + pf_data.busy_flag = 0; + break; + } + case PF_IOCTL_UNINIT: + pr_debug("PF_IOCTL_UNINIT\n"); + retval = mxc_pf_uninit(); + break; + case PF_IOCTL_REQBUFS: + { + pf_reqbufs_params reqbufs; + pr_debug("PF_IOCTL_REQBUFS\n"); + + if (copy_from_user + (&reqbufs, (void *)arg, _IOC_SIZE(cmd))) { + retval = -EFAULT; + break; + } + + retval = mxc_pf_reqbufs(&reqbufs); + + /* Return size of memory allocated */ + if (copy_to_user((void *)arg, &reqbufs, _IOC_SIZE(cmd))) { + retval = -EFAULT; + break; + } + + break; + } + case PF_IOCTL_QUERYBUF: + { + pf_buf buf; + pr_debug("PF_IOCTL_QUERYBUF\n"); + + if (copy_from_user(&buf, (void *)arg, _IOC_SIZE(cmd))) { + retval = -EFAULT; + break; + } + + if ((buf.index < 0) || + (buf.index >= PF_MAX_BUFFER_CNT) || + (pf_data.buf[buf.index].index != buf.index)) { + retval = -EINVAL; + break; + } + /* Return size of memory allocated */ + if (copy_to_user((void *)arg, &pf_data.buf[buf.index], + _IOC_SIZE(cmd))) { + retval = -EFAULT; + break; + } + + break; + } + case PF_IOCTL_START: + { + int index; + pf_start_params start_params; + pr_debug("PF_IOCTL_START\n"); + + if (pf_data.busy_flag) { + retval = -EBUSY; + break; + } + + if (copy_from_user(&start_params, (void *)arg, + _IOC_SIZE(cmd))) { + retval = -EFAULT; + break; + } + if (start_params.h264_pause_row >= + ((pf_data.height + 15) / 16)) { + retval = -EINVAL; + break; + } + + pf_data.busy_flag = 1; + + index = start_params.in.index; + if ((index >= 0) && (index < PF_MAX_BUFFER_CNT)) { + if (pf_data.buf[index].offset != + start_params.in.offset) { + retval = -EINVAL; + break; + } + } + + index = start_params.out.index; + if ((index >= 0) && (index < PF_MAX_BUFFER_CNT)) { + if (pf_data.buf[index].offset != + start_params.out.offset) { + retval = -EINVAL; + break; + } + } + + ipu_pf_set_pause_row(start_params.h264_pause_row); + + /*Update y, u, v buffers in DMA Channels */ + if ((retval = + mxc_pf_start(&start_params.in, &start_params.out, + start_params.qp_buf)) + < 0) { + break; + } + + pr_debug("PF_IOCTL_START - processing started\n"); + + if (!start_params.wait) { + break; + } + + pr_debug("PF_IOCTL_START - waiting for completion\n"); + + pf_data.wait_mask = PF_WAIT_ALL; + /* Fall thru to wait */ + } + case PF_IOCTL_WAIT: + { + if (!pf_data.wait_mask) + pf_data.wait_mask = (u32) arg; + + if (pf_data.mode == PF_MPEG4_DERING) + pf_data.wait_mask &= PF_WAIT_Y; + + if (!pf_data.wait_mask) { + retval = -EINVAL; + break; + } + + if (!wait_event_interruptible_timeout(pf_data.pf_wait, + ((pf_data. + done_mask & + pf_data. + wait_mask) == + pf_data. + wait_mask), + 1 * HZ)) { + pr_debug + ("PF_IOCTL_WAIT: timeout, done_mask = %d\n", + pf_data.done_mask); + retval = -ETIME; + break; + } else if (signal_pending(current)) { + pr_debug("PF_IOCTL_WAIT: interrupt received\n"); + retval = -ERESTARTSYS; + break; + } + pf_data.busy_flag = 0; + pf_data.wait_mask = 0; + + pr_debug("PF_IOCTL_WAIT - finished\n"); + break; + } + case PF_IOCTL_RESUME: + { + int pause_row; + pr_debug("PF_IOCTL_RESUME\n"); + + if (pf_data.busy_flag == 0) { + retval = -EFAULT; + break; + } + + if (copy_from_user(&pause_row, (void *)arg, + _IOC_SIZE(cmd))) { + retval = -EFAULT; + break; + } + + if (pause_row >= ((pf_data.height + 15) / 16)) { + retval = -EINVAL; + break; + } + + ipu_pf_set_pause_row(pause_row); + break; + } + + default: + printk(KERN_ERR "ipu_pf_ioctl not supported ioctl\n"); + retval = -1; + } + + if (retval < 0) + pr_debug("return = %d\n", retval); + return retval; +} + +/*! + * Post Filter driver mmap function. This function implements the Linux + * file_operations.mmap() API function for mapping driver buffers to user space. + * + * @param file struct file * + * + * @param vma structure vm_area_struct * + * + * @return 0 Success, EINTR busy lock error, + * ENOBUFS remap_page error. + */ +static int mxc_pf_mmap(struct file *file, struct vm_area_struct *vma) +{ + unsigned long size = vma->vm_end - vma->vm_start; + int res = 0; + + pr_debug("pgoff=0x%lx, start=0x%lx, end=0x%lx\n", + vma->vm_pgoff, vma->vm_start, vma->vm_end); + + /* make this _really_ smp-safe */ + if (down_interruptible(&pf_data.busy_lock)) + return -EINTR; + + /* make buffers write-thru cacheable */ + vma->vm_page_prot = __pgprot(pgprot_val(vma->vm_page_prot) & + ~L_PTE_BUFFERABLE); + + if (remap_pfn_range(vma, vma->vm_start, + vma->vm_pgoff, size, vma->vm_page_prot)) { + printk(KERN_ERR "mxc_pf: remap_pfn_range failed\n"); + res = -ENOBUFS; + goto mmap_exit; + } + + vma->vm_flags &= ~VM_IO; /* using shared anonymous pages */ + + mmap_exit: + up(&pf_data.busy_lock); + return res; +} + +/*! + * Post Filter driver fsync function. This function implements the Linux + * file_operations.fsync() API function. + * + * The user must call fsync() before reading an output buffer. This + * call flushes the L1 and L2 caches + * + * @param filp structure file * + * + * @param dentry struct dentry * + * + * @param datasync unused + * + * @return status POLLIN | POLLRDNORM + */ +int mxc_pf_fsync(struct file *filp, struct dentry *dentry, int datasync) +{ + flush_cache_all(); + outer_flush_all(); + return 0; +} + +/*! + * Post Filter driver poll function. This function implements the Linux + * file_operations.poll() API function. + * + * @param file structure file * + * + * @param wait structure poll_table * + * + * @return status POLLIN | POLLRDNORM + */ +static unsigned int mxc_pf_poll(struct file *file, poll_table * wait) +{ + wait_queue_head_t *queue = NULL; + int res = POLLIN | POLLRDNORM; + + if (down_interruptible(&pf_data.busy_lock)) + return -EINTR; + + queue = &pf_data.pf_wait; + poll_wait(file, queue, wait); + + up(&pf_data.busy_lock); + + return res; +} + +/*! + * File operation structure functions pointers. + */ +static struct file_operations mxc_pf_fops = { + .owner = THIS_MODULE, + .open = mxc_pf_open, + .release = mxc_pf_release, + .ioctl = mxc_pf_ioctl, + .poll = mxc_pf_poll, + .mmap = mxc_pf_mmap, + .fsync = mxc_pf_fsync, +}; + +static int mxc_pf_major = 0; + +/*! + * Post Filter driver module initialization function. + */ +int mxc_pf_dev_init(void) +{ + int ret = 0; + struct device *temp_class; + + mxc_pf_major = register_chrdev(0, "mxc_ipu_pf", &mxc_pf_fops); + + if (mxc_pf_major < 0) { + printk(KERN_INFO "Unable to get a major for mxc_ipu_pf"); + return mxc_pf_major; + } + + mxc_pf_class = class_create(THIS_MODULE, "mxc_ipu_pf"); + if (IS_ERR(mxc_pf_class)) { + printk(KERN_ERR "Error creating mxc_ipu_pf class.\n"); + ret = PTR_ERR(mxc_pf_class); + goto err_out1; + } + + temp_class = device_create(mxc_pf_class, NULL, MKDEV(mxc_pf_major, 0), + "mxc_ipu_pf"); + if (IS_ERR(temp_class)) { + printk(KERN_ERR "Error creating mxc_ipu_pf class device.\n"); + ret = PTR_ERR(temp_class); + goto err_out2; + } + + printk(KERN_INFO "IPU Post-filter loading\n"); + + return 0; + + err_out2: + class_destroy(mxc_pf_class); + err_out1: + unregister_chrdev(mxc_pf_major, "mxc_ipu_pf"); + return ret; +} + +/*! + * Post Filter driver module exit function. + */ +static void mxc_pf_exit(void) +{ + if (mxc_pf_major > 0) { + device_destroy(mxc_pf_class, MKDEV(mxc_pf_major, 0)); + class_destroy(mxc_pf_class); + unregister_chrdev(mxc_pf_major, "mxc_ipu_pf"); + } +} + +module_init(mxc_pf_dev_init); +module_exit(mxc_pf_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC MPEG4/H.264 Postfilter Driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/ipu3/Kconfig linux-2.6.26-lab126/drivers/mxc/ipu3/Kconfig --- linux-2.6.26/drivers/mxc/ipu3/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu3/Kconfig 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,5 @@ +config MXC_IPU_V3 + bool + +config MXC_IPU_V3D + bool diff -urN linux-2.6.26/drivers/mxc/ipu3/Makefile linux-2.6.26-lab126/drivers/mxc/ipu3/Makefile --- linux-2.6.26/drivers/mxc/ipu3/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu3/Makefile 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,4 @@ +obj-$(CONFIG_MXC_IPU_V3) = mxc_ipu.o + +mxc_ipu-objs := ipu_common.o ipu_ic.o ipu_disp.o ipu_capture.o ipu_device.o + diff -urN linux-2.6.26/drivers/mxc/ipu3/ipu_capture.c linux-2.6.26-lab126/drivers/mxc/ipu3/ipu_capture.c --- linux-2.6.26/drivers/mxc/ipu3/ipu_capture.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu3/ipu_capture.c 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,725 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_capture.c + * + * @brief IPU capture dase functions + * + * @ingroup IPU + */ +#include +#include +#include +#include +#include +#include +#include + +#include "ipu_prv.h" +#include "ipu_regs.h" + +static bool gipu_csi_get_mclk_flag[2] = {false, false}; + +/*! + * ipu_csi_init_interface + * Sets initial values for the CSI registers. + * The width and height of the sensor and the actual frame size will be + * set to the same values. + * @param width Sensor width + * @param height Sensor height + * @param pixel_fmt pixel format + * @param cfg_param ipu_csi_signal_cfg_t structure + * @param csi csi 0 or csi 1 + * + * @return 0 for success, -EINVAL for error + */ +int32_t +ipu_csi_init_interface(uint16_t width, uint16_t height, uint32_t pixel_fmt, + ipu_csi_signal_cfg_t cfg_param) +{ + uint32_t data = 0; + uint32_t csi = cfg_param.csi; + unsigned long lock_flags; + + /* Set SENS_DATA_FORMAT bits (8, 9 and 10) + RGB or YUV444 is 0 which is current value in data so not set + explicitly + This is also the default value if attempts are made to set it to + something invalid. */ + switch (pixel_fmt) { + case IPU_PIX_FMT_YUYV: + cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV; + break; + case IPU_PIX_FMT_UYVY: + cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY; + break; + case IPU_PIX_FMT_RGB24: + case IPU_PIX_FMT_BGR24: + cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB_YUV444; + break; + case IPU_PIX_FMT_GENERIC: + cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER; + break; + case IPU_PIX_FMT_RGB565: + cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB565; + break; + case IPU_PIX_FMT_RGB555: + cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB555; + break; + default: + return -EINVAL; + } + + /* Set the CSI_SENS_CONF register remaining fields */ + data |= cfg_param.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT | + cfg_param.data_fmt << CSI_SENS_CONF_DATA_FMT_SHIFT | + cfg_param.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT | + cfg_param.Vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT | + cfg_param.Hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT | + cfg_param.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT | + cfg_param.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT | + cfg_param.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT | + cfg_param.pack_tight << CSI_SENS_CONF_PACK_TIGHT_SHIFT | + cfg_param.force_eof << CSI_SENS_CONF_FORCE_EOF_SHIFT | + cfg_param.data_en_pol << CSI_SENS_CONF_DATA_EN_POL_SHIFT; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + __raw_writel(data, CSI_SENS_CONF(csi)); + + /* Setup sensor frame size */ + __raw_writel((width - 1) | (height - 1) << 16, CSI_SENS_FRM_SIZE(csi)); + + /* Set CCIR registers */ + if ((cfg_param.clk_mode == IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE) || + (cfg_param.clk_mode == IPU_CSI_CLK_MODE_CCIR656_INTERLACED)) { + _ipu_csi_ccir_err_detection_enable(csi); + __raw_writel(0x40030, CSI_CCIR_CODE_1(csi)); + __raw_writel(0xFF0000, CSI_CCIR_CODE_3(csi)); + } else if ((cfg_param.clk_mode == + IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR) || + (cfg_param.clk_mode == + IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR) || + (cfg_param.clk_mode == + IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR) || + (cfg_param.clk_mode == + IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR)) { + _ipu_csi_ccir_err_detection_enable(csi); + __raw_writel(0x40030, CSI_CCIR_CODE_1(csi)); + __raw_writel(0xFF0000, CSI_CCIR_CODE_3(csi)); + } else if ((cfg_param.clk_mode == IPU_CSI_CLK_MODE_GATED_CLK) || + (cfg_param.clk_mode == IPU_CSI_CLK_MODE_NONGATED_CLK)) { + _ipu_csi_ccir_err_detection_disable(csi); + } + + dev_dbg(g_ipu_dev, "CSI_SENS_CONF = 0x%08X\n", + __raw_readl(CSI_SENS_CONF(csi))); + dev_dbg(g_ipu_dev, "CSI_ACT_FRM_SIZE = 0x%08X\n", + __raw_readl(CSI_ACT_FRM_SIZE(csi))); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} +EXPORT_SYMBOL(ipu_csi_init_interface); + +/*! _ipu_csi_mclk_set + * + * @param pixel_clk desired pixel clock frequency in Hz + * @param csi csi 0 or csi 1 + * + * @return Returns 0 on success or negative error code on fail + */ +int _ipu_csi_mclk_set(uint32_t pixel_clk, uint32_t csi) +{ + uint32_t temp; + uint32_t div_ratio; + + div_ratio = (clk_get_rate(g_ipu_clk) / pixel_clk) - 1; + + if (div_ratio > 0xFF || div_ratio < 0) { + dev_dbg(g_ipu_dev, "The value of pixel_clk extends normal range\n"); + return -EINVAL; + } + + temp = __raw_readl(CSI_SENS_CONF(csi)); + temp &= ~CSI_SENS_CONF_DIVRATIO_MASK; + __raw_writel(temp | (div_ratio << CSI_SENS_CONF_DIVRATIO_SHIFT), + CSI_SENS_CONF(csi)); + + return 0; +} + +/*! + * ipu_csi_enable_mclk + * + * @param csi csi 0 or csi 1 + * @param flag true to enable mclk, false to disable mclk + * @param wait true to wait 100ms make clock stable, false not wait + * + * @return Returns 0 on success + */ +int ipu_csi_enable_mclk(int csi, bool flag, bool wait) +{ + if (flag) { + if (gipu_csi_get_mclk_flag[csi] == true) { + printk(KERN_WARNING "The clock of CSI%d has been enabled\n", csi); + return 0; + } + + clk_enable(g_csi_clk[csi]); + if (wait == true) + msleep(10); + gipu_csi_get_mclk_flag[csi] = true; + } else { + if (gipu_csi_get_mclk_flag[csi] == false) { + printk(KERN_WARNING "The clock of CSI%d has been disabled\n", csi); + return 0; + } + + clk_disable(g_csi_clk[csi]); + gipu_csi_get_mclk_flag[csi] = false; + } + + return 0; +} +EXPORT_SYMBOL(ipu_csi_enable_mclk); + +/*! + * ipu_csi_get_window_size + * + * @param width pointer to window width + * @param height pointer to window height + * @param csi csi 0 or csi 1 + */ +void ipu_csi_get_window_size(uint32_t *width, uint32_t *height, uint32_t csi) +{ + uint32_t reg; + unsigned long lock_flags; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(CSI_ACT_FRM_SIZE(csi)); + *width = (reg & 0xFFFF) + 1; + *height = (reg >> 16 & 0xFFFF) + 1; + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} +EXPORT_SYMBOL(ipu_csi_get_window_size); + +/*! + * ipu_csi_set_window_size + * + * @param width window width + * @param height window height + * @param csi csi 0 or csi 1 + */ +void ipu_csi_set_window_size(uint32_t width, uint32_t height, uint32_t csi) +{ + unsigned long lock_flags; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + __raw_writel((width - 1) | (height - 1) << 16, CSI_ACT_FRM_SIZE(csi)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} +EXPORT_SYMBOL(ipu_csi_set_window_size); + +/*! + * ipu_csi_set_window_pos + * + * @param left uint32 window x start + * @param top uint32 window y start + * @param csi csi 0 or csi 1 + */ +void ipu_csi_set_window_pos(uint32_t left, uint32_t top, uint32_t csi) +{ + uint32_t temp; + unsigned long lock_flags; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(CSI_OUT_FRM_CTRL(csi)); + temp &= ~(CSI_HSC_MASK | CSI_VSC_MASK); + temp |= ((top << CSI_VSC_SHIFT) | (left << CSI_HSC_SHIFT)); + __raw_writel(temp, CSI_OUT_FRM_CTRL(csi)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} +EXPORT_SYMBOL(ipu_csi_set_window_pos); + +/*! + * _ipu_csi_horizontal_downsize_enable + * Enable horizontal downsizing(decimation) by 2. + * + * @param csi csi 0 or csi 1 + */ +void _ipu_csi_horizontal_downsize_enable(uint32_t csi) +{ + uint32_t temp; + unsigned long lock_flags; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(CSI_OUT_FRM_CTRL(csi)); + temp |= CSI_HORI_DOWNSIZE_EN; + __raw_writel(temp, CSI_OUT_FRM_CTRL(csi)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} + +/*! + * _ipu_csi_horizontal_downsize_disable + * Disable horizontal downsizing(decimation) by 2. + * + * @param csi csi 0 or csi 1 + */ +void _ipu_csi_horizontal_downsize_disable(uint32_t csi) +{ + uint32_t temp; + unsigned long lock_flags; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(CSI_OUT_FRM_CTRL(csi)); + temp &= ~CSI_HORI_DOWNSIZE_EN; + __raw_writel(temp, CSI_OUT_FRM_CTRL(csi)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} + +/*! + * _ipu_csi_vertical_downsize_enable + * Enable vertical downsizing(decimation) by 2. + * + * @param csi csi 0 or csi 1 + */ +void _ipu_csi_vertical_downsize_enable(uint32_t csi) +{ + uint32_t temp; + unsigned long lock_flags; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(CSI_OUT_FRM_CTRL(csi)); + temp |= CSI_VERT_DOWNSIZE_EN; + __raw_writel(temp, CSI_OUT_FRM_CTRL(csi)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} + +/*! + * _ipu_csi_vertical_downsize_disable + * Disable vertical downsizing(decimation) by 2. + * + * @param csi csi 0 or csi 1 + */ +void _ipu_csi_vertical_downsize_disable(uint32_t csi) +{ + uint32_t temp; + unsigned long lock_flags; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(CSI_OUT_FRM_CTRL(csi)); + temp &= ~CSI_VERT_DOWNSIZE_EN; + __raw_writel(temp, CSI_OUT_FRM_CTRL(csi)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} + +/*! + * ipu_csi_set_test_generator + * + * @param active 1 for active and 0 for inactive + * @param r_value red value for the generated pattern of even pixel + * @param g_value green value for the generated pattern of even + * pixel + * @param b_value blue value for the generated pattern of even pixel + * @param pixel_clk desired pixel clock frequency in Hz + * @param csi csi 0 or csi 1 + */ +void ipu_csi_set_test_generator(bool active, uint32_t r_value, + uint32_t g_value, uint32_t b_value, uint32_t pix_clk, uint32_t csi) +{ + uint32_t temp; + unsigned long lock_flags; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(CSI_TST_CTRL(csi)); + + if (active == false) { + temp &= ~CSI_TEST_GEN_MODE_EN; + __raw_writel(temp, CSI_TST_CTRL(csi)); + } else { + /* Set sensb_mclk div_ratio*/ + _ipu_csi_mclk_set(pix_clk, csi); + + temp &= ~(CSI_TEST_GEN_R_MASK | CSI_TEST_GEN_G_MASK | + CSI_TEST_GEN_B_MASK); + temp |= CSI_TEST_GEN_MODE_EN; + temp |= (r_value << CSI_TEST_GEN_R_SHIFT) | + (g_value << CSI_TEST_GEN_G_SHIFT) | + (b_value << CSI_TEST_GEN_B_SHIFT); + __raw_writel(temp, CSI_TST_CTRL(csi)); + } + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} +EXPORT_SYMBOL(ipu_csi_set_test_generator); + +/*! + * _ipu_csi_ccir_err_detection_en + * Enable error detection and correction for + * CCIR interlaced mode with protection bit. + * + * @param csi csi 0 or csi 1 + */ +void _ipu_csi_ccir_err_detection_enable(uint32_t csi) +{ + uint32_t temp; + + temp = __raw_readl(CSI_CCIR_CODE_1(csi)); + temp |= CSI_CCIR_ERR_DET_EN; + __raw_writel(temp, CSI_CCIR_CODE_1(csi)); +} + +/*! + * _ipu_csi_ccir_err_detection_disable + * Disable error detection and correction for + * CCIR interlaced mode with protection bit. + * + * @param csi csi 0 or csi 1 + */ +void _ipu_csi_ccir_err_detection_disable(uint32_t csi) +{ + uint32_t temp; + + temp = __raw_readl(CSI_CCIR_CODE_1(csi)); + temp &= ~CSI_CCIR_ERR_DET_EN; + __raw_writel(temp, CSI_CCIR_CODE_1(csi)); +} + +/*! + * _ipu_csi_set_mipi_di + * + * @param num MIPI data identifier 0-3 handled by CSI + * @param di_val data identifier value + * @param csi csi 0 or csi 1 + * + * @return Returns 0 on success or negative error code on fail + */ +int _ipu_csi_set_mipi_di(uint32_t num, uint32_t di_val, uint32_t csi) +{ + uint32_t temp; + int retval = 0; + unsigned long lock_flags; + + if (di_val > 0xFFL) { + retval = -EINVAL; + goto err; + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(CSI_MIPI_DI(csi)); + + switch (num) { + case IPU_CSI_MIPI_DI0: + temp &= ~CSI_MIPI_DI0_MASK; + temp |= (di_val << CSI_MIPI_DI0_SHIFT); + __raw_writel(temp, CSI_MIPI_DI(csi)); + break; + case IPU_CSI_MIPI_DI1: + temp &= ~CSI_MIPI_DI1_MASK; + temp |= (di_val << CSI_MIPI_DI1_SHIFT); + __raw_writel(temp, CSI_MIPI_DI(csi)); + break; + case IPU_CSI_MIPI_DI2: + temp &= ~CSI_MIPI_DI2_MASK; + temp |= (di_val << CSI_MIPI_DI2_SHIFT); + __raw_writel(temp, CSI_MIPI_DI(csi)); + break; + case IPU_CSI_MIPI_DI3: + temp &= ~CSI_MIPI_DI3_MASK; + temp |= (di_val << CSI_MIPI_DI3_SHIFT); + __raw_writel(temp, CSI_MIPI_DI(csi)); + break; + default: + retval = -EINVAL; + goto err; + } + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +err: + return retval; +} + +/*! + * _ipu_csi_set_skip_isp + * + * @param skip select frames to be skipped and set the + * correspond bits to 1 + * @param max_ratio number of frames in a skipping set and the + * maximum value of max_ratio is 5 + * @param csi csi 0 or csi 1 + * + * @return Returns 0 on success or negative error code on fail + */ +int _ipu_csi_set_skip_isp(uint32_t skip, uint32_t max_ratio, uint32_t csi) +{ + uint32_t temp; + int retval = 0; + unsigned long lock_flags; + + if (max_ratio > 5) { + retval = -EINVAL; + goto err; + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(CSI_SKIP(csi)); + temp &= ~(CSI_MAX_RATIO_SKIP_ISP_MASK | CSI_SKIP_ISP_MASK); + temp |= (max_ratio << CSI_MAX_RATIO_SKIP_ISP_SHIFT) | + (skip << CSI_SKIP_ISP_SHIFT); + __raw_writel(temp, CSI_SKIP(csi)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +err: + return retval; +} + +/*! + * _ipu_csi_set_skip_smfc + * + * @param skip select frames to be skipped and set the + * correspond bits to 1 + * @param max_ratio number of frames in a skipping set and the + * maximum value of max_ratio is 5 + * @param id csi to smfc skipping id + * @param csi csi 0 or csi 1 + * + * @return Returns 0 on success or negative error code on fail + */ +int _ipu_csi_set_skip_smfc(uint32_t skip, uint32_t max_ratio, + uint32_t id, uint32_t csi) +{ + uint32_t temp; + int retval = 0; + unsigned long lock_flags; + + if (max_ratio > 5 || id > 3) { + retval = -EINVAL; + goto err; + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(CSI_SKIP(csi)); + temp &= ~(CSI_MAX_RATIO_SKIP_SMFC_MASK | CSI_ID_2_SKIP_MASK | + CSI_SKIP_SMFC_MASK); + temp |= (max_ratio << CSI_MAX_RATIO_SKIP_SMFC_SHIFT) | + (id << CSI_ID_2_SKIP_SHIFT) | + (skip << CSI_SKIP_SMFC_SHIFT); + __raw_writel(temp, CSI_SKIP(csi)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +err: + return retval; +} + +/*! + * _ipu_smfc_init + * Map CSI frames to IDMAC channels. + * + * @param channel IDMAC channel 0-3 + * @param mipi_id mipi id number 0-3 + * @param csi csi0 or csi1 + */ +void _ipu_smfc_init(ipu_channel_t channel, uint32_t mipi_id, uint32_t csi) +{ + uint32_t temp; + + temp = __raw_readl(SMFC_MAP); + + switch (channel) { + case CSI_MEM0: + temp &= ~SMFC_MAP_CH0_MASK; + temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH0_SHIFT; + break; + case CSI_MEM1: + temp &= ~SMFC_MAP_CH1_MASK; + temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH1_SHIFT; + break; + case CSI_MEM2: + temp &= ~SMFC_MAP_CH2_MASK; + temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH2_SHIFT; + break; + case CSI_MEM3: + temp &= ~SMFC_MAP_CH3_MASK; + temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH3_SHIFT; + break; + default: + return; + } + + __raw_writel(temp, SMFC_MAP); +} + +/*! + * _ipu_smfc_set_wmc + * Caution: The number of required channels, the enabled channels + * and the FIFO size per channel are configured restrictedly. + * + * @param channel IDMAC channel 0-3 + * @param set set 1 or clear 0 + * @param level water mark level when FIFO is on the + * relative size + */ +void _ipu_smfc_set_wmc(ipu_channel_t channel, bool set, uint32_t level) +{ + uint32_t temp; + unsigned long lock_flags; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(SMFC_WMC); + + switch (channel) { + case CSI_MEM0: + if (set == true) { + temp &= ~SMFC_WM0_SET_MASK; + temp |= level << SMFC_WM0_SET_SHIFT; + } else { + temp &= ~SMFC_WM0_CLR_MASK; + temp |= level << SMFC_WM0_CLR_SHIFT; + } + break; + case CSI_MEM1: + if (set == true) { + temp &= ~SMFC_WM1_SET_MASK; + temp |= level << SMFC_WM1_SET_SHIFT; + } else { + temp &= ~SMFC_WM1_CLR_MASK; + temp |= level << SMFC_WM1_CLR_SHIFT; + } + break; + case CSI_MEM2: + if (set == true) { + temp &= ~SMFC_WM2_SET_MASK; + temp |= level << SMFC_WM2_SET_SHIFT; + } else { + temp &= ~SMFC_WM2_CLR_MASK; + temp |= level << SMFC_WM2_CLR_SHIFT; + } + break; + case CSI_MEM3: + if (set == true) { + temp &= ~SMFC_WM3_SET_MASK; + temp |= level << SMFC_WM3_SET_SHIFT; + } else { + temp &= ~SMFC_WM3_CLR_MASK; + temp |= level << SMFC_WM3_CLR_SHIFT; + } + break; + default: + return; + } + + __raw_writel(temp, SMFC_WMC); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} + +/*! + * _ipu_smfc_set_burst_size + * + * @param channel IDMAC channel 0-3 + * @param bs burst size of IDMAC channel, + * the value programmed here shoud be BURST_SIZE-1 + */ +void _ipu_smfc_set_burst_size(ipu_channel_t channel, uint32_t bs) +{ + uint32_t temp; + unsigned long lock_flags; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(SMFC_BS); + + switch (channel) { + case CSI_MEM0: + temp &= ~SMFC_BS0_MASK; + temp |= bs << SMFC_BS0_SHIFT; + break; + case CSI_MEM1: + temp &= ~SMFC_BS1_MASK; + temp |= bs << SMFC_BS1_SHIFT; + break; + case CSI_MEM2: + temp &= ~SMFC_BS2_MASK; + temp |= bs << SMFC_BS2_SHIFT; + break; + case CSI_MEM3: + temp &= ~SMFC_BS3_MASK; + temp |= bs << SMFC_BS3_SHIFT; + break; + default: + return; + } + + __raw_writel(temp, SMFC_BS); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} + +/*! + * _ipu_csi_init + * + * @param channel IDMAC channel + * @param csi csi 0 or csi 1 + * + * @return Returns 0 on success or negative error code on fail + */ +int _ipu_csi_init(ipu_channel_t channel, uint32_t csi) +{ + uint32_t csi_sens_conf, csi_dest; + int retval = 0; + + switch (channel) { + case CSI_MEM0: + case CSI_MEM1: + case CSI_MEM2: + case CSI_MEM3: + csi_dest = CSI_DATA_DEST_IDMAC; + break; + case CSI_PRP_ENC_MEM: + case CSI_PRP_VF_MEM: + csi_dest = CSI_DATA_DEST_IC; + break; + default: + retval = -EINVAL; + goto err; + } + + csi_sens_conf = __raw_readl(CSI_SENS_CONF(csi)); + csi_sens_conf &= ~CSI_SENS_CONF_DATA_DEST_MASK; + __raw_writel(csi_sens_conf | (csi_dest << + CSI_SENS_CONF_DATA_DEST_SHIFT), CSI_SENS_CONF(csi)); +err: + return retval; +} diff -urN linux-2.6.26/drivers/mxc/ipu3/ipu_common.c linux-2.6.26-lab126/drivers/mxc/ipu3/ipu_common.c --- linux-2.6.26/drivers/mxc/ipu3/ipu_common.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu3/ipu_common.c 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,1938 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_common.c + * + * @brief This file contains the IPU driver common API functions. + * + * @ingroup IPU + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ipu_prv.h" +#include "ipu_regs.h" +#include "ipu_param_mem.h" + +struct ipu_irq_node { + irqreturn_t(*handler) (int, void *); /*!< the ISR */ + const char *name; /*!< device associated with the interrupt */ + void *dev_id; /*!< some unique information for the ISR */ + __u32 flags; /*!< not used */ +}; + +/* Globals */ +struct clk *g_ipu_clk; +bool g_ipu_clk_enabled; +struct clk *g_di_clk[2]; +struct clk *g_csi_clk[2]; +unsigned char g_dc_di_assignment[10]; +ipu_channel_t g_ipu_csi_channel[2]; +int g_ipu_irq[2]; +int g_ipu_hw_rev; +bool g_sec_chan_en[21]; +uint32_t g_channel_init_mask; +uint32_t g_channel_enable_mask; +DEFINE_SPINLOCK(ipu_lock); +struct device *g_ipu_dev; + +static struct ipu_irq_node ipu_irq_list[IPU_IRQ_COUNT]; +static const char driver_name[] = "mxc_ipu"; + +static int ipu_dc_use_count; +static int ipu_dp_use_count; +static int ipu_dmfc_use_count; +static int ipu_smfc_use_count; +static int ipu_ic_use_count; +static int ipu_rot_use_count; +static int ipu_di_use_count[2]; +static int ipu_csi_use_count[2]; + +/* for power gating */ +static uint32_t ipu_conf_reg; +static uint32_t ic_conf_reg; +static uint32_t ipu_cha_db_mode_reg[4]; +static uint32_t ipu_cha_cur_buf_reg[4]; +static uint32_t idma_enable_reg[2]; +static uint32_t buf_ready_reg[8]; + +u32 *ipu_cm_reg; +u32 *ipu_idmac_reg; +u32 *ipu_dp_reg; +u32 *ipu_ic_reg; +u32 *ipu_dc_reg; +u32 *ipu_dc_tmpl_reg; +u32 *ipu_dmfc_reg; +u32 *ipu_di_reg[2]; +u32 *ipu_smfc_reg; +u32 *ipu_csi_reg[2]; +u32 *ipu_cpmem_base; +u32 *ipu_tpmem_base; +u32 *ipu_disp_base[2]; + +/* Static functions */ +static irqreturn_t ipu_irq_handler(int irq, void *desc); + +static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type) +{ + return ((uint32_t) ch >> (6 * type)) & 0x3F; +}; + +static inline int _ipu_is_ic_chan(uint32_t dma_chan) +{ + return ((dma_chan >= 11) && (dma_chan <= 22)); +} + +static inline int _ipu_is_irt_chan(uint32_t dma_chan) +{ + return ((dma_chan >= 45) && (dma_chan <= 50)); +} + +static inline int _ipu_is_dmfc_chan(uint32_t dma_chan) +{ + return ((dma_chan >= 23) && (dma_chan <= 29)); +} + +static inline int _ipu_is_smfc_chan(uint32_t dma_chan) +{ + return ((dma_chan >= 0) && (dma_chan <= 3)); +} + +#define idma_is_valid(ch) (ch != NO_DMA) +#define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0) +#define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma)) + +/*! + * This function is called by the driver framework to initialize the IPU + * hardware. + * + * @param dev The device structure for the IPU passed in by the + * driver framework. + * + * @return Returns 0 on success or negative error code on error + */ +static int ipu_probe(struct platform_device *pdev) +{ + struct resource *res; + struct mxc_ipu_config *plat_data = pdev->dev.platform_data; + unsigned long ipu_base; + + spin_lock_init(&ipu_lock); + + g_ipu_hw_rev = plat_data->rev; + + g_ipu_dev = &pdev->dev; + + /* Register IPU interrupts */ + g_ipu_irq[0] = platform_get_irq(pdev, 0); + if (g_ipu_irq[0] < 0) + return -EINVAL; + + if (request_irq(g_ipu_irq[0], ipu_irq_handler, 0, pdev->name, 0) != 0) { + dev_err(g_ipu_dev, "request SYNC interrupt failed\n"); + return -EBUSY; + } + /* Some platforms have 2 IPU interrupts */ + g_ipu_irq[1] = platform_get_irq(pdev, 1); + if (g_ipu_irq[1] >= 0) { + if (request_irq + (g_ipu_irq[1], ipu_irq_handler, 0, pdev->name, 0) != 0) { + dev_err(g_ipu_dev, "request ERR interrupt failed\n"); + return -EBUSY; + } + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (IS_ERR(res)) + return -ENODEV; + + ipu_base = res->start; + ipu_cm_reg = ioremap(ipu_base + IPU_CM_REG_BASE, PAGE_SIZE); + ipu_ic_reg = ioremap(ipu_base + IPU_IC_REG_BASE, PAGE_SIZE); + ipu_idmac_reg = ioremap(ipu_base + IPU_IDMAC_REG_BASE, PAGE_SIZE); + /* DP Registers are accessed thru the SRM */ + ipu_dp_reg = ioremap(ipu_base + IPU_SRM_REG_BASE, PAGE_SIZE); + ipu_dc_reg = ioremap(ipu_base + IPU_DC_REG_BASE, PAGE_SIZE); + ipu_dmfc_reg = ioremap(ipu_base + IPU_DMFC_REG_BASE, PAGE_SIZE); + ipu_di_reg[0] = ioremap(ipu_base + IPU_DI0_REG_BASE, PAGE_SIZE); + ipu_di_reg[1] = ioremap(ipu_base + IPU_DI1_REG_BASE, PAGE_SIZE); + ipu_smfc_reg = ioremap(ipu_base + IPU_SMFC_REG_BASE, PAGE_SIZE); + ipu_csi_reg[0] = ioremap(ipu_base + IPU_CSI0_REG_BASE, PAGE_SIZE); + ipu_csi_reg[1] = ioremap(ipu_base + IPU_CSI1_REG_BASE, PAGE_SIZE); + ipu_cpmem_base = ioremap(ipu_base + IPU_CPMEM_REG_BASE, PAGE_SIZE); + ipu_tpmem_base = ioremap(ipu_base + IPU_TPM_REG_BASE, SZ_64K); + ipu_dc_tmpl_reg = ioremap(ipu_base + IPU_DC_TMPL_REG_BASE, SZ_128K); + ipu_disp_base[1] = ioremap(ipu_base + IPU_DISP1_BASE, SZ_4K); + + dev_dbg(g_ipu_dev, "IPU CM Regs = %p\n", ipu_cm_reg); + dev_dbg(g_ipu_dev, "IPU IC Regs = %p\n", ipu_ic_reg); + dev_dbg(g_ipu_dev, "IPU IDMAC Regs = %p\n", ipu_idmac_reg); + dev_dbg(g_ipu_dev, "IPU DP Regs = %p\n", ipu_dp_reg); + dev_dbg(g_ipu_dev, "IPU DC Regs = %p\n", ipu_dc_reg); + dev_dbg(g_ipu_dev, "IPU DMFC Regs = %p\n", ipu_dmfc_reg); + dev_dbg(g_ipu_dev, "IPU DI0 Regs = %p\n", ipu_di_reg[0]); + dev_dbg(g_ipu_dev, "IPU DI1 Regs = %p\n", ipu_di_reg[1]); + dev_dbg(g_ipu_dev, "IPU SMFC Regs = %p\n", ipu_smfc_reg); + dev_dbg(g_ipu_dev, "IPU CSI0 Regs = %p\n", ipu_csi_reg[0]); + dev_dbg(g_ipu_dev, "IPU CSI1 Regs = %p\n", ipu_csi_reg[1]); + dev_dbg(g_ipu_dev, "IPU CPMem = %p\n", ipu_cpmem_base); + dev_dbg(g_ipu_dev, "IPU TPMem = %p\n", ipu_tpmem_base); + dev_dbg(g_ipu_dev, "IPU DC Template Mem = %p\n", ipu_dc_tmpl_reg); + dev_dbg(g_ipu_dev, "IPU Display Region 1 Mem = %p\n", ipu_disp_base[1]); + + /* Enable IPU and CSI clocks */ + /* Get IPU clock freq */ + g_ipu_clk = clk_get(&pdev->dev, "ipu_clk"); + dev_dbg(g_ipu_dev, "ipu_clk = %lu\n", clk_get_rate(g_ipu_clk)); + + clk_enable(g_ipu_clk); + + g_di_clk[0] = plat_data->di_clk[0]; + g_di_clk[1] = plat_data->di_clk[1]; + + g_csi_clk[0] = clk_get(&pdev->dev, "csi_mclk1"); + g_csi_clk[1] = clk_get(&pdev->dev, "csi_mclk2"); + + __raw_writel(0x807FFFFF, IPU_MEM_RST); + while (__raw_readl(IPU_MEM_RST) & 0x80000000) ; + + _ipu_init_dc_mappings(); + + /* Enable error interrupts by default */ + __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(5)); + __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(6)); + __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(9)); + __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(10)); + + /* DMFC Init */ + _ipu_dmfc_init(); + + /* Set sync refresh channels as high priority */ + __raw_writel(0x18800000L, IDMAC_CHA_PRI(0)); + + /* Set MCU_T to divide MCU access window into 2 */ + __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN); + + clk_disable(g_ipu_clk); + + register_ipu_device(); + + return 0; +} + +int ipu_remove(struct platform_device *pdev) +{ + if (g_ipu_irq[0]) + free_irq(g_ipu_irq[0], 0); + if (g_ipu_irq[1]) + free_irq(g_ipu_irq[1], 0); + + clk_put(g_ipu_clk); + + iounmap(ipu_cm_reg); + iounmap(ipu_ic_reg); + iounmap(ipu_idmac_reg); + iounmap(ipu_dc_reg); + iounmap(ipu_dp_reg); + iounmap(ipu_dmfc_reg); + iounmap(ipu_di_reg[0]); + iounmap(ipu_di_reg[1]); + iounmap(ipu_smfc_reg); + iounmap(ipu_csi_reg[0]); + iounmap(ipu_csi_reg[1]); + iounmap(ipu_cpmem_base); + iounmap(ipu_tpmem_base); + iounmap(ipu_dc_tmpl_reg); + iounmap(ipu_disp_base[1]); + + return 0; +} + +void ipu_dump_registers(void) +{ + printk(KERN_DEBUG "IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF)); + printk(KERN_DEBUG "IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF)); + printk(KERN_DEBUG "IDMAC_CHA_EN1 = \t0x%08X\n", + __raw_readl(IDMAC_CHA_EN(0))); + printk(KERN_DEBUG "IDMAC_CHA_EN2 = \t0x%08X\n", + __raw_readl(IDMAC_CHA_EN(32))); + printk(KERN_DEBUG "IDMAC_CHA_PRI1 = \t0x%08X\n", + __raw_readl(IDMAC_CHA_PRI(0))); + printk(KERN_DEBUG "IDMAC_CHA_PRI2 = \t0x%08X\n", + __raw_readl(IDMAC_CHA_PRI(32))); + printk(KERN_DEBUG "IDMAC_BAND_EN1 = \t0x%08X\n", + __raw_readl(IDMAC_BAND_EN(0))); + printk(KERN_DEBUG "IDMAC_BAND_EN2 = \t0x%08X\n", + __raw_readl(IDMAC_BAND_EN(32))); + printk(KERN_DEBUG "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n", + __raw_readl(IPU_CHA_DB_MODE_SEL(0))); + printk(KERN_DEBUG "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n", + __raw_readl(IPU_CHA_DB_MODE_SEL(32))); + printk(KERN_DEBUG "DMFC_WR_CHAN = \t0x%08X\n", + __raw_readl(DMFC_WR_CHAN)); + printk(KERN_DEBUG "DMFC_WR_CHAN_DEF = \t0x%08X\n", + __raw_readl(DMFC_WR_CHAN_DEF)); + printk(KERN_DEBUG "DMFC_DP_CHAN = \t0x%08X\n", + __raw_readl(DMFC_DP_CHAN)); + printk(KERN_DEBUG "DMFC_DP_CHAN_DEF = \t0x%08X\n", + __raw_readl(DMFC_DP_CHAN_DEF)); + printk(KERN_DEBUG "DMFC_IC_CTRL = \t0x%08X\n", + __raw_readl(DMFC_IC_CTRL)); + printk(KERN_DEBUG "IPU_FS_PROC_FLOW1 = \t0x%08X\n", + __raw_readl(IPU_FS_PROC_FLOW1)); + printk(KERN_DEBUG "IPU_FS_PROC_FLOW2 = \t0x%08X\n", + __raw_readl(IPU_FS_PROC_FLOW2)); + printk(KERN_DEBUG "IPU_FS_PROC_FLOW3 = \t0x%08X\n", + __raw_readl(IPU_FS_PROC_FLOW3)); + printk(KERN_DEBUG "IPU_FS_DISP_FLOW1 = \t0x%08X\n", + __raw_readl(IPU_FS_DISP_FLOW1)); +} + +/*! + * This function is called to initialize a logical IPU channel. + * + * @param channel Input parameter for the logical channel ID to init. + * + * @param params Input parameter containing union of channel + * initialization parameters. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params) +{ + int ret = 0; + uint32_t ipu_conf; + uint32_t reg; + unsigned long lock_flags; + + dev_dbg(g_ipu_dev, "init channel = %d\n", IPU_CHAN_ID(channel)); + + /* re-enable error interrupts every time a channel is initialized */ + __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(5)); + __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(6)); + __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(9)); + __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(10)); + + if (g_ipu_clk_enabled == false) { + g_ipu_clk_enabled = true; + clk_enable(g_ipu_clk); + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) { + dev_err(g_ipu_dev, "Warning: channel already initialized %d\n", + IPU_CHAN_ID(channel)); + } + + switch (channel) { + case CSI_MEM0: + case CSI_MEM1: + case CSI_MEM2: + case CSI_MEM3: + if (params->csi_mem.csi > 1) { + ret = -EINVAL; + goto err; + } + + ipu_smfc_use_count++; + ipu_csi_use_count[params->csi_mem.csi]++; + g_ipu_csi_channel[params->csi_mem.csi] = channel; + + /*SMFC setting*/ + if (params->csi_mem.mipi_en) { + ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + + params->csi_mem.csi)); + _ipu_smfc_init(channel, params->csi_mem.mipi_id, + params->csi_mem.csi); + } else { + ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + + params->csi_mem.csi)); + _ipu_smfc_init(channel, 0, params->csi_mem.csi); + } + + /*CSI data (include compander) dest*/ + _ipu_csi_init(channel, params->csi_mem.csi); + break; + case CSI_PRP_ENC_MEM: + if (params->csi_prp_enc_mem.csi > 1) { + ret = -EINVAL; + goto err; + } + + ipu_ic_use_count++; + ipu_csi_use_count[params->csi_prp_enc_mem.csi]++; + g_ipu_csi_channel[params->csi_prp_enc_mem.csi] = channel; + + /*Without SMFC, CSI only support parallel data source*/ + ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + + params->csi_prp_enc_mem.csi)); + + /*CSI0/1 feed into IC*/ + ipu_conf &= ~IPU_CONF_IC_INPUT; + if (params->csi_prp_enc_mem.csi) + ipu_conf |= IPU_CONF_CSI_SEL; + else + ipu_conf &= ~IPU_CONF_CSI_SEL; + + /*PRP skip buffer in memory, only valid when RWS_EN is true*/ + reg = __raw_readl(IPU_FS_PROC_FLOW1); + __raw_writel(reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1); + + /*CSI data (include compander) dest*/ + _ipu_csi_init(channel, params->csi_prp_enc_mem.csi); + _ipu_ic_init_prpenc(params, true); + break; + case CSI_PRP_VF_MEM: + if (params->csi_prp_vf_mem.csi > 1) { + ret = -EINVAL; + goto err; + } + + ipu_ic_use_count++; + ipu_csi_use_count[params->csi_prp_vf_mem.csi]++; + g_ipu_csi_channel[params->csi_prp_vf_mem.csi] = channel; + + /*Without SMFC, CSI only support parallel data source*/ + ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + + params->csi_prp_vf_mem.csi)); + + /*CSI0/1 feed into IC*/ + ipu_conf &= ~IPU_CONF_IC_INPUT; + if (params->csi_prp_vf_mem.csi) + ipu_conf |= IPU_CONF_CSI_SEL; + else + ipu_conf &= ~IPU_CONF_CSI_SEL; + + /*PRP skip buffer in memory, only valid when RWS_EN is true*/ + reg = __raw_readl(IPU_FS_PROC_FLOW1); + __raw_writel(reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1); + + /*CSI data (include compander) dest*/ + _ipu_csi_init(channel, params->csi_prp_vf_mem.csi); + _ipu_ic_init_prpvf(params, true); + break; + case MEM_PRP_VF_MEM: + ipu_ic_use_count++; + reg = __raw_readl(IPU_FS_PROC_FLOW1); + __raw_writel(reg | FS_VF_IN_VALID, IPU_FS_PROC_FLOW1); + + if (params->mem_prp_vf_mem.graphics_combine_en) + g_sec_chan_en[IPU_CHAN_ID(channel)] = true; + + _ipu_ic_init_prpvf(params, false); + break; + case MEM_ROT_VF_MEM: + ipu_ic_use_count++; + ipu_rot_use_count++; + _ipu_ic_init_rotate_vf(params); + break; + case MEM_PRP_ENC_MEM: + ipu_ic_use_count++; + reg = __raw_readl(IPU_FS_PROC_FLOW1); + __raw_writel(reg | FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1); + _ipu_ic_init_prpenc(params, false); + break; + case MEM_ROT_ENC_MEM: + ipu_ic_use_count++; + ipu_rot_use_count++; + _ipu_ic_init_rotate_enc(params); + break; + case MEM_PP_MEM: + if (params->mem_pp_mem.graphics_combine_en) + g_sec_chan_en[IPU_CHAN_ID(channel)] = true; + _ipu_ic_init_pp(params); + ipu_ic_use_count++; + break; + case MEM_ROT_PP_MEM: + _ipu_ic_init_rotate_pp(params); + ipu_ic_use_count++; + ipu_rot_use_count++; + break; + case MEM_DC_SYNC: + if (params->mem_dc_sync.di > 1) { + ret = -EINVAL; + goto err; + } + + g_dc_di_assignment[1] = params->mem_dc_sync.di; + _ipu_dc_init(1, params->mem_dc_sync.di, + params->mem_dc_sync.interlaced); + ipu_di_use_count[params->mem_dc_sync.di]++; + ipu_dc_use_count++; + ipu_dmfc_use_count++; + break; + case MEM_BG_SYNC: + if (params->mem_dp_bg_sync.di > 1) { + ret = -EINVAL; + goto err; + } + + g_dc_di_assignment[5] = params->mem_dp_bg_sync.di; + _ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt, + params->mem_dp_bg_sync.out_pixel_fmt); + _ipu_dc_init(5, params->mem_dp_bg_sync.di, + params->mem_dp_bg_sync.interlaced); + ipu_di_use_count[params->mem_dp_bg_sync.di]++; + ipu_dc_use_count++; + ipu_dp_use_count++; + ipu_dmfc_use_count++; + break; + case MEM_FG_SYNC: + _ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt, + params->mem_dp_fg_sync.out_pixel_fmt); + ipu_dc_use_count++; + ipu_dp_use_count++; + ipu_dmfc_use_count++; + break; + case DIRECT_ASYNC0: + if (params->direct_async.di > 1) { + ret = -EINVAL; + goto err; + } + + g_dc_di_assignment[8] = params->direct_async.di; + _ipu_dc_init(8, params->direct_async.di, false); + ipu_di_use_count[params->direct_async.di]++; + ipu_dc_use_count++; + break; + case DIRECT_ASYNC1: + if (params->direct_async.di > 1) { + ret = -EINVAL; + goto err; + } + + g_dc_di_assignment[9] = params->direct_async.di; + _ipu_dc_init(9, params->direct_async.di, false); + ipu_di_use_count[params->direct_async.di]++; + ipu_dc_use_count++; + break; + default: + dev_err(g_ipu_dev, "Missing channel initialization\n"); + break; + } + + /* Enable IPU sub module */ + g_channel_init_mask |= 1L << IPU_CHAN_ID(channel); + ipu_conf = __raw_readl(IPU_CONF); + if (ipu_ic_use_count == 1) + ipu_conf |= IPU_CONF_IC_EN; + if (ipu_rot_use_count == 1) + ipu_conf |= IPU_CONF_ROT_EN; + if (ipu_dc_use_count == 1) + ipu_conf |= IPU_CONF_DC_EN; + if (ipu_dp_use_count == 1) + ipu_conf |= IPU_CONF_DP_EN; + if (ipu_dmfc_use_count == 1) + ipu_conf |= IPU_CONF_DMFC_EN; + if (ipu_di_use_count[0] == 1) { + ipu_conf |= IPU_CONF_DI0_EN; + clk_enable(g_di_clk[0]); + } + if (ipu_di_use_count[1] == 1) { + ipu_conf |= IPU_CONF_DI1_EN; + clk_enable(g_di_clk[1]); + } + if (ipu_smfc_use_count == 1) + ipu_conf |= IPU_CONF_SMFC_EN; + if (ipu_csi_use_count[0] == 1) + ipu_conf |= IPU_CONF_CSI0_EN; + if (ipu_csi_use_count[1] == 1) + ipu_conf |= IPU_CONF_CSI1_EN; + + __raw_writel(ipu_conf, IPU_CONF); + +err: + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return ret; +} +EXPORT_SYMBOL(ipu_init_channel); + +/*! + * This function is called to uninitialize a logical IPU channel. + * + * @param channel Input parameter for the logical channel ID to uninit. + */ +void ipu_uninit_channel(ipu_channel_t channel) +{ + unsigned long lock_flags; + uint32_t reg; + uint32_t in_dma, out_dma = 0; + uint32_t ipu_conf; + + if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) { + dev_err(g_ipu_dev, "Channel already uninitialized %d\n", + IPU_CHAN_ID(channel)); + return; + } + + /* Make sure channel is disabled */ + /* Get input and output dma channels */ + in_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + out_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER); + + if (idma_is_set(IDMAC_CHA_EN, in_dma) || + idma_is_set(IDMAC_CHA_EN, out_dma)) { + dev_err(g_ipu_dev, + "Channel %d is not disabled, disable first\n", + IPU_CHAN_ID(channel)); + return; + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + /* Reset the double buffer */ + reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma)); + __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma)); + reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma)); + __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma)); + + g_sec_chan_en[IPU_CHAN_ID(channel)] = false; + + switch (channel) { + case CSI_MEM0: + case CSI_MEM1: + case CSI_MEM2: + case CSI_MEM3: + ipu_smfc_use_count--; + if (g_ipu_csi_channel[0] == channel) { + g_ipu_csi_channel[0] = CHAN_NONE; + ipu_csi_use_count[0]--; + } else if (g_ipu_csi_channel[1] == channel) { + g_ipu_csi_channel[1] = CHAN_NONE; + ipu_csi_use_count[1]--; + } + break; + case CSI_PRP_ENC_MEM: + ipu_ic_use_count--; + _ipu_ic_uninit_prpenc(); + if (g_ipu_csi_channel[0] == channel) { + g_ipu_csi_channel[0] = CHAN_NONE; + ipu_csi_use_count[0]--; + } else if (g_ipu_csi_channel[1] == channel) { + g_ipu_csi_channel[1] = CHAN_NONE; + ipu_csi_use_count[1]--; + } + break; + case CSI_PRP_VF_MEM: + ipu_ic_use_count--; + _ipu_ic_uninit_prpvf(); + if (g_ipu_csi_channel[0] == channel) { + g_ipu_csi_channel[0] = CHAN_NONE; + ipu_csi_use_count[0]--; + } else if (g_ipu_csi_channel[1] == channel) { + g_ipu_csi_channel[1] = CHAN_NONE; + ipu_csi_use_count[1]--; + } + break; + case MEM_PRP_VF_MEM: + ipu_ic_use_count--; + _ipu_ic_uninit_prpvf(); + reg = __raw_readl(IPU_FS_PROC_FLOW1); + __raw_writel(reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1); + break; + case MEM_ROT_VF_MEM: + ipu_rot_use_count--; + ipu_ic_use_count--; + _ipu_ic_uninit_rotate_vf(); + break; + case MEM_PRP_ENC_MEM: + ipu_ic_use_count--; + _ipu_ic_uninit_prpenc(); + reg = __raw_readl(IPU_FS_PROC_FLOW1); + __raw_writel(reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1); + break; + case MEM_ROT_ENC_MEM: + ipu_rot_use_count--; + ipu_ic_use_count--; + _ipu_ic_uninit_rotate_enc(); + break; + case MEM_PP_MEM: + ipu_ic_use_count--; + _ipu_ic_uninit_pp(); + break; + case MEM_ROT_PP_MEM: + ipu_rot_use_count--; + ipu_ic_use_count--; + _ipu_ic_uninit_rotate_pp(); + break; + case MEM_DC_SYNC: + _ipu_dc_uninit(1); + ipu_di_use_count[g_dc_di_assignment[1]]--; + ipu_dc_use_count--; + ipu_dmfc_use_count--; + break; + case MEM_BG_SYNC: + _ipu_dp_uninit(channel); + _ipu_dc_uninit(5); + ipu_di_use_count[g_dc_di_assignment[5]]--; + ipu_dc_use_count--; + ipu_dp_use_count--; + ipu_dmfc_use_count--; + break; + case MEM_FG_SYNC: + _ipu_dp_uninit(channel); + ipu_dc_use_count--; + ipu_dp_use_count--; + ipu_dmfc_use_count--; + break; + case DIRECT_ASYNC0: + _ipu_dc_uninit(8); + ipu_di_use_count[g_dc_di_assignment[8]]--; + ipu_dc_use_count--; + break; + case DIRECT_ASYNC1: + _ipu_dc_uninit(9); + ipu_di_use_count[g_dc_di_assignment[9]]--; + ipu_dc_use_count--; + break; + default: + break; + } + + g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel)); + + ipu_conf = __raw_readl(IPU_CONF); + + if (ipu_ic_use_count == 0) + ipu_conf &= ~IPU_CONF_IC_EN; + if (ipu_rot_use_count == 0) + ipu_conf &= ~IPU_CONF_ROT_EN; + if (ipu_dc_use_count == 0) + ipu_conf &= ~IPU_CONF_DC_EN; + if (ipu_dp_use_count == 0) + ipu_conf &= ~IPU_CONF_DP_EN; + if (ipu_dmfc_use_count == 0) + ipu_conf &= ~IPU_CONF_DMFC_EN; + if (ipu_di_use_count[0] == 0) { + ipu_conf &= ~IPU_CONF_DI0_EN; + clk_disable(g_di_clk[0]); + } + if (ipu_di_use_count[1] == 0) { + ipu_conf &= ~IPU_CONF_DI1_EN; + clk_disable(g_di_clk[1]); + } + if (ipu_smfc_use_count == 0) + ipu_conf &= ~IPU_CONF_SMFC_EN; + if (ipu_csi_use_count[0] == 0) + ipu_conf &= ~IPU_CONF_CSI0_EN; + if (ipu_csi_use_count[1] == 0) + ipu_conf &= ~IPU_CONF_CSI1_EN; + + __raw_writel(ipu_conf, IPU_CONF); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + if (ipu_conf == 0) { + clk_disable(g_ipu_clk); + g_ipu_clk_enabled = false; + } + + WARN_ON(ipu_ic_use_count < 0); + WARN_ON(ipu_rot_use_count < 0); + WARN_ON(ipu_dc_use_count < 0); + WARN_ON(ipu_dp_use_count < 0); + WARN_ON(ipu_dmfc_use_count < 0); + WARN_ON(ipu_smfc_use_count < 0); +} +EXPORT_SYMBOL(ipu_uninit_channel); + +/*! + * This function is called to initialize a buffer for logical IPU channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to initialize. + * + * @param pixel_fmt Input parameter for pixel format of buffer. + * Pixel format is a FOURCC ASCII code. + * + * @param width Input parameter for width of buffer in pixels. + * + * @param height Input parameter for height of buffer in pixels. + * + * @param stride Input parameter for stride length of buffer + * in pixels. + * + * @param rot_mode Input parameter for rotation setting of buffer. + * A rotation setting other than + * IPU_ROTATE_VERT_FLIP + * should only be used for input buffers of + * rotation channels. + * + * @param phyaddr_0 Input parameter buffer 0 physical address. + * + * @param phyaddr_1 Input parameter buffer 1 physical address. + * Setting this to a value other than NULL enables + * double buffering mode. + * + * @param u private u offset for additional cropping, + * zero if not used. + * + * @param v private v offset for additional cropping, + * zero if not used. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + ipu_rotate_mode_t rot_mode, + dma_addr_t phyaddr_0, dma_addr_t phyaddr_1, + uint32_t u, uint32_t v) +{ + unsigned long lock_flags; + uint32_t reg; + uint32_t dma_chan; + uint32_t burst_size; + + dma_chan = channel_2_dma(channel, type); + if (!idma_is_valid(dma_chan)) + return -EINVAL; + + if (stride < width * bytes_per_pixel(pixel_fmt)) + stride = width * bytes_per_pixel(pixel_fmt); + + if (stride % 4) { + dev_err(g_ipu_dev, + "Stride not 32-bit aligned, stride = %d\n", stride); + return -EINVAL; + } + /* IC & IRT channels' width must be multiple of 8 pixels */ + if ((_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan)) + && (width % 8)) { + dev_err(g_ipu_dev, "Width must be 8 pixel multiple\n"); + return -EINVAL; + } + + /* Build parameter memory data for DMA channel */ + _ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0, + phyaddr_0, phyaddr_1); + if (rot_mode) + _ipu_ch_param_set_rotation(dma_chan, rot_mode); + + /* IC and ROT channels have restriction of 8 or 16 pix burst length */ + if (_ipu_is_ic_chan(dma_chan)) { + if ((width % 16) == 0) + _ipu_ch_param_set_burst_size(dma_chan, 16); + else + _ipu_ch_param_set_burst_size(dma_chan, 8); + } else if (_ipu_is_irt_chan(dma_chan)) { + _ipu_ch_param_set_burst_size(dma_chan, 8); + _ipu_ch_param_set_block_mode(dma_chan); + } else if (_ipu_is_dmfc_chan(dma_chan)) + _ipu_dmfc_set_wait4eot(dma_chan, width); + + if (_ipu_chan_is_interlaced(channel)) + _ipu_ch_param_set_interlaced_scan(dma_chan); + + if (_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan)) { + burst_size = _ipu_ch_param_get_burst_size(dma_chan); + _ipu_ic_idma_init(dma_chan, width, height, burst_size, + rot_mode); + } else if (_ipu_is_smfc_chan(dma_chan)) { + burst_size = _ipu_ch_param_get_burst_size(dma_chan); + if ((pixel_fmt == IPU_PIX_FMT_GENERIC) && + ((_ipu_ch_param_get_bpp(dma_chan) == 5) || + (_ipu_ch_param_get_bpp(dma_chan) == 3))) + burst_size = burst_size >> 4; + else + burst_size = burst_size >> 2; + _ipu_smfc_set_burst_size(channel, burst_size-1); + } + + if (idma_is_set(IDMAC_CHA_PRI, dma_chan)) + _ipu_ch_param_set_high_priority(dma_chan); + + _ipu_ch_param_dump(dma_chan); + + spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan)); + if (phyaddr_1) + reg |= idma_mask(dma_chan); + else + reg &= ~idma_mask(dma_chan); + __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan)); + + /* Reset to buffer 0 */ + __raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} +EXPORT_SYMBOL(ipu_init_channel_buffer); + +/*! + * This function is called to update the physical address of a buffer for + * a logical IPU channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to initialize. + * + * @param bufNum Input parameter for buffer number to update. + * 0 or 1 are the only valid values. + * + * @param phyaddr Input parameter buffer physical address. + * + * @return This function returns 0 on success or negative error code on + * fail. This function will fail if the buffer is set to ready. + */ +int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum, dma_addr_t phyaddr) +{ + uint32_t reg; + int ret = 0; + unsigned long lock_flags; + uint32_t dma_chan = channel_2_dma(channel, type); + + if (dma_chan == IDMA_CHAN_INVALID) + return -EINVAL; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + if (bufNum == 0) + reg = __raw_readl(IPU_CHA_BUF0_RDY(dma_chan)); + else + reg = __raw_readl(IPU_CHA_BUF1_RDY(dma_chan)); + + if ((reg & idma_mask(dma_chan)) == 0) + _ipu_ch_param_set_buffer(dma_chan, bufNum, phyaddr); + else + ret = -EACCES; + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return ret; +} +EXPORT_SYMBOL(ipu_update_channel_buffer); + +/*! + * This function is called to set a channel's buffer as ready. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to initialize. + * + * @param bufNum Input parameter for which buffer number set to + * ready state. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_select_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum) +{ + uint32_t dma_chan = channel_2_dma(channel, type); + + if (dma_chan == IDMA_CHAN_INVALID) + return -EINVAL; + + if (bufNum == 0) { + /*Mark buffer 0 as ready. */ + __raw_writel(idma_mask(dma_chan), IPU_CHA_BUF0_RDY(dma_chan)); + } else { + /*Mark buffer 1 as ready. */ + __raw_writel(idma_mask(dma_chan), IPU_CHA_BUF1_RDY(dma_chan)); + } + return 0; +} +EXPORT_SYMBOL(ipu_select_buffer); + +#define NA -1 +static int proc_dest_sel[] = + { 0, 1, 1, 3, 5, 5, 4, 7, 8, 9, 10, 11, 12, 14, 15 }; +static int proc_src_sel[] = { 0, 6, 7, 6, 7, 8, 5, NA, NA, NA, +NA, NA, NA, NA, NA, 1, 2, 3, 4, 7, 8 }; +static int disp_src_sel[] = { 0, 6, 7, 8, 3, 4, 5, NA, NA, NA, +NA, NA, NA, NA, NA, 1, NA, 2, NA, 3, 4 }; + +/*! + * This function links 2 channels together for automatic frame + * synchronization. The output of the source channel is linked to the input of + * the destination channel. + * + * @param src_ch Input parameter for the logical channel ID of + * the source channel. + * + * @param dest_ch Input parameter for the logical channel ID of + * the destination channel. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_link_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch) +{ + int retval = 0; + unsigned long lock_flags; + uint32_t fs_proc_flow1; + uint32_t fs_proc_flow2; + uint32_t fs_proc_flow3; + uint32_t fs_disp_flow1; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + fs_proc_flow1 = __raw_readl(IPU_FS_PROC_FLOW1); + fs_proc_flow2 = __raw_readl(IPU_FS_PROC_FLOW2); + fs_proc_flow3 = __raw_readl(IPU_FS_PROC_FLOW3); + fs_disp_flow1 = __raw_readl(IPU_FS_DISP_FLOW1); + + switch (src_ch) { + case CSI_MEM0: + fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK; + fs_proc_flow3 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_SMFC0_DEST_SEL_OFFSET; + break; + case CSI_MEM1: + fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK; + fs_proc_flow3 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_SMFC1_DEST_SEL_OFFSET; + break; + case CSI_MEM2: + fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK; + fs_proc_flow3 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_SMFC2_DEST_SEL_OFFSET; + break; + case CSI_MEM3: + fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK; + fs_proc_flow3 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_SMFC3_DEST_SEL_OFFSET; + break; + case CSI_PRP_ENC_MEM: + fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK; + fs_proc_flow2 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_PRPENC_DEST_SEL_OFFSET; + break; + case CSI_PRP_VF_MEM: + fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK; + fs_proc_flow2 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_PRPVF_DEST_SEL_OFFSET; + break; + case MEM_PP_MEM: + fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK; + fs_proc_flow2 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_PP_DEST_SEL_OFFSET; + break; + case MEM_ROT_PP_MEM: + fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK; + fs_proc_flow2 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_PP_ROT_DEST_SEL_OFFSET; + break; + case MEM_PRP_ENC_MEM: + fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK; + fs_proc_flow2 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_PRPENC_DEST_SEL_OFFSET; + break; + case MEM_ROT_ENC_MEM: + fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK; + fs_proc_flow2 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_PRPENC_ROT_DEST_SEL_OFFSET; + break; + case MEM_PRP_VF_MEM: + fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK; + fs_proc_flow2 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_PRPVF_DEST_SEL_OFFSET; + break; + case MEM_ROT_VF_MEM: + fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK; + fs_proc_flow2 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_PRPVF_ROT_DEST_SEL_OFFSET; + break; + default: + retval = -EINVAL; + goto err; + } + + switch (dest_ch) { + case MEM_PP_MEM: + fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK; + fs_proc_flow1 |= + proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PP_SRC_SEL_OFFSET; + break; + case MEM_ROT_PP_MEM: + fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK; + fs_proc_flow1 |= + proc_src_sel[IPU_CHAN_ID(src_ch)] << + FS_PP_ROT_SRC_SEL_OFFSET; + break; + case MEM_PRP_ENC_MEM: + fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK; + fs_proc_flow1 |= + proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET; + break; + case MEM_ROT_ENC_MEM: + fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK; + fs_proc_flow1 |= + proc_src_sel[IPU_CHAN_ID(src_ch)] << + FS_PRPENC_ROT_SRC_SEL_OFFSET; + break; + case MEM_PRP_VF_MEM: + fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK; + fs_proc_flow1 |= + proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET; + break; + case MEM_ROT_VF_MEM: + fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK; + fs_proc_flow1 |= + proc_src_sel[IPU_CHAN_ID(src_ch)] << + FS_PRPVF_ROT_SRC_SEL_OFFSET; + break; + case MEM_DC_SYNC: + fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK; + fs_disp_flow1 |= + disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC1_SRC_SEL_OFFSET; + break; + case MEM_BG_SYNC: + fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK; + fs_disp_flow1 |= + disp_src_sel[IPU_CHAN_ID(src_ch)] << + FS_DP_SYNC0_SRC_SEL_OFFSET; + break; + case MEM_FG_SYNC: + fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK; + fs_disp_flow1 |= + disp_src_sel[IPU_CHAN_ID(src_ch)] << + FS_DP_SYNC1_SRC_SEL_OFFSET; + break; + case MEM_DC_ASYNC: + fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK; + fs_disp_flow1 |= + disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC2_SRC_SEL_OFFSET; + break; + case MEM_BG_ASYNC0: + fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK; + fs_disp_flow1 |= + disp_src_sel[IPU_CHAN_ID(src_ch)] << + FS_DP_ASYNC0_SRC_SEL_OFFSET; + break; + case MEM_FG_ASYNC0: + fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK; + fs_disp_flow1 |= + disp_src_sel[IPU_CHAN_ID(src_ch)] << + FS_DP_ASYNC1_SRC_SEL_OFFSET; + break; + default: + retval = -EINVAL; + goto err; + } + + __raw_writel(fs_proc_flow1, IPU_FS_PROC_FLOW1); + __raw_writel(fs_proc_flow2, IPU_FS_PROC_FLOW2); + __raw_writel(fs_proc_flow3, IPU_FS_PROC_FLOW3); + __raw_writel(fs_disp_flow1, IPU_FS_DISP_FLOW1); + +err: + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return retval; +} +EXPORT_SYMBOL(ipu_link_channels); + +/*! + * This function unlinks 2 channels and disables automatic frame + * synchronization. + * + * @param src_ch Input parameter for the logical channel ID of + * the source channel. + * + * @param dest_ch Input parameter for the logical channel ID of + * the destination channel. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_unlink_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch) +{ + int retval = 0; + unsigned long lock_flags; + uint32_t fs_proc_flow1; + uint32_t fs_proc_flow2; + uint32_t fs_proc_flow3; + uint32_t fs_disp_flow1; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + fs_proc_flow1 = __raw_readl(IPU_FS_PROC_FLOW1); + fs_proc_flow2 = __raw_readl(IPU_FS_PROC_FLOW2); + fs_proc_flow3 = __raw_readl(IPU_FS_PROC_FLOW3); + fs_disp_flow1 = __raw_readl(IPU_FS_DISP_FLOW1); + + switch (src_ch) { + case CSI_MEM0: + fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK; + break; + case CSI_MEM1: + fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK; + break; + case CSI_MEM2: + fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK; + break; + case CSI_MEM3: + fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK; + break; + case CSI_PRP_ENC_MEM: + fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK; + break; + case CSI_PRP_VF_MEM: + fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK; + break; + case MEM_PP_MEM: + fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK; + break; + case MEM_ROT_PP_MEM: + fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK; + break; + case MEM_PRP_ENC_MEM: + fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK; + break; + case MEM_ROT_ENC_MEM: + fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK; + break; + case MEM_PRP_VF_MEM: + fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK; + break; + case MEM_ROT_VF_MEM: + fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK; + break; + default: + retval = -EINVAL; + goto err; + } + + switch (dest_ch) { + case MEM_PP_MEM: + fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK; + break; + case MEM_ROT_PP_MEM: + fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK; + break; + case MEM_PRP_ENC_MEM: + fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK; + break; + case MEM_ROT_ENC_MEM: + fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK; + break; + case MEM_PRP_VF_MEM: + fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK; + break; + case MEM_ROT_VF_MEM: + fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK; + break; + case MEM_DC_SYNC: + fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK; + break; + case MEM_BG_SYNC: + fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK; + break; + case MEM_FG_SYNC: + fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK; + break; + case MEM_DC_ASYNC: + fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK; + break; + case MEM_BG_ASYNC0: + fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK; + break; + case MEM_FG_ASYNC0: + fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK; + break; + default: + retval = -EINVAL; + goto err; + } + + __raw_writel(fs_proc_flow1, IPU_FS_PROC_FLOW1); + __raw_writel(fs_proc_flow2, IPU_FS_PROC_FLOW2); + __raw_writel(fs_proc_flow3, IPU_FS_PROC_FLOW3); + __raw_writel(fs_disp_flow1, IPU_FS_DISP_FLOW1); + +err: + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return retval; +} +EXPORT_SYMBOL(ipu_unlink_channels); + +/*! + * This function check whether a logical channel was enabled. + * + * @param channel Input parameter for the logical channel ID. + * + * @return This function returns 1 while request channel is enabled or + * 0 for not enabled. + */ +int32_t ipu_is_channel_busy(ipu_channel_t channel) +{ + uint32_t reg; + uint32_t in_dma; + uint32_t out_dma; + + out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER); + + reg = __raw_readl(IDMAC_CHA_EN(in_dma)); + if (reg & idma_mask(in_dma)) + return 1; + reg = __raw_readl(IDMAC_CHA_EN(out_dma)); + if (reg & idma_mask(out_dma)) + return 1; + return 0; +} +EXPORT_SYMBOL(ipu_is_channel_busy); + +/*! + * This function enables a logical channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_enable_channel(ipu_channel_t channel) +{ + uint32_t reg; + unsigned long lock_flags; + uint32_t in_dma; + uint32_t out_dma; + + if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) { + dev_err(g_ipu_dev, "Warning: channel already enabled %d\n", + IPU_CHAN_ID(channel)); + } + + /* Get input and output dma channels */ + out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER); + + spin_lock_irqsave(&ipu_lock, lock_flags); + + if (idma_is_valid(in_dma)) { + reg = __raw_readl(IDMAC_CHA_EN(in_dma)); + __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma)); + } + if (idma_is_valid(out_dma)) { + reg = __raw_readl(IDMAC_CHA_EN(out_dma)); + __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma)); + } + + if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) || + (channel == MEM_FG_SYNC)) + _ipu_dp_dc_enable(channel); + + if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) || + _ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma)) + _ipu_ic_enable_task(channel); + + g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} +EXPORT_SYMBOL(ipu_enable_channel); + +/*! + * This function disables a logical channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param wait_for_stop Flag to set whether to wait for channel end + * of frame or return immediately. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_disable_channel(ipu_channel_t channel, bool wait_for_stop) +{ + uint32_t reg; + unsigned long lock_flags; + uint32_t in_dma; + uint32_t out_dma; + uint32_t timeout; + + if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) { + dev_err(g_ipu_dev, "Channel already disabled %d\n", + IPU_CHAN_ID(channel)); + return 0; + } + + /* Get input and output dma channels */ + out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER); + + if ((idma_is_valid(in_dma) && + !idma_is_set(IDMAC_CHA_EN, in_dma)) + && (idma_is_valid(out_dma) && + !idma_is_set(IDMAC_CHA_EN, out_dma))) + return -EINVAL; + + if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) || + (channel == MEM_DC_SYNC)) { + _ipu_dp_dc_disable(channel); + } else if (wait_for_stop) { + timeout = 40; + while (idma_is_set(IDMAC_CHA_BUSY, in_dma) || + idma_is_set(IDMAC_CHA_BUSY, out_dma) || + (_ipu_channel_status(channel) == TASK_STAT_ACTIVE)) { + timeout--; + msleep(10); + if (timeout == 0) { + ipu_dump_registers(); + break; + } + } + dev_dbg(g_ipu_dev, "timeout = %d * 10ms\n", 40 - timeout); + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + /* Disable IC task */ + if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) || + _ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma)) + _ipu_ic_disable_task(channel); + + /* Disable DMA channel(s) */ + if (idma_is_valid(in_dma)) { + reg = __raw_readl(IDMAC_CHA_EN(in_dma)); + __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma)); + __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma)); + } + if (idma_is_valid(out_dma)) { + reg = __raw_readl(IDMAC_CHA_EN(out_dma)); + __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma)); + __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma)); + } + + /* Set channel buffers NOT to be ready */ + __raw_writel(0xF0000000, IPU_GPR); /* write one to clear */ + if (idma_is_valid(in_dma)) { + if (idma_is_set(IPU_CHA_BUF0_RDY, in_dma)) { + __raw_writel(idma_mask(in_dma), + IPU_CHA_BUF0_RDY(in_dma)); + } + if (idma_is_set(IPU_CHA_BUF1_RDY, in_dma)) { + __raw_writel(idma_mask(in_dma), + IPU_CHA_BUF1_RDY(in_dma)); + } + } + if (idma_is_valid(out_dma)) { + if (idma_is_set(IPU_CHA_BUF0_RDY, out_dma)) { + __raw_writel(idma_mask(out_dma), + IPU_CHA_BUF0_RDY(out_dma)); + } + if (idma_is_set(IPU_CHA_BUF1_RDY, out_dma)) { + __raw_writel(idma_mask(out_dma), + IPU_CHA_BUF1_RDY(out_dma)); + } + } + __raw_writel(0x0, IPU_GPR); /* write one to set */ + + g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} +EXPORT_SYMBOL(ipu_disable_channel); + +static irqreturn_t ipu_irq_handler(int irq, void *desc) +{ + int i; + uint32_t line; + irqreturn_t result = IRQ_NONE; + uint32_t int_stat; + const int err_reg[] = { 5, 6, 9, 10, 0 }; + const int int_reg[] = { 1, 2, 3, 4, 11, 12, 13, 14, 15, 0 }; + + if (g_ipu_irq[1]) { + disable_irq(g_ipu_irq[0]); + disable_irq(g_ipu_irq[1]); + } + + for (i = 0;; i++) { + if (err_reg[i] == 0) + break; + int_stat = __raw_readl(IPU_INT_STAT(err_reg[i])); + int_stat &= __raw_readl(IPU_INT_CTRL(err_reg[i])); + if (int_stat) { + __raw_writel(int_stat, IPU_INT_STAT(err_reg[i])); + dev_err(g_ipu_dev, + "IPU Error - IPU_INT_STAT_%d = 0x%08X\n", + err_reg[i], int_stat); + + /* Disable interrupts so we only get error once */ + int_stat = + __raw_readl(IPU_INT_CTRL(err_reg[i])) & ~int_stat; + __raw_writel(int_stat, IPU_INT_CTRL(err_reg[i])); + } + } + + for (i = 0;; i++) { + if (int_reg[i] == 0) + break; + int_stat = __raw_readl(IPU_INT_STAT(int_reg[i])); + int_stat &= __raw_readl(IPU_INT_CTRL(int_reg[i])); + __raw_writel(int_stat, IPU_INT_STAT(int_reg[i])); + while ((line = ffs(int_stat)) != 0) { + line--; + int_stat &= ~(1UL << line); + line += (int_reg[i] - 1) * 32; + result |= + ipu_irq_list[line].handler(line, + ipu_irq_list[line]. + dev_id); + } + } + + if (g_ipu_irq[1]) { + enable_irq(g_ipu_irq[0]); + enable_irq(g_ipu_irq[1]); + } + return result; +} + +/*! + * This function enables the interrupt for the specified interrupt line. + * The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to enable interrupt for. + * + */ +void ipu_enable_irq(uint32_t irq) +{ + uint32_t reg; + unsigned long lock_flags; + + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + + spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(IPUIRQ_2_CTRLREG(irq)); + reg |= IPUIRQ_2_MASK(irq); + __raw_writel(reg, IPUIRQ_2_CTRLREG(irq)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); +} +EXPORT_SYMBOL(ipu_enable_irq); + +/*! + * This function disables the interrupt for the specified interrupt line. + * The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to disable interrupt for. + * + */ +void ipu_disable_irq(uint32_t irq) +{ + uint32_t reg; + unsigned long lock_flags; + + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(IPUIRQ_2_CTRLREG(irq)); + reg &= ~IPUIRQ_2_MASK(irq); + __raw_writel(reg, IPUIRQ_2_CTRLREG(irq)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); +} +EXPORT_SYMBOL(ipu_disable_irq); + +/*! + * This function clears the interrupt for the specified interrupt line. + * The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to clear interrupt for. + * + */ +void ipu_clear_irq(uint32_t irq) +{ + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + + __raw_writel(IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq)); + + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); +} +EXPORT_SYMBOL(ipu_clear_irq); + +/*! + * This function returns the current interrupt status for the specified + * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to get status for. + * + * @return Returns true if the interrupt is pending/asserted or false if + * the interrupt is not pending. + */ +bool ipu_get_irq_status(uint32_t irq) +{ + uint32_t reg; + + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + + reg = __raw_readl(IPUIRQ_2_STATREG(irq)); + + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); + + if (reg & IPUIRQ_2_MASK(irq)) + return true; + else + return false; +} +EXPORT_SYMBOL(ipu_get_irq_status); + +/*! + * This function registers an interrupt handler function for the specified + * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to get status for. + * + * @param handler Input parameter for address of the handler + * function. + * + * @param irq_flags Flags for interrupt mode. Currently not used. + * + * @param devname Input parameter for string name of driver + * registering the handler. + * + * @param dev_id Input parameter for pointer of data to be + * passed to the handler. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int ipu_request_irq(uint32_t irq, + irqreturn_t(*handler) (int, void *), + uint32_t irq_flags, const char *devname, void *dev_id) +{ + unsigned long lock_flags; + + BUG_ON(irq >= IPU_IRQ_COUNT); + + spin_lock_irqsave(&ipu_lock, lock_flags); + + if (ipu_irq_list[irq].handler != NULL) { + dev_err(g_ipu_dev, + "handler already installed on irq %d\n", irq); + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return -EINVAL; + } + + ipu_irq_list[irq].handler = handler; + ipu_irq_list[irq].flags = irq_flags; + ipu_irq_list[irq].dev_id = dev_id; + ipu_irq_list[irq].name = devname; + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + ipu_enable_irq(irq); /* enable the interrupt */ + + return 0; +} +EXPORT_SYMBOL(ipu_request_irq); + +/*! + * This function unregisters an interrupt handler for the specified interrupt + * line. The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to get status for. + * + * @param dev_id Input parameter for pointer of data to be passed + * to the handler. This must match value passed to + * ipu_request_irq(). + * + */ +void ipu_free_irq(uint32_t irq, void *dev_id) +{ + ipu_disable_irq(irq); /* disable the interrupt */ + + if (ipu_irq_list[irq].dev_id == dev_id) + ipu_irq_list[irq].handler = NULL; +} +EXPORT_SYMBOL(ipu_free_irq); + +uint32_t _ipu_channel_status(ipu_channel_t channel) +{ + uint32_t stat = 0; + uint32_t task_stat_reg = __raw_readl(IPU_PROC_TASK_STAT); + + switch (channel) { + case MEM_PRP_VF_MEM: + stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET; + break; + case MEM_ROT_VF_MEM: + stat = + (task_stat_reg & TSTAT_VF_ROT_MASK) >> TSTAT_VF_ROT_OFFSET; + break; + case MEM_PRP_ENC_MEM: + stat = (task_stat_reg & TSTAT_ENC_MASK) >> TSTAT_ENC_OFFSET; + break; + case MEM_ROT_ENC_MEM: + stat = + (task_stat_reg & TSTAT_ENC_ROT_MASK) >> + TSTAT_ENC_ROT_OFFSET; + break; + case MEM_PP_MEM: + stat = (task_stat_reg & TSTAT_PP_MASK) >> TSTAT_PP_OFFSET; + break; + case MEM_ROT_PP_MEM: + stat = + (task_stat_reg & TSTAT_PP_ROT_MASK) >> TSTAT_PP_ROT_OFFSET; + break; + + default: + stat = TASK_STAT_IDLE; + break; + } + return stat; +} + +uint32_t bytes_per_pixel(uint32_t fmt) +{ + switch (fmt) { + case IPU_PIX_FMT_GENERIC: /*generic data */ + case IPU_PIX_FMT_RGB332: + case IPU_PIX_FMT_YUV420P: + case IPU_PIX_FMT_YUV422P: + return 1; + break; + case IPU_PIX_FMT_RGB565: + case IPU_PIX_FMT_YUYV: + case IPU_PIX_FMT_UYVY: + return 2; + break; + case IPU_PIX_FMT_BGR24: + case IPU_PIX_FMT_RGB24: + return 3; + break; + case IPU_PIX_FMT_GENERIC_32: /*generic data */ + case IPU_PIX_FMT_BGR32: + case IPU_PIX_FMT_BGRA32: + case IPU_PIX_FMT_RGB32: + case IPU_PIX_FMT_RGBA32: + case IPU_PIX_FMT_ABGR32: + return 4; + break; + default: + return 1; + break; + } + return 0; +} +EXPORT_SYMBOL(bytes_per_pixel); + +ipu_color_space_t format_to_colorspace(uint32_t fmt) +{ + switch (fmt) { + case IPU_PIX_FMT_RGB666: + case IPU_PIX_FMT_RGB565: + case IPU_PIX_FMT_BGR24: + case IPU_PIX_FMT_RGB24: + case IPU_PIX_FMT_BGR32: + case IPU_PIX_FMT_BGRA32: + case IPU_PIX_FMT_RGB32: + case IPU_PIX_FMT_RGBA32: + case IPU_PIX_FMT_ABGR32: + case IPU_PIX_FMT_LVDS666: + case IPU_PIX_FMT_LVDS888: + return RGB; + break; + + default: + return YCbCr; + break; + } + return RGB; +} + +void ipu_set_csc_coefficients(ipu_channel_t channel, int32_t param[][3]) +{ + _ipu_dp_set_csc_coefficients(channel, param); +} +EXPORT_SYMBOL(ipu_set_csc_coefficients); + +static int ipu_suspend(struct platform_device *pdev, pm_message_t state) +{ + if (g_ipu_clk_enabled) { + /* save and disable enabled channels*/ + idma_enable_reg[0] = __raw_readl(IDMAC_CHA_EN(0)); + idma_enable_reg[1] = __raw_readl(IDMAC_CHA_EN(32)); + while ((__raw_readl(IDMAC_CHA_BUSY(0)) & idma_enable_reg[0]) + || (__raw_readl(IDMAC_CHA_BUSY(32)) & + idma_enable_reg[1])) { + /* disable channel not busy already */ + uint32_t chan_should_disable, timeout = 1000, time = 0; + + chan_should_disable = + __raw_readl(IDMAC_CHA_BUSY(0)) + ^ idma_enable_reg[0]; + __raw_writel((~chan_should_disable) & + idma_enable_reg[0], IDMAC_CHA_EN(0)); + chan_should_disable = + __raw_readl(IDMAC_CHA_BUSY(1)) + ^ idma_enable_reg[1]; + __raw_writel((~chan_should_disable) & + idma_enable_reg[1], IDMAC_CHA_EN(32)); + msleep(2); + time += 2; + if (time >= timeout) + return -1; + } + __raw_writel(0, IDMAC_CHA_EN(0)); + __raw_writel(0, IDMAC_CHA_EN(32)); + + /* save double buffer select regs */ + ipu_cha_db_mode_reg[0] = __raw_readl(IPU_CHA_DB_MODE_SEL(0)); + ipu_cha_db_mode_reg[1] = __raw_readl(IPU_CHA_DB_MODE_SEL(32)); + ipu_cha_db_mode_reg[2] = + __raw_readl(IPU_ALT_CHA_DB_MODE_SEL(0)); + ipu_cha_db_mode_reg[3] = + __raw_readl(IPU_ALT_CHA_DB_MODE_SEL(32)); + + /* save current buffer regs */ + ipu_cha_cur_buf_reg[0] = __raw_readl(IPU_CHA_CUR_BUF(0)); + ipu_cha_cur_buf_reg[1] = __raw_readl(IPU_CHA_CUR_BUF(32)); + ipu_cha_cur_buf_reg[2] = __raw_readl(IPU_ALT_CUR_BUF0); + ipu_cha_cur_buf_reg[3] = __raw_readl(IPU_ALT_CUR_BUF1); + + /* save sub-modules status and disable all */ + ic_conf_reg = __raw_readl(IC_CONF); + __raw_writel(0, IC_CONF); + ipu_conf_reg = __raw_readl(IPU_CONF); + __raw_writel(0, IPU_CONF); + + /* save buf ready regs */ + buf_ready_reg[0] = __raw_readl(IPU_CHA_BUF0_RDY(0)); + buf_ready_reg[1] = __raw_readl(IPU_CHA_BUF0_RDY(32)); + buf_ready_reg[2] = __raw_readl(IPU_CHA_BUF1_RDY(0)); + buf_ready_reg[3] = __raw_readl(IPU_CHA_BUF1_RDY(32)); + buf_ready_reg[4] = __raw_readl(IPU_ALT_CHA_BUF0_RDY(0)); + buf_ready_reg[5] = __raw_readl(IPU_ALT_CHA_BUF0_RDY(32)); + buf_ready_reg[6] = __raw_readl(IPU_ALT_CHA_BUF1_RDY(0)); + buf_ready_reg[7] = __raw_readl(IPU_ALT_CHA_BUF1_RDY(32)); + } + + mxc_pg_enable(pdev); + + return 0; +} + +static int ipu_resume(struct platform_device *pdev) +{ + mxc_pg_disable(pdev); + + if (g_ipu_clk_enabled) { + + /* restore buf ready regs */ + __raw_writel(buf_ready_reg[0], IPU_CHA_BUF0_RDY(0)); + __raw_writel(buf_ready_reg[1], IPU_CHA_BUF0_RDY(32)); + __raw_writel(buf_ready_reg[2], IPU_CHA_BUF1_RDY(0)); + __raw_writel(buf_ready_reg[3], IPU_CHA_BUF1_RDY(32)); + __raw_writel(buf_ready_reg[4], IPU_ALT_CHA_BUF0_RDY(0)); + __raw_writel(buf_ready_reg[5], IPU_ALT_CHA_BUF0_RDY(32)); + __raw_writel(buf_ready_reg[6], IPU_ALT_CHA_BUF1_RDY(0)); + __raw_writel(buf_ready_reg[7], IPU_ALT_CHA_BUF1_RDY(32)); + + /* re-enable sub-modules*/ + __raw_writel(ipu_conf_reg, IPU_CONF); + __raw_writel(ic_conf_reg, IC_CONF); + + /* restore double buffer select regs */ + __raw_writel(ipu_cha_db_mode_reg[0], IPU_CHA_DB_MODE_SEL(0)); + __raw_writel(ipu_cha_db_mode_reg[1], IPU_CHA_DB_MODE_SEL(32)); + __raw_writel(ipu_cha_db_mode_reg[2], + IPU_ALT_CHA_DB_MODE_SEL(0)); + __raw_writel(ipu_cha_db_mode_reg[3], + IPU_ALT_CHA_DB_MODE_SEL(32)); + + /* restore current buffer select regs */ + __raw_writel(~(ipu_cha_cur_buf_reg[0]), IPU_CHA_CUR_BUF(0)); + __raw_writel(~(ipu_cha_cur_buf_reg[1]), IPU_CHA_CUR_BUF(32)); + __raw_writel(~(ipu_cha_cur_buf_reg[2]), IPU_ALT_CUR_BUF0); + __raw_writel(~(ipu_cha_cur_buf_reg[3]), IPU_ALT_CUR_BUF1); + + /* restart idma channel*/ + __raw_writel(idma_enable_reg[0], IDMAC_CHA_EN(0)); + __raw_writel(idma_enable_reg[1], IDMAC_CHA_EN(32)); + } else { + clk_enable(g_ipu_clk); + _ipu_dmfc_init(); + _ipu_init_dc_mappings(); + + /* Set sync refresh channels as high priority */ + __raw_writel(0x18800000L, IDMAC_CHA_PRI(0)); + clk_disable(g_ipu_clk); + } + + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxcipu_driver = { + .driver = { + .name = "mxc_ipu", + }, + .probe = ipu_probe, + .remove = ipu_remove, + .suspend_late = ipu_suspend, + .resume_early = ipu_resume, +}; + +int32_t __init ipu_gen_init(void) +{ + int32_t ret; + + ret = platform_driver_register(&mxcipu_driver); + return 0; +} + +subsys_initcall(ipu_gen_init); + +static void __exit ipu_gen_uninit(void) +{ + platform_driver_unregister(&mxcipu_driver); +} + +module_exit(ipu_gen_uninit); diff -urN linux-2.6.26/drivers/mxc/ipu3/ipu_device.c linux-2.6.26-lab126/drivers/mxc/ipu3/ipu_device.c --- linux-2.6.26/drivers/mxc/ipu3/ipu_device.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu3/ipu_device.c 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,496 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_device.c + * + * @brief This file contains the IPUv3 driver device interface and fops functions. + * + * @ingroup IPU + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ipu_prv.h" +#include "ipu_regs.h" +#include "ipu_param_mem.h" + +/* Strucutures and variables for exporting MXC IPU as device*/ + +#define MAX_Q_SIZE 10 + +static int mxc_ipu_major; +static struct class *mxc_ipu_class; + +DEFINE_SPINLOCK(queue_lock); +static DECLARE_MUTEX(user_mutex); + +static wait_queue_head_t waitq; +static int pending_events; +int read_ptr; +int write_ptr; + +ipu_event_info events[MAX_Q_SIZE]; + +int register_ipu_device(void); + +/* Static functions */ + +int get_events(ipu_event_info *p) +{ + unsigned long flags; + int ret = 0, i, cnt, found = 0; + + spin_lock_irqsave(&queue_lock, flags); + if (pending_events != 0) { + if (write_ptr > read_ptr) + cnt = write_ptr - read_ptr; + else + cnt = MAX_Q_SIZE - read_ptr + write_ptr; + for (i = 0; i < cnt; i++) { + if (p->irq == events[read_ptr].irq) { + *p = events[read_ptr]; + events[read_ptr].irq = 0; + read_ptr++; + if (read_ptr >= MAX_Q_SIZE) + read_ptr = 0; + found = 1; + break; + } + + if (events[read_ptr].irq) { + events[write_ptr] = events[read_ptr]; + events[read_ptr].irq = 0; + write_ptr++; + if (write_ptr >= MAX_Q_SIZE) + write_ptr = 0; + } else + pending_events--; + + read_ptr++; + if (read_ptr >= MAX_Q_SIZE) + read_ptr = 0; + } + if (found) + pending_events--; + else + ret = -1; + } else { + ret = -1; + } + + spin_unlock_irqrestore(&queue_lock, flags); + + return ret; +} + +static irqreturn_t mxc_ipu_generic_handler(int irq, void *dev_id) +{ + ipu_event_info e; + + e.irq = irq; + e.dev = dev_id; + events[write_ptr] = e; + write_ptr++; + if (write_ptr >= MAX_Q_SIZE) + write_ptr = 0; + pending_events++; + + /* Wakeup any blocking user context */ + wake_up_interruptible(&waitq); + return IRQ_HANDLED; +} + +static int mxc_ipu_open(struct inode *inode, struct file *file) +{ + int ret = 0; + return ret; +} +static int mxc_ipu_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + int ret = 0; + + switch (cmd) { + case IPU_INIT_CHANNEL: + { + ipu_channel_parm parm; + + if (copy_from_user + (&parm, (ipu_channel_parm *) arg, + sizeof(ipu_channel_parm))) + return -EFAULT; + + if (!parm.flag) { + ret = + ipu_init_channel(parm.channel, + &parm.params); + } else { + ret = ipu_init_channel(parm.channel, NULL); + } + } + break; + case IPU_UNINIT_CHANNEL: + { + ipu_channel_t ch; + int __user *argp = (void __user *)arg; + if (get_user(ch, argp)) + return -EFAULT; + ipu_uninit_channel(ch); + } + break; + case IPU_INIT_CHANNEL_BUFFER: + { + ipu_channel_buf_parm parm; + if (copy_from_user + (&parm, (ipu_channel_buf_parm *) arg, + sizeof(ipu_channel_buf_parm))) + return -EFAULT; + + ret = + ipu_init_channel_buffer( + parm.channel, parm.type, + parm.pixel_fmt, + parm.width, parm.height, + parm.stride, + parm.rot_mode, + parm.phyaddr_0, + parm.phyaddr_1, + parm.u_offset, + parm.v_offset); + + } + break; + case IPU_UPDATE_CHANNEL_BUFFER: + { + ipu_channel_buf_parm parm; + if (copy_from_user + (&parm, (ipu_channel_buf_parm *) arg, + sizeof(ipu_channel_buf_parm))) + return -EFAULT; + + if ((parm.phyaddr_0 != (dma_addr_t) NULL) + && (parm.phyaddr_1 == (dma_addr_t) NULL)) { + ret = + ipu_update_channel_buffer( + parm.channel, + parm.type, + parm.bufNum, + parm.phyaddr_0); + } else if ((parm.phyaddr_0 == (dma_addr_t) NULL) + && (parm.phyaddr_1 != (dma_addr_t) NULL)) { + ret = + ipu_update_channel_buffer( + parm.channel, + parm.type, + parm.bufNum, + parm.phyaddr_1); + } else { + ret = -1; + } + + } + break; + case IPU_SELECT_CHANNEL_BUFFER: + { + ipu_channel_buf_parm parm; + if (copy_from_user + (&parm, (ipu_channel_buf_parm *) arg, + sizeof(ipu_channel_buf_parm))) + return -EFAULT; + + ret = + ipu_select_buffer(parm.channel, + parm.type, parm.bufNum); + + } + break; + case IPU_LINK_CHANNELS: + { + ipu_channel_link link; + if (copy_from_user + (&link, (ipu_channel_link *) arg, + sizeof(ipu_channel_link))) + return -EFAULT; + + ret = ipu_link_channels(link.src_ch, + link.dest_ch); + + } + break; + case IPU_UNLINK_CHANNELS: + { + ipu_channel_link link; + if (copy_from_user + (&link, (ipu_channel_link *) arg, + sizeof(ipu_channel_link))) + return -EFAULT; + + ret = ipu_unlink_channels(link.src_ch, + link.dest_ch); + + } + break; + case IPU_ENABLE_CHANNEL: + { + ipu_channel_t ch; + int __user *argp = (void __user *)arg; + if (get_user(ch, argp)) + return -EFAULT; + ipu_enable_channel(ch); + } + break; + case IPU_DISABLE_CHANNEL: + { + ipu_channel_info info; + if (copy_from_user + (&info, (ipu_channel_info *) arg, + sizeof(ipu_channel_info))) + return -EFAULT; + + ret = ipu_disable_channel(info.channel, + info.stop); + } + break; + case IPU_ENABLE_IRQ: + { + uint32_t irq; + int __user *argp = (void __user *)arg; + if (get_user(irq, argp)) + return -EFAULT; + ipu_enable_irq(irq); + } + break; + case IPU_DISABLE_IRQ: + { + uint32_t irq; + int __user *argp = (void __user *)arg; + if (get_user(irq, argp)) + return -EFAULT; + ipu_disable_irq(irq); + } + break; + case IPU_CLEAR_IRQ: + { + uint32_t irq; + int __user *argp = (void __user *)arg; + if (get_user(irq, argp)) + return -EFAULT; + ipu_clear_irq(irq); + } + break; + case IPU_FREE_IRQ: + { + ipu_irq_info info; + int i; + + if (copy_from_user + (&info, (ipu_irq_info *) arg, + sizeof(ipu_irq_info))) + return -EFAULT; + + ipu_free_irq(info.irq, info.dev_id); + for (i = 0; i < MAX_Q_SIZE; i++) { + if (events[i].irq == info.irq) + events[i].irq = 0; + } + } + break; + case IPU_REQUEST_IRQ_STATUS: + { + uint32_t irq; + int __user *argp = (void __user *)arg; + if (get_user(irq, argp)) + return -EFAULT; + ret = ipu_get_irq_status(irq); + } + break; + case IPU_REGISTER_GENERIC_ISR: + { + ipu_event_info info; + if (copy_from_user + (&info, (ipu_event_info *) arg, + sizeof(ipu_event_info))) + return -EFAULT; + + ret = + ipu_request_irq(info.irq, + mxc_ipu_generic_handler, + 0, "video_sink", info.dev); + } + break; + case IPU_GET_EVENT: + /* User will have to allocate event_type + structure and pass the pointer in arg */ + { + ipu_event_info info; + int r = -1; + + if (copy_from_user + (&info, (ipu_event_info *) arg, + sizeof(ipu_event_info))) + return -EFAULT; + + r = get_events(&info); + if (r == -1) { + wait_event_interruptible_timeout(waitq, + (pending_events != 0), 2 * HZ); + r = get_events(&info); + } + ret = -1; + if (r == 0) { + if (!copy_to_user((ipu_event_info *) arg, + &info, sizeof(ipu_event_info))) + ret = 0; + } + } + break; + case IPU_ALOC_MEM: + { + ipu_mem_info info; + if (copy_from_user + (&info, (ipu_mem_info *) arg, + sizeof(ipu_mem_info))) + return -EFAULT; + + info.vaddr = dma_alloc_coherent(0, + PAGE_ALIGN(info.size), + &info.paddr, + GFP_DMA | GFP_KERNEL); + if (info.vaddr == 0) { + printk(KERN_ERR "dma alloc failed!\n"); + return -ENOBUFS; + } + if (copy_to_user((ipu_mem_info *) arg, &info, + sizeof(ipu_mem_info)) > 0) + return -EFAULT; + } + break; + case IPU_FREE_MEM: + { + ipu_mem_info info; + if (copy_from_user + (&info, (ipu_mem_info *) arg, + sizeof(ipu_mem_info))) + return -EFAULT; + + if (info.vaddr) + dma_free_coherent(0, PAGE_ALIGN(info.size), + info.vaddr, info.paddr); + else + return -EFAULT; + } + break; + case IPU_IS_CHAN_BUSY: + { + ipu_channel_t chan; + if (copy_from_user + (&chan, (ipu_channel_t *)arg, + sizeof(ipu_channel_t))) + return -EFAULT; + + if (ipu_is_channel_busy(chan)) + ret = 1; + else + ret = 0; + } + break; + default: + break; + } + return ret; +} + +static int mxc_ipu_mmap(struct file *file, struct vm_area_struct *vma) +{ + vma->vm_page_prot = pgprot_writethru(vma->vm_page_prot); + + if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) { + printk(KERN_ERR + "mmap failed!\n"); + return -ENOBUFS; + } + return 0; +} + +static int mxc_ipu_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static struct file_operations mxc_ipu_fops = { + .owner = THIS_MODULE, + .open = mxc_ipu_open, + .mmap = mxc_ipu_mmap, + .release = mxc_ipu_release, + .ioctl = mxc_ipu_ioctl +}; + +int register_ipu_device() +{ + int ret = 0; + struct device *temp; + mxc_ipu_major = register_chrdev(0, "mxc_ipu", &mxc_ipu_fops); + if (mxc_ipu_major < 0) { + printk(KERN_ERR + "Unable to register Mxc Ipu as a char device\n"); + return mxc_ipu_major; + } + + mxc_ipu_class = class_create(THIS_MODULE, "mxc_ipu"); + if (IS_ERR(mxc_ipu_class)) { + printk(KERN_ERR "Unable to create class for Mxc Ipu\n"); + ret = PTR_ERR(mxc_ipu_class); + goto err1; + } + + temp = device_create(mxc_ipu_class, NULL, MKDEV(mxc_ipu_major, 0), + "mxc_ipu"); + + if (IS_ERR(temp)) { + printk(KERN_ERR "Unable to create class device for Mxc Ipu\n"); + ret = PTR_ERR(temp); + goto err2; + } + spin_lock_init(&queue_lock); + init_waitqueue_head(&waitq); + + pending_events = 0; + read_ptr = 0; + write_ptr = 0; + + return ret; + +err2: + class_destroy(mxc_ipu_class); +err1: + unregister_chrdev(mxc_ipu_major, "mxc_ipu"); + return ret; + +} diff -urN linux-2.6.26/drivers/mxc/ipu3/ipu_disp.c linux-2.6.26-lab126/drivers/mxc/ipu3/ipu_disp.c --- linux-2.6.26/drivers/mxc/ipu3/ipu_disp.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu3/ipu_disp.c 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,1354 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_disp.c + * + * @brief IPU display submodule API functions + * + * @ingroup IPU + */ +#include +#include +#include +#include +#include +#include +#include +#include "ipu_prv.h" +#include "ipu_regs.h" +#include "ipu_param_mem.h" + +enum csc_type_t { + RGB2YUV = 0, + YUV2RGB, + RGB2RGB, + YUV2YUV, + CSC_NONE, + CSC_NUM +}; + +struct dp_csc_param_t { + int mode; + void *coeff; +}; + +#define SYNC_WAVE 0 +#define ASYNC_SER_WAVE 6 + +/* DC display ID assignments */ +#define DC_DISP_ID_SYNC(di) (di) +#define DC_DISP_ID_SERIAL 2 +#define DC_DISP_ID_ASYNC 3 + + +/* all value below is determined by fix reg setting in _ipu_dmfc_init*/ +#define DMFC_FIFO_SIZE_28 (128*4) +#define DMFC_FIFO_SIZE_29 (64*4) +#define DMFC_FIFO_SIZE_24 (64*4) +#define DMFC_FIFO_SIZE_27 (128*4) +#define DMFC_FIFO_SIZE_23 (128*4) + +void _ipu_dmfc_init(void) +{ + /* disable DMFC-IC channel*/ + __raw_writel(0x2, DMFC_IC_CTRL); + /* 1 - segment 0 and 1; 2, 1C and 2C unused */ + __raw_writel(0x00000090, DMFC_WR_CHAN); + __raw_writel(0x20202000, DMFC_WR_CHAN_DEF); + /* 5B - segment 2 and 3; 5F - segment 4 and 5; */ + /* 6B - segment 6; 6F - segment 7 */ + __raw_writel(0x1F1E9492, DMFC_DP_CHAN); +} + +void _ipu_dmfc_set_wait4eot(int dma_chan, int width) +{ + u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1); + + if (dma_chan == 23) { /*5B*/ + if (DMFC_FIFO_SIZE_23/width > 3) + dmfc_gen1 |= 1UL << 20; + else + dmfc_gen1 &= ~(1UL << 20); + } else if (dma_chan == 24) { /*6B*/ + if (DMFC_FIFO_SIZE_24/width > 1) + dmfc_gen1 |= 1UL << 22; + else + dmfc_gen1 &= ~(1UL << 22); + } else if (dma_chan == 27) { /*5F*/ + if (DMFC_FIFO_SIZE_27/width > 2) + dmfc_gen1 |= 1UL << 21; + else + dmfc_gen1 &= ~(1UL << 21); + } else if (dma_chan == 28) { /*1*/ + if (DMFC_FIFO_SIZE_28/width > 2) + dmfc_gen1 |= 1UL << 16; + else + dmfc_gen1 &= ~(1UL << 16); + } else if (dma_chan == 29) { /*6F*/ + if (DMFC_FIFO_SIZE_29/width > 1) + dmfc_gen1 |= 1UL << 23; + else + dmfc_gen1 &= ~(1UL << 23); + } + + __raw_writel(dmfc_gen1, DMFC_GENERAL1); +} + +static void _ipu_di_data_wave_config(int di, + int wave_gen, + int access_size, int component_size) +{ + u32 reg; + reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) | + (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET); + __raw_writel(reg, DI_DW_GEN(di, wave_gen)); +} + +static void _ipu_di_data_pin_config(int di, int wave_gen, int di_pin, int set, + int up, int down) +{ + u32 reg; + + reg = __raw_readl(DI_DW_GEN(di, wave_gen)); + reg &= ~(0x3 << (di_pin * 2)); + reg |= set << (di_pin * 2); + __raw_writel(reg, DI_DW_GEN(di, wave_gen)); + + __raw_writel((down << 16) | up, DI_DW_SET(di, wave_gen, set)); +} + +static void _ipu_di_sync_config(int di, int wave_gen, + int run_count, int run_src, + int offset_count, int offset_src, + int repeat_count, int cnt_clr_src, + int cnt_polarity_gen_en, + int cnt_polarity_clr_src, + int cnt_polarity_trigger_src, + int cnt_up, int cnt_down) +{ + u32 reg; + reg = (run_count << 19) | (++run_src << 16) | + (offset_count << 3) | ++offset_src; + __raw_writel(reg, DI_SW_GEN0(di, wave_gen)); + reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) | + (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9); + reg |= (cnt_down << 16) | cnt_up; + if (repeat_count == 0) { + /* Enable auto reload */ + reg |= 0x10000000; + } + __raw_writel(reg, DI_SW_GEN1(di, wave_gen)); + reg = __raw_readl(DI_STP_REP(di, wave_gen)); + reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1))); + reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1)); + __raw_writel(reg, DI_STP_REP(di, wave_gen)); +} + +static void _ipu_dc_map_config(int map, int byte_num, int offset, int mask) +{ + int ptr = map * 3 + byte_num; + u32 reg; + + reg = __raw_readl(DC_MAP_CONF_VAL(ptr)); + reg &= ~(0xFFFF << (16 * (ptr & 0x1))); + reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1)); + __raw_writel(reg, DC_MAP_CONF_VAL(ptr)); + + reg = __raw_readl(DC_MAP_CONF_PTR(map)); + reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num))); + reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num)); + __raw_writel(reg, DC_MAP_CONF_PTR(map)); +} + +static void _ipu_dc_map_clear(int map) +{ + u32 reg = __raw_readl(DC_MAP_CONF_PTR(map)); + __raw_writel(reg & ~(0xFFFF << (16 * (map & 0x1))), + DC_MAP_CONF_PTR(map)); +} + +static void _ipu_dc_write_tmpl(int word, u32 opcode, u32 operand, int map, + int wave, int glue, int sync) +{ + u32 reg; + int stop = 1; + + reg = sync; + reg |= (glue << 4); + reg |= (++wave << 11); + reg |= (++map << 15); + reg |= (operand << 20) & 0xFFF00000; + __raw_writel(reg, ipu_dc_tmpl_reg + word * 2); + + reg = (operand >> 12); + reg |= opcode << 4; + reg |= (stop << 9); + __raw_writel(reg, ipu_dc_tmpl_reg + word * 2 + 1); +} + +static void _ipu_dc_link_event(int chan, int event, int addr, int priority) +{ + u32 reg; + + reg = __raw_readl(DC_RL_CH(chan, event)); + reg &= ~(0xFFFF << (16 * (event & 0x1))); + reg |= ((addr << 8) | priority) << (16 * (event & 0x1)); + __raw_writel(reg, DC_RL_CH(chan, event)); +} + +/* Y = R * .299 + G * .587 + B * .114; + U = R * -.169 + G * -.332 + B * .500 + 128.; + V = R * .500 + G * -.419 + B * -.0813 + 128.;*/ +static const int rgb2ycbcr_coeff[5][3] = { + {153, 301, 58}, + {-87, -170, 0x0100}, + {0x100, -215, -42}, + {0x0000, 0x0200, 0x0200}, /* B0, B1, B2 */ + {0x2, 0x2, 0x2}, /* S0, S1, S2 */ +}; + +/* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128)); + G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128)); + B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */ +static const int ycbcr2rgb_coeff[5][3] = { + {0x095, 0x000, 0x0CC}, + {0x095, 0x3CE, 0x398}, + {0x095, 0x0FF, 0x000}, + {0x3E42, 0x010A, 0x3DD6}, /*B0,B1,B2 */ + {0x1, 0x1, 0x1}, /*S0,S1,S2 */ +}; + +#define mask_a(a) ((u32)(a) & 0x3FF) +#define mask_b(b) ((u32)(b) & 0x3FFF) + +static int _rgb_to_yuv(int n, int red, int green, int blue) +{ + int c; + c = red * rgb2ycbcr_coeff[n][0]; + c += green * rgb2ycbcr_coeff[n][1]; + c += blue * rgb2ycbcr_coeff[n][2]; + c /= 16; + c += rgb2ycbcr_coeff[3][n] * 4; + c += 8; + c /= 16; + if (c < 0) + c = 0; + if (c > 255) + c = 255; + return c; +} + +/* + * Row is for BG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE + * Column is for FG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE + */ +static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = { +{{DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff}, {0, 0}, {0, 0}, {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff} }, +{{0, 0}, {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff}, {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}, {0, 0}, {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff} }, +{{0, 0}, {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, {0, 0}, {0, 0}, {0, 0} }, +{{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, +{{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, {0, 0}, {0, 0}, {0, 0} } +}; + +static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE; + +void __ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param, + bool srm_mode_update) +{ + u32 reg; + const int (*coeff)[5][3]; + + if (dp_csc_param.mode >= 0) { + reg = __raw_readl(DP_COM_CONF(dp)); + reg &= ~DP_COM_CONF_CSC_DEF_MASK; + reg |= dp_csc_param.mode; + __raw_writel(reg, DP_COM_CONF(dp)); + } + + coeff = dp_csc_param.coeff; + + if (coeff) { + __raw_writel(mask_a((*coeff)[0][0]) | + (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0(dp)); + __raw_writel(mask_a((*coeff)[0][2]) | + (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1(dp)); + __raw_writel(mask_a((*coeff)[1][1]) | + (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2(dp)); + __raw_writel(mask_a((*coeff)[2][0]) | + (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3(dp)); + __raw_writel(mask_a((*coeff)[2][2]) | + (mask_b((*coeff)[3][0]) << 16) | + ((*coeff)[4][0] << 30), DP_CSC_0(dp)); + __raw_writel(mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) | + (mask_b((*coeff)[3][2]) << 16) | + ((*coeff)[4][2] << 30), DP_CSC_1(dp)); + } + + if (srm_mode_update) { + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + } +} + +int _ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt, + uint32_t out_pixel_fmt) +{ + int in_fmt, out_fmt; + int dp; + int partial = false; + + if (channel == MEM_FG_SYNC) { + dp = DP_SYNC; + partial = true; + } else if (channel == MEM_BG_SYNC) { + dp = DP_SYNC; + partial = false; + } else if (channel == MEM_BG_ASYNC0) { + dp = DP_ASYNC0; + partial = false; + } else { + return -EINVAL; + } + + in_fmt = format_to_colorspace(in_pixel_fmt); + out_fmt = format_to_colorspace(out_pixel_fmt); + + if (partial) { + if (in_fmt == RGB) { + if (out_fmt == RGB) + fg_csc_type = RGB2RGB; + else + fg_csc_type = RGB2YUV; + } else { + if (out_fmt == RGB) + fg_csc_type = YUV2RGB; + else + fg_csc_type = YUV2YUV; + } + } else { + if (in_fmt == RGB) { + if (out_fmt == RGB) + bg_csc_type = RGB2RGB; + else + bg_csc_type = RGB2YUV; + } else { + if (out_fmt == RGB) + bg_csc_type = YUV2RGB; + else + bg_csc_type = YUV2YUV; + } + } + + __ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], true); + + return 0; +} + +void _ipu_dp_uninit(ipu_channel_t channel) +{ + int dp; + int partial = false; + + if (channel == MEM_FG_SYNC) { + dp = DP_SYNC; + partial = true; + } else if (channel == MEM_BG_SYNC) { + dp = DP_SYNC; + partial = false; + } else if (channel == MEM_BG_ASYNC0) { + dp = DP_ASYNC0; + partial = false; + } else { + return; + } + + if (partial) + fg_csc_type = CSC_NONE; + else + bg_csc_type = CSC_NONE; + + __ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], false); +} + +void _ipu_dc_init(int dc_chan, int di, bool interlaced) +{ + u32 reg; + + if ((dc_chan == 1) || (dc_chan == 5)) { + if (interlaced) { + _ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 3); + _ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 2); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 1); + } else { + _ipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3); + _ipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 4, 1); + } + _ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0); + + /* Make sure other DC sync channel is not assigned same DI */ + reg = __raw_readl(DC_WR_CH_CONF(6 - dc_chan)); + if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) { + reg &= ~DC_WR_CH_CONF_PROG_DI_ID; + reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID; + __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan)); + } + + reg = 0x2; + reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET; + reg |= di << 2; + if (interlaced) + reg |= DC_WR_CH_CONF_FIELD_MODE; + } else if ((dc_chan == 8) || (dc_chan == 9)) { + /* async channels */ + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1); + + reg = 0x3; + reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET; + } + __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); + + __raw_writel(0x00000000, DC_WR_CH_ADDR(dc_chan)); + + __raw_writel(0x00000084, DC_GEN); +} + +void _ipu_dc_uninit(int dc_chan) +{ + if ((dc_chan == 1) || (dc_chan == 5)) { + _ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0); + } else if ((dc_chan == 8) || (dc_chan == 9)) { + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0); + } +} + +int _ipu_chan_is_interlaced(ipu_channel_t channel) +{ + if (channel == MEM_DC_SYNC) + return !!(__raw_readl(DC_WR_CH_CONF_1) & + DC_WR_CH_CONF_FIELD_MODE); + else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC)) + return !!(__raw_readl(DC_WR_CH_CONF_5) & + DC_WR_CH_CONF_FIELD_MODE); + return 0; +} + +void _ipu_dp_dc_enable(ipu_channel_t channel) +{ + uint32_t reg; + uint32_t dc_chan; + int irq = 0; + + if (channel == MEM_FG_SYNC) + irq = IPU_IRQ_DP_SF_END; + else if (channel == MEM_DC_SYNC) + dc_chan = 1; + else if (channel == MEM_BG_SYNC) + dc_chan = 5; + else + return; + + if (channel == MEM_FG_SYNC) { + /* Enable FG channel */ + reg = __raw_readl(DP_COM_CONF(DP_SYNC)); + __raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF(DP_SYNC)); + + return; + } + + reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); + reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET; + __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); + + reg = __raw_readl(IPU_DISP_GEN); + if (g_dc_di_assignment[dc_chan]) + reg |= DI1_COUNTER_RELEASE; + else + reg |= DI0_COUNTER_RELEASE; + __raw_writel(reg, IPU_DISP_GEN); +} + +static irqreturn_t dc_irq_handler(int irq, void *dev_id) +{ + u32 reg; + uint32_t dc_chan; + ipu_channel_t channel; + struct completion *comp = dev_id; + + if (irq == IPU_IRQ_DP_SF_END) { + channel = MEM_BG_SYNC; + dc_chan = 5; + } else if (irq == IPU_IRQ_DC_FC_1) { + channel = MEM_DC_SYNC; + dc_chan = 1; + } else { + return IRQ_HANDLED; + } + + reg = __raw_readl(IPU_DISP_GEN); + if (g_dc_di_assignment[dc_chan]) + reg &= ~DI1_COUNTER_RELEASE; + else + reg &= ~DI0_COUNTER_RELEASE; + __raw_writel(reg, IPU_DISP_GEN); + + reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); + reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK; + __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); + + if (__raw_readl(IPUIRQ_2_STATREG(IPU_IRQ_VSYNC_PRE_0 + g_dc_di_assignment[dc_chan])) & + IPUIRQ_2_MASK(IPU_IRQ_VSYNC_PRE_0 + g_dc_di_assignment[dc_chan])) + dev_err(g_ipu_dev, "VSyncPre occurred before DI%d disable\n", g_dc_di_assignment[dc_chan]); + + complete(comp); + return IRQ_HANDLED; +} + +void _ipu_dp_dc_disable(ipu_channel_t channel) +{ + int ret; + uint32_t lock_flags; + uint32_t reg; + uint32_t csc; + uint32_t dc_chan; + int irq = 0; + int timeout = 50; + DECLARE_COMPLETION_ONSTACK(dc_comp); + + if (channel == MEM_DC_SYNC) { + dc_chan = 1; + irq = IPU_IRQ_DC_FC_1; + } else if (channel == MEM_BG_SYNC) { + dc_chan = 5; + irq = IPU_IRQ_DP_SF_END; + } else if (channel == MEM_FG_SYNC) { + /* Disable FG channel */ + + spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(DP_COM_CONF(DP_SYNC)); + csc = reg & DP_COM_CONF_CSC_DEF_MASK; + if (csc == DP_COM_CONF_CSC_DEF_FG) + reg &= ~DP_COM_CONF_CSC_DEF_MASK; + + reg &= ~DP_COM_CONF_FG_EN; + __raw_writel(reg, DP_COM_CONF(DP_SYNC)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + __raw_writel(IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END), + IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END)); + while ((__raw_readl(IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END)) & + IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END)) == 0) { + msleep(2); + timeout -= 2; + if (timeout <= 0) + break; + } + return; + } else { + return; + } + + __raw_writel(IPUIRQ_2_MASK(IPU_IRQ_VSYNC_PRE_0 + g_dc_di_assignment[dc_chan]), + IPUIRQ_2_STATREG(IPU_IRQ_VSYNC_PRE_0 + g_dc_di_assignment[dc_chan])); + ipu_clear_irq(irq); + ret = ipu_request_irq(irq, dc_irq_handler, 0, NULL, &dc_comp); + if (ret < 0) { + dev_err(g_ipu_dev, "DC irq %d in use\n", irq); + return; + } + ret = wait_for_completion_timeout(&dc_comp, msecs_to_jiffies(50)); + + dev_dbg(g_ipu_dev, "DC stop timeout - %d * 10ms\n", 5 - ret); + ipu_free_irq(irq, &dc_comp); +} + +void _ipu_init_dc_mappings(void) +{ + /* IPU_PIX_FMT_RGB24 */ + _ipu_dc_map_clear(0); + _ipu_dc_map_config(0, 0, 7, 0xFF); + _ipu_dc_map_config(0, 1, 15, 0xFF); + _ipu_dc_map_config(0, 2, 23, 0xFF); + + /* IPU_PIX_FMT_RGB666 */ + _ipu_dc_map_clear(1); + _ipu_dc_map_config(1, 0, 5, 0xFC); + _ipu_dc_map_config(1, 1, 11, 0xFC); + _ipu_dc_map_config(1, 2, 17, 0xFC); + + /* IPU_PIX_FMT_YUV444 */ + _ipu_dc_map_clear(2); + _ipu_dc_map_config(2, 0, 15, 0xFF); + _ipu_dc_map_config(2, 1, 23, 0xFF); + _ipu_dc_map_config(2, 2, 7, 0xFF); + + /* IPU_PIX_FMT_RGB565 */ + _ipu_dc_map_clear(3); + _ipu_dc_map_config(3, 0, 4, 0xF8); + _ipu_dc_map_config(3, 1, 10, 0xFC); + _ipu_dc_map_config(3, 2, 15, 0xF8); + + /* IPU_PIX_FMT_LVDS666 */ + _ipu_dc_map_clear(4); + _ipu_dc_map_config(4, 0, 5, 0xFC); + _ipu_dc_map_config(4, 1, 13, 0xFC); + _ipu_dc_map_config(4, 2, 21, 0xFC); +} + +int _ipu_pixfmt_to_map(uint32_t fmt) +{ + switch (fmt) { + case IPU_PIX_FMT_GENERIC: + case IPU_PIX_FMT_RGB24: + return 0; + case IPU_PIX_FMT_RGB666: + return 1; + case IPU_PIX_FMT_YUV444: + return 2; + case IPU_PIX_FMT_RGB565: + return 3; + case IPU_PIX_FMT_LVDS666: + return 4; + } + + return -1; +} + +/*! + * This function sets the colorspace for of dp. + * modes. + * + * @param channel Input parameter for the logical channel ID. + * + * @param param If it's not NULL, update the csc table + * with this parameter. + * + * @return N/A + */ +void _ipu_dp_set_csc_coefficients(ipu_channel_t channel, int32_t param[][3]) +{ + int dp; + struct dp_csc_param_t dp_csc_param; + + if (channel == MEM_FG_SYNC) + dp = DP_SYNC; + else if (channel == MEM_BG_SYNC) + dp = DP_SYNC; + else if (channel == MEM_BG_ASYNC0) + dp = DP_ASYNC0; + else + return; + + dp_csc_param.mode = -1; + dp_csc_param.coeff = param; + __ipu_dp_csc_setup(dp, dp_csc_param, true); +} + +/*! + * This function is called to initialize a synchronous LCD panel. + * + * @param disp The DI the panel is attached to. + * + * @param pixel_clk Desired pixel clock frequency in Hz. + * + * @param pixel_fmt Input parameter for pixel format of buffer. + * Pixel format is a FOURCC ASCII code. + * + * @param width The width of panel in pixels. + * + * @param height The height of panel in pixels. + * + * @param hStartWidth The number of pixel clocks between the HSYNC + * signal pulse and the start of valid data. + * + * @param hSyncWidth The width of the HSYNC signal in units of pixel + * clocks. + * + * @param hEndWidth The number of pixel clocks between the end of + * valid data and the HSYNC signal for next line. + * + * @param vStartWidth The number of lines between the VSYNC + * signal pulse and the start of valid data. + * + * @param vSyncWidth The width of the VSYNC signal in units of lines + * + * @param vEndWidth The number of lines between the end of valid + * data and the VSYNC signal for next frame. + * + * @param sig Bitfield of signal polarities for LCD interface. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint16_t h_start_width, uint16_t h_sync_width, + uint16_t h_end_width, uint16_t v_start_width, + uint16_t v_sync_width, uint16_t v_end_width, + uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig) +{ + unsigned long lock_flags; + uint32_t field0_offset = 0; + uint32_t field1_offset; + uint32_t reg; + uint32_t disp_gen, di_gen, vsync_cnt; + uint32_t div, up; + uint32_t h_total, v_total; + int map; + struct clk *di_clk; + + dev_dbg(g_ipu_dev, "panel size = %d x %d\n", width, height); + + if ((v_sync_width == 0) || (h_sync_width == 0)) + return EINVAL; + + h_total = width + h_sync_width + h_start_width + h_end_width; + v_total = height + v_sync_width + v_start_width + v_end_width; + + /* Init clocking */ + dev_dbg(g_ipu_dev, "pixel clk = %d\n", pixel_clk); + if (sig.ext_clk) + di_clk = g_di_clk[disp]; + else + di_clk = g_ipu_clk; + + /* + * Calculate divider + * Fractional part is 4 bits, + * so simply multiply by 2^4 to get fractional part. + */ + div = (clk_get_rate(di_clk) * 16) / pixel_clk; + if (div < 0x10) /* Min DI disp clock divider is 1 */ + div = 0x10; + /* + * DI disp clock offset is zero, + * and fractional part is rounded off to 0.5. + */ + div &= 0xFF8; + + reg = __raw_readl(DI_GENERAL(disp)); + if (sig.ext_clk) + __raw_writel(reg | DI_GEN_DI_CLK_EXT, DI_GENERAL(disp)); + else + __raw_writel(reg & ~DI_GEN_DI_CLK_EXT, DI_GENERAL(disp)); + + spin_lock_irqsave(&ipu_lock, lock_flags); + + disp_gen = __raw_readl(IPU_DISP_GEN); + disp_gen &= disp ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE; + __raw_writel(disp_gen, IPU_DISP_GEN); + + __raw_writel(div, DI_BS_CLKGEN0(disp)); + + /* Setup pixel clock timing */ + /* FIXME: needs to be more flexible */ + /* Down time is half of period */ + __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(disp)); + + _ipu_di_data_wave_config(disp, SYNC_WAVE, div / 16 - 1, div / 16 - 1); + _ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div / 16 * 2); + + div = div / 16; /* Now divider is integer portion */ + + map = _ipu_pixfmt_to_map(pixel_fmt); + if (map < 0) { + dev_dbg(g_ipu_dev, "IPU_DISP: No MAP\n"); + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return -EINVAL; + } + + di_gen = 0; + if (sig.ext_clk) + di_gen |= DI_GEN_DI_CLK_EXT; + + if (sig.interlaced) { + if (cpu_is_mx51_rev(CHIP_REV_2_0)) { + /* Setup internal HSYNC waveform */ + _ipu_di_sync_config( + disp, /* display */ + 1, /* counter */ + h_total/2 - 1, /* run count */ + DI_SYNC_CLK, /* run_resolution */ + 0, /* offset */ + DI_SYNC_NONE, /* offset resolution */ + 0, /* repeat count */ + DI_SYNC_NONE, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* Field 1 VSYNC waveform */ + _ipu_di_sync_config( + disp, /* display */ + 2, /* counter */ + h_total - 1, /* run count */ + DI_SYNC_CLK, /* run_resolution */ + 0, /* offset */ + DI_SYNC_NONE, /* offset resolution */ + 0, /* repeat count */ + DI_SYNC_NONE, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 4 /* COUNT DOWN */ + ); + + /* Setup internal HSYNC waveform */ + _ipu_di_sync_config( + disp, /* display */ + 3, /* counter */ + v_total*2 - 1, /* run count */ + DI_SYNC_INT_HSYNC, /* run_resolution */ + 1, /* offset */ + DI_SYNC_INT_HSYNC, /* offset resolution */ + 0, /* repeat count */ + DI_SYNC_NONE, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 4 /* COUNT DOWN */ + ); + + /* Active Field ? */ + _ipu_di_sync_config( + disp, /* display */ + 4, /* counter */ + v_total/2 - 1, /* run count */ + DI_SYNC_HSYNC, /* run_resolution */ + v_start_width, /* offset */ + DI_SYNC_HSYNC, /* offset resolution */ + 2, /* repeat count */ + DI_SYNC_VSYNC, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* Active Line */ + _ipu_di_sync_config( + disp, /* display */ + 5, /* counter */ + 0, /* run count */ + DI_SYNC_HSYNC, /* run_resolution */ + 0, /* offset */ + DI_SYNC_NONE, /* offset resolution */ + height/2, /* repeat count */ + 4, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* Field 0 VSYNC waveform */ + _ipu_di_sync_config( + disp, /* display */ + 6, /* counter */ + v_total - 1, /* run count */ + DI_SYNC_HSYNC, /* run_resolution */ + 0, /* offset */ + DI_SYNC_NONE, /* offset resolution */ + 0, /* repeat count */ + DI_SYNC_NONE, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* DC VSYNC waveform */ + vsync_cnt = 7; + _ipu_di_sync_config( + disp, /* display */ + 7, /* counter */ + v_total/2 - 1, /* run count */ + DI_SYNC_HSYNC, /* run_resolution */ + 9, /* offset */ + DI_SYNC_HSYNC, /* offset resolution */ + 2, /* repeat count */ + DI_SYNC_VSYNC, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* active pixel waveform */ + _ipu_di_sync_config( + disp, /* display */ + 8, /* counter */ + 0, /* run count */ + DI_SYNC_CLK, /* run_resolution */ + h_start_width, /* offset */ + DI_SYNC_CLK, /* offset resolution */ + width, /* repeat count */ + 5, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* ??? */ + _ipu_di_sync_config( + disp, /* display */ + 9, /* counter */ + v_total - 1, /* run count */ + DI_SYNC_INT_HSYNC, /* run_resolution */ + v_total/2, /* offset */ + DI_SYNC_INT_HSYNC, /* offset resolution */ + 0, /* repeat count */ + DI_SYNC_HSYNC, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 4 /* COUNT DOWN */ + ); + + /* set gentime select and tag sel */ + reg = __raw_readl(DI_SW_GEN1(disp, 9)); + reg &= 0x1FFFFFFF; + reg |= (3-1)<<29 | 0x00008000; + __raw_writel(reg, DI_SW_GEN1(disp, 9)); + + __raw_writel(v_total / 2 - 1, DI_SCR_CONF(disp)); + + /* set y_sel = 1 */ + di_gen |= 0x10000000; + di_gen |= DI_GEN_POLARITY_5; + di_gen |= DI_GEN_POLARITY_8; + } else { + /* Setup internal HSYNC waveform */ + _ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK, + 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, + DI_SYNC_NONE, 0, 0); + + field1_offset = v_sync_width + v_start_width + height / 2 + + v_end_width; + if (sig.odd_field_first) { + field0_offset = field1_offset - 1; + field1_offset = 0; + } + v_total += v_start_width + v_end_width; + + /* Field 1 VSYNC waveform */ + _ipu_di_sync_config(disp, 2, v_total - 1, 1, + field0_offset, + field0_offset ? 1 : DI_SYNC_NONE, + 0, DI_SYNC_NONE, 0, + DI_SYNC_NONE, DI_SYNC_NONE, 0, 4); + + /* Setup internal HSYNC waveform */ + _ipu_di_sync_config(disp, 3, h_total - 1, DI_SYNC_CLK, + 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, + DI_SYNC_NONE, DI_SYNC_NONE, 0, 4); + + /* Active Field ? */ + _ipu_di_sync_config(disp, 4, + field0_offset ? + field0_offset : field1_offset - 2, + 1, v_start_width + v_sync_width, 1, 2, 2, + 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0); + + /* Active Line */ + _ipu_di_sync_config(disp, 5, 0, 1, + 0, DI_SYNC_NONE, + height / 2, 4, 0, DI_SYNC_NONE, + DI_SYNC_NONE, 0, 0); + + /* Field 0 VSYNC waveform */ + _ipu_di_sync_config(disp, 6, v_total - 1, 1, + 0, DI_SYNC_NONE, + 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, + DI_SYNC_NONE, 0, 0); + + /* DC VSYNC waveform */ + vsync_cnt = 7; + _ipu_di_sync_config(disp, 7, 0, 1, + field1_offset, + field1_offset ? 1 : DI_SYNC_NONE, + 1, 2, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0); + + /* active pixel waveform */ + _ipu_di_sync_config(disp, 8, 0, DI_SYNC_CLK, + h_sync_width + h_start_width, DI_SYNC_CLK, + width, 5, 0, DI_SYNC_NONE, DI_SYNC_NONE, + 0, 0); + + /* ??? */ + _ipu_di_sync_config(disp, 9, v_total - 1, 2, + 0, DI_SYNC_NONE, + 0, DI_SYNC_NONE, 6, DI_SYNC_NONE, + DI_SYNC_NONE, 0, 0); + + reg = __raw_readl(DI_SW_GEN1(disp, 9)); + reg |= 0x8000; + __raw_writel(reg, DI_SW_GEN1(disp, 9)); + + __raw_writel(v_sync_width + v_start_width + + v_end_width + height / 2 - 1, DI_SCR_CONF(disp)); + } + + /* Init template microcode */ + _ipu_dc_write_tmpl(0, WROD(0), 0, map, SYNC_WAVE, 0, 8); + + if (sig.Hsync_pol) + di_gen |= DI_GEN_POLARITY_3; + if (sig.Vsync_pol) + di_gen |= DI_GEN_POLARITY_2; + } else { + /* Setup internal HSYNC waveform */ + _ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK, + 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, + DI_SYNC_NONE, 0, 0); + + /* Setup external (delayed) HSYNC waveform */ + _ipu_di_sync_config(disp, DI_SYNC_HSYNC, h_total - 1, + DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK, + 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, + DI_SYNC_NONE, 0, div * h_sync_width * 2); + /* Setup VSYNC waveform */ + vsync_cnt = DI_SYNC_VSYNC; + _ipu_di_sync_config(disp, DI_SYNC_VSYNC, v_total - 1, + DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0, + DI_SYNC_NONE, 1, DI_SYNC_NONE, + DI_SYNC_INT_HSYNC, 0, v_sync_width * 2); + __raw_writel(v_total - 1, DI_SCR_CONF(disp)); + + /* Setup active data waveform to sync with DC */ + _ipu_di_sync_config(disp, 4, 0, DI_SYNC_HSYNC, + v_start_width, DI_SYNC_HSYNC, height, + DI_SYNC_VSYNC, 0, DI_SYNC_NONE, + DI_SYNC_NONE, 0, 0); + _ipu_di_sync_config(disp, 5, 0, DI_SYNC_CLK, + h_sync_width + h_start_width, DI_SYNC_CLK, + width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, + 0); + + /* Init template microcode */ + _ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5); + _ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5); + _ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5); + + if (sig.Hsync_pol) + di_gen |= DI_GEN_POLARITY_2; + if (sig.Vsync_pol) + di_gen |= DI_GEN_POLARITY_3; + } + + __raw_writel(di_gen, DI_GENERAL(disp)); + __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) | 0x00000002, + DI_SYNC_AS_GEN(disp)); + + reg = __raw_readl(DI_POL(disp)); + reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15); + if (sig.enable_pol) + reg |= DI_POL_DRDY_POLARITY_15; + if (sig.data_pol) + reg |= DI_POL_DRDY_DATA_POLARITY; + __raw_writel(reg, DI_POL(disp)); + + __raw_writel(width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp))); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} +EXPORT_SYMBOL(ipu_init_sync_panel); + + +int ipu_init_async_panel(int disp, int type, uint32_t cycle_time, + uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig) +{ + unsigned long lock_flags; + int map; + u32 ser_conf = 0; + u32 div; + u32 di_clk = clk_get_rate(g_ipu_clk); + + /* round up cycle_time, then calcalate the divider using scaled math */ + cycle_time += (1000000000UL / di_clk) - 1; + div = (cycle_time * (di_clk / 256UL)) / (1000000000UL / 256UL); + + map = _ipu_pixfmt_to_map(pixel_fmt); + if (map < 0) + return -EINVAL; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + if (type == IPU_PANEL_SERIAL) { + __raw_writel((div << 24) | ((sig.ifc_width - 1) << 4), + DI_DW_GEN(disp, ASYNC_SER_WAVE)); + + _ipu_di_data_pin_config(disp, ASYNC_SER_WAVE, DI_PIN_CS, + 0, 0, (div * 2) + 1); + _ipu_di_data_pin_config(disp, ASYNC_SER_WAVE, DI_PIN_SER_CLK, + 1, div, div * 2); + _ipu_di_data_pin_config(disp, ASYNC_SER_WAVE, DI_PIN_SER_RS, + 2, 0, 0); + + _ipu_dc_write_tmpl(0x64, WROD(0), 0, map, ASYNC_SER_WAVE, 0, 0); + + /* Configure DC for serial panel */ + __raw_writel(0x14, DC_DISP_CONF1(DC_DISP_ID_SERIAL)); + + if (sig.clk_pol) + ser_conf |= DI_SER_CONF_SERIAL_CLK_POL; + if (sig.data_pol) + ser_conf |= DI_SER_CONF_SERIAL_DATA_POL; + if (sig.rs_pol) + ser_conf |= DI_SER_CONF_SERIAL_RS_POL; + if (sig.cs_pol) + ser_conf |= DI_SER_CONF_SERIAL_CS_POL; + __raw_writel(ser_conf, DI_SER_CONF(disp)); + } + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return 0; +} +EXPORT_SYMBOL(ipu_init_async_panel); + +/*! + * This function sets the foreground and background plane global alpha blending + * modes. + * + * @param enable Boolean to enable or disable global alpha + * blending. If disabled, local blending is used. + * + * @param alpha Global alpha value. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, bool enable, + uint8_t alpha) +{ + uint32_t reg; + uint32_t flow; + unsigned long lock_flags; + + if (channel == MEM_BG_SYNC) + flow = DP_SYNC; + else if (channel == MEM_BG_ASYNC0) + flow = DP_ASYNC0; + else if (channel == MEM_BG_ASYNC1) + flow = DP_ASYNC1; + else + return -EINVAL; + + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + spin_lock_irqsave(&ipu_lock, lock_flags); + + if (enable) { + reg = __raw_readl(DP_GRAPH_WIND_CTRL(flow)) & 0x00FFFFFFL; + __raw_writel(reg | ((uint32_t) alpha << 24), + DP_GRAPH_WIND_CTRL(flow)); + + reg = __raw_readl(DP_COM_CONF(flow)); + __raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF(flow)); + } else { + reg = __raw_readl(DP_COM_CONF(flow)); + __raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF(flow)); + } + + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); + + return 0; +} +EXPORT_SYMBOL(ipu_disp_set_global_alpha); + +/*! + * This function sets the transparent color key for SDC graphic plane. + * + * @param channel Input parameter for the logical channel ID. + * + * @param enable Boolean to enable or disable color key + * + * @param colorKey 24-bit RGB color for transparent color key. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_disp_set_color_key(ipu_channel_t channel, bool enable, + uint32_t color_key) +{ + uint32_t reg, flow; + int y, u, v; + int red, green, blue; + unsigned long lock_flags; + + if (channel == MEM_BG_SYNC) + flow = DP_SYNC; + else if (channel == MEM_BG_ASYNC0) + flow = DP_ASYNC0; + else if (channel == MEM_BG_ASYNC1) + flow = DP_ASYNC1; + else + return -EINVAL; + + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + + /* Transform color key from rgb to yuv if CSC is enabled */ + reg = __raw_readl(DP_COM_CONF(flow)); + if ((reg & DP_COM_CONF_CSC_DEF_MASK) == DP_COM_CONF_CSC_DEF_BG) { + red = (color_key >> 16) & 0xFF; + green = (color_key >> 8) & 0xFF; + blue = color_key & 0xFF; + + y = _rgb_to_yuv(0, red, green, blue); + u = _rgb_to_yuv(0, red, green, blue); + v = _rgb_to_yuv(0, red, green, blue); + color_key = (y << 16) | (u << 8) | v; + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + if (enable) { + reg = __raw_readl(DP_GRAPH_WIND_CTRL(flow)) & 0xFF000000L; + __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL(flow)); + + reg = __raw_readl(DP_COM_CONF(flow)); + __raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF(flow)); + } else { + reg = __raw_readl(DP_COM_CONF(flow)); + __raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF(flow)); + } + + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); + + return 0; +} +EXPORT_SYMBOL(ipu_disp_set_color_key); + +/*! + * This function sets the window position of the foreground or background plane. + * modes. + * + * @param channel Input parameter for the logical channel ID. + * + * @param x_pos The X coordinate position to place window at. + * The position is relative to the top left corner. + * + * @param y_pos The Y coordinate position to place window at. + * The position is relative to the top left corner. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_disp_set_window_pos(ipu_channel_t channel, int16_t x_pos, + int16_t y_pos) +{ + u32 reg; + unsigned long lock_flags; + uint32_t flow = 0; + + if (channel == MEM_FG_SYNC) + flow = DP_SYNC; + else if (channel == MEM_FG_ASYNC0) + flow = DP_ASYNC0; + else if (channel == MEM_FG_ASYNC1) + flow = DP_ASYNC1; + else + return -EINVAL; + + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + + spin_lock_irqsave(&ipu_lock, lock_flags); + + __raw_writel((x_pos << 16) | y_pos, DP_FG_POS(flow)); + + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); + + return 0; +} +EXPORT_SYMBOL(ipu_disp_set_window_pos); + +void ipu_disp_direct_write(ipu_channel_t channel, u32 value, u32 offset) +{ + if (channel == DIRECT_ASYNC0) + __raw_writel(value, ipu_disp_base[0] + offset); + else if (channel == DIRECT_ASYNC1) + __raw_writel(value, ipu_disp_base[1] + offset); +} +EXPORT_SYMBOL(ipu_disp_direct_write); + +void ipu_reset_disp_panel(void) +{ + uint32_t tmp; + + tmp = __raw_readl(DI_GENERAL(1)); + __raw_writel(tmp | 0x08, DI_GENERAL(1)); + msleep(10); /* tRES >= 100us */ + tmp = __raw_readl(DI_GENERAL(1)); + __raw_writel(tmp & ~0x08, DI_GENERAL(1)); + msleep(60); + + return; +} +EXPORT_SYMBOL(ipu_reset_disp_panel); diff -urN linux-2.6.26/drivers/mxc/ipu3/ipu_ic.c linux-2.6.26-lab126/drivers/mxc/ipu3/ipu_ic.c --- linux-2.6.26/drivers/mxc/ipu3/ipu_ic.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu3/ipu_ic.c 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,632 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * @file ipu_ic.c + * + * @brief IPU IC functions + * + * @ingroup IPU + */ +#include +#include +#include +#include +#include +#include + +#include "ipu_prv.h" +#include "ipu_regs.h" +#include "ipu_param_mem.h" + +enum { + IC_TASK_VIEWFINDER, + IC_TASK_ENCODER, + IC_TASK_POST_PROCESSOR +}; + +static void _init_csc(uint8_t ic_task, ipu_color_space_t in_format, + ipu_color_space_t out_format); +static bool _calc_resize_coeffs(uint32_t inSize, uint32_t outSize, + uint32_t *resizeCoeff, + uint32_t *downsizeCoeff); + +void ic_dump_register(void) +{ + printk(KERN_DEBUG "IC_CONF = \t0x%08X\n", __raw_readl(IC_CONF)); + printk(KERN_DEBUG "IC_PRP_ENC_RSC = \t0x%08X\n", + __raw_readl(IC_PRP_ENC_RSC)); + printk(KERN_DEBUG "IC_PRP_VF_RSC = \t0x%08X\n", + __raw_readl(IC_PRP_VF_RSC)); + printk(KERN_DEBUG "IC_PP_RSC = \t0x%08X\n", __raw_readl(IC_PP_RSC)); + printk(KERN_DEBUG "IC_IDMAC_1 = \t0x%08X\n", __raw_readl(IC_IDMAC_1)); + printk(KERN_DEBUG "IC_IDMAC_2 = \t0x%08X\n", __raw_readl(IC_IDMAC_2)); + printk(KERN_DEBUG "IC_IDMAC_3 = \t0x%08X\n", __raw_readl(IC_IDMAC_3)); +} + +void _ipu_ic_enable_task(ipu_channel_t channel) +{ + uint32_t ic_conf; + + ic_conf = __raw_readl(IC_CONF); + switch (channel) { + case CSI_PRP_VF_MEM: + case MEM_PRP_VF_MEM: + ic_conf |= IC_CONF_PRPVF_EN; + break; + case MEM_ROT_VF_MEM: + ic_conf |= IC_CONF_PRPVF_ROT_EN; + break; + case CSI_PRP_ENC_MEM: + case MEM_PRP_ENC_MEM: + ic_conf |= IC_CONF_PRPENC_EN; + break; + case MEM_ROT_ENC_MEM: + ic_conf |= IC_CONF_PRPENC_ROT_EN; + break; + case MEM_PP_MEM: + ic_conf |= IC_CONF_PP_EN; + break; + case MEM_ROT_PP_MEM: + ic_conf |= IC_CONF_PP_ROT_EN; + break; + default: + break; + } + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_ic_disable_task(ipu_channel_t channel) +{ + uint32_t ic_conf; + + ic_conf = __raw_readl(IC_CONF); + switch (channel) { + case CSI_PRP_VF_MEM: + case MEM_PRP_VF_MEM: + ic_conf &= ~IC_CONF_PRPVF_EN; + break; + case MEM_ROT_VF_MEM: + ic_conf &= ~IC_CONF_PRPVF_ROT_EN; + break; + case CSI_PRP_ENC_MEM: + case MEM_PRP_ENC_MEM: + ic_conf &= ~IC_CONF_PRPENC_EN; + break; + case MEM_ROT_ENC_MEM: + ic_conf &= ~IC_CONF_PRPENC_ROT_EN; + break; + case MEM_PP_MEM: + ic_conf &= ~IC_CONF_PP_EN; + break; + case MEM_ROT_PP_MEM: + ic_conf &= ~IC_CONF_PP_ROT_EN; + break; + default: + break; + } + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_ic_init_prpvf(ipu_channel_params_t *params, bool src_is_csi) +{ + uint32_t reg, ic_conf; + uint32_t downsizeCoeff, resizeCoeff; + ipu_color_space_t in_fmt, out_fmt; + + /* Setup vertical resizing */ + _calc_resize_coeffs(params->mem_prp_vf_mem.in_height, + params->mem_prp_vf_mem.out_height, + &resizeCoeff, &downsizeCoeff); + reg = (downsizeCoeff << 30) | (resizeCoeff << 16); + + /* Setup horizontal resizing */ + _calc_resize_coeffs(params->mem_prp_vf_mem.in_width, + params->mem_prp_vf_mem.out_width, + &resizeCoeff, &downsizeCoeff); + reg |= (downsizeCoeff << 14) | resizeCoeff; + + __raw_writel(reg, IC_PRP_VF_RSC); + + ic_conf = __raw_readl(IC_CONF); + + /* Setup color space conversion */ + in_fmt = format_to_colorspace(params->mem_prp_vf_mem.in_pixel_fmt); + out_fmt = format_to_colorspace(params->mem_prp_vf_mem.out_pixel_fmt); + if (in_fmt == RGB) { + if ((out_fmt == YCbCr) || (out_fmt == YUV)) { + /* Enable RGB->YCBCR CSC */ + _init_csc(IC_TASK_VIEWFINDER, RGB, out_fmt); + ic_conf |= IC_CONF_PRPVF_CSC1; + } + } + if ((in_fmt == YCbCr) || (in_fmt == YUV)) { + if (out_fmt == RGB) { + /* Enable YCBCR->RGB CSC */ + _init_csc(IC_TASK_VIEWFINDER, YCbCr, RGB); + ic_conf |= IC_CONF_PRPVF_CSC1; + } else { + /* TODO: Support YUV<->YCbCr conversion? */ + } + } + + if (params->mem_prp_vf_mem.graphics_combine_en) { + ic_conf |= IC_CONF_PRPVF_CMB; + + /* need transparent CSC1 conversion */ + _init_csc(IC_TASK_POST_PROCESSOR, RGB, RGB); + ic_conf |= IC_CONF_PRPVF_CSC1; /* Enable RGB->RGB CSC */ + + if (params->mem_prp_vf_mem.global_alpha_en) + ic_conf |= IC_CONF_IC_GLB_LOC_A; + else + ic_conf &= ~IC_CONF_IC_GLB_LOC_A; + + if (params->mem_prp_vf_mem.key_color_en) + ic_conf |= IC_CONF_KEY_COLOR_EN; + else + ic_conf &= ~IC_CONF_KEY_COLOR_EN; + } else { + ic_conf &= ~IC_CONF_PRPVF_CMB; + } + + if (src_is_csi) + ic_conf &= ~IC_CONF_RWS_EN; + else + ic_conf |= IC_CONF_RWS_EN; + + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_ic_uninit_prpvf(void) +{ + uint32_t reg; + + reg = __raw_readl(IC_CONF); + reg &= ~(IC_CONF_PRPVF_EN | IC_CONF_PRPVF_CMB | + IC_CONF_PRPVF_CSC2 | IC_CONF_PRPVF_CSC1); + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_rotate_vf(ipu_channel_params_t *params) +{ +} + +void _ipu_ic_uninit_rotate_vf(void) +{ + uint32_t reg; + reg = __raw_readl(IC_CONF); + reg &= ~IC_CONF_PRPVF_ROT_EN; + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_prpenc(ipu_channel_params_t *params, bool src_is_csi) +{ + uint32_t reg, ic_conf; + uint32_t downsizeCoeff, resizeCoeff; + ipu_color_space_t in_fmt, out_fmt; + + /* Setup vertical resizing */ + _calc_resize_coeffs(params->mem_prp_enc_mem.in_height, + params->mem_prp_enc_mem.out_height, + &resizeCoeff, &downsizeCoeff); + reg = (downsizeCoeff << 30) | (resizeCoeff << 16); + + /* Setup horizontal resizing */ + _calc_resize_coeffs(params->mem_prp_enc_mem.in_width, + params->mem_prp_enc_mem.out_width, + &resizeCoeff, &downsizeCoeff); + reg |= (downsizeCoeff << 14) | resizeCoeff; + + __raw_writel(reg, IC_PRP_ENC_RSC); + + ic_conf = __raw_readl(IC_CONF); + + /* Setup color space conversion */ + in_fmt = format_to_colorspace(params->mem_prp_enc_mem.in_pixel_fmt); + out_fmt = format_to_colorspace(params->mem_prp_enc_mem.out_pixel_fmt); + if (in_fmt == RGB) { + if ((out_fmt == YCbCr) || (out_fmt == YUV)) { + /* Enable RGB->YCBCR CSC */ + _init_csc(IC_TASK_ENCODER, RGB, out_fmt); + ic_conf |= IC_CONF_PRPENC_CSC1; + } + } + if ((in_fmt == YCbCr) || (in_fmt == YUV)) { + if (out_fmt == RGB) { + /* Enable YCBCR->RGB CSC */ + _init_csc(IC_TASK_ENCODER, YCbCr, RGB); + ic_conf |= IC_CONF_PRPENC_CSC1; + } else { + /* TODO: Support YUV<->YCbCr conversion? */ + } + } + + if (src_is_csi) + ic_conf &= ~IC_CONF_RWS_EN; + else + ic_conf |= IC_CONF_RWS_EN; + + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_ic_uninit_prpenc(void) +{ + uint32_t reg; + + reg = __raw_readl(IC_CONF); + reg &= ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1); + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_rotate_enc(ipu_channel_params_t *params) +{ +} + +void _ipu_ic_uninit_rotate_enc(void) +{ + uint32_t reg; + + reg = __raw_readl(IC_CONF); + reg &= ~(IC_CONF_PRPENC_ROT_EN); + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_pp(ipu_channel_params_t *params) +{ + uint32_t reg, ic_conf; + uint32_t downsizeCoeff, resizeCoeff; + ipu_color_space_t in_fmt, out_fmt; + + /* Setup vertical resizing */ + _calc_resize_coeffs(params->mem_pp_mem.in_height, + params->mem_pp_mem.out_height, + &resizeCoeff, &downsizeCoeff); + reg = (downsizeCoeff << 30) | (resizeCoeff << 16); + + /* Setup horizontal resizing */ + _calc_resize_coeffs(params->mem_pp_mem.in_width, + params->mem_pp_mem.out_width, + &resizeCoeff, &downsizeCoeff); + reg |= (downsizeCoeff << 14) | resizeCoeff; + + __raw_writel(reg, IC_PP_RSC); + + ic_conf = __raw_readl(IC_CONF); + + /* Setup color space conversion */ + in_fmt = format_to_colorspace(params->mem_pp_mem.in_pixel_fmt); + out_fmt = format_to_colorspace(params->mem_pp_mem.out_pixel_fmt); + if (in_fmt == RGB) { + if ((out_fmt == YCbCr) || (out_fmt == YUV)) { + /* Enable RGB->YCBCR CSC */ + _init_csc(IC_TASK_POST_PROCESSOR, RGB, out_fmt); + ic_conf |= IC_CONF_PP_CSC2; + } + } + if ((in_fmt == YCbCr) || (in_fmt == YUV)) { + if (out_fmt == RGB) { + /* Enable YCBCR->RGB CSC */ + _init_csc(IC_TASK_POST_PROCESSOR, YCbCr, RGB); + ic_conf |= IC_CONF_PP_CSC1; + } else { + /* TODO: Support YUV<->YCbCr conversion? */ + } + } + + if (params->mem_pp_mem.graphics_combine_en) { + ic_conf |= IC_CONF_PP_CMB; + + /* need transparent CSC1 conversion */ + _init_csc(IC_TASK_POST_PROCESSOR, RGB, RGB); + ic_conf |= IC_CONF_PP_CSC1; /* Enable RGB->RGB CSC */ + + if (params->mem_pp_mem.global_alpha_en) + ic_conf |= IC_CONF_IC_GLB_LOC_A; + else + ic_conf &= ~IC_CONF_IC_GLB_LOC_A; + + if (params->mem_pp_mem.key_color_en) + ic_conf |= IC_CONF_KEY_COLOR_EN; + else + ic_conf &= ~IC_CONF_KEY_COLOR_EN; + } else { + ic_conf &= ~IC_CONF_PP_CMB; + } + + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_ic_uninit_pp(void) +{ + uint32_t reg; + + reg = __raw_readl(IC_CONF); + reg &= ~(IC_CONF_PP_EN | IC_CONF_PP_CSC1 | IC_CONF_PP_CSC2 | + IC_CONF_PP_CMB); + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_rotate_pp(ipu_channel_params_t *params) +{ +} + +void _ipu_ic_uninit_rotate_pp(void) +{ + uint32_t reg; + reg = __raw_readl(IC_CONF); + reg &= ~IC_CONF_PP_ROT_EN; + __raw_writel(reg, IC_CONF); +} + +int _ipu_ic_idma_init(int dma_chan, uint16_t width, uint16_t height, + int burst_size, ipu_rotate_mode_t rot) +{ + u32 ic_idmac_1, ic_idmac_2, ic_idmac_3; + u32 temp_rot = bitrev8(rot) >> 5; + bool need_hor_flip = false; + + if ((burst_size != 8) && (burst_size != 16)) { + dev_dbg(g_ipu_dev, "Illegal burst length for IC\n"); + return -EINVAL; + } + + width--; + height--; + + if (temp_rot & 0x2) /* Need horizontal flip */ + need_hor_flip = true; + + ic_idmac_1 = __raw_readl(IC_IDMAC_1); + ic_idmac_2 = __raw_readl(IC_IDMAC_2); + ic_idmac_3 = __raw_readl(IC_IDMAC_3); + if (dma_chan == 22) { /* PP output - CB2 */ + if (burst_size == 16) + ic_idmac_1 |= IC_IDMAC_1_CB2_BURST_16; + else + ic_idmac_1 &= ~IC_IDMAC_1_CB2_BURST_16; + + if (need_hor_flip) + ic_idmac_1 |= IC_IDMAC_1_PP_FLIP_RS; + else + ic_idmac_1 &= ~IC_IDMAC_1_PP_FLIP_RS; + + ic_idmac_2 &= ~IC_IDMAC_2_PP_HEIGHT_MASK; + ic_idmac_2 |= height << IC_IDMAC_2_PP_HEIGHT_OFFSET; + + ic_idmac_3 &= ~IC_IDMAC_3_PP_WIDTH_MASK; + ic_idmac_3 |= width << IC_IDMAC_3_PP_WIDTH_OFFSET; + + } else if (dma_chan == 11) { /* PP Input - CB5 */ + if (burst_size == 16) + ic_idmac_1 |= IC_IDMAC_1_CB5_BURST_16; + else + ic_idmac_1 &= ~IC_IDMAC_1_CB5_BURST_16; + } else if (dma_chan == 47) { /* PP Rot input */ + ic_idmac_1 &= ~IC_IDMAC_1_PP_ROT_MASK; + ic_idmac_1 |= temp_rot << IC_IDMAC_1_PP_ROT_OFFSET; + } + + if (dma_chan == 12) { /* PRP Input - CB6 */ + if (burst_size == 16) + ic_idmac_1 |= IC_IDMAC_1_CB6_BURST_16; + else + ic_idmac_1 &= ~IC_IDMAC_1_CB6_BURST_16; + } + + if (dma_chan == 20) { /* PRP ENC output - CB0 */ + if (burst_size == 16) + ic_idmac_1 |= IC_IDMAC_1_CB0_BURST_16; + else + ic_idmac_1 &= ~IC_IDMAC_1_CB0_BURST_16; + + if (need_hor_flip) + ic_idmac_1 |= IC_IDMAC_1_PRPENC_FLIP_RS; + else + ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_FLIP_RS; + + ic_idmac_2 &= ~IC_IDMAC_2_PRPENC_HEIGHT_MASK; + ic_idmac_2 |= height << IC_IDMAC_2_PRPENC_HEIGHT_OFFSET; + + ic_idmac_3 &= ~IC_IDMAC_3_PRPENC_WIDTH_MASK; + ic_idmac_3 |= width << IC_IDMAC_3_PRPENC_WIDTH_OFFSET; + + } else if (dma_chan == 45) { /* PRP ENC Rot input */ + ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_ROT_MASK; + ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPENC_ROT_OFFSET; + } + + if (dma_chan == 21) { /* PRP VF output - CB1 */ + if (burst_size == 16) + ic_idmac_1 |= IC_IDMAC_1_CB1_BURST_16; + else + ic_idmac_1 &= ~IC_IDMAC_1_CB1_BURST_16; + + if (need_hor_flip) + ic_idmac_1 |= IC_IDMAC_1_PRPVF_FLIP_RS; + else + ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_FLIP_RS; + + ic_idmac_2 &= ~IC_IDMAC_2_PRPVF_HEIGHT_MASK; + ic_idmac_2 |= height << IC_IDMAC_2_PRPVF_HEIGHT_OFFSET; + + ic_idmac_3 &= ~IC_IDMAC_3_PRPVF_WIDTH_MASK; + ic_idmac_3 |= width << IC_IDMAC_3_PRPVF_WIDTH_OFFSET; + + } else if (dma_chan == 46) { /* PRP VF Rot input */ + ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_ROT_MASK; + ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPVF_ROT_OFFSET; + } + __raw_writel(ic_idmac_1, IC_IDMAC_1); + __raw_writel(ic_idmac_2, IC_IDMAC_2); + __raw_writel(ic_idmac_3, IC_IDMAC_3); + + return 0; +} + +static void _init_csc(uint8_t ic_task, ipu_color_space_t in_format, + ipu_color_space_t out_format) +{ + +/* Y = R * .299 + G * .587 + B * .114; + U = R * -.169 + G * -.332 + B * .500 + 128.; + V = R * .500 + G * -.419 + B * -.0813 + 128.;*/ + static const uint32_t rgb2ycbcr_coeff[4][3] = { + {0x004D, 0x0096, 0x001D}, + {0x01D5, 0x01AB, 0x0080}, + {0x0080, 0x0195, 0x01EB}, + {0x0000, 0x0200, 0x0200}, /* A0, A1, A2 */ + }; + + /* transparent RGB->RGB matrix for combining + */ + static const uint32_t rgb2rgb_coeff[4][3] = { + {0x0080, 0x0000, 0x0000}, + {0x0000, 0x0080, 0x0000}, + {0x0000, 0x0000, 0x0080}, + {0x0000, 0x0000, 0x0000}, /* A0, A1, A2 */ + }; + +/* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128)); + G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128)); + B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */ + static const uint32_t ycbcr2rgb_coeff[4][3] = { + {149, 0, 204}, + {149, 462, 408}, + {149, 255, 0}, + {8192 - 446, 266, 8192 - 554}, /* A0, A1, A2 */ + }; + + uint32_t param; + uint32_t *base = NULL; + + if (ic_task == IC_TASK_ENCODER) { + base = ipu_tpmem_base + 0x2008 / 4; + } else if (ic_task == IC_TASK_VIEWFINDER) { + base = ipu_tpmem_base + 0x4028 / 4; + } else if (ic_task == IC_TASK_POST_PROCESSOR) { + base = ipu_tpmem_base + 0x6060 / 4; + } else { + BUG(); + } + + if ((in_format == YCbCr) && (out_format == RGB)) { + /* Init CSC1 (YCbCr->RGB) */ + param = (ycbcr2rgb_coeff[3][0] << 27) | + (ycbcr2rgb_coeff[0][0] << 18) | + (ycbcr2rgb_coeff[1][1] << 9) | ycbcr2rgb_coeff[2][2]; + __raw_writel(param, base++); + /* scale = 2, sat = 0 */ + param = (ycbcr2rgb_coeff[3][0] >> 5) | (2L << (40 - 32)); + __raw_writel(param, base++); + + param = (ycbcr2rgb_coeff[3][1] << 27) | + (ycbcr2rgb_coeff[0][1] << 18) | + (ycbcr2rgb_coeff[1][0] << 9) | ycbcr2rgb_coeff[2][0]; + __raw_writel(param, base++); + param = (ycbcr2rgb_coeff[3][1] >> 5); + __raw_writel(param, base++); + + param = (ycbcr2rgb_coeff[3][2] << 27) | + (ycbcr2rgb_coeff[0][2] << 18) | + (ycbcr2rgb_coeff[1][2] << 9) | ycbcr2rgb_coeff[2][1]; + __raw_writel(param, base++); + param = (ycbcr2rgb_coeff[3][2] >> 5); + __raw_writel(param, base++); + } else if ((in_format == RGB) && (out_format == YCbCr)) { + /* Init CSC1 (RGB->YCbCr) */ + param = (rgb2ycbcr_coeff[3][0] << 27) | + (rgb2ycbcr_coeff[0][0] << 18) | + (rgb2ycbcr_coeff[1][1] << 9) | rgb2ycbcr_coeff[2][2]; + __raw_writel(param, base++); + /* scale = 1, sat = 0 */ + param = (rgb2ycbcr_coeff[3][0] >> 5) | (1UL << 8); + __raw_writel(param, base++); + + param = (rgb2ycbcr_coeff[3][1] << 27) | + (rgb2ycbcr_coeff[0][1] << 18) | + (rgb2ycbcr_coeff[1][0] << 9) | rgb2ycbcr_coeff[2][0]; + __raw_writel(param, base++); + param = (rgb2ycbcr_coeff[3][1] >> 5); + __raw_writel(param, base++); + + param = (rgb2ycbcr_coeff[3][2] << 27) | + (rgb2ycbcr_coeff[0][2] << 18) | + (rgb2ycbcr_coeff[1][2] << 9) | rgb2ycbcr_coeff[2][1]; + __raw_writel(param, base++); + param = (rgb2ycbcr_coeff[3][2] >> 5); + __raw_writel(param, base++); + } else if ((in_format == RGB) && (out_format == RGB)) { + /* Init CSC1 */ + param = + (rgb2rgb_coeff[3][0] << 27) | (rgb2rgb_coeff[0][0] << 18) | + (rgb2rgb_coeff[1][1] << 9) | rgb2rgb_coeff[2][2]; + __raw_writel(param, base++); + /* scale = 2, sat = 0 */ + param = (rgb2rgb_coeff[3][0] >> 5) | (2UL << 8); + __raw_writel(param, base++); + + param = + (rgb2rgb_coeff[3][1] << 27) | (rgb2rgb_coeff[0][1] << 18) | + (rgb2rgb_coeff[1][0] << 9) | rgb2rgb_coeff[2][0]; + __raw_writel(param, base++); + param = (rgb2rgb_coeff[3][1] >> 5); + __raw_writel(param, base++); + + param = + (rgb2rgb_coeff[3][2] << 27) | (rgb2rgb_coeff[0][2] << 18) | + (rgb2rgb_coeff[1][2] << 9) | rgb2rgb_coeff[2][1]; + __raw_writel(param, base++); + param = (rgb2rgb_coeff[3][2] >> 5); + __raw_writel(param, base++); + } else { + dev_err(g_ipu_dev, "Unsupported color space conversion\n"); + } +} + +static bool _calc_resize_coeffs(uint32_t inSize, uint32_t outSize, + uint32_t *resizeCoeff, + uint32_t *downsizeCoeff) +{ + uint32_t tempSize; + uint32_t tempDownsize; + + /* Cannot downsize more than 8:1 */ + if ((outSize << 3) < inSize) + return false; + + /* compute downsizing coefficient */ + tempDownsize = 0; + tempSize = inSize; + while ((tempSize >= outSize * 2) && (tempDownsize < 2)) { + tempSize >>= 1; + tempDownsize++; + } + *downsizeCoeff = tempDownsize; + + /* compute resizing coefficient using the following equation: + resizeCoeff = M*(SI -1)/(SO - 1) + where M = 2^13, SI - input size, SO - output size */ + *resizeCoeff = (8192L * (tempSize - 1)) / (outSize - 1); + if (*resizeCoeff >= 16384L) { + dev_err(g_ipu_dev, "Warning! Overflow on resize coeff.\n"); + *resizeCoeff = 0x3FFF; + } + + dev_dbg(g_ipu_dev, "resizing from %u -> %u pixels, " + "downsize=%u, resize=%u.%lu (reg=%u)\n", inSize, outSize, + *downsizeCoeff, (*resizeCoeff >= 8192L) ? 1 : 0, + ((*resizeCoeff & 0x1FFF) * 10000L) / 8192L, *resizeCoeff); + + return true; +} diff -urN linux-2.6.26/drivers/mxc/ipu3/ipu_param_mem.h linux-2.6.26-lab126/drivers/mxc/ipu3/ipu_param_mem.h --- linux-2.6.26/drivers/mxc/ipu3/ipu_param_mem.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu3/ipu_param_mem.h 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,332 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __INCLUDE_IPU_PARAM_MEM_H__ +#define __INCLUDE_IPU_PARAM_MEM_H__ + +#include +#include + +extern u32 *ipu_cpmem_base; + +struct ipu_ch_param_word { + uint32_t data[5]; + uint32_t res[3]; +}; + +struct ipu_ch_param { + struct ipu_ch_param_word word[2]; +}; + +#define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch)) + +#define _param_word(base, w) \ + (((struct ipu_ch_param *)(base))->word[(w)].data) + +#define ipu_ch_param_set_field(base, w, bit, size, v) { \ + int i = (bit) / 32; \ + int off = (bit) % 32; \ + _param_word(base, w)[i] |= (v) << off; \ + if (((bit)+(size)-1)/32 > i) { \ + _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \ + } \ +} + +#define ipu_ch_param_mod_field(base, w, bit, size, v) { \ + int i = (bit) / 32; \ + int off = (bit) % 32; \ + u32 mask = (1UL << size) - 1; \ + u32 temp = _param_word(base, w)[i]; \ + temp &= ~(mask << off); \ + _param_word(base, w)[i] = temp | (v) << off; \ + if (((bit)+(size)-1)/32 > i) { \ + temp = _param_word(base, w)[i + 1]; \ + temp &= ~(mask >> (32 - off)); \ + _param_word(base, w)[i + 1] = \ + temp | ((v) >> (off ? (32 - off) : 0)); \ + } \ +} + +#define ipu_ch_param_read_field(base, w, bit, size) ({ \ + u32 temp2; \ + int i = (bit) / 32; \ + int off = (bit) % 32; \ + u32 mask = (1UL << size) - 1; \ + u32 temp1 = _param_word(base, w)[i]; \ + temp1 = mask & (temp1 >> off); \ + if (((bit)+(size)-1)/32 > i) { \ + temp2 = _param_word(base, w)[i + 1]; \ + temp2 &= mask >> (off ? (32 - off) : 0); \ + temp1 |= temp2 << (off ? (32 - off) : 0); \ + } \ + temp1; \ +}) + +static inline void _ipu_ch_params_set_packing(struct ipu_ch_param *p, + int red_width, int red_offset, + int green_width, int green_offset, + int blue_width, int blue_offset, + int alpha_width, int alpha_offset) +{ + /* Setup red width and offset */ + ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1); + ipu_ch_param_set_field(p, 1, 128, 5, red_offset); + /* Setup green width and offset */ + ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1); + ipu_ch_param_set_field(p, 1, 133, 5, green_offset); + /* Setup blue width and offset */ + ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1); + ipu_ch_param_set_field(p, 1, 138, 5, blue_offset); + /* Setup alpha width and offset */ + ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1); + ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset); +} + +static inline void _ipu_ch_param_dump(int ch) +{ + struct ipu_ch_param *p = ipu_ch_param_addr(ch); + pr_debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch, + p->word[0].data[0], p->word[0].data[1], p->word[0].data[2], + p->word[0].data[3], p->word[0].data[4]); + pr_debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch, + p->word[1].data[0], p->word[1].data[1], p->word[1].data[2], + p->word[1].data[3], p->word[1].data[4]); + pr_debug("PFS 0x%x, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4)); + pr_debug("BPP 0x%x, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3)); + pr_debug("NPB 0x%x\n", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7)); + + pr_debug("FW %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13)); + pr_debug("FH %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12)); + pr_debug("Stride %d\n", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14)); + + pr_debug("Width0 %d+1, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3)); + pr_debug("Width1 %d+1, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3)); + pr_debug("Width2 %d+1, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3)); + pr_debug("Width3 %d+1, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3)); + pr_debug("Offset0 %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5)); + pr_debug("Offset1 %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5)); + pr_debug("Offset2 %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5)); + pr_debug("Offset3 %d\n", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5)); +} + +static inline void _ipu_ch_param_init(int ch, + uint32_t pixel_fmt, uint32_t width, + uint32_t height, uint32_t stride, + uint32_t u, uint32_t v, + uint32_t uv_stride, dma_addr_t addr0, + dma_addr_t addr1) +{ + uint32_t u_offset = 0; + uint32_t v_offset = 0; + struct ipu_ch_param params; + + memset(¶ms, 0, sizeof(params)); + + ipu_ch_param_set_field(¶ms, 0, 125, 13, width - 1); + ipu_ch_param_set_field(¶ms, 0, 138, 12, height - 1); + ipu_ch_param_set_field(¶ms, 1, 102, 14, stride - 1); + + ipu_ch_param_set_field(¶ms, 1, 0, 29, addr0 >> 3); + ipu_ch_param_set_field(¶ms, 1, 29, 29, addr1 >> 3); + + switch (pixel_fmt) { + case IPU_PIX_FMT_GENERIC: + /*Represents 8-bit Generic data */ + ipu_ch_param_set_field(¶ms, 0, 107, 3, 5); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 6); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 63); /* burst size */ + break; + case IPU_PIX_FMT_GENERIC_32: + /*Represents 32-bit Generic data */ + break; + case IPU_PIX_FMT_RGB565: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + + _ipu_ch_params_set_packing(¶ms, 5, 0, 6, 5, 5, 11, 1, 16); + break; + case IPU_PIX_FMT_BGR24: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */ + + _ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 1, 24); + break; + case IPU_PIX_FMT_RGB24: + case IPU_PIX_FMT_YUV444: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */ + + _ipu_ch_params_set_packing(¶ms, 8, 16, 8, 8, 8, 0, 1, 24); + break; + case IPU_PIX_FMT_BGRA32: + case IPU_PIX_FMT_BGR32: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ + + _ipu_ch_params_set_packing(¶ms, 8, 8, 8, 16, 8, 24, 8, 0); + break; + case IPU_PIX_FMT_RGBA32: + case IPU_PIX_FMT_RGB32: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ + + _ipu_ch_params_set_packing(¶ms, 8, 24, 8, 16, 8, 8, 8, 0); + break; + case IPU_PIX_FMT_ABGR32: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ + + _ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24); + break; + case IPU_PIX_FMT_UYVY: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 0xA); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + break; + case IPU_PIX_FMT_YUYV: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 0x8); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + break; + case IPU_PIX_FMT_YUV420P2: + case IPU_PIX_FMT_YUV420P: + ipu_ch_param_set_field(¶ms, 1, 85, 4, 2); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + + if (uv_stride < stride / 2) + uv_stride = stride / 2; + + u_offset = stride * height; + v_offset = u_offset + (uv_stride * height / 2); + break; + case IPU_PIX_FMT_YVU422P: + /* BPP & pixel format */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + + if (uv_stride < stride / 2) + uv_stride = stride / 2; + + v_offset = (v == 0) ? stride * height : v; + u_offset = (u == 0) ? v_offset + v_offset / 2 : u; + break; + case IPU_PIX_FMT_YUV422P: + /* BPP & pixel format */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + + if (uv_stride < stride / 2) + uv_stride = stride / 2; + + u_offset = (u == 0) ? stride * height : u; + v_offset = (v == 0) ? u_offset + u_offset / 2 : v; + break; + case IPU_PIX_FMT_NV12: + /* BPP & pixel format */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 4); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + uv_stride = stride; + u_offset = (u == 0) ? stride * height : u; + break; + default: + dev_err(g_ipu_dev, "mxc ipu: unimplemented pixel format\n"); + break; + } + + if (uv_stride) + ipu_ch_param_set_field(¶ms, 1, 128, 14, uv_stride - 1); + + if (u > u_offset) + u_offset = u; + + if (v > v_offset) + v_offset = v; + + ipu_ch_param_set_field(¶ms, 0, 46, 22, u_offset / 8); + ipu_ch_param_set_field(¶ms, 0, 68, 22, v_offset / 8); + + pr_debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch)); + memcpy(ipu_ch_param_addr(ch), ¶ms, sizeof(params)); +}; + +static inline void _ipu_ch_param_set_burst_size(uint32_t ch, + uint16_t burst_pixels) +{ + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 78, 7, + burst_pixels - 1); +}; + +static inline int _ipu_ch_param_get_burst_size(uint32_t ch) +{ + return ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7) + 1; +}; + +static inline int _ipu_ch_param_get_bpp(uint32_t ch) +{ + return ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3); +}; + +static inline void _ipu_ch_param_set_buffer(uint32_t ch, int bufNum, + dma_addr_t phyaddr) +{ + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29, + phyaddr / 8); +}; + +static inline void _ipu_ch_param_set_rotation(uint32_t ch, + ipu_rotate_mode_t rot) +{ + u32 temp_rot = bitrev8(rot) >> 5; + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 0, 119, 3, temp_rot); +}; + +static inline void _ipu_ch_param_set_block_mode(uint32_t ch) +{ + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 0, 117, 2, 1); +}; + +static inline void _ipu_ch_param_set_interlaced_scan(uint32_t ch) +{ + u32 stride; + ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 113, 1, 1); + stride = ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14) + 1; + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 58, 20, stride / 8); + stride *= 2; + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 102, 14, stride - 1); +}; + +static inline void _ipu_ch_param_set_high_priority(uint32_t ch) +{ + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1); +}; + +#endif diff -urN linux-2.6.26/drivers/mxc/ipu3/ipu_prv.h linux-2.6.26-lab126/drivers/mxc/ipu3/ipu_prv.h --- linux-2.6.26/drivers/mxc/ipu3/ipu_prv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu3/ipu_prv.h 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,88 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __INCLUDE_IPU_PRV_H__ +#define __INCLUDE_IPU_PRV_H__ + +#include +#include +#include +#include +#include + +/* Globals */ +extern struct device *g_ipu_dev; +extern spinlock_t ipu_lock; +extern bool g_ipu_clk_enabled; +extern struct clk *g_ipu_clk; +extern struct clk *g_di_clk[2]; +extern struct clk *g_csi_clk[2]; +extern unsigned char g_dc_di_assignment[]; +extern int g_ipu_hw_rev; + +#define IDMA_CHAN_INVALID 0xFF + +struct ipu_channel { + u8 video_in_dma; + u8 alpha_in_dma; + u8 graph_in_dma; + u8 out_dma; +}; + +int register_ipu_device(void); +ipu_color_space_t format_to_colorspace(uint32_t fmt); + +void ipu_dump_registers(void); + +uint32_t _ipu_channel_status(ipu_channel_t channel); + +void _ipu_init_dc_mappings(void); +int _ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt, + uint32_t out_pixel_fmt); +void _ipu_dp_uninit(ipu_channel_t channel); +void _ipu_dc_init(int dc_chan, int di, bool interlaced); +void _ipu_dc_uninit(int dc_chan); +void _ipu_dp_dc_enable(ipu_channel_t channel); +void _ipu_dp_dc_disable(ipu_channel_t channel); +void _ipu_dmfc_init(void); +void _ipu_dmfc_set_wait4eot(int dma_chan, int width); +int _ipu_chan_is_interlaced(ipu_channel_t channel); + +void _ipu_ic_enable_task(ipu_channel_t channel); +void _ipu_ic_disable_task(ipu_channel_t channel); +void _ipu_ic_init_prpvf(ipu_channel_params_t *params, bool src_is_csi); +void _ipu_ic_uninit_prpvf(void); +void _ipu_ic_init_rotate_vf(ipu_channel_params_t *params); +void _ipu_ic_uninit_rotate_vf(void); +void _ipu_ic_init_csi(ipu_channel_params_t *params); +void _ipu_ic_uninit_csi(void); +void _ipu_ic_init_prpenc(ipu_channel_params_t *params, bool src_is_csi); +void _ipu_ic_uninit_prpenc(void); +void _ipu_ic_init_rotate_enc(ipu_channel_params_t *params); +void _ipu_ic_uninit_rotate_enc(void); +void _ipu_ic_init_pp(ipu_channel_params_t *params); +void _ipu_ic_uninit_pp(void); +void _ipu_ic_init_rotate_pp(ipu_channel_params_t *params); +void _ipu_ic_uninit_rotate_pp(void); +int _ipu_ic_idma_init(int dma_chan, uint16_t width, uint16_t height, + int burst_size, ipu_rotate_mode_t rot); +int _ipu_csi_init(ipu_channel_t channel, uint32_t csi); +void ipu_csi_set_test_generator(bool active, uint32_t r_value, + uint32_t g_value, uint32_t b_value, + uint32_t pix_clk, uint32_t csi); +void _ipu_csi_ccir_err_detection_enable(uint32_t csi); +void _ipu_csi_ccir_err_detection_disable(uint32_t csi); +void _ipu_smfc_init(ipu_channel_t channel, uint32_t mipi_id, uint32_t csi); +void _ipu_smfc_set_burst_size(ipu_channel_t channel, uint32_t bs); +void _ipu_dp_set_csc_coefficients(ipu_channel_t channel, int32_t param[][3]); + +#endif /* __INCLUDE_IPU_PRV_H__ */ diff -urN linux-2.6.26/drivers/mxc/ipu3/ipu_regs.h linux-2.6.26-lab126/drivers/mxc/ipu3/ipu_regs.h --- linux-2.6.26/drivers/mxc/ipu3/ipu_regs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ipu3/ipu_regs.h 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,625 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * @file ipu_regs.h + * + * @brief IPU Register definitions + * + * @ingroup IPU + */ +#ifndef __IPU_REGS_INCLUDED__ +#define __IPU_REGS_INCLUDED__ + +#define IPU_DISP0_BASE 0x00000000 +#define IPU_MCU_T_DEFAULT 8 +#define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25) +#define IPU_CM_REG_BASE 0x1E000000 +#define IPU_IDMAC_REG_BASE 0x1E008000 +#define IPU_ISP_REG_BASE 0x1E010000 +#define IPU_DP_REG_BASE 0x1E018000 +#define IPU_IC_REG_BASE 0x1E020000 +#define IPU_IRT_REG_BASE 0x1E028000 +#define IPU_CSI0_REG_BASE 0x1E030000 +#define IPU_CSI1_REG_BASE 0x1E038000 +#define IPU_DI0_REG_BASE 0x1E040000 +#define IPU_DI1_REG_BASE 0x1E048000 +#define IPU_SMFC_REG_BASE 0x1E050000 +#define IPU_DC_REG_BASE 0x1E058000 +#define IPU_DMFC_REG_BASE 0x1E060000 +#define IPU_CPMEM_REG_BASE 0x1F000000 +#define IPU_LUT_REG_BASE 0x1F020000 +#define IPU_SRM_REG_BASE 0x1F040000 +#define IPU_TPM_REG_BASE 0x1F060000 +#define IPU_DC_TMPL_REG_BASE 0x1F080000 +#define IPU_ISP_TBPR_REG_BASE 0x1F0C0000 + +extern u32 *ipu_cm_reg; +extern u32 *ipu_idmac_reg; +extern u32 *ipu_dp_reg; +extern u32 *ipu_ic_reg; +extern u32 *ipu_dc_reg; +extern u32 *ipu_dc_tmpl_reg; +extern u32 *ipu_dmfc_reg; +extern u32 *ipu_di_reg[]; +extern u32 *ipu_smfc_reg; +extern u32 *ipu_csi_reg[]; +extern u32 *ipu_tpmem_base; +extern u32 *ipu_disp_base[]; + +/* Register addresses */ +/* IPU Common registers */ +#define IPU_CONF (ipu_cm_reg) + +#define IPU_SRM_PRI1 (ipu_cm_reg + 0x00A0/4) +#define IPU_SRM_PRI2 (ipu_cm_reg + 0x00A4/4) +#define IPU_FS_PROC_FLOW1 (ipu_cm_reg + 0x00A8/4) +#define IPU_FS_PROC_FLOW2 (ipu_cm_reg + 0x00AC/4) +#define IPU_FS_PROC_FLOW3 (ipu_cm_reg + 0x00B0/4) +#define IPU_FS_DISP_FLOW1 (ipu_cm_reg + 0x00B4/4) +#define IPU_FS_DISP_FLOW2 (ipu_cm_reg + 0x00B8/4) +#define IPU_SKIP (ipu_cm_reg + 0x00BC/4) +#define IPU_DISP_ALT_CONF (ipu_cm_reg + 0x00C0/4) +#define IPU_DISP_GEN (ipu_cm_reg + 0x00C4/4) +#define IPU_DISP_ALT1 (ipu_cm_reg + 0x00C8/4) +#define IPU_DISP_ALT2 (ipu_cm_reg + 0x00CC/4) +#define IPU_DISP_ALT3 (ipu_cm_reg + 0x00D0/4) +#define IPU_DISP_ALT4 (ipu_cm_reg + 0x00D4/4) +#define IPU_SNOOP (ipu_cm_reg + 0x00D8/4) +#define IPU_MEM_RST (ipu_cm_reg + 0x00DC/4) +#define IPU_PM (ipu_cm_reg + 0x00E0/4) +#define IPU_GPR (ipu_cm_reg + 0x00E4/4) +#define IPU_CHA_DB_MODE_SEL(ch) (ipu_cm_reg + 0x0150/4 + (ch / 32)) +#define IPU_ALT_CHA_DB_MODE_SEL(ch) (ipu_cm_reg + 0x0168/4 + (ch / 32)) +#define IPU_CHA_CUR_BUF(ch) ({g_ipu_hw_rev == 2 ? \ + (ipu_cm_reg + 0x023C/4 + (ch / 32)) : \ + (ipu_cm_reg + 0x0124/4 + (ch / 32)); }) +#define IPU_ALT_CUR_BUF0 ({g_ipu_hw_rev == 2 ? \ + (ipu_cm_reg + 0x0244/4) : \ + (ipu_cm_reg + 0x012C/4); }) +#define IPU_ALT_CUR_BUF1 ({g_ipu_hw_rev == 2 ? \ + (ipu_cm_reg + 0x0248/4) : \ + (ipu_cm_reg + 0x0130/4); }) +#define IPU_SRM_STAT ({g_ipu_hw_rev == 2 ? \ + (ipu_cm_reg + 0x024C/4) : \ + (ipu_cm_reg + 0x0134/4); }) +#define IPU_PROC_TASK_STAT ({g_ipu_hw_rev == 2 ? \ + (ipu_cm_reg + 0x0250/4) : \ + (ipu_cm_reg + 0x0138/4); }) +#define IPU_DISP_TASK_STAT ({g_ipu_hw_rev == 2 ? \ + (ipu_cm_reg + 0x0254/4) : \ + (ipu_cm_reg + 0x013C/4); }) +#define IPU_CHA_BUF0_RDY(ch) ({g_ipu_hw_rev == 2 ? \ + (ipu_cm_reg + 0x0268/4 + (ch / 32)) : \ + (ipu_cm_reg + 0x0140/4 + (ch / 32)); }) +#define IPU_CHA_BUF1_RDY(ch) ({g_ipu_hw_rev == 2 ? \ + (ipu_cm_reg + 0x0270/4 + (ch / 32)) : \ + (ipu_cm_reg + 0x0148/4 + (ch / 32)); }) +#define IPU_ALT_CHA_BUF0_RDY(ch) ({g_ipu_hw_rev == 2 ? \ + (ipu_cm_reg + 0x0278/4 + (ch / 32)) : \ + (ipu_cm_reg + 0x0158/4 + (ch / 32)); }) +#define IPU_ALT_CHA_BUF1_RDY(ch) ({g_ipu_hw_rev == 2 ? \ + (ipu_cm_reg + 0x0280/4 + (ch / 32)) : \ + (ipu_cm_reg + 0x0160/4 + (ch / 32)); }) + +#define IPU_INT_CTRL(n) (ipu_cm_reg + 0x003C/4 + ((n) - 1)) +#define IPU_INT_CTRL_IRQ(irq) IPU_INT_CTRL(((irq) / 32)) +#define IPU_INT_STAT_IRQ(irq) IPU_INT_STAT(((irq) / 32)) +#define IPU_INT_STAT(n) ({g_ipu_hw_rev == 2 ? \ + (ipu_cm_reg + 0x0200/4 + ((n) - 1)) : \ + (ipu_cm_reg + 0x00E8/4 + ((n) - 1)); }) + +#define IPUIRQ_2_STATREG(irq) (IPU_INT_STAT(1) + ((irq) / 32)) +#define IPUIRQ_2_CTRLREG(irq) (IPU_INT_CTRL(1) + ((irq) / 32)) +#define IPUIRQ_2_MASK(irq) (1UL << ((irq) & 0x1F)) + +/* CMOS Sensor Interface Registers */ +#define CSI_SENS_CONF(csi) (ipu_csi_reg[csi]) +#define CSI_SENS_FRM_SIZE(csi) (ipu_csi_reg[csi] + 0x0004/4) +#define CSI_ACT_FRM_SIZE(csi) (ipu_csi_reg[csi] + 0x0008/4) +#define CSI_OUT_FRM_CTRL(csi) (ipu_csi_reg[csi] + 0x000C/4) +#define CSI_TST_CTRL(csi) (ipu_csi_reg[csi] + 0x0010/4) +#define CSI_CCIR_CODE_1(csi) (ipu_csi_reg[csi] + 0x0014/4) +#define CSI_CCIR_CODE_2(csi) (ipu_csi_reg[csi] + 0x0018/4) +#define CSI_CCIR_CODE_3(csi) (ipu_csi_reg[csi] + 0x001C/4) +#define CSI_MIPI_DI(csi) (ipu_csi_reg[csi] + 0x0020/4) +#define CSI_SKIP(csi) (ipu_csi_reg[csi] + 0x0024/4) +#define CSI_CPD_CTRL(csi) (ipu_csi_reg[csi] + 0x0028/4) +#define CSI_CPD_RC(csi, n) (ipu_csi_reg[csi] + 0x002C/4 + n) +#define CSI_CPD_RS(csi, n) (ipu_csi_reg[csi] + 0x004C/4 + n) +#define CSI_CPD_GRC(csi, n) (ipu_csi_reg[csi] + 0x005C/4 + n) +#define CSI_CPD_GRS(csi, n) (ipu_csi_reg[csi] + 0x007C/4 + n) +#define CSI_CPD_GBC(csi, n) (ipu_csi_reg[csi] + 0x008C/4 + n) +#define CSI_CPD_GBS(csi, n) (ipu_csi_reg[csi] + 0x00AC/4 + n) +#define CSI_CPD_BC(csi, n) (ipu_csi_reg[csi] + 0x00BC/4 + n) +#define CSI_CPD_BS(csi, n) (ipu_csi_reg[csi] + 0x00DC/4 + n) +#define CSI_CPD_OFFSET1(csi) (ipu_csi_reg[csi] + 0x00EC/4) +#define CSI_CPD_OFFSET2(csi) (ipu_csi_reg[csi] + 0x00F0/4) + +/*SMFC Registers */ +#define SMFC_MAP (ipu_smfc_reg) +#define SMFC_WMC (ipu_smfc_reg + 0x0004/4) +#define SMFC_BS (ipu_smfc_reg + 0x0008/4) + +/* Image Converter Registers */ +#define IC_CONF (ipu_ic_reg) +#define IC_PRP_ENC_RSC (ipu_ic_reg + 0x0004/4) +#define IC_PRP_VF_RSC (ipu_ic_reg + 0x0008/4) +#define IC_PP_RSC (ipu_ic_reg + 0x000C/4) +#define IC_CMBP_1 (ipu_ic_reg + 0x0010/4) +#define IC_CMBP_2 (ipu_ic_reg + 0x0014/4) +#define IC_IDMAC_1 (ipu_ic_reg + 0x0018/4) +#define IC_IDMAC_2 (ipu_ic_reg + 0x001C/4) +#define IC_IDMAC_3 (ipu_ic_reg + 0x0020/4) +#define IC_IDMAC_4 (ipu_ic_reg + 0x0024/4) + +#define IDMAC_CONF (ipu_idmac_reg + 0x0000) +#define IDMAC_CHA_EN(ch) (ipu_idmac_reg + 0x0004/4 + (ch/32)) +#define IDMAC_SEP_ALPHA (ipu_idmac_reg + 0x000C/4) +#define IDMAC_ALT_SEP_ALPHA (ipu_idmac_reg + 0x0010/4) +#define IDMAC_CHA_PRI(ch) (ipu_idmac_reg + 0x0014/4 + (ch/32)) +#define IDMAC_WM_EN(ch) (ipu_idmac_reg + 0x001C/4 + (ch/32)) +#define IDMAC_CH_LOCK_EN_1 ({g_ipu_hw_rev == 2 ? \ + (ipu_idmac_reg + 0x0024/4) : 0; }) +#define IDMAC_CH_LOCK_EN_2 ({g_ipu_hw_rev == 2 ? \ + (ipu_idmac_reg + 0x0028/4) : \ + (ipu_idmac_reg + 0x0024/4); }) +#define IDMAC_SUB_ADDR_0 ({g_ipu_hw_rev == 2 ? \ + (ipu_idmac_reg + 0x002C/4) : \ + (ipu_idmac_reg + 0x0028/4); }) +#define IDMAC_SUB_ADDR_1 ({g_ipu_hw_rev == 2 ? \ + (ipu_idmac_reg + 0x0030/4) : \ + (ipu_idmac_reg + 0x002C/4); }) +#define IDMAC_SUB_ADDR_2 ({g_ipu_hw_rev == 2 ? \ + (ipu_idmac_reg + 0x0034/4) : \ + (ipu_idmac_reg + 0x0030/4); }) +#define IDMAC_BAND_EN(ch) ({g_ipu_hw_rev == 2 ? \ + (ipu_idmac_reg + 0x0040/4 + (ch/32)) : \ + (ipu_idmac_reg + 0x0034/4 + (ch/32)); }) +#define IDMAC_CHA_BUSY(ch) ({g_ipu_hw_rev == 2 ? \ + (ipu_idmac_reg + 0x0100/4 + (ch/32)) : \ + (ipu_idmac_reg + 0x0040/4 + (ch/32)); }) + +#define DI_GENERAL(di) (ipu_di_reg[di]) +#define DI_BS_CLKGEN0(di) (ipu_di_reg[di] + 0x0004/4) +#define DI_BS_CLKGEN1(di) (ipu_di_reg[di] + 0x0008/4) + +#define DI_SW_GEN0(di, gen) (ipu_di_reg[di] + 0x000C/4 + (gen - 1)) +#define DI_SW_GEN1(di, gen) (ipu_di_reg[di] + 0x0030/4 + (gen - 1)) +#define DI_STP_REP(di, gen) (ipu_di_reg[di] + 0x0148/4 + (gen - 1)/2) +#define DI_SYNC_AS_GEN(di) (ipu_di_reg[di] + 0x0054/4) +#define DI_DW_GEN(di, gen) (ipu_di_reg[di] + 0x0058/4 + gen) +#define DI_DW_SET(di, gen, set) (ipu_di_reg[di] + 0x0088/4 + gen + 0xC*set) +#define DI_SER_CONF(di) (ipu_di_reg[di] + 0x015C/4) +#define DI_SSC(di) (ipu_di_reg[di] + 0x0160/4) +#define DI_POL(di) (ipu_di_reg[di] + 0x0164/4) +#define DI_AW0(di) (ipu_di_reg[di] + 0x0168/4) +#define DI_AW1(di) (ipu_di_reg[di] + 0x016C/4) +#define DI_SCR_CONF(di) (ipu_di_reg[di] + 0x0170/4) +#define DI_STAT(di) (ipu_di_reg[di] + 0x0174/4) + +#define DMFC_RD_CHAN (ipu_dmfc_reg) +#define DMFC_WR_CHAN (ipu_dmfc_reg + 0x0004/4) +#define DMFC_WR_CHAN_DEF (ipu_dmfc_reg + 0x0008/4) +#define DMFC_DP_CHAN (ipu_dmfc_reg + 0x000C/4) +#define DMFC_DP_CHAN_DEF (ipu_dmfc_reg + 0x0010/4) +#define DMFC_GENERAL1 (ipu_dmfc_reg + 0x0014/4) +#define DMFC_GENERAL2 (ipu_dmfc_reg + 0x0018/4) +#define DMFC_IC_CTRL (ipu_dmfc_reg + 0x001C/4) + +#define DC_MAP_CONF_PTR(n) (ipu_dc_reg + 0x0108/4 + n/2) +#define DC_MAP_CONF_VAL(n) (ipu_dc_reg + 0x0144/4 + n/2) + +#define _RL_CH_2_OFFSET(ch) ((ch == 0) ? 8 : ( \ + (ch == 1) ? 0x24 : ( \ + (ch == 2) ? 0x40 : ( \ + (ch == 5) ? 0x64 : ( \ + (ch == 6) ? 0x80 : ( \ + (ch == 8) ? 0x9C : ( \ + (ch == 9) ? 0xBC : (-1)))))))) +#define DC_RL_CH(ch, evt) (ipu_dc_reg + _RL_CH_2_OFFSET(ch)/4 + evt/2) + +#define DC_EVT_NF 0 +#define DC_EVT_NL 1 +#define DC_EVT_EOF 2 +#define DC_EVT_NFIELD 3 +#define DC_EVT_EOL 4 +#define DC_EVT_EOFIELD 5 +#define DC_EVT_NEW_ADDR 6 +#define DC_EVT_NEW_CHAN 7 +#define DC_EVT_NEW_DATA 8 + +#define DC_EVT_NEW_ADDR_W_0 0 +#define DC_EVT_NEW_ADDR_W_1 1 +#define DC_EVT_NEW_CHAN_W_0 2 +#define DC_EVT_NEW_CHAN_W_1 3 +#define DC_EVT_NEW_DATA_W_0 4 +#define DC_EVT_NEW_DATA_W_1 5 +#define DC_EVT_NEW_ADDR_R_0 6 +#define DC_EVT_NEW_ADDR_R_1 7 +#define DC_EVT_NEW_CHAN_R_0 8 +#define DC_EVT_NEW_CHAN_R_1 9 +#define DC_EVT_NEW_DATA_R_0 10 +#define DC_EVT_NEW_DATA_R_1 11 + +#define dc_ch_offset(ch) \ +({ \ + const u8 _offset[] = { \ + 0, 0x1C, 0x38, 0x54, 0x58, 0x5C, 0x78, 0, 0x94, 0xB4}; \ + _offset[ch]; \ +}) +#define DC_WR_CH_CONF(ch) (ipu_dc_reg + dc_ch_offset(ch)/4) +#define DC_WR_CH_ADDR(ch) (ipu_dc_reg + dc_ch_offset(ch)/4 + 4/4) + +#define DC_WR_CH_CONF_1 (ipu_dc_reg + 0x001C/4) +#define DC_WR_CH_ADDR_1 (ipu_dc_reg + 0x0020/4) +#define DC_WR_CH_CONF_5 (ipu_dc_reg + 0x005C/4) +#define DC_WR_CH_ADDR_5 (ipu_dc_reg + 0x0060/4) +#define DC_GEN (ipu_dc_reg + 0x00D4/4) +#define DC_DISP_CONF1(disp) (ipu_dc_reg + 0x00D8/4 + disp) +#define DC_DISP_CONF2(disp) (ipu_dc_reg + 0x00E8/4 + disp) +#define DC_STAT (ipu_dc_reg + 0x01C8/4) +#define DC_UGDE_0(evt) (ipu_dc_reg + 0x0174/4 + evt*4) +#define DC_UGDE_1(evt) (ipu_dc_reg + 0x0178/4 + evt*4) +#define DC_UGDE_2(evt) (ipu_dc_reg + 0x017C/4 + evt*4) +#define DC_UGDE_3(evt) (ipu_dc_reg + 0x0180/4 + evt*4) + +#define DP_SYNC 0 +#define DP_ASYNC0 0x60 +#define DP_ASYNC1 0xBC +#define DP_COM_CONF(flow) (ipu_dp_reg + flow/4) +#define DP_GRAPH_WIND_CTRL(flow) (ipu_dp_reg + 0x0004/4 + flow/4) +#define DP_FG_POS(flow) (ipu_dp_reg + 0x0008/4 + flow/4) +#define DP_CSC_A_0(flow) (ipu_dp_reg + 0x0044/4 + flow/4) +#define DP_CSC_A_1(flow) (ipu_dp_reg + 0x0048/4 + flow/4) +#define DP_CSC_A_2(flow) (ipu_dp_reg + 0x004C/4 + flow/4) +#define DP_CSC_A_3(flow) (ipu_dp_reg + 0x0050/4 + flow/4) +#define DP_CSC_0(flow) (ipu_dp_reg + 0x0054/4 + flow/4) +#define DP_CSC_1(flow) (ipu_dp_reg + 0x0058/4 + flow/4) + +enum { + IPU_CONF_CSI0_EN = 0x00000001, + IPU_CONF_CSI1_EN = 0x00000002, + IPU_CONF_IC_EN = 0x00000004, + IPU_CONF_ROT_EN = 0x00000008, + IPU_CONF_ISP_EN = 0x00000010, + IPU_CONF_DP_EN = 0x00000020, + IPU_CONF_DI0_EN = 0x00000040, + IPU_CONF_DI1_EN = 0x00000080, + IPU_CONF_DMFC_EN = 0x00000400, + IPU_CONF_SMFC_EN = 0x00000100, + IPU_CONF_DC_EN = 0x00000200, + IPU_CONF_IDMAC_DIS = 0x00400000, + IPU_CONF_IC_DMFC_SEL = 0x02000000, + IPU_CONF_IC_DMFC_SYNC = 0x04000000, + IPU_CONF_VDI_DMFC_SYNC = 0x08000000, + IPU_CONF_CSI0_DATA_SOURCE = 0x10000000, + IPU_CONF_CSI0_DATA_SOURCE_OFFSET = 28, + IPU_CONF_CSI1_DATA_SOURCE = 0x20000000, + IPU_CONF_IC_INPUT = 0x40000000, + IPU_CONF_CSI_SEL = 0x80000000, + + DI0_COUNTER_RELEASE = 0x01000000, + DI1_COUNTER_RELEASE = 0x02000000, + + FS_PRPVF_ROT_SRC_SEL_MASK = 0x00000F00, + FS_PRPVF_ROT_SRC_SEL_OFFSET = 8, + FS_PRPENC_ROT_SRC_SEL_MASK = 0x0000000F, + FS_PRPENC_ROT_SRC_SEL_OFFSET = 0, + FS_PP_ROT_SRC_SEL_MASK = 0x000F0000, + FS_PP_ROT_SRC_SEL_OFFSET = 16, + FS_PP_SRC_SEL_MASK = 0x0000F000, + FS_PP_SRC_SEL_OFFSET = 12, + FS_PRP_SRC_SEL_MASK = 0x0F000000, + FS_PRP_SRC_SEL_OFFSET = 24, + FS_VF_IN_VALID = 0x80000000, + FS_ENC_IN_VALID = 0x40000000, + + FS_PRPENC_DEST_SEL_MASK = 0x0000000F, + FS_PRPENC_DEST_SEL_OFFSET = 0, + FS_PRPVF_DEST_SEL_MASK = 0x000000F0, + FS_PRPVF_DEST_SEL_OFFSET = 4, + FS_PRPVF_ROT_DEST_SEL_MASK = 0x00000F00, + FS_PRPVF_ROT_DEST_SEL_OFFSET = 8, + FS_PP_DEST_SEL_MASK = 0x0000F000, + FS_PP_DEST_SEL_OFFSET = 12, + FS_PP_ROT_DEST_SEL_MASK = 0x000F0000, + FS_PP_ROT_DEST_SEL_OFFSET = 16, + FS_PRPENC_ROT_DEST_SEL_MASK = 0x00F00000, + FS_PRPENC_ROT_DEST_SEL_OFFSET = 20, + + FS_SMFC0_DEST_SEL_MASK = 0x0000000F, + FS_SMFC0_DEST_SEL_OFFSET = 0, + FS_SMFC1_DEST_SEL_MASK = 0x00000070, + FS_SMFC1_DEST_SEL_OFFSET = 4, + FS_SMFC2_DEST_SEL_MASK = 0x00000780, + FS_SMFC2_DEST_SEL_OFFSET = 7, + FS_SMFC3_DEST_SEL_MASK = 0x00003800, + FS_SMFC3_DEST_SEL_OFFSET = 11, + + FS_DC1_SRC_SEL_MASK = 0x00F00000, + FS_DC1_SRC_SEL_OFFSET = 20, + FS_DC2_SRC_SEL_MASK = 0x000F0000, + FS_DC2_SRC_SEL_OFFSET = 16, + FS_DP_SYNC0_SRC_SEL_MASK = 0x0000000F, + FS_DP_SYNC0_SRC_SEL_OFFSET = 0, + FS_DP_SYNC1_SRC_SEL_MASK = 0x000000F0, + FS_DP_SYNC1_SRC_SEL_OFFSET = 4, + FS_DP_ASYNC0_SRC_SEL_MASK = 0x00000F00, + FS_DP_ASYNC0_SRC_SEL_OFFSET = 8, + FS_DP_ASYNC1_SRC_SEL_MASK = 0x0000F000, + FS_DP_ASYNC1_SRC_SEL_OFFSET = 12, + + FS_AUTO_REF_PER_MASK = 0, + FS_AUTO_REF_PER_OFFSET = 16, + + TSTAT_VF_MASK = 0x0000000C, + TSTAT_VF_OFFSET = 2, + TSTAT_VF_ROT_MASK = 0x00000300, + TSTAT_VF_ROT_OFFSET = 8, + TSTAT_ENC_MASK = 0x00000003, + TSTAT_ENC_OFFSET = 0, + TSTAT_ENC_ROT_MASK = 0x000000C0, + TSTAT_ENC_ROT_OFFSET = 6, + TSTAT_PP_MASK = 0x00000030, + TSTAT_PP_OFFSET = 4, + TSTAT_PP_ROT_MASK = 0x00000C00, + TSTAT_PP_ROT_OFFSET = 10, + + TASK_STAT_IDLE = 0, + TASK_STAT_ACTIVE = 1, + TASK_STAT_WAIT4READY = 2, + + /* Image Converter Register bits */ + IC_CONF_PRPENC_EN = 0x00000001, + IC_CONF_PRPENC_CSC1 = 0x00000002, + IC_CONF_PRPENC_ROT_EN = 0x00000004, + IC_CONF_PRPVF_EN = 0x00000100, + IC_CONF_PRPVF_CSC1 = 0x00000200, + IC_CONF_PRPVF_CSC2 = 0x00000400, + IC_CONF_PRPVF_CMB = 0x00000800, + IC_CONF_PRPVF_ROT_EN = 0x00001000, + IC_CONF_PP_EN = 0x00010000, + IC_CONF_PP_CSC1 = 0x00020000, + IC_CONF_PP_CSC2 = 0x00040000, + IC_CONF_PP_CMB = 0x00080000, + IC_CONF_PP_ROT_EN = 0x00100000, + IC_CONF_IC_GLB_LOC_A = 0x10000000, + IC_CONF_KEY_COLOR_EN = 0x20000000, + IC_CONF_RWS_EN = 0x40000000, + IC_CONF_CSI_MEM_WR_EN = 0x80000000, + + IC_IDMAC_1_CB0_BURST_16 = 0x00000001, + IC_IDMAC_1_CB1_BURST_16 = 0x00000002, + IC_IDMAC_1_CB2_BURST_16 = 0x00000004, + IC_IDMAC_1_CB3_BURST_16 = 0x00000008, + IC_IDMAC_1_CB4_BURST_16 = 0x00000010, + IC_IDMAC_1_CB5_BURST_16 = 0x00000020, + IC_IDMAC_1_CB6_BURST_16 = 0x00000040, + IC_IDMAC_1_CB7_BURST_16 = 0x00000080, + IC_IDMAC_1_PRPENC_ROT_MASK = 0x00003800, + IC_IDMAC_1_PRPENC_ROT_OFFSET = 11, + IC_IDMAC_1_PRPVF_ROT_MASK = 0x0001C000, + IC_IDMAC_1_PRPVF_ROT_OFFSET = 14, + IC_IDMAC_1_PP_ROT_MASK = 0x000E0000, + IC_IDMAC_1_PP_ROT_OFFSET = 17, + IC_IDMAC_1_PP_FLIP_RS = 0x00400000, + IC_IDMAC_1_PRPVF_FLIP_RS = 0x00200000, + IC_IDMAC_1_PRPENC_FLIP_RS = 0x00100000, + + IC_IDMAC_2_PRPENC_HEIGHT_MASK = 0x000003FF, + IC_IDMAC_2_PRPENC_HEIGHT_OFFSET = 0, + IC_IDMAC_2_PRPVF_HEIGHT_MASK = 0x000FFC00, + IC_IDMAC_2_PRPVF_HEIGHT_OFFSET = 10, + IC_IDMAC_2_PP_HEIGHT_MASK = 0x3FF00000, + IC_IDMAC_2_PP_HEIGHT_OFFSET = 20, + + IC_IDMAC_3_PRPENC_WIDTH_MASK = 0x000003FF, + IC_IDMAC_3_PRPENC_WIDTH_OFFSET = 0, + IC_IDMAC_3_PRPVF_WIDTH_MASK = 0x000FFC00, + IC_IDMAC_3_PRPVF_WIDTH_OFFSET = 10, + IC_IDMAC_3_PP_WIDTH_MASK = 0x3FF00000, + IC_IDMAC_3_PP_WIDTH_OFFSET = 20, + + CSI_SENS_CONF_DATA_FMT_SHIFT = 8, + CSI_SENS_CONF_DATA_FMT_MASK = 0x00000700, + CSI_SENS_CONF_DATA_FMT_RGB_YUV444 = 0L, + CSI_SENS_CONF_DATA_FMT_YUV422_YUYV = 1L, + CSI_SENS_CONF_DATA_FMT_YUV422_UYVY = 2L, + CSI_SENS_CONF_DATA_FMT_BAYER = 3L, + CSI_SENS_CONF_DATA_FMT_RGB565 = 4L, + CSI_SENS_CONF_DATA_FMT_RGB555 = 5L, + CSI_SENS_CONF_DATA_FMT_RGB444 = 6L, + CSI_SENS_CONF_DATA_FMT_JPEG = 7L, + + CSI_SENS_CONF_VSYNC_POL_SHIFT = 0, + CSI_SENS_CONF_HSYNC_POL_SHIFT = 1, + CSI_SENS_CONF_DATA_POL_SHIFT = 2, + CSI_SENS_CONF_PIX_CLK_POL_SHIFT = 3, + CSI_SENS_CONF_SENS_PRTCL_SHIFT = 4, + CSI_SENS_CONF_PACK_TIGHT_SHIFT = 7, + CSI_SENS_CONF_DATA_WIDTH_SHIFT = 11, + CSI_SENS_CONF_EXT_VSYNC_SHIFT = 15, + CSI_SENS_CONF_DIVRATIO_SHIFT = 16, + + CSI_SENS_CONF_DIVRATIO_MASK = 0x00FF0000L, + CSI_SENS_CONF_DATA_DEST_SHIFT = 24, + CSI_SENS_CONF_DATA_DEST_MASK = 0x07000000L, + CSI_SENS_CONF_JPEG8_EN_SHIFT = 27, + CSI_SENS_CONF_JPEG_EN_SHIFT = 28, + CSI_SENS_CONF_FORCE_EOF_SHIFT = 29, + CSI_SENS_CONF_DATA_EN_POL_SHIFT = 31, + + CSI_DATA_DEST_ISP = 1L, + CSI_DATA_DEST_IC = 2L, + CSI_DATA_DEST_IDMAC = 4L, + + CSI_CCIR_ERR_DET_EN = 0x01000000L, + CSI_HORI_DOWNSIZE_EN = 0x80000000L, + CSI_VERT_DOWNSIZE_EN = 0x40000000L, + CSI_TEST_GEN_MODE_EN = 0x01000000L, + + CSI_HSC_MASK = 0x1FFF0000, + CSI_HSC_SHIFT = 16, + CSI_VSC_MASK = 0x00000FFF, + CSI_VSC_SHIFT = 0, + + CSI_TEST_GEN_R_MASK = 0x000000FFL, + CSI_TEST_GEN_R_SHIFT = 0, + CSI_TEST_GEN_G_MASK = 0x0000FF00L, + CSI_TEST_GEN_G_SHIFT = 8, + CSI_TEST_GEN_B_MASK = 0x00FF0000L, + CSI_TEST_GEN_B_SHIFT = 16, + + CSI_MIPI_DI0_MASK = 0x000000FFL, + CSI_MIPI_DI0_SHIFT = 0, + CSI_MIPI_DI1_MASK = 0x0000FF00L, + CSI_MIPI_DI1_SHIFT = 8, + CSI_MIPI_DI2_MASK = 0x00FF0000L, + CSI_MIPI_DI2_SHIFT = 16, + CSI_MIPI_DI3_MASK = 0xFF000000L, + CSI_MIPI_DI3_SHIFT = 24, + + CSI_MAX_RATIO_SKIP_ISP_MASK = 0x00070000L, + CSI_MAX_RATIO_SKIP_ISP_SHIFT = 16, + CSI_SKIP_ISP_MASK = 0x00F80000L, + CSI_SKIP_ISP_SHIFT = 19, + CSI_MAX_RATIO_SKIP_SMFC_MASK = 0x00000007L, + CSI_MAX_RATIO_SKIP_SMFC_SHIFT = 0, + CSI_SKIP_SMFC_MASK = 0x000000F8L, + CSI_SKIP_SMFC_SHIFT = 3, + CSI_ID_2_SKIP_MASK = 0x00000300L, + CSI_ID_2_SKIP_SHIFT = 8, + + CSI_COLOR_FIRST_ROW_MASK = 0x00000002L, + CSI_COLOR_FIRST_COMP_MASK = 0x00000001L, + + SMFC_MAP_CH0_MASK = 0x00000007L, + SMFC_MAP_CH0_SHIFT = 0, + SMFC_MAP_CH1_MASK = 0x00000038L, + SMFC_MAP_CH1_SHIFT = 3, + SMFC_MAP_CH2_MASK = 0x000001C0L, + SMFC_MAP_CH2_SHIFT = 6, + SMFC_MAP_CH3_MASK = 0x00000E00L, + SMFC_MAP_CH3_SHIFT = 9, + + SMFC_WM0_SET_MASK = 0x00000007L, + SMFC_WM0_SET_SHIFT = 0, + SMFC_WM1_SET_MASK = 0x000001C0L, + SMFC_WM1_SET_SHIFT = 6, + SMFC_WM2_SET_MASK = 0x00070000L, + SMFC_WM2_SET_SHIFT = 16, + SMFC_WM3_SET_MASK = 0x01C00000L, + SMFC_WM3_SET_SHIFT = 22, + + SMFC_WM0_CLR_MASK = 0x00000038L, + SMFC_WM0_CLR_SHIFT = 3, + SMFC_WM1_CLR_MASK = 0x00000E00L, + SMFC_WM1_CLR_SHIFT = 9, + SMFC_WM2_CLR_MASK = 0x00380000L, + SMFC_WM2_CLR_SHIFT = 19, + SMFC_WM3_CLR_MASK = 0x0E000000L, + SMFC_WM3_CLR_SHIFT = 25, + + SMFC_BS0_MASK = 0x0000000FL, + SMFC_BS0_SHIFT = 0, + SMFC_BS1_MASK = 0x000000F0L, + SMFC_BS1_SHIFT = 4, + SMFC_BS2_MASK = 0x00000F00L, + SMFC_BS2_SHIFT = 8, + SMFC_BS3_MASK = 0x0000F000L, + SMFC_BS3_SHIFT = 12, + + PF_CONF_TYPE_MASK = 0x00000007, + PF_CONF_TYPE_SHIFT = 0, + PF_CONF_PAUSE_EN = 0x00000010, + PF_CONF_RESET = 0x00008000, + PF_CONF_PAUSE_ROW_MASK = 0x00FF0000, + PF_CONF_PAUSE_ROW_SHIFT = 16, + + DI_DW_GEN_ACCESS_SIZE_OFFSET = 24, + DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16, + + DI_GEN_DI_CLK_EXT = 0x100000, + DI_GEN_POLARITY_1 = 0x00000001, + DI_GEN_POLARITY_2 = 0x00000002, + DI_GEN_POLARITY_3 = 0x00000004, + DI_GEN_POLARITY_4 = 0x00000008, + DI_GEN_POLARITY_5 = 0x00000010, + DI_GEN_POLARITY_6 = 0x00000020, + DI_GEN_POLARITY_7 = 0x00000040, + DI_GEN_POLARITY_8 = 0x00000080, + + DI_POL_DRDY_DATA_POLARITY = 0x00000080, + DI_POL_DRDY_POLARITY_15 = 0x00000010, + + DI_VSYNC_SEL_OFFSET = 13, + + DC_WR_CH_CONF_FIELD_MODE = 0x00000200, + DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5, + DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0, + DC_WR_CH_CONF_PROG_DI_ID = 0x00000004, + DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3, + DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018, + + DC_UGDE_0_ODD_EN = 0x02000000, + DC_UGDE_0_ID_CODED_MASK = 0x00000007, + DC_UGDE_0_ID_CODED_OFFSET = 0, + DC_UGDE_0_EV_PRIORITY_MASK = 0x00000078, + DC_UGDE_0_EV_PRIORITY_OFFSET = 3, + + DP_COM_CONF_FG_EN = 0x00000001, + DP_COM_CONF_GWSEL = 0x00000002, + DP_COM_CONF_GWAM = 0x00000004, + DP_COM_CONF_GWCKE = 0x00000008, + DP_COM_CONF_CSC_DEF_MASK = 0x00000300, + DP_COM_CONF_CSC_DEF_OFFSET = 8, + DP_COM_CONF_CSC_DEF_FG = 0x00000300, + DP_COM_CONF_CSC_DEF_BG = 0x00000200, + DP_COM_CONF_CSC_DEF_BOTH = 0x00000100, + + DI_SER_CONF_LLA_SER_ACCESS = 0x00000020, + DI_SER_CONF_SERIAL_CLK_POL = 0x00000010, + DI_SER_CONF_SERIAL_DATA_POL = 0x00000008, + DI_SER_CONF_SERIAL_RS_POL = 0x00000004, + DI_SER_CONF_SERIAL_CS_POL = 0x00000002, + DI_SER_CONF_WAIT4SERIAL = 0x00000001, +}; + +enum di_pins { + DI_PIN11 = 0, + DI_PIN12 = 1, + DI_PIN13 = 2, + DI_PIN14 = 3, + DI_PIN15 = 4, + DI_PIN16 = 5, + DI_PIN17 = 6, + DI_PIN_CS = 7, + + DI_PIN_SER_CLK = 0, + DI_PIN_SER_RS = 1, +}; + +enum di_sync_wave { + DI_SYNC_NONE = -1, + DI_SYNC_CLK = 0, + DI_SYNC_INT_HSYNC = 1, + DI_SYNC_HSYNC = 2, + DI_SYNC_VSYNC = 3, + DI_SYNC_DE = 5, +}; + +/* DC template opcodes */ +#define WROD(lf) (0x18 | (lf << 1)) + +#endif diff -urN linux-2.6.26/drivers/mxc/mcu_pmic/Kconfig linux-2.6.26-lab126/drivers/mxc/mcu_pmic/Kconfig --- linux-2.6.26/drivers/mxc/mcu_pmic/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/mcu_pmic/Kconfig 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,19 @@ +# +# PMIC Modules configuration +# + +config MXC_PMIC_MC9SDZ60 + tristate "MC9sDZ60 PMIC" + depends on ARCH_MXC && I2C + ---help--- + This is the MXC MC9sDZ60(MCU) PMIC support. + +config MXC_MC9SDZ60_RTC + tristate "MC9SDZ60 Real Time Clock (RTC) support" + depends on MXC_PMIC_MC9SDZ60 + ---help--- + This is the MC9SDZ60 RTC module driver. This module provides kernel API + for RTC part of MC9SDZ60. + If you want MC9SDZ60 RTC support, you should say Y here + + diff -urN linux-2.6.26/drivers/mxc/mcu_pmic/Makefile linux-2.6.26-lab126/drivers/mxc/mcu_pmic/Makefile --- linux-2.6.26/drivers/mxc/mcu_pmic/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/mcu_pmic/Makefile 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,8 @@ +# +# Makefile for the mc9sdz60 pmic drivers. +# + +obj-$(CONFIG_MXC_PMIC_MC9SDZ60) += pmic_mc9sdz60_mod.o +pmic_mc9sdz60_mod-objs := mcu_pmic_core.o max8660.o mc9sdz60.o mcu_pmic_gpio.o + + diff -urN linux-2.6.26/drivers/mxc/mcu_pmic/max8660.c linux-2.6.26-lab126/drivers/mxc/mcu_pmic/max8660.c --- linux-2.6.26/drivers/mxc/mcu_pmic/max8660.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/mcu_pmic/max8660.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,154 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file max8660.c + * @brief Driver for max8660 + * + * @ingroup pmic + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "max8660.h" + +/* I2C bus id and device address of mcu */ +#define I2C1_BUS 0 +#define MAX8660_I2C_ADDR 0x68 + +static struct i2c_client *max8660_i2c_client; + + /* reg names for max8660 + REG_MAX8660_OUTPUT_ENABLE_1, + REG_MAX8660_OUTPUT_ENABLE_2, + REG_MAX8660_VOLT__CHANGE_1, + REG_MAX8660_V3_TARGET_VOLT_1, + REG_MAX8660_V3_TARGET_VOLT_2, + REG_MAX8660_V4_TARGET_VOLT_1, + REG_MAX8660_V4_TARGET_VOLT_2, + REG_MAX8660_V5_TARGET_VOLT_1, + REG_MAX8660_V5_TARGET_VOLT_2, + REG_MAX8660_V6V7_TARGET_VOLT, + REG_MAX8660_FORCE_PWM + */ + + /* save down the reg values for the device is write only */ +static u8 max8660_reg_value_table[] = + { 0x0, 0x0, 0x0, 0x17, 0x17, 0x1F, 0x1F, 0x04, 0x04, 0x0, 0x0 +}; +static int max8660_dev_present; + +int is_max8660_present(void) +{ + return max8660_dev_present; +} + +int max8660_get_buffered_reg_val(int reg_name, u8 *value) +{ + if (!max8660_dev_present) + return -1; + /* outof range */ + if (reg_name < REG_MAX8660_OUTPUT_ENABLE_1 + || reg_name > REG_MAX8660_FORCE_PWM) + return -1; + *value = + max8660_reg_value_table[reg_name - REG_MAX8660_OUTPUT_ENABLE_1]; + return 0; +} +int max8660_save_buffered_reg_val(int reg_name, u8 value) +{ + + /* outof range */ + if (reg_name < REG_MAX8660_OUTPUT_ENABLE_1 + || reg_name > REG_MAX8660_FORCE_PWM) + return -1; + max8660_reg_value_table[reg_name - REG_MAX8660_OUTPUT_ENABLE_1] = value; + return 0; +} + +int max8660_write_reg(u8 reg, u8 value) +{ + if (max8660_dev_present && (i2c_smbus_write_byte_data( + max8660_i2c_client, reg, value) >= 0)) + return 0; + return -1; +} + +/*! + * max8660 I2C attach function + * + * @param adapter struct i2c_client * + * @return 0 for max8660 successfully detected + */ +static int max8660_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int retval; + max8660_i2c_client = client; + retval = i2c_smbus_write_byte_data(max8660_i2c_client, + MAX8660_OUTPUT_ENABLE_1, 0); + if (retval == 0) { + max8660_dev_present = 1; + pr_info("max8660 probed !\n"); + } else { + max8660_dev_present = 0; + pr_info("max8660 not detected!\n"); + } + return retval; +} + +/*! + * max8660 I2C detach function + * + * @param client struct i2c_client * + * @return 0 + */ +static int max8660_remove(struct i2c_client *client) +{ + return 0; +} + +static const struct i2c_device_id max8660_id[] = { + { "max8660", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, max8660_id); + +static struct i2c_driver max8660_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "max8660",}, + .probe = max8660_probe, + .remove = max8660_remove, + .id_table = max8660_id, +}; + +/* called by pmic core when init*/ +int max8660_init(void) +{ + int err; + err = i2c_add_driver(&max8660_i2c_driver); + return err; +} +void max8660_exit(void) +{ + i2c_del_driver(&max8660_i2c_driver); +} diff -urN linux-2.6.26/drivers/mxc/mcu_pmic/max8660.h linux-2.6.26-lab126/drivers/mxc/mcu_pmic/max8660.h --- linux-2.6.26/drivers/mxc/mcu_pmic/max8660.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/mcu_pmic/max8660.h 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,49 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file max8660.h + * @brief Driver for max8660 + * + * @ingroup pmic + */ +#ifndef _MAX8660_H_ +#define _MAX8660_H_ + +#ifdef __KERNEL__ + +#define MAX8660_OUTPUT_ENABLE_1 0x10 +#define MAX8660_OUTPUT_ENABLE_2 0x12 +#define MAX8660_VOLT_CHANGE_CONTROL 0x20 +#define MAX8660_V3_TARGET_VOLT_1 0x23 +#define MAX8660_V3_TARGET_VOLT_2 0x24 +#define MAX8660_V4_TARGET_VOLT_1 0x29 +#define MAX8660_V4_TARGET_VOLT_2 0x2A +#define MAX8660_V5_TARGET_VOLT_1 0x32 +#define MAX8660_V5_TARGET_VOLT_2 0x33 +#define MAX8660_V6V7_TARGET_VOLT 0x39 +#define MAX8660_FORCE_PWM 0x80 + +int is_max8660_present(void); +int max8660_write_reg(u8 reg, u8 value); +int max8660_save_buffered_reg_val(int reg_name, u8 value); +int max8660_get_buffered_reg_val(int reg_name, u8 *value); +int max8660_init(void); +void max8660_exit(void); + +extern int reg_max8660_probe(void); +extern int reg_max8660_remove(void); + +#endif /* __KERNEL__ */ + +#endif /* _MAX8660_H_ */ diff -urN linux-2.6.26/drivers/mxc/mcu_pmic/mc9sdz60.c linux-2.6.26-lab126/drivers/mxc/mcu_pmic/mc9sdz60.c --- linux-2.6.26/drivers/mxc/mcu_pmic/mc9sdz60.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/mcu_pmic/mc9sdz60.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,102 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + /*! + * @file mc9sdz60.c + * @brief Driver for MC9sdz60 + * + * @ingroup pmic + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "mc9sdz60.h" + +/* I2C bus id and device address of mcu */ +#define I2C1_BUS 0 +#define MC9SDZ60_I2C_ADDR 0xD2 /* 7bits I2C address */ +static struct i2c_client *mc9sdz60_i2c_client; + +int mc9sdz60_read_reg(u8 reg, u8 *value) +{ + *value = (u8) i2c_smbus_read_byte_data(mc9sdz60_i2c_client, reg); + return 0; +} + +int mc9sdz60_write_reg(u8 reg, u8 value) +{ + if (i2c_smbus_write_byte_data(mc9sdz60_i2c_client, reg, value) < 0) + return -1; + return 0; +} + +/*! + * mc9sdz60 I2C attach function + * + * @param adapter struct i2c_adapter * + * @return 0 + */ +static int mc9sdz60_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + mc9sdz60_i2c_client = client; + return 0; +} + +/*! + * mc9sdz60 I2C detach function + * + * @param client struct i2c_client * + * @return 0 + */ +static int mc9sdz60_remove(struct i2c_client *client) +{ + return 0; +} + +static const struct i2c_device_id mc9sdz60_id[] = { + { "mc9sdz60", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, mc9sdz60_id); + +static struct i2c_driver mc9sdz60_i2c_driver = { + .driver = {.owner = THIS_MODULE, + .name = "mc9sdz60", + }, + .probe = mc9sdz60_probe, + .remove = mc9sdz60_remove, + .id_table = mc9sdz60_id, +}; + +#define SET_BIT_IN_BYTE(byte, pos) (byte |= (0x01 << pos)) +#define CLEAR_BIT_IN_BYTE(byte, pos) (byte &= ~(0x01 << pos)) + +int mc9sdz60_init(void) +{ + int err; + err = i2c_add_driver(&mc9sdz60_i2c_driver); + return err; +} +void mc9sdz60_exit(void) +{ + i2c_del_driver(&mc9sdz60_i2c_driver); +} diff -urN linux-2.6.26/drivers/mxc/mcu_pmic/mc9sdz60.h linux-2.6.26-lab126/drivers/mxc/mcu_pmic/mc9sdz60.h --- linux-2.6.26/drivers/mxc/mcu_pmic/mc9sdz60.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/mcu_pmic/mc9sdz60.h 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,74 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc9sdz60.h + * @brief Driver for mc9sdz60 + * + * @ingroup pmic + */ +#ifndef _MC9SDZ60_H_ +#define _MC9SDZ60_H_ + +#define MCU_VERSION 0x00 +/*#define Reserved 0x01*/ +#define MCU_SECS 0x02 +#define MCU_MINS 0x03 +#define MCU_HRS 0x04 +#define MCU_DAY 0x05 +#define MCU_DATE 0x06 +#define MCU_MONTH 0x07 +#define MCU_YEAR 0x08 + +#define MCU_ALARM_SECS 0x09 +#define MCU_ALARM_MINS 0x0A +#define MCU_ALARM_HRS 0x0B +/* #define Reserved 0x0C*/ +/* #define Reserved 0x0D*/ +#define MCU_TS_CONTROL 0x0E +#define MCU_X_LOW 0x0F +#define MCU_Y_LOW 0x10 +#define MCU_XY_HIGH 0x11 +#define MCU_X_LEFT_LOW 0x12 +#define MCU_X_LEFT_HIGH 0x13 +#define MCU_X_RIGHT 0x14 +#define MCU_Y_TOP_LOW 0x15 +#define MCU_Y_TOP_HIGH 0x16 +#define MCU_Y_BOTTOM 0x17 +/* #define Reserved 0x18*/ +/* #define Reserved 0x19*/ +#define MCU_RESET_1 0x1A +#define MCU_RESET_2 0x1B +#define MCU_POWER_CTL 0x1C +#define MCU_DELAY_CONFIG 0x1D +/* #define Reserved 0x1E */ +/* #define Reserved 0x1F */ +#define MCU_GPIO_1 0x20 +#define MCU_GPIO_2 0x21 +#define MCU_KPD_1 0x22 +#define MCU_KPD_2 0x23 +#define MCU_KPD_CONTROL 0x24 +#define MCU_INT_ENABLE_1 0x25 +#define MCU_INT_ENABLE_2 0x26 +#define MCU_INT_FLAG_1 0x27 +#define MCU_INT_FLAG_2 0x28 +#define MCU_DES_FLAG 0x29 +int mc9sdz60_read_reg(u8 reg, u8 *value); +int mc9sdz60_write_reg(u8 reg, u8 value); +int mc9sdz60_init(void); +void mc9sdz60_exit(void); + +extern int reg_mc9sdz60_probe(void); +extern int reg_mc9sdz60_remove(void); + +#endif /* _MC9SDZ60_H_ */ + diff -urN linux-2.6.26/drivers/mxc/mcu_pmic/mcu_pmic_core.c linux-2.6.26-lab126/drivers/mxc/mcu_pmic/mcu_pmic_core.c --- linux-2.6.26/drivers/mxc/mcu_pmic/mcu_pmic_core.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/mcu_pmic/mcu_pmic_core.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,227 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc9sdz60/mcu_pmic_core.c + * @brief This is the main file of mc9sdz60 Power Control driver. + * + * @ingroup PMIC_POWER + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mc9sdz60.h" +#include "max8660.h" + +/* bitfield macros for mcu pmic*/ +#define SET_BIT_IN_BYTE(byte, pos) (byte |= (0x01 << pos)) +#define CLEAR_BIT_IN_BYTE(byte, pos) (byte &= ~(0x01 << pos)) + + +/* map reg names (enum pmic_reg in pmic_external.h) to real addr*/ +const static u8 mcu_pmic_reg_addr_table[] = { + MCU_VERSION, + MCU_SECS, + MCU_MINS, + MCU_HRS, + MCU_DAY, + MCU_DATE, + MCU_MONTH, + MCU_YEAR, + MCU_ALARM_SECS, + MCU_ALARM_MINS, + MCU_ALARM_HRS, + MCU_TS_CONTROL, + MCU_X_LOW, + MCU_Y_LOW, + MCU_XY_HIGH, + MCU_X_LEFT_LOW, + MCU_X_LEFT_HIGH, + MCU_X_RIGHT, + MCU_Y_TOP_LOW, + MCU_Y_TOP_HIGH, + MCU_Y_BOTTOM, + MCU_RESET_1, + MCU_RESET_2, + MCU_POWER_CTL, + MCU_DELAY_CONFIG, + MCU_GPIO_1, + MCU_GPIO_2, + MCU_KPD_1, + MCU_KPD_2, + MCU_KPD_CONTROL, + MCU_INT_ENABLE_1, + MCU_INT_ENABLE_2, + MCU_INT_FLAG_1, + MCU_INT_FLAG_2, + MCU_DES_FLAG, + MAX8660_OUTPUT_ENABLE_1, + MAX8660_OUTPUT_ENABLE_2, + MAX8660_VOLT_CHANGE_CONTROL, + MAX8660_V3_TARGET_VOLT_1, + MAX8660_V3_TARGET_VOLT_2, + MAX8660_V4_TARGET_VOLT_1, + MAX8660_V4_TARGET_VOLT_2, + MAX8660_V5_TARGET_VOLT_1, + MAX8660_V5_TARGET_VOLT_2, + MAX8660_V6V7_TARGET_VOLT, + MAX8660_FORCE_PWM +}; + +static int mcu_pmic_read(int reg_num, unsigned int *reg_val) +{ + int ret; + u8 value = 0; + /* mcu ops */ + if (reg_num >= REG_MCU_VERSION && reg_num <= REG_MCU_DES_FLAG) + ret = mc9sdz60_read_reg(mcu_pmic_reg_addr_table[reg_num], + &value); + else if (reg_num >= REG_MAX8660_OUTPUT_ENABLE_1 + && reg_num <= REG_MAX8660_FORCE_PWM) + ret = max8660_get_buffered_reg_val(reg_num, &value); + else + return -1; + + if (ret < 0) + return -1; + *reg_val = value; + + return 0; +} + +static int mcu_pmic_write(int reg_num, const unsigned int reg_val) +{ + int ret; + u8 value = reg_val; + /* mcu ops */ + if (reg_num >= REG_MCU_VERSION && reg_num <= REG_MCU_DES_FLAG) { + + ret = + mc9sdz60_write_reg(mcu_pmic_reg_addr_table[reg_num], value); + if (ret < 0) + return -1; + } else if (reg_num >= REG_MAX8660_OUTPUT_ENABLE_1 + && reg_num <= REG_MAX8660_FORCE_PWM) { + ret = + max8660_write_reg(mcu_pmic_reg_addr_table[reg_num], value); + + if (ret < 0) + return -1; + + ret = max8660_save_buffered_reg_val(reg_num, value); + } else + return -1; + + return 0; +} + +int mcu_pmic_read_reg(int reg, unsigned int *reg_value, + unsigned int reg_mask) +{ + int ret = 0; + unsigned int temp = 0; + + ret = mcu_pmic_read(reg, &temp); + if (ret != 0) + return -1; + *reg_value = (temp & reg_mask); + + pr_debug("Read REG[ %d ] = 0x%x\n", reg, *reg_value); + + return ret; +} + + +int mcu_pmic_write_reg(int reg, unsigned int reg_value, + unsigned int reg_mask) +{ + int ret = 0; + unsigned int temp = 0; + + ret = mcu_pmic_read(reg, &temp); + if (ret != 0) + return -1; + temp = (temp & (~reg_mask)) | reg_value; + + ret = mcu_pmic_write(reg, temp); + if (ret != 0) + return -1; + + pr_debug("Write REG[ %d ] = 0x%x\n", reg, reg_value); + + return ret; +} + +/*! + * make max8660 - mc9sdz60 enter low-power mode + */ +static void pmic_power_off(void) +{ + mcu_pmic_write_reg(REG_MCU_POWER_CTL, 0x10, 0x10); +} + +static int __init mcu_pmic_init(void) +{ + int err; + + /* init chips */ + err = max8660_init(); + if (err) + goto fail1; + + err = mc9sdz60_init(); + if (err) + goto fail1; + + if (is_max8660_present()) { + pr_info("max8660 is present, reg_max8660_probe\n"); + reg_max8660_probe(); + pm_power_off = pmic_power_off; + } else { + pr_debug("max8660 is not present, reg_mc9sdz60_probe\n"); + reg_mc9sdz60_probe(); + } + pr_info("mcu_pmic_init completed!\n"); + return 0; + +fail1: + pr_err("mcu_pmic_init failed!\n"); + return err; +} + +static void __exit mcu_pmic_exit(void) +{ + reg_max8660_remove(); + mc9sdz60_exit(); + max8660_exit(); +} + +subsys_initcall_sync(mcu_pmic_init); +module_exit(mcu_pmic_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("mcu pmic driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/mcu_pmic/mcu_pmic_gpio.c linux-2.6.26-lab126/drivers/mxc/mcu_pmic/mcu_pmic_gpio.c --- linux-2.6.26/drivers/mxc/mcu_pmic/mcu_pmic_gpio.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/mcu_pmic/mcu_pmic_gpio.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,132 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc9sdz60/mcu_pmic_gpio.c + * @brief This is the main file of mc9sdz60 Power Control driver. + * + * @ingroup PMIC_POWER + */ + +/* + * Includes + */ +#include +#include +#include +#include + +#define SET_BIT_IN_BYTE(byte, pos) (byte |= (0x01 << pos)) +#define CLEAR_BIT_IN_BYTE(byte, pos) (byte &= ~(0x01 << pos)) + +int pmic_gpio_set_bit_val(int reg, unsigned int bit, + unsigned int val) +{ + int reg_name; + u8 reg_mask = 0; + + if (bit > 7) + return -1; + + switch (reg) { + case MCU_GPIO_REG_RESET_1: + reg_name = REG_MCU_RESET_1; + break; + case MCU_GPIO_REG_RESET_2: + reg_name = REG_MCU_RESET_2; + break; + case MCU_GPIO_REG_POWER_CONTROL: + reg_name = REG_MCU_POWER_CTL; + break; + case MCU_GPIO_REG_GPIO_CONTROL_1: + reg_name = REG_MCU_GPIO_1; + break; + case MCU_GPIO_REG_GPIO_CONTROL_2: + reg_name = REG_MCU_GPIO_2; + break; + default: + return -1; + } + + SET_BIT_IN_BYTE(reg_mask, bit); + if (0 == val) + CHECK_ERROR(mcu_pmic_write_reg(reg_name, 0, reg_mask)); + else + CHECK_ERROR(mcu_pmic_write_reg(reg_name, reg_mask, reg_mask)); + + return 0; +} +EXPORT_SYMBOL(pmic_gpio_set_bit_val); + +int pmic_gpio_get_bit_val(int reg, unsigned int bit, + unsigned int *val) +{ + int reg_name; + unsigned int reg_read_val; + u8 reg_mask = 0; + + if (bit > 7) + return -1; + + switch (reg) { + case MCU_GPIO_REG_RESET_1: + reg_name = REG_MCU_RESET_1; + break; + case MCU_GPIO_REG_RESET_2: + reg_name = REG_MCU_RESET_2; + break; + case MCU_GPIO_REG_POWER_CONTROL: + reg_name = REG_MCU_POWER_CTL; + break; + case MCU_GPIO_REG_GPIO_CONTROL_1: + reg_name = REG_MCU_GPIO_1; + break; + case MCU_GPIO_REG_GPIO_CONTROL_2: + reg_name = REG_MCU_GPIO_2; + break; + default: + return -1; + } + + SET_BIT_IN_BYTE(reg_mask, bit); + CHECK_ERROR(mcu_pmic_read_reg(reg_name, ®_read_val, reg_mask)); + if (0 == reg_read_val) + *val = 0; + else + *val = 1; + + return 0; +} +EXPORT_SYMBOL(pmic_gpio_get_bit_val); + +int pmic_gpio_get_designation_bit_val(unsigned int bit, + unsigned int *val) +{ + unsigned int reg_read_val; + u8 reg_mask = 0; + + if (bit > 7) + return -1; + + SET_BIT_IN_BYTE(reg_mask, bit); + CHECK_ERROR( + mcu_pmic_read_reg(REG_MCU_DES_FLAG, ®_read_val, reg_mask)); + if (0 == reg_read_val) + *val = 0; + else + *val = 1; + + return 0; +} +EXPORT_SYMBOL(pmic_gpio_get_designation_bit_val); + diff -urN linux-2.6.26/drivers/mxc/mlb/Kconfig linux-2.6.26-lab126/drivers/mxc/mlb/Kconfig --- linux-2.6.26/drivers/mxc/mlb/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/mlb/Kconfig 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,13 @@ +# +# MLB configuration +# + +menu "MXC Media Local Bus Driver" + +config MXC_MLB + tristate "MLB support" + depends on ARCH_MX35 + ---help--- + Say Y to get the MLB support. + +endmenu diff -urN linux-2.6.26/drivers/mxc/mlb/Makefile linux-2.6.26-lab126/drivers/mxc/mlb/Makefile --- linux-2.6.26/drivers/mxc/mlb/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/mlb/Makefile 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,5 @@ +# +# Makefile for the kernel MLB driver +# + +obj-$(CONFIG_MXC_MLB) += mxc_mlb.o diff -urN linux-2.6.26/drivers/mxc/mlb/mxc_mlb.c linux-2.6.26-lab126/drivers/mxc/mlb/mxc_mlb.c --- linux-2.6.26/drivers/mxc/mlb/mxc_mlb.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/mlb/mxc_mlb.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,1048 @@ +/* + * linux/drivers/mxc/mlb/mxc_mlb.c + * + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/*! + * MLB module memory map registers define + */ +#define MLB_REG_DCCR 0x0 +#define MLB_REG_SSCR 0x4 +#define MLB_REG_SDCR 0x8 +#define MLB_REG_SMCR 0xC +#define MLB_REG_VCCR 0x1C +#define MLB_REG_SBCR 0x20 +#define MLB_REG_ABCR 0x24 +#define MLB_REG_CBCR 0x28 +#define MLB_REG_IBCR 0x2C +#define MLB_REG_CICR 0x30 +#define MLB_REG_CECRn 0x40 +#define MLB_REG_CSCRn 0x44 +#define MLB_REG_CCBCRn 0x48 +#define MLB_REG_CNBCRn 0x4C +#define MLB_REG_LCBCRn 0x280 + +#define MLB_DCCR_FS_OFFSET 28 +#define MLB_DCCR_EN (1 << 31) +#define MLB_DCCR_LBM_OFFSET 30 +#define MLB_DCCR_RESET (1 << 23) +#define MLB_CECR_CE (1 << 31) +#define MLB_CECR_TR (1 << 30) +#define MLB_CECR_CT_OFFSET 28 +#define MLB_CECR_MBS (1 << 19) +#define MLB_CSCR_CBPE (1 << 0) +#define MLB_CSCR_CBDB (1 << 1) +#define MLB_CSCR_CBD (1 << 2) +#define MLB_CSCR_CBS (1 << 3) +#define MLB_CSCR_BE (1 << 4) +#define MLB_CSCR_ABE (1 << 5) +#define MLB_CSCR_LFS (1 << 6) +#define MLB_CSCR_PBPE (1 << 8) +#define MLB_CSCR_PBDB (1 << 9) +#define MLB_CSCR_PBD (1 << 10) +#define MLB_CSCR_PBS (1 << 11) +#define MLB_CSCR_RDY (1 << 16) +#define MLB_CSCR_BM (1 << 31) +#define MLB_CSCR_BF (1 << 30) +#define MLB_SSCR_SDML (1 << 5) + +#define MLB_CONTROL_TX_CHANN (0 << 4) +#define MLB_CONTROL_RX_CHANN (1 << 4) +#define MLB_ASYNC_TX_CHANN (2 << 4) +#define MLB_ASYNC_RX_CHANN (3 << 4) + +#define MLB_MINOR_DEVICES 2 +#define MLB_CONTROL_DEV_NAME "ctrl" +#define MLB_ASYNC_DEV_NAME "async" + +#define TX_CHANNEL 0 +#define RX_CHANNEL 1 +#define TX_CHANNEL_BUF_SIZE 1024 +#define RX_CHANNEL_BUF_SIZE 2*1024 +/* max package data size */ +#define ASYNC_PACKET_SIZE 1024 +#define CTRL_PACKET_SIZE 64 +#define RX_RING_NODES 10 + +#define _get_txchan(dev) mlb_devinfo[dev].channels[TX_CHANNEL] +#define _get_rxchan(dev) mlb_devinfo[dev].channels[RX_CHANNEL] + +enum { + MLB_CTYPE_SYNC, + MLB_CTYPE_ISOC, + MLB_CTYPE_ASYNC, + MLB_CTYPE_CTRL, +}; + +/*! + * Rx ring buffer + */ +struct mlb_rx_ringnode { + int size; + char *data; +}; + +struct mlb_channel_info { + + /* channel offset in memmap */ + const unsigned int reg_offset; + /* channel address */ + int address; + /*! + * channel buffer start address + * for Rx, buf_head pointer to a loop ring buffer + */ + unsigned long buf_head; + /* physical buffer head address */ + unsigned long phy_head; + /* channel buffer size */ + unsigned int buf_size; + /* channel buffer current ptr */ + unsigned long buf_ptr; + /* buffer spin lock */ + rwlock_t buf_lock; +}; + +struct mlb_dev_info { + + /* device node name */ + const char dev_name[20]; + /* channel type */ + const unsigned int channel_type; + /* channel info for tx/rx */ + struct mlb_channel_info channels[2]; + /* rx ring buffer */ + struct mlb_rx_ringnode rx_bufs[RX_RING_NODES]; + /* rx ring buffer read/write ptr */ + unsigned int rdpos, wtpos; + /* exception event */ + unsigned long ex_event; + /* channel started up or not */ + atomic_t on; + /* device open count */ + atomic_t opencnt; + /* wait queue head for channel */ + wait_queue_head_t rd_wq; + wait_queue_head_t wt_wq; + /* spinlock for event access */ + spinlock_t event_lock; +}; + +static struct mlb_dev_info mlb_devinfo[MLB_MINOR_DEVICES] = { + { + .dev_name = MLB_CONTROL_DEV_NAME, + .channel_type = MLB_CTYPE_CTRL, + .channels = { + [0] = { + .reg_offset = MLB_CONTROL_TX_CHANN, + .buf_size = TX_CHANNEL_BUF_SIZE, + .buf_lock = + __RW_LOCK_UNLOCKED(mlb_devinfo[0].channels[0]. + buf_lock), + }, + [1] = { + .reg_offset = MLB_CONTROL_RX_CHANN, + .buf_size = RX_CHANNEL_BUF_SIZE, + .buf_lock = + __RW_LOCK_UNLOCKED(mlb_devinfo[0].channels[1]. + buf_lock), + }, + }, + .on = ATOMIC_INIT(0), + .opencnt = ATOMIC_INIT(0), + .rd_wq = __WAIT_QUEUE_HEAD_INITIALIZER(mlb_devinfo[0].rd_wq), + .wt_wq = __WAIT_QUEUE_HEAD_INITIALIZER(mlb_devinfo[0].wt_wq), + .event_lock = __SPIN_LOCK_UNLOCKED(mlb_devinfo[0].event_lock), + }, + { + .dev_name = MLB_ASYNC_DEV_NAME, + .channel_type = MLB_CTYPE_ASYNC, + .channels = { + [0] = { + .reg_offset = MLB_ASYNC_TX_CHANN, + .buf_size = TX_CHANNEL_BUF_SIZE, + .buf_lock = + __RW_LOCK_UNLOCKED(mlb_devinfo[1].channels[0]. + buf_lock), + }, + [1] = { + .reg_offset = MLB_ASYNC_RX_CHANN, + .buf_size = RX_CHANNEL_BUF_SIZE, + .buf_lock = + __RW_LOCK_UNLOCKED(mlb_devinfo[1].channels[1]. + buf_lock), + }, + }, + .on = ATOMIC_INIT(0), + .opencnt = ATOMIC_INIT(0), + .rd_wq = __WAIT_QUEUE_HEAD_INITIALIZER(mlb_devinfo[1].rd_wq), + .wt_wq = __WAIT_QUEUE_HEAD_INITIALIZER(mlb_devinfo[1].wt_wq), + .event_lock = __SPIN_LOCK_UNLOCKED(mlb_devinfo[1].event_lock), + }, +}; + +static struct regulator *reg_nvcc; /* NVCC_MLB regulator */ +static struct clk *mlb_clk; +static struct cdev mxc_mlb_dev; /* chareset device */ +static dev_t dev; +static struct class *mlb_class; /* device class */ +static struct device *class_dev; +static unsigned long mlb_base; /* mlb module base address */ +static unsigned int irq; + +/*! + * Initial the MLB module device + */ +static void mlb_dev_init(void) +{ + unsigned long dccr_val; + unsigned long phyaddr; + + /* reset the MLB module */ + __raw_writel(MLB_DCCR_RESET, mlb_base + MLB_REG_DCCR); + while (__raw_readl(mlb_base + MLB_REG_DCCR) + & MLB_DCCR_RESET) ; + + /*! + * Enable MLB device, disable loopback mode, + * set default fps to 512, set mlb device address to 0 + */ + dccr_val = MLB_DCCR_EN; + __raw_writel(dccr_val, mlb_base + MLB_REG_DCCR); + + /* disable all the system interrupt */ + __raw_writel(0x5F, mlb_base + MLB_REG_SMCR); + + /* write async, control tx/rx base address */ + phyaddr = _get_txchan(0).phy_head >> 16; + __raw_writel(phyaddr << 16 | phyaddr, mlb_base + MLB_REG_CBCR); + phyaddr = _get_txchan(1).phy_head >> 16; + __raw_writel(phyaddr << 16 | phyaddr, mlb_base + MLB_REG_ABCR); + +} + +static void mlb_dev_exit(void) +{ + __raw_writel(0, mlb_base + MLB_REG_DCCR); +} + +/*! + * MLB receive start function + * + * load phy_head to next buf register to start next rx + * here use single-packet buffer, set start=end + */ +static void mlb_start_rx(int cdev_id) +{ + struct mlb_channel_info *chinfo = &_get_rxchan(cdev_id); + unsigned long next; + + next = chinfo->phy_head & 0xFFFC; + /* load next buf */ + __raw_writel((next << 16) | next, mlb_base + + MLB_REG_CNBCRn + chinfo->reg_offset); + /* set ready bit to start next rx */ + __raw_writel(MLB_CSCR_RDY, mlb_base + MLB_REG_CSCRn + + chinfo->reg_offset); +} + +/*! + * MLB transmit start function + * make sure aquiring the rw buf_lock, when calling this + */ +static void mlb_start_tx(int cdev_id) +{ + struct mlb_channel_info *chinfo = &_get_txchan(cdev_id); + unsigned long begin, end; + + begin = chinfo->phy_head; + end = (chinfo->phy_head + chinfo->buf_ptr - chinfo->buf_head) & 0xFFFC; + /* load next buf */ + __raw_writel((begin << 16) | end, mlb_base + + MLB_REG_CNBCRn + chinfo->reg_offset); + /* set ready bit to start next tx */ + __raw_writel(MLB_CSCR_RDY, mlb_base + MLB_REG_CSCRn + + chinfo->reg_offset); +} + +/*! + * Enable the MLB channel + */ +static void mlb_channel_enable(int chan_dev_id, int on) +{ + unsigned long tx_regval = 0, rx_regval = 0; + /*! + * setup the direction, enable, channel type, + * mode select, channel address and mask buf start + */ + if (on) { + unsigned int ctype = mlb_devinfo[chan_dev_id].channel_type; + tx_regval = MLB_CECR_CE | MLB_CECR_TR | MLB_CECR_MBS | + (ctype << MLB_CECR_CT_OFFSET) | + _get_txchan(chan_dev_id).address; + rx_regval = MLB_CECR_CE | MLB_CECR_MBS | + (ctype << MLB_CECR_CT_OFFSET) | + _get_rxchan(chan_dev_id).address; + + atomic_set(&mlb_devinfo[chan_dev_id].on, 1); + } else { + atomic_set(&mlb_devinfo[chan_dev_id].on, 0); + } + + /* update the rx/tx channel entry config */ + __raw_writel(tx_regval, mlb_base + MLB_REG_CECRn + + _get_txchan(chan_dev_id).reg_offset); + __raw_writel(rx_regval, mlb_base + MLB_REG_CECRn + + _get_rxchan(chan_dev_id).reg_offset); + + if (on) + mlb_start_rx(chan_dev_id); +} + +/*! + * MLB interrupt handler + */ +void mlb_tx_isr(int minor, unsigned int cis) +{ + struct mlb_channel_info *chinfo = &_get_txchan(minor); + + if (cis & MLB_CSCR_CBD) { + /* buffer done, reset the buf_ptr */ + write_lock(&chinfo->buf_lock); + chinfo->buf_ptr = chinfo->buf_head; + write_unlock(&chinfo->buf_lock); + /* wake up the writer */ + wake_up_interruptible(&mlb_devinfo[minor].wt_wq); + } +} + +void mlb_rx_isr(int minor, unsigned int cis) +{ + struct mlb_channel_info *chinfo = &_get_rxchan(minor); + unsigned long end; + unsigned int len; + + if (cis & MLB_CSCR_CBD) { + + int wpos, rpos; + + rpos = mlb_devinfo[minor].rdpos; + wpos = mlb_devinfo[minor].wtpos; + + /* buffer done, get current buffer ptr */ + end = + __raw_readl(mlb_base + MLB_REG_CCBCRn + chinfo->reg_offset); + end >>= 16; /* end here is phy */ + len = end - (chinfo->phy_head & 0xFFFC); + + /*! + * copy packet from IRAM buf to ring buf. + * if the wpos++ == rpos, drop this packet + */ + if (((wpos + 1) % RX_RING_NODES) != rpos) { + +#ifdef DEBUG + if (mlb_devinfo[minor].channel_type == MLB_CTYPE_CTRL) { + if (len > CTRL_PACKET_SIZE) + pr_debug + ("mxc_mlb: ctrl packet" + "overflow\n"); + } else { + if (len > ASYNC_PACKET_SIZE) + pr_debug + ("mxc_mlb: async packet" + "overflow\n"); + } +#endif + memcpy(mlb_devinfo[minor].rx_bufs[wpos].data, + (const void *)chinfo->buf_head, len); + mlb_devinfo[minor].rx_bufs[wpos].size = len; + + /* update the ring wpos */ + mlb_devinfo[minor].wtpos = (wpos + 1) % RX_RING_NODES; + + /* wake up the reader */ + wake_up_interruptible(&mlb_devinfo[minor].rd_wq); + + pr_debug("recv package, len:%d, rdpos: %d, wtpos: %d\n", + len, rpos, mlb_devinfo[minor].wtpos); + } else { + pr_debug + ("drop package, due to no space, (%d,%d)\n", + rpos, mlb_devinfo[minor].wtpos); + } + + /* start next rx */ + mlb_start_rx(minor); + } +} + +static irqreturn_t mlb_isr(int irq, void *dev_id) +{ + unsigned long int_status, sscr, tx_cis, rx_cis; + struct mlb_dev_info *pdev; + int minor; + + sscr = __raw_readl(mlb_base + MLB_REG_SSCR); + pr_debug("mxc_mlb: system interrupt:%lx\n", sscr); + __raw_writel(0x7F, mlb_base + MLB_REG_SSCR); + + int_status = __raw_readl(mlb_base + MLB_REG_CICR) & 0xFFFF; + pr_debug("mxc_mlb: channel interrupt ids: %lx\n", int_status); + + for (minor = 0; minor < MLB_MINOR_DEVICES; minor++) { + + pdev = &mlb_devinfo[minor]; + tx_cis = rx_cis = 0; + + /* get tx channel interrupt status */ + if (int_status & (1 << (_get_txchan(minor).reg_offset >> 4))) + tx_cis = __raw_readl(mlb_base + MLB_REG_CSCRn + + _get_txchan(minor).reg_offset); + /* get rx channel interrupt status */ + if (int_status & (1 << (_get_rxchan(minor).reg_offset >> 4))) + rx_cis = __raw_readl(mlb_base + MLB_REG_CSCRn + + _get_rxchan(minor).reg_offset); + + if (!tx_cis && !rx_cis) + continue; + + pr_debug("tx/rx int status: 0x%08lx/0x%08lx\n", tx_cis, rx_cis); + /* fill exception event */ + spin_lock(&pdev->event_lock); + pdev->ex_event |= tx_cis & 0x303; + pdev->ex_event |= (rx_cis & 0x303) << 16; + spin_unlock(&pdev->event_lock); + + /* clear the interrupt status */ + __raw_writel(tx_cis & 0xFFFF, mlb_base + MLB_REG_CSCRn + + _get_txchan(minor).reg_offset); + __raw_writel(rx_cis & 0xFFFF, mlb_base + MLB_REG_CSCRn + + _get_rxchan(minor).reg_offset); + + /* handel tx channel */ + if (tx_cis) + mlb_tx_isr(minor, tx_cis); + /* handle rx channel */ + if (rx_cis) + mlb_rx_isr(minor, rx_cis); + + } + + return IRQ_HANDLED; +} + +static int mxc_mlb_open(struct inode *inode, struct file *filp) +{ + int minor; + + minor = MINOR(inode->i_rdev); + + if (minor < 0 || minor >= MLB_MINOR_DEVICES) + return -ENODEV; + + /* open for each channel device */ + if (atomic_cmpxchg(&mlb_devinfo[minor].opencnt, 0, 1) != 0) + return -EBUSY; + + /* reset the buffer read/write ptr */ + _get_txchan(minor).buf_ptr = _get_txchan(minor).buf_head; + _get_rxchan(minor).buf_ptr = _get_rxchan(minor).buf_head; + mlb_devinfo[minor].rdpos = mlb_devinfo[minor].wtpos = 0; + mlb_devinfo[minor].ex_event = 0; + + return 0; +} + +static int mxc_mlb_release(struct inode *inode, struct file *filp) +{ + int minor; + + minor = MINOR(inode->i_rdev); + + /* clear channel settings and info */ + mlb_channel_enable(minor, 0); + + /* decrease the open count */ + atomic_set(&mlb_devinfo[minor].opencnt, 0); + + return 0; +} + +static int mxc_mlb_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + void __user *argp = (void __user *)arg; + unsigned long flags, event; + int minor; + + minor = MINOR(inode->i_rdev); + + switch (cmd) { + + case MLB_CHAN_SETADDR: + { + unsigned int caddr; + /* get channel address from user space */ + if (copy_from_user(&caddr, argp, sizeof(caddr))) { + pr_err("mxc_mlb: copy from user failed\n"); + return -EFAULT; + } + _get_txchan(minor).address = (caddr >> 16) & 0xFFFF; + _get_rxchan(minor).address = caddr & 0xFFFF; + break; + } + + case MLB_CHAN_STARTUP: + if (atomic_read(&mlb_devinfo[minor].on)) { + pr_debug("mxc_mlb: channel areadly startup\n"); + break; + } + mlb_channel_enable(minor, 1); + break; + case MLB_CHAN_SHUTDOWN: + if (atomic_read(&mlb_devinfo[minor].on) == 0) { + pr_debug("mxc_mlb: channel areadly shutdown\n"); + break; + } + mlb_channel_enable(minor, 0); + break; + case MLB_CHAN_GETEVENT: + /* get and clear the ex_event */ + spin_lock_irqsave(&mlb_devinfo[minor].event_lock, flags); + event = mlb_devinfo[minor].ex_event; + mlb_devinfo[minor].ex_event = 0; + spin_unlock_irqrestore(&mlb_devinfo[minor].event_lock, flags); + + if (event) { + if (copy_to_user(argp, &event, sizeof(event))) { + pr_err("mxc_mlb: copy to user failed\n"); + return -EFAULT; + } + } else { + pr_debug("mxc_mlb: no exception event now\n"); + return -EAGAIN; + } + break; + case MLB_SET_FPS: + { + unsigned int fps; + unsigned long dccr_val; + + /* get fps from user space */ + if (copy_from_user(&fps, argp, sizeof(fps))) { + pr_err("mxc_mlb: copy from user failed\n"); + return -EFAULT; + } + + /* check fps value */ + if (fps != 256 && fps != 512 && fps != 1024) { + pr_debug("mxc_mlb: invalid fps argument\n"); + return -EINVAL; + } + + dccr_val = __raw_readl(mlb_base + MLB_REG_DCCR); + dccr_val &= ~(0x3 << MLB_DCCR_FS_OFFSET); + dccr_val |= (fps >> 9) << MLB_DCCR_FS_OFFSET; + __raw_writel(dccr_val, mlb_base + MLB_REG_DCCR); + break; + } + + case MLB_GET_VER: + { + unsigned long version; + + /* get MLB device module version */ + version = __raw_readl(mlb_base + MLB_REG_VCCR); + + if (copy_to_user(argp, &version, sizeof(version))) { + pr_err("mxc_mlb: copy to user failed\n"); + return -EFAULT; + } + break; + } + + case MLB_SET_DEVADDR: + { + unsigned long dccr_val; + unsigned char devaddr; + + /* get MLB device address from user space */ + if (copy_from_user + (&devaddr, argp, sizeof(unsigned char))) { + pr_err("mxc_mlb: copy from user failed\n"); + return -EFAULT; + } + + dccr_val = __raw_readl(mlb_base + MLB_REG_DCCR); + dccr_val &= ~0xFF; + dccr_val |= devaddr; + __raw_writel(dccr_val, mlb_base + MLB_REG_DCCR); + + break; + } + default: + pr_info("mxc_mlb: Invalid ioctl command\n"); + return -EINVAL; + } + + return 0; +} + +/*! + * MLB read routine + * + * Read the current received data from queued buffer, + * and free this buffer for hw to fill ingress data. + */ +static ssize_t mxc_mlb_read(struct file *filp, char __user *buf, + size_t count, loff_t *f_pos) +{ + int minor, ret; + int size, rdpos; + struct mlb_rx_ringnode *rxbuf; + + minor = MINOR(filp->f_dentry->d_inode->i_rdev); + + rdpos = mlb_devinfo[minor].rdpos; + rxbuf = mlb_devinfo[minor].rx_bufs; + + /* check the current rx buffer is available or not */ + if (rdpos == mlb_devinfo[minor].wtpos) { + if (filp->f_flags & O_NONBLOCK) + return -EAGAIN; + /* if !O_NONBLOCK, we wait for recv packet */ + ret = wait_event_interruptible(mlb_devinfo[minor].rd_wq, + (mlb_devinfo[minor].wtpos != + rdpos)); + if (ret < 0) + return ret; + } + + size = rxbuf[rdpos].size; + if (size > count) { + /* the user buffer is too small */ + pr_warning + ("mxc_mlb: received data size is bigger than count\n"); + return -EINVAL; + } + + /* copy rx buffer data to user buffer */ + if (copy_to_user(buf, rxbuf[rdpos].data, size)) { + pr_err("mxc_mlb: copy from user failed\n"); + return -EFAULT; + } + + /* update the read ptr */ + mlb_devinfo[minor].rdpos = (rdpos + 1) % RX_RING_NODES; + + *f_pos = 0; + + return size; +} + +/*! + * MLB write routine + * + * Copy the user data to tx channel buffer, + * and prepare the channel current/next buffer ptr. + */ +static ssize_t mxc_mlb_write(struct file *filp, const char __user *buf, + size_t count, loff_t *f_pos) +{ + int minor; + unsigned long flags; + DEFINE_WAIT(__wait); + int ret; + + minor = MINOR(filp->f_dentry->d_inode->i_rdev); + + if (count > _get_txchan(minor).buf_size) { + /* too many data to write */ + pr_warning("mxc_mlb: overflow write data\n"); + return -EFBIG; + } + + *f_pos = 0; + + /* check the current tx buffer is used or not */ + write_lock_irqsave(&_get_txchan(minor).buf_lock, flags); + if (_get_txchan(minor).buf_ptr != _get_txchan(minor).buf_head) { + write_unlock_irqrestore(&_get_txchan(minor).buf_lock, flags); + + /* there's already some datas being transmit now */ + if (filp->f_flags & O_NONBLOCK) + return -EAGAIN; + + /* if !O_NONBLOCK, we wait for transmit finish */ + for (;;) { + prepare_to_wait(&mlb_devinfo[minor].wt_wq, + &__wait, TASK_INTERRUPTIBLE); + + write_lock_irqsave(&_get_txchan(minor).buf_lock, flags); + if (_get_txchan(minor).buf_ptr == + _get_txchan(minor).buf_head) + break; + + write_unlock_irqrestore(&_get_txchan(minor).buf_lock, + flags); + if (!signal_pending(current)) { + schedule(); + continue; + } + return -ERESTARTSYS; + } + finish_wait(&mlb_devinfo[minor].wt_wq, &__wait); + } + + /* copy user buffer to tx buffer */ + if (copy_from_user((void *)_get_txchan(minor).buf_ptr, buf, count)) { + pr_err("mxc_mlb: copy from user failed\n"); + ret = -EFAULT; + goto out; + } + _get_txchan(minor).buf_ptr += count; + + /* set current/next buffer start/end */ + mlb_start_tx(minor); + + ret = count; + +out: + write_unlock_irqrestore(&_get_txchan(minor).buf_lock, flags); + return ret; +} + +static unsigned int mxc_mlb_poll(struct file *filp, + struct poll_table_struct *wait) +{ + int minor; + unsigned int ret = 0; + unsigned long flags; + + minor = MINOR(filp->f_dentry->d_inode->i_rdev); + + poll_wait(filp, &mlb_devinfo[minor].rd_wq, wait); + poll_wait(filp, &mlb_devinfo[minor].wt_wq, wait); + + /* check the tx buffer is avaiable or not */ + read_lock_irqsave(&_get_txchan(minor).buf_lock, flags); + if (_get_txchan(minor).buf_ptr == _get_txchan(minor).buf_head) + ret |= POLLOUT | POLLWRNORM; + read_unlock_irqrestore(&_get_txchan(minor).buf_lock, flags); + + /* check the rx buffer filled or not */ + if (mlb_devinfo[minor].rdpos != mlb_devinfo[minor].wtpos) + ret |= POLLIN | POLLRDNORM; + + /* check the exception event */ + if (mlb_devinfo[minor].ex_event) + ret |= POLLIN | POLLRDNORM; + + return ret; +} + +/*! + * char dev file operations structure + */ +static struct file_operations mxc_mlb_fops = { + + .owner = THIS_MODULE, + .open = mxc_mlb_open, + .release = mxc_mlb_release, + .ioctl = mxc_mlb_ioctl, + .poll = mxc_mlb_poll, + .read = mxc_mlb_read, + .write = mxc_mlb_write, +}; + +/*! + * This function is called whenever the MLB device is detected. + */ +static int __devinit mxc_mlb_probe(struct platform_device *pdev) +{ + int ret, mlb_major, i, j; + struct mxc_mlb_platform_data *plat_data; + struct resource *res; + void __iomem *base; + unsigned long bufaddr, phyaddr; + + /* malloc the Rx ring buffer firstly */ + for (i = 0; i < MLB_MINOR_DEVICES; i++) { + char *buf; + int bufsize; + + if (mlb_devinfo[i].channel_type == MLB_CTYPE_ASYNC) + bufsize = ASYNC_PACKET_SIZE; + else + bufsize = CTRL_PACKET_SIZE; + + buf = kmalloc(bufsize * RX_RING_NODES, GFP_KERNEL); + if (buf == NULL) { + ret = -ENOMEM; + dev_err(&pdev->dev, "can not alloc rx buffers\n"); + goto err4; + } + for (j = 0; j < RX_RING_NODES; j++) { + mlb_devinfo[i].rx_bufs[j].data = buf; + buf += bufsize; + } + } + + /** + * Register MLB lld as two character devices + * One for Packet date channel, the other for control data channel + */ + ret = alloc_chrdev_region(&dev, 0, MLB_MINOR_DEVICES, "mxc_mlb"); + mlb_major = MAJOR(dev); + + if (ret < 0) { + dev_err(&pdev->dev, "can't get major %d\n", mlb_major); + goto err3; + } + + cdev_init(&mxc_mlb_dev, &mxc_mlb_fops); + mxc_mlb_dev.owner = THIS_MODULE; + + ret = cdev_add(&mxc_mlb_dev, dev, MLB_MINOR_DEVICES); + if (ret) { + dev_err(&pdev->dev, "can't add cdev\n"); + goto err2; + } + + /* create class and device for udev information */ + mlb_class = class_create(THIS_MODULE, "mlb"); + if (IS_ERR(mlb_class)) { + dev_err(&pdev->dev, "failed to create mlb class\n"); + ret = -ENOMEM; + goto err2; + } + + for (i = 0; i < MLB_MINOR_DEVICES; i++) { + + class_dev = device_create(mlb_class, NULL, MKDEV(mlb_major, i), + mlb_devinfo[i].dev_name); + if (IS_ERR(class_dev)) { + dev_err(&pdev->dev, "failed to create mlb %s" + " class device\n", mlb_devinfo[i].dev_name); + ret = -ENOMEM; + goto err1; + } + } + + /* get irq line */ + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (res == NULL) { + dev_err(&pdev->dev, "No mlb irq line provided\n"); + goto err1; + } + + irq = res->start; + /* request irq */ + if (request_irq(irq, mlb_isr, 0, "mlb", NULL)) { + dev_err(&pdev->dev, "failed to request irq\n"); + ret = -EBUSY; + goto err1; + } + + /* ioremap from phy mlb to kernel space */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "No mlb base address provided\n"); + goto err0; + } + + base = ioremap(res->start, res->end - res->start); + dev_dbg(&pdev->dev, "mapped mlb base address: 0x%08x\n", + (unsigned int)base); + + if (base == NULL) { + dev_err(&pdev->dev, "failed to do ioremap with mlb base\n"); + goto err0; + } + mlb_base = (unsigned long)base; + + /*! + * get rx/tx buffer address from platform data + * make sure the buf_address is 4bytes aligned + * + * ------------------- <-- plat_data->buf_address + * | minor 0 tx buf | + * ----------------- + * | minor 0 rx buf | + * ----------------- + * | .... | + * ----------------- + * | minor n tx buf | + * ----------------- + * | minor n rx buf | + * ------------------- + */ + + plat_data = (struct mxc_mlb_platform_data *)pdev->dev.platform_data; + + bufaddr = plat_data->buf_address & ~0x3; + phyaddr = plat_data->phy_address & ~0x3; + + for (i = 0; i < MLB_MINOR_DEVICES; i++) { + /* set the virtual and physical buf head address */ + _get_txchan(i).buf_head = bufaddr; + _get_txchan(i).phy_head = phyaddr; + + bufaddr += TX_CHANNEL_BUF_SIZE; + phyaddr += TX_CHANNEL_BUF_SIZE; + + _get_rxchan(i).buf_head = bufaddr; + _get_rxchan(i).phy_head = phyaddr; + + bufaddr += RX_CHANNEL_BUF_SIZE; + phyaddr += RX_CHANNEL_BUF_SIZE; + + dev_dbg(&pdev->dev, "phy_head: tx(%lx), rx(%lx)\n", + _get_txchan(i).phy_head, _get_rxchan(i).phy_head); + dev_dbg(&pdev->dev, "buf_head: tx(%lx), rx(%lx)\n", + _get_txchan(i).buf_head, _get_rxchan(i).buf_head); + } + + /* enable GPIO */ + gpio_mlb_active(); + + /* power on MLB */ + reg_nvcc = regulator_get(&pdev->dev, plat_data->reg_nvcc); + /* set MAX LDO6 for NVCC to 2.5V */ + regulator_set_voltage(reg_nvcc, 2500000); + regulator_enable(reg_nvcc); + + /* enable clock */ + mlb_clk = clk_get(&pdev->dev, plat_data->mlb_clk); + clk_enable(mlb_clk); + + /* initial MLB module */ + mlb_dev_init(); + + return 0; + +err0: + free_irq(irq, NULL); +err1: + for (--i; i >= 0; i--) + device_destroy(mlb_class, MKDEV(mlb_major, i)); + + class_destroy(mlb_class); +err2: + cdev_del(&mxc_mlb_dev); +err3: + unregister_chrdev_region(dev, MLB_MINOR_DEVICES); +err4: + for (i = 0; i < MLB_MINOR_DEVICES; i++) + kfree(mlb_devinfo[i].rx_bufs[0].data); + + return ret; +} + +static int __devexit mxc_mlb_remove(struct platform_device *pdev) +{ + int i; + + mlb_dev_exit(); + + /* disable mlb clock */ + clk_disable(mlb_clk); + clk_put(mlb_clk); + + /* disable mlb power */ + regulator_disable(reg_nvcc); + regulator_put(reg_nvcc, &pdev->dev); + + /* inactive GPIO */ + gpio_mlb_inactive(); + + /* iounmap */ + iounmap((void *)mlb_base); + + free_irq(irq, NULL); + + /* destroy mlb device class */ + for (i = MLB_MINOR_DEVICES - 1; i >= 0; i--) + device_destroy(mlb_class, MKDEV(MAJOR(dev), i)); + class_destroy(mlb_class); + + /* Unregister the two MLB devices */ + cdev_del(&mxc_mlb_dev); + unregister_chrdev_region(dev, MLB_MINOR_DEVICES); + + for (i = 0; i < MLB_MINOR_DEVICES; i++) + kfree(mlb_devinfo[i].rx_bufs[0].data); + + return 0; +} + +#ifdef CONFIG_PM +static int mxc_mlb_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +static int mxc_mlb_resume(struct platform_device *pdev) +{ + return 0; +} +#else +#define mxc_mlb_suspend NULL +#define mxc_mlb_resume NULL +#endif + +/*! + * platform driver structure for MLB + */ +static struct platform_driver mxc_mlb_driver = { + .driver = { + .name = "mxc_mlb"}, + .probe = mxc_mlb_probe, + .remove = __devexit_p(mxc_mlb_remove), + .suspend = mxc_mlb_suspend, + .resume = mxc_mlb_resume, +}; + +static int __init mxc_mlb_init(void) +{ + return platform_driver_register(&mxc_mlb_driver); +} + +static void __exit mxc_mlb_exit(void) +{ + platform_driver_unregister(&mxc_mlb_driver); +} + +module_init(mxc_mlb_init); +module_exit(mxc_mlb_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MLB low level driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/pm/Kconfig linux-2.6.26-lab126/drivers/mxc/pm/Kconfig --- linux-2.6.26/drivers/mxc/pm/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pm/Kconfig 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,15 @@ +# +# Power Managment devices +# + +menu "Advanced Power Management devices" + +config MX27_DPTC + bool "MXC DPTC driver" + depends on ARCH_MX27 && MXC_PMIC_MC13783 + default y + help + This selects the Freescale MX27 Internal DPTC driver. + If unsure, say N. + +endmenu diff -urN linux-2.6.26/drivers/mxc/pm/Makefile linux-2.6.26-lab126/drivers/mxc/pm/Makefile --- linux-2.6.26/drivers/mxc/pm/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pm/Makefile 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,4 @@ +# +# Makefile for Power Managment devices. +# +obj-$(CONFIG_MX27_DPTC) += dptc_mx27.o diff -urN linux-2.6.26/drivers/mxc/pm/dptc_mx27.c linux-2.6.26-lab126/drivers/mxc/pm/dptc_mx27.c --- linux-2.6.26/drivers/mxc/pm/dptc_mx27.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pm/dptc_mx27.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,1415 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dptc_mx27.c + * + * @brief Driver for the Freescale Semiconductor MX27 DPTC module. + * + * The DPTC driver is designed as a character driver which interacts with the + * MX27 DPTC hardware. Upon initialization, the DPTC driver initializes the + * DPTC hardware sets up driver nodes attaches to the DPTC interrupt and + * initializes internal data structures. When the DPTC interrupt occurs the + * driver checks the cause of the interrupt (lower voltage, increase voltage or + * emergency) and changes the CPU voltage according to translation table that + * is loaded into the driver(the voltage changes are done by calling some + * routines in the mc13783 driver). The driver read method is used to read the + * currently loaded DPTC translation table and the write method is used + * in-order to update the translation table. Driver ioctls are used to change + * driver parameters and enable/disable the DPTC operation. + * + * @ingroup PM_MX27 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dvfs_dptc.h" + +#define MX27_PMCR_BASE_ADDR (SYSCTRL_BASE_ADDR + 0x60) +#define MX27_DCVR_BASE_ADDR (SYSCTRL_BASE_ADDR + 0x64) +#define MX27_DCVR0_OFFSET 0 +#define MX27_DCVR1_OFFSET 4 +#define MX27_DCVR2_OFFSET 8 +#define MX27_DCVR3_OFFSET 12 + +#define MX27_PMCR_MC_STATUS_OFFSET 31 +#define MX27_PMCR_MC_STATUS_MASK (1 << 31) +#define MX27_PMCR_EM_INTR_OFFSET 30 +#define MX27_PMCR_EM_INTR_MASK (1 << 30) +#define MX27_PMCR_UP_INTR_OFFSET 29 +#define MX27_PMCR_UP_INTR_MASK (1 << 29) +#define MX27_PMCR_LO_INTR_OFFSET 28 +#define MX27_PMCR_LO_INTR_MASK (1 << 28) +#define MX27_PMCR_REFCNT_OFFSET 16 +#define MX27_PMCR_REFCNT_MASK (0x7FF << 16) +#define MX27_PMCR_DCR_OFFSET 9 +#define MX27_PMCR_DCR_MASK (1 << 9) +#define MX27_PMCR_RCLKON_OFFSET 8 +#define MX27_PMCR_RCLKON_MASK (1 << 8) +#define MX27_PMCR_DRCE3_OFFSET 7 +#define MX27_PMCR_DRCE3_MASK (1 << 7) +#define MX27_PMCR_DRCE2_OFFSET 6 +#define MX27_PMCR_DRCE2_MASK (1 << 6) +#define MX27_PMCR_DRCE1_OFFSET 5 +#define MX27_PMCR_DRCE1_MASK (1 << 5) +#define MX27_PMCR_DRCE0_OFFSET 4 +#define MX27_PMCR_DRCE0_MASK (1 << 4) +#define MX27_PMCR_DIM_OFFSET 2 +#define MX27_PMCR_DIM_MASK (0x3 << 2) +#define MX27_PMCR_DIE_OFFSET 1 +#define MX27_PMCR_DIE_MASK (1 << 1) +#define MX27_PMCR_DPTEN_OFFSET 0 +#define MX27_PMCR_DPTEN_MASK (1 << 0) + +/*! + * DPTC proc file system entry name + */ +#define PROC_NODE_NAME "dptc" + +/* + * Prototypes + */ +static int dptc_mx27_open(struct inode *inode, struct file *filp); +static int dptc_mx27_release(struct inode *inode, struct file *filp); +static int dptc_mx27_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +static irqreturn_t dptc_mx27_irq(int irq, void *dev_id); + +/* + * Global variables + */ + +/*! + * The dvfs_dptc_params structure holds all the internal DPTC driver parameters + * (current working point, current frequency, translation table and DPTC + * log buffer). + */ +static dvfs_dptc_params_s dptc_params; + +static struct work_struct dptc_work; +static volatile u32 dptc_intr_status; +static u32 dptc_initial_wp; + +/*! + * Holds the automatically selected DPTC driver major number. + */ +static int major; + +static struct class *mxc_dvfs_dptc_class; + +/* + * This mutex makes the Read,Write and IOCTL command mutual exclusive. + */ +DECLARE_MUTEX(access_mutex); + +/*! + * This structure contains pointers for device driver entry point. + * The driver register function in init module will call this + * structure. + */ +static struct file_operations fops = { + .open = dptc_mx27_open, + .release = dptc_mx27_release, + .ioctl = dptc_mx27_ioctl, +}; + +static +void mx27_pmcr_modify_reg(u32 mask, u32 val) +{ + volatile u32 reg; + reg = __raw_readl(IO_ADDRESS(MX27_PMCR_BASE_ADDR)); + reg = (reg & (~mask)) | val; + __raw_writel(reg, IO_ADDRESS(MX27_PMCR_BASE_ADDR)); +} + +static +void mx27_dcvr_modify_reg(u32 offset, u32 val) +{ + __raw_writel(val, IO_ADDRESS(MX27_DCVR_BASE_ADDR) + offset); +} + +/*! + * Enable DPTC hardware + */ +static void dptc_enable_dptc(void) +{ + mx27_pmcr_modify_reg(MX27_PMCR_DPTEN_MASK, 1); +} + +/*! + * Disable DPTC hardware + */ +static void dptc_disable_dptc(void) +{ + mx27_pmcr_modify_reg(MX27_PMCR_DPTEN_MASK, 0); +} + +/*! + * Mask DPTC interrupt + */ +static void dptc_mask_dptc_int(void) +{ + mx27_pmcr_modify_reg(MX27_PMCR_DIE_MASK, (0 << MX27_PMCR_DIE_OFFSET)); +} + +/*! + * Unmask DPTC interrupt + */ +static void dptc_unmask_dptc_int(void) +{ + mx27_pmcr_modify_reg(MX27_PMCR_DIE_MASK, (1 << MX27_PMCR_DIE_OFFSET)); +} + +/*! + * Clear DCR bits of the CCM + */ +static void dptc_clear_dcr(void) +{ + mx27_pmcr_modify_reg(MX27_PMCR_DCR_MASK, (0 << MX27_PMCR_DCR_OFFSET)); +} + +/*! + * This function enables the DPTC reference circuits. + * + * @param rc_state each high bit specifies which + * reference circuite to enable + * @return 0 on success, error code on failure + */ +static int enable_ref_circuits(unsigned char rc_state) +{ + int ret_val; + + if (dptc_params.dptc_is_active == FALSE) { + dptc_params.rc_state = rc_state; + + if (rc_state & 0x1) { + mx27_pmcr_modify_reg(MX27_PMCR_DRCE0_MASK, + (1 << MX27_PMCR_DRCE0_OFFSET)); + } + if (rc_state & 0x2) { + mx27_pmcr_modify_reg(MX27_PMCR_DRCE1_MASK, + (1 << MX27_PMCR_DRCE1_OFFSET)); + } + if (rc_state & 0x4) { + mx27_pmcr_modify_reg(MX27_PMCR_DRCE2_MASK, + (1 << MX27_PMCR_DRCE2_OFFSET)); + } + if (rc_state & 0x8) { + mx27_pmcr_modify_reg(MX27_PMCR_DRCE3_MASK, + (1 << MX27_PMCR_DRCE3_OFFSET)); + } + + ret_val = 0; + } else { + ret_val = -EINVAL; + } + + return ret_val; +} + +/*! + * This function disables the DPTC reference circuits. + * + * @param rc_state each high bit specifies which + * reference circuite to disable + * @return 0 on success, error code on failure + */ +static int disable_ref_circuits(unsigned char rc_state) +{ + int ret_val; + + if (dptc_params.dptc_is_active == FALSE) { + dptc_params.rc_state &= ~rc_state; + + if (rc_state & 0x1) { + mx27_pmcr_modify_reg(MX27_PMCR_DRCE0_MASK, + (0 << MX27_PMCR_DRCE0_OFFSET)); + } + if (rc_state & 0x2) { + mx27_pmcr_modify_reg(MX27_PMCR_DRCE1_MASK, + (0 << MX27_PMCR_DRCE1_OFFSET)); + } + if (rc_state & 0x4) { + mx27_pmcr_modify_reg(MX27_PMCR_DRCE2_MASK, + (0 << MX27_PMCR_DRCE2_OFFSET)); + } + if (rc_state & 0x8) { + mx27_pmcr_modify_reg(MX27_PMCR_DRCE3_MASK, + (0 << MX27_PMCR_DRCE3_OFFSET)); + } + + ret_val = 0; + } else { + ret_val = -EINVAL; + } + + return ret_val; +} + +/*! + * This function updates the CPU voltage, produced by MC13783, by calling + * MC13783 driver functions. + * + * @param dvfs_dptc_tables_ptr pointer to the DPTC translation table. + * @param wp current wp value. + * + */ +static void set_pmic_voltage(dvfs_dptc_tables_s * dvfs_dptc_tables_ptr, int wp) +{ + /* Call MC13783 functions */ + t_regulator_voltage volt; + + volt.sw1a = dvfs_dptc_tables_ptr->wp[wp].pmic_values[0]; + pmic_power_regulator_set_voltage(SW_SW1A, volt); +} + +/*! + * This function updates the DPTC threshold registers. + * + * @param dvfs_dptc_tables_ptr pointer to the DPTC translation table. + * @param wp current wp value. + * + */ +static void update_dptc_thresholds(dvfs_dptc_tables_s * dvfs_dptc_tables_ptr, + int wp) +{ + dcvr_state *dcvr; + + /* Calculate current table entry offset in the DPTC translation table */ + dcvr = &dvfs_dptc_tables_ptr->dcvr[0][wp]; + + /* Update DPTC threshold registers */ + mx27_dcvr_modify_reg(MX27_DCVR0_OFFSET, dcvr->dcvr_reg[0].AsInt); + mx27_dcvr_modify_reg(MX27_DCVR1_OFFSET, dcvr->dcvr_reg[1].AsInt); + mx27_dcvr_modify_reg(MX27_DCVR2_OFFSET, dcvr->dcvr_reg[2].AsInt); + mx27_dcvr_modify_reg(MX27_DCVR3_OFFSET, dcvr->dcvr_reg[3].AsInt); +} + +/*! + * This function increments a log buffer index (head or tail) + * by the value of val. + * + * @param index pointer to the DPTC log buffer index that + * we wish to change. + * @param val the value in which the index should be incremented. + * + */ +static void inc_log_index(int *index, int val) +{ + *index = (*index + val) % LOG_ENTRIES; +} + +/*! + * This function adds a new entry to the DPTC log buffer. + * + * @param dptc_log pointer to the DPTC log buffer structure. + * @param wp value of the working point index written + * to the log buffer. + * + * @return number of log buffer entries. + * + */ +static void add_dptc_log_entry(dptc_log_s * dptc_log, int wp) +{ + /* + * Down the log buffer mutex to exclude others from reading and + * writing to the log buffer. + */ + if (down_interruptible(&dptc_log->mutex)) { + return; + } + + /* Write values to log buffer */ + dptc_log->entries[dptc_log->head].jiffies = jiffies; + dptc_log->entries[dptc_log->head].wp = wp; + + dptc_log->entries[dptc_log->head].voltage = wp; + dptc_log->entries[dptc_log->head].freq = 0; + + /* Increment the head index by 1 */ + inc_log_index(&dptc_log->head, 1); + /* If head index reaches the tail increment the tail by 1 */ + if (dptc_log->head == dptc_log->tail) { + inc_log_index(&dptc_log->tail, 1); + } + + /* Up the log buffer mutex to allow access to the log buffer */ + up(&dptc_log->mutex); +} + +/*! + * This function updates the drivers current working point index. This index is + * used for access the current DTPC table entry and it corresponds to the + * current CPU working point measured by the DPTC hardware. + * + * @param new_wp New working point index value to be set. + * + */ +static void set_dptc_wp(int new_wp) +{ + /* + * Check if new index is smaller than the maximal working point + * index in the DPTC translation table and larger that 0. + */ + if ((new_wp < dptc_params.dvfs_dptc_tables_ptr->wp_num) + && (new_wp >= 0)) { + /* Set current working point index to new index */ + dptc_params.dvfs_dptc_tables_ptr->curr_wp = new_wp; + } + + /* + * Check if new index is larger than the maximal working point index in + * the DPTC translation table. + */ + if (new_wp >= dptc_params.dvfs_dptc_tables_ptr->wp_num) { + /* + * Set current working point index to maximal working point + * index in the DPTC translation table. + */ + dptc_params.dvfs_dptc_tables_ptr->curr_wp = + dptc_params.dvfs_dptc_tables_ptr->wp_num - 1; + } + + /* Check if new index is smaller than 0. */ + if (new_wp < 0) { + /* Set current working point index to 0 (minimal value) */ + dptc_params.dvfs_dptc_tables_ptr->curr_wp = 0; + } + + /* Update the DPTC hardware thresholds */ + update_dptc_thresholds(dptc_params.dvfs_dptc_tables_ptr, + dptc_params.dvfs_dptc_tables_ptr->curr_wp); + + /* Update the MC13783 voltage */ + set_pmic_voltage(dptc_params.dvfs_dptc_tables_ptr, + dptc_params.dvfs_dptc_tables_ptr->curr_wp); + + /* Write DPTC changes in the DPTC log buffer */ + add_dptc_log_entry(&dptc_params.dptc_log_buffer, + dptc_params.dvfs_dptc_tables_ptr->curr_wp); + +} + +static void dptc_workqueue_handler(struct work_struct *work) +{ + if (dptc_intr_status & 0x4) { + /* Chip working point has increased dramatically, + * raise working point to maximum */ + set_dptc_wp(dptc_params.dvfs_dptc_tables_ptr->curr_wp - 2); + } else if (dptc_intr_status & 0x2) { + /* Chip working point has increased, raise working point + * by one */ + set_dptc_wp(dptc_params.dvfs_dptc_tables_ptr->curr_wp + 1); + } else { + /* Chip working point has decreased, lower working point + * by one */ + set_dptc_wp(dptc_params.dvfs_dptc_tables_ptr->curr_wp - 1); + } + + /* + * If the DPTC module is still active, re-enable + * the DPTC hardware + */ + if (dptc_params.dptc_is_active) { + dptc_enable_dptc(); + dptc_unmask_dptc_int(); + } +} + +/*! + * This function enables the DPTC module. this function updates the DPTC + * thresholds, updates the MC13783, unmasks the DPTC interrupt and enables + * the DPTC module + * + * @return 0 if DPTC module was enabled else returns -EINVAL. + */ +static int start_dptc(void) +{ + /* Check if DPTC module isn't already active */ + if (dptc_params.dptc_is_active == FALSE) { + + enable_ref_circuits(dptc_params.rc_state); + disable_ref_circuits(~dptc_params.rc_state); + + /* + * Set the DPTC thresholds and MC13783 voltage to + * correspond to the current working point and frequency. + */ + set_pmic_voltage(dptc_params.dvfs_dptc_tables_ptr, + dptc_params.dvfs_dptc_tables_ptr->curr_wp); + + update_dptc_thresholds(dptc_params.dvfs_dptc_tables_ptr, + dptc_params.dvfs_dptc_tables_ptr-> + curr_wp); + + /* Mark DPTC module as active */ + dptc_params.dptc_is_active = TRUE; + + /* Enable the DPTC module and unmask the DPTC interrupt */ + dptc_enable_dptc(); + dptc_unmask_dptc_int(); + + return 0; + } + + /* DPTC module already active return error */ + return -EINVAL; +} + +/*! + * This function disables the DPTC module. + * + * @return 0 if DPTC module was disabled else returns -EINVAL. + */ +static int stop_dptc(void) +{ + /* Check if DPTC module isn't already disabled */ + if (dptc_params.dptc_is_active != FALSE) { + + /* Disable the DPTC module and mask the DPTC interrupt */ + dptc_disable_dptc(); + dptc_mask_dptc_int(); + + /* Set working point to default */ + set_dptc_wp(dptc_initial_wp); + + /* Mark DPCT module as inactive */ + dptc_params.dptc_is_active = FALSE; + + return 0; + } + + /* DPTC module already disabled, return error */ + return -EINVAL; +} + +static void init_dptc_wp(void) +{ + /* Call MC13783 functions */ + t_regulator_voltage volt; + int i; + + /* Normal mode setting */ + pmic_power_regulator_get_voltage(SW_SW1A, &volt); + for (i = 0; i < dptc_params.dvfs_dptc_tables_ptr->wp_num; i++) { + if (volt.sw1a == + dptc_params.dvfs_dptc_tables_ptr->wp[i].pmic_values[0]) { + break; + } + } + + /* + * Check if new index is smaller than the maximal working point + * index in the DPTC translation table and larger that 0. + */ + if ((i < dptc_params.dvfs_dptc_tables_ptr->wp_num) && (i >= 0)) { + /* Set current working point index to new index */ + dptc_params.dvfs_dptc_tables_ptr->curr_wp = i; + } + + /* + * Check if new index is larger than the maximal working point index in + * the DPTC translation table. + */ + if (i >= dptc_params.dvfs_dptc_tables_ptr->wp_num) { + /* + * Set current working point index to maximal working point + * index in the DPTC translation table. + */ + dptc_params.dvfs_dptc_tables_ptr->curr_wp = + dptc_params.dvfs_dptc_tables_ptr->wp_num - 1; + } + + dptc_initial_wp = dptc_params.dvfs_dptc_tables_ptr->curr_wp; + + /* Initialize the log buffer */ + add_dptc_log_entry(&dptc_params.dptc_log_buffer, + dptc_params.dvfs_dptc_tables_ptr->curr_wp); +} + +/*! + * This function returns the number of entries in the DPTC log buffer. + * + * @param dptc_log pointer to the DPTC log buffer structure. + * + * @return number of log buffer entries. + * + */ +static int get_entry_count(dptc_log_s * dptc_log) +{ + return ((dptc_log->head - dptc_log->tail + LOG_ENTRIES) % LOG_ENTRIES); +} + +/*! + * This function is used by the proc file system to read the DPTC log buffer. + * Each time the DPTC proc file system file is read this function is called + * and returns the data written in the log buffer. + * + * @param buf pointer to the buffer the data should be written to. + * @param start pointer to the pointer where the new data is + * written to. + * procedure should update the start pointer to point to + * where in the buffer the data was written. + * @param offset current offset in the DPTC proc file. + * @param count number of bytes to read. + * @param eof pointer to eof flag. should be set to 1 when + * reaching eof. + * @param data driver specific data pointer. + * + * @return number byte read from the log buffer. + * + */ +static int read_log(char *buf, char **start, off_t offset, int count, + int *eof, void *data) +{ + int entries_to_read; + int num_of_entries; + int entries_to_end_of_buffer, entries_left; + void *entry_ptr; + char *buf_ptr; + dvfs_dptc_params_s *params; + + params = (dvfs_dptc_params_s *) data; + + /* Calculate number of log entries to read */ + entries_to_read = count / sizeof(dptc_log_entry_s); + /* Get the number of current log buffer entries */ + num_of_entries = get_entry_count(¶ms->dptc_log_buffer); + + /* + * If number of entries to read is larger that the number of entries + * in the log buffer set number of entries to read to number of + * entries in the log buffer and set eof flag to 1 + */ + if (num_of_entries < entries_to_read) { + entries_to_read = num_of_entries; + *eof = 1; + } + + /* + * Down the log buffer mutex to exclude others from reading and + * writing to the log buffer. + */ + if (down_interruptible(¶ms->dptc_log_buffer.mutex)) { + return -EAGAIN; + } + + if (num_of_entries == 0 && offset == 0) { + inc_log_index(¶ms->dptc_log_buffer.tail, -1); + num_of_entries++; + entries_to_read++; + } + + /* get the pointer of the last (oldest) entry in the log buffer */ + entry_ptr = (void *)¶ms->dptc_log_buffer. + entries[params->dptc_log_buffer.tail]; + + /* Check if tail index wraps during current read */ + if ((params->dptc_log_buffer.tail + entries_to_read) < LOG_ENTRIES) { + /* No tail wrap around copy data from log buffer to buf */ + memcpy(buf, entry_ptr, + (entries_to_read * sizeof(dptc_log_entry_s))); + } else { + /* + * Tail wrap around. + * First copy data from current position until end of buffer, + * after that copy the rest from start of the log buffer. + */ + entries_to_end_of_buffer = LOG_ENTRIES - + params->dptc_log_buffer.tail; + memcpy(buf, entry_ptr, + (entries_to_end_of_buffer * sizeof(dptc_log_entry_s))); + + entry_ptr = (void *)¶ms->dptc_log_buffer.entries[0]; + buf_ptr = buf + + (entries_to_end_of_buffer * sizeof(dptc_log_entry_s)); + entries_left = entries_to_read - entries_to_end_of_buffer; + memcpy(buf_ptr, entry_ptr, + (entries_left * sizeof(dptc_log_entry_s))); + } + + /* Increment the tail index by the number of entries read */ + inc_log_index(¶ms->dptc_log_buffer.tail, entries_to_read); + + /* Up the log buffer mutex to allow access to the log buffer */ + up(¶ms->dptc_log_buffer.mutex); + + /* set start of data to point to buf */ + *start = buf; + + return (entries_to_read * sizeof(dptc_log_entry_s)); +} + +/*! + * This function initializes the DPTC log buffer. + * + * @param dptc_log pointer to the DPTC log buffer structure. + * + */ +static void init_dptc_log(dptc_log_s * dptc_log) +{ + dptc_log->tail = 0; + dptc_log->head = 0; + + /* initialize log buffer mutex used for accessing the log buffer */ + sema_init(&dptc_log->mutex, 1); +} + +/*! + * This function initializes the DPTC hardware + * + */ +static int init_dptc_controller(void) +{ + INIT_WORK(&dptc_work, dptc_workqueue_handler); + + if (create_proc_read_entry(PROC_NODE_NAME, 0, + NULL, read_log, &dptc_params) == NULL) { + /* + * Error creating proc file system entry. + * Exit and return error code + */ + printk(KERN_ERR "DPTC: Unable create proc entry"); + return -EFAULT; + } + + /* Initialize the DPTC log buffer */ + init_dptc_log(&dptc_params.dptc_log_buffer); + + init_dptc_wp(); + + /* By default all reference circuits are enabled */ + dptc_params.rc_state = DPTC_REF_CIRCUITS_STATUS; + + dptc_clear_dcr(); + + /* Disable DPTC hardware and mask DPTC interrupt */ + dptc_disable_dptc(); + dptc_mask_dptc_int(); + + printk(KERN_INFO "DPTC controller initialized\n"); + return 0; +} + +/*! + * This function is called to put the DPTC in a low power state. + * + * @param pdev the device structure used to give information on which + * device to suspend (not relevant for DPTC) + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +int mxc_dptc_suspend(struct platform_device *pdev, pm_message_t state) +{ + if (dptc_params.dptc_is_active) { + dptc_disable_dptc(); + set_dptc_wp(dptc_params.dvfs_dptc_tables_ptr->curr_wp - 1); + } + + dptc_params.suspended = 1; + + return 0; +} + +/*! + * This function is called to resume the DPTC from a low power state. + * + * @param pdev the device structure used to give information on which + * device to suspend (not relevant for DPTC) + * + * @return The function always returns 0. + */ +int mxc_dptc_resume(struct platform_device *pdev) +{ + dptc_params.suspended = 0; + + if (dptc_params.dptc_is_active) { + dptc_enable_dptc(); + dptc_unmask_dptc_int(); + } + + return 0; +} + +/*! + * This function frees power management table structures + */ +static void free_dvfs_dptc_table(void) +{ + int i; + + for (i = 0; i < dptc_params.dvfs_dptc_tables_ptr->dvfs_state_num; i++) { + kfree(dptc_params.dvfs_dptc_tables_ptr->dcvr[i]); + } + + kfree(dptc_params.dvfs_dptc_tables_ptr->dcvr); + kfree(dptc_params.dvfs_dptc_tables_ptr->table); + kfree(dptc_params.dvfs_dptc_tables_ptr->wp); + + kfree(dptc_params.dvfs_dptc_tables_ptr); + + dptc_params.dvfs_dptc_tables_ptr = 0; +} + +/* + * DVFS & DPTC table parsing function + * reads the next line of the table in text format + * + * @param str pointer to the previous line + * + * @return pointer to the next line + */ +static char *pm_table_get_next_line(char *str) +{ + char *line_ptr; + int flag = 0; + + if (strlen(str) == 0) + return str; + + line_ptr = strchr(str, '\n') + 1; + + while (!flag) { + if (strlen(line_ptr) == 0) { + flag = 1; + } else if (line_ptr[0] == '\n') { + line_ptr++; + } else if (line_ptr[0] == '#') { + line_ptr = pm_table_get_next_line(line_ptr); + } else { + flag = 1; + } + } + + return line_ptr; +} + +/* + * DVFS & DPTC table parsing function + * sets the values of DVFS & DPTC tables from + * table in text format + * + * @param pm_table pointer to the table in binary format + * @param pm_str pointer to the table in text format + * + * @return 0 on success, error code on failure + */ +static int dvfs_dptc_parse_table(dvfs_dptc_tables_s * pm_table, char *pm_str) +{ + char *pm_str_ptr; + int i, j, n; + dptc_wp *wp; + + pm_str_ptr = pm_str; + + n = sscanf(pm_str_ptr, "WORKING POINT %d\n", &pm_table->wp_num); + + if (n != 1) { + printk(KERN_WARNING "Failed read WORKING POINT number\n"); + return -1; + } + + pm_table->curr_wp = 0; + + pm_str_ptr = pm_table_get_next_line(pm_str_ptr); + pm_table->dvfs_state_num = 1; + + pm_table->wp = + (dptc_wp *) kmalloc(sizeof(dptc_wp) * pm_table->wp_num, GFP_KERNEL); + if (!pm_table->wp) { + printk(KERN_ERR "Failed allocating memory\n"); + return -ENOMEM; + } + + for (i = 0; i < pm_table->wp_num; i++) { + + wp = &pm_table->wp[i]; + + wp->wp_index = i; + + n = sscanf(pm_str_ptr, "WP 0x%x\n", + (unsigned int *)&wp->pmic_values[0]); + + if (n != 1) { + printk(KERN_WARNING "Failed read WP %d\n", i); + kfree(pm_table->wp); + return -1; + } + + pm_str_ptr = pm_table_get_next_line(pm_str_ptr); + + } + + pm_table->table = + (dvfs_state *) kmalloc(sizeof(dvfs_state) * + pm_table->dvfs_state_num, GFP_KERNEL); + + if (!pm_table->table) { + printk(KERN_WARNING "Failed allocating memory\n"); + kfree(pm_table->wp); + return -ENOMEM; + } + + pm_table->dcvr = + (dcvr_state **) kmalloc(sizeof(dcvr_state *) * + pm_table->dvfs_state_num, GFP_KERNEL); + + if (!pm_table->dcvr) { + printk(KERN_WARNING "Failed allocating memory\n"); + kfree(pm_table->table); + kfree(pm_table->wp); + return -ENOMEM; + } + + for (i = 0; i < pm_table->dvfs_state_num; i++) { + pm_table->dcvr[i] = + (dcvr_state *) kmalloc(sizeof(dcvr_state) * + pm_table->wp_num, GFP_KERNEL); + + if (!pm_table->dcvr[i]) { + printk(KERN_WARNING "Failed allocating memory\n"); + + for (j = i - 1; j >= 0; j--) { + kfree(pm_table->dcvr[j]); + } + + kfree(pm_table->dcvr); + return -ENOMEM; + } + + for (j = 0; j < pm_table->wp_num; j++) { + + n = sscanf(pm_str_ptr, "DCVR 0x%x 0x%x 0x%x 0x%x\n", + &pm_table->dcvr[i][j].dcvr_reg[0].AsInt, + &pm_table->dcvr[i][j].dcvr_reg[1].AsInt, + &pm_table->dcvr[i][j].dcvr_reg[2].AsInt, + &pm_table->dcvr[i][j].dcvr_reg[3].AsInt); + + if (n != 4) { + printk(KERN_WARNING "Failed read FREQ %d\n", i); + + for (j = i; j >= 0; j--) { + kfree(pm_table->dcvr[j]); + } + kfree(pm_table->dcvr); + kfree(pm_table->table); + kfree(pm_table->wp); + return -1; + } + + pm_str_ptr = pm_table_get_next_line(pm_str_ptr); + } + } + + return 0; +} + +/* + * Initializes the default values of DVFS & DPTC table + * + * @return 0 on success, error code on failure + */ +static int __init dvfs_dptc_init_default_table(void) +{ + int res = 0; + char *table_str; + + dvfs_dptc_tables_s *default_table; + + default_table = kmalloc(sizeof(dvfs_dptc_tables_s), GFP_KERNEL); + + if (!default_table) { + return -ENOMEM; + } + + table_str = default_table_str; + + memset(default_table, 0, sizeof(dvfs_dptc_tables_s)); + res = dvfs_dptc_parse_table(default_table, table_str); + + if (res == 0) { + dptc_params.dvfs_dptc_tables_ptr = default_table; + } + + return res; +} + +/*! + * This function is called when the driver is opened. This function + * checks if the user that open the device has root privileges. + * + * @param inode Pointer to device inode + * @param filp Pointer to device file structure + * + * @return The function returns 0 on success and a non-zero value on + * failure. + */ +static int dptc_mx27_open(struct inode *inode, struct file *filp) +{ + /* + * check if the program that opened the driver has root + * privileges, if not return error. + */ + if (!capable(CAP_SYS_ADMIN)) { + return -EACCES; + } + + if (dptc_params.suspended) { + return -EPERM; + } + + return 0; +} + +/*! + * This function is called when the driver is close. + * + * @param inode Pointer to device inode + * @param filp Pointer to device file structure + * + * @return The function returns 0 on success and a non-zero value on + * failure. + * + */ +static int dptc_mx27_release(struct inode *inode, struct file *filp) +{ + return 0; +} + +/*! + * This function dumps dptc translation table into string pointer + * + * @param str string pointer + */ +static void dvfs_dptc_dump_table(char *str) +{ + int i, j; + dcvr_state **dcvr_arr; + dcvr_state *dcvr_row; + + memset(str, 0, MAX_TABLE_SIZE); + + sprintf(str, "WORKING POINT %d\n", + dptc_params.dvfs_dptc_tables_ptr->wp_num); + str += strlen(str); + + for (i = 0; i < dptc_params.dvfs_dptc_tables_ptr->wp_num; i++) { + sprintf(str, "WP 0x%x\n", (unsigned int) + dptc_params.dvfs_dptc_tables_ptr->wp[i].pmic_values[0]); + str += strlen(str); + } + + dcvr_arr = dptc_params.dvfs_dptc_tables_ptr->dcvr; + for (i = 0; i < dptc_params.dvfs_dptc_tables_ptr->dvfs_state_num; i++) { + dcvr_row = dcvr_arr[i]; + + for (j = 0; j < dptc_params.dvfs_dptc_tables_ptr->wp_num; j++) { + sprintf(str, + "DCVR 0x%x 0x%x 0x%x 0x%x\n", + dcvr_row[j].dcvr_reg[0].AsInt, + dcvr_row[j].dcvr_reg[1].AsInt, + dcvr_row[j].dcvr_reg[2].AsInt, + dcvr_row[j].dcvr_reg[3].AsInt); + + str += strlen(str); + } + } +} + +/*! + * This function reads DVFS & DPTC translation table from user + * + * @param user_table pointer to user table + * @return 0 on success, error code on failure + */ +static int dvfs_dptc_set_table(char *user_table) +{ + int ret_val = -ENOIOCTLCMD; + char *tmp_str; + char *tmp_str_ptr; + dvfs_dptc_tables_s *dptc_table; + + if (dptc_params.dptc_is_active == TRUE) { + ret_val = -EINVAL; + return ret_val; + } + + tmp_str = vmalloc(MAX_TABLE_SIZE); + + if (tmp_str < 0) { + ret_val = (int)tmp_str; + } else { + memset(tmp_str, 0, MAX_TABLE_SIZE); + tmp_str_ptr = tmp_str; + + /* + * read num_of_wp and dvfs_state_num + * parameters from new table + */ + while (tmp_str_ptr - tmp_str < MAX_TABLE_SIZE && + (!copy_from_user(tmp_str_ptr, user_table, 1)) && + tmp_str_ptr[0] != 0) { + tmp_str_ptr++; + user_table++; + } + if (tmp_str_ptr == tmp_str) { + /* error reading from table */ + printk(KERN_ERR "Failed reading table from user, \ +didn't copy a character\n"); + ret_val = -EFAULT; + } else if (tmp_str_ptr - tmp_str == MAX_TABLE_SIZE) { + /* error reading from table */ + printk(KERN_ERR "Failed reading table from user, \ +read more than %d\n", MAX_TABLE_SIZE); + ret_val = -EFAULT; + } else { + /* + * copy table from user and set it as + * the current DPTC table + */ + dptc_table = kmalloc(sizeof(dvfs_dptc_tables_s), + GFP_KERNEL); + + if (!dptc_table) { + ret_val = -ENOMEM; + } else { + ret_val = + dvfs_dptc_parse_table(dptc_table, tmp_str); + + if (ret_val == 0) { + free_dvfs_dptc_table(); + dptc_params.dvfs_dptc_tables_ptr = + dptc_table; + + set_dptc_wp(dptc_initial_wp); + } + } + + } + + vfree(tmp_str); + } + + return ret_val; +} + +/*! + * This function is called when a ioctl call is made from user space. + * + * @param inode Pointer to device inode + * @param filp Pointer to device file structure + * @param cmd Ioctl command + * @param arg Ioctl argument + * + * Following are the ioctl commands for user to use:\n + * DPTC_IOCTENABLE : Enables the DPTC module.\n + * DPTC_IOCTDISABLE : Disables the DPTC module.\n + * DPTC_IOCSENABLERC : Enables DPTC reference circuits.\n + * DPTC_IOCSDISABLERC : Disables DPTC reference circuits.\n + * DPTC_IOCGETSTATE : Returns 1 if the DPTC module is enabled, + * returns 0 if the DPTC module is disabled.\n + * DPTC_IOCSWP : Sets working point.\n + * PM_IOCSTABLE : Sets translation table.\n + * PM_IOCGTABLE : Gets translation table.\n + * PM_IOCGFREQ : Returns current CPU frequency in Hz + * + * @return The function returns 0 on success and a non-zero value on + * failure. + */ +static int dptc_mx27_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + struct clk *clk; + unsigned int tmp; + int ret_val = -ENOIOCTLCMD; + char *tmp_str; + + tmp = arg; + + if (dptc_params.suspended) { + return -EPERM; + } + + down(&access_mutex); + + pr_debug("DVFS_DPTC ioctl (%d)\n", cmd); + + switch (cmd) { + /* Enable the DPTC module */ + case DPTC_IOCTENABLE: + ret_val = start_dptc(); + break; + + /* Disable the DPTC module */ + case DPTC_IOCTDISABLE: + ret_val = stop_dptc(); + break; + + case DPTC_IOCSENABLERC: + ret_val = enable_ref_circuits(tmp); + break; + + case DPTC_IOCSDISABLERC: + ret_val = disable_ref_circuits(tmp); + break; + /* + * Return the DPTC module current state. + * Returns 1 if the DPTC module is enabled, else returns 0 + */ + case DPTC_IOCGSTATE: + ret_val = dptc_params.dptc_is_active; + break; + case DPTC_IOCSWP: + if (dptc_params.dptc_is_active == FALSE) { + if (arg >= 0 && + arg < dptc_params.dvfs_dptc_tables_ptr->wp_num) { + set_dptc_wp(arg); + ret_val = 0; + } else { + ret_val = -EINVAL; + } + } else { + ret_val = -EINVAL; + } + break; + + /* Update DPTC table */ + case PM_IOCSTABLE: + ret_val = dvfs_dptc_set_table((char *)arg); + break; + + case PM_IOCGTABLE: + tmp_str = vmalloc(MAX_TABLE_SIZE); + if (tmp_str < 0) { + ret_val = (int)tmp_str; + } else { + dvfs_dptc_dump_table(tmp_str); + if (copy_to_user((char *)tmp, tmp_str, strlen(tmp_str))) { + printk(KERN_ERR + "Failed copy %d characters to 0x%x\n", + strlen(tmp_str), tmp); + ret_val = -EFAULT; + } else { + ret_val = 0; + } + vfree(tmp_str); + } + break; + + case PM_IOCGFREQ: + clk = clk_get(NULL, "cpu_clk"); + ret_val = clk_get_rate(clk); + break; + + /* Unknown ioctl command -> return error */ + default: + printk(KERN_ERR "Unknown ioctl command 0x%x\n", cmd); + ret_val = -ENOIOCTLCMD; + } + + up(&access_mutex); + + return ret_val; +} + +/*! + * This function is the DPTC Interrupt handler. + * This function wakes-up the dptc_workqueue_handler function that handles the + * DPTC interrupt. + * + * @param irq The Interrupt number + * @param dev_id Driver private data + * + * @result The function returns \b IRQ_RETVAL(1) if interrupt was handled, + * returns \b IRQ_RETVAL(0) if the interrupt was not handled. + * \b IRQ_RETVAL is defined in include/linux/interrupt.h. + */ +static irqreturn_t dptc_mx27_irq(int irq, void *dev_id) +{ + if (dptc_params.dptc_is_active == TRUE) { + dptc_intr_status = __raw_readl(IO_ADDRESS(MX27_PMCR_BASE_ADDR)); + + /* Acknowledge the interrupt */ + __raw_writel(dptc_intr_status, IO_ADDRESS(MX27_PMCR_BASE_ADDR)); + + /* Extract the interrupt cause */ + dptc_intr_status = + (dptc_intr_status >> MX27_PMCR_LO_INTR_OFFSET) & 0x7; + + if (dptc_intr_status != 0) { + dptc_mask_dptc_int(); + dptc_disable_dptc(); + schedule_work(&dptc_work); + } + } + + return IRQ_RETVAL(1); +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxc_dptc_driver = { + .driver = { + .name = "mxc_dptc", + .bus = &platform_bus_type, + }, + .suspend = mxc_dptc_suspend, + .resume = mxc_dptc_resume, +}; + +/*! + * This is platform device structure for adding MU + */ +static struct platform_device mxc_dptc_device = { + .name = "mxc_dptc", + .id = 0, +}; + +/*! + * This function is called for module initialization. + * It initializes the driver data structures, sets up the DPTC hardware, + * registers the DPTC driver, creates a proc file system read entry and + * attaches the driver to the DPTC interrupt. + * + * @return 0 to indicate success else returns a negative number. + * + */ +static int __init dptc_mx27_init(void) +{ + int res; + struct device *temp_class; + + res = dvfs_dptc_init_default_table(); + + if (res < 0) { + printk(KERN_WARNING "Failed parsing default DPTC table\n"); + return res; + } + + /* Initialize DPTC hardware */ + res = init_dptc_controller(); + if (res < 0) { + free_dvfs_dptc_table(); + } + + /* Initialize internal driver structures */ + dptc_params.dptc_is_active = FALSE; + + /* + * Register DPTC driver as a char driver with an automatically allocated + * major number. + */ + major = register_chrdev(0, DEVICE_NAME, &fops); + + /* + * Return error if a negative major number is returned. + */ + if (major < 0) { + printk(KERN_ERR + "DPTC: Registering driver failed with %d\n", major); + free_dvfs_dptc_table(); + return major; + } + + mxc_dvfs_dptc_class = class_create(THIS_MODULE, DEVICE_NAME); + if (IS_ERR(mxc_dvfs_dptc_class)) { + printk(KERN_ERR "DPTC: Error creating class.\n"); + goto err_out; + } + + temp_class = device_create(mxc_dvfs_dptc_class, NULL, MKDEV(major, 0), + DEVICE_NAME); + if (IS_ERR(temp_class)) { + printk(KERN_ERR "DPTC: Error creating class device.\n"); + goto err_out; + } + + /* request the DPTC interrupt */ + res = request_irq(MXC_INT_CCM, dptc_mx27_irq, 0, DEVICE_NAME, NULL); + + /* + * If res is not 0, then where was an error + * during attaching to DPTC interrupt. + * Exit and return error code. + */ + if (res) { + printk(KERN_ERR "DPTC: Unable to attach to DPTC interrupt"); + free_dvfs_dptc_table(); + goto err_out; + } + + /* Register low power modes functions */ + res = platform_driver_register(&mxc_dptc_driver); + if (res == 0) { + res = platform_device_register(&mxc_dptc_device); + if (res != 0) { + free_dvfs_dptc_table(); + goto err_out; + } + } + + dptc_params.suspended = FALSE; + + return 0; + + err_out: + printk(KERN_WARNING "MX27 DPTC driver was not initialized\n"); + device_destroy(mxc_dvfs_dptc_class, MKDEV(major, 0)); + class_destroy(mxc_dvfs_dptc_class); + unregister_chrdev(major, DEVICE_NAME); + return -1; +} + +/*! + * This function is called whenever the module is removed from the kernel. It + * unregisters the DVFS & DPTC driver from kernel, frees the irq number + * and removes the proc file system entry. + */ +static void __exit dptc_mx27_cleanup(void) +{ + free_dvfs_dptc_table(); + + /* Un-register the driver and remove its node */ + device_destroy(mxc_dvfs_dptc_class, MKDEV(major, 0)); + class_destroy(mxc_dvfs_dptc_class); + unregister_chrdev(major, DEVICE_NAME); + + /* release the DPTC interrupt */ + free_irq(MXC_INT_CCM, NULL); + + /* Unregister low power modes functions */ + platform_driver_unregister(&mxc_dptc_driver); + platform_device_unregister(&mxc_dptc_device); + + /* remove the DPTC proc file system entry */ + remove_proc_entry(PROC_NODE_NAME, NULL); +} + +module_init(dptc_mx27_init); +module_exit(dptc_mx27_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MX27 DPTC driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/pm/dvfs_dptc.h linux-2.6.26-lab126/drivers/mxc/pm/dvfs_dptc.h --- linux-2.6.26/drivers/mxc/pm/dvfs_dptc.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pm/dvfs_dptc.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,83 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dvfs_dptc.h + * + * @brief MXC dvfs & dptc header file. + * + * @ingroup PM_MX27 PM_MX31 PM_MXC91321 + */ +#ifndef __DVFS_DPTC_H__ +#define __DVFS_DPTC_H__ + +#include +#include +#include + +#ifdef CONFIG_ARCH_MX27 +#include +#else +#include +#endif + +#ifdef CONFIG_ARCH_MX3 +#include "dvfs_dptc_table_mx31.h" +#include "dvfs_dptc_table_mx31_27ckih.h" +#include "dvfs_dptc_table_mx31_rev2.h" +#endif +#ifdef CONFIG_ARCH_MXC91321 +#include "dvfs_dptc_table_mxc91321.h" +#endif +#ifdef CONFIG_ARCH_MX27 +#include "dvfs_dptc_table_mx27.h" +#endif + +#ifdef CONFIG_MXC_DVFS +#ifndef CONFIG_MXC_DPTC +/*! + * DPTC Module Name + */ +#define DEVICE_NAME "dvfs" + +/*! + * DPTC driver node Name + */ +#define NODE_NAME "dvfs" +#endif /* ifndef CONFIG_MXC_DPTC */ +#ifdef CONFIG_MXC_DPTC +/*! + * DPTC Module Name + */ +#define DEVICE_NAME "dvfs_dptc" + +/*! + * DPTC driver node Name + */ +#define NODE_NAME "dvfs_dptc" +#endif /* ifdef CONFIG_MXC_DPTC */ +#else /* ifdef CONFIG_MXC_DVFS */ +/*! + * DPTC Module Name + */ +#define DEVICE_NAME "dptc" + +/*! + * DPTC driver node Name + */ +#define NODE_NAME "dptc" +#endif /* ifdef CONFIG_MXC_DVFS */ + +#define MAX_TABLE_SIZE 8192 + +#endif /* __DPTC_H__ */ diff -urN linux-2.6.26/drivers/mxc/pm/dvfs_dptc_table_mx27.h linux-2.6.26-lab126/drivers/mxc/pm/dvfs_dptc_table_mx27.h --- linux-2.6.26/drivers/mxc/pm/dvfs_dptc_table_mx27.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pm/dvfs_dptc_table_mx27.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,69 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dptc.h + * + * @brief i.MX27 dptc table file. + * + * @ingroup PM_MX27 + */ +#ifndef __DVFS_DPTC_TABLE_MX27_H__ +#define __DVFS_DPTC_TABLE_MX27_H__ + +/*! + * Default DPTC table definition + */ +#define NUM_OF_FREQS 1 +#define NUM_OF_WP 17 + +static char *default_table_str = "WORKING POINT 17\n\ +\n\ +WP 0x1c\n\ +WP 0x1b\n\ +WP 0x1a\n\ +WP 0x19\n\ +WP 0x18\n\ +WP 0x17\n\ +WP 0x16\n\ +WP 0x15\n\ +WP 0x14\n\ +WP 0x13\n\ +WP 0x12\n\ +WP 0x11\n\ +WP 0x10\n\ +WP 0xf\n\ +WP 0xe\n\ +WP 0xd\n\ +WP 0xc\n\ +\n\ +DCVR 0xffe00000 0x18e2e85b 0xffe00000 0x25c4688a \n\ +DCVR 0xffe00000 0x18e2e85b 0xffe00000 0x25c4688a \n\ +DCVR 0xffe00000 0x1902e85b 0xffe00000 0x25e4688a \n\ +DCVR 0xffe00000 0x1922e85b 0xffe00000 0x25e4688a \n\ +DCVR 0xffe00000 0x1942ec5b 0xffe00000 0x2604688a \n\ +DCVR 0xffe00000 0x1942ec5b 0xffe00000 0x26646c8a \n\ +DCVR 0xffe00000 0x1962ec5b 0xffe00000 0x26c4708b \n\ +DCVR 0xffe00000 0x1962ec5b 0xffe00000 0x26e4708b \n\ +DCVR 0xffe00000 0x1982f05c 0xffe00000 0x2704748b \n\ +DCVR 0xffe00000 0x19c2f05c 0xffe00000 0x2744748b \n\ +DCVR 0xffe00000 0x1a02f45c 0xffe00000 0x2784788b \n\ +DCVR 0xffe00000 0x1a42f45c 0xffe00000 0x27c47c8b \n\ +DCVR 0xffe00000 0x1a82f85c 0xffe00000 0x2824808c \n\ +DCVR 0xffe00000 0x1aa2f85c 0xffe00000 0x2884848c \n\ +DCVR 0xffe00000 0x1ac2fc5c 0xffe00000 0x28e4888c \n\ +DCVR 0xffe00000 0x1ae2fc5c 0xffe00000 0x2924888c \n\ +DCVR 0xffe00000 0x1b23005d 0xffe00000 0x29648c8c \n\ +"; + +#endif diff -urN linux-2.6.26/drivers/mxc/pmic/Kconfig linux-2.6.26-lab126/drivers/mxc/pmic/Kconfig --- linux-2.6.26/drivers/mxc/pmic/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/Kconfig 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,57 @@ +# +# PMIC device driver configuration +# + +menu "MXC PMIC support" + +config MXC_PMIC + boolean + +config MXC_PMIC_MC13783 + tristate "MC13783 PMIC" + depends on ARCH_MXC && SPI + select MXC_PMIC + ---help--- + This is the MXC MC13783(PMIC) support. It include + ADC, Audio, Battery, Connectivity, Light, Power and RTC. + +config MXC_PMIC_MC13892 + tristate "MC13892 PMIC" + depends on ARCH_MXC && (I2C || SPI) + select MXC_PMIC + ---help--- + This is the MXC MC13892(PMIC) support. It include + ADC, Battery, Connectivity, Light, Power and RTC. + +config MXC_PMIC_I2C + bool "Support PMIC I2C Interface" + depends on MXC_PMIC_MC13892 && I2C + +config MXC_PMIC_SPI + bool "Support PMIC SPI Interface" + depends on (MXC_PMIC_MC13892 || MXC_PMIC_MC13783) && SPI + +config MXC_PMIC_MC34704 + tristate "MC34704 PMIC" + depends on ARCH_MXC && I2C + select MXC_PMIC + ---help--- + This is the MXC MC34704 PMIC support. + +config MXC_PMIC_CHARDEV + tristate "MXC PMIC device interface" + depends on MXC_PMIC + help + Say Y here to use "pmic" device files, found in the /dev directory + on the system. They make it possible to have user-space programs + use or controll PMIC. Mainly its useful for notifying PMIC events + to user-space programs. + +comment "MXC PMIC Client Drivers" + depends on MXC_PMIC + +source "drivers/mxc/pmic/mc13783/Kconfig" + +source "drivers/mxc/pmic/mc13892/Kconfig" + +endmenu diff -urN linux-2.6.26/drivers/mxc/pmic/Makefile linux-2.6.26-lab126/drivers/mxc/pmic/Makefile --- linux-2.6.26/drivers/mxc/pmic/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/Makefile 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,8 @@ +# +# Makefile for the MXC PMIC drivers. +# + +obj-y += core/ +obj-$(CONFIG_MXC_PMIC_MC13783) += mc13783/ +obj-$(CONFIG_MXC_PMIC_MC13892) += mc13892/ + diff -urN linux-2.6.26/drivers/mxc/pmic/core/Makefile linux-2.6.26-lab126/drivers/mxc/pmic/core/Makefile --- linux-2.6.26/drivers/mxc/pmic/core/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/core/Makefile 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,22 @@ +# +# Makefile for the PMIC core drivers. +# +obj-$(CONFIG_MXC_PMIC_MC13783) += pmic_mc13783_mod.o +pmic_mc13783_mod-objs := pmic_external.o pmic_event.o pmic_common.o pmic_core_spi.o mc13783.o + +obj-$(CONFIG_MXC_PMIC_MC13892) += pmic_mc13892_mod.o +pmic_mc13892_mod-objs := pmic_external.o pmic_event.o pmic_common.o mc13892.o + +ifneq ($(CONFIG_MXC_PMIC_SPI),) +pmic_mc13892_mod-objs += pmic_core_spi.o +endif + +ifneq ($(CONFIG_MXC_PMIC_I2C),) +pmic_mc13892_mod-objs += pmic_core_i2c.o +endif + +obj-$(CONFIG_MXC_PMIC_MC34704) += pmic_mc34704_mod.o +pmic_mc34704_mod-objs := pmic_external.o pmic_event.o mc34704.o + +obj-$(CONFIG_MXC_PMIC_CHARDEV) += pmic-dev.o + diff -urN linux-2.6.26/drivers/mxc/pmic/core/mc13783.c linux-2.6.26-lab126/drivers/mxc/pmic/core/mc13783.c --- linux-2.6.26/drivers/mxc/pmic/core/mc13783.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/core/mc13783.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,366 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file pmic/core/mc13783.c + * @brief This file contains MC13783 specific PMIC code. This implementaion + * may differ for each PMIC chip. + * + * @ingroup PMIC_CORE + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "pmic.h" + +/* + * Defines + */ +#define EVENT_MASK_0 0x697fdf +#define EVENT_MASK_1 0x3efffb +#define MXC_PMIC_FRAME_MASK 0x00FFFFFF +#define MXC_PMIC_MAX_REG_NUM 0x3F +#define MXC_PMIC_REG_NUM_SHIFT 0x19 +#define MXC_PMIC_WRITE_BIT_SHIFT 31 + +static unsigned int events_enabled0 = 0; +static unsigned int events_enabled1 = 0; +struct mxc_pmic pmic_drv_data; + +/*! + * This function is called to read a register on PMIC. + * + * @param reg_num number of the pmic register to be read + * @param reg_val return value of register + * + * @return Returns 0 on success -1 on failure. + */ +int pmic_read(unsigned int reg_num, unsigned int *reg_val) +{ + unsigned int frame = 0; + int ret = 0; + + if (reg_num > MXC_PMIC_MAX_REG_NUM) + return PMIC_ERROR; + + frame |= reg_num << MXC_PMIC_REG_NUM_SHIFT; + + ret = spi_rw(pmic_drv_data.spi, (u8 *) & frame, 1); + + *reg_val = frame & MXC_PMIC_FRAME_MASK; + + return ret; +} + +/*! + * This function is called to write a value to the register on PMIC. + * + * @param reg_num number of the pmic register to be written + * @param reg_val value to be written + * + * @return Returns 0 on success -1 on failure. + */ +int pmic_write(int reg_num, const unsigned int reg_val) +{ + unsigned int frame = 0; + int ret = 0; + + if (reg_num > MXC_PMIC_MAX_REG_NUM) + return PMIC_ERROR; + + frame |= (1 << MXC_PMIC_WRITE_BIT_SHIFT); + + frame |= reg_num << MXC_PMIC_REG_NUM_SHIFT; + + frame |= reg_val & MXC_PMIC_FRAME_MASK; + + ret = spi_rw(pmic_drv_data.spi, (u8 *) & frame, 1); + + return ret; +} + +/*! + * This function initializes the SPI device parameters for this PMIC. + * + * @param spi the SPI slave device(PMIC) + * + * @return None + */ +int pmic_spi_setup(struct spi_device *spi) +{ + /* Setup the SPI slave i.e.PMIC */ + pmic_drv_data.spi = spi; + + spi->mode = SPI_MODE_2 | SPI_CS_HIGH; + spi->bits_per_word = 32; + + return spi_setup(spi); +} + +/*! + * This function initializes the PMIC registers. + * + * @return None + */ +int pmic_init_registers(void) +{ + CHECK_ERROR(pmic_write(REG_INTERRUPT_MASK_0, MXC_PMIC_FRAME_MASK)); + CHECK_ERROR(pmic_write(REG_INTERRUPT_MASK_1, MXC_PMIC_FRAME_MASK)); + CHECK_ERROR(pmic_write(REG_INTERRUPT_STATUS_0, MXC_PMIC_FRAME_MASK)); + CHECK_ERROR(pmic_write(REG_INTERRUPT_STATUS_1, MXC_PMIC_FRAME_MASK)); + return PMIC_SUCCESS; +} + +/*! + * This function returns the PMIC version in system. + * + * @param ver pointer to the pmic_version_t structure + * + * @return This function returns PMIC version. + */ +void pmic_get_revision(pmic_version_t * ver) +{ + int rev_id = 0; + int rev1 = 0; + int rev2 = 0; + int finid = 0; + int icid = 0; + + ver->id = PMIC_MC13783; + pmic_read(REG_REVISION, &rev_id); + + rev1 = (rev_id & 0x018) >> 3; + rev2 = (rev_id & 0x007); + icid = (rev_id & 0x01C0) >> 6; + finid = (rev_id & 0x01E00) >> 9; + + /* Ver 0.2 is actually 3.2a. Report as 3.2 */ + if ((rev1 == 0) && (rev2 == 2)) { + rev1 = 3; + } + + if (rev1 == 0 || icid != 2) { + ver->revision = -1; + printk(KERN_NOTICE + "mc13783: Not detected.\tAccess failed\t!!!\n"); + } else { + ver->revision = ((rev1 * 10) + rev2); + printk(KERN_INFO "mc13783 Rev %d.%d FinVer %x detected\n", rev1, + rev2, finid); + } + + return; + +} + +/*! + * This function reads the interrupt status registers of PMIC + * and determine the current active events. + * + * @param active_events array pointer to be used to return active + * event numbers. + * + * @return This function returns PMIC version. + */ +unsigned int pmic_get_active_events(unsigned int *active_events) +{ + unsigned int count = 0; + unsigned int status0, status1; + int bit_set; + + pmic_read(REG_INTERRUPT_STATUS_0, &status0); + pmic_read(REG_INTERRUPT_STATUS_1, &status1); + pmic_write(REG_INTERRUPT_STATUS_0, status0); + pmic_write(REG_INTERRUPT_STATUS_1, status1); + status0 &= events_enabled0; + status1 &= events_enabled1; + + while (status0) { + bit_set = ffs(status0) - 1; + *(active_events + count) = bit_set; + count++; + status0 ^= (1 << bit_set); + } + while (status1) { + bit_set = ffs(status1) - 1; + *(active_events + count) = bit_set + 24; + count++; + status1 ^= (1 << bit_set); + } + + return count; +} + +/*! + * This function unsets a bit in mask register of pmic to unmask an event IT. + * + * @param event the event to be unmasked + * + * @return This function returns PMIC_SUCCESS on SUCCESS, error on FAILURE. + */ +int pmic_event_unmask(type_event event) +{ + unsigned int event_mask = 0; + unsigned int mask_reg = 0; + unsigned int event_bit = 0; + int ret; + + if (event < EVENT_E1HZI) { + mask_reg = REG_INTERRUPT_MASK_0; + event_mask = EVENT_MASK_0; + event_bit = (1 << event); + events_enabled0 |= event_bit; + } else { + event -= 24; + mask_reg = REG_INTERRUPT_MASK_1; + event_mask = EVENT_MASK_1; + event_bit = (1 << event); + events_enabled1 |= event_bit; + } + + if ((event_bit & event_mask) == 0) { + pr_debug("Error: unmasking a reserved/unused event\n"); + return PMIC_ERROR; + } + + ret = pmic_write_reg(mask_reg, 0, event_bit); + + pr_debug("Enable Event : %d\n", event); + + return ret; +} + +/*! + * This function sets a bit in mask register of pmic to disable an event IT. + * + * @param event the event to be masked + * + * @return This function returns PMIC_SUCCESS on SUCCESS, error on FAILURE. + */ +int pmic_event_mask(type_event event) +{ + unsigned int event_mask = 0; + unsigned int mask_reg = 0; + unsigned int event_bit = 0; + int ret; + + if (event < EVENT_E1HZI) { + mask_reg = REG_INTERRUPT_MASK_0; + event_mask = EVENT_MASK_0; + event_bit = (1 << event); + events_enabled0 &= ~event_bit; + } else { + event -= 24; + mask_reg = REG_INTERRUPT_MASK_1; + event_mask = EVENT_MASK_1; + event_bit = (1 << event); + events_enabled1 &= ~event_bit; + } + + if ((event_bit & event_mask) == 0) { + pr_debug("Error: masking a reserved/unused event\n"); + return PMIC_ERROR; + } + + ret = pmic_write_reg(mask_reg, event_bit, event_bit); + + pr_debug("Disable Event : %d\n", event); + + return ret; +} + +/*! + * This function is called to read all sensor bits of PMIC. + * + * @param sensor Sensor to be checked. + * + * @return This function returns true if the sensor bit is high; + * or returns false if the sensor bit is low. + */ +bool pmic_check_sensor(t_sensor sensor) +{ + unsigned int reg_val = 0; + + CHECK_ERROR(pmic_read_reg + (REG_INTERRUPT_SENSE_0, ®_val, PMIC_ALL_BITS)); + + if ((1 << sensor) & reg_val) + return true; + else + return false; +} + +/*! + * This function checks one sensor of PMIC. + * + * @param sensor_bits structure of all sensor bits. + * + * @return This function returns PMIC_SUCCESS on SUCCESS, error on FAILURE. + */ + +PMIC_STATUS pmic_get_sensors(t_sensor_bits * sensor_bits) +{ + int sense_0 = 0; + int sense_1 = 0; + + memset(sensor_bits, 0, sizeof(t_sensor_bits)); + + pmic_read_reg(REG_INTERRUPT_SENSE_0, &sense_0, 0xffffff); + pmic_read_reg(REG_INTERRUPT_SENSE_1, &sense_1, 0xffffff); + + sensor_bits->sense_chgdets = (sense_0 & (1 << 6)) ? true : false; + sensor_bits->sense_chgovs = (sense_0 & (1 << 7)) ? true : false; + sensor_bits->sense_chgrevs = (sense_0 & (1 << 8)) ? true : false; + sensor_bits->sense_chgshorts = (sense_0 & (1 << 9)) ? true : false; + sensor_bits->sense_cccvs = (sense_0 & (1 << 10)) ? true : false; + sensor_bits->sense_chgcurrs = (sense_0 & (1 << 11)) ? true : false; + sensor_bits->sense_bpons = (sense_0 & (1 << 12)) ? true : false; + sensor_bits->sense_lobatls = (sense_0 & (1 << 13)) ? true : false; + sensor_bits->sense_lobaths = (sense_0 & (1 << 14)) ? true : false; + sensor_bits->sense_usb4v4s = (sense_0 & (1 << 16)) ? true : false; + sensor_bits->sense_usb2v0s = (sense_0 & (1 << 17)) ? true : false; + sensor_bits->sense_usb0v8s = (sense_0 & (1 << 18)) ? true : false; + sensor_bits->sense_id_floats = (sense_0 & (1 << 19)) ? true : false; + sensor_bits->sense_id_gnds = (sense_0 & (1 << 20)) ? true : false; + sensor_bits->sense_se1s = (sense_0 & (1 << 21)) ? true : false; + sensor_bits->sense_ckdets = (sense_0 & (1 << 22)) ? true : false; + + sensor_bits->sense_onofd1s = (sense_1 & (1 << 3)) ? true : false; + sensor_bits->sense_onofd2s = (sense_1 & (1 << 4)) ? true : false; + sensor_bits->sense_onofd3s = (sense_1 & (1 << 5)) ? true : false; + sensor_bits->sense_pwrrdys = (sense_1 & (1 << 11)) ? true : false; + sensor_bits->sense_thwarnhs = (sense_1 & (1 << 12)) ? true : false; + sensor_bits->sense_thwarnls = (sense_1 & (1 << 13)) ? true : false; + sensor_bits->sense_clks = (sense_1 & (1 << 14)) ? true : false; + sensor_bits->sense_mc2bs = (sense_1 & (1 << 17)) ? true : false; + sensor_bits->sense_hsdets = (sense_1 & (1 << 18)) ? true : false; + sensor_bits->sense_hsls = (sense_1 & (1 << 19)) ? true : false; + sensor_bits->sense_alspths = (sense_1 & (1 << 20)) ? true : false; + sensor_bits->sense_ahsshorts = (sense_1 & (1 << 21)) ? true : false; + return PMIC_SUCCESS; +} + +EXPORT_SYMBOL(pmic_check_sensor); +EXPORT_SYMBOL(pmic_get_sensors); diff -urN linux-2.6.26/drivers/mxc/pmic/core/mc13892.c linux-2.6.26-lab126/drivers/mxc/pmic/core/mc13892.c --- linux-2.6.26/drivers/mxc/pmic/core/mc13892.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/core/mc13892.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,594 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2009 Amazon Technologies, Inc. All Rights Reserved. + * Manish Lachwani (lachwani@lab126.com) + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file pmic/core/mc13892.c + * @brief This file contains MC13892 specific PMIC code. This implementaion + * may differ for each PMIC chip. + * + * @ingroup PMIC_CORE + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "pmic.h" + +/* + * Defines + */ +#define MC13892_I2C_RETRY_TIMES 10 +#define MXC_PMIC_FRAME_MASK 0x00FFFFFF +#define MXC_PMIC_MAX_REG_NUM 0x3F +#define MXC_PMIC_REG_NUM_SHIFT 0x19 +#define MXC_PMIC_WRITE_BIT_SHIFT 31 + +static unsigned int events_enabled0; +static unsigned int events_enabled1; +static struct mxc_pmic pmic_drv_data; +#ifndef CONFIG_MXC_PMIC_I2C +struct i2c_client *mc13892_client; +#endif + +#define BIT_CHG_CURR_LSH 3 +#define BIT_CHG_CURR_WID 4 +#define PMIC_ICHRG 0x6 +#define VBUSVALIDS 0x08 +#define CHGDETS 0x40 +#define IDFACTORYS 0x10 +#define PMIC_ICHRG_OPEN 0xf /* Externally powered */ +#define PMIC_ICHRG_DEFAULT 0x1 /* Default charging if not open or AC */ + +int pmic_i2c_24bit_read(struct i2c_client *client, unsigned int reg_num, + unsigned int *value) +{ + unsigned char buf[3]; + int ret; + int i; + + memset(buf, 0, 3); + for (i = 0; i < MC13892_I2C_RETRY_TIMES; i++) { + ret = i2c_smbus_read_i2c_block_data(client, reg_num, 3, buf); + if (ret == 3) + break; + msleep(1); + } + + if (ret == 3) { + *value = buf[0] << 16 | buf[1] << 8 | buf[2]; + return ret; + } else { + pr_debug("24bit read error, ret = %d\n", ret); + return -1; /* return -1 on failure */ + } +} + +int pmic_i2c_24bit_write(struct i2c_client *client, + unsigned int reg_num, unsigned int reg_val) +{ + char buf[3]; + int ret; + int i; + + buf[0] = (reg_val >> 16) & 0xff; + buf[1] = (reg_val >> 8) & 0xff; + buf[2] = (reg_val) & 0xff; + + for (i = 0; i < MC13892_I2C_RETRY_TIMES; i++) { + ret = i2c_smbus_write_i2c_block_data(client, reg_num, 3, buf); + if (ret == 0) + break; + msleep(1); + } + + return ret; +} + +int pmic_read(int reg_num, unsigned int *reg_val) +{ + unsigned int frame = 0; + int ret = 0; + + if (pmic_drv_data.spi != NULL) { + if (reg_num > MXC_PMIC_MAX_REG_NUM) + return PMIC_ERROR; + + frame |= reg_num << MXC_PMIC_REG_NUM_SHIFT; + + ret = spi_rw(pmic_drv_data.spi, (u8 *) &frame, 1); + + *reg_val = frame & MXC_PMIC_FRAME_MASK; + } else { + if (mc13892_client == NULL) + return PMIC_ERROR; + + if (pmic_i2c_24bit_read(mc13892_client, reg_num, reg_val) == -1) + return PMIC_ERROR; + } + + return PMIC_SUCCESS; +} + +int pmic_write(int reg_num, const unsigned int reg_val) +{ + unsigned int frame = 0; + int ret = 0; + + if (pmic_drv_data.spi != NULL) { + if (reg_num > MXC_PMIC_MAX_REG_NUM) + return PMIC_ERROR; + + frame |= (1 << MXC_PMIC_WRITE_BIT_SHIFT); + + frame |= reg_num << MXC_PMIC_REG_NUM_SHIFT; + + frame |= reg_val & MXC_PMIC_FRAME_MASK; + + ret = spi_rw(pmic_drv_data.spi, (u8 *) &frame, 1); + + return ret; + } else { + if (mc13892_client == NULL) + return PMIC_ERROR; + + return pmic_i2c_24bit_write(mc13892_client, reg_num, reg_val); + } +} + +/*! + * This function initializes the SPI device parameters for this PMIC. + * + * @param spi the SPI slave device(PMIC) + * + * @return None + */ +int pmic_spi_setup(struct spi_device *spi) +{ + /* Setup the SPI slave i.e.PMIC */ + pmic_drv_data.spi = spi; + + spi->mode = SPI_MODE_2 | SPI_CS_HIGH; + spi->bits_per_word = 32; + + return spi_setup(spi); +} + +static void pmic_set_ichrg(unsigned short curr) +{ + unsigned int mask; + unsigned int value; + + printk(KERN_INFO "Setting ichrg to %d\n", curr); + + /* Turn on CHRGLED */ + pmic_write_reg(REG_CHARGE, (1 << 18), (1 << 18)); + /* Turn on V & I programming */ + pmic_write_reg(REG_CHARGE, (1 << 23), (1 << 23)); + /* Turn off CHGAUTOB */ + pmic_write_reg(REG_CHARGE, (1 << 21), (1 << 21)); + /* Turn off TRICKLE CHARGE */ + pmic_write_reg(REG_CHARGE, (0 << 7), (1 << 7)); + + /* Set the ichrg */ + value = BITFVAL(BIT_CHG_CURR, curr); + mask = BITFMASK(BIT_CHG_CURR); + pmic_write_reg(REG_CHARGE, value, mask); + + /* Restart charging */ + pmic_write_reg(REG_CHARGE, (1 << 20), (1 << 20)); +} + +#ifdef CONFIG_DEBUG_FS + +/*------------------------------------------------------------------------- + Debug filesystem +-------------------------------------------------------------------------*/ +#include +#include + +static struct dentry *debugfs_root; +static struct dentry *debugfs_state; + +#define MC13892_MAX_REGS 63 + +extern pmic_version_t mxc_pmic_version; + +static int mc13892_regs_show(struct seq_file *s, void *p) +{ + int t = 0, i = 0; + int reg_value = 0; + pmic_get_revision(&mxc_pmic_version); + + t += seq_printf(s, "MC13892 Version: %d\n\n", mxc_pmic_version.revision); + + for (i = 0; i <= MC13892_MAX_REGS; i++) { + pmic_read_reg(i, ®_value, 0xffffffff); + t += seq_printf(s, "Reg# %d - 0x%x\n", i, reg_value); + } + + return 0; +} + +static int mc13892_regs_open(struct inode *inode, struct file *file) +{ + return single_open(file, mc13892_regs_show, inode->i_private); +} + +static const struct file_operations mc13892_regs_fops = { + .owner = THIS_MODULE, + .open = mc13892_regs_open, + .llseek = seq_lseek, + .read = seq_read, + .release = single_release, +}; + +static int mc13892_debugfs_init(void) +{ + struct dentry *root, *state; + int ret = -1; + + root = debugfs_create_dir("MC13892", NULL); + if (IS_ERR(root) || !root) + goto err_root; + + state = debugfs_create_file("mc13892_registers", 0400, root, (void *)0, + &mc13892_regs_fops); + + if (!state) + goto err_state; + + debugfs_root = root; + debugfs_state = state; + + return 0; +err_state: + debugfs_remove(root); +err_root: + printk(KERN_ERR "mc13892_regs: debugfs is not available\n"); + return ret; +} + +static void mc13892_cleanup_debugfs(void) +{ + debugfs_remove(debugfs_state); + debugfs_remove(debugfs_root); + debugfs_state = NULL; + debugfs_root = NULL; +} + +#endif + +/*! + * Check if a charger is connected or not + */ +static int pmic_connected_charger(void) +{ + int sense_0 = 0; + int ret = 0; /* Default: no host */ + + pmic_read_reg(REG_INT_SENSE0, &sense_0, 0xffffff); + + if (sense_0 & CHGDETS) + ret = 1; + + return ret; +} + +extern unsigned int usbdr_early_portsc1_read(void); + +static void pmic_enable_green_led(void) +{ + mc13892_bklit_set_current(LIT_GREEN, 0x7); + mc13892_bklit_set_ramp(LIT_GREEN, 0); + mc13892_bklit_set_dutycycle(LIT_GREEN, 0x3f); +} + +int luigi_button_green_led = 0; +EXPORT_SYMBOL(luigi_button_green_led); + +int pmic_init_registers(void) +{ + int sense_0 = 0, idfacs = 0; + + CHECK_ERROR(pmic_write(REG_INT_MASK0, 0xFFFFFF)); + CHECK_ERROR(pmic_write(REG_INT_MASK0, 0xFFFFFF)); + CHECK_ERROR(pmic_write(REG_INT_STATUS0, 0xFFFFFF)); + CHECK_ERROR(pmic_write(REG_INT_STATUS1, 0xFFFFFF)); + /* disable auto charge */ + if (machine_is_mx51_3ds()) + CHECK_ERROR(pmic_write(REG_CHARGE, 0xB40003)); + + /* Turn on support for VSD */ + CHECK_ERROR(pmic_write_reg(REG_MODE_1, 7 << 18, 7 << 18)); + + pmic_read_reg(REG_INT_SENSE0, &sense_0, 0xffffff); + if (sense_0 & IDFACTORYS) + idfacs = 1; + + /* + * Set the ichrg depending on whether booting off the battery + * or not. In factory mode, the board is booted using USB and + * there is no battery. In such a scenario, setting the ichrg to + * 0x3 does not make sense. This is a case where the board is externally + * powered and ichrg should be 0xf + */ + if (idfacs) { + pmic_set_ichrg(PMIC_ICHRG_OPEN); + } + else { + int portsc1 = usbdr_early_portsc1_read(); + printk(KERN_INFO "usbdr_early_portsc1_read: %d\n", portsc1); + + if (pmic_connected_charger() && (portsc1 == 0xc00)) + pmic_set_ichrg(PMIC_ICHRG); + else { + if (!pmic_connected_charger()) { + luigi_button_green_led = 1; + pmic_enable_green_led(); + } + else + pmic_set_ichrg(PMIC_ICHRG_DEFAULT); + } + } + +#ifdef CONFIG_DEBUG_FS + mc13892_debugfs_init(); +#endif + return PMIC_SUCCESS; +} + +void pmic_uninit_registers(void) +{ +#ifdef CONFIG_DEBUG_FS + mc13892_cleanup_debugfs(); +#endif +} + +extern int mxc_spi_suspended; +extern atomic_t mxc_device_suspended; + +unsigned int pmic_get_active_events(unsigned int *active_events) +{ + unsigned int count = 0; + unsigned int status0, status1; + unsigned int cause0 = 0, cause1 = 0; + int bit_set; + + while (mxc_spi_suspended) + yield(); + + pmic_read(REG_INT_STATUS0, &status0); + pmic_read(REG_INT_STATUS1, &status1); + pmic_write(REG_INT_STATUS0, status0); + pmic_write(REG_INT_STATUS1, status1); + status0 &= events_enabled0; + status1 &= events_enabled1; + + /* If the device is suspended, log the wakeup cause */ + if (atomic_read(&mxc_device_suspended)) { + cause0 = status0; + cause1 = status1; + + if (cause1 & 0x2) { + printk(KERN_INFO "kernel: I pmic:wakeup:source=RTC:\n"); + } + + if (cause1 & 0x8) { + printk(KERN_INFO "kernel: I pmic:wakeup:source=Power Button:\n"); + } + + if (cause1 & 0x10) { + printk(KERN_INFO "kernel: I pmic:wakeup:source=TPH:\n"); + } + + if (cause0 & 0x40) { + printk(KERN_INFO "kernel: I pmic:wakeup:source=Charger Plug:\n"); + } + + if (cause0 & 0x4000) { + printk(KERN_INFO "kernel: I pmic:wakeup:source=Lobath:\n"); + } + + /* Reset the flag for the next suspend */ + atomic_set(&mxc_device_suspended, 0); + } + + while (status0) { + bit_set = ffs(status0) - 1; + *(active_events + count) = bit_set; + count++; + status0 ^= (1 << bit_set); + } + while (status1) { + bit_set = ffs(status1) - 1; + *(active_events + count) = bit_set + 24; + count++; + status1 ^= (1 << bit_set); + } + + return count; +} + +#define EVENT_MASK_0 0x387fff +#define EVENT_MASK_1 0x1177fb + +int pmic_event_unmask(type_event event) +{ + unsigned int event_mask = 0; + unsigned int mask_reg = 0; + unsigned int event_bit = 0; + int ret; + + if (event < EVENT_1HZI) { + mask_reg = REG_INT_MASK0; + event_mask = EVENT_MASK_0; + event_bit = (1 << event); + events_enabled0 |= event_bit; + } else { + event -= 24; + mask_reg = REG_INT_MASK1; + event_mask = EVENT_MASK_1; + event_bit = (1 << event); + events_enabled1 |= event_bit; + } + + if ((event_bit & event_mask) == 0) { + pr_debug("Error: unmasking a reserved/unused event\n"); + return PMIC_ERROR; + } + + ret = pmic_write_reg(mask_reg, 0, event_bit); + + pr_debug("Enable Event : %d\n", event); + + return ret; +} + +int pmic_event_mask(type_event event) +{ + unsigned int event_mask = 0; + unsigned int mask_reg = 0; + unsigned int event_bit = 0; + int ret; + + if (event < EVENT_1HZI) { + mask_reg = REG_INT_MASK0; + event_mask = EVENT_MASK_0; + event_bit = (1 << event); + events_enabled0 &= ~event_bit; + } else { + event -= 24; + mask_reg = REG_INT_MASK1; + event_mask = EVENT_MASK_1; + event_bit = (1 << event); + events_enabled1 &= ~event_bit; + } + + if ((event_bit & event_mask) == 0) { + pr_debug("Error: masking a reserved/unused event\n"); + return PMIC_ERROR; + } + + ret = pmic_write_reg(mask_reg, event_bit, event_bit); + + pr_debug("Disable Event : %d\n", event); + + return ret; +} + +/*! + * This function returns the PMIC version in system. + * + * @param ver pointer to the pmic_version_t structure + * + * @return This function returns PMIC version. + */ +void pmic_get_revision(pmic_version_t *ver) +{ + int rev_id = 0; + int rev1 = 0; + int rev2 = 0; + int finid = 0; + int icid = 0; + + ver->id = PMIC_MC13892; + pmic_read(REG_IDENTIFICATION, &rev_id); + + rev1 = (rev_id & 0x018) >> 3; + rev2 = (rev_id & 0x007); + icid = (rev_id & 0x01C0) >> 6; + finid = (rev_id & 0x01E00) >> 9; + + ver->revision = ((rev1 * 10) + rev2); + printk(KERN_INFO "mc13892 Rev %d.%d FinVer %x detected\n", rev1, + rev2, finid); + + pmic_write_reg(REG_MODE_1, 0 << 18, 7 << 18); + mdelay(100); + pmic_write_reg(REG_MODE_1, 7 << 18, 7 << 18); + mdelay(10); + pmic_write_reg(REG_SETTING_1, 7 << 6, 7 << 6); +} + +void mc13892_power_off(void) +{ + unsigned int value; + + pmic_read_reg(REG_POWER_CTL0, &value, 0xffffff); + + value |= 0x000008; + + pmic_write_reg(REG_POWER_CTL0, value, 0xffffff); +} + +/*! + * This function checks one sensor of PMIC. + * + * @param sensor_bits structure of all sensor bits. + * + * @return This function returns PMIC_SUCCESS on SUCCESS, error on FAILURE. + */ +PMIC_STATUS pmic_get_sensors(t_sensor_bits * sensor_bits) +{ + int sense_0 = 0; + int sense_1 = 0; + + memset(sensor_bits, 0, sizeof(t_sensor_bits)); + + pmic_read_reg(REG_INT_SENSE0, &sense_0, 0xffffff); + pmic_read_reg(REG_INT_SENSE1, &sense_1, 0xffffff); + + sensor_bits->sense_vbusvs = (sense_0 & (1 << 3)) ? true : false; + sensor_bits->sense_idfacs = (sense_0 & (1 << 4)) ? true : false; + sensor_bits->sense_usbovs = (sense_0 & (1 << 5)) ? true : false; + sensor_bits->sense_chgdets = (sense_0 & (1 << 6)) ? true : false; + sensor_bits->sense_chgrevs = (sense_0 & (1 << 8)) ? true : false; + sensor_bits->sense_chgrshorts = (sense_0 & (1 << 9)) ? true : false; + sensor_bits->sense_cccvs = (sense_0 & (1 << 10)) ? true : false; + sensor_bits->sense_chgcurrs = (sense_0 & (1 << 11)) ? true : false; + sensor_bits->sense_bpons = (sense_0 & (1 << 12)) ? true : false; + sensor_bits->sense_lobatls = (sense_0 & (1 << 13)) ? true : false; + sensor_bits->sense_lobaths = (sense_0 & (1 << 14)) ? true : false; + sensor_bits->sense_idfloats = (sense_0 & (1 << 19)) ? true : false; + sensor_bits->sense_idgnds = (sense_0 & (1 << 20)) ? true : false; + sensor_bits->sense_se1s = (sense_0 & (1 << 21)) ? true : false; + + sensor_bits->sense_pwron3s = (sense_1 & (1 << 2)) ? true : false; + sensor_bits->sense_pwron1s = (sense_1 & (1 << 3)) ? true : false; + sensor_bits->sense_pwron2s = (sense_1 & (1 << 4)) ? true : false; + sensor_bits->sense_thwarnls = (sense_1 & (1 << 12)) ? true : false; + sensor_bits->sense_thwarnhs = (sense_1 & (1 << 13)) ? true : false; + sensor_bits->sense_clks = (sense_1 & (1 << 14)) ? true : false; + sensor_bits->sense_lbps = (sense_1 & (1 << 15)) ? true : false; + + return PMIC_SUCCESS; +} +EXPORT_SYMBOL(pmic_get_sensors); + diff -urN linux-2.6.26/drivers/mxc/pmic/core/mc34704.c linux-2.6.26-lab126/drivers/mxc/pmic/core/mc34704.c --- linux-2.6.26/drivers/mxc/pmic/core/mc34704.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/core/mc34704.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,314 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file pmic/core/mc34704.c + * @brief This file contains MC34704 specific PMIC code. + * + * @ingroup PMIC_CORE + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pmic.h" + +/* + * Globals + */ +static pmic_version_t mxc_pmic_version = { + .id = PMIC_MC34704, + .revision = 0, +}; +static unsigned int events_enabled; +unsigned int active_events[MAX_ACTIVE_EVENTS]; +struct i2c_client *mc34704_client; +static void pmic_trigger_poll(void); + +#define MAX_MC34704_REG 0x59 +static unsigned int mc34704_reg_readonly[MAX_MC34704_REG / 32 + 1] = { + (1 << 0x03) || (1 << 0x05) || (1 << 0x07) || (1 << 0x09) || + (1 << 0x0B) || (1 << 0x0E) || (1 << 0x11) || (1 << 0x14) || + (1 << 0x17) || (1 << 0x18), + 0, +}; +static unsigned int mc34704_reg_written[MAX_MC34704_REG / 32 + 1]; +static unsigned char mc34704_shadow_regs[MAX_MC34704_REG - 1]; +#define IS_READONLY(r) ((1 << ((r) % 32)) & mc34704_reg_readonly[(r) / 32]) +#define WAS_WRITTEN(r) ((1 << ((r) % 32)) & mc34704_reg_written[(r) / 32]) +#define MARK_WRITTEN(r) do { \ + mc34704_reg_written[(r) / 32] |= (1 << ((r) % 32)); \ +} while (0) + +int pmic_read(int reg_nr, unsigned int *reg_val) +{ + int c; + + /* + * Use the shadow register if we've written to it + */ + if (WAS_WRITTEN(reg_nr)) { + *reg_val = mc34704_shadow_regs[reg_nr]; + return PMIC_SUCCESS; + } + + /* + * Otherwise, actually read the real register. + * Write-only registers will read as zero. + */ + c = i2c_smbus_read_byte_data(mc34704_client, reg_nr); + if (c == -1) { + pr_debug("mc34704: error reading register 0x%02x\n", reg_nr); + return PMIC_ERROR; + } else { + *reg_val = c; + return PMIC_SUCCESS; + } +} + +int pmic_write(int reg_nr, const unsigned int reg_val) +{ + int ret; + + ret = i2c_smbus_write_byte_data(mc34704_client, reg_nr, reg_val); + if (ret == -1) { + return PMIC_ERROR; + } else { + /* + * Update our software copy of the register since you + * can't read what you wrote. + */ + if (!IS_READONLY(reg_nr)) { + mc34704_shadow_regs[reg_nr] = reg_val; + MARK_WRITTEN(reg_nr); + } + return PMIC_SUCCESS; + } +} + +unsigned int pmic_get_active_events(unsigned int *active_events) +{ + unsigned int count = 0; + unsigned int faults; + int bit_set; + + /* Check for any relevant PMIC faults */ + pmic_read(REG_MC34704_FAULTS, &faults); + faults &= events_enabled; + + /* + * Mask all active events, because there is no way to acknowledge + * or dismiss them in the PMIC -- they're sticky. + */ + events_enabled &= ~faults; + + /* Account for all unmasked faults */ + while (faults) { + bit_set = ffs(faults) - 1; + *(active_events + count) = bit_set; + count++; + faults ^= (1 << bit_set); + } + return count; +} + +int pmic_event_unmask(type_event event) +{ + unsigned int event_bit = 0; + unsigned int prior_events = events_enabled; + + event_bit = (1 << event); + events_enabled |= event_bit; + + pr_debug("Enable Event : %d\n", event); + + /* start the polling task as needed */ + if (events_enabled && prior_events == 0) + pmic_trigger_poll(); + + return 0; +} + +int pmic_event_mask(type_event event) +{ + unsigned int event_bit = 0; + + event_bit = (1 << event); + events_enabled &= ~event_bit; + + pr_debug("Disable Event : %d\n", event); + + return 0; +} + +/*! + * PMIC event polling task. This task is called periodically to poll + * for possible MC34704 events (No interrupt supplied by the hardware). + */ +static void pmic_event_task(struct work_struct *work); +DECLARE_DELAYED_WORK(pmic_ws, pmic_event_task); + +static void pmic_trigger_poll(void) +{ + schedule_delayed_work(&pmic_ws, HZ / 10); +} + +static void pmic_event_task(struct work_struct *work) +{ + unsigned int count = 0; + int i; + + count = pmic_get_active_events(active_events); + pr_debug("active events number %d\n", count); + + /* call handlers for all active events */ + for (i = 0; i < count; i++) + pmic_event_callback(active_events[i]); + + /* re-trigger this task, but only if somebody is watching */ + if (events_enabled) + pmic_trigger_poll(); + + return; +} + +pmic_version_t pmic_get_version(void) +{ + return mxc_pmic_version; +} +EXPORT_SYMBOL(pmic_get_version); + +int __devinit pmic_init_registers(void) +{ + /* + * Set some registers to what they should be, + * if for no other reason than to initialize our + * software register copies. + */ + CHECK_ERROR(pmic_write(REG_MC34704_GENERAL2, 0x09)); + CHECK_ERROR(pmic_write(REG_MC34704_VGSET1, 0)); + CHECK_ERROR(pmic_write(REG_MC34704_REG2SET1, 0)); + CHECK_ERROR(pmic_write(REG_MC34704_REG3SET1, 0)); + CHECK_ERROR(pmic_write(REG_MC34704_REG4SET1, 0)); + CHECK_ERROR(pmic_write(REG_MC34704_REG5SET1, 0)); + + return PMIC_SUCCESS; +} + +static int __devinit is_chip_onboard(struct i2c_client *client) +{ + int val; + + /* + * This PMIC has no version or ID register, so just see + * if it ACK's and returns 0 on some write-only register as + * evidence of its presence. + */ + val = i2c_smbus_read_byte_data(client, REG_MC34704_GENERAL2); + if (val != 0) + return -1; + + return 0; +} + +static int __devinit pmic_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret = 0; + + ret = is_chip_onboard(client); + + if (ret == -1) + return -ENODEV; + + mc34704_client = client; + + /* Initialize the PMIC event handling */ + pmic_event_list_init(); + + /* Initialize PMI registers */ + if (pmic_init_registers() != PMIC_SUCCESS) + return PMIC_ERROR; + + /* Tickle the regulator driver */ + reg_mc34704_probe(); + + dev_info(&client->dev, "Loaded\n"); + + return PMIC_SUCCESS; +} + +static int pmic_remove(struct i2c_client *client) +{ + return 0; +} + +static int pmic_suspend(struct i2c_client *client, pm_message_t state) +{ + return 0; +} + +static int pmic_resume(struct i2c_client *client) +{ + return 0; +} + +static const struct i2c_device_id mc34704_id[] = { + {"mc34704", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, mc34704_id); + +static struct i2c_driver pmic_driver = { + .driver = { + .name = "mc34704", + .bus = NULL, + }, + .probe = pmic_probe, + .remove = pmic_remove, + .suspend = pmic_suspend, + .resume = pmic_resume, + .id_table = mc34704_id, +}; + +static int __init pmic_init(void) +{ + return i2c_add_driver(&pmic_driver); +} + +static void __exit pmic_exit(void) +{ + i2c_del_driver(&pmic_driver); +} + +/* + * Module entry points + */ +subsys_initcall_sync(pmic_init); +module_exit(pmic_exit); + +MODULE_DESCRIPTION("MC34704 PMIC driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/pmic/core/pmic-dev.c linux-2.6.26-lab126/drivers/mxc/pmic/core/pmic-dev.c --- linux-2.6.26/drivers/mxc/pmic/core/pmic-dev.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/core/pmic-dev.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,317 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All rights reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file pmic-dev.c + * @brief This provides /dev interface to the user program. They make it + * possible to have user-space programs use or control PMIC. Mainly its + * useful for notifying PMIC events to user-space programs. + * + * @ingroup PMIC_CORE + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define PMIC_NAME "pmic" +#define CIRC_BUF_MAX 16 +#define CIRC_ADD(elem,cir_buf,size) \ + down(&event_mutex); \ + if(CIRC_SPACE(cir_buf.head, cir_buf.tail, size)){ \ + cir_buf.buf[cir_buf.head] = (char)elem; \ + cir_buf.head = (cir_buf.head + 1) & (size - 1); \ + } else { \ + pr_info("Failed to notify event to the user\n");\ + } \ + up(&event_mutex); + +#define CIRC_REMOVE(elem,cir_buf,size) \ + down(&event_mutex); \ + if(CIRC_CNT(cir_buf.head, cir_buf.tail, size)){ \ + elem = (int)cir_buf.buf[cir_buf.tail]; \ + cir_buf.tail = (cir_buf.tail + 1) & (size - 1); \ + } else { \ + elem = -1; \ + pr_info("No valid notified event\n"); \ + } \ + up(&event_mutex); + +static int pmic_major; +static struct class *pmic_class; +static struct fasync_struct *pmic_dev_queue; + +static DECLARE_MUTEX(event_mutex); +static struct circ_buf pmic_events; + +static void callbackfn(void *event) +{ + printk(KERN_INFO "\n\n DETECTED PMIC EVENT : %d\n\n", + (unsigned int)event); +} + +static void user_notify_callback(void *event) +{ + CIRC_ADD((int)event, pmic_events, CIRC_BUF_MAX); + kill_fasync(&pmic_dev_queue, SIGIO, POLL_IN); +} + +/*! + * This function implements IOCTL controls on a PMIC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @param cmd the command + * @param arg the parameter + * @return This function returns 0 if successful. + */ +static int pmic_dev_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + register_info reg_info; + pmic_event_callback_t event_sub; + type_event event; + int ret = 0; + + if (_IOC_TYPE(cmd) != 'P') + return -ENOTTY; + + switch (cmd) { + case PMIC_READ_REG: + if (copy_from_user(®_info, (register_info *) arg, + sizeof(register_info))) { + return -EFAULT; + } + ret = + pmic_read_reg(reg_info.reg, &(reg_info.reg_value), + 0x00ffffff); + pr_debug("read reg %d %x\n", reg_info.reg, reg_info.reg_value); + if (copy_to_user((register_info *) arg, ®_info, + sizeof(register_info))) { + return -EFAULT; + } + break; + + case PMIC_WRITE_REG: + if (copy_from_user(®_info, (register_info *) arg, + sizeof(register_info))) { + return -EFAULT; + } + ret = + pmic_write_reg(reg_info.reg, reg_info.reg_value, + 0x00ffffff); + pr_debug("write reg %d %x\n", reg_info.reg, reg_info.reg_value); + if (copy_to_user((register_info *) arg, ®_info, + sizeof(register_info))) { + return -EFAULT; + } + break; + + case PMIC_SUBSCRIBE: + if (get_user(event, (int __user *)arg)) { + return -EFAULT; + } + event_sub.func = callbackfn; + event_sub.param = (void *)event; + ret = pmic_event_subscribe(event, event_sub); + pr_debug("subscribe done\n"); + break; + + case PMIC_UNSUBSCRIBE: + if (get_user(event, (int __user *)arg)) { + return -EFAULT; + } + event_sub.func = callbackfn; + event_sub.param = (void *)event; + ret = pmic_event_unsubscribe(event, event_sub); + pr_debug("unsubscribe done\n"); + break; + + case PMIC_NOTIFY_USER: + if (get_user(event, (int __user *)arg)) { + return -EFAULT; + } + event_sub.func = user_notify_callback; + event_sub.param = (void *)event; + ret = pmic_event_subscribe(event, event_sub); + break; + + case PMIC_GET_NOTIFY: + CIRC_REMOVE(event, pmic_events, CIRC_BUF_MAX); + if (put_user(event, (int __user *)arg)) { + return -EFAULT; + } + break; + + default: + printk(KERN_ERR "%d unsupported ioctl command\n", (int)cmd); + return -EINVAL; + } + + return ret; +} + +/*! + * This function implements the open method on a PMIC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int pmic_dev_open(struct inode *inode, struct file *file) +{ + pr_debug("open\n"); + return PMIC_SUCCESS; +} + +/*! + * This function implements the release method on a PMIC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * + * @return This function returns 0. + */ +static int pmic_dev_free(struct inode *inode, struct file *file) +{ + pr_debug("free\n"); + return PMIC_SUCCESS; +} + +static int pmic_dev_fasync(int fd, struct file *filp, int mode) +{ + return fasync_helper(fd, filp, mode, &pmic_dev_queue); +} + +/*! + * This structure defines file operations for a PMIC device. + */ +static struct file_operations pmic_fops = { + /*! + * the owner + */ + .owner = THIS_MODULE, + /*! + * the ioctl operation + */ + .ioctl = pmic_dev_ioctl, + /*! + * the open operation + */ + .open = pmic_dev_open, + /*! + * the release operation + */ + .release = pmic_dev_free, + /*! + * the release operation + */ + .fasync = pmic_dev_fasync, +}; + +/*! + * This function implements the init function of the PMIC char device. + * This function is called when the module is loaded. It registers + * the character device for PMIC to be used by user-space programs. + * + * @return This function returns 0. + */ +static int __init pmic_dev_init(void) +{ + int ret = 0; + struct device *pmic_device; + pmic_version_t pmic_ver; + + pmic_ver = pmic_get_version(); + if (pmic_ver.revision < 0) { + printk(KERN_ERR "No PMIC device found\n"); + return -ENODEV; + } + + pmic_major = register_chrdev(0, PMIC_NAME, &pmic_fops); + if (pmic_major < 0) { + printk(KERN_ERR "unable to get a major for pmic\n"); + return pmic_major; + } + + pmic_class = class_create(THIS_MODULE, PMIC_NAME); + if (IS_ERR(pmic_class)) { + printk(KERN_ERR "Error creating pmic class.\n"); + ret = PMIC_ERROR; + goto err; + } + + pmic_device = device_create(pmic_class, NULL, MKDEV(pmic_major, 0), + PMIC_NAME); + if (IS_ERR(pmic_device)) { + printk(KERN_ERR "Error creating pmic class device.\n"); + ret = PMIC_ERROR; + goto err1; + } + + pmic_events.buf = kmalloc(CIRC_BUF_MAX * sizeof(char), GFP_KERNEL); + if (NULL == pmic_events.buf) { + ret = -ENOMEM; + goto err2; + } + pmic_events.head = pmic_events.tail = 0; + + printk(KERN_INFO "PMIC Character device: successfully loaded\n"); + return ret; + err2: + device_destroy(pmic_class, MKDEV(pmic_major, 0)); + err1: + class_destroy(pmic_class); + err: + unregister_chrdev(pmic_major, PMIC_NAME); + return ret; + +} + +/*! + * This function implements the exit function of the PMIC character device. + * This function is called when the module is unloaded. It unregisters + * the PMIC character device. + * + */ +static void __exit pmic_dev_exit(void) +{ + device_destroy(pmic_class, MKDEV(pmic_major, 0)); + class_destroy(pmic_class); + + unregister_chrdev(pmic_major, PMIC_NAME); + + printk(KERN_INFO "PMIC Character device: successfully unloaded\n"); +} + +/* + * Module entry points + */ + +module_init(pmic_dev_init); +module_exit(pmic_dev_exit); + +MODULE_DESCRIPTION("PMIC Protocol /dev entries driver"); +MODULE_AUTHOR("FreeScale"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/pmic/core/pmic.h linux-2.6.26-lab126/drivers/mxc/pmic/core/pmic.h --- linux-2.6.26/drivers/mxc/pmic/core/pmic.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/core/pmic.h 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,139 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __PMIC_H__ +#define __PMIC_H__ + + /*! + * @file pmic.h + * @brief This file contains prototypes of all the functions to be + * defined for each PMIC chip. The implementation of these may differ + * from PMIC chip to PMIC chip. + * + * @ingroup PMIC_CORE + */ + +#include + +#define MAX_ACTIVE_EVENTS 10 + +/*! + * This structure is a way for the PMIC core driver to define their own + * \b spi_device structure. This structure includes the core \b spi_device + * structure that is provided by Linux SPI Framework/driver as an + * element and may contain other elements that are required by core driver. + */ +struct mxc_pmic { + /*! + * Master side proxy for an SPI slave device(PMIC) + */ + struct spi_device *spi; +}; + +/*! + * This function is called to transfer data to PMIC on SPI. + * + * @param spi the SPI slave device(PMIC) + * @param buf the pointer to the data buffer + * @param len the length of the data to be transferred + * + * @return Returns 0 on success -1 on failure. + */ +static inline int spi_rw(struct spi_device *spi, u8 * buf, size_t len) +{ + struct spi_transfer t = { + .tx_buf = (const void *)buf, + .rx_buf = buf, + .len = len, + .cs_change = 0, + .delay_usecs = 0, + }; + struct spi_message m; + + spi_message_init(&m); + spi_message_add_tail(&t, &m); + if (spi_sync(spi, &m) != 0 || m.status != 0) + return PMIC_ERROR; + return (len - m.actual_length); +} + +/*! + * This function returns the PMIC version in system. + * + * @param ver pointer to the pmic_version_t structure + * + * @return This function returns PMIC version. + */ +void pmic_get_revision(pmic_version_t * ver); + +/*! + * This function initializes the SPI device parameters for this PMIC. + * + * @param spi the SPI slave device(PMIC) + * + * @return None + */ +int pmic_spi_setup(struct spi_device *spi); + +/*! + * This function initializes the PMIC registers. + * + * @return None + */ +int pmic_init_registers(void); + +/*! + * This function uninitializes the PMIC registers. + * + * @return None + */ +void pmic_uninit_registers(void); + +/*! + * This function reads the interrupt status registers of PMIC + * and determine the current active events. + * + * @param active_events array pointer to be used to return active + * event numbers. + * + * @return This function returns PMIC version. + */ +unsigned int pmic_get_active_events(unsigned int *active_events); + +/*! + * This function sets a bit in mask register of pmic to disable an event IT. + * + * @param event the event to be masked + * + * @return This function returns PMIC_SUCCESS on SUCCESS, error on FAILURE. + */ +int pmic_event_mask(type_event event); + +/*! + * This function unsets a bit in mask register of pmic to unmask an event IT. + * + * @param event the event to be unmasked + * + * @return This function returns PMIC_SUCCESS on SUCCESS, error on FAILURE. + */ +int pmic_event_unmask(type_event event); + +#ifdef CONFIG_MXC_PMIC_FIXARB +extern PMIC_STATUS pmic_fix_arbitration(struct spi_device *spi); +#else +static inline PMIC_STATUS pmic_fix_arbitration(struct spi_device *spi) +{ + return PMIC_SUCCESS; +} +#endif + +#endif /* __PMIC_H__ */ diff -urN linux-2.6.26/drivers/mxc/pmic/core/pmic_common.c linux-2.6.26-lab126/drivers/mxc/pmic/core/pmic_common.c --- linux-2.6.26/drivers/mxc/pmic/core/pmic_common.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/core/pmic_common.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,99 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file pmic_common.c + * @brief This is the common file for the PMIC Core/Protocol driver. + * + * @ingroup PMIC_CORE + */ + +/* + * Includes + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "pmic.h" + +/* + * Global variables + */ +pmic_version_t mxc_pmic_version; +unsigned int active_events[MAX_ACTIVE_EVENTS]; +struct workqueue_struct *pmic_event_wq; + +void pmic_bh_handler(struct work_struct *work); +/*! + * Bottom half handler of PMIC event handling. + */ +DECLARE_WORK(pmic_ws, pmic_bh_handler); + +/*! + * This function is the bottom half handler of the PMIC interrupt. + * It checks for active events and launches callback for the + * active events. + */ +void pmic_bh_handler(struct work_struct *work) +{ + unsigned int loop; + unsigned int count = 0; + + count = pmic_get_active_events(active_events); + pr_debug("active events number %d\n", count); + + for (loop = 0; loop < count; loop++) + pmic_event_callback(active_events[loop]); + + return; +} + +/*! + * This function is called when pmic interrupt occurs on the processor. + * It is the interrupt handler for the pmic module. + * + * @param irq the irq number + * @param dev_id the pointer on the device + * + * @return The function returns IRQ_HANDLED when handled. + */ +irqreturn_t pmic_irq_handler(int irq, void *dev_id) +{ + /* prepare a task */ + queue_work(pmic_event_wq, &pmic_ws); + + return IRQ_HANDLED; +} + +/*! + * This function is used to determine the PMIC type and its revision. + * + * @return Returns the PMIC type and its revision. + */ + +pmic_version_t pmic_get_version(void) +{ + return mxc_pmic_version; +} +EXPORT_SYMBOL(pmic_get_version); diff -urN linux-2.6.26/drivers/mxc/pmic/core/pmic_core_i2c.c linux-2.6.26-lab126/drivers/mxc/pmic/core/pmic_core_i2c.c --- linux-2.6.26/drivers/mxc/pmic/core/pmic_core_i2c.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/core/pmic_core_i2c.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,320 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file pmic_core_i2c.c + * @brief This is the main file for the PMIC Core/Protocol driver. i2c + * should be providing the interface between the PMIC and the MCU. + * + * @ingroup PMIC_CORE + */ + +/* + * Includes + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "pmic.h" + +#define MC13892_GENERATION_ID_LSH 6 +#define MC13892_IC_ID_LSH 13 + +#define MC13892_GENERATION_ID_WID 3 +#define MC13892_IC_ID_WID 6 + +#define MC13892_GEN_ID_VALUE 0x7 +#define MC13892_IC_ID_VALUE 1 + +/* + * Global variables + */ +struct i2c_client *mc13892_client; + +extern struct workqueue_struct *pmic_event_wq; +extern pmic_version_t mxc_pmic_version; +extern irqreturn_t pmic_irq_handler(int irq, void *dev_id); + +/* + * Platform device structure for PMIC client drivers + */ +static struct platform_device adc_ldm = { + .name = "pmic_adc", + .id = 1, +}; +static struct platform_device battery_ldm = { + .name = "pmic_battery", + .id = 1, +}; +static struct platform_device power_ldm = { + .name = "pmic_power", + .id = 1, +}; +static struct platform_device rtc_ldm = { + .name = "pmic_rtc", + .id = 1, +}; +static struct platform_device light_ldm = { + .name = "pmic_light", + .id = 1, +}; +static struct platform_device rleds_ldm = { + .name = "pmic_leds", + .id = 'r', +}; +static struct platform_device gleds_ldm = { + .name = "pmic_leds", + .id = 'g', +}; +static struct platform_device bleds_ldm = { + .name = "pmic_leds", + .id = 'b', +}; + +static void pmic_pdev_register(void) +{ + platform_device_register(&adc_ldm); + platform_device_register(&battery_ldm); + platform_device_register(&rtc_ldm); + platform_device_register(&power_ldm); + platform_device_register(&light_ldm); + platform_device_register(&rleds_ldm); + platform_device_register(&gleds_ldm); + platform_device_register(&bleds_ldm); +} + +/*! + * This function unregisters platform device structures for + * PMIC client drivers. + */ +static void pmic_pdev_unregister(void) +{ + platform_device_unregister(&adc_ldm); + platform_device_unregister(&battery_ldm); + platform_device_unregister(&rtc_ldm); + platform_device_unregister(&power_ldm); + platform_device_unregister(&light_ldm); +} + +static int __devinit is_chip_onboard(struct i2c_client *client) +{ + unsigned int ret = 0; + + /*bind the right device to the driver */ + if (pmic_i2c_24bit_read(client, REG_IDENTIFICATION, &ret) == -1) + return -1; + + if (MC13892_GEN_ID_VALUE != BITFEXT(ret, MC13892_GENERATION_ID)) { + /*compare the address value */ + dev_err(&client->dev, + "read generation ID 0x%x is not equal to 0x%x!\n", + BITFEXT(ret, MC13892_GENERATION_ID), + MC13892_GEN_ID_VALUE); + return -1; + } + + return 0; +} + +static ssize_t mc13892_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int i, value; + int offset = (REG_TEST4 + 1) / 4; + + for (i = 0; i < offset; i++) { + pmic_read(i, &value); + pr_info("reg%02d: %06x\t\t", i, value); + pmic_read(i + offset, &value); + pr_info("reg%02d: %06x\t\t", i + offset, value); + pmic_read(i + offset * 2, &value); + pr_info("reg%02d: %06x\t\t", i + offset * 2, value); + pmic_read(i + offset * 3, &value); + pr_info("reg%02d: %06x\n", i + offset * 3, value); + } + + return 0; +} + +static ssize_t mc13892_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + int reg, value, ret; + char *p; + + reg = simple_strtoul(buf, NULL, 10); + + p = NULL; + p = memchr(buf, ' ', count); + + if (p == NULL) { + pmic_read(reg, &value); + pr_debug("reg%02d: %06x\n", reg, value); + return count; + } + + p += 1; + + value = simple_strtoul(p, NULL, 16); + + ret = pmic_write(reg, value); + if (ret == 0) + pr_debug("write reg%02d: %06x\n", reg, value); + else + pr_debug("register update failed\n"); + + return count; +} + +static struct device_attribute mc13892_dev_attr = { + .attr = { + .name = "mc13892_ctl", + .mode = S_IRUSR | S_IWUSR, + }, + .show = mc13892_show, + .store = mc13892_store, +}; + +static int __devinit pmic_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret = 0; + int pmic_irq; + + ret = is_chip_onboard(client); + + if (ret == -1) + return -ENODEV; + + /* so far, we got matched chip on board */ + + mc13892_client = client; + + /* Initialize the PMIC event handling */ + pmic_event_list_init(); + + /* Initialize GPIO for PMIC Interrupt */ + gpio_pmic_active(); + + /* Initialize the PMIC parameters */ + ret = pmic_init_registers(); + if (ret != PMIC_SUCCESS) + return PMIC_ERROR; + + pmic_event_wq = create_workqueue("mc13892"); + if (!pmic_event_wq) { + pr_err("mc13892 pmic driver init: fail to create work queue"); + return -EFAULT; + } + + /* Set and install PMIC IRQ handler */ + pmic_irq = (int)(client->dev.platform_data); + if (pmic_irq == 0) + return PMIC_ERROR; + + set_irq_type(IOMUX_TO_IRQ(pmic_irq), IRQF_TRIGGER_RISING); + ret = + request_irq(IOMUX_TO_IRQ(pmic_irq), pmic_irq_handler, 0, "PMIC_IRQ", + 0); + + if (ret) { + dev_err(&client->dev, "request irq %d error!\n", pmic_irq); + return ret; + } + enable_irq_wake(IOMUX_TO_IRQ(pmic_irq)); + + reg_mc13892_probe(); + + ret = device_create_file(&client->dev, &mc13892_dev_attr); + if (ret) + dev_err(&client->dev, "create device file failed!\n"); + + pmic_pdev_register(); + + dev_info(&client->dev, "Loaded\n"); + + return PMIC_SUCCESS; +} + +static int pmic_remove(struct i2c_client *client) +{ + int pmic_irq = (int)(client->dev.platform_data); + + if (pmic_event_wq) + destroy_workqueue(pmic_event_wq); + + free_irq(pmic_irq, 0); + pmic_pdev_unregister(); + return 0; +} + +static int pmic_suspend(struct i2c_client *client, pm_message_t state) +{ + return 0; +} + +static int pmic_resume(struct i2c_client *client) +{ + return 0; +} + +static const struct i2c_device_id mc13892_id[] = { + {"mc13892", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, mc13892_id); + +static struct i2c_driver pmic_driver = { + .driver = { + .name = "mc13892", + .bus = NULL, + }, + .probe = pmic_probe, + .remove = pmic_remove, + .suspend = pmic_suspend, + .resume = pmic_resume, + .id_table = mc13892_id, +}; + +static int __init pmic_init(void) +{ + return i2c_add_driver(&pmic_driver); +} + +static void __exit pmic_exit(void) +{ + i2c_del_driver(&pmic_driver); +} + +/* + * Module entry points + */ +subsys_initcall_sync(pmic_init); +module_exit(pmic_exit); + +MODULE_DESCRIPTION("Core/Protocol driver for PMIC"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/pmic/core/pmic_core_spi.c linux-2.6.26-lab126/drivers/mxc/pmic/core/pmic_core_spi.c --- linux-2.6.26/drivers/mxc/pmic/core/pmic_core_spi.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/core/pmic_core_spi.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,300 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file pmic_core_spi.c + * @brief This is the main file for the PMIC Core/Protocol driver. SPI + * should be providing the interface between the PMIC and the MCU. + * + * @ingroup PMIC_CORE + */ + +/* + * Includes + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "pmic.h" + +/* + * Static functions + */ +static void pmic_pdev_register(void); +static void pmic_pdev_unregister(void); + +/* + * Platform device structure for PMIC client drivers + */ +static struct platform_device adc_ldm = { + .name = "pmic_adc", + .id = 1, +}; +static struct platform_device battery_ldm = { + .name = "pmic_battery", + .id = 1, +}; +static struct platform_device power_ldm = { + .name = "pmic_power", + .id = 1, +}; +static struct platform_device rtc_ldm = { + .name = "pmic_rtc", + .id = 1, +}; +static struct platform_device light_ldm = { + .name = "pmic_light", + .id = 1, +}; +static struct platform_device rleds_ldm = { + .name = "pmic_leds", + .id = 'r', +}; +static struct platform_device gleds_ldm = { + .name = "pmic_leds", + .id = 'g', +}; +static struct platform_device bleds_ldm = { + .name = "pmic_leds", + .id = 'b', +}; + +/* + * External functions + */ +extern void pmic_event_list_init(void); +extern void pmic_event_callback(type_event event); +extern void gpio_pmic_active(void); +extern irqreturn_t pmic_irq_handler(int irq, void *dev_id); +extern pmic_version_t mxc_pmic_version; +extern struct workqueue_struct *pmic_event_wq; + +/*! + * This function registers platform device structures for + * PMIC client drivers. + */ +static void pmic_pdev_register(void) +{ + platform_device_register(&adc_ldm); + platform_device_register(&battery_ldm); + platform_device_register(&rtc_ldm); + platform_device_register(&power_ldm); + platform_device_register(&light_ldm); + platform_device_register(&rleds_ldm); + platform_device_register(&gleds_ldm); + platform_device_register(&bleds_ldm); + reg_mc13783_probe(); + reg_mc13892_probe(); +} + +/*! + * This function unregisters platform device structures for + * PMIC client drivers. + */ +static void pmic_pdev_unregister(void) +{ + platform_device_unregister(&adc_ldm); + platform_device_unregister(&battery_ldm); + platform_device_unregister(&rtc_ldm); + platform_device_unregister(&power_ldm); + platform_device_unregister(&light_ldm); +} + +/*! + * This function puts the SPI slave device in low-power mode/state. + * + * @param spi the SPI slave device + * @param message the power state to enter + * + * @return Returns 0 on SUCCESS and error on FAILURE. + */ +static int pmic_suspend(struct spi_device *spi, pm_message_t message) +{ + return PMIC_SUCCESS; +} + +/*! + * This function brings the SPI slave device back from low-power mode/state. + * + * @param spi the SPI slave device + * + * @return Returns 0 on SUCCESS and error on FAILURE. + */ +static int pmic_resume(struct spi_device *spi) +{ + return PMIC_SUCCESS; +} + +static struct spi_driver pmic_driver; + +/*! + * This function is called whenever the SPI slave device is detected. + * + * @param spi the SPI slave device + * + * @return Returns 0 on SUCCESS and error on FAILURE. + */ +static int __devinit pmic_probe(struct spi_device *spi) +{ + int ret = 0; + + if (!strcmp(spi->dev.bus_id, PMIC_ARBITRATION)) { + if (PMIC_SUCCESS != pmic_fix_arbitration(spi)) { + dev_err((struct device *)spi, + "Unable to fix arbitration!! Access Failed\n"); + return -EACCES; + } + return PMIC_SUCCESS; + } + + /* Initialize the PMIC parameters */ + ret = pmic_spi_setup(spi); + if (ret != PMIC_SUCCESS) { + return PMIC_ERROR; + } + + /* Initialize the PMIC event handling */ + pmic_event_list_init(); + + /* Initialize GPIO for PMIC Interrupt */ + gpio_pmic_active(); + + /* Get the PMIC Version */ + pmic_get_revision(&mxc_pmic_version); + if (mxc_pmic_version.revision < 0) { + dev_err((struct device *)spi, + "PMIC not detected!!! Access Failed\n"); + return -ENODEV; + } else { + dev_dbg((struct device *)spi, + "Detected pmic core IC version number is %d\n", + mxc_pmic_version.revision); + } + + /* Initialize the PMIC parameters */ + ret = pmic_init_registers(); + if (ret != PMIC_SUCCESS) { + return PMIC_ERROR; + } + + pmic_event_wq = create_workqueue("pmic_spi"); + if (!pmic_event_wq) { + pr_err("mc13892 pmic driver init: fail to create work queue"); + return -EFAULT; + } + + /* Set and install PMIC IRQ handler */ + set_irq_type(spi->irq, IRQF_TRIGGER_RISING); + ret = request_irq(spi->irq, pmic_irq_handler, 0, "PMIC_IRQ", 0); + if (ret) { + dev_err((struct device *)spi, "gpio1: irq%d error.", spi->irq); + return ret; + } + + power_ldm.dev.platform_data = spi->dev.platform_data; + + enable_irq_wake(spi->irq); + + pmic_pdev_register(); + + printk(KERN_INFO "Device %s probed\n", spi->dev.bus_id); + + return PMIC_SUCCESS; +} + +/*! + * This function is called whenever the SPI slave device is removed. + * + * @param spi the SPI slave device + * + * @return Returns 0 on SUCCESS and error on FAILURE. + */ +static int __devexit pmic_remove(struct spi_device *spi) +{ + if (pmic_event_wq) + destroy_workqueue(pmic_event_wq); + + free_irq(spi->irq, 0); + + pmic_pdev_unregister(); + pmic_uninit_registers(); + + printk(KERN_INFO "Device %s removed\n", spi->dev.bus_id); + + return PMIC_SUCCESS; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct spi_driver pmic_driver = { + .driver = { + .name = "pmic_spi", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + .probe = pmic_probe, + .remove = __devexit_p(pmic_remove), + .suspend = pmic_suspend, + .resume = pmic_resume, +}; + +/* + * Initialization and Exit + */ + +/*! + * This function implements the init function of the PMIC device. + * This function is called when the module is loaded. It registers + * the PMIC Protocol driver. + * + * @return This function returns 0. + */ +static int __init pmic_init(void) +{ + printk("Registering the PMIC Protocol Driver\n"); + return spi_register_driver(&pmic_driver); +} + +/*! + * This function implements the exit function of the PMIC device. + * This function is called when the module is unloaded. It unregisters + * the PMIC Protocol driver. + * + */ +static void __exit pmic_exit(void) +{ + pr_debug("Unregistering the PMIC Protocol Driver\n"); + spi_unregister_driver(&pmic_driver); +} + +/* + * Module entry points + */ +subsys_initcall_sync(pmic_init); +module_exit(pmic_exit); + +MODULE_DESCRIPTION("Core/Protocol driver for PMIC"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/pmic/core/pmic_event.c linux-2.6.26-lab126/drivers/mxc/pmic/core/pmic_event.c --- linux-2.6.26/drivers/mxc/pmic/core/pmic_event.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/core/pmic_event.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,237 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file pmic_event.c + * @brief This file manage all event of PMIC component. + * + * It contains event subscription, unsubscription and callback + * launch methods implemeted. + * + * @ingroup PMIC_CORE + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "pmic.h" + +/*! + * This structure is used to keep a list of subscribed + * callbacks for an event. + */ +typedef struct { + /*! + * Keeps a list of subscribed clients to an event. + */ + struct list_head list; + + /*! + * Callback function with parameter, called when event occurs + */ + pmic_event_callback_t callback; +} pmic_event_callback_list_t; + +/* Create a mutex to be used to prevent concurrent access to the event list */ +static DECLARE_MUTEX(event_mutex); + +/* This is a pointer to the event handler array. It defines the currently + * active set of events and user-defined callback functions. + */ +static struct list_head pmic_events[PMIC_MAX_EVENTS]; + +/*! + * This function initializes event list for PMIC event handling. + * + */ +void pmic_event_list_init(void) +{ + int i; + + for (i = 0; i < PMIC_MAX_EVENTS; i++) { + INIT_LIST_HEAD(&pmic_events[i]); + } + + sema_init(&event_mutex, 1); + return; +} + +/*! + * This function is used to subscribe on an event. + * + * @param event the event number to be subscribed + * @param callback the callback funtion to be subscribed + * + * @return This function returns 0 on SUCCESS, error on FAILURE. + */ +PMIC_STATUS pmic_event_subscribe(type_event event, + pmic_event_callback_t callback) +{ + pmic_event_callback_list_t *new = NULL; + + pr_debug("Event:%d Subscribe\n", event); + + /* Check whether the event & callback are valid? */ + if (event >= PMIC_MAX_EVENTS) { + pr_debug("Invalid Event:%d\n", event); + return -EINVAL; + } + if (NULL == callback.func) { + pr_debug("Null or Invalid Callback\n"); + return -EINVAL; + } + + /* Create a new linked list entry */ + new = kmalloc(sizeof(pmic_event_callback_list_t), GFP_KERNEL); + if (NULL == new) { + return -ENOMEM; + } + /* Initialize the list node fields */ + new->callback.func = callback.func; + new->callback.param = callback.param; + INIT_LIST_HEAD(&new->list); + + /* Obtain the lock to access the list */ + if (down_interruptible(&event_mutex)) { + kfree(new); + return PMIC_SYSTEM_ERROR_EINTR; + } + + /* Unmask the requested event */ + if (list_empty(&pmic_events[event])) { + if (pmic_event_unmask(event) != PMIC_SUCCESS) { + kfree(new); + up(&event_mutex); + return PMIC_ERROR; + } + } + + /* Add this entry to the event list */ + list_add_tail(&new->list, &pmic_events[event]); + + /* Release the lock */ + up(&event_mutex); + + return PMIC_SUCCESS; +} + +/*! + * This function is used to unsubscribe on an event. + * + * @param event the event number to be unsubscribed + * @param callback the callback funtion to be unsubscribed + * + * @return This function returns 0 on SUCCESS, error on FAILURE. + */ +PMIC_STATUS pmic_event_unsubscribe(type_event event, + pmic_event_callback_t callback) +{ + struct list_head *p; + struct list_head *n; + pmic_event_callback_list_t *temp = NULL; + int ret = PMIC_EVENT_NOT_SUBSCRIBED; + + pr_debug("Event:%d Unsubscribe\n", event); + + /* Check whether the event & callback are valid? */ + if (event >= PMIC_MAX_EVENTS) { + pr_debug("Invalid Event:%d\n", event); + return -EINVAL; + } + + if (NULL == callback.func) { + pr_debug("Null or Invalid Callback\n"); + return -EINVAL; + } + + /* Obtain the lock to access the list */ + if (down_interruptible(&event_mutex)) { + return PMIC_SYSTEM_ERROR_EINTR; + } + + /* Find the entry in the list */ + list_for_each_safe(p, n, &pmic_events[event]) { + temp = list_entry(p, pmic_event_callback_list_t, list); + if (temp->callback.func == callback.func + && temp->callback.param == callback.param) { + /* Remove the entry from the list */ + list_del(p); + kfree(temp); + ret = PMIC_SUCCESS; + break; + } + } + + /* Unmask the requested event */ + if (list_empty(&pmic_events[event])) { + if (pmic_event_mask(event) != PMIC_SUCCESS) { + ret = PMIC_UNSUBSCRIBE_ERROR; + } + } + + /* Release the lock */ + up(&event_mutex); + + return ret; +} + +/*! + * This function calls all callback of a specific event. + * + * @param event the active event number + * + * @return None + */ +void pmic_event_callback(type_event event) +{ + struct list_head *p; + pmic_event_callback_list_t *temp = NULL; + + /* Obtain the lock to access the list */ + if (down_interruptible(&event_mutex)) { + return; + } + + if (list_empty(&pmic_events[event])) { + pr_debug("PMIC Event:%d detected. No callback subscribed\n", + event); + up(&event_mutex); + return; + } + + list_for_each(p, &pmic_events[event]) { + temp = list_entry(p, pmic_event_callback_list_t, list); + temp->callback.func(temp->callback.param); + } + + /* Release the lock */ + up(&event_mutex); + + return; + +} + +EXPORT_SYMBOL(pmic_event_subscribe); +EXPORT_SYMBOL(pmic_event_unsubscribe); diff -urN linux-2.6.26/drivers/mxc/pmic/core/pmic_external.c linux-2.6.26-lab126/drivers/mxc/pmic/core/pmic_external.c --- linux-2.6.26/drivers/mxc/pmic/core/pmic_external.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/core/pmic_external.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,103 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file pmic_external.c + * @brief This file contains all external functions of PMIC drivers. + * + * @ingroup PMIC_CORE + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/* + * External Functions + */ +extern int pmic_read(int reg_num, unsigned int *reg_val); +extern int pmic_write(int reg_num, const unsigned int reg_val); + +/*! + * This function is called by PMIC clients to read a register on PMIC. + * + * @param reg number of register + * @param reg_value return value of register + * @param reg_mask Bitmap mask indicating which bits to modify + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_read_reg(int reg, unsigned int *reg_value, + unsigned int reg_mask) +{ + int ret = 0; + unsigned int temp = 0; + + ret = pmic_read(reg, &temp); + if (ret != PMIC_SUCCESS) { + return PMIC_ERROR; + } + *reg_value = (temp & reg_mask); + + pr_debug("Read REG[ %d ] = 0x%x\n", reg, *reg_value); + + return ret; +} + +/*! + * This function is called by PMIC clients to write a register on PMIC. + * + * @param reg number of register + * @param reg_value New value of register + * @param reg_mask Bitmap mask indicating which bits to modify + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_write_reg(int reg, unsigned int reg_value, + unsigned int reg_mask) +{ + int ret = 0; + unsigned int temp = 0; + + ret = pmic_read(reg, &temp); + if (ret != PMIC_SUCCESS) { + return PMIC_ERROR; + } + temp = (temp & (~reg_mask)) | reg_value; +#ifdef CONFIG_MXC_PMIC_MC13783 + if (reg == REG_POWER_MISCELLANEOUS) + temp &= 0xFFFE7FFF; +#endif + ret = pmic_write(reg, temp); + if (ret != PMIC_SUCCESS) { + return PMIC_ERROR; + } + + pr_debug("Write REG[ %d ] = 0x%x\n", reg, reg_value); + + return ret; +} + +EXPORT_SYMBOL(pmic_read_reg); +EXPORT_SYMBOL(pmic_write_reg); diff -urN linux-2.6.26/drivers/mxc/pmic/mc13783/Kconfig linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/Kconfig --- linux-2.6.26/drivers/mxc/pmic/mc13783/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/Kconfig 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,55 @@ +# +# PMIC Modules configuration +# + +config MXC_MC13783_ADC + tristate "MC13783 ADC support" + depends on MXC_PMIC_MC13783 + ---help--- + This is the MC13783 ADC module driver. This module provides kernel API + for the ADC system of MC13783. + It controls also the touch screen interface. + If you want MC13783 ADC support, you should say Y here + +config MXC_MC13783_AUDIO + tristate "MC13783 Audio support" + depends on MXC_PMIC_MC13783 + ---help--- + This is the MC13783 audio module driver. This module provides kernel API + for audio part of MC13783. + If you want MC13783 audio support, you should say Y here +config MXC_MC13783_RTC + tristate "MC13783 Real Time Clock (RTC) support" + depends on MXC_PMIC_MC13783 + ---help--- + This is the MC13783 RTC module driver. This module provides kernel API + for RTC part of MC13783. + If you want MC13783 RTC support, you should say Y here +config MXC_MC13783_LIGHT + tristate "MC13783 Light and Backlight support" + depends on MXC_PMIC_MC13783 + ---help--- + This is the MC13783 Light module driver. This module provides kernel API + for led and backlight control part of MC13783. + If you want MC13783 Light support, you should say Y here +config MXC_MC13783_BATTERY + tristate "MC13783 Battery API support" + depends on MXC_PMIC_MC13783 + ---help--- + This is the MC13783 battery module driver. This module provides kernel API + for battery control part of MC13783. + If you want MC13783 battery support, you should say Y here +config MXC_MC13783_CONNECTIVITY + tristate "MC13783 Connectivity API support" + depends on MXC_PMIC_MC13783 + ---help--- + This is the MC13783 connectivity module driver. This module provides kernel API + for USB/RS232 connectivity control part of MC13783. + If you want MC13783 connectivity support, you should say Y here +config MXC_MC13783_POWER + tristate "MC13783 Power API support" + depends on MXC_PMIC_MC13783 + ---help--- + This is the MC13783 power and supplies module driver. This module provides kernel API + for power and regulator control part of MC13783. + If you want MC13783 power support, you should say Y here diff -urN linux-2.6.26/drivers/mxc/pmic/mc13783/Makefile linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/Makefile --- linux-2.6.26/drivers/mxc/pmic/mc13783/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/Makefile 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,18 @@ +# +# Makefile for the mc13783 pmic drivers. +# + +obj-$(CONFIG_MXC_MC13783_ADC) += pmic_adc-mod.o +obj-$(CONFIG_MXC_MC13783_AUDIO) += pmic_audio-mod.o +obj-$(CONFIG_MXC_MC13783_RTC) += pmic_rtc-mod.o +obj-$(CONFIG_MXC_MC13783_LIGHT) += pmic_light-mod.o +obj-$(CONFIG_MXC_MC13783_BATTERY) += pmic_battery-mod.o +obj-$(CONFIG_MXC_MC13783_CONNECTIVITY) += pmic_convity-mod.o +obj-$(CONFIG_MXC_MC13783_POWER) += pmic_power-mod.o +pmic_adc-mod-objs := pmic_adc.o +pmic_audio-mod-objs := pmic_audio.o +pmic_rtc-mod-objs := pmic_rtc.o +pmic_light-mod-objs := pmic_light.o +pmic_battery-mod-objs := pmic_battery.o +pmic_convity-mod-objs := pmic_convity.o +pmic_power-mod-objs := pmic_power.o diff -urN linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_adc.c linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_adc.c --- linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_adc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_adc.c 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,1544 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_adc.c + * @brief This is the main file of PMIC(mc13783) ADC driver. + * + * @ingroup PMIC_ADC + */ + +/* + * Includes + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "../core/pmic.h" +#include "pmic_adc_defs.h" + +#define NB_ADC_REG 5 + +static int pmic_adc_major; + +/* internal function */ +static void callback_tsi(void *); +static void callback_adcdone(void *); +static void callback_adcbisdone(void *); +static void callback_adc_comp_high(void *); + +/*! + * Number of users waiting in suspendq + */ +static int swait = 0; + +/*! + * To indicate whether any of the adc devices are suspending + */ +static int suspend_flag = 0; + +/*! + * The suspendq is used by blocking application calls + */ +static wait_queue_head_t suspendq; + +static struct class *pmic_adc_class; + +/* + * ADC mc13783 API + */ +/* EXPORTED FUNCTIONS */ +EXPORT_SYMBOL(pmic_adc_init); +EXPORT_SYMBOL(pmic_adc_deinit); +EXPORT_SYMBOL(pmic_adc_convert); +EXPORT_SYMBOL(pmic_adc_convert_8x); +EXPORT_SYMBOL(pmic_adc_convert_multichnnel); +EXPORT_SYMBOL(pmic_adc_set_touch_mode); +EXPORT_SYMBOL(pmic_adc_get_touch_mode); +EXPORT_SYMBOL(pmic_adc_get_touch_sample); +EXPORT_SYMBOL(pmic_adc_get_battery_current); +EXPORT_SYMBOL(pmic_adc_active_comparator); +EXPORT_SYMBOL(pmic_adc_deactive_comparator); + +static DECLARE_COMPLETION(adcdone_it); +static DECLARE_COMPLETION(adcbisdone_it); +static DECLARE_COMPLETION(adc_tsi); +static pmic_event_callback_t tsi_event; +static pmic_event_callback_t event_adc; +static pmic_event_callback_t event_adc_bis; +static pmic_event_callback_t adc_comp_h; +static bool data_ready_adc_1; +static bool data_ready_adc_2; +static bool adc_ts; +static bool wait_ts; +static bool monitor_en; +static bool monitor_adc; +static t_check_mode wcomp_mode; +static DECLARE_MUTEX(convert_mutex); + +void (*monitoring_cb) (void); /*call back to be called when event is detected. */ + +static DECLARE_WAIT_QUEUE_HEAD(queue_adc_busy); +static t_adc_state adc_dev[2]; + +static unsigned channel_num[] = { + 0, + 1, + 3, + 4, + 2, + 12, + 13, + 14, + 15, + -1, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 7, + 6, + -1, + -1, + -1, + -1, + 5, + 7 +}; + +static bool pmic_adc_ready; + +int is_pmic_adc_ready() +{ + return pmic_adc_ready; +} +EXPORT_SYMBOL(is_pmic_adc_ready); + + +/*! + * This is the suspend of power management for the mc13783 ADC API. + * It supports SAVE and POWER_DOWN state. + * + * @param pdev the device + * @param state the state + * + * @return This function returns 0 if successful. + */ +static int pmic_adc_suspend(struct platform_device *pdev, pm_message_t state) +{ + unsigned int reg_value = 0; + suspend_flag = 1; + CHECK_ERROR(pmic_write_reg(REG_ADC_0, DEF_ADC_0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_1, reg_value, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_2, reg_value, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_3, DEF_ADC_3, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_4, reg_value, PMIC_ALL_BITS)); + + return 0; +}; + +/*! + * This is the resume of power management for the mc13783 adc API. + * It supports RESTORE state. + * + * @param pdev the device + * + * @return This function returns 0 if successful. + */ +static int pmic_adc_resume(struct platform_device *pdev) +{ + /* nothing for mc13783 adc */ + unsigned int adc_0_reg, adc_1_reg; + suspend_flag = 0; + + /* let interrupt of TSI again */ + adc_0_reg = ADC_WAIT_TSI_0; + CHECK_ERROR(pmic_write_reg(REG_ADC_0, adc_0_reg, PMIC_ALL_BITS)); + adc_1_reg = ADC_WAIT_TSI_1 | (ADC_BIS * adc_ts); + CHECK_ERROR(pmic_write_reg(REG_ADC_1, adc_1_reg, PMIC_ALL_BITS)); + + while (swait > 0) { + swait--; + wake_up_interruptible(&suspendq); + } + + return 0; +}; + +/* + * Call back functions + */ + +/*! + * This is the callback function called on TSI mc13783 event, used in synchronous call. + */ +static void callback_tsi(void *unused) +{ + pr_debug("*** TSI IT mc13783 PMIC_ADC_GET_TOUCH_SAMPLE ***\n"); + if (wait_ts) { + complete(&adc_tsi); + pmic_event_mask(EVENT_TSI); + } +} + +/*! + * This is the callback function called on ADCDone mc13783 event. + */ +static void callback_adcdone(void *unused) +{ + if (data_ready_adc_1) { + complete(&adcdone_it); + } +} + +/*! + * This is the callback function called on ADCDone mc13783 event. + */ +static void callback_adcbisdone(void *unused) +{ + pr_debug("* adcdone bis it callback *\n"); + if (data_ready_adc_2) { + complete(&adcbisdone_it); + } +} + +/*! + * This is the callback function called on mc13783 event. + */ +static void callback_adc_comp_high(void *unused) +{ + pr_debug("* adc comp it high *\n"); + if (wcomp_mode == CHECK_HIGH || wcomp_mode == CHECK_LOW_OR_HIGH) { + /* launch callback */ + if (monitoring_cb != NULL) { + monitoring_cb(); + } + } +} + +/*! + * This function performs filtering and rejection of excessive noise prone + * samples. + * + * @param ts_curr Touch screen value + * + * @return This function returns 0 on success, -1 otherwise. + */ +static int pmic_adc_filter(t_touch_screen * ts_curr) +{ + unsigned int ydiff1, ydiff2, ydiff3, xdiff1, xdiff2, xdiff3; + unsigned int sample_sumx, sample_sumy; + static unsigned int prev_x[FILTLEN], prev_y[FILTLEN]; + int index = 0; + unsigned int y_curr, x_curr; + static int filt_count = 0; + /* Added a variable filt_type to decide filtering at run-time */ + unsigned int filt_type = 0; + + if (ts_curr->contact_resistance == 0) { + ts_curr->x_position = 0; + ts_curr->y_position = 0; + filt_count = 0; + return 0; + } + + ydiff1 = abs(ts_curr->y_position1 - ts_curr->y_position2); + ydiff2 = abs(ts_curr->y_position2 - ts_curr->y_position3); + ydiff3 = abs(ts_curr->y_position1 - ts_curr->y_position3); + if ((ydiff1 > DELTA_Y_MAX) || + (ydiff2 > DELTA_Y_MAX) || (ydiff3 > DELTA_Y_MAX)) { + pr_debug("pmic_adc_filter: Ret pos 1\n"); + return -1; + } + + xdiff1 = abs(ts_curr->x_position1 - ts_curr->x_position2); + xdiff2 = abs(ts_curr->x_position2 - ts_curr->x_position3); + xdiff3 = abs(ts_curr->x_position1 - ts_curr->x_position3); + + if ((xdiff1 > DELTA_X_MAX) || + (xdiff2 > DELTA_X_MAX) || (xdiff3 > DELTA_X_MAX)) { + pr_debug("mc13783_adc_filter: Ret pos 2\n"); + return -1; + } + /* Compute two closer values among the three available Y readouts */ + + if (ydiff1 < ydiff2) { + if (ydiff1 < ydiff3) { + // Sample 0 & 1 closest together + sample_sumy = ts_curr->y_position1 + + ts_curr->y_position2; + } else { + // Sample 0 & 2 closest together + sample_sumy = ts_curr->y_position1 + + ts_curr->y_position3; + } + } else { + if (ydiff2 < ydiff3) { + // Sample 1 & 2 closest together + sample_sumy = ts_curr->y_position2 + + ts_curr->y_position3; + } else { + // Sample 0 & 2 closest together + sample_sumy = ts_curr->y_position1 + + ts_curr->y_position3; + } + } + + /* + * Compute two closer values among the three available X + * readouts + */ + if (xdiff1 < xdiff2) { + if (xdiff1 < xdiff3) { + // Sample 0 & 1 closest together + sample_sumx = ts_curr->x_position1 + + ts_curr->x_position2; + } else { + // Sample 0 & 2 closest together + sample_sumx = ts_curr->x_position1 + + ts_curr->x_position3; + } + } else { + if (xdiff2 < xdiff3) { + // Sample 1 & 2 closest together + sample_sumx = ts_curr->x_position2 + + ts_curr->x_position3; + } else { + // Sample 0 & 2 closest together + sample_sumx = ts_curr->x_position1 + + ts_curr->x_position3; + } + } + /* + * Wait FILTER_MIN_DELAY number of samples to restart + * filtering + */ + if (filt_count < FILTER_MIN_DELAY) { + /* + * Current output is the average of the two closer + * values and no filtering is used + */ + y_curr = (sample_sumy / 2); + x_curr = (sample_sumx / 2); + ts_curr->y_position = y_curr; + ts_curr->x_position = x_curr; + filt_count++; + } else { + if (abs(sample_sumx - (prev_x[0] + prev_x[1])) > + (DELTA_X_MAX * 16)) { + pr_debug("pmic_adc_filter: : Ret pos 3\n"); + return -1; + } + if (abs(sample_sumy - (prev_y[0] + prev_y[1])) > + (DELTA_Y_MAX * 16)) { + return -1; + } + sample_sumy /= 2; + sample_sumx /= 2; + /* Use hard filtering if the sample difference < 10 */ + if ((abs(sample_sumy - prev_y[0]) > 10) || + (abs(sample_sumx - prev_x[0]) > 10)) { + filt_type = 1; + } + + /* + * Current outputs are the average of three previous + * values and the present readout + */ + y_curr = sample_sumy; + for (index = 0; index < FILTLEN; index++) { + if (filt_type == 0) { + y_curr = y_curr + (prev_y[index]); + } else { + y_curr = y_curr + (prev_y[index] / 3); + } + } + if (filt_type == 0) { + y_curr = y_curr >> 2; + } else { + y_curr = y_curr >> 1; + } + ts_curr->y_position = y_curr; + + x_curr = sample_sumx; + for (index = 0; index < FILTLEN; index++) { + if (filt_type == 0) { + x_curr = x_curr + (prev_x[index]); + } else { + x_curr = x_curr + (prev_x[index] / 3); + } + } + if (filt_type == 0) { + x_curr = x_curr >> 2; + } else { + x_curr = x_curr >> 1; + } + ts_curr->x_position = x_curr; + + } + + /* Update previous X and Y values */ + for (index = (FILTLEN - 1); index > 0; index--) { + prev_x[index] = prev_x[index - 1]; + prev_y[index] = prev_y[index - 1]; + } + + /* + * Current output will be the most recent past for the + * next sample + */ + prev_y[0] = y_curr; + prev_x[0] = x_curr; + + return 0; +} + +/*! + * This function implements the open method on a MC13783 ADC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int pmic_adc_open(struct inode *inode, struct file *file) +{ + while (suspend_flag == 1) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, (suspend_flag == 0))) { + return -ERESTARTSYS; + } + } + pr_debug("mc13783_adc : mc13783_adc_open()\n"); + return 0; +} + +/*! + * This function implements the release method on a MC13783 ADC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int pmic_adc_free(struct inode *inode, struct file *file) +{ + pr_debug("mc13783_adc : mc13783_adc_free()\n"); + return 0; +} + +/*! + * This function initializes all ADC registers with default values. This + * function also registers the interrupt events. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +int pmic_adc_init(void) +{ + unsigned int reg_value = 0, i = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + for (i = 0; i < ADC_NB_AVAILABLE; i++) { + adc_dev[i] = ADC_FREE; + } + CHECK_ERROR(pmic_write_reg(REG_ADC_0, DEF_ADC_0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_1, reg_value, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_2, reg_value, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_3, DEF_ADC_3, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_4, reg_value, PMIC_ALL_BITS)); + reg_value = 0x001000; + CHECK_ERROR(pmic_write_reg(REG_ARBITRATION_PERIPHERAL_AUDIO, reg_value, + 0xFFFFFF)); + + data_ready_adc_1 = false; + data_ready_adc_2 = false; + adc_ts = false; + wait_ts = false; + monitor_en = false; + monitor_adc = false; + wcomp_mode = CHECK_LOW; + monitoring_cb = NULL; + /* sub to ADCDone IT */ + event_adc.param = NULL; + event_adc.func = callback_adcdone; + CHECK_ERROR(pmic_event_subscribe(EVENT_ADCDONEI, event_adc)); + + /* sub to ADCDoneBis IT */ + event_adc_bis.param = NULL; + event_adc_bis.func = callback_adcbisdone; + CHECK_ERROR(pmic_event_subscribe(EVENT_ADCBISDONEI, event_adc_bis)); + + /* sub to Touch Screen IT */ + tsi_event.param = NULL; + tsi_event.func = callback_tsi; + CHECK_ERROR(pmic_event_subscribe(EVENT_TSI, tsi_event)); + + /* ADC reading above high limit */ + adc_comp_h.param = NULL; + adc_comp_h.func = callback_adc_comp_high; + CHECK_ERROR(pmic_event_subscribe(EVENT_WHIGHI, adc_comp_h)); + + return PMIC_SUCCESS; +} + +/*! + * This function disables the ADC, de-registers the interrupt events. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_deinit(void) +{ + CHECK_ERROR(pmic_event_unsubscribe(EVENT_ADCDONEI, event_adc)); + CHECK_ERROR(pmic_event_unsubscribe(EVENT_ADCBISDONEI, event_adc_bis)); + CHECK_ERROR(pmic_event_unsubscribe(EVENT_TSI, tsi_event)); + CHECK_ERROR(pmic_event_unsubscribe(EVENT_WHIGHI, adc_comp_h)); + + return PMIC_SUCCESS; +} + +/*! + * This function initializes adc_param structure. + * + * @param adc_param Structure to be initialized. + * + * @return This function returns 0 if successful. + */ +int mc13783_adc_init_param(t_adc_param * adc_param) +{ + int i = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + adc_param->delay = 0; + adc_param->conv_delay = false; + adc_param->single_channel = false; + adc_param->group = false; + adc_param->channel_0 = BATTERY_VOLTAGE; + adc_param->channel_1 = BATTERY_VOLTAGE; + adc_param->read_mode = 0; + adc_param->wait_tsi = 0; + adc_param->chrgraw_devide_5 = true; + adc_param->read_ts = false; + adc_param->ts_value.x_position = 0; + adc_param->ts_value.y_position = 0; + adc_param->ts_value.contact_resistance = 0; + for (i = 0; i <= MAX_CHANNEL; i++) { + adc_param->value[i] = 0; + } + return 0; +} + +/*! + * This function starts the convert. + * + * @param adc_param contains all adc configuration and return value. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS mc13783_adc_convert(t_adc_param * adc_param) +{ + bool use_bis = false; + unsigned int adc_0_reg = 0, adc_1_reg = 0, reg_1 = 0, result_reg = + 0, i = 0; + unsigned int result = 0, temp = 0; + pmic_version_t mc13783_ver; + pr_debug("mc13783 ADC - mc13783_adc_convert ....\n"); + if (suspend_flag == 1) { + return -EBUSY; + } + + if (adc_param->wait_tsi) { + /* we need to set ADCEN 1 for TSI interrupt on mc13783 1.x */ + /* configure adc to wait tsi interrupt */ + INIT_COMPLETION(adc_tsi); + pr_debug("mc13783 ADC - pmic_write_reg ....\n"); + /*for ts don't use bis */ + adc_0_reg = 0x001c00 | (ADC_BIS * 0); + pmic_event_unmask(EVENT_TSI); + CHECK_ERROR(pmic_write_reg + (REG_ADC_0, adc_0_reg, PMIC_ALL_BITS)); + /*for ts don't use bis */ + adc_1_reg = 0x200001 | (ADC_BIS * 0); + CHECK_ERROR(pmic_write_reg + (REG_ADC_1, adc_1_reg, PMIC_ALL_BITS)); + pr_debug("wait tsi ....\n"); + wait_ts = true; + wait_for_completion_interruptible(&adc_tsi); + wait_ts = false; + } + if (adc_param->read_ts == false) + down(&convert_mutex); + use_bis = mc13783_adc_request(adc_param->read_ts); + if (use_bis < 0) { + pr_debug("process has received a signal and got interrupted\n"); + return -EINTR; + } + + /* CONFIGURE ADC REG 0 */ + adc_0_reg = 0; + adc_1_reg = 0; + if (adc_param->read_ts == false) { + adc_0_reg = adc_param->read_mode & 0x00003F; + /* add auto inc */ + adc_0_reg |= ADC_INC; + if (use_bis) { + /* add adc bis */ + adc_0_reg |= ADC_BIS; + } + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + if (adc_param->chrgraw_devide_5) { + adc_0_reg |= ADC_CHRGRAW_D5; + } + } + if (adc_param->single_channel) { + adc_1_reg |= ADC_SGL_CH; + } + + if (adc_param->conv_delay) { + adc_1_reg |= ADC_ATO; + } + + if (adc_param->group) { + adc_1_reg |= ADC_ADSEL; + } + + if (adc_param->single_channel) { + adc_1_reg |= ADC_SGL_CH; + } + + adc_1_reg |= (adc_param->channel_0 << ADC_CH_0_POS) & + ADC_CH_0_MASK; + adc_1_reg |= (adc_param->channel_1 << ADC_CH_1_POS) & + ADC_CH_1_MASK; + } else { + adc_0_reg = 0x003c00 | (ADC_BIS * use_bis) | ADC_INC; + } + pr_debug("Write Reg %i = %x\n", REG_ADC_0, adc_0_reg); + /*Change has been made here */ + CHECK_ERROR(pmic_write_reg(REG_ADC_0, adc_0_reg, + ADC_INC | ADC_BIS | ADC_CHRGRAW_D5 | + 0xfff00ff)); + /* CONFIGURE ADC REG 1 */ + if (adc_param->read_ts == false) { + adc_1_reg |= ADC_NO_ADTRIG; + adc_1_reg |= ADC_EN; + adc_1_reg |= (adc_param->delay << ADC_DELAY_POS) & + ADC_DELAY_MASK; + if (use_bis) { + adc_1_reg |= ADC_BIS; + } + } else { + /* configure and start convert to read x and y position */ + /* configure to read 2 value in channel selection 1 & 2 */ + adc_1_reg = 0x100409 | (ADC_BIS * use_bis) | ADC_NO_ADTRIG; + } + reg_1 = adc_1_reg; + if (use_bis == 0) { + data_ready_adc_1 = false; + adc_1_reg |= ASC_ADC; + data_ready_adc_1 = true; + pr_debug("Write Reg %i = %x\n", REG_ADC_1, adc_1_reg); + INIT_COMPLETION(adcdone_it); + CHECK_ERROR(pmic_write_reg(REG_ADC_1, adc_1_reg, + ADC_SGL_CH | ADC_ATO | ADC_ADSEL + | ADC_CH_0_MASK | ADC_CH_1_MASK | + ADC_NO_ADTRIG | ADC_EN | + ADC_DELAY_MASK | ASC_ADC | ADC_BIS)); + pr_debug("wait adc done \n"); + wait_for_completion_interruptible(&adcdone_it); + data_ready_adc_1 = false; + } else { + data_ready_adc_2 = false; + adc_1_reg |= ASC_ADC; + data_ready_adc_2 = true; + INIT_COMPLETION(adcbisdone_it); + CHECK_ERROR(pmic_write_reg(REG_ADC_1, adc_1_reg, 0xFFFFFF)); + temp = 0x800000; + CHECK_ERROR(pmic_write_reg(REG_ADC_3, temp, 0xFFFFFF)); + temp = 0x001000; + pmic_write_reg(REG_ARBITRATION_PERIPHERAL_AUDIO, temp, + 0xFFFFFF); + pr_debug("wait adc done bis\n"); + wait_for_completion_interruptible(&adcbisdone_it); + data_ready_adc_2 = false; + } + /* read result and store in adc_param */ + result = 0; + if (use_bis == 0) { + result_reg = REG_ADC_2; + } else { + result_reg = REG_ADC_4; + } + CHECK_ERROR(pmic_write_reg(REG_ADC_1, 4 << ADC_CH_1_POS, + ADC_CH_0_MASK | ADC_CH_1_MASK)); + + for (i = 0; i <= 3; i++) { + CHECK_ERROR(pmic_read_reg(result_reg, &result, PMIC_ALL_BITS)); + pr_debug("result %i = %x\n", result_reg, result); + adc_param->value[i] = ((result & ADD1_RESULT_MASK) >> 2); + adc_param->value[i + 4] = ((result & ADD2_RESULT_MASK) >> 14); + } + if (adc_param->read_ts) { + adc_param->ts_value.x_position = adc_param->value[2]; + adc_param->ts_value.x_position1 = adc_param->value[0]; + adc_param->ts_value.x_position2 = adc_param->value[1]; + adc_param->ts_value.x_position3 = adc_param->value[2]; + adc_param->ts_value.y_position1 = adc_param->value[3]; + adc_param->ts_value.y_position2 = adc_param->value[4]; + adc_param->ts_value.y_position3 = adc_param->value[5]; + adc_param->ts_value.y_position = adc_param->value[5]; + adc_param->ts_value.contact_resistance = adc_param->value[6]; + + } + + /*if (adc_param->read_ts) { + adc_param->ts_value.x_position = adc_param->value[2]; + adc_param->ts_value.y_position = adc_param->value[5]; + adc_param->ts_value.contact_resistance = adc_param->value[6]; + } */ + mc13783_adc_release(use_bis); + if (adc_param->read_ts == false) + up(&convert_mutex); + + return PMIC_SUCCESS; +} + +/*! + * This function select the required read_mode for a specific channel. + * + * @param channel The channel to be sampled + * + * @return This function returns the requires read_mode + */ +t_reading_mode mc13783_set_read_mode(t_channel channel) +{ + t_reading_mode read_mode = 0; + + switch (channel) { + case LICELL: + read_mode = M_LITHIUM_CELL; + break; + case CHARGE_CURRENT: + read_mode = M_CHARGE_CURRENT; + break; + case BATTERY_CURRENT: + read_mode = M_BATTERY_CURRENT; + break; + case THERMISTOR: + read_mode = M_THERMISTOR; + break; + case DIE_TEMP: + read_mode = M_DIE_TEMPERATURE; + break; + case USB_ID: + read_mode = M_UID; + break; + default: + read_mode = 0; + } + + return read_mode; +} + +/*! + * This function triggers a conversion and returns one sampling result of one + * channel. + * + * @param channel The channel to be sampled + * @param result The pointer to the conversion result. The memory + * should be allocated by the caller of this function. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_convert(t_channel channel, unsigned short *result) +{ + t_adc_param adc_param; + PMIC_STATUS ret; + + if (suspend_flag == 1) { + return -EBUSY; + } + + channel = channel_num[channel]; + if (channel == -1) { + pr_debug("Wrong channel ID\n"); + return PMIC_PARAMETER_ERROR; + } + mc13783_adc_init_param(&adc_param); + pr_debug("pmic_adc_convert\n"); + adc_param.read_ts = false; + adc_param.read_mode = mc13783_set_read_mode(channel); + + adc_param.single_channel = true; + /* Find the group */ + if ((channel >= 0) && (channel <= 7)) { + adc_param.channel_0 = channel; + adc_param.group = false; + } else if ((channel >= 8) && (channel <= 15)) { + adc_param.channel_0 = channel & 0x07; + adc_param.group = true; + } else { + return PMIC_PARAMETER_ERROR; + } + ret = mc13783_adc_convert(&adc_param); + *result = adc_param.value[0]; + return ret; +} + +/*! + * This function triggers a conversion and returns eight sampling results of + * one channel. + * + * @param channel The channel to be sampled + * @param result The pointer to array to store eight sampling results. + * The memory should be allocated by the caller of this + * function. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_convert_8x(t_channel channel, unsigned short *result) +{ + t_adc_param adc_param; + int i; + PMIC_STATUS ret; + if (suspend_flag == 1) { + return -EBUSY; + } + + channel = channel_num[channel]; + + if (channel == -1) { + pr_debug("Wrong channel ID\n"); + return PMIC_PARAMETER_ERROR; + } + mc13783_adc_init_param(&adc_param); + pr_debug("pmic_adc_convert_8x\n"); + adc_param.read_ts = false; + adc_param.single_channel = true; + adc_param.read_mode = mc13783_set_read_mode(channel); + if ((channel >= 0) && (channel <= 7)) { + adc_param.channel_0 = channel; + adc_param.channel_1 = channel; + adc_param.group = false; + } else if ((channel >= 8) && (channel <= 15)) { + adc_param.channel_0 = channel & 0x07; + adc_param.channel_1 = channel & 0x07; + adc_param.group = true; + } else { + return PMIC_PARAMETER_ERROR; + } + + ret = mc13783_adc_convert(&adc_param); + for (i = 0; i <= 7; i++) { + result[i] = adc_param.value[i]; + } + return ret; +} + +/*! + * This function triggers a conversion and returns sampling results of each + * specified channel. + * + * @param channels This input parameter is bitmap to specify channels + * to be sampled. + * @param result The pointer to array to store sampling results. + * The memory should be allocated by the caller of this + * function. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_convert_multichnnel(t_channel channels, + unsigned short *result) +{ + t_adc_param adc_param; + int i; + PMIC_STATUS ret; + if (suspend_flag == 1) { + return -EBUSY; + } + mc13783_adc_init_param(&adc_param); + pr_debug("pmic_adc_convert_multichnnel\n"); + + channels = channel_num[channels]; + + if (channels == -1) { + pr_debug("Wrong channel ID\n"); + return PMIC_PARAMETER_ERROR; + } + + adc_param.read_ts = false; + adc_param.single_channel = false; + if ((channels >= 0) && (channels <= 7)) { + adc_param.channel_0 = channels; + adc_param.channel_1 = ((channels + 4) % 4) + 4; + adc_param.group = false; + } else if ((channels >= 8) && (channels <= 15)) { + channels = channels & 0x07; + adc_param.channel_0 = channels; + adc_param.channel_1 = ((channels + 4) % 4) + 4; + adc_param.group = true; + } else { + return PMIC_PARAMETER_ERROR; + } + adc_param.read_mode = 0x00003f; + adc_param.read_ts = false; + ret = mc13783_adc_convert(&adc_param); + + for (i = 0; i <= 7; i++) { + result[i] = adc_param.value[i]; + } + return ret; +} + +/*! + * This function sets touch screen operation mode. + * + * @param touch_mode Touch screen operation mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_set_touch_mode(t_touch_mode touch_mode) +{ + if (suspend_flag == 1) { + return -EBUSY; + } + CHECK_ERROR(pmic_write_reg(REG_ADC_0, + BITFVAL(MC13783_ADC0_TS_M, touch_mode), + BITFMASK(MC13783_ADC0_TS_M))); + return PMIC_SUCCESS; +} + +/*! + * This function retrieves the current touch screen operation mode. + * + * @param touch_mode Pointer to the retrieved touch screen operation + * mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_get_touch_mode(t_touch_mode * touch_mode) +{ + unsigned int value; + if (suspend_flag == 1) { + return -EBUSY; + } + CHECK_ERROR(pmic_read_reg(REG_ADC_0, &value, PMIC_ALL_BITS)); + + *touch_mode = BITFEXT(value, MC13783_ADC0_TS_M); + + return PMIC_SUCCESS; +} + +/*! + * This function retrieves the current touch screen (X,Y) coordinates. + * + * @param touch_sample Pointer to touch sample. + * @param wait indicates whether this call must block or not. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_get_touch_sample(t_touch_screen * touch_sample, int wait) +{ + if (mc13783_adc_read_ts(touch_sample, wait) != 0) + return PMIC_ERROR; + if (0 == pmic_adc_filter(touch_sample)) + return PMIC_SUCCESS; + else + return PMIC_ERROR; +} + +/*! + * This function read the touch screen value. + * + * @param ts_value return value of touch screen + * @param wait_tsi if true, this function is synchronous (wait in TSI event). + * + * @return This function returns 0. + */ +PMIC_STATUS mc13783_adc_read_ts(t_touch_screen * ts_value, int wait_tsi) +{ + t_adc_param param; + pr_debug("mc13783_adc : mc13783_adc_read_ts\n"); + if (suspend_flag == 1) { + return -EBUSY; + } + if (wait_ts) { + pr_debug("mc13783_adc : error TS busy \n"); + return PMIC_ERROR; + } + mc13783_adc_init_param(¶m); + param.wait_tsi = wait_tsi; + param.read_ts = true; + if (mc13783_adc_convert(¶m) != 0) + return PMIC_ERROR; + /* check if x-y is ok */ + if ((param.ts_value.x_position1 < TS_X_MAX) && + (param.ts_value.x_position1 >= TS_X_MIN) && + (param.ts_value.y_position1 < TS_Y_MAX) && + (param.ts_value.y_position1 >= TS_Y_MIN) && + (param.ts_value.x_position2 < TS_X_MAX) && + (param.ts_value.x_position2 >= TS_X_MIN) && + (param.ts_value.y_position2 < TS_Y_MAX) && + (param.ts_value.y_position2 >= TS_Y_MIN) && + (param.ts_value.x_position3 < TS_X_MAX) && + (param.ts_value.x_position3 >= TS_X_MIN) && + (param.ts_value.y_position3 < TS_Y_MAX) && + (param.ts_value.y_position3 >= TS_Y_MIN)) { + ts_value->x_position = param.ts_value.x_position; + ts_value->x_position1 = param.ts_value.x_position1; + ts_value->x_position2 = param.ts_value.x_position2; + ts_value->x_position3 = param.ts_value.x_position3; + ts_value->y_position = param.ts_value.y_position; + ts_value->y_position1 = param.ts_value.y_position1; + ts_value->y_position2 = param.ts_value.y_position2; + ts_value->y_position3 = param.ts_value.y_position3; + ts_value->contact_resistance = + param.ts_value.contact_resistance + 1; + + } else { + ts_value->x_position = 0; + ts_value->y_position = 0; + ts_value->contact_resistance = 0; + + } + return PMIC_SUCCESS; +} + +/*! + * This function starts a Battery Current mode conversion. + * + * @param mode Conversion mode. + * @param result Battery Current measurement result. + * if \a mode = ADC_8CHAN_1X, the result is \n + * result[0] = (BATTP - BATT_I) \n + * if \a mode = ADC_1CHAN_8X, the result is \n + * result[0] = BATTP \n + * result[1] = BATT_I \n + * result[2] = BATTP \n + * result[3] = BATT_I \n + * result[4] = BATTP \n + * result[5] = BATT_I \n + * result[6] = BATTP \n + * result[7] = BATT_I + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_get_battery_current(t_conversion_mode mode, + unsigned short *result) +{ + PMIC_STATUS ret; + t_channel channel; + if (suspend_flag == 1) { + return -EBUSY; + } + channel = BATTERY_CURRENT; + if (mode == ADC_8CHAN_1X) { + ret = pmic_adc_convert(channel, result); + } else { + ret = pmic_adc_convert_8x(channel, result); + } + return ret; +} + +/*! + * This function request a ADC. + * + * @return This function returns index of ADC to be used (0 or 1) if successful. + return -1 if error. + */ +int mc13783_adc_request(bool read_ts) +{ + int adc_index = -1; + if (read_ts != 0) { + /*for ts we use bis=0 */ + if (adc_dev[0] == ADC_USED) + return -1; + /*no wait here */ + adc_dev[0] = ADC_USED; + adc_index = 0; + } else { + /*for other adc use bis = 1 */ + if (adc_dev[1] == ADC_USED) { + return -1; + /*no wait here */ + } + adc_dev[1] = ADC_USED; + adc_index = 1; + } + pr_debug("mc13783_adc : request ADC %d\n", adc_index); + return adc_index; +} + +/*! + * This function release an ADC. + * + * @param adc_index index of ADC to be released. + * + * @return This function returns 0 if successful. + */ +int mc13783_adc_release(int adc_index) +{ + while (suspend_flag == 1) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, (suspend_flag == 0))) { + return -ERESTARTSYS; + } + } + + pr_debug("mc13783_adc : release ADC %d\n", adc_index); + if ((adc_dev[adc_index] == ADC_MONITORING) || + (adc_dev[adc_index] == ADC_USED)) { + adc_dev[adc_index] = ADC_FREE; + wake_up(&queue_adc_busy); + return 0; + } + return -1; +} + +/*! + * This function initializes monitoring structure. + * + * @param monitor Structure to be initialized. + * + * @return This function returns 0 if successful. + */ +int mc13783_adc_init_monitor_param(t_monitoring_param * monitor) +{ + pr_debug("mc13783_adc : init monitor\n"); + monitor->delay = 0; + monitor->conv_delay = false; + monitor->channel = BATTERY_VOLTAGE; + monitor->read_mode = 0; + monitor->comp_low = 0; + monitor->comp_high = 0; + monitor->group = 0; + monitor->check_mode = CHECK_LOW_OR_HIGH; + monitor->callback = NULL; + return 0; +} + +/*! + * This function actives the comparator. When comparator is active and ADC + * is enabled, the 8th converted value will be digitally compared against the + * window defined by WLOW and WHIGH registers. + * + * @param low Comparison window low threshold (WLOW). + * @param high Comparison window high threshold (WHIGH). + * @param channel The channel to be sampled + * @param callback Callback function to be called when the converted + * value is beyond the comparison window. The callback + * function will pass a parameter of type + * \b t_comp_expection to indicate the reason of + * comparator exception. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_active_comparator(unsigned char low, + unsigned char high, + t_channel channel, + t_comparator_cb callback) +{ + bool use_bis = false; + unsigned int adc_0_reg = 0, adc_1_reg = 0, adc_3_reg = 0; + t_monitoring_param monitoring; + + if (suspend_flag == 1) { + return -EBUSY; + } + if (monitor_en) { + pr_debug("mc13783_adc : monitoring already configured\n"); + return PMIC_ERROR; + } + monitor_en = true; + mc13783_adc_init_monitor_param(&monitoring); + monitoring.comp_low = low; + monitoring.comp_high = high; + monitoring.channel = channel; + monitoring.callback = (void *)callback; + + use_bis = mc13783_adc_request(false); + if (use_bis < 0) { + pr_debug("mc13783_adc : request error\n"); + return PMIC_ERROR; + } + monitor_adc = use_bis; + + adc_0_reg = 0; + + /* TO DO ADOUT CONFIGURE */ + adc_0_reg = monitoring.read_mode & ADC_MODE_MASK; + if (use_bis) { + /* add adc bis */ + adc_0_reg |= ADC_BIS; + } + adc_0_reg |= ADC_WCOMP; + + /* CONFIGURE ADC REG 1 */ + adc_1_reg = 0; + adc_1_reg |= ADC_EN; + if (monitoring.conv_delay) { + adc_1_reg |= ADC_ATO; + } + if (monitoring.group) { + adc_1_reg |= ADC_ADSEL; + } + adc_1_reg |= (monitoring.channel << ADC_CH_0_POS) & ADC_CH_0_MASK; + adc_1_reg |= (monitoring.delay << ADC_DELAY_POS) & ADC_DELAY_MASK; + if (use_bis) { + adc_1_reg |= ADC_BIS; + } + + adc_3_reg |= (monitoring.comp_high << ADC_WCOMP_H_POS) & + ADC_WCOMP_H_MASK; + adc_3_reg |= (monitoring.comp_low << ADC_WCOMP_L_POS) & + ADC_WCOMP_L_MASK; + if (use_bis) { + adc_3_reg |= ADC_BIS; + } + + wcomp_mode = monitoring.check_mode; + /* call back to be called when event is detected. */ + monitoring_cb = monitoring.callback; + + CHECK_ERROR(pmic_write_reg(REG_ADC_0, adc_0_reg, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_1, adc_1_reg, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_3, adc_3_reg, PMIC_ALL_BITS)); + return PMIC_SUCCESS; +} + +/*! + * This function deactivates the comparator. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_deactive_comparator(void) +{ + unsigned int reg_value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + if (!monitor_en) { + pr_debug("mc13783_adc : adc monitoring free\n"); + return PMIC_ERROR; + } + + if (monitor_en) { + reg_value = ADC_BIS; + } + + /* clear all reg value */ + CHECK_ERROR(pmic_write_reg(REG_ADC_0, reg_value, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_1, reg_value, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_3, reg_value, PMIC_ALL_BITS)); + + reg_value = 0; + + if (monitor_adc) { + CHECK_ERROR(pmic_write_reg + (REG_ADC_4, reg_value, PMIC_ALL_BITS)); + } else { + CHECK_ERROR(pmic_write_reg + (REG_ADC_2, reg_value, PMIC_ALL_BITS)); + } + + mc13783_adc_release(monitor_adc); + monitor_en = false; + return PMIC_SUCCESS; +} + +/*! + * This function implements IOCTL controls on a MC13783 ADC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @param cmd the command + * @param arg the parameter + * @return This function returns 0 if successful. + */ +static int pmic_adc_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + t_adc_convert_param *convert_param; + t_touch_mode touch_mode; + t_touch_screen touch_sample; + unsigned short b_current; + t_adc_comp_param *comp_param; + if ((_IOC_TYPE(cmd) != 'p') && (_IOC_TYPE(cmd) != 'D')) + return -ENOTTY; + + while (suspend_flag == 1) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, (suspend_flag == 0))) { + return -ERESTARTSYS; + } + } + + switch (cmd) { + case PMIC_ADC_INIT: + pr_debug("init adc\n"); + CHECK_ERROR(pmic_adc_init()); + break; + + case PMIC_ADC_DEINIT: + pr_debug("deinit adc\n"); + CHECK_ERROR(pmic_adc_deinit()); + break; + + case PMIC_ADC_CONVERT: + if ((convert_param = kmalloc(sizeof(t_adc_convert_param), + GFP_KERNEL)) == NULL) { + return -ENOMEM; + } + if (copy_from_user(convert_param, (t_adc_convert_param *) arg, + sizeof(t_adc_convert_param))) { + kfree(convert_param); + return -EFAULT; + } + CHECK_ERROR_KFREE(pmic_adc_convert(convert_param->channel, + convert_param->result), + (kfree(convert_param))); + + if (copy_to_user((t_adc_convert_param *) arg, convert_param, + sizeof(t_adc_convert_param))) { + kfree(convert_param); + return -EFAULT; + } + kfree(convert_param); + break; + + case PMIC_ADC_CONVERT_8X: + if ((convert_param = kmalloc(sizeof(t_adc_convert_param), + GFP_KERNEL)) == NULL) { + return -ENOMEM; + } + if (copy_from_user(convert_param, (t_adc_convert_param *) arg, + sizeof(t_adc_convert_param))) { + kfree(convert_param); + return -EFAULT; + } + CHECK_ERROR_KFREE(pmic_adc_convert_8x(convert_param->channel, + convert_param->result), + (kfree(convert_param))); + + if (copy_to_user((t_adc_convert_param *) arg, convert_param, + sizeof(t_adc_convert_param))) { + kfree(convert_param); + return -EFAULT; + } + kfree(convert_param); + break; + + case PMIC_ADC_CONVERT_MULTICHANNEL: + if ((convert_param = kmalloc(sizeof(t_adc_convert_param), + GFP_KERNEL)) == NULL) { + return -ENOMEM; + } + if (copy_from_user(convert_param, (t_adc_convert_param *) arg, + sizeof(t_adc_convert_param))) { + kfree(convert_param); + return -EFAULT; + } + + CHECK_ERROR_KFREE(pmic_adc_convert_multichnnel + (convert_param->channel, + convert_param->result), + (kfree(convert_param))); + + if (copy_to_user((t_adc_convert_param *) arg, convert_param, + sizeof(t_adc_convert_param))) { + kfree(convert_param); + return -EFAULT; + } + kfree(convert_param); + break; + + case PMIC_ADC_SET_TOUCH_MODE: + CHECK_ERROR(pmic_adc_set_touch_mode((t_touch_mode) arg)); + break; + + case PMIC_ADC_GET_TOUCH_MODE: + CHECK_ERROR(pmic_adc_get_touch_mode(&touch_mode)); + if (copy_to_user((t_touch_mode *) arg, &touch_mode, + sizeof(t_touch_mode))) { + return -EFAULT; + } + break; + + case PMIC_ADC_GET_TOUCH_SAMPLE: + pr_debug("pmic_adc_ioctl: " "PMIC_ADC_GET_TOUCH_SAMPLE\n"); + CHECK_ERROR(pmic_adc_get_touch_sample(&touch_sample, 1)); + if (copy_to_user((t_touch_screen *) arg, &touch_sample, + sizeof(t_touch_screen))) { + return -EFAULT; + } + break; + + case PMIC_ADC_GET_BATTERY_CURRENT: + CHECK_ERROR(pmic_adc_get_battery_current(ADC_8CHAN_1X, + &b_current)); + if (copy_to_user((unsigned short *)arg, &b_current, + sizeof(unsigned short))) { + + return -EFAULT; + } + break; + + case PMIC_ADC_ACTIVATE_COMPARATOR: + if ((comp_param = kmalloc(sizeof(t_adc_comp_param), GFP_KERNEL)) + == NULL) { + return -ENOMEM; + } + if (copy_from_user(comp_param, (t_adc_comp_param *) arg, + sizeof(t_adc_comp_param))) { + kfree(comp_param); + return -EFAULT; + } + CHECK_ERROR_KFREE(pmic_adc_active_comparator(comp_param->wlow, + comp_param->whigh, + comp_param-> + channel, + comp_param-> + callback), + (kfree(comp_param))); + break; + + case PMIC_ADC_DEACTIVE_COMPARATOR: + CHECK_ERROR(pmic_adc_deactive_comparator()); + break; + + default: + pr_debug("pmic_adc_ioctl: unsupported ioctl command 0x%x\n", + cmd); + return -EINVAL; + } + return 0; +} + +static struct file_operations mc13783_adc_fops = { + .owner = THIS_MODULE, + .ioctl = pmic_adc_ioctl, + .open = pmic_adc_open, + .release = pmic_adc_free, +}; + +static int pmic_adc_module_probe(struct platform_device *pdev) +{ + int ret = 0; + struct device *temp_class; + + pmic_adc_major = register_chrdev(0, "pmic_adc", &mc13783_adc_fops); + + if (pmic_adc_major < 0) { + pr_debug(KERN_ERR "Unable to get a major for pmic_adc\n"); + return pmic_adc_major; + } + init_waitqueue_head(&suspendq); + + pmic_adc_class = class_create(THIS_MODULE, "pmic_adc"); + if (IS_ERR(pmic_adc_class)) { + pr_debug(KERN_ERR "Error creating pmic_adc class.\n"); + ret = PTR_ERR(pmic_adc_class); + goto err_out1; + } + + temp_class = device_create(pmic_adc_class, NULL, + MKDEV(pmic_adc_major, 0), "pmic_adc"); + if (IS_ERR(temp_class)) { + pr_debug(KERN_ERR "Error creating pmic_adc class device.\n"); + ret = PTR_ERR(temp_class); + goto err_out2; + } + + ret = pmic_adc_init(); + if (ret != PMIC_SUCCESS) { + pr_debug(KERN_ERR "Error in pmic_adc_init.\n"); + goto err_out4; + } + + pmic_adc_ready = 1; + pr_debug(KERN_INFO "PMIC ADC successfully probed\n"); + return ret; + + err_out4: + device_destroy(pmic_adc_class, MKDEV(pmic_adc_major, 0)); + err_out2: + class_destroy(pmic_adc_class); + err_out1: + unregister_chrdev(pmic_adc_major, "pmic_adc"); + return ret; +} + +static int pmic_adc_module_remove(struct platform_device *pdev) +{ + pmic_adc_ready = 0; + pmic_adc_deinit(); + device_destroy(pmic_adc_class, MKDEV(pmic_adc_major, 0)); + class_destroy(pmic_adc_class); + unregister_chrdev(pmic_adc_major, "pmic_adc"); + pr_debug(KERN_INFO "PMIC ADC successfully removed\n"); + return 0; +} + +static struct platform_driver pmic_adc_driver_ldm = { + .driver = { + .name = "pmic_adc", + }, + .suspend = pmic_adc_suspend, + .resume = pmic_adc_resume, + .probe = pmic_adc_module_probe, + .remove = pmic_adc_module_remove, +}; + +/* + * Initialization and Exit + */ +static int __init pmic_adc_module_init(void) +{ + pr_debug("PMIC ADC driver loading...\n"); + return platform_driver_register(&pmic_adc_driver_ldm); +} + +static void __exit pmic_adc_module_exit(void) +{ + platform_driver_unregister(&pmic_adc_driver_ldm); + pr_debug("PMIC ADC driver successfully unloaded\n"); +} + +/* + * Module entry points + */ + +module_init(pmic_adc_module_init); +module_exit(pmic_adc_module_exit); + +MODULE_DESCRIPTION("PMIC ADC device driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_adc_defs.h linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_adc_defs.h --- linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_adc_defs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_adc_defs.h 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,321 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_adc_defs.h + * @brief This header contains all defines for PMIC(mc13783) ADC driver. + * + * @ingroup PMIC_ADC + */ + +#ifndef __MC13783_ADC__DEFS_H__ +#define __MC13783_ADC__DEFS_H__ + +#define MC13783_ADC_DEVICE "/dev/mc13783_adc" + +#define DEF_ADC_0 0x008000 +#define DEF_ADC_3 0x000080 + +#define ADC_NB_AVAILABLE 2 + +#define MAX_CHANNEL 7 + +/* + * Maximun allowed variation in the three X/Y co-ordinates acquired from + * touch-screen + */ +#define DELTA_Y_MAX 50 +#define DELTA_X_MAX 50 + +/* Upon clearing the filter, this is the delay in restarting the filter */ +#define FILTER_MIN_DELAY 4 + +/* Length of X and Y Touch screen filters */ +#define FILTLEN 3 + +#define TS_X_MAX 1000 +#define TS_Y_MAX 1000 + +#define TS_X_MIN 80 +#define TS_Y_MIN 80 + +#define MC13783_ADC0_TS_M_LSH 14 +#define MC13783_ADC0_TS_M_WID 3 +/* + * ADC 0 + */ +#define ADC_WAIT_TSI_0 0x001C00 + +/* + * ADC 1 + */ + +#define ADC_EN 0x000001 +#define ADC_SGL_CH 0x000002 +#define ADC_ADSEL 0x000008 +#define ADC_CH_0_POS 5 +#define ADC_CH_0_MASK 0x0000E0 +#define ADC_CH_1_POS 8 +#define ADC_CH_1_MASK 0x000700 +#define ADC_DELAY_POS 11 +#define ADC_DELAY_MASK 0x07F800 +#define ADC_ATO 0x080000 +#define ASC_ADC 0x100000 +#define ADC_WAIT_TSI_1 0x300001 +#define ADC_CHRGRAW_D5 0x008000 + +/* + * ADC 2 - 4 + */ +#define ADD1_RESULT_MASK 0x00000FFC +#define ADD2_RESULT_MASK 0x00FFC000 +#define ADC_TS_MASK 0x00FFCFFC + +/* + * ADC 3 + */ +#define ADC_INC 0x030000 +#define ADC_BIS 0x800000 + +/* + * ADC 3 + */ +#define ADC_NO_ADTRIG 0x200000 +#define ADC_WCOMP 0x040000 +#define ADC_WCOMP_H_POS 0 +#define ADC_WCOMP_L_POS 9 +#define ADC_WCOMP_H_MASK 0x00003F +#define ADC_WCOMP_L_MASK 0x007E00 + +#define ADC_MODE_MASK 0x00003F + +/* + * Interrupt Status 0 + */ +#define ADC_INT_BISDONEI 0x02 + +/*! + * Define state mode of ADC. + */ +typedef enum adc_state { + /*! + * Free. + */ + ADC_FREE, + /*! + * Used. + */ + ADC_USED, + /*! + * Monitoring + */ + ADC_MONITORING, +} t_adc_state; + +/*! + * This enumeration, is used to configure the mode of ADC. + */ +typedef enum reading_mode { + /*! + * Enables lithium cell reading + */ + M_LITHIUM_CELL = 0x000001, + /*! + * Enables charge current reading + */ + M_CHARGE_CURRENT = 0x000002, + /*! + * Enables battery current reading + */ + M_BATTERY_CURRENT = 0x000004, + /*! + * Enables thermistor reading + */ + M_THERMISTOR = 0x000008, + /*! + * Enables die temperature reading + */ + M_DIE_TEMPERATURE = 0x000010, + /*! + * Enables UID reading + */ + M_UID = 0x000020, +} t_reading_mode; + +/*! + * This enumeration, is used to configure the monitoring mode. + */ +typedef enum check_mode { + /*! + * Comparator low level + */ + CHECK_LOW, + /*! + * Comparator high level + */ + CHECK_HIGH, + /*! + * Comparator low or high level + */ + CHECK_LOW_OR_HIGH, +} t_check_mode; + +/*! + * This structure is used to configure and report adc value. + */ +typedef struct { + /*! + * Delay before first conversion + */ + unsigned int delay; + /*! + * sets the ATX bit for delay on all conversion + */ + bool conv_delay; + /*! + * Sets the single channel mode + */ + bool single_channel; + /*! + * Selects the set of inputs + */ + bool group; + /*! + * Channel selection 1 + */ + t_channel channel_0; + /*! + * Channel selection 2 + */ + t_channel channel_1; + /*! + * Used to configure ADC mode with t_reading_mode + */ + t_reading_mode read_mode; + /*! + * Sets the Touch screen mode + */ + bool read_ts; + /*! + * Wait TSI event before touch screen reading + */ + bool wait_tsi; + /*! + * Sets CHRGRAW scaling to divide by 5 + * Only supported on 2.0 and higher + */ + bool chrgraw_devide_5; + /*! + * Return ADC values + */ + unsigned int value[8]; + /*! + * Return touch screen values + */ + t_touch_screen ts_value; +} t_adc_param; + +/*! + * This structure is used to configure the monitoring mode of ADC. + */ +typedef struct { + /*! + * Delay before first conversion + */ + unsigned int delay; + /*! + * sets the ATX bit for delay on all conversion + */ + bool conv_delay; + /*! + * Channel selection 1 + */ + t_channel channel; + /*! + * Selects the set of inputs + */ + bool group; + /*! + * Used to configure ADC mode with t_reading_mode + */ + unsigned int read_mode; + /*! + * Comparator low level in WCOMP mode + */ + unsigned int comp_low; + /*! + * Comparator high level in WCOMP mode + */ + unsigned int comp_high; + /*! + * Sets type of monitoring (low, high or both) + */ + t_check_mode check_mode; + /*! + * Callback to be launched when event is detected + */ + void (*callback) (void); +} t_monitoring_param; + +/*! + * This function performs filtering and rejection of excessive noise prone + * samples. + * + * @param ts_curr Touch screen value + * + * @return This function returns 0 on success, -1 otherwise. + */ +static int pmic_adc_filter(t_touch_screen * ts_curr); + +/*! + * This function request a ADC. + * + * @return This function returns index of ADC to be used (0 or 1) if successful. + return -1 if error. + */ +int mc13783_adc_request(bool read_ts); + +/*! + * This function is used to update buffer of touch screen value in read mode. + */ +void update_buffer(void); + +/*! + * This function release an ADC. + * + * @param adc_index index of ADC to be released. + * + * @return This function returns 0 if successful. + */ +int mc13783_adc_release(int adc_index); + +/*! + * This function select the required read_mode for a specific channel. + * + * @param channel The channel to be sampled + * + * @return This function returns the requires read_mode + */ +t_reading_mode mc13783_set_read_mode(t_channel channel); + +/*! + * This function read the touch screen value. + * + * @param touch_sample return value of touch screen + * @param wait_tsi if true, this function is synchronous (wait in TSI event). + * + * @return This function returns 0. + */ +PMIC_STATUS mc13783_adc_read_ts(t_touch_screen * touch_sample, int wait_tsi); + +#endif /* __MC13783_ADC__DEFS_H__ */ diff -urN linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_audio.c linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_audio.c --- linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_audio.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_audio.c 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,5876 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_audio.c + * @brief Implementation of the PMIC(mc13783) Audio driver APIs. + * + * The PMIC Audio driver and this API were developed to support the + * audio playback, recording, and mixing capabilities of the power + * management ICs that are available from Freescale Semiconductor, Inc. + * + * The following operating modes are supported: + * + * @verbatim + Operating Mode mc13783 + ---------------------------- ------- + Stereo DAC Playback Yes + Stereo DAC Input Mixing Yes + Voice CODEC Playback Yes + Voice CODEC Input Mixing Yes + Voice CODEC Mono Recording Yes + Voice CODEC Stereo Recording Yes + Microphone Bias Control Yes + Output Amplifier Control Yes + Output Mixing Control Yes + Input Amplifier Control Yes + Master/Slave Mode Select Yes + Anti Pop Bias Circuit Control Yes + @endverbatim + * + * Note that the Voice CODEC may also be referred to as the Telephone + * CODEC in the PMIC DTS documentation. Also note that, while the power + * management ICs do provide similar audio capabilities, each PMIC may + * support additional configuration settings and features. Therefore, it + * is highly recommended that the appropriate power management IC DTS + * documents be used in conjunction with this API interface. + * + * @ingroup PMIC_AUDIO + */ + +#include +#include /* For tasklet interface. */ +#include /* For kernel module interface. */ +#include +#include /* For spinlock interface. */ +#include /* For PMIC ADC driver interface. */ +#include +#include /* For PMIC Audio driver interface. */ + +/* + * mc13783 PMIC Audio API + */ + +/* EXPORTED FUNCTIONS */ +EXPORT_SYMBOL(MIN_STDAC_SAMPLING_RATE_HZ); +EXPORT_SYMBOL(MAX_STDAC_SAMPLING_RATE_HZ); +EXPORT_SYMBOL(pmic_audio_open); +EXPORT_SYMBOL(pmic_audio_close); +EXPORT_SYMBOL(pmic_audio_set_protocol); +EXPORT_SYMBOL(pmic_audio_get_protocol); +EXPORT_SYMBOL(pmic_audio_enable); +EXPORT_SYMBOL(pmic_audio_disable); +EXPORT_SYMBOL(pmic_audio_reset); +EXPORT_SYMBOL(pmic_audio_reset_all); +EXPORT_SYMBOL(pmic_audio_set_callback); +EXPORT_SYMBOL(pmic_audio_clear_callback); +EXPORT_SYMBOL(pmic_audio_get_callback); +EXPORT_SYMBOL(pmic_audio_antipop_enable); +EXPORT_SYMBOL(pmic_audio_antipop_disable); +EXPORT_SYMBOL(pmic_audio_digital_filter_reset); +EXPORT_SYMBOL(pmic_audio_vcodec_set_clock); +EXPORT_SYMBOL(pmic_audio_vcodec_get_clock); +EXPORT_SYMBOL(pmic_audio_vcodec_set_rxtx_timeslot); +EXPORT_SYMBOL(pmic_audio_vcodec_get_rxtx_timeslot); +EXPORT_SYMBOL(pmic_audio_vcodec_set_secondary_txslot); +EXPORT_SYMBOL(pmic_audio_vcodec_get_secondary_txslot); +EXPORT_SYMBOL(pmic_audio_vcodec_set_config); +EXPORT_SYMBOL(pmic_audio_vcodec_clear_config); +EXPORT_SYMBOL(pmic_audio_vcodec_get_config); +EXPORT_SYMBOL(pmic_audio_vcodec_enable_bypass); +EXPORT_SYMBOL(pmic_audio_vcodec_disable_bypass); +EXPORT_SYMBOL(pmic_audio_stdac_set_clock); +EXPORT_SYMBOL(pmic_audio_stdac_get_clock); +EXPORT_SYMBOL(pmic_audio_stdac_set_rxtx_timeslot); +EXPORT_SYMBOL(pmic_audio_stdac_get_rxtx_timeslot); +EXPORT_SYMBOL(pmic_audio_stdac_set_config); +EXPORT_SYMBOL(pmic_audio_stdac_clear_config); +EXPORT_SYMBOL(pmic_audio_stdac_get_config); +EXPORT_SYMBOL(pmic_audio_input_set_config); +EXPORT_SYMBOL(pmic_audio_input_clear_config); +EXPORT_SYMBOL(pmic_audio_input_get_config); +EXPORT_SYMBOL(pmic_audio_vcodec_set_mic); +EXPORT_SYMBOL(pmic_audio_vcodec_get_mic); +EXPORT_SYMBOL(pmic_audio_vcodec_set_mic_on_off); +EXPORT_SYMBOL(pmic_audio_vcodec_get_mic_on_off); +EXPORT_SYMBOL(pmic_audio_vcodec_set_record_gain); +EXPORT_SYMBOL(pmic_audio_vcodec_get_record_gain); +EXPORT_SYMBOL(pmic_audio_vcodec_enable_micbias); +EXPORT_SYMBOL(pmic_audio_vcodec_disable_micbias); +EXPORT_SYMBOL(pmic_audio_vcodec_enable_mixer); +EXPORT_SYMBOL(pmic_audio_vcodec_disable_mixer); +EXPORT_SYMBOL(pmic_audio_stdac_enable_mixer); +EXPORT_SYMBOL(pmic_audio_stdac_disable_mixer); +EXPORT_SYMBOL(pmic_audio_output_set_port); +EXPORT_SYMBOL(pmic_audio_output_get_port); +EXPORT_SYMBOL(pmic_audio_output_clear_port); +EXPORT_SYMBOL(pmic_audio_output_set_stereo_in_gain); +EXPORT_SYMBOL(pmic_audio_output_get_stereo_in_gain); +EXPORT_SYMBOL(pmic_audio_output_set_pgaGain); +EXPORT_SYMBOL(pmic_audio_output_get_pgaGain); +EXPORT_SYMBOL(pmic_audio_output_enable_mixer); +EXPORT_SYMBOL(pmic_audio_output_disable_mixer); +EXPORT_SYMBOL(pmic_audio_output_set_balance); +EXPORT_SYMBOL(pmic_audio_output_get_balance); +EXPORT_SYMBOL(pmic_audio_output_enable_mono_adder); +EXPORT_SYMBOL(pmic_audio_output_disable_mono_adder); +EXPORT_SYMBOL(pmic_audio_output_set_mono_adder_gain); +EXPORT_SYMBOL(pmic_audio_output_get_mono_adder_gain); +EXPORT_SYMBOL(pmic_audio_output_set_config); +EXPORT_SYMBOL(pmic_audio_output_clear_config); +EXPORT_SYMBOL(pmic_audio_output_get_config); +EXPORT_SYMBOL(pmic_audio_output_enable_phantom_ground); +EXPORT_SYMBOL(pmic_audio_output_disable_phantom_ground); +EXPORT_SYMBOL(pmic_audio_set_autodetect); +#ifdef DEBUG_AUDIO +EXPORT_SYMBOL(pmic_audio_dump_registers); +#endif /* DEBUG_AUDIO */ +/*! + * Define the minimum sampling rate (in Hz) that is supported by the + * Stereo DAC. + */ +const unsigned MIN_STDAC_SAMPLING_RATE_HZ = 8000; + +/*! + * Define the maximum sampling rate (in Hz) that is supported by the + * Stereo DAC. + */ +const unsigned MAX_STDAC_SAMPLING_RATE_HZ = 96000; + +/*! @def SET_BITS + * Set a register field to a given value. + */ +#define SET_BITS(reg, field, value) (((value) << reg.field.offset) & \ + reg.field.mask) +/*! @def GET_BITS + * Get the current value of a given register field. + */ +#define GET_BITS(reg, field, value) (((value) & reg.field.mask) >> \ + reg.field.offset) + +/*! + * @brief Define the possible states for a device handle. + * + * This enumeration is used to track the current state of each device handle. + */ +typedef enum { + HANDLE_FREE, /*!< Handle is available for use. */ + HANDLE_IN_USE /*!< Handle is currently in use. */ +} HANDLE_STATE; + +/*! + * @brief Identifies the hardware interrupt source. + * + * This enumeration identifies which of the possible hardware interrupt + * sources actually caused the current interrupt handler to be called. + */ +typedef enum { + CORE_EVENT_MC2BI, /*!< Microphone Bias 2 detect. */ + CORE_EVENT_HSDETI, /*!< Detect Headset attach */ + CORE_EVENT_HSLI, /*!< Detect Stereo Headset */ + CORE_EVENT_ALSPTHI, /*!< Detect Thermal shutdown of ALSP */ + CORE_EVENT_AHSSHORTI /*!< Detect Short circuit on AHS outputs */ +} PMIC_CORE_EVENT; + +/*! + * @brief This structure is used to track the state of a microphone input. + */ +typedef struct { + PMIC_AUDIO_INPUT_PORT mic; /*!< Microphone input port. */ + PMIC_AUDIO_INPUT_MIC_STATE micOnOff; /*!< Microphone On/Off state. */ + PMIC_AUDIO_MIC_AMP_MODE ampMode; /*!< Input amplifier mode. */ + PMIC_AUDIO_MIC_GAIN gain; /*!< Input amplifier gain level. */ +} PMIC_MICROPHONE_STATE; + +/*! + * @brief Tracks whether a headset is currently attached or not. + */ +typedef enum { + NO_HEADSET, /*!< No headset currently attached. */ + HEADSET_ON /*!< Headset has been attached. */ +} HEADSET_STATUS; + +/*! + * @brief mc13783 only enum that indicates the path to output taken + * by the voice codec output + */ +typedef enum { + VCODEC_DIRECT_OUT, /*!< Vcodec signal out direct */ + VCODEC_MIXER_OUT /*!< Output via the mixer */ +} PMIC_AUDIO_VCODEC_OUTPUT_PATH; + +/*! + * @brief This structure is used to define a specific hardware register field. + * + * All hardware register fields are defined using an offset to the LSB + * and a mask. The offset is used to right shift a register value before + * applying the mask to actually obtain the value of the field. + */ +typedef struct { + const unsigned char offset; /*!< Offset of LSB of register field. */ + const unsigned int mask; /*!< Mask value used to isolate register field. */ +} REGFIELD; + +/*! + * @brief This structure lists all fields of the AUD_CODEC hardware register. + */ +typedef struct { + REGFIELD CDCSSISEL; /*!< codec SSI bus select */ + REGFIELD CDCCLKSEL; /*!< Codec clock input select */ + REGFIELD CDCSM; /*!< Codec slave / master select */ + REGFIELD CDCBCLINV; /*!< Codec bitclock inversion */ + REGFIELD CDCFSINV; /*!< Codec framesync inversion */ + REGFIELD CDCFS; /*!< Bus protocol selection - 2 bits */ + REGFIELD CDCCLK; /*!< Codec clock setting - 3 bits */ + REGFIELD CDCFS8K16K; /*!< Codec framesync select */ + REGFIELD CDCEN; /*!< Codec enable */ + REGFIELD CDCCLKEN; /*!< Codec clocking enable */ + REGFIELD CDCTS; /*!< Codec SSI tristate */ + REGFIELD CDCDITH; /*!< Codec dithering */ + REGFIELD CDCRESET; /*!< Codec filter reset */ + REGFIELD CDCBYP; /*!< Codec bypass */ + REGFIELD CDCALM; /*!< Codec analog loopback */ + REGFIELD CDCDLM; /*!< Codec digital loopback */ + REGFIELD AUDIHPF; /*!< Transmit high pass filter enable */ + REGFIELD AUDOHPF; /*!< Receive high pass filter enable */ +} REGISTER_AUD_CODEC; + +/*! + * @brief This variable is used to access the AUD_CODEC hardware register. + * + * This variable defines how to access all of the fields within the + * AUD_CODEC hardware register. The initial values consist of the offset + * and mask values needed to access each of the register fields. + */ +static const REGISTER_AUD_CODEC regAUD_CODEC = { + {0, 0x000001}, /* CDCSSISEL */ + {1, 0x000002}, /* CDCCLKSEL */ + {2, 0x000004}, /* CDCSM */ + {3, 0x000008}, /* CDCBCLINV */ + {4, 0x000010}, /* CDCFSINV */ + {5, 0x000060}, /* CDCFS */ + {7, 0x000380}, /* CDCCLK */ + {10, 0x000400}, /* CDCFS8K16K */ + {11, 0x000800}, /* CDCEN */ + {12, 0x001000}, /* CDCCLKEN */ + {13, 0x002000}, /* CDCTS */ + {14, 0x004000}, /* CDCDITH */ + {15, 0x008000}, /* CDCRESET */ + {16, 0x010000}, /* CDCBYP */ + {17, 0x020000}, /* CDCALM */ + {18, 0x040000}, /* CDCDLM */ + {19, 0x080000}, /* AUDIHPF */ + {20, 0x100000} /* AUDOHPF */ + /* Unused */ + /* Unused */ + /* Unused */ + +}; + +/*! + * @brief This structure lists all fields of the ST_DAC hardware register. + */ + /* VVV */ +typedef struct { + REGFIELD STDCSSISEL; /*!< Stereo DAC SSI bus select */ + REGFIELD STDCCLKSEL; /*!< Stereo DAC clock input select */ + REGFIELD STDCSM; /*!< Stereo DAC slave / master select */ + REGFIELD STDCBCLINV; /*!< Stereo DAC bitclock inversion */ + REGFIELD STDCFSINV; /*!< Stereo DAC framesync inversion */ + REGFIELD STDCFS; /*!< Bus protocol selection - 2 bits */ + REGFIELD STDCCLK; /*!< Stereo DAC clock setting - 3 bits */ + REGFIELD STDCFSDLYB; /*!< Stereo DAC framesync delay bar */ + REGFIELD STDCEN; /*!< Stereo DAC enable */ + REGFIELD STDCCLKEN; /*!< Stereo DAC clocking enable */ + REGFIELD STDCRESET; /*!< Stereo DAC filter reset */ + REGFIELD SPDIF; /*!< Stereo DAC SSI SPDIF mode. Mode no longer available. */ + REGFIELD SR; /*!< Stereo DAC sample rate - 4 bits */ +} REGISTER_ST_DAC; + +/*! + * @brief This variable is used to access the ST_DAC hardware register. + * + * This variable defines how to access all of the fields within the + * ST_DAC hardware register. The initial values consist of the offset + * and mask values needed to access each of the register fields. + */ +static const REGISTER_ST_DAC regST_DAC = { + {0, 0x000001}, /* STDCSSISEL */ + {1, 0x000002}, /* STDCCLKSEL */ + {2, 0x000004}, /* STDCSM */ + {3, 0x000008}, /* STDCBCLINV */ + {4, 0x000010}, /* STDCFSINV */ + {5, 0x000060}, /* STDCFS */ + {7, 0x000380}, /* STDCCLK */ + {10, 0x000400}, /* STDCFSDLYB */ + {11, 0x000800}, /* STDCEN */ + {12, 0x001000}, /* STDCCLKEN */ + {15, 0x008000}, /* STDCRESET */ + {16, 0x010000}, /* SPDIF */ + {17, 0x1E0000} /* SR */ +}; + +/*! + * @brief This structure lists all of the fields in the SSI_NETWORK hardware register. + */ +typedef struct { + REGFIELD CDCTXRXSLOT; /*!< Codec timeslot assignment - 2 bits */ + REGFIELD CDCTXSECSLOT; /*!< Codec secondary transmit timeslot - 2 bits */ + REGFIELD CDCRXSECSLOT; /*!< Codec secondary receive timeslot - 2 bits */ + REGFIELD CDCRXSECGAIN; /*!< Codec secondary receive channel gain setting - 2 bits */ + REGFIELD CDCSUMGAIN; /*!< Codec summed receive signal gain setting */ + REGFIELD CDCFSDLY; /*!< Codec framesync delay */ + REGFIELD STDCSLOTS; /*!< Stereo DAC number of timeslots select - 2 bits */ + REGFIELD STDCRXSLOT; /*!< Stereo DAC timeslot assignment - 2 bits */ + REGFIELD STDCRXSECSLOT; /*!< Stereo DAC secondary receive timeslot - 2 bits */ + REGFIELD STDCRXSECGAIN; /*!< Stereo DAC secondary receive channel gain setting - 2 bits */ + REGFIELD STDCSUMGAIN; /*!< Stereo DAC summed receive signal gain setting */ +} REGISTER_SSI_NETWORK; + +/*! + * @brief This variable is used to access the SSI_NETWORK hardware register. + * + * This variable defines how to access all of the fields within the + * SSI_NETWORK hardware register. The initial values consist of the offset + * and mask values needed to access each of the register fields. + */ +static const REGISTER_SSI_NETWORK regSSI_NETWORK = { + {2, 0x00000c}, /* CDCTXRXSLOT */ + {4, 0x000030}, /* CDCTXSECSLOT */ + {6, 0x0000c0}, /* CDCRXSECSLOT */ + {8, 0x000300}, /* CDCRXSECGAIN */ + {10, 0x000400}, /* CDCSUMGAIN */ + {11, 0x000800}, /* CDCFSDLY */ + {12, 0x003000}, /* STDCSLOTS */ + {14, 0x00c000}, /* STDCRXSLOT */ + {16, 0x030000}, /* STDCRXSECSLOT */ + {18, 0x0c0000}, /* STDCRXSECGAIN */ + {20, 0x100000} /* STDCSUMGAIN */ +}; + +/*! + * @brief This structure lists all fields of the AUDIO_TX hardware register. + * + * + */ +typedef struct { + REGFIELD MC1BEN; /*!< Microphone bias 1 enable */ + REGFIELD MC2BEN; /*!< Microphone bias 2 enable */ + REGFIELD MC2BDETDBNC; /*!< Microphone bias detect debounce setting */ + REGFIELD MC2BDETEN; /*!< Microphone bias 2 detect enable */ + REGFIELD AMC1REN; /*!< Amplifier Amc1R enable */ + REGFIELD AMC1RITOV; /*!< Amplifier Amc1R current to voltage mode enable */ + REGFIELD AMC1LEN; /*!< Amplifier Amc1L enable */ + REGFIELD AMC1LITOV; /*!< Amplifier Amc1L current to voltage mode enable */ + REGFIELD AMC2EN; /*!< Amplifier Amc2 enable */ + REGFIELD AMC2ITOV; /*!< Amplifier Amc2 current to voltage mode enable */ + REGFIELD ATXINEN; /*!< Amplifier Atxin enable */ + REGFIELD ATXOUTEN; /*!< Reserved for output TXOUT enable, currently not used */ + REGFIELD RXINREC; /*!< RXINR/RXINL to voice CODEC ADC routing enable */ + REGFIELD PGATXR; /*!< Transmit gain setting right - 5 bits */ + REGFIELD PGATXL; /*!< Transmit gain setting left - 5 bits */ +} REGISTER_AUDIO_TX; + +/*! + * @brief This variable is used to access the AUDIO_TX hardware register. + * + * This variable defines how to access all of the fields within the + * AUDIO_TX hardware register. The initial values consist of the offset + * and mask values needed to access each of the register fields. + */ +static const REGISTER_AUDIO_TX regAUDIO_TX = { + {0, 0x000001}, /* MC1BEN */ + {1, 0x000002}, /* MC2BEN */ + {2, 0x000004}, /* MC2BDETDBNC */ + {3, 0x000008}, /* MC2BDETEN */ + {5, 0x000020}, /* AMC1REN */ + {6, 0x000040}, /* AMC1RITOV */ + {7, 0x000080}, /* AMC1LEN */ + {8, 0x000100}, /* AMC1LITOV */ + {9, 0x000200}, /* AMC2EN */ + {10, 0x000400}, /* AMC2ITOV */ + {11, 0x000800}, /* ATXINEN */ + {12, 0x001000}, /* ATXOUTEN */ + {13, 0x002000}, /* RXINREC */ + {14, 0x07c000}, /* PGATXR */ + {19, 0xf80000} /* PGATXL */ +}; + +/*! + * @brief This structure lists all fields of the AUDIO_RX_0 hardware register. + */ +typedef struct { + REGFIELD VAUDIOON; /*!< Forces VAUDIO in active on mode */ + REGFIELD BIASEN; /*!< Audio bias enable */ + REGFIELD BIASSPEED; /*!< Turn on ramp speed of the audio bias */ + REGFIELD ASPEN; /*!< Amplifier Asp enable */ + REGFIELD ASPSEL; /*!< Asp input selector */ + REGFIELD ALSPEN; /*!< Amplifier Alsp enable */ + REGFIELD ALSPREF; /*!< Bias Alsp at common audio reference */ + REGFIELD ALSPSEL; /*!< Alsp input selector */ + REGFIELD LSPLEN; /*!< Output LSPL enable */ + REGFIELD AHSREN; /*!< Amplifier AhsR enable */ + REGFIELD AHSLEN; /*!< Amplifier AhsL enable */ + REGFIELD AHSSEL; /*!< Ahsr and Ahsl input selector */ + REGFIELD HSPGDIS; /*!< Phantom ground disable */ + REGFIELD HSDETEN; /*!< Headset detect enable */ + REGFIELD HSDETAUTOB; /*!< Amplifier state determined by headset detect */ + REGFIELD ARXOUTREN; /*!< Output RXOUTR enable */ + REGFIELD ARXOUTLEN; /*!< Output RXOUTL enable */ + REGFIELD ARXOUTSEL; /*!< Arxout input selector */ + REGFIELD CDCOUTEN; /*!< Output CDCOUT enable */ + REGFIELD HSLDETEN; /*!< Headset left channel detect enable */ + REGFIELD ADDCDC; /*!< Adder channel codec selection */ + REGFIELD ADDSTDC; /*!< Adder channel stereo DAC selection */ + REGFIELD ADDRXIN; /*!< Adder channel line in selection */ +} REGISTER_AUDIO_RX_0; + +/*! + * @brief This variable is used to access the AUDIO_RX_0 hardware register. + * + * This variable defines how to access all of the fields within the + * AUDIO_RX_0 hardware register. The initial values consist of the offset + * and mask values needed to access each of the register fields. + */ +static const REGISTER_AUDIO_RX_0 regAUDIO_RX_0 = { + {0, 0x000001}, /* VAUDIOON */ + {1, 0x000002}, /* BIASEN */ + {2, 0x000004}, /* BIASSPEED */ + {3, 0x000008}, /* ASPEN */ + {4, 0x000010}, /* ASPSEL */ + {5, 0x000020}, /* ALSPEN */ + {6, 0x000040}, /* ALSPREF */ + {7, 0x000080}, /* ALSPSEL */ + {8, 0x000100}, /* LSPLEN */ + {9, 0x000200}, /* AHSREN */ + {10, 0x000400}, /* AHSLEN */ + {11, 0x000800}, /* AHSSEL */ + {12, 0x001000}, /* HSPGDIS */ + {13, 0x002000}, /* HSDETEN */ + {14, 0x004000}, /* HSDETAUTOB */ + {15, 0x008000}, /* ARXOUTREN */ + {16, 0x010000}, /* ARXOUTLEN */ + {17, 0x020000}, /* ARXOUTSEL */ + {18, 0x040000}, /* CDCOUTEN */ + {19, 0x080000}, /* HSLDETEN */ + {21, 0x200000}, /* ADDCDC */ + {22, 0x400000}, /* ADDSTDC */ + {23, 0x800000} /* ADDRXIN */ +}; + +/*! + * @brief This structure lists all fields of the AUDIO_RX_1 hardware register. + */ +typedef struct { + REGFIELD PGARXEN; /*!< Codec receive PGA enable */ + REGFIELD PGARX; /*!< Codec receive gain setting - 4 bits */ + REGFIELD PGASTEN; /*!< Stereo DAC PGA enable */ + REGFIELD PGAST; /*!< Stereo DAC gain setting - 4 bits */ + REGFIELD ARXINEN; /*!< Amplifier Arx enable */ + REGFIELD ARXIN; /*!< Amplifier Arx additional gain setting */ + REGFIELD PGARXIN; /*!< PGArxin gain setting - 4 bits */ + REGFIELD MONO; /*!< Mono adder setting - 2 bits */ + REGFIELD BAL; /*!< Balance control - 3 bits */ + REGFIELD BALLR; /*!< Left / right balance */ +} REGISTER_AUDIO_RX_1; + +/*! + * @brief This variable is used to access the AUDIO_RX_1 hardware register. + * + * This variable defines how to access all of the fields within the + * AUDIO_RX_1 hardware register. The initial values consist of the offset + * and mask values needed to access each of the register fields. + */ +static const REGISTER_AUDIO_RX_1 regAUDIO_RX_1 = { + {0, 0x000001}, /* PGARXEN */ + {1, 0x00001e}, /* PGARX */ + {5, 0x000020}, /* PGASTEN */ + {6, 0x0003c0}, /* PGAST */ + {10, 0x000400}, /* ARXINEN */ + {11, 0x000800}, /* ARXIN */ + {12, 0x00f000}, /* PGARXIN */ + {16, 0x030000}, /* MONO */ + {18, 0x1c0000}, /* BAL */ + {21, 0x200000} /* BALLR */ +}; + +/*! Define a mask to access the entire hardware register. */ +static const unsigned int REG_FULLMASK = 0xffffff; + +/*! Reset value for the AUD_CODEC register. */ +static const unsigned int RESET_AUD_CODEC = 0x180027; + +/*! Reset value for the ST_DAC register. + * + * Note that we avoid resetting any of the arbitration bits. + */ +static const unsigned int RESET_ST_DAC = 0x0E0004; + +/*! Reset value for the SSI_NETWORK register. */ +static const unsigned int RESET_SSI_NETWORK = 0x013060; + +/*! Reset value for the AUDIO_TX register. + * + * Note that we avoid resetting any of the arbitration bits. + */ +static const unsigned int RESET_AUDIO_TX = 0x420000; + +/*! Reset value for the AUDIO_RX_0 register. */ +static const unsigned int RESET_AUDIO_RX_0 = 0x001000; + +/*! Reset value for the AUDIO_RX_1 register. */ +static const unsigned int RESET_AUDIO_RX_1 = 0x00D35A; + +/*! Reset mask for the SSI network Vcodec part. first 12 bits + * 0 - 11 */ +static const unsigned int REG_SSI_VCODEC_MASK = 0x000fff; + +/*! Reset mask for the SSI network STDAC part. last 12 bits + * 12 - 24 */ +static const unsigned int REG_SSI_STDAC_MASK = 0xfff000; + +/*! Constant NULL value for initializing/reseting the audio handles. */ +static const PMIC_AUDIO_HANDLE AUDIO_HANDLE_NULL = (PMIC_AUDIO_HANDLE) NULL; + +/*! + * @brief This structure maintains the current state of the Stereo DAC. + */ +typedef struct { + PMIC_AUDIO_HANDLE handle; /*!< Handle used to access + the Stereo DAC. */ + HANDLE_STATE handleState; /*!< Current handle state. */ + PMIC_AUDIO_DATA_BUS busID; /*!< Data bus used to access + the Stereo DAC. */ + bool protocol_set; + PMIC_AUDIO_BUS_PROTOCOL protocol; /*!< Data bus protocol. */ + PMIC_AUDIO_BUS_MODE masterSlave; /*!< Master/Slave mode + select. */ + PMIC_AUDIO_NUMSLOTS numSlots; /*!< Number of timeslots + used. */ + PMIC_AUDIO_CALLBACK callback; /*!< Event notification + callback function + pointer. */ + PMIC_AUDIO_EVENTS eventMask; /*!< Event notification mask. */ + PMIC_AUDIO_CLOCK_IN_SOURCE clockIn; /*!< Stereo DAC clock input + source select. */ + PMIC_AUDIO_STDAC_SAMPLING_RATE samplingRate; /*!< Stereo DAC sampling rate + select. */ + PMIC_AUDIO_STDAC_CLOCK_IN_FREQ clockFreq; /*!< Stereo DAC clock input + frequency. */ + PMIC_AUDIO_CLOCK_INVERT invert; /*!< Stereo DAC clock signal + invert select. */ + PMIC_AUDIO_STDAC_TIMESLOTS timeslot; /*!< Stereo DAC data + timeslots select. */ + PMIC_AUDIO_STDAC_CONFIG config; /*!< Stereo DAC configuration + options. */ +} PMIC_AUDIO_STDAC_STATE; + +/*! + * @brief This variable maintains the current state of the Stereo DAC. + * + * This variable tracks the current state of the Stereo DAC audio hardware + * along with any information that is required by the device driver to + * manage the hardware (e.g., callback functions and event notification + * masks). + * + * The initial values represent the reset/power on state of the Stereo DAC. + */ +static PMIC_AUDIO_STDAC_STATE stDAC = { + (PMIC_AUDIO_HANDLE) NULL, /* handle */ + HANDLE_FREE, /* handleState */ + AUDIO_DATA_BUS_1, /* busID */ + false, + NORMAL_MSB_JUSTIFIED_MODE, /* protocol */ + BUS_MASTER_MODE, /* masterSlave */ + USE_2_TIMESLOTS, /* numSlots */ + (PMIC_AUDIO_CALLBACK) NULL, /* callback */ + (PMIC_AUDIO_EVENTS) NULL, /* eventMask */ + CLOCK_IN_CLIA, /* clockIn */ + STDAC_RATE_44_1_KHZ, /* samplingRate */ + STDAC_CLI_13MHZ, /* clockFreq */ + NO_INVERT, /* invert */ + USE_TS0_TS1, /* timeslot */ + (PMIC_AUDIO_STDAC_CONFIG) 0 /* config */ +}; + +/*! + * @brief This structure maintains the current state of the Voice CODEC. + */ +typedef struct { + PMIC_AUDIO_HANDLE handle; /*!< Handle used to access + the Voice CODEC. */ + HANDLE_STATE handleState; /*!< Current handle state. */ + PMIC_AUDIO_DATA_BUS busID; /*!< Data bus used to access + the Voice CODEC. */ + bool protocol_set; + PMIC_AUDIO_BUS_PROTOCOL protocol; /*!< Data bus protocol. */ + PMIC_AUDIO_BUS_MODE masterSlave; /*!< Master/Slave mode + select. */ + PMIC_AUDIO_NUMSLOTS numSlots; /*!< Number of timeslots + used. */ + PMIC_AUDIO_CALLBACK callback; /*!< Event notification + callback function + pointer. */ + PMIC_AUDIO_EVENTS eventMask; /*!< Event notification + mask. */ + PMIC_AUDIO_CLOCK_IN_SOURCE clockIn; /*!< Voice CODEC clock input + source select. */ + PMIC_AUDIO_VCODEC_SAMPLING_RATE samplingRate; /*!< Voice CODEC sampling + rate select. */ + PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ clockFreq; /*!< Voice CODEC clock input + frequency. */ + PMIC_AUDIO_CLOCK_INVERT invert; /*!< Voice CODEC clock + signal invert select. */ + PMIC_AUDIO_VCODEC_TIMESLOT timeslot; /*!< Voice CODEC data + timeslot select. */ + PMIC_AUDIO_VCODEC_TIMESLOT secondaryTXtimeslot; + + PMIC_AUDIO_VCODEC_CONFIG config; /*!< Voice CODEC + configuration + options. */ + PMIC_MICROPHONE_STATE leftChannelMic; /*!< Left channel + microphone + configuration. */ + PMIC_MICROPHONE_STATE rightChannelMic; /*!< Right channel + microphone + configuration. */ +} PMIC_AUDIO_VCODEC_STATE; + +/*! + * @brief This variable maintains the current state of the Voice CODEC. + * + * This variable tracks the current state of the Voice CODEC audio hardware + * along with any information that is required by the device driver to + * manage the hardware (e.g., callback functions and event notification + * masks). + * + * The initial values represent the reset/power on state of the Voice CODEC. + */ +static PMIC_AUDIO_VCODEC_STATE vCodec = { + (PMIC_AUDIO_HANDLE) NULL, /* handle */ + HANDLE_FREE, /* handleState */ + AUDIO_DATA_BUS_2, /* busID */ + false, + NETWORK_MODE, /* protocol */ + BUS_SLAVE_MODE, /* masterSlave */ + USE_4_TIMESLOTS, /* numSlots */ + (PMIC_AUDIO_CALLBACK) NULL, /* callback */ + (PMIC_AUDIO_EVENTS) NULL, /* eventMask */ + CLOCK_IN_CLIB, /* clockIn */ + VCODEC_RATE_8_KHZ, /* samplingRate */ + VCODEC_CLI_13MHZ, /* clockFreq */ + NO_INVERT, /* invert */ + USE_TS0, /* timeslot pri */ + USE_TS2, /* timeslot sec TX */ + INPUT_HIGHPASS_FILTER | OUTPUT_HIGHPASS_FILTER, /* config */ + /* leftChannelMic */ + {NO_MIC, /* mic */ + MICROPHONE_OFF, /* micOnOff */ + AMP_OFF, /* ampMode */ + MIC_GAIN_0DB /* gain */ + }, + /* rightChannelMic */ + {NO_MIC, /* mic */ + MICROPHONE_OFF, /* micOnOff */ + AMP_OFF, /* ampMode */ + MIC_GAIN_0DB /* gain */ + } +}; + +/*! + * @brief This maintains the current state of the External Stereo Input. + */ +typedef struct { + PMIC_AUDIO_HANDLE handle; /*!< Handle used to access the + External Stereo Inputs. */ + HANDLE_STATE handleState; /*!< Current handle state. */ + PMIC_AUDIO_CALLBACK callback; /*!< Event notification callback + function pointer. */ + PMIC_AUDIO_EVENTS eventMask; /*!< Event notification mask. */ + PMIC_AUDIO_STEREO_IN_GAIN inputGain; /*!< External Stereo Input + amplifier gain level. */ +} PMIC_AUDIO_EXT_STEREO_IN_STATE; + +/*! + * @brief This maintains the current state of the External Stereo Input. + * + * This variable tracks the current state of the External Stereo Input audio + * hardware along with any information that is required by the device driver + * to manage the hardware (e.g., callback functions and event notification + * masks). + * + * The initial values represent the reset/power on state of the External + * Stereo Input. + */ +static PMIC_AUDIO_EXT_STEREO_IN_STATE extStereoIn = { + (PMIC_AUDIO_HANDLE) NULL, /* handle */ + HANDLE_FREE, /* handleState */ + (PMIC_AUDIO_CALLBACK) NULL, /* callback */ + (PMIC_AUDIO_EVENTS) NULL, /* eventMask */ + STEREO_IN_GAIN_0DB /* inputGain */ +}; + +/*! + * @brief This maintains the current state of the callback & Eventmask. + */ +typedef struct { + PMIC_AUDIO_CALLBACK callback; /*!< Event notification callback + function pointer. */ + PMIC_AUDIO_EVENTS eventMask; /*!< Event notification mask. */ +} PMIC_AUDIO_EVENT_STATE; + +static PMIC_AUDIO_EVENT_STATE event_state = { + (PMIC_AUDIO_CALLBACK) NULL, /*Callback */ + (PMIC_AUDIO_EVENTS) NULL, /* EventMask */ + +}; + +/*! + * @brief This maintains the current state of the Audio Output Section. + */ +typedef struct { + PMIC_AUDIO_OUTPUT_PORT outputPort; /*!< Current audio + output port. */ + PMIC_AUDIO_OUTPUT_PGA_GAIN vCodecoutputPGAGain; /*!< Output PGA gain + level codec */ + PMIC_AUDIO_OUTPUT_PGA_GAIN stDacoutputPGAGain; /*!< Output PGA gain + level stDAC */ + PMIC_AUDIO_OUTPUT_PGA_GAIN extStereooutputPGAGain; /*!< Output PGA gain + level stereo ext */ + PMIC_AUDIO_OUTPUT_BALANCE_GAIN balanceLeftGain; /*!< Left channel + balance gain + level. */ + PMIC_AUDIO_OUTPUT_BALANCE_GAIN balanceRightGain; /*!< Right channel + balance gain + level. */ + PMIC_AUDIO_MONO_ADDER_OUTPUT_GAIN monoAdderGain; /*!< Mono adder gain + level. */ + PMIC_AUDIO_OUTPUT_CONFIG config; /*!< Audio output + section config + options. */ + PMIC_AUDIO_VCODEC_OUTPUT_PATH vCodecOut; + +} PMIC_AUDIO_AUDIO_OUTPUT_STATE; + +/*! + * @brief This variable maintains the current state of the Audio Output Section. + * + * This variable tracks the current state of the Audio Output Section. + * + * The initial values represent the reset/power on state of the Audio + * Output Section. + */ +static PMIC_AUDIO_AUDIO_OUTPUT_STATE audioOutput = { + (PMIC_AUDIO_OUTPUT_PORT) NULL, /* outputPort */ + OUTPGA_GAIN_0DB, /* outputPGAGain */ + OUTPGA_GAIN_0DB, /* outputPGAGain */ + OUTPGA_GAIN_0DB, /* outputPGAGain */ + BAL_GAIN_0DB, /* balanceLeftGain */ + BAL_GAIN_0DB, /* balanceRightGain */ + MONOADD_GAIN_0DB, /* monoAdderGain */ + (PMIC_AUDIO_OUTPUT_CONFIG) 0, /* config */ + VCODEC_DIRECT_OUT +}; + +/*! The current headset status. */ +static HEADSET_STATUS headsetState = NO_HEADSET; + +/* Removed PTT variable */ +/*! Define a 1 ms wait interval that is needed to ensure that certain + * hardware operations are successfully completed. + */ +static const unsigned long delay_1ms = (HZ / 1000); + +/*! + * @brief This spinlock is used to provide mutual exclusion. + * + * Create a spinlock that can be used to provide mutually exclusive + * read/write access to the globally accessible data structures + * that were defined above. Mutually exclusive access is required to + * ensure that the audio data structures are consistent at all times + * when possibly accessed by multiple threads of execution (for example, + * while simultaneously handling a user request and an interrupt event). + * + * We need to use a spinlock whenever we do need to provide mutual + * exclusion while possibly executing in a hardware interrupt context. + * Spinlocks should be held for the minimum time that is necessary + * because hardware interrupts are disabled while a spinlock is held. + * + */ + +static spinlock_t lock = SPIN_LOCK_UNLOCKED; +/*! + * @brief This mutex is used to provide mutual exclusion. + * + * Create a mutex that can be used to provide mutually exclusive + * read/write access to the globally accessible data structures + * that were defined above. Mutually exclusive access is required to + * ensure that the audio data structures are consistent at all times + * when possibly accessed by multiple threads of execution. + * + * Note that we use a mutex instead of the spinlock whenever disabling + * interrupts while in the critical section is not required. This helps + * to minimize kernel interrupt handling latency. + */ +static DECLARE_MUTEX(mutex); + +/*! + * @brief Global variable to track currently active interrupt events. + * + * This global variable is used to keep track of all of the currently + * active interrupt events for the audio driver. Note that access to this + * variable may occur while within an interrupt context and, therefore, + * must be guarded by using a spinlock. + */ +/* static PMIC_CORE_EVENT eventID = 0; */ + +/* Prototypes for all static audio driver functions. */ +/* +static PMIC_STATUS pmic_audio_mic_boost_enable(void); +static PMIC_STATUS pmic_audio_mic_boost_disable(void);*/ +static PMIC_STATUS pmic_audio_close_handle(const PMIC_AUDIO_HANDLE handle); +static PMIC_STATUS pmic_audio_reset_device(const PMIC_AUDIO_HANDLE handle); + +static PMIC_STATUS pmic_audio_deregister(void *callback, + PMIC_AUDIO_EVENTS * const eventMask); + +/************************************************************************* + * Audio device access APIs. + ************************************************************************* + */ + +/*! + * @name General Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Audio + * hardware. + */ +/*@{*/ + +PMIC_STATUS pmic_audio_set_autodetect(int val) +{ + PMIC_STATUS status; + unsigned int reg_mask = 0, reg_write = 0; + reg_mask = SET_BITS(regAUDIO_RX_0, VAUDIOON, 1); + status = pmic_write_reg(REG_AUDIO_RX_0, reg_mask, reg_mask); + if (status != PMIC_SUCCESS) + return status; + reg_mask = 0; + if (val == 1) { + reg_write = SET_BITS(regAUDIO_RX_0, HSDETEN, 1) | + SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1); + } else { + reg_write = 0; + } + reg_mask = + SET_BITS(regAUDIO_RX_0, HSDETEN, 1) | SET_BITS(regAUDIO_RX_0, + HSDETAUTOB, 1); + status = pmic_write_reg(REG_AUDIO_RX_0, reg_write, reg_mask); + + return status; +} + +/*! + * @brief Request exclusive access to the PMIC Audio hardware. + * + * Attempt to open and gain exclusive access to a key PMIC audio hardware + * component (e.g., the Stereo DAC or the Voice CODEC). Depending upon the + * type of audio operation that is desired and the nature of the audio data + * stream, the Stereo DAC and/or the Voice CODEC will be a required hardware + * component and needs to be acquired by calling this function. + * + * If the open request is successful, then a numeric handle is returned + * and this handle must be used in all subsequent function calls to complete + * the configuration of either the Stereo DAC or the Voice CODEC and along + * with any other associated audio hardware components that will be needed. + * + * The same handle must also be used in the close call when use of the PMIC + * audio hardware is no longer required. + * + * The open request will fail if the requested audio hardware component has + * already been acquired by a previous open call but not yet closed. + * + * @param handle Device handle to be used for subsequent PMIC + * audio API calls. + * @param device The required PMIC audio hardware component. + * + * @retval PMIC_SUCCESS If the open request was successful + * @retval PMIC_PARAMETER_ERROR If the handle argument is NULL. + * @retval PMIC_ERROR If the audio hardware component is + * unavailable. + */ +PMIC_STATUS pmic_audio_open(PMIC_AUDIO_HANDLE * const handle, + const PMIC_AUDIO_SOURCE device) +{ + PMIC_STATUS rc = PMIC_ERROR; + + if (handle == (PMIC_AUDIO_HANDLE *) NULL) { + /* Do not dereference a NULL pointer. */ + return PMIC_PARAMETER_ERROR; + } + + /* We only need to acquire a mutex here because the interrupt handler + * never modifies the device handle or device handle state. Therefore, + * we don't need to worry about conflicts with the interrupt handler + * or the need to execute in an interrupt context. + * + * But we do need a critical section here to avoid problems in case + * multiple calls to pmic_audio_open() are made since we can only allow + * one of them to succeed. + */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + /* Check the current device handle state and acquire the handle if + * it is available. + */ + + if ((device == STEREO_DAC) && (stDAC.handleState == HANDLE_FREE)) { + stDAC.handle = (PMIC_AUDIO_HANDLE) (&stDAC); + stDAC.handleState = HANDLE_IN_USE; + *handle = stDAC.handle; + rc = PMIC_SUCCESS; + } else if ((device == VOICE_CODEC) + && (vCodec.handleState == HANDLE_FREE)) { + vCodec.handle = (PMIC_AUDIO_HANDLE) (&vCodec); + vCodec.handleState = HANDLE_IN_USE; + *handle = vCodec.handle; + rc = PMIC_SUCCESS; + } else if ((device == EXTERNAL_STEREO_IN) && + (extStereoIn.handleState == HANDLE_FREE)) { + extStereoIn.handle = (PMIC_AUDIO_HANDLE) (&extStereoIn); + extStereoIn.handleState = HANDLE_IN_USE; + *handle = extStereoIn.handle; + rc = PMIC_SUCCESS; + } else { + *handle = AUDIO_HANDLE_NULL; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Terminate further access to the PMIC audio hardware. + * + * Terminate further access to the PMIC audio hardware that was previously + * acquired by calling pmic_audio_open(). This now allows another thread to + * successfully call pmic_audio_open() to gain access. + * + * Note that we will shutdown/reset the Voice CODEC or Stereo DAC as well as + * any associated audio input/output components that are no longer required. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the close request was successful. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_audio_close(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* We need a critical section here to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + /* We can now call pmic_audio_close_handle() to actually do the work. */ + rc = pmic_audio_close_handle(handle); + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Configure the data bus protocol to be used. + * + * Provide the parameters needed to properly configure the audio data bus + * protocol so that data can be read/written to either the Stereo DAC or + * the Voice CODEC. + * + * @param handle Device handle from pmic_audio_open() call. + * @param busID Select data bus to be used. + * @param protocol Select the data bus protocol. + * @param masterSlave Select the data bus timing mode. + * @param numSlots Define the number of timeslots (only if in + * master mode). + * + * @retval PMIC_SUCCESS If the protocol was successful configured. + * @retval PMIC_PARAMETER_ERROR If the handle or the protocol parameters + * are invalid. + */ +PMIC_STATUS pmic_audio_set_protocol(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_DATA_BUS busID, + const PMIC_AUDIO_BUS_PROTOCOL protocol, + const PMIC_AUDIO_BUS_MODE masterSlave, + const PMIC_AUDIO_NUMSLOTS numSlots) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + const unsigned int ST_DAC_MASK = SET_BITS(regST_DAC, STDCSSISEL, 1) | + SET_BITS(regST_DAC, STDCFS, 3) | SET_BITS(regST_DAC, STDCSM, 1); + + unsigned int reg_mask; + /*unsigned int VCODEC_MASK = SET_BITS(regAUD_CODEC, CDCSSISEL, 1) | + SET_BITS(regAUD_CODEC, CDCFS, 3) | SET_BITS(regAUD_CODEC, CDCSM, 1); */ + + unsigned int SSI_NW_MASK = SET_BITS(regSSI_NETWORK, STDCSLOTS, 1); + unsigned int reg_value = 0; + unsigned int ssi_nw_value = 0; + + /* Enter a critical section so that we can ensure only one + * state change request is completed at a time. + */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if (handle == (PMIC_AUDIO_HANDLE) NULL) { + rc = PMIC_PARAMETER_ERROR; + } else { + if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) { + if ((stDAC.handleState == HANDLE_IN_USE) && + (stDAC.busID == busID) && (stDAC.protocol_set)) { + pr_debug("The requested bus already in USE\n"); + rc = PMIC_PARAMETER_ERROR; + } else if ((masterSlave == BUS_MASTER_MODE) + && (numSlots != USE_4_TIMESLOTS)) { + pr_debug + ("mc13783 supports only 4 slots in Master mode\n"); + rc = PMIC_NOT_SUPPORTED; + } else if ((masterSlave == BUS_SLAVE_MODE) + && (numSlots != USE_4_TIMESLOTS)) { + pr_debug + ("Driver currently supports only 4 slots in Slave mode\n"); + rc = PMIC_NOT_SUPPORTED; + } else if (!((protocol == NETWORK_MODE) || + (protocol == I2S_MODE))) { + pr_debug + ("mc13783 Voice codec works only in Network and I2S modes\n"); + rc = PMIC_NOT_SUPPORTED; + } else { + pr_debug + ("Proceeding to configure Voice Codec\n"); + if (busID == AUDIO_DATA_BUS_1) { + reg_value = + SET_BITS(regAUD_CODEC, CDCSSISEL, + 0); + } else { + reg_value = + SET_BITS(regAUD_CODEC, CDCSSISEL, + 1); + } + reg_mask = SET_BITS(regAUD_CODEC, CDCSSISEL, 1); + if (PMIC_SUCCESS != + pmic_write_reg(REG_AUDIO_CODEC, + reg_value, reg_mask)) + return PMIC_ERROR; + + if (masterSlave == BUS_MASTER_MODE) { + reg_value = + SET_BITS(regAUD_CODEC, CDCSM, 0); + } else { + reg_value = + SET_BITS(regAUD_CODEC, CDCSM, 1); + } + reg_mask = SET_BITS(regAUD_CODEC, CDCSM, 1); + if (PMIC_SUCCESS != + pmic_write_reg(REG_AUDIO_CODEC, + reg_value, reg_mask)) + return PMIC_ERROR; + + if (protocol == NETWORK_MODE) { + reg_value = + SET_BITS(regAUD_CODEC, CDCFS, 1); + } else { /* protocol == I2S, other options have been already eliminated */ + reg_value = + SET_BITS(regAUD_CODEC, CDCFS, 2); + } + reg_mask = SET_BITS(regAUD_CODEC, CDCFS, 3); + if (PMIC_SUCCESS != + pmic_write_reg(REG_AUDIO_CODEC, + reg_value, reg_mask)) + return PMIC_ERROR; + + ssi_nw_value = + SET_BITS(regSSI_NETWORK, CDCFSDLY, 1); + /*if (pmic_write_reg + (REG_AUDIO_CODEC, reg_value, + VCODEC_MASK) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { */ + vCodec.busID = busID; + vCodec.protocol = protocol; + vCodec.masterSlave = masterSlave; + vCodec.numSlots = numSlots; + vCodec.protocol_set = true; + //pmic_write_reg(REG_AUDIO_SSI_NETWORK, ssi_nw_value, ssi_nw_value); + + pr_debug + ("mc13783 Voice codec successfully configured\n"); + rc = PMIC_SUCCESS; + //} + + } + + } else if ((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) { + if ((vCodec.handleState == HANDLE_IN_USE) && + (vCodec.busID == busID) && (vCodec.protocol_set)) { + pr_debug("The requested bus already in USE\n"); + rc = PMIC_PARAMETER_ERROR; + } else if (((protocol == NORMAL_MSB_JUSTIFIED_MODE) || + (protocol == I2S_MODE)) + && (numSlots != USE_2_TIMESLOTS)) { + pr_debug + ("STDAC uses only 2 slots in Normal and I2S modes\n"); + rc = PMIC_PARAMETER_ERROR; + } else if ((protocol == NETWORK_MODE) && + !((numSlots == USE_2_TIMESLOTS) || + (numSlots == USE_4_TIMESLOTS) || + (numSlots == USE_8_TIMESLOTS))) { + pr_debug + ("STDAC uses only 2,4 or 8 slots in Network mode\n"); + rc = PMIC_PARAMETER_ERROR; + } else if (protocol == SPD_IF_MODE) { + pr_debug + ("STDAC driver currently does not support SPD IF mode\n"); + rc = PMIC_NOT_SUPPORTED; + } else { + pr_debug + ("Proceeding to configure Stereo DAC\n"); + if (busID == AUDIO_DATA_BUS_1) { + reg_value = + SET_BITS(regST_DAC, STDCSSISEL, 0); + } else { + reg_value = + SET_BITS(regST_DAC, STDCSSISEL, 1); + } + if (masterSlave == BUS_MASTER_MODE) { + reg_value |= + SET_BITS(regST_DAC, STDCSM, 0); + } else { + reg_value |= + SET_BITS(regST_DAC, STDCSM, 1); + } + if (protocol == NETWORK_MODE) { + reg_value |= + SET_BITS(regST_DAC, STDCFS, 1); + } else if (protocol == + NORMAL_MSB_JUSTIFIED_MODE) { + reg_value |= + SET_BITS(regST_DAC, STDCFS, 0); + } else { /* I2S mode as the other option has already been eliminated */ + reg_value |= + SET_BITS(regST_DAC, STDCFS, 2); + } + + if (pmic_write_reg + (REG_AUDIO_STEREO_DAC, + reg_value, ST_DAC_MASK) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + if (numSlots == USE_2_TIMESLOTS) { + reg_value = + SET_BITS(regSSI_NETWORK, + STDCSLOTS, 3); + } else if (numSlots == USE_4_TIMESLOTS) { + reg_value = + SET_BITS(regSSI_NETWORK, + STDCSLOTS, 2); + } else { /* Use 8 timeslots - L , R and 6 other */ + reg_value = + SET_BITS(regSSI_NETWORK, + STDCSLOTS, 1); + } + if (pmic_write_reg + (REG_AUDIO_SSI_NETWORK, + reg_value, + SSI_NW_MASK) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + stDAC.busID = busID; + stDAC.protocol = protocol; + stDAC.protocol_set = true; + stDAC.masterSlave = masterSlave; + stDAC.numSlots = numSlots; + pr_debug + ("mc13783 Stereo DAC successfully configured\n"); + rc = PMIC_SUCCESS; + } + } + + } + } else { + rc = PMIC_PARAMETER_ERROR; + /* Handle can only be Voice Codec or Stereo DAC */ + pr_debug("Handles only STDAC and VCODEC\n"); + } + + } + /* Exit critical section. */ + up(&mutex); + return rc; +} + +/*! + * @brief Retrieve the current data bus protocol configuration. + * + * Retrieve the parameters that define the current audio data bus protocol. + * + * @param handle Device handle from pmic_audio_open() call. + * @param busID The data bus being used. + * @param protocol The data bus protocol being used. + * @param masterSlave The data bus timing mode being used. + * @param numSlots The number of timeslots being used (if in + * master mode). + * + * @retval PMIC_SUCCESS If the protocol was successful retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_audio_get_protocol(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_DATA_BUS * const busID, + PMIC_AUDIO_BUS_PROTOCOL * const protocol, + PMIC_AUDIO_BUS_MODE * const masterSlave, + PMIC_AUDIO_NUMSLOTS * const numSlots) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + if ((busID != (PMIC_AUDIO_DATA_BUS *) NULL) && + (protocol != (PMIC_AUDIO_BUS_PROTOCOL *) NULL) && + (masterSlave != (PMIC_AUDIO_BUS_MODE *) NULL) && + (numSlots != (PMIC_AUDIO_NUMSLOTS *) NULL)) { + /* Enter a critical section so that we return a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) { + *busID = stDAC.busID; + *protocol = stDAC.protocol; + *masterSlave = stDAC.masterSlave; + *numSlots = stDAC.numSlots; + rc = PMIC_SUCCESS; + } else if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) { + *busID = vCodec.busID; + *protocol = vCodec.protocol; + *masterSlave = vCodec.masterSlave; + *numSlots = vCodec.numSlots; + rc = PMIC_SUCCESS; + } + + /* Exit critical section. */ + up(&mutex); + } + + return rc; +} + +/*! + * @brief Enable the Stereo DAC or the Voice CODEC. + * + * Explicitly enable the Stereo DAC or the Voice CODEC to begin audio + * playback or recording as required. This should only be done after + * successfully configuring all of the associated audio components (e.g., + * microphones, amplifiers, etc.). + * + * Note that the timed delays used in this function are necessary to + * ensure reliable operation of the Voice CODEC and Stereo DAC. The + * Stereo DAC seems to be particularly sensitive and it has been observed + * to fail to generate the required master mode clock signals if it is + * not allowed enough time to initialize properly. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the device was successful enabled. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_ERROR If the device could not be enabled. + */ +PMIC_STATUS pmic_audio_enable(const PMIC_AUDIO_HANDLE handle) +{ + const unsigned int AUDIO_BIAS_ENABLE = SET_BITS(regAUDIO_RX_0, + VAUDIOON, 1); + const unsigned int STDAC_ENABLE = SET_BITS(regST_DAC, STDCEN, 1); + const unsigned int VCODEC_ENABLE = SET_BITS(regAUD_CODEC, CDCEN, 1); + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + pmic_write_reg(REG_AUDIO_RX_0, AUDIO_BIAS_ENABLE, + AUDIO_BIAS_ENABLE); + reg_mask = + SET_BITS(regAUDIO_RX_0, HSDETEN, + 1) | SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1); + reg_write = + SET_BITS(regAUDIO_RX_0, HSDETEN, + 1) | SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1); + rc = pmic_write_reg(REG_AUDIO_RX_0, reg_write, reg_mask); + if (rc == PMIC_SUCCESS) + pr_debug("pmic_audio_enable\n"); + /* We can enable the Stereo DAC. */ + rc = pmic_write_reg(REG_AUDIO_STEREO_DAC, + STDAC_ENABLE, STDAC_ENABLE); + /*pmic_read_reg(REG_AUDIO_STEREO_DAC, ®_value); */ + if (rc != PMIC_SUCCESS) { + pr_debug("Failed to enable the Stereo DAC\n"); + rc = PMIC_ERROR; + } + } else if ((handle == vCodec.handle) + && (vCodec.handleState == HANDLE_IN_USE)) { + /* Must first set the audio bias bit to power up the audio circuits. */ + pmic_write_reg(REG_AUDIO_RX_0, AUDIO_BIAS_ENABLE, + AUDIO_BIAS_ENABLE); + reg_mask = SET_BITS(regAUDIO_RX_0, HSDETEN, 1) | + SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1); + reg_write = SET_BITS(regAUDIO_RX_0, HSDETEN, 1) | + SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1); + rc = pmic_write_reg(REG_AUDIO_RX_0, reg_write, reg_mask); + + /* Then we can enable the Voice CODEC. */ + rc = pmic_write_reg(REG_AUDIO_CODEC, VCODEC_ENABLE, + VCODEC_ENABLE); + + /* pmic_read_reg(REG_AUDIO_CODEC, ®_value); */ + if (rc != PMIC_SUCCESS) { + pr_debug("Failed to enable the Voice codec\n"); + rc = PMIC_ERROR; + } + } + /* Exit critical section. */ + up(&mutex); + return rc; +} + +/*! + * @brief Disable the Stereo DAC or the Voice CODEC. + * + * Explicitly disable the Stereo DAC or the Voice CODEC to end audio + * playback or recording as required. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the device was successful disabled. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_ERROR If the device could not be disabled. + */ +PMIC_STATUS pmic_audio_disable(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + const unsigned int STDAC_DISABLE = SET_BITS(regST_DAC, STDCEN, 1); + const unsigned int VCODEC_DISABLE = SET_BITS(regAUD_CODEC, CDCEN, 1); + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + rc = pmic_write_reg(REG_AUDIO_STEREO_DAC, 0, STDAC_DISABLE); + } else if ((handle == vCodec.handle) + && (vCodec.handleState == HANDLE_IN_USE)) { + rc = pmic_write_reg(REG_AUDIO_CODEC, 0, VCODEC_DISABLE); + } + if (rc == PMIC_SUCCESS) { + pr_debug("Disabled successfully\n"); + } + /* Exit critical section. */ + up(&mutex); + return rc; +} + +/*! + * @brief Reset the selected audio hardware control registers to their + * power on state. + * + * This resets all of the audio hardware control registers currently + * associated with the device handle back to their power on states. For + * example, if the handle is associated with the Stereo DAC and a + * specific output port and output amplifiers, then this function will + * reset all of those components to their initial power on state. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the reset operation was successful. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_ERROR If the reset was unsuccessful. + */ +PMIC_STATUS pmic_audio_reset(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + rc = pmic_audio_reset_device(handle); + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Reset all audio hardware control registers to their power on state. + * + * This resets all of the audio hardware control registers back to their + * power on states. Use this function with care since it also invalidates + * (i.e., automatically closes) all currently opened device handles. + * + * @retval PMIC_SUCCESS If the reset operation was successful. + * @retval PMIC_ERROR If the reset was unsuccessful. + */ +PMIC_STATUS pmic_audio_reset_all(void) +{ + PMIC_STATUS rc = PMIC_SUCCESS; + unsigned int audio_ssi_reset = 0; + unsigned int audio_rx1_reset = 0; + /* We need a critical section here to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + /* First close all opened device handles, also deregisters callbacks. */ + pmic_audio_close_handle(stDAC.handle); + pmic_audio_close_handle(vCodec.handle); + pmic_audio_close_handle(extStereoIn.handle); + + if (pmic_write_reg(REG_AUDIO_RX_1, RESET_AUDIO_RX_1, + PMIC_ALL_BITS) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + audio_rx1_reset = 1; + } + if (pmic_write_reg(REG_AUDIO_SSI_NETWORK, RESET_SSI_NETWORK, + PMIC_ALL_BITS) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + audio_ssi_reset = 1; + } + if (pmic_write_reg + (REG_AUDIO_STEREO_DAC, RESET_ST_DAC, + PMIC_ALL_BITS) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + /* Also reset the driver state information to match. Note that we + * keep the device handle and event callback settings unchanged + * since these don't affect the actual hardware and we rely on + * the user to explicitly close the handle or deregister callbacks + */ + if (audio_ssi_reset) { + /* better to check if SSI is also reset as some fields are represennted in SSI reg */ + stDAC.busID = AUDIO_DATA_BUS_1; + stDAC.protocol = NORMAL_MSB_JUSTIFIED_MODE; + stDAC.masterSlave = BUS_MASTER_MODE; + stDAC.protocol_set = false; + stDAC.numSlots = USE_2_TIMESLOTS; + stDAC.clockIn = CLOCK_IN_CLIA; + stDAC.samplingRate = STDAC_RATE_44_1_KHZ; + stDAC.clockFreq = STDAC_CLI_13MHZ; + stDAC.invert = NO_INVERT; + stDAC.timeslot = USE_TS0_TS1; + stDAC.config = (PMIC_AUDIO_STDAC_CONFIG) 0; + } + } + + if (pmic_write_reg(REG_AUDIO_CODEC, RESET_AUD_CODEC, + PMIC_ALL_BITS) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + /* Also reset the driver state information to match. Note that we + * keep the device handle and event callback settings unchanged + * since these don't affect the actual hardware and we rely on + * the user to explicitly close the handle or deregister callbacks + */ + if (audio_ssi_reset) { + vCodec.busID = AUDIO_DATA_BUS_2; + vCodec.protocol = NETWORK_MODE; + vCodec.masterSlave = BUS_SLAVE_MODE; + vCodec.protocol_set = false; + vCodec.numSlots = USE_4_TIMESLOTS; + vCodec.clockIn = CLOCK_IN_CLIB; + vCodec.samplingRate = VCODEC_RATE_8_KHZ; + vCodec.clockFreq = VCODEC_CLI_13MHZ; + vCodec.invert = NO_INVERT; + vCodec.timeslot = USE_TS0; + vCodec.config = + INPUT_HIGHPASS_FILTER | OUTPUT_HIGHPASS_FILTER; + } + } + + if (pmic_write_reg(REG_AUDIO_RX_0, RESET_AUDIO_RX_0, + PMIC_ALL_BITS) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + /* Also reset the driver state information to match. */ + audioOutput.outputPort = (PMIC_AUDIO_OUTPUT_PORT) NULL; + audioOutput.vCodecoutputPGAGain = OUTPGA_GAIN_0DB; + audioOutput.stDacoutputPGAGain = OUTPGA_GAIN_0DB; + audioOutput.extStereooutputPGAGain = OUTPGA_GAIN_0DB; + audioOutput.balanceLeftGain = BAL_GAIN_0DB; + audioOutput.balanceRightGain = BAL_GAIN_0DB; + audioOutput.monoAdderGain = MONOADD_GAIN_0DB; + audioOutput.config = (PMIC_AUDIO_OUTPUT_CONFIG) 0; + audioOutput.vCodecOut = VCODEC_DIRECT_OUT; + } + + if (pmic_write_reg(REG_AUDIO_TX, RESET_AUDIO_TX, + PMIC_ALL_BITS) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + /* Also reset the driver state information to match. Note that we + * reset the vCodec fields since all of the input/recording + * devices are only connected to the Voice CODEC and are managed + * as part of the Voice CODEC state. + */ + if (audio_rx1_reset) { + vCodec.leftChannelMic.mic = NO_MIC; + vCodec.leftChannelMic.micOnOff = MICROPHONE_OFF; + vCodec.leftChannelMic.ampMode = CURRENT_TO_VOLTAGE; + vCodec.leftChannelMic.gain = MIC_GAIN_0DB; + vCodec.rightChannelMic.mic = NO_MIC; + vCodec.rightChannelMic.micOnOff = MICROPHONE_OFF; + vCodec.rightChannelMic.ampMode = AMP_OFF; + vCodec.rightChannelMic.gain = MIC_GAIN_0DB; + } + } + /* Finally, also reset any global state variables. */ + headsetState = NO_HEADSET; + /* Exit the critical section. */ + up(&mutex); + return rc; +} + +/*! + * @brief Set the Audio callback function. + * + * Register a callback function that will be used to signal PMIC audio + * events. For example, the OSS audio driver should register a callback + * function in order to be notified of headset connect/disconnect events. + * + * @param func A pointer to the callback function. + * @param eventMask A mask selecting events to be notified. + * @param hs_state To know the headset state. + * + * + * + * @retval PMIC_SUCCESS If the callback was successfully + * registered. + * @retval PMIC_PARAMETER_ERROR If the handle or the eventMask is invalid. + */ +PMIC_STATUS pmic_audio_set_callback(void *func, + const PMIC_AUDIO_EVENTS eventMask, + PMIC_HS_STATE * hs_state) +{ + unsigned long flags; + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + pmic_event_callback_t eventNotify; + + /* We need to start a critical section here to ensure a consistent state + * in case simultaneous calls to pmic_audio_set_callback() are made. In + * that case, we must serialize the calls to ensure that the "callback" + * and "eventMask" state variables are always consistent. + * + * Note that we don't actually need to acquire the spinlock until later + * when we are finally ready to update the "callback" and "eventMask" + * state variables which are shared with the interrupt handler. + */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + rc = PMIC_ERROR; + /* Register for PMIC events from the core protocol driver. */ + if (eventMask & MICROPHONE_DETECTED) { + /* We need to register for the A1 amplifier interrupt. */ + eventNotify.func = func; + eventNotify.param = (void *)(CORE_EVENT_MC2BI); + rc = pmic_event_subscribe(EVENT_MC2BI, eventNotify); + + if (rc != PMIC_SUCCESS) { + pr_debug + ("%s: pmic_event_subscribe() for EVENT_HSDETI " + "failed\n", __FILE__); + goto End; + } + } + + if (eventMask & HEADSET_DETECTED) { + /* We need to register for the A1 amplifier interrupt. */ + eventNotify.func = func; + eventNotify.param = (void *)(CORE_EVENT_HSDETI); + rc = pmic_event_subscribe(EVENT_HSDETI, eventNotify); + + if (rc != PMIC_SUCCESS) { + pr_debug + ("%s: pmic_event_subscribe() for EVENT_HSDETI " + "failed\n", __FILE__); + goto Cleanup_HDT; + } + + } + if (eventMask & HEADSET_STEREO) { + /* We need to register for the A1 amplifier interrupt. */ + eventNotify.func = func; + eventNotify.param = (void *)(CORE_EVENT_HSLI); + rc = pmic_event_subscribe(EVENT_HSLI, eventNotify); + + if (rc != PMIC_SUCCESS) { + pr_debug + ("%s: pmic_event_subscribe() for EVENT_HSLI " + "failed\n", __FILE__); + goto Cleanup_HST; + } + } + if (eventMask & HEADSET_THERMAL_SHUTDOWN) { + /* We need to register for the A1 amplifier interrupt. */ + eventNotify.func = func; + eventNotify.param = (void *)(CORE_EVENT_ALSPTHI); + rc = pmic_event_subscribe(EVENT_ALSPTHI, eventNotify); + + if (rc != PMIC_SUCCESS) { + pr_debug + ("%s: pmic_event_subscribe() for EVENT_ALSPTHI " + "failed\n", __FILE__); + goto Cleanup_TSD; + } + pr_debug("Registered for EVENT_ALSPTHI\n"); + } + if (eventMask & HEADSET_SHORT_CIRCUIT) { + /* We need to register for the A1 amplifier interrupt. */ + eventNotify.func = func; + eventNotify.param = (void *)(CORE_EVENT_AHSSHORTI); + rc = pmic_event_subscribe(EVENT_AHSSHORTI, eventNotify); + + if (rc != PMIC_SUCCESS) { + pr_debug + ("%s: pmic_event_subscribe() for EVENT_AHSSHORTI " + "failed\n", __FILE__); + goto Cleanup_HShort; + } + pr_debug("Registered for EVENT_AHSSHORTI\n"); + } + + /* We also need the spinlock here to avoid possible problems + * with the interrupt handler when we update the + * "callback" and "eventMask" state variables. + */ + spin_lock_irqsave(&lock, flags); + + /* Successfully registered for all events. */ + event_state.callback = func; + event_state.eventMask = eventMask; + + /* The spinlock is no longer needed now that we've finished + * updating the "callback" and "eventMask" state variables. + */ + spin_unlock_irqrestore(&lock, flags); + + goto End; + + /* This section unregisters any already registered events if we should + * encounter an error partway through the registration process. Note + * that we don't check the return status here since it is already set + * to PMIC_ERROR before we get here. + */ + Cleanup_HShort: + + if (eventMask & HEADSET_SHORT_CIRCUIT) { + eventNotify.func = func; + eventNotify.param = (void *)(CORE_EVENT_AHSSHORTI); + pmic_event_unsubscribe(EVENT_AHSSHORTI, eventNotify); + } + + Cleanup_TSD: + + if (eventMask & HEADSET_THERMAL_SHUTDOWN) { + eventNotify.func = func; + eventNotify.param = (void *)(CORE_EVENT_ALSPTHI); + pmic_event_unsubscribe(EVENT_ALSPTHI, eventNotify); + } + + Cleanup_HST: + + if (eventMask & HEADSET_STEREO) { + eventNotify.func = func; + eventNotify.param = (void *)(CORE_EVENT_HSLI); + pmic_event_unsubscribe(EVENT_HSLI, eventNotify); + } + + Cleanup_HDT: + + if (eventMask & HEADSET_DETECTED) { + eventNotify.func = func; + eventNotify.param = (void *)(CORE_EVENT_HSDETI); + pmic_event_unsubscribe(EVENT_HSDETI, eventNotify); + } + + End: + /* Exit the critical section. */ + up(&mutex); + return rc; +} + +/*! + * @brief Deregisters the existing audio callback function. + * + * Deregister the callback function that was previously registered by calling + * pmic_audio_set_callback(). + * + * + * @retval PMIC_SUCCESS If the callback was successfully + * deregistered. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_audio_clear_callback(void) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* We need a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if (event_state.callback != (PMIC_AUDIO_CALLBACK) NULL) { + rc = pmic_audio_deregister(&(event_state.callback), + &(event_state.eventMask)); + } + + /* Exit the critical section. */ + up(&mutex); + return rc; +} + +/*! + * @brief Get the current audio callback function settings. + * + * Get the current callback function and event mask. + * + * @param func The current callback function. + * @param eventMask The current event selection mask. + * + * @retval PMIC_SUCCESS If the callback information was + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_audio_get_callback(PMIC_AUDIO_CALLBACK * const func, + PMIC_AUDIO_EVENTS * const eventMask) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* We only need to acquire the mutex here because we will not be updating + * anything that may affect the interrupt handler. We just need to ensure + * that the callback fields are not changed while we are in the critical + * section by calling either pmic_audio_set_callback() or + * pmic_audio_clear_callback(). + */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((func != (PMIC_AUDIO_CALLBACK *) NULL) && + (eventMask != (PMIC_AUDIO_EVENTS *) NULL)) { + + *func = event_state.callback; + *eventMask = event_state.eventMask; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + return rc; +} + +/*! + * @brief Enable the anti-pop circuitry to avoid extra noise when inserting + * or removing a external device (e.g., a headset). + * + * Enable the use of the built-in anti-pop circuitry to prevent noise from + * being generated when an external audio device is inserted or removed + * from an audio plug. A slow ramp speed may be needed to avoid extra noise. + * + * @param rampSpeed The desired anti-pop circuitry ramp speed. + * + * @retval PMIC_SUCCESS If the anti-pop circuitry was successfully + * enabled. + * @retval PMIC_ERROR If the anti-pop circuitry could not be + * enabled. + */ +PMIC_STATUS pmic_audio_antipop_enable(const PMIC_AUDIO_ANTI_POP_RAMP_SPEED + rampSpeed) +{ + PMIC_STATUS rc = PMIC_ERROR; + unsigned int reg_value = 0; + const unsigned int reg_mask = SET_BITS(regAUDIO_RX_0, BIASEN, 1) | + SET_BITS(regAUDIO_RX_0, BIASSPEED, 1); + + /* No critical section required here since we are not updating any + * global data. + */ + + /* + * Antipop is enabled by enabling the BIAS (BIASEN) and setting the + * BIASSPEED . + * BIASEN is just to make sure that BIAS is enabled + */ + reg_value = SET_BITS(regAUDIO_RX_0, BIASEN, 1) + | SET_BITS(regAUDIO_RX_0, BIASSPEED, 0) | SET_BITS(regAUDIO_RX_0, + HSLDETEN, 1); + rc = pmic_write_reg(REG_AUDIO_RX_0, reg_value, reg_mask); + return rc; +} + +/*! + * @brief Disable the anti-pop circuitry. + * + * Disable the use of the built-in anti-pop circuitry to prevent noise from + * being generated when an external audio device is inserted or removed + * from an audio plug. + * + * @retval PMIC_SUCCESS If the anti-pop circuitry was successfully + * disabled. + * @retval PMIC_ERROR If the anti-pop circuitry could not be + * disabled. + */ +PMIC_STATUS pmic_audio_antipop_disable(void) +{ + PMIC_STATUS rc = PMIC_ERROR; + const unsigned int reg_mask = SET_BITS(regAUDIO_RX_0, BIASSPEED, 1) | + SET_BITS(regAUDIO_RX_0, BIASEN, 1); + const unsigned int reg_write = SET_BITS(regAUDIO_RX_0, BIASSPEED, 1) | + SET_BITS(regAUDIO_RX_0, BIASEN, 0); + + /* No critical section required here since we are not updating any + * global data. + */ + + /* + * Antipop is disabled by setting BIASSPEED = 0. BIASEN bit remains set + * as only antipop needs to be disabled + */ + rc = pmic_write_reg(REG_AUDIO_RX_0, reg_write, reg_mask); + + return rc; +} + +/*! + * @brief Performs a reset of the Voice CODEC/Stereo DAC digital filter. + * + * The digital filter should be reset whenever the clock or sampling rate + * configuration has been changed. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the digital filter was successfully + * reset. + * @retval PMIC_ERROR If the digital filter could not be reset. + */ +PMIC_STATUS pmic_audio_digital_filter_reset(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask = 0; + + /* No critical section required here since we are not updating any + * global data. + */ + + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + reg_mask = SET_BITS(regST_DAC, STDCRESET, 1); + if (pmic_write_reg(REG_AUDIO_STEREO_DAC, reg_mask, + reg_mask) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + pr_debug("STDAC filter reset\n"); + } + + } else if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) { + reg_mask = SET_BITS(regAUD_CODEC, CDCRESET, 1); + if (pmic_write_reg(REG_AUDIO_CODEC, reg_mask, + reg_mask) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + pr_debug("CODEC filter reset\n"); + } + } + return rc; +} + +/*! + * @brief Get the most recent PTT button voltage reading. + * + * This feature is not supported by mc13783 + * @param level PTT button level. + * + * @retval PMIC_SUCCESS If the most recent PTT button voltage was + * returned. + * @retval PMIC_PARAMETER_ERROR If a NULL pointer argument was given. + */ +PMIC_STATUS pmic_audio_get_ptt_button_level(unsigned int *const level) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + return rc; +} + +#ifdef DEBUG_AUDIO + +/*! + * @brief Provide a hexadecimal dump of all PMIC audio registers (DEBUG only) + * + * This function is intended strictly for debugging purposes only and will + * print the current values of the following PMIC registers: + * + * - AUD_CODEC + * - ST_DAC + * - AUDIO_RX_0 + * - AUDIO_RX_1 + * - AUDIO_TX + * - AUDIO_SSI_NW + * + * The register fields will not be decoded. + * + * Note that we don't dump any of the arbitration bits because we cannot + * access the true arbitration bit settings when reading the registers + * from the secondary SPI bus. + * + * Also note that we must not call this function with interrupts disabled, + * for example, while holding a spinlock, because calls to pmic_read_reg() + * eventually end up in the SPI driver which will want to perform a + * schedule() operation. If schedule() is called with interrupts disabled, + * then you will see messages like the following: + * + * BUG: scheduling while atomic: ... + * + */ +void pmic_audio_dump_registers(void) +{ + unsigned int reg_value = 0; + + /* Dump the AUD_CODEC (Voice CODEC) register. */ + if (pmic_read_reg(REG_AUDIO_CODEC, ®_value, REG_FULLMASK) + == PMIC_SUCCESS) { + pr_debug("Audio Codec = 0x%x\n", reg_value); + } else { + pr_debug("Failed to read audio codec\n"); + } + + /* Dump the ST DAC (Stereo DAC) register. */ + if (pmic_read_reg + (REG_AUDIO_STEREO_DAC, ®_value, REG_FULLMASK) == PMIC_SUCCESS) { + pr_debug("Stereo DAC = 0x%x\n", reg_value); + } else { + pr_debug("Failed to read Stereo DAC\n"); + } + + /* Dump the SSI NW register. */ + if (pmic_read_reg + (REG_AUDIO_SSI_NETWORK, ®_value, REG_FULLMASK) == PMIC_SUCCESS) { + pr_debug("SSI Network = 0x%x\n", reg_value); + } else { + pr_debug("Failed to read SSI network\n"); + } + + /* Dump the Audio RX 0 register. */ + if (pmic_read_reg(REG_AUDIO_RX_0, ®_value, REG_FULLMASK) + == PMIC_SUCCESS) { + pr_debug("Audio RX 0 = 0x%x\n", reg_value); + } else { + pr_debug("Failed to read audio RX 0\n"); + } + + /* Dump the Audio RX 1 register. */ + if (pmic_read_reg(REG_AUDIO_RX_1, ®_value, REG_FULLMASK) + == PMIC_SUCCESS) { + pr_debug("Audio RX 1 = 0x%x\n", reg_value); + } else { + pr_debug("Failed to read audio RX 1\n"); + } + /* Dump the Audio TX register. */ + if (pmic_read_reg(REG_AUDIO_TX, ®_value, REG_FULLMASK) == + PMIC_SUCCESS) { + pr_debug("Audio Tx = 0x%x\n", reg_value); + } else { + pr_debug("Failed to read audio TX\n"); + } + +} + +#endif /* DEBUG_AUDIO */ + +/*@}*/ + +/************************************************************************* + * General Voice CODEC configuration. + ************************************************************************* + */ + +/*! + * @name General Voice CODEC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Voice + * CODEC hardware. + */ +/*@{*/ + +/*! + * @brief Set the Voice CODEC clock source and operating characteristics. + * + * Define the Voice CODEC clock source and operating characteristics. This + * must be done before the Voice CODEC is enabled. + * + * + * + * @param handle Device handle from pmic_audio_open() call. + * @param clockIn Select the clock signal source. + * @param clockFreq Select the clock signal frequency. + * @param samplingRate Select the audio data sampling rate. + * @param invert Enable inversion of the frame sync and/or + * bit clock inputs. + * + * @retval PMIC_SUCCESS If the Voice CODEC clock settings were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or clock configuration was + * invalid. + * @retval PMIC_ERROR If the Voice CODEC clock configuration + * could not be set. + */ +PMIC_STATUS pmic_audio_vcodec_set_clock(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_CLOCK_IN_SOURCE + clockIn, + const PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ + clockFreq, + const PMIC_AUDIO_VCODEC_SAMPLING_RATE + samplingRate, + const PMIC_AUDIO_CLOCK_INVERT invert) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_value = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + /* Validate all of the calling parameters. */ + if (handle == (PMIC_AUDIO_HANDLE) NULL) { + rc = PMIC_PARAMETER_ERROR; + } else if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) { + if ((clockIn != CLOCK_IN_CLIA) && (clockIn != CLOCK_IN_CLIB)) { + rc = PMIC_PARAMETER_ERROR; + } else if (!((clockFreq >= VCODEC_CLI_13MHZ) + && (clockFreq <= VCODEC_CLI_33_6MHZ))) { + rc = PMIC_PARAMETER_ERROR; + } else if ((samplingRate != VCODEC_RATE_8_KHZ) + && (samplingRate != VCODEC_RATE_16_KHZ)) { + rc = PMIC_PARAMETER_ERROR; + } else if (!((invert >= NO_INVERT) + && (invert <= INVERT_FRAMESYNC))) { + rc = PMIC_PARAMETER_ERROR; + } else { + /*reg_mask = SET_BITS(regAUD_CODEC, CDCCLK, 7) | + SET_BITS(regAUD_CODEC, CDCCLKSEL, 1) | + SET_BITS(regAUD_CODEC, CDCFS8K16K, 1) | + SET_BITS(regAUD_CODEC, CDCBCLINV, 1) | + SET_BITS(regAUD_CODEC, CDCFSINV, 1); */ + if (clockIn == CLOCK_IN_CLIA) { + reg_value = + SET_BITS(regAUD_CODEC, CDCCLKSEL, 0); + } else { + reg_value = + SET_BITS(regAUD_CODEC, CDCCLKSEL, 1); + } + reg_mask = SET_BITS(regAUD_CODEC, CDCCLKSEL, 1); + if (PMIC_SUCCESS != + pmic_write_reg(REG_AUDIO_CODEC, + reg_value, reg_mask)) + return PMIC_ERROR; + + reg_value = 0; + if (clockFreq == VCODEC_CLI_13MHZ) { + reg_value |= SET_BITS(regAUD_CODEC, CDCCLK, 0); + } else if (clockFreq == VCODEC_CLI_15_36MHZ) { + reg_value |= SET_BITS(regAUD_CODEC, CDCCLK, 1); + } else if (clockFreq == VCODEC_CLI_16_8MHZ) { + reg_value |= SET_BITS(regAUD_CODEC, CDCCLK, 2); + } else if (clockFreq == VCODEC_CLI_26MHZ) { + reg_value |= SET_BITS(regAUD_CODEC, CDCCLK, 4); + } else { + reg_value |= SET_BITS(regAUD_CODEC, CDCCLK, 7); + } + reg_mask = SET_BITS(regAUD_CODEC, CDCCLK, 7); + if (PMIC_SUCCESS != + pmic_write_reg(REG_AUDIO_CODEC, + reg_value, reg_mask)) + return PMIC_ERROR; + + reg_value = 0; + reg_mask = 0; + + if (samplingRate == VCODEC_RATE_8_KHZ) { + reg_value |= + SET_BITS(regAUD_CODEC, CDCFS8K16K, 0); + } else { + reg_value |= + SET_BITS(regAUD_CODEC, CDCFS8K16K, 1); + } + reg_mask = SET_BITS(regAUD_CODEC, CDCFS8K16K, 1); + if (PMIC_SUCCESS != + pmic_write_reg(REG_AUDIO_CODEC, + reg_value, reg_mask)) + return PMIC_ERROR; + reg_value = 0; + reg_mask = + SET_BITS(regAUD_CODEC, CDCBCLINV, + 1) | SET_BITS(regAUD_CODEC, CDCFSINV, 1); + + if (invert & INVERT_BITCLOCK) { + reg_value |= + SET_BITS(regAUD_CODEC, CDCBCLINV, 1); + } + if (invert & INVERT_FRAMESYNC) { + reg_value |= + SET_BITS(regAUD_CODEC, CDCFSINV, 1); + } + if (invert & NO_INVERT) { + reg_value |= + SET_BITS(regAUD_CODEC, CDCBCLINV, 0); + reg_value |= + SET_BITS(regAUD_CODEC, CDCFSINV, 0); + } + if (pmic_write_reg + (REG_AUDIO_CODEC, reg_value, + reg_mask) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + pr_debug("CODEC clock set\n"); + vCodec.clockIn = clockIn; + vCodec.clockFreq = clockFreq; + vCodec.samplingRate = samplingRate; + vCodec.invert = invert; + } + + } + + } else { + rc = PMIC_PARAMETER_ERROR; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the Voice CODEC clock source and operating characteristics. + * + * Get the current Voice CODEC clock source and operating characteristics. + * + * @param handle Device handle from pmic_audio_open() call. + * @param clockIn The clock signal source. + * @param clockFreq The clock signal frequency. + * @param samplingRate The audio data sampling rate. + * @param invert Inversion of the frame sync and/or + * bit clock inputs is enabled/disabled. + * + * @retval PMIC_SUCCESS If the Voice CODEC clock settings were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle invalid. + * @retval PMIC_ERROR If the Voice CODEC clock configuration + * could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_clock(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_CLOCK_IN_SOURCE * + const clockIn, + PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ * + const clockFreq, + PMIC_AUDIO_VCODEC_SAMPLING_RATE * + const samplingRate, + PMIC_AUDIO_CLOCK_INVERT * const invert) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure that we return a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE) && + (clockIn != (PMIC_AUDIO_CLOCK_IN_SOURCE *) NULL) && + (clockFreq != (PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ *) NULL) && + (samplingRate != (PMIC_AUDIO_VCODEC_SAMPLING_RATE *) NULL) && + (invert != (PMIC_AUDIO_CLOCK_INVERT *) NULL)) { + *clockIn = vCodec.clockIn; + *clockFreq = vCodec.clockFreq; + *samplingRate = vCodec.samplingRate; + *invert = vCodec.invert; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Set the Voice CODEC primary audio channel timeslot. + * + * Set the Voice CODEC primary audio channel timeslot. This function must be + * used if the default timeslot for the primary audio channel is to be changed. + * + * @param handle Device handle from pmic_audio_open() call. + * @param timeslot Select the primary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Voice CODEC primary audio channel + * timeslot was successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or audio channel timeslot + * was invalid. + * @retval PMIC_ERROR If the Voice CODEC primary audio channel + * timeslot could not be set. + */ +PMIC_STATUS pmic_audio_vcodec_set_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_VCODEC_TIMESLOT + timeslot) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + const unsigned int reg_mask = SET_BITS(regSSI_NETWORK, CDCTXRXSLOT, 3); + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE) && + ((timeslot == USE_TS0) || (timeslot == USE_TS1) || + (timeslot == USE_TS2) || (timeslot == USE_TS3))) { + reg_write = SET_BITS(regSSI_NETWORK, CDCTXRXSLOT, timeslot); + + rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK, reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + vCodec.timeslot = timeslot; + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the current Voice CODEC primary audio channel timeslot. + * + * Get the current Voice CODEC primary audio channel timeslot. + * + * @param handle Device handle from pmic_audio_open() call. + * @param timeslot The primary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Voice CODEC primary audio channel + * timeslot was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC primary audio channel + * timeslot could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_VCODEC_TIMESLOT * + const timeslot) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE) && + (timeslot != (PMIC_AUDIO_VCODEC_TIMESLOT *) NULL)) { + *timeslot = vCodec.timeslot; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Set the Voice CODEC secondary recording audio channel timeslot. + * + * Set the Voice CODEC secondary audio channel timeslot. This function must be + * used if the default timeslot for the secondary audio channel is to be + * changed. The secondary audio channel timeslot is used to transmit the audio + * data that was recorded by the Voice CODEC from the secondary audio input + * channel. + * + * @param handle Device handle from pmic_audio_open() call. + * @param timeslot Select the secondary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Voice CODEC secondary audio channel + * timeslot was successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or audio channel timeslot + * was invalid. + * @retval PMIC_ERROR If the Voice CODEC secondary audio channel + * timeslot could not be set. + */ +PMIC_STATUS pmic_audio_vcodec_set_secondary_txslot(const PMIC_AUDIO_HANDLE + handle, + const + PMIC_AUDIO_VCODEC_TIMESLOT + timeslot) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask = SET_BITS(regSSI_NETWORK, CDCTXSECSLOT, 3); + unsigned int reg_write = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + /* How to handle primary slot and secondary slot being the same */ + if ((timeslot >= USE_TS0) && (timeslot <= USE_TS3) + && (timeslot != vCodec.timeslot)) { + reg_write = + SET_BITS(regSSI_NETWORK, CDCTXSECSLOT, timeslot); + + rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + vCodec.secondaryTXtimeslot = timeslot; + } + } + + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the Voice CODEC secondary recording audio channel timeslot. + * + * Get the Voice CODEC secondary audio channel timeslot. + * + * @param handle Device handle from pmic_audio_open() call. + * @param timeslot The secondary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Voice CODEC secondary audio channel + * timeslot was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC secondary audio channel + * timeslot could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_secondary_txslot(const PMIC_AUDIO_HANDLE + handle, + PMIC_AUDIO_VCODEC_TIMESLOT * + const timeslot) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE) && + (timeslot != (PMIC_AUDIO_VCODEC_TIMESLOT *) NULL)) { + rc = PMIC_SUCCESS; + *timeslot = vCodec.secondaryTXtimeslot; + } + + /* Exit the critical section. */ + up(&mutex); + return rc; +} + +/*! + * @brief Set/Enable the Voice CODEC options. + * + * Set or enable various Voice CODEC options. The available options include + * the use of dithering, highpass digital filters, and loopback modes. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The Voice CODEC options to enable. + * + * @retval PMIC_SUCCESS If the Voice CODEC options were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or Voice CODEC options + * were invalid. + * @retval PMIC_ERROR If the Voice CODEC options could not be + * successfully set/enabled. + */ +PMIC_STATUS pmic_audio_vcodec_set_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_VCODEC_CONFIG config) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + if (config & DITHERING) { + reg_write = SET_BITS(regAUD_CODEC, CDCDITH, 0); + reg_mask = SET_BITS(regAUD_CODEC, CDCDITH, 1); + } + + if (config & INPUT_HIGHPASS_FILTER) { + reg_write |= SET_BITS(regAUD_CODEC, AUDIHPF, 1); + reg_mask |= SET_BITS(regAUD_CODEC, AUDIHPF, 1); + } + + if (config & OUTPUT_HIGHPASS_FILTER) { + reg_write |= SET_BITS(regAUD_CODEC, AUDOHPF, 1); + reg_mask |= SET_BITS(regAUD_CODEC, AUDOHPF, 1); + } + + if (config & DIGITAL_LOOPBACK) { + reg_write |= SET_BITS(regAUD_CODEC, CDCDLM, 1); + reg_mask |= SET_BITS(regAUD_CODEC, CDCDLM, 1); + } + + if (config & ANALOG_LOOPBACK) { + reg_write |= SET_BITS(regAUD_CODEC, CDCALM, 1); + reg_mask |= SET_BITS(regAUD_CODEC, CDCALM, 1); + } + + if (config & VCODEC_MASTER_CLOCK_OUTPUTS) { + reg_write |= SET_BITS(regAUD_CODEC, CDCCLKEN, 1) | + SET_BITS(regAUD_CODEC, CDCTS, 0); + reg_mask |= SET_BITS(regAUD_CODEC, CDCCLKEN, 1) | + SET_BITS(regAUD_CODEC, CDCTS, 1); + + } + + if (config & TRISTATE_TS) { + reg_write |= SET_BITS(regAUD_CODEC, CDCTS, 1); + reg_mask |= SET_BITS(regAUD_CODEC, CDCTS, 1); + } + + if (reg_mask == 0) { + /* We should not reach this point without having to configure + * anything so we flag it as an error. + */ + rc = PMIC_ERROR; + } else { + rc = pmic_write_reg(REG_AUDIO_CODEC, + reg_write, reg_mask); + } + + if (rc == PMIC_SUCCESS) { + vCodec.config |= config; + } + } + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Clear/Disable the Voice CODEC options. + * + * Clear or disable various Voice CODEC options. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The Voice CODEC options to be cleared/disabled. + * + * @retval PMIC_SUCCESS If the Voice CODEC options were + * successfully cleared/disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or the Voice CODEC options + * were invalid. + * @retval PMIC_ERROR If the Voice CODEC options could not be + * cleared/disabled. + */ +PMIC_STATUS pmic_audio_vcodec_clear_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_VCODEC_CONFIG + config) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + if (config & DITHERING) { + reg_mask = SET_BITS(regAUD_CODEC, CDCDITH, 1); + reg_write = SET_BITS(regAUD_CODEC, CDCDITH, 1); + } + + if (config & INPUT_HIGHPASS_FILTER) { + reg_mask |= SET_BITS(regAUD_CODEC, AUDIHPF, 1); + } + + if (config & OUTPUT_HIGHPASS_FILTER) { + reg_mask |= SET_BITS(regAUD_CODEC, AUDOHPF, 1); + } + + if (config & DIGITAL_LOOPBACK) { + reg_mask |= SET_BITS(regAUD_CODEC, CDCDLM, 1); + } + + if (config & ANALOG_LOOPBACK) { + reg_mask |= SET_BITS(regAUD_CODEC, CDCALM, 1); + } + + if (config & VCODEC_MASTER_CLOCK_OUTPUTS) { + reg_mask |= SET_BITS(regAUD_CODEC, CDCCLKEN, 1); + } + + if (config & TRISTATE_TS) { + reg_mask |= SET_BITS(regAUD_CODEC, CDCTS, 1); + } + + if (reg_mask == 0) { + /* We should not reach this point without having to configure + * anything so we flag it as an error. + */ + rc = PMIC_ERROR; + } else { + rc = pmic_write_reg(REG_AUDIO_CODEC, + reg_write, reg_mask); + } + + if (rc == PMIC_SUCCESS) { + vCodec.config |= config; + } + + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the current Voice CODEC options. + * + * Get the current Voice CODEC options. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The current set of Voice CODEC options. + * + * @retval PMIC_SUCCESS If the Voice CODEC options were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC options could not be + * retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_config(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_VCODEC_CONFIG * + const config) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE) && + (config != (PMIC_AUDIO_VCODEC_CONFIG *) NULL)) { + *config = vCodec.config; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Enable the Voice CODEC bypass audio pathway. + * + * Enables the Voice CODEC bypass pathway for audio data. This allows direct + * output of the voltages on the TX data bus line to the output amplifiers + * (bypassing the digital-to-analog converters within the Voice CODEC). + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the Voice CODEC bypass was successfully + * enabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC bypass could not be + * enabled. + */ +PMIC_STATUS pmic_audio_vcodec_enable_bypass(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + const unsigned int reg_write = SET_BITS(regAUD_CODEC, CDCBYP, 1); + const unsigned int reg_mask = SET_BITS(regAUD_CODEC, CDCBYP, 1); + + /* No critical section required here since we are not updating any + * global data. + */ + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + rc = pmic_write_reg(REG_AUDIO_CODEC, reg_write, reg_mask); + } + + return rc; +} + +/*! + * @brief Disable the Voice CODEC bypass audio pathway. + * + * Disables the Voice CODEC bypass pathway for audio data. This means that + * the TX data bus line will deliver digital data to the digital-to-analog + * converters within the Voice CODEC. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the Voice CODEC bypass was successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC bypass could not be + * disabled. + */ +PMIC_STATUS pmic_audio_vcodec_disable_bypass(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + const unsigned int reg_write = 0; + const unsigned int reg_mask = SET_BITS(regAUD_CODEC, CDCBYP, 1); + + /* No critical section required here since we are not updating any + * global data. + */ + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + rc = pmic_write_reg(REG_AUDIO_CODEC, reg_write, reg_mask); + } + + return rc; +} + +/*@}*/ + +/************************************************************************* + * General Stereo DAC configuration. + ************************************************************************* + */ + +/*! + * @name General Stereo DAC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Stereo + * DAC hardware. + */ +/*@{*/ + +/*! + * @brief Set the Stereo DAC clock source and operating characteristics. + * + * Define the Stereo DAC clock source and operating characteristics. This + * must be done before the Stereo DAC is enabled. + * + * + * @param handle Device handle from pmic_audio_open() call. + * @param clockIn Select the clock signal source. + * @param clockFreq Select the clock signal frequency. + * @param samplingRate Select the audio data sampling rate. + * @param invert Enable inversion of the frame sync and/or + * bit clock inputs. + * + * @retval PMIC_SUCCESS If the Stereo DAC clock settings were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or clock configuration was + * invalid. + * @retval PMIC_ERROR If the Stereo DAC clock configuration + * could not be set. + */ +PMIC_STATUS pmic_audio_stdac_set_clock(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_CLOCK_IN_SOURCE clockIn, + const PMIC_AUDIO_STDAC_CLOCK_IN_FREQ + clockFreq, + const PMIC_AUDIO_STDAC_SAMPLING_RATE + samplingRate, + const PMIC_AUDIO_CLOCK_INVERT invert) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_value = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + /* Validate all of the calling parameters. */ + if (handle == (PMIC_AUDIO_HANDLE) NULL) { + rc = PMIC_PARAMETER_ERROR; + } else if ((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) { + if ((clockIn != CLOCK_IN_CLIA) && (clockIn != CLOCK_IN_CLIB)) { + rc = PMIC_PARAMETER_ERROR; + } else if ((stDAC.masterSlave == BUS_MASTER_MODE) + && !((clockFreq >= STDAC_CLI_3_36864MHZ) + && (clockFreq <= STDAC_CLI_33_6MHZ))) { + rc = PMIC_PARAMETER_ERROR; + } else if ((stDAC.masterSlave == BUS_SLAVE_MODE) + && !((clockFreq >= STDAC_MCLK_PLL_DISABLED) + && (clockFreq <= STDAC_BCLK_IN_PLL))) { + rc = PMIC_PARAMETER_ERROR; + } else if (!((samplingRate >= STDAC_RATE_8_KHZ) + && (samplingRate <= STDAC_RATE_96_KHZ))) { + rc = PMIC_PARAMETER_ERROR; + } + /* + else if(!((invert >= NO_INVERT) && (invert <= INVERT_FRAMESYNC))) + { + rc = PMIC_PARAMETER_ERROR; + } */ + else { + reg_mask = SET_BITS(regST_DAC, STDCCLK, 7) | + SET_BITS(regST_DAC, STDCCLKSEL, 1) | + SET_BITS(regST_DAC, SR, 15) | + SET_BITS(regST_DAC, STDCBCLINV, 1) | + SET_BITS(regST_DAC, STDCFSINV, 1); + if (clockIn == CLOCK_IN_CLIA) { + reg_value = SET_BITS(regST_DAC, STDCCLKSEL, 0); + } else { + reg_value = SET_BITS(regST_DAC, STDCCLKSEL, 1); + } + /* How to take care of sample rates in SLAVE mode */ + if ((clockFreq == STDAC_CLI_3_36864MHZ) + || ((clockFreq == STDAC_FSYNC_IN_PLL))) { + reg_value |= SET_BITS(regST_DAC, STDCCLK, 6); + } else if ((clockFreq == STDAC_CLI_12MHZ) + || (clockFreq == STDAC_MCLK_PLL_DISABLED)) { + reg_value |= SET_BITS(regST_DAC, STDCCLK, 5); + } else if (clockFreq == STDAC_CLI_13MHZ) { + reg_value |= SET_BITS(regST_DAC, STDCCLK, 0); + } else if (clockFreq == STDAC_CLI_15_36MHZ) { + reg_value |= SET_BITS(regST_DAC, STDCCLK, 1); + } else if (clockFreq == STDAC_CLI_16_8MHZ) { + reg_value |= SET_BITS(regST_DAC, STDCCLK, 2); + } else if (clockFreq == STDAC_CLI_26MHZ) { + reg_value |= SET_BITS(regST_DAC, STDCCLK, 4); + } else if ((clockFreq == STDAC_CLI_33_6MHZ) + || (clockFreq == STDAC_BCLK_IN_PLL)) { + reg_value |= SET_BITS(regST_DAC, STDCCLK, 7); + } + + reg_value |= SET_BITS(regST_DAC, SR, samplingRate); + + if (invert & INVERT_BITCLOCK) { + reg_value |= SET_BITS(regST_DAC, STDCBCLINV, 1); + } + if (invert & INVERT_FRAMESYNC) { + reg_value |= SET_BITS(regST_DAC, STDCFSINV, 1); + } + if (invert & NO_INVERT) { + reg_value |= SET_BITS(regST_DAC, STDCBCLINV, 0); + reg_value |= SET_BITS(regST_DAC, STDCFSINV, 0); + } + if (pmic_write_reg + (REG_AUDIO_STEREO_DAC, reg_value, + reg_mask) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + pr_debug("STDAC clock set\n"); + rc = PMIC_SUCCESS; + stDAC.clockIn = clockIn; + stDAC.clockFreq = clockFreq; + stDAC.samplingRate = samplingRate; + stDAC.invert = invert; + } + + } + + } else { + rc = PMIC_PARAMETER_ERROR; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the Stereo DAC clock source and operating characteristics. + * + * Get the current Stereo DAC clock source and operating characteristics. + * + * @param handle Device handle from pmic_audio_open() call. + * @param clockIn The clock signal source. + * @param clockFreq The clock signal frequency. + * @param samplingRate The audio data sampling rate. + * @param invert Inversion of the frame sync and/or + * bit clock inputs is enabled/disabled. + * + * @retval PMIC_SUCCESS If the Stereo DAC clock settings were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle invalid. + * @retval PMIC_ERROR If the Stereo DAC clock configuration + * could not be retrieved. + */ +PMIC_STATUS pmic_audio_stdac_get_clock(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_CLOCK_IN_SOURCE * + const clockIn, + PMIC_AUDIO_STDAC_SAMPLING_RATE * + const samplingRate, + PMIC_AUDIO_STDAC_CLOCK_IN_FREQ * + const clockFreq, + PMIC_AUDIO_CLOCK_INVERT * const invert) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE) && + (clockIn != (PMIC_AUDIO_CLOCK_IN_SOURCE *) NULL) && + (samplingRate != (PMIC_AUDIO_STDAC_SAMPLING_RATE *) NULL) && + (clockFreq != (PMIC_AUDIO_STDAC_CLOCK_IN_FREQ *) NULL) && + (invert != (PMIC_AUDIO_CLOCK_INVERT *) NULL)) { + *clockIn = stDAC.clockIn; + *samplingRate = stDAC.samplingRate; + *clockFreq = stDAC.clockFreq; + *invert = stDAC.invert; + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Set the Stereo DAC primary audio channel timeslot. + * + * Set the Stereo DAC primary audio channel timeslot. This function must be + * used if the default timeslot for the primary audio channel is to be changed. + * + * @param handle Device handle from pmic_audio_open() call. + * @param timeslot Select the primary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Stereo DAC primary audio channel + * timeslot was successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or audio channel timeslot + * was invalid. + * @retval PMIC_ERROR If the Stereo DAC primary audio channel + * timeslot could not be set. + */ +PMIC_STATUS pmic_audio_stdac_set_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STDAC_TIMESLOTS + timeslot) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask = SET_BITS(regSSI_NETWORK, STDCRXSLOT, 3); + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + if ((timeslot == USE_TS0_TS1) || (timeslot == USE_TS2_TS3) + || (timeslot == USE_TS4_TS5) || (timeslot == USE_TS6_TS7)) { + if (pmic_write_reg + (REG_AUDIO_SSI_NETWORK, timeslot, + reg_mask) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + pr_debug("STDAC primary timeslot set\n"); + stDAC.timeslot = timeslot; + rc = PMIC_SUCCESS; + } + + } else { + rc = PMIC_PARAMETER_ERROR; + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the current Stereo DAC primary audio channel timeslot. + * + * Get the current Stereo DAC primary audio channel timeslot. + * + * @param handle Device handle from pmic_audio_open() call. + * @param timeslot The primary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Stereo DAC primary audio channel + * timeslot was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Stereo DAC primary audio channel + * timeslot could not be retrieved. + */ +PMIC_STATUS pmic_audio_stdac_get_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_STDAC_TIMESLOTS * + const timeslot) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE) && + (timeslot != (PMIC_AUDIO_STDAC_TIMESLOTS *) NULL)) { + *timeslot = stDAC.timeslot; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Set/Enable the Stereo DAC options. + * + * Set or enable various Stereo DAC options. The available options include + * resetting the digital filter and enabling the bus master clock outputs. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The Stereo DAC options to enable. + * + * @retval PMIC_SUCCESS If the Stereo DAC options were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or Stereo DAC options + * were invalid. + * @retval PMIC_ERROR If the Stereo DAC options could not be + * successfully set/enabled. + */ +PMIC_STATUS pmic_audio_stdac_set_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STDAC_CONFIG config) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + if (config & STDAC_MASTER_CLOCK_OUTPUTS) { + reg_write |= SET_BITS(regST_DAC, STDCCLKEN, 1); + reg_mask |= SET_BITS(regST_DAC, STDCCLKEN, 1); + } + + rc = pmic_write_reg(REG_AUDIO_STEREO_DAC, reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + stDAC.config |= config; + pr_debug("STDAC config set\n"); + + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Clear/Disable the Stereo DAC options. + * + * Clear or disable various Stereo DAC options. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The Stereo DAC options to be cleared/disabled. + * + * @retval PMIC_SUCCESS If the Stereo DAC options were + * successfully cleared/disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or the Stereo DAC options + * were invalid. + * @retval PMIC_ERROR If the Stereo DAC options could not be + * cleared/disabled. + */ +PMIC_STATUS pmic_audio_stdac_clear_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STDAC_CONFIG config) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + + if (config & STDAC_MASTER_CLOCK_OUTPUTS) { + reg_mask |= SET_BITS(regST_DAC, STDCCLKEN, 1); + } + + if (reg_mask != 0) { + rc = pmic_write_reg(REG_AUDIO_STEREO_DAC, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + stDAC.config &= ~config; + } + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the current Stereo DAC options. + * + * Get the current Stereo DAC options. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The current set of Stereo DAC options. + * + * @retval PMIC_SUCCESS If the Stereo DAC options were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Stereo DAC options could not be + * retrieved. + */ +PMIC_STATUS pmic_audio_stdac_get_config(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_STDAC_CONFIG * const config) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE) && + (config != (PMIC_AUDIO_STDAC_CONFIG *) NULL)) { + *config = stDAC.config; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*@}*/ + +/************************************************************************* + * Audio input section configuration. + ************************************************************************* + */ + +/*! + * @name Audio Input Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC audio + * input hardware. + */ +/*@{*/ + +/*! + * @brief Set/Enable the audio input section options. + * + * Set or enable various audio input section options. The only available + * option right now is to enable the automatic disabling of the microphone + * input amplifiers when a microphone/headset is inserted or removed. + * NOT SUPPORTED BY MC13783 + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The audio input section options to enable. + * + * @retval PMIC_SUCCESS If the audio input section options were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or audio input section + * options were invalid. + * @retval PMIC_ERROR If the audio input section options could + * not be successfully set/enabled. + */ +PMIC_STATUS pmic_audio_input_set_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_INPUT_CONFIG config) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + return rc; +} + +/*! + * @brief Clear/Disable the audio input section options. + * + * Clear or disable various audio input section options. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The audio input section options to be + * cleared/disabled. + * NOT SUPPORTED BY MC13783 + * + * @retval PMIC_SUCCESS If the audio input section options were + * successfully cleared/disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or the audio input section + * options were invalid. + * @retval PMIC_ERROR If the audio input section options could + * not be cleared/disabled. + */ +PMIC_STATUS pmic_audio_input_clear_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_INPUT_CONFIG config) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + return rc; + +} + +/*! + * @brief Get the current audio input section options. + * + * Get the current audio input section options. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] config The current set of audio input section options. + * NOT SUPPORTED BY MC13783 + * + * @retval PMIC_SUCCESS If the audio input section options were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the audio input section options could + * not be retrieved. + */ +PMIC_STATUS pmic_audio_input_get_config(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_INPUT_CONFIG * const config) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + return rc; +} + +/*@}*/ + +/************************************************************************* + * Audio recording using the Voice CODEC. + ************************************************************************* + */ + +/*! + * @name Audio Recording Using the Voice CODEC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Voice CODEC + * to perform audio recording. + */ +/*@{*/ + +/*! + * @brief Select the microphone inputs to be used for Voice CODEC recording. + * + * Select left (mc13783-only) and right microphone inputs for Voice CODEC + * recording. It is possible to disable or not use a particular microphone + * input channel by specifying NO_MIC as a parameter. + * + * @param handle Device handle from pmic_audio_open() call. + * @param leftChannel Select the left microphone input channel. + * @param rightChannel Select the right microphone input channel. + * + * @retval PMIC_SUCCESS If the microphone input channels were + * successfully enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or microphone input ports + * were invalid. + * @retval PMIC_ERROR If the microphone input channels could + * not be successfully enabled. + */ +PMIC_STATUS pmic_audio_vcodec_set_mic(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_INPUT_PORT leftChannel, + const PMIC_AUDIO_INPUT_PORT rightChannel) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + if (!((leftChannel == NO_MIC) || (leftChannel == MIC1_LEFT))) { + rc = PMIC_PARAMETER_ERROR; + } else if (!((rightChannel == NO_MIC) + || (rightChannel == MIC1_RIGHT_MIC_MONO) + || (rightChannel == TXIN_EXT) + || (rightChannel == MIC2_AUX))) { + rc = PMIC_PARAMETER_ERROR; + } else { + if (leftChannel == NO_MIC) { + } else { /* Left channel MIC enable */ + reg_mask = SET_BITS(regAUDIO_TX, AMC1LEN, 1) | + SET_BITS(regAUDIO_TX, RXINREC, 1); + reg_write = SET_BITS(regAUDIO_TX, AMC1LEN, 1) | + SET_BITS(regAUDIO_TX, RXINREC, 0); + } + /*For right channel enable one and clear the other two as well as RXINREC */ + if (rightChannel == NO_MIC) { + } else if (rightChannel == MIC1_RIGHT_MIC_MONO) { + reg_mask |= SET_BITS(regAUDIO_TX, AMC1REN, 1) | + SET_BITS(regAUDIO_TX, RXINREC, 1) | + SET_BITS(regAUDIO_TX, AMC2EN, 1) | + SET_BITS(regAUDIO_TX, ATXINEN, 1); + reg_write |= SET_BITS(regAUDIO_TX, AMC1REN, 1) | + SET_BITS(regAUDIO_TX, RXINREC, 0) | + SET_BITS(regAUDIO_TX, AMC2EN, 0) | + SET_BITS(regAUDIO_TX, ATXINEN, 0); + } else if (rightChannel == MIC2_AUX) { + reg_mask |= SET_BITS(regAUDIO_TX, AMC1REN, 1) | + SET_BITS(regAUDIO_TX, RXINREC, 1) | + SET_BITS(regAUDIO_TX, AMC2EN, 1) | + SET_BITS(regAUDIO_TX, ATXINEN, 1); + reg_write |= SET_BITS(regAUDIO_TX, AMC1REN, 0) | + SET_BITS(regAUDIO_TX, RXINREC, 0) | + SET_BITS(regAUDIO_TX, AMC2EN, 1) | + SET_BITS(regAUDIO_TX, ATXINEN, 0); + } else { /* TX line in */ + reg_mask |= SET_BITS(regAUDIO_TX, AMC1REN, 1) | + SET_BITS(regAUDIO_TX, RXINREC, 1) | + SET_BITS(regAUDIO_TX, AMC2EN, 1) | + SET_BITS(regAUDIO_TX, ATXINEN, 1); + reg_write |= SET_BITS(regAUDIO_TX, AMC1REN, 0) | + SET_BITS(regAUDIO_TX, RXINREC, 0) | + SET_BITS(regAUDIO_TX, AMC2EN, 0) | + SET_BITS(regAUDIO_TX, ATXINEN, 1); + } + + if (reg_mask == 0) { + rc = PMIC_PARAMETER_ERROR; + } else { + rc = pmic_write_reg(REG_AUDIO_TX, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug + ("MIC inputs configured successfully\n"); + vCodec.leftChannelMic.mic = leftChannel; + vCodec.rightChannelMic.mic = + rightChannel; + + } + } + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the current microphone inputs being used for Voice CODEC + * recording. + * + * Get the left (mc13783-only) and right microphone inputs currently being + * used for Voice CODEC recording. + * + * @param handle Device handle from pmic_audio_open() call. + * @param leftChannel The left microphone input channel. + * @param rightChannel The right microphone input channel. + * + * @retval PMIC_SUCCESS If the microphone input channels were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the microphone input channels could + * not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_mic(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_INPUT_PORT * const leftChannel, + PMIC_AUDIO_INPUT_PORT * + const rightChannel) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE) && + (leftChannel != (PMIC_AUDIO_INPUT_PORT *) NULL) && + (rightChannel != (PMIC_AUDIO_INPUT_PORT *) NULL)) { + *leftChannel = vCodec.leftChannelMic.mic; + *rightChannel = vCodec.rightChannelMic.mic; + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + return rc; +} + +/*! + * @brief Enable/disable the microphone input. + * + * This function enables/disables the current microphone input channel. The + * input amplifier is automatically turned off when the microphone input is + * disabled. + * + * @param handle Device handle from pmic_audio_open() call. + * @param leftChannel The left microphone input channel state. + * @param rightChannel the right microphone input channel state. + * + * @retval PMIC_SUCCESS If the microphone input channels were + * successfully reconfigured. + * @retval PMIC_PARAMETER_ERROR If the handle or microphone input states + * were invalid. + * @retval PMIC_ERROR If the microphone input channels could + * not be reconfigured. + */ +PMIC_STATUS pmic_audio_vcodec_set_mic_on_off(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_INPUT_MIC_STATE + leftChannel, + const PMIC_AUDIO_INPUT_MIC_STATE + rightChannel) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + unsigned int curr_left = 0; + unsigned int curr_right = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + curr_left = vCodec.leftChannelMic.mic; + curr_right = vCodec.rightChannelMic.mic; + if ((curr_left == NO_MIC) && (curr_right == NO_MIC)) { + rc = PMIC_PARAMETER_ERROR; + } else { + if (curr_left == MIC1_LEFT) { + if ((leftChannel == MICROPHONE_ON) && + (vCodec.leftChannelMic.micOnOff == + MICROPHONE_OFF)) { + /* Enable the microphone */ + reg_mask |= + SET_BITS(regAUDIO_TX, AMC1LEN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, 1); + reg_write |= + SET_BITS(regAUDIO_TX, AMC1LEN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, 0); + + } else if ((leftChannel == MICROPHONE_OFF) && + (vCodec.leftChannelMic.micOnOff == + MICROPHONE_ON)) { + /* Disable the microphone */ + reg_mask |= + SET_BITS(regAUDIO_TX, AMC1LEN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, 1); + reg_write |= + SET_BITS(regAUDIO_TX, AMC1LEN, + 0) | SET_BITS(regAUDIO_TX, + RXINREC, 0); + + } else { + /* Both are in same state . Nothing to be done */ + } + + } + if (curr_right == MIC1_RIGHT_MIC_MONO) { + if ((rightChannel == MICROPHONE_ON) && + (vCodec.leftChannelMic.micOnOff == + MICROPHONE_OFF)) { + /* Enable the microphone */ + reg_mask |= + SET_BITS(regAUDIO_TX, AMC1REN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, + 1) | + SET_BITS(regAUDIO_TX, AMC2EN, + 1) | SET_BITS(regAUDIO_TX, + ATXINEN, 1); + reg_write |= + SET_BITS(regAUDIO_TX, AMC1REN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, + 0) | + SET_BITS(regAUDIO_TX, AMC2EN, + 0) | SET_BITS(regAUDIO_TX, + ATXINEN, 0); + } else if ((rightChannel == MICROPHONE_OFF) + && (vCodec.leftChannelMic.micOnOff == + MICROPHONE_ON)) { + /* Disable the microphone */ + reg_mask |= + SET_BITS(regAUDIO_TX, AMC1REN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, + 1) | + SET_BITS(regAUDIO_TX, AMC2EN, + 1) | SET_BITS(regAUDIO_TX, + ATXINEN, 1); + reg_write |= + SET_BITS(regAUDIO_TX, AMC1REN, + 0) | SET_BITS(regAUDIO_TX, + RXINREC, + 0) | + SET_BITS(regAUDIO_TX, AMC2EN, + 0) | SET_BITS(regAUDIO_TX, + ATXINEN, 0); + } else { + /* Both are in same state . Nothing to be done */ + } + } else if (curr_right == MIC2_AUX) { + if ((rightChannel == MICROPHONE_ON) + && (vCodec.leftChannelMic.micOnOff == + MICROPHONE_OFF)) { + /* Enable the microphone */ + reg_mask |= + SET_BITS(regAUDIO_TX, AMC1REN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, + 1) | + SET_BITS(regAUDIO_TX, AMC2EN, + 1) | SET_BITS(regAUDIO_TX, + ATXINEN, 1); + reg_write |= + SET_BITS(regAUDIO_TX, AMC1REN, + 0) | SET_BITS(regAUDIO_TX, + RXINREC, + 0) | + SET_BITS(regAUDIO_TX, AMC2EN, + 1) | SET_BITS(regAUDIO_TX, + ATXINEN, 0); + } else if ((rightChannel == MICROPHONE_OFF) + && (vCodec.leftChannelMic.micOnOff == + MICROPHONE_ON)) { + /* Disable the microphone */ + reg_mask |= + SET_BITS(regAUDIO_TX, AMC1REN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, + 1) | + SET_BITS(regAUDIO_TX, AMC2EN, + 1) | SET_BITS(regAUDIO_TX, + ATXINEN, 1); + reg_write |= + SET_BITS(regAUDIO_TX, AMC1REN, + 0) | SET_BITS(regAUDIO_TX, + RXINREC, + 0) | + SET_BITS(regAUDIO_TX, AMC2EN, + 0) | SET_BITS(regAUDIO_TX, + ATXINEN, 0); + } else { + /* Both are in same state . Nothing to be done */ + } + } else if (curr_right == TXIN_EXT) { + if ((rightChannel == MICROPHONE_ON) + && (vCodec.leftChannelMic.micOnOff == + MICROPHONE_OFF)) { + /* Enable the microphone */ + reg_mask |= + SET_BITS(regAUDIO_TX, AMC1REN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, + 1) | + SET_BITS(regAUDIO_TX, AMC2EN, + 1) | SET_BITS(regAUDIO_TX, + ATXINEN, 1); + reg_write |= + SET_BITS(regAUDIO_TX, AMC1REN, + 0) | SET_BITS(regAUDIO_TX, + RXINREC, + 0) | + SET_BITS(regAUDIO_TX, AMC2EN, + 0) | SET_BITS(regAUDIO_TX, + ATXINEN, 1); + } else if ((rightChannel == MICROPHONE_OFF) + && (vCodec.leftChannelMic.micOnOff == + MICROPHONE_ON)) { + /* Disable the microphone */ + reg_mask |= + SET_BITS(regAUDIO_TX, AMC1REN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, + 1) | + SET_BITS(regAUDIO_TX, AMC2EN, + 1) | SET_BITS(regAUDIO_TX, + ATXINEN, 1); + reg_write |= + SET_BITS(regAUDIO_TX, AMC1REN, + 0) | SET_BITS(regAUDIO_TX, + RXINREC, + 0) | + SET_BITS(regAUDIO_TX, AMC2EN, + 0) | SET_BITS(regAUDIO_TX, + ATXINEN, 0); + } else { + /* Both are in same state . Nothing to be done */ + } + } + if (reg_mask == 0) { + } else { + rc = pmic_write_reg(REG_AUDIO_TX, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug + ("MIC states configured successfully\n"); + vCodec.leftChannelMic.micOnOff = + leftChannel; + vCodec.rightChannelMic.micOnOff = + rightChannel; + } + } + } + + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Return the current state of the microphone inputs. + * + * This function returns the current state (on/off) of the microphone + * input channels. + * + * @param handle Device handle from pmic_audio_open() call. + * @param leftChannel The current left microphone input channel + * state. + * @param rightChannel the current right microphone input channel + * state. + * + * @retval PMIC_SUCCESS If the microphone input channel states + * were successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the microphone input channel states + * could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_mic_on_off(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_INPUT_MIC_STATE * + const leftChannel, + PMIC_AUDIO_INPUT_MIC_STATE * + const rightChannel) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE) && + (leftChannel != (PMIC_AUDIO_INPUT_MIC_STATE *) NULL) && + (rightChannel != (PMIC_AUDIO_INPUT_MIC_STATE *) NULL)) { + *leftChannel = vCodec.leftChannelMic.micOnOff; + *rightChannel = vCodec.rightChannelMic.micOnOff; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Set the microphone input amplifier mode and gain level. + * + * This function sets the current microphone input amplifier operating mode + * and gain level. + * + * @param handle Device handle from pmic_audio_open() call. + * @param leftChannelMode The left microphone input amplifier mode. + * @param leftChannelGain The left microphone input amplifier gain level. + * @param rightChannelMode The right microphone input amplifier mode. + * @param rightChannelGain The right microphone input amplifier gain + * level. + * + * @retval PMIC_SUCCESS If the microphone input amplifiers were + * successfully reconfigured. + * @retval PMIC_PARAMETER_ERROR If the handle or microphone input amplifier + * modes or gain levels were invalid. + * @retval PMIC_ERROR If the microphone input amplifiers could + * not be reconfigured. + */ +PMIC_STATUS pmic_audio_vcodec_set_record_gain(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_MIC_AMP_MODE + leftChannelMode, + const PMIC_AUDIO_MIC_GAIN + leftChannelGain, + const PMIC_AUDIO_MIC_AMP_MODE + rightChannelMode, + const PMIC_AUDIO_MIC_GAIN + rightChannelGain) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + if (!(((leftChannelGain >= MIC_GAIN_MINUS_8DB) + && (leftChannelGain <= MIC_GAIN_PLUS_23DB)) + && ((rightChannelGain >= MIC_GAIN_MINUS_8DB) + && (rightChannelGain <= MIC_GAIN_PLUS_23DB)))) { + rc = PMIC_PARAMETER_ERROR; + pr_debug("VCODEC set record gain - wrong gain value\n"); + } else if (((leftChannelMode != AMP_OFF) + && (leftChannelMode != VOLTAGE_TO_VOLTAGE) + && (leftChannelMode != CURRENT_TO_VOLTAGE)) + || ((rightChannelMode != VOLTAGE_TO_VOLTAGE) + && (rightChannelMode != CURRENT_TO_VOLTAGE) + && (rightChannelMode != AMP_OFF))) { + rc = PMIC_PARAMETER_ERROR; + pr_debug("VCODEC set record gain - wrong amp mode\n"); + } else { + if (vCodec.leftChannelMic.mic == MIC1_LEFT) { + reg_mask = SET_BITS(regAUDIO_TX, AMC1LITOV, 1) | + SET_BITS(regAUDIO_TX, PGATXL, 31); + if (leftChannelMode == VOLTAGE_TO_VOLTAGE) { + reg_write = + SET_BITS(regAUDIO_TX, AMC1LITOV, 0); + } else { + reg_write = + SET_BITS(regAUDIO_TX, AMC1LITOV, 1); + } + reg_write |= + SET_BITS(regAUDIO_TX, PGATXL, + leftChannelGain); + } + if (vCodec.rightChannelMic.mic == MIC1_RIGHT_MIC_MONO) { + reg_mask |= + SET_BITS(regAUDIO_TX, AMC1RITOV, + 1) | SET_BITS(regAUDIO_TX, PGATXR, + 31); + if (rightChannelMode == VOLTAGE_TO_VOLTAGE) { + reg_write |= + SET_BITS(regAUDIO_TX, AMC1RITOV, 0); + } else { + reg_write |= + SET_BITS(regAUDIO_TX, AMC1RITOV, 1); + } + reg_write |= + SET_BITS(regAUDIO_TX, PGATXR, + rightChannelGain); + } else if (vCodec.rightChannelMic.mic == MIC2_AUX) { + reg_mask |= SET_BITS(regAUDIO_TX, AMC2ITOV, 1); + reg_mask |= SET_BITS(regAUDIO_TX, PGATXR, 31); + if (rightChannelMode == VOLTAGE_TO_VOLTAGE) { + reg_write |= + SET_BITS(regAUDIO_TX, AMC2ITOV, 0); + } else { + reg_write |= + SET_BITS(regAUDIO_TX, AMC2ITOV, 1); + } + reg_write |= + SET_BITS(regAUDIO_TX, PGATXR, + rightChannelGain); + } else if (vCodec.rightChannelMic.mic == TXIN_EXT) { + reg_mask |= SET_BITS(regAUDIO_TX, PGATXR, 31); + /* No current to voltage option for TX IN amplifier */ + reg_write |= + SET_BITS(regAUDIO_TX, PGATXR, + rightChannelGain); + } + + if (reg_mask == 0) { + } else { + rc = pmic_write_reg(REG_AUDIO_TX, + reg_write, reg_mask); + reg_write = + SET_BITS(regAUDIO_TX, PGATXL, + leftChannelGain); + reg_mask = SET_BITS(regAUDIO_TX, PGATXL, 31); + rc = pmic_write_reg(REG_AUDIO_TX, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug("MIC amp mode and gain set\n"); + vCodec.leftChannelMic.ampMode = + leftChannelMode; + vCodec.leftChannelMic.gain = + leftChannelGain; + vCodec.rightChannelMic.ampMode = + rightChannelMode; + vCodec.rightChannelMic.gain = + rightChannelGain; + + } + } + } + } + + /* Exit critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the current microphone input amplifier mode and gain level. + * + * This function gets the current microphone input amplifier operating mode + * and gain level. + * + * @param handle Device handle from pmic_audio_open() call. + * @param leftChannelMode The left microphone input amplifier mode. + * @param leftChannelGain The left microphone input amplifier gain level. + * @param rightChannelMode The right microphone input amplifier mode. + * @param rightChannelGain The right microphone input amplifier gain + * level. + * + * @retval PMIC_SUCCESS If the microphone input amplifier modes + * and gain levels were successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the microphone input amplifier modes + * and gain levels could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_record_gain(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_MIC_AMP_MODE * + const leftChannelMode, + PMIC_AUDIO_MIC_GAIN * + const leftChannelGain, + PMIC_AUDIO_MIC_AMP_MODE * + const rightChannelMode, + PMIC_AUDIO_MIC_GAIN * + const rightChannelGain) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE) && + (leftChannelMode != (PMIC_AUDIO_MIC_AMP_MODE *) NULL) && + (leftChannelGain != (PMIC_AUDIO_MIC_GAIN *) NULL) && + (rightChannelMode != (PMIC_AUDIO_MIC_AMP_MODE *) NULL) && + (rightChannelGain != (PMIC_AUDIO_MIC_GAIN *) NULL)) { + *leftChannelMode = vCodec.leftChannelMic.ampMode; + *leftChannelGain = vCodec.leftChannelMic.gain; + *rightChannelMode = vCodec.rightChannelMic.ampMode; + *rightChannelGain = vCodec.rightChannelMic.gain; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Enable a microphone bias circuit. + * + * This function enables one of the available microphone bias circuits. + * + * @param handle Device handle from pmic_audio_open() call. + * @param biasCircuit The microphone bias circuit to be enabled. + * + * @retval PMIC_SUCCESS If the microphone bias circuit was + * successfully enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or selected microphone bias + * circuit was invalid. + * @retval PMIC_ERROR If the microphone bias circuit could not + * be enabled. + */ +PMIC_STATUS pmic_audio_vcodec_enable_micbias(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_MIC_BIAS + biasCircuit) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* No critical section required here since we are not updating any + * global data. + */ + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + if (biasCircuit & MIC_BIAS1) { + reg_write = SET_BITS(regAUDIO_TX, MC1BEN, 1); + reg_mask = SET_BITS(regAUDIO_TX, MC1BEN, 1); + } + if (biasCircuit & MIC_BIAS2) { + reg_write |= SET_BITS(regAUDIO_TX, MC2BEN, 1); + reg_mask |= SET_BITS(regAUDIO_TX, MC2BEN, 1); + } + if (reg_mask != 0) { + rc = pmic_write_reg(REG_AUDIO_TX, reg_write, reg_mask); + } + } + + return rc; +} + +/*! + * @brief Disable a microphone bias circuit. + * + * This function disables one of the available microphone bias circuits. + * + * @param handle Device handle from pmic_audio_open() call. + * @param biasCircuit The microphone bias circuit to be disabled. + * + * @retval PMIC_SUCCESS If the microphone bias circuit was + * successfully disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or selected microphone bias + * circuit was invalid. + * @retval PMIC_ERROR If the microphone bias circuit could not + * be disabled. + */ +PMIC_STATUS pmic_audio_vcodec_disable_micbias(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_MIC_BIAS + biasCircuit) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* No critical section required here since we are not updating any + * global data. + */ + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + if (biasCircuit & MIC_BIAS1) { + reg_mask = SET_BITS(regAUDIO_TX, MC1BEN, 1); + } + + if (biasCircuit & MIC_BIAS2) { + reg_mask |= SET_BITS(regAUDIO_TX, MC2BEN, 1); + } + + if (reg_mask != 0) { + rc = pmic_write_reg(REG_AUDIO_TX, reg_write, reg_mask); + } + } + + return rc; +} + +/*@}*/ + +/************************************************************************* + * Audio Playback Using the Voice CODEC. + ************************************************************************* + */ + +/*! + * @name Audio Playback Using the Voice CODEC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Voice CODEC + * to perform audio playback. + */ +/*@{*/ + +/*! + * @brief Configure and enable the Voice CODEC mixer. + * + * This function configures and enables the Voice CODEC mixer. + * + * @param handle Device handle from pmic_audio_open() call. + * @param rxSecondaryTimeslot The timeslot used for the secondary audio + * channel. + * @param gainIn The secondary audio channel gain level. + * @param gainOut The mixer output gain level. + * + * @retval PMIC_SUCCESS If the Voice CODEC mixer was successfully + * configured and enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or mixer configuration + * was invalid. + * @retval PMIC_ERROR If the Voice CODEC mixer could not be + * reconfigured or enabled. + */ +PMIC_STATUS pmic_audio_vcodec_enable_mixer(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_VCODEC_TIMESLOT + rxSecondaryTimeslot, + const PMIC_AUDIO_VCODEC_MIX_IN_GAIN + gainIn, + const PMIC_AUDIO_VCODEC_MIX_OUT_GAIN + gainOut) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* No critical section required here since we are not updating any + * global data. + */ + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + if (!((rxSecondaryTimeslot >= USE_TS0) + && (rxSecondaryTimeslot <= USE_TS3))) { + pr_debug + ("VCODEC enable mixer - wrong sec rx timeslot\n"); + } else if (!((gainIn >= VCODEC_NO_MIX) + && (gainIn <= VCODEC_MIX_IN_MINUS_12DB))) { + pr_debug("VCODEC enable mixer - wrong mix in gain\n"); + + } else if (!((gainOut >= VCODEC_MIX_OUT_0DB) + && (gainOut <= VCODEC_MIX_OUT_MINUS_6DB))) { + pr_debug("VCODEC enable mixer - wrong mix out gain\n"); + } else { + + reg_mask = SET_BITS(regSSI_NETWORK, CDCRXSECSLOT, 3) | + SET_BITS(regSSI_NETWORK, CDCRXSECGAIN, 3) | + SET_BITS(regSSI_NETWORK, CDCSUMGAIN, 1); + reg_write = + SET_BITS(regSSI_NETWORK, CDCRXSECSLOT, + rxSecondaryTimeslot) | + SET_BITS(regSSI_NETWORK, CDCRXSECGAIN, + gainIn) | SET_BITS(regSSI_NETWORK, + CDCSUMGAIN, gainOut); + rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK, + reg_write, reg_mask); + if (rc == PMIC_SUCCESS) { + pr_debug("Vcodec mixer enabled\n"); + } + } + } + + return rc; +} + +/*! + * @brief Disable the Voice CODEC mixer. + * + * This function disables the Voice CODEC mixer. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the Voice CODEC mixer was successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC mixer could not be + * disabled. + */ +PMIC_STATUS pmic_audio_vcodec_disable_mixer(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask; + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + reg_mask = SET_BITS(regSSI_NETWORK, CDCRXSECGAIN, 1); + rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK, + VCODEC_NO_MIX, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug("Vcodec mixer disabled\n"); + } + + } + + return rc; +} + +/*@}*/ + +/************************************************************************* + * Audio Playback Using the Stereo DAC. + ************************************************************************* + */ + +/*! + * @name Audio Playback Using the Stereo DAC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Stereo DAC + * to perform audio playback. + */ +/*@{*/ + +/*! + * @brief Configure and enable the Stereo DAC mixer. + * + * This function configures and enables the Stereo DAC mixer. + * + * @param handle Device handle from pmic_audio_open() call. + * @param rxSecondaryTimeslot The timeslot used for the secondary audio + * channel. + * @param gainIn The secondary audio channel gain level. + * @param gainOut The mixer output gain level. + * + * @retval PMIC_SUCCESS If the Stereo DAC mixer was successfully + * configured and enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or mixer configuration + * was invalid. + * @retval PMIC_ERROR If the Stereo DAC mixer could not be + * reconfigured or enabled. + */ +PMIC_STATUS pmic_audio_stdac_enable_mixer(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STDAC_TIMESLOTS + rxSecondaryTimeslot, + const PMIC_AUDIO_STDAC_MIX_IN_GAIN + gainIn, + const PMIC_AUDIO_STDAC_MIX_OUT_GAIN + gainOut) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* No critical section required here since we are not updating any + * global data. + */ + + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + if (!((rxSecondaryTimeslot >= USE_TS0_TS1) + && (rxSecondaryTimeslot <= USE_TS6_TS7))) { + rc = PMIC_PARAMETER_ERROR; + pr_debug("STDAC enable mixer - wrong sec timeslot\n"); + } else if (!((gainIn >= STDAC_NO_MIX) + && (gainIn <= STDAC_MIX_IN_MINUS_12DB))) { + rc = PMIC_PARAMETER_ERROR; + pr_debug("STDAC enable mixer - wrong mix in gain\n"); + } else if (!((gainOut >= STDAC_MIX_OUT_0DB) + && (gainOut <= STDAC_MIX_OUT_MINUS_6DB))) { + rc = PMIC_PARAMETER_ERROR; + pr_debug("STDAC enable mixer - wrong mix out gain\n"); + } else { + + reg_mask = SET_BITS(regSSI_NETWORK, STDCRXSECSLOT, 3) | + SET_BITS(regSSI_NETWORK, STDCRXSECGAIN, 3) | + SET_BITS(regSSI_NETWORK, STDCSUMGAIN, 1); + reg_write = + SET_BITS(regSSI_NETWORK, STDCRXSECSLOT, + rxSecondaryTimeslot) | + SET_BITS(regSSI_NETWORK, STDCRXSECGAIN, + gainIn) | SET_BITS(regSSI_NETWORK, + STDCSUMGAIN, gainOut); + rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK, + reg_write, reg_mask); + if (rc == PMIC_SUCCESS) { + pr_debug("STDAC mixer enabled\n"); + } + } + + } + + return rc; +} + +/*! + * @brief Disable the Stereo DAC mixer. + * + * This function disables the Stereo DAC mixer. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the Stereo DAC mixer was successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Stereo DAC mixer could not be + * disabled. + */ +PMIC_STATUS pmic_audio_stdac_disable_mixer(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + const unsigned int reg_write = 0; + const unsigned int reg_mask = + SET_BITS(regSSI_NETWORK, STDCRXSECGAIN, 1); + + /* No critical section required here since we are not updating any + * global data. + */ + + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK, reg_write, reg_mask); + } + + return rc; +} + +/*@}*/ + +/************************************************************************* + * Audio Output Control + ************************************************************************* + */ + +/*! + * @name Audio Output Section Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC audio output + * section to support playback. + */ +/*@{*/ + +/*! + * @brief Select the audio output ports. + * + * This function selects the audio output ports to be used. This also enables + * the appropriate output amplifiers. + * + * @param handle Device handle from pmic_audio_open() call. + * @param port The audio output ports to be used. + * + * @retval PMIC_SUCCESS If the audio output ports were successfully + * acquired. + * @retval PMIC_PARAMETER_ERROR If the handle or output ports were + * invalid. + * @retval PMIC_ERROR If the audio output ports could not be + * acquired. + */ +PMIC_STATUS pmic_audio_output_set_port(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_PORT port) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((port == MONO_ALERT) || (port == MONO_EXTOUT)) { + rc = PMIC_NOT_SUPPORTED; + } else { + if (((handle == stDAC.handle) + && (stDAC.handleState == HANDLE_IN_USE)) + || ((handle == extStereoIn.handle) + && (extStereoIn.handleState == HANDLE_IN_USE)) + || ((handle == vCodec.handle) + && (vCodec.handleState == HANDLE_IN_USE) + && (audioOutput.vCodecOut == VCODEC_MIXER_OUT))) { + /* Stereo signal and MIXER source needs to be routed to the port + / Avoid Codec direct out */ + + if (port & MONO_SPEAKER) { + reg_mask = SET_BITS(regAUDIO_RX_0, ASPEN, 1) | + SET_BITS(regAUDIO_RX_0, ASPSEL, 1); + reg_write = SET_BITS(regAUDIO_RX_0, ASPEN, 1) | + SET_BITS(regAUDIO_RX_0, ASPSEL, 1); + } + if (port & MONO_LOUDSPEAKER) { + reg_mask |= SET_BITS(regAUDIO_RX_0, ALSPEN, 1) | + SET_BITS(regAUDIO_RX_0, ALSPREF, 1) | + SET_BITS(regAUDIO_RX_0, ALSPSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ALSPEN, + 1) | SET_BITS(regAUDIO_RX_0, + ALSPREF, + 1) | + SET_BITS(regAUDIO_RX_0, ALSPSEL, 1); + } + if (port & STEREO_HEADSET_LEFT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1) | + SET_BITS(regAUDIO_RX_0, AHSSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, AHSLEN, + 1) | SET_BITS(regAUDIO_RX_0, + AHSSEL, 1); + } + if (port & STEREO_HEADSET_RIGHT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSREN, 1) | + SET_BITS(regAUDIO_RX_0, AHSSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, AHSREN, + 1) | SET_BITS(regAUDIO_RX_0, + AHSSEL, 1); + } + if (port & STEREO_OUT_LEFT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, ARXOUTLEN, + 1) | SET_BITS(regAUDIO_RX_0, + ARXOUTSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ARXOUTLEN, + 1) | SET_BITS(regAUDIO_RX_0, + ARXOUTSEL, 1); + } + if (port & STEREO_OUT_RIGHT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, ARXOUTREN, + 1) | SET_BITS(regAUDIO_RX_0, + ARXOUTSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ARXOUTREN, + 1) | SET_BITS(regAUDIO_RX_0, + ARXOUTSEL, 1); + } + if (port & STEREO_LEFT_LOW_POWER) { + reg_mask |= SET_BITS(regAUDIO_RX_0, LSPLEN, 1); + + reg_write |= SET_BITS(regAUDIO_RX_0, LSPLEN, 1); + } + } else if ((handle == vCodec.handle) + && (vCodec.handleState == HANDLE_IN_USE) + && (audioOutput.vCodecOut = VCODEC_DIRECT_OUT)) { + if (port & MONO_SPEAKER) { + reg_mask = SET_BITS(regAUDIO_RX_0, ASPEN, 1) | + SET_BITS(regAUDIO_RX_0, ASPSEL, 1); + reg_write = SET_BITS(regAUDIO_RX_0, ASPEN, 1) | + SET_BITS(regAUDIO_RX_0, ASPSEL, 0); + } + if (port & MONO_LOUDSPEAKER) { + reg_mask |= SET_BITS(regAUDIO_RX_0, ALSPEN, 1) | + SET_BITS(regAUDIO_RX_0, ALSPREF, 1) | + SET_BITS(regAUDIO_RX_0, ALSPSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ALSPEN, + 1) | SET_BITS(regAUDIO_RX_0, + ALSPREF, + 1) | + SET_BITS(regAUDIO_RX_0, ALSPSEL, 0); + } + + if (port & STEREO_HEADSET_LEFT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1) | + SET_BITS(regAUDIO_RX_0, AHSSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, AHSLEN, + 1) | SET_BITS(regAUDIO_RX_0, + AHSSEL, 0); + } + if (port & STEREO_HEADSET_RIGHT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSREN, 1) | + SET_BITS(regAUDIO_RX_0, AHSSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, AHSREN, + 1) | SET_BITS(regAUDIO_RX_0, + AHSSEL, 0); + } + if (port & STEREO_OUT_LEFT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, ARXOUTLEN, + 1) | SET_BITS(regAUDIO_RX_0, + ARXOUTSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ARXOUTLEN, + 1) | SET_BITS(regAUDIO_RX_0, + ARXOUTSEL, 0); + } + if (port & STEREO_OUT_RIGHT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, ARXOUTREN, + 1) | SET_BITS(regAUDIO_RX_0, + ARXOUTSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ARXOUTREN, + 1) | SET_BITS(regAUDIO_RX_0, + ARXOUTSEL, 0); + } + if (port & MONO_CDCOUT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, CDCOUTEN, 1); + + reg_write |= + SET_BITS(regAUDIO_RX_0, CDCOUTEN, 1); + } + } + + if (reg_mask == 0) { + + } else { + rc = pmic_write_reg(REG_AUDIO_RX_0, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug("output ports enabled\n"); + audioOutput.outputPort = port; + + } + } + } + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Deselect/disable the audio output ports. + * + * This function disables the audio output ports that were previously enabled + * by calling pmic_audio_output_set_port(). + * + * @param handle Device handle from pmic_audio_open() call. + * @param port The audio output ports to be disabled. + * + * @retval PMIC_SUCCESS If the audio output ports were successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or output ports were + * invalid. + * @retval PMIC_ERROR If the audio output ports could not be + * disabled. + */ +PMIC_STATUS pmic_audio_output_clear_port(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_PORT port) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((port == MONO_ALERT) || (port == MONO_EXTOUT)) { + rc = PMIC_NOT_SUPPORTED; + } else { + if (((handle == stDAC.handle) + && (stDAC.handleState == HANDLE_IN_USE)) + || ((handle == extStereoIn.handle) + && (extStereoIn.handleState == HANDLE_IN_USE)) + || ((handle == vCodec.handle) + && (vCodec.handleState == HANDLE_IN_USE) + && (audioOutput.vCodecOut = VCODEC_MIXER_OUT))) { + /* Stereo signal and MIXER source needs to be routed to the port / + Avoid Codec direct out */ + if (port & MONO_SPEAKER) { + reg_mask = SET_BITS(regAUDIO_RX_0, ASPEN, 1); + reg_write = SET_BITS(regAUDIO_RX_0, ASPEN, 0); + } + if (port & MONO_LOUDSPEAKER) { + reg_mask |= SET_BITS(regAUDIO_RX_0, ALSPEN, 1) | + SET_BITS(regAUDIO_RX_0, ALSPREF, 1); + + reg_write |= + SET_BITS(regAUDIO_RX_0, ALSPEN, + 0) | SET_BITS(regAUDIO_RX_0, + ALSPREF, 0); + + } + if (port & STEREO_HEADSET_LEFT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, AHSLEN, 0); + } + if (port & STEREO_HEADSET_RIGHT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSREN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, AHSREN, 0); + } + if (port & STEREO_OUT_LEFT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, ARXOUTLEN, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ARXOUTLEN, 0); + } + if (port & STEREO_OUT_RIGHT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, ARXOUTREN, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ARXOUTREN, 0); + } + if (port & STEREO_LEFT_LOW_POWER) { + reg_mask |= SET_BITS(regAUDIO_RX_0, LSPLEN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, LSPLEN, 0); + } + } else if ((handle == vCodec.handle) + && (vCodec.handleState == HANDLE_IN_USE) + && (audioOutput.vCodecOut = VCODEC_DIRECT_OUT)) { + if (port & MONO_SPEAKER) { + reg_mask = SET_BITS(regAUDIO_RX_0, ASPEN, 1); + reg_write = SET_BITS(regAUDIO_RX_0, ASPEN, 0); + } + if (port & MONO_LOUDSPEAKER) { + reg_mask |= SET_BITS(regAUDIO_RX_0, ALSPEN, 1) | + SET_BITS(regAUDIO_RX_0, ALSPREF, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ALSPEN, + 0) | SET_BITS(regAUDIO_RX_0, + ALSPREF, 0); + } + if (port & STEREO_HEADSET_LEFT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, AHSLEN, 0); + } + if (port & STEREO_HEADSET_RIGHT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSREN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, AHSREN, 0); + } + if (port & STEREO_OUT_LEFT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, ARXOUTLEN, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ARXOUTLEN, 0); + } + if (port & STEREO_OUT_RIGHT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, ARXOUTREN, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ARXOUTREN, 0); + } + if (port & MONO_CDCOUT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, CDCOUTEN, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, CDCOUTEN, 0); + } + } +#ifdef CONFIG_HEADSET_DETECT_ENABLE + + if (port & STEREO_HEADSET_LEFT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, AHSLEN, 0); + } + if (port & STEREO_HEADSET_RIGHT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSREN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, AHSREN, 0); + } +#endif + + if (reg_mask == 0) { + + } else { + rc = pmic_write_reg(REG_AUDIO_RX_0, + reg_write, reg_mask); + if (rc == PMIC_SUCCESS) { + pr_debug("output ports disabled\n"); + audioOutput.outputPort &= ~port; + } + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the current audio output ports. + * + * This function retrieves the audio output ports that are currently being + * used. + * + * @param handle Device handle from pmic_audio_open() call. + * @param port The audio output ports currently being used. + * + * @retval PMIC_SUCCESS If the audio output ports were successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the audio output ports could not be + * retrieved. + */ +PMIC_STATUS pmic_audio_output_get_port(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_OUTPUT_PORT * const port) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) || + ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) || + ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE))) && + (port != (PMIC_AUDIO_OUTPUT_PORT *) NULL)) { + *port = audioOutput.outputPort; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Set the gain level for the external stereo inputs. + * + * This function sets the gain levels for the external stereo inputs. + * + * @param handle Device handle from pmic_audio_open() call. + * @param gain The external stereo input gain level. + * + * @retval PMIC_SUCCESS If the gain level was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle or gain level was invalid. + * @retval PMIC_ERROR If the gain level could not be set. + */ +PMIC_STATUS pmic_audio_output_set_stereo_in_gain(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STEREO_IN_GAIN + gain) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask = SET_BITS(regAUDIO_RX_1, ARXINEN, 1) | + SET_BITS(regAUDIO_RX_1, ARXIN, 1); + unsigned int reg_write = SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + + /* No critical section required here since we are not updating any + * global data. + */ + + /* The ARX amplifier for stereo is also enabled over here */ + + if ((gain == STEREO_IN_GAIN_0DB) || (gain == STEREO_IN_GAIN_PLUS_18DB)) { + if ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE)) { + + if (gain == STEREO_IN_GAIN_0DB) { + reg_write |= SET_BITS(regAUDIO_RX_1, ARXIN, 1); + } else { + reg_write |= SET_BITS(regAUDIO_RX_1, ARXIN, 0); + } + + rc = pmic_write_reg(REG_AUDIO_RX_1, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug("Ext stereo gain set\n"); + extStereoIn.inputGain = gain; + + } + + } else { + rc = PMIC_PARAMETER_ERROR; + } + } + + return rc; +} + +/*! + * @brief Get the current gain level for the external stereo inputs. + * + * This function retrieves the current gain levels for the external stereo + * inputs. + * + * @param handle Device handle from pmic_audio_open() call. + * @param gain The current external stereo input gain + * level. + * + * @retval PMIC_SUCCESS If the gain level was successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the gain level could not be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_stereo_in_gain(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_STEREO_IN_GAIN * + const gain) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE) && + (gain != (PMIC_AUDIO_STEREO_IN_GAIN *) NULL)) { + *gain = extStereoIn.inputGain; + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Set the output PGA gain level. + * + * This function sets the audio output PGA gain level. + * + * @param handle Device handle from pmic_audio_open() call. + * @param gain The output PGA gain level. + * + * @retval PMIC_SUCCESS If the gain level was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle or gain level was invalid. + * @retval PMIC_ERROR If the gain level could not be set. + */ +PMIC_STATUS pmic_audio_output_set_pgaGain(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_PGA_GAIN gain) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + unsigned int reg_gain; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if (!((gain >= OUTPGA_GAIN_MINUS_33DB) + && (gain <= OUTPGA_GAIN_PLUS_6DB))) { + rc = PMIC_NOT_SUPPORTED; + pr_debug("output set PGA gain - wrong gain value\n"); + } else { + reg_gain = gain + 2; + if ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE)) { + reg_mask = SET_BITS(regAUDIO_RX_1, ARXIN, 15) | + SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + reg_write = SET_BITS(regAUDIO_RX_1, ARXIN, reg_gain) | + SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + } else if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) { + reg_mask = SET_BITS(regAUDIO_RX_1, PGARX, 15); + reg_write = SET_BITS(regAUDIO_RX_1, PGARX, reg_gain); + } else if ((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) { + reg_mask = SET_BITS(regAUDIO_RX_1, PGAST, 15); + reg_write = SET_BITS(regAUDIO_RX_1, PGAST, reg_gain); + } + + if (reg_mask == 0) { + + } else { + rc = pmic_write_reg(REG_AUDIO_RX_1, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug("Output PGA gains set\n"); + + if (handle == stDAC.handle) { + audioOutput.stDacoutputPGAGain = gain; + } else if (handle == vCodec.handle) { + audioOutput.vCodecoutputPGAGain = gain; + } else { + audioOutput.extStereooutputPGAGain = + gain; + } + } else { + pr_debug + ("Error writing PGA gains to register\n"); + } + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the output PGA gain level. + * + * This function retrieves the current audio output PGA gain level. + * + * @param handle Device handle from pmic_audio_open() call. + * @param gain The current output PGA gain level. + * + * @retval PMIC_SUCCESS If the gain level was successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the gain level could not be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_pgaGain(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_OUTPUT_PGA_GAIN * + const gain) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if (gain != (PMIC_AUDIO_OUTPUT_PGA_GAIN *) NULL) { + if ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE)) { + *gain = audioOutput.extStereooutputPGAGain; + rc = PMIC_SUCCESS; + } else if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) { + *gain = audioOutput.vCodecoutputPGAGain; + rc = PMIC_SUCCESS; + } else if ((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) { + *gain = audioOutput.stDacoutputPGAGain; + rc = PMIC_SUCCESS; + } else { + rc = PMIC_PARAMETER_ERROR; + } + } else { + rc = PMIC_PARAMETER_ERROR; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Enable the output mixer. + * + * This function enables the output mixer for the audio stream that + * corresponds to the current handle (i.e., the Voice CODEC, Stereo DAC, or + * the external stereo inputs). + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the mixer was successfully enabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the mixer could not be enabled. + */ +PMIC_STATUS pmic_audio_output_enable_mixer(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask = 0; + unsigned int reg_write = 0; + unsigned int reg_mask_mix = 0; + unsigned int reg_write_mix = 0; + + /* No critical section required here since we are not updating any + * global data. + */ + + if (((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE))) { + reg_mask = SET_BITS(regAUDIO_RX_1, PGASTEN, 1); + reg_write = SET_BITS(regAUDIO_RX_1, PGASTEN, 1); + reg_mask_mix = SET_BITS(regAUDIO_RX_0, ADDSTDC, 1); + reg_write_mix = SET_BITS(regAUDIO_RX_0, ADDSTDC, 1); + } else if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) { + reg_mask = SET_BITS(regAUDIO_RX_1, PGARXEN, 1); + reg_write = SET_BITS(regAUDIO_RX_1, PGARXEN, 1); + audioOutput.vCodecOut = VCODEC_MIXER_OUT; + + reg_mask_mix = SET_BITS(regAUDIO_RX_0, ADDCDC, 1); + reg_write_mix = SET_BITS(regAUDIO_RX_0, ADDCDC, 1); + } else if ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE)) { + reg_mask = SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + reg_write = SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + reg_mask_mix = SET_BITS(regAUDIO_RX_0, ADDRXIN, 1); + reg_write_mix = SET_BITS(regAUDIO_RX_0, ADDRXIN, 1); + } + + if (reg_mask == 0) { + + } else { + rc = pmic_write_reg(REG_AUDIO_RX_1, reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + + rc = pmic_write_reg(REG_AUDIO_RX_0, + reg_write_mix, reg_mask_mix); + if (rc == PMIC_SUCCESS) { + pr_debug("Output PGA mixers enabled\n"); + rc = PMIC_SUCCESS; + } + + } else { + pr_debug("Error writing mixer enable to register\n"); + } + + } + + return rc; +} + +/*! + * @brief Disable the output mixer. + * + * This function disables the output mixer for the audio stream that + * corresponds to the current handle (i.e., the Voice CODEC, Stereo DAC, or + * the external stereo inputs). + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the mixer was successfully disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the mixer could not be disabled. + */ +PMIC_STATUS pmic_audio_output_disable_mixer(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask = 0; + unsigned int reg_write = 0; + + unsigned int reg_mask_mix = 0; + unsigned int reg_write_mix = 0; + + /* No critical section required here since we are not updating any + * global data. + */ + if (((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE))) { + /*reg_mask = SET_BITS(regAUDIO_RX_1, PGASTEN, 1); + reg_write = SET_BITS(regAUDIO_RX_1, PGASTEN, 0); */ + + reg_mask_mix = SET_BITS(regAUDIO_RX_0, ADDSTDC, 1); + reg_write_mix = SET_BITS(regAUDIO_RX_0, ADDSTDC, 0); + } else if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) { + reg_mask = SET_BITS(regAUDIO_RX_1, PGARXEN, 1); + reg_write = SET_BITS(regAUDIO_RX_1, PGARXEN, 0); + audioOutput.vCodecOut = VCODEC_DIRECT_OUT; + + reg_mask_mix = SET_BITS(regAUDIO_RX_0, ADDCDC, 1); + reg_write_mix = SET_BITS(regAUDIO_RX_0, ADDCDC, 0); + } else if ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE)) { + /*reg_mask = SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + reg_write = SET_BITS(regAUDIO_RX_1, ARXINEN, 0); */ + + reg_mask_mix = SET_BITS(regAUDIO_RX_0, ADDRXIN, 1); + reg_write_mix = SET_BITS(regAUDIO_RX_0, ADDRXIN, 1); + } + + if (reg_mask == 0) { + + } else { + rc = pmic_write_reg(REG_AUDIO_RX_1, reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + + rc = pmic_write_reg(REG_AUDIO_RX_0, + reg_write_mix, reg_mask_mix); + if (rc == PMIC_SUCCESS) { + pr_debug("Output PGA mixers disabled\n"); + } + } + } + return rc; +} + +/*! + * @brief Configure and enable the output balance amplifiers. + * + * This function configures and enables the output balance amplifiers. + * + * @param handle Device handle from pmic_audio_open() call. + * @param leftGain The desired left channel gain level. + * @param rightGain The desired right channel gain level. + * + * @retval PMIC_SUCCESS If the output balance amplifiers were + * successfully configured and enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or gain levels were invalid. + * @retval PMIC_ERROR If the output balance amplifiers could not + * be reconfigured or enabled. + */ +PMIC_STATUS pmic_audio_output_set_balance(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_BALANCE_GAIN + leftGain, + const PMIC_AUDIO_OUTPUT_BALANCE_GAIN + rightGain) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask = 0; + unsigned int reg_write = 0; + unsigned int reg_mask_ch = 0; + unsigned int reg_write_ch = 0; + + /* No critical section required here since we are not updating any + * global data. + */ + + if (!((leftGain >= BAL_GAIN_MINUS_21DB) && (leftGain <= BAL_GAIN_0DB))) { + rc = PMIC_PARAMETER_ERROR; + } else if (!((rightGain >= BAL_GAIN_MINUS_21DB) + && (rightGain <= BAL_GAIN_0DB))) { + rc = PMIC_PARAMETER_ERROR; + } else { + if (((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) || + ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) || + ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE))) { + /* In mc13783 only one channel can be attenuated wrt the other. + * It is not possible to specify attenuation for both + * This function will return an error if both channels + * are required to be attenuated + * The BALLR bit is set/reset depending on whether leftGain + * or rightGain is specified*/ + if ((rightGain == BAL_GAIN_0DB) + && (leftGain == BAL_GAIN_0DB)) { + /* Nothing to be done */ + } else if ((rightGain != BAL_GAIN_0DB) + && (leftGain == BAL_GAIN_0DB)) { + /* Attenuate right channel */ + reg_mask = SET_BITS(regAUDIO_RX_1, BAL, 7); + reg_mask_ch = SET_BITS(regAUDIO_RX_1, BALLR, 1); + reg_write = + SET_BITS(regAUDIO_RX_1, BAL, + (BAL_GAIN_0DB - rightGain)); + /* The enum and the register values are reversed in order .. */ + reg_write_ch = + SET_BITS(regAUDIO_RX_1, BALLR, 0); + /* BALLR = 0 selects right channel for atten */ + } else if ((rightGain == BAL_GAIN_0DB) + && (leftGain != BAL_GAIN_0DB)) { + /* Attenuate left channel */ + + reg_mask = SET_BITS(regAUDIO_RX_1, BAL, 7); + reg_mask_ch = SET_BITS(regAUDIO_RX_1, BALLR, 1); + reg_write = + SET_BITS(regAUDIO_RX_1, BAL, + (BAL_GAIN_0DB - leftGain)); + reg_write_ch = + SET_BITS(regAUDIO_RX_1, BALLR, 1); + /* BALLR = 1 selects left channel for atten */ + } else { + rc = PMIC_PARAMETER_ERROR; + } + + if ((reg_mask == 0) || (reg_mask_ch == 0)) { + + } else { + rc = pmic_write_reg(REG_AUDIO_RX_1, + reg_write_ch, reg_mask_ch); + + if (rc == PMIC_SUCCESS) { + rc = pmic_write_reg(REG_AUDIO_RX_1, + reg_write, + reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug + ("Output balance attenuation set\n"); + audioOutput.balanceLeftGain = + leftGain; + audioOutput.balanceRightGain = + rightGain; + } + } + } + } + } + return rc; +} + +/*! + * @brief Get the current output balance amplifier gain levels. + * + * This function retrieves the current output balance amplifier gain levels. + * + * @param handle Device handle from pmic_audio_open() call. + * @param leftGain The current left channel gain level. + * @param rightGain The current right channel gain level. + * + * @retval PMIC_SUCCESS If the output balance amplifier gain levels + * were successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the output balance amplifier gain levels + * could be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_balance(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_OUTPUT_BALANCE_GAIN * + const leftGain, + PMIC_AUDIO_OUTPUT_BALANCE_GAIN * + const rightGain) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) || + ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) || + ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE))) && + ((leftGain != (PMIC_AUDIO_OUTPUT_BALANCE_GAIN *) NULL) && + (rightGain != (PMIC_AUDIO_OUTPUT_BALANCE_GAIN *) NULL))) { + *leftGain = audioOutput.balanceLeftGain; + *rightGain = audioOutput.balanceRightGain; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Configure and enable the output mono adder. + * + * This function configures and enables the output mono adder. + * + * @param handle Device handle from pmic_audio_open() call. + * @param mode The desired mono adder operating mode. + * + * @retval PMIC_SUCCESS If the mono adder was successfully + * configured and enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or mono adder mode was + * invalid. + * @retval PMIC_ERROR If the mono adder could not be reconfigured + * or enabled. + */ +PMIC_STATUS pmic_audio_output_enable_mono_adder(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_MONO_ADDER_MODE + mode) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = SET_BITS(regAUDIO_RX_1, MONO, 3); + + /* No critical section required here since we are not updating any + * global data. + */ + + if ((mode >= MONO_ADDER_OFF) && (mode <= STEREO_OPPOSITE_PHASE)) { + if (((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) || + ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) || + ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE))) { + if (mode == MONO_ADDER_OFF) { + reg_write = SET_BITS(regAUDIO_RX_1, MONO, 0); + } else if (mode == MONO_ADD_LEFT_RIGHT) { + reg_write = SET_BITS(regAUDIO_RX_1, MONO, 2); + } else if (mode == MONO_ADD_OPPOSITE_PHASE) { + reg_write = SET_BITS(regAUDIO_RX_1, MONO, 3); + } else { /* stereo opposite */ + + reg_write = SET_BITS(regAUDIO_RX_1, MONO, 1); + } + + rc = pmic_write_reg(REG_AUDIO_RX_1, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug("Output mono adder mode set\n"); + + } + + } else { + rc = PMIC_PARAMETER_ERROR; + } + } else { + rc = PMIC_PARAMETER_ERROR; + } + return rc; +} + +/*! + * @brief Disable the output mono adder. + * + * This function disables the output mono adder. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the mono adder was successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the mono adder could not be disabled. + */ +PMIC_STATUS pmic_audio_output_disable_mono_adder(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + const unsigned int reg_write = 0; + const unsigned int reg_mask = SET_BITS(regAUDIO_RX_1, MONO, 3); + + /* No critical section required here since we are not updating any + * global data. + */ + + if (((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) || + ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) || + ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE))) { + rc = pmic_write_reg(REG_AUDIO_RX_1, reg_write, reg_mask); + } + + return rc; +} + +/*! + * @brief Configure the mono adder output gain level. + * + * This function configures the mono adder output amplifier gain level. + * + * @param handle Device handle from pmic_audio_open() call. + * @param gain The desired output gain level. + * + * @retval PMIC_SUCCESS If the mono adder output amplifier gain + * level was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle or gain level was invalid. + * @retval PMIC_ERROR If the mono adder output amplifier gain + * level could not be reconfigured. + */ +PMIC_STATUS pmic_audio_output_set_mono_adder_gain(const PMIC_AUDIO_HANDLE + handle, + const + PMIC_AUDIO_MONO_ADDER_OUTPUT_GAIN + gain) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + return rc; +} + +/*! + * @brief Get the current mono adder output gain level. + * + * This function retrieves the current mono adder output amplifier gain level. + * + * @param handle Device handle from pmic_audio_open() call. + * @param gain The current output gain level. + * + * @retval PMIC_SUCCESS If the mono adder output amplifier gain + * level was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the mono adder output amplifier gain + * level could not be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_mono_adder_gain(const PMIC_AUDIO_HANDLE + handle, + PMIC_AUDIO_MONO_ADDER_OUTPUT_GAIN + * const gain) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + return rc; +} + +/*! + * @brief Set various audio output section options. + * + * This function sets one or more audio output section configuration + * options. The currently supported options include whether to disable + * the non-inverting mono speaker output, enabling the loudspeaker common + * bias circuit, enabling detection of headset insertion/removal, and + * whether to automatically disable the headset amplifiers when a headset + * insertion/removal has been detected. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The desired audio output section + * configuration options to be set. + * + * @retval PMIC_SUCCESS If the desired configuration options were + * all successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle or configuration options + * were invalid. + * @retval PMIC_ERROR If the desired configuration options + * could not be set. + */ +PMIC_STATUS pmic_audio_output_set_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_CONFIG config) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask = 0; + unsigned int reg_write = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if (((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) || + ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) || + ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE))) { + if (config & MONO_SPEAKER_INVERT_OUT_ONLY) { + /* If this is one of the parameters */ + rc = PMIC_NOT_SUPPORTED; + } else { + if (config & MONO_LOUDSPEAKER_COMMON_BIAS) { + reg_mask = SET_BITS(regAUDIO_RX_0, ALSPREF, 1); + reg_write = SET_BITS(regAUDIO_RX_0, ALSPREF, 1); + } + if (config & HEADSET_DETECT_ENABLE) { + reg_mask |= SET_BITS(regAUDIO_RX_0, HSDETEN, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, HSDETEN, 1); + } + if (config & STEREO_HEADSET_AMP_AUTO_DISABLE) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1); + } + + if (reg_mask == 0) { + rc = PMIC_PARAMETER_ERROR; + } else { + rc = pmic_write_reg(REG_AUDIO_RX_0, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug("Output config set\n"); + audioOutput.config |= config; + + } + } + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Clear various audio output section options. + * + * This function clears one or more audio output section configuration + * options. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The desired audio output section + * configuration options to be cleared. + * + * @retval PMIC_SUCCESS If the desired configuration options were + * all successfully cleared. + * @retval PMIC_PARAMETER_ERROR If the handle or configuration options + * were invalid. + * @retval PMIC_ERROR If the desired configuration options + * could not be cleared. + */ +PMIC_STATUS pmic_audio_output_clear_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_CONFIG + config) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + /*unsigned int reg_write_RX = 0; + unsigned int reg_mask_RX = 0; + unsigned int reg_write_TX = 0; + unsigned int reg_mask_TX = 0; */ + unsigned int reg_mask = 0; + unsigned int reg_write = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if (((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) || + ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) || + ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE))) { + if (config & MONO_SPEAKER_INVERT_OUT_ONLY) { + /* If this is one of the parameters */ + rc = PMIC_NOT_SUPPORTED; + } else { + if (config & MONO_LOUDSPEAKER_COMMON_BIAS) { + reg_mask = SET_BITS(regAUDIO_RX_0, ALSPREF, 1); + reg_write = SET_BITS(regAUDIO_RX_0, ALSPREF, 0); + } + + if (config & HEADSET_DETECT_ENABLE) { + reg_mask |= SET_BITS(regAUDIO_RX_0, HSDETEN, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, HSDETEN, 0); + } + + if (config & STEREO_HEADSET_AMP_AUTO_DISABLE) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 0); + } + + if (reg_mask == 0) { + rc = PMIC_PARAMETER_ERROR; + } else { + rc = pmic_write_reg(REG_AUDIO_RX_0, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug("Output config cleared\n"); + audioOutput.config &= ~config; + + } + } + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the current audio output section options. + * + * This function retrieves the current audio output section configuration + * option settings. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The current audio output section + * configuration option settings. + * + * @retval PMIC_SUCCESS If the current configuration options were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the current configuration options + * could not be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_config(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_OUTPUT_CONFIG * + const config) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) || + ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) || + ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE))) && + (config != (PMIC_AUDIO_OUTPUT_CONFIG *) NULL)) { + *config = audioOutput.config; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Enable the phantom ground circuit that is used to help identify + * the type of headset that has been inserted. + * + * This function enables the phantom ground circuit that is used to help + * identify the type of headset (e.g., stereo or mono) that has been inserted. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the phantom ground circuit was + * successfully enabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the phantom ground circuit could not + * be enabled. + */ +PMIC_STATUS pmic_audio_output_enable_phantom_ground() +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + const unsigned int reg_mask = SET_BITS(regAUDIO_RX_0, HSPGDIS, 1); + + /* No critical section required here since we are not updating any + * global data. + */ + + rc = pmic_write_reg(REG_AUDIO_RX_0, 0, reg_mask); + if (rc == PMIC_SUCCESS) { + pr_debug("Phantom ground enabled\n"); + + } + return rc; +} + +/*! + * @brief Disable the phantom ground circuit that is used to help identify + * the type of headset that has been inserted. + * + * This function disables the phantom ground circuit that is used to help + * identify the type of headset (e.g., stereo or mono) that has been inserted. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the phantom ground circuit was + * successfully disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the phantom ground circuit could not + * be disabled. + */ +PMIC_STATUS pmic_audio_output_disable_phantom_ground() +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + const unsigned int reg_mask = SET_BITS(regAUDIO_RX_0, HSPGDIS, 1); + + /* No critical section required here since we are not updating any + * global data. + */ + + rc = pmic_write_reg(REG_AUDIO_RX_0, 1, reg_mask); + if (rc == PMIC_SUCCESS) { + pr_debug("Phantom ground disabled\n"); + + } + return rc; +} + +/*@}*/ + +/************************************************************************** + * Static functions. + ************************************************************************** + */ + +/*! + * @name Audio Driver Internal Support Functions + * These non-exported internal functions are used to support the functionality + * of the exported audio APIs. + */ +/*@{*/ + +/*! + * @brief Enables the 5.6V boost for the microphone bias 2 circuit. + * + * This function enables the switching regulator SW3 and configures it to + * provide the 5.6V boost that is required for driving the microphone bias 2 + * circuit when using a 5-pole jack configuration (which is the case for the + * Sphinx board). + * + * @retval PMIC_SUCCESS The 5.6V boost was successfully enabled. + * @retval PMIC_ERROR Failed to enable the 5.6V boost. + */ +/* +static PMIC_STATUS pmic_audio_mic_boost_enable(void) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + + return rc; +} +*/ +/*! + * @brief Disables the 5.6V boost for the microphone bias 2 circuit. + * + * This function disables the switching regulator SW3 to turn off the 5.6V + * boost for the microphone bias 2 circuit. + * + * @retval PMIC_SUCCESS The 5.6V boost was successfully disabled. + * @retval PMIC_ERROR Failed to disable the 5.6V boost. + */ +/* +static PMIC_STATUS pmic_audio_mic_boost_disable(void) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + + return rc; +} +*/ + +/*! + * @brief Free a device handle previously acquired by calling pmic_audio_open(). + * + * Terminate further access to the PMIC audio hardware that was previously + * acquired by calling pmic_audio_open(). This now allows another thread to + * successfully call pmic_audio_open() to gain access. + * + * Note that we will shutdown/reset the Voice CODEC or Stereo DAC as well as + * any associated audio input/output components that are no longer required. + * + * Also note that this function should only be called with the mutex already + * acquired. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the close request was successful. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +static PMIC_STATUS pmic_audio_close_handle(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Match up the handle to the audio device and then close it. */ + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + /* Also shutdown the Stereo DAC hardware. The simplest way to + * do this is to simply call pmic_audio_reset_device() which will + * restore the ST_DAC register to it's initial power-on state. + * + * This will also shutdown the audio output section if no one + * else is still using it. + */ + rc = pmic_audio_reset_device(stDAC.handle); + + if (rc == PMIC_SUCCESS) { + stDAC.handle = AUDIO_HANDLE_NULL; + stDAC.handleState = HANDLE_FREE; + } + } else if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) { + /* Also shutdown the Voice CODEC and audio input hardware. The + * simplest way to do this is to simply call pmic_audio_reset_device() + * which will restore the AUD_CODEC register to it's initial + * power-on state. + * + * This will also shutdown the audio output section if no one + * else is still using it. + */ + rc = pmic_audio_reset_device(vCodec.handle); + if (rc == PMIC_SUCCESS) { + vCodec.handle = AUDIO_HANDLE_NULL; + vCodec.handleState = HANDLE_FREE; + } + } else if ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE)) { + + /* Call pmic_audio_reset_device() here to shutdown the audio output + * section if no one else is still using it. + */ + rc = pmic_audio_reset_device(extStereoIn.handle); + + if (rc == PMIC_SUCCESS) { + extStereoIn.handle = AUDIO_HANDLE_NULL; + extStereoIn.handleState = HANDLE_FREE; + } + } + + return rc; +} + +/*! + * @brief Reset the selected audio hardware control registers to their + * power on state. + * + * This resets all of the audio hardware control registers currently + * associated with the device handle back to their power on states. For + * example, if the handle is associated with the Stereo DAC and a + * specific output port and output amplifiers, then this function will + * reset all of those components to their initial power on state. + * + * This function can only be called if the mutex has already been acquired. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the reset operation was successful. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_ERROR If the reset was unsuccessful. + */ +static PMIC_STATUS pmic_audio_reset_device(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask = 0; + + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + /* Also shutdown the audio output section if nobody else is using it. + if ((vCodec.handleState == HANDLE_FREE) && + (extStereoIn.handleState == HANDLE_FREE)) + { + pmic_write_reg(REG_RX_AUD_AMPS, RESET_RX_AUD_AMPS, + REG_FULLMASK); + } */ + + rc = pmic_write_reg(REG_AUDIO_STEREO_DAC, + RESET_ST_DAC, REG_FULLMASK); + + if (rc == PMIC_SUCCESS) { + rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK, + RESET_SSI_NETWORK, + REG_SSI_STDAC_MASK); + if (rc == PMIC_SUCCESS) { + /* Also reset the driver state information to match. Note that we + * keep the device handle and event callback settings unchanged + * since these don't affect the actual hardware and we rely on + * the user to explicitly close the handle or deregister callbacks + */ + stDAC.busID = AUDIO_DATA_BUS_1; + stDAC.protocol = NORMAL_MSB_JUSTIFIED_MODE; + stDAC.protocol_set = false; + stDAC.masterSlave = BUS_MASTER_MODE; + stDAC.numSlots = USE_2_TIMESLOTS; + stDAC.clockIn = CLOCK_IN_CLIA; + stDAC.samplingRate = STDAC_RATE_44_1_KHZ; + stDAC.clockFreq = STDAC_CLI_13MHZ; + stDAC.invert = NO_INVERT; + stDAC.timeslot = USE_TS0_TS1; + stDAC.config = (PMIC_AUDIO_STDAC_CONFIG) 0; + + } + } + } else if ((handle == vCodec.handle) + && (vCodec.handleState == HANDLE_IN_USE)) { + /* Disable the audio input section when disabling the Voice CODEC. */ + pmic_write_reg(REG_AUDIO_TX, RESET_AUDIO_TX, REG_FULLMASK); + + rc = pmic_write_reg(REG_AUDIO_CODEC, + RESET_AUD_CODEC, REG_FULLMASK); + + if (rc == PMIC_SUCCESS) { + rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK, + RESET_SSI_NETWORK, + REG_SSI_VCODEC_MASK); + if (rc == PMIC_SUCCESS) { + + /* Also reset the driver state information to match. Note that we + * keep the device handle and event callback settings unchanged + * since these don't affect the actual hardware and we rely on + * the user to explicitly close the handle or deregister callbacks + */ + vCodec.busID = AUDIO_DATA_BUS_2; + vCodec.protocol = NETWORK_MODE; + vCodec.protocol_set = false; + vCodec.masterSlave = BUS_SLAVE_MODE; + vCodec.numSlots = USE_4_TIMESLOTS; + vCodec.clockIn = CLOCK_IN_CLIB; + vCodec.samplingRate = VCODEC_RATE_8_KHZ; + vCodec.clockFreq = VCODEC_CLI_13MHZ; + vCodec.invert = NO_INVERT; + vCodec.timeslot = USE_TS0; + vCodec.config = + INPUT_HIGHPASS_FILTER | + OUTPUT_HIGHPASS_FILTER; + + } + } + + } else if ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE)) { + /* Disable the Ext stereo Amplifier and disable it as analog mixer input */ + reg_mask = SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + pmic_write_reg(REG_AUDIO_RX_1, 0, reg_mask); + + reg_mask = SET_BITS(regAUDIO_RX_0, ADDRXIN, 1); + pmic_write_reg(REG_AUDIO_RX_0, 0, reg_mask); + + /* We don't need to reset any other registers for this case. */ + rc = PMIC_SUCCESS; + } + + return rc; +} + +/*! + * @brief Deregister the callback function and event mask currently associated + * with an audio device handle. + * + * This function deregisters any existing callback function and event mask for + * the given audio device handle. This is done by either calling the + * pmic_audio_clear_callback() API or by closing the device handle. + * + * Note that this function should only be called with the mutex already + * acquired. We will also acquire the spinlock here to prevent possible + * race conditions with the interrupt handler. + * + * @param[in] callback The current event callback function pointer. + * @param[in] eventMask The current audio event mask. + * + * @retval PMIC_SUCCESS If the callback function and event mask + * were both successfully deregistered. + * @retval PMIC_ERROR If either the callback function or the + * event mask was not successfully + * deregistered. + */ + +static PMIC_STATUS pmic_audio_deregister(void *callback, + PMIC_AUDIO_EVENTS * const eventMask) +{ + unsigned long flags; + pmic_event_callback_t eventNotify; + PMIC_STATUS rc = PMIC_SUCCESS; + + /* Deregister each of the PMIC events that we had previously + * registered for by calling pmic_event_subscribe(). + */ + if (*eventMask & (HEADSET_DETECTED)) { + /* We need to deregister for the A1 amplifier interrupt. */ + eventNotify.func = callback; + eventNotify.param = (void *)(CORE_EVENT_HSDETI); + if (pmic_event_unsubscribe(EVENT_HSDETI, eventNotify) == + PMIC_SUCCESS) { + *eventMask &= ~(HEADSET_DETECTED); + pr_debug("Deregistered for EVENT_HSDETI\n"); + } else { + rc = PMIC_ERROR; + } + } + + if (*eventMask & (HEADSET_STEREO)) { + /* We need to deregister for the A1 amplifier interrupt. */ + eventNotify.func = callback; + eventNotify.param = (void *)(CORE_EVENT_HSLI); + if (pmic_event_unsubscribe(EVENT_HSLI, eventNotify) == + PMIC_SUCCESS) { + *eventMask &= ~(HEADSET_STEREO); + pr_debug("Deregistered for EVENT_HSLI\n"); + } else { + rc = PMIC_ERROR; + } + } + if (*eventMask & (HEADSET_THERMAL_SHUTDOWN)) { + /* We need to deregister for the A1 amplifier interrupt. */ + eventNotify.func = callback; + eventNotify.param = (void *)(CORE_EVENT_ALSPTHI); + if (pmic_event_unsubscribe(EVENT_ALSPTHI, eventNotify) == + PMIC_SUCCESS) { + *eventMask &= ~(HEADSET_THERMAL_SHUTDOWN); + pr_debug("Deregistered for EVENT_ALSPTHI\n"); + } else { + rc = PMIC_ERROR; + } + } + if (*eventMask & (HEADSET_SHORT_CIRCUIT)) { + /* We need to deregister for the A1 amplifier interrupt. */ + eventNotify.func = callback; + eventNotify.param = (void *)(CORE_EVENT_AHSSHORTI); + if (pmic_event_unsubscribe(EVENT_AHSSHORTI, eventNotify) == + PMIC_SUCCESS) { + *eventMask &= ~(HEADSET_SHORT_CIRCUIT); + pr_debug("Deregistered for EVENT_AHSSHORTI\n"); + } else { + rc = PMIC_ERROR; + } + } + + if (rc == PMIC_SUCCESS) { + /* We need to grab the spinlock here to create a critical section to + * avoid any possible race conditions with the interrupt handler + */ + spin_lock_irqsave(&lock, flags); + + /* Restore the initial reset values for the callback function + * and event mask parameters. This should be NULL and zero, + * respectively. + */ + callback = NULL; + *eventMask = 0; + + /* Exit the critical section. */ + spin_unlock_irqrestore(&lock, flags); + } + + return rc; +} + +/*! + * @brief enable/disable fm output. + * + * @param[in] enable true to enable false to disable + */ +PMIC_STATUS pmic_audio_fm_output_enable(bool enable) +{ + unsigned int reg_mask = 0; + unsigned int reg_write = 0; + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + if (enable) { + pmic_audio_antipop_enable(ANTI_POP_RAMP_FAST); + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1); + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSREN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, AHSREN, 1); + + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSSEL, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, AHSSEL, 1); + + reg_mask |= SET_BITS(regAUDIO_RX_0, ADDRXIN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, ADDRXIN, 1); + + reg_mask |= SET_BITS(regAUDIO_RX_0, HSPGDIS, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, HSPGDIS, 0); + } else { + reg_mask |= SET_BITS(regAUDIO_RX_0, ADDRXIN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, ADDRXIN, 0); + } + rc = pmic_write_reg(REG_AUDIO_RX_0, reg_write, reg_mask); + if (rc != PMIC_SUCCESS) + return rc; + if (enable) { + reg_mask = SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + reg_write = SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + } else { + reg_mask = SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + reg_write = SET_BITS(regAUDIO_RX_1, ARXINEN, 0); + } + rc = pmic_write_reg(REG_AUDIO_RX_1, reg_write, reg_mask); + return rc; +} + +/*@}*/ + +/************************************************************************** + * Module initialization and termination functions. + * + * Note that if this code is compiled into the kernel, then the + * module_init() function will be called within the device_initcall() + * group. + ************************************************************************** + */ + +/*! + * @name Audio Driver Loading/Unloading Functions + * These non-exported internal functions are used to support the audio + * device driver initialization and de-initialization operations. + */ +/*@{*/ + +/*! + * @brief This is the audio device driver initialization function. + * + * This function is called by the kernel when this device driver is first + * loaded. + */ +static int __init mc13783_pmic_audio_init(void) +{ + printk(KERN_INFO "PMIC Audio driver loading...\n"); + + return 0; +} + +/*! + * @brief This is the audio device driver de-initialization function. + * + * This function is called by the kernel when this device driver is about + * to be unloaded. + */ +static void __exit mc13783_pmic_audio_exit(void) +{ + printk(KERN_INFO "PMIC Audio driver unloading...\n"); + + /* Close all device handles that are still open. This will also + * deregister any callbacks that may still be active. + */ + if (stDAC.handleState == HANDLE_IN_USE) { + pmic_audio_close(stDAC.handle); + } + if (vCodec.handleState == HANDLE_IN_USE) { + pmic_audio_close(vCodec.handle); + } + if (extStereoIn.handleState == HANDLE_IN_USE) { + pmic_audio_close(extStereoIn.handle); + } + + /* Explicitly reset all of the audio registers so that there is no + * possibility of leaving the audio hardware in a state + * where it can cause problems if there is no device driver loaded. + */ + pmic_write_reg(REG_AUDIO_STEREO_DAC, RESET_ST_DAC, REG_FULLMASK); + pmic_write_reg(REG_AUDIO_CODEC, RESET_AUD_CODEC, REG_FULLMASK); + pmic_write_reg(REG_AUDIO_TX, RESET_AUDIO_TX, REG_FULLMASK); + pmic_write_reg(REG_AUDIO_SSI_NETWORK, RESET_SSI_NETWORK, REG_FULLMASK); + pmic_write_reg(REG_AUDIO_RX_0, RESET_AUDIO_RX_0, REG_FULLMASK); + pmic_write_reg(REG_AUDIO_RX_1, RESET_AUDIO_RX_1, REG_FULLMASK); +} + +/*@}*/ + +/* + * Module entry points and description information. + */ + +module_init(mc13783_pmic_audio_init); +module_exit(mc13783_pmic_audio_exit); + +MODULE_DESCRIPTION("PMIC - mc13783 ADC driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_battery.c linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_battery.c --- linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_battery.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_battery.c 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,1221 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_battery.c + * @brief This is the main file of PMIC(mc13783) Battery driver. + * + * @ingroup PMIC_BATTERY + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "pmic_battery_defs.h" + +#include +#ifdef CONFIG_MXC_HWEVENT +#include +#endif + +static int pmic_battery_major; + +/*! + * Number of users waiting in suspendq + */ +static int swait = 0; + +/*! + * To indicate whether any of the battery devices are suspending + */ +static int suspend_flag = 0; + +/*! + * The suspendq is used to block application calls + */ +static wait_queue_head_t suspendq; + +static struct class *pmic_battery_class; + +/* EXPORTED FUNCTIONS */ +EXPORT_SYMBOL(pmic_batt_enable_charger); +EXPORT_SYMBOL(pmic_batt_disable_charger); +EXPORT_SYMBOL(pmic_batt_set_charger); +EXPORT_SYMBOL(pmic_batt_get_charger_setting); +EXPORT_SYMBOL(pmic_batt_get_charge_current); +EXPORT_SYMBOL(pmic_batt_enable_eol); +EXPORT_SYMBOL(pmic_batt_bp_enable_eol); +EXPORT_SYMBOL(pmic_batt_disable_eol); +EXPORT_SYMBOL(pmic_batt_set_out_control); +EXPORT_SYMBOL(pmic_batt_set_threshold); +EXPORT_SYMBOL(pmic_batt_led_control); +EXPORT_SYMBOL(pmic_batt_set_reverse_supply); +EXPORT_SYMBOL(pmic_batt_set_unregulated); +EXPORT_SYMBOL(pmic_batt_set_5k_pull); +EXPORT_SYMBOL(pmic_batt_event_subscribe); +EXPORT_SYMBOL(pmic_batt_event_unsubscribe); + +static DECLARE_MUTEX(count_mutex); /* open count mutex */ +static int open_count; /* open count for device file */ + +/*! + * Callback function for events, we want on MGN board + */ +static void callback_chg_detect(void) +{ +#ifdef CONFIG_MXC_HWEVENT + t_sensor_bits sensor; + struct mxc_hw_event event = { HWE_BAT_CHARGER_PLUG, 0 }; + + pr_debug("In callback_chg_detect\n"); + + /* get sensor values */ + pmic_get_sensors(&sensor); + + pr_debug("Callback, charger detect:%d\n", sensor.sense_chgdets); + + if (sensor.sense_chgdets) + event.args = 1; + else + event.args = 0; + /* send hardware event */ + hw_event_send(HWE_DEF_PRIORITY, &event); +#endif +} + +static void callback_low_battery(void) +{ +#ifdef CONFIG_MXC_HWEVENT + struct mxc_hw_event event = { HWE_BAT_BATTERY_LOW, 0 }; + + pr_debug("In callback_low_battery\n"); + /* send hardware event */ + hw_event_send(HWE_DEF_PRIORITY, &event); +#endif +} + +static void callback_power_fail(void) +{ +#ifdef CONFIG_MXC_HWEVENT + struct mxc_hw_event event = { HWE_BAT_POWER_FAILED, 0 }; + + pr_debug("In callback_power_fail\n"); + /* send hardware event */ + hw_event_send(HWE_DEF_PRIORITY, &event); +#endif +} + +static void callback_chg_overvoltage(void) +{ +#ifdef CONFIG_MXC_HWEVENT + struct mxc_hw_event event = { HWE_BAT_CHARGER_OVERVOLTAGE, 0 }; + + pr_debug("In callback_chg_overvoltage\n"); + /* send hardware event */ + hw_event_send(HWE_DEF_PRIORITY, &event); +#endif +} + +static void callback_chg_full(void) +{ +#ifdef CONFIG_MXC_HWEVENT + t_sensor_bits sensor; + struct mxc_hw_event event = { HWE_BAT_CHARGER_FULL, 0 }; + + pr_debug("In callback_chg_full\n"); + + /* disable charge function */ + pmic_batt_disable_charger(BATT_MAIN_CHGR); + + /* get charger sensor */ + pmic_get_sensors(&sensor); + + /* if did not detect the charger */ + if (sensor.sense_chgdets) + return; + /* send hardware event */ + hw_event_send(HWE_DEF_PRIORITY, &event); +#endif +} + +/*! + * This is the suspend of power management for the pmic battery API. + * It suports SAVE and POWER_DOWN state. + * + * @param pdev the device + * @param state the state + * + * @return This function returns 0 if successful. + */ +static int pmic_battery_suspend(struct platform_device *pdev, + pm_message_t state) +{ + unsigned int reg_value = 0; + + suspend_flag = 1; + CHECK_ERROR(pmic_write_reg(REG_CHARGER, reg_value, PMIC_ALL_BITS)); + + return 0; +}; + +/*! + * This is the resume of power management for the pmic battery API. + * It suports RESTORE state. + * + * @param pdev the device + * + * @return This function returns 0 if successful. + */ +static int pmic_battery_resume(struct platform_device *pdev) +{ + suspend_flag = 0; + while (swait > 0) { + swait--; + wake_up_interruptible(&suspendq); + } + + return 0; +}; + +/*! + * This function is used to start charging a battery. For different charger, + * different voltage and current range are supported. \n + * + * + * @param chgr Charger as defined in \b t_batt_charger. + * @param c_voltage Charging voltage. + * @param c_current Charging current. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_enable_charger(t_batt_charger chgr, + unsigned char c_voltage, + unsigned char c_current) +{ + unsigned int val, mask, reg; + + val = 0; + mask = 0; + reg = 0; + + if (suspend_flag == 1) + return PMIC_ERROR; + + switch (chgr) { + case BATT_MAIN_CHGR: + val = BITFVAL(MC13783_BATT_DAC_DAC, c_current) | + BITFVAL(MC13783_BATT_DAC_V_DAC, c_voltage); + mask = BITFMASK(MC13783_BATT_DAC_DAC) | + BITFMASK(MC13783_BATT_DAC_V_DAC); + reg = REG_CHARGER; + break; + + case BATT_CELL_CHGR: + val = BITFVAL(MC13783_BATT_DAC_V_COIN, c_voltage) | + BITFVAL(MC13783_BATT_DAC_COIN_CH_EN, + MC13783_BATT_DAC_COIN_CH_EN_ENABLED); + mask = BITFMASK(MC13783_BATT_DAC_V_COIN) | + BITFMASK(MC13783_BATT_DAC_COIN_CH_EN); + reg = REG_POWER_CONTROL_0; + break; + + case BATT_TRCKLE_CHGR: + val = BITFVAL(MC13783_BATT_DAC_TRCKLE, c_current); + mask = BITFMASK(MC13783_BATT_DAC_TRCKLE); + reg = REG_CHARGER; + break; + + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, val, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function turns off a charger. + * + * @param chgr Charger as defined in \b t_batt_charger. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_disable_charger(t_batt_charger chgr) +{ + unsigned int val, mask, reg; + + val = 0; + mask = 0; + reg = 0; + + if (suspend_flag == 1) + return PMIC_ERROR; + switch (chgr) { + case BATT_MAIN_CHGR: + val = BITFVAL(MC13783_BATT_DAC_DAC, 0) | + BITFVAL(MC13783_BATT_DAC_V_DAC, 0); + mask = BITFMASK(MC13783_BATT_DAC_DAC) | + BITFMASK(MC13783_BATT_DAC_V_DAC); + reg = REG_CHARGER; + break; + + case BATT_CELL_CHGR: + val = BITFVAL(MC13783_BATT_DAC_COIN_CH_EN, + MC13783_BATT_DAC_COIN_CH_EN_DISABLED); + mask = BITFMASK(MC13783_BATT_DAC_COIN_CH_EN); + reg = REG_POWER_CONTROL_0; + break; + + case BATT_TRCKLE_CHGR: + val = BITFVAL(MC13783_BATT_DAC_TRCKLE, 0); + mask = BITFMASK(MC13783_BATT_DAC_TRCKLE); + reg = REG_CHARGER; + break; + + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, val, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function is used to change the charger setting. + * + * @param chgr Charger as defined in \b t_batt_charger. + * @param c_voltage Charging voltage. + * @param c_current Charging current. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_set_charger(t_batt_charger chgr, + unsigned char c_voltage, + unsigned char c_current) +{ + unsigned int val, mask, reg; + + val = 0; + mask = 0; + reg = 0; + + if (suspend_flag == 1) + return PMIC_ERROR; + + switch (chgr) { + case BATT_MAIN_CHGR: + val = BITFVAL(MC13783_BATT_DAC_DAC, c_current) | + BITFVAL(MC13783_BATT_DAC_V_DAC, c_voltage); + mask = BITFMASK(MC13783_BATT_DAC_DAC) | + BITFMASK(MC13783_BATT_DAC_V_DAC); + reg = REG_CHARGER; + break; + + case BATT_CELL_CHGR: + val = BITFVAL(MC13783_BATT_DAC_V_COIN, c_voltage); + mask = BITFMASK(MC13783_BATT_DAC_V_COIN); + reg = REG_POWER_CONTROL_0; + break; + + case BATT_TRCKLE_CHGR: + val = BITFVAL(MC13783_BATT_DAC_TRCKLE, c_current); + mask = BITFMASK(MC13783_BATT_DAC_TRCKLE); + reg = REG_CHARGER; + break; + + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, val, mask)); + return PMIC_SUCCESS; +} + +/*! + * This function is used to retrive the charger setting. + * + * @param chgr Charger as defined in \b t_batt_charger. + * @param c_voltage Output parameter for charging voltage setting. + * @param c_current Output parameter for charging current setting. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_get_charger_setting(t_batt_charger chgr, + unsigned char *c_voltage, + unsigned char *c_current) +{ + unsigned int val, reg; + + reg = 0; + + if (suspend_flag == 1) + return PMIC_ERROR; + + switch (chgr) { + case BATT_MAIN_CHGR: + case BATT_TRCKLE_CHGR: + reg = REG_CHARGER; + break; + case BATT_CELL_CHGR: + reg = REG_POWER_CONTROL_0; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, &val, PMIC_ALL_BITS)); + + switch (chgr) { + case BATT_MAIN_CHGR: + *c_voltage = BITFEXT(val, MC13783_BATT_DAC_V_DAC);; + *c_current = BITFEXT(val, MC13783_BATT_DAC_DAC); + break; + + case BATT_CELL_CHGR: + *c_voltage = BITFEXT(val, MC13783_BATT_DAC_V_COIN); + *c_current = 0; + break; + + case BATT_TRCKLE_CHGR: + *c_voltage = 0; + *c_current = BITFEXT(val, MC13783_BATT_DAC_TRCKLE); + break; + + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function is retrives the main battery voltage. + * + * @param b_voltage Output parameter for voltage setting. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_get_batt_voltage(unsigned short *b_voltage) +{ + t_channel channel; + unsigned short result[8]; + + if (suspend_flag == 1) + return PMIC_ERROR; + channel = BATTERY_VOLTAGE; + CHECK_ERROR(pmic_adc_convert(channel, result)); + *b_voltage = result[0]; + + return PMIC_SUCCESS; +} + +/*! + * This function is retrives the main battery current. + * + * @param b_current Output parameter for current setting. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_get_batt_current(unsigned short *b_current) +{ + t_channel channel; + unsigned short result[8]; + + if (suspend_flag == 1) + return PMIC_ERROR; + + channel = BATTERY_CURRENT; + CHECK_ERROR(pmic_adc_convert(channel, result)); + *b_current = result[0]; + + return PMIC_SUCCESS; +} + +/*! + * This function is retrives the main battery temperature. + * + * @param b_temper Output parameter for temperature setting. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_get_batt_temperature(unsigned short *b_temper) +{ + t_channel channel; + unsigned short result[8]; + + if (suspend_flag == 1) + return PMIC_ERROR; + + channel = GEN_PURPOSE_AD5; + CHECK_ERROR(pmic_adc_convert(channel, result)); + *b_temper = result[0]; + + return PMIC_SUCCESS; +} + +/*! + * This function is retrives the main battery charging voltage. + * + * @param c_voltage Output parameter for charging voltage setting. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_get_charge_voltage(unsigned short *c_voltage) +{ + t_channel channel; + unsigned short result[8]; + + if (suspend_flag == 1) + return PMIC_ERROR; + + channel = CHARGE_VOLTAGE; + CHECK_ERROR(pmic_adc_convert(channel, result)); + *c_voltage = result[0]; + + return PMIC_SUCCESS; +} + +/*! + * This function is retrives the main battery charging current. + * + * @param c_current Output parameter for charging current setting. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_get_charge_current(unsigned short *c_current) +{ + t_channel channel; + unsigned short result[8]; + + if (suspend_flag == 1) + return PMIC_ERROR; + + channel = CHARGE_CURRENT; + CHECK_ERROR(pmic_adc_convert(channel, result)); + *c_current = result[0]; + + return PMIC_SUCCESS; +} + +/*! + * This function enables End-of-Life comparator. Not supported on + * mc13783. Use pmic_batt_bp_enable_eol function. + * + * @param threshold End-of-Life threshold. + * + * @return This function returns PMIC_UNSUPPORTED + */ +PMIC_STATUS pmic_batt_enable_eol(unsigned char threshold) +{ + return PMIC_NOT_SUPPORTED; +} + +/*! + * This function enables End-of-Life comparator. + * + * @param typical Falling Edge Threshold threshold. + * @verbatim + BPDET UVDET LOBATL + ____ _____ ___________ + 0 2.6 UVDET + 0.2 + 1 2.6 UVDET + 0.3 + 2 2.6 UVDET + 0.4 + 3 2.6 UVDET + 0.5 + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_bp_enable_eol(t_bp_threshold typical) +{ + unsigned int val, mask; + + if (suspend_flag == 1) + return PMIC_ERROR; + + val = BITFVAL(MC13783_BATT_DAC_EOL_CMP_EN, + MC13783_BATT_DAC_EOL_CMP_EN_ENABLE) | + BITFVAL(MC13783_BATT_DAC_EOL_SEL, typical); + mask = BITFMASK(MC13783_BATT_DAC_EOL_CMP_EN) | + BITFMASK(MC13783_BATT_DAC_EOL_SEL); + + CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_0, val, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function disables End-of-Life comparator. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_disable_eol(void) +{ + unsigned int val, mask; + + if (suspend_flag == 1) + return PMIC_ERROR; + + val = BITFVAL(MC13783_BATT_DAC_EOL_CMP_EN, + MC13783_BATT_DAC_EOL_CMP_EN_DISABLE); + mask = BITFMASK(MC13783_BATT_DAC_EOL_CMP_EN); + + CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_0, val, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function sets the output controls. + * It sets the FETOVRD and FETCTRL bits of mc13783 + * + * @param control type of control. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_batt_set_out_control(t_control control) +{ + unsigned int val, mask; + if (suspend_flag == 1) + return PMIC_ERROR; + + switch (control) { + case CONTROL_HARDWARE: + val = BITFVAL(MC13783_BATT_DAC_FETOVRD_EN, 0) | + BITFVAL(MC13783_BATT_DAC_FETCTRL_EN, 0); + mask = BITFMASK(MC13783_BATT_DAC_FETOVRD_EN) | + BITFMASK(MC13783_BATT_DAC_FETCTRL_EN); + break; + case CONTROL_BPFET_LOW: + val = BITFVAL(MC13783_BATT_DAC_FETOVRD_EN, 1) | + BITFVAL(MC13783_BATT_DAC_FETCTRL_EN, 0); + mask = BITFMASK(MC13783_BATT_DAC_FETOVRD_EN) | + BITFMASK(MC13783_BATT_DAC_FETCTRL_EN); + break; + case CONTROL_BPFET_HIGH: + val = BITFVAL(MC13783_BATT_DAC_FETOVRD_EN, 1) | + BITFVAL(MC13783_BATT_DAC_FETCTRL_EN, 1); + mask = BITFMASK(MC13783_BATT_DAC_FETOVRD_EN) | + BITFMASK(MC13783_BATT_DAC_FETCTRL_EN); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask)); + return PMIC_SUCCESS; +} + +/*! + * This function sets over voltage threshold. + * + * @param threshold value of over voltage threshold. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_batt_set_threshold(int threshold) +{ + unsigned int val, mask; + + if (suspend_flag == 1) + return PMIC_ERROR; + + if (threshold > BAT_THRESHOLD_MAX) + return PMIC_PARAMETER_ERROR; + + val = BITFVAL(MC13783_BATT_DAC_OVCTRL, threshold); + mask = BITFMASK(MC13783_BATT_DAC_OVCTRL); + CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask)); + return PMIC_SUCCESS; +} + +/*! + * This function controls charge LED. + * + * @param on If on is ture, LED will be turned on, + * or otherwise, LED will be turned off. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_led_control(bool on) +{ + unsigned val, mask; + + if (suspend_flag == 1) + return PMIC_ERROR; + + val = BITFVAL(MC13783_BATT_DAC_LED_EN, on); + mask = BITFMASK(MC13783_BATT_DAC_LED_EN); + + CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function sets reverse supply mode. + * + * @param enable If enable is ture, reverse supply mode is enable, + * or otherwise, reverse supply mode is disabled. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_set_reverse_supply(bool enable) +{ + unsigned val, mask; + + if (suspend_flag == 1) + return PMIC_ERROR; + + val = BITFVAL(MC13783_BATT_DAC_REVERSE_SUPPLY, enable); + mask = BITFMASK(MC13783_BATT_DAC_REVERSE_SUPPLY); + + CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function sets unregulatored charging mode on main battery. + * + * @param enable If enable is ture, unregulated charging mode is + * enable, or otherwise, disabled. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_set_unregulated(bool enable) +{ + unsigned val, mask; + + if (suspend_flag == 1) + return PMIC_ERROR; + + val = BITFVAL(MC13783_BATT_DAC_UNREGULATED, enable); + mask = BITFMASK(MC13783_BATT_DAC_UNREGULATED); + + CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function sets a 5K pull down at CHRGRAW. + * To be used in the dual path charging configuration. + * + * @param enable If enable is true, 5k pull down is + * enable, or otherwise, disabled. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_set_5k_pull(bool enable) +{ + unsigned val, mask; + + if (suspend_flag == 1) + return PMIC_ERROR; + + val = BITFVAL(MC13783_BATT_DAC_5K, enable); + mask = BITFMASK(MC13783_BATT_DAC_5K); + + CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function is used to un/subscribe on battery event IT. + * + * @param event type of event. + * @param callback event callback function. + * @param sub define if Un/subscribe event. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS mc13783_battery_event(t_batt_event event, void *callback, bool sub) +{ + pmic_event_callback_t bat_callback; + type_event bat_event; + + bat_callback.func = callback; + bat_callback.param = NULL; + switch (event) { + case BAT_IT_CHG_DET: + bat_event = EVENT_CHGDETI; + break; + case BAT_IT_CHG_OVERVOLT: + bat_event = EVENT_CHGOVI; + break; + case BAT_IT_CHG_REVERSE: + bat_event = EVENT_CHGREVI; + break; + case BAT_IT_CHG_SHORT_CIRCUIT: + bat_event = EVENT_CHGSHORTI; + break; + case BAT_IT_CCCV: + bat_event = EVENT_CCCVI; + break; + case BAT_IT_BELOW_THRESHOLD: + bat_event = EVENT_CHRGCURRI; + break; + default: + return PMIC_PARAMETER_ERROR; + } + if (sub == true) { + CHECK_ERROR(pmic_event_subscribe(bat_event, bat_callback)); + } else { + CHECK_ERROR(pmic_event_unsubscribe(bat_event, bat_callback)); + } + return 0; +} + +/*! + * This function is used to subscribe on battery event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_batt_event_subscribe(t_batt_event event, void *callback) +{ + if (suspend_flag == 1) + return PMIC_ERROR; + + return mc13783_battery_event(event, callback, true); +} + +/*! + * This function is used to un subscribe on battery event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_batt_event_unsubscribe(t_batt_event event, void *callback) +{ + if (suspend_flag == 1) + return PMIC_ERROR; + + return mc13783_battery_event(event, callback, false); +} + +/*! + * This function implements IOCTL controls on a PMIC Battery device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @param cmd the command + * @param arg the parameter + * @return This function returns 0 if successful. + */ +static int pmic_battery_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + t_charger_setting *chgr_setting = NULL; + unsigned short c_current; + unsigned int bc_info; + t_eol_setting *eol_setting; + + if (_IOC_TYPE(cmd) != 'p') + return -ENOTTY; + + switch (cmd) { + case PMIC_BATT_CHARGER_CONTROL: + if ((chgr_setting = kmalloc(sizeof(t_charger_setting), + GFP_KERNEL)) == NULL) { + return -ENOMEM; + } + if (copy_from_user(chgr_setting, (t_charger_setting *) arg, + sizeof(t_charger_setting))) { + kfree(chgr_setting); + return -EFAULT; + } + + if (chgr_setting->on != false) { + CHECK_ERROR_KFREE(pmic_batt_enable_charger + (chgr_setting->chgr, + chgr_setting->c_voltage, + chgr_setting->c_current), + (kfree(chgr_setting))); + } else { + CHECK_ERROR(pmic_batt_disable_charger + (chgr_setting->chgr)); + } + + kfree(chgr_setting); + break; + + case PMIC_BATT_SET_CHARGER: + if ((chgr_setting = kmalloc(sizeof(t_charger_setting), + GFP_KERNEL)) == NULL) { + return -ENOMEM; + } + if (copy_from_user(chgr_setting, (t_charger_setting *) arg, + sizeof(t_charger_setting))) { + kfree(chgr_setting); + return -EFAULT; + } + + CHECK_ERROR_KFREE(pmic_batt_set_charger(chgr_setting->chgr, + chgr_setting->c_voltage, + chgr_setting-> + c_current), + (kfree(chgr_setting))); + + kfree(chgr_setting); + break; + + case PMIC_BATT_GET_CHARGER: + if ((chgr_setting = kmalloc(sizeof(t_charger_setting), + GFP_KERNEL)) == NULL) { + return -ENOMEM; + } + if (copy_from_user(chgr_setting, (t_charger_setting *) arg, + sizeof(t_charger_setting))) { + kfree(chgr_setting); + return -EFAULT; + } + + CHECK_ERROR_KFREE(pmic_batt_get_charger_setting + (chgr_setting->chgr, &chgr_setting->c_voltage, + &chgr_setting->c_current), + (kfree(chgr_setting))); + if (copy_to_user + ((t_charger_setting *) arg, chgr_setting, + sizeof(t_charger_setting))) { + return -EFAULT; + } + + kfree(chgr_setting); + break; + + case PMIC_BATT_GET_CHARGER_SENSOR: + { + t_sensor_bits sensor; + pmic_get_sensors(&sensor); + if (copy_to_user + ((unsigned int *)arg, &sensor.sense_chgdets, + sizeof(unsigned int))) + return -EFAULT; + + break; + } + case PMIC_BATT_GET_BATTERY_VOLTAGE: + CHECK_ERROR(pmic_batt_get_batt_voltage(&c_current)); + bc_info = (unsigned int)c_current * 2300 / 1023 + 2400; + if (copy_to_user((unsigned int *)arg, &bc_info, + sizeof(unsigned int))) + return -EFAULT; + + break; + + case PMIC_BATT_GET_BATTERY_CURRENT: + CHECK_ERROR(pmic_batt_get_batt_current(&c_current)); + bc_info = (unsigned int)c_current * 5750 / 1023; + if (copy_to_user((unsigned int *)arg, &bc_info, + sizeof(unsigned int))) + return -EFAULT; + break; + + case PMIC_BATT_GET_BATTERY_TEMPERATURE: + CHECK_ERROR(pmic_batt_get_batt_temperature(&c_current)); + bc_info = (unsigned int)c_current; + if (copy_to_user((unsigned int *)arg, &bc_info, + sizeof(unsigned int))) + return -EFAULT; + + break; + + case PMIC_BATT_GET_CHARGER_VOLTAGE: + CHECK_ERROR(pmic_batt_get_charge_voltage(&c_current)); + bc_info = (unsigned int)c_current * 23000 / 1023; + if (copy_to_user((unsigned int *)arg, &bc_info, + sizeof(unsigned int))) + return -EFAULT; + + break; + + case PMIC_BATT_GET_CHARGER_CURRENT: + CHECK_ERROR(pmic_batt_get_charge_current(&c_current)); + bc_info = (unsigned int)c_current * 5750 / 1023; + if (copy_to_user((unsigned int *)arg, &bc_info, + sizeof(unsigned int))) + return -EFAULT; + + break; + + case PMIC_BATT_EOL_CONTROL: + if ((eol_setting = kmalloc(sizeof(t_eol_setting), GFP_KERNEL)) + == NULL) { + return -ENOMEM; + } + if (copy_from_user(eol_setting, (t_eol_setting *) arg, + sizeof(t_eol_setting))) { + kfree(eol_setting); + return -EFAULT; + } + + if (eol_setting->enable != false) { + CHECK_ERROR_KFREE(pmic_batt_bp_enable_eol + (eol_setting->typical), + (kfree(chgr_setting))); + } else { + CHECK_ERROR_KFREE(pmic_batt_disable_eol(), + (kfree(chgr_setting))); + } + + kfree(eol_setting); + break; + + case PMIC_BATT_SET_OUT_CONTROL: + CHECK_ERROR(pmic_batt_set_out_control((t_control) arg)); + break; + + case PMIC_BATT_SET_THRESHOLD: + CHECK_ERROR(pmic_batt_set_threshold((int)arg)); + break; + + case PMIC_BATT_LED_CONTROL: + CHECK_ERROR(pmic_batt_led_control((bool) arg)); + break; + + case PMIC_BATT_REV_SUPP_CONTROL: + CHECK_ERROR(pmic_batt_set_reverse_supply((bool) arg)); + break; + + case PMIC_BATT_UNREG_CONTROL: + CHECK_ERROR(pmic_batt_set_unregulated((bool) arg)); + break; + + default: + return -EINVAL; + } + return 0; +} + +/*! + * This function implements the open method on a Pmic battery device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int pmic_battery_open(struct inode *inode, struct file *file) +{ + while (suspend_flag == 1) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, (suspend_flag == 0))) { + return -ERESTARTSYS; + } + } + + /* check open count, if open firstly, register callbacks */ + down(&count_mutex); + if (open_count++ > 0) { + up(&count_mutex); + return 0; + } + + pr_debug("Subscribe the callbacks\n"); + /* register battery event callback */ + if (pmic_batt_event_subscribe(BAT_IT_CHG_DET, callback_chg_detect)) { + pr_debug("Failed to subscribe the charger detect callback\n"); + goto event_err1; + } + if (pmic_power_event_sub(PWR_IT_LOBATLI, callback_power_fail)) { + pr_debug("Failed to subscribe the power failed callback\n"); + goto event_err2; + } + if (pmic_power_event_sub(PWR_IT_LOBATHI, callback_low_battery)) { + pr_debug("Failed to subscribe the low battery callback\n"); + goto event_err3; + } + if (pmic_batt_event_subscribe + (BAT_IT_CHG_OVERVOLT, callback_chg_overvoltage)) { + pr_debug("Failed to subscribe the low battery callback\n"); + goto event_err4; + } + if (pmic_batt_event_subscribe + (BAT_IT_BELOW_THRESHOLD, callback_chg_full)) { + pr_debug("Failed to subscribe the charge full callback\n"); + goto event_err5; + } + + up(&count_mutex); + + return 0; + + /* un-subscribe the event callbacks */ +event_err5: + pmic_batt_event_unsubscribe(BAT_IT_CHG_OVERVOLT, + callback_chg_overvoltage); +event_err4: + pmic_power_event_unsub(PWR_IT_LOBATHI, callback_low_battery); +event_err3: + pmic_power_event_unsub(PWR_IT_LOBATLI, callback_power_fail); +event_err2: + pmic_batt_event_unsubscribe(BAT_IT_CHG_DET, callback_chg_detect); +event_err1: + + open_count--; + up(&count_mutex); + + return -EFAULT; + +} + +/*! + * This function implements the release method on a Pmic battery device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int pmic_battery_release(struct inode *inode, struct file *file) +{ + while (suspend_flag == 1) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, (suspend_flag == 0))) { + return -ERESTARTSYS; + } + } + + /* check open count, if open firstly, register callbacks */ + down(&count_mutex); + if (--open_count == 0) { + /* unregister these event callback */ + pr_debug("Unsubscribe the callbacks\n"); + pmic_batt_event_unsubscribe(BAT_IT_BELOW_THRESHOLD, + callback_chg_full); + pmic_batt_event_unsubscribe(BAT_IT_CHG_OVERVOLT, + callback_chg_overvoltage); + pmic_power_event_unsub(PWR_IT_LOBATHI, callback_low_battery); + pmic_power_event_unsub(PWR_IT_LOBATLI, callback_power_fail); + pmic_batt_event_unsubscribe(BAT_IT_CHG_DET, + callback_chg_detect); + } + up(&count_mutex); + + return 0; +} + +static struct file_operations pmic_battery_fops = { + .owner = THIS_MODULE, + .ioctl = pmic_battery_ioctl, + .open = pmic_battery_open, + .release = pmic_battery_release, +}; + +static int pmic_battery_remove(struct platform_device *pdev) +{ + device_destroy(pmic_battery_class, MKDEV(pmic_battery_major, 0)); + class_destroy(pmic_battery_class); + unregister_chrdev(pmic_battery_major, PMIC_BATTERY_STRING); + return 0; +} + +static int pmic_battery_probe(struct platform_device *pdev) +{ + int ret = 0; + struct device *temp_class; + + pmic_battery_major = register_chrdev(0, PMIC_BATTERY_STRING, + &pmic_battery_fops); + + if (pmic_battery_major < 0) { + printk(KERN_ERR "Unable to get a major for pmic_battery\n"); + return pmic_battery_major; + } + init_waitqueue_head(&suspendq); + + pmic_battery_class = class_create(THIS_MODULE, PMIC_BATTERY_STRING); + if (IS_ERR(pmic_battery_class)) { + printk(KERN_ERR "Error creating PMIC battery class.\n"); + ret = PTR_ERR(pmic_battery_class); + goto err_out1; + } + + temp_class = device_create(pmic_battery_class, NULL, + MKDEV(pmic_battery_major, 0), + PMIC_BATTERY_STRING); + if (IS_ERR(temp_class)) { + printk(KERN_ERR "Error creating PMIC battery class device.\n"); + ret = PTR_ERR(temp_class); + goto err_out2; + } + + pmic_batt_led_control(true); + pmic_batt_set_5k_pull(true); + + printk(KERN_INFO "PMIC Battery successfully probed\n"); + + return ret; + + err_out2: + class_destroy(pmic_battery_class); + err_out1: + unregister_chrdev(pmic_battery_major, PMIC_BATTERY_STRING); + return ret; +} + +static struct platform_driver pmic_battery_driver_ldm = { + .driver = { + .name = "pmic_battery", + .bus = &platform_bus_type, + }, + .suspend = pmic_battery_suspend, + .resume = pmic_battery_resume, + .probe = pmic_battery_probe, + .remove = pmic_battery_remove, +}; + +/* + * Init and Exit + */ + +static int __init pmic_battery_init(void) +{ + pr_debug("PMIC Battery driver loading...\n"); + return platform_driver_register(&pmic_battery_driver_ldm); +} + +static void __exit pmic_battery_exit(void) +{ + platform_driver_unregister(&pmic_battery_driver_ldm); + pr_debug("PMIC Battery driver successfully unloaded\n"); +} + +/* + * Module entry points + */ + +module_init(pmic_battery_init); +module_exit(pmic_battery_exit); + +MODULE_DESCRIPTION("pmic_battery driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_battery_defs.h linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_battery_defs.h --- linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_battery_defs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_battery_defs.h 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,81 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_battery_defs.h + * @brief This is the internal header for PMIC(mc13783) Battery driver. + * + * @ingroup PMIC_BATTERY + */ + +#ifndef __PMIC_BATTERY_DEFS_H__ +#define __PMIC_BATTERY_DEFS_H__ + +#define PMIC_BATTERY_STRING "pmic_battery" + +/* REG_CHARGE */ +#define MC13783_BATT_DAC_V_DAC_LSH 0 +#define MC13783_BATT_DAC_V_DAC_WID 3 +#define MC13783_BATT_DAC_DAC_LSH 3 +#define MC13783_BATT_DAC_DAC_WID 4 +#define MC13783_BATT_DAC_TRCKLE_LSH 7 +#define MC13783_BATT_DAC_TRCKLE_WID 3 +#define MC13783_BATT_DAC_FETOVRD_EN_LSH 10 +#define MC13783_BATT_DAC_FETOVRD_EN_WID 1 +#define MC13783_BATT_DAC_FETCTRL_EN_LSH 11 +#define MC13783_BATT_DAC_FETCTRL_EN_WID 1 +#define MC13783_BATT_DAC_REVERSE_SUPPLY_LSH 13 +#define MC13783_BATT_DAC_REVERSE_SUPPLY_WID 1 +#define MC13783_BATT_DAC_OVCTRL_LSH 15 +#define MC13783_BATT_DAC_OVCTRL_WID 2 +#define MC13783_BATT_DAC_UNREGULATED_LSH 17 +#define MC13783_BATT_DAC_UNREGULATED_WID 1 +#define MC13783_BATT_DAC_LED_EN_LSH 18 +#define MC13783_BATT_DAC_LED_EN_WID 1 +#define MC13783_BATT_DAC_5K_LSH 19 +#define MC13783_BATT_DAC_5K_WID 1 + +#define BITS_OUT_VOLTAGE 0 +#define LONG_OUT_VOLTAGE 3 +#define BITS_CURRENT_MAIN 3 +#define LONG_CURRENT_MAIN 4 +#define BITS_CURRENT_TRICKLE 7 +#define LONG_CURRENT_TRICKLE 3 +#define BIT_FETOVRD 10 +#define BIT_FETCTRL 11 +#define BIT_RVRSMODE 13 +#define BITS_OVERVOLTAGE 15 +#define LONG_OVERVOLTAGE 2 +#define BIT_UNREGULATED 17 +#define BIT_CHRG_LED 18 +#define BIT_CHRGRAWPDEN 19 + +/* REG_POWXER_CONTROL_0 */ +#define MC13783_BATT_DAC_V_COIN_LSH 20 +#define MC13783_BATT_DAC_V_COIN_WID 3 +#define MC13783_BATT_DAC_COIN_CH_EN_LSH 23 +#define MC13783_BATT_DAC_COIN_CH_EN_WID 1 +#define MC13783_BATT_DAC_COIN_CH_EN_ENABLED 1 +#define MC13783_BATT_DAC_COIN_CH_EN_DISABLED 0 +#define MC13783_BATT_DAC_EOL_CMP_EN_LSH 18 +#define MC13783_BATT_DAC_EOL_CMP_EN_WID 1 +#define MC13783_BATT_DAC_EOL_CMP_EN_ENABLE 1 +#define MC13783_BATT_DAC_EOL_CMP_EN_DISABLE 0 +#define MC13783_BATT_DAC_EOL_SEL_LSH 16 +#define MC13783_BATT_DAC_EOL_SEL_WID 2 + +#define DEF_VALUE 0 + +#define BAT_THRESHOLD_MAX 3 + +#endif /* __PMIC_BATTERY_DEFS_H__ */ diff -urN linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_convity.c linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_convity.c --- linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_convity.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_convity.c 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,2482 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_convity.c + * @brief Implementation of the PMIC Connectivity driver APIs. + * + * The PMIC connectivity device driver and this API were developed to support + * the external connectivity capabilities of several power management ICs that + * are available from Freescale Semiconductor, Inc. + * + * The following operating modes, in terms of external connectivity, are + * supported: + * + * @verbatim + Operating Mode mc13783 + --------------- ------- + USB (incl. OTG) Yes + RS-232 Yes + CEA-936 Yes + + @endverbatim + * + * @ingroup PMIC_CONNECTIVITY + */ + +#include /* For tasklet interface. */ +#include /* For kernel module interface. */ +#include /* For spinlock interface. */ +#include /* For PMIC ADC driver interface. */ +#include +#include /* For PMIC Connectivity driver interface. */ + +/* + * mc13783 Connectivity API + */ +/* EXPORTED FUNCTIONS */ +EXPORT_SYMBOL(pmic_convity_open); +EXPORT_SYMBOL(pmic_convity_close); +EXPORT_SYMBOL(pmic_convity_set_mode); +EXPORT_SYMBOL(pmic_convity_get_mode); +EXPORT_SYMBOL(pmic_convity_reset); +EXPORT_SYMBOL(pmic_convity_set_callback); +EXPORT_SYMBOL(pmic_convity_clear_callback); +EXPORT_SYMBOL(pmic_convity_get_callback); +EXPORT_SYMBOL(pmic_convity_usb_set_speed); +EXPORT_SYMBOL(pmic_convity_usb_get_speed); +EXPORT_SYMBOL(pmic_convity_usb_set_power_source); +EXPORT_SYMBOL(pmic_convity_usb_get_power_source); +EXPORT_SYMBOL(pmic_convity_usb_set_xcvr); +EXPORT_SYMBOL(pmic_convity_usb_get_xcvr); +EXPORT_SYMBOL(pmic_convity_usb_otg_set_dlp_duration); +EXPORT_SYMBOL(pmic_convity_usb_otg_get_dlp_duration); +EXPORT_SYMBOL(pmic_convity_usb_otg_set_config); +EXPORT_SYMBOL(pmic_convity_usb_otg_clear_config); +EXPORT_SYMBOL(pmic_convity_usb_otg_get_config); +EXPORT_SYMBOL(pmic_convity_set_output); +EXPORT_SYMBOL(pmic_convity_rs232_set_config); +EXPORT_SYMBOL(pmic_convity_rs232_get_config); +EXPORT_SYMBOL(pmic_convity_cea936_exit_signal); + +/*! @def SET_BITS + * Set a register field to a given value. + */ + +#define SET_BITS(reg, field, value) (((value) << reg.field.offset) & \ + reg.field.mask) + +/*! @def GET_BITS + * Get the current value of a given register field. + */ +#define GET_BITS(reg, value) (((value) & reg.mask) >> \ + reg.offset) + +/*! + * @brief Define the possible states for a device handle. + * + * This enumeration is used to track the current state of each device handle. + */ +typedef enum { + HANDLE_FREE, /*!< Handle is available for use. */ + HANDLE_IN_USE /*!< Handle is currently in use. */ +} HANDLE_STATE; + +/* + * This structure is used to define a specific hardware register field. + * + * All hardware register fields are defined using an offset to the LSB + * and a mask. The offset is used to right shift a register value before + * applying the mask to actually obtain the value of the field. + */ +typedef struct { + const unsigned char offset; /* Offset of LSB of register field. */ + const unsigned int mask; /* Mask value used to isolate register field. */ +} REGFIELD; + +/*! + * @brief This structure is used to identify the fields in the USBCNTRL_REG_0 hardware register. + * + * This structure lists all of the fields within the USBCNTRL_REG_0 hardware + * register. + */ +typedef struct { + REGFIELD FSENB; /*!< USB Full Speed Enable */ + REGFIELD USB_SUSPEND; /*!< USB Suspend Mode Enable */ + REGFIELD USB_PU; /*!< USB Pullup Enable */ + REGFIELD UDP_PD; /*!< USB Data Plus Pulldown Enable */ + REGFIELD UDM_PD; /*!< USB 150K UDP Pullup Enable */ + REGFIELD DP150K_PU; /*!< USB Pullup/Pulldown Override Enable */ + REGFIELD VBUSPDENB; /*!< USB VBUS Pulldown NMOS Switch Enable */ + REGFIELD CURRENT_LIMIT; /*!< USB Regulator Current Limit Setting-3 bits */ + REGFIELD DLP_SRP; /*!< USB Data Line Pulsing Timer Enable */ + REGFIELD SE0_CONN; /*!< USB Pullup Connect When SE0 Detected */ + REGFIELD USBXCVREN; /*!< USB Transceiver Enabled When INTERFACE_MODE[2:0]=000 and RESETB=high */ + REGFIELD PULLOVR; /*!< 1K5 Pullup and UDP/UDM Pulldown Disable When UTXENB=Low */ + REGFIELD INTERFACE_MODE; /*!< Connectivity Interface Mode Select-3 Bits */ + REGFIELD DATSE0; /*!< USB Single or Differential Mode Select */ + REGFIELD BIDIR; /*!< USB Unidirectional/Bidirectional Transmission */ + REGFIELD USBCNTRL; /*!< USB Mode of Operation controlled By USBEN/SPI Pin */ + REGFIELD IDPD; /*!< USB UID Pulldown Enable */ + REGFIELD IDPULSE; /*!< USB Pulse to Gnd on UID Line Generated */ + REGFIELD IDPUCNTRL; /*!< USB UID Pin pulled high By 5ua Curr Source */ + REGFIELD DMPULSE; /*!< USB Positive pulse on the UDM Line Generated */ +} USBCNTRL_REG_0; + +/*! + * @brief This variable is used to access the USBCNTRL_REG_0 hardware register. + * + * This variable defines how to access all of the fields within the + * USBCNTRL_REG_0 hardware register. The initial values consist of the offset + * and mask values needed to access each of the register fields. + */ +static const USBCNTRL_REG_0 regUSB0 = { + {0, 0x000001}, /*!< FSENB */ + {1, 0x000002}, /*!< USB_SUSPEND */ + {2, 0x000004}, /*!< USB_PU */ + {3, 0x000008}, /*!< UDP_PD */ + {4, 0x000010}, /*!< UDM_PD */ + {5, 0x000020}, /*!< DP150K_PU */ + {6, 0x000040}, /*!< VBUSPDENB */ + {7, 0x000380}, /*!< CURRENT_LIMIT */ + {10, 0x000400}, /*!< DLP_SRP */ + {11, 0x000800}, /*!< SE0_CONN */ + {12, 0x001000}, /*!< USBXCVREN */ + {13, 0x002000}, /*!< PULLOVR */ + {14, 0x01c000}, /*!< INTERFACE_MODE */ + {17, 0x020000}, /*!< DATSE0 */ + {18, 0x040000}, /*!< BIDIR */ + {19, 0x080000}, /*!< USBCNTRL */ + {20, 0x100000}, /*!< IDPD */ + {21, 0x200000}, /*!< IDPULSE */ + {22, 0x400000}, /*!< IDPUCNTRL */ + {23, 0x800000} /*!< DMPULSE */ + +}; + +/*! + * @brief This structure is used to identify the fields in the USBCNTRL_REG_1 hardware register. + * + * This structure lists all of the fields within the USBCNTRL_REG_1 hardware + * register. + */ +typedef struct { + REGFIELD VUSBIN; /*!< Controls The Input Source For VUSB */ + REGFIELD VUSB; /*!< VUSB Output Voltage Select-High=3.3V Low=2.775V */ + REGFIELD VUSBEN; /*!< VUSB Output Enable- */ + REGFIELD VBUSEN; /*!< VBUS Output Enable- */ + REGFIELD RSPOL; /*!< Low=RS232 TX on UDM, RX on UDP + High= RS232 TX on UDP, RX on UDM */ + REGFIELD RSTRI; /*!< TX Forced To Tristate in RS232 Mode Only */ + REGFIELD ID100kPU; /*!< 100k UID Pullup Enabled */ +} USBCNTRL_REG_1; + +/*! + * @brief This variable is used to access the USBCNTRL_REG_1 hardware register. + * + * This variable defines how to access all of the fields within the + * USBCNTRL_REG_1 hardware register. The initial values consist of the offset + * and mask values needed to access each of the register fields. + */ +static const USBCNTRL_REG_1 regUSB1 = { + {0, 0x000003}, /*!< VUSBIN-2 Bits */ + {2, 0x000004}, /*!< VUSB */ + {3, 0x000008}, /*!< VUSBEN */ + /*{4, 0x000010} *//*!< Reserved */ + {5, 0x000020}, /*!< VBUSEN */ + {6, 0x000040}, /*!< RSPOL */ + {7, 0x000080}, /*!< RSTRI */ + {8, 0x000100} /*!< ID100kPU */ + /*!< 9-23 Unused */ +}; + +/*! Define a mask to access the entire hardware register. */ +static const unsigned int REG_FULLMASK = 0xffffff; + +/*! Define the mc13783 USBCNTRL_REG_0 register power on reset state. */ +static const unsigned int RESET_USBCNTRL_REG_0 = 0x080060; + +/*! Define the mc13783 USBCNTRL_REG_1 register power on reset state. */ +static const unsigned int RESET_USBCNTRL_REG_1 = 0x000006; + +static pmic_event_callback_t eventNotify; + +/*! + * @brief This structure is used to maintain the current device driver state. + * + * This structure maintains the current state of the connectivity driver. This + * includes both the PMIC hardware state as well as the device handle and + * callback states. + */ + +typedef struct { + PMIC_CONVITY_HANDLE handle; /*!< Device handle. */ + HANDLE_STATE handle_state; /*!< Device handle + state. */ + PMIC_CONVITY_MODE mode; /*!< Device mode. */ + PMIC_CONVITY_CALLBACK callback; /*!< Event callback function pointer. */ + PMIC_CONVITY_EVENTS eventMask; /*!< Event mask. */ + PMIC_CONVITY_USB_SPEED usbSpeed; /*!< USB connection + speed. */ + PMIC_CONVITY_USB_MODE usbMode; /*!< USB connection + mode. */ + PMIC_CONVITY_USB_POWER_IN usbPowerIn; /*!< USB transceiver + power source. */ + PMIC_CONVITY_USB_POWER_OUT usbPowerOut; /*!< USB transceiver + power output + level. */ + PMIC_CONVITY_USB_TRANSCEIVER_MODE usbXcvrMode; /*!< USB transceiver + mode. */ + unsigned int usbDlpDuration; /*!< USB Data Line + Pulsing duration. */ + PMIC_CONVITY_USB_OTG_CONFIG usbOtgCfg; /*!< USB OTG + configuration + options. */ + PMIC_CONVITY_RS232_INTERNAL rs232CfgInternal; /*!< RS-232 internal + connections. */ + PMIC_CONVITY_RS232_EXTERNAL rs232CfgExternal; /*!< RS-232 external + connections. */ +} pmic_convity_state_struct; + +/*! + * @brief This structure is used to maintain the current device driver state. + * + * This structure maintains the current state of the driver in USB mode. This + * includes both the PMIC hardware state as well as the device handle and + * callback states. + */ + +typedef struct { + PMIC_CONVITY_HANDLE handle; /*!< Device handle. */ + HANDLE_STATE handle_state; /*!< Device handle + state. */ + PMIC_CONVITY_MODE mode; /*!< Device mode. */ + PMIC_CONVITY_CALLBACK callback; /*!< Event callback function pointer. */ + PMIC_CONVITY_EVENTS eventMask; /*!< Event mask. */ + PMIC_CONVITY_USB_SPEED usbSpeed; /*!< USB connection + speed. */ + PMIC_CONVITY_USB_MODE usbMode; /*!< USB connection + mode. */ + PMIC_CONVITY_USB_POWER_IN usbPowerIn; /*!< USB transceiver + power source. */ + PMIC_CONVITY_USB_POWER_OUT usbPowerOut; /*!< USB transceiver + power output + level. */ + PMIC_CONVITY_USB_TRANSCEIVER_MODE usbXcvrMode; /*!< USB transceiver + mode. */ + unsigned int usbDlpDuration; /*!< USB Data Line + Pulsing duration. */ + PMIC_CONVITY_USB_OTG_CONFIG usbOtgCfg; /*!< USB OTG + configuration + options. */ +} pmic_convity_usb_state; + +/*! + * @brief This structure is used to maintain the current device driver state. + * + * This structure maintains the current state of the driver in RS_232 mode. This + * includes both the PMIC hardware state as well as the device handle and + * callback states. + */ + +typedef struct { + PMIC_CONVITY_HANDLE handle; /*!< Device handle. */ + HANDLE_STATE handle_state; /*!< Device handle + state. */ + PMIC_CONVITY_MODE mode; /*!< Device mode. */ + PMIC_CONVITY_CALLBACK callback; /*!< Event callback function pointer. */ + PMIC_CONVITY_EVENTS eventMask; /*!< Event mask. */ + PMIC_CONVITY_RS232_INTERNAL rs232CfgInternal; /*!< RS-232 internal + connections. */ + PMIC_CONVITY_RS232_EXTERNAL rs232CfgExternal; /*!< RS-232 external + connections. */ +} pmic_convity_rs232_state; + +/*! + * @brief This structure is used to maintain the current device driver state. + * + * This structure maintains the current state of the driver in cea-936 mode. This + * includes both the PMIC hardware state as well as the device handle and + * callback states. + */ + +typedef struct { + PMIC_CONVITY_HANDLE handle; /*!< Device handle. */ + HANDLE_STATE handle_state; /*!< Device handle + state. */ + PMIC_CONVITY_MODE mode; /*!< Device mode. */ + PMIC_CONVITY_CALLBACK callback; /*!< Event callback function pointer. */ + PMIC_CONVITY_EVENTS eventMask; /*!< Event mask. */ + +} pmic_convity_cea936_state; + +/*! + * @brief Identifies the hardware interrupt source. + * + * This enumeration identifies which of the possible hardware interrupt + * sources actually caused the current interrupt handler to be called. + */ +typedef enum { + CORE_EVENT_4V4 = 1, /*!< Detected USB 4.4 V event. */ + CORE_EVENT_2V0 = 2, /*!< Detected USB 2.0 V event. */ + CORE_EVENT_0V8 = 4, /*!< Detected USB 0.8 V event. */ + CORE_EVENT_ABDET = 8 /*!< Detected USB mini A-B connector event. */ +} PMIC_CORE_EVENT; + +/*! + * @brief This structure defines the reset/power on state for the Connectivity driver. + */ +static const pmic_convity_state_struct reset = { + 0, + HANDLE_FREE, + USB, + NULL, + 0, + USB_FULL_SPEED, + USB_PERIPHERAL, + USB_POWER_INTERNAL, + USB_POWER_3V3, + USB_TRANSCEIVER_OFF, + 0, + USB_PULL_OVERRIDE | USB_VBUS_CURRENT_LIMIT_HIGH, + RS232_TX_USE0VM_RX_UDATVP, + RS232_TX_UDM_RX_UDP +}; + +/*! + * @brief This structure maintains the current state of the Connectivity driver. + * + * The initial values must be identical to the reset state defined by the + * #reset variable. + */ +static pmic_convity_usb_state usb = { + 0, + HANDLE_FREE, + USB, + NULL, + 0, + USB_FULL_SPEED, + USB_PERIPHERAL, + USB_POWER_INTERNAL, + USB_POWER_3V3, + USB_TRANSCEIVER_OFF, + 0, + USB_PULL_OVERRIDE | USB_VBUS_CURRENT_LIMIT_HIGH, +}; + +/*! + * @brief This structure maintains the current state of the Connectivity driver. + * + * The initial values must be identical to the reset state defined by the + * #reset variable. + */ +static pmic_convity_rs232_state rs_232 = { + 0, + HANDLE_FREE, + RS232_1, + NULL, + 0, + RS232_TX_USE0VM_RX_UDATVP, + RS232_TX_UDM_RX_UDP +}; + +/*! + * @brief This structure maintains the current state of the Connectivity driver. + * + * The initial values must be identical to the reset state defined by the + * #reset variable. + */ +static pmic_convity_cea936_state cea_936 = { + 0, + HANDLE_FREE, + CEA936_MONO, + NULL, + 0, +}; + +/*! + * @brief This spinlock is used to provide mutual exclusion. + * + * Create a spinlock that can be used to provide mutually exclusive + * read/write access to the globally accessible "convity" data structure + * that was defined above. Mutually exclusive access is required to + * ensure that the convity data structure is consistent at all times + * when possibly accessed by multiple threads of execution (for example, + * while simultaneously handling a user request and an interrupt event). + * + * We need to use a spinlock sometimes because we need to provide mutual + * exclusion while handling a hardware interrupt. + */ +static spinlock_t lock = SPIN_LOCK_UNLOCKED; + +/*! + * @brief This mutex is used to provide mutual exclusion. + * + * Create a mutex that can be used to provide mutually exclusive + * read/write access to the globally accessible data structures + * that were defined above. Mutually exclusive access is required to + * ensure that the Connectivity data structures are consistent at all + * times when possibly accessed by multiple threads of execution. + * + * Note that we use a mutex instead of the spinlock whenever disabling + * interrupts while in the critical section is not required. This helps + * to minimize kernel interrupt handling latency. + */ +static DECLARE_MUTEX(mutex); + +/* Prototype for the connectivity driver tasklet function. */ +static void pmic_convity_tasklet(struct work_struct *work); + +/*! + * @brief Tasklet handler for the connectivity driver. + * + * Declare a tasklet that will do most of the processing for all of the + * connectivity-related interrupt events (USB4.4VI, USB2.0VI, USB0.8VI, + * and AB_DETI). Note that we cannot do all of the required processing + * within the interrupt handler itself because we may need to call the + * ADC driver to measure voltages as well as calling any user-registered + * callback functions. + */ +DECLARE_WORK(convityTasklet, pmic_convity_tasklet); + +/*! + * @brief Global variable to track currently active interrupt events. + * + * This global variable is used to keep track of all of the currently + * active interrupt events for the connectivity driver. Note that access + * to this variable may occur while within an interrupt context and, + * therefore, must be guarded by using a spinlock. + */ +static PMIC_CORE_EVENT eventID = 0; + +/* Prototypes for all static connectivity driver functions. */ +static PMIC_STATUS pmic_convity_set_mode_internal(const PMIC_CONVITY_MODE mode); +static PMIC_STATUS pmic_convity_deregister_all(void); +static void pmic_convity_event_handler(void *param); + +/************************************************************************** + * General setup and configuration functions. + ************************************************************************** + */ + +/*! + * @name General Setup and Configuration Connectivity APIs + * Functions for setting up and configuring the connectivity hardware. + */ +/*@{*/ + +/*! + * Attempt to open and gain exclusive access to the PMIC connectivity + * hardware. An initial operating mode must also be specified. + * + * If the open request is successful, then a numeric handle is returned + * and this handle must be used in all subsequent function calls. The + * same handle must also be used in the pmic_convity_close() call when use + * of the PMIC connectivity hardware is no longer required. + * + * @param handle device handle from open() call + * @param mode initial connectivity operating mode + * + * @return PMIC_SUCCESS if the open request was successful + */ +PMIC_STATUS pmic_convity_open(PMIC_CONVITY_HANDLE * const handle, + const PMIC_CONVITY_MODE mode) +{ + PMIC_STATUS rc = PMIC_ERROR; + + if (handle == (PMIC_CONVITY_HANDLE *) NULL) { + /* Do not dereference a NULL pointer. */ + return PMIC_ERROR; + } + + /* We only need to acquire a mutex here because the interrupt handler + * never modifies the device handle or device handle state. Therefore, + * we don't need to worry about conflicts with the interrupt handler + * or the need to execute in an interrupt context. + * + * But we do need a critical section here to avoid problems in case + * multiple calls to pmic_convity_open() are made since we can only + * allow one of them to succeed. + */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + /* Check the current device handle state and acquire the handle if + * it is available. + */ + if ((usb.handle_state != HANDLE_FREE) + && (rs_232.handle_state != HANDLE_FREE) + && (cea_936.handle_state != HANDLE_FREE)) { + + /* Cannot open the PMIC connectivity hardware at this time or an invalid + * mode was requested. + */ + *handle = reset.handle; + } else { + + if (mode == USB) { + usb.handle = (PMIC_CONVITY_HANDLE) (&usb); + usb.handle_state = HANDLE_IN_USE; + } else if ((mode == RS232_1) || (mode == RS232_2)) { + rs_232.handle = (PMIC_CONVITY_HANDLE) (&rs_232); + rs_232.handle_state = HANDLE_IN_USE; + } else if ((mode == CEA936_STEREO) || (mode == CEA936_MONO) + || (mode == CEA936_TEST_LEFT) + || (mode == CEA936_TEST_RIGHT)) { + cea_936.handle = (PMIC_CONVITY_HANDLE) (&cea_936); + cea_936.handle_state = HANDLE_IN_USE; + + } + /* Let's begin by acquiring the connectivity device handle. */ + /* Then we can try to set the desired operating mode. */ + rc = pmic_convity_set_mode_internal(mode); + + if (rc == PMIC_SUCCESS) { + /* Successfully set the desired operating mode, now return the + * handle to the caller. + */ + if (mode == USB) { + *handle = usb.handle; + } else if ((mode == RS232_1) || (mode == RS232_2)) { + *handle = rs_232.handle; + } else if ((mode == CEA936_STEREO) + || (mode == CEA936_MONO) + || (mode == CEA936_TEST_LEFT) + || (mode == CEA936_TEST_RIGHT)) { + *handle = cea_936.handle; + } + } else { + /* Failed to set the desired mode, return the handle to an unused + * state. + */ + if (mode == USB) { + usb.handle = reset.handle; + usb.handle_state = reset.handle_state; + } else if ((mode == RS232_1) || (mode == RS232_2)) { + rs_232.handle = reset.handle; + rs_232.handle_state = reset.handle_state; + } else if ((mode == CEA936_STEREO) + || (mode == CEA936_MONO) + || (mode == CEA936_TEST_LEFT) + || (mode == CEA936_TEST_RIGHT)) { + cea_936.handle = reset.handle; + cea_936.handle_state = reset.handle_state; + } + + *handle = reset.handle; + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Terminate further access to the PMIC connectivity hardware. Also allows + * another process to call pmic_convity_open() to gain access. + * + * @param handle device handle from open() call + * + * @return PMIC_SUCCESS if the close request was successful + */ +PMIC_STATUS pmic_convity_close(const PMIC_CONVITY_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Begin a critical section here to avoid the possibility of race + * conditions if multiple threads happen to call this function and + * pmic_convity_open() at the same time. + */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + /* Confirm that the device handle matches the one assigned in the + * pmic_convity_open() call and then close the connection. + */ + if (((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE)) || ((handle == rs_232.handle) + && (rs_232.handle_state == + HANDLE_IN_USE)) + || ((handle == cea_936.handle) + && (cea_936.handle_state == HANDLE_IN_USE))) { + rc = PMIC_SUCCESS; + + /* Deregister for all existing callbacks if necessary and make sure + * that the event handling settings are consistent following the + * close operation. + */ + if ((usb.callback != reset.callback) + || (rs_232.callback != reset.callback) + || (cea_936.callback != reset.callback)) { + /* Deregister the existing callback function and all registered + * events before we completely close the handle. + */ + rc = pmic_convity_deregister_all(); + if (rc == PMIC_SUCCESS) { + + } else if (usb.eventMask != reset.eventMask) { + /* Having a non-zero eventMask without a callback function being + * defined should never occur but let's just make sure here that + * we keep things consistent. + */ + usb.eventMask = reset.eventMask; + /* Mark the connectivity device handle as being closed. */ + usb.handle = reset.handle; + usb.handle_state = reset.handle_state; + + } else if (rs_232.eventMask != reset.eventMask) { + + rs_232.eventMask = reset.eventMask; + /* Mark the connectivity device handle as being closed. */ + rs_232.handle = reset.handle; + rs_232.handle_state = reset.handle_state; + + } else if (cea_936.eventMask != reset.eventMask) { + cea_936.eventMask = reset.eventMask; + /* Mark the connectivity device handle as being closed. */ + cea_936.handle = reset.handle; + cea_936.handle_state = reset.handle_state; + + } + + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Change the current operating mode of the PMIC connectivity hardware. + * The available connectivity operating modes is hardware dependent and + * consists of one or more of the following: USB (including USB On-the-Go), + * RS-232, and CEA-936. Requesting an operating mode that is not supported + * by the PMIC hardware will return PMIC_NOT_SUPPORTED. + * + * @param handle device handle from + open() call + * @param mode desired operating mode + * + * @return PMIC_SUCCESS if the requested mode was successfully set + */ +PMIC_STATUS pmic_convity_set_mode(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_MODE mode) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if (((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE)) || ((handle == rs_232.handle) + && (rs_232.handle_state == + HANDLE_IN_USE)) + || ((handle == cea_936.handle) + && (cea_936.handle_state == HANDLE_IN_USE))) { + rc = pmic_convity_set_mode_internal(mode); + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Get the current operating mode for the PMIC connectivity hardware. + * + * @param handle device handle from open() call + * @param mode the current PMIC connectivity operating mode + * + * @return PMIC_SUCCESS if the requested mode was successfully set + */ +PMIC_STATUS pmic_convity_get_mode(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_MODE * const mode) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE)) || ((handle == rs_232.handle) + && (rs_232. + handle_state == + HANDLE_IN_USE)) + || ((handle == cea_936.handle) + && (cea_936.handle_state == HANDLE_IN_USE))) + && (mode != (PMIC_CONVITY_MODE *) NULL)) { + + *mode = usb.mode; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Restore all registers to the initial power-on/reset state. + * + * @param handle device handle from open() call + * + * @return PMIC_SUCCESS if the reset was successful + */ +PMIC_STATUS pmic_convity_reset(const PMIC_CONVITY_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + if (((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE)) || ((handle == rs_232.handle) + && (rs_232.handle_state == + HANDLE_IN_USE)) + || ((handle == cea_936.handle) + && (cea_936.handle_state == HANDLE_IN_USE))) { + + /* Reset the PMIC Connectivity register to it's power on state. */ + rc = pmic_write_reg(REG_USB, RESET_USBCNTRL_REG_0, + REG_FULLMASK); + + rc = pmic_write_reg(REG_CHARGE_USB_SPARE, + RESET_USBCNTRL_REG_1, REG_FULLMASK); + + if (rc == PMIC_SUCCESS) { + /* Also reset the device driver state data structure. */ + + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Register a callback function that will be used to signal PMIC connectivity + * events. For example, the USB subsystem should register a callback function + * in order to be notified of device connect/disconnect events. Note, however, + * that non-USB events may also be signalled depending upon the PMIC hardware + * capabilities. Therefore, the callback function must be able to properly + * handle all of the possible events if support for non-USB peripherals is + * also to be included. + * + * @param handle device handle from open() call + * @param func a pointer to the callback function + * @param eventMask a mask selecting events to be notified + * + * @return PMIC_SUCCESS if the callback was successful registered + */ +PMIC_STATUS pmic_convity_set_callback(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_CALLBACK func, + const PMIC_CONVITY_EVENTS eventMask) +{ + unsigned long flags; + PMIC_STATUS rc = PMIC_ERROR; + + /* We need to start a critical section here to ensure a consistent state + * in case simultaneous calls to pmic_convity_set_callback() are made. In + * that case, we must serialize the calls to ensure that the "callback" + * and "eventMask" state variables are always consistent. + * + * Note that we don't actually need to acquire the spinlock until later + * when we are finally ready to update the "callback" and "eventMask" + * state variables which are shared with the interrupt handler. + */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && (usb.handle_state == HANDLE_IN_USE)) { + + /* Return an error if either the callback function or event mask + * is not properly defined. + * + * It is also considered an error if a callback function has already + * been defined. If you wish to register for a new set of events, + * then you must first call pmic_convity_clear_callback() to + * deregister the existing callback function and list of events + * before trying to register a new callback function. + */ + if ((func == NULL) || (eventMask == 0) + || (usb.callback != NULL)) { + rc = PMIC_ERROR; + + /* Register for PMIC events from the core protocol driver. */ + } else { + + if ((eventMask & USB_DETECT_4V4_RISE) || + (eventMask & USB_DETECT_4V4_FALL)) { + /* We need to register for the 4.4V interrupt. */ + //EVENT_USBI or EVENT_USB_44VI + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_4V4); + rc = pmic_event_subscribe(EVENT_USBI, + eventNotify); + + if (rc != PMIC_SUCCESS) { + return rc; + } + } + + if ((eventMask & USB_DETECT_2V0_RISE) || + (eventMask & USB_DETECT_2V0_FALL)) { + /* We need to register for the 2.0V interrupt. */ + //EVENT_USB_20VI or EVENT_USBI + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_2V0); + rc = pmic_event_subscribe(EVENT_USBI, + eventNotify); + + if (rc != PMIC_SUCCESS) { + goto Cleanup_4V4; + } + } + + if ((eventMask & USB_DETECT_0V8_RISE) || + (eventMask & USB_DETECT_0V8_FALL)) { + /* We need to register for the 0.8V interrupt. */ + //EVENT_USB_08VI or EVENT_USBI + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_0V8); + rc = pmic_event_subscribe(EVENT_USBI, + eventNotify); + + if (rc != PMIC_SUCCESS) { + goto Cleanup_2V0; + } + } + + if ((eventMask & USB_DETECT_MINI_A) || + (eventMask & USB_DETECT_MINI_B) + || (eventMask & USB_DETECT_NON_USB_ACCESSORY) + || (eventMask & USB_DETECT_FACTORY_MODE)) { + /* We need to register for the AB_DET interrupt. */ + //EVENT_AB_DETI or EVENT_IDI + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_ABDET); + rc = pmic_event_subscribe(EVENT_IDI, + eventNotify); + + if (rc != PMIC_SUCCESS) { + goto Cleanup_0V8; + } + } + + /* Use a critical section to maintain a consistent state. */ + spin_lock_irqsave(&lock, flags); + + /* Successfully registered for all events. */ + usb.callback = func; + usb.eventMask = eventMask; + spin_unlock_irqrestore(&lock, flags); + + goto End; + + /* This section unregisters any already registered events if we should + * encounter an error partway through the registration process. Note + * that we don't check the return status here since it is already set + * to PMIC_ERROR before we get here. + */ + Cleanup_0V8: + + if ((eventMask & USB_DETECT_0V8_RISE) || + (eventMask & USB_DETECT_0V8_FALL)) { + //EVENT_USB_08VI or EVENT_USBI + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_0V8); + pmic_event_unsubscribe(EVENT_USBI, eventNotify); + goto End; + } + + Cleanup_2V0: + + if ((eventMask & USB_DETECT_2V0_RISE) || + (eventMask & USB_DETECT_2V0_FALL)) { + //EVENT_USB_20VI or EVENT_USBI + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_2V0); + pmic_event_unsubscribe(EVENT_USBI, eventNotify); + goto End; + } + + Cleanup_4V4: + + if ((eventMask & USB_DETECT_4V4_RISE) || + (eventMask & USB_DETECT_4V4_FALL)) { + //EVENT_USB_44VI or EVENT_USBI + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_4V4); + pmic_event_unsubscribe(EVENT_USBI, eventNotify); + } + } + /* Exit the critical section. */ + + } + End:up(&mutex); + return rc; + +} + +/*! + * Clears the current callback function. If this function returns successfully + * then all future Connectivity events will only be handled by the default + * handler within the Connectivity driver. + * + * @param handle device handle from open() call + * + * @return PMIC_SUCCESS if the callback was successful cleared + */ +PMIC_STATUS pmic_convity_clear_callback(const PMIC_CONVITY_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + if (((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE)) || ((handle == rs_232.handle) + && (rs_232.handle_state == + HANDLE_IN_USE)) + || ((handle == cea_936.handle) + && (cea_936.handle_state == HANDLE_IN_USE))) { + + rc = pmic_convity_deregister_all(); + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Get the current callback function and event mask. + * + * @param handle device handle from open() call + * @param func the current callback function + * @param eventMask the current event selection mask + * + * @return PMIC_SUCCESS if the callback information was successful + * retrieved + */ +PMIC_STATUS pmic_convity_get_callback(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_CALLBACK * const func, + PMIC_CONVITY_EVENTS * const eventMask) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + if ((((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE)) || ((handle == rs_232.handle) + && (rs_232. + handle_state == + HANDLE_IN_USE)) + || ((handle == cea_936.handle) + && (cea_936.handle_state == HANDLE_IN_USE))) + && (func != (PMIC_CONVITY_CALLBACK *) NULL) + && (eventMask != (PMIC_CONVITY_EVENTS *) NULL)) { + *func = usb.callback; + *eventMask = usb.eventMask; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + + up(&mutex); + + return rc; +} + +/*@*/ + +/************************************************************************** + * USB-specific configuration and setup functions. + ************************************************************************** + */ + +/*! + * @name USB and USB-OTG Connectivity APIs + * Functions for controlling USB and USB-OTG connectivity. + */ +/*@{*/ + +/*! + * Set the USB transceiver speed. + * + * @param handle device handle from open() call + * @param speed the desired USB transceiver speed + * + * @return PMIC_SUCCESS if the transceiver speed was successfully set + */ +PMIC_STATUS pmic_convity_usb_set_speed(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_SPEED speed) +{ + PMIC_STATUS rc = PMIC_ERROR; + unsigned int reg_value = 0; + unsigned int reg_mask = SET_BITS(regUSB0, FSENB, 1); + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if (handle == (rs_232.handle || cea_936.handle)) { + return PMIC_PARAMETER_ERROR; + } else { + if ((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE)) { + /* Validate the function parameters and if they are valid, then + * configure the pull-up and pull-down resistors as required for + * the desired operating mode. + */ + if ((speed == USB_HIGH_SPEED)) { + /* + * The USB transceiver also does not support the high speed mode + * (which is also optional under the USB OTG specification). + */ + rc = PMIC_NOT_SUPPORTED; + } else if ((speed != USB_LOW_SPEED) + && (speed != USB_FULL_SPEED)) { + /* Final validity check on the speed parameter. */ + rc = PMIC_ERROR;; + } else { + /* First configure the D+ and D- pull-up/pull-down resistors as + * per the USB OTG specification. + */ + if (speed == USB_FULL_SPEED) { + /* Activate pull-up on D+ and pull-down on D-. */ + reg_value = + SET_BITS(regUSB0, UDM_PD, 1); + } else if (speed == USB_LOW_SPEED) { + /* Activate pull-up on D+ and pull-down on D-. */ + reg_value = SET_BITS(regUSB0, FSENB, 1); + } + + /* Now set the desired USB transceiver speed. Note that + * USB_FULL_SPEED simply requires FSENB=0 (which it + * already is). + */ + + rc = pmic_write_reg(REG_USB, reg_value, + reg_mask); + + if (rc == PMIC_SUCCESS) { + usb.usbSpeed = speed; + } + } + } + } + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Get the USB transceiver speed. + * + * @param handle device handle from open() call + * @param speed the current USB transceiver speed + * @param mode the current USB transceiver mode + * + * @return PMIC_SUCCESS if the transceiver speed was successfully + * obtained + */ +PMIC_STATUS pmic_convity_usb_get_speed(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_USB_SPEED * const speed, + PMIC_CONVITY_USB_MODE * const mode) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE) && + (speed != (PMIC_CONVITY_USB_SPEED *) NULL) && + (mode != (PMIC_CONVITY_USB_MODE *) NULL)) { + *speed = usb.usbSpeed; + *mode = usb.usbMode; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * This function enables/disables VUSB and VBUS output. + * This API configures the VUSBEN and VBUSEN bits of USB register + * + * @param handle device handle from open() call + * @param out_type true, for VBUS + * false, for VUSB + * @param out if true, output is enabled + * if false, output is disabled + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_convity_set_output(const PMIC_CONVITY_HANDLE handle, + bool out_type, bool out) +{ + + PMIC_STATUS rc = PMIC_ERROR; + unsigned int reg_value = 0; + + unsigned int reg_mask = 0; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && (usb.handle_state == HANDLE_IN_USE)) { + + if ((out_type == 0) && (out == 1)) { + + reg_value = SET_BITS(regUSB1, VUSBEN, 1); + reg_mask = SET_BITS(regUSB1, VUSBEN, 1); + + rc = pmic_write_reg(REG_CHARGE_USB_SPARE, + reg_value, reg_mask); + } else if (out_type == 0 && out == 0) { + reg_mask = SET_BITS(regUSB1, VBUSEN, 1); + + rc = pmic_write_reg(REG_CHARGE_USB_SPARE, + reg_value, reg_mask); + } else if (out_type == 1 && out == 1) { + + reg_value = SET_BITS(regUSB1, VBUSEN, 1); + reg_mask = SET_BITS(regUSB1, VBUSEN, 1); + + rc = pmic_write_reg(REG_CHARGE_USB_SPARE, + reg_value, reg_mask); + } + + else if (out_type == 1 && out == 0) { + + reg_mask = SET_BITS(regUSB1, VBUSEN, 1); + rc = pmic_write_reg(REG_CHARGE_USB_SPARE, + reg_value, reg_mask); + } + + /*else { + + rc = pmic_write_reg(REG_CHARGE_USB_SPARE, + reg_value, reg_mask); + } */ + } + + up(&mutex); + + return rc; +} + +/*! + * Set the USB transceiver's power supply configuration. + * + * @param handle device handle from open() call + * @param pwrin USB transceiver regulator input power source + * @param pwrout USB transceiver regulator output power level + * + * @return PMIC_SUCCESS if the USB transceiver's power supply + * configuration was successfully set + */ +PMIC_STATUS pmic_convity_usb_set_power_source(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_POWER_IN + pwrin, + const PMIC_CONVITY_USB_POWER_OUT + pwrout) +{ + PMIC_STATUS rc = PMIC_ERROR; + unsigned int reg_value = 0; + unsigned int reg_mask = 0; + /* SET_BITS(regUSB1, VUSBEN, 1) | SET_BITS(regUSB1, VBUSEN, + 1) | SET_BITS(regUSB1, + VUSBIN, + 2) | */ + // SET_BITS(regUSB1, VUSB, 1); +/* SET_BITS(regUSB1, VUSBIN, 1) | SET_BITS(regUSB1, VUSBEN, + 1) | SET_BITS(regUSB1, + VBUSEN, 1);*/ + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && (usb.handle_state == HANDLE_IN_USE)) { + + if (pwrin == USB_POWER_INTERNAL_BOOST) { + reg_value |= SET_BITS(regUSB1, VUSBIN, 0); + reg_mask = SET_BITS(regUSB1, VUSBIN, 1); + } else if (pwrin == USB_POWER_VBUS) { + reg_value |= SET_BITS(regUSB1, VUSBIN, 1); + reg_mask = SET_BITS(regUSB1, VUSBIN, 1); + } + + else if (pwrin == USB_POWER_INTERNAL) { + reg_value |= SET_BITS(regUSB1, VUSBIN, 2); + reg_mask = SET_BITS(regUSB1, VUSBIN, 1); + } + + if (pwrout == USB_POWER_3V3) { + reg_value |= SET_BITS(regUSB1, VUSB, 1); + reg_mask |= SET_BITS(regUSB1, VUSB, 1); + } + + else if (pwrout == USB_POWER_2V775) { + reg_value |= SET_BITS(regUSB1, VUSB, 0); + reg_mask |= SET_BITS(regUSB1, VUSB, 1); + } + rc = pmic_write_reg(REG_CHARGE_USB_SPARE, reg_value, reg_mask); + + if (rc == PMIC_SUCCESS) { + usb.usbPowerIn = pwrin; + usb.usbPowerOut = pwrout; + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Get the USB transceiver's current power supply configuration. + * + * @param handle device handle from open() call + * @param pwrin USB transceiver regulator input power source + * @param pwrout USB transceiver regulator output power level + * + * @return PMIC_SUCCESS if the USB transceiver's power supply + * configuration was successfully retrieved + */ +PMIC_STATUS pmic_convity_usb_get_power_source(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_USB_POWER_IN * + const pwrin, + PMIC_CONVITY_USB_POWER_OUT * + const pwrout) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE) && + (pwrin != (PMIC_CONVITY_USB_POWER_IN *) NULL) && + (pwrout != (PMIC_CONVITY_USB_POWER_OUT *) NULL)) { + *pwrin = usb.usbPowerIn; + *pwrout = usb.usbPowerOut; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Set the USB transceiver's operating mode. + * + * @param handle device handle from open() call + * @param mode desired operating mode + * + * @return PMIC_SUCCESS if the USB transceiver's operating mode + * was successfully configured + */ +PMIC_STATUS pmic_convity_usb_set_xcvr(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_TRANSCEIVER_MODE + mode) +{ + PMIC_STATUS rc = PMIC_ERROR; + unsigned int reg_value = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && (usb.handle_state == HANDLE_IN_USE)) { + + if (mode == USB_TRANSCEIVER_OFF) { + reg_value = SET_BITS(regUSB0, USBXCVREN, 0); + reg_mask |= SET_BITS(regUSB0, USB_SUSPEND, 1); + + rc = pmic_write_reg(REG_USB, reg_value, reg_mask); + + } + + if (mode == USB_SINGLE_ENDED_UNIDIR) { + reg_value |= + SET_BITS(regUSB0, DATSE0, 1) | SET_BITS(regUSB0, + BIDIR, 0); + reg_mask |= + SET_BITS(regUSB0, USB_SUSPEND, + 1) | SET_BITS(regUSB0, DATSE0, + 1) | SET_BITS(regUSB0, BIDIR, + 1); + } else if (mode == USB_SINGLE_ENDED_BIDIR) { + reg_value |= + SET_BITS(regUSB0, DATSE0, 1) | SET_BITS(regUSB0, + BIDIR, 1); + reg_mask |= + SET_BITS(regUSB0, USB_SUSPEND, + 1) | SET_BITS(regUSB0, DATSE0, + 1) | SET_BITS(regUSB0, BIDIR, + 1); + } else if (mode == USB_DIFFERENTIAL_UNIDIR) { + reg_value |= + SET_BITS(regUSB0, DATSE0, 0) | SET_BITS(regUSB0, + BIDIR, 0); + reg_mask |= + SET_BITS(regUSB0, USB_SUSPEND, + 1) | SET_BITS(regUSB0, DATSE0, + 1) | SET_BITS(regUSB0, BIDIR, + 1); + } else if (mode == USB_DIFFERENTIAL_BIDIR) { + reg_value |= + SET_BITS(regUSB0, DATSE0, 0) | SET_BITS(regUSB0, + BIDIR, 1); + reg_mask |= + SET_BITS(regUSB0, USB_SUSPEND, + 1) | SET_BITS(regUSB0, DATSE0, + 1) | SET_BITS(regUSB0, BIDIR, + 1); + } + + if (mode == USB_SUSPEND_ON) { + reg_value |= SET_BITS(regUSB0, USB_SUSPEND, 1); + reg_mask |= SET_BITS(regUSB0, USB_SUSPEND, 1); + } else if (mode == USB_SUSPEND_OFF) { + reg_value |= SET_BITS(regUSB0, USB_SUSPEND, 0); + reg_mask |= SET_BITS(regUSB0, USB_SUSPEND, 1); + } + + if (mode == USB_OTG_SRP_DLP_START) { + reg_value |= SET_BITS(regUSB0, USB_PU, 0); + reg_mask |= SET_BITS(regUSB0, USB_SUSPEND, 1); + } else if (mode == USB_OTG_SRP_DLP_STOP) { + reg_value &= SET_BITS(regUSB0, USB_PU, 1); + reg_mask |= SET_BITS(regUSB0, USB_PU, 1); + } + + rc = pmic_write_reg(REG_USB, reg_value, reg_mask); + + if (rc == PMIC_SUCCESS) { + usb.usbXcvrMode = mode; + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Get the USB transceiver's current operating mode. + * + * @param handle device handle from open() call + * @param mode current operating mode + * + * @return PMIC_SUCCESS if the USB transceiver's operating mode + * was successfully retrieved + */ +PMIC_STATUS pmic_convity_usb_get_xcvr(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_USB_TRANSCEIVER_MODE * + const mode) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE) && + (mode != (PMIC_CONVITY_USB_TRANSCEIVER_MODE *) NULL)) { + *mode = usb.usbXcvrMode; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Set the Data Line Pulse duration (in milliseconds) for the USB OTG + * Session Request Protocol. + * + * For mc13783, this feature is not supported.So return PMIC_NOT_SUPPORTED + * + * @param handle device handle from open() call + * @param duration the data line pulse duration (ms) + * + * @return PMIC_SUCCESS if the pulse duration was successfully set + */ +PMIC_STATUS pmic_convity_usb_otg_set_dlp_duration(const PMIC_CONVITY_HANDLE + handle, + const unsigned int duration) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + + /* The setting of the dlp duration is not supported by the mc13783 PMIC hardware. */ + + /* No critical section is required. */ + + if ((handle != usb.handle) + || (usb.handle_state != HANDLE_IN_USE)) { + /* Must return error indication for invalid handle parameter to be + * consistent with other APIs. + */ + rc = PMIC_ERROR; + } + + return rc; +} + +/*! + * Get the current Data Line Pulse duration (in milliseconds) for the USB + * OTG Session Request Protocol. + * + * @param handle device handle from open() call + * @param duration the data line pulse duration (ms) + * + * @return PMIC_SUCCESS if the pulse duration was successfully obtained + */ +PMIC_STATUS pmic_convity_usb_otg_get_dlp_duration(const PMIC_CONVITY_HANDLE + handle, + unsigned int *const duration) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + + /* The setting of dlp duration is not supported by the mc13783 PMIC hardware. */ + + /* No critical section is required. */ + + if ((handle != usb.handle) + || (usb.handle_state != HANDLE_IN_USE)) { + /* Must return error indication for invalid handle parameter to be + * consistent with other APIs. + */ + rc = PMIC_ERROR; + } + + return rc; +} + +/*! + * Set the USB On-The-Go (OTG) configuration. + * + * @param handle device handle from open() call + * @param cfg desired USB OTG configuration + * + * @return PMIC_SUCCESS if the OTG configuration was successfully set + */ +PMIC_STATUS pmic_convity_usb_otg_set_config(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_OTG_CONFIG + cfg) +{ + PMIC_STATUS rc = PMIC_ERROR; + unsigned int reg_value = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && (usb.handle_state == HANDLE_IN_USE)) { + if (cfg & USB_OTG_SE0CONN) { + reg_value = SET_BITS(regUSB0, SE0_CONN, 1); + reg_mask = SET_BITS(regUSB0, SE0_CONN, 1); + } + if (cfg & USBXCVREN) { + reg_value |= SET_BITS(regUSB0, USBXCVREN, 1); + reg_mask |= SET_BITS(regUSB0, USBXCVREN, 1); + } + + if (cfg & USB_OTG_DLP_SRP) { + reg_value |= SET_BITS(regUSB0, DLP_SRP, 1); + reg_mask |= SET_BITS(regUSB0, DLP_SRP, 1); + } + + if (cfg & USB_PULL_OVERRIDE) { + reg_value |= SET_BITS(regUSB0, PULLOVR, 1); + reg_mask |= SET_BITS(regUSB0, PULLOVR, 1); + } + + if (cfg & USB_PU) { + reg_value |= SET_BITS(regUSB0, USB_PU, 1); + reg_mask |= SET_BITS(regUSB0, USB_PU, 1); + } + + if (cfg & USB_UDM_PD) { + reg_value |= SET_BITS(regUSB0, UDM_PD, 1); + reg_mask |= SET_BITS(regUSB0, UDM_PD, 1); + } + + if (cfg & USB_UDP_PD) { + reg_value |= SET_BITS(regUSB0, UDP_PD, 1); + reg_mask |= SET_BITS(regUSB0, UDP_PD, 1); + } + + if (cfg & USB_DP150K_PU) { + reg_value |= SET_BITS(regUSB0, DP150K_PU, 1); + reg_mask |= SET_BITS(regUSB0, DP150K_PU, 1); + } + + if (cfg & USB_USBCNTRL) { + reg_value |= SET_BITS(regUSB0, USBCNTRL, 1); + reg_mask |= SET_BITS(regUSB0, USBCNTRL, 1); + } + + if (cfg & USB_VBUS_CURRENT_LIMIT_HIGH) { + reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 0); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_10MS) { + reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 1); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_20MS) { + reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 2); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_30MS) { + reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 3); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_40MS) { + reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 4); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_50MS) { + reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 5); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_60MS) { + reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 6); + } + if (cfg & USB_VBUS_CURRENT_LIMIT_LOW) { + reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 7); + reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 7); + } + + if (cfg & USB_VBUS_PULLDOWN) { + reg_value |= SET_BITS(regUSB0, VBUSPDENB, 1); + reg_mask |= SET_BITS(regUSB0, VBUSPDENB, 1); + } + + rc = pmic_write_reg(REG_USB, reg_value, reg_mask); + + if (rc == PMIC_SUCCESS) { + if ((cfg & USB_VBUS_CURRENT_LIMIT_HIGH) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_10MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_20MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_30MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_40MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_50MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_60MS)) { + /* Make sure that the VBUS current limit state is + * correctly set to either USB_VBUS_CURRENT_LIMIT_HIGH + * or USB_VBUS_CURRENT_LIMIT_LOW but never both at the + * same time. + * + * We guarantee this by first clearing both of the + * status bits and then resetting the correct one. + */ + usb.usbOtgCfg &= + ~(USB_VBUS_CURRENT_LIMIT_HIGH | + USB_VBUS_CURRENT_LIMIT_LOW | + USB_VBUS_CURRENT_LIMIT_LOW_10MS | + USB_VBUS_CURRENT_LIMIT_LOW_20MS | + USB_VBUS_CURRENT_LIMIT_LOW_30MS | + USB_VBUS_CURRENT_LIMIT_LOW_40MS | + USB_VBUS_CURRENT_LIMIT_LOW_50MS | + USB_VBUS_CURRENT_LIMIT_LOW_60MS); + } + + usb.usbOtgCfg |= cfg; + } + } + //} + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Clears the USB On-The-Go (OTG) configuration. Multiple configuration settings + * may be OR'd together in a single call. However, selecting conflicting + * settings (e.g., multiple VBUS current limits) will result in undefined + * behavior. + * + * @param handle Device handle from open() call. + * @param cfg USB OTG configuration settings to be cleared. + * + * @retval PMIC_SUCCESS If the OTG configuration was successfully + * cleared. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If the desired USB OTG configuration is + * not supported by the PMIC hardware. + */ +PMIC_STATUS pmic_convity_usb_otg_clear_config(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_OTG_CONFIG + cfg) +{ + PMIC_STATUS rc = PMIC_ERROR; + unsigned int reg_value = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && (usb.handle_state == HANDLE_IN_USE)) { + /* if ((cfg & USB_VBUS_CURRENT_LIMIT_LOW_10MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_20MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_30MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_40MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_50MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_60MS)) + { + rc = PMIC_NOT_SUPPORTED; + } */ + //else + + if (cfg & USB_OTG_SE0CONN) { + reg_mask = SET_BITS(regUSB0, SE0_CONN, 1); + } + + if (cfg & USB_OTG_DLP_SRP) { + reg_mask |= SET_BITS(regUSB0, DLP_SRP, 1); + } + + if (cfg & USB_DP150K_PU) { + reg_mask |= SET_BITS(regUSB0, DP150K_PU, 1); + } + + if (cfg & USB_PULL_OVERRIDE) { + reg_mask |= SET_BITS(regUSB0, PULLOVR, 1); + } + + if (cfg & USB_PU) { + + reg_mask |= SET_BITS(regUSB0, USB_PU, 1); + } + + if (cfg & USB_UDM_PD) { + + reg_mask |= SET_BITS(regUSB0, UDM_PD, 1); + } + + if (cfg & USB_UDP_PD) { + + reg_mask |= SET_BITS(regUSB0, UDP_PD, 1); + } + + if (cfg & USB_USBCNTRL) { + reg_mask |= SET_BITS(regUSB0, USBCNTRL, 1); + } + + if (cfg & USB_VBUS_CURRENT_LIMIT_HIGH) { + reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 0); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_10MS) { + reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 1); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_20MS) { + reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 2); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_30MS) { + reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 3); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_40MS) { + reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 4); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_50MS) { + reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 5); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_60MS) { + reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 6); + } + + if (cfg & USB_VBUS_PULLDOWN) { + // reg_value |= SET_BITS(regUSB0, VBUSPDENB, 1); + reg_mask |= SET_BITS(regUSB0, VBUSPDENB, 1); + } + + rc = pmic_write_reg(REG_USB, reg_value, reg_mask); + + if (rc == PMIC_SUCCESS) { + usb.usbOtgCfg &= ~cfg; + } + } + //} + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Get the current USB On-The-Go (OTG) configuration. + * + * @param handle device handle from open() call + * @param cfg the current USB OTG configuration + * + * @return PMIC_SUCCESS if the OTG configuration was successfully + * retrieved + */ +PMIC_STATUS pmic_convity_usb_otg_get_config(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_USB_OTG_CONFIG * + const cfg) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE) && + (cfg != (PMIC_CONVITY_USB_OTG_CONFIG *) NULL)) { + *cfg = usb.usbOtgCfg; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*@}*/ + +/************************************************************************** + * RS-232-specific configuration and setup functions. + ************************************************************************** + */ + +/*! + * @name RS-232 Serial Connectivity APIs + * Functions for controlling RS-232 serial connectivity. + */ +/*@{*/ + +/*! + * Set the connectivity interface to the selected RS-232 operating + * configuration. Note that the RS-232 operating mode will be automatically + * overridden if the USB_EN is asserted at any time (e.g., when a USB device + * is attached). However, we will also automatically return to the RS-232 + * mode once the USB device is detached. + * + * @param handle device handle from open() call + * @param cfgInternal RS-232 transceiver internal connections + * @param cfgExternal RS-232 transceiver external connections + * + * @return PMIC_SUCCESS if the requested mode was set + */ +PMIC_STATUS pmic_convity_rs232_set_config(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_RS232_INTERNAL + cfgInternal, + const PMIC_CONVITY_RS232_EXTERNAL + cfgExternal) +{ + PMIC_STATUS rc = PMIC_ERROR; + unsigned int reg_value0 = 0, reg_value1 = 0; + unsigned int reg_mask = SET_BITS(regUSB1, RSPOL, 1); + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == rs_232.handle) && (rs_232.handle_state == HANDLE_IN_USE)) { + rc = PMIC_SUCCESS; + + /* Validate the calling parameters. */ + /*if ((cfgInternal != RS232_TX_USE0VM_RX_UDATVP) && + (cfgInternal != RS232_TX_RX_INTERNAL_DEFAULT) && (cfgInternal != RS232_TX_UDATVP_RX_URXVM)) + { + + rc = PMIC_NOT_SUPPORTED; + } */ + if (cfgInternal == RS232_TX_USE0VM_RX_UDATVP) { + + reg_value0 = SET_BITS(regUSB0, INTERFACE_MODE, 1); + + } else if (cfgInternal == RS232_TX_RX_INTERNAL_DEFAULT) { + + reg_value0 = SET_BITS(regUSB0, INTERFACE_MODE, 1); + reg_mask |= SET_BITS(regUSB1, RSPOL, 1); + + } else if (cfgInternal == RS232_TX_UDATVP_RX_URXVM) { + + reg_value0 = SET_BITS(regUSB0, INTERFACE_MODE, 2); + reg_value1 |= SET_BITS(regUSB1, RSPOL, 1); + + } else if ((cfgExternal == RS232_TX_UDM_RX_UDP) || + (cfgExternal == RS232_TX_RX_EXTERNAL_DEFAULT)) { + /* Configure for TX on D+ and RX on D-. */ + reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 1); + reg_value1 |= SET_BITS(regUSB1, RSPOL, 0); + } else if (cfgExternal != RS232_TX_UDM_RX_UDP) { + /* Any other RS-232 configuration is an error. */ + rc = PMIC_ERROR; + } + + if (rc == PMIC_SUCCESS) { + /* Configure for TX on D- and RX on D+. */ + rc = pmic_write_reg(REG_USB, reg_value0, reg_mask); + + rc = pmic_write_reg(REG_CHARGE_USB_SPARE, + reg_value1, reg_mask); + + if (rc == PMIC_SUCCESS) { + rs_232.rs232CfgInternal = cfgInternal; + rs_232.rs232CfgExternal = cfgExternal; + } + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Get the connectivity interface's current RS-232 operating configuration. + * + * @param handle device handle from open() call + * @param cfgInternal RS-232 transceiver internal connections + * @param cfgExternal RS-232 transceiver external connections + * + * @return PMIC_SUCCESS if the requested mode was retrieved + */ +PMIC_STATUS pmic_convity_rs232_get_config(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_RS232_INTERNAL * + const cfgInternal, + PMIC_CONVITY_RS232_EXTERNAL * + const cfgExternal) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == rs_232.handle) && + (rs_232.handle_state == HANDLE_IN_USE) && + (cfgInternal != (PMIC_CONVITY_RS232_INTERNAL *) NULL) && + (cfgExternal != (PMIC_CONVITY_RS232_EXTERNAL *) NULL)) { + *cfgInternal = rs_232.rs232CfgInternal; + *cfgExternal = rs_232.rs232CfgExternal; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*@}*/ + +/************************************************************************** + * CEA-936-specific configuration and setup functions. + ************************************************************************** + */ + +/*! + * @name CEA-936 Connectivity APIs + * Functions for controlling CEA-936 connectivity. + */ +/*@{*/ + +/*! + * Signal the attached device to exit the current CEA-936 operating mode. + * Returns an error if the current operating mode is not CEA-936. + * + * @param handle device handle from open() call + * @param signal type of exit signal to be sent + * + * @return PMIC_SUCCESS if exit signal was sent + */ +PMIC_STATUS pmic_convity_cea936_exit_signal(const PMIC_CONVITY_HANDLE handle, + const + PMIC_CONVITY_CEA936_EXIT_SIGNAL + signal) +{ + PMIC_STATUS rc = PMIC_ERROR; + unsigned int reg_value = 0; + unsigned int reg_mask = + SET_BITS(regUSB0, IDPD, 1) | SET_BITS(regUSB0, IDPULSE, 1); + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle != cea_936.handle) + || (cea_936.handle_state != HANDLE_IN_USE)) { + /* Must return error indication for invalid handle parameter to be + * consistent with other APIs. + */ + rc = PMIC_ERROR; + } else if (signal == CEA936_UID_PULLDOWN_6MS) { + reg_value = + SET_BITS(regUSB0, IDPULSE, 0) | SET_BITS(regUSB0, IDPD, 0); + } else if (signal == CEA936_UID_PULLDOWN_6MS) { + reg_value = SET_BITS(regUSB0, IDPULSE, 1); + } else if (signal == CEA936_UID_PULLDOWN) { + reg_value = SET_BITS(regUSB0, IDPD, 1); + } else if (signal == CEA936_UDMPULSE) { + reg_value = SET_BITS(regUSB0, DMPULSE, 1); + } + + rc = pmic_write_reg(REG_USB, reg_value, reg_mask); + + up(&mutex); + + return rc; +} + +/*@}*/ + +/************************************************************************** + * Static functions. + ************************************************************************** + */ + +/*! + * @name Connectivity Driver Internal Support Functions + * These non-exported internal functions are used to support the functionality + * of the exported connectivity APIs. + */ +/*@{*/ + +/*! + * This internal helper function sets the desired operating mode (either USB + * OTG or RS-232). It must be called with the mutex already acquired. + * + * @param mode the desired operating mode (USB or RS232) + * + * @return PMIC_SUCCESS if the desired operating mode was set + * @return PMIC_NOT_SUPPORTED if the desired operating mode is invalid + */ +static PMIC_STATUS pmic_convity_set_mode_internal(const PMIC_CONVITY_MODE mode) +{ + unsigned int reg_value0 = 0, reg_value1 = 0; + unsigned int reg_mask0 = 0, reg_mask1 = 0; + + //unsigned int reg_mask1 = SET_BITS(regUSB1, VBUSEN, 1); + + PMIC_STATUS rc = PMIC_SUCCESS; + + switch (mode) { + case USB: + /* For the USB mode, we start by tri-stating the USB bus (by + * setting VBUSEN = 0) until a device is connected (i.e., + * until we receive a 4.4V rising edge event). All pull-up + * and pull-down resistors are also disabled until a USB + * device is actually connected and we have determined which + * device is the host and the desired USB bus speed. + * + * Also tri-state the RS-232 buffers (by setting RSTRI = 1). + * This prevents the hardware from automatically returning to + * the RS-232 mode when the USB device is detached. + */ + + reg_value0 = SET_BITS(regUSB0, INTERFACE_MODE, 0); + reg_mask0 = SET_BITS(regUSB0, INTERFACE_MODE, 7); + + /*reg_value1 = SET_BITS(regUSB1, RSTRI, 1); */ + + rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0); + /* if (rc == PMIC_SUCCESS) { + CHECK_ERROR(pmic_write_reg + (REG_CHARGE_USB_SPARE, + reg_value1, reg_mask1)); + } */ + + break; + + case RS232_1: + /* For the RS-232 mode, we tri-state the USB bus (by setting + * VBUSEN = 0) and enable the RS-232 transceiver (by setting + * RS232ENB = 0). + * + * Note that even in the RS-232 mode, if a USB device is + * plugged in, we will receive a 4.4V rising edge event which + * will automatically disable the RS-232 transceiver and + * tri-state the RS-232 buffers. This allows us to temporarily + * switch over to USB mode while the USB device is attached. + * The RS-232 transceiver and buffers will be automatically + * re-enabled when the USB device is detached. + */ + + /* Explicitly disconnect all of the USB pull-down resistors + * and the VUSB power regulator here just to be safe. + * + * But we do connect the internal pull-up resistor on USB_D+ + * to avoid having an extra load on the USB_D+ line when in + * RS-232 mode. + */ + + reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 1) | + SET_BITS(regUSB0, VBUSPDENB, 1) | + SET_BITS(regUSB0, USB_PU, 1); + reg_mask0 = + SET_BITS(regUSB0, INTERFACE_MODE, 7) | SET_BITS(regUSB0, + VBUSPDENB, + 1) | + SET_BITS(regUSB0, USB_PU, 1); + + reg_value1 = SET_BITS(regUSB1, RSPOL, 0); + + rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0); + + if (rc == PMIC_SUCCESS) { + CHECK_ERROR(pmic_write_reg + (REG_CHARGE_USB_SPARE, + reg_value1, reg_mask1)); + } + break; + + case RS232_2: + reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 2) | + SET_BITS(regUSB0, VBUSPDENB, 1) | + SET_BITS(regUSB0, USB_PU, 1); + reg_mask0 = + SET_BITS(regUSB0, INTERFACE_MODE, 7) | SET_BITS(regUSB0, + VBUSPDENB, + 1) | + SET_BITS(regUSB0, USB_PU, 1); + + reg_value1 = SET_BITS(regUSB1, RSPOL, 1); + + rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0); + + if (rc == PMIC_SUCCESS) { + CHECK_ERROR(pmic_write_reg + (REG_CHARGE_USB_SPARE, + reg_value1, reg_mask1)); + } + break; + + case CEA936_MONO: + reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 4); + + rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0); + break; + + case CEA936_STEREO: + reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 5); + reg_mask0 = SET_BITS(regUSB0, INTERFACE_MODE, 7); + + rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0); + break; + + case CEA936_TEST_RIGHT: + reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 6); + reg_mask0 = SET_BITS(regUSB0, INTERFACE_MODE, 7); + + rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0); + break; + + case CEA936_TEST_LEFT: + reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 7); + reg_mask0 = SET_BITS(regUSB0, INTERFACE_MODE, 7); + + rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0); + break; + + default: + rc = PMIC_NOT_SUPPORTED; + } + + if (rc == PMIC_SUCCESS) { + if (mode == USB) { + usb.mode = mode; + } else if ((mode == RS232_1) || (mode == RS232_1)) { + rs_232.mode = mode; + } else if ((mode == CEA936_MONO) || (mode == CEA936_STEREO) || + (mode == CEA936_TEST_RIGHT) + || (mode == CEA936_TEST_LEFT)) { + cea_936.mode = mode; + } + } + + return rc; +} + +/*! + * This internal helper function deregisters all of the currently registered + * callback events. It must be called with the mutual exclusion spinlock + * already acquired. + * + * We've defined the event and callback deregistration code here as a separate + * function because it can be called by either the pmic_convity_close() or the + * pmic_convity_clear_callback() APIs. We also wanted to avoid any possible + * issues with having the same thread calling spin_lock_irq() twice. + * + * Note that the mutex must have already been acquired. We will also acquire + * the spinlock here to avoid any possible race conditions with the interrupt + * handler. + * + * @return PMIC_SUCCESS if all of the callback events were cleared + */ +static PMIC_STATUS pmic_convity_deregister_all(void) +{ + unsigned long flags; + PMIC_STATUS rc = PMIC_SUCCESS; + + /* Deregister each of the PMIC events that we had previously + * registered for by using pmic_event_subscribe(). + */ + + if ((usb.eventMask & USB_DETECT_MINI_A) || + (usb.eventMask & USB_DETECT_MINI_B) || + (usb.eventMask & USB_DETECT_NON_USB_ACCESSORY) || + (usb.eventMask & USB_DETECT_FACTORY_MODE)) { + //EVENT_AB_DETI or EVENT_IDI + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_ABDET); + + if (pmic_event_unsubscribe(EVENT_IDI, eventNotify) == + PMIC_SUCCESS) { + /* Also acquire the spinlock here to avoid any possible race + * conditions with the interrupt handler. + */ + + spin_lock_irqsave(&lock, flags); + + usb.eventMask &= ~(USB_DETECT_MINI_A | + USB_DETECT_MINI_B | + USB_DETECT_NON_USB_ACCESSORY | + USB_DETECT_FACTORY_MODE); + + spin_unlock_irqrestore(&lock, flags); + } else { + pr_debug + ("%s: pmic_event_unsubscribe() for EVENT_AB_DETI failed\n", + __FILE__); + rc = PMIC_ERROR; + } + } + + else if ((usb.eventMask & USB_DETECT_0V8_RISE) || + (usb.eventMask & USB_DETECT_0V8_FALL)) { + //EVENT_USB_08VI or EVENT_USBI + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_0V8); + if (pmic_event_unsubscribe(EVENT_USBI, eventNotify) == + PMIC_SUCCESS) { + /* Also acquire the spinlock here to avoid any possible race + * conditions with the interrupt handler. + */ + spin_lock_irqsave(&lock, flags); + + usb.eventMask &= ~(USB_DETECT_0V8_RISE | + USB_DETECT_0V8_FALL); + + spin_unlock_irqrestore(&lock, flags); + } else { + pr_debug + ("%s: pmic_event_unsubscribe() for EVENT_USB_08VI failed\n", + __FILE__); + rc = PMIC_ERROR; + } + + } + + else if ((usb.eventMask & USB_DETECT_2V0_RISE) || + (usb.eventMask & USB_DETECT_2V0_FALL)) { + //EVENT_USB_20VI or EVENT_USBI + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_2V0); + if (pmic_event_unsubscribe(EVENT_USBI, eventNotify) == + PMIC_SUCCESS) { + /* Also acquire the spinlock here to avoid any possible race + * conditions with the interrupt handler. + */ + spin_lock_irqsave(&lock, flags); + + usb.eventMask &= ~(USB_DETECT_2V0_RISE | + USB_DETECT_2V0_FALL); + + spin_unlock_irqrestore(&lock, flags); + } else { + pr_debug + ("%s: pmic_event_unsubscribe() for EVENT_USB_20VI failed\n", + __FILE__); + rc = PMIC_ERROR; + } + } + + else if ((usb.eventMask & USB_DETECT_4V4_RISE) || + (usb.eventMask & USB_DETECT_4V4_FALL)) { + + //EVENT_USB_44VI or EVENT_USBI + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_4V4); + + if (pmic_event_unsubscribe(EVENT_USBI, eventNotify) == + PMIC_SUCCESS) { + + /* Also acquire the spinlock here to avoid any possible race + * conditions with the interrupt handler. + */ + spin_lock_irqsave(&lock, flags); + + usb.eventMask &= ~(USB_DETECT_4V4_RISE | + USB_DETECT_4V4_FALL); + + spin_unlock_irqrestore(&lock, flags); + } else { + pr_debug + ("%s: pmic_event_unsubscribe() for EVENT_USB_44VI failed\n", + __FILE__); + rc = PMIC_ERROR; + } + } + + if (rc == PMIC_SUCCESS) { + /* Also acquire the spinlock here to avoid any possible race + * conditions with the interrupt handler. + */ + spin_lock_irqsave(&lock, flags); + + /* Restore the initial reset values for the callback function + * and event mask parameters. This should be NULL and zero, + * respectively. + * + * Note that we wait until the end here to fully reset everything + * just in case some of the pmic_event_unsubscribe() calls above + * failed for some reason (which normally shouldn't happen). + */ + usb.callback = reset.callback; + usb.eventMask = reset.eventMask; + + spin_unlock_irqrestore(&lock, flags); + } + return rc; +} + +/*! + * This is the default event handler for all connectivity-related events + * and hardware interrupts. + * + * @param param event ID + */ +static void pmic_convity_event_handler(void *param) +{ + unsigned long flags; + + /* Update the global list of active interrupt events. */ + spin_lock_irqsave(&lock, flags); + eventID |= (PMIC_CORE_EVENT) (param); + spin_unlock_irqrestore(&lock, flags); + + /* Schedule the tasklet to be run as soon as it is convenient to do so. */ + schedule_work(&convityTasklet); +} + +/*! + * @brief This is the connectivity driver tasklet that handles interrupt events. + * + * This function is scheduled by the connectivity driver interrupt handler + * pmic_convity_event_handler() to complete the processing of all of the + * connectivity-related interrupt events. + * + * Since this tasklet runs with interrupts enabled, we can safely call + * the ADC driver, if necessary, to properly detect the type of USB connection + * that is being made and to call any user-registered callback functions. + * + * @param arg The parameter that was provided above in + * the DECLARE_TASKLET() macro (unused). + */ +static void pmic_convity_tasklet(struct work_struct *work) +{ + + PMIC_CONVITY_EVENTS activeEvents = 0; + unsigned long flags = 0; + + /* Check the interrupt sense bits to determine exactly what + * event just occurred. + */ + if (eventID & CORE_EVENT_4V4) { + spin_lock_irqsave(&lock, flags); + eventID &= ~CORE_EVENT_4V4; + spin_unlock_irqrestore(&lock, flags); + + activeEvents |= pmic_check_sensor(SENSE_USB4V4S) ? + USB_DETECT_4V4_RISE : USB_DETECT_4V4_FALL; + + if (activeEvents & ~usb.eventMask) { + /* The default handler for 4.4 V rising/falling edge detection + * is to simply ignore the event. + */ + ; + } + } + if (eventID & CORE_EVENT_2V0) { + spin_lock_irqsave(&lock, flags); + eventID &= ~CORE_EVENT_2V0; + spin_unlock_irqrestore(&lock, flags); + + activeEvents |= pmic_check_sensor(SENSE_USB2V0S) ? + USB_DETECT_2V0_RISE : USB_DETECT_2V0_FALL; + if (activeEvents & ~usb.eventMask) { + /* The default handler for 2.0 V rising/falling edge detection + * is to simply ignore the event. + */ + ; + } + } + if (eventID & CORE_EVENT_0V8) { + spin_lock_irqsave(&lock, flags); + eventID &= ~CORE_EVENT_0V8; + spin_unlock_irqrestore(&lock, flags); + + activeEvents |= pmic_check_sensor(SENSE_USB0V8S) ? + USB_DETECT_0V8_RISE : USB_DETECT_0V8_FALL; + + if (activeEvents & ~usb.eventMask) { + /* The default handler for 0.8 V rising/falling edge detection + * is to simply ignore the event. + */ + ; + } + } + if (eventID & CORE_EVENT_ABDET) { + spin_lock_irqsave(&lock, flags); + eventID &= ~CORE_EVENT_ABDET; + spin_unlock_irqrestore(&lock, flags); + + activeEvents |= pmic_check_sensor(SENSE_ID_GNDS) ? + USB_DETECT_MINI_A : 0; + + activeEvents |= pmic_check_sensor(SENSE_ID_FLOATS) ? + USB_DETECT_MINI_B : 0; + } + + /* Begin a critical section here so that we don't register/deregister + * for events or open/close the connectivity driver while the existing + * event handler (if it is currently defined) is in the middle of handling + * the current event. + */ + spin_lock_irqsave(&lock, flags); + + /* Finally, call the user-defined callback function if required. */ + if ((usb.handle_state == HANDLE_IN_USE) && + (usb.callback != NULL) && (activeEvents & usb.eventMask)) { + (*usb.callback) (activeEvents); + } + + spin_unlock_irqrestore(&lock, flags); +} + +/*@}*/ + +/************************************************************************** + * Module initialization and termination functions. + * + * Note that if this code is compiled into the kernel, then the + * module_init() function will be called within the device_initcall() + * group. + ************************************************************************** + */ + +/*! + * @name Connectivity Driver Loading/Unloading Functions + * These non-exported internal functions are used to support the connectivity + * device driver initialization and de-initialization operations. + */ +/*@{*/ + +/*! + * @brief This is the connectivity device driver initialization function. + * + * This function is called by the kernel when this device driver is first + * loaded. + */ +static int __init mc13783_pmic_convity_init(void) +{ + printk(KERN_INFO "PMIC Connectivity driver loading..\n"); + + return 0; +} + +/*! + * @brief This is the Connectivity device driver de-initialization function. + * + * This function is called by the kernel when this device driver is about + * to be unloaded. + */ +static void __exit mc13783_pmic_convity_exit(void) +{ + printk(KERN_INFO "PMIC Connectivity driver unloading\n"); + + /* Close the device handle if it is still open. This will also + * deregister any callbacks that may still be active. + */ + if (usb.handle_state == HANDLE_IN_USE) { + pmic_convity_close(usb.handle); + } else if (usb.handle_state == HANDLE_IN_USE) { + pmic_convity_close(rs_232.handle); + } else if (usb.handle_state == HANDLE_IN_USE) { + pmic_convity_close(cea_936.handle); + } + + /* Reset the PMIC Connectivity register to it's power on state. + * We should do this when unloading the module so that we don't + * leave the hardware in a state which could cause problems when + * no device driver is loaded. + */ + pmic_write_reg(REG_USB, RESET_USBCNTRL_REG_0, REG_FULLMASK); + pmic_write_reg(REG_CHARGE_USB_SPARE, RESET_USBCNTRL_REG_1, + REG_FULLMASK); + /* Note that there is no need to reset the "convity" device driver + * state structure to the reset state since we are in the final + * stage of unloading the device driver. The device driver state + * structure will be automatically and properly reinitialized if + * this device driver is reloaded. + */ +} + +/*@}*/ + +/* + * Module entry points and description information. + */ + +module_init(mc13783_pmic_convity_init); +module_exit(mc13783_pmic_convity_exit); + +MODULE_DESCRIPTION("mc13783 Connectivity device driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_light.c linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_light.c --- linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_light.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_light.c 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,2768 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_light.c + * @brief This is the main file of PMIC(mc13783) Light and Backlight driver. + * + * @ingroup PMIC_LIGHT + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include "pmic_light_defs.h" + +#define NB_LIGHT_REG 6 + +static int pmic_light_major; + +/*! + * Number of users waiting in suspendq + */ +static int swait = 0; + +/*! + * To indicate whether any of the light devices are suspending + */ +static int suspend_flag = 0; + +/*! + * The suspendq is used to block application calls + */ +static wait_queue_head_t suspendq; + +static struct class *pmic_light_class; + +/* EXPORTED FUNCTIONS */ +EXPORT_SYMBOL(pmic_bklit_tcled_master_enable); +EXPORT_SYMBOL(pmic_bklit_tcled_master_disable); +EXPORT_SYMBOL(pmic_bklit_master_enable); +EXPORT_SYMBOL(pmic_bklit_master_disable); +EXPORT_SYMBOL(pmic_bklit_set_current); +EXPORT_SYMBOL(pmic_bklit_get_current); +EXPORT_SYMBOL(pmic_bklit_set_dutycycle); +EXPORT_SYMBOL(pmic_bklit_get_dutycycle); +EXPORT_SYMBOL(pmic_bklit_set_cycle_time); +EXPORT_SYMBOL(pmic_bklit_get_cycle_time); +EXPORT_SYMBOL(pmic_bklit_set_mode); +EXPORT_SYMBOL(pmic_bklit_get_mode); +EXPORT_SYMBOL(pmic_bklit_rampup); +EXPORT_SYMBOL(pmic_bklit_off_rampup); +EXPORT_SYMBOL(pmic_bklit_rampdown); +EXPORT_SYMBOL(pmic_bklit_off_rampdown); +EXPORT_SYMBOL(pmic_bklit_enable_edge_slow); +EXPORT_SYMBOL(pmic_bklit_disable_edge_slow); +EXPORT_SYMBOL(pmic_bklit_get_edge_slow); +EXPORT_SYMBOL(pmic_bklit_set_strobemode); +EXPORT_SYMBOL(pmic_tcled_enable); +EXPORT_SYMBOL(pmic_tcled_disable); +EXPORT_SYMBOL(pmic_tcled_get_mode); +EXPORT_SYMBOL(pmic_tcled_ind_set_current); +EXPORT_SYMBOL(pmic_tcled_ind_get_current); +EXPORT_SYMBOL(pmic_tcled_ind_set_blink_pattern); +EXPORT_SYMBOL(pmic_tcled_ind_get_blink_pattern); +EXPORT_SYMBOL(pmic_tcled_fun_set_current); +EXPORT_SYMBOL(pmic_tcled_fun_get_current); +EXPORT_SYMBOL(pmic_tcled_fun_set_cycletime); +EXPORT_SYMBOL(pmic_tcled_fun_get_cycletime); +EXPORT_SYMBOL(pmic_tcled_fun_set_dutycycle); +EXPORT_SYMBOL(pmic_tcled_fun_get_dutycycle); +EXPORT_SYMBOL(pmic_tcled_fun_blendedramps); +EXPORT_SYMBOL(pmic_tcled_fun_sawramps); +EXPORT_SYMBOL(pmic_tcled_fun_blendedbowtie); +EXPORT_SYMBOL(pmic_tcled_fun_chasinglightspattern); +EXPORT_SYMBOL(pmic_tcled_fun_strobe); +EXPORT_SYMBOL(pmic_tcled_fun_rampup); +EXPORT_SYMBOL(pmic_tcled_get_fun_rampup); +EXPORT_SYMBOL(pmic_tcled_fun_rampdown); +EXPORT_SYMBOL(pmic_tcled_get_fun_rampdown); +EXPORT_SYMBOL(pmic_tcled_fun_triode_on); +EXPORT_SYMBOL(pmic_tcled_fun_triode_off); +EXPORT_SYMBOL(pmic_tcled_enable_edge_slow); +EXPORT_SYMBOL(pmic_tcled_disable_edge_slow); +EXPORT_SYMBOL(pmic_tcled_enable_half_current); +EXPORT_SYMBOL(pmic_tcled_disable_half_current); +EXPORT_SYMBOL(pmic_tcled_enable_audio_modulation); +EXPORT_SYMBOL(pmic_tcled_disable_audio_modulation); +EXPORT_SYMBOL(pmic_bklit_set_boost_mode); +EXPORT_SYMBOL(pmic_bklit_get_boost_mode); +EXPORT_SYMBOL(pmic_bklit_config_boost_mode); +EXPORT_SYMBOL(pmic_bklit_gets_boost_mode); + +/*! + * This is the suspend of power management for the pmic light API. + * It suports SAVE and POWER_DOWN state. + * + * @param pdev the device + * @param state the state + * + * @return This function returns 0 if successful. + */ +static int pmic_light_suspend(struct platform_device *dev, pm_message_t state) +{ + suspend_flag = 1; + /* switch off all leds and backlights */ + CHECK_ERROR(pmic_light_init_reg()); + + return 0; +}; + +/*! + * This is the resume of power management for the pmic light API. + * It suports RESTORE state. + * + * @param dev the device + * + * @return This function returns 0 if successful. + */ +static int pmic_light_resume(struct platform_device *pdev) +{ + suspend_flag = 0; + while (swait > 0) { + swait--; + wake_up_interruptible(&suspendq); + } + + return 0; +}; + +/*! + * This function enables backlight & tcled. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_tcled_master_enable(void) +{ + unsigned int reg_value = 0; + unsigned int mask = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + reg_value = BITFVAL(BIT_LEDEN, 1); + mask = BITFMASK(BIT_LEDEN); + CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function disables backlight & tcled. + * + * @return This function returns PMIC_SUCCESS if successful + */ +PMIC_STATUS pmic_bklit_tcled_master_disable(void) +{ + unsigned int reg_value = 0; + unsigned int mask = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + reg_value = BITFVAL(BIT_LEDEN, 0); + mask = BITFMASK(BIT_LEDEN); + CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function enables backlight. Not supported on mc13783 + * Use pmic_bklit_tcled_master_enable. + * + * @return This function returns PMIC_NOT_SUPPORTED + */ +PMIC_STATUS pmic_bklit_master_enable(void) +{ + return PMIC_NOT_SUPPORTED; +} + +/*! + * This function disables backlight. Not supported on mc13783 + * Use pmic_bklit_tcled_master_enable. + * + * @return This function returns PMIC_NOT_SUPPORTED + */ +PMIC_STATUS pmic_bklit_master_disable(void) +{ + return PMIC_NOT_SUPPORTED; +} + +/*! + * This function sets backlight current level. + * + * @param channel Backlight channel + * @param level Backlight current level, as the following table. + * @verbatim + level main & aux keyboard + ------ ----------- -------- + 0 0 mA 0 mA + 1 3 mA 12 mA + 2 6 mA 24 mA + 3 9 mA 36 mA + 4 12 mA 48 mA + 5 15 mA 60 mA + 6 18 mA 72 mA + 7 21 mA 84 mA + @endverbatim + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_set_current(t_bklit_channel channel, unsigned char level) +{ + unsigned int mask; + unsigned int value; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (channel) { + case BACKLIGHT_LED1: + value = BITFVAL(BIT_CL_MAIN, level); + mask = BITFMASK(BIT_CL_MAIN); + break; + case BACKLIGHT_LED2: + value = BITFVAL(BIT_CL_AUX, level); + mask = BITFMASK(BIT_CL_AUX); + break; + case BACKLIGHT_LED3: + value = BITFVAL(BIT_CL_KEY, level); + mask = BITFMASK(BIT_CL_KEY); + break; + default: + return PMIC_PARAMETER_ERROR; + } + CHECK_ERROR(pmic_write_reg(LREG_2, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function retrives backlight current level. + * The channels are not individually adjustable, hence + * the channel parameter is ignored. + * + * @param channel Backlight channel (Ignored because the + * channels are not individually adjustable) + * @param level Pointer to store backlight current level result. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_get_current(t_bklit_channel channel, + unsigned char *level) +{ + unsigned int reg_value = 0; + unsigned int mask = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (channel) { + case BACKLIGHT_LED1: + mask = BITFMASK(BIT_CL_MAIN); + break; + case BACKLIGHT_LED2: + mask = BITFMASK(BIT_CL_AUX); + break; + case BACKLIGHT_LED3: + mask = BITFMASK(BIT_CL_KEY); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(LREG_2, ®_value, mask)); + + switch (channel) { + case BACKLIGHT_LED1: + *level = BITFEXT(reg_value, BIT_CL_MAIN); + break; + case BACKLIGHT_LED2: + *level = BITFEXT(reg_value, BIT_CL_AUX); + break; + case BACKLIGHT_LED3: + *level = BITFEXT(reg_value, BIT_CL_KEY); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets a backlight channel duty cycle. + * LED perceived brightness for each zone may be individually set by setting + * duty cycle. The default setting is for 0% duty cycle; this keeps all zone + * drivers turned off even after the master enable command. Each LED current + * sink can be turned on and adjusted for brightness with an independent 4 bit + * word for a duty cycle ranging from 0% to 100% in approximately 6.7% steps. + * + * @param channel Backlight channel. + * @param dc Backlight duty cycle, as the following table. + * @verbatim + dc Duty Cycle (% On-time over Cycle Time) + ------ --------------------------------------- + 0 0% + 1 6.7% + 2 13.3% + 3 20% + 4 26.7% + 5 33.3% + 6 40% + 7 46.7% + 8 53.3% + 9 60% + 10 66.7% + 11 73.3% + 12 80% + 13 86.7% + 14 93.3% + 15 100% + @endverbatim + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_set_dutycycle(t_bklit_channel channel, unsigned char dc) +{ + unsigned int reg_value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + if (dc > 15) { + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(LREG_2, ®_value, PMIC_ALL_BITS)); + + switch (channel) { + case BACKLIGHT_LED1: + reg_value = reg_value & (~MASK_DUTY_CYCLE); + reg_value = reg_value | (dc << BIT_DUTY_CYCLE); + break; + case BACKLIGHT_LED2: + reg_value = reg_value & (~(MASK_DUTY_CYCLE << INDEX_AUX)); + reg_value = reg_value | (dc << (BIT_DUTY_CYCLE + INDEX_AUX)); + break; + case BACKLIGHT_LED3: + reg_value = reg_value & (~(MASK_DUTY_CYCLE << INDEX_KYD)); + reg_value = reg_value | (dc << (BIT_DUTY_CYCLE + INDEX_KYD)); + break; + default: + return PMIC_PARAMETER_ERROR; + } + CHECK_ERROR(pmic_write_reg(LREG_2, reg_value, PMIC_ALL_BITS)); + return PMIC_SUCCESS; + +} + +/*! + * This function retrives a backlight channel duty cycle. + * + * @param channel Backlight channel. + * @param dc Pointer to backlight duty cycle. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_get_dutycycle(t_bklit_channel channel, unsigned char *dc) +{ + unsigned int reg_value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + CHECK_ERROR(pmic_read_reg(LREG_2, ®_value, PMIC_ALL_BITS)); + + switch (channel) { + case BACKLIGHT_LED1: + *dc = (int)((reg_value & (MASK_DUTY_CYCLE)) + >> BIT_DUTY_CYCLE); + + break; + case BACKLIGHT_LED2: + *dc = (int)((reg_value & (MASK_DUTY_CYCLE << INDEX_AUX)) + >> (BIT_DUTY_CYCLE + INDEX_AUX)); + break; + case BACKLIGHT_LED3: + *dc = (int)((reg_value & (MASK_DUTY_CYCLE << + INDEX_KYD)) >> (BIT_DUTY_CYCLE + + INDEX_KYD)); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets a backlight channel cycle time. + * Cycle Time is defined as the period of a complete cycle of + * Time_on + Time_off. The default Cycle Time is set to 0.01 seconds such that + * the 100 Hz on-off cycling is averaged out by the eye to eliminate + * flickering. Additionally, the Cycle Time can be programmed to intentionally + * extend the period of on-off cycles for a visual pulsating or blinking effect. + * + * @param period Backlight cycle time, as the following table. + * @verbatim + period Cycle Time + -------- ------------ + 0 0.01 seconds + 1 0.1 seconds + 2 0.5 seconds + 3 2 seconds + @endverbatim + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_set_cycle_time(unsigned char period) +{ + unsigned int mask; + unsigned int value; + + if (suspend_flag == 1) { + return -EBUSY; + } + if (period > 3) { + return PMIC_PARAMETER_ERROR; + } + mask = BITFMASK(BIT_PERIOD); + value = BITFVAL(BIT_PERIOD, period); + CHECK_ERROR(pmic_write_reg(LREG_2, value, mask)); + return PMIC_SUCCESS; +} + +/*! + * This function retrives a backlight channel cycle time setting. + * + * @param period Pointer to save backlight cycle time setting result. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_get_cycle_time(unsigned char *period) +{ + unsigned int mask; + unsigned int value; + + if (suspend_flag == 1) { + return -EBUSY; + } + mask = BITFMASK(BIT_PERIOD); + CHECK_ERROR(pmic_read_reg(LREG_2, &value, mask)); + *period = BITFEXT(value, BIT_PERIOD); + return PMIC_SUCCESS; +} + +/*! + * This function sets backlight operation mode. There are two modes of + * operations: current control and triode mode. + * The Duty Cycle/Cycle Time control is retained in Triode Mode. Audio + * coupling is not available in Triode Mode. + * + * @param channel Backlight channel. + * @param mode Backlight operation mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_set_mode(t_bklit_channel channel, t_bklit_mode mode) +{ + unsigned int reg_value = 0; + unsigned int clear_val = 0; + unsigned int triode_val = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + CHECK_ERROR(pmic_read_reg(LREG_0, ®_value, PMIC_ALL_BITS)); + + switch (channel) { + case BACKLIGHT_LED1: + clear_val = ~(MASK_TRIODE_MAIN_BL); + triode_val = MASK_TRIODE_MAIN_BL; + break; + case BACKLIGHT_LED2: + clear_val = ~(MASK_TRIODE_MAIN_BL << INDEX_AUXILIARY); + triode_val = (MASK_TRIODE_MAIN_BL << INDEX_AUXILIARY); + break; + case BACKLIGHT_LED3: + clear_val = ~(MASK_TRIODE_MAIN_BL << INDEX_KEYPAD); + triode_val = (MASK_TRIODE_MAIN_BL << INDEX_KEYPAD); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + reg_value = (reg_value & clear_val); + + if (mode == BACKLIGHT_TRIODE_MODE) { + reg_value = (reg_value | triode_val); + } + + CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, PMIC_ALL_BITS)); + return PMIC_SUCCESS; +} + +/*! + * This function gets backlight operation mode. There are two modes of + * operations: current control and triode mode. + * The Duty Cycle/Cycle Time control is retained in Triode Mode. Audio + * coupling is not available in Triode Mode. + * + * @param channel Backlight channel. + * @param mode Backlight operation mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_get_mode(t_bklit_channel channel, t_bklit_mode * mode) +{ + unsigned int reg_value = 0; + unsigned int mask = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (channel) { + case BACKLIGHT_LED1: + mask = BITFMASK(BIT_TRIODE_MAIN_BL); + break; + case BACKLIGHT_LED2: + mask = BITFMASK(BIT_TRIODE_AUX_BL); + break; + case BACKLIGHT_LED3: + mask = BITFMASK(BIT_TRIODE_KEY_BL); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(LREG_0, ®_value, mask)); + + switch (channel) { + case BACKLIGHT_LED1: + *mode = BITFEXT(reg_value, BIT_TRIODE_MAIN_BL); + break; + case BACKLIGHT_LED2: + *mode = BITFEXT(reg_value, BIT_TRIODE_AUX_BL); + break; + case BACKLIGHT_LED3: + *mode = BITFEXT(reg_value, BIT_TRIODE_KEY_BL); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function starts backlight brightness ramp up function; ramp time is + * fixed at 0.5 seconds. + * + * @param channel Backlight channel. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_rampup(t_bklit_channel channel) +{ + unsigned int reg_value = 0; + unsigned int mask = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (channel) { + case BACKLIGHT_LED1: + mask = BITFMASK(BIT_UP_MAIN_BL); + reg_value = BITFVAL(BIT_UP_MAIN_BL, 1); + break; + case BACKLIGHT_LED2: + mask = BITFMASK(BIT_UP_AUX_BL); + reg_value = BITFVAL(BIT_UP_AUX_BL, 1); + break; + case BACKLIGHT_LED3: + mask = BITFMASK(BIT_UP_KEY_BL); + reg_value = BITFVAL(BIT_UP_KEY_BL, 1); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function stops backlight brightness ramp up function; + * + * @param channel Backlight channel. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_off_rampup(t_bklit_channel channel) +{ + unsigned int reg_value = 0; + unsigned int mask = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (channel) { + case BACKLIGHT_LED1: + mask = BITFMASK(BIT_UP_MAIN_BL); + break; + case BACKLIGHT_LED2: + mask = BITFMASK(BIT_UP_AUX_BL); + break; + case BACKLIGHT_LED3: + mask = BITFMASK(BIT_UP_KEY_BL); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function starts backlight brightness ramp down function; ramp time is + * fixed at 0.5 seconds. + * + * @param channel Backlight channel. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_rampdown(t_bklit_channel channel) +{ + unsigned int reg_value = 0; + unsigned int mask = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (channel) { + case BACKLIGHT_LED1: + mask = BITFMASK(BIT_DOWN_MAIN_BL); + reg_value = BITFVAL(BIT_DOWN_MAIN_BL, 1); + break; + case BACKLIGHT_LED2: + mask = BITFMASK(BIT_DOWN_AUX_BL); + reg_value = BITFVAL(BIT_DOWN_AUX_BL, 1); + break; + case BACKLIGHT_LED3: + mask = BITFMASK(BIT_DOWN_KEY_BL); + reg_value = BITFVAL(BIT_DOWN_KEY_BL, 1); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function stops backlight brightness ramp down function. + * + * @param channel Backlight channel. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_off_rampdown(t_bklit_channel channel) +{ + unsigned int reg_value = 0; + unsigned int mask = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (channel) { + case BACKLIGHT_LED1: + mask = BITFMASK(BIT_DOWN_MAIN_BL); + break; + case BACKLIGHT_LED2: + mask = BITFMASK(BIT_DOWN_AUX_BL); + break; + case BACKLIGHT_LED3: + mask = BITFMASK(BIT_DOWN_KEY_BL); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function enables backlight analog edge slowing mode. Analog Edge + * Slowing slows down the transient edges to reduce the chance of coupling LED + * modulation activity into other circuits. Rise and fall times will be targeted + * for approximately 50usec. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_enable_edge_slow(void) +{ + unsigned int mask; + unsigned int value; + + if (suspend_flag == 1) { + return -EBUSY; + } + mask = BITFMASK(BIT_SLEWLIMBL); + value = BITFVAL(BIT_SLEWLIMBL, 1); + CHECK_ERROR(pmic_write_reg(LREG_2, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function disables backlight analog edge slowing mode. The backlight + * drivers will default to an <93>Instant On<94> mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_disable_edge_slow(void) +{ + unsigned int mask; + + if (suspend_flag == 1) { + return -EBUSY; + } + mask = BITFMASK(BIT_SLEWLIMBL); + CHECK_ERROR(pmic_write_reg(LREG_2, 0, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets backlight analog edge slowing mode. DThe backlight + * + * @param edge Edge slowing mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_get_edge_slow(bool * edge) +{ + unsigned int mask; + unsigned int value; + + if (suspend_flag == 1) { + return -EBUSY; + } + mask = BITFMASK(BIT_SLEWLIMBL); + CHECK_ERROR(pmic_read_reg(LREG_2, &value, mask)); + *edge = (bool) BITFEXT(value, BIT_SLEWLIMBL); + + return PMIC_SUCCESS; +} + +/*! + * This function sets backlight Strobe Light Pulsing mode. + * + * @param channel Backlight channel. + * @param mode Strobe Light Pulsing mode. + * + * @return This function returns PMIC_NOT_SUPPORTED. + */ +PMIC_STATUS pmic_bklit_set_strobemode(t_bklit_channel channel, + t_bklit_strobe_mode mode) +{ + return PMIC_NOT_SUPPORTED; +} + +/*! + * This function enables tri-color LED. + * + * @param mode Tri-color LED operation mode. + * @param bank Selected tri-color bank + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_enable(t_tcled_mode mode, t_funlight_bank bank) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (mode) { + case TCLED_FUN_MODE: + switch (bank) { + case TCLED_FUN_BANK1: + mask = MASK_BK1_FL; + value = MASK_BK1_FL; + break; + case TCLED_FUN_BANK2: + mask = MASK_BK2_FL; + value = MASK_BK2_FL; + break; + case TCLED_FUN_BANK3: + mask = MASK_BK3_FL; + value = MASK_BK3_FL; + break; + default: + return PMIC_PARAMETER_ERROR; + } + break; + case TCLED_IND_MODE: + mask = MASK_BK1_FL | MASK_BK2_FL | MASK_BK3_FL; + break; + } + + CHECK_ERROR(pmic_write_reg(LREG_0, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function disables tri-color LED. + * + * @param bank Selected tri-color bank + * + * @return This function returns PMIC_SUCCESS if successful. + * + */ +PMIC_STATUS pmic_tcled_disable(t_funlight_bank bank) +{ + unsigned int mask = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + mask = MASK_BK1_FL; + break; + case TCLED_FUN_BANK2: + mask = MASK_BK2_FL; + break; + case TCLED_FUN_BANK3: + mask = MASK_BK3_FL; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(LREG_0, 0, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function retrives tri-color LED operation mode. + * + * @param mode Pointer to Tri-color LED operation mode. + * @param bank Selected tri-color bank + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_get_mode(t_tcled_mode * mode, t_funlight_bank bank) +{ + unsigned int val; + unsigned int mask; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + mask = MASK_BK1_FL; + break; + case TCLED_FUN_BANK2: + mask = MASK_BK2_FL; + break; + case TCLED_FUN_BANK3: + mask = MASK_BK3_FL; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(LREG_0, &val, mask)); + + if (val) { + *mode = TCLED_FUN_MODE; + } else { + *mode = TCLED_IND_MODE; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets a tri-color LED channel current level in indicator mode. + * + * @param channel Tri-color LED channel. + * @param level Current level. + * @param bank Selected tri-color bank + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_ind_set_current(t_ind_channel channel, + t_tcled_cur_level level, + t_funlight_bank bank) +{ + unsigned int reg_conf = 0; + unsigned int mask; + unsigned int value; + + if (suspend_flag == 1) { + return -EBUSY; + } + + if (level > TCLED_CUR_LEVEL_4) { + return PMIC_PARAMETER_ERROR; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_IND_RED: + value = BITFVAL(BITS_CL_RED, level); + mask = BITFMASK(BITS_CL_RED); + break; + case TCLED_IND_GREEN: + value = BITFVAL(BITS_CL_GREEN, level); + mask = BITFMASK(BITS_CL_GREEN); + break; + case TCLED_IND_BLUE: + value = BITFVAL(BITS_CL_BLUE, level); + mask = BITFMASK(BITS_CL_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg_conf, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function retrives a tri-color LED channel current level + * in indicator mode. + * + * @param channel Tri-color LED channel. + * @param level Pointer to current level. + * @param bank Selected tri-color bank + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_ind_get_current(t_ind_channel channel, + t_tcled_cur_level * level, + t_funlight_bank bank) +{ + unsigned int reg_conf = 0; + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_IND_RED: + mask = BITFMASK(BITS_CL_RED); + break; + case TCLED_IND_GREEN: + mask = BITFMASK(BITS_CL_GREEN); + break; + case TCLED_IND_BLUE: + mask = BITFMASK(BITS_CL_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg_conf, &value, mask)); + + switch (channel) { + case TCLED_IND_RED: + *level = BITFEXT(value, BITS_CL_RED); + break; + case TCLED_IND_GREEN: + *level = BITFEXT(value, BITS_CL_GREEN); + break; + case TCLED_IND_BLUE: + *level = BITFEXT(value, BITS_CL_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets a tri-color LED channel blinking pattern in indication + * mode. + * + * @param channel Tri-color LED channel. + * @param pattern Blinking pattern. + * @param skip If true, skip a cycle after each cycle. + * @param bank Selected tri-color bank + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_ind_set_blink_pattern(t_ind_channel channel, + t_tcled_ind_blink_pattern pattern, + bool skip, t_funlight_bank bank) +{ + unsigned int reg_conf = 0; + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + if (skip == true) { + return PMIC_NOT_SUPPORTED; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_IND_RED: + value = BITFVAL(BITS_DC_RED, pattern); + mask = BITFMASK(BITS_DC_RED); + break; + case TCLED_IND_GREEN: + value = BITFVAL(BITS_DC_GREEN, pattern); + mask = BITFMASK(BITS_DC_GREEN); + break; + case TCLED_IND_BLUE: + value = BITFVAL(BITS_DC_BLUE, pattern); + mask = BITFMASK(BITS_DC_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg_conf, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function retrives a tri-color LED channel blinking pattern in + * indication mode. + * + * @param channel Tri-color LED channel. + * @param pattern Pointer to Blinking pattern. + * @param skip Pointer to a boolean varible indicating if skip + * @param bank Selected tri-color bank + * a cycle after each cycle. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_ind_get_blink_pattern(t_ind_channel channel, + t_tcled_ind_blink_pattern * + pattern, bool * skip, + t_funlight_bank bank) +{ + unsigned int reg_conf = 0; + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_IND_RED: + mask = BITFMASK(BITS_DC_RED); + break; + case TCLED_IND_GREEN: + mask = BITFMASK(BITS_DC_GREEN); + break; + case TCLED_IND_BLUE: + mask = BITFMASK(BITS_DC_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg_conf, &value, mask)); + + switch (channel) { + case TCLED_IND_RED: + *pattern = BITFEXT(value, BITS_DC_RED); + break; + case TCLED_IND_GREEN: + *pattern = BITFEXT(value, BITS_DC_GREEN); + break; + case TCLED_IND_BLUE: + *pattern = BITFEXT(value, BITS_DC_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets a tri-color LED channel current level in Fun Light mode. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param level Current level. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_set_current(t_funlight_bank bank, + t_funlight_channel channel, + t_tcled_cur_level level) +{ + unsigned int reg_conf = 0; + unsigned int mask; + unsigned int value; + + if (suspend_flag == 1) { + return -EBUSY; + } + + if (level > TCLED_CUR_LEVEL_4) { + return PMIC_PARAMETER_ERROR; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_FUN_CHANNEL1: + value = BITFVAL(BITS_CL_RED, level); + mask = BITFMASK(BITS_CL_RED); + break; + case TCLED_FUN_CHANNEL2: + value = BITFVAL(BITS_CL_GREEN, level); + mask = BITFMASK(BITS_CL_GREEN); + break; + case TCLED_FUN_CHANNEL3: + value = BITFVAL(BITS_CL_BLUE, level); + mask = BITFMASK(BITS_CL_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg_conf, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function retrives a tri-color LED channel current level + * in Fun Light mode. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param level Pointer to current level. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_get_current(t_funlight_bank bank, + t_funlight_channel channel, + t_tcled_cur_level * level) +{ + unsigned int reg_conf = 0; + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_FUN_CHANNEL1: + mask = BITFMASK(BITS_CL_RED); + break; + case TCLED_FUN_CHANNEL2: + mask = BITFMASK(BITS_CL_GREEN); + break; + case TCLED_FUN_CHANNEL3: + mask = BITFMASK(BITS_CL_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg_conf, &value, mask)); + + switch (channel) { + case TCLED_FUN_CHANNEL1: + *level = BITFEXT(value, BITS_CL_RED); + break; + case TCLED_FUN_CHANNEL2: + *level = BITFEXT(value, BITS_CL_GREEN); + break; + case TCLED_FUN_CHANNEL3: + *level = BITFEXT(value, BITS_CL_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets tri-color LED cycle time. + * + * @param bank Tri-color LED bank + * @param ct Cycle time. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_set_cycletime(t_funlight_bank bank, + t_tcled_fun_cycle_time ct) +{ + unsigned int reg_conf = 0; + unsigned int mask; + unsigned int value; + + if (suspend_flag == 1) { + return -EBUSY; + } + + if (ct > TC_CYCLE_TIME_4) { + return PMIC_PARAMETER_ERROR; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + value = BITFVAL(BIT_PERIOD, ct); + mask = BITFMASK(BIT_PERIOD); + + CHECK_ERROR(pmic_write_reg(reg_conf, value, mask)); + return PMIC_SUCCESS; +} + +/*! + * This function retrives tri-color LED cycle time in Fun Light mode. + * + * @param bank Tri-color LED bank + * @param ct Pointer to cycle time. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_get_cycletime(t_funlight_bank bank, + t_tcled_fun_cycle_time * ct) +{ + unsigned int reg_conf = 0; + unsigned int mask; + unsigned int value; + + if (suspend_flag == 1) { + return -EBUSY; + } + + if (*ct > TC_CYCLE_TIME_4) { + return PMIC_PARAMETER_ERROR; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + mask = BITFMASK(BIT_PERIOD); + CHECK_ERROR(pmic_read_reg(reg_conf, &value, mask)); + + *ct = BITFVAL(BIT_PERIOD, value); + + return PMIC_SUCCESS; +} + +/*! + * This function sets a tri-color LED channel duty cycle in Fun Light mode. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param dc Duty cycle. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_set_dutycycle(t_funlight_bank bank, + t_funlight_channel channel, + unsigned char dc) +{ + unsigned int reg_conf = 0; + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_FUN_CHANNEL1: + value = BITFVAL(BITS_DC_RED, dc); + mask = BITFMASK(BITS_DC_RED); + break; + case TCLED_FUN_CHANNEL2: + value = BITFVAL(BITS_DC_GREEN, dc); + mask = BITFMASK(BITS_DC_GREEN); + break; + case TCLED_FUN_CHANNEL3: + value = BITFVAL(BITS_DC_BLUE, dc); + mask = BITFMASK(BITS_DC_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg_conf, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function retrives a tri-color LED channel duty cycle in Fun Light mode. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param dc Pointer to duty cycle. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_get_dutycycle(t_funlight_bank bank, + t_funlight_channel channel, + unsigned char *dc) +{ + unsigned int reg_conf = 0; + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_FUN_CHANNEL1: + mask = BITFMASK(BITS_DC_RED); + break; + case TCLED_FUN_CHANNEL2: + mask = BITFMASK(BITS_DC_GREEN); + break; + case TCLED_FUN_CHANNEL3: + mask = BITFMASK(BITS_DC_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg_conf, &value, mask)); + + switch (channel) { + case TCLED_FUN_CHANNEL1: + *dc = BITFEXT(value, BITS_DC_RED); + break; + case TCLED_FUN_CHANNEL2: + *dc = BITFEXT(value, BITS_DC_GREEN); + break; + case TCLED_FUN_CHANNEL3: + *dc = BITFEXT(value, BITS_DC_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function initiates Blended Ramp fun light pattern. + * + * @param bank Tri-color LED bank + * @param speed Speed of pattern. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_blendedramps(t_funlight_bank bank, + t_tcled_fun_speed speed) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (speed) { + case TC_OFF: + value = BITFVAL(BITS_FUN_LIGHT, FUN_LIGHTS_OFF); + break; + case TC_SLOW: + value = BITFVAL(BITS_FUN_LIGHT, BLENDED_RAMPS_SLOW); + break; + case TC_FAST: + value = BITFVAL(BITS_FUN_LIGHT, BLENDED_RAMPS_FAST); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + mask = BITFMASK(BITS_FUN_LIGHT); + CHECK_ERROR(pmic_write_reg(LREG_0, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function initiates Saw Ramp fun light pattern. + * + * @param bank Tri-color LED bank + * @param speed Speed of pattern. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_sawramps(t_funlight_bank bank, + t_tcled_fun_speed speed) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (speed) { + case TC_OFF: + value = BITFVAL(BITS_FUN_LIGHT, FUN_LIGHTS_OFF); + break; + case TC_SLOW: + value = BITFVAL(BITS_FUN_LIGHT, SAW_RAMPS_SLOW); + break; + case TC_FAST: + value = BITFVAL(BITS_FUN_LIGHT, SAW_RAMPS_FAST); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + mask = BITFMASK(BITS_FUN_LIGHT); + CHECK_ERROR(pmic_write_reg(LREG_0, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function initiates Blended Bowtie fun light pattern. + * + * @param bank Tri-color LED bank + * @param speed Speed of pattern. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_blendedbowtie(t_funlight_bank bank, + t_tcled_fun_speed speed) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (speed) { + case TC_OFF: + value = BITFVAL(BITS_FUN_LIGHT, FUN_LIGHTS_OFF); + break; + case TC_SLOW: + value = BITFVAL(BITS_FUN_LIGHT, BLENDED_INVERSE_RAMPS_SLOW); + break; + case TC_FAST: + value = BITFVAL(BITS_FUN_LIGHT, BLENDED_INVERSE_RAMPS_FAST); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + mask = BITFMASK(BITS_FUN_LIGHT); + CHECK_ERROR(pmic_write_reg(LREG_0, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function initiates Chasing Lights fun light pattern. + * + * @param bank Tri-color LED bank + * @param pattern Chasing light pattern mode. + * @param speed Speed of pattern. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_chasinglightspattern(t_funlight_bank bank, + t_chaselight_pattern pattern, + t_tcled_fun_speed speed) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + if (pattern > BGR) { + return PMIC_PARAMETER_ERROR; + } + + switch (speed) { + case TC_OFF: + value = BITFVAL(BITS_FUN_LIGHT, FUN_LIGHTS_OFF); + break; + case TC_SLOW: + if (pattern == PMIC_RGB) { + value = + BITFVAL(BITS_FUN_LIGHT, CHASING_LIGHTS_RGB_SLOW); + } else { + value = + BITFVAL(BITS_FUN_LIGHT, CHASING_LIGHTS_BGR_SLOW); + } + break; + case TC_FAST: + if (pattern == PMIC_RGB) { + value = + BITFVAL(BITS_FUN_LIGHT, CHASING_LIGHTS_RGB_FAST); + } else { + value = + BITFVAL(BITS_FUN_LIGHT, CHASING_LIGHTS_BGR_FAST); + } + break; + default: + return PMIC_PARAMETER_ERROR; + } + + mask = BITFMASK(BITS_FUN_LIGHT); + CHECK_ERROR(pmic_write_reg(LREG_0, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function initiates Strobe Mode fun light pattern. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param speed Speed of pattern. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_strobe(t_funlight_bank bank, + t_funlight_channel channel, + t_tcled_fun_strobe_speed speed) +{ + /* not supported on mc13783 */ + + return PMIC_NOT_SUPPORTED; +} + +/*! + * This function initiates Tri-color LED brightness Ramp Up function; Ramp time + * is fixed at 1 second. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param rampup Ramp-up configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_rampup(t_funlight_bank bank, + t_funlight_channel channel, bool rampup) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + mask = LEDR1RAMPUP; + value = LEDR1RAMPUP; + break; + case TCLED_FUN_BANK2: + mask = LEDR2RAMPUP; + value = LEDR2RAMPUP; + break; + case TCLED_FUN_BANK3: + mask = LEDR3RAMPUP; + value = LEDR3RAMPUP; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_FUN_CHANNEL1: + mask = mask; + value = value; + break; + case TCLED_FUN_CHANNEL2: + mask = mask * 2; + value = value * 2; + break; + case TCLED_FUN_CHANNEL3: + mask = mask * 4; + value = value * 4; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + if (!rampup) { + value = 0; + } + + CHECK_ERROR(pmic_write_reg(LREG_1, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets Tri-color LED brightness Ramp Up function; Ramp time + * is fixed at 1 second. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param rampup Ramp-up configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_get_fun_rampup(t_funlight_bank bank, + t_funlight_channel channel, bool * rampup) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + mask = LEDR1RAMPUP; + break; + case TCLED_FUN_BANK2: + mask = LEDR2RAMPUP; + break; + case TCLED_FUN_BANK3: + mask = LEDR3RAMPUP; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_FUN_CHANNEL1: + mask = mask; + break; + case TCLED_FUN_CHANNEL2: + mask = mask * 2; + break; + case TCLED_FUN_CHANNEL3: + mask = mask * 4; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(LREG_1, &value, mask)); + if (value) { + *rampup = true; + } else { + *rampup = false; + } + + return PMIC_SUCCESS; +} + +/*! + * This function initiates Tri-color LED brightness Ramp Down function; Ramp + * time is fixed at 1 second. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param rampdown Ramp-down configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_rampdown(t_funlight_bank bank, + t_funlight_channel channel, bool rampdown) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + mask = LEDR1RAMPDOWN; + value = LEDR1RAMPDOWN; + break; + case TCLED_FUN_BANK2: + mask = LEDR2RAMPDOWN; + value = LEDR2RAMPDOWN; + break; + case TCLED_FUN_BANK3: + mask = LEDR3RAMPDOWN; + value = LEDR3RAMPDOWN; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_FUN_CHANNEL1: + mask = mask; + value = value; + break; + case TCLED_FUN_CHANNEL2: + mask = mask * 2; + value = value * 2; + break; + case TCLED_FUN_CHANNEL3: + mask = mask * 4; + value = value * 4; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + if (!rampdown) { + value = 0; + } + + CHECK_ERROR(pmic_write_reg(LREG_1, value, mask)); + return PMIC_SUCCESS; +} + +/*! + * This function initiates Tri-color LED brightness Ramp Down function; Ramp + * time is fixed at 1 second. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param rampdown Ramp-down configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_get_fun_rampdown(t_funlight_bank bank, + t_funlight_channel channel, + bool * rampdown) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + mask = LEDR1RAMPDOWN; + break; + case TCLED_FUN_BANK2: + mask = LEDR2RAMPDOWN; + break; + case TCLED_FUN_BANK3: + mask = LEDR3RAMPDOWN; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_FUN_CHANNEL1: + mask = mask; + break; + case TCLED_FUN_CHANNEL2: + mask = mask * 2; + break; + case TCLED_FUN_CHANNEL3: + mask = mask * 4; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(LREG_1, &value, mask)); + if (value) { + *rampdown = true; + } else { + *rampdown = false; + } + return PMIC_SUCCESS; +} + +/*! + * This function enables a Tri-color channel triode mode. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_triode_on(t_funlight_bank bank, + t_funlight_channel channel) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + mask = MASK_BK1_FL; + value = ENABLE_BK1_FL; + break; + case TCLED_FUN_BANK2: + mask = MASK_BK2_FL; + value = ENABLE_BK2_FL; + break; + case TCLED_FUN_BANK3: + mask = MASK_BK3_FL; + value = ENABLE_BK2_FL; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(LREG_0, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function disables a Tri-color LED channel triode mode. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_triode_off(t_funlight_bank bank, + t_funlight_channel channel) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + mask = MASK_BK1_FL; + break; + case TCLED_FUN_BANK2: + mask = MASK_BK2_FL; + break; + case TCLED_FUN_BANK3: + mask = MASK_BK3_FL; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(LREG_0, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function enables Tri-color LED edge slowing. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_enable_edge_slow(void) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + value = BITFVAL(BIT_SLEWLIMTC, 1); + mask = BITFMASK(BIT_SLEWLIMTC); + + CHECK_ERROR(pmic_write_reg(LREG_1, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function disables Tri-color LED edge slowing. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_disable_edge_slow(void) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + value = BITFVAL(BIT_SLEWLIMTC, 0); + mask = BITFMASK(BIT_SLEWLIMTC); + + CHECK_ERROR(pmic_write_reg(LREG_1, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function enables Tri-color LED half current mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_enable_half_current(void) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + value = BITFVAL(BIT_TC1HALF, 1); + mask = BITFMASK(BIT_TC1HALF); + + CHECK_ERROR(pmic_write_reg(LREG_1, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function disables Tri-color LED half current mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_disable_half_current(void) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + value = BITFVAL(BIT_TC1HALF, 0); + mask = BITFMASK(BIT_TC1HALF); + + CHECK_ERROR(pmic_write_reg(LREG_1, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function enables backlight or Tri-color LED audio modulation. + * + * @return This function returns PMIC_NOT_SUPPORTED. + */ +PMIC_STATUS pmic_tcled_enable_audio_modulation(t_led_channel channel, + t_aud_path path, + t_aud_gain gain, bool lpf_bypass) +{ + return PMIC_NOT_SUPPORTED; +} + +/*! + * This function disables backlight or Tri-color LED audio modulation. + * + * @return This function returns PMIC_NOT_SUPPORTED. + */ +PMIC_STATUS pmic_tcled_disable_audio_modulation(void) +{ + return PMIC_NOT_SUPPORTED; +} + +/*! + * This function enables the boost mode. + * Only on mc13783 2.0 or higher + * + * @param en_dis Enable or disable the boost mode + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_bklit_set_boost_mode(bool en_dis) +{ + + pmic_version_t mc13783_ver; + unsigned int mask; + unsigned int value; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + + if (suspend_flag == 1) { + return -EBUSY; + } + + value = BITFVAL(BIT_BOOSTEN, en_dis); + mask = BITFMASK(BIT_BOOSTEN); + CHECK_ERROR(pmic_write_reg(LREG_0, value, mask)); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function gets the boost mode. + * Only on mc13783 2.0 or higher + * + * @param en_dis Enable or disable the boost mode + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_bklit_get_boost_mode(bool * en_dis) +{ + pmic_version_t mc13783_ver; + unsigned int mask; + unsigned int value; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + + if (suspend_flag == 1) { + return -EBUSY; + } + mask = BITFMASK(BIT_BOOSTEN); + CHECK_ERROR(pmic_read_reg(LREG_0, &value, mask)); + *en_dis = BITFEXT(value, BIT_BOOSTEN); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function sets boost mode configuration + * Only on mc13783 2.0 or higher + * + * @param abms Define adaptive boost mode selection + * @param abr Define adaptive boost reference + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_bklit_config_boost_mode(unsigned int abms, unsigned int abr) +{ + unsigned int conf_boost = 0; + unsigned int mask; + unsigned int value; + pmic_version_t mc13783_ver; + + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + if (suspend_flag == 1) { + return -EBUSY; + } + + if (abms > MAX_BOOST_ABMS) { + return PMIC_PARAMETER_ERROR; + } + + if (abr > MAX_BOOST_ABR) { + return PMIC_PARAMETER_ERROR; + } + + conf_boost = abms | (abr << 3); + + value = BITFVAL(BITS_BOOST, conf_boost); + mask = BITFMASK(BITS_BOOST); + CHECK_ERROR(pmic_write_reg(LREG_0, value, mask)); + + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function gets boost mode configuration + * Only on mc13783 2.0 or higher + * + * @param abms Define adaptive boost mode selection + * @param abr Define adaptive boost reference + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_bklit_gets_boost_mode(unsigned int *abms, unsigned int *abr) +{ + unsigned int mask; + unsigned int value; + pmic_version_t mc13783_ver; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + if (suspend_flag == 1) { + return -EBUSY; + } + + mask = BITFMASK(BITS_BOOST_ABMS); + CHECK_ERROR(pmic_read_reg(LREG_0, &value, mask)); + *abms = BITFEXT(value, BITS_BOOST_ABMS); + + mask = BITFMASK(BITS_BOOST_ABR); + CHECK_ERROR(pmic_read_reg(LREG_0, &value, mask)); + *abr = BITFEXT(value, BITS_BOOST_ABR); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function implements IOCTL controls on a PMIC Light device. + * + + * @param inode pointer on the node + * @param file pointer on the file + * @param cmd the command + * @param arg the parameter + * @return This function returns 0 if successful. + */ +static int pmic_light_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + t_bklit_setting_param *bklit_setting = NULL; + t_tcled_enable_param *tcled_setting; + t_fun_param *fun_param; + t_tcled_ind_param *tcled_ind; + + if (_IOC_TYPE(cmd) != 'p') + return -ENOTTY; + + switch (cmd) { + case PMIC_BKLIT_TCLED_ENABLE: + pmic_bklit_tcled_master_enable(); + break; + + case PMIC_BKLIT_TCLED_DISABLE: + pmic_bklit_tcled_master_disable(); + break; + + case PMIC_BKLIT_ENABLE: + pmic_bklit_master_enable(); + break; + + case PMIC_BKLIT_DISABLE: + pmic_bklit_master_disable(); + break; + + case PMIC_SET_BKLIT: + if ((bklit_setting = kmalloc(sizeof(t_bklit_setting_param), + GFP_KERNEL)) == NULL) { + return -ENOMEM; + } + if (copy_from_user(bklit_setting, (t_bklit_setting_param *) arg, + sizeof(t_bklit_setting_param))) { + kfree(bklit_setting); + return -EFAULT; + } + + CHECK_ERROR_KFREE(pmic_bklit_set_mode(bklit_setting->channel, + bklit_setting->mode), + (kfree(bklit_setting))); + + CHECK_ERROR_KFREE(pmic_bklit_set_current(bklit_setting->channel, + bklit_setting-> + current_level), + (kfree(bklit_setting))); + CHECK_ERROR_KFREE(pmic_bklit_set_dutycycle + (bklit_setting->channel, + bklit_setting->duty_cycle), + (kfree(bklit_setting))); + CHECK_ERROR_KFREE(pmic_bklit_set_cycle_time + (bklit_setting->cycle_time), + (kfree(bklit_setting))); + CHECK_ERROR_KFREE(pmic_bklit_set_boost_mode + (bklit_setting->en_dis), + (kfree(bklit_setting))); + CHECK_ERROR_KFREE(pmic_bklit_config_boost_mode + (bklit_setting->abms, bklit_setting->abr), + (kfree(bklit_setting))); + if (bklit_setting->edge_slow != false) { + CHECK_ERROR_KFREE(pmic_bklit_enable_edge_slow(), + (kfree(bklit_setting))); + } else { + CHECK_ERROR_KFREE(pmic_bklit_disable_edge_slow(), + (kfree(bklit_setting))); + } + + kfree(bklit_setting); + break; + + case PMIC_GET_BKLIT: + if ((bklit_setting = kmalloc(sizeof(t_bklit_setting_param), + GFP_KERNEL)) == NULL) { + return -ENOMEM; + } + + if (copy_from_user(bklit_setting, (t_bklit_setting_param *) arg, + sizeof(t_bklit_setting_param))) { + kfree(bklit_setting); + return -EFAULT; + } + + CHECK_ERROR_KFREE(pmic_bklit_get_current(bklit_setting->channel, + &bklit_setting-> + current_level), + (kfree(bklit_setting))); + CHECK_ERROR_KFREE(pmic_bklit_get_cycle_time + (&bklit_setting->cycle_time), + (kfree(bklit_setting))); + CHECK_ERROR_KFREE(pmic_bklit_get_dutycycle + (bklit_setting->channel, + &bklit_setting->duty_cycle), + (kfree(bklit_setting))); + bklit_setting->strobe = BACKLIGHT_STROBE_NONE; + CHECK_ERROR_KFREE(pmic_bklit_get_mode(bklit_setting->channel, + &bklit_setting->mode), + (kfree(bklit_setting))); + CHECK_ERROR_KFREE(pmic_bklit_get_edge_slow + (&bklit_setting->edge_slow), + (kfree(bklit_setting))); + CHECK_ERROR_KFREE(pmic_bklit_get_boost_mode + (&bklit_setting->en_dis), + (kfree(bklit_setting))); + CHECK_ERROR_KFREE(pmic_bklit_gets_boost_mode + (&bklit_setting->abms, &bklit_setting->abr), + (kfree(bklit_setting))); + + if (copy_to_user((t_bklit_setting_param *) arg, bklit_setting, + sizeof(t_bklit_setting_param))) { + kfree(bklit_setting); + return -EFAULT; + } + kfree(bklit_setting); + break; + + case PMIC_RAMPUP_BKLIT: + CHECK_ERROR(pmic_bklit_rampup((t_bklit_channel) arg)); + break; + + case PMIC_RAMPDOWN_BKLIT: + CHECK_ERROR(pmic_bklit_rampdown((t_bklit_channel) arg)); + break; + + case PMIC_OFF_RAMPUP_BKLIT: + CHECK_ERROR(pmic_bklit_off_rampup((t_bklit_channel) arg)); + break; + + case PMIC_OFF_RAMPDOWN_BKLIT: + CHECK_ERROR(pmic_bklit_off_rampdown((t_bklit_channel) arg)); + break; + + case PMIC_TCLED_ENABLE: + if ((tcled_setting = kmalloc(sizeof(t_tcled_enable_param), + GFP_KERNEL)) + == NULL) { + return -ENOMEM; + } + + if (copy_from_user(tcled_setting, (t_tcled_enable_param *) arg, + sizeof(t_tcled_enable_param))) { + kfree(tcled_setting); + return -EFAULT; + } + CHECK_ERROR_KFREE(pmic_tcled_enable(tcled_setting->mode, + tcled_setting->bank), + (kfree(bklit_setting))); + break; + + case PMIC_TCLED_DISABLE: + CHECK_ERROR(pmic_tcled_disable((t_funlight_bank) arg)); + break; + + case PMIC_TCLED_PATTERN: + if ((fun_param = kmalloc(sizeof(t_fun_param), + GFP_KERNEL)) == NULL) { + return -ENOMEM; + } + if (copy_from_user(fun_param, + (t_fun_param *) arg, sizeof(t_fun_param))) { + kfree(fun_param); + return -EFAULT; + } + + switch (fun_param->pattern) { + case BLENDED_RAMPS_SLOW: + CHECK_ERROR_KFREE(pmic_tcled_fun_blendedramps + (fun_param->bank, TC_SLOW), + (kfree(fun_param))); + break; + + case BLENDED_RAMPS_FAST: + CHECK_ERROR_KFREE(pmic_tcled_fun_blendedramps + (fun_param->bank, TC_FAST), + (kfree(fun_param))); + break; + + case SAW_RAMPS_SLOW: + CHECK_ERROR_KFREE(pmic_tcled_fun_sawramps + (fun_param->bank, TC_SLOW), + (kfree(fun_param))); + break; + + case SAW_RAMPS_FAST: + CHECK_ERROR_KFREE(pmic_tcled_fun_sawramps + (fun_param->bank, TC_FAST), + (kfree(fun_param))); + break; + + case BLENDED_BOWTIE_SLOW: + CHECK_ERROR_KFREE(pmic_tcled_fun_blendedbowtie + (fun_param->bank, TC_SLOW), + (kfree(fun_param))); + break; + + case BLENDED_BOWTIE_FAST: + CHECK_ERROR_KFREE(pmic_tcled_fun_blendedbowtie + (fun_param->bank, TC_FAST), + (kfree(fun_param))); + break; + + case STROBE_SLOW: + CHECK_ERROR_KFREE(pmic_tcled_fun_strobe + (fun_param->bank, fun_param->channel, + TC_STROBE_SLOW), (kfree(fun_param))); + break; + + case STROBE_FAST: + CHECK_ERROR_KFREE(pmic_tcled_fun_strobe + (fun_param->bank, + fun_param->channel, TC_STROBE_SLOW), + (kfree(fun_param))); + break; + + case CHASING_LIGHT_RGB_SLOW: + CHECK_ERROR_KFREE(pmic_tcled_fun_chasinglightspattern + (fun_param->bank, PMIC_RGB, TC_SLOW), + (kfree(fun_param))); + break; + + case CHASING_LIGHT_RGB_FAST: + CHECK_ERROR_KFREE(pmic_tcled_fun_chasinglightspattern + (fun_param->bank, PMIC_RGB, TC_FAST), + (kfree(fun_param))); + break; + + case CHASING_LIGHT_BGR_SLOW: + CHECK_ERROR_KFREE(pmic_tcled_fun_chasinglightspattern + (fun_param->bank, BGR, TC_SLOW), + (kfree(fun_param))); + break; + + case CHASING_LIGHT_BGR_FAST: + CHECK_ERROR_KFREE(pmic_tcled_fun_chasinglightspattern + (fun_param->bank, BGR, TC_FAST), + (kfree(fun_param))); + break; + } + + kfree(fun_param); + break; + + case PMIC_SET_TCLED: + if ((tcled_ind = kmalloc(sizeof(t_tcled_ind_param), GFP_KERNEL)) + == NULL) { + return -ENOMEM; + } + + if (copy_from_user(tcled_ind, (t_tcled_ind_param *) arg, + sizeof(t_tcled_ind_param))) { + kfree(tcled_ind); + return -EFAULT; + } + CHECK_ERROR_KFREE(pmic_tcled_ind_set_current(tcled_ind->channel, + tcled_ind->level, + tcled_ind->bank), + (kfree(tcled_ind))); + CHECK_ERROR_KFREE(pmic_tcled_ind_set_blink_pattern + (tcled_ind->channel, tcled_ind->pattern, + tcled_ind->skip, tcled_ind->bank), + (kfree(tcled_ind))); + CHECK_ERROR_KFREE(pmic_tcled_fun_rampup + (tcled_ind->bank, tcled_ind->channel, + tcled_ind->rampup), (kfree(tcled_ind))); + CHECK_ERROR_KFREE(pmic_tcled_fun_rampdown + (tcled_ind->bank, tcled_ind->channel, + tcled_ind->rampdown), (kfree(tcled_ind))); + if (tcled_ind->half_current) { + CHECK_ERROR_KFREE(pmic_tcled_enable_half_current(), + (kfree(tcled_ind))); + } else { + CHECK_ERROR_KFREE(pmic_tcled_disable_half_current(), + (kfree(tcled_ind))); + } + + kfree(tcled_ind); + break; + + case PMIC_GET_TCLED: + if ((tcled_ind = kmalloc(sizeof(t_tcled_ind_param), GFP_KERNEL)) + == NULL) { + return -ENOMEM; + } + if (copy_from_user(tcled_ind, (t_tcled_ind_param *) arg, + sizeof(t_tcled_ind_param))) { + kfree(tcled_ind); + return -EFAULT; + } + CHECK_ERROR_KFREE(pmic_tcled_ind_get_current(tcled_ind->channel, + &tcled_ind->level, + tcled_ind->bank), + (kfree(tcled_ind))); + CHECK_ERROR_KFREE(pmic_tcled_ind_get_blink_pattern + (tcled_ind->channel, &tcled_ind->pattern, + &tcled_ind->skip, tcled_ind->bank), + (kfree(tcled_ind))); + CHECK_ERROR_KFREE(pmic_tcled_get_fun_rampup + (tcled_ind->bank, tcled_ind->channel, + &tcled_ind->rampup), (kfree(tcled_ind))); + CHECK_ERROR_KFREE(pmic_tcled_get_fun_rampdown + (tcled_ind->bank, tcled_ind->channel, + &tcled_ind->rampdown), (kfree(tcled_ind))); + if (copy_to_user + ((t_tcled_ind_param *) arg, tcled_ind, + sizeof(t_tcled_ind_param))) { + return -EFAULT; + } + kfree(tcled_ind); + + break; + + default: + return -EINVAL; + } + return 0; +} + +/*! + * This function initialize Light registers of mc13783 with 0. + * + * @return This function returns 0 if successful. + */ +int pmic_light_init_reg(void) +{ + CHECK_ERROR(pmic_write_reg(LREG_0, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(LREG_1, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(LREG_2, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(LREG_3, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(LREG_4, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(LREG_5, 0, PMIC_ALL_BITS)); + return 0; +} + +/*! + * This function implements the open method on a mc13783 light device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int pmic_light_open(struct inode *inode, struct file *file) +{ + while (suspend_flag == 1) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, (suspend_flag == 0))) { + return -ERESTARTSYS; + } + } + return 0; +} + +/*! + * This function implements the release method on a mc13783 light device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int pmic_light_release(struct inode *inode, struct file *file) +{ + while (suspend_flag == 1) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, (suspend_flag == 0))) { + return -ERESTARTSYS; + } + } + return 0; +} + +static struct file_operations pmic_light_fops = { + .owner = THIS_MODULE, + .ioctl = pmic_light_ioctl, + .open = pmic_light_open, + .release = pmic_light_release, +}; + +static int pmic_light_remove(struct platform_device *pdev) +{ + device_destroy(pmic_light_class, MKDEV(pmic_light_major, 0)); + class_destroy(pmic_light_class); + unregister_chrdev(pmic_light_major, "pmic_light"); + return 0; +} + +static int pmic_light_probe(struct platform_device *pdev) +{ + int ret = 0; + struct device *temp_class; + + while (suspend_flag == 1) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, (suspend_flag == 0))) { + return -ERESTARTSYS; + } + } + pmic_light_major = register_chrdev(0, "pmic_light", &pmic_light_fops); + + if (pmic_light_major < 0) { + printk(KERN_ERR "Unable to get a major for pmic_light\n"); + return pmic_light_major; + } + init_waitqueue_head(&suspendq); + + pmic_light_class = class_create(THIS_MODULE, "pmic_light"); + if (IS_ERR(pmic_light_class)) { + printk(KERN_ERR "Error creating pmic_light class.\n"); + ret = PTR_ERR(pmic_light_class); + goto err_out1; + } + + temp_class = device_create(pmic_light_class, NULL, + MKDEV(pmic_light_major, 0), + "pmic_light"); + if (IS_ERR(temp_class)) { + printk(KERN_ERR "Error creating pmic_light class device.\n"); + ret = PTR_ERR(temp_class); + goto err_out2; + } + + ret = pmic_light_init_reg(); + if (ret != PMIC_SUCCESS) { + goto err_out3; + } + + printk(KERN_INFO "PMIC Light successfully loaded\n"); + return ret; + + err_out3: + device_destroy(pmic_light_class, MKDEV(pmic_light_major, 0)); + err_out2: + class_destroy(pmic_light_class); + err_out1: + unregister_chrdev(pmic_light_major, "pmic_light"); + return ret; +} + +static struct platform_driver pmic_light_driver_ldm = { + .driver = { + .name = "pmic_light", + }, + .suspend = pmic_light_suspend, + .resume = pmic_light_resume, + .probe = pmic_light_probe, + .remove = pmic_light_remove, +}; + +/* + * Initialization and Exit + */ + +static int __init pmic_light_init(void) +{ + pr_debug("PMIC Light driver loading...\n"); + return platform_driver_register(&pmic_light_driver_ldm); +} +static void __exit pmic_light_exit(void) +{ + platform_driver_unregister(&pmic_light_driver_ldm); + pr_debug("PMIC Light driver successfully unloaded\n"); +} + +/* + * Module entry points + */ + +subsys_initcall(pmic_light_init); +module_exit(pmic_light_exit); + +MODULE_DESCRIPTION("PMIC_LIGHT"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_light_defs.h linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_light_defs.h --- linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_light_defs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_light_defs.h 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,144 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_light_defs.h + * @brief This is the internal header PMIC(mc13783) Light and Backlight driver. + * + * @ingroup PMIC_LIGHT + */ + +#ifndef __MC13783_LIGHT_DEFS_H__ +#define __MC13783_LIGHT_DEFS_H__ + +#define LREG_0 REG_LED_CONTROL_0 +#define LREG_1 REG_LED_CONTROL_1 +#define LREG_2 REG_LED_CONTROL_2 +#define LREG_3 REG_LED_CONTROL_3 +#define LREG_4 REG_LED_CONTROL_4 +#define LREG_5 REG_LED_CONTROL_5 + +/* REG_LED_CONTROL_0 */ + +#define BIT_LEDEN_LSH 0 +#define BIT_LEDEN_WID 1 +#define MASK_TRIODE_MAIN_BL 0x080 +#define INDEX_AUXILIARY 1 +#define INDEX_KEYPAD 2 +#define BITS_FUN_LIGHT_LSH 17 +#define BITS_FUN_LIGHT_WID 4 +#define MASK_FUN_LIGHT 0x1E0000 +#define MASK_BK1_FL 0x200000 +#define ENABLE_BK1_FL 0x200000 +#define MASK_BK2_FL 0x400000 +#define ENABLE_BK2_FL 0x400000 +#define MASK_BK3_FL 0x800000 +#define ENABLE_BK3_FL 0x800000 +#define BIT_UP_MAIN_BL_LSH 1 +#define BIT_UP_MAIN_BL_WID 1 +#define BIT_UP_AUX_BL_LSH 2 +#define BIT_UP_AUX_BL_WID 1 +#define BIT_UP_KEY_BL_LSH 3 +#define BIT_UP_KEY_BL_WID 1 +#define BIT_DOWN_MAIN_BL_LSH 4 +#define BIT_DOWN_MAIN_BL_WID 1 +#define BIT_DOWN_AUX_BL_LSH 5 +#define BIT_DOWN_AUX_BL_WID 1 +#define BIT_DOWN_KEY_BL_LSH 6 +#define BIT_DOWN_KEY_BL_WID 1 +#define BIT_TRIODE_MAIN_BL_LSH 7 +#define BIT_TRIODE_MAIN_BL_WID 1 +#define BIT_TRIODE_AUX_BL_LSH 8 +#define BIT_TRIODE_AUX_BL_WID 1 +#define BIT_TRIODE_KEY_BL_LSH 9 +#define BIT_TRIODE_KEY_BL_WID 1 + +#define BIT_BOOSTEN_LSH 10 +#define BIT_BOOSTEN_WID 1 +#define BITS_BOOST_LSH 11 +#define BITS_BOOST_WID 5 +#define BITS_BOOST_ABMS_LSH 11 +#define BITS_BOOST_ABMS_WID 3 +#define BITS_BOOST_ABR_LSH 14 +#define BITS_BOOST_ABR_WID 2 + +#define MAX_BOOST_ABMS 7 +#define MAX_BOOST_ABR 3 + +/* REG_LED_CONTROL_1 */ + +#define BIT_SLEWLIMTC_LSH 23 +#define BIT_SLEWLIMTC_WID 1 +#define BIT_TC1HALF_LSH 18 +#define BIT_TC1HALF_WID 1 +#define LEDR1RAMPUP 0x000001 +#define LEDR2RAMPUP 0x000040 +#define LEDR3RAMPUP 0x001000 +#define LEDR1RAMPDOWN 0x000008 +#define LEDR2RAMPDOWN 0x000200 +#define LEDR3RAMPDOWN 0x008000 + +/* REG_LED_CONTROL_2 */ + +#define BIT_SLEWLIMBL_LSH 23 +#define BIT_SLEWLIMBL_WID 1 +#define BIT_DUTY_CYCLE 9 +#define MASK_DUTY_CYCLE 0x001E00 +#define INDEX_AUX 4 +#define INDEX_KYD 8 +#define BIT_CL_MAIN_LSH 0 +#define BIT_CL_MAIN_WID 3 +#define BIT_CL_AUX_LSH 3 +#define BIT_CL_AUX_WID 3 +#define BIT_CL_KEY_LSH 6 +#define BIT_CL_KEY_WID 3 + +/* REG_LED_CONTROL_3 4 5 */ +#define BITS_CL_RED_LSH 0 +#define BITS_CL_RED_WID 2 +#define BITS_CL_GREEN_LSH 2 +#define BITS_CL_GREEN_WID 2 +#define BITS_CL_BLUE_LSH 4 +#define BITS_CL_BLUE_WID 2 +#define BITS_DC_RED_LSH 6 +#define BITS_DC_RED_WID 5 +#define BITS_DC_GREEN_LSH 11 +#define BITS_DC_GREEN_WID 5 +#define BITS_DC_BLUE_LSH 16 +#define BITS_DC_BLUE_WID 5 +#define BIT_PERIOD_LSH 21 +#define BIT_PERIOD_WID 2 + +#define DUTY_CYCLE_MAX 31 + +/* Fun light pattern */ +#define BLENDED_RAMPS_SLOW 0 +#define BLENDED_RAMPS_FAST 1 +#define SAW_RAMPS_SLOW 2 +#define SAW_RAMPS_FAST 3 +#define BLENDED_INVERSE_RAMPS_SLOW 4 +#define BLENDED_INVERSE_RAMPS_FAST 5 +#define CHASING_LIGHTS_RGB_SLOW 6 +#define CHASING_LIGHTS_RGB_FAST 7 +#define CHASING_LIGHTS_BGR_SLOW 8 +#define CHASING_LIGHTS_BGR_FAST 9 +#define FUN_LIGHTS_OFF 15 + +/*! + * This function initialize Light registers of mc13783 with 0. + * + * @return This function returns 0 if successful. + */ +int pmic_light_init_reg(void); + +#endif /* __MC13783_LIGHT_DEFS_H__ */ diff -urN linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_power.c linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_power.c --- linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_power.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_power.c 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,3140 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_power.c + * @brief This is the main file of PMIC(mc13783) Power driver. + * + * @ingroup PMIC_POWER + */ + +/* + * Includes + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pmic_power_defs.h" + +#ifdef CONFIG_MXC_HWEVENT +#include +#endif + +#include + +#define MC13783_REGCTRL_GPOx_MASK 0x18000 + +static bool VBKUP1_EN = false; +static bool VBKUP2_EN = false; + +/* + * Power Pmic API + */ + +/* EXPORTED FUNCTIONS */ +EXPORT_SYMBOL(pmic_power_off); +EXPORT_SYMBOL(pmic_power_set_pc_config); +EXPORT_SYMBOL(pmic_power_get_pc_config); +EXPORT_SYMBOL(pmic_power_regulator_on); +EXPORT_SYMBOL(pmic_power_regulator_off); +EXPORT_SYMBOL(pmic_power_regulator_set_voltage); +EXPORT_SYMBOL(pmic_power_regulator_get_voltage); +EXPORT_SYMBOL(pmic_power_regulator_set_config); +EXPORT_SYMBOL(pmic_power_regulator_get_config); +EXPORT_SYMBOL(pmic_power_vbkup2_auto_en); +EXPORT_SYMBOL(pmic_power_get_vbkup2_auto_state); +EXPORT_SYMBOL(pmic_power_bat_det_en); +EXPORT_SYMBOL(pmic_power_get_bat_det_state); +EXPORT_SYMBOL(pmic_power_vib_pin_en); +EXPORT_SYMBOL(pmic_power_gets_vib_pin_state); +EXPORT_SYMBOL(pmic_power_get_power_mode_sense); +EXPORT_SYMBOL(pmic_power_set_regen_assig); +EXPORT_SYMBOL(pmic_power_get_regen_assig); +EXPORT_SYMBOL(pmic_power_set_regen_inv); +EXPORT_SYMBOL(pmic_power_get_regen_inv); +EXPORT_SYMBOL(pmic_power_esim_v_en); +EXPORT_SYMBOL(pmic_power_gets_esim_v_state); +EXPORT_SYMBOL(pmic_power_set_auto_reset_en); +EXPORT_SYMBOL(pmic_power_get_auto_reset_en); +EXPORT_SYMBOL(pmic_power_set_conf_button); +EXPORT_SYMBOL(pmic_power_get_conf_button); +EXPORT_SYMBOL(pmic_power_event_sub); +EXPORT_SYMBOL(pmic_power_event_unsub); + +/*! + * This function is called to put the power in a low power state. + * Switching off the platform cannot be decided by + * the power module. It has to be handled by the + * client application. + * + * @param pdev the device structure used to give information on which power + * device (0 through 3 channels) to suspend + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int pmic_power_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +}; + +/*! + * This function is called to resume the power from a low power state. + * + * @param pdev the device structure used to give information on which power + * device (0 through 3 channels) to suspend + * + * @return The function always returns 0. + */ +static int pmic_power_resume(struct platform_device *pdev) +{ + return 0; +}; + +/*! + * This function sets user power off in power control register and thus powers + * off the phone. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +void pmic_power_off(void) +{ + unsigned int mask, value; + + mask = BITFMASK(MC13783_PWRCTRL_USER_OFF_SPI); + value = BITFVAL(MC13783_PWRCTRL_USER_OFF_SPI, + MC13783_PWRCTRL_USER_OFF_SPI_ENABLE); + + pmic_write_reg(REG_POWER_CONTROL_0, value, mask); +} + +/*! + * This function sets the power control configuration. + * + * @param pc_config power control configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_set_pc_config(t_pc_config * pc_config) +{ + unsigned int pwrctrl_val_reg0 = 0; + unsigned int pwrctrl_val_reg1 = 0; + unsigned int pwrctrl_mask_reg0 = 0; + unsigned int pwrctrl_mask_reg1 = 0; + + if (pc_config == NULL) { + return PMIC_PARAMETER_ERROR; + } + + if (pc_config->pc_enable != false) { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_PCEN, + MC13783_PWRCTRL_PCEN_ENABLE); + pwrctrl_val_reg1 |= BITFVAL(MC13783_PWRCTRL_PCT, + pc_config->pc_timer); + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_PCEN, + MC13783_PWRCTRL_PCEN_DISABLE); + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_PCEN); + pwrctrl_mask_reg1 |= BITFMASK(MC13783_PWRCTRL_PCT); + + if (pc_config->pc_count_enable != false) { + + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_PC_COUNT_EN, + MC13783_PWRCTRL_PC_COUNT_EN_ENABLE); + pwrctrl_val_reg1 |= BITFVAL(MC13783_PWRCTRL_PC_COUNT, + pc_config->pc_count); + pwrctrl_val_reg1 |= BITFVAL(MC13783_PWRCTRL_PC_MAX_CNT, + pc_config->pc_max_count); + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_PC_COUNT_EN, + MC13783_PWRCTRL_PC_COUNT_EN_DISABLE); + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_PC_COUNT_EN); + pwrctrl_mask_reg1 |= BITFMASK(MC13783_PWRCTRL_PC_MAX_CNT) | + BITFMASK(MC13783_PWRCTRL_PC_COUNT); + + if (pc_config->warm_enable != false) { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_WARM_EN, + MC13783_PWRCTRL_WARM_EN_ENABLE); + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_WARM_EN, + MC13783_PWRCTRL_WARM_EN_DISABLE); + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_WARM_EN); + + if (pc_config->user_off_pc != false) { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_USER_OFF_PC, + MC13783_PWRCTRL_USER_OFF_PC_ENABLE); + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_WARM_EN, + MC13783_PWRCTRL_USER_OFF_PC_DISABLE); + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_USER_OFF_PC); + + if (pc_config->clk_32k_user_off != false) { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_32OUT_USER_OFF, + MC13783_PWRCTRL_32OUT_USER_OFF_ENABLE); + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_32OUT_USER_OFF, + MC13783_PWRCTRL_32OUT_USER_OFF_DISABLE); + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_32OUT_USER_OFF); + + if (pc_config->clk_32k_enable != false) { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_32OUT_EN, + MC13783_PWRCTRL_32OUT_EN_ENABLE); + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_32OUT_EN, + MC13783_PWRCTRL_32OUT_EN_DISABLE); + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_32OUT_EN); + + if (pc_config->en_vbkup1 != false) { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP1_EN, + MC13783_PWRCTRL_VBKUP_ENABLE); + VBKUP1_EN = true; + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP1_EN, + MC13783_PWRCTRL_VBKUP_DISABLE); + VBKUP1_EN = false; + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_VBKUP1_EN); + + if (pc_config->en_vbkup2 != false) { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP2_EN, + MC13783_PWRCTRL_VBKUP_ENABLE); + VBKUP2_EN = true; + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP2_EN, + MC13783_PWRCTRL_VBKUP_DISABLE); + VBKUP2_EN = false; + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_VBKUP2_EN); + + if (pc_config->auto_en_vbkup1 != false) { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP1_AUTO_EN, + MC13783_PWRCTRL_VBKUP_ENABLE); + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP1_AUTO_EN, + MC13783_PWRCTRL_VBKUP_DISABLE); + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_VBKUP1_AUTO_EN); + + if (pc_config->auto_en_vbkup2 != false) { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP2_AUTO_EN, + MC13783_PWRCTRL_VBKUP_ENABLE); + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP2_AUTO_EN, + MC13783_PWRCTRL_VBKUP_DISABLE); + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_VBKUP2_AUTO_EN); + + if (VBKUP1_EN != false) { + if (pc_config->vhold_voltage > 3 + || pc_config->vhold_voltage < 0) { + return PMIC_PARAMETER_ERROR; + } else { + + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP1, + pc_config->vhold_voltage); + } + } + if (VBKUP2_EN != false) { + if (pc_config->vhold_voltage > 3 + || pc_config->vhold_voltage < 0) { + return PMIC_PARAMETER_ERROR; + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP2, + pc_config->vhold_voltage2); + } + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_VBKUP1) | + BITFMASK(MC13783_PWRCTRL_VBKUP2); + + if (pc_config->mem_allon != false) { + pwrctrl_val_reg1 |= BITFVAL(MC13783_PWRCTRL_MEM_ALLON, + MC13783_PWRCTRL_MEM_ALLON_ENABLE); + pwrctrl_val_reg1 |= BITFVAL(MC13783_PWRCTRL_MEM_TMR, + pc_config->mem_timer); + } else { + pwrctrl_val_reg1 |= BITFVAL(MC13783_PWRCTRL_MEM_ALLON, + MC13783_PWRCTRL_MEM_ALLON_DISABLE); + } + pwrctrl_mask_reg1 |= BITFMASK(MC13783_PWRCTRL_MEM_ALLON) | + BITFMASK(MC13783_PWRCTRL_MEM_TMR); + + CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_0, + pwrctrl_val_reg0, pwrctrl_mask_reg0)); + CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_1, + pwrctrl_val_reg1, pwrctrl_mask_reg1)); + + return PMIC_SUCCESS; +} + +/*! + * This function retrives the power control configuration. + * + * @param pc_config pointer to power control configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_get_pc_config(t_pc_config * pc_config) +{ + unsigned int pwrctrl_val_reg0 = 0; + unsigned int pwrctrl_val_reg1 = 0; + + if (pc_config == NULL) { + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(REG_POWER_CONTROL_0, + &pwrctrl_val_reg0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_read_reg(REG_POWER_CONTROL_1, + &pwrctrl_val_reg1, PMIC_ALL_BITS)); + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_PCEN) + == MC13783_PWRCTRL_PCEN_ENABLE) { + pc_config->pc_enable = true; + pc_config->pc_timer = BITFEXT(pwrctrl_val_reg1, + MC13783_PWRCTRL_PCT); + + } else { + pc_config->pc_enable = false; + pc_config->pc_timer = 0; + } + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_PC_COUNT_EN) + == MC13783_PWRCTRL_PCEN_ENABLE) { + pc_config->pc_count_enable = true; + pc_config->pc_count = BITFEXT(pwrctrl_val_reg1, + MC13783_PWRCTRL_PC_COUNT); + pc_config->pc_max_count = BITFEXT(pwrctrl_val_reg1, + MC13783_PWRCTRL_PC_MAX_CNT); + } else { + pc_config->pc_count_enable = false; + pc_config->pc_count = 0; + pc_config->pc_max_count = 0; + } + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_WARM_EN) + == MC13783_PWRCTRL_WARM_EN_ENABLE) { + pc_config->warm_enable = true; + } else { + pc_config->warm_enable = false; + } + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_USER_OFF_PC) + == MC13783_PWRCTRL_USER_OFF_PC_ENABLE) { + pc_config->user_off_pc = true; + } else { + pc_config->user_off_pc = false; + } + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_32OUT_USER_OFF) + == MC13783_PWRCTRL_32OUT_USER_OFF_ENABLE) { + pc_config->clk_32k_user_off = true; + } else { + pc_config->clk_32k_user_off = false; + } + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_32OUT_EN) + == MC13783_PWRCTRL_32OUT_EN_ENABLE) { + pc_config->clk_32k_enable = true; + } else { + pc_config->clk_32k_enable = false; + } + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_VBKUP1_AUTO_EN) + == MC13783_PWRCTRL_VBKUP_ENABLE) { + pc_config->auto_en_vbkup1 = true; + } else { + pc_config->auto_en_vbkup1 = false; + } + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_VBKUP2_AUTO_EN) + == MC13783_PWRCTRL_VBKUP_ENABLE) { + pc_config->auto_en_vbkup2 = true; + } else { + pc_config->auto_en_vbkup2 = false; + } + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_VBKUP1_EN) + == MC13783_PWRCTRL_VBKUP_ENABLE) { + pc_config->en_vbkup1 = true; + pc_config->vhold_voltage = BITFEXT(pwrctrl_val_reg0, + MC13783_PWRCTRL_VBKUP1); + } else { + pc_config->en_vbkup1 = false; + pc_config->vhold_voltage = 0; + } + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_VBKUP2_EN) + == MC13783_PWRCTRL_VBKUP_ENABLE) { + pc_config->en_vbkup2 = true; + pc_config->vhold_voltage2 = BITFEXT(pwrctrl_val_reg0, + MC13783_PWRCTRL_VBKUP2); + } else { + pc_config->en_vbkup2 = false; + pc_config->vhold_voltage2 = 0; + } + + if (BITFEXT(pwrctrl_val_reg1, MC13783_PWRCTRL_MEM_ALLON) == + MC13783_PWRCTRL_MEM_ALLON_ENABLE) { + pc_config->mem_allon = true; + pc_config->mem_timer = BITFEXT(pwrctrl_val_reg1, + MC13783_PWRCTRL_MEM_TMR); + } else { + pc_config->mem_allon = false; + pc_config->mem_timer = 0; + } + + return PMIC_SUCCESS; +} + +/*! + * This function turns on a regulator. + * + * @param regulator The regulator to be truned on. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_on(t_pmic_regulator regulator) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_PLL: + reg_val = BITFVAL(MC13783_SWCTRL_PLL_EN, + MC13783_SWCTRL_PLL_EN_ENABLE); + reg_mask = BITFMASK(MC13783_SWCTRL_PLL_EN); + reg = REG_SWITCHERS_4; + break; + case SW_SW3: + reg_val = BITFVAL(MC13783_SWCTRL_SW3_EN, + MC13783_SWCTRL_SW3_EN_ENABLE); + reg_mask = BITFMASK(MC13783_SWCTRL_SW3_EN); + reg = REG_SWITCHERS_5; + break; + case REGU_VAUDIO: + reg_val = BITFVAL(MC13783_REGCTRL_VAUDIO_EN, + MC13783_REGCTRL_VAUDIO_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VAUDIO_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VIOHI: + reg_val = BITFVAL(MC13783_REGCTRL_VIOHI_EN, + MC13783_REGCTRL_VIOHI_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VIOHI_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VIOLO: + reg_val = BITFVAL(MC13783_REGCTRL_VIOLO_EN, + MC13783_REGCTRL_VIOLO_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VIOLO_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VDIG: + reg_val = BITFVAL(MC13783_REGCTRL_VDIG_EN, + MC13783_REGCTRL_VDIG_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VDIG_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VGEN: + reg_val = BITFVAL(MC13783_REGCTRL_VGEN_EN, + MC13783_REGCTRL_VGEN_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VGEN_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFDIG: + reg_val = BITFVAL(MC13783_REGCTRL_VRFDIG_EN, + MC13783_REGCTRL_VRFDIG_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFDIG_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFREF: + reg_val = BITFVAL(MC13783_REGCTRL_VRFREF_EN, + MC13783_REGCTRL_VRFREF_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFREF_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFCP: + reg_val = BITFVAL(MC13783_REGCTRL_VRFCP_EN, + MC13783_REGCTRL_VRFCP_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFCP_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VSIM: + reg_val = BITFVAL(MC13783_REGCTRL_VSIM_EN, + MC13783_REGCTRL_VSIM_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VSIM_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VESIM: + reg_val = BITFVAL(MC13783_REGCTRL_VESIM_EN, + MC13783_REGCTRL_VESIM_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VESIM_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VCAM: + reg_val = BITFVAL(MC13783_REGCTRL_VCAM_EN, + MC13783_REGCTRL_VCAM_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VCAM_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRFBG: + reg_val = BITFVAL(MC13783_REGCTRL_VRFBG_EN, + MC13783_REGCTRL_VRFBG_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFBG_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VVIB: + reg_val = BITFVAL(MC13783_REGCTRL_VVIB_EN, + MC13783_REGCTRL_VVIB_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VVIB_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRF1: + reg_val = BITFVAL(MC13783_REGCTRL_VRF1_EN, + MC13783_REGCTRL_VRF1_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRF1_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRF2: + reg_val = BITFVAL(MC13783_REGCTRL_VRF2_EN, + MC13783_REGCTRL_VRF2_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRF2_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VMMC1: + reg_val = BITFVAL(MC13783_REGCTRL_VMMC1_EN, + MC13783_REGCTRL_VMMC1_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VMMC1_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VMMC2: + reg_val = BITFVAL(MC13783_REGCTRL_VMMC2_EN, + MC13783_REGCTRL_VMMC2_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VMMC2_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_GPO1: + reg_val = BITFVAL(MC13783_REGCTRL_GPO1_EN, + MC13783_REGCTRL_GPO1_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_GPO1_EN); + reg = REG_POWER_MISCELLANEOUS; + break; + case REGU_GPO2: + reg_val = BITFVAL(MC13783_REGCTRL_GPO2_EN, + MC13783_REGCTRL_GPO2_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_GPO2_EN); + reg = REG_POWER_MISCELLANEOUS; + break; + case REGU_GPO3: + reg_val = BITFVAL(MC13783_REGCTRL_GPO3_EN, + MC13783_REGCTRL_GPO3_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_GPO3_EN); + reg = REG_POWER_MISCELLANEOUS; + break; + case REGU_GPO4: + reg_val = BITFVAL(MC13783_REGCTRL_GPO4_EN, + MC13783_REGCTRL_GPO4_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_GPO4_EN); + reg = REG_POWER_MISCELLANEOUS; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function turns off a regulator. + * + * @param regulator The regulator to be truned off. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_off(t_pmic_regulator regulator) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_PLL: + reg_val = BITFVAL(MC13783_SWCTRL_PLL_EN, + MC13783_SWCTRL_PLL_EN_DISABLE); + reg_mask = BITFMASK(MC13783_SWCTRL_PLL_EN); + reg = REG_SWITCHERS_4; + break; + case SW_SW3: + reg_val = BITFVAL(MC13783_SWCTRL_SW3_EN, + MC13783_SWCTRL_SW3_EN_DISABLE); + reg_mask = BITFMASK(MC13783_SWCTRL_SW3_EN); + reg = REG_SWITCHERS_5; + break; + case REGU_VAUDIO: + reg_val = BITFVAL(MC13783_REGCTRL_VAUDIO_EN, + MC13783_REGCTRL_VAUDIO_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VAUDIO_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VIOHI: + reg_val = BITFVAL(MC13783_REGCTRL_VIOHI_EN, + MC13783_REGCTRL_VIOHI_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VIOHI_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VIOLO: + reg_val = BITFVAL(MC13783_REGCTRL_VIOLO_EN, + MC13783_REGCTRL_VIOLO_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VIOLO_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VDIG: + reg_val = BITFVAL(MC13783_REGCTRL_VDIG_EN, + MC13783_REGCTRL_VDIG_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VDIG_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VGEN: + reg_val = BITFVAL(MC13783_REGCTRL_VGEN_EN, + MC13783_REGCTRL_VGEN_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VGEN_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFDIG: + reg_val = BITFVAL(MC13783_REGCTRL_VRFDIG_EN, + MC13783_REGCTRL_VRFDIG_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFDIG_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFREF: + reg_val = BITFVAL(MC13783_REGCTRL_VRFREF_EN, + MC13783_REGCTRL_VRFREF_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFREF_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFCP: + reg_val = BITFVAL(MC13783_REGCTRL_VRFCP_EN, + MC13783_REGCTRL_VRFCP_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFCP_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VSIM: + reg_val = BITFVAL(MC13783_REGCTRL_VSIM_EN, + MC13783_REGCTRL_VSIM_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VSIM_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VESIM: + reg_val = BITFVAL(MC13783_REGCTRL_VESIM_EN, + MC13783_REGCTRL_VESIM_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VESIM_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VCAM: + reg_val = BITFVAL(MC13783_REGCTRL_VCAM_EN, + MC13783_REGCTRL_VCAM_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VCAM_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRFBG: + reg_val = BITFVAL(MC13783_REGCTRL_VRFBG_EN, + MC13783_REGCTRL_VRFBG_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFBG_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VVIB: + reg_val = BITFVAL(MC13783_REGCTRL_VVIB_EN, + MC13783_REGCTRL_VVIB_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VVIB_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRF1: + reg_val = BITFVAL(MC13783_REGCTRL_VRF1_EN, + MC13783_REGCTRL_VRF1_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRF1_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRF2: + reg_val = BITFVAL(MC13783_REGCTRL_VRF2_EN, + MC13783_REGCTRL_VRF2_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRF2_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VMMC1: + reg_val = BITFVAL(MC13783_REGCTRL_VMMC1_EN, + MC13783_REGCTRL_VMMC1_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VMMC1_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VMMC2: + reg_val = BITFVAL(MC13783_REGCTRL_VMMC2_EN, + MC13783_REGCTRL_VMMC2_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VMMC2_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_GPO1: + reg_val = BITFVAL(MC13783_REGCTRL_GPO1_EN, + MC13783_REGCTRL_GPO1_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_GPO1_EN); + reg = REG_POWER_MISCELLANEOUS; + break; + case REGU_GPO2: + reg_val = BITFVAL(MC13783_REGCTRL_GPO2_EN, + MC13783_REGCTRL_GPO2_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_GPO2_EN); + reg = REG_POWER_MISCELLANEOUS; + break; + case REGU_GPO3: + reg_val = BITFVAL(MC13783_REGCTRL_GPO3_EN, + MC13783_REGCTRL_GPO3_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_GPO3_EN); + reg = REG_POWER_MISCELLANEOUS; + break; + case REGU_GPO4: + reg_val = BITFVAL(MC13783_REGCTRL_GPO4_EN, + MC13783_REGCTRL_GPO4_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_GPO4_EN); + reg = REG_POWER_MISCELLANEOUS; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function sets the regulator output voltage. + * + * @param regulator The regulator to be configured. + * @param voltage The regulator output voltage. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_set_voltage(t_pmic_regulator regulator, + t_regulator_voltage voltage) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + if ((voltage.sw1a < SW1A_0_9V) || (voltage.sw1a > SW1A_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW1A, voltage.sw1a); + reg_mask = BITFMASK(MC13783_SWSET_SW1A); + reg = REG_SWITCHERS_0; + break; + case SW_SW1B: + if ((voltage.sw1b < SW1B_0_9V) || (voltage.sw1b > SW1B_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW1B, voltage.sw1b); + reg_mask = BITFMASK(MC13783_SWSET_SW1B); + reg = REG_SWITCHERS_1; + break; + case SW_SW2A: + if ((voltage.sw2a < SW2A_0_9V) || (voltage.sw2a > SW2A_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW2A, voltage.sw1a); + reg_mask = BITFMASK(MC13783_SWSET_SW2A); + reg = REG_SWITCHERS_2; + break; + case SW_SW2B: + if ((voltage.sw2b < SW2B_0_9V) || (voltage.sw2b > SW2B_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW2B, voltage.sw2b); + reg_mask = BITFMASK(MC13783_SWSET_SW1A); + reg = REG_SWITCHERS_3; + break; + case SW_SW3: + if (voltage.sw3 != SW3_5V) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW3, voltage.sw3); + reg_mask = BITFMASK(MC13783_SWSET_SW3); + reg = REG_SWITCHERS_5; + break; + case REGU_VIOLO: + if ((voltage.violo < VIOLO_1_2V) || + (voltage.violo > VIOLO_1_8V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VIOLO, voltage.violo); + reg_mask = BITFMASK(MC13783_REGSET_VIOLO); + reg = REG_REGULATOR_SETTING_0; + break; + case REGU_VDIG: + if ((voltage.vdig < VDIG_1_2V) || (voltage.vdig > VDIG_1_8V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VDIG, voltage.vdig); + reg_mask = BITFMASK(MC13783_REGSET_VDIG); + reg = REG_REGULATOR_SETTING_0; + break; + case REGU_VGEN: + if ((voltage.vgen < VGEN_1_2V) || (voltage.vgen > VGEN_2_4V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VGEN, voltage.vgen); + reg_mask = BITFMASK(MC13783_REGSET_VGEN); + reg = REG_REGULATOR_SETTING_0; + break; + case REGU_VRFDIG: + if ((voltage.vrfdig < VRFDIG_1_2V) || + (voltage.vrfdig > VRFDIG_1_875V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VRFDIG, voltage.vrfdig); + reg_mask = BITFMASK(MC13783_REGSET_VRFDIG); + reg = REG_REGULATOR_SETTING_0; + break; + case REGU_VRFREF: + if ((voltage.vrfref < VRFREF_2_475V) || + (voltage.vrfref > VRFREF_2_775V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VRFREF, voltage.vrfref); + reg_mask = BITFMASK(MC13783_REGSET_VRFREF); + reg = REG_REGULATOR_SETTING_0; + break; + case REGU_VRFCP: + if ((voltage.vrfcp < VRFCP_2_7V) || + (voltage.vrfcp > VRFCP_2_775V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VRFCP, voltage.vrfcp); + reg_mask = BITFMASK(MC13783_REGSET_VRFCP); + reg = REG_REGULATOR_SETTING_0; + break; + case REGU_VSIM: + if ((voltage.vsim < VSIM_1_8V) || (voltage.vsim > VSIM_2_9V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VSIM, voltage.vsim); + reg_mask = BITFMASK(MC13783_REGSET_VSIM); + reg = REG_REGULATOR_SETTING_0; + break; + case REGU_VESIM: + if ((voltage.vesim < VESIM_1_8V) || + (voltage.vesim > VESIM_2_9V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VESIM, voltage.vesim); + reg_mask = BITFMASK(MC13783_REGSET_VESIM); + reg = REG_REGULATOR_SETTING_0; + break; + case REGU_VCAM: + if ((voltage.vcam < VCAM_1_5V) || (voltage.vcam > VCAM_3V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VCAM, voltage.vcam); + reg_mask = BITFMASK(MC13783_REGSET_VCAM); + reg = REG_REGULATOR_SETTING_0; + break; + case REGU_VVIB: + if ((voltage.vvib < VVIB_1_3V) || (voltage.vvib > VVIB_3V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VVIB, voltage.vvib); + reg_mask = BITFMASK(MC13783_REGSET_VVIB); + reg = REG_REGULATOR_SETTING_1; + break; + case REGU_VRF1: + if ((voltage.vrf1 < VRF1_1_5V) || (voltage.vrf1 > VRF1_2_775V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VRF1, voltage.vrf1); + reg_mask = BITFMASK(MC13783_REGSET_VRF1); + reg = REG_REGULATOR_SETTING_1; + break; + case REGU_VRF2: + if ((voltage.vrf2 < VRF2_1_5V) || (voltage.vrf2 > VRF2_2_775V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VRF2, voltage.vrf2); + reg_mask = BITFMASK(MC13783_REGSET_VRF2); + reg = REG_REGULATOR_SETTING_1; + break; + case REGU_VMMC1: + if ((voltage.vmmc1 < VMMC1_1_6V) || (voltage.vmmc1 > VMMC1_3V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VMMC1, voltage.vmmc1); + reg_mask = BITFMASK(MC13783_REGSET_VMMC1); + reg = REG_REGULATOR_SETTING_1; + break; + case REGU_VMMC2: + if ((voltage.vmmc2 < VMMC2_1_6V) || (voltage.vmmc2 > VMMC2_3V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VMMC2, voltage.vmmc2); + reg_mask = BITFMASK(MC13783_REGSET_VMMC2); + reg = REG_REGULATOR_SETTING_1; + break; + case REGU_VAUDIO: + case REGU_VIOHI: + case REGU_VRFBG: + case REGU_GPO1: + case REGU_GPO2: + case REGU_GPO3: + case REGU_GPO4: + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function retrives the regulator output voltage. + * + * @param regulator The regulator to be truned off. + * @param voltage Pointer to regulator output voltage. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_get_voltage(t_pmic_regulator regulator, + t_regulator_voltage * voltage) +{ + unsigned int reg_val = 0; + + if (regulator == SW_SW1A) { + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_0, + ®_val, PMIC_ALL_BITS)); + } else if (regulator == SW_SW1B) { + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_1, + ®_val, PMIC_ALL_BITS)); + } else if (regulator == SW_SW2A) { + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_2, + ®_val, PMIC_ALL_BITS)); + } else if (regulator == SW_SW2B) { + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_3, + ®_val, PMIC_ALL_BITS)); + } else if (regulator == SW_SW3) { + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_5, + ®_val, PMIC_ALL_BITS)); + } else if ((regulator == REGU_VIOLO) || (regulator == REGU_VDIG) || + (regulator == REGU_VGEN) || + (regulator == REGU_VRFDIG) || + (regulator == REGU_VRFREF) || + (regulator == REGU_VRFCP) || + (regulator == REGU_VSIM) || + (regulator == REGU_VESIM) || (regulator == REGU_VCAM)) { + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®_val, PMIC_ALL_BITS)); + } else if ((regulator == REGU_VVIB) || (regulator == REGU_VRF1) || + (regulator == REGU_VRF2) || + (regulator == REGU_VMMC1) || (regulator == REGU_VMMC2)) { + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_1, + ®_val, PMIC_ALL_BITS)); + } + + switch (regulator) { + case SW_SW1A: + voltage->sw1a = BITFEXT(reg_val, MC13783_SWSET_SW1A); + break; + case SW_SW1B: + voltage->sw1b = BITFEXT(reg_val, MC13783_SWSET_SW1B); + break; + case SW_SW2A: + voltage->sw2a = BITFEXT(reg_val, MC13783_SWSET_SW2A); + break; + case SW_SW2B: + voltage->sw2b = BITFEXT(reg_val, MC13783_SWSET_SW2B); + break; + case SW_SW3: + voltage->sw3 = BITFEXT(reg_val, MC13783_SWSET_SW3); + break; + case REGU_VIOLO: + voltage->violo = BITFEXT(reg_val, MC13783_REGSET_VIOLO); + break; + case REGU_VDIG: + voltage->vdig = BITFEXT(reg_val, MC13783_REGSET_VDIG); + break; + case REGU_VGEN: + voltage->vgen = BITFEXT(reg_val, MC13783_REGSET_VGEN); + break; + case REGU_VRFDIG: + voltage->vrfdig = BITFEXT(reg_val, MC13783_REGSET_VRFDIG); + break; + case REGU_VRFREF: + voltage->vrfref = BITFEXT(reg_val, MC13783_REGSET_VRFREF); + break; + case REGU_VRFCP: + voltage->vrfcp = BITFEXT(reg_val, MC13783_REGSET_VRFCP); + break; + case REGU_VSIM: + voltage->vsim = BITFEXT(reg_val, MC13783_REGSET_VSIM); + break; + case REGU_VESIM: + voltage->vesim = BITFEXT(reg_val, MC13783_REGSET_VESIM); + break; + case REGU_VCAM: + voltage->vcam = BITFEXT(reg_val, MC13783_REGSET_VCAM); + break; + case REGU_VVIB: + voltage->vvib = BITFEXT(reg_val, MC13783_REGSET_VVIB); + break; + case REGU_VRF1: + voltage->vrf1 = BITFEXT(reg_val, MC13783_REGSET_VRF1); + break; + case REGU_VRF2: + voltage->vrf2 = BITFEXT(reg_val, MC13783_REGSET_VRF2); + break; + case REGU_VMMC1: + voltage->vmmc1 = BITFEXT(reg_val, MC13783_REGSET_VMMC1); + break; + case REGU_VMMC2: + voltage->vmmc2 = BITFEXT(reg_val, MC13783_REGSET_VMMC2); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets the DVS voltage + * + * @param regulator The regulator to be configured. + * @param dvs The switch Dynamic Voltage Scaling + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_dvs(t_pmic_regulator regulator, + t_regulator_voltage dvs) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + if ((dvs.sw1a < SW1A_0_9V) || (dvs.sw1a > SW1A_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW1A_DVS, dvs.sw1a); + reg_mask = BITFMASK(MC13783_SWSET_SW1A_DVS); + reg = REG_SWITCHERS_0; + break; + case SW_SW1B: + if ((dvs.sw1b < SW1B_0_9V) || (dvs.sw1b > SW1B_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW1B_DVS, dvs.sw1b); + reg_mask = BITFMASK(MC13783_SWSET_SW1B_DVS); + reg = REG_SWITCHERS_1; + break; + case SW_SW2A: + if ((dvs.sw2a < SW2A_0_9V) || (dvs.sw2a > SW2A_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW2A_DVS, dvs.sw2a); + reg_mask = BITFMASK(MC13783_SWSET_SW2A_DVS); + reg = REG_SWITCHERS_2; + break; + case SW_SW2B: + if ((dvs.sw2b < SW2B_0_9V) || (dvs.sw2b > SW2B_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW2B_DVS, dvs.sw2b); + reg_mask = BITFMASK(MC13783_SWSET_SW2B_DVS); + reg = REG_SWITCHERS_3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets the DVS voltage + * + * @param regulator The regulator to be handled. + * @param dvs The switch Dynamic Voltage Scaling + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_dvs(t_pmic_regulator regulator, + t_regulator_voltage * dvs) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + reg_mask = BITFMASK(MC13783_SWSET_SW1A_DVS); + reg = REG_SWITCHERS_0; + break; + case SW_SW1B: + reg_mask = BITFMASK(MC13783_SWSET_SW1B_DVS); + reg = REG_SWITCHERS_1; + break; + case SW_SW2A: + reg_mask = BITFMASK(MC13783_SWSET_SW2A_DVS); + reg = REG_SWITCHERS_2; + break; + case SW_SW2B: + reg_mask = BITFMASK(MC13783_SWSET_SW2B_DVS); + reg = REG_SWITCHERS_3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, ®_val, reg_mask)); + + switch (regulator) { + case SW_SW1A: + *dvs = (t_regulator_voltage) BITFEXT(reg_val, + MC13783_SWSET_SW1A_DVS); + break; + case SW_SW1B: + *dvs = (t_regulator_voltage) BITFEXT(reg_val, + MC13783_SWSET_SW1B_DVS); + break; + case SW_SW2A: + *dvs = (t_regulator_voltage) BITFEXT(reg_val, + MC13783_SWSET_SW2A_DVS); + break; + case SW_SW2B: + *dvs = (t_regulator_voltage) BITFEXT(reg_val, + MC13783_SWSET_SW2B_DVS); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets the standiby voltage + * + * @param regulator The regulator to be configured. + * @param stby The switch standby voltage + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_stby(t_pmic_regulator regulator, + t_regulator_voltage stby) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + if ((stby.sw1a < SW1A_0_9V) || (stby.sw1a > SW1A_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW1A_STDBY, stby.sw1a); + reg_mask = BITFMASK(MC13783_SWSET_SW1A_STDBY); + reg = REG_SWITCHERS_0; + break; + case SW_SW1B: + if ((stby.sw1b < SW1B_0_9V) || (stby.sw1b > SW1B_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW1B_STDBY, stby.sw1b); + reg_mask = BITFMASK(MC13783_SWSET_SW1B_STDBY); + reg = REG_SWITCHERS_1; + break; + case SW_SW2A: + if ((stby.sw2a < SW2A_0_9V) || (stby.sw2a > SW2A_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW2A_STDBY, stby.sw2a); + reg_mask = BITFMASK(MC13783_SWSET_SW2A_STDBY); + reg = REG_SWITCHERS_2; + break; + case SW_SW2B: + if ((stby.sw2b < SW2B_0_9V) || (stby.sw2b > SW2B_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW2B_STDBY, stby.sw2b); + reg_mask = BITFMASK(MC13783_SWSET_SW2B_STDBY); + reg = REG_SWITCHERS_3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets the standiby voltage + * + * @param regulator The regulator to be handled. + * @param stby The switch standby voltage + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_stby(t_pmic_regulator regulator, + t_regulator_voltage * stby) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + reg_mask = BITFMASK(MC13783_SWSET_SW1A_STDBY); + reg = REG_SWITCHERS_0; + break; + case SW_SW1B: + reg_mask = BITFMASK(MC13783_SWSET_SW1B_STDBY); + reg = REG_SWITCHERS_1; + break; + case SW_SW2A: + reg_mask = BITFMASK(MC13783_SWSET_SW2A_STDBY); + reg = REG_SWITCHERS_2; + break; + case SW_SW2B: + reg_mask = BITFMASK(MC13783_SWSET_SW2B_STDBY); + reg = REG_SWITCHERS_3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, ®_val, reg_mask)); + + switch (regulator) { + case SW_SW1A: + *stby = (t_regulator_voltage) BITFEXT(reg_val, + MC13783_SWSET_SW1A_STDBY); + break; + case SW_SW1B: + *stby = (t_regulator_voltage) BITFEXT(reg_val, + MC13783_SWSET_SW1B_STDBY); + break; + case SW_SW2A: + *stby = (t_regulator_voltage) BITFEXT(reg_val, + MC13783_SWSET_SW2A_STDBY); + break; + case SW_SW2B: + *stby = (t_regulator_voltage) BITFEXT(reg_val, + MC13783_SWSET_SW2B_STDBY); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets the switchers mode. + * + * @param regulator The regulator to be configured. + * @param mode The switcher mode + * @param stby Switch between main and standby. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_mode(t_pmic_regulator regulator, + t_regulator_sw_mode mode, bool stby) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + unsigned int l_mode; + + if (mode == SYNC_RECT) { + l_mode = MC13783_SWCTRL_SW_MODE_SYNC_RECT_EN; + } else if (mode == NO_PULSE_SKIP) { + l_mode = MC13783_SWCTRL_SW_MODE_PULSE_NO_SKIP_EN; + } else if (mode == PULSE_SKIP) { + l_mode = MC13783_SWCTRL_SW_MODE_PULSE_SKIP_EN; + } else if (mode == LOW_POWER) { + l_mode = MC13783_SWCTRL_SW_MODE_LOW_POWER_EN; + } else { + return PMIC_PARAMETER_ERROR; + } + + switch (regulator) { + case SW_SW1A: + if (stby) { + reg_val = + BITFVAL(MC13783_SWCTRL_SW1A_STBY_MODE, l_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_STBY_MODE); + } else { + reg_val = BITFVAL(MC13783_SWCTRL_SW1A_MODE, l_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_MODE); + } + reg = REG_SWITCHERS_4; + break; + case SW_SW1B: + if (stby) { + reg_val = + BITFVAL(MC13783_SWCTRL_SW1B_STBY_MODE, l_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_STBY_MODE); + } else { + reg_val = BITFVAL(MC13783_SWCTRL_SW1B_MODE, l_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_MODE); + } + reg = REG_SWITCHERS_4; + break; + case SW_SW2A: + if (stby) { + reg_val = + BITFVAL(MC13783_SWCTRL_SW2A_STBY_MODE, l_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_STBY_MODE); + } else { + reg_val = BITFVAL(MC13783_SWCTRL_SW2A_MODE, l_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_MODE); + } + reg = REG_SWITCHERS_5; + break; + case SW_SW2B: + if (stby) { + reg_val = + BITFVAL(MC13783_SWCTRL_SW2B_STBY_MODE, l_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_STBY_MODE); + } else { + reg_val = BITFVAL(MC13783_SWCTRL_SW2B_MODE, l_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_MODE); + } + reg = REG_SWITCHERS_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets the switchers mode. + * + * @param regulator The regulator to be handled. + * @param mode The switcher mode. + * @param stby Switch between main and standby. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_mode(t_pmic_regulator regulator, + t_regulator_sw_mode * mode, bool stby) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg = 0; + unsigned int l_mode = 0; + + switch (regulator) { + case SW_SW1A: + if (stby) { + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_STBY_MODE); + } else { + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_MODE); + } + reg = REG_SWITCHERS_4; + break; + case SW_SW1B: + if (stby) { + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_STBY_MODE); + } else { + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_MODE); + } + reg = REG_SWITCHERS_4; + break; + case SW_SW2A: + if (stby) { + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_STBY_MODE); + } else { + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_MODE); + } + reg = REG_SWITCHERS_5; + break; + case SW_SW2B: + if (stby) { + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_STBY_MODE); + } else { + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_MODE); + } + reg = REG_SWITCHERS_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, ®_val, reg_mask)); + + switch (regulator) { + case SW_SW1A: + if (stby) { + l_mode = + BITFEXT(reg_val, MC13783_SWCTRL_SW1A_STBY_MODE); + } else { + l_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW1A_MODE); + } + break; + case SW_SW1B: + if (stby) { + l_mode = + BITFEXT(reg_val, MC13783_SWCTRL_SW1B_STBY_MODE); + } else { + l_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW1B_MODE); + } + break; + case SW_SW2A: + if (stby) { + l_mode = + BITFEXT(reg_val, MC13783_SWCTRL_SW2A_STBY_MODE); + } else { + l_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW2A_MODE); + } + break; + case SW_SW2B: + if (stby) { + l_mode = + BITFEXT(reg_val, MC13783_SWCTRL_SW2B_STBY_MODE); + } else { + l_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW2B_MODE); + } + break; + default: + return PMIC_PARAMETER_ERROR; + } + + if (l_mode == MC13783_SWCTRL_SW_MODE_SYNC_RECT_EN) { + *mode = SYNC_RECT; + } else if (l_mode == MC13783_SWCTRL_SW_MODE_PULSE_NO_SKIP_EN) { + *mode = NO_PULSE_SKIP; + } else if (l_mode == MC13783_SWCTRL_SW_MODE_PULSE_SKIP_EN) { + *mode = PULSE_SKIP; + } else if (l_mode == MC13783_SWCTRL_SW_MODE_LOW_POWER_EN) { + *mode = LOW_POWER; + } else { + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets the switch dvs speed + * + * @param regulator The regulator to be configured. + * @param speed The dvs speed. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_dvs_speed(t_pmic_regulator regulator, + t_switcher_dvs_speed speed) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + if (speed > 3 || speed < 0) { + return PMIC_PARAMETER_ERROR; + } + + switch (regulator) { + case SW_SW1A: + reg_val = BITFVAL(MC13783_SWCTRL_SW1A_DVS_SPEED, speed); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_DVS_SPEED); + reg = REG_SWITCHERS_4; + break; + case SW_SW1B: + reg_val = BITFVAL(MC13783_SWCTRL_SW2B_DVS_SPEED, speed); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_DVS_SPEED); + reg = REG_SWITCHERS_4; + break; + case SW_SW2A: + reg_val = BITFVAL(MC13783_SWCTRL_SW2A_DVS_SPEED, speed); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_DVS_SPEED); + reg = REG_SWITCHERS_5; + break; + case SW_SW2B: + reg_val = BITFVAL(MC13783_SWCTRL_SW2B_DVS_SPEED, speed); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_DVS_SPEED); + reg = REG_SWITCHERS_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets the switch dvs speed + * + * @param regulator The regulator to be handled. + * @param speed The dvs speed. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_dvs_speed(t_pmic_regulator regulator, + t_switcher_dvs_speed * speed) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_DVS_SPEED); + reg = REG_SWITCHERS_4; + break; + case SW_SW1B: + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_DVS_SPEED); + reg = REG_SWITCHERS_4; + break; + case SW_SW2A: + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_DVS_SPEED); + reg = REG_SWITCHERS_5; + break; + case SW_SW2B: + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_DVS_SPEED); + reg = REG_SWITCHERS_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, ®_val, reg_mask)); + + switch (regulator) { + case SW_SW1A: + *speed = BITFEXT(reg_val, MC13783_SWCTRL_SW1A_DVS_SPEED); + break; + case SW_SW1B: + *speed = BITFEXT(reg_val, MC13783_SWCTRL_SW1B_DVS_SPEED); + break; + case SW_SW2A: + *speed = BITFEXT(reg_val, MC13783_SWCTRL_SW2A_DVS_SPEED); + break; + case SW_SW2B: + *speed = BITFEXT(reg_val, MC13783_SWCTRL_SW2B_DVS_SPEED); + break; + default: + break; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets the switch panic mode + * + * @param regulator The regulator to be configured. + * @param panic_mode Enable or disable panic mode + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_panic_mode(t_pmic_regulator regulator, + bool panic_mode) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + reg_val = BITFVAL(MC13783_SWCTRL_SW1A_PANIC_MODE, panic_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_PANIC_MODE); + reg = REG_SWITCHERS_4; + break; + case SW_SW1B: + reg_val = BITFVAL(MC13783_SWCTRL_SW2B_PANIC_MODE, panic_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_PANIC_MODE); + reg = REG_SWITCHERS_4; + break; + case SW_SW2A: + reg_val = BITFVAL(MC13783_SWCTRL_SW2A_PANIC_MODE, panic_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_PANIC_MODE); + reg = REG_SWITCHERS_5; + break; + case SW_SW2B: + reg_val = BITFVAL(MC13783_SWCTRL_SW2B_PANIC_MODE, panic_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_PANIC_MODE); + reg = REG_SWITCHERS_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets the switch panic mode + * + * @param regulator The regulator to be handled + * @param panic_mode Enable or disable panic mode + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_panic_mode(t_pmic_regulator regulator, + bool * panic_mode) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_PANIC_MODE); + reg = REG_SWITCHERS_4; + break; + case SW_SW1B: + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_PANIC_MODE); + reg = REG_SWITCHERS_4; + break; + case SW_SW2A: + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_PANIC_MODE); + reg = REG_SWITCHERS_5; + break; + case SW_SW2B: + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_PANIC_MODE); + reg = REG_SWITCHERS_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, ®_val, reg_mask)); + + switch (regulator) { + case SW_SW1A: + *panic_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW1A_PANIC_MODE); + break; + case SW_SW1B: + *panic_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW1B_PANIC_MODE); + break; + case SW_SW2A: + *panic_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW2A_PANIC_MODE); + break; + case SW_SW2B: + *panic_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW2B_PANIC_MODE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets the switch softstart mode + * + * @param regulator The regulator to be configured. + * @param softstart Enable or disable softstart. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_softstart(t_pmic_regulator regulator, + bool softstart) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + reg_val = BITFVAL(MC13783_SWCTRL_SW1A_SOFTSTART, softstart); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_SOFTSTART); + reg = REG_SWITCHERS_4; + break; + case SW_SW1B: + reg_val = BITFVAL(MC13783_SWCTRL_SW2B_SOFTSTART, softstart); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_SOFTSTART); + reg = REG_SWITCHERS_4; + break; + case SW_SW2A: + reg_val = BITFVAL(MC13783_SWCTRL_SW2A_SOFTSTART, softstart); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_SOFTSTART); + reg = REG_SWITCHERS_5; + break; + case SW_SW2B: + reg_val = BITFVAL(MC13783_SWCTRL_SW2B_SOFTSTART, softstart); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_SOFTSTART); + reg = REG_SWITCHERS_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets the switch softstart mode + * + * @param regulator The regulator to be handled + * @param softstart Enable or disable softstart. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_softstart(t_pmic_regulator regulator, + bool * softstart) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_SOFTSTART); + reg = REG_SWITCHERS_4; + break; + case SW_SW1B: + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_SOFTSTART); + reg = REG_SWITCHERS_4; + break; + case SW_SW2A: + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_SOFTSTART); + reg = REG_SWITCHERS_5; + break; + case SW_SW2B: + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_SOFTSTART); + reg = REG_SWITCHERS_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, ®_val, reg_mask)); + + switch (regulator) { + case SW_SW1A: + *softstart = BITFEXT(reg_val, MC13783_SWCTRL_SW1A_SOFTSTART); + break; + case SW_SW1B: + *softstart = BITFEXT(reg_val, MC13783_SWCTRL_SW2B_SOFTSTART); + break; + case SW_SW2A: + *softstart = BITFEXT(reg_val, MC13783_SWCTRL_SW2A_SOFTSTART); + break; + case SW_SW2B: + *softstart = BITFEXT(reg_val, MC13783_SWCTRL_SW2B_SOFTSTART); + break; + default: + break; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets the PLL multiplication factor + * + * @param regulator The regulator to be configured. + * @param factor The multiplication factor. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_factor(t_pmic_regulator regulator, + t_switcher_factor factor) +{ + unsigned int reg_val = 0, reg_mask = 0; + + if (regulator != SW_PLL) { + return PMIC_PARAMETER_ERROR; + } + if (factor < FACTOR_28 || factor > FACTOR_35) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWCTRL_PLL_FACTOR, factor); + reg_mask = BITFMASK(MC13783_SWCTRL_PLL_FACTOR); + + CHECK_ERROR(pmic_write_reg(REG_SWITCHERS_4, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets the PLL multiplication factor + * + * @param regulator The regulator to be handled + * @param factor The multiplication factor. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_factor(t_pmic_regulator regulator, + t_switcher_factor * factor) +{ + unsigned int reg_val = 0, reg_mask = 0; + + if (regulator != SW_PLL) { + return PMIC_PARAMETER_ERROR; + } + reg_mask = BITFMASK(MC13783_SWCTRL_PLL_FACTOR); + + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_4, ®_val, reg_mask)); + + *factor = BITFEXT(reg_val, MC13783_SWCTRL_PLL_FACTOR); + + return PMIC_SUCCESS; +} + +/*! + * This function enables or disables low power mode. + * + * @param regulator The regulator to be configured. + * @param lp_mode Select nominal or low power mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_set_lp_mode(t_pmic_regulator regulator, + t_regulator_lp_mode lp_mode) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + unsigned int l_mode, l_stby; + + if (lp_mode == LOW_POWER_DISABLED) { + l_mode = MC13783_REGTRL_LP_MODE_DISABLE; + l_stby = MC13783_REGTRL_STBY_MODE_DISABLE; + } else if (lp_mode == LOW_POWER_CTRL_BY_PIN) { + l_mode = MC13783_REGTRL_LP_MODE_DISABLE; + l_stby = MC13783_REGTRL_STBY_MODE_ENABLE; + } else if (lp_mode == LOW_POWER_EN) { + l_mode = MC13783_REGTRL_LP_MODE_ENABLE; + l_stby = MC13783_REGTRL_STBY_MODE_DISABLE; + } else if (lp_mode == LOW_POWER_AND_LOW_POWER_CTRL_BY_PIN) { + l_mode = MC13783_REGTRL_LP_MODE_ENABLE; + l_stby = MC13783_REGTRL_STBY_MODE_ENABLE; + } else { + return PMIC_PARAMETER_ERROR; + } + + switch (regulator) { + case SW_SW3: + reg_val = BITFVAL(MC13783_SWCTRL_SW3_MODE, l_mode) | + BITFVAL(MC13783_SWCTRL_SW3_STBY, l_stby); + reg_mask = BITFMASK(MC13783_SWCTRL_SW3_MODE) | + BITFMASK(MC13783_SWCTRL_SW3_STBY); + reg = REG_SWITCHERS_5; + break; + case REGU_VAUDIO: + reg_val = BITFVAL(MC13783_REGCTRL_VAUDIO_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VAUDIO_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VAUDIO_MODE) | + BITFMASK(MC13783_REGCTRL_VAUDIO_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VIOHI: + reg_val = BITFVAL(MC13783_REGCTRL_VIOHI_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VIOHI_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VIOHI_MODE) | + BITFMASK(MC13783_REGCTRL_VIOHI_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VIOLO: + reg_val = BITFVAL(MC13783_REGCTRL_VIOLO_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VIOLO_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VIOLO_MODE) | + BITFMASK(MC13783_REGCTRL_VIOLO_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VDIG: + reg_val = BITFVAL(MC13783_REGCTRL_VDIG_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VDIG_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VDIG_MODE) | + BITFMASK(MC13783_REGCTRL_VDIG_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VGEN: + reg_val = BITFVAL(MC13783_REGCTRL_VGEN_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VGEN_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VGEN_MODE) | + BITFMASK(MC13783_REGCTRL_VGEN_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFDIG: + reg_val = BITFVAL(MC13783_REGCTRL_VRFDIG_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VRFDIG_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFDIG_MODE) | + BITFMASK(MC13783_REGCTRL_VRFDIG_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFREF: + reg_val = BITFVAL(MC13783_REGCTRL_VRFREF_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VRFREF_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFREF_MODE) | + BITFMASK(MC13783_REGCTRL_VRFREF_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFCP: + reg_val = BITFVAL(MC13783_REGCTRL_VRFCP_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VRFCP_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFCP_MODE) | + BITFMASK(MC13783_REGCTRL_VRFCP_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VSIM: + reg_val = BITFVAL(MC13783_REGCTRL_VSIM_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VSIM_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VSIM_MODE) | + BITFMASK(MC13783_REGCTRL_VSIM_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VESIM: + reg_val = BITFVAL(MC13783_REGCTRL_VESIM_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VESIM_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VESIM_MODE) | + BITFMASK(MC13783_REGCTRL_VESIM_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VCAM: + reg_val = BITFVAL(MC13783_REGCTRL_VCAM_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VCAM_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VCAM_MODE) | + BITFMASK(MC13783_REGCTRL_VCAM_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRFBG: + if ((lp_mode == LOW_POWER) || + (lp_mode == LOW_POWER_AND_LOW_POWER_CTRL_BY_PIN)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGCTRL_VRFBG_STBY, l_mode); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFBG_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRF1: + reg_val = BITFVAL(MC13783_REGCTRL_VRF1_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VRF1_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VRF1_MODE) | + BITFMASK(MC13783_REGCTRL_VRF1_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRF2: + reg_val = BITFVAL(MC13783_REGCTRL_VRF2_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VRF2_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VRF2_MODE) | + BITFMASK(MC13783_REGCTRL_VRF2_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VMMC1: + reg_val = BITFVAL(MC13783_REGCTRL_VMMC1_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VMMC1_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VMMC1_MODE) | + BITFMASK(MC13783_REGCTRL_VMMC1_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VMMC2: + reg_val = BITFVAL(MC13783_REGCTRL_VMMC2_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VMMC2_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VMMC2_MODE) | + BITFMASK(MC13783_REGCTRL_VMMC2_STBY); + reg = REG_REGULATOR_MODE_1; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets low power mode. + * + * @param regulator The regulator to be handled + * @param lp_mode Select nominal or low power mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_get_lp_mode(t_pmic_regulator regulator, + t_regulator_lp_mode * lp_mode) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + unsigned int l_mode, l_stby; + + switch (regulator) { + case SW_SW3: + reg_mask = BITFMASK(MC13783_SWCTRL_SW3_MODE) | + BITFMASK(MC13783_SWCTRL_SW3_STBY); + reg = REG_SWITCHERS_5; + break; + case REGU_VAUDIO: + reg_mask = BITFMASK(MC13783_REGCTRL_VAUDIO_MODE) | + BITFMASK(MC13783_REGCTRL_VAUDIO_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VIOHI: + reg_mask = BITFMASK(MC13783_REGCTRL_VIOHI_MODE) | + BITFMASK(MC13783_REGCTRL_VIOHI_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VIOLO: + reg_mask = BITFMASK(MC13783_REGCTRL_VIOLO_MODE) | + BITFMASK(MC13783_REGCTRL_VIOLO_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VDIG: + reg_mask = BITFMASK(MC13783_REGCTRL_VDIG_MODE) | + BITFMASK(MC13783_REGCTRL_VDIG_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VGEN: + reg_mask = BITFMASK(MC13783_REGCTRL_VGEN_MODE) | + BITFMASK(MC13783_REGCTRL_VGEN_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFDIG: + reg_mask = BITFMASK(MC13783_REGCTRL_VRFDIG_MODE) | + BITFMASK(MC13783_REGCTRL_VRFDIG_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFREF: + reg_mask = BITFMASK(MC13783_REGCTRL_VRFREF_MODE) | + BITFMASK(MC13783_REGCTRL_VRFREF_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFCP: + reg_mask = BITFMASK(MC13783_REGCTRL_VRFCP_MODE) | + BITFMASK(MC13783_REGCTRL_VRFCP_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VSIM: + reg_mask = BITFMASK(MC13783_REGCTRL_VSIM_MODE) | + BITFMASK(MC13783_REGCTRL_VSIM_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VESIM: + reg_mask = BITFMASK(MC13783_REGCTRL_VESIM_MODE) | + BITFMASK(MC13783_REGCTRL_VESIM_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VCAM: + reg_mask = BITFMASK(MC13783_REGCTRL_VCAM_MODE) | + BITFMASK(MC13783_REGCTRL_VCAM_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRFBG: + reg_mask = BITFMASK(MC13783_REGCTRL_VRFBG_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRF1: + reg_mask = BITFMASK(MC13783_REGCTRL_VRF1_MODE) | + BITFMASK(MC13783_REGCTRL_VRF1_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRF2: + reg_mask = BITFMASK(MC13783_REGCTRL_VRF2_MODE) | + BITFMASK(MC13783_REGCTRL_VRF2_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VMMC1: + reg_mask = BITFMASK(MC13783_REGCTRL_VMMC1_MODE) | + BITFMASK(MC13783_REGCTRL_VMMC1_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VMMC2: + reg_mask = BITFMASK(MC13783_REGCTRL_VMMC2_MODE) | + BITFMASK(MC13783_REGCTRL_VMMC2_STBY); + reg = REG_REGULATOR_MODE_1; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, ®_val, reg_mask)); + + switch (regulator) { + case SW_SW3: + l_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW3_MODE); + l_stby = BITFEXT(reg_val, MC13783_SWCTRL_SW3_STBY); + break; + case REGU_VAUDIO: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VAUDIO_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VAUDIO_STBY); + break; + case REGU_VIOHI: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VIOHI_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VIOHI_STBY); + break; + case REGU_VIOLO: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VIOLO_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VIOLO_STBY); + break; + case REGU_VDIG: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VDIG_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VDIG_STBY); + break; + case REGU_VGEN: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VGEN_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VGEN_STBY); + break; + case REGU_VRFDIG: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VRFDIG_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VRFDIG_STBY); + break; + case REGU_VRFREF: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VRFREF_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VRFREF_STBY); + break; + case REGU_VRFCP: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VRFCP_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VRFCP_STBY); + break; + case REGU_VSIM: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VSIM_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VSIM_STBY); + break; + case REGU_VESIM: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VESIM_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VESIM_STBY); + break; + case REGU_VCAM: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VCAM_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VCAM_STBY); + break; + case REGU_VRFBG: + l_mode = MC13783_REGTRL_LP_MODE_DISABLE; + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VRFBG_STBY); + break; + case REGU_VRF1: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VRF1_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VRF1_STBY); + break; + case REGU_VRF2: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VRF2_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VRF2_STBY); + break; + case REGU_VMMC1: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VMMC1_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VMMC1_STBY); + break; + case REGU_VMMC2: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VMMC2_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VMMC2_STBY); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + if ((l_mode == MC13783_REGTRL_LP_MODE_DISABLE) && + (l_stby == MC13783_REGTRL_STBY_MODE_DISABLE)) { + *lp_mode = LOW_POWER_DISABLED; + } else if ((l_mode == MC13783_REGTRL_LP_MODE_DISABLE) && + (l_stby == MC13783_REGTRL_STBY_MODE_ENABLE)) { + *lp_mode = LOW_POWER_CTRL_BY_PIN; + } else if ((l_mode == MC13783_REGTRL_LP_MODE_ENABLE) && + (l_stby == MC13783_REGTRL_STBY_MODE_DISABLE)) { + *lp_mode = LOW_POWER_EN; + } else { + *lp_mode = LOW_POWER_AND_LOW_POWER_CTRL_BY_PIN; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets the regulator configuration. + * + * @param regulator The regulator to be configured. + * @param config The regulator output configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_set_config(t_pmic_regulator regulator, + t_regulator_config * config) +{ + if (config == NULL) { + return PMIC_ERROR; + } + + switch (regulator) { + case SW_SW1A: + case SW_SW1B: + case SW_SW2A: + case SW_SW2B: + CHECK_ERROR(pmic_power_regulator_set_voltage + (regulator, config->voltage)); + CHECK_ERROR(pmic_power_switcher_set_dvs + (regulator, config->voltage_lvs)); + CHECK_ERROR(pmic_power_switcher_set_stby + (regulator, config->voltage_stby)); + CHECK_ERROR(pmic_power_switcher_set_mode + (regulator, config->mode, false)); + CHECK_ERROR(pmic_power_switcher_set_mode + (regulator, config->stby_mode, true)); + CHECK_ERROR(pmic_power_switcher_set_dvs_speed + (regulator, config->dvs_speed)); + CHECK_ERROR(pmic_power_switcher_set_panic_mode + (regulator, config->panic_mode)); + CHECK_ERROR(pmic_power_switcher_set_softstart + (regulator, config->softstart)); + break; + case SW_PLL: + CHECK_ERROR(pmic_power_switcher_set_factor + (regulator, config->factor)); + break; + case SW_SW3: + case REGU_VIOLO: + case REGU_VDIG: + case REGU_VGEN: + case REGU_VRFDIG: + case REGU_VRFREF: + case REGU_VRFCP: + case REGU_VSIM: + case REGU_VESIM: + case REGU_VCAM: + case REGU_VRF1: + case REGU_VRF2: + case REGU_VMMC1: + case REGU_VMMC2: + CHECK_ERROR(pmic_power_regulator_set_voltage + (regulator, config->voltage)); + CHECK_ERROR(pmic_power_regulator_set_lp_mode + (regulator, config->lp_mode)); + break; + case REGU_VVIB: + CHECK_ERROR(pmic_power_regulator_set_voltage + (regulator, config->voltage)); + break; + case REGU_VAUDIO: + case REGU_VIOHI: + case REGU_VRFBG: + CHECK_ERROR(pmic_power_regulator_set_lp_mode + (regulator, config->lp_mode)); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function retrives the regulator output configuration. + * + * @param regulator The regulator to be truned off. + * @param config Pointer to regulator configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_get_config(t_pmic_regulator regulator, + t_regulator_config * config) +{ + if (config == NULL) { + return PMIC_ERROR; + } + + switch (regulator) { + case SW_SW1A: + case SW_SW1B: + case SW_SW2A: + case SW_SW2B: + CHECK_ERROR(pmic_power_regulator_get_voltage + (regulator, &config->voltage)); + CHECK_ERROR(pmic_power_switcher_get_dvs + (regulator, &config->voltage_lvs)); + CHECK_ERROR(pmic_power_switcher_get_stby + (regulator, &config->voltage_stby)); + CHECK_ERROR(pmic_power_switcher_get_mode + (regulator, &config->mode, false)); + CHECK_ERROR(pmic_power_switcher_get_mode + (regulator, &config->stby_mode, true)); + CHECK_ERROR(pmic_power_switcher_get_dvs_speed + (regulator, &config->dvs_speed)); + CHECK_ERROR(pmic_power_switcher_get_panic_mode + (regulator, &config->panic_mode)); + CHECK_ERROR(pmic_power_switcher_get_softstart + (regulator, &config->softstart)); + break; + case SW_PLL: + CHECK_ERROR(pmic_power_switcher_get_factor + (regulator, &config->factor)); + break; + case SW_SW3: + case REGU_VIOLO: + case REGU_VDIG: + case REGU_VGEN: + case REGU_VRFDIG: + case REGU_VRFREF: + case REGU_VRFCP: + case REGU_VSIM: + case REGU_VESIM: + case REGU_VCAM: + case REGU_VRF1: + case REGU_VRF2: + case REGU_VMMC1: + case REGU_VMMC2: + CHECK_ERROR(pmic_power_regulator_get_voltage + (regulator, &config->voltage)); + CHECK_ERROR(pmic_power_regulator_get_lp_mode + (regulator, &config->lp_mode)); + break; + case REGU_VVIB: + CHECK_ERROR(pmic_power_regulator_get_voltage + (regulator, &config->voltage)); + break; + case REGU_VAUDIO: + case REGU_VIOHI: + case REGU_VRFBG: + CHECK_ERROR(pmic_power_regulator_get_lp_mode + (regulator, &config->lp_mode)); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function enables automatically VBKUP2 in the memory hold modes. + * Only on mc13783 2.0 or higher + * + * @param en if true, enable VBKUP2AUTOMH + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_vbkup2_auto_en(bool en) +{ + unsigned int reg_val = 0, reg_mask = 0; + pmic_version_t mc13783_ver; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + reg_val = BITFVAL(MC13783_REGCTRL_VBKUP2AUTOMH, en); + reg_mask = BITFMASK(MC13783_REGCTRL_VBKUP2AUTOMH); + + CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_0, + reg_val, reg_mask)); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function gets state of automatically VBKUP2. + * Only on mc13783 2.0 or higher + * + * @param en if true, VBKUP2AUTOMH is enabled + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_get_vbkup2_auto_state(bool * en) +{ + unsigned int reg_val = 0, reg_mask = 0; + pmic_version_t mc13783_ver; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + reg_mask = BITFMASK(MC13783_REGCTRL_VBKUP2AUTOMH); + CHECK_ERROR(pmic_read_reg(REG_POWER_CONTROL_0, + ®_val, reg_mask)); + *en = BITFEXT(reg_val, MC13783_REGCTRL_VBKUP2AUTOMH); + + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function enables battery detect function. + * Only on mc13783 2.0 or higher + * + * @param en if true, enable BATTDETEN + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_bat_det_en(bool en) +{ + unsigned int reg_val = 0, reg_mask = 0; + pmic_version_t mc13783_ver; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + reg_val = BITFVAL(MC13783_REGCTRL_BATTDETEN, en); + reg_mask = BITFMASK(MC13783_REGCTRL_BATTDETEN); + + CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_0, + reg_val, reg_mask)); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function gets state of battery detect function. + * Only on mc13783 2.0 or higher + * + * @param en if true, BATTDETEN is enabled + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_get_bat_det_state(bool * en) +{ + unsigned int reg_val = 0, reg_mask = 0; + pmic_version_t mc13783_ver; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + reg_mask = BITFMASK(MC13783_REGCTRL_BATTDETEN); + + CHECK_ERROR(pmic_read_reg(REG_POWER_CONTROL_0, + ®_val, reg_mask)); + *en = BITFEXT(reg_val, MC13783_REGCTRL_BATTDETEN); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function enables control of VVIB by VIBEN pin. + * Only on mc13783 2.0 or higher + * + * @param en if true, enable VIBPINCTRL + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_vib_pin_en(bool en) +{ + unsigned int reg_val = 0, reg_mask = 0; + pmic_version_t mc13783_ver; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + reg_val = BITFVAL(MC13783_REGCTRL_VIBPINCTRL, en); + reg_mask = BITFMASK(MC13783_REGCTRL_VIBPINCTRL); + + CHECK_ERROR(pmic_write_reg(REG_POWER_MISCELLANEOUS, + reg_val, reg_mask)); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function gets state of control of VVIB by VIBEN pin. + * Only on mc13783 2.0 or higher + * @param en if true, VIBPINCTRL is enabled + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_gets_vib_pin_state(bool * en) +{ + unsigned int reg_val = 0, reg_mask = 0; + pmic_version_t mc13783_ver; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + reg_mask = BITFMASK(MC13783_REGCTRL_VIBPINCTRL); + CHECK_ERROR(pmic_read_reg(REG_POWER_MISCELLANEOUS, + ®_val, reg_mask)); + *en = BITFEXT(reg_val, MC13783_REGCTRL_VIBPINCTRL); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function returns power up sense value + * + * @param p_up_sense value of power up sense + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_get_power_mode_sense(struct t_p_up_sense * p_up_sense) +{ + unsigned int reg_value = 0; + CHECK_ERROR(pmic_read_reg(REG_POWER_UP_MODE_SENSE, + ®_value, PMIC_ALL_BITS)); + p_up_sense->state_ictest = (STATE_ICTEST_MASK & reg_value); + p_up_sense->state_clksel = ((STATE_CLKSEL_MASK & reg_value) + >> STATE_CLKSEL_BIT); + p_up_sense->state_pums1 = ((STATE_PUMS1_MASK & reg_value) + >> STATE_PUMS1_BITS); + p_up_sense->state_pums2 = ((STATE_PUMS2_MASK & reg_value) + >> STATE_PUMS2_BITS); + p_up_sense->state_pums3 = ((STATE_PUMS3_MASK & reg_value) + >> STATE_PUMS3_BITS); + p_up_sense->state_chrgmode0 = ((STATE_CHRGM1_MASK & reg_value) + >> STATE_CHRGM1_BITS); + p_up_sense->state_chrgmode1 = ((STATE_CHRGM2_MASK & reg_value) + >> STATE_CHRGM2_BITS); + p_up_sense->state_umod = ((STATE_UMOD_MASK & reg_value) + >> STATE_UMOD_BITS); + p_up_sense->state_usben = ((STATE_USBEN_MASK & reg_value) + >> STATE_USBEN_BIT); + p_up_sense->state_sw_1a1b_joined = ((STATE_SW1A_J_B_MASK & reg_value) + >> STATE_SW1A_J_B_BIT); + p_up_sense->state_sw_2a2b_joined = ((STATE_SW2A_J_B_MASK & reg_value) + >> STATE_SW2A_J_B_BIT); + return PMIC_SUCCESS; +} + +/*! + * This function configures the Regen assignment for all regulator + * + * @param regulator type of regulator + * @param en_dis if true, the regulator is enabled by regen. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_set_regen_assig(t_pmic_regulator regulator, bool en_dis) +{ + unsigned int reg_val = 0, reg_mask = 0; + + switch (regulator) { + case REGU_VAUDIO: + reg_val = BITFVAL(MC13783_REGGEN_VAUDIO, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VAUDIO); + break; + case REGU_VIOHI: + reg_val = BITFVAL(MC13783_REGGEN_VIOHI, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VIOHI); + break; + case REGU_VIOLO: + reg_val = BITFVAL(MC13783_REGGEN_VIOLO, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VIOLO); + break; + case REGU_VDIG: + reg_val = BITFVAL(MC13783_REGGEN_VDIG, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VDIG); + break; + case REGU_VGEN: + reg_val = BITFVAL(MC13783_REGGEN_VGEN, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VGEN); + break; + case REGU_VRFDIG: + reg_val = BITFVAL(MC13783_REGGEN_VRFDIG, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VRFDIG); + break; + case REGU_VRFREF: + reg_val = BITFVAL(MC13783_REGGEN_VRFREF, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VRFREF); + break; + case REGU_VRFCP: + reg_val = BITFVAL(MC13783_REGGEN_VRFCP, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VRFCP); + break; + case REGU_VCAM: + reg_val = BITFVAL(MC13783_REGGEN_VCAM, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VCAM); + break; + case REGU_VRFBG: + reg_val = BITFVAL(MC13783_REGGEN_VRFBG, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VRFBG); + break; + case REGU_VRF1: + reg_val = BITFVAL(MC13783_REGGEN_VRF1, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VRF1); + break; + case REGU_VRF2: + reg_val = BITFVAL(MC13783_REGGEN_VRF2, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VRF2); + break; + case REGU_VMMC1: + reg_val = BITFVAL(MC13783_REGGEN_VMMC1, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VMMC1); + break; + case REGU_VMMC2: + reg_val = BITFVAL(MC13783_REGGEN_VMMC2, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VMMC2); + break; + case REGU_GPO1: + reg_val = BITFVAL(MC13783_REGGEN_GPO1, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_GPO1); + break; + case REGU_GPO2: + reg_val = BITFVAL(MC13783_REGGEN_GPO2, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_GPO2); + break; + case REGU_GPO3: + reg_val = BITFVAL(MC13783_REGGEN_GPO3, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_GPO3); + break; + case REGU_GPO4: + reg_val = BITFVAL(MC13783_REGGEN_GPO4, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_GPO4); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(REG_REGEN_ASSIGNMENT, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets the Regen assignment for all regulator + * + * @param regulator type of regulator + * @param en_dis return value, if true : + * the regulator is enabled by regen. + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_get_regen_assig(t_pmic_regulator regulator, + bool * en_dis) +{ + unsigned int reg_val = 0, reg_mask = 0; + + switch (regulator) { + case REGU_VAUDIO: + reg_mask = BITFMASK(MC13783_REGGEN_VAUDIO); + break; + case REGU_VIOHI: + reg_mask = BITFMASK(MC13783_REGGEN_VIOHI); + break; + case REGU_VIOLO: + reg_mask = BITFMASK(MC13783_REGGEN_VIOLO); + break; + case REGU_VDIG: + reg_mask = BITFMASK(MC13783_REGGEN_VDIG); + break; + case REGU_VGEN: + reg_mask = BITFMASK(MC13783_REGGEN_VGEN); + break; + case REGU_VRFDIG: + reg_mask = BITFMASK(MC13783_REGGEN_VRFDIG); + break; + case REGU_VRFREF: + reg_mask = BITFMASK(MC13783_REGGEN_VRFREF); + break; + case REGU_VRFCP: + reg_mask = BITFMASK(MC13783_REGGEN_VRFCP); + break; + case REGU_VCAM: + reg_mask = BITFMASK(MC13783_REGGEN_VCAM); + break; + case REGU_VRFBG: + reg_mask = BITFMASK(MC13783_REGGEN_VRFBG); + break; + case REGU_VRF1: + reg_mask = BITFMASK(MC13783_REGGEN_VRF1); + break; + case REGU_VRF2: + reg_mask = BITFMASK(MC13783_REGGEN_VRF2); + break; + case REGU_VMMC1: + reg_mask = BITFMASK(MC13783_REGGEN_VMMC1); + break; + case REGU_VMMC2: + reg_mask = BITFMASK(MC13783_REGGEN_VMMC2); + break; + case REGU_GPO1: + reg_mask = BITFMASK(MC13783_REGGEN_GPO1); + break; + case REGU_GPO2: + reg_mask = BITFMASK(MC13783_REGGEN_GPO2); + break; + case REGU_GPO3: + reg_mask = BITFMASK(MC13783_REGGEN_GPO3); + break; + case REGU_GPO4: + reg_mask = BITFMASK(MC13783_REGGEN_GPO4); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(REG_REGEN_ASSIGNMENT, ®_val, reg_mask)); + + switch (regulator) { + case REGU_VAUDIO: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VAUDIO); + break; + case REGU_VIOHI: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VIOHI); + break; + case REGU_VIOLO: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VIOLO); + break; + case REGU_VDIG: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VDIG); + break; + case REGU_VGEN: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VGEN); + break; + case REGU_VRFDIG: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VRFDIG); + break; + case REGU_VRFREF: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VRFREF); + break; + case REGU_VRFCP: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VRFCP); + break; + case REGU_VCAM: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VCAM); + break; + case REGU_VRFBG: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VRFBG); + break; + case REGU_VRF1: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VRF1); + break; + case REGU_VRF2: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VRF2); + break; + case REGU_VMMC1: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VMMC1); + break; + case REGU_VMMC2: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VMMC2); + break; + case REGU_GPO1: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_GPO1); + break; + case REGU_GPO2: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_GPO2); + break; + case REGU_GPO3: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_GPO3); + break; + case REGU_GPO4: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_GPO4); + break; + default: + break; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets the Regen polarity. + * + * @param en_dis If true regen is inverted. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_set_regen_inv(bool en_dis) +{ + unsigned int reg_val = 0, reg_mask = 0; + + reg_val = BITFVAL(MC13783_REGGEN_INV, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_INV); + + CHECK_ERROR(pmic_write_reg(REG_REGEN_ASSIGNMENT, reg_val, reg_mask)); + return PMIC_SUCCESS; +} + +/*! + * This function gets the Regen polarity. + * + * @param en_dis If true regen is inverted. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_get_regen_inv(bool * en_dis) +{ + unsigned int reg_val = 0, reg_mask = 0; + + reg_mask = BITFMASK(MC13783_REGGEN_INV); + CHECK_ERROR(pmic_read_reg(REG_REGEN_ASSIGNMENT, ®_val, reg_mask)); + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_INV); + return PMIC_SUCCESS; +} + +/*! + * This function enables esim control voltage. + * Only on mc13783 2.0 or higher + * + * @param vesim if true, enable VESIMESIMEN + * @param vmmc1 if true, enable VMMC1ESIMEN + * @param vmmc2 if true, enable VMMC2ESIMEN + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_esim_v_en(bool vesim, bool vmmc1, bool vmmc2) +{ + unsigned int reg_val = 0, reg_mask = 0; + pmic_version_t mc13783_ver; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + reg_val = BITFVAL(MC13783_REGGEN_VESIMESIM, vesim) | + BITFVAL(MC13783_REGGEN_VMMC1ESIM, vesim) | + BITFVAL(MC13783_REGGEN_VMMC2ESIM, vesim); + reg_mask = BITFMASK(MC13783_REGGEN_VESIMESIM) | + BITFMASK(MC13783_REGGEN_VMMC1ESIM) | + BITFMASK(MC13783_REGGEN_VMMC2ESIM); + CHECK_ERROR(pmic_write_reg(REG_REGEN_ASSIGNMENT, + reg_val, reg_mask)); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function gets esim control voltage values. + * Only on mc13783 2.0 or higher + * + * @param vesim if true, enable VESIMESIMEN + * @param vmmc1 if true, enable VMMC1ESIMEN + * @param vmmc2 if true, enable VMMC2ESIMEN + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_gets_esim_v_state(bool * vesim, bool * vmmc1, + bool * vmmc2) +{ + unsigned int reg_val = 0, reg_mask = 0; + pmic_version_t mc13783_ver; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + reg_mask = BITFMASK(MC13783_REGGEN_VESIMESIM) | + BITFMASK(MC13783_REGGEN_VMMC1ESIM) | + BITFMASK(MC13783_REGGEN_VMMC2ESIM); + CHECK_ERROR(pmic_read_reg(REG_REGEN_ASSIGNMENT, + ®_val, reg_mask)); + *vesim = BITFEXT(reg_val, MC13783_REGGEN_VESIMESIM); + *vmmc1 = BITFEXT(reg_val, MC13783_REGGEN_VMMC1ESIM); + *vmmc2 = BITFEXT(reg_val, MC13783_REGGEN_VMMC2ESIM); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function enables auto reset after a system reset. + * + * @param en if true, the auto reset is enabled + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_set_auto_reset_en(bool en) +{ + unsigned int reg_val = 0, reg_mask = 0; + + reg_val = BITFVAL(MC13783_AUTO_RESTART, en); + reg_mask = BITFMASK(MC13783_AUTO_RESTART); + + CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_2, reg_val, reg_mask)); + return PMIC_SUCCESS; +} + +/*! + * This function gets auto reset configuration. + * + * @param en if true, the auto reset is enabled + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_get_auto_reset_en(bool * en) +{ + unsigned int reg_val = 0, reg_mask = 0; + + reg_mask = BITFMASK(MC13783_AUTO_RESTART); + CHECK_ERROR(pmic_read_reg(REG_POWER_CONTROL_2, ®_val, reg_mask)); + *en = BITFEXT(reg_val, MC13783_AUTO_RESTART); + return PMIC_SUCCESS; +} + +/*! + * This function configures a system reset on a button. + * + * @param bt type of button. + * @param sys_rst if true, enable the system reset on this button + * @param deb_time sets the debounce time on this button pin + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_set_conf_button(t_button bt, bool sys_rst, int deb_time) +{ + int max_val = 0; + unsigned int reg_val = 0, reg_mask = 0; + + max_val = (1 << MC13783_DEB_BT_ON1B_WID) - 1; + if (deb_time > max_val) { + return PMIC_PARAMETER_ERROR; + } + + switch (bt) { + case BT_ON1B: + reg_val = BITFVAL(MC13783_EN_BT_ON1B, sys_rst) | + BITFVAL(MC13783_DEB_BT_ON1B, deb_time); + reg_mask = BITFMASK(MC13783_EN_BT_ON1B) | + BITFMASK(MC13783_DEB_BT_ON1B); + break; + case BT_ON2B: + reg_val = BITFVAL(MC13783_EN_BT_ON2B, sys_rst) | + BITFVAL(MC13783_DEB_BT_ON2B, deb_time); + reg_mask = BITFMASK(MC13783_EN_BT_ON2B) | + BITFMASK(MC13783_DEB_BT_ON2B); + break; + case BT_ON3B: + reg_val = BITFVAL(MC13783_EN_BT_ON3B, sys_rst) | + BITFVAL(MC13783_DEB_BT_ON3B, deb_time); + reg_mask = BITFMASK(MC13783_EN_BT_ON3B) | + BITFMASK(MC13783_DEB_BT_ON3B); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_2, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets configuration of a button. + * + * @param bt type of button. + * @param sys_rst if true, the system reset is enabled on this button + * @param deb_time gets the debounce time on this button pin + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_get_conf_button(t_button bt, + bool * sys_rst, int *deb_time) +{ + unsigned int reg_val = 0, reg_mask = 0; + + switch (bt) { + case BT_ON1B: + reg_mask = BITFMASK(MC13783_EN_BT_ON1B) | + BITFMASK(MC13783_DEB_BT_ON1B); + break; + case BT_ON2B: + reg_mask = BITFMASK(MC13783_EN_BT_ON2B) | + BITFMASK(MC13783_DEB_BT_ON2B); + break; + case BT_ON3B: + reg_mask = BITFMASK(MC13783_EN_BT_ON3B) | + BITFMASK(MC13783_DEB_BT_ON3B); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(REG_POWER_CONTROL_2, ®_val, reg_mask)); + + switch (bt) { + case BT_ON1B: + *sys_rst = BITFEXT(reg_val, MC13783_EN_BT_ON1B); + *deb_time = BITFEXT(reg_val, MC13783_DEB_BT_ON1B); + break; + case BT_ON2B: + *sys_rst = BITFEXT(reg_val, MC13783_EN_BT_ON2B); + *deb_time = BITFEXT(reg_val, MC13783_DEB_BT_ON2B); + break; + case BT_ON3B: + *sys_rst = BITFEXT(reg_val, MC13783_EN_BT_ON3B); + *deb_time = BITFEXT(reg_val, MC13783_DEB_BT_ON3B); + break; + default: + return PMIC_PARAMETER_ERROR; + } + return PMIC_SUCCESS; +} + +/*! + * This function is used to un/subscribe on power event IT. + * + * @param event type of event. + * @param callback event callback function. + * @param sub define if Un/subscribe event. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_event(t_pwr_int event, void *callback, bool sub) +{ + pmic_event_callback_t power_callback; + type_event power_event; + + power_callback.func = callback; + power_callback.param = NULL; + switch (event) { + case PWR_IT_BPONI: + power_event = EVENT_BPONI; + break; + case PWR_IT_LOBATLI: + power_event = EVENT_LOBATLI; + break; + case PWR_IT_LOBATHI: + power_event = EVENT_LOBATHI; + break; + case PWR_IT_ONOFD1I: + power_event = EVENT_ONOFD1I; + break; + case PWR_IT_ONOFD2I: + power_event = EVENT_ONOFD2I; + break; + case PWR_IT_ONOFD3I: + power_event = EVENT_ONOFD3I; + break; + case PWR_IT_SYSRSTI: + power_event = EVENT_SYSRSTI; + break; + case PWR_IT_PWRRDYI: + power_event = EVENT_PWRRDYI; + break; + case PWR_IT_PCI: + power_event = EVENT_PCI; + break; + case PWR_IT_WARMI: + power_event = EVENT_WARMI; + break; + default: + return PMIC_PARAMETER_ERROR; + } + if (sub == true) { + CHECK_ERROR(pmic_event_subscribe(power_event, power_callback)); + } else { + CHECK_ERROR(pmic_event_unsubscribe + (power_event, power_callback)); + } + return PMIC_SUCCESS; +} + +/*! + * This function is used to subscribe on power event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_event_sub(t_pwr_int event, void *callback) +{ + return pmic_power_event(event, callback, true); +} + +/*! + * This function is used to un subscribe on power event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_event_unsub(t_pwr_int event, void *callback) +{ + return pmic_power_event(event, callback, false); +} + +void pmic_power_key_callback(void) +{ +#ifdef CONFIG_MXC_HWEVENT + /*read the power key is pressed or up */ + t_sensor_bits sense; + struct mxc_hw_event event = { HWE_POWER_KEY, 0 }; + + pmic_get_sensors(&sense); + if (sense.sense_onofd1s) { + pr_debug("PMIC Power key up\n"); + event.args = PWRK_UNPRESS; + } else { + pr_debug("PMIC Power key pressed\n"); + event.args = PWRK_PRESS; + } + /* send hw event */ + hw_event_send(HWE_DEF_PRIORITY, &event); +#endif +} + +static irqreturn_t power_key_int(int irq, void *dev_id) +{ + pr_info(KERN_INFO "on-off key pressed\n"); + + return 0; +} + +extern void gpio_power_key_active(void); +/* + * Init and Exit + */ + +static int pmic_power_probe(struct platform_device *pdev) +{ + int irq, ret; + + /* configure on/off button */ + gpio_power_key_active(); + + irq = (int)pdev->dev.platform_data; + + if (irq == 0) { + pr_info(KERN_INFO "PMIC Power has no platform data\n"); + goto done; + } + set_irq_type(irq, IRQF_TRIGGER_RISING); + + ret = request_irq(irq, power_key_int, 0, "power_key", 0); + if (ret) + pr_info(KERN_ERR "register on-off key interrupt failed\n"); + + set_irq_wake(irq, 1); + + done: + pr_info(KERN_INFO "PMIC Power successfully probed\n"); + return 0; +} + +static struct platform_driver pmic_power_driver_ldm = { + .driver = { + .name = "pmic_power", + }, + .suspend = pmic_power_suspend, + .resume = pmic_power_resume, + .probe = pmic_power_probe, + .remove = NULL, +}; + +static int __init pmic_power_init(void) +{ + pr_debug("PMIC Power driver loading..\n"); + pmic_power_event_sub(PWR_IT_ONOFD1I, pmic_power_key_callback); + /* set power off hook to mc13783 power off */ + pm_power_off = pmic_power_off; + return platform_driver_register(&pmic_power_driver_ldm); +} +static void __exit pmic_power_exit(void) +{ + pmic_power_event_unsub(PWR_IT_ONOFD1I, pmic_power_key_callback); + platform_driver_unregister(&pmic_power_driver_ldm); + pr_debug("PMIC Power driver successfully unloaded\n"); +} + +/* + * Module entry points + */ + +subsys_initcall_sync(pmic_power_init); +module_exit(pmic_power_exit); + +MODULE_DESCRIPTION("pmic_power driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_power_defs.h linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_power_defs.h --- linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_power_defs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_power_defs.h 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,509 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_power_defs.h + * @brief This is the internal header define of PMIC(mc13783) Power driver. + * + * @ingroup PMIC_POWER + */ + +/* + * Includes + */ + +#ifndef __MC13783_POWER_DEFS_H__ +#define __MC13783_POWER_DEFS_H__ + +/* + * Power Up Mode Sense bits + */ + +#define STATE_ICTEST_MASK 0x000001 + +#define STATE_CLKSEL_BIT 1 +#define STATE_CLKSEL_MASK 0x000002 + +#define STATE_PUMS1_BITS 2 +#define STATE_PUMS1_MASK 0x00000C + +#define STATE_PUMS2_BITS 4 +#define STATE_PUMS2_MASK 0x000030 + +#define STATE_PUMS3_BITS 6 +#define STATE_PUMS3_MASK 0x0000C0 + +#define STATE_CHRGM1_BITS 8 +#define STATE_CHRGM1_MASK 0x000300 + +#define STATE_CHRGM2_BITS 10 +#define STATE_CHRGM2_MASK 0x000C00 + +#define STATE_UMOD_BITS 12 +#define STATE_UMOD_MASK 0x003000 + +#define STATE_USBEN_BIT 14 +#define STATE_USBEN_MASK 0x004000 + +#define STATE_SW1A_J_B_BIT 15 +#define STATE_SW1A_J_B_MASK 0x008000 + +#define STATE_SW2A_J_B_BIT 16 +#define STATE_SW2A_J_B_MASK 0x010000 + +#define PC_COUNT_MAX 3 +#define PC_COUNT_MIN 0 +/* + * Reg Regen + */ +#define MC13783_REGGEN_VAUDIO_LSH 0 +#define MC13783_REGGEN_VAUDIO_WID 1 +#define MC13783_REGGEN_VIOHI_LSH 1 +#define MC13783_REGGEN_VIOHI_WID 1 +#define MC13783_REGGEN_VIOLO_LSH 2 +#define MC13783_REGGEN_VIOLO_WID 1 +#define MC13783_REGGEN_VDIG_LSH 3 +#define MC13783_REGGEN_VDIG_WID 1 +#define MC13783_REGGEN_VGEN_LSH 4 +#define MC13783_REGGEN_VGEN_WID 1 +#define MC13783_REGGEN_VRFDIG_LSH 5 +#define MC13783_REGGEN_VRFDIG_WID 1 +#define MC13783_REGGEN_VRFREF_LSH 6 +#define MC13783_REGGEN_VRFREF_WID 1 +#define MC13783_REGGEN_VRFCP_LSH 7 +#define MC13783_REGGEN_VRFCP_WID 1 +#define MC13783_REGGEN_VCAM_LSH 8 +#define MC13783_REGGEN_VCAM_WID 1 +#define MC13783_REGGEN_VRFBG_LSH 9 +#define MC13783_REGGEN_VRFBG_WID 1 +#define MC13783_REGGEN_VRF1_LSH 10 +#define MC13783_REGGEN_VRF1_WID 1 +#define MC13783_REGGEN_VRF2_LSH 11 +#define MC13783_REGGEN_VRF2_WID 1 +#define MC13783_REGGEN_VMMC1_LSH 12 +#define MC13783_REGGEN_VMMC1_WID 1 +#define MC13783_REGGEN_VMMC2_LSH 13 +#define MC13783_REGGEN_VMMC2_WID 1 +#define MC13783_REGGEN_GPO1_LSH 16 +#define MC13783_REGGEN_GPO1_WID 1 +#define MC13783_REGGEN_GPO2_LSH 17 +#define MC13783_REGGEN_GPO2_WID 1 +#define MC13783_REGGEN_GPO3_LSH 18 +#define MC13783_REGGEN_GPO3_WID 1 +#define MC13783_REGGEN_GPO4_LSH 19 +#define MC13783_REGGEN_GPO4_WID 1 +#define MC13783_REGGEN_INV_LSH 20 +#define MC13783_REGGEN_INV_WID 1 +#define MC13783_REGGEN_VESIMESIM_LSH 21 +#define MC13783_REGGEN_VESIMESIM_WID 1 +#define MC13783_REGGEN_VMMC1ESIM_LSH 22 +#define MC13783_REGGEN_VMMC1ESIM_WID 1 +#define MC13783_REGGEN_VMMC2ESIM_LSH 23 +#define MC13783_REGGEN_VMMC2ESIM_WID 1 + +/* + * Reg Power Control 0 + */ +#define MC13783_PWRCTRL_PCEN_LSH 0 +#define MC13783_PWRCTRL_PCEN_WID 1 +#define MC13783_PWRCTRL_PCEN_ENABLE 1 +#define MC13783_PWRCTRL_PCEN_DISABLE 0 +#define MC13783_PWRCTRL_PC_COUNT_EN_LSH 1 +#define MC13783_PWRCTRL_PC_COUNT_EN_WID 1 +#define MC13783_PWRCTRL_PC_COUNT_EN_ENABLE 1 +#define MC13783_PWRCTRL_PC_COUNT_EN_DISABLE 0 +#define MC13783_PWRCTRL_WARM_EN_LSH 2 +#define MC13783_PWRCTRL_WARM_EN_WID 1 +#define MC13783_PWRCTRL_WARM_EN_ENABLE 1 +#define MC13783_PWRCTRL_WARM_EN_DISABLE 0 +#define MC13783_PWRCTRL_USER_OFF_SPI_LSH 3 +#define MC13783_PWRCTRL_USER_OFF_SPI_WID 1 +#define MC13783_PWRCTRL_USER_OFF_SPI_ENABLE 1 +#define MC13783_PWRCTRL_USER_OFF_PC_LSH 4 +#define MC13783_PWRCTRL_USER_OFF_PC_WID 1 +#define MC13783_PWRCTRL_USER_OFF_PC_ENABLE 1 +#define MC13783_PWRCTRL_USER_OFF_PC_DISABLE 0 +#define MC13783_PWRCTRL_32OUT_USER_OFF_LSH 5 +#define MC13783_PWRCTRL_32OUT_USER_OFF_WID 1 +#define MC13783_PWRCTRL_32OUT_USER_OFF_ENABLE 1 +#define MC13783_PWRCTRL_32OUT_USER_OFF_DISABLE 0 +#define MC13783_PWRCTRL_32OUT_EN_LSH 6 +#define MC13783_PWRCTRL_32OUT_EN_WID 1 +#define MC13783_PWRCTRL_32OUT_EN_ENABLE 1 +#define MC13783_PWRCTRL_32OUT_EN_DISABLE 0 +#define MC13783_REGCTRL_VBKUP2AUTOMH_LSH 7 +#define MC13783_REGCTRL_VBKUP2AUTOMH_WID 1 +#define MC13783_PWRCTRL_VBKUP1_EN_LSH 8 +#define MC13783_PWRCTRL_VBKUP1_EN_WID 1 +#define MC13783_PWRCTRL_VBKUP_ENABLE 1 +#define MC13783_PWRCTRL_VBKUP_DISABLE 0 +#define MC13783_PWRCTRL_VBKUP1_AUTO_EN_LSH 9 +#define MC13783_PWRCTRL_VBKUP1_AUTO_EN_WID 1 +#define MC13783_PWRCTRL_VBKUP1_LSH 10 +#define MC13783_PWRCTRL_VBKUP1_WID 2 +#define MC13783_PWRCTRL_VBKUP2_EN_LSH 12 +#define MC13783_PWRCTRL_VBKUP2_EN_WID 1 +#define MC13783_PWRCTRL_VBKUP2_AUTO_EN_LSH 13 +#define MC13783_PWRCTRL_VBKUP2_AUTO_EN_WID 1 +#define MC13783_PWRCTRL_VBKUP2_LSH 14 +#define MC13783_PWRCTRL_VBKUP2_WID 2 +#define MC13783_REGCTRL_BATTDETEN_LSH 19 +#define MC13783_REGCTRL_BATTDETEN_WID 1 + +/* + * Reg Power Control 1 + */ +#define MC13783_PWRCTRL_PCT_LSH 0 +#define MC13783_PWRCTRL_PCT_WID 8 +#define MC13783_PWRCTRL_PC_COUNT_LSH 8 +#define MC13783_PWRCTRL_PC_COUNT_WID 4 +#define MC13783_PWRCTRL_PC_MAX_CNT_LSH 12 +#define MC13783_PWRCTRL_PC_MAX_CNT_WID 4 +#define MC13783_PWRCTRL_MEM_TMR_LSH 16 +#define MC13783_PWRCTRL_MEM_TMR_WID 4 +#define MC13783_PWRCTRL_MEM_ALLON_LSH 20 +#define MC13783_PWRCTRL_MEM_ALLON_WID 1 +#define MC13783_PWRCTRL_MEM_ALLON_ENABLE 1 +#define MC13783_PWRCTRL_MEM_ALLON_DISABLE 0 + +/* + * Reg Power Control 2 + */ +#define MC13783_AUTO_RESTART_LSH 0 +#define MC13783_AUTO_RESTART_WID 1 +#define MC13783_EN_BT_ON1B_LSH 1 +#define MC13783_EN_BT_ON1B_WID 1 +#define MC13783_EN_BT_ON2B_LSH 2 +#define MC13783_EN_BT_ON2B_WID 1 +#define MC13783_EN_BT_ON3B_LSH 3 +#define MC13783_EN_BT_ON3B_WID 1 +#define MC13783_DEB_BT_ON1B_LSH 4 +#define MC13783_DEB_BT_ON1B_WID 2 +#define MC13783_DEB_BT_ON2B_LSH 6 +#define MC13783_DEB_BT_ON2B_WID 2 +#define MC13783_DEB_BT_ON3B_LSH 8 +#define MC13783_DEB_BT_ON3B_WID 2 + +/* + * Reg Regulator Mode 0 + */ +#define MC13783_REGCTRL_VAUDIO_EN_LSH 0 +#define MC13783_REGCTRL_VAUDIO_EN_WID 1 +#define MC13783_REGCTRL_VAUDIO_EN_ENABLE 1 +#define MC13783_REGCTRL_VAUDIO_EN_DISABLE 0 +#define MC13783_REGCTRL_VAUDIO_STBY_LSH 1 +#define MC13783_REGCTRL_VAUDIO_STBY_WID 1 +#define MC13783_REGCTRL_VAUDIO_MODE_LSH 2 +#define MC13783_REGCTRL_VAUDIO_MODE_WID 1 +#define MC13783_REGCTRL_VIOHI_EN_LSH 3 +#define MC13783_REGCTRL_VIOHI_EN_WID 1 +#define MC13783_REGCTRL_VIOHI_EN_ENABLE 1 +#define MC13783_REGCTRL_VIOHI_EN_DISABLE 0 +#define MC13783_REGCTRL_VIOHI_STBY_LSH 4 +#define MC13783_REGCTRL_VIOHI_STBY_WID 1 +#define MC13783_REGCTRL_VIOHI_MODE_LSH 5 +#define MC13783_REGCTRL_VIOHI_MODE_WID 1 +#define MC13783_REGCTRL_VIOLO_EN_LSH 6 +#define MC13783_REGCTRL_VIOLO_EN_WID 1 +#define MC13783_REGCTRL_VIOLO_EN_ENABLE 1 +#define MC13783_REGCTRL_VIOLO_EN_DISABLE 0 +#define MC13783_REGCTRL_VIOLO_STBY_LSH 7 +#define MC13783_REGCTRL_VIOLO_STBY_WID 1 +#define MC13783_REGCTRL_VIOLO_MODE_LSH 8 +#define MC13783_REGCTRL_VIOLO_MODE_WID 1 +#define MC13783_REGCTRL_VDIG_EN_LSH 9 +#define MC13783_REGCTRL_VDIG_EN_WID 1 +#define MC13783_REGCTRL_VDIG_EN_ENABLE 1 +#define MC13783_REGCTRL_VDIG_EN_DISABLE 0 +#define MC13783_REGCTRL_VDIG_STBY_LSH 10 +#define MC13783_REGCTRL_VDIG_STBY_WID 1 +#define MC13783_REGCTRL_VDIG_MODE_LSH 11 +#define MC13783_REGCTRL_VDIG_MODE_WID 1 +#define MC13783_REGCTRL_VGEN_EN_LSH 12 +#define MC13783_REGCTRL_VGEN_EN_WID 1 +#define MC13783_REGCTRL_VGEN_EN_ENABLE 1 +#define MC13783_REGCTRL_VGEN_EN_DISABLE 0 +#define MC13783_REGCTRL_VGEN_STBY_LSH 13 +#define MC13783_REGCTRL_VGEN_STBY_WID 1 +#define MC13783_REGCTRL_VGEN_MODE_LSH 14 +#define MC13783_REGCTRL_VGEN_MODE_WID 1 +#define MC13783_REGCTRL_VRFDIG_EN_LSH 15 +#define MC13783_REGCTRL_VRFDIG_EN_WID 1 +#define MC13783_REGCTRL_VRFDIG_EN_ENABLE 1 +#define MC13783_REGCTRL_VRFDIG_EN_DISABLE 0 +#define MC13783_REGCTRL_VRFDIG_STBY_LSH 16 +#define MC13783_REGCTRL_VRFDIG_STBY_WID 1 +#define MC13783_REGCTRL_VRFDIG_MODE_LSH 17 +#define MC13783_REGCTRL_VRFDIG_MODE_WID 1 +#define MC13783_REGCTRL_VRFREF_EN_LSH 18 +#define MC13783_REGCTRL_VRFREF_EN_WID 1 +#define MC13783_REGCTRL_VRFREF_EN_ENABLE 1 +#define MC13783_REGCTRL_VRFREF_EN_DISABLE 0 +#define MC13783_REGCTRL_VRFREF_STBY_LSH 19 +#define MC13783_REGCTRL_VRFREF_STBY_WID 1 +#define MC13783_REGCTRL_VRFREF_MODE_LSH 20 +#define MC13783_REGCTRL_VRFREF_MODE_WID 1 +#define MC13783_REGCTRL_VRFCP_EN_LSH 21 +#define MC13783_REGCTRL_VRFCP_EN_WID 1 +#define MC13783_REGCTRL_VRFCP_EN_ENABLE 1 +#define MC13783_REGCTRL_VRFCP_EN_DISABLE 0 +#define MC13783_REGCTRL_VRFCP_STBY_LSH 22 +#define MC13783_REGCTRL_VRFCP_STBY_WID 1 +#define MC13783_REGCTRL_VRFCP_MODE_LSH 23 +#define MC13783_REGCTRL_VRFCP_MODE_WID 1 + +/* + * Reg Regulator Mode 1 + */ +#define MC13783_REGCTRL_VSIM_EN_LSH 0 +#define MC13783_REGCTRL_VSIM_EN_WID 1 +#define MC13783_REGCTRL_VSIM_EN_ENABLE 1 +#define MC13783_REGCTRL_VSIM_EN_DISABLE 0 +#define MC13783_REGCTRL_VSIM_STBY_LSH 1 +#define MC13783_REGCTRL_VSIM_STBY_WID 1 +#define MC13783_REGCTRL_VSIM_MODE_LSH 2 +#define MC13783_REGCTRL_VSIM_MODE_WID 1 +#define MC13783_REGCTRL_VESIM_EN_LSH 3 +#define MC13783_REGCTRL_VESIM_EN_WID 1 +#define MC13783_REGCTRL_VESIM_EN_ENABLE 1 +#define MC13783_REGCTRL_VESIM_EN_DISABLE 0 +#define MC13783_REGCTRL_VESIM_STBY_LSH 4 +#define MC13783_REGCTRL_VESIM_STBY_WID 1 +#define MC13783_REGCTRL_VESIM_MODE_LSH 5 +#define MC13783_REGCTRL_VESIM_MODE_WID 1 +#define MC13783_REGCTRL_VCAM_EN_LSH 6 +#define MC13783_REGCTRL_VCAM_EN_WID 1 +#define MC13783_REGCTRL_VCAM_EN_ENABLE 1 +#define MC13783_REGCTRL_VCAM_EN_DISABLE 0 +#define MC13783_REGCTRL_VCAM_STBY_LSH 7 +#define MC13783_REGCTRL_VCAM_STBY_WID 1 +#define MC13783_REGCTRL_VCAM_MODE_LSH 8 +#define MC13783_REGCTRL_VCAM_MODE_WID 1 +#define MC13783_REGCTRL_VRFBG_EN_LSH 9 +#define MC13783_REGCTRL_VRFBG_EN_WID 1 +#define MC13783_REGCTRL_VRFBG_EN_ENABLE 1 +#define MC13783_REGCTRL_VRFBG_EN_DISABLE 0 +#define MC13783_REGCTRL_VRFBG_STBY_LSH 10 +#define MC13783_REGCTRL_VRFBG_STBY_WID 1 +#define MC13783_REGCTRL_VVIB_EN_LSH 11 +#define MC13783_REGCTRL_VVIB_EN_WID 1 +#define MC13783_REGCTRL_VVIB_EN_ENABLE 1 +#define MC13783_REGCTRL_VVIB_EN_DISABLE 0 +#define MC13783_REGCTRL_VRF1_EN_LSH 12 +#define MC13783_REGCTRL_VRF1_EN_WID 1 +#define MC13783_REGCTRL_VRF1_EN_ENABLE 1 +#define MC13783_REGCTRL_VRF1_EN_DISABLE 0 +#define MC13783_REGCTRL_VRF1_STBY_LSH 13 +#define MC13783_REGCTRL_VRF1_STBY_WID 1 +#define MC13783_REGCTRL_VRF1_MODE_LSH 14 +#define MC13783_REGCTRL_VRF1_MODE_WID 1 +#define MC13783_REGCTRL_VRF2_EN_LSH 15 +#define MC13783_REGCTRL_VRF2_EN_WID 1 +#define MC13783_REGCTRL_VRF2_EN_ENABLE 1 +#define MC13783_REGCTRL_VRF2_EN_DISABLE 0 +#define MC13783_REGCTRL_VRF2_STBY_LSH 16 +#define MC13783_REGCTRL_VRF2_STBY_WID 1 +#define MC13783_REGCTRL_VRF2_MODE_LSH 17 +#define MC13783_REGCTRL_VRF2_MODE_WID 1 +#define MC13783_REGCTRL_VMMC1_EN_LSH 18 +#define MC13783_REGCTRL_VMMC1_EN_WID 1 +#define MC13783_REGCTRL_VMMC1_EN_ENABLE 1 +#define MC13783_REGCTRL_VMMC1_EN_DISABLE 0 +#define MC13783_REGCTRL_VMMC1_STBY_LSH 19 +#define MC13783_REGCTRL_VMMC1_STBY_WID 1 +#define MC13783_REGCTRL_VMMC1_MODE_LSH 20 +#define MC13783_REGCTRL_VMMC1_MODE_WID 1 +#define MC13783_REGCTRL_VMMC2_EN_LSH 21 +#define MC13783_REGCTRL_VMMC2_EN_WID 1 +#define MC13783_REGCTRL_VMMC2_EN_ENABLE 1 +#define MC13783_REGCTRL_VMMC2_EN_DISABLE 0 +#define MC13783_REGCTRL_VMMC2_STBY_LSH 22 +#define MC13783_REGCTRL_VMMC2_STBY_WID 1 +#define MC13783_REGCTRL_VMMC2_MODE_LSH 23 +#define MC13783_REGCTRL_VMMC2_MODE_WID 1 + +/* + * Reg Regulator Misc. + */ +#define MC13783_REGCTRL_GPO1_EN_LSH 6 +#define MC13783_REGCTRL_GPO1_EN_WID 1 +#define MC13783_REGCTRL_GPO1_EN_ENABLE 1 +#define MC13783_REGCTRL_GPO1_EN_DISABLE 0 +#define MC13783_REGCTRL_GPO2_EN_LSH 8 +#define MC13783_REGCTRL_GPO2_EN_WID 1 +#define MC13783_REGCTRL_GPO2_EN_ENABLE 1 +#define MC13783_REGCTRL_GPO2_EN_DISABLE 0 +#define MC13783_REGCTRL_GPO3_EN_LSH 10 +#define MC13783_REGCTRL_GPO3_EN_WID 1 +#define MC13783_REGCTRL_GPO3_EN_ENABLE 1 +#define MC13783_REGCTRL_GPO3_EN_DISABLE 0 +#define MC13783_REGCTRL_GPO4_EN_LSH 12 +#define MC13783_REGCTRL_GPO4_EN_WID 1 +#define MC13783_REGCTRL_GPO4_EN_ENABLE 1 +#define MC13783_REGCTRL_GPO4_EN_DISABLE 0 +#define MC13783_REGCTRL_VIBPINCTRL_LSH 14 +#define MC13783_REGCTRL_VIBPINCTRL_WID 1 + +/* + * Reg Regulator Setting 0 + */ +#define MC13783_REGSET_VIOLO_LSH 2 +#define MC13783_REGSET_VIOLO_WID 2 +#define MC13783_REGSET_VDIG_LSH 4 +#define MC13783_REGSET_VDIG_WID 2 +#define MC13783_REGSET_VGEN_LSH 6 +#define MC13783_REGSET_VGEN_WID 3 +#define MC13783_REGSET_VRFDIG_LSH 9 +#define MC13783_REGSET_VRFDIG_WID 2 +#define MC13783_REGSET_VRFREF_LSH 11 +#define MC13783_REGSET_VRFREF_WID 2 +#define MC13783_REGSET_VRFCP_LSH 13 +#define MC13783_REGSET_VRFCP_WID 1 +#define MC13783_REGSET_VSIM_LSH 14 +#define MC13783_REGSET_VSIM_WID 1 +#define MC13783_REGSET_VESIM_LSH 15 +#define MC13783_REGSET_VESIM_WID 1 +#define MC13783_REGSET_VCAM_LSH 16 +#define MC13783_REGSET_VCAM_WID 3 + +/* + * Reg Regulator Setting 1 + */ +#define MC13783_REGSET_VVIB_LSH 0 +#define MC13783_REGSET_VVIB_WID 2 +#define MC13783_REGSET_VRF1_LSH 2 +#define MC13783_REGSET_VRF1_WID 2 +#define MC13783_REGSET_VRF2_LSH 4 +#define MC13783_REGSET_VRF2_WID 2 +#define MC13783_REGSET_VMMC1_LSH 6 +#define MC13783_REGSET_VMMC1_WID 3 +#define MC13783_REGSET_VMMC2_LSH 9 +#define MC13783_REGSET_VMMC2_WID 3 + +/* + * Reg Switcher 0 + */ +#define MC13783_SWSET_SW1A_LSH 0 +#define MC13783_SWSET_SW1A_WID 6 +#define MC13783_SWSET_SW1A_DVS_LSH 6 +#define MC13783_SWSET_SW1A_DVS_WID 6 +#define MC13783_SWSET_SW1A_STDBY_LSH 12 +#define MC13783_SWSET_SW1A_STDBY_WID 6 + +/* + * Reg Switcher 1 + */ +#define MC13783_SWSET_SW1B_LSH 0 +#define MC13783_SWSET_SW1B_WID 6 +#define MC13783_SWSET_SW1B_DVS_LSH 6 +#define MC13783_SWSET_SW1B_DVS_WID 6 +#define MC13783_SWSET_SW1B_STDBY_LSH 12 +#define MC13783_SWSET_SW1B_STDBY_WID 6 + +/* + * Reg Switcher 2 + */ +#define MC13783_SWSET_SW2A_LSH 0 +#define MC13783_SWSET_SW2A_WID 6 +#define MC13783_SWSET_SW2A_DVS_LSH 6 +#define MC13783_SWSET_SW2A_DVS_WID 6 +#define MC13783_SWSET_SW2A_STDBY_LSH 12 +#define MC13783_SWSET_SW2A_STDBY_WID 6 + +/* + * Reg Switcher 3 + */ +#define MC13783_SWSET_SW2B_LSH 0 +#define MC13783_SWSET_SW2B_WID 6 +#define MC13783_SWSET_SW2B_DVS_LSH 6 +#define MC13783_SWSET_SW2B_DVS_WID 6 +#define MC13783_SWSET_SW2B_STDBY_LSH 12 +#define MC13783_SWSET_SW2B_STDBY_WID 6 + +/* + * Reg Switcher 4 + */ +#define MC13783_SWCTRL_SW1A_MODE_LSH 0 +#define MC13783_SWCTRL_SW1A_MODE_WID 2 +#define MC13783_SWCTRL_SW1A_STBY_MODE_LSH 2 +#define MC13783_SWCTRL_SW1A_STBY_MODE_WID 2 +#define MC13783_SWCTRL_SW1A_DVS_SPEED_LSH 6 +#define MC13783_SWCTRL_SW1A_DVS_SPEED_WID 2 +#define MC13783_SWCTRL_SW1A_PANIC_MODE_LSH 8 +#define MC13783_SWCTRL_SW1A_PANIC_MODE_WID 1 +#define MC13783_SWCTRL_SW1A_SOFTSTART_LSH 9 +#define MC13783_SWCTRL_SW1A_SOFTSTART_WID 1 +#define MC13783_SWCTRL_SW1B_MODE_LSH 10 +#define MC13783_SWCTRL_SW1B_MODE_WID 2 +#define MC13783_SWCTRL_SW1B_STBY_MODE_LSH 12 +#define MC13783_SWCTRL_SW1B_STBY_MODE_WID 2 +#define MC13783_SWCTRL_SW1B_DVS_SPEED_LSH 14 +#define MC13783_SWCTRL_SW1B_DVS_SPEED_WID 2 +#define MC13783_SWCTRL_SW1B_PANIC_MODE_LSH 16 +#define MC13783_SWCTRL_SW1B_PANIC_MODE_WID 1 +#define MC13783_SWCTRL_SW1B_SOFTSTART_LSH 17 +#define MC13783_SWCTRL_SW1B_SOFTSTART_WID 1 +#define MC13783_SWCTRL_PLL_EN_LSH 18 +#define MC13783_SWCTRL_PLL_EN_WID 1 +#define MC13783_SWCTRL_PLL_EN_ENABLE 1 +#define MC13783_SWCTRL_PLL_EN_DISABLE 0 +#define MC13783_SWCTRL_PLL_FACTOR_LSH 19 +#define MC13783_SWCTRL_PLL_FACTOR_WID 3 + +/* + * Reg Switcher 5 + */ +#define MC13783_SWCTRL_SW2A_MODE_LSH 0 +#define MC13783_SWCTRL_SW2A_MODE_WID 2 +#define MC13783_SWCTRL_SW2A_STBY_MODE_LSH 2 +#define MC13783_SWCTRL_SW2A_STBY_MODE_WID 2 +#define MC13783_SWCTRL_SW2A_DVS_SPEED_LSH 6 +#define MC13783_SWCTRL_SW2A_DVS_SPEED_WID 2 +#define MC13783_SWCTRL_SW2A_PANIC_MODE_LSH 8 +#define MC13783_SWCTRL_SW2A_PANIC_MODE_WID 1 +#define MC13783_SWCTRL_SW2A_SOFTSTART_LSH 9 +#define MC13783_SWCTRL_SW2A_SOFTSTART_WID 1 +#define MC13783_SWCTRL_SW2B_MODE_LSH 10 +#define MC13783_SWCTRL_SW2B_MODE_WID 2 +#define MC13783_SWCTRL_SW2B_STBY_MODE_LSH 12 +#define MC13783_SWCTRL_SW2B_STBY_MODE_WID 2 +#define MC13783_SWCTRL_SW2B_DVS_SPEED_LSH 14 +#define MC13783_SWCTRL_SW2B_DVS_SPEED_WID 2 +#define MC13783_SWCTRL_SW2B_PANIC_MODE_LSH 16 +#define MC13783_SWCTRL_SW2B_PANIC_MODE_WID 1 +#define MC13783_SWCTRL_SW2B_SOFTSTART_LSH 17 +#define MC13783_SWCTRL_SW2B_SOFTSTART_WID 1 +#define MC13783_SWSET_SW3_LSH 18 +#define MC13783_SWSET_SW3_WID 2 +#define MC13783_SWCTRL_SW3_EN_LSH 20 +#define MC13783_SWCTRL_SW3_EN_WID 2 +#define MC13783_SWCTRL_SW3_EN_ENABLE 1 +#define MC13783_SWCTRL_SW3_EN_DISABLE 0 +#define MC13783_SWCTRL_SW3_STBY_LSH 21 +#define MC13783_SWCTRL_SW3_STBY_WID 1 +#define MC13783_SWCTRL_SW3_MODE_LSH 22 +#define MC13783_SWCTRL_SW3_MODE_WID 1 + +/* + * Switcher configuration + */ +#define MC13783_SWCTRL_SW_MODE_SYNC_RECT_EN 0 +#define MC13783_SWCTRL_SW_MODE_PULSE_NO_SKIP_EN 1 +#define MC13783_SWCTRL_SW_MODE_PULSE_SKIP_EN 2 +#define MC13783_SWCTRL_SW_MODE_LOW_POWER_EN 3 +#define MC13783_REGTRL_LP_MODE_ENABLE 1 +#define MC13783_REGTRL_LP_MODE_DISABLE 0 +#define MC13783_REGTRL_STBY_MODE_ENABLE 1 +#define MC13783_REGTRL_STBY_MODE_DISABLE 0 + +#endif /* __MC13783_POWER_DEFS_H__ */ diff -urN linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_rtc.c linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_rtc.c --- linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_rtc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_rtc.c 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,552 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_rtc.c + * @brief This is the main file of PMIC(mc13783) RTC driver. + * + * @ingroup PMIC_RTC + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include + +#include "pmic_rtc_defs.h" + +#define PMIC_LOAD_ERROR_MSG \ +"PMIC card was not correctly detected. Stop loading PMIC RTC driver\n" + +/* + * Global variables + */ +static int pmic_rtc_major; +static void callback_alarm_asynchronous(void *); +static void callback_alarm_synchronous(void *); +static unsigned int pmic_rtc_poll(struct file *file, poll_table * wait); +static DECLARE_WAIT_QUEUE_HEAD(queue_alarm); +static DECLARE_WAIT_QUEUE_HEAD(pmic_rtc_wait); +static pmic_event_callback_t alarm_callback; +static pmic_event_callback_t rtc_callback; +static int pmic_rtc_detected = 0; +static bool pmic_rtc_done = 0; +static struct class *pmic_rtc_class; + +static DECLARE_MUTEX(mutex); + +/* EXPORTED FUNCTIONS */ +EXPORT_SYMBOL(pmic_rtc_set_time); +EXPORT_SYMBOL(pmic_rtc_get_time); +EXPORT_SYMBOL(pmic_rtc_set_time_alarm); +EXPORT_SYMBOL(pmic_rtc_get_time_alarm); +EXPORT_SYMBOL(pmic_rtc_wait_alarm); +EXPORT_SYMBOL(pmic_rtc_event_sub); +EXPORT_SYMBOL(pmic_rtc_event_unsub); +EXPORT_SYMBOL(pmic_rtc_loaded); + +/* + * Real Time Clock Pmic API + */ + +/*! + * This is the callback function called on TSI Pmic event, used in asynchronous + * call. + */ +static void callback_alarm_asynchronous(void *unused) +{ + pmic_rtc_done = true; +} + +/*! + * This is the callback function is used in test code for (un)sub. + */ +static void callback_test_sub(void) +{ + printk(KERN_INFO "*****************************************\n"); + printk(KERN_INFO "***** PMIC RTC 'Alarm IT CallBack' ******\n"); + printk(KERN_INFO "*****************************************\n"); +} + +/*! + * This is the callback function called on TSI Pmic event, used in synchronous + * call. + */ +static void callback_alarm_synchronous(void *unused) +{ + printk(KERN_INFO "*** Alarm IT Pmic ***\n"); + wake_up(&queue_alarm); +} + +/*! + * This function wait the Alarm event + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_rtc_wait_alarm(void) +{ + DEFINE_WAIT(wait); + alarm_callback.func = callback_alarm_synchronous; + alarm_callback.param = NULL; + CHECK_ERROR(pmic_event_subscribe(EVENT_TODAI, alarm_callback)); + prepare_to_wait(&queue_alarm, &wait, TASK_UNINTERRUPTIBLE); + schedule(); + finish_wait(&queue_alarm, &wait); + CHECK_ERROR(pmic_event_unsubscribe(EVENT_TODAI, alarm_callback)); + return PMIC_SUCCESS; +} + +/*! + * This function set the real time clock of PMIC + * + * @param pmic_time value of date and time + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_rtc_set_time(struct timeval * pmic_time) +{ + unsigned int tod_reg_val = 0; + unsigned int day_reg_val = 0; + unsigned int mask, value; + + tod_reg_val = pmic_time->tv_sec % 86400; + day_reg_val = pmic_time->tv_sec / 86400; + + mask = BITFMASK(MC13783_RTCTIME_TIME); + value = BITFVAL(MC13783_RTCTIME_TIME, tod_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_TIME, value, mask)); + + mask = BITFMASK(MC13783_RTCDAY_DAY); + value = BITFVAL(MC13783_RTCDAY_DAY, day_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_DAY, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function get the real time clock of PMIC + * + * @param pmic_time return value of date and time + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_rtc_get_time(struct timeval * pmic_time) +{ + unsigned int tod_reg_val = 0; + unsigned int day_reg_val = 0; + unsigned int mask, value; + + mask = BITFMASK(MC13783_RTCTIME_TIME); + CHECK_ERROR(pmic_read_reg(REG_RTC_TIME, &value, mask)); + tod_reg_val = BITFEXT(value, MC13783_RTCTIME_TIME); + + mask = BITFMASK(MC13783_RTCDAY_DAY); + CHECK_ERROR(pmic_read_reg(REG_RTC_DAY, &value, mask)); + day_reg_val = BITFEXT(value, MC13783_RTCDAY_DAY); + + pmic_time->tv_sec = (unsigned long)((unsigned long)(tod_reg_val & + 0x0001FFFF) + + (unsigned long)(day_reg_val * + 86400)); + return PMIC_SUCCESS; +} + +/*! + * This function set the real time clock alarm of PMIC + * + * @param pmic_time value of date and time + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_rtc_set_time_alarm(struct timeval * pmic_time) +{ + unsigned int tod_reg_val = 0; + unsigned int day_reg_val = 0; + unsigned int mask, value; + int ret; + + if ((ret = down_interruptible(&mutex)) < 0) + return ret; + + tod_reg_val = pmic_time->tv_sec % 86400; + day_reg_val = pmic_time->tv_sec / 86400; + + mask = BITFMASK(MC13783_RTCALARM_TIME); + value = BITFVAL(MC13783_RTCALARM_TIME, tod_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_ALARM, value, mask)); + + mask = BITFMASK(MC13783_RTCALARM_DAY); + value = BITFVAL(MC13783_RTCALARM_DAY, day_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_DAY_ALARM, value, mask)); + up(&mutex); + return PMIC_SUCCESS; +} + +/*! + * This function get the real time clock alarm of PMIC + * + * @param pmic_time return value of date and time + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_rtc_get_time_alarm(struct timeval * pmic_time) +{ + unsigned int tod_reg_val = 0; + unsigned int day_reg_val = 0; + unsigned int mask, value; + + mask = BITFMASK(MC13783_RTCALARM_TIME); + CHECK_ERROR(pmic_read_reg(REG_RTC_ALARM, &value, mask)); + tod_reg_val = BITFEXT(value, MC13783_RTCALARM_TIME); + + mask = BITFMASK(MC13783_RTCALARM_DAY); + CHECK_ERROR(pmic_read_reg(REG_RTC_DAY_ALARM, &value, mask)); + day_reg_val = BITFEXT(value, MC13783_RTCALARM_DAY); + + pmic_time->tv_sec = (unsigned long)((unsigned long)(tod_reg_val & + 0x0001FFFF) + + (unsigned long)(day_reg_val * + 86400)); + + return PMIC_SUCCESS; +} + +/*! + * This function is used to un/subscribe on RTC event IT. + * + * @param event type of event. + * @param callback event callback function. + * @param sub define if Un/subscribe event. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_rtc_event(t_rtc_int event, void *callback, bool sub) +{ + type_event rtc_event; + if (callback == NULL) { + return PMIC_ERROR; + } else { + rtc_callback.func = callback; + rtc_callback.param = NULL; + } + switch (event) { + case RTC_IT_ALARM: + rtc_event = EVENT_TODAI; + break; + case RTC_IT_1HZ: + rtc_event = EVENT_E1HZI; + break; + case RTC_IT_RST: + rtc_event = EVENT_RTCRSTI; + break; + default: + return PMIC_PARAMETER_ERROR; + } + if (sub == true) { + CHECK_ERROR(pmic_event_subscribe(rtc_event, rtc_callback)); + } else { + CHECK_ERROR(pmic_event_unsubscribe(rtc_event, rtc_callback)); + } + return PMIC_SUCCESS; +} + +/*! + * This function is used to subscribe on RTC event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_rtc_event_sub(t_rtc_int event, void *callback) +{ + CHECK_ERROR(pmic_rtc_event(event, callback, true)); + return PMIC_SUCCESS; +} + +/*! + * This function is used to un subscribe on RTC event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_rtc_event_unsub(t_rtc_int event, void *callback) +{ + CHECK_ERROR(pmic_rtc_event(event, callback, false)); + return PMIC_SUCCESS; +} + +/* Called without the kernel lock - fine */ +static unsigned int pmic_rtc_poll(struct file *file, poll_table * wait) +{ + /*poll_wait(file, &pmic_rtc_wait, wait); */ + + if (pmic_rtc_done) + return POLLIN | POLLRDNORM; + return 0; +} + +/*! + * This function implements IOCTL controls on a PMIC RTC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @param cmd the command + * @param arg the parameter + * @return This function returns 0 if successful. + */ +static int pmic_rtc_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + struct timeval *pmic_time = NULL; + + if (_IOC_TYPE(cmd) != 'p') + return -ENOTTY; + + if (arg) { + if ((pmic_time = kmalloc(sizeof(struct timeval), + GFP_KERNEL)) == NULL) { + return -ENOMEM; + } + /* if (copy_from_user(pmic_time, (struct timeval *)arg, + sizeof(struct timeval))) { + return -EFAULT; + } */ + } + + switch (cmd) { + case PMIC_RTC_SET_TIME: + if (copy_from_user(pmic_time, (struct timeval *)arg, + sizeof(struct timeval))) { + return -EFAULT; + } + pr_debug("SET RTC\n"); + CHECK_ERROR(pmic_rtc_set_time(pmic_time)); + break; + case PMIC_RTC_GET_TIME: + if (copy_to_user((struct timeval *)arg, pmic_time, + sizeof(struct timeval))) { + return -EFAULT; + } + pr_debug("GET RTC\n"); + CHECK_ERROR(pmic_rtc_get_time(pmic_time)); + break; + case PMIC_RTC_SET_ALARM: + if (copy_from_user(pmic_time, (struct timeval *)arg, + sizeof(struct timeval))) { + return -EFAULT; + } + pr_debug("SET RTC ALARM\n"); + CHECK_ERROR(pmic_rtc_set_time_alarm(pmic_time)); + break; + case PMIC_RTC_GET_ALARM: + if (copy_to_user((struct timeval *)arg, pmic_time, + sizeof(struct timeval))) { + return -EFAULT; + } + pr_debug("GET RTC ALARM\n"); + CHECK_ERROR(pmic_rtc_get_time_alarm(pmic_time)); + break; + case PMIC_RTC_WAIT_ALARM: + printk(KERN_INFO "WAIT ALARM...\n"); + CHECK_ERROR(pmic_rtc_event_sub(RTC_IT_ALARM, + callback_test_sub)); + CHECK_ERROR(pmic_rtc_wait_alarm()); + printk(KERN_INFO "ALARM DONE\n"); + CHECK_ERROR(pmic_rtc_event_unsub(RTC_IT_ALARM, + callback_test_sub)); + break; + case PMIC_RTC_ALARM_REGISTER: + printk(KERN_INFO "PMIC RTC ALARM REGISTER\n"); + alarm_callback.func = callback_alarm_asynchronous; + alarm_callback.param = NULL; + CHECK_ERROR(pmic_event_subscribe(EVENT_TODAI, alarm_callback)); + break; + case PMIC_RTC_ALARM_UNREGISTER: + printk(KERN_INFO "PMIC RTC ALARM UNREGISTER\n"); + alarm_callback.func = callback_alarm_asynchronous; + alarm_callback.param = NULL; + CHECK_ERROR(pmic_event_unsubscribe + (EVENT_TODAI, alarm_callback)); + pmic_rtc_done = false; + break; + default: + pr_debug("%d unsupported ioctl command\n", (int)cmd); + return -EINVAL; + } + + if (arg) { + if (copy_to_user((struct timeval *)arg, pmic_time, + sizeof(struct timeval))) { + return -EFAULT; + } + kfree(pmic_time); + } + + return 0; +} + +/*! + * This function implements the open method on a PMIC RTC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int pmic_rtc_open(struct inode *inode, struct file *file) +{ + return 0; +} + +/*! + * This function implements the release method on a PMIC RTC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int pmic_rtc_release(struct inode *inode, struct file *file) +{ + return 0; +} + +/*! + * This function is called to put the RTC in a low power state. + * There is no need for power handlers for the RTC device. + * The RTC cannot be suspended. + * + * @param pdev the device structure used to give information on which RTC + * device (0 through 3 channels) to suspend + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int pmic_rtc_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +/*! + * This function is called to resume the RTC from a low power state. + * + * @param pdev the device structure used to give information on which RTC + * device (0 through 3 channels) to suspend + * + * @return The function always returns 0. + */ +static int pmic_rtc_resume(struct platform_device *pdev) +{ + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ + +static struct file_operations pmic_rtc_fops = { + .owner = THIS_MODULE, + .ioctl = pmic_rtc_ioctl, + .poll = pmic_rtc_poll, + .open = pmic_rtc_open, + .release = pmic_rtc_release, +}; + +int pmic_rtc_loaded(void) +{ + return pmic_rtc_detected; +} + +static int pmic_rtc_remove(struct platform_device *pdev) +{ + device_destroy(pmic_rtc_class, MKDEV(pmic_rtc_major, 0)); + class_destroy(pmic_rtc_class); + unregister_chrdev(pmic_rtc_major, "pmic_rtc"); + return 0; +} + +static int pmic_rtc_probe(struct platform_device *pdev) +{ + int ret = 0; + struct device *temp_class; + + pmic_rtc_major = register_chrdev(0, "pmic_rtc", &pmic_rtc_fops); + if (pmic_rtc_major < 0) { + printk(KERN_ERR "Unable to get a major for pmic_rtc\n"); + return pmic_rtc_major; + } + + pmic_rtc_class = class_create(THIS_MODULE, "pmic_rtc"); + if (IS_ERR(pmic_rtc_class)) { + printk(KERN_ERR "Error creating pmic rtc class.\n"); + ret = PTR_ERR(pmic_rtc_class); + goto err_out1; + } + + temp_class = device_create(pmic_rtc_class, NULL, + MKDEV(pmic_rtc_major, 0), + "pmic_rtc"); + if (IS_ERR(temp_class)) { + printk(KERN_ERR "Error creating pmic rtc class device.\n"); + ret = PTR_ERR(temp_class); + goto err_out2; + } + + pmic_rtc_detected = 1; + printk(KERN_INFO "PMIC RTC successfully probed\n"); + return ret; + + err_out2: + class_destroy(pmic_rtc_class); + err_out1: + unregister_chrdev(pmic_rtc_major, "pmic_rtc"); + return ret; +} + +static struct platform_driver pmic_rtc_driver_ldm = { + .driver = { + .name = "pmic_rtc", + .owner = THIS_MODULE, + }, + .suspend = pmic_rtc_suspend, + .resume = pmic_rtc_resume, + .probe = pmic_rtc_probe, + .remove = pmic_rtc_remove, +}; + +static int __init pmic_rtc_init(void) +{ + pr_debug("PMIC RTC driver loading...\n"); + return platform_driver_register(&pmic_rtc_driver_ldm); +} +static void __exit pmic_rtc_exit(void) +{ + platform_driver_unregister(&pmic_rtc_driver_ldm); + pr_debug("PMIC RTC driver successfully unloaded\n"); +} + +/* + * Module entry points + */ + +subsys_initcall(pmic_rtc_init); +module_exit(pmic_rtc_exit); + +MODULE_DESCRIPTION("Pmic_rtc driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_rtc_defs.h linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_rtc_defs.h --- linux-2.6.26/drivers/mxc/pmic/mc13783/pmic_rtc_defs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13783/pmic_rtc_defs.h 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,47 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MC13783_RTC_DEFS_H__ +#define __MC13783_RTC_DEFS_H__ + +/*! + * @file mc13783/pmic_rtc_defs.h + * @brief This is the internal header of PMIC(mc13783) RTC driver. + * + * @ingroup PMIC_RTC + */ + +/* + * RTC Time + */ +#define MC13783_RTCTIME_TIME_LSH 0 +#define MC13783_RTCTIME_TIME_WID 17 + +/* + * RTC Alarm + */ +#define MC13783_RTCALARM_TIME_LSH 0 +#define MC13783_RTCALARM_TIME_WID 17 + +/* + * RTC Day + */ +#define MC13783_RTCDAY_DAY_LSH 0 +#define MC13783_RTCDAY_DAY_WID 15 + +/* + * RTC Day alarm + */ +#define MC13783_RTCALARM_DAY_LSH 0 +#define MC13783_RTCALARM_DAY_WID 15 + +#endif /* __MC13783_RTC_DEFS_H__ */ diff -urN linux-2.6.26/drivers/mxc/pmic/mc13892/Kconfig linux-2.6.26-lab126/drivers/mxc/pmic/mc13892/Kconfig --- linux-2.6.26/drivers/mxc/pmic/mc13892/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13892/Kconfig 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,48 @@ +# +# PMIC Modules configuration +# + +config MXC_MC13892_ADC + tristate "MC13892 ADC support" + depends on MXC_PMIC_MC13892 + ---help--- + This is the MC13892 ADC module driver. This module provides kernel API + for the ADC system of MC13892. + It controls also the touch screen interface. + If you want MC13892 ADC support, you should say Y here + +config MXC_MC13892_RTC + tristate "MC13892 Real Time Clock (RTC) support" + depends on MXC_PMIC_MC13892 + ---help--- + This is the MC13892 RTC module driver. This module provides kernel API + for RTC part of MC13892. + If you want MC13892 RTC support, you should say Y here +config MXC_MC13892_LIGHT + tristate "MC13892 Light and Backlight support" + depends on MXC_PMIC_MC13892 + ---help--- + This is the MC13892 Light module driver. This module provides kernel API + for led and backlight control part of MC13892. + If you want MC13892 Light support, you should say Y here +config MXC_MC13892_BATTERY + tristate "MC13892 Battery API support" + depends on MXC_PMIC_MC13892 + ---help--- + This is the MC13892 battery module driver. This module provides kernel API + for battery control part of MC13892. + If you want MC13892 battery support, you should say Y here +config MXC_MC13892_CONNECTIVITY + tristate "MC13892 Connectivity API support" + depends on MXC_PMIC_MC13892 + ---help--- + This is the MC13892 connectivity module driver. This module provides kernel API + for USB/RS232 connectivity control part of MC13892. + If you want MC13892 connectivity support, you should say Y here +config MXC_MC13892_POWER + tristate "MC13892 Power API support" + depends on MXC_PMIC_MC13892 + ---help--- + This is the MC13892 power and supplies module driver. This module provides kernel API + for power and regulator control part of MC13892. + If you want MC13892 power support, you should say Y here diff -urN linux-2.6.26/drivers/mxc/pmic/mc13892/Makefile linux-2.6.26-lab126/drivers/mxc/pmic/mc13892/Makefile --- linux-2.6.26/drivers/mxc/pmic/mc13892/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13892/Makefile 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,10 @@ +# +# Makefile for the mc13783 pmic drivers. +# + +obj-$(CONFIG_MXC_MC13892_ADC) += pmic_adc.o +obj-$(CONFIG_MXC_MC13892_RTC) += pmic_rtc.o +obj-$(CONFIG_MXC_MC13892_LIGHT) += pmic_light.o +#obj-$(CONFIG_MXC_MC13892_BATTERY) += pmic_battery.o +#obj-$(CONFIG_MXC_MC13892_CONNECTIVITY) += pmic_convity.o +obj-$(CONFIG_MXC_MC13892_POWER) += pmic_power.o diff -urN linux-2.6.26/drivers/mxc/pmic/mc13892/pmic_adc.c linux-2.6.26-lab126/drivers/mxc/pmic/mc13892/pmic_adc.c --- linux-2.6.26/drivers/mxc/pmic/mc13892/pmic_adc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13892/pmic_adc.c 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,978 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "../core/pmic.h" + +#define DEF_ADC_0 0x008000 +#define DEF_ADC_3 0x0001c0 + +#define ADC_NB_AVAILABLE 2 + +#define MAX_CHANNEL 7 + +#define MC13892_ADC0_TS_M_LSH 14 +#define MC13892_ADC0_TS_M_WID 3 + +/* + * Maximun allowed variation in the three X/Y co-ordinates acquired from + * touch-screen + */ +#define DELTA_Y_MAX 50 +#define DELTA_X_MAX 50 + +/* + * ADC 0 + */ +#define ADC_WAIT_TSI_0 0x001400 + +#define ADC_INC 0x030000 +#define ADC_BIS 0x800000 +#define ADC_CHRGRAW_D5 0x008000 + +/* + * ADC 1 + */ + +#define ADC_EN 0x000001 +#define ADC_SGL_CH 0x000002 +#define ADC_ADSEL 0x000008 +#define ADC_CH_0_POS 5 +#define ADC_CH_0_MASK 0x0000E0 +#define ADC_CH_1_POS 8 +#define ADC_CH_1_MASK 0x000700 +#define ADC_DELAY_POS 11 +#define ADC_DELAY_MASK 0x07F800 +#define ADC_ATO 0x080000 +#define ASC_ADC 0x100000 +#define ADC_WAIT_TSI_1 0x300001 +#define ADC_NO_ADTRIG 0x200000 + +/* + * ADC 2 - 4 + */ +#define ADD1_RESULT_MASK 0x00000FFC +#define ADD2_RESULT_MASK 0x00FFC000 +#define ADC_TS_MASK 0x00FFCFFC + +#define ADC_WCOMP 0x040000 +#define ADC_WCOMP_H_POS 0 +#define ADC_WCOMP_L_POS 9 +#define ADC_WCOMP_H_MASK 0x00003F +#define ADC_WCOMP_L_MASK 0x007E00 + +#define ADC_MODE_MASK 0x00003F + +#define ADC_INT_BISDONEI 0x02 + +typedef enum adc_state { + ADC_FREE, + ADC_USED, + ADC_MONITORING, +} t_adc_state; + +typedef enum reading_mode { + /*! + * Enables lithium cell reading + */ + M_LITHIUM_CELL = 0x000001, + /*! + * Enables charge current reading + */ + M_CHARGE_CURRENT = 0x000002, + /*! + * Enables battery current reading + */ + M_BATTERY_CURRENT = 0x000004, +} t_reading_mode; + +typedef struct { + /*! + * Delay before first conversion + */ + unsigned int delay; + /*! + * sets the ATX bit for delay on all conversion + */ + bool conv_delay; + /*! + * Sets the single channel mode + */ + bool single_channel; + /*! + * Channel selection 1 + */ + t_channel channel_0; + /*! + * Channel selection 2 + */ + t_channel channel_1; + /*! + * Used to configure ADC mode with t_reading_mode + */ + t_reading_mode read_mode; + /*! + * Sets the Touch screen mode + */ + bool read_ts; + /*! + * Wait TSI event before touch screen reading + */ + bool wait_tsi; + /*! + * Sets CHRGRAW scaling to divide by 5 + * Only supported on 2.0 and higher + */ + bool chrgraw_devide_5; + /*! + * Return ADC values + */ + unsigned int value[8]; + /*! + * Return touch screen values + */ + t_touch_screen ts_value; +} t_adc_param; + +static int pmic_adc_filter(t_touch_screen *ts_curr); +int mc13892_adc_request(bool read_ts); +int mc13892_adc_release(int adc_index); +t_reading_mode mc13892_set_read_mode(t_channel channel); +PMIC_STATUS mc13892_adc_read_ts(t_touch_screen *touch_sample, int wait_tsi); + +/* internal function */ +static void callback_tsi(void *); + +static int swait; + +static int suspend_flag; + +static wait_queue_head_t suspendq; + +/* EXPORTED FUNCTIONS */ +EXPORT_SYMBOL(pmic_adc_init); +EXPORT_SYMBOL(pmic_adc_deinit); +EXPORT_SYMBOL(pmic_adc_convert); +EXPORT_SYMBOL(pmic_adc_convert_8x); +EXPORT_SYMBOL(pmic_adc_set_touch_mode); +EXPORT_SYMBOL(pmic_adc_get_touch_mode); +EXPORT_SYMBOL(pmic_adc_get_touch_sample); + +static DECLARE_COMPLETION(adcdone_it); +static DECLARE_COMPLETION(adcbisdone_it); +static DECLARE_COMPLETION(adc_tsi); +static pmic_event_callback_t tsi_event; +static bool data_ready_adc_1; +static bool data_ready_adc_2; +static bool adc_ts; +static bool wait_ts; +static bool monitor_en; +static bool monitor_adc; +static DECLARE_MUTEX(convert_mutex); + +static DECLARE_WAIT_QUEUE_HEAD(queue_adc_busy); +static t_adc_state adc_dev[2]; + +static unsigned channel_num[] = { + 0, + 1, + 3, + 4, + 2, + 0, + 1, + 3, + 4, + -1, + 5, + 6, + 7, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1 +}; + +static bool pmic_adc_ready; + +int is_pmic_adc_ready() +{ + return pmic_adc_ready; +} +EXPORT_SYMBOL(is_pmic_adc_ready); + + +static int pmic_adc_suspend(struct platform_device *pdev, pm_message_t state) +{ + suspend_flag = 1; + CHECK_ERROR(pmic_write_reg(REG_ADC0, DEF_ADC_0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC1, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC2, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC3, DEF_ADC_3, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC4, 0, PMIC_ALL_BITS)); + + return 0; +}; + +static int pmic_adc_resume(struct platform_device *pdev) +{ + /* nothing for mc13892 adc */ + unsigned int adc_0_reg, adc_1_reg; + suspend_flag = 0; + + /* let interrupt of TSI again */ + adc_0_reg = ADC_WAIT_TSI_0; + CHECK_ERROR(pmic_write_reg(REG_ADC0, adc_0_reg, PMIC_ALL_BITS)); + adc_1_reg = ADC_WAIT_TSI_1 | (ADC_BIS * adc_ts); + CHECK_ERROR(pmic_write_reg(REG_ADC1, adc_1_reg, PMIC_ALL_BITS)); + + while (swait > 0) { + swait--; + wake_up_interruptible(&suspendq); + } + + return 0; +}; + +static void callback_tsi(void *unused) +{ + pr_debug("*** TSI IT mc13892 PMIC_ADC_GET_TOUCH_SAMPLE ***\n"); + if (wait_ts) { + complete(&adc_tsi); + pmic_event_mask(EVENT_TSI); + } +} + +static int pmic_adc_filter(t_touch_screen *ts_curr) +{ + unsigned int ydiff, xdiff; + unsigned int sample_sumx, sample_sumy; + + if (ts_curr->contact_resistance == 0) { + ts_curr->x_position = 0; + ts_curr->y_position = 0; + return 0; + } + + ydiff = abs(ts_curr->y_position1 - ts_curr->y_position2); + if (ydiff > DELTA_Y_MAX) { + pr_debug("pmic_adc_filter: Ret pos y\n"); + return -1; + } + + xdiff = abs(ts_curr->x_position1 - ts_curr->x_position2); + if (xdiff > DELTA_X_MAX) { + pr_debug("mc13892_adc_filter: Ret pos x\n"); + return -1; + } + + sample_sumx = ts_curr->x_position1 + ts_curr->x_position2; + sample_sumy = ts_curr->y_position1 + ts_curr->y_position2; + + ts_curr->y_position = sample_sumy / 2; + ts_curr->x_position = sample_sumx / 2; + + return 0; +} + +int pmic_adc_init(void) +{ + unsigned int reg_value = 0, i = 0; + + if (suspend_flag == 1) + return -EBUSY; + + for (i = 0; i < ADC_NB_AVAILABLE; i++) + adc_dev[i] = ADC_FREE; + + CHECK_ERROR(pmic_write_reg(REG_ADC0, DEF_ADC_0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC1, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC2, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC3, DEF_ADC_3, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC4, 0, PMIC_ALL_BITS)); + reg_value = 0x001000; + + data_ready_adc_1 = false; + data_ready_adc_2 = false; + adc_ts = false; + wait_ts = false; + monitor_en = false; + monitor_adc = false; + + /* sub to Touch Screen IT */ + tsi_event.param = NULL; + tsi_event.func = callback_tsi; + CHECK_ERROR(pmic_event_subscribe(EVENT_TSI, tsi_event)); + + return PMIC_SUCCESS; +} + +PMIC_STATUS pmic_adc_deinit(void) +{ + CHECK_ERROR(pmic_event_unsubscribe(EVENT_TSI, tsi_event)); + + return PMIC_SUCCESS; +} + +int mc13892_adc_init_param(t_adc_param * adc_param) +{ + int i = 0; + + if (suspend_flag == 1) + return -EBUSY; + + adc_param->delay = 0; + adc_param->conv_delay = false; + adc_param->single_channel = false; + adc_param->channel_0 = BATTERY_VOLTAGE; + adc_param->channel_1 = BATTERY_VOLTAGE; + adc_param->read_mode = 0; + adc_param->wait_tsi = 0; + adc_param->chrgraw_devide_5 = true; + adc_param->read_ts = false; + adc_param->ts_value.x_position = 0; + adc_param->ts_value.y_position = 0; + adc_param->ts_value.contact_resistance = 0; + for (i = 0; i <= MAX_CHANNEL; i++) + adc_param->value[i] = 0; + + return 0; +} + +PMIC_STATUS mc13892_adc_convert(t_adc_param * adc_param) +{ + bool use_bis = false; + int retry_counter = 0; + unsigned int status0; + unsigned int adc_0_reg = 0, adc_1_reg = 0, reg_1 = 0, result_reg = + 0, i = 0; + unsigned int result = 0, temp = 0; + pmic_version_t mc13892_ver; + pr_debug("mc13892 ADC - mc13892_adc_convert ....\n"); + if (suspend_flag == 1) + return -EBUSY; + + if (adc_param->wait_tsi) { + /* configure adc to wait tsi interrupt */ + INIT_COMPLETION(adc_tsi); + + /*for ts don't use bis */ + /*put ts in interrupt mode */ + /* still kep reference? */ + adc_0_reg = 0x001400 | (ADC_BIS * 0); + pmic_event_unmask(EVENT_TSI); + CHECK_ERROR(pmic_write_reg(REG_ADC0, adc_0_reg, PMIC_ALL_BITS)); + /*for ts don't use bis */ + adc_1_reg = 0x200001 | (ADC_BIS * 0); + CHECK_ERROR(pmic_write_reg(REG_ADC1, adc_1_reg, PMIC_ALL_BITS)); + pr_debug("wait tsi ....\n"); + wait_ts = true; + wait_for_completion_interruptible(&adc_tsi); + wait_ts = false; + } + if (adc_param->read_ts == false) + down(&convert_mutex); + use_bis = mc13892_adc_request(adc_param->read_ts); + if (use_bis < 0) { + pr_debug("process has received a signal and got interrupted\n"); + return -EINTR; + } + + /* CONFIGURE ADC REG 0 */ + adc_0_reg = 0; + adc_1_reg = 0; + if (adc_param->read_ts == false) { + adc_0_reg = adc_param->read_mode & 0x00003F; + /* add auto inc */ + adc_0_reg |= ADC_INC; + if (use_bis) { + /* add adc bis */ + adc_0_reg |= ADC_BIS; + } + mc13892_ver = pmic_get_version(); + if (mc13892_ver.revision >= 20) + if (adc_param->chrgraw_devide_5) + adc_0_reg |= ADC_CHRGRAW_D5; + + if (adc_param->single_channel) + adc_1_reg |= ADC_SGL_CH; + + if (adc_param->conv_delay) + adc_1_reg |= ADC_ATO; + + if (adc_param->single_channel) + adc_1_reg |= ADC_SGL_CH; + + adc_1_reg |= (adc_param->channel_0 << ADC_CH_0_POS) & + ADC_CH_0_MASK; + adc_1_reg |= (adc_param->channel_1 << ADC_CH_1_POS) & + ADC_CH_1_MASK; + } else { + adc_0_reg = 0x002400 | (ADC_BIS * use_bis) | ADC_INC; + } + pr_debug("Write Reg %i = %x\n", REG_ADC0, adc_0_reg); + /*Change has been made here */ + CHECK_ERROR(pmic_write_reg(REG_ADC0, adc_0_reg, + ADC_INC | ADC_BIS | ADC_CHRGRAW_D5 | + 0xfff00ff)); + /* CONFIGURE ADC REG 1 */ + if (adc_param->read_ts == false) { + adc_1_reg |= ADC_NO_ADTRIG; + adc_1_reg |= ADC_EN; + adc_1_reg |= (adc_param->delay << ADC_DELAY_POS) & + ADC_DELAY_MASK; + if (use_bis) + adc_1_reg |= ADC_BIS; + } else { + /* configure and start convert to read x and y position */ + /* configure to read 2 value in channel selection 1 & 2 */ + adc_1_reg = 0x100409 | (ADC_BIS * use_bis) | ADC_NO_ADTRIG; + /* set ATOx = 5, it could be better for ts ADC */ + adc_1_reg |= 0x002800; + } + reg_1 = adc_1_reg; + if (use_bis == 0) { + data_ready_adc_1 = false; + adc_1_reg |= ASC_ADC; + data_ready_adc_1 = true; + pr_debug("Write Reg %i = %x\n", REG_ADC1, adc_1_reg); + INIT_COMPLETION(adcdone_it); + CHECK_ERROR(pmic_write_reg(REG_ADC1, adc_1_reg, + ADC_SGL_CH | ADC_ATO | ADC_ADSEL + | ADC_CH_0_MASK | ADC_CH_1_MASK | + ADC_NO_ADTRIG | ADC_EN | + ADC_DELAY_MASK | ASC_ADC | ADC_BIS)); + pr_debug("wait adc done \n"); + pmic_read(REG_INT_STATUS0, &status0); + for (retry_counter=0; retry_counter<=10; retry_counter++) { + if (status0 & 1) + break; + pmic_read(REG_INT_STATUS0, &status0); + } + + if (retry_counter == 10) { + mc13892_adc_release(use_bis); + return -EINTR; + } + + pmic_write_reg(REG_INT_STATUS0, (1 << 0), (1 << 0)); + data_ready_adc_1 = false; + } else { + data_ready_adc_2 = false; + adc_1_reg |= ASC_ADC; + data_ready_adc_2 = true; + INIT_COMPLETION(adcbisdone_it); + CHECK_ERROR(pmic_write_reg(REG_ADC1, adc_1_reg, 0xFFFFFF)); + temp = 0x800000; + CHECK_ERROR(pmic_write_reg(REG_ADC3, temp, 0xFFFFFF)); + + pmic_read(REG_INT_STATUS0, &status0); + for (retry_counter=0; retry_counter<=10; retry_counter++) { + if (status0 & 2) + break; + pmic_read(REG_INT_STATUS0, &status0); + } + if (retry_counter == 10) { + mc13892_adc_release(use_bis); + return -EINTR; + } + data_ready_adc_2 = false; + pmic_write_reg(REG_INT_STATUS0, (1 << 1), (1 << 1)); + } + /* read result and store in adc_param */ + result = 0; + if (use_bis == 0) + result_reg = REG_ADC2; + else + result_reg = REG_ADC4; + + CHECK_ERROR(pmic_write_reg(REG_ADC1, 4 << ADC_CH_1_POS, + ADC_CH_0_MASK | ADC_CH_1_MASK)); + + for (i = 0; i <= 3; i++) { + CHECK_ERROR(pmic_read_reg(result_reg, &result, PMIC_ALL_BITS)); + adc_param->value[i] = ((result & ADD1_RESULT_MASK) >> 2); + adc_param->value[i + 4] = ((result & ADD2_RESULT_MASK) >> 14); + pr_debug("value[%d] = %d, value[%d] = %d\n", + i, adc_param->value[i], + i + 4, adc_param->value[i + 4]); + } + if (adc_param->read_ts) { + adc_param->ts_value.x_position = adc_param->value[0]; + adc_param->ts_value.x_position1 = adc_param->value[0]; + adc_param->ts_value.x_position2 = adc_param->value[1]; + adc_param->ts_value.y_position = adc_param->value[3]; + adc_param->ts_value.y_position1 = adc_param->value[3]; + adc_param->ts_value.y_position2 = adc_param->value[4]; + adc_param->ts_value.contact_resistance = adc_param->value[6]; + } + + /*if (adc_param->read_ts) { + adc_param->ts_value.x_position = adc_param->value[2]; + adc_param->ts_value.y_position = adc_param->value[5]; + adc_param->ts_value.contact_resistance = adc_param->value[6]; + } */ + mc13892_adc_release(use_bis); + if (adc_param->read_ts == false) + up(&convert_mutex); + + return PMIC_SUCCESS; +} + +t_reading_mode mc13892_set_read_mode(t_channel channel) +{ + t_reading_mode read_mode = 0; + + switch (channel) { + case CHARGE_CURRENT: + read_mode = M_CHARGE_CURRENT; + break; + case BATTERY_CURRENT: + read_mode = M_BATTERY_CURRENT; + break; + default: + read_mode = 0; + } + + return read_mode; +} + +PMIC_STATUS pmic_adc_convert(t_channel channel, unsigned short *result) +{ + t_adc_param adc_param; + PMIC_STATUS ret; + + if (suspend_flag == 1) + return -EBUSY; + + channel = channel_num[channel]; + if (channel == -1) { + pr_debug("Wrong channel ID\n"); + return PMIC_PARAMETER_ERROR; + } + mc13892_adc_init_param(&adc_param); + pr_debug("pmic_adc_convert\n"); + adc_param.read_ts = false; + adc_param.single_channel = true; + adc_param.read_mode = mc13892_set_read_mode(channel); + + /* Find the group */ + if (channel <= 7) + adc_param.channel_0 = channel; + else + return PMIC_PARAMETER_ERROR; + + ret = mc13892_adc_convert(&adc_param); + *result = adc_param.value[0]; + return ret; +} + +PMIC_STATUS pmic_adc_convert_8x(t_channel channel, unsigned short *result) +{ + t_adc_param adc_param; + int i; + PMIC_STATUS ret; + if (suspend_flag == 1) + return -EBUSY; + + channel = channel_num[channel]; + + if (channel == -1) { + pr_debug("Wrong channel ID\n"); + return PMIC_PARAMETER_ERROR; + } + mc13892_adc_init_param(&adc_param); + pr_debug("pmic_adc_convert_8x\n"); + adc_param.read_ts = false; + adc_param.single_channel = true; + adc_param.read_mode = mc13892_set_read_mode(channel); + + if (channel <= 7) { + adc_param.channel_0 = channel; + adc_param.channel_1 = channel; + } else + return PMIC_PARAMETER_ERROR; + + ret = mc13892_adc_convert(&adc_param); + for (i = 0; i <= 7; i++) + result[i] = adc_param.value[i]; + + return ret; +} + +PMIC_STATUS pmic_adc_set_touch_mode(t_touch_mode touch_mode) +{ + if (suspend_flag == 1) + return -EBUSY; + + CHECK_ERROR(pmic_write_reg(REG_ADC0, + BITFVAL(MC13892_ADC0_TS_M, touch_mode), + BITFMASK(MC13892_ADC0_TS_M))); + return PMIC_SUCCESS; +} + +PMIC_STATUS pmic_adc_get_touch_mode(t_touch_mode * touch_mode) +{ + unsigned int value; + if (suspend_flag == 1) + return -EBUSY; + + CHECK_ERROR(pmic_read_reg(REG_ADC0, &value, PMIC_ALL_BITS)); + + *touch_mode = BITFEXT(value, MC13892_ADC0_TS_M); + + return PMIC_SUCCESS; +} + +PMIC_STATUS pmic_adc_get_touch_sample(t_touch_screen *touch_sample, int wait) +{ + if (mc13892_adc_read_ts(touch_sample, wait) != 0) + return PMIC_ERROR; + if (0 == pmic_adc_filter(touch_sample)) + return PMIC_SUCCESS; + else + return PMIC_ERROR; +} + +PMIC_STATUS mc13892_adc_read_ts(t_touch_screen *ts_value, int wait_tsi) +{ + t_adc_param param; + pr_debug("mc13892_adc : mc13892_adc_read_ts\n"); + if (suspend_flag == 1) + return -EBUSY; + + if (wait_ts) { + pr_debug("mc13892_adc : error TS busy \n"); + return PMIC_ERROR; + } + mc13892_adc_init_param(¶m); + param.wait_tsi = wait_tsi; + param.read_ts = true; + if (mc13892_adc_convert(¶m) != 0) + return PMIC_ERROR; + /* check if x-y is ok */ + if (param.ts_value.contact_resistance < 1000) { + ts_value->x_position = param.ts_value.x_position; + ts_value->x_position1 = param.ts_value.x_position1; + ts_value->x_position2 = param.ts_value.x_position2; + + ts_value->y_position = param.ts_value.y_position; + ts_value->y_position1 = param.ts_value.y_position1; + ts_value->y_position2 = param.ts_value.y_position2; + + ts_value->contact_resistance = + param.ts_value.contact_resistance + 1; + + } else { + ts_value->x_position = 0; + ts_value->y_position = 0; + ts_value->contact_resistance = 0; + + } + return PMIC_SUCCESS; +} + +int mc13892_adc_request(bool read_ts) +{ + int adc_index = -1; + if (read_ts != 0) { + /*for ts we use bis=0 */ + if (adc_dev[0] == ADC_USED) + return -1; + /*no wait here */ + adc_dev[0] = ADC_USED; + adc_index = 0; + } else { + /*for other adc use bis = 1 */ + if (adc_dev[1] == ADC_USED) { + return -1; + /*no wait here */ + } + adc_dev[1] = ADC_USED; + adc_index = 1; + } + pr_debug("mc13892_adc : request ADC %d\n", adc_index); + return adc_index; +} + +int mc13892_adc_release(int adc_index) +{ + while (suspend_flag == 1) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, (suspend_flag == 0))) + return -ERESTARTSYS; + } + + pr_debug("mc13892_adc : release ADC %d\n", adc_index); + if ((adc_dev[adc_index] == ADC_MONITORING) || + (adc_dev[adc_index] == ADC_USED)) { + adc_dev[adc_index] = ADC_FREE; + wake_up(&queue_adc_busy); + return 0; + } + return -1; +} + +#ifdef DEBUG +static t_adc_param adc_param_db; + +static ssize_t adc_info(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int *value = adc_param_db.value; + + pr_debug("adc_info\n"); + + pr_debug("ch0\t\t%d\n", adc_param_db.channel_0); + pr_debug("ch1\t\t%d\n", adc_param_db.channel_1); + pr_debug("d5\t\t%d\n", adc_param_db.chrgraw_devide_5); + pr_debug("conv delay\t%d\n", adc_param_db.conv_delay); + pr_debug("delay\t\t%d\n", adc_param_db.delay); + pr_debug("read mode\t%d\n", adc_param_db.read_mode); + pr_debug("read ts\t\t%d\n", adc_param_db.read_ts); + pr_debug("single ch\t%d\n", adc_param_db.single_channel); + pr_debug("wait ts int\t%d\n", adc_param_db.wait_tsi); + pr_debug("value0-3:\t%d\t%d\t%d\t%d\n", value[0], value[1], + value[2], value[3]); + pr_debug("value4-7:\t%d\t%d\t%d\t%d\n", value[4], value[5], + value[6], value[7]); + + return 0; +} + +enum { + ADC_SET_CH0 = 0, + ADC_SET_CH1, + ADC_SET_DV5, + ADC_SET_CON_DELAY, + ADC_SET_DELAY, + ADC_SET_RM, + ADC_SET_RT, + ADC_SET_S_CH, + ADC_SET_WAIT_TS, + ADC_INIT_P, + ADC_START, + ADC_TS, + ADC_TS_READ, + ADC_TS_CAL, + ADC_CMD_MAX +}; + +static const char *const adc_cmd[ADC_CMD_MAX] = { + [ADC_SET_CH0] = "ch0", + [ADC_SET_CH1] = "ch1", + [ADC_SET_DV5] = "dv5", + [ADC_SET_CON_DELAY] = "cd", + [ADC_SET_DELAY] = "dl", + [ADC_SET_RM] = "rm", + [ADC_SET_RT] = "rt", + [ADC_SET_S_CH] = "sch", + [ADC_SET_WAIT_TS] = "wt", + [ADC_INIT_P] = "init", + [ADC_START] = "start", + [ADC_TS] = "touch", + [ADC_TS_READ] = "touchr", + [ADC_TS_CAL] = "cal" +}; + +static int cmd(unsigned int index, int value) +{ + t_touch_screen ts; + + switch (index) { + case ADC_SET_CH0: + adc_param_db.channel_0 = value; + break; + case ADC_SET_CH1: + adc_param_db.channel_1 = value; + break; + case ADC_SET_DV5: + adc_param_db.chrgraw_devide_5 = value; + break; + case ADC_SET_CON_DELAY: + adc_param_db.conv_delay = value; + break; + case ADC_SET_RM: + adc_param_db.read_mode = value; + break; + case ADC_SET_RT: + adc_param_db.read_ts = value; + break; + case ADC_SET_S_CH: + adc_param_db.single_channel = value; + break; + case ADC_SET_WAIT_TS: + adc_param_db.wait_tsi = value; + break; + case ADC_INIT_P: + mc13892_adc_init_param(&adc_param_db); + break; + case ADC_START: + mc13892_adc_convert(&adc_param_db); + break; + case ADC_TS: + pmic_adc_get_touch_sample(&ts, 1); + pr_debug("x = %d\n", ts.x_position); + pr_debug("y = %d\n", ts.y_position); + pr_debug("p = %d\n", ts.contact_resistance); + break; + case ADC_TS_READ: + pmic_adc_get_touch_sample(&ts, 0); + pr_debug("x = %d\n", ts.x_position); + pr_debug("y = %d\n", ts.y_position); + pr_debug("p = %d\n", ts.contact_resistance); + break; + case ADC_TS_CAL: + break; + default: + pr_debug("error command\n"); + break; + } + return 0; +} + +static ssize_t adc_ctl(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int state = 0; + const char *const *s; + char *p, *q; + int error; + int len, value = 0; + + pr_debug("adc_ctl\n"); + + q = NULL; + q = memchr(buf, ' ', count); + + if (q != NULL) { + len = q - buf; + q += 1; + value = simple_strtoul(q, NULL, 10); + } else { + p = memchr(buf, '\n', count); + len = p ? p - buf : count; + } + + for (s = &adc_cmd[state]; state < ADC_CMD_MAX; s++, state++) { + if (*s && !strncmp(buf, *s, len)) + break; + } + if (state < ADC_CMD_MAX && *s) + error = cmd(state, value); + else + error = -EINVAL; + + return count; +} + +#else +static ssize_t adc_info(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return 0; +} + +static ssize_t adc_ctl(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + return count; +} + +#endif + +static DEVICE_ATTR(adc, 0644, adc_info, adc_ctl); + +static int pmic_adc_module_probe(struct platform_device *pdev) +{ + int ret = 0; + + pr_debug("PMIC ADC start probe\n"); + ret = device_create_file(&(pdev->dev), &dev_attr_adc); + if (ret) { + pr_debug("Can't create device file!\n"); + return -ENODEV; + } + + init_waitqueue_head(&suspendq); + + ret = pmic_adc_init(); + if (ret != PMIC_SUCCESS) { + pr_debug("Error in pmic_adc_init.\n"); + goto rm_dev_file; + } + + pmic_adc_ready = 1; + pr_debug("PMIC ADC successfully probed\n"); + return 0; + + rm_dev_file: + device_remove_file(&(pdev->dev), &dev_attr_adc); + return ret; +} + +static int pmic_adc_module_remove(struct platform_device *pdev) +{ + pmic_adc_deinit(); + pmic_adc_ready = 0; + pr_debug("PMIC ADC successfully removed\n"); + return 0; +} + +static struct platform_driver pmic_adc_driver_ldm = { + .driver = { + .name = "pmic_adc", + }, + .suspend = pmic_adc_suspend, + .resume = pmic_adc_resume, + .probe = pmic_adc_module_probe, + .remove = pmic_adc_module_remove, +}; + +static int __init pmic_adc_module_init(void) +{ + pr_debug("PMIC ADC driver loading...\n"); + return platform_driver_register(&pmic_adc_driver_ldm); +} + +static void __exit pmic_adc_module_exit(void) +{ + platform_driver_unregister(&pmic_adc_driver_ldm); + pr_debug("PMIC ADC driver successfully unloaded\n"); +} + +module_init(pmic_adc_module_init); +module_exit(pmic_adc_module_exit); + +MODULE_DESCRIPTION("PMIC ADC device driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/pmic/mc13892/pmic_light.c linux-2.6.26-lab126/drivers/mxc/pmic/mc13892/pmic_light.c --- linux-2.6.26/drivers/mxc/pmic/mc13892/pmic_light.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13892/pmic_light.c 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,694 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13892/pmic_light.c + * @brief This is the main file of PMIC(mc13783) Light and Backlight driver. + * + * @ingroup PMIC_LIGHT + */ + +/* + * Includes + */ +#define DEBUG +#include +#include +#include +#include +#include + +#define BIT_CL_MAIN_LSH 9 +#define BIT_CL_AUX_LSH 21 +#define BIT_CL_KEY_LSH 9 +#define BIT_CL_RED_LSH 9 +#define BIT_CL_GREEN_LSH 21 +#define BIT_CL_BLUE_LSH 9 + +#define BIT_CL_MAIN_WID 3 +#define BIT_CL_AUX_WID 3 +#define BIT_CL_KEY_WID 3 +#define BIT_CL_RED_WID 3 +#define BIT_CL_GREEN_WID 3 +#define BIT_CL_BLUE_WID 3 + +#define BIT_DC_MAIN_LSH 3 +#define BIT_DC_AUX_LSH 15 +#define BIT_DC_KEY_LSH 3 +#define BIT_DC_RED_LSH 3 +#define BIT_DC_GREEN_LSH 15 +#define BIT_DC_BLUE_LSH 3 + +#define BIT_DC_MAIN_WID 6 +#define BIT_DC_AUX_WID 6 +#define BIT_DC_KEY_WID 6 +#define BIT_DC_RED_WID 6 +#define BIT_DC_GREEN_WID 6 +#define BIT_DC_BLUE_WID 6 + +#define BIT_RP_MAIN_LSH 2 +#define BIT_RP_AUX_LSH 14 +#define BIT_RP_KEY_LSH 2 +#define BIT_RP_RED_LSH 2 +#define BIT_RP_GREEN_LSH 14 +#define BIT_RP_BLUE_LSH 2 + +#define BIT_RP_MAIN_WID 1 +#define BIT_RP_AUX_WID 1 +#define BIT_RP_KEY_WID 1 +#define BIT_RP_RED_WID 1 +#define BIT_RP_GREEN_WID 1 +#define BIT_RP_BLUE_WID 1 + +#define BIT_HC_MAIN_LSH 1 +#define BIT_HC_AUX_LSH 13 +#define BIT_HC_KEY_LSH 1 + +#define BIT_HC_MAIN_WID 1 +#define BIT_HC_AUX_WID 1 +#define BIT_HC_KEY_WID 1 + +#define BIT_BP_RED_LSH 0 +#define BIT_BP_GREEN_LSH 12 +#define BIT_BP_BLUE_LSH 0 + +#define BIT_BP_RED_WID 2 +#define BIT_BP_GREEN_WID 2 +#define BIT_BP_BLUE_WID 2 + +#ifdef CONFIG_MACH_LUIGI_LAB126 +extern int luigi_button_green_led; +#endif + +int pmic_light_init_reg(void) +{ +#ifdef CONFIG_MACH_LUIGI_LAB126 + if (luigi_button_green_led) + return 0; +#endif + + CHECK_ERROR(pmic_write_reg(REG_LED_CTL0, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_LED_CTL1, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_LED_CTL2, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_LED_CTL3, 0, PMIC_ALL_BITS)); + + return 0; +} + +static int pmic_light_suspend(struct platform_device *dev, pm_message_t state) +{ + return 0; +}; + +static int pmic_light_resume(struct platform_device *pdev) +{ + return 0; +}; + +PMIC_STATUS mc13892_bklit_set_hi_current(enum lit_channel channel, int mode) +{ + unsigned int mask; + unsigned int value; + int reg; + + switch (channel) { + case LIT_MAIN: + value = BITFVAL(BIT_HC_MAIN, mode); + mask = BITFMASK(BIT_HC_MAIN); + reg = REG_LED_CTL0; + break; + case LIT_AUX: + value = BITFVAL(BIT_HC_AUX, mode); + mask = BITFMASK(BIT_HC_AUX); + reg = REG_LED_CTL0; + break; + case LIT_KEY: + value = BITFVAL(BIT_HC_KEY, mode); + mask = BITFMASK(BIT_HC_KEY); + reg = REG_LED_CTL1; + break; + default: + return PMIC_PARAMETER_ERROR; + } + CHECK_ERROR(pmic_write_reg(reg, value, mask)); + return PMIC_SUCCESS; +} + +PMIC_STATUS mc13892_bklit_get_hi_current(enum lit_channel channel, int *mode) +{ + unsigned int mask; + int reg; + + switch (channel) { + case LIT_MAIN: + mask = BITFMASK(BIT_HC_MAIN); + reg = REG_LED_CTL0; + break; + case LIT_AUX: + mask = BITFMASK(BIT_HC_AUX); + reg = REG_LED_CTL0; + break; + case LIT_KEY: + mask = BITFMASK(BIT_HC_KEY); + reg = REG_LED_CTL1; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, mode, mask)); + return PMIC_SUCCESS; +} + +PMIC_STATUS mc13892_bklit_set_current(enum lit_channel channel, + unsigned char level) +{ + unsigned int mask; + unsigned int value; + int reg; + + if (level > LIT_CURR_HI_42) + return PMIC_PARAMETER_ERROR; + else if (level >= LIT_CURR_HI_0) { + CHECK_ERROR(mc13892_bklit_set_hi_current(channel, 1)); + level -= LIT_CURR_HI_0; + } + + switch (channel) { + case LIT_MAIN: + value = BITFVAL(BIT_CL_MAIN, level); + mask = BITFMASK(BIT_CL_MAIN); + reg = REG_LED_CTL0; + break; + case LIT_AUX: + value = BITFVAL(BIT_CL_AUX, level); + mask = BITFMASK(BIT_CL_AUX); + reg = REG_LED_CTL0; + break; + case LIT_KEY: + value = BITFVAL(BIT_CL_KEY, level); + mask = BITFMASK(BIT_CL_KEY); + reg = REG_LED_CTL1; + break; + case LIT_RED: + value = BITFVAL(BIT_CL_RED, level); + mask = BITFMASK(BIT_CL_RED); + reg = REG_LED_CTL2; + break; + case LIT_GREEN: + value = BITFVAL(BIT_CL_GREEN, level); + mask = BITFMASK(BIT_CL_GREEN); + reg = REG_LED_CTL2; + break; + case LIT_BLUE: + value = BITFVAL(BIT_CL_BLUE, level); + mask = BITFMASK(BIT_CL_BLUE); + reg = REG_LED_CTL3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + CHECK_ERROR(pmic_write_reg(reg, value, mask)); + + return PMIC_SUCCESS; +} + +PMIC_STATUS mc13892_bklit_get_current(enum lit_channel channel, + unsigned char *level) +{ + unsigned int reg_value = 0; + unsigned int mask = 0; + int reg, mode; + + CHECK_ERROR(mc13892_bklit_get_hi_current(channel, &mode)); + + switch (channel) { + case LIT_MAIN: + mask = BITFMASK(BIT_CL_MAIN); + reg = REG_LED_CTL0; + break; + case LIT_AUX: + mask = BITFMASK(BIT_CL_AUX); + reg = REG_LED_CTL0; + break; + case LIT_KEY: + mask = BITFMASK(BIT_CL_KEY); + reg = REG_LED_CTL1; + break; + case LIT_RED: + mask = BITFMASK(BIT_CL_RED); + reg = REG_LED_CTL2; + break; + case LIT_GREEN: + mask = BITFMASK(BIT_CL_GREEN); + reg = REG_LED_CTL2; + break; + case LIT_BLUE: + mask = BITFMASK(BIT_CL_BLUE); + reg = REG_LED_CTL3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, ®_value, mask)); + + switch (channel) { + case LIT_MAIN: + *level = BITFEXT(reg_value, BIT_CL_MAIN); + break; + case LIT_AUX: + *level = BITFEXT(reg_value, BIT_CL_AUX); + break; + case LIT_KEY: + *level = BITFEXT(reg_value, BIT_CL_KEY); + break; + case LIT_RED: + *level = BITFEXT(reg_value, BIT_CL_RED); + break; + case LIT_GREEN: + *level = BITFEXT(reg_value, BIT_CL_GREEN); + break; + case LIT_BLUE: + *level = BITFEXT(reg_value, BIT_CL_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + if (mode == 1) + *level += LIT_CURR_HI_0; + + return PMIC_SUCCESS; +} + +PMIC_STATUS mc13892_bklit_set_dutycycle(enum lit_channel channel, + unsigned char dc) +{ + unsigned int mask; + unsigned int value; + int reg; + + switch (channel) { + case LIT_MAIN: + value = BITFVAL(BIT_DC_MAIN, dc); + mask = BITFMASK(BIT_DC_MAIN); + reg = REG_LED_CTL0; + break; + case LIT_AUX: + value = BITFVAL(BIT_DC_AUX, dc); + mask = BITFMASK(BIT_DC_AUX); + reg = REG_LED_CTL0; + break; + case LIT_KEY: + value = BITFVAL(BIT_DC_KEY, dc); + mask = BITFMASK(BIT_DC_KEY); + reg = REG_LED_CTL1; + break; + case LIT_RED: + value = BITFVAL(BIT_DC_RED, dc); + mask = BITFMASK(BIT_DC_RED); + reg = REG_LED_CTL2; + break; + case LIT_GREEN: + value = BITFVAL(BIT_DC_GREEN, dc); + mask = BITFMASK(BIT_DC_GREEN); + reg = REG_LED_CTL2; + break; + case LIT_BLUE: + value = BITFVAL(BIT_DC_BLUE, dc); + mask = BITFMASK(BIT_DC_BLUE); + reg = REG_LED_CTL3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + CHECK_ERROR(pmic_write_reg(reg, value, mask)); + return PMIC_SUCCESS; +} + +PMIC_STATUS mc13892_bklit_get_dutycycle(enum lit_channel channel, + unsigned char *dc) +{ + unsigned int mask; + int reg; + unsigned int reg_value = 0; + + switch (channel) { + case LIT_MAIN: + mask = BITFMASK(BIT_DC_MAIN); + reg = REG_LED_CTL0; + break; + case LIT_AUX: + mask = BITFMASK(BIT_DC_AUX); + reg = REG_LED_CTL0; + break; + case LIT_KEY: + mask = BITFMASK(BIT_DC_KEY); + reg = REG_LED_CTL1; + break; + case LIT_RED: + mask = BITFMASK(BIT_DC_RED); + reg = REG_LED_CTL2; + break; + case LIT_GREEN: + mask = BITFMASK(BIT_DC_GREEN); + reg = REG_LED_CTL2; + break; + case LIT_BLUE: + mask = BITFMASK(BIT_DC_BLUE); + reg = REG_LED_CTL3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, ®_value, mask)); + return PMIC_SUCCESS; +} + +PMIC_STATUS mc13892_bklit_set_ramp(enum lit_channel channel, int flag) +{ + unsigned int mask; + unsigned int value; + int reg; + + switch (channel) { + case LIT_MAIN: + value = BITFVAL(BIT_RP_MAIN, flag); + mask = BITFMASK(BIT_RP_MAIN); + reg = REG_LED_CTL0; + break; + case LIT_AUX: + value = BITFVAL(BIT_RP_AUX, flag); + mask = BITFMASK(BIT_RP_AUX); + reg = REG_LED_CTL0; + break; + case LIT_KEY: + value = BITFVAL(BIT_RP_KEY, flag); + mask = BITFMASK(BIT_RP_KEY); + reg = REG_LED_CTL1; + break; + case LIT_RED: + value = BITFVAL(BIT_RP_RED, flag); + mask = BITFMASK(BIT_RP_RED); + reg = REG_LED_CTL2; + break; + case LIT_GREEN: + value = BITFVAL(BIT_RP_GREEN, flag); + mask = BITFMASK(BIT_RP_GREEN); + reg = REG_LED_CTL2; + break; + case LIT_BLUE: + value = BITFVAL(BIT_RP_BLUE, flag); + mask = BITFMASK(BIT_RP_BLUE); + reg = REG_LED_CTL3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + CHECK_ERROR(pmic_write_reg(reg, value, mask)); + return PMIC_SUCCESS; +} + +PMIC_STATUS mc13892_bklit_get_ramp(enum lit_channel channel, int *flag) +{ + unsigned int mask; + int reg; + + switch (channel) { + case LIT_MAIN: + mask = BITFMASK(BIT_RP_MAIN); + reg = REG_LED_CTL0; + break; + case LIT_AUX: + mask = BITFMASK(BIT_RP_AUX); + reg = REG_LED_CTL0; + break; + case LIT_KEY: + mask = BITFMASK(BIT_RP_KEY); + reg = REG_LED_CTL1; + break; + case LIT_RED: + mask = BITFMASK(BIT_RP_RED); + reg = REG_LED_CTL2; + break; + case LIT_GREEN: + mask = BITFMASK(BIT_RP_GREEN); + reg = REG_LED_CTL2; + break; + case LIT_BLUE: + mask = BITFMASK(BIT_RP_BLUE); + reg = REG_LED_CTL3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, flag, mask)); + return PMIC_SUCCESS; +} + +PMIC_STATUS mc13892_bklit_set_blink_p(enum lit_channel channel, int period) +{ + unsigned int mask; + unsigned int value; + int reg; + + switch (channel) { + case LIT_RED: + value = BITFVAL(BIT_BP_RED, period); + mask = BITFMASK(BIT_BP_RED); + reg = REG_LED_CTL2; + break; + case LIT_GREEN: + value = BITFVAL(BIT_BP_GREEN, period); + mask = BITFMASK(BIT_BP_GREEN); + reg = REG_LED_CTL2; + break; + case LIT_BLUE: + value = BITFVAL(BIT_BP_BLUE, period); + mask = BITFMASK(BIT_BP_BLUE); + reg = REG_LED_CTL3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + CHECK_ERROR(pmic_write_reg(reg, value, mask)); + return PMIC_SUCCESS; +} + +PMIC_STATUS mc13892_bklit_get_blink_p(enum lit_channel channel, int *period) +{ + unsigned int mask; + int reg; + + switch (channel) { + case LIT_RED: + mask = BITFMASK(BIT_BP_RED); + reg = REG_LED_CTL2; + break; + case LIT_GREEN: + mask = BITFMASK(BIT_BP_GREEN); + reg = REG_LED_CTL2; + break; + case LIT_BLUE: + mask = BITFMASK(BIT_BP_BLUE); + reg = REG_LED_CTL3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, period, mask)); + return PMIC_SUCCESS; +} + +EXPORT_SYMBOL(mc13892_bklit_set_current); +EXPORT_SYMBOL(mc13892_bklit_get_current); +EXPORT_SYMBOL(mc13892_bklit_set_dutycycle); +EXPORT_SYMBOL(mc13892_bklit_get_dutycycle); +EXPORT_SYMBOL(mc13892_bklit_set_ramp); +EXPORT_SYMBOL(mc13892_bklit_get_ramp); +EXPORT_SYMBOL(mc13892_bklit_set_blink_p); +EXPORT_SYMBOL(mc13892_bklit_get_blink_p); + +static int pmic_light_remove(struct platform_device *pdev) +{ + return 0; +} + +#ifdef DEBUG +static ssize_t lit_info(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return 0; +} + +enum { + SET_CURR = 0, + SET_DC, + SET_RAMP, + SET_BP, + SET_CH, + LIT_CMD_MAX +}; + +static const char *const lit_cmd[LIT_CMD_MAX] = { + [SET_CURR] = "cur", + [SET_DC] = "dc", + [SET_RAMP] = "ra", + [SET_BP] = "bp", + [SET_CH] = "ch" +}; + +static int cmd(unsigned int index, int value) +{ + static int ch = LIT_MAIN; + int ret = 0; + + switch (index) { + case SET_CH: + ch = value; + break; + case SET_CURR: + pr_debug("set %d cur %d\n", ch, value); + ret = mc13892_bklit_set_current(ch, value); + break; + case SET_DC: + pr_debug("set %d dc %d\n", ch, value); + ret = mc13892_bklit_set_dutycycle(ch, value); + break; + case SET_RAMP: + pr_debug("set %d ramp %d\n", ch, value); + ret = mc13892_bklit_set_ramp(ch, value); + break; + case SET_BP: + pr_debug("set %d bp %d\n", ch, value); + ret = mc13892_bklit_set_blink_p(ch, value); + break; + default: + pr_debug("error command\n"); + break; + } + + if (ret == PMIC_SUCCESS) + pr_debug("command exec successfully!\n"); + + return 0; +} + +static ssize_t lit_ctl(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int state = 0; + const char *const *s; + char *p, *q; + int error; + int len, value = 0; + + pr_debug("lit_ctl\n"); + + q = NULL; + q = memchr(buf, ' ', count); + + if (q != NULL) { + len = q - buf; + q += 1; + value = simple_strtoul(q, NULL, 10); + } else { + p = memchr(buf, '\n', count); + len = p ? p - buf : count; + } + + for (s = &lit_cmd[state]; state < LIT_CMD_MAX; s++, state++) { + if (*s && !strncmp(buf, *s, len)) + break; + } + if (state < LIT_CMD_MAX && *s) + error = cmd(state, value); + else + error = -EINVAL; + + return count; +} + +#else +static ssize_t lit_info(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return 0; +} + +static ssize_t lit_ctl(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + return count; +} + +#endif + +static DEVICE_ATTR(lit, 0644, lit_info, lit_ctl); + +static int pmic_light_probe(struct platform_device *pdev) +{ + int ret = 0; + + pr_debug("PMIC ADC start probe\n"); + ret = device_create_file(&(pdev->dev), &dev_attr_lit); + if (ret) { + pr_debug("Can't create device file!\n"); + return -ENODEV; + } + + pmic_light_init_reg(); + + pr_debug("PMIC Light successfully loaded\n"); + return 0; +} + +static struct platform_driver pmic_light_driver_ldm = { + .driver = { + .name = "pmic_light", + }, + .suspend = pmic_light_suspend, + .resume = pmic_light_resume, + .probe = pmic_light_probe, + .remove = pmic_light_remove, +}; + +/* + * Initialization and Exit + */ + +static int __init pmic_light_init(void) +{ + pr_debug("PMIC Light driver loading...\n"); + return platform_driver_register(&pmic_light_driver_ldm); +} +static void __exit pmic_light_exit(void) +{ + platform_driver_unregister(&pmic_light_driver_ldm); + pr_debug("PMIC Light driver successfully unloaded\n"); +} + +/* + * Module entry points + */ + +subsys_initcall(pmic_light_init); +module_exit(pmic_light_exit); + +MODULE_DESCRIPTION("PMIC_LIGHT"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/pmic/mc13892/pmic_power.c linux-2.6.26-lab126/drivers/mxc/pmic/mc13892/pmic_power.c --- linux-2.6.26/drivers/mxc/pmic/mc13892/pmic_power.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13892/pmic_power.c 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,208 @@ +/* + * Copyright 2009 Amazon Technologies, Inc. All Rights Reserved. + * Manish Lachwani (lachwani@lab126.com) + */ + +#include +#include + +/* + * Register specific defines + */ +/* + * Reg Power Control 1 + */ + +#define MC13892_PWRCTRL_USER_OFF_SPI_LSH 3 +#define MC13892_PWRCTRL_USER_OFF_SPI_WID 1 +#define MC13892_PWRCTRL_USER_OFF_SPI_ENABLE 1 +#define MC13892_PWRCTRL_PCT_LSH 0 +#define MC13892_PWRCTRL_PCT_WID 8 +#define MC13892_PWRCTRL_PC_COUNT_LSH 8 +#define MC13892_PWRCTRL_PC_COUNT_WID 4 +#define MC13892_PWRCTRL_PC_MAX_CNT_LSH 12 +#define MC13892_PWRCTRL_PC_MAX_CNT_WID 4 +#define MC13892_PWRCTRL_MEM_TMR_LSH 16 +#define MC13892_PWRCTRL_MEM_TMR_WID 4 +#define MC13892_PWRCTRL_MEM_ALLON_LSH 20 +#define MC13892_PWRCTRL_MEM_ALLON_WID 1 +#define MC13892_PWRCTRL_MEM_ALLON_ENABLE 1 +#define MC13892_PWRCTRL_MEM_ALLON_DISABLE 0 + +/* + * Reg Power Control 2 + */ +#define MC13892_AUTO_RESTART_LSH 0 +#define MC13892_AUTO_RESTART_WID 1 +#define MC13892_EN_BT_ON1B_LSH 1 +#define MC13892_EN_BT_ON1B_WID 1 +#define MC13892_EN_BT_ON2B_LSH 2 +#define MC13892_EN_BT_ON2B_WID 1 +#define MC13892_EN_BT_ON3B_LSH 3 +#define MC13892_EN_BT_ON3B_WID 1 +#define MC13892_DEB_BT_ON1B_LSH 4 +#define MC13892_DEB_BT_ON1B_WID 2 +#define MC13892_DEB_BT_ON2B_LSH 6 +#define MC13892_DEB_BT_ON2B_WID 2 +#define MC13892_DEB_BT_ON3B_LSH 8 +#define MC13892_DEB_BT_ON3B_WID 2 + +/*! + * This function sets user power off in power control register and thus powers + * off the device + */ +void pmic_power_off(void) +{ + unsigned int mask, value; + + mask = BITFMASK(MC13892_PWRCTRL_USER_OFF_SPI); + value = BITFVAL(MC13892_PWRCTRL_USER_OFF_SPI, + MC13892_PWRCTRL_USER_OFF_SPI_ENABLE); + + pmic_write_reg(REG_POWER_CTL0, value, mask); +} + +/*! + * This function enables auto reset after a system reset. + * + * @param en if true, the auto reset is enabled + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_set_auto_reset_en(bool en) +{ + unsigned int reg_val = 0, reg_mask = 0; + + reg_val = BITFVAL(MC13892_AUTO_RESTART, en); + reg_mask = BITFMASK(MC13892_AUTO_RESTART); + + CHECK_ERROR(pmic_write_reg(REG_POWER_CTL2, reg_val, reg_mask)); + return PMIC_SUCCESS; +} + +/*! + * This function configures a system reset on a button. + * + * @param bt type of button. + * @param sys_rst if true, enable the system reset on this button + * @param deb_time sets the debounce time on this button pin + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_set_conf_button(t_button bt, bool sys_rst, int deb_time) +{ + int max_val = 0; + unsigned int reg_val = 0, reg_mask = 0; + + max_val = (1 << MC13892_DEB_BT_ON1B_WID) - 1; + if (deb_time > max_val) + return PMIC_PARAMETER_ERROR; + + switch (bt) { + case BT_ON1B: + reg_val = BITFVAL(MC13892_EN_BT_ON1B, sys_rst) | + BITFVAL(MC13892_DEB_BT_ON1B, deb_time); + reg_mask = BITFMASK(MC13892_EN_BT_ON1B) | + BITFMASK(MC13892_DEB_BT_ON1B); + break; + case BT_ON2B: + reg_val = BITFVAL(MC13892_EN_BT_ON2B, sys_rst) | + BITFVAL(MC13892_DEB_BT_ON2B, deb_time); + reg_mask = BITFMASK(MC13892_EN_BT_ON2B) | + BITFMASK(MC13892_DEB_BT_ON2B); + break; + case BT_ON3B: + reg_val = BITFVAL(MC13892_EN_BT_ON3B, sys_rst) | + BITFVAL(MC13892_DEB_BT_ON3B, deb_time); + reg_mask = BITFMASK(MC13892_EN_BT_ON3B) | + BITFMASK(MC13892_DEB_BT_ON3B); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(REG_POWER_CTL2, reg_val, reg_mask)); + return PMIC_SUCCESS; +} + +/*! + * This function is used to un/subscribe on power event IT. + * + * @param event type of event. + * @param callback event callback function. + * @param sub define if Un/subscribe event. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_event(t_pwr_int event, void *callback, bool sub) +{ + pmic_event_callback_t power_callback; + type_event power_event; + + power_callback.func = callback; + power_callback.param = NULL; + switch (event) { + case PWR_IT_BPONI: + power_event = EVENT_BPONI; + break; + case PWR_IT_LOBATLI: + power_event = EVENT_LOBATLI; + break; + case PWR_IT_LOBATHI: + power_event = EVENT_LOBATHI; + break; + case PWR_IT_ONOFD1I: + power_event = EVENT_ONOFD1I; + break; + case PWR_IT_ONOFD2I: + power_event = EVENT_ONOFD2I; + break; + case PWR_IT_ONOFD3I: + power_event = EVENT_ONOFD3I; + break; + case PWR_IT_SYSRSTI: + power_event = EVENT_SYSRSTI; + break; + case PWR_IT_PCI: + power_event = EVENT_PCI; + break; + case PWR_IT_WARMI: + power_event = EVENT_WARMI; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + if (sub == true) + CHECK_ERROR(pmic_event_subscribe(power_event, power_callback)); + else + CHECK_ERROR(pmic_event_unsubscribe(power_event, power_callback)); + + return PMIC_SUCCESS; +} + +/*! + * This function is used to subscribe on power event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_event_sub(t_pwr_int event, void *callback) +{ + return pmic_power_event(event, callback, true); +} + +/*! + * This function is used to unsubscribe on power event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_event_unsub(t_pwr_int event, void *callback) +{ + return pmic_power_event(event, callback, false); +} diff -urN linux-2.6.26/drivers/mxc/pmic/mc13892/pmic_rtc.c linux-2.6.26-lab126/drivers/mxc/pmic/mc13892/pmic_rtc.c --- linux-2.6.26/drivers/mxc/pmic/mc13892/pmic_rtc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/pmic/mc13892/pmic_rtc.c 2010-08-10 04:15:35.000000000 -0400 @@ -0,0 +1,101 @@ +/* + * Copyright 2009 Amazon Technologies, Inc. All Rights Reserved. + * Manish Lachwani (lachwani@lab126.com) + */ + +#include + +#define MC13892_RTCTIME_TIME_LSH 0 +#define MC13892_RTCTIME_TIME_WID 17 + +#define MC13892_RTCALARM_TIME_LSH 0 +#define MC13892_RTCALARM_TIME_WID 17 + +#define MC13892_RTCDAY_DAY_LSH 0 +#define MC13892_RTCDAY_DAY_WID 15 + +#define MC13892_RTCALARM_DAY_LSH 0 +#define MC13892_RTCALARM_DAY_WID 15 + +/*! + * This function set the real time clock of PMIC + * + * @param pmic_time value of date and time + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_rtc_set_time(struct timeval * pmic_time) +{ + unsigned int tod_reg_val = 0; + unsigned int day_reg_val = 0; + unsigned int mask, value; + + tod_reg_val = pmic_time->tv_sec % 86400; + day_reg_val = pmic_time->tv_sec / 86400; + + mask = BITFMASK(MC13892_RTCTIME_TIME); + value = BITFVAL(MC13892_RTCTIME_TIME, tod_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_TIME, value, mask)); + + mask = BITFMASK(MC13892_RTCDAY_DAY); + value = BITFVAL(MC13892_RTCDAY_DAY, day_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_DAY, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function get the real time clock of PMIC + * + * @param pmic_time return value of date and time + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_rtc_get_time(struct timeval * pmic_time) +{ + unsigned int tod_reg_val = 0; + unsigned int day_reg_val = 0; + unsigned int mask, value; + + mask = BITFMASK(MC13892_RTCTIME_TIME); + CHECK_ERROR(pmic_read_reg(REG_RTC_TIME, &value, mask)); + tod_reg_val = BITFEXT(value, MC13892_RTCTIME_TIME); + + mask = BITFMASK(MC13892_RTCDAY_DAY); + CHECK_ERROR(pmic_read_reg(REG_RTC_DAY, &value, mask)); + day_reg_val = BITFEXT(value, MC13892_RTCDAY_DAY); + + pmic_time->tv_sec = (unsigned long)((unsigned long)(tod_reg_val & + 0x0001FFFF) + + (unsigned long)(day_reg_val * + 86400)); + + return PMIC_SUCCESS; +} + +/*! + * This function set the real time clock of PMIC + * + * @param pmic_time value of date and time + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_rtc_set_time_alarm(struct timeval * pmic_time) +{ + unsigned int tod_reg_val = 0; + unsigned int day_reg_val = 0; + unsigned int mask, value; + + tod_reg_val = pmic_time->tv_sec % 86400; + day_reg_val = pmic_time->tv_sec / 86400; + + mask = BITFMASK(MC13892_RTCALARM_TIME); + value = BITFVAL(MC13892_RTCALARM_TIME, tod_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_ALARM, value, mask)); + + mask = BITFMASK(MC13892_RTCALARM_DAY); + value = BITFVAL(MC13892_RTCALARM_DAY, day_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_DAY_ALARM, value, mask)); + + return PMIC_SUCCESS; +} diff -urN linux-2.6.26/drivers/mxc/security/Kconfig linux-2.6.26-lab126/drivers/mxc/security/Kconfig --- linux-2.6.26/drivers/mxc/security/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/Kconfig 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,67 @@ +menu "MXC Security Drivers" + +config MXC_SECURITY_SCC + tristate "MXC SCC Driver" + default n + ---help--- + This module contains the core API's for accessing the SCC module. + If you are unsure about this, say N here. + +config MXC_SECURITY_SCC2 + tristate "MXC SCC2 Driver" + depends on ARCH_MX37 || ARCH_MX51 + default n + ---help--- + This module contains the core API's for accessing the SCC2 module. + If you are unsure about this, say N here. + +config SCC_DEBUG + bool "MXC SCC Module debugging" + depends on MXC_SECURITY_SCC || MXC_SECURITY_SCC2 + ---help--- + This is an option for use by developers; most people should + say N here. This enables SCC module debugging. + +config MXC_SECURITY_RNG + tristate "MXC RNG Driver" + depends on ARCH_MXC + depends on !ARCH_MXC91321 + depends on !ARCH_MX27 + default n + select MXC_SECURITY_CORE + ---help--- + This module contains the core API's for accessing the RNG module. + If you are unsure about this, say N here. + +config MXC_RNG_TEST_DRIVER + bool "MXC RNG debug register" + depends on MXC_SECURITY_RNG + default n + ---help--- + This option enables the RNG kcore driver to provide peek-poke facility + into the RNG device registers. Enable this, only for development and + testing purposes. +config MXC_RNG_DEBUG + bool "MXC RNG Module Dubugging" + depends on MXC_SECURITY_RNG + default n + ---help--- + This is an option for use by developers; most people should + say N here. This enables RNG module debugging. + +config MXC_DRYICE + tristate "MXC DryIce Driver" + depends on ARCH_MX25 + default n + ---help--- + This module contains the core API's for accessing the DryIce module. + If you are unsure about this, say N here. + +config MXC_SECURITY_CORE + tristate + +if (ARCH_MX37 || ARCH_MX51 || ARCH_MX27) +source "drivers/mxc/security/sahara2/Kconfig" +endif + +endmenu diff -urN linux-2.6.26/drivers/mxc/security/Makefile linux-2.6.26-lab126/drivers/mxc/security/Makefile --- linux-2.6.26/drivers/mxc/security/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/Makefile 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,18 @@ +# Makefile for the Linux MXC Security API +ifeq ($( SCC_DEBUG),y) +EXTRA_CFLAGS += -DDEBUG +endif +ifeq ($(MXC_HAC_TEST_DEBUG),y) +EXTRA_CFLAGS += -DDEBUG +endif +ifeq ($(MXC_RTIC_TEST_DEBUG),y) +EXTRA_CFLAGS += -DDEBUG +endif +EXTRA_CFLAGS += -DMXC -DLINUX_KERNEL + +obj-$(CONFIG_MXC_SECURITY_SCC2) += scc2_driver.o +obj-$(CONFIG_MXC_SECURITY_SCC) += mxc_scc.o +obj-$(CONFIG_MXC_SECURITY_RNG) += rng/ +obj-$(CONFIG_MXC_SECURITY_CORE) += mxc_sec_mod.o +obj-$(CONFIG_MXC_SAHARA) += sahara2/ +obj-$(CONFIG_MXC_DRYICE) += dryice.o diff -urN linux-2.6.26/drivers/mxc/security/dryice-regs.h linux-2.6.26-lab126/drivers/mxc/security/dryice-regs.h --- linux-2.6.26/drivers/mxc/security/dryice-regs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/dryice-regs.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,207 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +#ifndef __DRYICE_REGS_H__ +#define __DRYICE_REGS_H__ + +/*********************************************************************** + * DryIce Register Definitions + ***********************************************************************/ + +/* DryIce Time Counter MSB Reg */ +#define DTCMR 0x00 + +/* DryIce Time Counter LSB Reg */ +#define DTCLR 0x04 + +/* DryIce Clock Alarm MSB Reg */ +#define DCAMR 0x08 + +/* DryIce Clock Alarm LSB Reg */ +#define DCALR 0x0c + +/* DryIce Control Reg */ +#define DCR 0x10 +#define DCR_TDCHL (1 << 30) /* Tamper Detect Config Hard Lock */ +#define DCR_TDCSL (1 << 29) /* Tamper Detect COnfig Soft Lock */ +#define DCR_KSHL (1 << 28) /* Key Select Hard Lock */ +#define DCR_KSSL (1 << 27) /* Key Select Soft Lock */ +#define DCR_RKHL (1 << 26) /* Random Key Hard Lock */ +#define DCR_RKSL (1 << 25) /* Random Key Soft Lock */ +#define DCR_PKRHL (1 << 24) /* Programmed Key Read Hard Lock */ +#define DCR_PKRSL (1 << 23) /* Programmed Key Read Soft Lock */ +#define DCR_PKWHL (1 << 22) /* Programmed Key Write Hard Lock */ +#define DCR_PKWSL (1 << 21) /* Programmed Key Write Soft Lock */ +#define DCR_MCHL (1 << 20) /* Monotonic Counter Hard Lock */ +#define DCR_MCSL (1 << 19) /* Monotonic Counter Soft Lock */ +#define DCR_TCHL (1 << 18) /* Time Counter Hard Lock */ +#define DCR_TCSL (1 << 17) /* Time Counter Soft Lock */ +#define DCR_FSHL (1 << 16) /* Failure State Hard Lock */ +#define DCR_NSA (1 << 15) /* Non-Secure Access */ +#define DCR_OSCB (1 << 14) /* Oscillator Bypass */ +#define DCR_APE (1 << 4) /* Alarm Pin Enable */ +#define DCR_TCE (1 << 3) /* Time Counter Enable */ +#define DCR_MCE (1 << 2) /* Monotonic Counter Enable */ +#define DCR_SWR (1 << 0) /* Software Reset (w/o) */ + +/* DryIce Status Reg */ +#define DSR 0x14 +#define DSR_WTD (1 << 23) /* Wire-mesh Tampering Detected */ +#define DSR_ETBD (1 << 22) /* External Tampering B Detected */ +#define DSR_ETAD (1 << 21) /* External Tampering A Detected */ +#define DSR_EBD (1 << 20) /* External Boot Detected */ +#define DSR_SAD (1 << 19) /* Security Alarm Detected */ +#define DSR_TTD (1 << 18) /* Temperature Tampering Detected */ +#define DSR_CTD (1 << 17) /* Clock Tampering Detected */ +#define DSR_VTD (1 << 16) /* Voltage Tampering Detected */ +#define DSR_KBF (1 << 11) /* Key Busy Flag */ +#define DSR_WBF (1 << 10) /* Write Busy Flag */ +#define DSR_WNF (1 << 9) /* Write Next Flag */ +#define DSR_WCF (1 << 8) /* Write Complete Flag */ +#define DSR_WEF (1 << 7) /* Write Error Flag */ +#define DSR_RKE (1 << 6) /* Random Key Error */ +#define DSR_RKV (1 << 5) /* Random Key Valid */ +#define DSR_CAF (1 << 4) /* Clock Alarm Flag */ +#define DSR_MCO (1 << 3) /* Monotonic Counter Overflow */ +#define DSR_TCO (1 << 2) /* Time Counter Overflow */ +#define DSR_NVF (1 << 1) /* Non-Valid Flag */ +#define DSR_SVF (1 << 0) /* Security Violation Flag */ + +#define DSR_TAMPER_BITS (DSR_WTD | DSR_ETBD | DSR_ETAD | DSR_EBD | DSR_SAD | \ + DSR_TTD | DSR_CTD | DSR_VTD | DSR_MCO | DSR_TCO) + +/* ensure that external tamper defs match register bits */ +#if DSR_WTD != DI_TAMPER_EVENT_WTD +#error "Mismatch between DSR_WTD and DI_TAMPER_EVENT_WTD" +#endif +#if DSR_ETBD != DI_TAMPER_EVENT_ETBD +#error "Mismatch between DSR_ETBD and DI_TAMPER_EVENT_ETBD" +#endif +#if DSR_ETAD != DI_TAMPER_EVENT_ETAD +#error "Mismatch between DSR_ETAD and DI_TAMPER_EVENT_ETAD" +#endif +#if DSR_EBD != DI_TAMPER_EVENT_EBD +#error "Mismatch between DSR_EBD and DI_TAMPER_EVENT_EBD" +#endif +#if DSR_SAD != DI_TAMPER_EVENT_SAD +#error "Mismatch between DSR_SAD and DI_TAMPER_EVENT_SAD" +#endif +#if DSR_TTD != DI_TAMPER_EVENT_TTD +#error "Mismatch between DSR_TTD and DI_TAMPER_EVENT_TTD" +#endif +#if DSR_CTD != DI_TAMPER_EVENT_CTD +#error "Mismatch between DSR_CTD and DI_TAMPER_EVENT_CTD" +#endif +#if DSR_VTD != DI_TAMPER_EVENT_VTD +#error "Mismatch between DSR_VTD and DI_TAMPER_EVENT_VTD" +#endif +#if DSR_MCO != DI_TAMPER_EVENT_MCO +#error "Mismatch between DSR_MCO and DI_TAMPER_EVENT_MCO" +#endif +#if DSR_TCO != DI_TAMPER_EVENT_TCO +#error "Mismatch between DSR_TCO and DI_TAMPER_EVENT_TCO" +#endif + +/* DryIce Interrupt Enable Reg */ +#define DIER 0x18 +#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */ +#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */ +#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */ +#define DIER_RKIE (1 << 5) /* Random Key Interrupt Enable */ +#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */ +#define DIER_MOIE (1 << 3) /* Monotonic Overflow Interrupt En */ +#define DIER_TOIE (1 << 2) /* Time Overflow Interrupt Enable */ +#define DIER_SVIE (1 << 0) /* Security Violation Interrupt En */ + +/* DryIce Monotonic Counter Reg */ +#define DMCR 0x1c + +/* DryIce Key Select Reg */ +#define DKSR 0x20 +#define DKSR_IIM_KEY 0x0 +#define DKSR_PROG_KEY 0x4 +#define DKSR_RAND_KEY 0x5 +#define DKSR_PROG_XOR_IIM_KEY 0x6 +#define DKSR_RAND_XOR_IIM_KEY 0x7 + +/* DryIce Key Control Reg */ +#define DKCR 0x24 +#define DKCR_LRK (1 << 0) /* Load Random Key */ + +/* DryIce Tamper Configuration Reg */ +#define DTCR 0x28 +#define DTCR_ETGFB_SHIFT 27 /* Ext Tamper Glitch Filter B */ +#define DTCR_ETGFB_MASK 0xf8000000 +#define DTCR_ETGFA_SHIFT 22 /* Ext Tamper Glitch Filter A */ +#define DTCR_ETGFA_MASK 0x07c00000 +#define DTCR_WTGF_SHIFT 17 /* Wire-mesh Tamper Glitch Filter */ +#define DTCR_WTGF_MASK 0x003e0000 +#define DTCR_WGFE (1 << 16) /* Wire-mesh Glitch Filter Enable */ +#define DTCR_SAOE (1 << 15) /* Security Alarm Output Enable */ +#define DTCR_MOE (1 << 9) /* Monotonic Overflow Enable */ +#define DTCR_TOE (1 << 8) /* Time Overflow Enable */ +#define DTCR_WTE (1 << 7) /* Wire-mesh Tampering Enable */ +#define DTCR_ETBE (1 << 6) /* External Tampering B Enable */ +#define DTCR_ETAE (1 << 5) /* External Tampering A Enable */ +#define DTCR_EBE (1 << 4) /* External Boot Enable */ +#define DTCR_SAIE (1 << 3) /* Security Alarm Input Enable */ +#define DTCR_TTE (1 << 2) /* Temperature Tamper Enable */ +#define DTCR_CTE (1 << 1) /* Clock Tamper Enable */ +#define DTCR_VTE (1 << 0) /* Voltage Tamper Enable */ + +/* DryIce Analog Configuration Reg */ +#define DACR 0x2c +#define DACR_VRC_SHIFT 6 /* Voltage Reference Configuration */ +#define DACR_VRC_MASK 0x000001c0 +#define DACR_HTDC_SHIFT 3 /* High Temperature Detect Configuration */ +#define DACR_HTDC_MASK 0x00000038 +#define DACR_LTDC_SHIFT 0 /* Low Temperature Detect Configuration */ +#define DACR_LTDC_MASK 0x00000007 + +/* DryIce General Purpose Reg */ +#define DGPR 0x3c + +/* DryIce Programmed Key0-7 Regs */ +#define DPKR0 0x40 +#define DPKR1 0x44 +#define DPKR2 0x48 +#define DPKR3 0x4c +#define DPKR4 0x50 +#define DPKR5 0x54 +#define DPKR6 0x58 +#define DPKR7 0x5c + +/* DryIce Random Key0-7 Regs */ +#define DRKR0 0x60 +#define DRKR1 0x64 +#define DRKR2 0x68 +#define DRKR3 0x6c +#define DRKR4 0x70 +#define DRKR5 0x74 +#define DRKR6 0x78 +#define DRKR7 0x7c + +#define DI_ADDRESS_RANGE (DRKR7 + 4) + +/* + * this doesn't really belong here but the + * portability layer doesn't include it + */ +#ifdef LINUX_KERNEL +#define EXTERN_SYMBOL(symbol) EXPORT_SYMBOL(symbol) +#else +#define EXTERN_SYMBOL(symbol) do {} while (0) +#endif + +#endif /* __DRYICE_REGS_H__ */ diff -urN linux-2.6.26/drivers/mxc/security/dryice.c linux-2.6.26-lab126/drivers/mxc/security/dryice.c --- linux-2.6.26/drivers/mxc/security/dryice.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/dryice.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,1121 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +#undef DI_DEBUG /* enable debug messages */ +#undef DI_DEBUG_REGIO /* show register read/write */ +#undef DI_TESTING /* include test code */ + +#ifdef DI_DEBUG +#define di_debug(fmt, arg...) os_printk(KERN_INFO fmt, ##arg) +#else +#define di_debug(fmt, arg...) do {} while (0) +#endif + +#define di_info(fmt, arg...) os_printk(KERN_INFO fmt, ##arg) +#define di_warn(fmt, arg...) os_printk(KERN_WARNING fmt, ##arg) + +#include "sahara2/include/portable_os.h" +#include "dryice.h" +#include "dryice-regs.h" + +/* mask of the lock-related function flags */ +#define DI_FUNC_LOCK_FLAGS (DI_FUNC_FLAG_READ_LOCK | \ + DI_FUNC_FLAG_WRITE_LOCK | \ + DI_FUNC_FLAG_HARD_LOCK) + +/* + * dryice hardware states + */ +enum di_states { + DI_STATE_VALID = 0, + DI_STATE_NON_VALID, + DI_STATE_FAILURE, +}; + +/* + * todo list actions + */ +enum todo_actions { + TODO_ACT_WRITE_VAL, + TODO_ACT_WRITE_PTR, + TODO_ACT_WRITE_PTR32, + TODO_ACT_ASSIGN, + TODO_ACT_WAIT_RKG, +}; + +/* + * todo list status + */ +enum todo_status { + TODO_ST_LOADING, + TODO_ST_READY, + TODO_ST_PEND_WCF, + TODO_ST_PEND_RKG, + TODO_ST_DONE, +}; + +OS_DEV_INIT_DCL(dryice_init) +OS_DEV_SHUTDOWN_DCL(dryice_exit) +OS_DEV_ISR_DCL(dryice_norm_irq) +OS_WAIT_OBJECT(done_queue); +OS_WAIT_OBJECT(exit_queue); + +struct dryice_data { + int busy; /* enforce exclusive access */ + os_lock_t busy_lock; + int exit_flag; /* don't start new operations */ + + uint32_t baseaddr; /* physical base address */ + void *ioaddr; /* virtual base address */ + + /* interrupt handling */ + struct irq_struct { + os_interrupt_id_t irq; + int set; + } irq_norm, irq_sec; + + struct clk *clk; /* clock control */ + + int key_programmed; /* key has been programmed */ + int key_selected; /* key has been selected */ + + /* callback function and cookie */ + void (*cb_func)(di_return_t rc, unsigned long cookie); + unsigned long cb_cookie; +} *di = NULL; + +#define TODO_LIST_LEN 12 +static struct { + struct td { + enum todo_actions action; + uint32_t src; + uint32_t dst; + int num; + } list[TODO_LIST_LEN]; + int cur; /* current todo pointer */ + int num; /* number of todo's on the list */ + int async; /* non-zero if list is async */ + int status; /* current status of the list */ + di_return_t rc; /* return code generated by the list */ +} todo; + +/* + * dryice register read/write functions + */ +#ifdef DI_DEBUG_REGIO +static uint32_t di_read(int reg) +{ + uint32_t val = os_read32(di->ioaddr + (reg)); + di_info("di_read(0x%02x) = 0x%08x\n", reg, val); + + return val; +} + +static void di_write(uint32_t val, int reg) +{ + di_info("dryice_write_reg(0x%08x, 0x%02x)\n", val, reg); + os_write32(di->ioaddr + (reg), val); +} +#else +#define di_read(reg) os_read32(di->ioaddr + (reg)) +#define di_write(val, reg) os_write32(di->ioaddr + (reg), val); +#endif + +/* + * set the dryice busy flag atomically, allowing + * for case where the driver is trying to exit. + */ +static int di_busy_set(void) +{ + os_lock_context_t context; + int rc = 0; + + os_lock_save_context(di->busy_lock, context); + if (di->exit_flag || di->busy) + rc = 1; + else + di->busy = 1; + os_unlock_restore_context(di->busy_lock, context); + + return rc; +} + +/* + * clear the dryice busy flag + */ +static inline void di_busy_clear(void) +{ + /* don't acquire the lock because the race is benign */ + di->busy = 0; + + if (di->exit_flag) + os_wake_sleepers(exit_queue); +} + +/* + * return the current state of dryice + * (valid, non-valid, or failure) + */ +static enum di_states di_state(void) +{ + enum di_states state = DI_STATE_VALID; + uint32_t dsr = di_read(DSR); + + if (dsr & DSR_NVF) + state = DI_STATE_NON_VALID; + else if (dsr & DSR_SVF) + state = DI_STATE_FAILURE; + + return state; +} + +#define DI_WRITE_LOOP_CNT 0x1000 +/* + * the write-error flag is something that shouldn't get set + * during normal operation. if it's set something is terribly + * wrong. the best we can do is try to clear the bit and hope + * that dryice will recover. this situation is similar to an + * unexpected bus fault in terms of severity. + */ +static void try_to_clear_wef(void) +{ + int cnt; + + while (1) { + di_write(DSR_WEF, DSR); + for (cnt = 0; cnt < DI_WRITE_LOOP_CNT; cnt++) { + if ((di_read(DSR) & DSR_WEF) == 0) + break; + } + di_warn("WARNING: DryIce cannot clear DSR_WEF " + "(Write Error Flag)!\n"); + } +} + +/* + * write a dryice register and loop, waiting for it + * to complete. use only during driver initialization. + * returns 0 on success or 1 on write failure. + */ +static int di_write_loop(uint32_t val, int reg) +{ + int rc = 0; + int cnt; + + di_debug("FUNC: %s\n", __func__); + di_write(val, reg); + + for (cnt = 0; cnt < DI_WRITE_LOOP_CNT; cnt++) { + uint32_t dsr = di_read(DSR); + if (dsr & DSR_WEF) { + try_to_clear_wef(); + rc = 1; + } + if (dsr & DSR_WCF) + break; + } + di_debug("wait_write_loop looped %d times\n", cnt); + if (cnt == DI_WRITE_LOOP_CNT) + rc = 1; + + if (rc) + di_warn("DryIce wait_write_done: WRITE ERROR!\n"); + return rc; +} + +/* + * initialize the todo list. must be called + * before adding items to the list. + */ +static void todo_init(int async_flag) +{ + di_debug("FUNC: %s\n", __func__); + todo.cur = 0; + todo.num = 0; + todo.async = async_flag; + todo.rc = 0; + todo.status = TODO_ST_LOADING; +} + +/* + * perform the current action on the todo list + */ +#define TC todo.list[todo.cur] +void todo_cur(void) +{ + di_debug("FUNC: %s[%d]\n", __func__, todo.cur); + switch (TC.action) { + case TODO_ACT_WRITE_VAL: + di_debug(" TODO_ACT_WRITE_VAL\n"); + /* enable the write-completion interrupt */ + todo.status = TODO_ST_PEND_WCF; + di_write(di_read(DIER) | DIER_WCIE, DIER); + + di_write(TC.src, TC.dst); + break; + + case TODO_ACT_WRITE_PTR32: + di_debug(" TODO_ACT_WRITE_PTR32\n"); + /* enable the write-completion interrupt */ + todo.status = TODO_ST_PEND_WCF; + di_write(di_read(DIER) | DIER_WCIE, DIER); + + di_write(*(uint32_t *)TC.src, TC.dst); + break; + + case TODO_ACT_WRITE_PTR: + { + uint8_t *p = (uint8_t *)TC.src; + uint32_t val = 0; + int num = TC.num; + + di_debug(" TODO_ACT_WRITE_PTR\n"); + while (num--) + val = (val << 8) | *p++; + + /* enable the write-completion interrupt */ + todo.status = TODO_ST_PEND_WCF; + di_write(di_read(DIER) | DIER_WCIE, DIER); + + di_write(val, TC.dst); + } + break; + + case TODO_ACT_ASSIGN: + di_debug(" TODO_ACT_ASSIGN\n"); + switch (TC.num) { + case 1: + *(uint8_t *)TC.dst = TC.src; + break; + case 2: + *(uint16_t *)TC.dst = TC.src; + break; + case 4: + *(uint32_t *)TC.dst = TC.src; + break; + default: + di_warn("Unexpected size in TODO_ACT_ASSIGN\n"); + break; + } + break; + + case TODO_ACT_WAIT_RKG: + di_debug(" TODO_ACT_WAIT_RKG\n"); + /* enable the random-key interrupt */ + todo.status = TODO_ST_PEND_RKG; + di_write(di_read(DIER) | DIER_RKIE, DIER); + break; + + default: + di_debug(" TODO_ACT_NOOP\n"); + break; + } +} + +/* + * called when done with the todo list. + * if async, it does the callback. + * if blocking, it wakes up the caller. + */ +static void todo_done(di_return_t rc) +{ + todo.rc = rc; + todo.status = TODO_ST_DONE; + if (todo.async) { + di_busy_clear(); + if (di->cb_func) + di->cb_func(rc, di->cb_cookie); + } else + os_wake_sleepers(done_queue); +} + +/* + * performs the actions sequentially from the todo list + * until it encounters an item that isn't ready. + */ +static void todo_run(void) +{ + di_debug("FUNC: %s\n", __func__); + while (todo.status == TODO_ST_READY) { + if (todo.cur == todo.num) { + todo_done(0); + break; + } + todo_cur(); + if (todo.status != TODO_ST_READY) + break; + todo.cur++; + } +} + +/* + * kick off the todo list by making it ready + */ +static void todo_start(void) +{ + di_debug("FUNC: %s\n", __func__); + todo.status = TODO_ST_READY; + todo_run(); +} + +/* + * blocking callers sleep here until the todo list is done + */ +static int todo_wait_done(void) +{ + di_debug("FUNC: %s\n", __func__); + os_sleep(done_queue, todo.status == TODO_ST_DONE, 0); + + return todo.rc; +} + +/* + * add a dryice register write to the todo list. + * the value to be written is supplied. + */ +#define todo_write_val(val, reg) \ + todo_add(TODO_ACT_WRITE_VAL, val, reg, 0) + +/* + * add a dryice register write to the todo list. + * "size" bytes pointed to by addr will be written. + */ +#define todo_write_ptr(addr, reg, size) \ + todo_add(TODO_ACT_WRITE_PTR, (uint32_t)addr, reg, size) + +/* + * add a dryice register write to the todo list. + * the word pointed to by addr will be written. + */ +#define todo_write_ptr32(addr, reg) \ + todo_add(TODO_ACT_WRITE_PTR32, (uint32_t)addr, reg, 0) + +/* + * add a dryice memory write to the todo list. + * object can only have a size of 1, 2, or 4 bytes. + */ +#define todo_assign(var, val) \ + todo_add(TODO_ACT_ASSIGN, val, (uint32_t)&(var), sizeof(var)) + +#define todo_wait_rkg() \ + todo_add(TODO_ACT_WAIT_RKG, 0, 0, 0) + +static void todo_add(int action, uint32_t src, uint32_t dst, int num) +{ + struct td *p = &todo.list[todo.num]; + + di_debug("FUNC: %s\n", __func__); + if (todo.num == TODO_LIST_LEN) { + di_warn("WARNING: DryIce todo-list overflow!\n"); + return; + } + p->action = action; + p->src = src; + p->dst = dst; + p->num = num; + todo.num++; +} + +#if defined(DI_DEBUG) || defined(DI_TESTING) +/* + * print out the contents of the dryice status register + * with all the bits decoded + */ +static void show_dsr(const char *heading) +{ + uint32_t dsr = di_read(DSR); + + di_info("%s\n", heading); + if (dsr & DSR_TAMPER_BITS) { + if (dsr & DSR_WTD) + di_info("Wire-mesh Tampering Detected\n"); + if (dsr & DSR_ETBD) + di_info("External Tampering B Detected\n"); + if (dsr & DSR_ETAD) + di_info("External Tampering A Detected\n"); + if (dsr & DSR_EBD) + di_info("External Boot Detected\n"); + if (dsr & DSR_SAD) + di_info("Security Alarm Detected\n"); + if (dsr & DSR_TTD) + di_info("Temperature Tampering Detected\n"); + if (dsr & DSR_CTD) + di_info("Clock Tampering Detected\n"); + if (dsr & DSR_VTD) + di_info("Voltage Tampering Detected\n"); + if (dsr & DSR_MCO) + di_info("Monotonic Counter Overflow\n"); + if (dsr & DSR_TCO) + di_info("Time Counter Overflow\n"); + } else + di_info("No Tamper Events Detected\n"); + + di_info("%d Key Busy Flag\n", !!(dsr & DSR_KBF)); + di_info("%d Write Busy Flag\n", !!(dsr & DSR_WBF)); + di_info("%d Write Next Flag\n", !!(dsr & DSR_WNF)); + di_info("%d Write Complete Flag\n", !!(dsr & DSR_WCF)); + di_info("%d Write Error Flag\n", !!(dsr & DSR_WEF)); + di_info("%d Random Key Error\n", !!(dsr & DSR_RKE)); + di_info("%d Random Key Valid\n", !!(dsr & DSR_RKV)); + di_info("%d Clock Alarm Flag\n", !!(dsr & DSR_CAF)); + di_info("%d Non-Valid Flag\n", !!(dsr & DSR_NVF)); + di_info("%d Security Violation Flag\n", !!(dsr & DSR_SVF)); +} + +/* + * print out a key in hex + */ +static void print_key(const char *tag, uint8_t *key, int bits) +{ + int bytes = (bits + 7) / 8; + + di_info("%s", tag); + while (bytes--) + os_printk("%02x", *key++); + os_printk("\n"); +} +#endif /* defined(DI_DEBUG) || defined(DI_TESTING) */ + +/* + * dryice normal interrupt service routine + */ +OS_DEV_ISR(dryice_norm_irq) +{ + /* save dryice status register */ + uint32_t dsr = di_read(DSR); + + if (dsr & DSR_WCF) { + /* disable the write-completion interrupt */ + di_write(di_read(DIER) & ~DIER_WCIE, DIER); + + if (todo.status == TODO_ST_PEND_WCF) { + if (dsr & DSR_WEF) { + try_to_clear_wef(); + todo_done(DI_ERR_WRITE); + } else { + todo.cur++; + todo.status = TODO_ST_READY; + todo_run(); + } + } + } else if (dsr & (DSR_RKV | DSR_RKE)) { + /* disable the random-key-gen interrupt */ + di_write(di_read(DIER) & ~DIER_RKIE, DIER); + + if (todo.status == TODO_ST_PEND_RKG) { + if (dsr & DSR_RKE) + todo_done(DI_ERR_FAIL); + else { + todo.cur++; + todo.status = TODO_ST_READY; + todo_run(); + } + } + } else + di_warn("unexpected interrupt\n"); + os_dev_isr_return(1); +} + +/* write loop with error handling -- for init only */ +#define di_write_loop_goto(val, reg, rc, label) \ + do {if (di_write_loop(val, reg)) \ + {rc = OS_ERROR_FAIL_S; goto label; } } while (0) + +/* + * dryice driver initialization + */ +OS_DEV_INIT(dryice_init) +{ + di_return_t rc = 0; + + di_info("MXC DryIce driver\n"); + + /* allocate memory */ + di = os_alloc_memory(sizeof(*di), GFP_KERNEL); + if (di == NULL) { + rc = OS_ERROR_NO_MEMORY_S; + goto err_alloc; + } + memset(di, 0, sizeof(*di)); + di->baseaddr = DRYICE_BASE_ADDR; + di->irq_norm.irq = MXC_INT_DRYICE_NORM; + di->irq_sec.irq = MXC_INT_DRYICE_SEC; + + /* map i/o registers */ + di->ioaddr = os_map_device(di->baseaddr, DI_ADDRESS_RANGE); + if (di->ioaddr == NULL) { + rc = OS_ERROR_FAIL_S; + goto err_iomap; + } + + /* allocate locks */ + di->busy_lock = os_lock_alloc_init(); + if (di->busy_lock == NULL) { + rc = OS_ERROR_NO_MEMORY_S; + goto err_locks; + } + + /* enable clocks (is there a portable way to do this?) */ + di->clk = clk_get(NULL, "dryice_clk"); + clk_enable(di->clk); + + /* register for interrupts */ + rc = os_register_interrupt("dry_ice", di->irq_norm.irq, + OS_DEV_ISR_REF(dryice_norm_irq)); + if (rc) + goto err_irqs; + else + di->irq_norm.set = 1; + + /* + * DRYICE HARDWARE INIT + */ + +#ifdef DI_DEBUG + show_dsr("DSR Pre-Initialization State"); +#endif + + if (di_state() == DI_STATE_NON_VALID) { + uint32_t dsr = di_read(DSR); + + di_debug("initializing from non-valid state\n"); + + /* clear security violation flag */ + if (dsr & DSR_SVF) + di_write_loop_goto(DSR_SVF, DSR, rc, err_write); + + /* clear tamper detect flags */ + if (dsr & DSR_TAMPER_BITS) + di_write_loop_goto(DSR_TAMPER_BITS, DSR, rc, err_write); + + /* initialize timers */ + di_write_loop_goto(0, DTCLR, rc, err_write); + di_write_loop_goto(0, DTCMR, rc, err_write); + di_write_loop_goto(0, DMCR, rc, err_write); + + /* clear non-valid flag */ + di_write_loop_goto(DSR_NVF, DSR, rc, err_write); + } + + /* set tamper events we are interested in watching */ + di_write_loop_goto(DTCR_WTE | DTCR_ETBE | DTCR_ETAE, DTCR, rc, + err_write); +#ifdef DI_DEBUG + show_dsr("DSR Post-Initialization State"); +#endif + os_dev_init_return(OS_ERROR_OK_S); + +err_write: + /* unregister interrupts */ + if (di->irq_norm.set) + os_deregister_interrupt(di->irq_norm.irq); + if (di->irq_sec.set) + os_deregister_interrupt(di->irq_sec.irq); + + /* turn off clocks (is there a portable way to do this?) */ + clk_disable(di->clk); + clk_put(di->clk); + +err_irqs: + /* unallocate locks */ + os_lock_deallocate(di->busy_lock); + +err_locks: + /* unmap i/o registers */ + os_unmap_device(di->ioaddr, DI_ADDRESS_RANGE); + +err_iomap: + /* free the dryice struct */ + os_free_memory(di); + +err_alloc: + os_dev_init_return(rc); +} + +/* + * dryice driver exit routine + */ +OS_DEV_SHUTDOWN(dryice_exit) +{ + /* don't allow new operations */ + di->exit_flag = 1; + + /* wait for the current operation to complete */ + os_sleep(exit_queue, di->busy == 0, 0); + + /* unregister interrupts */ + if (di->irq_norm.set) + os_deregister_interrupt(di->irq_norm.irq); + if (di->irq_sec.set) + os_deregister_interrupt(di->irq_sec.irq); + + /* turn off clocks (is there a portable way to do this?) */ + clk_disable(di->clk); + clk_put(di->clk); + + /* unallocate locks */ + os_lock_deallocate(di->busy_lock); + + /* unmap i/o registers */ + os_unmap_device(di->ioaddr, DI_ADDRESS_RANGE); + + /* free the dryice struct */ + os_free_memory(di); + + os_dev_shutdown_return(OS_ERROR_OK_S); +} + +di_return_t dryice_set_programmed_key(const void *key_data, int key_bits, + int flags) +{ + uint32_t dcr; + int key_bytes, reg; + di_return_t rc = 0; + + if (di_busy_set()) + return DI_ERR_BUSY; + + if (key_data == NULL) { + rc = DI_ERR_INVAL; + goto err; + } + if (key_bits < 0 || key_bits > MAX_KEY_LEN || key_bits % 8) { + rc = DI_ERR_INVAL; + goto err; + } + if (flags & DI_FUNC_FLAG_WORD_KEY) { + if (key_bits % 32 || (uint32_t)key_data & 0x3) { + rc = DI_ERR_INVAL; + goto err; + } + } + if (di->key_programmed) { + rc = DI_ERR_INUSE; + goto err; + } + if (di_state() == DI_STATE_FAILURE) { + rc = DI_ERR_STATE; + goto err; + } + dcr = di_read(DCR); + if (dcr & DCR_PKWHL) { + rc = DI_ERR_HLOCK; + goto err; + } + if (dcr & DCR_PKWSL) { + rc = DI_ERR_SLOCK; + goto err; + } + key_bytes = key_bits / 8; + + todo_init((flags & DI_FUNC_FLAG_ASYNC) != 0); + + /* accomodate busses that can only do 32-bit transfers */ + if (flags & DI_FUNC_FLAG_WORD_KEY) { + uint32_t *keyp = (void *)key_data; + + for (reg = 0; reg < MAX_KEY_WORDS; reg++) { + if (reg < MAX_KEY_WORDS - key_bytes / 4) + todo_write_val(0, DPKR7 - reg * 4); + else { + todo_write_ptr32(keyp, DPKR7 - reg * 4); + keyp++; + } + } + } else { + uint8_t *keyp = (void *)key_data; + + for (reg = 0; reg < MAX_KEY_WORDS; reg++) { + int size = key_bytes - (MAX_KEY_WORDS - reg - 1) * 4; + if (size <= 0) + todo_write_val(0, DPKR7 - reg * 4); + else { + if (size > 4) + size = 4; + todo_write_ptr(keyp, DPKR7 - reg * 4, size); + keyp += size; + } + } + } + todo_assign(di->key_programmed, 1); + + if (flags & DI_FUNC_LOCK_FLAGS) { + dcr = di_read(DCR); + if (flags & DI_FUNC_FLAG_READ_LOCK) { + if (flags & DI_FUNC_FLAG_HARD_LOCK) + dcr |= DCR_PKRHL; + else + dcr |= DCR_PKRSL; + } + if (flags & DI_FUNC_FLAG_WRITE_LOCK) { + if (flags & DI_FUNC_FLAG_HARD_LOCK) + dcr |= DCR_PKWHL; + else + dcr |= DCR_PKWSL; + } + todo_write_val(dcr, DCR); + } + todo_start(); + + if (flags & DI_FUNC_FLAG_ASYNC) + return 0; + + rc = todo_wait_done(); +err: + di_busy_clear(); + return rc; +} +EXTERN_SYMBOL(dryice_set_programmed_key); + +di_return_t dryice_get_programmed_key(uint8_t *key_data, int key_bits) +{ + int reg, byte, key_bytes; + uint32_t dcr, dpkr; + di_return_t rc = 0; + + if (di_busy_set()) + return DI_ERR_BUSY; + + if (key_data == NULL) { + rc = DI_ERR_INVAL; + goto err; + } + if (key_bits < 0 || key_bits > MAX_KEY_LEN || key_bits % 8) { + rc = DI_ERR_INVAL; + goto err; + } + #if 0 + if (!di->key_programmed) { + rc = DI_ERR_UNSET; + goto err; + } + #endif + if (di_state() == DI_STATE_FAILURE) { + rc = DI_ERR_STATE; + goto err; + } + dcr = di_read(DCR); + if (dcr & DCR_PKRHL) { + rc = DI_ERR_HLOCK; + goto err; + } + if (dcr & DCR_PKRSL) { + rc = DI_ERR_SLOCK; + goto err; + } + key_bytes = key_bits / 8; + + /* read key */ + for (reg = 0; reg < MAX_KEY_WORDS; reg++) { + if (reg < (MAX_KEY_BYTES - key_bytes) / 4) + continue; + dpkr = di_read(DPKR7 - reg * 4); + + for (byte = 0; byte < 4; byte++) { + if (reg * 4 + byte >= MAX_KEY_BYTES - key_bytes) { + int shift = 24 - byte * 8; + *key_data++ = (dpkr >> shift) & 0xff; + } + } + dpkr = 0; /* cleared for security */ + } +err: + di_busy_clear(); + return rc; +} +EXTERN_SYMBOL(dryice_get_programmed_key); + +di_return_t dryice_release_programmed_key(void) +{ + uint32_t dcr; + di_return_t rc = 0; + + if (di_busy_set()) + return DI_ERR_BUSY; + + if (!di->key_programmed) { + rc = DI_ERR_UNSET; + goto err; + } + dcr = di_read(DCR); + if (dcr & DCR_PKWHL) { + rc = DI_ERR_HLOCK; + goto err; + } + if (dcr & DCR_PKWSL) { + rc = DI_ERR_SLOCK; + goto err; + } + di->key_programmed = 0; + +err: + di_busy_clear(); + return rc; +} +EXTERN_SYMBOL(dryice_release_programmed_key); + +di_return_t dryice_set_random_key(int flags) +{ + uint32_t dcr; + di_return_t rc = 0; + + if (di_busy_set()) + return DI_ERR_BUSY; + + if (di_state() == DI_STATE_FAILURE) { + rc = DI_ERR_STATE; + goto err; + } + dcr = di_read(DCR); + if (dcr & DCR_RKHL) { + rc = DI_ERR_HLOCK; + goto err; + } + if (dcr & DCR_RKSL) { + rc = DI_ERR_SLOCK; + goto err; + } + todo_init((flags & DI_FUNC_FLAG_ASYNC) != 0); + + /* clear Random Key Error bit, if set */ + if (di_read(DSR) & DSR_RKE) + todo_write_val(DSR_RKE, DCR); + + /* load random key */ + todo_write_val(DKCR_LRK, DKCR); + + /* wait for RKV (valid) or RKE (error) */ + todo_wait_rkg(); + + if (flags & DI_FUNC_LOCK_FLAGS) { + dcr = di_read(DCR); + if (flags & DI_FUNC_FLAG_WRITE_LOCK) { + if (flags & DI_FUNC_FLAG_HARD_LOCK) + dcr |= DCR_RKHL; + else + dcr |= DCR_RKSL; + } + todo_write_val(dcr, DCR); + } + todo_start(); + + if (flags & DI_FUNC_FLAG_ASYNC) + return 0; + + rc = todo_wait_done(); +err: + di_busy_clear(); + return rc; +} +EXTERN_SYMBOL(dryice_set_random_key); + +di_return_t dryice_select_key(di_key_t key, int flags) +{ + uint32_t dcr, dksr; + di_return_t rc = 0; + + if (di_busy_set()) + return DI_ERR_BUSY; + + switch (key) { + case DI_KEY_FK: + dksr = DKSR_IIM_KEY; + break; + case DI_KEY_PK: + dksr = DKSR_PROG_KEY; + break; + case DI_KEY_RK: + dksr = DKSR_RAND_KEY; + break; + case DI_KEY_FPK: + dksr = DKSR_PROG_XOR_IIM_KEY; + break; + case DI_KEY_FRK: + dksr = DKSR_RAND_XOR_IIM_KEY; + break; + default: + rc = DI_ERR_INVAL; + goto err; + } + if (di->key_selected) { + rc = DI_ERR_INUSE; + goto err; + } + if (di_state() != DI_STATE_VALID) { + rc = DI_ERR_STATE; + goto err; + } + dcr = di_read(DCR); + if (dcr & DCR_KSHL) { + rc = DI_ERR_HLOCK; + goto err; + } + if (dcr & DCR_KSSL) { + rc = DI_ERR_SLOCK; + goto err; + } + todo_init((flags & DI_FUNC_FLAG_ASYNC) != 0); + + /* select key */ + todo_write_val(dksr, DKSR); + + todo_assign(di->key_selected, 1); + + if (flags & DI_FUNC_LOCK_FLAGS) { + dcr = di_read(DCR); + if (flags & DI_FUNC_FLAG_WRITE_LOCK) { + if (flags & DI_FUNC_FLAG_HARD_LOCK) + dcr |= DCR_KSHL; + else + dcr |= DCR_KSSL; + } + todo_write_val(dcr, DCR); + } + todo_start(); + + if (flags & DI_FUNC_FLAG_ASYNC) + return 0; + + rc = todo_wait_done(); +err: + di_busy_clear(); + return rc; +} +EXTERN_SYMBOL(dryice_select_key); + +di_return_t dryice_check_key(di_key_t *key) +{ + uint32_t dksr; + di_return_t rc = 0; + + if (di_busy_set()) + return DI_ERR_BUSY; + + if (key == NULL) { + rc = DI_ERR_INVAL; + goto err; + } + + dksr = di_read(DKSR); + + if (di_state() != DI_STATE_VALID) { + dksr = DKSR_IIM_KEY; + rc = DI_ERR_STATE; + } else if (dksr == DI_KEY_RK || dksr == DI_KEY_FRK) { + if (!(di_read(DSR) & DSR_RKV)) { + dksr = DKSR_IIM_KEY; + rc = DI_ERR_UNSET; + } + } + switch (dksr) { + case DKSR_IIM_KEY: + *key = DI_KEY_FK; + break; + case DKSR_PROG_KEY: + *key = DI_KEY_PK; + break; + case DKSR_RAND_KEY: + *key = DI_KEY_RK; + break; + case DKSR_PROG_XOR_IIM_KEY: + *key = DI_KEY_FPK; + break; + case DKSR_RAND_XOR_IIM_KEY: + *key = DI_KEY_FRK; + break; + } +err: + di_busy_clear(); + return rc; +} +EXTERN_SYMBOL(dryice_check_key); + +di_return_t dryice_release_key_selection(void) +{ + uint32_t dcr; + di_return_t rc = 0; + + if (di_busy_set()) + return DI_ERR_BUSY; + + if (!di->key_selected) { + rc = DI_ERR_UNSET; + goto err; + } + dcr = di_read(DCR); + if (dcr & DCR_KSHL) { + rc = DI_ERR_HLOCK; + goto err; + } + if (dcr & DCR_KSSL) { + rc = DI_ERR_SLOCK; + goto err; + } + di->key_selected = 0; + +err: + di_busy_clear(); + return rc; +} +EXTERN_SYMBOL(dryice_release_key_selection); + +di_return_t dryice_get_tamper_event(uint32_t *events, uint32_t *timestamp, + int flags) +{ + di_return_t rc = 0; + + if (di_busy_set()) + return DI_ERR_BUSY; + + if (di_state() == DI_STATE_VALID) { + rc = DI_ERR_STATE; + goto err; + } + if (events == NULL) { + rc = DI_ERR_INVAL; + goto err; + } + *events = di_read(DSR) & DSR_TAMPER_BITS; + if (timestamp) { + if (di_state() == DI_STATE_NON_VALID) + *timestamp = di_read(DTCMR); + else + *timestamp = 0; + } +err: + di_busy_clear(); + return rc; +} +EXTERN_SYMBOL(dryice_get_tamper_event); + +di_return_t dryice_register_callback(void (*func)(di_return_t, + unsigned long cookie), + unsigned long cookie) +{ + di_return_t rc = 0; + + if (di_busy_set()) + return DI_ERR_BUSY; + + di->cb_func = func; + di->cb_cookie = cookie; + + di_busy_clear(); + return rc; +} +EXTERN_SYMBOL(dryice_register_callback); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("DryIce"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/security/dryice.h linux-2.6.26-lab126/drivers/mxc/security/dryice.h --- linux-2.6.26/drivers/mxc/security/dryice.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/dryice.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,287 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +#ifndef __DRYICE_H__ +#define __DRYICE_H__ + + +/*! + * @file dryice.h + * @brief Definition of DryIce API. + */ + +/*! @page dryice_api DryIce API + * + * Definition of the DryIce API. + * + * The DryIce API implements a software interface to the DryIce hardware + * block. Methods are provided to store, retrieve, generate, and manage + * cryptographic keys and to monitor security tamper events. + * + * See @ref dryice_api for the DryIce API. + */ + +/*! + * This defines the SCC key length (in bits) + */ +#define SCC_KEY_LEN 168 + +/*! + * This defines the maximum key length (in bits) + */ +#define MAX_KEY_LEN 256 +#define MAX_KEY_BYTES ((MAX_KEY_LEN) / 8) +#define MAX_KEY_WORDS ((MAX_KEY_LEN) / 32) + +/*! + * @name DryIce Function Flags + */ +/*@{*/ +#define DI_FUNC_FLAG_ASYNC 0x01 /*!< do not block */ +#define DI_FUNC_FLAG_READ_LOCK 0x02 /*!< set read lock for this resource */ +#define DI_FUNC_FLAG_WRITE_LOCK 0x04 /*!< set write lock for resource */ +#define DI_FUNC_FLAG_HARD_LOCK 0x08 /*!< locks will be hard (default soft) */ +#define DI_FUNC_FLAG_WORD_KEY 0x10 /*!< key provided as 32-bit words */ +/*@}*/ + +/*! + * @name DryIce Tamper Events + */ +/*@{*/ +#define DI_TAMPER_EVENT_WTD (1 << 23) /*!< wire-mesh tampering det */ +#define DI_TAMPER_EVENT_ETBD (1 << 22) /*!< ext tampering det: input B */ +#define DI_TAMPER_EVENT_ETAD (1 << 21) /*!< ext tampering det: input A */ +#define DI_TAMPER_EVENT_EBD (1 << 20) /*!< external boot detected */ +#define DI_TAMPER_EVENT_SAD (1 << 19) /*!< security alarm detected */ +#define DI_TAMPER_EVENT_TTD (1 << 18) /*!< temperature tampering det */ +#define DI_TAMPER_EVENT_CTD (1 << 17) /*!< clock tampering det */ +#define DI_TAMPER_EVENT_VTD (1 << 16) /*!< voltage tampering det */ +#define DI_TAMPER_EVENT_MCO (1 << 3) /*!< monotonic counter overflow */ +#define DI_TAMPER_EVENT_TCO (1 << 2) /*!< time counter overflow */ +/*@}*/ + +/*! + * DryIce Key Sources + */ +typedef enum di_key { + DI_KEY_FK, /*!< the fused (IIM) key */ + DI_KEY_PK, /*!< the programmed key */ + DI_KEY_RK, /*!< the random key */ + DI_KEY_FPK, /*!< the programmed key XORed with the fused key */ + DI_KEY_FRK, /*!< the random key XORed with the fused key */ +} di_key_t; + +/*! + * DryIce Error Codes + */ +typedef enum dryice_return { + DI_SUCCESS = 0, /*!< operation was successful */ + DI_ERR_BUSY, /*!< device or resource busy */ + DI_ERR_STATE, /*!< dryice is in incompatible state */ + DI_ERR_INUSE, /*!< resource is already in use */ + DI_ERR_UNSET, /*!< resource has not been initialized */ + DI_ERR_WRITE, /*!< error occurred during register write */ + DI_ERR_INVAL, /*!< invalid argument */ + DI_ERR_FAIL, /*!< operation failed */ + DI_ERR_HLOCK, /*!< resource is hard locked */ + DI_ERR_SLOCK, /*!< resource is soft locked */ + DI_ERR_NOMEM, /*!< out of memory */ +} di_return_t; + +/*! + * These functions define the DryIce API. + */ + +/*! + * Write a given key to the Programmed Key registers in DryIce, and + * optionally lock the Programmed Key against either reading or further + * writing. The value is held until a call to the release_programmed_key + * interface is made, or until the appropriate HW reset if the write-lock + * flags are used. Unused key bits will be zeroed. + * + * @param[in] key_data A pointer to the key data to be programmed, with + * the most significant byte or word first. This + * will be interpreted as a byte pointer unless the + * WORD_KEY flag is set, in which case it will be + * treated as a word pointer and the key data will be + * read a word at a time, starting with the MSW. + * When called asynchronously, the data pointed to by + * key_data must persist until the operation completes. + * + * @param[in] key_bits The number of bits in the key to be stored. + * This must be a multiple of 8 and within the + * range of 0 and MAX_KEY_LEN. + * + * @param[in] flags This is a bit-wise OR of the flags to be passed + * to the function. Flags can include: + * ASYNC, READ_LOCK, WRITE_LOCK, HARD_LOCK, and + * WORD_KEY. + * + * @return Returns SUCCESS (0), BUSY if DryIce is busy, INVAL + * on invalid arguments, INUSE if key has already been + * programmed, STATE if DryIce is in the wrong state, + * HLOCK or SLOCK if the key registers are locked for + * writing, and WRITE if a write error occurs + * (See #di_return_t). + */ +extern di_return_t dryice_set_programmed_key(const void *key_data, int key_bits, + int flags); + +/*! + * Read the Programmed Key registers and write the contents into a buffer. + * + * @param[out] key_data A byte pointer to where the key data will be written, + * with the most significant byte being written first. + * + * @param[in] key_bits The number of bits of the key to be retrieved. + * This must be a multiple of 8 and within the + * range of 0 and MAX_KEY_LEN. + * + * @return Returns SUCCESS (0), BUSY if DryIce is busy, INVAL + * on invalid arguments, UNSET if key has not been + * programmed, STATE if DryIce is in the wrong state, + * and HLOCK or SLOCK if the key registers are locked for + * reading (See #di_return_t). + */ +extern di_return_t dryice_get_programmed_key(uint8_t *key_data, int key_bits); + +/*! + * Allow the set_programmed_key interface to be used to write a new + * Programmed Key to DryIce. Note that this interface does not overwrite + * the value in the Programmed Key registers. + * + * @return Returns SUCCESS (0), BUSY if DryIce is busy, + * UNSET if the key has not been previously set, and + * HLOCK or SLOCK if the key registers are locked for + * writing (See #di_return_t). + */ +extern di_return_t dryice_release_programmed_key(void); + +/*! + * Generate and load a new Random Key in DryIce, and optionally lock the + * Random Key against further change. + * + * @param[in] flags This is a bit-wise OR of the flags to be passed + * to the function. Flags can include: + * ASYNC, READ_LOCK, WRITE_LOCK, and HARD_LOCK. + * + * @return Returns SUCCESS (0), BUSY if DryIce is busy, STATE + * if DryIce is in the wrong state, FAIL if the key gen + * failed, HLOCK or SLOCK if the key registers are + * locked, and WRITE if a write error occurs + * (See #di_return_t). + */ +extern di_return_t dryice_set_random_key(int flags); + +/*! + * Set the key selection in DryIce to determine the key used by an + * encryption module such as SCC. The selection is held until a call to the + * Release Selected Key interface is made, or until the appropriate HW + * reset if the LOCK flags are used. + * + * @param[in] key The source of the key to be used by the SCC + * (See #di_key_t). + * + * @param[in] flags This is a bit-wise OR of the flags to be passed + * to the function. Flags can include: + * ASYNC, WRITE_LOCK, and HARD_LOCK. + * + * @return Returns SUCCESS (0), BUSY if DryIce is busy, INVAL + * on invalid arguments, INUSE if a selection has already + * been made, STATE if DryIce is in the wrong state, + * HLOCK or SLOCK if the selection register is locked, + * and WRITE if a write error occurs + */ +extern di_return_t dryice_select_key(di_key_t key, int flags); + +/*! + * Check which key will be used in the SCC. This is needed because in some + * DryIce states, the Key Select Register is overridden by a default value + * (the Fused/IIM key). + * + * @param[out] key The source of the key that is currently selected for + * use by the SCC. This may be different from the key + * specified by the dryice_select_key function + * (See #di_key_t). This value is set even if an error + * code (except for BUSY) is returned. + * + * @return Returns SUCCESS (0), BUSY if DryIce is busy, STATE if + * DryIce is in the wrong state, INVAL on invalid + * arguments, or UNSET if no key has been selected + * (See #di_return_t). + */ +extern di_return_t dryice_check_key(di_key_t *key); + +/*! + * Allow the dryice_select_key interface to be used to set a new key selection + * in DryIce. Note that this interface does not overwrite the value in DryIce. + * + * @return Returns SUCCESS (0), BUSY if DryIce is busy, UNSET + * if the no selection has been made previously, and + * HLOCK or SLOCK if the selection register is locked + * (See #di_return_t). + */ +extern di_return_t dryice_release_key_selection(void); + +/*! + * Returns tamper-detection status bits. Also an optional timestamp when + * DryIce is in the Non-valid state. If DryIce is not in Failure or Non-valid + * state, this interface returns a failure code. + * + * @param[out] events This is a bit-wise OR of the following events: + * WTD (Wire Mesh), ETBD (External Tamper B), + * ETAD (External Tamper A), EBD (External Boot), + * SAD (Security Alarm), TTD (Temperature Tamper), + * CTD (Clock Tamper), VTD (Voltage Tamper), + * MCO (Monolithic Counter Overflow), and + * TCO (Time Counter Overflow). + * + * @param[out] timestamp This is the value of the time counter in seconds + * when the tamper occurred. A timestamp will not be + * returned if a NULL pointer is specified. If DryIce + * is not in the Non-valid state the time cannot be + * read, so a timestamp of 0 will be returned. + * + * @param[in] flags This is a bit-wise OR of the flags to be passed + * to the function. Flags is ignored currently by + * this function. + * + * @return Returns SUCCESS (0), BUSY if DryIce is busy, and + * INVAL on invalid arguments (See #di_return_t). + */ +extern di_return_t +dryice_get_tamper_event(uint32_t *events, uint32_t *timestamp, int flags); + +/*! + * Provide a callback function to be called upon the completion of DryIce calls + * that are executed asynchronously. + * + * @param[in] func This is a pointer to a function of type: + * void callback(di_return_t rc, unsigned long cookie) + * The return code of the async function is passed + * back in "rc" along with the cookie provided when + * registering the callback. + * + * @param[in] cookie This is an "opaque" cookie of type unsigned long that + * is returned on subsequent callbacks. It may be of any + * value. + * + * @return Returns SUCCESS (0), or BUSY if DryIce is busy + * (See #di_return_t). + */ +extern di_return_t dryice_register_callback(void (*func)(di_return_t rc, + unsigned long cookie), + unsigned long cookie); + +#endif /* __DRYICE_H__ */ diff -urN linux-2.6.26/drivers/mxc/security/mxc_scc.c linux-2.6.26-lab126/drivers/mxc/security/mxc_scc.c --- linux-2.6.26/drivers/mxc/security/mxc_scc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/mxc_scc.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,2386 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_scc.c + * + * This is the driver code for the Security Controller (SCC). It has no device + * driver interface, so no user programs may access it. Its interaction with + * the Linux kernel is from calls to #scc_init() when the driver is loaded, and + * #scc_cleanup() should the driver be unloaded. The driver uses locking and + * (task-sleep/task-wakeup) functions of the kernel. It also registers itself + * to handle the interrupt line(s) from the SCC. + * + * Other drivers in the kernel may use the remaining API functions to get at + * the services of the SCC. The main service provided is the Secure Memory, + * which allows encoding and decoding of secrets with a per-chip secret key. + * + * The SCC is single-threaded, and so is this module. When the scc_crypt() + * routine is called, it will lock out other accesses to the function. If + * another task is already in the module, the subsequent caller will spin on a + * lock waiting for the other access to finish. + * + * Note that long crypto operations could cause a task to spin for a while, + * preventing other kernel work (other than interrupt processing) to get done. + * + * The external (kernel module) interface is through the following functions: + * @li scc_get_configuration() + * @li scc_crypt() + * @li scc_zeroize_memories() + * @li scc_monitor_security_failure() + * @li scc_stop_monitoring_security_failure() + * @li scc_set_sw_alarm() + * @li scc_read_register() + * @li scc_write_register() + * + * All other functions are internal to the driver. + * + * @ingroup MXCSCC +*/ +#include "sahara2/include/fsl_platform.h" +#include "sahara2/include/portable_os.h" +#include "mxc_scc_internals.h" + +#include + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) + +#include +#include +#include + +#else +#include +#include +#include + +#endif + +/*! + * This is the set of errors which signal that access to the SCM RAM has + * failed or will fail. + */ +#define SCM_ACCESS_ERRORS \ + (SCM_ERR_USER_ACCESS | SCM_ERR_ILLEGAL_ADDRESS | \ + SCM_ERR_ILLEGAL_MASTER | SCM_ERR_CACHEABLE_ACCESS | \ + SCM_ERR_UNALIGNED_ACCESS | SCM_ERR_BYTE_ACCESS | \ + SCM_ERR_INTERNAL_ERROR | SCM_ERR_SMN_BLOCKING_ACCESS | \ + SCM_ERR_CIPHERING | SCM_ERR_ZEROIZING | SCM_ERR_BUSY) +/****************************************************************************** + * + * Global / Static Variables + * + *****************************************************************************/ + +/*! + * This is type void* so that a) it cannot directly be dereferenced, + * and b) pointer arithmetic on it will function in a 'normal way' for + * the offsets in scc_defines.h + * + * scc_base is the location in the iomap where the SCC's registers + * (and memory) start. + * + * The referenced data is declared volatile so that the compiler will + * not make any assumptions about the value of registers in the SCC, + * and thus will always reload the register into CPU memory before + * using it (i.e. wherever it is referenced in the driver). + * + * This value should only be referenced by the #SCC_READ_REGISTER and + * #SCC_WRITE_REGISTER macros and their ilk. All dereferences must be + * 32 bits wide. + */ +static volatile void *scc_base; + +/*! Array to hold function pointers registered by + #scc_monitor_security_failure() and processed by + #scc_perform_callbacks() */ +static void (*scc_callbacks[SCC_CALLBACK_SIZE]) (void); + +/*! Structure returned by #scc_get_configuration() */ +static scc_config_t scc_configuration = { + .driver_major_version = SCC_DRIVER_MAJOR_VERSION_1, + .driver_minor_version = SCC_DRIVER_MINOR_VERSION_8, + .scm_version = -1, + .smn_version = -1, + .block_size_bytes = -1, + .black_ram_size_blocks = -1, + .red_ram_size_blocks = -1 +}; + +/*! Key Control Information. Integrity is controlled by use of + #scc_crypto_lock. */ +static struct scc_key_slot scc_key_info[SCC_KEY_SLOTS]; + +/*! Internal flag to know whether SCC is in Failed state (and thus many + * registers are unavailable). Once it goes failed, it never leaves it. */ +static volatile enum scc_status scc_availability = SCC_STATUS_INITIAL; + +/*! Flag to say whether interrupt handler has been registered for + * SMN interrupt */ +static int smn_irq_set = 0; + +/*! Flag to say whether interrupt handler has been registered for + * SCM interrupt */ +static int scm_irq_set = 0; + +/*! This lock protects the #scc_callbacks list as well as the @c + * callbacks_performed flag in #scc_perform_callbacks. Since the data this + * protects may be read or written from either interrupt or base level, all + * operations should use the irqsave/irqrestore or similar to make sure that + * interrupts are inhibited when locking from base level. + */ +static spinlock_t scc_callbacks_lock = SPIN_LOCK_UNLOCKED; + +/*! + * Ownership of this lock prevents conflicts on the crypto operation in the SCC + * and the integrity of the #scc_key_info. + */ +static spinlock_t scc_crypto_lock = SPIN_LOCK_UNLOCKED; + +/*! Calculated once for quick reference to size of the unreserved space in one + * RAM in SCM. + */ +static uint32_t scc_memory_size_bytes; + +/*! Calculated once for quick reference to size of SCM address space */ +static uint32_t scm_highest_memory_address; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)) +#ifndef SCC_CLOCK_NOT_GATED +/*! Pointer to SCC's clock information. Initialized during scc_init(). */ +static struct clk *scc_clk = NULL; +#endif +#endif + +/*! The lookup table for an 8-bit value. Calculated once + * by #scc_init_ccitt_crc(). + */ +static uint16_t scc_crc_lookup_table[256]; + +/*! Fixed padding for appending to plaintext to fill out a block */ +static uint8_t scc_block_padding[8] = + { SCC_DRIVER_PAD_CHAR, 0, 0, 0, 0, 0, 0, 0 }; + +/****************************************************************************** + * + * Function Implementations - Externally Accessible + * + *****************************************************************************/ + +/*****************************************************************************/ +/* fn scc_init() */ +/*****************************************************************************/ +/*! + * Initialize the driver at boot time or module load time. + * + * Register with the kernel as the interrupt handler for the SCC interrupt + * line(s). + * + * Map the SCC's register space into the driver's memory space. + * + * Query the SCC for its configuration and status. Save the configuration in + * #scc_configuration and save the status in #scc_availability. Called by the + * kernel. + * + * Do any locking/wait queue initialization which may be necessary. + * + * The availability fuse may be checked, depending on platform. + */ +static int scc_init(void) +{ + uint32_t smn_status; + int i; + int return_value = -EIO; /* assume error */ + if (scc_availability == SCC_STATUS_INITIAL) { + + /* Set this until we get an initial reading */ + scc_availability = SCC_STATUS_CHECKING; + + /* Initialize the constant for the CRC function */ + scc_init_ccitt_crc(); + + /* initialize the callback table */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + scc_callbacks[i] = 0; + } + + /* Initialize key slots */ + for (i = 0; i < SCC_KEY_SLOTS; i++) { + scc_key_info[i].offset = i * SCC_KEY_SLOT_SIZE; + scc_key_info[i].status = 0; /* unassigned */ + } + + /* Enable the SCC clock on platforms where it is gated */ +#ifndef SCC_CLOCK_NOT_GATED + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) + mxc_clks_enable(SCC_CLK); +#else + + scc_clk = clk_get(NULL, "scc_clk"); + if (scc_clk != ERR_PTR(ENOENT)) { + clk_enable(scc_clk); + } +#endif /* LINUX_VERSION_CODE */ + +#endif /* SCC_CLOCK_NOT_GATED */ + /* See whether there is an SCC available */ + if (0 && !SCC_ENABLED()) { + os_printk(KERN_ERR + "SCC: Fuse for SCC is set to disabled. Exiting.\n"); + } else { + /* Map the SCC (SCM and SMN) memory on the internal bus into + kernel address space */ + scc_base = (void *)IO_ADDRESS(SCC_BASE); + + /* If that worked, we can try to use the SCC */ + if (scc_base == NULL) { + os_printk(KERN_ERR + "SCC: Register mapping failed. Exiting.\n"); + } else { + /* Get SCM into 'clean' condition w/interrupts cleared & + disabled */ + SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL, + SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT + | + SCM_INTERRUPT_CTRL_MASK_INTERRUPTS); + + /* Clear error status register (any write will do it) */ + SCC_WRITE_REGISTER(SCM_ERROR_STATUS, 0); + + /* + * There is an SCC. Determine its current state. Side effect + * is to populate scc_config and scc_availability + */ + smn_status = scc_grab_config_values(); + + /* Try to set up interrupt handler(s) */ + if (scc_availability == SCC_STATUS_OK) { + if (setup_interrupt_handling() != 0) { + unsigned condition; + /*! + * The error could be only that the SCM interrupt was + * not set up. This interrupt is always masked, so + * that is not an issue. + * + * The SMN's interrupt may be shared on that line, it + * may be separate, or it may not be wired. Do what + * is necessary to check its status. + * + * Although the driver is coded for possibility of not + * having SMN interrupt, the fact that there is one + * means it should be available and used. + */ +#ifdef USE_SMN_INTERRUPT + condition = !smn_irq_set; /* Separate. Check SMN binding */ +#elif !defined(NO_SMN_INTERRUPT) + condition = !scm_irq_set; /* Shared. Check SCM binding */ +#else + condition = FALSE; /* SMN not wired at all. Ignore. */ +#endif + /* setup was not able to set up SMN interrupt */ + scc_availability = + SCC_STATUS_UNIMPLEMENTED; + } /* interrupt handling returned non-zero */ + } /* availability is OK */ + if (scc_availability == SCC_STATUS_OK) { + /* Get SMN into 'clean' condition w/interrupts cleared & + enabled */ + SCC_WRITE_REGISTER(SMN_COMMAND, + SMN_COMMAND_CLEAR_INTERRUPT + | + SMN_COMMAND_ENABLE_INTERRUPT); + } + /* availability is still OK */ + } /* if scc_base != NULL */ + + } /* if SCC_ENABLED() */ + + /* + * If status is SCC_STATUS_UNIMPLEMENTED or is still + * SCC_STATUS_CHECKING, could be leaving here with the driver partially + * initialized. In either case, cleanup (which will mark the SCC as + * UNIMPLEMENTED). + */ + if (scc_availability == SCC_STATUS_CHECKING || + scc_availability == SCC_STATUS_UNIMPLEMENTED) { + scc_cleanup(); + } else { + return_value = 0; /* All is well */ + } + } + /* ! STATUS_INITIAL */ + pr_debug("SCC: Driver Status is %s\n", + (scc_availability == SCC_STATUS_INITIAL) ? "INITIAL" : + (scc_availability == SCC_STATUS_CHECKING) ? "CHECKING" : + (scc_availability == + SCC_STATUS_UNIMPLEMENTED) ? "UNIMPLEMENTED" + : (scc_availability == + SCC_STATUS_OK) ? "OK" : (scc_availability == + SCC_STATUS_FAILED) ? "FAILED" : + "UNKNOWN"); + + return return_value; +} /* scc_init */ + +/*****************************************************************************/ +/* fn scc_cleanup() */ +/*****************************************************************************/ +/*! + * Perform cleanup before driver/module is unloaded by setting the machine + * state close to what it was when the driver was loaded. This function is + * called when the kernel is shutting down or when this driver is being + * unloaded. + * + * A driver like this should probably never be unloaded, especially if there + * are other module relying upon the callback feature for monitoring the SCC + * status. + * + * In any case, cleanup the callback table (by clearing out all of the + * pointers). Deregister the interrupt handler(s). Unmap SCC registers. + * + */ +static void scc_cleanup(void) +{ + int i; + + /* Mark the driver / SCC as unusable. */ + scc_availability = SCC_STATUS_UNIMPLEMENTED; + + /* Clear out callback table */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + scc_callbacks[i] = 0; + } + + /* If SCC has been mapped in, clean it up and unmap it */ + if (scc_base) { + /* For the SCM, disable interrupts, zeroize RAMs. Interrupt + * status will appear because zeroize will complete. */ + SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL, + SCM_INTERRUPT_CTRL_MASK_INTERRUPTS | + SCM_INTERRUPT_CTRL_ZEROIZE_MEMORY); + + /* For the SMN, clear and disable interrupts */ + SCC_WRITE_REGISTER(SMN_COMMAND, SMN_COMMAND_CLEAR_INTERRUPT); + + /* remove virtual mapping */ + iounmap((void *)scc_base); + } + + /* Now that interrupts cannot occur, disassociate driver from the interrupt + * lines. + */ + + /* Deregister SCM interrupt handler */ + if (scm_irq_set) { + os_deregister_interrupt(INT_SCC_SCM); + } + + /* Deregister SMN interrupt handler */ + if (smn_irq_set) { +#ifdef USE_SMN_INTERRUPT + os_deregister_interrupt(INT_SCC_SMN); +#endif + } + pr_debug("SCC driver cleaned up.\n"); + +} /* scc_cleanup */ + +/*****************************************************************************/ +/* fn scc_get_configuration() */ +/*****************************************************************************/ +scc_config_t *scc_get_configuration(void) +{ + /* + * If some other driver calls scc before the kernel does, make sure that + * this driver's initialization is performed. + */ + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /*! + * If there is no SCC, yet the driver exists, the value -1 will be in + * the #scc_config_t fields for other than the driver versions. + */ + return &scc_configuration; +} /* scc_get_configuration */ + +/*****************************************************************************/ +/* fn scc_zeroize_memories() */ +/*****************************************************************************/ +scc_return_t scc_zeroize_memories(void) +{ + scc_return_t return_status = SCC_RET_FAIL; + uint32_t status; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + if (scc_availability == SCC_STATUS_OK) { + unsigned long irq_flags; /* for IRQ save/restore */ + + /* Lock access to crypto memory of the SCC */ + spin_lock_irqsave(&scc_crypto_lock, irq_flags); + + /* Start the Zeroize by setting a bit in the SCM_INTERRUPT_CTRL + * register */ + SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL, + SCM_INTERRUPT_CTRL_MASK_INTERRUPTS + | SCM_INTERRUPT_CTRL_ZEROIZE_MEMORY); + + scc_wait_completion(); + + /* Get any error info */ + status = SCC_READ_REGISTER(SCM_ERROR_STATUS); + + /* unlock the SCC */ + spin_unlock_irqrestore(&scc_crypto_lock, irq_flags); + + if (!(status & SCM_ERR_ZEROIZE_FAILED)) { + return_status = SCC_RET_OK; + } else { + pr_debug + ("SCC: Zeroize failed. SCM Error Status is 0x%08x\n", + status); + } + + /* Clear out any status. */ + SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL, + SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT + | SCM_INTERRUPT_CTRL_MASK_INTERRUPTS); + + /* and any error status */ + SCC_WRITE_REGISTER(SCM_ERROR_STATUS, 0); + } + + return return_status; +} /* scc_zeroize_memories */ + +/*****************************************************************************/ +/* fn scc_crypt() */ +/*****************************************************************************/ +scc_return_t +scc_crypt(unsigned long count_in_bytes, const uint8_t * data_in, + const uint8_t * init_vector, + scc_enc_dec_t direction, scc_crypto_mode_t crypto_mode, + scc_verify_t check_mode, uint8_t * data_out, + unsigned long *count_out_bytes) + +{ + scc_return_t return_code = SCC_RET_FAIL; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + (void)scc_update_state(); /* in case no interrupt line from SMN */ + + /* make initial error checks */ + if (scc_availability != SCC_STATUS_OK + || count_in_bytes == 0 + || data_in == 0 + || data_out == 0 + || (crypto_mode != SCC_CBC_MODE && crypto_mode != SCC_ECB_MODE) + || (crypto_mode == SCC_CBC_MODE && init_vector == NULL) + || (direction != SCC_ENCRYPT && direction != SCC_DECRYPT) + || (check_mode == SCC_VERIFY_MODE_NONE && + count_in_bytes % SCC_BLOCK_SIZE_BYTES() != 0) + || (direction == SCC_DECRYPT && + count_in_bytes % SCC_BLOCK_SIZE_BYTES() != 0) + || (check_mode != SCC_VERIFY_MODE_NONE && + check_mode != SCC_VERIFY_MODE_CCITT_CRC)) { + pr_debug + ("SCC: scc_crypt() count_in_bytes_ok = %d; data_in_ok = %d;" + " data_out_ok = %d; iv_ok = %d\n", !(count_in_bytes == 0), + !(data_in == 0), !(data_out == 0), + !(crypto_mode == SCC_CBC_MODE && init_vector == NULL)); + pr_debug("SCC: scc_crypt() mode_ok=%d; direction_ok=%d;" + " size_ok=%d, check_mode_ok=%d\n", + !(crypto_mode != SCC_CBC_MODE + && crypto_mode != SCC_ECB_MODE), + !(direction != SCC_ENCRYPT + && direction != SCC_DECRYPT), + !((check_mode == SCC_VERIFY_MODE_NONE + && count_in_bytes % SCC_BLOCK_SIZE_BYTES() != 0) + || (direction == SCC_DECRYPT + && count_in_bytes % SCC_BLOCK_SIZE_BYTES() != + 0)), !(check_mode != SCC_VERIFY_MODE_NONE + && check_mode != + SCC_VERIFY_MODE_CCITT_CRC)); + pr_debug("SCC: scc_crypt() detected bad argument\n"); + } else { + /* Start settings for write to SCM_CONTROL register */ + uint32_t scc_control = SCM_CONTROL_START_CIPHER; + unsigned long irq_flags; /* for IRQ save/restore */ + + /* Lock access to crypto memory of the SCC */ + spin_lock_irqsave(&scc_crypto_lock, irq_flags); + + /* Special needs for CBC Mode */ + if (crypto_mode == SCC_CBC_MODE) { + scc_control |= SCM_CBC_MODE; /* change default of ECB */ + /* Put in Initial Context. Vector registers are contiguous */ + copy_to_scc(init_vector, SCM_INIT_VECTOR_0, + SCC_BLOCK_SIZE_BYTES(), NULL); + } + + /* Fill the RED_START register */ + SCC_WRITE_REGISTER(SCM_RED_START, + SCM_NON_RESERVED_OFFSET / + SCC_BLOCK_SIZE_BYTES()); + + /* Fill the BLACK_START register */ + SCC_WRITE_REGISTER(SCM_BLACK_START, + SCM_NON_RESERVED_OFFSET / + SCC_BLOCK_SIZE_BYTES()); + + if (direction == SCC_ENCRYPT) { + /* Check for sufficient space in data_out */ + if (check_mode == SCC_VERIFY_MODE_NONE) { + if (*count_out_bytes < count_in_bytes) { + return_code = + SCC_RET_INSUFFICIENT_SPACE; + } + } else { /* SCC_VERIFY_MODE_CCITT_CRC */ + /* Calculate extra bytes needed for crc (2) and block + padding */ + int padding_needed = + CRC_SIZE_BYTES + SCC_BLOCK_SIZE_BYTES() - + ((count_in_bytes + CRC_SIZE_BYTES) + % SCC_BLOCK_SIZE_BYTES()); + + /* Verify space is available */ + if (*count_out_bytes < + count_in_bytes + padding_needed) { + return_code = + SCC_RET_INSUFFICIENT_SPACE; + } + } + /* If did not detect space error, do the encryption */ + if (return_code != SCC_RET_INSUFFICIENT_SPACE) { + return_code = + scc_encrypt(count_in_bytes, data_in, + scc_control, data_out, + check_mode == + SCC_VERIFY_MODE_CCITT_CRC, + count_out_bytes); + } + + } + /* direction == SCC_ENCRYPT */ + else { /* SCC_DECRYPT */ + /* Check for sufficient space in data_out */ + if (check_mode == SCC_VERIFY_MODE_NONE) { + if (*count_out_bytes < count_in_bytes) { + return_code = + SCC_RET_INSUFFICIENT_SPACE; + } + } else { /* SCC_VERIFY_MODE_CCITT_CRC */ + /* Do initial check. Assume last block (of padding) and CRC + * will get stripped. After decipher is done and padding is + * removed, will know exact value. + */ + int possible_size = + (int)count_in_bytes - CRC_SIZE_BYTES - + SCC_BLOCK_SIZE_BYTES(); + if ((int)*count_out_bytes < possible_size) { + pr_debug + ("SCC: insufficient decrypt space %ld/%d.\n", + *count_out_bytes, possible_size); + return_code = + SCC_RET_INSUFFICIENT_SPACE; + } + } + + /* If did not detect space error, do the decryption */ + if (return_code != SCC_RET_INSUFFICIENT_SPACE) { + return_code = + scc_decrypt(count_in_bytes, data_in, + scc_control, data_out, + check_mode == + SCC_VERIFY_MODE_CCITT_CRC, + count_out_bytes); + } + + } /* SCC_DECRYPT */ + + /* unlock the SCC */ + spin_unlock_irqrestore(&scc_crypto_lock, irq_flags); + + } /* else no initial error */ + + return return_code; +} /* scc_crypt */ + +/*****************************************************************************/ +/* fn scc_set_sw_alarm() */ +/*****************************************************************************/ +void scc_set_sw_alarm(void) +{ + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* Update scc_availability based on current SMN status. This might + * perform callbacks. + */ + (void)scc_update_state(); + + /* if everything is OK, make it fail */ + if (scc_availability == SCC_STATUS_OK) { + + /* sound the alarm (and disable SMN interrupts */ + SCC_WRITE_REGISTER(SMN_COMMAND, SMN_COMMAND_SET_SOFTWARE_ALARM); + + scc_availability = SCC_STATUS_FAILED; /* Remember what we've done */ + + /* In case SMN interrupt is not available, tell the world */ + scc_perform_callbacks(); + } + + return; +} /* scc_set_sw_alarm */ + +/*****************************************************************************/ +/* fn scc_monitor_security_failure() */ +/*****************************************************************************/ +scc_return_t scc_monitor_security_failure(void callback_func(void)) +{ + int i; + unsigned long irq_flags; /* for IRQ save/restore */ + scc_return_t return_status = SCC_RET_TOO_MANY_FUNCTIONS; + int function_stored = FALSE; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* Acquire lock of callbacks table. Could be spin_lock_irq() if this + * routine were just called from base (not interrupt) level + */ + spin_lock_irqsave(&scc_callbacks_lock, irq_flags); + + /* Search through table looking for empty slot */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + if (scc_callbacks[i] == callback_func) { + if (function_stored) { + /* Saved duplicate earlier. Clear this later one. */ + scc_callbacks[i] = NULL; + } + /* Exactly one copy is now stored */ + return_status = SCC_RET_OK; + break; + } else if (scc_callbacks[i] == NULL && !function_stored) { + /* Found open slot. Save it and remember */ + scc_callbacks[i] = callback_func; + return_status = SCC_RET_OK; + function_stored = TRUE; + } + } + + /* Free the lock */ + spin_unlock_irqrestore(&scc_callbacks_lock, irq_flags); + + return return_status; +} /* scc_monitor_security_failure */ + +/*****************************************************************************/ +/* fn scc_stop_monitoring_security_failure() */ +/*****************************************************************************/ +void scc_stop_monitoring_security_failure(void callback_func(void)) +{ + unsigned long irq_flags; /* for IRQ save/restore */ + int i; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* Acquire lock of callbacks table. Could be spin_lock_irq() if this + * routine were just called from base (not interrupt) level + */ + spin_lock_irqsave(&scc_callbacks_lock, irq_flags); + + /* Search every entry of the table for this function */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + if (scc_callbacks[i] == callback_func) { + scc_callbacks[i] = NULL; /* found instance - clear it out */ + break; + } + } + + /* Free the lock */ + spin_unlock_irqrestore(&scc_callbacks_lock, irq_flags); + + return; +} /* scc_stop_monitoring_security_failure */ + +/*****************************************************************************/ +/* fn scc_read_register() */ +/*****************************************************************************/ +scc_return_t scc_read_register(int register_offset, uint32_t * value) +{ + scc_return_t return_status = SCC_RET_FAIL; + uint32_t smn_status; + uint32_t scm_status; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* First layer of protection -- completely unaccessible SCC */ + if (scc_availability != SCC_STATUS_UNIMPLEMENTED) { + + /* Second layer -- that offset is valid */ + if (register_offset != SMN_BITBANK_DECREMENT && /* write only! */ + check_register_offset(register_offset) == SCC_RET_OK) { + + /* Get current status / update local state */ + smn_status = scc_update_state(); + scm_status = SCC_READ_REGISTER(SCM_STATUS); + + /* + * Third layer - verify that the register being requested is + * available in the current state of the SCC. + */ + if ((return_status = + check_register_accessible(register_offset, + smn_status, + scm_status)) == + SCC_RET_OK) { + *value = SCC_READ_REGISTER(register_offset); + } + } + } + + return return_status; +} /* scc_read_register */ + +/*****************************************************************************/ +/* fn scc_write_register() */ +/*****************************************************************************/ +scc_return_t scc_write_register(int register_offset, uint32_t value) +{ + scc_return_t return_status = SCC_RET_FAIL; + uint32_t smn_status; + uint32_t scm_status; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* First layer of protection -- completely unaccessible SCC */ + if (scc_availability != SCC_STATUS_UNIMPLEMENTED) { + + /* Second layer -- that offset is valid */ + if (!(register_offset == SCM_STATUS || /* These registers are */ + register_offset == SCM_CONFIGURATION || /* Read Only */ + register_offset == SMN_BIT_COUNT || + register_offset == SMN_TIMER) && + check_register_offset(register_offset) == SCC_RET_OK) { + + /* Get current status / update local state */ + smn_status = scc_update_state(); + scm_status = SCC_READ_REGISTER(SCM_STATUS); + + /* + * Third layer - verify that the register being requested is + * available in the current state of the SCC. + */ + if (check_register_accessible + (register_offset, smn_status, scm_status) == 0) { + SCC_WRITE_REGISTER(register_offset, value); + return_status = SCC_RET_OK; + } + } + } + + return return_status; +} /* scc_write_register() */ + +/****************************************************************************** + * + * Function Implementations - Internal + * + *****************************************************************************/ + +/*****************************************************************************/ +/* fn scc_irq() */ +/*****************************************************************************/ +/*! + * This is the interrupt handler for the SCC. + * + * This function checks the SMN Status register to see whether it + * generated the interrupt, then it checks the SCM Status register to + * see whether it needs attention. + * + * If an SMN Interrupt is active, then the SCC state set to failure, and + * #scc_perform_callbacks() is invoked to notify any interested parties. + * + * The SCM Interrupt should be masked, as this driver uses polling to determine + * when the SCM has completed a crypto or zeroing operation. Therefore, if the + * interrupt is active, the driver will just clear the interrupt and (re)mask. + * + */ +OS_DEV_ISR(scc_irq) +{ + uint32_t smn_status; + uint32_t scm_status; + int handled = 0; /* assume interrupt isn't from SMN */ +#if defined(USE_SMN_INTERRUPT) + int smn_irq = INT_SCC_SMN; /* SMN interrupt is on a line by itself */ +#elif defined (NO_SMN_INTERRUPT) + int smn_irq = -1; /* not wired to CPU at all */ +#else + int smn_irq = INT_SCC_SCM; /* SMN interrupt shares a line with SCM */ +#endif + + /* Update current state... This will perform callbacks... */ + smn_status = scc_update_state(); + + /* SMN is on its own interrupt line. Verify the IRQ was triggered + * before clearing the interrupt and marking it handled. */ + if ((os_dev_get_irq() == smn_irq) && + (smn_status & SMN_STATUS_SMN_STATUS_IRQ)) { + SCC_WRITE_REGISTER(SMN_COMMAND, SMN_COMMAND_CLEAR_INTERRUPT); + handled++; /* tell kernel that interrupt was handled */ + } + + /* Check on the health of the SCM */ + scm_status = SCC_READ_REGISTER(SCM_STATUS); + + /* The driver masks interrupts, so this should never happen. */ + if (os_dev_get_irq() == INT_SCC_SCM) { + /* but if it does, try to prevent it in the future */ + SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL, + SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT + | SCM_INTERRUPT_CTRL_MASK_INTERRUPTS); + handled++; + } + + /* Any non-zero value of handled lets kernel know we got something */ + return IRQ_RETVAL(handled); +} + +/*****************************************************************************/ +/* fn scc_perform_callbacks() */ +/*****************************************************************************/ +/*! Perform callbacks registered by #scc_monitor_security_failure(). + * + * Make sure callbacks only happen once... Since there may be some reason why + * the interrupt isn't generated, this routine could be called from base(task) + * level. + * + * One at a time, go through #scc_callbacks[] and call any non-null pointers. + */ +static void scc_perform_callbacks(void) +{ + static int callbacks_performed = 0; + unsigned long irq_flags; /* for IRQ save/restore */ + int i; + + /* Acquire lock of callbacks table and callbacks_performed flag */ + spin_lock_irqsave(&scc_callbacks_lock, irq_flags); + + if (!callbacks_performed) { + callbacks_performed = 1; + + /* Loop over all of the entries in the table */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + /* If not null, ... */ + if (scc_callbacks[i]) { + scc_callbacks[i] (); /* invoke the callback routine */ + } + } + } + + spin_unlock_irqrestore(&scc_callbacks_lock, irq_flags); + + return; +} + +/*****************************************************************************/ +/* fn copy_to_scc() */ +/*****************************************************************************/ +/*! + * Move data from possibly unaligned source and realign for SCC, possibly + * while calculating CRC. + * + * Multiple calls can be made to this routine (without intervening calls to + * #copy_from_scc(), as long as the sum total of bytes copied is a multiple of + * four (SCC native word size). + * + * @param[in] from Location in memory + * @param[out] to Location in SCC + * @param[in] count_bytes Number of bytes to copy + * @param[in,out] crc Pointer to CRC. Initial value must be + * #CRC_CCITT_START if this is the start of + * message. Output is the resulting (maybe + * partial) CRC. If NULL, no crc is calculated. + * + * @return Zero - success. Non-zero - SCM status bits defining failure. + */ +static uint32_t +copy_to_scc(const uint8_t * from, uint32_t to, unsigned long count_bytes, + uint16_t * crc) +{ + int i; + uint32_t scm_word; + uint16_t current_crc = 0; /* local copy for fast access */ + uint32_t status; + + pr_debug("SCC: copying %ld bytes to 0x%0x.\n", count_bytes, to); + + status = SCC_READ_REGISTER(SCM_ERROR_STATUS) & SCM_ACCESS_ERRORS; + if (status != 0) { + pr_debug + ("SCC copy_to_scc(): Error status detected (before copy):" + " %08x\n", status); + /* clear out errors left behind by somebody else */ + SCC_WRITE_REGISTER(SCM_ERROR_STATUS, status); + } + + if (crc) { + current_crc = *crc; + } + + /* Initialize value being built for SCM. If we are starting 'clean', + * set it to zero. Otherwise pick up partial value which had been saved + * earlier. */ + if (SCC_BYTE_OFFSET(to) == 0) { + scm_word = 0; + } else { + scm_word = SCC_READ_REGISTER(SCC_WORD_PTR(to)); /* recover */ + } + + /* Now build up SCM words and write them out when each is full */ + for (i = 0; i < count_bytes; i++) { + uint8_t byte = *from++; /* value from plaintext */ + +#if defined(__BIG_ENDIAN) || defined(FSL_HAVE_DRYICE) + scm_word = (scm_word << 8) | byte; /* add byte to SCM word */ +#else + scm_word = (byte << 24) | (scm_word >> 8); +#endif + /* now calculate CCITT CRC */ + if (crc) { + CALC_CRC(byte, current_crc); + } + + to++; /* bump location in SCM */ + + /* check for full word */ + if (SCC_BYTE_OFFSET(to) == 0) { + SCC_WRITE_REGISTER((uint32_t) (to - 4), scm_word); /* write it out */ + } + } + + /* If at partial word after previous loop, save it in SCM memory for + next time. */ + if (SCC_BYTE_OFFSET(to) != 0) { + SCC_WRITE_REGISTER(SCC_WORD_PTR(to), scm_word); /* save */ + } + + /* Copy CRC back */ + if (crc) { + *crc = current_crc; + } + + status = SCC_READ_REGISTER(SCM_ERROR_STATUS) & SCM_ACCESS_ERRORS; + if (status != 0) { + pr_debug("SCC copy_to_scc(): Error status detected: %08x\n", + status); + /* Clear any/all bits. */ + SCC_WRITE_REGISTER(SCM_ERROR_STATUS, status); + } + return status; +} + +/*****************************************************************************/ +/* fn copy_from_scc() */ +/*****************************************************************************/ +/*! + * Move data from aligned 32-bit source and place in (possibly unaligned) + * target, and maybe calculate CRC at the same time. + * + * Multiple calls can be made to this routine (without intervening calls to + * #copy_to_scc(), as long as the sum total of bytes copied is be a multiple + * of four. + * + * @param[in] from Location in SCC + * @param[out] to Location in memory + * @param[in] count_bytes Number of bytes to copy + * @param[in,out] crc Pointer to CRC. Initial value must be + * #CRC_CCITT_START if this is the start of + * message. Output is the resulting (maybe + * partial) CRC. If NULL, crc is not calculated. + * + * @return Zero - success. Non-zero - SCM status bits defining failure. + */ +static uint32_t +copy_from_scc(const uint32_t from, uint8_t * to, unsigned long count_bytes, + uint16_t * crc) +{ + uint32_t running_from = from; + uint32_t scm_word; + uint16_t current_crc = 0; /* local copy for fast access */ + uint32_t status; + pr_debug("SCC: copying %ld bytes from 0x%x.\n", count_bytes, from); + status = SCC_READ_REGISTER(SCM_ERROR_STATUS) & SCM_ACCESS_ERRORS; + if (status != 0) { + pr_debug + ("SCC copy_from_scc(): Error status detected (before copy):" + " %08x\n", status); + /* clear out errors left behind by somebody else */ + SCC_WRITE_REGISTER(SCM_ERROR_STATUS, status); + } + + if (crc) { + current_crc = *crc; + } + + /* Read word which is sitting in SCM memory. Ignore byte offset */ + scm_word = SCC_READ_REGISTER(SCC_WORD_PTR(running_from)); + + /* If necessary, move the 'first' byte into place */ + if (SCC_BYTE_OFFSET(running_from) != 0) { +#if defined(__BIG_ENDIAN) || defined(FSL_HAVE_DRYICE) + scm_word <<= 8 * SCC_BYTE_OFFSET(running_from); +#else + scm_word >>= 8 * SCC_BYTE_OFFSET(running_from); +#endif + } + + /* Now build up SCM words and write them out when each is full */ + while (count_bytes--) { + uint8_t byte; /* value from plaintext */ + +#if defined(__BIG_ENDIAN) || defined(FSL_HAVE_DRYICE) + byte = (scm_word & 0xff000000) >> 24; /* pull byte out of SCM word */ + scm_word <<= 8; /* shift over to remove the just-pulled byte */ +#else + byte = (scm_word & 0xff); + scm_word >>= 8; /* shift over to remove the just-pulled byte */ +#endif + *to++ = byte; /* send byte to memory */ + + /* now calculate CRC */ + if (crc) { + CALC_CRC(byte, current_crc); + } + + running_from++; + /* check for empty word */ + if (count_bytes && SCC_BYTE_OFFSET(running_from) == 0) { + /* read one in */ + scm_word = SCC_READ_REGISTER((uint32_t) running_from); + } + } + + if (crc) { + *crc = current_crc; + } + + status = SCC_READ_REGISTER(SCM_ERROR_STATUS) & SCM_ACCESS_ERRORS; + if (status != 0) { + pr_debug("SCC copy_from_scc(): Error status detected: %08x\n", + status); + /* Clear any/all bits. */ + SCC_WRITE_REGISTER(SCM_ERROR_STATUS, status); + } + + return status; +} + +/*****************************************************************************/ +/* fn scc_strip_padding() */ +/*****************************************************************************/ +/*! + * Remove padding from plaintext. Search backwards for #SCC_DRIVER_PAD_CHAR, + * verifying that each byte passed over is zero (0). Maximum number of bytes + * to examine is 8. + * + * @param[in] from Pointer to byte after end of message + * @param[out] count_bytes_stripped Number of padding bytes removed by this + * function. + * + * @return #SCC_RET_OK if all goes, well, #SCC_RET_FAIL if padding was + * not present. +*/ +static scc_return_t +scc_strip_padding(uint8_t * from, unsigned *count_bytes_stripped) +{ + int i = SCC_BLOCK_SIZE_BYTES(); + scc_return_t return_code = SCC_RET_VERIFICATION_FAILED; + + /* + * Search backwards looking for the magic marker. If it isn't found, + * make sure that a 0 byte is there in its place. Stop after the maximum + * amount of padding (8 bytes) has been searched); + */ + while (i-- > 0) { + if (*--from == SCC_DRIVER_PAD_CHAR) { + *count_bytes_stripped = SCC_BLOCK_SIZE_BYTES() - i; + return_code = SCC_RET_OK; + break; + } else if (*from != 0) { /* if not marker, check for 0 */ + pr_debug("SCC: Found non-zero interim pad: 0x%x\n", + *from); + break; + } + } + + return return_code; +} + +/*****************************************************************************/ +/* fn scc_update_state() */ +/*****************************************************************************/ +/*! + * Make certain SCC is still running. + * + * Side effect is to update #scc_availability and, if the state goes to failed, + * run #scc_perform_callbacks(). + * + * (If #SCC_BRINGUP is defined, bring SCC to secure state if it is found to be + * in health check state) + * + * @return Current value of #SMN_STATUS register. + */ +static uint32_t scc_update_state(void) +{ + uint32_t smn_status_register = SMN_STATE_FAIL; + int smn_state; + + /* if FAIL or UNIMPLEMENTED, don't bother */ + if (scc_availability == SCC_STATUS_CHECKING || + scc_availability == SCC_STATUS_OK) { + + smn_status_register = SCC_READ_REGISTER(SMN_STATUS); + smn_state = smn_status_register & SMN_STATUS_STATE_MASK; + +#ifdef SCC_BRINGUP + /* If in Health Check while booting, try to 'bringup' to Secure mode */ + if (scc_availability == SCC_STATUS_CHECKING && + smn_state == SMN_STATE_HEALTH_CHECK) { + /* Code up a simple algorithm for the ASC */ + SCC_WRITE_REGISTER(SMN_SEQUENCE_START, 0xaaaa); + SCC_WRITE_REGISTER(SMN_SEQUENCE_END, 0x5555); + SCC_WRITE_REGISTER(SMN_SEQUENCE_CHECK, 0x5555); + /* State should be SECURE now */ + smn_status_register = SCC_READ_REGISTER(SMN_STATUS); + smn_state = smn_status_register & SMN_STATUS_STATE_MASK; + } +#endif + + /* + * State should be SECURE or NON_SECURE for operation of the part. If + * FAIL, mark failed (i.e. limited access to registers). Any other + * state, mark unimplemented, as the SCC is unuseable. + */ + if (smn_state == SMN_STATE_SECURE + || smn_state == SMN_STATE_NON_SECURE) { + /* Healthy */ + scc_availability = SCC_STATUS_OK; + } else if (smn_state == SMN_STATE_FAIL) { + scc_availability = SCC_STATUS_FAILED; /* uh oh - unhealthy */ + scc_perform_callbacks(); + os_printk(KERN_ERR "SCC: SCC went into FAILED mode\n"); + } else { + /* START, ZEROIZE RAM, HEALTH CHECK, or unknown */ + scc_availability = SCC_STATUS_UNIMPLEMENTED; /* unuseable */ + os_printk(KERN_ERR "SCC: SCC declared UNIMPLEMENTED\n"); + } + } + /* if availability is initial or ok */ + return smn_status_register; +} + +/*****************************************************************************/ +/* fn scc_init_ccitt_crc() */ +/*****************************************************************************/ +/*! + * Populate the partial CRC lookup table. + * + * @return none + * + */ +static void scc_init_ccitt_crc(void) +{ + int dividend; /* index for lookup table */ + uint16_t remainder; /* partial value for a given dividend */ + int bit; /* index into bits of a byte */ + + /* + * Compute the remainder of each possible dividend. + */ + for (dividend = 0; dividend < 256; ++dividend) { + /* + * Start with the dividend followed by zeros. + */ + remainder = dividend << (8); + + /* + * Perform modulo-2 division, a bit at a time. + */ + for (bit = 8; bit > 0; --bit) { + /* + * Try to divide the current data bit. + */ + if (remainder & 0x8000) { + remainder = (remainder << 1) ^ CRC_POLYNOMIAL; + } else { + remainder = (remainder << 1); + } + } + + /* + * Store the result into the table. + */ + scc_crc_lookup_table[dividend] = remainder; + } + +} /* scc_init_ccitt_crc() */ + +/*****************************************************************************/ +/* fn grab_config_values() */ +/*****************************************************************************/ +/*! + * grab_config_values() will read the SCM Configuration and SMN Status + * registers and store away version and size information for later use. + * + * @return The current value of the SMN Status register. + */ +static uint32_t scc_grab_config_values(void) +{ + uint32_t config_register; + uint32_t smn_status_register = SMN_STATE_FAIL; + + if (scc_availability != SCC_STATUS_UNIMPLEMENTED) { + /* access the SCC - these are 'safe' registers */ + config_register = SCC_READ_REGISTER(SCM_CONFIGURATION); + pr_debug("SCC Driver: SCM config is 0x%08x\n", config_register); + + /* Get SMN status and update scc_availability */ + smn_status_register = scc_update_state(); + pr_debug("SCC Driver: SMN status is 0x%08x\n", + smn_status_register); + + /* save sizes and versions information for later use */ + scc_configuration.block_size_bytes = (config_register & + SCM_CFG_BLOCK_SIZE_MASK) + >> SCM_CFG_BLOCK_SIZE_SHIFT; + + scc_configuration.red_ram_size_blocks = (config_register & + SCM_CFG_RED_SIZE_MASK) + >> SCM_CFG_RED_SIZE_SHIFT; + + scc_configuration.black_ram_size_blocks = (config_register & + SCM_CFG_BLACK_SIZE_MASK) + >> SCM_CFG_BLACK_SIZE_SHIFT; + + scc_configuration.scm_version = (config_register + & SCM_CFG_VERSION_ID_MASK) + >> SCM_CFG_VERSION_ID_SHIFT; + + scc_configuration.smn_version = (smn_status_register & + SMN_STATUS_VERSION_ID_MASK) + >> SMN_STATUS_VERSION_ID_SHIFT; + + if (scc_configuration.scm_version != SCM_VERSION_1) { + scc_availability = SCC_STATUS_UNIMPLEMENTED; /* Unknown version */ + } + + scc_memory_size_bytes = (SCC_BLOCK_SIZE_BYTES() * + scc_configuration. + black_ram_size_blocks) + - SCM_NON_RESERVED_OFFSET; + + /* This last is for driver consumption only */ + scm_highest_memory_address = SCM_BLACK_MEMORY + + (SCC_BLOCK_SIZE_BYTES() * + scc_configuration.black_ram_size_blocks); + } + + return smn_status_register; +} /* grab_config_values */ + +/*****************************************************************************/ +/* fn setup_interrupt_handling() */ +/*****************************************************************************/ +/*! + * Register the SCM and SMN interrupt handlers. + * + * Called from #scc_init() + * + * @return 0 on success + */ +static int setup_interrupt_handling(void) +{ + int smn_error_code = -1; + int scm_error_code = -1; + + /* Disnable SCM interrupts */ + SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL, + SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT + | SCM_INTERRUPT_CTRL_MASK_INTERRUPTS); + +#ifdef USE_SMN_INTERRUPT + /* Install interrupt service routine for SMN. */ + smn_error_code = os_register_interrupt(SCC_DRIVER_NAME, + INT_SCC_SMN, scc_irq); + if (smn_error_code != 0) { + os_printk + ("SCC Driver: Error installing SMN Interrupt Handler: %d\n", + smn_error_code); + } else { + smn_irq_set = 1; /* remember this for cleanup */ + /* Enable SMN interrupts */ + SCC_WRITE_REGISTER(SMN_COMMAND, + SMN_COMMAND_CLEAR_INTERRUPT | + SMN_COMMAND_ENABLE_INTERRUPT); + } +#else + smn_error_code = 0; /* no problems... will handle later */ +#endif + + /* + * Install interrupt service routine for SCM (or both together). + */ + scm_error_code = os_register_interrupt(SCC_DRIVER_NAME, + INT_SCC_SCM, scc_irq); + if (scm_error_code != 0) { +#ifndef MXC + os_printk + ("SCC Driver: Error installing SCM Interrupt Handler: %d\n", + scm_error_code); +#else + os_printk + ("SCC Driver: Error installing SCC Interrupt Handler: %d\n", + scm_error_code); +#endif + } else { + scm_irq_set = 1; /* remember this for cleanup */ +#if defined(USE_SMN_INTERRUPT) && !defined(NO_SMN_INTERRUPT) + /* Enable SMN interrupts */ + SCC_WRITE_REGISTER(SMN_COMMAND, + SMN_COMMAND_CLEAR_INTERRUPT | + SMN_COMMAND_ENABLE_INTERRUPT); +#endif + } + + /* Return an error if one was encountered */ + return scm_error_code ? scm_error_code : smn_error_code; +} /* setup_interrupt_handling */ + +/*****************************************************************************/ +/* fn scc_do_crypto() */ +/*****************************************************************************/ +/*! Have the SCM perform the crypto function. + * + * Set up length register, and the store @c scm_control into control register + * to kick off the operation. Wait for completion, gather status, clear + * interrupt / status. + * + * @param byte_count number of bytes to perform in this operation + * @param scm_control Bit values to be set in @c SCM_CONTROL register + * + * @return 0 on success, value of #SCM_ERROR_STATUS on failure + */ +static uint32_t scc_do_crypto(int byte_count, uint32_t scm_control) +{ + int block_count = byte_count / SCC_BLOCK_SIZE_BYTES(); + uint32_t crypto_status; + + /* clear any outstanding flags */ + SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL, + SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT + | SCM_INTERRUPT_CTRL_MASK_INTERRUPTS); + + /* In length register, 0 means 1, etc. */ + SCC_WRITE_REGISTER(SCM_LENGTH, block_count - 1); + + /* set modes and kick off the operation */ + SCC_WRITE_REGISTER(SCM_CONTROL, scm_control); + + scc_wait_completion(); + + /* Mask for done and error bits */ + crypto_status = SCC_READ_REGISTER(SCM_STATUS) + & (SCM_STATUS_CIPHERING_DONE + | SCM_STATUS_LENGTH_ERROR | SCM_STATUS_INTERNAL_ERROR); + + /* Only done bit should be on */ + if (crypto_status != SCM_STATUS_CIPHERING_DONE) { + /* Replace with error status instead */ + crypto_status = SCC_READ_REGISTER(SCM_ERROR_STATUS); + pr_debug("SCM Failure: 0x%x\n", crypto_status); + if (crypto_status == 0) { + /* That came up 0. Turn on arbitrary bit to signal error. */ + crypto_status = SCM_ERR_INTERNAL_ERROR; + } + } else { + crypto_status = 0; + } + + pr_debug("SCC: Done waiting.\n"); + + /* Clear out any status. */ + SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL, + SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT + | SCM_INTERRUPT_CTRL_MASK_INTERRUPTS); + + /* And clear any error status */ + SCC_WRITE_REGISTER(SCM_ERROR_STATUS, 0); + + return crypto_status; +} + +/*****************************************************************************/ +/* fn scc_encrypt() */ +/*****************************************************************************/ +/*! + * Perform an encryption on the input. If @c verify_crc is true, a CRC must be + * calculated on the plaintext, and appended, with padding, before computing + * the ciphertext. + * + * @param[in] count_in_bytes Count of bytes of plaintext + * @param[in] data_in Pointer to the plaintext + * @param[in] scm_control Bit values for the SCM_CONTROL register + * @param[in,out] data_out Pointer for storing ciphertext + * @param[in] add_crc Flag for computing CRC - 0 no, else yes + * @param[in,out] count_out_bytes Number of bytes available at @c data_out + */ +static scc_return_t +scc_encrypt(uint32_t count_in_bytes, const uint8_t * data_in, + uint32_t scm_control, + uint8_t * data_out, int add_crc, unsigned long *count_out_bytes) + +{ + scc_return_t return_code = SCC_RET_FAIL; /* initialised for failure */ + uint32_t input_bytes_left = count_in_bytes; /* local copy */ + uint32_t output_bytes_copied = 0; /* running total */ + uint32_t bytes_to_process; /* multi-purpose byte counter */ + uint16_t crc = CRC_CCITT_START; /* running CRC value */ + crc_t *crc_ptr = NULL; /* Reset if CRC required */ + /* byte address into SCM RAM */ + uint32_t scm_location = SCM_RED_MEMORY + SCM_NON_RESERVED_OFFSET; + /* free RED RAM */ + uint32_t scm_bytes_remaining = scc_memory_size_bytes; + /* CRC+padding holder */ + uint8_t padding_buffer[PADDING_BUFFER_MAX_BYTES]; + unsigned padding_byte_count = 0; /* Reset if padding required */ + uint32_t scm_error_status = 0; /* No known SCM error initially */ + uint32_t i; /* Counter for clear data loop */ + uint32_t dirty_bytes; /* Number of bytes of memory used + temporarily during encryption, + which need to be wiped after + completion of the operation. */ + + /* Set location of CRC and prepare padding bytes if required */ + if (add_crc != 0) { + crc_ptr = &crc; + padding_byte_count = SCC_BLOCK_SIZE_BYTES() + - (count_in_bytes + + CRC_SIZE_BYTES) % SCC_BLOCK_SIZE_BYTES(); + memcpy(padding_buffer + CRC_SIZE_BYTES, scc_block_padding, + padding_byte_count); + } + + /* Process remaining input or padding data */ + while (input_bytes_left > 0) { + + /* Determine how much work to do this pass */ + bytes_to_process = (input_bytes_left > scm_bytes_remaining) ? + scm_bytes_remaining : input_bytes_left; + + /* Copy plaintext into SCM RAM, calculating CRC if required */ + copy_to_scc(data_in, scm_location, bytes_to_process, crc_ptr); + + /* Adjust pointers & counters */ + input_bytes_left -= bytes_to_process; + data_in += bytes_to_process; + scm_location += bytes_to_process; + scm_bytes_remaining -= bytes_to_process; + + /* Add CRC and padding after the last byte is copied if required */ + if ((input_bytes_left == 0) && (crc_ptr != NULL)) { + + /* Copy CRC into padding buffer MSB first */ + padding_buffer[0] = (crc >> 8) & 0xFF; + padding_buffer[1] = crc & 0xFF; + + /* Reset pointers and counter */ + data_in = padding_buffer; + input_bytes_left = CRC_SIZE_BYTES + padding_byte_count; + crc_ptr = NULL; /* CRC no longer required */ + + /* Go round loop again to copy CRC and padding to SCM */ + continue; + } + + /* if no input and crc_ptr */ + /* Now have block-sized plaintext in SCM to encrypt */ + /* Encrypt plaintext; exit loop on error */ + bytes_to_process = scm_location - + (SCM_RED_MEMORY + SCM_NON_RESERVED_OFFSET); + + if (output_bytes_copied + bytes_to_process > *count_out_bytes) { + return_code = SCC_RET_INSUFFICIENT_SPACE; + scm_error_status = -1; /* error signal */ + pr_debug + ("SCC: too many ciphertext bytes for space available\n"); + break; + } + pr_debug("SCC: Starting encryption. %x for %d bytes (%p/%p)\n", + scm_control, bytes_to_process, + (void *)SCC_READ_REGISTER(SCM_RED_START), + (void *)SCC_READ_REGISTER(SCM_BLACK_START)); + scm_error_status = scc_do_crypto(bytes_to_process, scm_control); + if (scm_error_status != 0) { + break; + } + + /* Copy out ciphertext */ + copy_from_scc(SCM_BLACK_MEMORY + SCM_NON_RESERVED_OFFSET, + data_out, bytes_to_process, NULL); + + /* Adjust pointers and counters for next loop */ + output_bytes_copied += bytes_to_process; + data_out += bytes_to_process; + scm_location = SCM_RED_MEMORY + SCM_NON_RESERVED_OFFSET; + scm_bytes_remaining = scc_memory_size_bytes; + + } /* input_bytes_left > 0 */ + /* Clear all red and black memory used during ephemeral encryption */ + dirty_bytes = (count_in_bytes > scc_memory_size_bytes) ? + scc_memory_size_bytes : count_in_bytes; + + for (i = 0; i < dirty_bytes; i += 4) { + SCC_WRITE_REGISTER(SCM_RED_MEMORY + SCM_NON_RESERVED_OFFSET + i, + 0); + SCC_WRITE_REGISTER(SCM_BLACK_MEMORY + SCM_NON_RESERVED_OFFSET + + i, 0); + } + + /* If no SCM error, set OK status and save ouput byte count */ + if (scm_error_status == 0) { + return_code = SCC_RET_OK; + *count_out_bytes = output_bytes_copied; + } + + return return_code; +} /* scc_encrypt */ + +/*****************************************************************************/ +/* fn scc_decrypt() */ +/*****************************************************************************/ +/*! + * Perform a decryption on the input. If @c verify_crc is true, the last block + * (maybe the two last blocks) is special - it should contain a CRC and + * padding. These must be stripped and verified. + * + * @param[in] count_in_bytes Count of bytes of ciphertext + * @param[in] data_in Pointer to the ciphertext + * @param[in] scm_control Bit values for the SCM_CONTROL register + * @param[in,out] data_out Pointer for storing plaintext + * @param[in] verify_crc Flag for running CRC - 0 no, else yes + * @param[in,out] count_out_bytes Number of bytes available at @c data_out + + */ +static scc_return_t +scc_decrypt(uint32_t count_in_bytes, const uint8_t * data_in, + uint32_t scm_control, + uint8_t * data_out, int verify_crc, unsigned long *count_out_bytes) +{ + scc_return_t return_code = SCC_RET_FAIL; + uint32_t bytes_left = count_in_bytes; /* local copy */ + uint32_t bytes_copied = 0; /* running total of bytes going to user */ + uint32_t bytes_to_copy = 0; /* Number in this encryption 'chunk' */ + uint16_t crc = CRC_CCITT_START; /* running CRC value */ + /* next target for ctext */ + uint32_t scm_location = SCM_BLACK_MEMORY + SCM_NON_RESERVED_OFFSET; + unsigned padding_byte_count; /* number of bytes of padding stripped */ + uint8_t last_two_blocks[2 * SCC_BLOCK_SIZE_BYTES()]; /* temp */ + uint32_t scm_error_status = 0; /* register value */ + uint32_t i; /* Counter for clear data loop */ + uint32_t dirty_bytes; /* Number of bytes of memory used + temporarily during decryption, + which need to be wiped after + completion of the operation. */ + + scm_control |= SCM_DECRYPT_MODE; + + if (verify_crc) { + /* Save last two blocks (if there are at least two) of ciphertext for + special treatment. */ + bytes_left -= SCC_BLOCK_SIZE_BYTES(); + if (bytes_left >= SCC_BLOCK_SIZE_BYTES()) { + bytes_left -= SCC_BLOCK_SIZE_BYTES(); + } + } + + /* Copy ciphertext into SCM BLACK memory */ + while (bytes_left && scm_error_status == 0) { + + /* Determine how much work to do this pass */ + if (bytes_left > (scc_memory_size_bytes)) { + bytes_to_copy = scc_memory_size_bytes; + } else { + bytes_to_copy = bytes_left; + } + + if (bytes_copied + bytes_to_copy > *count_out_bytes) { + scm_error_status = -1; + break; + } + copy_to_scc(data_in, scm_location, bytes_to_copy, NULL); + data_in += bytes_to_copy; /* move pointer */ + + pr_debug("SCC: Starting decryption of %d bytes.\n", + bytes_to_copy); + + /* Do the work, wait for completion */ + scm_error_status = scc_do_crypto(bytes_to_copy, scm_control); + + copy_from_scc(SCM_RED_MEMORY + SCM_NON_RESERVED_OFFSET, + data_out, bytes_to_copy, &crc); + bytes_copied += bytes_to_copy; + data_out += bytes_to_copy; + scm_location = SCM_BLACK_MEMORY + SCM_NON_RESERVED_OFFSET; + + /* Do housekeeping */ + bytes_left -= bytes_to_copy; + + } /* while bytes_left */ + + /* At this point, either the process is finished, or this is verify mode */ + + if (scm_error_status == 0) { + if (!verify_crc) { + *count_out_bytes = bytes_copied; + return_code = SCC_RET_OK; + } else { + /* Verify mode. There are one or two blocks of unprocessed + * ciphertext sitting at data_in. They need to be moved to the + * SCM, decrypted, searched to remove padding, then the plaintext + * copied back to the user (while calculating CRC, of course). + */ + + /* Calculate ciphertext still left */ + bytes_to_copy = count_in_bytes - bytes_copied; + + copy_to_scc(data_in, scm_location, bytes_to_copy, NULL); + data_in += bytes_to_copy; /* move pointer */ + + pr_debug("SCC: Finishing decryption (%d bytes).\n", + bytes_to_copy); + + /* Do the work, wait for completion */ + scm_error_status = + scc_do_crypto(bytes_to_copy, scm_control); + + if (scm_error_status == 0) { + /* Copy decrypted data back from SCM RED memory */ + copy_from_scc(SCM_RED_MEMORY + + SCM_NON_RESERVED_OFFSET, + last_two_blocks, bytes_to_copy, + NULL); + + /* (Plaintext) + crc + padding should be in temp buffer */ + if (scc_strip_padding + (last_two_blocks + bytes_to_copy, + &padding_byte_count) == SCC_RET_OK) { + bytes_to_copy -= + padding_byte_count + CRC_SIZE_BYTES; + + /* verify enough space in user buffer */ + if (bytes_copied + bytes_to_copy <= + *count_out_bytes) { + int i = 0; + + /* Move out last plaintext and calc CRC */ + while (i < bytes_to_copy) { + CALC_CRC(last_two_blocks + [i], crc); + *data_out++ = + last_two_blocks + [i++]; + bytes_copied++; + } + + /* Verify the CRC by running over itself */ + CALC_CRC(last_two_blocks + [bytes_to_copy], crc); + CALC_CRC(last_two_blocks + [bytes_to_copy + 1], + crc); + if (crc == 0) { + /* Just fine ! */ + *count_out_bytes = + bytes_copied; + return_code = + SCC_RET_OK; + } else { + return_code = + SCC_RET_VERIFICATION_FAILED; + pr_debug + ("SCC: CRC values are %04x, %02x%02x\n", + crc, + last_two_blocks + [bytes_to_copy], + last_two_blocks + [bytes_to_copy + + 1]); + } + } /* if space available */ + } /* if scc_strip_padding... */ + else { + /* bad padding means bad verification */ + return_code = + SCC_RET_VERIFICATION_FAILED; + } + } + /* scm_error_status == 0 */ + } /* verify_crc */ + } + + /* scm_error_status == 0 */ + /* Clear all red and black memory used during ephemeral decryption */ + dirty_bytes = (count_in_bytes > scc_memory_size_bytes) ? + scc_memory_size_bytes : count_in_bytes; + + for (i = 0; i < dirty_bytes; i += 4) { + SCC_WRITE_REGISTER(SCM_RED_MEMORY + SCM_NON_RESERVED_OFFSET + i, + 0); + SCC_WRITE_REGISTER(SCM_BLACK_MEMORY + SCM_NON_RESERVED_OFFSET + + i, 0); + } + return return_code; +} /* scc_decrypt */ + +/*****************************************************************************/ +/* fn scc_alloc_slot() */ +/*****************************************************************************/ +/*! + * Allocate a key slot to fit the requested size. + * + * @param value_size_bytes Size of the key or other secure data + * @param owner_id Value to tie owner to slot + * @param[out] slot Handle to access or deallocate slot + * + * @return SCC_RET_OK on success, SCC_RET_INSUFFICIENT_SPACE if not slots of + * requested size are available. + */ +scc_return_t +scc_alloc_slot(uint32_t value_size_bytes, uint64_t owner_id, uint32_t * slot) +{ + scc_return_t status = SCC_RET_FAIL; + unsigned long irq_flags; + + if (scc_availability != SCC_STATUS_OK) { + goto out; + } + /* ACQUIRE LOCK to prevent others from using SCC crypto */ + spin_lock_irqsave(&scc_crypto_lock, irq_flags); + + pr_debug("SCC: Allocating %d-byte slot for 0x%Lx\n", + value_size_bytes, owner_id); + + if ((value_size_bytes != 0) && (value_size_bytes <= SCC_MAX_KEY_SIZE)) { + int i; + + for (i = 0; i < SCC_KEY_SLOTS; i++) { + if (scc_key_info[i].status == 0) { + scc_key_info[i].owner_id = owner_id; + scc_key_info[i].length = value_size_bytes; + scc_key_info[i].status = 1; /* assigned! */ + *slot = i; + status = SCC_RET_OK; + break; /* exit 'for' loop */ + } + } + + if (status != SCC_RET_OK) { + status = SCC_RET_INSUFFICIENT_SPACE; + } else { + pr_debug("SCC: Allocated slot %d (0x%Lx)\n", i, + owner_id); + } + } + + spin_unlock_irqrestore(&scc_crypto_lock, irq_flags); + + out: + return status; +} + +/*****************************************************************************/ +/* fn verify_slot_access() */ +/*****************************************************************************/ +inline static scc_return_t +verify_slot_access(uint64_t owner_id, uint32_t slot, uint32_t access_len) +{ + scc_return_t status = SCC_RET_FAIL; + if (scc_availability != SCC_STATUS_OK) { + goto out; + } + + if ((slot < SCC_KEY_SLOTS) && scc_key_info[slot].status + && (scc_key_info[slot].owner_id == owner_id) + && (access_len <= SCC_KEY_SLOT_SIZE)) { + status = SCC_RET_OK; + pr_debug("SCC: Verify on slot %d succeeded\n", slot); + } else { + if (slot >= SCC_KEY_SLOTS) { + pr_debug("SCC: Verify on bad slot (%d) failed\n", slot); + } else if (scc_key_info[slot].status) { + pr_debug("SCC: Verify on slot %d failed (%Lx) \n", slot, + owner_id); + } else { + pr_debug + ("SCC: Verify on slot %d failed: not allocated\n", + slot); + } + } + + out: + return status; +} + +scc_return_t +scc_verify_slot_access(uint64_t owner_id, uint32_t slot, uint32_t access_len) +{ + return verify_slot_access(owner_id, slot, access_len); +} + +/*****************************************************************************/ +/* fn scc_dealloc_slot() */ +/*****************************************************************************/ +scc_return_t scc_dealloc_slot(uint64_t owner_id, uint32_t slot) +{ + scc_return_t status; + unsigned long irq_flags; + int i; + + /* ACQUIRE LOCK to prevent others from using SCC crypto */ + spin_lock_irqsave(&scc_crypto_lock, irq_flags); + + status = verify_slot_access(owner_id, slot, 0); + + if (status == SCC_RET_OK) { + scc_key_info[slot].owner_id = 0; + scc_key_info[slot].status = 0; /* unassign */ + + /* clear old info */ + for (i = 0; i < SCC_KEY_SLOT_SIZE; i += 4) { + SCC_WRITE_REGISTER(SCM_RED_MEMORY + + scc_key_info[slot].offset + i, 0); + SCC_WRITE_REGISTER(SCM_BLACK_MEMORY + + scc_key_info[slot].offset + i, 0); + } + pr_debug("SCC: Deallocated slot %d\n", slot); + } + + spin_unlock_irqrestore(&scc_crypto_lock, irq_flags); + + return status; +} + +/*****************************************************************************/ +/* fn scc_load_slot() */ +/*****************************************************************************/ +/*! + * Load a value into a slot. + * + * @param owner_id Value of owner of slot + * @param slot Handle of slot + * @param key_data Data to load into the slot + * @param key_length Length, in bytes, of @c key_data to copy to SCC. + * + * @return SCC_RET_OK on success. SCC_RET_FAIL will be returned if slot + * specified cannot be accessed for any reason, or SCC_RET_INSUFFICIENT_SPACE + * if @c key_length exceeds the size of the slot. + */ +scc_return_t +scc_load_slot(uint64_t owner_id, uint32_t slot, const uint8_t * key_data, + uint32_t key_length) +{ + scc_return_t status; + unsigned long irq_flags; + + /* ACQUIRE LOCK to prevent others from using SCC crypto */ + spin_lock_irqsave(&scc_crypto_lock, irq_flags); + + status = verify_slot_access(owner_id, slot, key_length); + if ((status == SCC_RET_OK) && (key_data != NULL)) { + status = SCC_RET_FAIL; /* reset expectations */ + + if (key_length > SCC_KEY_SLOT_SIZE) { + pr_debug + ("SCC: scc_load_slot() rejecting key of %d bytes.\n", + key_length); + status = SCC_RET_INSUFFICIENT_SPACE; + } else { + if (copy_to_scc(key_data, + SCM_RED_MEMORY + + scc_key_info[slot].offset, key_length, + NULL)) { + pr_debug("SCC: RED copy_to_scc() failed for" + " scc_load_slot()\n"); + } else { + if ((key_length % 4) != 0) { + uint32_t zeros = 0; + + /* zero-pad to get remainder bytes in correct place */ + copy_to_scc((uint8_t *) & zeros, + SCM_RED_MEMORY + + + scc_key_info[slot].offset + + key_length, + 4 - (key_length % 4), NULL); + } + status = SCC_RET_OK; + } + } + } + + spin_unlock_irqrestore(&scc_crypto_lock, irq_flags); + + return status; +} /* scc_load_slot */ + +scc_return_t +scc_read_slot(uint64_t owner_id, uint32_t slot, uint32_t key_length, + uint8_t * key_data) +{ + scc_return_t status; + unsigned long irq_flags; + + /* ACQUIRE LOCK to prevent others from using SCC crypto */ + spin_lock_irqsave(&scc_crypto_lock, irq_flags); + + status = verify_slot_access(owner_id, slot, key_length); + if ((status == SCC_RET_OK) && (key_data != NULL)) { + status = SCC_RET_FAIL; /* reset expectations */ + + if (key_length > SCC_KEY_SLOT_SIZE) { + pr_debug + ("SCC: scc_read_slot() rejecting key of %d bytes.\n", + key_length); + status = SCC_RET_INSUFFICIENT_SPACE; + } else { + if (copy_from_scc + (SCM_RED_MEMORY + scc_key_info[slot].offset, + key_data, key_length, NULL)) { + pr_debug("SCC: RED copy_from_scc() failed for" + " scc_read_slot()\n"); + } else { + status = SCC_RET_OK; + } + } + } + + spin_unlock_irqrestore(&scc_crypto_lock, irq_flags); + + return status; +} /* scc_read_slot */ + +/*****************************************************************************/ +/* fn scc_encrypt_slot() */ +/*****************************************************************************/ +/*! + * Encrypt the key data stored in a slot. + * + * @param owner_id Value of owner of slot + * @param slot Handle of slot + * @param length Length, in bytes, of @c black_data + * @param black_data Location to store result of encrypting RED data in slot + * + * @return SCC_RET_OK on success, SCC_RET_FAIL if slot specified cannot be + * accessed for any reason. + */ +scc_return_t scc_encrypt_slot(uint64_t owner_id, uint32_t slot, + uint32_t length, uint8_t * black_data) +{ + unsigned long irq_flags; + scc_return_t status; + uint32_t crypto_status; + uint32_t slot_offset = + scc_key_info[slot].offset / SCC_BLOCK_SIZE_BYTES(); + + /* ACQUIRE LOCK to prevent others from using crypto or releasing slot */ + spin_lock_irqsave(&scc_crypto_lock, irq_flags); + + status = verify_slot_access(owner_id, slot, length); + if (status == SCC_RET_OK) { + SCC_WRITE_REGISTER(SCM_BLACK_START, slot_offset); + SCC_WRITE_REGISTER(SCM_RED_START, slot_offset); + + /* Use OwnerID as CBC IV to tie Owner to data */ + SCC_WRITE_REGISTER(SCM_INIT_VECTOR_0, *(uint32_t *) & owner_id); + SCC_WRITE_REGISTER(SCM_INIT_VECTOR_1, + *(((uint32_t *) & owner_id) + 1)); + + /* Set modes and kick off the encryption */ + crypto_status = scc_do_crypto(length, + SCM_CONTROL_START_CIPHER | + SCM_CBC_MODE); + + if (crypto_status != 0) { + pr_debug("SCM encrypt red crypto failure: 0x%x\n", + crypto_status); + } else { + + /* Give blob back to caller */ + if (!copy_from_scc + (SCM_BLACK_MEMORY + scc_key_info[slot].offset, + black_data, length, NULL)) { + status = SCC_RET_OK; + pr_debug("SCC: Encrypted slot %d\n", slot); + } + } + } + + spin_unlock_irqrestore(&scc_crypto_lock, irq_flags); + + return status; +} + +/*****************************************************************************/ +/* fn scc_decrypt_slot() */ +/*****************************************************************************/ +/*! + * Decrypt some black data and leave result in the slot. + * + * @param owner_id Value of owner of slot + * @param slot Handle of slot + * @param length Length, in bytes, of @c black_data + * @param black_data Location of data to dencrypt and store in slot + * + * @return SCC_RET_OK on success, SCC_RET_FAIL if slot specified cannot be + * accessed for any reason. + */ +scc_return_t scc_decrypt_slot(uint64_t owner_id, uint32_t slot, + uint32_t length, const uint8_t * black_data) +{ + unsigned long irq_flags; + scc_return_t status; + uint32_t crypto_status; + uint32_t slot_offset = + scc_key_info[slot].offset / SCC_BLOCK_SIZE_BYTES(); + + /* ACQUIRE LOCK to prevent others from using crypto or releasing slot */ + spin_lock_irqsave(&scc_crypto_lock, irq_flags); + + status = verify_slot_access(owner_id, slot, length); + if (status == SCC_RET_OK) { + status = SCC_RET_FAIL; /* reset expectations */ + + /* Place black key in to BLACK RAM and set up the SCC */ + copy_to_scc(black_data, + SCM_BLACK_MEMORY + scc_key_info[slot].offset, + length, NULL); + + SCC_WRITE_REGISTER(SCM_BLACK_START, slot_offset); + SCC_WRITE_REGISTER(SCM_RED_START, slot_offset); + + /* Use OwnerID as CBC IV to tie Owner to data */ + SCC_WRITE_REGISTER(SCM_INIT_VECTOR_0, *(uint32_t *) & owner_id); + SCC_WRITE_REGISTER(SCM_INIT_VECTOR_1, + *(((uint32_t *) & owner_id) + 1)); + + /* Set modes and kick off the decryption */ + crypto_status = scc_do_crypto(length, + SCM_CONTROL_START_CIPHER + | SCM_CBC_MODE | + SCM_DECRYPT_MODE); + + if (crypto_status != 0) { + pr_debug("SCM decrypt black crypto failure: 0x%x\n", + crypto_status); + } else { + status = SCC_RET_OK; + } + } + + spin_unlock_irqrestore(&scc_crypto_lock, irq_flags); + + return status; +} + +/*****************************************************************************/ +/* fn scc_get_slot_info() */ +/*****************************************************************************/ +/*! + * Determine address and value length for a give slot. + * + * @param owner_id Value of owner of slot + * @param slot Handle of slot + * @param address Location to store kernel address of slot data + * @param value_size_bytes Location to store allocated length of data in slot. + * May be NULL if value is not needed by caller. + * @param slot_size_bytes Location to store max length data in slot + * May be NULL if value is not needed by caller. + * + * @return SCC_RET_OK or error indication + */ +scc_return_t +scc_get_slot_info(uint64_t owner_id, uint32_t slot, uint32_t * address, + uint32_t * value_size_bytes, uint32_t * slot_size_bytes) +{ + scc_return_t status = verify_slot_access(owner_id, slot, 0); + + if (status == SCC_RET_OK) { + *address = + SCC_BASE + SCM_RED_MEMORY + scc_key_info[slot].offset; + if (value_size_bytes != NULL) { + *value_size_bytes = scc_key_info[slot].length; + } + if (slot_size_bytes != NULL) { + *slot_size_bytes = SCC_KEY_SLOT_SIZE; + } + } + + return status; +} + +/*****************************************************************************/ +/* fn scc_wait_completion() */ +/*****************************************************************************/ +/*! + * Poll looking for end-of-cipher indication. Only used + * if @c SCC_SCM_SLEEP is not defined. + * + * @internal + * + * On a Tahiti, crypto under 230 or so bytes is done after the first loop, all + * the way up to five sets of spins for 1024 bytes. (8- and 16-byte functions + * are done when we first look. Zeroizing takes one pass around. + */ +static void scc_wait_completion(void) +{ + int i = 0; + + /* check for completion by polling */ + while (!is_cipher_done() && (i++ < SCC_CIPHER_MAX_POLL_COUNT)) { + udelay(10); + } + pr_debug("SCC: Polled DONE %d times\n", i); +} /* scc_wait_completion() */ + +/*****************************************************************************/ +/* fn is_cipher_done() */ +/*****************************************************************************/ +/*! + * This function returns non-zero if SCM Status register indicates + * that a cipher has terminated or some other interrupt-generating + * condition has occurred. + */ +static int is_cipher_done(void) +{ + register uint32_t scm_status; + register int cipher_done; + + scm_status = SCC_READ_REGISTER(SCM_STATUS); + + /* + * Done when 'SCM is currently performing a function' bits are zero + */ + cipher_done = !(scm_status & (SCM_STATUS_ZEROIZING | + SCM_STATUS_CIPHERING)); + + return cipher_done; +} /* is_cipher_done() */ + +/*****************************************************************************/ +/* fn offset_within_smn() */ +/*****************************************************************************/ +/*! + * Check that the offset is with the bounds of the SMN register set. + * + * @param[in] register_offset register offset of SMN. + * + * @return 1 if true, 0 if false (not within SMN) + */ +static inline int offset_within_smn(uint32_t register_offset) +{ + return register_offset >= SMN_STATUS && register_offset <= SMN_TIMER; +} + +/*****************************************************************************/ +/* fn offset_within_scm() */ +/*****************************************************************************/ +/*! + * Check that the offset is with the bounds of the SCM register set. + * + * @param[in] register_offset Register offset of SCM + * + * @return 1 if true, 0 if false (not within SCM) + */ +static inline int offset_within_scm(uint32_t register_offset) +{ + return (register_offset >= SCM_RED_START) + && (register_offset < scm_highest_memory_address); + /* Although this would cause trouble for zeroize testing, this change would + * close a security whole which currently allows any kernel program to access + * any location in RED RAM. Perhaps enforce in non-SCC_DEBUG compiles? + && (register_offset <= SCM_INIT_VECTOR_1); */ +} + +/*****************************************************************************/ +/* fn check_register_accessible() */ +/*****************************************************************************/ +/*! + * Given the current SCM and SMN status, verify that access to the requested + * register should be OK. + * + * @param[in] register_offset register offset within SCC + * @param[in] smn_status recent value from #SMN_STATUS + * @param[in] scm_status recent value from #SCM_STATUS + * + * @return #SCC_RET_OK if ok, #SCC_RET_FAIL if not + */ +static scc_return_t +check_register_accessible(uint32_t register_offset, uint32_t smn_status, + uint32_t scm_status) +{ + int error_code = SCC_RET_FAIL; + + /* Verify that the register offset passed in is not among the verboten set + * if the SMN is in Fail mode. + */ + if (offset_within_smn(register_offset)) { + if ((smn_status & SMN_STATUS_STATE_MASK) == SMN_STATE_FAIL) { + if (!((register_offset == SMN_STATUS) || + (register_offset == SMN_COMMAND) || + (register_offset == SMN_DEBUG_DETECT_STAT))) { + pr_debug + ("SCC Driver: Note: Security State is in FAIL state.\n"); + } /* register not a safe one */ + else { + /* SMN is in FAIL, but register is a safe one */ + error_code = SCC_RET_OK; + } + } /* State is FAIL */ + else { + /* State is not fail. All registers accessible. */ + error_code = SCC_RET_OK; + } + } + /* offset within SMN */ + /* Not SCM register. Check for SCM busy. */ + else if (offset_within_scm(register_offset)) { + /* This is the 'cannot access' condition in the SCM */ + if ((scm_status & SCM_STATUS_BUSY) + /* these are always available - rest fail on busy */ + && !((register_offset == SCM_STATUS) || + (register_offset == SCM_ERROR_STATUS) || + (register_offset == SCM_INTERRUPT_CTRL) || + (register_offset == SCM_CONFIGURATION))) { + pr_debug + ("SCC Driver: Note: Secure Memory is in BUSY state.\n"); + } /* status is busy & register inaccessible */ + else { + error_code = SCC_RET_OK; + } + } + /* offset within SCM */ + return error_code; + +} /* check_register_accessible() */ + +/*****************************************************************************/ +/* fn check_register_offset() */ +/*****************************************************************************/ +/*! + * Check that the offset is with the bounds of the SCC register set. + * + * @param[in] register_offset register offset of SMN. + * + * #SCC_RET_OK if ok, #SCC_RET_FAIL if not + */ +static scc_return_t check_register_offset(uint32_t register_offset) +{ + int return_value = SCC_RET_FAIL; + + /* Is it valid word offset ? */ + if (SCC_BYTE_OFFSET(register_offset) == 0) { + /* Yes. Is register within SCM? */ + if (offset_within_scm(register_offset)) { + return_value = SCC_RET_OK; /* yes, all ok */ + } + /* Not in SCM. Now look within the SMN */ + else if (offset_within_smn(register_offset)) { + return_value = SCC_RET_OK; /* yes, all ok */ + } + } + + return return_value; +} + +#ifdef SCC_REGISTER_DEBUG + +/*****************************************************************************/ +/* fn dbg_scc_read_register() */ +/*****************************************************************************/ +/*! + * Noisily read a 32-bit value to an SCC register. + * @param offset The address of the register to read. + * + * @return The register value + * */ +static uint32_t dbg_scc_read_register(uint32_t offset) +{ + uint32_t value; + + value = readl(scc_base + offset); + +#ifndef SCC_RAM_DEBUG /* print no RAM references */ + if ((offset < SCM_RED_MEMORY) || (offset >= scm_highest_memory_address)) { +#endif + pr_debug("SCC RD: 0x%4x : 0x%08x\n", offset, value); +#ifndef SCC_RAM_DEBUG + } +#endif + + return value; +} + +/*****************************************************************************/ +/* fn dbg_scc_write_register() */ +/*****************************************************************************/ +/* + * Noisily read a 32-bit value to an SCC register. + * @param offset The address of the register to written. + * + * @param value The new register value + */ +static void dbg_scc_write_register(uint32_t offset, uint32_t value) +{ + +#ifndef SCC_RAM_DEBUG /* print no RAM references */ + if ((offset < SCM_RED_MEMORY) || (offset >= scm_highest_memory_address)) { +#endif + pr_debug("SCC WR: 0x%4x : 0x%08x\n", offset, value); +#ifndef SCC_RAM_DEBUG + } +#endif + + (void)writel(value, scc_base + offset); +} + +#endif /* SCC_REGISTER_DEBUG */ diff -urN linux-2.6.26/drivers/mxc/security/mxc_scc_internals.h linux-2.6.26-lab126/drivers/mxc/security/mxc_scc_internals.h --- linux-2.6.26/drivers/mxc/security/mxc_scc_internals.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/mxc_scc_internals.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,499 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MXC_SCC_INTERNALS_H__ +#define __MXC_SCC_INTERNALS_H__ + +/*! + * @file mxc_scc_internals.h + * + * @brief This is intended to be the file which contains most or all of the code or + * changes need to port the driver. It also includes other definitions needed + * by the driver. + * + * This header file should only ever be included by scc_driver.c + * + * Compile-time flags minimally needed: + * + * @li Some sort of platform flag. + * @li Some start-of-SCC consideration, such as SCC_BASE_ADDR + * + * Some changes which could be made when porting this driver: + * #SCC_SPIN_COUNT + * + * @ingroup MXCSCC + */ +#if 0 +#include /* Current version Linux kernel */ +#include /* Basic support for loadable modules, + printk */ +#include /* module_init, module_exit */ +#include /* General kernel system calls */ +#include /* for interrupt.h */ +#include +#include /* IRQ / interrupt definitions */ +#include /* ioremap() */ +#endif +#include + +/* Get handle on certain per-platform symbols */ +#ifdef TAHITI +#include + +/* + * Mark the SCC as always there... as Tahiti is not officially supported by + * driver. Porting opportunity. + */ +#define SCC_ENABLED() (1) + +#elif defined(MXC) + +#include +#include + +#ifdef SCC_FUSE + +/* + * This macro is used to determine whether the SCC is enabled/available + * on the platform. This macro may need to be ported. + */ +#define SCC_ENABLED() ((SCC_FUSE & MXC_IIMHWV1_SCC_DISABLE) == 0) + +#else + +#warning SCC_FUSE not defined, assuming the SCC is enabled. +#define SCC_ENABLED() (1) + +#endif + +#else /* neither TAHITI nor MXC */ + +#error Do not understand target architecture + +#endif /* TAHITI */ + +/* Temporarily define compile-time flags to make Doxygen happy. */ +#ifdef DOXYGEN_HACK +/*! @addtogroup scccompileflags */ +/*! @{ */ + +/*! @def NO_SMN_INTERRUPT + * The SMN interrupt is not wired to the CPU at all. + */ +#define NO_SMN_INTERRUPT + +/*! + * Register an interrupt handler for the SMN as well as + * the SCM. In some implementations, the SMN is not connected at all (see + * #NO_SMN_INTERRUPT), and in others, it is on the same interrupt line as the + * SCM. When defining this flag, the SMN interrupt should be on a separate + * line from the SCM interrupt. + */ + +#define USE_SMN_INTERRUPT + +/*! + * Turn on generation of run-time operational, debug, and error messages + */ +#define SCC_DEBUG + +/*! + * Turn on generation of run-time logging of access to the SCM and SMN + * registers. + */ +#define SCC_REGISTER_DEBUG + +/*! + * Turn on generation of run-time logging of access to the SCM Red and + * Black memories. Will only work if #SCC_REGISTER_DEBUG is also defined. + */ +#define SCC_RAM_DEBUG + +/*! + * If the driver finds the SCC in HEALTH_CHECK state, go ahead and + * run a quick ASC to bring it to SECURE state. + */ +#define SCC_BRINGUP + +/*! + * Expected to come from platform header files or compile command line. + * This symbol must be the address of the SCC + */ +#define SCC_BASE + +/*! + * This must be the interrupt line number of the SCM interrupt. + */ +#define INT_SCM + +/*! + * if #USE_SMN_INTERRUPT is defined, this must be the interrupt line number of + * the SMN interrupt. + */ +#define INT_SMN + +/*! + * Define the number of Stored Keys which the SCC driver will make available. + * Value shall be from 0 to 20. Default is zero (0). + */ +#define SCC_KEY_SLOTS + +/*! + * Make sure that this flag is defined if compiling for a Little-Endian + * platform. Linux Kernel builds provide this flag. + */ +#define __LITTLE_ENDIAN + +/*! + * Make sure that this flag is defined if compiling for a Big-Endian platform. + * Linux Kernel builds provide this flag. + */ +#define __BIG_ENDIAN + +/*! + * Read a 32-bit register value from a 'peripheral'. Standard Linux/Unix + * macro. + * + * @param offset Bus address of register to be read + * + * @return The value of the register + */ +#define readl(offset) + +/*! + * Write a 32-bit value to a register in a 'peripheral'. Standard Linux/Unix + * macro. + * + * @param value The 32-bit value to store + * @param offset Bus address of register to be written + * + * return (none) + */ +#define writel(value,offset) + + /*! @} *//* end group scccompileflags */ + +#endif /* DOXYGEN_HACK */ + +/*! + * Define the number of Stored Keys which the SCC driver will make available. + * Value shall be from 0 to 20. Default is zero (0). + */ +#define SCC_KEY_SLOTS 20 + +#ifndef SCC_KEY_SLOTS +#define SCC_KEY_SLOTS 0 + +#else + +#if (SCC_KEY_SLOTS < 0) || (SCC_KEY_SLOTS > 20) +#error Bad value for SCC_KEY_SLOTS +#endif + +/*! + * Maximum length of key/secret value which can be stored in SCC. + */ +#define SCC_MAX_KEY_SIZE 32 + +/*! + * This is the size, in bytes, of each key slot, and therefore the maximum size + * of the wrapped key. + */ +#define SCC_KEY_SLOT_SIZE 32 + +/*! + * This is the offset into each RAM of the base of the area which is + * not used for Stored Keys. + */ +#define SCM_NON_RESERVED_OFFSET (SCC_KEY_SLOTS * SCC_KEY_SLOT_SIZE) + +#endif + +/* These come for free with Linux, but may need to be set in a port. */ +#ifndef __BIG_ENDIAN +#ifndef __LITTLE_ENDIAN +#error One of __LITTLE_ENDIAN or __BIG_ENDIAN must be #defined +#endif +#else +#ifdef __LITTLE_ENDIAN +#error Exactly one of __LITTLE_ENDIAN or __BIG_ENDIAN must be #defined +#endif +#endif + +#ifndef SCC_CALLBACK_SIZE +/*! The number of function pointers which can be stored in #scc_callbacks. + * Defaults to 4, can be overridden with compile-line argument. + */ +#define SCC_CALLBACK_SIZE 4 +#endif + +/*! Initial CRC value for CCITT-CRC calculation. */ +#define CRC_CCITT_START 0xFFFF + +#ifdef TAHITI + +/*! + * The SCC_BASE has to be SMN_BASE_ADDR on TAHITI, as the banks of + * registers are swapped in place. + */ +#define SCC_BASE SMN_BASE_ADDR + +/*! The interrupt number for the SCC (SCM only!) on Tahiti */ +#define INT_SCC_SCM 62 + +/*! Tahiti does not have the SMN interrupt wired to the CPU. */ +#define NO_SMN_INTERRUPT + +#endif /* TAHITI */ + +/*! Number of times to spin between polling of SCC while waiting for cipher + * or zeroizing function to complete. See also #SCC_CIPHER_MAX_POLL_COUNT. */ +#define SCC_SPIN_COUNT 1000 + +/*! Number of times to polling SCC while waiting for cipher + * or zeroizing function to complete. See also #SCC_SPIN_COUNT. */ +#define SCC_CIPHER_MAX_POLL_COUNT 100 + +/*! + * @def SCC_READ_REGISTER + * Read a 32-bit value from an SCC register. Macro which depends upon + * #scc_base. Linux readl()/writel() macros operate on 32-bit quantities, as + * do SCC register reads/writes. + * + * @param offset Register offset within SCC. + * + * @return The value from the SCC's register. + */ +#ifndef SCC_REGISTER_DEBUG +#define SCC_READ_REGISTER(offset) __raw_readl(scc_base+(offset)) +#else +#define SCC_READ_REGISTER(offset) dbg_scc_read_register(offset) +#endif + +/*! + * Write a 32-bit value to an SCC register. Macro depends upon #scc_base. + * Linux readl()/writel() macros operate on 32-bit quantities, as do SCC + * register reads/writes. + * + * @param offset Register offset within SCC. + * @param value 32-bit value to store into the register + * + * @return (void) + */ +#ifndef SCC_REGISTER_DEBUG +#define SCC_WRITE_REGISTER(offset,value) (void)__raw_writel(value, scc_base+(offset)) +#else +#define SCC_WRITE_REGISTER(offset,value) dbg_scc_write_register(offset, value) +#endif + +/*! + * Calculates the byte offset into a word + * @param bp The byte (char*) pointer + * @return The offset (0, 1, 2, or 3) + */ +#define SCC_BYTE_OFFSET(bp) ((uint32_t)(bp) % sizeof(uint32_t)) + +/*! + * Converts (by rounding down) a byte pointer into a word pointer + * @param bp The byte (char*) pointer + * @return The word (uint32_t) as though it were an aligned (uint32_t*) + */ +#define SCC_WORD_PTR(bp) (((uint32_t)(bp)) & ~(sizeof(uint32_t)-1)) + +/*! + * Determine number of bytes in an SCC block + * + * @return Bytes / block + */ +#define SCC_BLOCK_SIZE_BYTES() scc_configuration.block_size_bytes + +/*! + * Maximum number of additional bytes which may be added in CRC+padding mode. + */ +#define PADDING_BUFFER_MAX_BYTES (CRC_SIZE_BYTES + sizeof(scc_block_padding)) + +/*! + * Shorthand (clearer, anyway) for number of bytes in a CRC. + */ +#define CRC_SIZE_BYTES (sizeof(crc_t)) + +/*! + * The polynomial used in CCITT-CRC calculation + */ +#define CRC_POLYNOMIAL 0x1021 + +/*! + * Calculate CRC on one byte of data + * + * @param[in,out] running_crc A value of type crc_t where CRC is kept. This + * must be an rvalue and an lvalue. + * @param[in] byte_value The byte (uint8_t, char) to be put in the CRC + * + * @return none + */ +#define CALC_CRC(byte_value,running_crc) { \ + uint8_t data; \ + data = (0xff&(byte_value)) ^ (running_crc >> 8); \ + running_crc = scc_crc_lookup_table[data] ^ (running_crc << 8); \ +} + +/*! Value of 'beginning of padding' marker in driver-provided padding */ +#define SCC_DRIVER_PAD_CHAR 0x80 + +/*! Name of the driver. Used (on Linux, anyway) when registering interrupts */ +#define SCC_DRIVER_NAME "scc" + +/* Port -- these symbols are defined in Linux 2.6 and later. They are defined + * here for backwards compatibility because this started life as a 2.4 + * driver, and as a guide to portation to other platforms. + */ + +#if !defined(LINUX_VERSION_CODE) || LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + +#define irqreturn_t void /* Return type of an interrupt handler */ + +#define IRQ_HANDLED /* Would be '1' for handled -- as in return IRQ_HANDLED; */ + +#define IRQ_NONE /* would be '0' for not handled -- as in return IRQ_NONE; */ + +#define IRQ_RETVAL(x) /* Return x==0 (not handled) or non-zero (handled) */ + +#endif /* LINUX earlier than 2.5 */ + +/* These are nice to have around */ +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE 1 +#endif + +/*! Provide a typedef for the CRC which can be used in encrypt/decrypt */ +typedef uint16_t crc_t; + +/*! Gives high-level view of state of the SCC */ +enum scc_status { + SCC_STATUS_INITIAL, /*!< State of driver before ever checking */ + SCC_STATUS_CHECKING, /*!< Transient state while driver loading */ + SCC_STATUS_UNIMPLEMENTED, /*!< SCC is non-existent or unuseable */ + SCC_STATUS_OK, /*!< SCC is in Secure or Default state */ + SCC_STATUS_FAILED /*!< In Failed state */ +}; + +/*! + * Information about a key slot. + */ +struct scc_key_slot { + uint64_t owner_id; /*!< Access control value. */ + uint32_t length; /*!< Length of value in slot. */ + uint32_t offset; /*!< Offset of value from start of each RAM. */ + uint32_t status; /*!< 0 = unassigned, 1 = assigned. */ +}; + +/* Forward-declare a number routines which are not part of user api */ +static int scc_init(void); +static void scc_cleanup(void); + +/* Forward defines of internal functions */ +OS_DEV_ISR(scc_irq); +/*! Perform callbacks registered by #scc_monitor_security_failure(). + * + * Make sure callbacks only happen once... Since there may be some reason why + * the interrupt isn't generated, this routine could be called from base(task) + * level. + * + * One at a time, go through #scc_callbacks[] and call any non-null pointers. + */ +static void scc_perform_callbacks(void); +static uint32_t copy_to_scc(const uint8_t * from, uint32_t to, + unsigned long count_bytes, uint16_t * crc); +static uint32_t copy_from_scc(const uint32_t from, uint8_t * to, + unsigned long count_bytes, uint16_t * crc); +static scc_return_t scc_strip_padding(uint8_t * from, + unsigned *count_bytes_stripped); +static uint32_t scc_update_state(void); +static void scc_init_ccitt_crc(void); +static uint32_t scc_grab_config_values(void); +static int setup_interrupt_handling(void); +/*! + * Perform an encryption on the input. If @c verify_crc is true, a CRC must be + * calculated on the plaintext, and appended, with padding, before computing + * the ciphertext. + * + * @param[in] count_in_bytes Count of bytes of plaintext + * @param[in] data_in Pointer to the plaintext + * @param[in] scm_control Bit values for the SCM_CONTROL register + * @param[in,out] data_out Pointer for storing ciphertext + * @param[in] add_crc Flag for computing CRC - 0 no, else yes + * @param[in,out] count_out_bytes Number of bytes available at @c data_out + */ +static scc_return_t scc_encrypt(uint32_t count_in_bytes, + const uint8_t * data_in, + uint32_t scm_control, uint8_t * data_out, + int add_crc, unsigned long *count_out_bytes); + +/*! + * Perform a decryption on the input. If @c verify_crc is true, the last block + * (maybe the two last blocks) is special - it should contain a CRC and + * padding. These must be stripped and verified. + * + * @param[in] count_in_bytes Count of bytes of ciphertext + * @param[in] data_in Pointer to the ciphertext + * @param[in] scm_control Bit values for the SCM_CONTROL register + * @param[in,out] data_out Pointer for storing plaintext + * @param[in] verify_crc Flag for running CRC - 0 no, else yes + * @param[in,out] count_out_bytes Number of bytes available at @c data_out + + */ +static scc_return_t scc_decrypt(uint32_t count_in_bytes, + const uint8_t * data_in, + uint32_t scm_control, uint8_t * data_out, + int verify_crc, unsigned long *count_out_bytes); + +static void scc_wait_completion(void); +static int is_cipher_done(void); +static scc_return_t check_register_accessible(uint32_t offset, + uint32_t smn_status, + uint32_t scm_status); +static scc_return_t check_register_offset(uint32_t offset); + +#ifdef SCC_REGISTER_DEBUG +static uint32_t dbg_scc_read_register(uint32_t offset); +static void dbg_scc_write_register(uint32_t offset, uint32_t value); +#endif + +/* For Linux kernel, export the API functions to other kernel modules */ +EXPORT_SYMBOL(scc_get_configuration); +EXPORT_SYMBOL(scc_zeroize_memories); +EXPORT_SYMBOL(scc_crypt); +EXPORT_SYMBOL(scc_set_sw_alarm); +EXPORT_SYMBOL(scc_monitor_security_failure); +EXPORT_SYMBOL(scc_stop_monitoring_security_failure); +EXPORT_SYMBOL(scc_read_register); +EXPORT_SYMBOL(scc_write_register); +EXPORT_SYMBOL(scc_alloc_slot); +EXPORT_SYMBOL(scc_dealloc_slot); +EXPORT_SYMBOL(scc_load_slot); +EXPORT_SYMBOL(scc_encrypt_slot); +EXPORT_SYMBOL(scc_decrypt_slot); +EXPORT_SYMBOL(scc_get_slot_info); + +/* Tell Linux where to invoke driver at boot/module load time */ +module_init(scc_init); +/* Tell Linux where to invoke driver on module unload */ +module_exit(scc_cleanup); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Device Driver for SCC (SMN/SCM)"); + +#endif /* __MXC_SCC_INTERNALS_H__ */ diff -urN linux-2.6.26/drivers/mxc/security/mxc_sec_mod.c linux-2.6.26-lab126/drivers/mxc/security/mxc_sec_mod.c --- linux-2.6.26/drivers/mxc/security/mxc_sec_mod.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/mxc_sec_mod.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,67 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include + +static int __init mxc_sec_mod_init(void) +{ + printk(KERN_INFO "SEC: mxc_sec_mod_init() called \n"); + return 0; +} + +static void __exit mxc_sec_mod_cleanup(void) +{ + printk(KERN_INFO "SEC: mxc_sec_mod_cleanup() called \n"); +} + +#ifndef CONFIG_ARCH_MX3 +#ifdef CONFIG_MXC_SECURITY_HAC +/* Export Symbol of HACC */ +EXPORT_SYMBOL(hac_hash_data); +EXPORT_SYMBOL(hac_hashing_status); +EXPORT_SYMBOL(hac_get_status); +EXPORT_SYMBOL(hac_stop); +EXPORT_SYMBOL(hac_hash_result); +EXPORT_SYMBOL(hac_swrst); +EXPORT_SYMBOL(hac_burst_mode); +EXPORT_SYMBOL(hac_burst_read); +#ifdef CONFIG_PM +EXPORT_SYMBOL(hac_suspend); +EXPORT_SYMBOL(hac_resume); +#endif +#endif +#endif + +#ifdef CONFIG_MXC_SECURITY_RTIC +/* Export Symbol of RTIC */ +EXPORT_SYMBOL(rtic_init); +EXPORT_SYMBOL(rtic_configure_mode); +EXPORT_SYMBOL(rtic_configure_mem_blk); +EXPORT_SYMBOL(rtic_start_hash); +EXPORT_SYMBOL(rtic_get_status); +EXPORT_SYMBOL(rtic_get_control); +EXPORT_SYMBOL(rtic_configure_interrupt); +EXPORT_SYMBOL(rtic_hash_result); +EXPORT_SYMBOL(rtic_hash_write); +EXPORT_SYMBOL(rtic_get_faultaddress); +EXPORT_SYMBOL(rtic_dma_burst_read); +EXPORT_SYMBOL(rtic_hash_once_dma_throttle); +EXPORT_SYMBOL(rtic_dma_delay); +EXPORT_SYMBOL(rtic_wd_timer); +EXPORT_SYMBOL(rtic_sw_reset); +EXPORT_SYMBOL(rtic_clr_irq); +#endif + +module_init(mxc_sec_mod_init); +module_exit(mxc_sec_mod_cleanup); diff -urN linux-2.6.26/drivers/mxc/security/rng/Makefile linux-2.6.26-lab126/drivers/mxc/security/rng/Makefile --- linux-2.6.26/drivers/mxc/security/rng/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/Makefile 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,35 @@ +# Makefile for the Linux RNG Driver +# +# This makefile works within a kernel driver tree + + # Makefile for rng_driver + + +# Possible configurable paramters +CFG_RNG += -DRNGA_MAX_REQUEST_SIZE=32 + +#DBG_RNGA = -DRNGA_DEBUG +#DBG_RNGA += -DRNGA_REGISTER_DEBUG +#DBG_RNGA += -DRNGA_ENTROPY_DEBUG + +EXTRA_CFLAGS = -DLINUX_KERNEL $(CFG_RNG) $(DBG_RNG) + + +ifeq ($(CONFIG_MXC_RNG_TEST_DRIVER),y) +EXTRA_CFLAGS += -DRNG_REGISTER_PEEK_POKE +endif +ifeq ($(CONFIG_RNG_DEBUG),y) +EXTRA_CFLAGS += -DDEBUG +endif + + +EXTRA_CFLAGS += -Idrivers/mxc/security/rng/include -Idrivers/mxc/security/sahara2/include + +obj-$(CONFIG_MXC_SECURITY_RNG) += shw.o +#shw-objs := shw_driver.o shw_memory_mapper.o ../sahara2/fsl_shw_keystore.o +shw-objs := shw_driver.o shw_memory_mapper.o ../sahara2/fsl_shw_keystore.o \ + fsl_shw_sym.o fsl_shw_wrap.o shw_dryice.o des_key.o \ + shw_hash.o shw_hmac.o + +obj-$(CONFIG_MXC_SECURITY_RNG) += rng.o +rng-objs := rng_driver.o diff -urN linux-2.6.26/drivers/mxc/security/rng/des_key.c linux-2.6.26-lab126/drivers/mxc/security/rng/des_key.c --- linux-2.6.26/drivers/mxc/security/rng/des_key.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/des_key.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,385 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +/*! + * @file des_key.c + * + * This file implements the function #fsl_shw_permute1_bytes(). + * + * The code was lifted from crypto++ v5.5.2, which is public domain code. The + * code to handle words instead of bytes was extensively modified from the byte + * version and then converted to handle one to three keys at once. + * + */ + +#include "shw_driver.h" +#ifdef DIAG_SECURITY_FUNC +#include "apihelp.h" +#endif + +#ifndef __KERNEL__ +#include +#include /* or whichever is proper for target arch */ +#endif + +#ifdef DEBUG +#undef DEBUG /* TEMPORARY */ +#endif + +#if defined(DEBUG) || defined(SELF_TEST) +static void DUMP_BYTES(const char *label, const uint8_t * data, int len) +{ + int i; + + printf("%s: ", label); + for (i = 0; i < len; i++) { + printf("%02X", data[i]); + if ((i % 8 == 0) && (i != 0)) { + printf("_"); /* key separator */ + } + } + printf("\n"); +} + +static void DUMP_WORDS(const char *label, const uint32_t * data, int len) +{ + int i, j; + + printf("%s: ", label); + /* Dump the words in reverse order, so that they are intelligible */ + for (i = len - 1; i >= 0; i--) { + for (j = 3; j >= 0; j--) { + uint32_t word = data[i]; + printf("%02X", (word >> ((j * 8)) & 0xff)); + if ((i != 0) && ((((i) * 4 + 5 + j) % 7) == 5)) + printf("_"); /* key separator */ + } + printf("|"); /* word separator */ + } + printf("\n"); +} +#else +#define DUMP_BYTES(label, data,len) +#define DUMP_WORDS(label, data,len) +#endif + +/*! + * permuted choice table (key) + * + * Note that this table has had one subtracted from each element so that the + * code doesn't have to do it. + */ +static const uint8_t pc1[] = { + 56, 48, 40, 32, 24, 16, 8, + 0, 57, 49, 41, 33, 25, 17, + 9, 1, 58, 50, 42, 34, 26, + 18, 10, 2, 59, 51, 43, 35, + 62, 54, 46, 38, 30, 22, 14, + 6, 61, 53, 45, 37, 29, 21, + 13, 5, 60, 52, 44, 36, 28, + 20, 12, 4, 27, 19, 11, 3, +}; + +/*! bit 0 is left-most in byte */ +static const int bytebit[] = { + 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 +}; + +/*! + * Convert a 3-key 3DES key into the first-permutation 168-bit version. + * + * This is the format of the input key: + * + * @verbatim + BIT: |191 128|127 64|63 0| + BYTE: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | + KEY: | 0 | 1 | 2 | + @endverbatim + * + * This is the format of the output key: + * + * @verbatim + BIT: |167 112|111 56|55 0| + BYTE: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | + KEY: | 1 | 2 | 3 | + @endverbatim + * + * @param[in] key bytes of 3DES key + * @param[out] permuted_key 21 bytes of permuted key + * @param[in] key_count How many DES keys (2 or 3) + */ +void fsl_shw_permute1_bytes(const uint8_t * key, uint8_t * permuted_key, + int key_count) +{ + int i; + int j; + int l; + int m; + + DUMP_BYTES("Input key", key, 8 * key_count); + + /* For each individual sub-key */ + for (i = 0; i < 3; i++) { + DUMP_BYTES("(key)", key, 8); + memset(permuted_key, 0, 7); + /* For each bit of key */ + for (j = 0; j < 56; j++) { /* convert pc1 to bits of key */ + l = pc1[j]; /* integer bit location */ + m = l & 07; /* find bit */ + permuted_key[j >> 3] |= (((key[l >> 3] & /* find which key byte l is in */ + bytebit[m]) /* and which bit of that byte */ + ? 0x80 : 0) >> (j % 8)); /* and store 1-bit result */ + } + switch (i) { + case 0: + if (key_count != 1) + key += 8; /* move on to second key */ + break; + case 1: + if (key_count == 2) + key -= 8; /* go back to first key */ + else if (key_count == 3) + key += 8; /* move on to third key */ + break; + default: + break; + } + permuted_key += 7; + } + DUMP_BYTES("Output key (bytes)", permuted_key - 21, 21); +} + +#ifdef SELF_TEST +const uint8_t key1_in[] = { + /* FE01FE01FE01FE01_01FE01FE01FE01FE_FEFE0101FEFE0101 */ + 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, + 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, + 0xFE, 0xFE, 0x01, 0x01, 0xFE, 0xFE, 0x01, 0x01 +}; + +const uint32_t key1_word_in[] = { + 0xFE01FE01, 0xFE01FE01, + 0x01FE01FE, 0x01FE01FE, + 0xFEFE0101, 0xFEFE0101 +}; + +uint8_t exp_key1_out[] = { + 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33 +}; + +uint32_t exp_word_key1_out[] = { + 0x33333333, 0xAA333333, 0xAAAAAAAA, 0x5555AAAA, + 0x55555555, 0x00000055, +}; + +const uint8_t key2_in[] = { + 0xEF, 0x10, 0xBB, 0xA4, 0x23, 0x49, 0x42, 0x58, + 0x01, 0x28, 0x01, 0x4A, 0x10, 0xE4, 0x03, 0x59, + 0xFE, 0x84, 0x30, 0x29, 0x8E, 0xF1, 0x10, 0x5A +}; + +const uint32_t key2_word_in[] = { + 0xEF10BBA4, 0x23494258, + 0x0128014A, 0x10E40359, + 0xFE843029, 0x8EF1105A +}; + +uint8_t exp_key2_out[] = { + 0x0D, 0xE1, 0x1D, 0x85, 0x50, 0x9A, 0x56, 0x20, + 0xA8, 0x22, 0x94, 0x82, 0x08, 0xA0, 0x33, 0xA1, + 0x2D, 0xE9, 0x11, 0x39, 0x95 +}; + +uint32_t exp_word_key2_out[] = { + 0xE9113995, 0xA033A12D, 0x22948208, 0x9A5620A8, + 0xE11D8550, 0x0000000D +}; + +const uint8_t key3_in[] = { + 0x3F, 0xE9, 0x49, 0x4B, 0x67, 0x57, 0x07, 0x3C, + 0x89, 0x77, 0x73, 0x0C, 0xA0, 0x05, 0x41, 0x69, + 0xB3, 0x7C, 0x98, 0xD8, 0xC9, 0x35, 0x57, 0x19 +}; + +const uint32_t key3_word_in[] = { + 0xEF10BBA4, 0x23494258, + 0x0128014A, 0x10E40359, + 0xFE843029, 0x8EF1105A +}; + +uint8_t exp_key3_out[] = { + 0x02, 0x3E, 0x93, 0xA7, 0x9F, 0x18, 0xF1, 0x11, + 0xC6, 0x96, 0x00, 0x62, 0xA8, 0x96, 0x02, 0x3E, + 0x93, 0xA7, 0x9F, 0x18, 0xF1 +}; + +uint32_t exp_word_key3_out[] = { + 0xE9113995, 0xA033A12D, 0x22948208, 0x9A5620A8, + 0xE11D8550, 0x0000000D +}; + +const uint8_t key4_in[] = { + 0x3F, 0xE9, 0x49, 0x4B, 0x67, 0x57, 0x07, 0x3C, + 0x89, 0x77, 0x73, 0x0C, 0xA0, 0x05, 0x41, 0x69, +}; + +const uint32_t key4_word_in[] = { + 0xEF10BBA4, 0x23494258, + 0x0128014A, 0x10E40359, + 0xFE843029, 0x8EF1105A +}; + +const uint8_t key5_in[] = { + 0x3F, 0xE9, 0x49, 0x4B, 0x67, 0x57, 0x07, 0x3C, + 0x89, 0x77, 0x73, 0x0C, 0xA0, 0x05, 0x41, 0x69, + 0x3F, 0xE9, 0x49, 0x4B, 0x67, 0x57, 0x07, 0x3C, +}; + +uint8_t exp_key4_out[] = { + 0x0D, 0xE1, 0x1D, 0x85, 0x50, 0x9A, 0x56, 0x20, + 0xA8, 0x22, 0x94, 0x82, 0x08, 0xA0, 0x33, 0xA1, + 0x2D, 0xE9, 0x11, 0x39, 0x95 +}; + +uint32_t exp_word_key4_out[] = { + 0xE9113995, 0xA033A12D, 0x22948208, 0x9A5620A8, + 0xE11D8550, 0x0000000D +}; + +const uint8_t key6_in[] = { + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 +}; + +uint8_t exp_key6_out[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +uint32_t exp_word_key6_out[] = { + 0x00000000, 0x0000000, 0x0000000, 0x00000000, + 0x00000000, 0x0000000 +}; + +const uint8_t key7_in[] = { + /* 01FE01FE01FE01FE_FE01FE01FE01FE01_0101FEFE0101FEFE */ + /* 0101FEFE0101FEFE_FE01FE01FE01FE01_01FE01FE01FE01FE */ + 0x01, 0x01, 0xFE, 0xFE, 0x01, 0x01, 0xFE, 0xFE, + 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, + 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, +}; + +uint8_t exp_key7_out[] = { + 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x55, + 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa +}; + +uint32_t exp_word_key7_out[] = { + 0xcccccccc, 0x55cccccc, 0x55555555, 0xaaaa5555, + 0xaaaaaaaa, 0x000000aa +}; + +int run_test(const uint8_t * key_in, + const int key_count, + const uint32_t * key_word_in, + const uint8_t * exp_bytes_key_out, + const uint32_t * exp_word_key_out) +{ + uint8_t key_out[22]; + uint32_t word_key_out[6]; + int failed = 0; + + memset(key_out, 0x42, 22); + fsl_shw_permute1_bytes(key_in, key_out, key_count); + if (memcmp(key_out, exp_bytes_key_out, 21) != 0) { + printf("bytes_to_bytes: ERROR: \n"); + DUMP_BYTES("key_in", key_in, 8 * key_count); + DUMP_BYTES("key_out", key_out, 21); + DUMP_BYTES("exp_out", exp_bytes_key_out, 21); + failed |= 1; + } else if (key_out[21] != 0x42) { + printf("bytes_to_bytes: ERROR: Buffer overflow 0x%02x\n", + (int)key_out[21]); + } else { + printf("bytes_to_bytes: OK\n"); + } +#if 0 + memset(word_key_out, 0x42, 21); + fsl_shw_permute1_bytes_to_words(key_in, word_key_out, key_count); + if (memcmp(word_key_out, exp_word_key_out, 21) != 0) { + printf("bytes_to_words: ERROR: \n"); + DUMP_BYTES("key_in", key_in, 8 * key_count); + DUMP_WORDS("key_out", word_key_out, 6); + DUMP_WORDS("exp_out", exp_word_key_out, 6); + failed |= 1; + } else { + printf("bytes_to_words: OK\n"); + } + + if (key_word_in != NULL) { + memset(word_key_out, 0x42, 21); + fsl_shw_permute1_words_to_words(key_word_in, word_key_out); + if (memcmp(word_key_out, exp_word_key_out, 21) != 0) { + printf("words_to_words: ERROR: \n"); + DUMP_BYTES("key_in", key_in, 24); + DUMP_WORDS("key_out", word_key_out, 6); + DUMP_WORDS("exp_out", exp_word_key_out, 6); + failed |= 1; + } else { + printf("words_to_words: OK\n"); + } + } +#endif + + return failed; +} /* end fn run_test */ + +int main() +{ + int failed = 0; + + printf("key1\n"); + failed |= + run_test(key1_in, 3, key1_word_in, exp_key1_out, exp_word_key1_out); + printf("\nkey2\n"); + failed |= + run_test(key2_in, 3, key2_word_in, exp_key2_out, exp_word_key2_out); + printf("\nkey3\n"); + failed |= run_test(key3_in, 3, NULL, exp_key3_out, exp_word_key3_out); + printf("\nkey4\n"); + failed |= run_test(key4_in, 2, NULL, exp_key4_out, exp_word_key4_out); + printf("\nkey5\n"); + failed |= run_test(key5_in, 3, NULL, exp_key4_out, exp_word_key4_out); + printf("\nkey6 - 3\n"); + failed |= run_test(key6_in, 3, NULL, exp_key6_out, exp_word_key6_out); + printf("\nkey6 - 2\n"); + failed |= run_test(key6_in, 2, NULL, exp_key6_out, exp_word_key6_out); + printf("\nkey6 - 1\n"); + failed |= run_test(key6_in, 1, NULL, exp_key6_out, exp_word_key6_out); + printf("\nkey7\n"); + failed |= run_test(key7_in, 3, NULL, exp_key7_out, exp_word_key7_out); + printf("\n"); + + if (failed != 0) { + printf("TEST FAILED\n"); + } + return failed; +} + +#endif /* SELF_TEST */ diff -urN linux-2.6.26/drivers/mxc/security/rng/fsl_shw_hash.c linux-2.6.26-lab126/drivers/mxc/security/rng/fsl_shw_hash.c --- linux-2.6.26/drivers/mxc/security/rng/fsl_shw_hash.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/fsl_shw_hash.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,84 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +/*! + * @file fsl_shw_hash.c + * + * This file implements Cryptographic Hashing functions of the FSL SHW API + * for Sahara. This does not include HMAC. + */ + +#include "shw_driver.h" + +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-005 */ +/*! + * Hash a stream of data with a cryptographic hash algorithm. + * + * The flags in the @a hash_ctx control the operation of this function. + * + * Hashing functions work on 64 octets of message at a time. Therefore, when + * any partial hashing of a long message is performed, the message @a length of + * each segment must be a multiple of 64. When ready to + * #FSL_HASH_FLAGS_FINALIZE the hash, the @a length may be any value. + * + * With the #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_FINALIZE flags on, a + * one-shot complete hash, including padding, will be performed. The @a length + * may be any value. + * + * The first octets of a data stream can be hashed by setting the + * #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_SAVE flags. The @a length must be + * a multiple of 64. + * + * The flag #FSL_HASH_FLAGS_LOAD is used to load a context previously saved by + * #FSL_HASH_FLAGS_SAVE. The two in combination will allow a (multiple-of-64 + * octets) 'middle sequence' of the data stream to be hashed with the + * beginning. The @a length must again be a multiple of 64. + * + * Since the flag #FSL_HASH_FLAGS_LOAD is used to load a context previously + * saved by #FSL_HASH_FLAGS_SAVE, the #FSL_HASH_FLAGS_LOAD and + * #FSL_HASH_FLAGS_FINALIZE flags, used together, can be used to finish the + * stream. The @a length may be any value. + * + * If the user program wants to do the padding for the hash, it can leave off + * the #FSL_HASH_FLAGS_FINALIZE flag. The @a length must then be a multiple of + * 64 octets. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] hash_ctx Hashing algorithm and state of the cipher. + * @param msg Pointer to the data to be hashed. + * @param length Length, in octets, of the @a msg. + * @param[out] result If not null, pointer to where to store the hash + * digest. + * @param result_len Number of octets to store in @a result. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_hash(fsl_shw_uco_t * user_ctx, + fsl_shw_hco_t * hash_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + /* Unused */ + (void)user_ctx; + (void)hash_ctx; + (void)msg; + (void)length; + (void)result; + (void)result_len; + + return ret; +} diff -urN linux-2.6.26/drivers/mxc/security/rng/fsl_shw_hmac.c linux-2.6.26-lab126/drivers/mxc/security/rng/fsl_shw_hmac.c --- linux-2.6.26/drivers/mxc/security/rng/fsl_shw_hmac.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/fsl_shw_hmac.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,83 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +/*! + * @file fsl_shw_hmac.c + * + * This file implements Hashed Message Authentication Code functions of the FSL + * SHW API. + */ + +#include "shw_driver.h" + +/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-001 */ +/*! + * Get the precompute information + * + * + * @param user_ctx + * @param key_info + * @param hmac_ctx + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_hmac_precompute(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx) +{ + fsl_shw_return_t status = FSL_RETURN_ERROR_S; + + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)hmac_ctx; + + return status; +} + +/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-002 */ +/*! + * Get the hmac + * + * + * @param user_ctx Info for acquiring memory + * @param key_info + * @param hmac_ctx + * @param msg + * @param length + * @param result + * @param result_len + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_hmac(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len) +{ + fsl_shw_return_t status = FSL_RETURN_ERROR_S; + + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)hmac_ctx; + (void)msg; + (void)length; + (void)result; + (void)result_len; + + return status; +} diff -urN linux-2.6.26/drivers/mxc/security/rng/fsl_shw_rand.c linux-2.6.26-lab126/drivers/mxc/security/rng/fsl_shw_rand.c --- linux-2.6.26/drivers/mxc/security/rng/fsl_shw_rand.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/fsl_shw_rand.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,122 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +/*! + * @file fsl_shw_rand.c + * + * This file implements Random Number Generation functions of the FSL SHW API + * in USER MODE for talking to a standalone RNGA/RNGC device driver. + * + * It contains the fsl_shw_get_random() and fsl_shw_add_entropy() functions. + * + * These routines will build a request block and pass it to the SHW driver. + */ + +#include +#include +#include +#include +#include +#include + +#ifdef FSL_DEBUG +#include +#include +#include +#endif /* FSL_DEBUG */ + +#include "shw_driver.h" + +extern fsl_shw_return_t validate_uco(fsl_shw_uco_t * uco); + +#if defined(FSL_HAVE_RNGA) || defined(FSL_HAVE_RNGB) || defined(FSL_HAVE_RNGC) + +/* REQ-S2LRD-PINTFC-API-BASIC-RNG-002 */ +fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + /* perform a sanity check / update uco */ + ret = validate_uco(user_ctx); + if (ret == FSL_RETURN_OK_S) { + struct get_random_req *req = malloc(sizeof(*req)); + + if (req == NULL) { + ret = FSL_RETURN_NO_RESOURCE_S; + } else { + + init_req(&req->hdr, user_ctx); + req->size = length; + req->random = data; + + ret = + send_req(SHW_USER_REQ_GET_RANDOM, &req->hdr, + user_ctx); + } + } + + return ret; +} + +fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + /* perform a sanity check on the uco */ + ret = validate_uco(user_ctx); + if (ret == FSL_RETURN_OK_S) { + struct add_entropy_req *req = malloc(sizeof(*req)); + + if (req == NULL) { + ret = FSL_RETURN_NO_RESOURCE_S; + } else { + init_req(&req->hdr, user_ctx); + req->size = length; + req->entropy = data; + + ret = + send_req(SHW_USER_REQ_ADD_ENTROPY, &req->hdr, + user_ctx); + } + } + + return ret; +} + +#else /* no H/W RNG block */ + +fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data) +{ + + (void)user_ctx; + (void)length; + (void)data; + + return FSL_RETURN_ERROR_S; +} + +fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data) +{ + + (void)user_ctx; + (void)length; + (void)data; + + return FSL_RETURN_ERROR_S; +} +#endif diff -urN linux-2.6.26/drivers/mxc/security/rng/fsl_shw_sym.c linux-2.6.26-lab126/drivers/mxc/security/rng/fsl_shw_sym.c --- linux-2.6.26/drivers/mxc/security/rng/fsl_shw_sym.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/fsl_shw_sym.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,317 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +/*! + * @file fsl_shw_sym.c + * + * This file implements the Symmetric Cipher functions of the FSL SHW API. Its + * features are limited to what can be done with the combination of SCC and + * DryIce. + */ +#include "fsl_platform.h" +#include "shw_driver.h" + +#if defined(__KERNEL__) && defined(FSL_HAVE_DRYICE) + +#include "../dryice.h" +#include +#ifdef DIAG_SECURITY_FUNC +#include "apihelp.h" +#endif + +#include + +#define SYM_DECRYPT 0 +#define SYM_ENCRYPT 1 + +extern fsl_shw_return_t shw_convert_pf_key(fsl_shw_pf_key_t shw_pf_key, + di_key_t * di_keyp); + +/*! 'Initial' IV for presence of FSL_SYM_CTX_LOAD flag */ +static uint8_t zeros[8] = { + 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/*! + * Common function for encryption and decryption + * + * This is for a device with DryIce. + * + * A key must either refer to a 'pure' HW key, or, if PRG or PRG_IIM, + * established, then that key will be programmed. Then, the HW_key in the + * object will be selected. After this setup, the ciphering will be performed + * by calling the SCC driver.. + * + * The function 'releases' the reservations before it completes. + */ +fsl_shw_return_t do_symmetric(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + int encrypt, + uint32_t length, + const uint8_t * in, uint8_t * out) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + int key_selected = 0; + uint8_t *iv = NULL; + unsigned long count_out = length; + di_key_t di_key = DI_KEY_PK; /* default for user key */ + di_key_t di_key_orig; /* currently selected key */ + di_key_t selected_key = -1; + di_return_t di_code; + scc_return_t scc_code; + + /* For now, only blocking mode calls are supported */ + if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + /* No software keys allowed */ + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + ret = FSL_RETURN_BAD_FLAG_S; + } + + /* The only algorithm the SCC supports */ + if (key_info->algorithm != FSL_KEY_ALG_TDES) { + ret = FSL_RETURN_BAD_ALGORITHM_S; + goto out; + } + + /* Validate key length */ + if ((key_info->key_length != 16) + && (key_info->key_length != 21) + && (key_info->key_length != 24)) { + ret = FSL_RETURN_BAD_KEY_LENGTH_S; + goto out; + } + + /* Validate data is multiple of DES/TDES block */ + if ((length & 7) != 0) { + ret = FSL_RETURN_BAD_DATA_LENGTH_S; + goto out; + } + + /* Do some setup according to where the key lives */ + if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) { + if ((key_info->pf_key != FSL_SHW_PF_KEY_PRG) + && (key_info->pf_key != FSL_SHW_PF_KEY_IIM_PRG)) { + ret = FSL_RETURN_ERROR_S; + } + } else if (key_info->flags & FSL_SKO_KEY_PRESENT) { + ret = FSL_RETURN_BAD_FLAG_S; + } else if (key_info->flags & FSL_SKO_KEY_SELECT_PF_KEY) { + /* + * No key present or established, just refer to HW + * as programmed. + */ + } else { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + /* Now make proper selection */ + ret = shw_convert_pf_key(key_info->pf_key, &di_key); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + /* Determine the current DI key selection */ + di_code = dryice_check_key(&di_key_orig); + if (di_code != DI_SUCCESS) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Could not save current DI key state: %s\n", + di_error_string(di_code)); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + + /* If the requested DI key is already selected, don't re-select it. */ + if (di_key != di_key_orig) { + di_code = dryice_select_key(di_key, 0); + if (di_code != DI_SUCCESS) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Error from select_key: %s\n", + di_error_string(di_code)); +#endif + ret = FSL_RETURN_INTERNAL_ERROR_S; + goto out; + } + } + key_selected = 1; + + /* Verify that we are using the key we want */ + di_code = dryice_check_key(&selected_key); + if (di_code != DI_SUCCESS) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Error from check_key: %s\n", + di_error_string(di_code)); +#endif + ret = FSL_RETURN_INTERNAL_ERROR_S; + goto out; + } + + if (di_key != selected_key) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Wrong key in use: %d instead of %d\n\n", + selected_key, di_key); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + + if (sym_ctx->mode == FSL_SYM_MODE_CBC) { + if ((sym_ctx->flags & FSL_SYM_CTX_LOAD) + && !(sym_ctx->flags & FSL_SYM_CTX_INIT)) { + iv = sym_ctx->context; + } else if ((sym_ctx->flags & FSL_SYM_CTX_INIT) + && !(sym_ctx->flags & FSL_SYM_CTX_LOAD)) { + iv = zeros; + } else { + /* Exactly one must be set! */ + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + } + + /* Now run the data through the SCC */ + scc_code = scc_crypt(length, in, iv, + encrypt ? SCC_ENCRYPT : SCC_DECRYPT, + (sym_ctx->mode == FSL_SYM_MODE_ECB) + ? SCC_ECB_MODE : SCC_CBC_MODE, + SCC_VERIFY_MODE_NONE, out, &count_out); + if (scc_code != SCC_RET_OK) { + ret = FSL_RETURN_INTERNAL_ERROR_S; +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("scc_code from scc_crypt() is %d\n", scc_code); +#endif + goto out; + } + + if ((sym_ctx->mode == FSL_SYM_MODE_CBC) + && (sym_ctx->flags & FSL_SYM_CTX_SAVE)) { + /* Save the context for the caller */ + if (encrypt) { + /* Last ciphertext block ... */ + memcpy(sym_ctx->context, out + length - 8, 8); + } else { + /* Last ciphertext block ... */ + memcpy(sym_ctx->context, in + length - 8, 8); + } + } + + ret = FSL_RETURN_OK_S; + + out: + if (key_selected) { + (void)dryice_release_key_selection(); + } + + return ret; +} + +EXPORT_SYMBOL(fsl_shw_symmetric_encrypt); +/*! + * Compute symmetric encryption + * + * + * @param user_ctx + * @param key_info + * @param sym_ctx + * @param length + * @param pt + * @param ct + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_symmetric_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * pt, uint8_t * ct) +{ + fsl_shw_return_t ret; + + ret = do_symmetric(user_ctx, key_info, sym_ctx, SYM_ENCRYPT, + length, pt, ct); + + return ret; +} + +EXPORT_SYMBOL(fsl_shw_symmetric_decrypt); +/*! + * Compute symmetric decryption + * + * + * @param user_ctx + * @param key_info + * @param sym_ctx + * @param length + * @param pt + * @param ct + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_symmetric_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * ct, uint8_t * pt) +{ + fsl_shw_return_t ret; + + ret = do_symmetric(user_ctx, key_info, sym_ctx, SYM_DECRYPT, + length, ct, pt); + + return ret; +} + +#else /* __KERNEL__ && DRYICE */ + +fsl_shw_return_t fsl_shw_symmetric_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * pt, uint8_t * ct) +{ + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)sym_ctx; + (void)length; + (void)pt; + (void)ct; + + return FSL_RETURN_ERROR_S; +} + +fsl_shw_return_t fsl_shw_symmetric_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * ct, uint8_t * pt) +{ + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)sym_ctx; + (void)length; + (void)ct; + (void)pt; + + return FSL_RETURN_ERROR_S; +} + +#endif /* __KERNEL__ and DRYICE */ diff -urN linux-2.6.26/drivers/mxc/security/rng/fsl_shw_wrap.c linux-2.6.26-lab126/drivers/mxc/security/rng/fsl_shw_wrap.c --- linux-2.6.26/drivers/mxc/security/rng/fsl_shw_wrap.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/fsl_shw_wrap.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,1301 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file fsl_shw_wrap.c + * + * This file implements Key-Wrap (Black Key) and Key Establishment functions of + * the FSL SHW API for the SHW (non-SAHARA) driver. + * + * This is the Black Key information: + * + *
    + *
  • Ownerid is an 8-byte, user-supplied, value to keep KEY + * confidential.
    • + *
  • KEY is a 1-32 byte value which starts in SCC RED RAM before + * wrapping, and ends up there on unwrap. Length is limited because of + * size of SCC1 RAM.
    • + *
  • KEY' is the encrypted KEY
    • + *
  • LEN is a 1-byte (for now) byte-length of KEY
    • + *
  • ALG is a 1-byte value for the algorithm which which the key is + * associated. Values are defined by the FSL SHW API
    • + *
  • FLAGS is a 1-byte value contain information like "this key is for + * software" (TBD)
    • + *
  • Ownerid, LEN, and ALG come from the user's "key_info" object, as does + * the slot number where KEY already is/will be.
    • + *
  • T is a Nonce
    • + *
  • T' is the encrypted T
    • + *
  • KEK is a Key-Encryption Key for the user's Key
    • + *
  • ICV is the "Integrity Check Value" for the wrapped key
    • + *
  • Black Key is the string of bytes returned as the wrapped key
    • + *
  • Wrap Key is the user's choice for encrypting the nonce. One of + * the Fused Key, the Random Key, or the XOR of the two. + *
+ + + + + + + + + + + + + + + + + + +
BLACK_KEY =ICV | T' | LEN | ALG | + FLAGS | KEY'
 
To Wrap
T = RND()16 +
KEK=HASHsha256(T | + Ownerid)16
KEY'= + TDEScbc-enc(Key=KEK, Data=KEY, IV=Ownerid)
ICV=HMACsha256 + (Key=T, Data=Ownerid | LEN | ALG | FLAGS | KEY')16
T'=TDESecb-enc + (Key=Wrap_Key, IV=Ownerid, Data=T)
 
To Unwrap
T=TDESecb-dec + (Key=Wrap_Key, IV=Ownerid, Data=T')
ICV=HMACsha256 + (Key=T, Data=Ownerid | LEN | ALG | FLAGS | KEY')16
KEK=HASHsha256 + (T | Ownerid)16
KEY=TDEScbc-dec + (Key=KEK, Data=KEY', IV=Ownerid)
+ + * This code supports two types of keys: Software Keys and keys destined for + * (or residing in) the DryIce Programmed Key Register. + * + * Software Keys go to / from the keystore. + * + * PK keys go to / from the DryIce Programmed Key Register. + * + * This code only works on a platform with DryIce. "software" keys go into + * the keystore. "Program" keys go to the DryIce Programmed Key Register. + * As far as this code is concerned, the size of that register is 21 bytes, + * the size of a 3DES key with parity stripped. + * + * The maximum key size supported for wrapped/unwrapped keys depends upon + * LENGTH_LENGTH. Currently, it is one byte, so the maximum key size is + * 255 bytes. However, key objects cannot currently hold a key of this + * length, so a smaller key size is the max. + */ + +#include "fsl_platform.h" + +/* This code only works in kernel mode */ + +#include "shw_driver.h" +#ifdef DIAG_SECURITY_FUNC +#include "apihelp.h" +#endif + +#if defined(__KERNEL__) && defined(FSL_HAVE_DRYICE) + +#include "../dryice.h" +#include + +#include "portable_os.h" +#include "fsl_shw_keystore.h" + +#include + +#include "shw_hmac.h" +#include "shw_hash.h" + +#define ICV_LENGTH 16 +#define T_LENGTH 16 +#define KEK_LENGTH 21 +#define LENGTH_LENGTH 1 +#define ALGORITHM_LENGTH 1 +#define FLAGS_LENGTH 1 + +/* ICV | T' | LEN | ALG | FLAGS | KEY' */ +#define ICV_OFFSET 0 +#define T_PRIME_OFFSET (ICV_OFFSET + ICV_LENGTH) +#define LENGTH_OFFSET (T_PRIME_OFFSET + T_LENGTH) +#define ALGORITHM_OFFSET (LENGTH_OFFSET + LENGTH_LENGTH) +#define FLAGS_OFFSET (ALGORITHM_OFFSET + ALGORITHM_LENGTH) +#define KEY_PRIME_OFFSET (FLAGS_OFFSET + FLAGS_LENGTH) + +#define FLAGS_SW_KEY 0x01 + +#define LENGTH_PATCH 8 +#define LENGTH_PATCH_MASK (LENGTH_PATCH - 1) + +/*! rounded up from 168 bits to the next word size */ +#define HW_KEY_LEN_WORDS_BITS 192 + +/*! + * Round a key length up to the TDES block size + * + * @param len Length of key, in bytes + * + * @return Length rounded up, if necessary + */ +#define ROUND_LENGTH(len) \ +({ \ + uint32_t orig_len = len; \ + uint32_t new_len; \ + \ + if ((orig_len & LENGTH_PATCH_MASK) != 0) { \ + new_len = (orig_len + LENGTH_PATCH \ + - (orig_len & LENGTH_PATCH_MASK)); \ + } \ + else { \ + new_len = orig_len; \ + } \ + \ + new_len; \ +}) + +/* This is the system keystore object */ +extern fsl_shw_kso_t system_keystore; + +#ifdef DIAG_SECURITY_FUNC +static void dump(const char *name, const uint8_t * data, unsigned int len) +{ + os_printk("%s: ", name); + while (len > 0) { + os_printk("%02x ", (unsigned)*data++); + len--; + } + os_printk("\n"); +} +#endif + +/* + * For testing of the algorithm implementation,, the DO_REPEATABLE_WRAP flag + * causes the T_block to go into the T field during a wrap operation. This + * will make the black key value repeatable (for a given SCC secret key, or + * always if the default key is in use). + * + * Normally, a random sequence is used. + */ +#ifdef DO_REPEATABLE_WRAP +/*! + * Block of zeroes which is maximum Symmetric block size, used for + * initializing context register, etc. + */ +static uint8_t T_block[16] = { + 0x42, 0, 0, 0x42, 0x42, 0, 0, 0x42, + 0x42, 0, 0, 0x42, 0x42, 0, 0, 0x42 +}; +#endif + +EXPORT_SYMBOL(fsl_shw_establish_key); +EXPORT_SYMBOL(fsl_shw_read_key); +EXPORT_SYMBOL(fsl_shw_extract_key); +EXPORT_SYMBOL(fsl_shw_release_key); + +extern fsl_shw_return_t alloc_slot(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info); + +extern fsl_shw_return_t load_slot(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + const uint8_t * key); + +extern fsl_shw_return_t dealloc_slot(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info); + +/*! + * Initalialize SKO and SCCO used for T <==> T' cipher operation + * + * @param wrap_key Which wrapping key user wants + * @param key_info Key object for selecting wrap key + * @param wrap_ctx Sym Context object for doing the cipher op + */ +static inline void init_wrap_key(fsl_shw_pf_key_t wrap_key, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * wrap_ctx) +{ + fsl_shw_sko_init_pf_key(key_info, FSL_KEY_ALG_TDES, wrap_key); + fsl_shw_scco_init(wrap_ctx, FSL_KEY_ALG_TDES, FSL_SYM_MODE_ECB); +} + +/*! + * Insert descriptors to calculate ICV = HMAC(key=T, data=LEN|ALG|KEY') + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param T Location of nonce (length is T_LENGTH bytes) + * @param userid Location of userid/ownerid + * @param userid_len Length, in bytes of @c userid + * @param black_key Beginning of Black Key region + * @param key_length Number of bytes of key' there are in @c black_key + * @param[out] hmac Location to store ICV. Will be tagged "USES" so + * sf routines will not try to free it. + * + * @return A return code of type #fsl_shw_return_t. + */ +static fsl_shw_return_t calc_icv(const uint8_t * T, + const uint8_t * userid, + unsigned int userid_len, + const uint8_t * black_key, + uint32_t key_length, uint8_t * hmac) +{ + fsl_shw_return_t code; + shw_hmac_state_t hmac_state; + + /* Load up T as key for the HMAC */ + code = shw_hmac_init(&hmac_state, T, T_LENGTH); + if (code != FSL_RETURN_OK_S) { + goto out; + } + + /* Previous step loaded key; Now set up to hash the data */ + + /* Input - start with ownerid */ + code = shw_hmac_update(&hmac_state, userid, userid_len); + if (code != FSL_RETURN_OK_S) { + goto out; + } + + /* Still input - Append black-key fields len, alg, key' */ + code = shw_hmac_update(&hmac_state, + (void *)black_key + LENGTH_OFFSET, + (LENGTH_LENGTH + + ALGORITHM_LENGTH + + FLAGS_LENGTH + key_length)); + if (code != FSL_RETURN_OK_S) { + goto out; + } + + /* Output - computed ICV/HMAC */ + code = shw_hmac_final(&hmac_state, hmac, ICV_LENGTH); + if (code != FSL_RETURN_OK_S) { + goto out; + } + + out: + + return code; +} /* calc_icv */ + +/*! + * Compute and return the KEK (Key Encryption Key) from the inputs + * + * @param userid The user's 'secret' for the key + * @param userid_len Length, in bytes of @c userid + * @param T The nonce + * @param[out] kek Location to store the computed KEK. It will + * be 21 bytes long. + * + * @return the usual error code + */ +static fsl_shw_return_t calc_kek(const uint8_t * userid, + unsigned int userid_len, + const uint8_t * T, uint8_t * kek) +{ + fsl_shw_return_t code = FSL_RETURN_INTERNAL_ERROR_S; + shw_hash_state_t hash_state; + + code = shw_hash_init(&hash_state, FSL_HASH_ALG_SHA256); + if (code != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Hash init failed: %s\n", fsl_error_string(code)); +#endif + goto out; + } + + code = shw_hash_update(&hash_state, T, T_LENGTH); + if (code != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Hash for T failed: %s\n", + fsl_error_string(code)); +#endif + goto out; + } + + code = shw_hash_update(&hash_state, userid, userid_len); + if (code != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Hash for userid failed: %s\n", + fsl_error_string(code)); +#endif + goto out; + } + + code = shw_hash_final(&hash_state, kek, KEK_LENGTH); + if (code != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Could not extract kek: %s\n", + fsl_error_string(code)); +#endif + goto out; + } + +#if KEK_LENGTH != 21 + { + uint8_t permuted_kek[21]; + + fsl_shw_permute1_bytes(kek, permuted_kek, KEK_LENGTH / 8); + memcpy(kek, permuted_kek, 21); + memset(permuted_kek, 0, sizeof(permuted_kek)); + } +#endif + +#ifdef DIAG_SECURITY_FUNC + dump("kek", kek, 21); +#endif + + out: + + return code; +} /* end fn calc_kek */ + +/*! + * Validate user's wrap key selection + * + * @param wrap_key The user's desired wrapping key + */ +static fsl_shw_return_t check_wrap_key(fsl_shw_pf_key_t wrap_key) +{ + /* unable to use desired key */ + fsl_shw_return_t ret = FSL_RETURN_NO_RESOURCE_S; + + if ((wrap_key != FSL_SHW_PF_KEY_IIM) && + (wrap_key != FSL_SHW_PF_KEY_RND) && + (wrap_key != FSL_SHW_PF_KEY_IIM_RND)) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Invalid wrap_key in key wrap/unwrap attempt"); +#endif + goto out; + } + ret = FSL_RETURN_OK_S; + + out: + return ret; +} /* end fn check_wrap_key */ + +/*! + * Perform unwrapping of a black key into a RED slot + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] key_info The information about the key to be which will + * be unwrapped... key length, slot info, etc. + * @param black_key Encrypted key + * + * @return A return code of type #fsl_shw_return_t. + */ +static fsl_shw_return_t unwrap(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + const uint8_t * black_key) +{ + fsl_shw_return_t ret; + uint8_t hmac[ICV_LENGTH]; + uint8_t T[T_LENGTH]; + uint8_t kek[KEK_LENGTH + 20]; + int key_length = black_key[LENGTH_OFFSET]; + int rounded_key_length = ROUND_LENGTH(key_length); + uint8_t key[rounded_key_length]; + fsl_shw_sko_t t_key_info; + fsl_shw_scco_t t_key_ctx; + fsl_shw_sko_t kek_key_info; + fsl_shw_scco_t kek_ctx; + int unwrapping_sw_key = key_info->flags & FSL_SKO_KEY_SW_KEY; + int pk_needs_restoration = 0; /* bool */ + unsigned original_key_length = key_info->key_length; + int pk_was_held = 0; + uint8_t current_pk[21]; + di_return_t di_code; + + ret = check_wrap_key(user_ctx->wrap_key); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + if (black_key == NULL) { + ret = FSL_RETURN_ERROR_S; + goto out; + } +#ifdef DIAG_SECURITY_FUNC + dump("black", black_key, KEY_PRIME_OFFSET + key_length); +#endif + /* Validate SW flags to prevent misuse */ + if ((key_info->flags & FSL_SKO_KEY_SW_KEY) + && !(black_key[FLAGS_OFFSET] & FLAGS_SW_KEY)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + /* Compute T = 3des-dec-ecb(wrap_key, T') */ + init_wrap_key(user_ctx->wrap_key, &t_key_info, &t_key_ctx); + ret = fsl_shw_symmetric_decrypt(user_ctx, &t_key_info, &t_key_ctx, + T_LENGTH, + black_key + T_PRIME_OFFSET, T); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Recovery of nonce (T) failed"); +#endif /*DIAG_SECURITY_FUNC */ + goto out; + } + + /* Compute ICV = HMAC(T, ownerid | len | alg | flags | key' */ + ret = calc_icv(T, (uint8_t *) & key_info->userid, + sizeof(key_info->userid), + black_key, original_key_length, hmac); + + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Calculation of ICV failed"); +#endif /*DIAG_SECURITY_FUNC */ + goto out; + } +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Validating MAC of wrapped key"); +#endif + + /* Check computed ICV against value in Black Key */ + if (memcmp(black_key + ICV_OFFSET, hmac, ICV_LENGTH) != 0) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Computed ICV fails validation\n"); +#endif + ret = FSL_RETURN_AUTH_FAILED_S; + goto out; + } + + /* Compute KEK = SHA256(T | ownerid). */ + ret = calc_kek((uint8_t *) & key_info->userid, sizeof(key_info->userid), + T, kek); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + if (unwrapping_sw_key) { + di_code = dryice_get_programmed_key(current_pk, 8 * 21); + if (di_code != DI_SUCCESS) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Could not save current PK: %s\n", + di_error_string(di_code)); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + } + + /* + * "Establish" the KEK in the PK. If the PK was held and unwrapping a + * software key, then release it and try again, but remember that we need + * to leave it 'held' if we are unwrapping a software key. + * + * If the PK is held while we are unwrapping a key for the PK, then + * the user didn't call release, so gets an error. + */ + di_code = dryice_set_programmed_key(kek, 8 * 21, 0); + if ((di_code == DI_ERR_INUSE) && unwrapping_sw_key) { + /* Temporarily reprogram the PK out from under the user */ + pk_was_held = 1; + dryice_release_programmed_key(); + di_code = dryice_set_programmed_key(kek, 8 * 21, 0); + } + if (di_code != DI_SUCCESS) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Could not program KEK: %s\n", + di_error_string(di_code)); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + + if (unwrapping_sw_key) { + pk_needs_restoration = 1; + } + dryice_release_programmed_key(); /* Because of previous 'set' */ + + /* Compute KEY = TDES-decrypt(KEK, KEY') */ + fsl_shw_sko_init_pf_key(&kek_key_info, FSL_KEY_ALG_TDES, + FSL_SHW_PF_KEY_PRG); + fsl_shw_sko_set_key_length(&kek_key_info, KEK_LENGTH); + + fsl_shw_scco_init(&kek_ctx, FSL_KEY_ALG_TDES, FSL_SYM_MODE_CBC); + fsl_shw_scco_set_flags(&kek_ctx, FSL_SYM_CTX_LOAD); + fsl_shw_scco_set_context(&kek_ctx, (uint8_t *) & key_info->userid); +#ifdef DIAG_SECURITY_FUNC + dump("KEY'", black_key + KEY_PRIME_OFFSET, rounded_key_length); +#endif + ret = fsl_shw_symmetric_decrypt(user_ctx, &kek_key_info, &kek_ctx, + rounded_key_length, + black_key + KEY_PRIME_OFFSET, key); + if (ret != FSL_RETURN_OK_S) { + goto out; + } +#ifdef DIAG_SECURITY_FUNC + dump("KEY", key, original_key_length); +#endif + /* Now either put key into PK or into a slot */ + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + ret = load_slot(user_ctx, key_info, key); + } else { + /* + * Since we have just unwrapped a program key, it had + * to have been wrapped as a program key, so it must + * be 168 bytes long and permuted ... + */ + ret = dryice_set_programmed_key(key, 8 * key_length, 0); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + } + + out: + key_info->key_length = original_key_length; + + if (pk_needs_restoration) { + di_code = dryice_set_programmed_key(current_pk, 8 * 21, 0); + } + + if (!pk_was_held) { + dryice_release_programmed_key(); + } + + /* Erase tracks of confidential data */ + memset(T, 0, T_LENGTH); + memset(key, 0, rounded_key_length); + memset(current_pk, 0, sizeof(current_pk)); + memset(&t_key_info, 0, sizeof(t_key_info)); + memset(&t_key_ctx, 0, sizeof(t_key_ctx)); + memset(&kek_key_info, 0, sizeof(kek_key_info)); + memset(&kek_ctx, 0, sizeof(kek_ctx)); + memset(kek, 0, KEK_LENGTH); + + return ret; +} /* unwrap */ + +/*! + * Perform wrapping of a black key from a RED slot (or the PK register) + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] key_info The information about the key to be which will + * be wrapped... key length, slot info, etc. + * @param black_key Place to store encrypted key + * + * @return A return code of type #fsl_shw_return_t. + */ +static fsl_shw_return_t wrap(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, uint8_t * black_key) +{ + fsl_shw_return_t ret = FSL_RETURN_OK_S; + fsl_shw_sko_t t_key_info; /* for holding T */ + fsl_shw_scco_t t_key_ctx; + fsl_shw_sko_t kek_key_info; + fsl_shw_scco_t kek_ctx; + unsigned original_key_length = key_info->key_length; + unsigned rounded_key_length; + uint8_t T[T_LENGTH]; + uint8_t kek[KEK_LENGTH + 20]; + uint8_t *red_key = 0; + int red_key_malloced = 0; /* bool */ + int pk_was_held = 0; /* bool */ + uint8_t saved_pk[21]; + uint8_t pk_needs_restoration; /* bool */ + di_return_t di_code; + + ret = check_wrap_key(user_ctx->wrap_key); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + if (black_key == NULL) { + ret = FSL_RETURN_ERROR_S; + goto out; + } + + if (key_info->flags & FSL_SKO_KEY_SELECT_PF_KEY) { + if ((key_info->pf_key != FSL_SHW_PF_KEY_PRG) + && (key_info->pf_key != FSL_SHW_PF_KEY_IIM_PRG)) { + ret = FSL_RETURN_ERROR_S; + goto out; + } + } else { + if (!(key_info->flags & FSL_SKO_KEY_ESTABLISHED)) { + ret = FSL_RETURN_BAD_FLAG_S; /* not established! */ + goto out; + } + } + + black_key[ALGORITHM_OFFSET] = key_info->algorithm; + +#ifndef DO_REPEATABLE_WRAP + /* Compute T = RND() */ + ret = fsl_shw_get_random(user_ctx, T_LENGTH, T); + if (ret != FSL_RETURN_OK_S) { + goto out; + } +#else + memcpy(T, T_block, T_LENGTH); +#endif + + /* Compute KEK = SHA256(T | ownerid). */ + ret = calc_kek((uint8_t *) & key_info->userid, sizeof(key_info->userid), + T, kek); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Calculation of KEK failed\n"); +#endif /*DIAG_SECURITY_FUNC */ + goto out; + } + + rounded_key_length = ROUND_LENGTH(original_key_length); + + di_code = dryice_get_programmed_key(saved_pk, 8 * 21); + if (di_code != DI_SUCCESS) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Could not save current PK: %s\n", + di_error_string(di_code)); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + + /* + * Load KEK into DI PKR. Note that we are NOT permuting it before loading, + * so we are using it as though it is a 168-bit key ready for the SCC. + */ + di_code = dryice_set_programmed_key(kek, 8 * 21, 0); + if (di_code == DI_ERR_INUSE) { + /* Temporarily reprogram the PK out from under the user */ + pk_was_held = 1; + dryice_release_programmed_key(); + di_code = dryice_set_programmed_key(kek, 8 * 21, 0); + } + if (di_code != DI_SUCCESS) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Could not program KEK: %s\n", + di_error_string(di_code)); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + pk_needs_restoration = 1; + dryice_release_programmed_key(); + + /* Find red key */ + if (key_info->flags & FSL_SKO_KEY_SELECT_PF_KEY) { + black_key[LENGTH_OFFSET] = 21; + rounded_key_length = 24; + + red_key = saved_pk; + } else { + black_key[LENGTH_OFFSET] = key_info->key_length; + + red_key = os_alloc_memory(key_info->key_length, 0); + if (red_key == NULL) { + ret = FSL_RETURN_NO_RESOURCE_S; + goto out; + } + red_key_malloced = 1; + + ret = fsl_shw_read_key(user_ctx, key_info, red_key); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + } + +#ifdef DIAG_SECURITY_FUNC + dump("KEY", red_key, black_key[LENGTH_OFFSET]); +#endif + /* Compute KEY' = TDES-encrypt(KEK, KEY) */ + fsl_shw_sko_init_pf_key(&kek_key_info, FSL_KEY_ALG_TDES, + FSL_SHW_PF_KEY_PRG); + fsl_shw_sko_set_key_length(&kek_key_info, KEK_LENGTH); + + fsl_shw_scco_init(&kek_ctx, FSL_KEY_ALG_TDES, FSL_SYM_MODE_CBC); + fsl_shw_scco_set_flags(&kek_ctx, FSL_SYM_CTX_LOAD); + fsl_shw_scco_set_context(&kek_ctx, (uint8_t *) & key_info->userid); + ret = fsl_shw_symmetric_encrypt(user_ctx, &kek_key_info, &kek_ctx, + rounded_key_length, + red_key, black_key + KEY_PRIME_OFFSET); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Encryption of KEY failed\n"); +#endif /*DIAG_SECURITY_FUNC */ + goto out; + } + + /* Set up flags info */ + black_key[FLAGS_OFFSET] = 0; + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + black_key[FLAGS_OFFSET] |= FLAGS_SW_KEY; + } +#ifdef DIAG_SECURITY_FUNC + dump("KEY'", black_key + KEY_PRIME_OFFSET, rounded_key_length); +#endif + /* Compute and store ICV into Black Key */ + ret = calc_icv(T, + (uint8_t *) & key_info->userid, + sizeof(key_info->userid), + black_key, original_key_length, black_key + ICV_OFFSET); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Calculation of ICV failed\n"); +#endif /*DIAG_SECURITY_FUNC */ + goto out; + } + + /* Compute T' = 3des-enc-ecb(wrap_key, T); Result goes to Black Key */ + init_wrap_key(user_ctx->wrap_key, &t_key_info, &t_key_ctx); + ret = fsl_shw_symmetric_encrypt(user_ctx, &t_key_info, &t_key_ctx, + T_LENGTH, + T, black_key + T_PRIME_OFFSET); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Encryption of nonce failed"); +#endif + goto out; + } +#ifdef DIAG_SECURITY_FUNC + dump("black", black_key, KEY_PRIME_OFFSET + black_key[LENGTH_OFFSET]); +#endif + + out: + if (pk_needs_restoration) { + dryice_set_programmed_key(saved_pk, 8 * 21, 0); + } + + if (!pk_was_held) { + dryice_release_programmed_key(); + } + + if (red_key_malloced) { + memset(red_key, 0, key_info->key_length); + os_free_memory(red_key); + } + + key_info->key_length = original_key_length; + + /* Erase tracks of confidential data */ + memset(T, 0, T_LENGTH); + memset(&t_key_info, 0, sizeof(t_key_info)); + memset(&t_key_ctx, 0, sizeof(t_key_ctx)); + memset(&kek_key_info, 0, sizeof(kek_key_info)); + memset(&kek_ctx, 0, sizeof(kek_ctx)); + memset(kek, 0, sizeof(kek)); + memset(saved_pk, 0, sizeof(saved_pk)); + + return ret; +} /* wrap */ + +static fsl_shw_return_t create(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + unsigned key_length = key_info->key_length; + di_return_t di_code; + + if (!(key_info->flags & FSL_SKO_KEY_SW_KEY)) { + /* Must be creating key for PK */ + if ((key_info->algorithm != FSL_KEY_ALG_TDES) || + ((key_info->key_length != 16) + && (key_info->key_length != 21) /* permuted 168-bit key */ + &&(key_info->key_length != 24))) { + ret = FSL_RETURN_ERROR_S; + goto out; + } + + key_length = 21; /* 168-bit PK */ + } + + /* operational block */ + { + uint8_t key_value[key_length]; + +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Creating random key\n"); +#endif + ret = fsl_shw_get_random(user_ctx, key_length, key_value); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("get_random for CREATE KEY failed\n"); +#endif + goto out; + } + + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + ret = load_slot(user_ctx, key_info, key_value); + } else { + di_code = + dryice_set_programmed_key(key_value, 8 * key_length, + 0); + if (di_code != 0) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("di set_pk failed: %s\n", + di_error_string(di_code)); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + ret = FSL_RETURN_OK_S; + } + memset(key_value, 0, key_length); + } /* end operational block */ + +#ifdef DIAG_SECURITY_FUNC + if (ret != FSL_RETURN_OK_S) { + LOG_DIAG("Loading random key failed"); + } +#endif + + out: + + return ret; +} /* end fn create */ + +static fsl_shw_return_t accept(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, const uint8_t * key) +{ + uint8_t permuted_key[21]; + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + if (key == NULL) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("ACCEPT: Red Key is NULL"); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } +#ifdef DIAG_SECURITY_FUNC + dump("red", key, key_info->key_length); +#endif + /* Only SW keys go into the keystore */ + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + + /* Copy in safe number of bytes of Red key */ + ret = load_slot(user_ctx, key_info, key); + } else { /* not SW key */ + di_return_t di_ret; + + /* Only 3DES PGM key types can be established */ + if (((key_info->pf_key != FSL_SHW_PF_KEY_PRG) + && (key_info->pf_key != FSL_SHW_PF_KEY_IIM_PRG)) + || (key_info->algorithm != FSL_KEY_ALG_TDES)) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS + ("ACCEPT: Failed trying to establish non-PRG" + " or invalid 3DES Key: iim%d, iim_prg%d, alg%d\n", + (key_info->pf_key != FSL_SHW_PF_KEY_PRG), + (key_info->pf_key != FSL_SHW_PF_KEY_IIM_PRG), + (key_info->algorithm != FSL_KEY_ALG_TDES)); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + if ((key_info->key_length != 16) + && (key_info->key_length != 21) + && (key_info->key_length != 24)) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("ACCEPT: Failed trying to establish" + " invalid 3DES Key: len=%d (%d)\n", + key_info->key_length, + ((key_info->key_length != 16) + && (key_info->key_length != 21) + && (key_info->key_length != 24))); +#endif + ret = FSL_RETURN_BAD_KEY_LENGTH_S; + goto out; + } + + /* Convert key into 168-bit value and put it into PK */ + if (key_info->key_length != 21) { + fsl_shw_permute1_bytes(key, permuted_key, + key_info->key_length / 8); + di_ret = + dryice_set_programmed_key(permuted_key, 168, 0); + } else { + /* Already permuted ! */ + di_ret = dryice_set_programmed_key(key, 168, 0); + } + if (di_ret != DI_SUCCESS) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS + ("ACCEPT: DryIce error setting Program Key: %s", + di_error_string(di_ret)); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + } + + ret = FSL_RETURN_OK_S; + + out: + memset(permuted_key, 0, 21); + + return ret; +} /* end fn accept */ + +/*! + * Place a key into a protected location for use only by cryptographic + * algorithms. + * + * This only needs to be used to a) unwrap a key, or b) set up a key which + * could be wrapped by calling #fsl_shw_extract_key() at some later time). + * + * The protected key will not be available for use until this operation + * successfully completes. + * + * @bug This whole discussion needs review. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] key_info The information about the key to be which will + * be established. In the create case, the key + * length must be set. + * @param establish_type How @a key will be interpreted to establish a + * key for use. + * @param key If @a establish_type is #FSL_KEY_WRAP_UNWRAP, + * this is the location of a wrapped key. If + * @a establish_type is #FSL_KEY_WRAP_CREATE, this + * parameter can be @a NULL. If @a establish_type + * is #FSL_KEY_WRAP_ACCEPT, this is the location + * of a plaintext key. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_establish_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_key_wrap_t establish_type, + const uint8_t * key) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + unsigned original_key_length = key_info->key_length; + unsigned rounded_key_length; + unsigned slot_allocated = 0; + + /* For now, only blocking mode calls are supported */ + if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("%s: Non-blocking call not supported\n", + __FUNCTION__); +#endif + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + /* + HW keys are always 'established', but otherwise do not allow user + * to establish over the top of an established key. + */ + if ((key_info->flags & FSL_SKO_KEY_ESTABLISHED) + && !(key_info->flags & FSL_SKO_KEY_SELECT_PF_KEY)) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("%s: Key already established\n", __FUNCTION__); +#endif + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + /* @bug VALIDATE KEY flags here -- SW or PRG/IIM_PRG */ + + /* Write operations into SCC memory require word-multiple number of + * bytes. For ACCEPT and CREATE functions, the key length may need + * to be rounded up. Calculate. */ + if (LENGTH_PATCH && (original_key_length & LENGTH_PATCH_MASK) != 0) { + rounded_key_length = original_key_length + LENGTH_PATCH + - (original_key_length & LENGTH_PATCH_MASK); + } else { + rounded_key_length = original_key_length; + } + + /* SW keys need a place to live */ + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + ret = alloc_slot(user_ctx, key_info); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Slot allocation failed\n"); +#endif + goto out; + } + slot_allocated = 1; + } + + switch (establish_type) { + case FSL_KEY_WRAP_CREATE: +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Creating random key\n"); +#endif + ret = create(user_ctx, key_info); + break; + + case FSL_KEY_WRAP_ACCEPT: +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Accepting plaintext key\n"); +#endif + ret = accept(user_ctx, key_info, key); + break; + + case FSL_KEY_WRAP_UNWRAP: +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Unwrapping wrapped key\n"); +#endif + ret = unwrap(user_ctx, key_info, key); + break; + + default: + ret = FSL_RETURN_BAD_FLAG_S; + break; + } /* switch */ + + out: + if (ret != FSL_RETURN_OK_S) { + if (slot_allocated) { + (void)dealloc_slot(user_ctx, key_info); + } + key_info->flags &= ~FSL_SKO_KEY_ESTABLISHED; + } else { + key_info->flags |= FSL_SKO_KEY_ESTABLISHED; + } + + return ret; +} /* end fn fsl_shw_establish_key */ + +/*! + * Wrap a key and retrieve the wrapped value. + * + * A wrapped key is a key that has been cryptographically obscured. It is + * only able to be used with #fsl_shw_establish_key(). + * + * This function will also release a software key (see #fsl_shw_release_key()) + * so it must be re-established before reuse. This is not true of PGM keys. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The information about the key to be deleted. + * @param[out] covered_key The location to store the 48-octet wrapped key. + * (This size is based upon the maximum key size + * of 32 octets). + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + uint8_t * covered_key) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + /* For now, only blocking mode calls are supported */ + if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Wrapping a key\n"); +#endif + + if (!(key_info->flags & FSL_SKO_KEY_ESTABLISHED)) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("%s: Key not established\n", __FUNCTION__); +#endif + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + /* Verify that a SW key info really belongs to a SW key */ + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + /* ret = FSL_RETURN_BAD_FLAG_S; + goto out;*/ + } + + ret = wrap(user_ctx, key_info, covered_key); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + /* Need to deallocate on successful extraction */ + (void)dealloc_slot(user_ctx, key_info); + /* Mark key not available in the flags */ + key_info->flags &= + ~(FSL_SKO_KEY_ESTABLISHED | FSL_SKO_KEY_PRESENT); + memset(key_info->key, 0, sizeof(key_info->key)); + } + + out: + return ret; +} /* end fn fsl_shw_extract_key */ + +/*! + * De-establish a key so that it can no longer be accessed. + * + * The key will need to be re-established before it can again be used. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The information about the key to be deleted. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_release_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + /* For now, only blocking mode calls are supported */ + if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Not in blocking mode\n"); +#endif + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Releasing a key\n"); +#endif + + if (!(key_info->flags & FSL_SKO_KEY_ESTABLISHED)) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Key not established\n"); +#endif + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + (void)dealloc_slot(user_ctx, key_info); + /* Turn off 'established' flag */ +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("dealloc_slot() called\n"); +#endif + key_info->flags &= ~FSL_SKO_KEY_ESTABLISHED; + ret = FSL_RETURN_OK_S; + goto out; + } + + if ((key_info->pf_key == FSL_SHW_PF_KEY_PRG) + || (key_info->pf_key == FSL_SHW_PF_KEY_IIM_PRG)) { + di_return_t di_ret; + + di_ret = dryice_release_programmed_key(); + if (di_ret != DI_SUCCESS) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS + ("dryice_release_programmed_key() failed: %d\n", + di_ret); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + } else { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Neither SW nor HW key\n"); +#endif + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + ret = FSL_RETURN_OK_S; + + out: + return ret; +} /* end fn fsl_shw_release_key */ + +fsl_shw_return_t fsl_shw_read_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, uint8_t * key) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + + /* Only blocking mode calls are supported */ + if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + printk("Reading a key\n"); +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Reading a key"); +#endif + if (key_info->flags & FSL_SKO_KEY_PRESENT) { + memcpy(key_info->key, key, key_info->key_length); + ret = FSL_RETURN_OK_S; + } else if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) { + printk("key established\n"); + if (key_info->keystore == NULL) { + printk("keystore is null\n"); + /* First verify that the key access is valid */ + ret = + system_keystore.slot_verify_access(system_keystore. + user_data, + key_info->userid, + key_info-> + handle); + + printk("key in system keystore\n"); + + /* Key is in system keystore */ + ret = keystore_slot_read(&system_keystore, + key_info->userid, + key_info->handle, + key_info->key_length, key); + } else { + printk("key goes in user keystore.\n"); + /* Key goes in user keystore */ + ret = keystore_slot_read(key_info->keystore, + key_info->userid, + key_info->handle, + key_info->key_length, key); + } + } + + out: + return ret; +} /* end fn fsl_shw_read_key */ + +#else /* __KERNEL__ && DRYICE */ + +/* User mode -- these functions are unsupported */ + +fsl_shw_return_t fsl_shw_establish_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_key_wrap_t establish_type, + const uint8_t * key) +{ + (void)user_ctx; + (void)key_info; + (void)establish_type; + (void)key; + + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + uint8_t * covered_key) +{ + (void)user_ctx; + (void)key_info; + (void)covered_key; + + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t fsl_shw_release_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info) +{ + (void)user_ctx; + (void)key_info; + + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t fsl_shw_read_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, uint8_t * key) +{ + (void)user_ctx; + (void)key_info; + (void)key; + + return FSL_RETURN_NO_RESOURCE_S; +} + +#endif /* __KERNEL__ && DRYICE */ diff -urN linux-2.6.26/drivers/mxc/security/rng/include/rng_driver.h linux-2.6.26-lab126/drivers/mxc/security/rng/include/rng_driver.h --- linux-2.6.26/drivers/mxc/security/rng/include/rng_driver.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/include/rng_driver.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,134 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +#ifndef RNG_DRIVER_H +#define RNG_DRIVER_H + +#include "shw_driver.h" + +/* This is a Linux flag meaning 'compiling kernel code'... */ +#ifndef __KERNEL__ +#include +#include +#include +#else +#include "../../sahara2/include/portable_os.h" +#endif + +#include "../../sahara2/include/fsl_platform.h" + +/*! @file rng_driver.h + * + * @brief Header file to use the RNG driver. + * + * @ingroup RNG + */ + +#if defined(FSL_HAVE_RNGA) + +#include "rng_rnga.h" + +#elif defined(FSL_HAVE_RNGB) || defined(FSL_HAVE_RNGC) + +#include "rng_rngc.h" + +#else /* neither RNGA, RNGB, nor RNGC */ + +#error NO_RNG_TYPE_IDENTIFIED + +#endif + +/***************************************************************************** + * Enumerations + *****************************************************************************/ + +/*! Values from Version ID register */ +enum rng_type { + /*! Type RNGA. */ + RNG_TYPE_RNGA = 0, + /*! Type RNGB. */ + RNG_TYPE_RNGB = 1, + /*! Type RNGC */ + RNG_TYPE_RNGC = 2 +}; + +/*! + * Return values (error codes) for kernel register interface functions + */ +typedef enum rng_return { + RNG_RET_OK = 0, /*!< Function succeeded */ + RNG_RET_FAIL /*!< Non-specific failure */ +} rng_return_t; + +/***************************************************************************** + * Data Structures + *****************************************************************************/ +/*! + * An entry in the RNG Work Queue. Based upon standard SHW queue entry. + * + * This entry also gets saved (for non-blocking requests) in the user's result + * pool. When the user picks up the request, the final processing (copy from + * data_local to data_user) will get made if status was good. + */ +typedef struct rng_work_entry { + struct shw_queue_entry_t hdr; /*!< Standards SHW queue info. */ + uint32_t length; /*!< Number of bytes still needed to satisfy request. */ + uint32_t *data_local; /*!< Where data from RNG FIFO gets placed. */ + uint8_t *data_user; /*!< Ultimate target of data. */ + unsigned completed; /*!< Non-zero if job is done. */ +} rng_work_entry_t; + +/***************************************************************************** + * Function Prototypes + *****************************************************************************/ + +#ifdef RNG_REGISTER_PEEK_POKE +/*! + * Read value from an RNG register. + * The offset will be checked for validity as well as whether it is + * accessible at the time of the call. + * + * This routine cannot be used to read the RNG's Output FIFO if the RNG is in + * High Assurance mode. + * + * @param[in] register_offset The (byte) offset within the RNG block + * of the register to be queried. See + * RNG(A, C) registers for meanings. + * @param[out] value Pointer to where value from the register + * should be placed. + * + * @return See #rng_return_t. + */ +/* REQ-FSLSHW-PINTFC-API-LLF-001 */ +extern rng_return_t rng_read_register(uint32_t register_offset, + uint32_t * value); + +/*! + * Write a new value into an RNG register. + * + * The offset will be checked for validity as well as whether it is + * accessible at the time of the call. + * + * @param[in] register_offset The (byte) offset within the RNG block + * of the register to be modified. See + * RNG(A, C) registers for meanings. + * @param[in] value The value to store into the register. + * + * @return See #rng_return_t. + */ +/* REQ-FSLSHW-PINTFC-API-LLF-002 */ +extern rng_return_t rng_write_register(uint32_t register_offset, + uint32_t value); +#endif /* RNG_REGISTER_PEEK_POKE */ + +#endif /* RNG_DRIVER_H */ diff -urN linux-2.6.26/drivers/mxc/security/rng/include/rng_internals.h linux-2.6.26-lab126/drivers/mxc/security/rng/include/rng_internals.h --- linux-2.6.26/drivers/mxc/security/rng/include/rng_internals.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/include/rng_internals.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,666 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef RNG_INTERNALS_H +#define RNG_INTERNALS_H + +/*! @file rng_internals.h + * + * This file contains definitions which are internal to the RNG driver. + * + * This header file should only ever be needed by rng_driver.c + * + * Compile-time flags minimally needed: + * + * @li Some sort of platform flag. (FSL_HAVE_RNGA or FSL_HAVE_RNGC) + * + * @ingroup RNG + */ + +#include "portable_os.h" +#include "shw_driver.h" +#include "rng_driver.h" + +/*! @defgroup rngcompileflags RNG Compile Flags + * + * These are flags which are used to configure the RNG driver at compilation + * time. + * + * Most of them default to good values for normal operation, but some + * (#INT_RNG and #RNG_BASE_ADDR) need to be provided. + * + * The terms 'defined' and 'undefined' refer to whether a @c \#define (or -D on + * a compile command) has defined a given preprocessor symbol. If a given + * symbol is defined, then @c \#ifdef \ will succeed. Some symbols + * described below default to not having a definition, i.e. they are undefined. + * + */ + +/*! @addtogroup rngcompileflags */ +/*! @{ */ + +/*! + * This is the maximum number of times the driver will loop waiting for the + * RNG hardware to say that it has generated random data. It prevents the + * driver from stalling forever should there be a hardware problem. + * + * Default value is 100. It should be revisited as CPU clocks speed up. + */ +#ifndef RNG_MAX_TRIES +#define RNG_MAX_TRIES 100 +#endif + +/* Temporarily define compile-time flags to make Doxygen happy and allow them + to get into the documentation. */ +#ifdef DOXYGEN_HACK + +/*! + * This symbol is the base address of the RNG in the CPU memory map. It may + * come from some included header file, or it may come from the compile command + * line. This symbol has no default, and the driver will not compile without + * it. + */ +#define RNG_BASE_ADDR +#undef RNG_BASE_ADDR + +/*! + * This symbol is the Interrupt Number of the RNG in the CPU. It may come + * from some included header file, or it may come from the compile command + * line. This symbol has no default, and the driver will not compile without + * it. + */ +#define INT_RNG +#undef INT_RNG + +/*! + * Defining this symbol will allow other kernel programs to call the + * #rng_read_register() and #rng_write_register() functions. If this symbol is + * not defined, those functions will not be present in the driver. + */ +#define RNG_REGISTER_PEEK_POKE +#undef RNG_REGISTER_PEEK_POKE + +/*! + * Turn on compilation of run-time operational, debug, and error messages. + * + * This flag is undefined by default. + */ +/* REQ-FSLSHW-DEBUG-001 */ + +/*! + * Turn on compilation of run-time logging of access to the RNG registers, + * except for the RNG's Output FIFO register. See #RNG_ENTROPY_DEBUG. + * + * This flag is undefined by default + */ +#define RNG_REGISTER_DEBUG +#undef RNG_REGISTER_DEBUG + +/*! + * Turn on compilation of run-time logging of reading of the RNG's Output FIFO + * register. This flag does nothing if #RNG_REGISTER_DEBUG is not defined. + * + * This flag is undefined by default + */ +#define RNG_ENTROPY_DEBUG +#undef RNG_ENTROPY_DEBUG + +/*! + * If this flag is defined, the driver will not attempt to put the RNG into + * High Assurance mode. + + * If it is undefined, the driver will attempt to put the RNG into High + * Assurance mode. If RNG fails to go into High Assurance mode, the driver + * will fail to initialize. + + * In either case, if the RNG is already in this mode, the driver will operate + * normally. + * + * This flag is undefined by default. + */ +#define RNG_NO_FORCE_HIGH_ASSURANCE +#undef RNG_NO_FORCE_HIGH_ASSURANCE + +/*! + * If this flag is defined, the driver will put the RNG into low power mode + * every opportunity. + * + * This flag is undefined by default. + */ +#define RNG_USE_LOW_POWER_MODE +#undef RNG_USE_LOW_POWER_MODE + +/*! @} */ +#endif /* end DOXYGEN_HACK */ + +/*! + * Read a 32-bit value from an RNG register. This macro depends upon + * #rng_base. The os_read32() macro operates on 32-bit quantities, as do + * all RNG register reads. + * + * @param offset Register byte offset within RNG. + * + * @return The value from the RNG's register. + */ +#ifndef RNG_REGISTER_DEBUG +#define RNG_READ_REGISTER(offset) os_read32(rng_base+(offset)) +#else +#define RNG_READ_REGISTER(offset) dbg_rng_read_register(offset) +#endif + +/*! + * Write a 32-bit value to an RNG register. This macro depends upon + * #rng_base. The os_write32() macro operates on 32-bit quantities, as do + * all RNG register writes. + * + * @param offset Register byte offset within RNG. + * @param value 32-bit value to store into the register + * + * @return (void) + */ +#ifndef RNG_REGISTER_DEBUG +#define RNG_WRITE_REGISTER(offset,value) \ + (void)os_write32(rng_base+(offset), value) +#else +#define RNG_WRITE_REGISTER(offset,value) dbg_rng_write_register(offset,value) +#endif + +#ifndef RNG_DRIVER_NAME +/*! @addtogroup rngcompileflags */ +/*! @{ */ +/*! Name the driver will use to register itself to the kernel as the driver. */ +#define RNG_DRIVER_NAME "rng" +/*! @} */ +#endif + +/*! + * Calculate number of words needed to hold the given number of bytes. + * + * @param byte_count Number of bytes + * + * @return Number of words + */ +#define BYTES_TO_WORDS(byte_count) \ + (((byte_count)+sizeof(uint32_t)-1)/sizeof(uint32_t)) + +/*! Gives high-level view of state of the RNG */ +typedef enum rng_status { + RNG_STATUS_INITIAL, /*!< Driver status before ever starting. */ + RNG_STATUS_CHECKING, /*!< During driver initialization. */ + RNG_STATUS_UNIMPLEMENTED, /*!< Hardware is non-existent / unreachable. */ + RNG_STATUS_OK, /*!< Hardware is In Secure or Default state. */ + RNG_STATUS_FAILED /*!< Hardware is In Failed state / other fatal + problem. Driver is still able to read/write + some registers, but cannot get Random + data. */ +} rng_status_t; + +static shw_queue_t rng_work_queue; + +/***************************************************************************** + * + * Function Declarations + * + *****************************************************************************/ + +/* kernel interface functions */ +OS_DEV_INIT_DCL(rng_init); +OS_DEV_TASK_DCL(rng_entropy_task); +OS_DEV_SHUTDOWN_DCL(rng_shutdown); +OS_DEV_ISR_DCL(rng_irq); + +#define RNG_ADD_QUEUE_ENTRY(pool, entry) \ + SHW_ADD_QUEUE_ENTRY(pool, (shw_queue_entry_t*)entry) + +#define RNG_REMOVE_QUEUE_ENTRY(pool, entry) \ + SHW_REMOVE_QUEUE_ENTRY(pool, (shw_queue_entry_t*)entry) +#define RNG_GET_WORK_ENTRY() \ + (rng_work_entry_t*)SHW_POP_FIRST_ENTRY(&rng_work_queue) + +/*! + * Add an work item to a work list. Item will be marked incomplete. + * + * @param work Work entry to place at tail of list. + * + * @return none + */ +inline static void RNG_ADD_WORK_ENTRY(rng_work_entry_t * work) +{ + work->completed = FALSE; + + SHW_ADD_QUEUE_ENTRY(&rng_work_queue, (shw_queue_entry_t *) work); + + os_dev_schedule_task(rng_entropy_task); +} + +/*! + * For #rng_check_register_accessible(), check read permission on given + * register. + */ +#define RNG_CHECK_READ 0 + +/*! + * For #rng_check_register_accessible(), check write permission on given + * register. + */ +#define RNG_CHECK_WRITE 1 + +/* Define different helper symbols based on RNG type */ +#ifdef FSL_HAVE_RNGA + +/****************************************************************************** + * + * RNGA support + * + *****************************************************************************/ + +/*! Interrupt number for driver. */ +#if defined(MXC_INT_RNG) +/* Most modern definition */ +#define INT_RNG MXC_INT_RNG +#elif defined(MXC_INT_RNGA) +#define INT_RNG MXC_INT_RNGA +#else +#define INT_RNG INT_RNGA +#endif + +/*! Base (bus?) address of RNG component. */ +#define RNG_BASE_ADDR RNGA_BASE_ADDR + +/*! Read and return the status register. */ +#define RNG_GET_STATUS() \ + RNG_READ_REGISTER(RNGA_STATUS) +/*! Configure RNG for Auto seeding */ +#define RNG_AUTO_SEED() +/* Put RNG for Seed Generation */ +#define RNG_SEED_GEN() +/*! + * Return RNG Type value. Should be RNG_TYPE_RNGA, RNG_TYPE_RNGB, + * or RNG_TYPE_RNGC. + */ +#define RNG_GET_RNG_TYPE() \ + ((RNG_READ_REGISTER(RNGA_CONTROL) & RNGA_CONTROL_RNG_TYPE_MASK) \ + >> RNGA_CONTROL_RNG_TYPE_SHIFT) + +/*! + * Verify Type value of RNG. + * + * Returns true of OK, false if not. + */ +#define RNG_VERIFY_TYPE(type) \ + ((type) == RNG_TYPE_RNGA) + +/*! Returns non-zero if RNG device is reporting an error. */ +#define RNG_HAS_ERROR() \ + (RNG_READ_REGISTER(RNGA_STATUS) & RNGA_STATUS_ERROR_INTERRUPT) +/*! Returns non-zero if Bad Key is selected */ +#define RNG_HAS_BAD_KEY() 0 +/*! Return non-zero if Self Test Done */ +#define RNG_SELF_TEST_DONE() 0 +/*! Returns non-zero if RNG ring oscillators have failed. */ +#define RNG_OSCILLATOR_FAILED() \ + (RNG_READ_REGISTER(RNGA_STATUS) & RNGA_STATUS_OSCILLATOR_DEAD) + +/*! Returns maximum number of 32-bit words in the RNG's output fifo. */ +#define RNG_GET_FIFO_SIZE() \ + ((RNG_READ_REGISTER(RNGA_STATUS) & RNGA_STATUS_OUTPUT_FIFO_SIZE_MASK) \ + >> RNGA_STATUS_OUTPUT_FIFO_SIZE_SHIFT) + +/*! Returns number of 32-bit words currently in the RNG's output fifo. */ +#define RNG_GET_WORDS_IN_FIFO() \ + ((RNG_READ_REGISTER(RNGA_STATUS) & RNGA_STATUS_OUTPUT_FIFO_LEVEL_MASK) \ + >> RNGA_STATUS_OUTPUT_FIFO_LEVEL_SHIFT) +/* Configuring RNG for Self Test */ +#define RNG_SELF_TEST() +/*! Get a random value from the RNG's output FIFO. */ +#define RNG_READ_FIFO() \ + RNG_READ_REGISTER(RNGA_OUTPUT_FIFO) + +/*! Put entropy into the RNG's algorithm. + * @param value 32-bit value to add to RNG's entropy. + **/ +#define RNG_ADD_ENTROPY(value) \ + RNG_WRITE_REGISTER(RNGA_ENTROPY, (value)) +/*! Return non-zero in case of Error during Self Test */ +#define RNG_CHECK_SELF_ERR() 0 +/*! Return non-zero in case of Error during Seed Generation */ +#define RNG_CHECK_SEED_ERR() 0 +/*! Get the RNG started at generating output. */ +#define RNG_GO() \ +{ \ + register uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL); \ + RNG_WRITE_REGISTER(RNGA_CONTROL, control | RNGA_CONTROL_GO); \ +} +/*! To clear all Error Bits in Error Status Register */ +#define RNG_CLEAR_ERR() +/*! Put RNG into High Assurance mode */ +#define RNG_SET_HIGH_ASSURANCE() \ +{ \ + register uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL); \ + RNG_WRITE_REGISTER(RNGA_CONTROL, control | RNGA_CONTROL_HIGH_ASSURANCE); \ +} + +/*! Return non-zero if the RNG is in High Assurance mode. */ +#define RNG_GET_HIGH_ASSURANCE() \ + (RNG_READ_REGISTER(RNGA_CONTROL) & RNGA_CONTROL_HIGH_ASSURANCE) + +/*! Clear all status, error and otherwise. */ +#define RNG_CLEAR_ALL_STATUS() \ +{ \ + register uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL); \ + RNG_WRITE_REGISTER(RNGA_CONTROL, control | RNGA_CONTROL_CLEAR_INTERRUPT); \ +} +/* Return non-zero if RESEED Required */ +#define RNG_RESEED() 1 + +/*! Return non-zero if Seeding is done */ +#define RNG_SEED_DONE() 1 + +/*! Return non-zero if everything seems OK with the RNG. */ +#define RNG_WORKING() \ + ((RNG_READ_REGISTER(RNGA_STATUS) \ + & (RNGA_STATUS_SLEEP | RNGA_STATUS_SECURITY_VIOLATION \ + | RNGA_STATUS_ERROR_INTERRUPT | RNGA_STATUS_FIFO_UNDERFLOW \ + | RNGA_STATUS_LAST_READ_STATUS )) == 0) + +/*! Put the RNG into sleep (low-power) mode. */ +#define RNG_SLEEP() \ +{ \ + register uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL); \ + RNG_WRITE_REGISTER(RNGA_CONTROL, control | RNGA_CONTROL_SLEEP); \ +} + +/*! Wake the RNG from sleep (low-power) mode. */ +#define RNG_WAKE() \ +{ \ + uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL); \ + RNG_WRITE_REGISTER(RNGA_CONTROL, control & ~RNGA_CONTROL_SLEEP); \ +} + +/*! Mask interrupts so that the driver/OS will not see them. */ +#define RNG_MASK_ALL_INTERRUPTS() \ +{ \ + register uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL); \ + RNG_WRITE_REGISTER(RNGA_CONTROL, control | RNGA_CONTROL_MASK_INTERRUPTS); \ +} + +/*! Unmask interrupts so that the driver/OS will see them. */ +#define RNG_UNMASK_ALL_INTERRUPTS() \ +{ \ + register uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL); \ + RNG_WRITE_REGISTER(RNGA_CONTROL, control & ~RNGA_CONTROL_MASK_INTERRUPTS);\ +} + +/*! + * @def RNG_PUT_RNG_TO_SLEEP() + * + * If compiled with #RNG_USE_LOW_POWER_MODE, this routine will put the RNG + * to sleep (low power mode). + * + * @return none + */ +/*! + * @def RNG_WAKE_RNG_FROM_SLEEP() + * + * If compiled with #RNG_USE_LOW_POWER_MODE, this routine will wake the RNG + * from sleep (low power mode). + * + * @return none + */ +#ifdef RNG_USE_LOW_POWER_MODE + +#define RNG_PUT_RNG_TO_SLEEP() \ + RNG_SLEEP() + +#define RNG_WAKE_FROM_SLEEP() \ + RNG_WAKE() 1 + +#else /* not low power mode */ + +#define RNG_PUT_RNG_TO_SLEEP() + +#define RNG_WAKE_FROM_SLEEP() + +#endif /* Use low-power mode */ + +#else /* FSL_HAVE_RNGB or FSL_HAVE_RNGC */ + +/****************************************************************************** + * + * RNGB and RNGC support + * + *****************************************************************************/ +/* + * The operational interfaces for RNGB and RNGC are almost identical, so + * the defines for RNGC work fine for both. There are minor differences + * which will be treated within this conditional block. + */ + +/*! Interrupt number for driver. */ +#if defined(MXC_INT_RNG) +/* Most modern definition */ +#define INT_RNG MXC_INT_RNG +#elif defined(MXC_INT_RNGC) +#define INT_RNG MXC_INT_RNGC +#elif defined(MXC_INT_RNGB) +#define INT_RNG MXC_INT_RNGB +#elif defined(INT_RNGC) +#define INT_RNG INT_RNGC +#else +#error NO_INTERRUPT_DEFINED +#endif + +/*! Base address of RNG component. */ +#ifdef FSL_HAVE_RNGB +#define RNG_BASE_ADDR RNGB_BASE_ADDR +#else +#define RNG_BASE_ADDR RNGC_BASE_ADDR +#endif + +/*! Read and return the status register. */ +#define RNG_GET_STATUS() \ + RNG_READ_REGISTER(RNGC_ERROR) + +/*! + * Return RNG Type value. Should be RNG_TYPE_RNGA or RNG_TYPE_RNGC. + */ +#define RNG_GET_RNG_TYPE() \ + ((RNG_READ_REGISTER(RNGC_VERSION_ID) & RNGC_VERID_RNG_TYPE_MASK) \ + >> RNGC_VERID_RNG_TYPE_SHIFT) + +/*! + * Verify Type value of RNG. + * + * Returns true of OK, false if not. + */ +#ifdef FSL_HAVE_RNGB +#define RNG_VERIFY_TYPE(type) \ + ((type) == RNG_TYPE_RNGB) +#else /* RNGC */ +#define RNG_VERIFY_TYPE(type) \ + ((type) == RNG_TYPE_RNGC) +#endif + +/*! Returns non-zero if RNG device is reporting an error. */ +#define RNG_HAS_ERROR() \ + (RNG_READ_REGISTER(RNGC_STATUS) & RNGC_STATUS_ERROR) +/*! Returns non-zero if Bad Key is selected */ +#define RNG_HAS_BAD_KEY() \ + (RNG_READ_REGISTER(RNGC_ERROR) & RNGC_ERROR_STATUS_BAD_KEY) +/*! Returns non-zero if RNG ring oscillators have failed. */ +#define RNG_OSCILLATOR_FAILED() \ + (RNG_READ_REGISTER(RNGC_ERROR) & RNGC_ERROR_STATUS_OSC_ERR) + +/*! Returns maximum number of 32-bit words in the RNG's output fifo. */ +#define RNG_GET_FIFO_SIZE() \ + ((RNG_READ_REGISTER(RNGC_STATUS) & RNGC_STATUS_FIFO_SIZE_MASK) \ + >> RNGC_STATUS_FIFO_SIZE_SHIFT) + +/*! Returns number of 32-bit words currently in the RNG's output fifo. */ +#define RNG_GET_WORDS_IN_FIFO() \ + ((RNG_READ_REGISTER(RNGC_STATUS) & RNGC_STATUS_FIFO_LEVEL_MASK) \ + >> RNGC_STATUS_FIFO_LEVEL_SHIFT) + +/*! Get a random value from the RNG's output FIFO. */ +#define RNG_READ_FIFO() \ + RNG_READ_REGISTER(RNGC_FIFO) + +/*! Put entropy into the RNG's algorithm. + * @param value 32-bit value to add to RNG's entropy. + **/ +#ifdef FSL_HAVE_RNGB +#define RNG_ADD_ENTROPY(value) \ + RNG_WRITE_REGISTER(RNGB_ENTROPY, value) +#else /* RNGC does not have Entropy register */ +#define RNG_ADD_ENTROPY(value) +#endif +/*! Wake the RNG from sleep (low-power) mode. */ +#define RNG_WAKE() 1 +/*! Get the RNG started at generating output. */ +#define RNG_GO() +/*! Put RNG into High Assurance mode. */ +#define RNG_SET_HIGH_ASSURANCE() +/*! Returns non-zero in case of Error during Self Test */ +#define RNG_CHECK_SELF_ERR() \ + (RNG_READ_REGISTER(RNGC_ERROR) & RNGC_ERROR_STATUS_ST_ERR) +/*! Return non-zero in case of Error during Seed Generation */ +#define RNG_CHECK_SEED_ERR() \ + (RNG_READ_REGISTER(RNGC_ERROR) & RNGC_ERROR_STATUS_STAT_ERR) + +/*! Configure RNG for Self Test */ +#define RNG_SELF_TEST() \ +{ \ + register uint32_t command = RNG_READ_REGISTER(RNGC_COMMAND); \ + RNG_WRITE_REGISTER(RNGC_COMMAND, command \ + | RNGC_COMMAND_SELF_TEST); \ +} +/*! Clearing the Error bits in Error Status Register */ +#define RNG_CLEAR_ERR() \ +{ \ + register uint32_t command = RNG_READ_REGISTER(RNGC_COMMAND); \ + RNG_WRITE_REGISTER(RNGC_COMMAND, command \ + | RNGC_COMMAND_CLEAR_ERROR); \ +} + +/*! Return non-zero if Self Test Done */ +#define RNG_SELF_TEST_DONE() \ + (RNG_READ_REGISTER(RNGC_STATUS) & RNGC_STATUS_ST_DONE) +/* Put RNG for SEED Generation */ +#define RNG_SEED_GEN() \ +{ \ + register uint32_t command = RNG_READ_REGISTER(RNGC_COMMAND); \ + RNG_WRITE_REGISTER(RNGC_COMMAND, command \ + | RNGC_COMMAND_SEED); \ +} +/* Return non-zero if RESEED Required */ +#define RNG_RESEED() \ + (RNG_READ_REGISTER(RNGC_STATUS) & RNGC_STATUS_RESEED) + +/*! Return non-zero if the RNG is in High Assurance mode. */ +#define RNG_GET_HIGH_ASSURANCE() (RNG_READ_REGISTER(RNGC_STATUS) & \ + RNGC_STATUS_SEC_STATE) + +/*! Clear all status, error and otherwise. */ +#define RNG_CLEAR_ALL_STATUS() \ + RNG_WRITE_REGISTER(RNGC_COMMAND, \ + RNGC_COMMAND_CLEAR_INTERRUPT \ + | RNGC_COMMAND_CLEAR_ERROR) + +/*! Return non-zero if everything seems OK with the RNG. */ +#define RNG_WORKING() \ + ((RNG_READ_REGISTER(RNGC_ERROR) \ + & (RNGC_ERROR_STATUS_STAT_ERR | RNGC_ERROR_STATUS_RAND_ERR \ + | RNGC_ERROR_STATUS_FIFO_ERR | RNGC_ERROR_STATUS_ST_ERR | \ + RNGC_ERROR_STATUS_OSC_ERR | RNGC_ERROR_STATUS_LFSR_ERR )) == 0) +/*! Return Non zero if SEEDING is DONE */ +#define RNG_SEED_DONE() \ + ((RNG_READ_REGISTER(RNGC_STATUS) & RNGC_STATUS_SEED_DONE) != 0) + +/*! Put the RNG into sleep (low-power) mode. */ +#define RNG_SLEEP() + +/*! Wake the RNG from sleep (low-power) mode. */ + +/*! Mask interrupts so that the driver/OS will not see them. */ +#define RNG_MASK_ALL_INTERRUPTS() \ +{ \ + register uint32_t control = RNG_READ_REGISTER(RNGC_CONTROL); \ + RNG_WRITE_REGISTER(RNGC_CONTROL, control \ + | RNGC_CONTROL_MASK_DONE \ + | RNGC_CONTROL_MASK_ERROR); \ +} +/*! Configuring RNGC for self Test. */ + +#define RNG_AUTO_SEED() \ +{ \ + register uint32_t control = RNG_READ_REGISTER(RNGC_CONTROL); \ + RNG_WRITE_REGISTER(RNGC_CONTROL, control \ + | RNGC_CONTROL_AUTO_SEED); \ +} + +/*! Unmask interrupts so that the driver/OS will see them. */ +#define RNG_UNMASK_ALL_INTERRUPTS() \ +{ \ + register uint32_t control = RNG_READ_REGISTER(RNGC_CONTROL); \ + RNG_WRITE_REGISTER(RNGC_CONTROL, \ + control & ~(RNGC_CONTROL_MASK_DONE|RNGC_CONTROL_MASK_ERROR)); \ +} + +/*! Put RNG to sleep if appropriate. */ +#define RNG_PUT_RNG_TO_SLEEP() + +/*! Wake RNG from sleep if necessary. */ +#define RNG_WAKE_FROM_SLEEP() + +#endif /* RNG TYPE */ + +/* internal functions */ +static os_error_code rng_map_RNG_memory(void); +static os_error_code rng_setup_interrupt_handling(void); +#ifdef RNG_REGISTER_PEEK_POKE +inline static int rng_check_register_offset(uint32_t offset); +inline static int rng_check_register_accessible(uint32_t offset, + int access_write); +#endif /* DEBUG_RNG_REGISTERS */ +static fsl_shw_return_t rng_drain_fifo(uint32_t * random_p, int count_words); +static os_error_code rng_grab_config_values(void); +static void rng_cleanup(void); + +#ifdef FSL_HAVE_RNGA +static void rng_sec_failure(void); +#endif + +#ifdef RNG_REGISTER_DEBUG +static uint32_t dbg_rng_read_register(uint32_t offset); +static void dbg_rng_write_register(uint32_t offset, uint32_t value); +#endif + +#if defined(LINUX_VERSION_CODE) + +EXPORT_SYMBOL(fsl_shw_add_entropy); +EXPORT_SYMBOL(fsl_shw_get_random); + +#ifdef RNG_REGISTER_PEEK_POKE +/* For Linux kernel, export the API functions to other kernel modules */ +EXPORT_SYMBOL(rng_read_register); +EXPORT_SYMBOL(rng_write_register); +#endif /* DEBUG_RNG_REGISTERS */ + + + +MODULE_AUTHOR("Freescale Semiconductor"); +MODULE_DESCRIPTION("Device Driver for RNG"); + +#endif /* LINUX_VERSION_CODE */ + +#endif /* RNG_INTERNALS_H */ diff -urN linux-2.6.26/drivers/mxc/security/rng/include/rng_rnga.h linux-2.6.26-lab126/drivers/mxc/security/rng/include/rng_rnga.h --- linux-2.6.26/drivers/mxc/security/rng/include/rng_rnga.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/include/rng_rnga.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,181 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef RNG_RNGA_H +#define RNG_RNGA_H + +/*! @defgroup rngaregs RNGA Registers + * @ingroup RNG + * These are the definitions for the RNG registers and their offsets + * within the RNG. They are used in the @c register_offset parameter of + * #rng_read_register() and #rng_write_register(). + */ +/*! @addtogroup rngaregs */ +/*! @{ */ + +/*! Control Register. See @ref rngacontrolreg. */ +#define RNGA_CONTROL 0x00 +/*! Status Register. See @ref rngastatusreg. */ +#define RNGA_STATUS 0x04 +/*! Register for adding to the Entropy of the RNG */ +#define RNGA_ENTROPY 0x08 +/*! Register containing latest 32 bits of random value */ +#define RNGA_OUTPUT_FIFO 0x0c +/*! Mode Register. Non-secure mode access only. See @ref rngmodereg. */ +#define RNGA_MODE 0x10 +/*! Verification Control Register. Non-secure mode access only. See + * @ref rngvfctlreg. */ +#define RNGA_VERIFICATION_CONTROL 0x14 +/*! Oscillator Control Counter Register. Non-secure mode access only. + * See @ref rngosccntctlreg. */ +#define RNGA_OSCILLATOR_CONTROL_COUNTER 0x18 +/*! Oscillator 1 Counter Register. Non-secure mode access only. See + * @ref rngosccntreg. */ +#define RNGA_OSCILLATOR1_COUNTER 0x1c +/*! Oscillator 2 Counter Register. Non-secure mode access only. See + * @ref rngosccntreg. */ +#define RNGA_OSCILLATOR2_COUNTER 0x20 +/*! Oscillator Counter Status Register. Non-secure mode access only. See + * @ref rngosccntstatreg. */ +#define RNGA_OSCILLATOR_COUNTER_STATUS 0x24 +/*! @} */ + +/*! Total address space of the RNGA, in bytes */ +#define RNG_ADDRESS_RANGE 0x28 + +/*! @defgroup rngacontrolreg RNGA Control Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngacontrolreg */ +/*! @{ */ +/*! These bits are unimplemented or reserved */ +#define RNGA_CONTROL_ZEROS_MASK 0x0fffffe0 +/*! 'RNG type' - should be 0 for RNGA */ +#define RNGA_CONTROL_RNG_TYPE_MASK 0xf0000000 +/*! Number of bits to shift the type to get it to LSB */ +#define RNGA_CONTROL_RNG_TYPE_SHIFT 28 +/*! Put RNG to sleep */ +#define RNGA_CONTROL_SLEEP 0x00000010 +/*! Clear interrupt & status */ +#define RNGA_CONTROL_CLEAR_INTERRUPT 0x00000008 +/*! Mask interrupt generation */ +#define RNGA_CONTROL_MASK_INTERRUPTS 0x00000004 +/*! Enter into Secure Mode. Notify SCC of security violation should FIFO + * underflow occur. */ +#define RNGA_CONTROL_HIGH_ASSURANCE 0x00000002 +/*! Load data into FIFO */ +#define RNGA_CONTROL_GO 0x00000001 +/*! @} */ + +/*! @defgroup rngastatusreg RNGA Status Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngastatusreg */ +/*! @{ */ +/*! RNG Oscillator not working */ +#define RNGA_STATUS_OSCILLATOR_DEAD 0x80000000 +/*! These bits are undefined or reserved */ +#define RNGA_STATUS_ZEROS1_MASK 0x7f000000 +/*! How big FIFO is, in bytes */ +#define RNGA_STATUS_OUTPUT_FIFO_SIZE_MASK 0x00ff0000 +/*! How many bits right to shift fifo size to make it LSB */ +#define RNGA_STATUS_OUTPUT_FIFO_SIZE_SHIFT 16 +/*! How many bytes are currently in the FIFO */ +#define RNGA_STATUS_OUTPUT_FIFO_LEVEL_MASK 0x0000ff00 +/*! How many bits right to shift fifo level to make it LSB */ +#define RNGA_STATUS_OUTPUT_FIFO_LEVEL_SHIFT 8 +/*! These bits are undefined or reserved. */ +#define RNGA_STATUS_ZEROS2_MASK 0x000000e0 +/*! RNG is sleeping. */ +#define RNGA_STATUS_SLEEP 0x00000010 +/*! Error detected. */ +#define RNGA_STATUS_ERROR_INTERRUPT 0x00000008 +/*! FIFO was empty on some read since last status read. */ +#define RNGA_STATUS_FIFO_UNDERFLOW 0x00000004 +/*! FIFO was empty on most recent read. */ +#define RNGA_STATUS_LAST_READ_STATUS 0x00000002 +/*! Security violation occurred. Will only happen in High Assurance mode. */ +#define RNGA_STATUS_SECURITY_VIOLATION 0x00000001 +/*! @} */ + +/*! @defgroup rngmodereg RNG Mode Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngmodereg */ +/*! @{ */ +/*! These bits are undefined or reserved */ +#define RNGA_MODE_ZEROS_MASK 0xfffffffc +/*! RNG is in / put RNG in Oscillator Frequency Test Mode. */ +#define RNGA_MODE_OSCILLATOR_FREQ_TEST 0x00000002 +/*! Put RNG in verification mode / RNG is in verification mode. */ +#define RNGA_MODE_VERIFICATION 0x00000001 +/*! @} */ + +/*! @defgroup rngvfctlreg RNG Verification Control Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngvfctlreg */ +/*! @{ */ +/*! These bits are undefined or reserved. */ +#define RNGA_VFCTL_ZEROS_MASK 0xfffffff8 +/*! Reset the shift registers. */ +#define RNGA_VFCTL_RESET_SHIFT_REGISTERS 0x00000004 +/*! Drive shift registers from system clock. */ +#define RNGA_VFCTL_FORCE_SYSTEM_CLOCK 0x00000002 +/*! Turn off shift register clocks. */ +#define RNGA_VFCTL_SHIFT_CLOCK_OFF 0x00000001 +/*! @} */ + +/*! + * @defgroup rngosccntctlreg RNG Oscillator Counter Control Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngosccntctlreg */ +/*! @{ */ +/*! These bits are undefined or reserved. */ +#define RNGA_OSCCR_ZEROS_MASK 0xfffc0000 +/*! Bits containing clock cycle counter */ +#define RNGA_OSCCR_CLOCK_CYCLES_MASK 0x0003ffff +/*! Bits to shift right RNG_OSCCR_CLOCK_CYCLES_MASK */ +#define RNGA_OSCCR_CLOCK_CYCLES_SHIFT 0 +/*! @} */ + +/*! + * @defgroup rngosccntreg RNG Oscillator (1 and 2) Counter Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngosccntreg */ +/*! @{ */ +/*! These bits are undefined or reserved. */ +#define RNGA_COUNTER_ZEROS_MASK 0xfff00000 +/*! Bits containing number of clock pulses received from the oscillator. */ +#define RNGA_COUNTER_PULSES_MASK 0x000fffff +/*! Bits right to shift RNG_COUNTER_PULSES_MASK to make it LSB. */ +#define RNGA_COUNTER_PULSES_SHIFT 0 +/*! @} */ + +/*! + * @defgroup rngosccntstatreg RNG Oscillator Counter Status Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngosccntstatreg */ +/*! @{ */ +/*! These bits are undefined or reserved. */ +#define RNGA_COUNTER_STATUS_ZEROS_MASK 0xfffffffc +/*! Oscillator 2 has toggled 0x400 times */ +#define RNGA_COUNTER_STATUS_OSCILLATOR2 0x00000002 +/*! Oscillator 1 has toggled 0x400 times */ +#define RNGA_COUNTER_STATUS_OSCILLATOR1 0x00000001 +/*! @} */ + +#endif /* RNG_RNGA_H */ diff -urN linux-2.6.26/drivers/mxc/security/rng/include/rng_rngc.h linux-2.6.26-lab126/drivers/mxc/security/rng/include/rng_rngc.h --- linux-2.6.26/drivers/mxc/security/rng/include/rng_rngc.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/include/rng_rngc.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,235 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @file rng_rngc.h + * + * Definition of the registers for the RNGB and RNGC. The names start with + * RNGC where they are in common or relate only to the RNGC; the RNGB-only + * definitions begin with RNGB. + * + */ + +#ifndef RNG_RNGC_H +#define RNG_RNGC_H + +#define RNGC_VERSION_MAJOR3 3 + +/*! @defgroup rngcregs RNGB/RNGC Registers + * These are the definitions for the RNG registers and their offsets + * within the RNG. They are used in the @c register_offset parameter of + * #rng_read_register() and #rng_write_register(). + * + * @ingroup RNG + */ +/*! @addtogroup rngcregs */ +/*! @{ */ + +/*! RNGC Version ID Register R/W */ +#define RNGC_VERSION_ID 0x0000 +/*! RNGC Command Register R/W */ +#define RNGC_COMMAND 0x0004 +/*! RNGC Control Register R/W */ +#define RNGC_CONTROL 0x0008 +/*! RNGC Status Register R */ +#define RNGC_STATUS 0x000C +/*! RNGC Error Status Register R */ +#define RNGC_ERROR 0x0010 +/*! RNGC FIFO Register W */ +#define RNGC_FIFO 0x0014 +/*! Undefined */ +#define RNGC_UNDEF_18 0x0018 +/*! RNGB Entropy Register W */ +#define RNGB_ENTROPY 0x0018 +/*! Undefined */ +#define RNGC_UNDEF_1C 0x001C +/*! RNGC Verification Control Register1 R/W */ +#define RNGC_VERIFICATION_CONTROL 0x0020 +/*! Undefined */ +#define RNGC_UNDEF_24 0x0024 +/*! RNGB XKEY Data Register R */ +#define RNGB_XKEY 0x0024 +/*! RNGC Oscillator Counter Control Register1 R/W */ +#define RNGC_OSC_COUNTER_CONTROL 0x0028 +/*! RNGC Oscillator Counter Register1 R */ +#define RNGC_OSC_COUNTER 0x002C +/*! RNGC Oscillator Counter Status Register1 R */ +#define RNGC_OSC_COUNTER_STATUS 0x0030 +/*! @} */ + +/*! @defgroup rngcveridreg RNGB/RNGC Version ID Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngcveridreg */ +/*! @{ */ +/*! These bits are unimplemented or reserved */ +#define RNGC_VERID_ZEROS_MASK 0x0f000000 +/*! Mask for RNG TYPE */ +#define RNGC_VERID_RNG_TYPE_MASK 0xf0000000 +/*! Shift to make RNG TYPE be LSB */ +#define RNGC_VERID_RNG_TYPE_SHIFT 28 +/*! Mask for RNG Chip Version */ +#define RNGC_VERID_CHIP_VERSION_MASK 0x00ff0000 +/*! Shift to make RNG Chip version be LSB */ +#define RNGC_VERID_CHIP_VERSION_SHIFT 16 +/*! Mask for RNG Major Version */ +#define RNGC_VERID_VERSION_MAJOR_MASK 0x0000ff00 +/*! Shift to make RNG Major version be LSB */ +#define RNGC_VERID_VERSION_MAJOR_SHIFT 8 +/*! Mask for RNG Minor Version */ +#define RNGC_VERID_VERSION_MINOR_MASK 0x000000ff +/*! Shift to make RNG Minor version be LSB */ +#define RNGC_VERID_VERSION_MINOR_SHIFT 0 +/*! @} */ + +/*! @defgroup rngccommandreg RNGB/RNGC Command Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngccommandreg */ +/*! @{ */ +/*! These bits are unimplemented or reserved. */ +#define RNGC_COMMAND_ZEROS_MASK 0xffffff8c +/*! Perform a software reset of the RNGC. */ +#define RNGC_COMMAND_SOFTWARE_RESET 0x00000040 +/*! Clear error from Error Status register (and interrupt). */ +#define RNGC_COMMAND_CLEAR_ERROR 0x00000020 +/*! Clear interrupt & status. */ +#define RNGC_COMMAND_CLEAR_INTERRUPT 0x00000010 +/*! Start RNGC seed generation. */ +#define RNGC_COMMAND_SEED 0x00000002 +/*! Perform a self test of (and reset) the RNGC. */ +#define RNGC_COMMAND_SELF_TEST 0x00000001 +/*! @} */ + +/*! @defgroup rngccontrolreg RNGB/RNGC Control Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngccontrolreg */ +/*! @{ */ +/*! These bits are unimplemented or reserved */ +#define RNGC_CONTROL_ZEROS_MASK 0xfffffc8c +/*! Allow access to verification registers. */ +#define RNGC_CONTROL_CTL_ACC 0x00000200 +/*! Put RNGC into deterministic verifcation mode. */ +#define RNGC_CONTROL_VERIF_MODE 0x00000100 +/*! Prevent RNGC from generating interrupts caused by errors. */ +#define RNGC_CONTROL_MASK_ERROR 0x00000040 + +/*! + * Prevent RNGB/RNGC from generating interrupts after Seed Done or Self Test + * Mode completion. + */ +#define RNGC_CONTROL_MASK_DONE 0x00000020 +/*! Allow RNGC to generate a new seed whenever it is needed. */ +#define RNGC_CONTROL_AUTO_SEED 0x00000010 +/*! Set FIFO Underflow Response.*/ +#define RNGC_CONTROL_FIFO_UFLOW_MASK 0x00000003 +/*! Shift value to make FIFO Underflow Response be LSB. */ +#define RNGC_CONTROL_FIFO_UFLOW_SHIFT 0 + +/*! @} */ + +/*! @{ */ +/*! FIFO Underflow should cause ... */ +#define RNGC_CONTROL_FIFO_UFLOW_ZEROS_ERROR 0 +/*! FIFO Underflow should cause ... */ +#define RNGC_CONTROL_FIFO_UFLOW_ZEROS_ERROR2 1 +/*! FIFO Underflow should cause ... */ +#define RNGC_CONTROL_FIFO_UFLOW_BUS_XFR 2 +/*! FIFO Underflow should cause ... */ +#define RNGC_CONTROL_FIFO_UFLOW_ZEROS_INTR 3 +/*! @} */ + +/*! @defgroup rngcstatusreg RNGB/RNGC Status Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngcstatusreg */ +/*! @{ */ +/*! Unused or MBZ. */ +#define RNGC_STATUS_ZEROS_MASK 0x003e0080 +/*! + * Statistical tests pass-fail. Individual bits on indicate failure of a + * particular test. + */ +#define RNGC_STATUS_STAT_TEST_PF_MASK 0xff000000 +/*! Mask to get Statistical PF to be LSB. */ +#define RNGC_STATUS_STAT_TEST_PF_SHIFT 24 +/*! + * Self tests pass-fail. Individual bits on indicate failure of a + * particular test. + */ +#define RNGC_STATUS_ST_PF_MASK 0x00c00000 +/*! Shift value to get Self Test PF field to be LSB. */ +#define RNGC_STATUS_ST_PF_SHIFT 22 +/* TRNG Self test pass-fail */ +#define RNGC_STATUS_ST_PF_TRNG 0x00800000 +/* PRNG Self test pass-fail */ +#define RNGC_STATUS_ST_PF_PRNG 0x00400000 +/*! Error detected in RNGC. See Error Status register. */ +#define RNGC_STATUS_ERROR 0x00010000 +/*! Size of the internal FIFO in 32-bit words. */ +#define RNGC_STATUS_FIFO_SIZE_MASK 0x0000f000 +/*! Shift value to get FIFO Size to be LSB. */ +#define RNGC_STATUS_FIFO_SIZE_SHIFT 12 +/*! The level (available data) of the internal FIFO in 32-bit words. */ +#define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00 +/*! Shift value to get FIFO Level to be LSB. */ +#define RNGC_STATUS_FIFO_LEVEL_SHIFT 8 +/*! A new seed is ready for use. */ +#define RNGC_STATUS_NEXT_SEED_DONE 0x00000040 +/*! The first seed has been generated. */ +#define RNGC_STATUS_SEED_DONE 0x00000020 +/*! Self Test has been completed. */ +#define RNGC_STATUS_ST_DONE 0x00000010 +/*! Reseed is necessary. */ +#define RNGC_STATUS_RESEED 0x00000008 +/*! RNGC is sleeping. */ +#define RNGC_STATUS_SLEEP 0x00000004 +/*! RNGC is currently generating numbers, seeding, generating next seed, or + performing a self test. */ +#define RNGC_STATUS_BUSY 0x00000002 +/*! RNGC is in secure state. */ +#define RNGC_STATUS_SEC_STATE 0x00000001 + +/*! @} */ + +/*! @defgroup rngcerrstatusreg RNGB/RNGC Error Status Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngcerrstatusreg */ +/*! @{ */ +/*! Unused or MBZ. */ +#define RNGC_ERROR_STATUS_ZEROS_MASK 0xffffff80 +/*! Bad Key Error Status */ +#define RNGC_ERROR_STATUS_BAD_KEY 0x00000040 +/*! Random Compare Error. Previous number matched the current number. */ +#define RNGC_ERROR_STATUS_RAND_ERR 0x00000020 +/*! FIFO Underflow. FIFO was read while empty. */ +#define RNGC_ERROR_STATUS_FIFO_ERR 0x00000010 +/*! Statistic Error Statistic Test failed for the last seed. */ +#define RNGC_ERROR_STATUS_STAT_ERR 0x00000008 +/*! Self-test error. Some self test has failed. */ +#define RNGC_ERROR_STATUS_ST_ERR 0x00000004 +/*! + * Oscillator Error. The oscillator may be broken. Clear by hard or soft + * reset. + */ +#define RNGC_ERROR_STATUS_OSC_ERR 0x00000002 +/*! LFSR Error. Clear by hard or soft reset. */ +#define RNGC_ERROR_STATUS_LFSR_ERR 0x00000001 + +/*! @} */ + +/*! Total address space of the RNGB/RNGC registers, in bytes */ +#define RNG_ADDRESS_RANGE 0x34 + +#endif /* RNG_RNGC_H */ diff -urN linux-2.6.26/drivers/mxc/security/rng/include/shw_driver.h linux-2.6.26-lab126/drivers/mxc/security/rng/include/shw_driver.h --- linux-2.6.26/drivers/mxc/security/rng/include/shw_driver.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/include/shw_driver.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,2971 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +#ifndef SHW_DRIVER_H +#define SHW_DRIVER_H + +/* This is a Linux flag meaning 'compiling kernel code'... */ +#ifndef __KERNEL__ +#include +#include +#include +#include +#include +#else +#include "../../sahara2/include/portable_os.h" +#endif /* __KERNEL__ */ + +#include "../../sahara2/include/fsl_platform.h" + +/*! @file shw_driver.h + * + * @brief Header file to use the SHW driver. + * + * The SHW driver is used in two modes: By a user, from the FSL SHW API in user + * space, which goes through /dev/fsl_shw to make open(), ioctl(), and close() + * calls; and by other kernel modules/drivers, which use the FSL SHW API, parts + * of which are supported directly by the SHW driver. + * + * Testing is performed by using the apitest and kernel api test routines + * developed for the Sahara2 driver. + */ +/*#define DIAG_SECURITY_FUNC*/ +/*! Perform a security function. */ +#define SHW_IOCTL_REQUEST 21 + +/* This definition may need a new name, and needs to go somewhere which + * can determine platform, kernel vs. user, os, etc. + */ +#define copy_bytes(out, in, len) memcpy(out, in, len) + + +/*! + * This is part of the IOCTL request type passed between kernel and user space. + * It is added to #SHW_IOCTL_REQUEST to generate the actual value. + */ +typedef enum shw_user_request_t { + SHW_USER_REQ_REGISTER_USER, /*!< Initialize user-kernel discussion. */ + SHW_USER_REQ_DEREGISTER_USER, /*!< Terminate user-kernel discussion. */ + SHW_USER_REQ_GET_RESULTS, /*!< Get information on outstanding + results. */ + SHW_USER_REQ_GET_CAPABILITIES, /*!< Get information on hardware support. */ + SHW_USER_REQ_GET_RANDOM, /*!< Get random data from RNG. */ + SHW_USER_REQ_ADD_ENTROPY, /*!< Add entropy to hardware RNG. */ + SHW_USER_REQ_DROP_PERMS, /*!< Diminish the permissions of a block of + secure memory */ + SHW_USER_REQ_SSTATUS, /*!< Check the status of a block of secure + memory */ + SHW_USER_REQ_SFREE, /*!< Free a block of secure memory */ + SHW_USER_REQ_SCC_ENCRYPT, /*!< Encrypt a region of user-owned secure + memory */ + SHW_USER_REQ_SCC_DECRYPT, /*!< Decrypt a region of user-owned secure + memory */ +} shw_user_request_t; + + +/*! + * @typedef scc_partition_status_t + */ +/** Partition status information. */ +typedef enum fsl_shw_partition_status_t { + FSL_PART_S_UNUSABLE, /*!< Partition not implemented */ + FSL_PART_S_UNAVAILABLE, /*!< Partition owned by other host */ + FSL_PART_S_AVAILABLE, /*!< Partition available */ + FSL_PART_S_ALLOCATED, /*!< Partition owned by host but not engaged + */ + FSL_PART_S_ENGAGED, /*!< Partition owned by host and engaged */ +} fsl_shw_partition_status_t; + + +/* + * Structure passed during user ioctl() calls to manage secure partitions. + */ +typedef struct scc_partition_info_t { + uint32_t user_base; /*!< Userspace pointer to base of partition */ + uint32_t permissions; /*!< Permissions to give the partition (only + used in call to _DROP_PERMS) */ + fsl_shw_partition_status_t status; /*!< Status of the partition */ +} scc_partition_info_t; + + +/****************************************************************************** + * Enumerations + *****************************************************************************/ +/*! + * Flags for the state of the User Context Object (#fsl_shw_uco_t). + */ +typedef enum fsl_shw_user_ctx_flags_t +{ + /*! + * API will block the caller until operation completes. The result will be + * available in the return code. If this is not set, user will have to get + * results using #fsl_shw_get_results(). + */ + FSL_UCO_BLOCKING_MODE = 0x01, + /*! + * User wants callback (at the function specified with + * #fsl_shw_uco_set_callback()) when the operation completes. This flag is + * valid only if #FSL_UCO_BLOCKING_MODE is not set. + */ + FSL_UCO_CALLBACK_MODE = 0x02, + /*! Do not free descriptor chain after driver (adaptor) finishes */ + FSL_UCO_SAVE_DESC_CHAIN = 0x04, + /*! + * User has made at least one request with callbacks requested, so API is + * ready to handle others. + */ + FSL_UCO_CALLBACK_SETUP_COMPLETE = 0x08, + /*! + * (virtual) pointer to descriptor chain is completely linked with physical + * (DMA) addresses, ready for the hardware. This flag should not be used + * by FSL SHW API programs. + */ + FSL_UCO_CHAIN_PREPHYSICALIZED = 0x10, + /*! + * The user has changed the context but the changes have not been copied to + * the kernel driver. + */ + FSL_UCO_CONTEXT_CHANGED = 0x20, + /*! Internal Use. This context belongs to a user-mode API user. */ + FSL_UCO_USERMODE_USER = 0x40, +} fsl_shw_user_ctx_flags_t; + + +/*! + * Return code for FSL_SHW library. + * + * These codes may be returned from a function call. In non-blocking mode, + * they will appear as the status in a Result Object. + */ +/* REQ-FSLSHW-ERR-001 */ +typedef enum fsl_shw_return_t +{ + /*! + * No error. As a function return code in Non-blocking mode, this may + * simply mean that the operation was accepted for eventual execution. + */ + FSL_RETURN_OK_S = 0, + /*! Failure for non-specific reason. */ + FSL_RETURN_ERROR_S, + /*! + * Operation failed because some resource was not able to be allocated. + */ + FSL_RETURN_NO_RESOURCE_S, + /*! Crypto algorithm unrecognized or improper. */ + FSL_RETURN_BAD_ALGORITHM_S, + /*! Crypto mode unrecognized or improper. */ + FSL_RETURN_BAD_MODE_S, + /*! Flag setting unrecognized or inconsistent. */ + FSL_RETURN_BAD_FLAG_S, + /*! Improper or unsupported key length for algorithm. */ + FSL_RETURN_BAD_KEY_LENGTH_S, + /*! Improper parity in a (DES, TDES) key. */ + FSL_RETURN_BAD_KEY_PARITY_S, + /*! + * Improper or unsupported data length for algorithm or internal buffer. + */ + FSL_RETURN_BAD_DATA_LENGTH_S, + /*! Authentication / Integrity Check code check failed. */ + FSL_RETURN_AUTH_FAILED_S, + /*! A memory error occurred. */ + FSL_RETURN_MEMORY_ERROR_S, + /*! An error internal to the hardware occurred. */ + FSL_RETURN_INTERNAL_ERROR_S, + /*! ECC detected Point at Infinity */ + FSL_RETURN_POINT_AT_INFINITY_S, + /*! ECC detected No Point at Infinity */ + FSL_RETURN_POINT_NOT_AT_INFINITY_S, + /*! GCD is One */ + FSL_RETURN_GCD_IS_ONE_S, + /*! GCD is not One */ + FSL_RETURN_GCD_IS_NOT_ONE_S, + /*! Candidate is Prime */ + FSL_RETURN_PRIME_S, + /*! Candidate is not Prime */ + FSL_RETURN_NOT_PRIME_S, + /*! N register loaded improperly with even value */ + FSL_RETURN_EVEN_MODULUS_ERROR_S, + /*! Divisor is zero. */ + FSL_RETURN_DIVIDE_BY_ZERO_ERROR_S, + /*! Bad Exponent or Scalar value for Point Multiply */ + FSL_RETURN_BAD_EXPONENT_ERROR_S, + /*! RNG hardware problem. */ + FSL_RETURN_OSCILLATOR_ERROR_S, + /*! RNG hardware problem. */ + FSL_RETURN_STATISTICS_ERROR_S, +} fsl_shw_return_t; + + +/*! + * Algorithm Identifier. + * + * Selection of algorithm will determine how large the block size of the + * algorithm is. Context size is the same length unless otherwise specified. + * Selection of algorithm also affects the allowable key length. + */ +typedef enum fsl_shw_key_alg_t +{ + /*! + * Key will be used to perform an HMAC. Key size is 1 to 64 octets. Block + * size is 64 octets. + */ + FSL_KEY_ALG_HMAC, + /*! + * Advanced Encryption Standard (Rijndael). Block size is 16 octets. Key + * size is 16 octets. (The single choice of key size is a Sahara platform + * limitation.) + */ + FSL_KEY_ALG_AES, + /*! + * Data Encryption Standard. Block size is 8 octets. Key size is 8 + * octets. + */ + FSL_KEY_ALG_DES, + /*! + * 2- or 3-key Triple DES. Block size is 8 octets. Key size is 16 octets + * for 2-key Triple DES, and 24 octets for 3-key. + */ + FSL_KEY_ALG_TDES, + /*! + * ARC4. No block size. Context size is 259 octets. Allowed key size is + * 1-16 octets. (The choices for key size are a Sahara platform + * limitation.) + */ + FSL_KEY_ALG_ARC4, +} fsl_shw_key_alg_t; + + +/*! + * Mode selector for Symmetric Ciphers. + * + * The selection of mode determines how a cryptographic algorithm will be + * used to process the plaintext or ciphertext. + * + * For all modes which are run block-by-block (that is, all but + * #FSL_SYM_MODE_STREAM), any partial operations must be performed on a text + * length which is multiple of the block size. Except for #FSL_SYM_MODE_CTR, + * these block-by-block algorithms must also be passed a total number of octets + * which is a multiple of the block size. + * + * In modes which require that the total number of octets of data be a multiple + * of the block size (#FSL_SYM_MODE_ECB and #FSL_SYM_MODE_CBC), and the user + * has a total number of octets which are not a multiple of the block size, the + * user must perform any necessary padding to get to the correct data length. + */ +typedef enum fsl_shw_sym_mode_t +{ + /*! + * Stream. There is no associated block size. Any request to process data + * may be of any length. This mode is only for ARC4 operations, and is + * also the only mode used for ARC4. + */ + FSL_SYM_MODE_STREAM, + + /*! + * Electronic Codebook. Each block of data is encrypted/decrypted. The + * length of the data stream must be a multiple of the block size. This + * mode may be used for DES, 3DES, and AES. The block size is determined + * by the algorithm. + */ + FSL_SYM_MODE_ECB, + /*! + * Cipher-Block Chaining. Each block of data is encrypted/decrypted and + * then "chained" with the previous block by an XOR function. Requires + * context to start the XOR (previous block). This mode may be used for + * DES, 3DES, and AES. The block size is determined by the algorithm. + */ + FSL_SYM_MODE_CBC, + /*! + * Counter. The counter is encrypted, then XORed with a block of data. + * The counter is then incremented (using modulus arithmetic) for the next + * block. The final operation may be non-multiple of block size. This mode + * may be used for AES. The block size is determined by the algorithm. + */ + FSL_SYM_MODE_CTR, +} fsl_shw_sym_mode_t; + + +/*! + * Algorithm selector for Cryptographic Hash functions. + * + * Selection of algorithm determines how large the context and digest will be. + * Context is the same size as the digest (resulting hash), unless otherwise + * specified. + */ +typedef enum fsl_shw_hash_alg_t +{ + FSL_HASH_ALG_MD5, /*!< MD5 algorithm. Digest is 16 octets. */ + FSL_HASH_ALG_SHA1, /*!< SHA-1 (aka SHA or SHA-160) algorithm. + Digest is 20 octets. */ + FSL_HASH_ALG_SHA224, /*!< SHA-224 algorithm. Digest is 28 octets, + though context is 32 octets. */ + FSL_HASH_ALG_SHA256 /*!< SHA-256 algorithm. Digest is 32 + octets. */ +} fsl_shw_hash_alg_t; + + +/*! + * The type of Authentication-Cipher function which will be performed. + */ +typedef enum fsl_shw_acc_mode_t +{ + /*! + * CBC-MAC for Counter. Requires context and modulus. Final operation may + * be non-multiple of block size. This mode may be used for AES. + */ + FSL_ACC_MODE_CCM, + /*! + * SSL mode. Not supported. Combines HMAC and encrypt (or decrypt). + * Needs one key object for encryption, another for the HMAC. The usual + * hashing and symmetric encryption algorithms are supported. + */ + FSL_ACC_MODE_SSL +} fsl_shw_acc_mode_t; + + +/* REQ-FSLSHW-PINTFC-COA-HCO-001 */ +/*! + * Flags which control a Hash operation. + */ +typedef enum fsl_shw_hash_ctx_flags_t +{ + FSL_HASH_FLAGS_INIT = 0x01, /*!< Context is empty. Hash is started + from scratch, with a message-processed + count of zero. */ + FSL_HASH_FLAGS_SAVE = 0x02, /*!< Retrieve context from hardware after + hashing. If used with the + #FSL_HASH_FLAGS_FINALIZE flag, the final + digest value will be saved in the + object. */ + FSL_HASH_FLAGS_LOAD = 0x04, /*!< Place context into hardware before + hashing. */ + FSL_HASH_FLAGS_FINALIZE = 0x08, /*!< PAD message and perform final digest + operation. If user message is + pre-padded, this flag should not be + used. */ +} fsl_shw_hash_ctx_flags_t; + + +/*! + * Flags which control an HMAC operation. + * + * These may be combined by ORing them together. See #fsl_shw_hmco_set_flags() + * and #fsl_shw_hmco_clear_flags(). + */ +typedef enum fsl_shw_hmac_ctx_flags_t +{ + FSL_HMAC_FLAGS_INIT = 1, /**< Message context is empty. HMAC is + started from scratch (with key) or from + precompute of inner hash, depending on + whether + #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT is + set. */ + FSL_HMAC_FLAGS_SAVE = 2, /**< Retrieve ongoing context from hardware + after hashing. If used with the + #FSL_HMAC_FLAGS_FINALIZE flag, the final + digest value (HMAC) will be saved in the + object. */ + FSL_HMAC_FLAGS_LOAD = 4, /**< Place ongoing context into hardware + before hashing. */ + FSL_HMAC_FLAGS_FINALIZE = 8, /**< PAD message and perform final HMAC + operations of inner and outer hashes. */ + FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT = 16 /**< This means that the context + contains precomputed inner and outer + hash values. */ +} fsl_shw_hmac_ctx_flags_t; + + +/** + * Flags to control use of the #fsl_shw_scco_t. + * + * These may be ORed together to get the desired effect. + * See #fsl_shw_scco_set_flags() and #fsl_shw_scco_clear_flags() + */ +typedef enum fsl_shw_sym_ctx_flags_t +{ + /** + * Context is empty. In ARC4, this means that the S-Box needs to be + * generated from the key. In #FSL_SYM_MODE_CBC mode, this allows an IV of + * zero to be specified. In #FSL_SYM_MODE_CTR mode, it means that an + * initial CTR value of zero is desired. + */ + FSL_SYM_CTX_INIT = 1, + /** + * Load context from object into hardware before running cipher. In + * #FSL_SYM_MODE_CTR mode, this would refer to the Counter Value. + */ + FSL_SYM_CTX_LOAD = 2, + /** + * Save context from hardware into object after running cipher. In + * #FSL_SYM_MODE_CTR mode, this would refer to the Counter Value. + */ + FSL_SYM_CTX_SAVE = 4, + /** + * Context (SBox) is to be unwrapped and wrapped on each use. + * This flag is unsupported. + * */ + FSL_SYM_CTX_PROTECT = 8, +} fsl_shw_sym_ctx_flags_t; + + +/** + * Flags which describe the state of the #fsl_shw_sko_t. + * + * These may be ORed together to get the desired effect. + * See #fsl_shw_sko_set_flags() and #fsl_shw_sko_clear_flags() + */ +typedef enum fsl_shw_key_flags_t +{ + FSL_SKO_KEY_IGNORE_PARITY = 1, /*!< If algorithm is DES or 3DES, do not + validate the key parity bits. */ + FSL_SKO_KEY_PRESENT = 2, /*!< Clear key is present in the object. */ + FSL_SKO_KEY_ESTABLISHED = 4, /*!< Key has been established for use. This + feature is not available for all + platforms, nor for all algorithms and + modes.*/ + FSL_SKO_USE_SECRET_KEY = 8, /*!< Use device-unique key. Not always + available. */ + FSL_SKO_KEY_SW_KEY = 16, /*!< Clear key can be provided to the user */ + FSL_SKO_KEY_SELECT_PF_KEY = 32, /*!< Internal flag to show that this key + references one of the hardware keys, and + its value is in pf_key. */ +} fsl_shw_key_flags_t; + + +/** + * Type of value which is associated with an established key. + */ +typedef uint64_t key_userid_t; + + +/** + * Flags which describe the state of the #fsl_shw_acco_t. + * + * The @a FSL_ACCO_CTX_INIT and @a FSL_ACCO_CTX_FINALIZE flags, when used + * together, provide for a one-shot operation. + */ +typedef enum fsl_shw_auth_ctx_flags_t +{ + FSL_ACCO_CTX_INIT = 1, /**< Initialize Context(s) */ + FSL_ACCO_CTX_LOAD = 2, /**< Load intermediate context(s). + This flag is unsupported. */ + FSL_ACCO_CTX_SAVE = 4, /**< Save intermediate context(s). + This flag is unsupported. */ + FSL_ACCO_CTX_FINALIZE = 8, /**< Create MAC during this operation. */ + FSL_ACCO_NIST_CCM = 0x10, /**< Formatting of CCM input data is + performed by calls to + #fsl_shw_ccm_nist_format_ctr_and_iv() and + #fsl_shw_ccm_nist_update_ctr_and_iv(). */ +} fsl_shw_auth_ctx_flags_t; + + +/** + * The operation which controls the behavior of #fsl_shw_establish_key(). + * + * These values are passed to #fsl_shw_establish_key(). + */ +typedef enum fsl_shw_key_wrap_t +{ + FSL_KEY_WRAP_CREATE, /**< Generate a key from random values. */ + FSL_KEY_WRAP_ACCEPT, /**< Use the provided clear key. */ + FSL_KEY_WRAP_UNWRAP /**< Unwrap a previously wrapped key. */ +} fsl_shw_key_wrap_t; + + +/** + * Modulus Selector for CTR modes. + * + * The incrementing of the Counter value may be modified by a modulus. If no + * modulus is needed or desired for AES, use #FSL_CTR_MOD_128. + */ +typedef enum fsl_shw_ctr_mod_t +{ + FSL_CTR_MOD_8, /**< Run counter with modulus of 2^8. */ + FSL_CTR_MOD_16, /**< Run counter with modulus of 2^16. */ + FSL_CTR_MOD_24, /**< Run counter with modulus of 2^24. */ + FSL_CTR_MOD_32, /**< Run counter with modulus of 2^32. */ + FSL_CTR_MOD_40, /**< Run counter with modulus of 2^40. */ + FSL_CTR_MOD_48, /**< Run counter with modulus of 2^48. */ + FSL_CTR_MOD_56, /**< Run counter with modulus of 2^56. */ + FSL_CTR_MOD_64, /**< Run counter with modulus of 2^64. */ + FSL_CTR_MOD_72, /**< Run counter with modulus of 2^72. */ + FSL_CTR_MOD_80, /**< Run counter with modulus of 2^80. */ + FSL_CTR_MOD_88, /**< Run counter with modulus of 2^88. */ + FSL_CTR_MOD_96, /**< Run counter with modulus of 2^96. */ + FSL_CTR_MOD_104, /**< Run counter with modulus of 2^104. */ + FSL_CTR_MOD_112, /**< Run counter with modulus of 2^112. */ + FSL_CTR_MOD_120, /**< Run counter with modulus of 2^120. */ + FSL_CTR_MOD_128 /**< Run counter with modulus of 2^128. */ +} fsl_shw_ctr_mod_t; + + +/** + * A work type associated with a work/result queue request. + */ +typedef enum shw_work_type_t +{ + SHW_WORK_GET_RANDOM = 1, /**< fsl_shw_get_random() request. */ + SHW_WORK_ADD_RANDOM, /**< fsl_shw_add_entropy() request. */ +} shw_work_type_t; + + +/** + * Permissions flags for Secure Partitions + */ +typedef enum fsl_shw_permission_t +{ +/** SCM Access Permission: Do not zeroize/deallocate partition on SMN Fail state */ + FSL_PERM_NO_ZEROIZE = 0x80000000, +/** SCM Access Permission: Enforce trusted key read in */ + FSL_PERM_TRUSTED_KEY_READ = 0x40000000, +/** SCM Access Permission: Ignore Supervisor/User mode in permission determination */ + FSL_PERM_HD_S = 0x00000800, +/** SCM Access Permission: Allow Read Access to Host Domain */ + FSL_PERM_HD_R = 0x00000400, +/** SCM Access Permission: Allow Write Access to Host Domain */ + FSL_PERM_HD_W = 0x00000200, +/** SCM Access Permission: Allow Execute Access to Host Domain */ + FSL_PERM_HD_X = 0x00000100, +/** SCM Access Permission: Allow Read Access to Trusted Host Domain */ + FSL_PERM_TH_R = 0x00000040, +/** SCM Access Permission: Allow Write Access to Trusted Host Domain */ + FSL_PERM_TH_W = 0x00000020, +/** SCM Access Permission: Allow Read Access to Other/World Domain */ + FSL_PERM_OT_R = 0x00000004, +/** SCM Access Permission: Allow Write Access to Other/World Domain */ + FSL_PERM_OT_W = 0x00000002, +/** SCM Access Permission: Allow Execute Access to Other/World Domain */ + FSL_PERM_OT_X = 0x00000001, +} fsl_shw_permission_t; + +/*! + * Select the cypher mode to use for partition cover/uncover operations. + * + * They currently map directly to the values used in the SCC2 driver, but this + * is not guarinteed behavior. + */ +typedef enum fsl_shw_cypher_mode_t +{ + FSL_SHW_CYPHER_MODE_ECB = 1, /*!< ECB mode */ + FSL_SHW_CYPHER_MODE_CBC = 2, /*!< CBC mode */ +} fsl_shw_cypher_mode_t; + +/*! + * Which platform key should be presented for cryptographic use. + */ +typedef enum fsl_shw_pf_key_t { + FSL_SHW_PF_KEY_IIM, /*!< Present fused IIM key */ + FSL_SHW_PF_KEY_PRG, /*!< Present Program key */ + FSL_SHW_PF_KEY_IIM_PRG, /*!< Present IIM ^ Program key */ + FSL_SHW_PF_KEY_IIM_RND, /*!< Present Random key */ + FSL_SHW_PF_KEY_RND, /*!< Present IIM ^ Random key */ +} fsl_shw_pf_key_t; + +/*! + * The various security tamper events + */ +typedef enum fsl_shw_tamper_t { + FSL_SHW_TAMPER_NONE, /*!< No error detected */ + FSL_SHW_TAMPER_WTD, /*!< wire-mesh tampering det */ + FSL_SHW_TAMPER_ETBD, /*!< ext tampering det: input B */ + FSL_SHW_TAMPER_ETAD, /*!< ext tampering det: input A */ + FSL_SHW_TAMPER_EBD, /*!< external boot detected */ + FSL_SHW_TAMPER_SAD, /*!< security alarm detected */ + FSL_SHW_TAMPER_TTD, /*!< temperature tampering det */ + FSL_SHW_TAMPER_CTD, /*!< clock tampering det */ + FSL_SHW_TAMPER_VTD, /*!< voltage tampering det */ + FSL_SHW_TAMPER_MCO, /*!< monotonic counter overflow */ + FSL_SHW_TAMPER_TCO, /*!< time counter overflow */ +} fsl_shw_tamper_t; + +/* + * Structure passed during user ioctl() calls to manage data stored in secure + * partitions. + */ + +typedef struct scc_region_t { + uint32_t partition_base; /*!< Base address of partition */ + uint32_t offset; /*!< Byte offset into partition */ + uint32_t length; /*!< Number of bytes in request */ + uint8_t *black_data; /*!< Address of cipher text */ + uint64_t owner_id; /*!< user's secret */ + fsl_shw_cypher_mode_t cypher_mode; /*!< ECB or CBC */ + uint32_t IV[4]; /*!< IV for CBC mode */ +} scc_region_t; + +/****************************************************************************** + * Data Structures + *****************************************************************************/ + +/** + * Initialization Object + */ +typedef struct fsl_sho_ibo +{ +} fsl_sho_ibo_t; + + +/** + * Common Entry structure for work queues, results queues. + */ +typedef struct shw_queue_entry_t { + struct shw_queue_entry_t* next; /**< Next entry in queue. */ + struct fsl_shw_uco_t* user_ctx; /**< Associated user context. */ + uint32_t flags; /**< User context flags at time of request. */ + void (*callback)(struct fsl_shw_uco_t* uco); /**< Any callback request. */ + uint32_t user_ref; /**< User's reference for this request. */ + fsl_shw_return_t code; /**< FSL SHW result of this operation. */ + uint32_t detail1; /**< Any extra error info. */ + uint32_t detail2; /**< More any extra error info. */ + void* user_mode_req; /**< Pointer into user space. */ + uint32_t (*postprocess)(struct shw_queue_entry_t* q); /**< (internal) + function to call + when this operation + completes. + */ +} shw_queue_entry_t; + + +/** + * A queue. Fields must be initialized to NULL before use. + */ +typedef struct shw_queue_t +{ + struct shw_queue_entry_t* head; /**< First entry in queue. */ + struct shw_queue_entry_t* tail; /**< Last entry. */ +} shw_queue_t; + + +/** + * Secure Partition information + */ +typedef struct fsl_shw_spo_t +{ + uint32_t user_base; + void* kernel_base; + struct fsl_shw_spo_t* next; +} fsl_shw_spo_t; + + +/* REQ-FSLSHW-PINTFC-COA-UCO-001 */ +/** + * User Context Object + */ +typedef struct fsl_shw_uco_t +{ + int openfd; /**< user-mode file descriptor */ + uint32_t user_ref; /**< User's reference */ + void (*callback)(struct fsl_shw_uco_t* uco); /**< User's callback fn */ + uint32_t flags; /**< from fsl_shw_user_ctx_flags_t */ + unsigned pool_size; /**< maximum size of user result pool */ +#ifdef __KERNEL__ + shw_queue_t result_pool; /**< where non-blocking results go */ + os_process_handle_t process; /**< remember for signalling User mode */ + fsl_shw_spo_t* partition; /**< chain of secure partitions owned by + the user */ +#endif + struct fsl_shw_uco_t* next; /**< To allow user-mode chaining of contexts, + for signalling and in kernel, to link user + contexts. */ + fsl_shw_pf_key_t wrap_key; /*!< What key for ciphering T */ +} fsl_shw_uco_t; + + +/* REQ-FSLSHW-PINTFC-API-GEN-006 ?? */ +/** + * Result object + */ +typedef struct fsl_shw_result_t +{ + uint32_t user_ref; /**< User's reference at time of request. */ + fsl_shw_return_t code; /**< Return code from request. */ + uint32_t detail1; /**< Extra error info. Unused in SHW driver. */ + uint32_t detail2; /**< Extra error info. Unused in SHW driver. */ + void* user_req; /**< Pointer to original user request. */ +} fsl_shw_result_t; + + +/** + * Keystore Object + */ +typedef struct fsl_shw_kso_t +{ +#ifdef __KERNEL__ + os_lock_t lock; /**< Pointer to lock that controls access to + the keystore. */ +#endif + void* user_data; /**< Pointer to user structure that handles + the internals of the keystore. */ + fsl_shw_return_t (*data_init) (fsl_shw_uco_t* user_ctx, + void** user_data); + void (*data_cleanup) (fsl_shw_uco_t* user_ctx, + void** user_data); + fsl_shw_return_t (*slot_verify_access)(void* user_data, uint64_t owner_id, + uint32_t slot); + fsl_shw_return_t (*slot_alloc) (void* user_data, uint32_t size_bytes, + uint64_t owner_id, uint32_t* slot); + fsl_shw_return_t (*slot_dealloc) (void* user_data, + uint64_t owner_id, uint32_t slot); + void* (*slot_get_address) (void* user_data, uint32_t slot); + uint32_t (*slot_get_base) (void* user_data, uint32_t slot); + uint32_t (*slot_get_offset) (void* user_data, uint32_t slot); + uint32_t (*slot_get_slot_size) (void* user_data, uint32_t slot); +} fsl_shw_kso_t; + + +/* REQ-FSLSHW-PINTFC-COA-SKO-001 */ +/** + * Secret Key Context Object + */ +typedef struct fsl_shw_sko_t +{ + uint32_t flags; /**< Flags from #fsl_shw_sym_ctx_flags_t. */ + fsl_shw_key_alg_t algorithm; /**< Algorithm for this key. */ + key_userid_t userid; /**< User's identifying value for Black key. */ + uint32_t handle; /**< Reference in SCC driver for Red key. */ + uint16_t key_length; /**< Length of stored key, in bytes. */ + uint8_t key[64]; /**< Bytes of stored key. */ + struct fsl_shw_kso_t* keystore; /**< If present, key is in keystore */ + fsl_shw_pf_key_t pf_key; /*!< What key to select for use when this key + is doing ciphering. If FSL_SHW_PF_KEY_PRG + or FSL_SHW_PF_KEY_PRG_IIM is the value, then + a 'present' or 'established' key will be + programed into the PK. */ +} fsl_shw_sko_t; + + +/* REQ-FSLSHW-PINTFC-COA-CO-001 */ +/** + * Platform Capability Object + * + * Pointer to this structure is returned by fsl_shw_get_capabilities() and + * queried with the various fsl_shw_pco_() functions. + */ +typedef struct fsl_shw_pco_t +{ + int api_major; /**< Major version number for API. */ + int api_minor; /**< Minor version number for API. */ + int driver_major; /**< Major version of some driver. */ + int driver_minor; /**< Minor version of some driver. */ + unsigned sym_algorithm_count; /**< Number of sym_algorithms. */ + fsl_shw_key_alg_t* sym_algorithms; /**< Pointer to array. */ + unsigned sym_mode_count; /**< Number of sym_modes. */ + fsl_shw_sym_mode_t* sym_modes; /**< Pointer to array. */ + unsigned hash_algorithm_count; /**< Number of hash_algorithms. */ + fsl_shw_hash_alg_t* hash_algorithms; /**< Pointer to array */ + uint8_t sym_support[5][4]; /**< indexed by key alg then mode */ + + int scc_driver_major; + int scc_driver_minor; + int scm_version; /**< Version from SCM Configuration register */ + int smn_version; /**< Version from SMN Status register */ + int block_size_bytes; /**< Number of bytes per block of RAM; also + block size of the crypto algorithm. */ + union { + struct scc_info { + int black_ram_size_blocks; /**< Number of blocks of Black RAM */ + int red_ram_size_blocks; /**< Number of blocks of Red RAM */ + } scc_info; + struct scc2_info { + int partition_size_bytes; /**< Number of bytes in each partition */ + int partition_count; /**< Number of partitions on this platform */ + } scc2_info; + } u; +} fsl_shw_pco_t; + + +/* REQ-FSLSHW-PINTFC-COA-HCO-001 */ +/** + * Hash Context Object + */ +typedef struct fsl_shw_hco_t /* fsl_shw_hash_context_object */ +{ + fsl_shw_hash_alg_t algorithm; /**< Algorithm for this context. */ + uint32_t flags; /**< Flags from + #fsl_shw_hash_ctx_flags_t. */ + uint8_t digest_length; /**< hash result length in bytes */ + uint8_t context_length; /**< Context length in bytes */ + uint8_t context_register_length; /**< in bytes */ + uint32_t context[9]; /**< largest digest + msg size */ +} fsl_shw_hco_t; + + +/* REQ-FSLSHW-PINTFC-COA-HCO-001 */ +/** + * HMAC Context Object + */ +typedef struct fsl_shw_hmco_t /* fsl_shw_hmac_context_object */ +{ + fsl_shw_hash_alg_t algorithm; /**< Hash algorithm for the HMAC. */ + uint32_t flags; /**< Flags from + #fsl_shw_hmac_ctx_flags_t. */ + uint8_t digest_length; /**< in bytes */ + uint8_t context_length; /**< in bytes */ + uint8_t context_register_length; /**< in bytes */ + uint32_t ongoing_context[9]; /**< largest digest + msg + size */ + uint32_t inner_precompute[9]; /**< largest digest + msg + size */ + uint32_t outer_precompute[9]; /**< largest digest + msg + size */ +} fsl_shw_hmco_t; + + +/* REQ-FSLSHW-PINTFC-COA-SCCO-001 */ +/** + * Symmetric Crypto Context Object Context Object + */ +typedef struct fsl_shw_scco_t +{ + uint32_t flags; /**< Flags from #fsl_shw_sym_ctx_flags_t. */ + unsigned block_size_bytes; /**< Both block and ctx size */ + fsl_shw_sym_mode_t mode; /**< Symmetric mode for this context. */ + /* Could put modulus plus 16-octet context in union with arc4 + sbox+ptrs... */ + fsl_shw_ctr_mod_t modulus_exp; /**< Exponent value for CTR modulus */ + uint8_t context[8]; /**< Stored context. Large enough + for 3DES. */ +} fsl_shw_scco_t; + + +/** + * Authenticate-Cipher Context Object + + * An object for controlling the function of, and holding information about, + * data for the authenticate-cipher functions, #fsl_shw_gen_encrypt() and + * #fsl_shw_auth_decrypt(). + */ +typedef struct fsl_shw_acco_t +{ + uint32_t flags; /**< See #fsl_shw_auth_ctx_flags_t for + meanings */ + fsl_shw_acc_mode_t mode; /**< CCM only */ + uint8_t mac_length; /**< User's value for length */ + unsigned q_length; /**< NIST parameter - */ + fsl_shw_scco_t cipher_ctx_info; /**< For running + encrypt/decrypt. */ + union { + fsl_shw_scco_t CCM_ctx_info; /**< For running the CBC in + AES-CCM. */ + fsl_shw_hco_t hash_ctx_info; /**< For running the hash */ + } auth_info; /**< "auth" info struct */ + uint8_t unencrypted_mac[16]; /**< max block size... */ +} fsl_shw_acco_t; + + +/** + * Common header in request structures between User-mode API and SHW driver. + */ +struct shw_req_header { + uint32_t flags; /**< Flags - from user-mode context. */ + uint32_t user_ref; /**< Reference - from user-mode context. */ + fsl_shw_return_t code; /**< Result code for operation. */ +}; + +/** + * Used by user-mode API to retrieve completed non-blocking results in + * SHW_USER_REQ_GET_RESULTS ioctl(). + */ +struct results_req { + struct shw_req_header hdr; /**< Boilerplate. */ + unsigned requested; /**< number of results requested, */ + unsigned actual; /**< number of results obtained. */ + fsl_shw_result_t *results; /**< pointer to memory to hold results. */ +}; + + +/** + * Used by user-mode API to retrieve hardware capabilities in + * SHW_USER_REQ_GET_CAPABILITIES ioctl(). + */ +struct capabilities_req { + struct shw_req_header hdr; /**< Boilerplate. */ + unsigned size; /**< Size, in bytes, capabilities. */ + fsl_shw_pco_t* capabilities; /**< Place to copy out the info. */ +}; + + +/** + * Used by user-mode API to get a random number + */ +struct get_random_req { + struct shw_req_header hdr; /**< Boilerplate. */ + unsigned size; /**< Size, in bytes, of random. */ + uint8_t* random; /**< Place to copy out the random number. */ +}; + + +/** + * Used by API to add entropy to a random number generator + */ +struct add_entropy_req { + struct shw_req_header hdr; /**< Boilerplate. */ + unsigned size; /**< Size, in bytes, of entropy. */ + uint8_t* entropy; /**< Location of the entropy to be added. */ +}; + + +/****************************************************************************** + * External variables + *****************************************************************************/ +#ifdef __KERNEL__ +extern os_lock_t shw_queue_lock; + +extern fsl_shw_uco_t* user_list; +#endif + + +/****************************************************************************** + * Access Macros for Objects + *****************************************************************************/ +/** + * Get FSL SHW API version + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] pcmajor A pointer to where the major version + * of the API is to be stored. + * @param[out] pcminor A pointer to where the minor version + * of the API is to be stored. + */ +#define fsl_shw_pco_get_version(pcobject, pcmajor, pcminor) \ +do { \ + *(pcmajor) = (pcobject)->api_major; \ + *(pcminor) = (pcobject)->api_minor; \ +} while (0) + + +/** + * Get underlying driver version. + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] pcmajor A pointer to where the major version + * of the driver is to be stored. + * @param[out] pcminor A pointer to where the minor version + * of the driver is to be stored. + */ +#define fsl_shw_pco_get_driver_version(pcobject, pcmajor, pcminor) \ +do { \ + *(pcmajor) = (pcobject)->driver_major; \ + *(pcminor) = (pcobject)->driver_minor; \ +} while (0) + + +/** + * Get list of symmetric algorithms supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] pcalgorithms A pointer to where to store the location of + * the list of algorithms. + * @param[out] pcacount A pointer to where to store the number of + * algorithms in the list at @a algorithms. + */ +#define fsl_shw_pco_get_sym_algorithms(pcobject, pcalgorithms, pcacount) \ +do { \ + *(pcalgorithms) = (pcobject)->sym_algorithms; \ + *(pcacount) = (pcobject)->sym_algorithm_count; \ +} while (0) + + +/** + * Get list of symmetric modes supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] gsmodes A pointer to where to store the location of + * the list of modes. + * @param[out] gsacount A pointer to where to store the number of + * algorithms in the list at @a modes. + */ +#define fsl_shw_pco_get_sym_modes(pcobject, gsmodes, gsacount) \ +do { \ + *(gsmodes) = (pcobject)->sym_modes; \ + *(gsacount) = (pcobject)->sym_mode_count; \ +} while (0) + + +/** + * Get list of hash algorithms supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] gsalgorithms A pointer which will be set to the list of + * algorithms. + * @param[out] gsacount The number of algorithms in the list at @a + * algorithms. + */ +#define fsl_shw_pco_get_hash_algorithms(pcobject, gsalgorithms, gsacount) \ +do { \ + *(gsalgorithms) = (pcobject)->hash_algorithms; \ + *(gsacount) = (pcobject)->hash_algorithm_count; \ +} while (0) + + +/** + * Determine whether the combination of a given symmetric algorithm and a given + * mode is supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param pcalg A Symmetric Cipher algorithm. + * @param pcmode A Symmetric Cipher mode. + * + * @return 0 if combination is not supported, non-zero if supported. + */ +#if defined(FSL_HAVE_DRYICE) && defined(__KERNEL__) +#define fsl_shw_pco_check_sym_supported(pcobject, pcalg, pcmode) \ + ((pcobject)->sym_support[pcalg][pcmode]) +#else +#define fsl_shw_pco_check_sym_supported(pcobject, pcalg, pcmode) \ + 0 +#endif + +/** + * Determine whether a given Encryption-Authentication mode is supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param pcmode The Authentication mode. + * + * @return 0 if mode is not supported, non-zero if supported. + */ +#define fsl_shw_pco_check_auth_supported(pcobject, pcmode) \ + 0 + + +/** + * Determine whether Black Keys (key establishment / wrapping) is supported. + * + * @param pcobject The Platform Capababilities Object to query. + * + * @return 0 if wrapping is not supported, non-zero if supported. + */ +#if defined(FSL_HAVE_DRYICE) && defined(__KERNEL__) +#define fsl_shw_pco_check_black_key_supported(pcobject) \ + 1 +#else +#define fsl_shw_pco_check_black_key_supported(pcobject) \ + 0 + +#endif + +/*! + * Determine whether Programmed Key features are available + * + * @param pcobject The Platform Capabilities Object to query. + * + * @return 1 if Programmed Key features are available, otherwise zero. + */ +#if defined(FSL_HAVE_DRYICE) && defined(__KERNEL__) +#define fsl_shw_pco_check_pk_supported(pcobject) \ + 1 +#else +#define fsl_shw_pco_check_pk_supported(pcobject) \ + 0 +#endif + +/*! + * Determine whether Software Key features are available + * + * @param pc_info The Platform Capabilities Object to query. + * + * @return 1 if Software key features are available, otherwise zero. + */ +#if defined(FSL_HAVE_DRYICE) && defined(__KERNEL__) +#define fsl_shw_pco_check_sw_keys_supported(pcobject) \ + 1 +#else +#define fsl_shw_pco_check_sw_keys_supported(pcobject) \ + 0 +#endif + +/*! + * Get FSL SHW SCC driver version + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] pcmajor A pointer to where the major version + * of the SCC driver is to be stored. + * @param[out] pcminor A pointer to where the minor version + * of the SCC driver is to be stored. + */ +#define fsl_shw_pco_get_scc_driver_version(pcobject, pcmajor, pcminor) \ +{ \ + *(pcmajor) = (pcobject)->scc_driver_major; \ + *(pcminor) = (pcobject)->scc_driver_minor; \ +} + + +/** + * Get SCM hardware version + * + * @param pcobject The Platform Capababilities Object to query. + * @return The SCM hardware version + */ +#define fsl_shw_pco_get_scm_version(pcobject) \ + ((pcobject)->scm_version) + + +/** + * Get SMN hardware version + * + * @param pcobject The Platform Capababilities Object to query. + * @return The SMN hardware version + */ +#define fsl_shw_pco_get_smn_version(pcobject) \ + ((pcobject)->smn_version) + + +/** + * Get the size of an SCM block, in bytes + * + * @param pcobject The Platform Capababilities Object to query. + * @return The size of an SCM block, in bytes. + */ +#define fsl_shw_pco_get_scm_block_size(pcobject) \ + ((pcobject)->block_size_bytes) + + +/** + * Get size of Black and Red RAM memory + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] black_size A pointer to where the size of the Black RAM, in + * blocks, is to be placed. + * @param[out] red_size A pointer to where the size of the Red RAM, in + * blocks, is to be placed. + */ +#define fsl_shw_pco_get_smn_size(pcobject, black_size, red_size) \ +{ \ + if ((pcobject)->scm_version == 1) { \ + *(black_size) = (pcobject)->u.scc_info.black_ram_size_blocks; \ + *(red_size) = (pcobject)->u.scc_info.red_ram_size_blocks; \ + } else { \ + *(black_size) = 0; \ + *(red_size) = 0; \ + } \ +} + + +/** + * Determine whether Secure Partitions are supported + * + * @param pcobject The Platform Capababilities Object to query. + * + * @return 0 if secure partitions are not supported, non-zero if supported. + */ +#define fsl_shw_pco_check_spo_supported(pcobject) \ + ((pcobject)->scm_version == 2) + + +/** + * Get the size of a Secure Partitions + * + * @param pcobject The Platform Capababilities Object to query. + * + * @return Partition size, in bytes. 0 if Secure Partitions not supported. + */ +#define fsl_shw_pco_get_spo_size_bytes(pcobject) \ + (((pcobject)->scm_version == 2) ? \ + ((pcobject)->u.scc2_info.partition_size_bytes) : 0 ) \ + + +/** + * Get the number of Secure Partitions on this platform + * + * @param pcobject The Platform Capababilities Object to query. + * + * @return Number of partitions. 0 if Secure Paritions not supported. Note + * that this returns the total number of partitions, not all may be + * available to the user. + */ +#define fsl_shw_pco_get_spo_count(pcobject) \ + (((pcobject)->scm_version == 2) ? \ + ((pcobject)->u.scc2_info.partition_count) : 0 ) \ + + +/*! + * Initialize a Secret Key Object. + * + * This function must be called before performing any other operation with + * the Object. + * + * @param skobject The Secret Key Object to be initialized. + * @param skalgorithm DES, AES, etc. + * + */ +#define fsl_shw_sko_init(skobject,skalgorithm) \ +{ \ + fsl_shw_sko_t* skop = skobject; \ + \ + skop->algorithm = skalgorithm; \ + skop->flags = 0; \ + skop->keystore = NULL; \ + skop->pf_key = FSL_SHW_PF_KEY_PRG; \ +} + +/*! + * Initialize a Secret Key Object to use a Platform Key register. + * + * This function must be called before performing any other operation with + * the Object. + * + * @param skobject The Secret Key Object to be initialized. + * @param skalgorithm DES, AES, etc. + * @param skhwkey one of the fsl_shw_pf_key_t values. + * + */ +#define fsl_shw_sko_init_pf_key(skobject,skalgorithm,skhwkey) \ +{ \ + fsl_shw_sko_t* skop = skobject; \ + fsl_shw_key_alg_t alg = skalgorithm; \ + fsl_shw_pf_key_t key = skhwkey; \ + \ + skop->algorithm = alg; \ + if (alg == FSL_KEY_ALG_TDES) { \ + skop->key_length = 21; \ + } \ + skop->keystore = NULL; \ + skop->flags = FSL_SKO_KEY_SELECT_PF_KEY; \ + skop->pf_key = key; \ + if ((key == FSL_SHW_PF_KEY_IIM) || (key == FSL_SHW_PF_KEY_PRG) \ + || (key == FSL_SHW_PF_KEY_IIM_PRG) \ + || (key == FSL_SHW_PF_KEY_IIM_RND) \ + || (key == FSL_SHW_PF_KEY_RND)) { \ + skop->flags |= FSL_SKO_KEY_ESTABLISHED; \ + } \ +} + +/*! + * Store a cleartext key in the key object. + * + * This has the side effect of setting the #FSL_SKO_KEY_PRESENT flag and + * resetting the #FSL_SKO_KEY_ESTABLISHED flag. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skkey A pointer to the beginning of the key. + * @param skkeylen The length, in octets, of the key. The value should be + * appropriate to the key size supported by the algorithm. + * 64 octets is the absolute maximum value allowed for this + * call. + */ +#define fsl_shw_sko_set_key(skobject, skkey, skkeylen) \ +{ \ + (skobject)->key_length = skkeylen; \ + copy_bytes((skobject)->key, skkey, skkeylen); \ + (skobject)->flags |= FSL_SKO_KEY_PRESENT; \ + (skobject)->flags &= ~FSL_SKO_KEY_ESTABLISHED; \ +} + +/** + * Set a size for the key. + * + * This function would normally be used when the user wants the key to be + * generated from a random source. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skkeylen The length, in octets, of the key. The value should be + * appropriate to the key size supported by the algorithm. + * 64 octets is the absolute maximum value allowed for this + * call. + */ +#define fsl_shw_sko_set_key_length(skobject, skkeylen) \ + (skobject)->key_length = skkeylen; + + +/** + * Set the User ID associated with the key. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skuserid The User ID to identify authorized users of the key. + */ +#define fsl_shw_sko_set_user_id(skobject, skuserid) \ + (skobject)->userid = (skuserid) + +/** + * Establish a user Keystore to hold the key. + */ +#define fsl_shw_sko_set_keystore(skobject, user_keystore) \ + (skobject)->keystore = (user_keystore) + + + +/** + * Set the establish key handle into a key object. + * + * The @a userid field will be used to validate the access to the unwrapped + * key. This feature is not available for all platforms, nor for all + * algorithms and modes. + * + * The #FSL_SKO_KEY_ESTABLISHED will be set (and the #FSL_SKO_KEY_PRESENT flag + * will be cleared). + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skuserid The User ID to verify this user is an authorized user of + * the key. + * @param skhandle A @a handle from #fsl_shw_sko_get_established_info. + */ +#define fsl_shw_sko_set_established_info(skobject, skuserid, skhandle) \ +{ \ + (skobject)->userid = (skuserid); \ + (skobject)->handle = (skhandle); \ + (skobject)->flags |= FSL_SKO_KEY_ESTABLISHED; \ + (skobject)->flags &= \ + ~(FSL_SKO_KEY_PRESENT); \ +} + + +/** + * Retrieve the established-key handle from a key object. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skhandle The location to store the @a handle of the unwrapped + * key. + */ +#define fsl_shw_sko_get_established_info(skobject, skhandle) \ + *(skhandle) = (skobject)->handle + + +/** + * Extract the algorithm from a key object. + * + * @param skobject The Key Object to be queried. + * @param[out] skalgorithm A pointer to the location to store the algorithm. + */ +#define fsl_shw_sko_get_algorithm(skobject, skalgorithm) \ + *(skalgorithm) = (skobject)->algorithm + + +/** + * Retrieve the cleartext key from a key object that is stored in a user + * keystore. + * + * @param skobject The Key Object to be queried. + * @param[out] skkey A pointer to the location to store the key. NULL + * if the key is not stored in a user keystore. + */ +#define fsl_shw_sko_get_key(skobject, skkey) \ +{ \ + fsl_shw_kso_t* keystore = (skobject)->keystore; \ + if (keystore != NULL) { \ + *(skkey) = keystore->slot_get_address(keystore->user_data, \ + (skobject)->handle); \ + } else { \ + *(skkey) = NULL; \ + } \ +} + + +/*! + * Determine the size of a wrapped key based upon the cleartext key's length. + * + * This function can be used to calculate the number of octets that + * #fsl_shw_extract_key() will write into the location at @a covered_key. + * + * If zero is returned at @a length, this means that the key length in + * @a key_info is not supported. + * + * @param wkeyinfo Information about a key to be wrapped. + * @param wkeylen Location to store the length of a wrapped + * version of the key in @a key_info. + */ +#define fsl_shw_sko_calculate_wrapped_size(wkeyinfo, wkeylen) \ +{ \ + register fsl_shw_sko_t* kp = wkeyinfo; \ + register uint32_t kl = kp->key_length; \ + int key_blocks; \ + int base_size = 35; /* ICV + T' + ALG + LEN + FLAGS */ \ + \ + if (kp->flags & FSL_SKO_KEY_SELECT_PF_KEY) { \ + kl = 21; /* 168-bit 3DES key */ \ + } \ + key_blocks = (kl + 7) / 8; \ + /* Round length up to 3DES block size for CBC mode */ \ + *(wkeylen) = base_size + 8 * key_blocks; \ +} + +/*! + * Set some flags in the key object. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skflags (One or more) ORed members of #fsl_shw_key_flags_t which + * are to be set. + */ +#define fsl_shw_sko_set_flags(skobject, skflags) \ + (skobject)->flags |= (skflags) + + +/** + * Clear some flags in the key object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skflags (One or more) ORed members of #fsl_shw_key_flags_t + * which are to be reset. + */ +#define fsl_shw_sko_clear_flags(skobject, skflags) \ + (skobject)->flags &= ~(skflags) + +/** + * Initialize a User Context Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the User Context Object to initial values, and set the size + * of the results pool. The mode will be set to a default of + * #FSL_UCO_BLOCKING_MODE. + * + * When using non-blocking operations, this sets the maximum number of + * operations which can be outstanding. This number includes the counts of + * operations waiting to start, operation(s) being performed, and results which + * have not been retrieved. + * + * Changes to this value are ignored once user registration has completed. It + * should be set to 1 if only blocking operations will ever be performed. + * + * @param ucontext The User Context object to operate on. + * @param usize The maximum number of operations which can be + * outstanding. + */ +#ifdef __KERNEL__ + +#define fsl_shw_uco_init(ucontext, usize) \ +do { \ + fsl_shw_uco_t* uco = ucontext; \ + \ + (uco)->pool_size = usize; \ + (uco)->flags = FSL_UCO_BLOCKING_MODE | FSL_UCO_CONTEXT_CHANGED; \ + (uco)->openfd = -1; \ + (uco)->callback = NULL; \ + (uco)->partition = NULL; \ + (uco)->wrap_key = FSL_SHW_PF_KEY_IIM; \ +} while (0) + +#else /* __KERNEL__ */ + +#define fsl_shw_uco_init(ucontext, usize) \ +do { \ + fsl_shw_uco_t* uco = ucontext; \ + \ + (uco)->pool_size = usize; \ + (uco)->flags = FSL_UCO_BLOCKING_MODE | FSL_UCO_CONTEXT_CHANGED; \ + (uco)->openfd = -1; \ + (uco)->callback = NULL; \ + (uco)->wrap_key = FSL_SHW_PF_KEY_IIM; \ +} while (0) + +#endif /* __KERNEL__ */ + + +/** + * Set the User Reference for the User Context. + * + * @param ucontext The User Context object to operate on. + * @param uref A value which will be passed back with a result. + */ +#define fsl_shw_uco_set_reference(ucontext, uref) \ +do { \ + fsl_shw_uco_t* uco = ucontext; \ + \ + (uco)->user_ref = uref; \ + (uco)->flags |= FSL_UCO_CONTEXT_CHANGED; \ +} while (0) + + +/** + * Set the User Reference for the User Context. + * + * @param ucontext The User Context object to operate on. + * @param ucallback The function the API will invoke when an operation + * completes. + */ +#define fsl_shw_uco_set_callback(ucontext, ucallback) \ +do { \ + fsl_shw_uco_t* uco = ucontext; \ + \ + (uco)->callback = ucallback; \ + (uco)->flags |= FSL_UCO_CONTEXT_CHANGED; \ +} while (0) + +/** + * Set flags in the User Context. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param ucontext The User Context object to operate on. + * @param uflags ORed values from #fsl_shw_user_ctx_flags_t. + */ +#define fsl_shw_uco_set_flags(ucontext, uflags) \ + (ucontext)->flags |= (uflags) | FSL_UCO_CONTEXT_CHANGED + + +/** + * Clear flags in the User Context. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param ucontext The User Context object to operate on. + * @param uflags ORed values from #fsl_shw_user_ctx_flags_t. + */ +#define fsl_shw_uco_clear_flags(ucontext, uflags) \ +do { \ + fsl_shw_uco_t* uco = ucontext; \ + \ + (uco)->flags &= ~(uflags); \ + (uco)->flags |= FSL_UCO_CONTEXT_CHANGED; \ +} while (0) + + +/** + * Retrieve the reference value from a Result Object. + * + * @param robject The result object to query. + * + * @return The reference associated with the request. + */ +#define fsl_shw_ro_get_reference(robject) \ + (robject)->user_ref + + +/** + * Retrieve the status code from a Result Object. + * + * @param robject The result object to query. + * + * @return The status of the request. + */ +#define fsl_shw_ro_get_status(robject) \ + (robject)->code + + + +/* REQ-FSL-SHW-PINTFC-API-BASIC-HASH-004 */ +/** + * Initialize a Hash Context Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the current message length and hash algorithm in the hash + * context object. + * + * @param hcobject The hash context to operate upon. + * @param hcalgorithm The hash algorithm to be used (#FSL_HASH_ALG_MD5, + * #FSL_HASH_ALG_SHA256, etc). + * + */ +#define fsl_shw_hco_init(hcobject, hcalgorithm) \ +do { \ + (hcobject)->algorithm = hcalgorithm; \ + (hcobject)->flags = 0; \ + switch (hcalgorithm) { \ + case FSL_HASH_ALG_MD5: \ + (hcobject)->digest_length = 16; \ + (hcobject)->context_length = 16; \ + (hcobject)->context_register_length = 24; \ + break; \ + case FSL_HASH_ALG_SHA1: \ + (hcobject)->digest_length = 20; \ + (hcobject)->context_length = 20; \ + (hcobject)->context_register_length = 24; \ + break; \ + case FSL_HASH_ALG_SHA224: \ + (hcobject)->digest_length = 28; \ + (hcobject)->context_length = 32; \ + (hcobject)->context_register_length = 36; \ + break; \ + case FSL_HASH_ALG_SHA256: \ + (hcobject)->digest_length = 32; \ + (hcobject)->context_length = 32; \ + (hcobject)->context_register_length = 36; \ + break; \ + default: \ + /* error ! */ \ + (hcobject)->digest_length = 1; \ + (hcobject)->context_length = 1; \ + (hcobject)->context_register_length = 1; \ + break; \ + } \ +} while (0) + + +/* REQ-FSL-SHW-PINTFC-API-BASIC-HASH-001 */ +/** + * Get the current hash value and message length from the hash context object. + * + * The algorithm must have already been specified. See #fsl_shw_hco_init(). + * + * @param hcobject The hash context to query. + * @param[out] hccontext Pointer to the location of @a length octets where to + * store a copy of the current value of the digest. + * @param hcclength Number of octets of hash value to copy. + * @param[out] hcmsglen Pointer to the location to store the number of octets + * already hashed. + */ +#define fsl_shw_hco_get_digest(hcobject, hccontext, hcclength, hcmsglen) \ +do { \ + memcpy(hccontext, (hcobject)->context, hcclength); \ + if ((hcobject)->algorithm == FSL_HASH_ALG_SHA224 \ + || (hcobject)->algorithm == FSL_HASH_ALG_SHA256) { \ + *(hcmsglen) = (hcobject)->context[8]; \ + } else { \ + *(hcmsglen) = (hcobject)->context[5]; \ + } \ +} while (0) + + +/* REQ-FSL-SHW-PINTFC-API-BASIC-HASH-002 */ +/** + * Get the hash algorithm from the hash context object. + * + * @param hcobject The hash context to query. + * @param[out] hcalgorithm Pointer to where the algorithm is to be stored. + */ +#define fsl_shw_hco_get_info(hcobject, hcalgorithm) \ +do { \ + *(hcalgorithm) = (hcobject)->algorithm; \ +} while (0) + + +/* REQ-FSL-SHW-PINTFC-API-BASIC-HASH-003 */ +/* REQ-FSL-SHW-PINTFC-API-BASIC-HASH-004 */ +/** + * Set the current hash value and message length in the hash context object. + * + * The algorithm must have already been specified. See #fsl_shw_hco_init(). + * + * @param hcobject The hash context to operate upon. + * @param hccontext Pointer to buffer of appropriate length to copy into + * the hash context object. + * @param hcmsglen The number of octets of the message which have + * already been hashed. + * + */ +#define fsl_shw_hco_set_digest(hcobject, hccontext, hcmsglen) \ +do { \ + memcpy((hcobject)->context, hccontext, (hcobject)->context_length); \ + if (((hcobject)->algorithm == FSL_HASH_ALG_SHA224) \ + || ((hcobject)->algorithm == FSL_HASH_ALG_SHA256)) { \ + (hcobject)->context[8] = hcmsglen; \ + } else { \ + (hcobject)->context[5] = hcmsglen; \ + } \ +} while (0) + + +/** + * Set flags in a Hash Context Object. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param hcobject The hash context to be operated on. + * @param hcflags The flags to be set in the context. These can be ORed + * members of #fsl_shw_hash_ctx_flags_t. + */ +#define fsl_shw_hco_set_flags(hcobject, hcflags) \ + (hcobject)->flags |= (hcflags) + + +/** + * Clear flags in a Hash Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param hcobject The hash context to be operated on. + * @param hcflags The flags to be reset in the context. These can be ORed + * members of #fsl_shw_hash_ctx_flags_t. + */ +#define fsl_shw_hco_clear_flags(hcobject, hcflags) \ + (hcobject)->flags &= ~(hcflags) + + +/** + * Initialize an HMAC Context Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the current message length and hash algorithm in the HMAC + * context object. + * + * @param hcobject The HMAC context to operate upon. + * @param hcalgorithm The hash algorithm to be used (#FSL_HASH_ALG_MD5, + * #FSL_HASH_ALG_SHA256, etc). + * + */ +#define fsl_shw_hmco_init(hcobject, hcalgorithm) \ + fsl_shw_hco_init(hcobject, hcalgorithm) + + +/** + * Set flags in an HMAC Context Object. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param hcobject The HMAC context to be operated on. + * @param hcflags The flags to be set in the context. These can be ORed + * members of #fsl_shw_hmac_ctx_flags_t. + */ +#define fsl_shw_hmco_set_flags(hcobject, hcflags) \ + (hcobject)->flags |= (hcflags) + + +/** + * Clear flags in an HMAC Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param hcobject The HMAC context to be operated on. + * @param hcflags The flags to be reset in the context. These can be ORed + * members of #fsl_shw_hmac_ctx_flags_t. + */ +#define fsl_shw_hmco_clear_flags(hcobject, hcflags) \ + (hcobject)->flags &= ~(hcflags) + + +/** + * Initialize a Symmetric Cipher Context Object. + * + * This function must be called before performing any other operation with the + * Object. This will set the @a mode and @a algorithm and initialize the + * Object. + * + * @param scobject The context object to operate on. + * @param scalg The cipher algorithm this context will be used with. + * @param scmode #FSL_SYM_MODE_CBC, #FSL_SYM_MODE_ECB, etc. + * + */ +#define fsl_shw_scco_init(scobject, scalg, scmode) \ +do { \ + register uint32_t bsb; /* block-size bytes */ \ + \ + switch (scalg) { \ + case FSL_KEY_ALG_AES: \ + bsb = 16; \ + break; \ + case FSL_KEY_ALG_DES: \ + /* fall through */ \ + case FSL_KEY_ALG_TDES: \ + bsb = 8; \ + break; \ + case FSL_KEY_ALG_ARC4: \ + bsb = 259; \ + break; \ + case FSL_KEY_ALG_HMAC: \ + bsb = 1; /* meaningless */ \ + break; \ + default: \ + bsb = 00; \ + } \ + (scobject)->block_size_bytes = bsb; \ + (scobject)->mode = scmode; \ + (scobject)->flags = 0; \ +} while (0) + + +/** + * Set the flags for a Symmetric Cipher Context. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param scobject The context object to operate on. + * @param scflags The flags to reset (one or more values from + * #fsl_shw_sym_ctx_flags_t ORed together). + * + */ +#define fsl_shw_scco_set_flags(scobject, scflags) \ + (scobject)->flags |= (scflags) + + +/** + * Clear some flags in a Symmetric Cipher Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param scobject The context object to operate on. + * @param scflags The flags to reset (one or more values from + * #fsl_shw_sym_ctx_flags_t ORed together). + * + */ +#define fsl_shw_scco_clear_flags(scobject, scflags) \ + (scobject)->flags &= ~(scflags) + + +/** + * Set the Context (IV) for a Symmetric Cipher Context. + * + * This is to set the context/IV for #FSL_SYM_MODE_CBC mode, or to set the + * context (the S-Box and pointers) for ARC4. The full context size will + * be copied. + * + * @param scobject The context object to operate on. + * @param sccontext A pointer to the buffer which contains the context. + * + */ +#define fsl_shw_scco_set_context(scobject, sccontext) \ + memcpy((scobject)->context, sccontext, \ + (scobject)->block_size_bytes) + + +/** + * Get the Context for a Symmetric Cipher Context. + * + * This is to retrieve the context/IV for #FSL_SYM_MODE_CBC mode, or to + * retrieve context (the S-Box and pointers) for ARC4. The full context + * will be copied. + * + * @param scobject The context object to operate on. + * @param[out] sccontext Pointer to location where context will be stored. + */ +#define fsl_shw_scco_get_context(scobject, sccontext) \ + memcpy(sccontext, (scobject)->context, (scobject)->block_size_bytes) + + +/** + * Set the Counter Value for a Symmetric Cipher Context. + * + * This will set the Counter Value for CTR mode. + * + * @param scobject The context object to operate on. + * @param sccounter The starting counter value. The number of octets. + * copied will be the block size for the algorithm. + * @param scmodulus The modulus for controlling the incrementing of the + * counter. + * + */ +#define fsl_shw_scco_set_counter_info(scobject, sccounter, scmodulus) \ +do { \ + if ((sccounter) != NULL) { \ + memcpy((scobject)->context, sccounter, \ + (scobject)->block_size_bytes); \ + } \ + (scobject)->modulus_exp = scmodulus; \ +} while (0) + + +/** + * Get the Counter Value for a Symmetric Cipher Context. + * + * This will retrieve the Counter Value is for CTR mode. + * + * @param scobject The context object to query. + * @param[out] sccounter Pointer to location to store the current counter + * value. The number of octets copied will be the + * block size for the algorithm. + * @param[out] scmodulus Pointer to location to store the modulus. + * + */ +#define fsl_shw_scco_get_counter_info(scobject, sccounter, scmodulus) \ +do { \ + if ((sccounter) != NULL) { \ + memcpy(sccounter, (scobject)->context, \ + (scobject)->block_size_bytes); \ + } \ + if ((scmodulus) != NULL) { \ + *(scmodulus) = (scobject)->modulus_exp; \ + } \ +} while (0) + + +/** + * Initialize a Authentication-Cipher Context. + * + * @param acobject Pointer to object to operate on. + * @param acmode The mode for this object (only #FSL_ACC_MODE_CCM + * supported). + */ +#define fsl_shw_acco_init(acobject, acmode) \ +do { \ + (acobject)->flags = 0; \ + (acobject)->mode = (acmode); \ +} while (0) + + +/** + * Set the flags for a Authentication-Cipher Context. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param acobject Pointer to object to operate on. + * @param acflags The flags to set (one or more from + * #fsl_shw_auth_ctx_flags_t ORed together). + * + */ +#define fsl_shw_acco_set_flags(acobject, acflags) \ + (acobject)->flags |= (acflags) + + +/** + * Clear some flags in a Authentication-Cipher Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param acobject Pointer to object to operate on. + * @param acflags The flags to reset (one or more from + * #fsl_shw_auth_ctx_flags_t ORed together). + * + */ +#define fsl_shw_acco_clear_flags(acobject, acflags) \ + (acobject)->flags &= ~(acflags) + + +/** + * Set up the Authentication-Cipher Object for CCM mode. + * + * This will set the @a auth_object for CCM mode and save the @a ctr, + * and @a mac_length. This function can be called instead of + * #fsl_shw_acco_init(). + * + * The paramater @a ctr is Counter Block 0, (counter value 0), which is for the + * MAC. + * + * @param acobject Pointer to object to operate on. + * @param acalg Cipher algorithm. Only AES is supported. + * @param accounter The initial counter value. + * @param acmaclen The number of octets used for the MAC. Valid values are + * 4, 6, 8, 10, 12, 14, and 16. + */ +/* Do we need to stash the +1 value of the CTR somewhere? */ +#define fsl_shw_acco_set_ccm(acobject, acalg, accounter, acmaclen) \ + do { \ + (acobject)->flags = 0; \ + (acobject)->mode = FSL_ACC_MODE_CCM; \ + (acobject)->auth_info.CCM_ctx_info.block_size_bytes = 16; \ + (acobject)->cipher_ctx_info.block_size_bytes = 16; \ + (acobject)->mac_length = acmaclen; \ + fsl_shw_scco_set_counter_info(&(acobject)->cipher_ctx_info, accounter, \ + FSL_CTR_MOD_128); \ +} while (0) + + +/** + * Format the First Block (IV) & Initial Counter Value per NIST CCM. + * + * This function will also set the IV and CTR values per Appendix A of NIST + * Special Publication 800-38C (May 2004). It will also perform the + * #fsl_shw_acco_set_ccm() operation with information derived from this set of + * parameters. + * + * Note this function assumes the algorithm is AES. It initializes the + * @a auth_object by setting the mode to #FSL_ACC_MODE_CCM and setting the + * flags to be #FSL_ACCO_NIST_CCM. + * + * @param acobject Pointer to object to operate on. + * @param act The number of octets used for the MAC. Valid values are + * 4, 6, 8, 10, 12, 14, and 16. + * @param acad Number of octets of Associated Data (may be zero). + * @param acq A value for the size of the length of @a q field. Valid + * values are 1-8. + * @param acN The Nonce (packet number or other changing value). Must + * be (15 - @a q_length) octets long. + * @param acQ The value of Q (size of the payload in octets). + * + */ +#define fsl_shw_ccm_nist_format_ctr_and_iv(acobject, act, acad, acq, acN, acQ)\ + do { \ + uint64_t Q = acQ; \ + uint8_t bflag = ((acad)?0x40:0) | ((((act)-2)/2)<<3) | ((acq)-1); \ + unsigned i; \ + uint8_t* qptr = (acobject)->auth_info.CCM_ctx_info.context + 15; \ + (acobject)->auth_info.CCM_ctx_info.block_size_bytes = 16; \ + (acobject)->cipher_ctx_info.block_size_bytes = 16; \ + (acobject)->mode = FSL_ACC_MODE_CCM; \ + (acobject)->flags = FSL_ACCO_NIST_CCM; \ + \ + /* Store away the MAC length (after calculating actual value */ \ + (acobject)->mac_length = (act); \ + /* Set Flag field in Block 0 */ \ + *((acobject)->auth_info.CCM_ctx_info.context) = bflag; \ + /* Set Nonce field in Block 0 */ \ + memcpy((acobject)->auth_info.CCM_ctx_info.context+1, acN, \ + 15-(acq)); \ + /* Set Flag field in ctr */ \ + *((acobject)->cipher_ctx_info.context) = (acq)-1; \ + /* Update the Q (payload length) field of Block0 */ \ + (acobject)->q_length = acq; \ + for (i = 0; i < (acq); i++) { \ + *qptr-- = Q & 0xFF; \ + Q >>= 8; \ + } \ + /* Set the Nonce field of the ctr */ \ + memcpy((acobject)->cipher_ctx_info.context+1, acN, 15-(acq)); \ + /* Clear the block counter field of the ctr */ \ + memset((acobject)->cipher_ctx_info.context+16-(acq), 0, (acq)+1); \ + } while (0) + + +/** + * Update the First Block (IV) & Initial Counter Value per NIST CCM. + * + * This function will set the IV and CTR values per Appendix A of NIST Special + * Publication 800-38C (May 2004). + * + * Note this function assumes that #fsl_shw_ccm_nist_format_ctr_and_iv() has + * previously been called on the @a auth_object. + * + * @param acobject Pointer to object to operate on. + * @param acN The Nonce (packet number or other changing value). Must + * be (15 - @a q_length) octets long. + * @param acQ The value of Q (size of the payload in octets). + * + */ +/* Do we need to stash the +1 value of the CTR somewhere? */ +#define fsl_shw_ccm_nist_update_ctr_and_iv(acobject, acN, acQ) \ + do { \ + uint64_t Q = acQ; \ + unsigned i; \ + uint8_t* qptr = (acobject)->auth_info.CCM_ctx_info.context + 15; \ + \ + /* Update the Nonce field field of Block0 */ \ + memcpy((acobject)->auth_info.CCM_ctx_info.context+1, acN, \ + 15 - (acobject)->q_length); \ + /* Update the Q (payload length) field of Block0 */ \ + for (i = 0; i < (acobject)->q_length; i++) { \ + *qptr-- = Q & 0xFF; \ + Q >>= 8; \ + } \ + /* Update the Nonce field of the ctr */ \ + memcpy((acobject)->cipher_ctx_info.context+1, acN, \ + 15 - (acobject)->q_length); \ + } while (0) + + +/****************************************************************************** + * Library functions + *****************************************************************************/ +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSLSHW-PINTFC-API-GEN-003 */ +/** + * Determine the hardware security capabilities of this platform. + * + * Though a user context object is passed into this function, it will always + * act in a non-blocking manner. + * + * @param user_ctx The user context which will be used for the query. + * + * @return A pointer to the capabilities object. + */ +extern fsl_shw_pco_t* fsl_shw_get_capabilities(fsl_shw_uco_t* user_ctx); + + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSLSHW-PINTFC-API-GEN-004 */ +/** + * Create an association between the the user and the provider of the API. + * + * @param user_ctx The user context which will be used for this association. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_register_user(fsl_shw_uco_t* user_ctx); + + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSLSHW-PINTFC-API-GEN-005 */ +/** + * Destroy the association between the the user and the provider of the API. + * + * @param user_ctx The user context which is no longer needed. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_deregister_user(fsl_shw_uco_t* user_ctx); + + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSLSHW-PINTFC-API-GEN-006 */ +/** + * Retrieve results from earlier operations. + * + * @param user_ctx The user's context. + * @param result_size The number of array elements of @a results. + * @param[in,out] results Pointer to first of the (array of) locations to + * store results. + * @param[out] result_count Pointer to store the number of results which + * were returned. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_get_results(fsl_shw_uco_t* user_ctx, + unsigned result_size, + fsl_shw_result_t results[], + unsigned* result_count); + +/** + * Place a key into a protected location for use only by cryptographic + * algorithms. + * + * This only needs to be used to a) unwrap a key, or b) set up a key which + * could be wrapped with a later call to #fsl_shw_extract_key(). Normal + * cleartext keys can simply be placed into #fsl_shw_sko_t key objects with + * #fsl_shw_sko_set_key() and used directly. + * + * The maximum key size supported for wrapped/unwrapped keys is 32 octets. + * (This is the maximum reasonable key length on Sahara - 32 octets for an HMAC + * key based on SHA-256.) The key size is determined by the @a key_info. The + * expected length of @a key can be determined by + * #fsl_shw_sko_calculate_wrapped_size() + * + * The protected key will not be available for use until this operation + * successfully completes. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] key_info The information about the key to be which will + * be established. In the create case, the key + * length must be set. + * @param establish_type How @a key will be interpreted to establish a + * key for use. + * @param key If @a establish_type is #FSL_KEY_WRAP_UNWRAP, + * this is the location of a wrapped key. If + * @a establish_type is #FSL_KEY_WRAP_CREATE, this + * parameter can be @a NULL. If @a establish_type + * is #FSL_KEY_WRAP_ACCEPT, this is the location + * of a plaintext key. + */ +extern fsl_shw_return_t fsl_shw_establish_key( + fsl_shw_uco_t* user_ctx, + fsl_shw_sko_t* key_info, + fsl_shw_key_wrap_t establish_type, + const uint8_t* key); + + +/** + * Wrap a key and retrieve the wrapped value. + * + * A wrapped key is a key that has been cryptographically obscured. It is + * only able to be used with #fsl_shw_establish_key(). + * + * This function will also release the key (see #fsl_shw_release_key()) so + * that it must be re-established before reuse. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The information about the key to be deleted. + * @param[out] covered_key The location to store the wrapped key. + * (This size is based upon the maximum key size + * of 32 octets). + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t* user_ctx, + fsl_shw_sko_t* key_info, + uint8_t* covered_key); + +/*! + * Read the key value from a key object. + * + * Only a key marked as a software key (#FSL_SKO_KEY_SW_KEY) can be read with + * this call. It has no effect on the status of the key store. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The referenced key. + * @param[out] key The location to store the key value. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_read_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + uint8_t * key); + +/** + * De-establish a key so that it can no longer be accessed. + * + * The key will need to be re-established before it can again be used. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The information about the key to be deleted. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_release_key( + fsl_shw_uco_t* user_ctx, + fsl_shw_sko_t* key_info); + + +/* + * In userspace, partition assignments will be tracked using the user context. + * In kernel mode, partition assignments are based on address only. + */ + +/** + * Allocate a block of secure memory + * + * @param user_ctx User context + * @param size Memory size (octets). Note: currently only + * supports only single-partition sized blocks. + * @param UMID User Mode ID to use when registering the + * partition. + * @param permissions Permissions to initialize the partition with. + * Can be made by ORing flags from the + * #fsl_shw_permission_t. + * + * @return Address of the allocated memory. NULL if the + * call was not successful. + */ +extern void *fsl_shw_smalloc(fsl_shw_uco_t* user_ctx, + uint32_t size, + const uint8_t* UMID, + uint32_t permissions); + + +/** + * Free a block of secure memory that was allocated with #fsl_shw_smalloc + * + * @param user_ctx User context + * @param address Address of the block of secure memory to be + * released. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_sfree( + fsl_shw_uco_t* user_ctx, + void* address); + + +/** + * Check the status of a block of a secure memory that was allocated with + * #fsl_shw_smalloc + * + * @param user_ctx User context + * @param address Address of the block of secure memory to be + * released. + * @param status Status of the partition, of type + * #fsl_partition_status_t + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_sstatus(fsl_shw_uco_t* user_ctx, + void* address, + fsl_shw_partition_status_t* status); + + +/** + * Diminish the permissions of a block of secure memory. Note that permissions + * can only be revoked. + * + * @param user_ctx User context + * @param address Base address of the secure memory to work with + * @param permissions Permissions to initialize the partition with. + * Can be made by ORing flags from the + * #fsl_shw_permission_t. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_diminish_perms( + fsl_shw_uco_t* user_ctx, + void* address, + uint32_t permissions); + +extern fsl_shw_return_t do_scc_engage_partition( + fsl_shw_uco_t* user_ctx, + void* address, + const uint8_t* UMID, + uint32_t permissions); + +extern fsl_shw_return_t do_system_keystore_slot_alloc( + fsl_shw_uco_t* user_ctx, + uint32_t key_lenth, + uint64_t ownerid, + uint32_t *slot); + +extern fsl_shw_return_t do_system_keystore_slot_dealloc( + fsl_shw_uco_t* user_ctx, + uint64_t ownerid, + uint32_t slot); + +extern fsl_shw_return_t do_system_keystore_slot_load( + fsl_shw_uco_t* user_ctx, + uint64_t ownerid, + uint32_t slot, + const uint8_t *key, + uint32_t key_length); + +extern fsl_shw_return_t do_system_keystore_slot_encrypt( + fsl_shw_uco_t* user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + uint8_t* black_data); + +extern fsl_shw_return_t do_system_keystore_slot_decrypt( + fsl_shw_uco_t* user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + const uint8_t* black_data); + + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSL-SHW-PINTFC-COA-SKO */ +/* REQ-FSL-SHW-PINTFC-COA-SCCO */ +/* REQ-FSLSHW-PINTFC-API-BASIC-SYM-001 */ +/* PINTFC-API-BASIC-SYM-ARC4-001 */ +/* PINTFC-API-BASIC-SYM-ARC4-002 */ +/** + * Encrypt a stream of data with a symmetric-key algorithm. + * + * In ARC4, and also in #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_CTR modes, the + * flags of the @a sym_ctx object will control part of the operation of this + * function. The #FSL_SYM_CTX_INIT flag means that there is no context info in + * the object. The #FSL_SYM_CTX_LOAD means to use information in the + * @a sym_ctx at the start of the operation, and the #FSL_SYM_CTX_SAVE flag + * means to update the object's context information after the operation has + * been performed. + * + * All of the data for an operation can be run through at once using the + * #FSL_SYM_CTX_INIT or #FSL_SYM_CTX_LOAD flags, as appropriate, and then using + * a @a length for the whole of the data. + * + * If a #FSL_SYM_CTX_SAVE flag were added, an additional call to the function + * would "pick up" where the previous call left off, allowing the user to + * perform the larger function in smaller steps. + * + * In #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_ECB modes, the @a length must always + * be a multiple of the block size for the algorithm being used. For proper + * operation in #FSL_SYM_MODE_CTR mode, the @a length must be a multiple of the + * block size until the last operation on the total octet stream. + * + * Some users of ARC4 may want to compute the context (S-Box and pointers) from + * the key before any data is available. This may be done by running this + * function with a @a length of zero, with the init & save flags flags on in + * the @a sym_ctx. Subsequent operations would then run as normal with the + * load and save flags. Note that they key object is still required. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info Key and algorithm being used for this operation. + * @param[in,out] sym_ctx Info on cipher mode, state of the cipher. + * @param length Length, in octets, of the pt (and ct). + * @param pt pointer to plaintext to be encrypted. + * @param[out] ct pointer to where to store the resulting ciphertext. + * + * @return A return code of type #fsl_shw_return_t. + * + */ +extern fsl_shw_return_t fsl_shw_symmetric_encrypt( + fsl_shw_uco_t* user_ctx, + fsl_shw_sko_t* key_info, + fsl_shw_scco_t* sym_ctx, + uint32_t length, + const uint8_t* pt, + uint8_t* ct); + + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSL-SHW-PINTFC-COA-SKO */ +/* REQ-FSL-SHW-PINTFC-COA-SCCO */ +/* PINTFC-API-BASIC-SYM-002 */ +/* PINTFC-API-BASIC-SYM-ARC4-001 */ +/* PINTFC-API-BASIC-SYM-ARC4-002 */ +/** + * Decrypt a stream of data with a symmetric-key algorithm. + * + * In ARC4, and also in #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_CTR modes, the + * flags of the @a sym_ctx object will control part of the operation of this + * function. The #FSL_SYM_CTX_INIT flag means that there is no context info in + * the object. The #FSL_SYM_CTX_LOAD means to use information in the + * @a sym_ctx at the start of the operation, and the #FSL_SYM_CTX_SAVE flag + * means to update the object's context information after the operation has + * been performed. + * + * All of the data for an operation can be run through at once using the + * #FSL_SYM_CTX_INIT or #FSL_SYM_CTX_LOAD flags, as appropriate, and then using + * a @a length for the whole of the data. + * + * If a #FSL_SYM_CTX_SAVE flag were added, an additional call to the function + * would "pick up" where the previous call left off, allowing the user to + * perform the larger function in smaller steps. + * + * In #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_ECB modes, the @a length must always + * be a multiple of the block size for the algorithm being used. For proper + * operation in #FSL_SYM_MODE_CTR mode, the @a length must be a multiple of the + * block size until the last operation on the total octet stream. + * + * Some users of ARC4 may want to compute the context (S-Box and pointers) from + * the key before any data is available. This may be done by running this + * function with a @a length of zero, with the #FSL_SYM_CTX_INIT & + * #FSL_SYM_CTX_SAVE flags on in the @a sym_ctx. Subsequent operations would + * then run as normal with the load & save flags. Note that they key object is + * still required. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The key and algorithm being used in this operation. + * @param[in,out] sym_ctx Info on cipher mode, state of the cipher. + * @param length Length, in octets, of the ct (and pt). + * @param ct pointer to ciphertext to be decrypted. + * @param[out] pt pointer to where to store the resulting plaintext. + * + * @return A return code of type #fsl_shw_return_t + * + */ +extern fsl_shw_return_t fsl_shw_symmetric_decrypt( + fsl_shw_uco_t* user_ctx, + fsl_shw_sko_t* key_info, + fsl_shw_scco_t* sym_ctx, + uint32_t length, + const uint8_t* ct, + uint8_t* pt); + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSL-SHW-PINTFC-COA-HCO */ +/* REQ-FSLSHW-PINTFC-API-BASIC-HASH-005 */ +/** + * Hash a stream of data with a cryptographic hash algorithm. + * + * The flags in the @a hash_ctx control the operation of this function. + * + * Hashing functions work on 64 octets of message at a time. Therefore, when + * any partial hashing of a long message is performed, the message @a length of + * each segment must be a multiple of 64. When ready to + * #FSL_HASH_FLAGS_FINALIZE the hash, the @a length may be any value. + * + * With the #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_FINALIZE flags on, a + * one-shot complete hash, including padding, will be performed. The @a length + * may be any value. + * + * The first octets of a data stream can be hashed by setting the + * #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_SAVE flags. The @a length must be + * a multiple of 64. + * + * The flag #FSL_HASH_FLAGS_LOAD is used to load a context previously saved by + * #FSL_HASH_FLAGS_SAVE. The two in combination will allow a (multiple-of-64 + * octets) 'middle sequence' of the data stream to be hashed with the + * beginning. The @a length must again be a multiple of 64. + * + * Since the flag #FSL_HASH_FLAGS_LOAD is used to load a context previously + * saved by #FSL_HASH_FLAGS_SAVE, the #FSL_HASH_FLAGS_LOAD and + * #FSL_HASH_FLAGS_FINALIZE flags, used together, can be used to finish the + * stream. The @a length may be any value. + * + * If the user program wants to do the padding for the hash, it can leave off + * the #FSL_HASH_FLAGS_FINALIZE flag. The @a length must then be a multiple of + * 64 octets. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] hash_ctx Hashing algorithm and state of the cipher. + * @param msg Pointer to the data to be hashed. + * @param length Length, in octets, of the @a msg. + * @param[out] result If not null, pointer to where to store the hash + * digest. + * @param result_len Number of octets to store in @a result. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_hash( + fsl_shw_uco_t* user_ctx, + fsl_shw_hco_t* hash_ctx, + const uint8_t* msg, + uint32_t length, + uint8_t* result, + uint32_t result_len); + + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSL-SHW-PINTFC-API-BASIC-HMAC-001 */ +/** + * Precompute the Key hashes for an HMAC operation. + * + * This function may be used to calculate the inner and outer precomputes, + * which are the hash contexts resulting from hashing the XORed key for the + * 'inner hash' and the 'outer hash', respectively, of the HMAC function. + * + * After execution of this function, the @a hmac_ctx will contain the + * precomputed inner and outer contexts, so that they may be used by + * #fsl_shw_hmac(). The flags of @a hmac_ctx will be updated with + * #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT to mark their presence. In addtion, the + * #FSL_HMAC_FLAGS_INIT flag will be set. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The key being used in this operation. Key must be + * 1 to 64 octets long. + * @param[in,out] hmac_ctx The context which controls, by its flags and + * algorithm, the operation of this function. + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_hmac_precompute( + fsl_shw_uco_t* user_ctx, + fsl_shw_sko_t* key_info, + fsl_shw_hmco_t* hmac_ctx); + + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSLSHW-PINTFC-API-BASIC-HMAC-002 */ +/** + * Continue, finalize, or one-shot an HMAC operation. + * + * There are a number of ways to use this function. The flags in the + * @a hmac_ctx object will determine what operations occur. + * + * If #FSL_HMAC_FLAGS_INIT is set, then the hash will be started either from + * the @a key_info, or from the precomputed inner hash value in the + * @a hmac_ctx, depending on the value of #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT. + * + * If, instead, #FSL_HMAC_FLAGS_LOAD is set, then the hash will be continued + * from the ongoing inner hash computation in the @a hmac_ctx. + * + * If #FSL_HMAC_FLAGS_FINALIZE are set, then the @a msg will be padded, hashed, + * the outer hash will be performed, and the @a result will be generated. + * + * If the #FSL_HMAC_FLAGS_SAVE flag is set, then the (ongoing or final) digest + * value will be stored in the ongoing inner hash computation field of the @a + * hmac_ctx. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info If #FSL_HMAC_FLAGS_INIT is set in the @a hmac_ctx, + * this is the key being used in this operation, and the + * IPAD. If #FSL_HMAC_FLAGS_INIT is set in the @a + * hmac_ctx and @a key_info is NULL, then + * #fsl_shw_hmac_precompute() has been used to populate + * the @a inner_precompute and @a outer_precompute + * contexts. If #FSL_HMAC_FLAGS_INIT is not set, this + * parameter is ignored. + + * @param[in,out] hmac_ctx The context which controls, by its flags and + * algorithm, the operation of this function. + * @param msg Pointer to the message to be hashed. + * @param length Length, in octets, of the @a msg. + * @param[out] result Pointer, of @a result_len octets, to where to + * store the HMAC. + * @param result_len Length of @a result buffer. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_hmac( + fsl_shw_uco_t* user_ctx, + fsl_shw_sko_t* key_info, + fsl_shw_hmco_t* hmac_ctx, + const uint8_t* msg, + uint32_t length, + uint8_t* result, + uint32_t result_len); + + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSLSHW-PINTFC-API-BASIC-RNG-002 */ +/** + * Get random data. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param length The number of octets of @a data being requested. + * @param[out] data A pointer to a location of @a length octets to where + * random data will be returned. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_get_random( + fsl_shw_uco_t* user_ctx, + uint32_t length, + uint8_t* data); + + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSLSHW-PINTFC-API-BASIC-RNG-003 */ +/** + * Add entropy to random number generator. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param length Number of bytes at @a data. + * @param data Entropy to add to random number generator. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_add_entropy( + fsl_shw_uco_t* user_ctx, + uint32_t length, + uint8_t* data); + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSL-SHW-PINTFC-COA-SKO */ +/** + * Perform Generation-Encryption by doing a Cipher and a Hash. + * + * Generate the authentication value @a auth_value as well as encrypt the @a + * payload into @a ct (the ciphertext). This is a one-shot function, so all of + * the @a auth_data and the total message @a payload must passed in one call. + * This also means that the flags in the @a auth_ctx must be #FSL_ACCO_CTX_INIT + * and #FSL_ACCO_CTX_FINALIZE. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param auth_ctx Controlling object for Authenticate-decrypt. + * @param cipher_key_info The key being used for the cipher part of this + * operation. In CCM mode, this key is used for + * both parts. + * @param auth_key_info The key being used for the authentication part + * of this operation. In CCM mode, this key is + * ignored and may be NULL. + * @param auth_data_length Length, in octets, of @a auth_data. + * @param auth_data Data to be authenticated but not encrypted. + * @param payload_length Length, in octets, of @a payload. + * @param payload Pointer to the plaintext to be encrypted. + * @param[out] ct Pointer to the where the encrypted @a payload + * will be stored. Must be @a payload_length + * octets long. + * @param[out] auth_value Pointer to where the generated authentication + * field will be stored. Must be as many octets as + * indicated by MAC length in the @a function_ctx. + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_gen_encrypt( + fsl_shw_uco_t* user_ctx, + fsl_shw_acco_t* auth_ctx, + fsl_shw_sko_t* cipher_key_info, + fsl_shw_sko_t* auth_key_info, + uint32_t auth_data_length, + const uint8_t* auth_data, + uint32_t payload_length, + const uint8_t* payload, + uint8_t* ct, + uint8_t* auth_value); + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSL-SHW-PINTFC-COA-SKO */ +/** + * Perform Authentication-Decryption in Cipher + Hash. + * + * This function will perform a one-shot decryption of a data stream as well as + * authenticate the authentication value. This is a one-shot function, so all + * of the @a auth_data and the total message @a payload must passed in one + * call. This also means that the flags in the @a auth_ctx must be + * #FSL_ACCO_CTX_INIT and #FSL_ACCO_CTX_FINALIZE. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param auth_ctx Controlling object for Authenticate-decrypt. + * @param cipher_key_info The key being used for the cipher part of this + * operation. In CCM mode, this key is used for + * both parts. + * @param auth_key_info The key being used for the authentication part + * of this operation. In CCM mode, this key is + * ignored and may be NULL. + * @param auth_data_length Length, in octets, of @a auth_data. + * @param auth_data Data to be authenticated but not decrypted. + * @param payload_length Length, in octets, of @a ct and @a pt. + * @param ct Pointer to the encrypted input stream. + * @param auth_value The (encrypted) authentication value which will + * be authenticated. This is the same data as the + * (output) @a auth_value argument to + * #fsl_shw_gen_encrypt(). + * @param[out] payload Pointer to where the plaintext resulting from + * the decryption will be stored. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_auth_decrypt( + fsl_shw_uco_t* user_ctx, + fsl_shw_acco_t* auth_ctx, + fsl_shw_sko_t* cipher_key_info, + fsl_shw_sko_t* auth_key_info, + uint32_t auth_data_length, + const uint8_t* auth_data, + uint32_t payload_length, + const uint8_t* ct, + const uint8_t* auth_value, + uint8_t* payload); + +/*! + * Cause the hardware to create a new random key for secure memory use. + * + * Have the hardware use the secure hardware random number generator to load a + * new secret key into the hardware random key register. It will not be made + * active without a call to #fsl_shw_select_pf_key(). + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * + * @return A return code of type #fsl_shw_return_t. + */ +#ifdef __KERNEL__ + +extern fsl_shw_return_t fsl_shw_gen_random_pf_key(fsl_shw_uco_t * user_ctx); + +#else + +#define fsl_shw_gen_random_pf_key(user_ctx) FSL_RETURN_NO_RESOURCE_S + +#endif /* __KERNEL__ */ + +/*! + * Retrieve the detected tamper event. + * + * Note that if more than one event was detected, this routine will only ever + * return one of them. + * + * @param[in] user_ctx A user context from #fsl_shw_register_user(). + * @param[out] tamperp Location to store the tamper information. + * @param[out] timestampp Locate to store timestamp from hardwhare when + * an event was detected. + * + * + * @return A return code of type #fsl_shw_return_t (for instance, if the platform + * is not in a fail state. + */ +#ifdef __KERNEL__ + +extern fsl_shw_return_t fsl_shw_read_tamper_event(fsl_shw_uco_t * user_ctx, + fsl_shw_tamper_t * tamperp, + uint64_t * timestampp); +#else + +#define fsl_shw_read_tamper_event(user_ctx,tamperp,timestampp) \ + FSL_RETURN_NO_RESOURCE_S + +#endif /* __KERNEL__ */ + +/***************************************************************************** + * + * Functions internal to SHW driver. + * +*****************************************************************************/ + +fsl_shw_return_t +do_scc_encrypt_region(fsl_shw_uco_t* user_ctx, + void* partition_base, uint32_t offset_bytes, + uint32_t byte_count, uint8_t* black_data, + uint32_t* IV, fsl_shw_cypher_mode_t cypher_mode); + +fsl_shw_return_t +do_scc_decrypt_region(fsl_shw_uco_t* user_ctx, + void* partition_base, uint32_t offset_bytes, + uint32_t byte_count, const uint8_t* black_data, + uint32_t* IV, fsl_shw_cypher_mode_t cypher_mode); + + +/***************************************************************************** + * + * Functions available to other SHW-family drivers. + * +*****************************************************************************/ + +#ifdef __KERNEL__ +/** + * Add an entry to a work/result queue. + * + * @param pool Pointer to list structure + * @param entry Entry to place at tail of list + * + * @return void + */ +inline static void SHW_ADD_QUEUE_ENTRY(shw_queue_t* pool, + shw_queue_entry_t* entry) +{ + os_lock_context_t lock_context; + + entry->next = NULL; + os_lock_save_context(shw_queue_lock, lock_context); + + if (pool->tail != NULL) { + pool->tail->next = entry; + } else { + /* Queue was empty, so this is also the head. */ + pool->head = entry; + } + pool->tail = entry; + + os_unlock_restore_context(shw_queue_lock, lock_context); + + return; + + +} + + +/** + * Get first entry on the queue and remove it from the queue. + * + * @return Pointer to first entry, or NULL if none. + */ +inline static shw_queue_entry_t* SHW_POP_FIRST_ENTRY(shw_queue_t* queue) +{ + shw_queue_entry_t* entry; + os_lock_context_t lock_context; + + os_lock_save_context(shw_queue_lock, lock_context); + + entry = queue->head; + + if (entry != NULL) { + queue->head = entry->next; + entry->next = NULL; + /* If this was only entry, clear the tail. */ + if (queue->tail == entry) { + queue->tail = NULL; + } + } + + os_unlock_restore_context(shw_queue_lock, lock_context); + + return entry; +} + + + +/** + * Remove an entry from the list. + * + * If the entry not on the queue, no error will be returned. + * + * @param pool Pointer to work queue + * @param entry Entry to remove from queue + * + * @return void + * + */ +inline static void SHW_QUEUE_REMOVE_ENTRY(shw_queue_t* pool, + shw_queue_entry_t* entry) +{ + os_lock_context_t lock_context; + + os_lock_save_context(shw_queue_lock, lock_context); + + /* Check for quick case.*/ + if (pool->head == entry) { + pool->head = entry->next; + entry->next = NULL; + if (pool->tail == entry) { + pool->tail = NULL; + } + } else { + register shw_queue_entry_t* prev = pool->head; + + /* We know it is not the head, so start looking at entry after head. */ + while (prev->next) { + if (prev->next != entry) { + prev = prev->next; /* Try another */ + continue; + } else { + /* Unlink from chain. */ + prev->next = entry->next; + entry->next = NULL; + /* If last in chain, update tail. */ + if (pool->tail == entry) { + pool->tail = prev; + } + break; + } + } /* while */ + } + + os_unlock_restore_context(shw_queue_lock, lock_context); + + return; +} +#endif /* __KERNEL__ */ + + +/***************************************************************************** + * + * Functions available to User-Mode API functions + * + ****************************************************************************/ +#ifndef __KERNEL__ + + + /** + * Sanity checks the user context object fields to ensure that they make some + * sense before passing the uco as a parameter. + * + * @brief Verify the user context object + * + * @param uco user context object + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t validate_uco(fsl_shw_uco_t *uco); + + +/** + * Initialize a request block to go to the driver. + * + * @param hdr Pointer to request block header + * @param user_ctx Pointer to user's context + * + * @return void + */ +inline static void init_req(struct shw_req_header* hdr, + fsl_shw_uco_t* user_ctx) +{ + hdr->flags = user_ctx->flags; + hdr->user_ref = user_ctx->user_ref; + hdr->code = FSL_RETURN_ERROR_S; + + return; +} + + +/** + * Send a request block off to the driver. + * + * If this is a non-blocking request, then req will be freed. + * + * @param type The type of request being sent + * @param req Pointer to the request block + * @param ctx Pointer to user's context + * + * @return code from driver if ioctl() succeeded, otherwise + * FSL_RETURN_INTERNAL_ERROR_S. + */ +inline static fsl_shw_return_t send_req(shw_user_request_t type, + struct shw_req_header* req, + fsl_shw_uco_t* ctx) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + unsigned blocking = ctx->flags & FSL_UCO_BLOCKING_MODE; + int code; + + code = ioctl(ctx->openfd, SHW_IOCTL_REQUEST + type, req); + + if (code == 0) { + if (blocking) { + ret = req->code; + } else { + ret = FSL_RETURN_OK_S; + } + } else { +#ifdef FSL_DEBUG + fprintf(stderr, "SHW: send_req failed with (%d), %s\n", errno, + strerror(errno)); +#endif + } + + if (blocking) { + free(req); + } + + return ret; +} + + +#endif /* no __KERNEL__ */ + +#if defined(FSL_HAVE_DRYICE) +/* Some kernel functions */ +void fsl_shw_permute1_bytes(const uint8_t * key, uint8_t * permuted_key, + int key_count); +void fsl_shw_permute1_bytes_to_words(const uint8_t * key, + uint32_t * permuted_key, int key_count); + +#define PFKEY_TO_STR(key_in) \ +({ \ + di_key_t key = key_in; \ + \ + ((key == DI_KEY_FK) ? "IIM" : \ + ((key == DI_KEY_PK) ? "PRG" : \ + ((key == DI_KEY_RK) ? "RND" : \ + ((key == DI_KEY_FPK) ? "IIM_PRG" : \ + ((key == DI_KEY_FRK) ? "IIM_RND" : "unk"))))); \ +}) + +#ifdef DIAG_SECURITY_FUNC +extern const char *di_error_string(int code); +#endif + +#endif /* HAVE DRYICE */ + +#endif /* SHW_DRIVER_H */ diff -urN linux-2.6.26/drivers/mxc/security/rng/include/shw_hash.h linux-2.6.26-lab126/drivers/mxc/security/rng/include/shw_hash.h --- linux-2.6.26/drivers/mxc/security/rng/include/shw_hash.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/include/shw_hash.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,96 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @file shw_hash.h + * + * This file contains definitions for use of the (internal) SHW hash + * software computation. It defines the usual three steps: + * + * - #shw_hash_init() + * - #shw_hash_update() + * - #shw_hash_final() + * + * The only other item of note to callers is #SHW_HASH_LEN, which is the number + * of bytes calculated for the hash. + */ + +#ifndef SHW_HASH_H +#define SHW_HASH_H + +/*! Define which gives the number of bytes available in an hash result */ +#define SHW_HASH_LEN 32 + +/* Define which matches block length in bytes of the underlying hash */ +#define SHW_HASH_BLOCK_LEN 64 + +/* "Internal" define which matches SHA-256 state size (32-bit words) */ +#define SHW_HASH_STATE_WORDS 8 + +/* "Internal" define which matches word length in blocks of the underlying + hash. */ +#define SHW_HASH_BLOCK_WORD_SIZE 16 + +#define SHW_HASH_STATE_SIZE 32 + +/*! + * State for a SHA-1/SHA-2 Hash + * + * (Note to maintainers: state needs to be updated to uint64_t to handle + * SHA-384/SHA-512)... And bit_count to uint128_t (heh). + */ +typedef struct shw_hash_state { + unsigned int partial_count_bytes; /*!< Number of bytes of message sitting + * in @c partial_block */ + uint8_t partial_block[SHW_HASH_BLOCK_LEN]; /*!< Data waiting to be processed as a block */ + uint32_t state[SHW_HASH_STATE_WORDS]; /*!< Current hash state variables */ + uint64_t bit_count; /*!< Number of bits sent through the update function */ +} shw_hash_state_t; + +/*! + * Initialize the hash state structure + * + * @param state Address of hash state structure. + * @param algorithm Which hash algorithm to use (must be FSL_HASH_ALG_SHA256) + * + * @return FSL_RETURN_OK_S if all went well, otherwise an error code. + */ +fsl_shw_return_t shw_hash_init(shw_hash_state_t * state, + fsl_shw_hash_alg_t algorithm); + +/*! + * Put data into the hash calculation + * + * @param state Address of hash state structure. + * @param msg Address of the message data for the hash. + * @param msg_len Number of bytes of @c msg. + * + * @return FSL_RETURN_OK_S if all went well, otherwise an error code. + */ +fsl_shw_return_t shw_hash_update(shw_hash_state_t * state, + const uint8_t * msg, unsigned int msg_len); + +/*! + * Calculate the final hash value + * + * @param state Address of hash state structure. + * @param hash Address of location to store the hash. + * @param hash_len Number of bytes of @c hash to be stored. + * + * @return FSL_RETURN_OK_S if all went well, FSL_RETURN_BAD_DATA_LENGTH_S if + * hash_len is too long, otherwise an error code. + */ +fsl_shw_return_t shw_hash_final(shw_hash_state_t * state, + uint8_t * hash, unsigned int hash_len); + +#endif /* SHW_HASH_H */ diff -urN linux-2.6.26/drivers/mxc/security/rng/include/shw_hmac.h linux-2.6.26-lab126/drivers/mxc/security/rng/include/shw_hmac.h --- linux-2.6.26/drivers/mxc/security/rng/include/shw_hmac.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/include/shw_hmac.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,82 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @file shw_hmac.h + * + * This file contains definitions for use of the (internal) SHW HMAC + * software computation. It defines the usual three steps: + * + * - #shw_hmac_init() + * - #shw_hmac_update() + * - #shw_hmac_final() + * + * The only other item of note to callers is #SHW_HASH_LEN, which is the number + * of bytes calculated for the HMAC. + */ + +#ifndef SHW_HMAC_H +#define SHW_HMAC_H + +#include "shw_hash.h" + +/*! + * State for an HMAC + * + * Note to callers: This structure contains key material and should be kept in + * a secure location, such as internal RAM. + */ +typedef struct shw_hmac_state { + shw_hash_state_t inner_hash; /*!< Current state of inner hash */ + shw_hash_state_t outer_hash; /*!< Current state of outer hash */ +} shw_hmac_state_t; + +/*! + * Initialize the HMAC state structure with the HMAC key + * + * @param state Address of HMAC state structure. + * @param key Address of the key to be used for the HMAC. + * @param key_len Number of bytes of @c key. This must not be greater than + * the block size of the underlying hash (#SHW_HASH_BLOCK_LEN). + * + * @return FSL_RETURN_OK_S if all went well, otherwise an error code. + */ +fsl_shw_return_t shw_hmac_init(shw_hmac_state_t * state, + const uint8_t * key, unsigned int key_len); + +/*! + * Put data into the HMAC calculation + * + * @param state Address of HMAC state structure. + * @param msg Address of the message data for the HMAC. + * @param msg_len Number of bytes of @c msg. + * + * @return FSL_RETURN_OK_S if all went well, otherwise an error code. + */ +fsl_shw_return_t shw_hmac_update(shw_hmac_state_t * state, + const uint8_t * msg, unsigned int msg_len); + +/*! + * Calculate the final HMAC + * + * @param state Address of HMAC state structure. + * @param hmac Address of location to store the HMAC. + * @param hmac_len Number of bytes of @c mac to be stored. Probably best if + * this value is no greater than #SHW_HASH_LEN. + * + * @return FSL_RETURN_OK_S if all went well, otherwise an error code. + */ +fsl_shw_return_t shw_hmac_final(shw_hmac_state_t * state, + uint8_t * hmac, unsigned int hmac_len); + +#endif /* SHW_HMAC_H */ diff -urN linux-2.6.26/drivers/mxc/security/rng/include/shw_internals.h linux-2.6.26-lab126/drivers/mxc/security/rng/include/shw_internals.h --- linux-2.6.26/drivers/mxc/security/rng/include/shw_internals.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/include/shw_internals.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,162 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef SHW_INTERNALS_H +#define SHW_INTERNALS_H + +/*! @file shw_internals.h + * + * This file contains definitions which are internal to the SHW driver. + * + * This header file should only ever be included by shw_driver.c + * + * Compile-time flags minimally needed: + * + * @li Some sort of platform flag. + * + */ + +#include "portable_os.h" +#include "shw_driver.h" + +/*! @defgroup shwcompileflags SHW Compile Flags + * + * These are flags which are used to configure the SHW driver at compilation + * time. + * + * The terms 'defined' and 'undefined' refer to whether a @c \#define (or -D on + * a compile command) has defined a given preprocessor symbol. If a given + * symbol is defined, then @c \#ifdef \ will succeed. Some symbols + * described below default to not having a definition, i.e. they are undefined. + * + */ + +/*! @addtogroup shwcompileflags */ +/*! @{ */ +#ifndef SHW_MAJOR_NODE +/*! + * This should be configured in a Makefile/compile command line. It is the + * value the driver will use to register itself as a device driver for a + * /dev/node file. Zero means allow (Linux) to assign a value. Any positive + * number will be attempted as the registration value, to allow for + * coordination with the creation/existence of a /dev/fsl_shw (for instance) + * file in the filesystem. + */ +#define SHW_MAJOR_NODE 0 +#endif + +/* Temporarily define compile-time flags to make Doxygen happy and allow them + to get into the documentation. */ +#ifdef DOXYGEN_HACK + +/*! + * Turn on compilation of run-time operational, debug, and error messages. + * + * This flag is undefined by default. + */ +/* REQ-FSLSHW-DEBUG-001 */ +#define SHW_DEBUG +#undef SHW_DEBUG + +/*! @} */ +#endif /* end DOXYGEN_HACK */ + +#ifndef SHW_DRIVER_NAME +/*! @addtogroup shwcompileflags */ +/*! @{ */ +/*! Name the driver will use to register itself to the kernel as the driver for + * the #shw_major_node and interrupt handling. */ +#define SHW_DRIVER_NAME "fsl_shw" +/*! @} */ +#endif +/*#define SHW_DEBUG*/ + +/*! + * Add a user context onto the list of registered users. + * + * Place it at the head of the #user_list queue. + * + * @param ctx A pointer to a user context + * + * @return void + */ +inline static void SHW_ADD_USER(fsl_shw_uco_t * ctx) +{ + os_lock_context_t lock_context; + + os_lock_save_context(shw_queue_lock, lock_context); + ctx->next = user_list; + user_list = ctx; + os_unlock_restore_context(shw_queue_lock, lock_context); + +} + +/*! + * Remove a user context from the list of registered users. + * + * @param ctx A pointer to a user context + * + * @return void + * + */ +inline static void SHW_REMOVE_USER(fsl_shw_uco_t * ctx) +{ + fsl_shw_uco_t *prev_ctx = user_list; + os_lock_context_t lock_context; + + os_lock_save_context(shw_queue_lock, lock_context); + + if (prev_ctx == ctx) { + /* Found at head, so just set new head */ + user_list = ctx->next; + } else { + for (; (prev_ctx != NULL); prev_ctx = prev_ctx->next) { + if (prev_ctx->next == ctx) { + prev_ctx->next = ctx->next; + break; + } + } + } + os_unlock_restore_context(shw_queue_lock, lock_context); +} + +static void shw_user_callback(fsl_shw_uco_t * uco); + +/* internal functions */ +static os_error_code shw_setup_user_driver_interaction(void); +static void shw_cleanup(void); + +static os_error_code init_uco(fsl_shw_uco_t * user_ctx, void *user_mode_uco); +static os_error_code get_capabilities(fsl_shw_uco_t * user_ctx, + void *user_mode_pco_request); +static os_error_code get_results(fsl_shw_uco_t * user_ctx, + void *user_mode_result_req); +static os_error_code get_random(fsl_shw_uco_t * user_ctx, + void *user_mode_get_random_req); +static os_error_code add_entropy(fsl_shw_uco_t * user_ctx, + void *user_mode_add_entropy_req); + +void* wire_user_memory(void* address, uint32_t length, void** page_ctx); +void unwire_user_memory(void** page_ctx); +os_error_code map_user_memory(struct vm_area_struct* vma, + uint32_t physical_addr, uint32_t size); +os_error_code unmap_user_memory(uint32_t user_addr, uint32_t size); + +#if defined(LINUX_VERSION_CODE) + +MODULE_AUTHOR("Freescale Semiconductor"); +MODULE_DESCRIPTION("Device Driver for FSL SHW API"); + +#endif /* LINUX_VERSION_CODE */ + +#endif /* SHW_INTERNALS_H */ diff -urN linux-2.6.26/drivers/mxc/security/rng/rng_driver.c linux-2.6.26-lab126/drivers/mxc/security/rng/rng_driver.c --- linux-2.6.26/drivers/mxc/security/rng/rng_driver.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/rng_driver.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,1150 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! @file rng_driver.c + * + * This is the driver code for the hardware Random Number Generator (RNG). + * + * It provides the following functions to callers: + * fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t* user_ctx, + * uint32_t length, + * uint8_t* data); + * + * fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t* user_ctx, + * uint32_t length, + * uint8_t* data); + * + * The life of the driver starts at boot (or module load) time, with a call by + * the kernel to #rng_init(). As part of initialization, a background task + * running #rng_entropy_task() will be created. + * + * The life of the driver ends when the kernel is shutting down (or the driver + * is being unloaded). At this time, #rng_shutdown() is called. No function + * will ever be called after that point. In the case that the driver is + * reloaded, a new copy of the driver, with fresh global values, etc., is + * loaded, and there will be a new call to #rng_init(). + * + * A call to fsl_shw_get_random() gets converted into a work entry which is + * queued and handed off to a background task for fulfilment. This provides + * for a single thread of control for reading the RNG's FIFO register, which + * might otherwise underflow if not carefully managed. + * + * A call to fsl_shw_add_entropy() will cause the additional entropy to + * be passed directly into the hardware. + * + * In a debug configuration, it provides the following kernel functions: + * rng_return_t rng_read_register(uint32_t byte_offset, uint32_t* valuep); + * rng_return_t rng_write_register(uint32_t byte_offset, uint32_t value); + * @ingroup RNG + */ + +#include "portable_os.h" +#include "fsl_shw.h" +#include "rng_internals.h" + +#ifdef FSL_HAVE_SCC2 +#include +#else +#include +#endif + +#if defined(RNG_DEBUG) || defined(RNG_ENTROPY_DEBUG) || \ + defined(RNG_REGISTER_DEBUG) + +#include + +#else + +#define LOG_KDIAG_ARGS(fmt, ...) +#define LOG_KDIAG(diag) + +#endif + +/* These are often handy */ +#ifndef FALSE +/*! Non-true value for arguments, return values. */ +#define FALSE 0 +#endif +#ifndef TRUE +/*! True value for arguments, return values. */ +#define TRUE 1 +#endif + +/****************************************************************************** + * + * Global / Static Variables + * + *****************************************************************************/ + +/*! + * This is type void* so that a) it cannot directly be dereferenced, and b) + * pointer arithmetic on it will function for the byte offsets in rng_rnga.h + * and rng_rngc.h + * + * rng_base is the location in the iomap where the RNG's registers + * (and memory) start. + * + * The referenced data is declared volatile so that the compiler will + * not make any assumptions about the value of registers in the RNG, + * and thus will always reload the register into CPU memory before + * using it (i.e. wherever it is referenced in the driver). + * + * This value should only be referenced by the #RNG_READ_REGISTER and + * #RNG_WRITE_REGISTER macros and their ilk. All dereferences must be + * 32 bits wide. + */ +static volatile void *rng_base; + +/*! + * Flag to say whether interrupt handler has been registered for RNG + * interrupt */ +static int rng_irq_set = FALSE; + +/*! + * Size of the RNG's OUTPUT_FIFO, in words. Retrieved with + * #RNG_GET_FIFO_SIZE() during driver initialization. + */ +static int rng_output_fifo_size; + +/*! Major number for device driver. */ +static int rng_major; + +/*! Registration handle for registering driver with OS. */ +os_driver_reg_t rng_reg_handle; + +/*! + * Internal flag to know whether RNG is in Failed state (and thus many + * registers are unavailable). If the value ever goes to #RNG_STATUS_FAILED, + * it will never change. + */ +static volatile rng_status_t rng_availability = RNG_STATUS_INITIAL; + +/*! + * Global lock for the RNG driver. Mainly used for entries on the RNG work + * queue. + */ +static os_lock_t rng_queue_lock = NULL; + +/*! + * Queue for the RNG task to process. + */ +static shw_queue_t rng_work_queue; + +/*! + * Flag to say whether task initialization succeeded. + */ +static unsigned task_started = FALSE; +/*! + * Waiting queue for RNG SELF TESTING + */ +static DECLARE_COMPLETION(rng_self_testing); +static DECLARE_COMPLETION(rng_seed_done); +/*! + * Object for blocking-mode callers of RNG driver to sleep. + */ +OS_WAIT_OBJECT(rng_wait_queue); + +/****************************************************************************** + * + * Function Implementations - Externally Accessible + * + *****************************************************************************/ + +/*****************************************************************************/ +/* fn rng_init() */ +/*****************************************************************************/ +/*! + * Initialize the driver. + * + * Set up the driver to have access to RNG device registers and verify that + * it appears to be a proper working device. + * + * Set up interrupt handling. Assure RNG is ready to go and (possibly) set it + * into High Assurance mode. Create a background task to run + * #rng_entropy_task(). Set up up a callback with the SCC driver should the + * security alarm go off. Tell the kernel that the driver is here. + * + * This routine is called during kernel init or module load (insmod). + * + * The function will fail in one of two ways: Returning OK to the caller so + * that kernel startup / driver initialization completes, or returning an + * error. In the success case, the function could set the rng_avaailability to + * RNG_STATUS_FAILED so that only minimal support (e.g. register peek / poke) + * is available in the driver. + * + * @return a call to os_dev_init_return() + */ +OS_DEV_INIT(rng_init) +{ + struct clk *clk; + os_error_code return_code = OS_ERROR_FAIL_S; + rng_availability = RNG_STATUS_CHECKING; + +#if !defined(FSL_HAVE_RNGA) + INIT_COMPLETION(rng_self_testing); + INIT_COMPLETION(rng_seed_done); +#endif + rng_work_queue.head = NULL; + rng_work_queue.tail = NULL; + + clk = clk_get(NULL, "rng_clk"); + + // Check that the clock was found + if (IS_ERR(clk)) { + LOG_KDIAG("RNG: Failed to find rng_clock."); + return_code = OS_ERROR_FAIL_S; + goto check_err; + } + + clk_enable(clk); + + os_printk(KERN_INFO "RNG Driver: Loading\n"); + + return_code = rng_map_RNG_memory(); + if (return_code != OS_ERROR_OK_S) { + rng_availability = RNG_STATUS_UNIMPLEMENTED; + LOG_KDIAG_ARGS("RNG: Driver failed to map RNG registers. %d", + return_code); + goto check_err; + } + LOG_KDIAG_ARGS("RNG Driver: rng_base is 0x%08x", (uint32_t) rng_base); + /*Check SCC keys are fused */ + if (RNG_HAS_ERROR()) { + if (RNG_HAS_BAD_KEY()) { +#ifdef RNG_DEBUG +#if !defined(FSL_HAVE_RNGA) + LOG_KDIAG("ERROR: BAD KEYS SELECTED"); + { + uint32_t rngc_status = + RNG_READ_REGISTER(RNGC_STATUS); + uint32_t rngc_error = + RNG_READ_REGISTER(RNGC_ERROR); + LOG_KDIAG_ARGS + ("status register: %08x, error status: %08x", + rngc_status, rngc_error); + } +#endif +#endif + rng_availability = RNG_STATUS_FAILED; + return_code = OS_ERROR_FAIL_S; + goto check_err; + } + } + + /* Check RNG configuration and status */ + return_code = rng_grab_config_values(); + if (return_code != OS_ERROR_OK_S) { + rng_availability = RNG_STATUS_UNIMPLEMENTED; + goto check_err; + } + + /* Masking All Interrupts */ + /* They are unmasked later in rng_setup_interrupt_handling() */ + RNG_MASK_ALL_INTERRUPTS(); + + RNG_WAKE(); + + /* Determine status of RNG */ + if (RNG_OSCILLATOR_FAILED()) { + LOG_KDIAG("RNG Driver: RNG Oscillator is dead"); + rng_availability = RNG_STATUS_FAILED; + goto check_err; + } + + /* Oscillator not dead. Setup interrupt code and start the RNG. */ + if ((return_code = rng_setup_interrupt_handling()) == OS_ERROR_OK_S) { +#if defined(FSL_HAVE_RNGA) + scc_return_t scc_code; +#endif + + RNG_GO(); + + /* Self Testing For RNG */ + do { + RNG_CLEAR_ERR(); + + /* wait for Clearing Erring finished */ + msleep(1); + + RNG_UNMASK_ALL_INTERRUPTS(); + RNG_SELF_TEST(); +#if !defined(FSL_HAVE_RNGA) + wait_for_completion(&rng_self_testing); +#endif + } while (RNG_CHECK_SELF_ERR()); + + RNG_CLEAR_ALL_STATUS(); + /* checking for RNG SEED done */ + do { + RNG_CLEAR_ERR(); + RNG_SEED_GEN(); +#if !defined(FSL_HAVE_RNGA) + wait_for_completion(&rng_seed_done); +#endif + } while (RNG_CHECK_SEED_ERR()); +#ifndef RNG_NO_FORCE_HIGH_ASSURANCE + RNG_SET_HIGH_ASSURANCE(); +#endif + if (RNG_GET_HIGH_ASSURANCE()) { + LOG_KDIAG("RNG Driver: RNG is in High Assurance mode"); + } else { +#ifndef RNG_NO_FORCE_HIGH_ASSURANCE + LOG_KDIAG + ("RNG Driver: RNG could not be put in High Assurance mode"); + rng_availability = RNG_STATUS_FAILED; + goto check_err; +#endif /* RNG_NO_FORCE_HIGH_ASSURANCE */ + } + + /* Check that RNG is OK */ + if (!RNG_WORKING()) { + LOG_KDIAG_ARGS + ("RNG determined to be inoperable. Status %08x", + RNG_GET_STATUS()); + /* Couldn't wake it up or other problem */ + rng_availability = RNG_STATUS_FAILED; + goto check_err; + } + + rng_queue_lock = os_lock_alloc_init(); + if (rng_queue_lock == NULL) { + LOG_KDIAG("RNG: lock initialization failed"); + rng_availability = RNG_STATUS_FAILED; + goto check_err; + } + + return_code = os_create_task(rng_entropy_task); + if (return_code != OS_ERROR_OK_S) { + LOG_KDIAG("RNG: task initialization failed"); + rng_availability = RNG_STATUS_FAILED; + goto check_err; + } else { + task_started = TRUE; + } +#ifdef FSL_HAVE_RNGA + scc_code = scc_monitor_security_failure(rng_sec_failure); + if (scc_code != SCC_RET_OK) { + LOG_KDIAG_ARGS("Failed to register SCC callback: %d", + scc_code); +#ifndef RNG_NO_FORCE_HIGH_ASSURANCE + return_code = OS_ERROR_FAIL_S; + goto check_err; +#endif + } +#endif /* FSL_HAVE_RNGA */ + return_code = os_driver_init_registration(rng_reg_handle); + if (return_code != OS_ERROR_OK_S) { + goto check_err; + } + /* add power suspend here */ + /* add power resume here */ + return_code = + os_driver_complete_registration(rng_reg_handle, + rng_major, RNG_DRIVER_NAME); + } + /* RNG is working */ + + check_err: + + /* If FIFO underflow or other error occurred during drain, this will fail, + * as system will have been put into fail mode by SCC. */ + if ((return_code == OS_ERROR_OK_S) + && (rng_availability == RNG_STATUS_CHECKING)) { + RNG_PUT_RNG_TO_SLEEP(); + rng_availability = RNG_STATUS_OK; /* RNG & driver are ready */ + } else if (return_code != OS_ERROR_OK_S) { + os_printk(KERN_ALERT "Driver initialization failed. %d", + return_code); + rng_cleanup(); + } + + os_dev_init_return(return_code); + +} /* rng_init */ + +/*****************************************************************************/ +/* fn rng_shutdown() */ +/*****************************************************************************/ +/*! + * Prepare driver for exit. + * + * This is called during @c rmmod when the driver is unloading. + * Try to undo whatever was done during #rng_init(), to make the machine be + * in the same state, if possible. + * + * Calls rng_cleanup() to do all work, and then unmap device's register space. + */ +OS_DEV_SHUTDOWN(rng_shutdown) +{ + LOG_KDIAG("shutdown called"); + + rng_cleanup(); + + os_driver_remove_registration(rng_reg_handle); + if (rng_base != NULL) { + /* release the virtual memory map to the RNG */ + os_unmap_device((void *)rng_base, RNG_ADDRESS_RANGE); + rng_base = NULL; + } + + os_dev_shutdown_return(OS_ERROR_OK_S); +} /* rng_shutdown */ + +/*****************************************************************************/ +/* fn rng_cleanup() */ +/*****************************************************************************/ +/*! + * Undo everything done by rng_init() and place driver in fail mode. + * + * Deregister from SCC, stop tasklet, shutdown the RNG. Leave the register + * map in place in case other drivers call rng_read/write_register() + * + * @return void + */ +static void rng_cleanup(void) +{ + struct clk *clk; + +#ifdef FSL_HAVE_RNGA + scc_stop_monitoring_security_failure(rng_sec_failure); +#endif + + clk = clk_get(NULL, "rng_clk"); + clk_disable(clk); + if (task_started) { + os_dev_stop_task(rng_entropy_task); + } + + if (rng_base != NULL) { + /* mask off RNG interrupts */ + RNG_MASK_ALL_INTERRUPTS(); + RNG_SLEEP(); + + if (rng_irq_set) { + /* unmap the interrupts from the IRQ lines */ + os_deregister_interrupt(INT_RNG); + rng_irq_set = FALSE; + } + LOG_KDIAG("Leaving rng driver status as failed"); + rng_availability = RNG_STATUS_FAILED; + } else { + LOG_KDIAG("Leaving rng driver status as unimplemented"); + rng_availability = RNG_STATUS_UNIMPLEMENTED; + } + LOG_KDIAG("Cleaned up"); +} /* rng_cleanup */ + +/*! + * Post-process routine for fsl_shw_get_random(). + * + * This function will copy the random data generated by the background task + * into the user's buffer and then free the local buffer. + * + * @param gen_entry The work request. + * + * @return 0 = meaning work completed, pass back result. + */ +static uint32_t finish_random(shw_queue_entry_t * gen_entry) +{ + rng_work_entry_t *work = (rng_work_entry_t *) gen_entry; + + if (work->hdr.flags & FSL_UCO_USERMODE_USER) { + os_copy_to_user(work->data_user, work->data_local, + work->length); + } else { + memcpy(work->data_user, work->data_local, work->length); + } + + os_free_memory(work->data_local); + work->data_local = NULL; + + return 0; /* means completed. */ +} + +/* REQ-FSLSHW-PINTFC-API-BASIC-RNG-002 */ +/*****************************************************************************/ +/* fn fsl_shw_get_random() */ +/*****************************************************************************/ +/*! + * Get random data. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param length The number of octets of @a data being requested. + * @param data A pointer to a location of @a length octets to where + * random data will be returned. + * + * @return FSL_RETURN_NO_RESOURCE_S A return code of type #fsl_shw_return_t. + * FSL_RETURN_OK_S + */ +fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx, uint32_t length, + uint8_t * data) +{ + fsl_shw_return_t return_code = FSL_RETURN_NO_RESOURCE_S; + /* Boost up length to cover any 'missing' bytes at end of a word */ + uint32_t *buf = os_alloc_memory(length + 3, 0); + volatile rng_work_entry_t *work = os_alloc_memory(sizeof(*work), 0); + + if ((rng_availability != RNG_STATUS_OK) || (buf == NULL) + || (work == NULL)) { + if (rng_availability != RNG_STATUS_OK) { + LOG_KDIAG_ARGS("rng not available: %d\n", + rng_availability); + } else { + LOG_KDIAG_ARGS + ("Resource allocation failure: %d or %d bytes", + length, sizeof(*work)); + } + /* Cannot perform function. Clean up and clear out. */ + if (buf != NULL) { + os_free_memory(buf); + } + if (work != NULL) { + os_free_memory((void *)work); + } + } else { + unsigned blocking = user_ctx->flags & FSL_UCO_BLOCKING_MODE; + + work->hdr.user_ctx = user_ctx; + work->hdr.flags = user_ctx->flags; + work->hdr.callback = user_ctx->callback; + work->hdr.user_ref = user_ctx->user_ref; + work->hdr.postprocess = finish_random; + work->length = length; + work->data_local = buf; + work->data_user = data; + + RNG_ADD_WORK_ENTRY((rng_work_entry_t *) work); + + if (blocking) { + os_sleep(rng_wait_queue, work->completed != FALSE, + FALSE); + finish_random((shw_queue_entry_t *) work); + return_code = work->hdr.code; + os_free_memory((void *)work); + } else { + return_code = FSL_RETURN_OK_S; + } + } + + return return_code; +} /* fsl_shw_get_entropy */ + +/*****************************************************************************/ +/* fn fsl_shw_add_entropy() */ +/*****************************************************************************/ +/*! + * Add entropy to random number generator. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param length Number of bytes at @a data. + * @param data Entropy to add to random number generator. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx, uint32_t length, + uint8_t * data) +{ + fsl_shw_return_t return_code = FSL_RETURN_NO_RESOURCE_S; +#if defined(FSL_HAVE_RNGC) + /* No Entropy Register in RNGC */ + return_code = FSL_RETURN_OK_S; +#else + uint32_t *local_data = NULL; + if (rng_availability == RNG_STATUS_OK) { + /* make 32-bit aligned place to hold data */ + local_data = os_alloc_memory(length + 3, 0); + if (local_data == NULL) { + return_code = FSL_RETURN_NO_RESOURCE_S; + } else { + memcpy(local_data, data, length); + + /* Copy one word at a time to hardware */ + while (TRUE) { + register uint32_t *ptr = local_data; + + RNG_ADD_ENTROPY(*ptr++); + if (length <= 4) { + break; + } + length -= 4; + } + return_code = FSL_RETURN_OK_S; + os_free_memory(local_data); + } /* else local_data not NULL */ + + } +#endif + /* rng_availability is OK */ + return return_code; +} /* fsl_shw_add_entropy */ + +#ifdef RNG_REGISTER_PEEK_POKE +/*****************************************************************************/ +/* fn rng_read_register() */ +/*****************************************************************************/ +/* + * Debug routines to allow reading of RNG registers. + * + * This routine is only for accesses by other than this driver. + * + * @param register_offset The byte offset of the register to be read. + * @param value Pointer to store the value of the register. + * + * @return RNG_RET_OK or an error return. + */ +rng_return_t rng_read_register(uint32_t register_offset, uint32_t * value) +{ + rng_return_t return_code = RNG_RET_FAIL; + + if ((rng_availability == RNG_STATUS_OK) + || (rng_availability == RNG_STATUS_FAILED)) { + if ((rng_check_register_offset(register_offset) + && rng_check_register_accessible(register_offset, + RNG_CHECK_READ))) { + /* The guards let the check through */ + *value = RNG_READ_REGISTER(register_offset); + return_code = RNG_RET_OK; + } + } + + return return_code; +} /* rng_read_register */ + +/*****************************************************************************/ +/* fn rng_write_register() */ +/*****************************************************************************/ +/* + * Debug routines to allow writing of RNG registers. + * + * This routine is only for accesses by other than this driver. + * + * @param register_offset The byte offset of the register to be written. + * @param value Value to store in the register. + * + * @return RNG_RET_OK or an error return. + */ +rng_return_t rng_write_register(uint32_t register_offset, uint32_t value) +{ + rng_return_t return_code = RNG_RET_FAIL; + + if ((rng_availability == RNG_STATUS_OK) + || (rng_availability == RNG_STATUS_FAILED)) { + if ((rng_check_register_offset(register_offset) + && rng_check_register_accessible(register_offset, + RNG_CHECK_WRITE))) { + RNG_WRITE_REGISTER(register_offset, value); + return_code = RNG_RET_OK; + } + } + + return return_code; +} /* rng_write_register */ +#endif /* RNG_REGISTER_PEEK_POKE */ + +/****************************************************************************** + * + * Function Implementations - Internal + * + *****************************************************************************/ + +#ifdef RNG_REGISTER_PEEK_POKE +/*****************************************************************************/ +/* fn check_register_offset() */ +/*****************************************************************************/ +/*! + * Verify that the @c offset is appropriate for the RNG's register set. + * + * @param[in] offset The (byte) offset within the RNG block + * of the register to be accessed. See + * RNG(A, C) register definitions for meanings. + * + * This routine is only for checking accesses by other than this driver. + * + * @return 0 if register offset out of bounds, 1 if ok to use + */ +inline int rng_check_register_offset(uint32_t offset) +{ + int return_code = FALSE; /* invalid */ + + /* Make sure offset isn't too high and also that it is aligned to + * aa 32-bit offset (multiple of four). + */ + if ((offset < RNG_ADDRESS_RANGE) && (offset % sizeof(uint32_t) == 0)) { + return_code = TRUE; /* OK */ + } else { + pr_debug("RNG: Denied access to offset %8x\n", offset); + } + + return return_code; + +} /* rng_check_register */ + +/*****************************************************************************/ +/* fn check_register_accessible() */ +/*****************************************************************************/ +/*! + * Make sure that register access is legal. + * + * Verify that, if in secure mode, only safe registers are used. + * For any register access, make sure that read-only registers are not written + * and that write-only registers are not read. This check also disallows any + * access to the RNG's Output FIFO, to prevent other drivers from draining the + * FIFO and causing an underflow condition. + * + * This routine is only for checking accesses by other than this driver. + * + * @param offset The (byte) offset within the RNG block + * of the register to be accessed. See + * @ref rngregs for meanings. + * @param access_write 0 for read, anything else for write + * + * @return 0 if invalid, 1 if OK. + */ +static int rng_check_register_accessible(uint32_t offset, int access_write) +{ + int return_code = FALSE; /* invalid */ + uint32_t secure = RNG_GET_HIGH_ASSURANCE(); + + /* First check for RNG in Secure Mode -- most registers inaccessible. + * Also disallowing access to RNG_OUTPUT_FIFO except by the driver. + */ + if (! +#ifdef FSL_HAVE_RNGA + (secure && + ((offset == RNGA_OUTPUT_FIFO) || + (offset == RNGA_MODE) || + (offset == RNGA_VERIFICATION_CONTROL) || + (offset == RNGA_OSCILLATOR_CONTROL_COUNTER) || + (offset == RNGA_OSCILLATOR1_COUNTER) || + (offset == RNGA_OSCILLATOR2_COUNTER) || + (offset == RNGA_OSCILLATOR_COUNTER_STATUS))) +#else /* RNGB or RNGC */ + (secure && + ((offset == RNGC_FIFO) || + (offset == RNGC_VERIFICATION_CONTROL) || + (offset == RNGC_OSC_COUNTER_CONTROL) || + (offset == RNGC_OSC_COUNTER) || + (offset == RNGC_OSC_COUNTER_STATUS))) +#endif + ) { + + /* Passed that test. Either not in high assurance, and/or are + checking register that is always available. Now check + R/W permissions. */ + if (access_write == RNG_CHECK_READ) { /* read request */ + /* Only the entropy register is write-only */ +#ifdef FSL_HAVE_RNGC + /* No registers are write-only */ + return_code = TRUE; +#else /* else RNGA or RNGB */ +#ifdef FSL_HAVE_RNGA + if (1) { +#else + if (!(offset == RNGB_ENTROPY)) { +#endif + return_code = TRUE; /* Let all others be read */ + } else { + pr_debug + ("RNG: Offset %04x denied read access\n", + offset); + } +#endif /* RNGA or RNGB */ + } /* read */ + else { /* access_write means write */ + /* Check against list of non-writable registers */ + if (! +#ifdef FSL_HAVE_RNGA + ((offset == RNGA_STATUS) || + (offset == RNGA_OUTPUT_FIFO) || + (offset == RNGA_OSCILLATOR1_COUNTER) || + (offset == RNGA_OSCILLATOR2_COUNTER) || + (offset == RNGA_OSCILLATOR_COUNTER_STATUS)) +#else /* FSL_HAVE_RNGB or FSL_HAVE_RNGC */ + ((offset == RNGC_STATUS) || + (offset == RNGC_FIFO) || + (offset == RNGC_OSC_COUNTER) || + (offset == RNGC_OSC_COUNTER_STATUS)) +#endif + ) { + return_code = TRUE; /* can be written */ + } else { + LOG_KDIAG_ARGS + ("Offset %04x denied write access", offset); + } + } /* write */ + } /* not high assurance and inaccessible register... */ + else { + LOG_KDIAG_ARGS("Offset %04x denied high-assurance access", + offset); + } + + return return_code; +} /* rng_check_register_accessible */ +#endif /* RNG_REGISTER_PEEK_POKE */ + +/*****************************************************************************/ +/* fn rng_irq() */ +/*****************************************************************************/ +/*! + * This is the interrupt handler for the RNG. It is only ever invoked if the + * RNG detects a FIFO Underflow error. + * + * If the error is a Security Violation, this routine will + * set the #rng_availability to #RNG_STATUS_FAILED, as the entropy pool may + * have been corrupted. The RNG will also be placed into low power mode. The + * SCC will have noticed the problem as well. + * + * The other possibility, if the RNG is not in High Assurance mode, would be + * simply a FIFO Underflow. No special action, other than to + * clear the interrupt, is taken. + */ +OS_DEV_ISR(rng_irq) +{ + int handled = FALSE; /* assume interrupt isn't from RNG */ + + LOG_KDIAG("rng irq!"); + + if (RNG_SEED_DONE()) { + complete(&rng_seed_done); + RNG_CLEAR_ALL_STATUS(); + handled = TRUE; + } + + if (RNG_SELF_TEST_DONE()) { + complete(&rng_self_testing); + RNG_CLEAR_ALL_STATUS(); + handled = TRUE; + } + /* Look to see whether RNG needs attention */ + if (RNG_HAS_ERROR()) { + if (RNG_GET_HIGH_ASSURANCE()) { + RNG_SLEEP(); + rng_availability = RNG_STATUS_FAILED; + RNG_MASK_ALL_INTERRUPTS(); + } + handled = TRUE; + /* Clear the interrupt */ + RNG_CLEAR_ALL_STATUS(); + + } + os_dev_isr_return(handled); +} /* rng_irq */ + +/*****************************************************************************/ +/* fn map_RNG_memory() */ +/*****************************************************************************/ +/*! + * Place the RNG's memory into kernel virtual space. + * + * @return OS_ERROR_OK_S on success, os_error_code on failure + */ +static os_error_code rng_map_RNG_memory(void) +{ + os_error_code error_code = OS_ERROR_FAIL_S; + + rng_base = os_map_device(RNG_BASE_ADDR, RNG_ADDRESS_RANGE); + if (rng_base == NULL) { + /* failure ! */ + LOG_KDIAG("RNG Driver: ioremap failed."); + } else { + error_code = OS_ERROR_OK_S; + } + + return error_code; +} /* rng_map_RNG_memory */ + +/*****************************************************************************/ +/* fn rng_setup_interrupt_handling() */ +/*****************************************************************************/ +/*! + * Register #rng_irq() as the interrupt handler for #INT_RNG. + * + * @return OS_ERROR_OK_S on success, os_error_code on failure + */ +static os_error_code rng_setup_interrupt_handling(void) +{ + os_error_code error_code; + + /* + * Install interrupt service routine for the RNG. Ignore the + * assigned IRQ number. + */ + error_code = os_register_interrupt(RNG_DRIVER_NAME, INT_RNG, + OS_DEV_ISR_REF(rng_irq)); + if (error_code != OS_ERROR_OK_S) { + LOG_KDIAG("RNG Driver: Error installing Interrupt Handler"); + } else { + rng_irq_set = TRUE; + RNG_UNMASK_ALL_INTERRUPTS(); + } + + return error_code; +} /* rng_setup_interrupt_handling */ + +/*****************************************************************************/ +/* fn rng_grab_config_values() */ +/*****************************************************************************/ +/*! + * Read configuration information from the RNG. + * + * Sets #rng_output_fifo_size. + * + * @return A error code indicating whether the part is the expected one. + */ +static os_error_code rng_grab_config_values(void) +{ + enum rng_type type; + os_error_code ret = OS_ERROR_FAIL_S; + + /* Go for type, versions... */ + type = RNG_GET_RNG_TYPE(); + + /* Make sure type is the one this code has been compiled for. */ + if (RNG_VERIFY_TYPE(type)) { + rng_output_fifo_size = RNG_GET_FIFO_SIZE(); + if (rng_output_fifo_size != 0) { + ret = OS_ERROR_OK_S; + } + } + if (ret != OS_ERROR_OK_S) { + LOG_KDIAG_ARGS + ("Unknown or unexpected RNG type %d (FIFO size %d)." + " Failing driver initialization", type, + rng_output_fifo_size); + } + + return ret; +} + + /* rng_grab_config_values */ + +/*****************************************************************************/ +/* fn rng_drain_fifo() */ +/*****************************************************************************/ +/*! + * This function copies words from the RNG FIFO into the caller's buffer. + * + * + * @param random_p Location to copy random data + * @param count_words Number of words to copy + * + * @return An error code. + */ +static fsl_shw_return_t rng_drain_fifo(uint32_t * random_p, int count_words) +{ + + int words_in_rng; /* Number of words available now in RNG */ + fsl_shw_return_t code = FSL_RETURN_ERROR_S; + int sequential_count = 0; /* times through big while w/empty FIFO */ + int fifo_empty_count = 0; /* number of times FIFO was empty */ + int max_sequential = 0; /* max times 0 seen in a row */ +#if !defined(FSL_HAVE_RNGA) + int count_for_reseed = 0; + INIT_COMPLETION(rng_seed_done); +#endif +#if !defined(FSL_HAVE_RNGA) + if (RNG_RESEED()) { + do { + LOG_KDIAG("Reseeding RNG"); + + RNG_CLEAR_ERR(); + RNG_SEED_GEN(); + wait_for_completion(&rng_seed_done); + if (count_for_reseed == 3) { + os_printk(KERN_ALERT + "Device was not able to enter RESEED Mode\n"); + code = FSL_RETURN_INTERNAL_ERROR_S; + } + count_for_reseed++; + } while (RNG_CHECK_SEED_ERR()); + } +#endif + /* Copy all of them in. Stop if pool fills. */ + while ((rng_availability == RNG_STATUS_OK) && (count_words > 0)) { + /* Ask RNG how many words currently in FIFO */ + words_in_rng = RNG_GET_WORDS_IN_FIFO(); + if (words_in_rng == 0) { + ++sequential_count; + fifo_empty_count++; + if (sequential_count > max_sequential) { + max_sequential = sequential_count; + } + if (sequential_count >= RNG_MAX_TRIES) { + LOG_KDIAG_ARGS("FIFO staying empty (%d)", + words_in_rng); + code = FSL_RETURN_NO_RESOURCE_S; + break; + } + } else { + /* Found at least one word */ + sequential_count = 0; + /* Now adjust: words_in_rng = MAX(count_words, words_in_rng) */ + words_in_rng = (count_words < words_in_rng) + ? count_words : words_in_rng; + } /* else found words */ + +#ifdef RNG_FORCE_FIFO_UNDERFLOW + /* + * For unit test, force occasional extraction of more words than + * available. This should cause FIFO Underflow, and IRQ invocation. + */ + words_in_rng = count_words; +#endif + + /* Copy out all available & neeeded data */ + while (words_in_rng-- > 0) { + *random_p++ = RNG_READ_FIFO(); + count_words--; + } + } /* while words still needed */ + + if (count_words == 0) { + code = FSL_RETURN_OK_S; + } + if (fifo_empty_count != 0) { + LOG_KDIAG_ARGS("FIFO empty %d times, max loop count %d", + fifo_empty_count, max_sequential); + } + + return code; +} /* rng_drain_fifo */ + +/*****************************************************************************/ +/* fn rng_entropy_task() */ +/*****************************************************************************/ +/*! + * This is the background task of the driver. It is scheduled by + * RNG_ADD_WORK_ENTRY(). + * + * This will process each entry on the #rng_work_queue. Blocking requests will + * cause sleepers to be awoken. Non-blocking requests will be placed on the + * results queue, and if appropriate, the callback function will be invoked. + */ +OS_DEV_TASK(rng_entropy_task) +{ + rng_work_entry_t *work; + + os_dev_task_begin(); + +#ifdef RNG_ENTROPY_DEBUG + LOG_KDIAG("entropy task starting"); +#endif + + while ((work = RNG_GET_WORK_ENTRY()) != NULL) { +#ifdef RNG_ENTROPY_DEBUG + LOG_KDIAG_ARGS("found %d bytes of work at %p (%p)", + work->length, work, work->data_local); +#endif + work->hdr.code = rng_drain_fifo(work->data_local, + BYTES_TO_WORDS(work->length)); + work->completed = TRUE; + + if (work->hdr.flags & FSL_UCO_BLOCKING_MODE) { +#ifdef RNG_ENTROPY_DEBUG + LOG_KDIAG("Waking queued processes"); +#endif + os_wake_sleepers(rng_wait_queue); + } else { + os_lock_context_t lock_context; + + os_lock_save_context(rng_queue_lock, lock_context); + RNG_ADD_QUEUE_ENTRY(&work->hdr.user_ctx->result_pool, + work); + os_unlock_restore_context(rng_queue_lock, lock_context); + + if (work->hdr.flags & FSL_UCO_CALLBACK_MODE) { + if (work->hdr.callback != NULL) { + work->hdr.callback(work->hdr.user_ctx); + } else { +#ifdef RNG_ENTROPY_DEBUG + LOG_KDIAG_ARGS + ("Callback ptr for %p is NULL", + work); +#endif + } + } + } + } /* while */ + +#ifdef RNG_ENTROPY_DEBUG + LOG_KDIAG("entropy task ending"); +#endif + + os_dev_task_return(OS_ERROR_OK_S); +} /* rng_entropy_task */ + +#ifdef FSL_HAVE_RNGA +/*****************************************************************************/ +/* fn rng_sec_failure() */ +/*****************************************************************************/ +/*! + * Function to handle "Security Alarm" indication from SCC. + * + * This function is registered with the Security Monitor ans the callback + * function for the RNG driver. Upon alarm, it will shut down the driver so + * that no more random data can be retrieved. + * + * @return void + */ +static void rng_sec_failure(void) +{ + os_printk(KERN_ALERT "RNG Driver: Security Failure Alarm received.\n"); + + rng_cleanup(); + + return; +} +#endif + +#ifdef RNG_REGISTER_DEBUG +/*****************************************************************************/ +/* fn dbg_rng_read_register() */ +/*****************************************************************************/ +/*! + * Noisily read a 32-bit value to an RNG register. + * @param offset The address of the register to read. + * + * @return The register value + * */ +static uint32_t dbg_rng_read_register(uint32_t offset) +{ + uint32_t value; + + value = os_read32(rng_base + offset); +#ifndef RNG_ENTROPY_DEBUG + if (offset != RNG_OUTPUT_FIFO) { +#endif + pr_debug("RNG RD: 0x%4x : 0x%08x\n", offset, value); +#ifndef RNG_ENTROPY_DEBUG + } +#endif + return value; +} + +/*****************************************************************************/ +/* fn dbg_rng_write_register() */ +/*****************************************************************************/ +/*! + * Noisily write a 32-bit value to an RNG register. + * @param offset The address of the register to written. + * + * @param value The new register value + */ +static void dbg_rng_write_register(uint32_t offset, uint32_t value) +{ + LOG_KDIAG_ARGS("WR: 0x%4x : 0x%08x", offset, value); + os_write32(value, rng_base + offset); + return; +} + +#endif /* RNG_REGISTER_DEBUG */ diff -urN linux-2.6.26/drivers/mxc/security/rng/shw_driver.c linux-2.6.26-lab126/drivers/mxc/security/rng/shw_driver.c --- linux-2.6.26/drivers/mxc/security/rng/shw_driver.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/shw_driver.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,2335 @@ +/* + * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! @file shw_driver.c + * + * This is the user-mode driver code for the FSL Security Hardware (SHW) API. + * as well as the 'common' FSL SHW API code for kernel API users. + * + * Its interaction with the Linux kernel is from calls to shw_init() when the + * driver is loaded, and shw_shutdown() should the driver be unloaded. + * + * The User API (driver interface) is handled by the following functions: + * @li shw_open() - handles open() system call on FSL SHW device + * @li shw_release() - handles close() system call on FSL SHW device + * @li shw_ioctl() - handles ioctl() system call on FSL SHW device + * + * The driver also provides the following functions for kernel users of the FSL + * SHW API: + * @li fsl_shw_register_user() + * @li fsl_shw_deregister_user() + * @li fsl_shw_get_capabilities() + * @li fsl_shw_get_results() + * + * All other functions are internal to the driver. + * + * The life of the driver starts at boot (or module load) time, with a call by + * the kernel to shw_init(). + * + * The life of the driver ends when the kernel is shutting down (or the driver + * is being unloaded). At this time, shw_shutdown() is called. No function + * will ever be called after that point. + * + * In the case that the driver is reloaded, a new copy of the driver, with + * fresh global values, etc., is loaded, and there will be a new call to + * shw_init(). + * + * In user mode, the user's fsl_shw_register_user() call causes an open() event + * on the driver followed by a ioctl() with the registration information. Any + * subsequent API calls by the user are handled through the ioctl() function + * and shuffled off to the appropriate routine (or driver) for service. The + * fsl_shw_deregister_user() call by the user results in a close() function + * call on the driver. + * + * In kernel mode, the driver provides the functions fsl_shw_register_user(), + * fsl_shw_deregister_user(), fsl_shw_get_capabilities(), and + * fsl_shw_get_results(). Other parts of the API are provided by other + * drivers, if available, to support the cryptographic functions. + */ + +#include "portable_os.h" +#include "fsl_shw.h" +#include "fsl_shw_keystore.h" + +#include "shw_internals.h" + +#ifdef FSL_HAVE_SCC2 +#include +#else +#include +#endif + +#ifdef SHW_DEBUG +#include +#endif + +/****************************************************************************** + * + * Function Declarations + * + *****************************************************************************/ + +/* kernel interface functions */ +OS_DEV_INIT_DCL(shw_init); +OS_DEV_SHUTDOWN_DCL(shw_shutdown); +OS_DEV_IOCTL_DCL(shw_ioctl); +OS_DEV_MMAP_DCL(shw_mmap); + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_smalloc); +EXPORT_SYMBOL(fsl_shw_sfree); +EXPORT_SYMBOL(fsl_shw_sstatus); +EXPORT_SYMBOL(fsl_shw_diminish_perms); +EXPORT_SYMBOL(do_scc_encrypt_region); +EXPORT_SYMBOL(do_scc_decrypt_region); + +EXPORT_SYMBOL(do_system_keystore_slot_alloc); +EXPORT_SYMBOL(do_system_keystore_slot_dealloc); +EXPORT_SYMBOL(do_system_keystore_slot_load); +EXPORT_SYMBOL(do_system_keystore_slot_encrypt); +EXPORT_SYMBOL(do_system_keystore_slot_decrypt); +#endif + +static os_error_code +shw_handle_scc_sfree(fsl_shw_uco_t * user_ctx, uint32_t info); + +static os_error_code +shw_handle_scc_sstatus(fsl_shw_uco_t * user_ctx, uint32_t info); + +static os_error_code +shw_handle_scc_drop_perms(fsl_shw_uco_t * user_ctx, uint32_t info); + +static os_error_code +shw_handle_scc_encrypt(fsl_shw_uco_t * user_ctx, uint32_t info); + +static os_error_code +shw_handle_scc_decrypt(fsl_shw_uco_t * user_ctx, uint32_t info); + +#ifdef FSL_HAVE_SCC2 +static fsl_shw_return_t register_user_partition(fsl_shw_uco_t * user_ctx, + uint32_t user_base, + void *kernel_base); +static fsl_shw_return_t deregister_user_partition(fsl_shw_uco_t * user_ctx, + uint32_t user_base); +void *lookup_user_partition(fsl_shw_uco_t * user_ctx, uint32_t user_base); + +#endif /* FSL_HAVE_SCC2 */ + +/****************************************************************************** + * + * Global / Static Variables + * + *****************************************************************************/ + +/*! + * Major node (user/device interaction value) of this driver. + */ +static int shw_major_node = SHW_MAJOR_NODE; + +/*! + * Flag to know whether the driver has been associated with its user device + * node (e.g. /dev/shw). + */ +static int shw_device_registered = 0; + +/*! + * OS-dependent handle used for registering user interface of a driver. + */ +static os_driver_reg_t reg_handle; + +/*! + * Linked List of registered users of the API + */ +fsl_shw_uco_t *user_list; + +/*! + * This is the lock for all user request pools. H/W component drivers may also + * use it for their own work queues. + */ +os_lock_t shw_queue_lock = NULL; + +/* This is the system keystore object */ +fsl_shw_kso_t system_keystore; + +#ifndef FSL_HAVE_SAHARA +/*! Empty list of supported symmetric algorithms. */ +static fsl_shw_key_alg_t pf_syms[] = { +}; + +/*! Empty list of supported symmetric modes. */ +static fsl_shw_sym_mode_t pf_modes[] = { +}; + +/*! Empty list of supported hash algorithms. */ +static fsl_shw_hash_alg_t pf_hashes[] = { +}; +#endif /* no Sahara */ + +/*! This matches SHW capabilities... */ +static fsl_shw_pco_t cap = { + 1, 3, /* api version number - major & minor */ + 2, 3, /* driver version number - major & minor */ + sizeof(pf_syms) / sizeof(fsl_shw_key_alg_t), /* key alg count */ + pf_syms, /* key alg list ptr */ + sizeof(pf_modes) / sizeof(fsl_shw_sym_mode_t), /* sym mode count */ + pf_modes, /* modes list ptr */ + sizeof(pf_hashes) / sizeof(fsl_shw_hash_alg_t), /* hash alg count */ + pf_hashes, /* hash list ptr */ + /* + * The following table must be set to handle all values of key algorithm + * and sym mode, and be in the correct order.. + */ + { /* Stream, ECB, CBC, CTR */ + {0, 0, 0, 0} + , /* HMAC */ + {0, 0, 0, 0} + , /* AES */ + {0, 0, 0, 0} + , /* DES */ +#ifdef FSL_HAVE_DRYICE + {0, 1, 1, 0} + , /* 3DES - ECB and CBC */ +#else + {0, 0, 0, 0} + , /* 3DES */ +#endif + {0, 0, 0, 0} /* ARC4 */ + } + , + 0, 0, /* SCC driver version */ + 0, 0, 0, /* SCC version/capabilities */ + {{0, 0} + } + , /* (filled in during OS_INIT) */ +}; + +/* These are often handy */ +#ifndef FALSE +/*! Not true. Guaranteed to be zero. */ +#define FALSE 0 +#endif +#ifndef TRUE +/*! True. Guaranteed to be non-zero. */ +#define TRUE 1 +#endif + +/****************************************************************************** + * + * Function Implementations - Externally Accessible + * + *****************************************************************************/ + +/*****************************************************************************/ +/* fn shw_init() */ +/*****************************************************************************/ +/*! + * Initialize the driver. + * + * This routine is called during kernel init or module load (insmod). + * + * @return OS_ERROR_OK_S on success, errno on failure + */ +OS_DEV_INIT(shw_init) +{ + os_error_code error_code = OS_ERROR_NO_MEMORY_S; /* assume failure */ + scc_config_t *shw_capabilities; + +#ifdef SHW_DEBUG + LOG_KDIAG("SHW Driver: Loading"); +#endif + + user_list = NULL; + shw_queue_lock = os_lock_alloc_init(); + + if (shw_queue_lock != NULL) { + error_code = shw_setup_user_driver_interaction(); + if (error_code != OS_ERROR_OK_S) { +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS + ("SHW Driver: Failed to setup user i/f: %d", + error_code); +#endif + } + } + + /* queue_lock not NULL */ + /* Fill in the SCC portion of the capabilities object */ + shw_capabilities = scc_get_configuration(); + cap.scc_driver_major = shw_capabilities->driver_major_version; + cap.scc_driver_minor = shw_capabilities->driver_minor_version; + cap.scm_version = shw_capabilities->scm_version; + cap.smn_version = shw_capabilities->smn_version; + cap.block_size_bytes = shw_capabilities->block_size_bytes; + +#ifdef FSL_HAVE_SCC + cap.u.scc_info.black_ram_size_blocks = + shw_capabilities->black_ram_size_blocks; + cap.u.scc_info.red_ram_size_blocks = + shw_capabilities->red_ram_size_blocks; +#elif defined(FSL_HAVE_SCC2) + cap.u.scc2_info.partition_size_bytes = + shw_capabilities->partition_size_bytes; + cap.u.scc2_info.partition_count = shw_capabilities->partition_count; +#endif + +#if defined(FSL_HAVE_SCC2) || defined(FSL_HAVE_DRYICE) + if (error_code == OS_ERROR_OK_S) { + /* set up the system keystore, using the default keystore handler */ + fsl_shw_init_keystore_default(&system_keystore); + + if (fsl_shw_establish_keystore(NULL, &system_keystore) + == FSL_RETURN_OK_S) { + error_code = OS_ERROR_OK_S; + } else { + error_code = OS_ERROR_FAIL_S; + } + + if (error_code != OS_ERROR_OK_S) { +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS + ("Registering the system keystore failed with error" + " code: %d\n", error_code); +#endif + } + } +#endif /* FSL_HAVE_SCC2 */ + + if (error_code != OS_ERROR_OK_S) { +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHW: Driver initialization failed. %d", + error_code); +#endif + shw_cleanup(); + } else { +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: Driver initialization complete."); +#endif + } + + os_dev_init_return(error_code); +} /* shw_init */ + +/*****************************************************************************/ +/* fn shw_shutdown() */ +/*****************************************************************************/ +/*! + * Prepare driver for exit. + * + * This is called during @c rmmod when the driver is unloading or when the + * kernel is shutting down. + * + * Calls shw_cleanup() to do all work to undo anything that happened during + * initialization or while driver was running. + */ +OS_DEV_SHUTDOWN(shw_shutdown) +{ + +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: shutdown called"); +#endif + shw_cleanup(); + + os_dev_shutdown_return(OS_ERROR_OK_S); +} /* shw_shutdown */ + +/*****************************************************************************/ +/* fn shw_cleanup() */ +/*****************************************************************************/ +/*! + * Prepare driver for shutdown. + * + * Remove the driver registration. + * + */ +static void shw_cleanup(void) +{ + if (shw_device_registered) { + + /* Turn off the all association with OS */ + os_driver_remove_registration(reg_handle); + shw_device_registered = 0; + } + + if (shw_queue_lock != NULL) { + os_lock_deallocate(shw_queue_lock); + } +#ifdef SHW_DEBUG + LOG_KDIAG("SHW Driver: Cleaned up"); +#endif +} /* shw_cleanup */ + +/*****************************************************************************/ +/* fn shw_open() */ +/*****************************************************************************/ +/*! + * Handle @c open() call from user. + * + * @return OS_ERROR_OK_S on success (always!) + */ +OS_DEV_OPEN(shw_open) +{ + os_error_code status = OS_ERROR_OK_S; + + os_dev_set_user_private(NULL); /* Make sure */ + + os_dev_open_return(status); +} /* shw_open */ + +/*****************************************************************************/ +/* fn shw_ioctl() */ +/*****************************************************************************/ +/*! + * Process an ioctl() request from user-mode API. + * + * This code determines which of the API requests the user has made and then + * sends the request off to the appropriate function. + * + * @return ioctl_return() + */ +OS_DEV_IOCTL(shw_ioctl) +{ + os_error_code code = OS_ERROR_FAIL_S; + + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHW: IOCTL %d received", os_dev_get_ioctl_op()); +#endif + switch (os_dev_get_ioctl_op()) { + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_REGISTER_USER: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: register_user ioctl received"); +#endif + { + fsl_shw_uco_t *user_ctx = + os_alloc_memory(sizeof(*user_ctx), 0); + + if (user_ctx == NULL) { + code = OS_ERROR_NO_MEMORY_S; + } else { + code = + init_uco(user_ctx, + (fsl_shw_uco_t *) + os_dev_get_ioctl_arg()); + if (code == OS_ERROR_OK_S) { + os_dev_set_user_private(user_ctx); + } else { + os_free_memory(user_ctx); + } + } + } + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_DEREGISTER_USER: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: deregister_user ioctl received"); +#endif + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + SHW_REMOVE_USER(user_ctx); + } + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_GET_RESULTS: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: get_results ioctl received"); +#endif + code = get_results(user_ctx, + (struct results_req *) + os_dev_get_ioctl_arg()); + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_GET_CAPABILITIES: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: get_capabilities ioctl received"); +#endif + code = get_capabilities(user_ctx, + (fsl_shw_pco_t *) + os_dev_get_ioctl_arg()); + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_GET_RANDOM: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: get_random ioctl received"); +#endif + code = get_random(user_ctx, + (struct get_random_req *) + os_dev_get_ioctl_arg()); + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_ADD_ENTROPY: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: add_entropy ioctl received"); +#endif + code = add_entropy(user_ctx, + (struct add_entropy_req *) + os_dev_get_ioctl_arg()); + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_DROP_PERMS: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: drop permissions ioctl received"); +#endif + code = + shw_handle_scc_drop_perms(user_ctx, os_dev_get_ioctl_arg()); + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_SSTATUS: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: sstatus ioctl received"); +#endif + code = shw_handle_scc_sstatus(user_ctx, os_dev_get_ioctl_arg()); + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_SFREE: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: sfree ioctl received"); +#endif + code = shw_handle_scc_sfree(user_ctx, os_dev_get_ioctl_arg()); + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_SCC_ENCRYPT: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: scc encrypt ioctl received"); +#endif + code = shw_handle_scc_encrypt(user_ctx, os_dev_get_ioctl_arg()); + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_SCC_DECRYPT: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: scc decrypt ioctl received"); +#endif + code = shw_handle_scc_decrypt(user_ctx, os_dev_get_ioctl_arg()); + break; + + default: +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHW: Unexpected ioctl %d", + os_dev_get_ioctl_op()); +#endif + break; + } + + os_dev_ioctl_return(code); +} + +#ifdef FSL_HAVE_SCC2 + +/*****************************************************************************/ +/* fn get_user_smid() */ +/*****************************************************************************/ +uint32_t get_user_smid(void *proc) +{ + /* + * A real implementation would have some way to handle signed applications + * which wouild be assigned distinct SMIDs. For the reference + * implementation, we show where this would be determined (here), but + * always provide a fixed answer, thus not separating users at all. + */ + + return 0x42eaae42; +} + +/* user_base: userspace base address of the partition + * kernel_base: kernel mode base address of the partition + */ +static fsl_shw_return_t register_user_partition(fsl_shw_uco_t * user_ctx, + uint32_t user_base, + void *kernel_base) +{ + fsl_shw_spo_t *partition_info; + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + if (user_ctx == NULL) { + goto out; + } + + partition_info = os_alloc_memory(sizeof(fsl_shw_spo_t), GFP_KERNEL); + + if (partition_info == NULL) { + goto out; + } + + /* stuff the partition info, then put it at the front of the chain */ + partition_info->user_base = user_base; + partition_info->kernel_base = kernel_base; + partition_info->next = user_ctx->partition; + + user_ctx->partition = (struct fsl_shw_spo_t *)partition_info; + +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS + ("partition with user_base=%p, kernel_base=%p registered.", + (void *)user_base, kernel_base); +#endif + + ret = FSL_RETURN_OK_S; + + out: + + return ret; +} + +/* if the partition is in the users list, remove it */ +static fsl_shw_return_t deregister_user_partition(fsl_shw_uco_t * user_ctx, + uint32_t user_base) +{ + fsl_shw_spo_t *curr = (fsl_shw_spo_t *) user_ctx->partition; + fsl_shw_spo_t *last = (fsl_shw_spo_t *) user_ctx->partition; + + while (curr != NULL) { + if (curr->user_base == user_base) { + +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS + ("deregister_user_partition: partition with " + "user_base=%p, kernel_base=%p deregistered.\n", + (void *)curr->user_base, curr->kernel_base); +#endif + + if (last == curr) { + user_ctx->partition = curr->next; + os_free_memory(curr); + return FSL_RETURN_OK_S; + } else { + last->next = curr->next; + os_free_memory(curr); + return FSL_RETURN_OK_S; + } + } + last = curr; + curr = (fsl_shw_spo_t *) curr->next; + } + + return FSL_RETURN_ERROR_S; +} + +/* Find the kernel-mode address of the partition. + * This can then be passed to the SCC functions. + */ +void *lookup_user_partition(fsl_shw_uco_t * user_ctx, uint32_t user_base) +{ + /* search through the partition chain to find one that matches the user base + * address. + */ + fsl_shw_spo_t *curr = (fsl_shw_spo_t *) user_ctx->partition; + + while (curr != NULL) { + if (curr->user_base == user_base) { + return curr->kernel_base; + } + curr = (fsl_shw_spo_t *) curr->next; + } + return NULL; +} + +#endif /* FSL_HAVE_SCC2 */ + +/*! +******************************************************************************* +* This function implements the smalloc() function for userspace programs, by +* making a call to the SCC2 mmap() function that acquires a region of secure +* memory on behalf of the user, and then maps it into the users memory space. +* Currently, the only memory size supported is that of a single SCC2 partition. +* Requests for other sized memory regions will fail. +*/ +OS_DEV_MMAP(shw_mmap) +{ + os_error_code status = OS_ERROR_NO_MEMORY_S; + +#ifdef FSL_HAVE_SCC2 + { + scc_return_t scc_ret; + fsl_shw_return_t fsl_ret; + uint32_t partition_registered = FALSE; + + uint32_t user_base; + void *partition_base; + uint32_t smid; + scc_config_t *scc_configuration; + + int part_no = -1; + uint32_t part_phys; + + fsl_shw_uco_t *user_ctx = + (fsl_shw_uco_t *) os_dev_get_user_private(); + + /* Make sure that the user context is valid */ + if (user_ctx == NULL) { + user_ctx = + os_alloc_memory(sizeof(*user_ctx), GFP_KERNEL); + + if (user_ctx == NULL) { + status = OS_ERROR_NO_MEMORY_S; + goto out; + } + fsl_shw_register_user(user_ctx); + os_dev_set_user_private(user_ctx); + } + + /* Determine the size of a secure partition */ + scc_configuration = scc_get_configuration(); + + /* Check that the memory size requested is equal to the partition + * size, and that the requested destination is on a page boundary. + */ + if (((os_mmap_user_base() % PAGE_SIZE) != 0) || + (os_mmap_memory_size() != + scc_configuration->partition_size_bytes)) { + status = OS_ERROR_BAD_ARG_S; + goto out; + } + + /* Retrieve the SMID associated with the user */ + smid = get_user_smid(user_ctx->process); + + /* Attempt to allocate a secure partition */ + scc_ret = + scc_allocate_partition(smid, &part_no, &partition_base, + &part_phys); + if (scc_ret != SCC_RET_OK) { + pr_debug + ("SCC mmap() request failed to allocate partition;" + " error %d\n", status); + status = OS_ERROR_FAIL_S; + goto out; + } + + pr_debug("scc_mmap() acquired partition %d at %08x\n", + part_no, part_phys); + + /* Record partition info in the user context */ + user_base = os_mmap_user_base(); + fsl_ret = + register_user_partition(user_ctx, user_base, + partition_base); + + if (fsl_ret != FSL_RETURN_OK_S) { + pr_debug + ("SCC mmap() request failed to register partition with user" + " context, error: %d\n", fsl_ret); + status = OS_ERROR_FAIL_S; + } + + partition_registered = TRUE; + + status = map_user_memory(os_mmap_memory_ctx(), part_phys, + os_mmap_memory_size()); + +#ifdef SHW_DEBUG + if (status == OS_ERROR_OK_S) { + LOG_KDIAG_ARGS + ("Partition allocated: user_base=%p, partition_base=%p.", + (void *)user_base, partition_base); + } +#endif + + out: + /* If there is an error it has to be handled here */ + if (status != OS_ERROR_OK_S) { + /* if the partition was registered with the user, unregister it. */ + if (partition_registered == TRUE) { + deregister_user_partition(user_ctx, user_base); + } + + /* if the partition was allocated, deallocate it */ + if (partition_base != NULL) { + scc_release_partition(partition_base); + } + } + } +#endif /* FSL_HAVE_SCC2 */ + + return status; +} + +/*****************************************************************************/ +/* fn shw_release() */ +/*****************************************************************************/ +/*! + * Handle @c close() call from user. + * This is a Linux device driver interface routine. + * + * @return OS_ERROR_OK_S on success (always!) + */ +OS_DEV_CLOSE(shw_release) +{ + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + os_error_code code = OS_ERROR_OK_S; + + if (user_ctx != NULL) { + + fsl_shw_deregister_user(user_ctx); + os_free_memory(user_ctx); + os_dev_set_user_private(NULL); + + } + + os_dev_close_return(code); +} /* shw_release */ + +/*****************************************************************************/ +/* fn shw_user_callback() */ +/*****************************************************************************/ +/*! + * FSL SHW User callback function. + * + * This function is set in the kernel version of the user context as the + * callback function when the user mode user wants a callback. Its job is to + * inform the user process that results (may) be available. It does this by + * sending a SIGUSR2 signal which is then caught by the user-mode FSL SHW + * library. + * + * @param user_ctx Kernel version of uco associated with the request. + * + * @return void + */ +static void shw_user_callback(fsl_shw_uco_t * user_ctx) +{ +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHW: Signalling callback user process for context %p\n", + user_ctx); +#endif + os_send_signal(user_ctx->process, SIGUSR2); +} + +/*****************************************************************************/ +/* fn setup_user_driver_interaction() */ +/*****************************************************************************/ +/*! + * Register the driver with the kernel as the driver for shw_major_node. Note + * that this value may be zero, in which case the major number will be assigned + * by the OS. shw_major_node is never modified. + * + * The open(), ioctl(), and close() handles for the driver ned to be registered + * with the kernel. Upon success, shw_device_registered will be true; + * + * @return OS_ERROR_OK_S on success, or an os err code + */ +static os_error_code shw_setup_user_driver_interaction(void) +{ + os_error_code error_code; + + os_driver_init_registration(reg_handle); + os_driver_add_registration(reg_handle, OS_FN_OPEN, + OS_DEV_OPEN_REF(shw_open)); + os_driver_add_registration(reg_handle, OS_FN_IOCTL, + OS_DEV_IOCTL_REF(shw_ioctl)); + os_driver_add_registration(reg_handle, OS_FN_CLOSE, + OS_DEV_CLOSE_REF(shw_release)); + os_driver_add_registration(reg_handle, OS_FN_MMAP, + OS_DEV_MMAP_REF(shw_mmap)); + error_code = os_driver_complete_registration(reg_handle, shw_major_node, + SHW_DRIVER_NAME); + + if (error_code != OS_ERROR_OK_S) { + /* failure ! */ +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHW Driver: register device driver failed: %d", + error_code); +#endif + } else { /* success */ + shw_device_registered = TRUE; +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHW Driver: Major node is %d\n", + os_driver_get_major(reg_handle)); +#endif + } + + return error_code; +} /* shw_setup_user_driver_interaction */ + +/******************************************************************/ +/* User Mode Support */ +/******************************************************************/ + +/*! + * Initialze kernel User Context Object from User-space version. + * + * Copy user UCO into kernel UCO, set flags and fields for operation + * within kernel space. Add user to driver's list of users. + * + * @param user_ctx Pointer to kernel space UCO + * @param user_mode_uco User pointer to user space version + * + * @return os_error_code + */ +static os_error_code init_uco(fsl_shw_uco_t * user_ctx, void *user_mode_uco) +{ + os_error_code code; + + code = os_copy_from_user(user_ctx, user_mode_uco, sizeof(*user_ctx)); + if (code == OS_ERROR_OK_S) { + user_ctx->flags |= FSL_UCO_USERMODE_USER; + user_ctx->result_pool.head = NULL; + user_ctx->result_pool.tail = NULL; + user_ctx->process = os_get_process_handle(); + user_ctx->callback = shw_user_callback; + SHW_ADD_USER(user_ctx); + } +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHW: init uco returning %d (flags %x)", + code, user_ctx->flags); +#endif + + return code; +} + +/*! + * Copy array from kernel to user space. + * + * This routine will check bounds before trying to copy, and return failure + * on bounds violation or error during the copy. + * + * @param userloc Location in userloc to place data. If NULL, the function + * will do nothing (except return NULL). + * @param userend Address beyond allowed copy region at @c userloc. + * @param data_start Location of data to be copied + * @param element_size sizeof() an element + * @param element_count Number of elements of size element_size to copy. + * @return New value of userloc, or NULL if there was an error. + */ +inline static void *copy_array(void *userloc, void *userend, void *data_start, + unsigned element_size, unsigned element_count) +{ + unsigned byte_count = element_size * element_count; + + if ((userloc == NULL) || (userend == NULL) + || ((userloc + byte_count) >= userend) || + (copy_to_user(userloc, data_start, byte_count) != OS_ERROR_OK_S)) { + userloc = NULL; + } else { + userloc += byte_count; + } + + return userloc; +} + +/*! + * Send an FSL SHW API return code up into the user-space request structure. + * + * @param user_header User address of request block / request header + * @param result_code The FSL SHW API code to be placed at header.code + * + * @return an os_error_code + * + * NOTE: This function assumes that the shw_req_header is at the beginning of + * each request structure. + */ +inline static os_error_code copy_fsl_code(void *user_header, + fsl_shw_return_t result_code) +{ + return os_copy_to_user(user_header + + offsetof(struct shw_req_header, code), + &result_code, sizeof(result_code)); +} + +static os_error_code shw_handle_scc_drop_perms(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code status = OS_ERROR_NO_MEMORY_S; +#ifdef FSL_HAVE_SCC2 + scc_return_t scc_ret; + scc_partition_info_t partition_info; + void *kernel_base; + + status = + os_copy_from_user(&partition_info, (void *)info, + sizeof(partition_info)); + + if (status != OS_ERROR_OK_S) { + goto out; + } + + /* validate that the user owns this partition, and look up its handle */ + kernel_base = lookup_user_partition(user_ctx, partition_info.user_base); + + if (kernel_base == NULL) { + status = OS_ERROR_FAIL_S; +#ifdef SHW_DEBUG + LOG_KDIAG("_scc_drop_perms(): failed to find partition\n"); +#endif + goto out; + } + + /* call scc driver to perform the drop */ + scc_ret = scc_diminish_permissions(kernel_base, + partition_info.permissions); + if (scc_ret == SCC_RET_OK) { + status = OS_ERROR_OK_S; + } else { + status = OS_ERROR_FAIL_S; + } + + out: +#endif /* FSL_HAVE_SCC2 */ + return status; +} + +static os_error_code shw_handle_scc_sstatus(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code status = OS_ERROR_NO_MEMORY_S; +#ifdef FSL_HAVE_SCC2 + scc_partition_info_t partition_info; + void *kernel_base; + + status = os_copy_from_user(&partition_info, + (void *)info, sizeof(partition_info)); + + if (status != OS_ERROR_OK_S) { + goto out; + } + + /* validate that the user owns this partition, and look up its handle */ + kernel_base = lookup_user_partition(user_ctx, partition_info.user_base); + + if (kernel_base == NULL) { + status = OS_ERROR_FAIL_S; +#ifdef SHW_DEBUG + LOG_KDIAG("Failed to find partition\n"); +#endif + goto out; + } + + /* Call the SCC driver to ask about the partition status */ + partition_info.status = scc_partition_status(kernel_base); + + /* and copy the structure out */ + status = os_copy_to_user((void *)info, + &partition_info, sizeof(partition_info)); + + out: +#endif /* FSL_HAVE_SCC2 */ + return status; +} + +static os_error_code shw_handle_scc_sfree(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code status = OS_ERROR_NO_MEMORY_S; +#ifdef FSL_HAVE_SCC2 + { + scc_partition_info_t partition_info; + void *kernel_base; + int ret; + + status = os_copy_from_user(&partition_info, + (void *)info, + sizeof(partition_info)); + + /* check that the copy was successful */ + if (status != OS_ERROR_OK_S) { + goto out; + } + + /* validate that the user owns this partition, and look up its handle */ + kernel_base = + lookup_user_partition(user_ctx, partition_info.user_base); + + if (kernel_base == NULL) { + status = OS_ERROR_FAIL_S; +#ifdef SHW_DEBUG + LOG_KDIAG("failed to find partition\n"); +#endif /*SHW_DEBUG */ + goto out; + } + + /* Unmap the memory region (see sys_munmap in mmap.c) */ + ret = unmap_user_memory(partition_info.user_base, 8192); + + /* If the memory was successfully released */ + if (ret == OS_ERROR_OK_S) { + + /* release the partition */ + scc_release_partition(kernel_base); + + /* and remove it from the users context */ + deregister_user_partition(user_ctx, + partition_info.user_base); + + status = OS_ERROR_OK_S; + + } else { +#ifdef SHW_DEBUG + LOG_KDIAG("do_munmap not successful!"); +#endif + } + + } + out: +#endif /* FSL_HAVE_SCC2 */ + return status; +} + +static os_error_code shw_handle_scc_encrypt(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code status = OS_ERROR_FAIL_S; +#ifdef FSL_HAVE_SCC2 + { + fsl_shw_return_t retval; + scc_region_t region_info; + void *page_ctx = NULL; + void *black_addr = NULL; + void *partition_base = NULL; + scc_config_t *scc_configuration; + + status = + os_copy_from_user(®ion_info, (void *)info, + sizeof(region_info)); + + if (status != OS_ERROR_OK_S) { + goto out; + } + + /* validate that the user owns this partition, and look up its handle */ + partition_base = lookup_user_partition(user_ctx, + region_info. + partition_base); + + if (partition_base == NULL) { + status = OS_ERROR_FAIL_S; +#ifdef SHW_DEBUG + LOG_KDIAG("failed to find secure partition\n"); +#endif + goto out; + } + + /* Check that the memory size requested is correct */ + scc_configuration = scc_get_configuration(); + if (region_info.offset + region_info.length > + scc_configuration->partition_size_bytes) { + status = OS_ERROR_FAIL_S; + goto out; + } + + /* wire down black_data */ + black_addr = wire_user_memory(region_info.black_data, + region_info.length, &page_ctx); + + if (black_addr == NULL) { + status = OS_ERROR_FAIL_S; + goto out; + } + + retval = + do_scc_encrypt_region(NULL, partition_base, + region_info.offset, + region_info.length, black_addr, + region_info.IV, + region_info.cypher_mode); + + if (retval == FSL_RETURN_OK_S) { + status = OS_ERROR_OK_S; + } else { + status = OS_ERROR_FAIL_S; + } + + /* release black data */ + unwire_user_memory(&page_ctx); + } + out: + +#endif /* FSL_HAVE_SCC2 */ + return status; +} + +static os_error_code shw_handle_scc_decrypt(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code status = OS_ERROR_FAIL_S; +#ifdef FSL_HAVE_SCC2 + { + fsl_shw_return_t retval; + scc_region_t region_info; + void *page_ctx = NULL; + void *black_addr; + void *partition_base; + scc_config_t *scc_configuration; + + status = + os_copy_from_user(®ion_info, (void *)info, + sizeof(region_info)); + +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS + ("partition_base: %p, offset: %i, length: %i, black data: %p", + (void *)region_info.partition_base, region_info.offset, + region_info.length, (void *)region_info.black_data); +#endif + + if (status != OS_ERROR_OK_S) { + goto out; + } + + /* validate that the user owns this partition, and look up its handle */ + partition_base = lookup_user_partition(user_ctx, + region_info. + partition_base); + + if (partition_base == NULL) { + status = OS_ERROR_FAIL_S; +#ifdef SHW_DEBUG + LOG_KDIAG("failed to find partition\n"); +#endif + goto out; + } + + /* Check that the memory size requested is correct */ + scc_configuration = scc_get_configuration(); + if (region_info.offset + region_info.length > + scc_configuration->partition_size_bytes) { + status = OS_ERROR_FAIL_S; + goto out; + } + + /* wire down black_data */ + black_addr = wire_user_memory(region_info.black_data, + region_info.length, &page_ctx); + + if (black_addr == NULL) { + status = OS_ERROR_FAIL_S; + goto out; + } + + retval = + do_scc_decrypt_region(NULL, partition_base, + region_info.offset, + region_info.length, black_addr, + region_info.IV, + region_info.cypher_mode); + + if (retval == FSL_RETURN_OK_S) { + status = OS_ERROR_OK_S; + } else { + status = OS_ERROR_FAIL_S; + } + + /* release black data */ + unwire_user_memory(&page_ctx); + } + out: + +#endif /* FSL_HAVE_SCC2 */ + return status; +} + +fsl_shw_return_t do_system_keystore_slot_alloc(fsl_shw_uco_t * user_ctx, + uint32_t key_length, + uint64_t ownerid, + uint32_t * slot) +{ + (void)user_ctx; + return keystore_slot_alloc(&system_keystore, key_length, ownerid, slot); +} + +fsl_shw_return_t do_system_keystore_slot_dealloc(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot) +{ + (void)user_ctx; + return keystore_slot_dealloc(&system_keystore, ownerid, slot); +} + +fsl_shw_return_t do_system_keystore_slot_load(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + const uint8_t * key, + uint32_t key_length) +{ + (void)user_ctx; + return keystore_slot_load(&system_keystore, ownerid, slot, + (void *)key, key_length); +} + +fsl_shw_return_t do_system_keystore_slot_encrypt(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + uint8_t * black_data) +{ + (void)user_ctx; + return keystore_slot_encrypt(NULL, &system_keystore, ownerid, + slot, key_length, black_data); +} + +fsl_shw_return_t do_system_keystore_slot_decrypt(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + const uint8_t * black_data) +{ + (void)user_ctx; + return keystore_slot_decrypt(NULL, &system_keystore, ownerid, + slot, key_length, black_data); +} + +fsl_shw_return_t do_system_keystore_slot_read(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + uint8_t * key_data) +{ + (void)user_ctx; + + return keystore_slot_read(&system_keystore, ownerid, + slot, key_length, key_data); +} + +/*! + * Handle user-mode Get Capabilities request + * + * Right now, this function can only have a failure if the user has failed to + * provide a pointer to a location in user space with enough room to hold the + * fsl_shw_pco_t structure and any associated data. It will treat this failure + * as an ioctl failure and return an ioctl error code, instead of treating it + * as an API failure. + * + * @param user_ctx The kernel version of user's context + * @param user_mode_pco_request Pointer to user-space request + * + * @return an os_error_code + */ +static os_error_code get_capabilities(fsl_shw_uco_t * user_ctx, + void *user_mode_pco_request) +{ + os_error_code code; + struct capabilities_req req; + fsl_shw_pco_t local_cap; + + memcpy(&local_cap, &cap, sizeof(cap)); + /* Initialize pointers to out-of-struct arrays */ + local_cap.sym_algorithms = NULL; + local_cap.sym_modes = NULL; + local_cap.sym_modes = NULL; + + code = os_copy_from_user(&req, user_mode_pco_request, sizeof(req)); + if (code == OS_ERROR_OK_S) { + void *endcap; + void *user_bounds; +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHE: Received get_cap request: 0x%p/%u/0x%x", + req.capabilities, req.size, + sizeof(fsl_shw_pco_t)); +#endif + endcap = req.capabilities + 1; /* point to end of structure */ + user_bounds = (void *)req.capabilities + req.size; /* end of area */ + + /* First verify that request is big enough for the main structure */ + if (endcap >= user_bounds) { + endcap = NULL; /* No! */ + } + + /* Copy any Symmetric Algorithm suppport */ + if (cap.sym_algorithm_count != 0) { + local_cap.sym_algorithms = endcap; + endcap = + copy_array(endcap, user_bounds, cap.sym_algorithms, + sizeof(fsl_shw_key_alg_t), + cap.sym_algorithm_count); + } + + /* Copy any Symmetric Modes suppport */ + if (cap.sym_mode_count != 0) { + local_cap.sym_modes = endcap; + endcap = copy_array(endcap, user_bounds, cap.sym_modes, + sizeof(fsl_shw_sym_mode_t), + cap.sym_mode_count); + } + + /* Copy any Hash Algorithm suppport */ + if (cap.hash_algorithm_count != 0) { + local_cap.hash_algorithms = endcap; + endcap = + copy_array(endcap, user_bounds, cap.hash_algorithms, + sizeof(fsl_shw_hash_alg_t), + cap.hash_algorithm_count); + } + + /* Now copy up the (possibly modified) main structure */ + if (endcap != NULL) { + code = + os_copy_to_user(req.capabilities, &local_cap, + sizeof(cap)); + } + + if (endcap == NULL) { + code = OS_ERROR_BAD_ADDRESS_S; + } + + /* And return the FSL SHW code in the request structure. */ + if (code == OS_ERROR_OK_S) { + code = + copy_fsl_code(user_mode_pco_request, + FSL_RETURN_OK_S); + } + } + + /* code may already be set to an error. This is another error case. */ + +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHW: get capabilities returning %d", code); +#endif + + return code; +} + +/*! + * Handle user-mode Get Results request + * + * Get arguments from user space into kernel space, then call + * fsl_shw_get_results, and then copy its return code and any results from + * kernel space back to user space. + * + * @param user_ctx The kernel version of user's context + * @param user_mode_results_req Pointer to user-space request + * + * @return an os_error_code + */ +static os_error_code get_results(fsl_shw_uco_t * user_ctx, + void *user_mode_results_req) +{ + os_error_code code; + struct results_req req; + fsl_shw_result_t *results = NULL; + int loop; + + code = os_copy_from_user(&req, user_mode_results_req, sizeof(req)); + loop = 0; + + if (code == OS_ERROR_OK_S) { + results = os_alloc_memory(req.requested * sizeof(*results), 0); + if (results == NULL) { + code = OS_ERROR_NO_MEMORY_S; + } + } + + if (code == OS_ERROR_OK_S) { + fsl_shw_return_t err = + fsl_shw_get_results(user_ctx, req.requested, + results, &req.actual); + + /* Send API return code up to user. */ + code = copy_fsl_code(user_mode_results_req, err); + + if ((code == OS_ERROR_OK_S) && (err == FSL_RETURN_OK_S)) { + /* Now copy up the result count */ + code = os_copy_to_user(user_mode_results_req + + offsetof(struct results_req, + actual), &req.actual, + sizeof(req.actual)); + if ((code == OS_ERROR_OK_S) && (req.actual != 0)) { + /* now copy up the results... */ + code = os_copy_to_user(req.results, results, + req.actual * + sizeof(*results)); + } + } + } + + if (results != NULL) { + os_free_memory(results); + } + + return code; +} + +/*! + * Process header of user-mode request. + * + * Mark header as User Mode request. Update UCO's flags and reference fields + * with current versions from the header. + * + * @param user_ctx Pointer to kernel version of UCO. + * @param hdr Pointer to common part of user request. + * + * @return void + */ +inline static void process_hdr(fsl_shw_uco_t * user_ctx, + struct shw_req_header *hdr) +{ + hdr->flags |= FSL_UCO_USERMODE_USER; + user_ctx->flags = hdr->flags; + user_ctx->user_ref = hdr->user_ref; + + return; +} + +/*! + * Handle user-mode Get Random request + * + * @param user_ctx The kernel version of user's context + * @param user_mode_get_random_req Pointer to user-space request + * + * @return an os_error_code + */ +static os_error_code get_random(fsl_shw_uco_t * user_ctx, + void *user_mode_get_random_req) +{ + os_error_code code; + struct get_random_req req; + + code = os_copy_from_user(&req, user_mode_get_random_req, sizeof(req)); + if (code == OS_ERROR_OK_S) { + process_hdr(user_ctx, &req.hdr); +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS + ("SHW: get_random() for %d bytes in %sblocking mode", + req.size, + (req.hdr.flags & FSL_UCO_BLOCKING_MODE) ? "" : "non-"); +#endif + req.hdr.code = + fsl_shw_get_random(user_ctx, req.size, req.random); + +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHW: get_random() returning %d", req.hdr.code); +#endif + + /* Copy FSL function status back to user */ + code = copy_fsl_code(user_mode_get_random_req, req.hdr.code); + } + + return code; +} + +/*! + * Handle user-mode Add Entropy request + * + * @param user_ctx Pointer to the kernel version of user's context + * @param user_mode_add_entropy_req Address of user-space request + * + * @return an os_error_code + */ +static os_error_code add_entropy(fsl_shw_uco_t * user_ctx, + void *user_mode_add_entropy_req) +{ + os_error_code code; + struct add_entropy_req req; + uint8_t *local_buffer = NULL; + + code = os_copy_from_user(&req, user_mode_add_entropy_req, sizeof(req)); + if (code == OS_ERROR_OK_S) { + local_buffer = os_alloc_memory(req.size, 0); /* for random */ + if (local_buffer != NULL) { + code = + os_copy_from_user(local_buffer, req.entropy, + req.size); + } + if (code == OS_ERROR_OK_S) { + req.hdr.code = fsl_shw_add_entropy(user_ctx, req.size, + local_buffer); + + code = + copy_fsl_code(user_mode_add_entropy_req, + req.hdr.code); + } + } + + if (local_buffer != NULL) { + os_free_memory(local_buffer); + } + + return code; +} + +/******************************************************************/ +/* End User Mode Support */ +/******************************************************************/ + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_register_user); +#endif +/* REQ-S2LRD-PINTFC-API-GEN-004 */ +/* + * Handle user registration. + * + * @param user_ctx The user context for the registration. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_register_user(fsl_shw_uco_t * user_ctx) +{ + fsl_shw_return_t code = FSL_RETURN_INTERNAL_ERROR_S; + + if ((user_ctx->flags & FSL_UCO_BLOCKING_MODE) && + (user_ctx->flags & FSL_UCO_CALLBACK_MODE)) { + code = FSL_RETURN_BAD_FLAG_S; + goto error_exit; + } else if (user_ctx->pool_size == 0) { + code = FSL_RETURN_NO_RESOURCE_S; + goto error_exit; + } else { + user_ctx->result_pool.head = NULL; + user_ctx->result_pool.tail = NULL; + SHW_ADD_USER(user_ctx); + code = FSL_RETURN_OK_S; + } + + error_exit: + return code; +} + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_deregister_user); +#endif +/* REQ-S2LRD-PINTFC-API-GEN-005 */ +/*! + * Destroy the association between the the user and the provider of the API. + * + * @param user_ctx The user context which is no longer needed. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_deregister_user(fsl_shw_uco_t * user_ctx) +{ + shw_queue_entry_t *finished_request; + fsl_shw_return_t ret = FSL_RETURN_OK_S; + + /* Clean up what we find in result pool. */ + do { + os_lock_context_t lock_context; + os_lock_save_context(shw_queue_lock, lock_context); + finished_request = user_ctx->result_pool.head; + + if (finished_request != NULL) { + SHW_QUEUE_REMOVE_ENTRY(&user_ctx->result_pool, + finished_request); + os_unlock_restore_context(shw_queue_lock, lock_context); + os_free_memory(finished_request); + } else { + os_unlock_restore_context(shw_queue_lock, lock_context); + } + } while (finished_request != NULL); + +#ifdef FSL_HAVE_SCC2 + { + fsl_shw_spo_t *partition; + struct mm_struct *mm = current->mm; + + while ((user_ctx->partition != NULL) + && (ret == FSL_RETURN_OK_S)) { + + partition = user_ctx->partition; + +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS + ("Found an abandoned secure partition at %p, releasing", + partition); +#endif + + /* It appears that current->mm is not valid if this is called from a + * close routine (perhaps only if the program raised an exception that + * caused it to close?) If that is the case, then still free the + * partition, but do not remove it from the memory space (dangerous?) + */ + + if (mm == NULL) { +#ifdef SHW_DEBUG + LOG_KDIAG + ("Warning: no mm structure found, not unmapping " + "partition from user memory\n"); +#endif + } else { + /* Unmap the memory region (see sys_munmap in mmap.c) */ + /* Note that this assumes a single memory partition */ + unmap_user_memory(partition->user_base, 8192); + } + + /* If the memory was successfully released */ + if (ret == OS_ERROR_OK_S) { + /* release the partition */ + scc_release_partition(partition->kernel_base); + + /* and remove it from the users context */ + deregister_user_partition(user_ctx, + partition->user_base); + + ret = FSL_RETURN_OK_S; + } else { + ret = FSL_RETURN_ERROR_S; + + goto out; + } + } + } + out: +#endif /* FSL_HAVE_SCC2 */ + + SHW_REMOVE_USER(user_ctx); + + return ret; +} + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_get_results); +#endif +/* REQ-S2LRD-PINTFC-API-GEN-006 */ +fsl_shw_return_t fsl_shw_get_results(fsl_shw_uco_t * user_ctx, + unsigned result_size, + fsl_shw_result_t results[], + unsigned *result_count) +{ + shw_queue_entry_t *finished_request; + unsigned loop = 0; + + do { + os_lock_context_t lock_context; + + /* Protect state of user's result pool until we have retrieved and + * remove the first entry, or determined that the pool is empty. */ + os_lock_save_context(shw_queue_lock, lock_context); + finished_request = user_ctx->result_pool.head; + + if (finished_request != NULL) { + uint32_t code = 0; + + SHW_QUEUE_REMOVE_ENTRY(&user_ctx->result_pool, + finished_request); + os_unlock_restore_context(shw_queue_lock, lock_context); + + results[loop].user_ref = finished_request->user_ref; + results[loop].code = finished_request->code; + results[loop].detail1 = 0; + results[loop].detail2 = 0; + results[loop].user_req = + finished_request->user_mode_req; + if (finished_request->postprocess != NULL) { + code = + finished_request-> + postprocess(finished_request); + } + + results[loop].code = finished_request->code; + os_free_memory(finished_request); + if (code == 0) { + loop++; + } + } else { /* finished_request is NULL */ + /* pool is empty */ + os_unlock_restore_context(shw_queue_lock, lock_context); + } + + } while ((loop < result_size) && (finished_request != NULL)); + + *result_count = loop; + + return FSL_RETURN_OK_S; +} + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_get_capabilities); +#endif +fsl_shw_pco_t *fsl_shw_get_capabilities(fsl_shw_uco_t * user_ctx) +{ + + /* Unused */ + (void)user_ctx; + + return ∩ +} + +#if !(defined(FSL_HAVE_SAHARA) || defined(FSL_HAVE_RNGA) \ + || defined(FSL_HAVE_RNGB) || defined(FSL_HAVE_RNGC)) + +#if defined(LINUX_VERSION_CODE) +EXPORT_SYMBOL(fsl_shw_get_random); +#endif +fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data) +{ + + /* Unused */ + (void)user_ctx; + (void)length; + (void)data; + + return FSL_RETURN_ERROR_S; +} + +#if defined(LINUX_VERSION_CODE) +EXPORT_SYMBOL(fsl_shw_add_entropy); +#endif +fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data) +{ + + /* Unused */ + (void)user_ctx; + (void)length; + (void)data; + + return FSL_RETURN_ERROR_S; +} +#endif + +#if !defined(FSL_HAVE_DRYICE) && !defined(FSL_HAVE_SAHARA2) +#if 0 +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_symmetric_decrypt); +#endif +fsl_shw_return_t fsl_shw_symmetric_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * ct, uint8_t * pt) +{ + + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)sym_ctx; + (void)length; + (void)ct; + (void)pt; + + return FSL_RETURN_ERROR_S; +} + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_symmetric_encrypt); +#endif +fsl_shw_return_t fsl_shw_symmetric_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * pt, uint8_t * ct) +{ + + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)sym_ctx; + (void)length; + (void)pt; + (void)ct; + + return FSL_RETURN_ERROR_S; +} + +/* DryIce support provided in separate file */ + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_establish_key); +#endif +fsl_shw_return_t fsl_shw_establish_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_key_wrap_t establish_type, + const uint8_t * key) +{ + + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)establish_type; + (void)key; + + return FSL_RETURN_ERROR_S; +} + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_extract_key); +#endif +fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + uint8_t * covered_key) +{ + + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)covered_key; + + return FSL_RETURN_ERROR_S; +} + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_release_key); +#endif +fsl_shw_return_t fsl_shw_release_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info) +{ + + /* Unused */ + (void)user_ctx; + (void)key_info; + + return FSL_RETURN_ERROR_S; +} +#endif +#endif /* SAHARA or DRYICE */ + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_hash); +#endif +#if !defined(FSL_HAVE_SAHARA) +fsl_shw_return_t fsl_shw_hash(fsl_shw_uco_t * user_ctx, + fsl_shw_hco_t * hash_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + /* Unused */ + (void)user_ctx; + (void)hash_ctx; + (void)msg; + (void)length; + (void)result; + (void)result_len; + + return ret; +} +#endif + +#ifndef FSL_HAVE_SAHARA +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_hmac_precompute); +#endif + +fsl_shw_return_t fsl_shw_hmac_precompute(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx) +{ + fsl_shw_return_t status = FSL_RETURN_ERROR_S; + + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)hmac_ctx; + + return status; +} + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_hmac); +#endif + +fsl_shw_return_t fsl_shw_hmac(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len) +{ + fsl_shw_return_t status = FSL_RETURN_ERROR_S; + + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)hmac_ctx; + (void)msg; + (void)length; + (void)result; + (void)result_len; + + return status; +} +#endif + +/*! + * Call the proper function to encrypt a region of encrypted secure memory + * + * @brief + * + * @param user_ctx User context of the partition owner (NULL in kernel) + * @param partition_base Base address (physical) of the partition + * @param offset_bytes Offset from base address of the data to be encrypted + * @param byte_count Length of the message (bytes) + * @param black_data Pointer to where the encrypted data is stored + * @param IV IV to use for encryption + * @param cypher_mode Cyphering mode to use, specified by type + * #fsl_shw_cypher_mode_t + * + * @return status + */ +fsl_shw_return_t +do_scc_encrypt_region(fsl_shw_uco_t * user_ctx, + void *partition_base, uint32_t offset_bytes, + uint32_t byte_count, uint8_t * black_data, + uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode) +{ + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; +#ifdef FSL_HAVE_SCC2 + + scc_return_t scc_ret; + +#ifdef SHW_DEBUG + uint32_t *owner_32 = (uint32_t *) & (owner_id); + + LOG_KDIAG_ARGS + ("partition base: %p, offset: %i, count: %i, black data: %p\n", + partition_base, offset_bytes, byte_count, (void *)black_data); + + LOG_KDIAG_ARGS("Owner ID: %08x%08x\n", owner_32[1], owner_32[0]); +#endif /* SHW_DEBUG */ + (void)user_ctx; + + os_cache_flush_range(black_data, byte_count); + + scc_ret = + scc_encrypt_region((uint32_t) partition_base, offset_bytes, + byte_count, __virt_to_phys(black_data), IV, + cypher_mode); + + if (scc_ret == SCC_RET_OK) { + retval = FSL_RETURN_OK_S; + } else { + retval = FSL_RETURN_ERROR_S; + } + + /* The SCC2 DMA engine should have written to the black ram, so we need to + * invalidate that region of memory. Note that the red ram is not an + * because it is mapped with the cache disabled. + */ + os_cache_inv_range(black_data, byte_count); + +#endif /* FSL_HAVE_SCC2 */ + return retval; +} + +/*! + * Call the proper function to decrypt a region of encrypted secure memory + * + * @brief + * + * @param user_ctx User context of the partition owner (NULL in kernel) + * @param partition_base Base address (physical) of the partition + * @param offset_bytes Offset from base address that the decrypted data + * shall be placed + * @param byte_count Length of the message (bytes) + * @param black_data Pointer to where the encrypted data is stored + * @param IV IV to use for decryption + * @param cypher_mode Cyphering mode to use, specified by type + * #fsl_shw_cypher_mode_t + * + * @return status + */ +fsl_shw_return_t +do_scc_decrypt_region(fsl_shw_uco_t * user_ctx, + void *partition_base, uint32_t offset_bytes, + uint32_t byte_count, const uint8_t * black_data, + uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode) +{ + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + +#ifdef FSL_HAVE_SCC2 + + scc_return_t scc_ret; + +#ifdef SHW_DEBUG + uint32_t *owner_32 = (uint32_t *) & (owner_id); + + LOG_KDIAG_ARGS + ("partition base: %p, offset: %i, count: %i, black data: %p\n", + partition_base, offset_bytes, byte_count, (void *)black_data); + + LOG_KDIAG_ARGS("Owner ID: %08x%08x\n", owner_32[1], owner_32[0]); +#endif /* SHW_DEBUG */ + + (void)user_ctx; + + /* The SCC2 DMA engine will be reading from the black ram, so we need to + * make sure that the data is pushed out of the cache. Note that the red + * ram is not an issue because it is mapped with the cache disabled. + */ + os_cache_flush_range(black_data, byte_count); + + scc_ret = + scc_decrypt_region((uint32_t) partition_base, offset_bytes, + byte_count, + (uint8_t *) __virt_to_phys(black_data), IV, + cypher_mode); + + if (scc_ret == SCC_RET_OK) { + retval = FSL_RETURN_OK_S; + } else { + retval = FSL_RETURN_ERROR_S; + } + +#endif /* FSL_HAVE_SCC2 */ + + return retval; +} + +void *fsl_shw_smalloc(fsl_shw_uco_t * user_ctx, + uint32_t size, const uint8_t * UMID, uint32_t permissions) +{ +#ifdef FSL_HAVE_SCC2 + int part_no; + void *part_base; + uint32_t part_phys; + scc_config_t *scc_configuration; + + /* Check that the memory size requested is correct */ + scc_configuration = scc_get_configuration(); + if (size != scc_configuration->partition_size_bytes) { + return NULL; + } + + /* attempt to grab a partition. */ + if (scc_allocate_partition(0, &part_no, &part_base, &part_phys) + != SCC_RET_OK) { + return NULL; + } +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("Partition_base: %p, partition_base_phys: %p\n", + part_base, (void *)part_phys); +#endif + + if (scc_engage_partition(part_base, UMID, permissions) + != SCC_RET_OK) { + /* Engagement failed, so the partition needs to be de-allocated */ + +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("Failed to engage partition %p, de-allocating", + part_base); +#endif + scc_release_partition(part_base); + + return NULL; + } + + return part_base; + +#else /* FSL_HAVE_SCC2 */ + + (void)user_ctx; + (void)size; + (void)UMID; + (void)permissions; + return NULL; + +#endif /* FSL_HAVE_SCC2 */ +} + +/* Release a block of secure memory */ +fsl_shw_return_t fsl_shw_sfree(fsl_shw_uco_t * user_ctx, void *address) +{ + (void)user_ctx; + +#ifdef FSL_HAVE_SCC2 + if (scc_release_partition(address) == SCC_RET_OK) { + return FSL_RETURN_OK_S; + } +#endif + + return FSL_RETURN_ERROR_S; +} + +/* Check the status of a block of secure memory */ +fsl_shw_return_t fsl_shw_sstatus(fsl_shw_uco_t * user_ctx, + void *address, + fsl_shw_partition_status_t * part_status) +{ + (void)user_ctx; + +#ifdef FSL_HAVE_SCC2 + *part_status = scc_partition_status(address); + + return FSL_RETURN_OK_S; +#endif + + return FSL_RETURN_ERROR_S; +} + +/* Diminish permissions on some secure memory */ +fsl_shw_return_t fsl_shw_diminish_perms(fsl_shw_uco_t * user_ctx, + void *address, uint32_t permissions) +{ + + (void)user_ctx; /* unused parameter warning */ + +#ifdef FSL_HAVE_SCC2 + if (scc_diminish_permissions(address, permissions) == SCC_RET_OK) { + return FSL_RETURN_OK_S; + } +#endif + return FSL_RETURN_ERROR_S; +} + +#ifndef FSL_HAVE_SAHARA +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_gen_encrypt); +#endif + +fsl_shw_return_t fsl_shw_gen_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + fsl_shw_sko_t * cipher_key_info, + fsl_shw_sko_t * auth_key_info, + uint32_t auth_data_length, + const uint8_t * auth_data, + uint32_t payload_length, + const uint8_t * payload, + uint8_t * ct, uint8_t * auth_value) +{ + volatile fsl_shw_return_t status = FSL_RETURN_ERROR_S; + + /* Unused */ + (void)user_ctx; + (void)auth_ctx; + (void)cipher_key_info; + (void)auth_key_info; /* save compilation warning */ + (void)auth_data_length; + (void)auth_data; + (void)payload_length; + (void)payload; + (void)ct; + (void)auth_value; + + return status; +} + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_auth_decrypt); +#endif +/*! + * @brief Authenticate and decrypt a (CCM) stream. + * + * @param user_ctx The user's context + * @param auth_ctx Info on this Auth operation + * @param cipher_key_info Key to encrypt payload + * @param auth_key_info (unused - same key in CCM) + * @param auth_data_length Length in bytes of @a auth_data + * @param auth_data Any auth-only data + * @param payload_length Length in bytes of @a payload + * @param ct The encrypted data + * @param auth_value The authentication code to validate + * @param[out] payload The location to store decrypted data + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_auth_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + fsl_shw_sko_t * cipher_key_info, + fsl_shw_sko_t * auth_key_info, + uint32_t auth_data_length, + const uint8_t * auth_data, + uint32_t payload_length, + const uint8_t * ct, + const uint8_t * auth_value, + uint8_t * payload) +{ + volatile fsl_shw_return_t status = FSL_RETURN_ERROR_S; + + /* Unused */ + (void)user_ctx; + (void)auth_ctx; + (void)cipher_key_info; + (void)auth_key_info; /* save compilation warning */ + (void)auth_data_length; + (void)auth_data; + (void)payload_length; + (void)ct; + (void)auth_value; + (void)payload; + + return status; +} + +#endif /* no SAHARA */ + +#ifndef FSL_HAVE_DRYICE + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_gen_random_pf_key); +#endif +/*! + * Cause the hardware to create a new random key for secure memory use. + * + * Have the hardware use the secure hardware random number generator to load a + * new secret key into the hardware random key register. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_gen_random_pf_key(fsl_shw_uco_t * user_ctx) +{ + volatile fsl_shw_return_t status = FSL_RETURN_ERROR_S; + + return status; +} + +#endif /* not have DRYICE */ + +fsl_shw_return_t alloc_slot(fsl_shw_uco_t * user_ctx, fsl_shw_sko_t * key_info) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_alloc(user_ctx, + key_info->key_length, + key_info->userid, + &(key_info->handle)); +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("key length: %i, handle: %i", + key_info->key_length, key_info->handle); +#endif + + } else { + /* Key goes in user keystore */ + ret = keystore_slot_alloc(key_info->keystore, + key_info->key_length, + key_info->userid, + &(key_info->handle)); + } + + return ret; +} /* end fn alloc_slot */ + +fsl_shw_return_t load_slot(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, const uint8_t * key) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_load(user_ctx, + key_info->userid, + key_info->handle, key, + key_info->key_length); + } else { + /* Key goes in user keystore */ + ret = keystore_slot_load(key_info->keystore, + key_info->userid, + key_info->handle, key, + key_info->key_length); + } + + return ret; +} /* end fn load_slot */ + +fsl_shw_return_t dealloc_slot(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + do_system_keystore_slot_dealloc(user_ctx, + key_info->userid, + key_info->handle); + } else { + /* Key goes in user keystore */ + keystore_slot_dealloc(key_info->keystore, + key_info->userid, key_info->handle); + } + + key_info->flags &= ~(FSL_SKO_KEY_ESTABLISHED | FSL_SKO_KEY_PRESENT); + + return ret; +} /* end fn slot_dealloc */ diff -urN linux-2.6.26/drivers/mxc/security/rng/shw_dryice.c linux-2.6.26-lab126/drivers/mxc/security/rng/shw_dryice.c --- linux-2.6.26/drivers/mxc/security/rng/shw_dryice.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/shw_dryice.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,204 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "shw_driver.h" +#include "../dryice.h" + +#include + +#ifdef FSL_HAVE_DRYICE + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_gen_random_pf_key); +#endif +/*! + * Cause the hardware to create a new random key for secure memory use. + * + * Have the hardware use the secure hardware random number generator to load a + * new secret key into the hardware random key register. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_gen_random_pf_key(fsl_shw_uco_t * user_ctx) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + di_return_t di_ret; + + /* For now, only blocking mode calls are supported */ + if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + di_ret = dryice_set_random_key(0); + if (di_ret != DI_SUCCESS) { + printk("dryice_set_random_key returned %d\n", di_ret); + goto out; + } + + ret = FSL_RETURN_OK_S; + + out: + return ret; +} + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_read_tamper_event); +#endif +fsl_shw_return_t fsl_shw_read_tamper_event(fsl_shw_uco_t * user_ctx, + fsl_shw_tamper_t * tamperp, + uint64_t * timestampp) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + di_return_t di_ret; + uint32_t di_events = 0; + uint32_t di_time_stamp; + + /* Only blocking mode calls are supported */ + if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + di_ret = dryice_get_tamper_event(&di_events, &di_time_stamp, 0); + if ((di_ret != DI_SUCCESS) && (di_ret != DI_ERR_STATE)) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("dryice_get_tamper_event returned %s\n", + di_error_string(di_ret)); +#endif + goto out; + } + + /* Pass time back to caller */ + *timestampp = (uint64_t) di_time_stamp; + + if (di_events & DI_TAMPER_EVENT_WTD) { + *tamperp = FSL_SHW_TAMPER_WTD; + } else if (di_events & DI_TAMPER_EVENT_ETBD) { + *tamperp = FSL_SHW_TAMPER_ETBD; + } else if (di_events & DI_TAMPER_EVENT_ETAD) { + *tamperp = FSL_SHW_TAMPER_ETAD; + } else if (di_events & DI_TAMPER_EVENT_EBD) { + *tamperp = FSL_SHW_TAMPER_EBD; + } else if (di_events & DI_TAMPER_EVENT_SAD) { + *tamperp = FSL_SHW_TAMPER_SAD; + } else if (di_events & DI_TAMPER_EVENT_TTD) { + *tamperp = FSL_SHW_TAMPER_TTD; + } else if (di_events & DI_TAMPER_EVENT_CTD) { + *tamperp = FSL_SHW_TAMPER_CTD; + } else if (di_events & DI_TAMPER_EVENT_VTD) { + *tamperp = FSL_SHW_TAMPER_VTD; + } else if (di_events & DI_TAMPER_EVENT_MCO) { + *tamperp = FSL_SHW_TAMPER_MCO; + } else if (di_events & DI_TAMPER_EVENT_TCO) { + *tamperp = FSL_SHW_TAMPER_TCO; + } else if (di_events != 0) { + /* Apparentliy a tamper type not known to this driver was detected */ + goto out; + } else { + *tamperp = FSL_SHW_TAMPER_NONE; + } + + ret = FSL_RETURN_OK_S; + + out: + return ret; +} /* end fn fsl_shw_read_tamper_event */ +#endif +/*! + * Convert an SHW HW key reference into a DI driver key reference + * + * @param shw_pf_key An SHW HW key value + * @param di_keyp Location to store the equivalent DI driver key + * + * @return FSL_RETURN_OK_S, or error if key is unknown or cannot translate. + */ +fsl_shw_return_t shw_convert_pf_key(fsl_shw_pf_key_t shw_pf_key, + di_key_t * di_keyp) +{ + fsl_shw_return_t ret = FSL_RETURN_BAD_FLAG_S; + + switch (shw_pf_key) { + case FSL_SHW_PF_KEY_IIM: + *di_keyp = DI_KEY_FK; + break; + case FSL_SHW_PF_KEY_RND: + *di_keyp = DI_KEY_RK; + break; + case FSL_SHW_PF_KEY_IIM_RND: + *di_keyp = DI_KEY_FRK; + break; + case FSL_SHW_PF_KEY_PRG: + *di_keyp = DI_KEY_PK; + break; + case FSL_SHW_PF_KEY_IIM_PRG: + *di_keyp = DI_KEY_FPK; + break; + default: + goto out; + } + + ret = FSL_RETURN_OK_S; + + out: + return ret; +} + +#ifdef DIAG_SECURITY_FUNC +const char *di_error_string(int code) +{ + char *str = "unknown"; + + switch (code) { + case DI_SUCCESS: + str = "operation was successful"; + break; + case DI_ERR_BUSY: + str = "device or resource busy"; + break; + case DI_ERR_STATE: + str = "dryice is in incompatible state"; + break; + case DI_ERR_INUSE: + str = "resource is already in use"; + break; + case DI_ERR_UNSET: + str = "resource has not been initialized"; + break; + case DI_ERR_WRITE: + str = "error occurred during register write"; + break; + case DI_ERR_INVAL: + str = "invalid argument"; + break; + case DI_ERR_FAIL: + str = "operation failed"; + break; + case DI_ERR_HLOCK: + str = "resource is hard locked"; + break; + case DI_ERR_SLOCK: + str = "resource is soft locked"; + break; + case DI_ERR_NOMEM: + str = "out of memory"; + break; + default: + break; + } + + return str; +} +#endif /* HAVE DRYICE */ diff -urN linux-2.6.26/drivers/mxc/security/rng/shw_hash.c linux-2.6.26-lab126/drivers/mxc/security/rng/shw_hash.c --- linux-2.6.26/drivers/mxc/security/rng/shw_hash.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/shw_hash.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,328 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file shw_hash.c + * + * This file contains implementations for use of the (internal) SHW hash + * software computation. It defines the usual three steps: + * + * - #shw_hash_init() + * - #shw_hash_update() + * - #shw_hash_final() + * + * In support of the above functions, it also contains these functions: + * - #sha256_init() + * - #sha256_process_block() + * + * + * These functions depend upon the Linux Endian functions __be32_to_cpu(), + * __cpu_to_be32() to convert a 4-byte big-endian array to an integer and + * vice-versa. For those without Linux, it should be pretty obvious what they + * do. + * + * The #shw_hash_update() and #shw_hash_final() functions are generic enough to + * support SHA-1/SHA-224/SHA-256, as needed. Some extra tweaking would be + * necessary to get them to support SHA-384/SHA-512. + * + */ + +#include "shw_driver.h" +#include "shw_hash.h" + +#ifndef __KERNEL__ +#include +#include /* or whichever is proper for target arch */ +#define printk printf +#endif + +/*! + * Rotate a value right by a number of bits. + * + * @param x Word of data which needs rotating + * @param y Number of bits to rotate + * + * @return The new value + */ +inline uint32_t rotr32fixed(uint32_t x, unsigned int y) +{ + return (uint32_t) ((x >> y) | (x << (32 - y))); +} + +#define blk0(i) (W[i] = data[i]) +// Referencing parameters so many times is really poor practice. Do not imitate these macros +#define blk2(i) (W[i & 15] += s1(W[(i - 2) & 15]) + W[(i - 7) & 15] + s0(W[(i - 15) & 15])) + +#define Ch(x,y,z) (z ^ (x & (y ^ z))) +#define Maj(x,y,z) ((x & y) | (z & (x | y))) + +#define a(i) T[(0 - i) & 7] +#define b(i) T[(1 - i) & 7] +#define c(i) T[(2 - i) & 7] +#define d(i) T[(3 - i) & 7] +#define e(i) T[(4 - i) & 7] +#define f(i) T[(5 - i) & 7] +#define g(i) T[(6 - i) & 7] +#define h(i) T[(7 - i) & 7] + +// This is a bad way to write a multi-statement macro... and referencing 'i' so many +// times is really poor practice. Do not imitate. +#define R(i) h(i) += S1( e(i)) + Ch(e(i), f(i), g(i)) + K[i + j] +(j ? blk2(i) : blk0(i));\ + d(i) += h(i);h(i) += S0(a(i)) + Maj(a(i), b(i), c(i)) + +// for SHA256 +#define S0(x) (rotr32fixed(x, 2) ^ rotr32fixed(x, 13) ^ rotr32fixed(x, 22)) +#define S1(x) (rotr32fixed(x, 6) ^ rotr32fixed(x, 11) ^ rotr32fixed(x, 25)) +#define s0(x) (rotr32fixed(x, 7) ^ rotr32fixed(x, 18) ^ (x >> 3)) +#define s1(x) (rotr32fixed(x, 17) ^ rotr32fixed(x, 19) ^ (x >> 10)) + +/*! + * Initialize the Hash State + * + * Constructs the SHA256 hash engine. + * Specification: + * State Size = 32 bytes + * Block Size = 64 bytes + * Digest Size = 32 bytes + * + * @param state Address of hash state structure + * + */ +void sha256_init(shw_hash_state_t * state) +{ + state->bit_count = 0; + state->partial_count_bytes = 0; + + state->state[0] = 0x6a09e667; + state->state[1] = 0xbb67ae85; + state->state[2] = 0x3c6ef372; + state->state[3] = 0xa54ff53a; + state->state[4] = 0x510e527f; + state->state[5] = 0x9b05688c; + state->state[6] = 0x1f83d9ab; + state->state[7] = 0x5be0cd19; +} + +const uint32_t K[64] = { + 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, + 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5, + 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3, + 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174, + 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc, + 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da, + 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7, + 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967, + 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13, + 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85, + 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3, + 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070, + 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, + 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3, + 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208, + 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2 +}; + +/*! + * Hash a block of data into the SHA-256 hash state. + * + * This function hash the block of data in the @c partial_block + * element of the state structure into the state variables of the + * state structure. + * + * @param state Address of hash state structure + * + */ +static void sha256_process_block(shw_hash_state_t * state) +{ + uint32_t W[16]; + uint32_t T[8]; + uint32_t stack_buffer[SHW_HASH_BLOCK_WORD_SIZE]; + uint32_t *data = &stack_buffer[0]; + uint8_t *input = state->partial_block; + unsigned int i; + unsigned int j; + + /* Copy byte-oriented input block into word-oriented registers */ + for (i = 0; i < SHW_HASH_BLOCK_LEN / sizeof(uint32_t); + i++, input += sizeof(uint32_t)) { + stack_buffer[i] = __be32_to_cpu(*(uint32_t *) input); + } + + /* Copy context->state[] to working vars */ + memcpy(T, state->state, sizeof(T)); + + /* 64 operations, partially loop unrolled */ + for (j = 0; j < SHW_HASH_BLOCK_LEN; j += 16) { + R(0); + R(1); + R(2); + R(3); + R(4); + R(5); + R(6); + R(7); + R(8); + R(9); + R(10); + R(11); + R(12); + R(13); + R(14); + R(15); + } + /* Add the working vars back into context.state[] */ + state->state[0] += a(0); + state->state[1] += b(0); + state->state[2] += c(0); + state->state[3] += d(0); + state->state[4] += e(0); + state->state[5] += f(0); + state->state[6] += g(0); + state->state[7] += h(0); + + /* Wipe variables */ + memset(W, 0, sizeof(W)); + memset(T, 0, sizeof(T)); +} + +/*! + * Initialize the hash state structure + * + * @param state Address of hash state structure. + * @param alg Which hash algorithm to use (must be FSL_HASH_ALG_SHA1) + * + * @return FSL_RETURN_OK_S if all went well, otherwise an error code. + */ +fsl_shw_return_t shw_hash_init(shw_hash_state_t * state, fsl_shw_hash_alg_t alg) +{ + if (alg != FSL_HASH_ALG_SHA256) { + return FSL_RETURN_BAD_ALGORITHM_S; + } + + sha256_init(state); + + return FSL_RETURN_OK_S; +} + +/*! + * Add input bytes to the hash + * + * The bytes are added to the partial_block element of the hash state, and as + * the partial block is filled, it is processed by sha1_process_block(). This + * function also updates the bit_count element of the hash state. + * + * @param state Address of hash state structure + * @param input Address of bytes to add to the hash + * @param input_len Numbef of bytes at @c input + * + */ +fsl_shw_return_t shw_hash_update(shw_hash_state_t * state, + const uint8_t * input, unsigned int input_len) +{ + unsigned int bytes_needed; /* Needed to fill a block */ + unsigned int bytes_to_copy; /* to copy into the block */ + + /* Account for new data */ + state->bit_count += 8 * input_len; + + /* + * Process input bytes into the ongoing block; process the block when it + * gets full. + */ + while (input_len > 0) { + bytes_needed = SHW_HASH_BLOCK_LEN - state->partial_count_bytes; + bytes_to_copy = ((input_len < bytes_needed) ? + input_len : bytes_needed); + + /* Add in the bytes and do the accounting */ + memcpy(state->partial_block + state->partial_count_bytes, + input, bytes_to_copy); + input += bytes_to_copy; + input_len -= bytes_to_copy; + state->partial_count_bytes += bytes_to_copy; + + /* Run a full block through the transform */ + if (state->partial_count_bytes == SHW_HASH_BLOCK_LEN) { + sha256_process_block(state); + state->partial_count_bytes = 0; + } + } + + return FSL_RETURN_OK_S; +} /* end fn shw_hash_update */ + +/*! + * Finalize the hash + * + * Performs the finalize operation on the previous input data & returns the + * resulting digest. The finalize operation performs the appropriate padding + * up to the block size. + * + * @param state Address of hash state structure + * @param result Location to store the hash result + * @param result_len Number of bytes of @c result to be stored. + * + * @return FSL_RETURN_OK_S if all went well, FSL_RETURN_BAD_DATA_LENGTH_S if + * hash_len is too long, otherwise an error code. + */ +fsl_shw_return_t shw_hash_final(shw_hash_state_t * state, uint8_t * result, + unsigned int result_len) +{ + static const uint8_t pad[SHW_HASH_BLOCK_LEN * 2] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + }; + + uint8_t data[sizeof(state->bit_count)]; + uint32_t pad_length; + uint64_t bit_count = state->bit_count; + uint8_t hash[SHW_HASH_LEN]; + int i; + + if (result_len > SHW_HASH_LEN) { + return FSL_RETURN_BAD_DATA_LENGTH_S; + } + + /* Save the length before padding. */ + for (i = sizeof(state->bit_count) - 1; i >= 0; i--) { + data[i] = bit_count & 0xFF; + bit_count >>= 8; + } + pad_length = ((state->partial_count_bytes < 56) ? + (56 - state->partial_count_bytes) : + (120 - state->partial_count_bytes)); + + /* Pad to 56 bytes mod 64 (BLOCK_SIZE). */ + shw_hash_update(state, pad, pad_length); + + /* + * Append the length. This should trigger transform of the final block. + */ + shw_hash_update(state, data, sizeof(state->bit_count)); + + /* Copy the result into a byte array */ + for (i = 0; i < SHW_HASH_STATE_WORDS; i++) { + *(uint32_t *) (hash + 4 * i) = __cpu_to_be32(state->state[i]); + } + + /* And copy the result out to caller */ + memcpy(result, hash, result_len); + + return FSL_RETURN_OK_S; +} /* end fn shw_hash_final */ diff -urN linux-2.6.26/drivers/mxc/security/rng/shw_hmac.c linux-2.6.26-lab126/drivers/mxc/security/rng/shw_hmac.c --- linux-2.6.26/drivers/mxc/security/rng/shw_hmac.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/shw_hmac.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,145 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file shw_hmac.c + * + * This file contains implementations for use of the (internal) SHW HMAC + * software computation. It defines the usual three steps: + * + * - #shw_hmac_init() + * - #shw_hmac_update() + * - #shw_hmac_final() + * + * + */ + +#include "shw_driver.h" +#include "shw_hmac.h" + +#ifndef __KERNEL__ +#include +#include /* or whichever is proper for target arch */ +#define printk printf +#endif + +/*! XOR value for HMAC inner key */ +#define INNER_HASH_CONSTANT 0x36 + +/*! XOR value for HMAC outer key */ +#define OUTER_HASH_CONSTANT 0x5C + +/*! + * Initialize the HMAC state structure with the HMAC key + * + * @param state Address of HMAC state structure + * @param key Address of the key to be used for the HMAC. + * @param key_len Number of bytes of @c key. + * + * Convert the key into its equivalent inner and outer hash state objects. + * + * @return FSL_RETURN_OK_S if all went well, otherwise an error code. + */ +fsl_shw_return_t shw_hmac_init(shw_hmac_state_t * state, + const uint8_t * key, unsigned int key_len) +{ + fsl_shw_return_t code = FSL_RETURN_ERROR_S; + uint8_t first_block[SHW_HASH_BLOCK_LEN]; + unsigned int i; + + /* Don't bother handling the pre-hash. */ + if (key_len > SHW_HASH_BLOCK_LEN) { + code = FSL_RETURN_BAD_KEY_LENGTH_S; + goto out; + } + + /* Prepare inner hash */ + for (i = 0; i < SHW_HASH_BLOCK_LEN; i++) { + if (i < key_len) { + first_block[i] = key[i] ^ INNER_HASH_CONSTANT; + } else { + first_block[i] = INNER_HASH_CONSTANT; + } + } + code = shw_hash_init(&state->inner_hash, FSL_HASH_ALG_SHA256); + if (code != FSL_RETURN_OK_S) { + goto out; + } + shw_hash_update(&state->inner_hash, first_block, SHW_HASH_BLOCK_LEN); + + /* Prepare outer hash */ + for (i = 0; i < SHW_HASH_BLOCK_LEN; i++) { + if (i < key_len) { + first_block[i] = key[i] ^ OUTER_HASH_CONSTANT; + } else { + first_block[i] = OUTER_HASH_CONSTANT; + } + } + code = shw_hash_init(&state->outer_hash, FSL_HASH_ALG_SHA256); + if (code != FSL_RETURN_OK_S) { + goto out; + } + shw_hash_update(&state->outer_hash, first_block, SHW_HASH_BLOCK_LEN); + + /* Wipe evidence of key */ + memset(first_block, 0, SHW_HASH_BLOCK_LEN); + + out: + return code; +} + +/*! + * Put data into the HMAC calculation + * + * Send the msg data inner inner hash's update function. + * + * @param state Address of HMAC state structure. + * @param msg Address of the message data for the HMAC. + * @param msg_len Number of bytes of @c msg. + * + * @return FSL_RETURN_OK_S if all went well, otherwise an error code. + */ +fsl_shw_return_t shw_hmac_update(shw_hmac_state_t * state, + const uint8_t * msg, unsigned int msg_len) +{ + shw_hash_update(&state->inner_hash, msg, msg_len); + + return FSL_RETURN_OK_S; +} + +/*! + * Calculate the final HMAC + * + * @param state Address of HMAC state structure. + * @param hmac Address of location to store the HMAC. + * @param hmac_len Number of bytes of @c mac to be stored. Probably best if + * this value is no greater than #SHW_HASH_LEN. + * + * This function finalizes the internal hash, and uses that result as + * data for the outer hash. As many bytes of that result are passed + * to the user as desired. + * + * @return FSL_RETURN_OK_S if all went well, otherwise an error code. + */ +fsl_shw_return_t shw_hmac_final(shw_hmac_state_t * state, + uint8_t * hmac, unsigned int hmac_len) +{ + uint8_t hash_result[SHW_HASH_LEN]; + + shw_hash_final(&state->inner_hash, hash_result, sizeof(hash_result)); + shw_hash_update(&state->outer_hash, hash_result, SHW_HASH_LEN); + + shw_hash_final(&state->outer_hash, hmac, hmac_len); + + return FSL_RETURN_OK_S; +} diff -urN linux-2.6.26/drivers/mxc/security/rng/shw_memory_mapper.c linux-2.6.26-lab126/drivers/mxc/security/rng/shw_memory_mapper.c --- linux-2.6.26/drivers/mxc/security/rng/shw_memory_mapper.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/rng/shw_memory_mapper.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,213 @@ +/* + * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + + +/** + * Memory management functions, from Sahara Crypto API + * + * This is a subset of the memory management functions from the Sahara Crypto + * API, and is intended to support user secure partitions. + */ + +#include "portable_os.h" +#include "fsl_shw.h" + +#include +#include +#include + +#ifdef SHW_DEBUG +#include +#endif + +/* Page context structure. Used by wire_user_memory and unwire_user_memory */ +typedef struct page_ctx_t { + uint32_t count; + struct page **local_pages; +} page_ctx_t; + +/** +******************************************************************************* +* Map and wire down a region of user memory. +* +* +* @param address Userspace address of the memory to wire +* @param length Length of the memory region to wire +* @param page_ctx Page context, to be passed to unwire_user_memory +* +* @return (if successful) Kernel virtual address of the wired pages +*/ +void* wire_user_memory(void* address, uint32_t length, void **page_ctx) +{ + void* kernel_black_addr = NULL; + int result = -1; + int page_index = 0; + page_ctx_t *page_context; + int nr_pages = 0; + unsigned long start_page; + fsl_shw_return_t status; + + /* Determine the number of pages being used for this link */ + nr_pages = (((unsigned long)(address) & ~PAGE_MASK) + + length + ~PAGE_MASK) >> PAGE_SHIFT; + + start_page = (unsigned long)(address) & PAGE_MASK; + + /* Allocate some memory to keep track of the wired user pages, so that + * they can be deallocated later. The block of memory will contain both + * the structure and the array of pages. + */ + page_context = kmalloc(sizeof(page_ctx_t) + + nr_pages * sizeof(struct page *), GFP_KERNEL); + + if (page_context == NULL) { + status = FSL_RETURN_NO_RESOURCE_S; /* no memory! */ +#ifdef DIAG_DRV_IF + LOG_KDIAG("kmalloc() failed."); +#endif + return NULL; + } + + /* Set the page pointer to point to the allocated region of memory */ + page_context->local_pages = (void*)page_context + sizeof(page_ctx_t); + +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS("page_context at: %p, local_pages at: %p", + (void *)page_context, + (void *)(page_context->local_pages)); +#endif + + /* Wire down the pages from user space */ + down_read(¤t->mm->mmap_sem); + result = get_user_pages(current, current->mm, + start_page, nr_pages, + WRITE, 0 /* noforce */, + (page_context->local_pages), NULL); + up_read(¤t->mm->mmap_sem); + + if (result < nr_pages) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("get_user_pages() failed."); +#endif + if (result > 0) { + for (page_index = 0; page_index < result; page_index++) + page_cache_release((page_context->local_pages[page_index])); + + kfree(page_context); + } + return NULL; + } + + kernel_black_addr = page_address(page_context->local_pages[0]) + + ((unsigned long)address & ~PAGE_MASK); + + page_context->count = nr_pages; + *page_ctx = page_context; + + return kernel_black_addr; +} + + +/** +******************************************************************************* +* Release and unmap a region of user memory. +* +* @param page_ctx Page context from wire_user_memory +*/ +void unwire_user_memory(void** page_ctx) +{ + int page_index = 0; + struct page_ctx_t *page_context = *page_ctx; + +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS("page_context at: %p, first page at:%p, count: %i", + (void *)page_context, + (void *)(page_context->local_pages), + page_context->count); +#endif + + if ((page_context != NULL) && (page_context->local_pages != NULL)) { + for (page_index = 0; page_index < page_context->count; page_index++) + page_cache_release(page_context->local_pages[page_index]); + + kfree(page_context); + *page_ctx = NULL; + } +} + + +/** +******************************************************************************* +* Map some physical memory into a users memory space +* +* @param vma Memory structure to map to +* @param physical_addr Physical address of the memory to be mapped in +* @param size Size of the memory to map (bytes) +* +* @return +*/ +os_error_code +map_user_memory(struct vm_area_struct *vma, uint32_t physical_addr, uint32_t size) +{ + os_error_code retval; + + /* Map the acquired partition into the user's memory space */ + vma->vm_end = vma->vm_start + size; + + /* set cache policy to uncached so that each write of the UMID and + * permissions get directly to the SCC2 in order to engage it + * properly. Once the permissions have been written, it may be + * useful to provide a service for the user to request a different + * cache policy + */ + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + /* Make sure that the user cannot fork() a child which will inherit + * this mapping, as it creates a security hole. Likewise, do not + * allow the user to 'expand' his mapping beyond this partition. + */ + vma->vm_flags |= VM_IO | VM_RESERVED | VM_DONTCOPY | VM_DONTEXPAND; + + retval = remap_pfn_range(vma, + vma->vm_start, + __phys_to_pfn(physical_addr), + size, + vma->vm_page_prot); + + return retval; +} + + +/** +******************************************************************************* +* Remove some memory from a user's memory space +* +* @param user_addr Userspace address of the memory to be unmapped +* @param size Size of the memory to map (bytes) +* +* @return +*/ +os_error_code +unmap_user_memory(uint32_t user_addr, uint32_t size) +{ + os_error_code retval; + struct mm_struct *mm = current->mm; + + /* Unmap the memory region (see sys_munmap in mmap.c) */ + down_write(&mm->mmap_sem); + retval = do_munmap(mm, (unsigned long)user_addr, size); + up_write(&mm->mmap_sem); + + return retval; +} diff -urN linux-2.6.26/drivers/mxc/security/sahara2/Kconfig linux-2.6.26-lab126/drivers/mxc/security/sahara2/Kconfig --- linux-2.6.26/drivers/mxc/security/sahara2/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/Kconfig 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,35 @@ +menu "SAHARA2 Security Hardware Support" + +config MXC_SAHARA + tristate "Security Hardware Support (FSL SHW)" + ---help--- + Provides driver and kernel mode API for using cryptographic + accelerators. + +config MXC_SAHARA_USER_MODE + tristate "User Mode API for FSL SHW" + depends on MXC_SAHARA + ---help--- + Provides kernel driver for User Mode API. + +config MXC_SAHARA_POLL_MODE + bool "Force driver to POLL for hardware completion." + depends on MXC_SAHARA + default n + ---help--- + When this flag is yes, the driver will not use interrupts to + determine when the hardware has completed a task, but instead + will hold onto the CPU and continually poll the hardware until + it completes. + +config MXC_SAHARA_POLL_MODE_TIMEOUT + hex "Poll loop timeout" + depends on MXC_SAHARA_POLL_MODE + default "0xFFFFFFFF" + help + To avoid infinite polling, a timeout is provided. Should the + timeout be reached, a fault is reported, indicating there must + be something wrong with SAHARA, and SAHARA is reset. The loop + will exit after the given number of iterations. + +endmenu diff -urN linux-2.6.26/drivers/mxc/security/sahara2/Makefile linux-2.6.26-lab126/drivers/mxc/security/sahara2/Makefile --- linux-2.6.26/drivers/mxc/security/sahara2/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/Makefile 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,47 @@ +# Makefile for the Linux Sahara2 driver +# +# This makefile works within a kernel driver tree + +# Need to augment this to support optionally building user-mode support +API_SOURCES = fsl_shw_sym.c fsl_shw_user.c fsl_shw_hash.c fsl_shw_auth.c \ + fsl_shw_hmac.c fsl_shw_rand.c sf_util.c km_adaptor.c fsl_shw_keystore.c \ + fsl_shw_wrap.c \ + + +SOURCES = sah_driver_interface.c sah_hardware_interface.c \ + sah_interrupt_handler.c sah_queue.c sah_queue_manager.c \ + sah_status_manager.c sah_memory_mapper.c + + +# Turn on for mostly full debugging +# DIAGS = -DDIAG_DRV_STATUS -DDIAG_DRV_QUEUE -DDIAG_DRV_INTERRUPT -DDIAG_DRV_IF +# DIAGS += -DDIAG_DURING_INTERRUPT + +# Turn on for lint-type checking +#EXTRA_CFLAGS = -Wall -W -Wstrict-prototypes -Wmissing-prototypes +EXTRA_CFLAGS += -DLINUX_KERNEL $(DIAGS) + + +ifeq ($(CONFIG_MXC_SAHARA_POLL_MODE),y) +EXTRA_CFLAGS += -DSAHARA_POLL_MODE +EXTRA_CFLAGS += -DSAHARA_POLL_MODE_TIMEOUT=$(CONFIG_SAHARA_POLL_MODE_TIMEOUT) +endif + +ifeq ($(CONFIG_MXC_SAHARA_USER_MODE),y) +EXTRA_CFLAGS += -DSAHARA_USER_MODE +SOURCES += +endif + +ifeq ($(CONFIG_PM),y) +EXTRA_CFLAGS += -DSAHARA_POWER_MANAGMENT +endif + +EXTRA_CFLAGS += -Idrivers/mxc/security/sahara2/include + +# handle buggy BSP -- uncomment if these are undefined during build +#EXTRA_CFLAGS += -DSAHARA_BASE_ADDR=HAC_BASE_ADDR -DINT_SAHARA=INT_HAC_RTIC + + +obj-$(CONFIG_MXC_SAHARA) += sahara.o + +sahara-objs := $(SOURCES:.c=.o) $(API_SOURCES:.c=.o) diff -urN linux-2.6.26/drivers/mxc/security/sahara2/fsl_shw_auth.c linux-2.6.26-lab126/drivers/mxc/security/sahara2/fsl_shw_auth.c --- linux-2.6.26/drivers/mxc/security/sahara2/fsl_shw_auth.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/fsl_shw_auth.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,706 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @file fsl_shw_auth.c + * + * This file contains the routines which do the combined encrypt+authentication + * functions. For now, only AES-CCM is supported. + */ + +#include "sahara.h" +#include "adaptor.h" +#include "sf_util.h" + +#ifdef __KERNEL__ +EXPORT_SYMBOL(fsl_shw_gen_encrypt); +EXPORT_SYMBOL(fsl_shw_auth_decrypt); +#endif + + +/*! Size of buffer to repetively sink useless CBC output */ +#define CBC_BUF_LEN 4096 + +/*! + * Compute the size, in bytes, of the encoded auth length + * + * @param l The actual associated data length + * + * @return The encoded length + */ +#define COMPUTE_NIST_AUTH_LEN_SIZE(l) \ +({ \ + unsigned val; \ + uint32_t len = l; \ + if (len == 0) { \ + val = 0; \ + } else if (len < 65280) { \ + val = 2; \ + } else { /* cannot handle >= 2^32 */ \ + val = 6; \ + } \ + val; \ +}) + +/*! + * Store the encoded Auth Length into the Auth Data + * + * @param l The actual Auth Length + * @param p Location to store encoding (must be uint8_t*) + * + * @return void + */ +#define STORE_NIST_AUTH_LEN(l, p) \ +{ \ + register uint32_t L = l; \ + if ((uint32_t)(l) < 65280) { \ + (p)[1] = L & 0xff; \ + L >>= 8; \ + (p)[0] = L & 0xff; \ + } else { /* cannot handle >= 2^32 */ \ + int i; \ + for (i = 5; i > 1; i--) { \ + (p)[i] = L & 0xff; \ + L >>= 8; \ + } \ + (p)[1] = 0xfe; /* Markers */ \ + (p)[0] = 0xff; \ + } \ +} + +#if defined (FSL_HAVE_SAHARA2) || defined (USE_S2_CCM_DECRYPT_CHAIN) \ + || defined (USE_S2_CCM_ENCRYPT_CHAIN) +/*! Buffer to repetively sink useless CBC output */ +static uint8_t cbc_buffer[CBC_BUF_LEN]; +#endif + +/*! + * Place to store useless output (while bumping CTR0 to CTR1, for instance. + * Must be maximum Symmetric block size + */ +static uint8_t garbage_output[16]; + +/*! + * Block of zeroes which is maximum Symmetric block size, used for + * initializing context register, etc. + */ +static uint8_t block_zeros[16] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/*! + * Append a descriptor chain which will compute CBC over the + * formatted associated data blocks. + * + * @param[in,out] link1 Where to append the new link + * @param[in,out] data_len Location of current/updated auth-only data length + * @param user_ctx Info for acquiring memory + * @param auth_ctx Location of block0 value + * @param auth_data Unformatted associated data + * @param auth_data_length Length in octets of @a auth_data + * @param[in,out] temp_buf Location of in-process data. + * + * @return A return code of type #fsl_shw_return_t. + */ +static inline fsl_shw_return_t process_assoc_from_nist_params(sah_Link ** link1, + uint32_t * + data_len, + fsl_shw_uco_t * + user_ctx, + fsl_shw_acco_t * + auth_ctx, + const uint8_t * + auth_data, + uint32_t + auth_data_length, + uint8_t ** + temp_buf) +{ + fsl_shw_return_t status; + uint32_t auth_size_length = + COMPUTE_NIST_AUTH_LEN_SIZE(auth_data_length); + uint32_t auth_pad_length = + auth_ctx->auth_info.CCM_ctx_info.block_size_bytes - + (auth_data_length + + auth_size_length) % + auth_ctx->auth_info.CCM_ctx_info.block_size_bytes; + + if (auth_pad_length == + auth_ctx->auth_info.CCM_ctx_info.block_size_bytes) { + auth_pad_length = 0; + } + + /* Put in Block0 */ + status = sah_Create_Link(user_ctx->mem_util, link1, + auth_ctx->auth_info.CCM_ctx_info.context, + auth_ctx->auth_info.CCM_ctx_info. + block_size_bytes, SAH_USES_LINK_DATA); + + if (auth_data_length != 0) { + if (status == FSL_RETURN_OK_S) { + /* Add on length preamble to auth data */ + STORE_NIST_AUTH_LEN(auth_data_length, *temp_buf); + status = sah_Append_Link(user_ctx->mem_util, *link1, + *temp_buf, auth_size_length, + SAH_OWNS_LINK_DATA); + *temp_buf += auth_size_length; /* 2, 6, or 10 bytes */ + } + + if (status == FSL_RETURN_OK_S) { + /* Add in auth data */ + status = sah_Append_Link(user_ctx->mem_util, *link1, + (uint8_t *) auth_data, + auth_data_length, + SAH_USES_LINK_DATA); + } + + if ((status == FSL_RETURN_OK_S) && (auth_pad_length > 0)) { + status = sah_Append_Link(user_ctx->mem_util, *link1, + block_zeros, auth_pad_length, + SAH_USES_LINK_DATA); + } + } + /* ... if auth_data_length != 0 */ + *data_len = auth_ctx->auth_info.CCM_ctx_info.block_size_bytes + + auth_data_length + auth_size_length + auth_pad_length; + + return status; +} /* end fn process_assoc_from_nist_params */ + +/*! + * Add a Descriptor which will process with CBC the NIST preamble data + * + * @param desc_chain Current chain + * @param user_ctx User's context + * @param auth_ctx Inf + * @pararm encrypt 0 => decrypt, non-zero => encrypt + * @param auth_data Additional auth data for this call + * @param auth_data_length Length in bytes of @a auth_data + * + * @return A return code of type #fsl_shw_return_t. + */ +static inline fsl_shw_return_t add_assoc_preamble(sah_Head_Desc ** desc_chain, + fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + int encrypt, + const uint8_t * auth_data, + uint32_t auth_data_length) +{ + uint8_t *temp_buf; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + fsl_shw_return_t status = FSL_RETURN_OK_S; + uint32_t cbc_data_length = 0; + /* Assume AES */ + uint32_t header = SAH_HDR_SKHA_ENC_DEC; + uint32_t temp_buf_flag; + unsigned chain_s2 = 1; + +#if defined (FSL_HAVE_SAHARA4) && !defined (USE_S2_CCM_DECRYPT_CHAIN) + if (!encrypt) { + chain_s2 = 0; + } +#endif +#if defined (FSL_HAVE_SAHARA4) && !defined (USE_S2_CCM_ENCRYPT_CHAIN) + if (encrypt) { + chain_s2 = 0; + } +#endif + /* Grab a block big enough for multiple uses so that only one allocate + * request needs to be made. + */ + temp_buf = + user_ctx->mem_util->mu_malloc(user_ctx->mem_util->mu_ref, + 3 * + auth_ctx->auth_info.CCM_ctx_info. + block_size_bytes); + + if (temp_buf == NULL) { + status = FSL_RETURN_NO_RESOURCE_S; + goto out; + } + + if (auth_ctx->flags & FSL_ACCO_NIST_CCM) { + status = process_assoc_from_nist_params(&link1, + &cbc_data_length, + user_ctx, + auth_ctx, + auth_data, + auth_data_length, + &temp_buf); + if (status != FSL_RETURN_OK_S) { + goto out; + } + /* temp_buf has been referenced (and incremented). Only 'own' it + * once, at its first value. Since the nist routine called above + * bumps it... + */ + temp_buf_flag = SAH_USES_LINK_DATA; + } else { /* if NIST */ + status = sah_Create_Link(user_ctx->mem_util, &link1, + (uint8_t *) auth_data, + auth_data_length, SAH_USES_LINK_DATA); + if (status != FSL_RETURN_OK_S) { + goto out; + } + /* for next/first use of temp_buf */ + temp_buf_flag = SAH_OWNS_LINK_DATA; + cbc_data_length = auth_data_length; + } /* else not NIST */ + +#if defined (FSL_HAVE_SAHARA2) || defined (USE_S2_CCM_ENCRYPT_CHAIN) \ + || defined (USE_S2_CCM_DECRYPT_CHAIN) + + if (!chain_s2) { + header = SAH_HDR_SKHA_CBC_ICV + ^ sah_insert_skha_mode_cbc ^ sah_insert_skha_aux0 + ^ sah_insert_skha_encrypt; + } else { + /* + * Auth data links have been created. Now create link for the + * useless output of the CBC calculation. + */ + status = sah_Create_Link(user_ctx->mem_util, &link2, + temp_buf, + auth_ctx->auth_info.CCM_ctx_info. + block_size_bytes, + temp_buf_flag | SAH_OUTPUT_LINK); + if (status != FSL_RETURN_OK_S) { + goto out; + } + + temp_buf += auth_ctx->auth_info.CCM_ctx_info.block_size_bytes; + + cbc_data_length -= + auth_ctx->auth_info.CCM_ctx_info.block_size_bytes; + if (cbc_data_length != 0) { + while ((status == FSL_RETURN_OK_S) + && (cbc_data_length != 0)) { + uint32_t linklen = + (cbc_data_length > + CBC_BUF_LEN) ? CBC_BUF_LEN : + cbc_data_length; + + status = + sah_Append_Link(user_ctx->mem_util, link2, + cbc_buffer, linklen, + SAH_USES_LINK_DATA | + SAH_OUTPUT_LINK); + if (status != FSL_RETURN_OK_S) { + goto out; + } + cbc_data_length -= linklen; + } + } + } +#else + header = SAH_HDR_SKHA_CBC_ICV + ^ sah_insert_skha_mode_cbc ^ sah_insert_skha_aux0 + ^ sah_insert_skha_encrypt; +#endif + /* Crank through auth data */ + status = sah_Append_Desc(user_ctx->mem_util, desc_chain, + header, link1, link2); + + out: + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(user_ctx->mem_util, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(user_ctx->mem_util, link2); + } + } + + (void)encrypt; + return status; +} /* add_assoc_preamble() */ + +#if SUPPORT_SSL +/*! + * Generate an SSL value + * + * @param user_ctx Info for acquiring memory + * @param auth_ctx Info for CTR0, size of MAC + * @param cipher_key_info + * @param auth_key_info + * @param auth_data_length + * @param auth_data + * @param payload_length + * @param payload + * @param ct + * @param auth_value + * + * @return A return code of type #fsl_shw_return_t. + */ +static fsl_shw_return_t do_ssl_gen(fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + fsl_shw_sko_t * cipher_key_info, + fsl_shw_sko_t * auth_key_info, + uint32_t auth_data_length, + const uint8_t * auth_data, + uint32_t payload_length, + const uint8_t * payload, + uint8_t * ct, uint8_t * auth_value) +{ + SAH_SF_DCLS; + uint8_t *ptr1 = NULL; + + /* Assume one-shot init-finalize... no precomputes */ + header = SAH_HDR_MDHA_SET_MODE_MD_KEY ^ + sah_insert_mdha_algorithm[auth_ctx->auth_info.hash_ctx_info. + algorithm] ^ sah_insert_mdha_init ^ + sah_insert_mdha_ssl ^ sah_insert_mdha_pdata ^ + sah_insert_mdha_mac_full; + + /* set up hmac */ + DESC_IN_KEY(header, 0, NULL, auth_key_info); + + /* This is wrong -- need to find 16 extra bytes of data from + * somewhere */ + DESC_IN_OUT(SAH_HDR_MDHA_HASH, payload_length, payload, 1, auth_value); + + /* set up encrypt */ + header = SAH_HDR_SKHA_SET_MODE_IV_KEY + ^ sah_insert_skha_mode[auth_ctx->cipher_ctx_info.mode] + ^ sah_insert_skha_encrypt + ^ sah_insert_skha_algorithm[cipher_key_info->algorithm]; + + /* Honor 'no key parity checking' for DES and TDES */ + if ((cipher_key_info->flags & FSL_SKO_KEY_IGNORE_PARITY) && + ((cipher_key_info->algorithm == FSL_KEY_ALG_DES) || + (cipher_key_info->algorithm == FSL_KEY_ALG_TDES))) { + header ^= sah_insert_skha_no_key_parity; + } + + if (auth_ctx->cipher_ctx_info.mode == FSL_SYM_MODE_CTR) { + header ^= + sah_insert_skha_modulus[auth_ctx->cipher_ctx_info. + modulus_exp]; + } + + if ((auth_ctx->cipher_ctx_info.mode == FSL_SYM_MODE_ECB) + || (auth_ctx->cipher_ctx_info.flags & FSL_SYM_CTX_INIT)) { + ptr1 = block_zeros; + } else { + ptr1 = auth_ctx->cipher_ctx_info.context; + } + + DESC_IN_KEY(header, auth_ctx->cipher_ctx_info.block_size_bytes, ptr1, + cipher_key_info); + + /* This is wrong -- need to find 16 extra bytes of data from + * somewhere... + */ + if (payload_length != 0) { + DESC_IN_OUT(SAH_HDR_SKHA_ENC_DEC, + payload_length, payload, payload_length, ct); + } + + SAH_SF_EXECUTE(); + + out: + SAH_SF_DESC_CLEAN(); + + /* Eliminate compiler warnings until full implementation... */ + (void)auth_data; + (void)auth_data_length; + + return ret; +} /* do_ssl_gen() */ +#endif + +/*! + * @brief Generate a (CCM) auth code and encrypt the payload. + * + * This is a very complicated function. Seven (or eight) descriptors are + * required to perform a CCM calculation. + * + * First: Load CTR0 and key. + * + * Second: Run an octet of data through to bump to CTR1. (This could be + * done in software, but software will have to bump and later decrement - + * or copy and bump. + * + * Third: (in Virtio) Load a descriptor with data of zeros for CBC IV. + * + * Fourth: Run any (optional) "additional data" through the CBC-mode + * portion of the algorithm. + * + * Fifth: Run the payload through in CCM mode. + * + * Sixth: Extract the unencrypted MAC. + * + * Seventh: Load CTR0. + * + * Eighth: Encrypt the MAC. + * + * @param user_ctx The user's context + * @param auth_ctx Info on this Auth operation + * @param cipher_key_info Key to encrypt payload + * @param auth_key_info (unused - same key in CCM) + * @param auth_data_length Length in bytes of @a auth_data + * @param auth_data Any auth-only data + * @param payload_length Length in bytes of @a payload + * @param payload The data to encrypt + * @param[out] ct The location to store encrypted data + * @param[out] auth_value The location to store authentication code + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_gen_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + fsl_shw_sko_t * cipher_key_info, + fsl_shw_sko_t * auth_key_info, + uint32_t auth_data_length, + const uint8_t * auth_data, + uint32_t payload_length, + const uint8_t * payload, + uint8_t * ct, uint8_t * auth_value) +{ + SAH_SF_DCLS; + + SAH_SF_USER_CHECK(); + + if (auth_ctx->mode == FSL_ACC_MODE_SSL) { +#if SUPPORT_SSL + ret = do_ssl_gen(user_ctx, auth_ctx, cipher_key_info, + auth_key_info, auth_data_length, auth_data, + payload_length, payload, ct, auth_value); +#else + ret = FSL_RETURN_BAD_MODE_S; +#endif + goto out; + } + + if (auth_ctx->mode != FSL_ACC_MODE_CCM) { + ret = FSL_RETURN_BAD_MODE_S; + goto out; + } + + /* Only support INIT and FINALIZE flags right now. */ + if ((auth_ctx->flags & (FSL_ACCO_CTX_INIT | FSL_ACCO_CTX_LOAD | + FSL_ACCO_CTX_SAVE | FSL_ACCO_CTX_FINALIZE)) + != (FSL_ACCO_CTX_INIT | FSL_ACCO_CTX_FINALIZE)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + /* Load CTR0 and Key */ + header = (SAH_HDR_SKHA_SET_MODE_IV_KEY + ^ sah_insert_skha_mode_ctr + ^ sah_insert_skha_modulus_128 ^ sah_insert_skha_encrypt); + DESC_IN_KEY(header, + auth_ctx->cipher_ctx_info.block_size_bytes, + auth_ctx->cipher_ctx_info.context, cipher_key_info); + + /* Encrypt dummy data to bump to CTR1 */ + header = SAH_HDR_SKHA_ENC_DEC; + DESC_IN_OUT(header, auth_ctx->mac_length, garbage_output, + auth_ctx->mac_length, garbage_output); + +#if defined(FSL_HAVE_SAHARA2) || defined(USE_S2_CCM_ENCRYPT_CHAIN) +#ifndef NO_ZERO_IV_LOAD + header = (SAH_HDR_SKHA_SET_MODE_IV_KEY + ^ sah_insert_skha_encrypt ^ sah_insert_skha_mode_cbc); + DESC_IN_IN(header, + auth_ctx->auth_info.CCM_ctx_info.block_size_bytes, + block_zeros, 0, NULL); +#endif +#endif + + ret = add_assoc_preamble(&desc_chain, user_ctx, + auth_ctx, 1, auth_data, auth_data_length); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + /* Process the payload */ + header = (SAH_HDR_SKHA_SET_MODE_ENC_DEC + ^ sah_insert_skha_mode_ccm + ^ sah_insert_skha_modulus_128 ^ sah_insert_skha_encrypt); +#if defined (FSL_HAVE_SAHARA4) && !defined (USE_S2_CCM_ENCRYPT_CHAIN) + header ^= sah_insert_skha_aux0; +#endif + if (payload_length != 0) { + DESC_IN_OUT(header, payload_length, payload, payload_length, + ct); + } else { + DESC_IN_OUT(header, 0, NULL, 0, NULL); + } /* if payload_length */ + +#if defined (FSL_HAVE_SAHARA4) && !defined (USE_S2_CCM_ENCRYPT_CHAIN) + /* Pull out the CBC-MAC value. */ + DESC_OUT_OUT(SAH_HDR_SKHA_READ_CONTEXT_IV, 0, NULL, + auth_ctx->mac_length, auth_value); +#else + /* Pull out the unencrypted CBC-MAC value. */ + DESC_OUT_OUT(SAH_HDR_SKHA_READ_CONTEXT_IV, + 0, NULL, auth_ctx->mac_length, auth_ctx->unencrypted_mac); + + /* Now load CTR0 in, and encrypt the MAC */ + header = SAH_HDR_SKHA_SET_MODE_IV_KEY + ^ sah_insert_skha_encrypt + ^ sah_insert_skha_mode_ctr ^ sah_insert_skha_modulus_128; + DESC_IN_IN(header, + auth_ctx->cipher_ctx_info.block_size_bytes, + auth_ctx->cipher_ctx_info.context, 0, NULL); + + header = SAH_HDR_SKHA_ENC_DEC; /* Desc. #4 SKHA Enc/Dec */ + DESC_IN_OUT(header, + auth_ctx->mac_length, auth_ctx->unencrypted_mac, + auth_ctx->mac_length, auth_value); +#endif + + SAH_SF_EXECUTE(); + + out: + SAH_SF_DESC_CLEAN(); + + (void)auth_key_info; + return ret; +} /* fsl_shw_gen_encrypt() */ + +/*! + * @brief Authenticate and decrypt a (CCM) stream. + * + * @param user_ctx The user's context + * @param auth_ctx Info on this Auth operation + * @param cipher_key_info Key to encrypt payload + * @param auth_key_info (unused - same key in CCM) + * @param auth_data_length Length in bytes of @a auth_data + * @param auth_data Any auth-only data + * @param payload_length Length in bytes of @a payload + * @param ct The encrypted data + * @param auth_value The authentication code to validate + * @param[out] payload The location to store decrypted data + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_auth_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + fsl_shw_sko_t * cipher_key_info, + fsl_shw_sko_t * auth_key_info, + uint32_t auth_data_length, + const uint8_t * auth_data, + uint32_t payload_length, + const uint8_t * ct, + const uint8_t * auth_value, + uint8_t * payload) +{ + SAH_SF_DCLS; +#if defined(FSL_HAVE_SAHARA2) || defined(USE_S2_CCM_DECRYPT_CHAIN) + uint8_t *calced_auth = NULL; + unsigned blocking = user_ctx->flags & FSL_UCO_BLOCKING_MODE; +#endif + + SAH_SF_USER_CHECK(); + + /* Only support CCM */ + if (auth_ctx->mode != FSL_ACC_MODE_CCM) { + ret = FSL_RETURN_BAD_MODE_S; + goto out; + } + /* Only support INIT and FINALIZE flags right now. */ + if ((auth_ctx->flags & (FSL_ACCO_CTX_INIT | FSL_ACCO_CTX_LOAD | + FSL_ACCO_CTX_SAVE | FSL_ACCO_CTX_FINALIZE)) + != (FSL_ACCO_CTX_INIT | FSL_ACCO_CTX_FINALIZE)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + /* Load CTR0 and Key */ + header = SAH_HDR_SKHA_SET_MODE_IV_KEY + ^ sah_insert_skha_mode_ctr ^ sah_insert_skha_modulus_128; +#if defined (FSL_HAVE_SAHARA4) && !defined (USE_S2_CCM_DECRYPT_CHAIN) + header ^= sah_insert_skha_aux0; +#endif + DESC_IN_KEY(header, + auth_ctx->cipher_ctx_info.block_size_bytes, + auth_ctx->cipher_ctx_info.context, cipher_key_info); + + /* Decrypt the MAC which the user passed in */ + header = SAH_HDR_SKHA_ENC_DEC; + DESC_IN_OUT(header, + auth_ctx->mac_length, auth_value, + auth_ctx->mac_length, auth_ctx->unencrypted_mac); + +#if defined(FSL_HAVE_SAHARA2) || defined(USE_S2_CCM_DECRYPT_CHAIN) +#ifndef NO_ZERO_IV_LOAD + header = (SAH_HDR_SKHA_SET_MODE_IV_KEY + ^ sah_insert_skha_encrypt ^ sah_insert_skha_mode_cbc); + DESC_IN_IN(header, + auth_ctx->auth_info.CCM_ctx_info.block_size_bytes, + block_zeros, 0, NULL); +#endif +#endif + + ret = add_assoc_preamble(&desc_chain, user_ctx, + auth_ctx, 0, auth_data, auth_data_length); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + /* Process the payload */ + header = (SAH_HDR_SKHA_SET_MODE_ENC_DEC + ^ sah_insert_skha_mode_ccm ^ sah_insert_skha_modulus_128); +#if defined (FSL_HAVE_SAHARA4) && !defined (USE_S2_CCM_DECRYPT_CHAIN) + header ^= sah_insert_skha_aux0; +#endif + if (payload_length != 0) { + DESC_IN_OUT(header, payload_length, ct, payload_length, + payload); + } else { + DESC_IN_OUT(header, 0, NULL, 0, NULL); + } + +#if defined (FSL_HAVE_SAHARA2) || defined (USE_S2_CCM_DECRYPT_CHAIN) + /* Now pull CBC context (unencrypted MAC) out for comparison. */ + /* Need to allocate a place for it, to handle non-blocking mode + * when this stack frame will disappear! + */ + calced_auth = DESC_TEMP_ALLOC(auth_ctx->mac_length); + header = SAH_HDR_SKHA_READ_CONTEXT_IV; + DESC_OUT_OUT(header, 0, NULL, auth_ctx->mac_length, calced_auth); + if (!blocking) { + /* get_results will need this for comparison */ + desc_chain->out1_ptr = calced_auth; + desc_chain->out2_ptr = auth_ctx->unencrypted_mac; + desc_chain->out_len = auth_ctx->mac_length; + } +#endif + + SAH_SF_EXECUTE(); + +#if defined (FSL_HAVE_SAHARA2) || defined (USE_S2_CCM_DECRYPT_CHAIN) + if (blocking && (ret == FSL_RETURN_OK_S)) { + unsigned i; + /* Validate the auth code */ + for (i = 0; i < auth_ctx->mac_length; i++) { + if (calced_auth[i] != auth_ctx->unencrypted_mac[i]) { + ret = FSL_RETURN_AUTH_FAILED_S; + break; + } + } + } +#endif + + out: + SAH_SF_DESC_CLEAN(); +#if defined (FSL_HAVE_SAHARA2) || defined (USE_S2_CCM_DECRYPT_CHAIN) + DESC_TEMP_FREE(calced_auth); +#endif + + (void)auth_key_info; + return ret; +} /* fsl_shw_gen_decrypt() */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/fsl_shw_hash.c linux-2.6.26-lab126/drivers/mxc/security/sahara2/fsl_shw_hash.c --- linux-2.6.26/drivers/mxc/security/sahara2/fsl_shw_hash.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/fsl_shw_hash.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,186 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file fsl_shw_hash.c + * + * This file implements Cryptographic Hashing functions of the FSL SHW API + * for Sahara. This does not include HMAC. + */ + +#include "sahara.h" +#include "sf_util.h" + +#ifdef LINUX_KERNEL +EXPORT_SYMBOL(fsl_shw_hash); +#endif + +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-005 */ +/*! + * Hash a stream of data with a cryptographic hash algorithm. + * + * The flags in the @a hash_ctx control the operation of this function. + * + * Hashing functions work on 64 octets of message at a time. Therefore, when + * any partial hashing of a long message is performed, the message @a length of + * each segment must be a multiple of 64. When ready to + * #FSL_HASH_FLAGS_FINALIZE the hash, the @a length may be any value. + * + * With the #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_FINALIZE flags on, a + * one-shot complete hash, including padding, will be performed. The @a length + * may be any value. + * + * The first octets of a data stream can be hashed by setting the + * #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_SAVE flags. The @a length must be + * a multiple of 64. + * + * The flag #FSL_HASH_FLAGS_LOAD is used to load a context previously saved by + * #FSL_HASH_FLAGS_SAVE. The two in combination will allow a (multiple-of-64 + * octets) 'middle sequence' of the data stream to be hashed with the + * beginning. The @a length must again be a multiple of 64. + * + * Since the flag #FSL_HASH_FLAGS_LOAD is used to load a context previously + * saved by #FSL_HASH_FLAGS_SAVE, the #FSL_HASH_FLAGS_LOAD and + * #FSL_HASH_FLAGS_FINALIZE flags, used together, can be used to finish the + * stream. The @a length may be any value. + * + * If the user program wants to do the padding for the hash, it can leave off + * the #FSL_HASH_FLAGS_FINALIZE flag. The @a length must then be a multiple of + * 64 octets. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] hash_ctx Hashing algorithm and state of the cipher. + * @param msg Pointer to the data to be hashed. + * @param length Length, in octets, of the @a msg. + * @param[out] result If not null, pointer to where to store the hash + * digest. + * @param result_len Number of octets to store in @a result. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_hash(fsl_shw_uco_t * user_ctx, + fsl_shw_hco_t * hash_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len) +{ + SAH_SF_DCLS; + unsigned ctx_flags = (hash_ctx->flags & (FSL_HASH_FLAGS_INIT + | FSL_HASH_FLAGS_LOAD + | FSL_HASH_FLAGS_SAVE + | FSL_HASH_FLAGS_FINALIZE)); + + SAH_SF_USER_CHECK(); + + /* Reset expectations if user gets overly zealous. */ + if (result_len > hash_ctx->digest_length) { + result_len = hash_ctx->digest_length; + } + + /* Validate hash ctx flags. + * Need INIT or LOAD but not both. + * Need SAVE or digest ptr (both is ok). + */ + if (((ctx_flags & (FSL_HASH_FLAGS_INIT | FSL_HASH_FLAGS_LOAD)) + == (FSL_HASH_FLAGS_INIT | FSL_HASH_FLAGS_LOAD)) + || ((ctx_flags & (FSL_HASH_FLAGS_INIT | FSL_HASH_FLAGS_LOAD)) == 0) + || (!(ctx_flags & FSL_HASH_FLAGS_SAVE) && (result == NULL))) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + if (ctx_flags & FSL_HASH_FLAGS_INIT) { + sah_Oct_Str out_ptr; + unsigned out_len; + + /* Create desc to perform the initial hashing operation */ + /* Desc. #8 w/INIT and algorithm */ + header = SAH_HDR_MDHA_SET_MODE_HASH + ^ sah_insert_mdha_init + ^ sah_insert_mdha_algorithm[hash_ctx->algorithm]; + + /* If user wants one-shot, set padding operation. */ + if (ctx_flags & FSL_HASH_FLAGS_FINALIZE) { + header ^= sah_insert_mdha_pdata; + } + + /* Determine where Digest will go - hash_ctx or result */ + if (ctx_flags & FSL_HASH_FLAGS_SAVE) { + out_ptr = (sah_Oct_Str) hash_ctx->context; + out_len = hash_ctx->context_register_length; + } else { + out_ptr = result; + out_len = (result_len > hash_ctx->digest_length) + ? hash_ctx->digest_length : result_len; + } + + DESC_IN_OUT(header, length, (sah_Oct_Str) msg, out_len, + out_ptr); + } else { /* not doing hash INIT */ + void *out_ptr; + unsigned out_len; + + /* + * Build two descriptors -- one to load in context/set mode, the + * other to compute & retrieve hash/context value. + * + * First up - Desc. #6 to load context. + */ + /* Desc. #8 w/algorithm */ + header = SAH_HDR_MDHA_SET_MODE_MD_KEY + ^ sah_insert_mdha_algorithm[hash_ctx->algorithm]; + + if (ctx_flags & FSL_HASH_FLAGS_FINALIZE) { + header ^= sah_insert_mdha_pdata; + } + + /* Message Digest (in) */ + DESC_IN_IN(header, + hash_ctx->context_register_length, + (sah_Oct_Str) hash_ctx->context, 0, NULL); + + if (ctx_flags & FSL_HASH_FLAGS_SAVE) { + out_ptr = hash_ctx->context; + out_len = hash_ctx->context_register_length; + } else { + out_ptr = result; + out_len = result_len; + } + + /* Second -- run data through and retrieve ctx regs */ + /* Desc. #10 - no mode register with this. */ + header = SAH_HDR_MDHA_HASH; + DESC_IN_OUT(header, length, (sah_Oct_Str) msg, out_len, + out_ptr); + } /* else not INIT */ + + /* Now that execution is rejoined, we can append another descriptor + to extract the digest/context a second time, into the result. */ + if ((ctx_flags & FSL_HASH_FLAGS_SAVE) + && (result != NULL) && (result_len != 0)) { + + header = SAH_HDR_MDHA_STORE_DIGEST; + + /* Message Digest (out) */ + DESC_IN_OUT(header, 0, NULL, + (result_len > hash_ctx->digest_length) + ? hash_ctx->digest_length : result_len, result); + } + + SAH_SF_EXECUTE(); + + out: + SAH_SF_DESC_CLEAN(); + + return ret; +} /* fsl_shw_hash() */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/fsl_shw_hmac.c linux-2.6.26-lab126/drivers/mxc/security/sahara2/fsl_shw_hmac.c --- linux-2.6.26/drivers/mxc/security/sahara2/fsl_shw_hmac.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/fsl_shw_hmac.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,266 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file fsl_shw_hmac.c + * + * This file implements Hashed Message Authentication Code functions of the FSL + * SHW API for Sahara. + */ + +#include "sahara.h" +#include "sf_util.h" + +#ifdef __KERNEL__ +EXPORT_SYMBOL(fsl_shw_hmac_precompute); +EXPORT_SYMBOL(fsl_shw_hmac); +#endif + +/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-001 */ +/*! + * Get the precompute information + * + * + * @param user_ctx + * @param key_info + * @param hmac_ctx + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_hmac_precompute(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx) +{ + SAH_SF_DCLS; + + SAH_SF_USER_CHECK(); + + if ((key_info->algorithm != FSL_KEY_ALG_HMAC) || + (key_info->key_length > 64)) { + return FSL_RETURN_BAD_ALGORITHM_S; + } else if (key_info->key_length == 0) { + return FSL_RETURN_BAD_KEY_LENGTH_S; + } + + /* Set up to start the Inner Calculation */ + /* Desc. #8 w/IPAD, & INIT */ + header = SAH_HDR_MDHA_SET_MODE_HASH + ^ sah_insert_mdha_ipad + ^ sah_insert_mdha_init + ^ sah_insert_mdha_algorithm[hmac_ctx->algorithm]; + + DESC_KEY_OUT(header, key_info, + hmac_ctx->context_register_length, + (uint8_t *) hmac_ctx->inner_precompute); + + /* Set up for starting Outer calculation */ + /* exchange IPAD bit for OPAD bit */ + header ^= (sah_insert_mdha_ipad ^ sah_insert_mdha_opad); + + /* Theoretically, we can leave this link out and use the key which is + * already in the register... however, if we do, the resulting opad + * hash does not have the correct value when using the model. */ + DESC_KEY_OUT(header, key_info, + hmac_ctx->context_register_length, + (uint8_t *) hmac_ctx->outer_precompute); + + SAH_SF_EXECUTE(); + if (ret == FSL_RETURN_OK_S) { + /* flag that precomputes have been entered in this hco + * assume it'll first be used for initilizing */ + hmac_ctx->flags |= (FSL_HMAC_FLAGS_INIT | + FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT); + } + + out: + SAH_SF_DESC_CLEAN(); + + return ret; +} + +/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-002 */ +/*! + * Get the hmac + * + * + * @param user_ctx Info for acquiring memory + * @param key_info + * @param hmac_ctx + * @param msg + * @param length + * @param result + * @param result_len + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_hmac(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len) +{ + SAH_SF_DCLS; + + SAH_SF_USER_CHECK(); + + /* check flag consistency */ + /* Note that Final, Init, and Save are an illegal combination when a key + * is being used. Because of the logic flow of this routine, that is + * taken care of without being explict */ + if ( + /* nothing to work on */ + (((hmac_ctx->flags & FSL_HMAC_FLAGS_INIT) == 0) && + ((hmac_ctx->flags & FSL_HMAC_FLAGS_LOAD) == 0)) || + /* can't do both */ + ((hmac_ctx->flags & FSL_HMAC_FLAGS_INIT) && + (hmac_ctx->flags & FSL_HMAC_FLAGS_LOAD)) || + /* must be some output */ + (((hmac_ctx->flags & FSL_HMAC_FLAGS_SAVE) == 0) && + ((hmac_ctx->flags & FSL_HMAC_FLAGS_FINALIZE) == 0))) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + /* build descriptor #6 */ + + /* start building descriptor header */ + header = SAH_HDR_MDHA_SET_MODE_MD_KEY ^ + sah_insert_mdha_algorithm[hmac_ctx->algorithm] ^ + sah_insert_mdha_init; + + /* if this is to finalize the digest, mark to pad last block */ + if (hmac_ctx->flags & FSL_HMAC_FLAGS_FINALIZE) { + header ^= sah_insert_mdha_pdata; + } + + /* Check if this is a one shot */ + if ((hmac_ctx->flags & FSL_HMAC_FLAGS_INIT) && + (hmac_ctx->flags & FSL_HMAC_FLAGS_FINALIZE)) { + + header ^= sah_insert_mdha_hmac; + + /* See if this uses Precomputes */ + if (hmac_ctx->flags & FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT) { + DESC_IN_IN(header, + hmac_ctx->context_register_length, + (uint8_t *) hmac_ctx->inner_precompute, + hmac_ctx->context_length, + (uint8_t *) hmac_ctx->outer_precompute); + } else { /* Precomputes not requested, try using Key */ + if (key_info->key != NULL) { + /* first, validate the key fields and related flag */ + if ((key_info->key_length == 0) + || (key_info->key_length > 64)) { + ret = FSL_RETURN_BAD_KEY_LENGTH_S; + goto out; + } else { + if (key_info->algorithm != + FSL_KEY_ALG_HMAC) { + ret = + FSL_RETURN_BAD_ALGORITHM_S; + goto out; + } + } + + /* finish building descriptor header (Key specific) */ + header ^= sah_insert_mdha_mac_full; + DESC_IN_KEY(header, 0, NULL, key_info); + } else { /* not using Key or Precomputes, so die */ + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + } + } else { /* it's not a one shot, must be multi-step */ + /* this the last chunk? */ + if (hmac_ctx->flags & FSL_HMAC_FLAGS_FINALIZE) { + header ^= sah_insert_mdha_hmac; + DESC_IN_IN(header, + hmac_ctx->context_register_length, + (uint8_t *) hmac_ctx->ongoing_context, + hmac_ctx->context_length, + (uint8_t *) hmac_ctx->outer_precompute); + } else { /* not last chunk */ + uint8_t *ptr1; + + if (hmac_ctx->flags & FSL_HMAC_FLAGS_INIT) { + /* must be using precomputes, cannot 'chunk' message + * starting with a key */ + if (hmac_ctx-> + flags & FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT) + { + ptr1 = + (uint8_t *) hmac_ctx-> + inner_precompute; + } else { + ret = FSL_RETURN_NO_RESOURCE_S; + goto out; + } + } else { + ptr1 = (uint8_t *) hmac_ctx->ongoing_context; + } + + if (ret != FSL_RETURN_OK_S) { + goto out; + } + DESC_IN_IN(header, + hmac_ctx->context_register_length, ptr1, + 0, NULL); + } + } /* multi-step */ + + /* build descriptor #10 & maybe 11 */ + header = SAH_HDR_MDHA_HASH; + + if (hmac_ctx->flags & FSL_HMAC_FLAGS_FINALIZE) { + /* check that the results parameters seem reasonable */ + if ((result_len != 0) && (result != NULL)) { + if (result_len > hmac_ctx->context_register_length) { + result_len = hmac_ctx->context_register_length; + } + + /* message in / digest out (descriptor #10) */ + DESC_IN_OUT(header, length, msg, result_len, result); + + /* see if descriptor #11 needs to be built */ + if (hmac_ctx->flags & FSL_HMAC_FLAGS_SAVE) { + header = SAH_HDR_MDHA_STORE_DIGEST; + /* nothing in / context out */ + DESC_IN_IN(header, 0, NULL, + hmac_ctx->context_register_length, + (uint8_t *) hmac_ctx-> + ongoing_context); + } + } else { + /* something wrong with result or its length */ + ret = FSL_RETURN_BAD_DATA_LENGTH_S; + } + } else { /* finalize not set, so store in ongoing context field */ + if ((length % 64) == 0) { /* this will change for 384/512 support */ + /* message in / context out */ + DESC_IN_OUT(header, length, msg, + hmac_ctx->context_register_length, + (uint8_t *) hmac_ctx->ongoing_context); + } else { + /* not final data, and not multiple of block length */ + ret = FSL_RETURN_BAD_DATA_LENGTH_S; + } + } + + SAH_SF_EXECUTE(); + + out: + SAH_SF_DESC_CLEAN(); + + return ret; +} /* fsl_shw_hmac() */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/fsl_shw_keystore.c linux-2.6.26-lab126/drivers/mxc/security/sahara2/fsl_shw_keystore.c --- linux-2.6.26/drivers/mxc/security/sahara2/fsl_shw_keystore.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/fsl_shw_keystore.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,837 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/** + * @file fsl_shw_keystore.c + * + * File which implements a default keystore policy, for use as the system + * keystore. + */ +#include "fsl_platform.h" +#include "fsl_shw.h" +#include "fsl_shw_keystore.h" + +#if defined(DIAG_DRV_IF) +#include +#endif + +#if !defined(FSL_HAVE_SCC2) && defined(__KERNEL__) +#include +#endif + +/* Define a semaphore to protect the keystore data */ +#ifdef __KERNEL__ +#define LOCK_INCLUDES os_lock_context_t context +#define ACQUIRE_LOCK os_lock_save_context(keystore->lock, context) +#define RELEASE_LOCK os_unlock_restore_context(keystore->lock, context); +#else +#define LOCK_INCLUDES +#define ACQUIRE_LOCK +#define RELEASE_LOCK +#endif /* __KERNEL__ */ + +/*! + * Calculates the byte offset into a word + * @param bp The byte (char*) pointer + * @return The offset (0, 1, 2, or 3) + */ +#define SCC_BYTE_OFFSET(bp) ((uint32_t)(bp) % sizeof(uint32_t)) + +/*! + * Converts (by rounding down) a byte pointer into a word pointer + * @param bp The byte (char*) pointer + * @return The word (uint32_t) as though it were an aligned (uint32_t*) + */ +#define SCC_WORD_PTR(bp) (((uint32_t)(bp)) & ~(sizeof(uint32_t)-1)) + +/* Depending on the architecture, these functions should be defined + * differently. On Platforms with SCC2, the functions use the secure + * partition interface and should be available in both user and kernel space. + * On platforms with SCC, they use the SCC keystore interface. This is only + * available in kernel mode, so they should be stubbed out in user mode. + */ +#if defined(FSL_HAVE_SCC2) || (defined(FSL_HAVE_SCC) && defined(__KERNEL__)) +EXPORT_SYMBOL(fsl_shw_init_keystore); +void fsl_shw_init_keystore( + fsl_shw_kso_t *keystore, + fsl_shw_return_t(*data_init) (fsl_shw_uco_t *user_ctx, + void **user_data), + void (*data_cleanup) (fsl_shw_uco_t *user_ctx, + void **user_data), + fsl_shw_return_t(*slot_alloc) (void *user_data, + uint32_t size, + uint64_t owner_id, + uint32_t *slot), + fsl_shw_return_t(*slot_dealloc) (void *user_data, + uint64_t + owner_id, + uint32_t slot), + fsl_shw_return_t(*slot_verify_access) (void + *user_data, + uint64_t + owner_id, + uint32_t + slot), + void *(*slot_get_address) (void *user_data, + uint32_t handle), + uint32_t(*slot_get_base) (void *user_data, + uint32_t handle), + uint32_t(*slot_get_offset) (void *user_data, + uint32_t handle), + uint32_t(*slot_get_slot_size) (void *user_data, + uint32_t handle)) +{ + keystore->data_init = data_init; + keystore->data_cleanup = data_cleanup; + keystore->slot_alloc = slot_alloc; + keystore->slot_dealloc = slot_dealloc; + keystore->slot_verify_access = slot_verify_access; + keystore->slot_get_address = slot_get_address; + keystore->slot_get_base = slot_get_base; + keystore->slot_get_offset = slot_get_offset; + keystore->slot_get_slot_size = slot_get_slot_size; +} + +EXPORT_SYMBOL(fsl_shw_init_keystore_default); +void fsl_shw_init_keystore_default(fsl_shw_kso_t *keystore) +{ + keystore->data_init = shw_kso_init_data; + keystore->data_cleanup = shw_kso_cleanup_data; + keystore->slot_alloc = shw_slot_alloc; + keystore->slot_dealloc = shw_slot_dealloc; + keystore->slot_verify_access = shw_slot_verify_access; + keystore->slot_get_address = shw_slot_get_address; + keystore->slot_get_base = shw_slot_get_base; + keystore->slot_get_offset = shw_slot_get_offset; + keystore->slot_get_slot_size = shw_slot_get_slot_size; +} + +/*! + * Do any keystore specific initializations + */ +EXPORT_SYMBOL(fsl_shw_establish_keystore); +fsl_shw_return_t fsl_shw_establish_keystore(fsl_shw_uco_t *user_ctx, + fsl_shw_kso_t *keystore) +{ + if (keystore->data_init == NULL) { + return FSL_RETURN_ERROR_S; + } + + /* Call the data_init function for any user setup */ + return keystore->data_init(user_ctx, &(keystore->user_data)); +} + +EXPORT_SYMBOL(fsl_shw_release_keystore); +void fsl_shw_release_keystore(fsl_shw_uco_t *user_ctx, + fsl_shw_kso_t *keystore) +{ + + /* Call the data_cleanup function for any keystore cleanup. + * NOTE: The keystore doesn't have any way of telling which keys are using + * it, so it is up to the user program to manage their key objects + * correctly. + */ + if ((keystore != NULL) && (keystore->data_cleanup != NULL)) { + keystore->data_cleanup(user_ctx, &(keystore->user_data)); + } + return; +} + +fsl_shw_return_t keystore_slot_alloc(fsl_shw_kso_t *keystore, uint32_t size, + uint64_t owner_id, uint32_t *slot) +{ + LOCK_INCLUDES; + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + +#ifdef DIAG_DRV_IF + LOG_DIAG("In keystore_slot_alloc."); + +#endif + ACQUIRE_LOCK; + if ((keystore->slot_alloc == NULL) || (keystore->user_data == NULL)) { + goto out; + } + +#ifdef DIAG_DRV_IF + LOG_DIAG_ARGS("key length: %i, handle: %i\n", size, *slot); + +#endif +retval = keystore->slot_alloc(keystore->user_data, size, owner_id, slot); +out:RELEASE_LOCK; + return retval; +} + +fsl_shw_return_t keystore_slot_dealloc(fsl_shw_kso_t *keystore, + uint64_t owner_id, uint32_t slot) +{ + LOCK_INCLUDES; + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + ACQUIRE_LOCK; + if ((keystore->slot_alloc == NULL) || (keystore->user_data == NULL)) { + goto out; + } + retval = + keystore->slot_dealloc(keystore->user_data, owner_id, slot); +out:RELEASE_LOCK; + return retval; +} + +fsl_shw_return_t +keystore_slot_load(fsl_shw_kso_t * keystore, uint64_t owner_id, uint32_t slot, + const uint8_t * key_data, uint32_t key_length) +{ + +#ifdef FSL_HAVE_SCC2 + LOCK_INCLUDES; + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + uint32_t slot_size; + uint32_t i; + uint8_t * slot_location; + ACQUIRE_LOCK; + if ((keystore->slot_verify_access == NULL) || + (keystore->user_data == NULL)) + goto out; + if (keystore-> + slot_verify_access(keystore->user_data, owner_id, + slot) !=FSL_RETURN_OK_S) { + retval = FSL_RETURN_AUTH_FAILED_S; + goto out; + } + slot_size = keystore->slot_get_slot_size(keystore->user_data, slot); + if (key_length > slot_size) { + retval = FSL_RETURN_BAD_DATA_LENGTH_S; + goto out; + } + slot_location = keystore->slot_get_address(keystore->user_data, slot); + for (i = 0; i < key_length; i++) { + slot_location[i] = key_data[i]; + } + retval = FSL_RETURN_OK_S; +out:RELEASE_LOCK; + return retval; + +#else /* FSL_HAVE_SCC2 */ + fsl_shw_return_t retval; + scc_return_t scc_ret; + scc_ret = + scc_load_slot(owner_id, slot, (uint8_t *) key_data, key_length); + switch (scc_ret) { + case SCC_RET_OK: + retval = FSL_RETURN_OK_S; + break; + case SCC_RET_VERIFICATION_FAILED: + retval = FSL_RETURN_AUTH_FAILED_S; + break; + case SCC_RET_INSUFFICIENT_SPACE: + retval = FSL_RETURN_BAD_DATA_LENGTH_S; + break; + default: + retval = FSL_RETURN_ERROR_S; + } + return retval; + +#endif /* FSL_HAVE_SCC2 */ +} + +fsl_shw_return_t +keystore_slot_read(fsl_shw_kso_t * keystore, uint64_t owner_id, uint32_t slot, + uint32_t key_length, uint8_t * key_data) +{ +#ifdef FSL_HAVE_SCC2 + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + uint8_t *slot_addr; + uint32_t slot_size; + + slot_addr = keystore->slot_get_address(keystore->user_data, slot); + slot_size = keystore->slot_get_slot_size(keystore->user_data, slot); + + if (key_length > slot_size) { + retval = FSL_RETURN_BAD_KEY_LENGTH_S; + goto out; + } + + memcpy(key_data, slot_addr, key_length); + retval = FSL_RETURN_OK_S; + + out: + return retval; + +#else /* Have SCC2 */ + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + scc_return_t scc_ret; + printk("keystore SCC \n"); + + scc_ret = + scc_read_slot(owner_id, slot, key_length, (uint8_t *) key_data); + printk("keystore SCC Ret value: %d \n", scc_ret); + switch (scc_ret) { + case SCC_RET_OK: + retval = FSL_RETURN_OK_S; + break; + case SCC_RET_VERIFICATION_FAILED: + retval = FSL_RETURN_AUTH_FAILED_S; + break; + case SCC_RET_INSUFFICIENT_SPACE: + retval = FSL_RETURN_BAD_DATA_LENGTH_S; + break; + default: + retval = FSL_RETURN_ERROR_S; + } + + return retval; + +#endif /* FSL_HAVE_SCC2 */ +}/* end fn keystore_slot_read */ + +fsl_shw_return_t +keystore_slot_encrypt(fsl_shw_uco_t *user_ctx, fsl_shw_kso_t *keystore, + uint64_t owner_id, uint32_t slot, uint32_t length, + uint8_t *destination) +{ + +#ifdef FSL_HAVE_SCC2 + LOCK_INCLUDES; + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + uint32_t slot_length; + uint32_t IV[4]; + uint32_t * iv_ptr = (uint32_t *) & (owner_id); + + /* Build the IV */ + IV[0] = iv_ptr[0]; + IV[1] = iv_ptr[1]; + IV[2] = 0; + IV[3] = 0; + ACQUIRE_LOCK; + + /* Ensure that the data will fit in the key slot */ + slot_length = + keystore->slot_get_slot_size(keystore->user_data, slot); + if (length > slot_length) { + goto out; + } + + /* Call scc encrypt function to encrypt the data. */ + retval = do_scc_encrypt_region(user_ctx, + (void *)keystore-> + slot_get_base(keystore->user_data, + slot), + keystore->slot_get_offset(keystore-> + user_data, + slot), + length, destination, IV, + FSL_SHW_CYPHER_MODE_CBC); + goto out; +out:RELEASE_LOCK; + return retval; + +#else + scc_return_t retval; + retval = scc_encrypt_slot(owner_id, slot, length, destination); + if (retval == SCC_RET_OK) + return FSL_RETURN_OK_S; + return FSL_RETURN_ERROR_S; + +#endif /* FSL_HAVE_SCC2 */ +} + +fsl_shw_return_t +keystore_slot_decrypt(fsl_shw_uco_t *user_ctx, fsl_shw_kso_t *keystore, + uint64_t owner_id, uint32_t slot, uint32_t length, + const uint8_t *source) +{ + +#ifdef FSL_HAVE_SCC2 + LOCK_INCLUDES; + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + uint32_t slot_length; + uint32_t IV[4]; + uint32_t *iv_ptr = (uint32_t *) & (owner_id); + + /* Build the IV */ + IV[0] = iv_ptr[0]; + IV[1] = iv_ptr[1]; + IV[2] = 0; + IV[3] = 0; + ACQUIRE_LOCK; + + /* Call scc decrypt function to decrypt the data. */ + + /* Ensure that the data will fit in the key slot */ + slot_length = + keystore->slot_get_slot_size(keystore->user_data, slot); + if (length > slot_length) + goto out; + + /* Call scc decrypt function to encrypt the data. */ + retval = do_scc_decrypt_region(user_ctx, + (void *)keystore-> + slot_get_base(keystore->user_data, + slot), + keystore->slot_get_offset(keystore-> + user_data, + slot), + length, source, IV, + FSL_SHW_CYPHER_MODE_CBC); + goto out; +out:RELEASE_LOCK; + return retval; + +#else + scc_return_t retval; + retval = scc_decrypt_slot(owner_id, slot, length, source); + if (retval == SCC_RET_OK) + return FSL_RETURN_OK_S; + return FSL_RETURN_ERROR_S; + +#endif /* FSL_HAVE_SCC2 */ +} + +#else /* SCC in userspace */ +void fsl_shw_init_keystore( + fsl_shw_kso_t *keystore, + fsl_shw_return_t(*data_init) (fsl_shw_uco_t *user_ctx, + void **user_data), + void (*data_cleanup) (fsl_shw_uco_t *user_ctx, + void **user_data), + fsl_shw_return_t(*slot_alloc) (void *user_data, + uint32_t size, + uint64_t owner_id, + uint32_t *slot), + fsl_shw_return_t(*slot_dealloc) (void *user_data, + uint64_t + owner_id, + uint32_t slot), + fsl_shw_return_t(*slot_verify_access) (void + *user_data, + uint64_t + owner_id, + uint32_t + slot), + void *(*slot_get_address) (void *user_data, + uint32_t handle), + uint32_t(*slot_get_base) (void *user_data, + uint32_t handle), + uint32_t(*slot_get_offset) (void *user_data, + uint32_t handle), + uint32_t(*slot_get_slot_size) (void *user_data, + uint32_t handle)) +{ + (void)keystore; + (void)data_init; + (void)data_cleanup; + (void)slot_alloc; + (void)slot_dealloc; + (void)slot_verify_access; + (void)slot_get_address; + (void)slot_get_base; + (void)slot_get_offset; + (void)slot_get_slot_size; +} + +void fsl_shw_init_keystore_default(fsl_shw_kso_t * keystore) +{ + (void)keystore; +} +fsl_shw_return_t fsl_shw_establish_keystore(fsl_shw_uco_t *user_ctx, + fsl_shw_kso_t *keystore) +{ + (void)user_ctx; + (void)keystore; + return FSL_RETURN_NO_RESOURCE_S; +} +void fsl_shw_release_keystore(fsl_shw_uco_t *user_ctx, + fsl_shw_kso_t *keystore) +{ + (void)user_ctx; + (void)keystore; + return; +} + +fsl_shw_return_t keystore_slot_alloc(fsl_shw_kso_t *keystore, uint32_t size, + uint64_t owner_id, uint32_t *slot) +{ + (void)keystore; + (void)size; + (void)owner_id; + (void)slot; + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t keystore_slot_dealloc(fsl_shw_kso_t *keystore, + uint64_t owner_id, uint32_t slot) +{ + (void)keystore; + (void)owner_id; + (void)slot; + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t +keystore_slot_load(fsl_shw_kso_t *keystore, uint64_t owner_id, uint32_t slot, + const uint8_t *key_data, uint32_t key_length) +{ + (void)keystore; + (void)owner_id; + (void)slot; + (void)key_data; + (void)key_length; + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t +keystore_slot_read(fsl_shw_kso_t * keystore, uint64_t owner_id, uint32_t slot, + uint32_t key_length, uint8_t * key_data) +{ + (void)keystore; + (void)owner_id; + (void)slot; + (void)key_length; + (void)key_data; + + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t +keystore_slot_decrypt(fsl_shw_uco_t *user_ctx, fsl_shw_kso_t *keystore, + uint64_t owner_id, uint32_t slot, uint32_t length, + const uint8_t *source) +{ + (void)user_ctx; + (void)keystore; + (void)owner_id; + (void)slot; + (void)length; + (void)source; + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t +keystore_slot_encrypt(fsl_shw_uco_t *user_ctx, fsl_shw_kso_t *keystore, + uint64_t owner_id, uint32_t slot, uint32_t length, + uint8_t *destination) +{ + (void)user_ctx; + (void)keystore; + (void)owner_id; + (void)slot; + (void)length; + (void)destination; + return FSL_RETURN_NO_RESOURCE_S; +} + + +#endif /* FSL_HAVE_SCC2 */ + +/***** Default keystore implementation **************************************/ + +#ifdef FSL_HAVE_SCC2 + fsl_shw_return_t shw_kso_init_data(fsl_shw_uco_t *user_ctx, + void **user_data) +{ + int retval = FSL_RETURN_ERROR_S; + keystore_data_t *keystore_data = NULL; + fsl_shw_pco_t *capabilities = fsl_shw_get_capabilities(user_ctx); + uint32_t partition_size; + uint32_t slot_count; + uint32_t keystore_data_size; + uint8_t UMID[16] = { + 0x42, 0, 0, 0, 0x43, 0, 0, 0, 0x19, 0, 0, 0, 0x59, 0, 0, 0}; + uint32_t permissions = + FSL_PERM_TH_R | FSL_PERM_TH_W | FSL_PERM_HD_R | FSL_PERM_HD_W | + FSL_PERM_HD_X; + + /* Look up the size of a partition to see how big to make the keystore */ + partition_size = fsl_shw_pco_get_spo_size_bytes(capabilities); + + /* Calculate the required size of the keystore data structure, based on the + * number of keys that can fit in the partition. + */ + slot_count = partition_size / KEYSTORE_SLOT_SIZE; + keystore_data_size = + sizeof(keystore_data_t) + + slot_count * sizeof(keystore_data_slot_info_t); + +#ifdef __KERNEL__ + keystore_data = os_alloc_memory(keystore_data_size, GFP_KERNEL); + +#else + keystore_data = malloc(keystore_data_size); + +#endif + if (keystore_data == NULL) { + retval = FSL_RETURN_NO_RESOURCE_S; + goto out; + } + + /* Clear the memory (effectively clear all key assignments) */ + memset(keystore_data, 0, keystore_data_size); + + /* Place the slot information structure directly after the keystore data + * structure. + */ + keystore_data->slot = + (keystore_data_slot_info_t *) (keystore_data + 1); + keystore_data->slot_count = slot_count; + + /* Retrieve a secure partition to put the keystore in. */ + keystore_data->base_address = + fsl_shw_smalloc(user_ctx, partition_size, UMID, permissions); + if (keystore_data->base_address == NULL) { + retval = FSL_RETURN_NO_RESOURCE_S; + goto out; + } + *user_data = keystore_data; + retval = FSL_RETURN_OK_S; +out:if (retval != FSL_RETURN_OK_S) { + if (keystore_data != NULL) { + if (keystore_data->base_address != NULL) + fsl_shw_sfree(NULL, + keystore_data->base_address); + +#ifdef __KERNEL__ + os_free_memory(keystore_data); + +#else + free(keystore_data); + +#endif + } + } + return retval; +} +void shw_kso_cleanup_data(fsl_shw_uco_t *user_ctx, void **user_data) +{ + if (user_data != NULL) { + keystore_data_t * keystore_data = + (keystore_data_t *) (*user_data); + fsl_shw_sfree(user_ctx, keystore_data->base_address); + +#ifdef __KERNEL__ + os_free_memory(*user_data); + +#else + free(*user_data); + +#endif + } + return; +} + +fsl_shw_return_t shw_slot_verify_access(void *user_data, uint64_t owner_id, + uint32_t slot) +{ + keystore_data_t * data = user_data; + if (data->slot[slot].owner == owner_id) { + return FSL_RETURN_OK_S; + } else { + +#ifdef DIAG_DRV_IF + LOG_DIAG_ARGS("Access to slot %i fails.\n", slot); + +#endif + return FSL_RETURN_AUTH_FAILED_S; + } +} + +fsl_shw_return_t shw_slot_alloc(void *user_data, uint32_t size, + uint64_t owner_id, uint32_t *slot) +{ + keystore_data_t *data = user_data; + uint32_t i; + if (size > KEYSTORE_SLOT_SIZE) + return FSL_RETURN_BAD_KEY_LENGTH_S; + for (i = 0; i < data->slot_count; i++) { + if (data->slot[i].allocated == 0) { + data->slot[i].allocated = 1; + data->slot[i].owner = owner_id; + (*slot) = i; + +#ifdef DIAG_DRV_IF + LOG_DIAG_ARGS("Keystore: allocated slot %i. Slot " + "address: %p\n", + (*slot), + data->base_address + + (*slot) * KEYSTORE_SLOT_SIZE); + +#endif + return FSL_RETURN_OK_S; + } + } + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t shw_slot_dealloc(void *user_data, uint64_t owner_id, + uint32_t slot) +{ + keystore_data_t * data = user_data; + (void)owner_id; + (void)slot; + if (slot >= data->slot_count) + return FSL_RETURN_ERROR_S; + if (data->slot[slot].allocated == 1) { + /* Forcibly remove the data from the keystore */ + memset(shw_slot_get_address(user_data, slot), 0, + KEYSTORE_SLOT_SIZE); + data->slot[slot].allocated = 0; + return FSL_RETURN_OK_S; + } + return FSL_RETURN_ERROR_S; +} + +void *shw_slot_get_address(void *user_data, uint32_t slot) +{ + keystore_data_t * data = user_data; + if (slot >= data->slot_count) + return NULL; + return data->base_address + slot * KEYSTORE_SLOT_SIZE; +} + +uint32_t shw_slot_get_base(void *user_data, uint32_t slot) +{ + keystore_data_t * data = user_data; + + /* There could potentially be more than one secure partition object + * associated with this keystore. For now, there is just one. + */ + (void)slot; + return (uint32_t) (data->base_address); +} + +uint32_t shw_slot_get_offset(void *user_data, uint32_t slot) +{ + keystore_data_t *data = user_data; + if (slot >= data->slot_count) + return FSL_RETURN_ERROR_S; + return (slot * KEYSTORE_SLOT_SIZE); +} + +uint32_t shw_slot_get_slot_size(void *user_data, uint32_t slot) +{ + (void)user_data; + (void)slot; + + /* All slots are the same size in the default implementation */ + return KEYSTORE_SLOT_SIZE; +} + +#else /* FSL_HAVE_SCC2 */ + +#ifdef __KERNEL__ + fsl_shw_return_t shw_kso_init_data(fsl_shw_uco_t *user_ctx, + void **user_data) +{ + + /* The SCC does its own initialization. All that needs to be done here is + * make sure an SCC exists. + */ + *user_data = (void *)0xFEEDFEED; + return FSL_RETURN_OK_S; +} +void shw_kso_cleanup_data(fsl_shw_uco_t *user_ctx, void **user_data) +{ + + /* The SCC does its own cleanup. */ + *user_data = NULL; + return; +} + +fsl_shw_return_t shw_slot_verify_access(void *user_data, uint64_t owner_id, + uint32_t slot) +{ + + /* Zero is used for the size because the newer interface does bounds + * checking later. + */ + scc_return_t retval; + retval = scc_verify_slot_access(owner_id, slot, 0); + if (retval == SCC_RET_OK) { + return FSL_RETURN_OK_S; + } + return FSL_RETURN_AUTH_FAILED_S; +} + +fsl_shw_return_t shw_slot_alloc(void *user_data, uint32_t size, + uint64_t owner_id, uint32_t *slot) +{ + scc_return_t retval; + +#ifdef DIAG_DRV_IF + LOG_DIAG_ARGS("key length: %i, handle: %i\n", size, *slot); + +#endif + retval = scc_alloc_slot(size, owner_id, slot); + if (retval == SCC_RET_OK) + return FSL_RETURN_OK_S; + + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t shw_slot_dealloc(void *user_data, uint64_t owner_id, + uint32_t slot) +{ + scc_return_t retval; + retval = scc_dealloc_slot(owner_id, slot); + if (retval == SCC_RET_OK) + return FSL_RETURN_OK_S; + + return FSL_RETURN_ERROR_S; +} +void *shw_slot_get_address(void *user_data, uint32_t slot) +{ + uint64_t owner_id = *((uint64_t *) user_data); + uint32_t address; + uint32_t value_size_bytes; + uint32_t slot_size_bytes; + scc_return_t scc_ret; + scc_ret = + scc_get_slot_info(owner_id, slot, &address, &value_size_bytes, + &slot_size_bytes); + if (scc_ret == SCC_RET_OK) { + return (void *)address; + } + return NULL; +} + +uint32_t shw_slot_get_base(void *user_data, uint32_t slot) +{ + return 0; +} + +uint32_t shw_slot_get_offset(void *user_data, uint32_t slot) +{ + return 0; +} + + +/* Return the size of the key slot, in octets */ +uint32_t shw_slot_get_slot_size(void *user_data, uint32_t slot) +{ + uint64_t owner_id = *((uint64_t *) user_data); + uint32_t address; + uint32_t value_size_bytes; + uint32_t slot_size_bytes; + scc_return_t scc_ret; + scc_ret = + scc_get_slot_info(owner_id, slot, &address, &value_size_bytes, + &slot_size_bytes); + if (scc_ret == SCC_RET_OK) + return slot_size_bytes; + return 0; +} + + +#endif /* __KERNEL__ */ + +#endif /* FSL_HAVE_SCC2 */ + +/*****************************************************************************/ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/fsl_shw_rand.c linux-2.6.26-lab126/drivers/mxc/security/sahara2/fsl_shw_rand.c --- linux-2.6.26/drivers/mxc/security/sahara2/fsl_shw_rand.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/fsl_shw_rand.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,96 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file fsl_shw_rand.c + * + * This file implements Random Number Generation functions of the FSL SHW API + * for Sahara. + */ + +#include "sahara.h" +#include "sf_util.h" + +#ifdef __KERNEL__ +EXPORT_SYMBOL(fsl_shw_get_random); +#endif + +/* REQ-S2LRD-PINTFC-API-BASIC-RNG-002 */ +/*! + * Get a random number + * + * + * @param user_ctx + * @param length + * @param data + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data) +{ + SAH_SF_DCLS; + + /* perform a sanity check on the uco */ + ret = sah_validate_uco(user_ctx); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + header = SAH_HDR_RNG_GENERATE; /* Desc. #18 */ + DESC_OUT_OUT(header, length, data, 0, NULL); + + SAH_SF_EXECUTE(); + + out: + SAH_SF_DESC_CLEAN(); + + return ret; +} + +#ifdef __KERNEL__ +EXPORT_SYMBOL(fsl_shw_add_entropy); +#endif + +/*! + * Add entropy to a random number generator + + * @param user_ctx + * @param length + * @param data + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data) +{ + SAH_SF_DCLS; + + /* perform a sanity check on the uco */ + ret = sah_validate_uco(user_ctx); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + header = SAH_HDR_RNG_GENERATE; /* Desc. #18 */ + + /* create descriptor #18. Generate random data */ + DESC_IN_IN(header, 0, NULL, length, data) + + SAH_SF_EXECUTE(); + + out: + SAH_SF_DESC_CLEAN(); + + return ret; +} diff -urN linux-2.6.26/drivers/mxc/security/sahara2/fsl_shw_sym.c linux-2.6.26-lab126/drivers/mxc/security/sahara2/fsl_shw_sym.c --- linux-2.6.26/drivers/mxc/security/sahara2/fsl_shw_sym.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/fsl_shw_sym.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,281 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file fsl_shw_sym.c + * + * This file implements Symmetric Cipher functions of the FSL SHW API for + * Sahara. This does not include CCM. + */ + +#include "sahara.h" +#include "fsl_platform.h" + +#include "sf_util.h" +#include "adaptor.h" + +#ifdef LINUX_KERNEL +EXPORT_SYMBOL(fsl_shw_symmetric_encrypt); +EXPORT_SYMBOL(fsl_shw_symmetric_decrypt); +#endif + +#if defined(NEED_CTR_WORKAROUND) +/* CTR mode needs block-multiple data in/out */ +#define LENGTH_PATCH (sym_ctx->block_size_bytes) +#define LENGTH_PATCH_MASK (sym_ctx->block_size_bytes-1) +#else +#define LENGTH_PATCH 0 +#define LENGTH_PATCH_MASK 0 /* du not use! */ +#endif + +/*! + * Block of zeroes which is maximum Symmetric block size, used for + * initializing context register, etc. + */ +static uint32_t block_zeros[4] = { + 0, 0, 0, 0 +}; + +typedef enum cipher_direction { + SYM_DECRYPT, + SYM_ENCRYPT +} cipher_direction_t; + +/*! + * Create and run the chain for a symmetric-key operation. + * + * @param user_ctx Who the user is + * @param key_info What key is to be used + * @param sym_ctx Info details about algorithm + * @param encrypt 0 = decrypt, non-zero = encrypt + * @param length Number of octets at @a in and @a out + * @param in Pointer to input data + * @param out Location to store output data + * + * @return The status of handing chain to driver, + * or an earlier argument/flag or allocation + * error. + */ +static fsl_shw_return_t do_symmetric(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + cipher_direction_t encrypt, + uint32_t length, + const uint8_t * in, uint8_t * out) +{ + SAH_SF_DCLS; + uint8_t *sink = NULL; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + sah_Oct_Str ptr1; + uint32_t size1 = sym_ctx->block_size_bytes; + + SAH_SF_USER_CHECK(); + + /* Two different sets of chains, depending on algorithm */ + if (key_info->algorithm == FSL_KEY_ALG_ARC4) { + if (sym_ctx->flags & FSL_SYM_CTX_INIT) { + /* Desc. #35 w/ARC4 - start from key */ + header = SAH_HDR_ARC4_SET_MODE_KEY + ^ sah_insert_skha_algorithm_arc4; + + DESC_IN_KEY(header, 0, NULL, key_info); + } else { /* load SBox */ + /* Desc. #33 w/ARC4 and NO PERMUTE */ + header = SAH_HDR_ARC4_SET_MODE_SBOX + ^ sah_insert_skha_no_permute + ^ sah_insert_skha_algorithm_arc4; + DESC_IN_IN(header, 256, sym_ctx->context, + 3, sym_ctx->context + 256); + } /* load SBox */ + + /* Add in-out data descriptor to process the data */ + if (length != 0) { + DESC_IN_OUT(SAH_HDR_SKHA_ENC_DEC, length, in, length, + out); + } + + /* Operation is done ... save what came out? */ + if (sym_ctx->flags & FSL_SYM_CTX_SAVE) { + /* Desc. #34 - Read SBox, pointers */ + header = SAH_HDR_ARC4_READ_SBOX; + DESC_OUT_OUT(header, 256, sym_ctx->context, + 3, sym_ctx->context + 256); + } + } else { /* not ARC4 */ + /* Doing 1- or 2- descriptor chain. */ + /* Desc. #1 and algorithm and mode */ + header = SAH_HDR_SKHA_SET_MODE_IV_KEY + ^ sah_insert_skha_mode[sym_ctx->mode] + ^ sah_insert_skha_algorithm[key_info->algorithm]; + + /* Honor 'no key parity checking' for DES and TDES */ + if ((key_info->flags & FSL_SKO_KEY_IGNORE_PARITY) && + ((key_info->algorithm == FSL_KEY_ALG_DES) || + (key_info->algorithm == FSL_KEY_ALG_TDES))) { + header ^= sah_insert_skha_no_key_parity; + } + + /* Header by default is decrypting, so... */ + if (encrypt == SYM_ENCRYPT) { + header ^= sah_insert_skha_encrypt; + } + + if (sym_ctx->mode == FSL_SYM_MODE_CTR) { + header ^= sah_insert_skha_modulus[sym_ctx->modulus_exp]; + } + + if (sym_ctx->mode == FSL_SYM_MODE_ECB) { + ptr1 = NULL; + size1 = 0; + } else if (sym_ctx->flags & FSL_SYM_CTX_INIT) { + ptr1 = (uint8_t *) block_zeros; + } else { + ptr1 = sym_ctx->context; + } + + DESC_IN_KEY(header, sym_ctx->block_size_bytes, ptr1, key_info); + + /* Add in-out data descriptor */ + if (length != 0) { + header = SAH_HDR_SKHA_ENC_DEC; + if (LENGTH_PATCH && (sym_ctx->mode == FSL_SYM_MODE_CTR) + && ((length & LENGTH_PATCH_MASK) != 0)) { + sink = DESC_TEMP_ALLOC(LENGTH_PATCH); + ret = + sah_Create_Link(user_ctx->mem_util, &link1, + (uint8_t *) in, length, + SAH_USES_LINK_DATA); + ret = + sah_Append_Link(user_ctx->mem_util, link1, + (uint8_t *) sink, + LENGTH_PATCH - + (length & + LENGTH_PATCH_MASK), + SAH_USES_LINK_DATA); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + ret = + sah_Create_Link(user_ctx->mem_util, &link2, + out, length, + SAH_USES_LINK_DATA | + SAH_OUTPUT_LINK); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + ret = sah_Append_Link(user_ctx->mem_util, link2, + sink, + LENGTH_PATCH - + (length & + LENGTH_PATCH_MASK), + SAH_USES_LINK_DATA); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + ret = + sah_Append_Desc(user_ctx->mem_util, + &desc_chain, header, link1, + link2); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + link1 = link2 = NULL; + } else { + DESC_IN_OUT(header, length, in, length, out); + } + } + + /* Unload any desired context */ + if (sym_ctx->flags & FSL_SYM_CTX_SAVE) { + DESC_OUT_OUT(SAH_HDR_SKHA_READ_CONTEXT_IV, 0, NULL, + sym_ctx->block_size_bytes, + sym_ctx->context); + } + + } /* not ARC4 */ + + SAH_SF_EXECUTE(); + + out: + SAH_SF_DESC_CLEAN(); + DESC_TEMP_FREE(sink); + if (LENGTH_PATCH) { + sah_Destroy_Link(user_ctx->mem_util, link1); + sah_Destroy_Link(user_ctx->mem_util, link2); + } + + return ret; +} + +/* REQ-S2LRD-PINTFC-API-BASIC-SYM-002 */ +/* PINTFC-API-BASIC-SYM-ARC4-001 */ +/* PINTFC-API-BASIC-SYM-ARC4-002 */ + +/*! + * Compute symmetric encryption + * + * + * @param user_ctx + * @param key_info + * @param sym_ctx + * @param length + * @param pt + * @param ct + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_symmetric_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * pt, uint8_t * ct) +{ + fsl_shw_return_t ret; + + ret = do_symmetric(user_ctx, key_info, sym_ctx, SYM_ENCRYPT, + length, pt, ct); + + return ret; +} + +/* PINTFC-API-BASIC-SYM-002 */ +/* PINTFC-API-BASIC-SYM-ARC4-001 */ +/* PINTFC-API-BASIC-SYM-ARC4-002 */ + +/*! + * Compute symmetric decryption + * + * + * @param user_ctx + * @param key_info + * @param sym_ctx + * @param length + * @param pt + * @param ct + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_symmetric_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * ct, uint8_t * pt) +{ + fsl_shw_return_t ret; + + ret = do_symmetric(user_ctx, key_info, sym_ctx, SYM_DECRYPT, + length, ct, pt); + + return ret; +} diff -urN linux-2.6.26/drivers/mxc/security/sahara2/fsl_shw_user.c linux-2.6.26-lab126/drivers/mxc/security/sahara2/fsl_shw_user.c --- linux-2.6.26/drivers/mxc/security/sahara2/fsl_shw_user.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/fsl_shw_user.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,137 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file fsl_shw_user.c + * + * This file implements user and platform capabilities functions of the FSL SHW + * API for Sahara + */ +#include "sahara.h" +#include +#include + +#ifdef __KERNEL__ +EXPORT_SYMBOL(fsl_shw_get_capabilities); +EXPORT_SYMBOL(fsl_shw_register_user); +EXPORT_SYMBOL(fsl_shw_deregister_user); +EXPORT_SYMBOL(fsl_shw_get_results); +#endif /* __KERNEL__ */ + +struct cap_t { + unsigned populated; + union { + uint32_t buffer[sizeof(fsl_shw_pco_t)]; + fsl_shw_pco_t pco; + }; +}; + +static struct cap_t cap = { + 0, + {} +}; + +/* REQ-S2LRD-PINTFC-API-GEN-003 */ +/*! + * Determine the hardware security capabilities of this platform. + * + * Though a user context object is passed into this function, it will always + * act in a non-blocking manner. + * + * @param user_ctx The user context which will be used for the query. + * + * @return A pointer to the capabilities object. + */ +fsl_shw_pco_t *fsl_shw_get_capabilities(fsl_shw_uco_t * user_ctx) +{ + fsl_shw_pco_t *retval = NULL; + + if (cap.populated) { + retval = &cap.pco; + } else { + if (get_capabilities(user_ctx, &cap.pco) == FSL_RETURN_OK_S) { + cap.populated = 1; + retval = &cap.pco; + } + } + return retval; +} + +/* REQ-S2LRD-PINTFC-API-GEN-004 */ + +/*! + * Create an association between the the user and the provider of the API. + * + * @param user_ctx The user context which will be used for this association. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_register_user(fsl_shw_uco_t * user_ctx) +{ + return sah_register(user_ctx); +} + +/* REQ-S2LRD-PINTFC-API-GEN-005 */ + +/*! + * Destroy the association between the the user and the provider of the API. + * + * @param user_ctx The user context which is no longer needed. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_deregister_user(fsl_shw_uco_t * user_ctx) +{ + return sah_deregister(user_ctx); +} + +/* REQ-S2LRD-PINTFC-API-GEN-006 */ + +/*! + * Retrieve results from earlier operations. + * + * @param user_ctx The user's context. + * @param result_size The number of array elements of @a results. + * @param[in,out] results Pointer to first of the (array of) locations to + * store results. + * @param[out] result_count Pointer to store the number of results which + * were returned. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_get_results(fsl_shw_uco_t * user_ctx, + unsigned result_size, + fsl_shw_result_t results[], + unsigned *result_count) +{ + fsl_shw_return_t status; + + /* perform a sanity check on the uco */ + status = sah_validate_uco(user_ctx); + + /* if uco appears ok, build structure and pass to get results */ + if (status == FSL_RETURN_OK_S) { + sah_results arg; + + /* if requested is zero, it's done before it started */ + if (result_size > 0) { + arg.requested = result_size; + arg.actual = result_count; + arg.results = results; + /* get the results */ + status = sah_get_results(&arg, user_ctx); + } + } + + return status; +} diff -urN linux-2.6.26/drivers/mxc/security/sahara2/fsl_shw_wrap.c linux-2.6.26-lab126/drivers/mxc/security/sahara2/fsl_shw_wrap.c --- linux-2.6.26/drivers/mxc/security/sahara2/fsl_shw_wrap.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/fsl_shw_wrap.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,967 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file fsl_shw_wrap.c + * + * This file implements Key-Wrap (Black Key) functions of the FSL SHW API for + * Sahara. + * + * - Ownerid is an 8-byte, user-supplied, value to keep KEY confidential. + * - KEY is a 1-32 byte value which starts in SCC RED RAM before + * wrapping, and ends up there on unwrap. Length is limited because of + * size of SCC1 RAM. + * - KEY' is the encrypted KEY + * - LEN is a 1-byte (for now) byte-length of KEY + * - ALG is a 1-byte value for the algorithm which which the key is + * associated. Values are defined by the FSL SHW API + * - Ownerid, LEN, and ALG come from the user's "key_info" object, as does the + * slot number where KEY already is/will be. + * - T is a Nonce + * - T' is the encrypted T + * - KEK is a Key-Encryption Key for the user's Key + * - ICV is the "Integrity Check Value" for the wrapped key + * - Black Key is the string of bytes returned as the wrapped key + + + + + + + + + + + + + + + + + + +
BLACK_KEY =ICV | T' | LEN | ALG | + KEY'
 
To Wrap
T = RND()16 +
KEK=HASHsha256(T | + Ownerid)16
KEY'= + AESctr-enc(Key=KEK, CTR=0, Data=KEY)
ICV=HMACsha256 + (Key=T, Data=Ownerid | LEN | ALG | KEY')16
T'=TDEScbc-enc + (Key=SLID, IV=Ownerid, Data=T)
 
To Unwrap
T=TDESecb-dec + (Key=SLID, IV=Ownerid, Data=T')
ICV=HMACsha256 + (Key=T, Data=Ownerid | LEN | ALG | KEY')16
KEK=HASHsha256 + (T | Ownerid)16
KEY=AESctr-dec + (Key=KEK, CTR=0, Data=KEY')
+ + */ + +#include "sahara.h" +#include "fsl_platform.h" +#include "fsl_shw_keystore.h" + +#include "sf_util.h" +#include "adaptor.h" + +#if defined(DIAG_SECURITY_FUNC) +#include +#endif + +#if defined(NEED_CTR_WORKAROUND) +/* CTR mode needs block-multiple data in/out */ +#define LENGTH_PATCH 16 +#define LENGTH_PATCH_MASK 0xF +#else +#define LENGTH_PATCH 4 +#define LENGTH_PATCH_MASK 3 +#endif + +#if LENGTH_PATCH +#define ROUND_LENGTH(len) \ +({ \ + uint32_t orig_len = len; \ + uint32_t new_len; \ + \ + if ((orig_len & LENGTH_PATCH_MASK) != 0) { \ + new_len = (orig_len + LENGTH_PATCH \ + - (orig_len & LENGTH_PATCH_MASK)); \ + } \ + else { \ + new_len = orig_len; \ + } \ + new_len; \ +}) +#else +#define ROUND_LENGTH(len) (len) +#endif + +#ifdef __KERNEL__ +EXPORT_SYMBOL(fsl_shw_establish_key); +EXPORT_SYMBOL(fsl_shw_extract_key); +EXPORT_SYMBOL(fsl_shw_release_key); +EXPORT_SYMBOL(fsl_shw_read_key); +#endif + +#define ICV_LENGTH 16 +#define T_LENGTH 16 +#define KEK_LENGTH 16 +#define LENGTH_LENGTH 1 +#define ALGORITHM_LENGTH 1 +#define FLAGS_LENGTH 1 + +/* ICV | T' | LEN | ALG | KEY' */ +#define ICV_OFFSET 0 +#define T_PRIME_OFFSET (ICV_OFFSET + ICV_LENGTH) +#define LENGTH_OFFSET (T_PRIME_OFFSET + T_LENGTH) +#define ALGORITHM_OFFSET (LENGTH_OFFSET + LENGTH_LENGTH) +#define FLAGS_OFFSET (ALGORITHM_OFFSET + ALGORITHM_LENGTH) +#define KEY_PRIME_OFFSET (FLAGS_OFFSET + FLAGS_LENGTH) +#define FLAGS_SW_KEY 0x01 + +/* + * For testing of the algorithm implementation,, the DO_REPEATABLE_WRAP flag + * causes the T_block to go into the T field during a wrap operation. This + * will make the black key value repeatable (for a given SCC secret key, or + * always if the default key is in use). + * + * Normally, a random sequence is used. + */ +#ifdef DO_REPEATABLE_WRAP +/*! + * Block of zeroes which is maximum Symmetric block size, used for + * initializing context register, etc. + */ +static uint8_t T_block_[16] = { + 0x42, 0, 0, 0x42, 0x42, 0, 0, 0x42, + 0x42, 0, 0, 0x42, 0x42, 0, 0, 0x42 +}; +#endif + +/*! + * Insert descriptors to calculate ICV = HMAC(key=T, data=LEN|ALG|KEY') + * + * @param user_ctx User's context for this operation + * @param desc_chain Descriptor chain to append to + * @param t_key_info T's key object + * @param black_key Beginning of Black Key region + * @param key_length Number of bytes of key' there are in @c black_key + * @param[out] hmac Location to store ICV. Will be tagged "USES" so + * sf routines will not try to free it. + * + * @return A return code of type #fsl_shw_return_t. + */ +static inline fsl_shw_return_t create_icv_calc(fsl_shw_uco_t * user_ctx, + sah_Head_Desc ** desc_chain, + fsl_shw_sko_t * t_key_info, + const uint8_t * black_key, + uint32_t key_length, + uint8_t * hmac) +{ + fsl_shw_return_t sah_code; + uint32_t header; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + + /* Load up T as key for the HMAC */ + header = (SAH_HDR_MDHA_SET_MODE_MD_KEY /* #6 */ + ^ sah_insert_mdha_algorithm_sha256 + ^ sah_insert_mdha_init ^ sah_insert_mdha_hmac ^ + sah_insert_mdha_pdata ^ sah_insert_mdha_mac_full); + sah_code = sah_add_in_key_desc(header, NULL, 0, t_key_info, /* Reference T in RED */ + user_ctx->mem_util, desc_chain); + if (sah_code != FSL_RETURN_OK_S) { + goto out; + } + + /* Previous step loaded key; Now set up to hash the data */ + header = SAH_HDR_MDHA_HASH; /* #10 */ + + /* Input - start with ownerid */ + sah_code = sah_Create_Link(user_ctx->mem_util, &link1, + (void *)&t_key_info->userid, + sizeof(t_key_info->userid), + SAH_USES_LINK_DATA); + if (sah_code != FSL_RETURN_OK_S) { + goto out; + } + + /* Still input - Append black-key fields len, alg, key' */ + sah_code = sah_Append_Link(user_ctx->mem_util, link1, + (void *)black_key + LENGTH_OFFSET, + (LENGTH_LENGTH + + ALGORITHM_LENGTH + + key_length), SAH_USES_LINK_DATA); + + if (sah_code != FSL_RETURN_OK_S) { + goto out; + } + /* Output - computed ICV/HMAC */ + sah_code = sah_Create_Link(user_ctx->mem_util, &link2, + hmac, ICV_LENGTH, + SAH_USES_LINK_DATA | SAH_OUTPUT_LINK); + if (sah_code != FSL_RETURN_OK_S) { + goto out; + } + + sah_code = sah_Append_Desc(user_ctx->mem_util, desc_chain, + header, link1, link2); + + out: + if (sah_code != FSL_RETURN_OK_S) { + (void)sah_Destroy_Link(user_ctx->mem_util, link1); + (void)sah_Destroy_Link(user_ctx->mem_util, link2); + } + + return sah_code; +} /* create_icv_calc */ + +/*! + * Perform unwrapping of a black key into a RED slot + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] key_info The information about the key to be which will + * be unwrapped... key length, slot info, etc. + * @param black_key Encrypted key + * + * @return A return code of type #fsl_shw_return_t. + */ +static fsl_shw_return_t unwrap(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + const uint8_t * black_key) +{ + SAH_SF_DCLS; + uint8_t *hmac = NULL; + fsl_shw_sko_t t_key_info; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + unsigned i; + unsigned rounded_key_length; + unsigned original_key_length = key_info->key_length; + + hmac = DESC_TEMP_ALLOC(ICV_LENGTH); + + /* Set up key_info for "T" - use same slot as eventual key */ + fsl_shw_sko_init(&t_key_info, FSL_KEY_ALG_AES); + t_key_info.userid = key_info->userid; + t_key_info.handle = key_info->handle; + t_key_info.flags = key_info->flags; + t_key_info.key_length = T_LENGTH; + t_key_info.keystore = key_info->keystore; + + /* Validate SW flags to prevent misuse */ + if ((key_info->flags & FSL_SKO_KEY_SW_KEY) + && !(black_key[FLAGS_OFFSET] & FLAGS_SW_KEY)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + /* Compute T = SLID_decrypt(T'); leave in RED slot */ + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_decrypt(user_ctx, + key_info->userid, + t_key_info.handle, + T_LENGTH, + black_key + T_PRIME_OFFSET); + + } else { + /* Key goes in user keystore */ + ret = keystore_slot_decrypt(user_ctx, + key_info->keystore, + key_info->userid, + t_key_info.handle, + T_LENGTH, + black_key + T_PRIME_OFFSET); + } + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + /* Compute ICV = HMAC(T, ownerid | len | alg | key' */ + ret = create_icv_calc(user_ctx, &desc_chain, &t_key_info, + black_key, original_key_length, hmac); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Creation of sah_Key_Link failed due to bad key" + " flag!\n"); +#endif /*DIAG_SECURITY_FUNC */ + goto out; + } +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Validating MAC of wrapped key"); +#endif + SAH_SF_EXECUTE(); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + SAH_SF_DESC_CLEAN(); + + /* Check computed ICV against value in Black Key */ + for (i = 0; i < ICV_LENGTH; i++) { + if (black_key[ICV_OFFSET + i] != hmac[i]) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("computed ICV fails at offset %i\n", i); + + { + char buff[300]; + int a; + for (a = 0; a < ICV_LENGTH; a++) + sprintf(&(buff[a * 2]), "%02x", + black_key[ICV_OFFSET + a]); + buff[a * 2 + 1] = 0; + LOG_DIAG_ARGS("black key: %s", buff); + + for (a = 0; a < ICV_LENGTH; a++) + sprintf(&(buff[a * 2]), "%02x", + hmac[a]); + buff[a * 2 + 1] = 0; + LOG_DIAG_ARGS("hmac: %s", buff); + } +#endif + ret = FSL_RETURN_AUTH_FAILED_S; + goto out; + } + } + + /* This is no longer needed. */ + DESC_TEMP_FREE(hmac); + + /* Compute KEK = SHA256(T | ownerid). Rewrite slot with value */ + header = (SAH_HDR_MDHA_SET_MODE_HASH /* #8 */ + ^ sah_insert_mdha_init + ^ sah_insert_mdha_algorithm_sha256 ^ sah_insert_mdha_pdata); + + /* Input - Start with T */ + ret = sah_Create_Key_Link(user_ctx->mem_util, &link1, &t_key_info); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + /* Still input - append ownerid */ + ret = sah_Append_Link(user_ctx->mem_util, link1, + (void *)&key_info->userid, + sizeof(key_info->userid), SAH_USES_LINK_DATA); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + /* Output - KEK goes into RED slot */ + ret = sah_Create_Key_Link(user_ctx->mem_util, &link2, &t_key_info); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + /* Put the Hash calculation into the chain. */ + ret = sah_Append_Desc(user_ctx->mem_util, &desc_chain, + header, link1, link2); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + /* Compute KEY = AES-decrypt(KEK, KEY') */ + header = (SAH_HDR_SKHA_SET_MODE_IV_KEY /* #1 */ + ^ sah_insert_skha_mode_ctr + ^ sah_insert_skha_algorithm_aes + ^ sah_insert_skha_modulus_128); + /* Load KEK in as the key to use */ + DESC_IN_KEY(header, 0, NULL, &t_key_info); + + rounded_key_length = ROUND_LENGTH(original_key_length); + key_info->key_length = rounded_key_length; + + /* Now set up for computation. Result in RED */ + header = SAH_HDR_SKHA_ENC_DEC; /* #4 */ + DESC_IN_KEY(header, rounded_key_length, black_key + KEY_PRIME_OFFSET, + key_info); + + /* Perform the operation */ +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Decrypting key with KEK"); +#endif + SAH_SF_EXECUTE(); + + out: + key_info->key_length = original_key_length; + SAH_SF_DESC_CLEAN(); + + DESC_TEMP_FREE(hmac); + + /* Erase tracks */ + t_key_info.userid = 0xdeadbeef; + t_key_info.handle = 0xdeadbeef; + + return ret; +} /* unwrap */ + +/*! + * Perform wrapping of a black key from a RED slot + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] key_info The information about the key to be which will + * be wrapped... key length, slot info, etc. + * @param black_key Place to store encrypted key + * + * @return A return code of type #fsl_shw_return_t. + */ +static fsl_shw_return_t wrap(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, uint8_t * black_key) +{ + SAH_SF_DCLS; + unsigned slots_allocated = 0; /* boolean */ + fsl_shw_sko_t T_key_info; /* for holding T */ + fsl_shw_sko_t KEK_key_info; /* for holding KEK */ + unsigned original_key_length = key_info->key_length; + unsigned rounded_key_length; + sah_Link *link1; + sah_Link *link2; + + black_key[LENGTH_OFFSET] = key_info->key_length; + black_key[ALGORITHM_OFFSET] = key_info->algorithm; + + memcpy(&T_key_info, key_info, sizeof(T_key_info)); + fsl_shw_sko_set_key_length(&T_key_info, T_LENGTH); + T_key_info.algorithm = FSL_KEY_ALG_HMAC; + + memcpy(&KEK_key_info, &T_key_info, sizeof(KEK_key_info)); + KEK_key_info.algorithm = FSL_KEY_ALG_AES; + + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_alloc(user_ctx, + T_LENGTH, key_info->userid, + &T_key_info.handle); + + } else { + /* Key goes in user keystore */ + ret = keystore_slot_alloc(key_info->keystore, + T_LENGTH, + key_info->userid, &T_key_info.handle); + } + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_alloc(user_ctx, + KEK_LENGTH, key_info->userid, + &KEK_key_info.handle); + + } else { + /* Key goes in user keystore */ + ret = keystore_slot_alloc(key_info->keystore, + KEK_LENGTH, key_info->userid, + &KEK_key_info.handle); + } + + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("do_scc_slot_alloc() failed"); +#endif + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + (void)do_system_keystore_slot_dealloc(user_ctx, + key_info->userid, T_key_info.handle); + + } else { + /* Key goes in user keystore */ + (void)keystore_slot_dealloc(key_info->keystore, + key_info->userid, T_key_info.handle); + } + } else { + slots_allocated = 1; + } + + /* Set up to compute everything except T' ... */ +#ifndef DO_REPEATABLE_WRAP + /* Compute T = RND() */ + header = SAH_HDR_RNG_GENERATE; /* Desc. #18 */ + DESC_KEY_OUT(header, &T_key_info, 0, NULL); +#else + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_load(user_ctx, + T_key_info.userid, + T_key_info.handle, T_block, + T_key_info.key_length); + } else { + /* Key goes in user keystore */ + ret = keystore_slot_load(key_info->keystore, + T_key_info.userid, + T_key_info.handle, + T_block, T_key_info.key_length); + } + + if (ret != FSL_RETURN_OK_S) { + goto out; + } +#endif + + /* Compute KEK = SHA256(T | Ownerid) */ + header = (SAH_HDR_MDHA_SET_MODE_HASH /* #8 */ + ^ sah_insert_mdha_init + ^ sah_insert_mdha_algorithm[FSL_HASH_ALG_SHA256] + ^ sah_insert_mdha_pdata); + /* Input - Start with T */ + ret = sah_Create_Key_Link(user_ctx->mem_util, &link1, &T_key_info); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + /* Still input - append ownerid */ + ret = sah_Append_Link(user_ctx->mem_util, link1, + (void *)&key_info->userid, + sizeof(key_info->userid), SAH_USES_LINK_DATA); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + /* Output - KEK goes into RED slot */ + ret = sah_Create_Key_Link(user_ctx->mem_util, &link2, &KEK_key_info); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + /* Put the Hash calculation into the chain. */ + ret = sah_Append_Desc(user_ctx->mem_util, &desc_chain, + header, link1, link2); + if (ret != FSL_RETURN_OK_S) { + goto out; + } +#if defined(NEED_CTR_WORKAROUND) + rounded_key_length = ROUND_LENGTH(original_key_length); + key_info->key_length = rounded_key_length; +#else + rounded_key_length = original_key_length; +#endif + /* Compute KEY' = AES-encrypt(KEK, KEY) */ + header = (SAH_HDR_SKHA_SET_MODE_IV_KEY /* #1 */ + ^ sah_insert_skha_mode[FSL_SYM_MODE_CTR] + ^ sah_insert_skha_algorithm[FSL_KEY_ALG_AES] + ^ sah_insert_skha_modulus[FSL_CTR_MOD_128]); + /* Set up KEK as key to use */ + DESC_IN_KEY(header, 0, NULL, &KEK_key_info); + header = SAH_HDR_SKHA_ENC_DEC; + DESC_KEY_OUT(header, key_info, + key_info->key_length, black_key + KEY_PRIME_OFFSET); + + /* Set up flags info */ + black_key[FLAGS_OFFSET] = 0; + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + black_key[FLAGS_OFFSET] |= FLAGS_SW_KEY; + } + + /* Compute and store ICV into Black Key */ + ret = create_icv_calc(user_ctx, &desc_chain, &T_key_info, + black_key, original_key_length, + black_key + ICV_OFFSET); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Creation of sah_Key_Link failed due to bad key" + " flag!\n"); +#endif /*DIAG_SECURITY_FUNC */ + goto out; + } + + /* Now get Sahara to do the work. */ +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Encrypting key with KEK"); +#endif + SAH_SF_EXECUTE(); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("sah_Descriptor_Chain_Execute() failed"); +#endif + goto out; + } + + /* Compute T' = SLID_encrypt(T); Result goes to Black Key */ + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_encrypt(user_ctx, + T_key_info.userid, T_key_info.handle, + T_LENGTH, black_key + T_PRIME_OFFSET); + } else { + /* Key goes in user keystore */ + ret = keystore_slot_encrypt(user_ctx, + key_info->keystore, + T_key_info.userid, + T_key_info.handle, + T_LENGTH, + black_key + T_PRIME_OFFSET); + } + + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("do_scc_slot_encrypt() failed"); +#endif + goto out; + } + + out: + key_info->key_length = original_key_length; + + SAH_SF_DESC_CLEAN(); + if (slots_allocated) { + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + (void)do_system_keystore_slot_dealloc(user_ctx, + key_info->userid, + T_key_info. + handle); + (void)do_system_keystore_slot_dealloc(user_ctx, + key_info->userid, + KEK_key_info. + handle); + } else { + /* Key goes in user keystore */ + (void)keystore_slot_dealloc(key_info->keystore, + key_info->userid, + T_key_info.handle); + (void)keystore_slot_dealloc(key_info->keystore, + key_info->userid, + KEK_key_info.handle); + } + } + + return ret; +} /* wrap */ + +/*! + * Place a key into a protected location for use only by cryptographic + * algorithms. + * + * This only needs to be used to a) unwrap a key, or b) set up a key which + * could be wrapped with a later call to #fsl_shw_extract_key(). Normal + * cleartext keys can simply be placed into #fsl_shw_sko_t key objects with + * #fsl_shw_sko_set_key() and used directly. + * + * The maximum key size supported for wrapped/unwrapped keys is 32 octets. + * (This is the maximum reasonable key length on Sahara - 32 octets for an HMAC + * key based on SHA-256.) The key size is determined by the @a key_info. The + * expected length of @a key can be determined by + * #fsl_shw_sko_calculate_wrapped_size() + * + * The protected key will not be available for use until this operation + * successfully completes. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] key_info The information about the key to be which will + * be established. In the create case, the key + * length must be set. + * @param establish_type How @a key will be interpreted to establish a + * key for use. + * @param key If @a establish_type is #FSL_KEY_WRAP_UNWRAP, + * this is the location of a wrapped key. If + * @a establish_type is #FSL_KEY_WRAP_CREATE, this + * parameter can be @a NULL. If @a establish_type + * is #FSL_KEY_WRAP_ACCEPT, this is the location + * of a plaintext key. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_establish_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_key_wrap_t establish_type, + const uint8_t * key) +{ + SAH_SF_DCLS; + unsigned original_key_length = key_info->key_length; + unsigned rounded_key_length; + unsigned slot_allocated = 0; + uint32_t old_flags; + + header = SAH_HDR_RNG_GENERATE; /* Desc. #18 for rand */ + + /* TODO: THIS STILL NEEDS TO BE REFACTORED */ + + /* Write operations into SCC memory require word-multiple number of + * bytes. For ACCEPT and CREATE functions, the key length may need + * to be rounded up. Calculate. */ + if (LENGTH_PATCH && (original_key_length & LENGTH_PATCH_MASK) != 0) { + rounded_key_length = original_key_length + LENGTH_PATCH + - (original_key_length & LENGTH_PATCH_MASK); + } else { + rounded_key_length = original_key_length; + } + + SAH_SF_USER_CHECK(); + + if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) { +#ifdef DIAG_SECURITY_FUNC + ret = FSL_RETURN_BAD_FLAG_S; + LOG_DIAG("Key already established\n"); +#endif + } + + + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_alloc(user_ctx, + key_info->key_length, + key_info->userid, + &(key_info->handle)); +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS + ("key length: %i, handle: %i, rounded key length: %i", + key_info->key_length, key_info->handle, + rounded_key_length); +#endif + + } else { + /* Key goes in user keystore */ + ret = keystore_slot_alloc(key_info->keystore, + key_info->key_length, + key_info->userid, + &(key_info->handle)); + } + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Slot allocation failed\n"); +#endif + goto out; + } + slot_allocated = 1; + + key_info->flags |= FSL_SKO_KEY_ESTABLISHED; + switch (establish_type) { + case FSL_KEY_WRAP_CREATE: +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Creating random key\n"); +#endif + /* Use safe version of key length */ + key_info->key_length = rounded_key_length; + /* Generate descriptor to put random value into */ + DESC_KEY_OUT(header, key_info, 0, NULL); + /* Restore actual, desired key length */ + key_info->key_length = original_key_length; + + old_flags = user_ctx->flags; + /* Now put random value into key */ + SAH_SF_EXECUTE(); + /* Restore user's old flag value */ + user_ctx->flags = old_flags; +#ifdef DIAG_SECURITY_FUNC + if (ret == FSL_RETURN_OK_S) { + LOG_DIAG("ret is ok"); + } else { + LOG_DIAG("ret is not ok"); + } +#endif + break; + + case FSL_KEY_WRAP_ACCEPT: +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Accepting plaintext key\n"); +#endif + if (key == NULL) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("ACCEPT: Red Key is NULL"); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + /* Copy in safe number of bytes of Red key */ + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_load(user_ctx, + key_info->userid, + key_info->handle, key, + rounded_key_length); + } else { + /* Key goes in user keystore */ + ret = keystore_slot_load(key_info->keystore, + key_info->userid, + key_info->handle, key, + key_info->key_length); + } + break; + + case FSL_KEY_WRAP_UNWRAP: +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Unwrapping wrapped key\n"); +#endif + /* For now, disallow non-blocking calls. */ + if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) { + ret = FSL_RETURN_BAD_FLAG_S; + } else if (key == NULL) { + ret = FSL_RETURN_ERROR_S; + } else { + ret = unwrap(user_ctx, key_info, key); + } + break; + + default: + ret = FSL_RETURN_BAD_FLAG_S; + break; + } /* switch */ + + out: + if (slot_allocated && (ret != FSL_RETURN_OK_S)) { + fsl_shw_return_t scc_err; + + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + scc_err = do_system_keystore_slot_dealloc(user_ctx, + key_info->userid, + key_info->handle); + } else { + /* Key goes in user keystore */ + scc_err = keystore_slot_dealloc(key_info->keystore, + key_info->userid, key_info->handle); + } + + key_info->flags &= ~FSL_SKO_KEY_ESTABLISHED; + } + + SAH_SF_DESC_CLEAN(); + + return ret; +} /* fsl_shw_establish_key() */ + +/*! + * Wrap a key and retrieve the wrapped value. + * + * A wrapped key is a key that has been cryptographically obscured. It is + * only able to be used with #fsl_shw_establish_key(). + * + * This function will also release the key (see #fsl_shw_release_key()) so + * that it must be re-established before reuse. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The information about the key to be deleted. + * @param[out] covered_key The location to store the 48-octet wrapped key. + * (This size is based upon the maximum key size + * of 32 octets). + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + uint8_t * covered_key) +{ + SAH_SF_DCLS; + + SAH_SF_USER_CHECK(); + + /* For now, only blocking mode calls are supported */ + if (user_ctx->flags & FSL_UCO_BLOCKING_MODE) { + if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) { + ret = wrap(user_ctx, key_info, covered_key); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + /* Verify that a SW key info really belongs to a SW key */ + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + /* ret = FSL_RETURN_BAD_FLAG_S; + goto out;*/ + } + + /* Need to deallocate on successful extraction */ + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_dealloc(user_ctx, + key_info->userid, key_info->handle); + } else { + /* Key goes in user keystore */ + ret = keystore_slot_dealloc(key_info->keystore, + key_info->userid, key_info->handle); + } + /* Mark key not available in the flags */ + key_info->flags &= + ~(FSL_SKO_KEY_ESTABLISHED | FSL_SKO_KEY_PRESENT); + } + } + +out: + SAH_SF_DESC_CLEAN(); + + return ret; +} + +/*! + * De-establish a key so that it can no longer be accessed. + * + * The key will need to be re-established before it can again be used. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The information about the key to be deleted. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_release_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info) +{ + SAH_SF_DCLS; + + SAH_SF_USER_CHECK(); + + if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) { + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + do_system_keystore_slot_dealloc(user_ctx, + key_info->userid, + key_info->handle); + } else { + /* Key goes in user keystore */ + keystore_slot_dealloc(key_info->keystore, + key_info->userid, + key_info->handle); + } + key_info->flags &= ~(FSL_SKO_KEY_ESTABLISHED | + FSL_SKO_KEY_PRESENT); + } + +out: + SAH_SF_DESC_CLEAN(); + + return ret; +} + +fsl_shw_return_t fsl_shw_read_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, uint8_t * key) +{ + SAH_SF_DCLS; + + SAH_SF_USER_CHECK(); + + if (!(key_info->flags & FSL_SKO_KEY_ESTABLISHED) + || !(key_info->flags & FSL_SKO_KEY_SW_KEY)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + if (key_info->keystore == NULL) { + /* Key lives in system keystore */ + ret = do_system_keystore_slot_read(user_ctx, + key_info->userid, + key_info->handle, + key_info->key_length, key); + } else { + /* Key lives in user keystore */ + ret = keystore_slot_read(key_info->keystore, + key_info->userid, + key_info->handle, + key_info->key_length, key); + } + + out: + SAH_SF_DESC_CLEAN(); + + return ret; +} diff -urN linux-2.6.26/drivers/mxc/security/sahara2/include/adaptor.h linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/adaptor.h --- linux-2.6.26/drivers/mxc/security/sahara2/include/adaptor.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/adaptor.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,113 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! +* @file adaptor.h +* +* @brief The Adaptor component provides an interface to the device +* driver. +* +* Intended to be used by the FSL SHW API, this can also be called directly +*/ + +#ifndef ADAPTOR_H +#define ADAPTOR_H + +#include + +/*! + * Structure passed during user ioctl() call to submit request. + */ +typedef struct sah_dar { + sah_Desc *desc_addr; /*!< head of descriptor chain */ + uint32_t uco_flags; /*!< copy of fsl_shw_uco flags field */ + uint32_t uco_user_ref; /*!< copy of fsl_shw_uco user_ref */ + uint32_t result; /*!< result of descriptor chain request */ + struct sah_dar *next; /*!< for driver use */ +} sah_dar_t; + +/*! + * Structure passed during user ioctl() call to Register a user + */ +typedef struct sah_register { + uint32_t pool_size; /*!< max number of outstanding requests possible */ + uint32_t result; /*!< result of registration request */ +} sah_register_t; + +/*! + * Structure passed during ioctl() call to request SCC operation + */ +typedef struct scc_data { + uint32_t length; /*!< length of data */ + uint8_t *in; /*!< input data */ + uint8_t *out; /*!< output data */ + unsigned direction; /*!< encrypt or decrypt */ + fsl_shw_sym_mode_t crypto_mode; /*!< CBC or EBC */ + uint8_t *init_vector; /*!< initialization vector or NULL */ +} scc_data_t; + +/*! + * Structure passed during user ioctl() calls to manage stored keys and + * stored-key slots. + */ +typedef struct scc_slot_t { + uint64_t ownerid; /*!< Owner's id to check/set permissions */ + uint32_t key_length; /*!< Length of key */ + uint32_t slot; /*!< Slot to operation on, or returned slot + number. */ + uint8_t *key; /*!< User-memory pointer to key value */ + fsl_shw_return_t code; /*!< API return code from operation */ +} scc_slot_t; + +/* + * Structure passed during user ioctl() calls to manage data stored in secure + * partitions. + */ +typedef struct scc_region_t { + uint32_t partition_base; /*!< User virtual address of the + partition base. */ + uint32_t offset; /*!< Offset from the start of the + partition where the cleartext data + is located. */ + uint32_t length; /*!< Length of the region to be + operated on */ + uint8_t *black_data; /*!< User virtual address of any black + (encrypted) data. */ + fsl_shw_cypher_mode_t cypher_mode; /*!< Cypher mode to use in an encryt/ + decrypt operation. */ + uint32_t IV[4]; /*!< Intialization vector to use in an + encrypt/decrypt operation. */ + fsl_shw_return_t code; /*!< API return code from operation */ +} scc_region_t; + +/* + * Structure passed during user ioctl() calls to manage secure partitions. + */ +typedef struct scc_partition_info_t { + uint32_t user_base; /**< Userspace pointer to base of partition */ + uint32_t permissions; /**< Permissions to give the partition (only + used in call to _DROP_PERMS) */ + fsl_shw_partition_status_t status; /*!< Status of the partition */ +} scc_partition_info_t; + +fsl_shw_return_t adaptor_Exec_Descriptor_Chain(sah_Head_Desc * dar, + fsl_shw_uco_t * uco); +fsl_shw_return_t sah_get_results(sah_results * arg, fsl_shw_uco_t * uco); +fsl_shw_return_t sah_register(fsl_shw_uco_t * user_ctx); +fsl_shw_return_t sah_deregister(fsl_shw_uco_t * user_ctx); +fsl_shw_return_t get_capabilities(fsl_shw_uco_t * user_ctx, + fsl_shw_pco_t *capabilities); + +#endif /* ADAPTOR_H */ + +/* End of adaptor.h */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/include/diagnostic.h linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/diagnostic.h --- linux-2.6.26/drivers/mxc/security/sahara2/include/diagnostic.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/diagnostic.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,116 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! +* @file diagnostic.h +* +* @brief Macros for outputting kernel and user space diagnostics. +*/ + +#ifndef DIAGNOSTIC_H +#define DIAGNOSTIC_H + +#ifndef __KERNEL__ /* linux flag */ +#include +#endif +#include "fsl_platform.h" + +#if defined(FSL_HAVE_SAHARA2) || defined(FSL_HAVE_SAHARA4) +#define DEV_NAME "sahara" +#elif defined(FSL_HAVE_RNGA) || defined(FSL_HAVE_RNGB) || \ + defined(FSL_HAVE_RNGC) +#define DEV_NAME "shw" +#endif + +/*! +******************************************************************** +* @brief This macro logs diagnostic messages to stderr. +* +* @param diag String that must be logged, char *. +* +* @return void +* +*/ +//#if defined DIAG_SECURITY_FUNC || defined DIAG_ADAPTOR +#define LOG_DIAG(diag) \ +({ \ + const char* fname = strrchr(__FILE__, '/'); \ + \ + sah_Log_Diag(fname ? fname+1 : __FILE__, __LINE__, diag); \ +}) + +#ifdef __KERNEL__ + +#define LOG_DIAG_ARGS(fmt, ...) \ +({ \ + const char* fname = strrchr(__FILE__, '/'); \ + os_printk(KERN_ALERT "%s:%i: " fmt "\n", \ + fname ? fname+1 : __FILE__, \ + __LINE__, \ + __VA_ARGS__); \ +}) + +#else + +#define LOG_DIAG_ARGS(fmt, ...) \ +({ \ + const char* fname = strrchr(__FILE__, '/'); \ + printf("%s:%i: " fmt "\n", \ + fname ? fname+1 : __FILE__, \ + __LINE__, \ + __VA_ARGS__); \ +}) + +#ifndef __KERNEL__ +void sah_Log_Diag(char *source_name, int source_line, char *diag); +#endif +#endif /* if define DIAG_SECURITY_FUNC ... */ + +#ifdef __KERNEL__ +/*! +******************************************************************** +* @brief This macro logs kernel diagnostic messages to the kernel +* log. +* +* @param diag String that must be logged, char *. +* +* @return As for printf() +*/ +#if 0 +#if defined(DIAG_DRV_IF) || defined(DIAG_DRV_QUEUE) || \ + defined(DIAG_DRV_STATUS) || defined(DIAG_DRV_INTERRUPT) || \ + defined(DIAG_MEM) || defined(DIAG_SECURITY_FUNC) || defined(DIAG_ADAPTOR) +#endif +#endif + +#define LOG_KDIAG_ARGS(fmt, ...) \ +({ \ + os_printk (KERN_ALERT "%s (%s:%i): " fmt "\n", \ + DEV_NAME, strrchr(__FILE__, '/')+1, __LINE__, __VA_ARGS__); \ +}) + +#define LOG_KDIAG(diag) \ + os_printk (KERN_ALERT "%s (%s:%i): %s\n", \ + DEV_NAME, strrchr(__FILE__, '/')+1, __LINE__, diag); + +#define sah_Log_Diag(n, l, d) \ + os_printk(KERN_ALERT "%s:%i: %s\n", n, l, d) + +#else /* not KERNEL */ + +#define sah_Log_Diag(n, l, d) \ + printf("%s:%i: %s\n", n, l, d) + +#endif /* __KERNEL__ */ + +#endif /* DIAGNOSTIC_H */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/include/fsl_platform.h linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/fsl_platform.h --- linux-2.6.26/drivers/mxc/security/sahara2/include/fsl_platform.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/fsl_platform.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,161 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file fsl_platform.h + * + * Header file to isolate code which might be platform-dependent + */ + +#ifndef FSL_PLATFORM_H +#define FSL_PLATFORM_H + +#ifdef __KERNEL__ +#include "portable_os.h" +#endif + +#if defined(FSL_PLATFORM_OTHER) + +/* Have Makefile or other method of setting FSL_HAVE_* flags */ + +#elif defined(CONFIG_ARCH_MX3) /* i.MX31 */ + +#define FSL_HAVE_SCC +#define FSL_HAVE_RTIC +#define FSL_HAVE_RNGA + +#elif defined(CONFIG_ARCH_MX21) + +#define FSL_HAVE_HAC +#define FSL_HAVE_RNGA +#define FSL_HAVE_SCC + +#elif defined(CONFIG_ARCH_MX25) + +#define FSL_HAVE_SCC +#define FSL_HAVE_RNGB +#define FSL_HAVE_RTIC3 +#define FSL_HAVE_DRYICE + +#elif defined(CONFIG_ARCH_MX27) + +#define FSL_HAVE_SAHARA2 +#define SUBMIT_MULTIPLE_DARS +#define FSL_HAVE_RTIC +#define FSL_HAVE_SCC +#define ALLOW_LLO_DESCRIPTORS + +#elif defined(CONFIG_ARCH_MX35) + +#define FSL_HAVE_SCC +#define FSL_HAVE_RNGC +#define FSL_HAVE_RTIC + +#elif defined(CONFIG_ARCH_MX37) + +#define FSL_HAVE_SCC2 +#define FSL_HAVE_RNGC +#define FSL_HAVE_RTIC2 +#define FSL_HAVE_SRTC + +#elif defined(CONFIG_ARCH_MX51) + +#define FSL_HAVE_SCC2 +#define FSL_HAVE_SAHARA4 +#define FSL_HAVE_RTIC3 +#define FSL_HAVE_SRTC +#define NO_RESEED_WORKAROUND +#define NEED_CTR_WORKAROUND +#define USE_S2_CCM_ENCRYPT_CHAIN +#define USE_S2_CCM_DECRYPT_CHAIN +#define ALLOW_LLO_DESCRIPTORS + +#elif defined(CONFIG_ARCH_MXC91131) + +#define FSL_HAVE_SCC +#define FSL_HAVE_RNGC +#define FSL_HAVE_HAC + +#elif defined(CONFIG_ARCH_MXC91221) + +#define FSL_HAVE_SCC +#define FSL_HAVE_RNGC +#define FSL_HAVE_RTIC2 + +#elif defined(CONFIG_ARCH_MXC91231) + +#define FSL_HAVE_SAHARA2 +#define FSL_HAVE_RTIC +#define FSL_HAVE_SCC +#define NO_OUTPUT_1K_CROSSING + +#elif defined(CONFIG_ARCH_MXC91311) + +#define FSL_HAVE_SCC +#define FSL_HAVE_RNGC + +#elif defined(CONFIG_ARCH_MXC91314) + +#define FSL_HAVE_SCC +#define FSL_HAVE_SAHAR4 +#define FSL_HAVE_RTIC3 +#define NO_RESEED_WORKAROUND +#define NEED_CTR_WORKAROUND +#define USE_S2_CCM_ENCRYPT_CHAIN +#define USE_S2_CCM_DECRYPT_CHAIN +#define ALLOW_LLO_DESCRIPTORS + +#elif defined(CONFIG_ARCH_MXC91321) + +#define FSL_HAVE_SAHARA2 +#define FSL_HAVE_RTIC +#define FSL_HAVE_SCC +#define SCC_CLOCK_NOT_GATED +#define NO_OUTPUT_1K_CROSSING + +#elif defined(CONFIG_ARCH_MXC92323) + +#define FSL_HAVE_SCC2 +#define FSL_HAVE_SAHARA4 +#define FSL_HAVE_PKHA +#define FSL_HAVE_RTIC2 +#define NO_1K_CROSSING +#define NO_RESEED_WORKAROUND +#define NEED_CTR_WORKAROUND +#define USE_S2_CCM_ENCRYPT_CHAIN +#define USE_S2_CCM_DECRYPT_CHAIN +#define ALLOW_LLO_DESCRIPTORS + + +#elif defined(CONFIG_ARCH_MXC91331) + +#define FSL_HAVE_SCC +#define FSL_HAVE_RNGA +#define FSL_HAVE_HAC +#define FSL_HAVE_RTIC + +#elif defined(CONFIG_8548) + +#define FSL_HAVE_SEC2x + +#elif defined(CONFIG_MPC8374) + +#define FSL_HAVE_SEC3x + +#else + +#error UNKNOWN_PLATFORM + +#endif /* platform checks */ + +#endif /* FSL_PLATFORM_H */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/include/fsl_shw.h linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/fsl_shw.h --- linux-2.6.26/drivers/mxc/security/sahara2/include/fsl_shw.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/fsl_shw.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,2515 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * NOTE TO MAINTAINERS: Although this header file is *the* header file to be + * #include'd by FSL SHW programs, it does not itself make any definitions for + * the API. Instead, it uses the fsl_platform.h file and / or compiler + * environment variables to determine which actual driver header file to + * include. This allows different implementations to contain different + * implementations of the various objects, macros, etc., or even to change + * which functions are macros and which are not. + */ + +/*! + * @file fsl_shw.h + * + * @brief Definition of the Freescale Security Hardware API. + * + * See @ref index for an overview of the API. + */ + +/*! + * @if USE_MAINPAGE + * @mainpage Common API for Freescale Security Hardware (FSL SHW API) + * @endif + * + * @section intro_sec Introduction + * + * This is the interface definition for the Freescale Security Hardware API + * (FSL SHW API) for User Mode and Kernel Mode to access Freescale Security + * Hardware components for cryptographic acceleration. The API is intended to + * provide cross-platform access to security hardware components of Freescale. + * + * This documentation has not been approved, and should not be taken to + * mean anything definite about future direction. + * + * Some example code is provided to give some idea of usage of this API. + * + * Note: This first version has been defined around the capabilities of the + * Sahara2 cryptographic accelerator, and may be expanded in the future to + * provide support for other platforms. The Platform Capabilities Object is + * intended as a way to allow programs to adapt to different platforms. + * + * The i.MX25 is an example of a platform without a SAHARA but yet has + * capabilities supported by this API. These include #fsl_shw_get_random() and + * #fsl_shw_add_entropy(), and the use of Triple-DES (TDEA) cipher algorithm + * (with no checking of key parity supported) in ECB and CBC modes with @ref + * sym_sec. See also the @ref di_sec for information on key handling, and @ref + * td_sec for detection of Tamper Events. Only the random functions are + * available from user space on this platform. + * + * @section usr_ctx The User Context + * + * The User Context Object (#fsl_shw_uco_t) controls the interaction between + * the user program and the API. It is initialized as part of user + * registration (#fsl_shw_register_user()), and is part of every interaction + * thereafter. + * + * @section pf_sec Platform Capabilities + * + * Since this API is not tied to one specific type of hardware or even one + * given version of a given type of hardware, the platform capabilities object + * could be used by a portable program to make choices about using software + * instead of hardware for certain operations. + * + * See the #fsl_shw_pco_t, returned by #fsl_shw_get_capabilities(). + * + * @ref pcoops are provided to query its contents. + * + * + * @section sym_sec Symmetric-Key Encryption and Decryption + * + * Symmetric-Key encryption support is provided for the block cipher algorithms + * AES, DES, and Triple DES. Modes supported are #FSL_SYM_MODE_ECB, + * #FSL_SYM_MODE_CBC, and #FSL_SYM_MODE_CTR, though not necessarily all modes + * for all algorithms. There is also support for the stream cipher algorithm + * commonly known as ARC4. + * + * Encryption and decryption are performed by using the functions + * #fsl_shw_symmetric_encrypt() and #fsl_shw_symmetric_decrypt(), respectively. + * There are two objects which provide information about the operation of these + * functions. They are the #fsl_shw_sko_t, to provide key and algorithm + * information; and the #fsl_shw_scco_t, to provide (and store) initial context + * or counter value information. + * + * CCM is not supported by these functions. For information CCM support, see + * @ref cmb_sec. + * + * + * @section hash_sec Cryptographic Hashing + * + * Hashing is performed by fsl_shw_hash(). Control of the function is through + * flags in the #fsl_shw_hco_t. The algorithms which are + * supported are listed in #fsl_shw_hash_alg_t. + * + * The hashing function works on octet streams. If a user application needs to + * hash a bitstream, it will need to do its own padding of the last block. + * + * + * @section hmac_sec Hashed Message Authentication Codes + * + * An HMAC is a method of combining a hash and a key so that a message cannot + * be faked by a third party. + * + * The #fsl_shw_hmac() can be used by itself for one-shot or multi-step + * operations, or in combination with #fsl_shw_hmac_precompute() to provide the + * ability to compute and save the beginning hashes from a key one time, and + * then use #fsl_shw_hmac() to calculate an HMAC on each message as it is + * processed. + * + * The maximum key length which is directly supported by this API is 64 octets. + * If a longer key size is needed for HMAC, the user will have to hash the key + * and present the digest value as the key to be used by the HMAC functions. + * + * + * @section rnd_sec Random Numbers + * + * Support is available for acquiring random values from a + * cryptographically-strong random number generator. See + * #fsl_shw_get_random(). The function #fsl_shw_add_entropy() may be used to + * add entropy to the random number generator. + * + * + * @section cmb_sec Combined Cipher and Authentication + * + * Some schemes require that messages be encrypted and that they also have an + * authentication code associated with the message. The function + * #fsl_shw_gen_encrypt() will generate the authentication code and encrypt the + * message. + * + * Upon receipt of such a message, the message must be decrypted and the + * authentication code validated. The function + * #fsl_shw_auth_decrypt() will perform these steps. + * + * Only AES-CCM is supported. + * + * + * @section wrap_sec Wrapped Keys + * + * On platforms with a Secure Memory, the function #fsl_shw_establish_key() can + * be used to place a key into the System Keystore. This key then can be used + * directly by the cryptographic hardware. It later then be wrapped + * (cryptographically obscured) by #fsl_shw_extract_key() and stored for later + * use. If a software key (#FSL_SKO_KEY_SW_KEY) was established, then its + * value can be retrieved with a call to #fsl_shw_read_key(). + * + * The wrapping and unwrapping functions provide security against unauthorized + * use and detection of tampering. + * + * The functions can also be used with a User Keystore. + * + * @section smalloc_sec Secure Memory Allocation + * + * On platforms with multiple partitions of Secure Memory, the function + * #fsl_shw_smalloc() can be used to acquire a partition for private use. The + * function #fsl_shw_diminish_perms() can then be used to revoke specific + * permissions on the partition, and #fsl_shw_sfree() can be used to release the + * partition. + * + * @section keystore_sec User Keystore + * + * User Keystore functionality is defined in fsl_shw_keystore.h. See @ref + * user_keystore for details. This is not supported on platforms without SCC2. + * + * @section di_sec Hardware key-select extensions - DryIce + * + * Some platforms have a component called DryIce which allows the software to + * control which key will be used by the secure memory encryption hardware. + * The choices are the secret per-chip Fused (IIM) Key, an unknown, hardware- + * generated Random Key, a software-written Programmed Key, or the IIM Key in + * combination with one of the others. #fsl_shw_pco_check_pk_supported() can + * be used to determine whether this feature is available on the platform. + * The rest of this section will explain the symmetric ciphering and key + * operations which are available on such a platform. + * + * The function #fsl_shw_sko_init_pf_key() will set up a Secret Key Object to + * refer to one of the system's platform keys. All keys which reference a + * platform key must use this initialization function, including a user- + * provided key value. Keys which are intended for software encryption must + * use #fsl_shw_sko_init(). + * + * To change the setting of the Programmed Key of the DryIce module, + * #fsl_shw_establish_key() must be called with a platform key object of type + * #FSL_SHW_PF_KEY_PRG or #FSL_SHW_PF_KEY_IIM_PRG. The key will be go + * into the PK register of DryIce and not to the keystore. Any symmetric + * operation which references either #FSL_SHW_PF_KEY_PRG or + * #FSL_SHW_PF_KEY_IIM_PRG will use the current PK value (possibly modified by + * the secret fused IIM key). Before the Flatform Key can be changed, a call to + * #fsl_shw_release_key() or #fsl_shw_extract_key() must be made. Neither + * function will change the value in the PK registers, and further ciphering + * can take place. + * + * When #fsl_shw_establish_key() is called to change the PK value, a plaintext + * key can be passed in with the #FSL_KEY_WRAP_ACCEPT argument or a previously + * wrapped key can be passed in with the #FSL_KEY_WRAP_UNWRAP argument. If + * #FSL_KEY_WRAP_CREATE is passed in, then a random value will be loaded into + * the PK register. The PK value can be wrapped by a call to + * #fsl_shw_extract_key() for later use with the #FSL_KEY_WRAP_UNWRAP argument. + * + * As an alternative to using only the fused key for @ref wrap_sec, + * #fsl_shw_uco_set_wrap_key() can be used to select either the random key or + * the random key with the fused key as the key which will be used to protect + * the one-time value used to wrap the key. This allows for these + * wrapped keys to be dependent upon and therefore unrecoverable after a tamper + * event causes the erasure of the DryIce Random Key register. + * + * The software can request that the hardware generate a (new) Random Key for + * DryIce by calling #fsl_shw_gen_random_pf_key(). + * + * + * @section td_sec Device Tamper-Detection + * + * Some platforms have a component which can detect certain types of tampering + * with the hardware. #fsl_shw_read_tamper_event() API will allow the + * retrieval of the type of event which caused a tamper-detection failure. + * + */ + +/*! @defgroup glossary Glossary + * + * @li @b AES - Advanced Encryption Standard - An NIST-created block cipher + * originally knowns as Rijndael. + * @li @b ARC4 - ARCFOUR - An S-Box-based OFB mode stream cipher. + * @li @b CBC - Cipher-Block Chaining - Each encrypted block is XORed with the + * result of the previous block's encryption. + * @li @b CCM - A way of combining CBC and CTR to perform cipher and + * authentication. + * @li @b ciphertext - @a plaintext which has been encrypted in some fashion. + * @li @b context - Information on the state of a cryptographic operation, + * excluding any key. This could include IV, Counter Value, or SBox. + * @li @b CTR - A mode where a counter value is encrypted and then XORed with + * the data. After each block, the counter value is incremented. + * @li @b DES - Data Encryption Standard - An 8-octet-block cipher. + * @li @b ECB - Electronic Codebook - A straight encryption/decryption of the + * data. + * @li @b hash - A cryptographically strong one-way function performed on data. + * @li @b HMAC - Hashed Message Authentication Code - A key-dependent one-way + * hash result, used to verify authenticity of a message. The equation + * for an HMAC is hash((K + A) || hash((K + B) || msg)), where K is the + * key, A is the constant for the outer hash, B is the constant for the + * inner hash, and hash is the hashing function (MD5, SHA256, etc). + * @li @b IPAD - In an HMAC operation, the context generated by XORing the key + * with a constant and then hashing that value as the first block of the + * inner hash. + * @li @b IV - An "Initial Vector" or @a context for modes like CBC. + * @li @b MAC - A Message Authentication Code. HMAC, hashing, and CCM all + * produce a MAC. + * @li @b mode - A way of using a cryptographic algorithm. See ECB, CBC, etc. + * @li @b MD5 - Message Digest 5 - A one-way hash function. + * @li @b plaintext - Data which has not been encrypted, or has been decrypted + * from @a ciphertext. + * @li @b OPAD - In an HMAC operation, the context generated by XORing the key + * with a constant and then hashing that value as the first block of the + * outer hash. + * @li @b SHA - Secure Hash Algorithm - A one-way hash function. + * @li @b TDES - AKA @b 3DES - Triple Data Encryption Standard - A method of + * using two or three keys and DES to perform three operations (encrypt + * decrypt encrypt) to create a new algorithm. + * @li @b XOR - Exclusive-OR. A Boolean arithmetic function. + * @li @b Wrapped value - A (key) which has been encrypted into an opaque datum + * which cannot be unwrapped (decrypted) for use except by an authorized + * user. Once created, the key is never visible, but may be used for + * other cryptographic operations. + */ + +#ifndef FSL_SHW_H +#define FSL_SHW_H + +/* Set FSL_HAVE_* flags */ + +#include "fsl_platform.h" + +#ifndef API_DOC + +#if defined(FSL_HAVE_SAHARA2) || defined(FSL_HAVE_SAHARA4) + +#include "sahara.h" + +#else + +#if defined(FSL_HAVE_RNGA) || defined(FSL_HAVE_RNGB) || defined(FSL_HAVE_RNGC) + +#include "rng_driver.h" + +#else + +#error FSL_SHW_API_platform_not_recognized + +#endif + +#endif /* HAVE SAHARA */ + +#else /* API_DOC */ + +#include /* for uint32_t, etc. */ +#include /* Mainly for definition of NULL !! */ + +/* These groups will appear in the order in which they are defined. */ + +/*! + * @defgroup strgrp Objects + * + * These objects are used to pass information into and out of the API. Through + * flags and other settings, they control the behavior of the @ref opfuns. + * + * They are manipulated and queried by use of the various access functions. + * There are different sets defined for each object. See @ref objman. + */ + +/*! + * @defgroup consgrp Enumerations and other Constants + * + * This collection of symbols comprise the values which can be passed into + * various functions to control how the API will work. + */ + +/*! @defgroup opfuns Operational Functions + * + * These functions request that the underlying hardware perform cryptographic + * operations. They are the heart of the API. + */ + +/****** Organization the Object Operations under one group ! **********/ +/*! @defgroup objman Object-Manipulation Operations + * + */ +/*! @addtogroup objman + @{ */ +/*! + * @defgroup pcoops Platform Context Object Operations + * + * The Platform Context object is "read-only", so only query operations are + * provided for it. It is returned by the #fsl_shw_get_capabilities() + * function. + */ + +/*! @defgroup ucoops User Context Operations + * + * These operations should be the only access to the #fsl_shw_uco_t + * type/struct, as the internal members of the object are subject to change. + * The #fsl_shw_uco_init() function must be called before any other use of the + * object. + */ + +/*! + * @defgroup rops Result Object Operations + * + * As the Result Object contains the result of one of the @ref opfuns. The + * manipulations provided are query-only. No initialization is needed for this + * object. + */ + +/*! + * @defgroup skoops Secret Key Object Operations + * + * These operations should be the only access to the #fsl_shw_sko_t + * type/struct, as the internal members of that object are subject to change. + */ + +/*! + * @defgroup ksoops Keystore Object Operations + * + * These operations should be the only access to the #fsl_shw_kso_t + * type/struct, as the internal members of that object are subject to change. + */ + +/*! + * @defgroup hcops Hash Context Object Operations + * + * These operations should be the only access to the #fsl_shw_hco_t + * type/struct, as the internal members of that object are subject to change. + */ + +/*! + * @defgroup hmcops HMAC Context Object Operations + * + * These operations should be the only access to the #fsl_shw_hmco_t + * type/struct, as the internal members of that object are subject to change. + */ + +/*! + * @defgroup sccops Symmetric Cipher Context Operations + * + * These operations should be the only access to the #fsl_shw_scco_t + * type/struct, as the internal members of that object are subject to change + */ + +/*! @defgroup accoops Authentication-Cipher Context Object Operations + * + * These functions operate on a #fsl_shw_acco_t. Their purpose is to set + * flags, fields, etc., in order to control the operation of + * #fsl_shw_gen_encrypt() and #fsl_shw_auth_decrypt(). + */ + + /* @} *//************ END GROUPING of Object Manipulations *****************/ + +/*! @defgroup miscfuns Miscellaneous Functions + * + * These functions are neither @ref opfuns nor @ref objman. Their behavior + * does not depend upon the flags in the #fsl_shw_uco_t, yet they may involve + * more interaction with the library and the kernel than simply querying an + * object. + */ + +/****************************************************************************** + * Enumerations + *****************************************************************************/ +/*! @addtogroup consgrp + @{ */ + +/*! + * Flags for the state of the User Context Object (#fsl_shw_uco_t). + * + * These flags describe how the @ref opfuns will operate. + */ +typedef enum fsl_shw_user_ctx_flags_t { + /*! + * API will block the caller until operation completes. The result will be + * available in the return code. If this is not set, user will have to get + * results using #fsl_shw_get_results(). + */ + FSL_UCO_BLOCKING_MODE, + /*! + * User wants callback (at the function specified with + * #fsl_shw_uco_set_callback()) when the operation completes. This flag is + * valid only if #FSL_UCO_BLOCKING_MODE is not set. + */ + FSL_UCO_CALLBACK_MODE, + /*! Do not free descriptor chain after driver (adaptor) finishes */ + FSL_UCO_SAVE_DESC_CHAIN, + /*! + * User has made at least one request with callbacks requested, so API is + * ready to handle others. + */ + FSL_UCO_CALLBACK_SETUP_COMPLETE, + /*! + * (virtual) pointer to descriptor chain is completely linked with physical + * (DMA) addresses, ready for the hardware. This flag should not be used + * by FSL SHW API programs. + */ + FSL_UCO_CHAIN_PREPHYSICALIZED, + /*! + * The user has changed the context but the changes have not been copied to + * the kernel driver. + */ + FSL_UCO_CONTEXT_CHANGED, + /*! Internal Use. This context belongs to a user-mode API user. */ + FSL_UCO_USERMODE_USER, +} fsl_shw_user_ctx_flags_t; + +/*! + * Return code for FSL_SHW library. + * + * These codes may be returned from a function call. In non-blocking mode, + * they will appear as the status in a Result Object. + */ +typedef enum fsl_shw_return_t { + /*! + * No error. As a function return code in Non-blocking mode, this may + * simply mean that the operation was accepted for eventual execution. + */ + FSL_RETURN_OK_S = 0, + /*! Failure for non-specific reason. */ + FSL_RETURN_ERROR_S, + /*! + * Operation failed because some resource was not able to be allocated. + */ + FSL_RETURN_NO_RESOURCE_S, + /*! Crypto algorithm unrecognized or improper. */ + FSL_RETURN_BAD_ALGORITHM_S, + /*! Crypto mode unrecognized or improper. */ + FSL_RETURN_BAD_MODE_S, + /*! Flag setting unrecognized or inconsistent. */ + FSL_RETURN_BAD_FLAG_S, + /*! Improper or unsupported key length for algorithm. */ + FSL_RETURN_BAD_KEY_LENGTH_S, + /*! Improper parity in a (DES, TDES) key. */ + FSL_RETURN_BAD_KEY_PARITY_S, + /*! + * Improper or unsupported data length for algorithm or internal buffer. + */ + FSL_RETURN_BAD_DATA_LENGTH_S, + /*! Authentication / Integrity Check code check failed. */ + FSL_RETURN_AUTH_FAILED_S, + /*! A memory error occurred. */ + FSL_RETURN_MEMORY_ERROR_S, + /*! An error internal to the hardware occurred. */ + FSL_RETURN_INTERNAL_ERROR_S, + /*! ECC detected Point at Infinity */ + FSL_RETURN_POINT_AT_INFINITY_S, + /*! ECC detected No Point at Infinity */ + FSL_RETURN_POINT_NOT_AT_INFINITY_S, + /*! GCD is One */ + FSL_RETURN_GCD_IS_ONE_S, + /*! GCD is not One */ + FSL_RETURN_GCD_IS_NOT_ONE_S, + /*! Candidate is Prime */ + FSL_RETURN_PRIME_S, + /*! Candidate is not Prime */ + FSL_RETURN_NOT_PRIME_S, + /*! N register loaded improperly with even value */ + FSL_RETURN_EVEN_MODULUS_ERROR_S, + /*! Divisor is zero. */ + FSL_RETURN_DIVIDE_BY_ZERO_ERROR_S, + /*! Bad Exponent or Scalar value for Point Multiply */ + FSL_RETURN_BAD_EXPONENT_ERROR_S, + /*! RNG hardware problem. */ + FSL_RETURN_OSCILLATOR_ERROR_S, + /*! RNG hardware problem. */ + FSL_RETURN_STATISTICS_ERROR_S, +} fsl_shw_return_t; + +/*! + * Algorithm Identifier. + * + * Selection of algorithm will determine how large the block size of the + * algorithm is. Context size is the same length unless otherwise specified. + * Selection of algorithm also affects the allowable key length. + */ +typedef enum fsl_shw_key_alg_t { + FSL_KEY_ALG_HMAC, /*!< Key will be used to perform an HMAC. Key + size is 1 to 64 octets. Block size is 64 + octets. */ + FSL_KEY_ALG_AES, /*!< Advanced Encryption Standard (Rijndael). + Block size is 16 octets. Key size is 16 + octets. (The single choice of key size is a + Sahara platform limitation.) */ + FSL_KEY_ALG_DES, /*!< Data Encryption Standard. Block size is + 8 octets. Key size is 8 octets. */ + FSL_KEY_ALG_TDES, /*!< 2- or 3-key Triple DES. Block size is 8 + octets. Key size is 16 octets for 2-key + Triple DES, and 24 octets for 3-key. */ + FSL_KEY_ALG_ARC4 /*!< ARC4. No block size. Context size is 259 + octets. Allowed key size is 1-16 octets. + (The choices for key size are a Sahara + platform limitation.) */ +} fsl_shw_key_alg_t; + +/*! + * Mode selector for Symmetric Ciphers. + * + * The selection of mode determines how a cryptographic algorithm will be + * used to process the plaintext or ciphertext. + * + * For all modes which are run block-by-block (that is, all but + * #FSL_SYM_MODE_STREAM), any partial operations must be performed on a text + * length which is multiple of the block size. Except for #FSL_SYM_MODE_CTR, + * these block-by-block algorithms must also be passed a total number of octets + * which is a multiple of the block size. + * + * In modes which require that the total number of octets of data be a multiple + * of the block size (#FSL_SYM_MODE_ECB and #FSL_SYM_MODE_CBC), and the user + * has a total number of octets which are not a multiple of the block size, the + * user must perform any necessary padding to get to the correct data length. + */ +typedef enum fsl_shw_sym_mode_t { + /*! + * Stream. There is no associated block size. Any request to process data + * may be of any length. This mode is only for ARC4 operations, and is + * also the only mode used for ARC4. + */ + FSL_SYM_MODE_STREAM, + + /*! + * Electronic Codebook. Each block of data is encrypted/decrypted. The + * length of the data stream must be a multiple of the block size. This + * mode may be used for DES, 3DES, and AES. The block size is determined + * by the algorithm. + */ + FSL_SYM_MODE_ECB, + /*! + * Cipher-Block Chaining. Each block of data is encrypted/decrypted and + * then "chained" with the previous block by an XOR function. Requires + * context to start the XOR (previous block). This mode may be used for + * DES, 3DES, and AES. The block size is determined by the algorithm. + */ + FSL_SYM_MODE_CBC, + /*! + * Counter. The counter is encrypted, then XORed with a block of data. + * The counter is then incremented (using modulus arithmetic) for the next + * block. The final operation may be non-multiple of block size. This mode + * may be used for AES. The block size is determined by the algorithm. + */ + FSL_SYM_MODE_CTR, +} fsl_shw_sym_mode_t; + +/*! + * Algorithm selector for Cryptographic Hash functions. + * + * Selection of algorithm determines how large the context and digest will be. + * Context is the same size as the digest (resulting hash), unless otherwise + * specified. + */ +typedef enum fsl_shw_hash_alg_t { + FSL_HASH_ALG_MD5, /*!< MD5 algorithm. Digest is 16 octets. */ + FSL_HASH_ALG_SHA1, /*!< SHA-1 (aka SHA or SHA-160) algorithm. + Digest is 20 octets. */ + FSL_HASH_ALG_SHA224, /*!< SHA-224 algorithm. Digest is 28 octets, + though context is 32 octets. */ + FSL_HASH_ALG_SHA256 /*!< SHA-256 algorithm. Digest is 32 + octets. */ +} fsl_shw_hash_alg_t; + +/*! + * The type of Authentication-Cipher function which will be performed. + */ +typedef enum fsl_shw_acc_mode_t { + /*! + * CBC-MAC for Counter. Requires context and modulus. Final operation may + * be non-multiple of block size. This mode may be used for AES. + */ + FSL_ACC_MODE_CCM, + /*! + * SSL mode. Not supported. Combines HMAC and encrypt (or decrypt). + * Needs one key object for encryption, another for the HMAC. The usual + * hashing and symmetric encryption algorithms are supported. + */ + FSL_ACC_MODE_SSL, +} fsl_shw_acc_mode_t; + +/*! + * The operation which controls the behavior of #fsl_shw_establish_key(). + * + * These values are passed to #fsl_shw_establish_key(). + */ +typedef enum fsl_shw_key_wrap_t { + FSL_KEY_WRAP_CREATE, /*!< Generate a key from random values. */ + FSL_KEY_WRAP_ACCEPT, /*!< Use the provided clear key. */ + FSL_KEY_WRAP_UNWRAP /*!< Unwrap a previously wrapped key. */ +} fsl_shw_key_wrap_t; + +/* REQ-S2LRD-PINTFC-COA-HCO-001 */ +/*! + * Flags which control a Hash operation. + * + * These may be combined by ORing them together. See #fsl_shw_hco_set_flags() + * and #fsl_shw_hco_clear_flags(). + */ +typedef enum fsl_shw_hash_ctx_flags_t { + FSL_HASH_FLAGS_INIT = 1, /*!< Context is empty. Hash is started + from scratch, with a message-processed + count of zero. */ + FSL_HASH_FLAGS_SAVE = 2, /*!< Retrieve context from hardware after + hashing. If used with the + #FSL_HASH_FLAGS_FINALIZE flag, the final + digest value will be saved in the + object. */ + FSL_HASH_FLAGS_LOAD = 4, /*!< Place context into hardware before + hashing. */ + FSL_HASH_FLAGS_FINALIZE = 8, /*!< PAD message and perform final digest + operation. If user message is + pre-padded, this flag should not be + used. */ +} fsl_shw_hash_ctx_flags_t; + +/*! + * Flags which control an HMAC operation. + * + * These may be combined by ORing them together. See #fsl_shw_hmco_set_flags() + * and #fsl_shw_hmco_clear_flags(). + */ +typedef enum fsl_shw_hmac_ctx_flags_t { + FSL_HMAC_FLAGS_INIT = 1, /*!< Message context is empty. HMAC is + started from scratch (with key) or from + precompute of inner hash, depending on + whether + #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT is + set. */ + FSL_HMAC_FLAGS_SAVE = 2, /*!< Retrieve ongoing context from hardware + after hashing. If used with the + #FSL_HMAC_FLAGS_FINALIZE flag, the final + digest value (HMAC) will be saved in the + object. */ + FSL_HMAC_FLAGS_LOAD = 4, /*!< Place ongoing context into hardware + before hashing. */ + FSL_HMAC_FLAGS_FINALIZE = 8, /*!< PAD message and perform final HMAC + operations of inner and outer hashes. */ + FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT = 16 /*!< This means that the context + contains precomputed inner and outer + hash values. */ +} fsl_shw_hmac_ctx_flags_t; + +/*! + * Flags to control use of the #fsl_shw_scco_t. + * + * These may be ORed together to get the desired effect. + * See #fsl_shw_scco_set_flags() and #fsl_shw_scco_clear_flags() + */ +typedef enum fsl_shw_sym_ctx_flags_t { + /*! + * Context is empty. In ARC4, this means that the S-Box needs to be + * generated from the key. In #FSL_SYM_MODE_CBC mode, this allows an IV of + * zero to be specified. In #FSL_SYM_MODE_CTR mode, it means that an + * initial CTR value of zero is desired. + */ + FSL_SYM_CTX_INIT = 1, + /*! + * Load context from object into hardware before running cipher. In + * #FSL_SYM_MODE_CTR mode, this would refer to the Counter Value. + */ + FSL_SYM_CTX_LOAD = 2, + /*! + * Save context from hardware into object after running cipher. In + * #FSL_SYM_MODE_CTR mode, this would refer to the Counter Value. + */ + FSL_SYM_CTX_SAVE = 4, + /*! + * Context (SBox) is to be unwrapped and wrapped on each use. + * This flag is unsupported. + * */ + FSL_SYM_CTX_PROTECT = 8, +} fsl_shw_sym_ctx_flags_t; + +/*! + * Flags which describe the state of the #fsl_shw_sko_t. + * + * These may be ORed together to get the desired effect. + * See #fsl_shw_sko_set_flags() and #fsl_shw_sko_clear_flags() + */ +typedef enum fsl_shw_key_flags_t { + FSL_SKO_KEY_IGNORE_PARITY = 1, /*!< If algorithm is DES or 3DES, do not + validate the key parity bits. */ + FSL_SKO_KEY_PRESENT = 2, /*!< Clear key is present in the object. */ + FSL_SKO_KEY_ESTABLISHED = 4, /*!< Key has been established for use. This + feature is not available for all + platforms, nor for all algorithms and + modes. */ + FSL_SKO_KEY_SW_KEY = 8, /*!< This key is for software use, and can + be copied out of a keystore by its owner. + The default is that they key is available + only for hardware (or security driver) + use. */ +} fsl_shw_key_flags_t; + +/*! + * Type of value which is associated with an established key. + */ +typedef uint64_t key_userid_t; + +/*! + * Flags which describe the state of the #fsl_shw_acco_t. + * + * The @a FSL_ACCO_CTX_INIT and @a FSL_ACCO_CTX_FINALIZE flags, when used + * together, provide for a one-shot operation. + */ +typedef enum fsl_shw_auth_ctx_flags_t { + FSL_ACCO_CTX_INIT = 1, /*!< Initialize Context(s) */ + FSL_ACCO_CTX_LOAD = 2, /*!< Load intermediate context(s). + This flag is unsupported. */ + FSL_ACCO_CTX_SAVE = 4, /*!< Save intermediate context(s). + This flag is unsupported. */ + FSL_ACCO_CTX_FINALIZE = 8, /*!< Create MAC during this operation. */ + FSL_ACCO_NIST_CCM = 16, /*!< Formatting of CCM input data is + performed by calls to + #fsl_shw_ccm_nist_format_ctr_and_iv() and + #fsl_shw_ccm_nist_update_ctr_and_iv(). */ +} fsl_shw_auth_ctx_flags_t; + +/*! + * Modulus Selector for CTR modes. + * + * The incrementing of the Counter value may be modified by a modulus. If no + * modulus is needed or desired for AES, use #FSL_CTR_MOD_128. + */ +typedef enum fsl_shw_ctr_mod_t { + FSL_CTR_MOD_8, /*!< Run counter with modulus of 2^8. */ + FSL_CTR_MOD_16, /*!< Run counter with modulus of 2^16. */ + FSL_CTR_MOD_24, /*!< Run counter with modulus of 2^24. */ + FSL_CTR_MOD_32, /*!< Run counter with modulus of 2^32. */ + FSL_CTR_MOD_40, /*!< Run counter with modulus of 2^40. */ + FSL_CTR_MOD_48, /*!< Run counter with modulus of 2^48. */ + FSL_CTR_MOD_56, /*!< Run counter with modulus of 2^56. */ + FSL_CTR_MOD_64, /*!< Run counter with modulus of 2^64. */ + FSL_CTR_MOD_72, /*!< Run counter with modulus of 2^72. */ + FSL_CTR_MOD_80, /*!< Run counter with modulus of 2^80. */ + FSL_CTR_MOD_88, /*!< Run counter with modulus of 2^88. */ + FSL_CTR_MOD_96, /*!< Run counter with modulus of 2^96. */ + FSL_CTR_MOD_104, /*!< Run counter with modulus of 2^104. */ + FSL_CTR_MOD_112, /*!< Run counter with modulus of 2^112. */ + FSL_CTR_MOD_120, /*!< Run counter with modulus of 2^120. */ + FSL_CTR_MOD_128 /*!< Run counter with modulus of 2^128. */ +} fsl_shw_ctr_mod_t; + +/*! + * Permissions flags for Secure Partitions + * + * They currently map directly to the SCC2 hardware values, but this is not + * guarinteed behavior. + */ +typedef enum fsl_shw_permission_t { +/*! SCM Access Permission: Do not zeroize/deallocate partition on SMN Fail state */ + FSL_PERM_NO_ZEROIZE, +/*! SCM Access Permission: Enforce trusted key read in */ + FSL_PERM_TRUSTED_KEY_READ, +/*! SCM Access Permission: Ignore Supervisor/User mode in permission determination */ + FSL_PERM_HD_S, +/*! SCM Access Permission: Allow Read Access to Host Domain */ + FSL_PERM_HD_R, +/*! SCM Access Permission: Allow Write Access to Host Domain */ + FSL_PERM_HD_W, +/*! SCM Access Permission: Allow Execute Access to Host Domain */ + FSL_PERM_HD_X, +/*! SCM Access Permission: Allow Read Access to Trusted Host Domain */ + FSL_PERM_TH_R, +/*! SCM Access Permission: Allow Write Access to Trusted Host Domain */ + FSL_PERM_TH_W, +/*! SCM Access Permission: Allow Read Access to Other/World Domain */ + FSL_PERM_OT_R, +/*! SCM Access Permission: Allow Write Access to Other/World Domain */ + FSL_PERM_OT_W, +/*! SCM Access Permission: Allow Execute Access to Other/World Domain */ + FSL_PERM_OT_X, +} fsl_shw_permission_t; + +/*! + * Select the cypher mode to use for partition cover/uncover operations. + * + * They currently map directly to the values used in the SCC2 driver, but this + * is not guarinteed behavior. + */ +typedef enum fsl_shw_cypher_mode_t { + FSL_SHW_CYPHER_MODE_ECB, /*!< ECB mode */ + FSL_SHW_CYPHER_MODE_CBC, /*!< CBC mode */ +} fsl_shw_cypher_mode_t; + +/*! + * Which platform key should be presented for cryptographic use. + */ +typedef enum fsl_shw_pf_key_t { + FSL_SHW_PF_KEY_IIM, /*!< Present fused IIM key */ + FSL_SHW_PF_KEY_PRG, /*!< Present Program key */ + FSL_SHW_PF_KEY_IIM_PRG, /*!< Present IIM ^ Program key */ + FSL_SHW_PF_KEY_IIM_RND, /*!< Present Random key */ + FSL_SHW_PF_KEY_RND, /*!< Present IIM ^ Random key */ +} fsl_shw_pf_key_t; + +/*! + * The various security tamper events + */ +typedef enum fsl_shw_tamper_t { + FSL_SHW_TAMPER_NONE, /*!< No error detected */ + FSL_SHW_TAMPER_WTD, /*!< wire-mesh tampering det */ + FSL_SHW_TAMPER_ETBD, /*!< ext tampering det: input B */ + FSL_SHW_TAMPER_ETAD, /*!< ext tampering det: input A */ + FSL_SHW_TAMPER_EBD, /*!< external boot detected */ + FSL_SHW_TAMPER_SAD, /*!< security alarm detected */ + FSL_SHW_TAMPER_TTD, /*!< temperature tampering det */ + FSL_SHW_TAMPER_CTD, /*!< clock tampering det */ + FSL_SHW_TAMPER_VTD, /*!< voltage tampering det */ + FSL_SHW_TAMPER_MCO, /*!< monotonic counter overflow */ + FSL_SHW_TAMPER_TCO, /*!< time counter overflow */ +} fsl_shw_tamper_t; + +/*! @} *//* consgrp */ + +/****************************************************************************** + * Data Structures + *****************************************************************************/ +/*! @addtogroup strgrp + @{ */ + +/* REQ-S2LRD-PINTFC-COA-IBO-001 */ +/*! + * Application Initialization Object + * + * This object, the operations on it, and its interaction with the driver are + * TBD. + */ +typedef struct fsl_sho_ibo_t { +} fsl_sho_ibo_t; + +/* REQ-S2LRD-PINTFC-COA-UCO-001 */ +/*! + * User Context Object + * + * This object must be initialized by a call to #fsl_shw_uco_init(). It must + * then be passed to #fsl_shw_register_user() before it can be used in any + * calls besides those in @ref ucoops. + * + * It contains the user's configuration for the API, for instance whether an + * operation should block, or instead should call back the user upon completion + * of the operation. + * + * See @ref ucoops for further information. + */ +typedef struct fsl_shw_uco_t { /* fsl_shw_user_context_object */ +} fsl_shw_uco_t; + +/* REQ-S2LRD-PINTFC-API-GEN-006 ?? */ +/*! + * Result Object + * + * This object will contain success and failure information about a specific + * cryptographic request which has been made. + * + * No direct access to its members should be made by programs. Instead, the + * object should be manipulated using the provided functions. See @ref rops. + */ +typedef struct fsl_shw_result_t { /* fsl_shw_result */ +} fsl_shw_result_t; + +/*! + * Keystore Object + * + * This object holds the context of a user keystore, including the functions + * that define the interface and pointers to where the key data is stored. The + * user must supply a set of functions to handle keystore management, including + * slot allocation, deallocation, etc. A default keystore manager is provided + * as part of the API. + * + * No direct access to its members should be made by programs. Instead, the + * object should be manipulated using the provided functions. See @ref ksoops. + */ +typedef struct fsl_shw_kso_t { /* fsl_shw_keystore_object */ +} fsl_shw_kso_t; + +/* REQ-S2LRD-PINTFC-COA-SKO-001 */ +/*! + * Secret Key Object + * + * This object contains a key for a cryptographic operation, and information + * about its current state, its intended usage, etc. It may instead contain + * information about a protected key, or an indication to use a platform- + * specific secret key. + * + * No direct access to its members should be made by programs. Instead, the + * object should be manipulated using the provided functions. See @ref skoops. + */ +typedef struct fsl_shw_sko_t { /* fsl_shw_secret_key_object */ +} fsl_shw_sko_t; + +/* REQ-S2LRD-PINTFC-COA-CO-001 */ +/*! + * Platform Capabilities Object + * + * This object will contain information about the cryptographic features of the + * platform which the program is running on. + * + * No direct access to its members should be made by programs. Instead, the + * object should be manipulated using the provided functions. + * + * See @ref pcoops. + */ +typedef struct fsl_shw_pco_t { /* fsl_shw_platform_capabilities_object */ +} fsl_shw_pco_t; + +/* REQ-S2LRD-PINTFC-COA-HCO-001 */ +/*! + * Hash Context Object + * + * This object contains information to control hashing functions. + + * No direct access to its members should be made by programs. Instead, the + * object should be manipulated using the provided functions. See @ref hcops. + */ +typedef struct fsl_shw_hco_t { /* fsl_shw_hash_context_object */ +} fsl_shw_hco_t; + +/*! + * HMAC Context Object + * + * This object contains information to control HMAC functions. + + * No direct access to its members should be made by programs. Instead, the + * object should be manipulated using the provided functions. See @ref hmcops. + */ +typedef struct fsl_shw_hmco_t { /* fsl_shw_hmac_context_object */ +} fsl_shw_hmco_t; + +/* REQ-S2LRD-PINTFC-COA-SCCO-001 */ +/*! + * Symmetric Cipher Context Object + * + * This object contains information to control Symmetric Ciphering encrypt and + * decrypt functions in #FSL_SYM_MODE_STREAM (ARC4), #FSL_SYM_MODE_ECB, + * #FSL_SYM_MODE_CBC, and #FSL_SYM_MODE_CTR modes and the + * #fsl_shw_symmetric_encrypt() and #fsl_shw_symmetric_decrypt() functions. + * CCM mode is controlled with the #fsl_shw_acco_t object. + * + * No direct access to its members should be made by programs. Instead, the + * object should be manipulated using the provided functions. See @ref sccops. + */ +typedef struct fsl_shw_scco_t { /* fsl_shw_symmetric_cipher_context_object */ +} fsl_shw_scco_t; + +/*! + * Authenticate-Cipher Context Object + + * An object for controlling the function of, and holding information about, + * data for the authenticate-cipher functions, #fsl_shw_gen_encrypt() and + * #fsl_shw_auth_decrypt(). + * + * No direct access to its members should be made by programs. Instead, the + * object should be manipulated using the provided functions. See @ref + * accoops. + */ +typedef struct fsl_shw_acco_t { /* fsl_shw_authenticate_cipher_context_object */ +} fsl_shw_acco_t; + /*! @} *//* strgrp */ + +/****************************************************************************** + * Access Macros for Objects + *****************************************************************************/ +/*! @addtogroup pcoops + @{ */ + +/*! + * Get FSL SHW API version + * + * @param pc_info The Platform Capabilities Object to query. + * @param[out] major A pointer to where the major version + * of the API is to be stored. + * @param[out] minor A pointer to where the minor version + * of the API is to be stored. + */ +void fsl_shw_pco_get_version(const fsl_shw_pco_t * pc_info, + uint32_t * major, uint32_t * minor); + +/*! + * Get underlying driver version. + * + * @param pc_info The Platform Capabilities Object to query. + * @param[out] major A pointer to where the major version + * of the driver is to be stored. + * @param[out] minor A pointer to where the minor version + * of the driver is to be stored. + */ +void fsl_shw_pco_get_driver_version(const fsl_shw_pco_t * pc_info, + uint32_t * major, uint32_t * minor); + +/*! + * Get list of symmetric algorithms supported. + * + * @param pc_info The Platform Capabilities Object to query. + * @param[out] algorithms A pointer to where to store the location of + * the list of algorithms. + * @param[out] algorithm_count A pointer to where to store the number of + * algorithms in the list at @a algorithms. + */ +void fsl_shw_pco_get_sym_algorithms(const fsl_shw_pco_t * pc_info, + fsl_shw_key_alg_t * algorithms[], + uint8_t * algorithm_count); + +/*! + * Get list of symmetric modes supported. + * + * @param pc_info The Platform Capabilities Object to query. + * @param[out] modes A pointer to where to store the location of + * the list of modes. + * @param[out] mode_count A pointer to where to store the number of + * algorithms in the list at @a modes. + */ +void fsl_shw_pco_get_sym_modes(const fsl_shw_pco_t * pc_info, + fsl_shw_sym_mode_t * modes[], + uint8_t * mode_count); + +/*! + * Get list of hash algorithms supported. + * + * @param pc_info The Platform Capabilities Object to query. + * @param[out] algorithms A pointer which will be set to the list of + * algorithms. + * @param[out] algorithm_count The number of algorithms in the list at @a + * algorithms. + */ +void fsl_shw_pco_get_hash_algorithms(const fsl_shw_pco_t * pc_info, + fsl_shw_hash_alg_t * algorithms[], + uint8_t * algorithm_count); + +/*! + * Determine whether the combination of a given symmetric algorithm and a given + * mode is supported. + * + * @param pc_info The Platform Capabilities Object to query. + * @param algorithm A Symmetric Cipher algorithm. + * @param mode A Symmetric Cipher mode. + * + * @return 0 if combination is not supported, non-zero if supported. + */ +int fsl_shw_pco_check_sym_supported(const fsl_shw_pco_t * pc_info, + fsl_shw_key_alg_t algorithm, + fsl_shw_sym_mode_t mode); + +/*! + * Determine whether a given Encryption-Authentication mode is supported. + * + * @param pc_info The Platform Capabilities Object to query. + * @param mode The Authentication mode. + * + * @return 0 if mode is not supported, non-zero if supported. + */ +int fsl_shw_pco_check_auth_supported(const fsl_shw_pco_t * pc_info, + fsl_shw_acc_mode_t mode); + +/*! + * Determine whether Black Keys (key establishment / wrapping) is supported. + * + * @param pc_info The Platform Capabilities Object to query. + * + * @return 0 if wrapping is not supported, non-zero if supported. + */ +int fsl_shw_pco_check_black_key_supported(const fsl_shw_pco_t * pc_info); + +/*! + * Get FSL SHW SCC driver version + * + * @param pc_info The Platform Capabilities Object to query. + * @param[out] major A pointer to where the major version + * of the SCC driver is to be stored. + * @param[out] minor A pointer to where the minor version + * of the SCC driver is to be stored. + */ +void fsl_shw_pco_get_scc_driver_version(const fsl_shw_pco_t * pc_info, + uint32_t * major, uint32_t * minor); + +/*! + * Get SCM hardware version + * + * @param pc_info The Platform Capabilities Object to query. + * @return The SCM hardware version + */ +uint32_t fsl_shw_pco_get_scm_version(const fsl_shw_pco_t * pc_info); + +/*! + * Get SMN hardware version + * + * @param pc_info The Platform Capabilities Object to query. + * @return The SMN hardware version + */ +uint32_t fsl_shw_pco_get_smn_version(const fsl_shw_pco_t * pc_info); + +/*! + * Get the size of an SCM block, in bytes + * + * @param pc_info The Platform Capabilities Object to query. + * @return The size of an SCM block, in bytes. + */ +uint32_t fsl_shw_pco_get_scm_block_size(const fsl_shw_pco_t * pc_info); + +/*! + * Get size of Black and Red RAM memory + * + * @param pc_info The Platform Capabilities Object to query. + * @param[out] black_size A pointer to where the size of the Black RAM, in + * blocks, is to be placed. + * @param[out] red_size A pointer to where the size of the Red RAM, in + * blocks, is to be placed. + */ +void fsl_shw_pco_get_smn_size(const fsl_shw_pco_t * pc_info, + uint32_t * black_size, uint32_t * red_size); + +/*! + * Determine whether Secure Partitions are supported + * + * @param pc_info The Platform Capabilities Object to query. + * + * @return 0 if secure partitions are not supported, non-zero if supported. + */ +int fsl_shw_pco_check_spo_supported(const fsl_shw_pco_t * pc_info); + +/*! + * Get the size of a Secure Partitions + * + * @param pc_info The Platform Capabilities Object to query. + * + * @return Partition size, in bytes. 0 if Secure Partitions not supported. + */ +uint32_t fsl_shw_pco_get_spo_size_bytes(const fsl_shw_pco_t * pc_info); + +/*! + * Get the number of Secure Partitions on this platform + * + * @param pc_info The Platform Capabilities Object to query. + * + * @return Number of partitions. 0 if Secure Partitions not supported. Note + * that this returns the total number of partitions, though + * not all may be available to the user. + */ +uint32_t fsl_shw_pco_get_spo_count(const fsl_shw_pco_t * pc_info); + +/*! + * Determine whether Platform Key features are available + * + * @param pc_info The Platform Capabilities Object to query. + * + * @return 1 if Programmed Key features are available, otherwise zero. + */ +int fsl_shw_pco_check_pk_supported(const fsl_shw_pco_t * pc_info); + +/*! + * Determine whether Software Key features are available + * + * @param pc_info The Platform Capabilities Object to query. + * + * @return 1 if Software key features are available, otherwise zero. + */ +int fsl_shw_pco_check_sw_keys_supported(const fsl_shw_pco_t * pc_info); + +/*! @} *//* pcoops */ + +/*! @addtogroup ucoops + @{ */ + +/*! + * Initialize a User Context Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the User Context Object to initial values, and set the size + * of the results pool. The mode will be set to a default of + * #FSL_UCO_BLOCKING_MODE. + * + * When using non-blocking operations, this sets the maximum number of + * operations which can be outstanding. This number includes the counts of + * operations waiting to start, operation(s) being performed, and results which + * have not been retrieved. + * + * Changes to this value are ignored once user registration has completed. It + * should be set to 1 if only blocking operations will ever be performed. + * + * @param user_ctx The User Context object to operate on. + * @param pool_size The maximum number of operations which can be + * outstanding. + */ +void fsl_shw_uco_init(fsl_shw_uco_t * user_ctx, uint16_t pool_size); + +/*! + * Set the User Reference for the User Context. + * + * @param user_ctx The User Context object to operate on. + * @param reference A value which will be passed back with a result. + */ +void fsl_shw_uco_set_reference(fsl_shw_uco_t * user_ctx, uint32_t reference); + +/*! + * Set the callback routine for the User Context. + * + * Note that the callback routine may be called when no results are available, + * and possibly even when no requests are outstanding. + * + * + * @param user_ctx The User Context object to operate on. + * @param callback_fn The function the API will invoke when an operation + * completes. + */ +void fsl_shw_uco_set_callback(fsl_shw_uco_t * user_ctx, + void (*callback_fn) (fsl_shw_uco_t * uco)); + +/*! + * Set flags in the User Context. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param user_ctx The User Context object to operate on. + * @param flags ORed values from #fsl_shw_user_ctx_flags_t. + */ +void fsl_shw_uco_set_flags(fsl_shw_uco_t * user_ctx, uint32_t flags); + +/*! + * Clear flags in the User Context. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param user_ctx The User Context object to operate on. + * @param flags ORed values from #fsl_shw_user_ctx_flags_t. + */ +void fsl_shw_uco_clear_flags(fsl_shw_uco_t * user_ctx, uint32_t flags); + +/*! + * Select a key for the key-wrap key for key wrapping/unwrapping + * + * Without a call to this function, default is FSL_SHW_PF_KEY_IIM. The wrap + * key is used to encrypt and decrypt the per-key random secret which is used + * to calculate the key which will encrypt/decrypt the user's key. + * + * @param user_ctx The User Context object to operate on. + * @param pf_key Which key to use. Valid choices are + * #FSL_SHW_PF_KEY_IIM, #FSL_SHW_PF_KEY_RND, and + * #FSL_SHW_PF_KEY_IIM_RND. + */ +void fsl_shw_uco_set_wrap_key(fsl_shw_uco_t * user_ctx, + fsl_shw_pf_key_t pf_key); + + /*! @} *//* ucoops */ + +/*! @addtogroup rops + @{ */ + +/*! + * Retrieve the status code from a Result Object. + * + * @param result The result object to query. + * + * @return The status of the request. + */ +fsl_shw_return_t fsl_shw_ro_get_status(fsl_shw_result_t * result); + +/*! + * Retrieve the reference value from a Result Object. + * + * @param result The result object to query. + * + * @return The reference associated with the request. + */ +uint32_t fsl_shw_ro_get_reference(fsl_shw_result_t * result); + + /* @} *//* rops */ + +/*! @addtogroup skoops + @{ */ + +/*! + * Initialize a Secret Key Object. + * + * This function or #fsl_shw_sko_init_pf_key() must be called before performing + * any other operation with the Object. + * + * @param key_info The Secret Key Object to be initialized. + * @param algorithm DES, AES, etc. + * + */ +void fsl_shw_sko_init(fsl_shw_sko_t * key_info, fsl_shw_key_alg_t algorithm); + +/*! + * Initialize a Secret Key Object to use a Platform Key register. + * + * This function or #fsl_shw_sko_init() must be called before performing any + * other operation with the Object. #fsl_shw_sko_set_key() does not work on + * a key object initialized in this way. + * + * If this function is used to initialize the key object, but no key is + * established with the key object, then the object will refer strictly to the + * key value specified by the @c pf_key selection. + * + * If the pf key is #FSL_SHW_PF_KEY_PRG or #FSL_SHW_PF_KEY_IIM_PRG, then the + * key object may be used with #fsl_shw_establish_key() to change the Program + * Key value. When the pf key is neither #FSL_SHW_PF_KEY_PRG nor + * #FSL_SHW_PF_KEY_IIM_PRG, it is an error to call #fsl_shw_establish_key(). + * + * @param key_info The Secret Key Object to be initialized. + * @param algorithm DES, AES, etc. + * @param pf_key Which platform key is referenced. + */ +void fsl_shw_sko_init_pf_key(fsl_shw_sko_t * key_info, + fsl_shw_key_alg_t algorithm, + fsl_shw_pf_key_t pf_key); + +/*! + * Store a cleartext key in the key object. + * + * This has the side effect of setting the #FSL_SKO_KEY_PRESENT flag. It should + * not be used if there is a key established with the key object. If there is, + * a call to #fsl_shw_release_key() should be made first. + * + * @param key_object A variable of type #fsl_shw_sko_t. + * @param key A pointer to the beginning of the key. + * @param key_length The length, in octets, of the key. The value should be + * appropriate to the key size supported by the algorithm. + * 64 octets is the absolute maximum value allowed for this + * call. + */ +void fsl_shw_sko_set_key(fsl_shw_sko_t * key_object, + const uint8_t * key, uint16_t key_length); + +/*! + * Set a size for the key. + * + * This function would normally be used when the user wants the key to be + * generated from a random source. + * + * @param key_object A variable of type #fsl_shw_sko_t. + * @param key_length The length, in octets, of the key. The value should be + * appropriate to the key size supported by the algorithm. + * 64 octets is the absolute maximum value allowed for this + * call. + */ +void fsl_shw_sko_set_key_length(fsl_shw_sko_t * key_object, + uint16_t key_length); + +/*! + * Set the User ID associated with the key. + * + * @param key_object A variable of type #fsl_shw_sko_t. + * @param userid The User ID to identify authorized users of the key. + */ +void fsl_shw_sko_set_user_id(fsl_shw_sko_t * key_object, key_userid_t userid); + +/*! + * Set the keystore that the key will be stored in. + * + * @param key_object A variable of type #fsl_shw_sko_t. + * @param keystore The keystore to place the key in. This is a variable of + * type #fsl_shw_kso_t. + */ +void fsl_shw_sko_set_keystore(fsl_shw_sko_t * key_object, + fsl_shw_kso_t * keystore); + +/*! + * Set the establish key handle into a key object. + * + * The @a userid field will be used to validate the access to the unwrapped + * key. This feature is not available for all platforms, nor for all + * algorithms and modes. + * + * The #FSL_SKO_KEY_ESTABLISHED will be set (and the #FSL_SKO_KEY_PRESENT + * flag will be cleared). + * + * @param key_object A variable of type #fsl_shw_sko_t. + * @param userid The User ID to verify this user is an authorized user of + * the key. + * @param handle A @a handle from #fsl_shw_sko_get_established_info. + */ +void fsl_shw_sko_set_established_info(fsl_shw_sko_t * key_object, + key_userid_t userid, uint32_t handle); + +/*! + * Extract the algorithm from a key object. + * + * @param key_info The Key Object to be queried. + * @param[out] algorithm A pointer to the location to store the algorithm. + */ +void fsl_shw_sko_get_algorithm(const fsl_shw_sko_t * key_info, + fsl_shw_key_alg_t * algorithm); + +/*! + * Retrieve the cleartext key from a key object that is stored in a user + * keystore. + * + * @param skobject The Key Object to be queried. + * @param[out] skkey A pointer to the location to store the key. NULL + * if the key is not stored in a user keystore. + */ +void fsl_shw_sko_get_key(const fsl_shw_sko_t * skobject, void *skkey); + +/*! + * Retrieve the established-key handle from a key object. + * + * @param key_object A variable of type #fsl_shw_sko_t. + * @param handle The location to store the @a handle of the unwrapped + * key. + */ +void fsl_shw_sko_get_established_info(fsl_shw_sko_t * key_object, + uint32_t * handle); + +/*! + * Determine the size of a wrapped key based upon the cleartext key's length. + * + * This function can be used to calculate the number of octets that + * #fsl_shw_extract_key() will write into the location at @a covered_key. + * + * If zero is returned at @a length, this means that the key length in + * @a key_info is not supported. + * + * @param key_info Information about a key to be wrapped. + * @param length Location to store the length of a wrapped + * version of the key in @a key_info. + */ +void fsl_shw_sko_calculate_wrapped_size(const fsl_shw_sko_t * key_info, + uint32_t * length); + +/*! + * Set some flags in the key object. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param key_object A variable of type #fsl_shw_sko_t. + * @param flags (One or more) ORed members of #fsl_shw_key_flags_t which + * are to be set. + */ +void fsl_shw_sko_set_flags(fsl_shw_sko_t * key_object, uint32_t flags); + +/*! + * Clear some flags in the key object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param key_object A variable of type #fsl_shw_sko_t. + * @param flags (One or more) ORed members of #fsl_shw_key_flags_t which + * are to be reset. + */ +void fsl_shw_sko_clear_flags(fsl_shw_sko_t * key_object, uint32_t flags); + + /*! @} *//* end skoops */ + +/*****************************************************************************/ + +/*! @addtogroup hcops + @{ */ + +/*****************************************************************************/ +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-004 - partially */ +/*! + * Initialize a Hash Context Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the current message length and hash algorithm in the hash + * context object. + * + * @param hash_ctx The hash context to operate upon. + * @param algorithm The hash algorithm to be used (#FSL_HASH_ALG_MD5, + * #FSL_HASH_ALG_SHA256, etc). + * + */ +void fsl_shw_hco_init(fsl_shw_hco_t * hash_ctx, fsl_shw_hash_alg_t algorithm); + +/*****************************************************************************/ +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-001 */ +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-002 */ +/*! + * Get the current hash value and message length from the hash context object. + * + * The algorithm must have already been specified. See #fsl_shw_hco_init(). + * + * @param hash_ctx The hash context to query. + * @param[out] digest Pointer to the location of @a length octets where to + * store a copy of the current value of the digest. + * @param length Number of octets of hash value to copy. + * @param[out] msg_length Pointer to the location to store the number of octets + * already hashed. + */ +void fsl_shw_hco_get_digest(const fsl_shw_hco_t * hash_ctx, uint8_t * digest, + uint8_t length, uint32_t * msg_length); + +/*****************************************************************************/ +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-002 - partially */ +/*! + * Get the hash algorithm from the hash context object. + * + * @param hash_ctx The hash context to query. + * @param[out] algorithm Pointer to where the algorithm is to be stored. + */ +void fsl_shw_hco_get_info(const fsl_shw_hco_t * hash_ctx, + fsl_shw_hash_alg_t * algorithm); + +/*****************************************************************************/ +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-003 */ +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-004 */ +/*! + * Set the current hash value and message length in the hash context object. + * + * The algorithm must have already been specified. See #fsl_shw_hco_init(). + * + * @param hash_ctx The hash context to operate upon. + * @param context Pointer to buffer of appropriate length to copy into + * the hash context object. + * @param msg_length The number of octets of the message which have + * already been hashed. + * + */ +void fsl_shw_hco_set_digest(fsl_shw_hco_t * hash_ctx, const uint8_t * context, + uint32_t msg_length); + +/*! + * Set flags in a Hash Context Object. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param hash_ctx The hash context to be operated on. + * @param flags The flags to be set in the context. These can be ORed + * members of #fsl_shw_hash_ctx_flags_t. + */ +void fsl_shw_hco_set_flags(fsl_shw_hco_t * hash_ctx, uint32_t flags); + +/*! + * Clear flags in a Hash Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param hash_ctx The hash context to be operated on. + * @param flags The flags to be reset in the context. These can be ORed + * members of #fsl_shw_hash_ctx_flags_t. + */ +void fsl_shw_hco_clear_flags(fsl_shw_hco_t * hash_ctx, uint32_t flags); + + /*! @} *//* end hcops */ + +/*****************************************************************************/ + +/*! @addtogroup hmcops + @{ */ + +/*! + * Initialize an HMAC Context Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the current message length and hash algorithm in the HMAC + * context object. + * + * @param hmac_ctx The HMAC context to operate upon. + * @param algorithm The hash algorithm to be used (#FSL_HASH_ALG_MD5, + * #FSL_HASH_ALG_SHA256, etc). + * + */ +void fsl_shw_hmco_init(fsl_shw_hmco_t * hmac_ctx, fsl_shw_hash_alg_t algorithm); + +/*! + * Set flags in an HMAC Context Object. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param hmac_ctx The HMAC context to be operated on. + * @param flags The flags to be set in the context. These can be ORed + * members of #fsl_shw_hmac_ctx_flags_t. + */ +void fsl_shw_hmco_set_flags(fsl_shw_hmco_t * hmac_ctx, uint32_t flags); + +/*! + * Clear flags in an HMAC Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param hmac_ctx The HMAC context to be operated on. + * @param flags The flags to be reset in the context. These can be ORed + * members of #fsl_shw_hmac_ctx_flags_t. + */ +void fsl_shw_hmco_clear_flags(fsl_shw_hmco_t * hmac_ctx, uint32_t flags); + +/*! @} */ + +/*****************************************************************************/ + +/*! @addtogroup sccops + @{ */ + +/*! + * Initialize a Symmetric Cipher Context Object. + * + * This function must be called before performing any other operation with the + * Object. This will set the @a mode and @a algorithm and initialize the + * Object. + * + * @param sym_ctx The context object to operate on. + * @param algorithm The cipher algorithm this context will be used with. + * @param mode #FSL_SYM_MODE_CBC, #FSL_SYM_MODE_ECB, etc. + * + */ +void fsl_shw_scco_init(fsl_shw_scco_t * sym_ctx, + fsl_shw_key_alg_t algorithm, fsl_shw_sym_mode_t mode); + +/*! + * Set the flags for a Symmetric Cipher Context. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param sym_ctx The context object to operate on. + * @param flags The flags to reset (one or more values from + * #fsl_shw_sym_ctx_flags_t ORed together). + * + */ +void fsl_shw_scco_set_flags(fsl_shw_scco_t * sym_ctx, uint32_t flags); + +/*! + * Clear some flags in a Symmetric Cipher Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param sym_ctx The context object to operate on. + * @param flags The flags to reset (one or more values from + * #fsl_shw_sym_ctx_flags_t ORed together). + * + */ +void fsl_shw_scco_clear_flags(fsl_shw_scco_t * sym_ctx, uint32_t flags); + +/*! + * Set the Context (IV) for a Symmetric Cipher Context. + * + * This is to set the context/IV for #FSL_SYM_MODE_CBC mode, or to set the + * context (the S-Box and pointers) for ARC4. The full context size will + * be copied. + * + * @param sym_ctx The context object to operate on. + * @param context A pointer to the buffer which contains the context. + * + */ +void fsl_shw_scco_set_context(fsl_shw_scco_t * sym_ctx, uint8_t * context); + +/*! + * Get the Context for a Symmetric Cipher Context. + * + * This is to retrieve the context/IV for #FSL_SYM_MODE_CBC mode, or to + * retrieve context (the S-Box and pointers) for ARC4. The full context + * will be copied. + * + * @param sym_ctx The context object to operate on. + * @param[out] context Pointer to location where context will be stored. + */ +void fsl_shw_scco_get_context(const fsl_shw_scco_t * sym_ctx, + uint8_t * context); + +/*! + * Set the Counter Value for a Symmetric Cipher Context. + * + * This will set the Counter Value for CTR mode. + * + * @param sym_ctx The context object to operate on. + * @param counter The starting counter value. The number of octets. + * copied will be the block size for the algorithm. + * @param modulus The modulus for controlling the incrementing of the counter. + * + */ +void fsl_shw_scco_set_counter_info(fsl_shw_scco_t * sym_ctx, + const uint8_t * counter, + fsl_shw_ctr_mod_t modulus); + +/*! + * Get the Counter Value for a Symmetric Cipher Context. + * + * This will retrieve the Counter Value is for CTR mode. + * + * @param sym_ctx The context object to query. + * @param[out] counter Pointer to location to store the current counter + * value. The number of octets copied will be the + * block size for the algorithm. + * @param[out] modulus Pointer to location to store the modulus. + * + */ +void fsl_shw_scco_get_counter_info(const fsl_shw_scco_t * sym_ctx, + uint8_t * counter, + fsl_shw_ctr_mod_t * modulus); + + /*! @} *//* end sccops */ + +/*****************************************************************************/ + +/*! @addtogroup accoops + @{ */ + +/*! + * Initialize a Authentication-Cipher Context. + * + * @param auth_object Pointer to object to operate on. + * @param mode The mode for this object (only #FSL_ACC_MODE_CCM + * supported). + */ +void fsl_shw_acco_init(fsl_shw_acco_t * auth_object, fsl_shw_acc_mode_t mode); + +/*! + * Set the flags for a Authentication-Cipher Context. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param auth_object Pointer to object to operate on. + * @param flags The flags to set (one or more from + * #fsl_shw_auth_ctx_flags_t ORed together). + * + */ +void fsl_shw_acco_set_flags(fsl_shw_acco_t * auth_object, uint32_t flags); + +/*! + * Clear some flags in a Authentication-Cipher Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param auth_object Pointer to object to operate on. + * @param flags The flags to reset (one or more from + * #fsl_shw_auth_ctx_flags_t ORed together). + * + */ +void fsl_shw_acco_clear_flags(fsl_shw_acco_t * auth_object, uint32_t flags); + +/*! + * Set up the Authentication-Cipher Object for CCM mode. + * + * This will set the @a auth_object for CCM mode and save the @a ctr, + * and @a mac_length. This function can be called instead of + * #fsl_shw_acco_init(). + * + * The parameter @a ctr is Counter Block 0, (counter value 0), which is for the + * MAC. + * + * @param auth_object Pointer to object to operate on. + * @param algorithm Cipher algorithm. Only AES is supported. + * @param ctr The initial counter value. + * @param mac_length The number of octets used for the MAC. Valid values are + * 4, 6, 8, 10, 12, 14, and 16. + */ +void fsl_shw_acco_set_ccm(fsl_shw_acco_t * auth_object, + fsl_shw_key_alg_t algorithm, + const uint8_t * ctr, uint8_t mac_length); + +/*! + * Format the First Block (IV) & Initial Counter Value per NIST CCM. + * + * This function will also set the IV and CTR values per Appendix A of NIST + * Special Publication 800-38C (May 2004). It will also perform the + * #fsl_shw_acco_set_ccm() operation with information derived from this set of + * parameters. + * + * Note this function assumes the algorithm is AES. It initializes the + * @a auth_object by setting the mode to #FSL_ACC_MODE_CCM and setting the + * flags to be #FSL_ACCO_NIST_CCM. + * + * @param auth_object Pointer to object to operate on. + * @param t_length The number of octets used for the MAC. Valid values are + * 4, 6, 8, 10, 12, 14, and 16. + * @param ad_length Number of octets of Associated Data (may be zero). + * @param q_length A value for the size of the length of @a q field. Valid + * values are 1-8. + * @param n The Nonce (packet number or other changing value). Must + * be (15 - @a q_length) octets long. + * @param q The value of Q (size of the payload in octets). + * + */ +void fsl_shw_ccm_nist_format_ctr_and_iv(fsl_shw_acco_t * auth_object, + uint8_t t_length, + uint32_t ad_length, + uint8_t q_length, + const uint8_t * n, uint32_t q); + +/*! + * Update the First Block (IV) & Initial Counter Value per NIST CCM. + * + * This function will set the IV and CTR values per Appendix A of NIST Special + * Publication 800-38C (May 2004). + * + * Note this function assumes that #fsl_shw_ccm_nist_format_ctr_and_iv() has + * previously been called on the @a auth_object. + * + * @param auth_object Pointer to object to operate on. + * @param n The Nonce (packet number or other changing value). Must + * be (15 - @a q_length) octets long. + * @param q The value of Q (size of the payload in octets). + * + */ +void fsl_shw_ccm_nist_update_ctr_and_iv(fsl_shw_acco_t * auth_object, + const uint8_t * n, uint32_t q); + + /* @} *//* accoops */ + +/****************************************************************************** + * Library functions + *****************************************************************************/ + +/*! @addtogroup miscfuns + @{ */ + +/* REQ-S2LRD-PINTFC-API-GEN-003 */ +/*! + * Determine the hardware security capabilities of this platform. + * + * Though a user context object is passed into this function, it will always + * act in a non-blocking manner. + * + * @param user_ctx The user context which will be used for the query. + * + * @return A pointer to the capabilities object. + */ +extern fsl_shw_pco_t *fsl_shw_get_capabilities(fsl_shw_uco_t * user_ctx); + +/* REQ-S2LRD-PINTFC-API-GEN-004 */ +/*! + * Create an association between the user and the provider of the API. + * + * @param user_ctx The user context which will be used for this association. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_register_user(fsl_shw_uco_t * user_ctx); + +/* REQ-S2LRD-PINTFC-API-GEN-005 */ +/*! + * Destroy the association between the user and the provider of the API. + * + * @param user_ctx The user context which is no longer needed. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_deregister_user(fsl_shw_uco_t * user_ctx); + +/* REQ-S2LRD-PINTFC-API-GEN-006 */ +/*! + * Retrieve results from earlier operations. + * + * @param user_ctx The user's context. + * @param result_size The number of array elements of @a results. + * @param[in,out] results Pointer to first of the (array of) locations to + * store results. + * @param[out] result_count Pointer to store the number of results which + * were returned. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_get_results(fsl_shw_uco_t * user_ctx, + uint16_t result_size, + fsl_shw_result_t results[], + uint16_t * result_count); + +/*! + * Allocate a block of secure memory + * + * @param user_ctx User context + * @param size Memory size (octets). Note: currently only + * supports only single-partition sized blocks. + * @param UMID User Mode ID to use when registering the + * partition. + * @param permissions Permissions to initialize the partition with. + * Can be made by ORing flags from the + * #fsl_shw_permission_t. + * + * @return Address of the allocated memory. NULL if the + * call was not successful. + */ +extern void *fsl_shw_smalloc(fsl_shw_uco_t * user_ctx, + uint32_t size, + const uint8_t * UMID, uint32_t permissions); + +/*! + * Free a block of secure memory that was allocated with #fsl_shw_smalloc + * + * @param user_ctx User context + * @param address Address of the block of secure memory to be + * released. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_sfree(fsl_shw_uco_t * user_ctx, void *address); + +/*! + * Diminish the permissions of a block of secure memory. Note that permissions + * can only be revoked. + * + * @param user_ctx User context + * @param address Base address of the secure memory to work with + * @param permissions Permissions to initialize the partition with. + * Can be made by ORing flags from the + * #fsl_shw_permission_t. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_diminish_perms(fsl_shw_uco_t * user_ctx, + void *address, + uint32_t permissions); + +/*! + * @brief Encrypt a region of secure memory using the hardware secret key + * + * @param user_ctx User context + * @param partition_base Base address of the partition + * @param offset_bytes Offset of data from the partition base + * @param byte_count Length of the data to encrypt + * @param black_data Location to store the encrypted data + * @param IV IV to use for the encryption routine + * @param cypher_mode Cyphering mode to use, specified by type + * #fsl_shw_cypher_mode_t + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t +do_scc_encrypt_region(fsl_shw_uco_t * user_ctx, + void *partition_base, uint32_t offset_bytes, + uint32_t byte_count, uint8_t * black_data, + uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode); + +/*! + * @brief Decrypt a region of secure memory using the hardware secret key + * + * @param user_ctx User context + * @param partition_base Base address of the partition + * @param offset_bytes Offset of data from the partition base + * @param byte_count Length of the data to encrypt + * @param black_data Location to store the encrypted data + * @param IV IV to use for the encryption routine + * @param cypher_mode Cyphering mode to use, specified by type + * #fsl_shw_cypher_mode_t + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t +do_scc_decrypt_region(fsl_shw_uco_t * user_ctx, + void *partition_base, uint32_t offset_bytes, + uint32_t byte_count, const uint8_t * black_data, + uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode); + + /*! @} *//* miscfuns */ + +/*! @addtogroup opfuns + @{ */ + +/* REQ-S2LRD-PINTFC-API-BASIC-SYM-002 */ +/* PINTFC-API-BASIC-SYM-ARC4-001 */ +/* PINTFC-API-BASIC-SYM-ARC4-002 */ +/*! + * Encrypt a stream of data with a symmetric-key algorithm. + * + * In ARC4, and also in #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_CTR modes, the + * flags of the @a sym_ctx object will control part of the operation of this + * function. The #FSL_SYM_CTX_INIT flag means that there is no context info in + * the object. The #FSL_SYM_CTX_LOAD means to use information in the + * @a sym_ctx at the start of the operation, and the #FSL_SYM_CTX_SAVE flag + * means to update the object's context information after the operation has + * been performed. + * + * All of the data for an operation can be run through at once using the + * #FSL_SYM_CTX_INIT or #FSL_SYM_CTX_LOAD flags, as appropriate, and then using + * a @a length for the whole of the data. + * + * If a #FSL_SYM_CTX_SAVE flag were added, an additional call to the function + * would "pick up" where the previous call left off, allowing the user to + * perform the larger function in smaller steps. + * + * In #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_ECB modes, the @a length must always + * be a multiple of the block size for the algorithm being used. For proper + * operation in #FSL_SYM_MODE_CTR mode, the @a length must be a multiple of the + * block size until the last operation on the total octet stream. + * + * Some users of ARC4 may want to compute the context (S-Box and pointers) from + * the key before any data is available. This may be done by running this + * function with a @a length of zero, with the init & save flags flags on in + * the @a sym_ctx. Subsequent operations would then run as normal with the + * load and save flags. Note that they key object is still required. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info Key and algorithm being used for this operation. + * @param[in,out] sym_ctx Info on cipher mode, state of the cipher. + * @param length Length, in octets, of the pt (and ct). + * @param pt pointer to plaintext to be encrypted. + * @param[out] ct pointer to where to store the resulting ciphertext. + * + * @return A return code of type #fsl_shw_return_t. + * + */ +extern fsl_shw_return_t fsl_shw_symmetric_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * pt, + uint8_t * ct); + +/* PINTFC-API-BASIC-SYM-002 */ +/* PINTFC-API-BASIC-SYM-ARC4-001 */ +/* PINTFC-API-BASIC-SYM-ARC4-002 */ +/*! + * Decrypt a stream of data with a symmetric-key algorithm. + * + * In ARC4, and also in #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_CTR modes, the + * flags of the @a sym_ctx object will control part of the operation of this + * function. The #FSL_SYM_CTX_INIT flag means that there is no context info in + * the object. The #FSL_SYM_CTX_LOAD means to use information in the + * @a sym_ctx at the start of the operation, and the #FSL_SYM_CTX_SAVE flag + * means to update the object's context information after the operation has + * been performed. + * + * All of the data for an operation can be run through at once using the + * #FSL_SYM_CTX_INIT or #FSL_SYM_CTX_LOAD flags, as appropriate, and then using + * a @a length for the whole of the data. + * + * If a #FSL_SYM_CTX_SAVE flag were added, an additional call to the function + * would "pick up" where the previous call left off, allowing the user to + * perform the larger function in smaller steps. + * + * In #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_ECB modes, the @a length must always + * be a multiple of the block size for the algorithm being used. For proper + * operation in #FSL_SYM_MODE_CTR mode, the @a length must be a multiple of the + * block size until the last operation on the total octet stream. + * + * Some users of ARC4 may want to compute the context (S-Box and pointers) from + * the key before any data is available. This may be done by running this + * function with a @a length of zero, with the #FSL_SYM_CTX_INIT & + * #FSL_SYM_CTX_SAVE flags on in the @a sym_ctx. Subsequent operations would + * then run as normal with the load & save flags. Note that they key object is + * still required. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The key and algorithm being used in this operation. + * @param[in,out] sym_ctx Info on cipher mode, state of the cipher. + * @param length Length, in octets, of the ct (and pt). + * @param ct pointer to ciphertext to be decrypted. + * @param[out] pt pointer to where to store the resulting plaintext. + * + * @return A return code of type #fsl_shw_return_t + * + */ +extern fsl_shw_return_t fsl_shw_symmetric_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * ct, + uint8_t * pt); + +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-005 */ +/*! + * Hash a stream of data with a cryptographic hash algorithm. + * + * The flags in the @a hash_ctx control the operation of this function. + * + * Hashing functions work on 64 octets of message at a time. Therefore, when + * any partial hashing of a long message is performed, the message @a length of + * each segment must be a multiple of 64. When ready to + * #FSL_HASH_FLAGS_FINALIZE the hash, the @a length may be any value. + * + * With the #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_FINALIZE flags on, a + * one-shot complete hash, including padding, will be performed. The @a length + * may be any value. + * + * The first octets of a data stream can be hashed by setting the + * #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_SAVE flags. The @a length must be + * a multiple of 64. + * + * The flag #FSL_HASH_FLAGS_LOAD is used to load a context previously saved by + * #FSL_HASH_FLAGS_SAVE. The two in combination will allow a (multiple-of-64 + * octets) 'middle sequence' of the data stream to be hashed with the + * beginning. The @a length must again be a multiple of 64. + * + * Since the flag #FSL_HASH_FLAGS_LOAD is used to load a context previously + * saved by #FSL_HASH_FLAGS_SAVE, the #FSL_HASH_FLAGS_LOAD and + * #FSL_HASH_FLAGS_FINALIZE flags, used together, can be used to finish the + * stream. The @a length may be any value. + * + * If the user program wants to do the padding for the hash, it can leave off + * the #FSL_HASH_FLAGS_FINALIZE flag. The @a length must then be a multiple of + * 64 octets. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] hash_ctx Hashing algorithm and state of the cipher. + * @param msg Pointer to the data to be hashed. + * @param length Length, in octets, of the @a msg. + * @param[out] result If not null, pointer to where to store the hash + * digest. + * @param result_len Number of octets to store in @a result. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_hash(fsl_shw_uco_t * user_ctx, + fsl_shw_hco_t * hash_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len); + +/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-001 */ +/*! + * Precompute the Key hashes for an HMAC operation. + * + * This function may be used to calculate the inner and outer precomputes, + * which are the hash contexts resulting from hashing the XORed key for the + * 'inner hash' and the 'outer hash', respectively, of the HMAC function. + * + * After execution of this function, the @a hmac_ctx will contain the + * precomputed inner and outer contexts, so that they may be used by + * #fsl_shw_hmac(). The flags of @a hmac_ctx will be updated with + * #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT to mark their presence. In addition, the + * #FSL_HMAC_FLAGS_INIT flag will be set. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The key being used in this operation. Key must be + * 1 to 64 octets long. + * @param[in,out] hmac_ctx The context which controls, by its flags and + * algorithm, the operation of this function. + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_hmac_precompute(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx); + +/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-002 */ +/*! + * Continue, finalize, or one-shot an HMAC operation. + * + * There are a number of ways to use this function. The flags in the + * @a hmac_ctx object will determine what operations occur. + * + * If #FSL_HMAC_FLAGS_INIT is set, then the hash will be started either from + * the @a key_info, or from the precomputed inner hash value in the + * @a hmac_ctx, depending on the value of #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT. + * + * If, instead, #FSL_HMAC_FLAGS_LOAD is set, then the hash will be continued + * from the ongoing inner hash computation in the @a hmac_ctx. + * + * If #FSL_HMAC_FLAGS_FINALIZE are set, then the @a msg will be padded, hashed, + * the outer hash will be performed, and the @a result will be generated. + * + * If the #FSL_HMAC_FLAGS_SAVE flag is set, then the (ongoing or final) digest + * value will be stored in the ongoing inner hash computation field of the @a + * hmac_ctx. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info If #FSL_HMAC_FLAGS_INIT is set in the @a hmac_ctx, + * this is the key being used in this operation, and the + * IPAD. If #FSL_HMAC_FLAGS_INIT is set in the @a + * hmac_ctx and @a key_info is NULL, then + * #fsl_shw_hmac_precompute() has been used to populate + * the @a inner_precompute and @a outer_precompute + * contexts. If #FSL_HMAC_FLAGS_INIT is not set, this + * parameter is ignored. + + * @param[in,out] hmac_ctx The context which controls, by its flags and + * algorithm, the operation of this function. + * @param msg Pointer to the message to be hashed. + * @param length Length, in octets, of the @a msg. + * @param[out] result Pointer, of @a result_len octets, to where to + * store the HMAC. + * @param result_len Length of @a result buffer. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_hmac(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len); + +/* REQ-S2LRD-PINTFC-API-BASIC-RNG-002 */ +/*! + * Get random data. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param length The number of octets of @a data being requested. + * @param[out] data A pointer to a location of @a length octets to where + * random data will be returned. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data); + +/* REQ-S2LRD-PINTFC-API-BASIC-RNG-002 */ +/*! + * Add entropy to random number generator. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param length Number of bytes at @a data. + * @param data Entropy to add to random number generator. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data); + +/*! + * Perform Generation-Encryption by doing a Cipher and a Hash. + * + * Generate the authentication value @a auth_value as well as encrypt the @a + * payload into @a ct (the ciphertext). This is a one-shot function, so all of + * the @a auth_data and the total message @a payload must passed in one call. + * This also means that the flags in the @a auth_ctx must be #FSL_ACCO_CTX_INIT + * and #FSL_ACCO_CTX_FINALIZE. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param auth_ctx Controlling object for Authenticate-decrypt. + * @param cipher_key_info The key being used for the cipher part of this + * operation. In CCM mode, this key is used for + * both parts. + * @param auth_key_info The key being used for the authentication part + * of this operation. In CCM mode, this key is + * ignored and may be NULL. + * @param auth_data_length Length, in octets, of @a auth_data. + * @param auth_data Data to be authenticated but not encrypted. + * @param payload_length Length, in octets, of @a payload. + * @param payload Pointer to the plaintext to be encrypted. + * @param[out] ct Pointer to the where the encrypted @a payload + * will be stored. Must be @a payload_length + * octets long. + * @param[out] auth_value Pointer to where the generated authentication + * field will be stored. Must be as many octets as + * indicated by MAC length in the @a function_ctx. + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_gen_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + fsl_shw_sko_t * cipher_key_info, + fsl_shw_sko_t * auth_key_info, + uint32_t auth_data_length, + const uint8_t * auth_data, + uint32_t payload_length, + const uint8_t * payload, + uint8_t * ct, uint8_t * auth_value); + +/*! + * Perform Authentication-Decryption in Cipher + Hash. + * + * This function will perform a one-shot decryption of a data stream as well as + * authenticate the authentication value. This is a one-shot function, so all + * of the @a auth_data and the total message @a payload must passed in one + * call. This also means that the flags in the @a auth_ctx must be + * #FSL_ACCO_CTX_INIT and #FSL_ACCO_CTX_FINALIZE. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param auth_ctx Controlling object for Authenticate-decrypt. + * @param cipher_key_info The key being used for the cipher part of this + * operation. In CCM mode, this key is used for + * both parts. + * @param auth_key_info The key being used for the authentication part + * of this operation. In CCM mode, this key is + * ignored and may be NULL. + * @param auth_data_length Length, in octets, of @a auth_data. + * @param auth_data Data to be authenticated but not decrypted. + * @param payload_length Length, in octets, of @a ct and @a pt. + * @param ct Pointer to the encrypted input stream. + * @param auth_value The (encrypted) authentication value which will + * be authenticated. This is the same data as the + * (output) @a auth_value argument to + * #fsl_shw_gen_encrypt(). + * @param[out] payload Pointer to where the plaintext resulting from + * the decryption will be stored. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_auth_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + fsl_shw_sko_t * cipher_key_info, + fsl_shw_sko_t * auth_key_info, + uint32_t auth_data_length, + const uint8_t * auth_data, + uint32_t payload_length, + const uint8_t * ct, + const uint8_t * auth_value, + uint8_t * payload); + +/*! + * Establish the key in a protected location, which can be the system keystore, + * user keystore, or (on platforms that support it) as a Platform Key. + * + * By default, keys initialized with #fsl_shw_sko_init() will be placed into + * the system keystore. The user can cause the key to be established in a + * user keystore by first calling #fsl_shw_sko_set_keystore() on the key. + * Normally, keys in the system keystore can only be used for hardware + * encrypt or decrypt operations, however if the #FSL_SKO_KEY_SW_KEY flag is + * applied using #fsl_shw_sko_set_flags(), the key will be established as a + * software key, which can then be read out using #fsl_shw_read_key(). + * + * Keys initialized with #fsl_shw_sko_init_pf_key() are established as a + * Platform Key. Their use is covered in @ref di_sec. + * + * This function only needs to be used when unwrapping a key, setting up a key + * which could be wrapped with a later call to #fsl_shw_extract_key(), or + * setting up a key as a Platform Key. Normal cleartext keys can simply be + * placed into #fsl_shw_sko_t key objects with #fsl_shw_sko_set_key() and used + * directly. + * + * The maximum key size supported for wrapped/unwrapped keys is 32 octets. + * (This is the maximum reasonable key length on Sahara - 32 octets for an HMAC + * key based on SHA-256.) The key size is determined by the @a key_info. The + * expected length of @a key can be determined by + * #fsl_shw_sko_calculate_wrapped_size() + * + * The protected key will not be available for use until this operation + * successfully completes. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] key_info The information about the key to be which will + * be established. In the create case, the key + * length must be set. + * @param establish_type How @a key will be interpreted to establish a + * key for use. + * @param key If @a establish_type is #FSL_KEY_WRAP_UNWRAP, + * this is the location of a wrapped key. If + * @a establish_type is #FSL_KEY_WRAP_CREATE, this + * parameter can be @a NULL. If @a establish_type + * is #FSL_KEY_WRAP_ACCEPT, this is the location + * of a plaintext key. + */ +extern fsl_shw_return_t fsl_shw_establish_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_key_wrap_t establish_type, + const uint8_t * key); + +/*! + * Read the key value from a key object. + * + * Only a key marked as a software key (#FSL_SKO_KEY_SW_KEY) can be read with + * this call. It has no effect on the status of the key store. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The referenced key. + * @param[out] key The location to store the key value. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_read_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + uint8_t * key); + +/*! + * Wrap a key and retrieve the wrapped value. + * + * A wrapped key is a key that has been cryptographically obscured. It is + * only able to be used with keys that have been established by + * #fsl_shw_establish_key(). + * + * For keys established in the system or user keystore, this function will + * also release the key (see #fsl_shw_release_key()) so that it must be re- + * established before reuse. This function will not release keys that are + * established as a Platform Key, so a call to #fsl_shw_release_key() is + * necessary to release those keys. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The information about the key to be deleted. + * @param[out] covered_key The location to store the wrapped key. + * (This size is based upon the maximum key size + * of 32 octets). + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + uint8_t * covered_key); + +/*! + * De-establish a key so that it can no longer be accessed. + * + * The key will need to be re-established before it can again be used. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The information about the key to be deleted. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_release_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info); + +/*! + * Cause the hardware to create a new random key for use by the secure memory + * encryption hardware. + * + * Have the hardware use the secure hardware random number generator to load a + * new secret key into the system's Random Key register. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_gen_random_pf_key(fsl_shw_uco_t * user_ctx); + +/*! + * Retrieve the detected tamper event. + * + * Note that if more than one event was detected, this routine will only ever + * return one of them. + * + * @param[in] user_ctx A user context from #fsl_shw_register_user(). + * @param[out] tamperp Location to store the tamper information. + * @param[out] timestampp Locate to store timestamp from hardwhare when + * an event was detected. + * + * + * @return A return code of type #fsl_shw_return_t (for instance, if the platform + * is not in a fail state. + */ +extern fsl_shw_return_t fsl_shw_read_tamper_event(fsl_shw_uco_t * user_ctx, + fsl_shw_tamper_t * tamperp, + uint64_t * timestampp); + +/*! @} *//* opfuns */ + +/* Insert example code into the API documentation. */ + +/*! + * @example apitest.c + */ + +/*! + * @example sym.c + */ + +/*! + * @example rand.c + */ + +/*! + * @example hash.c + */ + +/*! + * @example hmac1.c + */ + +/*! + * @example hmac2.c + */ + +/*! + * @example gen_encrypt.c + */ + +/*! + * @example auth_decrypt.c + */ + +/*! + * @example wrapped_key.c + */ + +/*! + * @example smalloc.c + */ + +/*! + * @example user_keystore.c + */ + +/*! + * @example dryice.c + */ + +#endif /* API_DOC */ + +#endif /* FSL_SHW_H */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/include/fsl_shw_keystore.h linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/fsl_shw_keystore.h --- linux-2.6.26/drivers/mxc/security/sahara2/include/fsl_shw_keystore.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/fsl_shw_keystore.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,475 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +#ifndef FSL_SHW_KEYSTORE_H +#define FSL_SHW_KEYSTORE_H + +/*! + * @file fsl_shw_keystore.h + * + * @brief Definition of the User Keystore API. + * + */ + +/*! \page user_keystore User Keystore API + * + * Definition of the User Keystore API. + * + * On platforms with multiple partitions of Secure Memory, the Keystore Object + * (#fsl_shw_kso_t) is provided to allow users to manage a private keystore for + * use in software cryptographic routines. The user can define a custom set of + * methods for managing their keystore, or use a default keystore handler. The + * keystore is established by #fsl_shw_establish_keystore(), and released by + * #fsl_shw_release_keystore(). The intent of this design is to make the + * keystore implementation as flexible as possible. + * + * See @ref keystore_api for the generic keystore API, and @ref + * default_keystore for the default keystore implementation. + * + */ + +/*! + * @defgroup keystore_api User Keystore API + * + * Keystore API + * + * These functions define the generic keystore API, which can be used in + * conjunction with a keystore implementation backend to support a user + * keystore. + */ + +/*! + * @defgroup default_keystore Default Keystore Implementation + * + * Default Keystore Implementation + * + * These functions define the default keystore implementation, which is used + * for the system keystore and for user keystores initialized by + * #fsl_shw_init_keystore_default(). They can be used as-is or as a reference + * for creating a custom keystore handler. It uses an entire Secure Memory + * partition, divided in to equal slots of length #KEYSTORE_SLOT_SIZE. These + * functions are not intended to be used directly- all user interaction with + * the keystore should be through the @ref keystore_api and the Wrapped Key + * interface. + * + * The current implementation is designed to work with both SCC and SCC2. + * Differences between the two versions are noted below. + */ + +/*! @addtogroup keystore_api + @{ */ + +#ifndef KEYSTORE_SLOT_SIZE +/*! Size of each key slot, in octets. This sets an upper bound on the size + * of a key that can placed in the keystore. + */ +#define KEYSTORE_SLOT_SIZE 32 +#endif + +/*! + * Initialize a Keystore Object. + * + * This function must be called before performing any other operation with the + * Object. It allows the user to associate a custom keystore interface by + * specifying the correct set of functions that will be used to perform actions + * on the keystore object. To use the default keystore handler, the function + * #fsl_shw_init_keystore_default() can be used instead. + * + * @param keystore The Keystore object to operate on. + * @param data_init Keystore initialization function. This function is + * responsible for initializing the keystore. A + * user-defined object can be assigned to the user_data + * pointer, and will be passed to any function acting on + * that keystore. It is called during + * #fsl_shw_establish_keystore(). + * @param data_cleanup Keystore cleanup function. This function cleans up + * any data structures associated with the keyboard. It + * is called by #fsl_shw_release_keystore(). + * @param slot_alloc Slot allocation function. This function allocates a + * key slot, potentially based on size and owner id. It + * is called by #fsl_shw_establish_key(). + * @param slot_dealloc Slot deallocation function. + * @param slot_verify_access Function to verify that a given Owner ID + * credential matches the given slot. + * @param slot_get_address For SCC2: Get the virtual address (kernel or + * userspace) of the data stored in the slot. + * For SCC: Get the physical address of the data + * stored in the slot. + * @param slot_get_base For SCC2: Get the (virtual) base address of the + * partition that the slot is located on. + * For SCC: Not implemented. + * @param slot_get_offset For SCC2: Get the offset from the start of the + * partition that the slot data is located at (in + * octets) + * For SCC: Not implemented. + * @param slot_get_slot_size Get the size of the key slot, in octets. + */ +extern void fsl_shw_init_keystore(fsl_shw_kso_t * keystore, + fsl_shw_return_t(*data_init) (fsl_shw_uco_t * + user_ctx, + void + **user_data), + void (*data_cleanup) (fsl_shw_uco_t * + user_ctx, + void **user_data), + fsl_shw_return_t(*slot_alloc) (void + *user_data, + uint32_t size, + uint64_t + owner_id, + uint32_t * + slot), + fsl_shw_return_t(*slot_dealloc) (void + *user_data, + uint64_t + owner_id, + uint32_t + slot), + fsl_shw_return_t(*slot_verify_access) (void + *user_data, + uint64_t + owner_id, + uint32_t + slot), + void *(*slot_get_address) (void *user_data, + uint32_t handle), + uint32_t(*slot_get_base) (void *user_data, + uint32_t handle), + uint32_t(*slot_get_offset) (void *user_data, + uint32_t handle), + uint32_t(*slot_get_slot_size) (void + *user_data, + uint32_t + handle)); + +/*! + * Initialize a Keystore Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the user keystore object up to use the default keystore + * handler. If a custom keystore handler is desired, the function + * #fsl_shw_init_keystore() can be used instead. + * + * @param keystore The Keystore object to operate on. + */ +extern void fsl_shw_init_keystore_default(fsl_shw_kso_t * keystore); + +/*! + * Establish a Keystore Object. + * + * This function establishes a keystore object that has been set up by a call + * to #fsl_shw_init_keystore(). It is a wrapper for the user-defined + * data_init() function, which is specified during keystore initialization. + * + * @param user_ctx The user context that this keystore should be attached + * to + * @param keystore The Keystore object to operate on. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_establish_keystore(fsl_shw_uco_t * user_ctx, + fsl_shw_kso_t * keystore); + +/*! + * Release a Keystore Object. + * + * This function releases an established keystore object. It is a wrapper for + * the user-defined data_cleanup() function, which is specified during keystore + * initialization. + * + * @param user_ctx The user context that this keystore should be attached + * to. + * @param keystore The Keystore object to operate on. + */ +extern void fsl_shw_release_keystore(fsl_shw_uco_t * user_ctx, + fsl_shw_kso_t * keystore); + +/*! + * Allocate a slot in the Keystore. + * + * This function attempts to allocate a slot to hold a key in the keystore. It + * is called by #fsl_shw_establish_key() when establishing a Secure Key Object, + * if the key has been flagged to be stored in a user keystore by the + * #fsl_shw_sko_set_keystore() function. It is a wrapper for the + * implementation-specific function slot_alloc(). + * + * @param keystore The Keystore object to operate on. + * @param[in] size Size of the key to be stored (octets). + * @param[in] owner_id ID of the key owner. + * @param[out] slot If successful, assigned slot ID + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t keystore_slot_alloc(fsl_shw_kso_t * keystore, + uint32_t size, + uint64_t owner_id, uint32_t * slot); + +/*! + * Deallocate a slot in the Keystore. + * + * This function attempts to allocate a slot to hold a key in the keystore. + * It is called by #fsl_shw_extract_key() and #fsl_shw_release_key() when the + * key that it contains is to be released. It is a wrapper for the + * implmentation-specific function slot_dealloc(). + + * @param keystore The Keystore object to operate on. + * @param[in] owner_id ID of the key owner. + * @param[in] slot If successful, assigned slot ID. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t keystore_slot_dealloc(fsl_shw_kso_t * keystore, + uint64_t owner_id, uint32_t slot); + +/*! + * Load cleartext key data into a key slot + * + * This function loads a key slot with cleartext data. + * + * @param keystore The Keystore object to operate on. + * @param[in] owner_id ID of the key owner. + * @param[in] slot If successful, assigned slot ID. + * @param[in] key_data Pointer to the location of the cleartext key data. + * @param[in] key_length Length of the key data (octets). + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t +keystore_slot_load(fsl_shw_kso_t * keystore, uint64_t owner_id, uint32_t slot, + const uint8_t * key_data, uint32_t key_length); + +/*! + * Read cleartext key data from a key slot + * + * This function returns the key in a key slot. + * + * @param keystore The Keystore object to operate on. + * @param[in] owner_id ID of the key owner. + * @param[in] slot ID of slot where key resides. + * @param[in] key_length Length of the key data (octets). + * @param[out] key_data Pointer to the location of the cleartext key data. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t +keystore_slot_read(fsl_shw_kso_t * keystore, uint64_t owner_id, uint32_t slot, + uint32_t key_length, uint8_t * key_data); + +/*! + * Encrypt a keyslot + * + * This function encrypts a key using the hardware secret key. + * + * @param user_ctx User context + * @param keystore The Keystore object to operate on. + * @param[in] owner_id ID of the key owner. + * @param[in] slot Slot ID of the key to encrypt. + * @param[in] length Length of the key + * @param[out] destination Pointer to the location where the encrypted data + * is to be stored. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t +keystore_slot_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_kso_t * keystore, uint64_t owner_id, + uint32_t slot, uint32_t length, uint8_t * destination); + +/*! + * Decrypt a keyslot + * + * This function decrypts a key using the hardware secret key. + * + * @param user_ctx User context + * @param keystore The Keystore object to operate on. + * @param[in] owner_id ID of the key owner. + * @param[in] slot Slot ID of the key to encrypt. + * @param[in] length Length of the key + * @param[in] source Pointer to the location where the encrypted data + * is stored. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t +keystore_slot_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_kso_t * keystore, uint64_t owner_id, + uint32_t slot, uint32_t length, const uint8_t * source); + +/* @} */ + +/*! @addtogroup default_keystore + @{ */ + +/*! + * Data structure to hold per-slot information + */ +typedef struct keystore_data_slot_info_t { + uint8_t allocated; /*!< Track slot assignments */ + uint64_t owner; /*!< Owner IDs */ + uint32_t key_length; /*!< Size of the key */ +} keystore_data_slot_info_t; + +/*! + * Data structure to hold keystore information. + */ +typedef struct keystore_data_t { + void *base_address; /*!< Base of the Secure Partition */ + uint32_t slot_count; /*!< Number of slots in the keystore */ + struct keystore_data_slot_info_t *slot; /*!< Per-slot information */ +} keystore_data_t; + +/*! + * Default keystore initialization routine. + * + * This function acquires a Secure Partition Object to store the keystore, + * divides it into slots of length #KEYSTORE_SLOT_SIZE, and builds a data + * structure to hold key information. + * + * @param user_ctx User context + * @param[out] user_data Pointer to the location where the keystore data + * structure is to be stored. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t shw_kso_init_data(fsl_shw_uco_t * user_ctx, void **user_data); + +/*! + * Default keystore cleanup routine. + * + * This function releases the Secure Partition Object and the memory holding + * the keystore data structure, that obtained by the shw_kso_init_data + * function. + * + * @param user_ctx User context + * @param[in,out] user_data Pointer to the location where the keystore data + * structure is stored. + */ +void shw_kso_cleanup_data(fsl_shw_uco_t * user_ctx, void **user_data); + +/*! + * Default keystore slot access verification + * + * This function compares the supplied Owner ID to the registered owner of + * the key slot, to see if the supplied ID is correct. + * + * @param[in] user_data Pointer to the location where the keystore data + * structure stored. + * @param[in] owner_id Owner ID supplied as a credential. + * @param[in] slot Requested slot + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t shw_slot_verify_access(void *user_data, uint64_t owner_id, + uint32_t slot); + +/*! + * Default keystore slot allocation + * + * This function first checks that the requested size is equal to or less than + * the maximum keystore slot size. If so, it searches the keystore for a free + * key slot, and if found, marks it as used and returns a slot reference to the + * user. + * + * @param[in] user_data Pointer to the location where the keystore data + * structure stored. + * @param[in] size Size of the key data that will be stored in this slot + * (octets) + * @param[in] owner_id Owner ID supplied as a credential. + * @param[out] slot Requested slot + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t shw_slot_alloc(void *user_data, uint32_t size, + uint64_t owner_id, uint32_t * slot); + +/*! + * Default keystore slot deallocation + * + * This function releases the given key slot in the keystore, making it + * available to store a new key. + * + * @param[in] user_data Pointer to the location where the keystore data + * structure stored. + * @param[in] owner_id Owner ID supplied as a credential. + * @param[in] slot Requested slot + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t shw_slot_dealloc(void *user_data, + uint64_t owner_id, uint32_t slot); + +/*! + * Default keystore slot address lookup + * + * This function calculates the address where the key data is stored. + * + * @param[in] user_data Pointer to the location where the keystore data + * structure stored. + * @param[in] slot Requested slot + * + * @return SCC2: Virtual address (kernel or userspace) of the key data. + * SCC: Physical address of the key data. + */ +void *shw_slot_get_address(void *user_data, uint32_t slot); + +/*! + * Default keystore slot base address lookup + * + * This function calculates the base address of the Secure Partition on which + * the key data is located. For the reference design, only one Secure + * Partition is used per Keystore, however in general, any number may be used. + * + * @param[in] user_data Pointer to the location where the keystore data + * structure stored. + * @param[in] slot Requested slot + * + * @return SCC2: Secure Partition virtual (kernel or userspace) base address. + * SCC: Secure Partition physical base address. + */ +uint32_t shw_slot_get_base(void *user_data, uint32_t slot); + +/*! + * Default keystore slot offset lookup + * + * This function calculates the offset from the base of the Secure Partition + * where the key data is located. + * + * @param[in] user_data Pointer to the location where the keystore data + * structure stored. + * @param[in] slot Requested slot + * + * @return SCC2: Key data offset (octets) + * SCC: Not implemented + */ +uint32_t shw_slot_get_offset(void *user_data, uint32_t slot); + +/*! + * Default keystore slot offset lookup + * + * This function returns the size of the given key slot. In the reference + * implementation, all key slots are of the same size, however in general, + * the keystore slot sizes can be made variable. + * + * @param[in] user_data Pointer to the location where the keystore data + * structure stored. + * @param[in] slot Requested slot + * + * @return SCC2: Keystore slot size. + * SCC: Not implemented + */ +uint32_t shw_slot_get_slot_size(void *user_data, uint32_t slot); + +/* @} */ + +#endif /* FSL_SHW_KEYSTORE_H */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/include/linux_port.h linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/linux_port.h --- linux-2.6.26/drivers/mxc/security/sahara2/include/linux_port.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/linux_port.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,1808 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file linux_port.h + * + * OS_PORT ported to Linux (2.6.9+ for now) + * + */ + + /*! + * @if USE_MAINPAGE + * @mainpage ==Linux version of== Generic OS API for STC Drivers + * @endif + * + * @section intro_sec Introduction + * + * This API / kernel programming environment blah blah. + * + * See @ref dkops "Driver-to-Kernel Operations" as a good place to start. + */ + +#ifndef LINUX_PORT_H +#define LINUX_PORT_H + +#define PORTABLE_OS_VERSION 101 + +/* Linux Kernel Includes */ +#include /* Current version Linux kernel */ + +#if defined(CONFIG_MODVERSIONS) && ! defined(MODVERSIONS) +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) +#include +#endif +#define MODVERSIONS +#endif +/*! + * __NO_VERSION__ defined due to Kernel module possibly spanning multiple + * files. + */ +#define __NO_VERSION__ + +#include /* Basic support for loadable modules, + printk */ +#include /* module_init, module_exit */ +#include /* General kernel system calls */ +#include /* for interrupt.h */ +#include /* for inode */ +#include +#include +#include +#include +#include /* kmalloc */ + +#include + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) +#include /* used in dynamic power management */ +#else +#include /* used in dynamic power management */ +#endif + +#include +#include + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) +#include /* clock en/disable for DPM */ +#else +#include /* clock en/disable for DPM */ +#endif + +#include +#include + +#include /* copy_to_user(), copy_from_user() */ +#include /* ioremap() */ +#include +#include + +#ifndef TRUE +/*! Useful symbol for unsigned values used as flags. */ +#define TRUE 1 +#endif + +#ifndef FALSE +/*! Useful symbol for unsigned values used as flags. */ +#define FALSE 0 +#endif + +/* These symbols are defined in Linux 2.6 and later. Include here for minimal + * support of 2.4 kernel. + **/ +#if !defined(LINUX_VERSION_CODE) || LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +/*! + * Symbol defined somewhere in 2.5/2.6. It is the return signature of an ISR. + */ +#define irqreturn_t void +/*! Possible return value of 'modern' ISR routine. */ +#define IRQ_HANDLED +/*! Method of generating value of 'modern' ISR routine. */ +#define IRQ_RETVAL(x) +#endif + +/*! + * Type used for registering and deregistering interrupts. + */ +typedef int os_interrupt_id_t; + +/*! + * Type used as handle for a process + * + * See #os_get_process_handle() and #os_send_signal(). + */ +/* + * The following should be defined this way, but it gets compiler errors + * on the current tool chain. + * + * typedef task_t *os_process_handle_t; + */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) +typedef task_t *os_process_handle_t; +#else +typedef struct task_struct *os_process_handle_t; +#endif + +/*! + * Generic return code for functions which need such a thing. + * + * No knowledge should be assumed of the value of any of these symbols except + * that @c OS_ERROR_OK_S is guaranteed to be zero. + */ +typedef enum { + OS_ERROR_OK_S = 0, /*!< Success */ + OS_ERROR_FAIL_S = -EIO, /*!< Generic driver failure */ + OS_ERROR_NO_MEMORY_S = -ENOMEM, /*!< Failure to acquire/use memory */ + OS_ERROR_BAD_ADDRESS_S = -EFAULT, /*!< Bad address */ + OS_ERROR_BAD_ARG_S = -EINVAL, /*!< Bad input argument */ +} os_error_code; + +/*! + * Handle to a lock. + */ +#ifdef CONFIG_PREEMPT_RT +typedef raw_spinlock_t *os_lock_t; +#else +typedef spinlock_t *os_lock_t; +#endif + +/*! + * Context while locking. + */ +typedef unsigned long os_lock_context_t; + +/*! + * Declare a wait object for sleeping/waking processes. + */ +#define OS_WAIT_OBJECT(name) \ + DECLARE_WAIT_QUEUE_HEAD(name##_qh) + +/*! + * Driver registration handle + * + * Used with #os_driver_init_registration(), #os_driver_add_registration(), + * and #os_driver_complete_registration(). + */ +typedef struct { + unsigned reg_complete; /*!< TRUE if next inits succeeded. */ + dev_t dev; /*!< dev_t for register_chrdev() */ + struct file_operations fops; /*!< struct for register_chrdev() */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13) + struct class_simple *cs; /*!< results of class_simple_create() */ +#else + struct class *cs; /*!< results of class_create() */ +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) + struct class_device *cd; /*!< Result of class_device_create() */ +#else + struct device *cd; /*!< Result of device_create() */ +#endif + unsigned power_complete; /*!< TRUE if next inits succeeded */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + struct device_driver dd; /*!< struct for register_driver() */ +#else + struct platform_driver dd; /*!< struct for register_driver() */ +#endif + struct platform_device pd; /*!< struct for platform_register_device() */ +} os_driver_reg_t; + +/* + * Function types which can be associated with driver entry points. + * + * Note that init and shutdown are absent. + */ +/*! @{ */ +/*! Keyword for registering open() operation handler. */ +#define OS_FN_OPEN open +/*! Keyword for registering close() operation handler. */ +#define OS_FN_CLOSE release +/*! Keyword for registering read() operation handler. */ +#define OS_FN_READ read +/*! Keyword for registering write() operation handler. */ +#define OS_FN_WRITE write +/*! Keyword for registering ioctl() operation handler. */ +#define OS_FN_IOCTL ioctl +/*! Keyword for registering mmap() operation handler. */ +#define OS_FN_MMAP mmap +/*! @} */ + +/*! + * Function signature for the portable interrupt handler + * + * While it would be nice to know which interrupt is being serviced, the + * Least Common Denominator rule says that no arguments get passed in. + * + * @return Zero if not handled, non-zero if handled. + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) +typedef int (*os_interrupt_handler_t) (int, void *, struct pt_regs *); +#else +typedef int (*os_interrupt_handler_t) (int, void *); +#endif + +/*! + * @defgroup dkops Driver-to-Kernel Operations + * + * These are the operations which drivers should call to get the OS to perform + * services. + */ + +/*! @addtogroup dkops */ +/*! @{ */ + +/*! + * Register an interrupt handler. + * + * @param driver_name The name of the driver + * @param interrupt_id The interrupt line to monitor (type + * #os_interrupt_id_t) + * @param function The function to be called to handle an interrupt + * + * @return #os_error_code + */ +#define os_register_interrupt(driver_name, interrupt_id, function) \ + request_irq(interrupt_id, function, 0, driver_name, NULL) + +/*! + * Deregister an interrupt handler. + * + * @param interrupt_id The interrupt line to stop monitoring + * + * @return #os_error_code + */ +#define os_deregister_interrupt(interrupt_id) \ + free_irq(interrupt_id, NULL) + +/*! + * INTERNAL implementation of os_driver_init_registration() + * + * @return An os error code. + */ +inline static int os_drv_do_init_reg(os_driver_reg_t * handle) +{ + memset(handle, 0, sizeof(*handle)); + handle->fops.owner = THIS_MODULE; + handle->power_complete = FALSE; + handle->reg_complete = FALSE; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + handle->dd.name = NULL; +#else + handle->dd.driver.name = NULL; +#endif + + return OS_ERROR_OK_S; +} + +/*! + * Initialize driver registration. + * + * If the driver handles open(), close(), ioctl(), read(), write(), or mmap() + * calls, then it needs to register their location with the kernel so that they + * get associated with the device. + * + * @param handle The handle object to be used with this registration. The + * object must live (be in memory somewhere) at least until + * os_driver_remove_registration() is called. + * + * @return A handle for further driver registration, or NULL if failed. + */ +#define os_driver_init_registration(handle) \ + os_drv_do_init_reg(&handle) + +/*! + * Add a function registration to driver registration. + * + * @param handle A handle initialized by #os_driver_init_registration(). + * @param name Which function is being supported. + * @param function The result of a call to a @c _REF version of one of the + * driver function signature macros + * @return void + */ +#define os_driver_add_registration(handle, name, function) \ + do {handle.fops.name = (void*)(function); } while (0) + +/*! + * Record 'power suspend' function for the device. + * + * @param handle A handle initialized by #os_driver_init_registration(). + * @param function Name of function to call on power suspend request + * + * Status: Provisional + * + * @return void + */ +#define os_driver_register_power_suspend(handle, function) \ + handle.dd.suspend = function + +/*! + * Record 'power resume' function for the device. + * + * @param handle A handle initialized by #os_driver_init_registration(). + * @param function Name of function to call on power resume request + * + * Status: Provisional + * + * @return void + */ +#define os_driver_register_resume(handle, function) \ + handle.dd.resume = function + +/*! + * INTERNAL function of the Linux port of the OS API. Implements the + * os_driver_complete_registration() function. + * + * @param handle The handle used with #os_driver_init_registration(). + * @param major The major device number to be associated with the driver. + * If this value is zero, a major number may be assigned. + * See #os_driver_get_major() to determine final value. + * #os_driver_remove_registration(). + * @param driver_name The driver name. Can be used as part of 'device node' + * name on platforms which support such a feature. + * + * @return An error code + */ +inline static int os_drv_do_reg(os_driver_reg_t * handle, + unsigned major, char *driver_name) +{ + os_error_code code = OS_ERROR_NO_MEMORY_S; + char *name = kmalloc(strlen(driver_name) + 1, 0); + + if (name != NULL) { + memcpy(name, driver_name, strlen(driver_name) + 1); + code = OS_ERROR_OK_S; /* OK so far */ + /* If any chardev/POSIX routines were added, then do chrdev part */ + if (handle->fops.open || handle->fops.release + || handle->fops.read || handle->fops.write + || handle->fops.ioctl || handle->fops.mmap) { + + printk("ioctl pointer: %p. mmap pointer: %p\n", + handle->fops.ioctl, handle->fops.mmap); + + /* this method is depricated, see: + * http://lwn.net/Articles/126808/ + */ + code = + register_chrdev(major, driver_name, &handle->fops); + + /* instead something like this: */ +#if 0 + handle->dev = MKDEV(major, 0); + code = + register_chrdev_region(handle->dev, 1, driver_name); + if (code < 0) { + code = OS_ERROR_FAIL_S; + } else { + cdev_init(&handle->cdev, &handle->fops); + code = cdev_add(&handle->cdev, major, 1); + } +#endif + + if (code < 0) { + code = OS_ERROR_FAIL_S; + } else { + if (code != 0) { + /* Zero was passed in for major; code is actual value */ + handle->dev = MKDEV(code, 0); + } else { + handle->dev = MKDEV(major, 0); + } + code = OS_ERROR_OK_S; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13) + handle->cs = + class_simple_create(THIS_MODULE, + driver_name); + if (IS_ERR(handle->cs)) { + code = (os_error_code) handle->cs; + handle->cs = NULL; + } else { + handle->cd = + class_simple_device_add(handle->cs, + handle->dev, + NULL, + driver_name); + if (IS_ERR(handle->cd)) { + class_simple_device_remove + (handle->dev); + unregister_chrdev(MAJOR + (handle->dev), + driver_name); + code = + (os_error_code) handle->cs; + handle->cs = NULL; + } else { + handle->reg_complete = TRUE; + } + } +#else + handle->cs = + class_create(THIS_MODULE, driver_name); + if (IS_ERR(handle->cs)) { + code = (os_error_code) handle->cs; + handle->cs = NULL; + } else { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) + handle->cd = + class_device_create(handle->cs, + NULL, + handle->dev, + NULL, + driver_name); +#else + handle->cd = + device_create(handle->cs, NULL, + handle->dev, + driver_name); +#endif + if (IS_ERR(handle->cd)) { + class_destroy(handle->cs); + unregister_chrdev(MAJOR + (handle->dev), + driver_name); + code = + (os_error_code) handle->cs; + handle->cs = NULL; + } else { + handle->reg_complete = TRUE; + } + } +#endif + } + } + /* ... fops routine registered */ + /* Handle power management fns through separate interface */ + if ((code == OS_ERROR_OK_S) && + (handle->dd.suspend || handle->dd.resume)) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + handle->dd.name = name; + handle->dd.bus = &platform_bus_type; + code = driver_register(&handle->dd); +#else + handle->dd.driver.name = name; + handle->dd.driver.bus = &platform_bus_type; + code = driver_register(&handle->dd.driver); +#endif + if (code == OS_ERROR_OK_S) { + handle->pd.name = name; + handle->pd.id = 0; + code = platform_device_register(&handle->pd); + if (code != OS_ERROR_OK_S) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + driver_unregister(&handle->dd); +#else + driver_unregister(&handle->dd.driver); +#endif + } else { + handle->power_complete = TRUE; + } + } + } /* ... suspend or resume */ + } /* name != NULL */ + return code; +} + +/*! + * Finalize the driver registration with the kernel. + * + * Upon return from this call, the driver may begin receiving calls at the + * defined entry points. + * + * @param handle The handle used with #os_driver_init_registration(). + * @param major The major device number to be associated with the driver. + * If this value is zero, a major number may be assigned. + * See #os_driver_get_major() to determine final value. + * #os_driver_remove_registration(). + * @param driver_name The driver name. Can be used as part of 'device node' + * name on platforms which support such a feature. + * + * @return An error code + */ +#define os_driver_complete_registration(handle, major, driver_name) \ + os_drv_do_reg(&handle, major, driver_name) + +/*! + * Get driver Major Number from handle after a successful registration. + * + * @param handle A handle which has completed registration. + * + * @return The major number (if any) associated with the handle. + */ +#define os_driver_get_major(handle) \ + (handle.reg_complete ? MAJOR(handle.dev) : -1) + +/*! + * INTERNAL implemention of os_driver_remove_registration. + * + * @param handle A handle initialized by #os_driver_init_registration(). + * + * @return An error code. + */ +inline static int os_drv_rmv_reg(os_driver_reg_t * handle) +{ + if (handle->reg_complete) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13) + if (handle->cd != NULL) { + class_simple_device_remove(handle->dev); + handle->cd = NULL; + } + if (handle->cs != NULL) { + class_simple_destroy(handle->cs); + handle->cs = NULL; + } + unregister_chrdev(MAJOR(handle->dev), handle->dd.name); +#else + if (handle->cd != NULL) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) + class_device_destroy(handle->cs, handle->dev); +#else + device_destroy(handle->cs, handle->dev); +#endif + handle->cd = NULL; + } + if (handle->cs != NULL) { + class_destroy(handle->cs); + handle->cs = NULL; + } + unregister_chrdev(MAJOR(handle->dev), handle->dd.driver.name); +#endif + handle->reg_complete = FALSE; + } + if (handle->power_complete) { + platform_device_unregister(&handle->pd); +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + driver_unregister(&handle->dd); +#else + driver_unregister(&handle->dd.driver); +#endif + handle->power_complete = FALSE; + } +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + if (handle->dd.name != NULL) { + kfree(handle->dd.name); + handle->dd.name = NULL; + } +#else + if (handle->dd.driver.name != NULL) { + kfree(handle->dd.driver.name); + handle->dd.driver.name = NULL; + } +#endif + return OS_ERROR_OK_S; +} + +/*! + * Remove the driver's registration with the kernel. + * + * Upon return from this call, the driver not receive any more calls at the + * defined entry points (other than ISR and shutdown). + * + * @param handle A handle initialized by #os_driver_init_registration(). + * + * @return An error code. + */ +#define os_driver_remove_registration(handle) \ + os_drv_rmv_reg(&handle) + +/*! + * Register a driver with the Linux Device Model. + * + * @param driver_information The device_driver structure information + * + * @return An error code. + * + * Status: denigrated in favor of #os_driver_complete_registration() + */ +#define os_register_to_driver(driver_information) \ + driver_register(driver_information) + +/*! + * Unregister a driver from the Linux Device Model + * + * this routine unregisters from the Linux Device Model + * + * @param driver_information The device_driver structure information + * + * @return An error code. + * + * Status: Denigrated. See #os_register_to_driver(). + */ +#define os_unregister_from_driver(driver_information) \ + driver_unregister(driver_information) + +/*! + * register a device to a driver + * + * this routine registers a drivers devices to the Linux Device Model + * + * @param device_information The platform_device structure information + * + * @return An error code. + * + * Status: denigrated in favor of #os_driver_complete_registration() + */ +#define os_register_a_device(device_information) \ + platform_device_register(device_information) + +/*! + * unregister a device from a driver + * + * this routine unregisters a drivers devices from the Linux Device Model + * + * @param device_information The platform_device structure information + * + * @return An error code. + * + * Status: Denigrated. See #os_register_a_device(). + */ +#define os_unregister_a_device(device_information) \ + platform_device_unregister(device_information) + +/*! + * Print a message to console / into log file. After the @c msg argument a + * number of printf-style arguments may be added. Types should be limited to + * printf string, char, octal, decimal, and hexadecimal types. (This excludes + * pointers, and floating point). + * + * @param msg The main text of the message to be logged + * @param s The printf-style arguments which go with msg, if any + * + * @return (void) + */ +#define os_printk(...) \ + (void) printk(__VA_ARGS__) + +/*! + * Prepare a task to execute the given function. This should only be done once + * per function,, during the driver's initialization routine. + * + * @param task_fn Name of the OS_DEV_TASK() function to be created. + * + * @return an OS ERROR code. + */ +#define os_create_task(function_name) \ + OS_ERROR_OK_S + +/*! + * Schedule execution of a task. + * + * @param function_name The function associated with the task. + * + * @return (void) + */ +#define os_dev_schedule_task(function_name) \ + tasklet_schedule(&(function_name ## let)) + +/*! + * Make sure that task is no longer running and will no longer run. + * + * This function will not return until both are true. This is useful when + * shutting down a driver. + */ +#define os_dev_stop_task(function_name) \ +do { \ + tasklet_disable(&(function_name ## let)); \ + tasklet_kill(&(function_name ## let)); \ +} while (0) + +/*! + * Allocate some kernel memory + * + * @param amount Number of 8-bit bytes to allocate + * @param flags Some indication of purpose of memory (needs definition) + * + * @return Pointer to allocated memory, or NULL if failed. + */ +#define os_alloc_memory(amount, flags) \ + (void*)kmalloc(amount, flags) + +/*! + * Free some kernel memory + * + * @param location The beginning of the region to be freed. + * + * Do some OSes have separate free() functions which should be + * distinguished by passing in @c flags here, too? Don't some also require the + * size of the buffer being freed? + */ +#define os_free_memory(location) \ + kfree(location) + +/*! + * Allocate cache-coherent memory + * + * @param amount Number of bytes to allocate + * @param[out] dma_addrp Location to store physical address of allocated + * memory. + * @param flags Some indication of purpose of memory (needs + * definition). + * + * @return (virtual space) pointer to allocated memory, or NULL if failed. + * + */ +#define os_alloc_coherent(amount, dma_addrp, flags) \ + (void*)dma_alloc_coherent(NULL, amount, dma_addrp, flags) + +/*! + * Free cache-coherent memory + * + * @param size Number of bytes which were allocated. + * @param virt_addr Virtual(kernel) address of memory.to be freed, as + * returned by #os_alloc_coherent(). + * @param dma_addr Physical address of memory.to be freed, as returned + * by #os_alloc_coherent(). + * + * @return void + * + */ +#define os_free_coherent(size, virt_addr, dma_addr) \ + dma_free_coherent(NULL, size, virt_addr, dma_addr + +/*! + * Map an I/O space into kernel memory space + * + * @param start The starting address of the (physical / io space) region + * @param range_bytes The number of bytes to map + * + * @return A pointer to the mapped area, or NULL on failure + */ +#define os_map_device(start, range_bytes) \ + (void*)ioremap_nocache((start), range_bytes) + +/*! + * Unmap an I/O space from kernel memory space + * + * @param start The starting address of the (virtual) region + * @param range_bytes The number of bytes to unmap + * + * @return None + */ +#define os_unmap_device(start, range_bytes) \ + iounmap((void*)(start)) + +/*! + * Copy data from Kernel space to User space + * + * @param to The target location in user memory + * @param from The source location in kernel memory + * @param size The number of bytes to be copied + * + * @return #os_error_code + */ +#define os_copy_to_user(to, from, size) \ + ((copy_to_user(to, from, size) == 0) ? 0 : OS_ERROR_BAD_ADDRESS_S) + +/*! + * Copy data from User space to Kernel space + * + * @param to The target location in kernel memory + * @param from The source location in user memory + * @param size The number of bytes to be copied + * + * @return #os_error_code + */ +#define os_copy_from_user(to, from, size) \ + ((copy_from_user(to, from, size) == 0) ? 0 : OS_ERROR_BAD_ADDRESS_S) + +/*! + * Read a 8-bit device register + * + * @param register_address The (bus) address of the register to write to + * @return The value in the register + */ +#define os_read8(register_address) \ + __raw_readb(register_address) + +/*! + * Write a 8-bit device register + * + * @param register_address The (bus) address of the register to write to + * @param value The value to write into the register + */ +#define os_write8(register_address, value) \ + __raw_writeb(value, register_address) + +/*! + * Read a 16-bit device register + * + * @param register_address The (bus) address of the register to write to + * @return The value in the register + */ +#define os_read16(register_address) \ + __raw_readw(register_address) + +/*! + * Write a 16-bit device register + * + * @param register_address The (bus) address of the register to write to + * @param value The value to write into the register + */ +#define os_write16(register_address, value) \ + __raw_writew(value, (uint32_t*)(register_address)) + +/*! + * Read a 32-bit device register + * + * @param register_address The (bus) address of the register to write to + * @return The value in the register + */ +#define os_read32(register_address) \ + __raw_readl((uint32_t*)(register_address)) + +/*! + * Write a 32-bit device register + * + * @param register_address The (bus) address of the register to write to + * @param value The value to write into the register + */ +#define os_write32(register_address, value) \ + __raw_writel(value, register_address) + +/*! + * Read a 64-bit device register + * + * @param register_address The (bus) address of the register to write to + * @return The value in the register + */ +#define os_read64(register_address) \ + ERROR_UNIMPLEMENTED + +/*! + * Write a 64-bit device register + * + * @param register_address The (bus) address of the register to write to + * @param value The value to write into the register + */ +#define os_write64(register_address, value) \ + ERROR_UNIMPLEMENTED + +/*! + * Delay some number of microseconds + * + * Note that this is a busy-loop, not a suspension of the task/process. + * + * @param msecs The number of microseconds to delay + * + * @return void + */ +#define os_mdelay mdelay + +/*! + * Calculate virtual address from physical address + * + * @param pa Physical address + * + * @return virtual address + * + * @note this assumes that addresses are 32 bits wide + */ +#define os_va __va + +/*! + * Calculate physical address from virtual address + * + * + * @param va Virtual address + * + * @return physical address + * + * @note this assumes that addresses are 32 bits wide + */ +#define os_pa __pa + +#ifdef CONFIG_PREEMPT_RT +/*! + * Allocate and initialize a lock, returning a lock handle. + * + * The lock state will be initialized to 'unlocked'. + * + * @return A lock handle, or NULL if an error occurred. + */ +inline static os_lock_t os_lock_alloc_init(void) +{ + raw_spinlock_t *lockp; + lockp = (raw_spinlock_t *) kmalloc(sizeof(raw_spinlock_t), 0); + if (lockp) { + _raw_spin_lock_init(lockp); + } else { + printk("OS: lock init failed\n"); + } + + return lockp; +} +#else +/*! + * Allocate and initialize a lock, returning a lock handle. + * + * The lock state will be initialized to 'unlocked'. + * + * @return A lock handle, or NULL if an error occurred. + */ +inline static os_lock_t os_lock_alloc_init(void) +{ + spinlock_t *lockp; + lockp = (spinlock_t *) kmalloc(sizeof(spinlock_t), 0); + if (lockp) { + spin_lock_init(lockp); + } else { + printk("OS: lock init failed\n"); + } + + return lockp; +} +#endif /* CONFIG_PREEMPT_RT */ + +/*! + * Acquire a lock. + * + * This function should only be called from an interrupt service routine. + * + * @param lock_handle A handle to the lock to acquire. + * + * @return void + */ +#define os_lock(lock_handle) \ + spin_lock(lock_handle) + +/*! + * Unlock a lock. Lock must have been acquired by #os_lock(). + * + * @param lock_handle A handle to the lock to unlock. + * + * @return void + */ +#define os_unlock(lock_handle) \ + spin_unlock(lock_handle) + +/*! + * Acquire a lock in non-ISR context + * + * This function will spin until the lock is available. + * + * @param lock_handle A handle of the lock to acquire. + * @param context Place to save the before-lock context + * + * @return void + */ +#define os_lock_save_context(lock_handle, context) \ + spin_lock_irqsave(lock_handle, context) + +/*! + * Release a lock in non-ISR context + * + * @param lock_handle A handle of the lock to release. + * @param context Place where before-lock context was saved. + * + * @return void + */ +#define os_unlock_restore_context(lock_handle, context) \ + spin_unlock_irqrestore(lock_handle, context) + +/*! + * Deallocate a lock handle. + * + * @param lock_handle An #os_lock_t that has been allocated. + * + * @return void + */ +#define os_lock_deallocate(lock_handle) \ + kfree(lock_handle) + +/*! + * Determine process handle + * + * The process handle of the current user is returned. + * + * @return A handle on the current process. + */ +#define os_get_process_handle() \ + current + +/*! + * Send a signal to a process + * + * @param proc A handle to the target process. + * @param sig The POSIX signal to send to that process. + */ +#define os_send_signal(proc, sig) \ + send_sig(sig, proc, 0); + +/*! + * Get some random bytes + * + * @param buf The location to store the random data. + * @param count The number of bytes to store. + * + * @return void + */ +#define os_get_random_bytes(buf, count) \ + get_random_bytes(buf, count) + +/*! + * Go to sleep on an object. + * + * @param object The object on which to sleep + * @param condition An expression to check for sleep completion. Must be + * coded so that it can be referenced more than once inside + * macro, i.e., no ++ or other modifying expressions. + * @param atomic Non-zero if sleep must not return until condition. + * + * @return error code -- OK or sleep interrupted?? + */ +#define os_sleep(object, condition, atomic) \ +({ \ + DEFINE_WAIT(_waitentry_); \ + os_error_code code = OS_ERROR_OK_S; \ + \ + while (!(condition)) { \ + prepare_to_wait(&(object##_qh), &_waitentry_, \ + atomic ? 0 : TASK_INTERRUPTIBLE); \ + if (!(condition)) { \ + schedule(); \ + } \ + \ + finish_wait(&(object##_qh), &_waitentry_); \ + \ + if (!atomic && signal_pending(current)) { \ + code = OS_ERROR_FAIL_S; /* NEED SOMETHING BETTER */ \ + break; \ + } \ + }; \ + \ + code; \ +}) + +/*! + * Wake up whatever is sleeping on sleep object + * + * @param object The object on which things might be sleeping + * + * @return none + */ +#define os_wake_sleepers(object) \ + wake_up_interruptible(&(object##_qh)); + + /*! @} *//* dkops */ + +/****************************************************************************** + * Function signature-generating macros + *****************************************************************************/ + +/*! + * @defgroup drsigs Driver Signatures + * + * These macros will define the entry point signatures for interrupt handlers; + * driver initialization and shutdown; device open/close; etc. + * + * There are two versions of each macro for a given Driver Entry Point. The + * first version is used to define a function and its implementation in the + * driver.c file, e.g. #OS_DEV_INIT(). + * + * The second form is used whenever a forward declaration (prototype) is + * needed. It has the letters @c _DCL appended to the name of the defintion + * function, and takes only the first two arguments (driver_name and + * function_name). These are not otherwise mentioned in this documenation. + * + * There is a third form used when a reference to a function is required, for + * instance when passing the routine as a pointer to a function. It has the + * letters @c _REF appended to it, and takes only the first two arguments + * (driver_name and function_name). These functions are not otherwise + * mentioned in this documentation. + * + * (Note that these two extra forms are required because of the + * possibility/likelihood of having a 'wrapper function' which invokes the + * generic function with expected arguments. An alternative would be to have a + * generic function which isn't able to get at any arguments directly, but + * would be equipped with macros which could get at information passed in. + * + * Example: + * + * (in a header file) + * @code + * OS_DEV_INIT_DCL(widget, widget_init); + * @endcode + * + * (in an implementation file) + * @code + * OS_DEV_INIT(widget, widget_init) + * { + * os_dev_init_return(TRUE); + * } + * @endcode + * + */ + +/*! @addtogroup drsigs */ +/*! @{ */ + +/*! + * Define a function which will handle device initialization + * + * This is tne driver initialization routine. This is normally where the + * part would be initialized; queues, locks, interrupts handlers defined; + * long-term dynamic memory allocated for driver use; etc. + * + * @param function_name The name of the portable initialization function. + * + * @return A call to #os_dev_init_return() + * + */ +#define OS_DEV_INIT(function_name) \ +module_init(function_name); \ +static int __init function_name (void) + +/*! Make declaration for driver init function. + * @param function_name foo + */ +#define OS_DEV_INIT_DCL(function_name) \ +static int __init function_name (void); + +/*! + * Generate a function reference to the driver's init function. + * @param function_name Name of the OS_DEV_INIT() function. + * + * @return A function pointer. + */ +#define OS_DEV_INIT_REF(function_name) \ +function_name + +/*! + * Define a function which will handle device shutdown + * + * This is the inverse of the #OS_DEV_INIT() routine. + * + * @param function_name The name of the portable driver shutdown routine. + * + * @return A call to #os_dev_shutdown_return() + * + */ +#define OS_DEV_SHUTDOWN(function_name) \ +module_exit(function_name); \ +static void function_name(void) + +/*! + * Generate a function reference to the driver's shutdown function. + * @param function_name Name of the OS_DEV_HUSTDOWN() function. + * + * @return A function pointer. + */ +#define OS_DEV_SHUTDOWN_DCL(function_name) \ +static void function_name(void); + +/*! + * Generate a reference to driver's shutdown function + * @param function_name Name of the OS_DEV_HUSTDOWN() function. +*/ + +#define OS_DEV_SHUTDOWN_REF(function_name) \ +function_name + +/*! + * Define a function which will open the device for a user. + * + * @param function_name The name of the driver open() function + * + * @return A call to #os_dev_open_return() + */ +#define OS_DEV_OPEN(function_name) \ +static int function_name(struct inode* inode_p_, struct file* file_p_) + +/*! + * Declare prototype for an open() function. + * + * @param function_name The name of the OS_DEV_OPEN() function. + */ +#define OS_DEV_OPEN_DCL(function_name) \ +OS_DEV_OPEN(function_name); + +/*! + * Generate a function reference to the driver's open() function. + * @param function_name Name of the OS_DEV_OPEN() function. + * + * @return A function pointer. + */ +#define OS_DEV_OPEN_REF(function_name) \ +function_name + +/*! + * Define a function which will handle a user's ioctl() request + * + * @param function_name The name of the driver ioctl() function + * + * @return A call to #os_dev_ioctl_return() + */ +#define OS_DEV_IOCTL(function_name) \ +static int function_name(struct inode* inode_p_, struct file* file_p_, \ + unsigned int cmd_, unsigned long data_) + +/*! Boo. */ +#define OS_DEV_IOCTL_DCL(function_name) \ +OS_DEV_IOCTL(function_name); + +/*! + * Generate a function reference to the driver's ioctl() function. + * @param function_name Name of the OS_DEV_IOCTL() function. + * + * @return A function pointer. + */ +#define OS_DEV_IOCTL_REF(function_name) \ +function_name + +/*! + * Define a function which will handle a user's mmap() request + * + * @param function_name The name of the driver mmap() function + * + * @return A call to #os_dev_ioctl_return() + */ +#define OS_DEV_MMAP(function_name) \ +int function_name(struct file* file_p_, struct vm_area_struct* vma_) + +#define OS_DEV_MMAP_DCL(function_name) \ +OS_DEV_MMAP(function_name); + +#define OS_DEV_MMAP_REF(function_name) \ +function_name + +/* Retrieve the context to the memory structure that is to be MMAPed */ +#define os_mmap_memory_ctx() (vma_) + +/* Determine the size of the requested MMAP region*/ +#define os_mmap_memory_size() (vma_->vm_end - vma_->vm_start) + +/* Determine the base address of the requested MMAP region*/ +#define os_mmap_user_base() (vma_->vm_start) + +/*! + * Declare prototype for an read() function. + * + * @param function_name The name of the driver read function. + */ +#define OS_DEV_READ_DCL(function_name) \ +OS_DEV_READ(function_name); + +/*! + * Generate a function reference to the driver's read() routine + * @param function_name Name of the OS_DEV_READ() function. + * + * @return A function pointer. + */ +#define OS_DEV_READ_REF(function_name) \ +function_name + +/*! + * Define a function which will handle a user's write() request + * + * @param function_name The name of the driver write() function + * + * @return A call to #os_dev_write_return() + */ +#define OS_DEV_WRITE(function_name) \ +static ssize_t function_name(struct file* file_p_, char* user_buffer_, \ + size_t count_bytes_, loff_t* file_position_) + +/*! + * Declare prototype for an write() function. + * + * @param function_name The name of the driver write function. + */ +#define OS_DEV_WRITE_DCL(function_name) \ +OS_DEV_WRITE(function_name); + +/*! + * Generate a function reference to the driver's write() routine + * @param function_name Name of the OS_DEV_WRITE() function. + * + * @return A function pointer. + */ +#define OS_DEV_WRITE_REF(function_name) \ +function_name + +/*! + * Define a function which will close the device - opposite of OS_DEV_OPEN() + * + * @param function_name The name of the driver close() function + * + * @return A call to #os_dev_close_return() + */ +#define OS_DEV_CLOSE(function_name) \ +static int function_name(struct inode* inode_p_, struct file* file_p_) + +/*! + * Declare prototype for an close() function + * + * @param function_name The name of the driver close() function. + */ +#define OS_DEV_CLOSE_DCL(function_name) \ +OS_DEV_CLOSE(function_name); + +/*! + * Generate a function reference to the driver's close function. + * @param function_name Name of the OS_DEV_CLOSE() function. + * + * @return A function pointer. + */ +#define OS_DEV_CLOSE_REF(function_name) \ +function_name + +/*! + * Define a function which will handle an interrupt + * + * No arguments are available to the generic function. It must not invoke any + * OS functions which are illegal in a ISR. It gets no parameters, and must + * have a call to #os_dev_isr_return() instead of any/all return statements. + * + * Example: + * @code + * OS_DEV_ISR(widget) + * { + * os_dev_isr_return(1); + * } + * @endcode + * + * @param function_name The name of the driver ISR function + * + * @return A call to #os_dev_isr_return() + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) +#define OS_DEV_ISR(function_name) \ +static irqreturn_t function_name(int N1_, void* N2_, struct pt_regs* N3_) +#else +#define OS_DEV_ISR(function_name) \ +static irqreturn_t function_name(int N1_, void* N2_) +#endif + +/*! + * Declare prototype for an ISR function. + * + * @param function_name The name of the driver ISR function. + */ +#define OS_DEV_ISR_DCL(function_name) \ +OS_DEV_ISR(function_name); + +/*! + * Generate a function reference to the driver's interrupt service routine + * @param function_name Name of the OS_DEV_ISR() function. + * + * @return A function pointer. + */ +#define OS_DEV_ISR_REF(function_name) \ +function_name + +/*! + * Define a function which will operate as a background task / bottom half. + * + * Tasklet stuff isn't strictly limited to 'Device drivers', but leave it + * this namespace anyway. + * + * @param function_name The name of this background task function + * + * @return A call to #os_dev_task_return() + */ +#define OS_DEV_TASK(function_name) \ +static void function_name(unsigned long data_) + +/*! + * Declare prototype for a background task / bottom half function + * + * @param function_name The name of this background task function + */ +#define OS_DEV_TASK_DCL(function_name) \ +OS_DEV_TASK(function_name); \ +DECLARE_TASKLET(function_name ## let, function_name, 0); + +/*! + * Generate a reference to an #OS_DEV_TASK() function + * + * @param function_name The name of the task being referenced. + */ +#define OS_DEV_TASK_REF(function_name) \ + (function_name ## let) + + /*! @} *//* drsigs */ + +/***************************************************************************** + * Functions/Macros for returning values from Driver Signature routines + *****************************************************************************/ + +/*! + * Return from the #OS_DEV_INIT() function + * + * @param code An error code to report success or failure. + * + */ +#define os_dev_init_return(code) \ + return code + +/*! + * Return from the #OS_DEV_SHUTDOWN() function + * + * @param code An error code to report success or failure. + * + */ +#define os_dev_shutdown_return(code) \ + return + +/*! + * Return from the #OS_DEV_ISR() function + * + * The function should verify that it really was supposed to be called, + * and that its device needed attention, in order to properly set the + * return code. + * + * @param code non-zero if interrupt handled, zero otherwise. + * + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) +#define os_dev_isr_return(code) \ +do { \ + /* Unused warnings */ \ + (void)N1_; \ + (void)N2_; \ + (void)N3_; \ + \ + return IRQ_RETVAL(code); \ +} while (0) +#else +#define os_dev_isr_return(code) \ +do { \ + /* Unused warnings */ \ + (void)N1_; \ + (void)N2_; \ + \ + return IRQ_RETVAL(code); \ +} while (0) +#endif + +/*! + * Return from the #OS_DEV_OPEN() function + * + * @param code An error code to report success or failure. + * + */ +#define os_dev_open_return(code) \ +do { \ + int retcode = code; \ + \ + /* get rid of 'unused parameter' warnings */ \ + (void)inode_p_; \ + (void)file_p_; \ + \ + return retcode; \ +} while (0) + +/*! + * Return from the #OS_DEV_IOCTL() function + * + * @param code An error code to report success or failure. + * + */ +#define os_dev_ioctl_return(code) \ +do { \ + int retcode = code; \ + \ + /* get rid of 'unused parameter' warnings */ \ + (void)inode_p_; \ + (void)file_p_; \ + (void)cmd_; \ + (void)data_; \ + \ + return retcode; \ +} while (0) + +/*! + * Return from the #OS_DEV_READ() function + * + * @param code Number of bytes read, or an error code to report failure. + * + */ +#define os_dev_read_return(code) \ +do { \ + ssize_t retcode = code; \ + \ + /* get rid of 'unused parameter' warnings */ \ + (void)file_p_; \ + (void)user_buffer_; \ + (void)count_bytes_; \ + (void)file_position_; \ + \ + return retcode; \ +} while (0) + +/*! + * Return from the #OS_DEV_WRITE() function + * + * @param code Number of bytes written, or an error code to report failure. + * + */ +#define os_dev_write_return(code) \ +do { \ + ssize_t retcode = code; \ + \ + /* get rid of 'unused parameter' warnings */ \ + (void)file_p_; \ + (void)user_buffer_; \ + (void)count_bytes_; \ + (void)file_position_; \ + \ + return retcode; \ +} while (0) + +/*! + * Return from the #OS_DEV_CLOSE() function + * + * @param code An error code to report success or failure. + * + */ +#define os_dev_close_return(code) \ +do { \ + ssize_t retcode = code; \ + \ + /* get rid of 'unused parameter' warnings */ \ + (void)inode_p_; \ + (void)file_p_; \ + \ + return retcode; \ +} while (0) + +/*! + * Start the #OS_DEV_TASK() function + * + * In some implementations, this could be turned into a label for + * the os_dev_task_return() call. + * + * @return none + */ +#define os_dev_task_begin() + +/*! + * Return from the #OS_DEV_TASK() function + * + * In some implementations, this could be turned into a sleep followed + * by a jump back to the os_dev_task_begin() call. + * + * @param code An error code to report success or failure. + * + */ +#define os_dev_task_return(code) \ +do { \ + /* Unused warnings */ \ + (void)data_; \ + \ + return; \ +} while (0) + +/***************************************************************************** + * Functions/Macros for accessing arguments from Driver Signature routines + *****************************************************************************/ + +/*! @defgroup drsigargs Functions for Getting Arguments in Signature functions + * + */ +/* @addtogroup @drsigargs */ +/*! @{ */ +/*! + * Used in #OS_DEV_OPEN(), #OS_DEV_CLOSE(), #OS_DEV_IOCTL(), #OS_DEV_READ() and + * #OS_DEV_WRITE() routines to check whether user is requesting read + * (permission) + */ +#define os_dev_is_flag_read() \ + (file_p_->f_mode & FMODE_READ) + +/*! + * Used in #OS_DEV_OPEN(), #OS_DEV_CLOSE(), #OS_DEV_IOCTL(), #OS_DEV_READ() and + * #OS_DEV_WRITE() routines to check whether user is requesting write + * (permission) + */ +#define os_dev_is_flag_write() \ + (file_p_->f_mode & FMODE_WRITE) + +/*! + * Used in #OS_DEV_OPEN(), #OS_DEV_CLOSE(), #OS_DEV_IOCTL(), #OS_DEV_READ() and + * #OS_DEV_WRITE() routines to check whether user is requesting non-blocking + * I/O. + */ +#define os_dev_is_flag_nonblock() \ + (file_p_->f_flags & (O_NONBLOCK | O_NDELAY)) + +/*! + * Used in #OS_DEV_OPEN() and #OS_DEV_CLOSE() to determine major device being + * accessed. + */ +#define os_dev_get_major() \ + (imajor(inode_p_)) + +/*! + * Used in #OS_DEV_OPEN() and #OS_DEV_CLOSE() to determine minor device being + * accessed. + */ +#define os_dev_get_minor() \ + (iminor(inode_p_)) + +/*! + * Used in #OS_DEV_IOCTL() to determine which operation the user wants + * performed. + * + * @return Value of the operation. + */ +#define os_dev_get_ioctl_op() \ + (cmd_) + +/*! + * Used in #OS_DEV_IOCTL() to return the associated argument for the desired + * operation. + * + * @return A value which can be cast to a struct pointer or used as + * int/long. + */ +#define os_dev_get_ioctl_arg() \ + (data_) + +/*! + * Used in OS_DEV_READ() and OS_DEV_WRITE() routines to access the requested + * byte count. + * + * @return (unsigned) a count of bytes + */ +#define os_dev_get_count() \ + ((unsigned)count_bytes_) + +/*! + * Used in OS_DEV_READ() and OS_DEV_WRITE() routines to return the pointer + * byte count. + * + * @return char* pointer to user buffer + */ +#define os_dev_get_user_buffer() \ + ((void*)user_buffer_) + +/*! + * Used in OS_DEV_READ(), OS_DEV_WRITE(), and OS_DEV_IOCTL() routines to + * get the POSIX flags field for the associated open file). + * + * @return The flags associated with the file. + */ +#define os_dev_get_file_flags() \ + (file_p_->f_flags) + +/*! + * Set the driver's private structure associated with this file/open. + * + * Generally used during #OS_DEV_OPEN(). See #os_dev_get_user_private(). + * + * @param struct_p The driver data structure to associate with this user. + */ +#define os_dev_set_user_private(struct_p) \ + file_p_->private_data = (void*)(struct_p) + +/*! + * Get the driver's private structure associated with this file. + * + * May be used during #OS_DEV_OPEN(), #OS_DEV_READ(), #OS_DEV_WRITE(), + * #OS_DEV_IOCTL(), and #OS_DEV_CLOSE(). See #os_dev_set_user_private(). + * + * @return The driver data structure to associate with this user. + */ +#define os_dev_get_user_private() \ + ((void*)file_p_->private_data) + +/*! + * Get the IRQ associated with this call to the #OS_DEV_ISR() function. + * + * @return The IRQ (integer) interrupt number. + */ +#define os_dev_get_irq() \ + N1_ + + /*! @} *//* drsigargs */ + +/*! + * @defgroup cacheops Cache Operations + * + * These functions are for synchronizing processor cache with RAM. + */ +/*! @addtogroup cacheops */ +/*! @{ */ + +/*! + * Flush and invalidate all cache lines. + */ +#if 0 +#define os_flush_cache_all() \ + flush_cache_all() +#else +/* Call ARM fn directly, in case L2cache=on3 not set */ +#define os_flush_cache_all() \ + v6_flush_kern_cache_all_L2() + +/*! + * ARM-routine to flush all cache. Defined here, because it exists in no + * easy-access header file. ARM-11 with L210 cache only! + */ +extern void v6_flush_kern_cache_all_L2(void); +#endif + +/* + * These macros are using part of the Linux DMA API. They rely on the + * map function to do nothing more than the equivalent clean/inv/flush + * operation at the time of the mapping, and do nothing at an unmapping + * call, which the Sahara driver code will never invoke. + */ + +/*! + * Clean a range of addresses from the cache. That is, write updates back + * to (RAM, next layer). + * + * @param start Starting virtual address + * @param len Number of bytes to flush + * + * @return void + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) +#define os_cache_clean_range(start,len) \ + dma_map_single(NULL, (void*)start, len, DMA_TO_DEVICE) +#else +#define os_cache_clean_range(start,len) \ +{ \ + void *s = (void*)start; \ + void *e = s + len; \ + dmac_clean_range(s, e); \ + outer_clean_range(__pa(s), __pa(e)); \ +} +#endif + +/*! + * Invalidate a range of addresses in the cache + * + * @param start Starting virtual address + * @param len Number of bytes to flush + * + * @return void + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) +#define os_cache_inv_range(start,len) \ + dma_map_single(NULL, (void*)start, len, DMA_FROM_DEVICE) +#else +#define os_cache_inv_range(start,len) \ +{ \ + void *s = (void*)start; \ + void *e = s + len; \ + dmac_inv_range(s, e); \ + outer_inv_range(__pa(s), __pa(e)); \ +} +#endif + +/*! + * Flush a range of addresses from the cache. That is, perform clean + * and invalidate + * + * @param start Starting virtual address + * @param len Number of bytes to flush + * + * @return void + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) +#define os_cache_flush_range(start,len) \ + dma_map_single(NULL, (void*)start, len, DMA_BIDIRECTIONAL) +#else +#define os_cache_flush_range(start,len) \ +{ \ + void *s = (void*)start; \ + void *e = s + len; \ + dmac_flush_range(s, e); \ + outer_flush_range(__pa(s), __pa(e)); \ +} +#endif + + /*! @} *//* cacheops */ + +#endif /* LINUX_PORT_H */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/include/platform_abstractions.h linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/platform_abstractions.h --- linux-2.6.26/drivers/mxc/security/sahara2/include/platform_abstractions.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/platform_abstractions.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,15 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @file platform_abstractions.h + */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/include/portable_os.h linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/portable_os.h --- linux-2.6.26/drivers/mxc/security/sahara2/include/portable_os.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/portable_os.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,1453 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef PORTABLE_OS_H +#define PORTABLE_OS_H + +/***************************************************************************/ + +/* + * Add support for your target OS by checking appropriate flags and then + * including the appropriate file. Don't forget to document the conditions + * in the later documentation section at the beginning of the + * DOXYGEN_PORTABLE_OS_DOC. + */ + +#if defined(LINUX_KERNEL) + +#include "linux_port.h" + +#elif defined(PORTABLE_OS) + +#include "check_portability.h" + +#else + +#error Target OS unsupported or unspecified + +#endif + + +/***************************************************************************/ + +/*! + * @file portable_os.h + * + * This file should be included by portable driver code in order to gain access + * to the OS-specific header files. It is the only OS-related header file that + * the writer of a portable driver should need. + * + * This file also contains the documentation for the common API. + * + * Begin reading the documentation for this file at the @ref index "main page". + * + */ + +/*! + * @if USE_MAINPAGE + * @mainpage Generic OS API for STC Drivers + * @endif + * + * @section intro_sec Introduction + * + * This defines the API / kernel programming environment for portable drivers. + * + * This API is broken up into several functional areas. It greatly limits the + * choices of a device-driver author, but at the same time should allow for + * greater portability of the resulting code. + * + * Each kernel-to-driver function (initialization function, interrupt service + * routine, etc.) has a 'portable signature' which must be used, and a specific + * function which must be called to generate the return statement. There is + * one exception, a background task or "bottom half" routine, which instead has + * a specific structure which must be followed. These signatures and function + * definitions are found in @ref drsigs. + * + * None of these kernel-to-driver functions seem to get any arguments passed to + * them. Instead, there are @ref drsigargs which allow one of these functions + * to get at fairly generic parts of its calling arguments, if there are any. + * + * Almost every driver will have some need to call the operating system + * @ref dkops is the list of services which are available to the driver. + * + * + * @subsection warn_sec Warning + * + * The specifics of the types, values of the various enumerations + * (unless specifically stated, like = 0), etc., are only here for illustrative + * purposes. No attempts should be made to make use of any specific knowledge + * gleaned from this documentation. These types are only meant to be passed in + * and out of the API, and their contents are to be handled only by the + * provided OS-specific functions. + * + * Also, note that the function may be provided as macros in some + * implementations, or vice versa. + * + * + * @section dev_sec Writing a Portable Driver + * + * First off, writing a portable driver means calling no function in an OS + * except what is available through this header file. + * + * Secondly, all OS-called functions in your driver must be invoked and + * referenced through the signature routines. + * + * Thirdly, there might be some rules which you can get away with ignoring or + * violating on one OS, yet will cause your code not to be portable to a + * different OS. + * + * + * @section limit_sec Limitations + * + * This API is not expected to handle every type of driver which may be found + * in an operating system. For example, it will not be able to handle the + * usual design for something like a UART driver, where there are multiple + * logical devices to access, because the design usually calls for some sort of + * indication to the #OS_DEV_TASK() function or OS_DEV_ISR() to indicate which + * channel is to be serviced by that instance of the task/function. This sort + * of argument is missing in this API for functions like os_dev_schedule_task() and + * os_register_interrupt(). + * + * + * @section port_guide Porting Guidelines + * + * This section is intended for a developer who needs to port the header file + * to an operating system which is not yet supported. + * + * This interface allows for a lot of flexibility when it comes to porting to + * an operating systems device driver interface. There are three main areas to + * examine: The use of Driver Routine Signatures, the use of Driver Argument + * Access functions, the Calls to Kernel Functions, and Data Types. + * + * + * @subsection port_sig Porting Driver Routine Signatures + * + * The three macros for each function (e.g. #OS_DEV_INIT(), #OS_DEV_INIT_DCL(), + * and #OS_DEV_INIT_REF()) allow the flexibility of having a 'wrapper' function + * with the OS-required signature, which would then call the user's function + * with some different signature. + * + * The first form would lay down the wrapper function, followed by the + * signature for the user function. The second form would lay down just the + * signatures for both functions, and the last function would reference the + * wrapper function, since that is the interface function called by the OS. + * + * Note that the driver author has no visibility at all to the signature of the + * routines. The author can access arguments only through a limited set of + * functions, and must return via another function. + * + * The Return Functions allow a lot of flexibility in converting the return + * value, or not returning a value at all. These will likely be implemented as + * macros. + * + * + * @subsection port_arg Porting Driver Argument Access Functions + * + * The signatures defined by the guide will usually be replaced with macro + * definitions. + * + * + * @subsection port_dki Porting Calls to Kernel Functions + * + * The signatures defined by the guide may be replaced with macro definitions, + * if that makes more sense. + * + * Implementors are free to ignore arguments which are not applicable to their + * OS. + * + * @subsection port_datatypes Porting Data Types + * + * + */ + +/*************************************************************************** + * Compile flags + **************************************************************************/ + +/* + * This compile flag should only be turned on when running doxygen to generate + * the API documentation. + */ +#ifdef DOXYGEN_PORTABLE_OS_DOC + +/*! + * @todo module_init()/module_cleanup() for Linux need to be added to OS + * abstractions. Also need EXPORT_SYMBOL() equivalent?? + * + */ + +/* Drop OS differentation documentation here */ + +/*! + * \#define this flag to build your driver as a Linux driver + */ +#define LINUX + +/* end OS differentation documentation */ + +/*! + * Symbol to give version number of the implementation file. Earliest + * definition is in version 1.1, with value 101 (to mean version 1.1) + */ +#define PORTABLE_OS_VERSION 101 + +/* + * NOTICE: The following definitions (the rest of the file) are not meant ever + * to be compiled. Instead, they are the documentation for the portable OS + * API, to be used by driver writers. + * + * Each individual OS port will define each of these types, functions, or + * macros as appropriate to the target OS. This is why they are under the + * DOXYGEN_PORTABLE_OS_DOC flag. + */ + +/*************************************************************************** + * Type definitions + **************************************************************************/ + +/*! + * Type used for registering and deregistering interrupts. + * + * This is typically an interrupt channel number. + */ +typedef int os_interrupt_id_t; + +/*! + * Type used as handle for a process + * + * See #os_get_process_handle() and #os_send_signal(). + */ +typedef int os_process_handle_t; + +/*! + * Generic return code for functions which need such a thing. + * + * No knowledge should be assumed of the value of any of these symbols except + * that @c OS_ERROR_OK_S is guaranteed to be zero. + * + * @todo Any other named values? What about (-EAGAIN? -ERESTARTSYS? Are they + * too Linux/Unix-specific read()/write() return values) ? + */ +typedef enum { + OS_ERROR_OK_S = 0, /*!< Success */ + OS_ERROR_FAIL_S, /*!< Generic driver failure */ + OS_ERROR_NO_MEMORY_S, /*!< Failure to acquire/use memory */ + OS_ERROR_BAD_ADDRESS_S, /*!< Bad address */ + OS_ERROR_BAD_ARG_S /*!< Bad input argument */ +} os_error_code; + +/*! + * Handle to a lock. + */ +typedef int *os_lock_t; + +/*! + * Context while locking. + */ +typedef int os_lock_context_t; + +/*! + * An object which can be slept on and later used to wake any/all sleepers. + */ +typedef int os_sleep_object_t; + +/*! + * Driver registration handle + */ +typedef void *os_driver_reg_t; + +/*! + * Function signature for an #OS_DEV_INIT() function. + * + * @return A call to os_dev_init_return() function. + */ +typedef void (*os_init_function_t) (void); + +/*! + * Function signature for an #OS_DEV_SHUTDOWN() function. + * + * @return A call to os_dev_shutdown_return() function. + */ +typedef void (*os_shutdown_function_t) (void); + +/*! + * Function signature for a user-driver function. + * + * @return A call to the appropriate os_dev_xxx_return() function. + */ +typedef void (*os_user_function_t) (void); + +/*! + * Function signature for the portable interrupt handler + * + * While it would be nice to know which interrupt is being serviced, the + * Least Common Denominator rule says that no arguments get passed in. + * + * @return A call to #os_dev_isr_return() + */ +typedef void (*os_interrupt_handler_t) (void); + +/*! + * Function signature for a task function + * + * Many task function definitions get some sort of generic argument so that the + * same function can run across many (queues, channels, ...) as separate task + * instances. This has been left out of this API. + * + * This function must be structured as documented by #OS_DEV_TASK(). + * + */ +typedef void (*os_task_fn_t) (void); + +/*! + * Function types which can be associated with driver entry points. These are + * used in os_driver_add_registration(). + * + * Note that init and shutdown are absent. + */ +typedef enum { + OS_FN_OPEN, /*!< open() operation handler. */ + OS_FN_CLOSE, /*!< close() operation handler. */ + OS_FN_READ, /*!< read() operation handler. */ + OS_FN_WRITE, /*!< write() operation handler. */ + OS_FN_IOCTL, /*!< ioctl() operation handler. */ + OS_FN_MMAP /*!< mmap() operation handler. */ +} os_driver_fn_t; + +/*************************************************************************** + * Driver-to-Kernel Operations + **************************************************************************/ + +/*! + * @defgroup dkops Driver-to-Kernel Operations + * + * These are the operations which drivers should call to get the OS to perform + * services. + */ + +/*! @addtogroup dkops */ +/*! @{ */ + +/*! + * Register an interrupt handler. + * + * @param driver_name The name of the driver + * @param interrupt_id The interrupt line to monitor (type + * #os_interrupt_id_t) + * @param function The function to be called to handle an interrupt + * + * @return #os_error_code + */ +os_error_code os_register_interrupt(char *driver_name, + os_interrupt_id_t interrupt_id, + os_interrupt_handler_t function); + +/*! + * Deregister an interrupt handler. + * + * @param interrupt_id The interrupt line to stop monitoring + * + * @return #os_error_code + */ +os_error_code os_deregister_interrupt(os_interrupt_id_t interrupt_id); + +/*! + * Initialize driver registration. + * + * If the driver handles open(), close(), ioctl(), read(), write(), or mmap() + * calls, then it needs to register their location with the kernel so that they + * get associated with the device. + * + * @param handle The handle object to be used with this registration. The + * object must live (be in memory somewhere) at least until + * os_driver_remove_registration() is called. + * + * @return An os error code. + */ +os_error_code os_driver_init_registration(os_driver_reg_t handle); + +/*! + * Add a function registration to driver registration. + * + * @param handle The handle used with #os_driver_init_registration(). + * @param name Which function is being supported. + * @param function The result of a call to a @c _REF version of one of the + * driver function signature macros + * driver function signature macros + * @return void + */ +void os_driver_add_registration(os_driver_reg_t handle, os_driver_fn_t name, + void *function); + +/*! + * Finalize the driver registration with the kernel. + * + * Upon return from this call, the driver may begin receiving calls at the + * defined entry points. + * + * @param handle The handle used with #os_driver_init_registration(). + * @param major The major device number to be associated with the driver. + * If this value is zero, a major number may be assigned. + * See #os_driver_get_major() to determine final value. + * #os_driver_remove_registration(). + * @param driver_name The driver name. Can be used as part of 'device node' + * name on platforms which support such a feature. + * + * @return An error code + */ +os_error_code os_driver_complete_registration(os_driver_reg_t handle, + int major, char *driver_name); + +/*! + * Get driver Major Number from handle after a successful registration. + * + * @param handle A handle which has completed registration. + * + * @return The major number (if any) associated with the handle. + */ +uint32_t os_driver_get_major(os_driver_reg_t handle); + +/*! + * Remove the driver's registration with the kernel. + * + * Upon return from this call, the driver not receive any more calls at the + * defined entry points (other than ISR and shutdown). + * + * @param major The major device number to be associated with the driver. + * @param driver_name The driver name + * + * @return An error code. + */ +os_error_code os_driver_remove_registration(int major, char *driver_name); + +/*! + * Print a message to console / into log file. After the @c msg argument a + * number of printf-style arguments may be added. Types should be limited to + * printf string, char, octal, decimal, and hexadecimal types. (This excludes + * pointers, and floating point). + * + * @param msg The message to print to console / system log + * + * @return (void) + */ +void os_printk(char *msg, ...); + +/*! + * Allocate some kernel memory + * + * @param amount Number of 8-bit bytes to allocate + * @param flags Some indication of purpose of memory (needs definition) + * + * @return Pointer to allocated memory, or NULL if failed. + */ +void *os_alloc_memory(unsigned amount, int flags); + +/*! + * Free some kernel memory + * + * @param location The beginning of the region to be freed. + * + * Do some OSes have separate free() functions which should be + * distinguished by passing in @c flags here, too? Don't some also require the + * size of the buffer being freed? Perhaps separate routines for each + * alloc/free pair (DMAable, etc.)? + */ +void os_free_memory(void *location); + +/*! + * Allocate cache-coherent memory + * + * @param amount Number of bytes to allocate + * @param[out] dma_addrp Location to store physical address of allocated + * memory. + * @param flags Some indication of purpose of memory (needs + * definition). + * + * @return (virtual space) pointer to allocated memory, or NULL if failed. + * + */ +void *os_alloc_coherent(unsigned amount, uint32_t * dma_addrp, int flags); + +/*! + * Free cache-coherent memory + * + * @param size Number of bytes which were allocated. + * @param[out] virt_addr Virtual(kernel) address of memory.to be freed, as + * returned by #os_alloc_coherent(). + * @param[out] dma_addr Physical address of memory.to be freed, as returned + * by #os_alloc_coherent(). + * + * @return void + * + */ +void os_free_coherent(unsigned size, void *virt_addr, uint32_t dma_addr); + +/*! + * Map an I/O space into kernel memory space + * + * @param start The starting address of the (physical / io space) region + * @param range_bytes The number of bytes to map + * + * @return A pointer to the mapped area, or NULL on failure + */ +void *os_map_device(uint32_t start, unsigned range_bytes); + +/*! + * Unmap an I/O space from kernel memory space + * + * @param start The starting address of the (virtual) region + * @param range_bytes The number of bytes to unmap + * + * @return None + */ +void os_unmap_device(void *start, unsigned range_bytes); + +/*! + * Copy data from Kernel space to User space + * + * @param to The target location in user memory + * @param from The source location in kernel memory + * @param size The number of bytes to be copied + * + * @return #os_error_code + */ +os_error_code os_copy_to_user(void *to, void *from, unsigned size); + +/*! + * Copy data from User space to Kernel space + * + * @param to The target location in kernel memory + * @param from The source location in user memory + * @param size The number of bytes to be copied + * + * @return #os_error_code + */ +os_error_code os_copy_from_user(void *to, void *from, unsigned size); + +/*! + * Read an 8-bit device register + * + * @param register_address The (bus) address of the register to write to + * @return The value in the register + */ +uint8_t os_read8(uint8_t * register_address); + +/*! + * Write an 8-bit device register + * + * @param register_address The (bus) address of the register to write to + * @param value The value to write into the register + */ +void os_write8(uint8_t * register_address, uint8_t value); + +/*! + * Read a 16-bit device register + * + * @param register_address The (bus) address of the register to write to + * @return The value in the register + */ +uint16_t os_read16(uint16_t * register_address); + +/*! + * Write a 16-bit device register + * + * @param register_address The (bus) address of the register to write to + * @param value The value to write into the register + */ +void os_write16(uint16_t * register_address, uint16_t value); + +/*! + * Read a 32-bit device register + * + * @param register_address The (bus) address of the register to write to + * @return The value in the register + */ +uint32_t os_read32(uint32_t * register_address); + +/*! + * Write a 32-bit device register + * + * @param register_address The (bus) address of the register to write to + * @param value The value to write into the register + */ +void os_write32(uint32_t * register_address, uint32_t value); + +/*! + * Read a 64-bit device register + * + * @param register_address The (bus) address of the register to write to + * @return The value in the register + */ +uint64_t os_read64(uint64_t * register_address); + +/*! + * Write a 64-bit device register + * + * @param register_address The (bus) address of the register to write to + * @param value The value to write into the register + */ +void os_write64(uint64_t * register_address, uint64_t value); + +/*! + * Prepare a task to execute the given function. This should only be done once + * per task, during the driver's initialization routine. + * + * @param task_fn Name of the OS_DEV_TASK() function to be created. + * + * @return an OS ERROR code. + */ +os_error os_create_task(os_task_fn_t * task_fn); + +/*! + * Run the task associated with an #OS_DEV_TASK() function + * + * The task will begin execution sometime after or during this call. + * + * @param task_fn Name of the OS_DEV_TASK() function to be scheduled. + * + * @return void + */ +void os_dev_schedule_task(os_task_fn_t * task_fn); + +/*! + * Make sure that task is no longer running and will no longer run. + * + * This function will not return until both are true. This is useful when + * shutting down a driver. + * + * @param task_fn Name of the OS_DEV_TASK() funciton to be stopped. + * + */ +void os_stop_task(os_task_fn_t * task_fn); + +/*! + * Delay some number of microseconds + * + * Note that this is a busy-loop, not a suspension of the task/process. + * + * @param msecs The number of microseconds to delay + * + * @return void + */ +void os_mdelay(unsigned long msecs); + +/*! + * Calculate virtual address from physical address + * + * @param pa Physical address + * + * @return virtual address + * + * @note this assumes that addresses are 32 bits wide + */ +void *os_va(uint32_t pa); + +/*! + * Calculate physical address from virtual address + * + * + * @param va Virtual address + * + * @return physical address + * + * @note this assumes that addresses are 32 bits wide + */ +uint32_t os_pa(void *va); + +/*! + * Allocate and initialize a lock, returning a lock handle. + * + * The lock state will be initialized to 'unlocked'. + * + * @return A lock handle, or NULL if an error occurred. + */ +os_lock_t os_lock_alloc_init(void); + +/*! + * Acquire a lock. + * + * This function should only be called from an interrupt service routine. + * + * @param lock_handle A handle to the lock to acquire. + * + * @return void + */ +void os_lock(os_lock_t lock_handle); + +/*! + * Unlock a lock. Lock must have been acquired by #os_lock(). + * + * @param lock_handle A handle to the lock to unlock. + * + * @return void + */ +void os_unlock(os_lock_t lock_handle); + +/*! + * Acquire a lock in non-ISR context + * + * This function will spin until the lock is available. + * + * @param lock_handle A handle of the lock to acquire. + * @param context Place to save the before-lock context + * + * @return void + */ +void os_lock_save_context(os_lock_t lock_handle, os_lock_context_t context); + +/*! + * Release a lock in non-ISR context + * + * @param lock_handle A handle of the lock to release. + * @param context Place where before-lock context was saved. + * + * @return void + */ +void os_unlock_restore_context(os_lock_t lock_handle, + os_lock_context_t context); + +/*! + * Deallocate a lock handle. + * + * @param lock_handle An #os_lock_t that has been allocated. + * + * @return void + */ +void os_lock_deallocate(os_lock_t lock_handle); + +/*! + * Determine process handle + * + * The process handle of the current user is returned. + * + * @return A handle on the current process. + */ +os_process_handle_t os_get_process_handle(); + +/*! + * Send a signal to a process + * + * @param proc A handle to the target process. + * @param sig The POSIX signal to send to that process. + */ +void os_send_signal(os_process_handle_t proc, int sig); + +/*! + * Get some random bytes + * + * @param buf The location to store the random data. + * @param count The number of bytes to store. + * + * @return void + */ +void os_get_random_bytes(void *buf, unsigned count); + +/*! + * Go to sleep on an object. + * + * Example: code = os_sleep(my_queue, available_count == 0, 0); + * + * @param object The object on which to sleep + * @param condition An expression to check for sleep completion. Must be + * coded so that it can be referenced more than once inside + * macro, i.e., no ++ or other modifying expressions. + * @param atomic Non-zero if sleep must not return until condition. + * + * @return error code -- OK or sleep interrupted?? + */ +os_error_code os_sleep(os_sleep_object_t object, unsigned condition, + unsigned atomic); + +/*! + * Wake up whatever is sleeping on sleep object + * + * @param object The object on which things might be sleeping + * + * @return none + */ +void os_wake_sleepers(os_sleep_object_t object); + + /*! @} *//* dkops */ + +/***************************************************************************** + * Function-signature-generating macros + *****************************************************************************/ + +/*! + * @defgroup drsigs Driver Function Signatures + * + * These macros will define the entry point signatures for interrupt handlers; + * driver initialization and shutdown; device open/close; etc. They are to be + * used whenever the Kernel will call into the Driver. They are not + * appropriate for driver calls to other routines in the driver. + * + * There are three versions of each macro for a given Driver Entry Point. The + * first version is used to define a function and its implementation in the + * driver.c file, e.g. #OS_DEV_INIT(). + * + * The second form is used whenever a forward declaration (prototype) is + * needed. It has the letters @c _DCL appended to the name of the definition + * function. These are not otherwise mentioned in this documenation. + * + * There is a third form used when a reference to a function is required, for + * instance when passing the routine as a pointer to a function. It has the + * letters @c _REF appended to the name of the definition function + * (e.g. DEV_IOCTL_REF). + * + * Note that these two extra forms are required because of the possibility of + * having an invisible 'wrapper function' created by the os-specific header + * file which would need to be invoked by the operating system, and which in + * turn would invoke the generic function. + * + * Example: + * + * (in a header file) + * @code + * OS_DEV_INIT_DCL(widget_init); + * OS_DEV_ISR_DCL(widget_isr); + * @endcode + * + * (in an implementation file) + * @code + * OS_DEV_INIT(widget, widget_init) + * { + * + * os_register_interrupt("widget", WIDGET_IRQ, OS_DEV_ISR_REF(widget_isr)); + * + * os_dev_init_return(OS_RETURN_NO_ERROR_S); + * } + * + * OS_DEV_ISR(widget_isr) + * { + * os_dev_isr_return(TRUE); + * } + * @endcode + */ + +/*! @addtogroup drsigs */ +/*! @{ */ + +/*! + * Define a function which will handle device initialization + * + * This is tne driver initialization routine. This is normally where the + * part would be initialized; queues, locks, interrupts handlers defined; + * long-term dynamic memory allocated for driver use; etc. + * + * @param function_name The name of the portable initialization function. + * + * @return A call to #os_dev_init_return() + * + */ +#define OS_DEV_INIT(function_name) + +/*! + * Define a function which will handle device shutdown + * + * This is the reverse of the #OS_DEV_INIT() routine. + * + * @param function_name The name of the portable driver shutdown routine. + * + * @return A call to #os_dev_shutdown_return() + */ +#define OS_DEV_SHUTDOWN(function_name) + +/*! + * Define a function which will open the device for a user. + * + * @param function_name The name of the driver open() function + * + * @return A call to #os_dev_open_return() + */ +#define OS_DEV_OPEN(function_name) + +/*! + * Define a function which will handle a user's ioctl() request + * + * @param function_name The name of the driver ioctl() function + * + * @return A call to #os_dev_ioctl_return() + */ +#define OS_DEV_IOCTL(function_name) + +/*! + * Define a function which will handle a user's read() request + * + * @param function_name The name of the driver read() function + * + * @return A call to #os_dev_read_return() + */ +#define OS_DEV_READ(function_name) + +/*! + * Define a function which will handle a user's write() request + * + * @param function_name The name of the driver write() function + * + * @return A call to #os_dev_write_return() + */ +#define OS_DEV_WRITE(function_name) + +/*! + * Define a function which will handle a user's mmap() request + * + * The mmap() function requests the driver to map some memory into user space. + * + * @todo Determine what support functions are needed for mmap() handling. + * + * @param function_name The name of the driver mmap() function + * + * @return A call to #os_dev_mmap_return() + */ +#define OS_DEV_MMAP(function_name) + +/*! + * Define a function which will close the device - opposite of OS_DEV_OPEN() + * + * @param function_name The name of the driver close() function + * + * @return A call to #os_dev_close_return() + */ +#define OS_DEV_CLOSE(function_name) + +/*! + * Define a function which will handle an interrupt + * + * No arguments are available to the generic function. It must not invoke any + * OS functions which are illegal in a ISR. It gets no parameters, and must + * have a call to #os_dev_isr_return() instead of any/all return statements. + * + * Example: + * @code + * OS_DEV_ISR(widget, widget_isr, WIDGET_IRQ_NUMBER) + * { + * os_dev_isr_return(1); + * } + * @endcode + * + * @param function_name The name of the driver ISR function + * + * @return A call to #os_dev_isr_return() + */ +#define OS_DEV_ISR(function_name) + +/*! + * Define a function which will operate as a background task / bottom half. + * + * The function implementation must be structured in the following manner: + * @code + * OS_DEV_TASK(widget_task) + * { + * OS_DEV_TASK_SETUP(widget_task); + * + * while OS_DEV_TASK_CONDITION(widget_task) } + * + * }; + * } + * @endcode + * + * @todo In some systems the OS_DEV_TASK_CONDITION() will be an action which + * will cause the task to sleep on some event triggered by os_run_task(). In + * others, the macro will reference a variable laid down by + * OS_DEV_TASK_SETUP() to make sure that the loop is only performed once. + * + * @param function_name The name of this background task function + */ +#define OS_DEV_TASK(function_name) + + /*! @} *//* drsigs */ + +/*! @defgroup dclsigs Routines to declare Driver Signature routines + * + * These macros drop prototypes suitable for forward-declaration of + * @ref drsigs "function signatures". + */ + +/*! @addtogroup dclsigs */ +/*! @{ */ + +/*! + * Declare prototype for the device initialization function + * + * @param function_name The name of the portable initialization function. + */ +#define OS_DEV_INIT_DCL(function_name) + +/*! + * Declare prototype for the device shutdown function + * + * @param function_name The name of the portable driver shutdown routine. + * + * @return A call to #os_dev_shutdown_return() + */ +#define OS_DEV_SHUTDOWN_DCL(function_name) + +/*! + * Declare prototype for the open() function. + * + * @param function_name The name of the driver open() function + * + * @return A call to #os_dev_open_return() + */ +#define OS_DEV_OPEN_DCL(function_name) + +/*! + * Declare prototype for the user's ioctl() request function + * + * @param function_name The name of the driver ioctl() function + * + * @return A call to #os_dev_ioctl_return() + */ +#define OS_DEV_IOCTL_DCL(function_name) + +/*! + * Declare prototype for the function a user's read() request + * + * @param function_name The name of the driver read() function + */ +#define OS_DEV_READ_DCL(function_name) + +/*! + * Declare prototype for the user's write() request function + * + * @param function_name The name of the driver write() function + */ +#define OS_DEV_WRITE_DCL(function_name) + +/*! + * Declare prototype for the user's mmap() request function + * + * @param function_name The name of the driver mmap() function + */ +#define OS_DEV_MMAP_DCL(function_name) + +/*! + * Declare prototype for the close function + * + * @param function_name The name of the driver close() function + * + * @return A call to #os_dev_close_return() + */ +#define OS_DEV_CLOSE_DCL(function_name) + +/*! + * Declare prototype for the interrupt handling function + * + * @param function_name The name of the driver ISR function + */ +#define OS_DEV_ISR_DCL(function_name) + +/*! + * Declare prototype for a background task / bottom half function + * + * @param function_name The name of this background task function + */ +#define OS_DEV_TASK_DCL(function_name) + + /*! @} *//* dclsigs */ + +/***************************************************************************** + * Functions for Returning Values from Driver Signature routines + *****************************************************************************/ + +/*! + * @defgroup retfns Functions to Return Values from Driver Signature routines + */ + +/*! @addtogroup retfns */ +/*! @{ */ + +/*! + * Return from the #OS_DEV_INIT() function + * + * @param code An error code to report success or failure. + * + */ +void os_dev_init_return(os_error_code code); + +/*! + * Return from the #OS_DEV_SHUTDOWN() function + * + * @param code An error code to report success or failure. + * + */ +void os_dev_shutdown_return(os_error_code code); + +/*! + * Return from the #OS_DEV_ISR() function + * + * The function should verify that it really was supposed to be called, + * and that its device needed attention, in order to properly set the + * return code. + * + * @param code non-zero if interrupt handled, zero otherwise. + * + */ +void os_dev_isr_return(int code); + +/*! + * Return from the #OS_DEV_OPEN() function + * + * @param code An error code to report success or failure. + * + */ +void os_dev_open_return(os_error_code code); + +/*! + * Return from the #OS_DEV_IOCTL() function + * + * @param code An error code to report success or failure. + * + */ +void os_dev_ioctl_return(os_error_code code); + +/*! + * Return from the #OS_DEV_READ() function + * + * @param code Number of bytes read, or an error code to report failure. + * + */ +void os_dev_read_return(os_error_code code); + +/*! + * Return from the #OS_DEV_WRITE() function + * + * @param code Number of bytes written, or an error code to report failure. + * + */ +void os_dev_write_return(os_error_code code); + +/*! + * Return from the #OS_DEV_MMAP() function + * + * @param code Number of bytes written, or an error code to report failure. + * + */ +void os_dev_mmap_return(os_error_code code); + +/*! + * Return from the #OS_DEV_CLOSE() function + * + * @param code An error code to report success or failure. + * + */ +void os_dev_close_return(os_error_code code); + +/*! + * Start the #OS_DEV_TASK() function + * + * In some implementations, this could be turned into a label for + * the os_dev_task_return() call. + * + * For a more portable interface, should this take the sleep object as an + * argument??? + * + * @return none + */ +void os_dev_task_begin(void); + +/*! + * Return from the #OS_DEV_TASK() function + * + * In some implementations, this could be turned into a sleep followed + * by a jump back to the os_dev_task_begin() call. + * + * @param code An error code to report success or failure. + * + */ +void os_dev_task_return(os_error_code code); + + /*! @} *//* retfns */ + +/***************************************************************************** + * Functions/Macros for accessing arguments from Driver Signature routines + *****************************************************************************/ + +/*! @defgroup drsigargs Functions for Getting Arguments in Signature functions + * + */ +/* @addtogroup @drsigargs */ +/*! @{ */ + +/*! + * Check whether user is requesting read (permission) on the file/device. + * Usable in #OS_DEV_OPEN(), #OS_DEV_CLOSE(), #OS_DEV_IOCTL(), #OS_DEV_READ() + * and #OS_DEV_WRITE() routines. + */ +int os_dev_is_flag_read(void); + +/*! + * Check whether user is requesting write (permission) on the file/device. + * Usable in #OS_DEV_OPEN(), #OS_DEV_CLOSE(), #OS_DEV_IOCTL(), #OS_DEV_READ() + * and #OS_DEV_WRITE() routines. + */ +int os_dev_is_flag_write(void); + +/*! + * Check whether user is requesting non-blocking I/O. Usable in + * #OS_DEV_OPEN(), #OS_DEV_CLOSE(), #OS_DEV_IOCTL(), #OS_DEV_READ() and + * #OS_DEV_WRITE() routines. + * + * @todo Specify required behavior when nonblock is requested and (sufficient?) + * data are not available to fulfill the request. + * + */ +int os_dev_is_flag_nonblock(void); + +/*! + * Determine which major device is being accessed. Usable in #OS_DEV_OPEN() + * and #OS_DEV_CLOSE(). + */ +int os_dev_get_major(void); + +/*! + * Determine which minor device is being accessed. Usable in #OS_DEV_OPEN() + * and #OS_DEV_CLOSE(). + */ +int os_dev_get_minor(void); + +/*! + * Determine which operation the user wants performed. Usable in + * #OS_DEV_IOCTL(). + * + * @return Value of the operation. + * + * @todo Define some generic way to define the individual operations. + */ +unsigned os_dev_get_ioctl_op(void); + +/*! + * Retrieve the associated argument for the desired operation. Usable in + * #OS_DEV_IOCTL(). + * + * @return A value which can be cast to a struct pointer or used as + * int/long. + */ +os_dev_ioctl_arg_t os_dev_get_ioctl_arg(void); + +/*! + * Determine the requested byte count. This should be the size of buffer at + * #os_dev_get_user_buffer(). Usable in OS_DEV_READ() and OS_DEV_WRITE() + * routines. + * + * @return A count of bytes + */ +unsigned os_dev_get_count(void); + +/*! + * Get the pointer to the user's data buffer. Usable in OS_DEV_READ(), + * OS_DEV_WRITE(), and OS_DEV_MMAP() routines. + * + * @return Pointer to user buffer (in user space). See #os_copy_to_user() + * and #os_copy_from_user(). + */ +void *os_dev_get_user_buffer(void); + +/*! + * Get the POSIX flags field for the associated open file. Usable in + * OS_DEV_READ(), OS_DEV_WRITE(), and OS_DEV_IOCTL() routines. + * + * @return The flags associated with the file. + */ +unsigned os_dev_get_file_flags(void); + +/*! + * Set the driver's private structure associated with this file/open. + * + * Generally used during #OS_DEV_OPEN(). May also be used during + * #OS_DEV_READ(), #OS_DEV_WRITE(), #OS_DEV_IOCTL(), #OS_DEV_MMAP(), and + * #OS_DEV_CLOSE(). See also #os_dev_get_user_private(). + * + * @param struct_p The driver data structure to associate with this user. + */ +void os_dev_set_user_private(void *struct_p); + +/*! + * Get the driver's private structure associated with this file. + * + * May be used during #OS_DEV_OPEN(), #OS_DEV_READ(), #OS_DEV_WRITE(), + * #OS_DEV_IOCTL(), #OS_DEV_MMAP(), and #OS_DEV_CLOSE(). See + * also #os_dev_set_user_private(). + * + * @return The driver data structure to associate with this user. + */ +void *os_dev_get_user_private(void); + +/*! + * Get the IRQ associated with this call to the #OS_DEV_ISR() function. + * + * @return The IRQ (integer) interrupt number. + */ +int os_dev_get_irq(void); + + /*! @} *//* drsigargs */ + +/***************************************************************************** + * Functions for Generating References to Driver Routines + *****************************************************************************/ + +/*! + * @defgroup drref Functions for Generating References to Driver Routines + * + * These functions will most likely be implemented as macros. They are a + * necessary part of the portable API to guarantee portability. The @c symbol + * type in here is the same symbol passed to the associated + * signature-generating macro. + * + * These macros must be used whenever referring to a + * @ref drsigs "driver signature function", for instance when storing or + * passing a pointer to the function. + */ + +/*! @addtogroup drref */ +/*! @{ */ + +/*! + * Generate a reference to an #OS_DEV_INIT() function + * + * @param function_name The name of the init function being referenced. + * + * @return A reference to the function + */ +os_init_function_t OS_DEV_INIT_REF(symbol function_name); + +/*! + * Generate a reference to an #OS_DEV_SHUTDOWN() function + * + * @param function_name The name of the shutdown function being referenced. + * + * @return A reference to the function + */ +os_shutdown_function_t OS_DEV_SHUTDOWN_REF(symbol function_name); + +/*! + * Generate a reference to an #OS_DEV_OPEN() function + * + * @param function_name The name of the open function being referenced. + * + * @return A reference to the function + */ +os_user_function_t OS_DEV_OPEN_REF(symbol function_name); + +/*! + * Generate a reference to an #OS_DEV_CLOSE() function + * + * @param function_name The name of the close function being referenced. + * + * @return A reference to the function + */ +os_user_function_t OS_DEV_CLOSE_REF(symbol function_name); + +/*! + * Generate a reference to an #OS_DEV_READ() function + * + * @param function_name The name of the read function being referenced. + * + * @return A reference to the function + */ +os_user_function_t OS_DEV_READ_REF(symbol function_name); + +/*! + * Generate a reference to an #OS_DEV_WRITE() function + * + * @param function_name The name of the write function being referenced. + * + * @return A reference to the function + */ +os_user_function_t OS_DEV_WRITE_REF(symbol function_name); + +/*! + * Generate a reference to an #OS_DEV_IOCTL() function + * + * @param function_name The name of the ioctl function being referenced. + * + * @return A reference to the function + */ +os_user_function_t OS_DEV_IOCTL_REF(symbol function_name); + +/*! + * Generate a reference to an #OS_DEV_MMAP() function + * + * @param function_name The name of the mmap function being referenced. + * + * @return A reference to the function + */ +os_user_function_t OS_DEV_MMAP_REF(symbol function_name); + +/*! + * Generate a reference to an #OS_DEV_ISR() function + * + * @param function_name The name of the isr being referenced. + * + * @return a reference to the function + */ +os_interrupt_handler_t OS_DEV_ISR_REF(symbol function_name); + + /*! @} *//* drref */ + +/*! + * Flush and invalidate all cache lines. + */ +void os_flush_cache_all(void); + +/*! + * Flush a range of addresses from the cache + * + * @param start Starting virtual address + * @param len Number of bytes to flush + */ +void os_cache_flush_range(void *start, uint32_t len); + +/*! + * Invalidate a range of addresses in the cache + * + * @param start Starting virtual address + * @param len Number of bytes to flush + */ +void os_cache_inv_range(void *start, uint32_t len); + +/*! + * Clean a range of addresses from the cache + * + * @param start Starting virtual address + * @param len Number of bytes to flush + */ +void os_cache_clean_range(void *start, uint32_t len); + +/*! + * @example widget.h + */ + +/*! + * @example widget.c + */ + +/*! + * @example rng_driver.h + */ + +/*! + * @example rng_driver.c + */ + +/*! + * @example shw_driver.h + */ + +/*! + * @example shw_driver.c + */ + +#endif /* DOXYGEN_PORTABLE_OS_DOC */ + +#endif /* PORTABLE_OS_H */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/include/sah_driver_common.h linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sah_driver_common.h --- linux-2.6.26/drivers/mxc/security/sahara2/include/sah_driver_common.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sah_driver_common.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,102 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/** +* @file sah_driver_common.h +* +* @brief Provides types and defined values for use in the Driver Interface. +* +*/ + +#ifndef SAH_DRIVER_COMMON_H +#define SAH_DRIVER_COMMON_H + +#include "fsl_platform.h" +#include +#include + +/** This specifies the permissions for the device file. It is equivalent to + * chmod 666. + */ +#define SAHARA_DEVICE_MODE S_IFCHR | S_IRUGO | S_IWUGO + +/** +* The status of entries in the Queue. +* +******************************************************************************/ +typedef enum +{ + /** This state indicates that the entry is in the queue and awaits + * execution on SAHARA. */ + SAH_STATE_PENDING, + /** This state indicates that the entry has been written to the SAHARA + * DAR. */ + SAH_STATE_ON_SAHARA, + /** This state indicates that the entry is off of SAHARA, and is awaiting + post-processing. */ + SAH_STATE_OFF_SAHARA, + /** This state indicates that the entry is successfully executed on SAHARA, + and it is finished with post-processing. */ + SAH_STATE_COMPLETE, + /** This state indicates that the entry caused an error or fault on SAHARA, + * and it is finished with post-processing. */ + SAH_STATE_FAILED, + /** This state indicates that the entry was reset via the Reset IO + * Control, and it is finished with post-processing. */ + SAH_STATE_RESET, + /** This state indicates that the entry was signalled from user-space and + * either in the DAR, IDAR or has finished executing pending Bottom Half + * processing. */ + SAH_STATE_IGNORE, + /** This state indicates that the entry was signalled from user-space and + * has been processed by the bottom half. */ + SAH_STATE_IGNORED +} sah_Queue_Status; + +/* any of these conditions being true indicates the descriptor's processing + * is complete */ +#define SAH_DESC_PROCESSED(status) \ + (((status) == SAH_STATE_COMPLETE) || \ + ((status) == SAH_STATE_FAILED ) || \ + ((status) == SAH_STATE_RESET )) + +extern os_lock_t desc_queue_lock; + +extern uint32_t dar_count; +extern uint32_t interrupt_count; +extern uint32_t done1done2_count; +extern uint32_t done1busy2_count; +extern uint32_t done1_count; + +#ifdef FSL_HAVE_SCC2 +extern void *lookup_user_partition(fsl_shw_uco_t * user_ctx, + uint32_t user_base); +#endif + +int sah_get_results_pointers(fsl_shw_uco_t* user_ctx, uint32_t arg); +fsl_shw_return_t sah_get_results_from_pool(volatile fsl_shw_uco_t* user_ctx, + sah_results *arg); +fsl_shw_return_t sah_handle_registration(fsl_shw_uco_t *user_cts); +fsl_shw_return_t sah_handle_deregistration(fsl_shw_uco_t *user_cts); + +int sah_Queue_Manager_Count_Entries(int ignore_state, sah_Queue_Status state); +unsigned long sah_Handle_Poll(sah_Head_Desc *entry); + +#ifdef DIAG_DRV_IF +/****************************************************************************** +* Descriptor and Link dumping functions. +******************************************************************************/ +void sah_Dump_Chain(const sah_Desc *chain, dma_addr_t addr); +#endif /* DIAG_DRV_IF */ + +#endif /* SAH_DRIVER_COMMON_H */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/include/sah_hardware_interface.h linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sah_hardware_interface.h --- linux-2.6.26/drivers/mxc/security/sahara2/include/sah_hardware_interface.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sah_hardware_interface.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,99 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/** +* @file sah_hardware_interface.h +* +* @brief Provides an interface to the SAHARA hardware registers. +* +*/ + +#ifndef SAH_HARDWARE_INTERFACE_H +#define SAH_HARDWARE_INTERFACE_H + +#include +#include + +/* These values can be used with sah_HW_Write_Control(). */ +#ifdef SAHARA1 +/** Define platform as Little-Endian */ +#define CTRL_LITTLE_END 0x00000002 +/** Bit to cause endian change in transfers */ +#define CTRL_INT_EN 0x00000004 +/** Set High Assurance mode */ +#define CTRL_HA 0x00000008 +#else +/** Bit to cause byte swapping in (data?) transfers */ +#define CTRL_BYTE_SWAP 0x00000001 +/** Bit to cause halfword swapping in (data?) transfers */ +#define CTRL_HALFWORD_SWAP 0x00000002 +/** Bit to cause endian change in (data?) transfers */ +#define CTRL_INT_EN 0x00000010 +/** Set High Assurance mode */ +#define CTRL_HA 0x00000020 +/** Disable High Assurance */ +#define CTRL_HA_DISABLE 0x00000040 +/** Reseed the RNG CHA */ +#define CTRL_RNG_RESEED 0x00000080 +#endif + + +/* These values can be used with sah_HW_Write_Command(). */ +/** Reset the Sahara */ +#define CMD_RESET 0x00000001 +/** Set Sahara into Batch mode. */ +#define CMD_BATCH 0x00010000 +/** Clear the Sahara interrupt */ +#define CMD_CLR_INT_BIT 0x00000100 +/** Clear the Sahara error */ +#define CMD_CLR_ERROR_BIT 0x00000200 + + +/** error status register contains error */ +#define STATUS_ERROR 0x00000010 + +/** Op status register contains op status */ +#define OP_STATUS 0x00000020 + + +/* High Level functions */ +int sah_HW_Reset(void); +fsl_shw_return_t sah_HW_Set_HA(void); +sah_Execute_Status sah_Wait_On_Sahara(void); + +/* Low Level functions */ +uint32_t sah_HW_Read_Version(void); +uint32_t sah_HW_Read_Control(void); +uint32_t sah_HW_Read_Status(void); +uint32_t sah_HW_Read_Error_Status(void); +uint32_t sah_HW_Read_Op_Status(void); +uint32_t sah_HW_Read_DAR(void); +uint32_t sah_HW_Read_CDAR(void); +uint32_t sah_HW_Read_IDAR(void); +uint32_t sah_HW_Read_Fault_Address(void); +uint32_t sah_HW_Read_MM_Status(void); +uint32_t sah_HW_Read_Config(void); +void sah_HW_Write_Command(uint32_t command); +void sah_HW_Write_Control(uint32_t control); +void sah_HW_Write_DAR(uint32_t pointer); +void sah_HW_Write_Config(uint32_t configuration); + +#if defined DIAG_DRV_IF || defined(DO_DBG) + +void sah_Dump_Words(const char *prefix, const unsigned *data, dma_addr_t addr, + unsigned length); +#endif + +#endif /* SAH_HARDWARE_INTERFACE_H */ + +/* End of sah_hardware_interface.c */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/include/sah_interrupt_handler.h linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sah_interrupt_handler.h --- linux-2.6.26/drivers/mxc/security/sahara2/include/sah_interrupt_handler.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sah_interrupt_handler.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,42 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/** +* @file sah_interrupt_handler.h +* +* @brief Provides a hardware interrupt handling mechanism for device driver. +* +*/ +/****************************************************************************** +* +* CAUTION: +* +* MODIFICATION HISTORY: +* +* Date Person Change +* 30/07/03 MW Initial Creation +******************************************************************* +*/ + +#ifndef SAH_INTERRUPT_HANDLER_H +#define SAH_INTERRUPT_HANDLER_H + +#include + +/****************************************************************************** +* External function declarations +******************************************************************************/ +int sah_Intr_Init (wait_queue_head_t *wait_queue); +void sah_Intr_Release (void); + +#endif /* SAH_INTERRUPT_HANDLER_H */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/include/sah_kernel.h linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sah_kernel.h --- linux-2.6.26/drivers/mxc/security/sahara2/include/sah_kernel.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sah_kernel.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,113 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* +* @file sah_kernel.h +* +* @brief Provides definitions for items that user-space and kernel-space share. +*/ +/****************************************************************************** +* +* This file needs to be PORTED to a non-Linux platform +*/ + +#ifndef SAH_KERNEL_H +#define SAH_KERNEL_H + +#if defined(__KERNEL__) + +#if defined(CONFIG_ARCH_MXC91321) || defined(CONFIG_ARCH_MXC91231) \ + || defined(CONFIG_ARCH_MX27) || defined(CONFIG_ARCH_MXC92323) +#include +#define SAHA_BASE_ADDR SAHARA_BASE_ADDR +#define SAHARA_IRQ MXC_INT_SAHARA +#elif defined(CONFIG_ARCH_MX51) +#include +#define SAHA_BASE_ADDR SAHARA_BASE_ADDR +#define SAHARA_IRQ MXC_INT_SAHARA_H0 +#else +#include +#endif + +#endif /* KERNEL */ + +/* IO Controls */ +/* The magic number 'k' is reserved for the SPARC architecture. (See /Documentation/ioctl-number.txt. + * + * Note: Numbers 8-13 were used in a previous version of the API and should + * be avoided. + */ +#define SAH_IOC_MAGIC 'k' +#define SAHARA_HWRESET _IO(SAH_IOC_MAGIC, 0) +#define SAHARA_SET_HA _IO(SAH_IOC_MAGIC, 1) +#define SAHARA_CHK_TEST_MODE _IOR(SAH_IOC_MAGIC,2, int) +#define SAHARA_DAR _IO(SAH_IOC_MAGIC, 3) +#define SAHARA_GET_RESULTS _IO(SAH_IOC_MAGIC, 4) +#define SAHARA_REGISTER _IO(SAH_IOC_MAGIC, 5) +#define SAHARA_DEREGISTER _IO(SAH_IOC_MAGIC, 6) +/* 7 */ +/* 8 */ +/* 9 */ +/* 10 */ +/* 11 */ +/* 12 */ +/* 13 */ + +#define SAHARA_SCC_DROP_PERMS _IOWR(SAH_IOC_MAGIC, 14, scc_partition_info_t) +#define SAHARA_SCC_SFREE _IOWR(SAH_IOC_MAGIC, 15, scc_partition_info_t) + +#define SAHARA_SK_ALLOC _IOWR(SAH_IOC_MAGIC, 16, scc_slot_t) +#define SAHARA_SK_DEALLOC _IOWR(SAH_IOC_MAGIC, 17, scc_slot_t) +#define SAHARA_SK_LOAD _IOWR(SAH_IOC_MAGIC, 18, scc_slot_t) +#define SAHARA_SK_UNLOAD _IOWR(SAH_IOC_MAGIC, 19, scc_slot_t) +#define SAHARA_SK_SLOT_ENC _IOWR(SAH_IOC_MAGIC, 20, scc_slot_t) +#define SAHARA_SK_SLOT_DEC _IOWR(SAH_IOC_MAGIC, 21, scc_slot_t) + +#define SAHARA_SCC_ENCRYPT _IOWR(SAH_IOC_MAGIC, 22, scc_region_t) +#define SAHARA_SCC_DECRYPT _IOWR(SAH_IOC_MAGIC, 23, scc_region_t) +#define SAHARA_GET_CAPS _IOWR(SAH_IOC_MAGIC, 24, fsl_shw_pco_t) + +#define SAHARA_SCC_SSTATUS _IOWR(SAH_IOC_MAGIC, 25, scc_partition_info_t) + +#define SAHARA_SK_READ _IOWR(SAH_IOC_MAGIC, 29, scc_slot_t) + +/*! This is the name that will appear in /proc/interrupts */ +#define SAHARA_NAME "SAHARA" + +/*! + * SAHARA IRQ number. See page 9-239 of TLICS - Motorola Semiconductors H.K. + * TAHITI-Lite IC Specification, Rev 1.1, Feb 2003. + * + * TAHITI has two blocks of 32 interrupts. The SAHARA IRQ is number 27 + * in the second block. This means that the SAHARA IRQ is 27 + 32 = 59. + */ +#ifndef SAHARA_IRQ +#define SAHARA_IRQ (27+32) +#endif + +/*! + * Device file definition. The #ifndef is here to support the unit test code + * by allowing it to specify a different test device. + */ +#ifndef SAHARA_DEVICE_SHORT +#define SAHARA_DEVICE_SHORT "sahara" +#endif + +#ifndef SAHARA_DEVICE +#define SAHARA_DEVICE "/dev/"SAHARA_DEVICE_SHORT +#endif + +#endif /* SAH_KERNEL_H */ + +/* End of sah_kernel.h */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/include/sah_memory_mapper.h linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sah_memory_mapper.h --- linux-2.6.26/drivers/mxc/security/sahara2/include/sah_memory_mapper.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sah_memory_mapper.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,79 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/** +* @file sah_memory_mapper.h +* +* @brief Re-creates SAHARA data structures in Kernel memory such that they are +* suitable for DMA. +* +*/ + +#ifndef SAH_MEMORY_MAPPER_H +#define SAH_MEMORY_MAPPER_H + +#include +#include + + +/****************************************************************************** +* External function declarations +******************************************************************************/ +sah_Head_Desc *sah_Copy_Descriptors(fsl_shw_uco_t * user_ctx, + sah_Head_Desc * desc); + +sah_Link *sah_Copy_Links(fsl_shw_uco_t * user_ctx, sah_Link * ptr); + +sah_Head_Desc *sah_Physicalise_Descriptors(sah_Head_Desc * desc); + +sah_Link *sah_Physicalise_Links (sah_Link *ptr); + +sah_Head_Desc *sah_DePhysicalise_Descriptors (sah_Head_Desc *desc); + +sah_Link *sah_DePhysicalise_Links (sah_Link *ptr); + +sah_Link *sah_Make_Links(fsl_shw_uco_t * user_ctx, + sah_Link * ptr, sah_Link ** tail); + + +void sah_Destroy_Descriptors (sah_Head_Desc *desc); + +void sah_Destroy_Links (sah_Link *link); + +void sah_Free_Chained_Descriptors (sah_Head_Desc *desc); + +void sah_Free_Chained_Links (sah_Link *link); + +int sah_Init_Mem_Map (void); + +void sah_Stop_Mem_Map (void); + +int sah_Block_Add_Page (int big); + +sah_Desc *sah_Alloc_Descriptor (void); +sah_Head_Desc *sah_Alloc_Head_Descriptor (void); +void sah_Free_Descriptor (sah_Desc *desc); +void sah_Free_Head_Descriptor (sah_Head_Desc *desc); +sah_Link *sah_Alloc_Link (void); +void sah_Free_Link (sah_Link *link); + +void *wire_user_memory(void *address, uint32_t length, void **page_ctx); +void unwire_user_memory(void **page_ctx); + +os_error_code map_user_memory(struct vm_area_struct *vma, + uint32_t physical_addr, uint32_t size); +os_error_code unmap_user_memory(uint32_t user_addr, uint32_t size); + +#endif /* SAH_MEMORY_MAPPER_H */ + +/* End of sah_memory_mapper.h */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/include/sah_queue_manager.h linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sah_queue_manager.h --- linux-2.6.26/drivers/mxc/security/sahara2/include/sah_queue_manager.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sah_queue_manager.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,63 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/** +* @file sah_queue_manager.h +* +* @brief This file definitions for the Queue Manager. + +* The Queue Manager manages additions and removal from the queue and updates +* the status of queue entries. It also calls sah_HW_* functions to interact +* with the hardware. +* +*/ + +#ifndef SAH_QUEUE_MANAGER_H +#define SAH_QUEUE_MANAGER_H + +#include +#include + + +/************************* +* Queue Manager Functions +*************************/ +fsl_shw_return_t sah_Queue_Manager_Init(void); +void sah_Queue_Manager_Close(void); +void sah_Queue_Manager_Reset_Entries(void); +void sah_Queue_Manager_Append_Entry(sah_Head_Desc *entry); +void sah_Queue_Manager_Remove_Entry(sah_Head_Desc *entry); + + +/************************* +* Queue Functions +*************************/ +sah_Queue *sah_Queue_Construct(void); +void sah_Queue_Destroy(sah_Queue *this); +void sah_Queue_Append_Entry(sah_Queue *this, sah_Head_Desc *entry); +void sah_Queue_Remove_Entry(sah_Queue *this); +void sah_Queue_Remove_Any_Entry(sah_Queue *this, sah_Head_Desc *entry); +void sah_postprocess_queue(unsigned long reset_flag); + + +/************************* +* Misc Releated Functions +*************************/ + +int sah_blocking_mode(struct sah_Head_Desc *entry); +fsl_shw_return_t sah_convert_error_status(uint32_t error_status); + + +#endif /* SAH_QUEUE_MANAGER_H */ + +/* End of sah_queue_manager.h */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/include/sah_status_manager.h linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sah_status_manager.h --- linux-2.6.26/drivers/mxc/security/sahara2/include/sah_status_manager.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sah_status_manager.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,228 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/** +* @file sah_status_manager.h +* +* @brief SAHARA Status Manager Types and Function Prototypes +* +* @author Stuart Holloway (SH) +* +*/ + +#ifndef STATUS_MANAGER_H +#define STATUS_MANAGER_H +#include "sah_driver_common.h" +#include "sahara.h" + + +/****************************************************************************** +* User defined data types +******************************************************************************/ +/** +****************************************************************************** +* sah_Execute_Status +* Types read from SAHARA Status Register, with additional state for Op Status +******************************************************************************/ +typedef enum sah_Execute_Status +{ + /** Sahara is Idle. */ + SAH_EXEC_IDLE = 0, + /** SAHARA is busy performing a resest or processing a decriptor chain. */ + SAH_EXEC_BUSY = 1, + /** An error occurred while SAHARA executed the first descriptor. */ + SAH_EXEC_ERROR1 = 2, + /** SAHARA has failed internally. */ + SAH_EXEC_FAULT = 3, + /** SAHARA has finished processing a descriptor chain and is idle. */ + SAH_EXEC_DONE1 = 4, + /** SAHARA has finished processing a descriptor chain, and is processing a + * second chain. */ + SAH_EXEC_DONE1_BUSY2 = 5, + /** SAHARA has finished processing a descriptor chain, but has generated an + * error while processing a second descriptor chain. */ + SAH_EXEC_DONE1_ERROR2 = 6, + /** SAHARA has finished two descriptors. */ + SAH_EXEC_DONE1_DONE2 = 7, + /** SAHARA has stopped, and first descriptor has Op Status, not Err */ + SAH_EXEC_OPSTAT1 = 0x20, +} sah_Execute_Status; + +/** + * When this bit is on in a #sah_Execute_Status, it means that DONE1 is true. + */ +#define SAH_EXEC_DONE1_BIT 4 + +/** + * Bits which make up the Sahara State + */ +#define SAH_EXEC_STATE_MASK 0x00000007 + +/** +******************************************************************************* +* sah_Execute_Error +* Types read from SAHARA Error Status Register +******************************************************************************/ +typedef enum sah_Execute_Error +{ + /** No Error */ + SAH_ERR_NONE = 0, + /** Header is not valid. */ + SAH_ERR_HEADER = 1, + /** Descriptor length is not correct. */ + SAH_ERR_DESC_LENGTH = 2, + /** Length or pointer field is zero while the other is non-zero. */ + SAH_ERR_DESC_POINTER = 3, + /** Length of the link is not a multiple of 4 and is not the last link */ + SAH_ERR_LINK_LENGTH = 4, + /** The data pointer in a link is zero */ + SAH_ERR_LINK_POINTER = 5, + /** Input Buffer reported an overflow */ + SAH_ERR_INPUT_BUFFER = 6, + /** Output Buffer reported an underflow */ + SAH_ERR_OUTPUT_BUFFER = 7, + /** Incorrect data in output buffer after CHA's has signalled 'done'. */ + SAH_ERR_OUTPUT_BUFFER_STARVATION = 8, + /** Internal Hardware Failure. */ + SAH_ERR_INTERNAL_STATE = 9, + /** Current Descriptor was not legal, but cause is unknown. */ + SAH_ERR_GENERAL_DESCRIPTOR = 10, + /** Reserved pointer fields have been set to 1. */ + SAH_ERR_RESERVED_FIELDS = 11, + /** Descriptor address error */ + SAH_ERR_DESCRIPTOR_ADDRESS = 12, + /** Link address error */ + SAH_ERR_LINK_ADDRESS = 13, + /** Processing error in CHA module */ + SAH_ERR_CHA = 14, + /** Processing error during DMA */ + SAH_ERR_DMA = 15 +} sah_Execute_Error; + + +/** +******************************************************************************* +* sah_CHA_Error_Source +* Types read from SAHARA Error Status Register for CHA Error Source +* +******************************************************************************/ +typedef enum sah_CHA_Error_Source +{ + /** No Error indicated in Source CHA Error. */ + SAH_CHA_NO_ERROR = 0, + /** Error in SKHA module. */ + SAH_CHA_SKHA_ERROR = 1, + /** Error in MDHA module. */ + SAH_CHA_MDHA_ERROR = 2, + /** Error in RNG module. */ + SAH_CHA_RNG_ERROR = 3, + /** Error in PKHA module. */ + SAH_CHA_PKHA_ERROR = 4, +} sah_CHA_Error_Source; + +/** +****************************************************************************** +* sah_CHA_Error_Status +* Types read from SAHARA Error Status Register for CHA Error Status +* +******************************************************************************/ +typedef enum sah_CHA_Error_Status +{ + /** No CHA error detected */ + SAH_CHA_NO_ERR = 0x000, + /** Non-empty input buffer when complete. */ + SAH_CHA_IP_BUF = 0x001, + /** Illegal Address Error. */ + SAH_CHA_ADD_ERR = 0x002, + /** Illegal Mode Error. */ + SAH_CHA_MODE_ERR = 0x004, + /** Illegal Data Size Error. */ + SAH_CHA_DATA_SIZE_ERR = 0x008, + /** Illegal Key Size Error. */ + SAH_CHA_KEY_SIZE_ERR = 0x010, + /** Mode/Context/Key written during processing. */ + SAH_CHA_PROC_ERR = 0x020, + /** Context Read During Processing. */ + SAH_CHA_CTX_READ_ERR = 0x040, + /** Internal Hardware Error. */ + SAH_CHA_INTERNAL_HW_ERR = 0x080, + /** Input Buffer not enabled or underflow. */ + SAH_CHA_IP_BUFF_ERR = 0x100, + /** Output Buffer not enabled or overflow. */ + SAH_CHA_OP_BUFF_ERR = 0x200, + /** DES key parity error (SKHA) */ + SAH_CHA_DES_KEY_ERR = 0x400, + /** Reserved error code. */ + SAH_CHA_RES = 0x800 +} sah_CHA_Error_Status; + +/** +***************************************************************************** +* sah_DMA_Error_Status +* Types read from SAHARA Error Status Register for DMA Error Status +******************************************************************************/ +typedef enum sah_DMA_Error_Status +{ + /** No DMA Error Code. */ + SAH_DMA_NO_ERR = 0, + /** AHB terminated a bus cycle with an error. */ + SAH_DMA_AHB_ERR = 2, + /** Internal IP bus cycle was terminated with an error termination. */ + SAH_DMA_IP_ERR = 4, + /** Parity error detected on DMA command. */ + SAH_DMA_PARITY_ERR = 6, + /** DMA was requested to cross a 256 byte internal address boundary. */ + SAH_DMA_BOUNDRY_ERR = 8, + /** DMA controller is busy */ + SAH_DMA_BUSY_ERR = 10, + /** Memory Bounds Error */ + SAH_DMA_RESERVED_ERR = 12, + /** Internal DMA hardware error detected */ + SAH_DMA_INT_ERR = 14 +} sah_DMA_Error_Status; + +/** +***************************************************************************** +* sah_DMA_Error_Size +* Types read from SAHARA Error Status Register for DMA Error Size +* +******************************************************************************/ +typedef enum sah_DMA_Error_Size +{ + /** Error during Byte transfer. */ + SAH_DMA_SIZE_BYTE = 0, + /** Error during Half-word transfer. */ + SAH_DMA_SIZE_HALF_WORD = 1, + /** Error during Word transfer. */ + SAH_DMA_SIZE_WORD = 2, + /** Reserved DMA word size. */ + SAH_DMA_SIZE_RES = 3 +} sah_DMA_Error_Size; + + + + +extern bool sah_dpm_flag; + +/************************* +* Status Manager Functions +*************************/ + +unsigned long sah_Handle_Interrupt(sah_Execute_Status hw_status); +sah_Head_Desc *sah_Find_With_State (sah_Queue_Status status); +int sah_dpm_init(void); +void sah_dpm_close(void); +void sah_Queue_Manager_Prime (sah_Head_Desc *entry); + + +#endif /* STATUS_MANAGER_H */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/include/sahara.h linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sahara.h --- linux-2.6.26/drivers/mxc/security/sahara2/include/sahara.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sahara.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,2266 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file sahara.h + * + * File which implements the FSL_SHW API when used on Sahara + */ +/*! + * @if USE_MAINPAGE + * @mainpage Sahara2 implemtation of FSL Security Hardware API + * @endif + * + */ + +#define _DIAG_DRV_IF +#define _DIAG_SECURITY_FUNC +#define _DIAG_ADAPTOR + +#ifndef SAHARA2_API_H +#define SAHARA2_API_H + +#ifdef DIAG_SECURITY_FUNC +#include +#endif /* DIAG_SECURITY_FUNC */ + +/* This is a Linux flag... ? */ +#ifndef __KERNEL__ +#include +#include +#include +#else +#include "portable_os.h" +#endif + +/* This definition may need a new name, and needs to go somewhere which + * can determine platform, kernel vs. user, os, etc. + */ +#define copy_bytes(out, in, len) memcpy(out, in, len) + +/* Does this belong here? */ +#ifndef SAHARA_DEVICE +#define SAHARA_DEVICE "/dev/sahara" +#endif + +/*! +******************************************************************************* +* @defgroup lnkflags Link Flags +* +* @brief Flags to show information about link data and link segments +* +******************************************************************************/ +/*! @addtogroup lnkflags + * @{ + */ + +/*! +******************************************************************************* +* This flag indicates that the data in a link is owned by the security +* function component and this memory will be freed by the security function +* component. To be used as part of the flag field of the sah_Link structure. +******************************************************************************/ +#define SAH_OWNS_LINK_DATA 0x01 + +/*! +******************************************************************************* +* The data in a link is not owned by the security function component and +* therefore it will not attempt to free this memory. To be used as part of the +* flag field of the sah_Link structure. +******************************************************************************/ +#define SAH_USES_LINK_DATA 0x02 + +/*! +******************************************************************************* +* The data in this link will change when the descriptor gets executed. +******************************************************************************/ +#define SAH_OUTPUT_LINK 0x04 + +/*! +******************************************************************************* +* The ptr and length in this link are really 'established key' info. They +* are to be converted to ptr/length before putting on request queue. +******************************************************************************/ +#define SAH_KEY_IS_HIDDEN 0x08 + +/*! +******************************************************************************* +* The link structure has been appended to the previous one by the driver. It +* needs to be removed before leaving the driver (and returning to API). +******************************************************************************/ +#define SAH_REWORKED_LINK 0x10 + +/*! +******************************************************************************* +* The length and data fields of this link contain the slot and user id +* used to access the SCC stored key +******************************************************************************/ +#define SAH_STORED_KEY_INFO 0x20 + +/*! +******************************************************************************* +* The Data field points to a physical address, and does not need to be +* processed by the driver. Honored only in Kernel API. +******************************************************************************/ +#define SAH_PREPHYS_DATA 0x40 + +/*! +******************************************************************************* +* The link was inserted during the Physicalise procedure. It is tagged so +* it can be removed during DePhysicalise, thereby returning to the caller an +* intact chain. +******************************************************************************/ +#define SAH_LINK_INSERTED_LINK 0x80 + +/*! +******************************************************************************* +* The Data field points to the location of the key, which is in a secure +* partition held by the user. The memory address needs to be converted to +* kernel space manually, by looking through the partitions that the user holds. +******************************************************************************/ +#define SAH_IN_USER_KEYSTORE 0x100 + +/*! +******************************************************************************* +* sah_Link_Flags +* +* Type to be used for flags associated with a Link in security function. +* These flags are used internally by the security function component only. +* +* Values defined at @ref lnkflags +* +* @brief typedef for flags field of sah_Link +******************************************************************************/ +typedef uint32_t sah_Link_Flags; + +/* +******************************************************************************* +* Security Parameters Related Structures +* +* All of structures associated with API parameters +* +******************************************************************************/ + +/* +******************************************************************************* +* Common Types +* +* All of structures used across several classes of crytography +******************************************************************************/ + +/*! +******************************************************************************* +* @brief Indefinite precision integer used for security operations on SAHARA +* accelerator. The data will always be in little Endian format. +******************************************************************************/ +typedef uint8_t *sah_Int; + +/*! +******************************************************************************* +* @brief Byte array used for block cipher and hash digest/MAC operations on +* SAHARA accelerator. The Endian format will be as specified by the function +* using the sah_Oct_Str. +******************************************************************************/ +typedef uint8_t *sah_Oct_Str; + +/*! + * A queue of descriptor heads -- used to hold requests waiting for user to + * pick up the results. */ +typedef struct sah_Queue { + int count; /*!< # entries in queue */ + struct sah_Head_Desc *head; /*!< first entry in queue */ + struct sah_Head_Desc *tail; /*!< last entry in queue */ +} sah_Queue; + +/****************************************************************************** + * Enumerations + *****************************************************************************/ +/*! + * Flags for the state of the User Context Object (#fsl_shw_uco_t). + */ +typedef enum fsl_shw_user_ctx_flags_t { + /*! + * API will block the caller until operation completes. The result will be + * available in the return code. If this is not set, user will have to get + * results using #fsl_shw_get_results(). + */ + FSL_UCO_BLOCKING_MODE = 0x01, + /*! + * User wants callback (at the function specified with + * #fsl_shw_uco_set_callback()) when the operation completes. This flag is + * valid only if #FSL_UCO_BLOCKING_MODE is not set. + */ + FSL_UCO_CALLBACK_MODE = 0x02, + /*! Do not free descriptor chain after driver (adaptor) finishes */ + FSL_UCO_SAVE_DESC_CHAIN = 0x04, + /*! + * User has made at least one request with callbacks requested, so API is + * ready to handle others. + */ + FSL_UCO_CALLBACK_SETUP_COMPLETE = 0x08, + /*! + * (virtual) pointer to descriptor chain is completely linked with physical + * (DMA) addresses, ready for the hardware. This flag should not be used + * by FSL SHW API programs. + */ + FSL_UCO_CHAIN_PREPHYSICALIZED = 0x10, + /*! + * The user has changed the context but the changes have not been copied to + * the kernel driver. + */ + FSL_UCO_CONTEXT_CHANGED = 0x20, + /*! Internal Use. This context belongs to a user-mode API user. */ + FSL_UCO_USERMODE_USER = 0x40, +} fsl_shw_user_ctx_flags_t; + +/*! + * Return code for FSL_SHW library. + * + * These codes may be returned from a function call. In non-blocking mode, + * they will appear as the status in a Result Object. + */ +typedef enum fsl_shw_return_t { + /*! + * No error. As a function return code in Non-blocking mode, this may + * simply mean that the operation was accepted for eventual execution. + */ + FSL_RETURN_OK_S = 0, + /*! Failure for non-specific reason. */ + FSL_RETURN_ERROR_S, + /*! + * Operation failed because some resource was not able to be allocated. + */ + FSL_RETURN_NO_RESOURCE_S, + /*! Crypto algorithm unrecognized or improper. */ + FSL_RETURN_BAD_ALGORITHM_S, + /*! Crypto mode unrecognized or improper. */ + FSL_RETURN_BAD_MODE_S, + /*! Flag setting unrecognized or inconsistent. */ + FSL_RETURN_BAD_FLAG_S, + /*! Improper or unsupported key length for algorithm. */ + FSL_RETURN_BAD_KEY_LENGTH_S, + /*! Improper parity in a (DES, TDES) key. */ + FSL_RETURN_BAD_KEY_PARITY_S, + /*! + * Improper or unsupported data length for algorithm or internal buffer. + */ + FSL_RETURN_BAD_DATA_LENGTH_S, + /*! Authentication / Integrity Check code check failed. */ + FSL_RETURN_AUTH_FAILED_S, + /*! A memory error occurred. */ + FSL_RETURN_MEMORY_ERROR_S, + /*! An error internal to the hardware occurred. */ + FSL_RETURN_INTERNAL_ERROR_S, + /*! ECC detected Point at Infinity */ + FSL_RETURN_POINT_AT_INFINITY_S, + /*! ECC detected No Point at Infinity */ + FSL_RETURN_POINT_NOT_AT_INFINITY_S, + /*! GCD is One */ + FSL_RETURN_GCD_IS_ONE_S, + /*! GCD is not One */ + FSL_RETURN_GCD_IS_NOT_ONE_S, + /*! Candidate is Prime */ + FSL_RETURN_PRIME_S, + /*! Candidate is not Prime */ + FSL_RETURN_NOT_PRIME_S, + /*! N register loaded improperly with even value */ + FSL_RETURN_EVEN_MODULUS_ERROR_S, + /*! Divisor is zero. */ + FSL_RETURN_DIVIDE_BY_ZERO_ERROR_S, + /*! Bad Exponent or Scalar value for Point Multiply */ + FSL_RETURN_BAD_EXPONENT_ERROR_S, + /*! RNG hardware problem. */ + FSL_RETURN_OSCILLATOR_ERROR_S, + /*! RNG hardware problem. */ + FSL_RETURN_STATISTICS_ERROR_S, +} fsl_shw_return_t; + +/*! + * Algorithm Identifier. + * + * Selection of algorithm will determine how large the block size of the + * algorithm is. Context size is the same length unless otherwise specified. + * Selection of algorithm also affects the allowable key length. + */ +typedef enum fsl_shw_key_alg_t { + /*! + * Key will be used to perform an HMAC. Key size is 1 to 64 octets. Block + * size is 64 octets. + */ + FSL_KEY_ALG_HMAC, + /*! + * Advanced Encryption Standard (Rijndael). Block size is 16 octets. Key + * size is 16 octets. (The single choice of key size is a Sahara platform + * limitation.) + */ + FSL_KEY_ALG_AES, + /*! + * Data Encryption Standard. Block size is 8 octets. Key size is 8 + * octets. + */ + FSL_KEY_ALG_DES, + /*! + * 2- or 3-key Triple DES. Block size is 8 octets. Key size is 16 octets + * for 2-key Triple DES, and 24 octets for 3-key. + */ + FSL_KEY_ALG_TDES, + /*! + * ARC4. No block size. Context size is 259 octets. Allowed key size is + * 1-16 octets. (The choices for key size are a Sahara platform + * limitation.) + */ + FSL_KEY_ALG_ARC4, + /*! + * Private key of a public-private key-pair. Max is 512 bits... + */ + FSL_KEY_PK_PRIVATE, +} fsl_shw_key_alg_t; + +/*! + * Mode selector for Symmetric Ciphers. + * + * The selection of mode determines how a cryptographic algorithm will be + * used to process the plaintext or ciphertext. + * + * For all modes which are run block-by-block (that is, all but + * #FSL_SYM_MODE_STREAM), any partial operations must be performed on a text + * length which is multiple of the block size. Except for #FSL_SYM_MODE_CTR, + * these block-by-block algorithms must also be passed a total number of octets + * which is a multiple of the block size. + * + * In modes which require that the total number of octets of data be a multiple + * of the block size (#FSL_SYM_MODE_ECB and #FSL_SYM_MODE_CBC), and the user + * has a total number of octets which are not a multiple of the block size, the + * user must perform any necessary padding to get to the correct data length. + */ +typedef enum fsl_shw_sym_mode_t { + /*! + * Stream. There is no associated block size. Any request to process data + * may be of any length. This mode is only for ARC4 operations, and is + * also the only mode used for ARC4. + */ + FSL_SYM_MODE_STREAM, + + /*! + * Electronic Codebook. Each block of data is encrypted/decrypted. The + * length of the data stream must be a multiple of the block size. This + * mode may be used for DES, 3DES, and AES. The block size is determined + * by the algorithm. + */ + FSL_SYM_MODE_ECB, + /*! + * Cipher-Block Chaining. Each block of data is encrypted/decrypted and + * then "chained" with the previous block by an XOR function. Requires + * context to start the XOR (previous block). This mode may be used for + * DES, 3DES, and AES. The block size is determined by the algorithm. + */ + FSL_SYM_MODE_CBC, + /*! + * Counter. The counter is encrypted, then XORed with a block of data. + * The counter is then incremented (using modulus arithmetic) for the next + * block. The final operation may be non-multiple of block size. This mode + * may be used for AES. The block size is determined by the algorithm. + */ + FSL_SYM_MODE_CTR, +} fsl_shw_sym_mode_t; + +/*! + * Algorithm selector for Cryptographic Hash functions. + * + * Selection of algorithm determines how large the context and digest will be. + * Context is the same size as the digest (resulting hash), unless otherwise + * specified. + */ +typedef enum fsl_shw_hash_alg_t { + /*! MD5 algorithm. Digest is 16 octets. */ + FSL_HASH_ALG_MD5, + /*! SHA-1 (aka SHA or SHA-160) algorithm. Digest is 20 octets. */ + FSL_HASH_ALG_SHA1, + /*! + * SHA-224 algorithm. Digest is 28 octets, though context is 32 octets. + */ + FSL_HASH_ALG_SHA224, + /*! SHA-256 algorithm. Digest is 32 octets. */ + FSL_HASH_ALG_SHA256 +} fsl_shw_hash_alg_t; + +/*! + * The type of Authentication-Cipher function which will be performed. + */ +typedef enum fsl_shw_acc_mode_t { + /*! + * CBC-MAC for Counter. Requires context and modulus. Final operation may + * be non-multiple of block size. This mode may be used for AES. + */ + FSL_ACC_MODE_CCM, + /*! + * SSL mode. Not supported. Combines HMAC and encrypt (or decrypt). + * Needs one key object for encryption, another for the HMAC. The usual + * hashing and symmetric encryption algorithms are supported. + */ + FSL_ACC_MODE_SSL, +} fsl_shw_acc_mode_t; + +/* REQ-S2LRD-PINTFC-COA-HCO-001 */ +/*! + * Flags which control a Hash operation. + */ +typedef enum fsl_shw_hash_ctx_flags_t { + /*! + * Context is empty. Hash is started from scratch, with a + * message-processed count of zero. + */ + FSL_HASH_FLAGS_INIT = 0x01, + /*! + * Retrieve context from hardware after hashing. If used with the + * #FSL_HASH_FLAGS_FINALIZE flag, the final digest value will be saved in + * the object. + */ + FSL_HASH_FLAGS_SAVE = 0x02, + /*! Place context into hardware before hashing. */ + FSL_HASH_FLAGS_LOAD = 0x04, + /*! + * PAD message and perform final digest operation. If user message is + * pre-padded, this flag should not be used. + */ + FSL_HASH_FLAGS_FINALIZE = 0x08, +} fsl_shw_hash_ctx_flags_t; + +/*! + * Flags which control an HMAC operation. + * + * These may be combined by ORing them together. See #fsl_shw_hmco_set_flags() + * and #fsl_shw_hmco_clear_flags(). + */ +typedef enum fsl_shw_hmac_ctx_flags_t { + /*! + * Message context is empty. HMAC is started from scratch (with key) or + * from precompute of inner hash, depending on whether + * #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT is set. + */ + FSL_HMAC_FLAGS_INIT = 1, + /*! + * Retrieve ongoing context from hardware after hashing. If used with the + * #FSL_HMAC_FLAGS_FINALIZE flag, the final digest value (HMAC) will be + * saved in the object. + */ + FSL_HMAC_FLAGS_SAVE = 2, + /*! Place ongoing context into hardware before hashing. */ + FSL_HMAC_FLAGS_LOAD = 4, + /*! + * PAD message and perform final HMAC operations of inner and outer + * hashes. + */ + FSL_HMAC_FLAGS_FINALIZE = 8, + /*! + * This means that the context contains precomputed inner and outer hash + * values. + */ + FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT = 16, +} fsl_shw_hmac_ctx_flags_t; + +/*! + * Flags to control use of the #fsl_shw_scco_t. + * + * These may be ORed together to get the desired effect. + * See #fsl_shw_scco_set_flags() and #fsl_shw_scco_clear_flags() + */ +typedef enum fsl_shw_sym_ctx_flags_t { + /*! + * Context is empty. In ARC4, this means that the S-Box needs to be + * generated from the key. In #FSL_SYM_MODE_CBC mode, this allows an IV of + * zero to be specified. In #FSL_SYM_MODE_CTR mode, it means that an + * initial CTR value of zero is desired. + */ + FSL_SYM_CTX_INIT = 1, + /*! + * Load context from object into hardware before running cipher. In + * #FSL_SYM_MODE_CTR mode, this would refer to the Counter Value. + */ + FSL_SYM_CTX_LOAD = 2, + /*! + * Save context from hardware into object after running cipher. In + * #FSL_SYM_MODE_CTR mode, this would refer to the Counter Value. + */ + FSL_SYM_CTX_SAVE = 4, + /*! + * Context (SBox) is to be unwrapped and wrapped on each use. + * This flag is unsupported. + * */ + FSL_SYM_CTX_PROTECT = 8, +} fsl_shw_sym_ctx_flags_t; + +/*! + * Flags which describe the state of the #fsl_shw_sko_t. + * + * These may be ORed together to get the desired effect. + * See #fsl_shw_sko_set_flags() and #fsl_shw_sko_clear_flags() + */ +typedef enum fsl_shw_key_flags_t { + /*! If algorithm is DES or 3DES, do not validate the key parity bits. */ + FSL_SKO_KEY_IGNORE_PARITY = 1, + /*! Clear key is present in the object. */ + FSL_SKO_KEY_PRESENT = 2, + /*! + * Key has been established for use. This feature is not available for all + * platforms, nor for all algorithms and modes. + */ + FSL_SKO_KEY_ESTABLISHED = 4, + /*! + * Key intended for user (software) use; can be read cleartext from the + * keystore. + */ + FSL_SKO_KEY_SW_KEY = 8, +} fsl_shw_key_flags_t; + +/*! + * Type of value which is associated with an established key. + */ +typedef uint64_t key_userid_t; + +/*! + * Flags which describe the state of the #fsl_shw_acco_t. + * + * The @a FSL_ACCO_CTX_INIT and @a FSL_ACCO_CTX_FINALIZE flags, when used + * together, provide for a one-shot operation. + */ +typedef enum fsl_shw_auth_ctx_flags_t { + /*! Initialize Context(s) */ + FSL_ACCO_CTX_INIT = 1, + /*! Load intermediate context(s). This flag is unsupported. */ + FSL_ACCO_CTX_LOAD = 2, + /*! Save intermediate context(s). This flag is unsupported. */ + FSL_ACCO_CTX_SAVE = 4, + /*! Create MAC during this operation. */ + FSL_ACCO_CTX_FINALIZE = 8, + /*! + * Formatting of CCM input data is performed by calls to + * #fsl_shw_ccm_nist_format_ctr_and_iv() and + * #fsl_shw_ccm_nist_update_ctr_and_iv(). + */ + FSL_ACCO_NIST_CCM = 0x10, +} fsl_shw_auth_ctx_flags_t; + +/*! + * The operation which controls the behavior of #fsl_shw_establish_key(). + * + * These values are passed to #fsl_shw_establish_key(). + */ +typedef enum fsl_shw_key_wrap_t { + /*! Generate a key from random values. */ + FSL_KEY_WRAP_CREATE, + /*! Use the provided clear key. */ + FSL_KEY_WRAP_ACCEPT, + /*! Unwrap a previously wrapped key. */ + FSL_KEY_WRAP_UNWRAP +} fsl_shw_key_wrap_t; + +/*! + * Modulus Selector for CTR modes. + * + * The incrementing of the Counter value may be modified by a modulus. If no + * modulus is needed or desired for AES, use #FSL_CTR_MOD_128. + */ +typedef enum fsl_shw_ctr_mod_t { + FSL_CTR_MOD_8, /*!< Run counter with modulus of 2^8. */ + FSL_CTR_MOD_16, /*!< Run counter with modulus of 2^16. */ + FSL_CTR_MOD_24, /*!< Run counter with modulus of 2^24. */ + FSL_CTR_MOD_32, /*!< Run counter with modulus of 2^32. */ + FSL_CTR_MOD_40, /*!< Run counter with modulus of 2^40. */ + FSL_CTR_MOD_48, /*!< Run counter with modulus of 2^48. */ + FSL_CTR_MOD_56, /*!< Run counter with modulus of 2^56. */ + FSL_CTR_MOD_64, /*!< Run counter with modulus of 2^64. */ + FSL_CTR_MOD_72, /*!< Run counter with modulus of 2^72. */ + FSL_CTR_MOD_80, /*!< Run counter with modulus of 2^80. */ + FSL_CTR_MOD_88, /*!< Run counter with modulus of 2^88. */ + FSL_CTR_MOD_96, /*!< Run counter with modulus of 2^96. */ + FSL_CTR_MOD_104, /*!< Run counter with modulus of 2^104. */ + FSL_CTR_MOD_112, /*!< Run counter with modulus of 2^112. */ + FSL_CTR_MOD_120, /*!< Run counter with modulus of 2^120. */ + FSL_CTR_MOD_128 /*!< Run counter with modulus of 2^128. */ +} fsl_shw_ctr_mod_t; + +/*! + * Permissions flags for Secure Partitions + */ +typedef enum fsl_shw_permission_t { +/*! SCM Access Permission: Do not zeroize/deallocate partition on SMN Fail state */ + FSL_PERM_NO_ZEROIZE = 0x80000000, +/*! SCM Access Permission: Enforce trusted key read in */ + FSL_PERM_TRUSTED_KEY_READ = 0x40000000, +/*! SCM Access Permission: Ignore Supervisor/User mode in permission determination */ + FSL_PERM_HD_S = 0x00000800, +/*! SCM Access Permission: Allow Read Access to Host Domain */ + FSL_PERM_HD_R = 0x00000400, +/*! SCM Access Permission: Allow Write Access to Host Domain */ + FSL_PERM_HD_W = 0x00000200, +/*! SCM Access Permission: Allow Execute Access to Host Domain */ + FSL_PERM_HD_X = 0x00000100, +/*! SCM Access Permission: Allow Read Access to Trusted Host Domain */ + FSL_PERM_TH_R = 0x00000040, +/*! SCM Access Permission: Allow Write Access to Trusted Host Domain */ + FSL_PERM_TH_W = 0x00000020, +/*! SCM Access Permission: Allow Read Access to Other/World Domain */ + FSL_PERM_OT_R = 0x00000004, +/*! SCM Access Permission: Allow Write Access to Other/World Domain */ + FSL_PERM_OT_W = 0x00000002, +/*! SCM Access Permission: Allow Execute Access to Other/World Domain */ + FSL_PERM_OT_X = 0x00000001, +} fsl_shw_permission_t; + +typedef enum fsl_shw_cypher_mode_t { + FSL_SHW_CYPHER_MODE_ECB = 1, /*!< ECB mode */ + FSL_SHW_CYPHER_MODE_CBC = 2, /*!< CBC mode */ +} fsl_shw_cypher_mode_t; + +typedef enum fsl_shw_pf_key_t { + FSL_SHW_PF_KEY_IIM, /*!< Present fused IIM key */ + FSL_SHW_PF_KEY_PRG, /*!< Present Program key */ + FSL_SHW_PF_KEY_IIM_PRG, /*!< Present IIM ^ Program key */ + FSL_SHW_PF_KEY_IIM_RND, /*!< Present Random key */ + FSL_SHW_PF_KEY_RND, /*!< Present IIM ^ Random key */ +} fsl_shw_pf_key_t; + +typedef enum fsl_shw_tamper_t { + FSL_SHW_TAMPER_NONE, /*!< No error detected */ + FSL_SHW_TAMPER_WTD, /*!< wire-mesh tampering det */ + FSL_SHW_TAMPER_ETBD, /*!< ext tampering det: input B */ + FSL_SHW_TAMPER_ETAD, /*!< ext tampering det: input A */ + FSL_SHW_TAMPER_EBD, /*!< external boot detected */ + FSL_SHW_TAMPER_SAD, /*!< security alarm detected */ + FSL_SHW_TAMPER_TTD, /*!< temperature tampering det */ + FSL_SHW_TAMPER_CTD, /*!< clock tampering det */ + FSL_SHW_TAMPER_VTD, /*!< voltage tampering det */ + FSL_SHW_TAMPER_MCO, /*!< monotonic counter overflow */ + FSL_SHW_TAMPER_TCO, /*!< time counter overflow */ +} fsl_shw_tamper_t; + +/****************************************************************************** + * Data Structures + *****************************************************************************/ + +/*! + * + * @brief Structure type for descriptors + * + * The first five fields are passed to the hardware. + * + *****************************************************************************/ +#ifndef USE_NEW_PTRS /* Experimental */ + +typedef struct sah_Desc { + uint32_t header; /*!< descriptor header value */ + uint32_t len1; /*!< number of data bytes in 'ptr1' buffer */ + void *ptr1; /*!< pointer to first sah_Link structure */ + uint32_t len2; /*!< number of data bytes in 'ptr2' buffer */ + void *ptr2; /*!< pointer to second sah_Link structure */ + struct sah_Desc *next; /*!< pointer to next descriptor */ +#ifdef __KERNEL__ /* This needs a better test */ + /* These two must be last. See sah_Copy_Descriptors */ + struct sah_Desc *virt_addr; /*!< Virtual (kernel) address of this + descriptor. */ + dma_addr_t dma_addr; /*!< Physical (bus) address of this + descriptor. */ + void *original_ptr1; /*!< user's pointer to ptr1 */ + void *original_ptr2; /*!< user's pointer to ptr2 */ + struct sah_Desc *original_next; /*!< user's pointer to next */ +#endif +} sah_Desc; + +#else + +typedef struct sah_Desc { + uint32_t header; /*!< descriptor header value */ + uint32_t len1; /*!< number of data bytes in 'ptr1' buffer */ + uint32_t hw_ptr1; /*!< pointer to first sah_Link structure */ + uint32_t len2; /*!< number of data bytes in 'ptr2' buffer */ + uint32_t hw_ptr2; /*!< pointer to second sah_Link structure */ + uint32_t hw_next; /*!< pointer to next descriptor */ + struct sah_Link *ptr1; /*!< (virtual) pointer to first sah_Link structure */ + struct sah_Link *ptr2; /*!< (virtual) pointer to first sah_Link structure */ + struct sah_Desc *next; /*!< (virtual) pointer to next descriptor */ +#ifdef __KERNEL__ /* This needs a better test */ + /* These two must be last. See sah_Copy_Descriptors */ + struct sah_Desc *virt_addr; /*!< Virtual (kernel) address of this + descriptor. */ + dma_addr_t dma_addr; /*!< Physical (bus) address of this + descriptor. */ +#endif +} sah_Desc; + +#endif + +/*! +******************************************************************************* +* @brief The first descriptor in a chain +******************************************************************************/ +typedef struct sah_Head_Desc { + sah_Desc desc; /*!< whole struct - must be first */ + struct fsl_shw_uco_t *user_info; /*!< where result pool lives */ + uint32_t user_ref; /*!< at time of request */ + uint32_t uco_flags; /*!< at time of request */ + uint32_t status; /*!< Status of queue entry */ + uint32_t error_status; /*!< If error, register from Sahara */ + uint32_t fault_address; /*!< If error, register from Sahara */ + uint32_t op_status; /*!< If error, register from Sahara */ + fsl_shw_return_t result; /*!< Result of running descriptor */ + struct sah_Head_Desc *next; /*!< Next in queue */ + struct sah_Head_Desc *prev; /*!< previous in queue */ + struct sah_Head_Desc *user_desc; /*!< For API async get_results */ + void *out1_ptr; /*!< For async post-processing */ + void *out2_ptr; /*!< For async post-processing */ + uint32_t out_len; /*!< For async post-processing */ +} sah_Head_Desc; + +/*! + * @brief Structure type for links + * + * The first three fields are used by hardware. + *****************************************************************************/ +#ifndef USE_NEW_PTRS + +typedef struct sah_Link { + size_t len; /*!< len of 'data' buffer in bytes */ + uint8_t *data; /*!< buffer to store data */ + struct sah_Link *next; /*!< pointer to the next sah_Link storing + * data */ + sah_Link_Flags flags; /*!< indicates the component that created the + * data buffer. Security Function internal + * information */ + key_userid_t ownerid; /*!< Auth code for established key */ + uint32_t slot; /*!< Location of the the established key */ +#ifdef __KERNEL__ /* This needs a better test */ + /* These two elements must be last. See sah_Copy_Links() */ + struct sah_Link *virt_addr; + dma_addr_t dma_addr; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) + struct page *vm_info; +#endif + uint8_t *original_data; /*!< user's version of data pointer */ + struct sah_Link *original_next; /*!< user's version of next pointer */ +#ifdef SAH_COPY_DATA + uint8_t *copy_data; /*!< Virtual address of acquired buffer */ +#endif +#endif /* kernel-only */ +} sah_Link; + +#else + +typedef struct sah_Link { + /*! len of 'data' buffer in bytes */ + size_t len; + /*! buffer to store data */ + uint32_t hw_data; + /*! Physical address */ + uint32_t hw_next; + /*! + * indicates the component that created the data buffer. Security Function + * internal information + */ + sah_Link_Flags flags; + /*! (virtual) pointer to data */ + uint8_t *data; + /*! (virtual) pointer to the next sah_Link storing data */ + struct sah_Link *next; + /*! Auth code for established key */ + key_userid_t ownerid; + /*! Location of the the established key */ + uint32_t slot; +#ifdef __KERNEL__ /* This needs a better test */ + /* These two elements must be last. See sah_Copy_Links() */ + struct sah_Link *virt_addr; + dma_addr_t dma_addr; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) + struct page *vm_info; +#endif +#endif /* kernel-only */ +} sah_Link; + +#endif + +/*! + * Initialization Object + */ +typedef struct fsl_sho_ibo_t { +} fsl_sho_ibo_t; + +/* Imported from Sahara1 driver -- is it needed forever? */ +/*! +******************************************************************************* +* FIELDS +* +* void * ref - parameter to be passed into the memory function calls +* +* void * (*malloc)(void *ref, size_t n) - pointer to user's malloc function +* +* void (*free)(void *ref, void *ptr) - pointer to user's free function +* +* void * (*memcpy)(void *ref, void *dest, const void *src, size_t n) - +* pointer to user's memcpy function +* +* void * (*memset)(void *ref, void *ptr, int ch, size_t n) - pointer to +* user's memset function +* +* @brief Structure for API memory utilities +******************************************************************************/ +typedef struct sah_Mem_Util { + /*! Who knows. Vestigial. */ + void *mu_ref; + /*! Acquire buffer of size n bytes */ + void *(*mu_malloc) (void *ref, size_t n); + /*! Acquire a sah_Head_Desc */ + sah_Head_Desc *(*mu_alloc_head_desc) (void *ref); + /* Acquire a sah_Desc */ + sah_Desc *(*mu_alloc_desc) (void *ref); + /* Acquire a sah_Link */ + sah_Link *(*mu_alloc_link) (void *ref); + /*! Free buffer at ptr */ + void (*mu_free) (void *ref, void *ptr); + /*! Free sah_Head_Desc at ptr */ + void (*mu_free_head_desc) (void *ref, sah_Head_Desc * ptr); + /*! Free sah_Desc at ptr */ + void (*mu_free_desc) (void *ref, sah_Desc * ptr); + /*! Free sah_Link at ptr */ + void (*mu_free_link) (void *ref, sah_Link * ptr); + /*! Funciton which will copy n bytes from src to dest */ + void *(*mu_memcpy) (void *ref, void *dest, const void *src, size_t n); + /*! Set all n bytes of ptr to ch */ + void *(*mu_memset) (void *ref, void *ptr, int ch, size_t n); +} sah_Mem_Util; + +/*! + * Secure Partition information + * + * This holds the context to a single secure partition owned by the user. It + * is only available in the kernel version of the User Context Object. + */ +typedef struct fsl_shw_spo_t { + uint32_t user_base; /*!< Base address (user virtual) */ + void *kernel_base; /*!< Base address (kernel virtual) */ + struct fsl_shw_spo_t *next; /*!< Pointer to the next partition + owned by the user. NULL if this + is the last partition. */ +} fsl_shw_spo_t; + +/* REQ-S2LRD-PINTFC-COA-UCO-001 */ +/*! + * User Context Object + */ +typedef struct fsl_shw_uco_t { + int sahara_openfd; /*!< this should be kernel-only?? */ + sah_Mem_Util *mem_util; /*!< Memory utility fns */ + uint32_t user_ref; /*!< User's reference */ + void (*callback) (struct fsl_shw_uco_t * uco); /*!< User's callback fn */ + uint32_t flags; /*!< from fsl_shw_user_ctx_flags_t */ + unsigned pool_size; /*!< maximum size of user pool */ +#ifdef __KERNEL__ + sah_Queue result_pool; /*!< where non-blocking results go */ + os_process_handle_t process; /*!< remember for signalling User mode */ + fsl_shw_spo_t *partition; /*!< chain of secure partitions owned by + the user */ +#else + struct fsl_shw_uco_t *next; /*!< To allow user-mode chaining of contexts, + for signalling. */ +#endif +} fsl_shw_uco_t; + +/* REQ-S2LRD-PINTFC-API-GEN-006 ?? */ +/*! + * Result object + */ +typedef struct fsl_shw_result_t { + uint32_t user_ref; + fsl_shw_return_t code; + uint32_t detail1; + uint32_t detail2; + sah_Head_Desc *user_desc; +} fsl_shw_result_t; + +/*! + * Keystore Object + */ +typedef struct fsl_shw_kso_t { +#ifdef __KERNEL__ + os_lock_t lock; /*!< Pointer to lock that controls access to + the keystore. */ +#endif + void *user_data; /*!< Pointer to user structure that handles + the internals of the keystore. */ + fsl_shw_return_t(*data_init) (fsl_shw_uco_t * user_ctx, + void **user_data); + void (*data_cleanup) (fsl_shw_uco_t * user_ctx, void **user_data); + fsl_shw_return_t(*slot_verify_access) (void *user_data, + uint64_t owner_id, + uint32_t slot); + fsl_shw_return_t(*slot_alloc) (void *user_data, uint32_t size_bytes, + uint64_t owner_id, uint32_t * slot); + fsl_shw_return_t(*slot_dealloc) (void *user_data, uint64_t owner_id, + uint32_t slot); + void *(*slot_get_address) (void *user_data, uint32_t slot); + uint32_t(*slot_get_base) (void *user_data, uint32_t slot); + uint32_t(*slot_get_offset) (void *user_data, uint32_t slot); + uint32_t(*slot_get_slot_size) (void *user_data, uint32_t slot); +} fsl_shw_kso_t; + +/* REQ-S2LRD-PINTFC-COA-SKO-001 */ +/*! + * Secret Key Context Object + */ +typedef struct fsl_shw_sko_t { + uint32_t flags; + fsl_shw_key_alg_t algorithm; + key_userid_t userid; + uint32_t handle; + uint16_t key_length; + uint8_t key[64]; + struct fsl_shw_kso_t *keystore; /*!< If present, key is in keystore */ +} fsl_shw_sko_t; + +/* REQ-S2LRD-PINTFC-COA-CO-001 */ +/*! + * @brief Platform Capability Object + */ +typedef struct fsl_shw_pco_t { /* Consider turning these constants into symbols */ + int api_major; + int api_minor; + int driver_major; + int driver_minor; + fsl_shw_key_alg_t sym_algorithms[4]; + fsl_shw_sym_mode_t sym_modes[4]; + fsl_shw_hash_alg_t hash_algorithms[4]; + uint8_t sym_support[5][4]; /* indexed by key alg then mode */ + + int scc_driver_major; + int scc_driver_minor; + int scm_version; /*!< Version from SCM Configuration register */ + int smn_version; /*!< Version from SMN Status register */ + int block_size_bytes; /*!< Number of bytes per block of RAM; also + block size of the crypto algorithm. */ + union { + struct { + int black_ram_size_blocks; /*!< Number of blocks of Black RAM */ + int red_ram_size_blocks; /*!< Number of blocks of Red RAM */ + } scc_info; + struct { + int partition_size_bytes; /*!< Number of bytes in each partition */ + int partition_count; /*!< Number of partitions on this platform */ + } scc2_info; + }; +} fsl_shw_pco_t; + +/* REQ-S2LRD-PINTFC-COA-HCO-001 */ +/*! + * Hash Context Object + */ +typedef struct fsl_shw_hco_t { /* fsl_shw_hash_context_object */ + fsl_shw_hash_alg_t algorithm; + uint32_t flags; + uint8_t digest_length; /* in bytes */ + uint8_t context_length; /* in bytes */ + uint8_t context_register_length; /* in bytes */ + uint32_t context[9]; /* largest digest + msg size */ +} fsl_shw_hco_t; + +/*! + * HMAC Context Object + */ +typedef struct fsl_shw_hmco_t { /* fsl_shw_hmac_context_object */ + fsl_shw_hash_alg_t algorithm; + uint32_t flags; + uint8_t digest_length; /*!< in bytes */ + uint8_t context_length; /*!< in bytes */ + uint8_t context_register_length; /*!< in bytes */ + uint32_t ongoing_context[9]; /*!< largest digest + msg + size */ + uint32_t inner_precompute[9]; /*!< largest digest + msg + size */ + uint32_t outer_precompute[9]; /*!< largest digest + msg + size */ +} fsl_shw_hmco_t; + +/* REQ-S2LRD-PINTFC-COA-SCCO-001 */ +/*! + * Symmetric Crypto Context Object Context Object + */ +typedef struct fsl_shw_scco_t { + uint32_t flags; + unsigned block_size_bytes; /* double duty block&ctx size */ + fsl_shw_sym_mode_t mode; + /* Could put modulus plus 16-octet context in union with arc4 + sbox+ptrs... */ + fsl_shw_ctr_mod_t modulus_exp; + uint8_t context[259]; +} fsl_shw_scco_t; + +/*! + * Authenticate-Cipher Context Object + + * An object for controlling the function of, and holding information about, + * data for the authenticate-cipher functions, #fsl_shw_gen_encrypt() and + * #fsl_shw_auth_decrypt(). + */ +typedef struct fsl_shw_acco_t { + uint32_t flags; /*!< See #fsl_shw_auth_ctx_flags_t for + meanings */ + fsl_shw_acc_mode_t mode; /*!< CCM only */ + uint8_t mac_length; /*!< User's value for length */ + unsigned q_length; /*!< NIST parameter - */ + fsl_shw_scco_t cipher_ctx_info; /*!< For running + encrypt/decrypt. */ + union { + fsl_shw_scco_t CCM_ctx_info; /*!< For running the CBC in + AES-CCM. */ + fsl_shw_hco_t hash_ctx_info; /*!< For running the hash */ + } auth_info; /*!< "auth" info struct */ + uint8_t unencrypted_mac[16]; /*!< max block size... */ +} fsl_shw_acco_t; + +/*! + * Used by Sahara API to retrieve completed non-blocking results. + */ +typedef struct sah_results { + unsigned requested; /*!< number of results requested */ + unsigned *actual; /*!< number of results obtained */ + fsl_shw_result_t *results; /*!< pointer to memory to hold results */ +} sah_results; + +/*! + * @typedef scc_partition_status_t + */ +/*! Partition status information. */ +typedef enum fsl_shw_partition_status_t { + FSL_PART_S_UNUSABLE, /*!< Partition not implemented */ + FSL_PART_S_UNAVAILABLE, /*!< Partition owned by other host */ + FSL_PART_S_AVAILABLE, /*!< Partition available */ + FSL_PART_S_ALLOCATED, /*!< Partition owned by host but not engaged + */ + FSL_PART_S_ENGAGED, /*!< Partition owned by host and engaged */ +} fsl_shw_partition_status_t; + +/****************************************************************************** + * Access Macros for Objects + *****************************************************************************/ +/*! + * Get FSL SHW API version + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] pcmajor A pointer to where the major version + * of the API is to be stored. + * @param[out] pcminor A pointer to where the minor version + * of the API is to be stored. + */ +#define fsl_shw_pco_get_version(pcobject, pcmajor, pcminor) \ +{ \ + *(pcmajor) = (pcobject)->api_major; \ + *(pcminor) = (pcobject)->api_minor; \ +} + +/*! + * Get underlying driver version. + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] pcmajor A pointer to where the major version + * of the driver is to be stored. + * @param[out] pcminor A pointer to where the minor version + * of the driver is to be stored. + */ +#define fsl_shw_pco_get_driver_version(pcobject, pcmajor, pcminor) \ +{ \ + *(pcmajor) = (pcobject)->driver_major; \ + *(pcminor) = (pcobject)->driver_minor; \ +} + +/*! + * Get list of symmetric algorithms supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] pcalgorithms A pointer to where to store the location of + * the list of algorithms. + * @param[out] pcacount A pointer to where to store the number of + * algorithms in the list at @a algorithms. + */ +#define fsl_shw_pco_get_sym_algorithms(pcobject, pcalgorithms, pcacount) \ +{ \ + *(pcalgorithms) = (pcobject)->sym_algorithms; \ + *(pcacount) = sizeof((pcobject)->sym_algorithms)/4; \ +} + +/*! + * Get list of symmetric modes supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] gsmodes A pointer to where to store the location of + * the list of modes. + * @param[out] gsacount A pointer to where to store the number of + * algorithms in the list at @a modes. + */ +#define fsl_shw_pco_get_sym_modes(pcobject, gsmodes, gsacount) \ +{ \ + *(gsmodes) = (pcobject)->sym_modes; \ + *(gsacount) = sizeof((pcobject)->sym_modes)/4; \ +} + +/*! + * Get list of hash algorithms supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] gsalgorithms A pointer which will be set to the list of + * algorithms. + * @param[out] gsacount The number of algorithms in the list at @a + * algorithms. + */ +#define fsl_shw_pco_get_hash_algorithms(pcobject, gsalgorithms, gsacount) \ +{ \ + *(gsalgorithms) = (pcobject)->hash_algorithms; \ + *(gsacount) = sizeof((pcobject)->hash_algorithms)/4; \ +} + +/*! + * Determine whether the combination of a given symmetric algorithm and a given + * mode is supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param pcalg A Symmetric Cipher algorithm. + * @param pcmode A Symmetric Cipher mode. + * + * @return 0 if combination is not supported, non-zero if supported. + */ +#define fsl_shw_pco_check_sym_supported(pcobject, pcalg, pcmode) \ + ((pcobject)->sym_support[pcalg][pcmode]) + +/*! + * Determine whether a given Encryption-Authentication mode is supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param pcmode The Authentication mode. + * + * @return 0 if mode is not supported, non-zero if supported. + */ +#define fsl_shw_pco_check_auth_supported(pcobject, pcmode) \ + ((pcmode == FSL_ACC_MODE_CCM) ? 1 : 0) + +/*! + * Determine whether Black Keys (key establishment / wrapping) is supported. + * + * @param pcobject The Platform Capababilities Object to query. + * + * @return 0 if wrapping is not supported, non-zero if supported. + */ +#define fsl_shw_pco_check_black_key_supported(pcobject) \ + 1 + +/*! + * Determine whether Programmed Key features are available + * + * @param pc_info The Platform Capabilities Object to query. + * + * @return 1 if Programmed Key features are available, otherwise zero. + */ +#define fsl_shw_pco_check_pk_supported(pcobject) \ + 0 + +/*! + * Determine whether Software Key features are available + * + * @param pc_info The Platform Capabilities Object to query. + * + * @return 1 if Software key features are available, otherwise zero. + */ +#define fsl_shw_pco_check_sw_keys_supported(pcobject) \ + 0 + +/*! + * Get FSL SHW SCC driver version + * + * @param pcobject The Platform Capabilities Object to query. + * @param[out] pcmajor A pointer to where the major version + * of the SCC driver is to be stored. + * @param[out] pcminor A pointer to where the minor version + * of the SCC driver is to be stored. + */ +#define fsl_shw_pco_get_scc_driver_version(pcobject, pcmajor, pcminor) \ +{ \ + *(pcmajor) = (pcobject)->scc_driver_major; \ + *(pcminor) = (pcobject)->scc_driver_minor; \ +} + +/*! + * Get SCM hardware version + * + * @param pcobject The Platform Capabilities Object to query. + * @return The SCM hardware version + */ +#define fsl_shw_pco_get_scm_version(pcobject) \ + ((pcobject)->scm_version) + +/*! + * Get SMN hardware version + * + * @param pcobject The Platform Capabilities Object to query. + * @return The SMN hardware version + */ +#define fsl_shw_pco_get_smn_version(pcobject) \ + ((pcobject)->smn_version) + +/*! + * Get the size of an SCM block, in bytes + * + * @param pcobject The Platform Capabilities Object to query. + * @return The size of an SCM block, in bytes. + */ +#define fsl_shw_pco_get_scm_block_size(pcobject) \ + ((pcobject)->block_size_bytes) + +/*! + * Get size of Black and Red RAM memory + * + * @param pcobject The Platform Capabilities Object to query. + * @param[out] black_size A pointer to where the size of the Black RAM, in + * blocks, is to be placed. + * @param[out] red_size A pointer to where the size of the Red RAM, in + * blocks, is to be placed. + */ +#define fsl_shw_pco_get_smn_size(pcobject, black_size, red_size) \ +{ \ + if ((pcobject)->scm_version == 1) { \ + *(black_size) = (pcobject)->scc_info.black_ram_size_blocks; \ + *(red_size) = (pcobject)->scc_info.red_ram_size_blocks; \ + } else { \ + *(black_size) = 0; \ + *(red_size) = 0; \ + } \ +} + +/*! + * Determine whether Secure Partitions are supported + * + * @param pcobject The Platform Capabilities Object to query. + * + * @return 0 if secure partitions are not supported, non-zero if supported. + */ +#define fsl_shw_pco_check_spo_supported(pcobject) \ + ((pcobject)->scm_version == 2) + +/*! + * Get the size of a Secure Partitions + * + * @param pcobject The Platform Capabilities Object to query. + * + * @return Partition size, in bytes. 0 if Secure Partitions not supported. + */ +#define fsl_shw_pco_get_spo_size_bytes(pcobject) \ + (((pcobject)->scm_version == 2) ? \ + ((pcobject)->scc2_info.partition_size_bytes) : 0 ) + +/*! + * Get the number of Secure Partitions on this platform + * + * @param pcobject The Platform Capabilities Object to query. + * + * @return Number of partitions. 0 if Secure Paritions not supported. Note + * that this returns the total number of partitions, not all may be + * available to the user. + */ +#define fsl_shw_pco_get_spo_count(pcobject) \ + (((pcobject)->scm_version == 2) ? \ + ((pcobject)->scc2_info.partition_count) : 0 ) + +/*! + * Initialize a User Context Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the User Context Object to initial values, and set the size + * of the results pool. The mode will be set to a default of + * #FSL_UCO_BLOCKING_MODE. + * + * When using non-blocking operations, this sets the maximum number of + * operations which can be outstanding. This number includes the counts of + * operations waiting to start, operation(s) being performed, and results which + * have not been retrieved. + * + * Changes to this value are ignored once user registration has completed. It + * should be set to 1 if only blocking operations will ever be performed. + * + * @param ucontext The User Context object to operate on. + * @param usize The maximum number of operations which can be + * outstanding. + */ +#ifdef __KERNEL__ +#define fsl_shw_uco_init(ucontext, usize) \ +{ \ + (ucontext)->pool_size = usize; \ + (ucontext)->flags = FSL_UCO_BLOCKING_MODE; \ + (ucontext)->sahara_openfd = -1; \ + (ucontext)->mem_util = NULL; \ + (ucontext)->partition = NULL; \ + (ucontext)->callback = NULL; \ +} +#else +#define fsl_shw_uco_init(ucontext, usize) \ +{ \ + (ucontext)->pool_size = usize; \ + (ucontext)->flags = FSL_UCO_BLOCKING_MODE; \ + (ucontext)->sahara_openfd = -1; \ + (ucontext)->mem_util = NULL; \ + (ucontext)->callback = NULL; \ +} +#endif + +/*! + * Set the User Reference for the User Context. + * + * @param ucontext The User Context object to operate on. + * @param uref A value which will be passed back with a result. + */ +#define fsl_shw_uco_set_reference(ucontext, uref) \ + (ucontext)->user_ref = uref + +/*! + * Set the User Reference for the User Context. + * + * @param ucontext The User Context object to operate on. + * @param ucallback The function the API will invoke when an operation + * completes. + */ +#define fsl_shw_uco_set_callback(ucontext, ucallback) \ + (ucontext)->callback = ucallback + +/*! + * Set flags in the User Context. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param ucontext The User Context object to operate on. + * @param uflags ORed values from #fsl_shw_user_ctx_flags_t. + */ +#define fsl_shw_uco_set_flags(ucontext, uflags) \ + (ucontext)->flags |= (uflags) + +/*! + * Clear flags in the User Context. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param ucontext The User Context object to operate on. + * @param uflags ORed values from #fsl_shw_user_ctx_flags_t. + */ +#define fsl_shw_uco_clear_flags(ucontext, uflags) \ + (ucontext)->flags &= ~(uflags) + +/*! + * Retrieve the reference value from a Result Object. + * + * @param robject The result object to query. + * + * @return The reference associated with the request. + */ +#define fsl_shw_ro_get_reference(robject) \ + (robject)->user_ref + +/*! + * Retrieve the status code from a Result Object. + * + * @param robject The result object to query. + * + * @return The status of the request. + */ +#define fsl_shw_ro_get_status(robject) \ + (robject)->code + +/*! + * Initialize a Secret Key Object. + * + * This function must be called before performing any other operation with + * the Object. + * + * @param skobject The Secret Key Object to be initialized. + * @param skalgorithm DES, AES, etc. + * + */ +#define fsl_shw_sko_init(skobject,skalgorithm) \ +{ \ + (skobject)->algorithm = skalgorithm; \ + (skobject)->flags = 0; \ + (skobject)->keystore = NULL; \ +} + +/*! + * Initialize a Secret Key Object to use a Platform Key register. + * + * This function must be called before performing any other operation with + * the Object. INVALID on this platform. + * + * @param skobject The Secret Key Object to be initialized. + * @param skalgorithm DES, AES, etc. + * @param skhwkey one of the fsl_shw_pf_key_t values. + * + */ +#define fsl_shw_sko_init_pf_key(skobject,skalgorithm,skhwkey) \ +{ \ + (skobject)->algorithm = -1; \ + (skobject)->flags = -1; \ + (skobject)->keystore = NULL; \ +} + +/*! + * Store a cleartext key in the key object. + * + * This has the side effect of setting the #FSL_SKO_KEY_PRESENT flag and + * resetting the #FSL_SKO_KEY_ESTABLISHED flag. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skkey A pointer to the beginning of the key. + * @param skkeylen The length, in octets, of the key. The value should be + * appropriate to the key size supported by the algorithm. + * 64 octets is the absolute maximum value allowed for this + * call. + */ +#define fsl_shw_sko_set_key(skobject, skkey, skkeylen) \ +{ \ + (skobject)->key_length = skkeylen; \ + copy_bytes((skobject)->key, skkey, skkeylen); \ + (skobject)->flags |= FSL_SKO_KEY_PRESENT; \ + (skobject)->flags &= ~FSL_SKO_KEY_ESTABLISHED; \ +} + +/*! + * Set a size for the key. + * + * This function would normally be used when the user wants the key to be + * generated from a random source. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skkeylen The length, in octets, of the key. The value should be + * appropriate to the key size supported by the algorithm. + * 64 octets is the absolute maximum value allowed for this + * call. + */ +#define fsl_shw_sko_set_key_length(skobject, skkeylen) \ + (skobject)->key_length = skkeylen; + +/*! + * Set the User ID associated with the key. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skuserid The User ID to identify authorized users of the key. + */ +#define fsl_shw_sko_set_user_id(skobject, skuserid) \ + (skobject)->userid = (skuserid) + +/*! + * Establish a user Keystore to hold the key. + */ +#define fsl_shw_sko_set_keystore(skobject, user_keystore) \ + (skobject)->keystore = (user_keystore) + +/*! + * Set the establish key handle into a key object. + * + * The @a userid field will be used to validate the access to the unwrapped + * key. This feature is not available for all platforms, nor for all + * algorithms and modes. + * + * The #FSL_SKO_KEY_ESTABLISHED will be set (and the #FSL_SKO_KEY_PRESENT flag + * will be cleared). + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skuserid The User ID to verify this user is an authorized user of + * the key. + * @param skhandle A @a handle from #fsl_shw_sko_get_established_info. + */ +#define fsl_shw_sko_set_established_info(skobject, skuserid, skhandle) \ +{ \ + (skobject)->userid = (skuserid); \ + (skobject)->handle = (skhandle); \ + (skobject)->flags |= FSL_SKO_KEY_ESTABLISHED; \ + (skobject)->flags &= \ + ~(FSL_SKO_KEY_PRESENT); \ +} + +/*! + * Retrieve the established-key handle from a key object. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skhandle The location to store the @a handle of the unwrapped + * key. + */ +#define fsl_shw_sko_get_established_info(skobject, skhandle) \ + *(skhandle) = (skobject)->handle + +/*! + * Extract the algorithm from a key object. + * + * @param skobject The Key Object to be queried. + * @param[out] skalgorithm A pointer to the location to store the algorithm. + */ +#define fsl_shw_sko_get_algorithm(skobject, skalgorithm) \ + *(skalgorithm) = (skobject)->algorithm + +/*! + * Retrieve the cleartext key from a key object that is stored in a user + * keystore. + * + * @param skobject The Key Object to be queried. + * @param[out] skkey A pointer to the location to store the key. NULL + * if the key is not stored in a user keystore. + */ +#define fsl_shw_sko_get_key(skobject, skkey) \ +{ \ + fsl_shw_kso_t* keystore = (skobject)->keystore; \ + if (keystore != NULL) { \ + *(skkey) = keystore->slot_get_address(keystore->user_data, \ + (skobject)->handle); \ + } else { \ + *(skkey) = NULL; \ + } \ +} + +/*! + * Determine the size of a wrapped key based upon the cleartext key's length. + * + * This function can be used to calculate the number of octets that + * #fsl_shw_extract_key() will write into the location at @a covered_key. + * + * If zero is returned at @a length, this means that the key length in + * @a key_info is not supported. + * + * @param wkeyinfo Information about a key to be wrapped. + * @param wkeylen Location to store the length of a wrapped + * version of the key in @a key_info. + */ +#define fsl_shw_sko_calculate_wrapped_size(wkeyinfo, wkeylen) \ +{ \ + register fsl_shw_sko_t* kp = wkeyinfo; \ + register uint32_t kl = kp->key_length; \ + int key_blocks = (kl + 15) / 16; \ + int base_size = 35; /* ICV + T' + ALG + LEN + FLAGS */ \ + \ + *(wkeylen) = base_size + 16 * key_blocks; \ +} + +/*! + * Set some flags in the key object. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skflags (One or more) ORed members of #fsl_shw_key_flags_t which + * are to be set. + */ +#define fsl_shw_sko_set_flags(skobject, skflags) \ + (skobject)->flags |= (skflags) + +/*! + * Clear some flags in the key object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skflags (One or more) ORed members of #fsl_shw_key_flags_t + * which are to be reset. + */ +#define fsl_shw_sko_clear_flags(skobject, skflags) \ + (skobject)->flags &= ~(skflags) + +/*! + * Initialize a Hash Context Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the current message length and hash algorithm in the hash + * context object. + * + * @param hcobject The hash context to operate upon. + * @param hcalgorithm The hash algorithm to be used (#FSL_HASH_ALG_MD5, + * #FSL_HASH_ALG_SHA256, etc). + * + */ +#define fsl_shw_hco_init(hcobject, hcalgorithm) \ +{ \ + (hcobject)->algorithm = hcalgorithm; \ + (hcobject)->flags = 0; \ + switch (hcalgorithm) { \ + case FSL_HASH_ALG_MD5: \ + (hcobject)->digest_length = 16; \ + (hcobject)->context_length = 16; \ + (hcobject)->context_register_length = 24; \ + break; \ + case FSL_HASH_ALG_SHA1: \ + (hcobject)->digest_length = 20; \ + (hcobject)->context_length = 20; \ + (hcobject)->context_register_length = 24; \ + break; \ + case FSL_HASH_ALG_SHA224: \ + (hcobject)->digest_length = 28; \ + (hcobject)->context_length = 32; \ + (hcobject)->context_register_length = 36; \ + break; \ + case FSL_HASH_ALG_SHA256: \ + (hcobject)->digest_length = 32; \ + (hcobject)->context_length = 32; \ + (hcobject)->context_register_length = 36; \ + break; \ + default: \ + /* error ! */ \ + (hcobject)->digest_length = 1; \ + (hcobject)->context_length = 1; \ + (hcobject)->context_register_length = 1; \ + break; \ + } \ +} + +/*! + * Get the current hash value and message length from the hash context object. + * + * The algorithm must have already been specified. See #fsl_shw_hco_init(). + * + * @param hcobject The hash context to query. + * @param[out] hccontext Pointer to the location of @a length octets where to + * store a copy of the current value of the digest. + * @param hcclength Number of octets of hash value to copy. + * @param[out] hcmsglen Pointer to the location to store the number of octets + * already hashed. + */ +#define fsl_shw_hco_get_digest(hcobject, hccontext, hcclength, hcmsglen) \ +{ \ + copy_bytes(hccontext, (hcobject)->context, hcclength); \ + if ((hcobject)->algorithm == FSL_HASH_ALG_SHA224 \ + || (hcobject)->algorithm == FSL_HASH_ALG_SHA256) { \ + *(hcmsglen) = (hcobject)->context[8]; \ + } else { \ + *(hcmsglen) = (hcobject)->context[5]; \ + } \ +} + +/*! + * Get the hash algorithm from the hash context object. + * + * @param hcobject The hash context to query. + * @param[out] hcalgorithm Pointer to where the algorithm is to be stored. + */ +#define fsl_shw_hco_get_info(hcobject, hcalgorithm) \ +{ \ + *(hcalgorithm) = (hcobject)->algorithm; \ +} + +/*! + * Set the current hash value and message length in the hash context object. + * + * The algorithm must have already been specified. See #fsl_shw_hco_init(). + * + * @param hcobject The hash context to operate upon. + * @param hccontext Pointer to buffer of appropriate length to copy into + * the hash context object. + * @param hcmsglen The number of octets of the message which have + * already been hashed. + * + */ +#define fsl_shw_hco_set_digest(hcobject, hccontext, hcmsglen) \ +{ \ + copy_bytes((hcobject)->context, hccontext, (hcobject)->context_length); \ + if (((hcobject)->algorithm == FSL_HASH_ALG_SHA224) \ + || ((hcobject)->algorithm == FSL_HASH_ALG_SHA256)) { \ + (hcobject)->context[8] = hcmsglen; \ + } else { \ + (hcobject)->context[5] = hcmsglen; \ + } \ +} + +/*! + * Set flags in a Hash Context Object. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param hcobject The hash context to be operated on. + * @param hcflags The flags to be set in the context. These can be ORed + * members of #fsl_shw_hash_ctx_flags_t. + */ +#define fsl_shw_hco_set_flags(hcobject, hcflags) \ + (hcobject)->flags |= (hcflags) + +/*! + * Clear flags in a Hash Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param hcobject The hash context to be operated on. + * @param hcflags The flags to be reset in the context. These can be ORed + * members of #fsl_shw_hash_ctx_flags_t. + */ +#define fsl_shw_hco_clear_flags(hcobject, hcflags) \ + (hcobject)->flags &= ~(hcflags) + +/*! + * Initialize an HMAC Context Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the current message length and hash algorithm in the HMAC + * context object. + * + * @param hcobject The HMAC context to operate upon. + * @param hcalgorithm The hash algorithm to be used (#FSL_HASH_ALG_MD5, + * #FSL_HASH_ALG_SHA256, etc). + * + */ +#define fsl_shw_hmco_init(hcobject, hcalgorithm) \ + fsl_shw_hco_init(hcobject, hcalgorithm) + +/*! + * Set flags in an HMAC Context Object. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param hcobject The HMAC context to be operated on. + * @param hcflags The flags to be set in the context. These can be ORed + * members of #fsl_shw_hmac_ctx_flags_t. + */ +#define fsl_shw_hmco_set_flags(hcobject, hcflags) \ + (hcobject)->flags |= (hcflags) + +/*! + * Clear flags in an HMAC Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param hcobject The HMAC context to be operated on. + * @param hcflags The flags to be reset in the context. These can be ORed + * members of #fsl_shw_hmac_ctx_flags_t. + */ +#define fsl_shw_hmco_clear_flags(hcobject, hcflags) \ + (hcobject)->flags &= ~(hcflags) + +/*! + * Initialize a Symmetric Cipher Context Object. + * + * This function must be called before performing any other operation with the + * Object. This will set the @a mode and @a algorithm and initialize the + * Object. + * + * @param scobject The context object to operate on. + * @param scalg The cipher algorithm this context will be used with. + * @param scmode #FSL_SYM_MODE_CBC, #FSL_SYM_MODE_ECB, etc. + * + */ +#define fsl_shw_scco_init(scobject, scalg, scmode) \ +{ \ + register uint32_t bsb; /* block-size bytes */ \ + \ + switch (scalg) { \ + case FSL_KEY_ALG_AES: \ + bsb = 16; \ + break; \ + case FSL_KEY_ALG_DES: \ + /* fall through */ \ + case FSL_KEY_ALG_TDES: \ + bsb = 8; \ + break; \ + case FSL_KEY_ALG_ARC4: \ + bsb = 259; \ + break; \ + case FSL_KEY_ALG_HMAC: \ + bsb = 1; /* meaningless */ \ + break; \ + default: \ + bsb = 00; \ + } \ + (scobject)->block_size_bytes = bsb; \ + (scobject)->mode = scmode; \ + (scobject)->flags = 0; \ +} + +/*! + * Set the flags for a Symmetric Cipher Context. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param scobject The context object to operate on. + * @param scflags The flags to reset (one or more values from + * #fsl_shw_sym_ctx_flags_t ORed together). + * + */ +#define fsl_shw_scco_set_flags(scobject, scflags) \ + (scobject)->flags |= (scflags) + +/*! + * Clear some flags in a Symmetric Cipher Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param scobject The context object to operate on. + * @param scflags The flags to reset (one or more values from + * #fsl_shw_sym_ctx_flags_t ORed together). + * + */ +#define fsl_shw_scco_clear_flags(scobject, scflags) \ + (scobject)->flags &= ~(scflags) + +/*! + * Set the Context (IV) for a Symmetric Cipher Context. + * + * This is to set the context/IV for #FSL_SYM_MODE_CBC mode, or to set the + * context (the S-Box and pointers) for ARC4. The full context size will + * be copied. + * + * @param scobject The context object to operate on. + * @param sccontext A pointer to the buffer which contains the context. + * + */ +#define fsl_shw_scco_set_context(scobject, sccontext) \ + copy_bytes((scobject)->context, sccontext, \ + (scobject)->block_size_bytes) + +/*! + * Get the Context for a Symmetric Cipher Context. + * + * This is to retrieve the context/IV for #FSL_SYM_MODE_CBC mode, or to + * retrieve context (the S-Box and pointers) for ARC4. The full context + * will be copied. + * + * @param scobject The context object to operate on. + * @param[out] sccontext Pointer to location where context will be stored. + */ +#define fsl_shw_scco_get_context(scobject, sccontext) \ + copy_bytes(sccontext, (scobject)->context, (scobject)->block_size_bytes) + +/*! + * Set the Counter Value for a Symmetric Cipher Context. + * + * This will set the Counter Value for CTR mode. + * + * @param scobject The context object to operate on. + * @param sccounter The starting counter value. The number of octets. + * copied will be the block size for the algorithm. + * @param scmodulus The modulus for controlling the incrementing of the + * counter. + * + */ +#define fsl_shw_scco_set_counter_info(scobject, sccounter, scmodulus) \ + { \ + if ((sccounter) != NULL) { \ + copy_bytes((scobject)->context, sccounter, \ + (scobject)->block_size_bytes); \ + } \ + (scobject)->modulus_exp = scmodulus; \ + } + +/*! + * Get the Counter Value for a Symmetric Cipher Context. + * + * This will retrieve the Counter Value is for CTR mode. + * + * @param scobject The context object to query. + * @param[out] sccounter Pointer to location to store the current counter + * value. The number of octets copied will be the + * block size for the algorithm. + * @param[out] scmodulus Pointer to location to store the modulus. + * + */ +#define fsl_shw_scco_get_counter_info(scobject, sccounter, scmodulus) \ + { \ + if ((sccounter) != NULL) { \ + copy_bytes(sccounter, (scobject)->context, \ + (scobject)->block_size_bytes); \ + } \ + if ((scmodulus) != NULL) { \ + *(scmodulus) = (scobject)->modulus_exp; \ + } \ + } + +/*! + * Initialize a Authentication-Cipher Context. + * + * @param acobject Pointer to object to operate on. + * @param acmode The mode for this object (only #FSL_ACC_MODE_CCM + * supported). + */ +#define fsl_shw_acco_init(acobject, acmode) \ + { \ + (acobject)->flags = 0; \ + (acobject)->mode = (acmode); \ + } + +/*! + * Set the flags for a Authentication-Cipher Context. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param acobject Pointer to object to operate on. + * @param acflags The flags to set (one or more from + * #fsl_shw_auth_ctx_flags_t ORed together). + * + */ +#define fsl_shw_acco_set_flags(acobject, acflags) \ + (acobject)->flags |= (acflags) + +/*! + * Clear some flags in a Authentication-Cipher Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param acobject Pointer to object to operate on. + * @param acflags The flags to reset (one or more from + * #fsl_shw_auth_ctx_flags_t ORed together). + * + */ +#define fsl_shw_acco_clear_flags(acobject, acflags) \ + (acobject)->flags &= ~(acflags) + +/*! + * Set up the Authentication-Cipher Object for CCM mode. + * + * This will set the @a auth_object for CCM mode and save the @a ctr, + * and @a mac_length. This function can be called instead of + * #fsl_shw_acco_init(). + * + * The paramater @a ctr is Counter Block 0, (counter value 0), which is for the + * MAC. + * + * @param acobject Pointer to object to operate on. + * @param acalg Cipher algorithm. Only AES is supported. + * @param accounter The initial counter value. + * @param acmaclen The number of octets used for the MAC. Valid values are + * 4, 6, 8, 10, 12, 14, and 16. + */ +/* Do we need to stash the +1 value of the CTR somewhere? */ +#define fsl_shw_acco_set_ccm(acobject, acalg, accounter, acmaclen) \ +{ \ + (acobject)->flags = 0; \ + (acobject)->mode = FSL_ACC_MODE_CCM; \ + (acobject)->auth_info.CCM_ctx_info.block_size_bytes = 16; \ + (acobject)->cipher_ctx_info.block_size_bytes = 16; \ + (acobject)->mac_length = acmaclen; \ + fsl_shw_scco_set_counter_info(&(acobject)->cipher_ctx_info, accounter, \ + FSL_CTR_MOD_128); \ +} + +/*! + * Format the First Block (IV) & Initial Counter Value per NIST CCM. + * + * This function will also set the IV and CTR values per Appendix A of NIST + * Special Publication 800-38C (May 2004). It will also perform the + * #fsl_shw_acco_set_ccm() operation with information derived from this set of + * parameters. + * + * Note this function assumes the algorithm is AES. It initializes the + * @a auth_object by setting the mode to #FSL_ACC_MODE_CCM and setting the + * flags to be #FSL_ACCO_NIST_CCM. + * + * @param acobject Pointer to object to operate on. + * @param act The number of octets used for the MAC. Valid values are + * 4, 6, 8, 10, 12, 14, and 16. + * @param acad Number of octets of Associated Data (may be zero). + * @param acq A value for the size of the length of @a q field. Valid + * values are 1-8. + * @param acN The Nonce (packet number or other changing value). Must + * be (15 - @a q_length) octets long. + * @param acQ The value of Q (size of the payload in octets). + * + */ +/* Do we need to stash the +1 value of the CTR somewhere? */ +#define fsl_shw_ccm_nist_format_ctr_and_iv(acobject, act, acad, acq, acN, acQ)\ + { \ + uint64_t Q = acQ; \ + uint8_t bflag = ((acad)?0x40:0) | ((((act)-2)/2)<<3) | ((acq)-1); \ + unsigned i; \ + uint8_t* qptr = (acobject)->auth_info.CCM_ctx_info.context + 15; \ + (acobject)->auth_info.CCM_ctx_info.block_size_bytes = 16; \ + (acobject)->cipher_ctx_info.block_size_bytes = 16; \ + (acobject)->mode = FSL_ACC_MODE_CCM; \ + (acobject)->flags = FSL_ACCO_NIST_CCM; \ + \ + /* Store away the MAC length (after calculating actual value */ \ + (acobject)->mac_length = (act); \ + /* Set Flag field in Block 0 */ \ + *((acobject)->auth_info.CCM_ctx_info.context) = bflag; \ + /* Set Nonce field in Block 0 */ \ + copy_bytes((acobject)->auth_info.CCM_ctx_info.context+1, acN, \ + 15-(acq)); \ + /* Set Flag field in ctr */ \ + *((acobject)->cipher_ctx_info.context) = (acq)-1; \ + /* Update the Q (payload length) field of Block0 */ \ + (acobject)->q_length = acq; \ + for (i = 0; i < (acq); i++) { \ + *qptr-- = Q & 0xFF; \ + Q >>= 8; \ + } \ + /* Set the Nonce field of the ctr */ \ + copy_bytes((acobject)->cipher_ctx_info.context+1, acN, 15-(acq)); \ + /* Clear the block counter field of the ctr */ \ + memset((acobject)->cipher_ctx_info.context+16-(acq), 0, (acq)+1); \ + } + +/*! + * Update the First Block (IV) & Initial Counter Value per NIST CCM. + * + * This function will set the IV and CTR values per Appendix A of NIST Special + * Publication 800-38C (May 2004). + * + * Note this function assumes that #fsl_shw_ccm_nist_format_ctr_and_iv() has + * previously been called on the @a auth_object. + * + * @param acobject Pointer to object to operate on. + * @param acN The Nonce (packet number or other changing value). Must + * be (15 - @a q_length) octets long. + * @param acQ The value of Q (size of the payload in octets). + * + */ +/* Do we need to stash the +1 value of the CTR somewhere? */ +#define fsl_shw_ccm_nist_update_ctr_and_iv(acobject, acN, acQ) \ + { \ + uint64_t Q = acQ; \ + unsigned i; \ + uint8_t* qptr = (acobject)->auth_info.CCM_ctx_info.context + 15; \ + \ + /* Update the Nonce field field of Block0 */ \ + copy_bytes((acobject)->auth_info.CCM_ctx_info.context+1, acN, \ + 15 - (acobject)->q_length); \ + /* Update the Q (payload length) field of Block0 */ \ + for (i = 0; i < (acobject)->q_length; i++) { \ + *qptr-- = Q & 0xFF; \ + Q >>= 8; \ + } \ + /* Update the Nonce field of the ctr */ \ + copy_bytes((acobject)->cipher_ctx_info.context+1, acN, \ + 15 - (acobject)->q_length); \ + } + +/****************************************************************************** + * Library functions + *****************************************************************************/ +/* REQ-S2LRD-PINTFC-API-GEN-003 */ +extern fsl_shw_pco_t *fsl_shw_get_capabilities(fsl_shw_uco_t * user_ctx); + +/* REQ-S2LRD-PINTFC-API-GEN-004 */ +extern fsl_shw_return_t fsl_shw_register_user(fsl_shw_uco_t * user_ctx); + +/* REQ-S2LRD-PINTFC-API-GEN-005 */ +extern fsl_shw_return_t fsl_shw_deregister_user(fsl_shw_uco_t * user_ctx); + +/* REQ-S2LRD-PINTFC-API-GEN-006 */ +extern fsl_shw_return_t fsl_shw_get_results(fsl_shw_uco_t * user_ctx, + unsigned result_size, + fsl_shw_result_t results[], + unsigned *result_count); + +extern fsl_shw_return_t fsl_shw_establish_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_key_wrap_t establish_type, + const uint8_t * key); + +extern fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + uint8_t * covered_key); + +extern fsl_shw_return_t fsl_shw_release_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info); + +extern void *fsl_shw_smalloc(fsl_shw_uco_t * user_ctx, + uint32_t size, + const uint8_t * UMID, uint32_t permissions); + +extern fsl_shw_return_t fsl_shw_sfree(fsl_shw_uco_t * user_ctx, void *address); + +extern fsl_shw_return_t fsl_shw_sstatus(fsl_shw_uco_t * user_ctx, + void *address, + fsl_shw_partition_status_t * status); + +extern fsl_shw_return_t fsl_shw_diminish_perms(fsl_shw_uco_t * user_ctx, + void *address, + uint32_t permissions); + +extern fsl_shw_return_t do_scc_engage_partition(fsl_shw_uco_t * user_ctx, + void *address, + const uint8_t * UMID, + uint32_t permissions); + +extern fsl_shw_return_t do_system_keystore_slot_alloc(fsl_shw_uco_t * user_ctx, + uint32_t key_lenth, + uint64_t ownerid, + uint32_t * slot); + +extern fsl_shw_return_t do_system_keystore_slot_dealloc(fsl_shw_uco_t * + user_ctx, + uint64_t ownerid, + uint32_t slot); + +extern fsl_shw_return_t do_system_keystore_slot_load(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + const uint8_t * key, + uint32_t key_length); + +extern fsl_shw_return_t do_system_keystore_slot_read(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + const uint8_t * key); + +extern fsl_shw_return_t do_system_keystore_slot_encrypt(fsl_shw_uco_t * + user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + uint8_t * black_data); + +extern fsl_shw_return_t do_system_keystore_slot_decrypt(fsl_shw_uco_t * + user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + const uint8_t * + black_data); + +extern fsl_shw_return_t +do_scc_encrypt_region(fsl_shw_uco_t * user_ctx, + void *partition_base, uint32_t offset_bytes, + uint32_t byte_count, uint8_t * black_data, + uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode); + +extern fsl_shw_return_t +do_scc_decrypt_region(fsl_shw_uco_t * user_ctx, + void *partition_base, uint32_t offset_bytes, + uint32_t byte_count, const uint8_t * black_data, + uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode); + +extern fsl_shw_return_t +system_keystore_get_slot_info(uint64_t owner_id, uint32_t slot, + uint32_t * address, uint32_t * slot_size_bytes); + +/* REQ-S2LRD-PINTFC-API-BASIC-SYM-002 */ +/* PINTFC-API-BASIC-SYM-ARC4-001 */ +/* PINTFC-API-BASIC-SYM-ARC4-002 */ +extern fsl_shw_return_t fsl_shw_symmetric_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * pt, + uint8_t * ct); + +/* PINTFC-API-BASIC-SYM-002 */ +/* PINTFC-API-BASIC-SYM-ARC4-001 */ +/* PINTFC-API-BASIC-SYM-ARC4-002 */ +extern fsl_shw_return_t fsl_shw_symmetric_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * ct, + uint8_t * pt); + +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-005 */ +extern fsl_shw_return_t fsl_shw_hash(fsl_shw_uco_t * user_ctx, + fsl_shw_hco_t * hash_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len); + +/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-001 */ +extern fsl_shw_return_t fsl_shw_hmac_precompute(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx); + +/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-002 */ +extern fsl_shw_return_t fsl_shw_hmac(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len); + +/* REQ-S2LRD-PINTFC-API-BASIC-RNG-002 */ +extern fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data); + +extern fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data); + +extern fsl_shw_return_t fsl_shw_gen_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + fsl_shw_sko_t * cipher_key_info, + fsl_shw_sko_t * auth_key_info, + uint32_t auth_data_length, + const uint8_t * auth_data, + uint32_t payload_length, + const uint8_t * payload, + uint8_t * ct, uint8_t * auth_value); + +extern fsl_shw_return_t fsl_shw_auth_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + fsl_shw_sko_t * cipher_key_info, + fsl_shw_sko_t * auth_key_info, + uint32_t auth_data_length, + const uint8_t * auth_data, + uint32_t payload_length, + const uint8_t * ct, + const uint8_t * auth_value, + uint8_t * payload); + +extern fsl_shw_return_t fsl_shw_read_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + uint8_t * key); + +static inline fsl_shw_return_t fsl_shw_gen_random_pf_key(fsl_shw_uco_t * + user_ctx) +{ + (void)user_ctx; + + return FSL_RETURN_NO_RESOURCE_S; +} + +static inline fsl_shw_return_t fsl_shw_read_tamper_event(fsl_shw_uco_t * + user_ctx, + fsl_shw_tamper_t * + tamperp, + uint64_t * timestampp) +{ + (void)user_ctx; + (void)tamperp; + (void)timestampp; + + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t sah_Append_Desc(const sah_Mem_Util * mu, + sah_Head_Desc ** desc_head, + const uint32_t header, + sah_Link * link1, sah_Link * link2); + +/* Utility Function leftover from sahara1 API */ +void sah_Descriptor_Chain_Destroy(const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/* Utility Function leftover from sahara1 API */ +fsl_shw_return_t sah_Descriptor_Chain_Execute(sah_Head_Desc * desc_chain, + fsl_shw_uco_t * user_ctx); + +fsl_shw_return_t sah_Append_Link(const sah_Mem_Util * mu, + sah_Link * link, + uint8_t * p, + const size_t length, + const sah_Link_Flags flags); + +fsl_shw_return_t sah_Create_Link(const sah_Mem_Util * mu, + sah_Link ** link, + uint8_t * p, + const size_t length, + const sah_Link_Flags flags); + +fsl_shw_return_t sah_Create_Key_Link(const sah_Mem_Util * mu, + sah_Link ** link, + fsl_shw_sko_t * key_info); + +void sah_Destroy_Link(const sah_Mem_Util * mu, sah_Link * link); + +void sah_Postprocess_Results(fsl_shw_uco_t * user_ctx, + sah_results * result_info); + +#endif /* SAHARA2_API_H */ + diff -urN linux-2.6.26/drivers/mxc/security/sahara2/include/sahara2_kernel.h linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sahara2_kernel.h --- linux-2.6.26/drivers/mxc/security/sahara2/include/sahara2_kernel.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sahara2_kernel.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,49 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#define DRIVER_NAME sahara2 + +#define SAHARA_MAJOR_NODE 78 + +#include "portable_os.h" + +#include "platform_abstractions.h" + +/* Forward-declare prototypes using signature macros */ + +OS_DEV_ISR_DCL(sahara2_isr); + +OS_DEV_INIT_DCL(sahara2_init); + +OS_DEV_SHUTDOWN_DCL(sahara2_shutdown); + +OS_DEV_OPEN_DCL(sahara2_open); + +OS_DEV_CLOSE_DCL(sahara2_release); + +OS_DEV_IOCTL_DCL(sahara2_ioctl); + +struct sahara2_kernel_user { + void *command_ring[32]; +}; + +struct sahara2_sym_arg { + char *key; + unsigned key_len; +}; + +/*! These need to be added to Linux / OS abstractions */ +/* +module_init(OS_DEV_INIT_REF(sahara2_init)); +module_cleanup(OS_DEV_SHUTDOWN_REF(sahara2_shutdown)); +*/ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/include/sf_util.h linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sf_util.h --- linux-2.6.26/drivers/mxc/security/sahara2/include/sf_util.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/include/sf_util.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,466 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! +* @file sf_util.h +* +* @brief Header for Sahara Descriptor-chain building Functions +*/ +#ifndef SF_UTIL_H +#define SF_UTIL_H + +#include +#include + +/*! Header value for Sahara Descriptor 1 */ +#define SAH_HDR_SKHA_SET_MODE_IV_KEY 0x10880000 +/*! Header value for Sahara Descriptor 2 */ +#define SAH_HDR_SKHA_SET_MODE_ENC_DEC 0x108D0000 +/*! Header value for Sahara Descriptor 4 */ +#define SAH_HDR_SKHA_ENC_DEC 0x90850000 +/*! Header value for Sahara Descriptor 5 */ +#define SAH_HDR_SKHA_READ_CONTEXT_IV 0x10820000 +/*! Header value for Sahara Descriptor 6 */ +#define SAH_HDR_MDHA_SET_MODE_MD_KEY 0x20880000 +/*! Header value for Sahara Descriptor 8 */ +#define SAH_HDR_MDHA_SET_MODE_HASH 0x208D0000 +/*! Header value for Sahara Descriptor 10 */ +#define SAH_HDR_MDHA_HASH 0xA0850000 +/*! Header value for Sahara Descriptor 11 */ +#define SAH_HDR_MDHA_STORE_DIGEST 0x20820000 +/*! Header value for Sahara Descriptor 18 */ +#define SAH_HDR_RNG_GENERATE 0x308C0000 +/*! Header value for Sahara Descriptor 19 */ +#define SAH_HDR_PKHA_LD_N_E 0xC0800000 +/*! Header value for Sahara Descriptor 20 */ +#define SAH_HDR_PKHA_LD_A_EX_ST_B 0x408D0000 +/*! Header value for Sahara Descriptor 21 */ +#define SAH_HDR_PKHA_LD_N_EX_ST_B 0x408E0000 +/*! Header value for Sahara Descriptor 22 */ +#define SAH_HDR_PKHA_LD_A_B 0xC0830000 +/*! Header value for Sahara Descriptor 23 */ +#define SAH_HDR_PKHA_LD_A0_A1 0x40840000 +/*! Header value for Sahara Descriptor 24 */ +#define SAH_HDR_PKHA_LD_A2_A3 0xC0850000 +/*! Header value for Sahara Descriptor 25 */ +#define SAH_HDR_PKHA_LD_B0_B1 0xC0860000 +/*! Header value for Sahara Descriptor 26 */ +#define SAH_HDR_PKHA_LD_B2_B3 0x40870000 +/*! Header value for Sahara Descriptor 27 */ +#define SAH_HDR_PKHA_ST_A_B 0x40820000 +/*! Header value for Sahara Descriptor 28 */ +#define SAH_HDR_PKHA_ST_A0_A1 0x40880000 +/*! Header value for Sahara Descriptor 29 */ +#define SAH_HDR_PKHA_ST_A2_A3 0xC0890000 +/*! Header value for Sahara Descriptor 30 */ +#define SAH_HDR_PKHA_ST_B0_B1 0xC08A0000 +/*! Header value for Sahara Descriptor 31 */ +#define SAH_HDR_PKHA_ST_B2_B3 0x408B0000 +/*! Header value for Sahara Descriptor 32 */ +#define SAH_HDR_PKHA_EX_ST_B1 0xC08C0000 +/*! Header value for Sahara Descriptor 33 */ +#define SAH_HDR_ARC4_SET_MODE_SBOX 0x90890000 +/*! Header value for Sahara Descriptor 34 */ +#define SAH_HDR_ARC4_READ_SBOX 0x90860000 +/*! Header value for Sahara Descriptor 35 */ +#define SAH_HDR_ARC4_SET_MODE_KEY 0x90830000 +/*! Header value for Sahara Descriptor 36 */ +#define SAH_HDR_PKHA_LD_A3_B0 0x40810000 +/*! Header value for Sahara Descriptor 37 */ +#define SAH_HDR_PKHA_ST_B1_B2 0xC08F0000 +/*! Header value for Sahara Descriptor 38 */ +#define SAH_HDR_SKHA_CBC_ICV 0x10840000 +/*! Header value for Sahara Descriptor 39 */ +#define SAH_HDR_MDHA_ICV_CHECK 0xA08A0000 + +/*! Header bit indicating "Link-List optimization" */ +#define SAH_HDR_LLO 0x01000000 + +#define SAH_SF_DCLS \ + fsl_shw_return_t ret; \ + unsigned sf_executed = 0; \ + sah_Head_Desc* desc_chain = NULL; \ + uint32_t header + +#define SAH_SF_USER_CHECK() \ +do { \ + ret = sah_validate_uco(user_ctx); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} while (0) + +#define SAH_SF_EXECUTE() \ +do { \ + sf_executed = 1; \ + ret = sah_Descriptor_Chain_Execute(desc_chain, user_ctx); \ +} while (0) + +#define SAH_SF_DESC_CLEAN() \ +do { \ + if (!sf_executed || (user_ctx->flags & FSL_UCO_BLOCKING_MODE)) { \ + sah_Descriptor_Chain_Destroy(user_ctx->mem_util, &desc_chain); \ + } \ + (void) header; \ +} while (0) + +/*! Add Descriptor with two inputs */ +#define DESC_IN_IN(hdr, len1, ptr1, len2, ptr2) \ +{ \ + ret = sah_add_two_in_desc(hdr, ptr1, len1, ptr2, len2, \ + user_ctx->mem_util, &desc_chain); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} + +/*! Add Descriptor with two vectors */ +#define DESC_D_D(hdr, len1, ptr1, len2, ptr2) \ +{ \ + ret = sah_add_two_d_desc(hdr, ptr1, len1, ptr2, len2, \ + user_ctx->mem_util, &desc_chain); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} + +/*! Add Descriptor with input and a key */ +#define DESC_IN_KEY(hdr, len1, ptr1, key2) \ +{ \ + ret = sah_add_in_key_desc(hdr, ptr1, len1, key2, \ + user_ctx->mem_util, &desc_chain); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} + +/*! Add Descriptor with input and an output */ +#define DESC_IN_OUT(hdr, len1, ptr1, len2, ptr2) \ +{ \ + ret = sah_add_in_out_desc(hdr, ptr1, len1, ptr2, len2, \ + user_ctx->mem_util, &desc_chain); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} + +/*! Add Descriptor with input and a key output */ +#define DESC_IN_KEYOUT(hdr, len1, ptr1, key2) \ +{ \ + ret = sah_add_in_keyout_desc(hdr, ptr1, len1, key2, \ + user_ctx->mem_util, &desc_chain); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} + +/*! Add Descriptor with a key and an output */ +#define DESC_KEY_OUT(hdr, key1, len2, ptr2) \ +{ \ + ret = sah_add_key_out_desc(hdr, key1, ptr2, len2, \ + user_ctx->mem_util, &desc_chain); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} + +/*! Add Descriptor with two outputs */ +#define DESC_OUT_OUT(hdr, len1, ptr1, len2, ptr2) \ +{ \ + ret = sah_add_two_out_desc(hdr, ptr1, len1, ptr2, len2, \ + user_ctx->mem_util, &desc_chain); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} + +/*! Add Descriptor with output then input pointers */ +#define DESC_OUT_IN(hdr, len1, ptr1, len2, ptr2) \ +{ \ + ret = sah_add_out_in_desc(hdr, ptr1, len1, ptr2, len2, \ + user_ctx->mem_util, &desc_chain); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} + +#ifdef SAH_SF_DEBUG +/*! Add Descriptor with two outputs */ +#define DBG_DESC(hdr, len1, ptr1, len2, ptr2) \ +{ \ + ret = sah_add_two_out_desc(hdr, ptr1, len1, ptr2, len2, \ + user_ctx->mem_util, &desc_chain); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} +#else +#define DBG_DESC(hdr, len1, ptr1, len2, ptr2) +#endif + +#ifdef __KERNEL__ +#define DESC_DBG_ON ({console_loglevel = 8;}) +#define DESC_DBG_OFF ({console_loglevel = 7;}) +#else +#define DESC_DBG_ON system("echo 8 > /proc/sys/kernel/printk") +#define DESC_DBG_OFF system("echo 7 > /proc/sys/kernel/printk") +#endif + +#define DESC_TEMP_ALLOC(size) \ +({ \ + uint8_t* ptr; \ + ptr = user_ctx->mem_util->mu_malloc(user_ctx->mem_util->mu_ref, \ + size); \ + if (ptr == NULL) { \ + ret = FSL_RETURN_NO_RESOURCE_S; \ + goto out; \ + } \ + \ + ptr; \ +}) + +#define DESC_TEMP_FREE(ptr) \ +({ \ + if ((ptr != NULL) && \ + (!sf_executed || (user_ctx->flags & FSL_UCO_BLOCKING_MODE))) { \ + user_ctx->mem_util-> \ + mu_free(user_ctx->mem_util->mu_ref, ptr); \ + ptr = NULL; \ + } \ +}) + +/* Temporary implementation. This needs to be in internal/secure RAM */ +#define DESC_TEMP_SECURE_ALLOC(size) \ +({ \ + uint8_t* ptr; \ + ptr = user_ctx->mem_util->mu_malloc(user_ctx->mem_util->mu_ref, \ + size); \ + if (ptr == NULL) { \ + ret = FSL_RETURN_NO_RESOURCE_S; \ + goto out; \ + } \ + \ + ptr; \ +}) + +#define DESC_TEMP_SECURE_FREE(ptr, size) \ +({ \ + if ((ptr != NULL) && \ + (!sf_executed || (user_ctx->flags & FSL_UCO_BLOCKING_MODE))) { \ + user_ctx->mem_util->mu_memset(user_ctx->mem_util->mu_ref, \ + ptr, 0, size); \ + \ + user_ctx->mem_util-> \ + mu_free(user_ctx->mem_util->mu_ref, ptr); \ + ptr = NULL; \ + } \ +}) + +extern const uint32_t sah_insert_mdha_algorithm[]; + +/*! @defgroup mdhaflags MDHA Mode Register Values + * + * These are bit fields and combinations of bit fields for setting the Mode + * Register portion of a Sahara Descriptor Header field. + * + * The parity bit has been set to ensure that these values have even parity, + * therefore using an Exclusive-OR operation against an existing header will + * preserve its parity. + * + * @addtogroup mdhaflags + @{ + */ +#define sah_insert_mdha_icv_check 0x80001000 +#define sah_insert_mdha_ssl 0x80000400 +#define sah_insert_mdha_mac_full 0x80000200 +#define sah_insert_mdha_opad 0x80000080 +#define sah_insert_mdha_ipad 0x80000040 +#define sah_insert_mdha_init 0x80000020 +#define sah_insert_mdha_hmac 0x80000008 +#define sah_insert_mdha_pdata 0x80000004 +#define sah_insert_mdha_algorithm_sha224 0x00000003 +#define sah_insert_mdha_algorithm_sha256 0x80000002 +#define sah_insert_mdha_algorithm_md5 0x80000001 +#define sah_insert_mdha_algorithm_sha1 0x00000000 +/*! @} */ + +extern const uint32_t sah_insert_skha_algorithm[]; +extern const uint32_t sah_insert_skha_mode[]; +extern const uint32_t sah_insert_skha_modulus[]; + +/*! @defgroup skhaflags SKHA Mode Register Values + * + * These are bit fields and combinations of bit fields for setting the Mode + * Register portion of a Sahara Descriptor Header field. + * + * The parity bit has been set to ensure that these values have even parity, + * therefore using an Exclusive-OR operation against an existing header will + * preserve its parity. + * + * @addtogroup skhaflags + @{ + */ +/*! */ +#define sah_insert_skha_modulus_128 0x00001e00 +#define sah_insert_skha_no_key_parity 0x80000100 +#define sah_insert_skha_ctr_last_block 0x80000020 +#define sah_insert_skha_suppress_cbc 0x80000020 +#define sah_insert_skha_no_permute 0x80000020 +#define sah_insert_skha_algorithm_arc4 0x00000003 +#define sah_insert_skha_algorithm_tdes 0x80000002 +#define sah_insert_skha_algorithm_des 0x80000001 +#define sah_insert_skha_algorithm_aes 0x00000000 +#define sah_insert_skha_aux0 0x80000020 +#define sah_insert_skha_mode_ctr 0x00000018 +#define sah_insert_skha_mode_ccm 0x80000010 +#define sah_insert_skha_mode_cbc 0x80000008 +#define sah_insert_skha_mode_ecb 0x00000000 +#define sah_insert_skha_encrypt 0x80000004 +#define sah_insert_skha_decrypt 0x00000000 +/*! @} */ + +/*! @defgroup rngflags RNG Mode Register Values + * + */ +/*! */ +#define sah_insert_rng_gen_seed 0x80000001 + +/*! @} */ + +/*! @defgroup pkhaflags PKHA Mode Register Values + * + */ +/*! */ +#define sah_insert_pkha_soft_err_false 0x80000200 +#define sah_insert_pkha_soft_err_true 0x80000100 + +#define sah_insert_pkha_rtn_clr_mem 0x80000001 +#define sah_insert_pkha_rtn_clr_eram 0x80000002 +#define sah_insert_pkha_rtn_mod_exp 0x00000003 +#define sah_insert_pkha_rtn_mod_r2modn 0x80000004 +#define sah_insert_pkha_rtn_mod_rrmodp 0x00000005 +#define sah_insert_pkha_rtn_ec_fp_aff_ptmul 0x00000006 +#define sah_insert_pkha_rtn_ec_f2m_aff_ptmul 0x80000007 +#define sah_insert_pkha_rtn_ec_fp_proj_ptmul 0x80000008 +#define sah_insert_pkha_rtn_ec_f2m_proj_ptmul 0x00000009 +#define sah_insert_pkha_rtn_ec_fp_add 0x0000000A +#define sah_insert_pkha_rtn_ec_fp_double 0x8000000B +#define sah_insert_pkha_rtn_ec_f2m_add 0x0000000C +#define sah_insert_pkha_rtn_ec_f2m_double 0x8000000D +#define sah_insert_pkha_rtn_f2m_r2modn 0x8000000E +#define sah_insert_pkha_rtn_f2m_inv 0x0000000F +#define sah_insert_pkha_rtn_mod_inv 0x80000010 +#define sah_insert_pkha_rtn_rsa_sstep 0x00000011 +#define sah_insert_pkha_rtn_mod_emodn 0x00000012 +#define sah_insert_pkha_rtn_f2m_emodn 0x80000013 +#define sah_insert_pkha_rtn_ec_fp_ptmul 0x00000014 +#define sah_insert_pkha_rtn_ec_f2m_ptmul 0x80000015 +#define sah_insert_pkha_rtn_f2m_gcd 0x80000016 +#define sah_insert_pkha_rtn_mod_gcd 0x00000017 +#define sah_insert_pkha_rtn_f2m_dbl_aff 0x00000018 +#define sah_insert_pkha_rtn_fp_dbl_aff 0x80000019 +#define sah_insert_pkha_rtn_f2m_add_aff 0x8000001A +#define sah_insert_pkha_rtn_fp_add_aff 0x0000001B +#define sah_insert_pkha_rtn_f2m_exp 0x8000001C +#define sah_insert_pkha_rtn_mod_exp_teq 0x0000001D +#define sah_insert_pkha_rtn_rsa_sstep_teq 0x0000001E +#define sah_insert_pkha_rtn_f2m_multn 0x8000001F +#define sah_insert_pkha_rtn_mod_multn 0x80000020 +#define sah_insert_pkha_rtn_mod_add 0x00000021 +#define sah_insert_pkha_rtn_mod_sub 0x00000022 +#define sah_insert_pkha_rtn_mod_mult1_mont 0x80000023 +#define sah_insert_pkha_rtn_mod_mult2_deconv 0x00000024 +#define sah_insert_pkha_rtn_f2m_add 0x80000025 +#define sah_insert_pkha_rtn_f2m_mult1_mont 0x80000026 +#define sah_insert_pkha_rtn_f2m_mult2_deconv 0x00000027 +#define sah_insert_pkha_rtn_miller_rabin 0x00000028 +#define sah_insert_pkha_rtn_mod_amodn 0x00000029 +#define sah_insert_pkha_rtn_f2m_amodn 0x8000002A +/*! @} */ + +/*! Add a descriptor with two input pointers */ +fsl_shw_return_t sah_add_two_in_desc(uint32_t header, + const uint8_t * in1, + uint32_t in1_length, + const uint8_t * in2, + uint32_t in2_length, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/*! Add a descriptor with two 'data' pointers */ +fsl_shw_return_t sah_add_two_d_desc(uint32_t header, + const uint8_t * in1, + uint32_t in1_length, + const uint8_t * in2, + uint32_t in2_length, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/*! Add a descriptor with an input and key pointer */ +fsl_shw_return_t sah_add_in_key_desc(uint32_t header, + const uint8_t * in1, + uint32_t in1_length, + fsl_shw_sko_t * key_info, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/*! Add a descriptor with two key pointers */ +fsl_shw_return_t sah_add_key_key_desc(uint32_t header, + fsl_shw_sko_t * key_info1, + fsl_shw_sko_t * key_info2, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/*! Add a descriptor with two output pointers */ +fsl_shw_return_t sah_add_two_out_desc(uint32_t header, + uint8_t * out1, + uint32_t out1_length, + uint8_t * out2, + uint32_t out2_length, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/*! Add a descriptor with an input and output pointer */ +fsl_shw_return_t sah_add_in_out_desc(uint32_t header, + const uint8_t * in, uint32_t in_length, + uint8_t * out, uint32_t out_length, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/*! Add a descriptor with an input and key output pointer */ +fsl_shw_return_t sah_add_in_keyout_desc(uint32_t header, + const uint8_t * in, uint32_t in_length, + fsl_shw_sko_t * key_info, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/*! Add a descriptor with a key and an output pointer */ +fsl_shw_return_t sah_add_key_out_desc(uint32_t header, + const fsl_shw_sko_t * key_info, + uint8_t * out, uint32_t out_length, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/*! Add a descriptor with an output and input pointer */ +fsl_shw_return_t sah_add_out_in_desc(uint32_t header, + uint8_t * out, uint32_t out_length, + const uint8_t * in, uint32_t in_length, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/*! Verify that supplied User Context Object is valid */ +fsl_shw_return_t sah_validate_uco(fsl_shw_uco_t * uco); + +#endif /* SF_UTIL_H */ + +/* End of sf_util.h */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/km_adaptor.c linux-2.6.26-lab126/drivers/mxc/security/sahara2/km_adaptor.c --- linux-2.6.26/drivers/mxc/security/sahara2/km_adaptor.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/km_adaptor.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,849 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! +* @file km_adaptor.c +* +* @brief The Adaptor component provides an interface to the +* driver for a kernel user. +*/ + +#include +#include +#include +#include +#include +#ifdef FSL_HAVE_SCC +#include +#elif defined (FSL_HAVE_SCC2) +#include +#endif + + +EXPORT_SYMBOL(adaptor_Exec_Descriptor_Chain); +EXPORT_SYMBOL(sah_register); +EXPORT_SYMBOL(sah_deregister); +EXPORT_SYMBOL(sah_get_results); +EXPORT_SYMBOL(fsl_shw_smalloc); +EXPORT_SYMBOL(fsl_shw_sfree); +EXPORT_SYMBOL(fsl_shw_sstatus); +EXPORT_SYMBOL(fsl_shw_diminish_perms); +EXPORT_SYMBOL(do_scc_encrypt_region); +EXPORT_SYMBOL(do_scc_decrypt_region); +EXPORT_SYMBOL(do_system_keystore_slot_alloc); +EXPORT_SYMBOL(do_system_keystore_slot_dealloc); +EXPORT_SYMBOL(do_system_keystore_slot_load); +EXPORT_SYMBOL(do_system_keystore_slot_read); +EXPORT_SYMBOL(do_system_keystore_slot_encrypt); +EXPORT_SYMBOL(do_system_keystore_slot_decrypt); + + +#if defined(DIAG_DRV_IF) || defined(DIAG_MEM) || defined(DIAG_ADAPTOR) +#include +#endif + +#if defined(DIAG_DRV_IF) || defined(DIAG_MEM) || defined(DIAG_ADAPTOR) +#define MAX_DUMP 16 + +#define DIAG_MSG_SIZE 300 +static char Diag_msg[DIAG_MSG_SIZE]; +#endif + +/* This is the wait queue to this mode of driver */ +DECLARE_WAIT_QUEUE_HEAD(Wait_queue_km); + +/*! This matches Sahara2 capabilities... */ +fsl_shw_pco_t sahara2_capabilities = { + 1, 3, /* api version number - major & minor */ + 1, 6, /* driver version number - major & minor */ + { + FSL_KEY_ALG_AES, + FSL_KEY_ALG_DES, + FSL_KEY_ALG_TDES, + FSL_KEY_ALG_ARC4}, + { + FSL_SYM_MODE_STREAM, + FSL_SYM_MODE_ECB, + FSL_SYM_MODE_CBC, + FSL_SYM_MODE_CTR}, + { + FSL_HASH_ALG_MD5, + FSL_HASH_ALG_SHA1, + FSL_HASH_ALG_SHA224, + FSL_HASH_ALG_SHA256}, + /* + * The following table must be set to handle all values of key algorithm + * and sym mode, and be in the correct order.. + */ + { /* Stream, ECB, CBC, CTR */ + {0, 0, 0, 0}, /* HMAC */ + {0, 1, 1, 1}, /* AES */ + {0, 1, 1, 0}, /* DES */ + {0, 1, 1, 0}, /* 3DES */ + {1, 0, 0, 0} /* ARC4 */ + }, + 0, 0, + 0, 0, 0, + {{0, 0}} +}; + +#ifdef DIAG_ADAPTOR +void km_Dump_Chain(const sah_Desc * chain); + +void km_Dump_Region(const char *prefix, const unsigned char *data, + unsigned length); + +static void km_Dump_Link(const char *prefix, const sah_Link * link); + +void km_Dump_Words(const char *prefix, const unsigned *data, unsigned length); +#endif + +/**** Memory routines ****/ + +static void *my_malloc(void *ref, size_t n) +{ + register void *mem; + +#ifndef DIAG_MEM_ERRORS + mem = os_alloc_memory(n, GFP_KERNEL); + +#else + { + uint32_t rand; + /* are we feeling lucky ? */ + os_get_random_bytes(&rand, sizeof(rand)); + if ((rand % DIAG_MEM_CONST) == 0) { + mem = 0; + } else { + mem = os_alloc_memory(n, GFP_ATOMIC); + } + } +#endif /* DIAG_MEM_ERRORS */ + +#ifdef DIAG_MEM + sprintf(Diag_msg, "API kmalloc: %p for %d\n", mem, n); + LOG_KDIAG(Diag_msg); +#endif + ref = 0; /* unused param warning */ + return mem; +} + +static sah_Head_Desc *my_alloc_head_desc(void *ref) +{ + register sah_Head_Desc *ptr; + +#ifndef DIAG_MEM_ERRORS + ptr = sah_Alloc_Head_Descriptor(); + +#else + { + uint32_t rand; + /* are we feeling lucky ? */ + os_get_random_bytes(&rand, sizeof(rand)); + if ((rand % DIAG_MEM_CONST) == 0) { + ptr = 0; + } else { + ptr = sah_Alloc_Head_Descriptor(); + } + } +#endif + ref = 0; + return ptr; +} + +static sah_Desc *my_alloc_desc(void *ref) +{ + register sah_Desc *ptr; + +#ifndef DIAG_MEM_ERRORS + ptr = sah_Alloc_Descriptor(); + +#else + { + uint32_t rand; + /* are we feeling lucky ? */ + os_get_random_bytes(&rand, sizeof(rand)); + if ((rand % DIAG_MEM_CONST) == 0) { + ptr = 0; + } else { + ptr = sah_Alloc_Descriptor(); + } + } +#endif + ref = 0; + return ptr; +} + +static sah_Link *my_alloc_link(void *ref) +{ + register sah_Link *ptr; + +#ifndef DIAG_MEM_ERRORS + ptr = sah_Alloc_Link(); + +#else + { + uint32_t rand; + /* are we feeling lucky ? */ + os_get_random_bytes(&rand, sizeof(rand)); + if ((rand % DIAG_MEM_CONST) == 0) { + ptr = 0; + } else { + ptr = sah_Alloc_Link(); + } + } +#endif + ref = 0; + return ptr; +} + +static void my_free(void *ref, void *ptr) +{ + ref = 0; /* unused param warning */ +#ifdef DIAG_MEM + sprintf(Diag_msg, "API kfree: %p\n", ptr); + LOG_KDIAG(Diag_msg); +#endif + os_free_memory(ptr); +} + +static void my_free_head_desc(void *ref, sah_Head_Desc * ptr) +{ + sah_Free_Head_Descriptor(ptr); +} + +static void my_free_desc(void *ref, sah_Desc * ptr) +{ + sah_Free_Descriptor(ptr); +} + +static void my_free_link(void *ref, sah_Link * ptr) +{ + sah_Free_Link(ptr); +} + +static void *my_memcpy(void *ref, void *dest, const void *src, size_t n) +{ + ref = 0; /* unused param warning */ + return memcpy(dest, src, n); +} + +static void *my_memset(void *ref, void *ptr, int ch, size_t n) +{ + ref = 0; /* unused param warning */ + return memset(ptr, ch, n); +} + +/*! Standard memory manipulation routines for kernel API. */ +static sah_Mem_Util std_kernelmode_mem_util = { + .mu_ref = 0, + .mu_malloc = my_malloc, + .mu_alloc_head_desc = my_alloc_head_desc, + .mu_alloc_desc = my_alloc_desc, + .mu_alloc_link = my_alloc_link, + .mu_free = my_free, + .mu_free_head_desc = my_free_head_desc, + .mu_free_desc = my_free_desc, + .mu_free_link = my_free_link, + .mu_memcpy = my_memcpy, + .mu_memset = my_memset +}; + +fsl_shw_return_t get_capabilities(fsl_shw_uco_t * user_ctx, + fsl_shw_pco_t * capabilities) +{ + scc_config_t *scc_capabilities; + + /* Fill in the Sahara2 capabilities. */ + memcpy(capabilities, &sahara2_capabilities, sizeof(fsl_shw_pco_t)); + + /* Fill in the SCC portion of the capabilities object */ + scc_capabilities = scc_get_configuration(); + capabilities->scc_driver_major = scc_capabilities->driver_major_version; + capabilities->scc_driver_minor = scc_capabilities->driver_minor_version; + capabilities->scm_version = scc_capabilities->scm_version; + capabilities->smn_version = scc_capabilities->smn_version; + capabilities->block_size_bytes = scc_capabilities->block_size_bytes; + +#ifdef FSL_HAVE_SCC + capabilities->scc_info.black_ram_size_blocks = + scc_capabilities->black_ram_size_blocks; + capabilities->scc_info.red_ram_size_blocks = + scc_capabilities->red_ram_size_blocks; +#elif defined(FSL_HAVE_SCC2) + capabilities->scc2_info.partition_size_bytes = + scc_capabilities->partition_size_bytes; + capabilities->scc2_info.partition_count = + scc_capabilities->partition_count; +#endif + + return FSL_RETURN_OK_S; +} + +/*! + * Sends a request to register this user + * + * @brief Sends a request to register this user + * + * @param[in,out] user_ctx part of the structure contains input parameters and + * part is filled in by the driver + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_register(fsl_shw_uco_t * user_ctx) +{ + fsl_shw_return_t status; + + /* this field is used in user mode to indicate a file open has occured. + * it is used here, in kernel mode, to indicate that the uco is registered + */ + user_ctx->sahara_openfd = 0; /* set to 'registered' */ + user_ctx->mem_util = &std_kernelmode_mem_util; + + /* check that uco is valid */ + status = sah_validate_uco(user_ctx); + + /* If life is good, register this user */ + if (status == FSL_RETURN_OK_S) { + status = sah_handle_registration(user_ctx); + } + + if (status != FSL_RETURN_OK_S) { + user_ctx->sahara_openfd = -1; /* set to 'not registered' */ + } + + return status; +} + +/*! + * Sends a request to deregister this user + * + * @brief Sends a request to deregister this user + * + * @param[in,out] user_ctx Info on user being deregistered. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_deregister(fsl_shw_uco_t * user_ctx) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + + if (user_ctx->sahara_openfd == 0) { + status = sah_handle_deregistration(user_ctx); + user_ctx->sahara_openfd = -1; /* set to 'no registered */ + } + + return status; +} + +/*! + * Sends a request to get results for this user + * + * @brief Sends a request to get results for this user + * + * @param[in,out] arg Pointer to structure to collect results + * @param uco User's context + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_get_results(sah_results * arg, fsl_shw_uco_t * uco) +{ + fsl_shw_return_t code = sah_get_results_from_pool(uco, arg); + + if ((code == FSL_RETURN_OK_S) && (arg->actual != 0)) { + sah_Postprocess_Results(uco, arg); + } + + return code; +} + +/*! + * This function writes the Descriptor Chain to the kernel driver. + * + * @brief Writes the Descriptor Chain to the kernel driver. + * + * @param dar A pointer to a Descriptor Chain of type sah_Head_Desc + * @param uco The user context object + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t adaptor_Exec_Descriptor_Chain(sah_Head_Desc * dar, + fsl_shw_uco_t * uco) +{ + sah_Head_Desc *kernel_space_desc = NULL; + fsl_shw_return_t code = FSL_RETURN_OK_S; + int os_error_code = 0; + unsigned blocking_mode = dar->uco_flags & FSL_UCO_BLOCKING_MODE; + +#ifdef DIAG_ADAPTOR + km_Dump_Chain(&dar->desc); +#endif + + dar->user_info = uco; + dar->user_desc = dar; + + /* This code has been shamelessly copied from sah_driver_interface.c */ + /* It needs to be moved somewhere common ... */ + kernel_space_desc = sah_Physicalise_Descriptors(dar); + + if (kernel_space_desc == NULL) { + /* We may have failed due to a -EFAULT as well, but we will return + * -ENOMEM since either way it is a memory related failure. */ + code = FSL_RETURN_NO_RESOURCE_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("sah_Physicalise_Descriptors() failed\n"); +#endif + } else { + if (blocking_mode) { +#ifdef SAHARA_POLL_MODE + os_error_code = sah_Handle_Poll(dar); +#else + os_error_code = sah_blocking_mode(dar); +#endif + if (os_error_code != 0) { + code = FSL_RETURN_ERROR_S; + } else { /* status of actual operation */ + code = dar->result; + } + } else { +#ifdef SAHARA_POLL_MODE + sah_Handle_Poll(dar); +#else + /* just put someting in the DAR */ + sah_Queue_Manager_Append_Entry(dar); +#endif /* SAHARA_POLL_MODE */ + } + } + + return code; +} + + +/* System keystore context, defined in sah_driver_interface.c */ +extern fsl_shw_kso_t system_keystore; + +fsl_shw_return_t do_system_keystore_slot_alloc(fsl_shw_uco_t * user_ctx, + uint32_t key_length, + uint64_t ownerid, + uint32_t * slot) +{ + (void)user_ctx; + return keystore_slot_alloc(&system_keystore, key_length, ownerid, slot); +} + +fsl_shw_return_t do_system_keystore_slot_dealloc(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot) +{ + (void)user_ctx; + return keystore_slot_dealloc(&system_keystore, ownerid, slot); +} + +fsl_shw_return_t do_system_keystore_slot_load(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + const uint8_t * key, + uint32_t key_length) +{ + (void)user_ctx; + return keystore_slot_load(&system_keystore, ownerid, slot, + (void *)key, key_length); +} + +fsl_shw_return_t do_system_keystore_slot_read(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + const uint8_t * key) +{ + (void)user_ctx; + return keystore_slot_read(&system_keystore, ownerid, slot, + key_length, (void *)key); +} + +fsl_shw_return_t do_system_keystore_slot_encrypt(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + uint8_t * black_data) +{ + (void)user_ctx; + return keystore_slot_encrypt(NULL, &system_keystore, ownerid, + slot, key_length, black_data); +} + +fsl_shw_return_t do_system_keystore_slot_decrypt(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + const uint8_t * black_data) +{ + (void)user_ctx; + return keystore_slot_decrypt(NULL, &system_keystore, ownerid, + slot, key_length, black_data); +} + +void *fsl_shw_smalloc(fsl_shw_uco_t * user_ctx, + uint32_t size, const uint8_t * UMID, uint32_t permissions) +{ +#ifdef FSL_HAVE_SCC2 + int part_no; + void *part_base; + uint32_t part_phys; + scc_config_t *scc_configuration; + + /* Check that the memory size requested is correct */ + scc_configuration = scc_get_configuration(); + if (size != scc_configuration->partition_size_bytes) { + return NULL; + } + + /* Attempt to grab a partition. */ + if (scc_allocate_partition(0, &part_no, &part_base, &part_phys) + != SCC_RET_OK) { + return NULL; + } + printk(KERN_ALERT "In fsh_shw_smalloc (km): partition_base:%p " + "partition_base_phys: %p\n", part_base, (void *)part_phys); + + /* these bits should be in a separate function */ + printk(KERN_ALERT "writing UMID and MAP to secure the partition\n"); + + scc_engage_partition(part_base, UMID, permissions); + + (void)user_ctx; /* unused param warning */ + + return part_base; +#else /* FSL_HAVE_SCC2 */ + (void)user_ctx; + (void)size; + (void)UMID; + (void)permissions; + return NULL; +#endif /* FSL_HAVE_SCC2 */ + +} + +fsl_shw_return_t fsl_shw_sfree(fsl_shw_uco_t * user_ctx, void *address) +{ + (void)user_ctx; + +#ifdef FSL_HAVE_SCC2 + if (scc_release_partition(address) == SCC_RET_OK) { + return FSL_RETURN_OK_S; + } +#endif + + return FSL_RETURN_ERROR_S; +} + +fsl_shw_return_t fsl_shw_sstatus(fsl_shw_uco_t * user_ctx, + void *address, + fsl_shw_partition_status_t * status) +{ + (void)user_ctx; + +#ifdef FSL_HAVE_SCC2 + *status = scc_partition_status(address); + return FSL_RETURN_OK_S; +#endif + + return FSL_RETURN_ERROR_S; +} + +/* Diminish permissions on some secure memory */ +fsl_shw_return_t fsl_shw_diminish_perms(fsl_shw_uco_t * user_ctx, + void *address, uint32_t permissions) +{ + + (void)user_ctx; /* unused parameter warning */ + +#ifdef FSL_HAVE_SCC2 + if (scc_diminish_permissions(address, permissions) == SCC_RET_OK) { + return FSL_RETURN_OK_S; + } +#endif + return FSL_RETURN_ERROR_S; +} + +/* + * partition_base - physical address of the partition + * offset - offset, in blocks, of the data from the start of the partition + * length - length, in bytes, of the data to be encrypted (multiple of 4) + * black_data - virtual address that the encrypted data should be stored at + * Note that this virtual address must be translatable using the __virt_to_phys + * macro; ie, it can't be a specially mapped address. To do encryption with those + * addresses, use the scc_encrypt_region function directly. This is to make + * this function compatible with the user mode declaration, which does not know + * the physical addresses of the data it is using. + */ +fsl_shw_return_t +do_scc_encrypt_region(fsl_shw_uco_t * user_ctx, + void *partition_base, uint32_t offset_bytes, + uint32_t byte_count, uint8_t * black_data, + uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode) +{ + scc_return_t scc_ret; + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + +#ifdef FSL_HAVE_SCC2 + +#ifdef DIAG_ADAPTOR + uint32_t *owner_32 = (uint32_t *) & (owner_id); + + LOG_KDIAG_ARGS + ("partition base: %p, offset: %i, count: %i, black data: %p\n", + partition_base, offset_bytes, byte_count, (void *)black_data); +#endif + (void)user_ctx; + + os_cache_flush_range(black_data, byte_count); + + scc_ret = + scc_encrypt_region((uint32_t) partition_base, offset_bytes, + byte_count, __virt_to_phys(black_data), IV, + cypher_mode); + + if (scc_ret == SCC_RET_OK) { + retval = FSL_RETURN_OK_S; + } else { + retval = FSL_RETURN_ERROR_S; + } + + /* The SCC2 DMA engine should have written to the black ram, so we need to + * invalidate that region of memory. Note that the red ram is not an + * because it is mapped with the cache disabled. + */ + os_cache_inv_range(black_data, byte_count); + +#else + (void)scc_ret; +#endif /* FSL_HAVE_SCC2 */ + + return retval; +} + +/*! + * Call the proper function to decrypt a region of encrypted secure memory + * + * @brief + * + * @param user_ctx User context of the partition owner (NULL in kernel) + * @param partition_base Base address (physical) of the partition + * @param offset_bytes Offset from base address that the decrypted data + * shall be placed + * @param byte_count Length of the message (bytes) + * @param black_data Pointer to where the encrypted data is stored + * @param owner_id + * + * @return status + */ + +fsl_shw_return_t +do_scc_decrypt_region(fsl_shw_uco_t * user_ctx, + void *partition_base, uint32_t offset_bytes, + uint32_t byte_count, const uint8_t * black_data, + uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode) +{ + scc_return_t scc_ret; + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + +#ifdef FSL_HAVE_SCC2 + +#ifdef DIAG_ADAPTOR + uint32_t *owner_32 = (uint32_t *) & (owner_id); + + LOG_KDIAG_ARGS + ("partition base: %p, offset: %i, count: %i, black data: %p\n", + partition_base, offset_bytes, byte_count, (void *)black_data); +#endif + + (void)user_ctx; + + /* The SCC2 DMA engine will be reading from the black ram, so we need to + * make sure that the data is pushed out of the cache. Note that the red + * ram is not an issue because it is mapped with the cache disabled. + */ + os_cache_flush_range(black_data, byte_count); + + scc_ret = + scc_decrypt_region((uint32_t) partition_base, offset_bytes, + byte_count, + (uint8_t *) __virt_to_phys(black_data), IV, + cypher_mode); + + if (scc_ret == SCC_RET_OK) { + retval = FSL_RETURN_OK_S; + } else { + retval = FSL_RETURN_ERROR_S; + } + +#else + (void)scc_ret; +#endif /* FSL_HAVE_SCC2 */ + + return retval; +} + +#ifdef DIAG_ADAPTOR +/*! + * Dump chain of descriptors to the log. + * + * @brief Dump descriptor chain + * + * @param chain Kernel virtual address of start of chain of descriptors + * + * @return void + */ +void km_Dump_Chain(const sah_Desc * chain) +{ + while (chain != NULL) { + km_Dump_Words("Desc", (unsigned *)chain, + 6 /*sizeof(*chain)/sizeof(unsigned) */ ); + /* place this definition elsewhere */ + if (chain->ptr1) { + if (chain->header & SAH_HDR_LLO) { + km_Dump_Region(" Data1", chain->ptr1, + chain->len1); + } else { + km_Dump_Link(" Link1", chain->ptr1); + } + } + if (chain->ptr2) { + if (chain->header & SAH_HDR_LLO) { + km_Dump_Region(" Data2", chain->ptr2, + chain->len2); + } else { + km_Dump_Link(" Link2", chain->ptr2); + } + } + + chain = chain->next; + } +} + +/*! + * Dump chain of links to the log. + * + * @brief Dump chain of links + * + * @param prefix Text to put in front of dumped data + * @param link Kernel virtual address of start of chain of links + * + * @return void + */ +static void km_Dump_Link(const char *prefix, const sah_Link * link) +{ + while (link != NULL) { + km_Dump_Words(prefix, (unsigned *)link, + 3 /* # words in h/w link */ ); + if (link->flags & SAH_STORED_KEY_INFO) { +#ifdef CAN_DUMP_SCC_DATA + uint32_t len; +#endif + +#ifdef CAN_DUMP_SCC_DATA + { + char buf[50]; + + scc_get_slot_info(link->ownerid, link->slot, (uint32_t *) & link->data, /* RED key address */ + &len); /* key length */ + sprintf(buf, " SCC slot %d: ", link->slot); + km_Dump_Words(buf, + (void *)IO_ADDRESS((uint32_t) + link->data), + link->len / 4); + } +#else + sprintf(Diag_msg, " SCC slot %d", link->slot); + LOG_KDIAG(Diag_msg); +#endif + } else if (link->data != NULL) { + km_Dump_Region(" Data", link->data, link->len); + } + + link = link->next; + } +} + +/*! + * Dump given region of data to the log. + * + * @brief Dump data + * + * @param prefix Text to put in front of dumped data + * @param data Kernel virtual address of start of region to dump + * @param length Amount of data to dump + * + * @return void +*/ +void km_Dump_Region(const char *prefix, const unsigned char *data, + unsigned length) +{ + unsigned count; + char *output; + unsigned data_len; + + sprintf(Diag_msg, "%s (%08X,%u):", prefix, (uint32_t) data, length); + + /* Restrict amount of data to dump */ + if (length > MAX_DUMP) { + data_len = MAX_DUMP; + } else { + data_len = length; + } + + /* We've already printed some text in output buffer, skip over it */ + output = Diag_msg + strlen(Diag_msg); + + for (count = 0; count < data_len; count++) { + if (count % 4 == 0) { + *output++ = ' '; + } + sprintf(output, "%02X", *data++); + output += 2; + } + + LOG_KDIAG(Diag_msg); +} + +/*! + * Dump given wors of data to the log. + * + * @brief Dump data + * + * @param prefix Text to put in front of dumped data + * @param data Kernel virtual address of start of region to dump + * @param word_count Amount of data to dump + * + * @return void +*/ +void km_Dump_Words(const char *prefix, const unsigned *data, + unsigned word_count) +{ + char *output; + + sprintf(Diag_msg, "%s (%08X,%uw): ", prefix, (uint32_t) data, + word_count); + + /* We've already printed some text in output buffer, skip over it */ + output = Diag_msg + strlen(Diag_msg); + + while (word_count--) { + sprintf(output, "%08X ", *data++); + output += 9; + } + + LOG_KDIAG(Diag_msg); +} +#endif diff -urN linux-2.6.26/drivers/mxc/security/sahara2/sah_driver_interface.c linux-2.6.26-lab126/drivers/mxc/security/sahara2/sah_driver_interface.c --- linux-2.6.26/drivers/mxc/security/sahara2/sah_driver_interface.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/sah_driver_interface.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,2162 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! +* @file sah_driver_interface.c +* +* @brief Provides a Linux Kernel Module interface to the SAHARA h/w device. +* +*/ + +/* SAHARA Includes */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef FSL_HAVE_SCC +#include +#else +#include +#endif + +#ifdef DIAG_DRV_IF +#include +#endif + +#if defined(CONFIG_DEVFS_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) +#include +#else +#include +#endif + +#include + +#ifdef PERF_TEST +#define interruptible_sleep_on(x) sah_Handle_Interrupt() +#endif + +#define TEST_MODE_OFF 1 +#define TEST_MODE_ON 2 + +/*! Version register on first deployments */ +#define SAHARA_VERSION2 2 +/*! Version register on MX27 */ +#define SAHARA_VERSION3 3 +/*! Version register on MXC92323 */ +#define SAHARA_VERSION4 4 + +/****************************************************************************** +* Module function declarations +******************************************************************************/ + +OS_DEV_INIT_DCL(sah_init); +OS_DEV_SHUTDOWN_DCL(sah_cleanup); +OS_DEV_OPEN_DCL(sah_open); +OS_DEV_CLOSE_DCL(sah_release); +OS_DEV_IOCTL_DCL(sah_ioctl); +OS_DEV_MMAP_DCL(sah_mmap); + +static os_error_code sah_handle_get_capabilities(fsl_shw_uco_t* user_ctx, + uint32_t info); + +static void sah_user_callback(fsl_shw_uco_t * user_ctx); +static os_error_code sah_handle_scc_sfree(fsl_shw_uco_t* user_ctx, + uint32_t info); +static os_error_code sah_handle_scc_sstatus(fsl_shw_uco_t* user_ctx, + uint32_t info); +static os_error_code sah_handle_scc_drop_perms(fsl_shw_uco_t* user_ctx, + uint32_t info); +static os_error_code sah_handle_scc_encrypt(fsl_shw_uco_t* user_ctx, + uint32_t info); +static os_error_code sah_handle_scc_decrypt(fsl_shw_uco_t* user_ctx, + uint32_t info); + +#ifdef FSL_HAVE_SCC2 +static fsl_shw_return_t register_user_partition(fsl_shw_uco_t * user_ctx, + uint32_t user_base, + void *kernel_base); +static fsl_shw_return_t deregister_user_partition(fsl_shw_uco_t * user_ctx, + uint32_t user_base); +#endif + +static os_error_code sah_handle_sk_slot_alloc(uint32_t info); +static os_error_code sah_handle_sk_slot_dealloc(uint32_t info); +static os_error_code sah_handle_sk_slot_load(uint32_t info); +static os_error_code sah_handle_sk_slot_read(uint32_t info); +static os_error_code sah_handle_sk_slot_decrypt(uint32_t info); +static os_error_code sah_handle_sk_slot_encrypt(uint32_t info); + +/*! Boolean flag for whether interrupt handler needs to be released on exit */ +static unsigned interrupt_registered; + +static int handle_sah_ioctl_dar(fsl_shw_uco_t * filp, uint32_t user_space_desc); + +#if !defined(CONFIG_DEVFS_FS) || (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) +static int sah_read_procfs(char *buf, + char **start, + off_t offset, int count, int *eof, void *data); + +static int sah_write_procfs(struct file *file, const char __user * buffer, + unsigned long count, void *data); +#endif + +#if defined(CONFIG_DEVFS_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) + +/* This is a handle to the sahara DEVFS entry. */ +static devfs_handle_t Sahara_devfs_handle; + +#else + +/* Major number assigned to our device driver */ +static int Major; + +/* This is a handle to the sahara PROCFS entry */ +static struct proc_dir_entry *Sahara_procfs_handle; + +#endif + +uint32_t sah_hw_version; + +/* This is the wait queue to this driver. Linux declaration. */ +DECLARE_WAIT_QUEUE_HEAD(Wait_queue); + +/* This is a global variable that is used to track how many times the device + * has been opened simultaneously. */ +#ifdef DIAG_DRV_IF +static int Device_in_use = 0; +#endif + +/* This is the system keystore object */ +fsl_shw_kso_t system_keystore; + +/*! + * OS-dependent handle used for registering user interface of a driver. + */ +static os_driver_reg_t reg_handle; + +#ifdef DIAG_DRV_IF +/* This is for sprintf() to use when constructing output. */ +#define DIAG_MSG_SIZE 1024 +static char Diag_msg[DIAG_MSG_SIZE]; +#endif + +/*! +******************************************************************************* +* This function gets called when the module is inserted (insmod) into the +* running kernel. +* +* @brief SAHARA device initialisation function. +* +* @return 0 on success +* @return -EBUSY if the device or proc file entry cannot be created. +* @return OS_ERROR_NO_MEMORY_S if kernel memory could not be allocated. +* @return OS_ERROR_FAIL_S if initialisation of proc entry failed +*/ +OS_DEV_INIT(sah_init) +{ + /* Status variable */ + int os_error_code = 0; + + interrupt_registered = 0; + + /* Enable the SAHARA Clocks */ +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA : Enabling the IPG and AHB clocks\n") +#endif /*DIAG_DRV_IF */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) + mxc_clks_enable(SAHARA2_CLK); +#else + { + struct clk *clk = clk_get(NULL, "sahara_clk"); + if (clk != ERR_PTR(ENOENT)) { + clk_enable(clk); + } + } +#endif + + /* Check for SPBA need */ +#if defined(CONFIG_ARCH_MXC91231) || defined(CONFIG_ARCH_MXC91321) + /* This needs to be a PLATFORM abstraction */ + if (spba_take_ownership(SPBA_SAHARA, SPBA_MASTER_A)) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("Sahara driver could not take ownership of Sahara\n"); +#endif + os_error_code = OS_ERROR_FAIL_S; + } +#endif /* SPBA */ + + if (os_error_code == OS_ERROR_OK_S) { + sah_hw_version = sah_HW_Read_Version(); + os_printk("Sahara HW Version is 0x%08x\n", sah_hw_version); + + /* verify code and hardware are version compatible */ + if ((sah_hw_version != SAHARA_VERSION2) + && (sah_hw_version != SAHARA_VERSION3)) { + if (((sah_hw_version >> 8) & 0xff) != SAHARA_VERSION4) { + os_printk + ("Sahara HW Version was not expected value.\n"); + os_error_code = OS_ERROR_FAIL_S; + } + } + } + + if (os_error_code == OS_ERROR_OK_S) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("Calling sah_Init_Mem_Map to initialise " + "memory subsystem."); +#endif + /* Do any memory-routine initialization */ + os_error_code = sah_Init_Mem_Map(); + } + + if (os_error_code == OS_ERROR_OK_S) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("Calling sah_HW_Reset() to Initialise the Hardware."); +#endif + /* Initialise the hardware */ + os_error_code = sah_HW_Reset(); + if (os_error_code != OS_ERROR_OK_S) { + os_printk + ("sah_HW_Reset() failed to Initialise the Hardware.\n"); + } + + } + + if (os_error_code == OS_ERROR_OK_S) { +#if defined(CONFIG_DEVFS_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) + /* Register the DEVFS entry */ + Sahara_devfs_handle = devfs_register(NULL, + SAHARA_DEVICE_SHORT, + DEVFS_FL_AUTO_DEVNUM, + 0, 0, + SAHARA_DEVICE_MODE, + &Fops, NULL); + if (Sahara_devfs_handle == NULL) { +#ifdef DIAG_DRV_IF + LOG_KDIAG + ("Registering the DEVFS character device failed."); +#endif /* DIAG_DRV_IF */ + os_error_code = -EBUSY; + } +#else /* CONFIG_DEVFS_FS */ + /* Create the PROCFS entry. This is used to report the assigned device + * major number back to user-space. */ +#if 1 + Sahara_procfs_handle = create_proc_entry(SAHARA_DEVICE_SHORT, 0700, /* default mode */ + NULL); /* parent dir */ + if (Sahara_procfs_handle == NULL) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("Registering the PROCFS interface failed."); +#endif /* DIAG_DRV_IF */ + os_error_code = OS_ERROR_FAIL_S; + } else { + Sahara_procfs_handle->nlink = 1; + Sahara_procfs_handle->data = 0; + Sahara_procfs_handle->read_proc = sah_read_procfs; + Sahara_procfs_handle->write_proc = sah_write_procfs; + } +#endif /* #if 1 */ + } + + if (os_error_code == OS_ERROR_OK_S) { +#ifdef DIAG_DRV_IF + LOG_KDIAG + ("Calling sah_Queue_Manager_Init() to Initialise the Queue " + "Manager."); +#endif + /* Initialise the Queue Manager */ + if (sah_Queue_Manager_Init() != FSL_RETURN_OK_S) { + os_error_code = -ENOMEM; + } + } +#ifndef SAHARA_POLL_MODE + if (os_error_code == OS_ERROR_OK_S) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("Calling sah_Intr_Init() to Initialise the Interrupt " + "Handler."); +#endif + /* Initialise the Interrupt Handler */ + os_error_code = sah_Intr_Init(&Wait_queue); + if (os_error_code == OS_ERROR_OK_S) { + interrupt_registered = 1; + } + } +#endif /* ifndef SAHARA_POLL_MODE */ + +#ifdef SAHARA_POWER_MANAGEMENT + if (os_error_code == OS_ERROR_OK_S) { + /* set up dynamic power management (dmp) */ + os_error_code = sah_dpm_init(); + } +#endif + + if (os_error_code == OS_ERROR_OK_S) { + os_driver_init_registration(reg_handle); + os_driver_add_registration(reg_handle, OS_FN_OPEN, + OS_DEV_OPEN_REF(sah_open)); + os_driver_add_registration(reg_handle, OS_FN_IOCTL, + OS_DEV_IOCTL_REF(sah_ioctl)); + os_driver_add_registration(reg_handle, OS_FN_CLOSE, + OS_DEV_CLOSE_REF(sah_release)); + os_driver_add_registration(reg_handle, OS_FN_MMAP, + OS_DEV_MMAP_REF(sah_mmap)); + + os_error_code = + os_driver_complete_registration(reg_handle, Major, + "sahara"); + + if (os_error_code < OS_ERROR_OK_S) { +#ifdef DIAG_DRV_IF + snprintf(Diag_msg, DIAG_MSG_SIZE, + "Registering the regular " + "character device failed with error code: %d\n", + os_error_code); + LOG_KDIAG(Diag_msg); +#endif + } + } +#endif /* CONFIG_DEVFS_FS */ + + if (os_error_code == OS_ERROR_OK_S) { + /* set up the system keystore, using the default keystore handler */ + fsl_shw_init_keystore_default(&system_keystore); + + if (fsl_shw_establish_keystore(NULL, &system_keystore) + == FSL_RETURN_OK_S) { + os_error_code = OS_ERROR_OK_S; + } else { + os_error_code = OS_ERROR_FAIL_S; + } + + if (os_error_code != OS_ERROR_OK_S) { +#ifdef DIAG_DRV_IF + snprintf(Diag_msg, DIAG_MSG_SIZE, + "Registering the system keystore " + "failed with error code: %d\n", os_error_code); + LOG_KDIAG(Diag_msg); +#endif + } + } + + if (os_error_code != OS_ERROR_OK_S) { +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) + cleanup_module(); +#else + sah_cleanup(); +#endif + } +#ifdef DIAG_DRV_IF + else { + LOG_KDIAG_ARGS("Sahara major node is %d\n", Major); + } +#endif + + os_dev_init_return(os_error_code); +} + +/*! +******************************************************************************* +* This function gets called when the module is removed (rmmod) from the running +* kernel. +* +* @brief SAHARA device clean-up function. +* +* @return void +*/ +OS_DEV_SHUTDOWN(sah_cleanup) +{ + int ret_val = 0; + + printk(KERN_ALERT "Sahara going into cleanup\n"); + + /* clear out the system keystore */ + fsl_shw_release_keystore(NULL, &system_keystore); + + /* Unregister the device */ +#if defined(CONFIG_DEVFS_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) + devfs_unregister(Sahara_devfs_handle); +#else + + if (Sahara_procfs_handle != NULL) { + remove_proc_entry(SAHARA_DEVICE_SHORT, NULL); + } + + if (Major >= 0) { + ret_val = os_driver_remove_registration(reg_handle); + } +#ifdef DIAG_DRV_IF + if (ret_val < 0) { + snprintf(Diag_msg, DIAG_MSG_SIZE, "Error while attempting to " + "unregister the device: %d\n", ret_val); + LOG_KDIAG(Diag_msg); + } +#endif + +#endif /* CONFIG_DEVFS_FS */ + sah_Queue_Manager_Close(); + +#ifndef SAHARA_POLL_MODE + if (interrupt_registered) { + sah_Intr_Release(); + interrupt_registered = 0; + } +#endif + sah_Stop_Mem_Map(); +#ifdef SAHARA_POWER_MANAGEMENT + sah_dpm_close(); +#endif + +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA : Disabling the clocks\n") +#endif /* DIAG_DRV_IF */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) + mxc_clks_disable(SAHARA2_CLK); +#else + { + struct clk *clk = clk_get(NULL, "sahara_clk"); + if (clk != ERR_PTR(ENOENT)) { + clk_disable(clk); + } + } +#endif + + os_dev_shutdown_return(OS_ERROR_OK_S); +} + +/*! +******************************************************************************* +* This function simply increments the module usage count. +* +* @brief SAHARA device open function. +* +* @param inode Part of the kernel prototype. +* @param file Part of the kernel prototype. +* +* @return 0 - Always returns 0 since any number of calls to this function are +* allowed. +* +*/ +OS_DEV_OPEN(sah_open) +{ + +#if defined(LINUX_VERSION) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10)) + MOD_INC_USE_COUNT; +#endif + +#ifdef DIAG_DRV_IF + Device_in_use++; + snprintf(Diag_msg, DIAG_MSG_SIZE, + "Incrementing module use count to: %d ", Device_in_use); + LOG_KDIAG(Diag_msg); +#endif + + os_dev_set_user_private(NULL); + + /* Return 0 to indicate success */ + os_dev_open_return(0); +} + +/*! +******************************************************************************* +* This function simply decrements the module usage count. +* +* @brief SAHARA device release function. +* +* @param inode Part of the kernel prototype. +* @param file Part of the kernel prototype. +* +* @return 0 - Always returns 0 since this function does not fail. +*/ +OS_DEV_CLOSE(sah_release) +{ + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + +#if defined(LINUX_VERSION) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10)) + MOD_DEC_USE_COUNT; +#endif + +#ifdef DIAG_DRV_IF + Device_in_use--; + snprintf(Diag_msg, DIAG_MSG_SIZE, + "Decrementing module use count to: %d ", Device_in_use); + LOG_KDIAG(Diag_msg); +#endif + + if (user_ctx != NULL) { + sah_handle_deregistration(user_ctx); + os_free_memory(user_ctx); + os_dev_set_user_private(NULL); + } + + /* Return 0 to indicate success */ + os_dev_close_return(OS_ERROR_OK_S); +} + +/*! +******************************************************************************* +* This function provides the IO Controls for the SAHARA driver. Three IO +* Controls are supported: +* +* SAHARA_HWRESET and +* SAHARA_SET_HA +* SAHARA_CHK_TEST_MODE +* +* @brief SAHARA device IO Control function. +* +* @param inode Part of the kernel prototype. +* @param filp Part of the kernel prototype. +* @param cmd Part of the kernel prototype. +* @param arg Part of the kernel prototype. +* +* @return 0 on success +* @return -EBUSY if the HA bit could not be set due to busy hardware. +* @return -ENOTTY if an unsupported IOCTL was attempted on the device. +* @return -EFAULT if put_user() fails +*/ +OS_DEV_IOCTL(sah_ioctl) +{ + int status = 0; + int test_mode; + + switch (os_dev_get_ioctl_op()) { + case SAHARA_HWRESET: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_HWRESET IOCTL."); +#endif + /* We need to reset the hardware. */ + sah_HW_Reset(); + + /* Mark all the entries in the Queue Manager's queue with state + * SAH_STATE_RESET. + */ + sah_Queue_Manager_Reset_Entries(); + + /* Wake up all sleeping write() calls. */ + wake_up_interruptible(&Wait_queue); + break; +#ifdef SAHARA_HA_ENABLED + case SAHARA_SET_HA: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SET_HA IOCTL."); +#endif /* DIAG_DRV_IF */ + if (sah_HW_Set_HA() == ERR_INTERNAL) { + status = -EBUSY; + } + break; +#endif /* SAHARA_HA_ENABLED */ + + case SAHARA_CHK_TEST_MODE: + /* load test_mode */ + test_mode = TEST_MODE_OFF; +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_CHECK_TEST_MODE IOCTL."); + test_mode = TEST_MODE_ON; +#endif /* DIAG_DRV_IF */ +#if defined(KERNEL_TEST) || defined(PERF_TEST) + test_mode = TEST_MODE_ON; +#endif /* KERNEL_TEST || PERF_TEST */ + /* copy test_mode back to user space. put_user() is Linux fn */ + /* compiler warning `register': no problem found so ignored */ + status = put_user(test_mode, (int *)os_dev_get_ioctl_arg()); + break; + + case SAHARA_DAR: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_DAR IOCTL."); +#endif /* DIAG_DRV_IF */ + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + if (user_ctx != NULL) { + status = + handle_sah_ioctl_dar(user_ctx, + os_dev_get_ioctl_arg + ()); + } else { + status = OS_ERROR_FAIL_S; + } + + } + break; + + case SAHARA_GET_RESULTS: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_GET_RESULTS IOCTL."); +#endif /* DIAG_DRV_IF */ + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + if (user_ctx != NULL) { + status = + sah_get_results_pointers(user_ctx, + os_dev_get_ioctl_arg + ()); + } else { + status = OS_ERROR_FAIL_S; + } + } + break; + + case SAHARA_REGISTER: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_REGISTER IOCTL."); +#endif /* DIAG_DRV_IF */ + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + if (user_ctx != NULL) { + status = OS_ERROR_FAIL_S; /* already registered */ + } else { + user_ctx = + os_alloc_memory(sizeof(fsl_shw_uco_t), + GFP_KERNEL); + if (user_ctx == NULL) { + status = OS_ERROR_NO_MEMORY_S; + } else { + /* Copy UCO from user, but only as big as the common UCO */ + if (os_copy_from_user(user_ctx, + (void *) + os_dev_get_ioctl_arg + (), + offsetof + (fsl_shw_uco_t, + result_pool))) { + status = OS_ERROR_FAIL_S; + } else { + os_dev_set_user_private + (user_ctx); + status = + sah_handle_registration + (user_ctx); + } + } + } + } + break; + + /* This ioctl cmd should disappear in favor of a close() routine. */ + case SAHARA_DEREGISTER: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_DEREGISTER IOCTL."); +#endif /* DIAG_DRV_IF */ + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + if (user_ctx == NULL) { + status = OS_ERROR_FAIL_S; + } else { + status = sah_handle_deregistration(user_ctx); + os_free_memory(user_ctx); + os_dev_set_user_private(NULL); + } + } + break; + case SAHARA_SCC_DROP_PERMS: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SCC_DROP_PERMS IOCTL."); +#endif /* DIAG_DRV_IF */ + { + /* drop permissions on the specified partition */ + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + status = + sah_handle_scc_drop_perms(user_ctx, + os_dev_get_ioctl_arg()); + } + break; + + case SAHARA_SCC_SFREE: + /* Unmap the specified partition from the users space, and then + * free it for use by someone else. + */ +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SCC_SFREE IOCTL."); +#endif /* DIAG_DRV_IF */ + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + status = + sah_handle_scc_sfree(user_ctx, + os_dev_get_ioctl_arg()); + } + break; + + case SAHARA_SCC_SSTATUS: + /* Unmap the specified partition from the users space, and then + * free it for use by someone else. + */ +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SCC_SSTATUS IOCTL."); +#endif /* DIAG_DRV_IF */ + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + status = + sah_handle_scc_sstatus(user_ctx, + os_dev_get_ioctl_arg()); + } + break; + + case SAHARA_SCC_ENCRYPT: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SCC_ENCRYPT IOCTL."); +#endif /* DIAG_DRV_IF */ + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + status = + sah_handle_scc_encrypt(user_ctx, + os_dev_get_ioctl_arg()); + } + break; + + case SAHARA_SCC_DECRYPT: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SCC_DECRYPT IOCTL."); +#endif /* DIAG_DRV_IF */ + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + status = + sah_handle_scc_decrypt(user_ctx, + os_dev_get_ioctl_arg()); + } + break; + + case SAHARA_SK_ALLOC: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SK_ALLOC IOCTL."); +#endif /* DIAG_DRV_IF */ + status = sah_handle_sk_slot_alloc(os_dev_get_ioctl_arg()); + break; + + case SAHARA_SK_DEALLOC: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SK_DEALLOC IOCTL."); +#endif /* DIAG_DRV_IF */ + status = sah_handle_sk_slot_dealloc(os_dev_get_ioctl_arg()); + break; + + case SAHARA_SK_LOAD: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SK_LOAD IOCTL."); +#endif /* DIAG_DRV_IF */ + status = sah_handle_sk_slot_load(os_dev_get_ioctl_arg()); + break; + case SAHARA_SK_READ: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SK_READ IOCTL."); +#endif /* DIAG_DRV_IF */ + status = sah_handle_sk_slot_read(os_dev_get_ioctl_arg()); + break; + + case SAHARA_SK_SLOT_DEC: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SK_SLOT_DECRYPT IOCTL."); +#endif /* DIAG_DRV_IF */ + status = sah_handle_sk_slot_decrypt(os_dev_get_ioctl_arg()); + break; + + case SAHARA_SK_SLOT_ENC: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SK_SLOT_ENCRYPT IOCTL."); +#endif /* DIAG_DRV_IF */ + status = sah_handle_sk_slot_encrypt(os_dev_get_ioctl_arg()); + break; + case SAHARA_GET_CAPS: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_GET_CAPS IOCTL."); +#endif /* DIAG_DRV_IF */ + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + status = + sah_handle_get_capabilities(user_ctx, + os_dev_get_ioctl_arg()); + } + break; + + default: +#ifdef DIAG_DRV_IF + LOG_KDIAG("Unknown SAHARA IOCTL."); +#endif /* DIAG_DRV_IF */ + status = OS_ERROR_FAIL_S; + } + + os_dev_ioctl_return(status); +} + +/* Fill in the user's capabilities structure */ +static os_error_code sah_handle_get_capabilities(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code status = OS_ERROR_FAIL_S; + fsl_shw_pco_t capabilities; + + status = os_copy_from_user(&capabilities, (void *)info, + sizeof(fsl_shw_pco_t)); + + if (status != OS_ERROR_OK_S) { + goto out; + } + + if (get_capabilities(user_ctx, &capabilities) == FSL_RETURN_OK_S) { + status = os_copy_to_user((void *)info, &capabilities, + sizeof(fsl_shw_pco_t)); + } + + out: + return status; +} + +#ifdef FSL_HAVE_SCC2 + +/* Find the kernel-mode address of the partition. + * This can then be passed to the SCC functions. + */ +void *lookup_user_partition(fsl_shw_uco_t * user_ctx, uint32_t user_base) +{ + /* search through the partition chain to find one that matches the user base + * address. + */ + fsl_shw_spo_t *curr = (fsl_shw_spo_t *) user_ctx->partition; + + while (curr != NULL) { + if (curr->user_base == user_base) { + return curr->kernel_base; + } + curr = (fsl_shw_spo_t *) curr->next; + } + return NULL; +} + +/* user_base: userspace base address of the partition + * kernel_base: kernel mode base address of the partition + */ +static fsl_shw_return_t register_user_partition(fsl_shw_uco_t * user_ctx, + uint32_t user_base, + void *kernel_base) +{ + fsl_shw_spo_t *partition_info; + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + if (user_ctx == NULL) { + goto out; + } + + partition_info = os_alloc_memory(sizeof(fsl_shw_spo_t), GFP_KERNEL); + + if (partition_info == NULL) { + goto out; + } + + /* stuff the partition info, then put it at the front of the chain */ + partition_info->user_base = user_base; + partition_info->kernel_base = kernel_base; + partition_info->next = user_ctx->partition; + + user_ctx->partition = (struct fsl_shw_spo_t *)partition_info; + +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS + ("partition with user_base=%p, kernel_base=%p registered.", + (void *)user_base, kernel_base); +#endif + + ret = FSL_RETURN_OK_S; + + out: + + return ret; +} + +/* if the partition is in the users list, remove it */ +static fsl_shw_return_t deregister_user_partition(fsl_shw_uco_t * user_ctx, + uint32_t user_base) +{ + fsl_shw_spo_t *curr = (fsl_shw_spo_t *) user_ctx->partition; + fsl_shw_spo_t *last = (fsl_shw_spo_t *) user_ctx->partition; + + while (curr != NULL) { + if (curr->user_base == user_base) { + +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS + ("deregister_user_partition: partition with " + "user_base=%p, kernel_base=%p deregistered.\n", + (void *)curr->user_base, curr->kernel_base); +#endif + + if (last == curr) { + user_ctx->partition = curr->next; + os_free_memory(curr); + return FSL_RETURN_OK_S; + } else { + last->next = curr->next; + os_free_memory(curr); + return FSL_RETURN_OK_S; + } + } + last = curr; + curr = (fsl_shw_spo_t *) curr->next; + } + + return FSL_RETURN_ERROR_S; +} + +#endif /* FSL_HAVE_SCC2 */ + +static os_error_code sah_handle_scc_drop_perms(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code status = OS_ERROR_NO_MEMORY_S; +#ifdef FSL_HAVE_SCC2 + scc_return_t scc_ret; + scc_partition_info_t partition_info; + void *kernel_base; + + status = + os_copy_from_user(&partition_info, (void *)info, + sizeof(partition_info)); + + if (status != OS_ERROR_OK_S) { + goto out; + } + + /* validate that the user owns this partition, and look up its handle */ + kernel_base = lookup_user_partition(user_ctx, partition_info.user_base); + + if (kernel_base == NULL) { + status = OS_ERROR_FAIL_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("_scc_drop_perms(): failed to find partition\n"); +#endif + goto out; + } + + /* call scc driver to perform the drop */ + scc_ret = scc_diminish_permissions(kernel_base, + partition_info.permissions); + if (scc_ret == SCC_RET_OK) { + status = OS_ERROR_OK_S; + } else { + status = OS_ERROR_FAIL_S; + } + + out: +#endif /* FSL_HAVE_SCC2 */ + return status; +} + +static os_error_code sah_handle_scc_sfree(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code status = OS_ERROR_NO_MEMORY_S; +#ifdef FSL_HAVE_SCC2 + { + scc_partition_info_t partition_info; + void *kernel_base; + int ret; + + status = + os_copy_from_user(&partition_info, (void *)info, + sizeof(partition_info)); + + /* check that the copy was successful */ + if (status != OS_ERROR_OK_S) { + goto out; + } + + /* validate that the user owns this partition, and look up its handle */ + kernel_base = + lookup_user_partition(user_ctx, partition_info.user_base); + + if (kernel_base == NULL) { + status = OS_ERROR_FAIL_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("failed to find partition\n"); +#endif /*DIAG_DRV_IF */ + goto out; + } + + /* Unmap the memory region (see sys_munmap in mmap.c) */ + ret = unmap_user_memory(partition_info.user_base, 8192); + + /* If the memory was successfully released */ + if (ret == OS_ERROR_OK_S) { + + /* release the partition */ + scc_release_partition(kernel_base); + + /* and remove it from the users context */ + deregister_user_partition(user_ctx, + partition_info.user_base); + + status = OS_ERROR_OK_S; + } + } + out: +#endif /* FSL_HAVE_SCC2 */ + return status; +} + +static os_error_code sah_handle_scc_sstatus(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code status = OS_ERROR_NO_MEMORY_S; +#ifdef FSL_HAVE_SCC2 + { + scc_partition_info_t partition_info; + void *kernel_base; + + status = + os_copy_from_user(&partition_info, (void *)info, + sizeof(partition_info)); + + /* check that the copy was successful */ + if (status != OS_ERROR_OK_S) { + goto out; + } + + /* validate that the user owns this partition, and look up its handle */ + kernel_base = + lookup_user_partition(user_ctx, partition_info.user_base); + + if (kernel_base == NULL) { + status = OS_ERROR_FAIL_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("failed to find partition\n"); +#endif /*DIAG_DRV_IF */ + goto out; + } + + partition_info.status = scc_partition_status(kernel_base); + + status = + os_copy_to_user((void *)info, &partition_info, + sizeof(partition_info)); + } + out: +#endif /* FSL_HAVE_SCC2 */ + return status; +} + +static os_error_code sah_handle_scc_encrypt(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code os_err = OS_ERROR_FAIL_S; +#ifdef FSL_HAVE_SCC2 + { + fsl_shw_return_t retval; + scc_region_t region_info; + void *page_ctx = NULL; + void *black_addr = NULL; + void *partition_base = NULL; + scc_config_t *scc_configuration; + + os_err = + os_copy_from_user(®ion_info, (void *)info, + sizeof(region_info)); + + if (os_err != OS_ERROR_OK_S) { + goto out; + } +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS + ("partition_base: %p, offset: %i, length: %i, black data: %p", + (void *)region_info.partition_base, region_info.offset, + region_info.length, (void *)region_info.black_data); +#endif + + /* validate that the user owns this partition, and look up its handle */ + partition_base = lookup_user_partition(user_ctx, + region_info. + partition_base); + + if (partition_base == NULL) { + retval = FSL_RETURN_ERROR_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("failed to find secure partition\n"); +#endif + goto out; + } + + /* Check that the memory size requested is correct */ + scc_configuration = scc_get_configuration(); + if (region_info.offset + region_info.length > + scc_configuration->partition_size_bytes) { + retval = FSL_RETURN_ERROR_S; + goto out; + } + + /* wire down black data */ + black_addr = wire_user_memory(region_info.black_data, + region_info.length, &page_ctx); + + if (black_addr == NULL) { + retval = FSL_RETURN_ERROR_S; + goto out; + } + + retval = + do_scc_encrypt_region(NULL, partition_base, + region_info.offset, + region_info.length, black_addr, + region_info.IV, + region_info.cypher_mode); + + /* release black data */ + unwire_user_memory(&page_ctx); + + out: + if (os_err == OS_ERROR_OK_S) { + /* Return error code */ + region_info.code = retval; + os_err = + os_copy_to_user((void *)info, ®ion_info, + sizeof(region_info)); + } + } + +#endif + return os_err; +} + +static os_error_code sah_handle_scc_decrypt(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code os_err = OS_ERROR_FAIL_S; +#ifdef FSL_HAVE_SCC2 + { + fsl_shw_return_t retval; + scc_region_t region_info; + void *page_ctx = NULL; + void *black_addr; + void *partition_base; + scc_config_t *scc_configuration; + + os_err = + os_copy_from_user(®ion_info, (void *)info, + sizeof(region_info)); + + if (os_err != OS_ERROR_OK_S) { + goto out; + } +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS + ("partition_base: %p, offset: %i, length: %i, black data: %p", + (void *)region_info.partition_base, region_info.offset, + region_info.length, (void *)region_info.black_data); +#endif + + /* validate that the user owns this partition, and look up its handle */ + partition_base = lookup_user_partition(user_ctx, + region_info. + partition_base); + + if (partition_base == NULL) { + retval = FSL_RETURN_ERROR_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("failed to find partition\n"); +#endif + goto out; + } + + /* Check that the memory size requested is correct */ + scc_configuration = scc_get_configuration(); + if (region_info.offset + region_info.length > + scc_configuration->partition_size_bytes) { + retval = FSL_RETURN_ERROR_S; + goto out; + } + + /* wire down black data */ + black_addr = wire_user_memory(region_info.black_data, + region_info.length, &page_ctx); + + if (black_addr == NULL) { + retval = FSL_RETURN_ERROR_S; + goto out; + } + + retval = + do_scc_decrypt_region(NULL, partition_base, + region_info.offset, + region_info.length, black_addr, + region_info.IV, + region_info.cypher_mode); + + /* release black data */ + unwire_user_memory(&page_ctx); + + out: + if (os_err == OS_ERROR_OK_S) { + /* Return error code */ + region_info.code = retval; + os_err = + os_copy_to_user((void *)info, ®ion_info, + sizeof(region_info)); + } + } + +#endif /* FSL_HAVE_SCC2 */ + return os_err; +} + +/*****************************************************************************/ +/* fn get_user_smid() */ +/*****************************************************************************/ +uint32_t get_user_smid(void *proc) +{ + /* + * A real implementation would have some way to handle signed applications + * which wouild be assigned distinct SMIDs. For the reference + * implementation, we show where this would be determined (here), but + * always provide a fixed answer, thus not separating users at all. + */ + + return 0x42eaae42; +} + +/*! +******************************************************************************* +* This function implements the smalloc() function for userspace programs, by +* making a call to the SCC2 mmap() function that acquires a region of secure +* memory on behalf of the user, and then maps it into the users memory space. +* Currently, the only memory size supported is that of a single SCC2 partition. +* Requests for other sized memory regions will fail. +*/ +OS_DEV_MMAP(sah_mmap) +{ + os_error_code status = OS_ERROR_NO_MEMORY_S; + +#ifdef FSL_HAVE_SCC2 + { + scc_return_t scc_ret; + fsl_shw_return_t fsl_ret; + uint32_t partition_registered = FALSE; + + uint32_t user_base; + void *partition_base; + uint32_t smid; + scc_config_t *scc_configuration; + + int part_no = -1; + uint32_t part_phys; + + fsl_shw_uco_t *user_ctx = + (fsl_shw_uco_t *) os_dev_get_user_private(); + + /* Make sure that the user context is valid */ + if (user_ctx == NULL) { + user_ctx = + os_alloc_memory(sizeof(*user_ctx), GFP_KERNEL); + + if (user_ctx == NULL) { + status = OS_ERROR_NO_MEMORY_S; + goto out; + } + + sah_handle_registration(user_ctx); + os_dev_set_user_private(user_ctx); + } + + /* Determine the size of a secure partition */ + scc_configuration = scc_get_configuration(); + + /* Check that the memory size requested is equal to the partition + * size, and that the requested destination is on a page boundary. + */ + if (((os_mmap_user_base() % PAGE_SIZE) != 0) || + (os_mmap_memory_size() != + scc_configuration->partition_size_bytes)) { + status = OS_ERROR_BAD_ARG_S; + goto out; + } + + /* Retrieve the SMID associated with the user */ + smid = get_user_smid(user_ctx->process); + + /* Attempt to allocate a secure partition */ + scc_ret = + scc_allocate_partition(smid, &part_no, &partition_base, + &part_phys); + if (scc_ret != SCC_RET_OK) { + pr_debug + ("SCC mmap() request failed to allocate partition;" + " error %d\n", status); + status = OS_ERROR_FAIL_S; + goto out; + } + + pr_debug("scc_mmap() acquired partition %d at %08x\n", + part_no, part_phys); + + /* Record partition info in the user context */ + user_base = os_mmap_user_base(); + fsl_ret = + register_user_partition(user_ctx, user_base, + partition_base); + + if (fsl_ret != FSL_RETURN_OK_S) { + pr_debug + ("SCC mmap() request failed to register partition with user" + " context, error: %d\n", fsl_ret); + status = OS_ERROR_FAIL_S; + } + + partition_registered = TRUE; + + status = map_user_memory(os_mmap_memory_ctx(), part_phys, + os_mmap_memory_size()); + +#ifdef SHW_DEBUG + if (status == OS_ERROR_OK_S) { + LOG_KDIAG_ARGS + ("Partition allocated: user_base=%p, partition_base=%p.", + (void *)user_base, partition_base); + } +#endif + + out: + /* If there is an error it has to be handled here */ + if (status != OS_ERROR_OK_S) { + /* if the partition was registered with the user, unregister it. */ + if (partition_registered == TRUE) { + deregister_user_partition(user_ctx, user_base); + } + + /* if the partition was allocated, deallocate it */ + if (partition_base != NULL) { + scc_release_partition(partition_base); + } + } + } +#endif /* FSL_HAVE_SCC2 */ + + return status; +} + +/* Find the physical address of a key stored in the system keystore */ +fsl_shw_return_t +system_keystore_get_slot_info(uint64_t owner_id, uint32_t slot, + uint32_t * address, uint32_t * slot_size_bytes) +{ + fsl_shw_return_t retval; + void *kernel_address; + + /* First verify that the key access is valid */ + retval = system_keystore.slot_verify_access(system_keystore.user_data, + owner_id, slot); + + if (retval != FSL_RETURN_OK_S) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("verification failed"); +#endif + return retval; + } + + if (address != NULL) { +#ifdef FSL_HAVE_SCC2 + kernel_address = + system_keystore.slot_get_address(system_keystore.user_data, + slot); + (*address) = scc_virt_to_phys(kernel_address); +#else + kernel_address = + system_keystore.slot_get_address((void *)&owner_id, slot); + (*address) = (uint32_t) kernel_address; +#endif + } + + if (slot_size_bytes != NULL) { +#ifdef FSL_HAVE_SCC2 + *slot_size_bytes = + system_keystore.slot_get_slot_size(system_keystore. + user_data, slot); +#else + *slot_size_bytes = + system_keystore.slot_get_slot_size((void *)&owner_id, slot); +#endif + } + + return retval; +} + +static os_error_code sah_handle_sk_slot_alloc(uint32_t info) +{ + scc_slot_t slot_info; + os_error_code os_err; + scc_return_t scc_ret; + + os_err = os_copy_from_user(&slot_info, (void *)info, sizeof(slot_info)); + if (os_err == OS_ERROR_OK_S) { + scc_ret = keystore_slot_alloc(&system_keystore, + slot_info.key_length, + slot_info.ownerid, + &slot_info.slot); + if (scc_ret == SCC_RET_OK) { + slot_info.code = FSL_RETURN_OK_S; + } else if (scc_ret == SCC_RET_INSUFFICIENT_SPACE) { + slot_info.code = FSL_RETURN_NO_RESOURCE_S; + } else { + slot_info.code = FSL_RETURN_ERROR_S; + } + +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS("key length: %i, handle: %i\n", + slot_info.key_length, slot_info.slot); +#endif + + /* Return error code and slot info */ + os_err = + os_copy_to_user((void *)info, &slot_info, + sizeof(slot_info)); + + if (os_err != OS_ERROR_OK_S) { + (void)keystore_slot_dealloc(&system_keystore, + slot_info.ownerid, + slot_info.slot); + } + } + + return os_err; +} + +static os_error_code sah_handle_sk_slot_dealloc(uint32_t info) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + scc_slot_t slot_info; + os_error_code os_err; + scc_return_t scc_ret; + + os_err = os_copy_from_user(&slot_info, (void *)info, sizeof(slot_info)); + + if (os_err == OS_ERROR_OK_S) { + scc_ret = keystore_slot_dealloc(&system_keystore, + slot_info.ownerid, + slot_info.slot); + + if (scc_ret == SCC_RET_OK) { + ret = FSL_RETURN_OK_S; + } else { + ret = FSL_RETURN_ERROR_S; + } + slot_info.code = ret; + + os_err = + os_copy_to_user((void *)info, &slot_info, + sizeof(slot_info)); + } + + return os_err; +} + +static os_error_code sah_handle_sk_slot_load(uint32_t info) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + scc_slot_t slot_info; + os_error_code os_err; + uint8_t *key = NULL; + + os_err = os_copy_from_user(&slot_info, (void *)info, sizeof(slot_info)); + + if (os_err == OS_ERROR_OK_S) { + /* Allow slop in alloc in case we are rounding up to word multiple */ + key = os_alloc_memory(slot_info.key_length + 3, GFP_KERNEL); + if (key == NULL) { + ret = FSL_RETURN_NO_RESOURCE_S; + os_err = OS_ERROR_NO_MEMORY_S; + } else { + os_err = os_copy_from_user(key, slot_info.key, + slot_info.key_length); + } + } + + if (os_err == OS_ERROR_OK_S) { + unsigned key_length = slot_info.key_length; + + /* Round up if necessary, as SCC call wants a multiple of 32-bit + * values for the full object being loaded. */ + if ((key_length & 3) != 0) { + key_length += 4 - (key_length & 3); + } + ret = keystore_slot_load(&system_keystore, + slot_info.ownerid, slot_info.slot, key, + key_length); + + slot_info.code = ret; + os_err = + os_copy_to_user((void *)info, &slot_info, + sizeof(slot_info)); + } + + if (key != NULL) { + memset(key, 0, slot_info.key_length); + os_free_memory(key); + } + + return os_err; +} + +static os_error_code sah_handle_sk_slot_read(uint32_t info) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + scc_slot_t slot_info; + os_error_code os_err; + uint8_t *key = NULL; + + os_err = os_copy_from_user(&slot_info, (void *)info, sizeof(slot_info)); + + if (os_err == OS_ERROR_OK_S) { + + /* This operation is not allowed for user keys */ + slot_info.code = FSL_RETURN_NO_RESOURCE_S; + os_err = + os_copy_to_user((void *)info, &slot_info, + sizeof(slot_info)); + + return os_err; + } + + if (os_err == OS_ERROR_OK_S) { + /* Allow slop in alloc in case we are rounding up to word multiple */ + key = os_alloc_memory(slot_info.key_length + 3, GFP_KERNEL); + if (key == NULL) { + ret = FSL_RETURN_NO_RESOURCE_S; + os_err = OS_ERROR_NO_MEMORY_S; + } + } + + if (os_err == OS_ERROR_OK_S) { + unsigned key_length = slot_info.key_length; + + /* @bug Do some PERMISSIONS checking - make sure this is SW key */ + + /* Round up if necessary, as SCC call wants a multiple of 32-bit + * values for the full object being loaded. */ + if ((key_length & 3) != 0) { + key_length += 4 - (key_length & 3); + } + ret = keystore_slot_read(&system_keystore, + slot_info.ownerid, slot_info.slot, + key_length, key); + + /* @bug do some error checking */ + + /* Send key back to user */ + os_err = os_copy_to_user(slot_info.key, key, + slot_info.key_length); + + slot_info.code = ret; + os_err = + os_copy_to_user((void *)info, &slot_info, + sizeof(slot_info)); + } + + if (key != NULL) { + memset(key, 0, slot_info.key_length); + os_free_memory(key); + } + + return os_err; +} + +static os_error_code sah_handle_sk_slot_encrypt(uint32_t info) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + scc_slot_t slot_info; + os_error_code os_err; + scc_return_t scc_ret; + uint8_t *key = NULL; + + os_err = os_copy_from_user(&slot_info, (void *)info, sizeof(slot_info)); + + if (os_err == OS_ERROR_OK_S) { + key = os_alloc_memory(slot_info.key_length, GFP_KERNEL); + if (key == NULL) { + ret = FSL_RETURN_NO_RESOURCE_S; + } + } + + if (key != NULL) { + + scc_ret = keystore_slot_encrypt(NULL, &system_keystore, + slot_info.ownerid, + slot_info.slot, + slot_info.key_length, key); + + if (scc_ret != SCC_RET_OK) { + ret = FSL_RETURN_ERROR_S; + } else { + os_err = + os_copy_to_user(slot_info.key, key, + slot_info.key_length); + if (os_err != OS_ERROR_OK_S) { + ret = FSL_RETURN_INTERNAL_ERROR_S; + } else { + ret = FSL_RETURN_OK_S; + } + } + + slot_info.code = ret; + os_err = + os_copy_to_user((void *)info, &slot_info, + sizeof(slot_info)); + + memset(key, 0, slot_info.key_length); + os_free_memory(key); + } + + return os_err; +} + +static os_error_code sah_handle_sk_slot_decrypt(uint32_t info) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + scc_slot_t slot_info; /*!< decrypt request fields */ + os_error_code os_err; + scc_return_t scc_ret; + uint8_t *key = NULL; + + os_err = os_copy_from_user(&slot_info, (void *)info, sizeof(slot_info)); + + if (os_err == OS_ERROR_OK_S) { + key = os_alloc_memory(slot_info.key_length, GFP_KERNEL); + if (key == NULL) { + ret = FSL_RETURN_NO_RESOURCE_S; + os_err = OS_ERROR_OK_S; + } else { + os_err = os_copy_from_user(key, slot_info.key, + slot_info.key_length); + } + } + + if (os_err == OS_ERROR_OK_S) { + scc_ret = keystore_slot_decrypt(NULL, &system_keystore, + slot_info.ownerid, + slot_info.slot, + slot_info.key_length, key); + if (scc_ret == SCC_RET_OK) { + ret = FSL_RETURN_OK_S; + } else { + ret = FSL_RETURN_ERROR_S; + } + + slot_info.code = ret; + os_err = + os_copy_to_user((void *)info, &slot_info, + sizeof(slot_info)); + } + + if (key != NULL) { + memset(key, 0, slot_info.key_length); + os_free_memory(key); + } + + return os_err; +} + +/*! + * Register a user + * + * @brief Register a user + * + * @param user_ctx information about this user + * + * @return status code + */ +fsl_shw_return_t sah_handle_registration(fsl_shw_uco_t * user_ctx) +{ + /* Initialize the user's result pool (like sah_Queue_Construct() */ + user_ctx->result_pool.head = NULL; + user_ctx->result_pool.tail = NULL; + user_ctx->result_pool.count = 0; + + /* initialize the user's partition chain */ + user_ctx->partition = NULL; + + return FSL_RETURN_OK_S; +} + +/*! + * Deregister a user + * + * @brief Deregister a user + * + * @param user_ctx information about this user + * + * @return status code + */ +fsl_shw_return_t sah_handle_deregistration(fsl_shw_uco_t * user_ctx) +{ + /* NOTE: + * This will release any secure partitions that are held by the user. + * Encryption keys that were placed in the system keystore by the user + * should not be removed here, because they might have been shared with + * another process. The user must be careful to release any that are no + * longer in use. + */ + fsl_shw_return_t ret = FSL_RETURN_OK_S; + +#ifdef FSL_HAVE_SCC2 + fsl_shw_spo_t *partition; + struct mm_struct *mm = current->mm; + + while ((user_ctx->partition != NULL) && (ret == FSL_RETURN_OK_S)) { + + partition = user_ctx->partition; + +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS + ("Found an abandoned secure partition at %p, releasing", + partition); +#endif + + /* It appears that current->mm is not valid if this is called from a + * close routine (perhaps only if the program raised an exception that + * caused it to close?) If that is the case, then still free the + * partition, but do not remove it from the memory space (dangerous?) + */ + + if (mm == NULL) { +#ifdef DIAG_DRV_IF + LOG_KDIAG + ("Warning: no mm structure found, not unmapping " + "partition from user memory\n"); +#endif + } else { + /* Unmap the memory region (see sys_munmap in mmap.c) */ + /* Note that this assumes a single memory partition */ + unmap_user_memory(partition->user_base, 8192); + } + + /* If the memory was successfully released */ + if (ret == OS_ERROR_OK_S) { + /* release the partition */ + scc_release_partition(partition->kernel_base); + + /* and remove it from the users context */ + deregister_user_partition(user_ctx, + partition->user_base); + + ret = FSL_RETURN_OK_S; + } else { + ret = FSL_RETURN_ERROR_S; + + goto out; + } + } + out: +#endif /* FSL_HAVE_SCC2 */ + + return ret; +} + +/*! + * Sets up memory to extract results from results pool + * + * @brief Sets up memory to extract results from results pool + * + * @param user_ctx information about this user + * @param[in,out] arg contains input parameters and fields that the driver + * fills in + * + * @return os error code or 0 on success + */ +int sah_get_results_pointers(fsl_shw_uco_t * user_ctx, uint32_t arg) +{ + sah_results results_arg; /* kernel mode usable version of 'arg' */ + fsl_shw_result_t *user_results; /* user mode address of results */ + unsigned *user_actual; /* user mode address of actual number of results */ + unsigned actual; /* local memory of actual number of results */ + int ret_val = OS_ERROR_FAIL_S; + sah_Head_Desc *finished_request; + unsigned int loop; + + /* copy structure from user to kernel space */ + if (!os_copy_from_user(&results_arg, (void *)arg, sizeof(sah_results))) { + /* save user space pointers */ + user_actual = results_arg.actual; /* where count goes */ + user_results = results_arg.results; /* where results goe */ + + /* Set pointer for actual value to temporary kernel memory location */ + results_arg.actual = &actual; + + /* Allocate kernel memory to hold temporary copy of the results */ + results_arg.results = + os_alloc_memory(sizeof(fsl_shw_result_t) * + results_arg.requested, GFP_KERNEL); + + /* if memory allocated, continue */ + if (results_arg.results == NULL) { + ret_val = OS_ERROR_NO_MEMORY_S; + } else { + fsl_shw_return_t get_status; + + /* get the results */ + get_status = + sah_get_results_from_pool(user_ctx, &results_arg); + + /* free the copy of the user space descriptor chain */ + for (loop = 0; loop < actual; ++loop) { + /* get sah_Head_Desc from results and put user address into + * the return structure */ + finished_request = + results_arg.results[loop].user_desc; + results_arg.results[loop].user_desc = + finished_request->user_desc; + /* return the descriptor chain memory to the block free pool */ + sah_Free_Chained_Descriptors(finished_request); + } + + /* if no errors, copy results and then the actual number of results + * back to user space + */ + if (get_status == FSL_RETURN_OK_S) { + if (os_copy_to_user + (user_results, results_arg.results, + actual * sizeof(fsl_shw_result_t)) + || os_copy_to_user(user_actual, &actual, + sizeof(user_actual))) { + ret_val = OS_ERROR_FAIL_S; + } else { + ret_val = 0; /* no error */ + } + } + /* free the allocated memory */ + os_free_memory(results_arg.results); + } + } + + return ret_val; +} + +/*! + * Extracts results from results pool + * + * @brief Extract results from results pool + * + * @param user_ctx information about this user + * @param[in,out] arg contains input parameters and fields that the + * driver fills in + * + * @return status code + */ +fsl_shw_return_t sah_get_results_from_pool(volatile fsl_shw_uco_t * user_ctx, + sah_results * arg) +{ + sah_Head_Desc *finished_request; + unsigned int loop = 0; + os_lock_context_t int_flags; + + /* Get the number of results requested, up to total number of results + * available + */ + do { + /* Protect state of user's result pool until we have retrieved and + * remove the first entry, or determined that the pool is empty. */ + os_lock_save_context(desc_queue_lock, int_flags); + finished_request = user_ctx->result_pool.head; + + if (finished_request != NULL) { + sah_Queue_Remove_Entry((sah_Queue *) & user_ctx-> + result_pool); + os_unlock_restore_context(desc_queue_lock, int_flags); + + /* Prepare to free. */ + (void)sah_DePhysicalise_Descriptors(finished_request); + + arg->results[loop].user_ref = + finished_request->user_ref; + arg->results[loop].code = finished_request->result; + arg->results[loop].detail1 = + finished_request->fault_address; + arg->results[loop].detail2 = 0; + arg->results[loop].user_desc = finished_request; + + loop++; + } else { /* finished_request is NULL */ + /* pool is empty */ + os_unlock_restore_context(desc_queue_lock, int_flags); + } + + } while ((loop < arg->requested) && (finished_request != NULL)); + + /* record number of results actually obtained */ + *arg->actual = loop; + + return FSL_RETURN_OK_S; +} + +/*! + * Converts descriptor chain to kernel space (from user space) and submits + * chain to Sahara for processing + * + * @brief Submits converted descriptor chain to sahara + * + * @param user_ctx Pointer to Kernel version of user's ctx + * @param user_space_desc user space address of descriptor chain that is + * in user space + * + * @return OS status code + */ +static int handle_sah_ioctl_dar(fsl_shw_uco_t * user_ctx, + uint32_t user_space_desc) +{ + int os_error_code = OS_ERROR_FAIL_S; + sah_Head_Desc *desc_chain_head; /* chain in kernel - virtual address */ + + /* This will re-create the linked list so that the SAHARA hardware can + * DMA on it. + */ + desc_chain_head = sah_Copy_Descriptors(user_ctx, + (sah_Head_Desc *) + user_space_desc); + + if (desc_chain_head == NULL) { + /* We may have failed due to a -EFAULT as well, but we will return + * OS_ERROR_NO_MEMORY_S since either way it is a memory related + * failure. + */ + os_error_code = OS_ERROR_NO_MEMORY_S; + } else { + fsl_shw_return_t stat; + + desc_chain_head->user_info = user_ctx; + desc_chain_head->user_desc = (sah_Head_Desc *) user_space_desc; + + if (desc_chain_head->uco_flags & FSL_UCO_BLOCKING_MODE) { +#ifdef SAHARA_POLL_MODE + sah_Handle_Poll(desc_chain_head); +#else + sah_blocking_mode(desc_chain_head); +#endif + stat = desc_chain_head->result; + /* return the descriptor chain memory to the block free pool */ + sah_Free_Chained_Descriptors(desc_chain_head); + /* Tell user how the call turned out */ + + /* Copy 'result' back up to the result member. + * + * The dereference of the different member will cause correct the + * arithmetic to occur on the user-space address because of the + * missing dma/bus locations in the user mode version of the + * sah_Desc structure. */ + os_error_code = + os_copy_to_user((void *)(user_space_desc + + offsetof(sah_Head_Desc, + uco_flags)), + &stat, sizeof(fsl_shw_return_t)); + + } else { /* not blocking mode - queue and forget */ + + if (desc_chain_head->uco_flags & FSL_UCO_CALLBACK_MODE) { + user_ctx->process = os_get_process_handle(); + user_ctx->callback = sah_user_callback; + } +#ifdef SAHARA_POLL_MODE + /* will put results in result pool */ + sah_Handle_Poll(desc_chain_head); +#else + /* just put someting in the DAR */ + sah_Queue_Manager_Append_Entry(desc_chain_head); +#endif + /* assume all went well */ + os_error_code = OS_ERROR_OK_S; + } + } + + return os_error_code; +} + +static void sah_user_callback(fsl_shw_uco_t * user_ctx) +{ + os_send_signal(user_ctx->process, SIGUSR2); +} + +/*! + * This function is called when a thread attempts to read from the /proc/sahara + * file. Upon read, statistics and information about the state of the driver + * are returned in nthe supplied buffer. + * + * @brief SAHARA PROCFS read function. + * + * @param buf Anything written to this buffer will be returned to the + * user-space process that is reading from this proc entry. + * @param start Part of the kernel prototype. + * @param offset Part of the kernel prototype. + * @param count The size of the buf argument. + * @param eof An integer which is set to one to tell the user-space + * process that there is no more data to read. + * @param data Part of the kernel prototype. + * + * @return The number of bytes written to the proc entry. + */ +#if !defined(CONFIG_DEVFS_FS) || (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) +static int sah_read_procfs(char *buf, + char **start, + off_t offset, int count, int *eof, void *data) +{ + int output_bytes = 0; + int in_queue_count = 0; + os_lock_context_t lock_context; + + os_lock_save_context(desc_queue_lock, lock_context); + in_queue_count = sah_Queue_Manager_Count_Entries(TRUE, 0); + os_unlock_restore_context(desc_queue_lock, lock_context); + output_bytes += snprintf(buf, count - output_bytes, "queued: %d\n", + in_queue_count); + output_bytes += snprintf(buf + output_bytes, count - output_bytes, + "Descriptors: %d, " + "Interrupts %d (%d Done1Done2, %d Done1Busy2, " + " %d Done1)\n", + dar_count, interrupt_count, done1done2_count, + done1busy2_count, done1_count); + output_bytes += snprintf(buf + output_bytes, count - output_bytes, + "Control: %08x\n", sah_HW_Read_Control()); +#if !defined(FSL_HAVE_SAHARA4) || defined(SAHARA4_NO_USE_SQUIB) + output_bytes += snprintf(buf + output_bytes, count - output_bytes, + "IDAR: %08x; CDAR: %08x\n", + sah_HW_Read_IDAR(), sah_HW_Read_CDAR()); +#endif +#ifdef DIAG_DRV_STATUS + output_bytes += snprintf(buf + output_bytes, count - output_bytes, + "Status: %08x; Error Status: %08x; Op Status: %08x\n", + sah_HW_Read_Status(), + sah_HW_Read_Error_Status(), + sah_HW_Read_Op_Status()); +#endif +#ifdef FSL_HAVE_SAHARA4 + output_bytes += snprintf(buf + output_bytes, count - output_bytes, + "MMStat: %08x; Config: %08x\n", + sah_HW_Read_MM_Status(), sah_HW_Read_Config()); +#endif + + /* Signal the end of the file */ + *eof = 1; + + /* To get rid of the unused parameter warnings */ + (void)start; + (void)data; + (void)offset; + + return output_bytes; +} + +static int sah_write_procfs(struct file *file, const char __user * buffer, + unsigned long count, void *data) +{ + + /* Any write to this file will reset all counts. */ + dar_count = interrupt_count = done1done2_count = + done1busy2_count = done1_count = 0; + + (void)file; + (void)buffer; + (void)data; + + return count; +} + +#endif + +#ifndef SAHARA_POLL_MODE +/*! + * Block user call until processing is complete. + * + * @param entry The user's request. + * + * @return An OS error code, or 0 if no error + */ +int sah_blocking_mode(sah_Head_Desc * entry) +{ + int os_error_code = 0; + sah_Queue_Status status; + + /* queue entry, put something in the DAR, if nothing is there currently */ + sah_Queue_Manager_Append_Entry(entry); + + /* get this descriptor chain's current status */ + status = ((volatile sah_Head_Desc *)entry)->status; + + while (!SAH_DESC_PROCESSED(status)) { + extern sah_Queue *main_queue; + + DEFINE_WAIT(sahara_wait); /* create a wait queue entry. Linux */ + + /* enter the wait queue entry into the queue */ + prepare_to_wait(&Wait_queue, &sahara_wait, TASK_INTERRUPTIBLE); + + /* check if this entry has been processed */ + status = ((volatile sah_Head_Desc *)entry)->status; + + if (!SAH_DESC_PROCESSED(status)) { + /* go to sleep - Linux */ + schedule(); + } + + /* un-queue the 'prepare to wait' queue? - Linux */ + finish_wait(&Wait_queue, &sahara_wait); + + /* signal belongs to this thread? */ + if (signal_pending(current)) { /* Linux */ + os_lock_context_t lock_flags; + + /* don't allow access during this check and operation */ + os_lock_save_context(desc_queue_lock, lock_flags); + status = ((volatile sah_Head_Desc *)entry)->status; + if (status == SAH_STATE_PENDING) { + sah_Queue_Remove_Any_Entry(main_queue, entry); + entry->result = FSL_RETURN_INTERNAL_ERROR_S; + ((volatile sah_Head_Desc *)entry)->status = + SAH_STATE_FAILED; + } + os_unlock_restore_context(desc_queue_lock, lock_flags); + } + + status = ((volatile sah_Head_Desc *)entry)->status; + } /* while ... */ + + /* Do this so that caller can free */ + (void)sah_DePhysicalise_Descriptors(entry); + + return os_error_code; +} + +/*! + * If interrupt does not return in a reasonable time, time out, trigger + * interrupt, and continue with process + * + * @param data ignored + */ +void sahara_timeout_handler(unsigned long data) +{ + /* Sahara has not issuing an interrupt, so timed out */ +#ifdef DIAG_DRV_IF + LOG_KDIAG("Sahara HW did not respond. Resetting.\n"); +#endif + /* assume hardware needs resetting */ + sah_Handle_Interrupt(SAH_EXEC_FAULT); + /* wake up sleeping thread to try again */ + wake_up_interruptible(&Wait_queue); +} + +#endif /* ifndef SAHARA_POLL_MODE */ + +/* End of sah_driver_interface.c */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/sah_hardware_interface.c linux-2.6.26-lab126/drivers/mxc/security/sahara2/sah_hardware_interface.c --- linux-2.6.26/drivers/mxc/security/sahara2/sah_hardware_interface.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/sah_hardware_interface.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,854 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file sah_hardware_interface.c + * + * @brief Provides an interface to the SAHARA hardware registers. + * + */ + +/* SAHARA Includes */ +#include +#include +#include +#include + +#if defined DIAG_DRV_IF || defined(DO_DBG) +#include +#ifndef LOG_KDIAG +#define LOG_KDIAG(x) os_printk("%s\n", x) +#endif + +static void sah_Dump_Link(const char *prefix, const sah_Link * link, + dma_addr_t addr); + +/* This is for sprintf() to use when constructing output. */ +#define DIAG_MSG_SIZE 1024 +/* was 200 */ +#define MAX_DUMP 200 +static char Diag_msg[DIAG_MSG_SIZE]; + +#endif /* DIAG_DRV_IF */ + +/*! + * Number of descriptors sent to Sahara. This value should only be updated + * with the main queue lock held. + */ +uint32_t dar_count; + +/*! The "link-list optimize" bit in the Header of a Descriptor */ +#define SAH_HDR_LLO 0x01000000 + +/* IO_ADDRESS() is Linux macro -- need portable equivalent */ +#define SAHARA_BASE_ADDRESS IO_ADDRESS(SAHA_BASE_ADDR) +#define SAHARA_VERSION_REGISTER_OFFSET 0x000 +#define SAHARA_DAR_REGISTER_OFFSET 0x004 +#define SAHARA_CONTROL_REGISTER_OFFSET 0x008 +#define SAHARA_COMMAND_REGISTER_OFFSET 0x00C +#define SAHARA_STATUS_REGISTER_OFFSET 0x010 +#define SAHARA_ESTATUS_REGISTER_OFFSET 0x014 +#define SAHARA_FLT_ADD_REGISTER_OFFSET 0x018 +#define SAHARA_CDAR_REGISTER_OFFSET 0x01C +#define SAHARA_IDAR_REGISTER_OFFSET 0x020 +#define SAHARA_OSTATUS_REGISTER_OFFSET 0x028 +#define SAHARA_CONFIG_REGISTER_OFFSET 0x02C +#define SAHARA_MM_STAT_REGISTER_OFFSET 0x030 + +/*! Register within Sahara which contains hardware version. (1 or 2). */ +#define SAHARA_VERSION_REGISTER (SAHARA_BASE_ADDRESS + \ + SAHARA_VERSION_REGISTER_OFFSET) + +/*! Register within Sahara which is used to provide new work to the block. */ +#define SAHARA_DAR_REGISTER (SAHARA_BASE_ADDRESS + \ + SAHARA_DAR_REGISTER_OFFSET) + +/*! Register with Sahara which is used for configuration. */ +#define SAHARA_CONTROL_REGISTER (SAHARA_BASE_ADDRESS + \ + SAHARA_CONTROL_REGISTER_OFFSET) + +/*! Register with Sahara which is used for changing status. */ +#define SAHARA_COMMAND_REGISTER (SAHARA_BASE_ADDRESS + \ + SAHARA_COMMAND_REGISTER_OFFSET) + +/*! Register with Sahara which is contains status and state. */ +#define SAHARA_STATUS_REGISTER (SAHARA_BASE_ADDRESS + \ + SAHARA_STATUS_REGISTER_OFFSET) + +/*! Register with Sahara which is contains error status information. */ +#define SAHARA_ESTATUS_REGISTER (SAHARA_BASE_ADDRESS + \ + SAHARA_ESTATUS_REGISTER_OFFSET) + +/*! Register with Sahara which is contains faulting address information. */ +#define SAHARA_FLT_ADD_REGISTER (SAHARA_BASE_ADDRESS + \ + SAHARA_FLT_ADD_REGISTER_OFFSET) + +/*! Register with Sahara which is contains current descriptor address. */ +#define SAHARA_CDAR_REGISTER (SAHARA_BASE_ADDRESS + \ + SAHARA_CDAR_REGISTER_OFFSET) + +/*! Register with Sahara which is contains initial descriptor address (of a + chain). */ +#define SAHARA_IDAR_REGISTER (SAHARA_BASE_ADDRESS + \ + SAHARA_IDAR_REGISTER_OFFSET) + +/*! Register with Sahara which is contains op status information. */ +#define SAHARA_OSTATUS_REGISTER (SAHARA_BASE_ADDRESS + \ + SAHARA_OSTATUS_REGISTER_OFFSET) + +/*! Register with Sahara which is contains configuration information. */ +#define SAHARA_CONFIG_REGISTER (SAHARA_BASE_ADDRESS + \ + SAHARA_CONFIG_REGISTER_OFFSET) + +/*! Register with Sahara which is contains configuration information. */ +#define SAHARA_MM_STAT_REGISTER (SAHARA_BASE_ADDRESS + \ + SAHARA_MM_STAT_REGISTER_OFFSET) + +/* Local Functions */ +#if defined DIAG_DRV_IF || defined DO_DBG +void sah_Dump_Region(const char *prefix, const unsigned char *data, + dma_addr_t addr, unsigned length); + +#endif /* DIAG_DRV_IF */ + +/* time out value when polling SAHARA status register for completion */ +static uint32_t sah_poll_timeout = 0xFFFFFFFF; + +/*! + * Polls Sahara to determine when its current operation is complete + * + * @return last value found in Sahara's status register + */ +sah_Execute_Status sah_Wait_On_Sahara() +{ + uint32_t count = 0; /* ensure we don't get stuck in the loop forever */ + sah_Execute_Status status; /* Sahara's status register */ + uint32_t stat_reg; + + pr_debug("Entered sah_Wait_On_Sahara\n"); + + do { + /* get current status register from Sahara */ + stat_reg = sah_HW_Read_Status(); + status = stat_reg & SAH_EXEC_STATE_MASK; + + /* timeout if SAHARA takes too long to complete */ + if (++count == sah_poll_timeout) { + status = SAH_EXEC_FAULT; + printk("sah_Wait_On_Sahara timed out\n"); + } + + /* stay in loop as long as Sahara is still busy */ + } while ((status == SAH_EXEC_BUSY) || (status == SAH_EXEC_DONE1_BUSY2)); + + if (status == SAH_EXEC_ERROR1) { + if (stat_reg & OP_STATUS) { + status = SAH_EXEC_OPSTAT1; + } + } + + return status; +} /* sah_Wait_on_Sahara() */ + +/*! + * This function resets the SAHARA hardware. The following operations are + * performed: + * 1. Resets SAHARA. + * 2. Requests BATCH mode. + * 3. Enables interrupts. + * 4. Requests Little Endian mode. + * + * @brief SAHARA hardware reset function. + * + * @return void + */ +int sah_HW_Reset(void) +{ + sah_Execute_Status sah_state; + int status; /* this is the value to return to the calling routine */ + uint32_t saha_control = 0; + +#ifndef USE_3WORD_BURST +#ifdef FSL_HAVE_SAHARA2 + saha_control |= (8 << 16); /* Allow 8-word burst */ +#endif +#else +/***************** HARDWARE BUG WORK AROUND ******************/ +/* A burst size of > 4 can cause Sahara DMA to issue invalid AHB transactions + * when crossing 1KB boundaries. By limiting the 'burst size' to 3, these + * invalid transactions will not be generated, but Sahara will still transfer + * data more efficiently than if the burst size were set to 1. + */ + saha_control |= (3 << 16); /* Limit DMA burst size. For versions 2/3 */ +#endif /* USE_3WORD_BURST */ + +#ifdef DIAG_DRV_IF + snprintf(Diag_msg, DIAG_MSG_SIZE, + "Address of SAHARA_BASE_ADDRESS = 0x%08x\n", + SAHARA_BASE_ADDRESS); + LOG_KDIAG(Diag_msg); + snprintf(Diag_msg, DIAG_MSG_SIZE, + "Sahara Status register before reset: %08x", + sah_HW_Read_Status()); + LOG_KDIAG(Diag_msg); +#endif + + /* Write the Reset & BATCH mode command to the SAHARA Command register. */ + sah_HW_Write_Command(CMD_BATCH | CMD_RESET); +#ifdef SAHARA4_NO_USE_SQUIB + { + uint32_t cfg = sah_HW_Read_Config(); + cfg &= ~0x10000; + sah_HW_Write_Config(cfg); + } +#endif + + sah_poll_timeout = 0x0FFFFFFF; + sah_state = sah_Wait_On_Sahara(); +#ifdef DIAG_DRV_IF + snprintf(Diag_msg, DIAG_MSG_SIZE, + "Sahara Status register after reset: %08x", + sah_HW_Read_Status()); + LOG_KDIAG(Diag_msg); +#endif + /* on reset completion, check that Sahara is in the idle state */ + status = (sah_state == SAH_EXEC_IDLE) ? 0 : OS_ERROR_FAIL_S; + + /* Set initial value out of reset */ + sah_HW_Write_Control(saha_control); + +#ifndef NO_RESEED_WORKAROUND +/***************** HARDWARE BUG WORK AROUND ******************/ +/* In order to set the 'auto reseed' bit, must first acquire a random value. */ + /* + * to solve a hardware bug, a random number must be generated before + * the 'RNG Auto Reseed' bit can be set. So this generates a random + * number that is thrown away. + * + * Note that the interrupt bit has not been set at this point so + * the result can be polled. + */ +#ifdef DIAG_DRV_IF + LOG_KDIAG("Create and submit Random Number Descriptor"); +#endif + + if (status == OS_ERROR_OK_S) { + /* place to put random number */ + volatile uint32_t *random_data_ptr; + sah_Head_Desc *random_desc; + dma_addr_t desc_dma; + dma_addr_t rand_dma; + const int rnd_cnt = 3; /* how many random 32-bit values to get */ + + /* Get space for data -- assume at least 32-bit aligned! */ + random_data_ptr = os_alloc_memory(rnd_cnt * sizeof(uint32_t), + GFP_ATOMIC); + + random_desc = sah_Alloc_Head_Descriptor(); + + if ((random_data_ptr == NULL) || (random_desc == NULL)) { + status = OS_ERROR_FAIL_S; + } else { + int i; + + /* Clear out values */ + for (i = 0; i < rnd_cnt; i++) { + random_data_ptr[i] = 0; + } + + rand_dma = os_pa(random_data_ptr); + + random_desc->desc.header = 0xB18C0000; /* LLO get random number */ + random_desc->desc.len1 = + rnd_cnt * sizeof(*random_data_ptr); + random_desc->desc.ptr1 = (void *)rand_dma; + random_desc->desc.original_ptr1 = + (void *)random_data_ptr; + + random_desc->desc.len2 = 0; /* not used */ + random_desc->desc.ptr2 = 0; /* not used */ + + random_desc->desc.next = 0; /* chain terminates here */ + random_desc->desc.original_next = 0; /* chain terminates here */ + + desc_dma = random_desc->desc.dma_addr; + + /* Force in-cache data out to RAM */ + os_cache_clean_range(random_data_ptr, + rnd_cnt * + sizeof(*random_data_ptr)); + + /* pass descriptor to Sahara */ + sah_HW_Write_DAR(desc_dma); + + /* + * Wait for RNG to complete (interrupts are disabled at this point + * due to sahara being reset previously) then check for error + */ + sah_state = sah_Wait_On_Sahara(); + /* Force CPU to ignore in-cache and reload from RAM */ + os_cache_inv_range(random_data_ptr, + rnd_cnt * sizeof(*random_data_ptr)); + + /* if it didn't move to done state, an error occured */ + if ( +#ifndef SUBMIT_MULTIPLE_DARS + (sah_state != SAH_EXEC_IDLE) && +#endif + (sah_state != SAH_EXEC_DONE1) + ) { + status = OS_ERROR_FAIL_S; + os_printk + ("(sahara) Failure: state is %08x; random_data is" + " %08x\n", sah_state, *random_data_ptr); + os_printk + ("(sahara) CDAR: %08x, IDAR: %08x, FADR: %08x," + " ESTAT: %08x\n", sah_HW_Read_CDAR(), + sah_HW_Read_IDAR(), + sah_HW_Read_Fault_Address(), + sah_HW_Read_Error_Status()); + } else { + int i; + int seen_rand = 0; + + for (i = 0; i < rnd_cnt; i++) { + if (*random_data_ptr != 0) { + seen_rand = 1; + break; + } + } + if (!seen_rand) { + status = OS_ERROR_FAIL_S; + os_printk + ("(sahara) Error: Random number is zero!\n"); + } + } + } + + if (random_data_ptr) { + os_free_memory((void *)random_data_ptr); + } + if (random_desc) { + sah_Free_Head_Descriptor(random_desc); + } + } +/***************** END HARDWARE BUG WORK AROUND ******************/ +#endif + + if (status == 0) { +#ifdef FSL_HAVE_SAHARA2 + saha_control |= CTRL_RNG_RESEED; +#endif + +#ifndef SAHARA_POLL_MODE + saha_control |= CTRL_INT_EN; /* enable interrupts */ +#else + sah_poll_timeout = SAHARA_POLL_MODE_TIMEOUT; +#endif + +#ifdef DIAG_DRV_IF + snprintf(Diag_msg, DIAG_MSG_SIZE, + "Setting up Sahara's Control Register: %08x\n", + saha_control); + LOG_KDIAG(Diag_msg); +#endif + + /* Rewrite the setup to the SAHARA Control register */ + sah_HW_Write_Control(saha_control); +#ifdef DIAG_DRV_IF + snprintf(Diag_msg, DIAG_MSG_SIZE, + "Sahara Status register after control write: %08x", + sah_HW_Read_Status()); + LOG_KDIAG(Diag_msg); +#endif + +#ifdef FSL_HAVE_SAHARA4 + { + uint32_t cfg = sah_HW_Read_Config(); + sah_HW_Write_Config(cfg | 0x100); /* Add RNG auto-reseed */ + } +#endif + } else { +#ifdef DIAG_DRV_IF + LOG_KDIAG("Reset failed\n"); +#endif + } + + return status; +} /* sah_HW_Reset() */ + +/*! + * This function enables High Assurance mode. + * + * @brief SAHARA hardware enable High Assurance mode. + * + * @return FSL_RETURN_OK_S - if HA was set successfully + * @return FSL_RETURN_INTERNAL_ERROR_S - if HA was not set due to SAHARA + * being busy. + */ +fsl_shw_return_t sah_HW_Set_HA(void) +{ + /* This is the value to write to the register */ + uint32_t value; + + /* Read from the control register. */ + value = sah_HW_Read_Control(); + + /* Set the HA bit */ + value |= CTRL_HA; + + /* Write to the control register. */ + sah_HW_Write_Control(value); + + /* Read from the control register. */ + value = sah_HW_Read_Control(); + + return (value & CTRL_HA) ? FSL_RETURN_OK_S : + FSL_RETURN_INTERNAL_ERROR_S; +} + +/*! + * This function reads the SAHARA hardware Version Register. + * + * @brief Read SAHARA hardware Version Register. + * + * @return uint32_t Register value. + */ +uint32_t sah_HW_Read_Version(void) +{ + return os_read32(SAHARA_VERSION_REGISTER); +} + +/*! + * This function reads the SAHARA hardware Control Register. + * + * @brief Read SAHARA hardware Control Register. + * + * @return uint32_t Register value. + */ +uint32_t sah_HW_Read_Control(void) +{ + return os_read32(SAHARA_CONTROL_REGISTER); +} + +/*! + * This function reads the SAHARA hardware Status Register. + * + * @brief Read SAHARA hardware Status Register. + * + * @return uint32_t Register value. + */ +uint32_t sah_HW_Read_Status(void) +{ + return os_read32(SAHARA_STATUS_REGISTER); +} + +/*! + * This function reads the SAHARA hardware Error Status Register. + * + * @brief Read SAHARA hardware Error Status Register. + * + * @return uint32_t Error Status value. + */ +uint32_t sah_HW_Read_Error_Status(void) +{ + return os_read32(SAHARA_ESTATUS_REGISTER); +} + +/*! + * This function reads the SAHARA hardware Op Status Register. + * + * @brief Read SAHARA hardware Op Status Register. + * + * @return uint32_t Op Status value. + */ +uint32_t sah_HW_Read_Op_Status(void) +{ + return os_read32(SAHARA_OSTATUS_REGISTER); +} + +/*! + * This function reads the SAHARA hardware Descriptor Address Register. + * + * @brief Read SAHARA hardware DAR Register. + * + * @return uint32_t DAR value. + */ +uint32_t sah_HW_Read_DAR(void) +{ + return os_read32(SAHARA_DAR_REGISTER); +} + +/*! + * This function reads the SAHARA hardware Current Descriptor Address Register. + * + * @brief Read SAHARA hardware CDAR Register. + * + * @return uint32_t CDAR value. + */ +uint32_t sah_HW_Read_CDAR(void) +{ + return os_read32(SAHARA_CDAR_REGISTER); +} + +/*! + * This function reads the SAHARA hardware Initial Descriptor Address Register. + * + * @brief Read SAHARA hardware IDAR Register. + * + * @return uint32_t IDAR value. + */ +uint32_t sah_HW_Read_IDAR(void) +{ + return os_read32(SAHARA_IDAR_REGISTER); +} + +/*! + * This function reads the SAHARA hardware Fault Address Register. + * + * @brief Read SAHARA Fault Address Register. + * + * @return uint32_t Fault Address value. + */ +uint32_t sah_HW_Read_Fault_Address(void) +{ + return os_read32(SAHARA_FLT_ADD_REGISTER); +} + +/*! + * This function reads the SAHARA hardware Multiple Master Status Register. + * + * @brief Read SAHARA hardware MM Stat Register. + * + * @return uint32_t MM Stat value. + */ +uint32_t sah_HW_Read_MM_Status(void) +{ + return os_read32(SAHARA_MM_STAT_REGISTER); +} + +/*! + * This function reads the SAHARA hardware Configuration Register. + * + * @brief Read SAHARA Configuration Register. + * + * @return uint32_t Configuration value. + */ +uint32_t sah_HW_Read_Config(void) +{ + return os_read32(SAHARA_CONFIG_REGISTER); +} + +/*! + * This function writes a command to the SAHARA hardware Command Register. + * + * @brief Write to SAHARA hardware Command Register. + * + * @param command An unsigned 32bit command value. + * + * @return void + */ +void sah_HW_Write_Command(uint32_t command) +{ + os_write32(SAHARA_COMMAND_REGISTER, command); +} + +/*! + * This function writes a control value to the SAHARA hardware Control + * Register. + * + * @brief Write to SAHARA hardware Control Register. + * + * @param control An unsigned 32bit control value. + * + * @return void + */ +void sah_HW_Write_Control(uint32_t control) +{ + os_write32(SAHARA_CONTROL_REGISTER, control); +} + +/*! + * This function writes a configuration value to the SAHARA hardware Configuration + * Register. + * + * @brief Write to SAHARA hardware Configuration Register. + * + * @param configuration An unsigned 32bit configuration value. + * + * @return void + */ +void sah_HW_Write_Config(uint32_t configuration) +{ + os_write32(SAHARA_CONFIG_REGISTER, configuration); +} + +/*! + * This function writes a descriptor address to the SAHARA Descriptor Address + * Register. + * + * @brief Write to SAHARA Descriptor Address Register. + * + * @param pointer An unsigned 32bit descriptor address value. + * + * @return void + */ +void sah_HW_Write_DAR(uint32_t pointer) +{ + os_write32(SAHARA_DAR_REGISTER, pointer); + dar_count++; +} + +#if defined DIAG_DRV_IF || defined DO_DBG + +static char *interpret_header(uint32_t header) +{ + unsigned desc_type = ((header >> 24) & 0x70) | ((header >> 16) & 0xF); + + switch (desc_type) { + case 0x12: + return "5/SKHA_ST_CTX"; + case 0x13: + return "35/SKHA_LD_MODE_KEY"; + case 0x14: + return "38/SKHA_LD_MODE_IN_CPHR_ST_CTX"; + case 0x15: + return "4/SKHA_IN_CPHR_OUT"; + case 0x16: + return "34/SKHA_ST_SBOX"; + case 0x18: + return "1/SKHA_LD_MODE_IV_KEY"; + case 0x19: + return "33/SKHA_ST_SBOX"; + case 0x1D: + return "2/SKHA_LD_MODE_IN_CPHR_OUT"; + case 0x22: + return "11/MDHA_ST_MD"; + case 0x25: + return "10/MDHA_HASH_ST_MD"; + case 0x28: + return "6/MDHA_LD_MODE_MD_KEY"; + case 0x2A: + return "39/MDHA_ICV"; + case 0x2D: + return "8/MDHA_LD_MODE_HASH_ST_MD"; + case 0x3C: + return "18/RNG_GEN"; + case 0x40: + return "19/PKHA_LD_N_E"; + case 0x41: + return "36/PKHA_LD_A3_B0"; + case 0x42: + return "27/PKHA_ST_A_B"; + case 0x43: + return "22/PKHA_LD_A_B"; + case 0x44: + return "23/PKHA_LD_A0_A1"; + case 0x45: + return "24/PKHA_LD_A2_A3"; + case 0x46: + return "25/PKHA_LD_B0_B1"; + case 0x47: + return "26/PKHA_LD_B2_B3"; + case 0x48: + return "28/PKHA_ST_A0_A1"; + case 0x49: + return "29/PKHA_ST_A2_A3"; + case 0x4A: + return "30/PKHA_ST_B0_B1"; + case 0x4B: + return "31/PKHA_ST_B2_B3"; + case 0x4C: + return "32/PKHA_EX_ST_B1"; + case 0x4D: + return "20/PKHA_LD_A_EX_ST_B"; + case 0x4E: + return "21/PKHA_LD_N_EX_ST_B"; + case 0x4F: + return "37/PKHA_ST_B1_B2"; + default: + return "??/UNKNOWN"; + } +} /* cvt_desc_name() */ + +/*! + * Dump chain of descriptors to the log. + * + * @brief Dump descriptor chain + * + * @param chain Kernel virtual address of start of chain of descriptors + * + * @return void + */ +void sah_Dump_Chain(const sah_Desc * chain, dma_addr_t addr) +{ + int desc_no = 1; + + pr_debug("Chain for Sahara\n"); + + while (chain != NULL) { + char desc_name[50]; + + sprintf(desc_name, "Desc %02d (%s)\n" KERN_DEBUG "Desc ", + desc_no++, interpret_header(chain->header)); + + sah_Dump_Words(desc_name, (unsigned *)chain, addr, + 6 /* #words in h/w link */ ); + if (chain->original_ptr1) { + if (chain->header & SAH_HDR_LLO) { + sah_Dump_Region(" Data1", + (unsigned char *)chain-> + original_ptr1, + (dma_addr_t) chain->ptr1, + chain->len1); + } else { + sah_Dump_Link(" Link1", chain->original_ptr1, + (dma_addr_t) chain->ptr1); + } + } + if (chain->ptr2) { + if (chain->header & SAH_HDR_LLO) { + sah_Dump_Region(" Data2", + (unsigned char *)chain-> + original_ptr2, + (dma_addr_t) chain->ptr2, + chain->len2); + } else { + sah_Dump_Link(" Link2", chain->original_ptr2, + (dma_addr_t) chain->ptr2); + } + } + + addr = (dma_addr_t) chain->next; + chain = (chain->next) ? (chain->original_next) : NULL; + } +} + +/*! + * Dump chain of links to the log. + * + * @brief Dump chain of links + * + * @param prefix Text to put in front of dumped data + * @param link Kernel virtual address of start of chain of links + * + * @return void + */ +static void sah_Dump_Link(const char *prefix, const sah_Link * link, + dma_addr_t addr) +{ +#ifdef DUMP_SCC_DATA + extern uint8_t *sahara_partition_base; + extern dma_addr_t sahara_partition_phys; +#endif + + while (link != NULL) { + sah_Dump_Words(prefix, (unsigned *)link, addr, + 3 /* # words in h/w link */ ); + if (link->flags & SAH_STORED_KEY_INFO) { +#ifdef SAH_DUMP_DATA +#ifdef DUMP_SCC_DATA + sah_Dump_Region(" Data", + (uint8_t *) link->data - + (uint8_t *) sahara_partition_phys + + sahara_partition_base, + (dma_addr_t) link->data, link->len); +#else + pr_debug(" Key Slot %d\n", link->slot); +#endif +#endif + } else { +#ifdef SAH_DUMP_DATA + sah_Dump_Region(" Data", link->original_data, + (dma_addr_t) link->data, link->len); +#endif + } + addr = (dma_addr_t) link->next; + link = link->original_next; + } +} + +/*! + * Dump given region of data to the log. + * + * @brief Dump data + * + * @param prefix Text to put in front of dumped data + * @param data Kernel virtual address of start of region to dump + * @param length Amount of data to dump + * + * @return void + */ +void sah_Dump_Region(const char *prefix, const unsigned char *data, + dma_addr_t addr, unsigned length) +{ + unsigned count; + char *output; + unsigned data_len; + + sprintf(Diag_msg, "%s (%08X,%u):", prefix, addr, length); + + /* Restrict amount of data to dump */ + if (length > MAX_DUMP) { + data_len = MAX_DUMP; + } else { + data_len = length; + } + + /* We've already printed some text in output buffer, skip over it */ + output = Diag_msg + strlen(Diag_msg); + + for (count = 0; count < data_len; count++) { + if ((count % 4) == 0) { + *output++ = ' '; + } + sprintf(output, "%02X", *data++); + output += 2; + } + + pr_debug("%s\n", Diag_msg); +} + +/*! + * Dump given word of data to the log. + * + * @brief Dump data + * + * @param prefix Text to put in front of dumped data + * @param data Kernel virtual address of start of region to dump + * @param word_count Amount of data to dump + * + * @return void + */ +void sah_Dump_Words(const char *prefix, const unsigned *data, dma_addr_t addr, + unsigned word_count) +{ + char *output; + + sprintf(Diag_msg, "%s (%08X,%uw): ", prefix, addr, word_count); + + /* We've already printed some text in output buffer, skip over it */ + output = Diag_msg + strlen(Diag_msg); + + while (word_count--) { + sprintf(output, "%08X ", *data++); + output += 9; + } + + pr_debug("%s\n", Diag_msg); + +} + +#endif /* DIAG_DRV_IF */ + +/* End of sah_hardware_interface.c */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/sah_interrupt_handler.c linux-2.6.26-lab126/drivers/mxc/security/sahara2/sah_interrupt_handler.c --- linux-2.6.26/drivers/mxc/security/sahara2/sah_interrupt_handler.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/sah_interrupt_handler.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,216 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! +* @file sah_interrupt_handler.c +* +* @brief Provides a hardware interrupt handling mechanism for device driver. +* +* This file needs to be ported for a non-Linux OS. +* +* It gets a call at #sah_Intr_Init() during initialization. +* +* #sah_Intr_Top_Half() is intended to be the Interrupt Service Routine. It +* calls a portable function in another file to process the Sahara status. +* +* #sah_Intr_Bottom_Half() is a 'background' task scheduled by the top half to +* take care of the expensive tasks of the interrupt processing. +* +* The driver shutdown code calls #sah_Intr_Release(). +* +*/ + +#include + +/* SAHARA Includes */ +#include +#include +#include +#include +#include + +/*Enable this flag for debugging*/ +#if 0 +#define DIAG_DRV_INTERRUPT +#endif + +#ifdef DIAG_DRV_INTERRUPT +#include +#endif + +/*! + * Number of interrupts received. This value should only be updated during + * interrupt processing. + */ +uint32_t interrupt_count; + +#ifndef SAHARA_POLL_MODE + +#if !defined(LINUX_VERSION_CODE) || LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +#define irqreturn_t void +#define IRQ_HANDLED +#define IRQ_RETVAL(x) +#endif + +/* Internal Prototypes */ +static irqreturn_t sah_Intr_Top_Half(int irq, void *dev_id); + +#ifdef KERNEL_TEST +extern void (*SAHARA_INT_PTR) (int, void *); +#endif + +unsigned long reset_flag; +static void sah_Intr_Bottom_Half(unsigned long reset_flag); + +/* This is the Bottom Half Task, (reset flag set to false) */ +DECLARE_TASKLET(BH_task, sah_Intr_Bottom_Half, (unsigned long)&reset_flag); + +/*! This is set by the Initialisation function */ +wait_queue_head_t *int_queue = NULL; + +/*! +******************************************************************************* +* This function registers the Top Half of the interrupt handler with the Kernel +* and the SAHARA IRQ number. +* +* @brief SAHARA Interrupt Handler Initialisation +* +* @param wait_queue Pointer to the wait queue used by driver interface +* +* @return int A return of Zero indicates successful initialisation. +*/ +/****************************************************************************** +* +* CAUTION: NONE +* +* MODIFICATION HISTORY: +* +* Date Person Change +* 30/07/2003 MW Initial Creation +******************************************************************************/ +int sah_Intr_Init(wait_queue_head_t * wait_queue) +{ + +#ifdef DIAG_DRV_INTERRUPT + char err_string[200]; +#endif + + int result; + +#ifdef KERNEL_TEST + SAHARA_INT_PTR = sah_Intr_Top_Half; +#endif + + /* Set queue used by the interrupt handler to match the driver interface */ + int_queue = wait_queue; + + /* Request use of the Interrupt line. */ + result = request_irq(SAHARA_IRQ, + sah_Intr_Top_Half, 0, SAHARA_NAME, NULL); + +#ifdef DIAG_DRV_INTERRUPT + if (result != 0) { + sprintf(err_string, "Cannot use SAHARA interrupt line %d. " + "request_irq() return code is %i.", SAHARA_IRQ, result); + LOG_KDIAG(err_string); + } else { + sprintf(err_string, + "SAHARA driver registered for interrupt %d. ", + SAHARA_IRQ); + LOG_KDIAG(err_string); + } +#endif + + return result; +} + +/*! +******************************************************************************* +* This function releases the Top Half of the interrupt handler. The driver will +* not receive any more interrupts after calling this functions. +* +* @brief SAHARA Interrupt Handler Release +* +* @return void +*/ +/****************************************************************************** +* +* CAUTION: NONE +* +* MODIFICATION HISTORY: +* +* Date Person Change +* 30/07/2003 MW Initial Creation +******************************************************************************/ +void sah_Intr_Release(void) +{ + /* Release the Interrupt. */ + free_irq(SAHARA_IRQ, NULL); +} + +/*! +******************************************************************************* +* This function is the Top Half of the interrupt handler. It updates the +* status of any finished descriptor chains and then tries to add any pending +* requests into the hardware. It then queues the bottom half to complete +* operations on the finished chains. +* +* @brief SAHARA Interrupt Handler Top Half +* +* @param irq Part of the kernel prototype. +* @param dev_id Part of the kernel prototype. +* +* @return An IRQ_RETVAL() -- non-zero to that function means 'handled' +*/ +static irqreturn_t sah_Intr_Top_Half(int irq, void *dev_id) +{ +#if defined(DIAG_DRV_INTERRUPT) && defined(DIAG_DURING_INTERRUPT) + LOG_KDIAG("Top half of Sahara's interrupt handler called."); +#endif + + interrupt_count++; + reset_flag = sah_Handle_Interrupt(sah_HW_Read_Status()); + + /* Schedule the Bottom Half of the Interrupt. */ + tasklet_schedule(&BH_task); + + /* To get rid of the unused parameter warnings. */ + irq = 0; + dev_id = NULL; + return IRQ_RETVAL(1); +} + +/*! +******************************************************************************* +* This function is the Bottom Half of the interrupt handler. It calls +* #sah_postprocess_queue() to complete the processing of the Descriptor Chains +* which were finished by the hardware. +* +* @brief SAHARA Interrupt Handler Bottom Half +* +* @param data Part of the kernel prototype. +* +* @return void +*/ +static void sah_Intr_Bottom_Half(unsigned long reset_flag) +{ +#if defined(DIAG_DRV_INTERRUPT) && defined(DIAG_DURING_INTERRUPT) + LOG_KDIAG("Bottom half of Sahara's interrupt handler called."); +#endif + sah_postprocess_queue(*(unsigned long *)reset_flag); + + return; +} + +/* end of sah_interrupt_handler.c */ +#endif /* ifndef SAHARA_POLL_MODE */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/sah_memory_mapper.c linux-2.6.26-lab126/drivers/mxc/security/sahara2/sah_memory_mapper.c --- linux-2.6.26/drivers/mxc/security/sahara2/sah_memory_mapper.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/sah_memory_mapper.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,2349 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! +* @file sah_memory_mapper.c +* +* @brief Re-creates SAHARA data structures in Kernel memory such that they are +* suitable for DMA. Provides support for kernel API. +* +* This file needs to be ported. +* +* The memory mapper gets a call at #sah_Init_Mem_Map() during driver +* initialization. +* +* The routine #sah_Copy_Descriptors() is used to bring descriptor chains from +* user memory down to kernel memory, relink using physical addresses, and make +* sure that all user data will be accessible by the Sahara DMA. +* #sah_Destroy_Descriptors() does the inverse. +* +* The #sah_Alloc_Block(), #sah_Free_Block(), and #sah_Block_Add_Page() routines +* implement a cache of free blocks used when allocating descriptors and links +* within the kernel. +* +* The memory mapper gets a call at #sah_Stop_Mem_Map() during driver shutdown. +* +*/ + +#include +#include +#include +#include +#ifdef FSL_HAVE_SCC2 +#include +#else +#include +#endif + +#if defined(DIAG_DRV_IF) || defined(DIAG_MEM) || defined(DO_DBG) +#include +#include +#endif + +#include /* get_user_pages() */ +#include +#include + +#include +#include + +#if defined(DIAG_MEM) || defined(DIAG_DRV_IF) +#define DIAG_MSG_SIZE 1024 +static char Diag_msg[DIAG_MSG_SIZE]; +#endif + +#ifdef LINUX_VERSION_CODE +#define FLUSH_SPECIFIC_DATA_ONLY +#else +#define SELF_MANAGED_POOL +#endif + +#if defined(LINUX_VERSION_CODE) +EXPORT_SYMBOL(sah_Alloc_Link); +EXPORT_SYMBOL(sah_Free_Link); +EXPORT_SYMBOL(sah_Alloc_Descriptor); +EXPORT_SYMBOL(sah_Free_Descriptor); +EXPORT_SYMBOL(sah_Alloc_Head_Descriptor); +EXPORT_SYMBOL(sah_Free_Head_Descriptor); +EXPORT_SYMBOL(sah_Physicalise_Descriptors); +EXPORT_SYMBOL(sah_DePhysicalise_Descriptors); +#endif + +/* Determine if L2 cache support should be built in. */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) +#ifdef CONFIG_OUTER_CACHE +#define HAS_L2_CACHE +#endif +#else +#ifdef CONFIG_CPU_CACHE_L210 +#define HAS_L2_CACHE +#endif +#endif + +/* Number of bytes the hardware uses out of sah_Link and sah_*Desc structs */ +#define SAH_HW_LINK_LEN 1 +#define SAH_HW_DESC_LEN 24 + +/* Macros for Descriptors */ +#define SAH_LLO_BIT 0x01000000 +#define sah_Desc_Get_LLO(desc) (desc->header & SAH_LLO_BIT) +#define sah_Desc_Set_Header(desc, h) (desc->header = (h)) + +#define sah_Desc_Get_Next(desc) (desc->next) +#define sah_Desc_Set_Next(desc, n) (desc->next = (n)) + +#define sah_Desc_Get_Ptr1(desc) (desc->ptr1) +#define sah_Desc_Get_Ptr2(desc) (desc->ptr2) +#define sah_Desc_Set_Ptr1(desc,p1) (desc->ptr1 = (p1)) +#define sah_Desc_Set_Ptr2(desc,p2) (desc->ptr2 = (p2)) + +#define sah_Desc_Get_Len1(desc) (desc->len1) +#define sah_Desc_Get_Len2(desc) (desc->len2) +#define sah_Desc_Set_Len1(desc,l1) (desc->len1 = (l1)) +#define sah_Desc_Set_Len2(desc,l2) (desc->len2 = (l2)) + +/* Macros for Links */ +#define sah_Link_Get_Next(link) (link->next) +#define sah_Link_Set_Next(link, n) (link->next = (n)) + +#define sah_Link_Get_Data(link) (link->data) +#define sah_Link_Set_Data(link,d) (link->data = (d)) + +#define sah_Link_Get_Len(link) (link->len) +#define sah_Link_Set_Len(link, l) (link->len = (l)) + +#define sah_Link_Get_Flags(link) (link->flags) + +/* Memory block defines */ +/* Warning! This assumes that kernel version of sah_Link + * is larger than kernel version of sah_Desc. + */ +#define MEM_BLOCK_SIZE sizeof(sah_Link) + +/*! Structure for link/descriptor memory blocks in internal pool */ +typedef struct mem_block { + uint8_t data[MEM_BLOCK_SIZE]; /*!< the actual buffer area */ + struct mem_block *next; /*!< next block when in free chain */ + dma_addr_t dma_addr; /*!< physical address of @a data */ +} Mem_Block; + +#define MEM_BLOCK_ENTRIES (PAGE_SIZE / sizeof(Mem_Block)) + +#define MEM_BIG_BLOCK_SIZE sizeof(sah_Head_Desc) + +/*! Structure for head descriptor memory blocks in internal pool */ +typedef struct mem_big_block { + uint8_t data[MEM_BIG_BLOCK_SIZE]; /*!< the actual buffer area */ + struct mem_big_block *next; /*!< next block when in free chain */ + uint32_t dma_addr; /*!< physical address of @a data */ +} Mem_Big_Block; + +#define MEM_BIG_BLOCK_ENTRIES (PAGE_SIZE / sizeof(Mem_Big_Block)) + +/* Shared variables */ + +/*! + * Lock to protect the memory chain composed of #block_free_head and + * #block_free_tail. + */ +static os_lock_t mem_lock; + +#ifndef SELF_MANAGED_POOL +static struct dma_pool *big_dma_pool = NULL; +static struct dma_pool *small_dma_pool = NULL; +#endif + +#ifdef SELF_MANAGED_POOL +/*! + * Memory block free pool - pointer to first block. Chain is protected by + * #mem_lock. + */ +static Mem_Block *block_free_head = NULL; +/*! + * Memory block free pool - pointer to last block. Chain is protected by + * #mem_lock. + */ +static Mem_Block *block_free_tail = NULL; +/*! + * Memory block free pool - pointer to first block. Chain is protected by + * #mem_lock. + */ +static Mem_Big_Block *big_block_free_head = NULL; +/*! + * Memory block free pool - pointer to last block. Chain is protected by + * #mem_lock. +a */ +static Mem_Big_Block *big_block_free_tail = NULL; +#endif /* SELF_MANAGED_POOL */ + +static Mem_Block *sah_Alloc_Block(void); +static void sah_Free_Block(Mem_Block * block); +static Mem_Big_Block *sah_Alloc_Big_Block(void); +static void sah_Free_Big_Block(Mem_Big_Block * block); +#ifdef SELF_MANAGED_POOL +static void sah_Append_Block(Mem_Block * block); +static void sah_Append_Big_Block(Mem_Big_Block * block); +#endif /* SELF_MANAGED_POOL */ + +/* Page context structure. Used by wire_user_memory and unwire_user_memory */ +typedef struct page_ctx_t { + uint32_t count; + struct page **local_pages; +} page_ctx_t; + +/*! +******************************************************************************* +* Map and wire down a region of user memory. +* +* +* @param address Userspace address of the memory to wire +* @param length Length of the memory region to wire +* @param page_ctx Page context, to be passed to unwire_user_memory +* +* @return (if successful) Kernel virtual address of the wired pages +*/ +void *wire_user_memory(void *address, uint32_t length, void **page_ctx) +{ + void *kernel_black_addr = NULL; + int result = -1; + int page_index = 0; + page_ctx_t *page_context; + int nr_pages = 0; + unsigned long start_page; + fsl_shw_return_t status; + + /* Determine the number of pages being used for this link */ + nr_pages = (((unsigned long)(address) & ~PAGE_MASK) + + length + ~PAGE_MASK) >> PAGE_SHIFT; + + start_page = (unsigned long)(address) & PAGE_MASK; + + /* Allocate some memory to keep track of the wired user pages, so that + * they can be deallocated later. The block of memory will contain both + * the structure and the array of pages. + */ + page_context = kmalloc(sizeof(page_ctx_t) + + nr_pages * sizeof(struct page *), GFP_KERNEL); + + if (page_context == NULL) { + status = FSL_RETURN_NO_RESOURCE_S; /* no memory! */ +#ifdef DIAG_DRV_IF + LOG_KDIAG("kmalloc() failed."); +#endif + return NULL; + } + + /* Set the page pointer to point to the allocated region of memory */ + page_context->local_pages = (void *)page_context + sizeof(page_ctx_t); + +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS("page_context at: %p, local_pages at: %p", + (void *)page_context, + (void *)(page_context->local_pages)); +#endif + + /* Wire down the pages from user space */ + down_read(¤t->mm->mmap_sem); + result = get_user_pages(current, current->mm, + start_page, nr_pages, WRITE, 0 /* noforce */ , + (page_context->local_pages), NULL); + up_read(¤t->mm->mmap_sem); + + if (result < nr_pages) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("get_user_pages() failed."); +#endif + if (result > 0) { + for (page_index = 0; page_index < result; page_index++) { + page_cache_release((page_context-> + local_pages[page_index])); + } + + kfree(page_context); + } + return NULL; + } + + kernel_black_addr = page_address(page_context->local_pages[0]) + + ((unsigned long)address & ~PAGE_MASK); + + page_context->count = nr_pages; + *page_ctx = page_context; + + return kernel_black_addr; +} + +/*! +******************************************************************************* +* Release and unmap a region of user memory. +* +* @param page_ctx Page context from wire_user_memory +*/ +void unwire_user_memory(void **page_ctx) +{ + int page_index = 0; + struct page_ctx_t *page_context = *page_ctx; + +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS("page_context at: %p, first page at:%p, count: %i", + (void *)page_context, + (void *)(page_context->local_pages), + page_context->count); +#endif + + if ((page_context != NULL) && (page_context->local_pages != NULL)) { + for (page_index = 0; page_index < page_context->count; + page_index++) { + page_cache_release(page_context-> + local_pages[page_index]); + } + + kfree(page_context); + *page_ctx = NULL; + } +} + +/*! +******************************************************************************* +* Map some physical memory into a users memory space +* +* @param vma Memory structure to map to +* @param physical_addr Physical address of the memory to be mapped in +* @param size Size of the memory to map (bytes) +* +* @return +*/ +os_error_code +map_user_memory(struct vm_area_struct *vma, uint32_t physical_addr, + uint32_t size) +{ + os_error_code retval; + + /* Map the acquired partition into the user's memory space */ + vma->vm_end = vma->vm_start + size; + + /* set cache policy to uncached so that each write of the UMID and + * permissions get directly to the SCC2 in order to engage it + * properly. Once the permissions have been written, it may be + * useful to provide a service for the user to request a different + * cache policy + */ + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + /* Make sure that the user cannot fork() a child which will inherit + * this mapping, as it creates a security hole. Likewise, do not + * allow the user to 'expand' his mapping beyond this partition. + */ + vma->vm_flags |= VM_IO | VM_RESERVED | VM_DONTCOPY | VM_DONTEXPAND; + + retval = remap_pfn_range(vma, + vma->vm_start, + __phys_to_pfn(physical_addr), + size, vma->vm_page_prot); + + return retval; +} + +/*! +******************************************************************************* +* Remove some memory from a user's memory space +* +* @param user_addr Userspace address of the memory to be unmapped +* @param size Size of the memory to map (bytes) +* +* @return +*/ +os_error_code unmap_user_memory(uint32_t user_addr, uint32_t size) +{ + os_error_code retval; + struct mm_struct *mm = current->mm; + + /* Unmap the memory region (see sys_munmap in mmap.c) */ + down_write(&mm->mmap_sem); + retval = do_munmap(mm, (unsigned long)user_addr, size); + up_write(&mm->mmap_sem); + + return retval; +} + +/*! +******************************************************************************* +* Free descriptor back to free pool +* +* @brief Free descriptor +* +* @param desc A descriptor allocated with sah_Alloc_Descriptor(). +* +* @return none +* +*/ +void sah_Free_Descriptor(sah_Desc * desc) +{ + memset(desc, 0x45, sizeof(*desc)); + sah_Free_Block((Mem_Block *) desc); +} + +/*! +******************************************************************************* +* Free Head descriptor back to free pool +* +* @brief Free Head descriptor +* +* @param desc A Head descriptor allocated with sah_Alloc_Head_Descriptor(). +* +* @return none +* +*/ +void sah_Free_Head_Descriptor(sah_Head_Desc * desc) +{ + memset(desc, 0x43, sizeof(*desc)); + sah_Free_Big_Block((Mem_Big_Block *) desc); +} + +/*! +******************************************************************************* +* Free link back to free pool +* +* @brief Free link +* +* @param link A link allocated with sah_Alloc_Link(). +* +* @return none +* +*/ +void sah_Free_Link(sah_Link * link) +{ + memset(link, 0x41, sizeof(*link)); + sah_Free_Block((Mem_Block *) link); +} + +/*! +******************************************************************************* +* This function runs through a descriptor chain pointed to by a user-space +* address. It duplicates each descriptor in Kernel space memory and calls +* sah_Copy_Links() to handle any links attached to the descriptors. This +* function cleans-up everything that it created in the case of a failure. +* +* @brief Kernel Descriptor Chain Copier +* +* @param fsl_shw_uco_t The user context to act under +* @param user_head_desc A Head Descriptor pointer from user-space. +* +* @return sah_Head_Desc * - A virtual address of the first descriptor in the +* chain. +* @return NULL - If there was some error. +* +*/ +sah_Head_Desc *sah_Copy_Descriptors(fsl_shw_uco_t * user_ctx, + sah_Head_Desc * user_head_desc) +{ + sah_Desc *curr_desc = NULL; + sah_Desc *prev_desc = NULL; + sah_Desc *next_desc = NULL; + sah_Head_Desc *head_desc = NULL; + sah_Desc *user_desc = NULL; + unsigned long result; + + /* Internal status variable to be used in this function */ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Head_Desc *ret_val = NULL; + + /* This will be set to True when we have finished processing our + * descriptor chain. + */ + int drv_if_done = FALSE; + int is_this_the_head = TRUE; + + do { + /* Allocate memory for this descriptor */ + if (is_this_the_head) { + head_desc = + (sah_Head_Desc *) sah_Alloc_Head_Descriptor(); + +#ifdef DIAG_MEM + sprintf(Diag_msg, + "Alloc_Head_Descriptor returned %p\n", + head_desc); + LOG_KDIAG(Diag_msg); +#endif + if (head_desc == NULL) { +#ifdef DIAG_DRV_IF + LOG_KDIAG + ("sah_Alloc_Head_Descriptor() failed."); +#endif + drv_if_done = TRUE; + status = FSL_RETURN_NO_RESOURCE_S; + } else { + void *virt_addr = head_desc->desc.virt_addr; + dma_addr_t dma_addr = head_desc->desc.dma_addr; + + /* Copy the head descriptor from user-space */ + /* Instead of copying the whole structure, + * unneeded bits at the end are left off. + * The user space version is missing virt/dma addrs, which + * means that the copy will be off for flags... */ + result = copy_from_user(head_desc, + user_head_desc, + (sizeof(*head_desc) - + sizeof(head_desc->desc. + dma_addr) - + sizeof(head_desc->desc. + virt_addr) - + sizeof(head_desc->desc. + original_ptr1) - +/* sizeof(head_desc->desc.original_ptr2) - + sizeof(head_desc->status) - + sizeof(head_desc->error_status) - + sizeof(head_desc->fault_address) - + sizeof(head_desc->current_dar) - + sizeof(head_desc->result) - + sizeof(head_desc->next) - + sizeof(head_desc->prev) - + sizeof(head_desc->user_desc) - +*/ sizeof(head_desc->out1_ptr) - + sizeof(head_desc-> + out2_ptr) - + sizeof(head_desc-> + out_len))); + /* there really isn't a 'next' descriptor at this point, so + * set that pointer to NULL, but remember it for if/when there + * is a next */ + next_desc = head_desc->desc.next; + head_desc->desc.next = NULL; + + if (result != 0) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("copy_from_user() failed."); +#endif + drv_if_done = TRUE; + status = FSL_RETURN_INTERNAL_ERROR_S; + /* when destroying the descriptor, skip these links. + * They've not been copied down, so don't exist */ + head_desc->desc.ptr1 = NULL; + head_desc->desc.ptr2 = NULL; + + } else { + /* The kernel DESC has five more words than user DESC, so + * the missing values are in the middle of the HEAD DESC, + * causing values after the missing ones to be at different + * offsets in kernel and user space. + * + * Patch up the problem by moving field two spots. + * This assumes sizeof(pointer) == sizeof(uint32_t). + * Note that 'user_info' is not needed, so not copied. + */ + head_desc->user_ref = + (uint32_t) head_desc->desc.dma_addr; + head_desc->uco_flags = + (uint32_t) head_desc->desc. + original_ptr1; +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS( + "User flags: %x; User Reference: %x", + head_desc->uco_flags, + head_desc->user_ref); +#endif + /* These values were destroyed by the copy. */ + head_desc->desc.virt_addr = virt_addr; + head_desc->desc.dma_addr = dma_addr; + + /* ensure that the save descriptor chain bit is not set. + * the copy of the user space descriptor chain should + * always be deleted */ + head_desc->uco_flags &= + ~FSL_UCO_SAVE_DESC_CHAIN; + + curr_desc = (sah_Desc *) head_desc; + is_this_the_head = FALSE; + } + } + } else { /* not head */ + curr_desc = sah_Alloc_Descriptor(); +#ifdef DIAG_MEM + LOG_KDIAG_ARGS("Alloc_Descriptor returned %p\n", + curr_desc); +#endif + if (curr_desc == NULL) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("sah_Alloc_Descriptor() failed."); +#endif + drv_if_done = TRUE; + status = FSL_RETURN_NO_RESOURCE_S; + } else { + /* need to update the previous descriptors' next field to + * pointer to the current descriptor. */ + prev_desc->original_next = curr_desc; + prev_desc->next = + (sah_Desc *) curr_desc->dma_addr; + + /* Copy the current descriptor from user-space */ + /* The virtual address and DMA address part of the sah_Desc + * struct are not copied to user space */ + result = copy_from_user(curr_desc, user_desc, (sizeof(sah_Desc) - sizeof(dma_addr_t) - /* dma_addr */ + sizeof(uint32_t) - /* virt_addr */ + sizeof(void *) - /* original_ptr1 */ + sizeof(void *) - /* original_ptr2 */ + sizeof(sah_Desc **))); /* original_next */ + /* there really isn't a 'next' descriptor at this point, so + * set that pointer to NULL, but remember it for if/when there + * is a next */ + next_desc = curr_desc->next; + curr_desc->next = NULL; + curr_desc->original_next = NULL; + + if (result != 0) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("copy_from_user() failed."); +#endif + drv_if_done = TRUE; + status = FSL_RETURN_INTERNAL_ERROR_S; + /* when destroying the descriptor chain, skip these links. + * They've not been copied down, so don't exist */ + curr_desc->ptr1 = NULL; + curr_desc->ptr2 = NULL; + } + } + } /* end if (is_this_the_head) */ + + if (status == FSL_RETURN_OK_S) { + if (!(curr_desc->header & SAH_LLO_BIT)) { + /* One or both pointer fields being NULL is a valid + * configuration. */ + if (curr_desc->ptr1 == NULL) { + curr_desc->original_ptr1 = NULL; + } else { + /* pointer fields point to sah_Link structures */ + curr_desc->original_ptr1 = + sah_Copy_Links(user_ctx, curr_desc->ptr1); + if (curr_desc->original_ptr1 == NULL) { + /* This descriptor and any links created successfully + * are cleaned-up at the bottom of this function. */ + drv_if_done = TRUE; + status = + FSL_RETURN_INTERNAL_ERROR_S; + /* mark that link 2 doesn't exist */ + curr_desc->ptr2 = NULL; +#ifdef DIAG_DRV_IF + LOG_KDIAG + ("sah_Copy_Links() failed."); +#endif + } else { + curr_desc->ptr1 = (void *) + ((sah_Link *) curr_desc-> + original_ptr1)->dma_addr; + } + } + + if (status == FSL_RETURN_OK_S) { + if (curr_desc->ptr2 == NULL) { + curr_desc->original_ptr2 = NULL; + } else { + /* pointer fields point to sah_Link structures */ + curr_desc->original_ptr2 = + sah_Copy_Links(user_ctx, curr_desc->ptr2); + if (curr_desc->original_ptr2 == + NULL) { + /* This descriptor and any links created + * successfully are cleaned-up at the bottom of + * this function. */ + drv_if_done = TRUE; + status = + FSL_RETURN_INTERNAL_ERROR_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG + ("sah_Copy_Links() failed."); +#endif + } else { + curr_desc->ptr2 = + (void + *)(((sah_Link *) + curr_desc-> + original_ptr2) + ->dma_addr); + } + } + } + } else { + /* Pointer fields point directly to user buffers. We don't + * support this mode. + */ +#ifdef DIAG_DRV_IF + LOG_KDIAG + ("The LLO bit in the Descriptor Header field was " + "set. This an invalid configuration."); +#endif + drv_if_done = TRUE; + status = FSL_RETURN_INTERNAL_ERROR_S; + } + } + + if (status == FSL_RETURN_OK_S) { + user_desc = next_desc; + prev_desc = curr_desc; + if (user_desc == NULL) { + /* We have reached the end our our descriptor chain */ + drv_if_done = TRUE; + } + } + + } while (drv_if_done == FALSE); + + if (status != FSL_RETURN_OK_S) { + /* Clean-up if failed */ + if (head_desc != NULL) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("Error! Calling destroy descriptors!\n"); +#endif + sah_Destroy_Descriptors(head_desc); + } + ret_val = NULL; + } else { + /* Flush the caches */ +#ifndef FLUSH_SPECIFIC_DATA_ONLY + os_flush_cache_all(); +#endif + + /* Success. Return the DMA'able head descriptor. */ + ret_val = head_desc; + + } + + return ret_val; +} /* sah_Copy_Descriptors() */ + +/*! +******************************************************************************* +* This function runs through a sah_Link chain pointed to by a kernel-space +* address. It computes the physical address for each pointer, and converts +* the chain to use these physical addresses. +* +****** +* This function needs to return some indication that the chain could not be +* converted. It also needs to back out any conversion already taken place on +* this chain of links. +* +* Then, of course, sah_Physicalise_Descriptors() will need to recognize that +* an error occured, and then be able to back out any physicalization of the +* chain which had taken place up to that point! +****** +* +* @brief Convert kernel Link chain +* +* @param first_link A sah_Link pointer from kernel space; must not be +* NULL, so error case can be distinguished. +* +* @return sah_Link * A dma'able address of the first descriptor in the +* chain. +* @return NULL If Link chain could not be physicalised, i.e. ERROR +* +*/ +sah_Link *sah_Physicalise_Links(sah_Link * first_link) +{ + sah_Link *link = first_link; + + while (link != NULL) { +#ifdef DO_DBG + sah_Dump_Words("Link", (unsigned *)link, link->dma_addr, 3); +#endif + link->vm_info = NULL; + + /* need to retrieve stored key? */ + if (link->flags & SAH_STORED_KEY_INFO) { + uint32_t max_len = 0; /* max slot length */ + fsl_shw_return_t ret_status; + + /* get length and physical address of stored key */ + ret_status = system_keystore_get_slot_info(link->ownerid, link->slot, (uint32_t *) & link->data, /* RED key address */ + &max_len); + if ((ret_status != FSL_RETURN_OK_S) || (link->len > max_len)) { + /* trying to illegally/incorrectly access a key. Cause the + * error status register to show a Link Length Error by + * putting a zero in the links length. */ + link->len = 0; /* Cause error. Somebody is up to no good. */ + } + } else if (link->flags & SAH_IN_USER_KEYSTORE) { + +#ifdef FSL_HAVE_SCC2 + /* The data field points to the virtual address of the key. Convert + * this to a physical address by modifying the address based + * on where the secure memory was mapped to the kernel. Note: In + * kernel mode, no attempt is made to track or control who owns what + * memory partition. + */ + link->data = (uint8_t *) scc_virt_to_phys(link->data); + + /* Do bounds checking to ensure that the user is not overstepping + * the bounds of their partition. This is a simple implementation + * that assumes the user only owns one partition. It only checks + * to see if the address of the last byte of data steps over a + * page boundary. + */ + +#ifdef DO_DBG + LOG_KDIAG_ARGS("start page: %08x, end page: %08x" + "first addr: %p, last addr: %p, len; %i", + ((uint32_t) (link->data) >> PAGE_SHIFT), + (((uint32_t) link->data + + link->len) >> PAGE_SHIFT), link->data, + link->data + link->len, link->len); +#endif + + if ((((uint32_t) link->data + + link->len) >> PAGE_SHIFT) != + ((uint32_t) link->data >> PAGE_SHIFT)) { + link->len = 0; /* Cause error. Somebody is up to no good. */ + } +#else /* FSL_HAVE_SCC2 */ + + /* User keystores are not valid on non-SCC2 platforms */ + link->len = 0; /* Cause error. Somebody is up to no good. */ + +#endif /* FSL_HAVE_SCC2 */ + + } else { + if (!(link->flags & SAH_PREPHYS_DATA)) { + link->original_data = link->data; + + /* All pointers are virtual right now */ + link->data = (void *)os_pa(link->data); +#ifdef DO_DBG + os_printk("%sput: %p (%d)\n", + (link-> + flags & SAH_OUTPUT_LINK) ? "out" : + "in", link->data, link->len); +#endif + + if (link->flags & SAH_OUTPUT_LINK) { + /* clean and invalidate */ + os_cache_flush_range(link-> + original_data, + link->len); + } else { + os_cache_clean_range(link->original_data, + link->len); + } + } /* not prephys */ + } /* else not key reference */ + +#if defined(NO_OUTPUT_1K_CROSSING) || defined(NO_1K_CROSSING) + if ( +#ifdef NO_OUTPUT_1K_CROSSING + /* Insert extra link if 1k boundary on output pointer + * crossed not at an 8-word boundary */ + (link->flags & SAH_OUTPUT_LINK) && + (((uint32_t) link->data % 32) != 0) && +#endif + ((((uint32_t) link->data & 1023) + link->len) > + 1024)) { + uint32_t full_length = link->len; + sah_Link *new_link = sah_Alloc_Link(); + link->len = 1024 - ((uint32_t) link->data % 1024); + new_link->len = full_length - link->len; + new_link->data = link->data + link->len; + new_link->original_data = + link->original_data + link->len; + new_link->flags = link->flags & ~(SAH_OWNS_LINK_DATA); + new_link->flags |= SAH_LINK_INSERTED_LINK; + new_link->next = link->next; + + link->next = (sah_Link *) new_link->dma_addr; + link->original_next = new_link; + link = new_link; + } +#endif /* ALLOW_OUTPUT_1K_CROSSING */ + + link->original_next = link->next; + if (link->next != NULL) { + link->next = (sah_Link *) link->next->dma_addr; + } +#ifdef DO_DBG + sah_Dump_Words("Link", link, link->dma_addr, 3); +#endif + + link = link->original_next; + } + + return (sah_Link *) first_link->dma_addr; +} /* sah_Physicalise_Links */ + +/*! + * Run through descriptors and links created by KM-API and set the + * dma addresses and 'do not free' flags. + * + * @param first_desc KERNEL VIRTUAL address of first descriptor in chain. + * + * Warning! This ONLY works without LLO flags in headers!!! + * + * @return Virtual address of @a first_desc. + * @return NULL if Descriptor Chain could not be physicalised + */ +sah_Head_Desc *sah_Physicalise_Descriptors(sah_Head_Desc * first_desc) +{ + sah_Desc *desc = &first_desc->desc; + + if (!(first_desc->uco_flags & FSL_UCO_CHAIN_PREPHYSICALIZED)) { + while (desc != NULL) { + sah_Desc *next_desc; + +#ifdef DO_DBG + + sah_Dump_Words("Desc", (unsigned *)desc, desc->dma_addr, 6); +#endif + + desc->original_ptr1 = desc->ptr1; + if (desc->ptr1 != NULL) { + if ((desc->ptr1 = + sah_Physicalise_Links(desc->ptr1)) == + NULL) { + /* Clean up ... */ + sah_DePhysicalise_Descriptors + (first_desc); + first_desc = NULL; + break; + } + } + desc->original_ptr2 = desc->ptr2; + if (desc->ptr2 != NULL) { + if ((desc->ptr2 = + sah_Physicalise_Links(desc->ptr2)) == + NULL) { + /* Clean up ... */ + sah_DePhysicalise_Descriptors + (first_desc); + first_desc = NULL; + break; + } + } + + desc->original_next = desc->next; + next_desc = desc->next; /* save for bottom of while loop */ + if (desc->next != NULL) { + desc->next = (sah_Desc *) desc->next->dma_addr; + } + + desc = next_desc; + } + } + /* not prephysicalized */ +#ifdef DO_DBG + os_printk("Physicalise finished\n"); +#endif + + return first_desc; +} /* sah_Physicalise_Descriptors() */ + +/*! +******************************************************************************* +* This function runs through a sah_Link chain pointed to by a physical address. +* It computes the virtual address for each pointer +* +* @brief Convert physical Link chain +* +* @param first_link A kernel address of a sah_Link +* +* @return sah_Link * A kernal address for the link chain of @c first_link +* @return NULL If there was some error. +* +* @post All links will be chained together by original virtual addresses, +* data pointers will point to virtual addresses. Appropriate cache +* lines will be flushed, memory unwired, etc. +*/ +sah_Link *sah_DePhysicalise_Links(sah_Link * first_link) +{ + sah_Link *link = first_link; + sah_Link *prev_link = NULL; + + /* Loop on virtual link pointer */ + while (link != NULL) { + +#ifdef DO_DBG + sah_Dump_Words("Link", (unsigned *)link, link->dma_addr, 3); +#endif + + /* if this references stored keys, don't want to dephysicalize them */ + if (!(link->flags & SAH_STORED_KEY_INFO) + && !(link->flags & SAH_PREPHYS_DATA) + && !(link->flags & SAH_IN_USER_KEYSTORE)) { + + /* */ + if (link->flags & SAH_OUTPUT_LINK) { + os_cache_inv_range(link->original_data, + link->len); + } + + /* determine if there is a page in user space associated with this + * link */ + if (link->vm_info != NULL) { + /* check that this isn't reserved and contains output */ + if (!PageReserved(link->vm_info) && + (link->flags & SAH_OUTPUT_LINK)) { + + /* Mark to force page eventually to backing store */ + SetPageDirty(link->vm_info); + } + + /* Untie this page from physical memory */ + page_cache_release(link->vm_info); + } else { + /* kernel-mode data */ +#ifdef DO_DBG + os_printk("%sput: %p (%d)\n", + (link-> + flags & SAH_OUTPUT_LINK) ? "out" : + "in", link->original_data, link->len); +#endif + } + link->data = link->original_data; + } +#ifndef ALLOW_OUTPUT_1K_CROSSING + if (link->flags & SAH_LINK_INSERTED_LINK) { + /* Reconsolidate data by merging this link with previous */ + prev_link->len += link->len; + prev_link->next = link->next; + prev_link->original_next = link->original_next; + sah_Free_Link(link); + link = prev_link; + + } +#endif + + if (link->next != NULL) { + link->next = link->original_next; + } + prev_link = link; + link = link->next; + } + + return first_link; +} /* sah_DePhysicalise_Links() */ + +/*! + * Run through descriptors and links that have been Physicalised + * (sah_Physicalise_Descriptors function) and set the dma addresses back + * to KM virtual addresses + * + * @param first_desc Kernel virtual address of first descriptor in chain. + * + * Warning! This ONLY works without LLO flags in headers!!! + */ +sah_Head_Desc *sah_DePhysicalise_Descriptors(sah_Head_Desc * first_desc) +{ + sah_Desc *desc = &first_desc->desc; + + if (!(first_desc->uco_flags & FSL_UCO_CHAIN_PREPHYSICALIZED)) { + while (desc != NULL) { +#ifdef DO_DBG + sah_Dump_Words("Desc", (unsigned *)desc, desc->dma_addr, 6); +#endif + + if (desc->ptr1 != NULL) { + desc->ptr1 = + sah_DePhysicalise_Links(desc-> + original_ptr1); + } + if (desc->ptr2 != NULL) { + desc->ptr2 = + sah_DePhysicalise_Links(desc-> + original_ptr2); + } + if (desc->next != NULL) { + desc->next = desc->original_next; + } + desc = desc->next; + } + } + /* not prephysicalized */ + return first_desc; +} /* sah_DePhysicalise_Descriptors() */ + +/*! +******************************************************************************* +* This walks through a SAHARA descriptor chain and free()'s everything +* that is not NULL. Finally it also unmaps all of the physical memory and +* frees the kiobuf_list Queue. +* +* @brief Kernel Descriptor Chain Destructor +* +* @param head_desc A Descriptor pointer from kernel-space. +* +* @return void +* +*/ +void sah_Free_Chained_Descriptors(sah_Head_Desc * head_desc) +{ + sah_Desc *desc = NULL; + sah_Desc *next_desc = NULL; + int this_is_head = 1; + + desc = &head_desc->desc; + + while (desc != NULL) { + + sah_Free_Chained_Links(desc->ptr1); + sah_Free_Chained_Links(desc->ptr2); + + /* Get a bus pointer to the next Descriptor */ + next_desc = desc->next; + + /* Zero the header and Length fields for security reasons. */ + desc->header = 0; + desc->len1 = 0; + desc->len2 = 0; + + if (this_is_head) { + sah_Free_Head_Descriptor(head_desc); + this_is_head = 0; +#ifdef DIAG_MEM + sprintf(Diag_msg, "Free_Head_Descriptor: %p\n", + head_desc); + LOG_KDIAG(Diag_msg); +#endif + } else { + /* free this descriptor */ + sah_Free_Descriptor(desc); +#ifdef DIAG_MEM + sprintf(Diag_msg, "Free_Descriptor: %p\n", desc); + LOG_KDIAG(Diag_msg); +#endif + } + + /* Look at the next Descriptor */ + desc = next_desc; + } +} /* sah_Free_Chained_Descriptors() */ + +/*! +******************************************************************************* +* This walks through a SAHARA link chain and frees everything that is +* not NULL, excluding user-space buffers. +* +* @brief Kernel Link Chain Destructor +* +* @param link A Link pointer from kernel-space. This is in bus address +* space. +* +* @return void +* +*/ +void sah_Free_Chained_Links(sah_Link * link) +{ + sah_Link *next_link = NULL; + + while (link != NULL) { + /* Get a bus pointer to the next Link */ + next_link = link->next; + + /* Zero some fields for security reasons. */ + link->data = NULL; + link->len = 0; + link->ownerid = 0; + + /* Free this Link */ +#ifdef DIAG_MEM + sprintf(Diag_msg, "Free_Link: %p(->%p)\n", link, link->next); + LOG_KDIAG(Diag_msg); +#endif + sah_Free_Link(link); + + /* Move on to the next Link */ + link = next_link; + } +} + +/*! +******************************************************************************* +* This function runs through a link chain pointed to by a user-space +* address. It makes a temporary kernel-space copy of each link in the +* chain and calls sah_Make_Links() to create a set of kernel-side links +* to replace it. +* +* @brief Kernel Link Chain Copier +* +* @param ptr A link pointer from user-space. +* +* @return sah_Link * - The virtual address of the first link in the +* chain. +* @return NULL - If there was some error. +*/ +sah_Link *sah_Copy_Links(fsl_shw_uco_t * user_ctx, sah_Link * ptr) +{ + sah_Link *head_link = NULL; + sah_Link *new_head_link = NULL; + sah_Link *new_tail_link = NULL; + sah_Link *prev_tail_link = NULL; + sah_Link *user_link = ptr; + sah_Link link_copy; + int link_data_length = 0; + + /* Internal status variable to be used in this function */ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Link *ret_val = NULL; + + /* This will be set to True when we have finished processing our + * link chain. */ + int drv_if_done = FALSE; + int is_this_the_head = TRUE; + int result; + + /* transfer all links, on this link chain, from user space */ + while (drv_if_done == FALSE) { + /* Copy the current link from user-space. The virtual address, DMA + * address, and vm_info fields of the sah_Link struct are not part + * of the user-space structure. They must be the last elements and + * should not be copied. */ + result = copy_from_user(&link_copy, + user_link, (sizeof(sah_Link) - +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) + sizeof(struct page *) - /* vm_info */ +#endif + sizeof(dma_addr_t) - /* dma_addr */ + sizeof(uint32_t) - /* virt_addr */ + sizeof(uint8_t *) - /* original_data */ + sizeof(sah_Link *))); /* original_next */ + + if (result != 0) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("copy_from_user() failed."); +#endif + drv_if_done = TRUE; + status = FSL_RETURN_INTERNAL_ERROR_S; + } + + if (status == FSL_RETURN_OK_S) { + /* This will create new links which can be used to replace tmp_link + * in the chain. This will return a new head and tail link. */ + link_data_length = link_data_length + link_copy.len; + new_head_link = + sah_Make_Links(user_ctx, &link_copy, &new_tail_link); + + if (new_head_link == NULL) { + /* If we ran out of memory or a user pointer was invalid */ + drv_if_done = TRUE; + status = FSL_RETURN_INTERNAL_ERROR_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("sah_Make_Links() failed."); +#endif + } else { + if (is_this_the_head == TRUE) { + /* Keep a reference to the head link */ + head_link = new_head_link; + is_this_the_head = FALSE; + } else { + /* Need to update the previous links' next field to point + * to the current link. */ + prev_tail_link->next = + (void *)new_head_link->dma_addr; + prev_tail_link->original_next = + new_head_link; + } + } + } + + if (status == FSL_RETURN_OK_S) { + /* Get to the next link in the chain. */ + user_link = link_copy.next; + prev_tail_link = new_tail_link; + + /* Check if the end of the link chain was reached (TRUE) or if + * there is another linked to this one (FALSE) */ + drv_if_done = (user_link == NULL) ? TRUE : FALSE; + } + } /* end while */ + + if (status != FSL_RETURN_OK_S) { + ret_val = NULL; + /* There could be clean-up to do here because we may have made some + * successful iterations through the while loop and as a result, the + * links created by sah_Make_Links() need to be destroyed. + */ + if (head_link != NULL) { + /* Failed somewhere in the while loop and need to clean-up. */ + sah_Destroy_Links(head_link); + } + } else { + /* Success. Return the head link. */ + ret_val = head_link; + } + + return ret_val; +} /* sah_Copy_Links() */ + +/*! +******************************************************************************* +* This function takes an input link pointed to by a user-space address +* and returns a chain of links that span the physical pages pointed +* to by the input link. +* +* @brief Kernel Link Chain Constructor +* +* @param ptr A link pointer from user-space. +* @param tail The address of a link pointer. This is used to return +* the tail link created by this function. +* +* @return sah_Link * - A virtual address of the first link in the +* chain. +* @return NULL - If there was some error. +* +*/ +sah_Link *sah_Make_Links(fsl_shw_uco_t * user_ctx, + sah_Link * ptr, sah_Link ** tail) +{ + int result = -1; + int page_index = 0; + fsl_shw_return_t status = FSL_RETURN_OK_S; + int is_this_the_head = TRUE; + void *buffer_start = NULL; + sah_Link *link = NULL; + sah_Link *prev_link = NULL; + sah_Link *head_link = NULL; + sah_Link *ret_val = NULL; + int buffer_length = 0; + struct page **local_pages = NULL; + int nr_pages = 0; + int write = (sah_Link_Get_Flags(ptr) & SAH_OUTPUT_LINK) ? WRITE : READ; + + /* need to retrieve stored key? */ + if (ptr->flags & SAH_STORED_KEY_INFO) { + fsl_shw_return_t ret_status; + + /* allocate space for this link */ + link = sah_Alloc_Link(); +#ifdef DIAG_MEM + sprintf(Diag_msg, "Alloc_Link returned %p/%p\n", link, + (void *)link->dma_addr); + LOG_KDIAG(Diag_msg); +#endif + + if (link == NULL) { + status = FSL_RETURN_NO_RESOURCE_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("sah_Alloc_Link() failed!"); +#endif + return link; + } else { + uint32_t max_len = 0; /* max slot length */ + + /* get length and physical address of stored key */ + ret_status = system_keystore_get_slot_info(ptr->ownerid, ptr->slot, (uint32_t *) & link->data, /* RED key address */ + &max_len); +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS + ("ret_status==SCC_RET_OK? %s. slot: %i. data: %p" + ". len: %i, key length: %i", + (ret_status == FSL_RETURN_OK_S ? "yes" : "no"), + ptr->slot, link->data, max_len, ptr->len); +#endif + + if ((ret_status == FSL_RETURN_OK_S) && (ptr->len <= max_len)) { + /* finish populating the link */ + link->len = ptr->len; + link->flags = ptr->flags & ~SAH_PREPHYS_DATA; + *tail = link; + } else { +#ifdef DIAG_DRV_IF + if (ret_status == FSL_RETURN_OK_S) { + LOG_KDIAG + ("SCC sah_Link key slot reference is too long"); + } else { + LOG_KDIAG + ("SCC sah_Link slot slot reference is invalid"); + } +#endif + sah_Free_Link(link); + status = FSL_RETURN_INTERNAL_ERROR_S; + return NULL; + } + return link; + } + } else if (ptr->flags & SAH_IN_USER_KEYSTORE) { + +#ifdef FSL_HAVE_SCC2 + + void *kernel_base; + + /* allocate space for this link */ + link = sah_Alloc_Link(); +#ifdef DIAG_MEM + sprintf(Diag_msg, "Alloc_Link returned %p/%p\n", link, + (void *)link->dma_addr); + LOG_KDIAG(Diag_msg); +#endif /* DIAG_MEM */ + + if (link == NULL) { + status = FSL_RETURN_NO_RESOURCE_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("sah_Alloc_Link() failed!"); +#endif + return link; + } else { + /* link->data points to the virtual address of the key data, however + * this memory does not need to be locked down. + */ + kernel_base = lookup_user_partition(user_ctx, + (uint32_t) ptr-> + data & PAGE_MASK); + + link->data = (uint8_t *) scc_virt_to_phys(kernel_base + + ((unsigned + long)ptr-> + data & + ~PAGE_MASK)); + + /* Do bounds checking to ensure that the user is not overstepping + * the bounds of their partition. This is a simple implementation + * that assumes the user only owns one partition. It only checks + * to see if the address of the last byte of data steps over a + * page boundary. + */ + if ((kernel_base != NULL) && + ((((uint32_t) link->data + + link->len) >> PAGE_SHIFT) == + ((uint32_t) link->data >> PAGE_SHIFT))) { + /* finish populating the link */ + link->len = ptr->len; + link->flags = ptr->flags & ~SAH_PREPHYS_DATA; + *tail = link; + } else { +#ifdef DIAG_DRV_IF + if (kernel_base != NULL) { + LOG_KDIAG + ("SCC sah_Link key slot reference is too long"); + } else { + LOG_KDIAG + ("SCC sah_Link slot slot reference is invalid"); + } +#endif + sah_Free_Link(link); + status = FSL_RETURN_INTERNAL_ERROR_S; + return NULL; + } + return link; + } + +#else /* FSL_HAVE_SCC2 */ + + return NULL; + +#endif /* FSL_HAVE_SCC2 */ + } + + if (ptr->data == NULL) { + /* The user buffer must not be NULL because map_user_kiobuf() cannot + * handle NULL pointer input. + */ + status = FSL_RETURN_BAD_DATA_LENGTH_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("sah_Link data pointer is NULL."); +#endif + } + + if (status == FSL_RETURN_OK_S) { + unsigned long start_page = (unsigned long)ptr->data & PAGE_MASK; + + /* determine number of pages being used for this link */ + nr_pages = (((unsigned long)(ptr->data) & ~PAGE_MASK) + + ptr->len + ~PAGE_MASK) >> PAGE_SHIFT; + + /* ptr contains all the 'user space' information, add the pages + * to it also just so everything is in one place */ + local_pages = + kmalloc(nr_pages * sizeof(struct page *), GFP_KERNEL); + + if (local_pages == NULL) { + status = FSL_RETURN_NO_RESOURCE_S; /* no memory! */ +#ifdef DIAG_DRV_IF + LOG_KDIAG("kmalloc() failed."); +#endif + } else { + /* get the actual pages being used in 'user space' */ + + down_read(¤t->mm->mmap_sem); + result = get_user_pages(current, current->mm, + start_page, nr_pages, + write, 0 /* noforce */ , + local_pages, NULL); + up_read(¤t->mm->mmap_sem); + + if (result < nr_pages) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("get_user_pages() failed."); +#endif + if (result > 0) { + for (page_index = 0; + page_index < result; + page_index++) { + page_cache_release(local_pages + [page_index]); + } + } + status = FSL_RETURN_INTERNAL_ERROR_S; + } + } + } + + /* Now we can walk through the list of pages in the buffer */ + if (status == FSL_RETURN_OK_S) { + +#if defined(FLUSH_SPECIFIC_DATA_ONLY) && !defined(HAS_L2_CACHE) + /* + * Now that pages are wired, clear user data from cache lines. When + * there is just an L1 cache, clean based on user virtual for ARM. + */ + if (write == WRITE) { + os_cache_flush_range(ptr->data, ptr->len); + } else { + os_cache_clean_range(ptr->data, ptr->len); + } +#endif + + for (page_index = 0; page_index < nr_pages; page_index++) { + /* Allocate a new link structure */ + link = sah_Alloc_Link(); +#ifdef DIAG_MEM + sprintf(Diag_msg, "Alloc_Link returned %p/%p\n", link, + (void *)link->dma_addr); + LOG_KDIAG(Diag_msg); +#endif + if (link == NULL) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("sah_Alloc_Link() failed."); +#endif + status = FSL_RETURN_NO_RESOURCE_S; + + /* need to free the rest of the pages. Destroy_Links will take + * care of the ones already assigned to a link */ + for (; page_index < nr_pages; page_index++) { + page_cache_release(local_pages + [page_index]); + } + break; /* exit 'for page_index' loop */ + } + + if (status == FSL_RETURN_OK_S) { + if (is_this_the_head == TRUE) { + /* keep a reference to the head link */ + head_link = link; + /* remember that we have seen the head link */ + is_this_the_head = FALSE; + } else { + /* If this is not the head link then set the previous + * link's next pointer to point to this link */ + prev_link->original_next = link; + prev_link->next = + (sah_Link *) link->dma_addr; + } + + buffer_start = + page_address(local_pages[page_index]); + + if (page_index == 0) { + /* If this is the first page, there might be an + * offset. We need to increment the address by this offset + * so we don't just get the start of the page. + */ + buffer_start += + (unsigned long) + sah_Link_Get_Data(ptr) + & ~PAGE_MASK; + buffer_length = PAGE_SIZE + - + ((unsigned long) + sah_Link_Get_Data(ptr) + & ~PAGE_MASK); + } else { + buffer_length = PAGE_SIZE; + } + + if (page_index == nr_pages - 1) { + /* if this is the last page, we need to adjust + * the buffer_length to account for the last page being + * partially used. + */ + buffer_length -= + nr_pages * PAGE_SIZE - + sah_Link_Get_Len(ptr) - + ((unsigned long) + sah_Link_Get_Data(ptr) & + ~PAGE_MASK); + } +#if defined(FLUSH_SPECIFIC_DATA_ONLY) && defined(HAS_L2_CACHE) + /* + * When there is an L2 cache, clean based on kernel + * virtual.. + */ + if (write == WRITE) { + os_cache_flush_range(buffer_start, + buffer_length); + } else { + os_cache_clean_range(buffer_start, + buffer_length); + } +#endif + + /* Fill in link information */ + link->len = buffer_length; +#if !defined(HAS_L2_CACHE) + /* use original virtual */ + link->original_data = ptr->data; +#else + /* use kernel virtual */ + link->original_data = buffer_start; +#endif + link->data = (void *)os_pa(buffer_start); + link->flags = ptr->flags & ~SAH_PREPHYS_DATA; + link->vm_info = local_pages[page_index]; + prev_link = link; + +#if defined(NO_OUTPUT_1K_CROSSING) || defined(NO_1K_CROSSING) + if ( +#ifdef NO_OUTPUT_1K_CROSSING + /* Insert extra link if 1k boundary on output pointer + * crossed not at an 8-word boundary */ + (link->flags & SAH_OUTPUT_LINK) && + (((uint32_t) buffer_start % 32) != 0) + && +#endif + ((((uint32_t) buffer_start & 1023) + + buffer_length) > 1024)) { + + /* Shorten current link to 1k boundary */ + link->len = + 1024 - + ((uint32_t) buffer_start % 1024); + + /* Get new link to follow it */ + link = sah_Alloc_Link(); + prev_link->len = + 1024 - + ((uint32_t) buffer_start % 1024); + prev_link->original_next = link; + prev_link->next = + (sah_Link *) link->dma_addr; + buffer_length -= prev_link->len; + buffer_start += prev_link->len; + +#if !defined(HAS_L2_CACHE) + /* use original virtual */ + link->original_data = ptr->data; +#else + /* use kernel virtual */ + link->original_data = buffer_start; +#endif + link->data = + (void *)os_pa(buffer_start); + link->vm_info = prev_link->vm_info; + prev_link->vm_info = NULL; /* delay release */ + link->flags = ptr->flags; + link->len = buffer_length; + prev_link = link; + } /* while link would cross 1K boundary */ +#endif /* 1K_CROSSING */ + } + } /* for each page */ + } + + if (local_pages != NULL) { + kfree(local_pages); + } + + if (status != FSL_RETURN_OK_S) { + /* De-allocated any links created, this routine first looks if + * head_link is NULL */ + sah_Destroy_Links(head_link); + + /* Clean-up of the KIOBUF will occur in the * sah_Copy_Descriptors() + * function. + * Clean-up of the Queue entry must occur in the function called + * sah_Copy_Descriptors(). + */ + } else { + + /* Success. Return the head link. */ + ret_val = head_link; + link->original_next = NULL; + /* return the tail link as well */ + *tail = link; + } + + return ret_val; +} /* sah_Make_Links() */ + +/*! +******************************************************************************* +* This walks through a SAHARA descriptor chain and frees everything +* that is not NULL. Finally it also unmaps all of the physical memory and +* frees the kiobuf_list Queue. +* +* @brief Kernel Descriptor Chain Destructor +* +* @param desc A Descriptor pointer from kernel-space. This should be +* in bus address space. +* +* @return void +* +*/ +void sah_Destroy_Descriptors(sah_Head_Desc * head_desc) +{ + sah_Desc *this_desc = (sah_Desc *) head_desc; + sah_Desc *next_desc = NULL; + int this_is_head = 1; + + /* + * Flush the D-cache. This flush is here because the hardware has finished + * processing this descriptor and probably has changed the contents of + * some linked user buffers as a result. This flush will enable + * user-space applications to see the correct data rather than the + * out-of-date cached version. + */ +#ifndef FLUSH_SPECIFIC_DATA_ONLY + os_flush_cache_all(); +#endif + + head_desc = (sah_Head_Desc *) this_desc->virt_addr; + + while (this_desc != NULL) { + if (this_desc->ptr1 != NULL) { + sah_Destroy_Links(this_desc->original_ptr1 + ? this_desc-> + original_ptr1 : this_desc->ptr1); + } + if (this_desc->ptr2 != NULL) { + sah_Destroy_Links(this_desc->original_ptr2 + ? this_desc-> + original_ptr2 : this_desc->ptr2); + } + + /* Get a bus pointer to the next Descriptor */ + next_desc = (this_desc->original_next + ? this_desc->original_next : this_desc->next); + + /* Zero the header and Length fields for security reasons. */ + this_desc->header = 0; + this_desc->len1 = 0; + this_desc->len2 = 0; + + if (this_is_head) { + sah_Free_Head_Descriptor(head_desc); +#ifdef DIAG_MEM + sprintf(Diag_msg, "Free_Head_Descriptor: %p\n", + head_desc); + LOG_KDIAG(Diag_msg); +#endif + this_is_head = 0; + } else { + /* free this descriptor */ + sah_Free_Descriptor(this_desc); +#ifdef DIAG_MEM + sprintf(Diag_msg, "Free_Descriptor: %p\n", this_desc); + LOG_KDIAG(Diag_msg); +#endif + } + + /* Set up for next round. */ + this_desc = (sah_Desc *) next_desc; + } +} + +/*! +******************************************************************************* +* This walks through a SAHARA link chain and frees everything that is +* not NULL excluding user-space buffers. +* +* @brief Kernel Link Chain Destructor +* +* @param link A Link pointer from kernel-space. +* +* @return void +* +*/ +void sah_Destroy_Links(sah_Link * link) +{ + sah_Link *this_link = link; + sah_Link *next_link = NULL; + + while (this_link != NULL) { + + /* if this link indicates an associated page, process it */ + if (this_link->vm_info != NULL) { + /* since this function is only called from the routine that + * creates a kernel copy of the user space descriptor chain, + * there are no pages to dirty. All that is needed is to release + * the page from cache */ + page_cache_release(this_link->vm_info); + } + + /* Get a bus pointer to the next Link */ + next_link = (this_link->original_next + ? this_link->original_next : this_link->next); + + /* Zero the Pointer and Length fields for security reasons. */ + this_link->data = NULL; + this_link->len = 0; + + /* Free this Link */ + sah_Free_Link(this_link); +#ifdef DIAG_MEM + sprintf(Diag_msg, "Free_Link: %p\n", this_link); + LOG_KDIAG(Diag_msg); +#endif + + /* Look at the next Link */ + this_link = next_link; + } +} + +/*! +******************************************************************************* +* @brief Initialize memory manager/mapper. +* +* In 2.4, this function also allocates a kiovec to be used when mapping user +* data to kernel space +* +* @return 0 for success, OS error code on failure +* +*/ +int sah_Init_Mem_Map(void) +{ + int ret = OS_ERROR_FAIL_S; + + mem_lock = os_lock_alloc_init(); + + /* + * If one of these fails, change the calculation in the #define earlier in + * the file to be the other one. + */ + if (sizeof(sah_Link) > MEM_BLOCK_SIZE) { + os_printk("Sahara Driver: sah_Link structure is too large\n"); + } else if (sizeof(sah_Desc) > MEM_BLOCK_SIZE) { + os_printk("Sahara Driver: sah_Desc structure is too large\n"); + } else { + ret = OS_ERROR_OK_S; + } + +#ifndef SELF_MANAGED_POOL + + big_dma_pool = dma_pool_create("sah_big_blocks", NULL, + sizeof(Mem_Big_Block), sizeof(uint32_t), + PAGE_SIZE); + small_dma_pool = dma_pool_create("sah_small_blocks", NULL, + sizeof(Mem_Block), sizeof(uint32_t), + PAGE_SIZE); +#else + +#endif + return ret; +} + +/*! +******************************************************************************* +* @brief Clean up memory manager/mapper. +* +* In 2.4, this function also frees the kiovec used when mapping user data to +* kernel space. +* +* @return none +* +*/ +void sah_Stop_Mem_Map(void) +{ + os_lock_deallocate(mem_lock); + +#ifndef SELF_MANAGED_POOL + if (big_dma_pool != NULL) { + dma_pool_destroy(big_dma_pool); + } + if (small_dma_pool != NULL) { + dma_pool_destroy(small_dma_pool); + } +#endif +} + +/*! +******************************************************************************* +* Allocate Head descriptor from free pool. +* +* @brief Allocate Head descriptor +* +* @return sah_Head_Desc Free descriptor, NULL if no free descriptors available. +* +*/ +sah_Head_Desc *sah_Alloc_Head_Descriptor(void) +{ + Mem_Big_Block *block; + sah_Head_Desc *desc; + + block = sah_Alloc_Big_Block(); + if (block != NULL) { + /* initialize everything */ + desc = (sah_Head_Desc *) block->data; + + desc->desc.virt_addr = (sah_Desc *) desc; + desc->desc.dma_addr = block->dma_addr; + desc->desc.original_ptr1 = NULL; + desc->desc.original_ptr2 = NULL; + desc->desc.original_next = NULL; + + desc->desc.ptr1 = NULL; + desc->desc.ptr2 = NULL; + desc->desc.next = NULL; + } else { + desc = NULL; + } + + return desc; +} + +/*! +******************************************************************************* +* Allocate descriptor from free pool. +* +* @brief Allocate descriptor +* +* @return sah_Desc Free descriptor, NULL if no free descriptors available. +* +*/ +sah_Desc *sah_Alloc_Descriptor(void) +{ + Mem_Block *block; + sah_Desc *desc; + + block = sah_Alloc_Block(); + if (block != NULL) { + /* initialize everything */ + desc = (sah_Desc *) block->data; + + desc->virt_addr = desc; + desc->dma_addr = block->dma_addr; + desc->original_ptr1 = NULL; + desc->original_ptr2 = NULL; + desc->original_next = NULL; + + desc->ptr1 = NULL; + desc->ptr2 = NULL; + desc->next = NULL; + } else { + desc = NULL; + } + + return (desc); +} + +/*! +******************************************************************************* +* Allocate link from free pool. +* +* @brief Allocate link +* +* @return sah_Link Free link, NULL if no free links available. +* +*/ +sah_Link *sah_Alloc_Link(void) +{ + Mem_Block *block; + sah_Link *link; + + block = sah_Alloc_Block(); + if (block != NULL) { + /* initialize everything */ + link = (sah_Link *) block->data; + + link->virt_addr = link; + link->original_next = NULL; + link->original_data = NULL; + /* information found in allocated block */ + link->dma_addr = block->dma_addr; + + /* Sahara link fields */ + link->len = 0; + link->data = NULL; + link->next = NULL; + + /* driver required fields */ + link->flags = 0; + link->vm_info = NULL; + } else { + link = NULL; + } + + return link; +} + +#ifdef SELF_MANAGED_POOL +/*! +******************************************************************************* +* Add a new page to end of block free pool. This will allocate one page and +* fill the pool with entries, appending to the end. +* +* @brief Add page of blocks to block free pool. +* +* @pre This function must be called with the #mem_lock held. +* +* @param big 0 - make blocks big enough for sah_Desc +* non-zero - make blocks big enough for sah_Head_Desc +* +* @return int TRUE if blocks added succeesfully, FALSE otherwise +* +*/ +int sah_Block_Add_Page(int big) +{ + void *page; + int success; + dma_addr_t dma_addr; + unsigned block_index; + uint32_t dma_offset; + unsigned block_entries = + big ? MEM_BIG_BLOCK_ENTRIES : MEM_BLOCK_ENTRIES; + unsigned block_size = big ? sizeof(Mem_Big_Block) : sizeof(Mem_Block); + void *block; + + /* Allocate page of memory */ +#ifndef USE_COHERENT_MEMORY + page = os_alloc_memory(PAGE_SIZE, GFP_ATOMIC | __GFP_DMA); + dma_addr = os_pa(page); +#else + page = os_alloc_coherent(PAGE_SIZE, &dma_addr, GFP_ATOMIC); +#endif + if (page != NULL) { + /* + * Find the difference between the virtual address and the DMA + * address of the page. This is used later to determine the DMA + * address of each individual block. + */ + dma_offset = page - (void *)dma_addr; + + /* Split page into blocks and add to free pool */ + block = page; + for (block_index = 0; block_index < block_entries; + block_index++) { + if (big) { + register Mem_Big_Block *blockp = block; + blockp->dma_addr = + (uint32_t) (block - dma_offset); + sah_Append_Big_Block(blockp); + } else { + register Mem_Block *blockp = block; + blockp->dma_addr = + (uint32_t) (block - dma_offset); + /* sah_Append_Block must be protected with spin locks. This is + * done in sah_Alloc_Block(), which calls + * sah_Block_Add_Page() */ + sah_Append_Block(blockp); + } + block += block_size; + } + success = TRUE; +#ifdef DIAG_MEM + LOG_KDIAG("Succeeded in allocating new page"); +#endif + } else { + success = FALSE; +#ifdef DIAG_MEM + LOG_KDIAG("Failed in allocating new page"); +#endif + } + + return success; +} +#endif /* SELF_MANAGED_POOL */ + +#ifdef SELF_MANAGED_POOL +/*! +******************************************************************************* +* Allocate block from free pool. A block is large enough to fit either a link +* or descriptor. +* +* @brief Allocate memory block +* +* @return Mem_Block Free block, NULL if no free blocks available. +* +*/ +static Mem_Big_Block *sah_Alloc_Big_Block(void) +{ + Mem_Big_Block *block; + os_lock_context_t lock_flags; + + os_lock_save_context(mem_lock, lock_flags); + + /* If the pool is empty, try to allocate more entries */ + if (big_block_free_head == NULL) { + (void)sah_Block_Add_Page(1); + } + + /* Check that the pool now has some free entries */ + if (big_block_free_head != NULL) { + /* Return the head of the free pool */ + block = big_block_free_head; + + big_block_free_head = big_block_free_head->next; + if (big_block_free_head == NULL) { + /* Allocated last entry in pool */ + big_block_free_tail = NULL; + } + } else { + block = NULL; + } + os_unlock_restore_context(mem_lock, lock_flags); + + return block; +} +#else +/*! +******************************************************************************* +* Allocate block from free pool. A block is large enough to fit either a link +* or descriptor. +* +* @brief Allocate memory block +* +* @return Mem_Block Free block, NULL if no free blocks available. +* +*/ +static Mem_Big_Block *sah_Alloc_Big_Block(void) +{ + dma_addr_t dma_addr; + Mem_Big_Block *block = + dma_pool_alloc(big_dma_pool, GFP_ATOMIC, &dma_addr); + + if (block == NULL) { + } else { + block->dma_addr = dma_addr; + } + + return block; +} +#endif + +#ifdef SELF_MANAGED_POOL +/*! +******************************************************************************* +* Allocate block from free pool. A block is large enough to fit either a link +* or descriptor. +* +* @brief Allocate memory block +* +* @return Mem_Block Free block, NULL if no free blocks available. +* +*/ +/****************************************************************************** +* +* MODIFICATION HISTORY: +* +* Date Person Change +* 31/10/2003 RWK PR52734 - Implement functions to allocate +* descriptors and links. Replace +* consistent_alloc() calls. Initial creation. +* +******************************************************************************/ +static Mem_Block *sah_Alloc_Block(void) +{ + Mem_Block *block; + os_lock_context_t lock_flags; + + os_lock_save_context(mem_lock, lock_flags); + + /* If the pool is empty, try to allocate more entries */ + if (block_free_head == NULL) { + (void)sah_Block_Add_Page(0); + } + + /* Check that the pool now has some free entries */ + if (block_free_head != NULL) { + /* Return the head of the free pool */ + block = block_free_head; + + block_free_head = block_free_head->next; + if (block_free_head == NULL) { + /* Allocated last entry in pool */ + block_free_tail = NULL; + } + } else { + block = NULL; + } + os_unlock_restore_context(mem_lock, lock_flags); + + return block; +} +#else +/*! +******************************************************************************* +* Allocate block from free pool. A block is large enough to fit either a link +* or descriptor. +* +* @brief Allocate memory block +* +* @return Mem_Block Free block, NULL if no free blocks available. +* +*/ +/****************************************************************************** +* +* MODIFICATION HISTORY: +* +* Date Person Change +* 31/10/2003 RWK PR52734 - Implement functions to allocate +* descriptors and links. Replace +* consistent_alloc() calls. Initial creation. +* +******************************************************************************/ +static Mem_Block *sah_Alloc_Block(void) +{ + + dma_addr_t dma_addr; + Mem_Block *block = + dma_pool_alloc(small_dma_pool, GFP_ATOMIC, &dma_addr); + + if (block == NULL) { + } else { + block->dma_addr = dma_addr; + } + + return block; +} +#endif + +#ifdef SELF_MANAGED_POOL +/*! +******************************************************************************* +* Free memory block back to free pool +* +* @brief Free memory block +* +* @param block A block allocated with sah_Alloc_Block(). +* +* @return none +* +*/ +static void sah_Free_Block(Mem_Block * block) +{ + os_lock_context_t lock_flags; + + os_lock_save_context(mem_lock, lock_flags); + sah_Append_Block(block); + os_unlock_restore_context(mem_lock, lock_flags); +} +#else +/*! +******************************************************************************* +* Free memory block back to free pool +* +* @brief Free memory block +* +* @param block A block allocated with sah_Alloc_Block(). +* +* @return none +* +*/ +static void sah_Free_Block(Mem_Block * block) +{ + dma_pool_free(small_dma_pool, block, block->dma_addr); +} +#endif + +#ifdef SELF_MANAGED_POOL +/*! +******************************************************************************* +* Free memory block back to free pool +* +* @brief Free memory block +* +* @param block A block allocated with sah_Alloc_Block(). +* +* @return none +* +*/ +static void sah_Free_Big_Block(Mem_Big_Block * block) +{ + os_lock_context_t lock_flags; + + os_lock_save_context(mem_lock, lock_flags); + sah_Append_Big_Block(block); + os_unlock_restore_context(mem_lock, lock_flags); +} +#else +/*! +******************************************************************************* +* Free memory block back to free pool +* +* @brief Free memory block +* +* @param block A block allocated with sah_Alloc_Block(). +* +* @return none +* +*/ +static void sah_Free_Big_Block(Mem_Big_Block * block) +{ + dma_pool_free(big_dma_pool, block, block->dma_addr); +} +#endif + +#ifdef SELF_MANAGED_POOL +/*! +******************************************************************************* +* Append memory block to end of free pool. +* +* @param block A block entry +* +* @return none +* +* @pre This function must be called with the #mem_lock held. +* +* @brief Append memory block to free pool +*/ +static void sah_Append_Big_Block(Mem_Big_Block * block) +{ + + /* Initialise block */ + block->next = NULL; + + /* Remember that block may be the first in the pool */ + if (big_block_free_tail != NULL) { + big_block_free_tail->next = block; + } else { + /* Pool is empty */ + big_block_free_head = block; + } + + big_block_free_tail = block; +} + +/*! +******************************************************************************* +* Append memory block to end of free pool. +* +* @brief Append memory block to free pool +* +* @param block A block entry +* +* @return none +* +* @pre #mem_lock must be held +* +*/ +static void sah_Append_Block(Mem_Block * block) +{ + + /* Initialise block */ + block->next = NULL; + + /* Remember that block may be the first in the pool */ + if (block_free_tail != NULL) { + block_free_tail->next = block; + } else { + /* Pool is empty */ + block_free_head = block; + } + + block_free_tail = block; +} +#endif /* SELF_MANAGED_POOL */ + +/* End of sah_memory_mapper.c */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/sah_queue.c linux-2.6.26-lab126/drivers/mxc/security/sahara2/sah_queue.c --- linux-2.6.26/drivers/mxc/security/sahara2/sah_queue.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/sah_queue.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,249 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! +* @file sah_queue.c +* +* @brief This file provides a FIFO Queue implementation. +* +*/ +/****************************************************************************** +* +* CAUTION: +******************************************************************* +*/ + +/* SAHARA Includes */ +#include +#ifdef DIAG_DRV_QUEUE +#include +#endif + +/****************************************************************************** +* Queue Functions +******************************************************************************/ + +/*! +******************************************************************************* +* This function constructs a new sah_Queue. +* +* @brief sah_Queue Constructor +* +* @return A pointer to a newly allocated sah_Queue. +* @return NULL if allocation of memory failed. +*/ +/****************************************************************************** +* +* CAUTION: This function may sleep in low-memory situations, as it uses +* kmalloc ( ..., GFP_KERNEL). +******************************************************************************/ +sah_Queue *sah_Queue_Construct(void) +{ + sah_Queue *q = (sah_Queue *) os_alloc_memory(sizeof(sah_Queue), + GFP_KERNEL); + + if (q != NULL) { + /* Initialise the queue to an empty state. */ + q->head = NULL; + q->tail = NULL; + q->count = 0; + } +#ifdef DIAG_DRV_QUEUE + else { + LOG_KDIAG("kmalloc() failed."); + } +#endif + + return q; +} + +/*! +******************************************************************************* +* This function destroys a sah_Queue. +* +* @brief sah_Queue Destructor +* +* @param q A pointer to a sah_Queue. +* +* @return void +*/ +/****************************************************************************** +* +* CAUTION: This function does not free any queue entries. +* +******************************************************************************/ +void sah_Queue_Destroy(sah_Queue * q) +{ +#ifdef DIAG_DRV_QUEUE + if (q == NULL) { + LOG_KDIAG("Trying to kfree() a NULL pointer."); + } else { + if (q->count != 0) { + LOG_KDIAG + ("Trying to destroy a queue that is not empty."); + } + } +#endif + + if (q != NULL) { + os_free_memory(q); + q = NULL; + } +} + +/*! +******************************************************************************* +* This function appends a sah_Head_Desc to the tail of a sah_Queue. +* +* @brief Appends a sah_Head_Desc to a sah_Queue. +* +* @param q A pointer to a sah_Queue to append to. +* @param entry A pointer to a sah_Head_Desc to append. +* +* @pre The #desc_queue_lock must be held before calling this function. +* +* @return void +*/ +/****************************************************************************** +* +* CAUTION: NONE +******************************************************************************/ +void sah_Queue_Append_Entry(sah_Queue * q, sah_Head_Desc * entry) +{ + sah_Head_Desc *tail_entry = NULL; + + if ((q == NULL) || (entry == NULL)) { +#ifdef DIAG_DRV_QUEUE + LOG_KDIAG("Null pointer input."); +#endif + return; + } + + if (q->count == 0) { + /* The queue is empty */ + q->head = entry; + q->tail = entry; + entry->next = NULL; + entry->prev = NULL; + } else { + /* The queue is not empty */ + tail_entry = q->tail; + tail_entry->next = entry; + entry->next = NULL; + entry->prev = tail_entry; + q->tail = entry; + } + q->count++; +} + +/*! +******************************************************************************* +* This function a removes a sah_Head_Desc from the head of a sah_Queue. +* +* @brief Removes a sah_Head_Desc from a the head of a sah_Queue. +* +* @param q A pointer to a sah_Queue to remove from. +* +* @pre The #desc_queue_lock must be held before calling this function. +* +* @return void +*/ +/****************************************************************************** +* +* CAUTION: This does not kfree() the entry. +******************************************************************************/ +void sah_Queue_Remove_Entry(sah_Queue * q) +{ + sah_Queue_Remove_Any_Entry(q, q->head); +} + +/*! +******************************************************************************* +* This function a removes a sah_Head_Desc from anywhere in a sah_Queue. +* +* @brief Removes a sah_Head_Desc from anywhere in a sah_Queue. +* +* @param qq A pointer to a sah_Queue to remove from. +* @param entry A pointer to a sah_Head_Desc to remove. +* +* @pre The #desc_queue_lock must be held before calling this function. +* +* @return void +*/ +/****************************************************************************** +* +* CAUTION: This does not kfree() the entry. Does not check to see if the entry +* actually belongs to the queue. +******************************************************************************/ +void sah_Queue_Remove_Any_Entry(sah_Queue * q, sah_Head_Desc * entry) +{ + sah_Head_Desc *prev_entry = NULL; + sah_Head_Desc *next_entry = NULL; + + if ((q == NULL) || (entry == NULL)) { +#if defined DIAG_DRV_QUEUE && defined DIAG_DURING_INTERRUPT + LOG_KDIAG("Null pointer input."); +#endif + return; + } + + if (q->count == 1) { + /* If q is the only entry in the queue. */ + q->tail = NULL; + q->head = NULL; + q->count = 0; + } else if (q->count > 1) { + /* There are 2 or more entries in the queue. */ + +#if defined DIAG_DRV_QUEUE && defined DIAG_DURING_INTERRUPT + if ((entry->next == NULL) && (entry->prev == NULL)) { + LOG_KDIAG + ("Queue is not empty yet both next and prev pointers" + " are NULL"); + } +#endif + + if (entry->next == NULL) { + /* If this is the end of the queue */ + prev_entry = entry->prev; + prev_entry->next = NULL; + q->tail = prev_entry; + } else if (entry->prev == NULL) { + /* If this is the head of the queue */ + next_entry = entry->next; + next_entry->prev = NULL; + q->head = next_entry; + } else { + /* If this is somewhere in the middle of the queue */ + prev_entry = entry->prev; + next_entry = entry->next; + prev_entry->next = next_entry; + next_entry->prev = prev_entry; + } + q->count--; + } + /* + * Otherwise we are removing an entry from an empty queue. + * Don't do anything in the product code + */ +#if defined DIAG_DRV_QUEUE && defined DIAG_DURING_INTERRUPT + else { + LOG_KDIAG("Trying to remove an entry from an empty queue."); + } +#endif + + entry->next = NULL; + entry->prev = NULL; +} + +/* End of sah_queue.c */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/sah_queue_manager.c linux-2.6.26-lab126/drivers/mxc/security/sahara2/sah_queue_manager.c --- linux-2.6.26/drivers/mxc/security/sahara2/sah_queue_manager.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/sah_queue_manager.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,1033 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file sah_queue_manager.c + * + * @brief This file provides a Queue Manager implementation. + * + * The Queue Manager manages additions and removal from the queue and updates + * the status of queue entries. It also calls sah_HW_* functions to interract + * with the hardware. +*/ + +#include "portable_os.h" + +/* SAHARA Includes */ +#include +#include +#include +#include +#if defined(DIAG_DRV_QUEUE) || defined(DIAG_DRV_STATUS) +#include +#endif +#include + +#ifdef DIAG_DRV_STATUS + +#define FSL_INVALID_RETURN 13 +#define MAX_RETURN_STRING_LEN 22 +#endif + +/* Defines for parsing value from Error Status register */ +#define SAH_STATUS_MASK 0x07 +#define SAH_ERROR_MASK 0x0F +#define SAH_CHA_ERR_SOURCE_MASK 0x07 +#define SAH_CHA_ERR_STATUS_MASK 0x0FFF +#define SAH_DMA_ERR_STATUS_MASK 0x0F +#define SAH_DMA_ERR_SIZE_MASK 0x03 +#define SAH_DMA_ERR_DIR_MASK 0x01 + +#define SHA_ERROR_STATUS_CONTINUE 0xFFFFFFFF +#define SHA_CHA_ERROR_STATUS_DONE 0xFFFFFFFF + +/* this maps the error status register's error source 4 bit field to the API + * return values. A 0xFFFFFFFF indicates additional fields must be checked to + * determine an appropriate return value */ +static sah_Execute_Error sah_Execute_Error_Array[] = { + FSL_RETURN_ERROR_S, /* SAH_ERR_NONE */ + FSL_RETURN_BAD_FLAG_S, /* SAH_ERR_HEADER */ + FSL_RETURN_BAD_DATA_LENGTH_S, /* SAH_ERR_DESC_LENGTH */ + FSL_RETURN_BAD_DATA_LENGTH_S, /* SAH_ERR_DESC_POINTER */ + FSL_RETURN_BAD_DATA_LENGTH_S, /* SAH_ERR_LINK_LENGTH */ + FSL_RETURN_BAD_DATA_LENGTH_S, /* SAH_ERR_LINK_POINTER */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_ERR_INPUT_BUFFER */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_ERR_OUTPUT_BUFFER */ + FSL_RETURN_BAD_DATA_LENGTH_S, /* SAH_ERR_OUTPUT_BUFFER_STARVATION */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_ERR_INTERNAL_STATE */ + FSL_RETURN_ERROR_S, /* SAH_ERR_GENERAL_DESCRIPTOR */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_ERR_RESERVED_FIELDS */ + FSL_RETURN_MEMORY_ERROR_S, /* SAH_ERR_DESCRIPTOR_ADDRESS */ + FSL_RETURN_MEMORY_ERROR_S, /* SAH_ERR_LINK_ADDRESS */ + SHA_ERROR_STATUS_CONTINUE, /* SAH_ERR_CHA */ + SHA_ERROR_STATUS_CONTINUE /* SAH_ERR_DMA */ +}; + +static sah_DMA_Error_Status sah_DMA_Error_Status_Array[] = { + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_DMA_NO_ERR */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_DMA_AHB_ERR */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_DMA_IP_ERR */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_DMA_PARITY_ERR */ + FSL_RETURN_BAD_DATA_LENGTH_S, /* SAH_DMA_BOUNDRY_ERR */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_DMA_BUSY_ERR */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_DMA_RESERVED_ERR */ + FSL_RETURN_INTERNAL_ERROR_S /* SAH_DMA_INT_ERR */ +}; + +static sah_CHA_Error_Status sah_CHA_Error_Status_Array[] = { + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_CHA_NO_ERR */ + FSL_RETURN_BAD_DATA_LENGTH_S, /* SAH_CHA_IP_BUF */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_CHA_ADD_ERR */ + FSL_RETURN_BAD_MODE_S, /* SAH_CHA_MODE_ERR */ + FSL_RETURN_BAD_DATA_LENGTH_S, /* SAH_CHA_DATA_SIZE_ERR */ + FSL_RETURN_BAD_KEY_LENGTH_S, /* SAH_CHA_KEY_SIZE_ERR */ + FSL_RETURN_BAD_MODE_S, /* SAH_CHA_PROC_ERR */ + FSL_RETURN_ERROR_S, /* SAH_CHA_CTX_READ_ERR */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_CHA_INTERNAL_HW_ERR */ + FSL_RETURN_MEMORY_ERROR_S, /* SAH_CHA_IP_BUFF_ERR */ + FSL_RETURN_MEMORY_ERROR_S, /* SAH_CHA_OP_BUFF_ERR */ + FSL_RETURN_BAD_KEY_PARITY_S, /* SAH_CHA_DES_KEY_ERR */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_CHA_RES */ +}; + +#ifdef DIAG_DRV_STATUS + +char sah_return_text[FSL_INVALID_RETURN][MAX_RETURN_STRING_LEN] = { + "No error", /* FSL_RETURN_OK_S */ + "Error", /* FSL_RETURN_ERROR_S */ + "No resource", /* FSL_RETURN_NO_RESOURCE_S */ + "Bad algorithm", /* FSL_RETURN_BAD_ALGORITHM_S */ + "Bad mode", /* FSL_RETURN_BAD_MODE_S */ + "Bad flag", /* FSL_RETURN_BAD_FLAG_S */ + "Bad key length", /* FSL_RETURN_BAD_KEY_LENGTH_S */ + "Bad key parity", /* FSL_RETURN_BAD_KEY_PARITY_S */ + "Bad data length", /* FSL_RETURN_BAD_DATA_LENGTH_S */ + "Authentication failed", /* FSL_RETURN_AUTH_FAILED_S */ + "Memory error", /* FSL_RETURN_MEMORY_ERROR_S */ + "Internal error", /* FSL_RETURN_INTERNAL_ERROR_S */ + "unknown value", /* default */ +}; + +#endif /* DIAG_DRV_STATUS */ + +/*! + * This lock must be held while performing any queuing or unqueuing functions, + * including reading the first pointer on the queue. It also protects reading + * and writing the Sahara DAR register. It must be held during a read-write + * operation on the DAR so that the 'test-and-set' is atomic. + */ +os_lock_t desc_queue_lock; + +/*! This is the main queue for the driver. This is shared between all threads + * and is not protected by mutexes since the kernel is non-preemptable. */ +sah_Queue *main_queue = NULL; + +/* Internal Prototypes */ +sah_Head_Desc *sah_Find_With_State(sah_Queue_Status state); + +#ifdef DIAG_DRV_STATUS +void sah_Log_Error(uint32_t descriptor, uint32_t error, uint32_t fault_address); +#endif + +extern wait_queue_head_t *int_queue; + +/*! + * This function initialises the Queue Manager + * + * @brief Initialise the Queue Manager + * + * @return FSL_RETURN_OK_S on success; FSL_RETURN_MEMORY_ERROR_S if not + */ +fsl_shw_return_t sah_Queue_Manager_Init(void) +{ + fsl_shw_return_t ret_val = FSL_RETURN_OK_S; + + desc_queue_lock = os_lock_alloc_init(); + + if (main_queue == NULL) { + /* Construct the main queue. */ + main_queue = sah_Queue_Construct(); + + if (main_queue == NULL) { + ret_val = FSL_RETURN_MEMORY_ERROR_S; + } + } else { +#ifdef DIAG_DRV_QUEUE + LOG_KDIAG + ("Trying to initialise the queue manager more than once."); +#endif + } + + return ret_val; +} + +/*! + * This function closes the Queue Manager + * + * @brief Close the Queue Manager + * + * @return void + */ +void sah_Queue_Manager_Close(void) +{ +#ifdef DIAG_DRV_QUEUE + if (main_queue && main_queue->count != 0) { + LOG_KDIAG + ("Trying to close the main queue when it is not empty."); + } +#endif + + if (main_queue) { + /* There is no error checking here because there is no way to handle + it. */ + sah_Queue_Destroy(main_queue); + main_queue = NULL; + } +} + +/*! + * Count the number of entries on the Queue Manager's queue + * + * @param ignore_state If non-zero, the @a state parameter is ignored. + * If zero, only entries matching @a state are counted. + * @param state State of entry to match for counting. + * + * @return Number of entries which matched criteria + */ +int sah_Queue_Manager_Count_Entries(int ignore_state, sah_Queue_Status state) +{ + int count = 0; + sah_Head_Desc *current_entry; + + /* Start at the head */ + current_entry = main_queue->head; + while (current_entry != NULL) { + if (ignore_state || (current_entry->status == state)) { + count++; + } + /* Jump to the next entry. */ + current_entry = current_entry->next; + } + + return count; +} + +/*! + * This function removes an entry from the Queue Manager's queue. The entry to + * be removed can be anywhere in the queue. + * + * @brief Remove an entry from the Queue Manager's queue. + * + * @param entry A pointer to a sah_Head_Desc to remove from the Queue + * Manager's queue. + * + * @pre The #desc_queue_lock must be held before calling this function. + * + * @return void + */ +void sah_Queue_Manager_Remove_Entry(sah_Head_Desc * entry) +{ + if (entry == NULL) { +#ifdef DIAG_DRV_QUEUE + LOG_KDIAG("NULL pointer input."); +#endif + } else { + sah_Queue_Remove_Any_Entry(main_queue, entry); + } +} + +/*! + * This function appends an entry to the Queue Managers queue. It primes SAHARA + * if this entry is the first PENDING entry in the Queue Manager's Queue. + * + * @brief Appends an entry to the Queue Manager's queue. + * + * @param entry A pointer to a sah_Head_Desc to append to the Queue + * Manager's queue. + * + * @pre The #desc_queue_lock may not may be held when calling this function. + * + * @return void + */ +void sah_Queue_Manager_Append_Entry(sah_Head_Desc * entry) +{ + sah_Head_Desc *current_entry; + os_lock_context_t int_flags; + +#ifdef DIAG_DRV_QUEUE + if (entry == NULL) { + LOG_KDIAG("NULL pointer input."); + } +#endif + entry->status = SAH_STATE_PENDING; + os_lock_save_context(desc_queue_lock, int_flags); + sah_Queue_Append_Entry(main_queue, entry); + + /* Prime SAHARA if the operation that was just appended is the only PENDING + * operation in the queue. + */ + current_entry = sah_Find_With_State(SAH_STATE_PENDING); + if (current_entry != NULL) { + if (current_entry == entry) { + sah_Queue_Manager_Prime(entry); + } + } + + os_unlock_restore_context(desc_queue_lock, int_flags); +} + +/*! + * This function marks all entries in the Queue Manager's queue with state + * SAH_STATE_RESET. + * + * @brief Mark all entries with state SAH_STATE_RESET + * + * @return void + * + * @note This feature needs re-visiting + */ +void sah_Queue_Manager_Reset_Entries(void) +{ + sah_Head_Desc *current_entry = NULL; + + /* Start at the head */ + current_entry = main_queue->head; + + while (current_entry != NULL) { + /* Set the state. */ + current_entry->status = SAH_STATE_RESET; + /* Jump to the next entry. */ + current_entry = current_entry->next; + } +} + +/*! + * This function primes SAHARA for the first time or after the queue becomes + * empty. Queue lock must have been set by the caller of this routine. + * + * @brief Prime SAHARA. + * + * @param entry A pointer to a sah_Head_Desc to Prime SAHARA with. + * + * @return void + */ +void sah_Queue_Manager_Prime(sah_Head_Desc * entry) +{ +#ifdef DIAG_DRV_QUEUE + LOG_KDIAG("Priming SAHARA"); + if (entry == NULL) { + LOG_KDIAG("Trying to prime SAHARA with a NULL entry pointer."); + } +#endif + +#ifndef SUBMIT_MULTIPLE_DARS + /* BUG FIX: state machine can transition from Done1 Busy2 directly + * to Idle. To fix that problem, only one DAR is being allowed on + * SAHARA at a time */ + if (sah_Find_With_State(SAH_STATE_ON_SAHARA) != NULL) { + return; + } +#endif + +#ifdef SAHARA_POWER_MANAGEMENT + /* check that dynamic power management is not asserted */ + if (!sah_dpm_flag) { +#endif + /* Make sure nothing is in the DAR */ + if (sah_HW_Read_DAR() == 0) { +#if defined(DIAG_DRV_IF) + sah_Dump_Chain(&entry->desc, entry->desc.dma_addr); +#endif /* DIAG_DRV_IF */ + + sah_HW_Write_DAR((entry->desc.dma_addr)); + entry->status = SAH_STATE_ON_SAHARA; + } +#ifdef DIAG_DRV_QUEUE + else { + LOG_KDIAG("DAR should be empty when Priming SAHARA"); + } +#endif +#ifdef SAHARA_POWER_MANAGEMENT + } +#endif +} + +#ifndef SAHARA_POLL_MODE + +/*! + * Reset SAHARA, then load the next descriptor on it, if one exists + */ +void sah_reset_sahara_request(void) +{ + sah_Head_Desc *desc; + os_lock_context_t lock_flags; + +#ifdef DIAG_DRV_STATUS + LOG_KDIAG("Sahara required reset from tasklet, replace chip"); +#endif + sah_HW_Reset(); + + /* Now stick in a waiting request */ + os_lock_save_context(desc_queue_lock, lock_flags); + if ((desc = sah_Find_With_State(SAH_STATE_PENDING))) { + sah_Queue_Manager_Prime(desc); + } + os_unlock_restore_context(desc_queue_lock, lock_flags); +} + +/*! + * Post-process a descriptor chain after the hardware has finished with it. + * + * The status of the descriptor could also be checked. (for FATAL or IGNORED). + * + * @param desc_head The finished chain + * @param error A boolean to mark whether hardware reported error + * + * @pre The #desc_queue_lock may not be held when calling this function. + */ +void sah_process_finished_request(sah_Head_Desc * desc_head, unsigned error) +{ + os_lock_context_t lock_flags; + + if (!error) { + desc_head->result = FSL_RETURN_OK_S; + } else if (desc_head->error_status == -1) { + /* Disaster! Sahara has faulted */ + desc_head->result = FSL_RETURN_ERROR_S; + } else { + /* translate from SAHARA error status to fsl_shw return values */ + desc_head->result = + sah_convert_error_status(desc_head->error_status); +#ifdef DIAG_DRV_STATUS + sah_Log_Error(desc_head->current_dar, desc_head->error_status, + desc_head->fault_address); +#endif + } + + /* Show that the request has been processd */ + desc_head->status = error ? SAH_STATE_FAILED : SAH_STATE_COMPLETE; + + if (desc_head->uco_flags & FSL_UCO_BLOCKING_MODE) { + + /* Wake up all processes on Sahara queue */ + wake_up_interruptible(int_queue); + + } else { + os_lock_save_context(desc_queue_lock, lock_flags); + sah_Queue_Append_Entry(&desc_head->user_info->result_pool, + desc_head); + os_unlock_restore_context(desc_queue_lock, lock_flags); + + /* perform callback */ + if (desc_head->uco_flags & FSL_UCO_CALLBACK_MODE) { + desc_head->user_info->callback(desc_head->user_info); + } + } +} /* sah_process_finished_request */ + +/*! Called from bottom half. + * + * @pre The #desc_queue_lock may not be held when calling this function. + */ +void sah_postprocess_queue(unsigned long reset_flag) +{ + + /* if SAHARA needs to be reset, do it here. This starts a descriptor chain + * if one is ready also */ + if (reset_flag) { + sah_reset_sahara_request(); + } + + /* now handle the descriptor chain(s) that has/have completed */ + do { + sah_Head_Desc *first_entry; + os_lock_context_t lock_flags; + + os_lock_save_context(desc_queue_lock, lock_flags); + + first_entry = main_queue->head; + if ((first_entry != NULL) && + (first_entry->status == SAH_STATE_OFF_SAHARA)) { + sah_Queue_Remove_Entry(main_queue); + os_unlock_restore_context(desc_queue_lock, lock_flags); + + sah_process_finished_request(first_entry, + (first_entry-> + error_status != 0)); + } else { + os_unlock_restore_context(desc_queue_lock, lock_flags); + break; + } + } while (1); + + return; +} + +#endif /* ifndef SAHARA_POLL_MODE */ + +/*! + * This is a helper function for Queue Manager. This function finds the first + * entry in the Queue Manager's queue whose state matches the given input + * state. This function starts at the head of the queue and works towards the + * tail. If a matching entry was found, the address of the entry is returned. + * + * @brief Handle the IDLE state. + * + * @param state A sah_Queue_Status value. + * + * @pre The #desc_queue_lock must be held before calling this function. + * + * @return A pointer to a sah_Head_Desc that matches the given state. + * @return NULL otherwise. + */ +sah_Head_Desc *sah_Find_With_State(sah_Queue_Status state) +{ + sah_Head_Desc *current_entry = NULL; + sah_Head_Desc *ret_val = NULL; + int done_looping = FALSE; + + /* Start at the head */ + current_entry = main_queue->head; + + while ((current_entry != NULL) && (done_looping == FALSE)) { + if (current_entry->status == state) { + done_looping = TRUE; + ret_val = current_entry; + } + /* Jump to the next entry. */ + current_entry = current_entry->next; + } + + return ret_val; +} /* sah_postprocess_queue */ + +/*! + * Process the value from the Sahara error status register and convert it into + * an FSL SHW API error code. + * + * Warning, this routine must only be called if an error exists. + * + * @param error_status The value from the error status register. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_convert_error_status(uint32_t error_status) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; /* catchall */ + uint8_t error_source; + uint8_t DMA_error_status; + uint8_t DMA_error_size; + + /* get the error source from the error status register */ + error_source = error_status & SAH_ERROR_MASK; + + /* array size is maximum allowed by mask, so no boundary checking is + * needed here */ + ret = sah_Execute_Error_Array[error_source]; + + /* is this one that needs additional fields checked to determine the + * error condition? */ + if (ret == SHA_ERROR_STATUS_CONTINUE) { + /* check the DMA fields */ + if (error_source == SAH_ERR_DMA) { + /* get the DMA transfer error size. If this indicates that no + * error was detected, something is seriously wrong */ + DMA_error_size = + (error_status >> 9) & SAH_DMA_ERR_SIZE_MASK; + if (DMA_error_size == SAH_DMA_NO_ERR) { + ret = FSL_RETURN_INTERNAL_ERROR_S; + } else { + /* get DMA error status */ + DMA_error_status = (error_status >> 12) & + SAH_DMA_ERR_STATUS_MASK; + + /* the DMA error bits cover all the even numbers. By dividing + * by 2 it can be used as an index into the error array */ + ret = + sah_DMA_Error_Status_Array[DMA_error_status + >> 1]; + } + } else { /* not SAH_ERR_DMA, so must be SAH_ERR_CHA */ + uint16_t CHA_error_status; + uint8_t CHA_error_source; + + /* get CHA Error Source. If this indicates that no error was + * detected, something is seriously wrong */ + CHA_error_source = + (error_status >> 28) & SAH_CHA_ERR_SOURCE_MASK; + if (CHA_error_source == SAH_CHA_NO_ERROR) { + ret = FSL_RETURN_INTERNAL_ERROR_S; + } else { + uint32_t mask = 1; + uint32_t count = 0; + + /* get CHA Error Status */ + CHA_error_status = (error_status >> 16) & + SAH_CHA_ERR_STATUS_MASK; + + /* If more than one bit is set (which shouldn't happen), only + * the first will be captured */ + if (CHA_error_status != 0) { + count = 1; + while (CHA_error_status != mask) { + ++count; + mask <<= 1; + } + } + + ret = sah_CHA_Error_Status_Array[count]; + } + } + } + + return ret; +} + +fsl_shw_return_t sah_convert_op_status(uint32_t op_status) +{ + unsigned op_source = (op_status >> 28) & 0x7; + unsigned op_detail = op_status & 0x3f; + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + switch (op_source) { + case 1: /* SKHA */ + /* Can't this have "ICV" error from CCM ?? */ + break; + case 2: /* MDHA */ + if (op_detail == 1) { + ret = FSL_RETURN_AUTH_FAILED_S; + } + break; + case 3: /* RNGA */ + /* Self-test and Compare errors... what to do? */ + break; + case 4: /* PKHA */ + switch (op_detail) { + case 0x01: + ret = FSL_RETURN_PRIME_S; + break; + case 0x02: + ret = FSL_RETURN_NOT_PRIME_S; + break; + case 0x04: + ret = FSL_RETURN_POINT_AT_INFINITY_S; + break; + case 0x08: + ret = FSL_RETURN_POINT_NOT_AT_INFINITY_S; + break; + case 0x10: + ret = FSL_RETURN_GCD_IS_ONE_S; + break; + case 0x20: + ret = FSL_RETURN_GCD_IS_NOT_ONE_S; + break; + default: + break; + } + break; + default: + break; + } + return ret; +} + +#ifdef DIAG_DRV_STATUS + +/*! + * This function logs the diagnostic information for the given error and + * descriptor address. Only used for diagnostic purposes. + * + * @brief (debug only) Log a description of hardware-detected error. + * + * @param descriptor The descriptor address that caused the error + * @param error The SAHARA error code + * @param fault_address Value from the Fault address register + * + * @return void + */ +void sah_Log_Error(uint32_t descriptor, uint32_t error, uint32_t fault_address) +{ + char *source_text; /* verbose error source from register */ + char *address; /* string buffer for descriptor address */ + char *error_log; /* the complete logging message */ + char *cha_log = NULL; /* string buffer for descriptor address */ + char *dma_log = NULL; /* string buffer for descriptor address */ + + uint16_t cha_error = 0; + uint16_t dma_error = 0; + + uint8_t error_source; + sah_Execute_Error return_code; + + /* log error code and descriptor address */ + error_source = error & SAH_ERROR_MASK; + return_code = sah_Execute_Error_Array[error_source]; + + source_text = os_alloc_memory(64, GFP_KERNEL); + + switch (error_source) { + case SAH_ERR_HEADER: + sprintf(source_text, "%s", "Header is not valid"); + break; + + case SAH_ERR_DESC_LENGTH: + sprintf(source_text, "%s", + "Descriptor length not equal to sum of link lengths"); + break; + + case SAH_ERR_DESC_POINTER: + sprintf(source_text, "%s", "Length or pointer " + "field is zero while the other is non-zero"); + break; + + case SAH_ERR_LINK_LENGTH: + /* note that the Sahara Block Guide 2.7 has an invalid explaination + * of this. It only happens when a link length is zero */ + sprintf(source_text, "%s", "A data length is a link is zero"); + break; + + case SAH_ERR_LINK_POINTER: + sprintf(source_text, "%s", + "The data pointer in a link is zero"); + break; + + case SAH_ERR_INPUT_BUFFER: + sprintf(source_text, "%s", "Input Buffer reported an overflow"); + break; + + case SAH_ERR_OUTPUT_BUFFER: + sprintf(source_text, "%s", + "Output Buffer reported an underflow"); + break; + + case SAH_ERR_OUTPUT_BUFFER_STARVATION: + sprintf(source_text, "%s", "Incorrect data in output " + "buffer after CHA has signalled 'done'"); + break; + + case SAH_ERR_INTERNAL_STATE: + sprintf(source_text, "%s", "Internal Hardware Failure"); + break; + + case SAH_ERR_GENERAL_DESCRIPTOR: + sprintf(source_text, "%s", + "Current Descriptor was not legal, but cause is unknown"); + break; + + case SAH_ERR_RESERVED_FIELDS: + sprintf(source_text, "%s", + "Reserved pointer field is non-zero"); + break; + + case SAH_ERR_DESCRIPTOR_ADDRESS: + sprintf(source_text, "%s", + "Descriptor address not word aligned"); + break; + + case SAH_ERR_LINK_ADDRESS: + sprintf(source_text, "%s", "Link address not word aligned"); + break; + + case SAH_ERR_CHA: + sprintf(source_text, "%s", "CHA Error"); + { + char *cha_module = os_alloc_memory(5, GFP_KERNEL); + char *cha_text = os_alloc_memory(45, GFP_KERNEL); + + cha_error = (error >> 28) & SAH_CHA_ERR_SOURCE_MASK; + + switch (cha_error) { + case SAH_CHA_SKHA_ERROR: + sprintf(cha_module, "%s", "SKHA"); + break; + + case SAH_CHA_MDHA_ERROR: + sprintf(cha_module, "%s", "MDHA"); + break; + + case SAH_CHA_RNG_ERROR: + sprintf(cha_module, "%s", "RNG "); + break; + + case SAH_CHA_PKHA_ERROR: + sprintf(cha_module, "%s", "PKHA"); + break; + + case SAH_CHA_NO_ERROR: + /* can't happen */ + /* no break */ + default: + sprintf(cha_module, "%s", "????"); + break; + } + + cha_error = (error >> 16) & SAH_CHA_ERR_STATUS_MASK; + + /* Log CHA Error Status */ + switch (cha_error) { + case SAH_CHA_IP_BUF: + sprintf(cha_text, "%s", + "Non-empty input buffer when done"); + break; + + case SAH_CHA_ADD_ERR: + sprintf(cha_text, "%s", "Illegal address"); + break; + + case SAH_CHA_MODE_ERR: + sprintf(cha_text, "%s", "Illegal mode"); + break; + + case SAH_CHA_DATA_SIZE_ERR: + sprintf(cha_text, "%s", "Illegal data size"); + break; + + case SAH_CHA_KEY_SIZE_ERR: + sprintf(cha_text, "%s", "Illegal key size"); + break; + + case SAH_CHA_PROC_ERR: + sprintf(cha_text, "%s", + "Mode/Context/Key written during processing"); + break; + + case SAH_CHA_CTX_READ_ERR: + sprintf(cha_text, "%s", + "Context read during processing"); + break; + + case SAH_CHA_INTERNAL_HW_ERR: + sprintf(cha_text, "%s", "Internal hardware"); + break; + + case SAH_CHA_IP_BUFF_ERR: + sprintf(cha_text, "%s", + "Input buffer not enabled or underflow"); + break; + + case SAH_CHA_OP_BUFF_ERR: + sprintf(cha_text, "%s", + "Output buffer not enabled or overflow"); + break; + + case SAH_CHA_DES_KEY_ERR: + sprintf(cha_text, "%s", "DES key parity error"); + break; + + case SAH_CHA_RES: + sprintf(cha_text, "%s", "Reserved"); + break; + + case SAH_CHA_NO_ERR: + /* can't happen */ + /* no break */ + default: + sprintf(cha_text, "%s", "Unknown error"); + break; + } + + cha_log = os_alloc_memory(90, GFP_KERNEL); + sprintf(cha_log, + " Module %s encountered the error: %s.", + cha_module, cha_text); + + os_free_memory(cha_module); + os_free_memory(cha_text); + + { + uint32_t mask = 1; + uint32_t count = 0; + + if (cha_error != 0) { + count = 1; + while (cha_error != mask) { + ++count; + mask <<= 1; + } + } + + return_code = sah_CHA_Error_Status_Array[count]; + } + cha_error = 1; + } + break; + + case SAH_ERR_DMA: + sprintf(source_text, "%s", "DMA Error"); + { + char *dma_direction = os_alloc_memory(6, GFP_KERNEL); + char *dma_size = os_alloc_memory(14, GFP_KERNEL); + char *dma_text = os_alloc_memory(250, GFP_KERNEL); + + if ((dma_direction == NULL) || (dma_size == NULL) || + (dma_text == NULL)) { + LOG_KDIAG + ("No memory allocated for DMA debug messages\n"); + } + + /* log DMA error direction */ + sprintf(dma_direction, "%s", + (((error >> 8) & SAH_DMA_ERR_DIR_MASK) == 1) ? + "read" : "write"); + + /* log the size of the DMA transfer error */ + dma_error = (error >> 9) & SAH_DMA_ERR_SIZE_MASK; + switch (dma_error) { + case SAH_DMA_SIZE_BYTE: + sprintf(dma_size, "%s", "byte"); + break; + + case SAH_DMA_SIZE_HALF_WORD: + sprintf(dma_size, "%s", "half-word"); + break; + + case SAH_DMA_SIZE_WORD: + sprintf(dma_size, "%s", "word"); + break; + + case SAH_DMA_SIZE_RES: + sprintf(dma_size, "%s", "reserved size"); + break; + + default: + sprintf(dma_size, "%s", "unknown size"); + break; + } + + /* log DMA error status */ + dma_error = (error >> 12) & SAH_DMA_ERR_STATUS_MASK; + switch (dma_error) { + case SAH_DMA_NO_ERR: + sprintf(dma_text, "%s", "No DMA Error Code"); + break; + + case SAH_DMA_AHB_ERR: + sprintf(dma_text, "%s", + "AHB terminated a bus cycle with an error"); + break; + + case SAH_DMA_IP_ERR: + sprintf(dma_text, "%s", + "Internal IP bus cycle was terminated with an " + "error termination. This would likely be " + "caused by a descriptor length being too " + "large, and thus accessing an illegal " + "internal address. Verify the length field " + "of the current descriptor"); + break; + + case SAH_DMA_PARITY_ERR: + sprintf(dma_text, "%s", + "Parity error detected on DMA command from " + "Descriptor Decoder. Cause is likely to be " + "internal hardware fault"); + break; + + case SAH_DMA_BOUNDRY_ERR: + sprintf(dma_text, "%s", + "DMA was requested to cross a 256 byte " + "internal address boundary. Cause is likely a " + "descriptor length being too large, thus " + "accessing two different internal hardware " + "blocks"); + break; + + case SAH_DMA_BUSY_ERR: + sprintf(dma_text, "%s", + "Descriptor Decoder has made a DMA request " + "while the DMA controller is busy. Cause is " + "likely due to hardware fault"); + break; + + case SAH_DMA_RESERVED_ERR: + sprintf(dma_text, "%s", "Reserved"); + break; + + case SAH_DMA_INT_ERR: + sprintf(dma_text, "%s", + "Internal DMA hardware error detected. The " + "DMA controller has detected an internal " + "condition which should never occur"); + break; + + default: + sprintf(dma_text, "%s", + "Unknown DMA Error Status Code"); + break; + } + + return_code = + sah_DMA_Error_Status_Array[dma_error >> 1]; + dma_error = 1; + + dma_log = os_alloc_memory(320, GFP_KERNEL); + sprintf(dma_log, + " Occurred during a %s operation of a %s transfer: %s.", + dma_direction, dma_size, dma_text); + + os_free_memory(dma_direction); + os_free_memory(dma_size); + os_free_memory(dma_text); + } + break; + + case SAH_ERR_NONE: + default: + sprintf(source_text, "%s", "Unknown Error Code"); + break; + } + + address = os_alloc_memory(35, GFP_KERNEL); + + /* convert error & descriptor address to strings */ + if (dma_error) { + sprintf(address, "Fault address is 0x%08x", fault_address); + } else { + sprintf(address, "Descriptor bus address is 0x%08x", + descriptor); + } + + if (return_code > FSL_INVALID_RETURN) { + return_code = FSL_INVALID_RETURN; + } + + error_log = os_alloc_memory(250, GFP_KERNEL); + + /* construct final log message */ + sprintf(error_log, "Error source = 0x%08x. Return = %s. %s. %s.", + error, sah_return_text[return_code], address, source_text); + + os_free_memory(source_text); + os_free_memory(address); + + /* log standard messages */ + LOG_KDIAG(error_log); + os_free_memory(error_log); + + /* add additional information if available */ + if (cha_error) { + LOG_KDIAG(cha_log); + os_free_memory(cha_log); + } + + if (dma_error) { + LOG_KDIAG(dma_log); + os_free_memory(dma_log); + } + + return; +} /* sah_Log_Error */ + +#endif /* DIAG_DRV_STATUS */ + +/* End of sah_queue_manager.c */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/sah_status_manager.c linux-2.6.26-lab126/drivers/mxc/security/sahara2/sah_status_manager.c --- linux-2.6.26/drivers/mxc/security/sahara2/sah_status_manager.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/sah_status_manager.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,710 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! +* @file sah_status_manager.c +* +* @brief Status Manager Function +* +* This file contains the function which processes the Sahara status register +* during an interrupt. +* +* This file does not need porting. +*/ + +#include "portable_os.h" + +#include +#include +#include +#include +#include + +#if defined(DIAG_DRV_INTERRUPT) && defined(DIAG_DURING_INTERRUPT) +#include +#endif + +/*! Compile-time flag to count various interrupt types. */ +#define DIAG_INT_COUNT + +/*! + * Number of interrupts processed with Done1Done2 status. Updates to this + * value should only be done in interrupt processing. + */ +uint32_t done1_count; + +/*! + * Number of interrupts processed with Done1Busy2 status. Updates to this + * value should only be done in interrupt processing. + */ +uint32_t done1busy2_count; + +/*! + * Number of interrupts processed with Done1Done2 status. Updates to this + * value should only be done in interrupt processing. + */ +uint32_t done1done2_count; + +/*! + * the dynameic power management flag is false when power management is not + * asserted and true when dpm is. + */ +#ifdef SAHARA_POWER_MANAGEMENT +bool sah_dpm_flag = FALSE; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) +static int sah_dpm_suspend(struct device *dev, uint32_t state, uint32_t level); +static int sah_dpm_resume(struct device *dev, uint32_t level); +#else +static int sah_dpm_suspend(struct platform_device *dev, pm_message_t state); +static int sah_dpm_resume(struct platform_device *dev); +#endif +#endif + +#ifndef SAHARA_POLL_MODE +/*! +******************************************************************************* +* This functionx processes the status register of the Sahara, updates the state +* of the finished queue entry, and then tries to find more work for Sahara to +* do. +* +* @brief The bulk of the interrupt handling code. +* +* @param hw_status The status register of Sahara at time of interrupt. +* The Clear interrupt bit is already handled by this +* register read prior to entry into this function. +* @return void +*/ +unsigned long sah_Handle_Interrupt(sah_Execute_Status hw_status) +{ + unsigned long reset_flag = 0; /* assume no SAHARA reset needed */ + os_lock_context_t lock_flags; + + /* HW status at time of interrupt */ + sah_Execute_Status state = hw_status & SAH_EXEC_STATE_MASK; + + do { + sah_Head_Desc *current_entry; + uint32_t dar; + +#ifdef DIAG_INT_COUNT + if (state == SAH_EXEC_DONE1) { + done1_count++; + } else if (state == SAH_EXEC_DONE1_BUSY2) { + done1busy2_count++; + } else if (state == SAH_EXEC_DONE1_DONE2) { + done1done2_count++; + } +#endif + + /* if the first entry on sahara has completed... */ + if ((state & SAH_EXEC_DONE1_BIT) || + (state == SAH_EXEC_ERROR1)) { + /* lock queue while searching */ + os_lock_save_context(desc_queue_lock, lock_flags); + current_entry = + sah_Find_With_State(SAH_STATE_ON_SAHARA); + os_unlock_restore_context(desc_queue_lock, lock_flags); + + /* an active descriptor was not found */ + if (current_entry == NULL) { + /* change state to avoid an infinite loop (possible if + * state is SAH_EXEC_DONE1_BUSY2 first time into loop) */ + hw_status = SAH_EXEC_IDLE; +#if defined(DIAG_DRV_INTERRUPT) && defined(DIAG_DURING_INTERRUPT) + LOG_KDIAG + ("Interrupt received with nothing on queue."); +#endif + } else { + /* SAHARA has completed its work on this descriptor chain */ + current_entry->status = SAH_STATE_OFF_SAHARA; + + if (state == SAH_EXEC_ERROR1) { + if (hw_status & STATUS_ERROR) { + /* Gather extra diagnostic information */ + current_entry->fault_address = + sah_HW_Read_Fault_Address(); + /* Read this last - it clears the error */ + current_entry->error_status = + sah_HW_Read_Error_Status(); + current_entry->op_status = 0; +#ifdef FSL_HAVE_SAHARA4 + } else { + current_entry->op_status = + sah_HW_Read_Op_Status(); + current_entry->error_status = 0; +#endif + } + + } else { + /* indicate that no errors were found with descriptor + * chain 1 */ + current_entry->error_status = 0; + current_entry->op_status = 0; + + /* is there a second, successfully, completed descriptor + * chain? (done1/error2 processing is handled later) */ + if (state == SAH_EXEC_DONE1_DONE2) { + os_lock_save_context + (desc_queue_lock, + lock_flags); + current_entry = + sah_Find_With_State + (SAH_STATE_ON_SAHARA); + os_unlock_restore_context + (desc_queue_lock, + lock_flags); + + if (current_entry == NULL) { +#if defined(DIAG_DRV_INTERRUPT) && defined(DIAG_DURING_INTERRUPT) + LOG_KDIAG + ("Done1_Done2 Interrupt received with " + "one entry on queue."); +#endif + } else { + /* indicate no errors in descriptor chain 2 */ + current_entry-> + error_status = 0; + current_entry->status = + SAH_STATE_OFF_SAHARA; + } + } + } + } + +#ifdef SAHARA_POWER_MANAGEMENT + /* check dynamic power management is not asserted */ + if (!sah_dpm_flag) { +#endif + do { + /* protect DAR and main_queue */ + os_lock_save_context(desc_queue_lock, + lock_flags); + dar = sah_HW_Read_DAR(); + /* check if SAHARA has space for another descriptor. SAHARA + * only accepts up to the DAR queue size number of DAR + * entries, after that 'dar' will not be zero until the + * pending interrupt is serviced */ + if (dar == 0) { + current_entry = + sah_Find_With_State + (SAH_STATE_PENDING); + if (current_entry != NULL) { +#ifndef SUBMIT_MULTIPLE_DARS + /* BUG FIX: state machine can transition from Done1 + * Busy2 directly to Idle. To fix that problem, + * only one DAR is being allowed on SAHARA at a + * time. If a high level interrupt has happened, + * there could * be an active descriptor chain */ + if (sah_Find_With_State + (SAH_STATE_ON_SAHARA) + == NULL) { +#endif +#if defined(DIAG_DRV_IF) && defined(DIAG_DURING_INTERRUPT) + sah_Dump_Chain + (¤t_entry-> + desc, + current_entry-> + desc. + dma_addr); +#endif /* DIAG_DRV_IF */ + sah_HW_Write_DAR + (current_entry-> + desc. + dma_addr); + current_entry-> + status = + SAH_STATE_ON_SAHARA; +#ifndef SUBMIT_MULTIPLE_DARS + } + current_entry = NULL; /* exit loop */ +#endif + } + } + os_unlock_restore_context + (desc_queue_lock, lock_flags); + } while ((dar == 0) && (current_entry != NULL)); +#ifdef SAHARA_POWER_MANAGEMENT + } /* sah_device_power_manager */ +#endif + } else { + if (state == SAH_EXEC_FAULT) { + sah_Head_Desc *previous_entry; /* point to chain 1 */ + /* Address of request when fault occured */ + uint32_t bad_dar = sah_HW_Read_IDAR(); + + reset_flag = 1; /* SAHARA needs to be reset */ + + /* get first of possible two descriptor chain that was + * on SAHARA */ + os_lock_save_context(desc_queue_lock, + lock_flags); + previous_entry = + sah_Find_With_State(SAH_STATE_ON_SAHARA); + os_unlock_restore_context(desc_queue_lock, + lock_flags); + + /* if it exists, continue processing the fault */ + if (previous_entry) { + /* assume this chain didn't complete correctly */ + previous_entry->error_status = -1; + previous_entry->status = + SAH_STATE_OFF_SAHARA; + + /* get the second descriptor chain */ + os_lock_save_context(desc_queue_lock, + lock_flags); + current_entry = + sah_Find_With_State + (SAH_STATE_ON_SAHARA); + os_unlock_restore_context + (desc_queue_lock, lock_flags); + + /* if it exists, continue processing both chains */ + if (current_entry) { + /* assume this chain didn't complete correctly */ + current_entry->error_status = + -1; + current_entry->status = + SAH_STATE_OFF_SAHARA; + + /* now see if either can be identified as the one + * in progress when the fault occured */ + if (current_entry->desc. + dma_addr == bad_dar) { + /* the second descriptor chain was active when the + * fault occured, so the first descriptor chain + * was successfull */ + previous_entry-> + error_status = 0; + } else { + if (previous_entry-> + desc.dma_addr == + bad_dar) { + /* if the first chain was in progress when the + * fault occured, the second has not yet been + * touched, so reset it to PENDING */ + current_entry-> + status = + SAH_STATE_PENDING; + } + } + } + } +#if defined(DIAG_DRV_INTERRUPT) && defined(DIAG_DURING_INTERRUPT) + } else { + /* shouldn't ever get here */ + if (state == SAH_EXEC_BUSY) { + LOG_KDIAG + ("Got Sahara interrupt in Busy state"); + } else { + if (state == SAH_EXEC_IDLE) { + LOG_KDIAG + ("Got Sahara interrupt in Idle state"); + } else { + LOG_KDIAG + ("Got Sahara interrupt in unknown state"); + } + } +#endif + } + } + + /* haven't handled the done1/error2 (the error 2 part), so setup to + * do that now. Otherwise, exit loop */ + state = (state == SAH_EXEC_DONE1_ERROR2) ? + SAH_EXEC_ERROR1 : SAH_EXEC_IDLE; + + /* Keep going while further status is available. */ + } while (state == SAH_EXEC_ERROR1); + + return reset_flag; +} + +#endif /* ifndef SAHARA_POLL_MODE */ + +#ifdef SAHARA_POLL_MODE +/*! +******************************************************************************* +* Submits descriptor chain to SAHARA, polls on SAHARA for completion, process +* results, and dephysicalizes chain +* +* @brief Handle poll mode. +* +* @param entry Virtual address of a physicalized chain +* +* @return 0 this function is always successful +*/ + +unsigned long sah_Handle_Poll(sah_Head_Desc * entry) +{ + sah_Execute_Status hw_status; /* Sahara's status register */ + os_lock_context_t lock_flags; + + /* lock SARAHA */ + os_lock_save_context(desc_queue_lock, lock_flags); + +#ifdef SAHARA_POWER_MANAGEMENT + /* check if the dynamic power management is asserted */ + if (sah_dpm_flag) { + /* return that request failed to be processed */ + entry->result = FSL_RETURN_ERROR_S; + entry->fault_address = 0xBAD; + entry->op_status= 0xBAD; + entry->error_status = 0xBAD; + } else { +#endif /* SAHARA_POWER_MANAGEMENT */ + +#if defined(DIAG_DRV_IF) + sah_Dump_Chain(&entry->desc, entry->desc.dma_addr); +#endif /* DIAG_DRV_IF */ + /* Nothing can be in the dar if we got the lock */ + sah_HW_Write_DAR((uint32_t) (entry->desc.dma_addr)); + + /* Wait for SAHARA to finish with this entry */ + hw_status = sah_Wait_On_Sahara(); + + /* if entry completed successfully, mark it as such */ + /**** HARDWARE ERROR WORK AROUND (hw_status == SAH_EXEC_IDLE) *****/ + if ( +#ifndef SUBMIT_MULTIPLE_DARS + (hw_status == SAH_EXEC_IDLE) || (hw_status == SAH_EXEC_DONE1_BUSY2) || /* should not happen */ +#endif + (hw_status == SAH_EXEC_DONE1) + ) { + entry->error_status = 0; + entry->result = FSL_RETURN_OK_S; + } else { + /* SAHARA is reporting an error with entry */ + if (hw_status == SAH_EXEC_ERROR1) { + /* Gather extra diagnostic information */ + entry->fault_address = + sah_HW_Read_Fault_Address(); + /* Read this register last - it clears the error */ + entry->error_status = + sah_HW_Read_Error_Status(); + entry->op_status = 0; + /* translate from SAHARA error status to fsl_shw return values */ + entry->result = + sah_convert_error_status(entry-> + error_status); +#ifdef DIAG_DRV_STATUS + sah_Log_Error(entry->op_status, + entry->error_status, + entry->fault_address); +#endif + } else if (hw_status == SAH_EXEC_OPSTAT1) { + entry->op_status = sah_HW_Read_Op_Status(); + entry->error_status = 0; + entry->result = + sah_convert_op_status(op_status); + } else { + /* SAHARA entered FAULT state (or something bazaar has + * happened) */ + pr_debug + ("Sahara: hw_status = 0x%x; Stat: 0x%08x; IDAR: 0x%08x; " + "CDAR: 0x%08x; FltAdr: 0x%08x; Estat: 0x%08x\n", + hw_status, sah_HW_Read_Status(), + sah_HW_Read_IDAR(), sah_HW_Read_CDAR(), + sah_HW_Read_Fault_Address(), + sah_HW_Read_Error_Status()); +#ifdef DIAG_DRV_IF + { + int old_level = console_loglevel; + console_loglevel = 8; + sah_Dump_Chain(&(entry->desc), + entry->desc.dma_addr); + console_loglevel = old_level; + } +#endif + + entry->error_status = -1; + entry->result = FSL_RETURN_ERROR_S; + sah_HW_Reset(); + } + } +#ifdef SAHARA_POWER_MANAGEMENT + } +#endif + + if (!(entry->uco_flags & FSL_UCO_BLOCKING_MODE)) { + /* put it in results pool to allow get_results to work */ + sah_Queue_Append_Entry(&entry->user_info->result_pool, entry); + if (entry->uco_flags & FSL_UCO_CALLBACK_MODE) { + /* invoke callback */ + entry->user_info->callback(entry->user_info); + } + } else { + /* convert the descriptor link back to virtual memory, mark dirty pages + * if they are from user mode, and release the page cache for user + * pages + */ + entry = sah_DePhysicalise_Descriptors(entry); + } + + os_unlock_restore_context(desc_queue_lock, lock_flags); + + return 0; +} + +#endif /* SAHARA_POLL_MODE */ + +/****************************************************************************** +* The following is the implementation of the Dynamic Power Management +* functionality. +******************************************************************************/ +#ifdef SAHARA_POWER_MANAGEMENT + +static bool sah_dpm_init_flag; + +/* dynamic power management information for the sahara driver */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) +static struct device_driver sah_dpm_driver = { + .name = "sahara_", + .bus = &platform_bus_type, +#else +static struct platform_driver sah_dpm_driver = { + .driver.name = "sahara_", + .driver.bus = &platform_bus_type, +#endif + .suspend = sah_dpm_suspend, + .resume = sah_dpm_resume +}; + +/* dynamic power management information for the sahara HW device */ +static struct platform_device sah_dpm_device = { + .name = "sahara_", + .id = 1, +}; + +/*! +******************************************************************************* +* Initilaizes the dynamic power managment functionality +* +* @brief Initialization of the Dynamic Power Management functionality +* +* @return 0 = success; failed otherwise +*/ +int sah_dpm_init() +{ + int status; + + /* dpm is not asserted */ + sah_dpm_flag = FALSE; + + /* register the driver to the kernel */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + status = os_register_to_driver(&sah_dpm_driver); +#else + status = os_register_to_driver(&sah_dpm_driver.driver); +#endif + + if (status == 0) { + /* register a single sahara chip */ + /*status = platform_device_register(&sah_dpm_device); */ + status = os_register_a_device(&sah_dpm_device); + + /* if something went awry, unregister the driver */ + if (status != 0) { + /*driver_unregister(&sah_dpm_driver); */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + os_unregister_from_driver(&sah_dpm_driver); +#else + os_unregister_from_driver(&sah_dpm_driver.driver); +#endif + sah_dpm_init_flag = FALSE; + } else { + /* if everything went okay, flag that life is good */ + sah_dpm_init_flag = TRUE; + } + } + + /* let the kernel know how it went */ + return status; + +} + +/*! +******************************************************************************* +* Unregister the dynamic power managment functionality +* +* @brief Unregister the Dynamic Power Management functionality +* +*/ +void sah_dpm_close() +{ + /* if dynamic power management was initilaized, kill it */ + if (sah_dpm_init_flag == TRUE) { + /*driver_unregister(&sah_dpm_driver); */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + os_unregister_from_driver(&sah_dpm_driver); +#else + os_unregister_from_driver(&sah_dpm_driver.driver); +#endif + /*platform_device_register(&sah_dpm_device); */ + os_unregister_a_device(&sah_dpm_device); + } +} + +/*! +******************************************************************************* +* Callback routine defined by the Linux Device Model / Dynamic Power management +* extension. It sets a global flag to disallow the driver to enter queued items +* into Sahara's DAR. +* +* It allows the current active descriptor chains to complete before it returns +* +* @brief Suspends the driver +* +* @param dev contains device information +* @param state contains state information +* @param level level of shutdown +* +* @return 0 = success; failed otherwise +*/ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) +static int sah_dpm_suspend(struct device *dev, uint32_t state, uint32_t level) +#else +static int sah_dpm_suspend(struct platform_device *dev, pm_message_t state) +#endif +{ + sah_Head_Desc *entry = NULL; + os_lock_context_t lock_flags; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + switch (level) { + case SUSPEND_DISABLE: + /* Assert dynamic power management. This stops the driver from + * entering queued requests to Sahara */ + sah_dpm_flag = TRUE; + break; + + case SUSPEND_SAVE_STATE: + break; + + case SUSPEND_POWER_DOWN: + /* hopefully between the DISABLE call and this one, the outstanding + * work Sahara was doing complete. this checks (and waits) for + * those entries that were already active on Sahara to complete */ + /* lock queue while searching */ + os_lock_save_context(desc_queue_lock, lock_flags); + do { + entry = sah_Find_With_State(SAH_STATE_ON_SAHARA); + } while (entry != NULL); + os_unlock_restore_context(desc_queue_lock, lock_flags); + + /* now we kill the clock so the control circuitry isn't sucking + * any power */ + mxc_clks_disable(SAHARA2_CLK); + break; + } +#else + /* Assert dynamic power management. This stops the driver from + * entering queued requests to Sahara */ + sah_dpm_flag = TRUE; + + /* Now wait for any outstanding work Sahara was doing to complete. + * this checks (and waits) for + * those entries that were already active on Sahara to complete */ + do { + /* lock queue while searching */ + os_lock_save_context(desc_queue_lock, lock_flags); + entry = sah_Find_With_State(SAH_STATE_ON_SAHARA); + os_unlock_restore_context(desc_queue_lock, lock_flags); + } while (entry != NULL); + + /* now we kill the clock so the control circuitry isn't sucking + * any power */ + { + struct clk *clk = clk_get(NULL, "sahara_clk"); + if (clk != ERR_PTR(ENOENT)) { + clk_disable(clk); + } + } +#endif + + return 0; +} + +/*! +******************************************************************************* +* Callback routine defined by the Linux Device Model / Dynamic Power management +* extension. It cleears a global flag to allow the driver to enter queued items +* into Sahara's DAR. +* +* It primes the mechanism to start depleting the queue +* +* @brief Resumes the driver +* +* @param dev contains device information +* @param level level of resumption +* +* @return 0 = success; failed otherwise +*/ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) +static int sah_dpm_resume(struct device *dev, uint32_t level) +#else +static int sah_dpm_resume(struct platform_device *dev) +#endif +{ + sah_Head_Desc *entry = NULL; + os_lock_context_t lock_flags; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + switch (level) { + case RESUME_POWER_ON: + /* enable Sahara's clock */ + mxc_clks_enable(SAHARA2_CLK); + break; + + case RESUME_RESTORE_STATE: + break; + + case RESUME_ENABLE: + /* Disable dynamic power managment. This allows the driver to put + * entries into Sahara's DAR */ + sah_dpm_flag = FALSE; + + /* find a pending entry to prime the pump */ + os_lock_save_context(desc_queue_lock, lock_flags); + entry = sah_Find_With_State(SAH_STATE_PENDING); + if (entry != NULL) { + sah_Queue_Manager_Prime(entry); + } + os_unlock_restore_context(desc_queue_lock, lock_flags); + break; + } +#else + { + /* enable Sahara's clock */ + struct clk *clk = clk_get(NULL, "sahara_clk"); + + if (clk != ERR_PTR(ENOENT)) { + clk_enable(clk); + } + } + sah_dpm_flag = FALSE; + + /* find a pending entry to prime the pump */ + os_lock_save_context(desc_queue_lock, lock_flags); + entry = sah_Find_With_State(SAH_STATE_PENDING); + if (entry != NULL) { + sah_Queue_Manager_Prime(entry); + } + os_unlock_restore_context(desc_queue_lock, lock_flags); +#endif + return 0; +} + +#endif /* SAHARA_POWER_MANAGEMENT */ diff -urN linux-2.6.26/drivers/mxc/security/sahara2/sf_util.c linux-2.6.26-lab126/drivers/mxc/security/sahara2/sf_util.c --- linux-2.6.26/drivers/mxc/security/sahara2/sf_util.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/sahara2/sf_util.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,1396 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/** +* @file sf_util.c +* +* @brief Security Functions component API - Utility functions +* +* These are the 'Sahara api' functions which are used by the higher-level +* FSL SHW API to build and then execute descriptor chains. +*/ + + +#include "sf_util.h" +#include + +#ifdef DIAG_SECURITY_FUNC +#include +#endif /*DIAG_SECURITY_FUNC*/ + + +#ifdef __KERNEL__ +EXPORT_SYMBOL(sah_Append_Desc); +EXPORT_SYMBOL(sah_Append_Link); +EXPORT_SYMBOL(sah_Create_Link); +EXPORT_SYMBOL(sah_Create_Key_Link); +EXPORT_SYMBOL(sah_Destroy_Link); +EXPORT_SYMBOL(sah_Descriptor_Chain_Execute); +EXPORT_SYMBOL(sah_insert_mdha_algorithm); +EXPORT_SYMBOL(sah_insert_skha_algorithm); +EXPORT_SYMBOL(sah_insert_skha_mode); +EXPORT_SYMBOL(sah_insert_skha_modulus); +EXPORT_SYMBOL(sah_Descriptor_Chain_Destroy); +EXPORT_SYMBOL(sah_add_two_in_desc); +EXPORT_SYMBOL(sah_add_in_key_desc); +EXPORT_SYMBOL(sah_add_two_out_desc); +EXPORT_SYMBOL(sah_add_in_out_desc); +EXPORT_SYMBOL(sah_add_key_out_desc); +#endif + +#ifdef DEBUG_REWORK +#ifndef __KERNEL__ +#include +#define os_printk printf +#endif +#endif + +/** + * Convert fsl_shw_hash_alg_t to mdha mode bits. + * + * Index must be maintained in order of fsl_shw_hash_alg_t enumeration!!! + */ +const uint32_t sah_insert_mdha_algorithm[] = +{ + [FSL_HASH_ALG_MD5] = sah_insert_mdha_algorithm_md5, + [FSL_HASH_ALG_SHA1] = sah_insert_mdha_algorithm_sha1, + [FSL_HASH_ALG_SHA224] = sah_insert_mdha_algorithm_sha224, + [FSL_HASH_ALG_SHA256] = sah_insert_mdha_algorithm_sha256, +}; + +/** + * Header bits for Algorithm field of SKHA header + * + * Index value must be kept in sync with fsl_shw_key_alg_t + */ +const uint32_t sah_insert_skha_algorithm[] = +{ + [FSL_KEY_ALG_HMAC] = 0x00000040, + [FSL_KEY_ALG_AES] = sah_insert_skha_algorithm_aes, + [FSL_KEY_ALG_DES] = sah_insert_skha_algorithm_des, + [FSL_KEY_ALG_TDES] = sah_insert_skha_algorithm_tdes, + [FSL_KEY_ALG_ARC4] = sah_insert_skha_algorithm_arc4, +}; + + +/** + * Header bits for MODE field of SKHA header + * + * Index value must be kept in sync with fsl_shw_sym_mod_t + */ +const uint32_t sah_insert_skha_mode[] = +{ + [FSL_SYM_MODE_STREAM] = sah_insert_skha_mode_ecb, + [FSL_SYM_MODE_ECB] = sah_insert_skha_mode_ecb, + [FSL_SYM_MODE_CBC] = sah_insert_skha_mode_cbc, + [FSL_SYM_MODE_CTR] = sah_insert_skha_mode_ctr, +}; + + +/** + * Header bits to set CTR modulus size. These have parity + * included to allow XOR insertion of values. + * + * @note Must be kept in sync with fsl_shw_ctr_mod_t + */ +const uint32_t sah_insert_skha_modulus[] = +{ + [FSL_CTR_MOD_8] = 0x00000000, /**< 2**8 */ + [FSL_CTR_MOD_16] = 0x80000200, /**< 2**16 */ + [FSL_CTR_MOD_24] = 0x80000400, /**< 2**24 */ + [FSL_CTR_MOD_32] = 0x00000600, /**< 2**32 */ + [FSL_CTR_MOD_40] = 0x80000800, /**< 2**40 */ + [FSL_CTR_MOD_48] = 0x00000a00, /**< 2**48 */ + [FSL_CTR_MOD_56] = 0x00000c00, /**< 2**56 */ + [FSL_CTR_MOD_64] = 0x80000e00, /**< 2**64 */ + [FSL_CTR_MOD_72] = 0x80001000, /**< 2**72 */ + [FSL_CTR_MOD_80] = 0x00001200, /**< 2**80 */ + [FSL_CTR_MOD_88] = 0x00001400, /**< 2**88 */ + [FSL_CTR_MOD_96] = 0x80001600, /**< 2**96 */ + [FSL_CTR_MOD_104] = 0x00001800, /**< 2**104 */ + [FSL_CTR_MOD_112] = 0x80001a00, /**< 2**112 */ + [FSL_CTR_MOD_120] = 0x80001c00, /**< 2**120 */ + [FSL_CTR_MOD_128] = 0x00001e00 /**< 2**128 */ +}; + + +/****************************************************************************** +* Internal function declarations +******************************************************************************/ +static fsl_shw_return_t sah_Create_Desc( + const sah_Mem_Util *mu, + sah_Desc ** desc, + int head, + uint32_t header, + sah_Link * link1, + sah_Link * link2); + + +/** + * Create a descriptor chain using the the header and links passed in as + * parameters. The newly created descriptor will be added to the end of + * the descriptor chain passed. + * + * If @a desc_head points to a NULL value, then a sah_Head_Desc will be created + * as the first descriptor. Otherwise a sah_Desc will be created and appended. + * + * @pre + * + * - None + * + * @post + * + * - A descriptor has been created from the header, link1 and link2. + * + * - The newly created descriptor has been appended to the end of + * desc_head, or its location stored into the location pointed to by + * @a desc_head. + * + * - On allocation failure, @a link1 and @a link2 will be destroyed., and + * @a desc_head will be untouched. + * + * @brief Create and append descriptor chain, inserting header and links + * pointing to link1 and link2 + * + * @param mu Memory functions + * @param header Value of descriptor header to be added + * @param desc_head Pointer to head of descriptor chain to append new desc + * @param link1 Pointer to sah_Link 1 (or NULL) + * @param link2 Pointer to sah_Link 2 (or NULL) + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_Append_Desc( + const sah_Mem_Util *mu, + sah_Head_Desc **desc_head, + const uint32_t header, + sah_Link *link1, + sah_Link *link2) +{ + fsl_shw_return_t status; + sah_Desc *desc; + sah_Desc *desc_ptr; + + + status = sah_Create_Desc(mu, (sah_Desc**)&desc, (*desc_head == NULL), + header, link1, link2); + /* append newly created descriptor to end of current chain */ + if (status == FSL_RETURN_OK_S) { + if (*desc_head == NULL) { + (*desc_head) = (sah_Head_Desc*)desc; + (*desc_head)->out1_ptr = NULL; + (*desc_head)->out2_ptr = NULL; + + } else { + desc_ptr = (sah_Desc*)*desc_head; + while (desc_ptr->next != NULL) { + desc_ptr = desc_ptr->next; + } + desc_ptr->next = desc; + } + } + + return status; +} + + +/** + * Releases the memory allocated by the Security Function library for + * descriptors, links and any internally allocated memory referenced in the + * given chain. Note that memory allocated by user applications is not + * released. + * + * @post The @a desc_head pointer will be set to NULL to prevent further use. + * + * @brief Destroy a descriptor chain and free memory of associated links + * + * @param mu Memory functions + * @param desc_head Pointer to head of descriptor chain to be freed + * + * @return none + */ +void sah_Descriptor_Chain_Destroy ( + const sah_Mem_Util *mu, + sah_Head_Desc **desc_head) +{ + sah_Desc *desc_ptr = &(*desc_head)->desc; + sah_Head_Desc *desc_head_ptr = (sah_Head_Desc *)desc_ptr; + + while (desc_ptr != NULL) { + register sah_Desc *next_desc_ptr; + + if (desc_ptr->ptr1 != NULL) { + sah_Destroy_Link(mu, desc_ptr->ptr1); + } + if (desc_ptr->ptr2 != NULL) { + sah_Destroy_Link(mu, desc_ptr->ptr2); + } + + next_desc_ptr = desc_ptr->next; + + /* Be sure to free head descriptor as such */ + if (desc_ptr == (sah_Desc*)desc_head_ptr) { + mu->mu_free_head_desc(mu->mu_ref, desc_head_ptr); + } else { + mu->mu_free_desc(mu->mu_ref, desc_ptr); + } + + desc_ptr = next_desc_ptr; + } + + *desc_head = NULL; +} + + +#ifndef NO_INPUT_WORKAROUND +/** + * Reworks the link chain + * + * @brief Reworks the link chain + * + * @param mu Memory functions + * @param link Pointer to head of link chain to be reworked + * + * @return none + */ +static fsl_shw_return_t sah_rework_link_chain( + const sah_Mem_Util *mu, + sah_Link* link) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + int found_potential_problem = 0; + uint32_t total_data = 0; +#ifdef DEBUG_REWORK + sah_Link* first_link = link; +#endif + + if ((link->flags & SAH_OUTPUT_LINK)) { + return status; + } + + while (link != NULL) { + total_data += link->len; + + /* Only non-key Input Links are affected by the DMA flush-to-FIFO + * problem */ + + /* If have seen problem and at end of chain... */ + if (found_potential_problem && (link->next == NULL) && + (total_data > 16)) { + /* insert new 1-byte link */ + sah_Link* new_tail_link = mu->mu_alloc_link(mu->mu_ref); + if (new_tail_link == NULL) { + status = FSL_RETURN_NO_RESOURCE_S; + } else { +#ifdef DEBUG_REWORK + sah_Link* dump_link = first_link; + while (dump_link != NULL) { + uint32_t i; + unsigned bytes_to_dump = (dump_link->len > 32) ? + 32 : dump_link->len; + os_printk("(rework)Link %p: %p/%u/%p\n", dump_link, + dump_link->data, dump_link->len, + dump_link->next); + if (!(dump_link->flags & SAH_STORED_KEY_INFO)) { + os_printk("(rework)Data %p: ", dump_link->data); + for (i = 0; i < bytes_to_dump; i++) { + os_printk("%02X ", dump_link->data[i]); + } + os_printk("\n"); + } + else { + os_printk("rework)Data %p: Red key data\n", dump_link); + } + dump_link = dump_link->next; + } +#endif + link->len--; + link->next = new_tail_link; + new_tail_link->len = 1; + new_tail_link->data = link->data+link->len; + new_tail_link->flags = link->flags & ~(SAH_OWNS_LINK_DATA); + new_tail_link->next = NULL; + link = new_tail_link; +#ifdef DEBUG_REWORK + os_printk("(rework)New link chain:\n"); + dump_link = first_link; + while (dump_link != NULL) { + uint32_t i; + unsigned bytes_to_dump = (dump_link->len > 32) ? + 32 : dump_link->len; + + os_printk("Link %p: %p/%u/%p\n", dump_link, + dump_link->data, dump_link->len, + dump_link->next); + if (!(dump_link->flags & SAH_STORED_KEY_INFO)) { + os_printk("Data %p: ", dump_link->data); + for (i = 0; i < bytes_to_dump; i++) { + os_printk("%02X ", dump_link->data[i]); + } + os_printk("\n"); + } + else { + os_printk("Data %p: Red key data\n", dump_link); + } + dump_link = dump_link->next; + } +#endif + } + } else if ((link->len % 4) || ((uint32_t)link->data % 4)) { + found_potential_problem = 1; + } + + link = link->next; + } + + return status; +} + + +/** + * Rework links to avoid H/W bug + * + * @param head Beginning of descriptor chain + * + * @return A return code of type #fsl_shw_return_t. + */ +static fsl_shw_return_t sah_rework_links( + const sah_Mem_Util *mu, + sah_Head_Desc *head) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Desc* desc = &head->desc; + + while ((status == FSL_RETURN_OK_S) && (desc != NULL)) { + if (desc->header & SAH_HDR_LLO) { + status = FSL_RETURN_ERROR_S; + break; + } + if (desc->ptr1 != NULL) { + status = sah_rework_link_chain(mu, desc->ptr1); + } + if ((status == FSL_RETURN_OK_S) && (desc->ptr2 != NULL)) { + status = sah_rework_link_chain(mu, desc->ptr2); + } + desc = desc->next; + } + + return status; +} +#endif /* NO_INPUT_WORKAROUND */ + + +/** + * Send a descriptor chain to the SAHARA driver for processing. + * + * Note that SAHARA will read the input data from and write the output data + * directly to the locations indicated during construction of the chain. + * + * @pre + * + * - None + * + * @post + * + * - @a head will have been executed on SAHARA + * - @a head Will be freed unless a SAVE flag is set + * + * @brief Execute a descriptor chain + * + * @param head Pointer to head of descriptor chain to be executed + * @param user_ctx The user context on which to execute the descriptor chain. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_Descriptor_Chain_Execute( + sah_Head_Desc *head, + fsl_shw_uco_t *user_ctx) +{ + fsl_shw_return_t status; + + /* Check for null pointer or non-multiple-of-four value */ + if ((head == NULL) || ((uint32_t)head & 0x3)) { + status = FSL_RETURN_ERROR_S; + goto out; + } + +#ifndef NO_INPUT_WORKAROUND + status = sah_rework_links(user_ctx->mem_util, head); + if (status != FSL_RETURN_OK_S) { + goto out; + } +#endif + + /* complete the information in the descriptor chain head node */ + head->user_ref = user_ctx->user_ref; + head->uco_flags = user_ctx->flags; + head->next = NULL; /* driver will use this to link chain heads */ + + status = adaptor_Exec_Descriptor_Chain(head, user_ctx); + +#ifdef DIAG_SECURITY_FUNC + if (status == FSL_RETURN_OK_S) + LOG_DIAG("after exec desc chain: status is ok\n"); + else + LOG_DIAG("after exec desc chain: status is not ok\n"); +#endif + + out: + return status; +} + + +/** + * Create Link + * + * @brief Allocate Memory for Link structure and populate using input + * parameters + * + * @post On allocation failure, @a p will be freed if #SAH_OWNS_LINK_DATA is + * p set in @a flags. + + * @param mu Memory functions + * @param link Pointer to link to be created + * @param p Pointer to data to use in link + * @param length Length of buffer 'p' in bytes + * @param flags Indicates whether memory has been allocated by the calling + * function or the security function + * + * @return FSL_RETURN_OK_S or FSL_RETURN_NO_RESOURCE_S + */ +fsl_shw_return_t sah_Create_Link( + const sah_Mem_Util *mu, + sah_Link **link, + uint8_t *p, + const size_t length, + const sah_Link_Flags flags) +{ + +#ifdef DIAG_SECURITY_FUNC + + char diag[50]; +#endif /*DIAG_SECURITY_FUNC_UGLY*/ + fsl_shw_return_t status = FSL_RETURN_NO_RESOURCE_S; + + + *link = mu->mu_alloc_link(mu->mu_ref); + + /* populate link if memory allocation successful */ + if (*link != NULL) { + (*link)->len = length; + (*link)->data = p; + (*link)->next = NULL; + (*link)->flags = flags; + status = FSL_RETURN_OK_S; + +#ifdef DIAG_SECURITY_FUNC + + LOG_DIAG("Created Link"); + LOG_DIAG("------------"); + sprintf(diag," address = 0x%x", (int) *link); + LOG_DIAG(diag); + sprintf(diag," link->len = %d",(*link)->len); + LOG_DIAG(diag); + sprintf(diag," link->data = 0x%x",(int) (*link)->data); + LOG_DIAG(diag); + sprintf(diag," link->flags = 0x%x",(*link)->flags); + LOG_DIAG(diag); + LOG_DIAG(" link->next = NULL"); +#endif /*DIAG_SECURITY_FUNC_UGLY*/ + + } else { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Allocation of memory for sah_Link failed!\n"); +#endif /*DIAG_SECURITY_FUNC*/ + + /* Free memory previously allocated by the security function layer for + link data. Note that the memory being pointed to will be zeroed before + being freed, for security reasons. */ + if (flags & SAH_OWNS_LINK_DATA) { + mu->mu_memset(mu->mu_ref, p, 0x00, length); + mu->mu_free(mu->mu_ref, p); + } + } + + return status; +} + + +/** + * Create Key Link + * + * @brief Allocate Memory for Link structure and populate using key info + * object + * + * @param mu Memory functions + * @param link Pointer to store address of link to be created + * @param key_info Pointer to Key Info object to be referenced + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_Create_Key_Link( + const sah_Mem_Util *mu, + sah_Link **link, + fsl_shw_sko_t *key_info) +{ +#ifdef DIAG_SECURITY_FUNC_UGLY + char diag[50]; +#endif /*DIAG_SECURITY_FUNC_UGLY*/ + fsl_shw_return_t status = FSL_RETURN_NO_RESOURCE_S; + sah_Link_Flags flags = 0; + + + *link = mu->mu_alloc_link(mu->mu_ref); + + /* populate link if memory allocation successful */ + if (*link != NULL) { + (*link)->len = key_info->key_length; + + if (key_info->flags & FSL_SKO_KEY_PRESENT) { + (*link)->data = key_info->key; + status = FSL_RETURN_OK_S; + } else { + if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) { + + if (key_info->keystore == NULL) { + /* System Keystore */ + (*link)->slot = key_info->handle; + (*link)->ownerid = key_info->userid; + (*link)->data = 0; + flags |= SAH_STORED_KEY_INFO; + status = FSL_RETURN_OK_S; + } else { +#ifdef FSL_HAVE_SCC2 + /* User Keystore */ + fsl_shw_kso_t *keystore = key_info->keystore; + /* Note: the key data is stored here, but the address has to + * be converted to a partition and offset in the kernel. + * This will be calculated in kernel space, based on the + * list of partitions held by the users context. + */ + (*link)->data = + keystore->slot_get_address(keystore->user_data, + key_info->handle); + + flags |= SAH_IN_USER_KEYSTORE; + status = FSL_RETURN_OK_S; +#else + /* User keystores only supported in SCC2 */ + status = FSL_RETURN_BAD_FLAG_S; +#endif /* FSL_HAVE_SCC2 */ + + } + } else { + /* the flag is bad. Should never get here */ + status = FSL_RETURN_BAD_FLAG_S; + } + } + + (*link)->next = NULL; + (*link)->flags = flags; + +#ifdef DIAG_SECURITY_FUNC_UGLY + if (status == FSL_RETURN_OK_S) { + LOG_DIAG("Created Link"); + LOG_DIAG("------------"); + sprintf(diag," address = 0x%x", (int) *link); + LOG_DIAG(diag); + sprintf(diag," link->len = %d", (*link)->len); + LOG_DIAG(diag); + if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) { + sprintf(diag," link->slot = 0x%x", (*link)->slot); + LOG_DIAG(diag); + } else { + sprintf(diag," link->data = 0x%x", (int)(*link)->data); + LOG_DIAG(diag); + } + sprintf(diag," link->flags = 0x%x", (*link)->flags); + LOG_DIAG(diag); + LOG_DIAG(" link->next = NULL"); + } +#endif /*DIAG_SECURITY_FUNC_UGLY*/ + + if (status == FSL_RETURN_BAD_FLAG_S) { + mu->mu_free_link(mu->mu_ref, *link); + *link = NULL; +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Creation of sah_Key_Link failed due to bad key flag!\n"); +#endif /*DIAG_SECURITY_FUNC*/ + } + + } else { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Allocation of memory for sah_Key_Link failed!\n"); +#endif /*DIAG_SECURITY_FUNC*/ + } + + return status; +} + + +/** + * Append Link + * + * @brief Allocate Memory for Link structure and append it to the end of + * the link chain. + * + * @post On allocation failure, @a p will be freed if #SAH_OWNS_LINK_DATA is + * p set in @a flags. + * + * @param mu Memory functions + * @param link_head Pointer to (head of) existing link chain + * @param p Pointer to data to use in link + * @param length Length of buffer 'p' in bytes + * @param flags Indicates whether memory has been allocated by the calling + * function or the security function + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_Append_Link( + const sah_Mem_Util *mu, + sah_Link *link_head, + uint8_t *p, + const size_t length, + const sah_Link_Flags flags) +{ + sah_Link* new_link; + fsl_shw_return_t status; + + + status = sah_Create_Link(mu, &new_link, p, length, flags); + + if (status == FSL_RETURN_OK_S) { + /* chase for the tail */ + while (link_head->next != NULL) { + link_head = link_head->next; + } + + /* and add new tail */ + link_head->next = new_link; + } + + return status; +} + + +/** + * Create and populate a single descriptor + * + * The pointer and length fields will be be set based on the chains passed in + * as @a link1 and @a link2. + * + * @param mu Memory utility suite + * @param desc Location to store pointer of new descriptor + * @param head_desc Non-zero if this will be first in chain; zero otherwise + * @param header The Sahara header value to store in the descriptor + * @param link1 A value (or NULL) for the first ptr + * @param link2 A value (or NULL) for the second ptr + * + * @post If allocation succeeded, the @a link1 and @link2 will be linked into + * the descriptor. If allocation failed, those link structues will be + * freed, and the @a desc will be unchanged. + * + * @return A return code of type #fsl_shw_return_t. + */ +static fsl_shw_return_t sah_Create_Desc( + const sah_Mem_Util *mu, + sah_Desc ** desc, + int head_desc, + uint32_t header, + sah_Link * link1, + sah_Link * link2) +{ + fsl_shw_return_t status = FSL_RETURN_NO_RESOURCE_S; +#ifdef DIAG_SECURITY_FUNC_UGLY + char diag[50]; +#endif /*DIAG_SECURITY_FUNC_UGLY*/ + + + if (head_desc != 0) { + *desc = (sah_Desc *)mu->mu_alloc_head_desc(mu->mu_ref); + } else { + *desc = mu->mu_alloc_desc(mu->mu_ref); + } + + /* populate descriptor if memory allocation successful */ + if ((*desc) != NULL) { + sah_Link* temp_link; + + status = FSL_RETURN_OK_S; + (*desc)->header = header; + + temp_link = (*desc)->ptr1 = link1; + (*desc)->len1 = 0; + while (temp_link != NULL) { + (*desc)->len1 += temp_link->len; + temp_link = temp_link->next; + } + + temp_link = (*desc)->ptr2 = link2; + (*desc)->len2 = 0; + while (temp_link != NULL) { + (*desc)->len2 += temp_link->len; + temp_link = temp_link->next; + } + + (*desc)->next = NULL; + +#ifdef DIAG_SECURITY_FUNC_UGLY + LOG_DIAG("Created Desc"); + LOG_DIAG("------------"); + sprintf(diag," address = 0x%x",(int) *desc); + LOG_DIAG(diag); + sprintf(diag," desc->header = 0x%x",(*desc)->header); + LOG_DIAG(diag); + sprintf(diag," desc->len1 = %d",(*desc)->len1); + LOG_DIAG(diag); + sprintf(diag," desc->ptr1 = 0x%x",(int) ((*desc)->ptr1)); + LOG_DIAG(diag); + sprintf(diag," desc->len2 = %d",(*desc)->len2); + LOG_DIAG(diag); + sprintf(diag," desc->ptr2 = 0x%x",(int) ((*desc)->ptr2)); + LOG_DIAG(diag); + sprintf(diag," desc->next = 0x%x",(int) ((*desc)->next)); + LOG_DIAG(diag); +#endif /*DIAG_SECURITY_FUNC_UGLY*/ + } else { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Allocation of memory for sah_Desc failed!\n"); +#endif /*DIAG_SECURITY_FUNC*/ + + /* Destroy the links, otherwise the memory allocated by the Security + Function layer for the links (and possibly the data within the links) + will be lost */ + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } + + return status; +} + + +/** + * Destroy a link (chain) and free memory + * + * @param mu memory utility suite + * @param link The Link to destroy + * + * @return none + */ +void sah_Destroy_Link( + const sah_Mem_Util *mu, + sah_Link * link) +{ + + while (link != NULL) { + sah_Link * next_link = link->next; + + if (link->flags & SAH_OWNS_LINK_DATA) { + /* zero data for security purposes */ + mu->mu_memset(mu->mu_ref, link->data, 0x00, link->len); + mu->mu_free(mu->mu_ref, link->data); + } + + link->data = NULL; + link->next = NULL; + mu->mu_free_link(mu->mu_ref, link); + + link = next_link; + } +} + + +/** + * Add descriptor where both links are inputs. + * + * @param header The Sahara header value for the descriptor. + * @param in1 The first input buffer (or NULL) + * @param in1_length Size of @a in1 + * @param[out] in2 The second input buffer (or NULL) + * @param in2_length Size of @a in2 + * @param mu Memory functions + * @param[in,out] desc_chain Chain to start or append to + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_add_two_in_desc(uint32_t header, + const uint8_t* in1, + uint32_t in1_length, + const uint8_t* in2, + uint32_t in2_length, + const sah_Mem_Util* mu, + sah_Head_Desc** desc_chain) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Link* link1 = NULL; + sah_Link* link2 = NULL; + + printk("Entering sah_add_two_in_desc \n"); + + if (in1 != NULL) { + status = sah_Create_Link(mu, &link1, + (sah_Oct_Str) in1, in1_length, + SAH_USES_LINK_DATA); + } + + if ( (in2 != NULL) && (status == FSL_RETURN_OK_S) ) { + status = sah_Create_Link(mu, &link2, + (sah_Oct_Str) in2, in2_length, + SAH_USES_LINK_DATA); + } + + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } else { + status = sah_Append_Desc(mu, desc_chain, header, link1, link2); + } + + return status; +} + +/*! + * Add descriptor where neither link needs sync + * + * @param header The Sahara header value for the descriptor. + * @param in1 The first input buffer (or NULL) + * @param in1_length Size of @a in1 + * @param[out] in2 The second input buffer (or NULL) + * @param in2_length Size of @a in2 + * @param mu Memory functions + * @param[in,out] desc_chain Chain to start or append to + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_add_two_d_desc(uint32_t header, + const uint8_t * in1, + uint32_t in1_length, + const uint8_t * in2, + uint32_t in2_length, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + + printk("Entering sah_add_two_d_desc \n"); + + if (in1 != NULL) { + status = sah_Create_Link(mu, &link1, + (sah_Oct_Str) in1, in1_length, + SAH_USES_LINK_DATA); + } + + if ((in2 != NULL) && (status == FSL_RETURN_OK_S)) { + status = sah_Create_Link(mu, &link2, + (sah_Oct_Str) in2, in2_length, + SAH_USES_LINK_DATA); + } + + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } else { + status = sah_Append_Desc(mu, desc_chain, header, link1, link2); + } + + return status; +} /* sah_add_two_d_desc() */ + +/** + * Add descriptor where both links are inputs, the second one being a key. + * + * @param header The Sahara header value for the descriptor. + * @param in1 The first input buffer (or NULL) + * @param in1_length Size of @a in1 + * @param[out] in2 The second input buffer (or NULL) + * @param in2_length Size of @a in2 + * @param mu Memory functions + * @param[in,out] desc_chain Chain to start or append to + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_add_in_key_desc(uint32_t header, + const uint8_t* in1, + uint32_t in1_length, + fsl_shw_sko_t* key_info, + const sah_Mem_Util* mu, + sah_Head_Desc** desc_chain) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + + if (in1 != NULL) { + status = sah_Create_Link(mu, &link1, + (sah_Oct_Str) in1, in1_length, + SAH_USES_LINK_DATA); + } + + if (status != FSL_RETURN_OK_S) { + goto out; + } + + status = sah_Create_Key_Link(mu, &link2, key_info); + + + if (status != FSL_RETURN_OK_S) { + goto out; + } + + status = sah_Append_Desc(mu, desc_chain, header, link1, link2); + +out: + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } + + return status; +} + + +/** + * Create two links using keys allocated in the scc + * + * @param header The Sahara header value for the descriptor. + * @param in1 The first input buffer (or NULL) + * @param in1_length Size of @a in1 + * @param[out] in2 The second input buffer (or NULL) + * @param in2_length Size of @a in2 + * @param mu Memory functions + * @param[in,out] desc_chain Chain to start or append to + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_add_key_key_desc(uint32_t header, + fsl_shw_sko_t *key_info1, + fsl_shw_sko_t *key_info2, + const sah_Mem_Util *mu, + sah_Head_Desc **desc_chain) +{ + fsl_shw_return_t status; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + + + status = sah_Create_Key_Link(mu, &link1, key_info1); + + if (status == FSL_RETURN_OK_S) { + status = sah_Create_Key_Link(mu, &link2, key_info2); + } + + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } else { + status = sah_Append_Desc(mu, desc_chain, header, link1, link2); + } + + return status; +} + + +/** + * Add descriptor where first link is input, the second is a changing key + * + * @param header The Sahara header value for the descriptor. + * @param in1 The first input buffer (or NULL) + * @param in1_length Size of @a in1 + * @param[out] in2 The key for output + * @param mu Memory functions + * @param[in,out] desc_chain Chain to start or append to + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_add_in_keyout_desc(uint32_t header, + const uint8_t* in1, + uint32_t in1_length, + fsl_shw_sko_t* key_info, + const sah_Mem_Util* mu, + sah_Head_Desc** desc_chain) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + + if (in1 != NULL) { + status = sah_Create_Link(mu, &link1, + (sah_Oct_Str) in1, in1_length, + SAH_USES_LINK_DATA); + } + + if (status != FSL_RETURN_OK_S) { + goto out; + } + + status = sah_Create_Key_Link(mu, &link2, key_info); + + if (status != FSL_RETURN_OK_S) { + goto out; + } + +link2->flags |= SAH_OUTPUT_LINK; /* mark key for output */ +status = sah_Append_Desc(mu, desc_chain, header, link1, link2); + +out: + + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } + + return status; +} + +/** + * Add descriptor where both links are outputs. + * + * @param header The Sahara header value for the descriptor. + * @param out1 The first output buffer (or NULL) + * @param out1_length Size of @a out1 + * @param[out] out2 The second output buffer (or NULL) + * @param out2_length Size of @a out2 + * @param mu Memory functions + * @param[in,out] desc_chain Chain to start or append to + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_add_two_out_desc(uint32_t header, + uint8_t* out1, + uint32_t out1_length, + uint8_t* out2, + uint32_t out2_length, + const sah_Mem_Util* mu, + sah_Head_Desc** desc_chain) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + + + printk("Entering sah_add_two_out_desc \n"); + + if (out1 != NULL) { + status = sah_Create_Link(mu, &link1, + (sah_Oct_Str) out1, out1_length, + SAH_OUTPUT_LINK | + SAH_USES_LINK_DATA); + } + + if ( (out2 != NULL) && (status == FSL_RETURN_OK_S) ) { + status = sah_Create_Link(mu, &link2, + (sah_Oct_Str) out2, out2_length, + SAH_OUTPUT_LINK | + SAH_USES_LINK_DATA); + } + + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } else { + status = sah_Append_Desc(mu, desc_chain, header, link1, link2); + } + + return status; +} + + +/** + * Add descriptor where first link is output, second is output + * + * @param header The Sahara header value for the descriptor. + * @param out1 The first output buffer (or NULL) + * @param out1_length Size of @a out1 + * @param[out] in2 The input buffer (or NULL) + * @param in2_length Size of @a in2 + * @param mu Memory functions + * @param[in,out] desc_chain Chain to start or append to + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_add_out_in_desc(uint32_t header, + uint8_t* out1, + uint32_t out1_length, + const uint8_t* in2, + uint32_t in2_length, + const sah_Mem_Util* mu, + sah_Head_Desc** desc_chain) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + + + if (out1 != NULL) { + status = sah_Create_Link(mu, &link1, + (sah_Oct_Str) out1, out1_length, + SAH_OUTPUT_LINK | + SAH_USES_LINK_DATA); + } + + if ( (in2 != NULL) && (status == FSL_RETURN_OK_S) ) { + status = sah_Create_Link(mu, &link2, + (sah_Oct_Str) in2, in2_length, + SAH_USES_LINK_DATA); + } + + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } else { + status = sah_Append_Desc(mu, desc_chain, header, link1, link2); + } + + return status; +} + + +/** + * Add descriptor where link1 is input buffer, link2 is output buffer. + * + * @param header The Sahara header value for the descriptor. + * @param in The input buffer + * @param in_length Size of the input buffer + * @param[out] out The output buffer + * @param out_length Size of the output buffer + * @param mu Memory functions + * @param[in,out] desc_chain Chain to start or append to + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_add_in_out_desc(uint32_t header, + const uint8_t* in, uint32_t in_length, + uint8_t* out, uint32_t out_length, + const sah_Mem_Util* mu, + sah_Head_Desc** desc_chain) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + + if (in != NULL) { + status = sah_Create_Link(mu, &link1, + (sah_Oct_Str) in, in_length, + SAH_USES_LINK_DATA); + } + + if ((status == FSL_RETURN_OK_S) && (out != NULL)) { + status = sah_Create_Link(mu, &link2, + (sah_Oct_Str) out, out_length, + SAH_OUTPUT_LINK | + SAH_USES_LINK_DATA); + } + + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } else { + status = sah_Append_Desc(mu, desc_chain, header, link1, link2); + } + + return status; +} + + +/** + * Add descriptor where link1 is a key, link2 is output buffer. + * + * @param header The Sahara header value for the descriptor. + * @param key_info Key information + * @param[out] out The output buffer + * @param out_length Size of the output buffer + * @param mu Memory functions + * @param[in,out] desc_chain Chain to start or append to + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_add_key_out_desc(uint32_t header, + const fsl_shw_sko_t *key_info, + uint8_t* out, uint32_t out_length, + const sah_Mem_Util *mu, + sah_Head_Desc **desc_chain) +{ + fsl_shw_return_t status; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + + status = sah_Create_Key_Link(mu, &link1, (fsl_shw_sko_t *) key_info); + if (status != FSL_RETURN_OK_S) { + goto out; + } + + + if (out != NULL) { + status = sah_Create_Link(mu, &link2, + (sah_Oct_Str) out, out_length, + SAH_OUTPUT_LINK | + SAH_USES_LINK_DATA); + if (status != FSL_RETURN_OK_S) { + goto out; + } + } +status = sah_Append_Desc(mu, desc_chain, header, link1, link2); + +out: + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } + + return status; +} + + +/** + * Sanity checks the user context object fields to ensure that they make some + * sense before passing the uco as a parameter + * + * @brief Verify the user context object + * + * @param uco user context object + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_validate_uco(fsl_shw_uco_t *uco) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + + + /* check if file is opened */ + if (uco->sahara_openfd < 0) { + status = FSL_RETURN_NO_RESOURCE_S; + } else { + /* check flag combination: the only invalid setting of the + * blocking and callback flags is blocking with callback. So check + * for that + */ + if ((uco->flags & (FSL_UCO_BLOCKING_MODE | FSL_UCO_CALLBACK_MODE)) == + (FSL_UCO_BLOCKING_MODE | FSL_UCO_CALLBACK_MODE)) { + status = FSL_RETURN_BAD_FLAG_S; + } else { + /* check that memory utilities have been attached */ + if (uco->mem_util == NULL) { + status = FSL_RETURN_MEMORY_ERROR_S; + } else { + /* must have pool of at least 1, even for blocking mode */ + if (uco->pool_size == 0) { + status = FSL_RETURN_ERROR_S; + } else { + /* if callback flag is set, it better have a callback + * routine */ + if (uco->flags & FSL_UCO_CALLBACK_MODE) { + if (uco->callback == NULL) { + status = FSL_RETURN_INTERNAL_ERROR_S; + } + } + } + } + } + } + + return status; +} + + +/** + * Perform any post-processing on non-blocking results. + * + * For instance, free descriptor chains, compare authentication codes, ... + * + * @param user_ctx User context object + * @param result_info A set of results + */ +void sah_Postprocess_Results(fsl_shw_uco_t* user_ctx, sah_results* result_info) +{ + unsigned i; + + /* for each result returned */ + for (i = 0; i < *result_info->actual; i++) { + sah_Head_Desc* desc = result_info->results[i].user_desc; + uint8_t* out1 = desc->out1_ptr; + uint8_t* out2 = desc->out2_ptr; + uint32_t len = desc->out_len; + + /* + * For now, tne only post-processing besides freeing the + * chain is the need to check the auth code for fsl_shw_auth_decrypt(). + * + * If other uses are required in the future, this code will probably + * need a flag in the sah_Head_Desc (or a function pointer!) to + * determine what needs to be done. + */ + if ((out1 != NULL) && (out2 != NULL)) { + unsigned j; + for (j = 0; j < len; j++) { + if (out1[j] != out2[j]) { + /* Problem detected. Change result. */ + result_info->results[i].code = FSL_RETURN_AUTH_FAILED_S; + break; + } + } + /* free allocated 'calced_auth' */ + user_ctx->mem_util-> + mu_free(user_ctx->mem_util->mu_ref, out1); + } + + /* Free the API-created chain, unless tagged as not-from-API */ + if (! (desc->uco_flags & FSL_UCO_SAVE_DESC_CHAIN)) { + sah_Descriptor_Chain_Destroy(user_ctx->mem_util, &desc); + } + } +} + + +/* End of sf_util.c */ diff -urN linux-2.6.26/drivers/mxc/security/scc2_driver.c linux-2.6.26-lab126/drivers/mxc/security/scc2_driver.c --- linux-2.6.26/drivers/mxc/security/scc2_driver.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/scc2_driver.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,2261 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! @file scc2_driver.c + * + * This is the driver code for the Security Controller version 2 (SCC2). It's + * interaction with the Linux kernel is from calls to #scc_init() when the + * driver is loaded, and #scc_cleanup() should the driver be unloaded. The + * driver uses locking and (task-sleep/task-wakeup) functions from the kernel. + * It also registers itself to handle the interrupt line(s) from the SCC. New + * to this version of the driver is an interface providing access to the secure + * partitions. This is in turn exposed to the API user through the + * fsl_shw_smalloc() series of functions. Other drivers in the kernel may use + * the remaining API functions to get at the services of the SCC. The main + * service provided is the Secure Memory, which allows encoding and decoding of + * secrets with a per-chip secret key. + * + * The SCC is single-threaded, and so is this module. When the scc_crypt() + * routine is called, it will lock out other accesses to the function. If + * another task is already in the module, the subsequent caller will spin on a + * lock waiting for the other access to finish. + * + * Note that long crypto operations could cause a task to spin for a while, + * preventing other kernel work (other than interrupt processing) to get done. + * + * The external (kernel module) interface is through the following functions: + * @li scc_get_configuration() @li scc_crypt() @li scc_zeroize_memories() @li + * scc_monitor_security_failure() @li scc_stop_monitoring_security_failure() + * @li scc_set_sw_alarm() @li scc_read_register() @li scc_write_register() @li + * scc_allocate_partition() @li scc_initialize_partition @li + * scc_release_partition() @li scc_diminish_permissions @li + * scc_encrypt_region() @li scc_decrypt_region() @li scc_virt_to_phys + * + * All other functions are internal to the driver. + */ + +#include "scc2_internals.h" +#include "sahara2/include/portable_os.h" +#include + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) + +#include +#include +#include + +#else + +#include +#include +#include + +#endif + +#include + +/** + * This is the set of errors which signal that access to the SCM RAM has + * failed or will fail. + */ +#define SCM_ACCESS_ERRORS \ + (SCM_ERRSTAT_ILM | SCM_ERRSTAT_SUP | SCM_ERRSTAT_ERC_MASK) + +/****************************************************************************** + * + * Global / Static Variables + * + *****************************************************************************/ + +#ifdef SCC_REGISTER_DEBUG + +#define REG_PRINT_BUFFER_SIZE 200 + +static char reg_print_buffer[REG_PRINT_BUFFER_SIZE]; + +typedef char *(*reg_print_routine_t) (uint32_t value, char *print_buffer, + int buf_size); + +#endif + +/** + * This is type void* so that a) it cannot directly be dereferenced, + * and b) pointer arithmetic on it will function in a 'normal way' for + * the offsets in scc_defines.h + * + * scc_base is the location in the iomap where the SCC's registers + * (and memory) start. + * + * The referenced data is declared volatile so that the compiler will + * not make any assumptions about the value of registers in the SCC, + * and thus will always reload the register into CPU memory before + * using it (i.e. wherever it is referenced in the driver). + * + * This value should only be referenced by the #SCC_READ_REGISTER and + * #SCC_WRITE_REGISTER macros and their ilk. All dereferences must be + * 32 bits wide. + */ +static volatile void *scc_base; + +/** Array to hold function pointers registered by + #scc_monitor_security_failure() and processed by + #scc_perform_callbacks() */ +static void (*scc_callbacks[SCC_CALLBACK_SIZE]) (void); +/*SCC need IRAM's base address but use only the partitions allocated for it.*/ +uint32_t scm_ram_phys_base = IRAM_BASE_ADDR; + +void *scm_ram_base = NULL; + +/** Calculated once for quick reference to size of the unreserved space in + * RAM in SCM. + */ +uint32_t scm_memory_size_bytes; + +/** Structure returned by #scc_get_configuration() */ +static scc_config_t scc_configuration = { + .driver_major_version = SCC_DRIVER_MAJOR_VERSION, + .driver_minor_version = SCC_DRIVER_MINOR_VERSION_2, + .scm_version = -1, + .smn_version = -1, + .block_size_bytes = -1, + .partition_size_bytes = -1, + .partition_count = -1, +}; + +/** Internal flag to know whether SCC is in Failed state (and thus many + * registers are unavailable). Once it goes failed, it never leaves it. */ +static volatile enum scc_status scc_availability = SCC_STATUS_INITIAL; + +/** Flag to say whether interrupt handler has been registered for + * SMN interrupt */ +static int smn_irq_set = 0; + +/** Flag to say whether interrupt handler has been registered for + * SCM interrupt */ +static int scm_irq_set = 0; + +/** This lock protects the #scc_callbacks list as well as the @c + * callbacks_performed flag in #scc_perform_callbacks. Since the data this + * protects may be read or written from either interrupt or base level, all + * operations should use the irqsave/irqrestore or similar to make sure that + * interrupts are inhibited when locking from base level. + */ +static os_lock_t scc_callbacks_lock = NULL; + +/** + * Ownership of this lock prevents conflicts on the crypto operation in the + * SCC. + */ +static os_lock_t scc_crypto_lock = NULL; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)) +/** Pointer to SCC's clock information. Initialized during scc_init(). */ +static struct clk *scc_clk = NULL; +#endif + +/** The lookup table for an 8-bit value. Calculated once + * by #scc_init_ccitt_crc(). + */ +static uint16_t scc_crc_lookup_table[256]; + +/****************************************************************************** + * + * Function Implementations - Externally Accessible + * + *****************************************************************************/ + +/** + * Allocate a partition of secure memory + * + * @param smid_value Value to use for the SMID register. Must be 0 for + * kernel mode access. + * @param[out] part_no (If successful) Assigned partition number. + * @param[out] part_base Kernel virtual address of the partition. + * @param[out] part_phys Physical address of the partition. + * + * @return + */ +scc_return_t scc_allocate_partition(uint32_t smid_value, + int *part_no, + void **part_base, uint32_t *part_phys) +{ + uint32_t i; + os_lock_context_t irq_flags = 0; /* for IRQ save/restore */ + int local_part; + scc_return_t retval = SCC_RET_FAIL; + void *base_addr = NULL; + uint32_t reg_value; + + local_part = -1; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + if (scc_availability == SCC_STATUS_UNIMPLEMENTED) { + goto out; + } + + /* ACQUIRE LOCK to prevent others from using crypto or acquiring a + * partition. Note that crypto operations could take a long time, so the + * calling process could potentially spin for some time. + */ + os_lock_save_context(scc_crypto_lock, irq_flags); + + do { + /* Find current state of partition ownership */ + reg_value = SCC_READ_REGISTER(SCM_PART_OWNERS_REG); + + /* Search for a free one */ + for (i = 0; i < scc_configuration.partition_count; i++) { + if (((reg_value >> (SCM_POWN_SHIFT * i)) + & SCM_POWN_MASK) == SCM_POWN_PART_FREE) { + break; /* found a free one */ + } + } + if (i == local_part) { + /* found this one last time, and failed to allocated it */ + pr_debug(KERN_ERR "Partition %d cannot be allocated\n", + i); + goto out; + } + if (i >= scc_configuration.partition_count) { + retval = SCC_RET_INSUFFICIENT_SPACE; /* all used up */ + goto out; + } + + pr_debug + ("SCC2: Attempting to allocate partition %i, owners:%08x\n", + i, SCC_READ_REGISTER(SCM_PART_OWNERS_REG)); + + local_part = i; + /* Store SMID to grab a partition */ + SCC_WRITE_REGISTER(SCM_SMID0_REG + + SCM_SMID_WIDTH * (local_part), smid_value); + mdelay(2); + + /* Now make sure it is ours... ? */ + reg_value = SCC_READ_REGISTER(SCM_PART_OWNERS_REG); + + if (((reg_value >> (SCM_POWN_SHIFT * (local_part))) + & SCM_POWN_MASK) != SCM_POWN_PART_OWNED) { + continue; /* try for another */ + } + base_addr = scm_ram_base + + (local_part * scc_configuration.partition_size_bytes); + break; + } while (1); + +out: + + /* Free the lock */ + os_unlock_restore_context(scc_callbacks_lock, irq_flags); + + /* If the base address was assigned, then a partition was successfully + * acquired. + */ + if (base_addr != NULL) { + pr_debug("SCC2 Part owners: %08x, engaged: %08x\n", + reg_value, SCC_READ_REGISTER(SCM_PART_ENGAGED_REG)); + pr_debug("SCC2 MAP for part %d: %08x\n", + local_part, + SCC_READ_REGISTER(SCM_ACC0_REG + 8 * local_part)); + + /* Copy the partition information to the data structures passed by the + * user. + */ + *part_no = local_part; + *part_base = base_addr; + *part_phys = (uint32_t) scm_ram_phys_base + + (local_part * scc_configuration.partition_size_bytes); + retval = SCC_RET_OK; + + pr_debug + ("SCC2 partition engaged. Kernel address: %p. Physical " + "address: %p, pfn: %08x\n", *part_base, (void *)*part_phys, + __phys_to_pfn(*part_phys)); + } + + return retval; +} /* allocate_partition() */ + +/** + * Release a partition of secure memory + * + * @param part_base Kernel virtual address of the partition to be released. + * + * @return SCC_RET_OK if successful. + */ +scc_return_t scc_release_partition(void *part_base) +{ + uint32_t partition_no; + + if (part_base == NULL) { + return SCC_RET_FAIL; + } + + /* Ensure that this is a proper partition location */ + partition_no = SCM_PART_NUMBER((uint32_t) part_base); + + pr_debug("SCC2: Attempting to release partition %i, owners:%08x\n", + partition_no, SCC_READ_REGISTER(SCM_PART_OWNERS_REG)); + + /* check that the partition is ours to de-establish */ + if (!host_owns_partition(partition_no)) { + return SCC_RET_FAIL; + } + + /* TODO: The state of the zeroize engine (SRS field in the Command Status + * Register) should be examined before issuing the zeroize command here. + * To make the driver thread-safe, a lock should be taken out before + * issuing the check and released after the zeroize command has been + * issued. + */ + + /* Zero the partition to release it */ + scc_write_register(SCM_ZCMD_REG, + (partition_no << SCM_ZCMD_PART_SHIFT) | + (ZCMD_DEALLOC_PART << SCM_ZCMD_CCMD_SHIFT)); + mdelay(2); + + pr_debug("SCC2: done releasing partition %i, owners:%08x\n", + partition_no, SCC_READ_REGISTER(SCM_PART_OWNERS_REG)); + + /* Check that the de-assignment went correctly */ + if (host_owns_partition(partition_no)) { + return SCC_RET_FAIL; + } + + return SCC_RET_OK; +} + +/** + * Diminish the permissions on a partition of secure memory + * + * @param part_base Kernel virtual address of the partition. + * @param permissions ORed values of the type SCM_PERM_* which will be used as + * initial partition permissions. SHW API users should use + * the FSL_PERM_* definitions instead. + * + * @return SCC_RET_OK if successful. + */ +scc_return_t scc_diminish_permissions(void *part_base, uint32_t permissions) +{ + uint32_t partition_no; + uint32_t permissions_requested; + permissions_requested = permissions; + + /* ensure that this is a proper partition location */ + partition_no = SCM_PART_NUMBER((uint32_t) part_base); + + /* invert the permissions, masking out unused bits */ + permissions = (~permissions) & SCM_PERM_MASK; + + /* attempt to diminish the permissions */ + scc_write_register(SCM_ACC0_REG + 8 * partition_no, permissions); + mdelay(2); + + /* Reading it back puts it into the original form */ + permissions = SCC_READ_REGISTER(SCM_ACC0_REG + 8 * partition_no); + if (permissions == permissions_requested) { + pr_debug("scc_partition_diminish_perms: successful\n"); + pr_debug("scc_partition_diminish_perms: successful\n"); + return SCC_RET_OK; + } + pr_debug("scc_partition_diminish_perms: not successful\n"); + + return SCC_RET_FAIL; +} + +extern scc_partition_status_t scc_partition_status(void *part_base) +{ + uint32_t part_no; + uint32_t part_owner; + + /* Determine the partition number from the address */ + part_no = SCM_PART_NUMBER((uint32_t) part_base); + + /* Check if the partition is implemented */ + if (part_no >= scc_configuration.partition_count) { + return SCC_PART_S_UNUSABLE; + } + + /* Determine the value of the partition owners register */ + part_owner = (SCC_READ_REGISTER(SCM_PART_OWNERS_REG) + >> (part_no * SCM_POWN_SHIFT)) & SCM_POWN_MASK; + + switch (part_owner) { + case SCM_POWN_PART_OTHER: + return SCC_PART_S_UNAVAILABLE; + break; + case SCM_POWN_PART_FREE: + return SCC_PART_S_AVAILABLE; + break; + case SCM_POWN_PART_OWNED: + /* could be allocated or engaged*/ + if (partition_engaged(part_no)) { + return SCC_PART_S_ENGAGED; + } else { + return SCC_PART_S_ALLOCATED; + } + break; + case SCM_POWN_PART_UNUSABLE: + default: + return SCC_PART_S_UNUSABLE; + break; + } +} + +/** + * Calculate the physical address from the kernel virtual address. + * + * @param address Kernel virtual address of data in an Secure Partition. + * @return Physical address of said data. + */ +uint32_t scc_virt_to_phys(void *address) +{ + return (uint32_t) address - (uint32_t) scm_ram_base + + (uint32_t) scm_ram_phys_base; +} + +/** + * Engage partition of secure memory + * + * @param part_base (kernel) Virtual + * @param UMID NULL, or 16-byte UMID for partition security + * @param permissions ORed values from fsl_shw_permission_t which + * will be used as initial partiition permissions. + * + * @return SCC_RET_OK if successful. + */ + +scc_return_t +scc_engage_partition(void *part_base, + const uint8_t *UMID, uint32_t permissions) +{ + uint32_t partition_no; + uint8_t *UMID_base = part_base + 0x10; + uint32_t *MAP_base = part_base; + uint8_t i; + + partition_no = SCM_PART_NUMBER((uint32_t) part_base); + + if (!host_owns_partition(partition_no) || + partition_engaged(partition_no) || + !(SCC_READ_REGISTER(SCM_SMID0_REG + (partition_no * 8)) == 0)) { + + return SCC_RET_FAIL; + } + + if (UMID != NULL) { + for (i = 0; i < 16; i++) { + UMID_base[i] = UMID[i]; + } + } + + MAP_base[0] = permissions; + + udelay(20); + + /* Check that the partition was engaged correctly, and that it has the + * proper permissions. + */ + + if ((!partition_engaged(partition_no)) || + (permissions != + SCC_READ_REGISTER(SCM_ACC0_REG + 8 * partition_no))) { + return SCC_RET_FAIL; + } + + return SCC_RET_OK; +} + +/*****************************************************************************/ +/* fn scc_init() */ +/*****************************************************************************/ +/** + * Initialize the driver at boot time or module load time. + * + * Register with the kernel as the interrupt handler for the SCC interrupt + * line(s). + * + * Map the SCC's register space into the driver's memory space. + * + * Query the SCC for its configuration and status. Save the configuration in + * #scc_configuration and save the status in #scc_availability. Called by the + * kernel. + * + * Do any locking/wait queue initialization which may be necessary. + * + * The availability fuse may be checked, depending on platform. + */ +static int scc_init(void) +{ + uint32_t smn_status; + int i; + int return_value = -EIO; /* assume error */ + + if (scc_availability == SCC_STATUS_INITIAL) { + + /* Set this until we get an initial reading */ + scc_availability = SCC_STATUS_CHECKING; + + /* Initialize the constant for the CRC function */ + scc_init_ccitt_crc(); + + /* initialize the callback table */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + scc_callbacks[i] = 0; + } + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) + mxc_clks_enable(SCC_CLK); +#else + scc_clk = clk_get(NULL, "scc_clk"); + if (scc_clk != ERR_PTR(ENOENT)) { + clk_enable(scc_clk); + } +#endif + + /* Set up the hardware access locks */ + scc_callbacks_lock = os_lock_alloc_init(); + scc_crypto_lock = os_lock_alloc_init(); + if (scc_callbacks_lock == NULL || scc_crypto_lock == NULL) { + os_printk(KERN_ERR + "SCC2: Failed to allocate context locks. Exiting.\n"); + goto out; + } + + /* See whether there is an SCC available */ + if (0 && !SCC_ENABLED()) { + os_printk(KERN_ERR + "SCC2: Fuse for SCC is set to disabled. Exiting.\n"); + goto out; + } + /* Map the SCC (SCM and SMN) memory on the internal bus into + kernel address space */ + scc_base = (void *)IO_ADDRESS(SCC_BASE); + if (scc_base == NULL) { + os_printk(KERN_ERR + "SCC2: Register mapping failed. Exiting.\n"); + goto out; + } + + /* If that worked, we can try to use the SCC */ + /* Get SCM into 'clean' condition w/interrupts cleared & + disabled */ + SCC_WRITE_REGISTER(SCM_INT_CTL_REG, 0); + + /* Clear error status register */ + (void)SCC_READ_REGISTER(SCM_ERR_STATUS_REG); + + /* + * There is an SCC. Determine its current state. Side effect + * is to populate scc_config and scc_availability + */ + smn_status = scc_grab_config_values(); + + /* Try to set up interrupt handler(s) */ + if (scc_availability != SCC_STATUS_OK) { + goto out; + } + + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) + scm_ram_phys_base += 0x8000; + + scm_ram_base = (void *)ioremap_nocache(scm_ram_phys_base, + scc_configuration. + partition_count * + scc_configuration. + partition_size_bytes); + if (scm_ram_base == NULL) { + os_printk(KERN_ERR + "SCC2: RAM failed to remap: %p for %d bytes\n", + (void *)scm_ram_phys_base, + scc_configuration.partition_count * + scc_configuration.partition_size_bytes); + goto out; + } + pr_debug("SCC2: RAM at Physical %p / Virtual %p\n", + (void *)scm_ram_phys_base, scm_ram_base); + + pr_debug("Secure Partition Table: Found %i partitions\n", + scc_configuration.partition_count); + + if (setup_interrupt_handling() != 0) { + unsigned err_cond; + /** + * The error could be only that the SCM interrupt was + * not set up. This interrupt is always masked, so + * that is not an issue. + * The SMN's interrupt may be shared on that line, it + * may be separate, or it may not be wired. Do what + * is necessary to check its status. + * Although the driver is coded for possibility of not + * having SMN interrupt, the fact that there is one + * means it should be available and used. + */ +#ifdef USE_SMN_INTERRUPT + err_cond = !smn_irq_set; /* Separate. Check SMN binding */ +#elif !defined(NO_SMN_INTERRUPT) + err_cond = !scm_irq_set; /* Shared. Check SCM binding */ +#else + err_cond = FALSE; /* SMN not wired at all. Ignore. */ +#endif + if (err_cond) { + /* setup was not able to set up SMN interrupt */ + scc_availability = SCC_STATUS_UNIMPLEMENTED; + goto out; + } + } + + /* interrupt handling returned non-zero */ + /* Get SMN into 'clean' condition w/interrupts cleared & + enabled */ + SCC_WRITE_REGISTER(SMN_COMMAND_REG, + SMN_COMMAND_CLEAR_INTERRUPT + | SMN_COMMAND_ENABLE_INTERRUPT); + + out: + /* + * If status is SCC_STATUS_UNIMPLEMENTED or is still + * SCC_STATUS_CHECKING, could be leaving here with the driver partially + * initialized. In either case, cleanup (which will mark the SCC as + * UNIMPLEMENTED). + */ + if (scc_availability == SCC_STATUS_CHECKING || + scc_availability == SCC_STATUS_UNIMPLEMENTED) { + scc_cleanup(); + } else { + return_value = 0; /* All is well */ + } + } + /* ! STATUS_INITIAL */ + os_printk(KERN_ALERT "SCC2: Driver Status is %s\n", + (scc_availability == SCC_STATUS_INITIAL) ? "INITIAL" : + (scc_availability == SCC_STATUS_CHECKING) ? "CHECKING" : + (scc_availability == + SCC_STATUS_UNIMPLEMENTED) ? "UNIMPLEMENTED" + : (scc_availability == + SCC_STATUS_OK) ? "OK" : (scc_availability == + SCC_STATUS_FAILED) ? "FAILED" : + "UNKNOWN"); + + return return_value; +} /* scc_init */ + +/*****************************************************************************/ +/* fn scc_cleanup() */ +/*****************************************************************************/ +/** + * Perform cleanup before driver/module is unloaded by setting the machine + * state close to what it was when the driver was loaded. This function is + * called when the kernel is shutting down or when this driver is being + * unloaded. + * + * A driver like this should probably never be unloaded, especially if there + * are other module relying upon the callback feature for monitoring the SCC + * status. + * + * In any case, cleanup the callback table (by clearing out all of the + * pointers). Deregister the interrupt handler(s). Unmap SCC registers. + * + * Note that this will not release any partitions that have been allocated. + * + */ +static void scc_cleanup(void) +{ + int i; + + /******************************************************/ + + /* Mark the driver / SCC as unusable. */ + scc_availability = SCC_STATUS_UNIMPLEMENTED; + + /* Clear out callback table */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + scc_callbacks[i] = 0; + } + + /* If SCC has been mapped in, clean it up and unmap it */ + if (scc_base) { + /* For the SCM, disable interrupts. */ + SCC_WRITE_REGISTER(SCM_INT_CTL_REG, 0); + + /* For the SMN, clear and disable interrupts */ + SCC_WRITE_REGISTER(SMN_COMMAND_REG, + SMN_COMMAND_CLEAR_INTERRUPT); + } + + /* Now that interrupts cannot occur, disassociate driver from the interrupt + * lines. + */ + + /* Deregister SCM interrupt handler */ + if (scm_irq_set) { + os_deregister_interrupt(INT_SCC_SCM); + } + + /* Deregister SMN interrupt handler */ + if (smn_irq_set) { +#ifdef USE_SMN_INTERRUPT + os_deregister_interrupt(INT_SCC_SMN); +#endif + } + + /* Finally, release the mapped memory */ + iounmap(scm_ram_base); + + if (scc_callbacks_lock != NULL) + os_lock_deallocate(scc_callbacks_lock); + + if (scc_crypto_lock != NULL) + os_lock_deallocate(scc_crypto_lock); + + pr_debug("SCC2 driver cleaned up.\n"); + +} /* scc_cleanup */ + +/*****************************************************************************/ +/* fn scc_get_configuration() */ +/*****************************************************************************/ +scc_config_t *scc_get_configuration(void) +{ + /* + * If some other driver calls scc before the kernel does, make sure that + * this driver's initialization is performed. + */ + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /** + * If there is no SCC, yet the driver exists, the value -1 will be in + * the #scc_config_t fields for other than the driver versions. + */ + return &scc_configuration; +} /* scc_get_configuration */ + +/*****************************************************************************/ +/* fn scc_zeroize_memories() */ +/*****************************************************************************/ +scc_return_t scc_zeroize_memories(void) +{ + scc_return_t return_status = SCC_RET_FAIL; + + return return_status; +} /* scc_zeroize_memories */ + +/*****************************************************************************/ +/* fn scc_set_sw_alarm() */ +/*****************************************************************************/ +void scc_set_sw_alarm(void) +{ + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* Update scc_availability based on current SMN status. This might + * perform callbacks. + */ + (void)scc_update_state(); + + /* if everything is OK, make it fail */ + if (scc_availability == SCC_STATUS_OK) { + + /* sound the alarm (and disable SMN interrupts */ + SCC_WRITE_REGISTER(SMN_COMMAND_REG, + SMN_COMMAND_SET_SOFTWARE_ALARM); + + scc_availability = SCC_STATUS_FAILED; /* Remember what we've done */ + + /* In case SMN interrupt is not available, tell the world */ + scc_perform_callbacks(); + } + + return; +} /* scc_set_sw_alarm */ + +/*****************************************************************************/ +/* fn scc_monitor_security_failure() */ +/*****************************************************************************/ +scc_return_t scc_monitor_security_failure(void callback_func(void)) +{ + int i; + os_lock_context_t irq_flags; /* for IRQ save/restore */ + scc_return_t return_status = SCC_RET_TOO_MANY_FUNCTIONS; + int function_stored = FALSE; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* Acquire lock of callbacks table. Could be spin_lock_irq() if this + * routine were just called from base (not interrupt) level + */ + os_lock_save_context(scc_callbacks_lock, irq_flags); + + /* Search through table looking for empty slot */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + if (scc_callbacks[i] == callback_func) { + if (function_stored) { + /* Saved duplicate earlier. Clear this later one. */ + scc_callbacks[i] = NULL; + } + /* Exactly one copy is now stored */ + return_status = SCC_RET_OK; + break; + } else if (scc_callbacks[i] == NULL && !function_stored) { + /* Found open slot. Save it and remember */ + scc_callbacks[i] = callback_func; + return_status = SCC_RET_OK; + function_stored = TRUE; + } + } + + /* Free the lock */ + os_unlock_restore_context(scc_callbacks_lock, irq_flags); + + return return_status; +} /* scc_monitor_security_failure */ + +/*****************************************************************************/ +/* fn scc_stop_monitoring_security_failure() */ +/*****************************************************************************/ +void scc_stop_monitoring_security_failure(void callback_func(void)) +{ + os_lock_context_t irq_flags; /* for IRQ save/restore */ + int i; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* Acquire lock of callbacks table. Could be spin_lock_irq() if this + * routine were just called from base (not interrupt) level + */ + os_lock_save_context(scc_callbacks_lock, irq_flags); + + /* Search every entry of the table for this function */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + if (scc_callbacks[i] == callback_func) { + scc_callbacks[i] = NULL; /* found instance - clear it out */ + break; + } + } + + /* Free the lock */ + os_unlock_restore_context(scc_callbacks_lock, irq_flags); + + return; +} /* scc_stop_monitoring_security_failure */ + +/*****************************************************************************/ +/* fn scc_read_register() */ +/*****************************************************************************/ +scc_return_t scc_read_register(int register_offset, uint32_t * value) +{ + scc_return_t return_status = SCC_RET_FAIL; + uint32_t smn_status; + uint32_t scm_status; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* First layer of protection -- completely unaccessible SCC */ + if (scc_availability != SCC_STATUS_UNIMPLEMENTED) { + + /* Second layer -- that offset is valid */ + if (register_offset != SMN_BB_DEC_REG && /* write only! */ + check_register_offset(register_offset) == SCC_RET_OK) { + + /* Get current status / update local state */ + smn_status = scc_update_state(); + scm_status = SCC_READ_REGISTER(SCM_STATUS_REG); + + /* + * Third layer - verify that the register being requested is + * available in the current state of the SCC. + */ + if ((return_status = + check_register_accessible(register_offset, + smn_status, + scm_status)) == + SCC_RET_OK) { + *value = SCC_READ_REGISTER(register_offset); + } + } + } + + return return_status; +} /* scc_read_register */ + +/*****************************************************************************/ +/* fn scc_write_register() */ +/*****************************************************************************/ +scc_return_t scc_write_register(int register_offset, uint32_t value) +{ + scc_return_t return_status = SCC_RET_FAIL; + uint32_t smn_status; + uint32_t scm_status; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* First layer of protection -- completely unaccessible SCC */ + if (scc_availability != SCC_STATUS_UNIMPLEMENTED) { + + /* Second layer -- that offset is valid */ + if (!((register_offset == SCM_STATUS_REG) || /* These registers are */ + (register_offset == SCM_VERSION_REG) || /* Read Only */ + (register_offset == SMN_BB_CNT_REG) || + (register_offset == SMN_TIMER_REG)) && + check_register_offset(register_offset) == SCC_RET_OK) { + + /* Get current status / update local state */ + smn_status = scc_update_state(); + scm_status = SCC_READ_REGISTER(SCM_STATUS_REG); + + /* + * Third layer - verify that the register being requested is + * available in the current state of the SCC. + */ + if (check_register_accessible + (register_offset, smn_status, scm_status) == 0) { + SCC_WRITE_REGISTER(register_offset, value); + return_status = SCC_RET_OK; + } + } + } + + return return_status; +} /* scc_write_register() */ + +/****************************************************************************** + * + * Function Implementations - Internal + * + *****************************************************************************/ + +/*****************************************************************************/ +/* fn scc_irq() */ +/*****************************************************************************/ +/** + * This is the interrupt handler for the SCC. + * + * This function checks the SMN Status register to see whether it + * generated the interrupt, then it checks the SCM Status register to + * see whether it needs attention. + * + * If an SMN Interrupt is active, then the SCC state set to failure, and + * #scc_perform_callbacks() is invoked to notify any interested parties. + * + * The SCM Interrupt should be masked, as this driver uses polling to determine + * when the SCM has completed a crypto or zeroing operation. Therefore, if the + * interrupt is active, the driver will just clear the interrupt and (re)mask. + */ +OS_DEV_ISR(scc_irq) +{ + uint32_t smn_status; + uint32_t scm_status; + int handled = 0; /* assume interrupt isn't from SMN */ +#if defined(USE_SMN_INTERRUPT) + int smn_irq = INT_SCC_SMN; /* SMN interrupt is on a line by itself */ +#elif defined (NO_SMN_INTERRUPT) + int smn_irq = -1; /* not wired to CPU at all */ +#else + int smn_irq = INT_SCC_SCM; /* SMN interrupt shares a line with SCM */ +#endif + + /* Update current state... This will perform callbacks... */ + smn_status = scc_update_state(); + + /* SMN is on its own interrupt line. Verify the IRQ was triggered + * before clearing the interrupt and marking it handled. */ + if ((os_dev_get_irq() == smn_irq) && + (smn_status & SMN_STATUS_SMN_STATUS_IRQ)) { + SCC_WRITE_REGISTER(SMN_COMMAND_REG, + SMN_COMMAND_CLEAR_INTERRUPT); + handled++; /* tell kernel that interrupt was handled */ + } + + /* Check on the health of the SCM */ + scm_status = SCC_READ_REGISTER(SCM_STATUS_REG); + + /* The driver masks interrupts, so this should never happen. */ + if (os_dev_get_irq() == INT_SCC_SCM) { + /* but if it does, try to prevent it in the future */ + SCC_WRITE_REGISTER(SCM_INT_CTL_REG, 0); + handled++; + } + + /* Any non-zero value of handled lets kernel know we got something */ + os_dev_isr_return(handled); +} + +/*****************************************************************************/ +/* fn scc_perform_callbacks() */ +/*****************************************************************************/ +/** Perform callbacks registered by #scc_monitor_security_failure(). + * + * Make sure callbacks only happen once... Since there may be some reason why + * the interrupt isn't generated, this routine could be called from base(task) + * level. + * + * One at a time, go through #scc_callbacks[] and call any non-null pointers. + */ +static void scc_perform_callbacks(void) +{ + static int callbacks_performed = 0; + unsigned long irq_flags; /* for IRQ save/restore */ + int i; + + /* Acquire lock of callbacks table and callbacks_performed flag */ + os_lock_save_context(scc_callbacks_lock, irq_flags); + + if (!callbacks_performed) { + callbacks_performed = 1; + + /* Loop over all of the entries in the table */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + /* If not null, ... */ + if (scc_callbacks[i]) { + scc_callbacks[i] (); /* invoke the callback routine */ + } + } + } + + os_unlock_restore_context(scc_callbacks_lock, irq_flags); + + return; +} + +/*****************************************************************************/ +/* fn scc_update_state() */ +/*****************************************************************************/ +/** + * Make certain SCC is still running. + * + * Side effect is to update #scc_availability and, if the state goes to failed, + * run #scc_perform_callbacks(). + * + * (If #SCC_BRINGUP is defined, bring SCC to secure state if it is found to be + * in health check state) + * + * @return Current value of #SMN_STATUS_REG register. + */ +static uint32_t scc_update_state(void) +{ + uint32_t smn_status_register = SMN_STATE_FAIL; + int smn_state; + + /* if FAIL or UNIMPLEMENTED, don't bother */ + if (scc_availability == SCC_STATUS_CHECKING || + scc_availability == SCC_STATUS_OK) { + + smn_status_register = SCC_READ_REGISTER(SMN_STATUS_REG); + smn_state = smn_status_register & SMN_STATUS_STATE_MASK; + +#ifdef SCC_BRINGUP + /* If in Health Check while booting, try to 'bringup' to Secure mode */ + if (scc_availability == SCC_STATUS_CHECKING && + smn_state == SMN_STATE_HEALTH_CHECK) { + /* Code up a simple algorithm for the ASC */ + SCC_WRITE_REGISTER(SMN_SEQ_START_REG, 0xaaaa); + SCC_WRITE_REGISTER(SMN_SEQ_END_REG, 0x5555); + SCC_WRITE_REGISTER(SMN_SEQ_CHECK_REG, 0x5555); + /* State should be SECURE now */ + smn_status_register = SCC_READ_REGISTER(SMN_STATUS); + smn_state = smn_status_register & SMN_STATUS_STATE_MASK; + } +#endif + + /* + * State should be SECURE or NON_SECURE for operation of the part. If + * FAIL, mark failed (i.e. limited access to registers). Any other + * state, mark unimplemented, as the SCC is unuseable. + */ + if (smn_state == SMN_STATE_SECURE + || smn_state == SMN_STATE_NON_SECURE) { + /* Healthy */ + scc_availability = SCC_STATUS_OK; + } else if (smn_state == SMN_STATE_FAIL) { + scc_availability = SCC_STATUS_FAILED; /* uh oh - unhealthy */ + scc_perform_callbacks(); + os_printk(KERN_ERR "SCC2: SCC went into FAILED mode\n"); + } else { + /* START, ZEROIZE RAM, HEALTH CHECK, or unknown */ + scc_availability = SCC_STATUS_UNIMPLEMENTED; /* unuseable */ + os_printk(KERN_ERR + "SCC2: SCC declared UNIMPLEMENTED\n"); + } + } + /* if availability is initial or ok */ + return smn_status_register; +} + +/*****************************************************************************/ +/* fn scc_init_ccitt_crc() */ +/*****************************************************************************/ +/** + * Populate the partial CRC lookup table. + * + * @return none + * + */ +static void scc_init_ccitt_crc(void) +{ + int dividend; /* index for lookup table */ + uint16_t remainder; /* partial value for a given dividend */ + int bit; /* index into bits of a byte */ + + /* + * Compute the remainder of each possible dividend. + */ + for (dividend = 0; dividend < 256; ++dividend) { + /* + * Start with the dividend followed by zeros. + */ + remainder = dividend << (8); + + /* + * Perform modulo-2 division, a bit at a time. + */ + for (bit = 8; bit > 0; --bit) { + /* + * Try to divide the current data bit. + */ + if (remainder & 0x8000) { + remainder = (remainder << 1) ^ CRC_POLYNOMIAL; + } else { + remainder = (remainder << 1); + } + } + + /* + * Store the result into the table. + */ + scc_crc_lookup_table[dividend] = remainder; + } + +} /* scc_init_ccitt_crc() */ + +/*****************************************************************************/ +/* fn grab_config_values() */ +/*****************************************************************************/ +/** + * grab_config_values() will read the SCM Configuration and SMN Status + * registers and store away version and size information for later use. + * + * @return The current value of the SMN Status register. + */ +static uint32_t scc_grab_config_values(void) +{ + uint32_t scm_version_register; + uint32_t smn_status_register = SMN_STATE_FAIL; + + if (scc_availability != SCC_STATUS_CHECKING) { + goto out; + } + scm_version_register = SCC_READ_REGISTER(SCM_VERSION_REG); + pr_debug("SCC2 Driver: SCM version is 0x%08x\n", scm_version_register); + + /* Get SMN status and update scc_availability */ + smn_status_register = scc_update_state(); + pr_debug("SCC2 Driver: SMN status is 0x%08x\n", smn_status_register); + + /* save sizes and versions information for later use */ + scc_configuration.block_size_bytes = 16; /* BPCP ? */ + scc_configuration.partition_count = + 1 + ((scm_version_register & SCM_VER_NP_MASK) >> SCM_VER_NP_SHIFT); + scc_configuration.partition_size_bytes = + 1 << ((scm_version_register & SCM_VER_BPP_MASK) >> + SCM_VER_BPP_SHIFT); + scc_configuration.scm_version = + (scm_version_register & SCM_VER_MAJ_MASK) >> SCM_VER_MAJ_SHIFT; + scc_configuration.smn_version = + (smn_status_register & SMN_STATUS_VERSION_ID_MASK) + >> SMN_STATUS_VERSION_ID_SHIFT; + if (scc_configuration.scm_version != SCM_MAJOR_VERSION_2) { + scc_availability = SCC_STATUS_UNIMPLEMENTED; /* Unknown version */ + } + + out: + return smn_status_register; +} /* grab_config_values */ + +/*****************************************************************************/ +/* fn setup_interrupt_handling() */ +/*****************************************************************************/ +/** + * Register the SCM and SMN interrupt handlers. + * + * Called from #scc_init() + * + * @return 0 on success + */ +static int setup_interrupt_handling(void) +{ + int smn_error_code = -1; + int scm_error_code = -1; + + /* Disnable SCM interrupts */ + SCC_WRITE_REGISTER(SCM_INT_CTL_REG, 0); + +#ifdef USE_SMN_INTERRUPT + /* Install interrupt service routine for SMN. */ + smn_error_code = os_register_interrupt(SCC_DRIVER_NAME, + INT_SCC_SMN, scc_irq); + if (smn_error_code != 0) { + os_printk(KERN_ERR + "SCC2 Driver: Error installing SMN Interrupt Handler: %d\n", + smn_error_code); + } else { + smn_irq_set = 1; /* remember this for cleanup */ + /* Enable SMN interrupts */ + SCC_WRITE_REGISTER(SMN_COMMAND_REG, + SMN_COMMAND_CLEAR_INTERRUPT | + SMN_COMMAND_ENABLE_INTERRUPT); + } +#else + smn_error_code = 0; /* no problems... will handle later */ +#endif + + /* + * Install interrupt service routine for SCM (or both together). + */ + scm_error_code = os_register_interrupt(SCC_DRIVER_NAME, + INT_SCC_SCM, scc_irq); + if (scm_error_code != 0) { +#ifndef MXC + os_printk(KERN_ERR + "SCC2 Driver: Error installing SCM Interrupt Handler: %d\n", + scm_error_code); +#else + os_printk(KERN_ERR + "SCC2 Driver: Error installing SCC Interrupt Handler: %d\n", + scm_error_code); +#endif + } else { + scm_irq_set = 1; /* remember this for cleanup */ +#if defined(USE_SMN_INTERRUPT) && !defined(NO_SMN_INTERRUPT) + /* Enable SMN interrupts */ + SCC_WRITE_REGISTER(SMN_COMMAND_REG, + SMN_COMMAND_CLEAR_INTERRUPT | + SMN_COMMAND_ENABLE_INTERRUPT); +#endif + } + + /* Return an error if one was encountered */ + return scm_error_code ? scm_error_code : smn_error_code; +} /* setup_interrupt_handling */ + +/*****************************************************************************/ +/* fn scc_do_crypto() */ +/*****************************************************************************/ +/** Have the SCM perform the crypto function. + * + * Set up length register, and the store @c scm_control into control register + * to kick off the operation. Wait for completion, gather status, clear + * interrupt / status. + * + * @param byte_count number of bytes to perform in this operation + * @param scm_command Bit values to be set in @c SCM_CCMD_REG register + * + * @return 0 on success, value of #SCM_ERR_STATUS_REG on failure + */ +static uint32_t scc_do_crypto(int byte_count, uint32_t scm_command) +{ + int block_count = byte_count / SCC_BLOCK_SIZE_BYTES(); + uint32_t crypto_status; + scc_return_t ret; + + /* This seems to be necessary in order to allow subsequent cipher + * operations to succeed when a partition is deallocated/reallocated! + */ + (void)SCC_READ_REGISTER(SCM_STATUS_REG); + + /* In length register, 0 means 1, etc. */ + scm_command |= (block_count - 1) << SCM_CCMD_LENGTH_SHIFT; + + /* set modes and kick off the operation */ + SCC_WRITE_REGISTER(SCM_CCMD_REG, scm_command); + + ret = scc_wait_completion(&crypto_status); + + /* Only done bit should be on */ + if (crypto_status & SCM_STATUS_ERR) { + /* Replace with error status instead */ + crypto_status = SCC_READ_REGISTER(SCM_ERR_STATUS_REG); + pr_debug("SCM Failure: 0x%x\n", crypto_status); + if (crypto_status == 0) { + /* That came up 0. Turn on arbitrary bit to signal error. */ + crypto_status = SCM_ERRSTAT_ILM; + } + } else { + crypto_status = 0; + } + pr_debug("SCC2: Done waiting.\n"); + + return crypto_status; +} + +/** + * Encrypt a region of secure memory. + * + * @param part_base Kernel virtual address of the partition. + * @param offset_bytes Offset from the start of the partition to the plaintext + * data. + * @param byte_count Length of the region (octets). + * @param black_data Physical location to store the encrypted data. + * @param IV Value to use for the IV. + * @param cypher_mode Cyphering mode to use, specified by type + * #scc_cypher_mode_t + * + * @return SCC_RET_OK if successful. + */ +scc_return_t +scc_encrypt_region(uint32_t part_base, uint32_t offset_bytes, + uint32_t byte_count, uint8_t *black_data, + uint32_t *IV, scc_cypher_mode_t cypher_mode) +{ + os_lock_context_t irq_flags; /* for IRQ save/restore */ + scc_return_t status = SCC_RET_OK; + uint32_t crypto_status; + uint32_t scm_command; + int offset_blocks = offset_bytes / SCC_BLOCK_SIZE_BYTES(); + + scm_command = ((offset_blocks << SCM_CCMD_OFFSET_SHIFT) | + (SCM_PART_NUMBER(part_base) << SCM_CCMD_PART_SHIFT)); + + switch (cypher_mode) { + case SCC_CYPHER_MODE_CBC: + scm_command |= SCM_CCMD_AES_ENC_CBC; + break; + case SCC_CYPHER_MODE_ECB: + scm_command |= SCM_CCMD_AES_ENC_ECB; + break; + default: + status = SCC_RET_FAIL; + break; + } + + pr_debug("Received encrypt request. SCM_C_BLACK_ST_REG: %p, " + "scm_Command: %08x, length: %i (part_base: %08x, " + "offset: %i)\n", + black_data, scm_command, byte_count, part_base, offset_blocks); + + if (status != SCC_RET_OK) + goto out; + + /* ACQUIRE LOCK to prevent others from using crypto or releasing slot */ + os_lock_save_context(scc_crypto_lock, irq_flags); + + if (status == SCC_RET_OK) { + SCC_WRITE_REGISTER(SCM_C_BLACK_ST_REG, (uint32_t) black_data); + + /* Only write the IV if it will actually be used */ + if (cypher_mode == SCC_CYPHER_MODE_CBC) { + /* Write the IV register */ + SCC_WRITE_REGISTER(SCM_AES_CBC_IV0_REG, *(IV)); + SCC_WRITE_REGISTER(SCM_AES_CBC_IV1_REG, *(IV + 1)); + SCC_WRITE_REGISTER(SCM_AES_CBC_IV2_REG, *(IV + 2)); + SCC_WRITE_REGISTER(SCM_AES_CBC_IV3_REG, *(IV + 3)); + } + + /* Set modes and kick off the encryption */ + crypto_status = scc_do_crypto(byte_count, scm_command); + + if (crypto_status != 0) { + pr_debug("SCM encrypt red crypto failure: 0x%x\n", + crypto_status); + } else { + status = SCC_RET_OK; + pr_debug("SCC2: Encrypted %d bytes\n", byte_count); + } + } + + os_unlock_restore_context(scc_crypto_lock, irq_flags); +out: + return status; +} + +/* Decrypt a region into secure memory + * + * @param part_base Kernel virtual address of the partition. + * @param offset_bytes Offset from the start of the partition to store the + * plaintext data. + * @param byte_counts Length of the region (octets). + * @param black_data Physical location of the encrypted data. + * @param IV Value to use for the IV. + * @param cypher_mode Cyphering mode to use, specified by type + * #scc_cypher_mode_t + * + * @return SCC_RET_OK if successful. + */ +scc_return_t +scc_decrypt_region(uint32_t part_base, uint32_t offset_bytes, + uint32_t byte_count, uint8_t *black_data, + uint32_t *IV, scc_cypher_mode_t cypher_mode) +{ + os_lock_context_t irq_flags; /* for IRQ save/restore */ + scc_return_t status = SCC_RET_OK; + uint32_t crypto_status; + uint32_t scm_command; + int offset_blocks = offset_bytes / SCC_BLOCK_SIZE_BYTES(); + + scm_command = ((offset_blocks << SCM_CCMD_OFFSET_SHIFT) | + (SCM_PART_NUMBER(part_base) << SCM_CCMD_PART_SHIFT)); + + switch (cypher_mode) { + case SCC_CYPHER_MODE_CBC: + scm_command |= SCM_CCMD_AES_DEC_CBC; + break; + case SCC_CYPHER_MODE_ECB: + scm_command |= SCM_CCMD_AES_DEC_ECB; + break; + default: + status = SCC_RET_FAIL; + break; + } + + pr_debug("Received decrypt request. SCM_C_BLACK_ST_REG: %p, " + "scm_Command: %08x, length: %i (part_base: %08x, " + "offset: %i)\n", + black_data, scm_command, byte_count, part_base, offset_blocks); + + if (status != SCC_RET_OK) + goto out; + + /* ACQUIRE LOCK to prevent others from using crypto or releasing slot */ + os_lock_save_context(scc_crypto_lock, irq_flags); + + if (status == SCC_RET_OK) { + status = SCC_RET_FAIL; /* reset expectations */ + SCC_WRITE_REGISTER(SCM_C_BLACK_ST_REG, (uint32_t) black_data); + + /* Write the IV register */ + SCC_WRITE_REGISTER(SCM_AES_CBC_IV0_REG, *(IV)); + SCC_WRITE_REGISTER(SCM_AES_CBC_IV1_REG, *(IV + 1)); + SCC_WRITE_REGISTER(SCM_AES_CBC_IV2_REG, *(IV + 2)); + SCC_WRITE_REGISTER(SCM_AES_CBC_IV3_REG, *(IV + 3)); + + /* Set modes and kick off the decryption */ + crypto_status = scc_do_crypto(byte_count, scm_command); + + if (crypto_status != 0) { + pr_debug("SCM decrypt black crypto failure: 0x%x\n", + crypto_status); + } else { + status = SCC_RET_OK; + pr_debug("SCC2: Decrypted %d bytes\n", byte_count); + } + } + + os_unlock_restore_context(scc_crypto_lock, irq_flags); +out: + return status; +} + +/*****************************************************************************/ +/* fn host_owns_partition() */ +/*****************************************************************************/ +/** + * Determine if the host owns a given partition. + * + * @internal + * + * @param part_no Partition number to query + * + * @return TRUE if the host owns the partition, FALSE otherwise. + */ + +static uint32_t host_owns_partition(uint32_t part_no) +{ + uint32_t value; + + if (part_no < scc_configuration.partition_count) { + + /* Check the partition owners register */ + value = SCC_READ_REGISTER(SCM_PART_OWNERS_REG); + if (((value >> (part_no * SCM_POWN_SHIFT)) & SCM_POWN_MASK) + == SCM_POWN_PART_OWNED) + return TRUE; + } + return FALSE; +} + +/*****************************************************************************/ +/* fn partition_engaged() */ +/*****************************************************************************/ +/** + * Determine if the given partition is engaged. + * + * @internal + * + * @param part_no Partition number to query + * + * @return TRUE if the partition is engaged, FALSE otherwise. + */ + +static uint32_t partition_engaged(uint32_t part_no) +{ + uint32_t value; + + if (part_no < scc_configuration.partition_count) { + + /* Check the partition engaged register */ + value = SCC_READ_REGISTER(SCM_PART_ENGAGED_REG); + if (((value >> (part_no * SCM_PENG_SHIFT)) & 0x1) + == SCM_PENG_ENGAGED) + return TRUE; + } + return FALSE; +} + +/*****************************************************************************/ +/* fn scc_wait_completion() */ +/*****************************************************************************/ +/** + * Poll looking for end-of-cipher indication. Only used + * if @c SCC_SCM_SLEEP is not defined. + * + * @internal + * + * On a Tahiti, crypto under 230 or so bytes is done after the first loop, all + * the way up to five sets of spins for 1024 bytes. (8- and 16-byte functions + * are done when we first look. Zeroizing takes one pass around. + * + * @param scm_status Address of the SCM_STATUS register + * + * @return A return code of type #scc_return_t + */ +static scc_return_t scc_wait_completion(uint32_t * scm_status) +{ + scc_return_t ret; + int done; + int i = 0; + + /* check for completion by polling */ + do { + done = is_cipher_done(scm_status); + if (done) + break; + /* TODO: shorten this delay */ + udelay(1000); + } while (i++ < SCC_CIPHER_MAX_POLL_COUNT); + + pr_debug("SCC2: Polled DONE %d times\n", i); + if (!done) { + ret = SCC_RET_FAIL; + } + + return ret; +} /* scc_wait_completion() */ + +/*****************************************************************************/ +/* fn is_cipher_done() */ +/*****************************************************************************/ +/** + * This function returns non-zero if SCM Status register indicates + * that a cipher has terminated or some other interrupt-generating + * condition has occurred. + * + * @param scm_status Address of the SCM STATUS register + * + * @return 0 if cipher operations are finished + */ +static int is_cipher_done(uint32_t * scm_status) +{ + register unsigned status; + register int cipher_done; + + *scm_status = SCC_READ_REGISTER(SCM_STATUS_REG); + status = (*scm_status & SCM_STATUS_SRS_MASK) >> SCM_STATUS_SRS_SHIFT; + + /* + * Done when SCM is not in 'currently performing a function' states. + */ + cipher_done = ((status != SCM_STATUS_SRS_ZBUSY) + && (status != SCM_STATUS_SRS_CBUSY) + && (status != SCM_STATUS_SRS_ABUSY)); + + return cipher_done; +} /* is_cipher_done() */ + +/*****************************************************************************/ +/* fn offset_within_smn() */ +/*****************************************************************************/ +/*! + * Check that the offset is with the bounds of the SMN register set. + * + * @param[in] register_offset register offset of SMN. + * + * @return 1 if true, 0 if false (not within SMN) + */ +static inline int offset_within_smn(uint32_t register_offset) +{ + return ((register_offset >= SMN_STATUS_REG) + && (register_offset <= SMN_HAC_REG)); +} + +/*****************************************************************************/ +/* fn offset_within_scm() */ +/*****************************************************************************/ +/*! + * Check that the offset is with the bounds of the SCM register set. + * + * @param[in] register_offset Register offset of SCM + * + * @return 1 if true, 0 if false (not within SCM) + */ +static inline int offset_within_scm(uint32_t register_offset) +{ + return 1; /* (register_offset >= SCM_RED_START) + && (register_offset < scm_highest_memory_address); */ +/* Although this would cause trouble for zeroize testing, this change would + * close a security hole which currently allows any kernel program to access + * any location in RED RAM. Perhaps enforce in non-SCC_DEBUG compiles? + && (register_offset <= SCM_INIT_VECTOR_1); */ +} + +/*****************************************************************************/ +/* fn check_register_accessible() */ +/*****************************************************************************/ +/** + * Given the current SCM and SMN status, verify that access to the requested + * register should be OK. + * + * @param[in] register_offset register offset within SCC + * @param[in] smn_status recent value from #SMN_STATUS_REG + * @param[in] scm_status recent value from #SCM_STATUS_REG + * + * @return #SCC_RET_OK if ok, #SCC_RET_FAIL if not + */ +static scc_return_t +check_register_accessible(uint32_t register_offset, uint32_t smn_status, + uint32_t scm_status) +{ + int error_code = SCC_RET_FAIL; + + /* Verify that the register offset passed in is not among the verboten set + * if the SMN is in Fail mode. + */ + if (offset_within_smn(register_offset)) { + if ((smn_status & SMN_STATUS_STATE_MASK) == SMN_STATE_FAIL) { + if (!((register_offset == SMN_STATUS_REG) || + (register_offset == SMN_COMMAND_REG) || + (register_offset == SMN_SEC_VIO_REG))) { + pr_debug + ("SCC2 Driver: Note: Security State is in FAIL state.\n"); + } /* register not a safe one */ + else { + /* SMN is in FAIL, but register is a safe one */ + error_code = SCC_RET_OK; + } + } /* State is FAIL */ + else { + /* State is not fail. All registers accessible. */ + error_code = SCC_RET_OK; + } + } + /* offset within SMN */ + /* Not SCM register. Check for SCM busy. */ + else if (offset_within_scm(register_offset)) { + /* This is the 'cannot access' condition in the SCM */ + if (0 /* (scm_status & SCM_STATUS_BUSY) */ + /* these are always available - rest fail on busy */ + && !((register_offset == SCM_STATUS_REG) || + (register_offset == SCM_ERR_STATUS_REG) || + (register_offset == SCM_INT_CTL_REG) || + (register_offset == SCM_VERSION_REG))) { + pr_debug + ("SCC2 Driver: Note: Secure Memory is in BUSY state.\n"); + } /* status is busy & register inaccessible */ + else { + error_code = SCC_RET_OK; + } + } + /* offset within SCM */ + return error_code; + +} /* check_register_accessible() */ + +/*****************************************************************************/ +/* fn check_register_offset() */ +/*****************************************************************************/ +/** + * Check that the offset is with the bounds of the SCC register set. + * + * @param[in] register_offset register offset of SMN. + * + * #SCC_RET_OK if ok, #SCC_RET_FAIL if not + */ +static scc_return_t check_register_offset(uint32_t register_offset) +{ + int return_value = SCC_RET_FAIL; + + /* Is it valid word offset ? */ + if (SCC_BYTE_OFFSET(register_offset) == 0) { + /* Yes. Is register within SCM? */ + if (offset_within_scm(register_offset)) { + return_value = SCC_RET_OK; /* yes, all ok */ + } + /* Not in SCM. Now look within the SMN */ + else if (offset_within_smn(register_offset)) { + return_value = SCC_RET_OK; /* yes, all ok */ + } + } + + return return_value; +} + +#ifdef SCC_REGISTER_DEBUG + +/** + * Names of the SCC Registers, indexed by register number + */ +static char *scc_regnames[] = { + "SCM_VERSION_REG", + "0x04", + "SCM_INT_CTL_REG", + "SCM_STATUS_REG", + "SCM_ERR_STATUS_REG", + "SCM_FAULT_ADR_REG", + "SCM_PART_OWNERS_REG", + "SCM_PART_ENGAGED_REG", + "SCM_UNIQUE_ID0_REG", + "SCM_UNIQUE_ID1_REG", + "SCM_UNIQUE_ID2_REG", + "SCM_UNIQUE_ID3_REG", + "0x30", + "0x34", + "0x38", + "0x3C", + "0x40", + "0x44", + "0x48", + "0x4C", + "SCM_ZCMD_REG", + "SCM_CCMD_REG", + "SCM_C_BLACK_ST_REG", + "SCM_DBG_STATUS_REG", + "SCM_AES_CBC_IV0_REG", + "SCM_AES_CBC_IV1_REG", + "SCM_AES_CBC_IV2_REG", + "SCM_AES_CBC_IV3_REG", + "0x70", + "0x74", + "0x78", + "0x7C", + "SCM_SMID0_REG", + "SCM_ACC0_REG", + "SCM_SMID1_REG", + "SCM_ACC1_REG", + "SCM_SMID2_REG", + "SCM_ACC2_REG", + "SCM_SMID3_REG", + "SCM_ACC3_REG", + "SCM_SMID4_REG", + "SCM_ACC4_REG", + "SCM_SMID5_REG", + "SCM_ACC5_REG", + "SCM_SMID6_REG", + "SCM_ACC6_REG", + "SCM_SMID7_REG", + "SCM_ACC7_REG", + "SCM_SMID8_REG", + "SCM_ACC8_REG", + "SCM_SMID9_REG", + "SCM_ACC9_REG", + "SCM_SMID10_REG", + "SCM_ACC10_REG", + "SCM_SMID11_REG", + "SCM_ACC11_REG", + "SCM_SMID12_REG", + "SCM_ACC12_REG", + "SCM_SMID13_REG", + "SCM_ACC13_REG", + "SCM_SMID14_REG", + "SCM_ACC14_REG", + "SCM_SMID15_REG", + "SCM_ACC15_REG", + "SMN_STATUS_REG", + "SMN_COMMAND_REG", + "SMN_SEQ_START_REG", + "SMN_SEQ_END_REG", + "SMN_SEQ_CHECK_REG", + "SMN_BB_CNT_REG", + "SMN_BB_INC_REG", + "SMN_BB_DEC_REG", + "SMN_COMPARE_REG", + "SMN_PT_CHK_REG", + "SMN_CT_CHK_REG", + "SMN_TIMER_IV_REG", + "SMN_TIMER_CTL_REG", + "SMN_SEC_VIO_REG", + "SMN_TIMER_REG", + "SMN_HAC_REG" +}; + +/** + * Names of the Secure RAM States + */ +static char *srs_names[] = { + "SRS_Reset", + "SRS_All_Ready", + "SRS_ZeroizeBusy", + "SRS_CipherBusy", + "SRS_AllBusy", + "SRS_ZeroizeDoneCipherReady", + "SRS_CipherDoneZeroizeReady", + "SRS_ZeroizeDoneCipherBusy", + "SRS_CipherDoneZeroizeBusy", + "SRS_UNKNOWN_STATE_9", + "SRS_TransitionalA", + "SRS_TransitionalB", + "SRS_TransitionalC", + "SRS_TransitionalD", + "SRS_AllDone", + "SRS_UNKNOWN_STATE_E", + "SRS_FAIL" +}; + +/** + * Create a text interpretation of the SCM Version Register + * + * @param value The value of the register + * @param[out] print_buffer Place to store the interpretation + * @param buf_size Number of bytes available at print_buffer + * + * @return The print_buffer + */ +static +char *scm_print_version_reg(uint32_t value, char *print_buffer, int buf_size) +{ + snprintf(print_buffer, buf_size, + "Bpp: %u, Bpcb: %u, np: %u, maj: %u, min: %u", + (value & SCM_VER_BPP_MASK) >> SCM_VER_BPP_SHIFT, + ((value & SCM_VER_BPCB_MASK) >> SCM_VER_BPCB_SHIFT) + 1, + ((value & SCM_VER_NP_MASK) >> SCM_VER_NP_SHIFT) + 1, + (value & SCM_VER_MAJ_MASK) >> SCM_VER_MAJ_SHIFT, + (value & SCM_VER_MIN_MASK) >> SCM_VER_MIN_SHIFT); + + return print_buffer; +} + +/** + * Create a text interpretation of the SCM Status Register + * + * @param value The value of the register + * @param[out] print_buffer Place to store the interpretation + * @param buf_size Number of bytes available at print_buffer + * + * @return The print_buffer + */ +static +char *scm_print_status_reg(uint32_t value, char *print_buffer, int buf_size) +{ + + snprintf(print_buffer, buf_size, "%s%s%s%s%s%s%s%s%s%s%s%s%s", + (value & SCM_STATUS_KST_DEFAULT_KEY) ? "KST_DefaultKey " : "", + /* reserved */ + (value & SCM_STATUS_KST_WRONG_KEY) ? "KST_WrongKey " : "", + (value & SCM_STATUS_KST_BAD_KEY) ? "KST_BadKey " : "", + (value & SCM_STATUS_ERR) ? "Error " : "", + (value & SCM_STATUS_MSS_FAIL) ? "MSS_FailState " : "", + (value & SCM_STATUS_MSS_SEC) ? "MSS_SecureState " : "", + (value & SCM_STATUS_RSS_FAIL) ? "RSS_FailState " : "", + (value & SCM_STATUS_RSS_SEC) ? "RSS_SecureState " : "", + (value & SCM_STATUS_RSS_INIT) ? "RSS_Initializing " : "", + (value & SCM_STATUS_UNV) ? "UID_Invalid " : "", + (value & SCM_STATUS_BIG) ? "BigEndian " : "", + (value & SCM_STATUS_USK) ? "SecretKey " : "", + srs_names[(value & SCM_STATUS_SRS_MASK) >> + SCM_STATUS_SRS_SHIFT]); + + return print_buffer; +} + +/** + * Names of the SCM Error Codes + */ +static +char *scm_err_code[] = { + "Unknown_0", + "UnknownAddress", + "UnknownCommand", + "ReadPermErr", + "WritePermErr", + "DMAErr", + "EncBlockLenOvfl", + "KeyNotEngaged", + "ZeroizeCmdQOvfl", + "CipherCmdQOvfl", + "ProcessIntr", + "WrongKey", + "DeviceBusy", + "DMAUnalignedAddr", + "Unknown_E", + "Unknown_F", +}; + +/** + * Names of the SMN States + */ +static char *smn_state_name[] = { + "Start", + "Invalid_01", + "Invalid_02", + "Invalid_03", + "Zeroizing_04", + "Zeroizing", + "HealthCheck", + "HealthCheck_07", + "Invalid_08", + "Fail", + "Secure", + "Invalid_0B", + "NonSecure", + "Invalid_0D", + "Invalid_0E", + "Invalid_0F", + "Invalid_10", + "Invalid_11", + "Invalid_12", + "Invalid_13", + "Invalid_14", + "Invalid_15", + "Invalid_16", + "Invalid_17", + "Invalid_18", + "FailHard", + "Invalid_1A", + "Invalid_1B", + "Invalid_1C", + "Invalid_1D", + "Invalid_1E", + "Invalid_1F" +}; + +/** + * Create a text interpretation of the SCM Error Status Register + * + * @param value The value of the register + * @param[out] print_buffer Place to store the interpretation + * @param buf_size Number of bytes available at print_buffer + * + * @return The print_buffer + */ +static +char *scm_print_err_status_reg(uint32_t value, char *print_buffer, int buf_size) +{ + snprintf(print_buffer, buf_size, + "MID: 0x%x, %s%s ErrorCode: %s, SMSState: %s, SCMState: %s", + (value & SCM_ERRSTAT_MID_MASK) >> SCM_ERRSTAT_MID_SHIFT, + (value & SCM_ERRSTAT_ILM) ? "ILM, " : "", + (value & SCM_ERRSTAT_SUP) ? "SUP, " : "", + scm_err_code[(value & SCM_ERRSTAT_ERC_MASK) >> + SCM_ERRSTAT_ERC_SHIFT], + smn_state_name[(value & SCM_ERRSTAT_SMS_MASK) >> + SCM_ERRSTAT_SMS_SHIFT], + srs_names[(value & SCM_ERRSTAT_SRS_MASK) >> + SCM_ERRSTAT_SRS_SHIFT]); + return print_buffer; +} + +/** + * Create a text interpretation of the SCM Zeroize Command Register + * + * @param value The value of the register + * @param[out] print_buffer Place to store the interpretation + * @param buf_size Number of bytes available at print_buffer + * + * @return The print_buffer + */ +static +char *scm_print_zcmd_reg(uint32_t value, char *print_buffer, int buf_size) +{ + unsigned cmd = (value & SCM_ZCMD_CCMD_MASK) >> SCM_CCMD_CCMD_SHIFT; + + snprintf(print_buffer, buf_size, "%s %u", + (cmd == + ZCMD_DEALLOC_PART) ? "DeallocPartition" : + "(unknown function)", + (value & SCM_ZCMD_PART_MASK) >> SCM_ZCMD_PART_SHIFT); + + return print_buffer; +} + +/** + * Create a text interpretation of the SCM Cipher Command Register + * + * @param value The value of the register + * @param[out] print_buffer Place to store the interpretation + * @param buf_size Number of bytes available at print_buffer + * + * @return The print_buffer + */ +static +char *scm_print_ccmd_reg(uint32_t value, char *print_buffer, int buf_size) +{ + unsigned cmd = (value & SCM_CCMD_CCMD_MASK) >> SCM_CCMD_CCMD_SHIFT; + + snprintf(print_buffer, buf_size, + "%s %u bytes, %s offset 0x%x, in partition %u", + (cmd == SCM_CCMD_AES_DEC_ECB) ? "ECB Decrypt" : (cmd == + SCM_CCMD_AES_ENC_ECB) + ? "ECB Encrypt" : (cmd == + SCM_CCMD_AES_DEC_CBC) ? "CBC Decrypt" : (cmd + == + SCM_CCMD_AES_ENC_CBC) + ? "CBC Encrypt" : "(unknown function)", + 16 + + 16 * ((value & SCM_CCMD_LENGTH_MASK) >> SCM_CCMD_LENGTH_SHIFT), + ((cmd == SCM_CCMD_AES_ENC_CBC) + || (cmd == SCM_CCMD_AES_ENC_ECB)) ? "at" : "to", + 16 * ((value & SCM_CCMD_OFFSET_MASK) >> SCM_CCMD_OFFSET_SHIFT), + (value & SCM_CCMD_PART_MASK) >> SCM_CCMD_PART_SHIFT); + + return print_buffer; +} + +/** + * Create a text interpretation of an SCM Access Permissions Register + * + * @param value The value of the register + * @param[out] print_buffer Place to store the interpretation + * @param buf_size Number of bytes available at print_buffer + * + * @return The print_buffer + */ +static +char *scm_print_acc_reg(uint32_t value, char *print_buffer, int buf_size) +{ + snprintf(print_buffer, buf_size, "%s%s%s%s%s%s%s%s%s%s", + (value & SCM_PERM_NO_ZEROIZE) ? "NO_ZERO " : "", + (value & SCM_PERM_HD_SUP_DISABLE) ? "SUP_DIS " : "", + (value & SCM_PERM_HD_READ) ? "HD_RD " : "", + (value & SCM_PERM_HD_WRITE) ? "HD_WR " : "", + (value & SCM_PERM_HD_EXECUTE) ? "HD_EX " : "", + (value & SCM_PERM_TH_READ) ? "TH_RD " : "", + (value & SCM_PERM_TH_WRITE) ? "TH_WR " : "", + (value & SCM_PERM_OT_READ) ? "OT_RD " : "", + (value & SCM_PERM_OT_WRITE) ? "OT_WR " : "", + (value & SCM_PERM_OT_EXECUTE) ? "OT_EX" : ""); + + return print_buffer; +} + +/** + * Create a text interpretation of the SCM Partitions Engaged Register + * + * @param value The value of the register + * @param[out] print_buffer Place to store the interpretation + * @param buf_size Number of bytes available at print_buffer + * + * @return The print_buffer + */ +static +char *scm_print_part_eng_reg(uint32_t value, char *print_buffer, int buf_size) +{ + snprintf(print_buffer, buf_size, "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", + (value & 0x8000) ? "15 " : "", + (value & 0x4000) ? "14 " : "", + (value & 0x2000) ? "13 " : "", + (value & 0x1000) ? "12 " : "", + (value & 0x0800) ? "11 " : "", + (value & 0x0400) ? "10 " : "", + (value & 0x0200) ? "9 " : "", + (value & 0x0100) ? "8 " : "", + (value & 0x0080) ? "7 " : "", + (value & 0x0040) ? "6 " : "", + (value & 0x0020) ? "5 " : "", + (value & 0x0010) ? "4 " : "", + (value & 0x0008) ? "3 " : "", + (value & 0x0004) ? "2 " : "", + (value & 0x0002) ? "1 " : "", (value & 0x0001) ? "0" : ""); + + return print_buffer; +} + +/** + * Create a text interpretation of the SMN Status Register + * + * @param value The value of the register + * @param[out] print_buffer Place to store the interpretation + * @param buf_size Number of bytes available at print_buffer + * + * @return The print_buffer + */ +static +char *smn_print_status_reg(uint32_t value, char *print_buffer, int buf_size) +{ + snprintf(print_buffer, buf_size, + "Version %d %s%s%s%s%s%s%s%s%s%s%s%s%s", + (value & SMN_STATUS_VERSION_ID_MASK) >> + SMN_STATUS_VERSION_ID_SHIFT, + (value & SMN_STATUS_ILLEGAL_MASTER) ? "IllMaster " : "", + (value & SMN_STATUS_SCAN_EXIT) ? "ScanExit " : "", + (value & SMN_STATUS_PERIP_INIT) ? "PeripInit " : "", + (value & SMN_STATUS_SMN_ERROR) ? "SMNError " : "", + (value & SMN_STATUS_SOFTWARE_ALARM) ? "SWAlarm " : "", + (value & SMN_STATUS_TIMER_ERROR) ? "TimerErr " : "", + (value & SMN_STATUS_PC_ERROR) ? "PTCTErr " : "", + (value & SMN_STATUS_BITBANK_ERROR) ? "BitbankErr " : "", + (value & SMN_STATUS_ASC_ERROR) ? "ASCErr " : "", + (value & SMN_STATUS_SECURITY_POLICY_ERROR) ? "SecPlcyErr " : + "", + (value & SMN_STATUS_SEC_VIO_ACTIVE_ERROR) ? "SecVioAct " : "", + (value & SMN_STATUS_INTERNAL_BOOT) ? "IntBoot " : "", + smn_state_name[(value & SMN_STATUS_STATE_MASK) >> + SMN_STATUS_STATE_SHIFT]); + + return print_buffer; +} + +/** + * The array, indexed by register number (byte-offset / 4), of print routines + * for the SCC (SCM and SMN) registers. + */ +static reg_print_routine_t reg_printers[] = { + scm_print_version_reg, + NULL, /* 0x04 */ + NULL, /* SCM_INT_CTL_REG */ + scm_print_status_reg, + scm_print_err_status_reg, + NULL, /* SCM_FAULT_ADR_REG */ + NULL, /* SCM_PART_OWNERS_REG */ + scm_print_part_eng_reg, + NULL, /* SCM_UNIQUE_ID0_REG */ + NULL, /* SCM_UNIQUE_ID1_REG */ + NULL, /* SCM_UNIQUE_ID2_REG */ + NULL, /* SCM_UNIQUE_ID3_REG */ + NULL, /* 0x30 */ + NULL, /* 0x34 */ + NULL, /* 0x38 */ + NULL, /* 0x3C */ + NULL, /* 0x40 */ + NULL, /* 0x44 */ + NULL, /* 0x48 */ + NULL, /* 0x4C */ + scm_print_zcmd_reg, + scm_print_ccmd_reg, + NULL, /* SCM_C_BLACK_ST_REG */ + NULL, /* SCM_DBG_STATUS_REG */ + NULL, /* SCM_AES_CBC_IV0_REG */ + NULL, /* SCM_AES_CBC_IV1_REG */ + NULL, /* SCM_AES_CBC_IV2_REG */ + NULL, /* SCM_AES_CBC_IV3_REG */ + NULL, /* 0x70 */ + NULL, /* 0x74 */ + NULL, /* 0x78 */ + NULL, /* 0x7C */ + NULL, /* SCM_SMID0_REG */ + scm_print_acc_reg, /* ACC0 */ + NULL, /* SCM_SMID1_REG */ + scm_print_acc_reg, /* ACC1 */ + NULL, /* SCM_SMID2_REG */ + scm_print_acc_reg, /* ACC2 */ + NULL, /* SCM_SMID3_REG */ + scm_print_acc_reg, /* ACC3 */ + NULL, /* SCM_SMID4_REG */ + scm_print_acc_reg, /* ACC4 */ + NULL, /* SCM_SMID5_REG */ + scm_print_acc_reg, /* ACC5 */ + NULL, /* SCM_SMID6_REG */ + scm_print_acc_reg, /* ACC6 */ + NULL, /* SCM_SMID7_REG */ + scm_print_acc_reg, /* ACC7 */ + NULL, /* SCM_SMID8_REG */ + scm_print_acc_reg, /* ACC8 */ + NULL, /* SCM_SMID9_REG */ + scm_print_acc_reg, /* ACC9 */ + NULL, /* SCM_SMID10_REG */ + scm_print_acc_reg, /* ACC10 */ + NULL, /* SCM_SMID11_REG */ + scm_print_acc_reg, /* ACC11 */ + NULL, /* SCM_SMID12_REG */ + scm_print_acc_reg, /* ACC12 */ + NULL, /* SCM_SMID13_REG */ + scm_print_acc_reg, /* ACC13 */ + NULL, /* SCM_SMID14_REG */ + scm_print_acc_reg, /* ACC14 */ + NULL, /* SCM_SMID15_REG */ + scm_print_acc_reg, /* ACC15 */ + smn_print_status_reg, + NULL, /* SMN_COMMAND_REG */ + NULL, /* SMN_SEQ_START_REG */ + NULL, /* SMN_SEQ_END_REG */ + NULL, /* SMN_SEQ_CHECK_REG */ + NULL, /* SMN_BB_CNT_REG */ + NULL, /* SMN_BB_INC_REG */ + NULL, /* SMN_BB_DEC_REG */ + NULL, /* SMN_COMPARE_REG */ + NULL, /* SMN_PT_CHK_REG */ + NULL, /* SMN_CT_CHK_REG */ + NULL, /* SMN_TIMER_IV_REG */ + NULL, /* SMN_TIMER_CTL_REG */ + NULL, /* SMN_SEC_VIO_REG */ + NULL, /* SMN_TIMER_REG */ + NULL, /* SMN_HAC_REG */ +}; + +/*****************************************************************************/ +/* fn dbg_scc_read_register() */ +/*****************************************************************************/ +/** + * Noisily read a 32-bit value to an SCC register. + * @param offset The address of the register to read. + * + * @return The register value + * */ +uint32_t dbg_scc_read_register(uint32_t offset) +{ + uint32_t value; + char *regname = scc_regnames[offset / 4]; + + value = __raw_readl(scc_base + offset); + pr_debug("SCC2 RD: 0x%03x : 0x%08x (%s) %s\n", offset, value, regname, + reg_printers[offset / 4] + ? reg_printers[offset / 4] (value, reg_print_buffer, + REG_PRINT_BUFFER_SIZE) + : ""); + + return value; +} + +/*****************************************************************************/ +/* fn dbg_scc_write_register() */ +/*****************************************************************************/ +/* + * Noisily read a 32-bit value to an SCC register. + * @param offset The address of the register to written. + * + * @param value The new register value + */ +void dbg_scc_write_register(uint32_t offset, uint32_t value) +{ + char *regname = scc_regnames[offset / 4]; + + pr_debug("SCC2 WR: 0x%03x : 0x%08x (%s) %s\n", offset, value, regname, + reg_printers[offset / 4] + ? reg_printers[offset / 4] (value, reg_print_buffer, + REG_PRINT_BUFFER_SIZE) + : ""); + (void)__raw_writel(value, scc_base + offset); +} + +#endif /* SCC_REGISTER_DEBUG */ diff -urN linux-2.6.26/drivers/mxc/security/scc2_internals.h linux-2.6.26-lab126/drivers/mxc/security/scc2_internals.h --- linux-2.6.26/drivers/mxc/security/scc2_internals.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/security/scc2_internals.h 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,527 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef SCC_INTERNALS_H +#define SCC_INTERNALS_H + +/** @file scc2_internals.h + * + * @brief This is intended to be the file which contains most or all of the + * code or changes need to port the driver. It also includes other definitions + * needed by the driver. + * + * This header file should only ever be included by scc2_driver.c + * + * Compile-time flags minimally needed: + * + * @li Some sort of platform flag. Currently TAHITI and MXC are understood. + * @li Some start-of-SCC consideration, such as SCC_BASE_ADDR + * + * Some changes which could be made when porting this driver: + * #SCC_SPIN_COUNT + * + */ + +#include /* Current version Linux kernel */ +#include /* Basic support for loadable modules, + printk */ +#include /* module_init, module_exit */ +#include /* General kernel system calls */ +#include /* for interrupt.h */ +#include + +#include /* ioremap() */ +#include /* IRQ / interrupt definitions */ + + +#include + +#if defined(MXC) + +#include +#include + + +/** + * This macro is used to determine whether the SCC is enabled/available + * on the platform. This macro may need to be ported. + */ +#define SCC_FUSE IO_ADDRESS(IIM_BASE_ADDR + MXC_IIMHWV1) +#define SCC_ENABLED() ((SCC_FUSE & MXC_IIMHWV1_SCC_DISABLE) == 0) + +#else /* neither TAHITI nor MXC */ + +#error Do not understand target architecture + +#endif /* TAHITI */ +/** + * Define the number of Stored Keys which the SCC driver will make available. + * Value shall be from 0 to 20. Default is zero (0). + */ +/*#define SCC_KEY_SLOTS 20*/ + + +/* Temporarily define compile-time flags to make Doxygen happy. */ +#ifdef DOXYGEN_HACK +/** @addtogroup scccompileflags */ +/** @{ */ + + +/** @def NO_SMN_INTERRUPT + * The SMN interrupt is not wired to the CPU at all. + */ +#define NO_SMN_INTERRUPT + + +/** + * Register an interrupt handler for the SMN as well as + * the SCM. In some implementations, the SMN is not connected at all (see + * #NO_SMN_INTERRUPT), and in others, it is on the same interrupt line as the + * SCM. When defining this flag, the SMN interrupt should be on a separate + * line from the SCM interrupt. + */ + +#define USE_SMN_INTERRUPT + + +/** + * Turn on generation of run-time operational, debug, and error messages + */ +#define SCC_DEBUG + + +/** + * Turn on generation of run-time logging of access to the SCM and SMN + * registers. + */ +#define SCC_REGISTER_DEBUG + + +/** + * Turn on generation of run-time logging of access to the SCM Red and + * Black memories. Will only work if #SCC_REGISTER_DEBUG is also defined. + */ +#define SCC_RAM_DEBUG + + +/** + * If the driver finds the SCC in HEALTH_CHECK state, go ahead and + * run a quick ASC to bring it to SECURE state. + */ +#define SCC_BRINGUP + + +/** + * Expected to come from platform header files or compile command line. + * This symbol must be the address of the SCC + */ +#define SCC_BASE + +/** + * This must be the interrupt line number of the SCM interrupt. + */ +#define INT_SCM + +/** + * if #USE_SMN_INTERRUPT is defined, this must be the interrupt line number of + * the SMN interrupt. + */ +#define INT_SMN + +/** + * Define the number of Stored Keys which the SCC driver will make available. + * Value shall be from 0 to 20. Default is zero (0). + */ +#define SCC_KEY_SLOTS + +/** + * Make sure that this flag is defined if compiling for a Little-Endian + * platform. Linux Kernel builds provide this flag. + */ +#define __LITTLE_ENDIAN + +/** + * Make sure that this flag is defined if compiling for a Big-Endian platform. + * Linux Kernel builds provide this flag. + */ +#define __BIG_ENDIAN + +/** + * Read a 32-bit register value from a 'peripheral'. Standard Linux/Unix + * macro. + * + * @param offset Bus address of register to be read + * + * @return The value of the register + */ +#define readl(offset) + + +/** + * Write a 32-bit value to a register in a 'peripheral'. Standard Linux/Unix + * macro. + * + * @param value The 32-bit value to store + * @param offset Bus address of register to be written + * + * return (none) + */ +#define writel(value,offset) + + +/** @} */ /* end group scccompileflags */ + +#endif /* DOXYGEN_HACK */ + + +#ifndef SCC_KEY_SLOTS +#define SCC_KEY_SLOTS 0 + +#else + +#if (SCC_KEY_SLOTS < 0) || (SCC_KEY_SLOTS > 20) +#error Bad value for SCC_KEY_SLOTS +#endif + +#endif + + +/** + * Maximum length of key/secret value which can be stored in SCC. + */ +#define SCC_MAX_KEY_SIZE 256 + + +/** + * This is the size, in bytes, of each key slot, and therefore the maximum size + * of the wrapped key. + */ +#define SCC_KEY_SLOT_SIZE 32 + + +/* These come for free with Linux, but may need to be set in a port. */ +#ifndef __BIG_ENDIAN +#ifndef __LITTLE_ENDIAN +#error One of __LITTLE_ENDIAN or __BIG_ENDIAN must be #defined +#endif +#else +#ifdef __LITTLE_ENDIAN +#error Exactly one of __LITTLE_ENDIAN or __BIG_ENDIAN must be #defined +#endif +#endif + + +#ifndef SCC_CALLBACK_SIZE +/** The number of function pointers which can be stored in #scc_callbacks. + * Defaults to 4, can be overridden with compile-line argument. + */ +#define SCC_CALLBACK_SIZE 4 +#endif + + +/** Initial CRC value for CCITT-CRC calculation. */ +#define CRC_CCITT_START 0xFFFF + + +#ifdef TAHITI + +/** + * The SCC_BASE has to be SMN_BASE_ADDR on TAHITI, as the banks of + * registers are swapped in place. + */ +#define SCC_BASE SMN_BASE_ADDR + + +/** The interrupt number for the SCC (SCM only!) on Tahiti */ +#define INT_SCC_SCM 62 + + +/** Tahiti does not have the SMN interrupt wired to the CPU. */ +#define NO_SMN_INTERRUPT + + +#endif /* TAHITI */ + + +/** Number of times to spin between polling of SCC while waiting for cipher + * or zeroizing function to complete. See also #SCC_CIPHER_MAX_POLL_COUNT. */ +#define SCC_SPIN_COUNT 1000 + + +/** Number of times to polling SCC while waiting for cipher + * or zeroizing function to complete. See also #SCC_SPIN_COUNT. */ +#define SCC_CIPHER_MAX_POLL_COUNT 100 + + +/** + * @def SCC_READ_REGISTER + * Read a 32-bit value from an SCC register. Macro which depends upon + * #scc_base. Linux readl()/writel() macros operate on 32-bit quantities, as + * do SCC register reads/writes. + * + * @param offset Register offset within SCC. + * + * @return The value from the SCC's register. + */ +#ifndef SCC_REGISTER_DEBUG +#define SCC_READ_REGISTER(offset) __raw_readl(scc_base+(offset)) +#else +#define SCC_READ_REGISTER(offset) dbg_scc_read_register(offset) +#endif + + +/** + * Write a 32-bit value to an SCC register. Macro depends upon #scc_base. + * Linux readl()/writel() macros operate on 32-bit quantities, as do SCC + * register reads/writes. + * + * @param offset Register offset within SCC. + * @param value 32-bit value to store into the register + * + * @return (void) + */ +#ifndef SCC_REGISTER_DEBUG +#define SCC_WRITE_REGISTER(offset,value) \ + (void)__raw_writel(value, scc_base+(offset)) +#else +#define SCC_WRITE_REGISTER(offset,value) \ + dbg_scc_write_register(offset, value) +#endif + +/** + * Calculate the physical address of a partition from the partition number. + */ +#define SCM_PART_PHYS_ADDRESS(part) \ + ((uint32_t)scm_ram_phys_base + (part*scc_configuration.partition_size_bytes)) + +/** + * Calculate the kernel virtual address of a partition from the partition number. + */ +#define SCM_PART_ADDRESS(part) \ + (scm_ram_base + (part*scc_configuration.partition_size_bytes)) + +/** + * Calculate the partition number from the kernel virtual address. + */ +#define SCM_PART_NUMBER(address) \ + ((address - (uint32_t)scm_ram_base)/scc_configuration.partition_size_bytes) + +/** + * Calculates the byte offset into a word + * @param bp The byte (char*) pointer + * @return The offset (0, 1, 2, or 3) + */ +#define SCC_BYTE_OFFSET(bp) ((uint32_t)(bp) % sizeof(uint32_t)) + + +/** + * Converts (by rounding down) a byte pointer into a word pointer + * @param bp The byte (char*) pointer + * @return The word (uint32_t) as though it were an aligned (uint32_t*) + */ +#define SCC_WORD_PTR(bp) (((uint32_t)(bp)) & ~(sizeof(uint32_t)-1)) + + +/** + * Determine number of bytes in an SCC block + * + * @return Bytes / block + */ +#define SCC_BLOCK_SIZE_BYTES() scc_configuration.block_size_bytes + + +/** + * Maximum number of additional bytes which may be added in CRC+padding mode. + */ +#define PADDING_BUFFER_MAX_BYTES (CRC_SIZE_BYTES + sizeof(scc_block_padding)) + +/** + * Shorthand (clearer, anyway) for number of bytes in a CRC. + */ +#define CRC_SIZE_BYTES (sizeof(crc_t)) + +/** + * The polynomial used in CCITT-CRC calculation + */ +#define CRC_POLYNOMIAL 0x1021 + +/** + * Calculate CRC on one byte of data + * + * @param[in,out] running_crc A value of type crc_t where CRC is kept. This + * must be an rvalue and an lvalue. + * @param[in] byte_value The byte (uint8_t, char) to be put in the CRC + * + * @return none + */ +#define CALC_CRC(byte_value,running_crc) { \ + uint8_t data; \ + data = (0xff&(byte_value)) ^ (running_crc >> 8); \ + running_crc = scc_crc_lookup_table[data] ^ (running_crc << 8); \ +} + +/** Value of 'beginning of padding' marker in driver-provided padding */ +#define SCC_DRIVER_PAD_CHAR 0x80 + + +/** Name of the driver. Used (on Linux, anyway) when registering interrupts */ +#define SCC_DRIVER_NAME "scc" + + +/* Port -- these symbols are defined in Linux 2.6 and later. They are defined + * here for backwards compatibility because this started life as a 2.4 + * driver, and as a guide to portation to other platforms. + */ + +#if !defined(LINUX_VERSION_CODE) || LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + +#define irqreturn_t void /* Return type of an interrupt handler */ + +#define IRQ_HANDLED /* Would be '1' for handled -- as in return IRQ_HANDLED; */ + +#define IRQ_NONE /* would be '0' for not handled -- as in return IRQ_NONE; */ + +#define IRQ_RETVAL(x) /* Return x==0 (not handled) or non-zero (handled) */ + +#endif /* LINUX earlier than 2.5 */ + + +/* These are nice to have around */ +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE 1 +#endif + + +/** Provide a typedef for the CRC which can be used in encrypt/decrypt */ +typedef uint16_t crc_t; + + +/** Gives high-level view of state of the SCC */ +enum scc_status { + SCC_STATUS_INITIAL, /**< State of driver before ever checking */ + SCC_STATUS_CHECKING, /**< Transient state while driver loading */ + SCC_STATUS_UNIMPLEMENTED, /**< SCC is non-existent or unuseable */ + SCC_STATUS_OK, /**< SCC is in Secure or Default state */ + SCC_STATUS_FAILED /**< In Failed state */ +}; + +/** + * Information about a key slot. + */ +struct scc_key_slot +{ + uint64_t owner_id; /**< Access control value. */ + uint32_t length; /**< Length of value in slot. */ + uint32_t offset; /**< Offset of value from start of RAM. */ + uint32_t status; /**< 0 = unassigned, 1 = assigned. */ + uint32_t part_ctl; /**< for the CCMD register */ +}; + +/* Forward-declare a number routines which are not part of user api */ +static int scc_init(void); +static void scc_cleanup(void); + +/* Forward defines of internal functions */ +OS_DEV_ISR(scc_irq); +/*static irqreturn_t scc_irq(int irq, void *dev_id);*/ +/** Perform callbacks registered by #scc_monitor_security_failure(). + * + * Make sure callbacks only happen once... Since there may be some reason why + * the interrupt isn't generated, this routine could be called from base(task) + * level. + * + * One at a time, go through #scc_callbacks[] and call any non-null pointers. + */ +static void scc_perform_callbacks(void); +/*static uint32_t copy_to_scc(const uint8_t* from, uint32_t to, unsigned long count_bytes, uint16_t* crc); +static uint32_t copy_from_scc(const uint32_t from, uint8_t* to,unsigned long count_bytes, uint16_t* crc); +static scc_return_t scc_strip_padding(uint8_t* from,unsigned* count_bytes_stripped);*/ +static uint32_t scc_update_state(void); +static void scc_init_ccitt_crc(void); +static uint32_t scc_grab_config_values(void); +static int setup_interrupt_handling(void); +/** + * Perform an encryption on the input. If @c verify_crc is true, a CRC must be + * calculated on the plaintext, and appended, with padding, before computing + * the ciphertext. + * + * @param[in] count_in_bytes Count of bytes of plaintext + * @param[in] data_in Pointer to the plaintext + * @param[in] scm_control Bit values for the SCM_CONTROL register + * @param[in,out] data_out Pointer for storing ciphertext + * @param[in] add_crc Flag for computing CRC - 0 no, else yes + * @param[in,out] count_out_bytes Number of bytes available at @c data_out + */ +/*static scc_return_t scc_encrypt(uint32_t count_in_bytes, uint8_t* data_in, uint32_t scm_control, uint8_t* data_out,int add_crc, unsigned long* count_out_bytes);*/ +/** + * Perform a decryption on the input. If @c verify_crc is true, the last block + * (maybe the two last blocks) is special - it should contain a CRC and + * padding. These must be stripped and verified. + * + * @param[in] count_in_bytes Count of bytes of ciphertext + * @param[in] data_in Pointer to the ciphertext + * @param[in] scm_control Bit values for the SCM_CONTROL register + * @param[in,out] data_out Pointer for storing plaintext + * @param[in] verify_crc Flag for running CRC - 0 no, else yes + * @param[in,out] count_out_bytes Number of bytes available at @c data_out + + */ +/*static scc_return_t scc_decrypt(uint32_t count_in_bytes, uint8_t* data_in, uint32_t scm_control, uint8_t* data_out, int verify_crc, unsigned long* count_out_bytes);*/ +static uint32_t host_owns_partition(uint32_t part_no); +static uint32_t partition_engaged(uint32_t part_no); + +static scc_return_t scc_wait_completion(uint32_t* scm_status); +static int is_cipher_done(uint32_t* scm_status); +static scc_return_t check_register_accessible (uint32_t offset, + uint32_t smn_status, + uint32_t scm_status); +static scc_return_t check_register_offset(uint32_t offset); +/*uint8_t make_vpu_partition(void);*/ + +#ifdef SCC_REGISTER_DEBUG +static uint32_t dbg_scc_read_register(uint32_t offset); +static void dbg_scc_write_register(uint32_t offset, uint32_t value); +#endif + + +/* For Linux kernel, export the API functions to other kernel modules */ +EXPORT_SYMBOL(scc_get_configuration); +EXPORT_SYMBOL(scc_zeroize_memories); +/*EXPORT_SYMBOL(scc_crypt);*/ +EXPORT_SYMBOL(scc_set_sw_alarm); +EXPORT_SYMBOL(scc_monitor_security_failure); +EXPORT_SYMBOL(scc_stop_monitoring_security_failure); +EXPORT_SYMBOL(scc_read_register); +EXPORT_SYMBOL(scc_write_register); +EXPORT_SYMBOL(scc_allocate_partition); +EXPORT_SYMBOL(scc_engage_partition); +EXPORT_SYMBOL(scc_release_partition); +EXPORT_SYMBOL(scc_diminish_permissions); +EXPORT_SYMBOL(scc_encrypt_region); +EXPORT_SYMBOL(scc_decrypt_region); +/*EXPORT_SYMBOL(make_vpu_partition);*/ +/* Tell Linux where to invoke driver at boot/module load time */ +module_init(scc_init); +/* Tell Linux where to invoke driver on module unload */ +module_exit(scc_cleanup); + + +/* Tell Linux this is not GPL code */ +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Device Driver for SCC (SMN/SCM)"); + + +#endif /* SCC_INTERNALS_H */ diff -urN linux-2.6.26/drivers/mxc/ssi/Kconfig linux-2.6.26-lab126/drivers/mxc/ssi/Kconfig --- linux-2.6.26/drivers/mxc/ssi/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ssi/Kconfig 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,12 @@ +# +# SPI device configuration +# + +menu "MXC SSI support" + +config MXC_SSI + tristate "SSI support" + ---help--- + Say Y to get the SSI services API available on MXC platform. + +endmenu diff -urN linux-2.6.26/drivers/mxc/ssi/Makefile linux-2.6.26-lab126/drivers/mxc/ssi/Makefile --- linux-2.6.26/drivers/mxc/ssi/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ssi/Makefile 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,7 @@ +# +# Makefile for the kernel SSI device drivers. +# + +obj-$(CONFIG_MXC_SSI) += ssimod.o + +ssimod-objs := ssi.o diff -urN linux-2.6.26/drivers/mxc/ssi/registers.h linux-2.6.26-lab126/drivers/mxc/ssi/registers.h --- linux-2.6.26/drivers/mxc/ssi/registers.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ssi/registers.h 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,208 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + /*! + * @file ../ssi/registers.h + * @brief This header file contains SSI driver low level definition to access module registers. + * + * @ingroup SSI + */ + +#ifndef __MXC_SSI_REGISTERS_H__ +#define __MXC_SSI_REGISTERS_H__ + +/*! + * This include to define bool type, false and true definitions. + */ +#include + +#define SPBA_CPU_SSI 0x07 + +#define MXC_SSISTX0 0x00 +#define MXC_SSISTX1 0x04 +#define MXC_SSISRX0 0x08 +#define MXC_SSISRX1 0x0C +#define MXC_SSISCR 0x10 +#define MXC_SSISISR 0x14 +#define MXC_SSISIER 0x18 +#define MXC_SSISTCR 0x1C +#define MXC_SSISRCR 0x20 +#define MXC_SSISTCCR 0x24 +#define MXC_SSISRCCR 0x28 +#define MXC_SSISFCSR 0x2C +#define MXC_SSISTR 0x30 +#define MXC_SSISOR 0x34 +#define MXC_SSISACNT 0x38 +#define MXC_SSISACADD 0x3C +#define MXC_SSISACDAT 0x40 +#define MXC_SSISATAG 0x44 +#define MXC_SSISTMSK 0x48 +#define MXC_SSISRMSK 0x4C + +/* MXC 91221 only */ +#define MXC_SSISACCST 0x50 +#define MXC_SSISACCEN 0x54 +#define MXC_SSISACCDIS 0x58 + +/*! SSI1 registers offset*/ +#define MXC_SSI1STX0 0x00 +#define MXC_SSI1STX1 0x04 +#define MXC_SSI1SRX0 0x08 +#define MXC_SSI1SRX1 0x0C +#define MXC_SSI1SCR 0x10 +#define MXC_SSI1SISR 0x14 +#define MXC_SSI1SIER 0x18 +#define MXC_SSI1STCR 0x1C +#define MXC_SSI1SRCR 0x20 +#define MXC_SSI1STCCR 0x24 +#define MXC_SSI1SRCCR 0x28 +#define MXC_SSI1SFCSR 0x2C +#define MXC_SSI1STR 0x30 +#define MXC_SSI1SOR 0x34 +#define MXC_SSI1SACNT 0x38 +#define MXC_SSI1SACADD 0x3C +#define MXC_SSI1SACDAT 0x40 +#define MXC_SSI1SATAG 0x44 +#define MXC_SSI1STMSK 0x48 +#define MXC_SSI1SRMSK 0x4C + +/* MXC91221 only */ + +#define MXC_SSISACCST 0x50 +#define MXC_SSISACCEN 0x54 +#define MXC_SSISACCDIS 0x58 + +/* Not on MXC91221 */ +/*! SSI2 registers offset*/ +#define MXC_SSI2STX0 0x00 +#define MXC_SSI2STX1 0x04 +#define MXC_SSI2SRX0 0x08 +#define MXC_SSI2SRX1 0x0C +#define MXC_SSI2SCR 0x10 +#define MXC_SSI2SISR 0x14 +#define MXC_SSI2SIER 0x18 +#define MXC_SSI2STCR 0x1C +#define MXC_SSI2SRCR 0x20 +#define MXC_SSI2STCCR 0x24 +#define MXC_SSI2SRCCR 0x28 +#define MXC_SSI2SFCSR 0x2C +#define MXC_SSI2STR 0x30 +#define MXC_SSI2SOR 0x34 +#define MXC_SSI2SACNT 0x38 +#define MXC_SSI2SACADD 0x3C +#define MXC_SSI2SACDAT 0x40 +#define MXC_SSI2SATAG 0x44 +#define MXC_SSI2STMSK 0x48 +#define MXC_SSI2SRMSK 0x4C + +/*! + * SCR Register bit shift definitions + */ +#define SSI_ENABLE_SHIFT 0 +#define SSI_TRANSMIT_ENABLE_SHIFT 1 +#define SSI_RECEIVE_ENABLE_SHIFT 2 +#define SSI_NETWORK_MODE_SHIFT 3 +#define SSI_SYNCHRONOUS_MODE_SHIFT 4 +#define SSI_I2S_MODE_SHIFT 5 +#define SSI_SYSTEM_CLOCK_SHIFT 7 +#define SSI_TWO_CHANNEL_SHIFT 8 +#define SSI_CLOCK_IDLE_SHIFT 9 + +/* MXC91221 only*/ +#define SSI_TX_FRAME_CLOCK_DISABLE_SHIFT 10 +#define SSI_RX_FRAME_CLOCK_DISABLE_SHIFT 11 + +/*! + * STCR & SRCR Registers bit shift definitions + */ +#define SSI_EARLY_FRAME_SYNC_SHIFT 0 +#define SSI_FRAME_SYNC_LENGTH_SHIFT 1 +#define SSI_FRAME_SYNC_INVERT_SHIFT 2 +#define SSI_CLOCK_POLARITY_SHIFT 3 +#define SSI_SHIFT_DIRECTION_SHIFT 4 +#define SSI_CLOCK_DIRECTION_SHIFT 5 +#define SSI_FRAME_DIRECTION_SHIFT 6 +#define SSI_FIFO_ENABLE_0_SHIFT 7 +#define SSI_FIFO_ENABLE_1_SHIFT 8 +#define SSI_BIT_0_SHIFT 9 + +/* MXC91221 only*/ +#define SSI_TX_FRAME_CLOCK_DISABLE_SHIFT 10 +#define SSI_RX_DATA_EXTENSION_SHIFT 10 /*SRCR only */ +/*! + * STCCR & SRCCR Registers bit shift definitions + */ +#define SSI_PRESCALER_MODULUS_SHIFT 0 +#define SSI_FRAME_RATE_DIVIDER_SHIFT 8 +#define SSI_WORD_LENGTH_SHIFT 13 +#define SSI_PRESCALER_RANGE_SHIFT 17 +#define SSI_DIVIDE_BY_TWO_SHIFT 18 +#define SSI_FRAME_DIVIDER_MASK 31 +#define SSI_MIN_FRAME_DIVIDER_RATIO 1 +#define SSI_MAX_FRAME_DIVIDER_RATIO 32 +#define SSI_PRESCALER_MODULUS_MASK 255 +#define SSI_MIN_PRESCALER_MODULUS_RATIO 1 +#define SSI_MAX_PRESCALER_MODULUS_RATIO 256 +#define SSI_WORD_LENGTH_MASK 15 + +#define SSI_IRQ_STATUS_NUMBER 25 + +/*! + * SFCSR Register bit shift definitions + */ +#define SSI_RX_FIFO_1_COUNT_SHIFT 28 +#define SSI_TX_FIFO_1_COUNT_SHIFT 24 +#define SSI_RX_FIFO_1_WATERMARK_SHIFT 20 +#define SSI_TX_FIFO_1_WATERMARK_SHIFT 16 +#define SSI_RX_FIFO_0_COUNT_SHIFT 12 +#define SSI_TX_FIFO_0_COUNT_SHIFT 8 +#define SSI_RX_FIFO_0_WATERMARK_SHIFT 4 +#define SSI_TX_FIFO_0_WATERMARK_SHIFT 0 +#define SSI_MIN_FIFO_WATERMARK 0 +#define SSI_MAX_FIFO_WATERMARK 8 + +/*! + * SSI Option Register (SOR) bit shift definitions + */ +#define SSI_FRAME_SYN_RESET_SHIFT 0 +#define SSI_WAIT_SHIFT 1 +#define SSI_INIT_SHIFT 3 +#define SSI_TRANSMITTER_CLEAR_SHIFT 4 +#define SSI_RECEIVER_CLEAR_SHIFT 5 +#define SSI_CLOCK_OFF_SHIFT 6 +#define SSI_WAIT_STATE_MASK 0x3 + +/*! + * SSI AC97 Control Register (SACNT) bit shift definitions + */ +#define AC97_MODE_ENABLE_SHIFT 0 +#define AC97_VARIABLE_OPERATION_SHIFT 1 +#define AC97_TAG_IN_FIFO_SHIFT 2 +#define AC97_READ_COMMAND_SHIFT 3 +#define AC97_WRITE_COMMAND_SHIFT 4 +#define AC97_FRAME_RATE_DIVIDER_SHIFT 5 +#define AC97_FRAME_RATE_MASK 0x3F + +/*! + * SSI Test Register (STR) bit shift definitions + */ +#define SSI_TEST_MODE_SHIFT 15 +#define SSI_RCK2TCK_SHIFT 14 +#define SSI_RFS2TFS_SHIFT 13 +#define SSI_RXSTATE_SHIFT 8 +#define SSI_TXD2RXD_SHIFT 7 +#define SSI_TCK2RCK_SHIFT 6 +#define SSI_TFS2RFS_SHIFT 5 +#define SSI_TXSTATE_SHIFT 0 + +#endif /* __MXC_SSI_REGISTERS_H__ */ diff -urN linux-2.6.26/drivers/mxc/ssi/ssi.c linux-2.6.26-lab126/drivers/mxc/ssi/ssi.c --- linux-2.6.26/drivers/mxc/ssi/ssi.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ssi/ssi.c 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,1238 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ssi.c + * @brief This file contains the implementation of the SSI driver main services + * + * + * @ingroup SSI + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "registers.h" +#include "ssi.h" + +static spinlock_t ssi_lock; +struct mxc_audio_platform_data *ssi_platform_data; + +EXPORT_SYMBOL(ssi_ac97_frame_rate_divider); +EXPORT_SYMBOL(ssi_ac97_get_command_address_register); +EXPORT_SYMBOL(ssi_ac97_get_command_data_register); +EXPORT_SYMBOL(ssi_ac97_get_tag_register); +EXPORT_SYMBOL(ssi_ac97_mode_enable); +EXPORT_SYMBOL(ssi_ac97_tag_in_fifo); +EXPORT_SYMBOL(ssi_ac97_read_command); +EXPORT_SYMBOL(ssi_ac97_set_command_address_register); +EXPORT_SYMBOL(ssi_ac97_set_command_data_register); +EXPORT_SYMBOL(ssi_ac97_set_tag_register); +EXPORT_SYMBOL(ssi_ac97_variable_mode); +EXPORT_SYMBOL(ssi_ac97_write_command); +EXPORT_SYMBOL(ssi_clock_idle_state); +EXPORT_SYMBOL(ssi_clock_off); +EXPORT_SYMBOL(ssi_enable); +EXPORT_SYMBOL(ssi_get_data); +EXPORT_SYMBOL(ssi_get_status); +EXPORT_SYMBOL(ssi_i2s_mode); +EXPORT_SYMBOL(ssi_interrupt_disable); +EXPORT_SYMBOL(ssi_interrupt_enable); +EXPORT_SYMBOL(ssi_network_mode); +EXPORT_SYMBOL(ssi_receive_enable); +EXPORT_SYMBOL(ssi_rx_bit0); +EXPORT_SYMBOL(ssi_rx_clock_direction); +EXPORT_SYMBOL(ssi_rx_clock_divide_by_two); +EXPORT_SYMBOL(ssi_rx_clock_polarity); +EXPORT_SYMBOL(ssi_rx_clock_prescaler); +EXPORT_SYMBOL(ssi_rx_early_frame_sync); +EXPORT_SYMBOL(ssi_rx_fifo_counter); +EXPORT_SYMBOL(ssi_rx_fifo_enable); +EXPORT_SYMBOL(ssi_rx_fifo_full_watermark); +EXPORT_SYMBOL(ssi_rx_flush_fifo); +EXPORT_SYMBOL(ssi_rx_frame_direction); +EXPORT_SYMBOL(ssi_rx_frame_rate); +EXPORT_SYMBOL(ssi_rx_frame_sync_active); +EXPORT_SYMBOL(ssi_rx_frame_sync_length); +EXPORT_SYMBOL(ssi_rx_mask_time_slot); +EXPORT_SYMBOL(ssi_rx_prescaler_modulus); +EXPORT_SYMBOL(ssi_rx_shift_direction); +EXPORT_SYMBOL(ssi_rx_word_length); +EXPORT_SYMBOL(ssi_set_data); +EXPORT_SYMBOL(ssi_set_wait_states); +EXPORT_SYMBOL(ssi_synchronous_mode); +EXPORT_SYMBOL(ssi_system_clock); +EXPORT_SYMBOL(ssi_transmit_enable); +EXPORT_SYMBOL(ssi_two_channel_mode); +EXPORT_SYMBOL(ssi_tx_bit0); +EXPORT_SYMBOL(ssi_tx_clock_direction); +EXPORT_SYMBOL(ssi_tx_clock_divide_by_two); +EXPORT_SYMBOL(ssi_tx_clock_polarity); +EXPORT_SYMBOL(ssi_tx_clock_prescaler); +EXPORT_SYMBOL(ssi_tx_early_frame_sync); +EXPORT_SYMBOL(ssi_tx_fifo_counter); +EXPORT_SYMBOL(ssi_tx_fifo_empty_watermark); +EXPORT_SYMBOL(ssi_tx_fifo_enable); +EXPORT_SYMBOL(ssi_tx_flush_fifo); +EXPORT_SYMBOL(ssi_tx_frame_direction); +EXPORT_SYMBOL(ssi_tx_frame_rate); +EXPORT_SYMBOL(ssi_tx_frame_sync_active); +EXPORT_SYMBOL(ssi_tx_frame_sync_length); +EXPORT_SYMBOL(ssi_tx_mask_time_slot); +EXPORT_SYMBOL(ssi_tx_prescaler_modulus); +EXPORT_SYMBOL(ssi_tx_shift_direction); +EXPORT_SYMBOL(ssi_tx_word_length); +EXPORT_SYMBOL(get_ssi_fifo_addr); + +struct resource *res; +void *base_addr_1; +void *base_addr_2; + +unsigned int get_ssi_fifo_addr(unsigned int ssi, int direction) +{ + unsigned int fifo_addr; + if (direction == 1) { + if (ssi_platform_data->ssi_num == 2) { + fifo_addr = + (ssi == + SSI1) ? (int)(base_addr_1 + + MXC_SSI1STX0) : (int)(base_addr_2 + + MXC_SSI2STX0); + } else { + fifo_addr = (int)(base_addr_1 + MXC_SSI1STX0); + } + } else { + fifo_addr = (int)(base_addr_1 + MXC_SSI1SRX0); + } + return fifo_addr; +} + +unsigned int get_ssi_base_addr(unsigned int ssi) +{ + int base_addr; + if (ssi_platform_data->ssi_num == 2) { + base_addr = + (ssi == + SSI1) ? IO_ADDRESS((int)base_addr_1) : IO_ADDRESS((int) + base_addr_2); + } else { + base_addr = IO_ADDRESS((int)base_addr_1); + } + return base_addr; +} + +void set_register_bits(unsigned int mask, unsigned int data, + unsigned int offset, unsigned int ssi) +{ + volatile unsigned long reg = 0; + unsigned int base_addr = 0; + unsigned long flags = 0; + + spin_lock_irqsave(&ssi_lock, flags); + base_addr = get_ssi_base_addr(ssi); + reg = __raw_readl(base_addr + offset); + reg = (reg & (~mask)) | data; + __raw_writel(reg, base_addr + offset); + spin_unlock_irqrestore(&ssi_lock, flags); +} + +unsigned long getreg_value(unsigned int offset, unsigned int ssi) +{ + volatile unsigned long reg = 0; + unsigned int base_addr = 0; + unsigned long flags = 0; + + spin_lock_irqsave(&ssi_lock, flags); + base_addr = get_ssi_base_addr(ssi); + reg = __raw_readl(base_addr + offset); + spin_unlock_irqrestore(&ssi_lock, flags); + + return reg; +} + +void set_register(unsigned int data, unsigned int offset, unsigned int ssi) +{ + unsigned int base_addr = 0; + unsigned long flags = 0; + + spin_lock_irqsave(&ssi_lock, flags); + base_addr = get_ssi_base_addr(ssi); + __raw_writel(data, base_addr + offset); + spin_unlock_irqrestore(&ssi_lock, flags); + +} + +/*! + * This function controls the AC97 frame rate divider. + * + * @param module the module number + * @param frame_rate_divider the AC97 frame rate divider + */ +void ssi_ac97_frame_rate_divider(ssi_mod module, + unsigned char frame_rate_divider) +{ + unsigned int reg = 0; + + reg = getreg_value(MXC_SSISACNT, module); + reg |= ((frame_rate_divider & AC97_FRAME_RATE_MASK) + << AC97_FRAME_RATE_DIVIDER_SHIFT); + set_register(reg, MXC_SSISACNT, module); +} + +/*! + * This function gets the AC97 command address register. + * + * @param module the module number + * @return This function returns the command address slot information. + */ +unsigned int ssi_ac97_get_command_address_register(ssi_mod module) +{ + return getreg_value(MXC_SSISACADD, module); +} + +/*! + * This function gets the AC97 command data register. + * + * @param module the module number + * @return This function returns the command data slot information. + */ +unsigned int ssi_ac97_get_command_data_register(ssi_mod module) +{ + return getreg_value(MXC_SSISACDAT, module); +} + +/*! + * This function gets the AC97 tag register. + * + * @param module the module number + * @return This function returns the tag information. + */ +unsigned int ssi_ac97_get_tag_register(ssi_mod module) +{ + return getreg_value(MXC_SSISATAG, module); +} + +/*! + * This function controls the AC97 mode. + * + * @param module the module number + * @param state the AC97 mode state (enabled or disabled) + */ +void ssi_ac97_mode_enable(ssi_mod module, bool state) +{ + unsigned int reg = 0; + + reg = getreg_value(MXC_SSISACNT, module); + if (state == true) { + reg |= (1 << AC97_MODE_ENABLE_SHIFT); + } else { + reg &= ~(1 << AC97_MODE_ENABLE_SHIFT); + } + + set_register(reg, MXC_SSISACNT, module); +} + +/*! + * This function controls the AC97 tag in FIFO behavior. + * + * @param module the module number + * @param state the tag in fifo behavior (Tag info stored in Rx FIFO 0 if true, + * Tag info stored in SATAG register otherwise) + */ +void ssi_ac97_tag_in_fifo(ssi_mod module, bool state) +{ + unsigned int reg = 0; + + reg = getreg_value(MXC_SSISACNT, module); + if (state == true) { + reg |= (1 << AC97_TAG_IN_FIFO_SHIFT); + } else { + reg &= ~(1 << AC97_TAG_IN_FIFO_SHIFT); + } + + set_register(reg, MXC_SSISACNT, module); +} + +/*! + * This function controls the AC97 read command. + * + * @param module the module number + * @param state the next AC97 command is a read command or not + */ +void ssi_ac97_read_command(ssi_mod module, bool state) +{ + unsigned int reg = 0; + + reg = getreg_value(MXC_SSISACNT, module); + if (state == true) { + reg |= (1 << AC97_READ_COMMAND_SHIFT); + } else { + reg &= ~(1 << AC97_READ_COMMAND_SHIFT); + } + + set_register(reg, MXC_SSISACNT, module); +} + +/*! + * This function sets the AC97 command address register. + * + * @param module the module number + * @param address the command address slot information + */ +void ssi_ac97_set_command_address_register(ssi_mod module, unsigned int address) +{ + set_register(address, MXC_SSISACADD, module); +} + +/*! + * This function sets the AC97 command data register. + * + * @param module the module number + * @param data the command data slot information + */ +void ssi_ac97_set_command_data_register(ssi_mod module, unsigned int data) +{ + set_register(data, MXC_SSISACDAT, module); +} + +/*! + * This function sets the AC97 tag register. + * + * @param module the module number + * @param tag the tag information + */ +void ssi_ac97_set_tag_register(ssi_mod module, unsigned int tag) +{ + set_register(tag, MXC_SSISATAG, module); +} + +/*! + * This function controls the AC97 variable mode. + * + * @param module the module number + * @param state the AC97 variable mode state (enabled or disabled) + */ void ssi_ac97_variable_mode(ssi_mod module, bool state) +{ + unsigned int reg = 0; + + reg = getreg_value(MXC_SSISACNT, module); + if (state == true) { + reg |= (1 << AC97_VARIABLE_OPERATION_SHIFT); + } else { + reg &= ~(1 << AC97_VARIABLE_OPERATION_SHIFT); + } + + set_register(reg, MXC_SSISACNT, module); +} + +/*! + * This function controls the AC97 write command. + * + * @param module the module number + * @param state the next AC97 command is a write command or not + */ +void ssi_ac97_write_command(ssi_mod module, bool state) +{ + unsigned int reg = 0; + + reg = getreg_value(MXC_SSISACNT, module); + if (state == true) { + reg |= (1 << AC97_WRITE_COMMAND_SHIFT); + } else { + reg &= ~(1 << AC97_WRITE_COMMAND_SHIFT); + } + + set_register(reg, MXC_SSISACNT, module); +} + +/*! + * This function controls the idle state of the transmit clock port during SSI internal gated mode. + * + * @param module the module number + * @param state the clock idle state + */ +void ssi_clock_idle_state(ssi_mod module, idle_state state) +{ + set_register_bits(1 << SSI_CLOCK_IDLE_SHIFT, + state << SSI_CLOCK_IDLE_SHIFT, MXC_SSISCR, module); +} + +/*! + * This function turns off/on the ccm_ssi_clk to reduce power consumption. + * + * @param module the module number + * @param state the state for ccm_ssi_clk (true: turn off, else:turn on) + */ +void ssi_clock_off(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_CLOCK_OFF_SHIFT, + state << SSI_CLOCK_OFF_SHIFT, MXC_SSISOR, module); +} + +/*! + * This function enables/disables the SSI module. + * + * @param module the module number + * @param state the state for SSI module + */ +void ssi_enable(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_ENABLE_SHIFT, state << SSI_ENABLE_SHIFT, + MXC_SSISCR, module); +} + +/*! + * This function gets the data word in the Receive FIFO of the SSI module. + * + * @param module the module number + * @param fifo the Receive FIFO to read + * @return This function returns the read data. + */ +unsigned int ssi_get_data(ssi_mod module, fifo_nb fifo) +{ + unsigned int result = 0; + + if (ssi_fifo_0 == fifo) { + result = getreg_value(MXC_SSISRX0, module); + } else { + result = getreg_value(MXC_SSISRX1, module); + } + + return result; +} + +/*! + * This function returns the status of the SSI module (SISR register) as a combination of status. + * + * @param module the module number + * @return This function returns the status of the SSI module + */ +ssi_status_enable_mask ssi_get_status(ssi_mod module) +{ + unsigned int result; + + result = getreg_value(MXC_SSISISR, module); + result &= ((1 << SSI_IRQ_STATUS_NUMBER) - 1); + + return (ssi_status_enable_mask) result; +} + +/*! + * This function selects the I2S mode of the SSI module. + * + * @param module the module number + * @param mode the I2S mode + */ +void ssi_i2s_mode(ssi_mod module, mode_i2s mode) +{ + set_register_bits(3 << SSI_I2S_MODE_SHIFT, mode << SSI_I2S_MODE_SHIFT, + MXC_SSISCR, module); +} + +/*! + * This function disables the interrupts of the SSI module. + * + * @param module the module number + * @param mask the mask of the interrupts to disable + */ +void ssi_interrupt_disable(ssi_mod module, ssi_status_enable_mask mask) +{ + set_register_bits(mask, 0, MXC_SSISIER, module); +} + +/*! + * This function enables the interrupts of the SSI module. + * + * @param module the module number + * @param mask the mask of the interrupts to enable + */ +void ssi_interrupt_enable(ssi_mod module, ssi_status_enable_mask mask) +{ + set_register_bits(0, mask, MXC_SSISIER, module); +} + +/*! + * This function enables/disables the network mode of the SSI module. + * + * @param module the module number + * @param state the network mode state + */ +void ssi_network_mode(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_NETWORK_MODE_SHIFT, + state << SSI_NETWORK_MODE_SHIFT, MXC_SSISCR, module); +} + +/*! + * This function enables/disables the receive section of the SSI module. + * + * @param module the module number + * @param state the receive section state + */ +void ssi_receive_enable(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_RECEIVE_ENABLE_SHIFT, + state << SSI_RECEIVE_ENABLE_SHIFT, MXC_SSISCR, + module); +} + +/*! + * This function configures the SSI module to receive data word at bit position 0 or 23 in the Receive shift register. + * + * @param module the module number + * @param state the state to receive at bit 0 + */ +void ssi_rx_bit0(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_BIT_0_SHIFT, state << SSI_BIT_0_SHIFT, + MXC_SSISRCR, module); +} + +/*! + * This function controls the source of the clock signal used to clock the Receive shift register. + * + * @param module the module number + * @param direction the clock signal direction + */ +void ssi_rx_clock_direction(ssi_mod module, ssi_tx_rx_direction direction) +{ + set_register_bits(1 << SSI_CLOCK_DIRECTION_SHIFT, + direction << SSI_CLOCK_DIRECTION_SHIFT, MXC_SSISRCR, + module); +} + +/*! + * This function configures the divide-by-two divider of the SSI module for the receive section. + * + * @param module the module number + * @param state the divider state + */ +void ssi_rx_clock_divide_by_two(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_DIVIDE_BY_TWO_SHIFT, + state << SSI_DIVIDE_BY_TWO_SHIFT, MXC_SSISRCCR, + module); +} + +/*! + * This function controls which bit clock edge is used to clock in data. + * + * @param module the module number + * @param polarity the clock polarity + */ +void ssi_rx_clock_polarity(ssi_mod module, ssi_tx_rx_clock_polarity polarity) +{ + set_register_bits(1 << SSI_CLOCK_POLARITY_SHIFT, + polarity << SSI_CLOCK_POLARITY_SHIFT, MXC_SSISRCR, + module); +} + +/*! + * This function configures a fixed divide-by-eight clock prescaler divider of the SSI module in series with the variable prescaler for the receive section. + * + * @param module the module number + * @param state the prescaler state + */ +void ssi_rx_clock_prescaler(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_PRESCALER_RANGE_SHIFT, + state << SSI_PRESCALER_RANGE_SHIFT, + MXC_SSISRCCR, module); +} + +/*! + * This function controls the early frame sync configuration. + * + * @param module the module number + * @param early the early frame sync configuration + */ +void ssi_rx_early_frame_sync(ssi_mod module, ssi_tx_rx_early_frame_sync early) +{ + set_register_bits(1 << SSI_EARLY_FRAME_SYNC_SHIFT, + early << SSI_EARLY_FRAME_SYNC_SHIFT, + MXC_SSISRCR, module); +} + +/*! + * This function gets the number of data words in the Receive FIFO. + * + * @param module the module number + * @param fifo the fifo + * @return This function returns the number of words in the Rx FIFO. + */ +unsigned char ssi_rx_fifo_counter(ssi_mod module, fifo_nb fifo) +{ + unsigned char result; + result = 0; + + if (ssi_fifo_0 == fifo) { + result = getreg_value(MXC_SSISFCSR, module); + result &= (0xF << SSI_RX_FIFO_0_COUNT_SHIFT); + result = result >> SSI_RX_FIFO_0_COUNT_SHIFT; + } else { + result = getreg_value(MXC_SSISFCSR, module); + result &= (0xF << SSI_RX_FIFO_1_COUNT_SHIFT); + result = result >> SSI_RX_FIFO_1_COUNT_SHIFT; + } + + return result; +} + +/*! + * This function enables the Receive FIFO. + * + * @param module the module number + * @param fifo the fifo to enable + * @param enable the state of the fifo, enabled or disabled + */ + +void ssi_rx_fifo_enable(ssi_mod module, fifo_nb fifo, bool enable) +{ + volatile unsigned int reg; + + reg = getreg_value(MXC_SSISRCR, module); + if (enable == true) { + reg |= ((1 + fifo) << SSI_FIFO_ENABLE_0_SHIFT); + } else { + reg &= ~((1 + fifo) << SSI_FIFO_ENABLE_0_SHIFT); + } + + set_register(reg, MXC_SSISRCR, module); +} + +/*! + * This function controls the threshold at which the RFFx flag will be set. + * + * @param module the module number + * @param fifo the fifo to enable + * @param watermark the watermark + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_rx_fifo_full_watermark(ssi_mod module, + fifo_nb fifo, unsigned char watermark) +{ + int result = -1; + result = -1; + + if ((watermark > SSI_MIN_FIFO_WATERMARK) && + (watermark <= SSI_MAX_FIFO_WATERMARK)) { + if (ssi_fifo_0 == fifo) { + set_register_bits(0xf << SSI_RX_FIFO_0_WATERMARK_SHIFT, + watermark << + SSI_RX_FIFO_0_WATERMARK_SHIFT, + MXC_SSISFCSR, module); + } else { + set_register_bits(0xf << SSI_RX_FIFO_1_WATERMARK_SHIFT, + watermark << + SSI_RX_FIFO_1_WATERMARK_SHIFT, + MXC_SSISFCSR, module); + } + + result = 0; + } + + return result; +} + +/*! + * This function flushes the Receive FIFOs. + * + * @param module the module number + */ +void ssi_rx_flush_fifo(ssi_mod module) +{ + set_register_bits(0, 1 << SSI_RECEIVER_CLEAR_SHIFT, MXC_SSISOR, module); +} + +/*! + * This function controls the direction of the Frame Sync signal for the receive section. + * + * @param module the module number + * @param direction the Frame Sync signal direction + */ +void ssi_rx_frame_direction(ssi_mod module, ssi_tx_rx_direction direction) +{ + set_register_bits(1 << SSI_FRAME_DIRECTION_SHIFT, + direction << SSI_FRAME_DIRECTION_SHIFT, + MXC_SSISRCR, module); +} + +/*! + * This function configures the Receive frame rate divider for the receive section. + * + * @param module the module number + * @param ratio the divide ratio from 1 to 32 + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_rx_frame_rate(ssi_mod module, unsigned char ratio) +{ + int result = -1; + + if ((ratio >= SSI_MIN_FRAME_DIVIDER_RATIO) && + (ratio <= SSI_MAX_FRAME_DIVIDER_RATIO)) { + set_register_bits(SSI_FRAME_DIVIDER_MASK << + SSI_FRAME_RATE_DIVIDER_SHIFT, + (ratio - 1) << SSI_FRAME_RATE_DIVIDER_SHIFT, + MXC_SSISRCCR, module); + result = 0; + } + + return result; +} + +/*! + * This function controls the Frame Sync active polarity for the receive section. + * + * @param module the module number + * @param active the Frame Sync active polarity + */ +void ssi_rx_frame_sync_active(ssi_mod module, + ssi_tx_rx_frame_sync_active active) +{ + set_register_bits(1 << SSI_FRAME_SYNC_INVERT_SHIFT, + active << SSI_FRAME_SYNC_INVERT_SHIFT, + MXC_SSISRCR, module); +} + +/*! + * This function controls the Frame Sync length (one word or one bit long) for the receive section. + * + * @param module the module number + * @param length the Frame Sync length + */ +void ssi_rx_frame_sync_length(ssi_mod module, + ssi_tx_rx_frame_sync_length length) +{ + set_register_bits(1 << SSI_FRAME_SYNC_LENGTH_SHIFT, + length << SSI_FRAME_SYNC_LENGTH_SHIFT, + MXC_SSISRCR, module); +} + +/*! + * This function configures the time slot(s) to mask for the receive section. + * + * @param module the module number + * @param mask the mask to indicate the time slot(s) masked + */ +void ssi_rx_mask_time_slot(ssi_mod module, unsigned int mask) +{ + set_register_bits(0xFFFFFFFF, mask, MXC_SSISRMSK, module); +} + +/*! + * This function configures the Prescale divider for the receive section. + * + * @param module the module number + * @param divider the divide ratio from 1 to 256 + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_rx_prescaler_modulus(ssi_mod module, unsigned int divider) +{ + int result = -1; + + if ((divider >= SSI_MIN_PRESCALER_MODULUS_RATIO) && + (divider <= SSI_MAX_PRESCALER_MODULUS_RATIO)) { + + set_register_bits(SSI_PRESCALER_MODULUS_MASK << + SSI_PRESCALER_MODULUS_SHIFT, + (divider - 1) << SSI_PRESCALER_MODULUS_SHIFT, + MXC_SSISRCCR, module); + result = 0; + } + + return result; +} + +/*! + * This function controls whether the MSB or LSB will be received first in a sample. + * + * @param module the module number + * @param direction the shift direction + */ +void ssi_rx_shift_direction(ssi_mod module, ssi_tx_rx_shift_direction direction) +{ + set_register_bits(1 << SSI_SHIFT_DIRECTION_SHIFT, + direction << SSI_SHIFT_DIRECTION_SHIFT, + MXC_SSISRCR, module); +} + +/*! + * This function configures the Receive word length. + * + * @param module the module number + * @param length the word length + */ +void ssi_rx_word_length(ssi_mod module, ssi_word_length length) +{ + set_register_bits(SSI_WORD_LENGTH_MASK << SSI_WORD_LENGTH_SHIFT, + length << SSI_WORD_LENGTH_SHIFT, + MXC_SSISRCCR, module); +} + +/*! + * This function sets the data word in the Transmit FIFO of the SSI module. + * + * @param module the module number + * @param fifo the FIFO number + * @param data the data to load in the FIFO + */ + +void ssi_set_data(ssi_mod module, fifo_nb fifo, unsigned int data) +{ + if (ssi_fifo_0 == fifo) { + set_register(data, MXC_SSISTX0, module); + } else { + set_register(data, MXC_SSISTX1, module); + } +} + +/*! + * This function controls the number of wait states between the core and SSI. + * + * @param module the module number + * @param wait the number of wait state(s) + */ +void ssi_set_wait_states(ssi_mod module, ssi_wait_states wait) +{ + set_register_bits(SSI_WAIT_STATE_MASK << SSI_WAIT_SHIFT, + wait << SSI_WAIT_SHIFT, MXC_SSISOR, module); +} + +/*! + * This function enables/disables the synchronous mode of the SSI module. + * + * @param module the module number + * @param state the synchronous mode state + */ +void ssi_synchronous_mode(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_SYNCHRONOUS_MODE_SHIFT, + state << SSI_SYNCHRONOUS_MODE_SHIFT, + MXC_SSISCR, module); +} + +/*! + * This function allows the SSI module to output the SYS_CLK at the SRCK port. + * + * @param module the module number + * @param state the system clock state + */ +void ssi_system_clock(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_SYSTEM_CLOCK_SHIFT, + state << SSI_SYSTEM_CLOCK_SHIFT, MXC_SSISCR, module); +} + +/*! + * This function enables/disables the transmit section of the SSI module. + * + * @param module the module number + * @param state the transmit section state + */ +void ssi_transmit_enable(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_TRANSMIT_ENABLE_SHIFT, + state << SSI_TRANSMIT_ENABLE_SHIFT, + MXC_SSISCR, module); +} + +/*! + * This function allows the SSI module to operate in the two channel mode. + * + * @param module the module number + * @param state the two channel mode state + */ +void ssi_two_channel_mode(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_TWO_CHANNEL_SHIFT, + state << SSI_TWO_CHANNEL_SHIFT, MXC_SSISCR, module); +} + +/*! + * This function configures the SSI module to transmit data word from bit position 0 or 23 in the Transmit shift register. + * + * @param module the module number + * @param state the transmit from bit 0 state + */ +void ssi_tx_bit0(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_BIT_0_SHIFT, + state << SSI_BIT_0_SHIFT, MXC_SSISTCR, module); +} + +/*! + * This function controls the direction of the clock signal used to clock the Transmit shift register. + * + * @param module the module number + * @param direction the clock signal direction + */ +void ssi_tx_clock_direction(ssi_mod module, ssi_tx_rx_direction direction) +{ + set_register_bits(1 << SSI_CLOCK_DIRECTION_SHIFT, + direction << SSI_CLOCK_DIRECTION_SHIFT, + MXC_SSISTCR, module); +} + +/*! + * This function configures the divide-by-two divider of the SSI module for the transmit section. + * + * @param module the module number + * @param state the divider state + */ +void ssi_tx_clock_divide_by_two(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_DIVIDE_BY_TWO_SHIFT, + state << SSI_DIVIDE_BY_TWO_SHIFT, + MXC_SSISTCCR, module); +} + +/*! + * This function controls which bit clock edge is used to clock out data. + * + * @param module the module number + * @param polarity the clock polarity + */ +void ssi_tx_clock_polarity(ssi_mod module, ssi_tx_rx_clock_polarity polarity) +{ + set_register_bits(1 << SSI_CLOCK_POLARITY_SHIFT, + polarity << SSI_CLOCK_POLARITY_SHIFT, + MXC_SSISTCR, module); +} + +/*! + * This function configures a fixed divide-by-eight clock prescaler divider of the SSI module in series with the variable prescaler for the transmit section. + * + * @param module the module number + * @param state the prescaler state + */ +void ssi_tx_clock_prescaler(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_PRESCALER_RANGE_SHIFT, + state << SSI_PRESCALER_RANGE_SHIFT, + MXC_SSISTCCR, module); +} + +/*! + * This function controls the early frame sync configuration for the transmit section. + * + * @param module the module number + * @param early the early frame sync configuration + */ +void ssi_tx_early_frame_sync(ssi_mod module, ssi_tx_rx_early_frame_sync early) +{ + set_register_bits(1 << SSI_EARLY_FRAME_SYNC_SHIFT, + early << SSI_EARLY_FRAME_SYNC_SHIFT, + MXC_SSISTCR, module); +} + +/*! + * This function gets the number of data words in the Transmit FIFO. + * + * @param module the module number + * @param fifo the fifo + * @return This function returns the number of words in the Tx FIFO. + */ +unsigned char ssi_tx_fifo_counter(ssi_mod module, fifo_nb fifo) +{ + unsigned char result = 0; + + if (ssi_fifo_0 == fifo) { + result = getreg_value(MXC_SSISFCSR, module); + result &= (0xF << SSI_TX_FIFO_0_COUNT_SHIFT); + result >>= SSI_TX_FIFO_0_COUNT_SHIFT; + } else { + result = getreg_value(MXC_SSISFCSR, module); + result &= (0xF << SSI_TX_FIFO_1_COUNT_SHIFT); + result >>= SSI_TX_FIFO_1_COUNT_SHIFT; + } + + return result; +} + +/*! + * This function controls the threshold at which the TFEx flag will be set. + * + * @param module the module number + * @param fifo the fifo to enable + * @param watermark the watermark + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_tx_fifo_empty_watermark(ssi_mod module, + fifo_nb fifo, unsigned char watermark) +{ + int result = -1; + + if ((watermark > SSI_MIN_FIFO_WATERMARK) && + (watermark <= SSI_MAX_FIFO_WATERMARK)) { + if (ssi_fifo_0 == fifo) { + set_register_bits(0xf << SSI_TX_FIFO_0_WATERMARK_SHIFT, + watermark << + SSI_TX_FIFO_0_WATERMARK_SHIFT, + MXC_SSISFCSR, module); + } else { + set_register_bits(0xf << SSI_TX_FIFO_1_WATERMARK_SHIFT, + watermark << + SSI_TX_FIFO_1_WATERMARK_SHIFT, + MXC_SSISFCSR, module); + } + + result = 0; + } + + return result; +} + +/*! + * This function enables the Transmit FIFO. + * + * @param module the module number + * @param fifo the fifo to enable + * @param enable the state of the fifo, enabled or disabled + */ + +void ssi_tx_fifo_enable(ssi_mod module, fifo_nb fifo, bool enable) +{ + unsigned int reg; + + reg = getreg_value(MXC_SSISTCR, module); + if (enable == true) { + reg |= ((1 + fifo) << SSI_FIFO_ENABLE_0_SHIFT); + } else { + reg &= ~((1 + fifo) << SSI_FIFO_ENABLE_0_SHIFT); + } + + set_register(reg, MXC_SSISTCR, module); +} + +/*! + * This function flushes the Transmit FIFOs. + * + * @param module the module number + */ +void ssi_tx_flush_fifo(ssi_mod module) +{ + set_register_bits(0, 1 << SSI_TRANSMITTER_CLEAR_SHIFT, + MXC_SSISOR, module); +} + +/*! + * This function controls the direction of the Frame Sync signal for the transmit section. + * + * @param module the module number + * @param direction the Frame Sync signal direction + */ +void ssi_tx_frame_direction(ssi_mod module, ssi_tx_rx_direction direction) +{ + set_register_bits(1 << SSI_FRAME_DIRECTION_SHIFT, + direction << SSI_FRAME_DIRECTION_SHIFT, + MXC_SSISTCR, module); +} + +/*! + * This function configures the Transmit frame rate divider. + * + * @param module the module number + * @param ratio the divide ratio from 1 to 32 + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_tx_frame_rate(ssi_mod module, unsigned char ratio) +{ + int result = -1; + + if ((ratio >= SSI_MIN_FRAME_DIVIDER_RATIO) && + (ratio <= SSI_MAX_FRAME_DIVIDER_RATIO)) { + + set_register_bits(SSI_FRAME_DIVIDER_MASK << + SSI_FRAME_RATE_DIVIDER_SHIFT, + (ratio - 1) << SSI_FRAME_RATE_DIVIDER_SHIFT, + MXC_SSISTCCR, module); + result = 0; + } + + return result; +} + +/*! + * This function controls the Frame Sync active polarity for the transmit section. + * + * @param module the module number + * @param active the Frame Sync active polarity + */ +void ssi_tx_frame_sync_active(ssi_mod module, + ssi_tx_rx_frame_sync_active active) +{ + set_register_bits(1 << SSI_FRAME_SYNC_INVERT_SHIFT, + active << SSI_FRAME_SYNC_INVERT_SHIFT, + MXC_SSISTCR, module); +} + +/*! + * This function controls the Frame Sync length (one word or one bit long) for the transmit section. + * + * @param module the module number + * @param length the Frame Sync length + */ +void ssi_tx_frame_sync_length(ssi_mod module, + ssi_tx_rx_frame_sync_length length) +{ + set_register_bits(1 << SSI_FRAME_SYNC_LENGTH_SHIFT, + length << SSI_FRAME_SYNC_LENGTH_SHIFT, + MXC_SSISTCR, module); +} + +/*! + * This function configures the time slot(s) to mask for the transmit section. + * + * @param module the module number + * @param mask the mask to indicate the time slot(s) masked + */ +void ssi_tx_mask_time_slot(ssi_mod module, unsigned int mask) +{ + set_register_bits(0xFFFFFFFF, mask, MXC_SSISTMSK, module); +} + +/*! + * This function configures the Prescale divider for the transmit section. + * + * @param module the module number + * @param divider the divide ratio from 1 to 256 + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_tx_prescaler_modulus(ssi_mod module, unsigned int divider) +{ + int result = -1; + + if ((divider >= SSI_MIN_PRESCALER_MODULUS_RATIO) && + (divider <= SSI_MAX_PRESCALER_MODULUS_RATIO)) { + + set_register_bits(SSI_PRESCALER_MODULUS_MASK << + SSI_PRESCALER_MODULUS_SHIFT, + (divider - 1) << SSI_PRESCALER_MODULUS_SHIFT, + MXC_SSISTCCR, module); + result = 0; + } + + return result; +} + +/*! + * This function controls whether the MSB or LSB will be transmitted first in a sample. + * + * @param module the module number + * @param direction the shift direction + */ +void ssi_tx_shift_direction(ssi_mod module, ssi_tx_rx_shift_direction direction) +{ + set_register_bits(1 << SSI_SHIFT_DIRECTION_SHIFT, + direction << SSI_SHIFT_DIRECTION_SHIFT, + MXC_SSISTCR, module); +} + +/*! + * This function configures the Transmit word length. + * + * @param module the module number + * @param length the word length + */ +void ssi_tx_word_length(ssi_mod module, ssi_word_length length) +{ + set_register_bits(SSI_WORD_LENGTH_MASK << SSI_WORD_LENGTH_SHIFT, + length << SSI_WORD_LENGTH_SHIFT, + MXC_SSISTCCR, module); +} + +/*! + * This function initializes the driver in terms of memory of the soundcard + * and some basic HW clock settings. + * + * @return 0 on success, -1 otherwise. + */ +static int __init ssi_probe(struct platform_device *pdev) +{ + int ret = -1; + ssi_platform_data = + (struct mxc_audio_platform_data *)pdev->dev.platform_data; + if (!ssi_platform_data) { + dev_err(&pdev->dev, "can't get the platform data for SSI\n"); + return -EINVAL; + } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (!res) { + dev_err(&pdev->dev, "can't get platform resource - SSI\n"); + ret = -ENOMEM; + goto err; + } + + if (pdev->id == 0) { + base_addr_1 = (void *)res->start; + } else if (pdev->id == 1) { + base_addr_2 = (void *)res->start; + } + + printk(KERN_INFO "SSI %d module loaded successfully \n", pdev->id + 1); + + return 0; + err: + return -1; + +} + +static int ssi_remove(struct platform_device *dev) +{ + return 0; +} + +static struct platform_driver mxc_ssi_driver = { + .probe = ssi_probe, + .remove = ssi_remove, + .driver = { + .name = "mxc_ssi", + }, +}; + +/*! + * This function implements the init function of the SSI device. + * This function is called when the module is loaded. + * + * @return This function returns 0. + */ +static int __init ssi_init(void) +{ + spin_lock_init(&ssi_lock); + return platform_driver_register(&mxc_ssi_driver); + +} + +/*! + * This function implements the exit function of the SPI device. + * This function is called when the module is unloaded. + * + */ +static void __exit ssi_exit(void) +{ + platform_driver_unregister(&mxc_ssi_driver); + printk(KERN_INFO "SSI module unloaded successfully\n"); +} + +module_init(ssi_init); +module_exit(ssi_exit); + +MODULE_DESCRIPTION("SSI char device driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/mxc/ssi/ssi.h linux-2.6.26-lab126/drivers/mxc/ssi/ssi.h --- linux-2.6.26/drivers/mxc/ssi/ssi.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ssi/ssi.h 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,574 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + /*! + * @defgroup SSI Synchronous Serial Interface (SSI) Driver + */ + + /*! + * @file ssi.h + * @brief This header file contains SSI driver functions prototypes. + * + * @ingroup SSI + */ + +#ifndef __MXC_SSI_H__ +#define __MXC_SSI_H__ + +#include "ssi_types.h" + +/*! + * This function gets the SSI fifo address. + * + * @param ssi ssi number + * @param direction To indicate playback / recording + * @return This function returns the SSI fifo address. + */ +unsigned int get_ssi_fifo_addr(unsigned int ssi, int direction); + +/*! + * This function controls the AC97 frame rate divider. + * + * @param module the module number + * @param frame_rate_divider the AC97 frame rate divider + */ +void ssi_ac97_frame_rate_divider(ssi_mod module, + unsigned char frame_rate_divider); + +/*! + * This function gets the AC97 command address register. + * + * @param module the module number + * @return This function returns the command address slot information. + */ +unsigned int ssi_ac97_get_command_address_register(ssi_mod module); + +/*! + * This function gets the AC97 command data register. + * + * @param module the module number + * @return This function returns the command data slot information. + */ +unsigned int ssi_ac97_get_command_data_register(ssi_mod module); + +/*! + * This function gets the AC97 tag register. + * + * @param module the module number + * @return This function returns the tag information. + */ +unsigned int ssi_ac97_get_tag_register(ssi_mod module); + +/*! + * This function controls the AC97 mode. + * + * @param module the module number + * @param state the AC97 mode state (enabled or disabled) + */ +void ssi_ac97_mode_enable(ssi_mod module, bool state); + +/*! + * This function controls the AC97 tag in FIFO behavior. + * + * @param module the module number + * @param state the tag in fifo behavior (Tag info stored in Rx FIFO 0 if TRUE, + * Tag info stored in SATAG register otherwise) + */ +void ssi_ac97_tag_in_fifo(ssi_mod module, bool state); + +/*! + * This function controls the AC97 read command. + * + * @param module the module number + * @param state the next AC97 command is a read command or not + */ +void ssi_ac97_read_command(ssi_mod module, bool state); + +/*! + * This function sets the AC97 command address register. + * + * @param module the module number + * @param address the command address slot information + */ +void ssi_ac97_set_command_address_register(ssi_mod module, + unsigned int address); + +/*! + * This function sets the AC97 command data register. + * + * @param module the module number + * @param data the command data slot information + */ +void ssi_ac97_set_command_data_register(ssi_mod module, unsigned int data); + +/*! + * This function sets the AC97 tag register. + * + * @param module the module number + * @param tag the tag information + */ +void ssi_ac97_set_tag_register(ssi_mod module, unsigned int tag); + +/*! + * This function controls the AC97 variable mode. + * + * @param module the module number + * @param state the AC97 variable mode state (enabled or disabled) + */ +void ssi_ac97_variable_mode(ssi_mod module, bool state); + +/*! + * This function controls the AC97 write command. + * + * @param module the module number + * @param state the next AC97 command is a write command or not + */ +void ssi_ac97_write_command(ssi_mod module, bool state); + +/*! + * This function controls the idle state of the transmit clock port during SSI internal gated mode. + * + * @param module the module number + * @param state the clock idle state + */ +void ssi_clock_idle_state(ssi_mod module, idle_state state); + +/*! + * This function turns off/on the ccm_ssi_clk to reduce power consumption. + * + * @param module the module number + * @param state the state for ccm_ssi_clk (true: turn off, else:turn on) + */ +void ssi_clock_off(ssi_mod module, bool state); + +/*! + * This function enables/disables the SSI module. + * + * @param module the module number + * @param state the state for SSI module + */ +void ssi_enable(ssi_mod module, bool state); + +/*! + * This function gets the data word in the Receive FIFO of the SSI module. + * + * @param module the module number + * @param fifo the Receive FIFO to read + * @return This function returns the read data. + */ +unsigned int ssi_get_data(ssi_mod module, fifo_nb fifo); + +/*! + * This function returns the status of the SSI module (SISR register) as a combination of status. + * + * @param module the module number + * @return This function returns the status of the SSI module. + */ +ssi_status_enable_mask ssi_get_status(ssi_mod module); + +/*! + * This function selects the I2S mode of the SSI module. + * + * @param module the module number + * @param mode the I2S mode + */ +void ssi_i2s_mode(ssi_mod module, mode_i2s mode); + +/*! + * This function disables the interrupts of the SSI module. + * + * @param module the module number + * @param mask the mask of the interrupts to disable + */ +void ssi_interrupt_disable(ssi_mod module, ssi_status_enable_mask mask); + +/*! + * This function enables the interrupts of the SSI module. + * + * @param module the module number + * @param mask the mask of the interrupts to enable + */ +void ssi_interrupt_enable(ssi_mod module, ssi_status_enable_mask mask); + +/*! + * This function enables/disables the network mode of the SSI module. + * + * @param module the module number + * @param state the network mode state + */ +void ssi_network_mode(ssi_mod module, bool state); + +/*! + * This function enables/disables the receive section of the SSI module. + * + * @param module the module number + * @param state the receive section state + */ +void ssi_receive_enable(ssi_mod module, bool state); + +/*! + * This function configures the SSI module to receive data word at bit position 0 or 23 in the Receive shift register. + * + * @param module the module number + * @param state the state to receive at bit 0 + */ +void ssi_rx_bit0(ssi_mod module, bool state); + +/*! + * This function controls the source of the clock signal used to clock the Receive shift register. + * + * @param module the module number + * @param direction the clock signal direction + */ +void ssi_rx_clock_direction(ssi_mod module, ssi_tx_rx_direction direction); + +/*! + * This function configures the divide-by-two divider of the SSI module for the receive section. + * + * @param module the module number + * @param state the divider state + */ +void ssi_rx_clock_divide_by_two(ssi_mod module, bool state); + +/*! + * This function controls which bit clock edge is used to clock in data. + * + * @param module the module number + * @param polarity the clock polarity + */ +void ssi_rx_clock_polarity(ssi_mod module, ssi_tx_rx_clock_polarity polarity); + +/*! + * This function configures a fixed divide-by-eight clock prescaler divider of the SSI module in series with the variable prescaler for the receive section. + * + * @param module the module number + * @param state the prescaler state + */ +void ssi_rx_clock_prescaler(ssi_mod module, bool state); + +/*! + * This function controls the early frame sync configuration. + * + * @param module the module number + * @param early the early frame sync configuration + */ +void ssi_rx_early_frame_sync(ssi_mod module, ssi_tx_rx_early_frame_sync early); + +/*! + * This function gets the number of data words in the Receive FIFO. + * + * @param module the module number + * @param fifo the fifo + * @return This function returns the number of words in the Rx FIFO. + */ +unsigned char ssi_rx_fifo_counter(ssi_mod module, fifo_nb fifo); + +/*! + * This function enables the Receive FIFO. + * + * @param module the module number + * @param fifo the fifo to enable + * @param enabled the state of the fifo, enabled or disabled + */ +void ssi_rx_fifo_enable(ssi_mod module, fifo_nb fifo, bool enabled); + +/*! + * This function controls the threshold at which the RFFx flag will be set. + * + * @param module the module number + * @param fifo the fifo to enable + * @param watermark the watermark + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_rx_fifo_full_watermark(ssi_mod module, + fifo_nb fifo, unsigned char watermark); + +/*! + * This function flushes the Receive FIFOs. + * + * @param module the module number + */ +void ssi_rx_flush_fifo(ssi_mod module); + +/*! + * This function controls the direction of the Frame Sync signal for the receive section. + * + * @param module the module number + * @param direction the Frame Sync signal direction + */ +void ssi_rx_frame_direction(ssi_mod module, ssi_tx_rx_direction direction); + +/*! + * This function configures the Receive frame rate divider for the receive section. + * + * @param module the module number + * @param ratio the divide ratio from 1 to 32 + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_rx_frame_rate(ssi_mod module, unsigned char ratio); + +/*! + * This function controls the Frame Sync active polarity for the receive section. + * + * @param module the module number + * @param active the Frame Sync active polarity + */ +void ssi_rx_frame_sync_active(ssi_mod module, + ssi_tx_rx_frame_sync_active active); + +/*! + * This function controls the Frame Sync length (one word or one bit long) for the receive section. + * + * @param module the module number + * @param length the Frame Sync length + */ +void ssi_rx_frame_sync_length(ssi_mod module, + ssi_tx_rx_frame_sync_length length); + +/*! + * This function configures the time slot(s) to mask for the receive section. + * + * @param module the module number + * @param mask the mask to indicate the time slot(s) masked + */ +void ssi_rx_mask_time_slot(ssi_mod module, unsigned int mask); + +/*! + * This function configures the Prescale divider for the receive section. + * + * @param module the module number + * @param divider the divide ratio from 1 to 256 + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_rx_prescaler_modulus(ssi_mod module, unsigned int divider); + +/*! + * This function controls whether the MSB or LSB will be received first in a sample. + * + * @param module the module number + * @param direction the shift direction + */ +void ssi_rx_shift_direction(ssi_mod module, + ssi_tx_rx_shift_direction direction); + +/*! + * This function configures the Receive word length. + * + * @param module the module number + * @param length the word length + */ +void ssi_rx_word_length(ssi_mod module, ssi_word_length length); + +/*! + * This function sets the data word in the Transmit FIFO of the SSI module. + * + * @param module the module number + * @param fifo the FIFO number + * @param data the data to load in the FIFO + */ +void ssi_set_data(ssi_mod module, fifo_nb fifo, unsigned int data); + +/*! + * This function controls the number of wait states between the core and SSI. + * + * @param module the module number + * @param wait the number of wait state(s) + */ +void ssi_set_wait_states(ssi_mod module, ssi_wait_states wait); + +/*! + * This function enables/disables the synchronous mode of the SSI module. + * + * @param module the module number + * @param state the synchronous mode state + */ +void ssi_synchronous_mode(ssi_mod module, bool state); + +/*! + * This function allows the SSI module to output the SYS_CLK at the SRCK port. + * + * @param module the module number + * @param state the system clock state + */ +void ssi_system_clock(ssi_mod module, bool state); + +/*! + * This function enables/disables the transmit section of the SSI module. + * + * @param module the module number + * @param state the transmit section state + */ +void ssi_transmit_enable(ssi_mod module, bool state); + +/*! + * This function allows the SSI module to operate in the two channel mode. + * + * @param module the module number + * @param state the two channel mode state + */ +void ssi_two_channel_mode(ssi_mod module, bool state); + +/*! + * This function configures the SSI module to transmit data word from bit position 0 or 23 in the Transmit shift register. + * + * @param module the module number + * @param state the transmit from bit 0 state + */ +void ssi_tx_bit0(ssi_mod module, bool state); + +/*! + * This function controls the direction of the clock signal used to clock the Transmit shift register. + * + * @param module the module number + * @param direction the clock signal direction + */ +void ssi_tx_clock_direction(ssi_mod module, ssi_tx_rx_direction direction); + +/*! + * This function configures the divide-by-two divider of the SSI module for the transmit section. + * + * @param module the module number + * @param state the divider state + */ +void ssi_tx_clock_divide_by_two(ssi_mod module, bool state); + +/*! + * This function controls which bit clock edge is used to clock out data. + * + * @param module the module number + * @param polarity the clock polarity + */ +void ssi_tx_clock_polarity(ssi_mod module, ssi_tx_rx_clock_polarity polarity); + +/*! + * This function configures a fixed divide-by-eight clock prescaler divider of the SSI module in series with the variable prescaler for the transmit section. + * + * @param module the module number + * @param state the prescaler state + */ +void ssi_tx_clock_prescaler(ssi_mod module, bool state); + +/*! + * This function controls the early frame sync configuration for the transmit section. + * + * @param module the module number + * @param early the early frame sync configuration + */ +void ssi_tx_early_frame_sync(ssi_mod module, ssi_tx_rx_early_frame_sync early); + +/*! + * This function gets the number of data words in the Transmit FIFO. + * + * @param module the module number + * @param fifo the fifo + * @return This function returns the number of words in the Tx FIFO. + */ +unsigned char ssi_tx_fifo_counter(ssi_mod module, fifo_nb fifo); + +/*! + * This function controls the threshold at which the TFEx flag will be set. + * + * @param module the module number + * @param fifo the fifo to enable + * @param watermark the watermark + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_tx_fifo_empty_watermark(ssi_mod module, fifo_nb fifo, + unsigned char watermark); + +/*! + * This function enables the Transmit FIFO. + * + * @param module the module number + * @param fifo the fifo to enable + * @param enable the state of the FIFO, enabled or disabled + */ +void ssi_tx_fifo_enable(ssi_mod module, fifo_nb fifo, bool enable); + +/*! + * This function flushes the Transmit FIFOs. + * + * @param module the module number + */ +void ssi_tx_flush_fifo(ssi_mod module); + +/*! + * This function controls the direction of the Frame Sync signal for the transmit section. + * + * @param module the module number + * @param direction the Frame Sync signal direction + */ +void ssi_tx_frame_direction(ssi_mod module, ssi_tx_rx_direction direction); + +/*! + * This function configures the Transmit frame rate divider. + * + * @param module the module number + * @param ratio the divide ratio from 1 to 32 + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_tx_frame_rate(ssi_mod module, unsigned char ratio); + +/*! + * This function controls the Frame Sync active polarity for the transmit section. + * + * @param module the module number + * @param active the Frame Sync active polarity + */ +void ssi_tx_frame_sync_active(ssi_mod module, + ssi_tx_rx_frame_sync_active active); + +/*! + * This function controls the Frame Sync length (one word or one bit long) for the transmit section. + * + * @param module the module number + * @param length the Frame Sync length + */ +void ssi_tx_frame_sync_length(ssi_mod module, + ssi_tx_rx_frame_sync_length length); + +/*! + * This function configures the time slot(s) to mask for the transmit section. + * + * @param module the module number + * @param mask the mask to indicate the time slot(s) masked + */ +void ssi_tx_mask_time_slot(ssi_mod module, unsigned int mask); + +/*! + * This function configures the Prescale divider for the transmit section. + * + * @param module the module number + * @param divider the divide ratio from 1 to 256 + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_tx_prescaler_modulus(ssi_mod module, unsigned int divider); + +/*! + * This function controls whether the MSB or LSB will be transmited first in a sample. + * + * @param module the module number + * @param direction the shift direction + */ +void ssi_tx_shift_direction(ssi_mod module, + ssi_tx_rx_shift_direction direction); + +/*! + * This function configures the Transmit word length. + * + * @param module the module number + * @param length the word length + */ +void ssi_tx_word_length(ssi_mod module, ssi_word_length length); + +#endif /* __MXC_SSI_H__ */ diff -urN linux-2.6.26/drivers/mxc/ssi/ssi_types.h linux-2.6.26-lab126/drivers/mxc/ssi/ssi_types.h --- linux-2.6.26/drivers/mxc/ssi/ssi_types.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/ssi/ssi_types.h 2010-08-10 04:15:36.000000000 -0400 @@ -0,0 +1,367 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + /*! + * @file ssi_types.h + * @brief This header file contains SSI types. + * + * @ingroup SSI + */ + +#ifndef __MXC_SSI_TYPES_H__ +#define __MXC_SSI_TYPES_H__ + +/*! + * This enumeration describes the FIFO number. + */ +typedef enum { + /*! + * FIFO 0 + */ + ssi_fifo_0 = 0, + /*! + * FIFO 1 + */ + ssi_fifo_1 = 1 +} fifo_nb; + +/*! + * This enumeration describes the clock idle state. + */ +typedef enum { + /*! + * Clock idle state is 1 + */ + clock_idle_state_1 = 0, + /*! + * Clock idle state is 0 + */ + clock_idle_state_0 = 1 +} idle_state; + +/*! + * This enumeration describes I2S mode. + */ +typedef enum { + /*! + * Normal mode + */ + i2s_normal = 0, + /*! + * Master mode + */ + i2s_master = 1, + /*! + * Slave mode + */ + i2s_slave = 2 +} mode_i2s; + +/*! + * This enumeration describes index for both SSI1 and SSI2 modules. + */ +typedef enum { + /*! + * SSI1 index + */ + SSI1 = 0, + /*! + * SSI2 index not present on MXC 91221 and MXC91311 + */ + SSI2 = 1 +} ssi_mod; + +/*! + * This enumeration describes the status/enable bits for interrupt source of the SSI module. + */ +typedef enum { + /*! + * SSI Transmit FIFO 0 empty bit + */ + ssi_tx_fifo_0_empty = 0x00000001, + /*! + * SSI Transmit FIFO 1 empty bit + */ + ssi_tx_fifo_1_empty = 0x00000002, + /*! + * SSI Receive FIFO 0 full bit + */ + ssi_rx_fifo_0_full = 0x00000004, + /*! + * SSI Receive FIFO 1 full bit + */ + ssi_rx_fifo_1_full = 0x00000008, + /*! + * SSI Receive Last Time Slot bit + */ + ssi_rls = 0x00000010, + /*! + * SSI Transmit Last Time Slot bit + */ + ssi_tls = 0x00000020, + /*! + * SSI Receive Frame Sync bit + */ + ssi_rfs = 0x00000040, + /*! + * SSI Transmit Frame Sync bit + */ + ssi_tfs = 0x00000080, + /*! + * SSI Transmitter underrun 0 bit + */ + ssi_transmitter_underrun_0 = 0x00000100, + /*! + * SSI Transmitter underrun 1 bit + */ + ssi_transmitter_underrun_1 = 0x00000200, + /*! + * SSI Receiver overrun 0 bit + */ + ssi_receiver_overrun_0 = 0x00000400, + /*! + * SSI Receiver overrun 1 bit + */ + ssi_receiver_overrun_1 = 0x00000800, + /*! + * SSI Transmit Data register empty 0 bit + */ + ssi_tx_data_reg_empty_0 = 0x00001000, + /*! + * SSI Transmit Data register empty 1 bit + */ + ssi_tx_data_reg_empty_1 = 0x00002000, + + /*! + * SSI Receive Data Ready 0 bit + */ + ssi_rx_data_ready_0 = 0x00004000, + /*! + * SSI Receive Data Ready 1 bit + */ + ssi_rx_data_ready_1 = 0x00008000, + /*! + * SSI Receive tag updated bit + */ + ssi_rx_tag_updated = 0x00010000, + /*! + * SSI Command data register updated bit + */ + ssi_cmd_data_reg_updated = 0x00020000, + /*! + * SSI Command address register updated bit + */ + ssi_cmd_address_reg_updated = 0x00040000, + /*! + * SSI Transmit interrupt enable bit + */ + ssi_tx_interrupt_enable = 0x00080000, + /*! + * SSI Transmit DMA enable bit + */ + ssi_tx_dma_interrupt_enable = 0x00100000, + /*! + * SSI Receive interrupt enable bit + */ + ssi_rx_interrupt_enable = 0x00200000, + /*! + * SSI Receive DMA enable bit + */ + ssi_rx_dma_interrupt_enable = 0x00400000, + /*! + * SSI Tx frame complete enable bit on MXC91221 & MXC91311 only + */ + ssi_tx_frame_complete = 0x00800000, + /*! + * SSI Rx frame complete on MXC91221 & MXC91311 only + */ + ssi_rx_frame_complete = 0x001000000 +} ssi_status_enable_mask; + +/*! + * This enumeration describes the clock edge to clock in or clock out data. + */ +typedef enum { + /*! + * Clock on rising edge + */ + ssi_clock_on_rising_edge = 0, + /*! + * Clock on falling edge + */ + ssi_clock_on_falling_edge = 1 +} ssi_tx_rx_clock_polarity; + +/*! + * This enumeration describes the clock direction. + */ +typedef enum { + /*! + * Clock is external + */ + ssi_tx_rx_externally = 0, + /*! + * Clock is generated internally + */ + ssi_tx_rx_internally = 1 +} ssi_tx_rx_direction; + +/*! + * This enumeration describes the early frame sync behavior. + */ +typedef enum { + /*! + * Frame Sync starts on the first data bit + */ + ssi_frame_sync_first_bit = 0, + /*! + * Frame Sync starts one bit before the first data bit + */ + ssi_frame_sync_one_bit_before = 1 +} ssi_tx_rx_early_frame_sync; + +/*! + * This enumeration describes the Frame Sync active value. + */ +typedef enum { + /*! + * Frame Sync is active when high + */ + ssi_frame_sync_active_high = 0, + /*! + * Frame Sync is active when low + */ + ssi_frame_sync_active_low = 1 +} ssi_tx_rx_frame_sync_active; + +/*! + * This enumeration describes the Frame Sync active length. + */ +typedef enum { + /*! + * Frame Sync is active when high + */ + ssi_frame_sync_one_word = 0, + /*! + * Frame Sync is active when low + */ + ssi_frame_sync_one_bit = 1 +} ssi_tx_rx_frame_sync_length; + +/*! + * This enumeration describes the Tx/Rx frame shift direction. + */ +typedef enum { + /*! + * MSB first + */ + ssi_msb_first = 0, + /*! + * LSB first + */ + ssi_lsb_first = 1 +} ssi_tx_rx_shift_direction; + +/*! + * This enumeration describes the wait state number. + */ +typedef enum { + /*! + * 0 wait state + */ + ssi_waitstates0 = 0x0, + /*! + * 1 wait state + */ + ssi_waitstates1 = 0x1, + /*! + * 2 wait states + */ + ssi_waitstates2 = 0x2, + /*! + * 3 wait states + */ + ssi_waitstates3 = 0x3 +} ssi_wait_states; + +/*! + * This enumeration describes the word length. + */ +typedef enum { + /*! + * 2 bits long + */ + ssi_2_bits = 0x0, + /*! + * 4 bits long + */ + ssi_4_bits = 0x1, + /*! + * 6 bits long + */ + ssi_6_bits = 0x2, + /*! + * 8 bits long + */ + ssi_8_bits = 0x3, + /*! + * 10 bits long + */ + ssi_10_bits = 0x4, + /*! + * 12 bits long + */ + ssi_12_bits = 0x5, + /*! + * 14 bits long + */ + ssi_14_bits = 0x6, + /*! + * 16 bits long + */ + ssi_16_bits = 0x7, + /*! + * 18 bits long + */ + ssi_18_bits = 0x8, + /*! + * 20 bits long + */ + ssi_20_bits = 0x9, + /*! + * 22 bits long + */ + ssi_22_bits = 0xA, + /*! + * 24 bits long + */ + ssi_24_bits = 0xB, + /*! + * 26 bits long + */ + ssi_26_bits = 0xC, + /*! + * 28 bits long + */ + ssi_28_bits = 0xD, + /*! + * 30 bits long + */ + ssi_30_bits = 0xE, + /*! + * 32 bits long + */ + ssi_32_bits = 0xF +} ssi_word_length; + +#endif /* __MXC_SSI_TYPES_H__ */ diff -urN linux-2.6.26/drivers/mxc/vpu/Kconfig linux-2.6.26-lab126/drivers/mxc/vpu/Kconfig --- linux-2.6.26/drivers/mxc/vpu/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/vpu/Kconfig 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,30 @@ +# +# Codec configuration +# + +menu "MXC VPU(Video Processing Unit) support" + +config MXC_VPU + tristate "Support for MXC VPU(Video Processing Unit)" + depends on (ARCH_MX3 || ARCH_MX27 || ARCH_MXC92323 || ARCH_MX37 || ARCH_MX51) + default y + ---help--- + The VPU codec device provides codec function for H.264/MPEG4/H.263, + as well as MPEG2/VC-1/DivX on some platforms. + +config MXC_VPU_IRAM + tristate "Use IRAM as temporary buffer for VPU to enhance performace" + depends on (ARCH_MX37 || ARCH_MX51) + default y + ---help--- + The VPU can use internal RAM as temporary buffer to save external + memroy bandwith, thus to enhance video performance. + +config MXC_VPU_DEBUG + bool "MXC VPU debugging" + depends on MXC_VPU != n + help + This is an option for the developers; most people should + say N here. This enables MXC VPU driver debugging. + +endmenu diff -urN linux-2.6.26/drivers/mxc/vpu/Makefile linux-2.6.26-lab126/drivers/mxc/vpu/Makefile --- linux-2.6.26/drivers/mxc/vpu/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/vpu/Makefile 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,10 @@ +# +# Makefile for the VPU drivers. +# + +obj-$(CONFIG_MXC_VPU) += vpu.o +vpu-objs := mxc_vpu.o mxc_vl2cc.o + +ifeq ($(CONFIG_MXC_VPU_DEBUG),y) +EXTRA_CFLAGS += -DDEBUG +endif diff -urN linux-2.6.26/drivers/mxc/vpu/mxc_vl2cc.c linux-2.6.26-lab126/drivers/mxc/vpu/mxc_vl2cc.c --- linux-2.6.26/drivers/mxc/vpu/mxc_vl2cc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/vpu/mxc_vl2cc.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,123 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_vl2cc.c + * + * @brief VL2CC initialization and flush operation implementation + * + * @ingroup VL2CC + */ + +#include +#include +#include +#include +#include +#include +#include + +#define VL2CC_CTRL_OFFSET (0x100) +#define VL2CC_AUXCTRL_OFFSET (0x104) +#define VL2CC_INVWAY_OFFSET (0x77C) +#define VL2CC_CLEANWAY_OFFSET (0x7BC) + +/*! VL2CC clock handle. */ +static struct clk *vl2cc_clk; +static u32 *vl2cc_base; + +/*! + * Initialization function of VL2CC. Remap the VL2CC base address. + * + * @return status 0 success. + */ +int vl2cc_init(u32 vl2cc_hw_base) +{ + vl2cc_base = ioremap(vl2cc_hw_base, SZ_8K - 1); + if (vl2cc_base == NULL) { + printk(KERN_INFO "vl2cc: Unable to ioremap\n"); + return -ENOMEM; + } + + vl2cc_clk = clk_get(NULL, "vl2cc_clk"); + if (IS_ERR(vl2cc_clk)) { + printk(KERN_INFO "vl2cc: Unable to get clock\n"); + iounmap(vl2cc_base); + return -EIO; + } + + printk(KERN_INFO "VL2CC initialized\n"); + return 0; +} + +/*! + * Enable VL2CC hardware + */ +void vl2cc_enable(void) +{ + volatile u32 reg; + + clk_enable(vl2cc_clk); + + /* Disable VL2CC */ + reg = __raw_readl(vl2cc_base + VL2CC_CTRL_OFFSET); + reg &= 0xFFFFFFFE; + __raw_writel(reg, vl2cc_base + VL2CC_CTRL_OFFSET); + + /* Set the latency for data RAM reads, data RAM writes, tag RAM and + * dirty RAM to 1 cycle - write 0x0 to AUX CTRL [11:0] and also + * configure the number of ways to 8 - write 8 to AUX CTRL [16:13] + */ + reg = __raw_readl(vl2cc_base + VL2CC_AUXCTRL_OFFSET); + reg &= 0xFFFE1000; /* Clear [16:13] too */ + reg |= (0x8 << 13); /* [16:13] = 8; */ + __raw_writel(reg, vl2cc_base + VL2CC_AUXCTRL_OFFSET); + + /* Invalidate the VL2CC ways - write 0xff to INV BY WAY and poll the + * register until its value is 0x0 + */ + __raw_writel(0xff, vl2cc_base + VL2CC_INVWAY_OFFSET); + while (__raw_readl(vl2cc_base + VL2CC_INVWAY_OFFSET) != 0x0) ; + + /* Enable VL2CC */ + reg = __raw_readl(vl2cc_base + VL2CC_CTRL_OFFSET); + reg |= 0x1; + __raw_writel(reg, vl2cc_base + VL2CC_CTRL_OFFSET); +} + +/*! + * Flush VL2CC + */ +void vl2cc_flush(void) +{ + __raw_writel(0xff, vl2cc_base + VL2CC_CLEANWAY_OFFSET); + while (__raw_readl(vl2cc_base + VL2CC_CLEANWAY_OFFSET) != 0x0) ; +} + +/*! + * Disable VL2CC + */ +void vl2cc_disable(void) +{ + __raw_writel(0, vl2cc_base + VL2CC_CTRL_OFFSET); + clk_disable(vl2cc_clk); +} + +/*! + * Cleanup VL2CC + */ +void vl2cc_cleanup(void) +{ + clk_put(vl2cc_clk); + iounmap(vl2cc_base); +} diff -urN linux-2.6.26/drivers/mxc/vpu/mxc_vpu.c linux-2.6.26-lab126/drivers/mxc/vpu/mxc_vpu.c --- linux-2.6.26/drivers/mxc/vpu/mxc_vpu.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/mxc/vpu/mxc_vpu.c 2010-08-10 04:15:37.000000000 -0400 @@ -0,0 +1,762 @@ +/* + * Copyright 2006-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_vpu.c + * + * @brief VPU system initialization and file operation implementation + * + * @ingroup VPU + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +struct vpu_priv { + struct fasync_struct *async_queue; +}; + +/* To track the allocated memory buffer */ +typedef struct memalloc_record { + struct list_head list; + struct vpu_mem_desc mem; +} memalloc_record; + +struct iram_setting { + u32 start; + u32 end; +}; + +static DEFINE_SPINLOCK(vpu_lock); +static LIST_HEAD(head); + +static int vpu_major = 0; +static struct class *vpu_class; +static struct vpu_priv vpu_data; +static u8 open_count = 0; +static struct clk *vpu_clk; +static struct vpu_mem_desc bitwork_mem = { 0 }; +static struct vpu_mem_desc pic_para_mem = { 0 }; +static struct vpu_mem_desc user_data_mem = { 0 }; + +/* IRAM setting */ +static struct iram_setting iram; + +/* implement the blocking ioctl */ +static int codec_done = 0; +static wait_queue_head_t vpu_queue; + +static u32 workctrl_regsave[6]; +static u32 rd_ptr_regsave[4]; +static u32 wr_ptr_regsave[4]; +static u32 dis_flag_regsave[4]; + +#define READ_REG(x) __raw_readl(IO_ADDRESS(VPU_BASE_ADDR+(x))) +#define WRITE_REG(val, x) \ + __raw_writel((val), IO_ADDRESS(VPU_BASE_ADDR+(x))) + +#define SAVE_WORK_REGS do { \ + int i; \ + for (i = 0; i < ARRAY_SIZE(workctrl_regsave)/2; i++) \ + workctrl_regsave[i] = READ_REG(BIT_WORK_CTRL_BUF_REG(i));\ +} while (0) +#define RESTORE_WORK_REGS do { \ + int i; \ + for (i = 0; i < ARRAY_SIZE(workctrl_regsave)/2; i++) \ + WRITE_REG(workctrl_regsave[i], BIT_WORK_CTRL_BUF_REG(i));\ +} while (0) +#define SAVE_CTRL_REGS do { \ + int i; \ + for (i = ARRAY_SIZE(workctrl_regsave)/2; \ + i < ARRAY_SIZE(workctrl_regsave); i++) \ + workctrl_regsave[i] = READ_REG(BIT_WORK_CTRL_BUF_REG(i));\ +} while (0) +#define RESTORE_CTRL_REGS do { \ + int i; \ + for (i = ARRAY_SIZE(workctrl_regsave)/2; \ + i < ARRAY_SIZE(workctrl_regsave); i++) \ + WRITE_REG(workctrl_regsave[i], BIT_WORK_CTRL_BUF_REG(i));\ +} while (0) +#define SAVE_RDWR_PTR_REGS do { \ + int i; \ + for (i = 0; i < ARRAY_SIZE(rd_ptr_regsave); i++) \ + rd_ptr_regsave[i] = READ_REG(BIT_RD_PTR_REG(i)); \ + for (i = 0; i < ARRAY_SIZE(wr_ptr_regsave); i++) \ + wr_ptr_regsave[i] = READ_REG(BIT_WR_PTR_REG(i)); \ +} while (0) +#define RESTORE_RDWR_PTR_REGS do { \ + int i; \ + for (i = 0; i < ARRAY_SIZE(rd_ptr_regsave); i++) \ + WRITE_REG(rd_ptr_regsave[i], BIT_RD_PTR_REG(i)); \ + for (i = 0; i < ARRAY_SIZE(wr_ptr_regsave); i++) \ + WRITE_REG(wr_ptr_regsave[i], BIT_WR_PTR_REG(i)); \ +} while (0) +#define SAVE_DIS_FLAG_REGS do { \ + int i; \ + for (i = 0; i < ARRAY_SIZE(dis_flag_regsave); i++) \ + dis_flag_regsave[i] = READ_REG(BIT_FRM_DIS_FLG_REG(i)); \ +} while (0) +#define RESTORE_DIS_FLAG_REGS do { \ + int i; \ + for (i = 0; i < ARRAY_SIZE(dis_flag_regsave); i++) \ + WRITE_REG(dis_flag_regsave[i], BIT_FRM_DIS_FLG_REG(i)); \ +} while (0) + +/*! + * Private function to alloc dma buffer + * @return status 0 success. + */ +static int vpu_alloc_dma_buffer(struct vpu_mem_desc *mem) +{ + mem->cpu_addr = (unsigned long) + dma_alloc_coherent(NULL, PAGE_ALIGN(mem->size), + (dma_addr_t *) (&mem->phy_addr), + GFP_DMA | GFP_KERNEL); + pr_debug("[ALLOC] mem alloc cpu_addr = 0x%x\n", mem->cpu_addr); + if ((void *)(mem->cpu_addr) == NULL) { + printk(KERN_ERR "Physical memory allocation error!\n"); + return -1; + } + return 0; +} + +/*! + * Private function to free dma buffer + */ +static void vpu_free_dma_buffer(struct vpu_mem_desc *mem) +{ + if (mem->cpu_addr != 0) { + dma_free_coherent(0, PAGE_ALIGN(mem->size), + (void *)mem->cpu_addr, mem->phy_addr); + } +} + +/*! + * Private function to free buffers + * @return status 0 success. + */ +static int vpu_free_buffers(void) +{ + struct memalloc_record *rec, *n; + struct vpu_mem_desc mem; + + list_for_each_entry_safe(rec, n, &head, list) { + mem = rec->mem; + if (mem.cpu_addr != 0) { + vpu_free_dma_buffer(&mem); + pr_debug("[FREE] freed paddr=0x%08X\n", mem.phy_addr); + /* delete from list */ + list_del(&rec->list); + kfree(rec); + } + } + + return 0; +} + +/*! + * @brief vpu interrupt handler + */ +static irqreturn_t vpu_irq_handler(int irq, void *dev_id) +{ + struct vpu_priv *dev = dev_id; + + READ_REG(BIT_INT_STATUS); + WRITE_REG(0x1, BIT_INT_CLEAR); + + if (dev->async_queue) + kill_fasync(&dev->async_queue, SIGIO, POLL_IN); + + /* + * Clock is gated on when dec/enc started, gate it off when + * interrupt is received. + */ + clk_disable(vpu_clk); + + codec_done = 1; + wake_up_interruptible(&vpu_queue); + + return IRQ_HANDLED; +} + +/*! + * @brief open function for vpu file operation + * + * @return 0 on success or negative error code on error + */ +static int vpu_open(struct inode *inode, struct file *filp) +{ + spin_lock(&vpu_lock); + if ((open_count++ == 0) && cpu_is_mx32()) + vl2cc_enable(); + filp->private_data = (void *)(&vpu_data); + spin_unlock(&vpu_lock); + return 0; +} + +/*! + * @brief IO ctrl function for vpu file operation + * @param cmd IO ctrl command + * @return 0 on success or negative error code on error + */ +static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd, + u_long arg) +{ + int ret = 0; + + switch (cmd) { + case VPU_IOC_PHYMEM_ALLOC: + { + struct memalloc_record *rec; + + rec = kzalloc(sizeof(*rec), GFP_KERNEL); + if (!rec) + return -ENOMEM; + + ret = copy_from_user(&(rec->mem), + (struct vpu_mem_desc *)arg, + sizeof(struct vpu_mem_desc)); + if (ret) { + kfree(rec); + return -EFAULT; + } + + pr_debug("[ALLOC] mem alloc size = 0x%x\n", + rec->mem.size); + + ret = vpu_alloc_dma_buffer(&(rec->mem)); + if (ret == -1) { + kfree(rec); + printk(KERN_ERR + "Physical memory allocation error!\n"); + break; + } + ret = copy_to_user((void __user *)arg, &(rec->mem), + sizeof(struct vpu_mem_desc)); + if (ret) { + kfree(rec); + ret = -EFAULT; + break; + } + + spin_lock(&vpu_lock); + list_add(&rec->list, &head); + spin_unlock(&vpu_lock); + + break; + } + case VPU_IOC_PHYMEM_FREE: + { + struct memalloc_record *rec, *n; + struct vpu_mem_desc vpu_mem; + + ret = copy_from_user(&vpu_mem, + (struct vpu_mem_desc *)arg, + sizeof(struct vpu_mem_desc)); + if (ret) + return -EACCES; + + pr_debug("[FREE] mem freed cpu_addr = 0x%x\n", + vpu_mem.cpu_addr); + if ((void *)vpu_mem.cpu_addr != NULL) { + vpu_free_dma_buffer(&vpu_mem); + } + + spin_lock(&vpu_lock); + list_for_each_entry_safe(rec, n, &head, list) { + if (rec->mem.cpu_addr == vpu_mem.cpu_addr) { + /* delete from list */ + list_del(&rec->list); + kfree(rec); + break; + } + } + spin_unlock(&vpu_lock); + + break; + } + case VPU_IOC_WAIT4INT: + { + u_long timeout = (u_long) arg; + if (!wait_event_interruptible_timeout + (vpu_queue, codec_done != 0, + msecs_to_jiffies(timeout))) { + printk(KERN_WARNING "VPU blocking: timeout.\n"); + ret = -ETIME; + } else if (signal_pending(current)) { + printk(KERN_WARNING + "VPU interrupt received.\n"); + ret = -ERESTARTSYS; + } + + codec_done = 0; + break; + } + case VPU_IOC_VL2CC_FLUSH: + if (cpu_is_mx32()) { + vl2cc_flush(); + } + break; + case VPU_IOC_IRAM_SETTING: + { + ret = copy_to_user((void __user *)arg, &iram, + sizeof(struct iram_setting)); + if (ret) + ret = -EFAULT; + + break; + } + case VPU_IOC_CLKGATE_SETTING: + { + u32 clkgate_en; + + if (get_user(clkgate_en, (u32 __user *) arg)) + return -EFAULT; + + if (clkgate_en) { + clk_enable(vpu_clk); + } else { + clk_disable(vpu_clk); + } + + break; + } + case VPU_IOC_GET_WORK_ADDR: + { + if (bitwork_mem.cpu_addr != 0) { + ret = + copy_to_user((void __user *)arg, + &bitwork_mem, + sizeof(struct vpu_mem_desc)); + break; + } else { + if (copy_from_user(&bitwork_mem, + (struct vpu_mem_desc *)arg, + sizeof(struct vpu_mem_desc))) + return -EFAULT; + + if (vpu_alloc_dma_buffer(&bitwork_mem) == -1) + ret = -EFAULT; + else if (copy_to_user((void __user *)arg, + &bitwork_mem, + sizeof(struct + vpu_mem_desc))) + ret = -EFAULT; + } + break; + } + case VPU_IOC_GET_PIC_PARA_ADDR: + { + if (pic_para_mem.cpu_addr != 0) { + ret = + copy_to_user((void __user *)arg, + &pic_para_mem, + sizeof(struct vpu_mem_desc)); + break; + } else { + if (copy_from_user(&pic_para_mem, + (struct vpu_mem_desc *)arg, + sizeof(struct vpu_mem_desc))) + return -EFAULT; + + if (vpu_alloc_dma_buffer(&pic_para_mem) == -1) + ret = -EFAULT; + else if (copy_to_user((void __user *)arg, + &pic_para_mem, + sizeof(struct + vpu_mem_desc))) + ret = -EFAULT; + } + break; + } + case VPU_IOC_GET_USER_DATA_ADDR: + { + if (user_data_mem.cpu_addr != 0) { + ret = + copy_to_user((void __user *)arg, + &user_data_mem, + sizeof(struct vpu_mem_desc)); + break; + } else { + if (copy_from_user(&user_data_mem, + (struct vpu_mem_desc *)arg, + sizeof(struct vpu_mem_desc))) + return -EFAULT; + + if (vpu_alloc_dma_buffer(&user_data_mem) == -1) + ret = -EFAULT; + else if (copy_to_user((void __user *)arg, + &user_data_mem, + sizeof(struct + vpu_mem_desc))) + ret = -EFAULT; + } + break; + } + case VPU_IOC_REG_DUMP: + break; + case VPU_IOC_PHYMEM_DUMP: + break; + default: + { + printk(KERN_ERR "No such IOCTL, cmd is %d\n", cmd); + break; + } + } + return ret; +} + +/*! + * @brief Release function for vpu file operation + * @return 0 on success or negative error code on error + */ +static int vpu_release(struct inode *inode, struct file *filp) +{ + spin_lock(&vpu_lock); + if (open_count > 0 && !(--open_count)) { + vpu_free_buffers(); + + if (cpu_is_mx32()) + vl2cc_disable(); + + } + spin_unlock(&vpu_lock); + + return 0; +} + +/*! + * @brief fasync function for vpu file operation + * @return 0 on success or negative error code on error + */ +static int vpu_fasync(int fd, struct file *filp, int mode) +{ + struct vpu_priv *dev = (struct vpu_priv *)filp->private_data; + return fasync_helper(fd, filp, mode, &dev->async_queue); +} + +/*! + * @brief memory map function of harware registers for vpu file operation + * @return 0 on success or negative error code on error + */ +static int vpu_map_hwregs(struct file *fp, struct vm_area_struct *vm) +{ + unsigned long pfn; + + vm->vm_flags |= VM_IO | VM_RESERVED; + vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot); + pfn = VPU_BASE_ADDR >> PAGE_SHIFT; + pr_debug("size=0x%x, page no.=0x%x\n", + (int)(vm->vm_end - vm->vm_start), (int)pfn); + return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end - vm->vm_start, + vm->vm_page_prot) ? -EAGAIN : 0; +} + +/*! + * @brief memory map function of memory for vpu file operation + * @return 0 on success or negative error code on error + */ +static int vpu_map_mem(struct file *fp, struct vm_area_struct *vm) +{ + int request_size; + request_size = vm->vm_end - vm->vm_start; + + pr_debug(" start=0x%x, pgoff=0x%x, size=0x%x\n", + (unsigned int)(vm->vm_start), (unsigned int)(vm->vm_pgoff), + request_size); + + vm->vm_flags |= VM_IO | VM_RESERVED; + vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot); + + return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, + request_size, vm->vm_page_prot) ? -EAGAIN : 0; + +} + +/*! + * @brief memory map interface for vpu file operation + * @return 0 on success or negative error code on error + */ +static int vpu_mmap(struct file *fp, struct vm_area_struct *vm) +{ + if (vm->vm_pgoff) + return vpu_map_mem(fp, vm); + else + return vpu_map_hwregs(fp, vm); +} + +struct file_operations vpu_fops = { + .owner = THIS_MODULE, + .open = vpu_open, + .ioctl = vpu_ioctl, + .release = vpu_release, + .fasync = vpu_fasync, + .mmap = vpu_mmap, +}; + +/*! + * This function is called by the driver framework to initialize the vpu device. + * @param dev The device structure for the vpu passed in by the framework. + * @return 0 on success or negative error code on error + */ +static int vpu_dev_probe(struct platform_device *pdev) +{ + int err = 0; + struct device *temp_class; + struct resource *res; + + if (cpu_is_mx32()) { + /* Obtain VL2CC base address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + printk(KERN_ERR "vpu: unable to get VL2CC base\n"); + return -ENOENT; + } + + err = vl2cc_init(res->start); + if (err != 0) + return err; + } + + if (cpu_is_mx37() || cpu_is_mx51()) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + printk(KERN_ERR "vpu: unable to get VPU IRAM base\n"); + return -ENOENT; + } + iram.start = res->start; + iram.end = res->end; + } + + vpu_major = register_chrdev(vpu_major, "mxc_vpu", &vpu_fops); + if (vpu_major < 0) { + printk(KERN_ERR "vpu: unable to get a major for VPU\n"); + err = -EBUSY; + goto error; + } + + vpu_class = class_create(THIS_MODULE, "mxc_vpu"); + if (IS_ERR(vpu_class)) { + err = PTR_ERR(vpu_class); + goto err_out_chrdev; + } + + temp_class = device_create(vpu_class, NULL, MKDEV(vpu_major, 0), + "mxc_vpu"); + if (IS_ERR(temp_class)) { + err = PTR_ERR(temp_class); + goto err_out_class; + } + + vpu_clk = clk_get(&pdev->dev, "vpu_clk"); + if (IS_ERR(vpu_clk)) { + err = -ENOENT; + goto err_out_class; + } + + err = request_irq(MXC_INT_VPU, vpu_irq_handler, 0, "VPU_CODEC_IRQ", + (void *)(&vpu_data)); + if (err) + goto err_out_class; + + printk(KERN_INFO "VPU initialized\n"); + goto out; + + err_out_class: + device_destroy(vpu_class, MKDEV(vpu_major, 0)); + class_destroy(vpu_class); + err_out_chrdev: + unregister_chrdev(vpu_major, "mxc_vpu"); + error: + if (cpu_is_mx32()) { + vl2cc_cleanup(); + } + out: + return err; +} + +#ifdef CONFIG_PM +static int vpu_suspend(struct platform_device *pdev, pm_message_t state) +{ + if (codec_done == 1) + return -EAGAIN; + + clk_enable(vpu_clk); + if (bitwork_mem.cpu_addr != 0) { + SAVE_WORK_REGS; + SAVE_CTRL_REGS; + SAVE_RDWR_PTR_REGS; + SAVE_DIS_FLAG_REGS; + + WRITE_REG(0x1, BIT_BUSY_FLAG); + WRITE_REG(VPU_SLEEP_REG_VALUE, BIT_RUN_COMMAND); + while (READ_REG(BIT_BUSY_FLAG)) ; + } + + clk_disable(vpu_clk); + + if (cpu_is_mx37() || cpu_is_mx51()) + mxc_pg_enable(pdev); + + return 0; +} + +static int vpu_resume(struct platform_device *pdev) +{ + if (cpu_is_mx37() || cpu_is_mx51()) + mxc_pg_disable(pdev); + + clk_enable(vpu_clk); + + if (bitwork_mem.cpu_addr != 0) { + u32 *p = (u32 *) bitwork_mem.cpu_addr; + u32 data; + u16 data_hi; + u16 data_lo; + int i; + + RESTORE_WORK_REGS; + + WRITE_REG(0x0, BIT_RESET_CTRL); + WRITE_REG(0x0, BIT_CODE_RUN); + + /* + * Re-load boot code, from the codebuffer in external RAM. + * Thankfully, we only need 4096 bytes, same for all platforms. + */ + if (cpu_is_mx51()) { + for (i = 0; i < 2048; i += 4) { + data = p[(i / 2) + 1]; + data_hi = (data >> 16) & 0xFFFF; + data_lo = data & 0xFFFF; + WRITE_REG((i << 16) | data_hi, BIT_CODE_DOWN); + WRITE_REG(((i + 1) << 16) | data_lo, + BIT_CODE_DOWN); + + data = p[i / 2]; + data_hi = (data >> 16) & 0xFFFF; + data_lo = data & 0xFFFF; + WRITE_REG(((i + 2) << 16) | data_hi, + BIT_CODE_DOWN); + WRITE_REG(((i + 3) << 16) | data_lo, + BIT_CODE_DOWN); + } + } else { + for (i = 0; i < 2048; i += 2) { + if (cpu_is_mx37()) + data = swab32(p[i / 2]); + else + data = p[i / 2]; + data_hi = (data >> 16) & 0xFFFF; + data_lo = data & 0xFFFF; + + WRITE_REG((i << 16) | data_hi, BIT_CODE_DOWN); + WRITE_REG(((i + 1) << 16) | data_lo, + BIT_CODE_DOWN); + } + } + + RESTORE_CTRL_REGS; + + WRITE_REG(BITVAL_PIC_RUN, BIT_INT_ENABLE); + + WRITE_REG(0x1, BIT_BUSY_FLAG); + WRITE_REG(0x1, BIT_CODE_RUN); + while (READ_REG(BIT_BUSY_FLAG)) ; + + RESTORE_RDWR_PTR_REGS; + RESTORE_DIS_FLAG_REGS; + + WRITE_REG(0x1, BIT_BUSY_FLAG); + WRITE_REG(VPU_WAKE_REG_VALUE, BIT_RUN_COMMAND); + while (READ_REG(BIT_BUSY_FLAG)) ; + } + + clk_disable(vpu_clk); + + return 0; +} +#else +#define vpu_suspend NULL +#define vpu_resume NULL +#endif /* !CONFIG_PM */ + +/*! Driver definition + * + */ +static struct platform_driver mxcvpu_driver = { + .driver = { + .name = "mxc_vpu", + }, + .probe = vpu_dev_probe, + .suspend = vpu_suspend, + .resume = vpu_resume, +}; + +static int __init vpu_init(void) +{ + int ret = platform_driver_register(&mxcvpu_driver); + + init_waitqueue_head(&vpu_queue); + + return ret; +} + +static void __exit vpu_exit(void) +{ + free_irq(MXC_INT_VPU, (void *)(&vpu_data)); + if (vpu_major > 0) { + device_destroy(vpu_class, MKDEV(vpu_major, 0)); + class_destroy(vpu_class); + unregister_chrdev(vpu_major, "mxc_vpu"); + vpu_major = 0; + } + + if (cpu_is_mx32()) { + vl2cc_cleanup(); + } + + vpu_free_dma_buffer(&bitwork_mem); + vpu_free_dma_buffer(&pic_para_mem); + vpu_free_dma_buffer(&user_data_mem); + + clk_put(vpu_clk); + + platform_driver_unregister(&mxcvpu_driver); + return; +} + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Linux VPU driver for Freescale i.MX27"); +MODULE_LICENSE("GPL"); + +module_init(vpu_init); +module_exit(vpu_exit); diff -urN linux-2.6.26/drivers/net/3c527.c linux-2.6.26-lab126/drivers/net/3c527.c --- linux-2.6.26/drivers/net/3c527.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/3c527.c 2010-08-10 04:17:02.000000000 -0400 @@ -182,7 +182,7 @@ u16 rx_ring_tail; /* index to rx de-queue end */ - struct semaphore cmd_mutex; /* Serialises issuing of execute commands */ + struct compat_semaphore cmd_mutex; /* Serialises issuing of execute commands */ struct completion execution_cmd; /* Card has completed an execute command */ struct completion xceiver_cmd; /* Card has completed a tx or rx command */ }; diff -urN linux-2.6.26/drivers/net/3c59x.c linux-2.6.26-lab126/drivers/net/3c59x.c --- linux-2.6.26/drivers/net/3c59x.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/3c59x.c 2010-08-10 04:17:02.000000000 -0400 @@ -791,9 +791,9 @@ { struct vortex_private *vp = netdev_priv(dev); unsigned long flags; - local_irq_save(flags); + local_irq_save_nort(flags); (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev); - local_irq_restore(flags); + local_irq_restore_nort(flags); } #endif @@ -1738,6 +1738,7 @@ int next_tick = 60*HZ; int ok = 0; int media_status, old_window; + unsigned long flags; if (vortex_debug > 2) { printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n", @@ -1745,7 +1746,7 @@ printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo); } - disable_irq_lockdep(dev->irq); + spin_lock_irqsave(&vp->lock, flags); old_window = ioread16(ioaddr + EL3_CMD) >> 13; EL3WINDOW(4); media_status = ioread16(ioaddr + Wn4_Media); @@ -1768,10 +1769,7 @@ case XCVR_MII: case XCVR_NWAY: { ok = 1; - /* Interrupts are already disabled */ - spin_lock(&vp->lock); vortex_check_media(dev, 0); - spin_unlock(&vp->lock); } break; default: /* Other media types handled by Tx timeouts. */ @@ -1827,7 +1825,7 @@ dev->name, media_tbl[dev->if_port].name); EL3WINDOW(old_window); - enable_irq_lockdep(dev->irq); + spin_unlock_irqrestore(&vp->lock, flags); mod_timer(&vp->timer, RUN_AT(next_tick)); if (vp->deferred) iowrite16(FakeIntr, ioaddr + EL3_CMD); @@ -1861,12 +1859,12 @@ * Block interrupts because vortex_interrupt does a bare spin_lock() */ unsigned long flags; - local_irq_save(flags); + local_irq_save_nort(flags); if (vp->full_bus_master_tx) boomerang_interrupt(dev->irq, dev); else vortex_interrupt(dev->irq, dev); - local_irq_restore(flags); + local_irq_restore_nort(flags); } } diff -urN linux-2.6.26/drivers/net/8139too.c linux-2.6.26-lab126/drivers/net/8139too.c --- linux-2.6.26/drivers/net/8139too.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/8139too.c 2010-08-10 04:17:02.000000000 -0400 @@ -2199,7 +2199,11 @@ */ static void rtl8139_poll_controller(struct net_device *dev) { - disable_irq(dev->irq); + /* + * use _nosync() variant - might be used by netconsole + * from atomic contexts: + */ + disable_irq_nosync(dev->irq); rtl8139_interrupt(dev->irq, dev); enable_irq(dev->irq); } diff -urN linux-2.6.26/drivers/net/Kconfig linux-2.6.26-lab126/drivers/net/Kconfig --- linux-2.6.26/drivers/net/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/Kconfig 2010-08-10 04:17:02.000000000 -0400 @@ -955,18 +955,30 @@ tristate "SMSC LAN911[5678] support" select CRC32 select MII - depends on ARCH_PXA || SH_MAGIC_PANEL_R2 + depends on ARCH_PXA || SH_MAGIC_PANEL_R2 || ARCH_MXC help This is a driver for SMSC's LAN911x series of Ethernet chipsets including the new LAN9115, LAN9116, LAN9117, and LAN9118. - Say Y if you want it compiled into the kernel, + Say Y if you want it compiled into the kernel, and read the Ethernet-HOWTO, available from . - This driver is also available as a module. The module will be - called smc911x. If you want to compile it as a module, say M + This driver is also available as a module. The module will be + called smc911x. If you want to compile it as a module, say M here and read +config SMSC911X + tristate "SMSC LAN911x/LAN921x families embedded ethernet support" + depends on NET_ETHERNET + select CRC32 + select MII + ---help--- + Say Y here if you want support for SMSC LAN911x and LAN921x families + of ethernet controllers. + To compile this driver as a module, choose M here and read + . The module + will be called smsc911x. + config NET_VENDOR_RACAL bool "Racal-Interlan (Micom) NI cards" depends on ISA @@ -1410,7 +1422,7 @@ config CS89x0 tristate "CS89x0 support" - depends on NET_PCI && (ISA || MACH_IXDP2351 || ARCH_IXDP2X01 || ARCH_PNX010X) + depends on (NET_PCI && (ISA || MACH_IXDP2351 || ARCH_IXDP2X01 || ARCH_PNX010X)) || ARCH_MXC ---help--- Support for CS89x0 chipset based Ethernet cards. If you have a network (Ethernet) card of this type, say Y and read the @@ -1445,9 +1457,9 @@ select MII ---help--- This driver supports Intel(R) PRO/100 family of adapters. - To verify that your adapter is supported, find the board ID number - on the adapter. Look for a label that has a barcode and a number - in the format 123456-001 (six digits hyphen three digits). + To verify that your adapter is supported, find the board ID number + on the adapter. Look for a label that has a barcode and a number + in the format 123456-001 (six digits hyphen three digits). Use the above information and the Adapter & Driver ID Guide at: @@ -1459,7 +1471,7 @@ - More specific information on configuring the driver is in + More specific information on configuring the driver is in . To compile this driver as a module, choose M here. The module @@ -1842,11 +1854,11 @@ the Motorola 68360 processor. config FEC - bool "FEC ethernet controller (of ColdFire CPUs)" - depends on M523x || M527x || M5272 || M528x || M520x + tristate "FEC ethernet controller" + depends on M523x || M527x || M5272 || M528x || M520x || ARCH_MX27 || ARCH_MX37 || ARCH_MX35 || ARCH_MX51 || ARCH_MX25 help Say Y here if you want to use the built-in 10/100 Fast ethernet - controller on some Motorola ColdFire processors. + controller on some Motorola/Freescale processors. config FEC2 bool "Second FEC ethernet controller (on some ColdFire CPUs)" @@ -1956,7 +1968,7 @@ depends on PCI ---help--- This driver supports Intel(R) PRO/1000 gigabit ethernet family of - adapters. For more information on how to identify your adapter, go + adapters. For more information on how to identify your adapter, go to the Adapter & Driver ID Guide at: @@ -1966,7 +1978,7 @@ - More specific information on configuring the driver is in + More specific information on configuring the driver is in . To compile this driver as a module, choose M here. The module @@ -2125,7 +2137,7 @@ ---help--- Say Y here for the r8169 driver to support the functions required by the kernel 802.1Q code. - + If in doubt, say Y. config SB1250_MAC @@ -2164,7 +2176,7 @@ and related Gigabit Ethernet adapters. It is a new smaller driver with better performance and more complete ethtool support. - It does not support the link failover and network management + It does not support the link failover and network management features that "portable" vendor supplied sk98lin driver does. This driver supports adapters based on the original Yukon chipset: @@ -2468,7 +2480,7 @@ - More specific information on configuring the driver is in + More specific information on configuring the driver is in . To compile this driver as a module, choose M here. The module @@ -2492,8 +2504,8 @@ tristate "S2IO 10Gbe XFrame NIC" depends on PCI ---help--- - This driver supports the 10Gbe XFrame NIC of S2IO. - More specific information on configuring the driver is in + This driver supports the 10Gbe XFrame NIC of S2IO. + More specific information on configuring the driver is in . config S2IO_NAPI @@ -2899,9 +2911,9 @@ Support for PPP over Ethernet. This driver requires the latest version of pppd from the CVS - repository at cvs.samba.org. Alternatively, see the + repository at cvs.samba.org. Alternatively, see the RoaringPenguin package () - which contains instruction on how to use this driver (under + which contains instruction on how to use this driver (under the heading "Kernel mode PPPoE"). config PPPOATM diff -urN linux-2.6.26/drivers/net/Makefile linux-2.6.26-lab126/drivers/net/Makefile --- linux-2.6.26/drivers/net/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/Makefile 2010-08-10 04:17:02.000000000 -0400 @@ -215,6 +215,7 @@ obj-$(CONFIG_MYRI10GE) += myri10ge/ obj-$(CONFIG_SMC91X) += smc91x.o obj-$(CONFIG_SMC911X) += smc911x.o +obj-$(CONFIG_SMSC911X) += smsc911x.o obj-$(CONFIG_BFIN_MAC) += bfin_mac.o obj-$(CONFIG_DM9000) += dm9000.o obj-$(CONFIG_FEC_8XX) += fec_8xx/ diff -urN linux-2.6.26/drivers/net/can/Kconfig linux-2.6.26-lab126/drivers/net/can/Kconfig --- linux-2.6.26/drivers/net/can/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/can/Kconfig 2010-08-10 04:16:27.000000000 -0400 @@ -22,4 +22,13 @@ a problem with CAN support and want to see more of what is going on. +config CAN_FLEXCAN + tristate "Freescale FlexCAN" + depends on CAN && ARCH_MX35 + default m + ---help--- + This select the support of Freescale CAN(FlexCAN). + This driver can also be built as a module. + If unsure, say N. + endmenu diff -urN linux-2.6.26/drivers/net/can/Makefile linux-2.6.26-lab126/drivers/net/can/Makefile --- linux-2.6.26/drivers/net/can/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/can/Makefile 2010-08-10 04:16:27.000000000 -0400 @@ -3,3 +3,4 @@ # obj-$(CONFIG_CAN_VCAN) += vcan.o +obj-$(CONFIG_CAN_FLEXCAN) += flexcan/ diff -urN linux-2.6.26/drivers/net/can/flexcan/Makefile linux-2.6.26-lab126/drivers/net/can/flexcan/Makefile --- linux-2.6.26/drivers/net/can/flexcan/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/can/flexcan/Makefile 2010-08-10 04:16:27.000000000 -0400 @@ -0,0 +1,3 @@ +obj-$(CONFIG_CAN_FLEXCAN) += flexcan.o + +flexcan-y := dev.o drv.o mbm.o diff -urN linux-2.6.26/drivers/net/can/flexcan/dev.c linux-2.6.26-lab126/drivers/net/can/flexcan/dev.c --- linux-2.6.26/drivers/net/can/flexcan/dev.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/can/flexcan/dev.c 2010-08-10 04:16:27.000000000 -0400 @@ -0,0 +1,619 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dev.c + * + * @brief Driver for Freescale CAN Controller FlexCAN. + * + * @ingroup can + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "flexcan.h" + +enum { + FLEXCAN_ATTR_STATE = 0, + FLEXCAN_ATTR_BITRATE, + FLEXCAN_ATTR_BR_PRESDIV, + FLEXCAN_ATTR_BR_RJW, + FLEXCAN_ATTR_BR_PROPSEG, + FLEXCAN_ATTR_BR_PSEG1, + FLEXCAN_ATTR_BR_PSEG2, + FLEXCAN_ATTR_BR_CLKSRC, + FLEXCAN_ATTR_MAXMB, + FLEXCAN_ATTR_XMIT_MAXMB, + FLEXCAN_ATTR_FIFO, + FLEXCAN_ATTR_WAKEUP, + FLEXCAN_ATTR_SRX_DIS, + FLEXCAN_ATTR_WAK_SRC, + FLEXCAN_ATTR_BCC, + FLEXCAN_ATTR_LOCAL_PRIORITY, + FLEXCAN_ATTR_ABORT, + FLEXCAN_ATTR_LOOPBACK, + FLEXCAN_ATTR_SMP, + FLEXCAN_ATTR_BOFF_REC, + FLEXCAN_ATTR_TSYN, + FLEXCAN_ATTR_LISTEN, + FLEXCAN_ATTR_EXTEND_MSG, + FLEXCAN_ATTR_STANDARD_MSG, +#ifdef CONFIG_CAN_DEBUG_DEVICES + FLEXCAN_ATTR_DUMP_REG, + FLEXCAN_ATTR_DUMP_XMIT_MB, + FLEXCAN_ATTR_DUMP_RX_MB, +#endif + FLEXCAN_ATTR_MAX +}; + +static ssize_t flexcan_show_attr(struct device *dev, + struct device_attribute *attr, char *buf); +static ssize_t flexcan_set_attr(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count); + +static struct device_attribute flexcan_dev_attr[FLEXCAN_ATTR_MAX] = { + [FLEXCAN_ATTR_STATE] = __ATTR(state, 0444, flexcan_show_attr, NULL), + [FLEXCAN_ATTR_BITRATE] = + __ATTR(bitrate, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_BR_PRESDIV] = + __ATTR(br_presdiv, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_BR_RJW] = + __ATTR(br_rjw, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_BR_PROPSEG] = + __ATTR(br_propseg, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_BR_PSEG1] = + __ATTR(br_pseg1, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_BR_PSEG2] = + __ATTR(br_pseg2, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_BR_CLKSRC] = + __ATTR(br_clksrc, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_MAXMB] = + __ATTR(maxmb, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_XMIT_MAXMB] = + __ATTR(xmit_maxmb, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_FIFO] = + __ATTR(fifo, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_WAKEUP] = + __ATTR(wakeup, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_SRX_DIS] = + __ATTR(srx_dis, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_WAK_SRC] = + __ATTR(wak_src, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_BCC] = + __ATTR(bcc, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_LOCAL_PRIORITY] = + __ATTR(local_priority, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_ABORT] = + __ATTR(abort, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_LOOPBACK] = + __ATTR(loopback, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_SMP] = + __ATTR(smp, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_BOFF_REC] = + __ATTR(boff_rec, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_TSYN] = + __ATTR(tsyn, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_LISTEN] = + __ATTR(listen, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_EXTEND_MSG] = + __ATTR(ext_msg, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_STANDARD_MSG] = + __ATTR(std_msg, 0644, flexcan_show_attr, flexcan_set_attr), +#ifdef CONFIG_CAN_DEBUG_DEVICES + [FLEXCAN_ATTR_DUMP_REG] = + __ATTR(dump_reg, 0444, flexcan_show_attr, NULL), + [FLEXCAN_ATTR_DUMP_XMIT_MB] = + __ATTR(dump_xmit_mb, 0444, flexcan_show_attr, NULL), + [FLEXCAN_ATTR_DUMP_RX_MB] = + __ATTR(dump_rx_mb, 0444, flexcan_show_attr, NULL), +#endif +}; + +static void flexcan_set_bitrate(struct flexcan_device *flexcan, int bitrate) +{ + /* TODO:: implement in future + * based on the bitrate to get the timing of + * presdiv, pseg1, pseg2, propseg + */ +} + +static void flexcan_update_bitrate(struct flexcan_device *flexcan) +{ + int rate, div; + + if (flexcan->br_clksrc) + rate = clk_get_rate(flexcan->clk); + else { + struct clk *clk; + clk = clk_get(NULL, "ckih"); + if (!clk) + return; + rate = clk_get_rate(clk); + clk_put(clk); + } + if (!rate) + return; + + div = (flexcan->br_presdiv + 1); + div *= + (flexcan->br_propseg + flexcan->br_pseg1 + flexcan->br_pseg2 + 4); + flexcan->bitrate = (rate + div - 1) / div; +} + +#ifdef CONFIG_CAN_DEBUG_DEVICES +static int flexcan_dump_reg(struct flexcan_device *flexcan, char *buf) +{ + int ret = 0; + unsigned int reg; + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR); + ret += sprintf(buf + ret, "MCR::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_CTRL); + ret += sprintf(buf + ret, "CTRL::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_RXGMASK); + ret += sprintf(buf + ret, "RXGMASK::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_RX14MASK); + ret += sprintf(buf + ret, "RX14MASK::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_RX15MASK); + ret += sprintf(buf + ret, "RX15MASK::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_ECR); + ret += sprintf(buf + ret, "ECR::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_ESR); + ret += sprintf(buf + ret, "ESR::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK2); + ret += sprintf(buf + ret, "IMASK2::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK1); + ret += sprintf(buf + ret, "IMASK1::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG2); + ret += sprintf(buf + ret, "IFLAG2::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG1); + ret += sprintf(buf + ret, "IFLAG1::0x%x\n", reg); + return ret; +} + +static int flexcan_dump_xmit_mb(struct flexcan_device *flexcan, char *buf) +{ + int ret = 0, i; + i = flexcan->xmit_maxmb + 1; + for (; i <= flexcan->maxmb; i++) + ret += + sprintf(buf + ret, + "mb[%d]::CS:0x%x ID:0x%x DATA[1~2]:0x%02x,0x%02x\n", + i, flexcan->hwmb[i].mb_cs.data, + flexcan->hwmb[i].mb_id, flexcan->hwmb[i].mb_data[1], + flexcan->hwmb[i].mb_data[2]); + return ret; +} + +static int flexcan_dump_rx_mb(struct flexcan_device *flexcan, char *buf) +{ + int ret = 0, i; + for (i = 0; i <= flexcan->xmit_maxmb; i++) + ret += + sprintf(buf + ret, + "mb[%d]::CS:0x%x ID:0x%x DATA[1~2]:0x%02x,0x%02x\n", + i, flexcan->hwmb[i].mb_cs.data, + flexcan->hwmb[i].mb_id, flexcan->hwmb[i].mb_data[1], + flexcan->hwmb[i].mb_data[2]); + return ret; +} +#endif + +static ssize_t flexcan_show_state(struct net_device *net, char *buf) +{ + int ret, esr; + struct flexcan_device *flexcan = netdev_priv(net); + ret = sprintf(buf, "%s::", netif_running(net) ? "Start" : "Stop"); + if (netif_carrier_ok(net)) { + esr = __raw_readl(flexcan->io_base + CAN_HW_REG_ESR); + switch ((esr & __ESR_FLT_CONF_MASK) >> __ESR_FLT_CONF_OFF) { + case 0: + ret += sprintf(buf + ret, "normal\n"); + break; + case 1: + ret += sprintf(buf + ret, "error passive\n"); + break; + default: + ret += sprintf(buf + ret, "bus off\n"); + } + } else + ret += sprintf(buf + ret, "bus off\n"); + return ret; +} + +static ssize_t flexcan_show_attr(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int attr_id; + struct net_device *net; + struct flexcan_device *flexcan; + + net = dev_get_drvdata(dev); + BUG_ON(!net); + flexcan = netdev_priv(net); + BUG_ON(!flexcan); + + attr_id = attr - flexcan_dev_attr; + switch (attr_id) { + case FLEXCAN_ATTR_STATE: + return flexcan_show_state(net, buf); + case FLEXCAN_ATTR_BITRATE: + return sprintf(buf, "%d\n", flexcan->bitrate); + case FLEXCAN_ATTR_BR_PRESDIV: + return sprintf(buf, "%d\n", flexcan->br_presdiv + 1); + case FLEXCAN_ATTR_BR_RJW: + return sprintf(buf, "%d\n", flexcan->br_rjw); + case FLEXCAN_ATTR_BR_PROPSEG: + return sprintf(buf, "%d\n", flexcan->br_propseg + 1); + case FLEXCAN_ATTR_BR_PSEG1: + return sprintf(buf, "%d\n", flexcan->br_pseg1 + 1); + case FLEXCAN_ATTR_BR_PSEG2: + return sprintf(buf, "%d\n", flexcan->br_pseg2 + 1); + case FLEXCAN_ATTR_BR_CLKSRC: + return sprintf(buf, "%s\n", flexcan->br_clksrc ? "bus" : "osc"); + case FLEXCAN_ATTR_MAXMB: + return sprintf(buf, "%d\n", flexcan->maxmb + 1); + case FLEXCAN_ATTR_XMIT_MAXMB: + return sprintf(buf, "%d\n", flexcan->xmit_maxmb + 1); + case FLEXCAN_ATTR_FIFO: + return sprintf(buf, "%d\n", flexcan->fifo); + case FLEXCAN_ATTR_WAKEUP: + return sprintf(buf, "%d\n", flexcan->wakeup); + case FLEXCAN_ATTR_SRX_DIS: + return sprintf(buf, "%d\n", flexcan->srx_dis); + case FLEXCAN_ATTR_WAK_SRC: + return sprintf(buf, "%d\n", flexcan->wak_src); + case FLEXCAN_ATTR_BCC: + return sprintf(buf, "%d\n", flexcan->bcc); + case FLEXCAN_ATTR_LOCAL_PRIORITY: + return sprintf(buf, "%d\n", flexcan->lprio); + case FLEXCAN_ATTR_ABORT: + return sprintf(buf, "%d\n", flexcan->abort); + case FLEXCAN_ATTR_LOOPBACK: + return sprintf(buf, "%d\n", flexcan->loopback); + case FLEXCAN_ATTR_SMP: + return sprintf(buf, "%d\n", flexcan->smp); + case FLEXCAN_ATTR_BOFF_REC: + return sprintf(buf, "%d\n", flexcan->boff_rec); + case FLEXCAN_ATTR_TSYN: + return sprintf(buf, "%d\n", flexcan->tsyn); + case FLEXCAN_ATTR_LISTEN: + return sprintf(buf, "%d\n", flexcan->listen); + case FLEXCAN_ATTR_EXTEND_MSG: + return sprintf(buf, "%d\n", flexcan->ext_msg); + case FLEXCAN_ATTR_STANDARD_MSG: + return sprintf(buf, "%d\n", flexcan->std_msg); +#ifdef CONFIG_CAN_DEBUG_DEVICES + case FLEXCAN_ATTR_DUMP_REG: + return flexcan_dump_reg(flexcan, buf); + case FLEXCAN_ATTR_DUMP_XMIT_MB: + return flexcan_dump_xmit_mb(flexcan, buf); + case FLEXCAN_ATTR_DUMP_RX_MB: + return flexcan_dump_rx_mb(flexcan, buf); +#endif + default: + return sprintf(buf, "%s:%p->%p\n", __func__, flexcan_dev_attr, + attr); + } +} + +static ssize_t flexcan_set_attr(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + int attr_id, tmp; + struct net_device *net; + struct flexcan_device *flexcan; + + net = dev_get_drvdata(dev); + BUG_ON(!net); + flexcan = netdev_priv(net); + BUG_ON(!flexcan); + + attr_id = attr - flexcan_dev_attr; + + if (mutex_lock_interruptible(&flexcan->mutex)) + return count; + + if (netif_running(net)) + goto set_finish; + + if (attr_id == FLEXCAN_ATTR_BR_CLKSRC) { + if (!strcasecmp(buf, "bus")) + flexcan->br_clksrc = 1; + else if (!strcasecmp(buf, "osc")) + flexcan->br_clksrc = 0; + goto set_finish; + } + + tmp = simple_strtoul(buf, NULL, 0); + switch (attr_id) { + case FLEXCAN_ATTR_BITRATE: + flexcan_set_bitrate(flexcan, tmp); + break; + case FLEXCAN_ATTR_BR_PRESDIV: + if ((tmp > 0) && (tmp <= FLEXCAN_MAX_PRESDIV)) { + flexcan->br_presdiv = tmp - 1; + flexcan_update_bitrate(flexcan); + } + break; + case FLEXCAN_ATTR_BR_RJW: + if ((tmp > 0) && (tmp <= FLEXCAN_MAX_RJW)) + flexcan->br_rjw = tmp - 1; + break; + case FLEXCAN_ATTR_BR_PROPSEG: + if ((tmp > 0) && (tmp <= FLEXCAN_MAX_PROPSEG)) { + flexcan->br_propseg = tmp - 1; + flexcan_update_bitrate(flexcan); + } + break; + case FLEXCAN_ATTR_BR_PSEG1: + if ((tmp > 0) && (tmp <= FLEXCAN_MAX_PSEG1)) { + flexcan->br_pseg1 = tmp - 1; + flexcan_update_bitrate(flexcan); + } + break; + case FLEXCAN_ATTR_BR_PSEG2: + if ((tmp > 0) && (tmp <= FLEXCAN_MAX_PSEG2)) { + flexcan->br_pseg2 = tmp - 1; + flexcan_update_bitrate(flexcan); + } + break; + case FLEXCAN_ATTR_MAXMB: + if ((tmp > 0) && (tmp <= FLEXCAN_MAX_MB)) { + if (flexcan->maxmb != (tmp - 1)) { + flexcan->maxmb = tmp - 1; + if (flexcan->xmit_maxmb < flexcan->maxmb) + flexcan->xmit_maxmb = flexcan->maxmb; + } + } + break; + case FLEXCAN_ATTR_XMIT_MAXMB: + if ((tmp > 0) && (tmp <= (flexcan->maxmb + 1))) { + if (flexcan->xmit_maxmb != (tmp - 1)) + flexcan->xmit_maxmb = tmp - 1; + } + break; + case FLEXCAN_ATTR_FIFO: + flexcan->fifo = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_WAKEUP: + flexcan->wakeup = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_SRX_DIS: + flexcan->srx_dis = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_WAK_SRC: + flexcan->wak_src = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_BCC: + flexcan->bcc = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_LOCAL_PRIORITY: + flexcan->lprio = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_ABORT: + flexcan->abort = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_LOOPBACK: + flexcan->loopback = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_SMP: + flexcan->smp = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_BOFF_REC: + flexcan->boff_rec = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_TSYN: + flexcan->tsyn = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_LISTEN: + flexcan->listen = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_EXTEND_MSG: + flexcan->ext_msg = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_STANDARD_MSG: + flexcan->std_msg = tmp ? 1 : 0; + break; + } + set_finish: + mutex_unlock(&flexcan->mutex); + return count; +} + +static void flexcan_device_default(struct flexcan_device *dev) +{ + dev->br_clksrc = 1; + dev->br_rjw = 2; + dev->br_presdiv = 6; + dev->br_propseg = 4; + dev->br_pseg1 = 4; + dev->br_pseg2 = 7; + + dev->bcc = 1; + dev->srx_dis = 1; + dev->smp = 1; + dev->boff_rec = 1; + + dev->maxmb = FLEXCAN_MAX_MB - 1; + dev->xmit_maxmb = (FLEXCAN_MAX_MB >> 1) - 1; + dev->xmit_mb = dev->maxmb - dev->xmit_maxmb; + + dev->ext_msg = 1; + dev->std_msg = 1; +} + +static int flexcan_device_attach(struct flexcan_device *flexcan) +{ + int ret; + struct resource *res; + struct platform_device *pdev = flexcan->dev; + struct flexcan_platform_data *plat_data = (pdev->dev).platform_data; + + res = platform_get_resource(flexcan->dev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + flexcan->io_base = ioremap(res->start, res->end - res->start + 1); + if (!flexcan->io_base) + return -ENOMEM; + + flexcan->irq = platform_get_irq(flexcan->dev, 0); + if (!flexcan->irq) { + ret = -ENODEV; + goto no_irq_err; + } + + ret = -EINVAL; + if (plat_data) { + if (plat_data->core_reg) { + flexcan->core_reg = regulator_get(&pdev->dev, + plat_data->core_reg); + if (!flexcan->core_reg) + goto plat_err; + } + + if (plat_data->io_reg) { + flexcan->io_reg = regulator_get(&pdev->dev, + plat_data->io_reg); + if (!flexcan->io_reg) + goto plat_err; + } + } + flexcan->clk = clk_get(&(flexcan->dev)->dev, "can_clk"); + flexcan->hwmb = (struct can_hw_mb *)(flexcan->io_base + CAN_MB_BASE); + flexcan->rx_mask = (unsigned int *)(flexcan->io_base + CAN_RXMASK_BASE); + + return 0; + plat_err: + if (flexcan->core_reg) { + regulator_put(flexcan->core_reg, &pdev->dev); + flexcan->core_reg = NULL; + } + no_irq_err: + if (flexcan->io_base) + iounmap(flexcan->io_base); + return ret; +} + +static void flexcan_device_detach(struct flexcan_device *flexcan) +{ + struct platform_device *pdev = flexcan->dev; + if (flexcan->clk) { + clk_put(flexcan->clk); + flexcan->clk = NULL; + } + + if (flexcan->io_reg) { + regulator_put(flexcan->io_reg, &pdev->dev); + flexcan->io_reg = NULL; + } + + if (flexcan->core_reg) { + regulator_put(flexcan->core_reg, &pdev->dev); + flexcan->core_reg = NULL; + } + + if (flexcan->io_base) + iounmap(flexcan->io_base); +} + +/*! + * @brief The function allocates can device. + * + * @param pdev the pointer of platform device. + * @param setup the initial function pointer of network device. + * + * @return none + */ +struct net_device *flexcan_device_alloc(struct platform_device *pdev, + void (*setup) (struct net_device *dev)) +{ + struct flexcan_device *flexcan; + struct net_device *net; + int i, num; + + net = alloc_netdev(sizeof(*flexcan), "can%d", setup); + if (net == NULL) { + printk(KERN_ERR "Allocate netdevice for FlexCAN fail!\n"); + return NULL; + } + flexcan = netdev_priv(net); + memset(flexcan, 0, sizeof(*flexcan)); + + mutex_init(&flexcan->mutex); + init_timer(&flexcan->timer); + + flexcan->dev = pdev; + if (flexcan_device_attach(flexcan)) { + printk(KERN_ERR "Attach FlexCAN fail!\n"); + free_netdev(net); + return NULL; + } + flexcan_device_default(flexcan); + flexcan_update_bitrate(flexcan); + + num = ARRAY_SIZE(flexcan_dev_attr); + + for (i = 0; i < num; i++) { + if (device_create_file(&pdev->dev, flexcan_dev_attr + i)) { + printk(KERN_ERR "Create attribute file fail!\n"); + break; + } + } + + if (i != num) { + for (; i >= 0; i--) + device_remove_file(&pdev->dev, flexcan_dev_attr + i); + free_netdev(net); + return NULL; + } + dev_set_drvdata(&pdev->dev, net); + return net; +} + +/*! + * @brief The function frees can device. + * + * @param pdev the pointer of platform device. + * + * @return none + */ +void flexcan_device_free(struct platform_device *pdev) +{ + struct net_device *net; + struct flexcan_device *flexcan; + int i, num; + net = (struct net_device *)dev_get_drvdata(&pdev->dev); + + unregister_netdev(net); + flexcan = netdev_priv(net); + del_timer(&flexcan->timer); + + num = ARRAY_SIZE(flexcan_dev_attr); + + for (i = 0; i < num; i++) + device_remove_file(&pdev->dev, flexcan_dev_attr + i); + + flexcan_device_detach(netdev_priv(net)); + free_netdev(net); +} diff -urN linux-2.6.26/drivers/net/can/flexcan/drv.c linux-2.6.26-lab126/drivers/net/can/flexcan/drv.c --- linux-2.6.26/drivers/net/can/flexcan/drv.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/can/flexcan/drv.c 2010-08-10 04:16:27.000000000 -0400 @@ -0,0 +1,624 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file drv.c + * + * @brief Driver for Freescale CAN Controller FlexCAN. + * + * @ingroup can + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include "flexcan.h" + +static void flexcan_hw_start(struct flexcan_device *flexcan) +{ + unsigned int reg; + if ((flexcan->maxmb + 1) > 32) { + __raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IMASK1); + reg = (1 << (flexcan->maxmb - 31)) - 1; + __raw_writel(reg, flexcan->io_base + CAN_HW_REG_IMASK2); + } else { + reg = (1 << (flexcan->maxmb + 1)) - 1; + __raw_writel(reg, flexcan->io_base + CAN_HW_REG_IMASK1); + __raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK2); + } + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR) & (~__MCR_HALT); + __raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR); +} + +static void flexcan_hw_stop(struct flexcan_device *flexcan) +{ + unsigned int reg; + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR); + __raw_writel(reg | __MCR_HALT, flexcan->io_base + CAN_HW_REG_MCR); +} + +static int flexcan_hw_reset(struct flexcan_device *flexcan) +{ + unsigned int reg; + int timeout = 100000; + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR); + __raw_writel(reg | __MCR_MDIS, flexcan->io_base + CAN_HW_REG_MCR); + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_CTRL); + if (flexcan->br_clksrc) + reg |= __CTRL_CLK_SRC; + else + reg &= ~__CTRL_CLK_SRC; + __raw_writel(reg, flexcan->io_base + CAN_HW_REG_CTRL); + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR) & (~__MCR_MDIS); + __raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR); + reg |= __MCR_SOFT_RST; + __raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR); + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR); + while (reg & __MCR_SOFT_RST) { + if (--timeout <= 0) { + printk(KERN_ERR "Flexcan software Reset Timeouted\n"); + return -1; + } + udelay(10); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR); + } + return 0; +} + +static inline void flexcan_mcr_setup(struct flexcan_device *flexcan) +{ + unsigned int reg; + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR); + reg &= ~(__MCR_MAX_MB_MASK | __MCR_WAK_MSK | __MCR_MAX_IDAM_MASK); + + if (flexcan->fifo) + reg |= __MCR_FEN; + else + reg &= ~__MCR_FEN; + + if (flexcan->wakeup) + reg |= __MCR_SLF_WAK | __MCR_WAK_MSK; + else + reg &= ~(__MCR_SLF_WAK | __MCR_WAK_MSK); + + if (flexcan->wak_src) + reg |= __MCR_WAK_SRC; + else + reg &= ~__MCR_WAK_SRC; + + if (flexcan->srx_dis) + reg |= __MCR_SRX_DIS; + else + reg &= ~__MCR_SRX_DIS; + + if (flexcan->bcc) + reg |= __MCR_BCC; + else + reg &= ~__MCR_BCC; + + if (flexcan->lprio) + reg |= __MCR_LPRIO_EN; + else + reg &= ~__MCR_LPRIO_EN; + + if (flexcan->abort) + reg |= __MCR_AEN; + else + reg &= ~__MCR_AEN; + + reg |= (flexcan->maxmb << __MCR_MAX_MB_OFFSET); + reg |= __MCR_DOZE | __MCR_MAX_IDAM_C; + __raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR); +} + +static inline void flexcan_ctrl_setup(struct flexcan_device *flexcan) +{ + unsigned int reg; + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_CTRL); + reg &= ~(__CTRL_PRESDIV_MASK | __CTRL_RJW_MASK | __CTRL_PSEG1_MASK | + __CTRL_PSEG2_MASK | __CTRL_PROPSEG_MASK); + + if (flexcan->loopback) + reg |= __CTRL_LPB; + else + reg &= ~__CTRL_LPB; + + if (flexcan->smp) + reg |= __CTRL_SMP; + else + reg &= ~__CTRL_SMP; + + if (flexcan->boff_rec) + reg |= __CTRL_BOFF_REC; + else + reg &= ~__CTRL_BOFF_REC; + + if (flexcan->tsyn) + reg |= __CTRL_TSYN; + else + reg &= ~__CTRL_TSYN; + + if (flexcan->listen) + reg |= __CTRL_LOM; + else + reg &= ~__CTRL_LOM; + + reg |= (flexcan->br_presdiv << __CTRL_PRESDIV_OFFSET) | + (flexcan->br_rjw << __CTRL_RJW_OFFSET) | + (flexcan->br_pseg1 << __CTRL_PSEG1_OFFSET) | + (flexcan->br_pseg2 << __CTRL_PSEG2_OFFSET) | + (flexcan->br_propseg << __CTRL_PROPSEG_OFFSET); + + reg &= ~__CTRL_LBUF; + + reg |= __CTRL_TWRN_MSK | __CTRL_RWRN_MSK | __CTRL_BOFF_MSK | + __CTRL_ERR_MSK; + + __raw_writel(reg, flexcan->io_base + CAN_HW_REG_CTRL); +} + +static int flexcan_hw_restart(struct net_device *dev) +{ + unsigned int reg; + struct flexcan_device *flexcan = netdev_priv(dev); + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR); + if (reg & __MCR_SOFT_RST) + return 1; + + flexcan_mcr_setup(flexcan); + + __raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK2); + __raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK1); + + __raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IFLAG2); + __raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IFLAG1); + + __raw_writel(0, flexcan->io_base + CAN_HW_REG_ECR); + + flexcan_mbm_init(flexcan); + netif_carrier_on(dev); + flexcan_hw_start(flexcan); + + if (netif_queue_stopped(dev)) + netif_start_queue(dev); + + return 0; +} + +static void flexcan_hw_watch(unsigned long data) +{ + unsigned int reg, ecr; + struct net_device *dev = (struct net_device *)data; + struct flexcan_device *flexcan = dev ? netdev_priv(dev) : NULL; + + BUG_ON(!flexcan); + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR); + if (reg & __MCR_MDIS) { + if (flexcan_hw_restart(dev)) + mod_timer(&flexcan->timer, HZ / 20); + return; + } + ecr = __raw_readl(flexcan->io_base + CAN_HW_REG_ECR); + if (flexcan->boff_rec) { + if (((reg & __ESR_FLT_CONF_MASK) >> __ESR_FLT_CONF_OFF) > 1) { + reg |= __MCR_SOFT_RST; + __raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR); + mod_timer(&flexcan->timer, HZ / 20); + return; + } + netif_carrier_on(dev); + } +} + +static void flexcan_hw_busoff(struct net_device *dev) +{ + struct flexcan_device *flexcan = netdev_priv(dev); + unsigned int reg; + + netif_carrier_off(dev); + + flexcan->timer.function = flexcan_hw_watch; + flexcan->timer.data = (unsigned long)dev; + + if (flexcan->boff_rec) { + mod_timer(&flexcan->timer, HZ / 10); + return; + } + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR); + __raw_writel(reg | __MCR_SOFT_RST, flexcan->io_base + CAN_HW_REG_MCR); + mod_timer(&flexcan->timer, HZ / 20); +} + +static int flexcan_hw_open(struct flexcan_device *flexcan) +{ + if (flexcan_hw_reset(flexcan)) + return -EFAULT; + + flexcan_mcr_setup(flexcan); + flexcan_ctrl_setup(flexcan); + + __raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK2); + __raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK1); + + __raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IFLAG2); + __raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IFLAG1); + + __raw_writel(0, flexcan->io_base + CAN_HW_REG_ECR); + return 0; +} + +static void flexcan_err_handler(struct net_device *dev) +{ + struct flexcan_device *flexcan = netdev_priv(dev); + struct sk_buff *skb; + struct can_frame *frame; + unsigned int esr, ecr; + + esr = __raw_readl(flexcan->io_base + CAN_HW_REG_ESR); + __raw_writel(esr & __ESR_INTERRUPTS, flexcan->io_base + CAN_HW_REG_ESR); + + if (esr & __ESR_WAK_INT) + return; + + skb = dev_alloc_skb(sizeof(struct can_frame)); + if (!skb) { + printk(KERN_ERR "%s: allocates skb fail in\n", __func__); + return; + } + frame = (struct can_frame *)skb_put(skb, sizeof(*frame)); + memset(frame, 0, sizeof(*frame)); + frame->can_id = CAN_ERR_FLAG | CAN_ERR_CRTL; + frame->can_dlc = CAN_ERR_DLC; + + if (esr & __ESR_TWRN_INT) + frame->data[1] |= CAN_ERR_CRTL_TX_WARNING; + + if (esr & __ESR_RWRN_INT) + frame->data[1] |= CAN_ERR_CRTL_RX_WARNING; + + if (esr & __ESR_BOFF_INT) + frame->can_id |= CAN_ERR_BUSOFF; + + if (esr & __ESR_ERR_INT) { + if (esr & __ESR_BIT1_ERR) + frame->data[2] |= CAN_ERR_PROT_BIT1; + + if (esr & __ESR_BIT0_ERR) + frame->data[2] |= CAN_ERR_PROT_BIT0; + + if (esr & __ESR_ACK_ERR) + frame->can_id |= CAN_ERR_ACK; + + /*TODO:// if (esr & __ESR_CRC_ERR) */ + + if (esr & __ESR_FRM_ERR) + frame->data[2] |= CAN_ERR_PROT_FORM; + + if (esr & __ESR_STF_ERR) + frame->data[2] |= CAN_ERR_PROT_STUFF; + + ecr = __raw_readl(flexcan->io_base + CAN_HW_REG_ECR); + switch ((esr & __ESR_FLT_CONF_MASK) >> __ESR_FLT_CONF_OFF) { + case 0: + if (__ECR_TX_ERR_COUNTER(ecr) >= __ECR_ACTIVE_THRESHOLD) + frame->data[1] |= CAN_ERR_CRTL_TX_WARNING; + if (__ECR_RX_ERR_COUNTER(ecr) >= __ECR_ACTIVE_THRESHOLD) + frame->data[1] |= CAN_ERR_CRTL_RX_WARNING; + break; + case 1: + if (__ECR_TX_ERR_COUNTER(ecr) >= + __ECR_PASSIVE_THRESHOLD) + frame->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; + + if (__ECR_RX_ERR_COUNTER(ecr) >= + __ECR_PASSIVE_THRESHOLD) + frame->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; + break; + default: + frame->can_id |= CAN_ERR_BUSOFF; + } + } + + if (frame->can_id & CAN_ERR_BUSOFF) + flexcan_hw_busoff(dev); + + skb->dev = dev; + skb->ip_summed = CHECKSUM_UNNECESSARY; + netif_receive_skb(skb); +} + +static irqreturn_t flexcan_irq_handler(int irq, void *data) +{ + struct net_device *dev = (struct net_device *)data; + struct flexcan_device *flexcan = dev ? netdev_priv(dev) : NULL; + unsigned int reg; + + BUG_ON(!flexcan); + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_ESR); + if (reg & __ESR_INTERRUPTS) { + flexcan_err_handler(dev); + return IRQ_HANDLED; + } + + flexcan_mbm_isr(dev); + return IRQ_HANDLED; +} + +static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct can_frame *frame = (struct can_frame *)skb->data; + struct flexcan_device *flexcan = netdev_priv(dev); + struct net_device_stats *stats = dev->get_stats(dev); + + BUG_ON(!flexcan); + + if (frame->can_dlc > 8) + return -EINVAL; + + if (!flexcan_mbm_xmit(flexcan, frame)) { + dev_kfree_skb(skb); + stats->tx_bytes += frame->can_dlc; + stats->tx_packets++; + dev->trans_start = jiffies; + return NETDEV_TX_OK; + } + netif_stop_queue(dev); + return NETDEV_TX_BUSY; +} + +static int flexcan_open(struct net_device *dev) +{ + struct flexcan_device *flexcan; + struct platform_device *pdev; + struct flexcan_platform_data *plat_data; + + flexcan = netdev_priv(dev); + BUG_ON(!flexcan); + + pdev = flexcan->dev; + plat_data = (pdev->dev).platform_data; + if (plat_data && plat_data->active) + plat_data->active(pdev->id); + + if (flexcan->clk) + if (clk_enable(flexcan->clk)) + goto clk_err; + + if (flexcan->core_reg) + if (regulator_enable(flexcan->core_reg)) + goto core_reg_err; + + if (flexcan->io_reg) + if (regulator_enable(flexcan->io_reg)) + goto io_reg_err; + + if (plat_data && plat_data->xcvr_enable) + plat_data->xcvr_enable(pdev->id, 1); + + if (request_irq(flexcan->irq, flexcan_irq_handler, IRQF_SAMPLE_RANDOM, + dev->name, dev)) + goto irq_err; + + if (flexcan_hw_open(flexcan)) + goto open_err; + + flexcan_mbm_init(flexcan); + netif_carrier_on(dev); + flexcan_hw_start(flexcan); + return 0; + open_err: + free_irq(flexcan->irq, dev); + irq_err: + if (plat_data && plat_data->xcvr_enable) + plat_data->xcvr_enable(pdev->id, 0); + + if (flexcan->io_reg) + regulator_disable(flexcan->io_reg); + io_reg_err: + if (flexcan->core_reg) + regulator_disable(flexcan->core_reg); + core_reg_err: + if (flexcan->clk) + clk_disable(flexcan->clk); + clk_err: + if (plat_data && plat_data->inactive) + plat_data->inactive(pdev->id); + return -ENODEV; +} + +static int flexcan_stop(struct net_device *dev) +{ + struct flexcan_device *flexcan; + struct platform_device *pdev; + struct flexcan_platform_data *plat_data; + + flexcan = netdev_priv(dev); + + BUG_ON(!flexcan); + + pdev = flexcan->dev; + plat_data = (pdev->dev).platform_data; + + flexcan_hw_stop(flexcan); + + free_irq(flexcan->irq, dev); + + if (plat_data && plat_data->xcvr_enable) + plat_data->xcvr_enable(pdev->id, 0); + + if (flexcan->io_reg) + regulator_disable(flexcan->io_reg); + if (flexcan->core_reg) + regulator_disable(flexcan->core_reg); + if (flexcan->clk) + clk_disable(flexcan->clk); + if (plat_data && plat_data->inactive) + plat_data->inactive(pdev->id); + return 0; +} + +static void flexcan_setup(struct net_device *dev) +{ + dev->type = ARPHRD_CAN; + dev->mtu = sizeof(struct can_frame); + dev->hard_header_len = 0; + dev->addr_len = 0; + dev->tx_queue_len = FLEXCAN_MAX_MB; + dev->flags = IFF_NOARP; + dev->features = NETIF_F_NO_CSUM; + + dev->open = flexcan_open; + dev->stop = flexcan_stop; + dev->hard_start_xmit = flexcan_start_xmit; +} + +static int flexcan_probe(struct platform_device *pdev) +{ + struct net_device *net; + net = flexcan_device_alloc(pdev, flexcan_setup); + if (!net) + return -ENOMEM; + + if (register_netdev(net)) { + flexcan_device_free(pdev); + return -ENODEV; + } + return 0; +} + +static int flexcan_remove(struct platform_device *pdev) +{ + flexcan_device_free(pdev); + return 0; +} + +static int flexcan_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct net_device *net; + struct flexcan_device *flexcan; + struct flexcan_platform_data *plat_data; + net = (struct net_device *)dev_get_drvdata(&pdev->dev); + flexcan = netdev_priv(net); + + BUG_ON(!flexcan); + + if (!(net->flags & IFF_UP)) + return 0; + if (flexcan->wakeup) + set_irq_wake(flexcan->irq, 1); + else { + plat_data = (pdev->dev).platform_data; + + if (plat_data && plat_data->xcvr_enable) + plat_data->xcvr_enable(pdev->id, 0); + + if (flexcan->io_reg) + regulator_disable(flexcan->io_reg); + if (flexcan->core_reg) + regulator_disable(flexcan->core_reg); + if (flexcan->clk) + clk_disable(flexcan->clk); + if (plat_data && plat_data->inactive) + plat_data->inactive(pdev->id); + } + return 0; +} + +static int flexcan_resume(struct platform_device *pdev) +{ + struct net_device *net; + struct flexcan_device *flexcan; + struct flexcan_platform_data *plat_data; + net = (struct net_device *)dev_get_drvdata(&pdev->dev); + flexcan = netdev_priv(net); + + BUG_ON(!flexcan); + + if (!(net->flags & IFF_UP)) + return 0; + + if (flexcan->wakeup) + set_irq_wake(flexcan->irq, 0); + else { + plat_data = (pdev->dev).platform_data; + if (plat_data && plat_data->active) + plat_data->active(pdev->id); + + if (flexcan->clk) { + if (clk_enable(flexcan->clk)) + printk(KERN_ERR "%s:enable clock fail\n", + __func__); + } + + if (flexcan->core_reg) { + if (regulator_enable(flexcan->core_reg)) + printk(KERN_ERR "%s:enable core voltage\n", + __func__); + } + if (flexcan->io_reg) { + if (regulator_enable(flexcan->io_reg)) + printk(KERN_ERR "%s:enable io voltage\n", + __func__); + } + + if (plat_data && plat_data->xcvr_enable) + plat_data->xcvr_enable(pdev->id, 1); + } + return 0; +} + +static struct platform_driver flexcan_driver = { + .driver = { + .name = FLEXCAN_DEVICE_NAME, + }, + .probe = flexcan_probe, + .remove = flexcan_remove, + .suspend = flexcan_suspend, + .resume = flexcan_resume, +}; + +static __init int flexcan_init(void) +{ + pr_info("Freescale FlexCAN Driver \n"); + return platform_driver_register(&flexcan_driver); +} + +static __exit void flexcan_exit(void) +{ + return platform_driver_unregister(&flexcan_driver); +} + +module_init(flexcan_init); +module_exit(flexcan_exit); + +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/net/can/flexcan/flexcan.h linux-2.6.26-lab126/drivers/net/can/flexcan/flexcan.h --- linux-2.6.26/drivers/net/can/flexcan/flexcan.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/can/flexcan/flexcan.h 2010-08-10 04:16:27.000000000 -0400 @@ -0,0 +1,223 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file flexcan.h + * + * @brief FlexCan definitions. + * + * @ingroup can + */ + +#ifndef __CAN_FLEXCAN_H__ +#define __CAN_FLEXCAN_H__ + +#include +#include +#include +#include +#include +#include +#include + +#define FLEXCAN_DEVICE_NAME "FlexCAN" + +struct can_mb_cs { + unsigned int time_stamp:16; + unsigned int length:4; + unsigned int rtr:1; + unsigned int ide:1; + unsigned int srr:1; + unsigned int nouse1:1; + unsigned int code:4; + unsigned int nouse2:4; +}; + +#define CAN_MB_RX_INACTIVE 0x0 +#define CAN_MB_RX_EMPTY 0x4 +#define CAN_MB_RX_FULL 0x2 +#define CAN_MB_RX_OVERRUN 0x6 +#define CAN_MB_RX_BUSY 0x1 + +#define CAN_MB_TX_INACTIVE 0x8 +#define CAN_MB_TX_ABORT 0x9 +#define CAN_MB_TX_ONCE 0xC +#define CAN_MB_TX_REMOTE 0xA + +struct can_hw_mb { + union { + struct can_mb_cs cs; + unsigned int data; + } mb_cs; + unsigned int mb_id; + unsigned char mb_data[8]; +}; + +#define CAN_HW_REG_MCR 0x00 +#define CAN_HW_REG_CTRL 0x04 +#define CAN_HW_REG_TIMER 0x08 +#define CAN_HW_REG_RXGMASK 0x10 +#define CAN_HW_REG_RX14MASK 0x14 +#define CAN_HW_REG_RX15MASK 0x18 +#define CAN_HW_REG_ECR 0x1C +#define CAN_HW_REG_ESR 0x20 +#define CAN_HW_REG_IMASK2 0x24 +#define CAN_HW_REG_IMASK1 0x28 +#define CAN_HW_REG_IFLAG2 0x2C +#define CAN_HW_REG_IFLAG1 0x30 + +#define CAN_MB_BASE 0x0080 +#define CAN_RXMASK_BASE 0x0880 +#define CAN_FIFO_BASE 0xE0 + +#define __MCR_MDIS (1 << 31) +#define __MCR_FRZ (1 << 30) +#define __MCR_FEN (1 << 29) +#define __MCR_HALT (1 << 28) +#define __MCR_NOTRDY (1 << 27) +#define __MCR_WAK_MSK (1 << 26) +#define __MCR_SOFT_RST (1 << 25) +#define __MCR_FRZ_ACK (1 << 24) +#define __MCR_SLF_WAK (1 << 22) +#define __MCR_WRN_EN (1 << 21) +#define __MCR_LPM_ACK (1 << 20) +#define __MCR_WAK_SRC (1 << 19) +#define __MCR_DOZE (1 << 18) +#define __MCR_SRX_DIS (1 << 17) +#define __MCR_BCC (1 << 16) +#define __MCR_LPRIO_EN (1 << 13) +#define __MCR_AEN (1 << 12) +#define __MCR_MAX_IDAM_OFFSET 8 +#define __MCR_MAX_IDAM_MASK (0x3 << __MCR_MAX_IDAM_OFFSET) +#define __MCR_MAX_IDAM_A (0x0 << __MCR_MAX_IDAM_OFFSET) +#define __MCR_MAX_IDAM_B (0x1 << __MCR_MAX_IDAM_OFFSET) +#define __MCR_MAX_IDAM_C (0x2 << __MCR_MAX_IDAM_OFFSET) +#define __MCR_MAX_IDAM_D (0x3 << __MCR_MAX_IDAM_OFFSET) +#define __MCR_MAX_MB_OFFSET 0 +#define __MCR_MAX_MB_MASK (0x3F) + +#define __CTRL_PRESDIV_OFFSET 24 +#define __CTRL_PRESDIV_MASK (0xFF << __CTRL_PRESDIV_OFFSET) +#define __CTRL_RJW_OFFSET 22 +#define __CTRL_RJW_MASK (0x3 << __CTRL_RJW_OFFSET) +#define __CTRL_PSEG1_OFFSET 19 +#define __CTRL_PSEG1_MASK (0x7 << __CTRL_PSEG1_OFFSET) +#define __CTRL_PSEG2_OFFSET 16 +#define __CTRL_PSEG2_MASK (0x7 << __CTRL_PSEG2_OFFSET) +#define __CTRL_BOFF_MSK (0x1 << 15) +#define __CTRL_ERR_MSK (0x1 << 14) +#define __CTRL_CLK_SRC (0x1 << 13) +#define __CTRL_LPB (0x1 << 12) +#define __CTRL_TWRN_MSK (0x1 << 11) +#define __CTRL_RWRN_MSK (0x1 << 10) +#define __CTRL_SMP (0x1 << 7) +#define __CTRL_BOFF_REC (0x1 << 6) +#define __CTRL_TSYN (0x1 << 5) +#define __CTRL_LBUF (0x1 << 4) +#define __CTRL_LOM (0x1 << 3) +#define __CTRL_PROPSEG_OFFSET 0 +#define __CTRL_PROPSEG_MASK (0x7) + +#define __ECR_TX_ERR_COUNTER(x) ((x) & 0xFF) +#define __ECR_RX_ERR_COUNTER(x) (((x) >> 8) & 0xFF) +#define __ECR_PASSIVE_THRESHOLD 128 +#define __ECR_ACTIVE_THRESHOLD 96 + +#define __ESR_TWRN_INT (0x1 << 17) +#define __ESR_RWRN_INT (0x1 << 16) +#define __ESR_BIT1_ERR (0x1 << 15) +#define __ESR_BIT0_ERR (0x1 << 14) +#define __ESR_ACK_ERR (0x1 << 13) +#define __ESR_CRC_ERR (0x1 << 12) +#define __ESR_FRM_ERR (0x1 << 11) +#define __ESR_STF_ERR (0x1 << 10) +#define __ESR_TX_WRN (0x1 << 9) +#define __ESR_RX_WRN (0x1 << 8) +#define __ESR_IDLE (0x1 << 7) +#define __ESR_TXRX (0x1 << 6) +#define __ESR_FLT_CONF_OFF 4 +#define __ESR_FLT_CONF_MASK (0x3 << __ESR_FLT_CONF_OFF) +#define __ESR_BOFF_INT (0x1 << 2) +#define __ESR_ERR_INT (0x1 << 1) +#define __ESR_WAK_INT (0x1) + +#define __ESR_INTERRUPTS (__ESR_WAK_INT | __ESR_ERR_INT | \ + __ESR_BOFF_INT | __ESR_TWRN_INT | \ + __ESR_RWRN_INT) + +#define __FIFO_OV_INT 0x0080 +#define __FIFO_WARN_INT 0x0040 +#define __FIFO_RDY_INT 0x0020 + +struct flexcan_device { + struct mutex mutex; + void *io_base; + struct can_hw_mb *hwmb; + unsigned int *rx_mask; + unsigned int xmit_mb; + unsigned int bitrate; + /* word 1 */ + unsigned int br_presdiv:8; + unsigned int br_rjw:2; + unsigned int br_propseg:3; + unsigned int br_pseg1:3; + unsigned int br_pseg2:3; + unsigned int maxmb:6; + unsigned int xmit_maxmb:6; + unsigned int wd1_resv:1; + + /* word 2 */ + unsigned int fifo:1; + unsigned int wakeup:1; + unsigned int srx_dis:1; + unsigned int wak_src:1; + unsigned int bcc:1; + unsigned int lprio:1; + unsigned int abort:1; + unsigned int br_clksrc:1; + unsigned int loopback:1; + unsigned int smp:1; + unsigned int boff_rec:1; + unsigned int tsyn:1; + unsigned int listen:1; + + unsigned int ext_msg:1; + unsigned int std_msg:1; + + struct timer_list timer; + struct platform_device *dev; + struct regulator *core_reg; + struct regulator *io_reg; + struct clk *clk; + int irq; +}; + +#define FLEXCAN_MAX_FIFO_MB 8 +#define FLEXCAN_MAX_MB 64 +#define FLEXCAN_MAX_PRESDIV 256 +#define FLEXCAN_MAX_RJW 4 +#define FLEXCAN_MAX_PSEG1 8 +#define FLEXCAN_MAX_PSEG2 8 +#define FLEXCAN_MAX_PROPSEG 8 +#define FLEXCAN_MAX_BITRATE 1000000 + +extern struct net_device *flexcan_device_alloc(struct platform_device *pdev, + void (*setup) (struct net_device + *dev)); +extern void flexcan_device_free(struct platform_device *pdev); + +extern void flexcan_mbm_init(struct flexcan_device *flexcan); +extern void flexcan_mbm_isr(struct net_device *dev); +extern int flexcan_mbm_xmit(struct flexcan_device *flexcan, + struct can_frame *frame); +#endif /* __CAN_FLEXCAN_H__ */ diff -urN linux-2.6.26/drivers/net/can/flexcan/mbm.c linux-2.6.26-lab126/drivers/net/can/flexcan/mbm.c --- linux-2.6.26/drivers/net/can/flexcan/mbm.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/can/flexcan/mbm.c 2010-08-10 04:16:27.000000000 -0400 @@ -0,0 +1,347 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mbm.c + * + * @brief Driver for Freescale CAN Controller FlexCAN. + * + * @ingroup can + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "flexcan.h" + +#define flexcan_swab32(x) \ + (((x) << 24) | ((x) >> 24) |\ + (((x) & (__u32)0x0000ff00UL) << 8) |\ + (((x) & (__u32)0x00ff0000UL) >> 8)) + +static inline void flexcan_memcpy(void *dst, void *src, int len) +{ + int i; + unsigned int *d = (unsigned int *)dst, *s = (unsigned int *)src; + len = (len + 3) >> 2; + for (i = 0; i < len; i++, s++, d++) + *d = flexcan_swab32(*s); +} + +static void flexcan_mb_bottom(struct net_device *dev, int index) +{ + struct flexcan_device *flexcan = netdev_priv(dev); + struct net_device_stats *stats = dev->get_stats(dev); + struct can_hw_mb *hwmb; + struct can_frame *frame; + struct sk_buff *skb; + unsigned int tmp; + + hwmb = flexcan->hwmb + index; + if (flexcan->fifo || (index >= (flexcan->maxmb - flexcan->xmit_maxmb))) { + if (hwmb->mb_cs.cs.code == CAN_MB_TX_ABORT) + hwmb->mb_cs.cs.code = CAN_MB_TX_INACTIVE; + + if (hwmb->mb_cs.cs.code & CAN_MB_TX_INACTIVE) { + if (netif_queue_stopped(dev)) + netif_start_queue(dev); + return; + } + } + skb = dev_alloc_skb(sizeof(struct can_frame)); + if (skb) { + frame = (struct can_frame *)skb_put(skb, sizeof(*frame)); + memset(frame, 0, sizeof(*frame)); + if (hwmb->mb_cs.cs.ide) + frame->can_id = + (hwmb->mb_id & CAN_EFF_MASK) | CAN_EFF_FLAG; + else + frame->can_id = (hwmb->mb_id >> 18) & CAN_SFF_MASK; + + if (hwmb->mb_cs.cs.rtr) + frame->can_id |= CAN_RTR_FLAG; + + frame->can_dlc = hwmb->mb_cs.cs.length; + + if (frame->can_dlc && frame->can_dlc) + flexcan_memcpy(frame->data, hwmb->mb_data, + frame->can_dlc); + + if (flexcan->fifo + || (index >= (flexcan->maxmb - flexcan->xmit_maxmb))) { + hwmb->mb_cs.cs.code = CAN_MB_TX_INACTIVE; + if (netif_queue_stopped(dev)) + netif_start_queue(dev); + } + + tmp = __raw_readl(flexcan->io_base + CAN_HW_REG_TIMER); + + dev->last_rx = jiffies; + stats->rx_packets++; + stats->rx_bytes += frame->can_dlc; + + skb->dev = dev; + skb->protocol = __constant_htons(ETH_P_CAN); + skb->ip_summed = CHECKSUM_UNNECESSARY; + netif_receive_skb(skb); + } else { + tmp = hwmb->mb_cs.data; + tmp = hwmb->mb_id; + tmp = hwmb->mb_data[0]; + if (flexcan->fifo + || (index >= (flexcan->maxmb - flexcan->xmit_maxmb))) { + + hwmb->mb_cs.cs.code = CAN_MB_TX_INACTIVE; + if (netif_queue_stopped(dev)) + netif_start_queue(dev); + } + tmp = __raw_readl(flexcan->io_base + CAN_HW_REG_TIMER); + stats->rx_dropped++; + } +} + +static void flexcan_fifo_isr(struct net_device *dev, unsigned int iflag1) +{ + struct flexcan_device *flexcan = dev ? netdev_priv(dev) : NULL; + struct net_device_stats *stats = dev->get_stats(dev); + struct sk_buff *skb; + struct can_hw_mb *hwmb = flexcan->hwmb; + struct can_frame *frame; + unsigned int tmp; + + if (iflag1 & __FIFO_RDY_INT) { + skb = dev_alloc_skb(sizeof(struct can_frame)); + if (skb) { + frame = + (struct can_frame *)skb_put(skb, sizeof(*frame)); + memset(frame, 0, sizeof(*frame)); + if (hwmb->mb_cs.cs.ide) + frame->can_id = + (hwmb->mb_id & CAN_EFF_MASK) | CAN_EFF_FLAG; + else + frame->can_id = + (hwmb->mb_id >> 18) & CAN_SFF_MASK; + + if (hwmb->mb_cs.cs.rtr) + frame->can_id |= CAN_RTR_FLAG; + + frame->can_dlc = hwmb->mb_cs.cs.length; + + if (frame->can_dlc && (frame->can_dlc <= 8)) + flexcan_memcpy(frame->data, hwmb->mb_data, + frame->can_dlc); + tmp = __raw_readl(flexcan->io_base + CAN_HW_REG_TIMER); + + dev->last_rx = jiffies; + + stats->rx_packets++; + stats->rx_bytes += frame->can_dlc; + + skb->dev = dev; + skb->protocol = __constant_htons(ETH_P_CAN); + skb->ip_summed = CHECKSUM_UNNECESSARY; + netif_receive_skb(skb); + } else { + tmp = hwmb->mb_cs.data; + tmp = hwmb->mb_id; + tmp = hwmb->mb_data[0]; + tmp = __raw_readl(flexcan->io_base + CAN_HW_REG_TIMER); + } + } + + if (iflag1 & (__FIFO_OV_INT | __FIFO_WARN_INT)) { + skb = dev_alloc_skb(sizeof(struct can_frame)); + if (skb) { + frame = + (struct can_frame *)skb_put(skb, sizeof(*frame)); + memset(frame, 0, sizeof(*frame)); + frame->can_id = CAN_ERR_FLAG | CAN_ERR_CRTL; + frame->can_dlc = CAN_ERR_DLC; + if (iflag1 & __FIFO_WARN_INT) + frame->data[1] |= + CAN_ERR_CRTL_TX_WARNING | + CAN_ERR_CRTL_RX_WARNING; + if (iflag1 & __FIFO_OV_INT) + frame->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; + + skb->dev = dev; + skb->protocol = __constant_htons(ETH_P_CAN); + skb->ip_summed = CHECKSUM_UNNECESSARY; + netif_receive_skb(skb); + } + } +} + +/*! + * @brief The function call by CAN ISR to handle mb events. + * + * @param dev the pointer of network device. + * + * @return none + */ +void flexcan_mbm_isr(struct net_device *dev) +{ + int i, iflag1, iflag2, maxmb; + struct flexcan_device *flexcan = dev ? netdev_priv(dev) : NULL; + + if (flexcan->maxmb > 31) { + maxmb = flexcan->maxmb + 1 - 32; + iflag1 = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG1) & + __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK1); + iflag2 = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG2) & + __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK2); + iflag2 &= (1 << maxmb) - 1; + maxmb = 32; + } else { + maxmb = flexcan->maxmb + 1; + iflag1 = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG1) & + __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK1); + iflag1 &= (1 << maxmb) - 1; + iflag2 = 0; + } + + __raw_writel(iflag1, flexcan->io_base + CAN_HW_REG_IFLAG1); + __raw_writel(iflag2, flexcan->io_base + CAN_HW_REG_IFLAG2); + + if (flexcan->fifo) { + flexcan_fifo_isr(dev, iflag1); + iflag1 &= 0xFFFFFF00; + } + for (i = 0; iflag1 && (i < maxmb); i++) { + if (iflag1 & (1 << i)) { + iflag1 &= ~(1 << i); + flexcan_mb_bottom(dev, i); + } + } + + for (i = maxmb; iflag2 && (i <= flexcan->maxmb); i++) { + if (iflag2 & (1 << (i - 32))) { + iflag2 &= ~(1 << (i - 32)); + flexcan_mb_bottom(dev, i); + } + } +} + +/*! + * @brief function to xmit message buffer + * + * @param flexcan the pointer of can hardware device. + * @param frame the pointer of can message frame. + * + * @return Returns 0 if xmit is success. otherwise returns non-zero. + */ +int flexcan_mbm_xmit(struct flexcan_device *flexcan, struct can_frame *frame) +{ + int i = flexcan->xmit_mb; + struct can_hw_mb *hwmb = flexcan->hwmb; + + do { + if (hwmb[i].mb_cs.cs.code == CAN_MB_TX_INACTIVE) + break; + if ((++i) > flexcan->maxmb) { + if (flexcan->fifo) + i = FLEXCAN_MAX_FIFO_MB; + else + i = flexcan->xmit_maxmb + 1; + } + if (i == flexcan->xmit_mb) + return -1; + } while (1); + + flexcan->xmit_mb = i + 1; + if (flexcan->xmit_mb > flexcan->maxmb) { + if (flexcan->fifo) + flexcan->xmit_mb = FLEXCAN_MAX_FIFO_MB; + else + flexcan->xmit_mb = flexcan->xmit_maxmb + 1; + } + + if (frame->can_id & CAN_RTR_FLAG) + hwmb[i].mb_cs.cs.rtr = 1; + else + hwmb[i].mb_cs.cs.rtr = 0; + + if (frame->can_id & CAN_EFF_FLAG) { + hwmb[i].mb_cs.cs.ide = 1; + hwmb[i].mb_cs.cs.srr = 1; + hwmb[i].mb_id = frame->can_id & CAN_EFF_MASK; + } else { + hwmb[i].mb_cs.cs.ide = 0; + hwmb[i].mb_id = (frame->can_id & CAN_SFF_MASK) << 18; + } + + hwmb[i].mb_cs.cs.length = frame->can_dlc; + flexcan_memcpy(hwmb[i].mb_data, frame->data, frame->can_dlc); + hwmb[i].mb_cs.cs.code = CAN_MB_TX_ONCE; + return 0; +} + +/*! + * @brief function to initial message buffer + * + * @param flexcan the pointer of can hardware device. + * + * @return none + */ +void flexcan_mbm_init(struct flexcan_device *flexcan) +{ + struct can_hw_mb *hwmb; + int rx_mb, i; + + /* Set global mask to receive all messages */ + __raw_writel(0, flexcan->io_base + CAN_HW_REG_RXGMASK); + __raw_writel(0, flexcan->io_base + CAN_HW_REG_RX14MASK); + __raw_writel(0, flexcan->io_base + CAN_HW_REG_RX15MASK); + + memset(flexcan->hwmb, 0, sizeof(*hwmb) * FLEXCAN_MAX_MB); + /* Set individual mask to receive all messages */ + memset(flexcan->rx_mask, 0, sizeof(unsigned int) * FLEXCAN_MAX_MB); + + if (flexcan->fifo) + rx_mb = FLEXCAN_MAX_FIFO_MB; + else + rx_mb = flexcan->maxmb - flexcan->xmit_maxmb; + + hwmb = flexcan->hwmb; + if (flexcan->fifo) { + unsigned long *id_table = flexcan->io_base + CAN_FIFO_BASE; + for (i = 0; i < rx_mb; i++) + id_table[i] = 0; + } else { + for (i = 0; i < rx_mb; i++) { + hwmb[i].mb_cs.cs.code = CAN_MB_RX_EMPTY; + /* + * IDE bit can not control by mask registers + * So set message buffer to receive extend + * or standard message. + */ + if (flexcan->ext_msg && flexcan->std_msg) + hwmb[i].mb_cs.cs.ide = i & 1; + else { + if (flexcan->ext_msg) + hwmb[i].mb_cs.cs.ide = 1; + } + } + } + + for (; i <= flexcan->maxmb; i++) + hwmb[i].mb_cs.cs.code = CAN_MB_TX_INACTIVE; + + flexcan->xmit_mb = rx_mb; +} diff -urN linux-2.6.26/drivers/net/cs89x0.c linux-2.6.26-lab126/drivers/net/cs89x0.c --- linux-2.6.26/drivers/net/cs89x0.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/cs89x0.c 2010-08-10 04:17:02.000000000 -0400 @@ -194,6 +194,17 @@ #define CIRRUS_DEFAULT_IRQ VH_INTC_INT_NUM_CASCADED_INTERRUPT_1 /* Event inputs bank 1 - ID 35/bit 3 */ static unsigned int netcard_portlist[] __used __initdata = {CIRRUS_DEFAULT_BASE, 0}; static unsigned int cs8900_irq_map[] = {CIRRUS_DEFAULT_IRQ, 0, 0, 0}; +#elif defined(CONFIG_ARCH_MXC) +/*! Null terminated portlist used to probe for the CS8900A device on ISA Bus + * Add 3 to reset the page window before probing (fixes eth probe when deployed + * using nand_boot) + */ +extern unsigned int netcard_portlist[2]; +/*! + * The CS8900A has 4 IRQ pins, which is software selectable, CS8900A interrupt + * pin 0 is used for interrupt generation. + */ +extern unsigned int cs8900_irq_map[4]; #else static unsigned int netcard_portlist[] __used __initdata = { 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0}; @@ -802,7 +813,7 @@ } else { i = lp->isa_config & INT_NO_MASK; if (lp->chip_type == CS8900) { -#if defined(CONFIG_MACH_IXDP2351) || defined(CONFIG_ARCH_IXDP2X01) || defined(CONFIG_ARCH_PNX010X) +#if defined(CONFIG_MACH_IXDP2351) || defined(CONFIG_ARCH_IXDP2X01) || defined(CONFIG_ARCH_PNX010X) || defined(CONFIG_ARCH_MXC) i = cs8900_irq_map[0]; #else /* Translate the IRQ using the IRQ mapping table. */ @@ -1029,6 +1040,7 @@ void __init reset_chip(struct net_device *dev) { +#if !defined(CONFIG_ARCH_MXC) #if !defined(CONFIG_MACH_IXDP2351) && !defined(CONFIG_ARCH_IXDP2X01) struct net_local *lp = netdev_priv(dev); int ioaddr = dev->base_addr; @@ -1057,6 +1069,7 @@ reset_start_time = jiffies; while( (readreg(dev, PP_SelfST) & INIT_DONE) == 0 && jiffies - reset_start_time < 2) ; +#endif /* !CONFIG_ARCH_MXC */ } @@ -1304,7 +1317,7 @@ else #endif { -#if !defined(CONFIG_MACH_IXDP2351) && !defined(CONFIG_ARCH_IXDP2X01) && !defined(CONFIG_ARCH_PNX010X) +#if !defined(CONFIG_MACH_IXDP2351) && !defined(CONFIG_ARCH_IXDP2X01) && !defined(CONFIG_ARCH_PNX010X) && !defined(CONFIG_ARCH_MXC) if (((1 << dev->irq) & lp->irq_map) == 0) { printk(KERN_ERR "%s: IRQ %d is not in our map of allowable IRQs, which is %x\n", dev->name, dev->irq, lp->irq_map); diff -urN linux-2.6.26/drivers/net/fec.c linux-2.6.26-lab126/drivers/net/fec.c --- linux-2.6.26/drivers/net/fec.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/fec.c 2010-08-10 04:17:02.000000000 -0400 @@ -2,12 +2,6 @@ * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) * - * This version of the driver is specific to the FADS implementation, - * since the board contains control registers external to the processor - * for the control of the LevelOne LXT970 transceiver. The MPC860T manual - * describes connections using the internal parallel port I/O, which - * is basically all of Port D. - * * Right now, I am very wasteful with the buffers. I allocate memory * pages and then divide them into 2K frame buffers. This way I know I * have buffers large enough to hold one frame within one buffer descriptor. @@ -24,6 +18,9 @@ * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) * Copyright (c) 2004-2006 Macq Electronique SA. */ +/* + * Copyright 2006-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ #include #include @@ -42,12 +39,14 @@ #include #include #include +#include #include #include #include #include #include +#include #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \ defined(CONFIG_M5272) || defined(CONFIG_M528x) || \ @@ -55,19 +54,29 @@ #include #include #include "fec.h" +#define FEC_ALIGNMENT (0x03) /*FEC needs 4bytes alignment*/ +#elif defined(CONFIG_ARCH_MXC) +#include +#include +#include "fec.h" +#define FEC_ALIGNMENT (0x0F) /*FEC needs 128bits(32bytes) alignment*/ #else #include #include #include "commproc.h" +#define FEC_ALIGNMENT (0x03) /*FEC needs 4bytes alignment */ #endif +#define FEC_ADDR_ALIGNMENT(x) ((unsigned char *)(((unsigned long )(x) + (FEC_ALIGNMENT)) & (~FEC_ALIGNMENT))) + #if defined(CONFIG_FEC2) #define FEC_MAX_PORTS 2 #else #define FEC_MAX_PORTS 1 #endif -#if defined(CONFIG_FADS) || defined(CONFIG_RPXCLASSIC) || defined(CONFIG_M5272) +#if defined(CONFIG_FADS) || defined(CONFIG_RPXCLASSIC) \ +|| defined(CONFIG_M5272) || defined(CONFIG_ARCH_MXC) #define HAVE_mii_link_interrupt #endif @@ -86,6 +95,8 @@ (MCF_MBAR+0x30000), #elif defined(CONFIG_M532x) (MCF_MBAR+0xfc030000), +#elif defined(CONFIG_ARCH_MXC) + (IO_ADDRESS(FEC_BASE_ADDR)), #else &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec), #endif @@ -163,6 +174,12 @@ #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ +#ifndef CONFIG_ARCH_MXC +#define FEC_ENET_MASK ((uint)0xffc00000) +#else +#define FEC_ENET_MASK ((uint)0xfff80000) +#endif + /* The FEC stores dest/src/type, data, and checksum for receive packets. */ #define PKT_MAXBUF_SIZE 1518 @@ -176,7 +193,7 @@ * account when setting it. */ #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ - defined(CONFIG_M520x) || defined(CONFIG_M532x) + defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC) #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) #else #define OPT_FRAME_SIZE 0 @@ -199,11 +216,13 @@ /* The saved address of a sent-in-place packet/buffer, for skfree(). */ unsigned char *tx_bounce[TX_RING_SIZE]; struct sk_buff* tx_skbuff[TX_RING_SIZE]; + struct sk_buff* rx_skbuff[RX_RING_SIZE]; ushort skb_cur; ushort skb_dirty; /* CPM dual port RAM relative addresses. */ + void * cbd_mem_base; /* save the virtual base address of rx&tx buffer descripter */ cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */ cbd_t *tx_bd_base; cbd_t *cur_rx, *cur_tx; /* The next free ring entry */ @@ -220,6 +239,7 @@ uint phy_speed; phy_info_t const *phy; struct work_struct phy_task; + struct net_device *net; uint sequence_done; uint mii_phy_task_queued; @@ -231,6 +251,8 @@ int link; int old_link; int full_duplex; + + struct clk *clk; }; static int fec_enet_open(struct net_device *dev); @@ -245,6 +267,17 @@ static void fec_stop(struct net_device *dev); static void fec_set_mac_address(struct net_device *dev); +static void __inline__ fec_dcache_inv_range(void * start, void * end); +static void __inline__ fec_dcache_flush_range(void * start, void * end); + +/* + * fec_copy_threshold controls the copy when recieving ethernet frame. + * If ethernet header aligns 4bytes, the ip header and upper header will not aligns 4bytes. + * The resean is ethernet header is 14bytes. + * And the max size of tcp & ip header is 128bytes. Normally it is 40bytes. + * So I set the default value between 128 to 256. + */ +static int fec_copy_threshold = 192; /* MII processing. We keep this as simple as possible. Requests are * placed on the list (if there is room). When the request is finished @@ -356,10 +389,10 @@ * 4-byte boundaries. Use bounce buffers to copy data * and get it aligned. Ugh. */ - if (bdp->cbd_bufaddr & 0x3) { + if ((bdp->cbd_bufaddr) & FEC_ALIGNMENT) { unsigned int index; index = bdp - fep->tx_bd_base; - memcpy(fep->tx_bounce[index], (void *) bdp->cbd_bufaddr, bdp->cbd_datlen); + memcpy(fep->tx_bounce[index], (void *) skb->data, skb->len); bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]); } @@ -373,8 +406,8 @@ /* Push the data cache so the CPM does not get stale memory * data. */ - flush_dcache_range((unsigned long)skb->data, - (unsigned long)skb->data + skb->len); + fec_dcache_flush_range(__va(bdp->cbd_bufaddr), __va(bdp->cbd_bufaddr) + + bdp->cbd_datlen); /* Send it on its way. Tell FEC it's ready, interrupt when done, * it's the last BD of the frame, and to put the CRC on the end. @@ -387,7 +420,7 @@ dev->trans_start = jiffies; /* Trigger transmission start */ - fecp->fec_x_des_active = 0; + fecp->fec_x_des_active = 0x01000000; /* If this was the last BD in the ring, start at the beginning again. */ @@ -474,7 +507,7 @@ /* Handle receive event in its own function. */ - if (int_events & FEC_ENET_RXF) { + if (int_events & (FEC_ENET_RXF | FEC_ENET_RXB)) { ret = IRQ_HANDLED; fec_enet_rx(dev); } @@ -483,7 +516,7 @@ descriptors. FEC handles all errors, we just discover them as part of the transmit process. */ - if (int_events & FEC_ENET_TXF) { + if (int_events & (FEC_ENET_TXF | FEC_ENET_TXB)) { ret = IRQ_HANDLED; fec_enet_tx(dev); } @@ -508,7 +541,7 @@ struct sk_buff *skb; fep = netdev_priv(dev); - spin_lock_irq(&fep->hw_lock); + spin_lock(&fep->hw_lock); bdp = fep->dirty_tx; while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { @@ -567,7 +600,7 @@ } } fep->dirty_tx = (cbd_t *)bdp; - spin_unlock_irq(&fep->hw_lock); + spin_unlock(&fep->hw_lock); } @@ -586,6 +619,7 @@ struct sk_buff *skb; ushort pkt_len; __u8 *data; + int rx_index ; #ifdef CONFIG_M532x flush_cache_all(); @@ -594,7 +628,7 @@ fep = netdev_priv(dev); fecp = (volatile fec_t*)dev->base_addr; - spin_lock_irq(&fep->hw_lock); + spin_lock(&fep->hw_lock); /* First, grab all of the stats for the incoming packet. * These get messed up if we get called due to a busy condition. @@ -602,7 +636,7 @@ bdp = fep->cur_rx; while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { - + rx_index = bdp - fep->rx_bd_base; #ifndef final_version /* Since we have allocated space to hold a complete frame, * the last indicator should be set. @@ -646,20 +680,36 @@ pkt_len = bdp->cbd_datlen; dev->stats.rx_bytes += pkt_len; data = (__u8*)__va(bdp->cbd_bufaddr); + fec_dcache_inv_range(data, data+pkt_len -4); /* This does 16 byte alignment, exactly what we need. * The packet length includes FCS, but we don't want to * include that when passing upstream as it messes up * bridging applications. */ - skb = dev_alloc_skb(pkt_len-4); + if ((pkt_len - 4) < fec_copy_threshold) { + skb = dev_alloc_skb(pkt_len); + } else { + skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE); + } if (skb == NULL) { printk("%s: Memory squeeze, dropping packet.\n", dev->name); dev->stats.rx_dropped++; } else { - skb_put(skb,pkt_len-4); /* Make room */ + if ((pkt_len - 4) < fec_copy_threshold) { + skb_reserve(skb, 2); /*skip 2bytes, so ipheader is align 4bytes*/ + skb_put(skb,pkt_len-4); /* Make room */ skb_copy_to_linear_data(skb, data, pkt_len-4); + } else { + struct sk_buff * pskb = fep->rx_skbuff[rx_index]; + + fep->rx_skbuff[rx_index] = skb; + skb->data = FEC_ADDR_ALIGNMENT(skb->data); + bdp->cbd_bufaddr = __pa(skb->data); + skb_put(pskb,pkt_len-4); /* Make room */ + skb = pskb; + } skb->protocol=eth_type_trans(skb,dev); netif_rx(skb); } @@ -686,7 +736,7 @@ * incoming frames. On a heavily loaded network, we should be * able to keep up at the expense of system resources. */ - fecp->fec_r_des_active = 0; + fecp->fec_r_des_active = 0x01000000; #endif } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */ fep->cur_rx = (cbd_t *)bdp; @@ -702,7 +752,7 @@ fecp->fec_r_des_active = 0; #endif - spin_unlock_irq(&fep->hw_lock); + spin_unlock(&fep->hw_lock); } @@ -716,7 +766,7 @@ uint mii_reg; fep = netdev_priv(dev); - spin_lock_irq(&fep->mii_lock); + spin_lock(&fep->mii_lock); ep = fep->hwp; mii_reg = ep->fec_mii_data; @@ -737,21 +787,19 @@ ep->fec_mii_data = mip->mii_regval; unlock: - spin_unlock_irq(&fep->mii_lock); + spin_unlock(&fep->mii_lock); } static int -mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *)) +mii_queue_unlocked(struct net_device *dev, int regval, void (*func)(uint, struct net_device *)) { struct fec_enet_private *fep; - unsigned long flags; mii_list_t *mip; int retval; /* Add PHY address to register command. */ fep = netdev_priv(dev); - spin_lock_irqsave(&fep->mii_lock, flags); regval |= fep->phy_addr << 23; retval = 0; @@ -772,7 +820,22 @@ retval = 1; } + return retval; +} + +static int +mii_queue(struct net_device *dev, int regval, + void (*func)(uint, struct net_device *)) +{ + struct fec_enet_private *fep; + unsigned long flags; + int retval; + + fep = netdev_priv(dev); + spin_lock_irqsave(&fep->mii_lock, flags); + retval = mii_queue_unlocked(dev, regval, func); spin_unlock_irqrestore(&fep->mii_lock, flags); + return retval; } @@ -1221,6 +1284,26 @@ }, }; +static phy_info_t phy_info_lan8700 = { + 0x0007C0C, + "LAN8700", + (const phy_cmd_t []) { /* config */ + { mk_mii_read(MII_REG_CR), mii_parse_cr }, + { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, + { mk_mii_end, } + }, + (const phy_cmd_t []) { /* startup */ + { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ + { mk_mii_read(MII_REG_SR), mii_parse_sr }, + { mk_mii_end, } + }, + (const phy_cmd_t []) { /* act_int */ + { mk_mii_end, } + }, + (const phy_cmd_t []) { /* shutdown */ + { mk_mii_end, } + }, +}; /* ------------------------------------------------------------------------- */ static phy_info_t const * const phy_info[] = { @@ -1230,22 +1313,33 @@ &phy_info_am79c874, &phy_info_ks8721bl, &phy_info_dp83848, + &phy_info_lan8700, NULL }; /* ------------------------------------------------------------------------- */ #ifdef HAVE_mii_link_interrupt -#ifdef CONFIG_RPXCLASSIC -static void -mii_link_interrupt(void *dev_id); -#else static irqreturn_t mii_link_interrupt(int irq, void * dev_id); #endif -#endif #if defined(CONFIG_M5272) /* + * * do some initializtion based architecture of this chip + * */ +static void __inline__ fec_arch_init(void) +{ + return; +} +/* + * * do some cleanup based architecture of this chip + * */ +static void __inline__ fec_arch_exit(void) +{ + return; +} + +/* * Code specific to Coldfire 5272 setup. */ static void __inline__ fec_request_intrs(struct net_device *dev) @@ -1265,7 +1359,7 @@ /* Setup interrupt handlers. */ for (idp = id; idp->name; idp++) { - if (request_irq(idp->irq, idp->handler, IRQF_DISABLED, idp->name, dev) != 0) + if (request_irq(idp->irq, idp->handler, IRQF_NODELAY | IRQF_DISABLED, idp->name, dev) != 0) printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq); } @@ -1346,15 +1440,40 @@ *icrp = 0x0d000000; } -static void __inline__ fec_localhw_setup(void) +static void __inline__ fec_localhw_setup(struct net_device *dev) +{ +} + +/* + * invalidate dcache related with the virtual memory range(start, end) + */ +static void __inline__ fec_dcache_inv_range(void * start, void * end) +{ + return ; +} + +/* + * flush dcache related with the virtual memory range(start, end) + */ +static void __inline__ fec_dcache_flush_range(void * start, void * end) +{ + return ; +} + +/* + * map memory space (addr, addr+size) to uncachable erea. + */ +static unsigned long __inline__ fec_map_uncache(unsigned long addr, int size) { + return addr; } /* - * Do not need to make region uncached on 5272. + * unmap memory erea started with addr from uncachable erea. */ -static void __inline__ fec_uncache(unsigned long addr) +static void __inline__ fec_unmap_uncache(void * addr) { + return ; } /* ------------------------------------------------------------------------- */ @@ -1362,6 +1481,22 @@ #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) /* + * do some initializtion based architecture of this chip + */ +static void __inline__ fec_arch_init(void) +{ + return; +} + +/* + * do some cleanup based architecture of this chip + */ +static void __inline__ fec_arch_exit(void) +{ + return; +} + +/* * Code specific to Coldfire 5230/5231/5232/5234/5235, * the 5270/5271/5274/5275 and 5280/5282 setups. */ @@ -1508,20 +1643,58 @@ { } -static void __inline__ fec_localhw_setup(void) +static void __inline__ fec_localhw_setup(struct net_device *dev) +{ +} +/* + * invalidate dcache related with the virtual memory range(start, end) + */ +static void __inline__ fec_dcache_inv_range(void * start, void * end) +{ + return ; +} + +/* + * flush dcache related with the virtual memory range(start, end) + */ +static void __inline__ fec_dcache_flush_range(void * start, void * end) +{ + return ; +} + +/* + * map memory space (addr, addr+size) to uncachable erea. + */ +static unsigned long __inline__ fec_map_uncache(unsigned long addr, int size) { + return addr; } /* - * Do not need to make region uncached on 5272. + * unmap memory erea started with addr from uncachable erea. */ -static void __inline__ fec_uncache(unsigned long addr) +static void __inline__ fec_unmap_uncache(void * addr) { + return ; } /* ------------------------------------------------------------------------- */ #elif defined(CONFIG_M520x) +/* + * do some initializtion based architecture of this chip + */ +static void __inline__ fec_arch_init(void) +{ + return; +} +/* + * do some cleanup based architecture of this chip + */ +static void __inline__ fec_arch_exit(void) +{ + return; +} /* * Code specific to Coldfire 520x @@ -1629,17 +1802,63 @@ { } -static void __inline__ fec_localhw_setup(void) +static void __inline__ fec_localhw_setup(struct net_device *dev) +{ +} + +/* + * invalidate dcache related with the virtual memory range(start, end) + */ +static void __inline__ fec_dcache_inv_range(void * start, void * end) +{ + return ; +} + +/* + * flush dcache related with the virtual memory range(start, end) + */ +static void __inline__ fec_dcache_flush_range(void * start, void * end) +{ + return ; +} + +/* + * map memory space (addr, addr+size) to uncachable erea. + */ +static unsigned long __inline__ fec_map_uncache(unsigned long addr, int size) { + return addr; } -static void __inline__ fec_uncache(unsigned long addr) +/* + * unmap memory erea started with addr from uncachable erea. + */ +static void __inline__ fec_unmap_uncache(void * addr) { + return ; } + /* ------------------------------------------------------------------------- */ #elif defined(CONFIG_M532x) + +/* + * do some initializtion based architecture of this chip + */ +static void __inline__ fec_arch_init(void) +{ + return; +} + +/* + * do some cleanup based architecture of this chip + */ +static void __inline__ fec_arch_exit(void) +{ + return; +} + /* * Code specific for M532x */ @@ -1768,21 +1987,294 @@ { } -static void __inline__ fec_localhw_setup(void) +static void __inline__ fec_localhw_setup(struct net_device *dev) +{ +} + +/* + * invalidate dcache related with the virtual memory range(start, end) + */ +static void __inline__ fec_dcache_inv_range(void * start, void * end) +{ + return ; +} + +/* + * flush dcache related with the virtual memory range(start, end) + */ +static void __inline__ fec_dcache_flush_range(void * start, void * end) +{ + return ; +} + +/* + * map memory space (addr, addr+size) to uncachable erea. + */ +static unsigned long __inline__ fec_map_uncache(unsigned long addr, int size) { + return addr; } /* - * Do not need to make region uncached on 532x. + * unmap memory erea started with addr from uncachable erea. */ -static void __inline__ fec_uncache(unsigned long addr) +static void __inline__ fec_unmap_uncache(void * addr) { + return ; } /* ------------------------------------------------------------------------- */ +#elif defined(CONFIG_ARCH_MXC) + +extern void gpio_fec_active(void); +extern void gpio_fec_inactive(void); +extern unsigned int expio_intr_fec; + +/* + * do some initializtion based architecture of this chip + */ +static void __inline__ fec_arch_init(void) +{ + struct clk *clk; + gpio_fec_active(); + clk = clk_get(NULL, "fec_clk"); + clk_enable(clk); + clk_put(clk); + return; +} +/* + * do some cleanup based architecture of this chip + */ +static void __inline__ fec_arch_exit(void) +{ + struct clk *clk; + clk = clk_get(NULL, "fec_clk"); + clk_disable(clk); + clk_put(clk); + gpio_fec_inactive(); + return; +} + +/* + * Code specific to Freescale i.MXC + */ +static void __inline__ fec_request_intrs(struct net_device *dev) +{ + /* Setup interrupt handlers. */ + if (request_irq(MXC_INT_FEC, fec_enet_interrupt, 0, "fec", dev) != 0) + panic("FEC: Could not allocate FEC IRQ(%d)!\n", MXC_INT_FEC); + /* TODO: disable now due to CPLD issue */ + if ((expio_intr_fec > 0) && + (request_irq(expio_intr_fec, mii_link_interrupt, 0, "fec(MII)", dev) != 0)) + panic("FEC: Could not allocate FEC(MII) IRQ(%d)!\n", expio_intr_fec); + disable_irq(expio_intr_fec); +} + +static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) +{ + u32 rate; + struct clk *clk; + volatile fec_t *fecp; + fecp = fep->hwp; + fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; + fecp->fec_x_cntrl = 0x00; + + /* + * Set MII speed to 2.5 MHz + */ + clk = clk_get(NULL, "fec_clk"); + rate = clk_get_rate(clk); + clk_put(clk); + + fep->phy_speed = + ((((rate / 2 + 4999999) / 2500000) / 2) & 0x3F) << 1; + fecp->fec_mii_speed = fep->phy_speed; + fec_restart(dev, 0); +} + +#define FEC_IIM_BASE IO_ADDRESS(IIM_BASE_ADDR) +static void __inline__ fec_get_mac(struct net_device *dev) +{ + struct fec_enet_private *fep = netdev_priv(dev); + volatile fec_t *fecp; + unsigned char *iap, tmpaddr[ETH_ALEN]; + int i; + unsigned long fec_mac_base = FEC_IIM_BASE + MXC_IIMKEY0; + fecp = fep->hwp; + + if (fecp->fec_addr_low || fecp->fec_addr_high) { + *((unsigned long *) &tmpaddr[0]) = + be32_to_cpu(fecp->fec_addr_low); + *((unsigned short *) &tmpaddr[4]) = + be32_to_cpu(fecp->fec_addr_high); + iap = &tmpaddr[0]; + } else { + if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) + fec_mac_base = FEC_IIM_BASE + MXC_IIMMAC; + + memset(tmpaddr, 0, ETH_ALEN); + if (!(machine_is_mx35_luigi() || cpu_is_mx51())) { + /* + * Get MAC address from IIM. + * If it is all 1's or 0's, use the default. + */ + for (i = 0; i < ETH_ALEN; i++) + tmpaddr[ETH_ALEN-1-i] = + __raw_readb(fec_mac_base + i * 4); + } + iap = &tmpaddr[0]; + + if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && + (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) + iap = fec_mac_default; + if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && + (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) + iap = fec_mac_default; + } + + memcpy(dev->dev_addr, iap, ETH_ALEN); + + /* Adjust MAC if using default MAC address */ + if (iap == fec_mac_default) + dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; +} + +#ifndef MODULE +static int fec_mac_setup(char *new_mac) +{ + char *ptr, *p = new_mac; + int i = 0; + + while (p && (*p) && i < 6) { + ptr = strchr(p, ':'); + if (ptr) + *ptr++ = '\0'; + + if (strlen(p)) { + unsigned long tmp = simple_strtoul(p, NULL, 16); + if (tmp > 0xff) + break; + fec_mac_default[i++] = tmp; + } + p = ptr; + } + + return 0; +} + +__setup("fec_mac=", fec_mac_setup); +#endif + +static void __inline__ fec_enable_phy_intr(void) +{ + if (expio_intr_fec > 0) + enable_irq(expio_intr_fec); +} + +static void __inline__ fec_disable_phy_intr(void) +{ + if (expio_intr_fec > 0) + disable_irq(expio_intr_fec); +} + +static void __inline__ fec_phy_ack_intr(void) +{ + if (expio_intr_fec > 0) + disable_irq(expio_intr_fec); +} + +#ifdef CONFIG_ARCH_MX25 +/* + * i.MX25 allows RMII mode to be configured via a gasket + */ +#define FEC_MIIGSK_CFGR_FRCONT (1 << 6) +#define FEC_MIIGSK_CFGR_LBMODE (1 << 4) +#define FEC_MIIGSK_CFGR_EMODE (1 << 3) +#define FEC_MIIGSK_CFGR_IF_MODE_MASK (3 << 0) +#define FEC_MIIGSK_CFGR_IF_MODE_MII (0 << 0) +#define FEC_MIIGSK_CFGR_IF_MODE_RMII (1 << 0) + +#define FEC_MIIGSK_ENR_READY (1 << 2) +#define FEC_MIIGSK_ENR_EN (1 << 1) + +static void __inline__ fec_localhw_setup(struct net_device *dev) +{ + struct fec_enet_private *fep = netdev_priv(dev); + volatile fec_t *fecp = fep->hwp; + /* + * Set up the MII gasket for RMII mode + */ + printk("%s: enable RMII gasket\n", dev->name); + + /* disable the gasket and wait */ + fecp->fec_miigsk_enr = 0; + while (fecp->fec_miigsk_enr & FEC_MIIGSK_ENR_READY) + udelay(1); + + /* configure the gasket for RMII, 50 MHz, no loopback, no echo */ + fecp->fec_miigsk_cfgr = FEC_MIIGSK_CFGR_IF_MODE_RMII; + + /* re-enable the gasket */ + fecp->fec_miigsk_enr = FEC_MIIGSK_ENR_EN; +} +#else +static void __inline__ fec_localhw_setup(struct net_device *dev) +{ +} +#endif + +/* + * invalidate dcache related with the virtual memory range(start, end) + */ +static void __inline__ fec_dcache_inv_range(void * start, void * end) +{ + dma_sync_single(NULL, (unsigned long)__pa(start), (unsigned long) (end-start), DMA_FROM_DEVICE); + return ; +} + +/* + * flush dcache related with the virtual memory range(start, end) + */ +static void __inline__ fec_dcache_flush_range(void * start, void * end) +{ + dma_sync_single(NULL, (unsigned long)__pa(start), (unsigned long) (end-start), DMA_BIDIRECTIONAL); + return ; +} + +/* + * map memory space (addr, addr+size) to uncachable erea. + */ +static unsigned long __inline__ fec_map_uncache(unsigned long addr, int size) +{ + return (unsigned long)ioremap(__pa(addr), size); +} + +/* + * unmap memory erea started with addr from uncachable erea. + */ +static void __inline__ fec_unmap_uncache(void * addr) +{ + return iounmap(addr); +} + +/* ------------------------------------------------------------------------- */ #else +/* + * do some initializtion based architecture of this chip + */ +static void __inline__ fec_arch_init(void) +{ + return; +} +/* + * do some cleanup based architecture of this chip + */ +static void __inline__ fec_arch_exit(void) +{ + return; +} /* * Code specific to the MPC860T setup. @@ -1795,24 +2287,6 @@ if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0) panic("Could not allocate FEC IRQ!"); - -#ifdef CONFIG_RPXCLASSIC - /* Make Port C, bit 15 an input that causes interrupts. - */ - immap->im_ioport.iop_pcpar &= ~0x0001; - immap->im_ioport.iop_pcdir &= ~0x0001; - immap->im_ioport.iop_pcso &= ~0x0001; - immap->im_ioport.iop_pcint |= 0x0001; - cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev); - - /* Make LEDS reflect Link status. - */ - *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE; -#endif -#ifdef CONFIG_FADS - if (request_8xxirq(SIU_IRQ2, mii_link_interrupt, 0, "mii", dev) != 0) - panic("Could not allocate MII IRQ!"); -#endif } static void __inline__ fec_get_mac(struct net_device *dev) @@ -1821,16 +2295,6 @@ bd = (bd_t *)__res; memcpy(dev->dev_addr, bd->bi_enetaddr, ETH_ALEN); - -#ifdef CONFIG_RPXCLASSIC - /* The Embedded Planet boards have only one MAC address in - * the EEPROM, but can have two Ethernet ports. For the - * FEC port, we create another address by setting one of - * the address bits above something that would have (up to - * now) been allocated. - */ - dev->dev_adrd[3] |= 0x80; -#endif } static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) @@ -1878,7 +2342,7 @@ { } -static void __inline__ fec_localhw_setup(void) +static void __inline__ fec_localhw_setup(struct net_device *dev) { volatile fec_t *fecp; @@ -1889,12 +2353,40 @@ fecp->fec_fun_code = 0x78000000; } -static void __inline__ fec_uncache(unsigned long addr) +/* + * invalidate dcache related with the virtual memory range(start, end) + */ +static void __inline__ fec_dcache_inv_range(void * start, void * end) +{ + return ; +} + +/* + * flush dcache related with the virtual memory range(start, end) + */ +static void __inline__ fec_dcache_flush_range(void * start, void * end) +{ + return ; +} + +/* + * map memory space (addr, addr+size) to uncachable erea. + */ +static unsigned long __inline__ fec_map_uncache(unsigned long addr, int size) { pte_t *pte; pte = va_to_pte(mem_addr); pte_val(*pte) |= _PAGE_NO_CACHE; flush_tlb_page(init_mm.mmap, mem_addr); + return addr; +} + +/* + * * unmap memory erea started with addr from uncachable erea. + * */ +static void __inline__ fec_unmap_uncache(void * addr) +{ + return ; } #endif @@ -2091,11 +2583,11 @@ /* Got first part of ID, now get remainder. */ fep->phy_id = phytype << 16; - mii_queue(dev, mk_mii_read(MII_REG_PHYIR2), + mii_queue_unlocked(dev, mk_mii_read(MII_REG_PHYIR2), mii_discover_phy3); } else { fep->phy_addr++; - mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), + mii_queue_unlocked(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy); } } else { @@ -2109,13 +2601,8 @@ /* This interrupt occurs when the PHY detects a link change. */ #ifdef HAVE_mii_link_interrupt -#ifdef CONFIG_RPXCLASSIC -static void -mii_link_interrupt(void *dev_id) -#else static irqreturn_t mii_link_interrupt(int irq, void * dev_id) -#endif { struct net_device *dev = dev_id; struct fec_enet_private *fep = netdev_priv(dev); @@ -2125,10 +2612,14 @@ #if 0 disable_irq(fep->mii_irq); /* disable now, enable later */ #endif - - mii_do_cmd(dev, fep->phy->ack_int); - mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */ - + /* + * Some board will trigger phy interrupt before phy enable. + * And at that moment , fep->phy is not initialized. + */ + if (fep->phy) { + mii_do_cmd(dev, fep->phy->ack_int); + mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */ + } return IRQ_HANDLED; } #endif @@ -2146,6 +2637,8 @@ fep->sequence_done = 0; fep->link = 0; + /* no phy, go full duplex, it's most likely a hub chip */ + fec_restart(dev, 1); if (fep->phy) { mii_do_cmd(dev, fep->phy->ack_int); mii_do_cmd(dev, fep->phy->config); @@ -2163,19 +2656,14 @@ mii_do_cmd(dev, fep->phy->startup); - /* Set the initial link state to true. A lot of hardware - * based on this device does not implement a PHY interrupt, - * so we are never notified of link change. - */ - fep->link = 1; - } else { - fep->link = 1; /* lets just try it and see */ - /* no phy, go full duplex, it's most likely a hub chip */ - fec_restart(dev, 1); } - - netif_start_queue(dev); + /* Set the initial link state to true. A lot of hardware + * based on this device does not implement a PHY interrupt, + * so we are never notified of link change. + */ + fep->link = 1; fep->opened = 1; + netif_start_queue(dev); return 0; /* Success */ } @@ -2187,9 +2675,9 @@ /* Don't know what to do yet. */ fep->opened = 0; - netif_stop_queue(dev); - fec_stop(dev); - + if (fep->link) { + fec_stop(dev); + } return 0; } @@ -2300,6 +2788,7 @@ unsigned long mem_addr; volatile cbd_t *bdp; cbd_t *cbd_base; + struct sk_buff* pskb; volatile fec_t *fecp; int i, j; static int index = 0; @@ -2308,6 +2797,8 @@ if (index >= FEC_MAX_PORTS) return -ENXIO; + fep->net = dev; + /* Allocate memory for buffer descriptors. */ mem_addr = __get_free_page(GFP_KERNEL); @@ -2316,6 +2807,7 @@ return -ENOMEM; } + fep->cbd_mem_base = (void *)mem_addr; spin_lock_init(&fep->hw_lock); spin_lock_init(&fep->mii_lock); @@ -2340,10 +2832,18 @@ */ fec_get_mac(dev); - cbd_base = (cbd_t *)mem_addr; - /* XXX: missing check for allocation failure */ +#if defined(CONFIG_MACH_MX35_LUIGI) + random_ether_addr(dev->dev_addr); +#endif + + cbd_base = (cbd_t *)fec_map_uncache(mem_addr, PAGE_SIZE); + if (cbd_base == NULL) { + free_page(mem_addr); + printk("FEC: map descriptor memory to uncacheable failed?\n"); + return -ENOMEM; + } - fec_uncache(mem_addr); + /* XXX: missing check for allocation failure */ /* Set receive and transmit descriptor base. */ @@ -2358,25 +2858,24 @@ /* Initialize the receive buffer descriptors. */ bdp = fep->rx_bd_base; - for (i=0; icbd_sc = BD_ENET_RX_EMPTY; - bdp->cbd_bufaddr = __pa(mem_addr); - mem_addr += FEC_ENET_RX_FRSIZE; - bdp++; + for (i=0; i0; i--) { + if( fep->rx_skbuff[i-1] ) { + kfree_skb(fep->rx_skbuff[i-1]); + fep->rx_skbuff[i-1] = NULL; + } + } + printk("FEC: allocate skb fail when initializing rx buffer \n"); + free_page(mem_addr); + return -ENOMEM; } + fep->rx_skbuff[i] = pskb; + pskb->data = FEC_ADDR_ALIGNMENT(pskb->data); + bdp->cbd_sc = BD_ENET_RX_EMPTY; + bdp->cbd_bufaddr = __pa(pskb->data); } - /* Set the last buffer to wrap. */ bdp--; @@ -2409,19 +2908,23 @@ /* Set receive and transmit descriptor base. */ - fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base)); - fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base)); + fecp->fec_r_des_start = __pa((uint)(fep->cbd_mem_base)); + fecp->fec_x_des_start = __pa((uint)(fep->cbd_mem_base + RX_RING_SIZE*sizeof(cbd_t))); /* Install our interrupt handlers. This varies depending on * the architecture. */ fec_request_intrs(dev); + /* Clear and enable interrupts */ + fecp->fec_ievent = FEC_ENET_MASK; + fecp->fec_imask = FEC_ENET_TXF | FEC_ENET_TXB | FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII; + fecp->fec_grp_hash_table_high = 0; fecp->fec_grp_hash_table_low = 0; fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; fecp->fec_ecntrl = 2; - fecp->fec_r_des_active = 0; + fecp->fec_r_des_active = 0x01000000; #ifndef CONFIG_M5272 fecp->fec_hash_table_high = 0; fecp->fec_hash_table_low = 0; @@ -2444,10 +2947,6 @@ /* setup MII interface */ fec_set_mii(dev, fep); - /* Clear and enable interrupts */ - fecp->fec_ievent = 0xffc00000; - fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII); - /* Queue up command to detect the PHY and initialize the * remainder of the interface. */ @@ -2479,9 +2978,15 @@ fecp->fec_ecntrl = 1; udelay(10); + /* Enable interrupts we wish to service. + */ + fecp->fec_imask = FEC_ENET_TXF | FEC_ENET_TXB | FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII; + /* Clear any outstanding interrupt. - */ - fecp->fec_ievent = 0xffc00000; + * + */ + fecp->fec_ievent = FEC_ENET_MASK; + fec_enable_phy_intr(); /* Set station address. @@ -2497,12 +3002,12 @@ */ fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; - fec_localhw_setup(); + fec_localhw_setup(dev); /* Set receive and transmit descriptor base. */ - fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base)); - fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base)); + fecp->fec_r_des_start = __pa((uint)(fep->cbd_mem_base)); + fecp->fec_x_des_start = __pa((uint)(fep->cbd_mem_base + RX_RING_SIZE*sizeof(cbd_t))); fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; fep->cur_rx = fep->rx_bd_base; @@ -2569,11 +3074,10 @@ /* And last, enable the transmit and receive processing. */ fecp->fec_ecntrl = 2; - fecp->fec_r_des_active = 0; + fecp->fec_r_des_active = 0x01000000; - /* Enable interrupts we wish to service. - */ - fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII); + if (fep->link) + netif_start_queue(dev); } static void @@ -2582,6 +3086,8 @@ volatile fec_t *fecp; struct fec_enet_private *fep; + netif_stop_queue(dev); + fep = netdev_priv(dev); fecp = fep->hwp; @@ -2617,6 +3123,7 @@ DECLARE_MAC_BUF(mac); printk("FEC ENET Version 0.2\n"); + fec_arch_init(); for (i = 0; (i < FEC_MAX_PORTS); i++) { dev = alloc_etherdev(sizeof(struct fec_enet_private)); diff -urN linux-2.6.26/drivers/net/fec.h linux-2.6.26-lab126/drivers/net/fec.h --- linux-2.6.26/drivers/net/fec.h 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/fec.h 2010-08-10 04:17:02.000000000 -0400 @@ -14,7 +14,7 @@ /****************************************************************************/ #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ - defined(CONFIG_M520x) || defined(CONFIG_M532x) + defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC) /* * Just figures, Motorola would have to change the offsets for * registers in the same peripheral device on different models @@ -56,6 +56,10 @@ unsigned long fec_r_des_start; /* Receive descriptor ring */ unsigned long fec_x_des_start; /* Transmit descriptor ring */ unsigned long fec_r_buff_size; /* Maximum receive buff size */ + unsigned long fec_reserved12[93]; + unsigned long fec_miigsk_cfgr; /* MIIGSK config register */ + unsigned long fec_reserved13; + unsigned long fec_miigsk_enr; /* MIIGSK enable register */ } fec_t; #else @@ -103,12 +107,22 @@ /* * Define the buffer descriptor structure. */ +/* Please see "Receive Buffer Descriptor Field Definitions" in Specification. + * It's LE. + */ +#ifdef CONFIG_ARCH_MXC +typedef struct bufdesc { + unsigned short cbd_datlen; /* Data length */ + unsigned short cbd_sc; /* Control and status info */ + unsigned long cbd_bufaddr; /* Buffer address */ +} cbd_t; +#else typedef struct bufdesc { unsigned short cbd_sc; /* Control and status info */ unsigned short cbd_datlen; /* Data length */ unsigned long cbd_bufaddr; /* Buffer address */ } cbd_t; - +#endif /* * The following definitions courtesy of commproc.h, which where diff -urN linux-2.6.26/drivers/net/hamradio/6pack.c linux-2.6.26-lab126/drivers/net/hamradio/6pack.c --- linux-2.6.26/drivers/net/hamradio/6pack.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/hamradio/6pack.c 2010-08-10 04:16:53.000000000 -0400 @@ -123,7 +123,7 @@ struct timer_list tx_t; struct timer_list resync_t; atomic_t refcnt; - struct semaphore dead_sem; + struct compat_semaphore dead_sem; spinlock_t lock; }; diff -urN linux-2.6.26/drivers/net/hamradio/mkiss.c linux-2.6.26-lab126/drivers/net/hamradio/mkiss.c --- linux-2.6.26/drivers/net/hamradio/mkiss.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/hamradio/mkiss.c 2010-08-10 04:16:53.000000000 -0400 @@ -84,7 +84,7 @@ #define CRC_MODE_SMACK_TEST 4 atomic_t refcnt; - struct semaphore dead_sem; + struct compat_semaphore dead_sem; }; /*---------------------------------------------------------------------------*/ diff -urN linux-2.6.26/drivers/net/ibm_emac/ibm_emac_core.c linux-2.6.26-lab126/drivers/net/ibm_emac/ibm_emac_core.c --- linux-2.6.26/drivers/net/ibm_emac/ibm_emac_core.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/ibm_emac/ibm_emac_core.c 2010-08-10 04:16:58.000000000 -0400 @@ -1058,6 +1058,8 @@ ++dev->stats.tx_packets; dev->stats.tx_bytes += len; + spin_unlock(&dev->tx_lock); + return 0; } @@ -1071,6 +1073,7 @@ u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY | MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb); + spin_lock(&dev->tx_lock); slot = dev->tx_slot++; if (dev->tx_slot == NUM_TX_BUFF) { dev->tx_slot = 0; @@ -1133,6 +1136,8 @@ if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE)) return emac_start_xmit(skb, ndev); + spin_lock(&dev->tx_lock); + len -= skb->data_len; /* Note, this is only an *estimation*, we can still run out of empty @@ -1201,6 +1206,7 @@ stop_queue: netif_stop_queue(ndev); DBG2("%d: stopped TX queue" NL, dev->def->index); + spin_unlock(&dev->tx_lock); return 1; } #else @@ -1240,6 +1246,7 @@ DBG2("%d: poll_tx, %d %d" NL, dev->def->index, dev->tx_cnt, dev->ack_slot); + spin_lock(&dev->tx_lock); if (dev->tx_cnt) { u16 ctrl; int slot = dev->ack_slot, n = 0; @@ -1249,6 +1256,7 @@ struct sk_buff *skb = dev->tx_skb[slot]; ++n; + spin_unlock(&dev->tx_lock); if (skb) { dev_kfree_skb(skb); dev->tx_skb[slot] = NULL; @@ -1258,6 +1266,7 @@ if (unlikely(EMAC_IS_BAD_TX(ctrl))) emac_parse_tx_error(dev, ctrl); + spin_lock(&dev->tx_lock); if (--dev->tx_cnt) goto again; } @@ -1270,6 +1279,7 @@ DBG2("%d: tx %d pkts" NL, dev->def->index, n); } } + spin_unlock(&dev->tx_lock); } static inline void emac_recycle_rx_skb(struct ocp_enet_private *dev, int slot, @@ -1964,6 +1974,7 @@ dev->ndev = ndev; dev->ldev = &ocpdev->dev; dev->def = ocpdev->def; + spin_lock_init(&dev->tx_lock); /* Find MAL device we are connected to */ maldev = diff -urN linux-2.6.26/drivers/net/ibm_emac/ibm_emac_core.h linux-2.6.26-lab126/drivers/net/ibm_emac/ibm_emac_core.h --- linux-2.6.26/drivers/net/ibm_emac/ibm_emac_core.h 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/ibm_emac/ibm_emac_core.h 2010-08-10 04:16:58.000000000 -0400 @@ -193,6 +193,8 @@ struct ibm_emac_error_stats estats; struct net_device_stats nstats; + spinlock_t tx_lock; + struct device* ldev; }; diff -urN linux-2.6.26/drivers/net/irda/Kconfig linux-2.6.26-lab126/drivers/net/irda/Kconfig --- linux-2.6.26/drivers/net/irda/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/irda/Kconfig 2010-08-10 04:16:26.000000000 -0400 @@ -342,5 +342,9 @@ To compile it as a module, choose M here: the module will be called mcs7780. +config MXC_FIR + tristate "Freescale MXC FIR driver" + depends on ARCH_MXC && IRDA + endmenu diff -urN linux-2.6.26/drivers/net/irda/Makefile linux-2.6.26-lab126/drivers/net/irda/Makefile --- linux-2.6.26/drivers/net/irda/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/irda/Makefile 2010-08-10 04:16:26.000000000 -0400 @@ -18,6 +18,7 @@ obj-$(CONFIG_VIA_FIR) += via-ircc.o obj-$(CONFIG_PXA_FICP) += pxaficp_ir.o obj-$(CONFIG_MCS_FIR) += mcs7780.o +obj-$(CONFIG_MXC_FIR) += mxc_ir.o obj-$(CONFIG_AU1000_FIR) += au1k_ir.o # SIR drivers obj-$(CONFIG_IRTTY_SIR) += irtty-sir.o sir-dev.o diff -urN linux-2.6.26/drivers/net/irda/mxc_ir.c linux-2.6.26-lab126/drivers/net/irda/mxc_ir.c --- linux-2.6.26/drivers/net/irda/mxc_ir.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/irda/mxc_ir.c 2010-08-10 04:16:26.000000000 -0400 @@ -0,0 +1,1777 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * Based on sa1100_ir.c - Copyright 2000-2001 Russell King + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_ir.c + * + * @brief Driver for the Freescale Semiconductor MXC FIRI. + * + * This driver is based on drivers/net/irda/sa1100_ir.c, by Russell King. + * + * @ingroup FIRI + */ + +/* + * Include Files + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include "mxc_ir.h" + +#define IS_SIR(mi) ( (mi)->speed <= 115200 ) +#define IS_MIR(mi) ( (mi)->speed < 4000000 && (mi)->speed >= 576000 ) +#define IS_FIR(mi) ( (mi)->speed >= 4000000 ) + +#define SDMA_START_DELAY() { \ + volatile int j,k;\ + int i;\ + for(i=0;i<10000;i++)\ + k=j;\ + } + +#define IRDA_FRAME_SIZE_LIMIT 2047 +#define UART_BUFF_SIZE 14384 + +#define UART4_UFCR_TXTL 16 +#define UART4_UFCR_RXTL 1 + +#define FIRI_SDMA_TX +#define FIRI_SDMA_RX + +/*! + * This structure is a way for the low level driver to define their own + * \b mxc_irda structure. This structure includes SK buffers, DMA buffers. + * and has other elements that are specifically required by this driver. + */ +struct mxc_irda { + /*! + * This keeps track of device is running or not + */ + unsigned char open; + + /*! + * This holds current FIRI communication speed + */ + int speed; + + /*! + * This holds FIRI communication speed for next packet + */ + int newspeed; + + /*! + * SK buffer for transmitter + */ + struct sk_buff *txskb; + + /*! + * SK buffer for receiver + */ + struct sk_buff *rxskb; + +#ifdef FIRI_SDMA_RX + /*! + * SK buffer for tasklet + */ + struct sk_buff *tskb; +#endif + + /*! + * DMA address for transmitter + */ + dma_addr_t dma_rx_buff_phy; + + /*! + * DMA address for receiver + */ + dma_addr_t dma_tx_buff_phy; + + /*! + * DMA Transmit buffer length + */ + unsigned int dma_tx_buff_len; + + /*! + * DMA channel for transmitter + */ + int txdma_ch; + + /*! + * DMA channel for receiver + */ + int rxdma_ch; + + /*! + * IrDA network device statistics + */ + struct net_device_stats stats; + + /*! + * The device structure used to get FIRI information + */ + struct device *dev; + + /*! + * Resource structure for UART, which will maintain base addresses and IRQs. + */ + struct resource *uart_res; + + /*! + * Base address of UART, used in readl and writel. + */ + void *uart_base; + + /*! + * Resource structure for FIRI, which will maintain base addresses and IRQs. + */ + struct resource *firi_res; + + /*! + * Base address of FIRI, used in readl and writel. + */ + void *firi_base; + + /*! + * UART IRQ number. + */ + int uart_irq; + + /*! + * Second UART IRQ number in case the interrupt lines are not muxed. + */ + int uart_irq1; + + /*! + * UART clock needed for baud rate calculations + */ + struct clk *uart_clk; + + /*! + * UART clock needed for baud rate calculations + */ + unsigned long uart_clk_rate; + + /*! + * FIRI clock needed for baud rate calculations + */ + struct clk *firi_clk; + + /*! + * FIRI IRQ number. + */ + int firi_irq; + + /*! + * IrLAP layer instance + */ + struct irlap_cb *irlap; + + /*! + * Driver supported baudrate capabilities + */ + struct qos_info qos; + + /*! + * Temporary transmit buffer used by the driver + */ + iobuff_t tx_buff; + + /*! + * Temporary receive buffer used by the driver + */ + iobuff_t rx_buff; + + /*! + * Pointer to platform specific data structure. + */ + struct mxc_ir_platform_data *mxc_ir_plat; + + /*! + * This holds the power management status of this module. + */ + int suspend; + +}; + +extern void gpio_firi_active(void *, unsigned int); +extern void gpio_firi_inactive(void); +extern void gpio_firi_init(void); + +void mxc_irda_firi_init(struct mxc_irda *si); +#ifdef FIRI_SDMA_RX +static void mxc_irda_fir_dma_rx_irq(void *id, int error_status, + unsigned int count); +#endif +#ifdef FIRI_SDMA_TX +static void mxc_irda_fir_dma_tx_irq(void *id, int error_status, + unsigned int count); +#endif + +/*! + * This function allocates and maps the receive buffer, + * unless it is already allocated. + * + * @param si FIRI device specific structure. + * @return The function returns 0 on success and a non-zero value on + * failure. + */ +static int mxc_irda_rx_alloc(struct mxc_irda *si) +{ +#ifdef FIRI_SDMA_RX + mxc_dma_requestbuf_t dma_request; +#endif + if (si->rxskb) { + return 0; + } + + si->rxskb = alloc_skb(IRDA_FRAME_SIZE_LIMIT + 1, GFP_ATOMIC); + + if (!si->rxskb) { + dev_err(si->dev, "mxc_ir: out of memory for RX SKB\n"); + return -ENOMEM; + } + + /* + * Align any IP headers that may be contained + * within the frame. + */ + skb_reserve(si->rxskb, 1); + +#ifdef FIRI_SDMA_RX + si->dma_rx_buff_phy = + dma_map_single(si->dev, si->rxskb->data, IRDA_FRAME_SIZE_LIMIT, + DMA_FROM_DEVICE); + + dma_request.num_of_bytes = IRDA_FRAME_SIZE_LIMIT; + dma_request.dst_addr = si->dma_rx_buff_phy; + dma_request.src_addr = si->firi_res->start; + + mxc_dma_config(si->rxdma_ch, &dma_request, 1, MXC_DMA_MODE_READ); +#endif + return 0; +} + +/*! + * This function is called to disable the FIRI dma + * + * @param si FIRI port specific structure. + */ +static void mxc_irda_disabledma(struct mxc_irda *si) +{ + /* Stop all DMA activity. */ +#ifdef FIRI_SDMA_TX + mxc_dma_disable(si->txdma_ch); +#endif +#ifdef FIRI_SDMA_RX + mxc_dma_disable(si->rxdma_ch); +#endif +} + +/*! + * This function is called to set the IrDA communications speed. + * + * @param si FIRI specific structure. + * @param speed new Speed to be configured for. + * + * @return The function returns 0 on success and a non-zero value on + * failure. + */ +static int mxc_irda_set_speed(struct mxc_irda *si, int speed) +{ + unsigned long flags; + int ret = 0; + unsigned int num, denom, baud; + unsigned int cr; + + dev_dbg(si->dev, "speed:%d\n", speed); + switch (speed) { + case 9600: + case 19200: + case 38400: + case 57600: + case 115200: + dev_dbg(si->dev, "starting SIR\n"); + baud = speed; + if (IS_FIR(si)) { +#ifdef FIRI_SDMA_RX + mxc_dma_disable(si->rxdma_ch); +#endif + cr = readl(si->firi_base + FIRITCR); + cr &= ~FIRITCR_TE; + writel(cr, si->firi_base + FIRITCR); + + cr = readl(si->firi_base + FIRIRCR); + cr &= ~FIRIRCR_RE; + writel(cr, si->firi_base + FIRIRCR); + + } + local_irq_save(flags); + + /* Disable Tx and Rx */ + cr = readl(si->uart_base + MXC_UARTUCR2); + cr &= ~(MXC_UARTUCR2_RXEN | MXC_UARTUCR2_TXEN); + writel(cr, si->uart_base + MXC_UARTUCR2); + + gpio_firi_inactive(); + + num = baud / 100 - 1; + denom = si->uart_clk_rate / 1600 - 1; + if ((denom < 65536) && (si->uart_clk_rate > 1600)) { + writel(num, si->uart_base + MXC_UARTUBIR); + writel(denom, si->uart_base + MXC_UARTUBMR); + } + + si->speed = speed; + + writel(0xFFFF, si->uart_base + MXC_UARTUSR1); + writel(0xFFFF, si->uart_base + MXC_UARTUSR2); + + /* Enable Receive Overrun and Data Ready interrupts. */ + cr = readl(si->uart_base + MXC_UARTUCR4); + cr |= (MXC_UARTUCR4_OREN | MXC_UARTUCR4_DREN); + writel(cr, si->uart_base + MXC_UARTUCR4); + + cr = readl(si->uart_base + MXC_UARTUCR2); + cr |= (MXC_UARTUCR2_RXEN | MXC_UARTUCR2_TXEN); + writel(cr, si->uart_base + MXC_UARTUCR2); + + local_irq_restore(flags); + break; + case 4000000: + local_irq_save(flags); + + /* Disable Receive Overrun and Data Ready interrupts. */ + cr = readl(si->uart_base + MXC_UARTUCR4); + cr &= ~(MXC_UARTUCR4_OREN | MXC_UARTUCR4_DREN); + writel(cr, si->uart_base + MXC_UARTUCR4); + + /* Disable Tx and Rx */ + cr = readl(si->uart_base + MXC_UARTUCR2); + cr &= ~(MXC_UARTUCR2_RXEN | MXC_UARTUCR2_TXEN); + writel(cr, si->uart_base + MXC_UARTUCR2); + + /* + * FIR configuration + */ + mxc_irda_disabledma(si); + + cr = readl(si->firi_base + FIRITCR); + cr &= ~FIRITCR_TE; + writel(cr, si->firi_base + FIRITCR); + + gpio_firi_active(si->firi_base + FIRITCR, FIRITCR_TPP); + + si->speed = speed; + + cr = readl(si->firi_base + FIRIRCR); + cr |= FIRIRCR_RE; + writel(cr, si->firi_base + FIRIRCR); + + dev_dbg(si->dev, "Going for fast IRDA ...\n"); + ret = mxc_irda_rx_alloc(si); + + /* clear RX status register */ + writel(0xFFFF, si->firi_base + FIRIRSR); +#ifdef FIRI_SDMA_RX + if (si->rxskb) { + mxc_dma_enable(si->rxdma_ch); + } +#endif + local_irq_restore(flags); + + break; + default: + dev_err(si->dev, "speed not supported by FIRI\n"); + break; + } + + return ret; +} + +/*! + * This function is called to set the IrDA communications speed. + * + * @param si FIRI specific structure. + * + * @return The function returns 0 on success and a non-zero value on + * failure. + */ +static inline int mxc_irda_fir_error(struct mxc_irda *si) +{ + struct sk_buff *skb = si->rxskb; + unsigned int dd_error, crc_error, overrun_error; + unsigned int sr; + + if (!skb) { + dev_err(si->dev, "no skb!\n"); + return -1; + } + + sr = readl(si->firi_base + FIRIRSR); + dd_error = sr & FIRIRSR_DDE; + crc_error = sr & FIRIRSR_CRCE; + overrun_error = sr & FIRIRSR_RFO; + + if (!(dd_error | crc_error | overrun_error)) { + return 0; + } + dev_err(si->dev, "dde,crce,rfo=%d,%d,%d.\n", dd_error, crc_error, + overrun_error); + si->stats.rx_errors++; + if (crc_error) { + si->stats.rx_crc_errors++; + } + if (dd_error) { + si->stats.rx_frame_errors++; + } + if (overrun_error) { + si->stats.rx_frame_errors++; + } + writel(sr, si->firi_base + FIRIRSR); + + return -1; +} + +#ifndef FIRI_SDMA_RX +/*! + * FIR interrupt service routine to handle receive. + * + * @param dev pointer to the net_device structure + */ +void mxc_irda_fir_irq_rx(struct net_device *dev) +{ + struct mxc_irda *si = dev->priv; + struct sk_buff *skb = si->rxskb; + unsigned int sr, len; + int i; + unsigned char *p = skb->data; + + /* + * Deal with any receive errors. + */ + if (mxc_irda_fir_error(si) != 0) { + return; + } + + sr = readl(si->firi_base + FIRIRSR); + + if (!(sr & FIRIRSR_RPE)) { + return; + } + + /* + * Coming here indicates that fir rx packet has been successfully recieved. + * And No error happened so far. + */ + writel(sr | FIRIRSR_RPE, si->firi_base + FIRIRSR); + + len = (sr & FIRIRSR_RFP) >> 8; + + /* 4 bytes of CRC */ + len -= 4; + + skb_put(skb, len); + + for (i = 0; i < len; i++) { + *p++ = readb(si->firi_base + FIRIRXFIFO); + } + + /* Discard the four CRC bytes */ + for (i = 0; i < 4; i++) { + readb(si->firi_base + FIRIRXFIFO); + } + + /* + * Deal with the case of packet complete. + */ + skb->dev = dev; + skb->mac.raw = skb->data; + skb->protocol = htons(ETH_P_IRDA); + si->stats.rx_packets++; + si->stats.rx_bytes += len; + netif_rx(skb); + + si->rxskb = NULL; + mxc_irda_rx_alloc(si); + + writel(0xFFFF, si->firi_base + FIRIRSR); + +} +#endif + +/*! + * FIR interrupt service routine to handle transmit. + * + * @param dev pointer to the net_device structure + */ +void mxc_irda_fir_irq_tx(struct net_device *dev) +{ + struct mxc_irda *si = dev->priv; + struct sk_buff *skb = si->txskb; + unsigned int cr, sr; + + sr = readl(si->firi_base + FIRITSR); + writel(sr, si->firi_base + FIRITSR); + + if (sr & FIRITSR_TC) { + +#ifdef FIRI_SDMA_TX + mxc_dma_disable(si->txdma_ch); +#endif + cr = readl(si->firi_base + FIRITCR); + cr &= ~(FIRITCR_TCIE | FIRITCR_TE); + writel(cr, si->firi_base + FIRITCR); + + if (si->newspeed) { + mxc_irda_set_speed(si, si->newspeed); + si->newspeed = 0; + } + si->txskb = NULL; + + cr = readl(si->firi_base + FIRIRCR); + cr |= FIRIRCR_RE; + writel(cr, si->firi_base + FIRIRCR); + + writel(0xFFFF, si->firi_base + FIRIRSR); + /* + * Account and free the packet. + */ + if (skb) { +#ifdef FIRI_SDMA_TX + dma_unmap_single(si->dev, si->dma_tx_buff_phy, skb->len, + DMA_TO_DEVICE); +#endif + si->stats.tx_packets++; + si->stats.tx_bytes += skb->len; + dev_kfree_skb_irq(skb); + } + /* + * Make sure that the TX queue is available for sending + * (for retries). TX has priority over RX at all times. + */ + netif_wake_queue(dev); + } +} + +/*! + * This is FIRI interrupt handler. + * + * @param dev pointer to the net_device structure + */ +void mxc_irda_fir_irq(struct net_device *dev) +{ + struct mxc_irda *si = dev->priv; + unsigned int sr1, sr2; + + sr1 = readl(si->firi_base + FIRIRSR); + sr2 = readl(si->firi_base + FIRITSR); + + if (sr2 & FIRITSR_TC) + mxc_irda_fir_irq_tx(dev); +#ifndef FIRI_SDMA_RX + if (sr1 & (FIRIRSR_RPE | FIRIRSR_RFO)) + mxc_irda_fir_irq_rx(dev); +#endif + +} + +/*! + * This is the SIR transmit routine. + * + * @param si FIRI specific structure. + * + * @param dev pointer to the net_device structure + * + * @return The function returns 0 on success and a non-zero value on + * failure. + */ +static int mxc_irda_sir_txirq(struct mxc_irda *si, struct net_device *dev) +{ + unsigned int sr1, sr2, cr; + unsigned int status; + + sr1 = readl(si->uart_base + MXC_UARTUSR1); + sr2 = readl(si->uart_base + MXC_UARTUSR2); + cr = readl(si->uart_base + MXC_UARTUCR2); + + /* + * Echo cancellation for IRDA Transmit chars + * Disable the receiver and enable Transmit complete. + */ + cr &= ~MXC_UARTUCR2_RXEN; + writel(cr, si->uart_base + MXC_UARTUCR2); + cr = readl(si->uart_base + MXC_UARTUCR4); + cr |= MXC_UARTUCR4_TCEN; + writel(cr, si->uart_base + MXC_UARTUCR4); + + while ((sr1 & MXC_UARTUSR1_TRDY) && si->tx_buff.len) { + + writel(*si->tx_buff.data++, si->uart_base + MXC_UARTUTXD); + si->tx_buff.len -= 1; + sr1 = readl(si->uart_base + MXC_UARTUSR1); + } + + if (si->tx_buff.len == 0) { + si->stats.tx_packets++; + si->stats.tx_bytes += si->tx_buff.data - si->tx_buff.head; + + /*Yoohoo...we are done...Lets stop Tx */ + cr = readl(si->uart_base + MXC_UARTUCR1); + cr &= ~MXC_UARTUCR1_TRDYEN; + writel(cr, si->uart_base + MXC_UARTUCR1); + + do { + status = readl(si->uart_base + MXC_UARTUSR2); + } while (!(status & MXC_UARTUSR2_TXDC)); + + if (si->newspeed) { + mxc_irda_set_speed(si, si->newspeed); + si->newspeed = 0; + } + /* I'm hungry! */ + netif_wake_queue(dev); + + /* Is the transmit complete to reenable the receiver? */ + if (status & MXC_UARTUSR2_TXDC) { + + cr = readl(si->uart_base + MXC_UARTUCR2); + cr |= MXC_UARTUCR2_RXEN; + writel(cr, si->uart_base + MXC_UARTUCR2); + /* Disable the Transmit complete interrupt bit */ + cr = readl(si->uart_base + MXC_UARTUCR4); + cr &= ~MXC_UARTUCR4_TCEN; + writel(cr, si->uart_base + MXC_UARTUCR4); + } + } + + return 0; +} + +/*! + * This is the SIR receive routine. + * + * @param si FIRI specific structure. + * + * @param dev pointer to the net_device structure + * + * @return The function returns 0 on success and a non-zero value on + * failure. + */ +static int mxc_irda_sir_rxirq(struct mxc_irda *si, struct net_device *dev) +{ + unsigned int data, status; + volatile unsigned int sr2; + + sr2 = readl(si->uart_base + MXC_UARTUSR2); + while ((sr2 & MXC_UARTUSR2_RDR) == 1) { + data = readl(si->uart_base + MXC_UARTURXD); + status = data & 0xf400; + if (status & MXC_UARTURXD_ERR) { + dev_err(si->dev, "Receive an incorrect data =0x%x.\n", + data); + si->stats.rx_errors++; + if (status & MXC_UARTURXD_OVRRUN) { + si->stats.rx_fifo_errors++; + dev_err(si->dev, "Rx overrun.\n"); + } + if (status & MXC_UARTURXD_FRMERR) { + si->stats.rx_frame_errors++; + dev_err(si->dev, "Rx frame error.\n"); + } + if (status & MXC_UARTURXD_PRERR) { + dev_err(si->dev, "Rx parity error.\n"); + } + /* Other: it is the Break char. + * Do nothing for it. throw out the data. + */ + async_unwrap_char(dev, &si->stats, &si->rx_buff, + (data & 0xFF)); + } else { + /* It is correct data. */ + data &= 0xFF; + async_unwrap_char(dev, &si->stats, &si->rx_buff, data); + + dev->last_rx = jiffies; + } + sr2 = readl(si->uart_base + MXC_UARTUSR2); + + writel(0xFFFF, si->uart_base + MXC_UARTUSR1); + writel(0xFFFF, si->uart_base + MXC_UARTUSR2); + } /*while */ + return 0; + +} + +static irqreturn_t mxc_irda_irq(int irq, void *dev_id) +{ + struct net_device *dev = dev_id; + struct mxc_irda *si = dev->priv; + + if (IS_FIR(si)) { + mxc_irda_fir_irq(dev); + return IRQ_HANDLED; + } + + if (readl(si->uart_base + MXC_UARTUCR2) & MXC_UARTUCR2_RXEN) { + mxc_irda_sir_rxirq(si, dev); + } + if ((readl(si->uart_base + MXC_UARTUCR1) & MXC_UARTUCR1_TRDYEN) && + (readl(si->uart_base + MXC_UARTUSR1) & MXC_UARTUSR1_TRDY)) { + mxc_irda_sir_txirq(si, dev); + } + + return IRQ_HANDLED; +} + +static irqreturn_t mxc_irda_tx_irq(int irq, void *dev_id) +{ + + struct net_device *dev = dev_id; + struct mxc_irda *si = dev->priv; + + mxc_irda_sir_txirq(si, dev); + + return IRQ_HANDLED; +} + +static irqreturn_t mxc_irda_rx_irq(int irq, void *dev_id) +{ + + struct net_device *dev = dev_id; + struct mxc_irda *si = dev->priv; + + /* Clear the aging timer bit */ + writel(MXC_UARTUSR1_AGTIM, si->uart_base + MXC_UARTUSR1); + + mxc_irda_sir_rxirq(si, dev); + + return IRQ_HANDLED; +} + +#ifdef FIRI_SDMA_RX +struct tasklet_struct dma_rx_tasklet; + +static void mxc_irda_rx_task(unsigned long tparam) +{ + struct mxc_irda *si = (struct mxc_irda *)tparam; + struct sk_buff *lskb = si->tskb; + + si->tskb = NULL; + if (lskb) { + lskb->mac_header = lskb->data; + lskb->protocol = htons(ETH_P_IRDA); + netif_rx(lskb); + } +} + +/*! + * Receiver DMA callback routine. + * + * @param id pointer to network device structure + * @param error_status used to pass error status to this callback function + * @param count number of bytes received + */ +static void mxc_irda_fir_dma_rx_irq(void *id, int error_status, + unsigned int count) +{ + struct net_device *dev = id; + struct mxc_irda *si = dev->priv; + struct sk_buff *skb = si->rxskb; + unsigned int cr; + unsigned int len; + + cr = readl(si->firi_base + FIRIRCR); + cr &= ~FIRIRCR_RE; + writel(cr, si->firi_base + FIRIRCR); + cr = readl(si->firi_base + FIRIRCR); + cr |= FIRIRCR_RE; + writel(cr, si->firi_base + FIRIRCR); + len = count - 4; /* remove 4 bytes for CRC */ + skb_put(skb, len); + skb->dev = dev; + si->tskb = skb; + tasklet_schedule(&dma_rx_tasklet); + + if (si->dma_rx_buff_phy != 0) + dma_unmap_single(si->dev, si->dma_rx_buff_phy, + IRDA_FRAME_SIZE_LIMIT, DMA_FROM_DEVICE); + + si->rxskb = NULL; + mxc_irda_rx_alloc(si); + + SDMA_START_DELAY(); + writel(0xFFFF, si->firi_base + FIRIRSR); + + if (si->rxskb) { + mxc_dma_enable(si->rxdma_ch); + } +} +#endif + +#ifdef FIRI_SDMA_TX +/*! + * This function is called by SDMA Interrupt Service Routine to indicate + * requested DMA transfer is completed. + * + * @param id pointer to network device structure + * @param error_status used to pass error status to this callback function + * @param count number of bytes sent + */ +static void mxc_irda_fir_dma_tx_irq(void *id, int error_status, + unsigned int count) +{ + struct net_device *dev = id; + struct mxc_irda *si = dev->priv; + + mxc_dma_disable(si->txdma_ch); +} +#endif + +/*! + * This function is called by Linux IrDA network subsystem to + * transmit the Infrared data packet. The TX DMA channel is configured + * to transfer SK buffer data to FIRI TX FIFO along with DMA transfer + * completion routine. + * + * @param skb The packet that is queued to be sent + * @param dev net_device structure. + * + * @return The function returns 0 on success and a negative value on + * failure. + */ +static int mxc_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct mxc_irda *si = dev->priv; + int speed = irda_get_next_speed(skb); + unsigned int cr; + + /* + * Does this packet contain a request to change the interface + * speed? If so, remember it until we complete the transmission + * of this frame. + */ + if (speed != si->speed && speed != -1) { + si->newspeed = speed; + } + + /* If this is an empty frame, we can bypass a lot. */ + if (skb->len == 0) { + if (si->newspeed) { + si->newspeed = 0; + mxc_irda_set_speed(si, speed); + } + dev_kfree_skb(skb); + return 0; + } + + /* We must not be transmitting... */ + netif_stop_queue(dev); + if (IS_SIR(si)) { + + si->tx_buff.data = si->tx_buff.head; + si->tx_buff.len = async_wrap_skb(skb, si->tx_buff.data, + si->tx_buff.truesize); + cr = readl(si->uart_base + MXC_UARTUCR1); + cr |= MXC_UARTUCR1_TRDYEN; + writel(cr, si->uart_base + MXC_UARTUCR1); + dev_kfree_skb(skb); + } else { + unsigned int mtt = irda_get_mtt(skb); + unsigned char *p = skb->data; + unsigned int skb_len = skb->len; +#ifdef FIRI_SDMA_TX + mxc_dma_requestbuf_t dma_request; +#else + unsigned int i, sr; +#endif + + skb_len = skb_len + ((4 - (skb_len % 4)) % 4); + + if (si->txskb) { + BUG(); + } + si->txskb = skb; + + /* + * If we have a mean turn-around time, impose the specified + * specified delay. We could shorten this by timing from + * the point we received the packet. + */ + if (mtt) { + udelay(mtt); + } + + cr = readl(si->firi_base + FIRIRCR); + cr &= ~FIRIRCR_RE; + writel(cr, si->firi_base + FIRIRCR); + + writel(skb->len - 1, si->firi_base + FIRITCTR); + +#ifdef FIRI_SDMA_TX + /* + * Configure DMA Tx Channel for source and destination addresses, + * Number of bytes in SK buffer to transfer and Transfer complete + * callback function. + */ + si->dma_tx_buff_len = skb_len; + si->dma_tx_buff_phy = + dma_map_single(si->dev, p, skb_len, DMA_TO_DEVICE); + + dma_request.num_of_bytes = skb_len; + dma_request.dst_addr = si->firi_res->start + FIRITXFIFO; + dma_request.src_addr = si->dma_tx_buff_phy; + + mxc_dma_config(si->txdma_ch, &dma_request, 1, + MXC_DMA_MODE_WRITE); + + mxc_dma_enable(si->txdma_ch); +#endif + cr = readl(si->firi_base + FIRITCR); + cr |= FIRITCR_TCIE; + writel(cr, si->firi_base + FIRITCR); + + cr |= FIRITCR_TE; + writel(cr, si->firi_base + FIRITCR); + +#ifndef FIRI_SDMA_TX + for (i = 0; i < skb->len;) { + sr = readl(si->firi_base + FIRITSR); + /* TFP = number of bytes in the TX FIFO for the + * Transmitter + * */ + if ((sr >> 8) < 128) { + writeb(*p, si->firi_base + FIRITXFIFO); + p++; + i++; + } + } +#endif + } + + dev->trans_start = jiffies; + return 0; +} + +/*! + * This function handles network interface ioctls passed to this driver.. + * + * @param dev net device structure + * @param ifreq user request data + * @param cmd command issued + * + * @return The function returns 0 on success and a non-zero value on + * failure. + */ +static int mxc_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd) +{ + struct if_irda_req *rq = (struct if_irda_req *)ifreq; + struct mxc_irda *si = dev->priv; + int ret = -EOPNOTSUPP; + + switch (cmd) { + /* This function will be used by IrLAP to change the speed */ + case SIOCSBANDWIDTH: + dev_dbg(si->dev, "%s:with cmd SIOCSBANDWIDTH\n", __FUNCTION__); + if (capable(CAP_NET_ADMIN)) { + /* + * We are unable to set the speed if the + * device is not running. + */ + if (si->open) { + ret = mxc_irda_set_speed(si, rq->ifr_baudrate); + } else { + dev_err(si->dev, "mxc_ir_ioctl: SIOCSBANDWIDTH:\ + !netif_running\n"); + ret = 0; + } + } + break; + case SIOCSMEDIABUSY: + dev_dbg(si->dev, "%s:with cmd SIOCSMEDIABUSY\n", __FUNCTION__); + ret = -EPERM; + if (capable(CAP_NET_ADMIN)) { + irda_device_set_media_busy(dev, TRUE); + ret = 0; + } + break; + case SIOCGRECEIVING: + rq->ifr_receiving = + IS_SIR(si) ? si->rx_buff.state != OUTSIDE_FRAME : 0; + ret = 0; + break; + default: + break; + } + return ret; +} + +/*! + * Kernel interface routine to get current statistics of the device + * which includes the number bytes/packets transmitted/received, + * receive errors, CRC errors, framing errors etc. + * + * @param dev the net_device structure + * + * @return This function returns IrDA network statistics + */ +static struct net_device_stats *mxc_irda_stats(struct net_device *dev) +{ + struct mxc_irda *si = dev->priv; + return &si->stats; +} + +/*! + * FIRI init function + * + * @param si FIRI device specific structure. + */ +void mxc_irda_firi_init(struct mxc_irda *si) +{ + unsigned int firi_baud, osf = 6; + unsigned int tcr, rcr, cr; + + si->firi_clk = clk_get(si->dev, "firi_clk"); + firi_baud = clk_round_rate(si->firi_clk, 48004500); + if ((firi_baud < 47995500) || + (clk_set_rate(si->firi_clk, firi_baud) < 0)) { + dev_err(si->dev, "Unable to set FIR clock to 48MHz.\n"); + return; + } + clk_enable(si->firi_clk); + + writel(0xFFFF, si->firi_base + FIRITSR); + writel(0xFFFF, si->firi_base + FIRIRSR); + writel(0x00, si->firi_base + FIRITCR); + writel(0x00, si->firi_base + FIRIRCR); + + /* set _BL & _OSF */ + cr = (osf - 1) | (16 << 5); + writel(cr, si->firi_base + FIRICR); + +#ifdef FIRI_SDMA_TX + tcr = + FIRITCR_TDT_FIR | FIRITCR_TM_FIR | FIRITCR_TCIE | + FIRITCR_PCF | FIRITCR_PC; +#else + tcr = FIRITCR_TM_FIR | FIRITCR_TCIE | FIRITCR_PCF | FIRITCR_PC; +#endif + +#ifdef FIRI_SDMA_RX + rcr = + FIRIRCR_RPEDE | FIRIRCR_RM_FIR | FIRIRCR_RDT_FIR | + FIRIRCR_RPA | FIRIRCR_RPP; +#else + rcr = + FIRIRCR_RPEDE | FIRIRCR_RM_FIR | FIRIRCR_RDT_FIR | FIRIRCR_RPEIE | + FIRIRCR_RPA | FIRIRCR_PAIE | FIRIRCR_RFOIE | FIRIRCR_RPP; +#endif + + writel(tcr, si->firi_base + FIRITCR); + writel(rcr, si->firi_base + FIRIRCR); + cr = 0; + writel(cr, si->firi_base + FIRITCTR); +} + +/*! + * This function initialises the UART. + * + * @param si FIRI port specific structure. + * + * @return The function returns 0 on success. + */ +static int mxc_irda_uart_init(struct mxc_irda *si) +{ + unsigned int per_clk; + unsigned int num, denom, baud, ufcr = 0; + unsigned int cr; + int d = 1; + int uart_ir_mux = 0; + + if (si->mxc_ir_plat) + uart_ir_mux = si->mxc_ir_plat->uart_ir_mux; + /* + * Clear Status Registers 1 and 2 + **/ + writel(0xFFFF, si->uart_base + MXC_UARTUSR1); + writel(0xFFFF, si->uart_base + MXC_UARTUSR2); + + /* Configure the IOMUX for the UART */ + gpio_firi_init(); + + per_clk = clk_get_rate(si->uart_clk); + baud = per_clk / 16; + if (baud > 1500000) { + baud = 1500000; + d = per_clk / ((baud * 16) + 1000); + if (d > 6) { + d = 6; + } + } + clk_enable(si->uart_clk); + + si->uart_clk_rate = per_clk / d; + writel(si->uart_clk_rate / 1000, si->uart_base + MXC_UARTONEMS); + + writel(si->mxc_ir_plat->ir_rx_invert | MXC_UARTUCR4_IRSC, + si->uart_base + MXC_UARTUCR4); + + if (uart_ir_mux) { + writel(MXC_UARTUCR3_RXDMUXSEL | si->mxc_ir_plat->ir_tx_invert | + MXC_UARTUCR3_DSR, si->uart_base + MXC_UARTUCR3); + } else { + writel(si->mxc_ir_plat->ir_tx_invert | MXC_UARTUCR3_DSR, + si->uart_base + MXC_UARTUCR3); + } + + writel(MXC_UARTUCR2_IRTS | MXC_UARTUCR2_CTS | MXC_UARTUCR2_WS | + MXC_UARTUCR2_ATEN | MXC_UARTUCR2_TXEN | MXC_UARTUCR2_RXEN, + si->uart_base + MXC_UARTUCR2); + /* Wait till we are out of software reset */ + do { + cr = readl(si->uart_base + MXC_UARTUCR2); + } while (!(cr & MXC_UARTUCR2_SRST)); + + ufcr |= (UART4_UFCR_TXTL << MXC_UARTUFCR_TXTL_OFFSET) | + ((6 - d) << MXC_UARTUFCR_RFDIV_OFFSET) | UART4_UFCR_RXTL; + writel(ufcr, si->uart_base + MXC_UARTUFCR); + + writel(MXC_UARTUCR1_UARTEN | MXC_UARTUCR1_IREN, + si->uart_base + MXC_UARTUCR1); + + baud = 9600; + num = baud / 100 - 1; + denom = si->uart_clk_rate / 1600 - 1; + + if ((denom < 65536) && (si->uart_clk_rate > 1600)) { + writel(num, si->uart_base + MXC_UARTUBIR); + writel(denom, si->uart_base + MXC_UARTUBMR); + } + + writel(0x0000, si->uart_base + MXC_UARTUTS); + return 0; + +} + +/*! + * This function enables FIRI port. + * + * @param si FIRI port specific structure. + * + * @return The function returns 0 on success and a non-zero value on + * failure. + */ +static int mxc_irda_startup(struct mxc_irda *si) +{ + int ret = 0; + + mxc_irda_uart_init(si); + mxc_irda_firi_init(si); + + /* configure FIRI device for speed */ + ret = mxc_irda_set_speed(si, si->speed = 9600); + + return ret; +} + +/*! + * When an ifconfig is issued which changes the device flag to include + * IFF_UP this function is called. It is only called when the change + * occurs, not when the interface remains up. The function grabs the interrupt + * resources and registers FIRI interrupt service routines, requests for DMA + * channels, configures the DMA channel. It then initializes the IOMUX + * registers to configure the pins for FIRI signals and finally initializes the + * various FIRI registers and enables the port for reception. + * + * @param dev net device structure that is being opened + * + * @return The function returns 0 for a successful open and non-zero value + * on failure. + */ +static int mxc_irda_start(struct net_device *dev) +{ + struct mxc_irda *si = dev->priv; + int err; + int ints_muxed = 0; + mxc_dma_device_t dev_id = 0; + + if (si->uart_irq == si->uart_irq1) + ints_muxed = 1; + + si->speed = 9600; + + if (si->uart_irq == si->firi_irq) { + err = + request_irq(si->uart_irq, mxc_irda_irq, 0, dev->name, dev); + if (err) { + dev_err(si->dev, "%s:Failed to request the IRQ\n", + __FUNCTION__); + return err; + } + /* + * The interrupt must remain disabled for now. + */ + disable_irq(si->uart_irq); + } else { + err = + request_irq(si->firi_irq, mxc_irda_irq, 0, dev->name, dev); + if (err) { + dev_err(si->dev, "%s:Failed to request FIRI IRQ\n", + __FUNCTION__); + return err; + } + /* + * The interrupt must remain disabled for now. + */ + disable_irq(si->firi_irq); + if (ints_muxed) { + + err = request_irq(si->uart_irq, mxc_irda_irq, 0, + dev->name, dev); + if (err) { + dev_err(si->dev, + "%s:Failed to request UART IRQ\n", + __FUNCTION__); + goto err_irq1; + } + /* + * The interrupt must remain disabled for now. + */ + disable_irq(si->uart_irq); + } else { + err = request_irq(si->uart_irq, mxc_irda_tx_irq, 0, + dev->name, dev); + if (err) { + dev_err(si->dev, + "%s:Failed to request UART IRQ\n", + __FUNCTION__); + goto err_irq1; + } + err = request_irq(si->uart_irq1, mxc_irda_rx_irq, 0, + dev->name, dev); + if (err) { + dev_err(si->dev, + "%s:Failed to request UART1 IRQ\n", + __FUNCTION__); + goto err_irq2; + } + /* + * The interrupts must remain disabled for now. + */ + disable_irq(si->uart_irq); + disable_irq(si->uart_irq1); + } + } +#ifdef FIRI_SDMA_RX + dev_id = MXC_DMA_FIR_RX; + si->rxdma_ch = mxc_dma_request(dev_id, "MXC FIRI RX"); + if (si->rxdma_ch < 0) { + dev_err(si->dev, "Cannot allocate FIR DMA channel\n"); + goto err_rx_dma; + } + mxc_dma_callback_set(si->rxdma_ch, mxc_irda_fir_dma_rx_irq, + (void *)dev_get_drvdata(si->dev)); +#endif +#ifdef FIRI_SDMA_TX + + dev_id = MXC_DMA_FIR_TX; + si->txdma_ch = mxc_dma_request(dev_id, "MXC FIRI TX"); + if (si->txdma_ch < 0) { + dev_err(si->dev, "Cannot allocate FIR DMA channel\n"); + goto err_tx_dma; + } + mxc_dma_callback_set(si->txdma_ch, mxc_irda_fir_dma_tx_irq, + (void *)dev_get_drvdata(si->dev)); +#endif + /* Setup the serial port port for the initial speed. */ + err = mxc_irda_startup(si); + if (err) { + goto err_startup; + } + + /* Open a new IrLAP layer instance. */ + si->irlap = irlap_open(dev, &si->qos, "mxc"); + err = -ENOMEM; + if (!si->irlap) { + goto err_irlap; + } + + /* Now enable the interrupt and start the queue */ + si->open = 1; + si->suspend = 0; + + if (si->uart_irq == si->firi_irq) { + enable_irq(si->uart_irq); + } else { + enable_irq(si->firi_irq); + if (ints_muxed == 1) { + enable_irq(si->uart_irq); + } else { + enable_irq(si->uart_irq); + enable_irq(si->uart_irq1); + } + } + + netif_start_queue(dev); + return 0; + + err_irlap: + si->open = 0; + mxc_irda_disabledma(si); + err_startup: +#ifdef FIRI_SDMA_TX + mxc_dma_free(si->txdma_ch); + err_tx_dma: +#endif +#ifdef FIRI_SDMA_RX + mxc_dma_free(si->rxdma_ch); + err_rx_dma: +#endif + if (si->uart_irq1 && !ints_muxed) + free_irq(si->uart_irq1, dev); + err_irq2: + if (si->uart_irq != si->firi_irq) + free_irq(si->uart_irq, dev); + err_irq1: + if (si->firi_irq) + free_irq(si->firi_irq, dev); + return err; +} + +/*! + * This function is called when IFF_UP flag has been cleared by the user via + * the ifconfig irda0 down command. This function stops any further + * transmissions being queued, and then disables the interrupts. + * Finally it resets the device. + * @param dev the net_device structure + * + * @return int the function always returns 0 indicating a success. + */ +static int mxc_irda_stop(struct net_device *dev) +{ + struct mxc_irda *si = netdev_priv(dev); + unsigned long flags; + + /* Stop IrLAP */ + if (si->irlap) { + irlap_close(si->irlap); + si->irlap = NULL; + } + + netif_stop_queue(dev); + + /*Save flags and disable the FIRI interrupts.. */ + if (si->open) { + local_irq_save(flags); + disable_irq(si->uart_irq); + free_irq(si->uart_irq, dev); + if (si->uart_irq != si->firi_irq) { + disable_irq(si->firi_irq); + free_irq(si->firi_irq, dev); + if (si->uart_irq1 != si->uart_irq) { + disable_irq(si->uart_irq1); + free_irq(si->uart_irq1, dev); + } + } + local_irq_restore(flags); + si->open = 0; + } +#ifdef FIRI_SDMA_RX + if (si->rxdma_ch) { + mxc_dma_disable(si->rxdma_ch); + mxc_dma_free(si->rxdma_ch); + if (si->dma_rx_buff_phy) { + dma_unmap_single(si->dev, si->dma_rx_buff_phy, + IRDA_FRAME_SIZE_LIMIT, + DMA_FROM_DEVICE); + si->dma_rx_buff_phy = 0; + } + si->rxdma_ch = 0; + } + tasklet_kill(&dma_rx_tasklet); +#endif +#ifdef FIRI_SDMA_TX + if (si->txdma_ch) { + mxc_dma_disable(si->txdma_ch); + mxc_dma_free(si->txdma_ch); + if (si->dma_tx_buff_phy) { + dma_unmap_single(si->dev, si->dma_tx_buff_phy, + si->dma_tx_buff_len, DMA_TO_DEVICE); + si->dma_tx_buff_phy = 0; + } + si->txdma_ch = 0; + } +#endif + return 0; +} + +#ifdef CONFIG_PM +/*! + * This function is called to put the FIRI in a low power state. Refer to the + * document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which FIRI + * to suspend + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int mxc_irda_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct net_device *ndev = platform_get_drvdata(pdev); + struct mxc_irda *si = netdev_priv(ndev); + unsigned int cr; + unsigned long flags; + + if (!si) { + return 0; + } + if (si->suspend == 1) { + dev_err(si->dev, + " suspend - Device is already suspended ... \n"); + return 0; + } + if (si->open) { + + netif_device_detach(ndev); + mxc_irda_disabledma(si); + + /*Save flags and disable the FIRI interrupts.. */ + local_irq_save(flags); + disable_irq(si->uart_irq); + if (si->uart_irq != si->firi_irq) { + disable_irq(si->firi_irq); + if (si->uart_irq != si->uart_irq1) { + disable_irq(si->uart_irq1); + } + } + local_irq_restore(flags); + + /* Disable Tx and Rx and then disable the UART clock */ + cr = readl(si->uart_base + MXC_UARTUCR2); + cr &= ~(MXC_UARTUCR2_TXEN | MXC_UARTUCR2_RXEN); + writel(cr, si->uart_base + MXC_UARTUCR2); + cr = readl(si->uart_base + MXC_UARTUCR1); + cr &= ~MXC_UARTUCR1_UARTEN; + writel(cr, si->uart_base + MXC_UARTUCR1); + clk_disable(si->uart_clk); + + /*Disable Tx and Rx for FIRI and then disable the FIRI clock.. */ + cr = readl(si->firi_base + FIRITCR); + cr &= ~FIRITCR_TE; + writel(cr, si->firi_base + FIRITCR); + cr = readl(si->firi_base + FIRIRCR); + cr &= ~FIRIRCR_RE; + writel(cr, si->firi_base + FIRIRCR); + clk_disable(si->firi_clk); + + gpio_firi_inactive(); + + si->suspend = 1; + si->open = 0; + } + return 0; +} + +/*! + * This function is called to bring the FIRI back from a low power state. Refer + * to the document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which FIRI + * to resume + * + * @return The function always returns 0. + */ +static int mxc_irda_resume(struct platform_device *pdev) +{ + struct net_device *ndev = platform_get_drvdata(pdev); + struct mxc_irda *si = netdev_priv(ndev); + unsigned long flags; + + if (!si) { + return 0; + } + + if (si->suspend == 1 && !si->open) { + + /*Initialise the UART first */ + clk_enable(si->uart_clk); + + /*Now init FIRI */ + gpio_firi_active(si->firi_base + FIRITCR, FIRITCR_TPP); + mxc_irda_startup(si); + + /* Enable the UART and FIRI interrupts.. */ + local_irq_save(flags); + enable_irq(si->uart_irq); + if (si->uart_irq != si->firi_irq) { + enable_irq(si->firi_irq); + if (si->uart_irq != si->uart_irq1) { + enable_irq(si->uart_irq1); + } + } + local_irq_restore(flags); + + /* Let the kernel know that we are alive and kicking.. */ + netif_device_attach(ndev); + + si->suspend = 0; + si->open = 1; + } + return 0; +} +#else +#define mxc_irda_suspend NULL +#define mxc_irda_resume NULL +#endif + +static int mxc_irda_init_iobuf(iobuff_t * io, int size) +{ + io->head = kmalloc(size, GFP_KERNEL | GFP_DMA); + if (io->head != NULL) { + io->truesize = size; + io->in_frame = FALSE; + io->state = OUTSIDE_FRAME; + io->data = io->head; + } + return io->head ? 0 : -ENOMEM; + +} + +/*! + * This function is called during the driver binding process. + * This function requests for memory, initializes net_device structure and + * registers with kernel. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions + * + * @return The function returns 0 on success and a non-zero value on failure + */ +static int mxc_irda_probe(struct platform_device *pdev) +{ + struct net_device *dev; + struct mxc_irda *si; + struct resource *uart_res, *firi_res; + int uart_irq, firi_irq, uart_irq1; + unsigned int baudrate_mask = 0; + int err; + + uart_res = &pdev->resource[0]; + uart_irq = pdev->resource[1].start; + + firi_res = &pdev->resource[2]; + firi_irq = pdev->resource[3].start; + + uart_irq1 = pdev->resource[4].start; + + if (!uart_res || uart_irq == NO_IRQ || !firi_res || firi_irq == NO_IRQ) { + dev_err(&pdev->dev, "Unable to find resources\n"); + return -ENXIO; + } + + err = + request_mem_region(uart_res->start, SZ_16K, + "MXC_IRDA") ? 0 : -EBUSY; + if (err) { + dev_err(&pdev->dev, "Failed to request UART memory region\n"); + return -ENOMEM; + } + + err = + request_mem_region(firi_res->start, SZ_16K, + "MXC_IRDA") ? 0 : -EBUSY; + if (err) { + dev_err(&pdev->dev, "Failed to request FIRI memory region\n"); + goto err_mem_1; + } + + dev = alloc_irdadev(sizeof(struct mxc_irda)); + if (!dev) { + goto err_mem_2; + } + + si = netdev_priv(dev); + si->dev = &pdev->dev; + + si->mxc_ir_plat = pdev->dev.platform_data; + si->uart_clk = si->mxc_ir_plat->uart_clk; + + si->uart_res = uart_res; + si->firi_res = firi_res; + si->uart_irq = uart_irq; + si->firi_irq = firi_irq; + si->uart_irq1 = uart_irq1; + + si->uart_base = ioremap(uart_res->start, SZ_16K); + si->firi_base = ioremap(firi_res->start, SZ_16K); + + if (!(si->uart_base || si->firi_base)) { + err = -ENOMEM; + goto err_mem_3; + } + + /* + * Initialise the SIR buffers + */ + err = mxc_irda_init_iobuf(&si->rx_buff, UART_BUFF_SIZE); + if (err) { + goto err_mem_4; + } + + err = mxc_irda_init_iobuf(&si->tx_buff, UART_BUFF_SIZE); + if (err) { + goto err_mem_5; + } + + dev->hard_start_xmit = mxc_irda_hard_xmit; + dev->open = mxc_irda_start; + dev->stop = mxc_irda_stop; + dev->do_ioctl = mxc_irda_ioctl; + dev->get_stats = mxc_irda_stats; + + irda_init_max_qos_capabilies(&si->qos); + + /* + * We support + * SIR(9600, 19200,38400, 57600 and 115200 bps) + * FIR(4 Mbps) + * Min Turn Time set to 1ms or greater. + */ + baudrate_mask |= IR_9600 | IR_19200 | IR_38400 | IR_57600 | IR_115200; + baudrate_mask |= IR_4000000 << 8; + + si->qos.baud_rate.bits &= baudrate_mask; + si->qos.min_turn_time.bits = 0x7; + + irda_qos_bits_to_value(&si->qos); + +#ifdef FIRI_SDMA_RX + si->tskb = NULL; + tasklet_init(&dma_rx_tasklet, mxc_irda_rx_task, (unsigned long)si); +#endif + err = register_netdev(dev); + if (err == 0) { + platform_set_drvdata(pdev, dev); + } else { + kfree(si->tx_buff.head); + err_mem_5: + kfree(si->rx_buff.head); + err_mem_4: + iounmap(si->uart_base); + iounmap(si->firi_base); + err_mem_3: + free_netdev(dev); + err_mem_2: + release_mem_region(firi_res->start, SZ_16K); + err_mem_1: + release_mem_region(uart_res->start, SZ_16K); + } + return err; +} + +/*! + * Dissociates the driver from the FIRI device. Removes the appropriate FIRI + * port structure from the kernel. + * + * @param pdev the device structure used to give information on which FIRI + * to remove + * + * @return The function always returns 0. + */ +static int mxc_irda_remove(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + struct mxc_irda *si = netdev_priv(dev); + + if (si->uart_base) + iounmap(si->uart_base); + if (si->firi_base) + iounmap(si->firi_base); + if (si->firi_res->start) + release_mem_region(si->firi_res->start, SZ_16K); + if (si->uart_res->start) + release_mem_region(si->uart_res->start, SZ_16K); + if (si->tx_buff.head) + kfree(si->tx_buff.head); + if (si->rx_buff.head) + kfree(si->rx_buff.head); + + platform_set_drvdata(pdev, NULL); + unregister_netdev(dev); + free_netdev(dev); + + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxcir_driver = { + .driver = { + .name = "mxcir", + }, + .probe = mxc_irda_probe, + .remove = mxc_irda_remove, + .suspend = mxc_irda_suspend, + .resume = mxc_irda_resume, +}; + +/*! + * This function is used to initialize the FIRI driver module. The function + * registers the power management callback functions with the kernel and also + * registers the FIRI callback functions. + * + * @return The function returns 0 on success and a non-zero value on failure. + */ +static int __init mxc_irda_init(void) +{ + return platform_driver_register(&mxcir_driver); +} + +/*! + * This function is used to cleanup all resources before the driver exits. + */ +static void __exit mxc_irda_exit(void) +{ + platform_driver_unregister(&mxcir_driver); +} + +module_init(mxc_irda_init); +module_exit(mxc_irda_exit); + +MODULE_AUTHOR("Freescale Semiconductor"); +MODULE_DESCRIPTION("MXC IrDA(SIR/FIR) driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/net/irda/mxc_ir.h linux-2.6.26-lab126/drivers/net/irda/mxc_ir.h --- linux-2.6.26/drivers/net/irda/mxc_ir.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/irda/mxc_ir.h 2010-08-10 04:16:26.000000000 -0400 @@ -0,0 +1,133 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MXC_FIRI_REG_H__ +#define __MXC_FIRI_REG_H__ + +#include + +/*! + * @defgroup FIRI Fast IR Driver + */ + +/*! + * @file mxc_ir.h + * + * @brief MXC FIRI header file + * + * This file defines base address and bits of FIRI registers + * + * @ingroup FIRI + */ + +/*! + * FIRI maximum packet length + */ +#define FIR_MAX_RXLEN 2047 + +/* + * FIRI Transmitter Control Register + */ +#define FIRITCR 0x00 +/* + * FIRI Transmitter Count Register + */ +#define FIRITCTR 0x04 +/* + * FIRI Receiver Control Register + */ +#define FIRIRCR 0x08 +/* + * FIRI Transmitter Status Register + */ +#define FIRITSR 0x0C +/* + * FIRI Receiver Status Register + */ +#define FIRIRSR 0x10 +/* + * FIRI Transmitter FIFO + */ +#define FIRITXFIFO 0x14 +/* + * FIRI Receiver FIFO + */ +#define FIRIRXFIFO 0x18 +/* + * FIRI Control Register + */ +#define FIRICR 0x1C + +/* + * Bit definitions of Transmitter Controller Register + */ +#define FIRITCR_HAG (1<<24) /* H/W address generator */ +#define FIRITCR_SRF_FIR (0<<13) /* Start field repeat factor */ +#define FIRITCR_SRF_MIR (1<<13) /* Start field Repeat Factor */ +#define FIRITCR_TDT_MIR (2<<10) /* TX trigger for MIR is set to 32 bytes) */ +#define FIRITCR_TDT_FIR (1<<10) /* TX trigger for FIR is set to 16 bytes) */ +#define FIRITCR_TCIE (1<<9) /* TX Complete Interrupt Enable */ +#define FIRITCR_TPEIE (1<<8) /* TX Packet End Interrupt Enable */ +#define FIRITCR_TFUIE (1<<7) /* TX FIFO Under-run Interrupt Enable */ +#define FIRITCR_PCF (1<<6) /* Packet Complete by FIFO */ +#define FIRITCR_PC (1<<5) /* Packet Complete */ +#define FIRITCR_SIP (1<<4) /* TX Enable of SIP */ +#define FIRITCR_TPP (1<<3) /* TX Pulse Polarity bit */ +#define FIRITCR_TM_FIR (0<<1) /* TX Mode 4 Mbps */ +#define FIRITCR_TM_MIR1 (1<<1) /* TX Mode 0.576 Mbps */ +#define FIRITCR_TM_MIR2 (1<<2) /* TX Mode 1.152 Mbps */ +#define FIRITCR_TE (1<<0) /* TX Enable */ + +/* + * Bit definitions of Transmitter Count Register + */ +#define FIRITCTR_TPL 511 /* TX Packet Length set to 512 bytes */ + +/* + * Bit definitions of Receiver Control Register + */ +#define FIRIRCR_RAM (1<<24) /* RX Address Match */ +#define FIRIRCR_RPEDE (1<<11) /* Packet End DMA request Enable */ +#define FIRIRCR_RDT_MIR (2<<8) /* DMA Trigger level(64 bytes in RXFIFO) */ +#define FIRIRCR_RDT_FIR (1<<8) /* DMA Trigger level(16 bytes in RXFIFO) */ +#define FIRIRCR_RPA (1<<7) /* RX Packet Abort */ +#define FIRIRCR_RPEIE (1<<6) /* RX Packet End Interrupt Enable */ +#define FIRIRCR_PAIE (1<<5) /* Packet Abort Interrupt Enable */ +#define FIRIRCR_RFOIE (1<<4) /* RX FIFO Overrun Interrupt Enable */ +#define FIRIRCR_RPP (1<<3) /* RX Pulse Polarity bit */ +#define FIRIRCR_RM_FIR (0<<1) /* 4 Mbps */ +#define FIRIRCR_RM_MIR1 (1<<1) /* 0.576 Mbps */ +#define FIRIRCR_RM_MIR2 (1<<2) /* 1.152 Mbps */ +#define FIRIRCR_RE (1<<0) /* RX Enable */ + +/* Transmitter Status Register */ +#define FIRITSR_TFP 0xFF00 /* Mask for available bytes in TX FIFO */ +#define FIRITSR_TC (1<<3) /* Transmit Complete bit */ +#define FIRITSR_SIPE (1<<2) /* SIP End bit */ +#define FIRITSR_TPE (1<<1) /* Transmit Packet End */ +#define FIRITSR_TFU (1<<0) /* TX FIFO Under-run */ + +/* Receiver Status Register */ +#define FIRIRSR_RFP 0xFF00 /* mask for available bytes RX FIFO */ +#define FIRIRSR_PAS (1<<5) /* preamble search */ +#define FIRIRSR_RPE (1<<4) /* RX Packet End */ +#define FIRIRSR_RFO (1<<3) /* RX FIFO Overrun */ +#define FIRIRSR_BAM (1<<2) /* Broadcast Address Match */ +#define FIRIRSR_CRCE (1<<1) /* CRC error */ +#define FIRIRSR_DDE (1<<0) /* Address, control or data field error */ + +/* FIRI Control Register */ +#define FIRICR_BL (32<<5) /* Burst Length is set to 32 */ +#define FIRICR_OSF (0<<1) /* Over Sampling Factor */ + +#endif /* __MXC_FIRI_REG_H__ */ diff -urN linux-2.6.26/drivers/net/loopback.c linux-2.6.26-lab126/drivers/net/loopback.c --- linux-2.6.26/drivers/net/loopback.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/loopback.c 2010-08-10 04:17:02.000000000 -0400 @@ -152,13 +152,13 @@ #endif dev->last_rx = jiffies; - /* it's OK to use per_cpu_ptr() because BHs are off */ pcpu_lstats = netdev_priv(dev); - lb_stats = per_cpu_ptr(pcpu_lstats, smp_processor_id()); + lb_stats = per_cpu_ptr(pcpu_lstats, get_cpu()); lb_stats->bytes += skb->len; lb_stats->packets++; + put_cpu(); - netif_rx(skb); + netif_rx_ni(skb); return 0; } diff -urN linux-2.6.26/drivers/net/ppp_async.c linux-2.6.26-lab126/drivers/net/ppp_async.c --- linux-2.6.26/drivers/net/ppp_async.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/ppp_async.c 2010-08-10 04:17:02.000000000 -0400 @@ -34,6 +34,10 @@ #include #include +#ifdef CONFIG_MACH_LUIGI_LAB126 +#include +#endif + #define PPP_VERSION "2.4.2" #define OBUFSIZE 256 @@ -67,7 +71,7 @@ struct tasklet_struct tsk; atomic_t refcnt; - struct semaphore dead_sem; + struct compat_semaphore dead_sem; struct ppp_channel chan; /* interface to generic ppp layer */ unsigned char obuf[OBUFSIZE]; }; @@ -393,6 +397,10 @@ .write_wakeup = ppp_asynctty_wakeup, }; +#ifdef CONFIG_MACH_LUIGI_LAB126 +static int modem_requires_sync_byte = 0; +#endif + static int __init ppp_async_init(void) { @@ -402,6 +410,11 @@ if (err != 0) printk(KERN_ERR "PPP_async: error %d registering line disc.\n", err); + +#ifdef CONFIG_MACH_LUIGI_LAB126 + modem_requires_sync_byte = wan_get_modem_type() == MODEM_TYPE_AD_DTP; +#endif + return err; } @@ -567,7 +580,12 @@ * character if necessary. */ if (islcp || flag_time == 0 - || time_after_eq(jiffies, ap->last_xmit + flag_time)) + || time_after_eq(jiffies, ap->last_xmit + flag_time) +#ifdef CONFIG_MACH_LUIGI_LAB126 + || modem_requires_sync_byte) +#else + ) +#endif *buf++ = PPP_FLAG; ap->last_xmit = jiffies; fcs = PPP_INITFCS; diff -urN linux-2.6.26/drivers/net/ppp_generic.c linux-2.6.26-lab126/drivers/net/ppp_generic.c --- linux-2.6.26/drivers/net/ppp_generic.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/ppp_generic.c 2010-08-11 00:35:01.000000000 -0400 @@ -2428,6 +2428,7 @@ dev->hard_start_xmit = ppp_start_xmit; dev->do_ioctl = ppp_net_ioctl; + dev->features = NETIF_F_LLTX; ret = -EEXIST; mutex_lock(&all_ppp_mutex); diff -urN linux-2.6.26/drivers/net/smc911x.h linux-2.6.26-lab126/drivers/net/smc911x.h --- linux-2.6.26/drivers/net/smc911x.h 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/smc911x.h 2010-08-10 04:17:02.000000000 -0400 @@ -44,6 +44,12 @@ #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW #endif +#ifdef CONFIG_ARCH_MXC + #define SMC_USE_16BIT 0 + #define SMC_USE_32BIT 1 + #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW +#endif + /* * Define the bus width specific IO macros @@ -608,6 +614,8 @@ #define CHIP_9116 0x116 #define CHIP_9117 0x117 #define CHIP_9118 0x118 +#define CHIP_9217 0x117A +#define CHIP_9218 0x118A struct chip_id { u16 id; @@ -619,6 +627,8 @@ { CHIP_9116, "LAN9116" }, { CHIP_9117, "LAN9117" }, { CHIP_9118, "LAN9118" }, + { CHIP_9217, "LAN9217" }, + { CHIP_9218, "LAN9218" }, { 0, NULL }, }; diff -urN linux-2.6.26/drivers/net/smsc911x.c linux-2.6.26-lab126/drivers/net/smsc911x.c --- linux-2.6.26/drivers/net/smsc911x.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/smsc911x.c 2010-08-10 04:17:02.000000000 -0400 @@ -0,0 +1,2253 @@ +/*************************************************************************** + * + * Copyright (C) 2004-2007 SMSC + * Copyright (C) 2005 ARM + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + *************************************************************************** + * Rewritten, heavily based on smsc911x simple driver by SMSC. + * Partly uses io macros from smc91x.c by Nicolas Pitre + * + * Supported devices: + * LAN9115, LAN9116, LAN9117, LAN9118 + * LAN9215, LAN9216, LAN9217, LAN9218 + * + * History: + * 05/05/2005 bahadir.balban@arm.com + * - Transition to linux coding style + * - Platform driver and module interface + * + * 17/07/2006 steve.glendinning@smsc.com + * - Added support for LAN921x family + * - Added workaround for multicast filters + * + * 31/07/2006 steve.glendinning@smsc.com + * - Removed tasklet, using NAPI poll instead + * - Multiple device support + * - Large tidy-up following feedback from netdev list + * + * 03/08/2006 steve.glendinning@smsc.com + * - Added ethtool support + * - Convert to use generic MII interface + * + * 04/08/2006 bahadir.balban@arm.com + * - Added ethtool eeprom r/w support + * + * 17/06/2007 steve.glendinning@smsc.com + * - Incorporate changes from Bill Gatliff and Russell King + * + * 04/07/2007 steve.glendinning@smsc.com + * - move irq configuration to platform_device + * - fix link poller after interface is stopped and restarted + * + * 13/07/2007 bahadir.balban@arm.com + * - set irq polarity before requesting irq + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "smsc911x.h" + +#define SMSC_CHIPNAME "smsc911x" +#define SMSC_DRV_VERSION "2007-07-13" + +MODULE_LICENSE("GPL"); + +struct smsc911x_data { + void __iomem *ioaddr; + + unsigned int idrev; + unsigned int generation; /* used to decide which workarounds apply */ + + /* device configuration */ + unsigned int irq_polarity; + unsigned int irq_type; + + /* This needs to be acquired before calling any of below: + * smsc911x_mac_read(), smsc911x_mac_write() + * smsc911x_phy_read(), smsc911x_phy_write() + */ + spinlock_t phy_lock; + + struct net_device_stats stats; + struct mii_if_info mii; + unsigned int using_extphy; + u32 msg_enable; +#ifdef USE_LED1_WORK_AROUND + unsigned int gpio_setting; + unsigned int gpio_orig_setting; +#endif + struct net_device *netdev; + struct napi_struct napi; + struct timer_list link_poll_timer; + unsigned int stop_link_poll; + + unsigned int software_irq_signal; + +#ifdef USE_PHY_WORK_AROUND +#define MIN_PACKET_SIZE (64) + char loopback_tx_pkt[MIN_PACKET_SIZE]; + char loopback_rx_pkt[MIN_PACKET_SIZE]; + unsigned int resetcount; +#endif + + /* Members for Multicast filter workaround */ + unsigned int multicast_update_pending; + unsigned int set_bits_mask; + unsigned int clear_bits_mask; + unsigned int hashhi; + unsigned int hashlo; +}; + +#if SMSC_CAN_USE_32BIT + +static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg) +{ + return readl(pdata->ioaddr + reg); +} + +static inline void smsc911x_reg_write(u32 val, struct smsc911x_data *pdata, + u32 reg) +{ + writel(val, pdata->ioaddr + reg); +} + +#elif SMSC_CAN_USE_SPI + +static u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg) +{ + u32 reg_val; + unsigned long flags; + + local_irq_save(flags); + reg_val = spi_cpld_read(reg); + local_irq_restore(flags); + + return reg_val; +} + +static void smsc911x_reg_write(u32 val, struct smsc911x_data *pdata, + u32 reg) +{ + unsigned long flags; + + local_irq_save(flags); + spi_cpld_write(reg, val); + local_irq_restore(flags); +} + +#else /* SMSC_CAN_USE_32BIT */ + +static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg) +{ + u32 reg_val; + unsigned long flags; + + /* these two 16-bit reads must be performed consecutively, so must + * not be interrupted by our own ISR (which would start another + * read operation) */ + local_irq_save(flags); + reg_val = ((readw(pdata->ioaddr + reg) & 0xFFFF) | + ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16)); + local_irq_restore(flags); + + return reg_val; +} + +static inline void smsc911x_reg_write(u32 val, struct smsc911x_data *pdata, + u32 reg) +{ + unsigned long flags; + + /* these two 16-bit writes must be performed consecutively, so must + * not be interrupted by our own ISR (which would start another + * read operation) */ + local_irq_save(flags); + writew(val & 0xFFFF, pdata->ioaddr + reg); + writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2); + local_irq_restore(flags); +} + +#endif /* SMSC_CAN_USE_32BIT */ + +/* Writes a packet to the TX_DATA_FIFO */ +static inline void +smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf, + unsigned int wordcount) +{ + while (wordcount--) + smsc911x_reg_write(*buf++, pdata, TX_DATA_FIFO); +} + +/* Reads a packet out of the RX_DATA_FIFO */ +static inline void +smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf, + unsigned int wordcount) +{ + while (wordcount--) + *buf++ = smsc911x_reg_read(pdata, RX_DATA_FIFO); +} + +/* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read + * and smsc911x_mac_write, so assumes phy_lock is held */ +static int smsc911x_mac_notbusy(struct smsc911x_data *pdata) +{ + int i; + u32 val; + + for (i = 0; i < 40; i++) { + val = smsc911x_reg_read(pdata, MAC_CSR_CMD); + if (!(val & MAC_CSR_CMD_CSR_BUSY_)) + return 1; + } + SMSC_WARNING("Timed out waiting for MAC not BUSY. " + "MAC_CSR_CMD: 0x%08X", val); + return 0; +} + +/* Fetches a MAC register value. Assumes phy_lock is acquired */ +static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset) +{ + unsigned int temp; + +#ifdef CONFIG_DEBUG_SPINLOCK + if (!spin_is_locked(&pdata->phy_lock)) + SMSC_WARNING("phy_lock not held"); +#endif /* CONFIG_DEBUG_SPINLOCK */ + + temp = smsc911x_reg_read(pdata, MAC_CSR_CMD); + if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) { + SMSC_WARNING("smsc911x_mac_read failed, MAC busy at entry"); + return 0xFFFFFFFF; + } + + /* Send the MAC cmd */ + smsc911x_reg_write(((offset & 0xFF) | MAC_CSR_CMD_CSR_BUSY_ + | MAC_CSR_CMD_R_NOT_W_), pdata, MAC_CSR_CMD); + + /* Workaround for hardware read-after-write restriction */ + temp = smsc911x_reg_read(pdata, BYTE_TEST); + + /* Wait for the read to happen */ + if (likely(smsc911x_mac_notbusy(pdata))) + return smsc911x_reg_read(pdata, MAC_CSR_DATA); + + SMSC_WARNING("smsc911x_mac_read failed, MAC busy after read"); + return 0xFFFFFFFF; +} + +/* Set a mac register, phy_lock must be acquired before calling */ +static void smsc911x_mac_write(struct smsc911x_data *pdata, + unsigned int offset, u32 val) +{ + unsigned int temp; + +#ifdef CONFIG_DEBUG_SPINLOCK + if (!spin_is_locked(&pdata->phy_lock)) + SMSC_WARNING("phy_lock not held"); +#endif /* CONFIG_DEBUG_SPINLOCK */ + + temp = smsc911x_reg_read(pdata, MAC_CSR_CMD); + if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) { + SMSC_WARNING("smsc911x_mac_write failed, MAC busy at entry"); + return; + } + + /* Send data to write */ + smsc911x_reg_write(val, pdata, MAC_CSR_DATA); + + /* Write the actual data */ + smsc911x_reg_write(((offset & 0xFF) | MAC_CSR_CMD_CSR_BUSY_), pdata, + MAC_CSR_CMD); + + /* Workaround for hardware read-after-write restriction */ + temp = smsc911x_reg_read(pdata, BYTE_TEST); + + /* Wait for the write to complete */ + if (likely(smsc911x_mac_notbusy(pdata))) + return; + + SMSC_WARNING("smsc911x_mac_write failed, MAC busy after write"); +} + +/* Gets a phy register, phy_lock must be acquired before calling */ +static u16 smsc911x_phy_read(struct smsc911x_data *pdata, unsigned int index) +{ + unsigned int addr; + int i; + +#ifdef CONFIG_DEBUG_SPINLOCK + if (!spin_is_locked(&pdata->phy_lock)) + SMSC_WARNING("phy_lock not held"); +#endif /* CONFIG_DEBUG_SPINLOCK */ + + /* Confirm MII not busy */ + if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { + SMSC_WARNING("MII is busy in smsc911x_phy_read???"); + return 0; + } + + /* Set the address, index & direction (read from PHY) */ + addr = (((pdata->mii.phy_id) & 0x1F) << 11) + | ((index & 0x1F) << 6); + smsc911x_mac_write(pdata, MII_ACC, addr); + + /* Wait for read to complete w/ timeout */ + for (i = 0; i < 100; i++) { + /* See if MII is finished yet */ + if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { + return smsc911x_mac_read(pdata, MII_DATA); + } + } + SMSC_WARNING("Timed out waiting for MII write to finish"); + return 0xFFFF; +} + +/* Sets a phy register, phy_lock must be acquired before calling */ +static void smsc911x_phy_write(struct smsc911x_data *pdata, + unsigned int index, u16 val) +{ + unsigned int addr; + int i; + +#ifdef CONFIG_DEBUG_SPINLOCK + if (!spin_is_locked(&pdata->phy_lock)) + SMSC_WARNING("phy_lock not held"); +#endif /* CONFIG_DEBUG_SPINLOCK */ + + /* Confirm MII not busy */ + if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { + SMSC_WARNING("MII is busy in smsc911x_write_phy???"); + return; + } + + /* Put the data to write in the MAC */ + smsc911x_mac_write(pdata, MII_DATA, val); + + /* Set the address, index & direction (write to PHY) */ + addr = (((pdata->mii.phy_id) & 0x1F) << 11) | + ((index & 0x1F) << 6) | MII_ACC_MII_WRITE_; + smsc911x_mac_write(pdata, MII_ACC, addr); + + /* Wait for write to complete w/ timeout */ + for (i = 0; i < 100; i++) { + /* See if MII is finished yet */ + if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) + return; + } + SMSC_WARNING("Timed out waiting for MII write to finish"); +} + +static int smsc911x_mdio_read(struct net_device *dev, int phy_id, int location) +{ + struct smsc911x_data *pdata = netdev_priv(dev); + unsigned long flags; + int reg; + + spin_lock_irqsave(&pdata->phy_lock, flags); + reg = smsc911x_phy_read(pdata, location); + spin_unlock_irqrestore(&pdata->phy_lock, flags); + + return reg; +} + +static void smsc911x_mdio_write(struct net_device *dev, int phy_id, + int location, int val) +{ + struct smsc911x_data *pdata = netdev_priv(dev); + unsigned long flags; + + spin_lock_irqsave(&pdata->phy_lock, flags); + smsc911x_phy_write(pdata, location, val); + spin_unlock_irqrestore(&pdata->phy_lock, flags); +} + +/* Autodetects and initialises external phy for SMSC9115 and SMSC9117 flavors. + * If something goes wrong, returns -ENODEV to revert back to internal phy. + * Performed at initialisation only, so interrupts are enabled */ +static int smsc911x_phy_initialise_external(struct smsc911x_data *pdata) +{ + unsigned int address; + unsigned int hwcfg; + unsigned int phyid1; + unsigned int phyid2; + + hwcfg = smsc911x_reg_read(pdata, HW_CFG); + + /* External phy is requested, supported, and detected */ + if (hwcfg & HW_CFG_EXT_PHY_DET_) { + + /* Attempt to switch to external phy for auto-detecting + * its address. Assuming tx and rx are stopped because + * smsc911x_phy_initialise is called before + * smsc911x_rx_initialise and tx_initialise. + */ + + /* Disable phy clocks to the MAC */ + hwcfg &= (~HW_CFG_PHY_CLK_SEL_); + hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_; + smsc911x_reg_write(hwcfg, pdata, HW_CFG); + udelay(10); /* Enough time for clocks to stop */ + + /* Switch to external phy */ + hwcfg |= HW_CFG_EXT_PHY_EN_; + smsc911x_reg_write(hwcfg, pdata, HW_CFG); + + /* Enable phy clocks to the MAC */ + hwcfg &= (~HW_CFG_PHY_CLK_SEL_); + hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_; + smsc911x_reg_write(hwcfg, pdata, HW_CFG); + udelay(10); /* Enough time for clocks to restart */ + + hwcfg |= HW_CFG_SMI_SEL_; + smsc911x_reg_write(hwcfg, pdata, HW_CFG); + + /* Auto-detect PHY */ + spin_lock_irq(&pdata->phy_lock); + for (address = 0; address <= 31; address++) { + pdata->mii.phy_id = address; + phyid1 = smsc911x_phy_read(pdata, MII_PHYSID1); + phyid2 = smsc911x_phy_read(pdata, MII_PHYSID2); + if ((phyid1 != 0xFFFFU) || (phyid2 != 0xFFFFU)) { + SMSC_TRACE("Detected PHY at address = " + "0x%02X = %d", address, address); + break; + } + } + spin_unlock_irq(&pdata->phy_lock); + + if ((phyid1 == 0xFFFFU) && (phyid2 == 0xFFFFU)) { + SMSC_WARNING("External PHY is not accessable, " + "using internal PHY instead"); + /* Revert back to internal phy settings. */ + + /* Disable phy clocks to the MAC */ + hwcfg &= (~HW_CFG_PHY_CLK_SEL_); + hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_; + smsc911x_reg_write(hwcfg, pdata, HW_CFG); + udelay(10); /* Enough time for clocks to stop */ + + /* Switch to internal phy */ + hwcfg &= (~HW_CFG_EXT_PHY_EN_); + smsc911x_reg_write(hwcfg, pdata, HW_CFG); + + /* Enable phy clocks to the MAC */ + hwcfg &= (~HW_CFG_PHY_CLK_SEL_); + hwcfg |= HW_CFG_PHY_CLK_SEL_INT_PHY_; + smsc911x_reg_write(hwcfg, pdata, HW_CFG); + udelay(10); /* Enough time for clocks to restart */ + + hwcfg &= (~HW_CFG_SMI_SEL_); + smsc911x_reg_write(hwcfg, pdata, HW_CFG); + /* Use internal phy */ + return -ENODEV; + } else { + SMSC_TRACE("Successfully switched to external PHY"); + pdata->using_extphy = 1; + } + } else { + SMSC_WARNING("No external PHY detected."); + SMSC_WARNING("Using internal PHY instead."); + /* Use internal phy */ + return -ENODEV; + } + return 0; +} + +/* called by phy_initialise and loopback test */ +static int smsc911x_phy_reset(struct smsc911x_data *pdata) +{ + unsigned int temp; + unsigned int i = 100000; + unsigned long flags; + + SMSC_TRACE("Performing PHY BCR Reset"); + spin_lock_irqsave(&pdata->phy_lock, flags); + smsc911x_phy_write(pdata, MII_BMCR, BMCR_RESET); + do { + udelay(10); + temp = smsc911x_phy_read(pdata, MII_BMCR); + } while ((i--) && (temp & BMCR_RESET)); + spin_unlock_irqrestore(&pdata->phy_lock, flags); + + if (temp & BMCR_RESET) { + SMSC_WARNING("PHY reset failed to complete."); + return 0; + } + /* Extra delay required because the phy may not be completed with + * its reset when BMCR_RESET is cleared. Specs say 256 uS is + * enough delay but using 1ms here to be safe + */ + msleep(1); + + return 1; +} + +/* Fetches a tx status out of the status fifo */ +static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata) +{ + unsigned int result = + smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_; + + if (result != 0) + result = smsc911x_reg_read(pdata, TX_STATUS_FIFO); + + return result; +} + +/* Fetches the next rx status */ +static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata) +{ + unsigned int result = + smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_; + + if (result != 0) + result = smsc911x_reg_read(pdata, RX_STATUS_FIFO); + + return result; +} + +#ifdef USE_PHY_WORK_AROUND +static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata) +{ + unsigned int tries; + u32 wrsz; + u32 rdsz; + u32 bufp; + + for (tries = 0; tries < 10; tries++) { + unsigned int txcmd_a; + unsigned int txcmd_b; + unsigned int status; + unsigned int pktlength; + unsigned int i; + + /* Zero-out rx packet memory */ + memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE); + + /* Write tx packet to 118 */ + txcmd_a = (((unsigned int)pdata->loopback_tx_pkt) + & 0x03) << 16; + txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; + txcmd_a |= MIN_PACKET_SIZE; + + txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE; + + smsc911x_reg_write(txcmd_a, pdata, TX_DATA_FIFO); + smsc911x_reg_write(txcmd_b, pdata, TX_DATA_FIFO); + + bufp = ((u32) pdata->loopback_tx_pkt) & 0xFFFFFFFC; + wrsz = MIN_PACKET_SIZE + 3; + wrsz += (((u32) pdata->loopback_tx_pkt) & 0x3); + wrsz >>= 2; + + smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz); + + /* Wait till transmit is done */ + i = 60; + do { + udelay(5); + status = smsc911x_tx_get_txstatus(pdata); + } while ((i--) && (!status)); + + if (!status) { + SMSC_WARNING("Failed to transmit during loopback test"); + continue; + } + if (status & TX_STS_ES_) { + SMSC_WARNING("Transmit encountered errors during " + "loopback test"); + continue; + } + + /* Wait till receive is done */ + i = 60; + do { + udelay(5); + status = smsc911x_rx_get_rxstatus(pdata); + } while ((i--) && (!status)); + + if (!status) { + SMSC_WARNING("Failed to receive during loopback test"); + continue; + } + if (status & RX_STS_ES_) { + SMSC_WARNING("Receive encountered errors during " + "loopback test"); + continue; + } + + pktlength = ((status & 0x3FFF0000UL) >> 16); + bufp = (u32)pdata->loopback_rx_pkt; + rdsz = pktlength + 3; + rdsz += ((u32)pdata->loopback_rx_pkt) & 0x3; + rdsz >>= 2; + + smsc911x_rx_readfifo(pdata, (unsigned int *)bufp, rdsz); + + if (pktlength != (MIN_PACKET_SIZE + 4)) { + SMSC_WARNING("Unexpected packet size during " + "loop back test, size=%d, " + "will retry", pktlength); + } else { + unsigned int j; + int mismatch = 0; + for (j = 0; j < MIN_PACKET_SIZE; j++) { + if (pdata->loopback_tx_pkt[j] + != pdata->loopback_rx_pkt[j]) { + mismatch = 1; + break; + } + } + if (!mismatch) { + SMSC_TRACE("Successfully verified " + "loopback packet"); + return 1; + } else { + SMSC_WARNING("Data miss match during " + "loop back test, will retry."); + } + } + } + + return 0; +} + +static int smsc911x_phy_loopbacktest(struct smsc911x_data *pdata) +{ + int result = 0; + unsigned int i; + unsigned int val; + unsigned long flags; + + /* Initialise tx packet */ + for (i = 0; i < 6; i++) { + /* Use broadcast destination address */ + pdata->loopback_tx_pkt[i] = (char)0xFF; + } + + for (i = 6; i < 12; i++) { + /* Use incrementing source address */ + pdata->loopback_tx_pkt[i] = (char)i; + } + + /* Set length type field */ + pdata->loopback_tx_pkt[12] = 0x00; + pdata->loopback_tx_pkt[13] = 0x00; + for (i = 14; i < MIN_PACKET_SIZE; i++) { + pdata->loopback_tx_pkt[i] = (char)i; + } + + val = smsc911x_reg_read(pdata, HW_CFG); + val &= HW_CFG_TX_FIF_SZ_; + val |= HW_CFG_SF_; + smsc911x_reg_write(val, pdata, HW_CFG); + + smsc911x_reg_write(TX_CFG_TX_ON_, pdata, TX_CFG); + smsc911x_reg_write((((unsigned int)pdata->loopback_rx_pkt) + & 0x03) << 8, pdata, RX_CFG); + + for (i = 0; i < 10; i++) { + /* Set PHY to 10/FD, no ANEG, and loopback mode */ + spin_lock_irqsave(&pdata->phy_lock, flags); + smsc911x_phy_write(pdata, MII_BMCR, 0x4100); + + /* Enable MAC tx/rx, FD */ + smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_ + | MAC_CR_TXEN_ | MAC_CR_RXEN_); + spin_unlock_irqrestore(&pdata->phy_lock, flags); + + if (smsc911x_phy_check_loopbackpkt(pdata)) { + result = 1; + break; + } + pdata->resetcount++; + + /* Disable MAC rx */ + spin_lock_irqsave(&pdata->phy_lock, flags); + smsc911x_mac_write(pdata, MAC_CR, 0); + spin_unlock_irqrestore(&pdata->phy_lock, flags); + + smsc911x_phy_reset(pdata); + } + + /* Disable MAC */ + spin_lock_irqsave(&pdata->phy_lock, flags); + smsc911x_mac_write(pdata, MAC_CR, 0); + + /* Cancel PHY loopback mode */ + smsc911x_phy_write(pdata, MII_BMCR, 0); + spin_unlock_irqrestore(&pdata->phy_lock, flags); + + smsc911x_reg_write(0, pdata, TX_CFG); + smsc911x_reg_write(0, pdata, RX_CFG); + + return result; +} +#endif /* USE_PHY_WORK_AROUND */ + +/* assumes phy_lock is held */ +static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata) +{ + unsigned int temp; + + if (pdata->mii.full_duplex) { + unsigned int phy_adv; + unsigned int phy_lpa; + phy_adv = smsc911x_phy_read(pdata, MII_ADVERTISE); + phy_lpa = smsc911x_phy_read(pdata, MII_LPA); + if (phy_adv & phy_lpa & LPA_PAUSE_CAP) { + /* Both ends support symmetric pause, enable + * PAUSE receive and transmit */ + smsc911x_mac_write(pdata, FLOW, 0xFFFF0002); + temp = smsc911x_reg_read(pdata, AFC_CFG); + temp |= 0xF; + smsc911x_reg_write(temp, pdata, AFC_CFG); + } else if (((phy_adv & ADVERTISE_PAUSE_ALL) == + ADVERTISE_PAUSE_ALL) && + ((phy_lpa & LPA_PAUSE_ALL) == LPA_PAUSE_ASYM)) { + /* We support symmetric and asym pause, the + * other end only supports asym, Enable PAUSE + * receive, disable PAUSE transmit */ + smsc911x_mac_write(pdata, FLOW, 0xFFFF0002); + temp = smsc911x_reg_read(pdata, AFC_CFG); + temp &= ~0xF; + smsc911x_reg_write(temp, pdata, AFC_CFG); + } else { + /* Disable PAUSE receive and transmit */ + smsc911x_mac_write(pdata, FLOW, 0); + temp = smsc911x_reg_read(pdata, AFC_CFG); + temp &= ~0xF; + smsc911x_reg_write(temp, pdata, AFC_CFG); + } + } else { + smsc911x_mac_write(pdata, FLOW, 0); + temp = smsc911x_reg_read(pdata, AFC_CFG); + temp |= 0xF; + smsc911x_reg_write(temp, pdata, AFC_CFG); + } +} + +/* Update link mode if any thing has changed */ +static void smsc911x_phy_update_linkmode(struct net_device *dev, int init) +{ + struct smsc911x_data *pdata = netdev_priv(dev); + unsigned long flags; + + if (mii_check_media(&pdata->mii, netif_msg_link(pdata), init)) { + /* duplex state has changed */ + unsigned int mac_cr; + + spin_lock_irqsave(&pdata->phy_lock, flags); + mac_cr = smsc911x_mac_read(pdata, MAC_CR); + if (pdata->mii.full_duplex) { + SMSC_TRACE("configuring for full duplex mode"); + mac_cr |= MAC_CR_FDPX_; + } else { + SMSC_TRACE("configuring for half duplex mode"); + mac_cr &= ~MAC_CR_FDPX_; + } + smsc911x_mac_write(pdata, MAC_CR, mac_cr); + + smsc911x_phy_update_flowcontrol(pdata); + + spin_unlock_irqrestore(&pdata->phy_lock, flags); + } +#ifdef USE_LED1_WORK_AROUND + if (netif_carrier_ok(dev)) { + if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) && + (!pdata->using_extphy)) { + /* Restore orginal GPIO configuration */ + pdata->gpio_setting = pdata->gpio_orig_setting; + smsc911x_reg_write(pdata->gpio_setting, pdata, + GPIO_CFG); + } + } else { + /* Check global setting that LED1 + * usage is 10/100 indicator */ + pdata->gpio_setting = smsc911x_reg_read(pdata, GPIO_CFG); + if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) + && (!pdata->using_extphy)) { + /* Force 10/100 LED off, after saving + * orginal GPIO configuration */ + pdata->gpio_orig_setting = pdata->gpio_setting; + + pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_; + pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_ + | GPIO_CFG_GPIODIR0_ + | GPIO_CFG_GPIOD0_); + smsc911x_reg_write(pdata->gpio_setting, pdata, + GPIO_CFG); + } + } +#endif /* USE_LED1_WORK_AROUND */ +} + +/* Entry point for the link poller */ +static void smsc911x_phy_checklink(unsigned long ptr) +{ + struct net_device *dev = (struct net_device *)ptr; + struct smsc911x_data *pdata = netdev_priv(dev); + + smsc911x_phy_update_linkmode(dev, 0); + + if (!(pdata->stop_link_poll)) { + pdata->link_poll_timer.expires = jiffies + 2 * HZ; + add_timer(&pdata->link_poll_timer); + } else { + pdata->stop_link_poll = 0; + } +} + +/* Initialises the PHY layer. Called at initialisation by open() so + * interrupts are enabled */ +static int smsc911x_phy_initialise(struct net_device *dev) +{ + struct smsc911x_data *pdata = netdev_priv(dev); + unsigned int phyid1 = 0; + unsigned int phyid2 = 0; + unsigned int temp; + + pdata->using_extphy = 0; + + switch (pdata->idrev & 0xFFFF0000) { + case 0x01170000: + case 0x01150000: + /* External PHY supported, try to autodetect */ + if (smsc911x_phy_initialise_external(pdata) < 0) { + SMSC_TRACE("External PHY is not detected, using " + "internal PHY instead"); + pdata->mii.phy_id = 1; + } + break; + default: + SMSC_TRACE("External PHY is not supported, using internal PHY " + "instead"); + pdata->mii.phy_id = 1; + break; + } + + spin_lock_irq(&pdata->phy_lock); + phyid1 = smsc911x_phy_read(pdata, MII_PHYSID1); + phyid2 = smsc911x_phy_read(pdata, MII_PHYSID2); + spin_unlock_irq(&pdata->phy_lock); + + if ((phyid1 == 0xFFFF) && (phyid2 == 0xFFFF)) { + SMSC_WARNING("Internal PHY not detected!"); + return 0; + } + + /* Reset the phy */ + if (!smsc911x_phy_reset(pdata)) { + SMSC_WARNING("PHY reset failed to complete."); + return 0; + } +#ifdef USE_PHY_WORK_AROUND + if (!smsc911x_phy_loopbacktest(pdata)) { + SMSC_WARNING("Failed Loop Back Test"); + return 0; + } else { + SMSC_TRACE("Passed Loop Back Test"); + } +#endif /* USE_PHY_WORK_AROUND */ + + /* Advertise all speeds and pause capabilities */ + spin_lock_irq(&pdata->phy_lock); + temp = smsc911x_phy_read(pdata, MII_ADVERTISE); + temp |= (ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); + smsc911x_phy_write(pdata, MII_ADVERTISE, temp); + pdata->mii.advertising = temp; + + if (!pdata->using_extphy) { + /* using internal phy, enable PHY interrupts */ + smsc911x_phy_read(pdata, MII_INTSTS); + smsc911x_phy_write(pdata, MII_INTMSK, PHY_INTMSK_DEFAULT_); + } + + /* begin to establish link */ + smsc911x_phy_write(pdata, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); + spin_unlock_irq(&pdata->phy_lock); + + smsc911x_phy_update_linkmode(dev, 1); + + setup_timer(&pdata->link_poll_timer, smsc911x_phy_checklink, + (unsigned long)dev); + pdata->link_poll_timer.expires = jiffies + 2 * HZ; + add_timer(&pdata->link_poll_timer); + + SMSC_TRACE("phy initialised succesfully"); + return 1; +} + +/* Gets the number of tx statuses in the fifo */ +static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata) +{ + unsigned int result = (smsc911x_reg_read(pdata, TX_FIFO_INF) + & TX_FIFO_INF_TSUSED_) >> 16; + return result; +} + +/* Reads tx statuses and increments counters where necessary */ +static void smsc911x_tx_update_txcounters(struct smsc911x_data *pdata) +{ + unsigned int tx_stat; + + while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) { + if (unlikely(tx_stat & 0x80000000)) { + /* In this driver the packet tag is used as the packet + * length. Since a packet length can never reach the + * size of 0x8000, this bit is reserved. It is worth + * noting that the "reserved bit" in the warning above + * does not reference a hardware defined reserved bit + * but rather a driver defined one. + */ + SMSC_WARNING("Packet tag reserved bit is high"); + } else { + if (unlikely(tx_stat & 0x00008000)) { + pdata->stats.tx_errors++; + } else { + pdata->stats.tx_packets++; + pdata->stats.tx_bytes += (tx_stat >> 16); + } + if (unlikely(tx_stat & 0x00000100)) { + pdata->stats.collisions += 16; + pdata->stats.tx_aborted_errors += 1; + } else { + pdata->stats.collisions += + ((tx_stat >> 3) & 0xF); + } + if (unlikely(tx_stat & 0x00000800)) { + pdata->stats.tx_carrier_errors += 1; + } + if (unlikely(tx_stat & 0x00000200)) { + pdata->stats.collisions++; + pdata->stats.tx_aborted_errors++; + } + } + } +} + +/* Increments the Rx error counters */ +static void +smsc911x_rx_counterrors(struct smsc911x_data *pdata, unsigned int rxstat) +{ + int crc_err = 0; + + if (unlikely(rxstat & 0x00008000)) { + pdata->stats.rx_errors++; + if (unlikely(rxstat & 0x00000002)) { + pdata->stats.rx_crc_errors++; + crc_err = 1; + } + } + if (likely(!crc_err)) { + if (unlikely((rxstat & 0x00001020) == 0x00001020)) { + /* Frame type indicates length, + * and length error is set */ + pdata->stats.rx_length_errors++; + } + if (rxstat & RX_STS_MCAST_) + pdata->stats.multicast++; + } +} + +/* Quickly dumps bad packets */ +static void +smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes) +{ + unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2; + + if (likely(pktwords >= 4)) { + unsigned int timeout = 500; + unsigned int val; + smsc911x_reg_write(RX_DP_CTRL_RX_FFWD_, pdata, RX_DP_CTRL); + do { + udelay(1); + val = smsc911x_reg_read(pdata, RX_DP_CTRL); + } while (timeout-- && (val & RX_DP_CTRL_RX_FFWD_)); + + if (unlikely(timeout == 0)) + SMSC_WARNING("Timed out waiting for RX FFWD " + "to finish, RX_DP_CTRL: 0x%08X", val); + } else { + unsigned int temp; + while (pktwords--) + temp = smsc911x_reg_read(pdata, RX_DATA_FIFO); + } +} + +/* NAPI poll function */ +static int smsc911x_poll(struct napi_struct *napi, int budget) +{ + struct smsc911x_data *pdata = container_of(napi, struct smsc911x_data, napi); + struct net_device *dev = pdata->netdev; + int npackets = 0; + + while (npackets < budget) { + unsigned int pktlength; + unsigned int pktwords; + unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata); + + /* break out of while loop if there are no more packets waiting */ + if (!rxstat) + break; + + pktlength = ((rxstat & 0x3FFF0000) >> 16); + pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2; + smsc911x_rx_counterrors(pdata, rxstat); + + if (likely((rxstat & RX_STS_ES_) == 0)) { + struct sk_buff *skb; + skb = dev_alloc_skb(pktlength + NET_IP_ALIGN); + if (likely(skb)) { + skb->data = skb->head; + skb->tail = skb->head; + /* Align IP on 16B boundary */ + skb_reserve(skb, NET_IP_ALIGN); + skb_put(skb, pktlength - 4); + smsc911x_rx_readfifo(pdata, + (unsigned int *)skb->head, + pktwords); + skb->dev = dev; + skb->protocol = eth_type_trans(skb, dev); + skb->ip_summed = CHECKSUM_NONE; + netif_receive_skb(skb); + + /* Update counters */ + pdata->stats.rx_packets++; + pdata->stats.rx_bytes += (pktlength - 4); + dev->last_rx = jiffies; + npackets++; + continue; + } else { + SMSC_WARNING("Unable to allocate sk_buff " + "for rx packet, in PIO path"); + pdata->stats.rx_dropped++; + } + } + /* At this point, the packet is to be read out + * of the fifo and discarded */ + smsc911x_rx_fastforward(pdata, pktlength); + } + + pdata->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP); + smsc911x_reg_write(INT_STS_RSFL_, pdata, INT_STS); + + if (npackets < budget) { + unsigned int temp; + /* We processed all packets available. Tell NAPI it can + * stop polling then re-enable rx interrupts */ + netif_rx_complete(dev, napi); + temp = smsc911x_reg_read(pdata, INT_EN); + temp |= INT_EN_RSFL_EN_; + smsc911x_reg_write(temp, pdata, INT_EN); + } + + /* There are still packets waiting */ + return npackets; +} + +/* Returns hash bit number for given MAC address + * Example: + * 01 00 5E 00 00 01 -> returns bit number 31 */ +static unsigned int smsc911x_hash(char addr[ETH_ALEN]) +{ + unsigned int crc; + unsigned int result; + + crc = ether_crc(ETH_ALEN, addr); + result = (crc >> 26) & 0x3f; + + return result; +} + +static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata) +{ + /* Performs the multicast & mac_cr update. This is called when + * safe on the current hardware, and with the phy_lock held */ + unsigned int mac_cr = smsc911x_mac_read(pdata, MAC_CR); + mac_cr |= pdata->set_bits_mask; + mac_cr &= ~(pdata->clear_bits_mask); + smsc911x_mac_write(pdata, MAC_CR, mac_cr); + smsc911x_mac_write(pdata, HASHH, pdata->hashhi); + smsc911x_mac_write(pdata, HASHL, pdata->hashlo); + SMSC_TRACE("maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X", mac_cr, + pdata->hashhi, pdata->hashlo); +} + +static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata) +{ + unsigned int mac_cr; + + /* This function is only called for older LAN911x devices + * (revA or revB), where MAC_CR, HASHH and HASHL should not + * be modified during Rx - newer devices immediately update the + * registers. + * + * This is called from interrupt context */ + + spin_lock(&pdata->phy_lock); + + /* Check Rx has stopped */ + if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_) + SMSC_WARNING("Rx not stopped\n"); + + /* Perform the update - safe to do now Rx has stopped */ + smsc911x_rx_multicast_update(pdata); + + /* Re-enable Rx */ + mac_cr = smsc911x_mac_read(pdata, MAC_CR); + mac_cr |= MAC_CR_RXEN_; + smsc911x_mac_write(pdata, MAC_CR, mac_cr); + + pdata->multicast_update_pending = 0; + + spin_unlock(&pdata->phy_lock); +} + +/* Sets the device MAC address to dev_addr, called with phy_lock held */ +static void +smsc911x_set_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6]) +{ + u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4]; + u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | + (dev_addr[1] << 8) | dev_addr[0]; + + smsc911x_mac_write(pdata, ADDRH, mac_high16); + smsc911x_mac_write(pdata, ADDRL, mac_low32); +} + +static int smsc911x_open(struct net_device *dev) +{ + struct smsc911x_data *pdata = netdev_priv(dev); + unsigned int timeout; + unsigned int temp; + unsigned int intcfg; + + spin_lock_init(&pdata->phy_lock); + + /* Reset the LAN911x */ + smsc911x_reg_write(HW_CFG_SRST_, pdata, HW_CFG); + timeout = 10; + do { + udelay(10); + temp = smsc911x_reg_read(pdata, HW_CFG); + } while ((--timeout) && (temp & HW_CFG_SRST_)); + + if (unlikely(temp & HW_CFG_SRST_)) { + SMSC_WARNING("Failed to complete reset"); + return -ENODEV; + } + + smsc911x_reg_write(0x00050000, pdata, HW_CFG); + smsc911x_reg_write(0x006E3740, pdata, AFC_CFG); + + /* Make sure EEPROM has finished loading before setting GPIO_CFG */ + timeout = 50; + while ((timeout--) && + (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_)) { + udelay(10); + } + + if (unlikely(timeout == 0)) { + SMSC_WARNING("Timed out waiting for EEPROM " + "busy bit to clear"); + } +#if USE_DEBUG >= 1 + smsc911x_reg_write(0x00670700, pdata, GPIO_CFG); +#else + smsc911x_reg_write(0x70070000, pdata, GPIO_CFG); +#endif + + /* Initialise irqs, but leave all sources disabled */ + smsc911x_reg_write(0, pdata, INT_EN); + smsc911x_reg_write(0xFFFFFFFF, pdata, INT_STS); + + /* Set interrupt deassertion to 100uS */ + intcfg = ((10 << 24) | INT_CFG_IRQ_EN_); + + if (pdata->irq_polarity) { + SMSC_TRACE("irq polarity: active high"); + intcfg |= INT_CFG_IRQ_POL_; + } else { + SMSC_TRACE("irq polarity: active low"); + } + + if (pdata->irq_type) { + SMSC_TRACE("irq type: push-pull"); + intcfg |= INT_CFG_IRQ_TYPE_; + } else { + SMSC_TRACE("irq type: open drain"); + } + + smsc911x_reg_write(intcfg, pdata, INT_CFG); + + SMSC_TRACE("Testing irq handler using IRQ %d", dev->irq); + pdata->software_irq_signal = 0; + smp_wmb(); + + temp = smsc911x_reg_read(pdata, INT_EN); + temp |= INT_EN_SW_INT_EN_; + smsc911x_reg_write(temp, pdata, INT_EN); + + timeout = 1000; + while (timeout--) { + smp_rmb(); + if (pdata->software_irq_signal) + break; + msleep(1); + } + + if (!pdata->software_irq_signal) { + printk(KERN_WARNING "%s: ISR failed signaling test (IRQ %d)\n", + dev->name, dev->irq); + return -ENODEV; + } + SMSC_TRACE("IRQ handler passed test using IRQ %d", dev->irq); + + printk(KERN_INFO "%s: SMSC911x/921x identified at %#08lx, IRQ: %d\n", + dev->name, (unsigned long)pdata->ioaddr, dev->irq); + + netif_carrier_off(dev); + + if (!smsc911x_phy_initialise(dev)) { + SMSC_WARNING("Failed to initialize PHY"); + return -ENODEV; + } + + smsc911x_set_mac_address(pdata, dev->dev_addr); + + temp = smsc911x_reg_read(pdata, HW_CFG); + temp &= HW_CFG_TX_FIF_SZ_; + temp |= HW_CFG_SF_; + smsc911x_reg_write(temp, pdata, HW_CFG); + + temp = smsc911x_reg_read(pdata, FIFO_INT); + temp |= FIFO_INT_TX_AVAIL_LEVEL_; + temp &= ~(FIFO_INT_RX_STS_LEVEL_); + smsc911x_reg_write(temp, pdata, FIFO_INT); + + /* set RX Data offset to 2 bytes for alignment */ + smsc911x_reg_write((2 << 8), pdata, RX_CFG); + + napi_enable(&pdata->napi); + + temp = smsc911x_reg_read(pdata, INT_EN); + temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_PHY_INT_EN_); + smsc911x_reg_write(temp, pdata, INT_EN); + + spin_lock_irq(&pdata->phy_lock); + temp = smsc911x_mac_read(pdata, MAC_CR); + temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_); + smsc911x_mac_write(pdata, MAC_CR, temp); + spin_unlock_irq(&pdata->phy_lock); + + smsc911x_reg_write(TX_CFG_TX_ON_, pdata, TX_CFG); + + netif_start_queue(dev); + return 0; +} + +/* Entry point for stopping the interface */ +static int smsc911x_stop(struct net_device *dev) +{ + struct smsc911x_data *pdata = netdev_priv(dev); + + napi_disable(&pdata->napi); + + pdata->stop_link_poll = 1; + del_timer_sync(&pdata->link_poll_timer); + + smsc911x_reg_write((smsc911x_reg_read(pdata, INT_CFG) & + (~INT_CFG_IRQ_EN_)), pdata, INT_CFG); + netif_stop_queue(dev); + + /* At this point all Rx and Tx activity is stopped */ + pdata->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP); + smsc911x_tx_update_txcounters(pdata); + + SMSC_TRACE("Interface stopped"); + return 0; +} + +/* Entry point for transmitting a packet */ +static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct smsc911x_data *pdata = netdev_priv(dev); + unsigned int freespace; + unsigned int tx_cmd_a; + unsigned int tx_cmd_b; + unsigned int temp; + u32 wrsz; + u32 bufp; + + freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_; + + if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD)) + SMSC_WARNING("Tx data fifo low, space available: %d", + freespace); + + /* Word alignment adjustment */ + tx_cmd_a = ((((unsigned int)(skb->data)) & 0x03) << 16); + tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; + tx_cmd_a |= (unsigned int)skb->len; + + tx_cmd_b = ((unsigned int)skb->len) << 16; + tx_cmd_b |= (unsigned int)skb->len; + + smsc911x_reg_write(tx_cmd_a, pdata, TX_DATA_FIFO); + smsc911x_reg_write(tx_cmd_b, pdata, TX_DATA_FIFO); + + bufp = ((u32)skb->data) & 0xFFFFFFFC; + wrsz = (u32)skb->len + 3; + wrsz += ((u32)skb->data) & 0x3; + wrsz >>= 2; + + smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz); + freespace -= (skb->len + 32); + dev_kfree_skb(skb); + dev->trans_start = jiffies; + + if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30)) + smsc911x_tx_update_txcounters(pdata); + + if (freespace < TX_FIFO_LOW_THRESHOLD) { + netif_stop_queue(dev); + temp = smsc911x_reg_read(pdata, FIFO_INT); + temp &= 0x00FFFFFF; + temp |= 0x32000000; + smsc911x_reg_write(temp, pdata, FIFO_INT); + } + + return NETDEV_TX_OK; +} + +/* Entry point for getting status counters */ +static struct net_device_stats *smsc911x_get_stats(struct net_device *dev) +{ + struct smsc911x_data *pdata = netdev_priv(dev); + smsc911x_tx_update_txcounters(pdata); + pdata->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP); + return &pdata->stats; +} + +/* Entry point for setting addressing modes */ +static void smsc911x_set_multicast_list(struct net_device *dev) +{ + struct smsc911x_data *pdata = netdev_priv(dev); + unsigned long flags; + + if (dev->flags & IFF_PROMISC) { + /* Enabling promiscuous mode */ + pdata->set_bits_mask = MAC_CR_PRMS_; + pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_); + pdata->hashhi = 0; + pdata->hashlo = 0; + } else if (dev->flags & IFF_ALLMULTI) { + /* Enabling all multicast mode */ + pdata->set_bits_mask = MAC_CR_MCPAS_; + pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_); + pdata->hashhi = 0; + pdata->hashlo = 0; + } else if (dev->mc_count > 0) { + /* Enabling specific multicast addresses */ + unsigned int hash_high = 0; + unsigned int hash_low = 0; + unsigned int count = 0; + struct dev_mc_list *mc_list = dev->mc_list; + + pdata->set_bits_mask = MAC_CR_HPFILT_; + pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_); + + while (mc_list) { + count++; + if ((mc_list->dmi_addrlen) == ETH_ALEN) { + unsigned int bitnum = + smsc911x_hash(mc_list->dmi_addr); + unsigned int mask = 0x01 << (bitnum & 0x1F); + if (bitnum & 0x20) + hash_high |= mask; + else + hash_low |= mask; + } else { + SMSC_WARNING("dmi_addrlen != 6"); + } + mc_list = mc_list->next; + } + if (count != (unsigned int)dev->mc_count) + SMSC_WARNING("mc_count != dev->mc_count"); + + pdata->hashhi = hash_high; + pdata->hashlo = hash_low; + } else { + /* Enabling local MAC address only */ + pdata->set_bits_mask = 0; + pdata->clear_bits_mask = + (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); + pdata->hashhi = 0; + pdata->hashlo = 0; + } + + spin_lock_irqsave(&pdata->phy_lock, flags); + + if (pdata->generation <= 1) { + /* Older hardware revision - cannot change these flags while + * receiving data */ + if (!pdata->multicast_update_pending) { + unsigned int temp; + SMSC_TRACE("scheduling mcast update"); + pdata->multicast_update_pending = 1; + + /* Request the hardware to stop, then perform the + * update when we get an RX_STOP interrupt */ + smsc911x_reg_write(INT_STS_RXSTOP_INT_, pdata, INT_STS); + temp = smsc911x_reg_read(pdata, INT_EN); + temp |= INT_EN_RXSTOP_INT_EN_; + smsc911x_reg_write(temp, pdata, INT_EN); + + temp = smsc911x_mac_read(pdata, MAC_CR); + temp &= ~(MAC_CR_RXEN_); + smsc911x_mac_write(pdata, MAC_CR, temp); + } else { + /* There is another update pending, this should now + * use the newer values */ + } + } else { + /* Newer hardware revision - can write immediately */ + smsc911x_rx_multicast_update(pdata); + } + + spin_unlock_irqrestore(&pdata->phy_lock, flags); +} + +static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id) +{ + struct net_device *dev = dev_id; + struct smsc911x_data *pdata = netdev_priv(dev); + unsigned int intsts; + unsigned int inten; + unsigned int temp; + int serviced = IRQ_NONE; + + intsts = smsc911x_reg_read(pdata, INT_STS); + inten = smsc911x_reg_read(pdata, INT_EN); + + if (unlikely(intsts & inten & INT_STS_SW_INT_)) { + temp = smsc911x_reg_read(pdata, INT_EN); + temp &= (~INT_EN_SW_INT_EN_); + smsc911x_reg_write(temp, pdata, INT_EN); + smsc911x_reg_write(INT_STS_SW_INT_, pdata, INT_STS); + pdata->software_irq_signal = 1; + smp_wmb(); + serviced = IRQ_HANDLED; + } + + if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) { + /* Called when there is a multicast update scheduled and + * it is now safe to complete the update */ + SMSC_TRACE("RX Stop interrupt"); + temp = smsc911x_reg_read(pdata, INT_EN); + temp &= (~INT_EN_RXSTOP_INT_EN_); + smsc911x_reg_write(temp, pdata, INT_EN); + smsc911x_reg_write(INT_STS_RXSTOP_INT_, pdata, INT_STS); + smsc911x_rx_multicast_update_workaround(pdata); + serviced = IRQ_HANDLED; + } + + if (intsts & inten & INT_STS_TDFA_) { + temp = smsc911x_reg_read(pdata, FIFO_INT); + temp |= FIFO_INT_TX_AVAIL_LEVEL_; + smsc911x_reg_write(temp, pdata, FIFO_INT); + smsc911x_reg_write(INT_STS_TDFA_, pdata, INT_STS); + netif_wake_queue(dev); + serviced = IRQ_HANDLED; + } + + if (unlikely(intsts & inten & INT_STS_RXE_)) { + smsc911x_reg_write(INT_STS_RXE_, pdata, INT_STS); + serviced = IRQ_HANDLED; + } + + if (likely(intsts & inten & INT_STS_RSFL_)) { + /* Disable Rx interrupts and schedule NAPI poll */ + temp = smsc911x_reg_read(pdata, INT_EN); + temp &= (~INT_EN_RSFL_EN_); + smsc911x_reg_write(temp, pdata, INT_EN); + netif_rx_schedule(dev, &pdata->napi); + serviced = IRQ_HANDLED; + } + + if (unlikely(intsts & inten & INT_STS_PHY_INT_)) { + smsc911x_reg_write(INT_STS_PHY_INT_, pdata, INT_STS); + spin_lock(&pdata->phy_lock); + temp = smsc911x_phy_read(pdata, MII_INTSTS); + spin_unlock(&pdata->phy_lock); + SMSC_TRACE("PHY interrupt, sts 0x%04X", (u16)temp); + smsc911x_phy_update_linkmode(dev, 0); + serviced = IRQ_HANDLED; + } + return serviced; +} + +#ifdef CONFIG_NET_POLL_CONTROLLER +void smsc911x_poll_controller(struct net_device *dev) +{ + disable_irq(dev->irq); + smsc911x_irqhandler(0, dev); + enable_irq(dev->irq); +} +#endif /* CONFIG_NET_POLL_CONTROLLER */ + +/* Standard ioctls for mii-tool */ +static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) +{ + struct smsc911x_data *pdata = netdev_priv(dev); + struct mii_ioctl_data *data = if_mii(ifr); + unsigned long flags; + + SMSC_TRACE("ioctl cmd 0x%x", cmd); + switch (cmd) { + case SIOCGMIIPHY: + data->phy_id = pdata->mii.phy_id; + return 0; + case SIOCGMIIREG: + spin_lock_irqsave(&pdata->phy_lock, flags); + data->val_out = smsc911x_phy_read(pdata, data->reg_num); + spin_unlock_irqrestore(&pdata->phy_lock, flags); + return 0; + case SIOCSMIIREG: + spin_lock_irqsave(&pdata->phy_lock, flags); + smsc911x_phy_write(pdata, data->reg_num, data->val_in); + spin_unlock_irqrestore(&pdata->phy_lock, flags); + return 0; + } + + SMSC_TRACE("unsupported ioctl cmd"); + return -1; +} + +static int +smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) +{ + struct smsc911x_data *pdata = netdev_priv(dev); + + cmd->maxtxpkt = 1; + cmd->maxrxpkt = 1; + return mii_ethtool_gset(&pdata->mii, cmd); +} + +static int +smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) +{ + struct smsc911x_data *pdata = netdev_priv(dev); + + return mii_ethtool_sset(&pdata->mii, cmd); +} + +static void smsc911x_ethtool_getdrvinfo(struct net_device *dev, + struct ethtool_drvinfo *info) +{ + strncpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver)); + strncpy(info->version, SMSC_DRV_VERSION, sizeof(info->version)); + strncpy(info->bus_info, dev->dev.bus_id, sizeof(info->bus_info)); +} + +static int smsc911x_ethtool_nwayreset(struct net_device *dev) +{ + struct smsc911x_data *pdata = netdev_priv(dev); + + return mii_nway_restart(&pdata->mii); +} + +static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev) +{ + struct smsc911x_data *pdata = netdev_priv(dev); + return pdata->msg_enable; +} + +static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level) +{ + struct smsc911x_data *pdata = netdev_priv(dev); + pdata->msg_enable = level; +} + +static int smsc911x_ethtool_getregslen(struct net_device *dev) +{ + return (((E2P_CMD - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) * + sizeof(u32); +} + +static void +smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs, + void *buf) +{ + struct smsc911x_data *pdata = netdev_priv(dev); + unsigned long flags; + unsigned int i; + unsigned int j = 0; + u32 *data = buf; + + regs->version = pdata->idrev; + for (i = ID_REV; i <= E2P_CMD; i += (sizeof(u32))) + data[j++] = smsc911x_reg_read(pdata, i); + + spin_lock_irqsave(&pdata->phy_lock, flags); + for (i = MAC_CR; i <= WUCSR; i++) + data[j++] = smsc911x_mac_read(pdata, i); + for (i = 0; i <= 31; i++) + data[j++] = smsc911x_phy_read(pdata, i); + spin_unlock_irqrestore(&pdata->phy_lock, flags); +} + +static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata) +{ + unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG); + temp &= ~GPIO_CFG_EEPR_EN_; + smsc911x_reg_write(temp, pdata, GPIO_CFG); + msleep(1); +} + +static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op) +{ + int timeout = 100; + u32 e2cmd; + + SMSC_TRACE("op 0x%08x", op); + if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) { + SMSC_WARNING("Busy at start"); + return -EBUSY; + } + + e2cmd = op | E2P_CMD_EPC_BUSY_; + smsc911x_reg_write(e2cmd, pdata, E2P_CMD); + + do { + msleep(1); + e2cmd = smsc911x_reg_read(pdata, E2P_CMD); + } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (timeout--)); + + if (!timeout) { + SMSC_TRACE("TIMED OUT"); + return -EAGAIN; + } + + if (e2cmd & E2P_CMD_EPC_TIMEOUT_) { + SMSC_TRACE("Error occured during eeprom operation"); + return -EINVAL; + } + + return 0; +} + +static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata, + u8 address, u8 *data) +{ + u32 op = E2P_CMD_EPC_CMD_READ_ | address; + int ret; + + SMSC_TRACE("address 0x%x", address); + ret = smsc911x_eeprom_send_cmd(pdata, op); + + if (!ret) + data[address] = smsc911x_reg_read(pdata, E2P_DATA); + + return ret; +} + +static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata, + u8 address, u8 data) +{ + u32 op = E2P_CMD_EPC_CMD_ERASE_ | address; + int ret; + + SMSC_TRACE("address 0x%x, data 0x%x", address, data); + ret = smsc911x_eeprom_send_cmd(pdata, op); + + if (!ret) { + op = E2P_CMD_EPC_CMD_WRITE_ | address; + smsc911x_reg_write((u32)data, pdata, E2P_DATA); + ret = smsc911x_eeprom_send_cmd(pdata, op); + } + + return ret; +} + +static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev) +{ + return SMSC911X_EEPROM_SIZE; +} + +static int smsc911x_ethtool_get_eeprom(struct net_device *dev, + struct ethtool_eeprom *eeprom, u8 *data) +{ + struct smsc911x_data *pdata = netdev_priv(dev); + u8 eeprom_data[SMSC911X_EEPROM_SIZE]; + int len; + int i; + + smsc911x_eeprom_enable_access(pdata); + + len = min(eeprom->len, SMSC911X_EEPROM_SIZE); + for (i = 0; i < len; i++) { + int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data); + if (ret < 0) { + eeprom->len = 0; + return ret; + } + } + + memcpy(data, &eeprom_data[eeprom->offset], len); + eeprom->len = len; + return 0; +} + +static int smsc911x_ethtool_set_eeprom(struct net_device *dev, + struct ethtool_eeprom *eeprom, u8 *data) +{ + int ret; + struct smsc911x_data *pdata = netdev_priv(dev); + + smsc911x_eeprom_enable_access(pdata); + smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_); + ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data); + smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_); + + /* Single byte write, according to man page */ + eeprom->len = 1; + + return ret; +} + +static struct ethtool_ops smsc911x_ethtool_ops = { + .get_settings = smsc911x_ethtool_getsettings, + .set_settings = smsc911x_ethtool_setsettings, + .get_link = ethtool_op_get_link, + .get_drvinfo = smsc911x_ethtool_getdrvinfo, + .nway_reset = smsc911x_ethtool_nwayreset, + .get_msglevel = smsc911x_ethtool_getmsglevel, + .set_msglevel = smsc911x_ethtool_setmsglevel, + .get_regs_len = smsc911x_ethtool_getregslen, + .get_regs = smsc911x_ethtool_getregs, + .get_eeprom_len = smsc911x_ethtool_get_eeprom_len, + .get_eeprom = smsc911x_ethtool_get_eeprom, + .set_eeprom = smsc911x_ethtool_set_eeprom, +}; + +/* Initializing private device structures */ +static int smsc911x_init(struct net_device *dev) +{ + u32 mac_high16; + u32 mac_low32; + struct smsc911x_data *pdata = netdev_priv(dev); + + SMSC_TRACE("Driver Parameters:"); + SMSC_TRACE("LAN base: 0x%08lX", (unsigned long)pdata->ioaddr); + SMSC_TRACE("IRQ: %d", dev->irq); + SMSC_TRACE("PHY will be autodetected."); + + if (pdata->ioaddr == 0) { + SMSC_WARNING("pdata->ioaddr: 0x00000000"); + return -ENODEV; + } + + /* Default generation to zero (all workarounds apply) */ + pdata->generation = 0; + + pdata->idrev = smsc911x_reg_read(pdata, ID_REV); + if (((pdata->idrev >> 16) & 0xFFFF) == (pdata->idrev & 0xFFFF)) { + SMSC_WARNING("idrev top 16 bits equal to bottom 16 bits, " + "idrev: 0x%08X", pdata->idrev); + SMSC_TRACE("This may mean the chip is set for 32 bit while " + "the bus is reading as 16 bit"); + return -ENODEV; + } + switch (pdata->idrev & 0xFFFF0000) { + case 0x01180000: + switch (pdata->idrev & 0x0000FFFFUL) { + case 0UL: + SMSC_TRACE("LAN9118 Beacon identified, idrev: 0x%08X", + pdata->idrev); + pdata->generation = 0; + break; + case 1UL: + SMSC_TRACE + ("LAN9118 Concord A0 identified, idrev: 0x%08X", + pdata->idrev); + pdata->generation = 1; + break; + case 2UL: + SMSC_TRACE + ("LAN9118 Concord A1 identified, idrev: 0x%08X", + pdata->idrev); + pdata->generation = 2; + break; + default: + SMSC_TRACE + ("LAN9118 Concord A1 identified (NEW), idrev: 0x%08X", + pdata->idrev); + pdata->generation = 2; + break; + } + break; + + case 0x01170000: + switch (pdata->idrev & 0x0000FFFFUL) { + case 0UL: + SMSC_TRACE("LAN9117 Beacon identified, idrev: 0x%08X", + pdata->idrev); + pdata->generation = 0; + break; + case 1UL: + SMSC_TRACE + ("LAN9117 Concord A0 identified, idrev: 0x%08X", + pdata->idrev); + pdata->generation = 1; + break; + case 2UL: + SMSC_TRACE + ("LAN9117 Concord A1 identified, idrev: 0x%08X", + pdata->idrev); + pdata->generation = 2; + break; + default: + SMSC_TRACE + ("LAN9117 Concord A1 identified (NEW), idrev: 0x%08X", + pdata->idrev); + pdata->generation = 2; + break; + } + break; + + case 0x01160000: + switch (pdata->idrev & 0x0000FFFFUL) { + case 0UL: + SMSC_WARNING("LAN911x not identified, idrev: 0x%08X", + pdata->idrev); + return -ENODEV; + case 1UL: + SMSC_TRACE + ("LAN9116 Concord A0 identified, idrev: 0x%08X", + pdata->idrev); + pdata->generation = 1; + break; + case 2UL: + SMSC_TRACE + ("LAN9116 Concord A1 identified, idrev: 0x%08X", + pdata->idrev); + pdata->generation = 2; + break; + default: + SMSC_TRACE + ("LAN9116 Concord A1 identified (NEW), idrev: 0x%08X", + pdata->idrev); + pdata->generation = 2; + break; + } + break; + + case 0x01150000: + switch (pdata->idrev & 0x0000FFFFUL) { + case 0UL: + SMSC_WARNING("LAN911x not identified, idrev: 0x%08X", + pdata->idrev); + return -ENODEV; + case 1UL: + SMSC_TRACE + ("LAN9115 Concord A0 identified, idrev: 0x%08X", + pdata->idrev); + pdata->generation = 1; + break; + case 2UL: + SMSC_TRACE + ("LAN9115 Concord A1 identified, idrev: 0x%08X", + pdata->idrev); + pdata->generation = 2; + break; + default: + SMSC_TRACE + ("LAN9115 Concord A1 identified (NEW), idrev: 0x%08X", + pdata->idrev); + pdata->generation = 2; + break; + } + break; + + case 0x118A0000UL: + switch (pdata->idrev & 0x0000FFFFUL) { + case 0UL: + SMSC_TRACE + ("LAN9218 Boylston identified, idrev: 0x%08X", + pdata->idrev); + pdata->generation = 3; + break; + default: + SMSC_TRACE + ("LAN9218 Boylston identified (NEW), idrev: 0x%08X", + pdata->idrev); + pdata->generation = 3; + break; + } + break; + + case 0x117A0000UL: + switch (pdata->idrev & 0x0000FFFFUL) { + case 0UL: + SMSC_TRACE + ("LAN9217 Boylston identified, idrev: 0x%08X", + pdata->idrev); + pdata->generation = 3; + break; + default: + SMSC_TRACE + ("LAN9217 Boylston identified (NEW), idrev: 0x%08X", + pdata->idrev); + pdata->generation = 3; + break; + } + break; + + case 0x116A0000UL: + switch (pdata->idrev & 0x0000FFFFUL) { + case 0UL: + SMSC_TRACE + ("LAN9216 Boylston identified, idrev: 0x%08X", + pdata->idrev); + pdata->generation = 3; + break; + default: + SMSC_TRACE + ("LAN9216 Boylston identified (NEW), idrev: 0x%08X", + pdata->idrev); + pdata->generation = 3; + break; + } + break; + + case 0x115A0000UL: + switch (pdata->idrev & 0x0000FFFFUL) { + case 0UL: + SMSC_TRACE + ("LAN9215 Boylston identified, idrev: 0x%08X", + pdata->idrev); + pdata->generation = 3; + break; + default: + SMSC_TRACE + ("LAN9215 Boylston identified (NEW), idrev: 0x%08X", + pdata->idrev); + pdata->generation = 3; + break; + } + break; + + case 0x92100000UL: + case 0x92110000UL: + case 0x92200000UL: + case 0x92210000UL: + /* LAN9210/LAN9211/LAN9220/LAN9221 */ + pdata->generation = 4; + break; + + default: + SMSC_WARNING("LAN911x not identified, idrev: 0x%08X", + pdata->idrev); + return -ENODEV; + } + + if (pdata->generation == 0) + SMSC_WARNING("This driver is not intended " + "for this chip revision"); + + ether_setup(dev); + dev->open = smsc911x_open; + dev->stop = smsc911x_stop; + dev->hard_start_xmit = smsc911x_hard_start_xmit; + dev->get_stats = smsc911x_get_stats; + dev->set_multicast_list = smsc911x_set_multicast_list; + dev->flags |= IFF_MULTICAST; + dev->do_ioctl = smsc911x_do_ioctl; + netif_napi_add(dev, &pdata->napi, smsc911x_poll, 64); + dev->ethtool_ops = &smsc911x_ethtool_ops; + + /* Check if mac address has been specified when bringing interface up */ + if (is_valid_ether_addr(dev->dev_addr)) { + smsc911x_set_mac_address(pdata, dev->dev_addr); + SMSC_TRACE("MAC Address is specified by configuration"); + } else { + /* Try reading mac address from device. if EEPROM is present + * it will already have been set */ + u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH); + u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL); + dev->dev_addr[0] = (u8)(mac_low32); + dev->dev_addr[1] = (u8)(mac_low32 >> 8); + dev->dev_addr[2] = (u8)(mac_low32 >> 16); + dev->dev_addr[3] = (u8)(mac_low32 >> 24); + dev->dev_addr[4] = (u8)(mac_high16); + dev->dev_addr[5] = (u8)(mac_high16 >> 8); + + if (is_valid_ether_addr(dev->dev_addr)) { + /* eeprom values are valid so use them */ + SMSC_TRACE("Mac Address is read from LAN911x EEPROM"); + } else { + /* eeprom values are invalid, generate random MAC */ + random_ether_addr(dev->dev_addr); + smsc911x_set_mac_address(pdata, dev->dev_addr); + SMSC_TRACE("MAC Address is set to random_ether_addr"); + } + } + + printk(KERN_INFO + "%s: SMSC911x MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n", + dev->name, dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], + dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); + +#ifdef CONFIG_NET_POLL_CONTROLLER + dev->poll_controller = smsc911x_poll_controller; +#endif /* CONFIG_NET_POLL_CONTROLLER */ + + pdata->mii.phy_id_mask = 0x1f; + pdata->mii.reg_num_mask = 0x1f; + pdata->mii.force_media = 0; + pdata->mii.full_duplex = 0; + pdata->mii.dev = dev; + pdata->mii.mdio_read = smsc911x_mdio_read; + pdata->mii.mdio_write = smsc911x_mdio_write; + + pdata->msg_enable = NETIF_MSG_LINK; + + return 0; +} + +static int smsc911x_drv_remove(struct platform_device *pdev) +{ + struct net_device *dev; + struct smsc911x_data *pdata; + struct resource *res; + + dev = platform_get_drvdata(pdev); + BUG_ON(!dev); + pdata = netdev_priv(dev); + BUG_ON(!pdata); + BUG_ON(!pdata->ioaddr); + + SMSC_TRACE("Stopping driver."); + platform_set_drvdata(pdev, NULL); + unregister_netdev(dev); + free_irq(dev->irq, dev); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "smsc911x-memory"); + if (!res) + platform_get_resource(pdev, IORESOURCE_MEM, 0); + + release_mem_region(res->start, res->end - res->start); + + iounmap(pdata->ioaddr); + + free_netdev(dev); + + return 0; +} + +static int smsc911x_drv_probe(struct platform_device *pdev) +{ + struct net_device *dev; + struct smsc911x_data *pdata; + struct resource *res; + unsigned int intcfg = 0; + int res_size; + int retval; + + printk(KERN_INFO "%s: Driver version %s.\n", SMSC_CHIPNAME, + SMSC_DRV_VERSION); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "smsc911x-memory"); + if (!res) + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + printk(KERN_WARNING "%s: Could not allocate resource.\n", + SMSC_CHIPNAME); + retval = -ENODEV; + goto out_0; + } + res_size = res->end - res->start; + + if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) { + retval = -EBUSY; + goto out_0; + } + + dev = alloc_etherdev(sizeof(struct smsc911x_data)); + if (!dev) { + printk(KERN_WARNING "%s: Could not allocate device.\n", + SMSC_CHIPNAME); + retval = -ENOMEM; + goto out_release_io_1; + } + + SET_NETDEV_DEV(dev, &pdev->dev); + + pdata = netdev_priv(dev); + pdata->netdev = dev; + + dev->irq = platform_get_irq(pdev, 0); + pdata->ioaddr = ioremap_nocache(res->start, res_size); + + /* copy config parameters across if present, otherwise pdata + * defaults to zeros */ + if (pdev->dev.platform_data) { + struct smsc911x_platform_config *config = pdev->dev.platform_data; + pdata->irq_polarity = config->irq_polarity; + pdata->irq_type = config->irq_type; + } + + if (pdata->ioaddr == NULL) { + SMSC_WARNING("Error smsc911x base address invalid"); + retval = -ENOMEM; + goto out_free_netdev_2; + } + + if ((retval = smsc911x_init(dev)) < 0) + goto out_unmap_io_3; + + /* configure irq polarity and type before connecting isr */ + if (pdata->irq_polarity) + intcfg |= INT_CFG_IRQ_POL_; + + if (pdata->irq_type) + intcfg |= INT_CFG_IRQ_TYPE_; + + smsc911x_reg_write(intcfg, pdata, INT_CFG); + + retval = request_irq(dev->irq, smsc911x_irqhandler, IRQF_DISABLED, + SMSC_CHIPNAME, dev); + if (retval) { + SMSC_WARNING("Unable to claim requested irq: %d", dev->irq); + goto out_unmap_io_3; + } + + platform_set_drvdata(pdev, dev); + + retval = register_netdev(dev); + if (retval) { + SMSC_WARNING("Error %i registering device", retval); + goto out_unset_drvdata_4; + } else { + SMSC_TRACE("Network interface: \"%s\"", dev->name); + } + + return 0; + +out_unset_drvdata_4: + platform_set_drvdata(pdev, NULL); + free_irq(dev->irq, dev); +out_unmap_io_3: + iounmap(pdata->ioaddr); +out_free_netdev_2: + free_netdev(dev); +out_release_io_1: + release_mem_region(res->start, res->end - res->start); +out_0: + return retval; +} + +static int smsc911x_drv_suspend(struct platform_device *pdev, + pm_message_t state) +{ + unsigned long flags; + struct net_device *dev; + struct smsc911x_data *pdata; + + dev = platform_get_drvdata(pdev); + BUG_ON(!dev); + pdata = netdev_priv(dev); + BUG_ON(!pdata); + BUG_ON(!pdata->ioaddr); + + spin_lock_irqsave(&pdata->phy_lock, flags); + smsc911x_phy_write(pdata, MII_BMCR, BMCR_PDOWN); + spin_unlock_irqrestore(&pdata->phy_lock, flags); + + smsc911x_reg_write(PMT_CTRL_PM_MODE_D2_, pdata, PMT_CTRL); + + return 0; +} + +static int smsc911x_drv_resume(struct platform_device *pdev) +{ + unsigned long flags; + struct net_device *dev; + struct smsc911x_data *pdata; + unsigned int temp; + + dev = platform_get_drvdata(pdev); + BUG_ON(!dev); + pdata = netdev_priv(dev); + BUG_ON(!pdata); + BUG_ON(!pdata->ioaddr); + + smsc911x_reg_write(0xFFFFFFFF, pdata, BYTE_TEST); + while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_)) + ; + + spin_lock_irqsave(&pdata->phy_lock, flags); + smsc911x_phy_write(pdata, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); + spin_unlock_irqrestore(&pdata->phy_lock, flags); + return 0; +} + +static struct platform_driver smsc911x_driver = { + .probe = smsc911x_drv_probe, + .remove = smsc911x_drv_remove, + .suspend = smsc911x_drv_suspend, + .resume = smsc911x_drv_resume, + .driver = { + .name = SMSC_CHIPNAME, + }, +}; + +/* Entry point for loading the module */ +static int __init smsc911x_init_module(void) +{ + return platform_driver_register(&smsc911x_driver); +} + +/* entry point for unloading the module */ +static void __exit smsc911x_cleanup_module(void) +{ + platform_driver_unregister(&smsc911x_driver); +} + +module_init(smsc911x_init_module); +module_exit(smsc911x_cleanup_module); diff -urN linux-2.6.26/drivers/net/smsc911x.h linux-2.6.26-lab126/drivers/net/smsc911x.h --- linux-2.6.26/drivers/net/smsc911x.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/smsc911x.h 2010-08-10 04:17:02.000000000 -0400 @@ -0,0 +1,395 @@ +/*************************************************************************** + * + * Copyright (C) 2004-2007 SMSC + * Copyright (C) 2005 ARM + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + ***************************************************************************/ +#ifndef __SMSC911X_H__ +#define __SMSC911X_H__ + +#if defined(CONFIG_MACH_MX37_3DS) || defined(CONFIG_MACH_MX25_3DS) +#define SMSC_CAN_USE_SPI 1 +#define SMSC_CAN_USE_32BIT 0 +#elif defined(CONFIG_MACH_MX31_3DS) || defined(CONFIG_MACH_MX35_3DS) +#define SMSC_CAN_USE_32BIT 0 +#define SMSC_CAN_USE_SPI 0 +#else +#define SMSC_CAN_USE_32BIT 1 +#define SMSC_CAN_USE_SPI 0 +#endif + +#define TX_FIFO_LOW_THRESHOLD (u32)1600 +#define SMSC911X_EEPROM_SIZE (u32)7 +#define USE_DEBUG 0 + +/* implements a PHY loopback test at initialisation time, to ensure a packet + * can be succesfully looped back */ +#define USE_PHY_WORK_AROUND + +/* 10/100 LED link-state inversion when media is disconnected */ +#define USE_LED1_WORK_AROUND + +/* platform_device configuration data, should be assigned to + * the platform_device's dev.platform_data */ +struct smsc911x_platform_config { + unsigned int irq_polarity; + unsigned int irq_type; +}; + +#if USE_DEBUG >= 1 +#define SMSC_WARNING(fmt, args...) \ + printk(KERN_EMERG "SMSC_WARNING: %s: " fmt "\n", \ + __FUNCTION__ , ## args) +#else +#define SMSC_WARNING(msg, args...) +#endif /* USE_DEBUG >= 1 */ + +#if USE_DEBUG >= 2 +#define SMSC_TRACE(fmt,args...) \ + printk(KERN_EMERG "SMSC_TRACE: %s: " fmt "\n", \ + __FUNCTION__ , ## args) +#else +#define SMSC_TRACE(msg,args...) +#endif /* USE_DEBUG >= 2 */ + +/* SMSC911x registers and bitfields */ +#define RX_DATA_FIFO 0x00 + +#define TX_DATA_FIFO 0x20 +#define TX_CMD_A_ON_COMP_ 0x80000000 +#define TX_CMD_A_BUF_END_ALGN_ 0x03000000 +#define TX_CMD_A_4_BYTE_ALGN_ 0x00000000 +#define TX_CMD_A_16_BYTE_ALGN_ 0x01000000 +#define TX_CMD_A_32_BYTE_ALGN_ 0x02000000 +#define TX_CMD_A_DATA_OFFSET_ 0x001F0000 +#define TX_CMD_A_FIRST_SEG_ 0x00002000 +#define TX_CMD_A_LAST_SEG_ 0x00001000 +#define TX_CMD_A_BUF_SIZE_ 0x000007FF +#define TX_CMD_B_PKT_TAG_ 0xFFFF0000 +#define TX_CMD_B_ADD_CRC_DISABLE_ 0x00002000 +#define TX_CMD_B_DISABLE_PADDING_ 0x00001000 +#define TX_CMD_B_PKT_BYTE_LENGTH_ 0x000007FF + +#define RX_STATUS_FIFO 0x40 +#define RX_STS_ES_ 0x00008000 +#define RX_STS_MCAST_ 0x00000400 + +#define RX_STATUS_FIFO_PEEK 0x44 + +#define TX_STATUS_FIFO 0x48 +#define TX_STS_ES_ 0x00008000 + +#define TX_STATUS_FIFO_PEEK 0x4C + +#define ID_REV 0x50 +#define ID_REV_CHIP_ID_ 0xFFFF0000 +#define ID_REV_REV_ID_ 0x0000FFFF + +#define INT_CFG 0x54 +#define INT_CFG_INT_DEAS_ 0xFF000000 +#define INT_CFG_INT_DEAS_CLR_ 0x00004000 +#define INT_CFG_INT_DEAS_STS_ 0x00002000 +#define INT_CFG_IRQ_INT_ 0x00001000 +#define INT_CFG_IRQ_EN_ 0x00000100 +#define INT_CFG_IRQ_POL_ 0x00000010 +#define INT_CFG_IRQ_TYPE_ 0x00000001 + +#define INT_STS 0x58 +#define INT_STS_SW_INT_ 0x80000000 +#define INT_STS_TXSTOP_INT_ 0x02000000 +#define INT_STS_RXSTOP_INT_ 0x01000000 +#define INT_STS_RXDFH_INT_ 0x00800000 +#define INT_STS_RXDF_INT_ 0x00400000 +#define INT_STS_TX_IOC_ 0x00200000 +#define INT_STS_RXD_INT_ 0x00100000 +#define INT_STS_GPT_INT_ 0x00080000 +#define INT_STS_PHY_INT_ 0x00040000 +#define INT_STS_PME_INT_ 0x00020000 +#define INT_STS_TXSO_ 0x00010000 +#define INT_STS_RWT_ 0x00008000 +#define INT_STS_RXE_ 0x00004000 +#define INT_STS_TXE_ 0x00002000 +#define INT_STS_TDFU_ 0x00000800 +#define INT_STS_TDFO_ 0x00000400 +#define INT_STS_TDFA_ 0x00000200 +#define INT_STS_TSFF_ 0x00000100 +#define INT_STS_TSFL_ 0x00000080 +#define INT_STS_RXDF_ 0x00000040 +#define INT_STS_RDFL_ 0x00000020 +#define INT_STS_RSFF_ 0x00000010 +#define INT_STS_RSFL_ 0x00000008 +#define INT_STS_GPIO2_INT_ 0x00000004 +#define INT_STS_GPIO1_INT_ 0x00000002 +#define INT_STS_GPIO0_INT_ 0x00000001 + +#define INT_EN 0x5C +#define INT_EN_SW_INT_EN_ 0x80000000 +#define INT_EN_TXSTOP_INT_EN_ 0x02000000 +#define INT_EN_RXSTOP_INT_EN_ 0x01000000 +#define INT_EN_RXDFH_INT_EN_ 0x00800000 +#define INT_EN_TIOC_INT_EN_ 0x00200000 +#define INT_EN_RXD_INT_EN_ 0x00100000 +#define INT_EN_GPT_INT_EN_ 0x00080000 +#define INT_EN_PHY_INT_EN_ 0x00040000 +#define INT_EN_PME_INT_EN_ 0x00020000 +#define INT_EN_TXSO_EN_ 0x00010000 +#define INT_EN_RWT_EN_ 0x00008000 +#define INT_EN_RXE_EN_ 0x00004000 +#define INT_EN_TXE_EN_ 0x00002000 +#define INT_EN_TDFU_EN_ 0x00000800 +#define INT_EN_TDFO_EN_ 0x00000400 +#define INT_EN_TDFA_EN_ 0x00000200 +#define INT_EN_TSFF_EN_ 0x00000100 +#define INT_EN_TSFL_EN_ 0x00000080 +#define INT_EN_RXDF_EN_ 0x00000040 +#define INT_EN_RDFL_EN_ 0x00000020 +#define INT_EN_RSFF_EN_ 0x00000010 +#define INT_EN_RSFL_EN_ 0x00000008 +#define INT_EN_GPIO2_INT_ 0x00000004 +#define INT_EN_GPIO1_INT_ 0x00000002 +#define INT_EN_GPIO0_INT_ 0x00000001 + +#define BYTE_TEST 0x64 + +#define FIFO_INT 0x68 +#define FIFO_INT_TX_AVAIL_LEVEL_ 0xFF000000 +#define FIFO_INT_TX_STS_LEVEL_ 0x00FF0000 +#define FIFO_INT_RX_AVAIL_LEVEL_ 0x0000FF00 +#define FIFO_INT_RX_STS_LEVEL_ 0x000000FF + +#define RX_CFG 0x6C +#define RX_CFG_RX_END_ALGN_ 0xC0000000 +#define RX_CFG_RX_END_ALGN4_ 0x00000000 +#define RX_CFG_RX_END_ALGN16_ 0x40000000 +#define RX_CFG_RX_END_ALGN32_ 0x80000000 +#define RX_CFG_RX_DMA_CNT_ 0x0FFF0000 +#define RX_CFG_RX_DUMP_ 0x00008000 +#define RX_CFG_RXDOFF_ 0x00001F00 + +#define TX_CFG 0x70 +#define TX_CFG_TXS_DUMP_ 0x00008000 +#define TX_CFG_TXD_DUMP_ 0x00004000 +#define TX_CFG_TXSAO_ 0x00000004 +#define TX_CFG_TX_ON_ 0x00000002 +#define TX_CFG_STOP_TX_ 0x00000001 + +#define HW_CFG 0x74 +#define HW_CFG_TTM_ 0x00200000 +#define HW_CFG_SF_ 0x00100000 +#define HW_CFG_TX_FIF_SZ_ 0x000F0000 +#define HW_CFG_TR_ 0x00003000 +#define HW_CFG_SRST_ 0x00000001 + +/* only available on 115/117 */ +#define HW_CFG_PHY_CLK_SEL_ 0x00000060 +#define HW_CFG_PHY_CLK_SEL_INT_PHY_ 0x00000000 +#define HW_CFG_PHY_CLK_SEL_EXT_PHY_ 0x00000020 +#define HW_CFG_PHY_CLK_SEL_CLK_DIS_ 0x00000040 +#define HW_CFG_SMI_SEL_ 0x00000010 +#define HW_CFG_EXT_PHY_DET_ 0x00000008 +#define HW_CFG_EXT_PHY_EN_ 0x00000004 +#define HW_CFG_SRST_TO_ 0x00000002 + +/* only available on 116/118 */ +#define HW_CFG_32_16_BIT_MODE_ 0x00000004 + +#define RX_DP_CTRL 0x78 +#define RX_DP_CTRL_RX_FFWD_ 0x80000000 + +#define RX_FIFO_INF 0x7C +#define RX_FIFO_INF_RXSUSED_ 0x00FF0000 +#define RX_FIFO_INF_RXDUSED_ 0x0000FFFF + +#define TX_FIFO_INF 0x80 +#define TX_FIFO_INF_TSUSED_ 0x00FF0000 +#define TX_FIFO_INF_TDFREE_ 0x0000FFFF + +#define PMT_CTRL 0x84 +#define PMT_CTRL_PM_MODE_ 0x00003000 +#define PMT_CTRL_PM_MODE_D0_ 0x00000000 +#define PMT_CTRL_PM_MODE_D1_ 0x00001000 +#define PMT_CTRL_PM_MODE_D2_ 0x00002000 +#define PMT_CTRL_PM_MODE_D3_ 0x00003000 +#define PMT_CTRL_PHY_RST_ 0x00000400 +#define PMT_CTRL_WOL_EN_ 0x00000200 +#define PMT_CTRL_ED_EN_ 0x00000100 +#define PMT_CTRL_PME_TYPE_ 0x00000040 +#define PMT_CTRL_WUPS_ 0x00000030 +#define PMT_CTRL_WUPS_NOWAKE_ 0x00000000 +#define PMT_CTRL_WUPS_ED_ 0x00000010 +#define PMT_CTRL_WUPS_WOL_ 0x00000020 +#define PMT_CTRL_WUPS_MULTI_ 0x00000030 +#define PMT_CTRL_PME_IND_ 0x00000008 +#define PMT_CTRL_PME_POL_ 0x00000004 +#define PMT_CTRL_PME_EN_ 0x00000002 +#define PMT_CTRL_READY_ 0x00000001 + +#define GPIO_CFG 0x88 +#define GPIO_CFG_LED3_EN_ 0x40000000 +#define GPIO_CFG_LED2_EN_ 0x20000000 +#define GPIO_CFG_LED1_EN_ 0x10000000 +#define GPIO_CFG_GPIO2_INT_POL_ 0x04000000 +#define GPIO_CFG_GPIO1_INT_POL_ 0x02000000 +#define GPIO_CFG_GPIO0_INT_POL_ 0x01000000 +#define GPIO_CFG_EEPR_EN_ 0x00700000 +#define GPIO_CFG_GPIOBUF2_ 0x00040000 +#define GPIO_CFG_GPIOBUF1_ 0x00020000 +#define GPIO_CFG_GPIOBUF0_ 0x00010000 +#define GPIO_CFG_GPIODIR2_ 0x00000400 +#define GPIO_CFG_GPIODIR1_ 0x00000200 +#define GPIO_CFG_GPIODIR0_ 0x00000100 +#define GPIO_CFG_GPIOD4_ 0x00000020 +#define GPIO_CFG_GPIOD3_ 0x00000010 +#define GPIO_CFG_GPIOD2_ 0x00000004 +#define GPIO_CFG_GPIOD1_ 0x00000002 +#define GPIO_CFG_GPIOD0_ 0x00000001 + +#define GPT_CFG 0x8C +#define GPT_CFG_TIMER_EN_ 0x20000000 +#define GPT_CFG_GPT_LOAD_ 0x0000FFFF + +#define GPT_CNT 0x90 +#define GPT_CNT_GPT_CNT_ 0x0000FFFF + +#define ENDIAN 0x98 + +#define FREE_RUN 0x9C + +#define RX_DROP 0xA0 + +#define MAC_CSR_CMD 0xA4 +#define MAC_CSR_CMD_CSR_BUSY_ 0x80000000 +#define MAC_CSR_CMD_R_NOT_W_ 0x40000000 +#define MAC_CSR_CMD_CSR_ADDR_ 0x000000FF + +#define MAC_CSR_DATA 0xA8 + +#define AFC_CFG 0xAC +#define AFC_CFG_AFC_HI_ 0x00FF0000 +#define AFC_CFG_AFC_LO_ 0x0000FF00 +#define AFC_CFG_BACK_DUR_ 0x000000F0 +#define AFC_CFG_FCMULT_ 0x00000008 +#define AFC_CFG_FCBRD_ 0x00000004 +#define AFC_CFG_FCADD_ 0x00000002 +#define AFC_CFG_FCANY_ 0x00000001 + +#define E2P_CMD 0xB0 +#define E2P_CMD_EPC_BUSY_ 0x80000000 +#define E2P_CMD_EPC_CMD_ 0x70000000 +#define E2P_CMD_EPC_CMD_READ_ 0x00000000 +#define E2P_CMD_EPC_CMD_EWDS_ 0x10000000 +#define E2P_CMD_EPC_CMD_EWEN_ 0x20000000 +#define E2P_CMD_EPC_CMD_WRITE_ 0x30000000 +#define E2P_CMD_EPC_CMD_WRAL_ 0x40000000 +#define E2P_CMD_EPC_CMD_ERASE_ 0x50000000 +#define E2P_CMD_EPC_CMD_ERAL_ 0x60000000 +#define E2P_CMD_EPC_CMD_RELOAD_ 0x70000000 +#define E2P_CMD_EPC_TIMEOUT_ 0x00000200 +#define E2P_CMD_MAC_ADDR_LOADED_ 0x00000100 +#define E2P_CMD_EPC_ADDR_ 0x000000FF + +#define E2P_DATA 0xB4 +#define E2P_DATA_EEPROM_DATA_ 0x000000FF +#define LAN_REGISTER_EXTENT 0x00000100 + +/* + * MAC Control and Status Register (Indirect Address) + * Offset (through the MAC_CSR CMD and DATA port) + */ +#define MAC_CR 0x01 +#define MAC_CR_RXALL_ 0x80000000 +#define MAC_CR_HBDIS_ 0x10000000 +#define MAC_CR_RCVOWN_ 0x00800000 +#define MAC_CR_LOOPBK_ 0x00200000 +#define MAC_CR_FDPX_ 0x00100000 +#define MAC_CR_MCPAS_ 0x00080000 +#define MAC_CR_PRMS_ 0x00040000 +#define MAC_CR_INVFILT_ 0x00020000 +#define MAC_CR_PASSBAD_ 0x00010000 +#define MAC_CR_HFILT_ 0x00008000 +#define MAC_CR_HPFILT_ 0x00002000 +#define MAC_CR_LCOLL_ 0x00001000 +#define MAC_CR_BCAST_ 0x00000800 +#define MAC_CR_DISRTY_ 0x00000400 +#define MAC_CR_PADSTR_ 0x00000100 +#define MAC_CR_BOLMT_MASK_ 0x000000C0 +#define MAC_CR_DFCHK_ 0x00000020 +#define MAC_CR_TXEN_ 0x00000008 +#define MAC_CR_RXEN_ 0x00000004 + +#define ADDRH 0x02 + +#define ADDRL 0x03 + +#define HASHH 0x04 + +#define HASHL 0x05 + +#define MII_ACC 0x06 +#define MII_ACC_PHY_ADDR_ 0x0000F800 +#define MII_ACC_MIIRINDA_ 0x000007C0 +#define MII_ACC_MII_WRITE_ 0x00000002 +#define MII_ACC_MII_BUSY_ 0x00000001 + +#define MII_DATA 0x07 + +#define FLOW 0x08 +#define FLOW_FCPT_ 0xFFFF0000 +#define FLOW_FCPASS_ 0x00000004 +#define FLOW_FCEN_ 0x00000002 +#define FLOW_FCBSY_ 0x00000001 + +#define VLAN1 0x09 + +#define VLAN2 0x0A + +#define WUFF 0x0B + +#define WUCSR 0x0C +#define WUCSR_GUE_ 0x00000200 +#define WUCSR_WUFR_ 0x00000040 +#define WUCSR_MPR_ 0x00000020 +#define WUCSR_WAKE_EN_ 0x00000004 +#define WUCSR_MPEN_ 0x00000002 + +/* + * Phy definitions (vendor-specific) + */ +#define LAN9118_PHY_ID 0x00C0001C + +#define MII_INTSTS 0x1D + +#define MII_INTMSK 0x1E +#define PHY_INTMSK_AN_RCV_ (1 << 1) +#define PHY_INTMSK_PDFAULT_ (1 << 2) +#define PHY_INTMSK_AN_ACK_ (1 << 3) +#define PHY_INTMSK_LNKDOWN_ (1 << 4) +#define PHY_INTMSK_RFAULT_ (1 << 5) +#define PHY_INTMSK_AN_COMP_ (1 << 6) +#define PHY_INTMSK_ENERGYON_ (1 << 7) +#define PHY_INTMSK_DEFAULT_ (PHY_INTMSK_ENERGYON_ | \ + PHY_INTMSK_AN_COMP_ | \ + PHY_INTMSK_RFAULT_ | \ + PHY_INTMSK_LNKDOWN_) + +#define ADVERTISE_PAUSE_ALL (ADVERTISE_PAUSE_CAP | \ + ADVERTISE_PAUSE_ASYM) + +#define LPA_PAUSE_ALL (LPA_PAUSE_CAP | \ + LPA_PAUSE_ASYM) + +#endif /* __SMSC911X_H__ */ diff -urN linux-2.6.26/drivers/net/sungem.c linux-2.6.26-lab126/drivers/net/sungem.c --- linux-2.6.26/drivers/net/sungem.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/sungem.c 2010-08-10 04:17:02.000000000 -0400 @@ -1033,10 +1033,8 @@ (csum_stuff_off << 21)); } - local_irq_save(flags); - if (!spin_trylock(&gp->tx_lock)) { + if (!spin_trylock_irqsave(&gp->tx_lock, flags)) { /* Tell upper layer to requeue */ - local_irq_restore(flags); return NETDEV_TX_LOCKED; } /* We raced with gem_do_stop() */ diff -urN linux-2.6.26/drivers/net/tulip/tulip_core.c linux-2.6.26-lab126/drivers/net/tulip/tulip_core.c --- linux-2.6.26/drivers/net/tulip/tulip_core.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/tulip/tulip_core.c 2010-08-10 04:16:28.000000000 -0400 @@ -1799,6 +1799,7 @@ pci_iounmap(pdev, tp->base_addr); free_netdev (dev); pci_release_regions (pdev); + pci_disable_device (pdev); pci_set_drvdata (pdev, NULL); /* pci_power_off (pdev, -1); */ diff -urN linux-2.6.26/drivers/net/usb/usbnet.c linux-2.6.26-lab126/drivers/net/usb/usbnet.c --- linux-2.6.26/drivers/net/usb/usbnet.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/usb/usbnet.c 2010-08-10 04:16:55.000000000 -0400 @@ -904,6 +904,8 @@ urb->dev = NULL; entry->state = tx_done; + spin_lock_rt(&dev->txq.lock); + spin_unlock_rt(&dev->txq.lock); defer_bh(dev, skb, &dev->txq); } diff -urN linux-2.6.26/drivers/net/wan/.gitignore linux-2.6.26-lab126/drivers/net/wan/.gitignore --- linux-2.6.26/drivers/net/wan/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/wan/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1 +0,0 @@ -wanxlfw.inc diff -urN linux-2.6.26/drivers/net/wan/Kconfig linux-2.6.26-lab126/drivers/net/wan/Kconfig --- linux-2.6.26/drivers/net/wan/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/wan/Kconfig 2010-08-10 04:16:56.000000000 -0400 @@ -496,4 +496,8 @@ If unsure, say N. +config LUIGI_WAN + tristate "Luigi WAN module support" + depends on MACH_MX35_LUIGI + endif # WAN diff -urN linux-2.6.26/drivers/net/wan/Makefile linux-2.6.26-lab126/drivers/net/wan/Makefile --- linux-2.6.26/drivers/net/wan/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/wan/Makefile 2010-08-10 04:16:56.000000000 -0400 @@ -46,6 +46,11 @@ clean-files := wanxlfw.inc $(obj)/wanxl.o: $(obj)/wanxlfw.inc +ifneq ($(CONFIG_LUIGI_WAN),) +obj-y += mwan-core.o +endif +obj-$(CONFIG_LUIGI_WAN) += mwan.o + ifeq ($(CONFIG_WANXL_BUILD_FIRMWARE),y) ifeq ($(ARCH),m68k) AS68K = $(AS) diff -urN linux-2.6.26/drivers/net/wan/mwan-core.c linux-2.6.26-lab126/drivers/net/wan/mwan-core.c --- linux-2.6.26/drivers/net/wan/mwan-core.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wan/mwan-core.c 2010-08-10 04:16:56.000000000 -0400 @@ -0,0 +1,34 @@ +/* + * mwan-core.c -- Mario WAN hardware control driver + * + * Copyright 2005-2008 Lab126, Inc. All rights reserved. + * + */ + +#include +#include +#include + + +static wan_status_t wan_power_status = WAN_INVALID; + + +void +wan_set_power_status( + wan_status_t status) +{ + wan_power_status = status; +} + +EXPORT_SYMBOL(wan_set_power_status); + + +wan_status_t +wan_get_power_status( + void) +{ + return wan_power_status; +} + +EXPORT_SYMBOL(wan_get_power_status); + diff -urN linux-2.6.26/drivers/net/wan/mwan.c linux-2.6.26-lab126/drivers/net/wan/mwan.c --- linux-2.6.26/drivers/net/wan/mwan.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wan/mwan.c 2010-08-10 04:16:56.000000000 -0400 @@ -0,0 +1,727 @@ +/* + * mwan.c -- Mario WAN hardware control driver + * + * Copyright 2005-2009 Lab126, Inc. All rights reserved. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)) +#include +#include +#else +#include +#endif +#include + +// DTP module hardware-specific settings +#undef USE_DTP_SLEEP_MODE +#undef USE_DTP_RFE_PULLUP + + +#undef DEBUG + +#ifdef DEBUG +#define log_debug(format, arg...) printk("mwan: D %s:" format, __func__, ## arg) +#else +#define log_debug(format, arg...) +#endif + +#define log_info(format, arg...) printk("mwan: I %s:" format, __func__, ## arg) +#define log_err(format, arg...) printk("mwan: E %s:" format, __func__, ## arg) + +#define VERSION "1.2.0" + +#define PROC_WAN "wan" +#define PROC_WAN_POWER "power" +#define PROC_WAN_ENABLE "enable" +#define PROC_WAN_TYPE "type" +#define PROC_WAN_USB "usb" + +static struct proc_dir_entry *proc_wan_parent; +static struct proc_dir_entry *proc_wan_power; +static struct proc_dir_entry *proc_wan_enable; +static struct proc_dir_entry *proc_wan_type; +static struct proc_dir_entry *proc_wan_usb; + +static wan_status_t wan_status = WAN_OFF; +static int modem_type = MODEM_TYPE_UNKNOWN; + +static int wan_rf_enable_state = 0; +static int wan_usb_enable_state = 0; +static int wan_on_off_state = 0; + + +#define WAN_STRING_CLASS "wan" +#define WAN_STRING_DEV "mwan" + +static struct file_operations mwan_ops = { + .owner = THIS_MODULE, + .ioctl = NULL, // (add ioctl support, if desired) +}; + + +static struct class *wan_class = NULL; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)) +static struct device *wan_dev = NULL; +#else +static struct class_device *wan_dev = NULL; +#endif +static int wan_major = 0; + +#define TPH_TYPE_NONE 0 +#define TPH_TYPE_RINGSMS 1 +#define TPH_TYPE_USBWAKE 2 +static time_t tph_last_seconds = 0; +static int tph_last_type = TPH_TYPE_NONE; + +// standard network deregistration time definition: +// 2s -- maximum time required between the start of power down and that of IMSI detach +// 5s -- maximum time required for the IMSI detach +// 5s -- maximum time required between the IMSI detach and power down finish (time +// required to stop tasks, etc.) +// 3s -- recommended safety margin +#define NETWORK_DEREG_TIME ((12 + 3) * 1000) + +// for the DTP module, we use an optimized path for performing deregistration +#define NETWORK_DEREG_TIME_OPT (3 * 1000) + +// minimum allowed delay between TPH notifications +#define WAKE_EVENT_INTERVAL 10 + + +static time_t modem_off_seconds = -1; + +#define DTP_ON_DELAY_SEC 5 // DTP WAN power-up boot delay +#define DTP_OFF_DELAY_SEC 3 // DTP WAN power-down supercap discharge delay + + +static inline int +get_wan_on_off( + void) +{ + return wan_on_off_state; +} + + +static void +set_wan_on_off( + int enable) +{ + extern void gpio_wan_power(int); + + enable = enable != 0; // (ensure that "enable" is a boolean) + + if (modem_type == MODEM_TYPE_AD_DTP) { + if (!enable) { + modem_off_seconds = CURRENT_TIME_SEC.tv_sec; + + } else if (modem_off_seconds > 0) { + long wait_seconds = (modem_off_seconds + DTP_OFF_DELAY_SEC) - CURRENT_TIME_SEC.tv_sec; + + if (wait_seconds < 0) { + modem_off_seconds = wait_seconds = 0; + + } else if (wait_seconds > 0) { + if (wait_seconds > DTP_OFF_DELAY_SEC) { + wait_seconds = DTP_OFF_DELAY_SEC; + } + + log_info("wpd:wait=%ld:modem power on delay\n", wait_seconds); + + ssleep(wait_seconds); + } + } + } + + log_debug("pow:enable=%d:setting WAN hardware power state\n", enable); + + gpio_wan_power(enable); + + wan_on_off_state = enable; +} + + +static inline int +get_wan_rf_enable( + void) +{ + return wan_rf_enable_state; +} + + +static void +set_wan_rf_enable( + int enable) +{ + extern void gpio_wan_rf_enable(int); + + if (enable != get_wan_rf_enable()) { + log_debug("swe:enable=%d:setting WAN RF enable state\n", enable); + + gpio_wan_rf_enable(enable); + + wan_rf_enable_state = enable; + } +} + + +static inline int +get_wan_usb_enable( + void) +{ + return wan_usb_enable_state; +} + + +static void +set_wan_usb_enable( + int enable) +{ + extern void gpio_wan_usb_enable(int); + + if (enable != get_wan_usb_enable()) { + log_debug("swu:enable=%d:setting WAN USB enable state\n", enable); + + gpio_wan_usb_enable(enable); + + wan_usb_enable_state = enable; + } +} + + +static int +set_wan_power( + wan_status_t new_status) +{ + wan_status_t check_status = new_status == WAN_OFF_KILL ? WAN_OFF : new_status; + + if (check_status == wan_status) { + return 0; + } + + // ignore any spurious WAKE line events during module power processing + tph_last_seconds = CURRENT_TIME_SEC.tv_sec; + + switch (new_status) { + + case WAN_ON : +#ifdef USE_DTP_SLEEP_MODE + if (get_wan_on_off() == 0 || modem_type != MODEM_TYPE_AD_DTP) { +#endif + // bring up WAN_ON_OFF + set_wan_on_off(1); +#ifdef USE_DTP_SLEEP_MODE + } +#endif + + if (modem_type == MODEM_TYPE_AD_DTP || modem_type == MODEM_TYPE_UNKNOWN) { + // pause following power-on before bringing up the RF_ENABLE line (use 1s per DTP spec) + ssleep(1); + + } else { + // pause for 100ms for all other modem types + msleep(100); + } + + // bring up WAN_RF_ENABLE + set_wan_rf_enable(1); + + if (modem_type == MODEM_TYPE_AD_DTP || modem_type == MODEM_TYPE_UNKNOWN) { + // (if modem is unknown, it could be a DTP, so must delay as well) + ssleep(DTP_ON_DELAY_SEC); + } + break; + + default : + log_err("req_err:request=%d:unknown power request\n", new_status); + + // (fall through) + + case WAN_OFF : + case WAN_OFF_KILL : + // bring down WAN_RF_ENABLE + set_wan_rf_enable(0); + + if (new_status != WAN_OFF_KILL) { + // wait the necessary deregistration interval + msleep(modem_type == MODEM_TYPE_AD_DTP ? NETWORK_DEREG_TIME_OPT : NETWORK_DEREG_TIME); + } + +#ifdef USE_DTP_SLEEP_MODE + if (new_status == WAN_OFF_KILL || modem_type != MODEM_TYPE_AD_DTP) { +#endif + // bring down WAN_ON_OFF + set_wan_on_off(0); +#ifdef USE_DTP_SLEEP_MODE + } +#endif + + new_status = WAN_OFF; + break; + + } + + wan_status = new_status; + + wan_set_power_status(wan_status); + + return 0; +} + + +static void +init_modem_type( + int type) +{ + if (modem_type != type) { + log_info("smt:type=%d:setting modem type\n", type); + + modem_type = type; + } +} + + +int +wan_get_modem_type( + void) +{ + return modem_type; +} + +EXPORT_SYMBOL(wan_get_modem_type); + + +static int +proc_power_read( + char *page, + char **start, + off_t off, + int count, + int *eof, + void *data) +{ + *eof = 1; + + return sprintf(page, "%d\n", wan_status == WAN_ON ? 1 : 0); +} + + +static int +proc_power_write( + struct file *file, + const char __user *buf, + unsigned long count, + void *data) +{ + char lbuf[16]; + unsigned char op; + + memset(lbuf, 0, sizeof(lbuf)); + + if (copy_from_user(lbuf, buf, 1)) { + return -EFAULT; + } + + op = lbuf[0]; + if (op >= '0' && op <= '9') { + wan_status_t new_wan_status = (wan_status_t)(op - '0'), prev_wan_status = wan_status; + + switch (new_wan_status) { + + case WAN_OFF : + case WAN_ON : + // perform normal on/off power handling + if ((new_wan_status == WAN_ON && prev_wan_status == WAN_OFF) || + (new_wan_status == WAN_OFF && prev_wan_status == WAN_ON)) { + set_wan_power(new_wan_status); + } + break; + + + case WAN_OFF_KILL : + set_wan_power(new_wan_status); + break; + + default : + log_err("req_err:request=%d:unknown power request\n", new_wan_status); + break; + + } + + } else { + log_err("req_err:request='%c':unknown power request\n", op); + } + + return count; +} + + +static int +proc_enable_read( + char *page, + char **start, + off_t off, + int count, + int *eof, + void *data) +{ + *eof = 1; + + return sprintf(page, "%d\n", get_wan_rf_enable()); +} + + +static int +proc_enable_write( + struct file *file, + const char __user *buf, + unsigned long count, + void *data) +{ + char lbuf[16]; + + memset(lbuf, 0, sizeof(lbuf)); + + if (copy_from_user(lbuf, buf, 1)) { + return -EFAULT; + } + + set_wan_rf_enable(lbuf[0] != '0'); + + return count; +} + + +static int +proc_type_read( + char *page, + char **start, + off_t off, + int count, + int *eof, + void *data) +{ + *eof = 1; + + return sprintf(page, "%d\n", modem_type); +} + + +static int +proc_type_write( + struct file *file, + const char __user *buf, + unsigned long count, + void *data) +{ + char lbuf[16], ch; + + memset(lbuf, 0, sizeof(lbuf)); + + if (copy_from_user(lbuf, buf, 1)) { + return -EFAULT; + } + + ch = lbuf[0]; + if (ch >= '0' && ch <= '9') { + init_modem_type(ch - '0'); + + } else { + log_err("type_err:type=%c:invalid type\n", ch); + + } + + return count; +} + + +static int +proc_usb_read( + char *page, + char **start, + off_t off, + int count, + int *eof, + void *data) +{ + *eof = 1; + + return sprintf(page, "%d\n", get_wan_usb_enable()); +} + + +static int +proc_usb_write( + struct file *file, + const char __user *buf, + unsigned long count, + void *data) +{ + char lbuf[16]; + + memset(lbuf, 0, sizeof(lbuf)); + + if (copy_from_user(lbuf, buf, 1)) { + return -EFAULT; + } + + set_wan_usb_enable(lbuf[0] != '0'); + + return count; +} + + +static wan_usb_wake_callback_t usb_wake_callback = NULL; + +void +wan_set_usb_wake_callback( + wan_usb_wake_callback_t wake_fn) +{ + usb_wake_callback = wake_fn; +} +EXPORT_SYMBOL(wan_set_usb_wake_callback); + + +static void +wan_tph_notify( + void) +{ + kobject_uevent(&wan_dev->kobj, KOBJ_CHANGE); + log_info("tph::tph event occurred; notifying system of TPH\n"); +} + +#define NUM_ITER_TPH 2 /* 70 ms threshold = 2 * 35 ms */ +#define ITER_DELAY_TPH 35 +#define SENSE_ON2B_MASK (1 << 4) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)) +#define HOST_WAKE_SENSE REG_INT_SENSE1 +#else +#define HOST_WAKE_SENSE REG_INTERRUPT_SENSE_1 +#endif + +static void +wan_tph_event_handler( + void) +{ + unsigned long tph_cur_seconds; + int long_delta; + + tph_cur_seconds = CURRENT_TIME_SEC.tv_sec; + + long_delta = (tph_last_seconds <= tph_cur_seconds) ? + (tph_cur_seconds - tph_last_seconds > WAKE_EVENT_INTERVAL) : + 1; + + tph_last_seconds = tph_cur_seconds; + + if (modem_type == MODEM_TYPE_AD_DTP) { + int i; + unsigned int sense; + if (usb_wake_callback == NULL && long_delta) { + wan_tph_notify(); + tph_last_type = TPH_TYPE_RINGSMS; + } else { + /* determine if long or short pulse */ + for (i = 0; i < NUM_ITER_TPH; i++) { + pmic_read_reg(HOST_WAKE_SENSE, &sense, SENSE_ON2B_MASK); + if (sense & SENSE_ON2B_MASK) { + break; + } + msleep(ITER_DELAY_TPH); + } + + if (i >= NUM_ITER_TPH) { + /* SMS TPH: immediately following USB wake ok */ + if (long_delta || tph_last_type == TPH_TYPE_USBWAKE) { + wan_tph_notify(); + } + tph_last_type = TPH_TYPE_RINGSMS; + } else { + /* USB wake: multiples not allowed */ + if (long_delta) { + (*usb_wake_callback)(); + log_info("uwake::usb wake sent to ehci-hcd\n"); + } + tph_last_type = TPH_TYPE_USBWAKE; + } + } + } else { + // other modules may generate extraneous TPH events; filter out these extra events + if (long_delta) { + wan_tph_notify(); + } + tph_last_type = TPH_TYPE_RINGSMS; + } +} + +static int +wan_init( + void) +{ + extern void gpio_wan_init(void *); + extern void gpio_wan_exit(void *); + int ret; + + gpio_wan_init(wan_tph_event_handler); + + wan_major = register_chrdev(0, WAN_STRING_DEV, &mwan_ops); + if (wan_major < 0) { + ret = wan_major; + log_err("dev_err:device=" WAN_STRING_DEV ",err=%d:could not register device\n", ret); + goto exit1; + } + + wan_class = class_create(THIS_MODULE, WAN_STRING_CLASS); + if (IS_ERR(wan_class)) { + ret = PTR_ERR(wan_class); + log_err("class_err:err=%d:could not create class\n", ret); + goto exit2; + } + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)) + wan_dev = device_create_drvdata(wan_class, NULL, MKDEV(wan_major, 0), NULL, WAN_STRING_DEV); +#else + wan_dev = class_device_create(wan_class, NULL, MKDEV(wan_major, 0), NULL, WAN_STRING_DEV); +#endif + if (IS_ERR(wan_dev)) { + ret = PTR_ERR(wan_dev); + log_err("dev_err:err=%d:could not create class device\n", ret); + goto exit3; + } + + wan_set_power_status(WAN_OFF); + + ret = 0; + goto exit0; + +exit3: + class_destroy(wan_class); + wan_class = NULL; + +exit2: + unregister_chrdev(wan_major, WAN_STRING_DEV); + +exit1: + gpio_wan_exit(wan_tph_event_handler); + +exit0: + return ret; +} + + +static void +wan_exit( + void) +{ + extern void gpio_wan_exit(void *); + + wan_set_power_status(WAN_INVALID); + + gpio_wan_exit(wan_tph_event_handler); + + if (wan_dev != NULL) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)) + device_destroy(wan_class, MKDEV(wan_major, 0)); +#else + class_device_destroy(wan_class, MKDEV(wan_major, 0)); +#endif + wan_dev = NULL; + class_destroy(wan_class); + unregister_chrdev(wan_major, WAN_STRING_DEV); + } +} + + +static int __init +mwan_init( + void) +{ + int ret = 0; + + log_info("init:mario WAN hardware driver " VERSION "\n"); + + // create the "/proc/wan" parent directory + proc_wan_parent = create_proc_entry(PROC_WAN, S_IFDIR | S_IRUGO | S_IXUGO, NULL); + if (proc_wan_parent != NULL) { + + // create the "/proc/wan/power" entry + proc_wan_power = create_proc_entry(PROC_WAN_POWER, S_IWUSR | S_IRUGO, proc_wan_parent); + if (proc_wan_power != NULL) { + proc_wan_power->data = NULL; + proc_wan_power->read_proc = proc_power_read; + proc_wan_power->write_proc = proc_power_write; + } + + // create the "/proc/wan/enable" entry + proc_wan_enable = create_proc_entry(PROC_WAN_ENABLE, S_IWUSR | S_IRUGO, proc_wan_parent); + if (proc_wan_enable != NULL) { + proc_wan_enable->data = NULL; + proc_wan_enable->read_proc = proc_enable_read; + proc_wan_enable->write_proc = proc_enable_write; + } + + // create the "/proc/wan/type" entry + proc_wan_type = create_proc_entry(PROC_WAN_TYPE, S_IWUSR | S_IRUGO, proc_wan_parent); + if (proc_wan_type != NULL) { + proc_wan_type->data = NULL; + proc_wan_type->read_proc = proc_type_read; + proc_wan_type->write_proc = proc_type_write; + } + + // create the "/proc/wan/usb" entry + proc_wan_usb = create_proc_entry(PROC_WAN_USB, S_IWUSR | S_IRUGO, proc_wan_parent); + if (proc_wan_usb != NULL) { + proc_wan_usb->data = NULL; + proc_wan_usb->read_proc = proc_usb_read; + proc_wan_usb->write_proc = proc_usb_write; + } + + } else { + ret = -1; + + } + + if (ret == 0) { + wan_init(); + } + + return ret; +} + + +static void __exit +mwan_exit( + void) +{ + if (proc_wan_parent != NULL) { + remove_proc_entry(PROC_WAN_USB, proc_wan_parent); + remove_proc_entry(PROC_WAN_TYPE, proc_wan_parent); + remove_proc_entry(PROC_WAN_ENABLE, proc_wan_parent); + remove_proc_entry(PROC_WAN_POWER, proc_wan_parent); + remove_proc_entry(PROC_WAN, NULL); + + proc_wan_usb = proc_wan_type = proc_wan_enable = proc_wan_power = proc_wan_parent = NULL; + } + + wan_exit(); +} + + +module_init(mwan_init); +module_exit(mwan_exit); + +MODULE_DESCRIPTION("Mario WAN hardware driver"); +MODULE_AUTHOR("Lab126"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(VERSION); + diff -urN linux-2.6.26/drivers/net/wireless/Kconfig linux-2.6.26-lab126/drivers/net/wireless/Kconfig --- linux-2.6.26/drivers/net/wireless/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/wireless/Kconfig 2010-08-10 04:16:47.000000000 -0400 @@ -681,5 +681,6 @@ source "drivers/net/wireless/b43legacy/Kconfig" source "drivers/net/wireless/zd1211rw/Kconfig" source "drivers/net/wireless/rt2x00/Kconfig" +source "drivers/net/wireless/ath6k/Kconfig" endmenu diff -urN linux-2.6.26/drivers/net/wireless/Makefile linux-2.6.26-lab126/drivers/net/wireless/Makefile --- linux-2.6.26/drivers/net/wireless/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/net/wireless/Makefile 2010-08-10 04:16:47.000000000 -0400 @@ -62,3 +62,4 @@ obj-$(CONFIG_P54_COMMON) += p54/ obj-$(CONFIG_ATH5K) += ath5k/ +obj-$(CONFIG_ATHEROS_AR6000) += ath6k22.133/ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/Kconfig linux-2.6.26-lab126/drivers/net/wireless/ar6000/Kconfig --- linux-2.6.26/drivers/net/wireless/ar6000/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/Kconfig 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,14 @@ +# +# Atheros WiFi driver +# +config ATHEROS_AR6000 + tristate "Atheros AR6000 driver" + #depends on INPUT + help + Say Y here if you have an Atheros WiFi chip in your system + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called ar6000. + diff -urN linux-2.6.26/drivers/net/wireless/ar6000/Makefile linux-2.6.26-lab126/drivers/net/wireless/ar6000/Makefile --- linux-2.6.26/drivers/net/wireless/ar6000/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/Makefile 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,22 @@ +# +# Atheros WiFi driver +# + +INCLDIR=$(srctree)/drivers/net/wireless/ar6000/include +LINUX_INCLDIR=$(srctree)/drivers/net/wireless/ar6000/os/linux/include +EXTRA_CFLAGS += -I${INCLDIR} -I${LINUX_INCLDIR} -DSEND_EVENT_TO_APP -DHTC_RAW_INTERFACE -DAR6000REV2 + +obj-$(CONFIG_ATHEROS_AR6000) += ar6000.o + +ar6000-objs := hif.o ar6k.o ar6k_events.o htc_send.o htc_recv.o \ + htc_services.o htc.o bmi.o ar6000_drv.o ar6000_raw_if.o \ + netbuf.o wireless_ext.o ioctl.o engine.o common_drv.o \ + credit_dist.o wmi.o wlan_node.o wlan_recv_beacon.o \ + wlan_utils.o + +ATH_BUILD_TYPE := NATIVEMMC +ATH_BUS_TYPE := SDIO +ATH_BUS_SUBTYPE := linux_sdio +ATH_OS_SUB_TYPE := linux_2_6 +export ATH_BUS_SUBTYPE + diff -urN linux-2.6.26/drivers/net/wireless/ar6000/ar6000_drv.c linux-2.6.26-lab126/drivers/net/wireless/ar6000/ar6000_drv.c --- linux-2.6.26/drivers/net/wireless/ar6000/ar6000_drv.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/ar6000_drv.c 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,3309 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +/* + * This driver is a pseudo ethernet driver to access the Atheros AR6000 + * WLAN Device + */ + +#include "ar6000_drv.h" +#include "htc.h" +#include "engine.h" + +MODULE_LICENSE("GPL and additional rights"); + +#ifndef REORG_APTC_HEURISTICS +#undef ADAPTIVE_POWER_THROUGHPUT_CONTROL +#endif /* REORG_APTC_HEURISTICS */ + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +#define APTC_TRAFFIC_SAMPLING_INTERVAL 100 /* msec */ +#define APTC_UPPER_THROUGHPUT_THRESHOLD 3000 /* Kbps */ +#define APTC_LOWER_THROUGHPUT_THRESHOLD 2000 /* Kbps */ + +typedef struct aptc_traffic_record { + A_BOOL timerScheduled; + struct timeval samplingTS; + unsigned long bytesReceived; + unsigned long bytesTransmitted; +} APTC_TRAFFIC_RECORD; + +A_TIMER aptcTimer; +APTC_TRAFFIC_RECORD aptcTR; +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +int bmienable = 0; +int fwloadenable = 0; +unsigned int bypasswmi = 0; +unsigned int debuglevel = 1; +int tspecCompliance = ATHEROS_COMPLIANCE; +unsigned int busspeedlow = 0; +unsigned int onebitmode = 0; +unsigned int skipflash = 0; +unsigned int wmitimeout = 2; +unsigned int wlanNodeCaching = 1; +unsigned int enableuartprint = 0; +unsigned int logWmiRawMsgs = 0; +unsigned int enabletimerwar = 0; +unsigned int mbox_yield_limit = 99; +int reduce_credit_dribble = 1 + HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF; +int allow_trace_signal = 0; +#ifdef CONFIG_HOST_TCMD_SUPPORT +unsigned int testmode =0; +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param(fwloadenable, int, 0644); +module_param(bmienable, int, 0644); +module_param(bypasswmi, int, 0644); +module_param(debuglevel, int, 0644); +module_param(tspecCompliance, int, 0644); +module_param(onebitmode, int, 0644); +module_param(busspeedlow, int, 0644); +module_param(skipflash, int, 0644); +module_param(wmitimeout, int, 0644); +module_param(wlanNodeCaching, int, 0644); +module_param(logWmiRawMsgs, int, 0644); +module_param(enableuartprint, int, 0644); +module_param(enabletimerwar, int, 0644); +module_param(mbox_yield_limit, int, 0644); +module_param(reduce_credit_dribble, int, 0644); +module_param(allow_trace_signal, int, 0644); +#ifdef CONFIG_HOST_TCMD_SUPPORT +module_param(testmode, int, 0644); +#endif +#else + +#define __user +/* for linux 2.4 and lower */ +MODULE_PARM(bmienable,"i"); +MODULE_PARM(bypasswmi,"i"); +MODULE_PARM(debuglevel, "i"); +MODULE_PARM(onebitmode,"i"); +MODULE_PARM(busspeedlow, "i"); +MODULE_PARM(skipflash, "i"); +MODULE_PARM(wmitimeout, "i"); +MODULE_PARM(wlanNodeCaching, "i"); +MODULE_PARM(enableuartprint,"i"); +MODULE_PARM(logWmiRawMsgs, "i"); +MODULE_PARM(enabletimerwar,"i"); +MODULE_PARM(mbox_yield_limit,"i"); +MODULE_PARM(reduce_credit_dribble,"i"); +MODULE_PARM(allow_trace_signal,"i"); +#ifdef CONFIG_HOST_TCMD_SUPPORT +MODULE_PARM(testmode, "i"); +#endif +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10) +/* in 2.6.10 and later this is now a pointer to a uint */ +unsigned int _mboxnum = HTC_MAILBOX_NUM_MAX; +#define mboxnum &_mboxnum +#else +unsigned int mboxnum = HTC_MAILBOX_NUM_MAX; +#endif + +#ifdef DEBUG +A_UINT32 g_dbg_flags = DBG_DEFAULTS; +unsigned int debugflags = 0; +int debugdriver = 1; +unsigned int debughtc = 128; +unsigned int debugbmi = 1; +unsigned int debughif = 2; +unsigned int txcreditsavailable[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int txcreditsconsumed[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int txcreditintrenable[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int txcreditintrenableaggregate[HTC_MAILBOX_NUM_MAX] = {0}; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param(debugflags, int, 0644); +module_param(debugdriver, int, 0644); +module_param(debughtc, int, 0644); +module_param(debugbmi, int, 0644); +module_param(debughif, int, 0644); +module_param_array(txcreditsavailable, int, mboxnum, 0644); +module_param_array(txcreditsconsumed, int, mboxnum, 0644); +module_param_array(txcreditintrenable, int, mboxnum, 0644); +module_param_array(txcreditintrenableaggregate, int, mboxnum, 0644); +#else +/* linux 2.4 and lower */ +MODULE_PARM(debugflags,"i"); +MODULE_PARM(debugdriver, "i"); +MODULE_PARM(debughtc, "i"); +MODULE_PARM(debugbmi, "i"); +MODULE_PARM(debughif, "i"); +MODULE_PARM(txcreditsavailable, "0-3i"); +MODULE_PARM(txcreditsconsumed, "0-3i"); +MODULE_PARM(txcreditintrenable, "0-3i"); +MODULE_PARM(txcreditintrenableaggregate, "0-3i"); +#endif + +#endif /* DEBUG */ + +unsigned int resetok = 1; +unsigned int tx_attempt[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int tx_post[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int tx_complete[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int hifBusRequestNumMax = 40; +unsigned int war23838_disabled = 0; +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +unsigned int enableAPTCHeuristics = 1; +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param_array(tx_attempt, int, mboxnum, 0644); +module_param_array(tx_post, int, mboxnum, 0644); +module_param_array(tx_complete, int, mboxnum, 0644); +module_param(hifBusRequestNumMax, int, 0644); +module_param(war23838_disabled, int, 0644); +module_param(resetok, int, 0644); +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +module_param(enableAPTCHeuristics, int, 0644); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ +#else +MODULE_PARM(tx_attempt, "0-3i"); +MODULE_PARM(tx_post, "0-3i"); +MODULE_PARM(tx_complete, "0-3i"); +MODULE_PARM(hifBusRequestNumMax, "i"); +MODULE_PARM(war23838_disabled, "i"); +MODULE_PARM(resetok, "i"); +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +MODULE_PARM(enableAPTCHeuristics, "i"); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ +#endif + +#ifdef BLOCK_TX_PATH_FLAG +int blocktx = 0; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param(blocktx, int, 0644); +#else +MODULE_PARM(blocktx, "i"); +#endif +#endif /* BLOCK_TX_PATH_FLAG */ + + +int reconnect_flag = 0; + +/* Function declarations */ +static int ar6000_init_module(void); +static void ar6000_cleanup_module(void); + +int ar6000_init(struct net_device *dev); +static int ar6000_open(struct net_device *dev); +static int ar6000_close(struct net_device *dev); +static void ar6000_init_control_info(AR_SOFTC_T *ar); +static int ar6000_data_tx(struct sk_buff *skb, struct net_device *dev); + +static void ar6000_destroy(struct net_device *dev, unsigned int unregister); +static void ar6000_detect_error(unsigned long ptr); +static struct net_device_stats *ar6000_get_stats(struct net_device *dev); +static struct iw_statistics *ar6000_get_iwstats(struct net_device * dev); + +/* + * HTC service connection handlers + */ +static void ar6000_avail_ev(HTC_HANDLE HTCHandle); + +static void ar6000_unavail_ev(void *Instance); + +static void ar6000_target_failure(void *Instance, A_STATUS Status); + +static void ar6000_rx(void *Context, HTC_PACKET *pPacket); + +static void ar6000_rx_refill(void *Context,HTC_ENDPOINT_ID Endpoint); + +static void ar6000_tx_complete(void *Context, HTC_PACKET *pPacket); + +static HTC_SEND_FULL_ACTION ar6000_tx_queue_full(void *Context, HTC_PACKET *pPacket); + +/* + * Static variables + */ + +static struct net_device *ar6000_devices[MAX_AR6000]; +extern struct iw_handler_def ath_iw_handler_def; +DECLARE_WAIT_QUEUE_HEAD(arEvent); +static void ar6000_cookie_init(AR_SOFTC_T *ar); +static void ar6000_cookie_cleanup(AR_SOFTC_T *ar); +static void ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie); +static struct ar_cookie *ar6000_alloc_cookie(AR_SOFTC_T *ar); +static void ar6000_TxDataCleanup(AR_SOFTC_T *ar); + +#ifdef USER_KEYS +static A_STATUS ar6000_reinstall_keys(AR_SOFTC_T *ar,A_UINT8 key_op_ctrl); +#endif + + +static struct ar_cookie s_ar_cookie_mem[MAX_COOKIE_NUM]; + +#define HOST_INTEREST_ITEM_ADDRESS(ar, item) \ +((ar->arTargetType == TARGET_TYPE_AR6001) ? \ + AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \ + AR6002_HOST_INTEREST_ITEM_ADDRESS(item)) + + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +/* Looks like we need this for 2.4 kernels */ +static inline void *netdev_priv(struct net_device *dev) +{ + return(dev->priv); +} +#endif + +/* Debug log support */ + +/* + * Flag to govern whether the debug logs should be parsed in the kernel + * or reported to the application. + */ +#define REPORT_DEBUG_LOGS_TO_APP + +A_STATUS +ar6000_set_host_app_area(AR_SOFTC_T *ar) +{ + A_UINT32 address, data; + struct host_app_area_s host_app_area; + + /* Fetch the address of the host_app_area_s instance in the host interest area */ + address = HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest); + if (ar6000_ReadRegDiag(ar->arHifDevice, &address, &data) != A_OK) { + return A_ERROR; + } + address = data; + host_app_area.wmi_protocol_ver = WMI_PROTOCOL_VERSION; + if (ar6000_WriteDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&host_app_area, + sizeof(struct host_app_area_s)) != A_OK) + { + return A_ERROR; + } + + return A_OK; +} + +A_UINT32 +dbglog_get_debug_hdr_ptr(AR_SOFTC_T *ar) +{ + A_UINT32 param; + A_UINT32 address; + A_STATUS status; + + address = HOST_INTEREST_ITEM_ADDRESS(ar, hi_dbglog_hdr); + if ((status = ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)¶m, 4)) != A_OK) + { + param = 0; + } + + return param; +} + +/* + * The dbglog module has been initialized. Its ok to access the relevant + * data stuctures over the diagnostic window. + */ +void +ar6000_dbglog_init_done(AR_SOFTC_T *ar) +{ + ar->dbglog_init_done = TRUE; +} + +A_UINT32 +dbglog_get_debug_fragment(A_INT8 *datap, A_UINT32 len, A_UINT32 limit) +{ + A_INT32 *buffer; + A_UINT32 count; + A_UINT32 numargs; + A_UINT32 length; + A_UINT32 fraglen; + + count = fraglen = 0; + buffer = (A_INT32 *)datap; + length = (limit >> 2); + + if (len <= limit) { + fraglen = len; + } else { + while (count < length) { + numargs = DBGLOG_GET_NUMARGS(buffer[count]); + fraglen = (count << 2); + count += numargs + 1; + } + } + + return fraglen; +} + +void +dbglog_parse_debug_logs(A_INT8 *datap, A_UINT32 len) +{ + A_INT32 *buffer; + A_UINT32 count; + A_UINT32 timestamp; + A_UINT32 debugid; + A_UINT32 moduleid; + A_UINT32 numargs; + A_UINT32 length; + + count = 0; + buffer = (A_INT32 *)datap; + length = (len >> 2); + while (count < length) { + debugid = DBGLOG_GET_DBGID(buffer[count]); + moduleid = DBGLOG_GET_MODULEID(buffer[count]); + numargs = DBGLOG_GET_NUMARGS(buffer[count]); + timestamp = DBGLOG_GET_TIMESTAMP(buffer[count]); + switch (numargs) { + case 0: + AR_DEBUG_PRINTF("%d %d (%d)\n", moduleid, debugid, timestamp); + break; + + case 1: + AR_DEBUG_PRINTF("%d %d (%d): 0x%x\n", moduleid, debugid, + timestamp, buffer[count+1]); + break; + + case 2: + AR_DEBUG_PRINTF("%d %d (%d): 0x%x, 0x%x\n", moduleid, debugid, + timestamp, buffer[count+1], buffer[count+2]); + break; + + default: + AR_DEBUG_PRINTF("Invalid args: %d\n", numargs); + } + count += numargs + 1; + } +} + +int +ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar) +{ + struct dbglog_hdr_s debug_hdr; + struct dbglog_buf_s debug_buf; + A_UINT32 address; + A_UINT32 length; + A_UINT32 dropped; + A_UINT32 firstbuf; + A_UINT32 debug_hdr_ptr; + + if (!ar->dbglog_init_done) return A_ERROR; + + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + if (ar->dbgLogFetchInProgress) { + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + return A_EBUSY; + } + + /* block out others */ + ar->dbgLogFetchInProgress = TRUE; + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + debug_hdr_ptr = dbglog_get_debug_hdr_ptr(ar); + printk("debug_hdr_ptr: 0x%x\n", debug_hdr_ptr); + + /* Get the contents of the ring buffer */ + if (debug_hdr_ptr) { + address = debug_hdr_ptr; + length = sizeof(struct dbglog_hdr_s); + ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&debug_hdr, length); + address = (A_UINT32)debug_hdr.dbuf; + firstbuf = address; + dropped = debug_hdr.dropped; + length = sizeof(struct dbglog_buf_s); + ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&debug_buf, length); + + do { + address = (A_UINT32)debug_buf.buffer; + length = debug_buf.length; + if ((length) && (debug_buf.length <= debug_buf.bufsize)) { + /* Rewind the index if it is about to overrun the buffer */ + if (ar->log_cnt > (DBGLOG_HOST_LOG_BUFFER_SIZE - length)) { + ar->log_cnt = 0; + } + if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&ar->log_buffer[ar->log_cnt], length)) + { + break; + } + ar6000_dbglog_event(ar, dropped, &ar->log_buffer[ar->log_cnt], length); + ar->log_cnt += length; + } else { + AR_DEBUG_PRINTF("Length: %d (Total size: %d)\n", + debug_buf.length, debug_buf.bufsize); + } + + address = (A_UINT32)debug_buf.next; + length = sizeof(struct dbglog_buf_s); + if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&debug_buf, length)) + { + break; + } + + } while (address != firstbuf); + } + + ar->dbgLogFetchInProgress = FALSE; + + return A_OK; +} + +void +ar6000_dbglog_event(AR_SOFTC_T *ar, A_UINT32 dropped, + A_INT8 *buffer, A_UINT32 length) +{ +#ifdef REPORT_DEBUG_LOGS_TO_APP + #define MAX_WIRELESS_EVENT_SIZE 252 + /* + * Break it up into chunks of MAX_WIRELESS_EVENT_SIZE bytes of messages. + * There seems to be a limitation on the length of message that could be + * transmitted to the user app via this mechanism. + */ + A_UINT32 send, sent; + + sent = 0; + send = dbglog_get_debug_fragment(&buffer[sent], length - sent, + MAX_WIRELESS_EVENT_SIZE); + while (send) { + ar6000_send_event_to_app(ar, WMIX_DBGLOG_EVENTID, &buffer[sent], send); + sent += send; + send = dbglog_get_debug_fragment(&buffer[sent], length - sent, + MAX_WIRELESS_EVENT_SIZE); + } +#else + AR_DEBUG_PRINTF("Dropped logs: 0x%x\nDebug info length: %d\n", + dropped, length); + + /* Interpret the debug logs */ + dbglog_parse_debug_logs(buffer, length); +#endif /* REPORT_DEBUG_LOGS_TO_APP */ +} + + + +static int __init +ar6000_init_module(void) +{ + static int probed = 0; + A_STATUS status; + HTC_INIT_INFO initInfo; + + A_MEMZERO(&initInfo,sizeof(initInfo)); + initInfo.AddInstance = ar6000_avail_ev; + initInfo.DeleteInstance = ar6000_unavail_ev; + initInfo.TargetFailure = ar6000_target_failure; + + printk(KERN_INFO "ar6000_init_module\n"); + +#ifdef DEBUG + /* Set the debug flags if specified at load time */ + if(debugflags != 0) + { + g_dbg_flags = debugflags; + } +#endif + + if (probed) { + return -ENODEV; + } + probed++; + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + memset(&aptcTR, 0, sizeof(APTC_TRAFFIC_RECORD)); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +#ifdef CONFIG_HOST_GPIO_SUPPORT + ar6000_gpio_init(); +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + + status = HTCInit(&initInfo); + if(status != A_OK) + return -ENODEV; + + return 0; +} + +static void __exit +ar6000_cleanup_module(void) +{ + int i = 0; + struct net_device *ar6000_netdev; + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + /* Delete the Adaptive Power Control timer */ + if (timer_pending(&aptcTimer)) { + del_timer_sync(&aptcTimer); + } +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + + for (i=0; i < MAX_AR6000; i++) { + if (ar6000_devices[i] != NULL) { + ar6000_netdev = ar6000_devices[i]; + ar6000_devices[i] = NULL; + ar6000_destroy(ar6000_netdev, 1); + } + } + + /* shutting down HTC will cause the HIF layer to detach from the + * underlying bus driver which will cause the subsequent deletion of + * all HIF and HTC instances */ + HTCShutDown(); + + AR_DEBUG_PRINTF("ar6000_cleanup: success\n"); +} + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +void +aptcTimerHandler(unsigned long arg) +{ + A_UINT32 numbytes; + A_UINT32 throughput; + AR_SOFTC_T *ar; + A_STATUS status; + + ar = (AR_SOFTC_T *)arg; + A_ASSERT(ar != NULL); + A_ASSERT(!timer_pending(&aptcTimer)); + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + /* Get the number of bytes transferred */ + numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived; + aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0; + + /* Calculate and decide based on throughput thresholds */ + throughput = ((numbytes * 8)/APTC_TRAFFIC_SAMPLING_INTERVAL); /* Kbps */ + if (throughput < APTC_LOWER_THROUGHPUT_THRESHOLD) { + /* Enable Sleep and delete the timer */ + A_ASSERT(ar->arWmiReady == TRUE); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + status = wmi_powermode_cmd(ar->arWmi, REC_POWER); + AR6000_SPIN_LOCK(&ar->arLock, 0); + A_ASSERT(status == A_OK); + aptcTR.timerScheduled = FALSE; + } else { + A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0); + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); +} +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +#ifdef FW_AUTOLOAD +extern int fwengine( unsigned char *img, int size, void *ar); +extern int ar6k_reg_preload( int reg, unsigned int value ); + +/* Linux driver dependent utilities for fwengine */ +int load_binary( unsigned int addr, unsigned char *cp, void *arg ) +{ + int size = 0; + int adv = 5; + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + + cp++; + size |= ( *cp & 0xFF ); cp++; + size |= ( *cp & 0xFF ) << 8; cp++; + size |= ( *cp & 0xFF ) << 16; cp++; + size |= ( *cp & 0xFF ) << 24; cp++; + + if (BMIWriteMemory(ar->arHifDevice, addr, cp, size) != A_OK) + return(-1); + + adv += size; + return(adv); +} + +int execute_on_target( unsigned int address, unsigned int parm, void *arg ) +{ + int ret ; + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + ret = BMIExecute(ar->arHifDevice, address, &parm); + + return(ret); +} + +unsigned int get_target_reg( unsigned address, void *arg ) +{ + int ret ; + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + if (BMIReadMemory(ar->arHifDevice, address, (A_UCHAR *)&ret, 4)!= A_OK) { + /* And what am I supposed to do? */; + return( -1 ); + } + return( ret ); + +} + +int write_target_reg( unsigned address, unsigned value, void *arg ) +{ + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + if (BMIWriteMemory(ar->arHifDevice, address, (A_UCHAR *)&value, 4) != A_OK) + return(-1); + return(0); +} + +void bmidone( void *arg ) +{ + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + BMIDone(ar->arHifDevice); +} +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) +static struct device ar6kfwdev = { + .bus_id = "sdio0", +}; +#endif +#endif /* FW_AUTOLOAD */ + + +/* + * HTC Event handlers + */ +static void +ar6000_avail_ev(HTC_HANDLE HTCHandle) +{ + int i; + struct net_device *dev; + AR_SOFTC_T *ar; + int device_index = 0; + A_UINT32 param; + + AR_DEBUG_PRINTF("ar6000_available\n"); + + for (i=0; i < MAX_AR6000; i++) { + if (ar6000_devices[i] == NULL) { + break; + } + } + + if (i == MAX_AR6000) { + AR_DEBUG_PRINTF("ar6000_available: max devices reached\n"); + return; + } + + /* Save this. It gives a bit better readability especially since */ + /* we use another local "i" variable below. */ + device_index = i; + + A_ASSERT(HTCHandle != NULL); + +#ifdef CONFIG_MACH_LUIGI_LAB126 + dev = alloc_etherdev_ar6000(sizeof(AR_SOFTC_T)); +#else + dev = alloc_etherdev_(sizeof(AR_SOFTC_T)); +#endif + + if (dev == NULL) { + AR_DEBUG_PRINTF("ar6000_available: can't alloc etherdev\n"); + return; + } +#ifdef SET_MODULE_OWNER + SET_MODULE_OWNER(dev); +#endif + ether_setup(dev); + + if (dev->priv == NULL) { + printk(KERN_CRIT "ar6000_available: Could not allocate memory\n"); + return; + } + + A_MEMZERO(dev->priv, sizeof(AR_SOFTC_T)); + + ar = (AR_SOFTC_T *)dev->priv; + ar->arNetDev = dev; + ar->arHtcTarget = HTCHandle; + ar->arHifDevice = HTCGetHifDevice(HTCHandle); + ar->arWlanState = WLAN_ENABLED; + ar->arDeviceIndex = device_index; + + A_INIT_TIMER(&ar->arHBChallengeResp.timer, ar6000_detect_error, dev); + ar->arHBChallengeResp.seqNum = 0; + ar->arHBChallengeResp.outstanding = FALSE; + ar->arHBChallengeResp.missCnt = 0; + ar->arHBChallengeResp.frequency = AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT; + ar->arHBChallengeResp.missThres = AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT; + + ar6000_init_control_info(ar); + init_waitqueue_head(&arEvent); + sema_init(&ar->arSem, 1); + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + A_INIT_TIMER(&aptcTimer, aptcTimerHandler, ar); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + + /* + * If requested, perform some magic which requires no cooperation from + * the Target. It causes the Target to ignore flash and execute to the + * OS from ROM. + * + * This is intended to support recovery from a corrupted flash on Targets + * that support flash. + */ + if (skipflash) + { +#if defined(CONFIG_AR6002_REV1_FORCE_HOST) + extern A_STATUS ar6002_REV1_reset_force_host(HIF_DEVICE *hifDevice); + ar6002_REV1_reset_force_host(ar->arHifDevice); +#else + ar6000_reset_device_skipflash(ar->arHifDevice); +#endif /* CONFIG_AR6002_REV1_FORCE_HOST */ + } + + BMIInit(); + { + struct bmi_target_info targ_info; + + if (BMIGetTargetInfo(ar->arHifDevice, &targ_info) != A_OK) { + return; + } + + ar->arVersion.target_ver = targ_info.target_ver; + ar->arTargetType = targ_info.target_type; + + /* do any target-specific preparation that can be done through BMI */ + if (ar6000_prepare_target(ar->arHifDevice, + targ_info.target_type, + targ_info.target_ver) != A_OK) { + return; + } + + } + + if (enableuartprint) { + param = 1; + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_serial_enable), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for enableuartprint failed \n"); + return ; + } + AR_DEBUG_PRINTF("Serial console prints enabled\n"); + } + + /* Tell target which HTC version it is used*/ + param = HTC_PROTOCOL_VERSION; + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for htc version failed \n"); + return ; + } + +#ifdef CONFIG_HOST_TCMD_SUPPORT + if(testmode) { + ar->arTargetMode = AR6000_TCMD_MODE; + }else { + ar->arTargetMode = AR6000_WLAN_MODE; + } +#endif + if (enabletimerwar) { + A_UINT32 param; + + if (BMIReadMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIReadMemory for enabletimerwar failed \n"); + return; + } + + param |= HI_OPTION_TIMER_WAR; + + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for enabletimerwar failed \n"); + return; + } + AR_DEBUG_PRINTF("Timer WAR enabled\n"); + } + + // No need to reserve RAM space for patch as AR6001 is flash based + if (ar->arTargetType == TARGET_TYPE_AR6001) { + param = 0; + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_end_RAM_reserve_sz), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for hi_end_RAM_reserve_sz failed \n"); + return; + } + } + + + /* since BMIInit is called in the driver layer, we have to set the block + * size here for the target */ + + if (A_FAILED(ar6000_set_htc_params(ar->arHifDevice, + ar->arTargetType, + mbox_yield_limit, + 0 /* use default number of control buffers */ + ))) { + return; + } + + spin_lock_init(&ar->arLock); + + /* Don't install the init function if BMI is requested */ + if(!bmienable) + { + dev->init = ar6000_init; + } else { + AR_DEBUG_PRINTF(" BMI enabled \n"); + } + + dev->open = &ar6000_open; + dev->stop = &ar6000_close; + dev->hard_start_xmit = &ar6000_data_tx; + dev->get_stats = &ar6000_get_stats; + + /* dev->tx_timeout = ar6000_tx_timeout; */ + dev->do_ioctl = &ar6000_ioctl; + dev->watchdog_timeo = AR6000_TX_TIMEOUT; + ar6000_ioctl_iwsetup(&ath_iw_handler_def); + dev->wireless_handlers = &ath_iw_handler_def; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) + dev->get_wireless_stats = ar6000_get_iwstats; /*Displayed via proc fs */ +#else + ath_iw_handler_def.get_wireless_stats = ar6000_get_iwstats; /*Displayed via proc fs */ +#endif + + /* + * We need the OS to provide us with more headroom in order to + * perform dix to 802.3, WMI header encap, and the HTC header + */ + dev->hard_header_len = ETH_HLEN + sizeof(ATH_LLC_SNAP_HDR) + + sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN; + + /* This runs the init function */ + if (register_netdev(dev)) { + AR_DEBUG_PRINTF("ar6000_avail: register_netdev failed\n"); + ar6000_destroy(dev, 0); + return; + } + + HTCSetInstance(ar->arHtcTarget, ar); + + /* We only register the device in the global list if we succeed. */ + /* If the device is in the global list, it will be destroyed */ + /* when the module is unloaded. */ + ar6000_devices[device_index] = dev; + + AR_DEBUG_PRINTF("ar6000_avail: name=%s htcTarget=0x%x, dev=0x%x (%d), ar=0x%x\n", + dev->name, (A_UINT32)HTCHandle, (A_UINT32)dev, device_index, + (A_UINT32)ar); +#ifdef FW_AUTOLOAD + if( fwloadenable ) { + /* To compile firmware into driver the following struct should + * be declared static, it's field 'data' initialised with ptr to + * image and field 'size' with image size. 'request_firmware call + * in that case should be bypassed. TODO: #ifdef that + */ + const struct firmware *fw_entry; + int ret; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) + if(request_firmware(&fw_entry, "ar6k_firmware", &ar6kfwdev)!=0) { +#else + if(request_firmware(&fw_entry, "ar6k_firmware", &dev->dev)!=0) { +#endif +// if(request_firmware(NULL, "ar6k_firmware", &dev->dev)!=0) { + printk(KERN_ERR "ar6000_fwload: ar6k_firmware not available\n"); + ar6000_destroy(dev,1); + } else { + ar6k_reg_preload( 14, ar->arTargetType ); + ar6k_reg_preload( 15, ar->arVersion.target_ver ); + ret = fwengine(fw_entry->data, fw_entry->size, (void *)ar); + release_firmware(fw_entry); + if( ret ) { + printk(KERN_ERR "ar600_fwload: error loading firmware\n"); + ar6000_destroy(dev,1); + } + } + } +#endif /* FW_AUTOLOAD */ + +} + +static void ar6000_target_failure(void *Instance, A_STATUS Status) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Instance; + WMI_TARGET_ERROR_REPORT_EVENT errEvent; + static A_BOOL sip = FALSE; + + if (Status != A_OK) { + if (timer_pending(&ar->arHBChallengeResp.timer)) { + A_UNTIMEOUT(&ar->arHBChallengeResp.timer); + } + + /* try dumping target assertion information (if any) */ + ar6000_dump_target_assert_info(ar->arHifDevice,ar->arTargetType); + + /* + * Fetch the logs from the target via the diagnostic + * window. + */ + ar6000_dbglog_get_debug_logs(ar); + + /* Report the error only once */ + if (!sip) { + sip = TRUE; + errEvent.errorVal = WMI_TARGET_COM_ERR | + WMI_TARGET_FATAL_ERR; + ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID, + (A_UINT8 *)&errEvent, + sizeof(WMI_TARGET_ERROR_REPORT_EVENT)); + } + } +} + +static void +ar6000_unavail_ev(void *Instance) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Instance; + /* NULL out it's entry in the global list */ + ar6000_devices[ar->arDeviceIndex] = NULL; + ar6000_destroy(ar->arNetDev, 1); +} + +/* + * We need to differentiate between the surprise and planned removal of the + * device because of the following consideration: + * - In case of surprise removal, the hcd already frees up the pending + * for the device and hence there is no need to unregister the function + * driver inorder to get these requests. For planned removal, the function + * driver has to explictly unregister itself to have the hcd return all the + * pending requests before the data structures for the devices are freed up. + * Note that as per the current implementation, the function driver will + * end up releasing all the devices since there is no API to selectively + * release a particular device. + * - Certain commands issued to the target can be skipped for surprise + * removal since they will anyway not go through. + */ +static void +ar6000_destroy(struct net_device *dev, unsigned int unregister) +{ + AR_SOFTC_T *ar; + + AR_DEBUG_PRINTF("+ar6000_destroy \n"); + + if((dev == NULL) || ((ar = netdev_priv(dev)) == NULL)) + { + AR_DEBUG_PRINTF("%s(): Failed to get device structure.\n", __func__); + return; + } + + /* Stop the transmit queues */ + netif_stop_queue(dev); + + /* Disable the target and the interrupts associated with it */ + if (ar->arWmiReady == TRUE) + { + if (!bypasswmi) + { + if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) + { + AR_DEBUG_PRINTF("%s(): Disconnect\n", __func__); + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar6000_init_profile_info(ar); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + wmi_disconnect_cmd(ar->arWmi); + } + + ar6000_dbglog_get_debug_logs(ar); + ar->arWmiReady = FALSE; + ar->arConnected = FALSE; + ar->arConnectPending = FALSE; + wmi_shutdown(ar->arWmi); + ar->arWmiEnabled = FALSE; + ar->arWmi = NULL; + ar->arWlanState = WLAN_ENABLED; +#ifdef USER_KEYS + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT; + ar->user_key_ctrl = 0; +#endif + } + + AR_DEBUG_PRINTF("%s(): WMI stopped\n", __func__); + } + else + { + AR_DEBUG_PRINTF("%s(): WMI not ready 0x%08x 0x%08x\n", + __func__, (unsigned int) ar, (unsigned int) ar->arWmi); + + /* Shut down WMI if we have started it */ + if(ar->arWmiEnabled == TRUE) + { + AR_DEBUG_PRINTF("%s(): Shut down WMI\n", __func__); + wmi_shutdown(ar->arWmi); + ar->arWmiEnabled = FALSE; + ar->arWmi = NULL; + } + } + + /* stop HTC */ + HTCStop(ar->arHtcTarget); + + /* set the instance to NULL so we do not get called back on remove incase we + * we're explicity destroyed by module unload */ + HTCSetInstance(ar->arHtcTarget, NULL); + + if (resetok) { + /* try to reset the device if we can + * The driver may have been configure NOT to reset the target during + * a debug session */ + AR_DEBUG_PRINTF(" Attempting to reset target on instance destroy.... \n"); + ar6000_reset_device(ar->arHifDevice, ar->arTargetType, TRUE); + } else { + AR_DEBUG_PRINTF(" Host does not want target reset. \n"); + } + + /* Done with cookies */ + ar6000_cookie_cleanup(ar); + + /* Cleanup BMI */ + BMIInit(); + + /* Clear the tx counters */ + memset(tx_attempt, 0, sizeof(tx_attempt)); + memset(tx_post, 0, sizeof(tx_post)); + memset(tx_complete, 0, sizeof(tx_complete)); + + + /* Free up the device data structure */ + if( unregister ) + unregister_netdev(dev); +#ifndef free_netdev + kfree(dev); +#else + free_netdev(dev); +#endif + + AR_DEBUG_PRINTF("-ar6000_destroy \n"); +} + +static void ar6000_detect_error(unsigned long ptr) +{ + struct net_device *dev = (struct net_device *)ptr; + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_TARGET_ERROR_REPORT_EVENT errEvent; + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + if (ar->arHBChallengeResp.outstanding) { + ar->arHBChallengeResp.missCnt++; + } else { + ar->arHBChallengeResp.missCnt = 0; + } + + if (ar->arHBChallengeResp.missCnt > ar->arHBChallengeResp.missThres) { + /* Send Error Detect event to the application layer and do not reschedule the error detection module timer */ + ar->arHBChallengeResp.missCnt = 0; + ar->arHBChallengeResp.seqNum = 0; + errEvent.errorVal = WMI_TARGET_COM_ERR | WMI_TARGET_FATAL_ERR; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID, + (A_UINT8 *)&errEvent, + sizeof(WMI_TARGET_ERROR_REPORT_EVENT)); + return; + } + + /* Generate the sequence number for the next challenge */ + ar->arHBChallengeResp.seqNum++; + ar->arHBChallengeResp.outstanding = TRUE; + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + /* Send the challenge on the control channel */ + if (wmi_get_challenge_resp_cmd(ar->arWmi, ar->arHBChallengeResp.seqNum, DRV_HB_CHALLENGE) != A_OK) { + AR_DEBUG_PRINTF("Unable to send heart beat challenge\n"); + } + + + /* Reschedule the timer for the next challenge */ + A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0); +} + +void ar6000_init_profile_info(AR_SOFTC_T *ar) +{ + ar->arSsidLen = 0; + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arNetworkType = INFRA_NETWORK; + ar->arDot11AuthMode = OPEN_AUTH; + ar->arAuthMode = NONE_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arPairwiseCryptoLen = 0; + ar->arGroupCrypto = NONE_CRYPT; + ar->arGroupCryptoLen = 0; + A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList)); + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + A_MEMZERO(ar->arBssid, sizeof(ar->arBssid)); + ar->arBssChannel = 0; +} + +static void +ar6000_init_control_info(AR_SOFTC_T *ar) +{ + ar->arWmiEnabled = FALSE; + ar6000_init_profile_info(ar); + ar->arDefTxKeyIndex = 0; + A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList)); + ar->arChannelHint = 0; + ar->arListenInterval = MAX_LISTEN_INTERVAL; + ar->arVersion.host_ver = AR6K_SW_VERSION; + ar->arRssi = 0; + ar->arTxPwr = 0; + ar->arTxPwrSet = FALSE; + ar->arSkipScan = 0; + ar->arBeaconInterval = 0; + ar->arBitRate = 0; + ar->arMaxRetries = 0; + ar->arWmmEnabled = TRUE; +} + +static int +ar6000_open(struct net_device *dev) +{ + /* Wake up the queues */ + netif_wake_queue(dev); + + return 0; +} + +static int +ar6000_close(struct net_device *dev) +{ + netif_stop_queue(dev); + + return 0; +} + +/* connect to a service */ +static A_STATUS ar6000_connectservice(AR_SOFTC_T *ar, + HTC_SERVICE_CONNECT_REQ *pConnect, + char *pDesc) +{ + A_STATUS status; + HTC_SERVICE_CONNECT_RESP response; + + do { + + A_MEMZERO(&response,sizeof(response)); + + status = HTCConnectService(ar->arHtcTarget, + pConnect, + &response); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(" Failed to connect to %s service status:%d \n", + pDesc, status); + break; + } + switch (pConnect->ServiceID) { + case WMI_CONTROL_SVC : + if (ar->arWmiEnabled) { + /* set control endpoint for WMI use */ + wmi_set_control_ep(ar->arWmi, response.Endpoint); + } + /* save EP for fast lookup */ + ar->arControlEp = response.Endpoint; + break; + case WMI_DATA_BE_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_BE, response.Endpoint); + break; + case WMI_DATA_BK_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_BK, response.Endpoint); + break; + case WMI_DATA_VI_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_VI, response.Endpoint); + break; + case WMI_DATA_VO_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_VO, response.Endpoint); + break; + default: + AR_DEBUG_PRINTF("ServiceID not mapped %d\n", pConnect->ServiceID); + status = A_EINVAL; + break; + } + + } while (FALSE); + + return status; +} + +static void ar6000_TxDataCleanup(AR_SOFTC_T *ar) +{ + /* flush all the data (non-control) streams + * we only flush packets that are tagged as data, we leave any control packets that + * were in the TX queues alone */ + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_BE), + AR6K_DATA_PKT_TAG); + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_BK), + AR6K_DATA_PKT_TAG); + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_VI), + AR6K_DATA_PKT_TAG); + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_VO), + AR6K_DATA_PKT_TAG); +} + +HTC_ENDPOINT_ID +ar6000_ac2_endpoint_id ( void * devt, A_UINT8 ac) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *) devt; + return(arAc2EndpointID(ar, ac)); +} + +A_UINT8 +ar6000_endpoint_id2_ac(void * devt, HTC_ENDPOINT_ID ep ) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *) devt; + return(arEndpoint2Ac(ar, ep )); +} + +/* This function does one time initialization for the lifetime of the device */ +int ar6000_init(struct net_device *dev) +{ + AR_SOFTC_T *ar; + A_STATUS status; + A_INT32 timeleft; + + if((ar = netdev_priv(dev)) == NULL) + { + return(-EIO); + } + + /* Do we need to finish the BMI phase */ + if(BMIDone(ar->arHifDevice) != A_OK) + { + return -EIO; + } + + if (!bypasswmi) + { +#if 0 /* TBDXXX */ + if (ar->arVersion.host_ver != ar->arVersion.target_ver) { + A_PRINTF("WARNING: Host version 0x%x does not match Target " + " version 0x%x!\n", + ar->arVersion.host_ver, ar->arVersion.target_ver); + } +#endif + + /* Indicate that WMI is enabled (although not ready yet) */ + ar->arWmiEnabled = TRUE; + if ((ar->arWmi = wmi_init((void *) ar)) == NULL) + { + AR_DEBUG_PRINTF("%s() Failed to initialize WMI.\n", __func__); + return(-EIO); + } + + AR_DEBUG_PRINTF("%s() Got WMI @ 0x%08x.\n", __func__, + (unsigned int) ar->arWmi); + } + + do { + HTC_SERVICE_CONNECT_REQ connect; + + /* the reason we have to wait for the target here is that the driver layer + * has to init BMI in order to set the host block size, + */ + status = HTCWaitTarget(ar->arHtcTarget); + + if (A_FAILED(status)) { + break; + } + + A_MEMZERO(&connect,sizeof(connect)); + /* meta data is unused for now */ + connect.pMetaData = NULL; + connect.MetaDataLength = 0; + /* these fields are the same for all service endpoints */ + connect.EpCallbacks.pContext = ar; + connect.EpCallbacks.EpTxComplete = ar6000_tx_complete; + connect.EpCallbacks.EpRecv = ar6000_rx; + connect.EpCallbacks.EpRecvRefill = ar6000_rx_refill; + connect.EpCallbacks.EpSendFull = ar6000_tx_queue_full; + /* set the max queue depth so that our ar6000_tx_queue_full handler gets called. + * Linux has the peculiarity of not providing flow control between the + * NIC and the network stack. There is no API to indicate that a TX packet + * was sent which could provide some back pressure to the network stack. + * Under linux you would have to wait till the network stack consumed all sk_buffs + * before any back-flow kicked in. Which isn't very friendly. + * So we have to manage this ourselves */ + connect.MaxSendQueueDepth = 32; + + /* connect to control service */ + connect.ServiceID = WMI_CONTROL_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI CONTROL"); + if (A_FAILED(status)) { + break; + } + + /* for the remaining data services set the connection flag to reduce dribbling, + * if configured to do so */ + if (reduce_credit_dribble) { + connect.ConnectionFlags |= HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE; + /* the credit dribble trigger threshold is (reduce_credit_dribble - 1) for a value + * of 0-3 */ + connect.ConnectionFlags &= ~HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK; + connect.ConnectionFlags |= + ((A_UINT16)reduce_credit_dribble - 1) & HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK; + } + /* connect to best-effort service */ + connect.ServiceID = WMI_DATA_BE_SVC; + + status = ar6000_connectservice(ar, + &connect, + "WMI DATA BE"); + if (A_FAILED(status)) { + break; + } + + /* connect to back-ground + * map this to WMI LOW_PRI */ + connect.ServiceID = WMI_DATA_BK_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI DATA BK"); + if (A_FAILED(status)) { + break; + } + + /* connect to Video service, map this to + * to HI PRI */ + connect.ServiceID = WMI_DATA_VI_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI DATA VI"); + if (A_FAILED(status)) { + break; + } + + /* connect to VO service, this is currently not + * mapped to a WMI priority stream due to historical reasons. + * WMI originally defined 3 priorities over 3 mailboxes + * We can change this when WMI is reworked so that priorities are not + * dependent on mailboxes */ + connect.ServiceID = WMI_DATA_VO_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI DATA VO"); + if (A_FAILED(status)) { + break; + } + + A_ASSERT(arAc2EndpointID(ar,WMM_AC_BE) != 0); + A_ASSERT(arAc2EndpointID(ar,WMM_AC_BK) != 0); + A_ASSERT(arAc2EndpointID(ar,WMM_AC_VI) != 0); + A_ASSERT(arAc2EndpointID(ar,WMM_AC_VO) != 0); + + /* setup access class priority mappings */ + ar->arAcStreamPriMap[WMM_AC_BK] = 0; /* lowest */ + ar->arAcStreamPriMap[WMM_AC_BE] = 1; /* */ + ar->arAcStreamPriMap[WMM_AC_VI] = 2; /* */ + ar->arAcStreamPriMap[WMM_AC_VO] = 3; /* highest */ + + } while (FALSE); + + if (A_FAILED(status)) { + return (-EIO); + } + + /* + * give our connected endpoints some buffers + */ + + ar6000_rx_refill(ar, ar->arControlEp); + ar6000_rx_refill(ar, arAc2EndpointID(ar,WMM_AC_BE)); + + /* + * We will post the receive buffers only for SPE or endpoint ping testing so we are + * making it conditional on the 'bypasswmi' flag. + */ + if (bypasswmi) { + ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_BK)); + ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_VI)); + ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_VO)); + } + + /* setup credit distribution */ + ar6000_setup_credit_dist(ar->arHtcTarget, &ar->arCreditStateInfo); + + /* Since cookies are used for HTC transports, they should be */ + /* initialized prior to enabling HTC. */ + ar6000_cookie_init(ar); + + /* start HTC */ + status = HTCStart(ar->arHtcTarget); + + if (status != A_OK) { + if (ar->arWmiEnabled == TRUE) { + wmi_shutdown(ar->arWmi); + ar->arWmiEnabled = FALSE; + ar->arWmi = NULL; + } + ar6000_cookie_cleanup(ar); + return -EIO; + } + + if (!bypasswmi) { + /* Wait for Wmi event to be ready */ + timeleft = wait_event_interruptible_timeout(arEvent, + (ar->arWmiReady == TRUE), wmitimeout * HZ); + + if(!timeleft || signal_pending(current)) + { + AR_DEBUG_PRINTF("WMI is not ready or wait was interrupted\n"); +#if defined(DWSIM) /* TBDXXX */ + AR_DEBUG_PRINTF(".....but proceed anyway.\n"); +#else + return -EIO; +#endif + } + + AR_DEBUG_PRINTF("%s() WMI is ready\n", __func__); + + /* Communicate the wmi protocol verision to the target */ + if ((ar6000_set_host_app_area(ar)) != A_OK) { + AR_DEBUG_PRINTF("Unable to set the host app area\n"); + } + } + + ar->arNumDataEndPts = 1; + + return(0); +} + + +void +ar6000_bitrate_rx(void *devt, A_INT32 rateKbps) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arBitRate = rateKbps; + wake_up(&arEvent); +} + +void +ar6000_ratemask_rx(void *devt, A_UINT16 ratemask) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arRateMask = ratemask; + wake_up(&arEvent); +} + +void +ar6000_txPwr_rx(void *devt, A_UINT8 txPwr) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arTxPwr = txPwr; + wake_up(&arEvent); +} + + +void +ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + A_MEMCPY(ar->arChannelList, chanList, numChan * sizeof (A_UINT16)); + ar->arNumChannels = numChan; + + wake_up(&arEvent); +} + +A_UINT8 +ar6000_ibss_map_epid(struct sk_buff *skb, struct net_device *dev, A_UINT32 * mapNo) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + A_UINT8 *datap; + ATH_MAC_HDR *macHdr; + A_UINT32 i, eptMap; + + (*mapNo) = 0; + datap = A_NETBUF_DATA(skb); + macHdr = (ATH_MAC_HDR *)(datap + sizeof(WMI_DATA_HDR)); + if (IEEE80211_IS_MULTICAST(macHdr->dstMac)) { + return ENDPOINT_2; + } + + eptMap = -1; + for (i = 0; i < ar->arNodeNum; i ++) { + if (IEEE80211_ADDR_EQ(macHdr->dstMac, ar->arNodeMap[i].macAddress)) { + (*mapNo) = i + 1; + ar->arNodeMap[i].txPending ++; + return ar->arNodeMap[i].epId; + } + + if ((eptMap == -1) && !ar->arNodeMap[i].txPending) { + eptMap = i; + } + } + + if (eptMap == -1) { + eptMap = ar->arNodeNum; + ar->arNodeNum ++; + A_ASSERT(ar->arNodeNum <= MAX_NODE_NUM); + } + + A_MEMCPY(ar->arNodeMap[eptMap].macAddress, macHdr->dstMac, IEEE80211_ADDR_LEN); + + for (i = ENDPOINT_2; i <= ENDPOINT_5; i ++) { + if (!ar->arTxPending[i]) { + ar->arNodeMap[eptMap].epId = i; + break; + } + // No free endpoint is available, start redistribution on the inuse endpoints. + if (i == ENDPOINT_5) { + ar->arNodeMap[eptMap].epId = ar->arNexEpId; + ar->arNexEpId ++; + if (ar->arNexEpId > ENDPOINT_5) { + ar->arNexEpId = ENDPOINT_2; + } + } + } + + (*mapNo) = eptMap + 1; + ar->arNodeMap[eptMap].txPending ++; + + return ar->arNodeMap[eptMap].epId; +} + +#ifdef DEBUG +static void ar6000_dump_skb(struct sk_buff *skb) +{ + u_char *ch; + for (ch = A_NETBUF_DATA(skb); + (A_UINT32)ch < ((A_UINT32)A_NETBUF_DATA(skb) + + A_NETBUF_LEN(skb)); ch++) + { + AR_DEBUG_PRINTF("%2.2x ", *ch); + } + AR_DEBUG_PRINTF("\n"); +} +#endif + +static int +ar6000_data_tx(struct sk_buff *skb, struct net_device *dev) +{ +#define AC_NOT_MAPPED 99 + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + A_UINT8 ac = AC_NOT_MAPPED; + HTC_ENDPOINT_ID eid = ENDPOINT_UNUSED; + A_UINT32 mapNo = 0; + int len; + struct ar_cookie *cookie; + A_BOOL checkAdHocPsMapping = FALSE; + +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,13) + skb->list = NULL; +#endif + + AR_DEBUG2_PRINTF("ar6000_data_tx start - skb=0x%x, data=0x%x, len=0x%x\n", + (A_UINT32)skb, (A_UINT32)A_NETBUF_DATA(skb), + A_NETBUF_LEN(skb)); + +#ifdef CONFIG_HOST_TCMD_SUPPORT + /* TCMD doesnt support any data, free the buf and return */ + if(ar->arTargetMode == AR6000_TCMD_MODE) { + A_NETBUF_FREE(skb); + return 0; + } +#endif + do { + + if (ar->arWmiReady == FALSE && bypasswmi == 0) { + break; + } + +#ifdef BLOCK_TX_PATH_FLAG + if (blocktx) { + break; + } +#endif /* BLOCK_TX_PATH_FLAG */ + + if (ar->arWmiEnabled) { + if (A_NETBUF_HEADROOM(skb) < dev->hard_header_len) { + struct sk_buff *newbuf; + /* + * We really should have gotten enough headroom but sometimes + * we still get packets with not enough headroom. Copy the packet. + */ + len = A_NETBUF_LEN(skb); + newbuf = A_NETBUF_ALLOC(len); + if (newbuf == NULL) { + break; + } + A_NETBUF_PUT(newbuf, len); + A_MEMCPY(A_NETBUF_DATA(newbuf), A_NETBUF_DATA(skb), len); + A_NETBUF_FREE(skb); + skb = newbuf; + /* fall through and assemble header */ + } + + if (wmi_dix_2_dot3(ar->arWmi, skb) != A_OK) { + AR_DEBUG_PRINTF("ar6000_data_tx - wmi_dix_2_dot3 failed\n"); + break; + } + + if (wmi_data_hdr_add(ar->arWmi, skb, DATA_MSGTYPE) != A_OK) { + AR_DEBUG_PRINTF("ar6000_data_tx - wmi_data_hdr_add failed\n"); + break; + } + + if ((ar->arNetworkType == ADHOC_NETWORK) && + ar->arIbssPsEnable && ar->arConnected) { + /* flag to check adhoc mapping once we take the lock below: */ + checkAdHocPsMapping = TRUE; + + } else { + /* get the stream mapping */ + ac = wmi_implicit_create_pstream(ar->arWmi, skb, 0, ar->arWmmEnabled); + } + + } else { + struct iphdr *ipHdr; + /* + * the endpoint is directly based on the TOS field in the IP + * header **** only for testing ****** + */ + ipHdr = A_NETBUF_DATA(skb) + sizeof(ATH_MAC_HDR); + /* here we map the TOS field to an access class, this is for + * the endpointping test application. The application uses 0,1,2,3 + * for the TOS field to emulate writing to mailboxes. The number is + * used to map directly to an access class */ + ac = (ipHdr->tos >> 1) & 0x3; + } + + } while (FALSE); + + /* did we succeed ? */ + if ((ac == AC_NOT_MAPPED) && !checkAdHocPsMapping) { + /* cleanup and exit */ + A_NETBUF_FREE(skb); + AR6000_STAT_INC(ar, tx_dropped); + AR6000_STAT_INC(ar, tx_aborted_errors); + return 0; + } + + cookie = NULL; + + /* take the lock to protect driver data */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + do { + + if (checkAdHocPsMapping) { + eid = ar6000_ibss_map_epid(skb, dev, &mapNo); + }else { + eid = arAc2EndpointID (ar, ac); + } + /* validate that the endpoint is connected */ + if (eid == 0 || eid == ENDPOINT_UNUSED ) { + AR_DEBUG_PRINTF(" eid %d is NOT mapped!\n", eid); + break; + } + /* allocate resource for this packet */ + cookie = ar6000_alloc_cookie(ar); + + if (cookie != NULL) { + /* update counts while the lock is held */ + ar->arTxPending[eid]++; + ar->arTotalTxDataPending++; + } + + } while (FALSE); + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + if (cookie != NULL) { + cookie->arc_bp[0] = (A_UINT32)skb; + cookie->arc_bp[1] = mapNo; + SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt, + cookie, + A_NETBUF_DATA(skb), + A_NETBUF_LEN(skb), + eid, + AR6K_DATA_PKT_TAG); + +#ifdef DEBUG + if (debugdriver >= 3) { + ar6000_dump_skb(skb); + } +#endif + /* HTC interface is asynchronous, if this fails, cleanup will happen in + * the ar6000_tx_complete callback */ + HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt); + } else { + /* no packet to send, cleanup */ + A_NETBUF_FREE(skb); + AR6000_STAT_INC(ar, tx_dropped); + AR6000_STAT_INC(ar, tx_aborted_errors); + } + + return 0; +} + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +static void +tvsub(register struct timeval *out, register struct timeval *in) +{ + if((out->tv_usec -= in->tv_usec) < 0) { + out->tv_sec--; + out->tv_usec += 1000000; + } + out->tv_sec -= in->tv_sec; +} + +void +applyAPTCHeuristics(AR_SOFTC_T *ar) +{ + A_UINT32 duration; + A_UINT32 numbytes; + A_UINT32 throughput; + struct timeval ts; + A_STATUS status; + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + if ((enableAPTCHeuristics) && (!aptcTR.timerScheduled)) { + do_gettimeofday(&ts); + tvsub(&ts, &aptcTR.samplingTS); + duration = ts.tv_sec * 1000 + ts.tv_usec / 1000; /* ms */ + numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived; + + if (duration > APTC_TRAFFIC_SAMPLING_INTERVAL) { + /* Initialize the time stamp and byte count */ + aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0; + do_gettimeofday(&aptcTR.samplingTS); + + /* Calculate and decide based on throughput thresholds */ + throughput = ((numbytes * 8) / duration); + if (throughput > APTC_UPPER_THROUGHPUT_THRESHOLD) { + /* Disable Sleep and schedule a timer */ + A_ASSERT(ar->arWmiReady == TRUE); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + status = wmi_powermode_cmd(ar->arWmi, MAX_PERF_POWER); + AR6000_SPIN_LOCK(&ar->arLock, 0); + A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0); + aptcTR.timerScheduled = TRUE; + } + } + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); +} +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +static HTC_SEND_FULL_ACTION ar6000_tx_queue_full(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + HTC_SEND_FULL_ACTION action = HTC_SEND_FULL_KEEP; + A_BOOL stopNet = FALSE; + HTC_ENDPOINT_ID Endpoint = HTC_GET_ENDPOINT_FROM_PKT(pPacket); + + do { + + if (bypasswmi) { + /* for endpointping testing no other checks need to be made + * we can however still allow the network to stop */ + stopNet = TRUE; + break; + } + + if (Endpoint == ar->arControlEp) { + /* under normal WMI if this is getting full, then something is running rampant + * the host should not be exhausting the WMI queue with too many commands + * the only exception to this is during testing using endpointping */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + /* set flag to handle subsequent messages */ + ar->arWMIControlEpFull = TRUE; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + AR_DEBUG_PRINTF("WMI Control Endpoint is FULL!!! \n"); + /* no need to stop the network */ + stopNet = FALSE; + break; + } + + /* if we get here, we are dealing with data endpoints getting full */ + + if (HTC_GET_TAG_FROM_PKT(pPacket) == AR6K_CONTROL_PKT_TAG) { + /* don't drop control packets issued on ANY data endpoint */ + break; + } + + if (ar->arNetworkType == ADHOC_NETWORK) { + /* in adhoc mode, we cannot differentiate traffic priorities so there is no need to + * continue, however we should stop the network */ + stopNet = TRUE; + break; + } + + if (ar->arAcStreamPriMap[arEndpoint2Ac(ar,Endpoint)] < ar->arHiAcStreamActivePri) { + /* this stream's priority is less than the highest active priority, we + * give preference to the highest priority stream by directing + * HTC to drop the packet that overflowed */ + action = HTC_SEND_FULL_DROP; + /* since we are dropping packets, no need to stop the network */ + stopNet = FALSE; + break; + } + + } while (FALSE); + + if (stopNet) { + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arNetQueueStopped = TRUE; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + /* one of the data endpoints queues is getting full..need to stop network stack + * the queue will resume in ar6000_tx_complete() */ + netif_stop_queue(ar->arNetDev); + } + + return action; +} + + +static void +ar6000_tx_complete(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + void *cookie = (void *)pPacket->pPktContext; + struct sk_buff *skb = NULL; + A_UINT32 mapNo = 0; + A_STATUS status; + struct ar_cookie * ar_cookie; + HTC_ENDPOINT_ID eid; + A_BOOL wakeEvent = FALSE; + + status = pPacket->Status; + ar_cookie = (struct ar_cookie *)cookie; + skb = (struct sk_buff *)ar_cookie->arc_bp[0]; + eid = pPacket->Endpoint ; + mapNo = ar_cookie->arc_bp[1]; + + A_ASSERT(skb); + A_ASSERT(pPacket->pBuffer == A_NETBUF_DATA(skb)); + + if (A_SUCCESS(status)) { + A_ASSERT(pPacket->ActualLength == A_NETBUF_LEN(skb)); + } + + AR_DEBUG2_PRINTF("ar6000_tx_complete skb=0x%x data=0x%x len=0x%x eid=%d ", + (A_UINT32)skb, (A_UINT32)pPacket->pBuffer, + pPacket->ActualLength, + eid); + + /* lock the driver as we update internal state */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + ar->arTxPending[eid]--; + + if ((eid != ar->arControlEp) || bypasswmi) { + ar->arTotalTxDataPending--; + } + + if (eid == ar->arControlEp) + { + if (ar->arWMIControlEpFull) { + /* since this packet completed, the WMI EP is no longer full */ + ar->arWMIControlEpFull = FALSE; + } + + if (ar->arTxPending[eid] == 0) { + wakeEvent = TRUE; + } + } + + if (A_FAILED(status)) { + AR6000_STAT_INC(ar, tx_errors); + if (status != A_NO_RESOURCE) { + AR_DEBUG_PRINTF("%s() -TX ERROR, status: 0x%x\n", __func__, + status); + } + } else { + AR_DEBUG2_PRINTF("OK\n"); + AR6000_STAT_INC(ar, tx_packets); + ar->arNetStats.tx_bytes += A_NETBUF_LEN(skb); +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + aptcTR.bytesTransmitted += a_netbuf_to_len(skb); + applyAPTCHeuristics(ar); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + } + + // TODO this needs to be looked at + if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable + && (eid != ar->arControlEp) && mapNo) + { + mapNo --; + ar->arNodeMap[mapNo].txPending --; + + if (!ar->arNodeMap[mapNo].txPending && (mapNo == (ar->arNodeNum - 1))) { + A_UINT32 i; + for (i = ar->arNodeNum; i > 0; i --) { + if (!ar->arNodeMap[i - 1].txPending) { + A_MEMZERO(&ar->arNodeMap[i - 1], sizeof(struct ar_node_mapping)); + ar->arNodeNum --; + } else { + break; + } + } + } + } + + /* Freeing a cookie should not be contingent on either of */ + /* these flags, just if we have a cookie or not. */ + /* Can we even get here without a cookie? Fix later. */ + if (ar->arWmiReady == TRUE || (bypasswmi)) + { + ar6000_free_cookie(ar, cookie); + } + + if (ar->arNetQueueStopped) { + ar->arNetQueueStopped = FALSE; + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + /* lock is released, we can freely call other kernel APIs */ + + A_NETBUF_FREE(skb); + + if ((ar->arConnected == TRUE) || (bypasswmi)) { + if (status != A_ECANCELED) { + /* don't wake the queue if we are flushing, other wise it will just + * keep queueing packets, which will keep failing */ + netif_wake_queue(ar->arNetDev); + } + } + + if (wakeEvent) { + wake_up(&arEvent); + } + +} + +/* + * Receive event handler. This is called by HTC when a packet is received + */ +int pktcount; +static void +ar6000_rx(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + struct sk_buff *skb = (struct sk_buff *)pPacket->pPktContext; + int minHdrLen; + A_STATUS status = pPacket->Status; + HTC_ENDPOINT_ID ept = pPacket->Endpoint; + + A_ASSERT((status != A_OK) || + (pPacket->pBuffer == (A_NETBUF_DATA(skb) + HTC_HEADER_LEN))); + + AR_DEBUG2_PRINTF("ar6000_rx ar=0x%x eid=%d, skb=0x%x, data=0x%x, len=0x%x ", + (A_UINT32)ar, ept, (A_UINT32)skb, (A_UINT32)pPacket->pBuffer, + pPacket->ActualLength); + if (status != A_OK) { + AR_DEBUG2_PRINTF("ERR\n"); + } else { + AR_DEBUG2_PRINTF("OK\n"); + } + + /* take lock to protect buffer counts + * and adaptive power throughput state */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + ar->arRxBuffers[ept]--; + + if (A_SUCCESS(status)) { + AR6000_STAT_INC(ar, rx_packets); + ar->arNetStats.rx_bytes += pPacket->ActualLength; +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + aptcTR.bytesReceived += a_netbuf_to_len(skb); + applyAPTCHeuristics(ar); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + + A_NETBUF_PUT(skb, pPacket->ActualLength + HTC_HEADER_LEN); + A_NETBUF_PULL(skb, HTC_HEADER_LEN); + +#ifdef DEBUG + if (debugdriver >= 2) { + ar6000_dump_skb(skb); + } +#endif /* DEBUG */ + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + if (status != A_OK) { + AR6000_STAT_INC(ar, rx_errors); + A_NETBUF_FREE(skb); + } else if (ar->arWmiEnabled == TRUE) { + if (ept == ar->arControlEp) { + /* + * this is a wmi control msg + */ + wmi_control_rx(ar->arWmi, skb); + } else { + /* + * this is a wmi data packet + */ + minHdrLen = sizeof (WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + + sizeof(ATH_LLC_SNAP_HDR); + + if ((pPacket->ActualLength < minHdrLen) || + (pPacket->ActualLength > AR6000_BUFFER_SIZE)) + { + /* + * packet is too short or too long + */ + AR_DEBUG_PRINTF("TOO SHORT or TOO LONG\n"); + AR6000_STAT_INC(ar, rx_errors); + AR6000_STAT_INC(ar, rx_length_errors); + A_NETBUF_FREE(skb); + } else { +#if 0 + /* Access RSSI values here */ + AR_DEBUG_PRINTF("RSSI %d\n", + ((WMI_DATA_HDR *) A_NETBUF_DATA(skb))->rssi); +#endif + wmi_data_hdr_remove(ar->arWmi, skb); + wmi_dot3_2_dix(ar->arWmi, skb); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + /* + * extra push and memcpy, for eth_type_trans() of 2.4 kernel + * will pull out hard_header_len bytes of the skb. + */ + A_NETBUF_PUSH(skb, sizeof(WMI_DATA_HDR) + sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN); + A_MEMCPY(A_NETBUF_DATA(skb), A_NETBUF_DATA(skb) + sizeof(WMI_DATA_HDR) + + sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN, sizeof(ATH_MAC_HDR)); +#endif + if ((ar->arNetDev->flags & IFF_UP) == IFF_UP) + { + skb->dev = ar->arNetDev; + skb->protocol = eth_type_trans(skb, ar->arNetDev); + netif_rx(skb); + } + else + { + A_NETBUF_FREE(skb); + } + } + } + } else { + if ((ar->arNetDev->flags & IFF_UP) == IFF_UP) + { + skb->dev = ar->arNetDev; + skb->protocol = eth_type_trans(skb, ar->arNetDev); + netif_rx(skb); + } + else + { + A_NETBUF_FREE(skb); + } + } + + if (status != A_ECANCELED) { + /* + * HTC provides A_ECANCELED status when it doesn't want to be refilled + * (probably due to a shutdown) + */ + ar6000_rx_refill(Context, ept); + } + + +} + +static void +ar6000_rx_refill(void *Context, HTC_ENDPOINT_ID Endpoint) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + void *osBuf; + int RxBuffers; + int buffersToRefill; + HTC_PACKET *pPacket; + + buffersToRefill = (int)AR6000_MAX_RX_BUFFERS - + (int)ar->arRxBuffers[Endpoint]; + + if (buffersToRefill <= 0) { + /* fast return, nothing to fill */ + return; + } + + AR_DEBUG2_PRINTF("ar6000_rx_refill: providing htc with %d buffers at eid=%d\n", + buffersToRefill, Endpoint); + + for (RxBuffers = 0; RxBuffers < buffersToRefill; RxBuffers++) { + osBuf = A_NETBUF_ALLOC(AR6000_BUFFER_SIZE); + if (NULL == osBuf) { + break; + } + /* the HTC packet wrapper is at the head of the reserved area + * in the skb */ + pPacket = (HTC_PACKET *)(A_NETBUF_HEAD(osBuf)); + /* set re-fill info */ + SET_HTC_PACKET_INFO_RX_REFILL(pPacket,osBuf,A_NETBUF_DATA(osBuf),AR6000_BUFFER_SIZE,Endpoint); + /* add this packet */ + HTCAddReceivePkt(ar->arHtcTarget, pPacket); + } + + /* update count */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arRxBuffers[Endpoint] += RxBuffers; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); +} + +static struct net_device_stats * +ar6000_get_stats(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + return &ar->arNetStats; +} + +static struct iw_statistics * +ar6000_get_iwstats(struct net_device * dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + TARGET_STATS *pStats = &ar->arTargetStats; + struct iw_statistics * pIwStats = &ar->arIwStats; + + if ((ar->arWmiReady == FALSE) + /* + * The in_atomic function is used to determine if the scheduling is + * allowed in the current context or not. This was introduced in 2.6 + * From what I have read on the differences between 2.4 and 2.6, the + * 2.4 kernel did not support preemption and so this check might not + * be required for 2.4 kernels. + */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + || (in_atomic()) +#endif + ) + { + pIwStats->status = 0; + pIwStats->qual.qual = 0; + pIwStats->qual.level =0; + pIwStats->qual.noise = 0; + pIwStats->discard.code =0; + pIwStats->discard.retries=0; + pIwStats->miss.beacon =0; + return pIwStats; + } + if (down_interruptible(&ar->arSem)) { + pIwStats->status = 0; + return pIwStats; + } + + + ar->statsUpdatePending = TRUE; + + if(wmi_get_stats_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + pIwStats->status = 0; + return pIwStats; + } + + wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ); + + if (signal_pending(current)) { + AR_DEBUG_PRINTF("ar6000 : WMI get stats timeout \n"); + up(&ar->arSem); + pIwStats->status = 0; + return pIwStats; + } + pIwStats->status = 1 ; + pIwStats->qual.qual = pStats->cs_aveBeacon_rssi; + pIwStats->qual.level =pStats->cs_aveBeacon_rssi + 161; /* noise is -95 dBm */ + pIwStats->qual.noise = pStats->noise_floor_calibation; + pIwStats->discard.code = pStats->rx_decrypt_err; + pIwStats->discard.retries = pStats->tx_retry_cnt; + pIwStats->miss.beacon = pStats->cs_bmiss_cnt; + up(&ar->arSem); + return pIwStats; +} + +void +ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap, A_UINT32 vers) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + struct net_device *dev = ar->arNetDev; + + ar->arWmiReady = TRUE; + wake_up(&arEvent); + A_MEMCPY(dev->dev_addr, datap, AR6000_ETH_ADDR_LEN); + AR_DEBUG_PRINTF("mac address = %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", + dev->dev_addr[0], dev->dev_addr[1], + dev->dev_addr[2], dev->dev_addr[3], + dev->dev_addr[4], dev->dev_addr[5]); + + ar->arPhyCapability = phyCap; + ar->arVersion.wlan_ver = vers; +} + +void +ar6000_connect_event(AR_SOFTC_T *ar, A_UINT16 channel, A_UINT8 *bssid, + A_UINT16 listenInterval, A_UINT16 beaconInterval, + NETWORK_TYPE networkType, A_UINT8 beaconIeLen, + A_UINT8 assocReqLen, A_UINT8 assocRespLen, + A_UINT8 *assocInfo) +{ + union iwreq_data wrqu; + int i, beacon_ie_pos, assoc_resp_ie_pos, assoc_req_ie_pos; + static const char *tag1 = "ASSOCINFO(ReqIEs="; + static const char *tag2 = "ASSOCRESPIE="; + static const char *beaconIetag = "BEACONIE="; + char buf[WMI_CONTROL_MSG_MAX_LEN * 2 + strlen(tag1) + 1]; + char *pos; + A_UINT8 key_op_ctrl; + + A_MEMCPY(ar->arBssid, bssid, sizeof(ar->arBssid)); + ar->arBssChannel = channel; + + A_PRINTF("AR6000 connected event on freq %d ", channel); + A_PRINTF("with bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x " + " listenInterval=%d, beaconInterval = %d, beaconIeLen = %d assocReqLen=%d" + " assocRespLen =%d\n", + bssid[0], bssid[1], bssid[2], + bssid[3], bssid[4], bssid[5], + listenInterval, beaconInterval, + beaconIeLen, assocReqLen, assocRespLen); + if (networkType & ADHOC_NETWORK) { + if (networkType & ADHOC_CREATOR) { + A_PRINTF("Network: Adhoc (Creator)\n"); + } else { + A_PRINTF("Network: Adhoc (Joiner)\n"); + } + } else { + A_PRINTF("Network: Infrastructure\n"); + } + + if (beaconIeLen && (sizeof(buf) > (9 + beaconIeLen * 2))) { + AR_DEBUG_PRINTF("\nBeaconIEs= "); + + beacon_ie_pos = 0; + A_MEMZERO(buf, sizeof(buf)); + sprintf(buf, "%s", beaconIetag); + pos = buf + 9; + for (i = beacon_ie_pos; i < beacon_ie_pos + beaconIeLen; i++) { + AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]); + sprintf(pos, "%2.2x", assocInfo[i]); + pos += 2; + } + AR_DEBUG_PRINTF("\n"); + + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + } + + if (assocRespLen && (sizeof(buf) > (12 + (assocRespLen * 2)))) + { + assoc_resp_ie_pos = beaconIeLen + assocReqLen + + sizeof(A_UINT16) + /* capinfo*/ + sizeof(A_UINT16) + /* status Code */ + sizeof(A_UINT16) ; /* associd */ + A_MEMZERO(buf, sizeof(buf)); + sprintf(buf, "%s", tag2); + pos = buf + 12; + AR_DEBUG_PRINTF("\nAssocRespIEs= "); + /* + * The Association Response Frame w.o. the WLAN header is delivered to + * the host, so skip over to the IEs + */ + for (i = assoc_resp_ie_pos; i < assoc_resp_ie_pos + assocRespLen - 6; i++) + { + AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]); + sprintf(pos, "%2.2x", assocInfo[i]); + pos += 2; + } + AR_DEBUG_PRINTF("\n"); + + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + } + + if (assocReqLen && (sizeof(buf) > (17 + (assocReqLen * 2)))) { + /* + * assoc Request includes capability and listen interval. Skip these. + */ + assoc_req_ie_pos = beaconIeLen + + sizeof(A_UINT16) + /* capinfo*/ + sizeof(A_UINT16); /* listen interval */ + + A_MEMZERO(buf, sizeof(buf)); + sprintf(buf, "%s", tag1); + pos = buf + 17; + AR_DEBUG_PRINTF("AssocReqIEs= "); + for (i = assoc_req_ie_pos; i < assoc_req_ie_pos + assocReqLen - 4; i++) { + AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]); + sprintf(pos, "%2.2x", assocInfo[i]); + pos += 2;; + } + AR_DEBUG_PRINTF("\n"); + + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + } + +#ifdef USER_KEYS + if (ar->user_savedkeys_stat == USER_SAVEDKEYS_STAT_RUN && + ar->user_saved_keys.keyOk == TRUE) + { + + key_op_ctrl = KEY_OP_VALID_MASK & ~KEY_OP_INIT_TSC; + if (ar->user_key_ctrl & AR6000_USER_SETKEYS_RSC_UNCHANGED) { + key_op_ctrl &= ~KEY_OP_INIT_RSC; + } else { + key_op_ctrl |= KEY_OP_INIT_RSC; + } + ar6000_reinstall_keys(ar, key_op_ctrl); + } +#endif /* USER_KEYS */ + + /* flush data queues */ + ar6000_TxDataCleanup(ar); + + netif_wake_queue(ar->arNetDev); + + if ((OPEN_AUTH == ar->arDot11AuthMode) && + (NONE_AUTH == ar->arAuthMode) && + (WEP_CRYPT == ar->arPairwiseCrypto)) + { + if (!ar->arConnected) { + ar6000_install_static_wep_keys(ar); + } + } + + ar->arConnected = TRUE; + ar->arConnectPending = FALSE; + + reconnect_flag = 0; + + A_MEMZERO(&wrqu, sizeof(wrqu)); + A_MEMCPY(wrqu.addr.sa_data, bssid, IEEE80211_ADDR_LEN); + wrqu.addr.sa_family = ARPHRD_ETHER; + wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL); + if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable) { + A_MEMZERO(ar->arNodeMap, sizeof(ar->arNodeMap)); + ar->arNodeNum = 0; + ar->arNexEpId = ENDPOINT_2; + } + if (!ar->arUserBssFilter) { + wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0); + } + +} + +void ar6000_set_numdataendpts(AR_SOFTC_T *ar, A_UINT32 num) +{ + A_ASSERT(num <= (HTC_MAILBOX_NUM_MAX - 1)); + ar->arNumDataEndPts = num; +} + +void +ar6000_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason, A_UINT8 *bssid, + A_UINT8 assocRespLen, A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus) +{ + A_UINT8 i; + + A_PRINTF("AR6000 disconnected"); + if (bssid[0] || bssid[1] || bssid[2] || bssid[3] || bssid[4] || bssid[5]) { + A_PRINTF(" from %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", + bssid[0], bssid[1], bssid[2], bssid[3], bssid[4], bssid[5]); + } + + AR_DEBUG_PRINTF("\nDisconnect Reason is %d", reason); + AR_DEBUG_PRINTF("\nProtocol Reason/Status Code is %d", protocolReasonStatus); + AR_DEBUG_PRINTF("\nAssocResp Frame = %s", + assocRespLen ? " " : "NULL"); + for (i = 0; i < assocRespLen; i++) { + if (!(i % 0x10)) { + AR_DEBUG_PRINTF("\n"); + } + AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]); + } + AR_DEBUG_PRINTF("\n"); + /* + * If the event is due to disconnect cmd from the host, only they the target + * would stop trying to connect. Under any other condition, target would + * keep trying to connect. + * + */ + if( reason == DISCONNECT_CMD) + { + ar->arConnectPending = FALSE; + if (!ar->arUserBssFilter) { + wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0); + } + } else { + ar->arConnectPending = TRUE; + if (((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x11)) || + ((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x0) && (reconnect_flag == 1))) { + ar->arConnected = TRUE; + return; + } + } + ar->arConnected = FALSE; + + if( (reason != CSERV_DISCONNECT) || (reconnect_flag != 1) ) { + reconnect_flag = 0; + } + +#ifdef USER_KEYS + if (reason != CSERV_DISCONNECT) + { + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT; + ar->user_key_ctrl = 0; + } +#endif /* USER_KEYS */ + + netif_stop_queue(ar->arNetDev); + A_MEMZERO(ar->arBssid, sizeof(ar->arBssid)); + ar->arBssChannel = 0; + ar->arBeaconInterval = 0; + + ar6000_TxDataCleanup(ar); +} + +void +ar6000_regDomain_event(AR_SOFTC_T *ar, A_UINT32 regCode) +{ + A_PRINTF("AR6000 Reg Code = 0x%x\n", regCode); + ar->arRegCode = regCode; +} + +void +ar6000_neighborReport_event(AR_SOFTC_T *ar, int numAps, WMI_NEIGHBOR_INFO *info) +{ + static const char *tag = "PRE-AUTH"; + char buf[128]; + union iwreq_data wrqu; + int i; + + AR_DEBUG_PRINTF("AR6000 Neighbor Report Event\n"); + for (i=0; i < numAps; info++, i++) { + AR_DEBUG_PRINTF("bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", + info->bssid[0], info->bssid[1], info->bssid[2], + info->bssid[3], info->bssid[4], info->bssid[5]); + if (info->bssFlags & WMI_PREAUTH_CAPABLE_BSS) { + AR_DEBUG_PRINTF("preauth-cap"); + } + if (info->bssFlags & WMI_PMKID_VALID_BSS) { + AR_DEBUG_PRINTF(" pmkid-valid\n"); + continue; /* we skip bss if the pmkid is already valid */ + } + AR_DEBUG_PRINTF("\n"); + snprintf(buf, sizeof(buf), "%s%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x", + tag, + info->bssid[0], info->bssid[1], info->bssid[2], + info->bssid[3], info->bssid[4], info->bssid[5], + i, info->bssFlags); + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + } +} + +void +ar6000_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast) +{ + static const char *tag = "MLME-MICHAELMICFAILURE.indication"; + char buf[128]; + union iwreq_data wrqu; + + A_PRINTF("AR6000 TKIP MIC error received for keyid %d %scast\n", + keyid, ismcast ? "multi": "uni"); + snprintf(buf, sizeof(buf), "%s(keyid=%d %sicast)", tag, keyid, + ismcast ? "mult" : "un"); + memset(&wrqu, 0, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); +} + +void +ar6000_scanComplete_event(AR_SOFTC_T *ar, A_STATUS status) +{ + if (!ar->arUserBssFilter) { + wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0); + } + AR_DEBUG_PRINTF("AR6000 scan complete: %d\n", status); +} + +void +ar6000_targetStats_event(AR_SOFTC_T *ar, WMI_TARGET_STATS *pTarget) +{ + TARGET_STATS *pStats = &ar->arTargetStats; + A_UINT8 ac; + + A_PRINTF("AR6000 updating target stats\n"); + + // Update the RSSI of the connected bss. + if (ar->arConnected) { + bss_t *pConnBss = NULL; + + pConnBss = wmi_find_node(ar->arWmi,ar->arBssid); + if (pConnBss) + { + pConnBss->ni_rssi = pTarget->cservStats.cs_aveBeacon_rssi; + pConnBss->ni_snr = pTarget->cservStats.cs_aveBeacon_snr; + wmi_node_return(ar->arWmi, pConnBss); + } + } + + pStats->tx_packets += pTarget->txrxStats.tx_stats.tx_packets; + pStats->tx_bytes += pTarget->txrxStats.tx_stats.tx_bytes; + pStats->tx_unicast_pkts += pTarget->txrxStats.tx_stats.tx_unicast_pkts; + pStats->tx_unicast_bytes += pTarget->txrxStats.tx_stats.tx_unicast_bytes; + pStats->tx_multicast_pkts += pTarget->txrxStats.tx_stats.tx_multicast_pkts; + pStats->tx_multicast_bytes += pTarget->txrxStats.tx_stats.tx_multicast_bytes; + pStats->tx_broadcast_pkts += pTarget->txrxStats.tx_stats.tx_broadcast_pkts; + pStats->tx_broadcast_bytes += pTarget->txrxStats.tx_stats.tx_broadcast_bytes; + pStats->tx_rts_success_cnt += pTarget->txrxStats.tx_stats.tx_rts_success_cnt; + for(ac = 0; ac < WMM_NUM_AC; ac++) + pStats->tx_packet_per_ac[ac] += pTarget->txrxStats.tx_stats.tx_packet_per_ac[ac]; + pStats->tx_errors += pTarget->txrxStats.tx_stats.tx_errors; + pStats->tx_failed_cnt += pTarget->txrxStats.tx_stats.tx_failed_cnt; + pStats->tx_retry_cnt += pTarget->txrxStats.tx_stats.tx_retry_cnt; + pStats->tx_mult_retry_cnt += pTarget->txrxStats.tx_stats.tx_mult_retry_cnt; + pStats->tx_rts_fail_cnt += pTarget->txrxStats.tx_stats.tx_rts_fail_cnt; + pStats->tx_unicast_rate = wmi_get_rate(pTarget->txrxStats.tx_stats.tx_unicast_rate); + + pStats->rx_packets += pTarget->txrxStats.rx_stats.rx_packets; + pStats->rx_bytes += pTarget->txrxStats.rx_stats.rx_bytes; + pStats->rx_unicast_pkts += pTarget->txrxStats.rx_stats.rx_unicast_pkts; + pStats->rx_unicast_bytes += pTarget->txrxStats.rx_stats.rx_unicast_bytes; + pStats->rx_multicast_pkts += pTarget->txrxStats.rx_stats.rx_multicast_pkts; + pStats->rx_multicast_bytes += pTarget->txrxStats.rx_stats.rx_multicast_bytes; + pStats->rx_broadcast_pkts += pTarget->txrxStats.rx_stats.rx_broadcast_pkts; + pStats->rx_broadcast_bytes += pTarget->txrxStats.rx_stats.rx_broadcast_bytes; + pStats->rx_fragment_pkt += pTarget->txrxStats.rx_stats.rx_fragment_pkt; + pStats->rx_errors += pTarget->txrxStats.rx_stats.rx_errors; + pStats->rx_crcerr += pTarget->txrxStats.rx_stats.rx_crcerr; + pStats->rx_key_cache_miss += pTarget->txrxStats.rx_stats.rx_key_cache_miss; + pStats->rx_decrypt_err += pTarget->txrxStats.rx_stats.rx_decrypt_err; + pStats->rx_duplicate_frames += pTarget->txrxStats.rx_stats.rx_duplicate_frames; + pStats->rx_unicast_rate = wmi_get_rate(pTarget->txrxStats.rx_stats.rx_unicast_rate); + + + pStats->tkip_local_mic_failure + += pTarget->txrxStats.tkipCcmpStats.tkip_local_mic_failure; + pStats->tkip_counter_measures_invoked + += pTarget->txrxStats.tkipCcmpStats.tkip_counter_measures_invoked; + pStats->tkip_replays += pTarget->txrxStats.tkipCcmpStats.tkip_replays; + pStats->tkip_format_errors += pTarget->txrxStats.tkipCcmpStats.tkip_format_errors; + pStats->ccmp_format_errors += pTarget->txrxStats.tkipCcmpStats.ccmp_format_errors; + pStats->ccmp_replays += pTarget->txrxStats.tkipCcmpStats.ccmp_replays; + + + pStats->power_save_failure_cnt += pTarget->pmStats.power_save_failure_cnt; + pStats->noise_floor_calibation = pTarget->noise_floor_calibation; + + pStats->cs_bmiss_cnt += pTarget->cservStats.cs_bmiss_cnt; + pStats->cs_lowRssi_cnt += pTarget->cservStats.cs_lowRssi_cnt; + pStats->cs_connect_cnt += pTarget->cservStats.cs_connect_cnt; + pStats->cs_disconnect_cnt += pTarget->cservStats.cs_disconnect_cnt; + pStats->cs_aveBeacon_snr = pTarget->cservStats.cs_aveBeacon_snr; + pStats->cs_aveBeacon_rssi = pTarget->cservStats.cs_aveBeacon_rssi; + pStats->cs_lastRoam_msec = pTarget->cservStats.cs_lastRoam_msec; + pStats->cs_snr = pTarget->cservStats.cs_snr; + pStats->cs_rssi = pTarget->cservStats.cs_rssi; + + pStats->lq_val = pTarget->lqVal; + + pStats->wow_num_pkts_dropped += pTarget->wowStats.wow_num_pkts_dropped; + pStats->wow_num_host_pkt_wakeups += pTarget->wowStats.wow_num_host_pkt_wakeups; + pStats->wow_num_host_event_wakeups += pTarget->wowStats.wow_num_host_event_wakeups; + pStats->wow_num_events_discarded += pTarget->wowStats.wow_num_events_discarded; + + if (ar->statsUpdatePending) { + ar->statsUpdatePending = FALSE; + wake_up(&arEvent); + } +} + +void +ar6000_rssiThreshold_event(AR_SOFTC_T *ar, WMI_RSSI_THRESHOLD_VAL newThreshold, A_INT16 rssi) +{ + USER_RSSI_THOLD userRssiThold; + + /* Send an event to the app */ + userRssiThold.tag = ar->rssi_map[newThreshold].tag; + userRssiThold.rssi = rssi + SIGNAL_QUALITY_NOISE_FLOOR; + A_PRINTF("rssi Threshold range = %d tag = %d rssi = %d\n", newThreshold, + userRssiThold.tag, userRssiThold.rssi); + + ar6000_send_event_to_app(ar, WMI_RSSI_THRESHOLD_EVENTID,(A_UINT8 *)&userRssiThold, sizeof(USER_RSSI_THOLD)); +} + + +void +ar6000_hbChallengeResp_event(AR_SOFTC_T *ar, A_UINT32 cookie, A_UINT32 source) +{ + if (source == APP_HB_CHALLENGE) { + /* Report it to the app in case it wants a positive acknowledgement */ + ar6000_send_event_to_app(ar, WMIX_HB_CHALLENGE_RESP_EVENTID, + (A_UINT8 *)&cookie, sizeof(cookie)); + } else { + /* This would ignore the replys that come in after their due time */ + if (cookie == ar->arHBChallengeResp.seqNum) { + ar->arHBChallengeResp.outstanding = FALSE; + } + } +} + + +void +ar6000_reportError_event(AR_SOFTC_T *ar, WMI_TARGET_ERROR_VAL errorVal) +{ + char *errString[] = { + [WMI_TARGET_PM_ERR_FAIL] "WMI_TARGET_PM_ERR_FAIL", + [WMI_TARGET_KEY_NOT_FOUND] "WMI_TARGET_KEY_NOT_FOUND", + [WMI_TARGET_DECRYPTION_ERR] "WMI_TARGET_DECRYPTION_ERR", + [WMI_TARGET_BMISS] "WMI_TARGET_BMISS", + [WMI_PSDISABLE_NODE_JOIN] "WMI_PSDISABLE_NODE_JOIN" + }; + + A_PRINTF("AR6000 Error on Target. Error = 0x%x\n", errorVal); + + /* One error is reported at a time, and errorval is a bitmask */ + if(errorVal & (errorVal - 1)) + return; + + A_PRINTF("AR6000 Error type = "); + switch(errorVal) + { + case WMI_TARGET_PM_ERR_FAIL: + case WMI_TARGET_KEY_NOT_FOUND: + case WMI_TARGET_DECRYPTION_ERR: + case WMI_TARGET_BMISS: + case WMI_PSDISABLE_NODE_JOIN: + A_PRINTF("%s\n", errString[errorVal]); + break; + default: + A_PRINTF("INVALID\n"); + break; + } + +} + + +void +ar6000_cac_event(AR_SOFTC_T *ar, A_UINT8 ac, A_UINT8 cacIndication, + A_UINT8 statusCode, A_UINT8 *tspecSuggestion) +{ + WMM_TSPEC_IE *tspecIe; + + /* + * This is the TSPEC IE suggestion from AP. + * Suggestion provided by AP under some error + * cases, could be helpful for the host app. + * Check documentation. + */ + tspecIe = (WMM_TSPEC_IE *)tspecSuggestion; + + /* + * What do we do, if we get TSPEC rejection? One thought + * that comes to mind is implictly delete the pstream... + */ + A_PRINTF("AR6000 CAC notification. " + "AC = %d, cacIndication = 0x%x, statusCode = 0x%x\n", + ac, cacIndication, statusCode); +} + +void +ar6000_channel_change_event(AR_SOFTC_T *ar, A_UINT16 oldChannel, + A_UINT16 newChannel) +{ + A_PRINTF("Channel Change notification\nOld Channel: %d, New Channel: %d\n", + oldChannel, newChannel); +} + +#define AR6000_PRINT_BSSID(_pBss) do { \ + A_PRINTF("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",\ + (_pBss)[0],(_pBss)[1],(_pBss)[2],(_pBss)[3],\ + (_pBss)[4],(_pBss)[5]); \ +} while(0) + +void +ar6000_roam_tbl_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_TBL *pTbl) +{ + A_UINT8 i; + + A_PRINTF("ROAM TABLE NO OF ENTRIES is %d ROAM MODE is %d\n", + pTbl->numEntries, pTbl->roamMode); + for (i= 0; i < pTbl->numEntries; i++) { + A_PRINTF("[%d]bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", i, + pTbl->bssRoamInfo[i].bssid[0], pTbl->bssRoamInfo[i].bssid[1], + pTbl->bssRoamInfo[i].bssid[2], + pTbl->bssRoamInfo[i].bssid[3], + pTbl->bssRoamInfo[i].bssid[4], + pTbl->bssRoamInfo[i].bssid[5]); + A_PRINTF("RSSI %d RSSIDT %d LAST RSSI %d UTIL %d ROAM_UTIL %d" + " BIAS %d\n", + pTbl->bssRoamInfo[i].rssi, + pTbl->bssRoamInfo[i].rssidt, + pTbl->bssRoamInfo[i].last_rssi, + pTbl->bssRoamInfo[i].util, + pTbl->bssRoamInfo[i].roam_util, + pTbl->bssRoamInfo[i].bias); + } +} + +void +ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters, WMI_GET_WOW_LIST_REPLY *wow_reply) +{ + A_UINT8 i,j; + + /*Each event now contains exactly one filter, see bug 26613*/ + A_PRINTF("WOW pattern %d of %d patterns\n", wow_reply->this_filter_num, wow_reply->num_filters); + A_PRINTF("wow mode = %s host mode = %s\n", + (wow_reply->wow_mode == 0? "disabled":"enabled"), + (wow_reply->host_mode == 1 ? "awake":"asleep")); + + + /*If there are no patterns, the reply will only contain generic + WoW information. Pattern information will exist only if there are + patterns present. Bug 26716*/ + + /* If this event contains pattern information, display it*/ + if (wow_reply->this_filter_num) { + i=0; + A_PRINTF("id=%d size=%d offset=%d\n", + wow_reply->wow_filters[i].wow_filter_id, + wow_reply->wow_filters[i].wow_filter_size, + wow_reply->wow_filters[i].wow_filter_offset); + A_PRINTF("wow pattern = "); + for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) { + A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_pattern[j]); + } + + A_PRINTF("\nwow mask = "); + for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) { + A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_mask[j]); + } + A_PRINTF("\n"); + } +} + +/* + * Report the Roaming related data collected on the target + */ +void +ar6000_display_roam_time(WMI_TARGET_ROAM_TIME *p) +{ + A_PRINTF("Disconnect Data : BSSID: "); + AR6000_PRINT_BSSID(p->disassoc_bssid); + A_PRINTF(" RSSI %d DISASSOC Time %d NO_TXRX_TIME %d\n", + p->disassoc_bss_rssi,p->disassoc_time, + p->no_txrx_time); + A_PRINTF("Connect Data: BSSID: "); + AR6000_PRINT_BSSID(p->assoc_bssid); + A_PRINTF(" RSSI %d ASSOC Time %d TXRX_TIME %d\n", + p->assoc_bss_rssi,p->assoc_time, + p->allow_txrx_time); + A_PRINTF("Last Data Tx Time (b4 Disassoc) %d "\ + "First Data Tx Time (after Assoc) %d\n", + p->last_data_txrx_time, p->first_data_txrx_time); +} + +void +ar6000_roam_data_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_DATA *p) +{ + switch (p->roamDataType) { + case ROAM_DATA_TIME: + ar6000_display_roam_time(&p->u.roamTime); + break; + default: + break; + } +} + +void +ar6000_bssInfo_event_rx(AR_SOFTC_T *ar, A_UINT8 *datap, int len) +{ + struct sk_buff *skb; + WMI_BSS_INFO_HDR *bih = (WMI_BSS_INFO_HDR *)datap; + + + if (!ar->arMgmtFilter) { + return; + } + if (((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_BEACON) && + (bih->frameType != BEACON_FTYPE)) || + ((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_PROBE_RESP) && + (bih->frameType != PROBERESP_FTYPE))) + { + return; + } + + if ((skb = A_NETBUF_ALLOC_RAW(len)) != NULL) { + + A_NETBUF_PUT(skb, len); + A_MEMCPY(A_NETBUF_DATA(skb), datap, len); + skb->dev = ar->arNetDev; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) + A_MEMCPY(skb_mac_header(skb), A_NETBUF_DATA(skb), 6); +#else + skb->mac.raw = A_NETBUF_DATA(skb); +#endif + skb->ip_summed = CHECKSUM_NONE; + skb->pkt_type = PACKET_OTHERHOST; + skb->protocol = __constant_htons(0x0019); + netif_rx(skb); + } +} + +A_UINT32 wmiSendCmdNum; + +A_STATUS +ar6000_control_tx(void *devt, void *osbuf, HTC_ENDPOINT_ID eid) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + A_STATUS status = A_OK; + struct ar_cookie *cookie = NULL; + int i; + + /* take lock to protect ar6000_alloc_cookie() */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + do { + + AR_DEBUG2_PRINTF("ar_contrstatus = ol_tx: skb=0x%x, len=0x%x eid =%d\n", + (A_UINT32)osbuf, A_NETBUF_LEN(osbuf), eid); + + if (ar->arWMIControlEpFull && (eid == ar->arControlEp)) { + /* control endpoint is full, don't allocate resources, we + * are just going to drop this packet */ + cookie = NULL; + AR_DEBUG_PRINTF(" WMI Control EP full, dropping packet : 0x%X, len:%d \n", + (A_UINT32)osbuf, A_NETBUF_LEN(osbuf)); + } else { + cookie = ar6000_alloc_cookie(ar); + } + + if (cookie == NULL) { + status = A_NO_MEMORY; + break; + } + + if(logWmiRawMsgs) { + A_PRINTF("WMI cmd send, msgNo %d :", wmiSendCmdNum); + for(i = 0; i < a_netbuf_to_len(osbuf); i++) + A_PRINTF("%x ", ((A_UINT8 *)a_netbuf_to_data(osbuf))[i]); + A_PRINTF("\n"); + } + + wmiSendCmdNum++; + + } while (FALSE); + + if (cookie != NULL) { + /* got a structure to send it out on */ + ar->arTxPending[eid]++; + + if (eid != ar->arControlEp) { + ar->arTotalTxDataPending++; + } + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + if (cookie != NULL) { + cookie->arc_bp[0] = (A_UINT32)osbuf; + cookie->arc_bp[1] = 0; + SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt, + cookie, + A_NETBUF_DATA(osbuf), + A_NETBUF_LEN(osbuf), + eid, + AR6K_CONTROL_PKT_TAG); + /* this interface is asynchronous, if there is an error, cleanup will happen in the + * TX completion callback */ + HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt); + status = A_OK; + } + + return status; +} + +/* indicate tx activity or inactivity on a WMI stream */ +void ar6000_indicate_tx_activity(void *devt, A_UINT8 TrafficClass, A_BOOL Active) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + HTC_ENDPOINT_ID eid ; + int i; + + if (ar->arWmiEnabled) { + eid = arAc2EndpointID(ar, TrafficClass); + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + ar->arAcStreamActive[TrafficClass] = Active; + + if (Active) { + /* when a stream goes active, keep track of the active stream with the highest priority */ + + if (ar->arAcStreamPriMap[TrafficClass] > ar->arHiAcStreamActivePri) { + /* set the new highest active priority */ + ar->arHiAcStreamActivePri = ar->arAcStreamPriMap[TrafficClass]; + } + + } else { + /* when a stream goes inactive, we may have to search for the next active stream + * that is the highest priority */ + + if (ar->arHiAcStreamActivePri == ar->arAcStreamPriMap[TrafficClass]) { + + /* the highest priority stream just went inactive */ + + /* reset and search for the "next" highest "active" priority stream */ + ar->arHiAcStreamActivePri = 0; + for (i = 0; i < WMM_NUM_AC; i++) { + if (ar->arAcStreamActive[i]) { + if (ar->arAcStreamPriMap[i] > ar->arHiAcStreamActivePri) { + /* set the new highest active priority */ + ar->arHiAcStreamActivePri = ar->arAcStreamPriMap[i]; + } + } + } + } + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + } else { + /* for mbox ping testing, the traffic class is mapped directly as a stream ID, + * see handling of AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE in ioctl.c */ + eid = (HTC_ENDPOINT_ID)TrafficClass; + } + + /* notify HTC, this may cause credit distribution changes */ + + HTCIndicateActivityChange(ar->arHtcTarget, + eid, + Active); + +} + +module_init(ar6000_init_module); +module_exit(ar6000_cleanup_module); + +/* Init cookie queue */ +static void +ar6000_cookie_init(AR_SOFTC_T *ar) +{ + A_UINT32 i; + + ar->arCookieList = NULL; + A_MEMZERO(s_ar_cookie_mem, sizeof(s_ar_cookie_mem)); + + for (i = 0; i < MAX_COOKIE_NUM; i++) { + ar6000_free_cookie(ar, &s_ar_cookie_mem[i]); + } +} + +/* cleanup cookie queue */ +static void +ar6000_cookie_cleanup(AR_SOFTC_T *ar) +{ + /* It is gone .... */ + ar->arCookieList = NULL; +} + +/* Init cookie queue */ +static void +ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie) +{ + /* Insert first */ + A_ASSERT(ar != NULL); + A_ASSERT(cookie != NULL); + cookie->arc_list_next = ar->arCookieList; + ar->arCookieList = cookie; +} + +/* cleanup cookie queue */ +static struct ar_cookie * +ar6000_alloc_cookie(AR_SOFTC_T *ar) +{ + struct ar_cookie *cookie; + + cookie = ar->arCookieList; + if(cookie != NULL) + { + ar->arCookieList = cookie->arc_list_next; + } + + return cookie; +} + +#ifdef SEND_EVENT_TO_APP +/* + * This function is used to send event which come from taget to + * the application. The buf which send to application is include + * the event ID and event content. + */ +#define EVENT_ID_LEN 2 +void ar6000_send_event_to_app(AR_SOFTC_T *ar, A_UINT16 eventId, + A_UINT8 *datap, int len) +{ + +#if (WIRELESS_EXT >= 15) + +/* note: IWEVCUSTOM only exists in wireless extensions after version 15 */ + + char *buf; + A_UINT16 size; + union iwreq_data wrqu; + + size = len + EVENT_ID_LEN; + + if (size > IW_CUSTOM_MAX) { + AR_DEBUG_PRINTF("WMI event ID : 0x%4.4X, len = %d too big for IWEVCUSTOM (max=%d) \n", + eventId, size, IW_CUSTOM_MAX); + return; + } + + buf = A_MALLOC_NOWAIT(size); + A_MEMZERO(buf, size); + A_MEMCPY(buf, &eventId, EVENT_ID_LEN); + A_MEMCPY(buf+EVENT_ID_LEN, datap, len); + + //AR_DEBUG_PRINTF("event ID = %d,len = %d\n",*(A_UINT16*)buf, size); + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = size; + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + + A_FREE(buf); +#endif + + +} +#endif + + +void +ar6000_tx_retry_err_event(void *devt) +{ + AR_DEBUG2_PRINTF("Tx retries reach maximum!\n"); +} + +void +ar6000_snrThresholdEvent_rx(void *devt, WMI_SNR_THRESHOLD_VAL newThreshold, A_UINT8 snr) +{ + WMI_SNR_THRESHOLD_EVENT event; + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + event.range = newThreshold; + event.snr = snr; + + ar6000_send_event_to_app(ar, WMI_SNR_THRESHOLD_EVENTID, (A_UINT8 *)&event, + sizeof(WMI_SNR_THRESHOLD_EVENT)); +} + +void +ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL newThreshold, A_UINT8 lq) +{ + AR_DEBUG2_PRINTF("lq threshold range %d, lq %d\n", newThreshold, lq); +} + + + +A_UINT32 +a_copy_to_user(void *to, const void *from, A_UINT32 n) +{ + return(copy_to_user(to, from, n)); +} + +A_UINT32 +a_copy_from_user(void *to, const void *from, A_UINT32 n) +{ + return(copy_from_user(to, from, n)); +} + + +A_STATUS +ar6000_get_driver_cfg(struct net_device *dev, + A_UINT16 cfgParam, + void *result) +{ + + A_STATUS ret = 0; + + switch(cfgParam) + { + case AR6000_DRIVER_CFG_GET_WLANNODECACHING: + *((A_UINT32 *)result) = wlanNodeCaching; + break; + case AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS: + *((A_UINT32 *)result) = logWmiRawMsgs; + break; + default: + ret = EINVAL; + break; + } + + return ret; +} + +void +ar6000_keepalive_rx(void *devt, A_UINT8 configured) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arKeepaliveConfigured = configured; + wake_up(&arEvent); +} + +void +ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID, WMI_PMKID *pmkidList, + A_UINT8 *bssidList) +{ + A_UINT8 i, j; + + A_PRINTF("Number of Cached PMKIDs is %d\n", numPMKID); + + for (i = 0; i < numPMKID; i++) { + A_PRINTF("\nBSSID %d ", i); + for (j = 0; j < ATH_MAC_LEN; j++) { + A_PRINTF("%2.2x", bssidList[j]); + } + bssidList += (ATH_MAC_LEN + WMI_PMKID_LEN); + A_PRINTF("\nPMKID %d ", i); + for (j = 0; j < WMI_PMKID_LEN; j++) { + A_PRINTF("%2.2x", pmkidList->pmkid[j]); + } + pmkidList = (WMI_PMKID *)((A_UINT8 *)pmkidList + ATH_MAC_LEN + + WMI_PMKID_LEN); + } +} + +#ifdef USER_KEYS +static A_STATUS + +ar6000_reinstall_keys(AR_SOFTC_T *ar, A_UINT8 key_op_ctrl) +{ + A_STATUS status = A_OK; + struct ieee80211req_key *uik = &ar->user_saved_keys.ucast_ik; + struct ieee80211req_key *bik = &ar->user_saved_keys.bcast_ik; + CRYPTO_TYPE keyType = ar->user_saved_keys.keyType; + + if (IEEE80211_CIPHER_CCKM_KRK != uik->ik_type) { + if (NONE_CRYPT == keyType) { + goto _reinstall_keys_out; + } + + if (uik->ik_keylen) { + status = wmi_addKey_cmd(ar->arWmi, uik->ik_keyix, + ar->user_saved_keys.keyType, PAIRWISE_USAGE, + uik->ik_keylen, (A_UINT8 *)&uik->ik_keyrsc, + uik->ik_keydata, key_op_ctrl, SYNC_BEFORE_WMIFLAG); + } + + } else { + status = wmi_add_krk_cmd(ar->arWmi, uik->ik_keydata); + } + + if (IEEE80211_CIPHER_CCKM_KRK != bik->ik_type) { + if (NONE_CRYPT == keyType) { + goto _reinstall_keys_out; + } + + if (bik->ik_keylen) { + status = wmi_addKey_cmd(ar->arWmi, bik->ik_keyix, + ar->user_saved_keys.keyType, GROUP_USAGE, + bik->ik_keylen, (A_UINT8 *)&bik->ik_keyrsc, + bik->ik_keydata, key_op_ctrl, NO_SYNC_WMIFLAG); + } + } else { + status = wmi_add_krk_cmd(ar->arWmi, bik->ik_keydata); + } + +_reinstall_keys_out: + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT; + ar->user_key_ctrl = 0; + + return status; +} +#endif /* USER_KEYS */ + + +void +ar6000_dset_open_req( + void *context, + A_UINT32 id, + A_UINT32 targHandle, + A_UINT32 targReplyFn, + A_UINT32 targReplyArg) +{ +} + +void +ar6000_dset_close( + void *context, + A_UINT32 access_cookie) +{ + return; +} + +void +ar6000_dset_data_req( + void *context, + A_UINT32 accessCookie, + A_UINT32 offset, + A_UINT32 length, + A_UINT32 targBuf, + A_UINT32 targReplyFn, + A_UINT32 targReplyArg) +{ +} diff -urN linux-2.6.26/drivers/net/wireless/ar6000/ar6000_raw_if.c linux-2.6.26-lab126/drivers/net/wireless/ar6000/ar6000_raw_if.c --- linux-2.6.26/drivers/net/wireless/ar6000/ar6000_raw_if.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/ar6000_raw_if.c 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,443 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#include "ar6000_drv.h" + +#ifdef HTC_RAW_INTERFACE + +static void +ar6000_htc_raw_read_cb(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + raw_htc_buffer *busy; + HTC_RAW_STREAM_ID streamID; + + busy = (raw_htc_buffer *)pPacket->pPktContext; + A_ASSERT(busy != NULL); + + if (pPacket->Status == A_ECANCELED) { + /* + * HTC provides A_ECANCELED status when it doesn't want to be refilled + * (probably due to a shutdown) + */ + return; + } + + streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint); + A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED); + +#ifdef CF + if (down_trylock(&ar->raw_htc_read_sem[streamID])) { +#else + if (down_interruptible(&ar->raw_htc_read_sem[streamID])) { +#endif /* CF */ + AR_DEBUG2_PRINTF("Unable to down the semaphore\n"); + } + + A_ASSERT((pPacket->Status != A_OK) || + (pPacket->pBuffer == (busy->data + HTC_HEADER_LEN))); + + busy->length = pPacket->ActualLength + HTC_HEADER_LEN; + busy->currPtr = HTC_HEADER_LEN; + ar->read_buffer_available[streamID] = TRUE; + //AR_DEBUG_PRINTF("raw read cb: 0x%X 0x%X \n", busy->currPtr,busy->length); + up(&ar->raw_htc_read_sem[streamID]); + + /* Signal the waiting process */ + AR_DEBUG2_PRINTF("Waking up the StreamID(%d) read process\n", streamID); + wake_up_interruptible(&ar->raw_htc_read_queue[streamID]); +} + +static void +ar6000_htc_raw_write_cb(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + raw_htc_buffer *free; + HTC_RAW_STREAM_ID streamID; + + free = (raw_htc_buffer *)pPacket->pPktContext; + A_ASSERT(free != NULL); + + if (pPacket->Status == A_ECANCELED) { + /* + * HTC provides A_ECANCELED status when it doesn't want to be refilled + * (probably due to a shutdown) + */ + return; + } + + streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint); + A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED); + +#ifdef CF + if (down_trylock(&ar->raw_htc_write_sem[streamID])) { +#else + if (down_interruptible(&ar->raw_htc_write_sem[streamID])) { +#endif + AR_DEBUG2_PRINTF("Unable to down the semaphore\n"); + } + + A_ASSERT(pPacket->pBuffer == (free->data + HTC_HEADER_LEN)); + + free->length = 0; + ar->write_buffer_available[streamID] = TRUE; + up(&ar->raw_htc_write_sem[streamID]); + + /* Signal the waiting process */ + AR_DEBUG2_PRINTF("Waking up the StreamID(%d) write process\n", streamID); + wake_up_interruptible(&ar->raw_htc_write_queue[streamID]); +} + +/* connect to a service */ +static A_STATUS ar6000_connect_raw_service(AR_SOFTC_T *ar, + HTC_RAW_STREAM_ID StreamID) +{ + A_STATUS status; + HTC_SERVICE_CONNECT_RESP response; + A_UINT8 streamNo; + HTC_SERVICE_CONNECT_REQ connect; + + do { + + A_MEMZERO(&connect,sizeof(connect)); + /* pass the stream ID as meta data to the RAW streams service */ + streamNo = (A_UINT8)StreamID; + connect.pMetaData = &streamNo; + connect.MetaDataLength = sizeof(A_UINT8); + /* these fields are the same for all endpoints */ + connect.EpCallbacks.pContext = ar; + connect.EpCallbacks.EpTxComplete = ar6000_htc_raw_write_cb; + connect.EpCallbacks.EpRecv = ar6000_htc_raw_read_cb; + /* simple interface, we don't need these optional callbacks */ + connect.EpCallbacks.EpRecvRefill = NULL; + connect.EpCallbacks.EpSendFull = NULL; + connect.MaxSendQueueDepth = RAW_HTC_WRITE_BUFFERS_NUM; + + /* connect to the raw streams service, we may be able to get 1 or more + * connections, depending on WHAT is running on the target */ + connect.ServiceID = HTC_RAW_STREAMS_SVC; + + A_MEMZERO(&response,sizeof(response)); + + /* try to connect to the raw stream, it is okay if this fails with + * status HTC_SERVICE_NO_MORE_EP */ + status = HTCConnectService(ar->arHtcTarget, + &connect, + &response); + + if (A_FAILED(status)) { + if (response.ConnectRespCode == HTC_SERVICE_NO_MORE_EP) { + AR_DEBUG_PRINTF("HTC RAW , No more streams allowed \n"); + status = A_OK; + } + break; + } + + /* set endpoint mapping for the RAW HTC streams */ + arSetRawStream2EndpointIDMap(ar,StreamID,response.Endpoint); + + AR_DEBUG_PRINTF("HTC RAW : stream ID: %d, endpoint: %d\n", + StreamID, arRawStream2EndpointID(ar,StreamID)); + + } while (FALSE); + + return status; +} + +int ar6000_htc_raw_open(AR_SOFTC_T *ar) +{ + A_STATUS status; + int streamID, endPt, count2; + raw_htc_buffer *buffer; + HTC_SERVICE_ID servicepriority; + + A_ASSERT(ar->arHtcTarget != NULL); + + /* wait for target */ + status = HTCWaitTarget(ar->arHtcTarget); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF("HTCWaitTarget failed (%d)\n", status); + return -ENODEV; + } + + for (endPt = 0; endPt < ENDPOINT_MAX; endPt++) { + ar->arEp2RawMapping[endPt] = HTC_RAW_STREAM_NOT_MAPPED; + } + + for (streamID = HTC_RAW_STREAM_0; streamID < HTC_RAW_STREAM_NUM_MAX; streamID++) { + /* Initialize the data structures */ + init_MUTEX(&ar->raw_htc_read_sem[streamID]); + init_MUTEX(&ar->raw_htc_write_sem[streamID]); + init_waitqueue_head(&ar->raw_htc_read_queue[streamID]); + init_waitqueue_head(&ar->raw_htc_write_queue[streamID]); + + /* try to connect to the raw service */ + status = ar6000_connect_raw_service(ar,streamID); + + if (A_FAILED(status)) { + break; + } + + if (arRawStream2EndpointID(ar,streamID) == 0) { + break; + } + + for (count2 = 0; count2 < RAW_HTC_READ_BUFFERS_NUM; count2 ++) { + /* Initialize the receive buffers */ + buffer = &ar->raw_htc_write_buffer[streamID][count2]; + memset(buffer, 0, sizeof(raw_htc_buffer)); + buffer = &ar->raw_htc_read_buffer[streamID][count2]; + memset(buffer, 0, sizeof(raw_htc_buffer)); + + SET_HTC_PACKET_INFO_RX_REFILL(&buffer->HTCPacket, + buffer, + buffer->data, + AR6000_BUFFER_SIZE, + arRawStream2EndpointID(ar,streamID)); + + /* Queue buffers to HTC for receive */ + if ((status = HTCAddReceivePkt(ar->arHtcTarget, &buffer->HTCPacket)) != A_OK) + { + BMIInit(); + return -EIO; + } + } + + for (count2 = 0; count2 < RAW_HTC_WRITE_BUFFERS_NUM; count2 ++) { + /* Initialize the receive buffers */ + buffer = &ar->raw_htc_write_buffer[streamID][count2]; + memset(buffer, 0, sizeof(raw_htc_buffer)); + } + + ar->read_buffer_available[streamID] = FALSE; + ar->write_buffer_available[streamID] = TRUE; + } + + if (A_FAILED(status)) { + return -EIO; + } + + AR_DEBUG_PRINTF("HTC RAW, number of streams the target supports: %d \n", streamID); + + servicepriority = HTC_RAW_STREAMS_SVC; /* only 1 */ + + /* set callbacks and priority list */ + HTCSetCreditDistribution(ar->arHtcTarget, + ar, + NULL, /* use default */ + NULL, /* use default */ + &servicepriority, + 1); + + /* Start the HTC component */ + if ((status = HTCStart(ar->arHtcTarget)) != A_OK) { + BMIInit(); + return -EIO; + } + + (ar)->arRawIfInit = TRUE; + + return 0; +} + +int ar6000_htc_raw_close(AR_SOFTC_T *ar) +{ + A_PRINTF("ar6000_htc_raw_close called \n"); + HTCStop(ar->arHtcTarget); + + /* reset the device */ + ar6000_reset_device(ar->arHifDevice, ar->arTargetType, TRUE); + /* Initialize the BMI component */ + BMIInit(); + + return 0; +} + +raw_htc_buffer * +get_filled_buffer(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID) +{ + int count; + raw_htc_buffer *busy; + + /* Check for data */ + for (count = 0; count < RAW_HTC_READ_BUFFERS_NUM; count ++) { + busy = &ar->raw_htc_read_buffer[StreamID][count]; + if (busy->length) { + break; + } + } + if (busy->length) { + ar->read_buffer_available[StreamID] = TRUE; + } else { + ar->read_buffer_available[StreamID] = FALSE; + } + + return busy; +} + +ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t length) +{ + int readPtr; + raw_htc_buffer *busy; + + if (arRawStream2EndpointID(ar,StreamID) == 0) { + AR_DEBUG_PRINTF("StreamID(%d) not connected! \n", StreamID); + return -EFAULT; + } + + if (down_interruptible(&ar->raw_htc_read_sem[StreamID])) { + return -ERESTARTSYS; + } + + busy = get_filled_buffer(ar,StreamID); + while (!ar->read_buffer_available[StreamID]) { + up(&ar->raw_htc_read_sem[StreamID]); + + /* Wait for the data */ + AR_DEBUG2_PRINTF("Sleeping StreamID(%d) read process\n", StreamID); + if (wait_event_interruptible(ar->raw_htc_read_queue[StreamID], + ar->read_buffer_available[StreamID])) + { + return -EINTR; + } + if (down_interruptible(&ar->raw_htc_read_sem[StreamID])) { + return -ERESTARTSYS; + } + busy = get_filled_buffer(ar,StreamID); + } + + /* Read the data */ + readPtr = busy->currPtr; + if (length > busy->length - HTC_HEADER_LEN) { + length = busy->length - HTC_HEADER_LEN; + } + if (copy_to_user(buffer, &busy->data[readPtr], length)) { + up(&ar->raw_htc_read_sem[StreamID]); + return -EFAULT; + } + + busy->currPtr += length; + + //AR_DEBUG_PRINTF("raw read ioctl: currPTR : 0x%X 0x%X \n", busy->currPtr,busy->length); + + if (busy->currPtr == busy->length) + { + busy->currPtr = 0; + busy->length = 0; + HTC_PACKET_RESET_RX(&busy->HTCPacket); + //AR_DEBUG_PRINTF("raw read ioctl: ep for packet:%d \n", busy->HTCPacket.Endpoint); + HTCAddReceivePkt(ar->arHtcTarget, &busy->HTCPacket); + } + ar->read_buffer_available[StreamID] = FALSE; + up(&ar->raw_htc_read_sem[StreamID]); + + return length; +} + +static raw_htc_buffer * +get_free_buffer(AR_SOFTC_T *ar, HTC_ENDPOINT_ID StreamID) +{ + int count; + raw_htc_buffer *free; + + free = NULL; + for (count = 0; count < RAW_HTC_WRITE_BUFFERS_NUM; count ++) { + free = &ar->raw_htc_write_buffer[StreamID][count]; + if (free->length == 0) { + break; + } + } + if (!free->length) { + ar->write_buffer_available[StreamID] = TRUE; + } else { + ar->write_buffer_available[StreamID] = FALSE; + } + + return free; +} + +ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t length) +{ + int writePtr; + raw_htc_buffer *free; + + if (arRawStream2EndpointID(ar,StreamID) == 0) { + AR_DEBUG_PRINTF("StreamID(%d) not connected! \n", StreamID); + return -EFAULT; + } + + if (down_interruptible(&ar->raw_htc_write_sem[StreamID])) { + return -ERESTARTSYS; + } + + /* Search for a free buffer */ + free = get_free_buffer(ar,StreamID); + + /* Check if there is space to write else wait */ + while (!ar->write_buffer_available[StreamID]) { + up(&ar->raw_htc_write_sem[StreamID]); + + /* Wait for buffer to become free */ + AR_DEBUG2_PRINTF("Sleeping StreamID(%d) write process\n", StreamID); + if (wait_event_interruptible(ar->raw_htc_write_queue[StreamID], + ar->write_buffer_available[StreamID])) + { + return -EINTR; + } + if (down_interruptible(&ar->raw_htc_write_sem[StreamID])) { + return -ERESTARTSYS; + } + free = get_free_buffer(ar,StreamID); + } + + /* Send the data */ + writePtr = HTC_HEADER_LEN; + if (length > (AR6000_BUFFER_SIZE - HTC_HEADER_LEN)) { + length = AR6000_BUFFER_SIZE - HTC_HEADER_LEN; + } + + if (copy_from_user(&free->data[writePtr], buffer, length)) { + up(&ar->raw_htc_read_sem[StreamID]); + return -EFAULT; + } + + free->length = length; + + SET_HTC_PACKET_INFO_TX(&free->HTCPacket, + free, + &free->data[writePtr], + length, + arRawStream2EndpointID(ar,StreamID), + AR6K_DATA_PKT_TAG); + + HTCSendPkt(ar->arHtcTarget,&free->HTCPacket); + + ar->write_buffer_available[StreamID] = FALSE; + up(&ar->raw_htc_write_sem[StreamID]); + + return length; +} +#endif /* HTC_RAW_INTERFACE */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/ar6k.c linux-2.6.26-lab126/drivers/net/wireless/ar6000/ar6k.c --- linux-2.6.26/drivers/net/wireless/ar6000/ar6k.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/ar6k.c 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,1006 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// AR6K device layer that handles register level I/O +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "AR6002/hw/mbox_host_reg.h" +#include "a_osapi.h" +#include "a_debug.h" +#include "hif.h" +#include "htc_packet.h" +#include "ar6k.h" + +#define MAILBOX_FOR_BLOCK_SIZE 1 + +extern A_UINT32 resetok; + +A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev); + +#define LOCK_AR6K(p) A_MUTEX_LOCK(&(p)->Lock); +#define UNLOCK_AR6K(p) A_MUTEX_UNLOCK(&(p)->Lock); + +void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket) +{ + LOCK_AR6K(pDev); + HTC_PACKET_ENQUEUE(&pDev->RegisterIOList,pPacket); + UNLOCK_AR6K(pDev); +} + +HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev) +{ + HTC_PACKET *pPacket; + + LOCK_AR6K(pDev); + pPacket = HTC_PACKET_DEQUEUE(&pDev->RegisterIOList); + UNLOCK_AR6K(pDev); + + return pPacket; +} + +void DevCleanup(AR6K_DEVICE *pDev) +{ + if (A_IS_MUTEX_VALID(&pDev->Lock)) { + A_MUTEX_DELETE(&pDev->Lock); + } +} + +A_STATUS DevSetup(AR6K_DEVICE *pDev) +{ + A_UINT32 mailboxaddrs[AR6K_MAILBOXES]; + A_UINT32 blocksizes[AR6K_MAILBOXES]; + A_STATUS status = A_OK; + int i; + + AR_DEBUG_ASSERT(AR6K_IRQ_PROC_REGS_SIZE == 16); + AR_DEBUG_ASSERT(AR6K_IRQ_ENABLE_REGS_SIZE == 4); + + do { + /* give a handle to HIF for this target */ + HIFSetHandle(pDev->HIFDevice, (void *)pDev); + /* initialize our free list of IO packets */ + INIT_HTC_PACKET_QUEUE(&pDev->RegisterIOList); + A_MUTEX_INIT(&pDev->Lock); + + /* get the addresses for all 4 mailboxes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR, + mailboxaddrs, sizeof(mailboxaddrs)); + + if (status != A_OK) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* carve up register I/O packets (these are for ASYNC register I/O ) */ + for (i = 0; i < AR6K_MAX_REG_IO_BUFFERS; i++) { + HTC_PACKET *pIOPacket; + pIOPacket = &pDev->RegIOBuffers[i].HtcPacket; + SET_HTC_PACKET_INFO_RX_REFILL(pIOPacket, + pDev, + pDev->RegIOBuffers[i].Buffer, + AR6K_REG_IO_BUFFER_SIZE, + 0); /* don't care */ + AR6KFreeIOPacket(pDev,pIOPacket); + } + + /* get the address of the mailbox we are using */ + pDev->MailboxAddress = mailboxaddrs[HTC_MAILBOX]; + + /* get the block sizes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + blocksizes, sizeof(blocksizes)); + + if (status != A_OK) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* note: we actually get the block size of a mailbox other than 0, for SDIO the block + * size on mailbox 0 is artificially set to 1. So we use the block size that is set + * for the other 3 mailboxes */ + pDev->BlockSize = blocksizes[MAILBOX_FOR_BLOCK_SIZE]; + /* must be a power of 2 */ + AR_DEBUG_ASSERT((pDev->BlockSize & (pDev->BlockSize - 1)) == 0); + + /* assemble mask, used for padding to a block */ + pDev->BlockMask = pDev->BlockSize - 1; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("BlockSize: %d, MailboxAddress:0x%X \n", + pDev->BlockSize, pDev->MailboxAddress)); + + pDev->GetPendingEventsFunc = NULL; + /* see if the HIF layer implements the get pending events function */ + HIFConfigureDevice(pDev->HIFDevice, + HIF_DEVICE_GET_PENDING_EVENTS_FUNC, + &pDev->GetPendingEventsFunc, + sizeof(pDev->GetPendingEventsFunc)); + + /* assume we can process HIF interrupt events asynchronously */ + pDev->HifIRQProcessingMode = HIF_DEVICE_IRQ_ASYNC_SYNC; + + /* see if the HIF layer overrides this assumption */ + HIFConfigureDevice(pDev->HIFDevice, + HIF_DEVICE_GET_IRQ_PROC_MODE, + &pDev->HifIRQProcessingMode, + sizeof(pDev->HifIRQProcessingMode)); + + switch (pDev->HifIRQProcessingMode) { + case HIF_DEVICE_IRQ_SYNC_ONLY: + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is SYNC ONLY\n")); + break; + case HIF_DEVICE_IRQ_ASYNC_SYNC: + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is ASYNC and SYNC\n")); + break; + default: + AR_DEBUG_ASSERT(FALSE); + } + + pDev->HifMaskUmaskRecvEvent = NULL; + + /* see if the HIF layer implements the mask/unmask recv events function */ + HIFConfigureDevice(pDev->HIFDevice, + HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC, + &pDev->HifMaskUmaskRecvEvent, + sizeof(pDev->HifMaskUmaskRecvEvent)); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF special overrides : 0x%X , 0x%X\n", + (A_UINT32)pDev->GetPendingEventsFunc, (A_UINT32)pDev->HifMaskUmaskRecvEvent)); + + status = DevDisableInterrupts(pDev); + + } while (FALSE); + + if (A_FAILED(status)) { + /* make sure handle is cleared */ + HIFSetHandle(pDev->HIFDevice, NULL); + } + + return status; + +} + +A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev) +{ + A_STATUS status; + AR6K_IRQ_ENABLE_REGISTERS regs; + + LOCK_AR6K(pDev); + + /* Enable all the interrupts except for the internal AR6000 CPU interrupt */ + pDev->IrqEnableRegisters.int_status_enable = INT_STATUS_ENABLE_ERROR_SET(0x01) | + INT_STATUS_ENABLE_CPU_SET(0x01) | + INT_STATUS_ENABLE_COUNTER_SET(0x01); + + if (NULL == pDev->GetPendingEventsFunc) { + pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } else { + /* The HIF layer provided us with a pending events function which means that + * the detection of pending mbox messages is handled in the HIF layer. + * This is the case for the SPI2 interface. + * In the normal case we enable MBOX interrupts, for the case + * with HIFs that offer this mechanism, we keep these interrupts + * masked */ + pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } + + + /* Set up the CPU Interrupt Status Register */ + pDev->IrqEnableRegisters.cpu_int_status_enable = CPU_INT_STATUS_ENABLE_BIT_SET(0x00); + + /* Set up the Error Interrupt Status Register */ + pDev->IrqEnableRegisters.error_status_enable = + ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(0x01) | + ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(0x01); + + /* Set up the Counter Interrupt Status Register (only for debug interrupt to catch fatal errors) */ + pDev->IrqEnableRegisters.counter_int_status_enable = + COUNTER_INT_STATUS_ENABLE_BIT_SET(AR6K_TARGET_DEBUG_INTR_MASK); + + /* copy into our temp area */ + A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE); + + UNLOCK_AR6K(pDev); + + /* always synchronous */ + status = HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + ®s.int_status_enable, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + /* Can't write it for some reason */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Failed to update interrupt control registers err: %d\n", status)); + + } + + return status; +} + +A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev) +{ + AR6K_IRQ_ENABLE_REGISTERS regs; + + LOCK_AR6K(pDev); + /* Disable all interrupts */ + pDev->IrqEnableRegisters.int_status_enable = 0; + pDev->IrqEnableRegisters.cpu_int_status_enable = 0; + pDev->IrqEnableRegisters.error_status_enable = 0; + pDev->IrqEnableRegisters.counter_int_status_enable = 0; + /* copy into our temp area */ + A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE); + + UNLOCK_AR6K(pDev); + + /* always synchronous */ + return HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + ®s.int_status_enable, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_SYNC_BYTE_INC, + NULL); +} + +/* enable device interrupts */ +A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev) +{ + /* for good measure, make sure interrupt are disabled before unmasking at the HIF + * layer. + * The rationale here is that between device insertion (where we clear the interrupts the first time) + * and when HTC is finally ready to handle interrupts, other software can perform target "soft" resets. + * The AR6K interrupt enables reset back to an "enabled" state when this happens. + * */ + DevDisableInterrupts(pDev); + + /* Unmask the host controller interrupts */ + HIFUnMaskInterrupt(pDev->HIFDevice); + + return DevEnableInterrupts(pDev); +} + +/* disable all device interrupts */ +A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev) +{ + /* mask the interrupt at the HIF layer, we don't want a stray interrupt taken while + * we zero out our shadow registers in DevDisableInterrupts()*/ + HIFMaskInterrupt(pDev->HIFDevice); + + return DevDisableInterrupts(pDev); +} + +/* callback when our fetch to enable/disable completes */ +static void DevDoEnableDisableRecvAsyncHandler(void *Context, HTC_PACKET *pPacket) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDoEnableDisableRecvAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); + + if (A_FAILED(pPacket->Status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" Failed to disable receiver, status:%d \n", pPacket->Status)); + } + /* free this IO packet */ + AR6KFreeIOPacket(pDev,pPacket); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDoEnableDisableRecvAsyncHandler \n")); +} + +/* disable packet reception (used in case the host runs out of buffers) + * this is the "override" method when the HIF reports another methods to + * disable recv events */ +static A_STATUS DevDoEnableDisableRecvOverride(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode) +{ + A_STATUS status = A_OK; + HTC_PACKET *pIOPacket = NULL; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("DevDoEnableDisableRecvOverride: Enable:%d Mode:%d\n", + EnableRecv,AsyncMode)); + + do { + + if (AsyncMode) { + + pIOPacket = AR6KAllocIOPacket(pDev); + + if (NULL == pIOPacket) { + status = A_NO_MEMORY; + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* stick in our completion routine when the I/O operation completes */ + pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler; + pIOPacket->pContext = pDev; + + /* call the HIF layer override and do this asynchronously */ + status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice, + EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV, + pIOPacket); + break; + } + + /* if we get here we are doing it synchronously */ + status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice, + EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV, + NULL); + + } while (FALSE); + + if (A_FAILED(status) && (pIOPacket != NULL)) { + AR6KFreeIOPacket(pDev,pIOPacket); + } + + return status; +} + +/* disable packet reception (used in case the host runs out of buffers) + * this is the "normal" method using the interrupt enable registers through + * the host I/F */ +static A_STATUS DevDoEnableDisableRecvNormal(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode) +{ + A_STATUS status = A_OK; + HTC_PACKET *pIOPacket = NULL; + AR6K_IRQ_ENABLE_REGISTERS regs; + + /* take the lock to protect interrupt enable shadows */ + LOCK_AR6K(pDev); + + if (EnableRecv) { + pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } else { + pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } + + /* copy into our temp area */ + A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE); + UNLOCK_AR6K(pDev); + + do { + + if (AsyncMode) { + + pIOPacket = AR6KAllocIOPacket(pDev); + + if (NULL == pIOPacket) { + status = A_NO_MEMORY; + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* copy values to write to our async I/O buffer */ + A_MEMCPY(pIOPacket->pBuffer,®s,AR6K_IRQ_ENABLE_REGS_SIZE); + + /* stick in our completion routine when the I/O operation completes */ + pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler; + pIOPacket->pContext = pDev; + + /* write it out asynchronously */ + HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + pIOPacket->pBuffer, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_ASYNC_BYTE_INC, + pIOPacket); + break; + } + + /* if we get here we are doing it synchronously */ + + status = HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + ®s.int_status_enable, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_SYNC_BYTE_INC, + NULL); + + } while (FALSE); + + if (A_FAILED(status) && (pIOPacket != NULL)) { + AR6KFreeIOPacket(pDev,pIOPacket); + } + + return status; +} + + +A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode) +{ + if (NULL == pDev->HifMaskUmaskRecvEvent) { + return DevDoEnableDisableRecvNormal(pDev,FALSE,AsyncMode); + } else { + return DevDoEnableDisableRecvOverride(pDev,FALSE,AsyncMode); + } +} + +A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode) +{ + if (NULL == pDev->HifMaskUmaskRecvEvent) { + return DevDoEnableDisableRecvNormal(pDev,TRUE,AsyncMode); + } else { + return DevDoEnableDisableRecvOverride(pDev,TRUE,AsyncMode); + } +} + +void DevDumpRegisters(AR6K_IRQ_PROC_REGISTERS *pIrqProcRegs, + AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs) +{ + + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("\n<------- Register Table -------->\n")); + + if (pIrqProcRegs != NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Int Status: 0x%x\n",pIrqProcRegs->host_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("CPU Int Status: 0x%x\n",pIrqProcRegs->cpu_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Error Int Status: 0x%x\n",pIrqProcRegs->error_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Counter Int Status: 0x%x\n",pIrqProcRegs->counter_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Mbox Frame: 0x%x\n",pIrqProcRegs->mbox_frame)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Rx Lookahead Valid: 0x%x\n",pIrqProcRegs->rx_lookahead_valid)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Rx Lookahead 0: 0x%x\n",pIrqProcRegs->rx_lookahead[0])); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Rx Lookahead 1: 0x%x\n",pIrqProcRegs->rx_lookahead[1])); + } + + if (pIrqEnableRegs != NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Int Status Enable: 0x%x\n",pIrqEnableRegs->int_status_enable)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Counter Int Status Enable: 0x%x\n",pIrqEnableRegs->counter_int_status_enable)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("<------------------------------->\n")); + } +} + + +#ifdef MBOXHW_UNIT_TEST + + +/* This is a mailbox hardware unit test that must be called in a schedulable context + * This test is very simple, it will send a list of buffers with a counting pattern + * and the target will invert the data and send the message back + * + * the unit test has the following constraints: + * + * The target has at least 8 buffers of 256 bytes each. The host will send + * the following pattern of buffers in rapid succession : + * + * 1 buffer - 128 bytes + * 1 buffer - 256 bytes + * 1 buffer - 512 bytes + * 1 buffer - 1024 bytes + * + * The host will send the buffers to one mailbox and wait for buffers to be reflected + * back from the same mailbox. The target sends the buffers FIFO order. + * Once the final buffer has been received for a mailbox, the next mailbox is tested. + * + * + * Note: To simplifythe test , we assume that the chosen buffer sizes + * will fall on a nice block pad + * + * It is expected that higher-order tests will be written to stress the mailboxes using + * a message-based protocol (with some performance timming) that can create more + * randomness in the packets sent over mailboxes. + * + * */ + +#define A_ROUND_UP_PWR2(x, align) (((int) (x) + ((align)-1)) & ~((align)-1)) + +#define BUFFER_BLOCK_PAD 128 + +#if 0 +#define BUFFER1 128 +#define BUFFER2 256 +#define BUFFER3 512 +#define BUFFER4 1024 +#endif + +#if 1 +#define BUFFER1 80 +#define BUFFER2 200 +#define BUFFER3 444 +#define BUFFER4 800 +#endif + +#define TOTAL_BYTES (A_ROUND_UP_PWR2(BUFFER1,BUFFER_BLOCK_PAD) + \ + A_ROUND_UP_PWR2(BUFFER2,BUFFER_BLOCK_PAD) + \ + A_ROUND_UP_PWR2(BUFFER3,BUFFER_BLOCK_PAD) + \ + A_ROUND_UP_PWR2(BUFFER4,BUFFER_BLOCK_PAD) ) + +#define TEST_BYTES (BUFFER1 + BUFFER2 + BUFFER3 + BUFFER4) + +#define TEST_CREDITS_RECV_TIMEOUT 100 + +static A_UINT8 g_Buffer[TOTAL_BYTES]; +static A_UINT32 g_MailboxAddrs[AR6K_MAILBOXES]; +static A_UINT32 g_BlockSizes[AR6K_MAILBOXES]; + +#define BUFFER_PROC_LIST_DEPTH 4 + +typedef struct _BUFFER_PROC_LIST{ + A_UINT8 *pBuffer; + A_UINT32 length; +}BUFFER_PROC_LIST; + + +#define PUSH_BUFF_PROC_ENTRY(pList,len,pCurrpos) \ +{ \ + (pList)->pBuffer = (pCurrpos); \ + (pList)->length = (len); \ + (pCurrpos) += (len); \ + (pList)++; \ +} + +/* a simple and crude way to send different "message" sizes */ +static void AssembleBufferList(BUFFER_PROC_LIST *pList) +{ + A_UINT8 *pBuffer = g_Buffer; + +#if BUFFER_PROC_LIST_DEPTH < 4 +#error "Buffer processing list depth is not deep enough!!" +#endif + + PUSH_BUFF_PROC_ENTRY(pList,BUFFER1,pBuffer); + PUSH_BUFF_PROC_ENTRY(pList,BUFFER2,pBuffer); + PUSH_BUFF_PROC_ENTRY(pList,BUFFER3,pBuffer); + PUSH_BUFF_PROC_ENTRY(pList,BUFFER4,pBuffer); + +} + +#define FILL_ZERO TRUE +#define FILL_COUNTING FALSE +static void InitBuffers(A_BOOL Zero) +{ + A_UINT16 *pBuffer16 = (A_UINT16 *)g_Buffer; + int i; + + /* fill buffer with 16 bit counting pattern or zeros */ + for (i = 0; i < (TOTAL_BYTES / 2) ; i++) { + if (!Zero) { + pBuffer16[i] = (A_UINT16)i; + } else { + pBuffer16[i] = 0; + } + } +} + + +static A_BOOL CheckOneBuffer(A_UINT16 *pBuffer16, int Length) +{ + int i; + A_UINT16 startCount; + A_BOOL success = TRUE; + + /* get the starting count */ + startCount = pBuffer16[0]; + /* invert it, this is the expected value */ + startCount = ~startCount; + /* scan the buffer and verify */ + for (i = 0; i < (Length / 2) ; i++,startCount++) { + /* target will invert all the data */ + if ((A_UINT16)pBuffer16[i] != (A_UINT16)~startCount) { + success = FALSE; + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Invalid Data Got:0x%X, Expecting:0x%X (offset:%d, total:%d) \n", + pBuffer16[i], ((A_UINT16)~startCount), i, Length)); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("0x%X 0x%X 0x%X 0x%X \n", + pBuffer16[i], pBuffer16[i + 1], pBuffer16[i + 2],pBuffer16[i+3])); + break; + } + } + + return success; +} + +static A_BOOL CheckBuffers(void) +{ + int i; + A_BOOL success = TRUE; + BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH]; + + /* assemble the list */ + AssembleBufferList(checkList); + + /* scan the buffers and verify */ + for (i = 0; i < BUFFER_PROC_LIST_DEPTH ; i++) { + success = CheckOneBuffer((A_UINT16 *)checkList[i].pBuffer, checkList[i].length); + if (!success) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer : 0x%X, Length:%d failed verify \n", + (A_UINT32)checkList[i].pBuffer, checkList[i].length)); + break; + } + } + + return success; +} + + /* find the end marker for the last buffer we will be sending */ +static A_UINT16 GetEndMarker(void) +{ + A_UINT8 *pBuffer; + BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH]; + + /* fill up buffers with the normal counting pattern */ + InitBuffers(FILL_COUNTING); + + /* assemble the list we will be sending down */ + AssembleBufferList(checkList); + /* point to the last 2 bytes of the last buffer */ + pBuffer = &(checkList[BUFFER_PROC_LIST_DEPTH - 1].pBuffer[(checkList[BUFFER_PROC_LIST_DEPTH - 1].length) - 2]); + + /* the last count in the last buffer is the marker */ + return (A_UINT16)pBuffer[0] | ((A_UINT16)pBuffer[1] << 8); +} + +#define ATH_PRINT_OUT_ZONE ATH_DEBUG_ERR + +/* send the ordered buffers to the target */ +static A_STATUS SendBuffers(AR6K_DEVICE *pDev, int mbox) +{ + A_STATUS status = A_OK; + A_UINT32 request = HIF_WR_SYNC_BLOCK_INC; + BUFFER_PROC_LIST sendList[BUFFER_PROC_LIST_DEPTH]; + int i; + int totalBytes = 0; + int paddedLength; + int totalwPadding = 0; + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sending buffers on mailbox : %d \n",mbox)); + + /* fill buffer with counting pattern */ + InitBuffers(FILL_COUNTING); + + /* assemble the order in which we send */ + AssembleBufferList(sendList); + + for (i = 0; i < BUFFER_PROC_LIST_DEPTH; i++) { + + /* we are doing block transfers, so we need to pad everything to a block size */ + paddedLength = (sendList[i].length + (g_BlockSizes[mbox] - 1)) & + (~(g_BlockSizes[mbox] - 1)); + + /* send each buffer synchronously */ + status = HIFReadWrite(pDev->HIFDevice, + g_MailboxAddrs[mbox], + sendList[i].pBuffer, + paddedLength, + request, + NULL); + if (status != A_OK) { + break; + } + totalBytes += sendList[i].length; + totalwPadding += paddedLength; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sent %d bytes (%d padded bytes) to mailbox : %d \n",totalBytes,totalwPadding,mbox)); + + return status; +} + +/* poll the mailbox credit counter until we get a credit or timeout */ +static A_STATUS GetCredits(AR6K_DEVICE *pDev, int mbox, int *pCredits) +{ + A_STATUS status = A_OK; + int timeout = TEST_CREDITS_RECV_TIMEOUT; + A_UINT8 credits = 0; + A_UINT32 address; + + while (TRUE) { + + /* Read the counter register to get credits, this auto-decrements */ + address = COUNT_DEC_ADDRESS + (AR6K_MAILBOXES + mbox) * 4; + status = HIFReadWrite(pDev->HIFDevice, address, &credits, sizeof(credits), + HIF_RD_SYNC_BYTE_FIX, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Unable to decrement the command credit count register (mbox=%d)\n",mbox)); + status = A_ERROR; + break; + } + + if (credits) { + break; + } + + timeout--; + + if (timeout <= 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" Timeout reading credit registers (mbox=%d, address:0x%X) \n",mbox,address)); + status = A_ERROR; + break; + } + + /* delay a little, target may not be ready */ + A_MDELAY(1000); + + } + + if (status == A_OK) { + *pCredits = credits; + } + + return status; +} + + +/* wait for the buffers to come back */ +static A_STATUS RecvBuffers(AR6K_DEVICE *pDev, int mbox) +{ + A_STATUS status = A_OK; + A_UINT32 request = HIF_RD_SYNC_BLOCK_INC; + BUFFER_PROC_LIST recvList[BUFFER_PROC_LIST_DEPTH]; + int curBuffer; + int credits; + int i; + int totalBytes = 0; + int paddedLength; + int totalwPadding = 0; + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for buffers on mailbox : %d \n",mbox)); + + /* zero the buffers */ + InitBuffers(FILL_ZERO); + + /* assemble the order in which we should receive */ + AssembleBufferList(recvList); + + curBuffer = 0; + + while (curBuffer < BUFFER_PROC_LIST_DEPTH) { + + /* get number of buffers that have been completed, this blocks + * until we get at least 1 credit or it times out */ + status = GetCredits(pDev, mbox, &credits); + + if (status != A_OK) { + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got %d messages on mailbox : %d \n",credits, mbox)); + + /* get all the buffers that are sitting on the queue */ + for (i = 0; i < credits; i++) { + AR_DEBUG_ASSERT(curBuffer < BUFFER_PROC_LIST_DEPTH); + /* recv the current buffer synchronously, the buffers should come back in + * order... with padding applied by the target */ + paddedLength = (recvList[curBuffer].length + (g_BlockSizes[mbox] - 1)) & + (~(g_BlockSizes[mbox] - 1)); + + status = HIFReadWrite(pDev->HIFDevice, + g_MailboxAddrs[mbox], + recvList[curBuffer].pBuffer, + paddedLength, + request, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to read %d bytes on mailbox:%d : address:0x%X \n", + recvList[curBuffer].length, mbox, g_MailboxAddrs[mbox])); + break; + } + + totalwPadding += paddedLength; + totalBytes += recvList[curBuffer].length; + curBuffer++; + } + + if (status != A_OK) { + break; + } + /* go back and get some more */ + credits = 0; + } + + if (totalBytes != TEST_BYTES) { + AR_DEBUG_ASSERT(FALSE); + } else { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got all buffers on mbox:%d total recv :%d (w/Padding : %d) \n", + mbox, totalBytes, totalwPadding)); + } + + return status; + + +} + +static A_STATUS DoOneMboxHWTest(AR6K_DEVICE *pDev, int mbox) +{ + A_STATUS status; + + do { + /* send out buffers */ + status = SendBuffers(pDev,mbox); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Sending buffers Failed : %d mbox:%d\n",status,mbox)); + break; + } + + /* go get them, this will block */ + status = RecvBuffers(pDev, mbox); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Recv buffers Failed : %d mbox:%d\n",status,mbox)); + break; + } + + /* check the returned data patterns */ + if (!CheckBuffers()) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer Verify Failed : mbox:%d\n",mbox)); + status = A_ERROR; + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" Send/Recv success! mailbox : %d \n",mbox)); + + } while (FALSE); + + return status; +} + +/* here is where the test starts */ +A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev) +{ + int i; + A_STATUS status; + int credits = 0; + A_UINT8 params[4]; + int numBufs; + int bufferSize; + A_UINT16 temp; + + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest START - \n")); + + do { + /* get the addresses for all 4 mailboxes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR, + g_MailboxAddrs, sizeof(g_MailboxAddrs)); + + if (status != A_OK) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* get the block sizes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + g_BlockSizes, sizeof(g_BlockSizes)); + + if (status != A_OK) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* note, the HIF layer usually reports mbox 0 to have a block size of + * 1, but our test wants to run in block-mode for all mailboxes, so we treat all mailboxes + * the same. */ + g_BlockSizes[0] = g_BlockSizes[1]; + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Block Size to use: %d \n",g_BlockSizes[0])); + + if (g_BlockSizes[1] > BUFFER_BLOCK_PAD) { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("%d Block size is too large for buffer pad %d\n", + g_BlockSizes[1], BUFFER_BLOCK_PAD)); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for target.... \n")); + + /* the target lets us know it is ready by giving us 1 credit on + * mailbox 0 */ + status = GetCredits(pDev, 0, &credits); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait for target ready \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Target is ready ...\n")); + + /* read the first 4 scratch registers */ + status = HIFReadWrite(pDev->HIFDevice, + SCRATCH_ADDRESS, + params, + 4, + HIF_RD_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait get parameters \n")); + break; + } + + numBufs = params[0]; + bufferSize = (int)(((A_UINT16)params[2] << 8) | (A_UINT16)params[1]); + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, + ("Target parameters: bufs per mailbox:%d, buffer size:%d bytes (total space: %d, minimum required space (w/padding): %d) \n", + numBufs, bufferSize, (numBufs * bufferSize), TOTAL_BYTES)); + + if ((numBufs * bufferSize) < TOTAL_BYTES) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Not Enough buffer space to run test! need:%d, got:%d \n", + TOTAL_BYTES, (numBufs*bufferSize))); + status = A_ERROR; + break; + } + + temp = GetEndMarker(); + + status = HIFReadWrite(pDev->HIFDevice, + SCRATCH_ADDRESS + 4, + (A_UINT8 *)&temp, + 2, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write end marker \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("End Marker: 0x%X \n",temp)); + + temp = (A_UINT16)g_BlockSizes[1]; + /* convert to a mask */ + temp = temp - 1; + status = HIFReadWrite(pDev->HIFDevice, + SCRATCH_ADDRESS + 6, + (A_UINT8 *)&temp, + 2, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write block mask \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Set Block Mask: 0x%X \n",temp)); + + /* execute the test on each mailbox */ + for (i = 0; i < AR6K_MAILBOXES; i++) { + status = DoOneMboxHWTest(pDev, i); + if (status != A_OK) { + break; + } + } + + } while (FALSE); + + if (status == A_OK) { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - SUCCESS! - \n")); + } else { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - FAILED! - \n")); + } + /* don't let HTC_Start continue, the target is actually not running any HTC code */ + return A_ERROR; +} +#endif + + + diff -urN linux-2.6.26/drivers/net/wireless/ar6000/ar6k_events.c linux-2.6.26-lab126/drivers/net/wireless/ar6000/ar6k_events.c --- linux-2.6.26/drivers/net/wireless/ar6000/ar6k_events.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/ar6k_events.c 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,650 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// AR6K Driver layer event handling (i.e. interrupts, message polling) +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "AR6002/hw/mbox_host_reg.h" +#include "a_osapi.h" +#include "a_debug.h" +#include "hif.h" +#include "htc_packet.h" +#include "ar6k.h" + +extern void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket); +extern HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev); + +static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev); + +#define DELAY_PER_INTERVAL_MS 10 /* 10 MS delay per polling interval */ + +/* completion routine for ALL HIF layer async I/O */ +A_STATUS DevRWCompletionHandler(void *context, A_STATUS status) +{ + HTC_PACKET *pPacket = (HTC_PACKET *)context; + + COMPLETE_HTC_PACKET(pPacket,status); + + return A_OK; +} + +/* mailbox recv message polling */ +A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev, + A_UINT32 *pLookAhead, + int TimeoutMS) +{ + A_STATUS status = A_OK; + int timeout = TimeoutMS/DELAY_PER_INTERVAL_MS; + + AR_DEBUG_ASSERT(timeout > 0); + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevPollMboxMsgRecv \n")); + + while (TRUE) { + + if (pDev->GetPendingEventsFunc != NULL) + { + + HIF_PENDING_EVENTS_INFO events; + + /* the HIF layer uses a special mechanism to get events, do this + * synchronously */ + status = pDev->GetPendingEventsFunc(pDev->HIFDevice, + &events, + NULL); + if (A_FAILED(status)) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get pending events \n")); + break; + } + + if (events.Events & HIF_RECV_MSG_AVAIL) + { + /* there is a message available, the lookahead should be valid now */ + *pLookAhead = events.LookAhead; + + break; + } + } + else + { + + /* this is the standard HIF way.... */ + /* load the register table */ + status = HIFReadWrite(pDev->HIFDevice, + HOST_INT_STATUS_ADDRESS, + (A_UINT8 *)&pDev->IrqProcRegisters, + AR6K_IRQ_PROC_REGS_SIZE, + HIF_RD_SYNC_BYTE_INC, + NULL); + + if (A_FAILED(status)) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to read register table \n")); + break; + } + + /* check for MBOX data and valid lookahead */ + if (pDev->IrqProcRegisters.host_int_status & (1 << HTC_MAILBOX)) + { + if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) + { + /* mailbox has a message and the look ahead is valid */ + *pLookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX]; + break; + } + } + + } + + timeout--; + + if (timeout <= 0) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Timeout waiting for recv message \n")); + status = A_ERROR; + + /* check if the target asserted */ + if ( pDev->IrqProcRegisters.counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) { + /* target signaled an assert, process this pending interrupt + * this will call the target failure handler */ + DevServiceDebugInterrupt(pDev); + } + + break; + } + + /* delay a little */ + A_MDELAY(DELAY_PER_INTERVAL_MS); + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Retry Mbox Poll : %d \n",timeout)); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevPollMboxMsgRecv \n")); + + return status; +} + +static A_STATUS DevServiceCPUInterrupt(AR6K_DEVICE *pDev) +{ + A_STATUS status; + A_UINT8 cpu_int_status; + A_UINT8 regBuffer[4]; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("CPU Interrupt\n")); + cpu_int_status = pDev->IrqProcRegisters.cpu_int_status & + pDev->IrqEnableRegisters.cpu_int_status_enable; + AR_DEBUG_ASSERT(cpu_int_status); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + ("Valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n", + cpu_int_status)); + + /* Clear the interrupt */ + pDev->IrqProcRegisters.cpu_int_status &= ~cpu_int_status; /* W1C */ + + /* set up the register transfer buffer to hit the register 4 times , this is done + * to make the access 4-byte aligned to mitigate issues with host bus interconnects that + * restrict bus transfer lengths to be a multiple of 4-bytes */ + + /* set W1C value to clear the interrupt, this hits the register first */ + regBuffer[0] = cpu_int_status; + /* the remaining 4 values are set to zero which have no-effect */ + regBuffer[1] = 0; + regBuffer[2] = 0; + regBuffer[3] = 0; + + status = HIFReadWrite(pDev->HIFDevice, + CPU_INT_STATUS_ADDRESS, + regBuffer, + 4, + HIF_WR_SYNC_BYTE_FIX, + NULL); + + AR_DEBUG_ASSERT(status == A_OK); + return status; +} + + +static A_STATUS DevServiceErrorInterrupt(AR6K_DEVICE *pDev) +{ + A_STATUS status; + A_UINT8 error_int_status; + A_UINT8 regBuffer[4]; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error Interrupt\n")); + error_int_status = pDev->IrqProcRegisters.error_int_status & 0x0F; + AR_DEBUG_ASSERT(error_int_status); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + ("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n", + error_int_status)); + + if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) { + /* Wakeup */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error : Wakeup\n")); + } + + if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) { + /* Rx Underflow */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Rx Underflow\n")); + } + + if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) { + /* Tx Overflow */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Tx Overflow\n")); + } + + /* Clear the interrupt */ + pDev->IrqProcRegisters.error_int_status &= ~error_int_status; /* W1C */ + + /* set up the register transfer buffer to hit the register 4 times , this is done + * to make the access 4-byte aligned to mitigate issues with host bus interconnects that + * restrict bus transfer lengths to be a multiple of 4-bytes */ + + /* set W1C value to clear the interrupt, this hits the register first */ + regBuffer[0] = error_int_status; + /* the remaining 4 values are set to zero which have no-effect */ + regBuffer[1] = 0; + regBuffer[2] = 0; + regBuffer[3] = 0; + + status = HIFReadWrite(pDev->HIFDevice, + ERROR_INT_STATUS_ADDRESS, + regBuffer, + 4, + HIF_WR_SYNC_BYTE_FIX, + NULL); + + AR_DEBUG_ASSERT(status == A_OK); + return status; +} + +static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev) +{ + A_UINT32 dummy; + A_STATUS status; + + /* Send a target failure event to the application */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Target debug interrupt\n")); + + if (pDev->TargetFailureCallback != NULL) { + pDev->TargetFailureCallback(pDev->HTCContext); + } + + /* clear the interrupt , the debug error interrupt is + * counter 0 */ + /* read counter to clear interrupt */ + status = HIFReadWrite(pDev->HIFDevice, + COUNT_DEC_ADDRESS, + (A_UINT8 *)&dummy, + 4, + HIF_RD_SYNC_BYTE_INC, + NULL); + + AR_DEBUG_ASSERT(status == A_OK); + return status; +} + +static A_STATUS DevServiceCounterInterrupt(AR6K_DEVICE *pDev) +{ + A_UINT8 counter_int_status; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Counter Interrupt\n")); + + counter_int_status = pDev->IrqProcRegisters.counter_int_status & + pDev->IrqEnableRegisters.counter_int_status_enable; + + AR_DEBUG_ASSERT(counter_int_status); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + ("Valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n", + counter_int_status)); + + /* Check if the debug interrupt is pending */ + if (counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) { + return DevServiceDebugInterrupt(pDev); + } + + return A_OK; +} + +/* callback when our fetch to get interrupt status registers completes */ +static void DevGetEventAsyncHandler(void *Context, HTC_PACKET *pPacket) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context; + A_UINT32 lookAhead = 0; + A_BOOL otherInts = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGetEventAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); + + do { + + if (A_FAILED(pPacket->Status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" GetEvents I/O request failed, status:%d \n", pPacket->Status)); + /* bail out, don't unmask HIF interrupt */ + break; + } + + if (pDev->GetPendingEventsFunc != NULL) { + /* the HIF layer collected the information for us */ + HIF_PENDING_EVENTS_INFO *pEvents = (HIF_PENDING_EVENTS_INFO *)pPacket->pBuffer; + if (pEvents->Events & HIF_RECV_MSG_AVAIL) { + lookAhead = pEvents->LookAhead; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler1, lookAhead is zero! \n")); + } + } + if (pEvents->Events & HIF_OTHER_EVENTS) { + otherInts = TRUE; + } + } else { + /* standard interrupt table handling.... */ + AR6K_IRQ_PROC_REGISTERS *pReg = (AR6K_IRQ_PROC_REGISTERS *)pPacket->pBuffer; + A_UINT8 host_int_status; + + host_int_status = pReg->host_int_status & pDev->IrqEnableRegisters.int_status_enable; + + if (host_int_status & (1 << HTC_MAILBOX)) { + host_int_status &= ~(1 << HTC_MAILBOX); + if (pReg->rx_lookahead_valid & (1 << HTC_MAILBOX)) { + /* mailbox has a message and the look ahead is valid */ + lookAhead = pReg->rx_lookahead[HTC_MAILBOX]; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler2, lookAhead is zero! \n")); + } + } + } + + if (host_int_status) { + /* there are other interrupts to handle */ + otherInts = TRUE; + } + } + + if (otherInts || (lookAhead == 0)) { + /* if there are other interrupts to process, we cannot do this in the async handler so + * ack the interrupt which will cause our sync handler to run again + * if however there are no more messages, we can now ack the interrupt */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + (" Acking interrupt from DevGetEventAsyncHandler (otherints:%d, lookahead:0x%X)\n", + otherInts, lookAhead)); + HIFAckInterrupt(pDev->HIFDevice); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + (" DevGetEventAsyncHandler : detected another message, lookahead :0x%X \n", + lookAhead)); + /* lookahead is non-zero and there are no other interrupts to service, + * go get the next message */ + pDev->MessagePendingCallback(pDev->HTCContext, lookAhead, NULL); + } + + } while (FALSE); + + /* free this IO packet */ + AR6KFreeIOPacket(pDev,pPacket); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGetEventAsyncHandler \n")); +} + +/* called by the HTC layer when it wants us to check if the device has any more pending + * recv messages, this starts off a series of async requests to read interrupt registers */ +A_STATUS DevCheckPendingRecvMsgsAsync(void *context) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)context; + A_STATUS status = A_OK; + HTC_PACKET *pIOPacket; + + /* this is called in an ASYNC only context, we may NOT block, sleep or call any apis that can + * cause us to switch contexts */ + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevCheckPendingRecvMsgsAsync: (dev: 0x%X)\n", (A_UINT32)pDev)); + + do { + + if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) { + /* break the async processing chain right here, no need to continue. + * The DevDsrHandler() will handle things in a loop when things are driven + * synchronously */ + break; + } + /* first allocate one of our HTC packets we created for async I/O + * we reuse HTC packet definitions so that we can use the completion mechanism + * in DevRWCompletionHandler() */ + pIOPacket = AR6KAllocIOPacket(pDev); + + if (NULL == pIOPacket) { + /* there should be only 1 asynchronous request out at a time to read these registers + * so this should actually never happen */ + status = A_NO_MEMORY; + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* stick in our completion routine when the I/O operation completes */ + pIOPacket->Completion = DevGetEventAsyncHandler; + pIOPacket->pContext = pDev; + + if (pDev->GetPendingEventsFunc) { + /* HIF layer has it's own mechanism, pass the IO to it.. */ + status = pDev->GetPendingEventsFunc(pDev->HIFDevice, + (HIF_PENDING_EVENTS_INFO *)pIOPacket->pBuffer, + pIOPacket); + + } else { + /* standard way, read the interrupt register table asynchronously again */ + status = HIFReadWrite(pDev->HIFDevice, + HOST_INT_STATUS_ADDRESS, + pIOPacket->pBuffer, + AR6K_IRQ_PROC_REGS_SIZE, + HIF_RD_ASYNC_BYTE_INC, + pIOPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Async IO issued to get interrupt status...\n")); + } while (FALSE); + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevCheckPendingRecvMsgsAsync \n")); + + return status; +} + +/* process pending interrupts synchronously */ +static A_STATUS ProcessPendingIRQs(AR6K_DEVICE *pDev, A_BOOL *pDone, A_BOOL *pASyncProcessing) +{ + A_STATUS status = A_OK; + A_UINT8 host_int_status = 0; + A_UINT32 lookAhead = 0; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+ProcessPendingIRQs: (dev: 0x%X)\n", (A_UINT32)pDev)); + + /*** NOTE: the HIF implementation guarantees that the context of this call allows + * us to perform SYNCHRONOUS I/O, that is we can block, sleep or call any API that + * can block or switch thread/task ontexts. + * This is a fully schedulable context. + * */ + do { + + if (pDev->IrqEnableRegisters.int_status_enable == 0) { + /* interrupt enables have been cleared, do not try to process any pending interrupts that + * may result in more bus transactions. The target may be unresponsive at this + * point. */ + break; + } + + if (pDev->GetPendingEventsFunc != NULL) { + HIF_PENDING_EVENTS_INFO events; + + /* the HIF layer uses a special mechanism to get events + * get this synchronously */ + status = pDev->GetPendingEventsFunc(pDev->HIFDevice, + &events, + NULL); + + if (A_FAILED(status)) { + break; + } + + if (events.Events & HIF_RECV_MSG_AVAIL) { + lookAhead = events.LookAhead; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs1 lookAhead is zero! \n")); + } + } + + if (!(events.Events & HIF_OTHER_EVENTS) || + !(pDev->IrqEnableRegisters.int_status_enable & OTHER_INTS_ENABLED)) { + /* no need to read the register table, no other interesting interrupts. + * Some interfaces (like SPI) can shadow interrupt sources without + * requiring the host to do a full table read */ + break; + } + + /* otherwise fall through and read the register table */ + } + + /* + * Read the first 28 bytes of the HTC register table. This will yield us + * the value of different int status registers and the lookahead + * registers. + * length = sizeof(int_status) + sizeof(cpu_int_status) + + * sizeof(error_int_status) + sizeof(counter_int_status) + + * sizeof(mbox_frame) + sizeof(rx_lookahead_valid) + + * sizeof(hole) + sizeof(rx_lookahead) + + * sizeof(int_status_enable) + sizeof(cpu_int_status_enable) + + * sizeof(error_status_enable) + + * sizeof(counter_int_status_enable); + * + */ + status = HIFReadWrite(pDev->HIFDevice, + HOST_INT_STATUS_ADDRESS, + (A_UINT8 *)&pDev->IrqProcRegisters, + AR6K_IRQ_PROC_REGS_SIZE, + HIF_RD_SYNC_BYTE_INC, + NULL); + + if (A_FAILED(status)) { + break; + } + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_IRQ)) { + DevDumpRegisters(&pDev->IrqProcRegisters, + &pDev->IrqEnableRegisters); + } + + /* Update only those registers that are enabled */ + host_int_status = pDev->IrqProcRegisters.host_int_status & + pDev->IrqEnableRegisters.int_status_enable; + + if (NULL == pDev->GetPendingEventsFunc) { + /* only look at mailbox status if the HIF layer did not provide this function, + * on some HIF interfaces reading the RX lookahead is not valid to do */ + if (host_int_status & (1 << HTC_MAILBOX)) { + /* mask out pending mailbox value, we use "lookAhead" as the real flag for + * mailbox processing below */ + host_int_status &= ~(1 << HTC_MAILBOX); + if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) { + /* mailbox has a message and the look ahead is valid */ + lookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX]; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs2, lookAhead is zero! \n")); + } + } + } + } else { + /* not valid to check if the HIF has another mechanism for reading mailbox pending status*/ + host_int_status &= ~(1 << HTC_MAILBOX); + } + + } while (FALSE); + + + do { + + /* did the interrupt status fetches succeed? */ + if (A_FAILED(status)) { + break; + } + + if ((0 == host_int_status) && (0 == lookAhead)) { + /* nothing to process, the caller can use this to break out of a loop */ + *pDone = TRUE; + break; + } + + if (lookAhead != 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Pending mailbox message, LookAhead: 0x%X\n",lookAhead)); + /* Mailbox Interrupt, the HTC layer may issue async requests to empty the + * mailbox... + * When emptying the recv mailbox we use the async handler above called from the + * completion routine of the callers read request. This can improve performance + * by reducing context switching when we rapidly pull packets */ + status = pDev->MessagePendingCallback(pDev->HTCContext, lookAhead, pASyncProcessing); + if (A_FAILED(status)) { + break; + } + } + + /* now handle the rest of them */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + (" Valid interrupt source(s) for OTHER interrupts: 0x%x\n", + host_int_status)); + + if (HOST_INT_STATUS_CPU_GET(host_int_status)) { + /* CPU Interrupt */ + status = DevServiceCPUInterrupt(pDev); + if (A_FAILED(status)){ + break; + } + } + + if (HOST_INT_STATUS_ERROR_GET(host_int_status)) { + /* Error Interrupt */ + status = DevServiceErrorInterrupt(pDev); + if (A_FAILED(status)){ + break; + } + } + + if (HOST_INT_STATUS_COUNTER_GET(host_int_status)) { + /* Counter Interrupt */ + status = DevServiceCounterInterrupt(pDev); + if (A_FAILED(status)){ + break; + } + } + + } while (FALSE); + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-ProcessPendingIRQs: (done:%d, async:%d) status=%d \n", + *pDone, *pASyncProcessing, status)); + + return status; +} + + +/* Synchronousinterrupt handler, this handler kicks off all interrupt processing.*/ +A_STATUS DevDsrHandler(void *context) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)context; + A_STATUS status = A_OK; + A_BOOL done = FALSE; + A_BOOL asyncProc = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDsrHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); + + + while (!done) { + status = ProcessPendingIRQs(pDev, &done, &asyncProc); + if (A_FAILED(status)) { + break; + } + + if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) { + /* the HIF layer does not allow async IRQ processing, override the asyncProc flag */ + asyncProc = FALSE; + /* this will cause us to re-enter ProcessPendingIRQ() and re-read interrupt status registers. + * this has a nice side effect of blocking us until all async read requests are completed. + * This behavior is required on some HIF implementations that do not allow ASYNC + * processing in interrupt handlers (like Windows CE) */ + } + + if (asyncProc) { + /* the function performed some async I/O for performance, we + need to exit the ISR immediately, the check below will prevent the interrupt from being + Ack'd while we handle it asynchronously */ + break; + } + + } + + if (A_SUCCESS(status) && !asyncProc) { + /* Ack the interrupt only if : + * 1. we did not get any errors in processing interrupts + * 2. there are no outstanding async processing requests */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Acking interrupt from DevDsrHandler \n")); + HIFAckInterrupt(pDev->HIFDevice); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDsrHandler \n")); + return status; +} + + diff -urN linux-2.6.26/drivers/net/wireless/ar6000/bmi.c linux-2.6.26-lab126/drivers/net/wireless/ar6000/bmi.c --- linux-2.6.26/drivers/net/wireless/ar6000/bmi.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/bmi.c 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,778 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// +// Author(s): ="Atheros" +//============================================================================== + +#include "hif.h" +#include "bmi.h" +#include "htc_api.h" +#include "bmi_internal.h" + +/* +Although we had envisioned BMI to run on top of HTC, this is not what the +final implementation boiled down to on chip. Its a part of BSP and does +not use the HTC protocol either. On the host side, however, we were still +living with the original idea. I think the time has come to accept the truth +and separate it from HTC which has been carrying BMI's burden all this while. +It shall make HTC state machine relatively simpler +*/ + +/* APIs visible to the driver */ +void +BMIInit(void) +{ + bmiDone = FALSE; +} + +A_STATUS +BMIDone(HIF_DEVICE *device) +{ + A_STATUS status; + A_UINT32 cid; + + if (bmiDone) { + AR_DEBUG_PRINTF (ATH_DEBUG_BMI, ("BMIDone skipped\n")); + return A_OK; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Enter (device: 0x%p)\n", device)); + bmiDone = TRUE; + cid = BMI_DONE; + + status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid)); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Exit\n")); + + return A_OK; +} + +A_STATUS +BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info) +{ + A_STATUS status; + A_UINT32 cid; + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Enter (device: 0x%p)\n", device)); + cid = BMI_GET_TARGET_INFO; + + status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid)); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_ver, + sizeof(targ_info->target_ver)); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Version from the device\n")); + return A_ERROR; + } + + if (targ_info->target_ver == TARGET_VERSION_SENTINAL) { + /* Determine how many bytes are in the Target's targ_info */ + status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_info_byte_count, + sizeof(targ_info->target_info_byte_count)); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info Byte Count from the device\n")); + return A_ERROR; + } + + /* + * The Target's targ_info doesn't match the Host's targ_info. + * We need to do some backwards compatibility work to make this OK. + */ + A_ASSERT(targ_info->target_info_byte_count == sizeof(*targ_info)); + + /* Read the remainder of the targ_info */ + status = bmiBufferReceive(device, + ((A_UCHAR *)targ_info)+sizeof(targ_info->target_info_byte_count), + sizeof(*targ_info)-sizeof(targ_info->target_info_byte_count)); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info (%d bytes) from the device\n", + targ_info->target_info_byte_count)); + return A_ERROR; + } + } else { + /* + * Target must be an AR6001 whose firmware does not + * support BMI_GET_TARGET_INFO. Construct the data + * that it would have sent. + */ + targ_info->target_info_byte_count=sizeof(*targ_info); + targ_info->target_type=TARGET_TYPE_AR6001; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Exit (ver: 0x%x type: 0x%x)\n", + targ_info->target_ver, targ_info->target_type)); + + return A_OK; +} + +A_STATUS +BMIReadMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + A_UINT32 remaining, rxlen; + static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)]; + memset (&data, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Read Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n", + device, address, length)); + + cid = BMI_READ_MEMORY; + + remaining = length; + + while (remaining) + { + rxlen = (remaining < BMI_DATASZ_MAX) ? remaining : BMI_DATASZ_MAX; + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&data[offset], &rxlen, sizeof(rxlen)); + offset += sizeof(length); + + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + status = bmiBufferReceive(device, data, rxlen); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + A_MEMCPY(&buffer[length - remaining], data, rxlen); + remaining -= rxlen; address += rxlen; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read Memory: Exit\n")); + return A_OK; +} + +A_STATUS +BMIWriteMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + A_UINT32 remaining, txlen; + const A_UINT32 header = sizeof(cid) + sizeof(address) + sizeof(length); + static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)]; + memset (&data, 0, BMI_DATASZ_MAX+header); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Write Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n", + device, address, length)); + + cid = BMI_WRITE_MEMORY; + + remaining = length; + while (remaining) + { + txlen = (remaining < (BMI_DATASZ_MAX - header)) ? + remaining : (BMI_DATASZ_MAX - header); + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&data[offset], &txlen, sizeof(txlen)); + offset += sizeof(txlen); + A_MEMCPY(&data[offset], &buffer[length - remaining], txlen); + offset += txlen; + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + remaining -= txlen; address += txlen; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Write Memory: Exit\n")); + + return A_OK; +} + +A_STATUS +BMIExecute(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address) + sizeof(*param)]; + memset (&data, 0, sizeof(cid) + sizeof(address) + sizeof(*param)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Execute: Enter (device: 0x%p, address: 0x%x, param: %d)\n", + device, address, *param)); + + cid = BMI_EXECUTE; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&data[offset], param, sizeof(*param)); + offset += sizeof(*param); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, data, sizeof(*param)); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + + A_MEMCPY(param, data, sizeof(*param)); + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Execute: Exit (param: %d)\n", *param)); + return A_OK; +} + +A_STATUS +BMISetAppStart(HIF_DEVICE *device, + A_UINT32 address) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address)]; + memset (&data, 0, sizeof(cid) + sizeof(address)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Set App Start: Enter (device: 0x%p, address: 0x%x)\n", + device, address)); + + cid = BMI_SET_APP_START; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Set App Start: Exit\n")); + return A_OK; +} + +A_STATUS +BMIReadSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address)]; + memset (&data, 0, sizeof(cid) + sizeof(address)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Read SOC Register: Enter (device: 0x%p, address: 0x%x)\n", + device, address)); + + cid = BMI_READ_SOC_REGISTER; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, data, sizeof(*param)); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + A_MEMCPY(param, data, sizeof(*param)); + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit (value: %d)\n", *param)); + return A_OK; +} + +A_STATUS +BMIWriteSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 param) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address) + sizeof(param)]; + + memset (&data, 0, sizeof(cid) + sizeof(address) + sizeof(param)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Write SOC Register: Enter (device: 0x%p, address: 0x%x, param: %d)\n", + device, address, param)); + + cid = BMI_WRITE_SOC_REGISTER; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&data[offset], ¶m, sizeof(param)); + offset += sizeof(param); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit\n")); + return A_OK; +} + +A_STATUS +BMIrompatchInstall(HIF_DEVICE *device, + A_UINT32 ROM_addr, + A_UINT32 RAM_addr, + A_UINT32 nbytes, + A_UINT32 do_activate, + A_UINT32 *rompatch_id) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) + + sizeof(nbytes) + sizeof(do_activate)]; + + memset (&data, 0, sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) + + sizeof(nbytes) + sizeof(do_activate)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI rompatch Install: Enter (device: 0x%p, ROMaddr: 0x%x, RAMaddr: 0x%x length: %d activate: %d)\n", + device, ROM_addr, RAM_addr, nbytes, do_activate)); + + cid = BMI_ROMPATCH_INSTALL; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &ROM_addr, sizeof(ROM_addr)); + offset += sizeof(ROM_addr); + A_MEMCPY(&data[offset], &RAM_addr, sizeof(RAM_addr)); + offset += sizeof(RAM_addr); + A_MEMCPY(&data[offset], &nbytes, sizeof(nbytes)); + offset += sizeof(nbytes); + A_MEMCPY(&data[offset], &do_activate, sizeof(do_activate)); + offset += sizeof(do_activate); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, (A_UCHAR *)rompatch_id, sizeof(*rompatch_id)); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch Install: (rompatch_id=%d)\n", *rompatch_id)); + return A_OK; +} + +A_STATUS +BMIrompatchUninstall(HIF_DEVICE *device, + A_UINT32 rompatch_id) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(rompatch_id)]; + memset (&data, 0, sizeof(cid) + sizeof(rompatch_id)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI rompatch Uninstall: Enter (device: 0x%p, rompatch_id: %d)\n", + device, rompatch_id)); + + cid = BMI_ROMPATCH_UNINSTALL; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &rompatch_id, sizeof(rompatch_id)); + offset += sizeof(rompatch_id); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch UNinstall: (rompatch_id=0x%x)\n", rompatch_id)); + return A_OK; +} + +static A_STATUS +_BMIrompatchChangeActivation(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list, + A_UINT32 do_activate) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count)]; + A_UINT32 length; + + memset (&data, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Change rompatch Activation: Enter (device: 0x%p, count: %d)\n", + device, rompatch_count)); + + cid = do_activate ? BMI_ROMPATCH_ACTIVATE : BMI_ROMPATCH_DEACTIVATE; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &rompatch_count, sizeof(rompatch_count)); + offset += sizeof(rompatch_count); + length = rompatch_count * sizeof(*rompatch_list); + A_MEMCPY(&data[offset], rompatch_list, length); + offset += length; + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Change rompatch Activation: Exit\n")); + + return A_OK; +} + +A_STATUS +BMIrompatchActivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list) +{ + return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 1); +} + +A_STATUS +BMIrompatchDeactivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list) +{ + return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 0); +} + +A_STATUS +BMILZData(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + A_UINT32 remaining, txlen; + const A_UINT32 header = sizeof(cid) + sizeof(length); + static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(length)]; + + memset (&data, 0, BMI_DATASZ_MAX+header); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Send LZ Data: Enter (device: 0x%p, length: %d)\n", + device, length)); + + cid = BMI_LZ_DATA; + + remaining = length; + while (remaining) + { + txlen = (remaining < (BMI_DATASZ_MAX - header)) ? + remaining : (BMI_DATASZ_MAX - header); + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &txlen, sizeof(txlen)); + offset += sizeof(txlen); + A_MEMCPY(&data[offset], &buffer[length - remaining], txlen); + offset += txlen; + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + remaining -= txlen; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI LZ Data: Exit\n")); + + return A_OK; +} + +A_STATUS +BMILZStreamStart(HIF_DEVICE *device, + A_UINT32 address) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address)]; + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI LZ Stream Start: Enter (device: 0x%p, address: 0x%x)\n", + device, address)); + + cid = BMI_LZ_STREAM_START; + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to Start LZ Stream to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI LZ Stream Start: Exit\n")); + + return A_OK; +} + +/* BMI Access routines */ +A_STATUS +bmiBufferSend(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_STATUS status; + A_UINT32 timeout; + A_UINT32 address; + static A_UINT32 cmdCredits; + A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX]; + + HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR, + &mboxAddress[0], sizeof(mboxAddress)); + + cmdCredits = 0; + timeout = BMI_COMMUNICATION_TIMEOUT; + + while(timeout-- && !cmdCredits) { + /* Read the counter register to get the command credits */ + address = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4; + /* hit the credit counter with a 4-byte access, the first byte read will hit the counter and cause + * a decrement, while the remaining 3 bytes has no effect. The rationale behind this is to + * make all HIF accesses 4-byte aligned */ + status = HIFReadWrite(device, address, (A_UINT8 *)&cmdCredits, 4, + HIF_RD_SYNC_BYTE_INC, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to decrement the command credit count register\n")); + return A_ERROR; + } + /* the counter is only 8=bits, ignore anything in the upper 3 bytes */ + cmdCredits &= 0xFF; + } + + if (cmdCredits) { + address = mboxAddress[ENDPOINT1]; + status = HIFReadWrite(device, address, buffer, length, + HIF_WR_SYNC_BYTE_INC, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to send the BMI data to the device\n")); + return A_ERROR; + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout\n")); + return A_ERROR; + } + + return status; +} + +A_STATUS +bmiBufferReceive(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_STATUS status; + A_UINT32 address; + A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX]; + + HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR, + &mboxAddress[0], sizeof(mboxAddress)); + +#define AVOID_BMI_READ_TIMEOUTS 0 +#if AVOID_BMI_READ_TIMEOUTS + /* + * During normal bootups, small reads may be required. + * Rather than issue an HIF Read and then wait as the Target adds + * successive bytes to the FIFO, we wait here until the Target + * has finished the entire response and has issued the next + * BMI Command Credit. At that point we read the full response + * and continue. This allows us to cleanly timeout on an unexpected + * Target failure rather than risk problems at the HIF level. In + * particular, this avoids SDIO timeouts. And on an interconnect + * such as Compact Flash that does not provide any indication on + * data timeout, it avoids a potential hang. + * + * This synchronization doesn't work for reads larger than the + * size of the MBOX FIFO (128B), because the Target is unable + * to push the 129th byte of data until AFTER an HIF Read is + * posted. So for large reads we proceed to post the HIF Read + * without this safety net. Fortunately, large BMI reads do not + * occur in practice -- they're supported for debug/development. + * + * This credit check is also useless when firmware chooses to + * allow multiple outstanding BMI Command Credits. To restrict + * the Target to one BMI Command Credit, see HI_OPTION_BMI_CRED_LIMIT. + * + * For a more conservative Host implementation (which would be + * safer for a Compact Flash interconnect): + * Set AVOID_BMI_READ_TIMEOUTS (above) to 1 and + * Set HI_OPTION_BMI_CRED_LIMIT and + * reduce BMI_DATASZ_MAX to 32 or 64 + */ + if (length < 128) { /* check against MBOX FIFO size */ + A_UINT32 timeout; + static A_UINT32 cmdCredits; + cmdCredits = 0; + timeout = BMI_COMMUNICATION_TIMEOUT; + while(timeout-- && !cmdCredits) { + /* Read the counter register to get the command credits */ + address = COUNT_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 1; + /* read the counter using a 4-byte read. Since the counter is NOT auto-decrementing, + * we can read this counter multiple times using a non-incrementing address mode. + * The rationale here is to make all HIF accesses a multiple of 4 bytes */ + status = HIFReadWrite(device, address, (A_UINT8 *)&cmdCredits, sizeof(cmdCredits), + HIF_RD_SYNC_BYTE_FIX, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the command credit count register\n")); + return A_ERROR; + } + /* we did a 4-byte read to the same count register so mask off upper bytes */ + cmdCredits &= 0xFF; + } + + if (!cmdCredits) { + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Communication timeout\n")); + return A_ERROR; + } + } +#endif + + address = mboxAddress[ENDPOINT1]; + status = HIFReadWrite(device, address, buffer, length, HIF_RD_SYNC_BYTE_INC, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the BMI data from the device\n")); + return A_ERROR; + } + + return A_OK; +} diff -urN linux-2.6.26/drivers/net/wireless/ar6000/common_drv.c linux-2.6.26-lab126/drivers/net/wireless/ar6000/common_drv.c --- linux-2.6.26/drivers/net/wireless/ar6000/common_drv.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/common_drv.c 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,851 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "AR6002/hw/mbox_host_reg.h" +#if defined(CONFIG_AR6002_REV1_FORCE_HOST) +#include "AR6002/hw/vmc_reg.h" +#endif +#include "targaddrs.h" +#include "a_osapi.h" +#include "hif.h" +#include "htc_api.h" +#include "wmi.h" +#include "bmi.h" +#include "bmi_msg.h" +#include "common_drv.h" +#include "a_debug.h" + +#define HOST_INTEREST_ITEM_ADDRESS(target, item) \ +(((target) == TARGET_TYPE_AR6001) ? \ + AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \ + AR6002_HOST_INTEREST_ITEM_ADDRESS(item)) + + +#define AR6001_LOCAL_COUNT_ADDRESS 0x0c014080 +#define AR6002_LOCAL_COUNT_ADDRESS 0x00018080 +#define AR6001_RESET_CONTROL_ADDRESS 0x0C000000 +#define AR6002_RESET_CONTROL_ADDRESS 0x00004000 + +#define RESET_CONTROL_COLD_RST_MASK 0x00000100 +#define RESET_CONTROL_WARM_RST_MASK 0x00000080 +#define RESET_CAUSE_LAST_MASK 0x00000007 + +/* Compile the 4BYTE version of the window register setup routine, + * This mitigates host interconnect issues with non-4byte aligned bus requests, some + * interconnects use bus adapters that impose strict limitations. + * Since diag window access is not intended for performance critical operations, the 4byte mode should + * be satisfactory even though it generates 4X the bus activity. */ + +#ifdef USE_4BYTE_REGISTER_ACCESS + + /* set the window address register (using 4-byte register access ). */ +A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address) +{ + A_STATUS status; + A_UINT8 addrValue[4]; + A_INT32 i; + + /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written + * last to initiate the access cycle */ + + for (i = 1; i <= 3; i++) { + /* fill the buffer with the address byte value we want to hit 4 times*/ + addrValue[0] = ((A_UINT8 *)&Address)[i]; + addrValue[1] = addrValue[0]; + addrValue[2] = addrValue[0]; + addrValue[3] = addrValue[0]; + + /* hit each byte of the register address with a 4-byte write operation to the same address, + * this is a harmless operation */ + status = HIFReadWrite(hifDevice, + RegisterAddr+i, + addrValue, + 4, + HIF_WR_SYNC_BYTE_FIX, + NULL); + if (status != A_OK) { + break; + } + } + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n", + RegisterAddr, Address)); + return status; + } + + /* write the address register again, this time write the whole 4-byte value. + * The effect here is that the LSB write causes the cycle to start, the extra + * 3 byte write to bytes 1,2,3 has no effect since we are writing the same values again */ + status = HIFReadWrite(hifDevice, + RegisterAddr, + (A_UCHAR *)(&Address), + 4, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n", + RegisterAddr, Address)); + return status; + } + + return A_OK; + + + +} + + +#else + + /* set the window address register */ +A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address) +{ + A_STATUS status; + + /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written + * last to initiate the access cycle */ + status = HIFReadWrite(hifDevice, + RegisterAddr+1, /* write upper 3 bytes */ + ((A_UCHAR *)(&Address))+1, + sizeof(A_UINT32)-1, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n", + RegisterAddr, Address)); + return status; + } + + /* write the LSB of the register, this initiates the operation */ + status = HIFReadWrite(hifDevice, + RegisterAddr, + (A_UCHAR *)(&Address), + sizeof(A_UINT8), + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n", + RegisterAddr, Address)); + return status; + } + + return A_OK; +} + +#endif + +/* + * Read from the AR6000 through its diagnostic window. + * No cooperation from the Target is required for this. + */ +A_STATUS +ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data) +{ + A_STATUS status; + + /* set window register to start read cycle */ + status = ar6000_SetAddressWindowRegister(hifDevice, + WINDOW_READ_ADDR_ADDRESS, + *address); + + if (status != A_OK) { + return status; + } + + /* read the data */ + status = HIFReadWrite(hifDevice, + WINDOW_DATA_ADDRESS, + (A_UCHAR *)data, + sizeof(A_UINT32), + HIF_RD_SYNC_BYTE_INC, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from WINDOW_DATA_ADDRESS\n")); + return status; + } + + return status; +} + + +/* + * Write to the AR6000 through its diagnostic window. + * No cooperation from the Target is required for this. + */ +A_STATUS +ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data) +{ + A_STATUS status; + + /* set write data */ + status = HIFReadWrite(hifDevice, + WINDOW_DATA_ADDRESS, + (A_UCHAR *)data, + sizeof(A_UINT32), + HIF_WR_SYNC_BYTE_INC, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to WINDOW_DATA_ADDRESS\n", *data)); + return status; + } + + /* set window register, which starts the write cycle */ + return ar6000_SetAddressWindowRegister(hifDevice, + WINDOW_WRITE_ADDR_ADDRESS, + *address); + } + +A_STATUS +ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length) +{ + A_UINT32 count; + A_STATUS status = A_OK; + + for (count = 0; count < length; count += 4, address += 4) { + if ((status = ar6000_ReadRegDiag(hifDevice, &address, + (A_UINT32 *)&data[count])) != A_OK) + { + break; + } + } + + return status; +} + +A_STATUS +ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length) +{ + A_UINT32 count; + A_STATUS status = A_OK; + + for (count = 0; count < length; count += 4, address += 4) { + if ((status = ar6000_WriteRegDiag(hifDevice, &address, + (A_UINT32 *)&data[count])) != A_OK) + { + break; + } + } + + return status; +} + +static A_STATUS +_do_write_diag(HIF_DEVICE *hifDevice, A_UINT32 addr, A_UINT32 value) +{ + A_STATUS status; + + status = ar6000_WriteRegDiag(hifDevice, &addr, &value); + if (status != A_OK) + { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot force Target to execute ROM!\n")); + } + + return status; +} + + +/* + * Delay up to wait_msecs millisecs to allow Target to enter BMI phase, + * which is a good sign that it's alive and well. This is used after + * explicitly forcing the Target to reset. + * + * The wait_msecs time should be sufficiently long to cover any reasonable + * boot-time delay. For instance, AR6001 firmware allow one second for a + * low frequency crystal to settle before it calibrates the refclk frequency. + * + * TBD: Might want to add special handling for AR6K_OPTION_BMI_DISABLE. + */ +static A_STATUS +_delay_until_target_alive(HIF_DEVICE *hifDevice, A_INT32 wait_msecs, A_UINT32 TargetType) +{ + A_INT32 actual_wait; + A_INT32 i; + A_UINT32 address; + + actual_wait = 0; + + /* Hardcode the address of LOCAL_COUNT_ADDRESS based on the target type */ + if (TargetType == TARGET_TYPE_AR6001) { + address = AR6001_LOCAL_COUNT_ADDRESS; + } else { + address = AR6002_LOCAL_COUNT_ADDRESS; + } + address += 0x10; + for (i=0; actual_wait < wait_msecs; i++) { + A_UINT32 data; + + A_MDELAY(100); + actual_wait += 100; + + data = 0; + if (ar6000_ReadRegDiag(hifDevice, &address, &data) != A_OK) { + return A_ERROR; + } + + if (data != 0) { + /* No need to wait longer -- we have a BMI credit */ + return A_OK; + } + } + return A_ERROR; /* timed out */ +} + +A_STATUS +ar6000_reset_device_skipflash(HIF_DEVICE *hifDevice) +{ + struct forceROM_s { + A_UINT32 addr; + A_UINT32 data; + }; + struct forceROM_s *ForceROM; + A_INT32 szForceROM; + A_UINT32 instruction; + + static struct forceROM_s ForceROM_REV2[] = { + /* NB: This works for AR6001 REV2 ROM (old). */ + {0x00001ff0, 0x175b0027}, /* jump instruction at 0xa0001ff0 */ + {0x00001ff4, 0x00000000}, /* nop instruction at 0xa0001ff4 */ + +#define MC_REMAP_TARGET_ADDRESS 0x0c004200 +#define MC_REMAP_COMPARE_ADDRESS 0x0c004180 +#define MC_REMAP_SIZE_ADDRESS 0x0c004100 +#define MC_REMAP_VALID_ADDRESS 0x0c004080 +#define LOCAL_SCRATCH_ADDRESS 0x0c0140c0 + + {MC_REMAP_TARGET_ADDRESS, 0x00001ff0}, /* remap to 0xa0001ff0 */ + {MC_REMAP_COMPARE_ADDRESS, 0x01000040},/* ...from 0xbfc00040 */ + {MC_REMAP_SIZE_ADDRESS, 0x00000000}, /* ...1 cache line */ + {MC_REMAP_VALID_ADDRESS, 0x00000001}, /* ...remap is valid */ + + /* Force is_host_present to return TRUE */ + {0x00001fe0, 0x8c620000}, + {0x00001fe4, 0x34420002}, + {0x00001fe8, 0xac620000}, + {0x00001fec, 0x00000000}, + {MC_REMAP_TARGET_ADDRESS+4, 0x00001fe0}, /* remap to 0xa0001fe0 */ + {MC_REMAP_COMPARE_ADDRESS+4, 0x01003de0},/* ...from 0x81003de0 */ + {MC_REMAP_SIZE_ADDRESS+4, 0x00000000}, /* ...1 cache line */ + {MC_REMAP_VALID_ADDRESS+4, 0x00000001}, /* ...remap is valid */ + }; + + static struct forceROM_s ForceROM_NEW[] = { + /* NB: This works for AR6001 ROM REV3 and beyond. */ + {LOCAL_SCRATCH_ADDRESS, AR6K_OPTION_IGNORE_FLASH}, + }; + + /* + * Examine a semi-arbitrary instruction that's different + * in REV2 and other revisions. + * NB: If a Host port does not require simultaneous support + * for multiple revisions of Target ROM, this code can be elided. + */ + (void)ar6000_ReadDataDiag(hifDevice, 0x01000040, + (A_UCHAR *)&instruction, 4); + + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("instruction=0x%x\n", instruction)); + + if (instruction == 0x3c1aa200) { + /* It's an old ROM */ + ForceROM = ForceROM_REV2; + szForceROM = sizeof(ForceROM_REV2)/sizeof(*ForceROM); + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Using OLD method\n")); + } else { + ForceROM = ForceROM_NEW; + szForceROM = sizeof(ForceROM_NEW)/sizeof(*ForceROM); + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Using NEW method\n")); + } + + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Force Target to execute from ROM....\n")); + { + A_INT32 i; + + for (i = 0; i < szForceROM; i++) + { + if (_do_write_diag(hifDevice, ForceROM[i].addr, ForceROM[i].data) != A_OK) { + return A_ERROR; + } + } + } + + + { + A_INT32 attempt_number; + A_INT32 i; + + /* + * We may need multiple consecutive warm resets. Current belief is + * that if the first warm reset occurs while there are outstanding + * reads (e.g. to flash) then instruction/data loads in startup + * code -- which executes just after the reset -- may return + * bogus results. The second warm reset occurs quickly enough + * so that we're likely to still be in ROM code (i.e. not + * accessing flash) when it occurs, and everything works well. + * + * The details depend on board and flash part, so this reset algorithm + * tries a single warm reset first. If that doesn't work, we try + * multiple warm resets. + * + * TBDXXX: Hardware Eng to verify that a warm reset with pending + * reads to flash may be problematic. + */ + for (attempt_number = 1; attempt_number <= 3; attempt_number++) + { + /* Clear BMI credit counter */ + if (_do_write_diag(hifDevice, + AR6001_LOCAL_COUNT_ADDRESS+0x10, + 0) != A_OK) + { + return A_ERROR; + } + +#if defined(AR6001) + /* Clear any memctlr errors, since they're sticky */ + if (_do_write_diag(hifDevice, + ERROR_VALID_ADDRESS, + ERROR_VALID_ERROR_CAPTURE_ENABLE_MASK) != A_OK) + { + return A_ERROR; + } +#endif + + /* Issue 1 or more consecutive WARM resets */ + for (i=0; i +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "a_debug.h" +#include "htc_api.h" +#include "common_drv.h" + +/********* CREDIT DISTRIBUTION FUNCTIONS ******************************************/ + +#define NO_VO_SERVICE 1 /* currently WMI only uses 3 data streams, so we leave VO service inactive */ + +#ifdef NO_VO_SERVICE +#define DATA_SVCS_USED 3 +#else +#define DATA_SVCS_USED 4 +#endif + +static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList); + +static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList); + +/* reduce an ep's credits back to a set limit */ +static INLINE void ReduceCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEpDist, + int Limit) +{ + int credits; + + /* set the new limit */ + pEpDist->TxCreditsAssigned = Limit; + + if (pEpDist->TxCredits <= Limit) { + return; + } + + /* figure out how much to take away */ + credits = pEpDist->TxCredits - Limit; + /* take them away */ + pEpDist->TxCredits -= credits; + pCredInfo->CurrentFreeCredits += credits; +} + +/* give an endpoint some credits from the free credit pool */ +#define GiveCredits(pCredInfo,pEpDist,credits) \ +{ \ + (pEpDist)->TxCredits += (credits); \ + (pEpDist)->TxCreditsAssigned += (credits); \ + (pCredInfo)->CurrentFreeCredits -= (credits); \ +} + + +/* default credit init callback. + * This function is called in the context of HTCStart() to setup initial (application-specific) + * credit distributions */ +static void ar6000_credit_init(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + int TotalCredits) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + int count; + COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context; + + pCredInfo->CurrentFreeCredits = TotalCredits; + pCredInfo->TotalAvailableCredits = TotalCredits; + + pCurEpDist = pEPList; + + /* run through the list and initialize */ + while (pCurEpDist != NULL) { + + /* set minimums for each endpoint */ + pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg; + + if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) { + /* give control service some credits */ + GiveCredits(pCredInfo,pCurEpDist,pCurEpDist->TxCreditsMin); + /* control service is always marked active, it never goes inactive EVER */ + SET_EP_ACTIVE(pCurEpDist); + } else if (pCurEpDist->ServiceID == WMI_DATA_BK_SVC) { + /* this is the lowest priority data endpoint, save this off for easy access */ + pCredInfo->pLowestPriEpDist = pCurEpDist; + } + + /* Streams have to be created (explicit | implicit)for all kinds + * of traffic. BE endpoints are also inactive in the beginning. + * When BE traffic starts it creates implicit streams that + * redistributes credits. + */ + + /* note, all other endpoints have minimums set but are initially given NO credits. + * Credits will be distributed as traffic activity demands */ + pCurEpDist = pCurEpDist->pNext; + } + + if (pCredInfo->CurrentFreeCredits <= 0) { + AR_DEBUG_PRINTF(ATH_LOG_INF, ("Not enough credits (%d) to do credit distributions \n", TotalCredits)); + A_ASSERT(FALSE); + return; + } + + /* reset list */ + pCurEpDist = pEPList; + /* now run through the list and set max operating credit limits for everyone */ + while (pCurEpDist != NULL) { + if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) { + /* control service max is just 1 max message */ + pCurEpDist->TxCreditsNorm = pCurEpDist->TxCreditsPerMaxMsg; + } else { + /* for the remaining data endpoints, we assume that each TxCreditsPerMaxMsg are + * the same. + * We use a simple calculation here, we take the remaining credits and + * determine how many max messages this can cover and then set each endpoint's + * normal value equal to 3/4 this amount. + * */ + count = (pCredInfo->CurrentFreeCredits/pCurEpDist->TxCreditsPerMaxMsg) * pCurEpDist->TxCreditsPerMaxMsg; + count = (count * 3) >> 2; + count = max(count,pCurEpDist->TxCreditsPerMaxMsg); + /* set normal */ + pCurEpDist->TxCreditsNorm = count; + + } + pCurEpDist = pCurEpDist->pNext; + } + +} + + +/* default credit distribution callback + * This callback is invoked whenever endpoints require credit distributions. + * A lock is held while this function is invoked, this function shall NOT block. + * The pEPDistList is a list of distribution structures in prioritized order as + * defined by the call to the HTCSetCreditDistribution() api. + * + */ +static void ar6000_credit_distribute(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList, + HTC_CREDIT_DIST_REASON Reason) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context; + + switch (Reason) { + case HTC_CREDIT_DIST_SEND_COMPLETE : + pCurEpDist = pEPDistList; + /* we are given the start of the endpoint distribution list. + * There may be one or more endpoints to service. + * Run through the list and distribute credits */ + while (pCurEpDist != NULL) { + + if (pCurEpDist->TxCreditsToDist > 0) { + /* return the credits back to the endpoint */ + pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist; + /* always zero out when we are done */ + pCurEpDist->TxCreditsToDist = 0; + + if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsAssigned) { + /* reduce to the assigned limit, previous credit reductions + * could have caused the limit to change */ + ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsAssigned); + } + + if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsNorm) { + /* oversubscribed endpoints need to reduce back to normal */ + ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsNorm); + } + } + + pCurEpDist = pCurEpDist->pNext; + } + + break; + + case HTC_CREDIT_DIST_ACTIVITY_CHANGE : + RedistributeCredits(pCredInfo,pEPDistList); + break; + case HTC_CREDIT_DIST_SEEK_CREDITS : + SeekCredits(pCredInfo,pEPDistList); + break; + case HTC_DUMP_CREDIT_STATE : + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Credit Distribution, total : %d, free : %d\n", + pCredInfo->TotalAvailableCredits, pCredInfo->CurrentFreeCredits)); + break; + default: + break; + + } + + /* sanity checks done after each distribution action */ + A_ASSERT(pCredInfo->CurrentFreeCredits <= pCredInfo->TotalAvailableCredits); + A_ASSERT(pCredInfo->CurrentFreeCredits >= 0); + +} + +/* redistribute credits based on activity change */ +static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist = pEPDistList; + + /* walk through the list and remove credits from inactive endpoints */ + while (pCurEpDist != NULL) { + + if (pCurEpDist->ServiceID != WMI_CONTROL_SVC) { + if (!IS_EP_ACTIVE(pCurEpDist)) { + /* EP is inactive, reduce credits back to zero */ + ReduceCredits(pCredInfo, pCurEpDist, 0); + } + } + + /* NOTE in the active case, we do not need to do anything further, + * when an EP goes active and needs credits, HTC will call into + * our distribution function using a reason code of HTC_CREDIT_DIST_SEEK_CREDITS */ + + pCurEpDist = pCurEpDist->pNext; + } + +} + +/* HTC has an endpoint that needs credits, pEPDist is the endpoint in question */ +static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDist) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + int credits = 0; + int need; + + do { + + if (pEPDist->ServiceID == WMI_CONTROL_SVC) { + /* we never oversubscribe on the control service, this is not + * a high performance path and the target never holds onto control + * credits for too long */ + break; + } + + if (pEPDist->ServiceID == WMI_DATA_VI_SVC) { + if (pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm) { + /* limit VI service from oversubscribing */ + break; + } + } + + if (pEPDist->ServiceID == WMI_DATA_VO_SVC) { + if (pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm) { + /* limit VO service from oversubscribing */ + break; + } + } + + /* for all other services, we follow a simple algorithm of + * 1. checking the free pool for credits + * 2. checking lower priority endpoints for credits to take */ + + /* give what we can */ + credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek); + + if (credits >= pEPDist->TxCreditsSeek) { + /* we found some to fullfill the seek request */ + break; + } + + /* we don't have enough in the free pool, try taking away from lower priority services + * + * The rule for taking away credits: + * 1. Only take from lower priority endpoints + * 2. Only take what is allocated above the minimum (never starve an endpoint completely) + * 3. Only take what you need. + * + * */ + + /* starting at the lowest priority */ + pCurEpDist = pCredInfo->pLowestPriEpDist; + + /* work backwards until we hit the endpoint again */ + while (pCurEpDist != pEPDist) { + /* calculate how many we need so far */ + need = pEPDist->TxCreditsSeek - pCredInfo->CurrentFreeCredits; + + if ((pCurEpDist->TxCreditsAssigned - need) >= pCurEpDist->TxCreditsMin) { + /* the current one has been allocated more than it's minimum and it + * has enough credits assigned above it's minimum to fullfill our need + * try to take away just enough to fullfill our need */ + ReduceCredits(pCredInfo, + pCurEpDist, + pCurEpDist->TxCreditsAssigned - need); + + if (pCredInfo->CurrentFreeCredits >= pEPDist->TxCreditsSeek) { + /* we have enough */ + break; + } + } + + pCurEpDist = pCurEpDist->pPrev; + } + + /* return what we can get */ + credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek); + + } while (FALSE); + + /* did we find some credits? */ + if (credits) { + /* give what we can */ + GiveCredits(pCredInfo, pEPDist, credits); + } + +} + +/* initialize and setup credit distribution */ +A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo) +{ + HTC_SERVICE_ID servicepriority[5]; + + A_MEMZERO(pCredInfo,sizeof(COMMON_CREDIT_STATE_INFO)); + + servicepriority[0] = WMI_CONTROL_SVC; /* highest */ + servicepriority[1] = WMI_DATA_VO_SVC; + servicepriority[2] = WMI_DATA_VI_SVC; + servicepriority[3] = WMI_DATA_BE_SVC; + servicepriority[4] = WMI_DATA_BK_SVC; /* lowest */ + + /* set callbacks and priority list */ + HTCSetCreditDistribution(HTCHandle, + pCredInfo, + ar6000_credit_distribute, + ar6000_credit_init, + servicepriority, + 5); + + return A_OK; +} + diff -urN linux-2.6.26/drivers/net/wireless/ar6000/engine.c linux-2.6.26-lab126/drivers/net/wireless/ar6000/engine.c --- linux-2.6.26/drivers/net/wireless/ar6000/engine.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/engine.c 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,278 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ +#include "engine.h" + +#define ACC regs[0] + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +static unsigned int regs[16]; +static int offset; +static unsigned char *cp; + +int ar6k_reg_preload( int reg, unsigned int value ) +{ + if( (reg < 0) || (reg > 16) ) + return(-1); /* Illegal register */ + + regs[ reg ] = value; + return(0); +} + +static int getoffset( void ) +{ + int i = 0; + + cp++; + offset++; + + i |= (*cp & 0xFF); cp++; offset++; + i |= (*cp & 0xFF) << 8; cp++; offset++; + i |= (*cp & 0xFF) << 16; cp++; offset++; + i |= (*cp & 0xFF) << 24; cp++; offset++; + + return(i); +} + +static int getarg( void ) +{ + int i; + + if( *cp & 0x0F ) + { + i = regs[ *cp & 0xF ]; + cp++; offset++; + return(i); + } + return( getoffset() ); +} + +static void dumpregs( void ) +{ + int i; + + sysprint("Acc: 0x%X\n", ACC); + + for(i=1; i<16; i++) + sysprint("r%x : 0x%X\n", i, regs[ i ]); + +} + +int fwengine( unsigned char *img, int size, void *ar) +{ + unsigned int crc; + int i; + + /* 14 is the minimal size of an empty image */ + if( ! (*img) || (*img != 0xFF) || (size <14) ) + { + syserr("Wrong image or no image\n"); + return -1; + } + + /* Check crc32 */ + cp = img + size - 4; + + *cp = ~(*cp) & 0xFF ; cp++; + *cp = ~(*cp) & 0xFF ; cp++; + *cp = ~(*cp) & 0xFF ; cp++; + *cp = ~(*cp) & 0xFF ; + + crc = crc32( ~0, img, size ); + + if( crc ) + { + syserr("Image CRC error\n"); + return -1; + } + + if( *(img+1) > VERSION ) + { + syserr("Image version is newer than the driver\n"); + return -1; + } + + /* Basic checks complete, we can print greeting and FW_ID here if desired */ + + /* Get to the first opcode */ + + cp = img + 2; /* Skip magic and version */ + offset = 2; + + while( (offset < size) && (*cp) ) + { + cp++; /* Skip build host name */ + offset++; + } + + cp += 6; /* Skip build date */ + offset += 6; + + while( (cp > img) && (cp < (img+size-4)) ) /* just an additional bounds check */ + { + /* First, find out opcode class */ + switch( (*cp & 0xF0) ) + { + case RLoad : + ACC = getarg( ); + break; + case Ror : + ACC |= getarg( ); + break; + case Rand : + ACC &= getarg( ); + break; + case Add : + ACC += getarg( ); + break; + case Rstor : + regs[ *cp & 0xF ] = ACC; + cp++; + offset++; + break; + case Shift : + i = getarg( ); + if(i < 0) + ACC >>= -i; + else + ACC <<= i; + break; + case Nneg : + if( *cp & 0xF ) + regs[ *cp & 0xF ] = ~regs[ *cp & 0xF ]; + else + ACC = -ACC; + cp++; + offset++; + break; + case Trr : + ACC = get_target_reg( getarg(), ar ); + break; + case Trw : + write_target_reg( getarg(), ACC , ar ); + break; + case Trx : + ACC = execute_on_target( getarg(), ACC, ar ); + break; + case Exit : + if( *cp & 0xF ) /* abort with code */ + return( regs[ *cp & 0xF ] ); + else{ /* clean exit */ + bmidone( ar ); + return(0); + } + break; + case Cmp : + ACC -= getarg(); + break; + case Ldprn : + if( ! (*cp & 0xF) ) /* register dump */ + dumpregs(); + else + { + int ret; + + ret = load_binary(ACC, cp, ar); + if( ret < 0 ) + return( -1 ); /* Error */ + cp += ret; + offset += ret; + } + break; + case Jump : + if( !(*cp & 0xF) || + ((*cp == 0xE1) && (ACC)) || + ((*cp == 0xE2) && !(ACC)) ) + + offset = getoffset(); + cp = img + offset; + + break; + default: + syserr("Image format error\n"); + break; + + } + } + return(0); +} +#ifdef UNIT_TEST +#include + +unsigned char fwbuf[ 4 * 1024 * 1024 ]; + +void bmidone( void *ar ) +{ + printf("BMI done.\n"); +} +int load_binary( unsigned int addr, unsigned char *cp, void *ar ) +{ + int size = 0; + int adv = 5; + + cp++; + size |= ( *cp & 0xFF ); cp++; + size |= ( *cp & 0xFF ) << 8; cp++; + size |= ( *cp & 0xFF ) << 16; cp++; + size |= ( *cp & 0xFF ) << 24; cp++; + + printf("Loading binary to address 0x%X, size %d\n", addr, size); + adv += size; + return(adv); +} + +int execute_on_target( unsigned address, unsigned arg, void *ar ) +{ + printf("Start target execution at address 0x%X with argument 0x%X\n", address, arg); + return(0); +} + +int write_target_reg( unsigned address, unsigned value, void *ar ) +{ + printf("Writing target register 0x%X with 0x%X\n", address, value); + return(0); +} + +unsigned int get_target_reg( unsigned address, void *ar ) +{ + unsigned int ret = 1; + + printf("Reading target register 0x%X, returning 0x%X\n", address, ret ); + return (ret); +} +int main() +{ + int ch, ret; + unsigned char *bufptr = fwbuf; + + init_crc32(); + + printf("Reading firmware image\n"); + while( (ch = getchar()) != EOF) + *bufptr++ = ch; + + printf("Calling firmware engine for image size: %d\n", bufptr - fwbuf + 1); + ret = engine( fwbuf, bufptr - fwbuf, NULL ); + printf("Engine returned with code %d\n", ret); +} +#endif /* UNIT_TEST */ +#endif /* KERNEL_VERSION 2.6 only */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/hif.c linux-2.6.26-lab126/drivers/net/wireless/ar6000/hif.c --- linux-2.6.26/drivers/net/wireless/ar6000/hif.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/hif.c 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,718 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// HIF layer reference implementation for Linux Native MMC stack +// +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include +/* by default setup a bounce buffer for the data packets, if the underlying host controller driver + does not use DMA you may be able to skip this step and save the memory allocation and transfer time */ +#define HIF_USE_DMA_BOUNCE_BUFFER 1 +#include "hif_internal.h" + + +static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id); +static void hifDeviceRemoved(struct sdio_func *func); +static HIF_DEVICE *addHifDevice(struct sdio_func *func); +static HIF_DEVICE *getHifDevice(struct sdio_func *func); +static void delHifDevice(HIF_DEVICE * device); + + + +/* ------ Static Variables ------ */ +static const struct sdio_device_id ar6k_id_table[] = { + { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x0)) }, + { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x1)) }, + { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0)) }, + { /* null */ }, +}; +MODULE_DEVICE_TABLE(sdio, ar6k_id_table); + +static struct sdio_driver ar6k_driver = { + .name = "ar6k_wlan", + .id_table = ar6k_id_table, + .probe = hifDeviceInserted, + .remove = hifDeviceRemoved, +}; +/* make sure we only unregister when registered. */ +static int registered = 0; + +HTC_CALLBACKS htcCallbacks; +extern A_UINT32 onebitmode; +extern A_UINT32 busspeedlow; +extern A_UINT32 debughif; + +#ifdef DEBUG +#define ATH_DEBUG_ERROR 1 +#define ATH_DEBUG_WARN 2 +#define ATH_DEBUG_TRACE 3 +#define _AR_DEBUG_PRINTX_ARG(arg...) arg +#define AR_DEBUG_PRINTF(lvl, args)\ + {if (lvl <= debughif)\ + A_PRINTF(KERN_ALERT _AR_DEBUG_PRINTX_ARG args);\ + } +#define AR_DEBUG_ASSERT(test) do { \ + if (!(test)) { \ + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test)); \ + } \ +} while(0) +#else +#define AR_DEBUG_PRINTF(lvl, args) +#define AR_DEBUG_ASSERT(test) +#endif + +static BUS_REQUEST *hifAllocateBusRequest(HIF_DEVICE *device); +static void hifFreeBusRequest(HIF_DEVICE *device, BUS_REQUEST *busrequest); +static void ResetAllCards(void); + +/* ------ Functions ------ */ +int HIFInit(HTC_CALLBACKS *callbacks) +{ + int status; + AR_DEBUG_ASSERT(callbacks != NULL); + + /* Store the callback and event handlers */ + htcCallbacks.deviceInsertedHandler = callbacks->deviceInsertedHandler; + htcCallbacks.deviceRemovedHandler = callbacks->deviceRemovedHandler; + htcCallbacks.deviceSuspendHandler = callbacks->deviceSuspendHandler; + htcCallbacks.deviceResumeHandler = callbacks->deviceResumeHandler; + htcCallbacks.deviceWakeupHandler = callbacks->deviceWakeupHandler; + htcCallbacks.rwCompletionHandler = callbacks->rwCompletionHandler; + htcCallbacks.dsrHandler = callbacks->dsrHandler; + + /* Register with bus driver core */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFInit registering\n")); + registered = 1; + status = sdio_register_driver(&ar6k_driver); + AR_DEBUG_ASSERT(status==0); + + if (status != 0) { + return A_ERROR; + } + + return A_OK; + +} + +static A_STATUS +__HIFReadWrite(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length, + A_UINT32 request, + void *context) +{ + A_UINT8 opcode; + A_STATUS status = A_OK; + int ret; + A_UINT8 *tbuffer; + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device: 0x%p, buffer:0x%p\n", device, buffer)); + + do { + if (request & HIF_EXTENDED_IO) { + //AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Command type: CMD53\n")); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid command type: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + + if (request & HIF_BLOCK_BASIS) { + /* round to whole block length size */ + length = (length / HIF_MBOX_BLOCK_SIZE) * HIF_MBOX_BLOCK_SIZE; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Block mode (BlockLen: %d)\n", + length)); + } else if (request & HIF_BYTE_BASIS) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Byte mode (BlockLen: %d)\n", + length)); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid data mode: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + +#if 0 + /* useful for checking register accesses */ + if (length & 0x3) { + A_PRINTF(KERN_ALERT"AR6000: HIF (%s) is not a multiple of 4 bytes, addr:0x%X, len:%d\n", + request & HIF_WRITE ? "write":"read", address, length); + } +#endif + + if ((address >= HIF_MBOX_START_ADDR(0)) && + (address <= HIF_MBOX_END_ADDR(3))) + { + + AR_DEBUG_ASSERT(length <= HIF_MBOX_WIDTH); + + /* + * Mailbox write. Adjust the address so that the last byte + * falls on the EOM address. + */ + address += (HIF_MBOX_WIDTH - length); + } + + if (request & HIF_FIXED_ADDRESS) { + opcode = CMD53_FIXED_ADDRESS; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Address mode: Fixed 0x%X\n", address)); + } else if (request & HIF_INCREMENTAL_ADDRESS) { + opcode = CMD53_INCR_ADDRESS; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Address mode: Incremental 0x%X\n", address)); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid address mode: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + + if (request & HIF_WRITE) { +#if HIF_USE_DMA_BOUNCE_BUFFER + AR_DEBUG_ASSERT(device->dma_buffer != NULL); + tbuffer = device->dma_buffer; + /* copy the write data to the dma buffer */ + AR_DEBUG_ASSERT(length <= HIF_DMA_BUFFER_SIZE); + memcpy(tbuffer, buffer, length); +#else + tbuffer = buffer; +#endif + if (opcode == CMD53_FIXED_ADDRESS) { + ret = sdio_writesb(device->func, address, tbuffer, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: writesb ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } else { + ret = sdio_memcpy_toio(device->func, address, tbuffer, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: writeio ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } + } else if (request & HIF_READ) { +#if HIF_USE_DMA_BOUNCE_BUFFER + AR_DEBUG_ASSERT(device->dma_buffer != NULL); + AR_DEBUG_ASSERT(length <= HIF_DMA_BUFFER_SIZE); + tbuffer = device->dma_buffer; +#else + tbuffer = buffer; +#endif + if (opcode == CMD53_FIXED_ADDRESS) { + ret = sdio_readsb(device->func, tbuffer, address, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: readsb ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } else { + ret = sdio_memcpy_fromio(device->func, tbuffer, address, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: readio ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } +#if HIF_USE_DMA_BOUNCE_BUFFER + /* copy the read data from the dma buffer */ + memcpy(buffer, tbuffer, length); +#endif + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid direction: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + + if (ret) { + status = A_ERROR; + } + } while (FALSE); + + return status; +} + +/* queue a read/write request */ +A_STATUS +HIFReadWrite(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length, + A_UINT32 request, + void *context) +{ + A_STATUS status = A_OK; + unsigned long flags; + BUS_REQUEST *busrequest; + BUS_REQUEST *async; + BUS_REQUEST *active; + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device: %p\n", device)); + + do { + if ((request & HIF_ASYNCHRONOUS) || (request & HIF_SYNCHRONOUS)){ + /* serialize all requests through the async thread */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Execution mode: %s\n", (request & HIF_ASYNCHRONOUS)?"Async":"Synch")); + busrequest = hifAllocateBusRequest(device); + if (busrequest == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: no async bus requests available\n")); + return A_ERROR; + } + spin_lock_irqsave(&device->asynclock, flags); + busrequest->address = address; + busrequest->buffer = buffer; + busrequest->length = length; + busrequest->request = request; + busrequest->context = context; + /* add to async list */ + active = device->asyncreq; + if (active == NULL) { + device->asyncreq = busrequest; + device->asyncreq->inusenext = NULL; + } else { + for (async = device->asyncreq; + async != NULL; + async = async->inusenext) { + active = async; + } + active->inusenext = busrequest; + busrequest->inusenext = NULL; + } + spin_unlock_irqrestore(&device->asynclock, flags); + if (request & HIF_SYNCHRONOUS) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: queued sync req: 0x%X\n", (unsigned int)busrequest)); + + /* wait for completion */ + up(&device->sem_async); + if (down_interruptible(&busrequest->sem_req) != 0) { + /* interrupted, exit */ + return A_ERROR; + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: sync return freeing 0x%X: 0x%X\n", + (unsigned int)busrequest, busrequest->status)); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: freeing req: 0x%X\n", (unsigned int)request)); + hifFreeBusRequest(device, busrequest); + return busrequest->status; + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: queued async req: 0x%X\n", (unsigned int)busrequest)); + up(&device->sem_async); + return A_PENDING; + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid execution mode: 0x%08x\n", (unsigned int)request)); + status = A_EINVAL; + break; + } + } while(0); + + return status; +} +/* thread to serialize all requests, both sync and async */ +static int async_task(void *param) + { + HIF_DEVICE *device; + BUS_REQUEST *request; + A_STATUS status; + unsigned long flags; + + device = (HIF_DEVICE *)param; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task\n")); + set_current_state(TASK_INTERRUPTIBLE); + while(!device->async_shutdown) { + /* wait for work */ + if (down_interruptible(&device->sem_async) != 0) { + /* interrupted, exit */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task interrupted\n")); + break; + } + if (device->async_shutdown) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task stopping\n")); + break; + } + /* we want to hold the host over multiple cmds if possible, but holding the host blocks card interrupts */ + sdio_claim_host(device->func); + spin_lock_irqsave(&device->asynclock, flags); + /* pull the request to work on */ + while (device->asyncreq != NULL) { + request = device->asyncreq; + if (request->inusenext != NULL) { + device->asyncreq = request->inusenext; + } else { + device->asyncreq = NULL; + } + spin_unlock_irqrestore(&device->asynclock, flags); + /* call HIFReadWrite in sync mode to do the work */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task processing req: 0x%X\n", (unsigned int)request)); + status = __HIFReadWrite(device, request->address, request->buffer, + request->length, request->request & ~HIF_SYNCHRONOUS, NULL); + if (request->request & HIF_ASYNCHRONOUS) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task completion routine req: 0x%X\n", (unsigned int)request)); + htcCallbacks.rwCompletionHandler(request->context, status); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task freeing req: 0x%X\n", (unsigned int)request)); + hifFreeBusRequest(device, request); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task upping req: 0x%X\n", (unsigned int)request)); + request->status = status; + up(&request->sem_req); + } + spin_lock_irqsave(&device->asynclock, flags); + } + spin_unlock_irqrestore(&device->asynclock, flags); + sdio_release_host(device->func); + } + + complete_and_exit(&device->async_completion, 0); + return 0; + } + +A_STATUS +HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode, + void *config, A_UINT32 configLen) +{ + A_UINT32 count; + + switch(opcode) { + case HIF_DEVICE_GET_MBOX_BLOCK_SIZE: + ((A_UINT32 *)config)[0] = HIF_MBOX0_BLOCK_SIZE; + ((A_UINT32 *)config)[1] = HIF_MBOX1_BLOCK_SIZE; + ((A_UINT32 *)config)[2] = HIF_MBOX2_BLOCK_SIZE; + ((A_UINT32 *)config)[3] = HIF_MBOX3_BLOCK_SIZE; + break; + + case HIF_DEVICE_GET_MBOX_ADDR: + for (count = 0; count < 4; count ++) { + ((A_UINT32 *)config)[count] = HIF_MBOX_START_ADDR(count); + } + break; + case HIF_DEVICE_GET_IRQ_PROC_MODE: + *((HIF_DEVICE_IRQ_PROCESSING_MODE *)config) = HIF_DEVICE_IRQ_SYNC_ONLY; + break; + default: + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, + ("AR6000: Unsupported configuration opcode: %d\n", opcode)); + return A_ERROR; + } + + return A_OK; +} + +void +HIFShutDownDevice(HIF_DEVICE *device) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +HIFShutDownDevice\n")); + if (device != NULL) { + AR_DEBUG_ASSERT(device->func != NULL); + } else { + /* since we are unloading the driver anyways, reset all cards in case the SDIO card + * is externally powered and we are unloading the SDIO stack. This avoids the problem when + * the SDIO stack is reloaded and attempts are made to re-enumerate a card that is already + * enumerated */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFShutDownDevice, resetting\n")); + ResetAllCards(); + } + /* Unregister with bus driver core */ + if (registered) { + registered = 0; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Unregistering with the bus driver\n")); + sdio_unregister_driver(&ar6k_driver); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Unregistered\n")); + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -HIFShutDownDevice\n")); +} + +static void +hifIRQHandler(struct sdio_func *func) +{ + A_STATUS status; + HIF_DEVICE *device; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifIRQHandler\n")); + + device = getHifDevice(func); + /* release the host during ints so we can pick it back up when we process cmds */ + sdio_release_host(device->func); + status = htcCallbacks.dsrHandler(device->htc_handle); + sdio_claim_host(device->func); + AR_DEBUG_ASSERT(status == A_OK); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifIRQHandler\n")); +} + +/* handle HTC startup via thread*/ +static int startup_task(void *param) +{ + HIF_DEVICE *device; + + device = (HIF_DEVICE *)param; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: call HTC from startup_task\n")); + /* start up Inform HTC */ + if ((htcCallbacks.deviceInsertedHandler(device)) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device rejected\n")); + } + return 0; +} + +static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id) +{ + int ret; + HIF_DEVICE * device; + int count; + struct task_struct* startup_task_struct; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: hifDeviceInserted, Function: 0x%X, Vendor ID: 0x%X, Device ID: 0x%X, block size: 0x%X/0x%X\n", + func->num, func->vendor, func->device, func->max_blksize, func->cur_blksize)); + + addHifDevice(func); + device = getHifDevice(func); + + spin_lock_init(&device->lock); + spin_lock_init(&device->asynclock); + + /* enable the SDIO function */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: claim\n")); + sdio_claim_host(func); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: enable\n")); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + /* give us some time to enable, in ms */ + func->enable_timeout = 100; +#endif + + ret = sdio_enable_func(func); + if (ret) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to enable AR6K: 0x%X\n", + __FUNCTION__, ret)); + sdio_release_host(func); + return ret; + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: set block size 0x%X\n", HIF_MBOX_BLOCK_SIZE)); + ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE); + sdio_release_host(func); + if (ret) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to set block size 0x%x AR6K: 0x%X\n", + __FUNCTION__, HIF_MBOX_BLOCK_SIZE, ret)); + sdio_release_host(func); + return ret; + } + /* Initialize the bus requests to be used later */ + A_MEMZERO(device->busRequest, sizeof(device->busRequest)); + for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) { + sema_init(&device->busRequest[count].sem_req, 0); + hifFreeBusRequest(device, &device->busRequest[count]); + } + + /* create async I/O thread */ + device->async_shutdown = 0; + device->async_task = kthread_create(async_task, + (void *)device, + "AR6K Async"); + if (device->async_task == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create async task\n", __FUNCTION__)); + sdio_release_host(func); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start async task\n")); + sema_init(&device->sem_async, 0); + wake_up_process(device->async_task ); + + /* create startup thread */ + startup_task_struct = kthread_create(startup_task, + (void *)device, + "AR6K startup"); + if (startup_task_struct == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create startup task\n", __FUNCTION__)); + sdio_release_host(func); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start startup task\n")); + wake_up_process(startup_task_struct); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: return %d\n", ret)); + return ret; +} + + +void +HIFAckInterrupt(HIF_DEVICE *device) +{ + AR_DEBUG_ASSERT(device != NULL); + + /* Acknowledge our function IRQ */ +} + +void +HIFUnMaskInterrupt(HIF_DEVICE *device) +{ + int ret;; + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFUnMaskInterrupt\n")); + + /* Register the IRQ Handler */ + sdio_claim_host(device->func); + ret = sdio_claim_irq(device->func, hifIRQHandler); + sdio_release_host(device->func); + AR_DEBUG_ASSERT(ret == 0); +} + +void HIFMaskInterrupt(HIF_DEVICE *device) +{ + int ret;; + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFMaskInterrupt\n")); + + /* Mask our function IRQ */ + sdio_claim_host(device->func); + ret = sdio_release_irq(device->func); + sdio_release_host(device->func); + AR_DEBUG_ASSERT(ret == 0); +} + +static BUS_REQUEST *hifAllocateBusRequest(HIF_DEVICE *device) +{ + BUS_REQUEST *busrequest; + unsigned long flag; + + /* Acquire lock */ + spin_lock_irqsave(&device->lock, flag); + + /* Remove first in list */ + if((busrequest = device->s_busRequestFreeQueue) != NULL) + { + device->s_busRequestFreeQueue = busrequest->next; + } + + /* Release lock */ + spin_unlock_irqrestore(&device->lock, flag); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: hifAllocateBusRequest: 0x%p\n", busrequest)); + return busrequest; +} + +static void +hifFreeBusRequest(HIF_DEVICE *device, BUS_REQUEST *busrequest) +{ + unsigned long flag; + + AR_DEBUG_ASSERT(busrequest != NULL); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: hifFreeBusRequest: 0x%p\n", busrequest)); + /* Acquire lock */ + spin_lock_irqsave(&device->lock, flag); + + + /* Insert first in list */ + busrequest->next = device->s_busRequestFreeQueue; + busrequest->inusenext = NULL; + device->s_busRequestFreeQueue = busrequest; + + /* Release lock */ + spin_unlock_irqrestore(&device->lock, flag); +} + +static void hifDeviceRemoved(struct sdio_func *func) +{ + A_STATUS status = A_OK; + HIF_DEVICE *device; + int ret; + AR_DEBUG_ASSERT(func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDeviceRemoved\n")); + device = getHifDevice(func); + status = htcCallbacks.deviceRemovedHandler(device->htc_handle, A_OK); + + if (device->async_task != NULL) { + init_completion(&device->async_completion); + device->async_shutdown = 1; + up(&device->sem_async); + wait_for_completion(&device->async_completion); + device->async_task = NULL; + } + /* Disable the card */ + sdio_claim_host(device->func); + ret = sdio_disable_func(device->func); + sdio_release_host(device->func); + delHifDevice(device); + AR_DEBUG_ASSERT(status == A_OK); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifDeviceRemoved\n")); +} + + +static HIF_DEVICE * +addHifDevice(struct sdio_func *func) +{ + HIF_DEVICE *hifdevice; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice\n")); + AR_DEBUG_ASSERT(func != NULL); + hifdevice = (HIF_DEVICE *)kzalloc(sizeof(HIF_DEVICE), GFP_KERNEL); + AR_DEBUG_ASSERT(hifdevice != NULL); +#if HIF_USE_DMA_BOUNCE_BUFFER + hifdevice->dma_buffer = kmalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL); + AR_DEBUG_ASSERT(hifdevice->dma_buffer != NULL); +#endif + hifdevice->func = func; + sdio_set_drvdata(func, hifdevice); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice; 0x%p\n", hifdevice)); + return hifdevice; +} + +static HIF_DEVICE * +getHifDevice(struct sdio_func *func) +{ + AR_DEBUG_ASSERT(func != NULL); + return (HIF_DEVICE *)sdio_get_drvdata(func); +} + +static void +delHifDevice(HIF_DEVICE * device) +{ + AR_DEBUG_ASSERT(device!= NULL); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: delHifDevice; 0x%p\n", device)); + if (device->dma_buffer != NULL) { + kfree(device->dma_buffer); + } + kfree(device); +} + +void HIFSetHandle(void *hif_handle, void *handle) +{ + HIF_DEVICE *device = (HIF_DEVICE *) hif_handle; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFSetHandle\n")); + if (device == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFSetHandle NULL****\n")); + } else { + device->htc_handle = handle; + } + + return; +} + +static void ResetAllCards(void) +{ +} diff -urN linux-2.6.26/drivers/net/wireless/ar6000/htc.c linux-2.6.26-lab126/drivers/net/wireless/ar6000/htc.c --- linux-2.6.26/drivers/net/wireless/ar6000/htc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/htc.c 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,580 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + + +static HTC_INIT_INFO HTCInitInfo = {NULL,NULL,NULL}; +static A_BOOL HTCInitialized = FALSE; + +static A_STATUS HTCTargetInsertedHandler(void *hif_handle); +static A_STATUS HTCTargetRemovedHandler(void *handle, A_STATUS status); +static void HTCReportFailure(void *Context); + +/* Initializes the HTC layer */ +A_STATUS HTCInit(HTC_INIT_INFO *pInitInfo) +{ + HTC_CALLBACKS htcCallbacks; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCInit: Enter\n")); + if (HTCInitialized) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCInit: Exit\n")); + return A_OK; + } + + A_MEMCPY(&HTCInitInfo,pInitInfo,sizeof(HTC_INIT_INFO)); + + A_MEMZERO(&htcCallbacks, sizeof(HTC_CALLBACKS)); + + /* setup HIF layer callbacks */ + htcCallbacks.deviceInsertedHandler = HTCTargetInsertedHandler; + htcCallbacks.deviceRemovedHandler = HTCTargetRemovedHandler; + /* the device layer handles these */ + htcCallbacks.rwCompletionHandler = DevRWCompletionHandler; + htcCallbacks.dsrHandler = DevDsrHandler; + HIFInit(&htcCallbacks); + HTCInitialized = TRUE; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCInit: Exit\n")); + return A_OK; +} + +void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList) +{ + LOCK_HTC(target); + HTC_PACKET_ENQUEUE(pList,pPacket); + UNLOCK_HTC(target); +} + +HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList) +{ + HTC_PACKET *pPacket; + + LOCK_HTC(target); + pPacket = HTC_PACKET_DEQUEUE(pList); + UNLOCK_HTC(target); + + return pPacket; +} + +/* cleanup the HTC instance */ +static void HTCCleanup(HTC_TARGET *target) +{ + A_INT32 i; + + DevCleanup(&target->Device); + + for (i = 0;i < NUM_CONTROL_BUFFERS;i++) { + if (target->HTCControlBuffers[i].Buffer) { + A_FREE(target->HTCControlBuffers[i].Buffer); + } + } + + if (A_IS_MUTEX_VALID(&target->HTCLock)) { + A_MUTEX_DELETE(&target->HTCLock); + } + + if (A_IS_MUTEX_VALID(&target->HTCRxLock)) { + A_MUTEX_DELETE(&target->HTCRxLock); + } + + if (A_IS_MUTEX_VALID(&target->HTCTxLock)) { + A_MUTEX_DELETE(&target->HTCTxLock); + } + /* free our instance */ + A_FREE(target); +} + +/* registered target arrival callback from the HIF layer */ +static A_STATUS HTCTargetInsertedHandler(void *hif_handle) +{ + HTC_TARGET *target = NULL; + A_STATUS status; + int i; + A_UINT32 ctrl_bufsz; + A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX]; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcTargetInserted - Enter\n")); + + do { + + /* allocate target memory */ + if ((target = (HTC_TARGET *)A_MALLOC(sizeof(HTC_TARGET))) == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n")); + status = A_ERROR; + break; + } + + A_MEMZERO(target, sizeof(HTC_TARGET)); + A_MUTEX_INIT(&target->HTCLock); + A_MUTEX_INIT(&target->HTCRxLock); + A_MUTEX_INIT(&target->HTCTxLock); + INIT_HTC_PACKET_QUEUE(&target->ControlBufferTXFreeList); + INIT_HTC_PACKET_QUEUE(&target->ControlBufferRXFreeList); + + /* give device layer the hif device handle */ + target->Device.HIFDevice = hif_handle; + /* give the device layer our context (for event processing) + * the device layer will register it's own context with HIF + * so we need to set this so we can fetch it in the target remove handler */ + target->Device.HTCContext = target; + /* set device layer target failure callback */ + target->Device.TargetFailureCallback = HTCReportFailure; + /* set device layer recv message pending callback */ + target->Device.MessagePendingCallback = HTCRecvMessagePendingHandler; + target->EpWaitingForBuffers = ENDPOINT_MAX; + + /* setup device layer */ + status = DevSetup(&target->Device); + + if (A_FAILED(status)) { + break; + } + + + /* get the block sizes */ + status = HIFConfigureDevice(hif_handle, HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + blocksizes, sizeof(blocksizes)); + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get block size info from HIF layer...\n")); + break; + } + + /* Set the control buffer size based on the block size */ + if (blocksizes[1] > HTC_MAX_CONTROL_MESSAGE_LENGTH) { + ctrl_bufsz = blocksizes[1] + HTC_HDR_LENGTH; + } else { + ctrl_bufsz = HTC_MAX_CONTROL_MESSAGE_LENGTH + HTC_HDR_LENGTH; + } + for (i = 0;i < NUM_CONTROL_BUFFERS;i++) { + target->HTCControlBuffers[i].Buffer = A_MALLOC(ctrl_bufsz); + if (target->HTCControlBuffers[i].Buffer == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n")); + status = A_ERROR; + break; + } + } + + if (A_FAILED(status)) { + break; + } + + /* carve up buffers/packets for control messages */ + for (i = 0; i < NUM_CONTROL_RX_BUFFERS; i++) { + HTC_PACKET *pControlPacket; + pControlPacket = &target->HTCControlBuffers[i].HtcPacket; + SET_HTC_PACKET_INFO_RX_REFILL(pControlPacket, + target, + target->HTCControlBuffers[i].Buffer, + ctrl_bufsz, + ENDPOINT_0); + HTC_FREE_CONTROL_RX(target,pControlPacket); + } + + for (;i < NUM_CONTROL_BUFFERS;i++) { + HTC_PACKET *pControlPacket; + pControlPacket = &target->HTCControlBuffers[i].HtcPacket; + INIT_HTC_PACKET_INFO(pControlPacket, + target->HTCControlBuffers[i].Buffer, + ctrl_bufsz); + HTC_FREE_CONTROL_TX(target,pControlPacket); + } + + } while (FALSE); + + if (A_SUCCESS(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" calling AddInstance callback \n")); + /* announce ourselves */ + HTCInitInfo.AddInstance((HTC_HANDLE)target); + } else { + if (target != NULL) { + HTCCleanup(target); + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcTargetInserted - Exit\n")); + + return status; +} + +/* registered removal callback from the HIF layer */ +static A_STATUS HTCTargetRemovedHandler(void *handle, A_STATUS status) +{ + HTC_TARGET *target; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCTargetRemovedHandler handle:0x%X \n",(A_UINT32)handle)); + + if (NULL == handle) { + /* this could be NULL in the event that target initialization failed */ + return A_OK; + } + + target = ((AR6K_DEVICE *)handle)->HTCContext; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" removing target:0x%X instance:0x%X ... \n", + (A_UINT32)target, (A_UINT32)target->pInstanceContext)); + + if (target->pInstanceContext != NULL) { + /* let upper layer know, it needs to call HTCStop() */ + HTCInitInfo.DeleteInstance(target->pInstanceContext); + } + + HIFShutDownDevice(target->Device.HIFDevice); + + HTCCleanup(target); + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCTargetRemovedHandler \n")); + return A_OK; +} + +/* get the low level HIF device for the caller , the caller may wish to do low level + * HIF requests */ +void *HTCGetHifDevice(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + return target->Device.HIFDevice; +} + +/* set the instance block for this HTC handle, so that on removal, the blob can be + * returned to the caller */ +void HTCSetInstance(HTC_HANDLE HTCHandle, void *Instance) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + + target->pInstanceContext = Instance; +} + +/* wait for the target to arrive (sends HTC Ready message) + * this operation is fully synchronous and the message is polled for */ +A_STATUS HTCWaitTarget(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_STATUS status; + HTC_PACKET *pPacket = NULL; + HTC_READY_MSG *pRdyMsg; + HTC_SERVICE_CONNECT_REQ connect; + HTC_SERVICE_CONNECT_RESP resp; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Enter (target:0x%X) \n", (A_UINT32)target)); + + do { + +#ifdef MBOXHW_UNIT_TEST + + status = DoMboxHWTest(&target->Device); + + if (status != A_OK) { + break; + } + +#endif + + /* we should be getting 1 control message that the target is ready */ + status = HTCWaitforControlMessage(target, &pPacket); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Target Not Available!!\n")); + break; + } + + /* we controlled the buffer creation so it has to be properly aligned */ + pRdyMsg = (HTC_READY_MSG *)pPacket->pBuffer; + + if ((pRdyMsg->MessageID != HTC_MSG_READY_ID) || + (pPacket->ActualLength < sizeof(HTC_READY_MSG))) { + /* this message is not valid */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + if (pRdyMsg->CreditCount == 0 || pRdyMsg->CreditSize == 0) { + /* this message is not valid */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + target->TargetCredits = pRdyMsg->CreditCount; + target->TargetCreditSize = pRdyMsg->CreditSize; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" Target Ready: credits: %d credit size: %d\n", + target->TargetCredits, target->TargetCreditSize)); + + /* setup our pseudo HTC control endpoint connection */ + A_MEMZERO(&connect,sizeof(connect)); + A_MEMZERO(&resp,sizeof(resp)); + connect.EpCallbacks.pContext = target; + connect.EpCallbacks.EpTxComplete = HTCControlTxComplete; + connect.EpCallbacks.EpRecv = HTCControlRecv; + connect.EpCallbacks.EpRecvRefill = NULL; /* not needed */ + connect.EpCallbacks.EpSendFull = NULL; /* not nedded */ + connect.MaxSendQueueDepth = NUM_CONTROL_BUFFERS; + connect.ServiceID = HTC_CTRL_RSVD_SVC; + + /* connect fake service */ + status = HTCConnectService((HTC_HANDLE)target, + &connect, + &resp); + + if (!A_FAILED(status)) { + break; + } + + } while (FALSE); + + if (pPacket != NULL) { + HTC_FREE_CONTROL_RX(target,pPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Exit\n")); + + return status; +} + + + +/* Start HTC, enable interrupts and let the target know host has finished setup */ +A_STATUS HTCStart(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_PACKET *pPacket; + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Enter\n")); + + /* make sure interrupts are disabled at the chip level, + * this function can be called again from a reboot of the target without shutting down HTC */ + DevDisableInterrupts(&target->Device); + /* make sure state is cleared again */ + target->HTCStateFlags = 0; + + /* now that we are starting, push control receive buffers into the + * HTC control endpoint */ + + while (1) { + pPacket = HTC_ALLOC_CONTROL_RX(target); + if (NULL == pPacket) { + break; + } + HTCAddReceivePkt((HTC_HANDLE)target,pPacket); + } + + do { + + AR_DEBUG_ASSERT(target->InitCredits != NULL); + AR_DEBUG_ASSERT(target->EpCreditDistributionListHead != NULL); + AR_DEBUG_ASSERT(target->EpCreditDistributionListHead->pNext != NULL); + + /* call init credits callback to do the distribution , + * NOTE: the first entry in the distribution list is ENDPOINT_0, so + * we pass the start of the list after this one. */ + target->InitCredits(target->pCredDistContext, + target->EpCreditDistributionListHead->pNext, + target->TargetCredits); + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_TRC)) { + DumpCreditDistStates(target); + } + + /* the caller is done connecting to services, so we can indicate to the + * target that the setup phase is complete */ + status = HTCSendSetupComplete(target); + + if (A_FAILED(status)) { + break; + } + + /* unmask interrupts */ + status = DevUnmaskInterrupts(&target->Device); + + if (A_FAILED(status)) { + HTCStop(target); + } + + } while (FALSE); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Exit\n")); + return status; +} + +static void ResetEndpointStates(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + int i; + + for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) { + pEndpoint = &target->EndPoint[i]; + + A_MEMZERO(&pEndpoint->CreditDist, sizeof(pEndpoint->CreditDist)); + pEndpoint->ServiceID = 0; + pEndpoint->CurrentTxQueueDepth = 0; + pEndpoint->MaxMsgLength = 0; + pEndpoint->MaxTxQueueDepth = 0; +#ifdef HTC_EP_STAT_PROFILING + A_MEMZERO(&pEndpoint->EndPointStats,sizeof(pEndpoint->EndPointStats)); +#endif + INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBuffers); + INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue); + } + /* reset distribution list */ + target->EpCreditDistributionListHead = NULL; +} + +/* stop HTC communications, i.e. stop interrupt reception, and flush all queued buffers */ +void HTCStop(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCStop \n")); + + /* mark that we are shutting down .. */ + target->HTCStateFlags |= HTC_STATE_STOPPING; + + /* Masking interrupts is a synchronous operation, when this function returns + * all pending HIF I/O has completed, we can safely flush the queues */ + DevMaskInterrupts(&target->Device); + + /* flush all send packets */ + HTCFlushSendPkts(target); + /* flush all recv buffers */ + HTCFlushRecvBuffers(target); + + ResetEndpointStates(target); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCStop \n")); +} + +/* undo what was done in HTCInit() */ +void HTCShutDown(void) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCShutDown: \n")); + HTCInitialized = FALSE; + /* undo HTCInit */ + HIFShutDownDevice(NULL); + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCShutDown: \n")); +} + +void HTCDumpCreditStates(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + + LOCK_HTC_TX(target); + + DumpCreditDistStates(target); + + UNLOCK_HTC_TX(target); +} + +/* report a target failure from the device, this is a callback from the device layer + * which uses a mechanism to report errors from the target (i.e. special interrupts) */ +static void HTCReportFailure(void *Context) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + + target->TargetFailure = TRUE; + + if ((target->pInstanceContext != NULL) && (HTCInitInfo.TargetFailure != NULL)) { + /* let upper layer know, it needs to call HTCStop() */ + HTCInitInfo.TargetFailure(target->pInstanceContext, A_ERROR); + } +} + +void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription) +{ + A_CHAR stream[60]; + A_UINT32 i; + A_UINT16 offset, count; + + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("<---------Dumping %d Bytes : %s ------>\n", length, pDescription)); + + count = 0; + offset = 0; + for(i = 0; i < length; i++) { + A_SPRINTF(stream + offset, "%2.2X ", buffer[i]); + count ++; + offset += 3; + + if(count == 16) { + count = 0; + offset = 0; + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("[H]: %s\n", stream)); + A_MEMZERO(stream, 60); + } + } + + if(offset != 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("[H]: %s\n", stream)); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("<------------------------------------------------->\n")); +} + +A_BOOL HTCGetEndpointStatistics(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + HTC_ENDPOINT_STAT_ACTION Action, + HTC_ENDPOINT_STATS *pStats) +{ + +#ifdef HTC_EP_STAT_PROFILING + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_BOOL clearStats = FALSE; + A_BOOL sample = FALSE; + + switch (Action) { + case HTC_EP_STAT_SAMPLE : + sample = TRUE; + break; + case HTC_EP_STAT_SAMPLE_AND_CLEAR : + sample = TRUE; + clearStats = TRUE; + break; + case HTC_EP_STAT_CLEAR : + clearStats = TRUE; + break; + default: + break; + } + + A_ASSERT(Endpoint < ENDPOINT_MAX); + + /* lock out TX and RX while we sample and/or clear */ + LOCK_HTC_TX(target); + LOCK_HTC_RX(target); + + if (sample) { + A_ASSERT(pStats != NULL); + /* return the stats to the caller */ + A_MEMCPY(pStats, &target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS)); + } + + if (clearStats) { + /* reset stats */ + A_MEMZERO(&target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS)); + } + + UNLOCK_HTC_RX(target); + UNLOCK_HTC_TX(target); + + return TRUE; +#else + return FALSE; +#endif +} diff -urN linux-2.6.26/drivers/net/wireless/ar6000/htc_recv.c linux-2.6.26-lab126/drivers/net/wireless/ar6000/htc_recv.c --- linux-2.6.26/drivers/net/wireless/ar6000/htc_recv.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/htc_recv.c 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,766 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + +#define HTCIssueRecv(t, p) \ + DevRecvPacket(&(t)->Device, \ + (p), \ + (p)->ActualLength) + +#define DO_RCV_COMPLETION(t,p,e) \ +{ \ + if ((p)->ActualLength > 0) { \ + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" completing packet 0x%X (%d bytes) on ep : %d \n", \ + (A_UINT32)(p), (p)->ActualLength, (p)->Endpoint)); \ + (e)->EpCallBacks.EpRecv((e)->EpCallBacks.pContext, \ + (p)); \ + } else { \ + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" recycling empty packet \n")); \ + HTC_RECYCLE_RX_PKT((t), (p), (e)); \ + } \ +} + +#ifdef HTC_EP_STAT_PROFILING +#define HTC_RX_STAT_PROFILE(t,ep,lookAhead) \ +{ \ + LOCK_HTC_RX((t)); \ + INC_HTC_EP_STAT((ep), RxReceived, 1); \ + if ((lookAhead) != 0) { \ + INC_HTC_EP_STAT((ep), RxLookAheads, 1); \ + } \ + UNLOCK_HTC_RX((t)); \ +} +#else +#define HTC_RX_STAT_PROFILE(t,ep,lookAhead) +#endif + +static INLINE A_STATUS HTCProcessTrailer(HTC_TARGET *target, + A_UINT8 *pBuffer, + int Length, + A_UINT32 *pNextLookAhead, + HTC_ENDPOINT_ID FromEndpoint) +{ + HTC_RECORD_HDR *pRecord; + A_UINT8 *pRecordBuf; + HTC_LOOKAHEAD_REPORT *pLookAhead; + A_UINT8 *pOrigBuffer; + int origLength; + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessTrailer (length:%d) \n", Length)); + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + AR_DEBUG_PRINTBUF(pBuffer,Length,"Recv Trailer"); + } + + pOrigBuffer = pBuffer; + origLength = Length; + status = A_OK; + + while (Length > 0) { + + if (Length < sizeof(HTC_RECORD_HDR)) { + status = A_EPROTO; + break; + } + /* these are byte aligned structs */ + pRecord = (HTC_RECORD_HDR *)pBuffer; + Length -= sizeof(HTC_RECORD_HDR); + pBuffer += sizeof(HTC_RECORD_HDR); + + if (pRecord->Length > Length) { + /* no room left in buffer for record */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" invalid record length: %d (id:%d) buffer has: %d bytes left \n", + pRecord->Length, pRecord->RecordID, Length)); + status = A_EPROTO; + break; + } + /* start of record follows the header */ + pRecordBuf = pBuffer; + + switch (pRecord->RecordID) { + case HTC_RECORD_CREDITS: + AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_CREDIT_REPORT)); + HTCProcessCreditRpt(target, + (HTC_CREDIT_REPORT *)pRecordBuf, + pRecord->Length / (sizeof(HTC_CREDIT_REPORT)), + FromEndpoint); + break; + case HTC_RECORD_LOOKAHEAD: + AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_LOOKAHEAD_REPORT)); + pLookAhead = (HTC_LOOKAHEAD_REPORT *)pRecordBuf; + if ((pLookAhead->PreValid == ((~pLookAhead->PostValid) & 0xFF)) && + (pNextLookAhead != NULL)) { + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + (" LookAhead Report Found (pre valid:0x%X, post valid:0x%X) \n", + pLookAhead->PreValid, + pLookAhead->PostValid)); + + /* look ahead bytes are valid, copy them over */ + ((A_UINT8 *)pNextLookAhead)[0] = pLookAhead->LookAhead[0]; + ((A_UINT8 *)pNextLookAhead)[1] = pLookAhead->LookAhead[1]; + ((A_UINT8 *)pNextLookAhead)[2] = pLookAhead->LookAhead[2]; + ((A_UINT8 *)pNextLookAhead)[3] = pLookAhead->LookAhead[3]; + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + DebugDumpBytes((A_UINT8 *)pNextLookAhead,4,"Next Look Ahead"); + } + } + break; + default: + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" unhandled record: id:%d length:%d \n", + pRecord->RecordID, pRecord->Length)); + break; + } + + if (A_FAILED(status)) { + break; + } + + /* advance buffer past this record for next time around */ + pBuffer += pRecord->Length; + Length -= pRecord->Length; + } + + if (A_FAILED(status)) { + DebugDumpBytes(pOrigBuffer,origLength,"BAD Recv Trailer"); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessTrailer \n")); + return status; + +} + +/* process a received message (i.e. strip off header, process any trailer data) + * note : locks must be released when this function is called */ +static A_STATUS HTCProcessRecvHeader(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT32 *pNextLookAhead) +{ + A_UINT8 temp; + A_UINT8 *pBuf; + A_STATUS status = A_OK; + A_UINT16 payloadLen; + A_UINT32 lookAhead; + + pBuf = pPacket->pBuffer; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessRecvHeader \n")); + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + AR_DEBUG_PRINTBUF(pBuf,pPacket->ActualLength,"HTC Recv PKT"); + } + + do { + /* note, we cannot assume the alignment of pBuffer, so we use the safe macros to + * retrieve 16 bit fields */ + payloadLen = A_GET_UINT16_FIELD(pBuf, HTC_FRAME_HDR, PayloadLen); + + ((A_UINT8 *)&lookAhead)[0] = pBuf[0]; + ((A_UINT8 *)&lookAhead)[1] = pBuf[1]; + ((A_UINT8 *)&lookAhead)[2] = pBuf[2]; + ((A_UINT8 *)&lookAhead)[3] = pBuf[3]; + + if (lookAhead != pPacket->HTCReserved) { + /* somehow the lookahead that gave us the full read length did not + * reflect the actual header in the pending message */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCProcessRecvHeader, lookahead mismatch! \n")); + DebugDumpBytes((A_UINT8 *)&pPacket->HTCReserved,4,"Expected Message LookAhead"); + DebugDumpBytes(pBuf,sizeof(HTC_FRAME_HDR),"Current Frame Header"); +#ifdef HTC_CAPTURE_LAST_FRAME + DebugDumpBytes((A_UINT8 *)&target->LastFrameHdr,sizeof(HTC_FRAME_HDR),"Last Frame Header"); + if (target->LastTrailerLength != 0) { + DebugDumpBytes(target->LastTrailer, + target->LastTrailerLength, + "Last trailer"); + } +#endif + status = A_EPROTO; + break; + } + + /* get flags */ + temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, Flags); + + if (temp & HTC_FLAGS_RECV_TRAILER) { + /* this packet has a trailer */ + + /* extract the trailer length in control byte 0 */ + temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, ControlBytes[0]); + + if ((temp < sizeof(HTC_RECORD_HDR)) || (temp > payloadLen)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCProcessRecvHeader, invalid header (payloadlength should be :%d, CB[0] is:%d) \n", + payloadLen, temp)); + status = A_EPROTO; + break; + } + + /* process trailer data that follows HDR + application payload */ + status = HTCProcessTrailer(target, + (pBuf + HTC_HDR_LENGTH + payloadLen - temp), + temp, + pNextLookAhead, + pPacket->Endpoint); + + if (A_FAILED(status)) { + break; + } + +#ifdef HTC_CAPTURE_LAST_FRAME + A_MEMCPY(target->LastTrailer, (pBuf + HTC_HDR_LENGTH + payloadLen - temp), temp); + target->LastTrailerLength = temp; +#endif + /* trim length by trailer bytes */ + pPacket->ActualLength -= temp; + } +#ifdef HTC_CAPTURE_LAST_FRAME + else { + target->LastTrailerLength = 0; + } +#endif + + /* if we get to this point, the packet is good */ + /* remove header and adjust length */ + pPacket->pBuffer += HTC_HDR_LENGTH; + pPacket->ActualLength -= HTC_HDR_LENGTH; + + } while (FALSE); + + if (A_FAILED(status)) { + /* dump the whole packet */ + DebugDumpBytes(pBuf,pPacket->ActualLength,"BAD HTC Recv PKT"); + } else { +#ifdef HTC_CAPTURE_LAST_FRAME + A_MEMCPY(&target->LastFrameHdr,pBuf,sizeof(HTC_FRAME_HDR)); +#endif + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + if (pPacket->ActualLength > 0) { + AR_DEBUG_PRINTBUF(pPacket->pBuffer,pPacket->ActualLength,"HTC - Application Msg"); + } + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessRecvHeader \n")); + return status; +} + +/* asynchronous completion handler for recv packet fetching, when the device layer + * completes a read request, it will call this completion handler */ +void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + HTC_ENDPOINT *pEndpoint; + A_UINT32 nextLookAhead = 0; + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCRecvCompleteHandler (status:%d, ep:%d) \n", + pPacket->Status, pPacket->Endpoint)); + + AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX); + pEndpoint = &target->EndPoint[pPacket->Endpoint]; + pPacket->Completion = NULL; + + /* get completion status */ + status = pPacket->Status; + + do { + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HTCRecvCompleteHandler: request failed (status:%d, ep:%d) \n", + pPacket->Status, pPacket->Endpoint)); + break; + } + /* process the header for any trailer data */ + status = HTCProcessRecvHeader(target,pPacket,&nextLookAhead); + + if (A_FAILED(status)) { + break; + } + /* was there a lookahead for the next packet? */ + if (nextLookAhead != 0) { + A_STATUS nextStatus; + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("HTCRecvCompleteHandler - next look ahead was non-zero : 0x%X \n", + nextLookAhead)); + /* we have another packet, get the next packet fetch started (pipelined) before + * we call into the endpoint's callback, this will start another async request */ + nextStatus = HTCRecvMessagePendingHandler(target,nextLookAhead,NULL); + if (A_EPROTO == nextStatus) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Next look ahead from recv header was INVALID\n")); + DebugDumpBytes((A_UINT8 *)&nextLookAhead, + 4, + "BAD lookahead from lookahead report"); + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("HTCRecvCompleteHandler - rechecking for more messages...\n")); + /* if we did not get anything on the look-ahead, + * call device layer to asynchronously re-check for messages. If we can keep the async + * processing going we get better performance. If there is a pending message we will keep processing + * messages asynchronously which should pipeline things nicely */ + DevCheckPendingRecvMsgsAsync(&target->Device); + } + + HTC_RX_STAT_PROFILE(target,pEndpoint,nextLookAhead); + DO_RCV_COMPLETION(target,pPacket,pEndpoint); + + } while (FALSE); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCRecvCompleteHandler , message fetch failed (status = %d) \n", + status)); + /* recyle this packet */ + HTC_RECYCLE_RX_PKT(target, pPacket, pEndpoint); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCRecvCompleteHandler\n")); +} + +/* synchronously wait for a control message from the target, + * This function is used at initialization time ONLY. At init messages + * on ENDPOINT 0 are expected. */ +A_STATUS HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket) +{ + A_STATUS status; + A_UINT32 lookAhead; + HTC_PACKET *pPacket = NULL; + HTC_FRAME_HDR *pHdr; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCWaitforControlMessage \n")); + + do { + + *ppControlPacket = NULL; + + /* call the polling function to see if we have a message */ + status = DevPollMboxMsgRecv(&target->Device, + &lookAhead, + HTC_TARGET_RESPONSE_TIMEOUT); + + if (A_FAILED(status)) { + break; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("HTCWaitforControlMessage : lookAhead : 0x%X \n", lookAhead)); + + /* check the lookahead */ + pHdr = (HTC_FRAME_HDR *)&lookAhead; + + if (pHdr->EndpointID != ENDPOINT_0) { + /* unexpected endpoint number, should be zero */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + if (A_FAILED(status)) { + /* bad message */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + pPacket = HTC_ALLOC_CONTROL_RX(target); + + if (pPacket == NULL) { + AR_DEBUG_ASSERT(FALSE); + status = A_NO_MEMORY; + break; + } + + pPacket->HTCReserved = lookAhead; + pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH; + + if (pPacket->ActualLength > pPacket->BufferLength) { + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + /* we want synchronous operation */ + pPacket->Completion = NULL; + + /* get the message from the device, this will block */ + status = HTCIssueRecv(target, pPacket); + + if (A_FAILED(status)) { + break; + } + + /* process receive header */ + status = HTCProcessRecvHeader(target,pPacket,NULL); + + pPacket->Status = status; + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCWaitforControlMessage, HTCProcessRecvHeader failed (status = %d) \n", + status)); + break; + } + + /* give the caller this control message packet, they are responsible to free */ + *ppControlPacket = pPacket; + + } while (FALSE); + + if (A_FAILED(status)) { + if (pPacket != NULL) { + /* cleanup buffer on error */ + HTC_FREE_CONTROL_RX(target,pPacket); + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCWaitforControlMessage \n")); + + return status; +} + +/* callback when device layer or lookahead report parsing detects a pending message */ +A_STATUS HTCRecvMessagePendingHandler(void *Context, A_UINT32 LookAhead, A_BOOL *pAsyncProc) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + A_STATUS status = A_OK; + HTC_PACKET *pPacket = NULL; + HTC_FRAME_HDR *pHdr = NULL; + HTC_ENDPOINT *pEndpoint = NULL; + A_BOOL asyncProc = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCRecvMessagePendingHandler LookAhead:0x%X \n",LookAhead)); + + if (IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(&target->Device)) { + /* We use async mode to get the packets if the device layer supports it. + * The device layer interfaces with HIF in which HIF may have restrictions on + * how interrupts are processed */ + asyncProc = TRUE; + } + + if (pAsyncProc != NULL) { + /* indicate to caller how we decided to process this */ + *pAsyncProc = asyncProc; + } + + while (TRUE) { + pHdr = (HTC_FRAME_HDR *)&LookAhead; + + if (pHdr->EndpointID >= ENDPOINT_MAX) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Endpoint in look-ahead: %d \n",pHdr->EndpointID)); + /* invalid endpoint */ + status = A_EPROTO; + break; + } + + if (pHdr->PayloadLen > HTC_MAX_PAYLOAD_LENGTH) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Payload length %d exceeds max HTC : %d !\n", + pHdr->PayloadLen, HTC_MAX_PAYLOAD_LENGTH)); + status = A_EPROTO; + break; + } + + pEndpoint = &target->EndPoint[pHdr->EndpointID]; + + if (0 == pEndpoint->ServiceID) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Endpoint %d is not connected !\n",pHdr->EndpointID)); + /* endpoint isn't even connected */ + status = A_EPROTO; + break; + } + + if (pEndpoint->EpCallBacks.EpRecvAlloc != NULL) { + /* user is using a per-packet allocation callback */ + pPacket = pEndpoint->EpCallBacks.EpRecvAlloc(pEndpoint->EpCallBacks.pContext, + (HTC_ENDPOINT_ID) pHdr->EndpointID, + pHdr->PayloadLen + sizeof(HTC_FRAME_HDR)); + + /* lock RX, in case this allocation fails, we need to update internal state below */ + + LOCK_HTC_RX(target); + + } else { + /* user is using a refill handler that can refill multiple HTC buffers */ + /* lock RX to get a buffer */ + LOCK_HTC_RX(target); + + /* get a packet from the endpoint recv queue */ + pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers); + + if (NULL == pPacket) { + /* check for refill handler */ + if (pEndpoint->EpCallBacks.EpRecvRefill != NULL) { + UNLOCK_HTC_RX(target); + /* call the re-fill handler */ + pEndpoint->EpCallBacks.EpRecvRefill(pEndpoint->EpCallBacks.pContext, + (HTC_ENDPOINT_ID) pHdr->EndpointID); + LOCK_HTC_RX(target); + /* check if we have more buffers */ + pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers); + /* fall through */ + } + } + } + + if (NULL == pPacket) { + /* this is not an error, we simply need to mark that we are waiting for buffers.*/ + target->HTCStateFlags |= HTC_STATE_WAIT_BUFFERS; + target->EpWaitingForBuffers = (HTC_ENDPOINT_ID) pHdr->EndpointID; + status = A_NO_MEMORY; + } + + if (HTC_STOPPING(target)) { + status = A_ECANCELED; + } + + UNLOCK_HTC_RX(target); + + if (A_FAILED(status)) { + /* no buffers or stopping */ + break; + } + + AR_DEBUG_ASSERT(pPacket->Endpoint == pHdr->EndpointID); + + /* make sure this message can fit in the endpoint buffer */ + if ((pHdr->PayloadLen + HTC_HDR_LENGTH) > pPacket->BufferLength) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Payload Length Error : header reports payload of: %d, endpoint buffer size: %d \n", + pHdr->PayloadLen, pPacket->BufferLength)); + status = A_EPROTO; + break; + } + + pPacket->HTCReserved = LookAhead; /* set expected look ahead */ + /* set the amount of data to fetch */ + pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH; + + if (asyncProc) { + /* we use async mode to get the packet if the device layer supports it + * set our callback and context */ + pPacket->Completion = HTCRecvCompleteHandler; + pPacket->pContext = target; + } else { + /* fully synchronous */ + pPacket->Completion = NULL; + } + + /* go fetch the packet */ + status = HTCIssueRecv(target, pPacket); + + if (A_FAILED(status)) { + break; + } + + if (asyncProc) { + /* we did this asynchronously so we can get out of the loop, the asynch processing + * creates a chain of requests to continue processing pending messages in the + * context of callbacks */ + break; + } + + /* in the sync case, we process the packet, check lookaheads and then repeat */ + + LookAhead = 0; + status = HTCProcessRecvHeader(target,pPacket,&LookAhead); + + if (A_FAILED(status)) { + break; + } + + HTC_RX_STAT_PROFILE(target,pEndpoint,LookAhead); + DO_RCV_COMPLETION(target,pPacket,pEndpoint); + + pPacket = NULL; + + if (0 == LookAhead) { + break; + } + + /* check whether other OS contexts have queued any WMI command/data for WLAN. + * This check is needed only if WLAN Tx and Rx happens in same thread context */ + A_CHECK_DRV_TX(); + } + + if (A_NO_MEMORY == status) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" Endpoint :%d has no buffers, blocking receiver to prevent overrun.. \n", + (pHdr != NULL) ? pHdr->EndpointID : 0xFFFF)); + /* try to stop receive at the device layer */ + DevStopRecv(&target->Device, asyncProc ? DEV_STOP_RECV_ASYNC : DEV_STOP_RECV_SYNC); + status = A_OK; + } else if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Failed to get pending message : LookAhead Value: 0x%X (status = %d) \n", + LookAhead, status)); + if (pPacket != NULL) { + /* clean up packet on error */ + HTC_RECYCLE_RX_PKT(target, pPacket, pEndpoint); + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCRecvMessagePendingHandler \n")); + + return status; +} + +/* Makes a buffer available to the HTC module */ +A_STATUS HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint; + A_BOOL unblockRecv = FALSE; + A_STATUS status = A_OK; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("+- HTCAddReceivePkt: endPointId: %d, buffer: 0x%X, length: %d\n", + pPacket->Endpoint, (A_UINT32)pPacket->pBuffer, pPacket->BufferLength)); + + do { + AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX); + + pEndpoint = &target->EndPoint[pPacket->Endpoint]; + + LOCK_HTC_RX(target); + + if (HTC_STOPPING(target)) { + pPacket->Status = A_ECANCELED; + status = A_ECANCELED; + UNLOCK_HTC_RX(target); + pEndpoint->EpCallBacks.EpRecv(pEndpoint->EpCallBacks.pContext, pPacket); + break; + } + + /* store receive packet */ + HTC_PACKET_ENQUEUE(&pEndpoint->RxBuffers, pPacket); + + /* check if we are blocked waiting for a new buffer */ + if (target->HTCStateFlags & HTC_STATE_WAIT_BUFFERS) { + if (target->EpWaitingForBuffers == pPacket->Endpoint) { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" receiver was blocked on ep:%d, unblocking.. \n", + target->EpWaitingForBuffers)); + target->HTCStateFlags &= ~HTC_STATE_WAIT_BUFFERS; + target->EpWaitingForBuffers = ENDPOINT_MAX; + unblockRecv = TRUE; + } + } + + UNLOCK_HTC_RX(target); + + if (unblockRecv && !HTC_STOPPING(target)) { + /* TODO : implement a buffer threshold count? */ + DevEnableRecv(&target->Device,DEV_ENABLE_RECV_SYNC); + } + + } while (FALSE); + + return status; +} + +void HTCUnblockRecv(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_BOOL unblockRecv = FALSE; + + LOCK_HTC_RX(target); + + /* check if we are blocked waiting for a new buffer */ + if (target->HTCStateFlags & HTC_STATE_WAIT_BUFFERS) { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HTCUnblockRx : receiver was blocked on ep:%d, unblocking.. \n", + target->EpWaitingForBuffers)); + target->HTCStateFlags &= ~HTC_STATE_WAIT_BUFFERS; + target->EpWaitingForBuffers = ENDPOINT_MAX; + unblockRecv = TRUE; + } + + UNLOCK_HTC_RX(target); + + if (unblockRecv && !HTC_STOPPING(target)) { + /* re-enable */ + DevEnableRecv(&target->Device,DEV_ENABLE_RECV_ASYNC); + } +} + +static void HTCFlushEndpointRX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint) +{ + HTC_PACKET *pPacket; + + LOCK_HTC_RX(target); + + while (1) { + pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers); + if (NULL == pPacket) { + break; + } + UNLOCK_HTC_RX(target); + pPacket->Status = A_ECANCELED; + pPacket->ActualLength = 0; + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" Flushing RX packet:0x%X, length:%d, ep:%d \n", + (A_UINT32)pPacket, pPacket->BufferLength, pPacket->Endpoint)); + /* give the packet back */ + pEndpoint->EpCallBacks.EpRecv(pEndpoint->EpCallBacks.pContext, + pPacket); + LOCK_HTC_RX(target); + } + + UNLOCK_HTC_RX(target); + + +} + +void HTCFlushRecvBuffers(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + int i; + + for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) { + pEndpoint = &target->EndPoint[i]; + if (pEndpoint->ServiceID == 0) { + /* not in use.. */ + continue; + } + HTCFlushEndpointRX(target,pEndpoint); + } +} + + +void HTCEnableRecv(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + + if (!HTC_STOPPING(target)) { + /* re-enable */ + DevEnableRecv(&target->Device,DEV_ENABLE_RECV_SYNC); + } +} + +void HTCDisableRecv(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + + if (!HTC_STOPPING(target)) { + /* disable */ + DevStopRecv(&target->Device,DEV_ENABLE_RECV_SYNC); + } +} diff -urN linux-2.6.26/drivers/net/wireless/ar6000/htc_send.c linux-2.6.26-lab126/drivers/net/wireless/ar6000/htc_send.c --- linux-2.6.26/drivers/net/wireless/ar6000/htc_send.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/htc_send.c 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,593 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + +typedef enum _HTC_SEND_QUEUE_RESULT { + HTC_SEND_QUEUE_OK = 0, /* packet was queued */ + HTC_SEND_QUEUE_DROP = 1, /* this packet should be dropped */ +} HTC_SEND_QUEUE_RESULT; + +#define DO_EP_TX_COMPLETION(ep,p) \ +{ \ + (p)->Completion = NULL; \ + (ep)->EpCallBacks.EpTxComplete((ep)->EpCallBacks.pContext,(p)); \ +} + + +/* call the distribute credits callback with the distribution */ +#define DO_DISTRIBUTION(t,reason,description,pList) \ +{ \ + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, \ + (" calling distribute function (%s) (dfn:0x%X, ctxt:0x%X, dist:0x%X) \n", \ + (description), \ + (A_UINT32)(t)->DistributeCredits, \ + (A_UINT32)(t)->pCredDistContext, \ + (A_UINT32)pList)); \ + (t)->DistributeCredits((t)->pCredDistContext, \ + (pList), \ + (reason)); \ +} + +/* our internal send packet completion handler when packets are submited to the AR6K device + * layer */ +static void HTCSendPktCompletionHandler(void *Context, HTC_PACKET *pPacket) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + HTC_ENDPOINT *pEndpoint = &target->EndPoint[pPacket->Endpoint]; + + + if (A_FAILED(pPacket->Status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCSendPktCompletionHandler: request failed (status:%d, ep:%d) \n", + pPacket->Status, pPacket->Endpoint)); + } + /* first, fixup the head room we allocated */ + pPacket->pBuffer += HTC_HDR_LENGTH; + /* do completion */ + DO_EP_TX_COMPLETION(pEndpoint,pPacket); +} + +A_STATUS HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT8 SendFlags) +{ + A_STATUS status; + A_UINT8 *pHdrBuf; + A_BOOL sync = FALSE; + + /* caller always provides headrooom */ + pPacket->pBuffer -= HTC_HDR_LENGTH; + pHdrBuf = pPacket->pBuffer; + /* setup frame header */ + A_SET_UINT16_FIELD(pHdrBuf,HTC_FRAME_HDR,PayloadLen,(A_UINT16)pPacket->ActualLength); + A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,Flags,SendFlags); + A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,EndpointID, (A_UINT8)pPacket->Endpoint); + + if (pPacket->Completion == NULL) { + /* mark that this request was synchronously issued */ + sync = TRUE; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("+-HTCIssueSend: transmit length : %d (%s) \n", + pPacket->ActualLength + HTC_HDR_LENGTH, + sync ? "SYNC" : "ASYNC" )); + + /* send message to device */ + status = DevSendPacket(&target->Device, + pPacket, + pPacket->ActualLength + HTC_HDR_LENGTH); + + if (sync) { + /* use local sync variable. If this was issued asynchronously, pPacket is no longer + * safe to access. */ + pPacket->pBuffer += HTC_HDR_LENGTH; + } + + /* if this request was asynchronous, the packet completion routine will be invoked by + * the device layer when the HIF layer completes the request */ + + return status; +} + +/* try to send the current packet or a packet at the head of the TX queue, + * if there are no credits, the packet remains in the queue. + * this function returns the result of the attempt to send the HTC packet */ +static HTC_SEND_QUEUE_RESULT HTCTrySend(HTC_TARGET *target, + HTC_ENDPOINT *pEndpoint, + HTC_PACKET *pPacketToSend) +{ + HTC_PACKET *pPacket; + int creditsRequired; + int remainder; + A_UINT8 sendFlags; + HTC_SEND_QUEUE_RESULT result; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HTCTrySend (pPkt:0x%X)\n",(A_UINT32)pPacketToSend)); + + if (pPacketToSend != NULL) { + /* see if adding this packet hits the max depth */ + if ((pEndpoint->CurrentTxQueueDepth + 1) >= pEndpoint->MaxTxQueueDepth) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d, TX queue is full, Depth:%d, Max:%d \n", + pPacketToSend->Endpoint, pEndpoint->CurrentTxQueueDepth, pEndpoint->MaxTxQueueDepth)); + /* queue will be full, invoke any callbacks to determine what action to take */ + if (pEndpoint->EpCallBacks.EpSendFull != NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Calling driver's send full callback.... \n")); + if (pEndpoint->EpCallBacks.EpSendFull(pEndpoint->EpCallBacks.pContext, + pPacketToSend) == HTC_SEND_FULL_DROP) { + /* callback wants the packet dropped */ + INC_HTC_EP_STAT(pEndpoint, TxDropped, 1); + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend: \n")); + return HTC_SEND_QUEUE_DROP; + } + } + } + } + + LOCK_HTC_TX(target); + + result = HTC_SEND_QUEUE_OK; + + if (pPacketToSend != NULL) { + /* packet was supplied to be queued */ + HTC_PACKET_ENQUEUE(&pEndpoint->TxQueue,pPacketToSend); + pEndpoint->CurrentTxQueueDepth++; + } + + /* now drain the TX queue for transmission as long as we have enough + * credits */ + + while (1) { + + if (HTC_QUEUE_EMPTY(&pEndpoint->TxQueue)) { + /* nothing in the queue */ + break; + } + + if (HTC_STOPPING(target)) { + if (pPacketToSend != NULL) { + HTC_PACKET_REMOVE(pPacketToSend); + pEndpoint->CurrentTxQueueDepth--; + result = HTC_SEND_QUEUE_DROP; + } + break; + } + + sendFlags = 0; + + /* get packet at head, but don't remove it */ + pPacket = HTC_GET_PKT_AT_HEAD(&pEndpoint->TxQueue); + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Got head packet:0x%X , Queue Depth: %d\n", + (A_UINT32)pPacket, pEndpoint->CurrentTxQueueDepth)); + + /* figure out how many credits this message requires */ + creditsRequired = (pPacket->ActualLength + HTC_HDR_LENGTH) / target->TargetCreditSize; + remainder = (pPacket->ActualLength + HTC_HDR_LENGTH) % target->TargetCreditSize; + + if (remainder) { + creditsRequired++; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Creds Required:%d Got:%d\n", + creditsRequired, pEndpoint->CreditDist.TxCredits)); + + if (pEndpoint->CreditDist.TxCredits < creditsRequired) { + + /* not enough credits */ + + if (pPacket->Endpoint == ENDPOINT_0) { + /* leave it in the queue */ + break; + } + /* invoke the registered distribution function only if this is not + * endpoint 0, we let the driver layer provide more credits if it can. + * We pass the credit distribution list starting at the endpoint in question + * */ + + /* set how many credits we need */ + pEndpoint->CreditDist.TxCreditsSeek = + creditsRequired - pEndpoint->CreditDist.TxCredits; + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_SEEK_CREDITS, + "Seek Credits", + &pEndpoint->CreditDist); + pEndpoint->CreditDist.TxCreditsSeek = 0; + + if (pEndpoint->CreditDist.TxCredits < creditsRequired) { + /* still not enough credits to send, leave packet in the queue */ + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + (" Not enough credits for ep %d leaving packet in queue..\n", + pPacket->Endpoint)); + break; + } + + } + + pEndpoint->CreditDist.TxCredits -= creditsRequired; + INC_HTC_EP_STAT(pEndpoint, TxCreditsConsummed, creditsRequired); + + /* check if we need credits back from the target */ + if (pEndpoint->CreditDist.TxCredits < pEndpoint->CreditDist.TxCreditsPerMaxMsg) { + /* we are getting low on credits, see if we can ask for more from the distribution function */ + pEndpoint->CreditDist.TxCreditsSeek = + pEndpoint->CreditDist.TxCreditsPerMaxMsg - pEndpoint->CreditDist.TxCredits; + + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_SEEK_CREDITS, + "Seek Credits", + &pEndpoint->CreditDist); + + pEndpoint->CreditDist.TxCreditsSeek = 0; + /* see if we were successful in getting more */ + if (pEndpoint->CreditDist.TxCredits < pEndpoint->CreditDist.TxCreditsPerMaxMsg) { + /* tell the target we need credits ASAP! */ + sendFlags |= HTC_FLAGS_NEED_CREDIT_UPDATE; + INC_HTC_EP_STAT(pEndpoint, TxCreditLowIndications, 1); + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Host Needs Credits \n")); + } + } + + /* now we can fully dequeue */ + pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->TxQueue); + pEndpoint->CurrentTxQueueDepth--; + + INC_HTC_EP_STAT(pEndpoint, TxIssued, 1); + + UNLOCK_HTC_TX(target); + + HTCIssueSend(target, pPacket, sendFlags); + + LOCK_HTC_TX(target); + + /* go back and check for more messages */ + } + + UNLOCK_HTC_TX(target); + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend: \n")); + + return result; +} + +/* HTC API - HTCSendPkt */ +A_STATUS HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint; + HTC_ENDPOINT_ID ep; + A_STATUS status = A_OK; + HTC_SEND_QUEUE_RESULT result; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("+HTCSendPkt: Enter endPointId: %d, buffer: 0x%X, length: %d \n", + pPacket->Endpoint, (A_UINT32)pPacket->pBuffer, pPacket->ActualLength)); + + ep = pPacket->Endpoint; + AR_DEBUG_ASSERT(ep < ENDPOINT_MAX); + pEndpoint = &target->EndPoint[ep]; + + do { + + /* everything sent through this interface is asynchronous */ + /* fill in HTC completion routines */ + pPacket->Completion = HTCSendPktCompletionHandler; + pPacket->pContext = target; + + result = HTCTrySend(target, pEndpoint, pPacket); + + if (HTC_SEND_QUEUE_DROP == result) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d, TX packet dropped \n", ep)); + if (HTC_STOPPING(target)) { + status = A_ECANCELED; + } else { + status = A_NO_RESOURCE; + } + } + + } while (FALSE); + + if (A_FAILED(status)) { + pPacket->Status = status; + DO_EP_TX_COMPLETION(pEndpoint,pPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCSendPkt \n")); + + return status; +} + + +/* check TX queues to drain because of credit distribution update */ +static INLINE void HTCCheckEndpointTxQueues(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + HTC_ENDPOINT_CREDIT_DIST *pDistItem; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCCheckEndpointTxQueues \n")); + pDistItem = target->EpCreditDistributionListHead; + + /* run through the credit distribution list to see + * if there are packets queued + * NOTE: no locks need to be taken since the distribution list + * is not dynamic (cannot be re-ordered) and we are not modifying any state */ + while (pDistItem != NULL) { + pEndpoint = (HTC_ENDPOINT *)pDistItem->pHTCReserved; + + if (pEndpoint->CurrentTxQueueDepth > 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Ep %d has %d credits and %d Packets in TX Queue \n", + pDistItem->Endpoint, pEndpoint->CreditDist.TxCredits, pEndpoint->CurrentTxQueueDepth)); + /* try to start the stalled queue, this list is ordered by priority. + * Highest priority queue get's processed first, if there are credits available the + * highest priority queue will get a chance to reclaim credits from lower priority + * ones */ + HTCTrySend(target, pEndpoint, NULL); + } + + pDistItem = pDistItem->pNext; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCCheckEndpointTxQueues \n")); +} + +/* process credit reports and call distribution function */ +void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint) +{ + int i; + HTC_ENDPOINT *pEndpoint; + int totalCredits = 0; + A_BOOL doDist = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCProcessCreditRpt, Credit Report Entries:%d \n", NumEntries)); + + /* lock out TX while we update credits */ + LOCK_HTC_TX(target); + + for (i = 0; i < NumEntries; i++, pRpt++) { + if (pRpt->EndpointID >= ENDPOINT_MAX) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + pEndpoint = &target->EndPoint[pRpt->EndpointID]; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d got %d credits \n", + pRpt->EndpointID, pRpt->Credits)); + + +#ifdef HTC_EP_STAT_PROFILING + + INC_HTC_EP_STAT(pEndpoint, TxCreditRpts, 1); + INC_HTC_EP_STAT(pEndpoint, TxCreditsReturned, pRpt->Credits); + + if (FromEndpoint == pRpt->EndpointID) { + /* this credit report arrived on the same endpoint indicating it arrived in an RX + * packet */ + INC_HTC_EP_STAT(pEndpoint, TxCreditsFromRx, pRpt->Credits); + INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromRx, 1); + } else if (FromEndpoint == ENDPOINT_0) { + /* this credit arrived on endpoint 0 as a NULL message */ + INC_HTC_EP_STAT(pEndpoint, TxCreditsFromEp0, pRpt->Credits); + INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromEp0, 1); + } else { + /* arrived on another endpoint */ + INC_HTC_EP_STAT(pEndpoint, TxCreditsFromOther, pRpt->Credits); + INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromOther, 1); + } + +#endif + + if (ENDPOINT_0 == pRpt->EndpointID) { + /* always give endpoint 0 credits back */ + pEndpoint->CreditDist.TxCredits += pRpt->Credits; + } else { + /* for all other endpoints, update credits to distribute, the distribution function + * will handle giving out credits back to the endpoints */ + pEndpoint->CreditDist.TxCreditsToDist += pRpt->Credits; + /* flag that we have to do the distribution */ + doDist = TRUE; + } + + totalCredits += pRpt->Credits; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Report indicated %d credits to distribute \n", totalCredits)); + + if (doDist) { + /* this was a credit return based on a completed send operations + * note, this is done with the lock held */ + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_SEND_COMPLETE, + "Send Complete", + target->EpCreditDistributionListHead->pNext); + } + + UNLOCK_HTC_TX(target); + + if (totalCredits) { + HTCCheckEndpointTxQueues(target); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCProcessCreditRpt \n")); +} + +/* flush endpoint TX queue */ +static void HTCFlushEndpointTX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint, HTC_TX_TAG Tag) +{ + HTC_PACKET *pPacket; + HTC_PACKET_QUEUE discardQueue; + + /* initialize the discard queue */ + INIT_HTC_PACKET_QUEUE(&discardQueue); + + LOCK_HTC_TX(target); + + /* interate from the front of the TX queue and flush out packets */ + ITERATE_OVER_LIST_ALLOW_REMOVE(&pEndpoint->TxQueue, pPacket, HTC_PACKET, ListLink) { + + /* check for removal */ + if ((HTC_TX_PACKET_TAG_ALL == Tag) || (Tag == pPacket->PktInfo.AsTx.Tag)) { + /* remove from queue */ + HTC_PACKET_REMOVE(pPacket); + /* add it to the discard pile */ + HTC_PACKET_ENQUEUE(&discardQueue, pPacket); + pEndpoint->CurrentTxQueueDepth--; + } + + } ITERATE_END; + + UNLOCK_HTC_TX(target); + + /* empty the discard queue */ + while (1) { + pPacket = HTC_PACKET_DEQUEUE(&discardQueue); + if (NULL == pPacket) { + break; + } + pPacket->Status = A_ECANCELED; + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" Flushing TX packet:0x%X, length:%d, ep:%d tag:0x%X \n", + (A_UINT32)pPacket, pPacket->ActualLength, pPacket->Endpoint, pPacket->PktInfo.AsTx.Tag)); + DO_EP_TX_COMPLETION(pEndpoint,pPacket); + } + +} + +void DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("--- EP : %d ServiceID: 0x%X --------------\n", + pEPDist->Endpoint, pEPDist->ServiceID)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" this:0x%X next:0x%X prev:0x%X\n", + (A_UINT32)pEPDist, (A_UINT32)pEPDist->pNext, (A_UINT32)pEPDist->pPrev)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" DistFlags : 0x%X \n", pEPDist->DistFlags)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsNorm : %d \n", pEPDist->TxCreditsNorm)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsMin : %d \n", pEPDist->TxCreditsMin)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCredits : %d \n", pEPDist->TxCredits)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsAssigned : %d \n", pEPDist->TxCreditsAssigned)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsSeek : %d \n", pEPDist->TxCreditsSeek)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditSize : %d \n", pEPDist->TxCreditSize)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsPerMaxMsg : %d \n", pEPDist->TxCreditsPerMaxMsg)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsToDist : %d \n", pEPDist->TxCreditsToDist)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxQueueDepth : %d \n", + ((HTC_ENDPOINT *) pEPDist->pHTCReserved)->CurrentTxQueueDepth)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("----------------------------------------------------\n")); +} + +void DumpCreditDistStates(HTC_TARGET *target) +{ + HTC_ENDPOINT_CREDIT_DIST *pEPList = target->EpCreditDistributionListHead; + + while (pEPList != NULL) { + DumpCreditDist(pEPList); + pEPList = pEPList->pNext; + } + + if (target->DistributeCredits != NULL) { + DO_DISTRIBUTION(target, + HTC_DUMP_CREDIT_STATE, + "Dump State", + NULL); + } +} + +/* flush all send packets from all endpoint queues */ +void HTCFlushSendPkts(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + int i; + + DumpCreditDistStates(target); + + for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) { + pEndpoint = &target->EndPoint[i]; + if (pEndpoint->ServiceID == 0) { + /* not in use.. */ + continue; + } + HTCFlushEndpointTX(target,pEndpoint,HTC_TX_PACKET_TAG_ALL); + } + + +} + +/* HTC API to flush an endpoint's TX queue*/ +void HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint = &target->EndPoint[Endpoint]; + + if (pEndpoint->ServiceID == 0) { + AR_DEBUG_ASSERT(FALSE); + /* not in use.. */ + return; + } + + HTCFlushEndpointTX(target, pEndpoint, Tag); +} + +/* HTC API to indicate activity to the credit distribution function */ +void HTCIndicateActivityChange(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + A_BOOL Active) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint = &target->EndPoint[Endpoint]; + A_BOOL doDist = FALSE; + + if (pEndpoint->ServiceID == 0) { + AR_DEBUG_ASSERT(FALSE); + /* not in use.. */ + return; + } + + LOCK_HTC_TX(target); + + if (Active) { + if (!(pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE)) { + /* mark active now */ + pEndpoint->CreditDist.DistFlags |= HTC_EP_ACTIVE; + doDist = TRUE; + } + } else { + if (pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE) { + /* mark inactive now */ + pEndpoint->CreditDist.DistFlags &= ~HTC_EP_ACTIVE; + doDist = TRUE; + } + } + + if (doDist) { + /* do distribution again based on activity change + * note, this is done with the lock held */ + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_ACTIVITY_CHANGE, + "Activity Change", + target->EpCreditDistributionListHead->pNext); + } + + UNLOCK_HTC_TX(target); + + if (doDist && !Active) { + /* if a stream went inactive and this resulted in a credit distribution change, + * some credits may now be available for HTC packets that are stuck in + * HTC queues */ + HTCCheckEndpointTxQueues(target); + } +} + diff -urN linux-2.6.26/drivers/net/wireless/ar6000/htc_services.c linux-2.6.26-lab126/drivers/net/wireless/ar6000/htc_services.c --- linux-2.6.26/drivers/net/wireless/ar6000/htc_services.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/htc_services.c 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,412 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + +void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket) +{ + /* not implemented + * we do not send control TX frames during normal runtime, only during setup */ + AR_DEBUG_ASSERT(FALSE); +} + + /* callback when a control message arrives on this endpoint */ +void HTCControlRecv(void *Context, HTC_PACKET *pPacket) +{ + AR_DEBUG_ASSERT(pPacket->Endpoint == ENDPOINT_0); + + if (pPacket->Status == A_ECANCELED) { + /* this is a flush operation, return the control packet back to the pool */ + HTC_FREE_CONTROL_RX((HTC_TARGET*)Context,pPacket); + return; + } + + /* the only control messages we are expecting are NULL messages (credit resports), which should + * never get here */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCControlRecv, got message with length:%d \n", + pPacket->ActualLength + HTC_HDR_LENGTH)); + + /* dump header and message */ + DebugDumpBytes(pPacket->pBuffer - HTC_HDR_LENGTH, + pPacket->ActualLength + HTC_HDR_LENGTH, + "Unexpected ENDPOINT 0 Message"); + + HTC_RECYCLE_RX_PKT((HTC_TARGET*)Context,pPacket,&((HTC_TARGET*)Context)->EndPoint[0]); +} + +A_STATUS HTCSendSetupComplete(HTC_TARGET *target) +{ + HTC_PACKET *pSendPacket = NULL; + A_STATUS status; + HTC_SETUP_COMPLETE_MSG *pSetupComplete; + + do { + /* allocate a packet to send to the target */ + pSendPacket = HTC_ALLOC_CONTROL_TX(target); + + if (NULL == pSendPacket) { + status = A_NO_MEMORY; + break; + } + + /* assemble setup complete message */ + pSetupComplete = (HTC_SETUP_COMPLETE_MSG *)pSendPacket->pBuffer; + A_MEMZERO(pSetupComplete,sizeof(HTC_SETUP_COMPLETE_MSG)); + pSetupComplete->MessageID = HTC_MSG_SETUP_COMPLETE_ID; + + SET_HTC_PACKET_INFO_TX(pSendPacket, + NULL, + (A_UINT8 *)pSetupComplete, + sizeof(HTC_SETUP_COMPLETE_MSG), + ENDPOINT_0, + HTC_SERVICE_TX_PACKET_TAG); + + /* we want synchronous operation */ + pSendPacket->Completion = NULL; + /* send the message */ + status = HTCIssueSend(target,pSendPacket,0); + + } while (FALSE); + + if (pSendPacket != NULL) { + HTC_FREE_CONTROL_TX(target,pSendPacket); + } + + return status; +} + + +A_STATUS HTCConnectService(HTC_HANDLE HTCHandle, + HTC_SERVICE_CONNECT_REQ *pConnectReq, + HTC_SERVICE_CONNECT_RESP *pConnectResp) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_STATUS status = A_OK; + HTC_PACKET *pRecvPacket = NULL; + HTC_PACKET *pSendPacket = NULL; + HTC_CONNECT_SERVICE_RESPONSE_MSG *pResponseMsg; + HTC_CONNECT_SERVICE_MSG *pConnectMsg; + HTC_ENDPOINT_ID assignedEndpoint = ENDPOINT_MAX; + HTC_ENDPOINT *pEndpoint; + int maxMsgSize = 0; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCConnectService, target:0x%X SvcID:0x%X \n", + (A_UINT32)target, pConnectReq->ServiceID)); + + do { + + AR_DEBUG_ASSERT(pConnectReq->ServiceID != 0); + + if (HTC_CTRL_RSVD_SVC == pConnectReq->ServiceID) { + /* special case for pseudo control service */ + assignedEndpoint = ENDPOINT_0; + maxMsgSize = HTC_MAX_CONTROL_MESSAGE_LENGTH; + } else { + /* allocate a packet to send to the target */ + pSendPacket = HTC_ALLOC_CONTROL_TX(target); + + if (NULL == pSendPacket) { + AR_DEBUG_ASSERT(FALSE); + status = A_NO_MEMORY; + break; + } + /* assemble connect service message */ + pConnectMsg = (HTC_CONNECT_SERVICE_MSG *)pSendPacket->pBuffer; + AR_DEBUG_ASSERT(pConnectMsg != NULL); + A_MEMZERO(pConnectMsg,sizeof(HTC_CONNECT_SERVICE_MSG)); + pConnectMsg->MessageID = HTC_MSG_CONNECT_SERVICE_ID; + pConnectMsg->ServiceID = pConnectReq->ServiceID; + pConnectMsg->ConnectionFlags = pConnectReq->ConnectionFlags; + /* check caller if it wants to transfer meta data */ + if ((pConnectReq->pMetaData != NULL) && + (pConnectReq->MetaDataLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) { + /* copy meta data into message buffer (after header ) */ + A_MEMCPY((A_UINT8 *)pConnectMsg + sizeof(HTC_CONNECT_SERVICE_MSG), + pConnectReq->pMetaData, + pConnectReq->MetaDataLength); + pConnectMsg->ServiceMetaLength = pConnectReq->MetaDataLength; + } + + SET_HTC_PACKET_INFO_TX(pSendPacket, + NULL, + (A_UINT8 *)pConnectMsg, + sizeof(HTC_CONNECT_SERVICE_MSG) + pConnectMsg->ServiceMetaLength, + ENDPOINT_0, + HTC_SERVICE_TX_PACKET_TAG); + + /* we want synchronous operation */ + pSendPacket->Completion = NULL; + + status = HTCIssueSend(target,pSendPacket,0); + + if (A_FAILED(status)) { + break; + } + + /* wait for response */ + status = HTCWaitforControlMessage(target, &pRecvPacket); + + if (A_FAILED(status)) { + break; + } + /* we controlled the buffer creation so it has to be properly aligned */ + pResponseMsg = (HTC_CONNECT_SERVICE_RESPONSE_MSG *)pRecvPacket->pBuffer; + + if ((pResponseMsg->MessageID != HTC_MSG_CONNECT_SERVICE_RESPONSE_ID) || + (pRecvPacket->ActualLength < sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG))) { + /* this message is not valid */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + pConnectResp->ConnectRespCode = pResponseMsg->Status; + /* check response status */ + if (pResponseMsg->Status != HTC_SERVICE_SUCCESS) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" Target failed service 0x%X connect request (status:%d)\n", + pResponseMsg->ServiceID, pResponseMsg->Status)); + status = A_EPROTO; + break; + } + + assignedEndpoint = (HTC_ENDPOINT_ID) pResponseMsg->EndpointID; + maxMsgSize = pResponseMsg->MaxMsgSize; + + if ((pConnectResp->pMetaData != NULL) && + (pResponseMsg->ServiceMetaLength > 0) && + (pResponseMsg->ServiceMetaLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) { + /* caller supplied a buffer and the target responded with data */ + int copyLength = min((int)pConnectResp->BufferLength, (int)pResponseMsg->ServiceMetaLength); + /* copy the meta data */ + A_MEMCPY(pConnectResp->pMetaData, + ((A_UINT8 *)pResponseMsg) + sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG), + copyLength); + pConnectResp->ActualLength = copyLength; + } + + } + + /* the rest of these are parameter checks so set the error status */ + status = A_EPROTO; + + if (assignedEndpoint >= ENDPOINT_MAX) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + if (0 == maxMsgSize) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + pEndpoint = &target->EndPoint[assignedEndpoint]; + + if (pEndpoint->ServiceID != 0) { + /* endpoint already in use! */ + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* return assigned endpoint to caller */ + pConnectResp->Endpoint = assignedEndpoint; + pConnectResp->MaxMsgLength = maxMsgSize; + + /* setup the endpoint */ + pEndpoint->ServiceID = pConnectReq->ServiceID; /* this marks the endpoint in use */ + pEndpoint->MaxTxQueueDepth = pConnectReq->MaxSendQueueDepth; + pEndpoint->MaxMsgLength = maxMsgSize; + /* copy all the callbacks */ + pEndpoint->EpCallBacks = pConnectReq->EpCallbacks; + INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBuffers); + INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue); + /* set the credit distribution info for this endpoint, this information is + * passed back to the credit distribution callback function */ + pEndpoint->CreditDist.ServiceID = pConnectReq->ServiceID; + pEndpoint->CreditDist.pHTCReserved = pEndpoint; + pEndpoint->CreditDist.Endpoint = assignedEndpoint; + pEndpoint->CreditDist.TxCreditSize = target->TargetCreditSize; + pEndpoint->CreditDist.TxCreditsPerMaxMsg = maxMsgSize / target->TargetCreditSize; + + if (0 == pEndpoint->CreditDist.TxCreditsPerMaxMsg) { + pEndpoint->CreditDist.TxCreditsPerMaxMsg = 1; + } + + status = A_OK; + + } while (FALSE); + + if (pSendPacket != NULL) { + HTC_FREE_CONTROL_TX(target,pSendPacket); + } + + if (pRecvPacket != NULL) { + HTC_FREE_CONTROL_RX(target,pRecvPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCConnectService \n")); + + return status; +} + +static void AddToEndpointDistList(HTC_TARGET *target, HTC_ENDPOINT_CREDIT_DIST *pEpDist) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEntry,*pLastEntry; + + if (NULL == target->EpCreditDistributionListHead) { + target->EpCreditDistributionListHead = pEpDist; + pEpDist->pNext = NULL; + pEpDist->pPrev = NULL; + return; + } + + /* queue to the end of the list, this does not have to be very + * fast since this list is built at startup time */ + pCurEntry = target->EpCreditDistributionListHead; + + while (pCurEntry) { + pLastEntry = pCurEntry; + pCurEntry = pCurEntry->pNext; + } + + pLastEntry->pNext = pEpDist; + pEpDist->pPrev = pLastEntry; + pEpDist->pNext = NULL; +} + + + +/* default credit init callback */ +static void HTCDefaultCreditInit(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + int TotalCredits) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + int totalEps = 0; + int creditsPerEndpoint; + + pCurEpDist = pEPList; + /* first run through the list and figure out how many endpoints we are dealing with */ + while (pCurEpDist != NULL) { + pCurEpDist = pCurEpDist->pNext; + totalEps++; + } + + /* even distribution */ + creditsPerEndpoint = TotalCredits/totalEps; + + pCurEpDist = pEPList; + /* run through the list and set minimum and normal credits and + * provide the endpoint with some credits to start */ + while (pCurEpDist != NULL) { + + if (creditsPerEndpoint < pCurEpDist->TxCreditsPerMaxMsg) { + /* too many endpoints and not enough credits */ + AR_DEBUG_ASSERT(FALSE); + break; + } + /* our minimum is set for at least 1 max message */ + pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg; + /* this value is ignored by our credit alg, since we do + * not dynamically adjust credits, this is the policy of + * the "default" credit distribution, something simple and easy */ + pCurEpDist->TxCreditsNorm = 0xFFFF; + /* give the endpoint minimum credits */ + pCurEpDist->TxCredits = creditsPerEndpoint; + pCurEpDist->TxCreditsAssigned = creditsPerEndpoint; + pCurEpDist = pCurEpDist->pNext; + } + +} + +/* default credit distribution callback, NOTE, this callback holds the TX lock */ +void HTCDefaultCreditDist(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList, + HTC_CREDIT_DIST_REASON Reason) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + + if (Reason == HTC_CREDIT_DIST_SEND_COMPLETE) { + pCurEpDist = pEPDistList; + /* simple distribution */ + while (pCurEpDist != NULL) { + if (pCurEpDist->TxCreditsToDist > 0) { + /* just give the endpoint back the credits */ + pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist; + pCurEpDist->TxCreditsToDist = 0; + } + pCurEpDist = pCurEpDist->pNext; + } + } + + /* note we do not need to handle the other reason codes as this is a very + * simple distribution scheme, no need to seek for more credits or handle inactivity */ +} + +void HTCSetCreditDistribution(HTC_HANDLE HTCHandle, + void *pCreditDistContext, + HTC_CREDIT_DIST_CALLBACK CreditDistFunc, + HTC_CREDIT_INIT_CALLBACK CreditInitFunc, + HTC_SERVICE_ID ServicePriorityOrder[], + int ListLength) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + int i; + int ep; + + if (CreditInitFunc != NULL) { + /* caller has supplied their own distribution functions */ + target->InitCredits = CreditInitFunc; + AR_DEBUG_ASSERT(CreditDistFunc != NULL); + target->DistributeCredits = CreditDistFunc; + target->pCredDistContext = pCreditDistContext; + } else { + /* caller wants HTC to do distribution */ + /* if caller wants service to handle distributions then + * it must set both of these to NULL! */ + AR_DEBUG_ASSERT(CreditDistFunc == NULL); + target->InitCredits = HTCDefaultCreditInit; + target->DistributeCredits = HTCDefaultCreditDist; + target->pCredDistContext = target; + } + + /* always add HTC control endpoint first, we only expose the list after the + * first one, this is added for TX queue checking */ + AddToEndpointDistList(target, &target->EndPoint[ENDPOINT_0].CreditDist); + + /* build the list of credit distribution structures in priority order + * supplied by the caller, these will follow endpoint 0 */ + for (i = 0; i < ListLength; i++) { + /* match services with endpoints and add the endpoints to the distribution list + * in FIFO order */ + for (ep = ENDPOINT_1; ep < ENDPOINT_MAX; ep++) { + if (target->EndPoint[ep].ServiceID == ServicePriorityOrder[i]) { + /* queue this one to the list */ + AddToEndpointDistList(target, &target->EndPoint[ep].CreditDist); + break; + } + } + AR_DEBUG_ASSERT(ep < ENDPOINT_MAX); + } + +} diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/AR6000/ar6k.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/AR6000/ar6k.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/AR6000/ar6k.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/AR6000/ar6k.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,199 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// AR6K device layer that handles register level I/O +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef AR6K_H_ +#define AR6K_H_ + +#define AR6K_MAILBOXES 4 + +/* HTC runs over mailbox 0 */ +#define HTC_MAILBOX 0 + +#define AR6K_TARGET_DEBUG_INTR_MASK 0x01 + +#define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK | \ + INT_STATUS_ENABLE_CPU_MASK | \ + INT_STATUS_ENABLE_COUNTER_MASK) + +//#define MBOXHW_UNIT_TEST 1 + +#include "athstartpack.h" +typedef PREPACK struct _AR6K_IRQ_PROC_REGISTERS { + A_UINT8 host_int_status; + A_UINT8 cpu_int_status; + A_UINT8 error_int_status; + A_UINT8 counter_int_status; + A_UINT8 mbox_frame; + A_UINT8 rx_lookahead_valid; + A_UINT8 hole[2]; + A_UINT32 rx_lookahead[2]; +} POSTPACK AR6K_IRQ_PROC_REGISTERS; + +#define AR6K_IRQ_PROC_REGS_SIZE sizeof(AR6K_IRQ_PROC_REGISTERS) + + + +typedef PREPACK struct _AR6K_IRQ_ENABLE_REGISTERS { + A_UINT8 int_status_enable; + A_UINT8 cpu_int_status_enable; + A_UINT8 error_status_enable; + A_UINT8 counter_int_status_enable; +} POSTPACK AR6K_IRQ_ENABLE_REGISTERS; + +#include "athendpack.h" + +#define AR6K_IRQ_ENABLE_REGS_SIZE sizeof(AR6K_IRQ_ENABLE_REGISTERS) + +#define AR6K_REG_IO_BUFFER_SIZE 32 +#define AR6K_MAX_REG_IO_BUFFERS 8 + +/* buffers for ASYNC I/O */ +typedef struct AR6K_ASYNC_REG_IO_BUFFER { + HTC_PACKET HtcPacket; /* we use an HTC packet as a wrapper for our async register-based I/O */ + A_UINT8 Buffer[AR6K_REG_IO_BUFFER_SIZE]; +} AR6K_ASYNC_REG_IO_BUFFER; + +typedef struct _AR6K_DEVICE { + A_MUTEX_T Lock; + AR6K_IRQ_PROC_REGISTERS IrqProcRegisters; + AR6K_IRQ_ENABLE_REGISTERS IrqEnableRegisters; + void *HIFDevice; + A_UINT32 BlockSize; + A_UINT32 BlockMask; + A_UINT32 MailboxAddress; + HIF_PENDING_EVENTS_FUNC GetPendingEventsFunc; + void *HTCContext; + HTC_PACKET_QUEUE RegisterIOList; + AR6K_ASYNC_REG_IO_BUFFER RegIOBuffers[AR6K_MAX_REG_IO_BUFFERS]; + void (*TargetFailureCallback)(void *Context); + A_STATUS (*MessagePendingCallback)(void *Context, A_UINT32 LookAhead, A_BOOL *pAsyncProc); + HIF_DEVICE_IRQ_PROCESSING_MODE HifIRQProcessingMode; + HIF_MASK_UNMASK_RECV_EVENT HifMaskUmaskRecvEvent; +} AR6K_DEVICE; + +#define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) ((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY) + +A_STATUS DevSetup(AR6K_DEVICE *pDev); +void DevCleanup(AR6K_DEVICE *pDev); +A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev, + A_UINT32 *pLookAhead, + int TimeoutMS); +A_STATUS DevRWCompletionHandler(void *context, A_STATUS status); +A_STATUS DevDsrHandler(void *context); +A_STATUS DevCheckPendingRecvMsgsAsync(void *context); +void DevDumpRegisters(AR6K_IRQ_PROC_REGISTERS *pIrqProcRegs, + AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs); + +#define DEV_STOP_RECV_ASYNC TRUE +#define DEV_STOP_RECV_SYNC FALSE +#define DEV_ENABLE_RECV_ASYNC TRUE +#define DEV_ENABLE_RECV_SYNC FALSE +A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode); +A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode); +A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev); + +static INLINE A_STATUS DevSendPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 SendLength) { + A_UINT32 paddedLength; + A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE; + A_STATUS status; + + /* adjust the length to be a multiple of block size if appropriate */ + paddedLength = (SendLength + (pDev->BlockMask)) & + (~(pDev->BlockMask)); +#if 0 // BufferLength may not be set in , fix this... + if (paddedLength > pPacket->BufferLength) { + AR_DEBUG_ASSERT(FALSE); + if (pPacket->Completion != NULL) { + COMPLETE_HTC_PACKET(pPacket,A_EINVAL); + } + return A_EINVAL; + } +#endif + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("DevSendPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n", + paddedLength, + pDev->MailboxAddress, + sync ? "SYNC" : "ASYNC")); + + status = HIFReadWrite(pDev->HIFDevice, + pDev->MailboxAddress, + pPacket->pBuffer, + paddedLength, /* the padded length */ + sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC, + sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */ + + if (sync) { + pPacket->Status = status; + } + + return status; +} + +static INLINE A_STATUS DevRecvPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 RecvLength) { + A_UINT32 paddedLength; + A_STATUS status; + A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE; + + /* adjust the length to be a multiple of block size if appropriate */ + paddedLength = (RecvLength + (pDev->BlockMask)) & + (~(pDev->BlockMask)); + if (paddedLength > pPacket->BufferLength) { + AR_DEBUG_ASSERT(FALSE); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("DevRecvPacket, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n", + paddedLength,RecvLength,pPacket->BufferLength)); + if (pPacket->Completion != NULL) { + COMPLETE_HTC_PACKET(pPacket,A_EINVAL); + } + return A_EINVAL; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("DevRecvPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n", + paddedLength, + pDev->MailboxAddress, + sync ? "SYNC" : "ASYNC")); + + status = HIFReadWrite(pDev->HIFDevice, + pDev->MailboxAddress, + pPacket->pBuffer, + paddedLength, + sync ? HIF_RD_SYNC_BLOCK_INC : HIF_RD_ASYNC_BLOCK_INC, + sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */ + + if (sync) { + pPacket->Status = status; + } + + return status; +} + +#ifdef MBOXHW_UNIT_TEST +A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev); +#endif + +#endif /*AR6K_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/AR6002/AR6002_regdump.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/AR6002/AR6002_regdump.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/AR6002/AR6002_regdump.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/AR6002/AR6002_regdump.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,59 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2006 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __AR6002_REGDUMP_H__ +#define __AR6002_REGDUMP_H__ + +#if !defined(__ASSEMBLER__) +/* + * XTensa CPU state + * This must match the state saved by the target exception handler. + */ +struct XTensa_exception_frame_s { + A_UINT32 xt_pc; + A_UINT32 xt_ps; + A_UINT32 xt_sar; + A_UINT32 xt_vpri; + A_UINT32 xt_a2; + A_UINT32 xt_a3; + A_UINT32 xt_a4; + A_UINT32 xt_a5; + A_UINT32 xt_exccause; + A_UINT32 xt_lcount; + A_UINT32 xt_lbeg; + A_UINT32 xt_lend; + + /* Extra info to simplify post-mortem stack walkback */ +#define AR6002_REGDUMP_FRAMES 5 + struct { + A_UINT32 a0; /* pc */ + A_UINT32 a1; /* sp */ + A_UINT32 a2; + A_UINT32 a3; + } wb[AR6002_REGDUMP_FRAMES]; +}; +typedef struct XTensa_exception_frame_s CPU_exception_frame_t; +#define RD_SIZE sizeof(CPU_exception_frame_t) + +#endif +#endif /* __AR6002_REGDUMP_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/AR6002/AR6K_version.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/AR6002/AR6K_version.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/AR6002/AR6K_version.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/AR6002/AR6K_version.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#define __VER_MAJOR_ 2 +#define __VER_MINOR_ 1 +#define __VER_PATCH_ 2 + + +/* The makear6ksdk script (used for release builds) modifies the following line. */ +#define __BUILD_NUMBER_ 20 + + +/* Format of the version number. */ +#define VER_MAJOR_BIT_OFFSET 28 +#define VER_MINOR_BIT_OFFSET 24 +#define VER_PATCH_BIT_OFFSET 16 +#define VER_BUILD_NUM_BIT_OFFSET 0 + + +/* + * The version has the following format: + * Bits 28-31: Major version + * Bits 24-27: Minor version + * Bits 16-23: Patch version + * Bits 0-15: Build number (automatically generated during build process ) + * E.g. Build 1.1.3.7 would be represented as 0x11030007. + * + * DO NOT split the following macro into multiple lines as this may confuse the build scripts. + */ +#define AR6K_SW_VERSION ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) ) + + diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/AR6002/addrs.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/AR6002/addrs.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/AR6002/addrs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/AR6002/addrs.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,63 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __ADDRS_H__ +#define __ADDRS_H__ + +/* + * Special AR6002 Addresses that may be needed by special + * applications (e.g. ART) on the Host as well as Target. + */ + +#define AR6K_RAM_START 0x00500000 +#define AR6K_RAM_ADDR(byte_offset) (AR6K_RAM_START+(byte_offset)) +#define TARG_RAM_ADDRS(byte_offset) AR6K_RAM_ADDR(byte_offset) +#define TARG_RAM_OFFSET(vaddr) ((A_UINT32)(vaddr) & 0xfffff) +#define TARG_RAM_SZ (184*1024) + +#define AR6K_ROM_START 0x004e0000 +#define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset)) +#define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset) + +/* + * At this ROM address is a pointer to the start of the ROM DataSet Index. + * If there are no ROM DataSets, there's a 0 at this address. + */ +#define ROM_DATASET_INDEX_ADDR 0x004f3ff8 +#define ROM_MBIST_CKSUM_ADDR 0x004f3ffc + +/* + * The API A_BOARD_DATA_ADDR() is the proper way to get a read pointer to + * board data. + */ + +/* Size of Board Data, in bytes */ +#define AR6002_BOARD_DATA_SZ 768 +#define BOARD_DATA_SZ AR6002_BOARD_DATA_SZ + +/* + * Constants used by ASM code to access fields of host_interest_s, + * which is at a fixed location in RAM. + */ +#define FLASH_IS_PRESENT_TARGADDR 0x0050040c +#endif /* __ADDRS_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/AR6002/hw/mbox_host_reg.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/AR6002/hw/mbox_host_reg.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/AR6002/hw/mbox_host_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/AR6002/hw/mbox_host_reg.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,409 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MBOX_HOST_REG_REG_H_ +#define _MBOX_HOST_REG_REG_H_ + +#define HOST_INT_STATUS_ADDRESS 0x00000400 +#define HOST_INT_STATUS_OFFSET 0x00000400 +#define HOST_INT_STATUS_ERROR_MSB 7 +#define HOST_INT_STATUS_ERROR_LSB 7 +#define HOST_INT_STATUS_ERROR_MASK 0x00000080 +#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB) +#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK) +#define HOST_INT_STATUS_CPU_MSB 6 +#define HOST_INT_STATUS_CPU_LSB 6 +#define HOST_INT_STATUS_CPU_MASK 0x00000040 +#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB) +#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK) +#define HOST_INT_STATUS_DRAGON_INT_MSB 5 +#define HOST_INT_STATUS_DRAGON_INT_LSB 5 +#define HOST_INT_STATUS_DRAGON_INT_MASK 0x00000020 +#define HOST_INT_STATUS_DRAGON_INT_GET(x) (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB) +#define HOST_INT_STATUS_DRAGON_INT_SET(x) (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK) +#define HOST_INT_STATUS_COUNTER_MSB 4 +#define HOST_INT_STATUS_COUNTER_LSB 4 +#define HOST_INT_STATUS_COUNTER_MASK 0x00000010 +#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB) +#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK) +#define HOST_INT_STATUS_MBOX_DATA_MSB 3 +#define HOST_INT_STATUS_MBOX_DATA_LSB 0 +#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f +#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB) +#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ADDRESS 0x00000401 +#define CPU_INT_STATUS_OFFSET 0x00000401 +#define CPU_INT_STATUS_BIT_MSB 7 +#define CPU_INT_STATUS_BIT_LSB 0 +#define CPU_INT_STATUS_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB) +#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK) + +#define ERROR_INT_STATUS_ADDRESS 0x00000402 +#define ERROR_INT_STATUS_OFFSET 0x00000402 +#define ERROR_INT_STATUS_SPI_MSB 3 +#define ERROR_INT_STATUS_SPI_LSB 3 +#define ERROR_INT_STATUS_SPI_MASK 0x00000008 +#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB) +#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK) +#define ERROR_INT_STATUS_WAKEUP_MSB 2 +#define ERROR_INT_STATUS_WAKEUP_LSB 2 +#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 +#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB) +#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK) +#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB) +#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) +#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB) +#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ADDRESS 0x00000403 +#define COUNTER_INT_STATUS_OFFSET 0x00000403 +#define COUNTER_INT_STATUS_COUNTER_MSB 7 +#define COUNTER_INT_STATUS_COUNTER_LSB 0 +#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff +#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB) +#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK) + +#define MBOX_FRAME_ADDRESS 0x00000404 +#define MBOX_FRAME_OFFSET 0x00000404 +#define MBOX_FRAME_RX_EOM_MSB 7 +#define MBOX_FRAME_RX_EOM_LSB 4 +#define MBOX_FRAME_RX_EOM_MASK 0x000000f0 +#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB) +#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK) +#define MBOX_FRAME_RX_SOM_MSB 3 +#define MBOX_FRAME_RX_SOM_LSB 0 +#define MBOX_FRAME_RX_SOM_MASK 0x0000000f +#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB) +#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK) + +#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405 +#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405 +#define RX_LOOKAHEAD_VALID_MBOX_MSB 3 +#define RX_LOOKAHEAD_VALID_MBOX_LSB 0 +#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f +#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB) +#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK) + +#define RX_LOOKAHEAD0_ADDRESS 0x00000408 +#define RX_LOOKAHEAD0_OFFSET 0x00000408 +#define RX_LOOKAHEAD0_DATA_MSB 7 +#define RX_LOOKAHEAD0_DATA_LSB 0 +#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB) +#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK) + +#define RX_LOOKAHEAD1_ADDRESS 0x0000040c +#define RX_LOOKAHEAD1_OFFSET 0x0000040c +#define RX_LOOKAHEAD1_DATA_MSB 7 +#define RX_LOOKAHEAD1_DATA_LSB 0 +#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB) +#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK) + +#define RX_LOOKAHEAD2_ADDRESS 0x00000410 +#define RX_LOOKAHEAD2_OFFSET 0x00000410 +#define RX_LOOKAHEAD2_DATA_MSB 7 +#define RX_LOOKAHEAD2_DATA_LSB 0 +#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB) +#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK) + +#define RX_LOOKAHEAD3_ADDRESS 0x00000414 +#define RX_LOOKAHEAD3_OFFSET 0x00000414 +#define RX_LOOKAHEAD3_DATA_MSB 7 +#define RX_LOOKAHEAD3_DATA_LSB 0 +#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB) +#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK) + +#define INT_STATUS_ENABLE_ADDRESS 0x00000418 +#define INT_STATUS_ENABLE_OFFSET 0x00000418 +#define INT_STATUS_ENABLE_ERROR_MSB 7 +#define INT_STATUS_ENABLE_ERROR_LSB 7 +#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080 +#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB) +#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK) +#define INT_STATUS_ENABLE_CPU_MSB 6 +#define INT_STATUS_ENABLE_CPU_LSB 6 +#define INT_STATUS_ENABLE_CPU_MASK 0x00000040 +#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB) +#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK) +#define INT_STATUS_ENABLE_DRAGON_INT_MSB 5 +#define INT_STATUS_ENABLE_DRAGON_INT_LSB 5 +#define INT_STATUS_ENABLE_DRAGON_INT_MASK 0x00000020 +#define INT_STATUS_ENABLE_DRAGON_INT_GET(x) (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB) +#define INT_STATUS_ENABLE_DRAGON_INT_SET(x) (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK) +#define INT_STATUS_ENABLE_COUNTER_MSB 4 +#define INT_STATUS_ENABLE_COUNTER_LSB 4 +#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 +#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB) +#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK) +#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3 +#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0 +#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f +#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB) +#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 +#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419 +#define CPU_INT_STATUS_ENABLE_BIT_MSB 7 +#define CPU_INT_STATUS_ENABLE_BIT_LSB 0 +#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB) +#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK) + +#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a +#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a +#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004 +#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB) +#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7 +#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 +#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB) +#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) + +#define COUNT_ADDRESS 0x00000420 +#define COUNT_OFFSET 0x00000420 +#define COUNT_VALUE_MSB 7 +#define COUNT_VALUE_LSB 0 +#define COUNT_VALUE_MASK 0x000000ff +#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB) +#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK) + +#define COUNT_DEC_ADDRESS 0x00000440 +#define COUNT_DEC_OFFSET 0x00000440 +#define COUNT_DEC_VALUE_MSB 7 +#define COUNT_DEC_VALUE_LSB 0 +#define COUNT_DEC_VALUE_MASK 0x000000ff +#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB) +#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK) + +#define SCRATCH_ADDRESS 0x00000460 +#define SCRATCH_OFFSET 0x00000460 +#define SCRATCH_VALUE_MSB 7 +#define SCRATCH_VALUE_LSB 0 +#define SCRATCH_VALUE_MASK 0x000000ff +#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB) +#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK) + +#define FIFO_TIMEOUT_ADDRESS 0x00000468 +#define FIFO_TIMEOUT_OFFSET 0x00000468 +#define FIFO_TIMEOUT_VALUE_MSB 7 +#define FIFO_TIMEOUT_VALUE_LSB 0 +#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff +#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB) +#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK) + +#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469 +#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469 +#define FIFO_TIMEOUT_ENABLE_SET_MSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_LSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001 +#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB) +#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK) + +#define DISABLE_SLEEP_ADDRESS 0x0000046a +#define DISABLE_SLEEP_OFFSET 0x0000046a +#define DISABLE_SLEEP_FOR_INT_MSB 1 +#define DISABLE_SLEEP_FOR_INT_LSB 1 +#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002 +#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB) +#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK) +#define DISABLE_SLEEP_ON_MSB 0 +#define DISABLE_SLEEP_ON_LSB 0 +#define DISABLE_SLEEP_ON_MASK 0x00000001 +#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB) +#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK) + +#define LOCAL_BUS_ADDRESS 0x00000470 +#define LOCAL_BUS_OFFSET 0x00000470 +#define LOCAL_BUS_STATE_MSB 1 +#define LOCAL_BUS_STATE_LSB 0 +#define LOCAL_BUS_STATE_MASK 0x00000003 +#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB) +#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK) + +#define INT_WLAN_ADDRESS 0x00000472 +#define INT_WLAN_OFFSET 0x00000472 +#define INT_WLAN_VECTOR_MSB 7 +#define INT_WLAN_VECTOR_LSB 0 +#define INT_WLAN_VECTOR_MASK 0x000000ff +#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB) +#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK) + +#define WINDOW_DATA_ADDRESS 0x00000474 +#define WINDOW_DATA_OFFSET 0x00000474 +#define WINDOW_DATA_DATA_MSB 7 +#define WINDOW_DATA_DATA_LSB 0 +#define WINDOW_DATA_DATA_MASK 0x000000ff +#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB) +#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK) + +#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 +#define WINDOW_WRITE_ADDR_OFFSET 0x00000478 +#define WINDOW_WRITE_ADDR_ADDR_MSB 7 +#define WINDOW_WRITE_ADDR_ADDR_LSB 0 +#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB) +#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK) + +#define WINDOW_READ_ADDR_ADDRESS 0x0000047c +#define WINDOW_READ_ADDR_OFFSET 0x0000047c +#define WINDOW_READ_ADDR_ADDR_MSB 7 +#define WINDOW_READ_ADDR_ADDR_LSB 0 +#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB) +#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK) + +#define SPI_CONFIG_ADDRESS 0x00000480 +#define SPI_CONFIG_OFFSET 0x00000480 +#define SPI_CONFIG_SPI_RESET_MSB 4 +#define SPI_CONFIG_SPI_RESET_LSB 4 +#define SPI_CONFIG_SPI_RESET_MASK 0x00000010 +#define SPI_CONFIG_SPI_RESET_GET(x) (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB) +#define SPI_CONFIG_SPI_RESET_SET(x) (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK) +#define SPI_CONFIG_INTERRUPT_ENABLE_MSB 3 +#define SPI_CONFIG_INTERRUPT_ENABLE_LSB 3 +#define SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008 +#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB) +#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) +#define SPI_CONFIG_TEST_MODE_MSB 2 +#define SPI_CONFIG_TEST_MODE_LSB 2 +#define SPI_CONFIG_TEST_MODE_MASK 0x00000004 +#define SPI_CONFIG_TEST_MODE_GET(x) (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB) +#define SPI_CONFIG_TEST_MODE_SET(x) (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK) +#define SPI_CONFIG_DATA_SIZE_MSB 1 +#define SPI_CONFIG_DATA_SIZE_LSB 0 +#define SPI_CONFIG_DATA_SIZE_MASK 0x00000003 +#define SPI_CONFIG_DATA_SIZE_GET(x) (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB) +#define SPI_CONFIG_DATA_SIZE_SET(x) (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK) + +#define SPI_STATUS_ADDRESS 0x00000481 +#define SPI_STATUS_OFFSET 0x00000481 +#define SPI_STATUS_ADDR_ERR_MSB 3 +#define SPI_STATUS_ADDR_ERR_LSB 3 +#define SPI_STATUS_ADDR_ERR_MASK 0x00000008 +#define SPI_STATUS_ADDR_ERR_GET(x) (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB) +#define SPI_STATUS_ADDR_ERR_SET(x) (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK) +#define SPI_STATUS_RD_ERR_MSB 2 +#define SPI_STATUS_RD_ERR_LSB 2 +#define SPI_STATUS_RD_ERR_MASK 0x00000004 +#define SPI_STATUS_RD_ERR_GET(x) (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB) +#define SPI_STATUS_RD_ERR_SET(x) (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK) +#define SPI_STATUS_WR_ERR_MSB 1 +#define SPI_STATUS_WR_ERR_LSB 1 +#define SPI_STATUS_WR_ERR_MASK 0x00000002 +#define SPI_STATUS_WR_ERR_GET(x) (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB) +#define SPI_STATUS_WR_ERR_SET(x) (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK) +#define SPI_STATUS_READY_MSB 0 +#define SPI_STATUS_READY_LSB 0 +#define SPI_STATUS_READY_MASK 0x00000001 +#define SPI_STATUS_READY_GET(x) (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB) +#define SPI_STATUS_READY_SET(x) (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK) + +#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482 +#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482 +#define NON_ASSOC_SLEEP_EN_BIT_MSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_LSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001 +#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB) +#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK) + +#define CIS_WINDOW_ADDRESS 0x00000600 +#define CIS_WINDOW_OFFSET 0x00000600 +#define CIS_WINDOW_DATA_MSB 7 +#define CIS_WINDOW_DATA_LSB 0 +#define CIS_WINDOW_DATA_MASK 0x000000ff +#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB) +#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mbox_host_reg_reg_s { + unsigned char pad0[1024]; /* pad to 0x400 */ + volatile unsigned char host_int_status; + volatile unsigned char cpu_int_status; + volatile unsigned char error_int_status; + volatile unsigned char counter_int_status; + volatile unsigned char mbox_frame; + volatile unsigned char rx_lookahead_valid; + unsigned char pad1[2]; /* pad to 0x408 */ + volatile unsigned char rx_lookahead0[4]; + volatile unsigned char rx_lookahead1[4]; + volatile unsigned char rx_lookahead2[4]; + volatile unsigned char rx_lookahead3[4]; + volatile unsigned char int_status_enable; + volatile unsigned char cpu_int_status_enable; + volatile unsigned char error_status_enable; + volatile unsigned char counter_int_status_enable; + unsigned char pad2[4]; /* pad to 0x420 */ + volatile unsigned char count[8]; + unsigned char pad3[24]; /* pad to 0x440 */ + volatile unsigned char count_dec[32]; + volatile unsigned char scratch[8]; + volatile unsigned char fifo_timeout; + volatile unsigned char fifo_timeout_enable; + volatile unsigned char disable_sleep; + unsigned char pad4[5]; /* pad to 0x470 */ + volatile unsigned char local_bus; + unsigned char pad5[1]; /* pad to 0x472 */ + volatile unsigned char int_wlan; + unsigned char pad6[1]; /* pad to 0x474 */ + volatile unsigned char window_data[4]; + volatile unsigned char window_write_addr[4]; + volatile unsigned char window_read_addr[4]; + volatile unsigned char spi_config; + volatile unsigned char spi_status; + volatile unsigned char non_assoc_sleep_en; + unsigned char pad7[381]; /* pad to 0x600 */ + volatile unsigned char cis_window[512]; +} mbox_host_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_HOST_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/a_config.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/a_config.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/a_config.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/a_config.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,41 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains software configuration options that enables +// specific software "features" +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_CONFIG_H_ +#define _A_CONFIG_H_ + +#ifdef UNDER_CE +#include "../os/wince/include/config_wince.h" +#endif + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "../os/linux/include/config_linux.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/config_rexos.h" +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/a_debug.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/a_debug.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/a_debug.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/a_debug.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,53 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_DEBUG_H_ +#define _A_DEBUG_H_ + +#include +#include + +#define DBG_INFO 0x00000001 +#define DBG_ERROR 0x00000002 +#define DBG_WARNING 0x00000004 +#define DBG_SDIO 0x00000008 +#define DBG_HIF 0x00000010 +#define DBG_HTC 0x00000020 +#define DBG_WMI 0x00000040 +#define DBG_WMI2 0x00000080 +#define DBG_DRIVER 0x00000100 + +#define DBG_DEFAULTS (DBG_ERROR|DBG_WARNING) + +#ifdef UNDER_CE +#include "../os/wince/include/debug_wince.h" +#endif + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "../os/linux/include/debug_linux.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/debug_rexos.h" +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/a_drv.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/a_drv.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/a_drv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/a_drv.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,42 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions of the basic atheros data types. +// It is used to map the data types in atheros files to a platform specific +// type. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_DRV_H_ +#define _A_DRV_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "../os/linux/include/athdrv_linux.h" +#endif + +#ifdef UNDER_CE +#include "../os/wince/include/athdrv_wince.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/athdrv_rexos.h" +#endif + +#endif /* _ADRV_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/a_drv_api.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/a_drv_api.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/a_drv_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/a_drv_api.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,198 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_DRV_API_H_ +#define _A_DRV_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************/ +/****************************************************************************/ +/** **/ +/** WMI related hooks **/ +/** **/ +/****************************************************************************/ +/****************************************************************************/ + +#include + +#define A_WMI_CHANNELLIST_RX(devt, numChan, chanList) \ + ar6000_channelList_rx((devt), (numChan), (chanList)) + +#define A_WMI_SET_NUMDATAENDPTS(devt, num) \ + ar6000_set_numdataendpts((devt), (num)) + +#define A_WMI_CONTROL_TX(devt, osbuf, streamID) \ + ar6000_control_tx((devt), (osbuf), (streamID)) + +#define A_WMI_TARGETSTATS_EVENT(devt, pStats) \ + ar6000_targetStats_event((devt), (pStats)) + +#define A_WMI_SCANCOMPLETE_EVENT(devt, status) \ + ar6000_scanComplete_event((devt), (status)) + +#ifdef CONFIG_HOST_DSET_SUPPORT + +#define A_WMI_DSET_DATA_REQ(devt, access_cookie, offset, length, targ_buf, targ_reply_fn, targ_reply_arg) \ + ar6000_dset_data_req((devt), (access_cookie), (offset), (length), (targ_buf), (targ_reply_fn), (targ_reply_arg)) + +#define A_WMI_DSET_CLOSE(devt, access_cookie) \ + ar6000_dset_close((devt), (access_cookie)) + +#endif + +#define A_WMI_DSET_OPEN_REQ(devt, id, targ_handle, targ_reply_fn, targ_reply_arg) \ + ar6000_dset_open_req((devt), (id), (targ_handle), (targ_reply_fn), (targ_reply_arg)) + +#define A_WMI_CONNECT_EVENT(devt, channel, bssid, listenInterval, beaconInterval, networkType, beaconIeLen, assocReqLen, assocRespLen, assocInfo) \ + ar6000_connect_event((devt), (channel), (bssid), (listenInterval), (beaconInterval), (networkType), (beaconIeLen), (assocReqLen), (assocRespLen), (assocInfo)) + +#define A_WMI_REGDOMAIN_EVENT(devt, regCode) \ + ar6000_regDomain_event((devt), (regCode)) + +#define A_WMI_NEIGHBORREPORT_EVENT(devt, numAps, info) \ + ar6000_neighborReport_event((devt), (numAps), (info)) + +#define A_WMI_DISCONNECT_EVENT(devt, reason, bssid, assocRespLen, assocInfo, protocolReasonStatus) \ + ar6000_disconnect_event((devt), (reason), (bssid), (assocRespLen), (assocInfo), (protocolReasonStatus)) + +#define A_WMI_TKIP_MICERR_EVENT(devt, keyid, ismcast) \ + ar6000_tkip_micerr_event((devt), (keyid), (ismcast)) + +#define A_WMI_BITRATE_RX(devt, rateKbps) \ + ar6000_bitrate_rx((devt), (rateKbps)) + +#define A_WMI_TXPWR_RX(devt, txPwr) \ + ar6000_txPwr_rx((devt), (txPwr)) + +#define A_WMI_READY_EVENT(devt, datap, phyCap, ver) \ + ar6000_ready_event((devt), (datap), (phyCap), (ver)) + +#define A_WMI_DBGLOG_INIT_DONE(ar) \ + ar6000_dbglog_init_done(ar); + +#define A_WMI_RSSI_THRESHOLD_EVENT(devt, newThreshold, rssi) \ + ar6000_rssiThreshold_event((devt), (newThreshold), (rssi)) + +#define A_WMI_REPORT_ERROR_EVENT(devt, errorVal) \ + ar6000_reportError_event((devt), (errorVal)) + +#define A_WMI_ROAM_TABLE_EVENT(devt, pTbl) \ + ar6000_roam_tbl_event((devt), (pTbl)) + +#define A_WMI_ROAM_DATA_EVENT(devt, p) \ + ar6000_roam_data_event((devt), (p)) + +#define A_WMI_WOW_LIST_EVENT(devt, num_filters, wow_filters) \ + ar6000_wow_list_event((devt), (num_filters), (wow_filters)) + +#define A_WMI_CAC_EVENT(devt, ac, cac_indication, statusCode, tspecSuggestion) \ + ar6000_cac_event((devt), (ac), (cac_indication), (statusCode), (tspecSuggestion)) + +#define A_WMI_CHANNEL_CHANGE_EVENT(devt, oldChannel, newChannel) \ + ar6000_channel_change_event((devt), (oldChannel), (newChannel)) + +#define A_WMI_PMKID_LIST_EVENT(devt, num_pmkid, pmkid_list, bssid_list) \ + ar6000_pmkid_list_event((devt), (num_pmkid), (pmkid_list), (bssid_list)) + +#ifdef CONFIG_HOST_GPIO_SUPPORT + +#define A_WMI_GPIO_INTR_RX(intr_mask, input_values) \ + ar6000_gpio_intr_rx((intr_mask), (input_values)) + +#define A_WMI_GPIO_DATA_RX(reg_id, value) \ + ar6000_gpio_data_rx((reg_id), (value)) + +#define A_WMI_GPIO_ACK_RX() \ + ar6000_gpio_ack_rx() + +#endif + +#ifdef SEND_EVENT_TO_APP + +#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) \ + ar6000_send_event_to_app((ar), (eventId), (datap), (len)) + +#else + +#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) + +#endif + +#ifdef CONFIG_HOST_TCMD_SUPPORT +#define A_WMI_TCMD_RX_REPORT_EVENT(devt, results, len) \ + ar6000_tcmd_rx_report_event((devt), (results), (len)) +#endif + +#define A_WMI_HBCHALLENGERESP_EVENT(devt, cookie, source) \ + ar6000_hbChallengeResp_event((devt), (cookie), (source)) + +#define A_WMI_TX_RETRY_ERR_EVENT(devt) \ + ar6000_tx_retry_err_event((devt)) + +#define A_WMI_SNR_THRESHOLD_EVENT_RX(devt, newThreshold, snr) \ + ar6000_snrThresholdEvent_rx((devt), (newThreshold), (snr)) + +#define A_WMI_LQ_THRESHOLD_EVENT_RX(devt, range, lqVal) \ + ar6000_lqThresholdEvent_rx((devt), (range), (lqVal)) + +#define A_WMI_RATEMASK_RX(devt, ratemask) \ + ar6000_ratemask_rx((devt), (ratemask)) + +#define A_WMI_KEEPALIVE_RX(devt, configured) \ + ar6000_keepalive_rx((devt), (configured)) + +#define A_WMI_BSSINFO_EVENT_RX(ar, datp, len) \ + ar6000_bssInfo_event_rx((ar), (datap), (len)) + +#define A_WMI_DBGLOG_EVENT(ar, dropped, buffer, length) \ + ar6000_dbglog_event((ar), (dropped), (buffer), (length)); + +#define A_WMI_STREAM_TX_ACTIVE(devt,trafficClass) \ + ar6000_indicate_tx_activity((devt),(trafficClass), TRUE) + +#define A_WMI_STREAM_TX_INACTIVE(devt,trafficClass) \ + ar6000_indicate_tx_activity((devt),(trafficClass), FALSE) +#define A_WMI_Ac2EndpointID(devht, ac)\ + ar6000_ac2_endpoint_id((devht), (ac)) + +#define A_WMI_Endpoint2Ac(devt, ep) \ + ar6000_endpoint_id2_ac((devt), (ep)) +/****************************************************************************/ +/****************************************************************************/ +/** **/ +/** HTC related hooks **/ +/** **/ +/****************************************************************************/ +/****************************************************************************/ + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +#define A_WMI_PROF_COUNT_RX(addr, count) prof_count_rx((addr), (count)) +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + +#ifdef __cplusplus +} +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/a_osapi.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/a_osapi.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/a_osapi.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/a_osapi.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,47 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions of the basic atheros data types. +// It is used to map the data types in atheros files to a platform specific +// type. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_OSAPI_H_ +#define _A_OSAPI_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "../os/linux/include/osapi_linux.h" +#endif + +#ifdef UNDER_CE +#include "../os/wince/include/osapi_wince.h" +#include "../os/wince/ndis/netbuf.h" +#if defined __cplusplus || defined __STDC__ +extern "C" +#endif +A_UINT32 a_copy_from_user(void *to, const void *from, A_UINT32 n); +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/osapi_rexos.h" +#endif + +#endif /* _OSAPI_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/a_types.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/a_types.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/a_types.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/a_types.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,42 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions of the basic atheros data types. +// It is used to map the data types in atheros files to a platform specific +// type. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_TYPES_H_ +#define _A_TYPES_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "../os/linux/include/athtypes_linux.h" +#endif + +#ifdef UNDER_CE +#include "../os/wince/include/athtypes_wince.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/athtypes_rexos.h" +#endif + +#endif /* _ATHTYPES_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/ar6000_api.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/ar6000_api.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/ar6000_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/ar6000_api.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,42 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the API to access the OS dependent atheros host driver +// by the WMI or WLAN generic modules. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _AR6000_API_H_ +#define _AR6000_API_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "../os/linux/include/ar6xapi_linux.h" +#endif + +#ifdef UNDER_CE +#include "../os/wince/include/ar6xapi_wince.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/ar6xapi_rexos.h" +#endif + +#endif /* _AR6000_API_H */ + diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/ar6000_diag.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/ar6000_diag.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/ar6000_diag.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/ar6000_diag.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,42 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef AR6000_DIAG_H_ +#define AR6000_DIAG_H_ + + +A_STATUS +ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS +ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS +ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length); + +A_STATUS +ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length); + +#endif /*AR6000_DIAG_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/ar6k.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/ar6k.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/ar6k.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/ar6k.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,199 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// AR6K device layer that handles register level I/O +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef AR6K_H_ +#define AR6K_H_ + +#define AR6K_MAILBOXES 4 + +/* HTC runs over mailbox 0 */ +#define HTC_MAILBOX 0 + +#define AR6K_TARGET_DEBUG_INTR_MASK 0x01 + +#define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK | \ + INT_STATUS_ENABLE_CPU_MASK | \ + INT_STATUS_ENABLE_COUNTER_MASK) + +//#define MBOXHW_UNIT_TEST 1 + +#include "athstartpack.h" +typedef PREPACK struct _AR6K_IRQ_PROC_REGISTERS { + A_UINT8 host_int_status; + A_UINT8 cpu_int_status; + A_UINT8 error_int_status; + A_UINT8 counter_int_status; + A_UINT8 mbox_frame; + A_UINT8 rx_lookahead_valid; + A_UINT8 hole[2]; + A_UINT32 rx_lookahead[2]; +} POSTPACK AR6K_IRQ_PROC_REGISTERS; + +#define AR6K_IRQ_PROC_REGS_SIZE sizeof(AR6K_IRQ_PROC_REGISTERS) + + + +typedef PREPACK struct _AR6K_IRQ_ENABLE_REGISTERS { + A_UINT8 int_status_enable; + A_UINT8 cpu_int_status_enable; + A_UINT8 error_status_enable; + A_UINT8 counter_int_status_enable; +} POSTPACK AR6K_IRQ_ENABLE_REGISTERS; + +#include "athendpack.h" + +#define AR6K_IRQ_ENABLE_REGS_SIZE sizeof(AR6K_IRQ_ENABLE_REGISTERS) + +#define AR6K_REG_IO_BUFFER_SIZE 32 +#define AR6K_MAX_REG_IO_BUFFERS 8 + +/* buffers for ASYNC I/O */ +typedef struct AR6K_ASYNC_REG_IO_BUFFER { + HTC_PACKET HtcPacket; /* we use an HTC packet as a wrapper for our async register-based I/O */ + A_UINT8 Buffer[AR6K_REG_IO_BUFFER_SIZE]; +} AR6K_ASYNC_REG_IO_BUFFER; + +typedef struct _AR6K_DEVICE { + A_MUTEX_T Lock; + AR6K_IRQ_PROC_REGISTERS IrqProcRegisters; + AR6K_IRQ_ENABLE_REGISTERS IrqEnableRegisters; + void *HIFDevice; + A_UINT32 BlockSize; + A_UINT32 BlockMask; + A_UINT32 MailboxAddress; + HIF_PENDING_EVENTS_FUNC GetPendingEventsFunc; + void *HTCContext; + HTC_PACKET_QUEUE RegisterIOList; + AR6K_ASYNC_REG_IO_BUFFER RegIOBuffers[AR6K_MAX_REG_IO_BUFFERS]; + void (*TargetFailureCallback)(void *Context); + A_STATUS (*MessagePendingCallback)(void *Context, A_UINT32 LookAhead, A_BOOL *pAsyncProc); + HIF_DEVICE_IRQ_PROCESSING_MODE HifIRQProcessingMode; + HIF_MASK_UNMASK_RECV_EVENT HifMaskUmaskRecvEvent; +} AR6K_DEVICE; + +#define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) ((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY) + +A_STATUS DevSetup(AR6K_DEVICE *pDev); +void DevCleanup(AR6K_DEVICE *pDev); +A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev, + A_UINT32 *pLookAhead, + int TimeoutMS); +A_STATUS DevRWCompletionHandler(void *context, A_STATUS status); +A_STATUS DevDsrHandler(void *context); +A_STATUS DevCheckPendingRecvMsgsAsync(void *context); +void DevDumpRegisters(AR6K_IRQ_PROC_REGISTERS *pIrqProcRegs, + AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs); + +#define DEV_STOP_RECV_ASYNC TRUE +#define DEV_STOP_RECV_SYNC FALSE +#define DEV_ENABLE_RECV_ASYNC TRUE +#define DEV_ENABLE_RECV_SYNC FALSE +A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode); +A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode); +A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev); + +static INLINE A_STATUS DevSendPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 SendLength) { + A_UINT32 paddedLength; + A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE; + A_STATUS status; + + /* adjust the length to be a multiple of block size if appropriate */ + paddedLength = (SendLength + (pDev->BlockMask)) & + (~(pDev->BlockMask)); +#if 0 // BufferLength may not be set in , fix this... + if (paddedLength > pPacket->BufferLength) { + AR_DEBUG_ASSERT(FALSE); + if (pPacket->Completion != NULL) { + COMPLETE_HTC_PACKET(pPacket,A_EINVAL); + } + return A_EINVAL; + } +#endif + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("DevSendPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n", + paddedLength, + pDev->MailboxAddress, + sync ? "SYNC" : "ASYNC")); + + status = HIFReadWrite(pDev->HIFDevice, + pDev->MailboxAddress, + pPacket->pBuffer, + paddedLength, /* the padded length */ + sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC, + sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */ + + if (sync) { + pPacket->Status = status; + } + + return status; +} + +static INLINE A_STATUS DevRecvPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 RecvLength) { + A_UINT32 paddedLength; + A_STATUS status; + A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE; + + /* adjust the length to be a multiple of block size if appropriate */ + paddedLength = (RecvLength + (pDev->BlockMask)) & + (~(pDev->BlockMask)); + if (paddedLength > pPacket->BufferLength) { + AR_DEBUG_ASSERT(FALSE); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("DevRecvPacket, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n", + paddedLength,RecvLength,pPacket->BufferLength)); + if (pPacket->Completion != NULL) { + COMPLETE_HTC_PACKET(pPacket,A_EINVAL); + } + return A_EINVAL; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("DevRecvPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n", + paddedLength, + pDev->MailboxAddress, + sync ? "SYNC" : "ASYNC")); + + status = HIFReadWrite(pDev->HIFDevice, + pDev->MailboxAddress, + pPacket->pBuffer, + paddedLength, + sync ? HIF_RD_SYNC_BLOCK_INC : HIF_RD_ASYNC_BLOCK_INC, + sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */ + + if (sync) { + pPacket->Status = status; + } + + return status; +} + +#ifdef MBOXHW_UNIT_TEST +A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev); +#endif + +#endif /*AR6K_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/athdefs.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/athdefs.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/athdefs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/athdefs.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,102 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef __ATHDEFS_H__ +#define __ATHDEFS_H__ + +/* + * This file contains definitions that may be used across both + * Host and Target software. Nothing here is module-dependent + * or platform-dependent. + */ + +/* + * Generic error codes that can be used by hw, sta, ap, sim, dk + * and any other environments. Since these are enums, feel free to + * add any more codes that you need. + */ + +typedef enum { + A_ERROR = -1, /* Generic error return */ + A_OK = 0, /* success */ + /* Following values start at 1 */ + A_DEVICE_NOT_FOUND, /* not able to find PCI device */ + A_NO_MEMORY, /* not able to allocate memory, not available */ + A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */ + A_NO_FREE_DESC, /* no free descriptors available */ + A_BAD_ADDRESS, /* address does not match descriptor */ + A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */ + A_REGS_NOT_MAPPED, /* registers not correctly mapped */ + A_EPERM, /* Not superuser */ + A_EACCES, /* Access denied */ + A_ENOENT, /* No such entry, search failed, etc. */ + A_EEXIST, /* The object already exists (can't create) */ + A_EFAULT, /* Bad address fault */ + A_EBUSY, /* Object is busy */ + A_EINVAL, /* Invalid parameter */ + A_EMSGSIZE, /* Inappropriate message buffer length */ + A_ECANCELED, /* Operation canceled */ + A_ENOTSUP, /* Operation not supported */ + A_ECOMM, /* Communication error on send */ + A_EPROTO, /* Protocol error */ + A_ENODEV, /* No such device */ + A_EDEVNOTUP, /* device is not UP */ + A_NO_RESOURCE, /* No resources for requested operation */ + A_HARDWARE, /* Hardware failure */ + A_PENDING, /* Asynchronous routine; will send up results la +ter (typically in callback) */ + A_EBADCHANNEL, /* The channel cannot be used */ + A_DECRYPT_ERROR, /* Decryption error */ + A_PHY_ERROR, /* RX PHY error */ + A_CONSUMED /* Object was consumed */ +} A_STATUS; + +#define A_SUCCESS(x) (x == A_OK) +#define A_FAILED(x) (!A_SUCCESS(x)) + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +/* + * The following definition is WLAN specific definition + */ +typedef enum { + MODE_11A = 0, /* 11a Mode */ + MODE_11G = 1, /* 11g + 11b Mode */ + MODE_11B = 2, /* 11b Mode */ + MODE_11GONLY = 3, /* 11g only Mode */ + MODE_UNKNOWN = 4, + MODE_MAX = 4 +} WLAN_PHY_MODE; + +typedef enum { + WLAN_11A_CAPABILITY = 1, + WLAN_11G_CAPABILITY = 2, + WLAN_11AG_CAPABILITY = 3, +}WLAN_CAPABILITY; + +#endif /* __ATHDEFS_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/athdrv.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/athdrv.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/athdrv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/athdrv.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,35 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _ATHDRV_H_ +#define _ATHDRV_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* _ATHDRV_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/athendpack.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/athendpack.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/athendpack.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/athendpack.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,44 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// end compiler-specific structure packing +// +// Author(s): ="Atheros" +//============================================================================== +#ifdef VXWORKS +#endif /* VXWORKS */ + +#ifdef LINUX +#endif /* LINUX */ + +#ifdef QNX +#endif /* QNX */ + +#ifdef INTEGRITY +#include "integrity/athendpack_integrity.h" +#endif /* INTEGRITY */ + +#ifdef NUCLEUS +#endif /* NUCLEUS */ + +#ifdef UNDER_CE +#include "../os/wince/include/athendpack_wince.h" +#endif /* WINCE */ + diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/athstartpack.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/athstartpack.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/athstartpack.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/athstartpack.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,44 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// start compiler-specific structure packing +// +// Author(s): ="Atheros" +//============================================================================== +#ifdef VXWORKS +#endif /* VXWORKS */ + +#ifdef LINUX +#endif /* LINUX */ + +#ifdef QNX +#endif /* QNX */ + +#ifdef INTEGRITY +#include "integrity/athstartpack_integrity.h" +#endif /* INTEGRITY */ + +#ifdef NUCLEUS +#endif /* NUCLEUS */ + +#ifdef UNDER_CE +#include "../os/wince/include/athstartpack_wince.h" +#endif /* WINCE */ + diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/bmi.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/bmi.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/bmi.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/bmi.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,115 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// BMI declarations and prototypes +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _BMI_H_ +#define _BMI_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Header files */ +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "hif.h" +#include "a_osapi.h" +#include "bmi_msg.h" + +void +BMIInit(void); + +A_STATUS +BMIDone(HIF_DEVICE *device); + +A_STATUS +BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info); + +A_STATUS +BMIReadMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length); + +A_STATUS +BMIWriteMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length); + +A_STATUS +BMIExecute(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param); + +A_STATUS +BMISetAppStart(HIF_DEVICE *device, + A_UINT32 address); + +A_STATUS +BMIReadSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param); + +A_STATUS +BMIWriteSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 param); + +A_STATUS +BMIrompatchInstall(HIF_DEVICE *device, + A_UINT32 ROM_addr, + A_UINT32 RAM_addr, + A_UINT32 nbytes, + A_UINT32 do_activate, + A_UINT32 *patch_id); + +A_STATUS +BMIrompatchUninstall(HIF_DEVICE *device, + A_UINT32 rompatch_id); + +A_STATUS +BMIrompatchActivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list); + +A_STATUS +BMIrompatchDeactivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list); + +A_STATUS +BMILZStreamStart(HIF_DEVICE *device, + A_UINT32 address); + +A_STATUS +BMILZData(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length); + +#ifdef __cplusplus +} +#endif + +#endif /* _BMI_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/bmi_internal.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/bmi_internal.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/bmi_internal.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/bmi_internal.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,50 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef BMI_INTERNAL_H +#define BMI_INTERNAL_H + +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "a_debug.h" +#include "AR6002/hw/mbox_host_reg.h" +#include "bmi_msg.h" + +#define BMI_COMMUNICATION_TIMEOUT 100000 + +/* ------ Global Variable Declarations ------- */ +A_BOOL bmiDone; + +A_STATUS +bmiBufferSend(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length); + +A_STATUS +bmiBufferReceive(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length); + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/bmi_msg.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/bmi_msg.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/bmi_msg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/bmi_msg.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,234 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __BMI_MSG_H__ +#define __BMI_MSG_H__ + +/* + * Bootloader Messaging Interface (BMI) + * + * BMI is a very simple messaging interface used during initialization + * to read memory, write memory, execute code, and to define an + * application entry PC. + * + * It is used to download an application to AR6K, to provide + * patches to code that is already resident on AR6K, and generally + * to examine and modify state. The Host has an opportunity to use + * BMI only once during bootup. Once the Host issues a BMI_DONE + * command, this opportunity ends. + * + * The Host writes BMI requests to mailbox0, and reads BMI responses + * from mailbox0. BMI requests all begin with a command + * (see below for specific commands), and are followed by + * command-specific data. + * + * Flow control: + * The Host can only issue a command once the Target gives it a + * "BMI Command Credit", using AR6K Counter #4. As soon as the + * Target has completed a command, it issues another BMI Command + * Credit (so the Host can issue the next command). + * + * BMI handles all required Target-side cache flushing. + */ + + +/* Maximum data size used for BMI transfers */ +#define BMI_DATASZ_MAX 256 + +/* BMI Commands */ + +#define BMI_NO_COMMAND 0 + +#define BMI_DONE 1 + /* + * Semantics: Host is done using BMI + * Request format: + * A_UINT32 command (BMI_DONE) + * Response format: none + */ + +#define BMI_READ_MEMORY 2 + /* + * Semantics: Host reads AR6K memory + * Request format: + * A_UINT32 command (BMI_READ_MEMORY) + * A_UINT32 address + * A_UINT32 length, at most BMI_DATASZ_MAX + * Response format: + * A_UINT8 data[length] + */ + +#define BMI_WRITE_MEMORY 3 + /* + * Semantics: Host writes AR6K memory + * Request format: + * A_UINT32 command (BMI_WRITE_MEMORY) + * A_UINT32 address + * A_UINT32 length, at most BMI_DATASZ_MAX + * A_UINT8 data[length] + * Response format: none + */ + +#define BMI_EXECUTE 4 + /* + * Semantics: Causes AR6K to execute code + * Request format: + * A_UINT32 command (BMI_EXECUTE) + * A_UINT32 address + * A_UINT32 parameter + * Response format: + * A_UINT32 return value + */ + +#define BMI_SET_APP_START 5 + /* + * Semantics: Set Target application starting address + * Request format: + * A_UINT32 command (BMI_SET_APP_START) + * A_UINT32 address + * Response format: none + */ + +#define BMI_READ_SOC_REGISTER 6 + /* + * Semantics: Read a 32-bit Target SOC register. + * Request format: + * A_UINT32 command (BMI_READ_REGISTER) + * A_UINT32 address + * Response format: + * A_UINT32 value + */ + +#define BMI_WRITE_SOC_REGISTER 7 + /* + * Semantics: Write a 32-bit Target SOC register. + * Request format: + * A_UINT32 command (BMI_WRITE_REGISTER) + * A_UINT32 address + * A_UINT32 value + * + * Response format: none + */ + +#define BMI_GET_TARGET_ID 8 +#define BMI_GET_TARGET_INFO 8 + /* + * Semantics: Fetch the 4-byte Target information + * Request format: + * A_UINT32 command (BMI_GET_TARGET_ID/INFO) + * Response format1 (old firmware): + * A_UINT32 TargetVersionID + * Response format2 (newer firmware): + * A_UINT32 TARGET_VERSION_SENTINAL + * struct bmi_target_info; + */ + +struct bmi_target_info { + A_UINT32 target_info_byte_count; /* size of this structure */ + A_UINT32 target_ver; /* Target Version ID */ + A_UINT32 target_type; /* Target type */ +}; +#define TARGET_VERSION_SENTINAL 0xffffffff +#define TARGET_TYPE_AR6001 1 +#define TARGET_TYPE_AR6002 2 + + +#define BMI_ROMPATCH_INSTALL 9 + /* + * Semantics: Install a ROM Patch. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_INSTALL) + * A_UINT32 Target ROM Address + * A_UINT32 Target RAM Address + * A_UINT32 Size, in bytes + * A_UINT32 Activate? 1-->activate; + * 0-->install but do not activate + * Response format: + * A_UINT32 PatchID + */ + +#define BMI_ROMPATCH_UNINSTALL 10 + /* + * Semantics: Uninstall a previously-installed ROM Patch, + * automatically deactivating, if necessary. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_UNINSTALL) + * A_UINT32 PatchID + * + * Response format: none + */ + +#define BMI_ROMPATCH_ACTIVATE 11 + /* + * Semantics: Activate a list of previously-installed ROM Patches. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_ACTIVATE) + * A_UINT32 rompatch_count + * A_UINT32 PatchID[rompatch_count] + * + * Response format: none + */ + +#define BMI_ROMPATCH_DEACTIVATE 12 + /* + * Semantics: Deactivate a list of active ROM Patches. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_DEACTIVATE) + * A_UINT32 rompatch_count + * A_UINT32 PatchID[rompatch_count] + * + * Response format: none + */ + + +#define BMI_LZ_STREAM_START 13 + /* + * Semantics: Begin an LZ-compressed stream of input + * which is to be uncompressed by the Target to an + * output buffer at address. The output buffer must + * be sufficiently large to hold the uncompressed + * output from the compressed input stream. This BMI + * command should be followed by a series of 1 or more + * BMI_LZ_DATA commands. + * A_UINT32 command (BMI_LZ_STREAM_START) + * A_UINT32 address + * Note: Not supported on all versions of ROM firmware. + */ + +#define BMI_LZ_DATA 14 + /* + * Semantics: Host writes AR6K memory with LZ-compressed + * data which is uncompressed by the Target. This command + * must be preceded by a BMI_LZ_STREAM_START command. A series + * of BMI_LZ_DATA commands are considered part of a single + * input stream until another BMI_LZ_STREAM_START is issued. + * Request format: + * A_UINT32 command (BMI_LZ_DATA) + * A_UINT32 length (of compressed data), + * at most BMI_DATASZ_MAX + * A_UINT8 CompressedData[length] + * Response format: none + * Note: Not supported on all versions of ROM firmware. + */ + +#endif /* __BMI_MSG_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/common_drv.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/common_drv.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/common_drv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/common_drv.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,79 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef COMMON_DRV_H_ +#define COMMON_DRV_H_ + +#include "hif.h" +#include "htc_packet.h" + +/* structure that is the state information for the default credit distribution callback + * drivers should instantiate (zero-init as well) this structure in their driver instance + * and pass it as a context to the HTC credit distribution functions */ +typedef struct _COMMON_CREDIT_STATE_INFO { + int TotalAvailableCredits; /* total credits in the system at startup */ + int CurrentFreeCredits; /* credits available in the pool that have not been + given out to endpoints */ + HTC_ENDPOINT_CREDIT_DIST *pLowestPriEpDist; /* pointer to the lowest priority endpoint dist struct */ +} COMMON_CREDIT_STATE_INFO; + + +/* HTC TX packet tagging definitions */ +#define AR6K_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED +#define AR6K_DATA_PKT_TAG (AR6K_CONTROL_PKT_TAG + 1) + +#define AR6002_VERSION_REV1 0x20000086 +#define AR6002_VERSION_REV2 0x20000188 + +#ifdef __cplusplus +extern "C" { +#endif + +/* OS-independent APIs */ +A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo); + +A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, A_UCHAR *data, A_UINT32 length); + +A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType, A_BOOL waitForCompletion); + +void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType); + +A_STATUS ar6000_reset_device_skipflash(HIF_DEVICE *hifDevice); + +A_STATUS ar6000_set_htc_params(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 MboxIsrYieldValue, + A_UINT8 HtcControlBuffers); + +A_STATUS ar6000_prepare_target(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 TargetVersion); + +#ifdef __cplusplus +} +#endif + +#endif /*COMMON_DRV_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/dbglog.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/dbglog.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/dbglog.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/dbglog.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,128 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _DBGLOG_H_ +#define _DBGLOG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define DBGLOG_TIMESTAMP_OFFSET 0 +#define DBGLOG_TIMESTAMP_MASK 0x0000FFFF /* Bit 0-15. Contains bit + 8-23 of the LF0 timer */ +#define DBGLOG_DBGID_OFFSET 16 +#define DBGLOG_DBGID_MASK 0x03FF0000 /* Bit 16-25 */ +#define DBGLOG_DBGID_NUM_MAX 256 /* Upper limit is width of mask */ + +#define DBGLOG_MODULEID_OFFSET 26 +#define DBGLOG_MODULEID_MASK 0x3C000000 /* Bit 26-29 */ +#define DBGLOG_MODULEID_NUM_MAX 16 /* Upper limit is width of mask */ + +/* + * Please ensure that the definition of any new module intrduced is captured + * between the DBGLOG_MODULEID_START and DBGLOG_MODULEID_END defines. The + * structure is required for the parser to correctly pick up the values for + * different modules. + */ +#define DBGLOG_MODULEID_START +#define DBGLOG_MODULEID_INF 0 +#define DBGLOG_MODULEID_WMI 1 +#define DBGLOG_MODULEID_CSERV 2 +#define DBGLOG_MODULEID_PM 3 +#define DBGLOG_MODULEID_TXRX_MGMTBUF 4 +#define DBGLOG_MODULEID_TXRX_TXBUF 5 +#define DBGLOG_MODULEID_TXRX_RXBUF 6 +#define DBGLOG_MODULEID_WOW 7 +#define DBGLOG_MODULEID_WHAL 8 +#define DBGLOG_MODULEID_DC 9 +#define DBGLOG_MODULEID_CO 10 +#define DBGLOG_MODULEID_RO 11 +#define DBGLOG_MODULEID_CM 12 +#define DBGLOG_MODULEID_TMR 13 +#define DBGLOG_MODULEID_END + +#define DBGLOG_NUM_ARGS_OFFSET 30 +#define DBGLOG_NUM_ARGS_MASK 0xC0000000 /* Bit 30-31 */ +#define DBGLOG_NUM_ARGS_MAX 2 /* Upper limit is width of mask */ + +#define DBGLOG_MODULE_LOG_ENABLE_OFFSET 0 +#define DBGLOG_MODULE_LOG_ENABLE_MASK 0x0000FFFF + +#define DBGLOG_REPORTING_ENABLED_OFFSET 16 +#define DBGLOG_REPORTING_ENABLED_MASK 0x00010000 + +#define DBGLOG_TIMESTAMP_RESOLUTION_OFFSET 17 +#define DBGLOG_TIMESTAMP_RESOLUTION_MASK 0x000E0000 + +#define DBGLOG_REPORT_SIZE_OFFSET 20 +#define DBGLOG_REPORT_SIZE_MASK 0x3FF00000 + +#define DBGLOG_LOG_BUFFER_SIZE 1500 + /* set the max length to 90 characters, even though the majority of the + * text here is 81 columns/chars per line or less.. + ***WARNING** this has to be >= to the number of columns in this file + * This file is parsed by the target logging tools */ +#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90 + +struct dbglog_buf_s { + struct dbglog_buf_s *next; + A_INT8 *buffer; + A_UINT32 bufsize; + A_UINT32 length; + A_UINT32 count; + A_UINT32 free; +}; + +struct dbglog_hdr_s { + struct dbglog_buf_s *dbuf; + A_UINT32 dropped; +}; + +struct dbglog_config_s { + A_UINT32 cfgvalid; /* Mask with valid config bits */ + union { + /* TODO: Take care of endianness */ + struct { + A_UINT32 mmask:16; /* Mask of modules with logging on */ + A_UINT32 rep:1; /* Reporting enabled or not */ + A_UINT32 tsr:3; /* Time stamp resolution. Def: 1 ms */ + A_UINT32 size:10; /* Report size in number of messages */ + A_UINT32 reserved:2; + } dbglog_config; + + A_UINT32 value; + } u; +}; + +#define cfgmmask u.dbglog_config.mmask +#define cfgrep u.dbglog_config.rep +#define cfgtsr u.dbglog_config.tsr +#define cfgsize u.dbglog_config.size +#define cfgvalue u.value + +#ifdef __cplusplus +} +#endif + +#endif /* _DBGLOG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/dbglog_api.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/dbglog_api.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/dbglog_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/dbglog_api.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains host side debug primitives. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _DBGLOG_API_H_ +#define _DBGLOG_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbglog.h" + +#define DBGLOG_HOST_LOG_BUFFER_SIZE DBGLOG_LOG_BUFFER_SIZE + +#define DBGLOG_GET_DBGID(arg) \ + ((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET) + +#define DBGLOG_GET_MODULEID(arg) \ + ((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET) + +#define DBGLOG_GET_NUMARGS(arg) \ + ((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET) + +#define DBGLOG_GET_TIMESTAMP(arg) \ + ((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET) + +#ifdef __cplusplus +} +#endif + +#endif /* _DBGLOG_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/dl_list.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/dl_list.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/dl_list.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/dl_list.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,118 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Double-link list definitions (adapted from Atheros SDIO stack) +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef __DL_LIST_H___ +#define __DL_LIST_H___ + +#define A_CONTAINING_STRUCT(address, struct_type, field_name)\ + ((struct_type *)((A_UINT32)(address) - (A_UINT32)(&((struct_type *)0)->field_name))) + +/* list functions */ +/* pointers for the list */ +typedef struct _DL_LIST { + struct _DL_LIST *pPrev; + struct _DL_LIST *pNext; +}DL_LIST, *PDL_LIST; +/* + * DL_LIST_INIT , initialize doubly linked list +*/ +#define DL_LIST_INIT(pList)\ + {(pList)->pPrev = pList; (pList)->pNext = pList;} + +#define DL_LIST_IS_EMPTY(pList) (((pList)->pPrev == (pList)) && ((pList)->pNext == (pList))) +#define DL_LIST_GET_ITEM_AT_HEAD(pList) (pList)->pNext +#define DL_LIST_GET_ITEM_AT_TAIL(pList) (pList)->pPrev +/* + * ITERATE_OVER_LIST pStart is the list, pTemp is a temp list member + * NOT: do not use this function if the items in the list are deleted inside the + * iteration loop +*/ +#define ITERATE_OVER_LIST(pStart, pTemp) \ + for((pTemp) =(pStart)->pNext; pTemp != (pStart); (pTemp) = (pTemp)->pNext) + + +/* safe iterate macro that allows the item to be removed from the list + * the iteration continues to the next item in the list + */ +#define ITERATE_OVER_LIST_ALLOW_REMOVE(pStart,pItem,st,offset) \ +{ \ + PDL_LIST pTemp; \ + pTemp = (pStart)->pNext; \ + while (pTemp != (pStart)) { \ + (pItem) = A_CONTAINING_STRUCT(pTemp,st,offset); \ + pTemp = pTemp->pNext; \ + +#define ITERATE_END }} + +/* + * DL_ListInsertTail - insert pAdd to the end of the list +*/ +static INLINE PDL_LIST DL_ListInsertTail(PDL_LIST pList, PDL_LIST pAdd) { + /* insert at tail */ + pAdd->pPrev = pList->pPrev; + pAdd->pNext = pList; + pList->pPrev->pNext = pAdd; + pList->pPrev = pAdd; + return pAdd; +} + +/* + * DL_ListInsertHead - insert pAdd into the head of the list +*/ +static INLINE PDL_LIST DL_ListInsertHead(PDL_LIST pList, PDL_LIST pAdd) { + /* insert at head */ + pAdd->pPrev = pList; + pAdd->pNext = pList->pNext; + pList->pNext->pPrev = pAdd; + pList->pNext = pAdd; + return pAdd; +} + +#define DL_ListAdd(pList,pItem) DL_ListInsertHead((pList),(pItem)) +/* + * DL_ListRemove - remove pDel from list +*/ +static INLINE PDL_LIST DL_ListRemove(PDL_LIST pDel) { + pDel->pNext->pPrev = pDel->pPrev; + pDel->pPrev->pNext = pDel->pNext; + /* point back to itself just to be safe, incase remove is called again */ + pDel->pNext = pDel; + pDel->pPrev = pDel; + return pDel; +} + +/* + * DL_ListRemoveItemFromHead - get a list item from the head +*/ +static INLINE PDL_LIST DL_ListRemoveItemFromHead(PDL_LIST pList) { + PDL_LIST pItem = NULL; + if (pList->pNext != pList) { + pItem = pList->pNext; + /* remove the first item from head */ + DL_ListRemove(pItem); + } + return pItem; +} + +#endif /* __DL_LIST_H___ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/dset_api.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/dset_api.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/dset_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/dset_api.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,65 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Host-side DataSet API. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _DSET_API_H_ +#define _DSET_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* + * Host-side DataSet support is optional, and is not + * currently required for correct operation. To disable + * Host-side DataSet support, set this to 0. + */ +#ifndef CONFIG_HOST_DSET_SUPPORT +#define CONFIG_HOST_DSET_SUPPORT 1 +#endif + +/* Called to send a DataSet Open Reply back to the Target. */ +A_STATUS wmi_dset_open_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT32 access_cookie, + A_UINT32 size, + A_UINT32 version, + A_UINT32 targ_handle, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); + +/* Called to send a DataSet Data Reply back to the Target. */ +A_STATUS wmi_dset_data_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT8 *host_buf, + A_UINT32 length, + A_UINT32 targ_buf, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* _DSET_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/gpio.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/gpio.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/gpio.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/gpio.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,49 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2005 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#if defined(AR6001) +#define GPIO_PIN_COUNT 18 +#else +#define GPIO_PIN_COUNT 18 +#endif + +/* + * Possible values for WMIX_GPIO_SET_REGISTER_CMDID. + * NB: These match hardware order, so that addresses can + * easily be computed. + */ +#define GPIO_ID_OUT 0x00000000 +#define GPIO_ID_OUT_W1TS 0x00000001 +#define GPIO_ID_OUT_W1TC 0x00000002 +#define GPIO_ID_ENABLE 0x00000003 +#define GPIO_ID_ENABLE_W1TS 0x00000004 +#define GPIO_ID_ENABLE_W1TC 0x00000005 +#define GPIO_ID_IN 0x00000006 +#define GPIO_ID_STATUS 0x00000007 +#define GPIO_ID_STATUS_W1TS 0x00000008 +#define GPIO_ID_STATUS_W1TC 0x00000009 +#define GPIO_ID_PIN0 0x0000000a +#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) + +#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(17) +#define GPIO_ID_NONE 0xffffffff diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/gpio_api.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/gpio_api.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/gpio_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/gpio_api.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,59 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Host-side General Purpose I/O API. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _GPIO_API_H_ +#define _GPIO_API_H_ + +/* + * Send a command to the Target in order to change output on GPIO pins. + */ +A_STATUS wmi_gpio_output_set(struct wmi_t *wmip, + A_UINT32 set_mask, + A_UINT32 clear_mask, + A_UINT32 enable_mask, + A_UINT32 disable_mask); + +/* + * Send a command to the Target requesting input state of GPIO pins. + */ +A_STATUS wmi_gpio_input_get(struct wmi_t *wmip); + +/* + * Send a command to the Target to change the value of a GPIO register. + */ +A_STATUS wmi_gpio_register_set(struct wmi_t *wmip, + A_UINT32 gpioreg_id, + A_UINT32 value); + +/* + * Send a command to the Target to fetch the value of a GPIO register. + */ +A_STATUS wmi_gpio_register_get(struct wmi_t *wmip, A_UINT32 gpioreg_id); + +/* + * Send a command to the Target, acknowledging some GPIO interrupts. + */ +A_STATUS wmi_gpio_intr_ack(struct wmi_t *wmip, A_UINT32 ack_mask); + +#endif /* _GPIO_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/hif.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/hif.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/hif.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/hif.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,317 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// HIF specific declarations and prototypes +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HIF_H_ +#define _HIF_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Header files */ +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" + +typedef struct htc_callbacks HTC_CALLBACKS; +typedef struct hif_device HIF_DEVICE; + +/* + * direction - Direction of transfer (HIF_READ/HIF_WRITE). + */ +#define HIF_READ 0x00000001 +#define HIF_WRITE 0x00000002 +#define HIF_DIR_MASK (HIF_READ | HIF_WRITE) + +/* + * type - An interface may support different kind of read/write commands. + * For example: SDIO supports CMD52/CMD53s. In case of MSIO it + * translates to using different kinds of TPCs. The command type + * is thus divided into a basic and an extended command and can + * be specified using HIF_BASIC_IO/HIF_EXTENDED_IO. + */ +#define HIF_BASIC_IO 0x00000004 +#define HIF_EXTENDED_IO 0x00000008 +#define HIF_TYPE_MASK (HIF_BASIC_IO | HIF_EXTENDED_IO) + +/* + * emode - This indicates the whether the command is to be executed in a + * blocking or non-blocking fashion (HIF_SYNCHRONOUS/ + * HIF_ASYNCHRONOUS). The read/write data paths in HTC have been + * implemented using the asynchronous mode allowing the the bus + * driver to indicate the completion of operation through the + * registered callback routine. The requirement primarily comes + * from the contexts these operations get called from (a driver's + * transmit context or the ISR context in case of receive). + * Support for both of these modes is essential. + */ +#define HIF_SYNCHRONOUS 0x00000010 +#define HIF_ASYNCHRONOUS 0x00000020 +#define HIF_EMODE_MASK (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS) + +/* + * dmode - An interface may support different kinds of commands based on + * the tradeoff between the amount of data it can carry and the + * setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/ + * HIF_BLOCK_BASIS). In case of latter, the data is rounded off + * to the nearest block size by padding. The size of the block is + * configurable at compile time using the HIF_BLOCK_SIZE and is + * negotiated with the target during initialization after the + * AR6000 interrupts are enabled. + */ +#define HIF_BYTE_BASIS 0x00000040 +#define HIF_BLOCK_BASIS 0x00000080 +#define HIF_DMODE_MASK (HIF_BYTE_BASIS | HIF_BLOCK_BASIS) + +/* + * amode - This indicates if the address has to be incremented on AR6000 + * after every read/write operation (HIF?FIXED_ADDRESS/ + * HIF_INCREMENTAL_ADDRESS). + */ +#define HIF_FIXED_ADDRESS 0x00000100 +#define HIF_INCREMENTAL_ADDRESS 0x00000200 +#define HIF_AMODE_MASK (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS) + +#define HIF_WR_ASYNC_BYTE_FIX \ + (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_WR_ASYNC_BYTE_INC \ + (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_WR_ASYNC_BLOCK_INC \ + (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_WR_SYNC_BYTE_FIX \ + (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_WR_SYNC_BYTE_INC \ + (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_WR_SYNC_BLOCK_INC \ + (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_SYNC_BYTE_INC \ + (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_SYNC_BYTE_FIX \ + (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_RD_ASYNC_BYTE_FIX \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_RD_ASYNC_BLOCK_FIX \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS) +#define HIF_RD_ASYNC_BYTE_INC \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_ASYNC_BLOCK_INC \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_SYNC_BLOCK_INC \ + (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) + + +typedef enum { + HIF_DEVICE_POWER_STATE = 0, + HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + HIF_DEVICE_GET_MBOX_ADDR, + HIF_DEVICE_GET_PENDING_EVENTS_FUNC, + HIF_DEVICE_GET_IRQ_PROC_MODE, + HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC, + HIF_DEVICE_POWER_STATE_CHANGE, +} HIF_DEVICE_CONFIG_OPCODE; + +/* + * HIF CONFIGURE definitions: + * + * HIF_DEVICE_GET_MBOX_BLOCK_SIZE + * input : none + * output : array of 4 A_UINT32s + * notes: block size is returned for each mailbox (4) + * + * HIF_DEVICE_GET_MBOX_ADDR + * input : none + * output : array of 4 A_UINT32 + * notes: address is returned for each mailbox (4) in the array + * + * HIF_DEVICE_GET_PENDING_EVENTS_FUNC + * input : none + * output: HIF_PENDING_EVENTS_FUNC function pointer + * notes: this is optional for the HIF layer, if the request is + * not handled then it indicates that the upper layer can use + * the standard device methods to get pending events (IRQs, mailbox messages etc..) + * otherwise it can call the function pointer to check pending events. + * + * HIF_DEVICE_GET_IRQ_PROC_MODE + * input : none + * output : HIF_DEVICE_IRQ_PROCESSING_MODE (interrupt processing mode) + * note: the hif layer interfaces with the underlying OS-specific bus driver. The HIF + * layer can report whether IRQ processing is requires synchronous behavior or + * can be processed using asynchronous bus requests (typically faster). + * + * HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC + * input : + * output : HIF_MASK_UNMASK_RECV_EVENT function pointer + * notes: this is optional for the HIF layer. The HIF layer may require a special mechanism + * to mask receive message events. The upper layer can call this pointer when it needs + * to mask/unmask receive events (in case it runs out of buffers). + * + * HIF_DEVICE_POWER_STATE_CHANGE + * + * input : HIF_DEVICE_POWER_CHANGE_TYPE + * output : none + * note: this is optional for the HIF layer. The HIF layer can handle power on/off state change + * requests in an interconnect specific way. This is highly OS and bus driver dependent. + * The caller must guarantee that no HIF read/write requests will be made after the device + * is powered down. + * + * + * + */ + +typedef enum { + HIF_DEVICE_IRQ_SYNC_ONLY, /* for HIF implementations that require the DSR to process all + interrupts before returning */ + HIF_DEVICE_IRQ_ASYNC_SYNC, /* for HIF implementations that allow DSR to process interrupts + using ASYNC I/O (that is HIFAckInterrupt can be called at a + later time */ +} HIF_DEVICE_IRQ_PROCESSING_MODE; + +typedef enum { + HIF_DEVICE_POWER_UP, /* HIF layer should power up interface and/or module */ + HIF_DEVICE_POWER_DOWN, /* HIF layer should initiate bus-specific measures to minimize power */ + HIF_DEVICE_POWER_CUT /* HIF layer should initiate bus-specific AND/OR platform-specific measures + to completely power-off the module and associated hardware (i.e. cut power supplies) + */ +} HIF_DEVICE_POWER_CHANGE_TYPE; + +#define HIF_MAX_DEVICES 1 + +struct htc_callbacks { + A_UCHAR *name; + A_UINT32 id; + A_STATUS (* deviceInsertedHandler)(void *hif_handle); + A_STATUS (* deviceRemovedHandler)(void *htc_handle, A_STATUS status); + A_STATUS (* deviceSuspendHandler)(void *htc_handle); + A_STATUS (* deviceResumeHandler)(void *htc_handle); + A_STATUS (* deviceWakeupHandler)(void *htc_handle); + A_STATUS (* rwCompletionHandler)(void *context, A_STATUS status); + A_STATUS (* dsrHandler)(void *htc_handle); +}; + + +#define HIF_OTHER_EVENTS (1 << 0) /* other interrupts (non-Recv) are pending, host + needs to read the register table to figure out what */ +#define HIF_RECV_MSG_AVAIL (1 << 1) /* pending recv packet */ + +typedef struct _HIF_PENDING_EVENTS_INFO { + A_UINT32 Events; + A_UINT32 LookAhead; +} HIF_PENDING_EVENTS_INFO; + + /* function to get pending events , some HIF modules use special mechanisms + * to detect packet available and other interrupts */ +typedef A_STATUS ( *HIF_PENDING_EVENTS_FUNC)(HIF_DEVICE *device, + HIF_PENDING_EVENTS_INFO *pEvents, + void *AsyncContext); + +#define HIF_MASK_RECV TRUE +#define HIF_UNMASK_RECV FALSE + /* function to mask recv events */ +typedef A_STATUS ( *HIF_MASK_UNMASK_RECV_EVENT)(HIF_DEVICE *device, + A_BOOL Mask, + void *AsyncContext); + + +/* + * This API is used by the HTC layer to initialize the HIF layer and to + * register different callback routines. Support for following events has + * been captured - DSR, Read/Write completion, Device insertion/removal, + * Device suspension/resumption/wakeup. In addition to this, the API is + * also used to register the name and the revision of the chip. The latter + * can be used to verify the revision of the chip read from the device + * before reporting it to HTC. + */ +int HIFInit(HTC_CALLBACKS *callbacks); + +/* + * This API is used to provide the read/write interface over the specific bus + * interface. + * address - Starting address in the AR6000's address space. For mailbox + * writes, it refers to the start of the mbox boundary. It should + * be ensured that the last byte falls on the mailbox's EOM. For + * mailbox reads, it refers to the end of the mbox boundary. + * buffer - Pointer to the buffer containg the data to be transmitted or + * received. + * length - Amount of data to be transmitted or received. + * request - Characterizes the attributes of the command. + */ +A_STATUS +HIFReadWrite(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length, + A_UINT32 request, + void *context); + +/* + * This can be initiated from the unload driver context ie when the HTCShutdown + * routine is called. + */ +void HIFShutDownDevice(HIF_DEVICE *device); + +/* + * This should translate to an acknowledgment to the bus driver indicating that + * the previous interrupt request has been serviced and the all the relevant + * sources have been cleared. HTC is ready to process more interrupts. + * This should prevent the bus driver from raising an interrupt unless the + * previous one has been serviced and acknowledged using the previous API. + */ +void HIFAckInterrupt(HIF_DEVICE *device); + +void HIFMaskInterrupt(HIF_DEVICE *device); + +void HIFUnMaskInterrupt(HIF_DEVICE *device); + +/* + * This set of functions are to be used by the bus driver to notify + * the HIF module about various events. + * These are not implemented if the bus driver provides an alternative + * way for this notification though callbacks for instance. + */ +int HIFInsertEventNotify(void); + +int HIFRemoveEventNotify(void); + +int HIFIRQEventNotify(void); + +int HIFRWCompleteEventNotify(void); + +/* + * This function associates a opaque handle with the HIF layer + * to be used in communication with upper layer i.e. HTC. + * This would normaly be a pointer to htc_target data structure. + */ +void HIFSetHandle(void *hif_handle, void *handle); + +A_STATUS +HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode, + void *config, A_UINT32 configLen); + + +#ifdef __cplusplus +} +#endif + +#endif /* _HIF_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/hif_internal.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/hif_internal.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/hif_internal.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/hif_internal.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,88 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// internal header file for hif layer +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "hif.h" + +#define MANUFACTURER_ID_AR6001_BASE 0x100 +#define MANUFACTURER_ID_AR6002_BASE 0x200 +#define MANUFACTURER_ID_AR6003_BASE 0x300 +#define FUNCTION_CLASS 0x0 +#define MANUFACTURER_CODE 0x271 + +#define BUS_REQUEST_MAX_NUM 64 + +#define SDIO_CLOCK_FREQUENCY_DEFAULT 25000000 +#define SDWLAN_ENABLE_DISABLE_TIMEOUT 20 +#define FLAGS_CARD_ENAB 0x02 +#define FLAGS_CARD_IRQ_UNMSK 0x04 + +#define HIF_MBOX_BLOCK_SIZE 128 +#define HIF_MBOX_BASE_ADDR 0x800 +#define HIF_MBOX_WIDTH 0x800 +#define HIF_MBOX0_BLOCK_SIZE 1 +#define HIF_MBOX1_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE +#define HIF_MBOX2_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE +#define HIF_MBOX3_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE + +#define HIF_MBOX_START_ADDR(mbox) \ + HIF_MBOX_BASE_ADDR + mbox * HIF_MBOX_WIDTH + +#define HIF_MBOX_END_ADDR(mbox) \ + HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1 + +typedef struct bus_request { + struct bus_request *next; /* link list of available requests */ + struct bus_request *inusenext; /* link list of in use requests */ + struct compat_semaphore sem_req; + A_UINT32 address; /* request data */ + A_UCHAR *buffer; + A_UINT32 length; + A_UINT32 request; + void *context; + A_STATUS status; +} BUS_REQUEST; + +struct hif_device { + struct sdio_func *func; + void *htc_handle; + spinlock_t asynclock; + struct task_struct* async_task; /* task to handle async commands */ + struct compat_semaphore sem_async; /* wake up for async task */ + int async_shutdown; /* stop the async task */ + struct completion async_completion; /* thread completion */ + BUS_REQUEST *asyncreq; /* request for async tasklet */ + BUS_REQUEST *taskreq; /* async tasklet data */ + spinlock_t lock; + BUS_REQUEST *s_busRequestFreeQueue; /* free list */ + BUS_REQUEST busRequest[BUS_REQUEST_MAX_NUM]; /* available bus requests */ + A_UINT8 *dma_buffer; +}; + +#define HIF_DMA_BUFFER_SIZE (32 * 1024) +#define CMD53_FIXED_ADDRESS 1 +#define CMD53_INCR_ADDRESS 2 diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/host_version.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/host_version.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/host_version.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/host_version.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains version information for the sample host driver for the +// AR6000 chip +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HOST_VERSION_H_ +#define _HOST_VERSION_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* + * The version number is made up of major, minor, patch and build + * numbers. These are 16 bit numbers. The build and release script will + * set the build number using a Perforce counter. Here the build number is + * set to 9999 so that builds done without the build-release script are easily + * identifiable. + */ + +#define ATH_SW_VER_MAJOR __VER_MAJOR_ +#define ATH_SW_VER_MINOR __VER_MINOR_ +#define ATH_SW_VER_PATCH __VER_PATCH_ +#define ATH_SW_VER_BUILD __BUILD_NUMBER_ + +#ifdef __cplusplus +} +#endif + +#endif /* _HOST_VERSION_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/htc.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/htc.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/htc.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/htc.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,204 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __HTC_H__ +#define __HTC_H__ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field)) + +#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \ + (((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)])) + +/* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a + * structure using only the type and field name. + * Use these macros if there is the potential for unaligned buffer accesses. */ +#define A_GET_UINT16_FIELD(p,type,field) \ + ASSEMBLE_UNALIGNED_UINT16(p,\ + A_OFFSETOF(type,field) + 1, \ + A_OFFSETOF(type,field)) + +#define A_SET_UINT16_FIELD(p,type,field,value) \ +{ \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (A_UINT8)(value); \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field) + 1] = (A_UINT8)((value) >> 8); \ +} + +#define A_GET_UINT8_FIELD(p,type,field) \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] + +#define A_SET_UINT8_FIELD(p,type,field,value) \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (value) + +/****** DANGER DANGER *************** + * + * The frame header length and message formats defined herein were + * selected to accommodate optimal alignment for target processing. This reduces code + * size and improves performance. + * + * Any changes to the header length may alter the alignment and cause exceptions + * on the target. When adding to the message structures insure that fields are + * properly aligned. + * + */ + +/* HTC frame header */ +typedef PREPACK struct _HTC_FRAME_HDR{ + /* do not remove or re-arrange these fields, these are minimally required + * to take advantage of 4-byte lookaheads in some hardware implementations */ + A_UINT8 EndpointID; + A_UINT8 Flags; + A_UINT16 PayloadLen; /* length of data (including trailer) that follows the header */ + + /***** end of 4-byte lookahead ****/ + + A_UINT8 ControlBytes[2]; + + /* message payload starts after the header */ + +} POSTPACK HTC_FRAME_HDR; + +/* frame header flags */ +#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0) +#define HTC_FLAGS_RECV_TRAILER (1 << 1) + + +#define HTC_HDR_LENGTH (sizeof(HTC_FRAME_HDR)) +#define HTC_MAX_TRAILER_LENGTH 255 +#define HTC_MAX_PAYLOAD_LENGTH (2048 - sizeof(HTC_FRAME_HDR)) + +/* HTC control message IDs */ +typedef enum { + HTC_MSG_READY_ID = 1, + HTC_MSG_CONNECT_SERVICE_ID = 2, + HTC_MSG_CONNECT_SERVICE_RESPONSE_ID = 3, + HTC_MSG_SETUP_COMPLETE_ID = 4, +} HTC_MSG_IDS; + +#define HTC_MAX_CONTROL_MESSAGE_LENGTH 256 + +/* base message ID header */ +typedef PREPACK struct { + A_UINT16 MessageID; +} POSTPACK HTC_UNKNOWN_MSG; + +/* HTC ready message + * direction : target-to-host */ +typedef PREPACK struct { + A_UINT16 MessageID; /* ID */ + A_UINT16 CreditCount; /* number of credits the target can offer */ + A_UINT16 CreditSize; /* size of each credit */ + A_UINT8 MaxEndpoints; /* maximum number of endpoints the target has resources for */ + A_UINT8 _Pad1; +} POSTPACK HTC_READY_MSG; + +#define HTC_SERVICE_META_DATA_MAX_LENGTH 128 + +/* connect service + * direction : host-to-target */ +typedef PREPACK struct { + A_UINT16 MessageID; + A_UINT16 ServiceID; /* service ID of the service to connect to */ + A_UINT16 ConnectionFlags; /* connection flags */ + +#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) /* reduce credit dribbling when + the host needs credits */ +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3) +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3 + + A_UINT8 ServiceMetaLength; /* length of meta data that follows */ + A_UINT8 _Pad1; + + /* service-specific meta data starts after the header */ + +} POSTPACK HTC_CONNECT_SERVICE_MSG; + +/* connect response + * direction : target-to-host */ +typedef PREPACK struct { + A_UINT16 MessageID; + A_UINT16 ServiceID; /* service ID that the connection request was made */ + A_UINT8 Status; /* service connection status */ + A_UINT8 EndpointID; /* assigned endpoint ID */ + A_UINT16 MaxMsgSize; /* maximum expected message size on this endpoint */ + A_UINT8 ServiceMetaLength; /* length of meta data that follows */ + A_UINT8 _Pad1; + + /* service-specific meta data starts after the header */ + +} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG; + +typedef PREPACK struct { + A_UINT16 MessageID; + /* currently, no other fields */ +} POSTPACK HTC_SETUP_COMPLETE_MSG; + + +/* connect response status codes */ +#define HTC_SERVICE_SUCCESS 0 /* success */ +#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */ +#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */ +#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */ +#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more + endpoints */ + +/* report record IDs */ +typedef enum { + HTC_RECORD_NULL = 0, + HTC_RECORD_CREDITS = 1, + HTC_RECORD_LOOKAHEAD = 2, +} HTC_RPT_IDS; + +typedef PREPACK struct { + A_UINT8 RecordID; /* Record ID */ + A_UINT8 Length; /* Length of record */ +} POSTPACK HTC_RECORD_HDR; + +typedef PREPACK struct { + A_UINT8 EndpointID; /* Endpoint that owns these credits */ + A_UINT8 Credits; /* credits to report since last report */ +} POSTPACK HTC_CREDIT_REPORT; + +typedef PREPACK struct { + A_UINT8 PreValid; /* pre valid guard */ + A_UINT8 LookAhead[4]; /* 4 byte lookahead */ + A_UINT8 PostValid; /* post valid guard */ + + /* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes. + * The PreValid bytes must equal the inverse of the PostValid byte */ + +} POSTPACK HTC_LOOKAHEAD_REPORT; + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + + +#endif /* __HTC_H__ */ + diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/htc_api.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/htc_api.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/htc_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/htc_api.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,474 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HTC_API_H_ +#define _HTC_API_H_ + +#include +#include +#include "htc_packet.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* TODO.. for BMI */ +#define ENDPOINT1 0 +// TODO -remove me, but we have to fix BMI first +#define HTC_MAILBOX_NUM_MAX 4 + +/* this is the amount of header room required by users of HTC */ +#define HTC_HEADER_LEN HTC_HDR_LENGTH + +typedef void *HTC_HANDLE; + +typedef A_UINT16 HTC_SERVICE_ID; + +typedef struct _HTC_INIT_INFO { + void (*AddInstance)(HTC_HANDLE); + void (*DeleteInstance)(void *Instance); + void (*TargetFailure)(void *Instance, A_STATUS Status); +} HTC_INIT_INFO; + +/* per service connection send completion */ +typedef void (*HTC_EP_SEND_PKT_COMPLETE)(void *,HTC_PACKET *); +/* per service connection pkt received */ +typedef void (*HTC_EP_RECV_PKT)(void *,HTC_PACKET *); + +/* Optional per service connection receive buffer re-fill callback, + * On some OSes (like Linux) packets are allocated from a global pool and indicated up + * to the network stack. The driver never gets the packets back from the OS. For these OSes + * a refill callback can be used to allocate and re-queue buffers into HTC. + * + * On other OSes, the network stack can call into the driver's OS-specifc "return_packet" handler and + * the driver can re-queue these buffers into HTC. In this regard a refill callback is + * unnecessary */ +typedef void (*HTC_EP_RECV_REFILL)(void *, HTC_ENDPOINT_ID Endpoint); + +/* Optional per service connection receive buffer allocation callback. + * On some systems packet buffers are an extremely limited resource. Rather than + * queue largest-possible-sized buffers to HTC, some systems would rather + * allocate a specific size as the packet is received. The trade off is + * slightly more processing (callback invoked for each RX packet) + * for the benefit of committing fewer buffer resources into HTC. + * + * The callback is provided the length of the pending packet to fetch. This includes the + * HTC header length plus the length of payload. The callback can return a pointer to + * the allocated HTC packet for immediate use. + * + * NOTE*** This callback is mutually exclusive with the the refill callback above. + * + * */ +typedef HTC_PACKET *(*HTC_EP_RECV_ALLOC)(void *, HTC_ENDPOINT_ID Endpoint, int Length); + +typedef enum _HTC_SEND_FULL_ACTION { + HTC_SEND_FULL_KEEP = 0, /* packet that overflowed should be kept in the queue */ + HTC_SEND_FULL_DROP = 1, /* packet that overflowed should be dropped */ +} HTC_SEND_FULL_ACTION; + +/* Optional per service connection callback when a send queue is full. This can occur if the + * host continues queueing up TX packets faster than credits can arrive + * To prevent the host (on some Oses like Linux) from continuously queueing packets + * and consuming resources, this callback is provided so that that the host + * can disable TX in the subsystem (i.e. network stack). + * This callback is invoked for each packet that "overflows" the HTC queue. The callback can + * determine whether the new packet that overflowed the queue can be kept (HTC_SEND_FULL_KEEP) or + * dropped (HTC_SEND_FULL_DROP). If a packet is dropped, the EpTxComplete handler will be called + * and the packet's status field will be set to A_NO_RESOURCE. + * Other OSes require a "per-packet" indication for each completed TX packet, this + * closed loop mechanism will prevent the network stack from overunning the NIC + * The packet to keep or drop is passed for inspection to the registered handler the handler + * must ONLY inspect the packet, it may not free or reclaim the packet. */ +typedef HTC_SEND_FULL_ACTION (*HTC_EP_SEND_QUEUE_FULL)(void *, HTC_PACKET *pPacket); + +typedef struct _HTC_EP_CALLBACKS { + void *pContext; /* context for each callback */ + HTC_EP_SEND_PKT_COMPLETE EpTxComplete; /* tx completion callback for connected endpoint */ + HTC_EP_RECV_PKT EpRecv; /* receive callback for connected endpoint */ + HTC_EP_RECV_REFILL EpRecvRefill; /* OPTIONAL receive re-fill callback for connected endpoint */ + HTC_EP_SEND_QUEUE_FULL EpSendFull; /* OPTIONAL send full callback */ + HTC_EP_RECV_ALLOC EpRecvAlloc; /* OPTIONAL recv allocation callback */ +} HTC_EP_CALLBACKS; + +/* service connection information */ +typedef struct _HTC_SERVICE_CONNECT_REQ { + HTC_SERVICE_ID ServiceID; /* service ID to connect to */ + A_UINT16 ConnectionFlags; /* connection flags, see htc protocol definition */ + A_UINT8 *pMetaData; /* ptr to optional service-specific meta-data */ + A_UINT8 MetaDataLength; /* optional meta data length */ + HTC_EP_CALLBACKS EpCallbacks; /* endpoint callbacks */ + int MaxSendQueueDepth; /* maximum depth of any send queue */ +} HTC_SERVICE_CONNECT_REQ; + +/* service connection response information */ +typedef struct _HTC_SERVICE_CONNECT_RESP { + A_UINT8 *pMetaData; /* caller supplied buffer to optional meta-data */ + A_UINT8 BufferLength; /* length of caller supplied buffer */ + A_UINT8 ActualLength; /* actual length of meta data */ + HTC_ENDPOINT_ID Endpoint; /* endpoint to communicate over */ + int MaxMsgLength; /* max length of all messages over this endpoint */ + A_UINT8 ConnectRespCode; /* connect response code from target */ +} HTC_SERVICE_CONNECT_RESP; + +/* endpoint distribution structure */ +typedef struct _HTC_ENDPOINT_CREDIT_DIST { + struct _HTC_ENDPOINT_CREDIT_DIST *pNext; + struct _HTC_ENDPOINT_CREDIT_DIST *pPrev; + HTC_SERVICE_ID ServiceID; /* Service ID (set by HTC) */ + HTC_ENDPOINT_ID Endpoint; /* endpoint for this distribution struct (set by HTC) */ + A_UINT32 DistFlags; /* distribution flags, distribution function can + set default activity using SET_EP_ACTIVE() macro */ + int TxCreditsNorm; /* credits for normal operation, anything above this + indicates the endpoint is over-subscribed, this field + is only relevant to the credit distribution function */ + int TxCreditsMin; /* floor for credit distribution, this field is + only relevant to the credit distribution function */ + int TxCreditsAssigned; /* number of credits assigned to this EP, this field + is only relevant to the credit dist function */ + int TxCredits; /* current credits available, this field is used by + HTC to determine whether a message can be sent or + must be queued */ + int TxCreditsToDist; /* pending credits to distribute on this endpoint, this + is set by HTC when credit reports arrive. + The credit distribution functions sets this to zero + when it distributes the credits */ + int TxCreditsSeek; /* this is the number of credits that the current pending TX + packet needs to transmit. This is set by HTC when + and endpoint needs credits in order to transmit */ + int TxCreditSize; /* size in bytes of each credit (set by HTC) */ + int TxCreditsPerMaxMsg; /* credits required for a maximum sized messages (set by HTC) */ + void *pHTCReserved; /* reserved for HTC use */ +} HTC_ENDPOINT_CREDIT_DIST; + +#define HTC_EP_ACTIVE ((A_UINT32) (1 << 31)) + +/* macro to check if an endpoint has gone active, useful for credit + * distributions */ +#define IS_EP_ACTIVE(epDist) ((epDist)->DistFlags & HTC_EP_ACTIVE) +#define SET_EP_ACTIVE(epDist) (epDist)->DistFlags |= HTC_EP_ACTIVE + + /* credit distibution code that is passed into the distrbution function, + * there are mandatory and optional codes that must be handled */ +typedef enum _HTC_CREDIT_DIST_REASON { + HTC_CREDIT_DIST_SEND_COMPLETE = 0, /* credits available as a result of completed + send operations (MANDATORY) resulting in credit reports */ + HTC_CREDIT_DIST_ACTIVITY_CHANGE = 1, /* a change in endpoint activity occured (OPTIONAL) */ + HTC_CREDIT_DIST_SEEK_CREDITS, /* an endpoint needs to "seek" credits (OPTIONAL) */ + HTC_DUMP_CREDIT_STATE /* for debugging, dump any state information that is kept by + the distribution function */ +} HTC_CREDIT_DIST_REASON; + +typedef void (*HTC_CREDIT_DIST_CALLBACK)(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + HTC_CREDIT_DIST_REASON Reason); + +typedef void (*HTC_CREDIT_INIT_CALLBACK)(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + int TotalCredits); + + /* endpoint statistics action */ +typedef enum _HTC_ENDPOINT_STAT_ACTION { + HTC_EP_STAT_SAMPLE = 0, /* only read statistics */ + HTC_EP_STAT_SAMPLE_AND_CLEAR = 1, /* sample and immediately clear statistics */ + HTC_EP_STAT_CLEAR /* clear only */ +} HTC_ENDPOINT_STAT_ACTION; + + /* endpoint statistics */ +typedef struct _HTC_ENDPOINT_STATS { + A_UINT32 TxCreditLowIndications; /* number of times the host set the credit-low flag in a send message on + this endpoint */ + A_UINT32 TxIssued; /* running count of TX packets issued */ + A_UINT32 TxDropped; /* tx packets that were dropped */ + A_UINT32 TxCreditRpts; /* running count of total credit reports received for this endpoint */ + A_UINT32 TxCreditRptsFromRx; /* credit reports received from this endpoint's RX packets */ + A_UINT32 TxCreditRptsFromOther; /* credit reports received from RX packets of other endpoints */ + A_UINT32 TxCreditRptsFromEp0; /* credit reports received from endpoint 0 RX packets */ + A_UINT32 TxCreditsFromRx; /* count of credits received via Rx packets on this endpoint */ + A_UINT32 TxCreditsFromOther; /* count of credits received via another endpoint */ + A_UINT32 TxCreditsFromEp0; /* count of credits received via another endpoint */ + A_UINT32 TxCreditsConsummed; /* count of consummed credits */ + A_UINT32 TxCreditsReturned; /* count of credits returned */ + A_UINT32 RxReceived; /* count of RX packets received */ + A_UINT32 RxLookAheads; /* count of lookahead records + found in messages received on this endpoint */ +} HTC_ENDPOINT_STATS; + +/* ------ Function Prototypes ------ */ +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Initialize HTC + @function name: HTCInit + @input: pInfo - initialization information + @output: + @return: A_OK on success + @notes: The caller initializes global HTC state and registers various instance + notification callbacks (see HTC_INIT_INFO). + + @example: + @see also: HTCShutdown ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCInit(HTC_INIT_INFO *pInfo); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Get the underlying HIF device handle + @function name: HTCGetHifDevice + @input: HTCHandle - handle passed into the AddInstance callback + @output: + @return: opaque HIF device handle usable in HIF API calls. + @notes: + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void *HTCGetHifDevice(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Set the associated instance for the HTC handle + @function name: HTCSetInstance + @input: HTCHandle - handle passed into the AddInstance callback + Instance - caller supplied instance object + @output: + @return: + @notes: Caller must set the instance information for the HTC handle in order to receive + notifications for instance deletion (DeleteInstance callback is called) and for target + failure notification. + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCSetInstance(HTC_HANDLE HTCHandle, void *Instance); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Set credit distribution parameters + @function name: HTCSetCreditDistribution + @input: HTCHandle - HTC handle + pCreditDistCont - caller supplied context to pass into distribution functions + CreditDistFunc - Distribution function callback + CreditDistInit - Credit Distribution initialization callback + ServicePriorityOrder - Array containing list of service IDs, lowest index is highest + priority + ListLength - number of elements in ServicePriorityOrder + @output: + @return: + @notes: The user can set a custom credit distribution function to handle special requirements + for each endpoint. A default credit distribution routine can be used by setting + CreditInitFunc to NULL. The default credit distribution is only provided for simple + "fair" credit distribution without regard to any prioritization. + + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCSetCreditDistribution(HTC_HANDLE HTCHandle, + void *pCreditDistContext, + HTC_CREDIT_DIST_CALLBACK CreditDistFunc, + HTC_CREDIT_INIT_CALLBACK CreditInitFunc, + HTC_SERVICE_ID ServicePriorityOrder[], + int ListLength); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Wait for the target to indicate the HTC layer is ready + @function name: HTCWaitTarget + @input: HTCHandle - HTC handle + @output: + @return: + @notes: This API blocks until the target responds with an HTC ready message. + The caller should not connect services until the target has indicated it is + ready. + @example: + @see also: HTCConnectService ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCWaitTarget(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Start target service communications + @function name: HTCStart + @input: HTCHandle - HTC handle + @output: + @return: + @notes: This API indicates to the target that the service connection phase is complete + and the target can freely start all connected services. This API should only be + called AFTER all service connections have been made. TCStart will issue a + SETUP_COMPLETE message to the target to indicate that all service connections + have been made and the target can start communicating over the endpoints. + @example: + @see also: HTCConnectService ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCStart(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Add receive packet to HTC + @function name: HTCAddReceivePkt + @input: HTCHandle - HTC handle + pPacket - HTC receive packet to add + @output: + @return: A_OK on success + @notes: user must supply HTC packets for capturing incomming HTC frames. The caller + must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL() + macro. + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Connect to an HTC service + @function name: HTCConnectService + @input: HTCHandle - HTC handle + pReq - connection details + @output: pResp - connection response + @return: + @notes: Service connections must be performed before HTCStart. User provides callback handlers + for various endpoint events. + @example: + @see also: HTCStart ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCConnectService(HTC_HANDLE HTCHandle, + HTC_SERVICE_CONNECT_REQ *pReq, + HTC_SERVICE_CONNECT_RESP *pResp); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Send an HTC packet + @function name: HTCSendPkt + @input: HTCHandle - HTC handle + pPacket - packet to send + @output: + @return: A_OK + @notes: Caller must initialize packet using SET_HTC_PACKET_INFO_TX() macro. + This interface is fully asynchronous. On error, HTC SendPkt will + call the registered Endpoint callback to cleanup the packet. + @example: + @see also: HTCFlushEndpoint ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Stop HTC service communications + @function name: HTCStop + @input: HTCHandle - HTC handle + @output: + @return: + @notes: HTC communications is halted. All receive and pending TX packets will + be flushed. + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCStop(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Shutdown HTC + @function name: HTCShutdown + @input: + @output: + @return: + @notes: This cleans up all resources allocated by HTCInit(). + @example: + @see also: HTCInit ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCShutDown(void); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Flush pending TX packets + @function name: HTCFlushEndpoint + @input: HTCHandle - HTC handle + Endpoint - Endpoint to flush + Tag - flush tag + @output: + @return: + @notes: The Tag parameter is used to selectively flush packets with matching tags. + The value of 0 forces all packets to be flush regardless of tag. + @example: + @see also: HTCSendPkt ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Dump credit distribution state + @function name: HTCDumpCreditStates + @input: HTCHandle - HTC handle + @output: + @return: + @notes: This dumps all credit distribution information to the debugger + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCDumpCreditStates(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Indicate a traffic activity change on an endpoint + @function name: HTCIndicateActivityChange + @input: HTCHandle - HTC handle + Endpoint - endpoint in which activity has changed + Active - TRUE if active, FALSE if it has become inactive + @output: + @return: + @notes: This triggers the registered credit distribution function to + re-adjust credits for active/inactive endpoints. + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCIndicateActivityChange(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + A_BOOL Active); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Get endpoint statistics + @function name: HTCGetEndpointStatistics + @input: HTCHandle - HTC handle + Endpoint - Endpoint identifier + Action - action to take with statistics + @output: + pStats - statistics that were sampled (can be NULL if Action is HTC_EP_STAT_CLEAR) + + @return: TRUE if statistics profiling is enabled, otherwise FALSE. + + @notes: Statistics is a compile-time option and this function may return FALSE + if HTC is not compiled with profiling. + + The caller can specify the statistic "action" to take when sampling + the statistics. This includes: + + HTC_EP_STAT_SAMPLE: The pStats structure is filled with the current values. + HTC_EP_STAT_SAMPLE_AND_CLEAR: The structure is filled and the current statistics + are cleared. + HTC_EP_STAT_CLEA : the statistics are cleared, the called can pass a NULL value for + pStats + + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_BOOL HTCGetEndpointStatistics(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + HTC_ENDPOINT_STAT_ACTION Action, + HTC_ENDPOINT_STATS *pStats); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Unblock HTC message reception + @function name: HTCUnblockRecv + @input: HTCHandle - HTC handle + @output: + @return: + @notes: + HTC will block the receiver if the EpRecvAlloc callback fails to provide a packet. + The caller can use this API to indicate to HTC when resources (buffers) are available + such that the receiver can be unblocked and HTC may re-attempt fetching the pending message. + + This API is not required if the user uses the EpRecvRefill callback or uses the HTCAddReceivePacket() + API to recycle or provide receive packets to HTC. + + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCUnblockRecv(HTC_HANDLE HTCHandle); + +/* internally used functions for testing... */ +void HTCEnableRecv(HTC_HANDLE HTCHandle); +void HTCDisableRecv(HTC_HANDLE HTCHandle); + +#ifdef __cplusplus +} +#endif + +#endif /* _HTC_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/htc_internal.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/htc_internal.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/htc_internal.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/htc_internal.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,176 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HTC_INTERNAL_H_ +#define _HTC_INTERNAL_H_ + +/* for debugging, uncomment this to capture the last frame header, on frame header + * processing errors, the last frame header is dump for comparison */ +//#define HTC_CAPTURE_LAST_FRAME + +//#define HTC_EP_STAT_PROFILING + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Header files */ +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "a_debug.h" +#include "htc.h" +#include "htc_api.h" +#include "bmi_msg.h" +#include "hif.h" +#include "AR6000/ar6k.h" + +/* HTC operational parameters */ +#define HTC_TARGET_RESPONSE_TIMEOUT 2000 /* in ms */ +#define HTC_TARGET_DEBUG_INTR_MASK 0x01 +#define HTC_TARGET_CREDIT_INTR_MASK 0xF0 + +typedef struct _HTC_ENDPOINT { + HTC_SERVICE_ID ServiceID; /* service ID this endpoint is bound to + non-zero value means this endpoint is in use */ + HTC_PACKET_QUEUE TxQueue; /* HTC frame buffer TX queue */ + HTC_PACKET_QUEUE RxBuffers; /* HTC frame buffer RX list */ + HTC_ENDPOINT_CREDIT_DIST CreditDist; /* credit distribution structure (exposed to driver layer) */ + HTC_EP_CALLBACKS EpCallBacks; /* callbacks associated with this endpoint */ + int MaxTxQueueDepth; /* max depth of the TX queue before we need to + call driver's full handler */ + int CurrentTxQueueDepth; /* current TX queue depth */ + int MaxMsgLength; /* max length of endpoint message */ +#ifdef HTC_EP_STAT_PROFILING + HTC_ENDPOINT_STATS EndPointStats; /* endpoint statistics */ +#endif +} HTC_ENDPOINT; + +#ifdef HTC_EP_STAT_PROFILING +#define INC_HTC_EP_STAT(p,stat,count) (p)->EndPointStats.stat += (count); +#else +#define INC_HTC_EP_STAT(p,stat,count) +#endif + +#define HTC_SERVICE_TX_PACKET_TAG HTC_TX_PACKET_TAG_INTERNAL + +#define NUM_CONTROL_BUFFERS 8 +#define NUM_CONTROL_TX_BUFFERS 2 +#define NUM_CONTROL_RX_BUFFERS (NUM_CONTROL_BUFFERS - NUM_CONTROL_TX_BUFFERS) + +typedef struct HTC_CONTROL_BUFFER { + HTC_PACKET HtcPacket; + A_UINT8 *Buffer; +} HTC_CONTROL_BUFFER; + +/* our HTC target state */ +typedef struct _HTC_TARGET { + HTC_ENDPOINT EndPoint[ENDPOINT_MAX]; + HTC_CONTROL_BUFFER HTCControlBuffers[NUM_CONTROL_BUFFERS]; + HTC_ENDPOINT_CREDIT_DIST *EpCreditDistributionListHead; + HTC_PACKET_QUEUE ControlBufferTXFreeList; + HTC_PACKET_QUEUE ControlBufferRXFreeList; + HTC_CREDIT_DIST_CALLBACK DistributeCredits; + HTC_CREDIT_INIT_CALLBACK InitCredits; + void *pCredDistContext; + int TargetCredits; + int TargetCreditSize; + A_MUTEX_T HTCLock; + A_MUTEX_T HTCRxLock; + A_MUTEX_T HTCTxLock; + AR6K_DEVICE Device; /* AR6K - specific state */ + A_UINT32 HTCStateFlags; + HTC_ENDPOINT_ID EpWaitingForBuffers; + A_BOOL TargetFailure; + void *pInstanceContext; +#define HTC_STATE_WAIT_BUFFERS (1 << 0) +#define HTC_STATE_STOPPING (1 << 1) +#ifdef HTC_CAPTURE_LAST_FRAME + HTC_FRAME_HDR LastFrameHdr; /* useful for debugging */ + A_UINT8 LastTrailer[256]; + A_UINT8 LastTrailerLength; +#endif +} HTC_TARGET; + +#define HTC_STOPPING(t) ((t)->HTCStateFlags & HTC_STATE_STOPPING) +#define LOCK_HTC(t) A_MUTEX_LOCK(&(t)->HTCLock); +#define UNLOCK_HTC(t) A_MUTEX_UNLOCK(&(t)->HTCLock); +#define LOCK_HTC_RX(t) A_MUTEX_LOCK(&(t)->HTCRxLock); +#define UNLOCK_HTC_RX(t) A_MUTEX_UNLOCK(&(t)->HTCRxLock); +#define LOCK_HTC_TX(t) A_MUTEX_LOCK(&(t)->HTCTxLock); +#define UNLOCK_HTC_TX(t) A_MUTEX_UNLOCK(&(t)->HTCTxLock); + +#define GET_HTC_TARGET_FROM_HANDLE(hnd) ((HTC_TARGET *)(hnd)) +#define HTC_RECYCLE_RX_PKT(target,p,e) \ +{ \ + if ((e)->EpCallBacks.EpRecvAlloc != NULL) { \ + HTC_PACKET_RESET_RX(pPacket); \ + pPacket->Status = A_ECANCELED; \ + (e)->EpCallBacks.EpRecv((e)->EpCallBacks.pContext, \ + (p)); \ + } else { \ + HTC_PACKET_RESET_RX(pPacket); \ + HTCAddReceivePkt((HTC_HANDLE)(target),(p)); \ + } \ +} + +/* internal HTC functions */ +void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket); +void HTCControlRecv(void *Context, HTC_PACKET *pPacket); +A_STATUS HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket); +HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList); +void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList); +A_STATUS HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT8 Flags); +A_STATUS HTCIssueRecv(HTC_TARGET *target, HTC_PACKET *pPacket); +void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket); +A_STATUS HTCRecvMessagePendingHandler(void *Context, A_UINT32 LookAhead, A_BOOL *pAsyncProc); +void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint); +A_STATUS HTCSendSetupComplete(HTC_TARGET *target); +void HTCFlushRecvBuffers(HTC_TARGET *target); +void HTCFlushSendPkts(HTC_TARGET *target); +void DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist); +void DumpCreditDistStates(HTC_TARGET *target); +void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription); + +static INLINE HTC_PACKET *HTC_ALLOC_CONTROL_TX(HTC_TARGET *target) { + HTC_PACKET *pPacket = HTCAllocControlBuffer(target,&target->ControlBufferTXFreeList); + if (pPacket != NULL) { + /* set payload pointer area with some headroom */ + pPacket->pBuffer = pPacket->pBufferStart + HTC_HDR_LENGTH; + } + return pPacket; +} + +#define HTC_FREE_CONTROL_TX(t,p) HTCFreeControlBuffer((t),(p),&(t)->ControlBufferTXFreeList) +#define HTC_ALLOC_CONTROL_RX(t) HTCAllocControlBuffer((t),&(t)->ControlBufferRXFreeList) +#define HTC_FREE_CONTROL_RX(t,p) \ +{ \ + HTC_PACKET_RESET_RX(p); \ + HTCFreeControlBuffer((t),(p),&(t)->ControlBufferRXFreeList); \ +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HTC_INTERNAL_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/htc_packet.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/htc_packet.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/htc_packet.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/htc_packet.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,160 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef HTC_PACKET_H_ +#define HTC_PACKET_H_ + + +#include "dl_list.h" + +/* ------ Endpoint IDS ------ */ +typedef enum +{ + ENDPOINT_UNUSED = -1, + ENDPOINT_0 = 0, + ENDPOINT_1 = 1, + ENDPOINT_2 = 2, + ENDPOINT_3, + ENDPOINT_4, + ENDPOINT_5, + ENDPOINT_6, + ENDPOINT_7, + ENDPOINT_8, + ENDPOINT_MAX, +} HTC_ENDPOINT_ID; + +struct _HTC_PACKET; + +typedef void (* HTC_PACKET_COMPLETION)(void *,struct _HTC_PACKET *); + +typedef A_UINT16 HTC_TX_TAG; + +typedef struct _HTC_TX_PACKET_INFO { + HTC_TX_TAG Tag; /* tag used to selective flush packets */ +} HTC_TX_PACKET_INFO; + +#define HTC_TX_PACKET_TAG_ALL 0 /* a tag of zero is reserved and used to flush ALL packets */ +#define HTC_TX_PACKET_TAG_INTERNAL 1 /* internal tags start here */ +#define HTC_TX_PACKET_TAG_USER_DEFINED (HTC_TX_PACKET_TAG_INTERNAL + 9) /* user-defined tags start here */ + +typedef struct _HTC_RX_PACKET_INFO { + A_UINT32 Unused; /* for future use and to make compilers happy */ +} HTC_RX_PACKET_INFO; + +/* wrapper around endpoint-specific packets */ +typedef struct _HTC_PACKET { + DL_LIST ListLink; /* double link */ + void *pPktContext; /* caller's per packet specific context */ + + A_UINT8 *pBufferStart; /* the true buffer start , the caller can + store the real buffer start here. In + receive callbacks, the HTC layer sets pBuffer + to the start of the payload past the header. This + field allows the caller to reset pBuffer when it + recycles receive packets back to HTC */ + /* + * Pointer to the start of the buffer. In the transmit + * direction this points to the start of the payload. In the + * receive direction, however, the buffer when queued up + * points to the start of the HTC header but when returned + * to the caller points to the start of the payload + */ + A_UINT8 *pBuffer; /* payload start (RX/TX) */ + A_UINT32 BufferLength; /* length of buffer */ + A_UINT32 ActualLength; /* actual length of payload */ + HTC_ENDPOINT_ID Endpoint; /* endpoint that this packet was sent/recv'd from */ + A_STATUS Status; /* completion status */ + union { + HTC_TX_PACKET_INFO AsTx; /* Tx Packet specific info */ + HTC_RX_PACKET_INFO AsRx; /* Rx Packet specific info */ + } PktInfo; + + /* the following fields are for internal HTC use */ + HTC_PACKET_COMPLETION Completion; /* completion */ + void *pContext; /* HTC private completion context */ + A_UINT32 HTCReserved; /* reserved */ +} HTC_PACKET; + + + +#define COMPLETE_HTC_PACKET(p,status) \ +{ \ + (p)->Status = (status); \ + (p)->Completion((p)->pContext,(p)); \ +} + +#define INIT_HTC_PACKET_INFO(p,b,len) \ +{ \ + (p)->pBufferStart = (b); \ + (p)->BufferLength = (len); \ +} + +/* macro to set an initial RX packet for refilling HTC */ +#define SET_HTC_PACKET_INFO_RX_REFILL(p,c,b,len,ep) \ +{ \ + (p)->pPktContext = (c); \ + (p)->pBuffer = (b); \ + (p)->pBufferStart = (b); \ + (p)->BufferLength = (len); \ + (p)->Endpoint = (ep); \ +} + +/* fast macro to recycle an RX packet that will be re-queued to HTC */ +#define HTC_PACKET_RESET_RX(p) \ + (p)->pBuffer = (p)->pBufferStart + +/* macro to set packet parameters for TX */ +#define SET_HTC_PACKET_INFO_TX(p,c,b,len,ep,tag) \ +{ \ + (p)->pPktContext = (c); \ + (p)->pBuffer = (b); \ + (p)->ActualLength = (len); \ + (p)->Endpoint = (ep); \ + (p)->PktInfo.AsTx.Tag = (tag); \ +} + +/* HTC Packet Queueing Macros */ +typedef DL_LIST HTC_PACKET_QUEUE; +/* initialize queue */ +#define INIT_HTC_PACKET_QUEUE(pQ) DL_LIST_INIT((pQ)) +/* enqueue HTC packet to the tail of the queue */ +#define HTC_PACKET_ENQUEUE(pQ,p) DL_ListInsertTail((pQ),&(p)->ListLink) +/* test if a queue is empty */ +#define HTC_QUEUE_EMPTY(pQ) DL_LIST_IS_EMPTY((pQ)) +/* get packet at head without removing it */ +#define HTC_GET_PKT_AT_HEAD(pQ) A_CONTAINING_STRUCT((DL_LIST_GET_ITEM_AT_HEAD(pQ)),HTC_PACKET,ListLink); +/* remove a packet from the current list it is linked to */ +#define HTC_PACKET_REMOVE(p) DL_ListRemove(&(p)->ListLink) + +/* dequeue an HTC packet from the head of the queue */ +static INLINE HTC_PACKET *HTC_PACKET_DEQUEUE(HTC_PACKET_QUEUE *queue) { + DL_LIST *pItem = DL_ListRemoveItemFromHead(queue); + if (pItem != NULL) { + return A_CONTAINING_STRUCT(pItem, HTC_PACKET, ListLink); + } + return NULL; +} + +#define HTC_GET_ENDPOINT_FROM_PKT(p) (p)->Endpoint +#define HTC_GET_TAG_FROM_PKT(p) (p)->PktInfo.AsTx.Tag + +#endif /*HTC_PACKET_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/htc_services.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/htc_services.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/htc_services.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/htc_services.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __HTC_SERVICES_H__ +#define __HTC_SERVICES_H__ + +/* Current service IDs */ + +typedef enum { + RSVD_SERVICE_GROUP = 0, + WMI_SERVICE_GROUP = 1, + + HTC_TEST_GROUP = 254, + HTC_SERVICE_GROUP_LAST = 255 +}HTC_SERVICE_GROUP_IDS; + +#define MAKE_SERVICE_ID(group,index) \ + (int)(((int)group << 8) | (int)(index)) + +/* NOTE: service ID of 0x0000 is reserved and should never be used */ +#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1) +#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0) +#define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1) +#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2) +#define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3) +#define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4) +#define WMI_MAX_SERVICES 5 + +/* raw stream service (i.e. flash, tcmd, calibration apps) */ +#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0) + +#endif /*HTC_SERVICES_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/ieee80211.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/ieee80211.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/ieee80211.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/ieee80211.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,344 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _NET80211_IEEE80211_H_ +#define _NET80211_IEEE80211_H_ + +#include "athstartpack.h" + +/* + * 802.11 protocol definitions. + */ + +#define IEEE80211_ADDR_LEN 6 /* size of 802.11 address */ +/* is 802.11 address multicast/broadcast? */ +#define IEEE80211_IS_MULTICAST(_a) (*(_a) & 0x01) +#define IEEE80211_ADDR_EQ(addr1, addr2) \ + (A_MEMCMP(addr1, addr2, IEEE80211_ADDR_LEN) == 0) + +#define IEEE80211_KEYBUF_SIZE 16 +#define IEEE80211_MICBUF_SIZE (8+8) /* space for both tx and rx */ + +/* + * NB: these values are ordered carefully; there are lots of + * of implications in any reordering. In particular beware + * that 4 is not used to avoid conflicting with IEEE80211_F_PRIVACY. + */ +#define IEEE80211_CIPHER_WEP 0 +#define IEEE80211_CIPHER_TKIP 1 +#define IEEE80211_CIPHER_AES_OCB 2 +#define IEEE80211_CIPHER_AES_CCM 3 +#define IEEE80211_CIPHER_CKIP 5 +#define IEEE80211_CIPHER_CCKM_KRK 6 +#define IEEE80211_CIPHER_NONE 7 /* pseudo value */ + +#define IEEE80211_CIPHER_MAX (IEEE80211_CIPHER_NONE+1) + +#define IEEE80211_IS_VALID_WEP_CIPHER_LEN(len) \ + (((len) == 5) || ((len) == 13) || ((len) == 16)) + + + +/* + * generic definitions for IEEE 802.11 frames + */ +PREPACK struct ieee80211_frame { + A_UINT8 i_fc[2]; + A_UINT8 i_dur[2]; + A_UINT8 i_addr1[IEEE80211_ADDR_LEN]; + A_UINT8 i_addr2[IEEE80211_ADDR_LEN]; + A_UINT8 i_addr3[IEEE80211_ADDR_LEN]; + A_UINT8 i_seq[2]; + /* possibly followed by addr4[IEEE80211_ADDR_LEN]; */ + /* see below */ +} POSTPACK; + +#define IEEE80211_FC0_VERSION_MASK 0x03 +#define IEEE80211_FC0_VERSION_SHIFT 0 +#define IEEE80211_FC0_VERSION_0 0x00 +#define IEEE80211_FC0_TYPE_MASK 0x0c +#define IEEE80211_FC0_TYPE_SHIFT 2 +#define IEEE80211_FC0_TYPE_MGT 0x00 +#define IEEE80211_FC0_TYPE_CTL 0x04 +#define IEEE80211_FC0_TYPE_DATA 0x08 + +#define IEEE80211_FC0_SUBTYPE_MASK 0xf0 +#define IEEE80211_FC0_SUBTYPE_SHIFT 4 +/* for TYPE_MGT */ +#define IEEE80211_FC0_SUBTYPE_ASSOC_REQ 0x00 +#define IEEE80211_FC0_SUBTYPE_ASSOC_RESP 0x10 +#define IEEE80211_FC0_SUBTYPE_REASSOC_REQ 0x20 +#define IEEE80211_FC0_SUBTYPE_REASSOC_RESP 0x30 +#define IEEE80211_FC0_SUBTYPE_PROBE_REQ 0x40 +#define IEEE80211_FC0_SUBTYPE_PROBE_RESP 0x50 +#define IEEE80211_FC0_SUBTYPE_BEACON 0x80 +#define IEEE80211_FC0_SUBTYPE_ATIM 0x90 +#define IEEE80211_FC0_SUBTYPE_DISASSOC 0xa0 +#define IEEE80211_FC0_SUBTYPE_AUTH 0xb0 +#define IEEE80211_FC0_SUBTYPE_DEAUTH 0xc0 +/* for TYPE_CTL */ +#define IEEE80211_FC0_SUBTYPE_PS_POLL 0xa0 +#define IEEE80211_FC0_SUBTYPE_RTS 0xb0 +#define IEEE80211_FC0_SUBTYPE_CTS 0xc0 +#define IEEE80211_FC0_SUBTYPE_ACK 0xd0 +#define IEEE80211_FC0_SUBTYPE_CF_END 0xe0 +#define IEEE80211_FC0_SUBTYPE_CF_END_ACK 0xf0 +/* for TYPE_DATA (bit combination) */ +#define IEEE80211_FC0_SUBTYPE_DATA 0x00 +#define IEEE80211_FC0_SUBTYPE_CF_ACK 0x10 +#define IEEE80211_FC0_SUBTYPE_CF_POLL 0x20 +#define IEEE80211_FC0_SUBTYPE_CF_ACPL 0x30 +#define IEEE80211_FC0_SUBTYPE_NODATA 0x40 +#define IEEE80211_FC0_SUBTYPE_CFACK 0x50 +#define IEEE80211_FC0_SUBTYPE_CFPOLL 0x60 +#define IEEE80211_FC0_SUBTYPE_CF_ACK_CF_ACK 0x70 +#define IEEE80211_FC0_SUBTYPE_QOS 0x80 +#define IEEE80211_FC0_SUBTYPE_QOS_NULL 0xc0 + +#define IEEE80211_FC1_DIR_MASK 0x03 +#define IEEE80211_FC1_DIR_NODS 0x00 /* STA->STA */ +#define IEEE80211_FC1_DIR_TODS 0x01 /* STA->AP */ +#define IEEE80211_FC1_DIR_FROMDS 0x02 /* AP ->STA */ +#define IEEE80211_FC1_DIR_DSTODS 0x03 /* AP ->AP */ + +#define IEEE80211_FC1_MORE_FRAG 0x04 +#define IEEE80211_FC1_RETRY 0x08 +#define IEEE80211_FC1_PWR_MGT 0x10 +#define IEEE80211_FC1_MORE_DATA 0x20 +#define IEEE80211_FC1_WEP 0x40 +#define IEEE80211_FC1_ORDER 0x80 + +#define IEEE80211_SEQ_FRAG_MASK 0x000f +#define IEEE80211_SEQ_FRAG_SHIFT 0 +#define IEEE80211_SEQ_SEQ_MASK 0xfff0 +#define IEEE80211_SEQ_SEQ_SHIFT 4 + +#define IEEE80211_NWID_LEN 32 + +/* + * 802.11 rate set. + */ +#define IEEE80211_RATE_SIZE 8 /* 802.11 standard */ +#define IEEE80211_RATE_MAXSIZE 15 /* max rates we'll handle */ + +#define WMM_NUM_AC 4 /* 4 AC categories */ + +#define WMM_PARAM_ACI_M 0x60 /* Mask for ACI field */ +#define WMM_PARAM_ACI_S 5 /* Shift for ACI field */ +#define WMM_PARAM_ACM_M 0x10 /* Mask for ACM bit */ +#define WMM_PARAM_ACM_S 4 /* Shift for ACM bit */ +#define WMM_PARAM_AIFSN_M 0x0f /* Mask for aifsn field */ +#define WMM_PARAM_LOGCWMIN_M 0x0f /* Mask for CwMin field (in log) */ +#define WMM_PARAM_LOGCWMAX_M 0xf0 /* Mask for CwMax field (in log) */ +#define WMM_PARAM_LOGCWMAX_S 4 /* Shift for CwMax field */ + +#define WMM_AC_TO_TID(_ac) ( \ + ((_ac) == WMM_AC_VO) ? 6 : \ + ((_ac) == WMM_AC_VI) ? 5 : \ + ((_ac) == WMM_AC_BK) ? 1 : \ + 0) + +#define TID_TO_WMM_AC(_tid) ( \ + ((_tid) < 1) ? WMM_AC_BE : \ + ((_tid) < 3) ? WMM_AC_BK : \ + ((_tid) < 6) ? WMM_AC_VI : \ + WMM_AC_VO) +/* + * Management information element payloads. + */ + +enum { + IEEE80211_ELEMID_SSID = 0, + IEEE80211_ELEMID_RATES = 1, + IEEE80211_ELEMID_FHPARMS = 2, + IEEE80211_ELEMID_DSPARMS = 3, + IEEE80211_ELEMID_CFPARMS = 4, + IEEE80211_ELEMID_TIM = 5, + IEEE80211_ELEMID_IBSSPARMS = 6, + IEEE80211_ELEMID_COUNTRY = 7, + IEEE80211_ELEMID_CHALLENGE = 16, + /* 17-31 reserved for challenge text extension */ + IEEE80211_ELEMID_PWRCNSTR = 32, + IEEE80211_ELEMID_PWRCAP = 33, + IEEE80211_ELEMID_TPCREQ = 34, + IEEE80211_ELEMID_TPCREP = 35, + IEEE80211_ELEMID_SUPPCHAN = 36, + IEEE80211_ELEMID_CHANSWITCH = 37, + IEEE80211_ELEMID_MEASREQ = 38, + IEEE80211_ELEMID_MEASREP = 39, + IEEE80211_ELEMID_QUIET = 40, + IEEE80211_ELEMID_IBSSDFS = 41, + IEEE80211_ELEMID_ERP = 42, + IEEE80211_ELEMID_RSN = 48, + IEEE80211_ELEMID_XRATES = 50, + IEEE80211_ELEMID_TPC = 150, + IEEE80211_ELEMID_CCKM = 156, + IEEE80211_ELEMID_VENDOR = 221, /* vendor private */ +}; + +#define ATH_OUI 0x7f0300 /* Atheros OUI */ +#define ATH_OUI_TYPE 0x01 +#define ATH_OUI_SUBTYPE 0x01 +#define ATH_OUI_VERSION 0x00 + +#define WPA_OUI 0xf25000 +#define WPA_OUI_TYPE 0x01 +#define WPA_VERSION 1 /* current supported version */ + +#define WPA_CSE_NULL 0x00 +#define WPA_CSE_WEP40 0x01 +#define WPA_CSE_TKIP 0x02 +#define WPA_CSE_CCMP 0x04 +#define WPA_CSE_WEP104 0x05 + +#define WPA_ASE_NONE 0x00 +#define WPA_ASE_8021X_UNSPEC 0x01 +#define WPA_ASE_8021X_PSK 0x02 + +#define RSN_OUI 0xac0f00 +#define RSN_VERSION 1 /* current supported version */ + +#define RSN_CSE_NULL 0x00 +#define RSN_CSE_WEP40 0x01 +#define RSN_CSE_TKIP 0x02 +#define RSN_CSE_WRAP 0x03 +#define RSN_CSE_CCMP 0x04 +#define RSN_CSE_WEP104 0x05 + +#define RSN_ASE_NONE 0x00 +#define RSN_ASE_8021X_UNSPEC 0x01 +#define RSN_ASE_8021X_PSK 0x02 + +#define RSN_CAP_PREAUTH 0x01 + +#define WMM_OUI 0xf25000 +#define WMM_OUI_TYPE 0x02 +#define WMM_INFO_OUI_SUBTYPE 0x00 +#define WMM_PARAM_OUI_SUBTYPE 0x01 +#define WMM_VERSION 1 + +/* WMM stream classes */ +#define WMM_NUM_AC 4 +#define WMM_AC_BE 0 /* best effort */ +#define WMM_AC_BK 1 /* background */ +#define WMM_AC_VI 2 /* video */ +#define WMM_AC_VO 3 /* voice */ + +/* TSPEC related */ +#define ACTION_CATEGORY_CODE_TSPEC 17 +#define ACTION_CODE_TSPEC_ADDTS 0 +#define ACTION_CODE_TSPEC_ADDTS_RESP 1 +#define ACTION_CODE_TSPEC_DELTS 2 + +typedef enum { + TSPEC_STATUS_CODE_ADMISSION_ACCEPTED = 0, + TSPEC_STATUS_CODE_ADDTS_INVALID_PARAMS = 0x1, + TSPEC_STATUS_CODE_ADDTS_REQUEST_REFUSED = 0x3, + TSPEC_STATUS_CODE_UNSPECIFIED_QOS_RELATED_FAILURE = 0xC8, + TSPEC_STATUS_CODE_REQUESTED_REFUSED_POLICY_CONFIGURATION = 0xC9, + TSPEC_STATUS_CODE_INSUFFCIENT_BANDWIDTH = 0xCA, + TSPEC_STATUS_CODE_INVALID_PARAMS = 0xCB, + TSPEC_STATUS_CODE_DELTS_SENT = 0x30, + TSPEC_STATUS_CODE_DELTS_RECV = 0x31, +} TSPEC_STATUS_CODE; + +/* + * WMM/802.11e Tspec Element + */ +typedef PREPACK struct wmm_tspec_ie_t { + A_UINT8 elementId; + A_UINT8 len; + A_UINT8 oui[3]; + A_UINT8 ouiType; + A_UINT8 ouiSubType; + A_UINT8 version; + A_UINT16 tsInfo_info; + A_UINT8 tsInfo_reserved; + A_UINT16 nominalMSDU; + A_UINT16 maxMSDU; + A_UINT32 minServiceInt; + A_UINT32 maxServiceInt; + A_UINT32 inactivityInt; + A_UINT32 suspensionInt; + A_UINT32 serviceStartTime; + A_UINT32 minDataRate; + A_UINT32 meanDataRate; + A_UINT32 peakDataRate; + A_UINT32 maxBurstSize; + A_UINT32 delayBound; + A_UINT32 minPhyRate; + A_UINT16 sba; + A_UINT16 mediumTime; +} POSTPACK WMM_TSPEC_IE; + + +/* + * BEACON management packets + * + * octet timestamp[8] + * octet beacon interval[2] + * octet capability information[2] + * information element + * octet elemid + * octet length + * octet information[length] + */ + +#define IEEE80211_BEACON_INTERVAL(beacon) \ + ((beacon)[8] | ((beacon)[9] << 8)) +#define IEEE80211_BEACON_CAPABILITY(beacon) \ + ((beacon)[10] | ((beacon)[11] << 8)) + +#define IEEE80211_CAPINFO_ESS 0x0001 +#define IEEE80211_CAPINFO_IBSS 0x0002 +#define IEEE80211_CAPINFO_CF_POLLABLE 0x0004 +#define IEEE80211_CAPINFO_CF_POLLREQ 0x0008 +#define IEEE80211_CAPINFO_PRIVACY 0x0010 +#define IEEE80211_CAPINFO_SHORT_PREAMBLE 0x0020 +#define IEEE80211_CAPINFO_PBCC 0x0040 +#define IEEE80211_CAPINFO_CHNL_AGILITY 0x0080 +/* bits 8-9 are reserved */ +#define IEEE80211_CAPINFO_SHORT_SLOTTIME 0x0400 +#define IEEE80211_CAPINFO_APSD 0x0800 +/* bit 12 is reserved */ +#define IEEE80211_CAPINFO_DSSSOFDM 0x2000 +/* bits 14-15 are reserved */ + +/* + * Authentication Modes + */ + +enum ieee80211_authmode { + IEEE80211_AUTH_NONE = 0, + IEEE80211_AUTH_OPEN = 1, + IEEE80211_AUTH_SHARED = 2, + IEEE80211_AUTH_8021X = 3, + IEEE80211_AUTH_AUTO = 4, /* auto-select/accept */ + /* NB: these are used only for ioctls */ + IEEE80211_AUTH_WPA = 5, /* WPA/RSN w/ 802.1x */ + IEEE80211_AUTH_WPA_PSK = 6, /* WPA/RSN w/ PSK */ + IEEE80211_AUTH_WPA_CCKM = 7, /* WPA/RSN IE w/ CCKM */ +}; + +#include "athendpack.h" + +#endif /* _NET80211_IEEE80211_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/ieee80211_node.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/ieee80211_node.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/ieee80211_node.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/ieee80211_node.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,85 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _IEEE80211_NODE_H_ +#define _IEEE80211_NODE_H_ + +/* + * Node locking definitions. + */ +#define IEEE80211_NODE_LOCK_INIT(_nt) A_MUTEX_INIT(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_LOCK_DESTROY(_nt) if (A_IS_MUTEX_VALID(&(_nt)->nt_nodelock)) { \ + A_MUTEX_DELETE(&(_nt)->nt_nodelock); } + +#define IEEE80211_NODE_LOCK(_nt) A_MUTEX_LOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_UNLOCK(_nt) A_MUTEX_UNLOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_LOCK_BH(_nt) A_MUTEX_LOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_UNLOCK_BH(_nt) A_MUTEX_UNLOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_LOCK_ASSERT(_nt) + +/* + * Node reference counting definitions. + * + * ieee80211_node_initref initialize the reference count to 1 + * ieee80211_node_incref add a reference + * ieee80211_node_decref remove a reference + * ieee80211_node_dectestref remove a reference and return 1 if this + * is the last reference, otherwise 0 + * ieee80211_node_refcnt reference count for printing (only) + */ +#define ieee80211_node_initref(_ni) ((_ni)->ni_refcnt = 1) +#define ieee80211_node_incref(_ni) ((_ni)->ni_refcnt++) +#define ieee80211_node_decref(_ni) ((_ni)->ni_refcnt--) +#define ieee80211_node_dectestref(_ni) (((_ni)->ni_refcnt--) == 0) +#define ieee80211_node_refcnt(_ni) ((_ni)->ni_refcnt) + +#define IEEE80211_NODE_HASHSIZE 32 +/* simple hash is enough for variation of macaddr */ +#define IEEE80211_NODE_HASH(addr) \ + (((const A_UINT8 *)(addr))[IEEE80211_ADDR_LEN - 1] % \ + IEEE80211_NODE_HASHSIZE) + +/* + * Table of ieee80211_node instances. Each ieee80211com + * has at least one for holding the scan candidates. + * When operating as an access point or in ibss mode there + * is a second table for associated stations or neighbors. + */ +struct ieee80211_node_table { + void *nt_wmip; /* back reference */ + A_MUTEX_T nt_nodelock; /* on node table */ + struct bss *nt_node_first; /* information of all nodes */ + struct bss *nt_node_last; /* information of all nodes */ + struct bss *nt_hash[IEEE80211_NODE_HASHSIZE]; + const char *nt_name; /* for debugging */ + A_UINT32 nt_scangen; /* gen# for timeout scan */ + A_TIMER nt_inact_timer; + A_UINT8 isTimerArmed; /* is the node timer armed */ + A_UINT32 nt_nodeAge; /* node aging time */ +#ifdef OS_ROAM_MANAGEMENT + A_UINT32 nt_si_gen; /* gen# for scan indication*/ +#endif +}; + +#define WLAN_NODE_INACT_TIMEOUT_MSEC 120000 + +#endif /* _IEEE80211_NODE_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/regdump.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/regdump.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/regdump.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/regdump.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,49 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __REGDUMP_H__ +#define __REGDUMP_H__ +#if defined(AR6001) +#include "AR6001/AR6001_regdump.h" +#endif +#if defined(AR6002) +#include "AR6002/AR6002_regdump.h" +#endif + +#if !defined(__ASSEMBLER__) +/* + * Target CPU state at the time of failure is reflected + * in a register dump, which the Host can fetch through + * the diagnostic window. + */ +struct register_dump_s { + A_UINT32 target_id; /* Target ID */ + A_UINT32 assline; /* Line number (if assertion failure) */ + A_UINT32 pc; /* Program Counter at time of exception */ + A_UINT32 badvaddr; /* Virtual address causing exception */ + CPU_exception_frame_t exc_frame; /* CPU-specific exception info */ + + /* Could copy top of stack here, too.... */ +}; +#endif /* __ASSEMBLER__ */ +#endif /* __REGDUMP_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/roaming.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/roaming.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/roaming.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/roaming.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,41 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _ROAMING_H_ +#define _ROAMING_H_ + +/* + * The signal quality could be in terms of either snr or rssi. We should + * have an enum for both of them. For the time being, we are going to move + * it to wmi.h that is shared by both host and the target, since we are + * repartitioning the code to the host + */ +#define SIGNAL_QUALITY_NOISE_FLOOR -95 +#define SIGNAL_QUALITY_METRICS_NUM_MAX 2 +typedef enum { + SIGNAL_QUALITY_METRICS_SNR = 0, + SIGNAL_QUALITY_METRICS_RSSI, + SIGNAL_QUALITY_METRICS_ALL, +} SIGNAL_QUALITY_METRICS_TYPE; + +#endif /* _ROAMING_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/targaddrs.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/targaddrs.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/targaddrs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/targaddrs.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,175 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __TARGADDRS_H__ +#define __TARGADDRS_H__ +#if defined(AR6001) +#include "AR6001/addrs.h" +#endif +#if defined(AR6002) +#include "AR6002/addrs.h" +#endif + +/* + * AR6K option bits, to enable/disable various features. + * By default, all option bits are 0. + * These bits can be set in LOCAL_SCRATCH register 0. + */ +#define AR6K_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */ +#define AR6K_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */ +#define AR6K_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */ +#define AR6K_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */ +#define AR6K_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */ +#define AR6K_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */ +#define AR6K_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */ +#define AR6K_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */ + +/* + * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the + * host_interest structure. It must match the address of the _host_interest + * symbol (see linker script). + * + * Host Interest is shared between Host and Target in order to coordinate + * between the two, and is intended to remain constant (with additions only + * at the end) across software releases. + */ +#define AR6001_HOST_INTEREST_ADDRESS 0x80000600 +#define AR6002_HOST_INTEREST_ADDRESS 0x00500400 + +#define HOST_INTEREST_MAX_SIZE 0x100 + +#if !defined(__ASSEMBLER__) +struct register_dump_s; +struct dbglog_hdr_s; + +/* + * These are items that the Host may need to access + * via BMI or via the Diagnostic Window. The position + * of items in this structure must remain constant + * across firmware revisions! + * + * Types for each item must be fixed size across + * target and host platforms. + * + * More items may be added at the end. + */ +struct host_interest_s { + /* + * Pointer to application-defined area, if any. + * Set by Target application during startup. + */ + A_UINT32 hi_app_host_interest; /* 0x00 */ + + /* Pointer to register dump area, valid after Target crash. */ + A_UINT32 hi_failure_state; /* 0x04 */ + + /* Pointer to debug logging header */ + A_UINT32 hi_dbglog_hdr; /* 0x08 */ + + /* Indicates whether or not flash is present on Target. + * NB: flash_is_present indicator is here not just + * because it might be of interest to the Host; but + * also because it's set early on by Target's startup + * asm code and we need it to have a special RAM address + * so that it doesn't get reinitialized with the rest + * of data. + */ + A_UINT32 hi_flash_is_present; /* 0x0c */ + + /* + * General-purpose flag bits, similar to AR6000_OPTION_* flags. + * Can be used by application rather than by OS. + */ + A_UINT32 hi_option_flag; /* 0x10 */ + + /* + * Boolean that determines whether or not to + * display messages on the serial port. + */ + A_UINT32 hi_serial_enable; /* 0x14 */ + + /* Start address of Flash DataSet index, if any */ + A_UINT32 hi_dset_list_head; /* 0x18 */ + + /* Override Target application start address */ + A_UINT32 hi_app_start; /* 0x1c */ + + /* Clock and voltage tuning */ + A_UINT32 hi_skip_clock_init; /* 0x20 */ + A_UINT32 hi_core_clock_setting; /* 0x24 */ + A_UINT32 hi_cpu_clock_setting; /* 0x28 */ + A_UINT32 hi_system_sleep_setting; /* 0x2c */ + A_UINT32 hi_xtal_control_setting; /* 0x30 */ + A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ + A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ + A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */ + A_UINT32 hi_clock_info; /* 0x40 */ + + /* + * Flash configuration overrides, used only + * when firmware is not executing from flash. + * (When using flash, modify the global variables + * with equivalent names.) + */ + A_UINT32 hi_bank0_addr_value; /* 0x44 */ + A_UINT32 hi_bank0_read_value; /* 0x48 */ + A_UINT32 hi_bank0_write_value; /* 0x4c */ + A_UINT32 hi_bank0_config_value; /* 0x50 */ + + /* Pointer to Board Data */ + A_UINT32 hi_board_data; /* 0x54 */ + A_UINT32 hi_board_data_initialized; /* 0x58 */ + + A_UINT32 hi_dset_RAM_index_table; /* 0x5c */ + + A_UINT32 hi_desired_baud_rate; /* 0x60 */ + A_UINT32 hi_dbglog_config; /* 0x64 */ + A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */ + A_UINT32 hi_mbox_io_block_sz; /* 0x6c */ + + A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */ + A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */ + + A_UINT32 hi_refclk_hz; /* 0x78 */ + A_UINT32 hi_ext_clk_detected; /* 0x7c */ +}; + +/* Bits defined in hi_option_flag */ +#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */ +#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */ + +/* + * Intended for use by Host software, this macro returns the Target RAM + * address of any item in the host_interest structure. + * Example: target_addr = AR6001_HOST_INTEREST_ITEM_ADDRESS(hi_board_data); + */ +#define AR6001_HOST_INTEREST_ITEM_ADDRESS(item) \ + ((A_UINT32)&((((struct host_interest_s *)(AR6001_HOST_INTEREST_ADDRESS))->item))) + +#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \ + ((A_UINT32)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item))) + + +#endif /* !__ASSEMBLER__ */ + +#endif /* __TARGADDRS_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/testcmd.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/testcmd.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/testcmd.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/testcmd.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,163 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2005 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef TESTCMD_H_ +#define TESTCMD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ZEROES_PATTERN = 0, + ONES_PATTERN, + REPEATING_10, + PN7_PATTERN, + PN9_PATTERN, + PN15_PATTERN +}TX_DATA_PATTERN; + +/* Continous tx + mode : TCMD_CONT_TX_OFF - Disabling continous tx + TCMD_CONT_TX_SINE - Enable continuous unmodulated tx + TCMD_CONT_TX_FRAME- Enable continuous modulated tx + freq : Channel freq in Mhz. (e.g 2412 for channel 1 in 11 g) +dataRate: 0 - 1 Mbps + 1 - 2 Mbps + 2 - 5.5 Mbps + 3 - 11 Mbps + 4 - 6 Mbps + 5 - 9 Mbps + 6 - 12 Mbps + 7 - 18 Mbps + 8 - 24 Mbps + 9 - 36 Mbps + 10 - 28 Mbps + 11 - 54 Mbps + txPwr: Tx power in dBm[5 -11] for unmod Tx, [5-14] for mod Tx +antenna: 1 - one antenna + 2 - two antenna +Note : Enable/disable continuous tx test cmd works only when target is awake. +*/ + +typedef enum { + TCMD_CONT_TX_OFF = 0, + TCMD_CONT_TX_SINE, + TCMD_CONT_TX_FRAME, + TCMD_CONT_TX_TX99, + TCMD_CONT_TX_TX100 +} TCMD_CONT_TX_MODE; + +typedef PREPACK struct { + A_UINT32 testCmdId; + A_UINT32 mode; + A_UINT32 freq; + A_UINT32 dataRate; + A_INT32 txPwr; + A_UINT32 antenna; + A_UINT32 enANI; + A_UINT32 scramblerOff; + A_UINT32 aifsn; + A_UINT16 pktSz; + A_UINT16 txPattern; +} POSTPACK TCMD_CONT_TX; + +#define TCMD_TXPATTERN_ZERONE 0x1 +#define TCMD_TXPATTERN_ZERONE_DIS_SCRAMBLE 0x2 + +/* Continuous Rx + act: TCMD_CONT_RX_PROMIS - promiscuous mode (accept all incoming frames) + TCMD_CONT_RX_FILTER - filter mode (accept only frames with dest + address equal specified + mac address (set via act =3) + TCMD_CONT_RX_REPORT off mode (disable cont rx mode and get the + report from the last cont + Rx test) + + TCMD_CONT_RX_SETMAC - set MacAddr mode (sets the MAC address for the + target. This Overrides + the default MAC address.) + +*/ +typedef enum { + TCMD_CONT_RX_PROMIS =0, + TCMD_CONT_RX_FILTER, + TCMD_CONT_RX_REPORT, + TCMD_CONT_RX_SETMAC, + TCMD_CONT_RX_SET_ANT_SWITCH_TABLE +} TCMD_CONT_RX_ACT; + +typedef PREPACK struct { + A_UINT32 testCmdId; + A_UINT32 act; + A_UINT32 enANI; + PREPACK union { + struct PREPACK TCMD_CONT_RX_PARA { + A_UINT32 freq; + A_UINT32 antenna; + } POSTPACK para; + struct PREPACK TCMD_CONT_RX_REPORT { + A_UINT32 totalPkt; + A_INT32 rssiInDBm; + } POSTPACK report; + struct PREPACK TCMD_CONT_RX_MAC { + A_UCHAR addr[ATH_MAC_LEN]; + } POSTPACK mac; + struct PREPACK TCMD_CONT_RX_ANT_SWITCH_TABLE { + A_UINT32 antswitch1; + A_UINT32 antswitch2; + }POSTPACK antswitchtable; + } POSTPACK u; +} POSTPACK TCMD_CONT_RX; + +/* Force sleep/wake test cmd + mode: TCMD_PM_WAKEUP - Wakeup the target + TCMD_PM_SLEEP - Force the target to sleep. + */ +typedef enum { + TCMD_PM_WAKEUP = 1, /* be consistent with target */ + TCMD_PM_SLEEP +} TCMD_PM_MODE; + +typedef PREPACK struct { + A_UINT32 testCmdId; + A_UINT32 mode; +} POSTPACK TCMD_PM; + +typedef enum { + TCMD_CONT_TX_ID, + TCMD_CONT_RX_ID, + TCMD_PM_ID +} TCMD_ID; + +typedef PREPACK union { + TCMD_CONT_TX contTx; + TCMD_CONT_RX contRx; + TCMD_PM pm; +} POSTPACK TEST_CMD; + +#ifdef __cplusplus +} +#endif + +#endif /* TESTCMD_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/wlan_api.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/wlan_api.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/wlan_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/wlan_api.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,110 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the API for the host wlan module +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HOST_WLAN_API_H_ +#define _HOST_WLAN_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +struct ieee80211_node_table; +struct ieee80211_frame; + +struct ieee80211_common_ie { + A_UINT16 ie_chan; + A_UINT8 *ie_tstamp; + A_UINT8 *ie_ssid; + A_UINT8 *ie_rates; + A_UINT8 *ie_xrates; + A_UINT8 *ie_country; + A_UINT8 *ie_wpa; + A_UINT8 *ie_rsn; + A_UINT8 *ie_wmm; + A_UINT8 *ie_ath; + A_UINT16 ie_capInfo; + A_UINT16 ie_beaconInt; + A_UINT8 *ie_tim; + A_UINT8 *ie_chswitch; + A_UINT8 ie_erp; + A_UINT8 *ie_wsc; +}; + +typedef struct bss { + A_UINT8 ni_macaddr[6]; + A_UINT8 ni_snr; + A_INT16 ni_rssi; + struct bss *ni_list_next; + struct bss *ni_list_prev; + struct bss *ni_hash_next; + struct bss *ni_hash_prev; + struct ieee80211_common_ie ni_cie; + A_UINT8 *ni_buf; + struct ieee80211_node_table *ni_table; + A_UINT32 ni_refcnt; + int ni_scangen; + A_UINT32 ni_tstamp; +#ifdef OS_ROAM_MANAGEMENT + A_UINT32 ni_si_gen; +#endif +} bss_t; + +typedef void wlan_node_iter_func(void *arg, bss_t *); + +bss_t *wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size); +void wlan_node_free(bss_t *ni); +void wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni, + const A_UINT8 *macaddr); +bss_t *wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr); +void wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni); +void wlan_free_allnodes(struct ieee80211_node_table *nt); +void wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f, + void *arg); + +void wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt); +void wlan_node_table_reset(struct ieee80211_node_table *nt); +void wlan_node_table_cleanup(struct ieee80211_node_table *nt); + +A_STATUS wlan_parse_beacon(A_UINT8 *buf, int framelen, + struct ieee80211_common_ie *cie); + +A_UINT16 wlan_ieee2freq(int chan); +A_UINT32 wlan_freq2ieee(A_UINT16 freq); + +void wlan_set_nodeage(struct ieee80211_node_table *nt, A_UINT32 nodeAge); + +bss_t * +wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID); + +void +wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni); + +bss_t *wlan_node_remove(struct ieee80211_node_table *nt, A_UINT8 *bssid); + +#ifdef __cplusplus +} +#endif + +#endif /* _HOST_WLAN_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/wmi.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/wmi.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/wmi.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/wmi.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,1871 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +/* + * This file contains the definitions of the WMI protocol specified in the + * Wireless Module Interface (WMI). It includes definitions of all the + * commands and events. Commands are messages from the host to the WM. + * Events and Replies are messages from the WM to the host. + * + * Ownership of correctness in regards to WMI commands + * belongs to the host driver and the WM is not required to validate + * parameters for value, proper range, or any other checking. + * + */ + +#ifndef _WMI_H_ +#define _WMI_H_ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#include "wmix.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HTC_PROTOCOL_VERSION 0x0002 +#define HTC_PROTOCOL_REVISION 0x0000 + +#define WMI_PROTOCOL_VERSION 0x0002 +#define WMI_PROTOCOL_REVISION 0x0000 + +#define ATH_MAC_LEN 6 /* length of mac in bytes */ +#define WMI_CMD_MAX_LEN 100 +#define WMI_CONTROL_MSG_MAX_LEN 256 +#define WMI_OPT_CONTROL_MSG_MAX_LEN 1536 +#define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600) +#define RFC1042OUI {0x00, 0x00, 0x00} + +#define IP_ETHERTYPE 0x0800 + +#define WMI_IMPLICIT_PSTREAM 0xFF +#define WMI_MAX_THINSTREAM 15 + +struct host_app_area_s { + A_UINT32 wmi_protocol_ver; +}; + +/* + * Data Path + */ +typedef PREPACK struct { + A_UINT8 dstMac[ATH_MAC_LEN]; + A_UINT8 srcMac[ATH_MAC_LEN]; + A_UINT16 typeOrLen; +} POSTPACK ATH_MAC_HDR; + +typedef PREPACK struct { + A_UINT8 dsap; + A_UINT8 ssap; + A_UINT8 cntl; + A_UINT8 orgCode[3]; + A_UINT16 etherType; +} POSTPACK ATH_LLC_SNAP_HDR; + +typedef enum { + DATA_MSGTYPE = 0x0, + CNTL_MSGTYPE, + SYNC_MSGTYPE, + OPT_MSGTYPE, +} WMI_MSG_TYPE; + + +typedef PREPACK struct { + A_INT8 rssi; + A_UINT8 info; /* WMI_MSG_TYPE in lower 2 bits - b1b0 */ + /* UP in next 3 bits - b4b3b2 */ +#define WMI_DATA_HDR_MSG_TYPE_MASK 0x03 +#define WMI_DATA_HDR_MSG_TYPE_SHIFT 0 +#define WMI_DATA_HDR_UP_MASK 0x07 +#define WMI_DATA_HDR_UP_SHIFT 2 +#define WMI_DATA_HDR_IS_MSG_TYPE(h, t) (((h)->info & (WMI_DATA_HDR_MSG_TYPE_MASK)) == (t)) +} POSTPACK WMI_DATA_HDR; + + +#define WMI_DATA_HDR_SET_MSG_TYPE(h, t) (h)->info = (((h)->info & ~(WMI_DATA_HDR_MSG_TYPE_MASK << WMI_DATA_HDR_MSG_TYPE_SHIFT)) | (t << WMI_DATA_HDR_MSG_TYPE_SHIFT)) +#define WMI_DATA_HDR_SET_UP(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_UP_MASK << WMI_DATA_HDR_UP_SHIFT)) | (p << WMI_DATA_HDR_UP_SHIFT)) + +/* + * Control Path + */ +typedef PREPACK struct { + A_UINT16 commandId; +} POSTPACK WMI_CMD_HDR; /* used for commands and events */ + +/* + * List of Commnands + */ +typedef enum { + WMI_CONNECT_CMDID = 0x0001, + WMI_RECONNECT_CMDID, + WMI_DISCONNECT_CMDID, + WMI_SYNCHRONIZE_CMDID, + WMI_CREATE_PSTREAM_CMDID, + WMI_DELETE_PSTREAM_CMDID, + WMI_START_SCAN_CMDID, + WMI_SET_SCAN_PARAMS_CMDID, + WMI_SET_BSS_FILTER_CMDID, + WMI_SET_PROBED_SSID_CMDID, + WMI_SET_LISTEN_INT_CMDID, + WMI_SET_BMISS_TIME_CMDID, + WMI_SET_DISC_TIMEOUT_CMDID, + WMI_GET_CHANNEL_LIST_CMDID, + WMI_SET_BEACON_INT_CMDID, + WMI_GET_STATISTICS_CMDID, + WMI_SET_CHANNEL_PARAMS_CMDID, + WMI_SET_POWER_MODE_CMDID, + WMI_SET_IBSS_PM_CAPS_CMDID, + WMI_SET_POWER_PARAMS_CMDID, + WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID, + WMI_ADD_CIPHER_KEY_CMDID, + WMI_DELETE_CIPHER_KEY_CMDID, + WMI_ADD_KRK_CMDID, + WMI_DELETE_KRK_CMDID, + WMI_SET_PMKID_CMDID, + WMI_SET_TX_PWR_CMDID, + WMI_GET_TX_PWR_CMDID, + WMI_SET_ASSOC_INFO_CMDID, + WMI_ADD_BAD_AP_CMDID, + WMI_DELETE_BAD_AP_CMDID, + WMI_SET_TKIP_COUNTERMEASURES_CMDID, + WMI_RSSI_THRESHOLD_PARAMS_CMDID, + WMI_TARGET_ERROR_REPORT_BITMASK_CMDID, + WMI_SET_ACCESS_PARAMS_CMDID, + WMI_SET_RETRY_LIMITS_CMDID, + WMI_SET_OPT_MODE_CMDID, + WMI_OPT_TX_FRAME_CMDID, + WMI_SET_VOICE_PKT_SIZE_CMDID, + WMI_SET_MAX_SP_LEN_CMDID, + WMI_SET_ROAM_CTRL_CMDID, + WMI_GET_ROAM_TBL_CMDID, + WMI_GET_ROAM_DATA_CMDID, + WMI_ENABLE_RM_CMDID, + WMI_SET_MAX_OFFHOME_DURATION_CMDID, + WMI_EXTENSION_CMDID, /* Non-wireless extensions */ + WMI_SNR_THRESHOLD_PARAMS_CMDID, + WMI_LQ_THRESHOLD_PARAMS_CMDID, + WMI_SET_LPREAMBLE_CMDID, + WMI_SET_RTS_CMDID, + WMI_CLR_RSSI_SNR_CMDID, + WMI_SET_FIXRATES_CMDID, + WMI_GET_FIXRATES_CMDID, + WMI_SET_AUTH_MODE_CMDID, + WMI_SET_REASSOC_MODE_CMDID, + WMI_SET_WMM_CMDID, + WMI_SET_WMM_TXOP_CMDID, + WMI_TEST_CMDID, + WMI_SET_BT_STATUS_CMDID, + WMI_SET_BT_PARAMS_CMDID, + + WMI_SET_KEEPALIVE_CMDID, + WMI_GET_KEEPALIVE_CMDID, + WMI_SET_APPIE_CMDID, + WMI_GET_APPIE_CMDID, + WMI_SET_WSC_STATUS_CMDID, + + /* Wake on Wireless */ + WMI_SET_HOST_SLEEP_MODE_CMDID, + WMI_SET_WOW_MODE_CMDID, + WMI_GET_WOW_LIST_CMDID, + WMI_ADD_WOW_PATTERN_CMDID, + WMI_DEL_WOW_PATTERN_CMDID, + + /* + * Developer commands starts at 0xF000 + */ + WMI_SET_BITRATE_CMDID = 0xF000, + WMI_GET_BITRATE_CMDID, + WMI_SET_WHALPARAM_CMDID, + + + /*Should add the new command to the tail for compatible with + * etna. + */ + WMI_SET_MAC_ADDRESS_CMDID, + WMI_SET_AKMP_PARAMS_CMDID, + WMI_SET_PMKID_LIST_CMDID, + WMI_GET_PMKID_LIST_CMDID, + WMI_ABORT_SCAN_CMDID, + WMI_SET_TARGET_EVENT_REPORT_CMDID, + + WMI_SET_MCAST_FILTER_CMDID, + WMI_DEL_MCAST_FILTER_CMDID +} WMI_COMMAND_ID; + +/* + * Frame Types + */ +typedef enum { + WMI_FRAME_BEACON = 0, + WMI_FRAME_PROBE_REQ, + WMI_FRAME_PROBE_RESP, + WMI_FRAME_ASSOC_REQ, + WMI_FRAME_ASSOC_RESP, + WMI_NUM_MGMT_FRAME +} WMI_MGMT_FRAME_TYPE; + +/* + * Connect Command + */ +typedef enum { + INFRA_NETWORK = 0x01, + ADHOC_NETWORK = 0x02, + ADHOC_CREATOR = 0x04, + OPT_NETWORK = 0x08, +} NETWORK_TYPE; + +typedef enum { + OPEN_AUTH = 0x01, + SHARED_AUTH = 0x02, + LEAP_AUTH = 0x04, /* different from IEEE_AUTH_MODE definitions */ +} DOT11_AUTH_MODE; + +typedef enum { + NONE_AUTH = 0x01, + WPA_AUTH = 0x02, + WPA_PSK_AUTH = 0x03, + WPA2_AUTH = 0x04, + WPA2_PSK_AUTH = 0x05, + WPA_AUTH_CCKM = 0x06, + WPA2_AUTH_CCKM = 0x07, +} AUTH_MODE; + +typedef enum { + NONE_CRYPT = 0x01, + WEP_CRYPT = 0x02, + TKIP_CRYPT = 0x03, + AES_CRYPT = 0x04, +#ifdef WAPI_ENABLE + WAPI_CRYPT = 0x05, +#endif /* WAPI_ENABLE */ +} CRYPTO_TYPE; + +#define WMI_MIN_CRYPTO_TYPE NONE_CRYPT +#ifndef WAPI_ENABLE +#define WMI_MAX_CRYPTO_TYPE (AES_CRYPT + 1) +#else +#define WMI_MAX_CRYPTO_TYPE (WAPI_CRYPT + 1) +#endif /* WAPI_ENABLE */ + +#define WMI_MIN_KEY_INDEX 0 +#ifndef WAPI_ENABLE +#define WMI_MAX_KEY_INDEX 3 +#else +#define WMI_MAX_KEY_INDEX 7 /* wapi grpKey 0-3, prwKey 4-7 */ +#endif + +#define WMI_MAX_KEY_LEN 32 + +#define WMI_MAX_SSID_LEN 32 + +typedef enum { + CONNECT_ASSOC_POLICY_USER = 0x0001, + CONNECT_SEND_REASSOC = 0x0002, + CONNECT_IGNORE_WPAx_GROUP_CIPHER = 0x0004, + CONNECT_PROFILE_MATCH_DONE = 0x0008, + CONNECT_IGNORE_AAC_BEACON = 0x0010, + CONNECT_CSA_FOLLOW_BSS = 0x0020, +} WMI_CONNECT_CTRL_FLAGS_BITS; + +#define DEFAULT_CONNECT_CTRL_FLAGS (CONNECT_CSA_FOLLOW_BSS) + +typedef PREPACK struct { + A_UINT8 networkType; + A_UINT8 dot11AuthMode; + A_UINT8 authMode; + A_UINT8 pairwiseCryptoType; + A_UINT8 pairwiseCryptoLen; + A_UINT8 groupCryptoType; + A_UINT8 groupCryptoLen; + A_UINT8 ssidLength; + A_UCHAR ssid[WMI_MAX_SSID_LEN]; + A_UINT16 channel; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT32 ctrl_flags; +} POSTPACK WMI_CONNECT_CMD; + +/* + * WMI_RECONNECT_CMDID + */ +typedef PREPACK struct { + A_UINT16 channel; /* hint */ + A_UINT8 bssid[ATH_MAC_LEN]; /* mandatory if set */ +} POSTPACK WMI_RECONNECT_CMD; + +/* + * WMI_ADD_CIPHER_KEY_CMDID + */ +typedef enum { + PAIRWISE_USAGE = 0x00, + GROUP_USAGE = 0x01, + TX_USAGE = 0x02, /* default Tx Key - Static WEP only */ +} KEY_USAGE; + +/* + * Bit Flag + * Bit 0 - Initialise TSC - default is Initialize + */ +#define KEY_OP_INIT_TSC 0x01 +#define KEY_OP_INIT_RSC 0x02 + +#define KEY_OP_INIT_VAL 0x03 /* Default Initialise the TSC & RSC */ +#define KEY_OP_VALID_MASK 0x03 + +typedef PREPACK struct { + A_UINT8 keyIndex; + A_UINT8 keyType; + A_UINT8 keyUsage; /* KEY_USAGE */ + A_UINT8 keyLength; + A_UINT8 keyRSC[8]; /* key replay sequence counter */ + A_UINT8 key[WMI_MAX_KEY_LEN]; + A_UINT8 key_op_ctrl; /* Additional Key Control information */ +} POSTPACK WMI_ADD_CIPHER_KEY_CMD; + +/* + * WMI_DELETE_CIPHER_KEY_CMDID + */ +typedef PREPACK struct { + A_UINT8 keyIndex; +} POSTPACK WMI_DELETE_CIPHER_KEY_CMD; + +#define WMI_KRK_LEN 16 +/* + * WMI_ADD_KRK_CMDID + */ +typedef PREPACK struct { + A_UINT8 krk[WMI_KRK_LEN]; +} POSTPACK WMI_ADD_KRK_CMD; + +/* + * WMI_SET_TKIP_COUNTERMEASURES_CMDID + */ +typedef enum { + WMI_TKIP_CM_DISABLE = 0x0, + WMI_TKIP_CM_ENABLE = 0x1, +} WMI_TKIP_CM_CONTROL; + +typedef PREPACK struct { + A_UINT8 cm_en; /* WMI_TKIP_CM_CONTROL */ +} POSTPACK WMI_SET_TKIP_COUNTERMEASURES_CMD; + +/* + * WMI_SET_PMKID_CMDID + */ + +#define WMI_PMKID_LEN 16 + +typedef enum { + PMKID_DISABLE = 0, + PMKID_ENABLE = 1, +} PMKID_ENABLE_FLG; + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT8 enable; /* PMKID_ENABLE_FLG */ + A_UINT8 pmkid[WMI_PMKID_LEN]; +} POSTPACK WMI_SET_PMKID_CMD; + +/* + * WMI_START_SCAN_CMD + */ +typedef enum { + WMI_LONG_SCAN = 0, + WMI_SHORT_SCAN = 1, +} WMI_SCAN_TYPE; + +typedef PREPACK struct { + A_BOOL forceFgScan; + A_BOOL isLegacy; /* For Legacy Cisco AP compatibility */ + A_UINT32 homeDwellTime; /* Maximum duration in the home channel(milliseconds) */ + A_UINT32 forceScanInterval; /* Time interval between scans (milliseconds)*/ + A_UINT8 scanType; /* WMI_SCAN_TYPE */ + A_UINT8 numChannels; /* how many channels follow */ + A_UINT16 channelList[1]; /* channels in Mhz */ +} POSTPACK WMI_START_SCAN_CMD; + +/* + * WMI_SET_SCAN_PARAMS_CMDID + */ +#define WMI_SHORTSCANRATIO_DEFAULT 3 +typedef enum { + CONNECT_SCAN_CTRL_FLAGS = 0x01, /* set if can scan in the Connect cmd */ + SCAN_CONNECTED_CTRL_FLAGS = 0x02, /* set if scan for the SSID it is */ + /* already connected to */ + ACTIVE_SCAN_CTRL_FLAGS = 0x04, /* set if enable active scan */ + ROAM_SCAN_CTRL_FLAGS = 0x08, /* set if enable roam scan when bmiss and lowrssi */ + REPORT_BSSINFO_CTRL_FLAGS = 0x10, /* set if follows customer BSSINFO reporting rule */ + ENABLE_AUTO_CTRL_FLAGS = 0x20, /* if disabled, target doesn't + scan after a disconnect event */ + ENABLE_SCAN_ABORT_EVENT = 0x40 /* Scan complete event with canceled status will be generated when a scan is prempted before it gets completed */ + +} WMI_SCAN_CTRL_FLAGS_BITS; + +#define CAN_SCAN_IN_CONNECT(flags) (flags & CONNECT_SCAN_CTRL_FLAGS) +#define CAN_SCAN_CONNECTED(flags) (flags & SCAN_CONNECTED_CTRL_FLAGS) +#define ENABLE_ACTIVE_SCAN(flags) (flags & ACTIVE_SCAN_CTRL_FLAGS) +#define ENABLE_ROAM_SCAN(flags) (flags & ROAM_SCAN_CTRL_FLAGS) +#define CONFIG_REPORT_BSSINFO(flags) (flags & REPORT_BSSINFO_CTRL_FLAGS) +#define IS_AUTO_SCAN_ENABLED(flags) (flags & ENABLE_AUTO_CTRL_FLAGS) +#define SCAN_ABORT_EVENT_ENABLED(flags) (flags & ENABLE_SCAN_ABORT_EVENT) + +#define DEFAULT_SCAN_CTRL_FLAGS (CONNECT_SCAN_CTRL_FLAGS| SCAN_CONNECTED_CTRL_FLAGS| ACTIVE_SCAN_CTRL_FLAGS| ROAM_SCAN_CTRL_FLAGS | ENABLE_AUTO_CTRL_FLAGS) + + +typedef PREPACK struct { + A_UINT16 fg_start_period; /* seconds */ + A_UINT16 fg_end_period; /* seconds */ + A_UINT16 bg_period; /* seconds */ + A_UINT16 maxact_chdwell_time; /* msec */ + A_UINT16 pas_chdwell_time; /* msec */ + A_UINT8 shortScanRatio; /* how many shorts scan for one long */ + A_UINT8 scanCtrlFlags; + A_UINT16 minact_chdwell_time; /* msec */ + A_UINT16 reserved; /* alignment */ + A_UINT32 max_dfsch_act_time; /* msecs */ +} POSTPACK WMI_SCAN_PARAMS_CMD; + +/* + * WMI_SET_BSS_FILTER_CMDID + */ +typedef enum { + NONE_BSS_FILTER = 0x0, /* no beacons forwarded */ + ALL_BSS_FILTER, /* all beacons forwarded */ + PROFILE_FILTER, /* only beacons matching profile */ + ALL_BUT_PROFILE_FILTER, /* all but beacons matching profile */ + CURRENT_BSS_FILTER, /* only beacons matching current BSS */ + ALL_BUT_BSS_FILTER, /* all but beacons matching BSS */ + PROBED_SSID_FILTER, /* beacons matching probed ssid */ + LAST_BSS_FILTER, /* marker only */ +} WMI_BSS_FILTER; + +typedef PREPACK struct { + A_UINT8 bssFilter; /* see WMI_BSS_FILTER */ + A_UINT8 reserved1; /* For alignment */ + A_UINT16 reserved2; /* For alignment */ + A_UINT32 ieMask; +} POSTPACK WMI_BSS_FILTER_CMD; + +/* + * WMI_SET_PROBED_SSID_CMDID + */ +#define MAX_PROBED_SSID_INDEX 5 + +typedef enum { + DISABLE_SSID_FLAG = 0, /* disables entry */ + SPECIFIC_SSID_FLAG = 0x01, /* probes specified ssid */ + ANY_SSID_FLAG = 0x02, /* probes for any ssid */ +} WMI_SSID_FLAG; + +typedef PREPACK struct { + A_UINT8 entryIndex; /* 0 to MAX_PROBED_SSID_INDEX */ + A_UINT8 flag; /* WMI_SSID_FLG */ + A_UINT8 ssidLength; + A_UINT8 ssid[32]; +} POSTPACK WMI_PROBED_SSID_CMD; + +/* + * WMI_SET_LISTEN_INT_CMDID + * The Listen interval is between 15 and 3000 TUs + */ +#define MIN_LISTEN_INTERVAL 15 +#define MAX_LISTEN_INTERVAL 5000 +#define MIN_LISTEN_BEACONS 1 +#define MAX_LISTEN_BEACONS 50 + +typedef PREPACK struct { + A_UINT16 listenInterval; + A_UINT16 numBeacons; +} POSTPACK WMI_LISTEN_INT_CMD; + +/* + * WMI_SET_BEACON_INT_CMDID + */ +typedef PREPACK struct { + A_UINT16 beaconInterval; +} POSTPACK WMI_BEACON_INT_CMD; + +/* + * WMI_SET_BMISS_TIME_CMDID + * valid values are between 1000 and 5000 TUs + */ + +#define MIN_BMISS_TIME 1000 +#define MAX_BMISS_TIME 5000 +#define MIN_BMISS_BEACONS 1 +#define MAX_BMISS_BEACONS 50 + +typedef PREPACK struct { + A_UINT16 bmissTime; + A_UINT16 numBeacons; +} POSTPACK WMI_BMISS_TIME_CMD; + +/* + * WMI_SET_POWER_MODE_CMDID + */ +typedef enum { + REC_POWER = 0x01, + MAX_PERF_POWER, +} WMI_POWER_MODE; + +typedef PREPACK struct { + A_UINT8 powerMode; /* WMI_POWER_MODE */ +} POSTPACK WMI_POWER_MODE_CMD; + +/* + * WMI_SET_POWER_PARAMS_CMDID + */ +typedef enum { + IGNORE_DTIM = 0x01, + NORMAL_DTIM = 0x02, + STICK_DTIM = 0x03, +} WMI_DTIM_POLICY; + +typedef PREPACK struct { + A_UINT16 idle_period; /* msec */ + A_UINT16 pspoll_number; + A_UINT16 dtim_policy; +} POSTPACK WMI_POWER_PARAMS_CMD; + +typedef PREPACK struct { + A_UINT8 power_saving; + A_UINT8 ttl; /* number of beacon periods */ + A_UINT16 atim_windows; /* msec */ + A_UINT16 timeout_value; /* msec */ +} POSTPACK WMI_IBSS_PM_CAPS_CMD; + +/* + * WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID + */ +typedef enum { + IGNORE_TIM_ALL_QUEUES_APSD = 0, + PROCESS_TIM_ALL_QUEUES_APSD = 1, + IGNORE_TIM_SIMULATED_APSD = 2, + PROCESS_TIM_SIMULATED_APSD = 3, +} APSD_TIM_POLICY; + +typedef PREPACK struct { + A_UINT16 psPollTimeout; /* msec */ + A_UINT16 triggerTimeout; /* msec */ + A_UINT32 apsdTimPolicy; /* TIM behavior with ques APSD enabled. Default is IGNORE_TIM_ALL_QUEUES_APSD */ + A_UINT32 simulatedAPSDTimPolicy; /* TIM behavior with simulated APSD enabled. Default is PROCESS_TIM_SIMULATED_APSD */ +} POSTPACK WMI_POWERSAVE_TIMERS_POLICY_CMD; + +/* + * WMI_SET_VOICE_PKT_SIZE_CMDID + */ +typedef PREPACK struct { + A_UINT16 voicePktSize; +} POSTPACK WMI_SET_VOICE_PKT_SIZE_CMD; + +/* + * WMI_SET_MAX_SP_LEN_CMDID + */ +typedef enum { + DELIVER_ALL_PKT = 0x0, + DELIVER_2_PKT = 0x1, + DELIVER_4_PKT = 0x2, + DELIVER_6_PKT = 0x3, +} APSD_SP_LEN_TYPE; + +typedef PREPACK struct { + A_UINT8 maxSPLen; +} POSTPACK WMI_SET_MAX_SP_LEN_CMD; + +/* + * WMI_SET_DISC_TIMEOUT_CMDID + */ +typedef PREPACK struct { + A_UINT8 disconnectTimeout; /* seconds */ +} POSTPACK WMI_DISC_TIMEOUT_CMD; + +typedef enum { + UPLINK_TRAFFIC = 0, + DNLINK_TRAFFIC = 1, + BIDIR_TRAFFIC = 2, +} DIR_TYPE; + +typedef enum { + DISABLE_FOR_THIS_AC = 0, + ENABLE_FOR_THIS_AC = 1, + ENABLE_FOR_ALL_AC = 2, +} VOICEPS_CAP_TYPE; + +typedef enum { + TRAFFIC_TYPE_APERIODIC = 0, + TRAFFIC_TYPE_PERIODIC = 1, +}TRAFFIC_TYPE; + +/* + * WMI_SYNCHRONIZE_CMDID + */ +typedef PREPACK struct { + A_UINT8 dataSyncMap; +} POSTPACK WMI_SYNC_CMD; + +/* + * WMI_CREATE_PSTREAM_CMDID + */ +typedef PREPACK struct { + A_UINT32 minServiceInt; /* in milli-sec */ + A_UINT32 maxServiceInt; /* in milli-sec */ + A_UINT32 inactivityInt; /* in milli-sec */ + A_UINT32 suspensionInt; /* in milli-sec */ + A_UINT32 serviceStartTime; + A_UINT32 minDataRate; /* in bps */ + A_UINT32 meanDataRate; /* in bps */ + A_UINT32 peakDataRate; /* in bps */ + A_UINT32 maxBurstSize; + A_UINT32 delayBound; + A_UINT32 minPhyRate; /* in bps */ + A_UINT32 sba; + A_UINT32 mediumTime; + A_UINT16 nominalMSDU; /* in octects */ + A_UINT16 maxMSDU; /* in octects */ + A_UINT8 trafficClass; + A_UINT8 trafficDirection; /* DIR_TYPE */ + A_UINT8 rxQueueNum; + A_UINT8 trafficType; /* TRAFFIC_TYPE */ + A_UINT8 voicePSCapability; /* VOICEPS_CAP_TYPE */ + A_UINT8 tsid; + A_UINT8 userPriority; /* 802.1D user priority */ +} POSTPACK WMI_CREATE_PSTREAM_CMD; + +/* + * WMI_DELETE_PSTREAM_CMDID + */ +typedef PREPACK struct { + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficDirection; + A_UINT8 trafficClass; + A_UINT8 tsid; +} POSTPACK WMI_DELETE_PSTREAM_CMD; + +/* + * WMI_SET_CHANNEL_PARAMS_CMDID + */ +typedef enum { + WMI_11A_MODE = 0x1, + WMI_11G_MODE = 0x2, + WMI_11AG_MODE = 0x3, + WMI_11B_MODE = 0x4, + WMI_11GONLY_MODE = 0x5, +} WMI_PHY_MODE; + +#define WMI_MAX_CHANNELS 32 + +typedef PREPACK struct { + A_UINT8 reserved1; + A_UINT8 scanParam; /* set if enable scan */ + A_UINT8 phyMode; /* see WMI_PHY_MODE */ + A_UINT8 numChannels; /* how many channels follow */ + A_UINT16 channelList[1]; /* channels in Mhz */ +} POSTPACK WMI_CHANNEL_PARAMS_CMD; + + +/* + * WMI_RSSI_THRESHOLD_PARAMS_CMDID + * Setting the polltime to 0 would disable polling. + * Threshold values are in the ascending order, and should agree to: + * (lowThreshold_lowerVal < lowThreshold_upperVal < highThreshold_lowerVal + * < highThreshold_upperVal) + */ + +typedef PREPACK struct WMI_RSSI_THRESHOLD_PARAMS{ + A_UINT32 pollTime; /* Polling time as a factor of LI */ + A_INT16 thresholdAbove1_Val; /* lowest of upper */ + A_INT16 thresholdAbove2_Val; + A_INT16 thresholdAbove3_Val; + A_INT16 thresholdAbove4_Val; + A_INT16 thresholdAbove5_Val; + A_INT16 thresholdAbove6_Val; /* highest of upper */ + A_INT16 thresholdBelow1_Val; /* lowest of bellow */ + A_INT16 thresholdBelow2_Val; + A_INT16 thresholdBelow3_Val; + A_INT16 thresholdBelow4_Val; + A_INT16 thresholdBelow5_Val; + A_INT16 thresholdBelow6_Val; /* highest of bellow */ + A_UINT8 weight; /* "alpha" */ + A_UINT8 reserved[3]; +} POSTPACK WMI_RSSI_THRESHOLD_PARAMS_CMD; + +/* + * WMI_SNR_THRESHOLD_PARAMS_CMDID + * Setting the polltime to 0 would disable polling. + */ + +typedef PREPACK struct WMI_SNR_THRESHOLD_PARAMS{ + A_UINT32 pollTime; /* Polling time as a factor of LI */ + A_UINT8 weight; /* "alpha" */ + A_UINT8 thresholdAbove1_Val; /* lowest of uppper*/ + A_UINT8 thresholdAbove2_Val; + A_UINT8 thresholdAbove3_Val; + A_UINT8 thresholdAbove4_Val; /* highest of upper */ + A_UINT8 thresholdBelow1_Val; /* lowest of bellow */ + A_UINT8 thresholdBelow2_Val; + A_UINT8 thresholdBelow3_Val; + A_UINT8 thresholdBelow4_Val; /* highest of bellow */ + A_UINT8 reserved[3]; +} POSTPACK WMI_SNR_THRESHOLD_PARAMS_CMD; + +/* + * WMI_LQ_THRESHOLD_PARAMS_CMDID + */ +typedef PREPACK struct WMI_LQ_THRESHOLD_PARAMS { + A_UINT8 enable; + A_UINT8 thresholdAbove1_Val; + A_UINT8 thresholdAbove2_Val; + A_UINT8 thresholdAbove3_Val; + A_UINT8 thresholdAbove4_Val; + A_UINT8 thresholdBelow1_Val; + A_UINT8 thresholdBelow2_Val; + A_UINT8 thresholdBelow3_Val; + A_UINT8 thresholdBelow4_Val; + A_UINT8 reserved[3]; +} POSTPACK WMI_LQ_THRESHOLD_PARAMS_CMD; + +typedef enum { + WMI_LPREAMBLE_DISABLED = 0, + WMI_LPREAMBLE_ENABLED +} WMI_LPREAMBLE_STATUS; + +typedef PREPACK struct { + A_UINT8 status; +}POSTPACK WMI_SET_LPREAMBLE_CMD; + +typedef PREPACK struct { + A_UINT16 threshold; +}POSTPACK WMI_SET_RTS_CMD; + +/* + * WMI_TARGET_ERROR_REPORT_BITMASK_CMDID + * Sets the error reporting event bitmask in target. Target clears it + * upon an error. Subsequent errors are counted, but not reported + * via event, unless the bitmask is set again. + */ +typedef PREPACK struct { + A_UINT32 bitmask; +} POSTPACK WMI_TARGET_ERROR_REPORT_BITMASK; + +/* + * WMI_SET_TX_PWR_CMDID + */ +typedef PREPACK struct { + A_UINT8 dbM; /* in dbM units */ +} POSTPACK WMI_SET_TX_PWR_CMD, WMI_TX_PWR_REPLY; + +/* + * WMI_SET_ASSOC_INFO_CMDID + * + * A maximum of 2 private IEs can be sent in the [Re]Assoc request. + * A 3rd one, the CCX version IE can also be set from the host. + */ +#define WMI_MAX_ASSOC_INFO_TYPE 2 +#define WMI_CCX_VER_IE 2 /* ieType to set CCX Version IE */ + +#define WMI_MAX_ASSOC_INFO_LEN 240 + +typedef PREPACK struct { + A_UINT8 ieType; + A_UINT8 bufferSize; + A_UINT8 assocInfo[1]; /* up to WMI_MAX_ASSOC_INFO_LEN */ +} POSTPACK WMI_SET_ASSOC_INFO_CMD; + + +/* + * WMI_GET_TX_PWR_CMDID does not take any parameters + */ + +/* + * WMI_ADD_BAD_AP_CMDID + */ +#define WMI_MAX_BAD_AP_INDEX 1 + +typedef PREPACK struct { + A_UINT8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */ + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_ADD_BAD_AP_CMD; + +/* + * WMI_DELETE_BAD_AP_CMDID + */ +typedef PREPACK struct { + A_UINT8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */ +} POSTPACK WMI_DELETE_BAD_AP_CMD; + +/* + * WMI_SET_ACCESS_PARAMS_CMDID + */ +#define WMI_DEFAULT_TXOP_ACPARAM 0 /* implies one MSDU */ +#define WMI_DEFAULT_ECWMIN_ACPARAM 4 /* corresponds to CWmin of 15 */ +#define WMI_DEFAULT_ECWMAX_ACPARAM 10 /* corresponds to CWmax of 1023 */ +#define WMI_MAX_CW_ACPARAM 15 /* maximum eCWmin or eCWmax */ +#define WMI_DEFAULT_AIFSN_ACPARAM 2 +#define WMI_MAX_AIFSN_ACPARAM 15 +typedef PREPACK struct { + A_UINT16 txop; /* in units of 32 usec */ + A_UINT8 eCWmin; + A_UINT8 eCWmax; + A_UINT8 aifsn; +} POSTPACK WMI_SET_ACCESS_PARAMS_CMD; + + +/* + * WMI_SET_RETRY_LIMITS_CMDID + * + * This command is used to customize the number of retries the + * wlan device will perform on a given frame. + */ +#define WMI_MIN_RETRIES 2 +#define WMI_MAX_RETRIES 13 +typedef enum { + MGMT_FRAMETYPE = 0, + CONTROL_FRAMETYPE = 1, + DATA_FRAMETYPE = 2 +} WMI_FRAMETYPE; + +typedef PREPACK struct { + A_UINT8 frameType; /* WMI_FRAMETYPE */ + A_UINT8 trafficClass; /* applies only to DATA_FRAMETYPE */ + A_UINT8 maxRetries; + A_UINT8 enableNotify; +} POSTPACK WMI_SET_RETRY_LIMITS_CMD; + +/* + * WMI_SET_ROAM_CTRL_CMDID + * + * This command is used to influence the Roaming behaviour + * Set the host biases of the BSSs before setting the roam mode as bias + * based. + */ + +/* + * Different types of Roam Control + */ + +typedef enum { + WMI_FORCE_ROAM = 1, /* Roam to the specified BSSID */ + WMI_SET_ROAM_MODE = 2, /* default ,progd bias, no roam */ + WMI_SET_HOST_BIAS = 3, /* Set the Host Bias */ + WMI_SET_LOWRSSI_SCAN_PARAMS = 4, /* Set lowrssi Scan parameters */ +} WMI_ROAM_CTRL_TYPE; + +#define WMI_MIN_ROAM_CTRL_TYPE WMI_FORCE_ROAM +#define WMI_MAX_ROAM_CTRL_TYPE WMI_SET_LOWRSSI_SCAN_PARAMS + +/* + * ROAM MODES + */ + +typedef enum { + WMI_DEFAULT_ROAM_MODE = 1, /* RSSI based ROAM */ + WMI_HOST_BIAS_ROAM_MODE = 2, /* HOST BIAS based ROAM */ + WMI_LOCK_BSS_MODE = 3 /* Lock to the Current BSS - no Roam */ +} WMI_ROAM_MODE; + +/* + * BSS HOST BIAS INFO + */ + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_INT8 bias; +} POSTPACK WMI_BSS_BIAS; + +typedef PREPACK struct { + A_UINT8 numBss; + WMI_BSS_BIAS bssBias[1]; +} POSTPACK WMI_BSS_BIAS_INFO; + +typedef PREPACK struct WMI_LOWRSSI_SCAN_PARAMS { + A_UINT16 lowrssi_scan_period; + A_INT16 lowrssi_scan_threshold; + A_INT16 lowrssi_roam_threshold; + A_UINT8 roam_rssi_floor; + A_UINT8 reserved[1]; /* For alignment */ +} POSTPACK WMI_LOWRSSI_SCAN_PARAMS; + +typedef PREPACK struct { + PREPACK union { + A_UINT8 bssid[ATH_MAC_LEN]; /* WMI_FORCE_ROAM */ + A_UINT8 roamMode; /* WMI_SET_ROAM_MODE */ + WMI_BSS_BIAS_INFO bssBiasInfo; /* WMI_SET_HOST_BIAS */ + WMI_LOWRSSI_SCAN_PARAMS lrScanParams; + } POSTPACK info; + A_UINT8 roamCtrlType ; +} POSTPACK WMI_SET_ROAM_CTRL_CMD; + +/* + * WMI_ENABLE_RM_CMDID + */ +typedef PREPACK struct { + A_BOOL enable_radio_measurements; +} POSTPACK WMI_ENABLE_RM_CMD; + +/* + * WMI_SET_MAX_OFFHOME_DURATION_CMDID + */ +typedef PREPACK struct { + A_UINT8 max_offhome_duration; +} POSTPACK WMI_SET_MAX_OFFHOME_DURATION_CMD; + +typedef PREPACK struct { + A_UINT32 frequency; + A_UINT8 threshold; +} POSTPACK WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD; + +typedef enum { + BT_STREAM_UNDEF = 0, + BT_STREAM_SCO, /* SCO stream */ + BT_STREAM_A2DP, /* A2DP stream */ + BT_STREAM_SCAN, /* BT Discovery or Page */ + BT_STREAM_ESCO, + BT_STREAM_MAX +} BT_STREAM_TYPE; + +typedef enum { + BT_PARAM_SCO = 1, /* SCO stream parameters */ + BT_PARAM_A2DP , + BT_PARAM_ANTENNA_CONFIG, + BT_PARAM_COLOCATED_BT_DEVICE, + BT_PARAM_ACLCOEX, + BT_PARAM_11A_SEPARATE_ANT, + BT_PARAM_MAX +} BT_PARAM_TYPE; + +typedef enum { + BT_PARAM_SCO_PSPOLL_LATENCY_ONE_FOURTH =1, + BT_PARAM_SCO_PSPOLL_LATENCY_HALF, + BT_PARAM_SCO_PSPOLL_LATENCY_THREE_FOURTH, +} BT_PARAMS_SCO_PSPOLL_LATENCY; + +typedef enum { + BT_PARAMS_SCO_STOMP_SCO_NEVER =1, + BT_PARAMS_SCO_STOMP_SCO_ALWAYS, + BT_PARAMS_SCO_STOMP_SCO_IN_LOWRSSI, +} BT_PARAMS_SCO_STOMP_RULES; + +typedef enum { + BT_STATUS_UNDEF = 0, + BT_STATUS_START, + BT_STATUS_STOP, + BT_STATUS_RESUME, + BT_STATUS_SUSPEND, + BT_STATUS_MAX +} BT_STREAM_STATUS; + +typedef PREPACK struct { + A_UINT8 streamType; + A_UINT8 status; +} POSTPACK WMI_SET_BT_STATUS_CMD; + +typedef enum { + BT_ANT_TYPE_UNDEF=0, + BT_ANT_TYPE_DUAL, + BT_ANT_TYPE_SPLITTER, + BT_ANT_TYPE_SWITCH +} BT_ANT_FRONTEND_CONFIG; + +typedef enum { + BT_COLOCATED_DEV_BTS4020=0, + BT_COLCATED_DEV_CSR , + BT_COLOCATED_DEV_VALKYRIE +} BT_COLOCATED_DEV_TYPE; + +typedef PREPACK struct { + A_UINT32 numScoCyclesForceTrigger; /* Number SCO cycles after which + force a pspoll. default = 10 */ + A_UINT32 dataResponseTimeout; /* Timeout Waiting for Downlink pkt + in response for ps-poll, + default = 10 msecs */ + A_UINT32 stompScoRules; + A_UINT8 stompDutyCyleVal; /* Sco cycles to limit ps-poll queuing + if stomped */ + A_UINT8 psPollLatencyFraction; /* Fraction of idle + period, within which + additional ps-polls + can be queued */ + A_UINT8 noSCOSlots; /* Number of SCO Tx/Rx slots. + HVx, EV3, 2EV3 = 2 */ + A_UINT8 noIdleSlots; /* Number of Bluetooth idle slots between + consecutive SCO Tx/Rx slots + HVx, EV3 = 4 + 2EV3 = 10 */ +} POSTPACK BT_PARAMS_SCO; + +typedef PREPACK struct { + A_UINT32 a2dpWlanUsageLimit; /* MAX time firmware uses the medium for + wlan, after it identifies the idle time + default (30 msecs) */ + A_UINT32 a2dpBurstCntMin; /* Minimum number of bluetooth data frames + to replenish Wlan Usage limit (default 3) */ + A_UINT32 a2dpDataRespTimeout; + A_UINT32 isCoLocatedBtRoleMaster; +}POSTPACK BT_PARAMS_A2DP; + +/* During BT ftp/ BT OPP or any another data based acl profile on bluetooth + (non a2dp).*/ +typedef PREPACK struct { + A_UINT32 aclWlanMediumUsageTime; /* Wlan usage time during Acl (non-a2dp) + coexistence (default 30 msecs) */ + A_UINT32 aclBtMediumUsageTime; /* Bt usage time during acl coexistence + (default 30 msecs)*/ + A_UINT32 aclDataRespTimeout; +}POSTPACK BT_PARAMS_ACLCOEX; + +typedef PREPACK struct { + PREPACK union { + BT_PARAMS_SCO scoParams; + BT_PARAMS_A2DP a2dpParams; + BT_PARAMS_ACLCOEX aclCoexParams; + A_UINT8 antType; /* 0 -Disabled (default) + 1 - BT_ANT_TYPE_DUAL + 2 - BT_ANT_TYPE_SPLITTER + 3 - BT_ANT_TYPE_SWITCH */ + A_UINT8 coLocatedBtDev; /* 0 - BT_COLOCATED_DEV_BTS4020 (default) + 1 - BT_COLCATED_DEV_CSR + 2 - BT_COLOCATED_DEV_VALKYRIe + */ + } POSTPACK info; + A_UINT8 paramType ; +} POSTPACK WMI_SET_BT_PARAMS_CMD; + +typedef enum { + DISCONN_EVT_IN_RECONN = 0, /* default */ + NO_DISCONN_EVT_IN_RECONN +} TARGET_EVENT_REPORT_CONFIG; + +typedef PREPACK struct { + A_UINT32 evtConfig; +} POSTPACK WMI_SET_TARGET_EVENT_REPORT_CMD; + +#define MAC_MAX_FILTERS_PER_LIST 4 + +typedef PREPACK struct { + A_UINT8 multicast_mac[ATH_MAC_LEN]; /* WMI_SET_MCAST_FILTER */ +} POSTPACK WMI_SET_MCAST_FILTER_CMD; + +typedef PREPACK struct { + A_UINT8 valid_filter; + A_UINT8 mac_addr[ATH_MAC_LEN]; +} POSTPACK MAC_FILTER; + +typedef PREPACK struct { + A_UINT8 total_list_size; + MAC_FILTER list[MAC_MAX_FILTERS_PER_LIST]; +} POSTPACK MAC_FILTER_LIST; + + +/* + * Command Replies + */ + +/* + * WMI_GET_CHANNEL_LIST_CMDID reply + */ +typedef PREPACK struct { + A_UINT8 reserved1; + A_UINT8 numChannels; /* number of channels in reply */ + A_UINT16 channelList[1]; /* channel in Mhz */ +} POSTPACK WMI_CHANNEL_LIST_REPLY; + +typedef enum { + A_SUCCEEDED = A_OK, + A_FAILED_DELETE_STREAM_DOESNOT_EXIST=250, + A_SUCCEEDED_MODIFY_STREAM=251, + A_FAILED_INVALID_STREAM = 252, + A_FAILED_MAX_THINSTREAMS = 253, + A_FAILED_CREATE_REMOVE_PSTREAM_FIRST = 254, +} PSTREAM_REPLY_STATUS; + +typedef PREPACK struct { + A_UINT8 status; /* PSTREAM_REPLY_STATUS */ + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficClass; + A_UINT8 trafficDirection; /* DIR_TYPE */ +} POSTPACK WMI_CRE_PRIORITY_STREAM_REPLY; + +typedef PREPACK struct { + A_UINT8 status; /* PSTREAM_REPLY_STATUS */ + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficDirection; /* DIR_TYPE */ + A_UINT8 trafficClass; +} POSTPACK WMI_DEL_PRIORITY_STREAM_REPLY; + +/* + * List of Events (target to host) + */ +typedef enum { + WMI_READY_EVENTID = 0x1001, + WMI_CONNECT_EVENTID, + WMI_DISCONNECT_EVENTID, + WMI_BSSINFO_EVENTID, + WMI_CMDERROR_EVENTID, + WMI_REGDOMAIN_EVENTID, + WMI_PSTREAM_TIMEOUT_EVENTID, + WMI_NEIGHBOR_REPORT_EVENTID, + WMI_TKIP_MICERR_EVENTID, + WMI_SCAN_COMPLETE_EVENTID, + WMI_REPORT_STATISTICS_EVENTID, + WMI_RSSI_THRESHOLD_EVENTID, + WMI_ERROR_REPORT_EVENTID, + WMI_OPT_RX_FRAME_EVENTID, + WMI_REPORT_ROAM_TBL_EVENTID, + WMI_EXTENSION_EVENTID, + WMI_CAC_EVENTID, + WMI_SNR_THRESHOLD_EVENTID, + WMI_LQ_THRESHOLD_EVENTID, + WMI_TX_RETRY_ERR_EVENTID, + WMI_REPORT_ROAM_DATA_EVENTID, + WMI_TEST_EVENTID, + WMI_APLIST_EVENTID, + WMI_GET_WOW_LIST_EVENTID, + WMI_GET_PMKID_LIST_EVENTID, + WMI_CHANNEL_CHANGE_EVENTID +} WMI_EVENT_ID; + +typedef enum { + WMI_11A_CAPABILITY = 1, + WMI_11G_CAPABILITY = 2, + WMI_11AG_CAPABILITY = 3, +} WMI_PHY_CAPABILITY; + +typedef PREPACK struct { + A_UINT8 macaddr[ATH_MAC_LEN]; + A_UINT8 phyCapability; /* WMI_PHY_CAPABILITY */ +} POSTPACK WMI_READY_EVENT_1; + +typedef PREPACK struct { + A_UINT32 version; + A_UINT8 macaddr[ATH_MAC_LEN]; + A_UINT8 phyCapability; /* WMI_PHY_CAPABILITY */ +} POSTPACK WMI_READY_EVENT_2; + +#if defined(ATH_TARGET) +#define WMI_READY_EVENT WMI_READY_EVENT_1 /* AR6002_REV2 target code */ +#else +#define WMI_READY_EVENT WMI_READY_EVENT_2 /* host code */ +#endif + + +/* + * Connect Event + */ +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT16 listenInterval; + A_UINT16 beaconInterval; + A_UINT32 networkType; + A_UINT8 beaconIeLen; + A_UINT8 assocReqLen; + A_UINT8 assocRespLen; + A_UINT8 assocInfo[1]; +} POSTPACK WMI_CONNECT_EVENT; + +/* + * Disconnect Event + */ +typedef enum { + NO_NETWORK_AVAIL = 0x01, + LOST_LINK = 0x02, /* bmiss */ + DISCONNECT_CMD = 0x03, + BSS_DISCONNECTED = 0x04, + AUTH_FAILED = 0x05, + ASSOC_FAILED = 0x06, + NO_RESOURCES_AVAIL = 0x07, + CSERV_DISCONNECT = 0x08, + INVALID_PROFILE = 0x0a, + DOT11H_CHANNEL_SWITCH = 0x0b, + PROFILE_MISMATCH = 0x0c, +} WMI_DISCONNECT_REASON; + +typedef PREPACK struct { + A_UINT16 protocolReasonStatus; /* reason code, see 802.11 spec. */ + A_UINT8 bssid[ATH_MAC_LEN]; /* set if known */ + A_UINT8 disconnectReason ; /* see WMI_DISCONNECT_REASON */ + A_UINT8 assocRespLen; + A_UINT8 assocInfo[1]; +} POSTPACK WMI_DISCONNECT_EVENT; + +/* + * BSS Info Event. + * Mechanism used to inform host of the presence and characteristic of + * wireless networks present. Consists of bss info header followed by + * the beacon or probe-response frame body. The 802.11 header is not included. + */ +typedef enum { + BEACON_FTYPE = 0x1, + PROBERESP_FTYPE, + ACTION_MGMT_FTYPE, +} WMI_BI_FTYPE; + +enum { + BSS_ELEMID_CHANSWITCH = 0x01, + BSS_ELEMID_ATHEROS = 0x02, +}; + +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 frameType; /* see WMI_BI_FTYPE */ + A_UINT8 snr; + A_INT16 rssi; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT32 ieMask; +} POSTPACK WMI_BSS_INFO_HDR; + +/* + * Command Error Event + */ +typedef enum { + INVALID_PARAM = 0x01, + ILLEGAL_STATE = 0x02, + INTERNAL_ERROR = 0x03, +} WMI_ERROR_CODE; + +typedef PREPACK struct { + A_UINT16 commandId; + A_UINT8 errorCode; +} POSTPACK WMI_CMD_ERROR_EVENT; + +/* + * New Regulatory Domain Event + */ +typedef PREPACK struct { + A_UINT32 regDomain; +} POSTPACK WMI_REG_DOMAIN_EVENT; + +typedef PREPACK struct { + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficDirection; + A_UINT8 trafficClass; +} POSTPACK WMI_PSTREAM_TIMEOUT_EVENT; + +/* + * The WMI_NEIGHBOR_REPORT Event is generated by the target to inform + * the host of BSS's it has found that matches the current profile. + * It can be used by the host to cache PMKs and/to initiate pre-authentication + * if the BSS supports it. The first bssid is always the current associated + * BSS. + * The bssid and bssFlags information repeats according to the number + * or APs reported. + */ +typedef enum { + WMI_DEFAULT_BSS_FLAGS = 0x00, + WMI_PREAUTH_CAPABLE_BSS = 0x01, + WMI_PMKID_VALID_BSS = 0x02, +} WMI_BSS_FLAGS; + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT8 bssFlags; /* see WMI_BSS_FLAGS */ +} POSTPACK WMI_NEIGHBOR_INFO; + +typedef PREPACK struct { + A_INT8 numberOfAps; + WMI_NEIGHBOR_INFO neighbor[1]; +} POSTPACK WMI_NEIGHBOR_REPORT_EVENT; + +/* + * TKIP MIC Error Event + */ +typedef PREPACK struct { + A_UINT8 keyid; + A_UINT8 ismcast; +} POSTPACK WMI_TKIP_MICERR_EVENT; + +/* + * WMI_SCAN_COMPLETE_EVENTID - no parameters (old), staus parameter (new) + */ +typedef PREPACK struct { + A_INT32 status; +} POSTPACK WMI_SCAN_COMPLETE_EVENT; + +#define MAX_OPT_DATA_LEN 1400 + +/* + * WMI_SET_ADHOC_BSSID_CMDID + */ +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_SET_ADHOC_BSSID_CMD; + +/* + * WMI_SET_OPT_MODE_CMDID + */ +typedef enum { + SPECIAL_OFF, + SPECIAL_ON, +} OPT_MODE_TYPE; + +typedef PREPACK struct { + A_UINT8 optMode; +} POSTPACK WMI_SET_OPT_MODE_CMD; + +/* + * WMI_TX_OPT_FRAME_CMDID + */ +typedef enum { + OPT_PROBE_REQ = 0x01, + OPT_PROBE_RESP = 0x02, + OPT_CPPP_START = 0x03, + OPT_CPPP_STOP = 0x04, +} WMI_OPT_FTYPE; + +typedef PREPACK struct { + A_UINT16 optIEDataLen; + A_UINT8 frmType; + A_UINT8 dstAddr[ATH_MAC_LEN]; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT8 reserved; /* For alignment */ + A_UINT8 optIEData[1]; +} POSTPACK WMI_OPT_TX_FRAME_CMD; + +/* + * Special frame receive Event. + * Mechanism used to inform host of the receiption of the special frames. + * Consists of special frame info header followed by special frame body. + * The 802.11 header is not included. + */ +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 frameType; /* see WMI_OPT_FTYPE */ + A_INT8 snr; + A_UINT8 srcAddr[ATH_MAC_LEN]; + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_OPT_RX_INFO_HDR; + +/* + * Reporting statistics. + */ +typedef PREPACK struct { + A_UINT32 tx_packets; + A_UINT32 tx_bytes; + A_UINT32 tx_unicast_pkts; + A_UINT32 tx_unicast_bytes; + A_UINT32 tx_multicast_pkts; + A_UINT32 tx_multicast_bytes; + A_UINT32 tx_broadcast_pkts; + A_UINT32 tx_broadcast_bytes; + A_UINT32 tx_rts_success_cnt; + A_UINT32 tx_packet_per_ac[4]; + A_UINT32 tx_errors_per_ac[4]; + + A_UINT32 tx_errors; + A_UINT32 tx_failed_cnt; + A_UINT32 tx_retry_cnt; + A_UINT32 tx_mult_retry_cnt; + A_UINT32 tx_rts_fail_cnt; + A_INT32 tx_unicast_rate; +}POSTPACK tx_stats_t; + +typedef PREPACK struct { + A_UINT32 rx_packets; + A_UINT32 rx_bytes; + A_UINT32 rx_unicast_pkts; + A_UINT32 rx_unicast_bytes; + A_UINT32 rx_multicast_pkts; + A_UINT32 rx_multicast_bytes; + A_UINT32 rx_broadcast_pkts; + A_UINT32 rx_broadcast_bytes; + A_UINT32 rx_fragment_pkt; + + A_UINT32 rx_errors; + A_UINT32 rx_crcerr; + A_UINT32 rx_key_cache_miss; + A_UINT32 rx_decrypt_err; + A_UINT32 rx_duplicate_frames; + A_INT32 rx_unicast_rate; +}POSTPACK rx_stats_t; + +typedef PREPACK struct { + A_UINT32 tkip_local_mic_failure; + A_UINT32 tkip_counter_measures_invoked; + A_UINT32 tkip_replays; + A_UINT32 tkip_format_errors; + A_UINT32 ccmp_format_errors; + A_UINT32 ccmp_replays; +}POSTPACK tkip_ccmp_stats_t; + +typedef PREPACK struct { + A_UINT32 power_save_failure_cnt; +}POSTPACK pm_stats_t; + +typedef PREPACK struct { + A_UINT32 cs_bmiss_cnt; + A_UINT32 cs_lowRssi_cnt; + A_UINT16 cs_connect_cnt; + A_UINT16 cs_disconnect_cnt; + A_INT16 cs_aveBeacon_rssi; + A_UINT16 cs_roam_count; + A_INT16 cs_rssi; + A_UINT8 cs_snr; + A_UINT8 cs_aveBeacon_snr; + A_UINT8 cs_lastRoam_msec; +} POSTPACK cserv_stats_t; + +typedef PREPACK struct { + tx_stats_t tx_stats; + rx_stats_t rx_stats; + tkip_ccmp_stats_t tkipCcmpStats; +}POSTPACK wlan_net_stats_t; + +typedef PREPACK struct { + A_UINT32 wow_num_pkts_dropped; + A_UINT16 wow_num_events_discarded; + A_UINT8 wow_num_host_pkt_wakeups; + A_UINT8 wow_num_host_event_wakeups; +} POSTPACK wlan_wow_stats_t; + +typedef PREPACK struct { + A_UINT32 lqVal; + A_INT32 noise_floor_calibation; + pm_stats_t pmStats; + wlan_net_stats_t txrxStats; + wlan_wow_stats_t wowStats; + cserv_stats_t cservStats; +} POSTPACK WMI_TARGET_STATS; + +/* + * WMI_RSSI_THRESHOLD_EVENTID. + * Indicate the RSSI events to host. Events are indicated when we breach a + * thresold value. + */ +typedef enum{ + WMI_RSSI_THRESHOLD1_ABOVE = 0, + WMI_RSSI_THRESHOLD2_ABOVE, + WMI_RSSI_THRESHOLD3_ABOVE, + WMI_RSSI_THRESHOLD4_ABOVE, + WMI_RSSI_THRESHOLD5_ABOVE, + WMI_RSSI_THRESHOLD6_ABOVE, + WMI_RSSI_THRESHOLD1_BELOW, + WMI_RSSI_THRESHOLD2_BELOW, + WMI_RSSI_THRESHOLD3_BELOW, + WMI_RSSI_THRESHOLD4_BELOW, + WMI_RSSI_THRESHOLD5_BELOW, + WMI_RSSI_THRESHOLD6_BELOW +}WMI_RSSI_THRESHOLD_VAL; + +typedef PREPACK struct { + A_INT16 rssi; + A_UINT8 range; +}POSTPACK WMI_RSSI_THRESHOLD_EVENT; + +/* + * WMI_ERROR_REPORT_EVENTID + */ +typedef enum{ + WMI_TARGET_PM_ERR_FAIL = 0x00000001, + WMI_TARGET_KEY_NOT_FOUND = 0x00000002, + WMI_TARGET_DECRYPTION_ERR = 0x00000004, + WMI_TARGET_BMISS = 0x00000008, + WMI_PSDISABLE_NODE_JOIN = 0x00000010, + WMI_TARGET_COM_ERR = 0x00000020, + WMI_TARGET_FATAL_ERR = 0x00000040 +} WMI_TARGET_ERROR_VAL; + +typedef PREPACK struct { + A_UINT32 errorVal; +}POSTPACK WMI_TARGET_ERROR_REPORT_EVENT; + +typedef PREPACK struct { + A_UINT8 retrys; +}POSTPACK WMI_TX_RETRY_ERR_EVENT; + +typedef enum{ + WMI_SNR_THRESHOLD1_ABOVE = 1, + WMI_SNR_THRESHOLD1_BELOW, + WMI_SNR_THRESHOLD2_ABOVE, + WMI_SNR_THRESHOLD2_BELOW, + WMI_SNR_THRESHOLD3_ABOVE, + WMI_SNR_THRESHOLD3_BELOW, + WMI_SNR_THRESHOLD4_ABOVE, + WMI_SNR_THRESHOLD4_BELOW +} WMI_SNR_THRESHOLD_VAL; + +typedef PREPACK struct { + A_UINT8 range; /* WMI_SNR_THRESHOLD_VAL */ + A_UINT8 snr; +}POSTPACK WMI_SNR_THRESHOLD_EVENT; + +typedef enum{ + WMI_LQ_THRESHOLD1_ABOVE = 1, + WMI_LQ_THRESHOLD1_BELOW, + WMI_LQ_THRESHOLD2_ABOVE, + WMI_LQ_THRESHOLD2_BELOW, + WMI_LQ_THRESHOLD3_ABOVE, + WMI_LQ_THRESHOLD3_BELOW, + WMI_LQ_THRESHOLD4_ABOVE, + WMI_LQ_THRESHOLD4_BELOW +} WMI_LQ_THRESHOLD_VAL; + +typedef PREPACK struct { + A_INT32 lq; + A_UINT8 range; /* WMI_LQ_THRESHOLD_VAL */ +}POSTPACK WMI_LQ_THRESHOLD_EVENT; +/* + * WMI_REPORT_ROAM_TBL_EVENTID + */ +#define MAX_ROAM_TBL_CAND 5 + +typedef PREPACK struct { + A_INT32 roam_util; + A_UINT8 bssid[ATH_MAC_LEN]; + A_INT8 rssi; + A_INT8 rssidt; + A_INT8 last_rssi; + A_INT8 util; + A_INT8 bias; + A_UINT8 reserved; /* For alignment */ +} POSTPACK WMI_BSS_ROAM_INFO; + + +typedef PREPACK struct { + A_UINT16 roamMode; + A_UINT16 numEntries; + WMI_BSS_ROAM_INFO bssRoamInfo[1]; +} POSTPACK WMI_TARGET_ROAM_TBL; + +/* + * WMI_CAC_EVENTID + */ +typedef enum { + CAC_INDICATION_ADMISSION = 0x00, + CAC_INDICATION_ADMISSION_RESP = 0x01, + CAC_INDICATION_DELETE = 0x02, + CAC_INDICATION_NO_RESP = 0x03, +}CAC_INDICATION; + +#define WMM_TSPEC_IE_LEN 63 + +typedef PREPACK struct { + A_UINT8 ac; + A_UINT8 cac_indication; + A_UINT8 statusCode; + A_UINT8 tspecSuggestion[WMM_TSPEC_IE_LEN]; +}POSTPACK WMI_CAC_EVENT; + +/* + * WMI_APLIST_EVENTID + */ + +typedef enum { + APLIST_VER1 = 1, +} APLIST_VER; + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT16 channel; +} POSTPACK WMI_AP_INFO_V1; + +typedef PREPACK union { + WMI_AP_INFO_V1 apInfoV1; +} POSTPACK WMI_AP_INFO; + +typedef PREPACK struct { + A_UINT8 apListVer; + A_UINT8 numAP; + WMI_AP_INFO apList[1]; +} POSTPACK WMI_APLIST_EVENT; + +/* + * developer commands + */ + +/* + * WMI_SET_BITRATE_CMDID + * + * Get bit rate cmd uses same definition as set bit rate cmd + */ +typedef enum { + RATE_AUTO = -1, + RATE_1Mb = 0, + RATE_2Mb = 1, + RATE_5_5Mb = 2, + RATE_11Mb = 3, + RATE_6Mb = 4, + RATE_9Mb = 5, + RATE_12Mb = 6, + RATE_18Mb = 7, + RATE_24Mb = 8, + RATE_36Mb = 9, + RATE_48Mb = 10, + RATE_54Mb = 11, +} WMI_BIT_RATE; + +typedef PREPACK struct { + A_INT8 rateIndex; /* see WMI_BIT_RATE */ +} POSTPACK WMI_BIT_RATE_CMD, WMI_BIT_RATE_REPLY; + +/* + * WMI_SET_FIXRATES_CMDID + * + * Get fix rates cmd uses same definition as set fix rates cmd + */ +typedef enum { + FIX_RATE_1Mb = 0x1, + FIX_RATE_2Mb = 0x2, + FIX_RATE_5_5Mb = 0x4, + FIX_RATE_11Mb = 0x8, + FIX_RATE_6Mb = 0x10, + FIX_RATE_9Mb = 0x20, + FIX_RATE_12Mb = 0x40, + FIX_RATE_18Mb = 0x80, + FIX_RATE_24Mb = 0x100, + FIX_RATE_36Mb = 0x200, + FIX_RATE_48Mb = 0x400, + FIX_RATE_54Mb = 0x800, +} WMI_FIX_RATES_MASK; + +typedef PREPACK struct { + A_UINT16 fixRateMask; /* see WMI_BIT_RATE */ +} POSTPACK WMI_FIX_RATES_CMD, WMI_FIX_RATES_REPLY; + +/* + * WMI_SET_RECONNECT_AUTH_MODE_CMDID + * + * Set authentication mode + */ +typedef enum { + RECONN_DO_AUTH = 0x00, + RECONN_NOT_AUTH = 0x01 +} WMI_AUTH_MODE; + +typedef PREPACK struct { + A_UINT8 mode; +} POSTPACK WMI_SET_AUTH_MODE_CMD; + +/* + * WMI_SET_REASSOC_MODE_CMDID + * + * Set authentication mode + */ +typedef enum { + REASSOC_DO_DISASSOC = 0x00, + REASSOC_DONOT_DISASSOC = 0x01 +} WMI_REASSOC_MODE; + +typedef PREPACK struct { + A_UINT8 mode; +}POSTPACK WMI_SET_REASSOC_MODE_CMD; + +typedef enum { + ROAM_DATA_TIME = 1, /* Get The Roam Time Data */ +} ROAM_DATA_TYPE; + +typedef PREPACK struct { + A_UINT32 disassoc_time; + A_UINT32 no_txrx_time; + A_UINT32 assoc_time; + A_UINT32 allow_txrx_time; + A_UINT32 last_data_txrx_time; + A_UINT32 first_data_txrx_time; + A_UINT8 disassoc_bssid[ATH_MAC_LEN]; + A_INT8 disassoc_bss_rssi; + A_UINT8 assoc_bssid[ATH_MAC_LEN]; + A_INT8 assoc_bss_rssi; +} POSTPACK WMI_TARGET_ROAM_TIME; + +typedef PREPACK struct { + PREPACK union { + WMI_TARGET_ROAM_TIME roamTime; + } POSTPACK u; + A_UINT8 roamDataType ; +} POSTPACK WMI_TARGET_ROAM_DATA; + +typedef enum { + WMI_WMM_DISABLED = 0, + WMI_WMM_ENABLED +} WMI_WMM_STATUS; + +typedef PREPACK struct { + A_UINT8 status; +}POSTPACK WMI_SET_WMM_CMD; + +typedef enum { + WMI_TXOP_DISABLED = 0, + WMI_TXOP_ENABLED +} WMI_TXOP_CFG; + +typedef PREPACK struct { + A_UINT8 txopEnable; +}POSTPACK WMI_SET_WMM_TXOP_CMD; + +typedef PREPACK struct { + A_UINT8 keepaliveInterval; +} POSTPACK WMI_SET_KEEPALIVE_CMD; + +typedef PREPACK struct { + A_BOOL configured; + A_UINT8 keepaliveInterval; +} POSTPACK WMI_GET_KEEPALIVE_CMD; + +/* + * Add Application specified IE to a management frame + */ +#define WMI_MAX_IE_LEN 78 + +typedef PREPACK struct { + A_UINT8 mgmtFrmType; /* one of WMI_MGMT_FRAME_TYPE */ + A_UINT8 ieLen; /* Length of the IE that should be added to the MGMT frame */ + A_UINT8 ieInfo[1]; +} POSTPACK WMI_SET_APPIE_CMD; + +/* + * Notify the WSC registration status to the target + */ +#define WSC_REG_ACTIVE 1 +#define WSC_REG_INACTIVE 0 +/* Generic Hal Interface for setting hal paramters. */ +/* Add new Set HAL Param cmdIds here for newer params */ +typedef enum { + WHAL_SETCABTO_CMDID = 1, +}WHAL_CMDID; + +typedef PREPACK struct { + A_UINT8 cabTimeOut; +} POSTPACK WHAL_SETCABTO_PARAM; + +typedef PREPACK struct { + A_UINT8 whalCmdId; + A_UINT8 data[1]; +} POSTPACK WHAL_PARAMCMD; + + +#define WOW_MAX_FILTER_LISTS 1 /*4*/ +#define WOW_MAX_FILTERS_PER_LIST 4 +#define WOW_PATTERN_SIZE 64 +#define WOW_MASK_SIZE 64 + +typedef PREPACK struct { + A_UINT8 wow_valid_filter; + A_UINT8 wow_filter_id; + A_UINT8 wow_filter_size; + A_UINT8 wow_filter_offset; + A_UINT8 wow_filter_mask[WOW_MASK_SIZE]; + A_UINT8 wow_filter_pattern[WOW_PATTERN_SIZE]; +} POSTPACK WOW_FILTER; + + +typedef PREPACK struct { + A_UINT8 wow_valid_list; + A_UINT8 wow_list_id; + A_UINT8 wow_num_filters; + A_UINT8 wow_total_list_size; + WOW_FILTER list[WOW_MAX_FILTERS_PER_LIST]; +} POSTPACK WOW_FILTER_LIST; + +typedef PREPACK struct { + A_BOOL awake; + A_BOOL asleep; +} POSTPACK WMI_SET_HOST_SLEEP_MODE_CMD; + +typedef PREPACK struct { + A_BOOL enable_wow; +} POSTPACK WMI_SET_WOW_MODE_CMD; + +typedef PREPACK struct { + A_UINT8 filter_list_id; +} POSTPACK WMI_GET_WOW_LIST_CMD; + +/* + * WMI_GET_WOW_LIST_CMD reply + */ +typedef PREPACK struct { + A_UINT8 num_filters; /* number of patterns in reply */ + A_UINT8 this_filter_num; /* this is filter # x of total num_filters */ + A_UINT8 wow_mode; + A_UINT8 host_mode; + WOW_FILTER wow_filters[1]; +} POSTPACK WMI_GET_WOW_LIST_REPLY; + +typedef PREPACK struct { + A_UINT8 filter_list_id; + A_UINT8 filter_size; + A_UINT8 filter_offset; + A_UINT8 filter[1]; +} POSTPACK WMI_ADD_WOW_PATTERN_CMD; + +typedef PREPACK struct { + A_UINT16 filter_list_id; + A_UINT16 filter_id; +} POSTPACK WMI_DEL_WOW_PATTERN_CMD; + +typedef PREPACK struct { + A_UINT8 macaddr[ATH_MAC_LEN]; +} POSTPACK WMI_SET_MAC_ADDRESS_CMD; + +/* + * WMI_SET_AKMP_PARAMS_CMD + */ + +#define WMI_AKMP_MULTI_PMKID_EN 0x000001 + +typedef PREPACK struct { + A_UINT32 akmpInfo; +} POSTPACK WMI_SET_AKMP_PARAMS_CMD; + +typedef PREPACK struct { + A_UINT8 pmkid[WMI_PMKID_LEN]; +} POSTPACK WMI_PMKID; + +/* + * WMI_SET_PMKID_LIST_CMD + */ +#define WMI_MAX_PMKID_CACHE 8 + +typedef PREPACK struct { + A_UINT32 numPMKID; + WMI_PMKID pmkidList[WMI_MAX_PMKID_CACHE]; +} POSTPACK WMI_SET_PMKID_LIST_CMD; + +/* + * WMI_GET_PMKID_LIST_CMD Reply + * Following the Number of PMKIDs is the list of PMKIDs + */ +typedef PREPACK struct { + A_UINT32 numPMKID; + A_UINT8 bssidList[ATH_MAC_LEN][1]; + WMI_PMKID pmkidList[1]; +} POSTPACK WMI_PMKID_LIST_REPLY; + +typedef PREPACK struct { + A_UINT16 oldChannel; + A_UINT32 newChannel; +} POSTPACK WMI_CHANNEL_CHANGE_EVENT; + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/wmi_api.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/wmi_api.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/wmi_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/wmi_api.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,289 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions for the Wireless Module Interface (WMI). +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _WMI_API_H_ +#define _WMI_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * IP QoS Field definitions according to 802.1p + */ +#define BEST_EFFORT_PRI 0 +#define BACKGROUND_PRI 1 +#define EXCELLENT_EFFORT_PRI 3 +#define CONTROLLED_LOAD_PRI 4 +#define VIDEO_PRI 5 +#define VOICE_PRI 6 +#define NETWORK_CONTROL_PRI 7 +#define MAX_NUM_PRI 8 + +#define UNDEFINED_PRI (0xff) + +#define WMI_IMPLICIT_PSTREAM_INACTIVITY_INT 5000 /* 5 seconds */ + +typedef enum { + ATHEROS_COMPLIANCE = 0x1, +}TSPEC_PARAM_COMPLIANCE; + +struct wmi_t; + +void *wmi_init(void *devt); + +void wmi_qos_state_init(struct wmi_t *wmip); +void wmi_shutdown(struct wmi_t *wmip); +HTC_ENDPOINT_ID wmi_get_control_ep(struct wmi_t * wmip); +void wmi_set_control_ep(struct wmi_t * wmip, HTC_ENDPOINT_ID eid); +A_UINT16 wmi_get_mapped_qos_queue(struct wmi_t *, A_UINT8); +A_STATUS wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf); +A_STATUS wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType); +A_STATUS wmi_dot3_2_dix(struct wmi_t *wmip, void *osbuf); +A_STATUS wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf); +A_STATUS wmi_syncpoint(struct wmi_t *wmip); +A_STATUS wmi_syncpoint_reset(struct wmi_t *wmip); +A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT32 layer2Priority, A_BOOL wmmEnabled); + +A_STATUS wmi_control_rx(struct wmi_t *wmip, void *osbuf); +void wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg); +void wmi_free_allnodes(struct wmi_t *wmip); +bss_t *wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr); +void wmi_free_node(struct wmi_t *wmip, const A_UINT8 *macaddr); + + +typedef enum { + NO_SYNC_WMIFLAG = 0, + SYNC_BEFORE_WMIFLAG, /* transmit all queued data before cmd */ + SYNC_AFTER_WMIFLAG, /* any new data waits until cmd execs */ + SYNC_BOTH_WMIFLAG, + END_WMIFLAG /* end marker */ +} WMI_SYNC_FLAG; + +A_STATUS wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId, + WMI_SYNC_FLAG flag); +A_STATUS wmi_connect_cmd(struct wmi_t *wmip, + NETWORK_TYPE netType, + DOT11_AUTH_MODE dot11AuthMode, + AUTH_MODE authMode, + CRYPTO_TYPE pairwiseCrypto, + A_UINT8 pairwiseCryptoLen, + CRYPTO_TYPE groupCrypto, + A_UINT8 groupCryptoLen, + int ssidLength, + A_UCHAR *ssid, + A_UINT8 *bssid, + A_UINT16 channel, + A_UINT32 ctrl_flags); +A_STATUS wmi_reconnect_cmd(struct wmi_t *wmip, + A_UINT8 *bssid, + A_UINT16 channel); +A_STATUS wmi_disconnect_cmd(struct wmi_t *wmip); +A_STATUS wmi_getrev_cmd(struct wmi_t *wmip); +A_STATUS wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType, + A_BOOL forceFgScan, A_BOOL isLegacy, + A_UINT32 homeDwellTime, A_UINT32 forceScanInterval, + A_INT8 numChan, A_UINT16 *channelList); +A_STATUS wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec, + A_UINT16 fg_end_sec, A_UINT16 bg_sec, + A_UINT16 minact_chdw_msec, + A_UINT16 maxact_chdw_msec, A_UINT16 pas_chdw_msec, + A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags, + A_UINT32 max_dfsch_act_time); +A_STATUS wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask); +A_STATUS wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag, + A_UINT8 ssidLength, A_UCHAR *ssid); +A_STATUS wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons); +A_STATUS wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmisstime, A_UINT16 bmissbeacons); +A_STATUS wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType, + A_UINT8 ieLen, A_UINT8 *ieInfo); +A_STATUS wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode); +A_STATUS wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl, + A_UINT16 atim_windows, A_UINT16 timeout_value); +A_STATUS wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod, + A_UINT16 psPollNum, A_UINT16 dtimPolicy); +A_STATUS wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout); +A_STATUS wmi_sync_cmd(struct wmi_t *wmip, A_UINT8 syncNumber); +A_STATUS wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *pstream); +A_STATUS wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 streamID); +A_STATUS wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 rate); +A_STATUS wmi_get_bitrate_cmd(struct wmi_t *wmip); +A_INT8 wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate); +A_STATUS wmi_get_regDomain_cmd(struct wmi_t *wmip); +A_STATUS wmi_get_channelList_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam, + WMI_PHY_MODE mode, A_INT8 numChan, + A_UINT16 *channelList); + +A_STATUS wmi_set_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd); +A_STATUS wmi_set_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd); +A_STATUS wmi_clr_rssi_snr(struct wmi_t *wmip); +A_STATUS wmi_set_lq_threshold_params(struct wmi_t *wmip, + WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd); +A_STATUS wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold); +A_STATUS wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status); + +A_STATUS wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 bitmask); + +A_STATUS wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie, + A_UINT32 source); +A_STATUS wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask, + A_UINT16 tsr, A_BOOL rep, A_UINT16 size, + A_UINT32 valid); +A_STATUS wmi_get_stats_cmd(struct wmi_t *wmip); +A_STATUS wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex, + CRYPTO_TYPE keyType, A_UINT8 keyUsage, + A_UINT8 keyLength,A_UINT8 *keyRSC, + A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl, + WMI_SYNC_FLAG sync_flag); +A_STATUS wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk); +A_STATUS wmi_delete_krk_cmd(struct wmi_t *wmip); +A_STATUS wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex); +A_STATUS wmi_set_akmp_params_cmd(struct wmi_t *wmip, + WMI_SET_AKMP_PARAMS_CMD *akmpParams); +A_STATUS wmi_get_pmkid_list_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_pmkid_list_cmd(struct wmi_t *wmip, + WMI_SET_PMKID_LIST_CMD *pmkInfo); +A_STATUS wmi_abort_scan_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM); +A_STATUS wmi_get_txPwr_cmd(struct wmi_t *wmip); +A_STATUS wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid); +A_STATUS wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex); +A_STATUS wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en); +A_STATUS wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId, + A_BOOL set); +A_STATUS wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT16 txop, + A_UINT8 eCWmin, A_UINT8 eCWmax, + A_UINT8 aifsn); +A_STATUS wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType, + A_UINT8 trafficClass, A_UINT8 maxRetries, + A_UINT8 enableNotify); + +void wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid); + +A_STATUS wmi_get_roam_tbl_cmd(struct wmi_t *wmip); +A_STATUS wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType); +A_STATUS wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p, + A_UINT8 size); +A_STATUS wmi_set_powersave_timers_cmd(struct wmi_t *wmip, + WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd, + A_UINT8 size); + +A_STATUS wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode); +A_STATUS wmi_opt_tx_frame_cmd(struct wmi_t *wmip, + A_UINT8 frmType, + A_UINT8 *dstMacAddr, + A_UINT8 *bssid, + A_UINT16 optIEDataLen, + A_UINT8 *optIEData); + +A_STATUS wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl); +A_STATUS wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize); +A_STATUS wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSpLen); +A_UINT8 convert_userPriority_to_trafficClass(A_UINT8 userPriority); +A_UINT8 wmi_get_power_mode_cmd(struct wmi_t *wmip); +A_STATUS wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance); + +#ifdef CONFIG_HOST_TCMD_SUPPORT +A_STATUS wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32 len); +#endif + +A_STATUS wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status); +A_STATUS wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd); + + +/* + * This function is used to configure the fix rates mask to the target. + */ +A_STATUS wmi_set_fixrates_cmd(struct wmi_t *wmip, A_INT16 fixRatesMask); +A_STATUS wmi_get_ratemask_cmd(struct wmi_t *wmip); + +A_STATUS wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode); + +A_STATUS wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode); + +A_STATUS wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status); +A_STATUS wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG txEnable); + +A_STATUS wmi_get_keepalive_configured(struct wmi_t *wmip); +A_UINT8 wmi_get_keepalive_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval); + +A_STATUS wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType, + A_UINT8 ieLen,A_UINT8 *ieInfo); + +A_STATUS wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen); + +A_INT32 wmi_get_rate(A_INT8 rateindex); + +/*Wake on Wireless WMI commands*/ +A_STATUS wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip, WMI_SET_HOST_SLEEP_MODE_CMD *cmd); +A_STATUS wmi_set_wow_mode_cmd(struct wmi_t *wmip, WMI_SET_WOW_MODE_CMD *cmd); +A_STATUS wmi_get_wow_list_cmd(struct wmi_t *wmip, WMI_GET_WOW_LIST_CMD *cmd); +A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip, + WMI_ADD_WOW_PATTERN_CMD *cmd, A_UINT8* pattern, A_UINT8* mask, A_UINT8 pattern_size); +A_STATUS wmi_del_wow_pattern_cmd(struct wmi_t *wmip, + WMI_DEL_WOW_PATTERN_CMD *cmd); +A_STATUS wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status); + +A_STATUS +wmi_set_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4); + +A_STATUS +wmi_del_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4); + +bss_t * +wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID); + +void +wmi_node_return (struct wmi_t *wmip, bss_t *bss); + +void +wmi_set_nodeage(struct wmi_t *wmip, A_UINT32 nodeAge); + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +A_STATUS wmi_prof_cfg_cmd(struct wmi_t *wmip, A_UINT32 period, A_UINT32 nbins); +A_STATUS wmi_prof_addr_set_cmd(struct wmi_t *wmip, A_UINT32 addr); +A_STATUS wmi_prof_start_cmd(struct wmi_t *wmip); +A_STATUS wmi_prof_stop_cmd(struct wmi_t *wmip); +A_STATUS wmi_prof_count_get_cmd(struct wmi_t *wmip); +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ +#ifdef OS_ROAM_MANAGEMENT +void wmi_scan_indication (struct wmi_t *wmip); +#endif + +A_STATUS +wmi_set_target_event_report_cmd(struct wmi_t *wmip, WMI_SET_TARGET_EVENT_REPORT_CMD* cmd); + +bss_t *wmi_rm_current_bss (struct wmi_t *wmip, A_UINT8 *id); +A_STATUS wmi_add_current_bss (struct wmi_t *wmip, A_UINT8 *id, bss_t *bss); + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/wmi_host.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/wmi_host.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/wmi_host.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/wmi_host.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,77 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains local definitios for the wmi host module. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _WMI_HOST_H_ +#define _WMI_HOST_H_ + +#include "roaming.h" +#ifdef __cplusplus +extern "C" { +#endif + +struct wmi_stats { + A_UINT32 cmd_len_err; + A_UINT32 cmd_id_err; +}; + +/* Host side link management data structures */ +#define SIGNAL_QUALITY_THRESHOLD_LEVELS 6 +#define SIGNAL_QUALITY_UPPER_THRESHOLD_LEVELS SIGNAL_QUALITY_THRESHOLD_LEVELS +#define SIGNAL_QUALITY_LOWER_THRESHOLD_LEVELS SIGNAL_QUALITY_THRESHOLD_LEVELS +typedef struct sq_threshold_params_s { + A_INT16 upper_threshold[SIGNAL_QUALITY_UPPER_THRESHOLD_LEVELS]; + A_INT16 lower_threshold[SIGNAL_QUALITY_LOWER_THRESHOLD_LEVELS]; + A_UINT32 upper_threshold_valid_count; + A_UINT32 lower_threshold_valid_count; + A_UINT32 polling_interval; + A_UINT8 weight; + A_UINT8 last_rssi; //normally you would expect this to be bss specific but we keep only one instance because its only valid when the device is in a connected state. Not sure if it belongs to host or target. + A_UINT8 last_rssi_poll_event; //Not sure if it belongs to host or target +} SQ_THRESHOLD_PARAMS; +struct wmi_t { + A_BOOL wmi_ready; + A_BOOL wmi_numQoSStream; + A_UINT16 wmi_streamExistsForAC[WMM_NUM_AC]; + A_UINT8 wmi_fatPipeExists; + void *wmi_devt; + struct wmi_stats wmi_stats; + struct ieee80211_node_table wmi_scan_table; + A_UINT8 wmi_bssid[ATH_MAC_LEN]; + A_UINT8 wmi_powerMode; + A_UINT8 wmi_phyMode; + A_UINT8 wmi_keepaliveInterval; + A_MUTEX_T wmi_lock; + HTC_ENDPOINT_ID wmi_endpoint_id; + SQ_THRESHOLD_PARAMS wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_NUM_MAX]; +}; + + +#define LOCK_WMI(w) A_MUTEX_LOCK(&(w)->wmi_lock); +#define UNLOCK_WMI(w) A_MUTEX_UNLOCK(&(w)->wmi_lock); + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_HOST_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/include/wmix.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/wmix.h --- linux-2.6.26/drivers/net/wireless/ar6000/include/wmix.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/include/wmix.h 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,279 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +/* + * This file contains extensions of the WMI protocol specified in the + * Wireless Module Interface (WMI). It includes definitions of all + * extended commands and events. Extensions include useful commands + * that are not directly related to wireless activities. They may + * be hardware-specific, and they might not be supported on all + * implementations. + * + * Extended WMIX commands are encapsulated in a WMI message with + * cmd=WMI_EXTENSION_CMD. + */ + +#ifndef _WMIX_H_ +#define _WMIX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#include "dbglog.h" + +/* + * Extended WMI commands are those that are needed during wireless + * operation, but which are not really wireless commands. This allows, + * for instance, platform-specific commands. Extended WMI commands are + * embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID. + * Extended WMI events are similarly embedded in a WMI event message with + * WMI_EVENT_ID=WMI_EXTENSION_EVENTID. + */ +typedef PREPACK struct { + A_UINT32 commandId; +} POSTPACK WMIX_CMD_HDR; + +typedef enum { + WMIX_DSETOPEN_REPLY_CMDID = 0x2001, + WMIX_DSETDATA_REPLY_CMDID, + WMIX_GPIO_OUTPUT_SET_CMDID, + WMIX_GPIO_INPUT_GET_CMDID, + WMIX_GPIO_REGISTER_SET_CMDID, + WMIX_GPIO_REGISTER_GET_CMDID, + WMIX_GPIO_INTR_ACK_CMDID, + WMIX_HB_CHALLENGE_RESP_CMDID, + WMIX_DBGLOG_CFG_MODULE_CMDID, + WMIX_PROF_CFG_CMDID, + WMIX_PROF_ADDR_SET_CMDID, + WMIX_PROF_START_CMDID, + WMIX_PROF_STOP_CMDID, + WMIX_PROF_COUNT_GET_CMDID, +} WMIX_COMMAND_ID; + +typedef enum { + WMIX_DSETOPENREQ_EVENTID = 0x3001, + WMIX_DSETCLOSE_EVENTID, + WMIX_DSETDATAREQ_EVENTID, + WMIX_GPIO_INTR_EVENTID, + WMIX_GPIO_DATA_EVENTID, + WMIX_GPIO_ACK_EVENTID, + WMIX_HB_CHALLENGE_RESP_EVENTID, + WMIX_DBGLOG_EVENTID, + WMIX_PROF_COUNT_EVENTID, +} WMIX_EVENT_ID; + +/* + * =============DataSet support================= + */ + +/* + * WMIX_DSETOPENREQ_EVENTID + * DataSet Open Request Event + */ +typedef PREPACK struct { + A_UINT32 dset_id; + A_UINT32 targ_dset_handle; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */ +} POSTPACK WMIX_DSETOPENREQ_EVENT; + +/* + * WMIX_DSETCLOSE_EVENTID + * DataSet Close Event + */ +typedef PREPACK struct { + A_UINT32 access_cookie; +} POSTPACK WMIX_DSETCLOSE_EVENT; + +/* + * WMIX_DSETDATAREQ_EVENTID + * DataSet Data Request Event + */ +typedef PREPACK struct { + A_UINT32 access_cookie; + A_UINT32 offset; + A_UINT32 length; + A_UINT32 targ_buf; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */ +} POSTPACK WMIX_DSETDATAREQ_EVENT; + +typedef PREPACK struct { + A_UINT32 status; + A_UINT32 targ_dset_handle; + A_UINT32 targ_reply_fn; + A_UINT32 targ_reply_arg; + A_UINT32 access_cookie; + A_UINT32 size; + A_UINT32 version; +} POSTPACK WMIX_DSETOPEN_REPLY_CMD; + +typedef PREPACK struct { + A_UINT32 status; + A_UINT32 targ_buf; + A_UINT32 targ_reply_fn; + A_UINT32 targ_reply_arg; + A_UINT32 length; + A_UINT8 buf[1]; +} POSTPACK WMIX_DSETDATA_REPLY_CMD; + + +/* + * =============GPIO support================= + * All masks are 18-bit masks with bit N operating on GPIO pin N. + */ + +#include "gpio.h" + +/* + * Set GPIO pin output state. + * In order for output to be driven, a pin must be enabled for output. + * This can be done during initialization through the GPIO Configuration + * DataSet, or during operation with the enable_mask. + * + * If a request is made to simultaneously set/clear or set/disable or + * clear/disable or disable/enable, results are undefined. + */ +typedef PREPACK struct { + A_UINT32 set_mask; /* pins to set */ + A_UINT32 clear_mask; /* pins to clear */ + A_UINT32 enable_mask; /* pins to enable for output */ + A_UINT32 disable_mask; /* pins to disable/tristate */ +} POSTPACK WMIX_GPIO_OUTPUT_SET_CMD; + +/* + * Set a GPIO register. For debug/exceptional cases. + * Values for gpioreg_id are GPIO_REGISTER_IDs, defined in a + * platform-dependent header. + */ +typedef PREPACK struct { + A_UINT32 gpioreg_id; /* GPIO register ID */ + A_UINT32 value; /* value to write */ +} POSTPACK WMIX_GPIO_REGISTER_SET_CMD; + +/* Get a GPIO register. For debug/exceptional cases. */ +typedef PREPACK struct { + A_UINT32 gpioreg_id; /* GPIO register to read */ +} POSTPACK WMIX_GPIO_REGISTER_GET_CMD; + +/* + * Host acknowledges and re-arms GPIO interrupts. A single + * message should be used to acknowledge all interrupts that + * were delivered in an earlier WMIX_GPIO_INTR_EVENT message. + */ +typedef PREPACK struct { + A_UINT32 ack_mask; /* interrupts to acknowledge */ +} POSTPACK WMIX_GPIO_INTR_ACK_CMD; + +/* + * Target informs Host of GPIO interrupts that have ocurred since the + * last WMIX_GIPO_INTR_ACK_CMD was received. Additional information -- + * the current GPIO input values is provided -- in order to support + * use of a GPIO interrupt as a Data Valid signal for other GPIO pins. + */ +typedef PREPACK struct { + A_UINT32 intr_mask; /* pending GPIO interrupts */ + A_UINT32 input_values; /* recent GPIO input values */ +} POSTPACK WMIX_GPIO_INTR_EVENT; + +/* + * Target responds to Host's earlier WMIX_GPIO_INPUT_GET_CMDID request + * using a GPIO_DATA_EVENT with + * value set to the mask of GPIO pin inputs and + * reg_id set to GPIO_ID_NONE + * + * + * Target responds to Hosts's earlier WMIX_GPIO_REGISTER_GET_CMDID request + * using a GPIO_DATA_EVENT with + * value set to the value of the requested register and + * reg_id identifying the register (reflects the original request) + * NB: reg_id supports the future possibility of unsolicited + * WMIX_GPIO_DATA_EVENTs (for polling GPIO input), and it may + * simplify Host GPIO support. + */ +typedef PREPACK struct { + A_UINT32 value; + A_UINT32 reg_id; +} POSTPACK WMIX_GPIO_DATA_EVENT; + +/* + * =============Error Detection support================= + */ + +/* + * WMIX_HB_CHALLENGE_RESP_CMDID + * Heartbeat Challenge Response command + */ +typedef PREPACK struct { + A_UINT32 cookie; + A_UINT32 source; +} POSTPACK WMIX_HB_CHALLENGE_RESP_CMD; + +/* + * WMIX_HB_CHALLENGE_RESP_EVENTID + * Heartbeat Challenge Response Event + */ +#define WMIX_HB_CHALLENGE_RESP_EVENT WMIX_HB_CHALLENGE_RESP_CMD + +typedef PREPACK struct { + struct dbglog_config_s config; +} POSTPACK WMIX_DBGLOG_CFG_MODULE_CMD; + +/* + * =============Target Profiling support================= + */ + +typedef PREPACK struct { + A_UINT32 period; /* Time (in 30.5us ticks) between samples */ + A_UINT32 nbins; +} POSTPACK WMIX_PROF_CFG_CMD; + +typedef PREPACK struct { + A_UINT32 addr; +} POSTPACK WMIX_PROF_ADDR_SET_CMD; + +/* + * Target responds to Hosts's earlier WMIX_PROF_COUNT_GET_CMDID request + * using a WMIX_PROF_COUNT_EVENT with + * addr set to the next address + * count set to the corresponding count + */ +typedef PREPACK struct { + A_UINT32 addr; + A_UINT32 count; +} POSTPACK WMIX_PROF_COUNT_EVENT; + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _WMIX_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/ioctl.c linux-2.6.26-lab126/drivers/net/wireless/ar6000/ioctl.c --- linux-2.6.26/drivers/net/wireless/ar6000/ioctl.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/ioctl.c 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,2756 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#include "ar6000_drv.h" + +static A_UINT8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; +static A_UINT8 null_mac[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; +extern unsigned int wmitimeout; +extern A_WAITQUEUE_HEAD arEvent; +extern int tspecCompliance; +extern int bmienable; +extern int bypasswmi; + +static int +ar6000_ioctl_get_roam_tbl(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if(wmi_get_roam_tbl_cmd(ar->arWmi) != A_OK) { + return -EIO; + } + + return 0; +} + +static int +ar6000_ioctl_get_roam_data(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + /* currently assume only roam times are required */ + if(wmi_get_roam_data_cmd(ar->arWmi, ROAM_DATA_TIME) != A_OK) { + return -EIO; + } + + + return 0; +} + +static int +ar6000_ioctl_set_roam_ctrl(struct net_device *dev, char *userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_SET_ROAM_CTRL_CMD cmd; + A_UINT8 size = sizeof(cmd); + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if (cmd.roamCtrlType == WMI_SET_HOST_BIAS) { + if (cmd.info.bssBiasInfo.numBss > 1) { + size += (cmd.info.bssBiasInfo.numBss - 1) * sizeof(WMI_BSS_BIAS); + } + } + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if(wmi_set_roam_ctrl_cmd(ar->arWmi, &cmd, size) != A_OK) { + return -EIO; + } + + return 0; +} + +static int +ar6000_ioctl_set_powersave_timers(struct net_device *dev, char *userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_POWERSAVE_TIMERS_POLICY_CMD cmd; + A_UINT8 size = sizeof(cmd); + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if(wmi_set_powersave_timers_cmd(ar->arWmi, &cmd, size) != A_OK) { + return -EIO; + } + + return 0; +} + +static int +ar6000_ioctl_set_wmm(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_SET_WMM_CMD cmd; + A_STATUS ret; + + if ((dev->flags & IFF_UP) != IFF_UP) { + return -EIO; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1), + sizeof(cmd))) + { + return -EFAULT; + } + + if (cmd.status == WMI_WMM_ENABLED) { + ar->arWmmEnabled = TRUE; + } else { + ar->arWmmEnabled = FALSE; + } + + ret = wmi_set_wmm_cmd(ar->arWmi, cmd.status); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_set_txop(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_SET_WMM_TXOP_CMD cmd; + A_STATUS ret; + + if ((dev->flags & IFF_UP) != IFF_UP) { + return -EIO; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1), + sizeof(cmd))) + { + return -EFAULT; + } + + ret = wmi_set_wmm_txop(ar->arWmi, cmd.txopEnable); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_get_rd(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + A_STATUS ret = 0; + + if ((dev->flags & IFF_UP) != IFF_UP || ar->arWmiReady == FALSE) { + return -EIO; + } + + if(copy_to_user((char *)((unsigned int*)rq->ifr_data + 1), + &ar->arRegCode, sizeof(ar->arRegCode))) + ret = -EFAULT; + + return ret; +} + + +/* Get power mode command */ +static int +ar6000_ioctl_get_power_mode(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_POWER_MODE_CMD power_mode; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + power_mode.powerMode = wmi_get_power_mode_cmd(ar->arWmi); + if (copy_to_user(rq->ifr_data, &power_mode, sizeof(WMI_POWER_MODE_CMD))) { + ret = -EFAULT; + } + + return ret; +} + + +static int +ar6000_ioctl_set_channelParams(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_CHANNEL_PARAMS_CMD cmd, *cmdp; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (cmd.numChannels > 1) { + cmdp = A_MALLOC(130); + if (copy_from_user(cmdp, rq->ifr_data, + sizeof (*cmdp) + + ((cmd.numChannels - 1) * sizeof(A_UINT16)))) + { + kfree(cmdp); + return -EFAULT; + } + } else { + cmdp = &cmd; + } + + if ((ar->arPhyCapability == WMI_11G_CAPABILITY) && + ((cmdp->phyMode == WMI_11A_MODE) || (cmdp->phyMode == WMI_11AG_MODE))) + { + ret = -EINVAL; + } + + if (!ret && + (wmi_set_channelParams_cmd(ar->arWmi, cmdp->scanParam, cmdp->phyMode, + cmdp->numChannels, cmdp->channelList) + != A_OK)) + { + ret = -EIO; + } + + if (cmd.numChannels > 1) { + kfree(cmdp); + } + + return ret; +} + + +static int +ar6000_ioctl_set_snr_threshold(struct net_device *dev, struct ifreq *rq) +{ + + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_SNR_THRESHOLD_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if( wmi_set_snr_threshold_params(ar->arWmi, &cmd) != A_OK ) { + ret = -EIO; + } + + return ret; +} + +static int +ar6000_ioctl_set_rssi_threshold(struct net_device *dev, struct ifreq *rq) +{ +#define SWAP_THOLD(thold1, thold2) do { \ + USER_RSSI_THOLD tmpThold; \ + tmpThold.tag = thold1.tag; \ + tmpThold.rssi = thold1.rssi; \ + thold1.tag = thold2.tag; \ + thold1.rssi = thold2.rssi; \ + thold2.tag = tmpThold.tag; \ + thold2.rssi = tmpThold.rssi; \ +} while (0) + + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_RSSI_THRESHOLD_PARAMS_CMD cmd; + USER_RSSI_PARAMS rssiParams; + A_INT32 i, j; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user((char *)&rssiParams, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(USER_RSSI_PARAMS))) { + return -EFAULT; + } + cmd.weight = rssiParams.weight; + cmd.pollTime = rssiParams.pollTime; + + A_MEMCPY(ar->rssi_map, &rssiParams.tholds, sizeof(ar->rssi_map)); + /* + * only 6 elements, so use bubble sorting, in ascending order + */ + for (i = 5; i > 0; i--) { + for (j = 0; j < i; j++) { /* above tholds */ + if (ar->rssi_map[j+1].rssi < ar->rssi_map[j].rssi) { + SWAP_THOLD(ar->rssi_map[j+1], ar->rssi_map[j]); + } else if (ar->rssi_map[j+1].rssi == ar->rssi_map[j].rssi) { + return EFAULT; + } + } + } + for (i = 11; i > 6; i--) { + for (j = 6; j < i; j++) { /* below tholds */ + if (ar->rssi_map[j+1].rssi < ar->rssi_map[j].rssi) { + SWAP_THOLD(ar->rssi_map[j+1], ar->rssi_map[j]); + } else if (ar->rssi_map[j+1].rssi == ar->rssi_map[j].rssi) { + return EFAULT; + } + } + } + +#ifdef DEBUG + for (i = 0; i < 12; i++) { + AR_DEBUG2_PRINTF("thold[%d].tag: %d, thold[%d].rssi: %d \n", + i, ar->rssi_map[i].tag, i, ar->rssi_map[i].rssi); + } +#endif + cmd.thresholdAbove1_Val = ar->rssi_map[0].rssi; + cmd.thresholdAbove2_Val = ar->rssi_map[1].rssi; + cmd.thresholdAbove3_Val = ar->rssi_map[2].rssi; + cmd.thresholdAbove4_Val = ar->rssi_map[3].rssi; + cmd.thresholdAbove5_Val = ar->rssi_map[4].rssi; + cmd.thresholdAbove6_Val = ar->rssi_map[5].rssi; + cmd.thresholdBelow1_Val = ar->rssi_map[6].rssi; + cmd.thresholdBelow2_Val = ar->rssi_map[7].rssi; + cmd.thresholdBelow3_Val = ar->rssi_map[8].rssi; + cmd.thresholdBelow4_Val = ar->rssi_map[9].rssi; + cmd.thresholdBelow5_Val = ar->rssi_map[10].rssi; + cmd.thresholdBelow6_Val = ar->rssi_map[11].rssi; + + if( wmi_set_rssi_threshold_params(ar->arWmi, &cmd) != A_OK ) { + ret = -EIO; + } + + return ret; +} + +static int +ar6000_ioctl_set_lq_threshold(struct net_device *dev, struct ifreq *rq) +{ + + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_LQ_THRESHOLD_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(cmd))) { + return -EFAULT; + } + + if( wmi_set_lq_threshold_params(ar->arWmi, &cmd) != A_OK ) { + ret = -EIO; + } + + return ret; +} + + +static int +ar6000_ioctl_set_probedSsid(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_PROBED_SSID_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_probedSsid_cmd(ar->arWmi, cmd.entryIndex, cmd.flag, cmd.ssidLength, + cmd.ssid) != A_OK) + { + ret = -EIO; + } + + return ret; +} + +static int +ar6000_ioctl_set_badAp(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_ADD_BAD_AP_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (cmd.badApIndex > WMI_MAX_BAD_AP_INDEX) { + return -EIO; + } + + if (A_MEMCMP(cmd.bssid, null_mac, AR6000_ETH_ADDR_LEN) == 0) { + /* + * This is a delete badAP. + */ + if (wmi_deleteBadAp_cmd(ar->arWmi, cmd.badApIndex) != A_OK) { + ret = -EIO; + } + } else { + if (wmi_addBadAp_cmd(ar->arWmi, cmd.badApIndex, cmd.bssid) != A_OK) { + ret = -EIO; + } + } + + return ret; +} + +static int +ar6000_ioctl_create_qos(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_CREATE_PSTREAM_CMD cmd; + A_STATUS ret; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + ret = wmi_verify_tspec_params(&cmd, tspecCompliance); + if (ret == A_OK) + ret = wmi_create_pstream_cmd(ar->arWmi, &cmd); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_delete_qos(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_DELETE_PSTREAM_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + ret = wmi_delete_pstream_cmd(ar->arWmi, cmd.trafficClass, cmd.tsid); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_get_qos_queue(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + struct ar6000_queuereq qreq; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if( copy_from_user(&qreq, rq->ifr_data, + sizeof(struct ar6000_queuereq))) + return -EFAULT; + + qreq.activeTsids = wmi_get_mapped_qos_queue(ar->arWmi, qreq.trafficClass); + + if (copy_to_user(rq->ifr_data, &qreq, + sizeof(struct ar6000_queuereq))) + { + ret = -EFAULT; + } + + return ret; +} + +#ifdef CONFIG_HOST_TCMD_SUPPORT +static A_STATUS +ar6000_ioctl_tcmd_get_rx_report(struct net_device *dev, + struct ifreq *rq, A_UINT8 *data, A_UINT32 len) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + A_UINT32 buf[2]; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + ar->tcmdRxReport = 0; + if (wmi_test_cmd(ar->arWmi, data, len) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->tcmdRxReport != 0, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + + buf[0] = ar->tcmdRxTotalPkt; + buf[1] = ar->tcmdRxRssi; + if (!ret && copy_to_user(rq->ifr_data, buf, sizeof(buf))) { + ret = -EFAULT; + } + + up(&ar->arSem); + + return ret; +} + +void +ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + TCMD_CONT_RX * rx_rep = (TCMD_CONT_RX *)results; + + ar->tcmdRxTotalPkt = rx_rep->u.report.totalPkt; + ar->tcmdRxRssi = rx_rep->u.report.rssiInDBm; + ar->tcmdRxReport = 1; + + wake_up(&arEvent); +} +#endif /* CONFIG_HOST_TCMD_SUPPORT*/ + +static int +ar6000_ioctl_set_error_report_bitmask(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_TARGET_ERROR_REPORT_BITMASK cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + ret = wmi_set_error_report_bitmask(ar->arWmi, cmd.bitmask); + + return (ret==0 ? ret : -EINVAL); +} + +static int +ar6000_clear_target_stats(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + TARGET_STATS *pStats = &ar->arTargetStats; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + AR6000_SPIN_LOCK(&ar->arLock, 0); + A_MEMZERO(pStats, sizeof(TARGET_STATS)); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + return ret; +} + +static int +ar6000_ioctl_get_target_stats(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + TARGET_STATS_CMD cmd; + TARGET_STATS *pStats = &ar->arTargetStats; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + ar->statsUpdatePending = TRUE; + + if(wmi_get_stats_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + + if (!ret && copy_to_user(rq->ifr_data, pStats, sizeof(*pStats))) { + ret = -EFAULT; + } + + if (cmd.clearStats == 1) { + ret = ar6000_clear_target_stats(dev); + } + + up(&ar->arSem); + + return ret; +} + +static int +ar6000_ioctl_set_access_params(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_SET_ACCESS_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_access_params_cmd(ar->arWmi, cmd.txop, cmd.eCWmin, cmd.eCWmax, + cmd.aifsn) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +static int +ar6000_ioctl_set_disconnect_timeout(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_DISC_TIMEOUT_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_disctimeout_cmd(ar->arWmi, cmd.disconnectTimeout) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +static int +ar6000_xioctl_set_voice_pkt_size(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_SET_VOICE_PKT_SIZE_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_voice_pkt_size_cmd(ar->arWmi, cmd.voicePktSize) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + + return (ret); +} + +static int +ar6000_xioctl_set_max_sp_len(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_SET_MAX_SP_LEN_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_max_sp_len_cmd(ar->arWmi, cmd.maxSPLen) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + + +static int +ar6000_xioctl_set_bt_status_cmd(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_SET_BT_STATUS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_bt_status_cmd(ar->arWmi, cmd.streamType, cmd.status) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +static int +ar6000_xioctl_set_bt_params_cmd(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_SET_BT_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_bt_params_cmd(ar->arWmi, &cmd) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +#ifdef CONFIG_HOST_GPIO_SUPPORT +struct ar6000_gpio_intr_wait_cmd_s gpio_intr_results; +/* gpio_reg_results and gpio_data_available are protected by arSem */ +static struct ar6000_gpio_register_cmd_s gpio_reg_results; +static A_BOOL gpio_data_available; /* Requested GPIO data available */ +static A_BOOL gpio_intr_available; /* GPIO interrupt info available */ +static A_BOOL gpio_ack_received; /* GPIO ack was received */ + +/* Host-side initialization for General Purpose I/O support */ +void ar6000_gpio_init(void) +{ + gpio_intr_available = FALSE; + gpio_data_available = FALSE; + gpio_ack_received = FALSE; +} + +/* + * Called when a GPIO interrupt is received from the Target. + * intr_values shows which GPIO pins have interrupted. + * input_values shows a recent value of GPIO pins. + */ +void +ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values) +{ + gpio_intr_results.intr_mask = intr_mask; + gpio_intr_results.input_values = input_values; + *((volatile A_BOOL *)&gpio_intr_available) = TRUE; + wake_up(&arEvent); +} + +/* + * This is called when a response is received from the Target + * for a previous or ar6000_gpio_input_get or ar6000_gpio_register_get + * call. + */ +void +ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value) +{ + gpio_reg_results.gpioreg_id = reg_id; + gpio_reg_results.value = value; + *((volatile A_BOOL *)&gpio_data_available) = TRUE; + wake_up(&arEvent); +} + +/* + * This is called when an acknowledgement is received from the Target + * for a previous or ar6000_gpio_output_set or ar6000_gpio_register_set + * call. + */ +void +ar6000_gpio_ack_rx(void) +{ + gpio_ack_received = TRUE; + wake_up(&arEvent); +} + +A_STATUS +ar6000_gpio_output_set(struct net_device *dev, + A_UINT32 set_mask, + A_UINT32 clear_mask, + A_UINT32 enable_mask, + A_UINT32 disable_mask) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + gpio_ack_received = FALSE; + return wmi_gpio_output_set(ar->arWmi, + set_mask, clear_mask, enable_mask, disable_mask); +} + +static A_STATUS +ar6000_gpio_input_get(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + *((volatile A_BOOL *)&gpio_data_available) = FALSE; + return wmi_gpio_input_get(ar->arWmi); +} + +static A_STATUS +ar6000_gpio_register_set(struct net_device *dev, + A_UINT32 gpioreg_id, + A_UINT32 value) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + gpio_ack_received = FALSE; + return wmi_gpio_register_set(ar->arWmi, gpioreg_id, value); +} + +static A_STATUS +ar6000_gpio_register_get(struct net_device *dev, + A_UINT32 gpioreg_id) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + *((volatile A_BOOL *)&gpio_data_available) = FALSE; + return wmi_gpio_register_get(ar->arWmi, gpioreg_id); +} + +static A_STATUS +ar6000_gpio_intr_ack(struct net_device *dev, + A_UINT32 ack_mask) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + gpio_intr_available = FALSE; + return wmi_gpio_intr_ack(ar->arWmi, ack_mask); +} +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +static struct prof_count_s prof_count_results; +static A_BOOL prof_count_available; /* Requested GPIO data available */ + +static A_STATUS +prof_count_get(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + *((volatile A_BOOL *)&prof_count_available) = FALSE; + return wmi_prof_count_get_cmd(ar->arWmi); +} + +/* + * This is called when a response is received from the Target + * for a previous prof_count_get call. + */ +void +prof_count_rx(A_UINT32 addr, A_UINT32 count) +{ + prof_count_results.addr = addr; + prof_count_results.count = count; + *((volatile A_BOOL *)&prof_count_available) = TRUE; + wake_up(&arEvent); +} +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + +int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + HIF_DEVICE *hifDevice = ar->arHifDevice; + int ret, param; + unsigned int address = 0; + unsigned int length = 0; + unsigned char *buffer; + char *userdata; + A_UINT32 connectCtrlFlags; + + + static WMI_SCAN_PARAMS_CMD scParams = {0, 0, 0, 0, 0, + WMI_SHORTSCANRATIO_DEFAULT, + DEFAULT_SCAN_CTRL_FLAGS, + 0}; + WMI_SET_AKMP_PARAMS_CMD akmpParams; + WMI_SET_PMKID_LIST_CMD pmkidInfo; + + if (cmd == AR6000_IOCTL_EXTENDED) + { + /* + * This allows for many more wireless ioctls than would otherwise + * be available. Applications embed the actual ioctl command in + * the first word of the parameter block, and use the command + * AR6000_IOCTL_EXTENDED_CMD on the ioctl call. + */ + get_user(cmd, (int *)rq->ifr_data); + userdata = (char *)(((unsigned int *)rq->ifr_data)+1); + } + else + { + userdata = (char *)rq->ifr_data; + } + + if ((ar->arWlanState == WLAN_DISABLED) && + ((cmd != AR6000_XIOCTRL_WMI_SET_WLAN_STATE) && + (cmd != AR6000_XIOCTL_DIAG_READ) && + (cmd != AR6000_XIOCTL_DIAG_WRITE))) + { + return -EIO; + } + + ret = 0; + switch(cmd) + { +#ifdef CONFIG_HOST_TCMD_SUPPORT + case AR6000_XIOCTL_TCMD_CONT_TX: + { + TCMD_CONT_TX txCmd; + + if (ar->tcmdPm == TCMD_PM_SLEEP) { + A_PRINTF("Can NOT send tx tcmd when target is asleep! \n"); + return -EFAULT; + } + + if(copy_from_user(&txCmd, userdata, sizeof(TCMD_CONT_TX))) + return -EFAULT; + wmi_test_cmd(ar->arWmi,(A_UINT8 *)&txCmd, sizeof(TCMD_CONT_TX)); + } + break; + case AR6000_XIOCTL_TCMD_CONT_RX: + { + TCMD_CONT_RX rxCmd; + + if (ar->tcmdPm == TCMD_PM_SLEEP) { + A_PRINTF("Can NOT send rx tcmd when target is asleep! \n"); + return -EFAULT; + } + if(copy_from_user(&rxCmd, userdata, sizeof(TCMD_CONT_RX))) + return -EFAULT; + switch(rxCmd.act) + { + case TCMD_CONT_RX_PROMIS: + case TCMD_CONT_RX_FILTER: + case TCMD_CONT_RX_SETMAC: + case TCMD_CONT_RX_SET_ANT_SWITCH_TABLE: + wmi_test_cmd(ar->arWmi,(A_UINT8 *)&rxCmd, + sizeof(TCMD_CONT_RX)); + break; + case TCMD_CONT_RX_REPORT: + ar6000_ioctl_tcmd_get_rx_report(dev, rq, + (A_UINT8 *)&rxCmd, sizeof(TCMD_CONT_RX)); + break; + default: + A_PRINTF("Unknown Cont Rx mode: %d\n",rxCmd.act); + return -EINVAL; + } + } + break; + case AR6000_XIOCTL_TCMD_PM: + { + TCMD_PM pmCmd; + + if(copy_from_user(&pmCmd, userdata, sizeof(TCMD_PM))) + return -EFAULT; + ar->tcmdPm = pmCmd.mode; + wmi_test_cmd(ar->arWmi, (A_UINT8*)&pmCmd, sizeof(TCMD_PM)); + } + break; +#endif /* CONFIG_HOST_TCMD_SUPPORT */ + + case AR6000_XIOCTL_BMI_DONE: + if(bmienable) + { + ret = ar6000_init(dev); + } + else + { + ret = BMIDone(hifDevice); + } + break; + + case AR6000_XIOCTL_BMI_READ_MEMORY: + get_user(address, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + AR_DEBUG_PRINTF("Read Memory (address: 0x%x, length: %d)\n", + address, length); + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + ret = BMIReadMemory(hifDevice, address, buffer, length); + if (copy_to_user(rq->ifr_data, buffer, length)) { + ret = -EFAULT; + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + break; + + case AR6000_XIOCTL_BMI_WRITE_MEMORY: + get_user(address, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + AR_DEBUG_PRINTF("Write Memory (address: 0x%x, length: %d)\n", + address, length); + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + if (copy_from_user(buffer, &userdata[sizeof(address) + + sizeof(length)], length)) + { + ret = -EFAULT; + } else { + ret = BMIWriteMemory(hifDevice, address, buffer, length); + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + break; + + case AR6000_XIOCTL_BMI_TEST: + AR_DEBUG_PRINTF("No longer supported\n"); + ret = -EOPNOTSUPP; + break; + + case AR6000_XIOCTL_BMI_EXECUTE: + get_user(address, (unsigned int *)userdata); + get_user(param, (unsigned int *)userdata + 1); + AR_DEBUG_PRINTF("Execute (address: 0x%x, param: %d)\n", + address, param); + ret = BMIExecute(hifDevice, address, ¶m); + put_user(param, (unsigned int *)rq->ifr_data); /* return value */ + break; + + case AR6000_XIOCTL_BMI_SET_APP_START: + get_user(address, (unsigned int *)userdata); + AR_DEBUG_PRINTF("Set App Start (address: 0x%x)\n", address); + ret = BMISetAppStart(hifDevice, address); + break; + + case AR6000_XIOCTL_BMI_READ_SOC_REGISTER: + get_user(address, (unsigned int *)userdata); + ret = BMIReadSOCRegister(hifDevice, address, ¶m); + put_user(param, (unsigned int *)rq->ifr_data); /* return value */ + break; + + case AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER: + get_user(address, (unsigned int *)userdata); + get_user(param, (unsigned int *)userdata + 1); + ret = BMIWriteSOCRegister(hifDevice, address, param); + break; + +#ifdef HTC_RAW_INTERFACE + case AR6000_XIOCTL_HTC_RAW_OPEN: + ret = A_OK; + if (!arRawIfEnabled(ar)) { + /* make sure block size is set in case the target was reset since last + * BMI phase (i.e. flashup downloads) */ + ret = ar6000_set_htc_params(ar->arHifDevice, + ar->arTargetType, + 0, /* use default yield */ + 0 /* use default number of HTC ctrl buffers */ + ); + if (A_FAILED(ret)) { + break; + } + /* Terminate the BMI phase */ + ret = BMIDone(hifDevice); + if (ret == A_OK) { + ret = ar6000_htc_raw_open(ar); + } + } + break; + + case AR6000_XIOCTL_HTC_RAW_CLOSE: + if (arRawIfEnabled(ar)) { + ret = ar6000_htc_raw_close(ar); + arRawIfEnabled(ar) = FALSE; + } else { + ret = A_ERROR; + } + break; + + case AR6000_XIOCTL_HTC_RAW_READ: + if (arRawIfEnabled(ar)) { + unsigned int streamID; + get_user(streamID, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + mb(); /* Memory barrier */ + buffer = rq->ifr_data + sizeof(length); + ret = ar6000_htc_raw_read(ar, (HTC_RAW_STREAM_ID)streamID, + buffer, length); + put_user(ret, (unsigned int *)rq->ifr_data); + } else { + ret = A_ERROR; + } + break; + + case AR6000_XIOCTL_HTC_RAW_WRITE: + if (arRawIfEnabled(ar)) { + unsigned int streamID; + get_user(streamID, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + mb(); /* Memory barrier */ + buffer = userdata + sizeof(streamID) + sizeof(length); + ret = ar6000_htc_raw_write(ar, (HTC_RAW_STREAM_ID)streamID, + buffer, length); + put_user(ret, (unsigned int *)rq->ifr_data); + } else { + ret = A_ERROR; + } + break; +#endif /* HTC_RAW_INTERFACE */ + + case AR6000_XIOCTL_BMI_LZ_STREAM_START: + get_user(address, (unsigned int *)userdata); + AR_DEBUG_PRINTF("Start Compressed Stream (address: 0x%x)\n", address); + ret = BMILZStreamStart(hifDevice, address); + break; + + case AR6000_XIOCTL_BMI_LZ_DATA: + get_user(length, (unsigned int *)userdata); + AR_DEBUG_PRINTF("Send Compressed Data (length: %d)\n", length); + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + if (copy_from_user(buffer, &userdata[sizeof(length)], length)) + { + ret = -EFAULT; + } else { + ret = BMILZData(hifDevice, buffer, length); + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + break; + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) + /* + * Optional support for Target-side profiling. + * Not needed in production. + */ + + /* Configure Target-side profiling */ + case AR6000_XIOCTL_PROF_CFG: + { + A_UINT32 period; + A_UINT32 nbins; + get_user(period, (unsigned int *)userdata); + get_user(nbins, (unsigned int *)userdata + 1); + + if (wmi_prof_cfg_cmd(ar->arWmi, period, nbins) != A_OK) { + ret = -EIO; + } + + break; + } + + /* Start a profiling bucket/bin at the specified address */ + case AR6000_XIOCTL_PROF_ADDR_SET: + { + A_UINT32 addr; + get_user(addr, (unsigned int *)userdata); + + if (wmi_prof_addr_set_cmd(ar->arWmi, addr) != A_OK) { + ret = -EIO; + } + + break; + } + + /* START Target-side profiling */ + case AR6000_XIOCTL_PROF_START: + wmi_prof_start_cmd(ar->arWmi); + break; + + /* STOP Target-side profiling */ + case AR6000_XIOCTL_PROF_STOP: + wmi_prof_stop_cmd(ar->arWmi); + break; + case AR6000_XIOCTL_PROF_COUNT_GET: + { + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + prof_count_available = FALSE; + ret = prof_count_get(dev); + if (ret != A_OK) { + up(&ar->arSem); + return -EIO; + } + + /* Wait for Target to respond. */ + wait_event_interruptible(arEvent, prof_count_available); + if (signal_pending(current)) { + ret = -EINTR; + } else { + if (copy_to_user(userdata, &prof_count_results, + sizeof(prof_count_results))) + { + ret = -EFAULT; + } + } + up(&ar->arSem); + break; + } +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + + case AR6000_IOCTL_WMI_GETREV: + { + if (copy_to_user(rq->ifr_data, &ar->arVersion, + sizeof(ar->arVersion))) + { + ret = -EFAULT; + } + break; + } + case AR6000_IOCTL_WMI_SETPWR: + { + WMI_POWER_MODE_CMD pwrModeCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&pwrModeCmd, userdata, + sizeof(pwrModeCmd))) + { + ret = -EFAULT; + } else { + if (wmi_powermode_cmd(ar->arWmi, pwrModeCmd.powerMode) + != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS: + { + WMI_IBSS_PM_CAPS_CMD ibssPmCaps; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&ibssPmCaps, userdata, + sizeof(ibssPmCaps))) + { + ret = -EFAULT; + } else { + if (wmi_ibsspmcaps_cmd(ar->arWmi, ibssPmCaps.power_saving, ibssPmCaps.ttl, + ibssPmCaps.atim_windows, ibssPmCaps.timeout_value) != A_OK) + { + ret = -EIO; + } + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arIbssPsEnable = ibssPmCaps.power_saving; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + break; + } + case AR6000_IOCTL_WMI_SET_PMPARAMS: + { + WMI_POWER_PARAMS_CMD pmParams; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&pmParams, userdata, + sizeof(pmParams))) + { + ret = -EFAULT; + } else { + if (wmi_pmparams_cmd(ar->arWmi, pmParams.idle_period, + pmParams.pspoll_number, + pmParams.dtim_policy) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SETSCAN: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&scParams, userdata, + sizeof(scParams))) + { + ret = -EFAULT; + } else { + if (CAN_SCAN_IN_CONNECT(scParams.scanCtrlFlags)) { + ar->arSkipScan = FALSE; + } else { + ar->arSkipScan = TRUE; + } + + if (wmi_scanparams_cmd(ar->arWmi, scParams.fg_start_period, + scParams.fg_end_period, + scParams.bg_period, + scParams.minact_chdwell_time, + scParams.maxact_chdwell_time, + scParams.pas_chdwell_time, + scParams.shortScanRatio, + scParams.scanCtrlFlags, + scParams.max_dfsch_act_time) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SETLISTENINT: + { + WMI_LISTEN_INT_CMD listenCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&listenCmd, userdata, + sizeof(listenCmd))) + { + ret = -EFAULT; + } else { + if (wmi_listeninterval_cmd(ar->arWmi, listenCmd.listenInterval, listenCmd.numBeacons) != A_OK) { + ret = -EIO; + } else { + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arListenInterval = param; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + + } + break; + } + case AR6000_IOCTL_WMI_SET_BMISS_TIME: + { + WMI_BMISS_TIME_CMD bmissCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&bmissCmd, userdata, + sizeof(bmissCmd))) + { + ret = -EFAULT; + } else { + if (wmi_bmisstime_cmd(ar->arWmi, bmissCmd.bmissTime, bmissCmd.numBeacons) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SETBSSFILTER: + { + WMI_BSS_FILTER_CMD filt; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&filt, userdata, + sizeof(filt))) + { + ret = -EFAULT; + } else { + if (wmi_bssfilter_cmd(ar->arWmi, filt.bssFilter, filt.ieMask) + != A_OK) { + ret = -EIO; + } else { + ar->arUserBssFilter = filt.bssFilter; + } + } + break; + } + case AR6000_IOCTL_WMI_SET_SNRTHRESHOLD: + { + ret = ar6000_ioctl_set_snr_threshold(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD: + { + ret = ar6000_ioctl_set_rssi_threshold(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_CLR_RSSISNR: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } + ret = wmi_clr_rssi_snr(ar->arWmi); + break; + } + case AR6000_XIOCTL_WMI_SET_LQTHRESHOLD: + { + ret = ar6000_ioctl_set_lq_threshold(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_SET_LPREAMBLE: + { + WMI_SET_LPREAMBLE_CMD setLpreambleCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setLpreambleCmd, userdata, + sizeof(setLpreambleCmd))) + { + ret = -EFAULT; + } else { + if (wmi_set_lpreamble_cmd(ar->arWmi, setLpreambleCmd.status) + != A_OK) + { + ret = -EIO; + } + } + + break; + } + case AR6000_XIOCTL_WMI_SET_RTS: + { + WMI_SET_RTS_CMD rtsCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&rtsCmd, userdata, + sizeof(rtsCmd))) + { + ret = -EFAULT; + } else { + if (wmi_set_rts_cmd(ar->arWmi, rtsCmd.threshold) + != A_OK) + { + ret = -EIO; + } + } + + break; + } + case AR6000_XIOCTL_WMI_SET_WMM: + { + ret = ar6000_ioctl_set_wmm(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_SET_TXOP: + { + ret = ar6000_ioctl_set_txop(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_GET_RD: + { + ret = ar6000_ioctl_get_rd(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_CHANNELPARAMS: + { + ret = ar6000_ioctl_set_channelParams(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_PROBEDSSID: + { + ret = ar6000_ioctl_set_probedSsid(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_BADAP: + { + ret = ar6000_ioctl_set_badAp(dev, rq); + break; + } + case AR6000_IOCTL_WMI_CREATE_QOS: + { + ret = ar6000_ioctl_create_qos(dev, rq); + break; + } + case AR6000_IOCTL_WMI_DELETE_QOS: + { + ret = ar6000_ioctl_delete_qos(dev, rq); + break; + } + case AR6000_IOCTL_WMI_GET_QOS_QUEUE: + { + ret = ar6000_ioctl_get_qos_queue(dev, rq); + break; + } + case AR6000_IOCTL_WMI_GET_TARGET_STATS: + { + ret = ar6000_ioctl_get_target_stats(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK: + { + ret = ar6000_ioctl_set_error_report_bitmask(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_ASSOC_INFO: + { + WMI_SET_ASSOC_INFO_CMD cmd; + A_UINT8 assocInfo[WMI_MAX_ASSOC_INFO_LEN]; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + get_user(cmd.ieType, userdata); + if (cmd.ieType >= WMI_MAX_ASSOC_INFO_TYPE) { + ret = -EIO; + } else { + get_user(cmd.bufferSize, userdata + 1); + if (cmd.bufferSize > WMI_MAX_ASSOC_INFO_LEN) { + ret = -EFAULT; + break; + } + if (copy_from_user(assocInfo, userdata + 2, + cmd.bufferSize)) + { + ret = -EFAULT; + } else { + if (wmi_associnfo_cmd(ar->arWmi, cmd.ieType, + cmd.bufferSize, + assocInfo) != A_OK) + { + ret = -EIO; + } + } + } + } + break; + } + case AR6000_IOCTL_WMI_SET_ACCESS_PARAMS: + { + ret = ar6000_ioctl_set_access_params(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_DISC_TIMEOUT: + { + ret = ar6000_ioctl_set_disconnect_timeout(dev, rq); + break; + } + case AR6000_XIOCTL_FORCE_TARGET_RESET: + { + if (ar->arHtcTarget) + { +// HTCForceReset(htcTarget); + } + else + { + AR_DEBUG_PRINTF("ar6000_ioctl cannot attempt reset.\n"); + } + break; + } + case AR6000_XIOCTL_TARGET_INFO: + case AR6000_XIOCTL_CHECK_TARGET_READY: /* backwards compatibility */ + { + /* If we made it to here, then the Target exists and is ready. */ + + if (cmd == AR6000_XIOCTL_TARGET_INFO) { + if (copy_to_user((A_UINT32 *)rq->ifr_data, &ar->arVersion.target_ver, + sizeof(ar->arVersion.target_ver))) + { + ret = -EFAULT; + } + if (copy_to_user(((A_UINT32 *)rq->ifr_data)+1, &ar->arTargetType, + sizeof(ar->arTargetType))) + { + ret = -EFAULT; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS: + { + WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD hbparam; + + if (copy_from_user(&hbparam, userdata, sizeof(hbparam))) + { + ret = -EFAULT; + } else { + AR6000_SPIN_LOCK(&ar->arLock, 0); + /* Start a cyclic timer with the parameters provided. */ + if (hbparam.frequency) { + ar->arHBChallengeResp.frequency = hbparam.frequency; + } + if (hbparam.threshold) { + ar->arHBChallengeResp.missThres = hbparam.threshold; + } + + /* Delete the pending timer and start a new one */ + if (timer_pending(&ar->arHBChallengeResp.timer)) { + A_UNTIMEOUT(&ar->arHBChallengeResp.timer); + } + A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + break; + } + case AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP: + { + A_UINT32 cookie; + + if (copy_from_user(&cookie, userdata, sizeof(cookie))) { + return -EFAULT; + } + + /* Send the challenge on the control channel */ + if (wmi_get_challenge_resp_cmd(ar->arWmi, cookie, APP_HB_CHALLENGE) != A_OK) { + return -EIO; + } + break; + } +#ifdef USER_KEYS + case AR6000_XIOCTL_USER_SETKEYS: + { + + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_RUN; + + if (copy_from_user(&ar->user_key_ctrl, userdata, + sizeof(ar->user_key_ctrl))) + { + return -EFAULT; + } + + A_PRINTF("ar6000 USER set key %x\n", ar->user_key_ctrl); + break; + } +#endif /* USER_KEYS */ + +#ifdef CONFIG_HOST_GPIO_SUPPORT + case AR6000_XIOCTL_GPIO_OUTPUT_SET: + { + struct ar6000_gpio_output_set_cmd_s gpio_output_set_cmd; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (copy_from_user(&gpio_output_set_cmd, userdata, + sizeof(gpio_output_set_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_output_set(dev, + gpio_output_set_cmd.set_mask, + gpio_output_set_cmd.clear_mask, + gpio_output_set_cmd.enable_mask, + gpio_output_set_cmd.disable_mask); + if (ret != A_OK) { + ret = EIO; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_INPUT_GET: + { + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + ret = ar6000_gpio_input_get(dev); + if (ret != A_OK) { + up(&ar->arSem); + return -EIO; + } + + /* Wait for Target to respond. */ + wait_event_interruptible(arEvent, gpio_data_available); + if (signal_pending(current)) { + ret = -EINTR; + } else { + A_ASSERT(gpio_reg_results.gpioreg_id == GPIO_ID_NONE); + + if (copy_to_user(userdata, &gpio_reg_results.value, + sizeof(gpio_reg_results.value))) + { + ret = -EFAULT; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_REGISTER_SET: + { + struct ar6000_gpio_register_cmd_s gpio_register_cmd; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (copy_from_user(&gpio_register_cmd, userdata, + sizeof(gpio_register_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_register_set(dev, + gpio_register_cmd.gpioreg_id, + gpio_register_cmd.value); + if (ret != A_OK) { + ret = EIO; + } + + /* Wait for acknowledgement from Target */ + wait_event_interruptible(arEvent, gpio_ack_received); + if (signal_pending(current)) { + ret = -EINTR; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_REGISTER_GET: + { + struct ar6000_gpio_register_cmd_s gpio_register_cmd; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (copy_from_user(&gpio_register_cmd, userdata, + sizeof(gpio_register_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_register_get(dev, gpio_register_cmd.gpioreg_id); + if (ret != A_OK) { + up(&ar->arSem); + return -EIO; + } + + /* Wait for Target to respond. */ + wait_event_interruptible(arEvent, gpio_data_available); + if (signal_pending(current)) { + ret = -EINTR; + } else { + A_ASSERT(gpio_register_cmd.gpioreg_id == gpio_reg_results.gpioreg_id); + if (copy_to_user(userdata, &gpio_reg_results, + sizeof(gpio_reg_results))) + { + ret = -EFAULT; + } + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_INTR_ACK: + { + struct ar6000_gpio_intr_ack_cmd_s gpio_intr_ack_cmd; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (copy_from_user(&gpio_intr_ack_cmd, userdata, + sizeof(gpio_intr_ack_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_intr_ack(dev, gpio_intr_ack_cmd.ack_mask); + if (ret != A_OK) { + ret = EIO; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_INTR_WAIT: + { + /* Wait for Target to report an interrupt. */ + dev_hold(dev); + rtnl_unlock(); + wait_event_interruptible(arEvent, gpio_intr_available); + rtnl_lock(); + __dev_put(dev); + + if (signal_pending(current)) { + ret = -EINTR; + } else { + if (copy_to_user(userdata, &gpio_intr_results, + sizeof(gpio_intr_results))) + { + ret = -EFAULT; + } + } + break; + } +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + + case AR6000_XIOCTL_DBGLOG_CFG_MODULE: + { + struct ar6000_dbglog_module_config_s config; + + if (copy_from_user(&config, userdata, sizeof(config))) { + return -EFAULT; + } + + /* Send the challenge on the control channel */ + if (wmi_config_debug_module_cmd(ar->arWmi, config.mmask, + config.tsr, config.rep, + config.size, config.valid) != A_OK) + { + return -EIO; + } + break; + } + + case AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS: + { + /* Send the challenge on the control channel */ + if (ar6000_dbglog_get_debug_logs(ar) != A_OK) + { + return -EIO; + } + break; + } + + case AR6000_XIOCTL_SET_ADHOC_BSSID: + { + WMI_SET_ADHOC_BSSID_CMD adhocBssid; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&adhocBssid, userdata, + sizeof(adhocBssid))) + { + ret = -EFAULT; + } else if (A_MEMCMP(adhocBssid.bssid, bcast_mac, + AR6000_ETH_ADDR_LEN) == 0) + { + ret = -EFAULT; + } else { + + A_MEMCPY(ar->arReqBssid, adhocBssid.bssid, sizeof(ar->arReqBssid)); + } + break; + } + + case AR6000_XIOCTL_SET_OPT_MODE: + { + WMI_SET_OPT_MODE_CMD optModeCmd; + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&optModeCmd, userdata, + sizeof(optModeCmd))) + { + ret = -EFAULT; + } else if (ar->arConnected && optModeCmd.optMode == SPECIAL_ON) { + ret = -EFAULT; + + } else if (wmi_set_opt_mode_cmd(ar->arWmi, optModeCmd.optMode) + != A_OK) + { + ret = -EIO; + } + break; + } + + case AR6000_XIOCTL_OPT_SEND_FRAME: + { + WMI_OPT_TX_FRAME_CMD optTxFrmCmd; + A_UINT8 data[MAX_OPT_DATA_LEN]; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&optTxFrmCmd, userdata, + sizeof(optTxFrmCmd))) + { + ret = -EFAULT; + } else if (copy_from_user(data, + userdata+sizeof(WMI_OPT_TX_FRAME_CMD)-1, + optTxFrmCmd.optIEDataLen)) + { + ret = -EFAULT; + } else { + ret = wmi_opt_tx_frame_cmd(ar->arWmi, + optTxFrmCmd.frmType, + optTxFrmCmd.dstAddr, + optTxFrmCmd.bssid, + optTxFrmCmd.optIEDataLen, + data); + } + + break; + } + case AR6000_XIOCTL_WMI_SETRETRYLIMITS: + { + WMI_SET_RETRY_LIMITS_CMD setRetryParams; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setRetryParams, userdata, + sizeof(setRetryParams))) + { + ret = -EFAULT; + } else { + if (wmi_set_retry_limits_cmd(ar->arWmi, setRetryParams.frameType, + setRetryParams.trafficClass, + setRetryParams.maxRetries, + setRetryParams.enableNotify) != A_OK) + { + ret = -EIO; + } + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arMaxRetries = setRetryParams.maxRetries; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + break; + } + + case AR6000_XIOCTL_SET_ADHOC_BEACON_INTVAL: + { + WMI_BEACON_INT_CMD bIntvlCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&bIntvlCmd, userdata, + sizeof(bIntvlCmd))) + { + ret = -EFAULT; + } else if (wmi_set_adhoc_bconIntvl_cmd(ar->arWmi, bIntvlCmd.beaconInterval) + != A_OK) + { + ret = -EIO; + } + break; + } + case IEEE80211_IOCTL_SETAUTHALG: + { + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + struct ieee80211req_authalg req; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&req, userdata, + sizeof(struct ieee80211req_authalg))) + { + ret = -EFAULT; + } else if (req.auth_alg == AUTH_ALG_OPEN_SYSTEM) { + ar->arDot11AuthMode = OPEN_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arGroupCrypto = NONE_CRYPT; + } else if (req.auth_alg == AUTH_ALG_LEAP) { + ar->arDot11AuthMode = LEAP_AUTH; + } else { + ret = -EIO; + } + break; + } + + case AR6000_XIOCTL_SET_VOICE_PKT_SIZE: + ret = ar6000_xioctl_set_voice_pkt_size(dev, userdata); + break; + + case AR6000_XIOCTL_SET_MAX_SP: + ret = ar6000_xioctl_set_max_sp_len(dev, userdata); + break; + + case AR6000_XIOCTL_WMI_GET_ROAM_TBL: + ret = ar6000_ioctl_get_roam_tbl(dev, rq); + break; + case AR6000_XIOCTL_WMI_SET_ROAM_CTRL: + ret = ar6000_ioctl_set_roam_ctrl(dev, userdata); + break; + case AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS: + ret = ar6000_ioctl_set_powersave_timers(dev, userdata); + break; + case AR6000_XIOCTRL_WMI_GET_POWER_MODE: + ret = ar6000_ioctl_get_power_mode(dev, rq); + break; + case AR6000_XIOCTRL_WMI_SET_WLAN_STATE: + get_user(ar->arWlanState, (unsigned int *)userdata); + if (ar->arWmiReady == FALSE) { + ret = -EIO; + break; + } + + if (ar->arWlanState == WLAN_ENABLED) { + /* Enable foreground scanning */ + if (wmi_scanparams_cmd(ar->arWmi, scParams.fg_start_period, + scParams.fg_end_period, + scParams.bg_period, + scParams.minact_chdwell_time, + scParams.maxact_chdwell_time, + scParams.pas_chdwell_time, + scParams.shortScanRatio, + scParams.scanCtrlFlags, + scParams.max_dfsch_act_time) != A_OK) + { + ret = -EIO; + } + if (ar->arSsidLen) { + ar->arConnectPending = TRUE; + if (wmi_connect_cmd(ar->arWmi, ar->arNetworkType, + ar->arDot11AuthMode, ar->arAuthMode, + ar->arPairwiseCrypto, + ar->arPairwiseCryptoLen, + ar->arGroupCrypto, ar->arGroupCryptoLen, + ar->arSsidLen, ar->arSsid, + ar->arReqBssid, ar->arChannelHint, + ar->arConnectCtrlFlags) != A_OK) + { + ret = -EIO; + ar->arConnectPending = FALSE; + } + } + } else { + /* Disconnect from the AP and disable foreground scanning */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) { + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + wmi_disconnect_cmd(ar->arWmi); + } else { + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + + if (wmi_scanparams_cmd(ar->arWmi, 0xFFFF, 0, 0, 0, 0, 0, 0, 0xFF, 0) != A_OK) + { + ret = -EIO; + } + } + break; + case AR6000_XIOCTL_WMI_GET_ROAM_DATA: + ret = ar6000_ioctl_get_roam_data(dev, rq); + break; + case AR6000_XIOCTL_WMI_SET_BT_STATUS: + ret = ar6000_xioctl_set_bt_status_cmd(dev, userdata); + break; + case AR6000_XIOCTL_WMI_SET_BT_PARAMS: + ret = ar6000_xioctl_set_bt_params_cmd(dev, userdata); + break; + case AR6000_XIOCTL_WMI_STARTSCAN: + { + WMI_START_SCAN_CMD setStartScanCmd, *cmdp; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setStartScanCmd, userdata, + sizeof(setStartScanCmd))) + { + ret = -EFAULT; + } else { + if (setStartScanCmd.numChannels > 1) { + cmdp = A_MALLOC(130); + if (copy_from_user(cmdp, userdata, + sizeof (*cmdp) + + ((setStartScanCmd.numChannels - 1) * + sizeof(A_UINT16)))) + { + kfree(cmdp); + return -EFAULT; + } + } else { + cmdp = &setStartScanCmd; + } + + if (wmi_startscan_cmd(ar->arWmi, cmdp->scanType, + cmdp->forceFgScan, + cmdp->isLegacy, + cmdp->homeDwellTime, + cmdp->forceScanInterval, + cmdp->numChannels, + cmdp->channelList) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SETFIXRATES: + { + WMI_FIX_RATES_CMD setFixRatesCmd; + A_STATUS returnStatus; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setFixRatesCmd, userdata, + sizeof(setFixRatesCmd))) + { + ret = -EFAULT; + } else { + returnStatus = wmi_set_fixrates_cmd(ar->arWmi, setFixRatesCmd.fixRateMask); + if (returnStatus == A_EINVAL) + { + ret = -EINVAL; + } + else if(returnStatus != A_OK) { + ret = -EIO; + } + } + break; + } + + case AR6000_XIOCTL_WMI_GETFIXRATES: + { + WMI_FIX_RATES_CMD getFixRatesCmd; + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + /* Used copy_from_user/copy_to_user to access user space data */ + if (copy_from_user(&getFixRatesCmd, userdata, sizeof(getFixRatesCmd))) { + ret = -EFAULT; + } else { + ar->arRateMask = 0xFFFF; + + if (wmi_get_ratemask_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->arRateMask != 0xFFFF, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + + if (!ret) { + getFixRatesCmd.fixRateMask = ar->arRateMask; + } + + if(copy_to_user(userdata, &getFixRatesCmd, sizeof(getFixRatesCmd))) { + ret = -EFAULT; + } + + up(&ar->arSem); + } + break; + } + case AR6000_XIOCTL_WMI_SET_AUTHMODE: + { + WMI_SET_AUTH_MODE_CMD setAuthMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setAuthMode, userdata, + sizeof(setAuthMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_authmode_cmd(ar->arWmi, setAuthMode.mode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_REASSOCMODE: + { + WMI_SET_REASSOC_MODE_CMD setReassocMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setReassocMode, userdata, + sizeof(setReassocMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_reassocmode_cmd(ar->arWmi, setReassocMode.mode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_DIAG_READ: + { + A_UINT32 addr, data; + get_user(addr, (unsigned int *)userdata); + if (ar6000_ReadRegDiag(ar->arHifDevice, &addr, &data) != A_OK) { + ret = -EIO; + } + put_user(data, (unsigned int *)userdata + 1); + break; + } + case AR6000_XIOCTL_DIAG_WRITE: + { + A_UINT32 addr, data; + get_user(addr, (unsigned int *)userdata); + get_user(data, (unsigned int *)userdata + 1); + if (ar6000_WriteRegDiag(ar->arHifDevice, &addr, &data) != A_OK) { + ret = -EIO; + } + break; + } + case AR6000_XIOCTL_WMI_SET_KEEPALIVE: + { + WMI_SET_KEEPALIVE_CMD setKeepAlive; + if (ar->arWmiReady == FALSE) { + return -EIO; + } else if (copy_from_user(&setKeepAlive, userdata, + sizeof(setKeepAlive))){ + ret = -EFAULT; + } else { + if (wmi_set_keepalive_cmd(ar->arWmi, setKeepAlive.keepaliveInterval) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_GET_KEEPALIVE: + { + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + WMI_GET_KEEPALIVE_CMD getKeepAlive; + int ret = 0; + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (copy_from_user(&getKeepAlive, userdata,sizeof(getKeepAlive))) { + ret = -EFAULT; + } else { + getKeepAlive.keepaliveInterval = wmi_get_keepalive_cmd(ar->arWmi); + ar->arKeepaliveConfigured = 0xFF; + if (wmi_get_keepalive_configured(ar->arWmi) != A_OK){ + up(&ar->arSem); + return -EIO; + } + wait_event_interruptible_timeout(arEvent, ar->arKeepaliveConfigured != 0xFF, wmitimeout * HZ); + if (signal_pending(current)) { + ret = -EINTR; + } + + if (!ret) { + getKeepAlive.configured = ar->arKeepaliveConfigured; + } + if (copy_to_user(userdata, &getKeepAlive, sizeof(getKeepAlive))) { + ret = -EFAULT; + } + up(&ar->arSem); + } + break; + } + case AR6000_XIOCTL_WMI_SET_APPIE: + { + WMI_SET_APPIE_CMD appIEcmd; + A_UINT8 appIeInfo[IEEE80211_APPIE_FRAME_MAX_LEN]; + A_UINT32 fType,ieLen; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + get_user(fType, (A_UINT32 *)userdata); + appIEcmd.mgmtFrmType = fType; + if (appIEcmd.mgmtFrmType >= IEEE80211_APPIE_NUM_OF_FRAME) { + ret = -EIO; + } else { + get_user(ieLen, (A_UINT32 *)(userdata + 4)); + appIEcmd.ieLen = ieLen; + if (appIEcmd.ieLen > IEEE80211_APPIE_FRAME_MAX_LEN) { + ret = -EIO; + break; + } + if (copy_from_user(appIeInfo, userdata + 8, appIEcmd.ieLen)) { + ret = -EFAULT; + } else { + if (wmi_set_appie_cmd(ar->arWmi, appIEcmd.mgmtFrmType, + appIEcmd.ieLen, appIeInfo) != A_OK) + { + ret = -EIO; + } + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER: + { + WMI_BSS_FILTER_CMD cmd; + A_UINT32 filterType; + + if (copy_from_user(&filterType, userdata, sizeof(A_UINT32))) + { + return -EFAULT; + } + if (filterType & (IEEE80211_FILTER_TYPE_BEACON | + IEEE80211_FILTER_TYPE_PROBE_RESP)) + { + cmd.bssFilter = ALL_BSS_FILTER; + } else { + cmd.bssFilter = NONE_BSS_FILTER; + } + if (wmi_bssfilter_cmd(ar->arWmi, cmd.bssFilter, 0) != A_OK) { + ret = -EIO; + } else { + ar->arUserBssFilter = cmd.bssFilter; + } + + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arMgmtFilter = filterType; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + break; + } + case AR6000_XIOCTL_WMI_SET_WSC_STATUS: + { + A_UINT32 wsc_status; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } else if (copy_from_user(&wsc_status, userdata, sizeof(A_UINT32))) + { + return -EFAULT; + } + if (wmi_set_wsc_status_cmd(ar->arWmi, wsc_status) != A_OK) { + ret = -EIO; + } + break; + } + case AR6000_XIOCTL_BMI_ROMPATCH_INSTALL: + { + A_UINT32 ROM_addr; + A_UINT32 RAM_addr; + A_UINT32 nbytes; + A_UINT32 do_activate; + A_UINT32 rompatch_id; + + get_user(ROM_addr, (A_UINT32 *)userdata); + get_user(RAM_addr, (A_UINT32 *)userdata + 1); + get_user(nbytes, (A_UINT32 *)userdata + 2); + get_user(do_activate, (A_UINT32 *)userdata + 3); + AR_DEBUG_PRINTF("Install rompatch from ROM: 0x%x to RAM: 0x%x length: %d\n", + ROM_addr, RAM_addr, nbytes); + ret = BMIrompatchInstall(hifDevice, ROM_addr, RAM_addr, + nbytes, do_activate, &rompatch_id); + if (ret == A_OK) { + put_user(rompatch_id, (unsigned int *)rq->ifr_data); /* return value */ + } + break; + } + + case AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL: + { + A_UINT32 rompatch_id; + + get_user(rompatch_id, (A_UINT32 *)userdata); + AR_DEBUG_PRINTF("UNinstall rompatch_id %d\n", rompatch_id); + ret = BMIrompatchUninstall(hifDevice, rompatch_id); + break; + } + + case AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE: + case AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE: + { + A_UINT32 rompatch_count; + + get_user(rompatch_count, (A_UINT32 *)userdata); + AR_DEBUG_PRINTF("Change rompatch activation count=%d\n", rompatch_count); + length = sizeof(A_UINT32) * rompatch_count; + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + if (copy_from_user(buffer, &userdata[sizeof(rompatch_count)], length)) + { + ret = -EFAULT; + } else { + if (cmd == AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE) { + ret = BMIrompatchActivate(hifDevice, rompatch_count, (A_UINT32 *)buffer); + } else { + ret = BMIrompatchDeactivate(hifDevice, rompatch_count, (A_UINT32 *)buffer); + } + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + + break; + } + + case AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE: + { + WMI_SET_HOST_SLEEP_MODE_CMD setHostSleepMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setHostSleepMode, userdata, + sizeof(setHostSleepMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_host_sleep_mode_cmd(ar->arWmi, + &setHostSleepMode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_WOW_MODE: + { + WMI_SET_WOW_MODE_CMD setWowMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setWowMode, userdata, + sizeof(setWowMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_wow_mode_cmd(ar->arWmi, + &setWowMode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_GET_WOW_LIST: + { + WMI_GET_WOW_LIST_CMD getWowList; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&getWowList, userdata, + sizeof(getWowList))) + { + ret = -EFAULT; + } else { + if (wmi_get_wow_list_cmd(ar->arWmi, + &getWowList) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_ADD_WOW_PATTERN: + { +#define WOW_PATTERN_SIZE 64 +#define WOW_MASK_SIZE 64 + + WMI_ADD_WOW_PATTERN_CMD cmd; + A_UINT8 mask_data[WOW_PATTERN_SIZE]={0}; + A_UINT8 pattern_data[WOW_PATTERN_SIZE]={0}; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + + if(copy_from_user(&cmd, userdata, + sizeof(WMI_ADD_WOW_PATTERN_CMD))) + return -EFAULT; + if (copy_from_user(pattern_data, + userdata + 3, + cmd.filter_size)){ + ret = -EFAULT; + break; + } + if (copy_from_user(mask_data, + (userdata + 3 + cmd.filter_size), + cmd.filter_size)){ + ret = -EFAULT; + break; + } else { + if (wmi_add_wow_pattern_cmd(ar->arWmi, + &cmd, pattern_data, mask_data, cmd.filter_size) != A_OK){ + ret = -EIO; + } + } + } +#undef WOW_PATTERN_SIZE +#undef WOW_MASK_SIZE + break; + } + case AR6000_XIOCTL_WMI_DEL_WOW_PATTERN: + { + WMI_DEL_WOW_PATTERN_CMD delWowPattern; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&delWowPattern, userdata, + sizeof(delWowPattern))) + { + ret = -EFAULT; + } else { + if (wmi_del_wow_pattern_cmd(ar->arWmi, + &delWowPattern) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE: + if (ar->arHtcTarget != NULL) { + HTCDumpCreditStates(ar->arHtcTarget); + } + break; + case AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE: + if (ar->arHtcTarget != NULL) { + struct ar6000_traffic_activity_change data; + + if (copy_from_user(&data, userdata, sizeof(data))) + { + return -EFAULT; + } + /* note, this is used for testing (mbox ping testing), indicate activity + * change using the stream ID as the traffic class */ + ar6000_indicate_tx_activity(ar, + (A_UINT8)data.StreamID, + data.Active ? TRUE : FALSE); + } + break; + case AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&connectCtrlFlags, userdata, + sizeof(connectCtrlFlags))) + { + ret = -EFAULT; + } else { + ar->arConnectCtrlFlags = connectCtrlFlags; + } + break; + case AR6000_XIOCTL_WMI_SET_AKMP_PARAMS: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&akmpParams, userdata, + sizeof(WMI_SET_AKMP_PARAMS_CMD))) + { + ret = -EFAULT; + } else { + if (wmi_set_akmp_params_cmd(ar->arWmi, &akmpParams) != A_OK) { + ret = -EIO; + } + } + break; + case AR6000_XIOCTL_WMI_SET_PMKID_LIST: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + if (copy_from_user(&pmkidInfo.numPMKID, userdata, + sizeof(pmkidInfo.numPMKID))) + { + ret = -EFAULT; + break; + } + if (copy_from_user(&pmkidInfo.pmkidList, + userdata + sizeof(pmkidInfo.numPMKID), + pmkidInfo.numPMKID * sizeof(WMI_PMKID))) + { + ret = -EFAULT; + break; + } + if (wmi_set_pmkid_list_cmd(ar->arWmi, &pmkidInfo) != A_OK) { + ret = -EIO; + } + } + break; + case AR6000_XIOCTL_WMI_GET_PMKID_LIST: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + if (wmi_get_pmkid_list_cmd(ar->arWmi) != A_OK) { + ret = -EIO; + } + } + break; + case AR6000_XIOCTL_WMI_ABORT_SCAN: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } + ret = wmi_abort_scan_cmd(ar->arWmi); + break; + case AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT: + { + WMI_SET_TARGET_EVENT_REPORT_CMD evtCfgCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } + if (copy_from_user(&evtCfgCmd, userdata, + sizeof(evtCfgCmd))) { + ret = -EFAULT; + break; + } + ret = wmi_set_target_event_report_cmd(ar->arWmi, &evtCfgCmd); + break; + } + case AR6000_XIOCTL_WMI_SET_MCAST_FILTER: + { + WMI_SET_MCAST_FILTER_CMD cmd; + if (ar->arWmiReady == FALSE) { + return -EIO; + } else if (copy_from_user(&cmd, userdata, + sizeof(cmd))){ + ret = -EFAULT; + } else { + if (wmi_set_mcast_filter_cmd(ar->arWmi, cmd.multicast_mac[0], + cmd.multicast_mac[1], + cmd.multicast_mac[2], + cmd.multicast_mac[3]) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_DEL_MCAST_FILTER: + { + WMI_SET_MCAST_FILTER_CMD cmd; + if (ar->arWmiReady == FALSE) { + return -EIO; + } else if (copy_from_user(&cmd, userdata, sizeof(cmd))){ + ret = -EFAULT; + } else { + if (wmi_del_mcast_filter_cmd(ar->arWmi, cmd.multicast_mac[0], + cmd.multicast_mac[1], + cmd.multicast_mac[2], + cmd.multicast_mac[3]) != A_OK) { + ret = -EIO; + } + } + break; + } + default: + ret = -EOPNOTSUPP; + } + return ret; +} + diff -urN linux-2.6.26/drivers/net/wireless/ar6000/netbuf.c linux-2.6.26-lab126/drivers/net/wireless/ar6000/netbuf.c --- linux-2.6.26/drivers/net/wireless/ar6000/netbuf.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/netbuf.c 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,229 @@ + +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ +#include +#include +#include +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "htc_packet.h" + +#define AR6000_DATA_OFFSET 64 + +void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt) +{ + skb_queue_tail((struct sk_buff_head *) q, (struct sk_buff *) pkt); +} + +void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt) +{ + skb_queue_head((struct sk_buff_head *) q, (struct sk_buff *) pkt); +} + +void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q) +{ + return((void *) skb_dequeue((struct sk_buff_head *) q)); +} + +int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q) +{ + return(skb_queue_len((struct sk_buff_head *) q)); +} + +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q) +{ + return(skb_queue_empty((struct sk_buff_head *) q)); +} + +void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q) +{ + skb_queue_head_init((struct sk_buff_head *) q); +} + +void * +a_netbuf_alloc(int size) +{ + struct sk_buff *skb; + skb = dev_alloc_skb(AR6000_DATA_OFFSET + sizeof(HTC_PACKET) + size); + skb_reserve(skb, AR6000_DATA_OFFSET + sizeof(HTC_PACKET)); + return ((void *)skb); +} + +/* + * Allocate an SKB w.o. any encapsulation requirement. + */ +void * +a_netbuf_alloc_raw(int size) +{ + struct sk_buff *skb; + + skb = dev_alloc_skb(size); + + return ((void *)skb); +} + +void +a_netbuf_free(void *bufPtr) +{ + struct sk_buff *skb = (struct sk_buff *)bufPtr; + + dev_kfree_skb(skb); +} + +A_UINT32 +a_netbuf_to_len(void *bufPtr) +{ + return (((struct sk_buff *)bufPtr)->len); +} + +void * +a_netbuf_to_data(void *bufPtr) +{ + return (((struct sk_buff *)bufPtr)->data); +} + +/* + * Add len # of bytes to the beginning of the network buffer + * pointed to by bufPtr + */ +A_STATUS +a_netbuf_push(void *bufPtr, A_INT32 len) +{ + skb_push((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Add len # of bytes to the beginning of the network buffer + * pointed to by bufPtr and also fill with data + */ +A_STATUS +a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len) +{ + skb_push((struct sk_buff *) bufPtr, len); + A_MEMCPY(((struct sk_buff *)bufPtr)->data, srcPtr, len); + + return A_OK; +} + +/* + * Add len # of bytes to the end of the network buffer + * pointed to by bufPtr + */ +A_STATUS +a_netbuf_put(void *bufPtr, A_INT32 len) +{ + skb_put((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Add len # of bytes to the end of the network buffer + * pointed to by bufPtr and also fill with data + */ +A_STATUS +a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len) +{ + char *start = ((struct sk_buff *)bufPtr)->data + + ((struct sk_buff *)bufPtr)->len; + skb_put((struct sk_buff *)bufPtr, len); + A_MEMCPY(start, srcPtr, len); + + return A_OK; +} + + +/* + * Trim the network buffer pointed to by bufPtr to len # of bytes + */ +A_STATUS +a_netbuf_setlen(void *bufPtr, A_INT32 len) +{ + skb_trim((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Chop of len # of bytes from the end of the buffer. + */ +A_STATUS +a_netbuf_trim(void *bufPtr, A_INT32 len) +{ + skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len); + + return A_OK; +} + +/* + * Chop of len # of bytes from the end of the buffer and return the data. + */ +A_STATUS +a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len) +{ + char *start = ((struct sk_buff *)bufPtr)->data + + (((struct sk_buff *)bufPtr)->len - len); + + A_MEMCPY(dstPtr, start, len); + skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len); + + return A_OK; +} + + +/* + * Returns the number of bytes available to a a_netbuf_push() + */ +A_INT32 +a_netbuf_headroom(void *bufPtr) +{ + return (skb_headroom((struct sk_buff *)bufPtr)); +} + +/* + * Removes specified number of bytes from the beginning of the buffer + */ +A_STATUS +a_netbuf_pull(void *bufPtr, A_INT32 len) +{ + skb_pull((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Removes specified number of bytes from the beginning of the buffer + * and return the data + */ +A_STATUS +a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len) +{ + A_MEMCPY(dstPtr, ((struct sk_buff *)bufPtr)->data, len); + skb_pull((struct sk_buff *)bufPtr, len); + + return A_OK; +} + diff -urN linux-2.6.26/drivers/net/wireless/ar6000/os/linux/include/ar6000_drv.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/os/linux/include/ar6000_drv.h --- linux-2.6.26/drivers/net/wireless/ar6000/os/linux/include/ar6000_drv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/os/linux/include/ar6000_drv.h 2010-08-10 04:16:45.000000000 -0400 @@ -0,0 +1,377 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _AR6000_H_ +#define _AR6000_H_ + +#include + + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,17) +#include +#else +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "a_types.h" +#include "a_osapi.h" +#include "htc_api.h" +#include "wmi.h" +#include "a_drv.h" +#include "bmi.h" +#include +#include +#include +#include +#include "gpio_api.h" +#include "gpio.h" +#include +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +#include +#else +#include +#include +#endif +#include "ar6000_api.h" +#ifdef CONFIG_HOST_TCMD_SUPPORT +#include +#endif + +#include "targaddrs.h" +#include "dbglog_api.h" +#include "ar6000_diag.h" +#include "common_drv.h" +#include "roaming.h" + +#ifndef __dev_put +#define __dev_put(dev) dev_put(dev) +#endif + + +#ifdef USER_KEYS + +#define USER_SAVEDKEYS_STAT_INIT 0 +#define USER_SAVEDKEYS_STAT_RUN 1 + +// TODO this needs to move into the AR_SOFTC struct +struct USER_SAVEDKEYS { + struct ieee80211req_key ucast_ik; + struct ieee80211req_key bcast_ik; + CRYPTO_TYPE keyType; + A_BOOL keyOk; +}; +#endif + +#define DBG_INFO 0x00000001 +#define DBG_ERROR 0x00000002 +#define DBG_WARNING 0x00000004 +#define DBG_SDIO 0x00000008 +#define DBG_HIF 0x00000010 +#define DBG_HTC 0x00000020 +#define DBG_WMI 0x00000040 +#define DBG_WMI2 0x00000080 +#define DBG_DRIVER 0x00000100 + +#define DBG_DEFAULTS (DBG_ERROR|DBG_WARNING) + + +#ifdef DEBUG +#define AR_DEBUG_PRINTF(args...) if (debugdriver) A_PRINTF(args); +#define AR_DEBUG2_PRINTF(args...) if (debugdriver >= 2) A_PRINTF(args); +extern int debugdriver; +#else +#define AR_DEBUG_PRINTF(args...) +#define AR_DEBUG2_PRINTF(args...) +#endif + +A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); +A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAX_AR6000 1 +#define AR6000_MAX_RX_BUFFERS 16 +#define AR6000_BUFFER_SIZE 1664 +#define AR6000_TX_TIMEOUT 10 +#define AR6000_ETH_ADDR_LEN 6 +#define AR6000_MAX_ENDPOINTS 4 +#define MAX_NODE_NUM 15 +#define MAX_COOKIE_NUM 150 +#define AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT 1 +#define AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT 1 + +enum { + DRV_HB_CHALLENGE = 0, + APP_HB_CHALLENGE +}; + +/* HTC RAW streams */ +typedef enum _HTC_RAW_STREAM_ID { + HTC_RAW_STREAM_NOT_MAPPED = -1, + HTC_RAW_STREAM_0 = 0, + HTC_RAW_STREAM_1 = 1, + HTC_RAW_STREAM_2 = 2, + HTC_RAW_STREAM_3 = 3, + HTC_RAW_STREAM_NUM_MAX +} HTC_RAW_STREAM_ID; + +#define RAW_HTC_READ_BUFFERS_NUM 4 +#define RAW_HTC_WRITE_BUFFERS_NUM 4 + +typedef struct { + int currPtr; + int length; + unsigned char data[AR6000_BUFFER_SIZE]; + HTC_PACKET HTCPacket; +} raw_htc_buffer; + +#ifdef CONFIG_HOST_TCMD_SUPPORT +/* + * add TCMD_MODE besides wmi and bypasswmi + * in TCMD_MODE, only few TCMD releated wmi commands + * counld be hanlder + */ +enum { + AR6000_WMI_MODE = 0, + AR6000_BYPASS_MODE, + AR6000_TCMD_MODE, + AR6000_WLAN_MODE +}; +#endif /* CONFIG_HOST_TCMD_SUPPORT */ + +struct ar_wep_key { + A_UINT8 arKeyIndex; + A_UINT8 arKeyLen; + A_UINT8 arKey[64]; +} ; + +struct ar_node_mapping { + A_UINT8 macAddress[6]; + A_UINT8 epId; + A_UINT8 txPending; +}; + +struct ar_cookie { + A_UINT32 arc_bp[2]; /* Must be first field */ + HTC_PACKET HtcPkt; /* HTC packet wrapper */ + struct ar_cookie *arc_list_next; +}; + +struct ar_hb_chlng_resp { + A_TIMER timer; + A_UINT32 frequency; + A_UINT32 seqNum; + A_BOOL outstanding; + A_UINT8 missCnt; + A_UINT8 missThres; +}; + +typedef struct ar6_softc { + struct net_device *arNetDev; /* net_device pointer */ + void *arWmi; + int arTxPending[ENDPOINT_MAX]; + int arTotalTxDataPending; + A_UINT8 arNumDataEndPts; + A_BOOL arWmiEnabled; + A_BOOL arWmiReady; + A_BOOL arConnected; + HTC_HANDLE arHtcTarget; + void *arHifDevice; + spinlock_t arLock; + struct compat_semaphore arSem; + int arRxBuffers[ENDPOINT_MAX]; + int arSsidLen; + u_char arSsid[32]; + A_UINT8 arNetworkType; + A_UINT8 arDot11AuthMode; + A_UINT8 arAuthMode; + A_UINT8 arPairwiseCrypto; + A_UINT8 arPairwiseCryptoLen; + A_UINT8 arGroupCrypto; + A_UINT8 arGroupCryptoLen; + A_UINT8 arDefTxKeyIndex; + struct ar_wep_key arWepKeyList[WMI_MAX_KEY_INDEX + 1]; + A_UINT8 arBssid[6]; + A_UINT8 arReqBssid[6]; + A_UINT16 arChannelHint; + A_UINT16 arBssChannel; + A_UINT16 arListenInterval; + struct ar6000_version arVersion; + A_UINT32 arTargetType; + A_INT8 arRssi; + A_UINT8 arTxPwr; + A_BOOL arTxPwrSet; + A_INT32 arBitRate; + struct net_device_stats arNetStats; + struct iw_statistics arIwStats; + A_INT8 arNumChannels; + A_UINT16 arChannelList[32]; + A_UINT32 arRegCode; + A_BOOL statsUpdatePending; + TARGET_STATS arTargetStats; + A_INT8 arMaxRetries; + A_UINT8 arPhyCapability; +#ifdef CONFIG_HOST_TCMD_SUPPORT + A_UINT8 tcmdRxReport; + A_UINT32 tcmdRxTotalPkt; + A_INT32 tcmdRxRssi; + A_UINT32 tcmdPm; + A_UINT32 arTargetMode; +#endif + AR6000_WLAN_STATE arWlanState; + struct ar_node_mapping arNodeMap[MAX_NODE_NUM]; + A_UINT8 arIbssPsEnable; + A_UINT8 arNodeNum; + A_UINT8 arNexEpId; + struct ar_cookie *arCookieList; + A_UINT16 arRateMask; + A_UINT8 arSkipScan; + A_UINT16 arBeaconInterval; + A_BOOL arConnectPending; + A_BOOL arWmmEnabled; + struct ar_hb_chlng_resp arHBChallengeResp; + A_UINT8 arKeepaliveConfigured; + A_UINT32 arMgmtFilter; + HTC_ENDPOINT_ID arAc2EpMapping[WMM_NUM_AC]; + A_BOOL arAcStreamActive[WMM_NUM_AC]; + A_UINT8 arAcStreamPriMap[WMM_NUM_AC]; + A_UINT8 arHiAcStreamActivePri; + A_UINT8 arEp2AcMapping[ENDPOINT_MAX]; + HTC_ENDPOINT_ID arControlEp; +#ifdef HTC_RAW_INTERFACE + HTC_ENDPOINT_ID arRaw2EpMapping[HTC_RAW_STREAM_NUM_MAX]; + HTC_RAW_STREAM_ID arEp2RawMapping[ENDPOINT_MAX]; + struct compat_semaphore raw_htc_read_sem[HTC_RAW_STREAM_NUM_MAX]; + struct compat_semaphore raw_htc_write_sem[HTC_RAW_STREAM_NUM_MAX]; + wait_queue_head_t raw_htc_read_queue[HTC_RAW_STREAM_NUM_MAX]; + wait_queue_head_t raw_htc_write_queue[HTC_RAW_STREAM_NUM_MAX]; + raw_htc_buffer raw_htc_read_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_READ_BUFFERS_NUM]; + raw_htc_buffer raw_htc_write_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_WRITE_BUFFERS_NUM]; + A_BOOL write_buffer_available[HTC_RAW_STREAM_NUM_MAX]; + A_BOOL read_buffer_available[HTC_RAW_STREAM_NUM_MAX]; +#endif + A_BOOL arNetQueueStopped; + A_BOOL arRawIfInit; + int arDeviceIndex; + COMMON_CREDIT_STATE_INFO arCreditStateInfo; + A_BOOL arWMIControlEpFull; + A_BOOL dbgLogFetchInProgress; + A_UCHAR log_buffer[DBGLOG_HOST_LOG_BUFFER_SIZE]; + A_UINT32 log_cnt; + A_UINT32 dbglog_init_done; + A_UINT32 arConnectCtrlFlags; +#ifdef USER_KEYS + A_INT32 user_savedkeys_stat; + A_UINT32 user_key_ctrl; + struct USER_SAVEDKEYS user_saved_keys; +#endif + USER_RSSI_THOLD rssi_map[12]; + A_UINT8 arUserBssFilter; +} AR_SOFTC_T; + + +#define arAc2EndpointID(ar,ac) (ar)->arAc2EpMapping[(ac)] +#define arSetAc2EndpointIDMap(ar,ac,ep) \ +{ (ar)->arAc2EpMapping[(ac)] = (ep); \ + (ar)->arEp2AcMapping[(ep)] = (ac); } +#define arEndpoint2Ac(ar,ep) (ar)->arEp2AcMapping[(ep)] + +#define arRawIfEnabled(ar) (ar)->arRawIfInit +#define arRawStream2EndpointID(ar,raw) (ar)->arRaw2EpMapping[(raw)] +#define arSetRawStream2EndpointIDMap(ar,raw,ep) \ +{ (ar)->arRaw2EpMapping[(raw)] = (ep); \ + (ar)->arEp2RawMapping[(ep)] = (raw); } +#define arEndpoint2RawStreamID(ar,ep) (ar)->arEp2RawMapping[(ep)] + +struct ar_giwscan_param { + char *current_ev; + char *end_buf; + A_BOOL firstPass; +}; + +#define AR6000_STAT_INC(ar, stat) (ar->arNetStats.stat++) + +#define AR6000_SPIN_LOCK(lock, param) do { \ + if (irqs_disabled()) { \ + AR_DEBUG_PRINTF("IRQs disabled:AR6000_LOCK\n"); \ + } \ + spin_lock_bh(lock); \ +} while (0) + +#define AR6000_SPIN_UNLOCK(lock, param) do { \ + if (irqs_disabled()) { \ + AR_DEBUG_PRINTF("IRQs disabled: AR6000_UNLOCK\n"); \ + } \ + spin_unlock_bh(lock); \ +} while (0) + +int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); +int ar6000_ioctl_dispatcher(struct net_device *dev, struct ifreq *rq, int cmd); +void ar6000_ioctl_iwsetup(struct iw_handler_def *def); +void ar6000_gpio_init(void); +void ar6000_init_profile_info(AR_SOFTC_T *ar); +void ar6000_install_static_wep_keys(AR_SOFTC_T *ar); +int ar6000_init(struct net_device *dev); +int ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar); + +#ifdef HTC_RAW_INTERFACE + +#ifndef __user +#define __user +#endif + +int ar6000_htc_raw_open(AR_SOFTC_T *ar); +int ar6000_htc_raw_close(AR_SOFTC_T *ar); +ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar, + HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t count); +ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar, + HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t count); + +#endif /* HTC_RAW_INTERFACE */ + +#ifdef __cplusplus +} +#endif + +#endif /* _AR6000_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/os/linux/include/ar6xapi_linux.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/os/linux/include/ar6xapi_linux.h --- linux-2.6.26/drivers/net/wireless/ar6000/os/linux/include/ar6xapi_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/os/linux/include/ar6xapi_linux.h 2010-08-10 04:16:45.000000000 -0400 @@ -0,0 +1,143 @@ +#ifndef _AR6XAPI_LINUX_H +#define _AR6XAPI_LINUX_H +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifdef __cplusplus +extern "C" { +#endif + +struct ar6_softc; + +void ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap, + A_UINT32 ver); +A_STATUS ar6000_control_tx(void *devt, void *osbuf, HTC_ENDPOINT_ID eid); +void ar6000_connect_event(struct ar6_softc *ar, A_UINT16 channel, + A_UINT8 *bssid, A_UINT16 listenInterval, + A_UINT16 beaconInterval, NETWORK_TYPE networkType, + A_UINT8 beaconIeLen, A_UINT8 assocReqLen, + A_UINT8 assocRespLen,A_UINT8 *assocInfo); +void ar6000_disconnect_event(struct ar6_softc *ar, A_UINT8 reason, + A_UINT8 *bssid, A_UINT8 assocRespLen, + A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus); +void ar6000_tkip_micerr_event(struct ar6_softc *ar, A_UINT8 keyid, + A_BOOL ismcast); +void ar6000_bitrate_rx(void *devt, A_INT32 rateKbps); +void ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList); +void ar6000_regDomain_event(struct ar6_softc *ar, A_UINT32 regCode); +void ar6000_txPwr_rx(void *devt, A_UINT8 txPwr); +void ar6000_keepalive_rx(void *devt, A_UINT8 configured); +void ar6000_neighborReport_event(struct ar6_softc *ar, int numAps, + WMI_NEIGHBOR_INFO *info); +void ar6000_set_numdataendpts(struct ar6_softc *ar, A_UINT32 num); +void ar6000_scanComplete_event(struct ar6_softc *ar, A_STATUS status); +void ar6000_targetStats_event(struct ar6_softc *ar, WMI_TARGET_STATS *pStats); +void ar6000_rssiThreshold_event(struct ar6_softc *ar, + WMI_RSSI_THRESHOLD_VAL newThreshold, + A_INT16 rssi); +void ar6000_reportError_event(struct ar6_softc *, WMI_TARGET_ERROR_VAL errorVal); +void ar6000_cac_event(struct ar6_softc *ar, A_UINT8 ac, A_UINT8 cac_indication, + A_UINT8 statusCode, A_UINT8 *tspecSuggestion); +void ar6000_channel_change_event(struct ar6_softc *ar, A_UINT16 oldChannel, A_UINT16 newChannel); +void ar6000_hbChallengeResp_event(struct ar6_softc *, A_UINT32 cookie, A_UINT32 source); +void +ar6000_roam_tbl_event(struct ar6_softc *ar, WMI_TARGET_ROAM_TBL *pTbl); + +void +ar6000_roam_data_event(struct ar6_softc *ar, WMI_TARGET_ROAM_DATA *p); + +void +ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters, + WMI_GET_WOW_LIST_REPLY *wow_reply); + +void ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID, + WMI_PMKID *pmkidList, A_UINT8 *bssidList); + +void ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values); +void ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value); +void ar6000_gpio_ack_rx(void); + +void ar6000_dbglog_init_done(struct ar6_softc *ar); + +#ifdef SEND_EVENT_TO_APP +void ar6000_send_event_to_app(struct ar6_softc *ar, A_UINT16 eventId, A_UINT8 *datap, int len); +#endif + +#ifdef CONFIG_HOST_TCMD_SUPPORT +void ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len); +#endif + +void ar6000_tx_retry_err_event(void *devt); + +void ar6000_snrThresholdEvent_rx(void *devt, + WMI_SNR_THRESHOLD_VAL newThreshold, + A_UINT8 snr); + +void ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL range, A_UINT8 lqVal); + + +void ar6000_ratemask_rx(void *devt, A_UINT16 ratemask); + +A_STATUS ar6000_get_driver_cfg(struct net_device *dev, + A_UINT16 cfgParam, + void *result); +void ar6000_bssInfo_event_rx(struct ar6_softc *ar, A_UINT8 *data, int len); + +void ar6000_dbglog_event(struct ar6_softc *ar, A_UINT32 dropped, + A_INT8 *buffer, A_UINT32 length); + +int ar6000_dbglog_get_debug_logs(struct ar6_softc *ar); + +void ar6000_indicate_tx_activity(void *devt, A_UINT8 trafficClass, A_BOOL Active); +HTC_ENDPOINT_ID ar6000_ac2_endpoint_id ( void * devt, A_UINT8 ac); +A_UINT8 ar6000_endpoint_id2_ac (void * devt, HTC_ENDPOINT_ID ep ); + +void ar6000_dset_open_req(void *devt, + A_UINT32 id, + A_UINT32 targ_handle, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); +void ar6000_dset_close(void *devt, A_UINT32 access_cookie); +void ar6000_dset_data_req(void *devt, + A_UINT32 access_cookie, + A_UINT32 offset, + A_UINT32 length, + A_UINT32 targ_buf, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); + + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +void prof_count_rx(unsigned int addr, unsigned int count); +#endif + +A_UINT32 ar6000_getnodeAge (void); + +A_UINT32 ar6000_getclkfreq (void); + + +#ifdef __cplusplus +} +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ar6000/os/linux/include/athdrv_linux.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/os/linux/include/athdrv_linux.h --- linux-2.6.26/drivers/net/wireless/ar6000/os/linux/include/athdrv_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/os/linux/include/athdrv_linux.h 2010-08-10 04:16:45.000000000 -0400 @@ -0,0 +1,1053 @@ +/* + * Copyright (c) 2004-2006 Atheros Communications Inc. + * All rights reserved. + * + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _ATHDRV_LINUX_H +#define _ATHDRV_LINUX_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* + * There are two types of ioctl's here: Standard ioctls and + * eXtended ioctls. All extended ioctls (XIOCTL) are multiplexed + * off of the single ioctl command, AR6000_IOCTL_EXTENDED. The + * arguments for every XIOCTL starts with a 32-bit command word + * that is used to select which extended ioctl is in use. After + * the command word are command-specific arguments. + */ + +/* Linux standard Wireless Extensions, private ioctl interfaces */ +#define IEEE80211_IOCTL_SETPARAM (SIOCIWFIRSTPRIV+0) +#define IEEE80211_IOCTL_GETPARAM (SIOCIWFIRSTPRIV+1) +#define IEEE80211_IOCTL_SETKEY (SIOCIWFIRSTPRIV+2) +#define IEEE80211_IOCTL_SETWMMPARAMS (SIOCIWFIRSTPRIV+3) +#define IEEE80211_IOCTL_DELKEY (SIOCIWFIRSTPRIV+4) +#define IEEE80211_IOCTL_GETWMMPARAMS (SIOCIWFIRSTPRIV+5) +#define IEEE80211_IOCTL_SETMLME (SIOCIWFIRSTPRIV+6) +#define IEEE80211_IOCTL_SETOPTIE (SIOCIWFIRSTPRIV+6) +#define IEEE80211_IOCTL_GETOPTIE (SIOCIWFIRSTPRIV+7) +#define IEEE80211_IOCTL_ADDPMKID (SIOCIWFIRSTPRIV+8) +//#define IEEE80211_IOCTL_SETAUTHALG (SIOCIWFIRSTPRIV+10) +#define IEEE80211_IOCTL_LASTONE (SIOCIWFIRSTPRIV+9) + + + +/* ====WMI Ioctls==== */ +/* + * + * Many ioctls simply provide WMI services to application code: + * an application makes such an ioctl call with a set of arguments + * that are packaged into the corresponding WMI message, and sent + * to the Target. + */ + +#define AR6000_IOCTL_WMI_GETREV (SIOCIWFIRSTPRIV+10) +/* + * arguments: + * ar6000_version *revision + */ + +#define AR6000_IOCTL_WMI_SETPWR (SIOCIWFIRSTPRIV+11) +/* + * arguments: + * WMI_POWER_MODE_CMD pwrModeCmd (see include/wmi.h) + * uses: WMI_SET_POWER_MODE_CMDID + */ + +#define AR6000_IOCTL_WMI_SETSCAN (SIOCIWFIRSTPRIV+12) +/* + * arguments: + * WMI_SCAN_PARAMS_CMD scanParams (see include/wmi.h) + * uses: WMI_SET_SCAN_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SETLISTENINT (SIOCIWFIRSTPRIV+13) +/* + * arguments: + * UINT32 listenInterval + * uses: WMI_SET_LISTEN_INT_CMDID + */ + +#define AR6000_IOCTL_WMI_SETBSSFILTER (SIOCIWFIRSTPRIV+14) +/* + * arguments: + * WMI_BSS_FILTER filter (see include/wmi.h) + * uses: WMI_SET_BSS_FILTER_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_CHANNELPARAMS (SIOCIWFIRSTPRIV+16) +/* + * arguments: + * WMI_CHANNEL_PARAMS_CMD chParams + * uses: WMI_SET_CHANNEL_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_PROBEDSSID (SIOCIWFIRSTPRIV+17) +/* + * arguments: + * WMI_PROBED_SSID_CMD probedSsids (see include/wmi.h) + * uses: WMI_SETPROBED_SSID_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_PMPARAMS (SIOCIWFIRSTPRIV+18) +/* + * arguments: + * WMI_POWER_PARAMS_CMD powerParams (see include/wmi.h) + * uses: WMI_SET_POWER_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_BADAP (SIOCIWFIRSTPRIV+19) +/* + * arguments: + * WMI_ADD_BAD_AP_CMD badAPs (see include/wmi.h) + * uses: WMI_ADD_BAD_AP_CMDID + */ + +#define AR6000_IOCTL_WMI_GET_QOS_QUEUE (SIOCIWFIRSTPRIV+20) +/* + * arguments: + * ar6000_queuereq queueRequest (see below) + */ + +#define AR6000_IOCTL_WMI_CREATE_QOS (SIOCIWFIRSTPRIV+21) +/* + * arguments: + * WMI_CREATE_PSTREAM createPstreamCmd (see include/wmi.h) + * uses: WMI_CREATE_PSTREAM_CMDID + */ + +#define AR6000_IOCTL_WMI_DELETE_QOS (SIOCIWFIRSTPRIV+22) +/* + * arguments: + * WMI_DELETE_PSTREAM_CMD deletePstreamCmd (see include/wmi.h) + * uses: WMI_DELETE_PSTREAM_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_SNRTHRESHOLD (SIOCIWFIRSTPRIV+23) +/* + * arguments: + * WMI_SNR_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h) + * uses: WMI_SNR_THRESHOLD_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24) +/* + * arguments: + * WMI_TARGET_ERROR_REPORT_BITMASK errorReportBitMask (see include/wmi.h) + * uses: WMI_TARGET_ERROR_REPORT_BITMASK_CMDID + */ + +#define AR6000_IOCTL_WMI_GET_TARGET_STATS (SIOCIWFIRSTPRIV+25) +/* + * arguments: + * TARGET_STATS *targetStats (see below) + * uses: WMI_GET_STATISTICS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_ASSOC_INFO (SIOCIWFIRSTPRIV+26) +/* + * arguments: + * WMI_SET_ASSOC_INFO_CMD setAssocInfoCmd + * uses: WMI_SET_ASSOC_INFO_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_ACCESS_PARAMS (SIOCIWFIRSTPRIV+27) +/* + * arguments: + * WMI_SET_ACCESS_PARAMS_CMD setAccessParams (see include/wmi.h) + * uses: WMI_SET_ACCESS_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_BMISS_TIME (SIOCIWFIRSTPRIV+28) +/* + * arguments: + * UINT32 beaconMissTime + * uses: WMI_SET_BMISS_TIME_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_DISC_TIMEOUT (SIOCIWFIRSTPRIV+29) +/* + * arguments: + * WMI_DISC_TIMEOUT_CMD disconnectTimeoutCmd (see include/wmi.h) + * uses: WMI_SET_DISC_TIMEOUT_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS (SIOCIWFIRSTPRIV+30) +/* + * arguments: + * WMI_IBSS_PM_CAPS_CMD ibssPowerMgmtCapsCmd + * uses: WMI_SET_IBSS_PM_CAPS_CMDID + */ + +/* + * There is a very small space available for driver-private + * wireless ioctls. In order to circumvent this limitation, + * we multiplex a bunch of ioctls (XIOCTLs) on top of a + * single AR6000_IOCTL_EXTENDED ioctl. + */ +#define AR6000_IOCTL_EXTENDED (SIOCIWFIRSTPRIV+31) + + +/* ====BMI Extended Ioctls==== */ + +#define AR6000_XIOCTL_BMI_DONE 1 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_DONE) + * uses: BMI_DONE + */ + +#define AR6000_XIOCTL_BMI_READ_MEMORY 2 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_READ_MEMORY) + * UINT32 address + * UINT32 length + * } + * char results[length] + * } + * uses: BMI_READ_MEMORY + */ + +#define AR6000_XIOCTL_BMI_WRITE_MEMORY 3 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_MEMORY) + * UINT32 address + * UINT32 length + * char data[length] + * uses: BMI_WRITE_MEMORY + */ + +#define AR6000_XIOCTL_BMI_EXECUTE 4 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_EXECUTE) + * UINT32 TargetAddress + * UINT32 parameter + * uses: BMI_EXECUTE + */ + +#define AR6000_XIOCTL_BMI_SET_APP_START 5 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_SET_APP_START) + * UINT32 TargetAddress + * uses: BMI_SET_APP_START + */ + +#define AR6000_XIOCTL_BMI_READ_SOC_REGISTER 6 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_READ_SOC_REGISTER) + * UINT32 TargetAddress, 32-bit aligned + * } + * UINT32 result + * } + * uses: BMI_READ_SOC_REGISTER + */ + +#define AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER 7 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER) + * UINT32 TargetAddress, 32-bit aligned + * UINT32 newValue + * } + * uses: BMI_WRITE_SOC_REGISTER + */ + +#define AR6000_XIOCTL_BMI_TEST 8 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_TEST) + * UINT32 address + * UINT32 length + * UINT32 count + */ + + + +/* Historical Host-side DataSet support */ +#define AR6000_XIOCTL_UNUSED9 9 +#define AR6000_XIOCTL_UNUSED10 10 +#define AR6000_XIOCTL_UNUSED11 11 + +/* ====Misc Extended Ioctls==== */ + +#define AR6000_XIOCTL_FORCE_TARGET_RESET 12 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_FORCE_TARGET_RESET) + */ + + +#ifdef HTC_RAW_INTERFACE +/* HTC Raw Interface Ioctls */ +#define AR6000_XIOCTL_HTC_RAW_OPEN 13 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_OPEN) + */ + +#define AR6000_XIOCTL_HTC_RAW_CLOSE 14 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_CLOSE) + */ + +#define AR6000_XIOCTL_HTC_RAW_READ 15 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_READ) + * UINT32 mailboxID + * UINT32 length + * } + * results[length] + * } + */ + +#define AR6000_XIOCTL_HTC_RAW_WRITE 16 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_WRITE) + * UINT32 mailboxID + * UINT32 length + * char buffer[length] + */ +#endif /* HTC_RAW_INTERFACE */ + +#define AR6000_XIOCTL_CHECK_TARGET_READY 17 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_CHECK_TARGET_READY) + */ + + + +/* ====GPIO (General Purpose I/O) Extended Ioctls==== */ + +#define AR6000_XIOCTL_GPIO_OUTPUT_SET 18 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_OUTPUT_SET) + * ar6000_gpio_output_set_cmd_s (see below) + * uses: WMIX_GPIO_OUTPUT_SET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_INPUT_GET 19 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_INPUT_GET) + * uses: WMIX_GPIO_INPUT_GET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_REGISTER_SET 20 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_SET) + * ar6000_gpio_register_cmd_s (see below) + * uses: WMIX_GPIO_REGISTER_SET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_REGISTER_GET 21 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_GET) + * ar6000_gpio_register_cmd_s (see below) + * uses: WMIX_GPIO_REGISTER_GET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_INTR_ACK 22 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_ACK) + * ar6000_cpio_intr_ack_cmd_s (see below) + * uses: WMIX_GPIO_INTR_ACK_CMDID + */ + +#define AR6000_XIOCTL_GPIO_INTR_WAIT 23 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_WAIT) + */ + + + +/* ====more wireless commands==== */ + +#define AR6000_XIOCTL_SET_ADHOC_BSSID 24 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_ADHOC_BSSID) + * WMI_SET_ADHOC_BSSID_CMD setAdHocBssidCmd (see include/wmi.h) + */ + +#define AR6000_XIOCTL_SET_OPT_MODE 25 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_OPT_MODE) + * WMI_SET_OPT_MODE_CMD setOptModeCmd (see include/wmi.h) + * uses: WMI_SET_OPT_MODE_CMDID + */ + +#define AR6000_XIOCTL_OPT_SEND_FRAME 26 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_OPT_SEND_FRAME) + * WMI_OPT_TX_FRAME_CMD optTxFrameCmd (see include/wmi.h) + * uses: WMI_OPT_TX_FRAME_CMDID + */ + +#define AR6000_XIOCTL_SET_ADHOC_BEACON_INTVAL 27 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_ADHOC_BEACON_INTVAL) + * WMI_BEACON_INT_CMD beaconIntCmd (see include/wmi.h) + * uses: WMI_SET_BEACON_INT_CMDID + */ + + +#define IEEE80211_IOCTL_SETAUTHALG 28 + + +#define AR6000_XIOCTL_SET_VOICE_PKT_SIZE 29 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_VOICE_PKT_SIZE) + * WMI_SET_VOICE_PKT_SIZE_CMD setVoicePktSizeCmd (see include/wmi.h) + * uses: WMI_SET_VOICE_PKT_SIZE_CMDID + */ + + +#define AR6000_XIOCTL_SET_MAX_SP 30 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_MAX_SP) + * WMI_SET_MAX_SP_LEN_CMD maxSPLen(see include/wmi.h) + * uses: WMI_SET_MAX_SP_LEN_CMDID + */ + +#define AR6000_XIOCTL_WMI_GET_ROAM_TBL 31 + +#define AR6000_XIOCTL_WMI_SET_ROAM_CTRL 32 + +#define AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS 33 + + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS) + * WMI_SET_POWERSAVE_TIMERS_CMD powerSaveTimers(see include/wmi.h) + * WMI_SET_POWERSAVE_TIMERS_CMDID + */ + +#define AR6000_XIOCTRL_WMI_GET_POWER_MODE 34 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTRL_WMI_GET_POWER_MODE) + */ + +#define AR6000_XIOCTRL_WMI_SET_WLAN_STATE 35 +typedef enum { + WLAN_DISABLED, + WLAN_ENABLED +} AR6000_WLAN_STATE; +/* + * arguments: + * enable/disable + */ + +#define AR6000_XIOCTL_WMI_GET_ROAM_DATA 36 + +#define AR6000_XIOCTL_WMI_SETRETRYLIMITS 37 +/* + * arguments: + * WMI_SET_RETRY_LIMITS_CMD ibssSetRetryLimitsCmd + * uses: WMI_SET_RETRY_LIMITS_CMDID + */ + +#ifdef CONFIG_HOST_TCMD_SUPPORT +/* ====extended commands for radio test ==== */ + +#define AR6000_XIOCTL_TCMD_CONT_TX 38 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_TX) + * WMI_TCMD_CONT_TX_CMD contTxCmd (see include/wmi.h) + * uses: WMI_TCMD_CONT_TX_CMDID + */ + +#define AR6000_XIOCTL_TCMD_CONT_RX 39 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_RX) + * WMI_TCMD_CONT_RX_CMD rxCmd (see include/wmi.h) + * uses: WMI_TCMD_CONT_RX_CMDID + */ + +#define AR6000_XIOCTL_TCMD_PM 40 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TCMD_PM) + * WMI_TCMD_PM_CMD pmCmd (see include/wmi.h) + * uses: WMI_TCMD_PM_CMDID + */ + +#endif /* CONFIG_HOST_TCMD_SUPPORT */ + +#define AR6000_XIOCTL_WMI_STARTSCAN 41 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_STARTSCAN) + * UINT8 scanType + * UINT8 scanConnected + * A_BOOL forceFgScan + * uses: WMI_START_SCAN_CMDID + */ + +#define AR6000_XIOCTL_WMI_SETFIXRATES 42 + +#define AR6000_XIOCTL_WMI_GETFIXRATES 43 + + +#define AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD 44 +/* + * arguments: + * WMI_RSSI_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h) + * uses: WMI_RSSI_THRESHOLD_PARAMS_CMDID + */ + +#define AR6000_XIOCTL_WMI_CLR_RSSISNR 45 +/* + * arguments: + * WMI_CLR_RSSISNR_CMD thresholdParams (see include/wmi.h) + * uses: WMI_CLR_RSSISNR_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_LQTHRESHOLD 46 +/* + * arguments: + * WMI_LQ_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h) + * uses: WMI_LQ_THRESHOLD_PARAMS_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_RTS 47 +/* + * arguments: + * WMI_SET_RTS_MODE_CMD (see include/wmi.h) + * uses: WMI_SET_RTS_MODE_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_LPREAMBLE 48 + +#define AR6000_XIOCTL_WMI_SET_AUTHMODE 49 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_AUTHMODE) + * UINT8 mode + * uses: WMI_SET_RECONNECT_AUTH_MODE_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_REASSOCMODE 50 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_WMM) + * UINT8 mode + * uses: WMI_SET_WMM_CMDID + */ +#define AR6000_XIOCTL_WMI_SET_WMM 51 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS) + * UINT32 frequency + * UINT8 threshold + */ +#define AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS 52 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP) + * UINT32 cookie + */ +#define AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP 53 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_GET_RD) + * UINT32 regDomain + */ +#define AR6000_XIOCTL_WMI_GET_RD 54 + +#define AR6000_XIOCTL_DIAG_READ 55 + +#define AR6000_XIOCTL_DIAG_WRITE 56 + +/* + * arguments cmd (AR6000_XIOCTL_SET_TXOP) + * WMI_TXOP_CFG txopEnable + */ +#define AR6000_XIOCTL_WMI_SET_TXOP 57 + +#ifdef USER_KEYS +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_USER_SETKEYS) + * UINT32 keyOpCtrl + * uses AR6000_USER_SETKEYS_INFO + */ +#define AR6000_XIOCTL_USER_SETKEYS 58 +#endif /* USER_KEYS */ + +#define AR6000_XIOCTL_WMI_SET_KEEPALIVE 59 +/* + * arguments: + * UINT8 cmd (AR6000_XIOCTL_WMI_SET_KEEPALIVE) + * UINT8 keepaliveInterval + * uses: WMI_SET_KEEPALIVE_CMDID + */ + +#define AR6000_XIOCTL_WMI_GET_KEEPALIVE 60 +/* + * arguments: + * UINT8 cmd (AR6000_XIOCTL_WMI_GET_KEEPALIVE) + * UINT8 keepaliveInterval + * A_BOOL configured + * uses: WMI_GET_KEEPALIVE_CMDID + */ + +/* ====ROM Patching Extended Ioctls==== */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_INSTALL 61 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_INSTALL) + * UINT32 ROM Address + * UINT32 RAM Address + * UINT32 number of bytes + * UINT32 activate? (0 or 1) + * } + * A_UINT32 resulting rompatch ID + * } + * uses: BMI_ROMPATCH_INSTALL + */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL 62 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL) + * UINT32 rompatch ID + * } + * uses: BMI_ROMPATCH_UNINSTALL + */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE 63 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE) + * UINT32 rompatch count + * UINT32 rompatch IDs[rompatch count] + * } + * uses: BMI_ROMPATCH_ACTIVATE + */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE 64 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE) + * UINT32 rompatch count + * UINT32 rompatch IDs[rompatch count] + * } + * uses: BMI_ROMPATCH_DEACTIVATE + */ + +#define AR6000_XIOCTL_WMI_SET_APPIE 65 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_APPIE) + * UINT32 app_frmtype; + * UINT32 app_buflen; + * UINT8 app_buf[]; + * } + */ +#define AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER 66 +/* + * arguments: + * A_UINT32 filter_type; + */ + +#define AR6000_XIOCTL_DBGLOG_CFG_MODULE 67 + +#define AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS 68 + +#define AR6000_XIOCTL_WMI_SET_WSC_STATUS 70 +/* + * arguments: + * A_UINT32 wsc_status; + * (WSC_REG_INACTIVE or WSC_REG_ACTIVE) + */ + +/* + * arguments: + * struct { + * A_UINT8 streamType; + * A_UINT8 status; + * } + * uses: WMI_SET_BT_STATUS_CMDID + */ +#define AR6000_XIOCTL_WMI_SET_BT_STATUS 71 + +/* + * arguments: + * struct { + * A_UINT8 paramType; + * union { + * A_UINT8 noSCOPkts; + * BT_PARAMS_A2DP a2dpParams; + * BT_COEX_REGS regs; + * }; + * } + * uses: WMI_SET_BT_PARAM_CMDID + */ +#define AR6000_XIOCTL_WMI_SET_BT_PARAMS 72 + +#define AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE 73 +#define AR6000_XIOCTL_WMI_SET_WOW_MODE 74 +#define AR6000_XIOCTL_WMI_GET_WOW_LIST 75 +#define AR6000_XIOCTL_WMI_ADD_WOW_PATTERN 76 +#define AR6000_XIOCTL_WMI_DEL_WOW_PATTERN 77 + + + +#define AR6000_XIOCTL_TARGET_INFO 78 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TARGET_INFO) + * A_UINT32 TargetVersion (returned) + * A_UINT32 TargetType (returned) + * (See also bmi_msg.h target_ver and target_type) + */ + +#define AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE 79 +/* + * arguments: + * none + */ + +#define AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE 80 +/* + * This ioctl is used to emulate traffic activity + * timeouts. Activity/inactivity will trigger the driver + * to re-balance credits. + * + * arguments: + * ar6000_traffic_activity_change + */ + +#define AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS 81 +/* + * This ioctl is used to set the connect control flags + * + * arguments: + * A_UINT32 connectCtrlFlags + */ + +#define AR6000_XIOCTL_WMI_SET_AKMP_PARAMS 82 +/* + * This IOCTL sets any Authentication,Key Management and Protection + * related parameters. This is used along with the information set in + * Connect Command. + * Currently this enables Multiple PMKIDs to an AP. + * + * arguments: + * struct { + * A_UINT32 akmpInfo; + * } + * uses: WMI_SET_AKMP_PARAMS_CMD + */ + +#define AR6000_XIOCTL_WMI_GET_PMKID_LIST 83 + +#define AR6000_XIOCTL_WMI_SET_PMKID_LIST 84 +/* + * This IOCTL is used to set a list of PMKIDs. This list of + * PMKIDs is used in the [Re]AssocReq Frame. This list is used + * only if the MultiPMKID option is enabled via the + * AR6000_XIOCTL_WMI_SET_AKMP_PARAMS IOCTL. + * + * arguments: + * struct { + * A_UINT32 numPMKID; + * WMI_PMKID pmkidList[WMI_MAX_PMKID_CACHE]; + * } + * uses: WMI_SET_PMKIDLIST_CMD + */ + +#define AR6000_XIOCTL_WMI_SET_MCAST_FILTER 85 +#define AR6000_XIOCTL_WMI_DEL_MCAST_FILTER 86 + + +/* Historical DSETPATCH support for INI patches */ +#define AR6000_XIOCTL_UNUSED90 90 + + +/* Support LZ-compressed firmware download */ +#define AR6000_XIOCTL_BMI_LZ_STREAM_START 91 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_LZ_STREAM_START) + * UINT32 address + * uses: BMI_LZ_STREAM_START + */ + +#define AR6000_XIOCTL_BMI_LZ_DATA 92 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_LZ_DATA) + * UINT32 length + * char data[length] + * uses: BMI_LZ_DATA + */ + +#define AR6000_XIOCTL_PROF_CFG 93 +/* + * arguments: + * A_UINT32 period + * A_UINT32 nbins + */ + +#define AR6000_XIOCTL_PROF_ADDR_SET 94 +/* + * arguments: + * A_UINT32 Target address + */ + +#define AR6000_XIOCTL_PROF_START 95 + +#define AR6000_XIOCTL_PROF_STOP 96 + +#define AR6000_XIOCTL_PROF_COUNT_GET 97 + +#define AR6000_XIOCTL_WMI_ABORT_SCAN 98 + +#define AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT 99 + +/* used by AR6000_IOCTL_WMI_GETREV */ +struct ar6000_version { + A_UINT32 host_ver; + A_UINT32 target_ver; + A_UINT32 wlan_ver; +}; + +/* used by AR6000_IOCTL_WMI_GET_QOS_QUEUE */ +struct ar6000_queuereq { + A_UINT8 trafficClass; + A_UINT16 activeTsids; +}; + +/* used by AR6000_IOCTL_WMI_GET_TARGET_STATS */ +typedef struct targetStats_t { + A_UINT64 tx_packets; + A_UINT64 tx_bytes; + A_UINT64 tx_unicast_pkts; + A_UINT64 tx_unicast_bytes; + A_UINT64 tx_multicast_pkts; + A_UINT64 tx_multicast_bytes; + A_UINT64 tx_broadcast_pkts; + A_UINT64 tx_broadcast_bytes; + A_UINT64 tx_rts_success_cnt; + A_UINT64 tx_packet_per_ac[4]; + + A_UINT64 tx_errors; + A_UINT64 tx_failed_cnt; + A_UINT64 tx_retry_cnt; + A_UINT64 tx_mult_retry_cnt; + A_UINT64 tx_rts_fail_cnt; + + A_UINT64 rx_packets; + A_UINT64 rx_bytes; + A_UINT64 rx_unicast_pkts; + A_UINT64 rx_unicast_bytes; + A_UINT64 rx_multicast_pkts; + A_UINT64 rx_multicast_bytes; + A_UINT64 rx_broadcast_pkts; + A_UINT64 rx_broadcast_bytes; + A_UINT64 rx_fragment_pkt; + + A_UINT64 rx_errors; + A_UINT64 rx_crcerr; + A_UINT64 rx_key_cache_miss; + A_UINT64 rx_decrypt_err; + A_UINT64 rx_duplicate_frames; + + A_UINT64 tkip_local_mic_failure; + A_UINT64 tkip_counter_measures_invoked; + A_UINT64 tkip_replays; + A_UINT64 tkip_format_errors; + A_UINT64 ccmp_format_errors; + A_UINT64 ccmp_replays; + + A_UINT64 power_save_failure_cnt; + + A_UINT64 cs_bmiss_cnt; + A_UINT64 cs_lowRssi_cnt; + A_UINT64 cs_connect_cnt; + A_UINT64 cs_disconnect_cnt; + + A_INT32 tx_unicast_rate; + A_INT32 rx_unicast_rate; + + A_UINT32 lq_val; + + A_UINT32 wow_num_pkts_dropped; + A_UINT16 wow_num_events_discarded; + + A_INT16 noise_floor_calibation; + A_INT16 cs_rssi; + A_INT16 cs_aveBeacon_rssi; + A_UINT8 cs_aveBeacon_snr; + A_UINT8 cs_lastRoam_msec; + A_UINT8 cs_snr; + + A_UINT8 wow_num_host_pkt_wakeups; + A_UINT8 wow_num_host_event_wakeups; + +}TARGET_STATS; + +typedef struct targetStats_cmd_t { + TARGET_STATS targetStats; + int clearStats; +} TARGET_STATS_CMD; + +/* used by AR6000_XIOCTL_USER_SETKEYS */ + +/* + * Setting this bit to 1 doesnot initialize the RSC on the firmware + */ +#define AR6000_XIOCTL_USER_SETKEYS_RSC_CTRL 1 +#define AR6000_USER_SETKEYS_RSC_UNCHANGED 0x00000002 + +typedef struct { + A_UINT32 keyOpCtrl; /* Bit Map of Key Mgmt Ctrl Flags */ +} AR6000_USER_SETKEYS_INFO; + + +/* used by AR6000_XIOCTL_GPIO_OUTPUT_SET */ +struct ar6000_gpio_output_set_cmd_s { + A_UINT32 set_mask; + A_UINT32 clear_mask; + A_UINT32 enable_mask; + A_UINT32 disable_mask; +}; + +/* + * used by AR6000_XIOCTL_GPIO_REGISTER_GET and AR6000_XIOCTL_GPIO_REGISTER_SET + */ +struct ar6000_gpio_register_cmd_s { + A_UINT32 gpioreg_id; + A_UINT32 value; +}; + +/* used by AR6000_XIOCTL_GPIO_INTR_ACK */ +struct ar6000_gpio_intr_ack_cmd_s { + A_UINT32 ack_mask; +}; + +/* used by AR6000_XIOCTL_GPIO_INTR_WAIT */ +struct ar6000_gpio_intr_wait_cmd_s { + A_UINT32 intr_mask; + A_UINT32 input_values; +}; + +/* used by the AR6000_XIOCTL_DBGLOG_CFG_MODULE */ +typedef struct ar6000_dbglog_module_config_s { + A_UINT32 valid; + A_UINT16 mmask; + A_UINT16 tsr; + A_BOOL rep; + A_UINT16 size; +} DBGLOG_MODULE_CONFIG; + +typedef struct user_rssi_thold_t { + A_INT16 tag; + A_INT16 rssi; +} USER_RSSI_THOLD; + +typedef struct user_rssi_params_t { + A_UINT8 weight; + A_UINT32 pollTime; + USER_RSSI_THOLD tholds[12]; +} USER_RSSI_PARAMS; + +/* + * Host driver may have some config parameters. Typically, these + * config params are one time config parameters. These could + * correspond to any of the underlying modules. Host driver exposes + * an api for the underlying modules to get this config. + */ +#define AR6000_DRIVER_CFG_BASE 0x8000 + +/* Should driver perform wlan node caching? */ +#define AR6000_DRIVER_CFG_GET_WLANNODECACHING 0x8001 +/*Should we log raw WMI msgs */ +#define AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS 0x8002 + +/* used by AR6000_XIOCTL_DIAG_READ & AR6000_XIOCTL_DIAG_WRITE */ +struct ar6000_diag_window_cmd_s { + unsigned int addr; + unsigned int value; +}; + + +struct ar6000_traffic_activity_change { + A_UINT32 StreamID; /* stream ID to indicate activity change */ + A_UINT32 Active; /* active (1) or inactive (0) */ +}; + +/* Used with AR6000_XIOCTL_PROF_COUNT_GET */ +struct prof_count_s { + A_UINT32 addr; /* bin start address */ + A_UINT32 count; /* hit count */ +}; + +#ifdef __cplusplus +} +#endif +#endif diff -urN linux-2.6.26/drivers/net/wireless/ar6000/os/linux/include/athtypes_linux.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/os/linux/include/athtypes_linux.h --- linux-2.6.26/drivers/net/wireless/ar6000/os/linux/include/athtypes_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/os/linux/include/athtypes_linux.h 2010-08-10 04:16:45.000000000 -0400 @@ -0,0 +1,49 @@ +/* + * This file contains the definitions of the basic atheros data types. + * It is used to map the data types in atheros files to a platform specific + * type. + * + * Copyright 2003-2005 Atheros Communications, Inc., All Rights Reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _ATHTYPES_LINUX_H_ +#define _ATHTYPES_LINUX_H_ + +#ifdef __KERNEL__ +#include +#endif + +typedef int8_t A_INT8; +typedef int16_t A_INT16; +typedef int32_t A_INT32; +typedef int64_t A_INT64; + +typedef u_int8_t A_UINT8; +typedef u_int16_t A_UINT16; +typedef u_int32_t A_UINT32; +typedef u_int64_t A_UINT64; + +typedef int A_BOOL; +typedef char A_CHAR; +typedef unsigned char A_UCHAR; +typedef unsigned long A_ATH_TIMER; + + +#endif /* _ATHTYPES_LINUX_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/os/linux/include/config_linux.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/os/linux/include/config_linux.h --- linux-2.6.26/drivers/net/wireless/ar6000/os/linux/include/config_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/os/linux/include/config_linux.h 2010-08-10 04:16:45.000000000 -0400 @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _CONFIG_LINUX_H_ +#define _CONFIG_LINUX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Host-side GPIO support is optional. + * If run-time access to GPIO pins is not required, then + * this should be changed to #undef. + */ +#define CONFIG_HOST_GPIO_SUPPORT + +/* + * Host side Test Command support + */ +#define CONFIG_HOST_TCMD_SUPPORT + +#define USE_4BYTE_REGISTER_ACCESS + +/* Host-side support for Target-side profiling */ +#undef CONFIG_TARGET_PROFILE_SUPPORT + +/* Force AR6002 REV1 hardware to recognize Host */ +#undef CONFIG_AR6002_REV1_FORCE_HOST + +#ifdef __cplusplus +} +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ar6000/os/linux/include/debug_linux.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/os/linux/include/debug_linux.h --- linux-2.6.26/drivers/net/wireless/ar6000/os/linux/include/debug_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/os/linux/include/debug_linux.h 2010-08-10 04:16:45.000000000 -0400 @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2004-2006 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _DEBUG_LINUX_H_ +#define _DEBUG_LINUX_H_ + +#define DBG_DEFAULTS (DBG_ERROR|DBG_WARNING) + +extern A_UINT32 g_dbg_flags; + +#define DBGFMT "%s() : " +#define DBGARG __func__ +#define DBGFN A_PRINTF + +/* ------- Debug related stuff ------- */ +enum { + ATH_DEBUG_SEND = 0x0001, + ATH_DEBUG_RECV = 0x0002, + ATH_DEBUG_SYNC = 0x0004, + ATH_DEBUG_DUMP = 0x0008, + ATH_DEBUG_IRQ = 0x0010, + ATH_DEBUG_TRC = 0x0020, + ATH_DEBUG_WARN = 0x0040, + ATH_DEBUG_ERR = 0x0080, + ATH_LOG_INF = 0x0100, + ATH_DEBUG_BMI = 0x0110, + ATH_DEBUG_WMI = 0x0120, + ATH_DEBUG_HIF = 0x0140, + ATH_DEBUG_HTC = 0x0180, + ATH_DEBUG_WLAN = 0x1000, + ATH_LOG_ERR = 0x1010, + ATH_DEBUG_ANY = 0xFFFF, +}; + +#ifdef DEBUG + +#define A_DPRINTF(f, a) \ + if(g_dbg_flags & (f)) \ + { \ + DBGFN a ; \ + } + + +// TODO FIX usage of A_PRINTF! +#define AR_DEBUG_LVL_CHECK(lvl) (debughtc & (lvl)) +#define AR_DEBUG_PRINTBUF(buffer, length, desc) do { \ + if (debughtc & ATH_DEBUG_DUMP) { \ + DebugDumpBytes(buffer, length,desc); \ + } \ +} while(0) +#define PRINTX_ARG(arg...) arg +#define AR_DEBUG_PRINTF(flags, args) do { \ + if (debughtc & (flags)) { \ + A_PRINTF(KERN_ALERT PRINTX_ARG args); \ + } \ +} while (0) +#define AR_DEBUG_ASSERT(test) do { \ + if (!(test)) { \ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test)); \ + } \ +} while(0) +extern int debughtc; +#else +#define AR_DEBUG_PRINTF(flags, args) +#define AR_DEBUG_PRINTBUF(buffer, length, desc) +#define AR_DEBUG_ASSERT(test) +#define AR_DEBUG_LVL_CHECK(lvl) 0 +#define A_DPRINTF(f, a) +#endif + +#endif /* _DEBUG_LINUX_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/os/linux/include/engine.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/os/linux/include/engine.h --- linux-2.6.26/drivers/net/wireless/ar6000/os/linux/include/engine.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/os/linux/include/engine.h 2010-08-10 04:16:45.000000000 -0400 @@ -0,0 +1,97 @@ +/* + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ +/* + * athloader.h - definitions for atheros firmware loader. + * + * Firmware image format: + * + * unsigned char 0xFF // "magic" + * unsigned char version // fw loader / tool version, not fw version major/minor 4 bits each + * char hostname[variable] // zero delimited hostname where the image was built + * unsigned char month // + * unsigned char day // Date and time when the image was built + * unsigned char year // year is a number of years after 2008, i.e. 2008 is coided as 0 + * unsigned char hour // + * unsigned char min // + * // the rest are optional blocks that may be repeated and/or mixed + * unsigned char instruction + * unsigned char argument[4] // optional constant, mask or offset + * unsigned char image[variable] // optional loadable image + * // repeated as necessary + * unsigned char crc32[4] // inverted crc32 + * + */ +#ifndef ATHLOADER_IS_SEEN +#define ATHLOADER_IS_SEEN + +#include + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +#define FW_AUTOLOAD +/* Uncomment the following to build standalone application for testing + +#define UNIT_TEST +#define syserr printf +#define sysprint printf +#include "crc32.h" +#include + */ + +#ifndef UNIT_TEST +#if defined(__linux__) || defined(LINUX) +#include +#include +#include +#include +#include +#include +#define syserr(arg...) printk( KERN_ERR arg) +#define sysprint(arg...) printk( KERN_INFO arg) +#endif /* __linux__ */ +#endif /* UNIT_TEST */ + +#define VERSION (0x01) + +/* Opcodes */ +#define RLoad (0x10) +#define Ror (0x20) +#define Rand (0x30) +#define Add (0x40) +#define Rstor (0x50) +#define Shift (0x60) +#define Nneg (0x70) +#define Trr (0x80) +#define Trw (0x90) +#define Trx (0xA0) +#define Exit (0xB0) +#define Cmp (0xC0) +#define Ldprn (0xD0) +#define Jump (0xE0) + +extern unsigned int get_target_reg( unsigned address, void *ar ); +extern int write_target_reg( unsigned address, unsigned value, void *ar ); +extern int execute_on_target( unsigned int address, unsigned int arg, void *ar ); +extern int load_binary(unsigned int addr, unsigned char *data, void *ar ); +extern void bmidone( void *ar ); +#endif /* KERNEL 2.6 only */ +#endif /* ATHLOADER_IS_SEEN */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/os/linux/include/ieee80211_ioctl.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/os/linux/include/ieee80211_ioctl.h --- linux-2.6.26/drivers/net/wireless/ar6000/os/linux/include/ieee80211_ioctl.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/os/linux/include/ieee80211_ioctl.h 2010-08-10 04:16:45.000000000 -0400 @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2004-2005 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _IEEE80211_IOCTL_H_ +#define _IEEE80211_IOCTL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Extracted from the MADWIFI net80211/ieee80211_ioctl.h + */ + +/* + * WPA/RSN get/set key request. Specify the key/cipher + * type and whether the key is to be used for sending and/or + * receiving. The key index should be set only when working + * with global keys (use IEEE80211_KEYIX_NONE for ``no index''). + * Otherwise a unicast/pairwise key is specified by the bssid + * (on a station) or mac address (on an ap). They key length + * must include any MIC key data; otherwise it should be no + more than IEEE80211_KEYBUF_SIZE. + */ +struct ieee80211req_key { + u_int8_t ik_type; /* key/cipher type */ + u_int8_t ik_pad; + u_int16_t ik_keyix; /* key index */ + u_int8_t ik_keylen; /* key length in bytes */ + u_int8_t ik_flags; +#define IEEE80211_KEY_XMIT 0x01 +#define IEEE80211_KEY_RECV 0x02 +#define IEEE80211_KEY_DEFAULT 0x80 /* default xmit key */ + u_int8_t ik_macaddr[IEEE80211_ADDR_LEN]; + u_int64_t ik_keyrsc; /* key receive sequence counter */ + u_int64_t ik_keytsc; /* key transmit sequence counter */ + u_int8_t ik_keydata[IEEE80211_KEYBUF_SIZE+IEEE80211_MICBUF_SIZE]; +}; +/* + * Delete a key either by index or address. Set the index + * to IEEE80211_KEYIX_NONE when deleting a unicast key. + */ +struct ieee80211req_del_key { + u_int8_t idk_keyix; /* key index */ + u_int8_t idk_macaddr[IEEE80211_ADDR_LEN]; +}; +/* + * MLME state manipulation request. IEEE80211_MLME_ASSOC + * only makes sense when operating as a station. The other + * requests can be used when operating as a station or an + * ap (to effect a station). + */ +struct ieee80211req_mlme { + u_int8_t im_op; /* operation to perform */ +#define IEEE80211_MLME_ASSOC 1 /* associate station */ +#define IEEE80211_MLME_DISASSOC 2 /* disassociate station */ +#define IEEE80211_MLME_DEAUTH 3 /* deauthenticate station */ +#define IEEE80211_MLME_AUTHORIZE 4 /* authorize station */ +#define IEEE80211_MLME_UNAUTHORIZE 5 /* unauthorize station */ + u_int16_t im_reason; /* 802.11 reason code */ + u_int8_t im_macaddr[IEEE80211_ADDR_LEN]; +}; + +struct ieee80211req_addpmkid { + u_int8_t pi_bssid[IEEE80211_ADDR_LEN]; + u_int8_t pi_enable; + u_int8_t pi_pmkid[16]; +}; + +#define AUTH_ALG_OPEN_SYSTEM 0x01 +#define AUTH_ALG_SHARED_KEY 0x02 +#define AUTH_ALG_LEAP 0x04 + +struct ieee80211req_authalg { + u_int8_t auth_alg; +}; + +/* + * Request to add an IE to a Management Frame + */ +enum{ + IEEE80211_APPIE_FRAME_BEACON = 0, + IEEE80211_APPIE_FRAME_PROBE_REQ = 1, + IEEE80211_APPIE_FRAME_PROBE_RESP = 2, + IEEE80211_APPIE_FRAME_ASSOC_REQ = 3, + IEEE80211_APPIE_FRAME_ASSOC_RESP = 4, + IEEE80211_APPIE_NUM_OF_FRAME = 5 +}; + +/* + * The Maximum length of the IE that can be added to a Management frame + */ +#define IEEE80211_APPIE_FRAME_MAX_LEN 78 + +struct ieee80211req_getset_appiebuf { + u_int32_t app_frmtype; /* management frame type for which buffer is added */ + u_int32_t app_buflen; /*application supplied buffer length */ + u_int8_t app_buf[]; +}; + +/* + * The following definitions are used by an application to set filter + * for receiving management frames + */ +enum { + IEEE80211_FILTER_TYPE_BEACON = 0x1, + IEEE80211_FILTER_TYPE_PROBE_REQ = 0x2, + IEEE80211_FILTER_TYPE_PROBE_RESP = 0x4, + IEEE80211_FILTER_TYPE_ASSOC_REQ = 0x8, + IEEE80211_FILTER_TYPE_ASSOC_RESP = 0x10, + IEEE80211_FILTER_TYPE_AUTH = 0x20, + IEEE80211_FILTER_TYPE_DEAUTH = 0x40, + IEEE80211_FILTER_TYPE_DISASSOC = 0x80, + IEEE80211_FILTER_TYPE_ALL = 0xFF /* used to check the valid filter bits */ +}; + +struct ieee80211req_set_filter { + u_int32_t app_filterype; /* management frame filter type */ +}; + +enum { + IEEE80211_PARAM_AUTHMODE = 3, /* Authentication Mode */ + IEEE80211_PARAM_MCASTCIPHER = 5, + IEEE80211_PARAM_MCASTKEYLEN = 6, /* multicast key length */ + IEEE80211_PARAM_UCASTCIPHER = 8, + IEEE80211_PARAM_UCASTKEYLEN = 9, /* unicast key length */ + IEEE80211_PARAM_WPA = 10, /* WPA mode (0,1,2) */ + IEEE80211_PARAM_ROAMING = 12, /* roaming mode */ + IEEE80211_PARAM_PRIVACY = 13, /* privacy invoked */ + IEEE80211_PARAM_COUNTERMEASURES = 14, /* WPA/TKIP countermeasures */ + IEEE80211_PARAM_DROPUNENCRYPTED = 15, /* discard unencrypted frames */ +}; + +/* + * Values for IEEE80211_PARAM_WPA + */ +#define WPA_MODE_WPA1 1 +#define WPA_MODE_WPA2 2 +#define WPA_MODE_AUTO 3 +#define WPA_MODE_NONE 4 + +#ifdef __cplusplus +} +#endif + +#endif /* _IEEE80211_IOCTL_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/os/linux/include/osapi_linux.h linux-2.6.26-lab126/drivers/net/wireless/ar6000/os/linux/include/osapi_linux.h --- linux-2.6.26/drivers/net/wireless/ar6000/os/linux/include/osapi_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/os/linux/include/osapi_linux.h 2010-08-10 04:16:45.000000000 -0400 @@ -0,0 +1,331 @@ +/* + * This file contains the definitions of the basic atheros data types. + * It is used to map the data types in atheros files to a platform specific + * type. + * + * Copyright 2003-2005 Atheros Communications, Inc., All Rights Reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _OSAPI_LINUX_H_ +#define _OSAPI_LINUX_H_ + +#ifdef __KERNEL__ + +#include +#include +#include +#include +#include +#include +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +#include +#endif +#include +#include +#include +#ifdef KERNEL_2_4 +#include +#include +#endif + +#ifdef __GNUC__ +#define __ATTRIB_PACK __attribute__ ((packed)) +#define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2))) +#define __ATTRIB_NORETURN __attribute__ ((noreturn)) +#ifndef INLINE +#define INLINE __inline__ +#endif +#else /* Not GCC */ +#define __ATTRIB_PACK +#define __ATTRIB_PRINTF +#define __ATTRIB_NORETURN +#ifndef INLINE +#define INLINE __inline +#endif +#endif /* End __GNUC__ */ + +#define PREPACK +#define POSTPACK __ATTRIB_PACK + +/* + * Endianes macros + */ +#define A_BE2CPU8(x) ntohb(x) +#define A_BE2CPU16(x) ntohs(x) +#define A_BE2CPU32(x) ntohl(x) + +#define A_LE2CPU8(x) (x) +#define A_LE2CPU16(x) (x) +#define A_LE2CPU32(x) (x) + +#define A_CPU2BE8(x) htonb(x) +#define A_CPU2BE16(x) htons(x) +#define A_CPU2BE32(x) htonl(x) + +#define A_MEMCPY(dst, src, len) memcpy((A_UINT8 *)(dst), (src), (len)) +#define A_MEMZERO(addr, len) memset(addr, 0, len) +#define A_MEMCMP(addr1, addr2, len) memcmp((addr1), (addr2), (len)) +#define A_MALLOC(size) kmalloc((size), GFP_KERNEL) +#define A_MALLOC_NOWAIT(size) kmalloc((size), GFP_ATOMIC) +#define A_FREE(addr) kfree(addr) +#define A_PRINTF(args...) printk(args) +#define A_SPRINTF(buf, args...) sprintf (buf, args) + +/* Mutual Exclusion */ +typedef spinlock_t A_MUTEX_T; +#define A_MUTEX_INIT(mutex) spin_lock_init(mutex) +#define A_MUTEX_LOCK(mutex) spin_lock_bh(mutex) +#define A_MUTEX_UNLOCK(mutex) spin_unlock_bh(mutex) +#define A_IS_MUTEX_VALID(mutex) TRUE /* okay to return true, since A_MUTEX_DELETE does nothing */ +#define A_MUTEX_DELETE(mutex) /* spin locks are not kernel resources so nothing to free.. */ + +/* Get current time in ms adding a constant offset (in ms) */ +#define A_GET_MS(offset) \ + (jiffies + ((offset) / 1000) * HZ) + +/* + * Timer Functions + */ +#define A_MDELAY(msecs) mdelay(msecs) +typedef struct timer_list A_TIMER; + +#define A_INIT_TIMER(pTimer, pFunction, pArg) do { \ + init_timer(pTimer); \ + (pTimer)->function = (pFunction); \ + (pTimer)->data = (unsigned long)(pArg); \ +} while (0) + +/* + * Start a Timer that elapses after 'periodMSec' milli-seconds + * Support is provided for a one-shot timer. The 'repeatFlag' is + * ignored. + */ +#define A_TIMEOUT_MS(pTimer, periodMSec, repeatFlag) do { \ + if (repeatFlag) { \ + printk("\n" __FILE__ ":%d: Timer Repeat requested\n",__LINE__); \ + panic("Timer Repeat"); \ + } \ + mod_timer((pTimer), jiffies + HZ * (periodMSec) / 1000); \ +} while (0) + +/* + * Cancel the Timer. + */ +#define A_UNTIMEOUT(pTimer) do { \ + del_timer((pTimer)); \ +} while (0) + +#define A_DELETE_TIMER(pTimer) do { \ +} while (0) + +/* + * Wait Queue related functions + */ +typedef wait_queue_head_t A_WAITQUEUE_HEAD; +#define A_INIT_WAITQUEUE_HEAD(head) init_waitqueue_head(head) +#ifndef wait_event_interruptible_timeout +#define __wait_event_interruptible_timeout(wq, condition, ret) \ +do { \ + wait_queue_t __wait; \ + init_waitqueue_entry(&__wait, current); \ + \ + add_wait_queue(&wq, &__wait); \ + for (;;) { \ + set_current_state(TASK_INTERRUPTIBLE); \ + if (condition) \ + break; \ + if (!signal_pending(current)) { \ + ret = schedule_timeout(ret); \ + if (!ret) \ + break; \ + continue; \ + } \ + ret = -ERESTARTSYS; \ + break; \ + } \ + current->state = TASK_RUNNING; \ + remove_wait_queue(&wq, &__wait); \ +} while (0) + +#define wait_event_interruptible_timeout(wq, condition, timeout) \ +({ \ + long __ret = timeout; \ + if (!(condition)) \ + __wait_event_interruptible_timeout(wq, condition, __ret); \ + __ret; \ +}) +#endif /* wait_event_interruptible_timeout */ + +#define A_WAIT_EVENT_INTERRUPTIBLE_TIMEOUT(head, condition, timeout) do { \ + wait_event_interruptible_timeout(head, condition, timeout); \ +} while (0) + +#define A_WAKE_UP(head) wake_up(head) + +#ifdef DEBUG +#define A_ASSERT(expr) \ + if (!(expr)) { \ + printk(KERN_ALERT "\n" __FILE__ ":%d: Assertion " #expr " failed!\n",__LINE__); \ + panic(#expr); \ + } + +#else +#define A_ASSERT(expr) +#endif /* DEBUG */ + +/* + * Initialization of the network buffer subsystem + */ +#define A_NETBUF_INIT() + +/* + * Network buffer queue support + */ +typedef struct sk_buff_head A_NETBUF_QUEUE_T; + +#define A_NETBUF_QUEUE_INIT(q) \ + a_netbuf_queue_init(q) + +#define A_NETBUF_ENQUEUE(q, pkt) \ + a_netbuf_enqueue((q), (pkt)) +#define A_NETBUF_PREQUEUE(q, pkt) \ + a_netbuf_prequeue((q), (pkt)) +#define A_NETBUF_DEQUEUE(q) \ + (a_netbuf_dequeue(q)) +#define A_NETBUF_QUEUE_SIZE(q) \ + a_netbuf_queue_size(q) +#define A_NETBUF_QUEUE_EMPTY(q) \ + a_netbuf_queue_empty(q) + +/* + * Network buffer support + */ +#define A_NETBUF_ALLOC(size) \ + a_netbuf_alloc(size) +#define A_NETBUF_ALLOC_RAW(size) \ + a_netbuf_alloc_raw(size) +#define A_NETBUF_FREE(bufPtr) \ + a_netbuf_free(bufPtr) +#define A_NETBUF_DATA(bufPtr) \ + a_netbuf_to_data(bufPtr) +#define A_NETBUF_LEN(bufPtr) \ + a_netbuf_to_len(bufPtr) +#define A_NETBUF_PUSH(bufPtr, len) \ + a_netbuf_push(bufPtr, len) +#define A_NETBUF_PUT(bufPtr, len) \ + a_netbuf_put(bufPtr, len) +#define A_NETBUF_TRIM(bufPtr,len) \ + a_netbuf_trim(bufPtr, len) +#define A_NETBUF_PULL(bufPtr, len) \ + a_netbuf_pull(bufPtr, len) +#define A_NETBUF_HEADROOM(bufPtr)\ + a_netbuf_headroom(bufPtr) +#define A_NETBUF_SETLEN(bufPtr,len) \ + a_netbuf_setlen(bufPtr, len) + +/* Add data to end of a buffer */ +#define A_NETBUF_PUT_DATA(bufPtr, srcPtr, len) \ + a_netbuf_put_data(bufPtr, srcPtr, len) + +/* Add data to start of the buffer */ +#define A_NETBUF_PUSH_DATA(bufPtr, srcPtr, len) \ + a_netbuf_push_data(bufPtr, srcPtr, len) + +/* Remove data at start of the buffer */ +#define A_NETBUF_PULL_DATA(bufPtr, dstPtr, len) \ + a_netbuf_pull_data(bufPtr, dstPtr, len) + +/* Remove data from the end of the buffer */ +#define A_NETBUF_TRIM_DATA(bufPtr, dstPtr, len) \ + a_netbuf_trim_data(bufPtr, dstPtr, len) + +/* View data as "size" contiguous bytes of type "t" */ +#define A_NETBUF_VIEW_DATA(bufPtr, t, size) \ + (t )( ((struct skbuf *)(bufPtr))->data) + +/* return the beginning of the headroom for the buffer */ +#define A_NETBUF_HEAD(bufPtr) \ + ((((struct sk_buff *)(bufPtr))->head)) + +/* + * OS specific network buffer access routines + */ +void *a_netbuf_alloc(int size); +void *a_netbuf_alloc_raw(int size); +void a_netbuf_free(void *bufPtr); +void *a_netbuf_to_data(void *bufPtr); +A_UINT32 a_netbuf_to_len(void *bufPtr); +A_STATUS a_netbuf_push(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len); +A_STATUS a_netbuf_put(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len); +A_STATUS a_netbuf_pull(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len); +A_STATUS a_netbuf_trim(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len); +A_STATUS a_netbuf_setlen(void *bufPtr, A_INT32 len); +A_INT32 a_netbuf_headroom(void *bufPtr); +void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt); +void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt); +void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q); +int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q); +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q); +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q); +void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q); + +/* + * Kernel v.s User space functions + */ +A_UINT32 a_copy_to_user(void *to, const void *from, A_UINT32 n); +A_UINT32 a_copy_from_user(void *to, const void *from, A_UINT32 n); + +/* In linux, WLAN Rx and Tx run in different contexts, so no need to check + * for any commands/data queued for WLAN */ +#define A_CHECK_DRV_TX() + +#else /* __KERNEL__ */ + +#ifdef __GNUC__ +#define __ATTRIB_PACK __attribute__ ((packed)) +#define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2))) +#define __ATTRIB_NORETURN __attribute__ ((noreturn)) +#ifndef INLINE +#define INLINE __inline__ +#endif +#else /* Not GCC */ +#define __ATTRIB_PACK +#define __ATTRIB_PRINTF +#define __ATTRIB_NORETURN +#ifndef INLINE +#define INLINE __inline +#endif +#endif /* End __GNUC__ */ + +#define PREPACK +#define POSTPACK __ATTRIB_PACK + +#define A_MEMCPY(dst, src, len) memcpy((dst), (src), (len)) +#define A_MEMZERO(addr, len) memset((addr), 0, (len)) +#define A_MEMCMP(addr1, addr2, len) memcmp((addr1), (addr2), (len)) +#define A_MALLOC(size) malloc(size) +#define A_FREE(addr) free(addr) +#endif /* __KERNEL__ */ + +#endif /* _OSAPI_LINUX_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ar6000/wireless_ext.c linux-2.6.26-lab126/drivers/net/wireless/ar6000/wireless_ext.c --- linux-2.6.26/drivers/net/wireless/ar6000/wireless_ext.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/wireless_ext.c 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,2313 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#include "ar6000_drv.h" + +static A_UINT8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; +static void ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi); +extern unsigned int wmitimeout; +extern A_WAITQUEUE_HEAD arEvent; + + +#if WIRELESS_EXT > 14 +/* + * Encode a WPA or RSN information element as a custom + * element using the hostap format. + */ +static u_int +encode_ie(void *buf, size_t bufsize, + const u_int8_t *ie, size_t ielen, + const char *leader, size_t leader_len) +{ + u_int8_t *p; + int i; + + if (bufsize < leader_len) + return 0; + p = buf; + memcpy(p, leader, leader_len); + bufsize -= leader_len; + p += leader_len; + for (i = 0; i < ielen && bufsize > 2; i++) + p += sprintf(p, "%02x", ie[i]); + return (i == ielen ? p - (u_int8_t *)buf : 0); +} +#endif /* WIRELESS_EXT > 14 */ + +void +ar6000_scan_node(void *arg, bss_t *ni) +{ + struct iw_event iwe; +#if WIRELESS_EXT > 14 + char buf[256]; +#endif + struct ar_giwscan_param *param; + A_CHAR *current_ev; + A_CHAR *end_buf; + struct ieee80211_common_ie *cie; + A_CHAR *current_val; + A_INT32 j; + A_UINT32 rate_len; + param = (struct ar_giwscan_param *)arg; + + if (param->current_ev >= param->end_buf) { + return; + } + if ((param->firstPass == TRUE) && + ((ni->ni_cie.ie_wpa == NULL) && (ni->ni_cie.ie_rsn == NULL))) { + /* + * Only forward wpa bss's in first pass + */ + return; + } + + if ((param->firstPass == FALSE) && + ((ni->ni_cie.ie_wpa != NULL) || (ni->ni_cie.ie_rsn != NULL))) { + /* + * Only forward non-wpa bss's in 2nd pass + */ + return; + } + + current_ev = param->current_ev; + end_buf = param->end_buf; + + cie = &ni->ni_cie; + + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWAP; + iwe.u.ap_addr.sa_family = ARPHRD_ETHER; + A_MEMCPY(iwe.u.ap_addr.sa_data, ni->ni_macaddr, 6); + current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, + IW_EV_ADDR_LEN); + + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWESSID; + iwe.u.data.flags = 1; + iwe.u.data.length = cie->ie_ssid[1]; + current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, + &cie->ie_ssid[2]); + + if (cie->ie_capInfo & (IEEE80211_CAPINFO_ESS|IEEE80211_CAPINFO_IBSS)) { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWMODE; + iwe.u.mode = cie->ie_capInfo & IEEE80211_CAPINFO_ESS ? + IW_MODE_MASTER : IW_MODE_ADHOC; + current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, + IW_EV_UINT_LEN); + } + + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWFREQ; + iwe.u.freq.m = cie->ie_chan * 100000; + iwe.u.freq.e = 1; + current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, + IW_EV_FREQ_LEN); + + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVQUAL; + ar6000_set_quality(&iwe.u.qual, ni->ni_snr); + current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, + IW_EV_QUAL_LEN); + + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWENCODE; + if (cie->ie_capInfo & IEEE80211_CAPINFO_PRIVACY) { + iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; + } else { + iwe.u.data.flags = IW_ENCODE_DISABLED; + } + iwe.u.data.length = 0; + current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, ""); + + /* supported bit rate */ + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWRATE; + iwe.u.bitrate.fixed = 0; + iwe.u.bitrate.disabled = 0; + iwe.u.bitrate.value = 0; + current_val = current_ev + IW_EV_LCP_LEN; + + if (cie->ie_rates != NULL) { + rate_len = cie->ie_rates[1]; + for (j = 0; j < rate_len; j++) { + unsigned char val; + val = cie->ie_rates[2 + j]; + iwe.u.bitrate.value = + (val >= 0x80)? ((val - 0x80) * 500000): (val * 500000); + current_val = iwe_stream_add_value( + current_ev, + current_val, + end_buf, + &iwe, + IW_EV_PARAM_LEN); + } + } + if (cie->ie_xrates != NULL) { + rate_len = cie->ie_xrates[1]; + for (j = 0; j < rate_len; j++) { + unsigned char val; + val = cie->ie_xrates[2 + j]; + iwe.u.bitrate.value = + (val >= 0x80)? ((val - 0x80) * 500000): (val * 500000); + current_val = iwe_stream_add_value( + current_ev, + current_val, + end_buf, + &iwe, + IW_EV_PARAM_LEN); + } + } + /* remove fixed header if no rates were added */ + if ((current_val - current_ev) > IW_EV_LCP_LEN) + current_ev = current_val; + +#if WIRELESS_EXT >= 18 + /* IE */ + if (cie->ie_wpa != NULL) { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVGENIE; + iwe.u.data.length = cie->ie_wpa[1] + 2; + memcpy(buf, cie->ie_wpa, cie->ie_wpa[1] + 2); + current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, buf); + } + if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVGENIE; + iwe.u.data.length = cie->ie_rsn[1] + 2; + memcpy(buf, cie->ie_rsn, cie->ie_rsn[1] + 2); + current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, buf); + } +#endif + + /* protocol */ + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWNAME; +#define CHAN_IS_11A(x) (!((x >= 2412) && (x <= 2484))) + if (CHAN_IS_11A(cie->ie_chan)) { + /* 11a */ + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11a"); + } else if ((cie->ie_erp) || (cie->ie_xrates)) { + /* 11g */ + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11g"); + } else { + /* 11b */ + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11b"); + } + current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_CHAR_LEN); + +#if WIRELESS_EXT > 14 + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + snprintf(buf, sizeof(buf), "bcn_int=%d", cie->ie_beaconInt); + iwe.u.data.length = strlen(buf); + current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, buf); + +#if WIRELESS_EXT < 18 + if (cie->ie_wpa != NULL) { + static const char wpa_leader[] = "wpa_ie="; + + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wpa, + cie->ie_wpa[1]+2, + wpa_leader, sizeof(wpa_leader)-1); + + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, buf); + } + } + + if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) { + static const char rsn_leader[] = "rsn_ie="; + + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_rsn, + cie->ie_rsn[1]+2, + rsn_leader, sizeof(rsn_leader)-1); + + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, buf); + } + } +#endif + + if (cie->ie_wmm != NULL) { + static const char wmm_leader[] = "wmm_ie="; + + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wmm, + cie->ie_wmm[1]+2, + wmm_leader, sizeof(wmm_leader)-1); + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, buf); + } + } + + if (cie->ie_ath != NULL) { + static const char ath_leader[] = "ath_ie="; + + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_ath, + cie->ie_ath[1]+2, + ath_leader, sizeof(ath_leader)-1); + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, buf); + } + } + + if (cie->ie_wsc != NULL) { + static const char wsc_leader[] = "wsc_ie="; + + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wsc, + cie->ie_wsc[1]+2, + wsc_leader, sizeof(wsc_leader)-1); + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, buf); + } + } +#endif /* WIRELESS_EXT > 14 */ + + param->current_ev = current_ev; +} + +int +ar6000_ioctl_giwscan(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + struct ar_giwscan_param param; + int i; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + param.current_ev = extra; + param.end_buf = extra + IW_SCAN_MAX_DATA; + param.firstPass = TRUE; + + /* + * Do two passes to insure WPA scan candidates + * are sorted to the front. This is a hack to deal with + * the wireless extensions capping scan results at + * IW_SCAN_MAX_DATA bytes. In densely populated environments + * it's easy to overflow this buffer (especially with WPA/RSN + * information elements). Note this sorting hack does not + * guarantee we won't overflow anyway. + */ + for (i = 0; i < 2; i++) { + /* + * Translate data to WE format. + */ + wmi_iterate_nodes(ar->arWmi, ar6000_scan_node, ¶m); + param.firstPass = FALSE; + if (param.current_ev >= param.end_buf) { + data->length = param.current_ev - extra; + return -E2BIG; + } + } + + if(!(data->length = param.current_ev - extra)) + return -EAGAIN; + return 0; +} + +extern int reconnect_flag; +/* SIOCSIWESSID */ +static int +ar6000_ioctl_siwessid(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *ssid) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + A_STATUS status; + A_UINT8 arNetworkType; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + +#if defined(WIRELESS_EXT) + if (WIRELESS_EXT >= 20) { + data->length += 1; + } +#endif + + /* + * iwconfig passes a null terminated string with length including this + * so we need to account for this + */ + if (data->flags && (!data->length || (data->length == 1) || + ((data->length - 1) > sizeof(ar->arSsid)))) + { + /* + * ssid is invalid + */ + return -EINVAL; + } + /* Added for bug 25178, return an IOCTL error instead of target returning + Illegal parameter error when either the BSSID or channel is missing + and we cannot scan during connect. + */ + if (data->flags) { + if (ar->arSkipScan == TRUE && + (ar->arChannelHint == 0 || + (!ar->arReqBssid[0] && !ar->arReqBssid[1] && !ar->arReqBssid[2] && + !ar->arReqBssid[3] && !ar->arReqBssid[4] && !ar->arReqBssid[5]))) + { + return -EINVAL; + } + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (ar->arTxPending[wmi_get_control_ep(ar->arWmi)]) { + /* + * sleep until the command queue drains + */ + wait_event_interruptible_timeout(arEvent, + ar->arTxPending[wmi_get_control_ep(ar->arWmi)] == 0, wmitimeout * HZ); + if (signal_pending(current)) { + return -EINTR; + } + } + + if (!data->flags) { + arNetworkType = ar->arNetworkType; + ar6000_init_profile_info(ar); + ar->arNetworkType = arNetworkType; + } + + if ((ar->arSsidLen) || (!data->flags)) + { + if ((!data->flags) || + (A_MEMCMP(ar->arSsid, ssid, ar->arSsidLen) != 0) || + (ar->arSsidLen != (data->length - 1))) + { + /* + * SSID set previously or essid off has been issued. + * + * Disconnect Command is issued in two cases after wmi is ready + * (1) ssid is different from the previous setting + * (2) essid off has been issued + * + */ + if (ar->arWmiReady == TRUE) { + reconnect_flag = 0; + status = wmi_disconnect_cmd(ar->arWmi); + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = 0; + if (ar->arSkipScan == FALSE) { + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + } + if (!data->flags) { + up(&ar->arSem); + return 0; + } + } else { + up(&ar->arSem); + } + } + else + { + /* + * SSID is same, so we assume profile hasn't changed. + * If the interface is up and wmi is ready, we issue + * a reconnect cmd. Issue a reconnect only we are already + * connected. + */ + if((ar->arConnected == TRUE) && (ar->arWmiReady == TRUE)) + { + reconnect_flag = TRUE; + status = wmi_reconnect_cmd(ar->arWmi,ar->arReqBssid, + ar->arChannelHint); + up(&ar->arSem); + if (status != A_OK) { + return -EIO; + } + return 0; + } + else{ + /* + * Dont return if connect is pending. + */ + if(!(ar->arConnectPending)) { + up(&ar->arSem); + return 0; + } + } + } + } + + ar->arSsidLen = data->length - 1; + A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen); + + /* The ssid length check prevents second "essid off" from the user, + to be treated as a connect cmd. The second "essid off" is ignored. + */ + if((ar->arWmiReady == TRUE) && (ar->arSsidLen > 0) ) + { + if (SHARED_AUTH == ar->arDot11AuthMode) { + ar6000_install_static_wep_keys(ar); + } + + if (!ar->arUserBssFilter) { + if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != A_OK) { + up(&ar->arSem); + return -EIO; + } + } + + AR_DEBUG_PRINTF("Connect called with authmode %d dot11 auth %d"\ + " PW crypto %d PW crypto Len %d GRP crypto %d"\ + " GRP crypto Len %d\n", + ar->arAuthMode, ar->arDot11AuthMode, + ar->arPairwiseCrypto, ar->arPairwiseCryptoLen, + ar->arGroupCrypto, ar->arGroupCryptoLen); + reconnect_flag = 0; + status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType, + ar->arDot11AuthMode, ar->arAuthMode, + ar->arPairwiseCrypto, ar->arPairwiseCryptoLen, + ar->arGroupCrypto,ar->arGroupCryptoLen, + ar->arSsidLen, ar->arSsid, + ar->arReqBssid, ar->arChannelHint, + ar->arConnectCtrlFlags); + + + up(&ar->arSem); + + if (status != A_OK) { + return -EIO; + } + ar->arConnectPending = TRUE; + }else{ + up(&ar->arSem); + } + return 0; +} + +/* SIOCGIWESSID */ +static int +ar6000_ioctl_giwessid(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *essid) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (!ar->arSsidLen) { + return -EINVAL; + } + + data->flags = 1; + data->length = ar->arSsidLen; + A_MEMCPY(essid, ar->arSsid, ar->arSsidLen); + + return 0; +} + + +void ar6000_install_static_wep_keys(AR_SOFTC_T *ar) +{ + A_UINT8 index; + A_UINT8 keyUsage; + + for (index = WMI_MIN_KEY_INDEX; index <= WMI_MAX_KEY_INDEX; index++) { + if (ar->arWepKeyList[index].arKeyLen) { + keyUsage = GROUP_USAGE; + if (index == ar->arDefTxKeyIndex) { + keyUsage |= TX_USAGE; + } + wmi_addKey_cmd(ar->arWmi, + index, + WEP_CRYPT, + keyUsage, + ar->arWepKeyList[index].arKeyLen, + NULL, + ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL, + NO_SYNC_WMIFLAG); + } + } +} + +int +ar6000_ioctl_delkey(struct net_device *dev, struct iw_request_info *info, + void *w, char *extra) +{ + return 0; +} + +int +ar6000_ioctl_setmlme(struct net_device *dev, struct iw_request_info *info, + void *w, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + struct ieee80211req_mlme *mlme = (struct ieee80211req_mlme *)extra; + + if ((ar->arWmiReady == FALSE) || (ar->arConnected != TRUE)) { + return -EIO; + } + + switch (mlme->im_op) { + case IEEE80211_MLME_DISASSOC: + case IEEE80211_MLME_DEAUTH: + /* Not Supported */ + break; + default: + break; + } + return 0; +} + + +int +ar6000_ioctl_setwmmparams(struct net_device *dev, struct iw_request_info *info, + void *w, char *extra) +{ + return -EIO; /* for now */ +} + +int +ar6000_ioctl_getwmmparams(struct net_device *dev, struct iw_request_info *info, + void *w, char *extra) +{ + return -EIO; /* for now */ +} + +int +ar6000_ioctl_setoptie(struct net_device *dev, struct iw_request_info *info, + void *w, char *extra) +{ + return 0; +} + +int +ar6000_ioctl_setauthalg(struct net_device *dev, struct iw_request_info *info, + void *w, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + struct ieee80211req_authalg *req = (struct ieee80211req_authalg *)extra; + int ret = 0; + + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + if (req->auth_alg == AUTH_ALG_OPEN_SYSTEM) { + ar->arDot11AuthMode = OPEN_AUTH; + } else if (req->auth_alg == AUTH_ALG_LEAP) { + ar->arDot11AuthMode = LEAP_AUTH; + ar->arPairwiseCrypto = WEP_CRYPT; + ar->arGroupCrypto = WEP_CRYPT; + } else { + ret = -EIO; + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + return ret; +} +static int +ar6000_ioctl_addpmkid(struct net_device *dev, struct iw_request_info *info, + void *w, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + struct ieee80211req_addpmkid *req = (struct ieee80211req_addpmkid *)extra; + A_STATUS status; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + AR_DEBUG_PRINTF("Add pmkid for %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x en=%d\n", + req->pi_bssid[0], req->pi_bssid[1], req->pi_bssid[2], + req->pi_bssid[3], req->pi_bssid[4], req->pi_bssid[5], + req->pi_enable); + + status = wmi_setPmkid_cmd(ar->arWmi, req->pi_bssid, req->pi_pmkid, + req->pi_enable); + + if (status != A_OK) { + return -EIO; + } + + return 0; +} + +/* + * SIOCSIWRATE + */ +int +ar6000_ioctl_siwrate(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + A_UINT32 kbps; + + if (rrq->fixed) { + kbps = rrq->value / 1000; /* rrq->value is in bps */ + } else { + kbps = -1; /* -1 indicates auto rate */ + } + if(kbps != -1 && wmi_validate_bitrate(ar->arWmi, kbps) == A_EINVAL) + { + AR_DEBUG_PRINTF("BitRate is not Valid %d\n", kbps); + return -EINVAL; + } + ar->arBitRate = kbps; + if(ar->arWmiReady == TRUE) + { + if (wmi_set_bitrate_cmd(ar->arWmi, kbps) != A_OK) { + return -EINVAL; + } + } + return 0; +} + +/* + * SIOCGIWRATE + */ +int +ar6000_ioctl_giwrate(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + int ret = 0; + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if(ar->arWmiReady == TRUE) + { + ar->arBitRate = 0xFFFF; + if (wmi_get_bitrate_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + wait_event_interruptible_timeout(arEvent, ar->arBitRate != 0xFFFF, wmitimeout * HZ); + if (signal_pending(current)) { + ret = -EINTR; + } + } + /* If the interface is down or wmi is not ready or the target is not + connected - return the value stored in the device structure */ + if (!ret) { + if (ar->arBitRate == -1) { + rrq->fixed = TRUE; + rrq->value = 0; + } else { + rrq->value = ar->arBitRate * 1000; + } + } + + up(&ar->arSem); + + return ret; +} + +/* + * SIOCSIWTXPOW + */ +static int +ar6000_ioctl_siwtxpow(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + A_UINT8 dbM; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (rrq->disabled) { + return -EOPNOTSUPP; + } + + if (rrq->fixed) { + if (rrq->flags != IW_TXPOW_DBM) { + return -EOPNOTSUPP; + } + ar->arTxPwr= dbM = rrq->value; + ar->arTxPwrSet = TRUE; + } else { + ar->arTxPwr = dbM = 0; + ar->arTxPwrSet = FALSE; + } + if(ar->arWmiReady == TRUE) + { + AR_DEBUG_PRINTF("Set tx pwr cmd %d dbM\n", dbM); + wmi_set_txPwr_cmd(ar->arWmi, dbM); + } + return 0; +} + +/* + * SIOCGIWTXPOW + */ +int +ar6000_ioctl_giwtxpow(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + int ret = 0; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if((ar->arWmiReady == TRUE) && (ar->arConnected == TRUE)) + { + ar->arTxPwr = 0; + + if (wmi_get_txPwr_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->arTxPwr != 0, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + } + /* If the interace is down or wmi is not ready or target is not connected + then return value stored in the device structure */ + + if (!ret) { + if (ar->arTxPwrSet == TRUE) { + rrq->fixed = TRUE; + } + rrq->value = ar->arTxPwr; + rrq->flags = IW_TXPOW_DBM; + } + + up(&ar->arSem); + + return ret; +} + +/* + * SIOCSIWRETRY + * since iwconfig only provides us with one max retry value, we use it + * to apply to data frames of the BE traffic class. + */ +static int +ar6000_ioctl_siwretry(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (rrq->disabled) { + return -EOPNOTSUPP; + } + + if ((rrq->flags & IW_RETRY_TYPE) != IW_RETRY_LIMIT) { + return -EOPNOTSUPP; + } + + if ( !(rrq->value >= WMI_MIN_RETRIES) || !(rrq->value <= WMI_MAX_RETRIES)) { + return - EINVAL; + } + if(ar->arWmiReady == TRUE) + { + if (wmi_set_retry_limits_cmd(ar->arWmi, DATA_FRAMETYPE, WMM_AC_BE, + rrq->value, 0) != A_OK){ + return -EINVAL; + } + } + ar->arMaxRetries = rrq->value; + return 0; +} + +/* + * SIOCGIWRETRY + */ +static int +ar6000_ioctl_giwretry(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + rrq->disabled = 0; + switch (rrq->flags & IW_RETRY_TYPE) { + case IW_RETRY_LIFETIME: + return -EOPNOTSUPP; + break; + case IW_RETRY_LIMIT: + rrq->flags = IW_RETRY_LIMIT; + switch (rrq->flags & IW_RETRY_MODIFIER) { + case IW_RETRY_MIN: + rrq->flags |= IW_RETRY_MIN; + rrq->value = WMI_MIN_RETRIES; + break; + case IW_RETRY_MAX: + rrq->flags |= IW_RETRY_MAX; + rrq->value = ar->arMaxRetries; + break; + } + break; + } + return 0; +} + +/* + * SIOCSIWENCODE + */ +static int +ar6000_ioctl_siwencode(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, char *keybuf) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + int index; + A_INT32 auth = ar->arDot11AuthMode; + /* + * Static WEP Keys should be configured before setting the SSID + */ + if (ar->arSsidLen) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + index = erq->flags & IW_ENCODE_INDEX; + + if (index && (((index - 1) < WMI_MIN_KEY_INDEX) || + ((index - 1) > WMI_MAX_KEY_INDEX))) + { + return -EIO; + } + + if (erq->flags & IW_ENCODE_DISABLED) { + /* + * Encryption disabled + */ + if (index) { + /* + * If key index was specified then clear the specified key + */ + index--; + A_MEMZERO(ar->arWepKeyList[index].arKey, + sizeof(ar->arWepKeyList[index].arKey)); + ar->arWepKeyList[index].arKeyLen = 0; + } + ar->arDot11AuthMode = OPEN_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arGroupCrypto = NONE_CRYPT; + ar->arAuthMode = NONE_AUTH; + } else { + /* + * Enabling WEP encryption + */ + if (index) { + index--; /* keyindex is off base 1 in iwconfig */ + } + + if (erq->flags & IW_ENCODE_OPEN) { + auth = OPEN_AUTH; + } else if (erq->flags & IW_ENCODE_RESTRICTED) { + auth = SHARED_AUTH; + } + + if (erq->length) { + if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(erq->length)) { + return -EIO; + } + + A_MEMZERO(ar->arWepKeyList[index].arKey, + sizeof(ar->arWepKeyList[index].arKey)); + A_MEMCPY(ar->arWepKeyList[index].arKey, keybuf, erq->length); + ar->arWepKeyList[index].arKeyLen = erq->length; + } else { + if (ar->arWepKeyList[index].arKeyLen == 0) { + return -EIO; + } + ar->arDefTxKeyIndex = index; + } + + ar->arPairwiseCrypto = WEP_CRYPT; + ar->arGroupCrypto = WEP_CRYPT; + ar->arDot11AuthMode = auth; + ar->arAuthMode = NONE_AUTH; + } + + /* + * profile has changed. Erase ssid to signal change + */ + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + + return 0; +} + +static int +ar6000_ioctl_giwencode(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, char *key) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + A_UINT8 keyIndex; + struct ar_wep_key *wk; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arPairwiseCrypto == NONE_CRYPT) { + erq->length = 0; + erq->flags = IW_ENCODE_DISABLED; + } else { + /* get the keyIndex */ + keyIndex = erq->flags & IW_ENCODE_INDEX; + if (0 == keyIndex) { + keyIndex = ar->arDefTxKeyIndex; + } else if ((keyIndex - 1 < WMI_MIN_KEY_INDEX) || + (keyIndex - 1 > WMI_MAX_KEY_INDEX)) + { + keyIndex = WMI_MIN_KEY_INDEX; + } else { + keyIndex--; + } + erq->flags = keyIndex + 1; + erq->flags |= IW_ENCODE_ENABLED; + wk = &ar->arWepKeyList[keyIndex]; + if (erq->length > wk->arKeyLen) { + erq->length = wk->arKeyLen; + } + if (wk->arKeyLen) { + A_MEMCPY(key, wk->arKey, erq->length); + } + if (ar->arDot11AuthMode == OPEN_AUTH) { + erq->flags |= IW_ENCODE_OPEN; + } else if (ar->arDot11AuthMode == SHARED_AUTH) { + erq->flags |= IW_ENCODE_RESTRICTED; + } + } + + return 0; +} + +#if WIRELESS_EXT >= 18 +/* + * SIOCSIWGENIE + */ +static int +ar6000_ioctl_siwgenie(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + return 0; +} + + +/* + * SIOCGIWGENIE + */ +static int +ar6000_ioctl_giwgenie(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + erq->length = 0; + erq->flags = 0; + + return 0; +} + +/* + * SIOCSIWAUTH + */ +static int +ar6000_ioctl_siwauth(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + A_BOOL profChanged; + A_UINT16 param; + A_INT32 ret; + A_INT32 value; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + param = data->flags & IW_AUTH_INDEX; + value = data->value; + profChanged = TRUE; + ret = 0; + + switch (param) { + case IW_AUTH_WPA_VERSION: + if (value & IW_AUTH_WPA_VERSION_DISABLED) { + ar->arAuthMode = NONE_AUTH; + } else if (value & IW_AUTH_WPA_VERSION_WPA) { + ar->arAuthMode = WPA_AUTH; + } else if (value & IW_AUTH_WPA_VERSION_WPA2) { + ar->arAuthMode = WPA2_AUTH; + } else { + ret = -1; + profChanged = FALSE; + } + break; + case IW_AUTH_CIPHER_PAIRWISE: + if (value & IW_AUTH_CIPHER_NONE) { + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arPairwiseCryptoLen = 0; + } else if (value & IW_AUTH_CIPHER_WEP40) { + ar->arPairwiseCrypto = WEP_CRYPT; + ar->arPairwiseCryptoLen = 5; + } else if (value & IW_AUTH_CIPHER_TKIP) { + ar->arPairwiseCrypto = TKIP_CRYPT; + ar->arPairwiseCryptoLen = 0; + } else if (value & IW_AUTH_CIPHER_CCMP) { + ar->arPairwiseCrypto = AES_CRYPT; + ar->arPairwiseCryptoLen = 0; + } else if (value & IW_AUTH_CIPHER_WEP104) { + ar->arPairwiseCrypto = WEP_CRYPT; + ar->arPairwiseCryptoLen = 13; + } else { + ret = -1; + profChanged = FALSE; + } + break; + case IW_AUTH_CIPHER_GROUP: + if (value & IW_AUTH_CIPHER_NONE) { + ar->arGroupCrypto = NONE_CRYPT; + ar->arGroupCryptoLen = 0; + } else if (value & IW_AUTH_CIPHER_WEP40) { + ar->arGroupCrypto = WEP_CRYPT; + ar->arGroupCryptoLen = 5; + } else if (value & IW_AUTH_CIPHER_TKIP) { + ar->arGroupCrypto = TKIP_CRYPT; + ar->arGroupCryptoLen = 0; + } else if (value & IW_AUTH_CIPHER_CCMP) { + ar->arGroupCrypto = AES_CRYPT; + ar->arGroupCryptoLen = 0; + } else if (value & IW_AUTH_CIPHER_WEP104) { + ar->arGroupCrypto = WEP_CRYPT; + ar->arGroupCryptoLen = 13; + } else { + ret = -1; + profChanged = FALSE; + } + break; + case IW_AUTH_KEY_MGMT: + if (value & IW_AUTH_KEY_MGMT_PSK) { + if (WPA_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA_PSK_AUTH; + } else if (WPA2_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA2_PSK_AUTH; + } else { + ret = -1; + } + } else if (!(value & IW_AUTH_KEY_MGMT_802_1X)) { + ar->arAuthMode = NONE_AUTH; + } + break; + case IW_AUTH_TKIP_COUNTERMEASURES: + wmi_set_tkip_countermeasures_cmd(ar->arWmi, value); + profChanged = FALSE; + break; + case IW_AUTH_DROP_UNENCRYPTED: + profChanged = FALSE; + break; + case IW_AUTH_80211_AUTH_ALG: + if (value & IW_AUTH_ALG_OPEN_SYSTEM) { + ar->arDot11AuthMode = OPEN_AUTH; + } else if (value & IW_AUTH_ALG_SHARED_KEY) { + ar->arDot11AuthMode = SHARED_AUTH; + } else if (value & IW_AUTH_ALG_LEAP) { + ar->arDot11AuthMode = LEAP_AUTH; + } else { + ret = -1; + profChanged = FALSE; + } + break; + case IW_AUTH_WPA_ENABLED: + if (!value) { + ar->arAuthMode = NONE_AUTH; + } + break; + case IW_AUTH_RX_UNENCRYPTED_EAPOL: + profChanged = FALSE; + break; + case IW_AUTH_ROAMING_CONTROL: + profChanged = FALSE; + break; + case IW_AUTH_PRIVACY_INVOKED: + if (!value) { + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arPairwiseCryptoLen = 0; + ar->arGroupCrypto = NONE_CRYPT; + ar->arGroupCryptoLen = 0; + } + break; + default: + ret = -1; + profChanged = FALSE; + break; + } + + if (profChanged == TRUE) { + /* + * profile has changed. Erase ssid to signal change + */ + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + } + + return ret; +} + + +/* + * SIOCGIWAUTH + */ +static int +ar6000_ioctl_giwauth(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + A_UINT16 param; + A_INT32 ret; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + param = data->flags & IW_AUTH_INDEX; + ret = 0; + data->value = 0; + + + switch (param) { + case IW_AUTH_WPA_VERSION: + if (ar->arAuthMode == NONE_AUTH) { + data->value |= IW_AUTH_WPA_VERSION_DISABLED; + } else if (ar->arAuthMode == WPA_AUTH) { + data->value |= IW_AUTH_WPA_VERSION_WPA; + } else if (ar->arAuthMode == WPA2_AUTH) { + data->value |= IW_AUTH_WPA_VERSION_WPA2; + } else { + ret = -1; + } + break; + case IW_AUTH_CIPHER_PAIRWISE: + if (ar->arPairwiseCrypto == NONE_CRYPT) { + data->value |= IW_AUTH_CIPHER_NONE; + } else if (ar->arPairwiseCrypto == WEP_CRYPT) { + if (ar->arPairwiseCryptoLen == 13) { + data->value |= IW_AUTH_CIPHER_WEP104; + } else { + data->value |= IW_AUTH_CIPHER_WEP104; + } + } else if (ar->arPairwiseCrypto == TKIP_CRYPT) { + data->value |= IW_AUTH_CIPHER_TKIP; + } else if (ar->arPairwiseCrypto == AES_CRYPT) { + data->value |= IW_AUTH_CIPHER_CCMP; + } else { + ret = -1; + } + break; + case IW_AUTH_CIPHER_GROUP: + if (ar->arGroupCrypto == NONE_CRYPT) { + data->value |= IW_AUTH_CIPHER_NONE; + } else if (ar->arGroupCrypto == WEP_CRYPT) { + if (ar->arGroupCryptoLen == 13) { + data->value |= IW_AUTH_CIPHER_WEP104; + } else { + data->value |= IW_AUTH_CIPHER_WEP104; + } + } else if (ar->arGroupCrypto == TKIP_CRYPT) { + data->value |= IW_AUTH_CIPHER_TKIP; + } else if (ar->arGroupCrypto == AES_CRYPT) { + data->value |= IW_AUTH_CIPHER_CCMP; + } else { + ret = -1; + } + break; + case IW_AUTH_KEY_MGMT: + if ((ar->arAuthMode == WPA_PSK_AUTH) || + (ar->arAuthMode == WPA2_PSK_AUTH)) { + data->value |= IW_AUTH_KEY_MGMT_PSK; + } else if ((ar->arAuthMode == WPA_AUTH) || + (ar->arAuthMode == WPA2_AUTH)) { + data->value |= IW_AUTH_KEY_MGMT_802_1X; + } + break; + case IW_AUTH_TKIP_COUNTERMEASURES: + // TODO. Save countermeassure enable/disable + data->value = 0; + break; + case IW_AUTH_DROP_UNENCRYPTED: + break; + case IW_AUTH_80211_AUTH_ALG: + if (ar->arDot11AuthMode == OPEN_AUTH) { + data->value |= IW_AUTH_ALG_OPEN_SYSTEM; + } else if (ar->arDot11AuthMode == SHARED_AUTH) { + data->value |= IW_AUTH_ALG_SHARED_KEY; + } else if (ar->arDot11AuthMode == LEAP_AUTH) { + data->value |= IW_AUTH_ALG_LEAP; + } else { + ret = -1; + } + break; + case IW_AUTH_WPA_ENABLED: + if (ar->arAuthMode == NONE_AUTH) { + data->value = 0; + } else { + data->value = 1; + } + break; + case IW_AUTH_RX_UNENCRYPTED_EAPOL: + break; + case IW_AUTH_ROAMING_CONTROL: + break; + case IW_AUTH_PRIVACY_INVOKED: + if (ar->arPairwiseCrypto == NONE_CRYPT) { + data->value = 0; + } else { + data->value = 1; + } + break; + default: + ret = -1; + break; + } + + return 0; +} + +/* + * SIOCSIWPMKSA + */ +static int +ar6000_ioctl_siwpmksa(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + A_INT32 ret; + A_STATUS status; + struct iw_pmksa *pmksa; + + pmksa = (struct iw_pmksa *)extra; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + ret = 0; + status = A_OK; + + switch (pmksa->cmd) { + case IW_PMKSA_ADD: + status = wmi_setPmkid_cmd(ar->arWmi, pmksa->bssid.sa_data, pmksa->pmkid, TRUE); + break; + case IW_PMKSA_REMOVE: + status = wmi_setPmkid_cmd(ar->arWmi, pmksa->bssid.sa_data, pmksa->pmkid, FALSE); + break; + case IW_PMKSA_FLUSH: + break; + default: + ret=-1; + break; + } + if (status != A_OK) { + ret = -1; + } + + return ret; +} + +/* + * SIOCSIWENCODEEXT + */ +static int +ar6000_ioctl_siwencodeext(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + A_INT32 index; + struct iw_encode_ext *ext; + KEY_USAGE keyUsage; + A_INT32 keyLen; + A_UINT8 *keyData; + A_UINT8 keyRsc[8]; + A_STATUS status; + CRYPTO_TYPE keyType; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + index = erq->flags & IW_ENCODE_INDEX; + + if (index && (((index - 1) < WMI_MIN_KEY_INDEX) || + ((index - 1) > WMI_MAX_KEY_INDEX))) + { + return -EIO; + } + + ext = (struct iw_encode_ext *)extra; + if (erq->flags & IW_ENCODE_DISABLED) { + /* + * Encryption disabled + */ + if (index) { + /* + * If key index was specified then clear the specified key + */ + index--; + A_MEMZERO(ar->arWepKeyList[index].arKey, + sizeof(ar->arWepKeyList[index].arKey)); + ar->arWepKeyList[index].arKeyLen = 0; + } + } else { + /* + * Enabling WEP encryption + */ + if (index) { + index--; /* keyindex is off base 1 in iwconfig */ + } + + keyUsage = 0; + keyLen = erq->length - sizeof(struct iw_encode_ext); + + if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) { + keyUsage = TX_USAGE; + ar->arDefTxKeyIndex = index; + // Just setting the key index + if (keyLen == 0) { + return 0; + } + } + + if (keyLen <= 0) { + return -EIO; + } + + /* key follows iw_encode_ext */ + keyData = (A_UINT8 *)(ext + 1); + + switch (ext->alg) { + case IW_ENCODE_ALG_WEP: + keyType = WEP_CRYPT; + if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(keyLen)) { + return -EIO; + } + + // Check whether it is static wep + if (!ar->arConnected) { + A_MEMZERO(ar->arWepKeyList[index].arKey, + sizeof(ar->arWepKeyList[index].arKey)); + A_MEMCPY(ar->arWepKeyList[index].arKey, keyData, keyLen); + ar->arWepKeyList[index].arKeyLen = keyLen; + + return 0; + } + break; + case IW_ENCODE_ALG_TKIP: + keyType = TKIP_CRYPT; + break; + case IW_ENCODE_ALG_CCMP: + keyType = AES_CRYPT; + break; + default: + return -EIO; + } + + if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) { + keyUsage |= GROUP_USAGE; + } else { + keyUsage |= PAIRWISE_USAGE; + } + + if (ext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) { + A_MEMCPY(keyRsc, ext->rx_seq, sizeof(keyRsc)); + } else { + A_MEMZERO(keyRsc, sizeof(keyRsc)); + } + + status = wmi_addKey_cmd(ar->arWmi, index, keyType, keyUsage, + keyLen, keyRsc, + keyData, KEY_OP_INIT_VAL, + SYNC_BOTH_WMIFLAG); + if (status != A_OK) { + return -EIO; + } + } + + return 0; +} + +/* + * SIOCGIWENCODEEXT + */ +static int +ar6000_ioctl_giwencodeext(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arPairwiseCrypto == NONE_CRYPT) { + erq->length = 0; + erq->flags = IW_ENCODE_DISABLED; + } else { + erq->length = 0; + } + + return 0; +} +#endif // WIRELESS_EXT >= 18 + +static int +ar6000_ioctl_setparam(struct net_device *dev, + struct iw_request_info *info, + void *erq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + int *i = (int *)extra; + int param = i[0]; + int value = i[1]; + int ret = 0; + A_BOOL profChanged = FALSE; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + switch (param) { + case IEEE80211_PARAM_WPA: + switch (value) { + case WPA_MODE_WPA1: + ar->arAuthMode = WPA_AUTH; + profChanged = TRUE; + break; + case WPA_MODE_WPA2: + ar->arAuthMode = WPA2_AUTH; + profChanged = TRUE; + break; + case WPA_MODE_NONE: + ar->arAuthMode = NONE_AUTH; + profChanged = TRUE; + break; + } + break; + case IEEE80211_PARAM_AUTHMODE: + switch(value) { + case IEEE80211_AUTH_WPA_PSK: + if (WPA_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA_PSK_AUTH; + profChanged = TRUE; + } else if (WPA2_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA2_PSK_AUTH; + profChanged = TRUE; + } else { + AR_DEBUG_PRINTF("Error - Setting PSK mode when WPA "\ + "param was set to %d\n", + ar->arAuthMode); + ret = -1; + } + break; + case IEEE80211_AUTH_WPA_CCKM: + if (WPA2_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA2_AUTH_CCKM; + } else { + ar->arAuthMode = WPA_AUTH_CCKM; + } + break; + default: + break; + } + break; + case IEEE80211_PARAM_UCASTCIPHER: + switch (value) { + case IEEE80211_CIPHER_AES_CCM: + ar->arPairwiseCrypto = AES_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_TKIP: + ar->arPairwiseCrypto = TKIP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_WEP: + ar->arPairwiseCrypto = WEP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_NONE: + ar->arPairwiseCrypto = NONE_CRYPT; + profChanged = TRUE; + break; + } + break; + case IEEE80211_PARAM_UCASTKEYLEN: + if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) { + ret = -EIO; + } else { + ar->arPairwiseCryptoLen = value; + } + break; + case IEEE80211_PARAM_MCASTCIPHER: + switch (value) { + case IEEE80211_CIPHER_AES_CCM: + ar->arGroupCrypto = AES_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_TKIP: + ar->arGroupCrypto = TKIP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_WEP: + ar->arGroupCrypto = WEP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_NONE: + ar->arGroupCrypto = NONE_CRYPT; + profChanged = TRUE; + break; + } + break; + case IEEE80211_PARAM_MCASTKEYLEN: + if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) { + ret = -EIO; + } else { + ar->arGroupCryptoLen = value; + } + break; + case IEEE80211_PARAM_COUNTERMEASURES: + if (ar->arWmiReady == FALSE) { + return -EIO; + } + wmi_set_tkip_countermeasures_cmd(ar->arWmi, value); + break; + default: + break; + } + + if (profChanged == TRUE) { + /* + * profile has changed. Erase ssid to signal change + */ + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + } + + return ret; +} + +int +ar6000_ioctl_getparam(struct net_device *dev, struct iw_request_info *info, + void *w, char *extra) +{ + return -EIO; /* for now */ +} + +int +ar6000_ioctl_setkey(struct net_device *dev, struct iw_request_info *info, + void *w, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + struct ieee80211req_key *ik = (struct ieee80211req_key *)extra; + KEY_USAGE keyUsage; + A_STATUS status; + CRYPTO_TYPE keyType = NONE_CRYPT; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } +#ifdef USER_KEYS + ar->user_saved_keys.keyOk = FALSE; +#endif + + if ( 0 == memcmp(ik->ik_macaddr, "\x00\x00\x00\x00\x00\x00", + IEEE80211_ADDR_LEN)) { + keyUsage = GROUP_USAGE; +#ifdef USER_KEYS + A_MEMCPY(&ar->user_saved_keys.bcast_ik, ik, + sizeof(struct ieee80211req_key)); +#endif + } else { + keyUsage = PAIRWISE_USAGE; +#ifdef USER_KEYS + A_MEMCPY(&ar->user_saved_keys.ucast_ik, ik, + sizeof(struct ieee80211req_key)); +#endif + } + + switch (ik->ik_type) { + case IEEE80211_CIPHER_WEP: + keyType = WEP_CRYPT; + break; + case IEEE80211_CIPHER_TKIP: + keyType = TKIP_CRYPT; + break; + case IEEE80211_CIPHER_AES_CCM: + keyType = AES_CRYPT; + break; + default: + break; + } +#ifdef USER_KEYS + ar->user_saved_keys.keyType = keyType; +#endif + if (IEEE80211_CIPHER_CCKM_KRK != ik->ik_type) { + if (NONE_CRYPT == keyType) { + return -EIO; + } + + status = wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, keyUsage, + ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc, + ik->ik_keydata, KEY_OP_INIT_VAL, + SYNC_BOTH_WMIFLAG); + + if (status != A_OK) { + return -EIO; + } + } else { + status = wmi_add_krk_cmd(ar->arWmi, ik->ik_keydata); + } + +#ifdef USER_KEYS + ar->user_saved_keys.keyOk = TRUE; +#endif + + return 0; +} + + +/* + * SIOCGIWNAME + */ +int +ar6000_ioctl_giwname(struct net_device *dev, + struct iw_request_info *info, + char *name, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + switch (ar->arPhyCapability) { + case (WMI_11A_CAPABILITY): + strncpy(name, "AR6000 802.11a", IFNAMSIZ); + break; + case (WMI_11G_CAPABILITY): + strncpy(name, "AR6000 802.11g", IFNAMSIZ); + break; + case (WMI_11AG_CAPABILITY): + strncpy(name, "AR6000 802.11ag", IFNAMSIZ); + break; + default: + strncpy(name, "AR6000 802.11", IFNAMSIZ); + break; + } + + return 0; +} + +/* + * SIOCSIWFREQ + */ +int +ar6000_ioctl_siwfreq(struct net_device *dev, + struct iw_request_info *info, + struct iw_freq *freq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + /* + * We support limiting the channels via wmiconfig. + * + * We use this command to configure the channel hint for the connect cmd + * so it is possible the target will end up connecting to a different + * channel. + */ + if (freq->e > 1) { + return -EINVAL; + } else if (freq->e == 1) { + ar->arChannelHint = freq->m / 100000; + } else { + ar->arChannelHint = wlan_ieee2freq(freq->m); + } + + A_PRINTF("channel hint set to %d\n", ar->arChannelHint); + return 0; +} + +/* + * SIOCGIWFREQ + */ +int +ar6000_ioctl_giwfreq(struct net_device *dev, + struct iw_request_info *info, + struct iw_freq *freq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arConnected != TRUE) { + return -EINVAL; + } + + freq->m = ar->arBssChannel * 100000; + freq->e = 1; + + return 0; +} + +/* + * SIOCSIWMODE + */ +int +ar6000_ioctl_siwmode(struct net_device *dev, + struct iw_request_info *info, + __u32 *mode, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + /* + * clear SSID during mode switch in connected state + */ + if(!(ar->arNetworkType == (((*mode) == IW_MODE_INFRA) ? INFRA_NETWORK : ADHOC_NETWORK)) && (ar->arConnected == TRUE) ){ + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + } + + switch (*mode) { + case IW_MODE_INFRA: + ar->arNetworkType = INFRA_NETWORK; + break; + case IW_MODE_ADHOC: + ar->arNetworkType = ADHOC_NETWORK; + break; + default: + return -EINVAL; + } + + return 0; +} + +/* + * SIOCGIWMODE + */ +int +ar6000_ioctl_giwmode(struct net_device *dev, + struct iw_request_info *info, + __u32 *mode, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + switch (ar->arNetworkType) { + case INFRA_NETWORK: + *mode = IW_MODE_INFRA; + break; + case ADHOC_NETWORK: + *mode = IW_MODE_ADHOC; + break; + default: + return -EIO; + } + return 0; +} + +/* + * SIOCSIWSENS + */ +int +ar6000_ioctl_siwsens(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *sens, char *extra) +{ + return 0; +} + +/* + * SIOCGIWSENS + */ +int +ar6000_ioctl_giwsens(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *sens, char *extra) +{ + sens->value = 0; + sens->fixed = 1; + + return 0; +} + +/* + * SIOCGIWRANGE + */ +int +ar6000_ioctl_giwrange(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + struct iw_range *range = (struct iw_range *) extra; + int i, ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + ar->arNumChannels = -1; + A_MEMZERO(ar->arChannelList, sizeof (ar->arChannelList)); + + if (wmi_get_channelList_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->arNumChannels != -1, wmitimeout * HZ); + + if (signal_pending(current)) { + up(&ar->arSem); + return -EINTR; + } + + data->length = sizeof(struct iw_range); + A_MEMZERO(range, sizeof(struct iw_range)); + + range->txpower_capa = 0; + + range->min_pmp = 1 * 1024; + range->max_pmp = 65535 * 1024; + range->min_pmt = 1 * 1024; + range->max_pmt = 1000 * 1024; + range->pmp_flags = IW_POWER_PERIOD; + range->pmt_flags = IW_POWER_TIMEOUT; + range->pm_capa = 0; + + range->we_version_compiled = WIRELESS_EXT; + range->we_version_source = 13; + + range->retry_capa = IW_RETRY_LIMIT; + range->retry_flags = IW_RETRY_LIMIT; + range->min_retry = 0; + range->max_retry = 255; + + range->num_frequency = range->num_channels = ar->arNumChannels; + for (i = 0; i < ar->arNumChannels; i++) { + range->freq[i].i = wlan_freq2ieee(ar->arChannelList[i]); + range->freq[i].m = ar->arChannelList[i] * 100000; + range->freq[i].e = 1; + /* + * Linux supports max of 32 channels, bail out once you + * reach the max. + */ + if (i == IW_MAX_FREQUENCIES) { + break; + } + } + + /* Max quality is max field value minus noise floor */ + range->max_qual.qual = 0xff - 161; + + /* + * In order to use dBm measurements, 'level' must be lower + * than any possible measurement (see iw_print_stats() in + * wireless tools). It's unclear how this is meant to be + * done, but setting zero in these values forces dBm and + * the actual numbers are not used. + */ + range->max_qual.level = 0; + range->max_qual.noise = 0; + + range->sensitivity = 3; + + range->max_encoding_tokens = 4; + /* XXX query driver to find out supported key sizes */ + range->num_encoding_sizes = 3; + range->encoding_size[0] = 5; /* 40-bit */ + range->encoding_size[1] = 13; /* 104-bit */ + range->encoding_size[2] = 16; /* 128-bit */ + + range->num_bitrates = 0; + + /* estimated maximum TCP throughput values (bps) */ + range->throughput = 22000000; + + range->min_rts = 0; + range->max_rts = 2347; + range->min_frag = 256; + range->max_frag = 2346; + + up(&ar->arSem); + + return ret; +} + + +/* + * SIOCSIWAP + * This ioctl is used to set the desired bssid for the connect command. + */ +int +ar6000_ioctl_siwap(struct net_device *dev, + struct iw_request_info *info, + struct sockaddr *ap_addr, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ap_addr->sa_family != ARPHRD_ETHER) { + return -EIO; + } + + if (A_MEMCMP(&ap_addr->sa_data, bcast_mac, AR6000_ETH_ADDR_LEN) == 0) { + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + } else { + A_MEMCPY(ar->arReqBssid, &ap_addr->sa_data, sizeof(ar->arReqBssid)); + } + + return 0; +} + +/* + * SIOCGIWAP + */ +int +ar6000_ioctl_giwap(struct net_device *dev, + struct iw_request_info *info, + struct sockaddr *ap_addr, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arConnected != TRUE) { + return -EINVAL; + } + + A_MEMCPY(&ap_addr->sa_data, ar->arBssid, sizeof(ar->arBssid)); + ap_addr->sa_family = ARPHRD_ETHER; + + return 0; +} + +/* + * SIOCGIWAPLIST + */ +int +ar6000_ioctl_iwaplist(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + return -EIO; /* for now */ +} + +/* + * SIOCGIWSCAN + */ +int +ar6000_ioctl_siwscan(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ +#define ACT_DWELLTIME_DEFAULT 105 +#define HOME_TXDRAIN_TIME 100 +#define SCAN_INT HOME_TXDRAIN_TIME + ACT_DWELLTIME_DEFAULT + AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (!ar->arUserBssFilter) { + if (wmi_bssfilter_cmd(ar->arWmi, (ar->arConnected ? ALL_BUT_BSS_FILTER : ALL_BSS_FILTER), 0) != A_OK) { + return -EIO; + } + } + + if (ar->arConnected) { + if (wmi_get_stats_cmd(ar->arWmi) != A_OK) { + return -EIO; + } + } + + if (wmi_startscan_cmd(ar->arWmi, WMI_LONG_SCAN, FALSE, FALSE, \ + HOME_TXDRAIN_TIME, SCAN_INT, 0, NULL) != A_OK) { + ret = -EIO; + } + + return ret; +#undef ACT_DWELLTIME_DEFAULT +#undef HOME_TXDRAIN_TIME +#undef SCAN_INT +} + + +/* + * Units are in db above the noise floor. That means the + * rssi values reported in the tx/rx descriptors in the + * driver are the SNR expressed in db. + * + * If you assume that the noise floor is -95, which is an + * excellent assumption 99.5 % of the time, then you can + * derive the absolute signal level (i.e. -95 + rssi). + * There are some other slight factors to take into account + * depending on whether the rssi measurement is from 11b, + * 11g, or 11a. These differences are at most 2db and + * can be documented. + * + * NB: various calculations are based on the orinoco/wavelan + * drivers for compatibility + */ +static void +ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi) +{ + if (rssi < 0) { + iq->qual = 0; + } else { + iq->qual = rssi; + } + + /* NB: max is 94 because noise is hardcoded to 161 */ + if (iq->qual > 94) + iq->qual = 94; + + iq->noise = 161; /* -95dBm */ + iq->level = iq->noise + iq->qual; + iq->updated = 7; +} + + +/* Structures to export the Wireless Handlers */ +static const iw_handler ath_handlers[] = { + (iw_handler) NULL, /* SIOCSIWCOMMIT */ + (iw_handler) ar6000_ioctl_giwname, /* SIOCGIWNAME */ + (iw_handler) NULL, /* SIOCSIWNWID */ + (iw_handler) NULL, /* SIOCGIWNWID */ + (iw_handler) ar6000_ioctl_siwfreq, /* SIOCSIWFREQ */ + (iw_handler) ar6000_ioctl_giwfreq, /* SIOCGIWFREQ */ + (iw_handler) ar6000_ioctl_siwmode, /* SIOCSIWMODE */ + (iw_handler) ar6000_ioctl_giwmode, /* SIOCGIWMODE */ + (iw_handler) ar6000_ioctl_siwsens, /* SIOCSIWSENS */ + (iw_handler) ar6000_ioctl_giwsens, /* SIOCGIWSENS */ + (iw_handler) NULL /* not _used */, /* SIOCSIWRANGE */ + (iw_handler) ar6000_ioctl_giwrange, /* SIOCGIWRANGE */ + (iw_handler) NULL /* not used */, /* SIOCSIWPRIV */ + (iw_handler) NULL /* kernel code */, /* SIOCGIWPRIV */ + (iw_handler) NULL /* not used */, /* SIOCSIWSTATS */ + (iw_handler) NULL /* kernel code */, /* SIOCGIWSTATS */ + (iw_handler) NULL, /* SIOCSIWSPY */ + (iw_handler) NULL, /* SIOCGIWSPY */ + (iw_handler) NULL, /* SIOCSIWTHRSPY */ + (iw_handler) NULL, /* SIOCGIWTHRSPY */ + (iw_handler) ar6000_ioctl_siwap, /* SIOCSIWAP */ + (iw_handler) ar6000_ioctl_giwap, /* SIOCGIWAP */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) ar6000_ioctl_iwaplist, /* SIOCGIWAPLIST */ + (iw_handler) ar6000_ioctl_siwscan, /* SIOCSIWSCAN */ + (iw_handler) ar6000_ioctl_giwscan, /* SIOCGIWSCAN */ + (iw_handler) ar6000_ioctl_siwessid, /* SIOCSIWESSID */ + (iw_handler) ar6000_ioctl_giwessid, /* SIOCGIWESSID */ + (iw_handler) NULL, /* SIOCSIWNICKN */ + (iw_handler) NULL, /* SIOCGIWNICKN */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) ar6000_ioctl_siwrate, /* SIOCSIWRATE */ + (iw_handler) ar6000_ioctl_giwrate, /* SIOCGIWRATE */ + (iw_handler) NULL, /* SIOCSIWRTS */ + (iw_handler) NULL, /* SIOCGIWRTS */ + (iw_handler) NULL, /* SIOCSIWFRAG */ + (iw_handler) NULL, /* SIOCGIWFRAG */ + (iw_handler) ar6000_ioctl_siwtxpow, /* SIOCSIWTXPOW */ + (iw_handler) ar6000_ioctl_giwtxpow, /* SIOCGIWTXPOW */ + (iw_handler) ar6000_ioctl_siwretry, /* SIOCSIWRETRY */ + (iw_handler) ar6000_ioctl_giwretry, /* SIOCGIWRETRY */ + (iw_handler) ar6000_ioctl_siwencode, /* SIOCSIWENCODE */ + (iw_handler) ar6000_ioctl_giwencode, /* SIOCGIWENCODE */ + (iw_handler) NULL, /* SIOCSIWPOWER */ + (iw_handler) NULL, /* SIOCGIWPOWER */ +#if WIRELESS_EXT >= 18 + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) ar6000_ioctl_siwgenie, /* SIOCSIWGENIE */ + (iw_handler) ar6000_ioctl_giwgenie, /* SIOCGIWGENIE */ + (iw_handler) ar6000_ioctl_siwauth, /* SIOCSIWAUTH */ + (iw_handler) ar6000_ioctl_giwauth, /* SIOCGIWAUTH */ + (iw_handler) ar6000_ioctl_siwencodeext, /* SIOCSIWENCODEEXT */ + (iw_handler) ar6000_ioctl_giwencodeext, /* SIOCGIWENCODEEXT */ + (iw_handler) ar6000_ioctl_siwpmksa, /* SIOCSIWPMKSA */ +#endif // WIRELESS_EXT >= 18 +}; + +static const iw_handler ath_priv_handlers[] = { + (iw_handler) ar6000_ioctl_setparam, /* SIOCWFIRSTPRIV+0 */ + (iw_handler) ar6000_ioctl_getparam, /* SIOCWFIRSTPRIV+1 */ + (iw_handler) ar6000_ioctl_setkey, /* SIOCWFIRSTPRIV+2 */ + (iw_handler) ar6000_ioctl_setwmmparams, /* SIOCWFIRSTPRIV+3 */ + (iw_handler) ar6000_ioctl_delkey, /* SIOCWFIRSTPRIV+4 */ + (iw_handler) ar6000_ioctl_getwmmparams, /* SIOCWFIRSTPRIV+5 */ + (iw_handler) NULL, /* SIOCWFIRSTPRIV+6 */ + (iw_handler) NULL, /* SIOCWFIRSTPRIV+7 */ + (iw_handler) ar6000_ioctl_addpmkid, /* SIOCWFIRSTPRIV+8 */ + (iw_handler) NULL, /* SIOCWFIRSTPRIV+9 */ +#ifdef NOT_YET + (iw_handler) ar6000_ioctl_setauthalg, /* SIOCWFIRSTPRIV+10 */ +#endif +}; + + +#define IW_PRIV_TYPE_KEY \ + (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_key)) +#define IW_PRIV_TYPE_DELKEY \ + (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_del_key)) +#define IW_PRIV_TYPE_MLME \ + (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_mlme)) +#define IW_PRIV_TYPE_ADDPMKID \ + (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_addpmkid)) + +static const struct iw_priv_args ar6000_priv_args[] = { + { IEEE80211_IOCTL_SETKEY, + IW_PRIV_TYPE_KEY | IW_PRIV_SIZE_FIXED, 0, "setkey"}, + { IEEE80211_IOCTL_DELKEY, + IW_PRIV_TYPE_DELKEY | IW_PRIV_SIZE_FIXED, 0, "delkey"}, + { IEEE80211_IOCTL_SETPARAM, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "setparam"}, + { IEEE80211_IOCTL_GETPARAM, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "getparam"}, + { IEEE80211_IOCTL_SETWMMPARAMS, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 4, 0, "setwmmparams"}, + { IEEE80211_IOCTL_GETWMMPARAMS, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 3, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "getwmmparams"}, + { IEEE80211_IOCTL_ADDPMKID, + IW_PRIV_TYPE_ADDPMKID | IW_PRIV_SIZE_FIXED, 0, "addpmkid"}, +}; + +void ar6000_ioctl_iwsetup(struct iw_handler_def *def) +{ +#define N(a) (sizeof(a) / sizeof(a[0])) + def->private_args = (struct iw_priv_args *)ar6000_priv_args; + def->num_private_args = N(ar6000_priv_args); +#undef N +} + +struct iw_handler_def ath_iw_handler_def = { +#define N(a) (sizeof (a) / sizeof (a[0])) + .standard = (iw_handler *)ath_handlers, + .num_standard = N(ath_handlers), + .private = (iw_handler *)ath_priv_handlers, + .num_private = N(ath_priv_handlers), +#undef N +}; diff -urN linux-2.6.26/drivers/net/wireless/ar6000/wlan_node.c linux-2.6.26-lab126/drivers/net/wireless/ar6000/wlan_node.c --- linux-2.6.26/drivers/net/wireless/ar6000/wlan_node.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/wlan_node.c 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,467 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// IEEE 802.11 node handling support. +// +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void wlan_node_timeout(A_ATH_TIMER arg); +static bss_t * _ieee80211_find_node(struct ieee80211_node_table *nt, + const A_UINT8 *macaddr); + +bss_t * +wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size) +{ + bss_t *ni; + + ni = A_MALLOC_NOWAIT(sizeof(bss_t)); + + if (ni != NULL) { + if (wh_size) + { + ni->ni_buf = A_MALLOC_NOWAIT(wh_size); + if (ni->ni_buf == NULL) { + A_FREE(ni); + ni = NULL; + return ni; + } + } + } else { + return ni; + } + + /* Make sure our lists are clean */ + ni->ni_list_next = NULL; + ni->ni_list_prev = NULL; + ni->ni_hash_next = NULL; + ni->ni_hash_prev = NULL; + + // + // ni_scangen never initialized before and during suspend/resume of winmobile, + // that some junk has been stored in this, due to this scan list didn't properly updated + // + ni->ni_scangen = 0; + +#ifdef OS_ROAM_MANAGEMENT + ni->ni_si_gen = 0; +#endif + + return ni; +} + +void +wlan_node_free(bss_t *ni) +{ + if (ni->ni_buf != NULL) { + A_FREE(ni->ni_buf); + } + A_FREE(ni); +} + +void +wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni, + const A_UINT8 *macaddr) +{ + int hash; + A_UINT32 timeoutValue = 0; + + A_MEMCPY(ni->ni_macaddr, macaddr, IEEE80211_ADDR_LEN); + hash = IEEE80211_NODE_HASH(macaddr); + ieee80211_node_initref(ni); /* mark referenced */ + + timeoutValue = nt->nt_nodeAge; + ni->ni_tstamp = A_GET_MS(timeoutValue); + IEEE80211_NODE_LOCK_BH(nt); + + /* Insert at the end of the node list */ + ni->ni_list_next = NULL; + ni->ni_list_prev = nt->nt_node_last; + if(nt->nt_node_last != NULL) + { + nt->nt_node_last->ni_list_next = ni; + } + nt->nt_node_last = ni; + if(nt->nt_node_first == NULL) + { + nt->nt_node_first = ni; + } + + /* Insert into the hash list i.e. the bucket */ + if((ni->ni_hash_next = nt->nt_hash[hash]) != NULL) + { + nt->nt_hash[hash]->ni_hash_prev = ni; + } + ni->ni_hash_prev = NULL; + nt->nt_hash[hash] = ni; + + if (!nt->isTimerArmed) { + A_TIMEOUT_MS(&nt->nt_inact_timer, timeoutValue, 0); + nt->isTimerArmed = TRUE; + } + + IEEE80211_NODE_UNLOCK_BH(nt); +} + +static bss_t * +_ieee80211_find_node(struct ieee80211_node_table *nt, + const A_UINT8 *macaddr) +{ + bss_t *ni; + int hash; + + IEEE80211_NODE_LOCK_ASSERT(nt); + + hash = IEEE80211_NODE_HASH(macaddr); + for(ni = nt->nt_hash[hash]; ni; ni = ni->ni_hash_next) { + if (IEEE80211_ADDR_EQ(ni->ni_macaddr, macaddr)) { + ieee80211_node_incref(ni); /* mark referenced */ + return ni; + } + } + return NULL; +} + +bss_t * +wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr) +{ + bss_t *ni; + + IEEE80211_NODE_LOCK(nt); + ni = _ieee80211_find_node(nt, macaddr); + IEEE80211_NODE_UNLOCK(nt); + return ni; +} + +/* + * Reclaim a node. If this is the last reference count then + * do the normal free work. Otherwise remove it from the node + * table and mark it gone by clearing the back-reference. + */ +void +wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni) +{ + IEEE80211_NODE_LOCK(nt); + + if(ni->ni_list_prev == NULL) + { + /* First in list so fix the list head */ + nt->nt_node_first = ni->ni_list_next; + } + else + { + ni->ni_list_prev->ni_list_next = ni->ni_list_next; + } + + if(ni->ni_list_next == NULL) + { + /* Last in list so fix list tail */ + nt->nt_node_last = ni->ni_list_prev; + } + else + { + ni->ni_list_next->ni_list_prev = ni->ni_list_prev; + } + + if(ni->ni_hash_prev == NULL) + { + /* First in list so fix the list head */ + int hash; + hash = IEEE80211_NODE_HASH(ni->ni_macaddr); + nt->nt_hash[hash] = ni->ni_hash_next; + } + else + { + ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next; + } + + if(ni->ni_hash_next != NULL) + { + ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev; + } + wlan_node_free(ni); + + IEEE80211_NODE_UNLOCK(nt); +} + +static void +wlan_node_dec_free(bss_t *ni) +{ + if (ieee80211_node_dectestref(ni)) { + wlan_node_free(ni); + } +} + +void +wlan_free_allnodes(struct ieee80211_node_table *nt) +{ + bss_t *ni; + + while ((ni = nt->nt_node_first) != NULL) { + wlan_node_reclaim(nt, ni); + } +} + +void +wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f, + void *arg) +{ + bss_t *ni; + A_UINT32 gen; + + gen = ++nt->nt_scangen; + + IEEE80211_NODE_LOCK(nt); + for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) { + if (ni->ni_scangen != gen) { + ni->ni_scangen = gen; + (void) ieee80211_node_incref(ni); + (*f)(arg, ni); + wlan_node_dec_free(ni); + } + } + IEEE80211_NODE_UNLOCK(nt); +} + +/* + * Node table support. + */ +void +wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt) +{ + int i; + + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN, ("node table = 0x%x\n", (A_UINT32)nt)); + IEEE80211_NODE_LOCK_INIT(nt); + + nt->nt_node_first = nt->nt_node_last = NULL; + for(i = 0; i < IEEE80211_NODE_HASHSIZE; i++) + { + nt->nt_hash[i] = NULL; + } + A_INIT_TIMER(&nt->nt_inact_timer, wlan_node_timeout, nt); + nt->isTimerArmed = FALSE; + nt->nt_wmip = wmip; + nt->nt_nodeAge = WLAN_NODE_INACT_TIMEOUT_MSEC; + + // + // nt_scangen never initialized before and during suspend/resume of winmobile, customer (LG/SEMCO) identified + // that some junk has been stored in this, due to this scan list didn't properly updated + // + nt->nt_scangen = 0; + +#ifdef OS_ROAM_MANAGEMENT + nt->nt_si_gen = 0; +#endif +} + +void +wlan_set_nodeage(struct ieee80211_node_table *nt, A_UINT32 nodeAge) +{ + nt->nt_nodeAge = nodeAge; + return; +} + +static void +wlan_node_timeout(A_ATH_TIMER arg) +{ + struct ieee80211_node_table *nt = (struct ieee80211_node_table *)arg; + bss_t *bss, *nextBss; + A_UINT8 myBssid[IEEE80211_ADDR_LEN], reArmTimer = FALSE; + A_UINT32 timeoutValue = 0; + + timeoutValue = nt->nt_nodeAge; + + wmi_get_current_bssid(nt->nt_wmip, myBssid); + + bss = nt->nt_node_first; + while (bss != NULL) + { + nextBss = bss->ni_list_next; + if (A_MEMCMP(myBssid, bss->ni_macaddr, sizeof(myBssid)) != 0) + { + + if (bss->ni_tstamp <= A_GET_MS(0)) + { + /* + * free up all but the current bss - if set + */ + wlan_node_reclaim(nt, bss); + } + else + { + /* + * Re-arm timer, only when we have a bss other than + * current bss AND it is not aged-out. + */ + reArmTimer = TRUE; + } + } + bss = nextBss; + } + + if(reArmTimer) + A_TIMEOUT_MS(&nt->nt_inact_timer, timeoutValue, 0); + + nt->isTimerArmed = reArmTimer; +} + +void +wlan_node_table_cleanup(struct ieee80211_node_table *nt) +{ + A_UNTIMEOUT(&nt->nt_inact_timer); + A_DELETE_TIMER(&nt->nt_inact_timer); + wlan_free_allnodes(nt); + IEEE80211_NODE_LOCK_DESTROY(nt); +} + +bss_t * +wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID) +{ + bss_t *ni = NULL; + A_UCHAR *pIESsid = NULL; + + IEEE80211_NODE_LOCK (nt); + + for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) { + pIESsid = ni->ni_cie.ie_ssid; + if (pIESsid[1] <= 32) { + + // Step 1 : Check SSID + if (0x00 == memcmp (pSsid, &pIESsid[2], ssidLength)) { + + // + // Step 2.1 : Check MatchSSID is TRUE, if so, return Matched SSID + // Profile, otherwise check whether WPA2 or WPA + // + if (TRUE == bMatchSSID) { + ieee80211_node_incref (ni); /* mark referenced */ + IEEE80211_NODE_UNLOCK (nt); + return ni; + } + + // Step 2 : if SSID matches, check WPA or WPA2 + if (TRUE == bIsWPA2 && NULL != ni->ni_cie.ie_rsn) { + ieee80211_node_incref (ni); /* mark referenced */ + IEEE80211_NODE_UNLOCK (nt); + return ni; + } + if (FALSE == bIsWPA2 && NULL != ni->ni_cie.ie_wpa) { + ieee80211_node_incref(ni); /* mark referenced */ + IEEE80211_NODE_UNLOCK (nt); + return ni; + } + } + } + } + + IEEE80211_NODE_UNLOCK (nt); + + return NULL; +} + +void +wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni) +{ + IEEE80211_NODE_LOCK (nt); + wlan_node_dec_free (ni); + IEEE80211_NODE_UNLOCK (nt); +} + +void +wlan_node_remove_core (struct ieee80211_node_table *nt, bss_t *ni) +{ + if(ni->ni_list_prev == NULL) + { + /* First in list so fix the list head */ + nt->nt_node_first = ni->ni_list_next; + } + else + { + ni->ni_list_prev->ni_list_next = ni->ni_list_next; + } + + if(ni->ni_list_next == NULL) + { + /* Last in list so fix list tail */ + nt->nt_node_last = ni->ni_list_prev; + } + else + { + ni->ni_list_next->ni_list_prev = ni->ni_list_prev; + } + + if(ni->ni_hash_prev == NULL) + { + /* First in list so fix the list head */ + int hash; + hash = IEEE80211_NODE_HASH(ni->ni_macaddr); + nt->nt_hash[hash] = ni->ni_hash_next; + } + else + { + ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next; + } + + if(ni->ni_hash_next != NULL) + { + ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev; + } +} + +bss_t * +wlan_node_remove(struct ieee80211_node_table *nt, A_UINT8 *bssid) +{ + bss_t *bss, *nextBss; + + IEEE80211_NODE_LOCK(nt); + + bss = nt->nt_node_first; + + while (bss != NULL) + { + nextBss = bss->ni_list_next; + + if (A_MEMCMP(bssid, bss->ni_macaddr, 6) == 0) + { + wlan_node_remove_core (nt, bss); + IEEE80211_NODE_UNLOCK(nt); + return bss; + } + + bss = nextBss; + } + + IEEE80211_NODE_UNLOCK(nt); + return NULL; +} diff -urN linux-2.6.26/drivers/net/wireless/ar6000/wlan_recv_beacon.c linux-2.6.26-lab126/drivers/net/wireless/ar6000/wlan_recv_beacon.c --- linux-2.6.26/drivers/net/wireless/ar6000/wlan_recv_beacon.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/wlan_recv_beacon.c 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,185 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// IEEE 802.11 input handling. +// +// Author(s): ="Atheros" +//============================================================================== + +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include +#include +#include + +#define IEEE80211_VERIFY_LENGTH(_len, _minlen) do { \ + if ((_len) < (_minlen)) { \ + return A_EINVAL; \ + } \ +} while (0) + +#define IEEE80211_VERIFY_ELEMENT(__elem, __maxlen) do { \ + if ((__elem) == NULL) { \ + return A_EINVAL; \ + } \ + if ((__elem)[1] > (__maxlen)) { \ + return A_EINVAL; \ + } \ +} while (0) + + +/* unaligned little endian access */ +#define LE_READ_2(p) \ + ((A_UINT16) \ + ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8))) + +#define LE_READ_4(p) \ + ((A_UINT32) \ + ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8) | \ + (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24))) + + +static int __inline +iswpaoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((WPA_OUI_TYPE<<24)|WPA_OUI); +} + +static int __inline +iswmmoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((WMM_OUI_TYPE<<24)|WMM_OUI); +} + +/* unused functions for now */ +#if 0 +static int __inline +iswmmparam(const A_UINT8 *frm) +{ + return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE; +} + +static int __inline +iswmminfo(const A_UINT8 *frm) +{ + return frm[1] > 5 && frm[6] == WMM_INFO_OUI_SUBTYPE; +} +#endif + +static int __inline +isatherosoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((ATH_OUI_TYPE<<24)|ATH_OUI); +} + +static int __inline +iswscoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((0x04<<24)|WPA_OUI); +} + +A_STATUS +wlan_parse_beacon(A_UINT8 *buf, int framelen, struct ieee80211_common_ie *cie) +{ + A_UINT8 *frm, *efrm; + + frm = buf; + efrm = (A_UINT8 *) (frm + framelen); + + /* + * beacon/probe response frame format + * [8] time stamp + * [2] beacon interval + * [2] capability information + * [tlv] ssid + * [tlv] supported rates + * [tlv] country information + * [tlv] parameter set (FH/DS) + * [tlv] erp information + * [tlv] extended supported rates + * [tlv] WMM + * [tlv] WPA or RSN + * [tlv] Atheros Advanced Capabilities + */ + IEEE80211_VERIFY_LENGTH(efrm - frm, 12); + A_MEMZERO(cie, sizeof(*cie)); + + cie->ie_tstamp = frm; frm += 8; + cie->ie_beaconInt = A_LE2CPU16(*(A_UINT16 *)frm); frm += 2; + cie->ie_capInfo = A_LE2CPU16(*(A_UINT16 *)frm); frm += 2; + cie->ie_chan = 0; + + while (frm < efrm) { + switch (*frm) { + case IEEE80211_ELEMID_SSID: + cie->ie_ssid = frm; + break; + case IEEE80211_ELEMID_RATES: + cie->ie_rates = frm; + break; + case IEEE80211_ELEMID_COUNTRY: + cie->ie_country = frm; + break; + case IEEE80211_ELEMID_FHPARMS: + break; + case IEEE80211_ELEMID_DSPARMS: + cie->ie_chan = frm[2]; + break; + case IEEE80211_ELEMID_TIM: + cie->ie_tim = frm; + break; + case IEEE80211_ELEMID_IBSSPARMS: + break; + case IEEE80211_ELEMID_XRATES: + cie->ie_xrates = frm; + break; + case IEEE80211_ELEMID_ERP: + if (frm[1] != 1) { + //A_PRINTF("Discarding ERP Element - Bad Len\n"); + return A_EINVAL; + } + cie->ie_erp = frm[2]; + break; + case IEEE80211_ELEMID_RSN: + cie->ie_rsn = frm; + break; + case IEEE80211_ELEMID_VENDOR: + if (iswpaoui(frm)) { + cie->ie_wpa = frm; + } else if (iswmmoui(frm)) { + cie->ie_wmm = frm; + } else if (isatherosoui(frm)) { + cie->ie_ath = frm; + } else if(iswscoui(frm)) { + cie->ie_wsc = frm; + } + break; + default: + break; + } + frm += frm[1] + 2; + } + IEEE80211_VERIFY_ELEMENT(cie->ie_rates, IEEE80211_RATE_MAXSIZE); + IEEE80211_VERIFY_ELEMENT(cie->ie_ssid, IEEE80211_NWID_LEN); + + return A_OK; +} diff -urN linux-2.6.26/drivers/net/wireless/ar6000/wlan_utils.c linux-2.6.26-lab126/drivers/net/wireless/ar6000/wlan_utils.c --- linux-2.6.26/drivers/net/wireless/ar6000/wlan_utils.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/wlan_utils.c 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,61 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This module implements frequently used wlan utilies +// +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include + +/* + * converts ieee channel number to frequency + */ +A_UINT16 +wlan_ieee2freq(int chan) +{ + if (chan == 14) { + return 2484; + } + if (chan < 14) { /* 0-13 */ + return (2407 + (chan*5)); + } + if (chan < 27) { /* 15-26 */ + return (2512 + ((chan-15)*20)); + } + return (5000 + (chan*5)); +} + +/* + * Converts MHz frequency to IEEE channel number. + */ +A_UINT32 +wlan_freq2ieee(A_UINT16 freq) +{ + if (freq == 2484) + return 14; + if (freq < 2484) + return (freq - 2407) / 5; + if (freq < 5000) + return 15 + ((freq - 2512) / 20); + return (freq - 5000) / 5; +} diff -urN linux-2.6.26/drivers/net/wireless/ar6000/wmi.c linux-2.6.26-lab126/drivers/net/wireless/ar6000/wmi.c --- linux-2.6.26/drivers/net/wireless/ar6000/wmi.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ar6000/wmi.c 2010-08-10 04:16:46.000000000 -0400 @@ -0,0 +1,4780 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This module implements the hardware independent layer of the +// Wireless Module Interface (WMI) protocol. +// +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include +#include "htc.h" +#include "htc_api.h" +#include "wmi.h" +#include +#include +#include +#include +#include "dset_api.h" +#include "gpio_api.h" +#include "wmi_host.h" +#include "a_drv.h" +#include "a_drv_api.h" +#include "a_debug.h" +#include "dbglog_api.h" +#include "roaming.h" + +static A_STATUS wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_sync_point(struct wmi_t *wmip); + +static A_STATUS wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); + +static A_STATUS wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +#ifdef CONFIG_HOST_DSET_SUPPORT +static A_STATUS wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +#endif /* CONFIG_HOST_DSET_SUPPORT */ + + +static A_STATUS wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_channel_change_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS +wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len); + +#ifdef CONFIG_HOST_GPIO_SUPPORT +static A_STATUS wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +#ifdef CONFIG_HOST_TCMD_SUPPORT +static A_STATUS +wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +#endif + +static A_STATUS +wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS +wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS +wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_BOOL +wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_INT32 rateIndex); + +static A_STATUS +wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS +wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +A_STATUS wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMIX_COMMAND_ID cmdId, + WMI_SYNC_FLAG syncflag); + +static A_UINT8 ar6000_determine_userPriority( A_UINT8 *pkt, A_UINT32 layer2Pri); + +A_UINT8 ar6000_get_upper_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, A_UINT32 size); +A_UINT8 ar6000_get_lower_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, A_UINT32 size); + +void wmi_cache_configure_rssithreshold(struct wmi_t *wmip, WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd); +void wmi_cache_configure_snrthreshold(struct wmi_t *wmip, WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd); +static A_STATUS wmi_send_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd); +static A_STATUS wmi_send_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd); +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +static A_STATUS +wmi_prof_count_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + +int wps_enable; +static const A_INT32 wmi_rateTable[] = { + 1000, + 2000, + 5500, + 11000, + 6000, + 9000, + 12000, + 18000, + 24000, + 36000, + 48000, + 54000, + 0}; + +#define MODE_A_SUPPORT_RATE_START ((A_INT32) 4) +#define MODE_A_SUPPORT_RATE_STOP ((A_INT32) 11) + +#define MODE_GONLY_SUPPORT_RATE_START MODE_A_SUPPORT_RATE_START +#define MODE_GONLY_SUPPORT_RATE_STOP MODE_A_SUPPORT_RATE_STOP + +#define MODE_B_SUPPORT_RATE_START ((A_INT32) 0) +#define MODE_B_SUPPORT_RATE_STOP ((A_INT32) 3) + +#define MODE_G_SUPPORT_RATE_START ((A_INT32) 0) +#define MODE_G_SUPPORT_RATE_STOP ((A_INT32) 11) + +#define MAX_NUMBER_OF_SUPPORT_RATES (MODE_G_SUPPORT_RATE_STOP + 1) + +/* 802.1d to AC mapping. Refer pg 57 of WMM-test-plan-v1.2 */ +const A_UINT8 up_to_ac[]= { + WMM_AC_BE, + WMM_AC_BK, + WMM_AC_BK, + WMM_AC_BE, + WMM_AC_VI, + WMM_AC_VI, + WMM_AC_VO, + WMM_AC_VO, + }; + +#include "athstartpack.h" + +/* This stuff is used when we want a simple layer-3 visibility */ +typedef PREPACK struct _iphdr { + A_UINT8 ip_ver_hdrlen; /* version and hdr length */ + A_UINT8 ip_tos; /* type of service */ + A_UINT16 ip_len; /* total length */ + A_UINT16 ip_id; /* identification */ + A_INT16 ip_off; /* fragment offset field */ +#define IP_DF 0x4000 /* dont fragment flag */ +#define IP_MF 0x2000 /* more fragments flag */ +#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */ + A_UINT8 ip_ttl; /* time to live */ + A_UINT8 ip_p; /* protocol */ + A_UINT16 ip_sum; /* checksum */ + A_UINT8 ip_src[4]; /* source and dest address */ + A_UINT8 ip_dst[4]; +} POSTPACK iphdr; + +#include "athendpack.h" + + +void * +wmi_init(void *devt) +{ + struct wmi_t *wmip; + + wmip = A_MALLOC(sizeof(struct wmi_t)); + if (wmip == NULL) { + return (NULL); + } + A_MEMZERO(wmip, sizeof(*wmip)); + A_MUTEX_INIT(&wmip->wmi_lock); + wmip->wmi_devt = devt; + wlan_node_table_init(wmip, &wmip->wmi_scan_table); + wmi_qos_state_init(wmip); + wmip->wmi_powerMode = REC_POWER; + wmip->wmi_phyMode = WMI_11G_MODE; + + return (wmip); +} + +void +wmi_qos_state_init(struct wmi_t *wmip) +{ + A_UINT8 i; + + if (wmip == NULL) { + return; + } + LOCK_WMI(wmip); + + /* Initialize QoS States */ + wmip->wmi_numQoSStream = 0; + + wmip->wmi_fatPipeExists = 0; + + for (i=0; i < WMM_NUM_AC; i++) { + wmip->wmi_streamExistsForAC[i]=0; + } + + UNLOCK_WMI(wmip); + + A_WMI_SET_NUMDATAENDPTS(wmip->wmi_devt, 1); +} + +void +wmi_set_control_ep(struct wmi_t * wmip, HTC_ENDPOINT_ID eid) +{ + A_ASSERT( eid != ENDPOINT_UNUSED); + wmip->wmi_endpoint_id = eid; +} + +HTC_ENDPOINT_ID +wmi_get_control_ep(struct wmi_t * wmip) +{ + return(wmip->wmi_endpoint_id); +} + +void +wmi_shutdown(struct wmi_t *wmip) +{ + if (wmip != NULL) { + wlan_node_table_cleanup(&wmip->wmi_scan_table); + if (A_IS_MUTEX_VALID(&wmip->wmi_lock)) { + A_MUTEX_DELETE(&wmip->wmi_lock); + } + A_FREE(wmip); + } +} + +/* + * performs DIX to 802.3 encapsulation for transmit packets. + * uses passed in buffer. Returns buffer or NULL if failed. + * Assumes the entire DIX header is contigous and that there is + * enough room in the buffer for a 802.3 mac header and LLC+SNAP headers. + */ +A_STATUS +wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf) +{ + A_UINT8 *datap; + A_UINT16 typeorlen; + ATH_MAC_HDR macHdr; + ATH_LLC_SNAP_HDR *llcHdr; + + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_HEADROOM(osbuf) < + (sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR))) + { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + typeorlen = *(A_UINT16 *)(datap + ATH_MAC_LEN + ATH_MAC_LEN); + + if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) { + /* + * packet is already in 802.3 format - return success + */ + A_DPRINTF(DBG_WMI, (DBGFMT "packet already 802.3\n", DBGARG)); + return (A_OK); + } + + /* + * Save mac fields and length to be inserted later + */ + A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN); + A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN); + macHdr.typeOrLen = A_CPU2BE16(A_NETBUF_LEN(osbuf) - sizeof(ATH_MAC_HDR) + + sizeof(ATH_LLC_SNAP_HDR)); + + /* + * Make room for LLC+SNAP headers + */ + if (A_NETBUF_PUSH(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR)); + + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR)); + llcHdr->dsap = 0xAA; + llcHdr->ssap = 0xAA; + llcHdr->cntl = 0x03; + llcHdr->orgCode[0] = 0x0; + llcHdr->orgCode[1] = 0x0; + llcHdr->orgCode[2] = 0x0; + llcHdr->etherType = typeorlen; + + return (A_OK); +} + +/* + * Adds a WMI data header + * Assumes there is enough room in the buffer to add header. + */ +A_STATUS +wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType) +{ + WMI_DATA_HDR *dtHdr; + + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf); + dtHdr->info = msgType; + dtHdr->rssi = 0; + + return (A_OK); +} + +A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT32 layer2Priority, A_BOOL wmmEnabled) +{ + A_UINT8 *datap; + A_UINT8 trafficClass = WMM_AC_BE; + ATH_LLC_SNAP_HDR *llcHdr; + A_UINT16 ipType = IP_ETHERTYPE; + WMI_DATA_HDR *dtHdr; + WMI_CREATE_PSTREAM_CMD cmd; + A_BOOL streamExists = FALSE; + A_UINT8 userPriority; + + A_ASSERT(osbuf != NULL); + + datap = A_NETBUF_DATA(osbuf); + + if (!wmmEnabled) { + /* If WMM is disabled all traffic goes as BE traffic */ + userPriority = 0; + } else { + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) + + sizeof(ATH_MAC_HDR)); + + if (llcHdr->etherType == A_CPU2BE16(ipType)) { + /* Extract the endpoint info from the TOS field in the IP header */ + + userPriority = ar6000_determine_userPriority(((A_UINT8 *)llcHdr) + sizeof(ATH_LLC_SNAP_HDR),layer2Priority); + } else { + userPriority = layer2Priority & 0x7; + } + } + + trafficClass = convert_userPriority_to_trafficClass(userPriority); + + dtHdr = (WMI_DATA_HDR *)datap; + dtHdr->info |= (userPriority & WMI_DATA_HDR_UP_MASK) << WMI_DATA_HDR_UP_SHIFT; /* lower 3-bits are 802.1d priority */ + + LOCK_WMI(wmip); + streamExists = wmip->wmi_fatPipeExists; + UNLOCK_WMI(wmip); + + if (!(streamExists & (1 << trafficClass))) { + + A_MEMZERO(&cmd, sizeof(cmd)); + cmd.trafficClass = trafficClass; + cmd.userPriority = userPriority; + cmd.inactivityInt = WMI_IMPLICIT_PSTREAM_INACTIVITY_INT; + /* Implicit streams are created with TSID 0xFF */ + cmd.tsid = WMI_IMPLICIT_PSTREAM; + wmi_create_pstream_cmd(wmip, &cmd); + } + + return trafficClass; +} + +/* + * performs 802.3 to DIX encapsulation for received packets. + * Assumes the entire 802.3 header is contigous. + */ +A_STATUS +wmi_dot3_2_dix(struct wmi_t *wmip, void *osbuf) +{ + A_UINT8 *datap; + ATH_MAC_HDR macHdr; + ATH_LLC_SNAP_HDR *llcHdr; + + A_ASSERT(osbuf != NULL); + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY(&macHdr, datap, sizeof(ATH_MAC_HDR)); + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR)); + macHdr.typeOrLen = llcHdr->etherType; + + if (A_NETBUF_PULL(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR)); + + return (A_OK); +} + +/* + * Removes a WMI data header + */ +A_STATUS +wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf) +{ + A_ASSERT(osbuf != NULL); + + return (A_NETBUF_PULL(osbuf, sizeof(WMI_DATA_HDR))); +} + +void +wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg) +{ + wlan_iterate_nodes(&wmip->wmi_scan_table, f, arg); +} + +/* + * WMI Extended Event received from Target. + */ +A_STATUS +wmi_control_rx_xtnd(struct wmi_t *wmip, void *osbuf) +{ + WMIX_CMD_HDR *cmd; + A_UINT16 id; + A_UINT8 *datap; + A_UINT32 len; + A_STATUS status = A_OK; + + if (A_NETBUF_LEN(osbuf) < sizeof(WMIX_CMD_HDR)) { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + A_NETBUF_FREE(osbuf); + return A_ERROR; + } + + cmd = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf); + id = cmd->commandId; + + if (A_NETBUF_PULL(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + A_NETBUF_FREE(osbuf); + return A_ERROR; + } + + datap = A_NETBUF_DATA(osbuf); + len = A_NETBUF_LEN(osbuf); + + switch (id) { + case (WMIX_DSETOPENREQ_EVENTID): + status = wmi_dset_open_req_rx(wmip, datap, len); + break; +#ifdef CONFIG_HOST_DSET_SUPPORT + case (WMIX_DSETCLOSE_EVENTID): + status = wmi_dset_close_rx(wmip, datap, len); + break; + case (WMIX_DSETDATAREQ_EVENTID): + status = wmi_dset_data_req_rx(wmip, datap, len); + break; +#endif /* CONFIG_HOST_DSET_SUPPORT */ +#ifdef CONFIG_HOST_GPIO_SUPPORT + case (WMIX_GPIO_INTR_EVENTID): + wmi_gpio_intr_rx(wmip, datap, len); + break; + case (WMIX_GPIO_DATA_EVENTID): + wmi_gpio_data_rx(wmip, datap, len); + break; + case (WMIX_GPIO_ACK_EVENTID): + wmi_gpio_ack_rx(wmip, datap, len); + break; +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + case (WMIX_HB_CHALLENGE_RESP_EVENTID): + wmi_hbChallengeResp_rx(wmip, datap, len); + break; + case (WMIX_DBGLOG_EVENTID): + wmi_dbglog_event_rx(wmip, datap, len); + break; +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) + case (WMIX_PROF_COUNT_EVENTID): + wmi_prof_count_rx(wmip, datap, len); + break; +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + default: + A_DPRINTF(DBG_WMI|DBG_ERROR, + (DBGFMT "Unknown id 0x%x\n", DBGARG, id)); + wmip->wmi_stats.cmd_id_err++; + status = A_ERROR; + break; + } + + return status; +} + +/* + * Control Path + */ +A_UINT32 cmdRecvNum; + +A_STATUS +wmi_control_rx(struct wmi_t *wmip, void *osbuf) +{ + WMI_CMD_HDR *cmd; + A_UINT16 id; + A_UINT8 *datap; + A_UINT32 len, i, loggingReq; + A_STATUS status = A_OK; + + A_ASSERT(osbuf != NULL); + if (A_NETBUF_LEN(osbuf) < sizeof(WMI_CMD_HDR)) { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + A_NETBUF_FREE(osbuf); + return A_ERROR; + } + + cmd = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf); + id = cmd->commandId; + + if (A_NETBUF_PULL(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + A_NETBUF_FREE(osbuf); + return A_ERROR; + } + + datap = A_NETBUF_DATA(osbuf); + len = A_NETBUF_LEN(osbuf); + + loggingReq = 0; + + ar6000_get_driver_cfg(wmip->wmi_devt, + AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS, + &loggingReq); + + if(loggingReq) { + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI %d \n",id)); + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI recv, MsgNo %d : ", cmdRecvNum)); + for(i = 0; i < len; i++) + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("%x ", datap[i])); + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("\n")); + } + + LOCK_WMI(wmip); + cmdRecvNum++; + UNLOCK_WMI(wmip); + + switch (id) { + case (WMI_GET_BITRATE_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_BITRATE_CMDID\n", DBGARG)); + status = wmi_bitrate_reply_rx(wmip, datap, len); + break; + case (WMI_GET_CHANNEL_LIST_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_CHANNEL_LIST_CMDID\n", DBGARG)); + status = wmi_channelList_reply_rx(wmip, datap, len); + break; + case (WMI_GET_TX_PWR_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_TX_PWR_CMDID\n", DBGARG)); + status = wmi_txPwr_reply_rx(wmip, datap, len); + break; + case (WMI_READY_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_READY_EVENTID\n", DBGARG)); + status = wmi_ready_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + A_WMI_DBGLOG_INIT_DONE(wmip->wmi_devt); + break; + case (WMI_CONNECT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CONNECT_EVENTID\n", DBGARG)); + status = wmi_connect_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_DISCONNECT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_DISCONNECT_EVENTID\n", DBGARG)); + status = wmi_disconnect_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_TKIP_MICERR_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TKIP_MICERR_EVENTID\n", DBGARG)); + status = wmi_tkip_micerr_event_rx(wmip, datap, len); + break; + case (WMI_BSSINFO_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BSSINFO_EVENTID\n", DBGARG)); + status = wmi_bssInfo_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_REGDOMAIN_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REGDOMAIN_EVENTID\n", DBGARG)); + status = wmi_regDomain_event_rx(wmip, datap, len); + break; + case (WMI_PSTREAM_TIMEOUT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_PSTREAM_TIMEOUT_EVENTID\n", DBGARG)); + status = wmi_pstream_timeout_event_rx(wmip, datap, len); + /* pstreams are fatpipe abstractions that get implicitly created. + * User apps only deal with thinstreams. creation of a thinstream + * by the user or data traffic flow in an AC triggers implicit + * pstream creation. Do we need to send this event to App..? + * no harm in sending it. + */ + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_NEIGHBOR_REPORT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_NEIGHBOR_REPORT_EVENTID\n", DBGARG)); + status = wmi_neighborReport_event_rx(wmip, datap, len); + break; + case (WMI_SCAN_COMPLETE_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SCAN_COMPLETE_EVENTID\n", DBGARG)); + status = wmi_scanComplete_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_CMDERROR_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CMDERROR_EVENTID\n", DBGARG)); + status = wmi_errorEvent_rx(wmip, datap, len); + break; + case (WMI_REPORT_STATISTICS_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_STATISTICS_EVENTID\n", DBGARG)); + status = wmi_statsEvent_rx(wmip, datap, len); + break; + case (WMI_RSSI_THRESHOLD_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_RSSI_THRESHOLD_EVENTID\n", DBGARG)); + status = wmi_rssiThresholdEvent_rx(wmip, datap, len); + break; + case (WMI_ERROR_REPORT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_ERROR_REPORT_EVENTID\n", DBGARG)); + status = wmi_reportErrorEvent_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_OPT_RX_FRAME_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_OPT_RX_FRAME_EVENTID\n", DBGARG)); + status = wmi_opt_frame_event_rx(wmip, datap, len); + break; + case (WMI_REPORT_ROAM_TBL_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_TBL_EVENTID\n", DBGARG)); + status = wmi_roam_tbl_event_rx(wmip, datap, len); + break; + case (WMI_EXTENSION_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_EXTENSION_EVENTID\n", DBGARG)); + status = wmi_control_rx_xtnd(wmip, osbuf); + break; + case (WMI_CAC_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CAC_EVENTID\n", DBGARG)); + status = wmi_cac_event_rx(wmip, datap, len); + break; + case (WMI_CHANNEL_CHANGE_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CHANNEL_CHANGE_EVENTID\n", DBGARG)); + status = wmi_channel_change_event_rx(wmip, datap, len); + break; + case (WMI_REPORT_ROAM_DATA_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_DATA_EVENTID\n", DBGARG)); + status = wmi_roam_data_event_rx(wmip, datap, len); + break; +#ifdef CONFIG_HOST_TCMD_SUPPORT + case (WMI_TEST_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TEST_EVENTID\n", DBGARG)); + status = wmi_tcmd_test_report_rx(wmip, datap, len); + break; +#endif + case (WMI_GET_FIXRATES_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_FIXRATES_CMDID\n", DBGARG)); + status = wmi_ratemask_reply_rx(wmip, datap, len); + break; + case (WMI_TX_RETRY_ERR_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TX_RETRY_ERR_EVENTID\n", DBGARG)); + status = wmi_txRetryErrEvent_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_SNR_THRESHOLD_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SNR_THRESHOLD_EVENTID\n", DBGARG)); + status = wmi_snrThresholdEvent_rx(wmip, datap, len); + break; + case (WMI_LQ_THRESHOLD_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_LQ_THRESHOLD_EVENTID\n", DBGARG)); + status = wmi_lqThresholdEvent_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_APLIST_EVENTID): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Received APLIST Event\n")); + status = wmi_aplistEvent_rx(wmip, datap, len); + break; + case (WMI_GET_KEEPALIVE_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_KEEPALIVE_CMDID\n", DBGARG)); + status = wmi_keepalive_reply_rx(wmip, datap, len); + break; + case (WMI_GET_WOW_LIST_EVENTID): + status = wmi_get_wow_list_event_rx(wmip, datap, len); + break; + case (WMI_GET_PMKID_LIST_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_PMKID_LIST Event\n", DBGARG)); + status = wmi_get_pmkid_list_event_rx(wmip, datap, len); + break; + default: + A_DPRINTF(DBG_WMI|DBG_ERROR, + (DBGFMT "Unknown id 0x%x\n", DBGARG, id)); + wmip->wmi_stats.cmd_id_err++; + status = A_ERROR; + break; + } + + A_NETBUF_FREE(osbuf); + + return status; +} + +/* Send a "simple" wmi command -- one with no arguments */ +static A_STATUS +wmi_simple_cmd(struct wmi_t *wmip, WMI_COMMAND_ID cmdid) +{ + void *osbuf; + + osbuf = A_NETBUF_ALLOC(0); + + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + return (wmi_cmd_send(wmip, osbuf, cmdid, NO_SYNC_WMIFLAG)); +} + +/* Send a "simple" extended wmi command -- one with no arguments. + Enabling this command only if GPIO or profiling support is enabled. + This is to suppress warnings on some platforms */ +#if defined(CONFIG_HOST_GPIO_SUPPORT) || defined(CONFIG_TARGET_PROFILE_SUPPORT) +static A_STATUS +wmi_simple_cmd_xtnd(struct wmi_t *wmip, WMIX_COMMAND_ID cmdid) +{ + void *osbuf; + + osbuf = A_NETBUF_ALLOC(0); + + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + return (wmi_cmd_send_xtnd(wmip, osbuf, cmdid, NO_SYNC_WMIFLAG)); +} +#endif + +static A_STATUS +wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_READY_EVENT *ev = (WMI_READY_EVENT *)datap; + + if (len < sizeof(WMI_READY_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + wmip->wmi_ready = TRUE; + A_WMI_READY_EVENT(wmip->wmi_devt, ev->macaddr, ev->phyCapability, + ev->version); + + return A_OK; +} + +static A_STATUS +wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CONNECT_EVENT *ev; + + if (len < sizeof(WMI_CONNECT_EVENT)) { + return A_EINVAL; + } + ev = (WMI_CONNECT_EVENT *)datap; + A_DPRINTF(DBG_WMI, + (DBGFMT "freq %d bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", + DBGARG, ev->channel, + ev->bssid[0], ev->bssid[1], ev->bssid[2], + ev->bssid[3], ev->bssid[4], ev->bssid[5])); + + A_MEMCPY(wmip->wmi_bssid, ev->bssid, ATH_MAC_LEN); + + A_WMI_CONNECT_EVENT(wmip->wmi_devt, ev->channel, ev->bssid, + ev->listenInterval, ev->beaconInterval, + (NETWORK_TYPE) ev->networkType, ev->beaconIeLen, + ev->assocReqLen, ev->assocRespLen, + ev->assocInfo); + + return A_OK; +} + +static A_STATUS +wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_REG_DOMAIN_EVENT *ev; + + if (len < sizeof(*ev)) { + return A_EINVAL; + } + ev = (WMI_REG_DOMAIN_EVENT *)datap; + + A_WMI_REGDOMAIN_EVENT(wmip->wmi_devt, ev->regDomain); + + return A_OK; +} + +static A_STATUS +wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_NEIGHBOR_REPORT_EVENT *ev; + int numAps; + + if (len < sizeof(*ev)) { + return A_EINVAL; + } + ev = (WMI_NEIGHBOR_REPORT_EVENT *)datap; + numAps = ev->numberOfAps; + + if (len < (int)(sizeof(*ev) + ((numAps - 1) * sizeof(WMI_NEIGHBOR_INFO)))) { + return A_EINVAL; + } + + A_WMI_NEIGHBORREPORT_EVENT(wmip->wmi_devt, numAps, ev->neighbor); + + return A_OK; +} + +static A_STATUS +wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_DISCONNECT_EVENT *ev; + + if (len < sizeof(WMI_DISCONNECT_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + ev = (WMI_DISCONNECT_EVENT *)datap; + + A_MEMZERO(wmip->wmi_bssid, sizeof(wmip->wmi_bssid)); + + A_WMI_DISCONNECT_EVENT(wmip->wmi_devt, ev->disconnectReason, ev->bssid, + ev->assocRespLen, ev->assocInfo, ev->protocolReasonStatus); + + return A_OK; +} + +static A_STATUS +wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TKIP_MICERR_EVENT *ev; + + if (len < sizeof(*ev)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + ev = (WMI_TKIP_MICERR_EVENT *)datap; + A_WMI_TKIP_MICERR_EVENT(wmip->wmi_devt, ev->keyid, ev->ismcast); + + return A_OK; +} + +static A_STATUS +wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + bss_t *bss = NULL; + WMI_BSS_INFO_HDR *bih; + A_UINT8 *buf; + A_UINT32 nodeCachingAllowed = 1; + + if (len <= sizeof(WMI_BSS_INFO_HDR)) { + return A_EINVAL; + } + + bih = (WMI_BSS_INFO_HDR *)datap; + bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid); + + if (bih->rssi > 0) { + if (NULL == bss) + return A_OK; //no node found in the table, just drop the node with incorrect RSSI + else + bih->rssi = bss->ni_rssi; //Adjust RSSI in datap in case it is used in A_WMI_BSSINFO_EVENT_RX + } + + A_WMI_BSSINFO_EVENT_RX(wmip->wmi_devt, datap, len); + /* What is driver config for wlan node caching? */ + if(ar6000_get_driver_cfg(wmip->wmi_devt, + AR6000_DRIVER_CFG_GET_WLANNODECACHING, + &nodeCachingAllowed) != A_OK) { + return A_EINVAL; + } + + if(!nodeCachingAllowed) { + return A_OK; + } + + buf = datap + sizeof(WMI_BSS_INFO_HDR); + len -= sizeof(WMI_BSS_INFO_HDR); + + A_DPRINTF(DBG_WMI2, (DBGFMT "bssInfo event - ch %u, rssi %02x, " + "bssid \"%02x:%02x:%02x:%02x:%02x:%02x\"\n", DBGARG, + bih->channel, (unsigned char) bih->rssi, bih->bssid[0], + bih->bssid[1], bih->bssid[2], bih->bssid[3], bih->bssid[4], + bih->bssid[5])); + + if(wps_enable && (bih->frameType == PROBERESP_FTYPE) ) + return A_OK; + + if (bss != NULL) { + /* + * Free up the node. Not the most efficient process given + * we are about to allocate a new node but it is simple and should be + * adequate. + */ + wlan_node_reclaim(&wmip->wmi_scan_table, bss); + } + + bss = wlan_node_alloc(&wmip->wmi_scan_table, len); + if (bss == NULL) { + return A_NO_MEMORY; + } + + bss->ni_snr = bih->snr; + bss->ni_rssi = bih->rssi; + A_ASSERT(bss->ni_buf != NULL); + A_MEMCPY(bss->ni_buf, buf, len); + + if (wlan_parse_beacon(bss->ni_buf, len, &bss->ni_cie) != A_OK) { + wlan_node_free(bss); + return A_EINVAL; + } + + /* + * Update the frequency in ie_chan, overwriting of channel number + * which is done in wlan_parse_beacon + */ + bss->ni_cie.ie_chan = bih->channel; + wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid); + + return A_OK; +} + +static A_STATUS +wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + bss_t *bss; + WMI_OPT_RX_INFO_HDR *bih; + A_UINT8 *buf; + + if (len <= sizeof(WMI_OPT_RX_INFO_HDR)) { + return A_EINVAL; + } + + bih = (WMI_OPT_RX_INFO_HDR *)datap; + buf = datap + sizeof(WMI_OPT_RX_INFO_HDR); + len -= sizeof(WMI_OPT_RX_INFO_HDR); + + A_DPRINTF(DBG_WMI2, (DBGFMT "opt frame event %2.2x:%2.2x\n", DBGARG, + bih->bssid[4], bih->bssid[5])); + + bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid); + if (bss != NULL) { + /* + * Free up the node. Not the most efficient process given + * we are about to allocate a new node but it is simple and should be + * adequate. + */ + wlan_node_reclaim(&wmip->wmi_scan_table, bss); + } + + bss = wlan_node_alloc(&wmip->wmi_scan_table, len); + if (bss == NULL) { + return A_NO_MEMORY; + } + + bss->ni_snr = bih->snr; + bss->ni_cie.ie_chan = bih->channel; + A_ASSERT(bss->ni_buf != NULL); + A_MEMCPY(bss->ni_buf, buf, len); + wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid); + + return A_OK; +} + + /* This event indicates inactivity timeout of a fatpipe(pstream) + * at the target + */ +static A_STATUS +wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_PSTREAM_TIMEOUT_EVENT *ev; + + if (len < sizeof(WMI_PSTREAM_TIMEOUT_EVENT)) { + return A_EINVAL; + } + + A_DPRINTF(DBG_WMI, (DBGFMT "wmi_pstream_timeout_event_rx\n", DBGARG)); + + ev = (WMI_PSTREAM_TIMEOUT_EVENT *)datap; + + /* When the pstream (fat pipe == AC) timesout, it means there were no + * thinStreams within this pstream & it got implicitly created due to + * data flow on this AC. We start the inactivity timer only for + * implicitly created pstream. Just reset the host state. + */ + /* Set the activeTsids for this AC to 0 */ + LOCK_WMI(wmip); + wmip->wmi_streamExistsForAC[ev->trafficClass]=0; + wmip->wmi_fatPipeExists &= ~(1 << ev->trafficClass); + UNLOCK_WMI(wmip); + + /*Indicate inactivity to driver layer for this fatpipe (pstream)*/ + A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, ev->trafficClass); + + return A_OK; +} + +static A_STATUS +wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_BIT_RATE_CMD *reply; + A_INT32 rate; + + if (len < sizeof(WMI_BIT_RATE_CMD)) { + return A_EINVAL; + } + reply = (WMI_BIT_RATE_CMD *)datap; + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - rateindex %d\n", DBGARG, reply->rateIndex)); + + if (reply->rateIndex == (A_INT8) RATE_AUTO) { + rate = RATE_AUTO; + } else { + rate = wmi_rateTable[(A_UINT32) reply->rateIndex]; + } + + A_WMI_BITRATE_RX(wmip->wmi_devt, rate); + + return A_OK; +} + +static A_STATUS +wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_FIX_RATES_CMD *reply; + + if (len < sizeof(WMI_BIT_RATE_CMD)) { + return A_EINVAL; + } + reply = (WMI_FIX_RATES_CMD *)datap; + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - fixed rate mask %x\n", DBGARG, reply->fixRateMask)); + + A_WMI_RATEMASK_RX(wmip->wmi_devt, reply->fixRateMask); + + return A_OK; +} + +static A_STATUS +wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CHANNEL_LIST_REPLY *reply; + + if (len < sizeof(WMI_CHANNEL_LIST_REPLY)) { + return A_EINVAL; + } + reply = (WMI_CHANNEL_LIST_REPLY *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_CHANNELLIST_RX(wmip->wmi_devt, reply->numChannels, + reply->channelList); + + return A_OK; +} + +static A_STATUS +wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TX_PWR_REPLY *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TX_PWR_REPLY *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TXPWR_RX(wmip->wmi_devt, reply->dbM); + + return A_OK; +} +static A_STATUS +wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_GET_KEEPALIVE_CMD *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_GET_KEEPALIVE_CMD *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_KEEPALIVE_RX(wmip->wmi_devt, reply->configured); + + return A_OK; +} + + +static A_STATUS +wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_DSETOPENREQ_EVENT *dsetopenreq; + + if (len < sizeof(WMIX_DSETOPENREQ_EVENT)) { + return A_EINVAL; + } + dsetopenreq = (WMIX_DSETOPENREQ_EVENT *)datap; + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - dset_id=0x%x\n", DBGARG, dsetopenreq->dset_id)); + A_WMI_DSET_OPEN_REQ(wmip->wmi_devt, + dsetopenreq->dset_id, + dsetopenreq->targ_dset_handle, + dsetopenreq->targ_reply_fn, + dsetopenreq->targ_reply_arg); + + return A_OK; +} + +#ifdef CONFIG_HOST_DSET_SUPPORT +static A_STATUS +wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_DSETCLOSE_EVENT *dsetclose; + + if (len < sizeof(WMIX_DSETCLOSE_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + dsetclose = (WMIX_DSETCLOSE_EVENT *)datap; + A_WMI_DSET_CLOSE(wmip->wmi_devt, dsetclose->access_cookie); + + return A_OK; +} + +static A_STATUS +wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_DSETDATAREQ_EVENT *dsetdatareq; + + if (len < sizeof(WMIX_DSETDATAREQ_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + dsetdatareq = (WMIX_DSETDATAREQ_EVENT *)datap; + A_WMI_DSET_DATA_REQ(wmip->wmi_devt, + dsetdatareq->access_cookie, + dsetdatareq->offset, + dsetdatareq->length, + dsetdatareq->targ_buf, + dsetdatareq->targ_reply_fn, + dsetdatareq->targ_reply_arg); + + return A_OK; +} +#endif /* CONFIG_HOST_DSET_SUPPORT */ + +static A_STATUS +wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_SCAN_COMPLETE_EVENT *ev; + + ev = (WMI_SCAN_COMPLETE_EVENT *)datap; + A_WMI_SCANCOMPLETE_EVENT(wmip->wmi_devt, (A_STATUS) ev->status); + + return A_OK; +} + +/* + * Target is reporting a programming error. This is for + * developer aid only. Target only checks a few common violations + * and it is responsibility of host to do all error checking. + * Behavior of target after wmi error event is undefined. + * A reset is recommended. + */ +static A_STATUS +wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CMD_ERROR_EVENT *ev; + + ev = (WMI_CMD_ERROR_EVENT *)datap; + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Programming Error: cmd=%d ", ev->commandId)); + switch (ev->errorCode) { + case (INVALID_PARAM): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal Parameter\n")); + break; + case (ILLEGAL_STATE): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal State\n")); + break; + case (INTERNAL_ERROR): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Internal Error\n")); + break; + } + + return A_OK; +} + + +static A_STATUS +wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TARGET_STATS *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TARGET_STATS *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TARGETSTATS_EVENT(wmip->wmi_devt, reply); + + return A_OK; +} + +static A_STATUS +wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_RSSI_THRESHOLD_EVENT *reply; + WMI_RSSI_THRESHOLD_VAL newThreshold; + WMI_RSSI_THRESHOLD_PARAMS_CMD cmd; + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_RSSI]; + A_UINT8 upper_rssi_threshold, lower_rssi_threshold; + A_INT16 rssi; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_RSSI_THRESHOLD_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + newThreshold = (WMI_RSSI_THRESHOLD_VAL) reply->range; + rssi = reply->rssi; + + /* + * Identify the threshold breached and communicate that to the app. After + * that install a new set of thresholds based on the signal quality + * reported by the target + */ + if (newThreshold) { + /* Upper threshold breached */ + if (rssi < sq_thresh->upper_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious upper RSSI threshold event: " + " %d\n", DBGARG, rssi)); + } else if ((rssi < sq_thresh->upper_threshold[1]) && + (rssi >= sq_thresh->upper_threshold[0])) + { + newThreshold = WMI_RSSI_THRESHOLD1_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[2]) && + (rssi >= sq_thresh->upper_threshold[1])) + { + newThreshold = WMI_RSSI_THRESHOLD2_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[3]) && + (rssi >= sq_thresh->upper_threshold[2])) + { + newThreshold = WMI_RSSI_THRESHOLD3_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[4]) && + (rssi >= sq_thresh->upper_threshold[3])) + { + newThreshold = WMI_RSSI_THRESHOLD4_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[5]) && + (rssi >= sq_thresh->upper_threshold[4])) + { + newThreshold = WMI_RSSI_THRESHOLD5_ABOVE; + } else if (rssi >= sq_thresh->upper_threshold[5]) { + newThreshold = WMI_RSSI_THRESHOLD6_ABOVE; + } + } else { + /* Lower threshold breached */ + if (rssi > sq_thresh->lower_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious lower RSSI threshold event: " + "%d %d\n", DBGARG, rssi, sq_thresh->lower_threshold[0])); + } else if ((rssi > sq_thresh->lower_threshold[1]) && + (rssi <= sq_thresh->lower_threshold[0])) + { + newThreshold = WMI_RSSI_THRESHOLD6_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[2]) && + (rssi <= sq_thresh->lower_threshold[1])) + { + newThreshold = WMI_RSSI_THRESHOLD5_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[3]) && + (rssi <= sq_thresh->lower_threshold[2])) + { + newThreshold = WMI_RSSI_THRESHOLD4_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[4]) && + (rssi <= sq_thresh->lower_threshold[3])) + { + newThreshold = WMI_RSSI_THRESHOLD3_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[5]) && + (rssi <= sq_thresh->lower_threshold[4])) + { + newThreshold = WMI_RSSI_THRESHOLD2_BELOW; + } else if (rssi <= sq_thresh->lower_threshold[5]) { + newThreshold = WMI_RSSI_THRESHOLD1_BELOW; + } + } + /* Calculate and install the next set of thresholds */ + lower_rssi_threshold = ar6000_get_lower_threshold(rssi, sq_thresh, + sq_thresh->lower_threshold_valid_count); + upper_rssi_threshold = ar6000_get_upper_threshold(rssi, sq_thresh, + sq_thresh->upper_threshold_valid_count); + /* Issue a wmi command to install the thresholds */ + cmd.thresholdAbove1_Val = upper_rssi_threshold; + cmd.thresholdBelow1_Val = lower_rssi_threshold; + cmd.weight = sq_thresh->weight; + cmd.pollTime = sq_thresh->polling_interval; + + if (wmi_send_rssi_threshold_params(wmip, &cmd) != A_OK) { + A_DPRINTF(DBG_WMI, (DBGFMT "Unable to configure the RSSI thresholds\n", + DBGARG)); + } + + A_WMI_RSSI_THRESHOLD_EVENT(wmip->wmi_devt, (WMI_RSSI_THRESHOLD_VAL) reply->range, + reply->rssi); + + return A_OK; +} + + +static A_STATUS +wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TARGET_ERROR_REPORT_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TARGET_ERROR_REPORT_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_REPORT_ERROR_EVENT(wmip->wmi_devt, (WMI_TARGET_ERROR_VAL) reply->errorVal); + + return A_OK; +} + +static A_STATUS +wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CAC_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_CAC_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_CAC_EVENT(wmip->wmi_devt, reply->ac, + reply->cac_indication, reply->statusCode, + reply->tspecSuggestion); + + return A_OK; +} + +static A_STATUS +wmi_channel_change_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CHANNEL_CHANGE_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_CHANNEL_CHANGE_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_CHANNEL_CHANGE_EVENT(wmip->wmi_devt, reply->oldChannel, + reply->newChannel); + + return A_OK; +} + +static A_STATUS +wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_HB_CHALLENGE_RESP_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMIX_HB_CHALLENGE_RESP_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "wmi: challenge response event\n", DBGARG)); + + A_WMI_HBCHALLENGERESP_EVENT(wmip->wmi_devt, reply->cookie, reply->source); + + return A_OK; +} + +static A_STATUS +wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TARGET_ROAM_TBL *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TARGET_ROAM_TBL *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_ROAM_TABLE_EVENT(wmip->wmi_devt, reply); + + return A_OK; +} + +static A_STATUS +wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TARGET_ROAM_DATA *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TARGET_ROAM_DATA *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_ROAM_DATA_EVENT(wmip->wmi_devt, reply); + + return A_OK; +} + +static A_STATUS +wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + if (len < sizeof(WMI_TX_RETRY_ERR_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TX_RETRY_ERR_EVENT(wmip->wmi_devt); + + return A_OK; +} + +static A_STATUS +wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_SNR_THRESHOLD_EVENT *reply; + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_SNR]; + WMI_SNR_THRESHOLD_VAL newThreshold; + WMI_SNR_THRESHOLD_PARAMS_CMD cmd; + A_UINT8 upper_snr_threshold, lower_snr_threshold; + A_INT16 snr; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_SNR_THRESHOLD_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + newThreshold = (WMI_SNR_THRESHOLD_VAL) reply->range; + snr = reply->snr; + /* + * Identify the threshold breached and communicate that to the app. After + * that install a new set of thresholds based on the signal quality + * reported by the target + */ + if (newThreshold) { + /* Upper threshold breached */ + if (snr < sq_thresh->upper_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious upper SNR threshold event: " + "%d\n", DBGARG, snr)); + } else if ((snr < sq_thresh->upper_threshold[1]) && + (snr >= sq_thresh->upper_threshold[0])) + { + newThreshold = WMI_SNR_THRESHOLD1_ABOVE; + } else if ((snr < sq_thresh->upper_threshold[2]) && + (snr >= sq_thresh->upper_threshold[1])) + { + newThreshold = WMI_SNR_THRESHOLD2_ABOVE; + } else if ((snr < sq_thresh->upper_threshold[3]) && + (snr >= sq_thresh->upper_threshold[2])) + { + newThreshold = WMI_SNR_THRESHOLD3_ABOVE; + } else if (snr >= sq_thresh->upper_threshold[3]) { + newThreshold = WMI_SNR_THRESHOLD4_ABOVE; + } + } else { + /* Lower threshold breached */ + if (snr > sq_thresh->lower_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious lower SNR threshold event: " + "%d %d\n", DBGARG, snr, sq_thresh->lower_threshold[0])); + } else if ((snr > sq_thresh->lower_threshold[1]) && + (snr <= sq_thresh->lower_threshold[0])) + { + newThreshold = WMI_SNR_THRESHOLD4_BELOW; + } else if ((snr > sq_thresh->lower_threshold[2]) && + (snr <= sq_thresh->lower_threshold[1])) + { + newThreshold = WMI_SNR_THRESHOLD3_BELOW; + } else if ((snr > sq_thresh->lower_threshold[3]) && + (snr <= sq_thresh->lower_threshold[2])) + { + newThreshold = WMI_SNR_THRESHOLD2_BELOW; + } else if (snr <= sq_thresh->lower_threshold[3]) { + newThreshold = WMI_SNR_THRESHOLD1_BELOW; + } + } + + /* Calculate and install the next set of thresholds */ + lower_snr_threshold = ar6000_get_lower_threshold(snr, sq_thresh, + sq_thresh->lower_threshold_valid_count); + upper_snr_threshold = ar6000_get_upper_threshold(snr, sq_thresh, + sq_thresh->upper_threshold_valid_count); + + /* Issue a wmi command to install the thresholds */ + cmd.thresholdAbove1_Val = upper_snr_threshold; + cmd.thresholdBelow1_Val = lower_snr_threshold; + cmd.weight = sq_thresh->weight; + cmd.pollTime = sq_thresh->polling_interval; + + A_DPRINTF(DBG_WMI, (DBGFMT "snr: %d, threshold: %d, lower: %d, upper: %d\n" + ,DBGARG, snr, newThreshold, lower_snr_threshold, + upper_snr_threshold)); + + if (wmi_send_snr_threshold_params(wmip, &cmd) != A_OK) { + A_DPRINTF(DBG_WMI, (DBGFMT "Unable to configure the SNR thresholds\n", + DBGARG)); + } + A_WMI_SNR_THRESHOLD_EVENT_RX(wmip->wmi_devt, + (WMI_SNR_THRESHOLD_VAL) reply->range, + reply->snr); + + return A_OK; +} + +static A_STATUS +wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_LQ_THRESHOLD_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_LQ_THRESHOLD_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_LQ_THRESHOLD_EVENT_RX(wmip->wmi_devt, + (WMI_LQ_THRESHOLD_VAL) reply->range, + reply->lq); + + return A_OK; +} + +static A_STATUS +wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + A_UINT16 ap_info_entry_size; + WMI_APLIST_EVENT *ev = (WMI_APLIST_EVENT *)datap; + WMI_AP_INFO_V1 *ap_info_v1; + A_UINT8 i; + + if (len < sizeof(WMI_APLIST_EVENT)) { + return A_EINVAL; + } + + if (ev->apListVer == APLIST_VER1) { + ap_info_entry_size = sizeof(WMI_AP_INFO_V1); + ap_info_v1 = (WMI_AP_INFO_V1 *)ev->apList; + } else { + return A_EINVAL; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Number of APs in APLIST Event is %d\n", ev->numAP)); + if (len < (int)(sizeof(WMI_APLIST_EVENT) + + (ev->numAP - 1) * ap_info_entry_size)) + { + return A_EINVAL; + } + + /* + * AP List Ver1 Contents + */ + for (i = 0; i < ev->numAP; i++) { + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("AP#%d BSSID %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x "\ + "Channel %d\n", i, + ap_info_v1->bssid[0], ap_info_v1->bssid[1], + ap_info_v1->bssid[2], ap_info_v1->bssid[3], + ap_info_v1->bssid[4], ap_info_v1->bssid[5], + ap_info_v1->channel)); + ap_info_v1++; + } + return A_OK; +} + +static A_STATUS +wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + A_UINT32 dropped; + + dropped = *((A_UINT32 *)datap); + datap += sizeof(dropped); + len -= sizeof(dropped); + A_WMI_DBGLOG_EVENT(wmip->wmi_devt, dropped, datap, len); + return A_OK; +} + +#ifdef CONFIG_HOST_GPIO_SUPPORT +static A_STATUS +wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_GPIO_INTR_EVENT *gpio_intr = (WMIX_GPIO_INTR_EVENT *)datap; + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - intrmask=0x%x input=0x%x.\n", DBGARG, + gpio_intr->intr_mask, gpio_intr->input_values)); + + A_WMI_GPIO_INTR_RX(gpio_intr->intr_mask, gpio_intr->input_values); + + return A_OK; +} + +static A_STATUS +wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_GPIO_DATA_EVENT *gpio_data = (WMIX_GPIO_DATA_EVENT *)datap; + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG, + gpio_data->reg_id, gpio_data->value)); + + A_WMI_GPIO_DATA_RX(gpio_data->reg_id, gpio_data->value); + + return A_OK; +} + +static A_STATUS +wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_GPIO_ACK_RX(); + + return A_OK; +} +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +/* + * Called to send a wmi command. Command specific data is already built + * on osbuf and current osbuf->data points to it. + */ +A_STATUS +wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId, + WMI_SYNC_FLAG syncflag) +{ +#define IS_OPT_TX_CMD(cmdId) ((cmdId == WMI_OPT_TX_FRAME_CMDID)) + WMI_CMD_HDR *cHdr; + HTC_ENDPOINT_ID eid = wmip->wmi_endpoint_id; + + A_ASSERT(osbuf != NULL); + + if (syncflag >= END_WMIFLAG) { + return A_EINVAL; + } + + if ((syncflag == SYNC_BEFORE_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) { + /* + * We want to make sure all data currently queued is transmitted before + * the cmd execution. Establish a new sync point. + */ + wmi_sync_point(wmip); + } + + if (A_NETBUF_PUSH(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + cHdr = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf); + cHdr->commandId = (A_UINT16) cmdId; + + /* + * Only for OPT_TX_CMD, use BE endpoint. + */ + if (IS_OPT_TX_CMD(cmdId)) { + wmi_data_hdr_add(wmip, osbuf, OPT_MSGTYPE); + eid = A_WMI_Ac2EndpointID(wmip->wmi_devt, WMM_AC_BE); + } + A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, eid); + + if ((syncflag == SYNC_AFTER_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) { + /* + * We want to make sure all new data queued waits for the command to + * execute. Establish a new sync point. + */ + wmi_sync_point(wmip); + } + return (A_OK); +#undef IS_OPT_TX_CMD +} + +A_STATUS +wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMIX_COMMAND_ID cmdId, + WMI_SYNC_FLAG syncflag) +{ + WMIX_CMD_HDR *cHdr; + + if (A_NETBUF_PUSH(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + cHdr = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf); + cHdr->commandId = (A_UINT32) cmdId; + + return wmi_cmd_send(wmip, osbuf, WMI_EXTENSION_CMDID, syncflag); +} + +A_STATUS +wmi_connect_cmd(struct wmi_t *wmip, NETWORK_TYPE netType, + DOT11_AUTH_MODE dot11AuthMode, AUTH_MODE authMode, + CRYPTO_TYPE pairwiseCrypto, A_UINT8 pairwiseCryptoLen, + CRYPTO_TYPE groupCrypto, A_UINT8 groupCryptoLen, + int ssidLength, A_UCHAR *ssid, + A_UINT8 *bssid, A_UINT16 channel, A_UINT32 ctrl_flags) +{ + void *osbuf; + WMI_CONNECT_CMD *cc; + + if ((pairwiseCrypto == NONE_CRYPT) && (groupCrypto != NONE_CRYPT)) { + return A_EINVAL; + } + if ((pairwiseCrypto != NONE_CRYPT) && (groupCrypto == NONE_CRYPT)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_CONNECT_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_CONNECT_CMD)); + + cc = (WMI_CONNECT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cc, sizeof(*cc)); + + if (ssidLength) + { + A_MEMCPY(cc->ssid, ssid, ssidLength); + } + + cc->ssidLength = ssidLength; + cc->networkType = netType; + cc->dot11AuthMode = dot11AuthMode; + cc->authMode = authMode; + cc->pairwiseCryptoType = pairwiseCrypto; + cc->pairwiseCryptoLen = pairwiseCryptoLen; + cc->groupCryptoType = groupCrypto; + cc->groupCryptoLen = groupCryptoLen; + cc->channel = channel; + cc->ctrl_flags = ctrl_flags; + + if (bssid != NULL) { + A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN); + } + if (wmi_set_keepalive_cmd(wmip, wmip->wmi_keepaliveInterval) != A_OK) { + return(A_ERROR); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_CONNECT_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_reconnect_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT16 channel) +{ + void *osbuf; + WMI_RECONNECT_CMD *cc; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_RECONNECT_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_RECONNECT_CMD)); + + cc = (WMI_RECONNECT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cc, sizeof(*cc)); + + cc->channel = channel; + + if (bssid != NULL) { + A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_RECONNECT_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_disconnect_cmd(struct wmi_t *wmip) +{ + A_STATUS status; + + /* Bug fix for 24817(elevator bug) - the disconnect command does not + need to do a SYNC before.*/ + status = wmi_simple_cmd(wmip, WMI_DISCONNECT_CMDID); + + return status; +} + +A_STATUS +wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType, + A_BOOL forceFgScan, A_BOOL isLegacy, + A_UINT32 homeDwellTime, A_UINT32 forceScanInterval, + A_INT8 numChan, A_UINT16 *channelList) +{ + void *osbuf; + WMI_START_SCAN_CMD *sc; + A_INT8 size; + + size = sizeof (*sc); + + if ((scanType != WMI_LONG_SCAN) && (scanType != WMI_SHORT_SCAN)) { + return A_EINVAL; + } + + if (numChan) { + if (numChan > WMI_MAX_CHANNELS) { + return A_EINVAL; + } + size += sizeof(A_UINT16) * (numChan - 1); + } + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + sc = (WMI_START_SCAN_CMD *)(A_NETBUF_DATA(osbuf)); + sc->scanType = scanType; + sc->forceFgScan = forceFgScan; + sc->isLegacy = isLegacy; + sc->homeDwellTime = homeDwellTime; + sc->forceScanInterval = forceScanInterval; + sc->numChannels = numChan; + if (numChan) { + A_MEMCPY(sc->channelList, channelList, numChan * sizeof(A_UINT16)); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_START_SCAN_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec, + A_UINT16 fg_end_sec, A_UINT16 bg_sec, + A_UINT16 minact_chdw_msec, A_UINT16 maxact_chdw_msec, + A_UINT16 pas_chdw_msec, + A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags, + A_UINT32 max_dfsch_act_time) +{ + void *osbuf; + WMI_SCAN_PARAMS_CMD *sc; + + osbuf = A_NETBUF_ALLOC(sizeof(*sc)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*sc)); + + sc = (WMI_SCAN_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(sc, sizeof(*sc)); + sc->fg_start_period = fg_start_sec; + sc->fg_end_period = fg_end_sec; + sc->bg_period = bg_sec; + sc->minact_chdwell_time = minact_chdw_msec; + sc->maxact_chdwell_time = maxact_chdw_msec; + sc->pas_chdwell_time = pas_chdw_msec; + sc->shortScanRatio = shScanRatio; + sc->scanCtrlFlags = scanCtrlFlags; + sc->max_dfsch_act_time = max_dfsch_act_time; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_SCAN_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask) +{ + void *osbuf; + WMI_BSS_FILTER_CMD *cmd; + + if (filter >= LAST_BSS_FILTER) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_BSS_FILTER_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->bssFilter = filter; + cmd->ieMask = ieMask; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BSS_FILTER_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag, + A_UINT8 ssidLength, A_UCHAR *ssid) +{ + void *osbuf; + WMI_PROBED_SSID_CMD *cmd; + + if (index > MAX_PROBED_SSID_INDEX) { + return A_EINVAL; + } + if (ssidLength > sizeof(cmd->ssid)) { + return A_EINVAL; + } + if ((flag & (DISABLE_SSID_FLAG | ANY_SSID_FLAG)) && (ssidLength > 0)) { + return A_EINVAL; + } + if ((flag & SPECIFIC_SSID_FLAG) && !ssidLength) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_PROBED_SSID_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->entryIndex = index; + cmd->flag = flag; + cmd->ssidLength = ssidLength; + A_MEMCPY(cmd->ssid, ssid, ssidLength); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PROBED_SSID_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons) +{ + void *osbuf; + WMI_LISTEN_INT_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_LISTEN_INT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->listenInterval = listenInterval; + cmd->numBeacons = listenBeacons; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_LISTEN_INT_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmissTime, A_UINT16 bmissBeacons) +{ + void *osbuf; + WMI_BMISS_TIME_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_BMISS_TIME_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->bmissTime = bmissTime; + cmd->numBeacons = bmissBeacons; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BMISS_TIME_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType, + A_UINT8 ieLen, A_UINT8 *ieInfo) +{ + void *osbuf; + WMI_SET_ASSOC_INFO_CMD *cmd; + A_UINT16 cmdLen; + + cmdLen = sizeof(*cmd) + ieLen - 1; + osbuf = A_NETBUF_ALLOC(cmdLen); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, cmdLen); + + cmd = (WMI_SET_ASSOC_INFO_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + cmd->ieType = ieType; + cmd->bufferSize = ieLen; + A_MEMCPY(cmd->assocInfo, ieInfo, ieLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_ASSOC_INFO_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode) +{ + void *osbuf; + WMI_POWER_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_POWER_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->powerMode = powerMode; + wmip->wmi_powerMode = powerMode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl, + A_UINT16 atim_windows, A_UINT16 timeout_value) +{ + void *osbuf; + WMI_IBSS_PM_CAPS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_IBSS_PM_CAPS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->power_saving = pmEnable; + cmd->ttl = ttl; + cmd->atim_windows = atim_windows; + cmd->timeout_value = timeout_value; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_IBSS_PM_CAPS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod, + A_UINT16 psPollNum, A_UINT16 dtimPolicy) +{ + void *osbuf; + WMI_POWER_PARAMS_CMD *pm; + + osbuf = A_NETBUF_ALLOC(sizeof(*pm)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*pm)); + + pm = (WMI_POWER_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(pm, sizeof(*pm)); + pm->idle_period = idlePeriod; + pm->pspoll_number = psPollNum; + pm->dtim_policy = dtimPolicy; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout) +{ + void *osbuf; + WMI_DISC_TIMEOUT_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DISC_TIMEOUT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->disconnectTimeout = timeout; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_DISC_TIMEOUT_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex, CRYPTO_TYPE keyType, + A_UINT8 keyUsage, A_UINT8 keyLength, A_UINT8 *keyRSC, + A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl, + WMI_SYNC_FLAG sync_flag) +{ + void *osbuf; + WMI_ADD_CIPHER_KEY_CMD *cmd; + + if ((keyIndex > WMI_MAX_KEY_INDEX) || (keyLength > WMI_MAX_KEY_LEN) || + (keyMaterial == NULL)) + { + return A_EINVAL; + } + + if ((WEP_CRYPT != keyType) && (NULL == keyRSC)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_ADD_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->keyIndex = keyIndex; + cmd->keyType = keyType; + cmd->keyUsage = keyUsage; + cmd->keyLength = keyLength; + A_MEMCPY(cmd->key, keyMaterial, keyLength); + if (NULL != keyRSC) { + A_MEMCPY(cmd->keyRSC, keyRSC, sizeof(cmd->keyRSC)); + } + cmd->key_op_ctrl = key_op_ctrl; + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_CIPHER_KEY_CMDID, sync_flag)); +} + +A_STATUS +wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk) +{ + void *osbuf; + WMI_ADD_KRK_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_ADD_KRK_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + A_MEMCPY(cmd->krk, krk, WMI_KRK_LEN); + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_KRK_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_delete_krk_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_DELETE_KRK_CMDID); +} + +A_STATUS +wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex) +{ + void *osbuf; + WMI_DELETE_CIPHER_KEY_CMD *cmd; + + if (keyIndex > WMI_MAX_KEY_INDEX) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DELETE_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->keyIndex = keyIndex; + + return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_CIPHER_KEY_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId, + A_BOOL set) +{ + void *osbuf; + WMI_SET_PMKID_CMD *cmd; + + if (bssid == NULL) { + return A_EINVAL; + } + + if ((set == TRUE) && (pmkId == NULL)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_PMKID_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid)); + if (set == TRUE) { + A_MEMCPY(cmd->pmkid, pmkId, sizeof(cmd->pmkid)); + cmd->enable = PMKID_ENABLE; + } else { + A_MEMZERO(cmd->pmkid, sizeof(cmd->pmkid)); + cmd->enable = PMKID_DISABLE; + } + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en) +{ + void *osbuf; + WMI_SET_TKIP_COUNTERMEASURES_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_TKIP_COUNTERMEASURES_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->cm_en = (en == TRUE)? WMI_TKIP_CM_ENABLE : WMI_TKIP_CM_DISABLE; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_TKIP_COUNTERMEASURES_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_akmp_params_cmd(struct wmi_t *wmip, + WMI_SET_AKMP_PARAMS_CMD *akmpParams) +{ + void *osbuf; + WMI_SET_AKMP_PARAMS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + cmd = (WMI_SET_AKMP_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->akmpInfo = akmpParams->akmpInfo; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_AKMP_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_pmkid_list_cmd(struct wmi_t *wmip, + WMI_SET_PMKID_LIST_CMD *pmkInfo) +{ + void *osbuf; + WMI_SET_PMKID_LIST_CMD *cmd; + A_UINT16 cmdLen; + A_UINT8 i; + + cmdLen = sizeof(pmkInfo->numPMKID) + + pmkInfo->numPMKID * sizeof(WMI_PMKID); + + osbuf = A_NETBUF_ALLOC(cmdLen); + + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, cmdLen); + cmd = (WMI_SET_PMKID_LIST_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->numPMKID = pmkInfo->numPMKID; + + for (i = 0; i < cmd->numPMKID; i++) { + A_MEMCPY(&cmd->pmkidList[i], &pmkInfo->pmkidList[i], + WMI_PMKID_LEN); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_LIST_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_pmkid_list_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_PMKID_LIST_CMDID); +} + +A_STATUS +wmi_dataSync_send(struct wmi_t *wmip, void *osbuf, HTC_ENDPOINT_ID eid) +{ + WMI_DATA_HDR *dtHdr; + + A_ASSERT( eid != wmip->wmi_endpoint_id); + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf); + dtHdr->info = + (SYNC_MSGTYPE & WMI_DATA_HDR_MSG_TYPE_MASK) << WMI_DATA_HDR_MSG_TYPE_SHIFT; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter - eid %d\n", DBGARG, eid)); + + return (A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, eid)); +} + +typedef struct _WMI_DATA_SYNC_BUFS { + A_UINT8 trafficClass; + void *osbuf; +}WMI_DATA_SYNC_BUFS; + +static A_STATUS +wmi_sync_point(struct wmi_t *wmip) +{ + void *cmd_osbuf; + WMI_SYNC_CMD *cmd; + WMI_DATA_SYNC_BUFS dataSyncBufs[WMM_NUM_AC]; + A_UINT8 i,numPriStreams=0; + A_STATUS status = A_OK; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + memset(dataSyncBufs,0,sizeof(dataSyncBufs)); + + /* lock out while we walk through the priority list and assemble our local array */ + LOCK_WMI(wmip); + + for (i=0; i < WMM_NUM_AC ; i++) { + if (wmip->wmi_fatPipeExists & (1 << i)) { + numPriStreams++; + dataSyncBufs[numPriStreams-1].trafficClass = i; + } + } + + UNLOCK_WMI(wmip); + + /* dataSyncBufs is now filled with entries (starting at index 0) containing valid streamIDs */ + + do { + /* + * We allocate all network buffers needed so we will be able to + * send all required frames. + */ + cmd_osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (cmd_osbuf == NULL) { + status = A_NO_MEMORY; + break; + } + + A_NETBUF_PUT(cmd_osbuf, sizeof(*cmd)); + + cmd = (WMI_SYNC_CMD *)(A_NETBUF_DATA(cmd_osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + /* In the SYNC cmd sent on the control Ep, send a bitmap of the data + * eps on which the Data Sync will be sent + */ + cmd->dataSyncMap = wmip->wmi_fatPipeExists; + + for (i=0; i < numPriStreams ; i++) { + dataSyncBufs[i].osbuf = A_NETBUF_ALLOC(0); + if (dataSyncBufs[i].osbuf == NULL) { + status = A_NO_MEMORY; + break; + } + } //end for + + /* if Buffer allocation for any of the dataSync fails, then do not + * send the Synchronize cmd on the control ep + */ + if (A_FAILED(status)) { + break; + } + + /* + * Send sync cmd followed by sync data messages on all endpoints being + * used + */ + status = wmi_cmd_send(wmip, cmd_osbuf, WMI_SYNCHRONIZE_CMDID, + NO_SYNC_WMIFLAG); + + if (A_FAILED(status)) { + break; + } + /* cmd buffer sent, we no longer own it */ + cmd_osbuf = NULL; + + for(i=0; i < numPriStreams; i++) { + A_ASSERT(dataSyncBufs[i].osbuf != NULL); + status = wmi_dataSync_send(wmip, + dataSyncBufs[i].osbuf, + A_WMI_Ac2EndpointID(wmip->wmi_devt, + dataSyncBufs[i]. + trafficClass) + ); + + if (A_FAILED(status)) { + break; + } + /* we don't own this buffer anymore, NULL it out of the array so it + * won't get cleaned up */ + dataSyncBufs[i].osbuf = NULL; + } //end for + + } while(FALSE); + + /* free up any resources left over (possibly due to an error) */ + + if (cmd_osbuf != NULL) { + A_NETBUF_FREE(cmd_osbuf); + } + + for (i = 0; i < numPriStreams; i++) { + if (dataSyncBufs[i].osbuf != NULL) { + A_NETBUF_FREE(dataSyncBufs[i].osbuf); + } + } + + return (status); +} + +A_STATUS +wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *params) +{ + void *osbuf; + WMI_CREATE_PSTREAM_CMD *cmd; + A_UINT8 fatPipeExistsForAC=0; + + /* Validate all the parameters. */ + if( !((params->userPriority < 8) && + (params->userPriority <= 0x7) && + (convert_userPriority_to_trafficClass(params->userPriority) == params->trafficClass) && + (params->trafficDirection == UPLINK_TRAFFIC || + params->trafficDirection == DNLINK_TRAFFIC || + params->trafficDirection == BIDIR_TRAFFIC) && + (params->trafficType == TRAFFIC_TYPE_APERIODIC || + params->trafficType == TRAFFIC_TYPE_PERIODIC ) && + (params->voicePSCapability == DISABLE_FOR_THIS_AC || + params->voicePSCapability == ENABLE_FOR_THIS_AC || + params->voicePSCapability == ENABLE_FOR_ALL_AC) && + (params->tsid == WMI_IMPLICIT_PSTREAM || params->tsid <= WMI_MAX_THINSTREAM)) ) + { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + A_DPRINTF(DBG_WMI, + (DBGFMT "Sending create_pstream_cmd: ac=%d tsid:%d\n", DBGARG, + params->trafficClass, params->tsid)); + + cmd = (WMI_CREATE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + A_MEMCPY(cmd, params, sizeof(*cmd)); + + /* this is an implicitly created Fat pipe */ + if (params->tsid == WMI_IMPLICIT_PSTREAM) { + LOCK_WMI(wmip); + fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass)); + wmip->wmi_fatPipeExists |= (1<trafficClass); + UNLOCK_WMI(wmip); + } else { + /* this is an explicitly created thin stream within a fat pipe */ + LOCK_WMI(wmip); + fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass)); + wmip->wmi_streamExistsForAC[params->trafficClass] |= (1<tsid); + /* if a thinstream becomes active, the fat pipe automatically + * becomes active + */ + wmip->wmi_fatPipeExists |= (1<trafficClass); + UNLOCK_WMI(wmip); + } + + /* Indicate activty change to driver layer only if this is the + * first TSID to get created in this AC explicitly or an implicit + * fat pipe is getting created. + */ + if (!fatPipeExistsForAC) { + A_WMI_STREAM_TX_ACTIVE(wmip->wmi_devt, params->trafficClass); + } + + /* mike: should be SYNC_BEFORE_WMIFLAG */ + return (wmi_cmd_send(wmip, osbuf, WMI_CREATE_PSTREAM_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 tsid) +{ + void *osbuf; + WMI_DELETE_PSTREAM_CMD *cmd; + A_STATUS status; + A_UINT16 activeTsids=0; + + /* validate the parameters */ + if (trafficClass > 3) { + A_DPRINTF(DBG_WMI, (DBGFMT "Invalid trafficClass: %d\n", DBGARG, trafficClass)); + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DELETE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->trafficClass = trafficClass; + cmd->tsid = tsid; + + LOCK_WMI(wmip); + activeTsids = wmip->wmi_streamExistsForAC[trafficClass]; + UNLOCK_WMI(wmip); + + /* Check if the tsid was created & exists */ + if (!(activeTsids & (1<wmi_streamExistsForAC[trafficClass] &= ~(1<wmi_streamExistsForAC[trafficClass]; + UNLOCK_WMI(wmip); + + + /* Indicate stream inactivity to driver layer only if all tsids + * within this AC are deleted. + */ + if(!activeTsids) { + A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, trafficClass); + LOCK_WMI(wmip); + wmip->wmi_fatPipeExists &= ~(1<rateIndex = index; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BITRATE_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_bitrate_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_BITRATE_CMDID); +} + +/* + * Returns TRUE iff the given rate index is legal in the current PHY mode. + */ +A_BOOL +wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_INT32 rateIndex) +{ + WMI_PHY_MODE phyMode = (WMI_PHY_MODE) wmip->wmi_phyMode; + A_BOOL isValid = TRUE; + switch(phyMode) { + case WMI_11A_MODE: + if ((rateIndex < MODE_A_SUPPORT_RATE_START) || (rateIndex > MODE_A_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + + case WMI_11B_MODE: + if ((rateIndex < MODE_B_SUPPORT_RATE_START) || (rateIndex > MODE_B_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + + case WMI_11GONLY_MODE: + if ((rateIndex < MODE_GONLY_SUPPORT_RATE_START) || (rateIndex > MODE_GONLY_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + + case WMI_11G_MODE: + case WMI_11AG_MODE: + if ((rateIndex < MODE_G_SUPPORT_RATE_START) || (rateIndex > MODE_G_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + + default: + A_ASSERT(FALSE); + break; + } + + return isValid; +} + +A_INT8 +wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate) +{ + A_INT8 i; + if (rate != -1) + { + for (i=0;;i++) + { + if (wmi_rateTable[(A_UINT32) i] == 0) { + return A_EINVAL; + } + if (wmi_rateTable[(A_UINT32) i] == rate) { + break; + } + } + } + else{ + i = -1; + } + + if(wmi_is_bitrate_index_valid(wmip, (A_INT32) i) != TRUE) { + return A_EINVAL; + } + + return i; +} + +A_STATUS +wmi_set_fixrates_cmd(struct wmi_t *wmip, A_INT16 fixRatesMask) +{ + void *osbuf; + WMI_FIX_RATES_CMD *cmd; + A_INT32 rateIndex; + + /* Make sure all rates in the mask are valid in the current PHY mode */ + for(rateIndex = 0; rateIndex < MAX_NUMBER_OF_SUPPORT_RATES; rateIndex++) { + if((1 << rateIndex) & (A_UINT32)fixRatesMask) { + if(wmi_is_bitrate_index_valid(wmip, rateIndex) != TRUE) { + A_DPRINTF(DBG_WMI, (DBGFMT "Set Fix Rates command failed: Given rate is illegal in current PHY mode\n", DBGARG)); + return A_EINVAL; + } + } + } + + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_FIX_RATES_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->fixRateMask = fixRatesMask; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_FIXRATES_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_ratemask_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_FIXRATES_CMDID); +} + +A_STATUS +wmi_get_channelList_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_CHANNEL_LIST_CMDID); +} + +/* + * used to generate a wmi sey channel Parameters cmd. + * mode should always be specified and corresponds to the phy mode of the + * wlan. + * numChan should alway sbe specified. If zero indicates that all available + * channels should be used. + * channelList is an array of channel frequencies (in Mhz) which the radio + * should limit its operation to. It should be NULL if numChan == 0. Size of + * array should correspond to numChan entries. + */ +A_STATUS +wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam, + WMI_PHY_MODE mode, A_INT8 numChan, + A_UINT16 *channelList) +{ + void *osbuf; + WMI_CHANNEL_PARAMS_CMD *cmd; + A_INT8 size; + + size = sizeof (*cmd); + + if (numChan) { + if (numChan > WMI_MAX_CHANNELS) { + return A_EINVAL; + } + size += sizeof(A_UINT16) * (numChan - 1); + } + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_CHANNEL_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + wmip->wmi_phyMode = mode; + cmd->scanParam = scanParam; + cmd->phyMode = mode; + cmd->numChannels = numChan; + A_MEMCPY(cmd->channelList, channelList, numChan * sizeof(A_UINT16)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_CHANNEL_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +void +wmi_cache_configure_rssithreshold(struct wmi_t *wmip, WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd) +{ + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_RSSI]; + /* + * Parse the command and store the threshold values here. The checks + * for valid values can be put here + */ + sq_thresh->weight = rssiCmd->weight; + sq_thresh->polling_interval = rssiCmd->pollTime; + + sq_thresh->upper_threshold[0] = rssiCmd->thresholdAbove1_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[1] = rssiCmd->thresholdAbove2_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[2] = rssiCmd->thresholdAbove3_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[3] = rssiCmd->thresholdAbove4_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[4] = rssiCmd->thresholdAbove5_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[5] = rssiCmd->thresholdAbove6_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold_valid_count = 6; + + /* List sorted in descending order */ + sq_thresh->lower_threshold[0] = rssiCmd->thresholdBelow6_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[1] = rssiCmd->thresholdBelow5_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[2] = rssiCmd->thresholdBelow4_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[3] = rssiCmd->thresholdBelow3_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[4] = rssiCmd->thresholdBelow2_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[5] = rssiCmd->thresholdBelow1_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold_valid_count = 6; + + /* + * Configuring the thresholds to their extremes allows the host to get an + * event from the target which is used for the configuring the correct + * thresholds + */ + rssiCmd->thresholdAbove1_Val = sq_thresh->upper_threshold[0]; + rssiCmd->thresholdBelow1_Val = sq_thresh->lower_threshold[0]; +} + +A_STATUS +wmi_set_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd) +{ + /* Check these values are in ascending order */ + if( rssiCmd->thresholdAbove6_Val <= rssiCmd->thresholdAbove5_Val || + rssiCmd->thresholdAbove5_Val <= rssiCmd->thresholdAbove4_Val || + rssiCmd->thresholdAbove4_Val <= rssiCmd->thresholdAbove3_Val || + rssiCmd->thresholdAbove3_Val <= rssiCmd->thresholdAbove2_Val || + rssiCmd->thresholdAbove2_Val <= rssiCmd->thresholdAbove1_Val || + rssiCmd->thresholdBelow6_Val <= rssiCmd->thresholdBelow5_Val || + rssiCmd->thresholdBelow5_Val <= rssiCmd->thresholdBelow4_Val || + rssiCmd->thresholdBelow4_Val <= rssiCmd->thresholdBelow3_Val || + rssiCmd->thresholdBelow3_Val <= rssiCmd->thresholdBelow2_Val || + rssiCmd->thresholdBelow2_Val <= rssiCmd->thresholdBelow1_Val) + { + return A_EINVAL; + } + + wmi_cache_configure_rssithreshold(wmip, rssiCmd); + + return (wmi_send_rssi_threshold_params(wmip, rssiCmd)); +} + +A_STATUS +wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip, + WMI_SET_HOST_SLEEP_MODE_CMD *hostModeCmd) +{ + void *osbuf; + A_INT8 size; + WMI_SET_HOST_SLEEP_MODE_CMD *cmd; + A_UINT16 activeTsids=0; + A_UINT8 streamExists=0; + A_UINT8 i; + + if( hostModeCmd->awake == hostModeCmd->asleep) { + return A_EINVAL; + } + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_SET_HOST_SLEEP_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, hostModeCmd, sizeof(WMI_SET_HOST_SLEEP_MODE_CMD)); + + if(hostModeCmd->asleep) { + /* + * Relinquish credits from all implicitly created pstreams since when we + * go to sleep. If user created explicit thinstreams exists with in a + * fatpipe leave them intact for the user to delete + */ + LOCK_WMI(wmip); + streamExists = wmip->wmi_fatPipeExists; + UNLOCK_WMI(wmip); + + for(i=0;i< WMM_NUM_AC;i++) { + if (streamExists & (1<wmi_streamExistsForAC[i]; + UNLOCK_WMI(wmip); + /* If there are no user created thin streams delete the fatpipe */ + if(!activeTsids) { + streamExists &= ~(1<wmi_devt,i); + } + } + } + + /* Update the fatpipes that exists*/ + LOCK_WMI(wmip); + wmip->wmi_fatPipeExists = streamExists; + UNLOCK_WMI(wmip); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_HOST_SLEEP_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_wow_mode_cmd(struct wmi_t *wmip, + WMI_SET_WOW_MODE_CMD *wowModeCmd) +{ + void *osbuf; + A_INT8 size; + WMI_SET_WOW_MODE_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_SET_WOW_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, wowModeCmd, sizeof(WMI_SET_WOW_MODE_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WOW_MODE_CMDID, + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_get_wow_list_cmd(struct wmi_t *wmip, + WMI_GET_WOW_LIST_CMD *wowListCmd) +{ + void *osbuf; + A_INT8 size; + WMI_GET_WOW_LIST_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_GET_WOW_LIST_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, wowListCmd, sizeof(WMI_GET_WOW_LIST_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_GET_WOW_LIST_CMDID, + NO_SYNC_WMIFLAG)); + +} + +static A_STATUS +wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_GET_WOW_LIST_REPLY *reply; + + if (len < sizeof(WMI_GET_WOW_LIST_REPLY)) { + return A_EINVAL; + } + reply = (WMI_GET_WOW_LIST_REPLY *)datap; + + A_WMI_WOW_LIST_EVENT(wmip->wmi_devt, reply->num_filters, + reply); + + return A_OK; +} + +A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip, + WMI_ADD_WOW_PATTERN_CMD *addWowCmd, + A_UINT8* pattern, A_UINT8* mask, + A_UINT8 pattern_size) +{ + void *osbuf; + A_INT8 size; + WMI_ADD_WOW_PATTERN_CMD *cmd; + A_UINT8 *filter_mask = NULL; + + size = sizeof (*cmd); + + size += ((2 * addWowCmd->filter_size)* sizeof(A_UINT8)); + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_ADD_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->filter_list_id = addWowCmd->filter_list_id; + cmd->filter_offset = addWowCmd->filter_offset; + cmd->filter_size = addWowCmd->filter_size; + + A_MEMCPY(cmd->filter, pattern, addWowCmd->filter_size); + + filter_mask = (A_UINT8*)(cmd->filter + cmd->filter_size); + A_MEMCPY(filter_mask, mask, addWowCmd->filter_size); + + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_WOW_PATTERN_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_del_wow_pattern_cmd(struct wmi_t *wmip, + WMI_DEL_WOW_PATTERN_CMD *delWowCmd) +{ + void *osbuf; + A_INT8 size; + WMI_DEL_WOW_PATTERN_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_DEL_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, delWowCmd, sizeof(WMI_DEL_WOW_PATTERN_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_DEL_WOW_PATTERN_CMDID, + NO_SYNC_WMIFLAG)); + +} + +void +wmi_cache_configure_snrthreshold(struct wmi_t *wmip, WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd) +{ + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_SNR]; + /* + * Parse the command and store the threshold values here. The checks + * for valid values can be put here + */ + sq_thresh->weight = snrCmd->weight; + sq_thresh->polling_interval = snrCmd->pollTime; + + sq_thresh->upper_threshold[0] = snrCmd->thresholdAbove1_Val; + sq_thresh->upper_threshold[1] = snrCmd->thresholdAbove2_Val; + sq_thresh->upper_threshold[2] = snrCmd->thresholdAbove3_Val; + sq_thresh->upper_threshold[3] = snrCmd->thresholdAbove4_Val; + sq_thresh->upper_threshold_valid_count = 4; + + /* List sorted in descending order */ + sq_thresh->lower_threshold[0] = snrCmd->thresholdBelow4_Val; + sq_thresh->lower_threshold[1] = snrCmd->thresholdBelow3_Val; + sq_thresh->lower_threshold[2] = snrCmd->thresholdBelow2_Val; + sq_thresh->lower_threshold[3] = snrCmd->thresholdBelow1_Val; + sq_thresh->lower_threshold_valid_count = 4; + + /* + * Configuring the thresholds to their extremes allows the host to get an + * event from the target which is used for the configuring the correct + * thresholds + */ + snrCmd->thresholdAbove1_Val = (A_UINT8)sq_thresh->upper_threshold[0]; + snrCmd->thresholdBelow1_Val = (A_UINT8)sq_thresh->lower_threshold[0]; +} +A_STATUS +wmi_set_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd) +{ + if( snrCmd->thresholdAbove4_Val <= snrCmd->thresholdAbove3_Val || + snrCmd->thresholdAbove3_Val <= snrCmd->thresholdAbove2_Val || + snrCmd->thresholdAbove2_Val <= snrCmd->thresholdAbove1_Val || + snrCmd->thresholdBelow4_Val <= snrCmd->thresholdBelow3_Val || + snrCmd->thresholdBelow3_Val <= snrCmd->thresholdBelow2_Val || + snrCmd->thresholdBelow2_Val <= snrCmd->thresholdBelow1_Val) + { + return A_EINVAL; + } + wmi_cache_configure_snrthreshold(wmip, snrCmd); + return (wmi_send_snr_threshold_params(wmip, snrCmd)); +} + +A_STATUS +wmi_clr_rssi_snr(struct wmi_t *wmip) +{ + void *osbuf; + + osbuf = A_NETBUF_ALLOC(sizeof(int)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + return (wmi_cmd_send(wmip, osbuf, WMI_CLR_RSSI_SNR_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_lq_threshold_params(struct wmi_t *wmip, + WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd) +{ + void *osbuf; + A_INT8 size; + WMI_LQ_THRESHOLD_PARAMS_CMD *cmd; + /* These values are in ascending order */ + if( lqCmd->thresholdAbove4_Val <= lqCmd->thresholdAbove3_Val || + lqCmd->thresholdAbove3_Val <= lqCmd->thresholdAbove2_Val || + lqCmd->thresholdAbove2_Val <= lqCmd->thresholdAbove1_Val || + lqCmd->thresholdBelow4_Val <= lqCmd->thresholdBelow3_Val || + lqCmd->thresholdBelow3_Val <= lqCmd->thresholdBelow2_Val || + lqCmd->thresholdBelow2_Val <= lqCmd->thresholdBelow1_Val ) { + + return A_EINVAL; + } + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_LQ_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, lqCmd, sizeof(WMI_LQ_THRESHOLD_PARAMS_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_LQ_THRESHOLD_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 mask) +{ + void *osbuf; + A_INT8 size; + WMI_TARGET_ERROR_REPORT_BITMASK *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_TARGET_ERROR_REPORT_BITMASK *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + cmd->bitmask = mask; + + return (wmi_cmd_send(wmip, osbuf, WMI_TARGET_ERROR_REPORT_BITMASK_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie, A_UINT32 source) +{ + void *osbuf; + WMIX_HB_CHALLENGE_RESP_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_HB_CHALLENGE_RESP_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->cookie = cookie; + cmd->source = source; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_HB_CHALLENGE_RESP_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask, + A_UINT16 tsr, A_BOOL rep, A_UINT16 size, + A_UINT32 valid) +{ + void *osbuf; + WMIX_DBGLOG_CFG_MODULE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_DBGLOG_CFG_MODULE_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->config.cfgmmask = mmask; + cmd->config.cfgtsr = tsr; + cmd->config.cfgrep = rep; + cmd->config.cfgsize = size; + cmd->config.cfgvalid = valid; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DBGLOG_CFG_MODULE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_stats_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_STATISTICS_CMDID); +} + +A_STATUS +wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid) +{ + void *osbuf; + WMI_ADD_BAD_AP_CMD *cmd; + + if ((bssid == NULL) || (apIndex > WMI_MAX_BAD_AP_INDEX)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_ADD_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->badApIndex = apIndex; + A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid)); + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_BAD_AP_CMDID, SYNC_BEFORE_WMIFLAG)); +} + +A_STATUS +wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex) +{ + void *osbuf; + WMI_DELETE_BAD_AP_CMD *cmd; + + if (apIndex > WMI_MAX_BAD_AP_INDEX) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DELETE_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->badApIndex = apIndex; + + return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_BAD_AP_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_abort_scan_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_ABORT_SCAN_CMDID); +} + +A_STATUS +wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM) +{ + void *osbuf; + WMI_SET_TX_PWR_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_TX_PWR_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->dbM = dbM; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_TX_PWR_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_txPwr_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_TX_PWR_CMDID); +} + +A_UINT16 +wmi_get_mapped_qos_queue(struct wmi_t *wmip, A_UINT8 trafficClass) +{ + A_UINT16 activeTsids=0; + + LOCK_WMI(wmip); + activeTsids = wmip->wmi_streamExistsForAC[trafficClass]; + UNLOCK_WMI(wmip); + + return activeTsids; +} + +A_STATUS +wmi_get_roam_tbl_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_ROAM_TBL_CMDID); +} + +A_STATUS +wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType) +{ + void *osbuf; + A_UINT32 size = sizeof(A_UINT8); + WMI_TARGET_ROAM_DATA *cmd; + + osbuf = A_NETBUF_ALLOC(size); /* no payload */ + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_TARGET_ROAM_DATA *)(A_NETBUF_DATA(osbuf)); + cmd->roamDataType = roamDataType; + + return (wmi_cmd_send(wmip, osbuf, WMI_GET_ROAM_DATA_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p, + A_UINT8 size) +{ + void *osbuf; + WMI_SET_ROAM_CTRL_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_SET_ROAM_CTRL_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + A_MEMCPY(cmd, p, size); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_ROAM_CTRL_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_powersave_timers_cmd(struct wmi_t *wmip, + WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd, + A_UINT8 size) +{ + void *osbuf; + WMI_POWERSAVE_TIMERS_POLICY_CMD *cmd; + + /* These timers can't be zero */ + if(!pCmd->psPollTimeout || !pCmd->triggerTimeout || + !(pCmd->apsdTimPolicy == IGNORE_TIM_ALL_QUEUES_APSD || + pCmd->apsdTimPolicy == PROCESS_TIM_ALL_QUEUES_APSD) || + !(pCmd->simulatedAPSDTimPolicy == IGNORE_TIM_SIMULATED_APSD || + pCmd->simulatedAPSDTimPolicy == PROCESS_TIM_SIMULATED_APSD)) + return A_EINVAL; + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_POWERSAVE_TIMERS_POLICY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + A_MEMCPY(cmd, pCmd, size); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID, + NO_SYNC_WMIFLAG)); +} + +#ifdef CONFIG_HOST_GPIO_SUPPORT +/* Send a command to Target to change GPIO output pins. */ +A_STATUS +wmi_gpio_output_set(struct wmi_t *wmip, + A_UINT32 set_mask, + A_UINT32 clear_mask, + A_UINT32 enable_mask, + A_UINT32 disable_mask) +{ + void *osbuf; + WMIX_GPIO_OUTPUT_SET_CMD *output_set; + int size; + + size = sizeof(*output_set); + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - set=0x%x clear=0x%x enb=0x%x dis=0x%x\n", DBGARG, + set_mask, clear_mask, enable_mask, disable_mask)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + output_set = (WMIX_GPIO_OUTPUT_SET_CMD *)(A_NETBUF_DATA(osbuf)); + + output_set->set_mask = set_mask; + output_set->clear_mask = clear_mask; + output_set->enable_mask = enable_mask; + output_set->disable_mask = disable_mask; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_OUTPUT_SET_CMDID, + NO_SYNC_WMIFLAG)); +} + +/* Send a command to the Target requesting state of the GPIO input pins */ +A_STATUS +wmi_gpio_input_get(struct wmi_t *wmip) +{ + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + return wmi_simple_cmd_xtnd(wmip, WMIX_GPIO_INPUT_GET_CMDID); +} + +/* Send a command to the Target that changes the value of a GPIO register. */ +A_STATUS +wmi_gpio_register_set(struct wmi_t *wmip, + A_UINT32 gpioreg_id, + A_UINT32 value) +{ + void *osbuf; + WMIX_GPIO_REGISTER_SET_CMD *register_set; + int size; + + size = sizeof(*register_set); + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG, gpioreg_id, value)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + register_set = (WMIX_GPIO_REGISTER_SET_CMD *)(A_NETBUF_DATA(osbuf)); + + register_set->gpioreg_id = gpioreg_id; + register_set->value = value; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_SET_CMDID, + NO_SYNC_WMIFLAG)); +} + +/* Send a command to the Target to fetch the value of a GPIO register. */ +A_STATUS +wmi_gpio_register_get(struct wmi_t *wmip, + A_UINT32 gpioreg_id) +{ + void *osbuf; + WMIX_GPIO_REGISTER_GET_CMD *register_get; + int size; + + size = sizeof(*register_get); + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter - reg=%d\n", DBGARG, gpioreg_id)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + register_get = (WMIX_GPIO_REGISTER_GET_CMD *)(A_NETBUF_DATA(osbuf)); + + register_get->gpioreg_id = gpioreg_id; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_GET_CMDID, + NO_SYNC_WMIFLAG)); +} + +/* Send a command to the Target acknowledging some GPIO interrupts. */ +A_STATUS +wmi_gpio_intr_ack(struct wmi_t *wmip, + A_UINT32 ack_mask) +{ + void *osbuf; + WMIX_GPIO_INTR_ACK_CMD *intr_ack; + int size; + + size = sizeof(*intr_ack); + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter ack_mask=0x%x\n", DBGARG, ack_mask)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + intr_ack = (WMIX_GPIO_INTR_ACK_CMD *)(A_NETBUF_DATA(osbuf)); + + intr_ack->ack_mask = ack_mask; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_INTR_ACK_CMDID, + NO_SYNC_WMIFLAG)); +} +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +A_STATUS +wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT16 txop, A_UINT8 eCWmin, + A_UINT8 eCWmax, A_UINT8 aifsn) +{ + void *osbuf; + WMI_SET_ACCESS_PARAMS_CMD *cmd; + + if ((eCWmin > WMI_MAX_CW_ACPARAM) || (eCWmax > WMI_MAX_CW_ACPARAM) || + (aifsn > WMI_MAX_AIFSN_ACPARAM)) + { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_ACCESS_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->txop = txop; + cmd->eCWmin = eCWmin; + cmd->eCWmax = eCWmax; + cmd->aifsn = aifsn; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_ACCESS_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType, + A_UINT8 trafficClass, A_UINT8 maxRetries, + A_UINT8 enableNotify) +{ + void *osbuf; + WMI_SET_RETRY_LIMITS_CMD *cmd; + + if ((frameType != MGMT_FRAMETYPE) && (frameType != CONTROL_FRAMETYPE) && + (frameType != DATA_FRAMETYPE)) + { + return A_EINVAL; + } + + if (maxRetries > WMI_MAX_RETRIES) { + return A_EINVAL; + } + + if (frameType != DATA_FRAMETYPE) { + trafficClass = 0; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_RETRY_LIMITS_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->frameType = frameType; + cmd->trafficClass = trafficClass; + cmd->maxRetries = maxRetries; + cmd->enableNotify = enableNotify; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_RETRY_LIMITS_CMDID, + NO_SYNC_WMIFLAG)); +} + +void +wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid) +{ + if (bssid != NULL) { + A_MEMCPY(bssid, wmip->wmi_bssid, ATH_MAC_LEN); + } +} + +A_STATUS +wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode) +{ + void *osbuf; + WMI_SET_OPT_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_OPT_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->optMode = optMode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_OPT_MODE_CMDID, + SYNC_BOTH_WMIFLAG)); +} + +A_STATUS +wmi_opt_tx_frame_cmd(struct wmi_t *wmip, + A_UINT8 frmType, + A_UINT8 *dstMacAddr, + A_UINT8 *bssid, + A_UINT16 optIEDataLen, + A_UINT8 *optIEData) +{ + void *osbuf; + WMI_OPT_TX_FRAME_CMD *cmd; + osbuf = A_NETBUF_ALLOC(optIEDataLen + sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, (optIEDataLen + sizeof(*cmd))); + + cmd = (WMI_OPT_TX_FRAME_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, (optIEDataLen + sizeof(*cmd)-1)); + + cmd->frmType = frmType; + cmd->optIEDataLen = optIEDataLen; + //cmd->optIEData = (A_UINT8 *)((int)cmd + sizeof(*cmd)); + A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid)); + A_MEMCPY(cmd->dstAddr, dstMacAddr, sizeof(cmd->dstAddr)); + A_MEMCPY(&cmd->optIEData[0], optIEData, optIEDataLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_OPT_TX_FRAME_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl) +{ + void *osbuf; + WMI_BEACON_INT_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_BEACON_INT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->beaconInterval = intvl; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BEACON_INT_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize) +{ + void *osbuf; + WMI_SET_VOICE_PKT_SIZE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_VOICE_PKT_SIZE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->voicePktSize = voicePktSize; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_VOICE_PKT_SIZE_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSPLen) +{ + void *osbuf; + WMI_SET_MAX_SP_LEN_CMD *cmd; + + /* maxSPLen is a two-bit value. If user trys to set anything + * other than this, then its invalid + */ + if(maxSPLen & ~0x03) + return A_EINVAL; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_MAX_SP_LEN_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->maxSPLen = maxSPLen; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_MAX_SP_LEN_CMDID, + NO_SYNC_WMIFLAG)); +} + +static A_UINT8 +ar6000_determine_userPriority( + A_UINT8 *pkt, + A_UINT32 layer2Pri) +{ + A_UINT8 ipPri; + iphdr *ipHdr = (iphdr *)pkt; + + /* Determine IPTOS priority */ + /* + * IP Tos format : + * (Refer Pg 57 WMM-test-plan-v1.2) + * IP-TOS - 8bits + * : DSCP(6-bits) ECN(2-bits) + * : DSCP - P2 P1 P0 X X X + * where (P2 P1 P0) form 802.1D + */ + ipPri = ipHdr->ip_tos >> 5; + ipPri &= 0x7; + + if ((layer2Pri & 0x7) > ipPri) + return ((A_UINT8)layer2Pri & 0x7); + else + return ipPri; +} + +A_UINT8 +convert_userPriority_to_trafficClass(A_UINT8 userPriority) +{ + return (up_to_ac[userPriority & 0x7]); +} + +A_UINT8 +wmi_get_power_mode_cmd(struct wmi_t *wmip) +{ + return wmip->wmi_powerMode; +} + +A_STATUS +wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance) +{ + A_STATUS ret = A_OK; + +#define TSPEC_SUSPENSION_INTERVAL_ATHEROS_DEF (~0) +#define TSPEC_SERVICE_START_TIME_ATHEROS_DEF 0 +#define TSPEC_MAX_BURST_SIZE_ATHEROS_DEF 0 +#define TSPEC_DELAY_BOUND_ATHEROS_DEF 0 +#define TSPEC_MEDIUM_TIME_ATHEROS_DEF 0 +#define TSPEC_SBA_ATHEROS_DEF 0x2000 /* factor is 1 */ + + /* Verify TSPEC params for ATHEROS compliance */ + if(tspecCompliance == ATHEROS_COMPLIANCE) { + if ((pCmd->suspensionInt != TSPEC_SUSPENSION_INTERVAL_ATHEROS_DEF) || + (pCmd->serviceStartTime != TSPEC_SERVICE_START_TIME_ATHEROS_DEF) || + (pCmd->minDataRate != pCmd->meanDataRate) || + (pCmd->minDataRate != pCmd->peakDataRate) || + (pCmd->maxBurstSize != TSPEC_MAX_BURST_SIZE_ATHEROS_DEF) || + (pCmd->delayBound != TSPEC_DELAY_BOUND_ATHEROS_DEF) || + (pCmd->sba != TSPEC_SBA_ATHEROS_DEF) || + (pCmd->mediumTime != TSPEC_MEDIUM_TIME_ATHEROS_DEF)) { + + A_DPRINTF(DBG_WMI, (DBGFMT "Invalid TSPEC params\n", DBGARG)); + //A_PRINTF("%s: Invalid TSPEC params\n", __func__); + ret = A_EINVAL; + } + } + + return ret; +} + +#ifdef CONFIG_HOST_TCMD_SUPPORT +static A_STATUS +wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TCMD_RX_REPORT_EVENT(wmip->wmi_devt, datap, len); + + return A_OK; +} + +#endif /* CONFIG_HOST_TCMD_SUPPORT*/ + +A_STATUS +wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode) +{ + void *osbuf; + WMI_SET_AUTH_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_AUTH_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->mode = mode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_AUTH_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode) +{ + void *osbuf; + WMI_SET_REASSOC_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_REASSOC_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->mode = mode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_REASSOC_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status) +{ + void *osbuf; + WMI_SET_LPREAMBLE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_LPREAMBLE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->status = status; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_LPREAMBLE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold) +{ + void *osbuf; + WMI_SET_RTS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_RTS_CMD*)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->threshold = threshold; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_RTS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status) +{ + void *osbuf; + WMI_SET_WMM_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_WMM_CMD*)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->status = status; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_CMDID, + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG cfg) +{ + void *osbuf; + WMI_SET_WMM_TXOP_CMD *cmd; + + if( !((cfg == WMI_TXOP_DISABLED) || (cfg == WMI_TXOP_ENABLED)) ) + return A_EINVAL; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_WMM_TXOP_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->txopEnable = cfg; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_TXOP_CMDID, + NO_SYNC_WMIFLAG)); + +} + +#ifdef CONFIG_HOST_TCMD_SUPPORT +/* WMI layer doesn't need to know the data type of the test cmd. + This would be beneficial for customers like Qualcomm, who might + have different test command requirements from differnt manufacturers + */ +A_STATUS +wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32 len) +{ + void *osbuf; + char *data; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + osbuf= A_NETBUF_ALLOC(len); + if(osbuf == NULL) + { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, len); + data = A_NETBUF_DATA(osbuf); + A_MEMCPY(data, buf, len); + + return(wmi_cmd_send(wmip, osbuf, WMI_TEST_CMDID, + NO_SYNC_WMIFLAG)); +} + +#endif + +A_STATUS +wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status) +{ + void *osbuf; + WMI_SET_BT_STATUS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_BT_STATUS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->streamType = streamType; + cmd->status = status; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_STATUS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd) +{ + void *osbuf; + WMI_SET_BT_PARAMS_CMD* alloc_cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + alloc_cmd = (WMI_SET_BT_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(alloc_cmd, sizeof(*cmd)); + A_MEMCPY(alloc_cmd, cmd, sizeof(*cmd)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_keepalive_configured(struct wmi_t *wmip) +{ + void *osbuf; + WMI_GET_KEEPALIVE_CMD *cmd; + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + cmd = (WMI_GET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + return (wmi_cmd_send(wmip, osbuf, WMI_GET_KEEPALIVE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_UINT8 +wmi_get_keepalive_cmd(struct wmi_t *wmip) +{ + return wmip->wmi_keepaliveInterval; +} + +A_STATUS +wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval) +{ + void *osbuf; + WMI_SET_KEEPALIVE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->keepaliveInterval = keepaliveInterval; + wmip->wmi_keepaliveInterval = keepaliveInterval; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_KEEPALIVE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType, A_UINT8 ieLen, + A_UINT8 *ieInfo) +{ + void *osbuf; + WMI_SET_APPIE_CMD *cmd; + A_UINT16 cmdLen; + + cmdLen = sizeof(*cmd) + ieLen - 1; + osbuf = A_NETBUF_ALLOC(cmdLen); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, cmdLen); + + cmd = (WMI_SET_APPIE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + + cmd->mgmtFrmType = mgmtFrmType; + cmd->ieLen = ieLen; + A_MEMCPY(cmd->ieInfo, ieInfo, ieLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_APPIE_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen) +{ + void *osbuf; + A_UINT8 *data; + + osbuf = A_NETBUF_ALLOC(dataLen); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, dataLen); + + data = A_NETBUF_DATA(osbuf); + + A_MEMCPY(data, cmd, dataLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WHALPARAM_CMDID, NO_SYNC_WMIFLAG)); +} + +A_INT32 +wmi_get_rate(A_INT8 rateindex) +{ + if (rateindex == RATE_AUTO) { + return 0; + } else { + return(wmi_rateTable[(A_UINT32) rateindex]); + } +} + +void +wmi_node_return (struct wmi_t *wmip, bss_t *bss) +{ + if (NULL != bss) + { + wlan_node_return (&wmip->wmi_scan_table, bss); + } +} + +void +wmi_set_nodeage(struct wmi_t *wmip, A_UINT32 nodeAge) +{ + wlan_set_nodeage(&wmip->wmi_scan_table,nodeAge); +} + +bss_t * +wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID) +{ + bss_t *node = NULL; + node = wlan_find_Ssidnode (&wmip->wmi_scan_table, pSsid, + ssidLength, bIsWPA2, bMatchSSID); + return node; +} + +void +wmi_free_allnodes(struct wmi_t *wmip) +{ + wlan_free_allnodes(&wmip->wmi_scan_table); +} + +bss_t * +wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr) +{ + bss_t *ni=NULL; + ni=wlan_find_node(&wmip->wmi_scan_table,macaddr); + return ni; +} + +void +wmi_free_node(struct wmi_t *wmip, const A_UINT8 *macaddr) +{ + bss_t *ni=NULL; + + ni=wlan_find_node(&wmip->wmi_scan_table,macaddr); + if (ni != NULL) { + wlan_node_reclaim(&wmip->wmi_scan_table, ni); + } + + return; +} + +A_STATUS +wmi_dset_open_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT32 access_cookie, + A_UINT32 dset_size, + A_UINT32 dset_version, + A_UINT32 targ_handle, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg) +{ + void *osbuf; + WMIX_DSETOPEN_REPLY_CMD *open_reply; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter - wmip=0x%x\n", DBGARG, (int)wmip)); + + osbuf = A_NETBUF_ALLOC(sizeof(*open_reply)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*open_reply)); + open_reply = (WMIX_DSETOPEN_REPLY_CMD *)(A_NETBUF_DATA(osbuf)); + + open_reply->status = status; + open_reply->targ_dset_handle = targ_handle; + open_reply->targ_reply_fn = targ_reply_fn; + open_reply->targ_reply_arg = targ_reply_arg; + open_reply->access_cookie = access_cookie; + open_reply->size = dset_size; + open_reply->version = dset_version; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETOPEN_REPLY_CMDID, + NO_SYNC_WMIFLAG)); +} + +static A_STATUS +wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len) +{ + WMI_PMKID_LIST_REPLY *reply; + A_UINT32 expected_len; + + if (len < sizeof(WMI_PMKID_LIST_REPLY)) { + return A_EINVAL; + } + reply = (WMI_PMKID_LIST_REPLY *)datap; + expected_len = sizeof(reply->numPMKID) + reply->numPMKID * WMI_PMKID_LEN; + + if (len < expected_len) { + return A_EINVAL; + } + + A_WMI_PMKID_LIST_EVENT(wmip->wmi_devt, reply->numPMKID, + reply->pmkidList, reply->bssidList[0]); + + return A_OK; +} + +#ifdef CONFIG_HOST_DSET_SUPPORT +A_STATUS +wmi_dset_data_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT8 *user_buf, + A_UINT32 length, + A_UINT32 targ_buf, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg) +{ + void *osbuf; + WMIX_DSETDATA_REPLY_CMD *data_reply; + int size; + + size = sizeof(*data_reply) + length; + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - length=%d status=%d\n", DBGARG, length, status)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + data_reply = (WMIX_DSETDATA_REPLY_CMD *)(A_NETBUF_DATA(osbuf)); + + data_reply->status = status; + data_reply->targ_buf = targ_buf; + data_reply->targ_reply_fn = targ_reply_fn; + data_reply->targ_reply_arg = targ_reply_arg; + data_reply->length = length; + + if (status == A_OK) { + if (a_copy_from_user(data_reply->buf, user_buf, length)) { + return A_ERROR; + } + } + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETDATA_REPLY_CMDID, + NO_SYNC_WMIFLAG)); +} +#endif /* CONFIG_HOST_DSET_SUPPORT */ + +A_STATUS +wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status) +{ + void *osbuf; + char *cmd; + + wps_enable = status; + + osbuf = a_netbuf_alloc(sizeof(1)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + a_netbuf_put(osbuf, sizeof(1)); + + cmd = (char *)(a_netbuf_to_data(osbuf)); + + A_MEMZERO(cmd, sizeof(*cmd)); + cmd[0] = (status?1:0); + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WSC_STATUS_CMDID, + NO_SYNC_WMIFLAG)); +} + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +A_STATUS +wmi_prof_cfg_cmd(struct wmi_t *wmip, + A_UINT32 period, + A_UINT32 nbins) +{ + void *osbuf; + WMIX_PROF_CFG_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_PROF_CFG_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->period = period; + cmd->nbins = nbins; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_PROF_CFG_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_prof_addr_set_cmd(struct wmi_t *wmip, A_UINT32 addr) +{ + void *osbuf; + WMIX_PROF_ADDR_SET_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_PROF_ADDR_SET_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->addr = addr; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_PROF_ADDR_SET_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_prof_start_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_START_CMDID); +} + +A_STATUS +wmi_prof_stop_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_STOP_CMDID); +} + +A_STATUS +wmi_prof_count_get_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_COUNT_GET_CMDID); +} + +/* Called to handle WMIX_PROF_CONT_EVENTID */ +static A_STATUS +wmi_prof_count_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_PROF_COUNT_EVENT *prof_data = (WMIX_PROF_COUNT_EVENT *)datap; + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - addr=0x%x count=%d\n", DBGARG, + prof_data->addr, prof_data->count)); + + A_WMI_PROF_COUNT_RX(prof_data->addr, prof_data->count); + + return A_OK; +} +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + +#ifdef OS_ROAM_MANAGEMENT + +#define ETHERNET_MAC_ADDRESS_LENGTH 6 + +void +wmi_scan_indication (struct wmi_t *wmip) +{ + struct ieee80211_node_table *nt; + A_UINT32 gen; + A_UINT32 size; + A_UINT32 bsssize; + bss_t *bss; + A_UINT32 numbss; + PNDIS_802_11_BSSID_SCAN_INFO psi; + PBYTE pie; + NDIS_802_11_FIXED_IEs *pFixed; + NDIS_802_11_VARIABLE_IEs *pVar; + A_UINT32 RateSize; + + struct ar6kScanIndication + { + NDIS_802_11_STATUS_INDICATION ind; + NDIS_802_11_BSSID_SCAN_INFO_LIST slist; + } *pAr6kScanIndEvent; + + nt = &wmip->wmi_scan_table; + + ++nt->nt_si_gen; + + + gen = nt->nt_si_gen; + + size = offsetof(struct ar6kScanIndication, slist) + + offsetof(NDIS_802_11_BSSID_SCAN_INFO_LIST, BssidScanInfo); + + numbss = 0; + + IEEE80211_NODE_LOCK(nt); + + //calc size + for (bss = nt->nt_node_first; bss; bss = bss->ni_list_next) { + if (bss->ni_si_gen != gen) { + bsssize = offsetof(NDIS_802_11_BSSID_SCAN_INFO, Bssid) + offsetof(NDIS_WLAN_BSSID_EX, IEs); + bsssize = bsssize + sizeof(NDIS_802_11_FIXED_IEs); + +#ifdef SUPPORT_WPA2 + if (bss->ni_cie.ie_rsn) { + bsssize = bsssize + bss->ni_cie.ie_rsn[1] + 2; + } +#endif + if (bss->ni_cie.ie_wpa) { + bsssize = bsssize + bss->ni_cie.ie_wpa[1] + 2; + } + + // bsssize must be a multiple of 4 to maintain alignment. + bsssize = (bsssize + 3) & ~3; + + size += bsssize; + + numbss++; + } + } + + if (0 == numbss) + { +// RETAILMSG(1, (L"AR6K: scan indication: 0 bss\n")); + ar6000_scan_indication (wmip->wmi_devt, NULL, 0); + IEEE80211_NODE_UNLOCK (nt); + return; + } + + pAr6kScanIndEvent = A_MALLOC(size); + + if (NULL == pAr6kScanIndEvent) + { + IEEE80211_NODE_UNLOCK(nt); + return; + } + + A_MEMZERO(pAr6kScanIndEvent, size); + + //copy data + pAr6kScanIndEvent->ind.StatusType = Ndis802_11StatusType_BssidScanInfoList; + pAr6kScanIndEvent->slist.Version = 1; + pAr6kScanIndEvent->slist.NumItems = numbss; + + psi = &pAr6kScanIndEvent->slist.BssidScanInfo[0]; + + for (bss = nt->nt_node_first; bss; bss = bss->ni_list_next) { + if (bss->ni_si_gen != gen) { + + bss->ni_si_gen = gen; + + //Set scan time + psi->ScanTime = bss->ni_tstamp - WLAN_NODE_INACT_TIMEOUT_MSEC; + + // Copy data to bssid_ex + bsssize = offsetof(NDIS_WLAN_BSSID_EX, IEs); + bsssize = bsssize + sizeof(NDIS_802_11_FIXED_IEs); + +#ifdef SUPPORT_WPA2 + if (bss->ni_cie.ie_rsn) { + bsssize = bsssize + bss->ni_cie.ie_rsn[1] + 2; + } +#endif + if (bss->ni_cie.ie_wpa) { + bsssize = bsssize + bss->ni_cie.ie_wpa[1] + 2; + } + + // bsssize must be a multiple of 4 to maintain alignment. + bsssize = (bsssize + 3) & ~3; + + psi->Bssid.Length = bsssize; + + memcpy (psi->Bssid.MacAddress, bss->ni_macaddr, ETHERNET_MAC_ADDRESS_LENGTH); + + +//if (((bss->ni_macaddr[3] == 0xCE) && (bss->ni_macaddr[4] == 0xF0) && (bss->ni_macaddr[5] == 0xE7)) || +// ((bss->ni_macaddr[3] == 0x03) && (bss->ni_macaddr[4] == 0xE2) && (bss->ni_macaddr[5] == 0x70))) +// RETAILMSG (1, (L"%x\n",bss->ni_macaddr[5])); + + psi->Bssid.Ssid.SsidLength = 0; + pie = bss->ni_cie.ie_ssid; + + if (pie) { + // Format of SSID IE is: + // Type (1 octet) + // Length (1 octet) + // SSID (Length octets) + // + // Validation of the IE should have occurred within WMI. + // + if (pie[1] <= 32) { + psi->Bssid.Ssid.SsidLength = pie[1]; + memcpy(psi->Bssid.Ssid.Ssid, &pie[2], psi->Bssid.Ssid.SsidLength); + } + } + psi->Bssid.Privacy = (bss->ni_cie.ie_capInfo & 0x10) ? 1 : 0; + + //Post the RSSI value relative to the Standard Noise floor value. + psi->Bssid.Rssi = bss->ni_rssi; + + if (bss->ni_cie.ie_chan >= 2412 && bss->ni_cie.ie_chan <= 2484) { + + if (bss->ni_cie.ie_rates && bss->ni_cie.ie_xrates) { + psi->Bssid.NetworkTypeInUse = Ndis802_11OFDM24; + } + else { + psi->Bssid.NetworkTypeInUse = Ndis802_11DS; + } + } + else { + psi->Bssid.NetworkTypeInUse = Ndis802_11OFDM5; + } + + psi->Bssid.Configuration.Length = sizeof(psi->Bssid.Configuration); + psi->Bssid.Configuration.BeaconPeriod = bss->ni_cie.ie_beaconInt; // Units are Kmicroseconds (1024 us) + psi->Bssid.Configuration.ATIMWindow = 0; + psi->Bssid.Configuration.DSConfig = bss->ni_cie.ie_chan * 1000; + psi->Bssid.InfrastructureMode = ((bss->ni_cie.ie_capInfo & 0x03) == 0x01 ) ? Ndis802_11Infrastructure : Ndis802_11IBSS; + + RateSize = 0; + pie = bss->ni_cie.ie_rates; + if (pie) { + RateSize = (pie[1] < NDIS_802_11_LENGTH_RATES_EX) ? pie[1] : NDIS_802_11_LENGTH_RATES_EX; + memcpy(psi->Bssid.SupportedRates, &pie[2], RateSize); + } + pie = bss->ni_cie.ie_xrates; + if (pie && RateSize < NDIS_802_11_LENGTH_RATES_EX) { + memcpy(psi->Bssid.SupportedRates + RateSize, &pie[2], + (pie[1] < (NDIS_802_11_LENGTH_RATES_EX - RateSize)) ? pie[1] : (NDIS_802_11_LENGTH_RATES_EX - RateSize)); + } + + // Copy the fixed IEs + psi->Bssid.IELength = sizeof(NDIS_802_11_FIXED_IEs); + + pFixed = (NDIS_802_11_FIXED_IEs *)psi->Bssid.IEs; + memcpy(pFixed->Timestamp, bss->ni_cie.ie_tstamp, sizeof(pFixed->Timestamp)); + pFixed->BeaconInterval = bss->ni_cie.ie_beaconInt; + pFixed->Capabilities = bss->ni_cie.ie_capInfo; + + // Copy selected variable IEs + + pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pFixed + sizeof(NDIS_802_11_FIXED_IEs)); + +#ifdef SUPPORT_WPA2 + // Copy the WPAv2 IE + if (bss->ni_cie.ie_rsn) { + pie = bss->ni_cie.ie_rsn; + psi->Bssid.IELength += pie[1] + 2; + memcpy(pVar, pie, pie[1] + 2); + pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pVar + pie[1] + 2); + } +#endif + // Copy the WPAv1 IE + if (bss->ni_cie.ie_wpa) { + pie = bss->ni_cie.ie_wpa; + psi->Bssid.IELength += pie[1] + 2; + memcpy(pVar, pie, pie[1] + 2); + pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pVar + pie[1] + 2); + } + + // Advance buffer pointer + psi = (PNDIS_802_11_BSSID_SCAN_INFO)((BYTE*)psi + bsssize + FIELD_OFFSET(NDIS_802_11_BSSID_SCAN_INFO, Bssid)); + } + } + + IEEE80211_NODE_UNLOCK(nt); + +// wmi_free_allnodes(wmip); + +// RETAILMSG(1, (L"AR6K: scan indication: %u bss\n", numbss)); + + ar6000_scan_indication (wmip->wmi_devt, pAr6kScanIndEvent, size); + + A_FREE(pAr6kScanIndEvent); +} +#endif +A_UINT8 +ar6000_get_upper_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, + A_UINT32 size) +{ + A_UINT32 index; + A_UINT8 threshold = (A_UINT8)sq_thresh->upper_threshold[size - 1]; + + /* The list is already in sorted order. Get the next lower value */ + for (index = 0; index < size; index ++) { + if (rssi < sq_thresh->upper_threshold[index]) { + threshold = (A_UINT8)sq_thresh->upper_threshold[index]; + break; + } + } + + return threshold; +} + +A_UINT8 +ar6000_get_lower_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, + A_UINT32 size) +{ + A_UINT32 index; + A_UINT8 threshold = (A_UINT8)sq_thresh->lower_threshold[size - 1]; + + /* The list is already in sorted order. Get the next lower value */ + for (index = 0; index < size; index ++) { + if (rssi > sq_thresh->lower_threshold[index]) { + threshold = (A_UINT8)sq_thresh->lower_threshold[index]; + break; + } + } + + return threshold; +} +static A_STATUS +wmi_send_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd) +{ + void *osbuf; + A_INT8 size; + WMI_RSSI_THRESHOLD_PARAMS_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_RSSI_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, rssiCmd, sizeof(WMI_RSSI_THRESHOLD_PARAMS_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_RSSI_THRESHOLD_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} +static A_STATUS +wmi_send_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd) +{ + void *osbuf; + A_INT8 size; + WMI_SNR_THRESHOLD_PARAMS_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + cmd = (WMI_SNR_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, snrCmd, sizeof(WMI_SNR_THRESHOLD_PARAMS_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SNR_THRESHOLD_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_target_event_report_cmd(struct wmi_t *wmip, WMI_SET_TARGET_EVENT_REPORT_CMD* cmd) +{ + void *osbuf; + WMI_SET_TARGET_EVENT_REPORT_CMD* alloc_cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + alloc_cmd = (WMI_SET_TARGET_EVENT_REPORT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(alloc_cmd, sizeof(*cmd)); + A_MEMCPY(alloc_cmd, cmd, sizeof(*cmd)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_TARGET_EVENT_REPORT_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4) +{ + void *osbuf; + WMI_SET_MCAST_FILTER_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->multicast_mac[0] = 0x01; + cmd->multicast_mac[1] = 0x00; + cmd->multicast_mac[2] = 0x5e; + cmd->multicast_mac[3] = dot2&0x7F; + cmd->multicast_mac[4] = dot3; + cmd->multicast_mac[5] = dot4; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_MCAST_FILTER_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_del_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4) +{ + void *osbuf; + WMI_SET_MCAST_FILTER_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->multicast_mac[0] = 0x01; + cmd->multicast_mac[1] = 0x00; + cmd->multicast_mac[2] = 0x5e; + cmd->multicast_mac[3] = dot2&0x7F; + cmd->multicast_mac[4] = dot3; + cmd->multicast_mac[5] = dot4; + + return (wmi_cmd_send(wmip, osbuf, WMI_DEL_MCAST_FILTER_CMDID, + NO_SYNC_WMIFLAG)); +} + +bss_t *wmi_rm_current_bss (struct wmi_t *wmip, A_UINT8 *id) +{ + wmi_get_current_bssid (wmip, id); + return wlan_node_remove (&wmip->wmi_scan_table, id); +} + +A_STATUS wmi_add_current_bss (struct wmi_t *wmip, A_UINT8 *id, bss_t *bss) +{ + wlan_setup_node (&wmip->wmi_scan_table, bss, id); + return A_OK; +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k/AR6002_regdump.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/AR6002_regdump.h --- linux-2.6.26/drivers/net/wireless/ath6k/AR6002_regdump.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/AR6002_regdump.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,59 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2006 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __AR6002_REGDUMP_H__ +#define __AR6002_REGDUMP_H__ + +#if !defined(__ASSEMBLER__) +/* + * XTensa CPU state + * This must match the state saved by the target exception handler. + */ +struct XTensa_exception_frame_s { + A_UINT32 xt_pc; + A_UINT32 xt_ps; + A_UINT32 xt_sar; + A_UINT32 xt_vpri; + A_UINT32 xt_a2; + A_UINT32 xt_a3; + A_UINT32 xt_a4; + A_UINT32 xt_a5; + A_UINT32 xt_exccause; + A_UINT32 xt_lcount; + A_UINT32 xt_lbeg; + A_UINT32 xt_lend; + + /* Extra info to simplify post-mortem stack walkback */ +#define AR6002_REGDUMP_FRAMES 5 + struct { + A_UINT32 a0; /* pc */ + A_UINT32 a1; /* sp */ + A_UINT32 a2; + A_UINT32 a3; + } wb[AR6002_REGDUMP_FRAMES]; +}; +typedef struct XTensa_exception_frame_s CPU_exception_frame_t; +#define RD_SIZE sizeof(CPU_exception_frame_t) + +#endif +#endif /* __AR6002_REGDUMP_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/AR6K_version.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/AR6K_version.h --- linux-2.6.26/drivers/net/wireless/ath6k/AR6K_version.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/AR6K_version.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#define __VER_MAJOR_ 2 +#define __VER_MINOR_ 2 +#define __VER_PATCH_ 0 + + +/* The makear6ksdk script (used for release builds) modifies the following line. */ +#define __BUILD_NUMBER_ 78 + + +/* Format of the version number. */ +#define VER_MAJOR_BIT_OFFSET 28 +#define VER_MINOR_BIT_OFFSET 24 +#define VER_PATCH_BIT_OFFSET 16 +#define VER_BUILD_NUM_BIT_OFFSET 0 + + +/* + * The version has the following format: + * Bits 28-31: Major version + * Bits 24-27: Minor version + * Bits 16-23: Patch version + * Bits 0-15: Build number (automatically generated during build process ) + * E.g. Build 1.1.3.7 would be represented as 0x11030007. + * + * DO NOT split the following macro into multiple lines as this may confuse the build scripts. + */ +#define AR6K_SW_VERSION ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) ) + + diff -urN linux-2.6.26/drivers/net/wireless/ath6k/AR6K_version.h.NEW linux-2.6.26-lab126/drivers/net/wireless/ath6k/AR6K_version.h.NEW --- linux-2.6.26/drivers/net/wireless/ath6k/AR6K_version.h.NEW 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/AR6K_version.h.NEW 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,38 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// $ATH_LICENSE_HOSTSDK0_C$ +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#define __VER_MAJOR_ 2 +#define __VER_MINOR_ 2 +#define __VER_PATCH_ 0 + + +/* The makear6ksdk script (used for release builds) modifies the following line. */ +#define __BUILD_NUMBER_ 78 + + +/* Format of the version number. */ +#define VER_MAJOR_BIT_OFFSET 28 +#define VER_MINOR_BIT_OFFSET 24 +#define VER_PATCH_BIT_OFFSET 16 +#define VER_BUILD_NUM_BIT_OFFSET 0 + + +/* + * The version has the following format: + * Bits 28-31: Major version + * Bits 24-27: Minor version + * Bits 16-23: Patch version + * Bits 0-15: Build number (automatically generated during build process ) + * E.g. Build 1.1.3.7 would be represented as 0x11030007. + * + * DO NOT split the following macro into multiple lines as this may confuse the build scripts. + */ +#define AR6K_SW_VERSION ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) ) + + diff -urN linux-2.6.26/drivers/net/wireless/ath6k/Kconfig linux-2.6.26-lab126/drivers/net/wireless/ath6k/Kconfig --- linux-2.6.26/drivers/net/wireless/ath6k/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/Kconfig 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,14 @@ +# +# Atheros WiFi driver +# +config ATHEROS_AR6000 + tristate "Atheros AR6000 driver" + #depends on INPUT + help + Say Y here if you have an Atheros WiFi chip in your system + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called ar6000. + diff -urN linux-2.6.26/drivers/net/wireless/ath6k/Makefile linux-2.6.26-lab126/drivers/net/wireless/ath6k/Makefile --- linux-2.6.26/drivers/net/wireless/ath6k/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/Makefile 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,20 @@ +# +# Atheros WiFi driver +# + +EXTRA_CFLAGS += -DSEND_EVENT_TO_APP -DHTC_RAW_INTERFACE -DAR6000REV2 + +obj-$(CONFIG_ATHEROS_AR6000) += ar6000.o + +ar6000-objs := hif.o ar6k.o ar6k_events.o htc_send.o htc_recv.o \ + htc_services.o htc.o bmi.o ar6000_drv.o ar6000_raw_if.o \ + netbuf.o wireless_ext.o ioctl.o engine.o common_drv.o \ + credit_dist.o wmi.o wlan_node.o wlan_recv_beacon.o \ + wlan_utils.o + +ATH_BUILD_TYPE := NATIVEMMC +ATH_BUS_TYPE := SDIO +ATH_BUS_SUBTYPE := linux_sdio +ATH_OS_SUB_TYPE := linux_2_6 +export ATH_BUS_SUBTYPE + diff -urN linux-2.6.26/drivers/net/wireless/ath6k/README.txt linux-2.6.26-lab126/drivers/net/wireless/ath6k/README.txt --- linux-2.6.26/drivers/net/wireless/ath6k/README.txt 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/README.txt 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,3 @@ +This directory holds Mercury header files. Put something like the line below +into your Perforce client specification. + //depot/chips/mercury/2.0/dv/fpga/10312007/reg_headers/... //YourClientName/YourDirectory/include/AR6002/hw.2/... diff -urN linux-2.6.26/drivers/net/wireless/ath6k/a_config.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/a_config.h --- linux-2.6.26/drivers/net/wireless/ath6k/a_config.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/a_config.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,45 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains software configuration options that enables +// specific software "features" +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_CONFIG_H_ +#define _A_CONFIG_H_ + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/config_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/config_wince.h" +#endif + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "config_linux.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/config_rexos.h" +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k/a_debug.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/a_debug.h --- linux-2.6.26/drivers/net/wireless/ath6k/a_debug.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/a_debug.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,59 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_DEBUG_H_ +#define _A_DEBUG_H_ + +#include "a_types.h" +#include "a_osapi.h" + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/debug_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/debug_wince.h" +#endif + +#ifndef UNDER_CE +#define DBG_INFO 0x00000001 +#define DBG_ERROR 0x00000002 +#define DBG_WARNING 0x00000004 +#define DBG_SDIO 0x00000008 +#define DBG_HIF 0x00000010 +#define DBG_HTC 0x00000020 +#define DBG_WMI 0x00000040 +#define DBG_WMI2 0x00000080 +#define DBG_DRIVER 0x00000100 + +#define DBG_DEFAULTS (DBG_ERROR|DBG_WARNING) +#endif + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "debug_linux.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/debug_rexos.h" +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k/a_drv.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/a_drv.h --- linux-2.6.26/drivers/net/wireless/ath6k/a_drv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/a_drv.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,46 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions of the basic atheros data types. +// It is used to map the data types in atheros files to a platform specific +// type. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_DRV_H_ +#define _A_DRV_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "athdrv_linux.h" +#endif + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/athdrv_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/athdrv_wince.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/athdrv_rexos.h" +#endif + +#endif /* _ADRV_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/a_drv_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/a_drv_api.h --- linux-2.6.26/drivers/net/wireless/ath6k/a_drv_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/a_drv_api.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,207 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_DRV_API_H_ +#define _A_DRV_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************/ +/****************************************************************************/ +/** **/ +/** WMI related hooks **/ +/** **/ +/****************************************************************************/ +/****************************************************************************/ + +#include "ar6000_api.h" + +#define A_WMI_CHANNELLIST_RX(devt, numChan, chanList) \ + ar6000_channelList_rx((devt), (numChan), (chanList)) + +#define A_WMI_SET_NUMDATAENDPTS(devt, num) \ + ar6000_set_numdataendpts((devt), (num)) + +#define A_WMI_CONTROL_TX(devt, osbuf, streamID) \ + ar6000_control_tx((devt), (osbuf), (streamID)) + +#define A_WMI_TARGETSTATS_EVENT(devt, pStats) \ + ar6000_targetStats_event((devt), (pStats)) + +#define A_WMI_SCANCOMPLETE_EVENT(devt, status) \ + ar6000_scanComplete_event((devt), (status)) + +#ifdef CONFIG_HOST_DSET_SUPPORT + +#define A_WMI_DSET_DATA_REQ(devt, access_cookie, offset, length, targ_buf, targ_reply_fn, targ_reply_arg) \ + ar6000_dset_data_req((devt), (access_cookie), (offset), (length), (targ_buf), (targ_reply_fn), (targ_reply_arg)) + +#define A_WMI_DSET_CLOSE(devt, access_cookie) \ + ar6000_dset_close((devt), (access_cookie)) + +#endif + +#define A_WMI_DSET_OPEN_REQ(devt, id, targ_handle, targ_reply_fn, targ_reply_arg) \ + ar6000_dset_open_req((devt), (id), (targ_handle), (targ_reply_fn), (targ_reply_arg)) + +#define A_WMI_CONNECT_EVENT(devt, channel, bssid, listenInterval, beaconInterval, networkType, beaconIeLen, assocReqLen, assocRespLen, assocInfo) \ + ar6000_connect_event((devt), (channel), (bssid), (listenInterval), (beaconInterval), (networkType), (beaconIeLen), (assocReqLen), (assocRespLen), (assocInfo)) + +#define A_WMI_PSPOLL_EVENT(devt, aid)\ + ar6000_pspoll_event((devt),(aid)) + +#define A_WMI_DTIMEXPIRY_EVENT(devt)\ + ar6000_dtimexpiry_event((devt)) + +#define A_WMI_REGDOMAIN_EVENT(devt, regCode) \ + ar6000_regDomain_event((devt), (regCode)) + +#define A_WMI_NEIGHBORREPORT_EVENT(devt, numAps, info) \ + ar6000_neighborReport_event((devt), (numAps), (info)) + +#define A_WMI_DISCONNECT_EVENT(devt, reason, bssid, assocRespLen, assocInfo, protocolReasonStatus) \ + ar6000_disconnect_event((devt), (reason), (bssid), (assocRespLen), (assocInfo), (protocolReasonStatus)) + +#define A_WMI_TKIP_MICERR_EVENT(devt, keyid, ismcast) \ + ar6000_tkip_micerr_event((devt), (keyid), (ismcast)) + +#define A_WMI_BITRATE_RX(devt, rateKbps) \ + ar6000_bitrate_rx((devt), (rateKbps)) + +#define A_WMI_TXPWR_RX(devt, txPwr) \ + ar6000_txPwr_rx((devt), (txPwr)) + +#define A_WMI_READY_EVENT(devt, datap, phyCap, ver) \ + ar6000_ready_event((devt), (datap), (phyCap), (ver)) + +#define A_WMI_DBGLOG_INIT_DONE(ar) \ + ar6000_dbglog_init_done(ar); + +#define A_WMI_RSSI_THRESHOLD_EVENT(devt, newThreshold, rssi) \ + ar6000_rssiThreshold_event((devt), (newThreshold), (rssi)) + +#define A_WMI_REPORT_ERROR_EVENT(devt, errorVal) \ + ar6000_reportError_event((devt), (errorVal)) + +#define A_WMI_ROAM_TABLE_EVENT(devt, pTbl) \ + ar6000_roam_tbl_event((devt), (pTbl)) + +#define A_WMI_ROAM_DATA_EVENT(devt, p) \ + ar6000_roam_data_event((devt), (p)) + +#define A_WMI_WOW_LIST_EVENT(devt, num_filters, wow_filters) \ + ar6000_wow_list_event((devt), (num_filters), (wow_filters)) + +#define A_WMI_CAC_EVENT(devt, ac, cac_indication, statusCode, tspecSuggestion) \ + ar6000_cac_event((devt), (ac), (cac_indication), (statusCode), (tspecSuggestion)) + +#define A_WMI_CHANNEL_CHANGE_EVENT(devt, oldChannel, newChannel) \ + ar6000_channel_change_event((devt), (oldChannel), (newChannel)) + +#define A_WMI_PMKID_LIST_EVENT(devt, num_pmkid, pmkid_list, bssid_list) \ + ar6000_pmkid_list_event((devt), (num_pmkid), (pmkid_list), (bssid_list)) + +#define A_WMI_PEER_EVENT(devt, eventCode, bssid) \ + ar6000_peer_event ((devt), (eventCode), (bssid)) + +#ifdef CONFIG_HOST_GPIO_SUPPORT + +#define A_WMI_GPIO_INTR_RX(intr_mask, input_values) \ + ar6000_gpio_intr_rx((intr_mask), (input_values)) + +#define A_WMI_GPIO_DATA_RX(reg_id, value) \ + ar6000_gpio_data_rx((reg_id), (value)) + +#define A_WMI_GPIO_ACK_RX() \ + ar6000_gpio_ack_rx() + +#endif + +#ifdef SEND_EVENT_TO_APP + +#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) \ + ar6000_send_event_to_app((ar), (eventId), (datap), (len)) + +#else + +#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) + +#endif + +#ifdef CONFIG_HOST_TCMD_SUPPORT +#define A_WMI_TCMD_RX_REPORT_EVENT(devt, results, len) \ + ar6000_tcmd_rx_report_event((devt), (results), (len)) +#endif + +#define A_WMI_HBCHALLENGERESP_EVENT(devt, cookie, source) \ + ar6000_hbChallengeResp_event((devt), (cookie), (source)) + +#define A_WMI_TX_RETRY_ERR_EVENT(devt) \ + ar6000_tx_retry_err_event((devt)) + +#define A_WMI_SNR_THRESHOLD_EVENT_RX(devt, newThreshold, snr) \ + ar6000_snrThresholdEvent_rx((devt), (newThreshold), (snr)) + +#define A_WMI_LQ_THRESHOLD_EVENT_RX(devt, range, lqVal) \ + ar6000_lqThresholdEvent_rx((devt), (range), (lqVal)) + +#define A_WMI_RATEMASK_RX(devt, ratemask) \ + ar6000_ratemask_rx((devt), (ratemask)) + +#define A_WMI_KEEPALIVE_RX(devt, configured) \ + ar6000_keepalive_rx((devt), (configured)) + +#define A_WMI_BSSINFO_EVENT_RX(ar, datp, len) \ + ar6000_bssInfo_event_rx((ar), (datap), (len)) + +#define A_WMI_DBGLOG_EVENT(ar, dropped, buffer, length) \ + ar6000_dbglog_event((ar), (dropped), (buffer), (length)); + +#define A_WMI_STREAM_TX_ACTIVE(devt,trafficClass) \ + ar6000_indicate_tx_activity((devt),(trafficClass), TRUE) + +#define A_WMI_STREAM_TX_INACTIVE(devt,trafficClass) \ + ar6000_indicate_tx_activity((devt),(trafficClass), FALSE) +#define A_WMI_Ac2EndpointID(devht, ac)\ + ar6000_ac2_endpoint_id((devht), (ac)) + +#define A_WMI_Endpoint2Ac(devt, ep) \ + ar6000_endpoint_id2_ac((devt), (ep)) +/****************************************************************************/ +/****************************************************************************/ +/** **/ +/** HTC related hooks **/ +/** **/ +/****************************************************************************/ +/****************************************************************************/ + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +#define A_WMI_PROF_COUNT_RX(addr, count) prof_count_rx((addr), (count)) +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + +#ifdef __cplusplus +} +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k/a_osapi.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/a_osapi.h --- linux-2.6.26/drivers/net/wireless/ath6k/a_osapi.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/a_osapi.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,56 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions of the basic atheros data types. +// It is used to map the data types in atheros files to a platform specific +// type. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_OSAPI_H_ +#define _A_OSAPI_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "osapi_linux.h" +#endif + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/osapi_wince.h" +#include "../os/windows/common/include/netbuf.h" +#if defined __cplusplus || defined __STDC__ +extern "C" +#endif +A_UINT32 a_copy_from_user(void *to, const void *from, A_UINT32 n); +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/osapi_wince.h" +#include "../os/wince/include/netbuf.h" +#if defined __cplusplus || defined __STDC__ +extern "C" +#endif +A_UINT32 a_copy_from_user(void *to, const void *from, A_UINT32 n); +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/osapi_rexos.h" +#endif + +#endif /* _OSAPI_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/a_pyxis.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/a_pyxis.h --- linux-2.6.26/drivers/net/wireless/ath6k/a_pyxis.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/a_pyxis.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,60 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// +//The software source and binaries included in this development package are +//licensed, not sold. You, or your company, received the package under one +//or more license agreements. The rights granted to you are specifically +//listed in these license agreement(s). All other rights remain with Atheros +//Communications, Inc., its subsidiaries, or the respective owner including +//those listed on the included copyright notices.. Distribution of any +//portion of this package must be in strict compliance with the license +//agreement(s) terms. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the Pyxis definitions for host +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_PYXIS_H_ +#define _A_PYXIS_H_ +/* + * Copyright (c) 2004-2005 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +/* + * This file contains software key stream pyxis adhoc mode options that enables + * specific software "features" + */ +#ifdef UNDER_CE +#include "../os/wince/include/ks_custom_ndis.h" +#endif + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#endif + +#ifdef REXOS +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k/a_types.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/a_types.h --- linux-2.6.26/drivers/net/wireless/ath6k/a_types.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/a_types.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,46 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions of the basic atheros data types. +// It is used to map the data types in atheros files to a platform specific +// type. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_TYPES_H_ +#define _A_TYPES_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "athtypes_linux.h" +#endif + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/athtypes_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/athtypes_wince.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/athtypes_rexos.h" +#endif + +#endif /* _ATHTYPES_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/addrs.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/addrs.h --- linux-2.6.26/drivers/net/wireless/ath6k/addrs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/addrs.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,85 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __ADDRS_H__ +#define __ADDRS_H__ + +/* + * Special AR6002 Addresses that may be needed by special + * applications (e.g. ART) on the Host as well as Target. + */ + +#if defined(AR6002_REV2) +#define AR6K_RAM_START 0x00500000 +#define TARG_RAM_OFFSET(vaddr) ((A_UINT32)(vaddr) & 0xfffff) +#define TARG_RAM_SZ (184*1024) +#define TARG_ROM_SZ (80*1024) +#endif +#if defined(AR6002_REV4) || defined(AR6003) +#define AR6K_RAM_START 0x00540000 +#define TARG_RAM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0xfffff) - 0x40000) +#define TARG_RAM_SZ (256*1024) +#define TARG_ROM_SZ (256*1024) +#endif + +#define AR6002_BOARD_DATA_SZ 768 +#define AR6003_BOARD_DATA_SZ 1504 + +#define AR6K_RAM_ADDR(byte_offset) (AR6K_RAM_START+(byte_offset)) +#define TARG_RAM_ADDRS(byte_offset) AR6K_RAM_ADDR(byte_offset) + +#define AR6K_ROM_START 0x004e0000 +#define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset)) +#define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset) + +/* + * At this ROM address is a pointer to the start of the ROM DataSet Index. + * If there are no ROM DataSets, there's a 0 at this address. + */ +#define ROM_DATASET_INDEX_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-8) +#define ROM_MBIST_CKSUM_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-4) + +/* + * The API A_BOARD_DATA_ADDR() is the proper way to get a read pointer to + * board data. + */ + +/* Size of Board Data, in bytes */ +#if defined(AR6002_REV4) || defined(AR6003) +#define BOARD_DATA_SZ AR6003_BOARD_DATA_SZ +#else +#define BOARD_DATA_SZ AR6002_BOARD_DATA_SZ +#endif + + +/* + * Constants used by ASM code to access fields of host_interest_s, + * which is at a fixed location in RAM. + */ +#define HOST_INTEREST_FLASH_IS_PRESENT_ADDR (AR6K_RAM_START + 0x40c) +#define FLASH_IS_PRESENT_TARGADDR HOST_INTEREST_FLASH_IS_PRESENT_ADDR + +/* override REV2 ROM's app start address */ +#define AR6002_REV2_APP_START_OVERRIDE 0x9148f0 + +#endif /* __ADDRS_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/analog_intf_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/analog_intf_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k/analog_intf_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/analog_intf_reg.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,87 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _ANALOG_INTF_REG_REG_H_ +#define _ANALOG_INTF_REG_REG_H_ + +#define SW_OVERRIDE_ADDRESS 0x00000080 +#define SW_OVERRIDE_OFFSET 0x00000080 +#define SW_OVERRIDE_SUPDATE_DELAY_MSB 1 +#define SW_OVERRIDE_SUPDATE_DELAY_LSB 1 +#define SW_OVERRIDE_SUPDATE_DELAY_MASK 0x00000002 +#define SW_OVERRIDE_SUPDATE_DELAY_GET(x) (((x) & SW_OVERRIDE_SUPDATE_DELAY_MASK) >> SW_OVERRIDE_SUPDATE_DELAY_LSB) +#define SW_OVERRIDE_SUPDATE_DELAY_SET(x) (((x) << SW_OVERRIDE_SUPDATE_DELAY_LSB) & SW_OVERRIDE_SUPDATE_DELAY_MASK) +#define SW_OVERRIDE_ENABLE_MSB 0 +#define SW_OVERRIDE_ENABLE_LSB 0 +#define SW_OVERRIDE_ENABLE_MASK 0x00000001 +#define SW_OVERRIDE_ENABLE_GET(x) (((x) & SW_OVERRIDE_ENABLE_MASK) >> SW_OVERRIDE_ENABLE_LSB) +#define SW_OVERRIDE_ENABLE_SET(x) (((x) << SW_OVERRIDE_ENABLE_LSB) & SW_OVERRIDE_ENABLE_MASK) + +#define SIN_VAL_ADDRESS 0x00000084 +#define SIN_VAL_OFFSET 0x00000084 +#define SIN_VAL_SIN_MSB 0 +#define SIN_VAL_SIN_LSB 0 +#define SIN_VAL_SIN_MASK 0x00000001 +#define SIN_VAL_SIN_GET(x) (((x) & SIN_VAL_SIN_MASK) >> SIN_VAL_SIN_LSB) +#define SIN_VAL_SIN_SET(x) (((x) << SIN_VAL_SIN_LSB) & SIN_VAL_SIN_MASK) + +#define SW_SCLK_ADDRESS 0x00000088 +#define SW_SCLK_OFFSET 0x00000088 +#define SW_SCLK_SW_SCLK_MSB 0 +#define SW_SCLK_SW_SCLK_LSB 0 +#define SW_SCLK_SW_SCLK_MASK 0x00000001 +#define SW_SCLK_SW_SCLK_GET(x) (((x) & SW_SCLK_SW_SCLK_MASK) >> SW_SCLK_SW_SCLK_LSB) +#define SW_SCLK_SW_SCLK_SET(x) (((x) << SW_SCLK_SW_SCLK_LSB) & SW_SCLK_SW_SCLK_MASK) + +#define SW_CNTL_ADDRESS 0x0000008c +#define SW_CNTL_OFFSET 0x0000008c +#define SW_CNTL_SW_SCAPTURE_MSB 2 +#define SW_CNTL_SW_SCAPTURE_LSB 2 +#define SW_CNTL_SW_SCAPTURE_MASK 0x00000004 +#define SW_CNTL_SW_SCAPTURE_GET(x) (((x) & SW_CNTL_SW_SCAPTURE_MASK) >> SW_CNTL_SW_SCAPTURE_LSB) +#define SW_CNTL_SW_SCAPTURE_SET(x) (((x) << SW_CNTL_SW_SCAPTURE_LSB) & SW_CNTL_SW_SCAPTURE_MASK) +#define SW_CNTL_SW_SUPDATE_MSB 1 +#define SW_CNTL_SW_SUPDATE_LSB 1 +#define SW_CNTL_SW_SUPDATE_MASK 0x00000002 +#define SW_CNTL_SW_SUPDATE_GET(x) (((x) & SW_CNTL_SW_SUPDATE_MASK) >> SW_CNTL_SW_SUPDATE_LSB) +#define SW_CNTL_SW_SUPDATE_SET(x) (((x) << SW_CNTL_SW_SUPDATE_LSB) & SW_CNTL_SW_SUPDATE_MASK) +#define SW_CNTL_SW_SOUT_MSB 0 +#define SW_CNTL_SW_SOUT_LSB 0 +#define SW_CNTL_SW_SOUT_MASK 0x00000001 +#define SW_CNTL_SW_SOUT_GET(x) (((x) & SW_CNTL_SW_SOUT_MASK) >> SW_CNTL_SW_SOUT_LSB) +#define SW_CNTL_SW_SOUT_SET(x) (((x) << SW_CNTL_SW_SOUT_LSB) & SW_CNTL_SW_SOUT_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct analog_intf_reg_reg_s { + unsigned char pad0[128]; /* pad to 0x80 */ + volatile unsigned int sw_override; + volatile unsigned int sin_val; + volatile unsigned int sw_sclk; + volatile unsigned int sw_cntl; +} analog_intf_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _ANALOG_INTF_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/analog_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/analog_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k/analog_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/analog_reg.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,1955 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _ANALOG_REG_REG_H_ +#define _ANALOG_REG_REG_H_ + +#define SYNTH_SYNTH1_ADDRESS 0x00000000 +#define SYNTH_SYNTH1_OFFSET 0x00000000 +#define SYNTH_SYNTH1_PWD_BIAS_MSB 31 +#define SYNTH_SYNTH1_PWD_BIAS_LSB 31 +#define SYNTH_SYNTH1_PWD_BIAS_MASK 0x80000000 +#define SYNTH_SYNTH1_PWD_BIAS_GET(x) (((x) & SYNTH_SYNTH1_PWD_BIAS_MASK) >> SYNTH_SYNTH1_PWD_BIAS_LSB) +#define SYNTH_SYNTH1_PWD_BIAS_SET(x) (((x) << SYNTH_SYNTH1_PWD_BIAS_LSB) & SYNTH_SYNTH1_PWD_BIAS_MASK) +#define SYNTH_SYNTH1_PWD_CP_MSB 30 +#define SYNTH_SYNTH1_PWD_CP_LSB 30 +#define SYNTH_SYNTH1_PWD_CP_MASK 0x40000000 +#define SYNTH_SYNTH1_PWD_CP_GET(x) (((x) & SYNTH_SYNTH1_PWD_CP_MASK) >> SYNTH_SYNTH1_PWD_CP_LSB) +#define SYNTH_SYNTH1_PWD_CP_SET(x) (((x) << SYNTH_SYNTH1_PWD_CP_LSB) & SYNTH_SYNTH1_PWD_CP_MASK) +#define SYNTH_SYNTH1_PWD_VCMON_MSB 29 +#define SYNTH_SYNTH1_PWD_VCMON_LSB 29 +#define SYNTH_SYNTH1_PWD_VCMON_MASK 0x20000000 +#define SYNTH_SYNTH1_PWD_VCMON_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCMON_MASK) >> SYNTH_SYNTH1_PWD_VCMON_LSB) +#define SYNTH_SYNTH1_PWD_VCMON_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCMON_LSB) & SYNTH_SYNTH1_PWD_VCMON_MASK) +#define SYNTH_SYNTH1_PWD_VCO_MSB 28 +#define SYNTH_SYNTH1_PWD_VCO_LSB 28 +#define SYNTH_SYNTH1_PWD_VCO_MASK 0x10000000 +#define SYNTH_SYNTH1_PWD_VCO_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCO_MASK) >> SYNTH_SYNTH1_PWD_VCO_LSB) +#define SYNTH_SYNTH1_PWD_VCO_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCO_LSB) & SYNTH_SYNTH1_PWD_VCO_MASK) +#define SYNTH_SYNTH1_PWD_PRESC_MSB 27 +#define SYNTH_SYNTH1_PWD_PRESC_LSB 27 +#define SYNTH_SYNTH1_PWD_PRESC_MASK 0x08000000 +#define SYNTH_SYNTH1_PWD_PRESC_GET(x) (((x) & SYNTH_SYNTH1_PWD_PRESC_MASK) >> SYNTH_SYNTH1_PWD_PRESC_LSB) +#define SYNTH_SYNTH1_PWD_PRESC_SET(x) (((x) << SYNTH_SYNTH1_PWD_PRESC_LSB) & SYNTH_SYNTH1_PWD_PRESC_MASK) +#define SYNTH_SYNTH1_PWD_LODIV_MSB 26 +#define SYNTH_SYNTH1_PWD_LODIV_LSB 26 +#define SYNTH_SYNTH1_PWD_LODIV_MASK 0x04000000 +#define SYNTH_SYNTH1_PWD_LODIV_GET(x) (((x) & SYNTH_SYNTH1_PWD_LODIV_MASK) >> SYNTH_SYNTH1_PWD_LODIV_LSB) +#define SYNTH_SYNTH1_PWD_LODIV_SET(x) (((x) << SYNTH_SYNTH1_PWD_LODIV_LSB) & SYNTH_SYNTH1_PWD_LODIV_MASK) +#define SYNTH_SYNTH1_PWD_LOMIX_MSB 25 +#define SYNTH_SYNTH1_PWD_LOMIX_LSB 25 +#define SYNTH_SYNTH1_PWD_LOMIX_MASK 0x02000000 +#define SYNTH_SYNTH1_PWD_LOMIX_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOMIX_MASK) >> SYNTH_SYNTH1_PWD_LOMIX_LSB) +#define SYNTH_SYNTH1_PWD_LOMIX_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOMIX_LSB) & SYNTH_SYNTH1_PWD_LOMIX_MASK) +#define SYNTH_SYNTH1_FORCE_LO_ON_MSB 24 +#define SYNTH_SYNTH1_FORCE_LO_ON_LSB 24 +#define SYNTH_SYNTH1_FORCE_LO_ON_MASK 0x01000000 +#define SYNTH_SYNTH1_FORCE_LO_ON_GET(x) (((x) & SYNTH_SYNTH1_FORCE_LO_ON_MASK) >> SYNTH_SYNTH1_FORCE_LO_ON_LSB) +#define SYNTH_SYNTH1_FORCE_LO_ON_SET(x) (((x) << SYNTH_SYNTH1_FORCE_LO_ON_LSB) & SYNTH_SYNTH1_FORCE_LO_ON_MASK) +#define SYNTH_SYNTH1_PWD_LOBUF5G_MSB 23 +#define SYNTH_SYNTH1_PWD_LOBUF5G_LSB 23 +#define SYNTH_SYNTH1_PWD_LOBUF5G_MASK 0x00800000 +#define SYNTH_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK) >> SYNTH_SYNTH1_PWD_LOBUF5G_LSB) +#define SYNTH_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOBUF5G_LSB) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK) +#define SYNTH_SYNTH1_VCOREGBYPASS_MSB 22 +#define SYNTH_SYNTH1_VCOREGBYPASS_LSB 22 +#define SYNTH_SYNTH1_VCOREGBYPASS_MASK 0x00400000 +#define SYNTH_SYNTH1_VCOREGBYPASS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBYPASS_MASK) >> SYNTH_SYNTH1_VCOREGBYPASS_LSB) +#define SYNTH_SYNTH1_VCOREGBYPASS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBYPASS_LSB) & SYNTH_SYNTH1_VCOREGBYPASS_MASK) +#define SYNTH_SYNTH1_VCOREGLEVEL_MSB 21 +#define SYNTH_SYNTH1_VCOREGLEVEL_LSB 20 +#define SYNTH_SYNTH1_VCOREGLEVEL_MASK 0x00300000 +#define SYNTH_SYNTH1_VCOREGLEVEL_GET(x) (((x) & SYNTH_SYNTH1_VCOREGLEVEL_MASK) >> SYNTH_SYNTH1_VCOREGLEVEL_LSB) +#define SYNTH_SYNTH1_VCOREGLEVEL_SET(x) (((x) << SYNTH_SYNTH1_VCOREGLEVEL_LSB) & SYNTH_SYNTH1_VCOREGLEVEL_MASK) +#define SYNTH_SYNTH1_VCOREGBIAS_MSB 19 +#define SYNTH_SYNTH1_VCOREGBIAS_LSB 18 +#define SYNTH_SYNTH1_VCOREGBIAS_MASK 0x000c0000 +#define SYNTH_SYNTH1_VCOREGBIAS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBIAS_MASK) >> SYNTH_SYNTH1_VCOREGBIAS_LSB) +#define SYNTH_SYNTH1_VCOREGBIAS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBIAS_LSB) & SYNTH_SYNTH1_VCOREGBIAS_MASK) +#define SYNTH_SYNTH1_SLIDINGIF_MSB 17 +#define SYNTH_SYNTH1_SLIDINGIF_LSB 17 +#define SYNTH_SYNTH1_SLIDINGIF_MASK 0x00020000 +#define SYNTH_SYNTH1_SLIDINGIF_GET(x) (((x) & SYNTH_SYNTH1_SLIDINGIF_MASK) >> SYNTH_SYNTH1_SLIDINGIF_LSB) +#define SYNTH_SYNTH1_SLIDINGIF_SET(x) (((x) << SYNTH_SYNTH1_SLIDINGIF_LSB) & SYNTH_SYNTH1_SLIDINGIF_MASK) +#define SYNTH_SYNTH1_SPARE_PWD_MSB 16 +#define SYNTH_SYNTH1_SPARE_PWD_LSB 16 +#define SYNTH_SYNTH1_SPARE_PWD_MASK 0x00010000 +#define SYNTH_SYNTH1_SPARE_PWD_GET(x) (((x) & SYNTH_SYNTH1_SPARE_PWD_MASK) >> SYNTH_SYNTH1_SPARE_PWD_LSB) +#define SYNTH_SYNTH1_SPARE_PWD_SET(x) (((x) << SYNTH_SYNTH1_SPARE_PWD_LSB) & SYNTH_SYNTH1_SPARE_PWD_MASK) +#define SYNTH_SYNTH1_CON_VDDVCOREG_MSB 15 +#define SYNTH_SYNTH1_CON_VDDVCOREG_LSB 15 +#define SYNTH_SYNTH1_CON_VDDVCOREG_MASK 0x00008000 +#define SYNTH_SYNTH1_CON_VDDVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK) >> SYNTH_SYNTH1_CON_VDDVCOREG_LSB) +#define SYNTH_SYNTH1_CON_VDDVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_VDDVCOREG_LSB) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK) +#define SYNTH_SYNTH1_CON_IVCOREG_MSB 14 +#define SYNTH_SYNTH1_CON_IVCOREG_LSB 14 +#define SYNTH_SYNTH1_CON_IVCOREG_MASK 0x00004000 +#define SYNTH_SYNTH1_CON_IVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCOREG_MASK) >> SYNTH_SYNTH1_CON_IVCOREG_LSB) +#define SYNTH_SYNTH1_CON_IVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOREG_LSB) & SYNTH_SYNTH1_CON_IVCOREG_MASK) +#define SYNTH_SYNTH1_CON_IVCOBUF_MSB 13 +#define SYNTH_SYNTH1_CON_IVCOBUF_LSB 13 +#define SYNTH_SYNTH1_CON_IVCOBUF_MASK 0x00002000 +#define SYNTH_SYNTH1_CON_IVCOBUF_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCOBUF_MASK) >> SYNTH_SYNTH1_CON_IVCOBUF_LSB) +#define SYNTH_SYNTH1_CON_IVCOBUF_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOBUF_LSB) & SYNTH_SYNTH1_CON_IVCOBUF_MASK) +#define SYNTH_SYNTH1_SEL_VCMONABUS_MSB 12 +#define SYNTH_SYNTH1_SEL_VCMONABUS_LSB 10 +#define SYNTH_SYNTH1_SEL_VCMONABUS_MASK 0x00001c00 +#define SYNTH_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK) >> SYNTH_SYNTH1_SEL_VCMONABUS_LSB) +#define SYNTH_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << SYNTH_SYNTH1_SEL_VCMONABUS_LSB) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK) +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MSB 9 +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB 9 +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK 0x00000200 +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK) >> SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB) +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK) +#define SYNTH_SYNTH1_PWUP_LODIV_PD_MSB 8 +#define SYNTH_SYNTH1_PWUP_LODIV_PD_LSB 8 +#define SYNTH_SYNTH1_PWUP_LODIV_PD_MASK 0x00000100 +#define SYNTH_SYNTH1_PWUP_LODIV_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK) >> SYNTH_SYNTH1_PWUP_LODIV_PD_LSB) +#define SYNTH_SYNTH1_PWUP_LODIV_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LODIV_PD_LSB) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK) +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MSB 7 +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB 7 +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK 0x00000080 +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB) +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK) +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MSB 6 +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB 6 +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK 0x00000040 +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB) +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK) +#define SYNTH_SYNTH1_MONITOR_FB_MSB 5 +#define SYNTH_SYNTH1_MONITOR_FB_LSB 5 +#define SYNTH_SYNTH1_MONITOR_FB_MASK 0x00000020 +#define SYNTH_SYNTH1_MONITOR_FB_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB_MASK) >> SYNTH_SYNTH1_MONITOR_FB_LSB) +#define SYNTH_SYNTH1_MONITOR_FB_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_FB_LSB) & SYNTH_SYNTH1_MONITOR_FB_MASK) +#define SYNTH_SYNTH1_MONITOR_REF_MSB 4 +#define SYNTH_SYNTH1_MONITOR_REF_LSB 4 +#define SYNTH_SYNTH1_MONITOR_REF_MASK 0x00000010 +#define SYNTH_SYNTH1_MONITOR_REF_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_REF_MASK) >> SYNTH_SYNTH1_MONITOR_REF_LSB) +#define SYNTH_SYNTH1_MONITOR_REF_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_REF_LSB) & SYNTH_SYNTH1_MONITOR_REF_MASK) +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MSB 3 +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB 3 +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000008 +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK) >> SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB) +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK) +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MSB 2 +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB 2 +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000004 +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK) >> SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB) +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK) +#define SYNTH_SYNTH1_MONITOR_VC2LOW_MSB 1 +#define SYNTH_SYNTH1_MONITOR_VC2LOW_LSB 1 +#define SYNTH_SYNTH1_MONITOR_VC2LOW_MASK 0x00000002 +#define SYNTH_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK) >> SYNTH_SYNTH1_MONITOR_VC2LOW_LSB) +#define SYNTH_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_VC2LOW_LSB) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK) +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 0 +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 0 +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000001 +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK) >> SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB) +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK) + +#define SYNTH_SYNTH2_ADDRESS 0x00000004 +#define SYNTH_SYNTH2_OFFSET 0x00000004 +#define SYNTH_SYNTH2_VC_CAL_REF_MSB 31 +#define SYNTH_SYNTH2_VC_CAL_REF_LSB 29 +#define SYNTH_SYNTH2_VC_CAL_REF_MASK 0xe0000000 +#define SYNTH_SYNTH2_VC_CAL_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_CAL_REF_MASK) >> SYNTH_SYNTH2_VC_CAL_REF_LSB) +#define SYNTH_SYNTH2_VC_CAL_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_CAL_REF_LSB) & SYNTH_SYNTH2_VC_CAL_REF_MASK) +#define SYNTH_SYNTH2_VC_HI_REF_MSB 28 +#define SYNTH_SYNTH2_VC_HI_REF_LSB 26 +#define SYNTH_SYNTH2_VC_HI_REF_MASK 0x1c000000 +#define SYNTH_SYNTH2_VC_HI_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_HI_REF_MASK) >> SYNTH_SYNTH2_VC_HI_REF_LSB) +#define SYNTH_SYNTH2_VC_HI_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_HI_REF_LSB) & SYNTH_SYNTH2_VC_HI_REF_MASK) +#define SYNTH_SYNTH2_VC_MID_REF_MSB 25 +#define SYNTH_SYNTH2_VC_MID_REF_LSB 23 +#define SYNTH_SYNTH2_VC_MID_REF_MASK 0x03800000 +#define SYNTH_SYNTH2_VC_MID_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_MID_REF_MASK) >> SYNTH_SYNTH2_VC_MID_REF_LSB) +#define SYNTH_SYNTH2_VC_MID_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_MID_REF_LSB) & SYNTH_SYNTH2_VC_MID_REF_MASK) +#define SYNTH_SYNTH2_VC_LOW_REF_MSB 22 +#define SYNTH_SYNTH2_VC_LOW_REF_LSB 20 +#define SYNTH_SYNTH2_VC_LOW_REF_MASK 0x00700000 +#define SYNTH_SYNTH2_VC_LOW_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_LOW_REF_MASK) >> SYNTH_SYNTH2_VC_LOW_REF_LSB) +#define SYNTH_SYNTH2_VC_LOW_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_LOW_REF_LSB) & SYNTH_SYNTH2_VC_LOW_REF_MASK) +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MSB 19 +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB 15 +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK 0x000f8000 +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_GET(x) (((x) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK) >> SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB) +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_SET(x) (((x) << SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK) +#define SYNTH_SYNTH2_LOOP_CP_MSB 14 +#define SYNTH_SYNTH2_LOOP_CP_LSB 10 +#define SYNTH_SYNTH2_LOOP_CP_MASK 0x00007c00 +#define SYNTH_SYNTH2_LOOP_CP_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CP_MASK) >> SYNTH_SYNTH2_LOOP_CP_LSB) +#define SYNTH_SYNTH2_LOOP_CP_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CP_LSB) & SYNTH_SYNTH2_LOOP_CP_MASK) +#define SYNTH_SYNTH2_LOOP_RS_MSB 9 +#define SYNTH_SYNTH2_LOOP_RS_LSB 5 +#define SYNTH_SYNTH2_LOOP_RS_MASK 0x000003e0 +#define SYNTH_SYNTH2_LOOP_RS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_RS_MASK) >> SYNTH_SYNTH2_LOOP_RS_LSB) +#define SYNTH_SYNTH2_LOOP_RS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_RS_LSB) & SYNTH_SYNTH2_LOOP_RS_MASK) +#define SYNTH_SYNTH2_LOOP_CS_MSB 4 +#define SYNTH_SYNTH2_LOOP_CS_LSB 3 +#define SYNTH_SYNTH2_LOOP_CS_MASK 0x00000018 +#define SYNTH_SYNTH2_LOOP_CS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CS_MASK) >> SYNTH_SYNTH2_LOOP_CS_LSB) +#define SYNTH_SYNTH2_LOOP_CS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CS_LSB) & SYNTH_SYNTH2_LOOP_CS_MASK) +#define SYNTH_SYNTH2_SPARE_BITS_MSB 2 +#define SYNTH_SYNTH2_SPARE_BITS_LSB 0 +#define SYNTH_SYNTH2_SPARE_BITS_MASK 0x00000007 +#define SYNTH_SYNTH2_SPARE_BITS_GET(x) (((x) & SYNTH_SYNTH2_SPARE_BITS_MASK) >> SYNTH_SYNTH2_SPARE_BITS_LSB) +#define SYNTH_SYNTH2_SPARE_BITS_SET(x) (((x) << SYNTH_SYNTH2_SPARE_BITS_LSB) & SYNTH_SYNTH2_SPARE_BITS_MASK) + +#define SYNTH_SYNTH3_ADDRESS 0x00000008 +#define SYNTH_SYNTH3_OFFSET 0x00000008 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_MSB 31 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_LSB 31 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK) >> SYNTH_SYNTH3_DIS_CLK_XTAL_LSB) +#define SYNTH_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << SYNTH_SYNTH3_DIS_CLK_XTAL_LSB) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK) +#define SYNTH_SYNTH3_SEL_CLK_DIV2_MSB 30 +#define SYNTH_SYNTH3_SEL_CLK_DIV2_LSB 30 +#define SYNTH_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000 +#define SYNTH_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK) >> SYNTH_SYNTH3_SEL_CLK_DIV2_LSB) +#define SYNTH_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << SYNTH_SYNTH3_SEL_CLK_DIV2_LSB) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK) +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29 +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24 +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000 +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB) +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK) +#define SYNTH_SYNTH3_WAIT_PWRUP_MSB 23 +#define SYNTH_SYNTH3_WAIT_PWRUP_LSB 18 +#define SYNTH_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000 +#define SYNTH_SYNTH3_WAIT_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_PWRUP_LSB) +#define SYNTH_SYNTH3_WAIT_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_PWRUP_MASK) +#define SYNTH_SYNTH3_WAIT_CAL_BIN_MSB 17 +#define SYNTH_SYNTH3_WAIT_CAL_BIN_LSB 12 +#define SYNTH_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000 +#define SYNTH_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_BIN_LSB) +#define SYNTH_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_BIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK) +#define SYNTH_SYNTH3_WAIT_CAL_LIN_MSB 11 +#define SYNTH_SYNTH3_WAIT_CAL_LIN_LSB 6 +#define SYNTH_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0 +#define SYNTH_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_LIN_LSB) +#define SYNTH_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_LIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK) +#define SYNTH_SYNTH3_WAIT_VC_CHECK_MSB 5 +#define SYNTH_SYNTH3_WAIT_VC_CHECK_LSB 0 +#define SYNTH_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f +#define SYNTH_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK) >> SYNTH_SYNTH3_WAIT_VC_CHECK_LSB) +#define SYNTH_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << SYNTH_SYNTH3_WAIT_VC_CHECK_LSB) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK) + +#define SYNTH_SYNTH4_ADDRESS 0x0000000c +#define SYNTH_SYNTH4_OFFSET 0x0000000c +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31 +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31 +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000 +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK) >> SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB) +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK) +#define SYNTH_SYNTH4_DIS_LOSTVC_MSB 30 +#define SYNTH_SYNTH4_DIS_LOSTVC_LSB 30 +#define SYNTH_SYNTH4_DIS_LOSTVC_MASK 0x40000000 +#define SYNTH_SYNTH4_DIS_LOSTVC_GET(x) (((x) & SYNTH_SYNTH4_DIS_LOSTVC_MASK) >> SYNTH_SYNTH4_DIS_LOSTVC_LSB) +#define SYNTH_SYNTH4_DIS_LOSTVC_SET(x) (((x) << SYNTH_SYNTH4_DIS_LOSTVC_LSB) & SYNTH_SYNTH4_DIS_LOSTVC_MASK) +#define SYNTH_SYNTH4_ALWAYS_SHORTR_MSB 29 +#define SYNTH_SYNTH4_ALWAYS_SHORTR_LSB 29 +#define SYNTH_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000 +#define SYNTH_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK) >> SYNTH_SYNTH4_ALWAYS_SHORTR_LSB) +#define SYNTH_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << SYNTH_SYNTH4_ALWAYS_SHORTR_LSB) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK) +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28 +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28 +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000 +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK) >> SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB) +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK) +#define SYNTH_SYNTH4_FORCE_PINVC_MSB 27 +#define SYNTH_SYNTH4_FORCE_PINVC_LSB 27 +#define SYNTH_SYNTH4_FORCE_PINVC_MASK 0x08000000 +#define SYNTH_SYNTH4_FORCE_PINVC_GET(x) (((x) & SYNTH_SYNTH4_FORCE_PINVC_MASK) >> SYNTH_SYNTH4_FORCE_PINVC_LSB) +#define SYNTH_SYNTH4_FORCE_PINVC_SET(x) (((x) << SYNTH_SYNTH4_FORCE_PINVC_LSB) & SYNTH_SYNTH4_FORCE_PINVC_MASK) +#define SYNTH_SYNTH4_FORCE_VCOCAP_MSB 26 +#define SYNTH_SYNTH4_FORCE_VCOCAP_LSB 26 +#define SYNTH_SYNTH4_FORCE_VCOCAP_MASK 0x04000000 +#define SYNTH_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK) >> SYNTH_SYNTH4_FORCE_VCOCAP_LSB) +#define SYNTH_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << SYNTH_SYNTH4_FORCE_VCOCAP_LSB) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK) +#define SYNTH_SYNTH4_VCOCAP_OVR_MSB 25 +#define SYNTH_SYNTH4_VCOCAP_OVR_LSB 18 +#define SYNTH_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000 +#define SYNTH_SYNTH4_VCOCAP_OVR_GET(x) (((x) & SYNTH_SYNTH4_VCOCAP_OVR_MASK) >> SYNTH_SYNTH4_VCOCAP_OVR_LSB) +#define SYNTH_SYNTH4_VCOCAP_OVR_SET(x) (((x) << SYNTH_SYNTH4_VCOCAP_OVR_LSB) & SYNTH_SYNTH4_VCOCAP_OVR_MASK) +#define SYNTH_SYNTH4_VCOCAPPULLUP_MSB 17 +#define SYNTH_SYNTH4_VCOCAPPULLUP_LSB 17 +#define SYNTH_SYNTH4_VCOCAPPULLUP_MASK 0x00020000 +#define SYNTH_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK) >> SYNTH_SYNTH4_VCOCAPPULLUP_LSB) +#define SYNTH_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << SYNTH_SYNTH4_VCOCAPPULLUP_LSB) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK) +#define SYNTH_SYNTH4_REFDIVSEL_MSB 16 +#define SYNTH_SYNTH4_REFDIVSEL_LSB 15 +#define SYNTH_SYNTH4_REFDIVSEL_MASK 0x00018000 +#define SYNTH_SYNTH4_REFDIVSEL_GET(x) (((x) & SYNTH_SYNTH4_REFDIVSEL_MASK) >> SYNTH_SYNTH4_REFDIVSEL_LSB) +#define SYNTH_SYNTH4_REFDIVSEL_SET(x) (((x) << SYNTH_SYNTH4_REFDIVSEL_LSB) & SYNTH_SYNTH4_REFDIVSEL_MASK) +#define SYNTH_SYNTH4_PFDDELAY_MSB 14 +#define SYNTH_SYNTH4_PFDDELAY_LSB 14 +#define SYNTH_SYNTH4_PFDDELAY_MASK 0x00004000 +#define SYNTH_SYNTH4_PFDDELAY_GET(x) (((x) & SYNTH_SYNTH4_PFDDELAY_MASK) >> SYNTH_SYNTH4_PFDDELAY_LSB) +#define SYNTH_SYNTH4_PFDDELAY_SET(x) (((x) << SYNTH_SYNTH4_PFDDELAY_LSB) & SYNTH_SYNTH4_PFDDELAY_MASK) +#define SYNTH_SYNTH4_PFD_DISABLE_MSB 13 +#define SYNTH_SYNTH4_PFD_DISABLE_LSB 13 +#define SYNTH_SYNTH4_PFD_DISABLE_MASK 0x00002000 +#define SYNTH_SYNTH4_PFD_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_PFD_DISABLE_MASK) >> SYNTH_SYNTH4_PFD_DISABLE_LSB) +#define SYNTH_SYNTH4_PFD_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_PFD_DISABLE_LSB) & SYNTH_SYNTH4_PFD_DISABLE_MASK) +#define SYNTH_SYNTH4_PRESCSEL_MSB 12 +#define SYNTH_SYNTH4_PRESCSEL_LSB 11 +#define SYNTH_SYNTH4_PRESCSEL_MASK 0x00001800 +#define SYNTH_SYNTH4_PRESCSEL_GET(x) (((x) & SYNTH_SYNTH4_PRESCSEL_MASK) >> SYNTH_SYNTH4_PRESCSEL_LSB) +#define SYNTH_SYNTH4_PRESCSEL_SET(x) (((x) << SYNTH_SYNTH4_PRESCSEL_LSB) & SYNTH_SYNTH4_PRESCSEL_MASK) +#define SYNTH_SYNTH4_RESET_PRESC_MSB 10 +#define SYNTH_SYNTH4_RESET_PRESC_LSB 10 +#define SYNTH_SYNTH4_RESET_PRESC_MASK 0x00000400 +#define SYNTH_SYNTH4_RESET_PRESC_GET(x) (((x) & SYNTH_SYNTH4_RESET_PRESC_MASK) >> SYNTH_SYNTH4_RESET_PRESC_LSB) +#define SYNTH_SYNTH4_RESET_PRESC_SET(x) (((x) << SYNTH_SYNTH4_RESET_PRESC_LSB) & SYNTH_SYNTH4_RESET_PRESC_MASK) +#define SYNTH_SYNTH4_SDM_DISABLE_MSB 9 +#define SYNTH_SYNTH4_SDM_DISABLE_LSB 9 +#define SYNTH_SYNTH4_SDM_DISABLE_MASK 0x00000200 +#define SYNTH_SYNTH4_SDM_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_SDM_DISABLE_MASK) >> SYNTH_SYNTH4_SDM_DISABLE_LSB) +#define SYNTH_SYNTH4_SDM_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_SDM_DISABLE_LSB) & SYNTH_SYNTH4_SDM_DISABLE_MASK) +#define SYNTH_SYNTH4_SDM_MODE_MSB 8 +#define SYNTH_SYNTH4_SDM_MODE_LSB 8 +#define SYNTH_SYNTH4_SDM_MODE_MASK 0x00000100 +#define SYNTH_SYNTH4_SDM_MODE_GET(x) (((x) & SYNTH_SYNTH4_SDM_MODE_MASK) >> SYNTH_SYNTH4_SDM_MODE_LSB) +#define SYNTH_SYNTH4_SDM_MODE_SET(x) (((x) << SYNTH_SYNTH4_SDM_MODE_LSB) & SYNTH_SYNTH4_SDM_MODE_MASK) +#define SYNTH_SYNTH4_SDM_DITHER_MSB 7 +#define SYNTH_SYNTH4_SDM_DITHER_LSB 6 +#define SYNTH_SYNTH4_SDM_DITHER_MASK 0x000000c0 +#define SYNTH_SYNTH4_SDM_DITHER_GET(x) (((x) & SYNTH_SYNTH4_SDM_DITHER_MASK) >> SYNTH_SYNTH4_SDM_DITHER_LSB) +#define SYNTH_SYNTH4_SDM_DITHER_SET(x) (((x) << SYNTH_SYNTH4_SDM_DITHER_LSB) & SYNTH_SYNTH4_SDM_DITHER_MASK) +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MSB 5 +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB 5 +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020 +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK) >> SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB) +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK) +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MSB 4 +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB 4 +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK 0x00000010 +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_GET(x) (((x) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK) >> SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB) +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_SET(x) (((x) << SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK) +#define SYNTH_SYNTH4_SPARE_MISC_MSB 3 +#define SYNTH_SYNTH4_SPARE_MISC_LSB 2 +#define SYNTH_SYNTH4_SPARE_MISC_MASK 0x0000000c +#define SYNTH_SYNTH4_SPARE_MISC_GET(x) (((x) & SYNTH_SYNTH4_SPARE_MISC_MASK) >> SYNTH_SYNTH4_SPARE_MISC_LSB) +#define SYNTH_SYNTH4_SPARE_MISC_SET(x) (((x) << SYNTH_SYNTH4_SPARE_MISC_LSB) & SYNTH_SYNTH4_SPARE_MISC_MASK) +#define SYNTH_SYNTH4_LONGSHIFTSEL_MSB 1 +#define SYNTH_SYNTH4_LONGSHIFTSEL_LSB 1 +#define SYNTH_SYNTH4_LONGSHIFTSEL_MASK 0x00000002 +#define SYNTH_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK) >> SYNTH_SYNTH4_LONGSHIFTSEL_LSB) +#define SYNTH_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << SYNTH_SYNTH4_LONGSHIFTSEL_LSB) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK) +#define SYNTH_SYNTH4_FORCE_SHIFTREG_MSB 0 +#define SYNTH_SYNTH4_FORCE_SHIFTREG_LSB 0 +#define SYNTH_SYNTH4_FORCE_SHIFTREG_MASK 0x00000001 +#define SYNTH_SYNTH4_FORCE_SHIFTREG_GET(x) (((x) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK) >> SYNTH_SYNTH4_FORCE_SHIFTREG_LSB) +#define SYNTH_SYNTH4_FORCE_SHIFTREG_SET(x) (((x) << SYNTH_SYNTH4_FORCE_SHIFTREG_LSB) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK) + +#define SYNTH_SYNTH5_ADDRESS 0x00000010 +#define SYNTH_SYNTH5_OFFSET 0x00000010 +#define SYNTH_SYNTH5_LOOP_IP0_MSB 31 +#define SYNTH_SYNTH5_LOOP_IP0_LSB 28 +#define SYNTH_SYNTH5_LOOP_IP0_MASK 0xf0000000 +#define SYNTH_SYNTH5_LOOP_IP0_GET(x) (((x) & SYNTH_SYNTH5_LOOP_IP0_MASK) >> SYNTH_SYNTH5_LOOP_IP0_LSB) +#define SYNTH_SYNTH5_LOOP_IP0_SET(x) (((x) << SYNTH_SYNTH5_LOOP_IP0_LSB) & SYNTH_SYNTH5_LOOP_IP0_MASK) +#define SYNTH_SYNTH5_SLOPE_IP_MSB 27 +#define SYNTH_SYNTH5_SLOPE_IP_LSB 25 +#define SYNTH_SYNTH5_SLOPE_IP_MASK 0x0e000000 +#define SYNTH_SYNTH5_SLOPE_IP_GET(x) (((x) & SYNTH_SYNTH5_SLOPE_IP_MASK) >> SYNTH_SYNTH5_SLOPE_IP_LSB) +#define SYNTH_SYNTH5_SLOPE_IP_SET(x) (((x) << SYNTH_SYNTH5_SLOPE_IP_LSB) & SYNTH_SYNTH5_SLOPE_IP_MASK) +#define SYNTH_SYNTH5_CPBIAS_MSB 24 +#define SYNTH_SYNTH5_CPBIAS_LSB 23 +#define SYNTH_SYNTH5_CPBIAS_MASK 0x01800000 +#define SYNTH_SYNTH5_CPBIAS_GET(x) (((x) & SYNTH_SYNTH5_CPBIAS_MASK) >> SYNTH_SYNTH5_CPBIAS_LSB) +#define SYNTH_SYNTH5_CPBIAS_SET(x) (((x) << SYNTH_SYNTH5_CPBIAS_LSB) & SYNTH_SYNTH5_CPBIAS_MASK) +#define SYNTH_SYNTH5_CPSTEERING_EN_MSB 22 +#define SYNTH_SYNTH5_CPSTEERING_EN_LSB 22 +#define SYNTH_SYNTH5_CPSTEERING_EN_MASK 0x00400000 +#define SYNTH_SYNTH5_CPSTEERING_EN_GET(x) (((x) & SYNTH_SYNTH5_CPSTEERING_EN_MASK) >> SYNTH_SYNTH5_CPSTEERING_EN_LSB) +#define SYNTH_SYNTH5_CPSTEERING_EN_SET(x) (((x) << SYNTH_SYNTH5_CPSTEERING_EN_LSB) & SYNTH_SYNTH5_CPSTEERING_EN_MASK) +#define SYNTH_SYNTH5_CPLOWLK_MSB 21 +#define SYNTH_SYNTH5_CPLOWLK_LSB 21 +#define SYNTH_SYNTH5_CPLOWLK_MASK 0x00200000 +#define SYNTH_SYNTH5_CPLOWLK_GET(x) (((x) & SYNTH_SYNTH5_CPLOWLK_MASK) >> SYNTH_SYNTH5_CPLOWLK_LSB) +#define SYNTH_SYNTH5_CPLOWLK_SET(x) (((x) << SYNTH_SYNTH5_CPLOWLK_LSB) & SYNTH_SYNTH5_CPLOWLK_MASK) +#define SYNTH_SYNTH5_LOOPLEAKCUR_MSB 20 +#define SYNTH_SYNTH5_LOOPLEAKCUR_LSB 17 +#define SYNTH_SYNTH5_LOOPLEAKCUR_MASK 0x001e0000 +#define SYNTH_SYNTH5_LOOPLEAKCUR_GET(x) (((x) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK) >> SYNTH_SYNTH5_LOOPLEAKCUR_LSB) +#define SYNTH_SYNTH5_LOOPLEAKCUR_SET(x) (((x) << SYNTH_SYNTH5_LOOPLEAKCUR_LSB) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK) +#define SYNTH_SYNTH5_CAPRANGE1_MSB 16 +#define SYNTH_SYNTH5_CAPRANGE1_LSB 13 +#define SYNTH_SYNTH5_CAPRANGE1_MASK 0x0001e000 +#define SYNTH_SYNTH5_CAPRANGE1_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE1_MASK) >> SYNTH_SYNTH5_CAPRANGE1_LSB) +#define SYNTH_SYNTH5_CAPRANGE1_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE1_LSB) & SYNTH_SYNTH5_CAPRANGE1_MASK) +#define SYNTH_SYNTH5_CAPRANGE2_MSB 12 +#define SYNTH_SYNTH5_CAPRANGE2_LSB 9 +#define SYNTH_SYNTH5_CAPRANGE2_MASK 0x00001e00 +#define SYNTH_SYNTH5_CAPRANGE2_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE2_MASK) >> SYNTH_SYNTH5_CAPRANGE2_LSB) +#define SYNTH_SYNTH5_CAPRANGE2_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE2_LSB) & SYNTH_SYNTH5_CAPRANGE2_MASK) +#define SYNTH_SYNTH5_CAPRANGE3_MSB 8 +#define SYNTH_SYNTH5_CAPRANGE3_LSB 5 +#define SYNTH_SYNTH5_CAPRANGE3_MASK 0x000001e0 +#define SYNTH_SYNTH5_CAPRANGE3_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE3_MASK) >> SYNTH_SYNTH5_CAPRANGE3_LSB) +#define SYNTH_SYNTH5_CAPRANGE3_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE3_LSB) & SYNTH_SYNTH5_CAPRANGE3_MASK) +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MSB 4 +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB 4 +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK 0x00000010 +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB) +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK) +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MSB 3 +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB 2 +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK 0x0000000c +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_GET(x) (((x) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK) >> SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB) +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_SET(x) (((x) << SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK) +#define SYNTH_SYNTH5_SPARE_MSB 1 +#define SYNTH_SYNTH5_SPARE_LSB 0 +#define SYNTH_SYNTH5_SPARE_MASK 0x00000003 +#define SYNTH_SYNTH5_SPARE_GET(x) (((x) & SYNTH_SYNTH5_SPARE_MASK) >> SYNTH_SYNTH5_SPARE_LSB) +#define SYNTH_SYNTH5_SPARE_SET(x) (((x) << SYNTH_SYNTH5_SPARE_LSB) & SYNTH_SYNTH5_SPARE_MASK) + +#define SYNTH_SYNTH6_ADDRESS 0x00000014 +#define SYNTH_SYNTH6_OFFSET 0x00000014 +#define SYNTH_SYNTH6_IRCP_MSB 31 +#define SYNTH_SYNTH6_IRCP_LSB 29 +#define SYNTH_SYNTH6_IRCP_MASK 0xe0000000 +#define SYNTH_SYNTH6_IRCP_GET(x) (((x) & SYNTH_SYNTH6_IRCP_MASK) >> SYNTH_SYNTH6_IRCP_LSB) +#define SYNTH_SYNTH6_IRCP_SET(x) (((x) << SYNTH_SYNTH6_IRCP_LSB) & SYNTH_SYNTH6_IRCP_MASK) +#define SYNTH_SYNTH6_IRVCMON_MSB 28 +#define SYNTH_SYNTH6_IRVCMON_LSB 26 +#define SYNTH_SYNTH6_IRVCMON_MASK 0x1c000000 +#define SYNTH_SYNTH6_IRVCMON_GET(x) (((x) & SYNTH_SYNTH6_IRVCMON_MASK) >> SYNTH_SYNTH6_IRVCMON_LSB) +#define SYNTH_SYNTH6_IRVCMON_SET(x) (((x) << SYNTH_SYNTH6_IRVCMON_LSB) & SYNTH_SYNTH6_IRVCMON_MASK) +#define SYNTH_SYNTH6_IRSPARE_MSB 25 +#define SYNTH_SYNTH6_IRSPARE_LSB 23 +#define SYNTH_SYNTH6_IRSPARE_MASK 0x03800000 +#define SYNTH_SYNTH6_IRSPARE_GET(x) (((x) & SYNTH_SYNTH6_IRSPARE_MASK) >> SYNTH_SYNTH6_IRSPARE_LSB) +#define SYNTH_SYNTH6_IRSPARE_SET(x) (((x) << SYNTH_SYNTH6_IRSPARE_LSB) & SYNTH_SYNTH6_IRSPARE_MASK) +#define SYNTH_SYNTH6_ICPRESC_MSB 22 +#define SYNTH_SYNTH6_ICPRESC_LSB 20 +#define SYNTH_SYNTH6_ICPRESC_MASK 0x00700000 +#define SYNTH_SYNTH6_ICPRESC_GET(x) (((x) & SYNTH_SYNTH6_ICPRESC_MASK) >> SYNTH_SYNTH6_ICPRESC_LSB) +#define SYNTH_SYNTH6_ICPRESC_SET(x) (((x) << SYNTH_SYNTH6_ICPRESC_LSB) & SYNTH_SYNTH6_ICPRESC_MASK) +#define SYNTH_SYNTH6_ICLODIV_MSB 19 +#define SYNTH_SYNTH6_ICLODIV_LSB 17 +#define SYNTH_SYNTH6_ICLODIV_MASK 0x000e0000 +#define SYNTH_SYNTH6_ICLODIV_GET(x) (((x) & SYNTH_SYNTH6_ICLODIV_MASK) >> SYNTH_SYNTH6_ICLODIV_LSB) +#define SYNTH_SYNTH6_ICLODIV_SET(x) (((x) << SYNTH_SYNTH6_ICLODIV_LSB) & SYNTH_SYNTH6_ICLODIV_MASK) +#define SYNTH_SYNTH6_ICLOMIX_MSB 16 +#define SYNTH_SYNTH6_ICLOMIX_LSB 14 +#define SYNTH_SYNTH6_ICLOMIX_MASK 0x0001c000 +#define SYNTH_SYNTH6_ICLOMIX_GET(x) (((x) & SYNTH_SYNTH6_ICLOMIX_MASK) >> SYNTH_SYNTH6_ICLOMIX_LSB) +#define SYNTH_SYNTH6_ICLOMIX_SET(x) (((x) << SYNTH_SYNTH6_ICLOMIX_LSB) & SYNTH_SYNTH6_ICLOMIX_MASK) +#define SYNTH_SYNTH6_ICSPAREA_MSB 13 +#define SYNTH_SYNTH6_ICSPAREA_LSB 11 +#define SYNTH_SYNTH6_ICSPAREA_MASK 0x00003800 +#define SYNTH_SYNTH6_ICSPAREA_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREA_MASK) >> SYNTH_SYNTH6_ICSPAREA_LSB) +#define SYNTH_SYNTH6_ICSPAREA_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREA_LSB) & SYNTH_SYNTH6_ICSPAREA_MASK) +#define SYNTH_SYNTH6_ICSPAREB_MSB 10 +#define SYNTH_SYNTH6_ICSPAREB_LSB 8 +#define SYNTH_SYNTH6_ICSPAREB_MASK 0x00000700 +#define SYNTH_SYNTH6_ICSPAREB_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREB_MASK) >> SYNTH_SYNTH6_ICSPAREB_LSB) +#define SYNTH_SYNTH6_ICSPAREB_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREB_LSB) & SYNTH_SYNTH6_ICSPAREB_MASK) +#define SYNTH_SYNTH6_ICVCO_MSB 7 +#define SYNTH_SYNTH6_ICVCO_LSB 5 +#define SYNTH_SYNTH6_ICVCO_MASK 0x000000e0 +#define SYNTH_SYNTH6_ICVCO_GET(x) (((x) & SYNTH_SYNTH6_ICVCO_MASK) >> SYNTH_SYNTH6_ICVCO_LSB) +#define SYNTH_SYNTH6_ICVCO_SET(x) (((x) << SYNTH_SYNTH6_ICVCO_LSB) & SYNTH_SYNTH6_ICVCO_MASK) +#define SYNTH_SYNTH6_VCOBUFBIAS_MSB 4 +#define SYNTH_SYNTH6_VCOBUFBIAS_LSB 3 +#define SYNTH_SYNTH6_VCOBUFBIAS_MASK 0x00000018 +#define SYNTH_SYNTH6_VCOBUFBIAS_GET(x) (((x) & SYNTH_SYNTH6_VCOBUFBIAS_MASK) >> SYNTH_SYNTH6_VCOBUFBIAS_LSB) +#define SYNTH_SYNTH6_VCOBUFBIAS_SET(x) (((x) << SYNTH_SYNTH6_VCOBUFBIAS_LSB) & SYNTH_SYNTH6_VCOBUFBIAS_MASK) +#define SYNTH_SYNTH6_SPARE_BIAS_MSB 2 +#define SYNTH_SYNTH6_SPARE_BIAS_LSB 0 +#define SYNTH_SYNTH6_SPARE_BIAS_MASK 0x00000007 +#define SYNTH_SYNTH6_SPARE_BIAS_GET(x) (((x) & SYNTH_SYNTH6_SPARE_BIAS_MASK) >> SYNTH_SYNTH6_SPARE_BIAS_LSB) +#define SYNTH_SYNTH6_SPARE_BIAS_SET(x) (((x) << SYNTH_SYNTH6_SPARE_BIAS_LSB) & SYNTH_SYNTH6_SPARE_BIAS_MASK) + +#define SYNTH_SYNTH7_ADDRESS 0x00000018 +#define SYNTH_SYNTH7_OFFSET 0x00000018 +#define SYNTH_SYNTH7_SYNTH_ON_MSB 31 +#define SYNTH_SYNTH7_SYNTH_ON_LSB 31 +#define SYNTH_SYNTH7_SYNTH_ON_MASK 0x80000000 +#define SYNTH_SYNTH7_SYNTH_ON_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_ON_MASK) >> SYNTH_SYNTH7_SYNTH_ON_LSB) +#define SYNTH_SYNTH7_SYNTH_ON_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_ON_LSB) & SYNTH_SYNTH7_SYNTH_ON_MASK) +#define SYNTH_SYNTH7_SYNTH_SM_STATE_MSB 30 +#define SYNTH_SYNTH7_SYNTH_SM_STATE_LSB 27 +#define SYNTH_SYNTH7_SYNTH_SM_STATE_MASK 0x78000000 +#define SYNTH_SYNTH7_SYNTH_SM_STATE_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK) >> SYNTH_SYNTH7_SYNTH_SM_STATE_LSB) +#define SYNTH_SYNTH7_SYNTH_SM_STATE_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_SM_STATE_LSB) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK) +#define SYNTH_SYNTH7_CAP_SEARCH_MSB 26 +#define SYNTH_SYNTH7_CAP_SEARCH_LSB 26 +#define SYNTH_SYNTH7_CAP_SEARCH_MASK 0x04000000 +#define SYNTH_SYNTH7_CAP_SEARCH_GET(x) (((x) & SYNTH_SYNTH7_CAP_SEARCH_MASK) >> SYNTH_SYNTH7_CAP_SEARCH_LSB) +#define SYNTH_SYNTH7_CAP_SEARCH_SET(x) (((x) << SYNTH_SYNTH7_CAP_SEARCH_LSB) & SYNTH_SYNTH7_CAP_SEARCH_MASK) +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MSB 25 +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB 25 +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK 0x02000000 +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK) >> SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB) +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK) +#define SYNTH_SYNTH7_PIN_VC_MSB 24 +#define SYNTH_SYNTH7_PIN_VC_LSB 24 +#define SYNTH_SYNTH7_PIN_VC_MASK 0x01000000 +#define SYNTH_SYNTH7_PIN_VC_GET(x) (((x) & SYNTH_SYNTH7_PIN_VC_MASK) >> SYNTH_SYNTH7_PIN_VC_LSB) +#define SYNTH_SYNTH7_PIN_VC_SET(x) (((x) << SYNTH_SYNTH7_PIN_VC_LSB) & SYNTH_SYNTH7_PIN_VC_MASK) +#define SYNTH_SYNTH7_VCO_CAP_ST_MSB 23 +#define SYNTH_SYNTH7_VCO_CAP_ST_LSB 16 +#define SYNTH_SYNTH7_VCO_CAP_ST_MASK 0x00ff0000 +#define SYNTH_SYNTH7_VCO_CAP_ST_GET(x) (((x) & SYNTH_SYNTH7_VCO_CAP_ST_MASK) >> SYNTH_SYNTH7_VCO_CAP_ST_LSB) +#define SYNTH_SYNTH7_VCO_CAP_ST_SET(x) (((x) << SYNTH_SYNTH7_VCO_CAP_ST_LSB) & SYNTH_SYNTH7_VCO_CAP_ST_MASK) +#define SYNTH_SYNTH7_SHORT_R_MSB 15 +#define SYNTH_SYNTH7_SHORT_R_LSB 15 +#define SYNTH_SYNTH7_SHORT_R_MASK 0x00008000 +#define SYNTH_SYNTH7_SHORT_R_GET(x) (((x) & SYNTH_SYNTH7_SHORT_R_MASK) >> SYNTH_SYNTH7_SHORT_R_LSB) +#define SYNTH_SYNTH7_SHORT_R_SET(x) (((x) << SYNTH_SYNTH7_SHORT_R_LSB) & SYNTH_SYNTH7_SHORT_R_MASK) +#define SYNTH_SYNTH7_RESET_RFD_MSB 14 +#define SYNTH_SYNTH7_RESET_RFD_LSB 14 +#define SYNTH_SYNTH7_RESET_RFD_MASK 0x00004000 +#define SYNTH_SYNTH7_RESET_RFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_RFD_MASK) >> SYNTH_SYNTH7_RESET_RFD_LSB) +#define SYNTH_SYNTH7_RESET_RFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_RFD_LSB) & SYNTH_SYNTH7_RESET_RFD_MASK) +#define SYNTH_SYNTH7_RESET_PFD_MSB 13 +#define SYNTH_SYNTH7_RESET_PFD_LSB 13 +#define SYNTH_SYNTH7_RESET_PFD_MASK 0x00002000 +#define SYNTH_SYNTH7_RESET_PFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_PFD_MASK) >> SYNTH_SYNTH7_RESET_PFD_LSB) +#define SYNTH_SYNTH7_RESET_PFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_PFD_LSB) & SYNTH_SYNTH7_RESET_PFD_MASK) +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MSB 12 +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB 12 +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK 0x00001000 +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_GET(x) (((x) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK) >> SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB) +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_SET(x) (((x) << SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK) +#define SYNTH_SYNTH7_RESET_SDM_B_MSB 11 +#define SYNTH_SYNTH7_RESET_SDM_B_LSB 11 +#define SYNTH_SYNTH7_RESET_SDM_B_MASK 0x00000800 +#define SYNTH_SYNTH7_RESET_SDM_B_GET(x) (((x) & SYNTH_SYNTH7_RESET_SDM_B_MASK) >> SYNTH_SYNTH7_RESET_SDM_B_LSB) +#define SYNTH_SYNTH7_RESET_SDM_B_SET(x) (((x) << SYNTH_SYNTH7_RESET_SDM_B_LSB) & SYNTH_SYNTH7_RESET_SDM_B_MASK) +#define SYNTH_SYNTH7_VC2HIGH_MSB 10 +#define SYNTH_SYNTH7_VC2HIGH_LSB 10 +#define SYNTH_SYNTH7_VC2HIGH_MASK 0x00000400 +#define SYNTH_SYNTH7_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH7_VC2HIGH_MASK) >> SYNTH_SYNTH7_VC2HIGH_LSB) +#define SYNTH_SYNTH7_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH7_VC2HIGH_LSB) & SYNTH_SYNTH7_VC2HIGH_MASK) +#define SYNTH_SYNTH7_VC2LOW_MSB 9 +#define SYNTH_SYNTH7_VC2LOW_LSB 9 +#define SYNTH_SYNTH7_VC2LOW_MASK 0x00000200 +#define SYNTH_SYNTH7_VC2LOW_GET(x) (((x) & SYNTH_SYNTH7_VC2LOW_MASK) >> SYNTH_SYNTH7_VC2LOW_LSB) +#define SYNTH_SYNTH7_VC2LOW_SET(x) (((x) << SYNTH_SYNTH7_VC2LOW_LSB) & SYNTH_SYNTH7_VC2LOW_MASK) +#define SYNTH_SYNTH7_LOOP_IP_MSB 8 +#define SYNTH_SYNTH7_LOOP_IP_LSB 5 +#define SYNTH_SYNTH7_LOOP_IP_MASK 0x000001e0 +#define SYNTH_SYNTH7_LOOP_IP_GET(x) (((x) & SYNTH_SYNTH7_LOOP_IP_MASK) >> SYNTH_SYNTH7_LOOP_IP_LSB) +#define SYNTH_SYNTH7_LOOP_IP_SET(x) (((x) << SYNTH_SYNTH7_LOOP_IP_LSB) & SYNTH_SYNTH7_LOOP_IP_MASK) +#define SYNTH_SYNTH7_LOBUF5GTUNE_MSB 4 +#define SYNTH_SYNTH7_LOBUF5GTUNE_LSB 3 +#define SYNTH_SYNTH7_LOBUF5GTUNE_MASK 0x00000018 +#define SYNTH_SYNTH7_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH7_LOBUF5GTUNE_LSB) +#define SYNTH_SYNTH7_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH7_LOBUF5GTUNE_LSB) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK) +#define SYNTH_SYNTH7_SPARE_READ_MSB 2 +#define SYNTH_SYNTH7_SPARE_READ_LSB 0 +#define SYNTH_SYNTH7_SPARE_READ_MASK 0x00000007 +#define SYNTH_SYNTH7_SPARE_READ_GET(x) (((x) & SYNTH_SYNTH7_SPARE_READ_MASK) >> SYNTH_SYNTH7_SPARE_READ_LSB) +#define SYNTH_SYNTH7_SPARE_READ_SET(x) (((x) << SYNTH_SYNTH7_SPARE_READ_LSB) & SYNTH_SYNTH7_SPARE_READ_MASK) + +#define SYNTH_SYNTH8_ADDRESS 0x0000001c +#define SYNTH_SYNTH8_OFFSET 0x0000001c +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MSB 31 +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB 31 +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK 0x80000000 +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_GET(x) (((x) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK) >> SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB) +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_SET(x) (((x) << SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK) +#define SYNTH_SYNTH8_FRACMODE_MSB 30 +#define SYNTH_SYNTH8_FRACMODE_LSB 30 +#define SYNTH_SYNTH8_FRACMODE_MASK 0x40000000 +#define SYNTH_SYNTH8_FRACMODE_GET(x) (((x) & SYNTH_SYNTH8_FRACMODE_MASK) >> SYNTH_SYNTH8_FRACMODE_LSB) +#define SYNTH_SYNTH8_FRACMODE_SET(x) (((x) << SYNTH_SYNTH8_FRACMODE_LSB) & SYNTH_SYNTH8_FRACMODE_MASK) +#define SYNTH_SYNTH8_AMODEREFSEL_MSB 29 +#define SYNTH_SYNTH8_AMODEREFSEL_LSB 28 +#define SYNTH_SYNTH8_AMODEREFSEL_MASK 0x30000000 +#define SYNTH_SYNTH8_AMODEREFSEL_GET(x) (((x) & SYNTH_SYNTH8_AMODEREFSEL_MASK) >> SYNTH_SYNTH8_AMODEREFSEL_LSB) +#define SYNTH_SYNTH8_AMODEREFSEL_SET(x) (((x) << SYNTH_SYNTH8_AMODEREFSEL_LSB) & SYNTH_SYNTH8_AMODEREFSEL_MASK) +#define SYNTH_SYNTH8_SPARE_MSB 27 +#define SYNTH_SYNTH8_SPARE_LSB 27 +#define SYNTH_SYNTH8_SPARE_MASK 0x08000000 +#define SYNTH_SYNTH8_SPARE_GET(x) (((x) & SYNTH_SYNTH8_SPARE_MASK) >> SYNTH_SYNTH8_SPARE_LSB) +#define SYNTH_SYNTH8_SPARE_SET(x) (((x) << SYNTH_SYNTH8_SPARE_LSB) & SYNTH_SYNTH8_SPARE_MASK) +#define SYNTH_SYNTH8_CHANSEL_MSB 26 +#define SYNTH_SYNTH8_CHANSEL_LSB 18 +#define SYNTH_SYNTH8_CHANSEL_MASK 0x07fc0000 +#define SYNTH_SYNTH8_CHANSEL_GET(x) (((x) & SYNTH_SYNTH8_CHANSEL_MASK) >> SYNTH_SYNTH8_CHANSEL_LSB) +#define SYNTH_SYNTH8_CHANSEL_SET(x) (((x) << SYNTH_SYNTH8_CHANSEL_LSB) & SYNTH_SYNTH8_CHANSEL_MASK) +#define SYNTH_SYNTH8_CHANFRAC_MSB 17 +#define SYNTH_SYNTH8_CHANFRAC_LSB 1 +#define SYNTH_SYNTH8_CHANFRAC_MASK 0x0003fffe +#define SYNTH_SYNTH8_CHANFRAC_GET(x) (((x) & SYNTH_SYNTH8_CHANFRAC_MASK) >> SYNTH_SYNTH8_CHANFRAC_LSB) +#define SYNTH_SYNTH8_CHANFRAC_SET(x) (((x) << SYNTH_SYNTH8_CHANFRAC_LSB) & SYNTH_SYNTH8_CHANFRAC_MASK) +#define SYNTH_SYNTH8_FORCE_FRACLSB_MSB 0 +#define SYNTH_SYNTH8_FORCE_FRACLSB_LSB 0 +#define SYNTH_SYNTH8_FORCE_FRACLSB_MASK 0x00000001 +#define SYNTH_SYNTH8_FORCE_FRACLSB_GET(x) (((x) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK) >> SYNTH_SYNTH8_FORCE_FRACLSB_LSB) +#define SYNTH_SYNTH8_FORCE_FRACLSB_SET(x) (((x) << SYNTH_SYNTH8_FORCE_FRACLSB_LSB) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK) + +#define RF5G_RF5G1_ADDRESS 0x00000020 +#define RF5G_RF5G1_OFFSET 0x00000020 +#define RF5G_RF5G1_PDTXLO5_MSB 31 +#define RF5G_RF5G1_PDTXLO5_LSB 31 +#define RF5G_RF5G1_PDTXLO5_MASK 0x80000000 +#define RF5G_RF5G1_PDTXLO5_GET(x) (((x) & RF5G_RF5G1_PDTXLO5_MASK) >> RF5G_RF5G1_PDTXLO5_LSB) +#define RF5G_RF5G1_PDTXLO5_SET(x) (((x) << RF5G_RF5G1_PDTXLO5_LSB) & RF5G_RF5G1_PDTXLO5_MASK) +#define RF5G_RF5G1_PDTXMIX5_MSB 30 +#define RF5G_RF5G1_PDTXMIX5_LSB 30 +#define RF5G_RF5G1_PDTXMIX5_MASK 0x40000000 +#define RF5G_RF5G1_PDTXMIX5_GET(x) (((x) & RF5G_RF5G1_PDTXMIX5_MASK) >> RF5G_RF5G1_PDTXMIX5_LSB) +#define RF5G_RF5G1_PDTXMIX5_SET(x) (((x) << RF5G_RF5G1_PDTXMIX5_LSB) & RF5G_RF5G1_PDTXMIX5_MASK) +#define RF5G_RF5G1_PDTXBUF5_MSB 29 +#define RF5G_RF5G1_PDTXBUF5_LSB 29 +#define RF5G_RF5G1_PDTXBUF5_MASK 0x20000000 +#define RF5G_RF5G1_PDTXBUF5_GET(x) (((x) & RF5G_RF5G1_PDTXBUF5_MASK) >> RF5G_RF5G1_PDTXBUF5_LSB) +#define RF5G_RF5G1_PDTXBUF5_SET(x) (((x) << RF5G_RF5G1_PDTXBUF5_LSB) & RF5G_RF5G1_PDTXBUF5_MASK) +#define RF5G_RF5G1_PDPADRV5_MSB 28 +#define RF5G_RF5G1_PDPADRV5_LSB 28 +#define RF5G_RF5G1_PDPADRV5_MASK 0x10000000 +#define RF5G_RF5G1_PDPADRV5_GET(x) (((x) & RF5G_RF5G1_PDPADRV5_MASK) >> RF5G_RF5G1_PDPADRV5_LSB) +#define RF5G_RF5G1_PDPADRV5_SET(x) (((x) << RF5G_RF5G1_PDPADRV5_LSB) & RF5G_RF5G1_PDPADRV5_MASK) +#define RF5G_RF5G1_PDPAOUT5_MSB 27 +#define RF5G_RF5G1_PDPAOUT5_LSB 27 +#define RF5G_RF5G1_PDPAOUT5_MASK 0x08000000 +#define RF5G_RF5G1_PDPAOUT5_GET(x) (((x) & RF5G_RF5G1_PDPAOUT5_MASK) >> RF5G_RF5G1_PDPAOUT5_LSB) +#define RF5G_RF5G1_PDPAOUT5_SET(x) (((x) << RF5G_RF5G1_PDPAOUT5_LSB) & RF5G_RF5G1_PDPAOUT5_MASK) +#define RF5G_RF5G1_TUNE_PADRV5_MSB 26 +#define RF5G_RF5G1_TUNE_PADRV5_LSB 24 +#define RF5G_RF5G1_TUNE_PADRV5_MASK 0x07000000 +#define RF5G_RF5G1_TUNE_PADRV5_GET(x) (((x) & RF5G_RF5G1_TUNE_PADRV5_MASK) >> RF5G_RF5G1_TUNE_PADRV5_LSB) +#define RF5G_RF5G1_TUNE_PADRV5_SET(x) (((x) << RF5G_RF5G1_TUNE_PADRV5_LSB) & RF5G_RF5G1_TUNE_PADRV5_MASK) +#define RF5G_RF5G1_PWDTXPKD_MSB 23 +#define RF5G_RF5G1_PWDTXPKD_LSB 21 +#define RF5G_RF5G1_PWDTXPKD_MASK 0x00e00000 +#define RF5G_RF5G1_PWDTXPKD_GET(x) (((x) & RF5G_RF5G1_PWDTXPKD_MASK) >> RF5G_RF5G1_PWDTXPKD_LSB) +#define RF5G_RF5G1_PWDTXPKD_SET(x) (((x) << RF5G_RF5G1_PWDTXPKD_LSB) & RF5G_RF5G1_PWDTXPKD_MASK) +#define RF5G_RF5G1_DB5_MSB 20 +#define RF5G_RF5G1_DB5_LSB 18 +#define RF5G_RF5G1_DB5_MASK 0x001c0000 +#define RF5G_RF5G1_DB5_GET(x) (((x) & RF5G_RF5G1_DB5_MASK) >> RF5G_RF5G1_DB5_LSB) +#define RF5G_RF5G1_DB5_SET(x) (((x) << RF5G_RF5G1_DB5_LSB) & RF5G_RF5G1_DB5_MASK) +#define RF5G_RF5G1_OB5_MSB 17 +#define RF5G_RF5G1_OB5_LSB 15 +#define RF5G_RF5G1_OB5_MASK 0x00038000 +#define RF5G_RF5G1_OB5_GET(x) (((x) & RF5G_RF5G1_OB5_MASK) >> RF5G_RF5G1_OB5_LSB) +#define RF5G_RF5G1_OB5_SET(x) (((x) << RF5G_RF5G1_OB5_LSB) & RF5G_RF5G1_OB5_MASK) +#define RF5G_RF5G1_TX5_ATB_SEL_MSB 14 +#define RF5G_RF5G1_TX5_ATB_SEL_LSB 12 +#define RF5G_RF5G1_TX5_ATB_SEL_MASK 0x00007000 +#define RF5G_RF5G1_TX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_TX5_ATB_SEL_MASK) >> RF5G_RF5G1_TX5_ATB_SEL_LSB) +#define RF5G_RF5G1_TX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_TX5_ATB_SEL_LSB) & RF5G_RF5G1_TX5_ATB_SEL_MASK) +#define RF5G_RF5G1_PDLO5DIV_MSB 11 +#define RF5G_RF5G1_PDLO5DIV_LSB 11 +#define RF5G_RF5G1_PDLO5DIV_MASK 0x00000800 +#define RF5G_RF5G1_PDLO5DIV_GET(x) (((x) & RF5G_RF5G1_PDLO5DIV_MASK) >> RF5G_RF5G1_PDLO5DIV_LSB) +#define RF5G_RF5G1_PDLO5DIV_SET(x) (((x) << RF5G_RF5G1_PDLO5DIV_LSB) & RF5G_RF5G1_PDLO5DIV_MASK) +#define RF5G_RF5G1_PDLO5MIX_MSB 10 +#define RF5G_RF5G1_PDLO5MIX_LSB 10 +#define RF5G_RF5G1_PDLO5MIX_MASK 0x00000400 +#define RF5G_RF5G1_PDLO5MIX_GET(x) (((x) & RF5G_RF5G1_PDLO5MIX_MASK) >> RF5G_RF5G1_PDLO5MIX_LSB) +#define RF5G_RF5G1_PDLO5MIX_SET(x) (((x) << RF5G_RF5G1_PDLO5MIX_LSB) & RF5G_RF5G1_PDLO5MIX_MASK) +#define RF5G_RF5G1_PDQBUF5_MSB 9 +#define RF5G_RF5G1_PDQBUF5_LSB 9 +#define RF5G_RF5G1_PDQBUF5_MASK 0x00000200 +#define RF5G_RF5G1_PDQBUF5_GET(x) (((x) & RF5G_RF5G1_PDQBUF5_MASK) >> RF5G_RF5G1_PDQBUF5_LSB) +#define RF5G_RF5G1_PDQBUF5_SET(x) (((x) << RF5G_RF5G1_PDQBUF5_LSB) & RF5G_RF5G1_PDQBUF5_MASK) +#define RF5G_RF5G1_PDLO5AGC_MSB 8 +#define RF5G_RF5G1_PDLO5AGC_LSB 8 +#define RF5G_RF5G1_PDLO5AGC_MASK 0x00000100 +#define RF5G_RF5G1_PDLO5AGC_GET(x) (((x) & RF5G_RF5G1_PDLO5AGC_MASK) >> RF5G_RF5G1_PDLO5AGC_LSB) +#define RF5G_RF5G1_PDLO5AGC_SET(x) (((x) << RF5G_RF5G1_PDLO5AGC_LSB) & RF5G_RF5G1_PDLO5AGC_MASK) +#define RF5G_RF5G1_PDREGLO5_MSB 7 +#define RF5G_RF5G1_PDREGLO5_LSB 7 +#define RF5G_RF5G1_PDREGLO5_MASK 0x00000080 +#define RF5G_RF5G1_PDREGLO5_GET(x) (((x) & RF5G_RF5G1_PDREGLO5_MASK) >> RF5G_RF5G1_PDREGLO5_LSB) +#define RF5G_RF5G1_PDREGLO5_SET(x) (((x) << RF5G_RF5G1_PDREGLO5_LSB) & RF5G_RF5G1_PDREGLO5_MASK) +#define RF5G_RF5G1_LO5_ATB_SEL_MSB 6 +#define RF5G_RF5G1_LO5_ATB_SEL_LSB 4 +#define RF5G_RF5G1_LO5_ATB_SEL_MASK 0x00000070 +#define RF5G_RF5G1_LO5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_LO5_ATB_SEL_MASK) >> RF5G_RF5G1_LO5_ATB_SEL_LSB) +#define RF5G_RF5G1_LO5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_LO5_ATB_SEL_LSB) & RF5G_RF5G1_LO5_ATB_SEL_MASK) +#define RF5G_RF5G1_LO5CONTROL_MSB 3 +#define RF5G_RF5G1_LO5CONTROL_LSB 3 +#define RF5G_RF5G1_LO5CONTROL_MASK 0x00000008 +#define RF5G_RF5G1_LO5CONTROL_GET(x) (((x) & RF5G_RF5G1_LO5CONTROL_MASK) >> RF5G_RF5G1_LO5CONTROL_LSB) +#define RF5G_RF5G1_LO5CONTROL_SET(x) (((x) << RF5G_RF5G1_LO5CONTROL_LSB) & RF5G_RF5G1_LO5CONTROL_MASK) +#define RF5G_RF5G1_REGLO_BYPASS5_MSB 2 +#define RF5G_RF5G1_REGLO_BYPASS5_LSB 2 +#define RF5G_RF5G1_REGLO_BYPASS5_MASK 0x00000004 +#define RF5G_RF5G1_REGLO_BYPASS5_GET(x) (((x) & RF5G_RF5G1_REGLO_BYPASS5_MASK) >> RF5G_RF5G1_REGLO_BYPASS5_LSB) +#define RF5G_RF5G1_REGLO_BYPASS5_SET(x) (((x) << RF5G_RF5G1_REGLO_BYPASS5_LSB) & RF5G_RF5G1_REGLO_BYPASS5_MASK) +#define RF5G_RF5G1_SPARE_MSB 1 +#define RF5G_RF5G1_SPARE_LSB 0 +#define RF5G_RF5G1_SPARE_MASK 0x00000003 +#define RF5G_RF5G1_SPARE_GET(x) (((x) & RF5G_RF5G1_SPARE_MASK) >> RF5G_RF5G1_SPARE_LSB) +#define RF5G_RF5G1_SPARE_SET(x) (((x) << RF5G_RF5G1_SPARE_LSB) & RF5G_RF5G1_SPARE_MASK) + +#define RF5G_RF5G2_ADDRESS 0x00000024 +#define RF5G_RF5G2_OFFSET 0x00000024 +#define RF5G_RF5G2_AGCLO_B_MSB 31 +#define RF5G_RF5G2_AGCLO_B_LSB 29 +#define RF5G_RF5G2_AGCLO_B_MASK 0xe0000000 +#define RF5G_RF5G2_AGCLO_B_GET(x) (((x) & RF5G_RF5G2_AGCLO_B_MASK) >> RF5G_RF5G2_AGCLO_B_LSB) +#define RF5G_RF5G2_AGCLO_B_SET(x) (((x) << RF5G_RF5G2_AGCLO_B_LSB) & RF5G_RF5G2_AGCLO_B_MASK) +#define RF5G_RF5G2_RX5_ATB_SEL_MSB 28 +#define RF5G_RF5G2_RX5_ATB_SEL_LSB 26 +#define RF5G_RF5G2_RX5_ATB_SEL_MASK 0x1c000000 +#define RF5G_RF5G2_RX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G2_RX5_ATB_SEL_MASK) >> RF5G_RF5G2_RX5_ATB_SEL_LSB) +#define RF5G_RF5G2_RX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G2_RX5_ATB_SEL_LSB) & RF5G_RF5G2_RX5_ATB_SEL_MASK) +#define RF5G_RF5G2_PDCMOSLO5_MSB 25 +#define RF5G_RF5G2_PDCMOSLO5_LSB 25 +#define RF5G_RF5G2_PDCMOSLO5_MASK 0x02000000 +#define RF5G_RF5G2_PDCMOSLO5_GET(x) (((x) & RF5G_RF5G2_PDCMOSLO5_MASK) >> RF5G_RF5G2_PDCMOSLO5_LSB) +#define RF5G_RF5G2_PDCMOSLO5_SET(x) (((x) << RF5G_RF5G2_PDCMOSLO5_LSB) & RF5G_RF5G2_PDCMOSLO5_MASK) +#define RF5G_RF5G2_PDVGM5_MSB 24 +#define RF5G_RF5G2_PDVGM5_LSB 24 +#define RF5G_RF5G2_PDVGM5_MASK 0x01000000 +#define RF5G_RF5G2_PDVGM5_GET(x) (((x) & RF5G_RF5G2_PDVGM5_MASK) >> RF5G_RF5G2_PDVGM5_LSB) +#define RF5G_RF5G2_PDVGM5_SET(x) (((x) << RF5G_RF5G2_PDVGM5_LSB) & RF5G_RF5G2_PDVGM5_MASK) +#define RF5G_RF5G2_PDCSLNA5_MSB 23 +#define RF5G_RF5G2_PDCSLNA5_LSB 23 +#define RF5G_RF5G2_PDCSLNA5_MASK 0x00800000 +#define RF5G_RF5G2_PDCSLNA5_GET(x) (((x) & RF5G_RF5G2_PDCSLNA5_MASK) >> RF5G_RF5G2_PDCSLNA5_LSB) +#define RF5G_RF5G2_PDCSLNA5_SET(x) (((x) << RF5G_RF5G2_PDCSLNA5_LSB) & RF5G_RF5G2_PDCSLNA5_MASK) +#define RF5G_RF5G2_PDRFVGA5_MSB 22 +#define RF5G_RF5G2_PDRFVGA5_LSB 22 +#define RF5G_RF5G2_PDRFVGA5_MASK 0x00400000 +#define RF5G_RF5G2_PDRFVGA5_GET(x) (((x) & RF5G_RF5G2_PDRFVGA5_MASK) >> RF5G_RF5G2_PDRFVGA5_LSB) +#define RF5G_RF5G2_PDRFVGA5_SET(x) (((x) << RF5G_RF5G2_PDRFVGA5_LSB) & RF5G_RF5G2_PDRFVGA5_MASK) +#define RF5G_RF5G2_PDREGFE5_MSB 21 +#define RF5G_RF5G2_PDREGFE5_LSB 21 +#define RF5G_RF5G2_PDREGFE5_MASK 0x00200000 +#define RF5G_RF5G2_PDREGFE5_GET(x) (((x) & RF5G_RF5G2_PDREGFE5_MASK) >> RF5G_RF5G2_PDREGFE5_LSB) +#define RF5G_RF5G2_PDREGFE5_SET(x) (((x) << RF5G_RF5G2_PDREGFE5_LSB) & RF5G_RF5G2_PDREGFE5_MASK) +#define RF5G_RF5G2_TUNE_RFVGA5_MSB 20 +#define RF5G_RF5G2_TUNE_RFVGA5_LSB 18 +#define RF5G_RF5G2_TUNE_RFVGA5_MASK 0x001c0000 +#define RF5G_RF5G2_TUNE_RFVGA5_GET(x) (((x) & RF5G_RF5G2_TUNE_RFVGA5_MASK) >> RF5G_RF5G2_TUNE_RFVGA5_LSB) +#define RF5G_RF5G2_TUNE_RFVGA5_SET(x) (((x) << RF5G_RF5G2_TUNE_RFVGA5_LSB) & RF5G_RF5G2_TUNE_RFVGA5_MASK) +#define RF5G_RF5G2_BRFVGA5_MSB 17 +#define RF5G_RF5G2_BRFVGA5_LSB 15 +#define RF5G_RF5G2_BRFVGA5_MASK 0x00038000 +#define RF5G_RF5G2_BRFVGA5_GET(x) (((x) & RF5G_RF5G2_BRFVGA5_MASK) >> RF5G_RF5G2_BRFVGA5_LSB) +#define RF5G_RF5G2_BRFVGA5_SET(x) (((x) << RF5G_RF5G2_BRFVGA5_LSB) & RF5G_RF5G2_BRFVGA5_MASK) +#define RF5G_RF5G2_BCSLNA5_MSB 14 +#define RF5G_RF5G2_BCSLNA5_LSB 12 +#define RF5G_RF5G2_BCSLNA5_MASK 0x00007000 +#define RF5G_RF5G2_BCSLNA5_GET(x) (((x) & RF5G_RF5G2_BCSLNA5_MASK) >> RF5G_RF5G2_BCSLNA5_LSB) +#define RF5G_RF5G2_BCSLNA5_SET(x) (((x) << RF5G_RF5G2_BCSLNA5_LSB) & RF5G_RF5G2_BCSLNA5_MASK) +#define RF5G_RF5G2_BVGM5_MSB 11 +#define RF5G_RF5G2_BVGM5_LSB 9 +#define RF5G_RF5G2_BVGM5_MASK 0x00000e00 +#define RF5G_RF5G2_BVGM5_GET(x) (((x) & RF5G_RF5G2_BVGM5_MASK) >> RF5G_RF5G2_BVGM5_LSB) +#define RF5G_RF5G2_BVGM5_SET(x) (((x) << RF5G_RF5G2_BVGM5_LSB) & RF5G_RF5G2_BVGM5_MASK) +#define RF5G_RF5G2_REGFE_BYPASS5_MSB 8 +#define RF5G_RF5G2_REGFE_BYPASS5_LSB 8 +#define RF5G_RF5G2_REGFE_BYPASS5_MASK 0x00000100 +#define RF5G_RF5G2_REGFE_BYPASS5_GET(x) (((x) & RF5G_RF5G2_REGFE_BYPASS5_MASK) >> RF5G_RF5G2_REGFE_BYPASS5_LSB) +#define RF5G_RF5G2_REGFE_BYPASS5_SET(x) (((x) << RF5G_RF5G2_REGFE_BYPASS5_LSB) & RF5G_RF5G2_REGFE_BYPASS5_MASK) +#define RF5G_RF5G2_LNA5_ATTENMODE_MSB 7 +#define RF5G_RF5G2_LNA5_ATTENMODE_LSB 6 +#define RF5G_RF5G2_LNA5_ATTENMODE_MASK 0x000000c0 +#define RF5G_RF5G2_LNA5_ATTENMODE_GET(x) (((x) & RF5G_RF5G2_LNA5_ATTENMODE_MASK) >> RF5G_RF5G2_LNA5_ATTENMODE_LSB) +#define RF5G_RF5G2_LNA5_ATTENMODE_SET(x) (((x) << RF5G_RF5G2_LNA5_ATTENMODE_LSB) & RF5G_RF5G2_LNA5_ATTENMODE_MASK) +#define RF5G_RF5G2_ENABLE_PCA_MSB 5 +#define RF5G_RF5G2_ENABLE_PCA_LSB 5 +#define RF5G_RF5G2_ENABLE_PCA_MASK 0x00000020 +#define RF5G_RF5G2_ENABLE_PCA_GET(x) (((x) & RF5G_RF5G2_ENABLE_PCA_MASK) >> RF5G_RF5G2_ENABLE_PCA_LSB) +#define RF5G_RF5G2_ENABLE_PCA_SET(x) (((x) << RF5G_RF5G2_ENABLE_PCA_LSB) & RF5G_RF5G2_ENABLE_PCA_MASK) +#define RF5G_RF5G2_TUNE_LO_MSB 4 +#define RF5G_RF5G2_TUNE_LO_LSB 2 +#define RF5G_RF5G2_TUNE_LO_MASK 0x0000001c +#define RF5G_RF5G2_TUNE_LO_GET(x) (((x) & RF5G_RF5G2_TUNE_LO_MASK) >> RF5G_RF5G2_TUNE_LO_LSB) +#define RF5G_RF5G2_TUNE_LO_SET(x) (((x) << RF5G_RF5G2_TUNE_LO_LSB) & RF5G_RF5G2_TUNE_LO_MASK) +#define RF5G_RF5G2_SPARE_MSB 1 +#define RF5G_RF5G2_SPARE_LSB 0 +#define RF5G_RF5G2_SPARE_MASK 0x00000003 +#define RF5G_RF5G2_SPARE_GET(x) (((x) & RF5G_RF5G2_SPARE_MASK) >> RF5G_RF5G2_SPARE_LSB) +#define RF5G_RF5G2_SPARE_SET(x) (((x) << RF5G_RF5G2_SPARE_LSB) & RF5G_RF5G2_SPARE_MASK) + +#define RF2G_RF2G1_ADDRESS 0x00000028 +#define RF2G_RF2G1_OFFSET 0x00000028 +#define RF2G_RF2G1_BLNA1_MSB 31 +#define RF2G_RF2G1_BLNA1_LSB 29 +#define RF2G_RF2G1_BLNA1_MASK 0xe0000000 +#define RF2G_RF2G1_BLNA1_GET(x) (((x) & RF2G_RF2G1_BLNA1_MASK) >> RF2G_RF2G1_BLNA1_LSB) +#define RF2G_RF2G1_BLNA1_SET(x) (((x) << RF2G_RF2G1_BLNA1_LSB) & RF2G_RF2G1_BLNA1_MASK) +#define RF2G_RF2G1_BLNA1F_MSB 28 +#define RF2G_RF2G1_BLNA1F_LSB 26 +#define RF2G_RF2G1_BLNA1F_MASK 0x1c000000 +#define RF2G_RF2G1_BLNA1F_GET(x) (((x) & RF2G_RF2G1_BLNA1F_MASK) >> RF2G_RF2G1_BLNA1F_LSB) +#define RF2G_RF2G1_BLNA1F_SET(x) (((x) << RF2G_RF2G1_BLNA1F_LSB) & RF2G_RF2G1_BLNA1F_MASK) +#define RF2G_RF2G1_BLNA1BUF_MSB 25 +#define RF2G_RF2G1_BLNA1BUF_LSB 23 +#define RF2G_RF2G1_BLNA1BUF_MASK 0x03800000 +#define RF2G_RF2G1_BLNA1BUF_GET(x) (((x) & RF2G_RF2G1_BLNA1BUF_MASK) >> RF2G_RF2G1_BLNA1BUF_LSB) +#define RF2G_RF2G1_BLNA1BUF_SET(x) (((x) << RF2G_RF2G1_BLNA1BUF_LSB) & RF2G_RF2G1_BLNA1BUF_MASK) +#define RF2G_RF2G1_BLNA2_MSB 22 +#define RF2G_RF2G1_BLNA2_LSB 20 +#define RF2G_RF2G1_BLNA2_MASK 0x00700000 +#define RF2G_RF2G1_BLNA2_GET(x) (((x) & RF2G_RF2G1_BLNA2_MASK) >> RF2G_RF2G1_BLNA2_LSB) +#define RF2G_RF2G1_BLNA2_SET(x) (((x) << RF2G_RF2G1_BLNA2_LSB) & RF2G_RF2G1_BLNA2_MASK) +#define RF2G_RF2G1_DB_MSB 19 +#define RF2G_RF2G1_DB_LSB 17 +#define RF2G_RF2G1_DB_MASK 0x000e0000 +#define RF2G_RF2G1_DB_GET(x) (((x) & RF2G_RF2G1_DB_MASK) >> RF2G_RF2G1_DB_LSB) +#define RF2G_RF2G1_DB_SET(x) (((x) << RF2G_RF2G1_DB_LSB) & RF2G_RF2G1_DB_MASK) +#define RF2G_RF2G1_OB_MSB 16 +#define RF2G_RF2G1_OB_LSB 14 +#define RF2G_RF2G1_OB_MASK 0x0001c000 +#define RF2G_RF2G1_OB_GET(x) (((x) & RF2G_RF2G1_OB_MASK) >> RF2G_RF2G1_OB_LSB) +#define RF2G_RF2G1_OB_SET(x) (((x) << RF2G_RF2G1_OB_LSB) & RF2G_RF2G1_OB_MASK) +#define RF2G_RF2G1_FE_ATB_SEL_MSB 13 +#define RF2G_RF2G1_FE_ATB_SEL_LSB 11 +#define RF2G_RF2G1_FE_ATB_SEL_MASK 0x00003800 +#define RF2G_RF2G1_FE_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_FE_ATB_SEL_MASK) >> RF2G_RF2G1_FE_ATB_SEL_LSB) +#define RF2G_RF2G1_FE_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_FE_ATB_SEL_LSB) & RF2G_RF2G1_FE_ATB_SEL_MASK) +#define RF2G_RF2G1_RF_ATB_SEL_MSB 10 +#define RF2G_RF2G1_RF_ATB_SEL_LSB 8 +#define RF2G_RF2G1_RF_ATB_SEL_MASK 0x00000700 +#define RF2G_RF2G1_RF_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_RF_ATB_SEL_MASK) >> RF2G_RF2G1_RF_ATB_SEL_LSB) +#define RF2G_RF2G1_RF_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_RF_ATB_SEL_LSB) & RF2G_RF2G1_RF_ATB_SEL_MASK) +#define RF2G_RF2G1_SELLNA_MSB 7 +#define RF2G_RF2G1_SELLNA_LSB 7 +#define RF2G_RF2G1_SELLNA_MASK 0x00000080 +#define RF2G_RF2G1_SELLNA_GET(x) (((x) & RF2G_RF2G1_SELLNA_MASK) >> RF2G_RF2G1_SELLNA_LSB) +#define RF2G_RF2G1_SELLNA_SET(x) (((x) << RF2G_RF2G1_SELLNA_LSB) & RF2G_RF2G1_SELLNA_MASK) +#define RF2G_RF2G1_LOCONTROL_MSB 6 +#define RF2G_RF2G1_LOCONTROL_LSB 6 +#define RF2G_RF2G1_LOCONTROL_MASK 0x00000040 +#define RF2G_RF2G1_LOCONTROL_GET(x) (((x) & RF2G_RF2G1_LOCONTROL_MASK) >> RF2G_RF2G1_LOCONTROL_LSB) +#define RF2G_RF2G1_LOCONTROL_SET(x) (((x) << RF2G_RF2G1_LOCONTROL_LSB) & RF2G_RF2G1_LOCONTROL_MASK) +#define RF2G_RF2G1_SHORTLNA2_MSB 5 +#define RF2G_RF2G1_SHORTLNA2_LSB 5 +#define RF2G_RF2G1_SHORTLNA2_MASK 0x00000020 +#define RF2G_RF2G1_SHORTLNA2_GET(x) (((x) & RF2G_RF2G1_SHORTLNA2_MASK) >> RF2G_RF2G1_SHORTLNA2_LSB) +#define RF2G_RF2G1_SHORTLNA2_SET(x) (((x) << RF2G_RF2G1_SHORTLNA2_LSB) & RF2G_RF2G1_SHORTLNA2_MASK) +#define RF2G_RF2G1_SPARE_MSB 4 +#define RF2G_RF2G1_SPARE_LSB 0 +#define RF2G_RF2G1_SPARE_MASK 0x0000001f +#define RF2G_RF2G1_SPARE_GET(x) (((x) & RF2G_RF2G1_SPARE_MASK) >> RF2G_RF2G1_SPARE_LSB) +#define RF2G_RF2G1_SPARE_SET(x) (((x) << RF2G_RF2G1_SPARE_LSB) & RF2G_RF2G1_SPARE_MASK) + +#define RF2G_RF2G2_ADDRESS 0x0000002c +#define RF2G_RF2G2_OFFSET 0x0000002c +#define RF2G_RF2G2_PDCGLNA_MSB 31 +#define RF2G_RF2G2_PDCGLNA_LSB 31 +#define RF2G_RF2G2_PDCGLNA_MASK 0x80000000 +#define RF2G_RF2G2_PDCGLNA_GET(x) (((x) & RF2G_RF2G2_PDCGLNA_MASK) >> RF2G_RF2G2_PDCGLNA_LSB) +#define RF2G_RF2G2_PDCGLNA_SET(x) (((x) << RF2G_RF2G2_PDCGLNA_LSB) & RF2G_RF2G2_PDCGLNA_MASK) +#define RF2G_RF2G2_PDCGLNABUF_MSB 30 +#define RF2G_RF2G2_PDCGLNABUF_LSB 30 +#define RF2G_RF2G2_PDCGLNABUF_MASK 0x40000000 +#define RF2G_RF2G2_PDCGLNABUF_GET(x) (((x) & RF2G_RF2G2_PDCGLNABUF_MASK) >> RF2G_RF2G2_PDCGLNABUF_LSB) +#define RF2G_RF2G2_PDCGLNABUF_SET(x) (((x) << RF2G_RF2G2_PDCGLNABUF_LSB) & RF2G_RF2G2_PDCGLNABUF_MASK) +#define RF2G_RF2G2_PDCSLNA_MSB 29 +#define RF2G_RF2G2_PDCSLNA_LSB 29 +#define RF2G_RF2G2_PDCSLNA_MASK 0x20000000 +#define RF2G_RF2G2_PDCSLNA_GET(x) (((x) & RF2G_RF2G2_PDCSLNA_MASK) >> RF2G_RF2G2_PDCSLNA_LSB) +#define RF2G_RF2G2_PDCSLNA_SET(x) (((x) << RF2G_RF2G2_PDCSLNA_LSB) & RF2G_RF2G2_PDCSLNA_MASK) +#define RF2G_RF2G2_PDDIV_MSB 28 +#define RF2G_RF2G2_PDDIV_LSB 28 +#define RF2G_RF2G2_PDDIV_MASK 0x10000000 +#define RF2G_RF2G2_PDDIV_GET(x) (((x) & RF2G_RF2G2_PDDIV_MASK) >> RF2G_RF2G2_PDDIV_LSB) +#define RF2G_RF2G2_PDDIV_SET(x) (((x) << RF2G_RF2G2_PDDIV_LSB) & RF2G_RF2G2_PDDIV_MASK) +#define RF2G_RF2G2_PDPADRV_MSB 27 +#define RF2G_RF2G2_PDPADRV_LSB 27 +#define RF2G_RF2G2_PDPADRV_MASK 0x08000000 +#define RF2G_RF2G2_PDPADRV_GET(x) (((x) & RF2G_RF2G2_PDPADRV_MASK) >> RF2G_RF2G2_PDPADRV_LSB) +#define RF2G_RF2G2_PDPADRV_SET(x) (((x) << RF2G_RF2G2_PDPADRV_LSB) & RF2G_RF2G2_PDPADRV_MASK) +#define RF2G_RF2G2_PDPAOUT_MSB 26 +#define RF2G_RF2G2_PDPAOUT_LSB 26 +#define RF2G_RF2G2_PDPAOUT_MASK 0x04000000 +#define RF2G_RF2G2_PDPAOUT_GET(x) (((x) & RF2G_RF2G2_PDPAOUT_MASK) >> RF2G_RF2G2_PDPAOUT_LSB) +#define RF2G_RF2G2_PDPAOUT_SET(x) (((x) << RF2G_RF2G2_PDPAOUT_LSB) & RF2G_RF2G2_PDPAOUT_MASK) +#define RF2G_RF2G2_PDREGLNA_MSB 25 +#define RF2G_RF2G2_PDREGLNA_LSB 25 +#define RF2G_RF2G2_PDREGLNA_MASK 0x02000000 +#define RF2G_RF2G2_PDREGLNA_GET(x) (((x) & RF2G_RF2G2_PDREGLNA_MASK) >> RF2G_RF2G2_PDREGLNA_LSB) +#define RF2G_RF2G2_PDREGLNA_SET(x) (((x) << RF2G_RF2G2_PDREGLNA_LSB) & RF2G_RF2G2_PDREGLNA_MASK) +#define RF2G_RF2G2_PDREGLO_MSB 24 +#define RF2G_RF2G2_PDREGLO_LSB 24 +#define RF2G_RF2G2_PDREGLO_MASK 0x01000000 +#define RF2G_RF2G2_PDREGLO_GET(x) (((x) & RF2G_RF2G2_PDREGLO_MASK) >> RF2G_RF2G2_PDREGLO_LSB) +#define RF2G_RF2G2_PDREGLO_SET(x) (((x) << RF2G_RF2G2_PDREGLO_LSB) & RF2G_RF2G2_PDREGLO_MASK) +#define RF2G_RF2G2_PDRFGM_MSB 23 +#define RF2G_RF2G2_PDRFGM_LSB 23 +#define RF2G_RF2G2_PDRFGM_MASK 0x00800000 +#define RF2G_RF2G2_PDRFGM_GET(x) (((x) & RF2G_RF2G2_PDRFGM_MASK) >> RF2G_RF2G2_PDRFGM_LSB) +#define RF2G_RF2G2_PDRFGM_SET(x) (((x) << RF2G_RF2G2_PDRFGM_LSB) & RF2G_RF2G2_PDRFGM_MASK) +#define RF2G_RF2G2_PDRXLO_MSB 22 +#define RF2G_RF2G2_PDRXLO_LSB 22 +#define RF2G_RF2G2_PDRXLO_MASK 0x00400000 +#define RF2G_RF2G2_PDRXLO_GET(x) (((x) & RF2G_RF2G2_PDRXLO_MASK) >> RF2G_RF2G2_PDRXLO_LSB) +#define RF2G_RF2G2_PDRXLO_SET(x) (((x) << RF2G_RF2G2_PDRXLO_LSB) & RF2G_RF2G2_PDRXLO_MASK) +#define RF2G_RF2G2_PDTXLO_MSB 21 +#define RF2G_RF2G2_PDTXLO_LSB 21 +#define RF2G_RF2G2_PDTXLO_MASK 0x00200000 +#define RF2G_RF2G2_PDTXLO_GET(x) (((x) & RF2G_RF2G2_PDTXLO_MASK) >> RF2G_RF2G2_PDTXLO_LSB) +#define RF2G_RF2G2_PDTXLO_SET(x) (((x) << RF2G_RF2G2_PDTXLO_LSB) & RF2G_RF2G2_PDTXLO_MASK) +#define RF2G_RF2G2_PDTXMIX_MSB 20 +#define RF2G_RF2G2_PDTXMIX_LSB 20 +#define RF2G_RF2G2_PDTXMIX_MASK 0x00100000 +#define RF2G_RF2G2_PDTXMIX_GET(x) (((x) & RF2G_RF2G2_PDTXMIX_MASK) >> RF2G_RF2G2_PDTXMIX_LSB) +#define RF2G_RF2G2_PDTXMIX_SET(x) (((x) << RF2G_RF2G2_PDTXMIX_LSB) & RF2G_RF2G2_PDTXMIX_MASK) +#define RF2G_RF2G2_REGLNA_BYPASS_MSB 19 +#define RF2G_RF2G2_REGLNA_BYPASS_LSB 19 +#define RF2G_RF2G2_REGLNA_BYPASS_MASK 0x00080000 +#define RF2G_RF2G2_REGLNA_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLNA_BYPASS_MASK) >> RF2G_RF2G2_REGLNA_BYPASS_LSB) +#define RF2G_RF2G2_REGLNA_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLNA_BYPASS_LSB) & RF2G_RF2G2_REGLNA_BYPASS_MASK) +#define RF2G_RF2G2_REGLO_BYPASS_MSB 18 +#define RF2G_RF2G2_REGLO_BYPASS_LSB 18 +#define RF2G_RF2G2_REGLO_BYPASS_MASK 0x00040000 +#define RF2G_RF2G2_REGLO_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLO_BYPASS_MASK) >> RF2G_RF2G2_REGLO_BYPASS_LSB) +#define RF2G_RF2G2_REGLO_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLO_BYPASS_LSB) & RF2G_RF2G2_REGLO_BYPASS_MASK) +#define RF2G_RF2G2_ENABLE_PCB_MSB 17 +#define RF2G_RF2G2_ENABLE_PCB_LSB 17 +#define RF2G_RF2G2_ENABLE_PCB_MASK 0x00020000 +#define RF2G_RF2G2_ENABLE_PCB_GET(x) (((x) & RF2G_RF2G2_ENABLE_PCB_MASK) >> RF2G_RF2G2_ENABLE_PCB_LSB) +#define RF2G_RF2G2_ENABLE_PCB_SET(x) (((x) << RF2G_RF2G2_ENABLE_PCB_LSB) & RF2G_RF2G2_ENABLE_PCB_MASK) +#define RF2G_RF2G2_SPARE_MSB 16 +#define RF2G_RF2G2_SPARE_LSB 0 +#define RF2G_RF2G2_SPARE_MASK 0x0001ffff +#define RF2G_RF2G2_SPARE_GET(x) (((x) & RF2G_RF2G2_SPARE_MASK) >> RF2G_RF2G2_SPARE_LSB) +#define RF2G_RF2G2_SPARE_SET(x) (((x) << RF2G_RF2G2_SPARE_LSB) & RF2G_RF2G2_SPARE_MASK) + +#define TOP_GAIN_ADDRESS 0x00000030 +#define TOP_GAIN_OFFSET 0x00000030 +#define TOP_GAIN_TX6DBLOQGAIN_MSB 31 +#define TOP_GAIN_TX6DBLOQGAIN_LSB 30 +#define TOP_GAIN_TX6DBLOQGAIN_MASK 0xc0000000 +#define TOP_GAIN_TX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX6DBLOQGAIN_MASK) >> TOP_GAIN_TX6DBLOQGAIN_LSB) +#define TOP_GAIN_TX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX6DBLOQGAIN_LSB) & TOP_GAIN_TX6DBLOQGAIN_MASK) +#define TOP_GAIN_TX1DBLOQGAIN_MSB 29 +#define TOP_GAIN_TX1DBLOQGAIN_LSB 27 +#define TOP_GAIN_TX1DBLOQGAIN_MASK 0x38000000 +#define TOP_GAIN_TX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX1DBLOQGAIN_MASK) >> TOP_GAIN_TX1DBLOQGAIN_LSB) +#define TOP_GAIN_TX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX1DBLOQGAIN_LSB) & TOP_GAIN_TX1DBLOQGAIN_MASK) +#define TOP_GAIN_TXV2IGAIN_MSB 26 +#define TOP_GAIN_TXV2IGAIN_LSB 25 +#define TOP_GAIN_TXV2IGAIN_MASK 0x06000000 +#define TOP_GAIN_TXV2IGAIN_GET(x) (((x) & TOP_GAIN_TXV2IGAIN_MASK) >> TOP_GAIN_TXV2IGAIN_LSB) +#define TOP_GAIN_TXV2IGAIN_SET(x) (((x) << TOP_GAIN_TXV2IGAIN_LSB) & TOP_GAIN_TXV2IGAIN_MASK) +#define TOP_GAIN_PABUF5GN_MSB 24 +#define TOP_GAIN_PABUF5GN_LSB 24 +#define TOP_GAIN_PABUF5GN_MASK 0x01000000 +#define TOP_GAIN_PABUF5GN_GET(x) (((x) & TOP_GAIN_PABUF5GN_MASK) >> TOP_GAIN_PABUF5GN_LSB) +#define TOP_GAIN_PABUF5GN_SET(x) (((x) << TOP_GAIN_PABUF5GN_LSB) & TOP_GAIN_PABUF5GN_MASK) +#define TOP_GAIN_PADRVGN_MSB 23 +#define TOP_GAIN_PADRVGN_LSB 21 +#define TOP_GAIN_PADRVGN_MASK 0x00e00000 +#define TOP_GAIN_PADRVGN_GET(x) (((x) & TOP_GAIN_PADRVGN_MASK) >> TOP_GAIN_PADRVGN_LSB) +#define TOP_GAIN_PADRVGN_SET(x) (((x) << TOP_GAIN_PADRVGN_LSB) & TOP_GAIN_PADRVGN_MASK) +#define TOP_GAIN_PAOUT2GN_MSB 20 +#define TOP_GAIN_PAOUT2GN_LSB 18 +#define TOP_GAIN_PAOUT2GN_MASK 0x001c0000 +#define TOP_GAIN_PAOUT2GN_GET(x) (((x) & TOP_GAIN_PAOUT2GN_MASK) >> TOP_GAIN_PAOUT2GN_LSB) +#define TOP_GAIN_PAOUT2GN_SET(x) (((x) << TOP_GAIN_PAOUT2GN_LSB) & TOP_GAIN_PAOUT2GN_MASK) +#define TOP_GAIN_LNAON_MSB 17 +#define TOP_GAIN_LNAON_LSB 17 +#define TOP_GAIN_LNAON_MASK 0x00020000 +#define TOP_GAIN_LNAON_GET(x) (((x) & TOP_GAIN_LNAON_MASK) >> TOP_GAIN_LNAON_LSB) +#define TOP_GAIN_LNAON_SET(x) (((x) << TOP_GAIN_LNAON_LSB) & TOP_GAIN_LNAON_MASK) +#define TOP_GAIN_LNAGAIN_MSB 16 +#define TOP_GAIN_LNAGAIN_LSB 13 +#define TOP_GAIN_LNAGAIN_MASK 0x0001e000 +#define TOP_GAIN_LNAGAIN_GET(x) (((x) & TOP_GAIN_LNAGAIN_MASK) >> TOP_GAIN_LNAGAIN_LSB) +#define TOP_GAIN_LNAGAIN_SET(x) (((x) << TOP_GAIN_LNAGAIN_LSB) & TOP_GAIN_LNAGAIN_MASK) +#define TOP_GAIN_RFVGA5GAIN_MSB 12 +#define TOP_GAIN_RFVGA5GAIN_LSB 11 +#define TOP_GAIN_RFVGA5GAIN_MASK 0x00001800 +#define TOP_GAIN_RFVGA5GAIN_GET(x) (((x) & TOP_GAIN_RFVGA5GAIN_MASK) >> TOP_GAIN_RFVGA5GAIN_LSB) +#define TOP_GAIN_RFVGA5GAIN_SET(x) (((x) << TOP_GAIN_RFVGA5GAIN_LSB) & TOP_GAIN_RFVGA5GAIN_MASK) +#define TOP_GAIN_RFGMGN_MSB 10 +#define TOP_GAIN_RFGMGN_LSB 8 +#define TOP_GAIN_RFGMGN_MASK 0x00000700 +#define TOP_GAIN_RFGMGN_GET(x) (((x) & TOP_GAIN_RFGMGN_MASK) >> TOP_GAIN_RFGMGN_LSB) +#define TOP_GAIN_RFGMGN_SET(x) (((x) << TOP_GAIN_RFGMGN_LSB) & TOP_GAIN_RFGMGN_MASK) +#define TOP_GAIN_RX6DBLOQGAIN_MSB 7 +#define TOP_GAIN_RX6DBLOQGAIN_LSB 6 +#define TOP_GAIN_RX6DBLOQGAIN_MASK 0x000000c0 +#define TOP_GAIN_RX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBLOQGAIN_MASK) >> TOP_GAIN_RX6DBLOQGAIN_LSB) +#define TOP_GAIN_RX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBLOQGAIN_LSB) & TOP_GAIN_RX6DBLOQGAIN_MASK) +#define TOP_GAIN_RX1DBLOQGAIN_MSB 5 +#define TOP_GAIN_RX1DBLOQGAIN_LSB 3 +#define TOP_GAIN_RX1DBLOQGAIN_MASK 0x00000038 +#define TOP_GAIN_RX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX1DBLOQGAIN_MASK) >> TOP_GAIN_RX1DBLOQGAIN_LSB) +#define TOP_GAIN_RX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX1DBLOQGAIN_LSB) & TOP_GAIN_RX1DBLOQGAIN_MASK) +#define TOP_GAIN_RX6DBHIQGAIN_MSB 2 +#define TOP_GAIN_RX6DBHIQGAIN_LSB 1 +#define TOP_GAIN_RX6DBHIQGAIN_MASK 0x00000006 +#define TOP_GAIN_RX6DBHIQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBHIQGAIN_MASK) >> TOP_GAIN_RX6DBHIQGAIN_LSB) +#define TOP_GAIN_RX6DBHIQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBHIQGAIN_LSB) & TOP_GAIN_RX6DBHIQGAIN_MASK) +#define TOP_GAIN_SPARE_MSB 0 +#define TOP_GAIN_SPARE_LSB 0 +#define TOP_GAIN_SPARE_MASK 0x00000001 +#define TOP_GAIN_SPARE_GET(x) (((x) & TOP_GAIN_SPARE_MASK) >> TOP_GAIN_SPARE_LSB) +#define TOP_GAIN_SPARE_SET(x) (((x) << TOP_GAIN_SPARE_LSB) & TOP_GAIN_SPARE_MASK) + +#define TOP_TOP_ADDRESS 0x00000034 +#define TOP_TOP_OFFSET 0x00000034 +#define TOP_TOP_LOCALTXGAIN_MSB 31 +#define TOP_TOP_LOCALTXGAIN_LSB 31 +#define TOP_TOP_LOCALTXGAIN_MASK 0x80000000 +#define TOP_TOP_LOCALTXGAIN_GET(x) (((x) & TOP_TOP_LOCALTXGAIN_MASK) >> TOP_TOP_LOCALTXGAIN_LSB) +#define TOP_TOP_LOCALTXGAIN_SET(x) (((x) << TOP_TOP_LOCALTXGAIN_LSB) & TOP_TOP_LOCALTXGAIN_MASK) +#define TOP_TOP_LOCALRXGAIN_MSB 30 +#define TOP_TOP_LOCALRXGAIN_LSB 30 +#define TOP_TOP_LOCALRXGAIN_MASK 0x40000000 +#define TOP_TOP_LOCALRXGAIN_GET(x) (((x) & TOP_TOP_LOCALRXGAIN_MASK) >> TOP_TOP_LOCALRXGAIN_LSB) +#define TOP_TOP_LOCALRXGAIN_SET(x) (((x) << TOP_TOP_LOCALRXGAIN_LSB) & TOP_TOP_LOCALRXGAIN_MASK) +#define TOP_TOP_LOCALMODE_MSB 29 +#define TOP_TOP_LOCALMODE_LSB 29 +#define TOP_TOP_LOCALMODE_MASK 0x20000000 +#define TOP_TOP_LOCALMODE_GET(x) (((x) & TOP_TOP_LOCALMODE_MASK) >> TOP_TOP_LOCALMODE_LSB) +#define TOP_TOP_LOCALMODE_SET(x) (((x) << TOP_TOP_LOCALMODE_LSB) & TOP_TOP_LOCALMODE_MASK) +#define TOP_TOP_CALFC_MSB 28 +#define TOP_TOP_CALFC_LSB 28 +#define TOP_TOP_CALFC_MASK 0x10000000 +#define TOP_TOP_CALFC_GET(x) (((x) & TOP_TOP_CALFC_MASK) >> TOP_TOP_CALFC_LSB) +#define TOP_TOP_CALFC_SET(x) (((x) << TOP_TOP_CALFC_LSB) & TOP_TOP_CALFC_MASK) +#define TOP_TOP_CALDC_MSB 27 +#define TOP_TOP_CALDC_LSB 27 +#define TOP_TOP_CALDC_MASK 0x08000000 +#define TOP_TOP_CALDC_GET(x) (((x) & TOP_TOP_CALDC_MASK) >> TOP_TOP_CALDC_LSB) +#define TOP_TOP_CALDC_SET(x) (((x) << TOP_TOP_CALDC_LSB) & TOP_TOP_CALDC_MASK) +#define TOP_TOP_CAL_RESIDUE_MSB 26 +#define TOP_TOP_CAL_RESIDUE_LSB 26 +#define TOP_TOP_CAL_RESIDUE_MASK 0x04000000 +#define TOP_TOP_CAL_RESIDUE_GET(x) (((x) & TOP_TOP_CAL_RESIDUE_MASK) >> TOP_TOP_CAL_RESIDUE_LSB) +#define TOP_TOP_CAL_RESIDUE_SET(x) (((x) << TOP_TOP_CAL_RESIDUE_LSB) & TOP_TOP_CAL_RESIDUE_MASK) +#define TOP_TOP_BMODE_MSB 25 +#define TOP_TOP_BMODE_LSB 25 +#define TOP_TOP_BMODE_MASK 0x02000000 +#define TOP_TOP_BMODE_GET(x) (((x) & TOP_TOP_BMODE_MASK) >> TOP_TOP_BMODE_LSB) +#define TOP_TOP_BMODE_SET(x) (((x) << TOP_TOP_BMODE_LSB) & TOP_TOP_BMODE_MASK) +#define TOP_TOP_SYNTHON_MSB 24 +#define TOP_TOP_SYNTHON_LSB 24 +#define TOP_TOP_SYNTHON_MASK 0x01000000 +#define TOP_TOP_SYNTHON_GET(x) (((x) & TOP_TOP_SYNTHON_MASK) >> TOP_TOP_SYNTHON_LSB) +#define TOP_TOP_SYNTHON_SET(x) (((x) << TOP_TOP_SYNTHON_LSB) & TOP_TOP_SYNTHON_MASK) +#define TOP_TOP_RXON_MSB 23 +#define TOP_TOP_RXON_LSB 23 +#define TOP_TOP_RXON_MASK 0x00800000 +#define TOP_TOP_RXON_GET(x) (((x) & TOP_TOP_RXON_MASK) >> TOP_TOP_RXON_LSB) +#define TOP_TOP_RXON_SET(x) (((x) << TOP_TOP_RXON_LSB) & TOP_TOP_RXON_MASK) +#define TOP_TOP_TXON_MSB 22 +#define TOP_TOP_TXON_LSB 22 +#define TOP_TOP_TXON_MASK 0x00400000 +#define TOP_TOP_TXON_GET(x) (((x) & TOP_TOP_TXON_MASK) >> TOP_TOP_TXON_LSB) +#define TOP_TOP_TXON_SET(x) (((x) << TOP_TOP_TXON_LSB) & TOP_TOP_TXON_MASK) +#define TOP_TOP_PAON_MSB 21 +#define TOP_TOP_PAON_LSB 21 +#define TOP_TOP_PAON_MASK 0x00200000 +#define TOP_TOP_PAON_GET(x) (((x) & TOP_TOP_PAON_MASK) >> TOP_TOP_PAON_LSB) +#define TOP_TOP_PAON_SET(x) (((x) << TOP_TOP_PAON_LSB) & TOP_TOP_PAON_MASK) +#define TOP_TOP_CALTX_MSB 20 +#define TOP_TOP_CALTX_LSB 20 +#define TOP_TOP_CALTX_MASK 0x00100000 +#define TOP_TOP_CALTX_GET(x) (((x) & TOP_TOP_CALTX_MASK) >> TOP_TOP_CALTX_LSB) +#define TOP_TOP_CALTX_SET(x) (((x) << TOP_TOP_CALTX_LSB) & TOP_TOP_CALTX_MASK) +#define TOP_TOP_LOCALADDAC_MSB 19 +#define TOP_TOP_LOCALADDAC_LSB 19 +#define TOP_TOP_LOCALADDAC_MASK 0x00080000 +#define TOP_TOP_LOCALADDAC_GET(x) (((x) & TOP_TOP_LOCALADDAC_MASK) >> TOP_TOP_LOCALADDAC_LSB) +#define TOP_TOP_LOCALADDAC_SET(x) (((x) << TOP_TOP_LOCALADDAC_LSB) & TOP_TOP_LOCALADDAC_MASK) +#define TOP_TOP_PWDPLL_MSB 18 +#define TOP_TOP_PWDPLL_LSB 18 +#define TOP_TOP_PWDPLL_MASK 0x00040000 +#define TOP_TOP_PWDPLL_GET(x) (((x) & TOP_TOP_PWDPLL_MASK) >> TOP_TOP_PWDPLL_LSB) +#define TOP_TOP_PWDPLL_SET(x) (((x) << TOP_TOP_PWDPLL_LSB) & TOP_TOP_PWDPLL_MASK) +#define TOP_TOP_PWDADC_MSB 17 +#define TOP_TOP_PWDADC_LSB 17 +#define TOP_TOP_PWDADC_MASK 0x00020000 +#define TOP_TOP_PWDADC_GET(x) (((x) & TOP_TOP_PWDADC_MASK) >> TOP_TOP_PWDADC_LSB) +#define TOP_TOP_PWDADC_SET(x) (((x) << TOP_TOP_PWDADC_LSB) & TOP_TOP_PWDADC_MASK) +#define TOP_TOP_PWDDAC_MSB 16 +#define TOP_TOP_PWDDAC_LSB 16 +#define TOP_TOP_PWDDAC_MASK 0x00010000 +#define TOP_TOP_PWDDAC_GET(x) (((x) & TOP_TOP_PWDDAC_MASK) >> TOP_TOP_PWDDAC_LSB) +#define TOP_TOP_PWDDAC_SET(x) (((x) << TOP_TOP_PWDDAC_LSB) & TOP_TOP_PWDDAC_MASK) +#define TOP_TOP_LOCALXTAL_MSB 15 +#define TOP_TOP_LOCALXTAL_LSB 15 +#define TOP_TOP_LOCALXTAL_MASK 0x00008000 +#define TOP_TOP_LOCALXTAL_GET(x) (((x) & TOP_TOP_LOCALXTAL_MASK) >> TOP_TOP_LOCALXTAL_LSB) +#define TOP_TOP_LOCALXTAL_SET(x) (((x) << TOP_TOP_LOCALXTAL_LSB) & TOP_TOP_LOCALXTAL_MASK) +#define TOP_TOP_PWDCLKIN_MSB 14 +#define TOP_TOP_PWDCLKIN_LSB 14 +#define TOP_TOP_PWDCLKIN_MASK 0x00004000 +#define TOP_TOP_PWDCLKIN_GET(x) (((x) & TOP_TOP_PWDCLKIN_MASK) >> TOP_TOP_PWDCLKIN_LSB) +#define TOP_TOP_PWDCLKIN_SET(x) (((x) << TOP_TOP_PWDCLKIN_LSB) & TOP_TOP_PWDCLKIN_MASK) +#define TOP_TOP_OSCON_MSB 13 +#define TOP_TOP_OSCON_LSB 13 +#define TOP_TOP_OSCON_MASK 0x00002000 +#define TOP_TOP_OSCON_GET(x) (((x) & TOP_TOP_OSCON_MASK) >> TOP_TOP_OSCON_LSB) +#define TOP_TOP_OSCON_SET(x) (((x) << TOP_TOP_OSCON_LSB) & TOP_TOP_OSCON_MASK) +#define TOP_TOP_SCLKEN_FORCE_MSB 12 +#define TOP_TOP_SCLKEN_FORCE_LSB 12 +#define TOP_TOP_SCLKEN_FORCE_MASK 0x00001000 +#define TOP_TOP_SCLKEN_FORCE_GET(x) (((x) & TOP_TOP_SCLKEN_FORCE_MASK) >> TOP_TOP_SCLKEN_FORCE_LSB) +#define TOP_TOP_SCLKEN_FORCE_SET(x) (((x) << TOP_TOP_SCLKEN_FORCE_LSB) & TOP_TOP_SCLKEN_FORCE_MASK) +#define TOP_TOP_SYNTHON_FORCE_MSB 11 +#define TOP_TOP_SYNTHON_FORCE_LSB 11 +#define TOP_TOP_SYNTHON_FORCE_MASK 0x00000800 +#define TOP_TOP_SYNTHON_FORCE_GET(x) (((x) & TOP_TOP_SYNTHON_FORCE_MASK) >> TOP_TOP_SYNTHON_FORCE_LSB) +#define TOP_TOP_SYNTHON_FORCE_SET(x) (((x) << TOP_TOP_SYNTHON_FORCE_LSB) & TOP_TOP_SYNTHON_FORCE_MASK) +#define TOP_TOP_PDBIAS_MSB 10 +#define TOP_TOP_PDBIAS_LSB 10 +#define TOP_TOP_PDBIAS_MASK 0x00000400 +#define TOP_TOP_PDBIAS_GET(x) (((x) & TOP_TOP_PDBIAS_MASK) >> TOP_TOP_PDBIAS_LSB) +#define TOP_TOP_PDBIAS_SET(x) (((x) << TOP_TOP_PDBIAS_LSB) & TOP_TOP_PDBIAS_MASK) +#define TOP_TOP_DATAOUTSEL_MSB 9 +#define TOP_TOP_DATAOUTSEL_LSB 8 +#define TOP_TOP_DATAOUTSEL_MASK 0x00000300 +#define TOP_TOP_DATAOUTSEL_GET(x) (((x) & TOP_TOP_DATAOUTSEL_MASK) >> TOP_TOP_DATAOUTSEL_LSB) +#define TOP_TOP_DATAOUTSEL_SET(x) (((x) << TOP_TOP_DATAOUTSEL_LSB) & TOP_TOP_DATAOUTSEL_MASK) +#define TOP_TOP_REVID_MSB 7 +#define TOP_TOP_REVID_LSB 5 +#define TOP_TOP_REVID_MASK 0x000000e0 +#define TOP_TOP_REVID_GET(x) (((x) & TOP_TOP_REVID_MASK) >> TOP_TOP_REVID_LSB) +#define TOP_TOP_REVID_SET(x) (((x) << TOP_TOP_REVID_LSB) & TOP_TOP_REVID_MASK) +#define TOP_TOP_INT2PAD_MSB 4 +#define TOP_TOP_INT2PAD_LSB 4 +#define TOP_TOP_INT2PAD_MASK 0x00000010 +#define TOP_TOP_INT2PAD_GET(x) (((x) & TOP_TOP_INT2PAD_MASK) >> TOP_TOP_INT2PAD_LSB) +#define TOP_TOP_INT2PAD_SET(x) (((x) << TOP_TOP_INT2PAD_LSB) & TOP_TOP_INT2PAD_MASK) +#define TOP_TOP_INTH2PAD_MSB 3 +#define TOP_TOP_INTH2PAD_LSB 3 +#define TOP_TOP_INTH2PAD_MASK 0x00000008 +#define TOP_TOP_INTH2PAD_GET(x) (((x) & TOP_TOP_INTH2PAD_MASK) >> TOP_TOP_INTH2PAD_LSB) +#define TOP_TOP_INTH2PAD_SET(x) (((x) << TOP_TOP_INTH2PAD_LSB) & TOP_TOP_INTH2PAD_MASK) +#define TOP_TOP_PAD2GND_MSB 2 +#define TOP_TOP_PAD2GND_LSB 2 +#define TOP_TOP_PAD2GND_MASK 0x00000004 +#define TOP_TOP_PAD2GND_GET(x) (((x) & TOP_TOP_PAD2GND_MASK) >> TOP_TOP_PAD2GND_LSB) +#define TOP_TOP_PAD2GND_SET(x) (((x) << TOP_TOP_PAD2GND_LSB) & TOP_TOP_PAD2GND_MASK) +#define TOP_TOP_INT2GND_MSB 1 +#define TOP_TOP_INT2GND_LSB 1 +#define TOP_TOP_INT2GND_MASK 0x00000002 +#define TOP_TOP_INT2GND_GET(x) (((x) & TOP_TOP_INT2GND_MASK) >> TOP_TOP_INT2GND_LSB) +#define TOP_TOP_INT2GND_SET(x) (((x) << TOP_TOP_INT2GND_LSB) & TOP_TOP_INT2GND_MASK) +#define TOP_TOP_FORCE_XPAON_MSB 0 +#define TOP_TOP_FORCE_XPAON_LSB 0 +#define TOP_TOP_FORCE_XPAON_MASK 0x00000001 +#define TOP_TOP_FORCE_XPAON_GET(x) (((x) & TOP_TOP_FORCE_XPAON_MASK) >> TOP_TOP_FORCE_XPAON_LSB) +#define TOP_TOP_FORCE_XPAON_SET(x) (((x) << TOP_TOP_FORCE_XPAON_LSB) & TOP_TOP_FORCE_XPAON_MASK) + +#define BIAS_BIAS_SEL_ADDRESS 0x00000038 +#define BIAS_BIAS_SEL_OFFSET 0x00000038 +#define BIAS_BIAS_SEL_PADON_MSB 31 +#define BIAS_BIAS_SEL_PADON_LSB 31 +#define BIAS_BIAS_SEL_PADON_MASK 0x80000000 +#define BIAS_BIAS_SEL_PADON_GET(x) (((x) & BIAS_BIAS_SEL_PADON_MASK) >> BIAS_BIAS_SEL_PADON_LSB) +#define BIAS_BIAS_SEL_PADON_SET(x) (((x) << BIAS_BIAS_SEL_PADON_LSB) & BIAS_BIAS_SEL_PADON_MASK) +#define BIAS_BIAS_SEL_SEL_BIAS_MSB 30 +#define BIAS_BIAS_SEL_SEL_BIAS_LSB 25 +#define BIAS_BIAS_SEL_SEL_BIAS_MASK 0x7e000000 +#define BIAS_BIAS_SEL_SEL_BIAS_GET(x) (((x) & BIAS_BIAS_SEL_SEL_BIAS_MASK) >> BIAS_BIAS_SEL_SEL_BIAS_LSB) +#define BIAS_BIAS_SEL_SEL_BIAS_SET(x) (((x) << BIAS_BIAS_SEL_SEL_BIAS_LSB) & BIAS_BIAS_SEL_SEL_BIAS_MASK) +#define BIAS_BIAS_SEL_SEL_SPARE_MSB 24 +#define BIAS_BIAS_SEL_SEL_SPARE_LSB 21 +#define BIAS_BIAS_SEL_SEL_SPARE_MASK 0x01e00000 +#define BIAS_BIAS_SEL_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SEL_SPARE_LSB) +#define BIAS_BIAS_SEL_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SEL_SPARE_MASK) +#define BIAS_BIAS_SEL_SPARE_MSB 20 +#define BIAS_BIAS_SEL_SPARE_LSB 20 +#define BIAS_BIAS_SEL_SPARE_MASK 0x00100000 +#define BIAS_BIAS_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SPARE_LSB) +#define BIAS_BIAS_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SPARE_MASK) +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MSB 19 +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB 17 +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK 0x000e0000 +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB) +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK) +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MSB 16 +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB 16 +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK 0x00010000 +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB) +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK) +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MSB 15 +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB 15 +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK 0x00008000 +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB) +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK) +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MSB 14 +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB 14 +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK 0x00004000 +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB) +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK) +#define BIAS_BIAS_SEL_PWD_ICCPLL25_MSB 13 +#define BIAS_BIAS_SEL_PWD_ICCPLL25_LSB 13 +#define BIAS_BIAS_SEL_PWD_ICCPLL25_MASK 0x00002000 +#define BIAS_BIAS_SEL_PWD_ICCPLL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK) >> BIAS_BIAS_SEL_PWD_ICCPLL25_LSB) +#define BIAS_BIAS_SEL_PWD_ICCPLL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCPLL25_LSB) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK) +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MSB 12 +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB 10 +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK 0x00001c00 +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB) +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK) +#define BIAS_BIAS_SEL_PWD_ICXTAL25_MSB 9 +#define BIAS_BIAS_SEL_PWD_ICXTAL25_LSB 7 +#define BIAS_BIAS_SEL_PWD_ICXTAL25_MASK 0x00000380 +#define BIAS_BIAS_SEL_PWD_ICXTAL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK) >> BIAS_BIAS_SEL_PWD_ICXTAL25_LSB) +#define BIAS_BIAS_SEL_PWD_ICXTAL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICXTAL25_LSB) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK) +#define BIAS_BIAS_SEL_PWD_ICTSENS25_MSB 6 +#define BIAS_BIAS_SEL_PWD_ICTSENS25_LSB 4 +#define BIAS_BIAS_SEL_PWD_ICTSENS25_MASK 0x00000070 +#define BIAS_BIAS_SEL_PWD_ICTSENS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK) >> BIAS_BIAS_SEL_PWD_ICTSENS25_LSB) +#define BIAS_BIAS_SEL_PWD_ICTSENS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTSENS25_LSB) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK) +#define BIAS_BIAS_SEL_PWD_ICTXPC25_MSB 3 +#define BIAS_BIAS_SEL_PWD_ICTXPC25_LSB 1 +#define BIAS_BIAS_SEL_PWD_ICTXPC25_MASK 0x0000000e +#define BIAS_BIAS_SEL_PWD_ICTXPC25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK) >> BIAS_BIAS_SEL_PWD_ICTXPC25_LSB) +#define BIAS_BIAS_SEL_PWD_ICTXPC25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTXPC25_LSB) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK) +#define BIAS_BIAS_SEL_PWD_ICLDO25_MSB 0 +#define BIAS_BIAS_SEL_PWD_ICLDO25_LSB 0 +#define BIAS_BIAS_SEL_PWD_ICLDO25_MASK 0x00000001 +#define BIAS_BIAS_SEL_PWD_ICLDO25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK) >> BIAS_BIAS_SEL_PWD_ICLDO25_LSB) +#define BIAS_BIAS_SEL_PWD_ICLDO25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICLDO25_LSB) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK) + +#define BIAS_BIAS1_ADDRESS 0x0000003c +#define BIAS_BIAS1_OFFSET 0x0000003c +#define BIAS_BIAS1_PWD_ICDAC2BB25_MSB 31 +#define BIAS_BIAS1_PWD_ICDAC2BB25_LSB 29 +#define BIAS_BIAS1_PWD_ICDAC2BB25_MASK 0xe0000000 +#define BIAS_BIAS1_PWD_ICDAC2BB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK) >> BIAS_BIAS1_PWD_ICDAC2BB25_LSB) +#define BIAS_BIAS1_PWD_ICDAC2BB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDAC2BB25_LSB) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK) +#define BIAS_BIAS1_PWD_IC2GVGM25_MSB 28 +#define BIAS_BIAS1_PWD_IC2GVGM25_LSB 26 +#define BIAS_BIAS1_PWD_IC2GVGM25_MASK 0x1c000000 +#define BIAS_BIAS1_PWD_IC2GVGM25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GVGM25_MASK) >> BIAS_BIAS1_PWD_IC2GVGM25_LSB) +#define BIAS_BIAS1_PWD_IC2GVGM25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GVGM25_LSB) & BIAS_BIAS1_PWD_IC2GVGM25_MASK) +#define BIAS_BIAS1_PWD_IC2GRFFE25_MSB 25 +#define BIAS_BIAS1_PWD_IC2GRFFE25_LSB 23 +#define BIAS_BIAS1_PWD_IC2GRFFE25_MASK 0x03800000 +#define BIAS_BIAS1_PWD_IC2GRFFE25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK) >> BIAS_BIAS1_PWD_IC2GRFFE25_LSB) +#define BIAS_BIAS1_PWD_IC2GRFFE25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GRFFE25_LSB) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK) +#define BIAS_BIAS1_PWD_IC2GLOREG25_MSB 22 +#define BIAS_BIAS1_PWD_IC2GLOREG25_LSB 20 +#define BIAS_BIAS1_PWD_IC2GLOREG25_MASK 0x00700000 +#define BIAS_BIAS1_PWD_IC2GLOREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLOREG25_LSB) +#define BIAS_BIAS1_PWD_IC2GLOREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLOREG25_LSB) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK) +#define BIAS_BIAS1_PWD_IC2GLNAREG25_MSB 19 +#define BIAS_BIAS1_PWD_IC2GLNAREG25_LSB 17 +#define BIAS_BIAS1_PWD_IC2GLNAREG25_MASK 0x000e0000 +#define BIAS_BIAS1_PWD_IC2GLNAREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLNAREG25_LSB) +#define BIAS_BIAS1_PWD_IC2GLNAREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLNAREG25_LSB) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK) +#define BIAS_BIAS1_PWD_ICDETECTORB25_MSB 16 +#define BIAS_BIAS1_PWD_ICDETECTORB25_LSB 16 +#define BIAS_BIAS1_PWD_ICDETECTORB25_MASK 0x00010000 +#define BIAS_BIAS1_PWD_ICDETECTORB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORB25_LSB) +#define BIAS_BIAS1_PWD_ICDETECTORB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETECTORB25_LSB) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK) +#define BIAS_BIAS1_PWD_ICDETECTORA25_MSB 15 +#define BIAS_BIAS1_PWD_ICDETECTORA25_LSB 15 +#define BIAS_BIAS1_PWD_ICDETECTORA25_MASK 0x00008000 +#define BIAS_BIAS1_PWD_ICDETECTORA25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORA25_LSB) +#define BIAS_BIAS1_PWD_ICDETECTORA25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETECTORA25_LSB) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK) +#define BIAS_BIAS1_PWD_IC5GRXRF25_MSB 14 +#define BIAS_BIAS1_PWD_IC5GRXRF25_LSB 14 +#define BIAS_BIAS1_PWD_IC5GRXRF25_MASK 0x00004000 +#define BIAS_BIAS1_PWD_IC5GRXRF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK) >> BIAS_BIAS1_PWD_IC5GRXRF25_LSB) +#define BIAS_BIAS1_PWD_IC5GRXRF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GRXRF25_LSB) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK) +#define BIAS_BIAS1_PWD_IC5GTXPA25_MSB 13 +#define BIAS_BIAS1_PWD_IC5GTXPA25_LSB 11 +#define BIAS_BIAS1_PWD_IC5GTXPA25_MASK 0x00003800 +#define BIAS_BIAS1_PWD_IC5GTXPA25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK) >> BIAS_BIAS1_PWD_IC5GTXPA25_LSB) +#define BIAS_BIAS1_PWD_IC5GTXPA25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXPA25_LSB) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK) +#define BIAS_BIAS1_PWD_IC5GTXBUF25_MSB 10 +#define BIAS_BIAS1_PWD_IC5GTXBUF25_LSB 8 +#define BIAS_BIAS1_PWD_IC5GTXBUF25_MASK 0x00000700 +#define BIAS_BIAS1_PWD_IC5GTXBUF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK) >> BIAS_BIAS1_PWD_IC5GTXBUF25_LSB) +#define BIAS_BIAS1_PWD_IC5GTXBUF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXBUF25_LSB) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK) +#define BIAS_BIAS1_PWD_IC5GQB25_MSB 7 +#define BIAS_BIAS1_PWD_IC5GQB25_LSB 5 +#define BIAS_BIAS1_PWD_IC5GQB25_MASK 0x000000e0 +#define BIAS_BIAS1_PWD_IC5GQB25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GQB25_MASK) >> BIAS_BIAS1_PWD_IC5GQB25_LSB) +#define BIAS_BIAS1_PWD_IC5GQB25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GQB25_LSB) & BIAS_BIAS1_PWD_IC5GQB25_MASK) +#define BIAS_BIAS1_PWD_IC5GMIXQ25_MSB 4 +#define BIAS_BIAS1_PWD_IC5GMIXQ25_LSB 2 +#define BIAS_BIAS1_PWD_IC5GMIXQ25_MASK 0x0000001c +#define BIAS_BIAS1_PWD_IC5GMIXQ25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK) >> BIAS_BIAS1_PWD_IC5GMIXQ25_LSB) +#define BIAS_BIAS1_PWD_IC5GMIXQ25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GMIXQ25_LSB) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK) +#define BIAS_BIAS1_SPARE_MSB 1 +#define BIAS_BIAS1_SPARE_LSB 0 +#define BIAS_BIAS1_SPARE_MASK 0x00000003 +#define BIAS_BIAS1_SPARE_GET(x) (((x) & BIAS_BIAS1_SPARE_MASK) >> BIAS_BIAS1_SPARE_LSB) +#define BIAS_BIAS1_SPARE_SET(x) (((x) << BIAS_BIAS1_SPARE_LSB) & BIAS_BIAS1_SPARE_MASK) + +#define BIAS_BIAS2_ADDRESS 0x00000040 +#define BIAS_BIAS2_OFFSET 0x00000040 +#define BIAS_BIAS2_PWD_IC5GMIXI25_MSB 31 +#define BIAS_BIAS2_PWD_IC5GMIXI25_LSB 29 +#define BIAS_BIAS2_PWD_IC5GMIXI25_MASK 0xe0000000 +#define BIAS_BIAS2_PWD_IC5GMIXI25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK) >> BIAS_BIAS2_PWD_IC5GMIXI25_LSB) +#define BIAS_BIAS2_PWD_IC5GMIXI25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GMIXI25_LSB) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK) +#define BIAS_BIAS2_PWD_IC5GDIV25_MSB 28 +#define BIAS_BIAS2_PWD_IC5GDIV25_LSB 26 +#define BIAS_BIAS2_PWD_IC5GDIV25_MASK 0x1c000000 +#define BIAS_BIAS2_PWD_IC5GDIV25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GDIV25_MASK) >> BIAS_BIAS2_PWD_IC5GDIV25_LSB) +#define BIAS_BIAS2_PWD_IC5GDIV25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GDIV25_LSB) & BIAS_BIAS2_PWD_IC5GDIV25_MASK) +#define BIAS_BIAS2_PWD_IC5GLOREG25_MSB 25 +#define BIAS_BIAS2_PWD_IC5GLOREG25_LSB 23 +#define BIAS_BIAS2_PWD_IC5GLOREG25_MASK 0x03800000 +#define BIAS_BIAS2_PWD_IC5GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK) >> BIAS_BIAS2_PWD_IC5GLOREG25_LSB) +#define BIAS_BIAS2_PWD_IC5GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GLOREG25_LSB) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK) +#define BIAS_BIAS2_PWD_IRPLL25_MSB 22 +#define BIAS_BIAS2_PWD_IRPLL25_LSB 22 +#define BIAS_BIAS2_PWD_IRPLL25_MASK 0x00400000 +#define BIAS_BIAS2_PWD_IRPLL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRPLL25_MASK) >> BIAS_BIAS2_PWD_IRPLL25_LSB) +#define BIAS_BIAS2_PWD_IRPLL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRPLL25_LSB) & BIAS_BIAS2_PWD_IRPLL25_MASK) +#define BIAS_BIAS2_PWD_IRXTAL25_MSB 21 +#define BIAS_BIAS2_PWD_IRXTAL25_LSB 19 +#define BIAS_BIAS2_PWD_IRXTAL25_MASK 0x00380000 +#define BIAS_BIAS2_PWD_IRXTAL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRXTAL25_MASK) >> BIAS_BIAS2_PWD_IRXTAL25_LSB) +#define BIAS_BIAS2_PWD_IRXTAL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRXTAL25_LSB) & BIAS_BIAS2_PWD_IRXTAL25_MASK) +#define BIAS_BIAS2_PWD_IRTSENS25_MSB 18 +#define BIAS_BIAS2_PWD_IRTSENS25_LSB 16 +#define BIAS_BIAS2_PWD_IRTSENS25_MASK 0x00070000 +#define BIAS_BIAS2_PWD_IRTSENS25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTSENS25_MASK) >> BIAS_BIAS2_PWD_IRTSENS25_LSB) +#define BIAS_BIAS2_PWD_IRTSENS25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTSENS25_LSB) & BIAS_BIAS2_PWD_IRTSENS25_MASK) +#define BIAS_BIAS2_PWD_IRTXPC25_MSB 15 +#define BIAS_BIAS2_PWD_IRTXPC25_LSB 13 +#define BIAS_BIAS2_PWD_IRTXPC25_MASK 0x0000e000 +#define BIAS_BIAS2_PWD_IRTXPC25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTXPC25_MASK) >> BIAS_BIAS2_PWD_IRTXPC25_LSB) +#define BIAS_BIAS2_PWD_IRTXPC25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTXPC25_LSB) & BIAS_BIAS2_PWD_IRTXPC25_MASK) +#define BIAS_BIAS2_PWD_IRLDO25_MSB 12 +#define BIAS_BIAS2_PWD_IRLDO25_LSB 12 +#define BIAS_BIAS2_PWD_IRLDO25_MASK 0x00001000 +#define BIAS_BIAS2_PWD_IRLDO25_GET(x) (((x) & BIAS_BIAS2_PWD_IRLDO25_MASK) >> BIAS_BIAS2_PWD_IRLDO25_LSB) +#define BIAS_BIAS2_PWD_IRLDO25_SET(x) (((x) << BIAS_BIAS2_PWD_IRLDO25_LSB) & BIAS_BIAS2_PWD_IRLDO25_MASK) +#define BIAS_BIAS2_PWD_IR2GTXMIX25_MSB 11 +#define BIAS_BIAS2_PWD_IR2GTXMIX25_LSB 9 +#define BIAS_BIAS2_PWD_IR2GTXMIX25_MASK 0x00000e00 +#define BIAS_BIAS2_PWD_IR2GTXMIX25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK) >> BIAS_BIAS2_PWD_IR2GTXMIX25_LSB) +#define BIAS_BIAS2_PWD_IR2GTXMIX25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GTXMIX25_LSB) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK) +#define BIAS_BIAS2_PWD_IR2GLOREG25_MSB 8 +#define BIAS_BIAS2_PWD_IR2GLOREG25_LSB 6 +#define BIAS_BIAS2_PWD_IR2GLOREG25_MASK 0x000001c0 +#define BIAS_BIAS2_PWD_IR2GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLOREG25_LSB) +#define BIAS_BIAS2_PWD_IR2GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLOREG25_LSB) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK) +#define BIAS_BIAS2_PWD_IR2GLNAREG25_MSB 5 +#define BIAS_BIAS2_PWD_IR2GLNAREG25_LSB 3 +#define BIAS_BIAS2_PWD_IR2GLNAREG25_MASK 0x00000038 +#define BIAS_BIAS2_PWD_IR2GLNAREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLNAREG25_LSB) +#define BIAS_BIAS2_PWD_IR2GLNAREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLNAREG25_LSB) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK) +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MSB 2 +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB 0 +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK 0x00000007 +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_GET(x) (((x) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK) >> BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB) +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_SET(x) (((x) << BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK) + +#define BIAS_BIAS3_ADDRESS 0x00000044 +#define BIAS_BIAS3_OFFSET 0x00000044 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_MSB 31 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_LSB 29 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_MASK 0xe0000000 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK) >> BIAS_BIAS3_PWD_IR5GTXMIX25_LSB) +#define BIAS_BIAS3_PWD_IR5GTXMIX25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GTXMIX25_LSB) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK) +#define BIAS_BIAS3_PWD_IR5GAGC25_MSB 28 +#define BIAS_BIAS3_PWD_IR5GAGC25_LSB 26 +#define BIAS_BIAS3_PWD_IR5GAGC25_MASK 0x1c000000 +#define BIAS_BIAS3_PWD_IR5GAGC25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GAGC25_MASK) >> BIAS_BIAS3_PWD_IR5GAGC25_LSB) +#define BIAS_BIAS3_PWD_IR5GAGC25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GAGC25_LSB) & BIAS_BIAS3_PWD_IR5GAGC25_MASK) +#define BIAS_BIAS3_PWD_ICDAC50_MSB 25 +#define BIAS_BIAS3_PWD_ICDAC50_LSB 23 +#define BIAS_BIAS3_PWD_ICDAC50_MASK 0x03800000 +#define BIAS_BIAS3_PWD_ICDAC50_GET(x) (((x) & BIAS_BIAS3_PWD_ICDAC50_MASK) >> BIAS_BIAS3_PWD_ICDAC50_LSB) +#define BIAS_BIAS3_PWD_ICDAC50_SET(x) (((x) << BIAS_BIAS3_PWD_ICDAC50_LSB) & BIAS_BIAS3_PWD_ICDAC50_MASK) +#define BIAS_BIAS3_PWD_ICSYNTH50_MSB 22 +#define BIAS_BIAS3_PWD_ICSYNTH50_LSB 22 +#define BIAS_BIAS3_PWD_ICSYNTH50_MASK 0x00400000 +#define BIAS_BIAS3_PWD_ICSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_ICSYNTH50_MASK) >> BIAS_BIAS3_PWD_ICSYNTH50_LSB) +#define BIAS_BIAS3_PWD_ICSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_ICSYNTH50_LSB) & BIAS_BIAS3_PWD_ICSYNTH50_MASK) +#define BIAS_BIAS3_PWD_ICBB50_MSB 21 +#define BIAS_BIAS3_PWD_ICBB50_LSB 21 +#define BIAS_BIAS3_PWD_ICBB50_MASK 0x00200000 +#define BIAS_BIAS3_PWD_ICBB50_GET(x) (((x) & BIAS_BIAS3_PWD_ICBB50_MASK) >> BIAS_BIAS3_PWD_ICBB50_LSB) +#define BIAS_BIAS3_PWD_ICBB50_SET(x) (((x) << BIAS_BIAS3_PWD_ICBB50_LSB) & BIAS_BIAS3_PWD_ICBB50_MASK) +#define BIAS_BIAS3_PWD_IC2GDIV50_MSB 20 +#define BIAS_BIAS3_PWD_IC2GDIV50_LSB 18 +#define BIAS_BIAS3_PWD_IC2GDIV50_MASK 0x001c0000 +#define BIAS_BIAS3_PWD_IC2GDIV50_GET(x) (((x) & BIAS_BIAS3_PWD_IC2GDIV50_MASK) >> BIAS_BIAS3_PWD_IC2GDIV50_LSB) +#define BIAS_BIAS3_PWD_IC2GDIV50_SET(x) (((x) << BIAS_BIAS3_PWD_IC2GDIV50_LSB) & BIAS_BIAS3_PWD_IC2GDIV50_MASK) +#define BIAS_BIAS3_PWD_IRSYNTH50_MSB 17 +#define BIAS_BIAS3_PWD_IRSYNTH50_LSB 17 +#define BIAS_BIAS3_PWD_IRSYNTH50_MASK 0x00020000 +#define BIAS_BIAS3_PWD_IRSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_IRSYNTH50_MASK) >> BIAS_BIAS3_PWD_IRSYNTH50_LSB) +#define BIAS_BIAS3_PWD_IRSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_IRSYNTH50_LSB) & BIAS_BIAS3_PWD_IRSYNTH50_MASK) +#define BIAS_BIAS3_PWD_IRBB50_MSB 16 +#define BIAS_BIAS3_PWD_IRBB50_LSB 16 +#define BIAS_BIAS3_PWD_IRBB50_MASK 0x00010000 +#define BIAS_BIAS3_PWD_IRBB50_GET(x) (((x) & BIAS_BIAS3_PWD_IRBB50_MASK) >> BIAS_BIAS3_PWD_IRBB50_LSB) +#define BIAS_BIAS3_PWD_IRBB50_SET(x) (((x) << BIAS_BIAS3_PWD_IRBB50_LSB) & BIAS_BIAS3_PWD_IRBB50_MASK) +#define BIAS_BIAS3_PWD_IC25SPARE1_MSB 15 +#define BIAS_BIAS3_PWD_IC25SPARE1_LSB 13 +#define BIAS_BIAS3_PWD_IC25SPARE1_MASK 0x0000e000 +#define BIAS_BIAS3_PWD_IC25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPARE1_MASK) >> BIAS_BIAS3_PWD_IC25SPARE1_LSB) +#define BIAS_BIAS3_PWD_IC25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPARE1_LSB) & BIAS_BIAS3_PWD_IC25SPARE1_MASK) +#define BIAS_BIAS3_PWD_IC25SPARE2_MSB 12 +#define BIAS_BIAS3_PWD_IC25SPARE2_LSB 10 +#define BIAS_BIAS3_PWD_IC25SPARE2_MASK 0x00001c00 +#define BIAS_BIAS3_PWD_IC25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPARE2_MASK) >> BIAS_BIAS3_PWD_IC25SPARE2_LSB) +#define BIAS_BIAS3_PWD_IC25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPARE2_LSB) & BIAS_BIAS3_PWD_IC25SPARE2_MASK) +#define BIAS_BIAS3_PWD_IR25SPARE1_MSB 9 +#define BIAS_BIAS3_PWD_IR25SPARE1_LSB 7 +#define BIAS_BIAS3_PWD_IR25SPARE1_MASK 0x00000380 +#define BIAS_BIAS3_PWD_IR25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPARE1_MASK) >> BIAS_BIAS3_PWD_IR25SPARE1_LSB) +#define BIAS_BIAS3_PWD_IR25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPARE1_LSB) & BIAS_BIAS3_PWD_IR25SPARE1_MASK) +#define BIAS_BIAS3_PWD_IR25SPARE2_MSB 6 +#define BIAS_BIAS3_PWD_IR25SPARE2_LSB 4 +#define BIAS_BIAS3_PWD_IR25SPARE2_MASK 0x00000070 +#define BIAS_BIAS3_PWD_IR25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPARE2_MASK) >> BIAS_BIAS3_PWD_IR25SPARE2_LSB) +#define BIAS_BIAS3_PWD_IR25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPARE2_LSB) & BIAS_BIAS3_PWD_IR25SPARE2_MASK) +#define BIAS_BIAS3_PWD_ICDACREG12P5_MSB 3 +#define BIAS_BIAS3_PWD_ICDACREG12P5_LSB 1 +#define BIAS_BIAS3_PWD_ICDACREG12P5_MASK 0x0000000e +#define BIAS_BIAS3_PWD_ICDACREG12P5_GET(x) (((x) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK) >> BIAS_BIAS3_PWD_ICDACREG12P5_LSB) +#define BIAS_BIAS3_PWD_ICDACREG12P5_SET(x) (((x) << BIAS_BIAS3_PWD_ICDACREG12P5_LSB) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK) +#define BIAS_BIAS3_SPARE_MSB 0 +#define BIAS_BIAS3_SPARE_LSB 0 +#define BIAS_BIAS3_SPARE_MASK 0x00000001 +#define BIAS_BIAS3_SPARE_GET(x) (((x) & BIAS_BIAS3_SPARE_MASK) >> BIAS_BIAS3_SPARE_LSB) +#define BIAS_BIAS3_SPARE_SET(x) (((x) << BIAS_BIAS3_SPARE_LSB) & BIAS_BIAS3_SPARE_MASK) + +#define TXPC_TXPC_ADDRESS 0x00000048 +#define TXPC_TXPC_OFFSET 0x00000048 +#define TXPC_TXPC_SELINTPD_MSB 31 +#define TXPC_TXPC_SELINTPD_LSB 31 +#define TXPC_TXPC_SELINTPD_MASK 0x80000000 +#define TXPC_TXPC_SELINTPD_GET(x) (((x) & TXPC_TXPC_SELINTPD_MASK) >> TXPC_TXPC_SELINTPD_LSB) +#define TXPC_TXPC_SELINTPD_SET(x) (((x) << TXPC_TXPC_SELINTPD_LSB) & TXPC_TXPC_SELINTPD_MASK) +#define TXPC_TXPC_TEST_MSB 30 +#define TXPC_TXPC_TEST_LSB 30 +#define TXPC_TXPC_TEST_MASK 0x40000000 +#define TXPC_TXPC_TEST_GET(x) (((x) & TXPC_TXPC_TEST_MASK) >> TXPC_TXPC_TEST_LSB) +#define TXPC_TXPC_TEST_SET(x) (((x) << TXPC_TXPC_TEST_LSB) & TXPC_TXPC_TEST_MASK) +#define TXPC_TXPC_TESTGAIN_MSB 29 +#define TXPC_TXPC_TESTGAIN_LSB 28 +#define TXPC_TXPC_TESTGAIN_MASK 0x30000000 +#define TXPC_TXPC_TESTGAIN_GET(x) (((x) & TXPC_TXPC_TESTGAIN_MASK) >> TXPC_TXPC_TESTGAIN_LSB) +#define TXPC_TXPC_TESTGAIN_SET(x) (((x) << TXPC_TXPC_TESTGAIN_LSB) & TXPC_TXPC_TESTGAIN_MASK) +#define TXPC_TXPC_TESTDAC_MSB 27 +#define TXPC_TXPC_TESTDAC_LSB 22 +#define TXPC_TXPC_TESTDAC_MASK 0x0fc00000 +#define TXPC_TXPC_TESTDAC_GET(x) (((x) & TXPC_TXPC_TESTDAC_MASK) >> TXPC_TXPC_TESTDAC_LSB) +#define TXPC_TXPC_TESTDAC_SET(x) (((x) << TXPC_TXPC_TESTDAC_LSB) & TXPC_TXPC_TESTDAC_MASK) +#define TXPC_TXPC_TESTPWDPC_MSB 21 +#define TXPC_TXPC_TESTPWDPC_LSB 21 +#define TXPC_TXPC_TESTPWDPC_MASK 0x00200000 +#define TXPC_TXPC_TESTPWDPC_GET(x) (((x) & TXPC_TXPC_TESTPWDPC_MASK) >> TXPC_TXPC_TESTPWDPC_LSB) +#define TXPC_TXPC_TESTPWDPC_SET(x) (((x) << TXPC_TXPC_TESTPWDPC_LSB) & TXPC_TXPC_TESTPWDPC_MASK) +#define TXPC_TXPC_CURHALF_MSB 20 +#define TXPC_TXPC_CURHALF_LSB 20 +#define TXPC_TXPC_CURHALF_MASK 0x00100000 +#define TXPC_TXPC_CURHALF_GET(x) (((x) & TXPC_TXPC_CURHALF_MASK) >> TXPC_TXPC_CURHALF_LSB) +#define TXPC_TXPC_CURHALF_SET(x) (((x) << TXPC_TXPC_CURHALF_LSB) & TXPC_TXPC_CURHALF_MASK) +#define TXPC_TXPC_NEGOUT_MSB 19 +#define TXPC_TXPC_NEGOUT_LSB 19 +#define TXPC_TXPC_NEGOUT_MASK 0x00080000 +#define TXPC_TXPC_NEGOUT_GET(x) (((x) & TXPC_TXPC_NEGOUT_MASK) >> TXPC_TXPC_NEGOUT_LSB) +#define TXPC_TXPC_NEGOUT_SET(x) (((x) << TXPC_TXPC_NEGOUT_LSB) & TXPC_TXPC_NEGOUT_MASK) +#define TXPC_TXPC_CLKDELAY_MSB 18 +#define TXPC_TXPC_CLKDELAY_LSB 18 +#define TXPC_TXPC_CLKDELAY_MASK 0x00040000 +#define TXPC_TXPC_CLKDELAY_GET(x) (((x) & TXPC_TXPC_CLKDELAY_MASK) >> TXPC_TXPC_CLKDELAY_LSB) +#define TXPC_TXPC_CLKDELAY_SET(x) (((x) << TXPC_TXPC_CLKDELAY_LSB) & TXPC_TXPC_CLKDELAY_MASK) +#define TXPC_TXPC_SELMODREF_MSB 17 +#define TXPC_TXPC_SELMODREF_LSB 17 +#define TXPC_TXPC_SELMODREF_MASK 0x00020000 +#define TXPC_TXPC_SELMODREF_GET(x) (((x) & TXPC_TXPC_SELMODREF_MASK) >> TXPC_TXPC_SELMODREF_LSB) +#define TXPC_TXPC_SELMODREF_SET(x) (((x) << TXPC_TXPC_SELMODREF_LSB) & TXPC_TXPC_SELMODREF_MASK) +#define TXPC_TXPC_SELCMOUT_MSB 16 +#define TXPC_TXPC_SELCMOUT_LSB 16 +#define TXPC_TXPC_SELCMOUT_MASK 0x00010000 +#define TXPC_TXPC_SELCMOUT_GET(x) (((x) & TXPC_TXPC_SELCMOUT_MASK) >> TXPC_TXPC_SELCMOUT_LSB) +#define TXPC_TXPC_SELCMOUT_SET(x) (((x) << TXPC_TXPC_SELCMOUT_LSB) & TXPC_TXPC_SELCMOUT_MASK) +#define TXPC_TXPC_TSMODE_MSB 15 +#define TXPC_TXPC_TSMODE_LSB 14 +#define TXPC_TXPC_TSMODE_MASK 0x0000c000 +#define TXPC_TXPC_TSMODE_GET(x) (((x) & TXPC_TXPC_TSMODE_MASK) >> TXPC_TXPC_TSMODE_LSB) +#define TXPC_TXPC_TSMODE_SET(x) (((x) << TXPC_TXPC_TSMODE_LSB) & TXPC_TXPC_TSMODE_MASK) +#define TXPC_TXPC_N_MSB 13 +#define TXPC_TXPC_N_LSB 6 +#define TXPC_TXPC_N_MASK 0x00003fc0 +#define TXPC_TXPC_N_GET(x) (((x) & TXPC_TXPC_N_MASK) >> TXPC_TXPC_N_LSB) +#define TXPC_TXPC_N_SET(x) (((x) << TXPC_TXPC_N_LSB) & TXPC_TXPC_N_MASK) +#define TXPC_TXPC_ON1STSYNTHON_MSB 5 +#define TXPC_TXPC_ON1STSYNTHON_LSB 5 +#define TXPC_TXPC_ON1STSYNTHON_MASK 0x00000020 +#define TXPC_TXPC_ON1STSYNTHON_GET(x) (((x) & TXPC_TXPC_ON1STSYNTHON_MASK) >> TXPC_TXPC_ON1STSYNTHON_LSB) +#define TXPC_TXPC_ON1STSYNTHON_SET(x) (((x) << TXPC_TXPC_ON1STSYNTHON_LSB) & TXPC_TXPC_ON1STSYNTHON_MASK) +#define TXPC_TXPC_SELINIT_MSB 4 +#define TXPC_TXPC_SELINIT_LSB 3 +#define TXPC_TXPC_SELINIT_MASK 0x00000018 +#define TXPC_TXPC_SELINIT_GET(x) (((x) & TXPC_TXPC_SELINIT_MASK) >> TXPC_TXPC_SELINIT_LSB) +#define TXPC_TXPC_SELINIT_SET(x) (((x) << TXPC_TXPC_SELINIT_LSB) & TXPC_TXPC_SELINIT_MASK) +#define TXPC_TXPC_SELCOUNT_MSB 2 +#define TXPC_TXPC_SELCOUNT_LSB 2 +#define TXPC_TXPC_SELCOUNT_MASK 0x00000004 +#define TXPC_TXPC_SELCOUNT_GET(x) (((x) & TXPC_TXPC_SELCOUNT_MASK) >> TXPC_TXPC_SELCOUNT_LSB) +#define TXPC_TXPC_SELCOUNT_SET(x) (((x) << TXPC_TXPC_SELCOUNT_LSB) & TXPC_TXPC_SELCOUNT_MASK) +#define TXPC_TXPC_ATBSEL_MSB 1 +#define TXPC_TXPC_ATBSEL_LSB 0 +#define TXPC_TXPC_ATBSEL_MASK 0x00000003 +#define TXPC_TXPC_ATBSEL_GET(x) (((x) & TXPC_TXPC_ATBSEL_MASK) >> TXPC_TXPC_ATBSEL_LSB) +#define TXPC_TXPC_ATBSEL_SET(x) (((x) << TXPC_TXPC_ATBSEL_LSB) & TXPC_TXPC_ATBSEL_MASK) + +#define TXPC_MISC_ADDRESS 0x0000004c +#define TXPC_MISC_OFFSET 0x0000004c +#define TXPC_MISC_FLIPBMODE_MSB 31 +#define TXPC_MISC_FLIPBMODE_LSB 31 +#define TXPC_MISC_FLIPBMODE_MASK 0x80000000 +#define TXPC_MISC_FLIPBMODE_GET(x) (((x) & TXPC_MISC_FLIPBMODE_MASK) >> TXPC_MISC_FLIPBMODE_LSB) +#define TXPC_MISC_FLIPBMODE_SET(x) (((x) << TXPC_MISC_FLIPBMODE_LSB) & TXPC_MISC_FLIPBMODE_MASK) +#define TXPC_MISC_LEVEL_MSB 30 +#define TXPC_MISC_LEVEL_LSB 29 +#define TXPC_MISC_LEVEL_MASK 0x60000000 +#define TXPC_MISC_LEVEL_GET(x) (((x) & TXPC_MISC_LEVEL_MASK) >> TXPC_MISC_LEVEL_LSB) +#define TXPC_MISC_LEVEL_SET(x) (((x) << TXPC_MISC_LEVEL_LSB) & TXPC_MISC_LEVEL_MASK) +#define TXPC_MISC_LDO_TEST_MODE_MSB 28 +#define TXPC_MISC_LDO_TEST_MODE_LSB 28 +#define TXPC_MISC_LDO_TEST_MODE_MASK 0x10000000 +#define TXPC_MISC_LDO_TEST_MODE_GET(x) (((x) & TXPC_MISC_LDO_TEST_MODE_MASK) >> TXPC_MISC_LDO_TEST_MODE_LSB) +#define TXPC_MISC_LDO_TEST_MODE_SET(x) (((x) << TXPC_MISC_LDO_TEST_MODE_LSB) & TXPC_MISC_LDO_TEST_MODE_MASK) +#define TXPC_MISC_NOTCXODET_MSB 27 +#define TXPC_MISC_NOTCXODET_LSB 27 +#define TXPC_MISC_NOTCXODET_MASK 0x08000000 +#define TXPC_MISC_NOTCXODET_GET(x) (((x) & TXPC_MISC_NOTCXODET_MASK) >> TXPC_MISC_NOTCXODET_LSB) +#define TXPC_MISC_NOTCXODET_SET(x) (((x) << TXPC_MISC_NOTCXODET_LSB) & TXPC_MISC_NOTCXODET_MASK) +#define TXPC_MISC_PWDCLKIND_MSB 26 +#define TXPC_MISC_PWDCLKIND_LSB 26 +#define TXPC_MISC_PWDCLKIND_MASK 0x04000000 +#define TXPC_MISC_PWDCLKIND_GET(x) (((x) & TXPC_MISC_PWDCLKIND_MASK) >> TXPC_MISC_PWDCLKIND_LSB) +#define TXPC_MISC_PWDCLKIND_SET(x) (((x) << TXPC_MISC_PWDCLKIND_LSB) & TXPC_MISC_PWDCLKIND_MASK) +#define TXPC_MISC_PWDXINPAD_MSB 25 +#define TXPC_MISC_PWDXINPAD_LSB 25 +#define TXPC_MISC_PWDXINPAD_MASK 0x02000000 +#define TXPC_MISC_PWDXINPAD_GET(x) (((x) & TXPC_MISC_PWDXINPAD_MASK) >> TXPC_MISC_PWDXINPAD_LSB) +#define TXPC_MISC_PWDXINPAD_SET(x) (((x) << TXPC_MISC_PWDXINPAD_LSB) & TXPC_MISC_PWDXINPAD_MASK) +#define TXPC_MISC_LOCALBIAS_MSB 24 +#define TXPC_MISC_LOCALBIAS_LSB 24 +#define TXPC_MISC_LOCALBIAS_MASK 0x01000000 +#define TXPC_MISC_LOCALBIAS_GET(x) (((x) & TXPC_MISC_LOCALBIAS_MASK) >> TXPC_MISC_LOCALBIAS_LSB) +#define TXPC_MISC_LOCALBIAS_SET(x) (((x) << TXPC_MISC_LOCALBIAS_LSB) & TXPC_MISC_LOCALBIAS_MASK) +#define TXPC_MISC_LOCALBIAS2X_MSB 23 +#define TXPC_MISC_LOCALBIAS2X_LSB 23 +#define TXPC_MISC_LOCALBIAS2X_MASK 0x00800000 +#define TXPC_MISC_LOCALBIAS2X_GET(x) (((x) & TXPC_MISC_LOCALBIAS2X_MASK) >> TXPC_MISC_LOCALBIAS2X_LSB) +#define TXPC_MISC_LOCALBIAS2X_SET(x) (((x) << TXPC_MISC_LOCALBIAS2X_LSB) & TXPC_MISC_LOCALBIAS2X_MASK) +#define TXPC_MISC_SELTSP_MSB 22 +#define TXPC_MISC_SELTSP_LSB 22 +#define TXPC_MISC_SELTSP_MASK 0x00400000 +#define TXPC_MISC_SELTSP_GET(x) (((x) & TXPC_MISC_SELTSP_MASK) >> TXPC_MISC_SELTSP_LSB) +#define TXPC_MISC_SELTSP_SET(x) (((x) << TXPC_MISC_SELTSP_LSB) & TXPC_MISC_SELTSP_MASK) +#define TXPC_MISC_SELTSN_MSB 21 +#define TXPC_MISC_SELTSN_LSB 21 +#define TXPC_MISC_SELTSN_MASK 0x00200000 +#define TXPC_MISC_SELTSN_GET(x) (((x) & TXPC_MISC_SELTSN_MASK) >> TXPC_MISC_SELTSN_LSB) +#define TXPC_MISC_SELTSN_SET(x) (((x) << TXPC_MISC_SELTSN_LSB) & TXPC_MISC_SELTSN_MASK) +#define TXPC_MISC_SPARE_A_MSB 20 +#define TXPC_MISC_SPARE_A_LSB 18 +#define TXPC_MISC_SPARE_A_MASK 0x001c0000 +#define TXPC_MISC_SPARE_A_GET(x) (((x) & TXPC_MISC_SPARE_A_MASK) >> TXPC_MISC_SPARE_A_LSB) +#define TXPC_MISC_SPARE_A_SET(x) (((x) << TXPC_MISC_SPARE_A_LSB) & TXPC_MISC_SPARE_A_MASK) +#define TXPC_MISC_DECOUT_MSB 17 +#define TXPC_MISC_DECOUT_LSB 8 +#define TXPC_MISC_DECOUT_MASK 0x0003ff00 +#define TXPC_MISC_DECOUT_GET(x) (((x) & TXPC_MISC_DECOUT_MASK) >> TXPC_MISC_DECOUT_LSB) +#define TXPC_MISC_DECOUT_SET(x) (((x) << TXPC_MISC_DECOUT_LSB) & TXPC_MISC_DECOUT_MASK) +#define TXPC_MISC_XTALDIV_MSB 7 +#define TXPC_MISC_XTALDIV_LSB 6 +#define TXPC_MISC_XTALDIV_MASK 0x000000c0 +#define TXPC_MISC_XTALDIV_GET(x) (((x) & TXPC_MISC_XTALDIV_MASK) >> TXPC_MISC_XTALDIV_LSB) +#define TXPC_MISC_XTALDIV_SET(x) (((x) << TXPC_MISC_XTALDIV_LSB) & TXPC_MISC_XTALDIV_MASK) +#define TXPC_MISC_SPARE_MSB 5 +#define TXPC_MISC_SPARE_LSB 0 +#define TXPC_MISC_SPARE_MASK 0x0000003f +#define TXPC_MISC_SPARE_GET(x) (((x) & TXPC_MISC_SPARE_MASK) >> TXPC_MISC_SPARE_LSB) +#define TXPC_MISC_SPARE_SET(x) (((x) << TXPC_MISC_SPARE_LSB) & TXPC_MISC_SPARE_MASK) + +#define RXTXBB_RXTXBB1_ADDRESS 0x00000050 +#define RXTXBB_RXTXBB1_OFFSET 0x00000050 +#define RXTXBB_RXTXBB1_SPARE_MSB 31 +#define RXTXBB_RXTXBB1_SPARE_LSB 19 +#define RXTXBB_RXTXBB1_SPARE_MASK 0xfff80000 +#define RXTXBB_RXTXBB1_SPARE_GET(x) (((x) & RXTXBB_RXTXBB1_SPARE_MASK) >> RXTXBB_RXTXBB1_SPARE_LSB) +#define RXTXBB_RXTXBB1_SPARE_SET(x) (((x) << RXTXBB_RXTXBB1_SPARE_LSB) & RXTXBB_RXTXBB1_SPARE_MASK) +#define RXTXBB_RXTXBB1_FNOTCH_MSB 18 +#define RXTXBB_RXTXBB1_FNOTCH_LSB 17 +#define RXTXBB_RXTXBB1_FNOTCH_MASK 0x00060000 +#define RXTXBB_RXTXBB1_FNOTCH_GET(x) (((x) & RXTXBB_RXTXBB1_FNOTCH_MASK) >> RXTXBB_RXTXBB1_FNOTCH_LSB) +#define RXTXBB_RXTXBB1_FNOTCH_SET(x) (((x) << RXTXBB_RXTXBB1_FNOTCH_LSB) & RXTXBB_RXTXBB1_FNOTCH_MASK) +#define RXTXBB_RXTXBB1_SEL_ATB_MSB 16 +#define RXTXBB_RXTXBB1_SEL_ATB_LSB 9 +#define RXTXBB_RXTXBB1_SEL_ATB_MASK 0x0001fe00 +#define RXTXBB_RXTXBB1_SEL_ATB_GET(x) (((x) & RXTXBB_RXTXBB1_SEL_ATB_MASK) >> RXTXBB_RXTXBB1_SEL_ATB_LSB) +#define RXTXBB_RXTXBB1_SEL_ATB_SET(x) (((x) << RXTXBB_RXTXBB1_SEL_ATB_LSB) & RXTXBB_RXTXBB1_SEL_ATB_MASK) +#define RXTXBB_RXTXBB1_PDDACINTERFACE_MSB 8 +#define RXTXBB_RXTXBB1_PDDACINTERFACE_LSB 8 +#define RXTXBB_RXTXBB1_PDDACINTERFACE_MASK 0x00000100 +#define RXTXBB_RXTXBB1_PDDACINTERFACE_GET(x) (((x) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK) >> RXTXBB_RXTXBB1_PDDACINTERFACE_LSB) +#define RXTXBB_RXTXBB1_PDDACINTERFACE_SET(x) (((x) << RXTXBB_RXTXBB1_PDDACINTERFACE_LSB) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK) +#define RXTXBB_RXTXBB1_PDV2I_MSB 7 +#define RXTXBB_RXTXBB1_PDV2I_LSB 7 +#define RXTXBB_RXTXBB1_PDV2I_MASK 0x00000080 +#define RXTXBB_RXTXBB1_PDV2I_GET(x) (((x) & RXTXBB_RXTXBB1_PDV2I_MASK) >> RXTXBB_RXTXBB1_PDV2I_LSB) +#define RXTXBB_RXTXBB1_PDV2I_SET(x) (((x) << RXTXBB_RXTXBB1_PDV2I_LSB) & RXTXBB_RXTXBB1_PDV2I_MASK) +#define RXTXBB_RXTXBB1_PDI2V_MSB 6 +#define RXTXBB_RXTXBB1_PDI2V_LSB 6 +#define RXTXBB_RXTXBB1_PDI2V_MASK 0x00000040 +#define RXTXBB_RXTXBB1_PDI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDI2V_MASK) >> RXTXBB_RXTXBB1_PDI2V_LSB) +#define RXTXBB_RXTXBB1_PDI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDI2V_LSB) & RXTXBB_RXTXBB1_PDI2V_MASK) +#define RXTXBB_RXTXBB1_PDRXTXBB_MSB 5 +#define RXTXBB_RXTXBB1_PDRXTXBB_LSB 5 +#define RXTXBB_RXTXBB1_PDRXTXBB_MASK 0x00000020 +#define RXTXBB_RXTXBB1_PDRXTXBB_GET(x) (((x) & RXTXBB_RXTXBB1_PDRXTXBB_MASK) >> RXTXBB_RXTXBB1_PDRXTXBB_LSB) +#define RXTXBB_RXTXBB1_PDRXTXBB_SET(x) (((x) << RXTXBB_RXTXBB1_PDRXTXBB_LSB) & RXTXBB_RXTXBB1_PDRXTXBB_MASK) +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MSB 4 +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB 4 +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK 0x00000010 +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB) +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK) +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MSB 3 +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB 3 +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK 0x00000008 +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB) +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK) +#define RXTXBB_RXTXBB1_PDOFFSETI2V_MSB 2 +#define RXTXBB_RXTXBB1_PDOFFSETI2V_LSB 2 +#define RXTXBB_RXTXBB1_PDOFFSETI2V_MASK 0x00000004 +#define RXTXBB_RXTXBB1_PDOFFSETI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK) >> RXTXBB_RXTXBB1_PDOFFSETI2V_LSB) +#define RXTXBB_RXTXBB1_PDOFFSETI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETI2V_LSB) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK) +#define RXTXBB_RXTXBB1_PDLOQ_MSB 1 +#define RXTXBB_RXTXBB1_PDLOQ_LSB 1 +#define RXTXBB_RXTXBB1_PDLOQ_MASK 0x00000002 +#define RXTXBB_RXTXBB1_PDLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDLOQ_MASK) >> RXTXBB_RXTXBB1_PDLOQ_LSB) +#define RXTXBB_RXTXBB1_PDLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDLOQ_LSB) & RXTXBB_RXTXBB1_PDLOQ_MASK) +#define RXTXBB_RXTXBB1_PDHIQ_MSB 0 +#define RXTXBB_RXTXBB1_PDHIQ_LSB 0 +#define RXTXBB_RXTXBB1_PDHIQ_MASK 0x00000001 +#define RXTXBB_RXTXBB1_PDHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDHIQ_MASK) >> RXTXBB_RXTXBB1_PDHIQ_LSB) +#define RXTXBB_RXTXBB1_PDHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDHIQ_LSB) & RXTXBB_RXTXBB1_PDHIQ_MASK) + +#define RXTXBB_RXTXBB2_ADDRESS 0x00000054 +#define RXTXBB_RXTXBB2_OFFSET 0x00000054 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MSB 31 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB 29 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK 0xe0000000 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB) +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK) +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MSB 28 +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB 26 +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK 0x1c000000 +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB) +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK) +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MSB 25 +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB 23 +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK 0x03800000 +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB) +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK) +#define RXTXBB_RXTXBB2_SPARE_MSB 22 +#define RXTXBB_RXTXBB2_SPARE_LSB 21 +#define RXTXBB_RXTXBB2_SPARE_MASK 0x00600000 +#define RXTXBB_RXTXBB2_SPARE_GET(x) (((x) & RXTXBB_RXTXBB2_SPARE_MASK) >> RXTXBB_RXTXBB2_SPARE_LSB) +#define RXTXBB_RXTXBB2_SPARE_SET(x) (((x) << RXTXBB_RXTXBB2_SPARE_LSB) & RXTXBB_RXTXBB2_SPARE_MASK) +#define RXTXBB_RXTXBB2_SHORTBUFFER_MSB 20 +#define RXTXBB_RXTXBB2_SHORTBUFFER_LSB 20 +#define RXTXBB_RXTXBB2_SHORTBUFFER_MASK 0x00100000 +#define RXTXBB_RXTXBB2_SHORTBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK) >> RXTXBB_RXTXBB2_SHORTBUFFER_LSB) +#define RXTXBB_RXTXBB2_SHORTBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SHORTBUFFER_LSB) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK) +#define RXTXBB_RXTXBB2_SELBUFFER_MSB 19 +#define RXTXBB_RXTXBB2_SELBUFFER_LSB 19 +#define RXTXBB_RXTXBB2_SELBUFFER_MASK 0x00080000 +#define RXTXBB_RXTXBB2_SELBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SELBUFFER_MASK) >> RXTXBB_RXTXBB2_SELBUFFER_LSB) +#define RXTXBB_RXTXBB2_SELBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SELBUFFER_LSB) & RXTXBB_RXTXBB2_SELBUFFER_MASK) +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MSB 18 +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB 18 +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK 0x00040000 +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK) +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MSB 17 +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB 17 +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK 0x00020000 +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK) +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MSB 16 +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB 16 +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK 0x00010000 +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK) +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MSB 15 +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB 15 +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK 0x00008000 +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK) +#define RXTXBB_RXTXBB2_CMSEL_MSB 14 +#define RXTXBB_RXTXBB2_CMSEL_LSB 13 +#define RXTXBB_RXTXBB2_CMSEL_MASK 0x00006000 +#define RXTXBB_RXTXBB2_CMSEL_GET(x) (((x) & RXTXBB_RXTXBB2_CMSEL_MASK) >> RXTXBB_RXTXBB2_CMSEL_LSB) +#define RXTXBB_RXTXBB2_CMSEL_SET(x) (((x) << RXTXBB_RXTXBB2_CMSEL_LSB) & RXTXBB_RXTXBB2_CMSEL_MASK) +#define RXTXBB_RXTXBB2_FILTERFC_MSB 12 +#define RXTXBB_RXTXBB2_FILTERFC_LSB 8 +#define RXTXBB_RXTXBB2_FILTERFC_MASK 0x00001f00 +#define RXTXBB_RXTXBB2_FILTERFC_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERFC_MASK) >> RXTXBB_RXTXBB2_FILTERFC_LSB) +#define RXTXBB_RXTXBB2_FILTERFC_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERFC_LSB) & RXTXBB_RXTXBB2_FILTERFC_MASK) +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MSB 7 +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB 7 +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK 0x00000080 +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_GET(x) (((x) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK) >> RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB) +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_SET(x) (((x) << RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK) +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MSB 6 +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB 6 +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK 0x00000040 +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK) >> RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB) +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK) +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MSB 5 +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB 5 +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK 0x00000020 +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MSB 4 +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB 4 +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK 0x00000010 +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MSB 3 +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB 3 +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK 0x00000008 +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MSB 2 +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB 2 +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK 0x00000004 +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MSB 1 +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB 1 +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK 0x00000002 +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MSB 0 +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB 0 +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK 0x00000001 +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_GET(x) (((x) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK) >> RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB) +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_SET(x) (((x) << RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK) + +#define RXTXBB_RXTXBB3_ADDRESS 0x00000058 +#define RXTXBB_RXTXBB3_OFFSET 0x00000058 +#define RXTXBB_RXTXBB3_SPARE_MSB 31 +#define RXTXBB_RXTXBB3_SPARE_LSB 27 +#define RXTXBB_RXTXBB3_SPARE_MASK 0xf8000000 +#define RXTXBB_RXTXBB3_SPARE_GET(x) (((x) & RXTXBB_RXTXBB3_SPARE_MASK) >> RXTXBB_RXTXBB3_SPARE_LSB) +#define RXTXBB_RXTXBB3_SPARE_SET(x) (((x) << RXTXBB_RXTXBB3_SPARE_LSB) & RXTXBB_RXTXBB3_SPARE_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MSB 26 +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB 24 +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK 0x07000000 +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MSB 23 +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB 21 +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK 0x00e00000 +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MSB 20 +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB 18 +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK 0x001c0000 +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MSB 17 +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB 15 +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK 0x00038000 +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MSB 14 +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB 12 +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK 0x00007000 +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MSB 11 +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB 9 +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK 0x00000e00 +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MSB 8 +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB 6 +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK 0x000001c0 +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MSB 5 +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB 3 +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK 0x00000038 +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK) >> RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MSB 2 +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB 0 +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK 0x00000007 +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK) + +#define RXTXBB_RXTXBB4_ADDRESS 0x0000005c +#define RXTXBB_RXTXBB4_OFFSET 0x0000005c +#define RXTXBB_RXTXBB4_SPARE_MSB 31 +#define RXTXBB_RXTXBB4_SPARE_LSB 31 +#define RXTXBB_RXTXBB4_SPARE_MASK 0x80000000 +#define RXTXBB_RXTXBB4_SPARE_GET(x) (((x) & RXTXBB_RXTXBB4_SPARE_MASK) >> RXTXBB_RXTXBB4_SPARE_LSB) +#define RXTXBB_RXTXBB4_SPARE_SET(x) (((x) << RXTXBB_RXTXBB4_SPARE_LSB) & RXTXBB_RXTXBB4_SPARE_MASK) +#define RXTXBB_RXTXBB4_LOCALOFFSET_MSB 30 +#define RXTXBB_RXTXBB4_LOCALOFFSET_LSB 30 +#define RXTXBB_RXTXBB4_LOCALOFFSET_MASK 0x40000000 +#define RXTXBB_RXTXBB4_LOCALOFFSET_GET(x) (((x) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK) >> RXTXBB_RXTXBB4_LOCALOFFSET_LSB) +#define RXTXBB_RXTXBB4_LOCALOFFSET_SET(x) (((x) << RXTXBB_RXTXBB4_LOCALOFFSET_LSB) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRHII_MSB 29 +#define RXTXBB_RXTXBB4_OFSTCORRHII_LSB 25 +#define RXTXBB_RXTXBB4_OFSTCORRHII_MASK 0x3e000000 +#define RXTXBB_RXTXBB4_OFSTCORRHII_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHII_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRHII_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRHII_LSB) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MSB 24 +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB 20 +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK 0x01f00000 +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRLOI_MSB 19 +#define RXTXBB_RXTXBB4_OFSTCORRLOI_LSB 15 +#define RXTXBB_RXTXBB4_OFSTCORRLOI_MASK 0x000f8000 +#define RXTXBB_RXTXBB4_OFSTCORRLOI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOI_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRLOI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRLOI_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MSB 14 +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB 10 +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK 0x00007c00 +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MSB 9 +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB 5 +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK 0x000003e0 +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MSB 4 +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB 0 +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK 0x0000001f +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK) + +#define ADDAC_ADDAC1_ADDRESS 0x00000060 +#define ADDAC_ADDAC1_OFFSET 0x00000060 +#define ADDAC_ADDAC1_PLL_SVREG_MSB 31 +#define ADDAC_ADDAC1_PLL_SVREG_LSB 31 +#define ADDAC_ADDAC1_PLL_SVREG_MASK 0x80000000 +#define ADDAC_ADDAC1_PLL_SVREG_GET(x) (((x) & ADDAC_ADDAC1_PLL_SVREG_MASK) >> ADDAC_ADDAC1_PLL_SVREG_LSB) +#define ADDAC_ADDAC1_PLL_SVREG_SET(x) (((x) << ADDAC_ADDAC1_PLL_SVREG_LSB) & ADDAC_ADDAC1_PLL_SVREG_MASK) +#define ADDAC_ADDAC1_PLL_SCLAMP_MSB 30 +#define ADDAC_ADDAC1_PLL_SCLAMP_LSB 28 +#define ADDAC_ADDAC1_PLL_SCLAMP_MASK 0x70000000 +#define ADDAC_ADDAC1_PLL_SCLAMP_GET(x) (((x) & ADDAC_ADDAC1_PLL_SCLAMP_MASK) >> ADDAC_ADDAC1_PLL_SCLAMP_LSB) +#define ADDAC_ADDAC1_PLL_SCLAMP_SET(x) (((x) << ADDAC_ADDAC1_PLL_SCLAMP_LSB) & ADDAC_ADDAC1_PLL_SCLAMP_MASK) +#define ADDAC_ADDAC1_PLL_ATB_MSB 27 +#define ADDAC_ADDAC1_PLL_ATB_LSB 26 +#define ADDAC_ADDAC1_PLL_ATB_MASK 0x0c000000 +#define ADDAC_ADDAC1_PLL_ATB_GET(x) (((x) & ADDAC_ADDAC1_PLL_ATB_MASK) >> ADDAC_ADDAC1_PLL_ATB_LSB) +#define ADDAC_ADDAC1_PLL_ATB_SET(x) (((x) << ADDAC_ADDAC1_PLL_ATB_LSB) & ADDAC_ADDAC1_PLL_ATB_MASK) +#define ADDAC_ADDAC1_PLL_ICP_MSB 25 +#define ADDAC_ADDAC1_PLL_ICP_LSB 23 +#define ADDAC_ADDAC1_PLL_ICP_MASK 0x03800000 +#define ADDAC_ADDAC1_PLL_ICP_GET(x) (((x) & ADDAC_ADDAC1_PLL_ICP_MASK) >> ADDAC_ADDAC1_PLL_ICP_LSB) +#define ADDAC_ADDAC1_PLL_ICP_SET(x) (((x) << ADDAC_ADDAC1_PLL_ICP_LSB) & ADDAC_ADDAC1_PLL_ICP_MASK) +#define ADDAC_ADDAC1_PLL_FILTER_MSB 22 +#define ADDAC_ADDAC1_PLL_FILTER_LSB 15 +#define ADDAC_ADDAC1_PLL_FILTER_MASK 0x007f8000 +#define ADDAC_ADDAC1_PLL_FILTER_GET(x) (((x) & ADDAC_ADDAC1_PLL_FILTER_MASK) >> ADDAC_ADDAC1_PLL_FILTER_LSB) +#define ADDAC_ADDAC1_PLL_FILTER_SET(x) (((x) << ADDAC_ADDAC1_PLL_FILTER_LSB) & ADDAC_ADDAC1_PLL_FILTER_MASK) +#define ADDAC_ADDAC1_PWDPLL_MSB 14 +#define ADDAC_ADDAC1_PWDPLL_LSB 14 +#define ADDAC_ADDAC1_PWDPLL_MASK 0x00004000 +#define ADDAC_ADDAC1_PWDPLL_GET(x) (((x) & ADDAC_ADDAC1_PWDPLL_MASK) >> ADDAC_ADDAC1_PWDPLL_LSB) +#define ADDAC_ADDAC1_PWDPLL_SET(x) (((x) << ADDAC_ADDAC1_PWDPLL_LSB) & ADDAC_ADDAC1_PWDPLL_MASK) +#define ADDAC_ADDAC1_PWDADC_MSB 13 +#define ADDAC_ADDAC1_PWDADC_LSB 13 +#define ADDAC_ADDAC1_PWDADC_MASK 0x00002000 +#define ADDAC_ADDAC1_PWDADC_GET(x) (((x) & ADDAC_ADDAC1_PWDADC_MASK) >> ADDAC_ADDAC1_PWDADC_LSB) +#define ADDAC_ADDAC1_PWDADC_SET(x) (((x) << ADDAC_ADDAC1_PWDADC_LSB) & ADDAC_ADDAC1_PWDADC_MASK) +#define ADDAC_ADDAC1_PWDDAC_MSB 12 +#define ADDAC_ADDAC1_PWDDAC_LSB 12 +#define ADDAC_ADDAC1_PWDDAC_MASK 0x00001000 +#define ADDAC_ADDAC1_PWDDAC_GET(x) (((x) & ADDAC_ADDAC1_PWDDAC_MASK) >> ADDAC_ADDAC1_PWDDAC_LSB) +#define ADDAC_ADDAC1_PWDDAC_SET(x) (((x) << ADDAC_ADDAC1_PWDDAC_LSB) & ADDAC_ADDAC1_PWDDAC_MASK) +#define ADDAC_ADDAC1_FORCEMSBLOW_MSB 11 +#define ADDAC_ADDAC1_FORCEMSBLOW_LSB 11 +#define ADDAC_ADDAC1_FORCEMSBLOW_MASK 0x00000800 +#define ADDAC_ADDAC1_FORCEMSBLOW_GET(x) (((x) & ADDAC_ADDAC1_FORCEMSBLOW_MASK) >> ADDAC_ADDAC1_FORCEMSBLOW_LSB) +#define ADDAC_ADDAC1_FORCEMSBLOW_SET(x) (((x) << ADDAC_ADDAC1_FORCEMSBLOW_LSB) & ADDAC_ADDAC1_FORCEMSBLOW_MASK) +#define ADDAC_ADDAC1_SELMANPWDS_MSB 10 +#define ADDAC_ADDAC1_SELMANPWDS_LSB 10 +#define ADDAC_ADDAC1_SELMANPWDS_MASK 0x00000400 +#define ADDAC_ADDAC1_SELMANPWDS_GET(x) (((x) & ADDAC_ADDAC1_SELMANPWDS_MASK) >> ADDAC_ADDAC1_SELMANPWDS_LSB) +#define ADDAC_ADDAC1_SELMANPWDS_SET(x) (((x) << ADDAC_ADDAC1_SELMANPWDS_LSB) & ADDAC_ADDAC1_SELMANPWDS_MASK) +#define ADDAC_ADDAC1_INV_CLK160_ADC_MSB 9 +#define ADDAC_ADDAC1_INV_CLK160_ADC_LSB 9 +#define ADDAC_ADDAC1_INV_CLK160_ADC_MASK 0x00000200 +#define ADDAC_ADDAC1_INV_CLK160_ADC_GET(x) (((x) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK) >> ADDAC_ADDAC1_INV_CLK160_ADC_LSB) +#define ADDAC_ADDAC1_INV_CLK160_ADC_SET(x) (((x) << ADDAC_ADDAC1_INV_CLK160_ADC_LSB) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK) +#define ADDAC_ADDAC1_CM_SEL_MSB 8 +#define ADDAC_ADDAC1_CM_SEL_LSB 7 +#define ADDAC_ADDAC1_CM_SEL_MASK 0x00000180 +#define ADDAC_ADDAC1_CM_SEL_GET(x) (((x) & ADDAC_ADDAC1_CM_SEL_MASK) >> ADDAC_ADDAC1_CM_SEL_LSB) +#define ADDAC_ADDAC1_CM_SEL_SET(x) (((x) << ADDAC_ADDAC1_CM_SEL_LSB) & ADDAC_ADDAC1_CM_SEL_MASK) +#define ADDAC_ADDAC1_DISABLE_DAC_REG_MSB 6 +#define ADDAC_ADDAC1_DISABLE_DAC_REG_LSB 6 +#define ADDAC_ADDAC1_DISABLE_DAC_REG_MASK 0x00000040 +#define ADDAC_ADDAC1_DISABLE_DAC_REG_GET(x) (((x) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK) >> ADDAC_ADDAC1_DISABLE_DAC_REG_LSB) +#define ADDAC_ADDAC1_DISABLE_DAC_REG_SET(x) (((x) << ADDAC_ADDAC1_DISABLE_DAC_REG_LSB) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK) +#define ADDAC_ADDAC1_SPARE_MSB 5 +#define ADDAC_ADDAC1_SPARE_LSB 0 +#define ADDAC_ADDAC1_SPARE_MASK 0x0000003f +#define ADDAC_ADDAC1_SPARE_GET(x) (((x) & ADDAC_ADDAC1_SPARE_MASK) >> ADDAC_ADDAC1_SPARE_LSB) +#define ADDAC_ADDAC1_SPARE_SET(x) (((x) << ADDAC_ADDAC1_SPARE_LSB) & ADDAC_ADDAC1_SPARE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct analog_reg_reg_s { + volatile unsigned int synth_synth1; + volatile unsigned int synth_synth2; + volatile unsigned int synth_synth3; + volatile unsigned int synth_synth4; + volatile unsigned int synth_synth5; + volatile unsigned int synth_synth6; + volatile unsigned int synth_synth7; + volatile unsigned int synth_synth8; + volatile unsigned int rf5g_rf5g1; + volatile unsigned int rf5g_rf5g2; + volatile unsigned int rf2g_rf2g1; + volatile unsigned int rf2g_rf2g2; + volatile unsigned int top_gain; + volatile unsigned int top_top; + volatile unsigned int bias_bias_sel; + volatile unsigned int bias_bias1; + volatile unsigned int bias_bias2; + volatile unsigned int bias_bias3; + volatile unsigned int txpc_txpc; + volatile unsigned int txpc_misc; + volatile unsigned int rxtxbb_rxtxbb1; + volatile unsigned int rxtxbb_rxtxbb2; + volatile unsigned int rxtxbb_rxtxbb3; + volatile unsigned int rxtxbb_rxtxbb4; + volatile unsigned int addac_addac1; +} analog_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _ANALOG_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/apb_map.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/apb_map.h --- linux-2.6.26/drivers/net/wireless/ath6k/apb_map.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/apb_map.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,36 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _APB_MAP_H_ +#define _APB_MAP_H_ + +#define RTC_BASE_ADDRESS 0x00004000 +#define VMC_BASE_ADDRESS 0x00008000 +#define UART_BASE_ADDRESS 0x0000c000 +#define SI_BASE_ADDRESS 0x00010000 +#define GPIO_BASE_ADDRESS 0x00014000 +#define MBOX_BASE_ADDRESS 0x00018000 +#define ANALOG_INTF_BASE_ADDRESS 0x0001c000 +#define MAC_BASE_ADDRESS 0x00020000 + +#endif /* _APB_MAP_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/ar6000_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6000_api.h --- linux-2.6.26/drivers/net/wireless/ath6k/ar6000_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6000_api.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,46 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the API to access the OS dependent atheros host driver +// by the WMI or WLAN generic modules. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _AR6000_API_H_ +#define _AR6000_API_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "ar6xapi_linux.h" +#endif + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/ar6xapi_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/ar6xapi_wince.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/ar6xapi_rexos.h" +#endif + +#endif /* _AR6000_API_H */ + diff -urN linux-2.6.26/drivers/net/wireless/ath6k/ar6000_diag.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6000_diag.h --- linux-2.6.26/drivers/net/wireless/ath6k/ar6000_diag.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6000_diag.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,42 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef AR6000_DIAG_H_ +#define AR6000_DIAG_H_ + + +A_STATUS +ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS +ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS +ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length); + +A_STATUS +ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length); + +#endif /*AR6000_DIAG_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/ar6000_drv.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6000_drv.c --- linux-2.6.26/drivers/net/wireless/ath6k/ar6000_drv.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6000_drv.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,4300 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +/* + * This driver is a pseudo ethernet driver to access the Atheros AR6000 + * WLAN Device + */ +static const char athId[] __attribute__ ((unused)) = "$Id: //depot/sw/releases/olca2.2/host/os/linux/ar6000_drv.c#13 $"; + +/* ATHENV */ +#include +/* ATHENV */ + +#include "ar6000_drv.h" +#include "htc.h" +#include "engine.h" +#include "wmi_filter_linux.h" + +#define IS_MAC_NULL(mac) (mac[0]==0 && mac[1]==0 && mac[2]==0 && mac[3]==0 && mac[4]==0 && mac[5]==0) + +MODULE_LICENSE("GPL and additional rights"); + +#ifndef REORG_APTC_HEURISTICS +#undef ADAPTIVE_POWER_THROUGHPUT_CONTROL +#endif /* REORG_APTC_HEURISTICS */ + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +#define APTC_TRAFFIC_SAMPLING_INTERVAL 100 /* msec */ +#define APTC_UPPER_THROUGHPUT_THRESHOLD 3000 /* Kbps */ +#define APTC_LOWER_THROUGHPUT_THRESHOLD 2000 /* Kbps */ + +typedef struct aptc_traffic_record { + A_BOOL timerScheduled; + struct timeval samplingTS; + unsigned long bytesReceived; + unsigned long bytesTransmitted; +} APTC_TRAFFIC_RECORD; + +A_TIMER aptcTimer; +APTC_TRAFFIC_RECORD aptcTR; +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +unsigned int processDot11Hdr = 0; +/* ATHENV */ +#ifdef ANDROID_ENV +int bmienable = 1; +#else +int bmienable = 0; +#endif +/* ATHENV */ + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +char ifname[IFNAMSIZ] = {0,}; +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) */ + +int fwloadenable = 0; +unsigned int bypasswmi = 0; +unsigned int debuglevel = 0; +int tspecCompliance = ATHEROS_COMPLIANCE; +unsigned int busspeedlow = 0; +unsigned int onebitmode = 0; +unsigned int skipflash = 0; +unsigned int wmitimeout = 2; +unsigned int wlanNodeCaching = 1; +unsigned int enableuartprint = 0; +unsigned int logWmiRawMsgs = 0; +unsigned int enabletimerwar = 0; +unsigned int fwmode = 1; +unsigned int mbox_yield_limit = 99; +int reduce_credit_dribble = 1 + HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF; +int allow_trace_signal = 0; +/* ATHENV */ +#ifdef ANDROID_ENV +int work_mode = 0; +char *tgt_fw = "/system/wifi/athwlan.bin.z77"; +char *tgt_patch = "/system/wifi/data.patch.hw2_0.bin"; +char *tcmd_fw = "/system/wifi/athtcmd_ram.bin"; +static char *art_fw = "/system/wifi/device.bin"; +char *eeprom_bin = "/system/wifi/eeprom.bin"; +#ifdef FAKE_EEPROM_USED +char *eeprom_data = "/system/wifi/fakeBoardData_AR6002.bin"; +#else +char *eeprom_data = "/system/wifi/eeprom.data"; +#endif +#endif /* ANDROID_ENV */ +/* ATHENV */ +#ifdef CONFIG_HOST_TCMD_SUPPORT +unsigned int testmode =0; +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param_string(ifname, ifname, sizeof(ifname), 0644); +module_param(fwloadenable, int, 0644); +module_param(bmienable, int, 0644); +module_param(bypasswmi, int, 0644); +module_param(debuglevel, int, 0644); +module_param(tspecCompliance, int, 0644); +module_param(onebitmode, int, 0644); +module_param(busspeedlow, int, 0644); +module_param(skipflash, int, 0644); +module_param(wmitimeout, int, 0644); +module_param(wlanNodeCaching, int, 0644); +module_param(logWmiRawMsgs, int, 0644); +module_param(enableuartprint, int, 0644); +module_param(enabletimerwar, int, 0644); +module_param(fwmode, int, 0644); +module_param(mbox_yield_limit, int, 0644); +module_param(reduce_credit_dribble, int, 0644); +module_param(allow_trace_signal, int, 0644); +module_param(processDot11Hdr, int, 0644); +/* ATHENV */ +#ifdef ANDROID_ENV +module_param(work_mode, int, 0644); +module_param(tgt_fw, charp, S_IRUGO); +module_param(tgt_patch, charp, S_IRUGO); +module_param(eeprom_bin, charp, S_IRUGO); +module_param(eeprom_data, charp, S_IRUGO); +#endif +/* ATHENV */ +#ifdef CONFIG_HOST_TCMD_SUPPORT +module_param(testmode, int, 0644); +#endif +#else + +#define __user +/* for linux 2.4 and lower */ +MODULE_PARM(bmienable,"i"); +MODULE_PARM(fwloadenable,"i"); +MODULE_PARM(bypasswmi,"i"); +MODULE_PARM(debuglevel, "i"); +MODULE_PARM(onebitmode,"i"); +MODULE_PARM(busspeedlow, "i"); +MODULE_PARM(skipflash, "i"); +MODULE_PARM(wmitimeout, "i"); +MODULE_PARM(wlanNodeCaching, "i"); +MODULE_PARM(enableuartprint,"i"); +MODULE_PARM(logWmiRawMsgs, "i"); +MODULE_PARM(enabletimerwar,"i"); +MODULE_PARM(fwmode,"i"); +MODULE_PARM(mbox_yield_limit,"i"); +MODULE_PARM(reduce_credit_dribble,"i"); +MODULE_PARM(allow_trace_signal,"i"); +MODULE_PARM(processDot11Hdr,"i"); +#ifdef CONFIG_HOST_TCMD_SUPPORT +MODULE_PARM(testmode, "i"); +#endif +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10) +/* in 2.6.10 and later this is now a pointer to a uint */ +unsigned int _mboxnum = HTC_MAILBOX_NUM_MAX; +#define mboxnum &_mboxnum +#else +unsigned int mboxnum = HTC_MAILBOX_NUM_MAX; +#endif + +#ifdef DEBUG +A_UINT32 g_dbg_flags = DBG_DEFAULTS; +unsigned int debugflags = 0; +int debugdriver = 1; +unsigned int debughtc = 128; +unsigned int debugbmi = 1; +unsigned int debughif = 2; +unsigned int txcreditsavailable[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int txcreditsconsumed[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int txcreditintrenable[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int txcreditintrenableaggregate[HTC_MAILBOX_NUM_MAX] = {0}; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param(debugflags, int, 0644); +module_param(debugdriver, int, 0644); +module_param(debughtc, int, 0644); +module_param(debugbmi, int, 0644); +module_param(debughif, int, 0644); +module_param_array(txcreditsavailable, int, mboxnum, 0644); +module_param_array(txcreditsconsumed, int, mboxnum, 0644); +module_param_array(txcreditintrenable, int, mboxnum, 0644); +module_param_array(txcreditintrenableaggregate, int, mboxnum, 0644); +#else +/* linux 2.4 and lower */ +MODULE_PARM(debugflags,"i"); +MODULE_PARM(debugdriver, "i"); +MODULE_PARM(debughtc, "i"); +MODULE_PARM(debugbmi, "i"); +MODULE_PARM(debughif, "i"); +MODULE_PARM(txcreditsavailable, "0-3i"); +MODULE_PARM(txcreditsconsumed, "0-3i"); +MODULE_PARM(txcreditintrenable, "0-3i"); +MODULE_PARM(txcreditintrenableaggregate, "0-3i"); +#endif + +#endif /* DEBUG */ + +unsigned int resetok = 1; +unsigned int tx_attempt[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int tx_post[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int tx_complete[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int hifBusRequestNumMax = 40; +unsigned int war23838_disabled = 0; +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +unsigned int enableAPTCHeuristics = 1; +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param_array(tx_attempt, int, mboxnum, 0644); +module_param_array(tx_post, int, mboxnum, 0644); +module_param_array(tx_complete, int, mboxnum, 0644); +module_param(hifBusRequestNumMax, int, 0644); +module_param(war23838_disabled, int, 0644); +module_param(resetok, int, 0644); +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +module_param(enableAPTCHeuristics, int, 0644); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ +#else +MODULE_PARM(tx_attempt, "0-3i"); +MODULE_PARM(tx_post, "0-3i"); +MODULE_PARM(tx_complete, "0-3i"); +MODULE_PARM(hifBusRequestNumMax, "i"); +MODULE_PARM(war23838_disabled, "i"); +MODULE_PARM(resetok, "i"); +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +MODULE_PARM(enableAPTCHeuristics, "i"); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ +#endif + +#ifdef BLOCK_TX_PATH_FLAG +int blocktx = 0; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param(blocktx, int, 0644); +#else +MODULE_PARM(blocktx, "i"); +#endif +#endif /* BLOCK_TX_PATH_FLAG */ + + +int reconnect_flag = 0; + +/* Function declarations */ +static int ar6000_init_module(void); +static void ar6000_cleanup_module(void); + +int ar6000_init(struct net_device *dev); +static int ar6000_open(struct net_device *dev); +static int ar6000_close(struct net_device *dev); +static void ar6000_init_control_info(AR_SOFTC_T *ar); +static int ar6000_data_tx(struct sk_buff *skb, struct net_device *dev); + +static void ar6000_destroy(struct net_device *dev, unsigned int unregister); +static void ar6000_detect_error(unsigned long ptr); +static struct net_device_stats *ar6000_get_stats(struct net_device *dev); +static struct iw_statistics *ar6000_get_iwstats(struct net_device * dev); + +/* + * HTC service connection handlers + */ +static A_STATUS ar6000_avail_ev(void *context, void *hif_handle); + +static A_STATUS ar6000_unavail_ev(void *context, void *hif_handle); + +static void ar6000_target_failure(void *Instance, A_STATUS Status); + +static void ar6000_rx(void *Context, HTC_PACKET *pPacket); + +static void ar6000_rx_refill(void *Context,HTC_ENDPOINT_ID Endpoint); + +static void ar6000_tx_complete(void *Context, HTC_PACKET *pPacket); + +static HTC_SEND_FULL_ACTION ar6000_tx_queue_full(void *Context, HTC_PACKET *pPacket); + +static void deliver_frames_to_nw_stack(struct sk_buff *skb); + +/* + * Static variables + */ + +static struct net_device *ar6000_devices[MAX_AR6000]; +extern struct iw_handler_def ath_iw_handler_def; +DECLARE_WAIT_QUEUE_HEAD(arEvent); +DECLARE_WAIT_QUEUE_HEAD(ar6000_scan_queue); +static void ar6000_cookie_init(AR_SOFTC_T *ar); +static void ar6000_cookie_cleanup(AR_SOFTC_T *ar); +static void ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie); +static struct ar_cookie *ar6000_alloc_cookie(AR_SOFTC_T *ar); + +#ifdef USER_KEYS +static A_STATUS ar6000_reinstall_keys(AR_SOFTC_T *ar,A_UINT8 key_op_ctrl); +#endif + + +static struct ar_cookie s_ar_cookie_mem[MAX_COOKIE_NUM]; + +#define HOST_INTEREST_ITEM_ADDRESS(ar, item) \ + (((ar)->arTargetType == TARGET_TYPE_AR6001) ? AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((ar)->arTargetType == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((ar)->arTargetType == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : 0))) + + +/* Debug log support */ + +/* + * Flag to govern whether the debug logs should be parsed in the kernel + * or reported to the application. + */ +#define REPORT_DEBUG_LOGS_TO_APP + +A_STATUS +ar6000_set_host_app_area(AR_SOFTC_T *ar) +{ + A_UINT32 address, data; + struct host_app_area_s host_app_area; + + /* Fetch the address of the host_app_area_s instance in the host interest area */ + address = TARG_VTOP(ar->arTargetType, HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest)); + if (ar6000_ReadRegDiag(ar->arHifDevice, &address, &data) != A_OK) { + return A_ERROR; + } + address = TARG_VTOP(ar->arTargetType, data); + host_app_area.wmi_protocol_ver = WMI_PROTOCOL_VERSION; + if (ar6000_WriteDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&host_app_area, + sizeof(struct host_app_area_s)) != A_OK) + { + return A_ERROR; + } + + return A_OK; +} + +A_UINT32 +dbglog_get_debug_hdr_ptr(AR_SOFTC_T *ar) +{ + A_UINT32 param; + A_UINT32 address; + A_STATUS status; + + address = TARG_VTOP(ar->arTargetType, HOST_INTEREST_ITEM_ADDRESS(ar, hi_dbglog_hdr)); + if ((status = ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)¶m, 4)) != A_OK) + { + param = 0; + } + + return param; +} + +/* + * The dbglog module has been initialized. Its ok to access the relevant + * data stuctures over the diagnostic window. + */ +void +ar6000_dbglog_init_done(AR_SOFTC_T *ar) +{ + ar->dbglog_init_done = TRUE; +} + +A_UINT32 +dbglog_get_debug_fragment(A_INT8 *datap, A_UINT32 len, A_UINT32 limit) +{ + A_INT32 *buffer; + A_UINT32 count; + A_UINT32 numargs; + A_UINT32 length; + A_UINT32 fraglen; + + count = fraglen = 0; + buffer = (A_INT32 *)datap; + length = (limit >> 2); + + if (len <= limit) { + fraglen = len; + } else { + while (count < length) { + numargs = DBGLOG_GET_NUMARGS(buffer[count]); + fraglen = (count << 2); + count += numargs + 1; + } + } + + return fraglen; +} + +void +dbglog_parse_debug_logs(A_INT8 *datap, A_UINT32 len) +{ + A_INT32 *buffer; + A_UINT32 count; + A_UINT32 timestamp; + A_UINT32 debugid; + A_UINT32 moduleid; + A_UINT32 numargs; + A_UINT32 length; + + count = 0; + buffer = (A_INT32 *)datap; + length = (len >> 2); + while (count < length) { + debugid = DBGLOG_GET_DBGID(buffer[count]); + moduleid = DBGLOG_GET_MODULEID(buffer[count]); + numargs = DBGLOG_GET_NUMARGS(buffer[count]); + timestamp = DBGLOG_GET_TIMESTAMP(buffer[count]); + switch (numargs) { + case 0: + AR_DEBUG_PRINTF("%d %d (%d)\n", moduleid, debugid, timestamp); + break; + + case 1: + AR_DEBUG_PRINTF("%d %d (%d): 0x%x\n", moduleid, debugid, + timestamp, buffer[count+1]); + break; + + case 2: + AR_DEBUG_PRINTF("%d %d (%d): 0x%x, 0x%x\n", moduleid, debugid, + timestamp, buffer[count+1], buffer[count+2]); + break; + + default: + AR_DEBUG_PRINTF("Invalid args: %d\n", numargs); + } + count += numargs + 1; + } +} + +int +ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar) +{ + struct dbglog_hdr_s debug_hdr; + struct dbglog_buf_s debug_buf; + A_UINT32 address; + A_UINT32 length; + A_UINT32 dropped; + A_UINT32 firstbuf; + A_UINT32 debug_hdr_ptr; + + if (!ar->dbglog_init_done) return A_ERROR; + + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + if (ar->dbgLogFetchInProgress) { + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + return A_EBUSY; + } + + /* block out others */ + ar->dbgLogFetchInProgress = TRUE; + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + debug_hdr_ptr = dbglog_get_debug_hdr_ptr(ar); + printk("debug_hdr_ptr: 0x%x\n", debug_hdr_ptr); + + /* Get the contents of the ring buffer */ + if (debug_hdr_ptr) { + address = TARG_VTOP(ar->arTargetType, debug_hdr_ptr); + length = sizeof(struct dbglog_hdr_s); + ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&debug_hdr, length); + address = TARG_VTOP(ar->arTargetType, (A_UINT32)debug_hdr.dbuf); + firstbuf = address; + dropped = debug_hdr.dropped; + length = sizeof(struct dbglog_buf_s); + ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&debug_buf, length); + + do { + address = TARG_VTOP(ar->arTargetType, (A_UINT32)debug_buf.buffer); + length = debug_buf.length; + if ((length) && (debug_buf.length <= debug_buf.bufsize)) { + /* Rewind the index if it is about to overrun the buffer */ + if (ar->log_cnt > (DBGLOG_HOST_LOG_BUFFER_SIZE - length)) { + ar->log_cnt = 0; + } + if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&ar->log_buffer[ar->log_cnt], length)) + { + break; + } + ar6000_dbglog_event(ar, dropped, &ar->log_buffer[ar->log_cnt], length); + ar->log_cnt += length; + } else { + AR_DEBUG_PRINTF("Length: %d (Total size: %d)\n", + debug_buf.length, debug_buf.bufsize); + } + + address = TARG_VTOP(ar->arTargetType, (A_UINT32)debug_buf.next); + length = sizeof(struct dbglog_buf_s); + if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&debug_buf, length)) + { + break; + } + + } while (address != firstbuf); + } + + ar->dbgLogFetchInProgress = FALSE; + + return A_OK; +} + +void +ar6000_dbglog_event(AR_SOFTC_T *ar, A_UINT32 dropped, + A_INT8 *buffer, A_UINT32 length) +{ +#ifdef REPORT_DEBUG_LOGS_TO_APP + #define MAX_WIRELESS_EVENT_SIZE 252 + /* + * Break it up into chunks of MAX_WIRELESS_EVENT_SIZE bytes of messages. + * There seems to be a limitation on the length of message that could be + * transmitted to the user app via this mechanism. + */ + A_UINT32 send, sent; + + sent = 0; + send = dbglog_get_debug_fragment(&buffer[sent], length - sent, + MAX_WIRELESS_EVENT_SIZE); + while (send) { + ar6000_send_event_to_app(ar, WMIX_DBGLOG_EVENTID, &buffer[sent], send); + sent += send; + send = dbglog_get_debug_fragment(&buffer[sent], length - sent, + MAX_WIRELESS_EVENT_SIZE); + } +#else + AR_DEBUG_PRINTF("Dropped logs: 0x%x\nDebug info length: %d\n", + dropped, length); + + /* Interpret the debug logs */ + dbglog_parse_debug_logs(buffer, length); +#endif /* REPORT_DEBUG_LOGS_TO_APP */ +} + + + +static int __init +ar6000_init_module(void) +{ + static int probed = 0; + A_STATUS status; + OSDRV_CALLBACKS osdrvCallbacks; + +/* ATHENV */ +#ifdef ANDROID_ENV + if (work_mode == 1) { + printk("TCMD mode.\n"); + testmode = 1; + tgt_fw = tcmd_fw; + } else if (work_mode == 2) { + printk("ART mode.\n"); + enableuartprint = 1; + resetok = 0; + bypasswmi = 1; + tgt_fw = art_fw; + } else { + printk("Normal WIFI mode.\n"); + } +#endif +/* ATHENV */ + + A_MEMZERO(&osdrvCallbacks,sizeof(osdrvCallbacks)); + osdrvCallbacks.deviceInsertedHandler = ar6000_avail_ev; + osdrvCallbacks.deviceRemovedHandler = ar6000_unavail_ev; + +#ifdef DEBUG + /* Set the debug flags if specified at load time */ + if(debugflags != 0) + { + g_dbg_flags = debugflags; + } +#endif + + if (probed) { + return -ENODEV; + } + probed++; + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + memset(&aptcTR, 0, sizeof(APTC_TRAFFIC_RECORD)); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +#ifdef CONFIG_HOST_GPIO_SUPPORT + ar6000_gpio_init(); +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + + status = HIFInit(&osdrvCallbacks); + if(status != A_OK) + return -ENODEV; + + return 0; +} + +static void __exit +ar6000_cleanup_module(void) +{ + int i = 0; + struct net_device *ar6000_netdev; + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + /* Delete the Adaptive Power Control timer */ + if (timer_pending(&aptcTimer)) { + del_timer_sync(&aptcTimer); + } +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + + for (i=0; i < MAX_AR6000; i++) { + if (ar6000_devices[i] != NULL) { + ar6000_netdev = ar6000_devices[i]; + ar6000_devices[i] = NULL; + ar6000_destroy(ar6000_netdev, 1); + } + } + + HIFShutDownDevice(NULL); + + AR_DEBUG_PRINTF("ar6000_cleanup: success\n"); +} + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +void +aptcTimerHandler(unsigned long arg) +{ + A_UINT32 numbytes; + A_UINT32 throughput; + AR_SOFTC_T *ar; + A_STATUS status; + + ar = (AR_SOFTC_T *)arg; + A_ASSERT(ar != NULL); + A_ASSERT(!timer_pending(&aptcTimer)); + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + /* Get the number of bytes transferred */ + numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived; + aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0; + + /* Calculate and decide based on throughput thresholds */ + throughput = ((numbytes * 8)/APTC_TRAFFIC_SAMPLING_INTERVAL); /* Kbps */ + if (throughput < APTC_LOWER_THROUGHPUT_THRESHOLD) { + /* Enable Sleep and delete the timer */ + A_ASSERT(ar->arWmiReady == TRUE); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + status = wmi_powermode_cmd(ar->arWmi, REC_POWER); + AR6000_SPIN_LOCK(&ar->arLock, 0); + A_ASSERT(status == A_OK); + aptcTR.timerScheduled = FALSE; + } else { + A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0); + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); +} +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +/* ATHENV */ + +/* ATHENV */ +#ifdef ANDROID_ENV +extern void eeprom_ar6000_transfer(HIF_DEVICE *device, char *fake_file); +#endif +/* ATHENV */ + +#define MAX_BUF (8*1024) +/* #define A_ROUND_UP(x, y) ((((x)+((y)-1))/(y))*(y)) */ /* already defined in wmi_api.h */ + +/* ATHENV */ +#ifdef ANDROID_ENV +char * fw_buf; +static void firmware_transfer(HIF_DEVICE *device, char* filename, A_UINT32 address, A_BOOL isCompressed) +{ + struct file *filp; + struct inode *inode = NULL; + int length, remaining; + int length1; + A_STATUS ret; + mm_segment_t oldfs; + + + printk("%s: Enter, filename=%s\n", __FUNCTION__, filename); + + // Open file + oldfs = get_fs(); + set_fs(KERNEL_DS); + + filp = filp_open(filename, O_RDONLY, S_IRUSR); + if ( IS_ERR(filp) ) { + printk("%s: file %s filp_open error\n", __FUNCTION__, filename); + return; + } + if (!filp->f_op) { + printk("%s: File Operation Method Error\n", __FUNCTION__); + return; + } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + inode = filp->f_path.dentry->d_inode; +#else + inode = flip->dentry->d_inode; +#endif + + if (!inode) { + printk("%s: Get inode from filp failed\n", __FUNCTION__); + filp_close(filp, NULL); + return; + } + + printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos); + + fw_buf = (char*)kmalloc((MAX_BUF+12), GFP_KERNEL); + if (fw_buf==NULL) { + printk("%s: kernel memory alloc error\n", __FUNCTION__); + filp_close(filp, NULL); + return; + } + + length = i_size_read(inode->i_mapping->host); + if (length==0 ) { + printk("%s: Try to get file size error\n", __FUNCTION__); + goto Transfer_DONE; + } + printk("%s: length=%d, address=0x%x\n", __FUNCTION__, length, address); + + if ( isCompressed) { + ret = BMILZStreamStart(device, address); + if (ret != A_OK) { + printk("%s: BMILZStreamStart failed, ret=%d\n", __FUNCTION__, ret); + goto Transfer_DONE; + } + } + + remaining = length; + + while (remaining>0) { + length = (remaining > MAX_BUF)? MAX_BUF : remaining; + + if ( isCompressed ) { + ((A_UINT32 *)fw_buf)[((length-1)/4)] = 0; + } + + if (filp->f_op->read(filp, fw_buf, length, &filp->f_pos) != length) { + printk("%s: file read error, remaining=%d\n", __FUNCTION__, remaining); + goto Transfer_DONE; + } + + length1 = A_ROUND_UP(length, 4); + + if ( isCompressed ) { + printk("%s: BMILZData: len=%d, org_len=%d\n", __FUNCTION__, length1, length); + ret = BMILZData(device, fw_buf, length1); + if (ret != A_OK) { + printk("%s: BMILZData failed, ret=%d\n", __FUNCTION__, ret); + goto Transfer_DONE; + } + } else { + ret = BMIWriteMemory(device, address, fw_buf, length1); + if (ret != A_OK) { + printk("%s: BMIWriteMemory failed, ret=%d\n", __FUNCTION__, ret); + goto Transfer_DONE; + } + } + + remaining -= length; + address += length; + } + +Transfer_DONE: + kfree(fw_buf); + filp_close(filp, NULL); + set_fs(oldfs); +} + +#endif +/* ATHENV */ + + +#ifdef FW_AUTOLOAD +extern int fwengine( unsigned char *img, int size, void *ar); +extern int ar6k_reg_preload( int reg, unsigned int value ); + +/* Linux driver dependent utilities for fwengine */ +int load_binary( unsigned int addr, unsigned char *cp, void *arg ) +{ + int size = 0; + int adv = 5; + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + + cp++; + size |= ( *cp & 0xFF ); cp++; + size |= ( *cp & 0xFF ) << 8; cp++; + size |= ( *cp & 0xFF ) << 16; cp++; + size |= ( *cp & 0xFF ) << 24; cp++; + + if (BMIWriteMemory(ar->arHifDevice, addr, cp, size) != A_OK) + return(-1); + + adv += size; + return(adv); +} + +int execute_on_target( unsigned int address, unsigned int parm, void *arg ) +{ + int ret ; + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + ret = BMIExecute(ar->arHifDevice, address, &parm); + + return(ret); +} + +unsigned int get_target_reg( unsigned address, void *arg ) +{ + int ret ; + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + if (BMIReadMemory(ar->arHifDevice, address, (A_UCHAR *)&ret, 4)!= A_OK) { + /* And what am I supposed to do? */; + return( -1 ); + } + return( ret ); + +} + +int write_target_reg( unsigned address, unsigned value, void *arg ) +{ + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + if (BMIWriteMemory(ar->arHifDevice, address, (A_UCHAR *)&value, 4) != A_OK) + return(-1); + return(0); +} + +void bmidone( void *arg ) +{ + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + BMIDone(ar->arHifDevice); +} +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) +static struct device ar6kfwdev = { + .bus_id = "sdio0", +}; +#endif +#endif /* FW_AUTOLOAD */ + +/* + * HTC Event handlers + */ +static A_STATUS +ar6000_avail_ev(void *context, void *hif_handle) +{ + int i; + struct net_device *dev; + void *ar_netif; + AR_SOFTC_T *ar; + int device_index = 0; + A_UINT32 param; + HTC_INIT_INFO htcInfo; + + AR_DEBUG_PRINTF("ar6000_available\n"); + + for (i=0; i < MAX_AR6000; i++) { + if (ar6000_devices[i] == NULL) { + break; + } + } + + if (i == MAX_AR6000) { + AR_DEBUG_PRINTF("ar6000_available: max devices reached\n"); + return A_ERROR; + } + + /* Save this. It gives a bit better readability especially since */ + /* we use another local "i" variable below. */ + device_index = i; +#ifdef CONFIG_MACH_LUIGI_LAB126 + dev = alloc_etherdev_ar6000(sizeof(AR_SOFTC_T)); +#else + dev = alloc_etherdev_(sizeof(AR_SOFTC_T)); +#endif + if (dev == NULL) { + AR_DEBUG_PRINTF("ar6000_available: can't alloc etherdev\n"); + return A_ERROR; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + if (ifname[0]) + { + strcpy(dev->name, ifname); + } +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) */ + +#ifdef SET_MODULE_OWNER + SET_MODULE_OWNER(dev); +#endif + ether_setup(dev); + + ar_netif = netdev_priv(dev); + if (ar_netif == NULL) { + printk(KERN_CRIT "ar6000_available: Could not allocate memory\n"); + return A_ERROR; + } + + A_MEMZERO(ar_netif, sizeof(AR_SOFTC_T)); + + ar = (AR_SOFTC_T *)ar_netif; + ar->arNetDev = dev; + ar->arHifDevice = hif_handle; + ar->arWlanState = WLAN_ENABLED; + ar->arDeviceIndex = device_index; + + A_INIT_TIMER(&ar->arHBChallengeResp.timer, ar6000_detect_error, dev); + ar->arHBChallengeResp.seqNum = 0; + ar->arHBChallengeResp.outstanding = FALSE; + ar->arHBChallengeResp.missCnt = 0; + ar->arHBChallengeResp.frequency = AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT; + ar->arHBChallengeResp.missThres = AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT; + + ar6000_init_control_info(ar); + init_waitqueue_head(&arEvent); + sema_init(&ar->arSem, 1); + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + A_INIT_TIMER(&aptcTimer, aptcTimerHandler, ar); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + + /* + * If requested, perform some magic which requires no cooperation from + * the Target. It causes the Target to ignore flash and execute to the + * OS from ROM. + * + * This is intended to support recovery from a corrupted flash on Targets + * that support flash. + */ + if (skipflash) + { + AR_DEBUG_PRINTF("Skip flash feature not supported\n"); + return A_ERROR; + } + + BMIInit(); + { + struct bmi_target_info targ_info; + + if (BMIGetTargetInfo(ar->arHifDevice, &targ_info) != A_OK) { + return A_ERROR; + } + + ar->arVersion.target_ver = targ_info.target_ver; + ar->arTargetType = targ_info.target_type; + + /* do any target-specific preparation that can be done through BMI */ + if (ar6000_prepare_target(ar->arHifDevice, + targ_info.target_type, + targ_info.target_ver) != A_OK) { + return A_ERROR; + } + + } + + if (enableuartprint) { + param = 1; + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_serial_enable), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for enableuartprint failed \n"); + return A_ERROR; + } + AR_DEBUG_PRINTF("Serial console prints enabled\n"); + } + + /* Tell target which HTC version it is used*/ + param = HTC_PROTOCOL_VERSION; + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for htc version failed \n"); + return A_ERROR; + } + +#ifdef CONFIG_HOST_TCMD_SUPPORT + if(testmode) { + ar->arTargetMode = AR6000_TCMD_MODE; + }else { + ar->arTargetMode = AR6000_WLAN_MODE; + } +#endif + if (enabletimerwar) { + A_UINT32 param; + + if (BMIReadMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIReadMemory for enabletimerwar failed \n"); + return A_ERROR; + } + + param |= HI_OPTION_TIMER_WAR; + + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for enabletimerwar failed \n"); + return A_ERROR; + } + AR_DEBUG_PRINTF("Timer WAR enabled\n"); + } + + /* set the firmware mode to STA/IBSS/AP */ + { + A_UINT32 param; + + if (BMIReadMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIReadMemory for setting fwmode failed \n"); + return A_ERROR; + } + + param |= (fwmode << HI_OPTION_FW_MODE_SHIFT); + + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for setting fwmode failed \n"); + return A_ERROR; + } + AR_DEBUG_PRINTF("Firmware mode set\n"); + } + + if (processDot11Hdr) { + A_UINT32 param; + + if (BMIReadMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIReadMemory for processDot11Hdr failed \n"); + return A_ERROR; + } + + param |= HI_OPTION_RELAY_DOT11_HDR; + + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for processDot11Hdr failed \n"); + return A_ERROR; + } + AR_DEBUG_PRINTF("processDot11Hdr enabled\n"); + } + + + // No need to reserve RAM space for patch as olca/dragon is flash based + if (ar->arTargetType == TARGET_TYPE_AR6001) { + param = 0; + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_end_RAM_reserve_sz), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for hi_end_RAM_reserve_sz failed \n"); + return A_ERROR; + } + } + + + /* since BMIInit is called in the driver layer, we have to set the block + * size here for the target */ + + if (A_FAILED(ar6000_set_htc_params(ar->arHifDevice, + ar->arTargetType, + mbox_yield_limit, + 0 /* use default number of control buffers */ + ))) { + return A_ERROR; + } + + A_MEMZERO(&htcInfo,sizeof(htcInfo)); + htcInfo.pContext = ar; + htcInfo.TargetFailure = ar6000_target_failure; + + printk(KERN_INFO "ar6000_init_module\n"); + + ar->arHtcTarget = HTCCreate(ar->arHifDevice,&htcInfo); + + if (ar->arHtcTarget == NULL) { + return A_ERROR; + } + + spin_lock_init(&ar->arLock); + + /* Don't install the init function if BMI is requested */ + if(!bmienable) + { + dev->init = ar6000_init; + } else { + AR_DEBUG_PRINTF(" BMI enabled \n"); + } + + dev->open = &ar6000_open; + dev->stop = &ar6000_close; + dev->hard_start_xmit = &ar6000_data_tx; + dev->get_stats = &ar6000_get_stats; + + /* dev->tx_timeout = ar6000_tx_timeout; */ + dev->do_ioctl = &ar6000_ioctl; + dev->watchdog_timeo = AR6000_TX_TIMEOUT; + dev->wireless_handlers = &ath_iw_handler_def; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) + dev->get_wireless_stats = ar6000_get_iwstats; /*Displayed via proc fs */ +#else + ath_iw_handler_def.get_wireless_stats = ar6000_get_iwstats; /*Displayed via proc fs */ +#endif + + if (processDot11Hdr) { + dev->hard_header_len = sizeof(struct ieee80211_qosframe) + sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN; + } else { + /* + * We need the OS to provide us with more headroom in order to + * perform dix to 802.3, WMI header encap, and the HTC header + */ + dev->hard_header_len = ETH_HLEN + sizeof(ATH_LLC_SNAP_HDR) + + sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN; + } + + /* This runs the init function */ + if (register_netdev(dev)) { + AR_DEBUG_PRINTF("ar6000_avail: register_netdev failed\n"); + ar6000_destroy(dev, 0); + return A_ERROR; + } + + HIFClaimDevice(ar->arHifDevice, ar); + + /* We only register the device in the global list if we succeed. */ + /* If the device is in the global list, it will be destroyed */ + /* when the module is unloaded. */ + ar6000_devices[device_index] = dev; + + AR_DEBUG_PRINTF("ar6000_avail: name=%s hifdevice=0x%x, dev=0x%x (%d), ar=0x%x\n", + dev->name, (A_UINT32)ar->arHifDevice, (A_UINT32)dev, device_index, + (A_UINT32)ar); +/* ATHENV */ +#ifdef ANDROID_ENV + if (tgt_fw != NULL) { + A_UINT32 value, old_options, old_sleep; + A_STATUS ret; + + /* temporarily disable system sleep */ + value = 0; + BMIReadSOCRegister(ar->arHifDevice, 0x180c0, &value); + old_options = value; + value |= 0x08; + BMIWriteSOCRegister(ar->arHifDevice, 0x180c0, value); + value = 0; + BMIReadSOCRegister(ar->arHifDevice, 0x40c4, &value); + old_sleep = value; + value |= 0x01; + BMIWriteSOCRegister(ar->arHifDevice, 0x40c4, value); + printk("old options [%d] old sleep [%d]\n", old_options, old_sleep); + + /* run at 40/44MHz by default */ + value = 0; + BMIWriteSOCRegister(ar->arHifDevice, 0x4020, value); + + /* use internal clock? */ + BMIReadSOCRegister(ar->arHifDevice, 0x50047c, &value); + if (value == 0) { + printk("use internal clock\n"); + value = 0x100000; + BMIWriteSOCRegister(ar->arHifDevice, 0x40e0, value); + } + + /* eeprom */ +#ifdef FAKE_EEPROM_USED + printk("AR6000: download fake eeprom\n"); + eeprom_ar6000_transfer(ar->arHifDevice, eeprom_data, NULL); +#else + printk("AR6000: eeprom transfer\n"); + firmware_transfer(ar->arHifDevice, eeprom_data, 0x502070, FALSE); + firmware_transfer(ar->arHifDevice, eeprom_bin, 0x5148f0, FALSE); + value = 1; + printk("AR6000: BMIExecute\n"); + BMIExecute(ar->arHifDevice, 0x9148f0, &value); +#endif + printk("AR6000: BMISetAppStart\n"); + BMISetAppStart(ar->arHifDevice, 0x9148f0); + + /* enable HI_OPTION_TIMER_WAR */ + printk("AR6000: enable HI_OPTION_TIMER_WAR\n"); + value = 0; + BMIReadSOCRegister(ar->arHifDevice, 0x500410, &value); + value |= 0x01; + BMIWriteSOCRegister(ar->arHifDevice, 0x500410, value); + + /* fw */ + printk("AR6000: firmware_transfer\n"); + if ((tgt_fw[strlen(tgt_fw) - 3] == 'z') + && (tgt_fw[strlen(tgt_fw) - 2] == '7') + && (tgt_fw[strlen(tgt_fw) - 1] == '7')) { + firmware_transfer(ar->arHifDevice, tgt_fw, 0x502070, TRUE); + } else { + firmware_transfer(ar->arHifDevice, tgt_fw, 0x502070, FALSE); + } + + /* WLAN patch DataSets */ + firmware_transfer(ar->arHifDevice, tgt_patch, 0x52d8b0, FALSE); + BMIWriteSOCRegister(ar->arHifDevice, 0x500418, 0x52d8b0); + + /* restore system sleep */ + BMIWriteSOCRegister(ar->arHifDevice, 0x40c4, old_sleep); + BMIWriteSOCRegister(ar->arHifDevice, 0x180c0, old_options); + + if (work_mode == 2) { + /* art mode */ + BMIWriteSOCRegister(ar->arHifDevice, 0x500478, 26000000); + BMIWriteSOCRegister(ar->arHifDevice, 0x500458, 0x1); + } else { + /* normal WIFI or TCMD mode, done */ + ret = ar6000_init(dev); + if ( ret!= A_OK ) { + printk("%s: ar6000_init failed, ret=%d\n", __FUNCTION__, ret); + } + } + } +#endif +/* ATHENV */ + +#ifdef FW_AUTOLOAD + if( fwloadenable ) { + /* To compile firmware into driver the following struct should + * be declared static, it's field 'data' initialised with ptr to + * image and field 'size' with image size. 'request_firmware call + * in that case should be bypassed. TODO: #ifdef that + */ + const struct firmware *fw_entry; + int ret; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) + if(request_firmware(&fw_entry, "ar6k_firmware", &ar6kfwdev)!=0) { +#else + if(request_firmware(&fw_entry, "ar6k_firmware", &dev->dev)!=0) { +#endif +// if(request_firmware(NULL, "ar6k_firmware", &dev->dev)!=0) { + printk(KERN_ERR "ar6000_fwload: ar6k_firmware not available\n"); + ar6000_destroy(dev, 0); + return A_ERROR; + } else { + ar6k_reg_preload( 14, ar->arTargetType ); + ar6k_reg_preload( 15, ar->arVersion.target_ver ); + ret = fwengine(fw_entry->data, fw_entry->size, (void *)ar); + release_firmware(fw_entry); + if( ret ) { + printk(KERN_ERR "ar600_fwload: error loading firmware\n"); + ar6000_destroy(dev, 0); + return A_ERROR; + } + } + } +#endif /* FW_AUTOLOAD */ + + return A_OK; +} + +static void ar6000_target_failure(void *Instance, A_STATUS Status) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Instance; + WMI_TARGET_ERROR_REPORT_EVENT errEvent; + static A_BOOL sip = FALSE; + + if (Status != A_OK) { + + printk(KERN_ERR "ar6000_target_failure: target asserted \n"); + + if (timer_pending(&ar->arHBChallengeResp.timer)) { + A_UNTIMEOUT(&ar->arHBChallengeResp.timer); + } + + /* try dumping target assertion information (if any) */ + ar6000_dump_target_assert_info(ar->arHifDevice,ar->arTargetType); + + /* + * Fetch the logs from the target via the diagnostic + * window. + */ + ar6000_dbglog_get_debug_logs(ar); + + /* Report the error only once */ + if (!sip) { + sip = TRUE; + errEvent.errorVal = WMI_TARGET_COM_ERR | + WMI_TARGET_FATAL_ERR; + ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID, + (A_UINT8 *)&errEvent, + sizeof(WMI_TARGET_ERROR_REPORT_EVENT)); + } + } +} + +static A_STATUS +ar6000_unavail_ev(void *context, void *hif_handle) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)context; + /* NULL out it's entry in the global list */ + ar6000_devices[ar->arDeviceIndex] = NULL; + ar6000_destroy(ar->arNetDev, 1); + + return A_OK; +} + +/* + * We need to differentiate between the surprise and planned removal of the + * device because of the following consideration: + * - In case of surprise removal, the hcd already frees up the pending + * for the device and hence there is no need to unregister the function + * driver inorder to get these requests. For planned removal, the function + * driver has to explictly unregister itself to have the hcd return all the + * pending requests before the data structures for the devices are freed up. + * Note that as per the current implementation, the function driver will + * end up releasing all the devices since there is no API to selectively + * release a particular device. + * - Certain commands issued to the target can be skipped for surprise + * removal since they will anyway not go through. + */ +static void +ar6000_destroy(struct net_device *dev, unsigned int unregister) +{ + AR_SOFTC_T *ar; + + AR_DEBUG_PRINTF("+ar6000_destroy \n"); + + if((dev == NULL) || ((ar = netdev_priv(dev)) == NULL)) + { + AR_DEBUG_PRINTF("%s(): Failed to get device structure.\n", __func__); + return; + } + + /* Stop the transmit queues */ + netif_stop_queue(dev); + + /* Disable the target and the interrupts associated with it */ + if (ar->arWmiReady == TRUE) + { + if (!bypasswmi) + { + if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) + { + AR_DEBUG_PRINTF("%s(): Disconnect\n", __func__); + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar6000_init_profile_info(ar); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + wmi_disconnect_cmd(ar->arWmi); + } + + ar6000_dbglog_get_debug_logs(ar); + ar->arWmiReady = FALSE; + ar->arConnected = FALSE; + ar->arConnectPending = FALSE; + wmi_shutdown(ar->arWmi); + ar->arWmiEnabled = FALSE; + ar->arWmi = NULL; + ar->arWlanState = WLAN_ENABLED; +#ifdef USER_KEYS + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT; + ar->user_key_ctrl = 0; +#endif + } + + AR_DEBUG_PRINTF("%s(): WMI stopped\n", __func__); + } + else + { + AR_DEBUG_PRINTF("%s(): WMI not ready 0x%08x 0x%08x\n", + __func__, (unsigned int) ar, (unsigned int) ar->arWmi); + + /* Shut down WMI if we have started it */ + if(ar->arWmiEnabled == TRUE) + { + AR_DEBUG_PRINTF("%s(): Shut down WMI\n", __func__); + wmi_shutdown(ar->arWmi); + ar->arWmiEnabled = FALSE; + ar->arWmi = NULL; + } + } + + if (ar->arHtcTarget != NULL) { + AR_DEBUG_PRINTF(" Shuting down HTC .... \n"); + /* stop HTC */ + HTCStop(ar->arHtcTarget); + /* destroy HTC */ + HTCDestroy(ar->arHtcTarget); + } + + if (resetok) { + /* try to reset the device if we can + * The driver may have been configure NOT to reset the target during + * a debug session */ + AR_DEBUG_PRINTF(" Attempting to reset target on instance destroy.... \n"); + if (ar->arHifDevice != NULL) { + ar6000_reset_device(ar->arHifDevice, ar->arTargetType, TRUE); + } + } else { + AR_DEBUG_PRINTF(" Host does not want target reset. \n"); + } + + if (ar->arHifDevice != NULL) { + /*release the device so we do not get called back on remove incase we + * we're explicity destroyed by module unload */ + HIFReleaseDevice(ar->arHifDevice); + HIFShutDownDevice(ar->arHifDevice); + } + + /* Done with cookies */ + ar6000_cookie_cleanup(ar); + + /* Cleanup BMI */ + BMIInit(); + + /* Clear the tx counters */ + memset(tx_attempt, 0, sizeof(tx_attempt)); + memset(tx_post, 0, sizeof(tx_post)); + memset(tx_complete, 0, sizeof(tx_complete)); + + + /* Free up the device data structure */ + if( unregister ) + unregister_netdev(dev); +#ifndef free_netdev + kfree(dev); +#else + free_netdev(dev); +#endif + + AR_DEBUG_PRINTF("-ar6000_destroy \n"); +} + +static void ar6000_detect_error(unsigned long ptr) +{ + struct net_device *dev = (struct net_device *)ptr; + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_TARGET_ERROR_REPORT_EVENT errEvent; + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + if (ar->arHBChallengeResp.outstanding) { + ar->arHBChallengeResp.missCnt++; + } else { + ar->arHBChallengeResp.missCnt = 0; + } + + if (ar->arHBChallengeResp.missCnt > ar->arHBChallengeResp.missThres) { + /* Send Error Detect event to the application layer and do not reschedule the error detection module timer */ + ar->arHBChallengeResp.missCnt = 0; + ar->arHBChallengeResp.seqNum = 0; + errEvent.errorVal = WMI_TARGET_COM_ERR | WMI_TARGET_FATAL_ERR; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID, + (A_UINT8 *)&errEvent, + sizeof(WMI_TARGET_ERROR_REPORT_EVENT)); + return; + } + + /* Generate the sequence number for the next challenge */ + ar->arHBChallengeResp.seqNum++; + ar->arHBChallengeResp.outstanding = TRUE; + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + /* Send the challenge on the control channel */ + if (wmi_get_challenge_resp_cmd(ar->arWmi, ar->arHBChallengeResp.seqNum, DRV_HB_CHALLENGE) != A_OK) { + AR_DEBUG_PRINTF("Unable to send heart beat challenge\n"); + } + + + /* Reschedule the timer for the next challenge */ + A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0); +} + +void ar6000_init_profile_info(AR_SOFTC_T *ar) +{ + ar->arSsidLen = 0; + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + + switch(fwmode) { + case HI_OPTION_FW_MODE_IBSS: + ar->arNetworkType = ar->arNextMode = ADHOC_NETWORK; + break; + case HI_OPTION_FW_MODE_BSS_STA: + ar->arNetworkType = ar->arNextMode = INFRA_NETWORK; + break; + case HI_OPTION_FW_MODE_AP: + ar->arNetworkType = ar->arNextMode = AP_NETWORK; + break; + } + + ar->arDot11AuthMode = OPEN_AUTH; + ar->arAuthMode = NONE_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arPairwiseCryptoLen = 0; + ar->arGroupCrypto = NONE_CRYPT; + ar->arGroupCryptoLen = 0; + A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList)); + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + A_MEMZERO(ar->arBssid, sizeof(ar->arBssid)); + ar->arBssChannel = 0; +} + +static void +ar6000_init_control_info(AR_SOFTC_T *ar) +{ + ar->arWmiEnabled = FALSE; + ar6000_init_profile_info(ar); + ar->arDefTxKeyIndex = 0; + A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList)); + ar->arChannelHint = 0; + ar->arListenInterval = MAX_LISTEN_INTERVAL; + ar->arVersion.host_ver = AR6K_SW_VERSION; + ar->arRssi = 0; + ar->arTxPwr = 0; + ar->arTxPwrSet = FALSE; + ar->arSkipScan = 0; + ar->arBeaconInterval = 0; + ar->arBitRate = 0; + ar->arMaxRetries = 0; + ar->arWmmEnabled = TRUE; + ar->intra_bss = 1; + + /* Initialize the AP mode state info */ + { + A_UINT8 ctr; + A_MEMZERO((A_UINT8 *)ar->sta_list, AP_MAX_NUM_STA * sizeof(sta_t)); + + /* init the Mutexes */ + A_MUTEX_INIT(&ar->mcastpsqLock); + + /* Init the PS queues */ + for (ctr=0; ctr < AP_MAX_NUM_STA ; ctr++) { + A_MUTEX_INIT(&ar->sta_list[ctr].psqLock); + A_NETBUF_QUEUE_INIT(&ar->sta_list[ctr].psq); + } + + ar->ap_profile_flag = 0; + A_NETBUF_QUEUE_INIT(&ar->mcastpsq); + } +} + +static int +ar6000_open(struct net_device *dev) +{ + unsigned long flags; + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + spin_lock_irqsave(&ar->arLock, flags); + if( ar->arConnected || bypasswmi) { + netif_carrier_on(dev); + /* Wake up the queues */ + netif_wake_queue(dev); + } + else + netif_carrier_off(dev); + + spin_unlock_irqrestore(&ar->arLock, flags); + return 0; +} + +static int +ar6000_close(struct net_device *dev) +{ + netif_stop_queue(dev); + + return 0; +} + +/* connect to a service */ +static A_STATUS ar6000_connectservice(AR_SOFTC_T *ar, + HTC_SERVICE_CONNECT_REQ *pConnect, + char *pDesc) +{ + A_STATUS status; + HTC_SERVICE_CONNECT_RESP response; + + do { + + A_MEMZERO(&response,sizeof(response)); + + status = HTCConnectService(ar->arHtcTarget, + pConnect, + &response); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(" Failed to connect to %s service status:%d \n", + pDesc, status); + break; + } + switch (pConnect->ServiceID) { + case WMI_CONTROL_SVC : + if (ar->arWmiEnabled) { + /* set control endpoint for WMI use */ + wmi_set_control_ep(ar->arWmi, response.Endpoint); + } + /* save EP for fast lookup */ + ar->arControlEp = response.Endpoint; + break; + case WMI_DATA_BE_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_BE, response.Endpoint); + break; + case WMI_DATA_BK_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_BK, response.Endpoint); + break; + case WMI_DATA_VI_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_VI, response.Endpoint); + break; + case WMI_DATA_VO_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_VO, response.Endpoint); + break; + default: + AR_DEBUG_PRINTF("ServiceID not mapped %d\n", pConnect->ServiceID); + status = A_EINVAL; + break; + } + + } while (FALSE); + + return status; +} + +void ar6000_TxDataCleanup(AR_SOFTC_T *ar) +{ + /* flush all the data (non-control) streams + * we only flush packets that are tagged as data, we leave any control packets that + * were in the TX queues alone */ + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_BE), + AR6K_DATA_PKT_TAG); + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_BK), + AR6K_DATA_PKT_TAG); + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_VI), + AR6K_DATA_PKT_TAG); + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_VO), + AR6K_DATA_PKT_TAG); +} + +HTC_ENDPOINT_ID +ar6000_ac2_endpoint_id ( void * devt, A_UINT8 ac) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *) devt; + return(arAc2EndpointID(ar, ac)); +} + +A_UINT8 +ar6000_endpoint_id2_ac(void * devt, HTC_ENDPOINT_ID ep ) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *) devt; + return(arEndpoint2Ac(ar, ep )); +} + +/* This function does one time initialization for the lifetime of the device */ +int ar6000_init(struct net_device *dev) +{ + AR_SOFTC_T *ar; + A_STATUS status; + A_INT32 timeleft; + + if((ar = netdev_priv(dev)) == NULL) + { + return(-EIO); + } + + /* Do we need to finish the BMI phase */ + if(BMIDone(ar->arHifDevice) != A_OK) + { + return -EIO; + } + + if (!bypasswmi) + { +#if 0 /* TBDXXX */ + if (ar->arVersion.host_ver != ar->arVersion.target_ver) { + A_PRINTF("WARNING: Host version 0x%x does not match Target " + " version 0x%x!\n", + ar->arVersion.host_ver, ar->arVersion.target_ver); + } +#endif + + /* Indicate that WMI is enabled (although not ready yet) */ + ar->arWmiEnabled = TRUE; + if ((ar->arWmi = wmi_init((void *) ar)) == NULL) + { + AR_DEBUG_PRINTF("%s() Failed to initialize WMI.\n", __func__); + return(-EIO); + } + + AR_DEBUG_PRINTF("%s() Got WMI @ 0x%08x.\n", __func__, + (unsigned int) ar->arWmi); + } + + do { + HTC_SERVICE_CONNECT_REQ connect; + + /* the reason we have to wait for the target here is that the driver layer + * has to init BMI in order to set the host block size, + */ + status = HTCWaitTarget(ar->arHtcTarget); + + if (A_FAILED(status)) { + break; + } + + A_MEMZERO(&connect,sizeof(connect)); + /* meta data is unused for now */ + connect.pMetaData = NULL; + connect.MetaDataLength = 0; + /* these fields are the same for all service endpoints */ + connect.EpCallbacks.pContext = ar; + connect.EpCallbacks.EpTxComplete = ar6000_tx_complete; + connect.EpCallbacks.EpRecv = ar6000_rx; + connect.EpCallbacks.EpRecvRefill = ar6000_rx_refill; + connect.EpCallbacks.EpSendFull = ar6000_tx_queue_full; + /* set the max queue depth so that our ar6000_tx_queue_full handler gets called. + * Linux has the peculiarity of not providing flow control between the + * NIC and the network stack. There is no API to indicate that a TX packet + * was sent which could provide some back pressure to the network stack. + * Under linux you would have to wait till the network stack consumed all sk_buffs + * before any back-flow kicked in. Which isn't very friendly. + * So we have to manage this ourselves */ + connect.MaxSendQueueDepth = 32; + + /* connect to control service */ + connect.ServiceID = WMI_CONTROL_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI CONTROL"); + if (A_FAILED(status)) { + break; + } + + /* for the remaining data services set the connection flag to reduce dribbling, + * if configured to do so */ + if (reduce_credit_dribble) { + connect.ConnectionFlags |= HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE; + /* the credit dribble trigger threshold is (reduce_credit_dribble - 1) for a value + * of 0-3 */ + connect.ConnectionFlags &= ~HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK; + connect.ConnectionFlags |= + ((A_UINT16)reduce_credit_dribble - 1) & HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK; + } + /* connect to best-effort service */ + connect.ServiceID = WMI_DATA_BE_SVC; + + status = ar6000_connectservice(ar, + &connect, + "WMI DATA BE"); + if (A_FAILED(status)) { + break; + } + + /* connect to back-ground + * map this to WMI LOW_PRI */ + connect.ServiceID = WMI_DATA_BK_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI DATA BK"); + if (A_FAILED(status)) { + break; + } + + /* connect to Video service, map this to + * to HI PRI */ + connect.ServiceID = WMI_DATA_VI_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI DATA VI"); + if (A_FAILED(status)) { + break; + } + + /* connect to VO service, this is currently not + * mapped to a WMI priority stream due to historical reasons. + * WMI originally defined 3 priorities over 3 mailboxes + * We can change this when WMI is reworked so that priorities are not + * dependent on mailboxes */ + connect.ServiceID = WMI_DATA_VO_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI DATA VO"); + if (A_FAILED(status)) { + break; + } + + A_ASSERT(arAc2EndpointID(ar,WMM_AC_BE) != 0); + A_ASSERT(arAc2EndpointID(ar,WMM_AC_BK) != 0); + A_ASSERT(arAc2EndpointID(ar,WMM_AC_VI) != 0); + A_ASSERT(arAc2EndpointID(ar,WMM_AC_VO) != 0); + + /* setup access class priority mappings */ + ar->arAcStreamPriMap[WMM_AC_BK] = 0; /* lowest */ + ar->arAcStreamPriMap[WMM_AC_BE] = 1; /* */ + ar->arAcStreamPriMap[WMM_AC_VI] = 2; /* */ + ar->arAcStreamPriMap[WMM_AC_VO] = 3; /* highest */ + + } while (FALSE); + + if (A_FAILED(status)) { + return (-EIO); + } + + /* + * give our connected endpoints some buffers + */ + + ar6000_rx_refill(ar, ar->arControlEp); + ar6000_rx_refill(ar, arAc2EndpointID(ar,WMM_AC_BE)); + + /* + * We will post the receive buffers only for SPE or endpoint ping testing so we are + * making it conditional on the 'bypasswmi' flag. + */ + if (bypasswmi) { + ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_BK)); + ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_VI)); + ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_VO)); + } + + /* setup credit distribution */ + ar6000_setup_credit_dist(ar->arHtcTarget, &ar->arCreditStateInfo); + + /* Since cookies are used for HTC transports, they should be */ + /* initialized prior to enabling HTC. */ + ar6000_cookie_init(ar); + + /* start HTC */ + status = HTCStart(ar->arHtcTarget); + + if (status != A_OK) { + if (ar->arWmiEnabled == TRUE) { + wmi_shutdown(ar->arWmi); + ar->arWmiEnabled = FALSE; + ar->arWmi = NULL; + } + ar6000_cookie_cleanup(ar); + return -EIO; + } + + if (!bypasswmi) { + /* Wait for Wmi event to be ready */ + timeleft = wait_event_interruptible_timeout(arEvent, + (ar->arWmiReady == TRUE), wmitimeout * HZ); + + if(!timeleft || signal_pending(current)) + { + AR_DEBUG_PRINTF("WMI is not ready or wait was interrupted\n"); + return -EIO; + } + + AR_DEBUG_PRINTF("%s() WMI is ready\n", __func__); + + /* Communicate the wmi protocol verision to the target */ + if ((ar6000_set_host_app_area(ar)) != A_OK) { + AR_DEBUG_PRINTF("Unable to set the host app area\n"); + } + } + + ar->arNumDataEndPts = 1; + + if (bypasswmi) { + /* for tests like endpoint ping, the MAC address needs to be non-zero otherwise + * the data path through a raw socket is disabled */ + dev->dev_addr[0] = 0x00; + dev->dev_addr[1] = 0x01; + dev->dev_addr[2] = 0x02; + dev->dev_addr[3] = 0xAA; + dev->dev_addr[4] = 0xBB; + dev->dev_addr[5] = 0xCC; + } + + return(0); +} + + +void +ar6000_bitrate_rx(void *devt, A_INT32 rateKbps) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arBitRate = rateKbps; + wake_up(&arEvent); +} + +void +ar6000_ratemask_rx(void *devt, A_UINT16 ratemask) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arRateMask = ratemask; + wake_up(&arEvent); +} + +void +ar6000_txPwr_rx(void *devt, A_UINT8 txPwr) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arTxPwr = txPwr; + wake_up(&arEvent); +} + + +void +ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + A_MEMCPY(ar->arChannelList, chanList, numChan * sizeof (A_UINT16)); + ar->arNumChannels = numChan; + + wake_up(&arEvent); +} + +A_UINT8 +ar6000_ibss_map_epid(struct sk_buff *skb, struct net_device *dev, A_UINT32 * mapNo) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_UINT8 *datap; + ATH_MAC_HDR *macHdr; + A_UINT32 i, eptMap; + + (*mapNo) = 0; + datap = A_NETBUF_DATA(skb); + macHdr = (ATH_MAC_HDR *)(datap + sizeof(WMI_DATA_HDR)); + if (IEEE80211_IS_MULTICAST(macHdr->dstMac)) { + return ENDPOINT_2; + } + + eptMap = -1; + for (i = 0; i < ar->arNodeNum; i ++) { + if (IEEE80211_ADDR_EQ(macHdr->dstMac, ar->arNodeMap[i].macAddress)) { + (*mapNo) = i + 1; + ar->arNodeMap[i].txPending ++; + return ar->arNodeMap[i].epId; + } + + if ((eptMap == -1) && !ar->arNodeMap[i].txPending) { + eptMap = i; + } + } + + if (eptMap == -1) { + eptMap = ar->arNodeNum; + ar->arNodeNum ++; + A_ASSERT(ar->arNodeNum <= MAX_NODE_NUM); + } + + A_MEMCPY(ar->arNodeMap[eptMap].macAddress, macHdr->dstMac, IEEE80211_ADDR_LEN); + + for (i = ENDPOINT_2; i <= ENDPOINT_5; i ++) { + if (!ar->arTxPending[i]) { + ar->arNodeMap[eptMap].epId = i; + break; + } + // No free endpoint is available, start redistribution on the inuse endpoints. + if (i == ENDPOINT_5) { + ar->arNodeMap[eptMap].epId = ar->arNexEpId; + ar->arNexEpId ++; + if (ar->arNexEpId > ENDPOINT_5) { + ar->arNexEpId = ENDPOINT_2; + } + } + } + + (*mapNo) = eptMap + 1; + ar->arNodeMap[eptMap].txPending ++; + + return ar->arNodeMap[eptMap].epId; +} + +#ifdef DEBUG +static void ar6000_dump_skb(struct sk_buff *skb) +{ + u_char *ch; + for (ch = A_NETBUF_DATA(skb); + (A_UINT32)ch < ((A_UINT32)A_NETBUF_DATA(skb) + + A_NETBUF_LEN(skb)); ch++) + { + AR_DEBUG_PRINTF("%2.2x ", *ch); + } + AR_DEBUG_PRINTF("\n"); +} +#endif + +static int +ar6000_data_tx(struct sk_buff *skb, struct net_device *dev) +{ +#define AC_NOT_MAPPED 99 + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_UINT8 ac = AC_NOT_MAPPED; + HTC_ENDPOINT_ID eid = ENDPOINT_UNUSED; + A_UINT32 mapNo = 0; + int len; + struct ar_cookie *cookie; + A_BOOL checkAdHocPsMapping = FALSE,bMoreData = FALSE; + +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,13) + skb->list = NULL; +#endif + + AR_DEBUG2_PRINTF("ar6000_data_tx start - skb=0x%x, data=0x%x, len=0x%x\n", + (A_UINT32)skb, (A_UINT32)A_NETBUF_DATA(skb), + A_NETBUF_LEN(skb)); + + /* If target is not associated */ + if( (!ar->arConnected && !bypasswmi) +#ifdef CONFIG_HOST_TCMD_SUPPORT + /* TCMD doesnt support any data, free the buf and return */ + || (ar->arTargetMode == AR6000_TCMD_MODE) +#endif + ) { + A_NETBUF_FREE(skb); + return 0; + } + + do { + + if (ar->arWmiReady == FALSE && bypasswmi == 0) { + break; + } + +#ifdef BLOCK_TX_PATH_FLAG + if (blocktx) { + break; + } +#endif /* BLOCK_TX_PATH_FLAG */ + + /* AP mode Power save processing */ + /* If the dst STA is in sleep state, queue the pkt in its PS queue */ + + if (ar->arNetworkType == AP_NETWORK) { + ATH_MAC_HDR *datap = (ATH_MAC_HDR *)A_NETBUF_DATA(skb); + sta_t *conn = NULL; + + /* If the dstMac is a Multicast address & atleast one of the + * associated STA is in PS mode, then queue the pkt to the + * mcastq + */ + if (IEEE80211_IS_MULTICAST(datap->dstMac)) { + A_UINT8 ctr=0; + A_BOOL qMcast=FALSE; + + for (ctr=0; ctrsta_list[ctr]))) { + qMcast = TRUE; + } + } + if(qMcast) { + /* If this transmit is not because of a Dtim Expiry q it */ + if (ar->DTIMExpired == FALSE) { + A_BOOL isMcastqEmpty = FALSE; + + A_MUTEX_LOCK(&ar->mcastpsqLock); + isMcastqEmpty = A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq); + A_NETBUF_ENQUEUE(&ar->mcastpsq, skb); + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + + /* If this is the first Mcast pkt getting queued + * indicate to the target to set the BitmapControl LSB + * of the TIM IE. + */ + if (isMcastqEmpty) { + wmi_set_pvb_cmd(ar->arWmi, MCAST_AID, 1); + } + return 0; + } else { + /* This transmit is because of Dtim expiry. Determine if + * MoreData bit has to be set. + */ + A_MUTEX_LOCK(&ar->mcastpsqLock); + if(!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) { + bMoreData = TRUE; + } + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + } + } + } else { + conn = ieee80211_find_conn(ar, datap->dstMac); + if (conn) { + if (STA_IS_PWR_SLEEP(conn)) { + /* If this transmit is not because of a PsPoll q it*/ + if (!STA_IS_PS_POLLED(conn)) { + A_BOOL isPsqEmpty = FALSE; + /* Queue the frames if the STA is sleeping */ + A_MUTEX_LOCK(&conn->psqLock); + isPsqEmpty = A_NETBUF_QUEUE_EMPTY(&conn->psq); + A_NETBUF_ENQUEUE(&conn->psq, skb); + A_MUTEX_UNLOCK(&conn->psqLock); + + /* If this is the first pkt getting queued + * for this STA, update the PVB for this STA + */ + if (isPsqEmpty) { + wmi_set_pvb_cmd(ar->arWmi, conn->aid, 1); + } + + return 0; + } else { + /* This tx is because of a PsPoll. Determine if + * MoreData bit has to be set + */ + A_MUTEX_LOCK(&conn->psqLock); + if (!A_NETBUF_QUEUE_EMPTY(&conn->psq)) { + bMoreData = TRUE; + } + A_MUTEX_UNLOCK(&conn->psqLock); + } + } + } else { + + /* non existent STA. drop the frame */ + A_NETBUF_FREE(skb); + return 0; + } + } + } + + if (ar->arWmiEnabled) { + if (A_NETBUF_HEADROOM(skb) < dev->hard_header_len) { + struct sk_buff *newbuf; + + /* + * We really should have gotten enough headroom but sometimes + * we still get packets with not enough headroom. Copy the packet. + */ + len = A_NETBUF_LEN(skb); + newbuf = A_NETBUF_ALLOC(len); + if (newbuf == NULL) { + break; + } + A_NETBUF_PUT(newbuf, len); + A_MEMCPY(A_NETBUF_DATA(newbuf), A_NETBUF_DATA(skb), len); + A_NETBUF_FREE(skb); + skb = newbuf; + /* fall through and assemble header */ + } + + if (processDot11Hdr) { + if (wmi_dot11_hdr_add(ar->arWmi,skb,ar->arNetworkType) != A_OK) { + AR_DEBUG_PRINTF("ar6000_data_tx-wmi_dot11_hdr_add failed\n"); + break; + } + } else { + if (wmi_dix_2_dot3(ar->arWmi, skb) != A_OK) { + AR_DEBUG_PRINTF("ar6000_data_tx - wmi_dix_2_dot3 failed\n"); + break; + } + } + + if (wmi_data_hdr_add(ar->arWmi, skb, DATA_MSGTYPE, bMoreData) != A_OK) { + AR_DEBUG_PRINTF("ar6000_data_tx - wmi_data_hdr_add failed\n"); + break; + } + + if ((ar->arNetworkType == ADHOC_NETWORK) && + ar->arIbssPsEnable && ar->arConnected) { + /* flag to check adhoc mapping once we take the lock below: */ + checkAdHocPsMapping = TRUE; + + } else { + /* get the stream mapping */ + ac = wmi_implicit_create_pstream(ar->arWmi, skb, 0, ar->arWmmEnabled); + } + + } else { + struct iphdr *ipHdr; + /* + * the endpoint is directly based on the TOS field in the IP + * header **** only for testing ****** + */ + ipHdr = A_NETBUF_DATA(skb) + sizeof(ATH_MAC_HDR); + /* here we map the TOS field to an access class, this is for + * the endpointping test application. The application uses 0,1,2,3 + * for the TOS field to emulate writing to mailboxes. The number is + * used to map directly to an access class */ + ac = (ipHdr->tos >> 1) & 0x3; + } + + } while (FALSE); + + /* did we succeed ? */ + if ((ac == AC_NOT_MAPPED) && !checkAdHocPsMapping) { + /* cleanup and exit */ + A_NETBUF_FREE(skb); + AR6000_STAT_INC(ar, tx_dropped); + AR6000_STAT_INC(ar, tx_aborted_errors); + return 0; + } + + cookie = NULL; + + /* take the lock to protect driver data */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + do { + + if (checkAdHocPsMapping) { + eid = ar6000_ibss_map_epid(skb, dev, &mapNo); + }else { + eid = arAc2EndpointID (ar, ac); + } + /* validate that the endpoint is connected */ + if (eid == 0 || eid == ENDPOINT_UNUSED ) { + AR_DEBUG_PRINTF(" eid %d is NOT mapped!\n", eid); + break; + } + /* allocate resource for this packet */ + cookie = ar6000_alloc_cookie(ar); + + if (cookie != NULL) { + /* update counts while the lock is held */ + ar->arTxPending[eid]++; + ar->arTotalTxDataPending++; + } + + } while (FALSE); + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + if (cookie != NULL) { + cookie->arc_bp[0] = (A_UINT32)skb; + cookie->arc_bp[1] = mapNo; + SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt, + cookie, + A_NETBUF_DATA(skb), + A_NETBUF_LEN(skb), + eid, + AR6K_DATA_PKT_TAG); + +#ifdef DEBUG + if (debugdriver >= 3) { + ar6000_dump_skb(skb); + } +#endif + /* HTC interface is asynchronous, if this fails, cleanup will happen in + * the ar6000_tx_complete callback */ + HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt); + } else { + /* no packet to send, cleanup */ + A_NETBUF_FREE(skb); + AR6000_STAT_INC(ar, tx_dropped); + AR6000_STAT_INC(ar, tx_aborted_errors); + } + + return 0; +} + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +static void +tvsub(register struct timeval *out, register struct timeval *in) +{ + if((out->tv_usec -= in->tv_usec) < 0) { + out->tv_sec--; + out->tv_usec += 1000000; + } + out->tv_sec -= in->tv_sec; +} + +void +applyAPTCHeuristics(AR_SOFTC_T *ar) +{ + A_UINT32 duration; + A_UINT32 numbytes; + A_UINT32 throughput; + struct timeval ts; + A_STATUS status; + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + if ((enableAPTCHeuristics) && (!aptcTR.timerScheduled)) { + do_gettimeofday(&ts); + tvsub(&ts, &aptcTR.samplingTS); + duration = ts.tv_sec * 1000 + ts.tv_usec / 1000; /* ms */ + numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived; + + if (duration > APTC_TRAFFIC_SAMPLING_INTERVAL) { + /* Initialize the time stamp and byte count */ + aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0; + do_gettimeofday(&aptcTR.samplingTS); + + /* Calculate and decide based on throughput thresholds */ + throughput = ((numbytes * 8) / duration); + if (throughput > APTC_UPPER_THROUGHPUT_THRESHOLD) { + /* Disable Sleep and schedule a timer */ + A_ASSERT(ar->arWmiReady == TRUE); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + status = wmi_powermode_cmd(ar->arWmi, MAX_PERF_POWER); + AR6000_SPIN_LOCK(&ar->arLock, 0); + A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0); + aptcTR.timerScheduled = TRUE; + } + } + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); +} +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +static HTC_SEND_FULL_ACTION ar6000_tx_queue_full(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + HTC_SEND_FULL_ACTION action = HTC_SEND_FULL_KEEP; + A_BOOL stopNet = FALSE; + HTC_ENDPOINT_ID Endpoint = HTC_GET_ENDPOINT_FROM_PKT(pPacket); + + do { + + if (bypasswmi) { + /* for endpointping testing no other checks need to be made + * we can however still allow the network to stop */ + stopNet = TRUE; + break; + } + + if (Endpoint == ar->arControlEp) { + /* under normal WMI if this is getting full, then something is running rampant + * the host should not be exhausting the WMI queue with too many commands + * the only exception to this is during testing using endpointping */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + /* set flag to handle subsequent messages */ + ar->arWMIControlEpFull = TRUE; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + AR_DEBUG_PRINTF("WMI Control Endpoint is FULL!!! \n"); + /* no need to stop the network */ + stopNet = FALSE; + break; + } + + /* if we get here, we are dealing with data endpoints getting full */ + + if (HTC_GET_TAG_FROM_PKT(pPacket) == AR6K_CONTROL_PKT_TAG) { + /* don't drop control packets issued on ANY data endpoint */ + break; + } + + if (ar->arNetworkType == ADHOC_NETWORK) { + /* in adhoc mode, we cannot differentiate traffic priorities so there is no need to + * continue, however we should stop the network */ + stopNet = TRUE; + break; + } + + if (ar->arAcStreamPriMap[arEndpoint2Ac(ar,Endpoint)] < ar->arHiAcStreamActivePri) { + /* this stream's priority is less than the highest active priority, we + * give preference to the highest priority stream by directing + * HTC to drop the packet that overflowed */ + action = HTC_SEND_FULL_DROP; + /* since we are dropping packets, no need to stop the network */ + stopNet = FALSE; + break; + } + + } while (FALSE); + + if (stopNet) { + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arNetQueueStopped = TRUE; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + /* one of the data endpoints queues is getting full..need to stop network stack + * the queue will resume in ar6000_tx_complete() */ + netif_stop_queue(ar->arNetDev); + } + + return action; +} + + +static void +ar6000_tx_complete(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + void *cookie = (void *)pPacket->pPktContext; + struct sk_buff *skb = NULL; + A_UINT32 mapNo = 0; + A_STATUS status; + struct ar_cookie * ar_cookie; + HTC_ENDPOINT_ID eid; + A_BOOL wakeEvent = FALSE; + + status = pPacket->Status; + ar_cookie = (struct ar_cookie *)cookie; + skb = (struct sk_buff *)ar_cookie->arc_bp[0]; + eid = pPacket->Endpoint ; + mapNo = ar_cookie->arc_bp[1]; + + A_ASSERT(skb); + A_ASSERT(pPacket->pBuffer == A_NETBUF_DATA(skb)); + + if (A_SUCCESS(status)) { + A_ASSERT(pPacket->ActualLength == A_NETBUF_LEN(skb)); + } + + AR_DEBUG2_PRINTF("ar6000_tx_complete skb=0x%x data=0x%x len=0x%x eid=%d ", + (A_UINT32)skb, (A_UINT32)pPacket->pBuffer, + pPacket->ActualLength, + eid); + + /* lock the driver as we update internal state */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + ar->arTxPending[eid]--; + + if ((eid != ar->arControlEp) || bypasswmi) { + ar->arTotalTxDataPending--; + } + + if (eid == ar->arControlEp) + { + if (ar->arWMIControlEpFull) { + /* since this packet completed, the WMI EP is no longer full */ + ar->arWMIControlEpFull = FALSE; + } + + if (ar->arTxPending[eid] == 0) { + wakeEvent = TRUE; + } + } + + if (A_FAILED(status)) { + AR6000_STAT_INC(ar, tx_errors); + if (status != A_NO_RESOURCE) { + AR_DEBUG_PRINTF("%s() -TX ERROR, status: 0x%x\n", __func__, + status); + } + } else { + AR_DEBUG2_PRINTF("OK\n"); + AR6000_STAT_INC(ar, tx_packets); + ar->arNetStats.tx_bytes += A_NETBUF_LEN(skb); +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + aptcTR.bytesTransmitted += a_netbuf_to_len(skb); + applyAPTCHeuristics(ar); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + } + + // TODO this needs to be looked at + if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable + && (eid != ar->arControlEp) && mapNo) + { + mapNo --; + ar->arNodeMap[mapNo].txPending --; + + if (!ar->arNodeMap[mapNo].txPending && (mapNo == (ar->arNodeNum - 1))) { + A_UINT32 i; + for (i = ar->arNodeNum; i > 0; i --) { + if (!ar->arNodeMap[i - 1].txPending) { + A_MEMZERO(&ar->arNodeMap[i - 1], sizeof(struct ar_node_mapping)); + ar->arNodeNum --; + } else { + break; + } + } + } + } + + /* Freeing a cookie should not be contingent on either of */ + /* these flags, just if we have a cookie or not. */ + /* Can we even get here without a cookie? Fix later. */ + if (ar->arWmiReady == TRUE || (bypasswmi)) + { + ar6000_free_cookie(ar, cookie); + } + + if (ar->arNetQueueStopped) { + ar->arNetQueueStopped = FALSE; + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + /* lock is released, we can freely call other kernel APIs */ + + A_NETBUF_FREE(skb); + + if ((ar->arConnected == TRUE) || (bypasswmi)) { + if (status != A_ECANCELED) { + /* don't wake the queue if we are flushing, other wise it will just + * keep queueing packets, which will keep failing */ + netif_wake_queue(ar->arNetDev); + } + } + + if (wakeEvent) { + wake_up(&arEvent); + } + +} + +sta_t * +ieee80211_find_conn(AR_SOFTC_T *ar, A_UINT8 *node_addr) +{ + sta_t *conn = NULL; + A_UINT8 i, max_conn; + + switch(ar->arNetworkType) { + case AP_NETWORK: + max_conn = AP_MAX_NUM_STA; + break; + default: + max_conn=0; + break; + } + + for (i = 0; i < max_conn; i++) { + if (IEEE80211_ADDR_EQ(node_addr, ar->sta_list[i].mac)) { + conn = &ar->sta_list[i]; + break; + } + } + + return conn; +} + +sta_t *ieee80211_find_conn_for_aid(AR_SOFTC_T *ar, A_UINT8 aid) +{ + sta_t *conn = NULL; + A_UINT8 ctr; + + for (ctr = 0; ctr < AP_MAX_NUM_STA; ctr++) { + if (ar->sta_list[ctr].aid == aid) { + conn = &ar->sta_list[ctr]; + break; + } + } + return conn; +} + +/* + * Receive event handler. This is called by HTC when a packet is received + */ +int pktcount; +static void +ar6000_rx(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + struct sk_buff *skb = (struct sk_buff *)pPacket->pPktContext; + int minHdrLen; + A_STATUS status = pPacket->Status; + HTC_ENDPOINT_ID ept = pPacket->Endpoint; + + A_ASSERT((status != A_OK) || + (pPacket->pBuffer == (A_NETBUF_DATA(skb) + HTC_HEADER_LEN))); + + AR_DEBUG2_PRINTF("ar6000_rx ar=0x%x eid=%d, skb=0x%x, data=0x%x, len=0x%x ", + (A_UINT32)ar, ept, (A_UINT32)skb, (A_UINT32)pPacket->pBuffer, + pPacket->ActualLength); + if (status != A_OK) { + AR_DEBUG2_PRINTF("ERR\n"); + } else { + AR_DEBUG2_PRINTF("OK\n"); + } + + /* take lock to protect buffer counts + * and adaptive power throughput state */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + ar->arRxBuffers[ept]--; + + if (A_SUCCESS(status)) { + AR6000_STAT_INC(ar, rx_packets); + ar->arNetStats.rx_bytes += pPacket->ActualLength; +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + aptcTR.bytesReceived += a_netbuf_to_len(skb); + applyAPTCHeuristics(ar); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + + A_NETBUF_PUT(skb, pPacket->ActualLength + HTC_HEADER_LEN); + A_NETBUF_PULL(skb, HTC_HEADER_LEN); + +#ifdef DEBUG + if (debugdriver >= 2) { + ar6000_dump_skb(skb); + } +#endif /* DEBUG */ + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + skb->dev = ar->arNetDev; + if (status != A_OK) { + AR6000_STAT_INC(ar, rx_errors); + A_NETBUF_FREE(skb); + } else if (ar->arWmiEnabled == TRUE) { + if (ept == ar->arControlEp) { + /* + * this is a wmi control msg + */ + wmi_control_rx(ar->arWmi, skb); + } else { + /* + * this is a wmi data packet + */ + // NWF + + if (processDot11Hdr) { + minHdrLen = sizeof(WMI_DATA_HDR) + sizeof(struct ieee80211_frame) + sizeof(ATH_LLC_SNAP_HDR); + } else { + minHdrLen = sizeof (WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + + sizeof(ATH_LLC_SNAP_HDR); + } + + /* In the case of AP mode we may receive NULL data frames + * that do not have LLC hdr. They are 16 bytes in size. + * Allow these frames in the AP mode. + */ + if (ar->arNetworkType != AP_NETWORK && ((pPacket->ActualLength < minHdrLen) || + (pPacket->ActualLength > AR6000_BUFFER_SIZE))) + { + /* + * packet is too short or too long + */ + AR_DEBUG_PRINTF("TOO SHORT or TOO LONG\n"); + AR6000_STAT_INC(ar, rx_errors); + AR6000_STAT_INC(ar, rx_length_errors); + A_NETBUF_FREE(skb); + } else { +#if 0 + /* Access RSSI values here */ + AR_DEBUG_PRINTF("RSSI %d\n", + ((WMI_DATA_HDR *) A_NETBUF_DATA(skb))->rssi); +#endif + /* Get the Power save state of the STA */ + if (ar->arNetworkType == AP_NETWORK) { + sta_t *conn = NULL; + A_UINT8 psState=0,prevPsState; + ATH_MAC_HDR *datap=NULL; + + psState = (((WMI_DATA_HDR *)A_NETBUF_DATA(skb))->info + >> WMI_DATA_HDR_PS_SHIFT) & WMI_DATA_HDR_PS_MASK; + datap = (ATH_MAC_HDR *)(A_NETBUF_DATA(skb)+sizeof(WMI_DATA_HDR)); + conn = ieee80211_find_conn(ar, datap->srcMac); + + + if (conn) { + /* if there is a change in PS state of the STA, + * take appropriate steps. + * 1. If Sleep-->Awake, flush the psq for the STA + * Clear the PVB for the STA. + * 2. If Awake-->Sleep, Starting queueing frames + * the STA. + */ + prevPsState = STA_IS_PWR_SLEEP(conn); + if (psState) { + STA_SET_PWR_SLEEP(conn); + } else { + STA_CLR_PWR_SLEEP(conn); + } + + if (prevPsState ^ STA_IS_PWR_SLEEP(conn)) { + + if (!STA_IS_PWR_SLEEP(conn)) { + + A_MUTEX_LOCK(&conn->psqLock); + while (!A_NETBUF_QUEUE_EMPTY(&conn->psq)) { + struct sk_buff *skb=NULL; + + skb = A_NETBUF_DEQUEUE(&conn->psq); + A_MUTEX_UNLOCK(&conn->psqLock); + ar6000_data_tx(skb,ar->arNetDev); + A_MUTEX_LOCK(&conn->psqLock); + } + A_MUTEX_UNLOCK(&conn->psqLock); + /* Clear the PVB for this STA */ + wmi_set_pvb_cmd(ar->arWmi, conn->aid, 0); + } + } + } else { + /* This frame is from a STA that is not associated*/ + A_ASSERT(FALSE); + } + + /* Drop NULL data frames here */ + if((pPacket->ActualLength < minHdrLen) || + (pPacket->ActualLength > AR6000_BUFFER_SIZE)) { + A_NETBUF_FREE(skb); + goto refill; + } + } + + wmi_data_hdr_remove(ar->arWmi, skb); + /* NWF: print the 802.11 hdr bytes */ + if(processDot11Hdr) { + wmi_dot11_hdr_remove(ar->arWmi,skb); + } else { + wmi_dot3_2_dix(ar->arWmi, skb); + } + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + /* + * extra push and memcpy, for eth_type_trans() of 2.4 kernel + * will pull out hard_header_len bytes of the skb. + */ + A_NETBUF_PUSH(skb, sizeof(WMI_DATA_HDR) + sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN); + A_MEMCPY(A_NETBUF_DATA(skb), A_NETBUF_DATA(skb) + sizeof(WMI_DATA_HDR) + + sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN, sizeof(ATH_MAC_HDR)); +#endif + if ((ar->arNetDev->flags & IFF_UP) == IFF_UP) { + if (ar->arNetworkType == AP_NETWORK) { + struct sk_buff *skb1 = NULL; + ATH_MAC_HDR *datap; + + datap = (ATH_MAC_HDR *)A_NETBUF_DATA(skb); + if (IEEE80211_IS_MULTICAST(datap->dstMac)) { + /* Bcast/Mcast frames should be sent to the OS + * stack as well as on the air. + */ + skb1 = skb_copy(skb,GFP_ATOMIC); + } else { + /* Search for a connected STA with dstMac as + * the Mac address. If found send the frame to + * it on the air else send the frame up the + * stack + */ + sta_t *conn = NULL; + conn = ieee80211_find_conn(ar, datap->dstMac); + + if (conn) { + skb1 = skb; + skb = NULL; + } + } + if (skb1 && ar->intra_bss) { + ar6000_data_tx(skb1, ar->arNetDev); + } + } + } + deliver_frames_to_nw_stack(skb); + } + } + } else { + deliver_frames_to_nw_stack(skb); + } +refill: + if (status != A_ECANCELED) { + /* + * HTC provides A_ECANCELED status when it doesn't want to be refilled + * (probably due to a shutdown) + */ + ar6000_rx_refill(Context, ept); + } + + +} + +static void +deliver_frames_to_nw_stack(struct sk_buff *skb) +{ + if(skb) { + if ((skb->dev->flags & IFF_UP) == IFF_UP) { + skb->protocol = eth_type_trans(skb, skb->dev); + netif_rx(skb); + } else { + A_NETBUF_FREE(skb); + } + } +} + + +static void +ar6000_rx_refill(void *Context, HTC_ENDPOINT_ID Endpoint) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + void *osBuf; + int RxBuffers; + int buffersToRefill; + HTC_PACKET *pPacket; + + buffersToRefill = (int)AR6000_MAX_RX_BUFFERS - + (int)ar->arRxBuffers[Endpoint]; + + if (buffersToRefill <= 0) { + /* fast return, nothing to fill */ + return; + } + + AR_DEBUG2_PRINTF("ar6000_rx_refill: providing htc with %d buffers at eid=%d\n", + buffersToRefill, Endpoint); + + for (RxBuffers = 0; RxBuffers < buffersToRefill; RxBuffers++) { + osBuf = A_NETBUF_ALLOC(AR6000_BUFFER_SIZE); + if (NULL == osBuf) { + break; + } + /* the HTC packet wrapper is at the head of the reserved area + * in the skb */ + pPacket = (HTC_PACKET *)(A_NETBUF_HEAD(osBuf)); + /* set re-fill info */ + SET_HTC_PACKET_INFO_RX_REFILL(pPacket,osBuf,A_NETBUF_DATA(osBuf),AR6000_BUFFER_SIZE,Endpoint); + /* add this packet */ + HTCAddReceivePkt(ar->arHtcTarget, pPacket); + } + + /* update count */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arRxBuffers[Endpoint] += RxBuffers; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); +} + +static struct net_device_stats * +ar6000_get_stats(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + return &ar->arNetStats; +} + +static struct iw_statistics * +ar6000_get_iwstats(struct net_device * dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + TARGET_STATS *pStats = &ar->arTargetStats; + struct iw_statistics * pIwStats = &ar->arIwStats; + + if ((ar->arWmiReady == FALSE) + /* + * The in_atomic function is used to determine if the scheduling is + * allowed in the current context or not. This was introduced in 2.6 + * From what I have read on the differences between 2.4 and 2.6, the + * 2.4 kernel did not support preemption and so this check might not + * be required for 2.4 kernels. + */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + || (in_atomic()) +#endif + ) + { + pIwStats->status = 0; + pIwStats->qual.qual = 0; + pIwStats->qual.level =0; + pIwStats->qual.noise = 0; + pIwStats->discard.code =0; + pIwStats->discard.retries=0; + pIwStats->miss.beacon =0; + return pIwStats; + } + if (down_interruptible(&ar->arSem)) { + pIwStats->status = 0; + return pIwStats; + } + + + ar->statsUpdatePending = TRUE; + + if(wmi_get_stats_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + pIwStats->status = 0; + return pIwStats; + } + + wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ); + + if (signal_pending(current)) { + AR_DEBUG_PRINTF("ar6000 : WMI get stats timeout \n"); + up(&ar->arSem); + pIwStats->status = 0; + return pIwStats; + } + pIwStats->status = 1 ; + pIwStats->qual.qual = pStats->cs_aveBeacon_rssi - 161; + pIwStats->qual.level =pStats->cs_aveBeacon_rssi; /* noise is -95 dBm */ + pIwStats->qual.noise = pStats->noise_floor_calibation; + pIwStats->discard.code = pStats->rx_decrypt_err; + pIwStats->discard.retries = pStats->tx_retry_cnt; + pIwStats->miss.beacon = pStats->cs_bmiss_cnt; + up(&ar->arSem); + return pIwStats; +} + +void +ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap, A_UINT32 vers) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + struct net_device *dev = ar->arNetDev; + + ar->arWmiReady = TRUE; + wake_up(&arEvent); + A_MEMCPY(dev->dev_addr, datap, AR6000_ETH_ADDR_LEN); + AR_DEBUG_PRINTF("mac address = %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", + dev->dev_addr[0], dev->dev_addr[1], + dev->dev_addr[2], dev->dev_addr[3], + dev->dev_addr[4], dev->dev_addr[5]); + + ar->arPhyCapability = phyCap; + ar->arVersion.wlan_ver = vers; +} + +A_UINT8 +add_new_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 aid, A_UINT8 *wpaie, A_UINT8 ielen) +{ + A_INT8 free_slot=-1, i; + + for(i=0; i < AP_MAX_NUM_STA; i++) { + if(A_MEMCMP(ar->sta_list[i].mac, mac, ATH_MAC_LEN)==0) { + /* it is already available */ + return 0; + } + + if(!((1 << i) & ar->sta_list_index)) { + free_slot = i; + break; + } + } + + if(free_slot >= 0) { + A_MEMCPY(ar->sta_list[free_slot].mac, mac, ATH_MAC_LEN); + A_MEMCPY(ar->sta_list[free_slot].wpa_ie, wpaie, ielen); + ar->sta_list[free_slot].aid = aid; + ar->sta_list_index = ar->sta_list_index | (1 << free_slot); + return 1; + } + return 0; /* not added */ +} + +void +ar6000_connect_event(AR_SOFTC_T *ar, A_UINT16 channel, A_UINT8 *bssid, + A_UINT16 listenInterval, A_UINT16 beaconInterval, + NETWORK_TYPE networkType, A_UINT8 beaconIeLen, + A_UINT8 assocReqLen, A_UINT8 assocRespLen, + A_UINT8 *assocInfo) +{ + union iwreq_data wrqu; + int i, beacon_ie_pos, assoc_resp_ie_pos, assoc_req_ie_pos; + static const char *tag1 = "ASSOCINFO(ReqIEs="; + static const char *tag2 = "ASSOCRESPIE="; + static const char *beaconIetag = "BEACONIE="; + char buf[WMI_CONTROL_MSG_MAX_LEN * 2 + strlen(tag1) + 1]; + char *pos; + unsigned long flags; + + if(ar->arNetworkType & AP_NETWORK) { + A_PRINTF("NEW STA %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x " + " aid=%d WPAIE=%d\n", bssid[0], bssid[1], bssid[2], + bssid[3], bssid[4], bssid[5], channel, assocRespLen); + add_new_sta(ar, bssid, channel /*aid*/, + assocInfo /* WPA IE */, assocRespLen /* IE len */); + + /* Send event to application */ + A_MEMZERO(&wrqu, sizeof(wrqu)); + A_MEMCPY(wrqu.addr.sa_data, bssid, ATH_MAC_LEN); + wireless_send_event(ar->arNetDev, IWEVREGISTERED, &wrqu, NULL); + /* In case the queue is stopped when we switch modes, this will + * wake it up + */ + netif_wake_queue(ar->arNetDev); + return; + } + + A_MEMCPY(ar->arBssid, bssid, sizeof(ar->arBssid)); + ar->arBssChannel = channel; + + A_PRINTF("AR6000 connected event on freq %d ", channel); + A_PRINTF("with bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x " + " listenInterval=%d, beaconInterval = %d, beaconIeLen = %d assocReqLen=%d" + " assocRespLen =%d\n", + bssid[0], bssid[1], bssid[2], + bssid[3], bssid[4], bssid[5], + listenInterval, beaconInterval, + beaconIeLen, assocReqLen, assocRespLen); + if (networkType & ADHOC_NETWORK) { + if (networkType & ADHOC_CREATOR) { + A_PRINTF("Network: Adhoc (Creator)\n"); + } else { + A_PRINTF("Network: Adhoc (Joiner)\n"); + } + } else { + A_PRINTF("Network: Infrastructure\n"); + } + + if (beaconIeLen && (sizeof(buf) > (9 + beaconIeLen * 2))) { + AR_DEBUG_PRINTF("\nBeaconIEs= "); + + beacon_ie_pos = 0; + A_MEMZERO(buf, sizeof(buf)); + sprintf(buf, "%s", beaconIetag); + pos = buf + 9; + for (i = beacon_ie_pos; i < beacon_ie_pos + beaconIeLen; i++) { + AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]); + sprintf(pos, "%2.2x", assocInfo[i]); + pos += 2; + } + AR_DEBUG_PRINTF("\n"); + + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + } + + if (assocRespLen && (sizeof(buf) > (12 + (assocRespLen * 2)))) + { + assoc_resp_ie_pos = beaconIeLen + assocReqLen + + sizeof(A_UINT16) + /* capinfo*/ + sizeof(A_UINT16) + /* status Code */ + sizeof(A_UINT16) ; /* associd */ + A_MEMZERO(buf, sizeof(buf)); + sprintf(buf, "%s", tag2); + pos = buf + 12; + AR_DEBUG_PRINTF("\nAssocRespIEs= "); + /* + * The Association Response Frame w.o. the WLAN header is delivered to + * the host, so skip over to the IEs + */ + for (i = assoc_resp_ie_pos; i < assoc_resp_ie_pos + assocRespLen - 6; i++) + { + AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]); + sprintf(pos, "%2.2x", assocInfo[i]); + pos += 2; + } + AR_DEBUG_PRINTF("\n"); + + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + } + + if (assocReqLen && (sizeof(buf) > (17 + (assocReqLen * 2)))) { + /* + * assoc Request includes capability and listen interval. Skip these. + */ + assoc_req_ie_pos = beaconIeLen + + sizeof(A_UINT16) + /* capinfo*/ + sizeof(A_UINT16); /* listen interval */ + + A_MEMZERO(buf, sizeof(buf)); + sprintf(buf, "%s", tag1); + pos = buf + 17; + AR_DEBUG_PRINTF("AssocReqIEs= "); + for (i = assoc_req_ie_pos; i < assoc_req_ie_pos + assocReqLen - 4; i++) { + AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]); + sprintf(pos, "%2.2x", assocInfo[i]); + pos += 2;; + } + AR_DEBUG_PRINTF("\n"); + + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + } + +#ifdef USER_KEYS + if (ar->user_savedkeys_stat == USER_SAVEDKEYS_STAT_RUN && + ar->user_saved_keys.keyOk == TRUE) + { + key_op_ctrl = KEY_OP_VALID_MASK & ~KEY_OP_INIT_TSC; + + if (ar->user_key_ctrl & AR6000_USER_SETKEYS_RSC_UNCHANGED) { + key_op_ctrl &= ~KEY_OP_INIT_RSC; + } else { + key_op_ctrl |= KEY_OP_INIT_RSC; + } + ar6000_reinstall_keys(ar, key_op_ctrl); + } +#endif /* USER_KEYS */ + + netif_wake_queue(ar->arNetDev); + + if ((OPEN_AUTH == ar->arDot11AuthMode) && + (NONE_AUTH == ar->arAuthMode) && + (WEP_CRYPT == ar->arPairwiseCrypto)) + { + if (!ar->arConnected) { + ar6000_install_static_wep_keys(ar); + } + } + + /* Update connect & link status atomically */ + spin_lock_irqsave(&ar->arLock, flags); + ar->arConnected = TRUE; + ar->arConnectPending = FALSE; + netif_carrier_on(ar->arNetDev); + spin_unlock_irqrestore(&ar->arLock, flags); + + reconnect_flag = 0; + + A_MEMZERO(&wrqu, sizeof(wrqu)); + A_MEMCPY(wrqu.addr.sa_data, bssid, IEEE80211_ADDR_LEN); + wrqu.addr.sa_family = ARPHRD_ETHER; + wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL); + if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable) { + A_MEMZERO(ar->arNodeMap, sizeof(ar->arNodeMap)); + ar->arNodeNum = 0; + ar->arNexEpId = ENDPOINT_2; + } +} + +void ar6000_set_numdataendpts(AR_SOFTC_T *ar, A_UINT32 num) +{ + A_ASSERT(num <= (HTC_MAILBOX_NUM_MAX - 1)); + ar->arNumDataEndPts = num; +} + +A_UINT8 +remove_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 reason) +{ + A_INT8 i; + struct sk_buff *skb; + + if(IS_MAC_NULL(mac)) { + return 0; + } + + for(i=0; i < AP_MAX_NUM_STA; i++) { + if(A_MEMCMP(ar->sta_list[i].mac, mac, ATH_MAC_LEN)==0) { + + /* empty the queued pkts in the PS queue if any */ + A_MUTEX_LOCK(&ar->sta_list[i].psqLock); + while (!A_NETBUF_QUEUE_EMPTY(&ar->sta_list[i].psq)) { + skb = A_NETBUF_DEQUEUE(&ar->sta_list[i].psq); + A_NETBUF_FREE(skb); + } + A_MUTEX_UNLOCK(&ar->sta_list[i].psqLock); + + A_PRINTF("DEL STA %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x " + " aid=%d REASON=%d\n", mac[0], mac[1], mac[2], + mac[3], mac[4], mac[5], ar->sta_list[i].aid, reason); + + /* Zero out the state fields */ + A_MEMZERO(&ar->sta_list[i].mac, ATH_MAC_LEN); + A_MEMZERO(&ar->sta_list[i].wpa_ie, IEEE80211_MAX_IE); + ar->sta_list[i].aid = 0; + ar->sta_list[i].flags = 0; + + ar->sta_list_index = ar->sta_list_index & ~(1 << i); + return 1; + } + } + + return 0; /* not removed */ +} + +void +ar6000_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason, A_UINT8 *bssid, + A_UINT8 assocRespLen, A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus) +{ + A_UINT8 i; + unsigned long flags; + union iwreq_data wrqu; + + if(ar->arNetworkType & AP_NETWORK) { + struct sk_buff *skb; + + if(!remove_sta(ar, bssid, protocolReasonStatus)) { + return; + } + + /* If there are no more associated STAs, empty the mcast PS q */ + if (ar->sta_list_index == 0) { + A_MUTEX_LOCK(&ar->mcastpsqLock); + while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) { + skb = A_NETBUF_DEQUEUE(&ar->mcastpsq); + A_NETBUF_FREE(skb); + } + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + } + + /* Send event to application */ + A_MEMZERO(&wrqu, sizeof(wrqu)); + A_MEMCPY(wrqu.addr.sa_data, bssid, ATH_MAC_LEN); + wireless_send_event(ar->arNetDev, IWEVEXPIRED, &wrqu, NULL); + return; + } + + /* Always send a DEL_LINK event */ + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.addr.sa_family = ARPHRD_ETHER; + + /* Send disconnect event to supplicant */ + wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL); + + A_PRINTF("AR6000 disconnected"); + if (bssid[0] || bssid[1] || bssid[2] || bssid[3] || bssid[4] || bssid[5]) { + A_PRINTF(" from %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", + bssid[0], bssid[1], bssid[2], bssid[3], bssid[4], bssid[5]); + } + + AR_DEBUG_PRINTF("\nDisconnect Reason is %d", reason); + AR_DEBUG_PRINTF("\nProtocol Reason/Status Code is %d", protocolReasonStatus); + AR_DEBUG_PRINTF("\nAssocResp Frame = %s", + assocRespLen ? " " : "NULL"); + for (i = 0; i < assocRespLen; i++) { + if (!(i % 0x10)) { + AR_DEBUG_PRINTF("\n"); + } + AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]); + } + AR_DEBUG_PRINTF("\n"); + /* + * If the event is due to disconnect cmd from the host, only they the target + * would stop trying to connect. Under any other condition, target would + * keep trying to connect. + * + */ + if( reason == DISCONNECT_CMD) + { + ar->arConnectPending = FALSE; + } else { + ar->arConnectPending = TRUE; + if (((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x11)) || + ((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x0) && (reconnect_flag == 1))) { + ar->arConnected = TRUE; + return; + } + } + + /* Update connect & link status atomically */ + spin_lock_irqsave(&ar->arLock, flags); + ar->arConnected = FALSE; + netif_carrier_off(ar->arNetDev); + spin_unlock_irqrestore(&ar->arLock, flags); + + if( (reason != CSERV_DISCONNECT) || (reconnect_flag != 1) ) { + reconnect_flag = 0; + } + +#ifdef USER_KEYS + if (reason != CSERV_DISCONNECT) + { + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT; + ar->user_key_ctrl = 0; + } +#endif /* USER_KEYS */ + + netif_stop_queue(ar->arNetDev); + A_MEMZERO(ar->arBssid, sizeof(ar->arBssid)); + ar->arBssChannel = 0; + ar->arBeaconInterval = 0; + + ar6000_TxDataCleanup(ar); +} + +void +ar6000_regDomain_event(AR_SOFTC_T *ar, A_UINT32 regCode) +{ + A_PRINTF("AR6000 Reg Code = 0x%x\n", regCode); + ar->arRegCode = regCode; +} + +void +ar6000_neighborReport_event(AR_SOFTC_T *ar, int numAps, WMI_NEIGHBOR_INFO *info) +{ + static const char *tag = "PRE-AUTH"; + char buf[128]; + union iwreq_data wrqu; + int i; + + AR_DEBUG_PRINTF("AR6000 Neighbor Report Event\n"); + for (i=0; i < numAps; info++, i++) { + AR_DEBUG_PRINTF("bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", + info->bssid[0], info->bssid[1], info->bssid[2], + info->bssid[3], info->bssid[4], info->bssid[5]); + if (info->bssFlags & WMI_PREAUTH_CAPABLE_BSS) { + AR_DEBUG_PRINTF("preauth-cap"); + } + if (info->bssFlags & WMI_PMKID_VALID_BSS) { + AR_DEBUG_PRINTF(" pmkid-valid\n"); + continue; /* we skip bss if the pmkid is already valid */ + } + AR_DEBUG_PRINTF("\n"); + snprintf(buf, sizeof(buf), "%s%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x", + tag, + info->bssid[0], info->bssid[1], info->bssid[2], + info->bssid[3], info->bssid[4], info->bssid[5], + i, info->bssFlags); + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + } +} + +void +ar6000_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast) +{ + static const char *tag = "MLME-MICHAELMICFAILURE.indication"; + char buf[128]; + union iwreq_data wrqu; + + /* + * For AP case, keyid will have aid of STA which sent pkt with + * MIC error. Use this aid to get MAC & send it to hostapd. + */ + if (ar->arNetworkType == AP_NETWORK) { + sta_t *s = ieee80211_find_conn_for_aid(ar, keyid); + A_PRINTF("AP TKIP MIC error received from aid=%d\n", keyid); + snprintf(buf,sizeof(buf), "%s addr=%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x", + tag, s->mac[0],s->mac[1],s->mac[2],s->mac[3],s->mac[4],s->mac[5]); + } else { + A_PRINTF("AR6000 TKIP MIC error received for keyid %d %scast\n", + keyid, ismcast ? "multi": "uni"); + snprintf(buf, sizeof(buf), "%s(keyid=%d %sicast)", tag, keyid, + ismcast ? "mult" : "un"); + } + + memset(&wrqu, 0, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); +} + +void +ar6000_scanComplete_event(AR_SOFTC_T *ar, A_STATUS status) +{ + AR_DEBUG_PRINTF("AR6000 scan complete: %d\n", status); + ar->scan_complete = 1; + wake_up_interruptible(&ar6000_scan_queue); +} + +void +ar6000_targetStats_event(AR_SOFTC_T *ar, WMI_TARGET_STATS *pTarget) +{ + TARGET_STATS *pStats = &ar->arTargetStats; + A_UINT8 ac; + + A_PRINTF("AR6000 updating target stats\n"); + pStats->tx_packets += pTarget->txrxStats.tx_stats.tx_packets; + pStats->tx_bytes += pTarget->txrxStats.tx_stats.tx_bytes; + pStats->tx_unicast_pkts += pTarget->txrxStats.tx_stats.tx_unicast_pkts; + pStats->tx_unicast_bytes += pTarget->txrxStats.tx_stats.tx_unicast_bytes; + pStats->tx_multicast_pkts += pTarget->txrxStats.tx_stats.tx_multicast_pkts; + pStats->tx_multicast_bytes += pTarget->txrxStats.tx_stats.tx_multicast_bytes; + pStats->tx_broadcast_pkts += pTarget->txrxStats.tx_stats.tx_broadcast_pkts; + pStats->tx_broadcast_bytes += pTarget->txrxStats.tx_stats.tx_broadcast_bytes; + pStats->tx_rts_success_cnt += pTarget->txrxStats.tx_stats.tx_rts_success_cnt; + for(ac = 0; ac < WMM_NUM_AC; ac++) + pStats->tx_packet_per_ac[ac] += pTarget->txrxStats.tx_stats.tx_packet_per_ac[ac]; + pStats->tx_errors += pTarget->txrxStats.tx_stats.tx_errors; + pStats->tx_failed_cnt += pTarget->txrxStats.tx_stats.tx_failed_cnt; + pStats->tx_retry_cnt += pTarget->txrxStats.tx_stats.tx_retry_cnt; + pStats->tx_mult_retry_cnt += pTarget->txrxStats.tx_stats.tx_mult_retry_cnt; + pStats->tx_rts_fail_cnt += pTarget->txrxStats.tx_stats.tx_rts_fail_cnt; + pStats->tx_unicast_rate = wmi_get_rate(pTarget->txrxStats.tx_stats.tx_unicast_rate); + + pStats->rx_packets += pTarget->txrxStats.rx_stats.rx_packets; + pStats->rx_bytes += pTarget->txrxStats.rx_stats.rx_bytes; + pStats->rx_unicast_pkts += pTarget->txrxStats.rx_stats.rx_unicast_pkts; + pStats->rx_unicast_bytes += pTarget->txrxStats.rx_stats.rx_unicast_bytes; + pStats->rx_multicast_pkts += pTarget->txrxStats.rx_stats.rx_multicast_pkts; + pStats->rx_multicast_bytes += pTarget->txrxStats.rx_stats.rx_multicast_bytes; + pStats->rx_broadcast_pkts += pTarget->txrxStats.rx_stats.rx_broadcast_pkts; + pStats->rx_broadcast_bytes += pTarget->txrxStats.rx_stats.rx_broadcast_bytes; + pStats->rx_fragment_pkt += pTarget->txrxStats.rx_stats.rx_fragment_pkt; + pStats->rx_errors += pTarget->txrxStats.rx_stats.rx_errors; + pStats->rx_crcerr += pTarget->txrxStats.rx_stats.rx_crcerr; + pStats->rx_key_cache_miss += pTarget->txrxStats.rx_stats.rx_key_cache_miss; + pStats->rx_decrypt_err += pTarget->txrxStats.rx_stats.rx_decrypt_err; + pStats->rx_duplicate_frames += pTarget->txrxStats.rx_stats.rx_duplicate_frames; + pStats->rx_unicast_rate = wmi_get_rate(pTarget->txrxStats.rx_stats.rx_unicast_rate); + + + pStats->tkip_local_mic_failure + += pTarget->txrxStats.tkipCcmpStats.tkip_local_mic_failure; + pStats->tkip_counter_measures_invoked + += pTarget->txrxStats.tkipCcmpStats.tkip_counter_measures_invoked; + pStats->tkip_replays += pTarget->txrxStats.tkipCcmpStats.tkip_replays; + pStats->tkip_format_errors += pTarget->txrxStats.tkipCcmpStats.tkip_format_errors; + pStats->ccmp_format_errors += pTarget->txrxStats.tkipCcmpStats.ccmp_format_errors; + pStats->ccmp_replays += pTarget->txrxStats.tkipCcmpStats.ccmp_replays; + + + pStats->power_save_failure_cnt += pTarget->pmStats.power_save_failure_cnt; + pStats->noise_floor_calibation = pTarget->noise_floor_calibation; + + pStats->cs_bmiss_cnt += pTarget->cservStats.cs_bmiss_cnt; + pStats->cs_lowRssi_cnt += pTarget->cservStats.cs_lowRssi_cnt; + pStats->cs_connect_cnt += pTarget->cservStats.cs_connect_cnt; + pStats->cs_disconnect_cnt += pTarget->cservStats.cs_disconnect_cnt; + pStats->cs_aveBeacon_snr = pTarget->cservStats.cs_aveBeacon_snr; + pStats->cs_aveBeacon_rssi = pTarget->cservStats.cs_aveBeacon_rssi; + pStats->cs_lastRoam_msec = pTarget->cservStats.cs_lastRoam_msec; + pStats->cs_snr = pTarget->cservStats.cs_snr; + pStats->cs_rssi = pTarget->cservStats.cs_rssi; + + pStats->lq_val = pTarget->lqVal; + + pStats->wow_num_pkts_dropped += pTarget->wowStats.wow_num_pkts_dropped; + pStats->wow_num_host_pkt_wakeups += pTarget->wowStats.wow_num_host_pkt_wakeups; + pStats->wow_num_host_event_wakeups += pTarget->wowStats.wow_num_host_event_wakeups; + pStats->wow_num_events_discarded += pTarget->wowStats.wow_num_events_discarded; + + pStats->arp_received += pTarget->arpStats.arp_received; + pStats->arp_matched += pTarget->arpStats.arp_matched; + pStats->arp_replied += pTarget->arpStats.arp_replied; + + ar->statsUpdatePending = FALSE; + wake_up(&arEvent); +} + +void +ar6000_rssiThreshold_event(AR_SOFTC_T *ar, WMI_RSSI_THRESHOLD_VAL newThreshold, A_INT16 rssi) +{ + USER_RSSI_THOLD userRssiThold; + + /* Send an event to the app */ + userRssiThold.tag = ar->rssi_map[newThreshold].tag; + userRssiThold.rssi = rssi + SIGNAL_QUALITY_NOISE_FLOOR; + A_PRINTF("rssi Threshold range = %d tag = %d rssi = %d\n", newThreshold, + userRssiThold.tag, userRssiThold.rssi); + + ar6000_send_event_to_app(ar, WMI_RSSI_THRESHOLD_EVENTID,(A_UINT8 *)&userRssiThold, sizeof(USER_RSSI_THOLD)); +} + + +void +ar6000_hbChallengeResp_event(AR_SOFTC_T *ar, A_UINT32 cookie, A_UINT32 source) +{ + if (source == APP_HB_CHALLENGE) { + /* Report it to the app in case it wants a positive acknowledgement */ + ar6000_send_event_to_app(ar, WMIX_HB_CHALLENGE_RESP_EVENTID, + (A_UINT8 *)&cookie, sizeof(cookie)); + } else { + /* This would ignore the replys that come in after their due time */ + if (cookie == ar->arHBChallengeResp.seqNum) { + ar->arHBChallengeResp.outstanding = FALSE; + } + } +} + + +void +ar6000_reportError_event(AR_SOFTC_T *ar, WMI_TARGET_ERROR_VAL errorVal) +{ + char *errString[] = { + [WMI_TARGET_PM_ERR_FAIL] "WMI_TARGET_PM_ERR_FAIL", + [WMI_TARGET_KEY_NOT_FOUND] "WMI_TARGET_KEY_NOT_FOUND", + [WMI_TARGET_DECRYPTION_ERR] "WMI_TARGET_DECRYPTION_ERR", + [WMI_TARGET_BMISS] "WMI_TARGET_BMISS", + [WMI_PSDISABLE_NODE_JOIN] "WMI_PSDISABLE_NODE_JOIN" + }; + + A_PRINTF("AR6000 Error on Target. Error = 0x%x\n", errorVal); + + /* One error is reported at a time, and errorval is a bitmask */ + if(errorVal & (errorVal - 1)) + return; + + A_PRINTF("AR6000 Error type = "); + switch(errorVal) + { + case WMI_TARGET_PM_ERR_FAIL: + case WMI_TARGET_KEY_NOT_FOUND: + case WMI_TARGET_DECRYPTION_ERR: + case WMI_TARGET_BMISS: + case WMI_PSDISABLE_NODE_JOIN: + A_PRINTF("%s\n", errString[errorVal]); + break; + default: + A_PRINTF("INVALID\n"); + break; + } + +} + + +void +ar6000_cac_event(AR_SOFTC_T *ar, A_UINT8 ac, A_UINT8 cacIndication, + A_UINT8 statusCode, A_UINT8 *tspecSuggestion) +{ + WMM_TSPEC_IE *tspecIe; + + /* + * This is the TSPEC IE suggestion from AP. + * Suggestion provided by AP under some error + * cases, could be helpful for the host app. + * Check documentation. + */ + tspecIe = (WMM_TSPEC_IE *)tspecSuggestion; + + /* + * What do we do, if we get TSPEC rejection? One thought + * that comes to mind is implictly delete the pstream... + */ + A_PRINTF("AR6000 CAC notification. " + "AC = %d, cacIndication = 0x%x, statusCode = 0x%x\n", + ac, cacIndication, statusCode); +} + +void +ar6000_channel_change_event(AR_SOFTC_T *ar, A_UINT16 oldChannel, + A_UINT16 newChannel) +{ + A_PRINTF("Channel Change notification\nOld Channel: %d, New Channel: %d\n", + oldChannel, newChannel); +} + +#define AR6000_PRINT_BSSID(_pBss) do { \ + A_PRINTF("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",\ + (_pBss)[0],(_pBss)[1],(_pBss)[2],(_pBss)[3],\ + (_pBss)[4],(_pBss)[5]); \ +} while(0) + +void +ar6000_roam_tbl_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_TBL *pTbl) +{ + A_UINT8 i; + + A_PRINTF("ROAM TABLE NO OF ENTRIES is %d ROAM MODE is %d\n", + pTbl->numEntries, pTbl->roamMode); + for (i= 0; i < pTbl->numEntries; i++) { + A_PRINTF("[%d]bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", i, + pTbl->bssRoamInfo[i].bssid[0], pTbl->bssRoamInfo[i].bssid[1], + pTbl->bssRoamInfo[i].bssid[2], + pTbl->bssRoamInfo[i].bssid[3], + pTbl->bssRoamInfo[i].bssid[4], + pTbl->bssRoamInfo[i].bssid[5]); + A_PRINTF("RSSI %d RSSIDT %d LAST RSSI %d UTIL %d ROAM_UTIL %d" + " BIAS %d\n", + pTbl->bssRoamInfo[i].rssi, + pTbl->bssRoamInfo[i].rssidt, + pTbl->bssRoamInfo[i].last_rssi, + pTbl->bssRoamInfo[i].util, + pTbl->bssRoamInfo[i].roam_util, + pTbl->bssRoamInfo[i].bias); + } +} + +void +ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters, WMI_GET_WOW_LIST_REPLY *wow_reply) +{ + A_UINT8 i,j; + + /*Each event now contains exactly one filter, see bug 26613*/ + A_PRINTF("WOW pattern %d of %d patterns\n", wow_reply->this_filter_num, wow_reply->num_filters); + A_PRINTF("wow mode = %s host mode = %s\n", + (wow_reply->wow_mode == 0? "disabled":"enabled"), + (wow_reply->host_mode == 1 ? "awake":"asleep")); + + + /*If there are no patterns, the reply will only contain generic + WoW information. Pattern information will exist only if there are + patterns present. Bug 26716*/ + + /* If this event contains pattern information, display it*/ + if (wow_reply->this_filter_num) { + i=0; + A_PRINTF("id=%d size=%d offset=%d\n", + wow_reply->wow_filters[i].wow_filter_id, + wow_reply->wow_filters[i].wow_filter_size, + wow_reply->wow_filters[i].wow_filter_offset); + A_PRINTF("wow pattern = "); + for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) { + A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_pattern[j]); + } + + A_PRINTF("\nwow mask = "); + for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) { + A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_mask[j]); + } + A_PRINTF("\n"); + } +} + +/* + * Report the Roaming related data collected on the target + */ +void +ar6000_display_roam_time(WMI_TARGET_ROAM_TIME *p) +{ + A_PRINTF("Disconnect Data : BSSID: "); + AR6000_PRINT_BSSID(p->disassoc_bssid); + A_PRINTF(" RSSI %d DISASSOC Time %d NO_TXRX_TIME %d\n", + p->disassoc_bss_rssi,p->disassoc_time, + p->no_txrx_time); + A_PRINTF("Connect Data: BSSID: "); + AR6000_PRINT_BSSID(p->assoc_bssid); + A_PRINTF(" RSSI %d ASSOC Time %d TXRX_TIME %d\n", + p->assoc_bss_rssi,p->assoc_time, + p->allow_txrx_time); + A_PRINTF("Last Data Tx Time (b4 Disassoc) %d "\ + "First Data Tx Time (after Assoc) %d\n", + p->last_data_txrx_time, p->first_data_txrx_time); +} + +void +ar6000_roam_data_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_DATA *p) +{ + switch (p->roamDataType) { + case ROAM_DATA_TIME: + ar6000_display_roam_time(&p->u.roamTime); + break; + default: + break; + } +} + +void +ar6000_bssInfo_event_rx(AR_SOFTC_T *ar, A_UINT8 *datap, int len) +{ + struct sk_buff *skb; + WMI_BSS_INFO_HDR *bih = (WMI_BSS_INFO_HDR *)datap; + + + if (!ar->arMgmtFilter) { + return; + } + if (((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_BEACON) && + (bih->frameType != BEACON_FTYPE)) || + ((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_PROBE_RESP) && + (bih->frameType != PROBERESP_FTYPE))) + { + return; + } + + if ((skb = A_NETBUF_ALLOC_RAW(len)) != NULL) { + + A_NETBUF_PUT(skb, len); + A_MEMCPY(A_NETBUF_DATA(skb), datap, len); + skb->dev = ar->arNetDev; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) + A_MEMCPY(skb_mac_header(skb), A_NETBUF_DATA(skb), 6); +#else + skb->mac.raw = A_NETBUF_DATA(skb); +#endif + skb->ip_summed = CHECKSUM_NONE; + skb->pkt_type = PACKET_OTHERHOST; + skb->protocol = __constant_htons(0x0019); + netif_rx(skb); + } +} + +A_UINT32 wmiSendCmdNum; + +A_STATUS +ar6000_control_tx(void *devt, void *osbuf, HTC_ENDPOINT_ID eid) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + A_STATUS status = A_OK; + struct ar_cookie *cookie = NULL; + int i; + + /* take lock to protect ar6000_alloc_cookie() */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + do { + + AR_DEBUG2_PRINTF("ar_contrstatus = ol_tx: skb=0x%x, len=0x%x eid =%d\n", + (A_UINT32)osbuf, A_NETBUF_LEN(osbuf), eid); + + if (ar->arWMIControlEpFull && (eid == ar->arControlEp)) { + /* control endpoint is full, don't allocate resources, we + * are just going to drop this packet */ + cookie = NULL; + AR_DEBUG_PRINTF(" WMI Control EP full, dropping packet : 0x%X, len:%d \n", + (A_UINT32)osbuf, A_NETBUF_LEN(osbuf)); + } else { + cookie = ar6000_alloc_cookie(ar); + } + + if (cookie == NULL) { + status = A_NO_MEMORY; + break; + } + + if(logWmiRawMsgs) { + A_PRINTF("WMI cmd send, msgNo %d :", wmiSendCmdNum); + for(i = 0; i < a_netbuf_to_len(osbuf); i++) + A_PRINTF("%x ", ((A_UINT8 *)a_netbuf_to_data(osbuf))[i]); + A_PRINTF("\n"); + } + + wmiSendCmdNum++; + + } while (FALSE); + + if (cookie != NULL) { + /* got a structure to send it out on */ + ar->arTxPending[eid]++; + + if (eid != ar->arControlEp) { + ar->arTotalTxDataPending++; + } + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + if (cookie != NULL) { + cookie->arc_bp[0] = (A_UINT32)osbuf; + cookie->arc_bp[1] = 0; + SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt, + cookie, + A_NETBUF_DATA(osbuf), + A_NETBUF_LEN(osbuf), + eid, + AR6K_CONTROL_PKT_TAG); + /* this interface is asynchronous, if there is an error, cleanup will happen in the + * TX completion callback */ + HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt); + status = A_OK; + } + + return status; +} + +/* indicate tx activity or inactivity on a WMI stream */ +void ar6000_indicate_tx_activity(void *devt, A_UINT8 TrafficClass, A_BOOL Active) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + HTC_ENDPOINT_ID eid ; + int i; + + if (ar->arWmiEnabled) { + eid = arAc2EndpointID(ar, TrafficClass); + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + ar->arAcStreamActive[TrafficClass] = Active; + + if (Active) { + /* when a stream goes active, keep track of the active stream with the highest priority */ + + if (ar->arAcStreamPriMap[TrafficClass] > ar->arHiAcStreamActivePri) { + /* set the new highest active priority */ + ar->arHiAcStreamActivePri = ar->arAcStreamPriMap[TrafficClass]; + } + + } else { + /* when a stream goes inactive, we may have to search for the next active stream + * that is the highest priority */ + + if (ar->arHiAcStreamActivePri == ar->arAcStreamPriMap[TrafficClass]) { + + /* the highest priority stream just went inactive */ + + /* reset and search for the "next" highest "active" priority stream */ + ar->arHiAcStreamActivePri = 0; + for (i = 0; i < WMM_NUM_AC; i++) { + if (ar->arAcStreamActive[i]) { + if (ar->arAcStreamPriMap[i] > ar->arHiAcStreamActivePri) { + /* set the new highest active priority */ + ar->arHiAcStreamActivePri = ar->arAcStreamPriMap[i]; + } + } + } + } + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + } else { + /* for mbox ping testing, the traffic class is mapped directly as a stream ID, + * see handling of AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE in ioctl.c */ + eid = (HTC_ENDPOINT_ID)TrafficClass; + } + + /* notify HTC, this may cause credit distribution changes */ + + HTCIndicateActivityChange(ar->arHtcTarget, + eid, + Active); + +} + +module_init(ar6000_init_module); +module_exit(ar6000_cleanup_module); + +/* Init cookie queue */ +static void +ar6000_cookie_init(AR_SOFTC_T *ar) +{ + A_UINT32 i; + + ar->arCookieList = NULL; + A_MEMZERO(s_ar_cookie_mem, sizeof(s_ar_cookie_mem)); + + for (i = 0; i < MAX_COOKIE_NUM; i++) { + ar6000_free_cookie(ar, &s_ar_cookie_mem[i]); + } +} + +/* cleanup cookie queue */ +static void +ar6000_cookie_cleanup(AR_SOFTC_T *ar) +{ + /* It is gone .... */ + ar->arCookieList = NULL; +} + +/* Init cookie queue */ +static void +ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie) +{ + /* Insert first */ + A_ASSERT(ar != NULL); + A_ASSERT(cookie != NULL); + cookie->arc_list_next = ar->arCookieList; + ar->arCookieList = cookie; +} + +/* cleanup cookie queue */ +static struct ar_cookie * +ar6000_alloc_cookie(AR_SOFTC_T *ar) +{ + struct ar_cookie *cookie; + + cookie = ar->arCookieList; + if(cookie != NULL) + { + ar->arCookieList = cookie->arc_list_next; + } + + return cookie; +} + +#ifdef SEND_EVENT_TO_APP +/* + * This function is used to send event which come from taget to + * the application. The buf which send to application is include + * the event ID and event content. + */ +#define EVENT_ID_LEN 2 +void ar6000_send_event_to_app(AR_SOFTC_T *ar, A_UINT16 eventId, + A_UINT8 *datap, int len) +{ + +#if (WIRELESS_EXT >= 15) + +/* note: IWEVCUSTOM only exists in wireless extensions after version 15 */ + + char *buf; + A_UINT16 size; + union iwreq_data wrqu; + + size = len + EVENT_ID_LEN; + + if (size > IW_CUSTOM_MAX) { + AR_DEBUG_PRINTF("WMI event ID : 0x%4.4X, len = %d too big for IWEVCUSTOM (max=%d) \n", + eventId, size, IW_CUSTOM_MAX); + return; + } + + buf = A_MALLOC_NOWAIT(size); + A_MEMZERO(buf, size); + A_MEMCPY(buf, &eventId, EVENT_ID_LEN); + A_MEMCPY(buf+EVENT_ID_LEN, datap, len); + + //AR_DEBUG_PRINTF("event ID = %d,len = %d\n",*(A_UINT16*)buf, size); + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = size; + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + + A_FREE(buf); +#endif + + +} +#endif + + +void +ar6000_tx_retry_err_event(void *devt) +{ + AR_DEBUG2_PRINTF("Tx retries reach maximum!\n"); +} + +void +ar6000_snrThresholdEvent_rx(void *devt, WMI_SNR_THRESHOLD_VAL newThreshold, A_UINT8 snr) +{ + WMI_SNR_THRESHOLD_EVENT event; + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + event.range = newThreshold; + event.snr = snr; + + ar6000_send_event_to_app(ar, WMI_SNR_THRESHOLD_EVENTID, (A_UINT8 *)&event, + sizeof(WMI_SNR_THRESHOLD_EVENT)); +} + +void +ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL newThreshold, A_UINT8 lq) +{ + AR_DEBUG2_PRINTF("lq threshold range %d, lq %d\n", newThreshold, lq); +} + + + +A_UINT32 +a_copy_to_user(void *to, const void *from, A_UINT32 n) +{ + return(copy_to_user(to, from, n)); +} + +A_UINT32 +a_copy_from_user(void *to, const void *from, A_UINT32 n) +{ + return(copy_from_user(to, from, n)); +} + + +A_STATUS +ar6000_get_driver_cfg(struct net_device *dev, + A_UINT16 cfgParam, + void *result) +{ + + A_STATUS ret = 0; + + switch(cfgParam) + { + case AR6000_DRIVER_CFG_GET_WLANNODECACHING: + *((A_UINT32 *)result) = wlanNodeCaching; + break; + case AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS: + *((A_UINT32 *)result) = logWmiRawMsgs; + break; + default: + ret = EINVAL; + break; + } + + return ret; +} + +void +ar6000_keepalive_rx(void *devt, A_UINT8 configured) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arKeepaliveConfigured = configured; + wake_up(&arEvent); +} + +void +ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID, WMI_PMKID *pmkidList, + A_UINT8 *bssidList) +{ + A_UINT8 i, j; + + A_PRINTF("Number of Cached PMKIDs is %d\n", numPMKID); + + for (i = 0; i < numPMKID; i++) { + A_PRINTF("\nBSSID %d ", i); + for (j = 0; j < ATH_MAC_LEN; j++) { + A_PRINTF("%2.2x", bssidList[j]); + } + bssidList += (ATH_MAC_LEN + WMI_PMKID_LEN); + A_PRINTF("\nPMKID %d ", i); + for (j = 0; j < WMI_PMKID_LEN; j++) { + A_PRINTF("%2.2x", pmkidList->pmkid[j]); + } + pmkidList = (WMI_PMKID *)((A_UINT8 *)pmkidList + ATH_MAC_LEN + + WMI_PMKID_LEN); + } +} + +void ar6000_pspoll_event(AR_SOFTC_T *ar,A_UINT8 aid) +{ + sta_t *conn=NULL; + A_BOOL isPsqEmpty = FALSE; + + conn = ieee80211_find_conn_for_aid(ar, aid); + + /* If the PS q for this STA is not empty, dequeue and send a pkt from + * the head of the q. Also update the More data bit in the WMI_DATA_HDR + * if there are more pkts for this STA in the PS q. If there are no more + * pkts for this STA, update the PVB for this STA. + */ + A_MUTEX_LOCK(&conn->psqLock); + isPsqEmpty = A_NETBUF_QUEUE_EMPTY(&conn->psq); + A_MUTEX_UNLOCK(&conn->psqLock); + + if (isPsqEmpty) { + /* TODO:No buffered pkts for this STA. Send out a NULL data frame */ + } else { + struct sk_buff *skb = NULL; + + A_MUTEX_LOCK(&conn->psqLock); + skb = A_NETBUF_DEQUEUE(&conn->psq); + A_MUTEX_UNLOCK(&conn->psqLock); + /* Set the STA flag to PSPolled, so that the frame will go out */ + STA_SET_PS_POLLED(conn); + ar6000_data_tx(skb, ar->arNetDev); + STA_CLR_PS_POLLED(conn); + + /* Clear the PVB for this STA if the queue has become empty */ + A_MUTEX_LOCK(&conn->psqLock); + isPsqEmpty = A_NETBUF_QUEUE_EMPTY(&conn->psq); + A_MUTEX_UNLOCK(&conn->psqLock); + + if (isPsqEmpty) { + wmi_set_pvb_cmd(ar->arWmi, conn->aid, 0); + } + } +} + +void ar6000_dtimexpiry_event(AR_SOFTC_T *ar) +{ + A_BOOL isMcastQueued = FALSE; + struct sk_buff *skb = NULL; + + A_MUTEX_LOCK(&ar->mcastpsqLock); + isMcastQueued = A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq); + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + + A_ASSERT(isMcastQueued == FALSE); + + /* Flush the mcast psq to the target */ + /* Set the STA flag to DTIMExpired, so that the frame will go out */ + ar->DTIMExpired = TRUE; + + A_MUTEX_LOCK(&ar->mcastpsqLock); + while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) { + skb = A_NETBUF_DEQUEUE(&ar->mcastpsq); + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + + ar6000_data_tx(skb, ar->arNetDev); + + A_MUTEX_LOCK(&ar->mcastpsqLock); + } + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + + /* Reset the DTIMExpired flag back to 0 */ + ar->DTIMExpired = FALSE; + + /* Clear the LSB of the BitMapCtl field of the TIM IE */ + wmi_set_pvb_cmd(ar->arWmi, MCAST_AID, 0); +} + +#ifdef USER_KEYS +static A_STATUS + +ar6000_reinstall_keys(AR_SOFTC_T *ar, A_UINT8 key_op_ctrl) +{ + A_STATUS status = A_OK; + struct ieee80211req_key *uik = &ar->user_saved_keys.ucast_ik; + struct ieee80211req_key *bik = &ar->user_saved_keys.bcast_ik; + CRYPTO_TYPE keyType = ar->user_saved_keys.keyType; + + if (IEEE80211_CIPHER_CCKM_KRK != uik->ik_type) { + if (NONE_CRYPT == keyType) { + goto _reinstall_keys_out; + } + + if (uik->ik_keylen) { + status = wmi_addKey_cmd(ar->arWmi, uik->ik_keyix, + ar->user_saved_keys.keyType, PAIRWISE_USAGE, + uik->ik_keylen, (A_UINT8 *)&uik->ik_keyrsc, + uik->ik_keydata, key_op_ctrl, uik->ik_macaddr, SYNC_BEFORE_WMIFLAG); + } + + } else { + status = wmi_add_krk_cmd(ar->arWmi, uik->ik_keydata); + } + + if (IEEE80211_CIPHER_CCKM_KRK != bik->ik_type) { + if (NONE_CRYPT == keyType) { + goto _reinstall_keys_out; + } + + if (bik->ik_keylen) { + status = wmi_addKey_cmd(ar->arWmi, bik->ik_keyix, + ar->user_saved_keys.keyType, GROUP_USAGE, + bik->ik_keylen, (A_UINT8 *)&bik->ik_keyrsc, + bik->ik_keydata, key_op_ctrl, bik->ik_macaddr, NO_SYNC_WMIFLAG); + } + } else { + status = wmi_add_krk_cmd(ar->arWmi, bik->ik_keydata); + } + +_reinstall_keys_out: + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT; + ar->user_key_ctrl = 0; + + return status; +} +#endif /* USER_KEYS */ + + +void +ar6000_dset_open_req( + void *context, + A_UINT32 id, + A_UINT32 targHandle, + A_UINT32 targReplyFn, + A_UINT32 targReplyArg) +{ +} + +void +ar6000_dset_close( + void *context, + A_UINT32 access_cookie) +{ + return; +} + +void +ar6000_dset_data_req( + void *context, + A_UINT32 accessCookie, + A_UINT32 offset, + A_UINT32 length, + A_UINT32 targBuf, + A_UINT32 targReplyFn, + A_UINT32 targReplyArg) +{ +} + +int +ar6000_ap_mode_profile_commit(struct ar6_softc *ar) +{ + WMI_CONNECT_CMD p; + struct ieee80211req_key *ik; + CRYPTO_TYPE keyType = NONE_CRYPT; + + /* No change in AP's profile configuration */ + if(ar->ap_profile_flag==0) { + A_PRINTF("COMMIT: No change in profile!!!\n"); + return -ENODATA; + } + + if(!ar->arSsidLen) { + A_PRINTF("SSID not set!!!\n"); + return -ECHRNG; + } + + if(!ar->arChannelHint) { + /* Without channel info, can't start AP */ + A_PRINTF("Channel not set!!!\n"); + return -ECHRNG; + } + + if(ar->arPairwiseCrypto != ar->arGroupCrypto) { + A_PRINTF("Mixed cipher not supported in AP mode\n"); + return -EOPNOTSUPP; + } + + switch(ar->arAuthMode) { + case NONE_AUTH: + if((ar->arPairwiseCrypto != NONE_CRYPT) && + (ar->arPairwiseCrypto != WEP_CRYPT)) { + A_PRINTF("Cipher not supported in AP mode Open auth\n"); + return -EOPNOTSUPP; + } + break; + case WPA_PSK_AUTH: + if(ar->arPairwiseCrypto != TKIP_CRYPT) { + A_PRINTF("Cipher not supported in AP mode WPA\n"); + return -EOPNOTSUPP; + } + break; + case WPA2_PSK_AUTH: + if(ar->arPairwiseCrypto != AES_CRYPT) { + A_PRINTF("Cipher not supported in AP mode WPA2\n"); + return -EOPNOTSUPP; + } + break; + case WPA_AUTH: + case WPA2_AUTH: + case WPA_AUTH_CCKM: + case WPA2_AUTH_CCKM: + A_PRINTF("This key mgmt type not supported in AP mode\n"); + return -EOPNOTSUPP; + } + + /* Update the arNetworkType */ + ar->arNetworkType = ar->arNextMode; + + A_MEMZERO(&p,sizeof(p)); + p.ssidLength = ar->arSsidLen; + A_MEMCPY(p.ssid,ar->arSsid,p.ssidLength); + p.channel = ar->arChannelHint; + p.networkType = ar->arNetworkType; + + p.dot11AuthMode = ar->arDot11AuthMode; + p.authMode = ar->arAuthMode; + p.pairwiseCryptoType = ar->arPairwiseCrypto; + p.pairwiseCryptoLen = ar->arPairwiseCryptoLen; + p.groupCryptoType = ar->arGroupCrypto; + p.groupCryptoLen = ar->arGroupCryptoLen; + p.ctrl_flags = ar->arConnectCtrlFlags; + + wmi_ap_profile_commit(ar->arWmi, &p); + ar->arConnected = TRUE; + ar->ap_profile_flag = 0; + + switch(ar->arAuthMode) { + case NONE_AUTH: + if(ar->arPairwiseCrypto == WEP_CRYPT) { + ar6000_install_static_wep_keys(ar); + } + break; + case WPA_PSK_AUTH: + case WPA2_PSK_AUTH: + ik = &ar->ap_mode_bkey; + switch (ik->ik_type) { + case IEEE80211_CIPHER_TKIP: + keyType = TKIP_CRYPT; + break; + case IEEE80211_CIPHER_AES_CCM: + keyType = AES_CRYPT; + break; + default: + goto skip_key; + } + wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, GROUP_USAGE, + ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc, + ik->ik_keydata, KEY_OP_INIT_VAL, ik->ik_macaddr, + SYNC_BOTH_WMIFLAG); + + break; + } + +skip_key: + return 0; +} + +A_STATUS +ar6000_ap_mode_get_wpa_ie(struct ar6_softc *ar, struct ieee80211req_wpaie *wpaie) +{ + sta_t *conn = NULL; + conn = ieee80211_find_conn(ar, wpaie->wpa_macaddr); + + A_MEMZERO(wpaie->wpa_ie, IEEE80211_MAX_IE); + A_MEMZERO(wpaie->rsn_ie, IEEE80211_MAX_IE); + + if(conn) { + A_MEMCPY(wpaie->wpa_ie, conn->wpa_ie, IEEE80211_MAX_IE); + } + + return 0; +} + +A_STATUS +is_iwioctl_allowed(A_UINT8 mode, A_UINT16 cmd) +{ + if(cmd >= SIOCSIWCOMMIT && cmd <= SIOCGIWPOWER) { + cmd -= SIOCSIWCOMMIT; + if(sioctl_filter[cmd] == 0xFF) return A_OK; + if(sioctl_filter[cmd] & mode) return A_OK; + } else if(cmd >= SIOCIWFIRSTPRIV && cmd <= (SIOCIWFIRSTPRIV+30)) { + cmd -= SIOCIWFIRSTPRIV; + if(pioctl_filter[cmd] == 0xFF) return A_OK; + if(pioctl_filter[cmd] & mode) return A_OK; + } else { + return A_ERROR; + } + return A_ENOTSUP; +} + +A_STATUS +is_xioctl_allowed(A_UINT8 mode, int cmd) +{ + if(sizeof(xioctl_filter)-1 < cmd) { + A_PRINTF("Filter for this cmd=%d not defined\n",cmd); + return 0; + } + if(xioctl_filter[cmd] == 0xFF) return A_OK; + if(xioctl_filter[cmd] & mode) return A_OK; + return A_ERROR; +} +void ar6000_peer_event( + void *context, + A_UINT8 eventCode, + A_UINT8 *macAddr) +{ + A_UINT8 pos; + + for (pos=0;pos<6;pos++) + printk("%02x: ",*(macAddr+pos)); + printk("\n"); +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k/ar6000_drv.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6000_drv.h --- linux-2.6.26/drivers/net/wireless/ath6k/ar6000_drv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6000_drv.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,444 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _AR6000_H_ +#define _AR6000_H_ + +#include + + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,17) +#include +#else +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) +#include +#else +#include +#endif +#include +#include +#include + +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "htc_api.h" +#include "wmi.h" +#include "a_drv.h" +#include "bmi.h" +#include "ieee80211.h" +#include "ieee80211_ioctl.h" +#include "wlan_api.h" +#include "wmi_api.h" +#include "gpio_api.h" +#include "gpio.h" +#include "host_version.h" +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +#include +#else +#include +#include +#endif +#include "mbox_host_reg.h" +#include "mbox_reg.h" +#include "rtc_reg.h" +#include "ar6000_api.h" +#ifdef CONFIG_HOST_TCMD_SUPPORT +#include "testcmd.h" +#endif + +#include "targaddrs.h" +#include "dbglog_api.h" +#include "ar6000_diag.h" +#include "common_drv.h" +#include "roaming.h" + +#ifndef __dev_put +#define __dev_put(dev) dev_put(dev) +#endif + + +#ifdef USER_KEYS + +#define USER_SAVEDKEYS_STAT_INIT 0 +#define USER_SAVEDKEYS_STAT_RUN 1 + +// TODO this needs to move into the AR_SOFTC struct +struct USER_SAVEDKEYS { + struct ieee80211req_key ucast_ik; + struct ieee80211req_key bcast_ik; + CRYPTO_TYPE keyType; + A_BOOL keyOk; +}; +#endif + +#define DBG_INFO 0x00000001 +#define DBG_ERROR 0x00000002 +#define DBG_WARNING 0x00000004 +#define DBG_SDIO 0x00000008 +#define DBG_HIF 0x00000010 +#define DBG_HTC 0x00000020 +#define DBG_WMI 0x00000040 +#define DBG_WMI2 0x00000080 +#define DBG_DRIVER 0x00000100 + +#define DBG_DEFAULTS (DBG_ERROR|DBG_WARNING) + + +#ifdef DEBUG +#define AR_DEBUG_PRINTF(args...) if (debugdriver) A_PRINTF(args); +#define AR_DEBUG2_PRINTF(args...) if (debugdriver >= 2) A_PRINTF(args); +extern int debugdriver; +#else +#define AR_DEBUG_PRINTF(args...) +#define AR_DEBUG2_PRINTF(args...) +#endif + +A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); +A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAX_AR6000 1 +#define AR6000_MAX_RX_BUFFERS 16 +#define AR6000_BUFFER_SIZE 1664 +#define AR6000_TX_TIMEOUT 10 +#define AR6000_ETH_ADDR_LEN 6 +#define AR6000_MAX_ENDPOINTS 4 +#define MAX_NODE_NUM 15 +#define MAX_COOKIE_NUM 150 +#define AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT 1 +#define AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT 1 + +enum { + DRV_HB_CHALLENGE = 0, + APP_HB_CHALLENGE +}; + +/* HTC RAW streams */ +typedef enum _HTC_RAW_STREAM_ID { + HTC_RAW_STREAM_NOT_MAPPED = -1, + HTC_RAW_STREAM_0 = 0, + HTC_RAW_STREAM_1 = 1, + HTC_RAW_STREAM_2 = 2, + HTC_RAW_STREAM_3 = 3, + HTC_RAW_STREAM_NUM_MAX +} HTC_RAW_STREAM_ID; + +#define RAW_HTC_READ_BUFFERS_NUM 4 +#define RAW_HTC_WRITE_BUFFERS_NUM 4 + +typedef struct { + int currPtr; + int length; + unsigned char data[AR6000_BUFFER_SIZE]; + HTC_PACKET HTCPacket; +} raw_htc_buffer; + +#ifdef CONFIG_HOST_TCMD_SUPPORT +/* + * add TCMD_MODE besides wmi and bypasswmi + * in TCMD_MODE, only few TCMD releated wmi commands + * counld be hanlder + */ +enum { + AR6000_WMI_MODE = 0, + AR6000_BYPASS_MODE, + AR6000_TCMD_MODE, + AR6000_WLAN_MODE +}; +#endif /* CONFIG_HOST_TCMD_SUPPORT */ + +struct ar_wep_key { + A_UINT8 arKeyIndex; + A_UINT8 arKeyLen; + A_UINT8 arKey[64]; +} ; + +struct ar_node_mapping { + A_UINT8 macAddress[6]; + A_UINT8 epId; + A_UINT8 txPending; +}; + +struct ar_cookie { + A_UINT32 arc_bp[2]; /* Must be first field */ + HTC_PACKET HtcPkt; /* HTC packet wrapper */ + struct ar_cookie *arc_list_next; +}; + +struct ar_hb_chlng_resp { + A_TIMER timer; + A_UINT32 frequency; + A_UINT32 seqNum; + A_BOOL outstanding; + A_UINT8 missCnt; + A_UINT8 missThres; +}; + +/* Per STA data, used in AP mode */ +/*TODO: All this should move to OS independent dir */ + +#define STA_PWR_MGMT_MASK 0x1 +#define STA_PWR_MGMT_SHIFT 0x0 +#define STA_PWR_MGMT_AWAKE 0x0 +#define STA_PWR_MGMT_SLEEP 0x1 + +#define STA_SET_PWR_SLEEP(sta) (sta->flags |= (STA_PWR_MGMT_MASK << STA_PWR_MGMT_SHIFT)) +#define STA_CLR_PWR_SLEEP(sta) (sta->flags &= ~(STA_PWR_MGMT_MASK << STA_PWR_MGMT_SHIFT)) +#define STA_IS_PWR_SLEEP(sta) ((sta->flags >> STA_PWR_MGMT_SHIFT) & STA_PWR_MGMT_MASK) + +#define STA_PS_POLLED_MASK 0x1 +#define STA_PS_POLLED_SHIFT 0x1 +#define STA_SET_PS_POLLED(sta) (sta->flags |= (STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT)) +#define STA_CLR_PS_POLLED(sta) (sta->flags &= ~(STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT)) +#define STA_IS_PS_POLLED(sta) (sta->flags & (STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT)) + +typedef struct { + A_UINT16 flags; + A_UINT8 mac[ATH_MAC_LEN]; + A_UINT8 aid; + A_UINT8 wpa_ie[IEEE80211_MAX_IE]; + A_NETBUF_QUEUE_T psq; /* power save q */ + A_MUTEX_T psqLock; +} sta_t; + +typedef struct ar6_softc { + struct net_device *arNetDev; /* net_device pointer */ + void *arWmi; + int arTxPending[ENDPOINT_MAX]; + int arTotalTxDataPending; + A_UINT8 arNumDataEndPts; + A_BOOL arWmiEnabled; + A_BOOL arWmiReady; + A_BOOL arConnected; + HTC_HANDLE arHtcTarget; + void *arHifDevice; + spinlock_t arLock; + struct compat_semaphore arSem; + int arRxBuffers[ENDPOINT_MAX]; + int arSsidLen; + u_char arSsid[32]; + A_UINT8 arNextMode; + A_UINT8 arNetworkType; + A_UINT8 arDot11AuthMode; + A_UINT8 arAuthMode; + A_UINT8 arPairwiseCrypto; + A_UINT8 arPairwiseCryptoLen; + A_UINT8 arGroupCrypto; + A_UINT8 arGroupCryptoLen; + A_UINT8 arDefTxKeyIndex; + struct ar_wep_key arWepKeyList[WMI_MAX_KEY_INDEX + 1]; + A_UINT8 arBssid[6]; + A_UINT8 arReqBssid[6]; + A_UINT16 arChannelHint; + A_UINT16 arBssChannel; + A_UINT16 arListenInterval; + struct ar6000_version arVersion; + A_UINT32 arTargetType; + A_INT8 arRssi; + A_UINT8 arTxPwr; + A_BOOL arTxPwrSet; + A_INT32 arBitRate; + struct net_device_stats arNetStats; + struct iw_statistics arIwStats; + A_INT8 arNumChannels; + A_UINT16 arChannelList[32]; + A_UINT32 arRegCode; + A_BOOL statsUpdatePending; + TARGET_STATS arTargetStats; + A_INT8 arMaxRetries; + A_UINT8 arPhyCapability; +#ifdef CONFIG_HOST_TCMD_SUPPORT + A_UINT8 tcmdRxReport; + A_UINT32 tcmdRxTotalPkt; + A_INT32 tcmdRxRssi; + A_UINT32 tcmdPm; + A_UINT32 arTargetMode; + A_UINT32 tcmdRxcrcErrPkt; + A_UINT32 tcmdRxsecErrPkt; +#endif + AR6000_WLAN_STATE arWlanState; + struct ar_node_mapping arNodeMap[MAX_NODE_NUM]; + A_UINT8 arIbssPsEnable; + A_UINT8 arNodeNum; + A_UINT8 arNexEpId; + struct ar_cookie *arCookieList; + A_UINT16 arRateMask; + A_UINT8 arSkipScan; + A_UINT16 arBeaconInterval; + A_BOOL arConnectPending; + A_BOOL arWmmEnabled; + struct ar_hb_chlng_resp arHBChallengeResp; + A_UINT8 arKeepaliveConfigured; + A_UINT32 arMgmtFilter; + HTC_ENDPOINT_ID arAc2EpMapping[WMM_NUM_AC]; + A_BOOL arAcStreamActive[WMM_NUM_AC]; + A_UINT8 arAcStreamPriMap[WMM_NUM_AC]; + A_UINT8 arHiAcStreamActivePri; + A_UINT8 arEp2AcMapping[ENDPOINT_MAX]; + HTC_ENDPOINT_ID arControlEp; +#ifdef HTC_RAW_INTERFACE + HTC_ENDPOINT_ID arRaw2EpMapping[HTC_RAW_STREAM_NUM_MAX]; + HTC_RAW_STREAM_ID arEp2RawMapping[ENDPOINT_MAX]; + struct compat_semaphore raw_htc_read_sem[HTC_RAW_STREAM_NUM_MAX]; + struct compat_semaphore raw_htc_write_sem[HTC_RAW_STREAM_NUM_MAX]; + wait_queue_head_t raw_htc_read_queue[HTC_RAW_STREAM_NUM_MAX]; + wait_queue_head_t raw_htc_write_queue[HTC_RAW_STREAM_NUM_MAX]; + raw_htc_buffer raw_htc_read_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_READ_BUFFERS_NUM]; + raw_htc_buffer raw_htc_write_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_WRITE_BUFFERS_NUM]; + A_BOOL write_buffer_available[HTC_RAW_STREAM_NUM_MAX]; + A_BOOL read_buffer_available[HTC_RAW_STREAM_NUM_MAX]; +#endif + A_BOOL arNetQueueStopped; + A_BOOL arRawIfInit; + int arDeviceIndex; + COMMON_CREDIT_STATE_INFO arCreditStateInfo; + A_BOOL arWMIControlEpFull; + A_BOOL dbgLogFetchInProgress; + A_UCHAR log_buffer[DBGLOG_HOST_LOG_BUFFER_SIZE]; + A_UINT32 log_cnt; + A_UINT32 dbglog_init_done; + A_UINT32 arConnectCtrlFlags; +#ifdef USER_KEYS + A_INT32 user_savedkeys_stat; + A_UINT32 user_key_ctrl; + struct USER_SAVEDKEYS user_saved_keys; +#endif + A_UINT32 scan_complete; + USER_RSSI_THOLD rssi_map[12]; + A_UINT16 ap_profile_flag; /* AP mode */ + WMI_AP_ACL g_acl; /* AP mode */ + sta_t sta_list[AP_MAX_NUM_STA]; /* AP mode */ + A_UINT8 sta_list_index; /* AP mode */ + struct ieee80211req_key ap_mode_bkey; /* AP mode */ + A_NETBUF_QUEUE_T mcastpsq; /* power save q for Mcast frames */ + A_MUTEX_T mcastpsqLock; + A_BOOL DTIMExpired; /* flag to indicate DTIM expired */ + A_UINT8 intra_bss; /* enable/disable intra bss data forward */ +} AR_SOFTC_T; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +/* Looks like we need this for 2.4 kernels */ +static inline void *netdev_priv(struct net_device *dev) +{ + return(dev->priv); +} +#endif + +#define arAc2EndpointID(ar,ac) (ar)->arAc2EpMapping[(ac)] +#define arSetAc2EndpointIDMap(ar,ac,ep) \ +{ (ar)->arAc2EpMapping[(ac)] = (ep); \ + (ar)->arEp2AcMapping[(ep)] = (ac); } +#define arEndpoint2Ac(ar,ep) (ar)->arEp2AcMapping[(ep)] + +#define arRawIfEnabled(ar) (ar)->arRawIfInit +#define arRawStream2EndpointID(ar,raw) (ar)->arRaw2EpMapping[(raw)] +#define arSetRawStream2EndpointIDMap(ar,raw,ep) \ +{ (ar)->arRaw2EpMapping[(raw)] = (ep); \ + (ar)->arEp2RawMapping[(ep)] = (raw); } +#define arEndpoint2RawStreamID(ar,ep) (ar)->arEp2RawMapping[(ep)] + +struct ar_giwscan_param { + char *current_ev; + char *end_buf; + A_UINT32 bytes_needed; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + struct iw_request_info *info; +#endif +}; + +#define AR6000_STAT_INC(ar, stat) (ar->arNetStats.stat++) + +#define AR6000_SPIN_LOCK(lock, param) do { \ + if (irqs_disabled()) { \ + AR_DEBUG_PRINTF("IRQs disabled:AR6000_LOCK\n"); \ + } \ + spin_lock_bh(lock); \ +} while (0) + +#define AR6000_SPIN_UNLOCK(lock, param) do { \ + if (irqs_disabled()) { \ + AR_DEBUG_PRINTF("IRQs disabled: AR6000_UNLOCK\n"); \ + } \ + spin_unlock_bh(lock); \ +} while (0) + +int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); +int ar6000_ioctl_dispatcher(struct net_device *dev, struct ifreq *rq, int cmd); +void ar6000_gpio_init(void); +void ar6000_init_profile_info(AR_SOFTC_T *ar); +void ar6000_install_static_wep_keys(AR_SOFTC_T *ar); +int ar6000_init(struct net_device *dev); +int ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar); +void ar6000_TxDataCleanup(AR_SOFTC_T *ar); + +#ifdef HTC_RAW_INTERFACE + +#ifndef __user +#define __user +#endif + +int ar6000_htc_raw_open(AR_SOFTC_T *ar); +int ar6000_htc_raw_close(AR_SOFTC_T *ar); +ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar, + HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t count); +ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar, + HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t count); + +#endif /* HTC_RAW_INTERFACE */ + +/* AP mode */ +/*TODO: These routines should be moved to a file that is common across OS */ +sta_t * +ieee80211_find_conn(AR_SOFTC_T *ar, A_UINT8 *node_addr); + +sta_t * +ieee80211_find_conn_for_aid(AR_SOFTC_T *ar, A_UINT8 aid); + +A_UINT8 +remove_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 reason); + +#ifdef __cplusplus +} +#endif + +#endif /* _AR6000_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/ar6000_raw_if.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6000_raw_if.c --- linux-2.6.26/drivers/net/wireless/ath6k/ar6000_raw_if.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6000_raw_if.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,443 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#include "ar6000_drv.h" + +#ifdef HTC_RAW_INTERFACE + +static void +ar6000_htc_raw_read_cb(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + raw_htc_buffer *busy; + HTC_RAW_STREAM_ID streamID; + + busy = (raw_htc_buffer *)pPacket->pPktContext; + A_ASSERT(busy != NULL); + + if (pPacket->Status == A_ECANCELED) { + /* + * HTC provides A_ECANCELED status when it doesn't want to be refilled + * (probably due to a shutdown) + */ + return; + } + + streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint); + A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED); + +#ifdef CF + if (down_trylock(&ar->raw_htc_read_sem[streamID])) { +#else + if (down_interruptible(&ar->raw_htc_read_sem[streamID])) { +#endif /* CF */ + AR_DEBUG2_PRINTF("Unable to down the semaphore\n"); + } + + A_ASSERT((pPacket->Status != A_OK) || + (pPacket->pBuffer == (busy->data + HTC_HEADER_LEN))); + + busy->length = pPacket->ActualLength + HTC_HEADER_LEN; + busy->currPtr = HTC_HEADER_LEN; + ar->read_buffer_available[streamID] = TRUE; + //AR_DEBUG_PRINTF("raw read cb: 0x%X 0x%X \n", busy->currPtr,busy->length); + up(&ar->raw_htc_read_sem[streamID]); + + /* Signal the waiting process */ + AR_DEBUG2_PRINTF("Waking up the StreamID(%d) read process\n", streamID); + wake_up_interruptible(&ar->raw_htc_read_queue[streamID]); +} + +static void +ar6000_htc_raw_write_cb(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + raw_htc_buffer *free; + HTC_RAW_STREAM_ID streamID; + + free = (raw_htc_buffer *)pPacket->pPktContext; + A_ASSERT(free != NULL); + + if (pPacket->Status == A_ECANCELED) { + /* + * HTC provides A_ECANCELED status when it doesn't want to be refilled + * (probably due to a shutdown) + */ + return; + } + + streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint); + A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED); + +#ifdef CF + if (down_trylock(&ar->raw_htc_write_sem[streamID])) { +#else + if (down_interruptible(&ar->raw_htc_write_sem[streamID])) { +#endif + AR_DEBUG2_PRINTF("Unable to down the semaphore\n"); + } + + A_ASSERT(pPacket->pBuffer == (free->data + HTC_HEADER_LEN)); + + free->length = 0; + ar->write_buffer_available[streamID] = TRUE; + up(&ar->raw_htc_write_sem[streamID]); + + /* Signal the waiting process */ + AR_DEBUG2_PRINTF("Waking up the StreamID(%d) write process\n", streamID); + wake_up_interruptible(&ar->raw_htc_write_queue[streamID]); +} + +/* connect to a service */ +static A_STATUS ar6000_connect_raw_service(AR_SOFTC_T *ar, + HTC_RAW_STREAM_ID StreamID) +{ + A_STATUS status; + HTC_SERVICE_CONNECT_RESP response; + A_UINT8 streamNo; + HTC_SERVICE_CONNECT_REQ connect; + + do { + + A_MEMZERO(&connect,sizeof(connect)); + /* pass the stream ID as meta data to the RAW streams service */ + streamNo = (A_UINT8)StreamID; + connect.pMetaData = &streamNo; + connect.MetaDataLength = sizeof(A_UINT8); + /* these fields are the same for all endpoints */ + connect.EpCallbacks.pContext = ar; + connect.EpCallbacks.EpTxComplete = ar6000_htc_raw_write_cb; + connect.EpCallbacks.EpRecv = ar6000_htc_raw_read_cb; + /* simple interface, we don't need these optional callbacks */ + connect.EpCallbacks.EpRecvRefill = NULL; + connect.EpCallbacks.EpSendFull = NULL; + connect.MaxSendQueueDepth = RAW_HTC_WRITE_BUFFERS_NUM; + + /* connect to the raw streams service, we may be able to get 1 or more + * connections, depending on WHAT is running on the target */ + connect.ServiceID = HTC_RAW_STREAMS_SVC; + + A_MEMZERO(&response,sizeof(response)); + + /* try to connect to the raw stream, it is okay if this fails with + * status HTC_SERVICE_NO_MORE_EP */ + status = HTCConnectService(ar->arHtcTarget, + &connect, + &response); + + if (A_FAILED(status)) { + if (response.ConnectRespCode == HTC_SERVICE_NO_MORE_EP) { + AR_DEBUG_PRINTF("HTC RAW , No more streams allowed \n"); + status = A_OK; + } + break; + } + + /* set endpoint mapping for the RAW HTC streams */ + arSetRawStream2EndpointIDMap(ar,StreamID,response.Endpoint); + + AR_DEBUG_PRINTF("HTC RAW : stream ID: %d, endpoint: %d\n", + StreamID, arRawStream2EndpointID(ar,StreamID)); + + } while (FALSE); + + return status; +} + +int ar6000_htc_raw_open(AR_SOFTC_T *ar) +{ + A_STATUS status; + int streamID, endPt, count2; + raw_htc_buffer *buffer; + HTC_SERVICE_ID servicepriority; + + A_ASSERT(ar->arHtcTarget != NULL); + + /* wait for target */ + status = HTCWaitTarget(ar->arHtcTarget); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF("HTCWaitTarget failed (%d)\n", status); + return -ENODEV; + } + + for (endPt = 0; endPt < ENDPOINT_MAX; endPt++) { + ar->arEp2RawMapping[endPt] = HTC_RAW_STREAM_NOT_MAPPED; + } + + for (streamID = HTC_RAW_STREAM_0; streamID < HTC_RAW_STREAM_NUM_MAX; streamID++) { + /* Initialize the data structures */ + init_MUTEX(&ar->raw_htc_read_sem[streamID]); + init_MUTEX(&ar->raw_htc_write_sem[streamID]); + init_waitqueue_head(&ar->raw_htc_read_queue[streamID]); + init_waitqueue_head(&ar->raw_htc_write_queue[streamID]); + + /* try to connect to the raw service */ + status = ar6000_connect_raw_service(ar,streamID); + + if (A_FAILED(status)) { + break; + } + + if (arRawStream2EndpointID(ar,streamID) == 0) { + break; + } + + for (count2 = 0; count2 < RAW_HTC_READ_BUFFERS_NUM; count2 ++) { + /* Initialize the receive buffers */ + buffer = &ar->raw_htc_write_buffer[streamID][count2]; + memset(buffer, 0, sizeof(raw_htc_buffer)); + buffer = &ar->raw_htc_read_buffer[streamID][count2]; + memset(buffer, 0, sizeof(raw_htc_buffer)); + + SET_HTC_PACKET_INFO_RX_REFILL(&buffer->HTCPacket, + buffer, + buffer->data, + AR6000_BUFFER_SIZE, + arRawStream2EndpointID(ar,streamID)); + + /* Queue buffers to HTC for receive */ + if ((status = HTCAddReceivePkt(ar->arHtcTarget, &buffer->HTCPacket)) != A_OK) + { + BMIInit(); + return -EIO; + } + } + + for (count2 = 0; count2 < RAW_HTC_WRITE_BUFFERS_NUM; count2 ++) { + /* Initialize the receive buffers */ + buffer = &ar->raw_htc_write_buffer[streamID][count2]; + memset(buffer, 0, sizeof(raw_htc_buffer)); + } + + ar->read_buffer_available[streamID] = FALSE; + ar->write_buffer_available[streamID] = TRUE; + } + + if (A_FAILED(status)) { + return -EIO; + } + + AR_DEBUG_PRINTF("HTC RAW, number of streams the target supports: %d \n", streamID); + + servicepriority = HTC_RAW_STREAMS_SVC; /* only 1 */ + + /* set callbacks and priority list */ + HTCSetCreditDistribution(ar->arHtcTarget, + ar, + NULL, /* use default */ + NULL, /* use default */ + &servicepriority, + 1); + + /* Start the HTC component */ + if ((status = HTCStart(ar->arHtcTarget)) != A_OK) { + BMIInit(); + return -EIO; + } + + (ar)->arRawIfInit = TRUE; + + return 0; +} + +int ar6000_htc_raw_close(AR_SOFTC_T *ar) +{ + A_PRINTF("ar6000_htc_raw_close called \n"); + HTCStop(ar->arHtcTarget); + + /* reset the device */ + ar6000_reset_device(ar->arHifDevice, ar->arTargetType, TRUE); + /* Initialize the BMI component */ + BMIInit(); + + return 0; +} + +raw_htc_buffer * +get_filled_buffer(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID) +{ + int count; + raw_htc_buffer *busy; + + /* Check for data */ + for (count = 0; count < RAW_HTC_READ_BUFFERS_NUM; count ++) { + busy = &ar->raw_htc_read_buffer[StreamID][count]; + if (busy->length) { + break; + } + } + if (busy->length) { + ar->read_buffer_available[StreamID] = TRUE; + } else { + ar->read_buffer_available[StreamID] = FALSE; + } + + return busy; +} + +ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t length) +{ + int readPtr; + raw_htc_buffer *busy; + + if (arRawStream2EndpointID(ar,StreamID) == 0) { + AR_DEBUG_PRINTF("StreamID(%d) not connected! \n", StreamID); + return -EFAULT; + } + + if (down_interruptible(&ar->raw_htc_read_sem[StreamID])) { + return -ERESTARTSYS; + } + + busy = get_filled_buffer(ar,StreamID); + while (!ar->read_buffer_available[StreamID]) { + up(&ar->raw_htc_read_sem[StreamID]); + + /* Wait for the data */ + AR_DEBUG2_PRINTF("Sleeping StreamID(%d) read process\n", StreamID); + if (wait_event_interruptible(ar->raw_htc_read_queue[StreamID], + ar->read_buffer_available[StreamID])) + { + return -EINTR; + } + if (down_interruptible(&ar->raw_htc_read_sem[StreamID])) { + return -ERESTARTSYS; + } + busy = get_filled_buffer(ar,StreamID); + } + + /* Read the data */ + readPtr = busy->currPtr; + if (length > busy->length - HTC_HEADER_LEN) { + length = busy->length - HTC_HEADER_LEN; + } + if (copy_to_user(buffer, &busy->data[readPtr], length)) { + up(&ar->raw_htc_read_sem[StreamID]); + return -EFAULT; + } + + busy->currPtr += length; + + //AR_DEBUG_PRINTF("raw read ioctl: currPTR : 0x%X 0x%X \n", busy->currPtr,busy->length); + + if (busy->currPtr == busy->length) + { + busy->currPtr = 0; + busy->length = 0; + HTC_PACKET_RESET_RX(&busy->HTCPacket); + //AR_DEBUG_PRINTF("raw read ioctl: ep for packet:%d \n", busy->HTCPacket.Endpoint); + HTCAddReceivePkt(ar->arHtcTarget, &busy->HTCPacket); + } + ar->read_buffer_available[StreamID] = FALSE; + up(&ar->raw_htc_read_sem[StreamID]); + + return length; +} + +static raw_htc_buffer * +get_free_buffer(AR_SOFTC_T *ar, HTC_ENDPOINT_ID StreamID) +{ + int count; + raw_htc_buffer *free; + + free = NULL; + for (count = 0; count < RAW_HTC_WRITE_BUFFERS_NUM; count ++) { + free = &ar->raw_htc_write_buffer[StreamID][count]; + if (free->length == 0) { + break; + } + } + if (!free->length) { + ar->write_buffer_available[StreamID] = TRUE; + } else { + ar->write_buffer_available[StreamID] = FALSE; + } + + return free; +} + +ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t length) +{ + int writePtr; + raw_htc_buffer *free; + + if (arRawStream2EndpointID(ar,StreamID) == 0) { + AR_DEBUG_PRINTF("StreamID(%d) not connected! \n", StreamID); + return -EFAULT; + } + + if (down_interruptible(&ar->raw_htc_write_sem[StreamID])) { + return -ERESTARTSYS; + } + + /* Search for a free buffer */ + free = get_free_buffer(ar,StreamID); + + /* Check if there is space to write else wait */ + while (!ar->write_buffer_available[StreamID]) { + up(&ar->raw_htc_write_sem[StreamID]); + + /* Wait for buffer to become free */ + AR_DEBUG2_PRINTF("Sleeping StreamID(%d) write process\n", StreamID); + if (wait_event_interruptible(ar->raw_htc_write_queue[StreamID], + ar->write_buffer_available[StreamID])) + { + return -EINTR; + } + if (down_interruptible(&ar->raw_htc_write_sem[StreamID])) { + return -ERESTARTSYS; + } + free = get_free_buffer(ar,StreamID); + } + + /* Send the data */ + writePtr = HTC_HEADER_LEN; + if (length > (AR6000_BUFFER_SIZE - HTC_HEADER_LEN)) { + length = AR6000_BUFFER_SIZE - HTC_HEADER_LEN; + } + + if (copy_from_user(&free->data[writePtr], buffer, length)) { + up(&ar->raw_htc_read_sem[StreamID]); + return -EFAULT; + } + + free->length = length; + + SET_HTC_PACKET_INFO_TX(&free->HTCPacket, + free, + &free->data[writePtr], + length, + arRawStream2EndpointID(ar,StreamID), + AR6K_DATA_PKT_TAG); + + HTCSendPkt(ar->arHtcTarget,&free->HTCPacket); + + ar->write_buffer_available[StreamID] = FALSE; + up(&ar->raw_htc_write_sem[StreamID]); + + return length; +} +#endif /* HTC_RAW_INTERFACE */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/ar6k.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6k.c --- linux-2.6.26/drivers/net/wireless/ath6k/ar6k.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6k.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,1033 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// AR6K device layer that handles register level I/O +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "mbox_host_reg.h" +#include "a_osapi.h" +#include "a_debug.h" +#include "hif.h" +#include "htc_packet.h" +#include "ar6k.h" + +#define MAILBOX_FOR_BLOCK_SIZE 1 + +extern A_UINT32 resetok; + +A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev); + +#define LOCK_AR6K(p) A_MUTEX_LOCK(&(p)->Lock); +#define UNLOCK_AR6K(p) A_MUTEX_UNLOCK(&(p)->Lock); + +void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket) +{ + LOCK_AR6K(pDev); + HTC_PACKET_ENQUEUE(&pDev->RegisterIOList,pPacket); + UNLOCK_AR6K(pDev); +} + +HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev) +{ + HTC_PACKET *pPacket; + + LOCK_AR6K(pDev); + pPacket = HTC_PACKET_DEQUEUE(&pDev->RegisterIOList); + UNLOCK_AR6K(pDev); + + return pPacket; +} + +void DevCleanup(AR6K_DEVICE *pDev) +{ + if (A_IS_MUTEX_VALID(&pDev->Lock)) { + A_MUTEX_DELETE(&pDev->Lock); + } + + if (pDev->HifAttached) { + HIFDetachHTC(pDev->HIFDevice); + pDev->HifAttached = FALSE; + } + +} + +A_STATUS DevSetup(AR6K_DEVICE *pDev) +{ + A_UINT32 mailboxaddrs[AR6K_MAILBOXES]; + A_UINT32 blocksizes[AR6K_MAILBOXES]; + A_STATUS status = A_OK; + int i; + HTC_CALLBACKS htcCallbacks; + + AR_DEBUG_ASSERT(AR6K_IRQ_PROC_REGS_SIZE == 16); + AR_DEBUG_ASSERT(AR6K_IRQ_ENABLE_REGS_SIZE == 4); + + do { + + A_MEMZERO(&htcCallbacks, sizeof(HTC_CALLBACKS)); + /* the device layer handles these */ + htcCallbacks.rwCompletionHandler = DevRWCompletionHandler; + htcCallbacks.dsrHandler = DevDsrHandler; + htcCallbacks.context = pDev; + + status = HIFAttachHTC(pDev->HIFDevice, &htcCallbacks); + + if (A_FAILED(status)) { + break; + } + + pDev->HifAttached = TRUE; + + /* initialize our free list of IO packets */ + INIT_HTC_PACKET_QUEUE(&pDev->RegisterIOList); + A_MUTEX_INIT(&pDev->Lock); + + /* get the addresses for all 4 mailboxes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR, + mailboxaddrs, sizeof(mailboxaddrs)); + + if (status != A_OK) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* carve up register I/O packets (these are for ASYNC register I/O ) */ + for (i = 0; i < AR6K_MAX_REG_IO_BUFFERS; i++) { + HTC_PACKET *pIOPacket; + pIOPacket = &pDev->RegIOBuffers[i].HtcPacket; + SET_HTC_PACKET_INFO_RX_REFILL(pIOPacket, + pDev, + pDev->RegIOBuffers[i].Buffer, + AR6K_REG_IO_BUFFER_SIZE, + 0); /* don't care */ + AR6KFreeIOPacket(pDev,pIOPacket); + } + + /* get the address of the mailbox we are using */ + pDev->MailboxAddress = mailboxaddrs[HTC_MAILBOX]; + + /* get the block sizes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + blocksizes, sizeof(blocksizes)); + + if (status != A_OK) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* note: we actually get the block size of a mailbox other than 0, for SDIO the block + * size on mailbox 0 is artificially set to 1. So we use the block size that is set + * for the other 3 mailboxes */ + pDev->BlockSize = blocksizes[MAILBOX_FOR_BLOCK_SIZE]; + /* must be a power of 2 */ + AR_DEBUG_ASSERT((pDev->BlockSize & (pDev->BlockSize - 1)) == 0); + + /* assemble mask, used for padding to a block */ + pDev->BlockMask = pDev->BlockSize - 1; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("BlockSize: %d, MailboxAddress:0x%X \n", + pDev->BlockSize, pDev->MailboxAddress)); + + pDev->GetPendingEventsFunc = NULL; + /* see if the HIF layer implements the get pending events function */ + HIFConfigureDevice(pDev->HIFDevice, + HIF_DEVICE_GET_PENDING_EVENTS_FUNC, + &pDev->GetPendingEventsFunc, + sizeof(pDev->GetPendingEventsFunc)); + + /* assume we can process HIF interrupt events asynchronously */ + pDev->HifIRQProcessingMode = HIF_DEVICE_IRQ_ASYNC_SYNC; + + /* see if the HIF layer overrides this assumption */ + HIFConfigureDevice(pDev->HIFDevice, + HIF_DEVICE_GET_IRQ_PROC_MODE, + &pDev->HifIRQProcessingMode, + sizeof(pDev->HifIRQProcessingMode)); + + switch (pDev->HifIRQProcessingMode) { + case HIF_DEVICE_IRQ_SYNC_ONLY: + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is SYNC ONLY\n")); + break; + case HIF_DEVICE_IRQ_ASYNC_SYNC: + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is ASYNC and SYNC\n")); + break; + default: + AR_DEBUG_ASSERT(FALSE); + } + + pDev->HifMaskUmaskRecvEvent = NULL; + + /* see if the HIF layer implements the mask/unmask recv events function */ + HIFConfigureDevice(pDev->HIFDevice, + HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC, + &pDev->HifMaskUmaskRecvEvent, + sizeof(pDev->HifMaskUmaskRecvEvent)); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF special overrides : 0x%X , 0x%X\n", + (A_UINT32)pDev->GetPendingEventsFunc, (A_UINT32)pDev->HifMaskUmaskRecvEvent)); + + status = DevDisableInterrupts(pDev); + + } while (FALSE); + + if (A_FAILED(status)) { + if (pDev->HifAttached) { + HIFDetachHTC(pDev->HIFDevice); + pDev->HifAttached = FALSE; + } + } + + return status; + +} + +A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev) +{ + A_STATUS status; + AR6K_IRQ_ENABLE_REGISTERS regs; + + LOCK_AR6K(pDev); + + /* Enable all the interrupts except for the internal AR6000 CPU interrupt */ + pDev->IrqEnableRegisters.int_status_enable = INT_STATUS_ENABLE_ERROR_SET(0x01) | + INT_STATUS_ENABLE_CPU_SET(0x01) | + INT_STATUS_ENABLE_COUNTER_SET(0x01); + + if (NULL == pDev->GetPendingEventsFunc) { + pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } else { + /* The HIF layer provided us with a pending events function which means that + * the detection of pending mbox messages is handled in the HIF layer. + * This is the case for the SPI2 interface. + * In the normal case we enable MBOX interrupts, for the case + * with HIFs that offer this mechanism, we keep these interrupts + * masked */ + pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } + + + /* Set up the CPU Interrupt Status Register */ + pDev->IrqEnableRegisters.cpu_int_status_enable = CPU_INT_STATUS_ENABLE_BIT_SET(0x00); + + /* Set up the Error Interrupt Status Register */ + pDev->IrqEnableRegisters.error_status_enable = + ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(0x01) | + ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(0x01); + + /* Set up the Counter Interrupt Status Register (only for debug interrupt to catch fatal errors) */ + pDev->IrqEnableRegisters.counter_int_status_enable = + COUNTER_INT_STATUS_ENABLE_BIT_SET(AR6K_TARGET_DEBUG_INTR_MASK); + + /* copy into our temp area */ + A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE); + + UNLOCK_AR6K(pDev); + +/* ATHENV */ +#ifdef ANDROID_ENV + mdelay(100); +#endif +/* ATHENV */ + /* always synchronous */ + status = HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + ®s.int_status_enable, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + /* Can't write it for some reason */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Failed to update interrupt control registers err: %d\n", status)); + + } + + return status; +} + +A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev) +{ + AR6K_IRQ_ENABLE_REGISTERS regs; + + LOCK_AR6K(pDev); + /* Disable all interrupts */ + pDev->IrqEnableRegisters.int_status_enable = 0; + pDev->IrqEnableRegisters.cpu_int_status_enable = 0; + pDev->IrqEnableRegisters.error_status_enable = 0; + pDev->IrqEnableRegisters.counter_int_status_enable = 0; + /* copy into our temp area */ + A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE); + + UNLOCK_AR6K(pDev); + + /* always synchronous */ + return HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + ®s.int_status_enable, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_SYNC_BYTE_INC, + NULL); +} + +/* enable device interrupts */ +A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev) +{ + /* for good measure, make sure interrupt are disabled before unmasking at the HIF + * layer. + * The rationale here is that between device insertion (where we clear the interrupts the first time) + * and when HTC is finally ready to handle interrupts, other software can perform target "soft" resets. + * The AR6K interrupt enables reset back to an "enabled" state when this happens. + * */ + DevDisableInterrupts(pDev); + + /* Unmask the host controller interrupts */ + HIFUnMaskInterrupt(pDev->HIFDevice); + + return DevEnableInterrupts(pDev); +} + +/* disable all device interrupts */ +A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev) +{ + /* mask the interrupt at the HIF layer, we don't want a stray interrupt taken while + * we zero out our shadow registers in DevDisableInterrupts()*/ + HIFMaskInterrupt(pDev->HIFDevice); + + return DevDisableInterrupts(pDev); +} + +/* callback when our fetch to enable/disable completes */ +static void DevDoEnableDisableRecvAsyncHandler(void *Context, HTC_PACKET *pPacket) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDoEnableDisableRecvAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); + + if (A_FAILED(pPacket->Status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" Failed to disable receiver, status:%d \n", pPacket->Status)); + } + /* free this IO packet */ + AR6KFreeIOPacket(pDev,pPacket); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDoEnableDisableRecvAsyncHandler \n")); +} + +/* disable packet reception (used in case the host runs out of buffers) + * this is the "override" method when the HIF reports another methods to + * disable recv events */ +static A_STATUS DevDoEnableDisableRecvOverride(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode) +{ + A_STATUS status = A_OK; + HTC_PACKET *pIOPacket = NULL; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("DevDoEnableDisableRecvOverride: Enable:%d Mode:%d\n", + EnableRecv,AsyncMode)); + + do { + + if (AsyncMode) { + + pIOPacket = AR6KAllocIOPacket(pDev); + + if (NULL == pIOPacket) { + status = A_NO_MEMORY; + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* stick in our completion routine when the I/O operation completes */ + pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler; + pIOPacket->pContext = pDev; + + /* call the HIF layer override and do this asynchronously */ + status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice, + EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV, + pIOPacket); + break; + } + + /* if we get here we are doing it synchronously */ + status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice, + EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV, + NULL); + + } while (FALSE); + + if (A_FAILED(status) && (pIOPacket != NULL)) { + AR6KFreeIOPacket(pDev,pIOPacket); + } + + return status; +} + +/* disable packet reception (used in case the host runs out of buffers) + * this is the "normal" method using the interrupt enable registers through + * the host I/F */ +static A_STATUS DevDoEnableDisableRecvNormal(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode) +{ + A_STATUS status = A_OK; + HTC_PACKET *pIOPacket = NULL; + AR6K_IRQ_ENABLE_REGISTERS regs; + + /* take the lock to protect interrupt enable shadows */ + LOCK_AR6K(pDev); + + if (EnableRecv) { + pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } else { + pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } + + /* copy into our temp area */ + A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE); + UNLOCK_AR6K(pDev); + + do { + + if (AsyncMode) { + + pIOPacket = AR6KAllocIOPacket(pDev); + + if (NULL == pIOPacket) { + status = A_NO_MEMORY; + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* copy values to write to our async I/O buffer */ + A_MEMCPY(pIOPacket->pBuffer,®s,AR6K_IRQ_ENABLE_REGS_SIZE); + + /* stick in our completion routine when the I/O operation completes */ + pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler; + pIOPacket->pContext = pDev; + + /* write it out asynchronously */ + HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + pIOPacket->pBuffer, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_ASYNC_BYTE_INC, + pIOPacket); + break; + } + + /* if we get here we are doing it synchronously */ + + status = HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + ®s.int_status_enable, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_SYNC_BYTE_INC, + NULL); + + } while (FALSE); + + if (A_FAILED(status) && (pIOPacket != NULL)) { + AR6KFreeIOPacket(pDev,pIOPacket); + } + + return status; +} + + +A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode) +{ + if (NULL == pDev->HifMaskUmaskRecvEvent) { + return DevDoEnableDisableRecvNormal(pDev,FALSE,AsyncMode); + } else { + return DevDoEnableDisableRecvOverride(pDev,FALSE,AsyncMode); + } +} + +A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode) +{ + if (NULL == pDev->HifMaskUmaskRecvEvent) { + return DevDoEnableDisableRecvNormal(pDev,TRUE,AsyncMode); + } else { + return DevDoEnableDisableRecvOverride(pDev,TRUE,AsyncMode); + } +} + +void DevDumpRegisters(AR6K_IRQ_PROC_REGISTERS *pIrqProcRegs, + AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs) +{ + + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("\n<------- Register Table -------->\n")); + + if (pIrqProcRegs != NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Int Status: 0x%x\n",pIrqProcRegs->host_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("CPU Int Status: 0x%x\n",pIrqProcRegs->cpu_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Error Int Status: 0x%x\n",pIrqProcRegs->error_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Counter Int Status: 0x%x\n",pIrqProcRegs->counter_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Mbox Frame: 0x%x\n",pIrqProcRegs->mbox_frame)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Rx Lookahead Valid: 0x%x\n",pIrqProcRegs->rx_lookahead_valid)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Rx Lookahead 0: 0x%x\n",pIrqProcRegs->rx_lookahead[0])); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Rx Lookahead 1: 0x%x\n",pIrqProcRegs->rx_lookahead[1])); + } + + if (pIrqEnableRegs != NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Int Status Enable: 0x%x\n",pIrqEnableRegs->int_status_enable)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Counter Int Status Enable: 0x%x\n",pIrqEnableRegs->counter_int_status_enable)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("<------------------------------->\n")); + } +} + + +#ifdef MBOXHW_UNIT_TEST + + +/* This is a mailbox hardware unit test that must be called in a schedulable context + * This test is very simple, it will send a list of buffers with a counting pattern + * and the target will invert the data and send the message back + * + * the unit test has the following constraints: + * + * The target has at least 8 buffers of 256 bytes each. The host will send + * the following pattern of buffers in rapid succession : + * + * 1 buffer - 128 bytes + * 1 buffer - 256 bytes + * 1 buffer - 512 bytes + * 1 buffer - 1024 bytes + * + * The host will send the buffers to one mailbox and wait for buffers to be reflected + * back from the same mailbox. The target sends the buffers FIFO order. + * Once the final buffer has been received for a mailbox, the next mailbox is tested. + * + * + * Note: To simplifythe test , we assume that the chosen buffer sizes + * will fall on a nice block pad + * + * It is expected that higher-order tests will be written to stress the mailboxes using + * a message-based protocol (with some performance timming) that can create more + * randomness in the packets sent over mailboxes. + * + * */ + +#define A_ROUND_UP_PWR2(x, align) (((int) (x) + ((align)-1)) & ~((align)-1)) + +#define BUFFER_BLOCK_PAD 128 + +#if 0 +#define BUFFER1 128 +#define BUFFER2 256 +#define BUFFER3 512 +#define BUFFER4 1024 +#endif + +#if 1 +#define BUFFER1 80 +#define BUFFER2 200 +#define BUFFER3 444 +#define BUFFER4 800 +#endif + +#define TOTAL_BYTES (A_ROUND_UP_PWR2(BUFFER1,BUFFER_BLOCK_PAD) + \ + A_ROUND_UP_PWR2(BUFFER2,BUFFER_BLOCK_PAD) + \ + A_ROUND_UP_PWR2(BUFFER3,BUFFER_BLOCK_PAD) + \ + A_ROUND_UP_PWR2(BUFFER4,BUFFER_BLOCK_PAD) ) + +#define TEST_BYTES (BUFFER1 + BUFFER2 + BUFFER3 + BUFFER4) + +#define TEST_CREDITS_RECV_TIMEOUT 100 + +static A_UINT8 g_Buffer[TOTAL_BYTES]; +static A_UINT32 g_MailboxAddrs[AR6K_MAILBOXES]; +static A_UINT32 g_BlockSizes[AR6K_MAILBOXES]; + +#define BUFFER_PROC_LIST_DEPTH 4 + +typedef struct _BUFFER_PROC_LIST{ + A_UINT8 *pBuffer; + A_UINT32 length; +}BUFFER_PROC_LIST; + + +#define PUSH_BUFF_PROC_ENTRY(pList,len,pCurrpos) \ +{ \ + (pList)->pBuffer = (pCurrpos); \ + (pList)->length = (len); \ + (pCurrpos) += (len); \ + (pList)++; \ +} + +/* a simple and crude way to send different "message" sizes */ +static void AssembleBufferList(BUFFER_PROC_LIST *pList) +{ + A_UINT8 *pBuffer = g_Buffer; + +#if BUFFER_PROC_LIST_DEPTH < 4 +#error "Buffer processing list depth is not deep enough!!" +#endif + + PUSH_BUFF_PROC_ENTRY(pList,BUFFER1,pBuffer); + PUSH_BUFF_PROC_ENTRY(pList,BUFFER2,pBuffer); + PUSH_BUFF_PROC_ENTRY(pList,BUFFER3,pBuffer); + PUSH_BUFF_PROC_ENTRY(pList,BUFFER4,pBuffer); + +} + +#define FILL_ZERO TRUE +#define FILL_COUNTING FALSE +static void InitBuffers(A_BOOL Zero) +{ + A_UINT16 *pBuffer16 = (A_UINT16 *)g_Buffer; + int i; + + /* fill buffer with 16 bit counting pattern or zeros */ + for (i = 0; i < (TOTAL_BYTES / 2) ; i++) { + if (!Zero) { + pBuffer16[i] = (A_UINT16)i; + } else { + pBuffer16[i] = 0; + } + } +} + + +static A_BOOL CheckOneBuffer(A_UINT16 *pBuffer16, int Length) +{ + int i; + A_UINT16 startCount; + A_BOOL success = TRUE; + + /* get the starting count */ + startCount = pBuffer16[0]; + /* invert it, this is the expected value */ + startCount = ~startCount; + /* scan the buffer and verify */ + for (i = 0; i < (Length / 2) ; i++,startCount++) { + /* target will invert all the data */ + if ((A_UINT16)pBuffer16[i] != (A_UINT16)~startCount) { + success = FALSE; + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Invalid Data Got:0x%X, Expecting:0x%X (offset:%d, total:%d) \n", + pBuffer16[i], ((A_UINT16)~startCount), i, Length)); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("0x%X 0x%X 0x%X 0x%X \n", + pBuffer16[i], pBuffer16[i + 1], pBuffer16[i + 2],pBuffer16[i+3])); + break; + } + } + + return success; +} + +static A_BOOL CheckBuffers(void) +{ + int i; + A_BOOL success = TRUE; + BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH]; + + /* assemble the list */ + AssembleBufferList(checkList); + + /* scan the buffers and verify */ + for (i = 0; i < BUFFER_PROC_LIST_DEPTH ; i++) { + success = CheckOneBuffer((A_UINT16 *)checkList[i].pBuffer, checkList[i].length); + if (!success) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer : 0x%X, Length:%d failed verify \n", + (A_UINT32)checkList[i].pBuffer, checkList[i].length)); + break; + } + } + + return success; +} + + /* find the end marker for the last buffer we will be sending */ +static A_UINT16 GetEndMarker(void) +{ + A_UINT8 *pBuffer; + BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH]; + + /* fill up buffers with the normal counting pattern */ + InitBuffers(FILL_COUNTING); + + /* assemble the list we will be sending down */ + AssembleBufferList(checkList); + /* point to the last 2 bytes of the last buffer */ + pBuffer = &(checkList[BUFFER_PROC_LIST_DEPTH - 1].pBuffer[(checkList[BUFFER_PROC_LIST_DEPTH - 1].length) - 2]); + + /* the last count in the last buffer is the marker */ + return (A_UINT16)pBuffer[0] | ((A_UINT16)pBuffer[1] << 8); +} + +#define ATH_PRINT_OUT_ZONE ATH_DEBUG_ERR + +/* send the ordered buffers to the target */ +static A_STATUS SendBuffers(AR6K_DEVICE *pDev, int mbox) +{ + A_STATUS status = A_OK; + A_UINT32 request = HIF_WR_SYNC_BLOCK_INC; + BUFFER_PROC_LIST sendList[BUFFER_PROC_LIST_DEPTH]; + int i; + int totalBytes = 0; + int paddedLength; + int totalwPadding = 0; + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sending buffers on mailbox : %d \n",mbox)); + + /* fill buffer with counting pattern */ + InitBuffers(FILL_COUNTING); + + /* assemble the order in which we send */ + AssembleBufferList(sendList); + + for (i = 0; i < BUFFER_PROC_LIST_DEPTH; i++) { + + /* we are doing block transfers, so we need to pad everything to a block size */ + paddedLength = (sendList[i].length + (g_BlockSizes[mbox] - 1)) & + (~(g_BlockSizes[mbox] - 1)); + + /* send each buffer synchronously */ + status = HIFReadWrite(pDev->HIFDevice, + g_MailboxAddrs[mbox], + sendList[i].pBuffer, + paddedLength, + request, + NULL); + if (status != A_OK) { + break; + } + totalBytes += sendList[i].length; + totalwPadding += paddedLength; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sent %d bytes (%d padded bytes) to mailbox : %d \n",totalBytes,totalwPadding,mbox)); + + return status; +} + +/* poll the mailbox credit counter until we get a credit or timeout */ +static A_STATUS GetCredits(AR6K_DEVICE *pDev, int mbox, int *pCredits) +{ + A_STATUS status = A_OK; + int timeout = TEST_CREDITS_RECV_TIMEOUT; + A_UINT8 credits = 0; + A_UINT32 address; + + while (TRUE) { + + /* Read the counter register to get credits, this auto-decrements */ + address = COUNT_DEC_ADDRESS + (AR6K_MAILBOXES + mbox) * 4; + status = HIFReadWrite(pDev->HIFDevice, address, &credits, sizeof(credits), + HIF_RD_SYNC_BYTE_FIX, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Unable to decrement the command credit count register (mbox=%d)\n",mbox)); + status = A_ERROR; + break; + } + + if (credits) { + break; + } + + timeout--; + + if (timeout <= 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" Timeout reading credit registers (mbox=%d, address:0x%X) \n",mbox,address)); + status = A_ERROR; + break; + } + + /* delay a little, target may not be ready */ + A_MDELAY(1000); + + } + + if (status == A_OK) { + *pCredits = credits; + } + + return status; +} + + +/* wait for the buffers to come back */ +static A_STATUS RecvBuffers(AR6K_DEVICE *pDev, int mbox) +{ + A_STATUS status = A_OK; + A_UINT32 request = HIF_RD_SYNC_BLOCK_INC; + BUFFER_PROC_LIST recvList[BUFFER_PROC_LIST_DEPTH]; + int curBuffer; + int credits; + int i; + int totalBytes = 0; + int paddedLength; + int totalwPadding = 0; + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for buffers on mailbox : %d \n",mbox)); + + /* zero the buffers */ + InitBuffers(FILL_ZERO); + + /* assemble the order in which we should receive */ + AssembleBufferList(recvList); + + curBuffer = 0; + + while (curBuffer < BUFFER_PROC_LIST_DEPTH) { + + /* get number of buffers that have been completed, this blocks + * until we get at least 1 credit or it times out */ + status = GetCredits(pDev, mbox, &credits); + + if (status != A_OK) { + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got %d messages on mailbox : %d \n",credits, mbox)); + + /* get all the buffers that are sitting on the queue */ + for (i = 0; i < credits; i++) { + AR_DEBUG_ASSERT(curBuffer < BUFFER_PROC_LIST_DEPTH); + /* recv the current buffer synchronously, the buffers should come back in + * order... with padding applied by the target */ + paddedLength = (recvList[curBuffer].length + (g_BlockSizes[mbox] - 1)) & + (~(g_BlockSizes[mbox] - 1)); + + status = HIFReadWrite(pDev->HIFDevice, + g_MailboxAddrs[mbox], + recvList[curBuffer].pBuffer, + paddedLength, + request, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to read %d bytes on mailbox:%d : address:0x%X \n", + recvList[curBuffer].length, mbox, g_MailboxAddrs[mbox])); + break; + } + + totalwPadding += paddedLength; + totalBytes += recvList[curBuffer].length; + curBuffer++; + } + + if (status != A_OK) { + break; + } + /* go back and get some more */ + credits = 0; + } + + if (totalBytes != TEST_BYTES) { + AR_DEBUG_ASSERT(FALSE); + } else { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got all buffers on mbox:%d total recv :%d (w/Padding : %d) \n", + mbox, totalBytes, totalwPadding)); + } + + return status; + + +} + +static A_STATUS DoOneMboxHWTest(AR6K_DEVICE *pDev, int mbox) +{ + A_STATUS status; + + do { + /* send out buffers */ + status = SendBuffers(pDev,mbox); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Sending buffers Failed : %d mbox:%d\n",status,mbox)); + break; + } + + /* go get them, this will block */ + status = RecvBuffers(pDev, mbox); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Recv buffers Failed : %d mbox:%d\n",status,mbox)); + break; + } + + /* check the returned data patterns */ + if (!CheckBuffers()) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer Verify Failed : mbox:%d\n",mbox)); + status = A_ERROR; + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" Send/Recv success! mailbox : %d \n",mbox)); + + } while (FALSE); + + return status; +} + +/* here is where the test starts */ +A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev) +{ + int i; + A_STATUS status; + int credits = 0; + A_UINT8 params[4]; + int numBufs; + int bufferSize; + A_UINT16 temp; + + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest START - \n")); + + do { + /* get the addresses for all 4 mailboxes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR, + g_MailboxAddrs, sizeof(g_MailboxAddrs)); + + if (status != A_OK) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* get the block sizes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + g_BlockSizes, sizeof(g_BlockSizes)); + + if (status != A_OK) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* note, the HIF layer usually reports mbox 0 to have a block size of + * 1, but our test wants to run in block-mode for all mailboxes, so we treat all mailboxes + * the same. */ + g_BlockSizes[0] = g_BlockSizes[1]; + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Block Size to use: %d \n",g_BlockSizes[0])); + + if (g_BlockSizes[1] > BUFFER_BLOCK_PAD) { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("%d Block size is too large for buffer pad %d\n", + g_BlockSizes[1], BUFFER_BLOCK_PAD)); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for target.... \n")); + + /* the target lets us know it is ready by giving us 1 credit on + * mailbox 0 */ + status = GetCredits(pDev, 0, &credits); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait for target ready \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Target is ready ...\n")); + + /* read the first 4 scratch registers */ + status = HIFReadWrite(pDev->HIFDevice, + SCRATCH_ADDRESS, + params, + 4, + HIF_RD_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait get parameters \n")); + break; + } + + numBufs = params[0]; + bufferSize = (int)(((A_UINT16)params[2] << 8) | (A_UINT16)params[1]); + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, + ("Target parameters: bufs per mailbox:%d, buffer size:%d bytes (total space: %d, minimum required space (w/padding): %d) \n", + numBufs, bufferSize, (numBufs * bufferSize), TOTAL_BYTES)); + + if ((numBufs * bufferSize) < TOTAL_BYTES) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Not Enough buffer space to run test! need:%d, got:%d \n", + TOTAL_BYTES, (numBufs*bufferSize))); + status = A_ERROR; + break; + } + + temp = GetEndMarker(); + + status = HIFReadWrite(pDev->HIFDevice, + SCRATCH_ADDRESS + 4, + (A_UINT8 *)&temp, + 2, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write end marker \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("End Marker: 0x%X \n",temp)); + + temp = (A_UINT16)g_BlockSizes[1]; + /* convert to a mask */ + temp = temp - 1; + status = HIFReadWrite(pDev->HIFDevice, + SCRATCH_ADDRESS + 6, + (A_UINT8 *)&temp, + 2, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write block mask \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Set Block Mask: 0x%X \n",temp)); + + /* execute the test on each mailbox */ + for (i = 0; i < AR6K_MAILBOXES; i++) { + status = DoOneMboxHWTest(pDev, i); + if (status != A_OK) { + break; + } + } + + } while (FALSE); + + if (status == A_OK) { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - SUCCESS! - \n")); + } else { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - FAILED! - \n")); + } + /* don't let HTC_Start continue, the target is actually not running any HTC code */ + return A_ERROR; +} +#endif + + + diff -urN linux-2.6.26/drivers/net/wireless/ath6k/ar6k.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6k.h --- linux-2.6.26/drivers/net/wireless/ath6k/ar6k.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6k.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,206 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// AR6K device layer that handles register level I/O +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef AR6K_H_ +#define AR6K_H_ + +#define AR6K_MAILBOXES 4 + +/* HTC runs over mailbox 0 */ +#define HTC_MAILBOX 0 + +#define AR6K_TARGET_DEBUG_INTR_MASK 0x01 + +#define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK | \ + INT_STATUS_ENABLE_CPU_MASK | \ + INT_STATUS_ENABLE_COUNTER_MASK) + +//#define MBOXHW_UNIT_TEST 1 + +#include "athstartpack.h" +typedef PREPACK struct _AR6K_IRQ_PROC_REGISTERS { + A_UINT8 host_int_status; + A_UINT8 cpu_int_status; + A_UINT8 error_int_status; + A_UINT8 counter_int_status; + A_UINT8 mbox_frame; + A_UINT8 rx_lookahead_valid; + A_UINT8 hole[2]; + A_UINT32 rx_lookahead[2]; +} POSTPACK AR6K_IRQ_PROC_REGISTERS; + +#define AR6K_IRQ_PROC_REGS_SIZE sizeof(AR6K_IRQ_PROC_REGISTERS) + + + +typedef PREPACK struct _AR6K_IRQ_ENABLE_REGISTERS { + A_UINT8 int_status_enable; + A_UINT8 cpu_int_status_enable; + A_UINT8 error_status_enable; + A_UINT8 counter_int_status_enable; +} POSTPACK AR6K_IRQ_ENABLE_REGISTERS; + +#include "athendpack.h" + +#define AR6K_IRQ_ENABLE_REGS_SIZE sizeof(AR6K_IRQ_ENABLE_REGISTERS) + +#define AR6K_REG_IO_BUFFER_SIZE 32 +#define AR6K_MAX_REG_IO_BUFFERS 8 + +/* buffers for ASYNC I/O */ +typedef struct _AR6K_ASYNC_REG_IO_BUFFER { + HTC_PACKET HtcPacket; /* we use an HTC packet as a wrapper for our async register-based I/O */ + A_UINT8 Buffer[AR6K_REG_IO_BUFFER_SIZE]; +} AR6K_ASYNC_REG_IO_BUFFER; + +typedef enum _AR6K_TARGET_FAILURE_TYPE { + AR6K_TARGET_ASSERT = 1, + AR6K_TARGET_RX_ERROR, + AR6K_TARGET_TX_ERROR +} AR6K_TARGET_FAILURE_TYPE; + +typedef struct _AR6K_DEVICE { + A_MUTEX_T Lock; + AR6K_IRQ_PROC_REGISTERS IrqProcRegisters; + AR6K_IRQ_ENABLE_REGISTERS IrqEnableRegisters; + void *HIFDevice; + A_UINT32 BlockSize; + A_UINT32 BlockMask; + A_UINT32 MailboxAddress; + HIF_PENDING_EVENTS_FUNC GetPendingEventsFunc; + void *HTCContext; + HTC_PACKET_QUEUE RegisterIOList; + AR6K_ASYNC_REG_IO_BUFFER RegIOBuffers[AR6K_MAX_REG_IO_BUFFERS]; + void (*TargetFailureCallback)(void *Context, AR6K_TARGET_FAILURE_TYPE Type); + A_STATUS (*MessagePendingCallback)(void *Context, A_UINT32 *LookAhead, A_BOOL *pAsyncProc); + HIF_DEVICE_IRQ_PROCESSING_MODE HifIRQProcessingMode; + HIF_MASK_UNMASK_RECV_EVENT HifMaskUmaskRecvEvent; + A_BOOL HifAttached; +} AR6K_DEVICE; + +#define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) ((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY) + +A_STATUS DevSetup(AR6K_DEVICE *pDev); +void DevCleanup(AR6K_DEVICE *pDev); +A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev, + A_UINT32 *pLookAhead, + int TimeoutMS); +A_STATUS DevRWCompletionHandler(void *context, A_STATUS status); +A_STATUS DevDsrHandler(void *context); +A_STATUS DevCheckPendingRecvMsgsAsync(void *context); +void DevDumpRegisters(AR6K_IRQ_PROC_REGISTERS *pIrqProcRegs, + AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs); + +#define DEV_STOP_RECV_ASYNC TRUE +#define DEV_STOP_RECV_SYNC FALSE +#define DEV_ENABLE_RECV_ASYNC TRUE +#define DEV_ENABLE_RECV_SYNC FALSE +A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode); +A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode); +A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev); + +static INLINE A_STATUS DevSendPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 SendLength) { + A_UINT32 paddedLength; + A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE; + A_STATUS status; + + /* adjust the length to be a multiple of block size if appropriate */ + paddedLength = (SendLength + (pDev->BlockMask)) & + (~(pDev->BlockMask)); +#if 0 // BufferLength may not be set in , fix this... + if (paddedLength > pPacket->BufferLength) { + AR_DEBUG_ASSERT(FALSE); + if (pPacket->Completion != NULL) { + COMPLETE_HTC_PACKET(pPacket,A_EINVAL); + } + return A_EINVAL; + } +#endif + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("DevSendPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n", + paddedLength, + pDev->MailboxAddress, + sync ? "SYNC" : "ASYNC")); + + status = HIFReadWrite(pDev->HIFDevice, + pDev->MailboxAddress, + pPacket->pBuffer, + paddedLength, /* the padded length */ + sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC, + sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */ + + if (sync) { + pPacket->Status = status; + } + + return status; +} + +static INLINE A_STATUS DevRecvPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 RecvLength) { + A_UINT32 paddedLength; + A_STATUS status; + A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE; + + /* adjust the length to be a multiple of block size if appropriate */ + paddedLength = (RecvLength + (pDev->BlockMask)) & + (~(pDev->BlockMask)); + if (paddedLength > pPacket->BufferLength) { + AR_DEBUG_ASSERT(FALSE); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("DevRecvPacket, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n", + paddedLength,RecvLength,pPacket->BufferLength)); + if (pPacket->Completion != NULL) { + COMPLETE_HTC_PACKET(pPacket,A_EINVAL); + } + return A_EINVAL; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("DevRecvPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n", + paddedLength, + pDev->MailboxAddress, + sync ? "SYNC" : "ASYNC")); + + status = HIFReadWrite(pDev->HIFDevice, + pDev->MailboxAddress, + pPacket->pBuffer, + paddedLength, + sync ? HIF_RD_SYNC_BLOCK_INC : HIF_RD_ASYNC_BLOCK_INC, + sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */ + + if (sync) { + pPacket->Status = status; + } + + return status; +} + +#ifdef MBOXHW_UNIT_TEST +A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev); +#endif + +#endif /*AR6K_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/ar6k_events.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6k_events.c --- linux-2.6.26/drivers/net/wireless/ath6k/ar6k_events.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6k_events.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,665 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// AR6K Driver layer event handling (i.e. interrupts, message polling) +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" + +#include "mbox_host_reg.h" +#include "rtc_reg.h" + +#include "a_osapi.h" +#include "a_debug.h" +#include "hif.h" +#include "htc_packet.h" +#include "ar6k.h" + + +extern void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket); +extern HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev); + +static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev); + +#define DELAY_PER_INTERVAL_MS 10 /* 10 MS delay per polling interval */ + +/* completion routine for ALL HIF layer async I/O */ +A_STATUS DevRWCompletionHandler(void *context, A_STATUS status) +{ + HTC_PACKET *pPacket = (HTC_PACKET *)context; + + COMPLETE_HTC_PACKET(pPacket,status); + + return A_OK; +} + +/* mailbox recv message polling */ +A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev, + A_UINT32 *pLookAhead, + int TimeoutMS) +{ + A_STATUS status = A_OK; + int timeout = TimeoutMS/DELAY_PER_INTERVAL_MS; + + AR_DEBUG_ASSERT(timeout > 0); + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevPollMboxMsgRecv \n")); + + while (TRUE) { + + if (pDev->GetPendingEventsFunc != NULL) + { + + HIF_PENDING_EVENTS_INFO events; + + /* the HIF layer uses a special mechanism to get events, do this + * synchronously */ + status = pDev->GetPendingEventsFunc(pDev->HIFDevice, + &events, + NULL); + if (A_FAILED(status)) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get pending events \n")); + break; + } + + if (events.Events & HIF_RECV_MSG_AVAIL) + { + /* there is a message available, the lookahead should be valid now */ + *pLookAhead = events.LookAhead; + + break; + } + } + else + { + + /* this is the standard HIF way.... */ + /* load the register table */ + status = HIFReadWrite(pDev->HIFDevice, + HOST_INT_STATUS_ADDRESS, + (A_UINT8 *)&pDev->IrqProcRegisters, + AR6K_IRQ_PROC_REGS_SIZE, + HIF_RD_SYNC_BYTE_INC, + NULL); + + if (A_FAILED(status)) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to read register table \n")); + break; + } + + /* check for MBOX data and valid lookahead */ + if (pDev->IrqProcRegisters.host_int_status & (1 << HTC_MAILBOX)) + { + if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) + { + /* mailbox has a message and the look ahead is valid */ + *pLookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX]; + break; + } + } + + } + + timeout--; + + if (timeout <= 0) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Timeout waiting for recv message \n")); + status = A_ERROR; + + /* check if the target asserted */ + if ( pDev->IrqProcRegisters.counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) { + /* target signaled an assert, process this pending interrupt + * this will call the target failure handler */ + DevServiceDebugInterrupt(pDev); + } + + break; + } + + /* delay a little */ + A_MDELAY(DELAY_PER_INTERVAL_MS); + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Retry Mbox Poll : %d \n",timeout)); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevPollMboxMsgRecv \n")); + + return status; +} + +static A_STATUS DevServiceCPUInterrupt(AR6K_DEVICE *pDev) +{ + A_STATUS status; + A_UINT8 cpu_int_status; + A_UINT8 regBuffer[4]; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("CPU Interrupt\n")); + cpu_int_status = pDev->IrqProcRegisters.cpu_int_status & + pDev->IrqEnableRegisters.cpu_int_status_enable; + AR_DEBUG_ASSERT(cpu_int_status); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + ("Valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n", + cpu_int_status)); + + /* Clear the interrupt */ + pDev->IrqProcRegisters.cpu_int_status &= ~cpu_int_status; /* W1C */ + + /* set up the register transfer buffer to hit the register 4 times , this is done + * to make the access 4-byte aligned to mitigate issues with host bus interconnects that + * restrict bus transfer lengths to be a multiple of 4-bytes */ + + /* set W1C value to clear the interrupt, this hits the register first */ + regBuffer[0] = cpu_int_status; + /* the remaining 4 values are set to zero which have no-effect */ + regBuffer[1] = 0; + regBuffer[2] = 0; + regBuffer[3] = 0; + + status = HIFReadWrite(pDev->HIFDevice, + CPU_INT_STATUS_ADDRESS, + regBuffer, + 4, + HIF_WR_SYNC_BYTE_FIX, + NULL); + + AR_DEBUG_ASSERT(status == A_OK); + return status; +} + + +static A_STATUS DevServiceErrorInterrupt(AR6K_DEVICE *pDev) +{ + A_STATUS status; + A_UINT8 error_int_status; + A_UINT8 regBuffer[4]; + + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error Interrupt\n")); + error_int_status = pDev->IrqProcRegisters.error_int_status & 0x0F; + AR_DEBUG_ASSERT(error_int_status); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n", + error_int_status)); + + if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) { + /* Wakeup */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error : Wakeup\n")); + } + + if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) { + /* Rx Underflow */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Rx Underflow\n")); + if (pDev->TargetFailureCallback != NULL) { + pDev->TargetFailureCallback(pDev->HTCContext, AR6K_TARGET_RX_ERROR); + } + } + + if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) { + /* Tx Overflow */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Tx Overflow\n")); + if (pDev->TargetFailureCallback != NULL) { + pDev->TargetFailureCallback(pDev->HTCContext, AR6K_TARGET_TX_ERROR); + } + } + + /* Clear the interrupt */ + pDev->IrqProcRegisters.error_int_status &= ~error_int_status; /* W1C */ + + /* set up the register transfer buffer to hit the register 4 times , this is done + * to make the access 4-byte aligned to mitigate issues with host bus interconnects that + * restrict bus transfer lengths to be a multiple of 4-bytes */ + + /* set W1C value to clear the interrupt, this hits the register first */ + regBuffer[0] = error_int_status; + /* the remaining 4 values are set to zero which have no-effect */ + regBuffer[1] = 0; + regBuffer[2] = 0; + regBuffer[3] = 0; + + status = HIFReadWrite(pDev->HIFDevice, + ERROR_INT_STATUS_ADDRESS, + regBuffer, + 4, + HIF_WR_SYNC_BYTE_FIX, + NULL); + + AR_DEBUG_ASSERT(status == A_OK); + return status; +} + +static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev) +{ + A_UINT32 dummy; + A_STATUS status; + + /* Send a target failure event to the application */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Target debug interrupt\n")); + + if (pDev->TargetFailureCallback != NULL) { + pDev->TargetFailureCallback(pDev->HTCContext, AR6K_TARGET_ASSERT); + } + + /* clear the interrupt , the debug error interrupt is + * counter 0 */ + /* read counter to clear interrupt */ + status = HIFReadWrite(pDev->HIFDevice, + COUNT_DEC_ADDRESS, + (A_UINT8 *)&dummy, + 4, + HIF_RD_SYNC_BYTE_INC, + NULL); + + AR_DEBUG_ASSERT(status == A_OK); + return status; +} + +static A_STATUS DevServiceCounterInterrupt(AR6K_DEVICE *pDev) +{ + A_UINT8 counter_int_status; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Counter Interrupt\n")); + + counter_int_status = pDev->IrqProcRegisters.counter_int_status & + pDev->IrqEnableRegisters.counter_int_status_enable; + + AR_DEBUG_ASSERT(counter_int_status); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + ("Valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n", + counter_int_status)); + + /* Check if the debug interrupt is pending */ + if (counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) { + return DevServiceDebugInterrupt(pDev); + } + + return A_OK; +} + +/* callback when our fetch to get interrupt status registers completes */ +static void DevGetEventAsyncHandler(void *Context, HTC_PACKET *pPacket) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context; + A_UINT32 lookAhead = 0; + A_BOOL otherInts = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGetEventAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); + + do { + + if (A_FAILED(pPacket->Status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" GetEvents I/O request failed, status:%d \n", pPacket->Status)); + /* bail out, don't unmask HIF interrupt */ + break; + } + + if (pDev->GetPendingEventsFunc != NULL) { + /* the HIF layer collected the information for us */ + HIF_PENDING_EVENTS_INFO *pEvents = (HIF_PENDING_EVENTS_INFO *)pPacket->pBuffer; + if (pEvents->Events & HIF_RECV_MSG_AVAIL) { + lookAhead = pEvents->LookAhead; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler1, lookAhead is zero! \n")); + } + } + if (pEvents->Events & HIF_OTHER_EVENTS) { + otherInts = TRUE; + } + } else { + /* standard interrupt table handling.... */ + AR6K_IRQ_PROC_REGISTERS *pReg = (AR6K_IRQ_PROC_REGISTERS *)pPacket->pBuffer; + A_UINT8 host_int_status; + + host_int_status = pReg->host_int_status & pDev->IrqEnableRegisters.int_status_enable; + + if (host_int_status & (1 << HTC_MAILBOX)) { + host_int_status &= ~(1 << HTC_MAILBOX); + if (pReg->rx_lookahead_valid & (1 << HTC_MAILBOX)) { + /* mailbox has a message and the look ahead is valid */ + lookAhead = pReg->rx_lookahead[HTC_MAILBOX]; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler2, lookAhead is zero! \n")); + } + } + } + + if (host_int_status) { + /* there are other interrupts to handle */ + otherInts = TRUE; + } + } + + if (otherInts || (lookAhead == 0)) { + /* if there are other interrupts to process, we cannot do this in the async handler so + * ack the interrupt which will cause our sync handler to run again + * if however there are no more messages, we can now ack the interrupt */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + (" Acking interrupt from DevGetEventAsyncHandler (otherints:%d, lookahead:0x%X)\n", + otherInts, lookAhead)); + HIFAckInterrupt(pDev->HIFDevice); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + (" DevGetEventAsyncHandler : detected another message, lookahead :0x%X \n", + lookAhead)); + /* lookahead is non-zero and there are no other interrupts to service, + * go get the next message */ + pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, NULL); + } + + } while (FALSE); + + /* free this IO packet */ + AR6KFreeIOPacket(pDev,pPacket); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGetEventAsyncHandler \n")); +} + +/* called by the HTC layer when it wants us to check if the device has any more pending + * recv messages, this starts off a series of async requests to read interrupt registers */ +A_STATUS DevCheckPendingRecvMsgsAsync(void *context) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)context; + A_STATUS status = A_OK; + HTC_PACKET *pIOPacket; + + /* this is called in an ASYNC only context, we may NOT block, sleep or call any apis that can + * cause us to switch contexts */ + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevCheckPendingRecvMsgsAsync: (dev: 0x%X)\n", (A_UINT32)pDev)); + + do { + + if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) { + /* break the async processing chain right here, no need to continue. + * The DevDsrHandler() will handle things in a loop when things are driven + * synchronously */ + break; + } + /* first allocate one of our HTC packets we created for async I/O + * we reuse HTC packet definitions so that we can use the completion mechanism + * in DevRWCompletionHandler() */ + pIOPacket = AR6KAllocIOPacket(pDev); + + if (NULL == pIOPacket) { + /* there should be only 1 asynchronous request out at a time to read these registers + * so this should actually never happen */ + status = A_NO_MEMORY; + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* stick in our completion routine when the I/O operation completes */ + pIOPacket->Completion = DevGetEventAsyncHandler; + pIOPacket->pContext = pDev; + + if (pDev->GetPendingEventsFunc) { + /* HIF layer has it's own mechanism, pass the IO to it.. */ + status = pDev->GetPendingEventsFunc(pDev->HIFDevice, + (HIF_PENDING_EVENTS_INFO *)pIOPacket->pBuffer, + pIOPacket); + + } else { + /* standard way, read the interrupt register table asynchronously again */ + status = HIFReadWrite(pDev->HIFDevice, + HOST_INT_STATUS_ADDRESS, + pIOPacket->pBuffer, + AR6K_IRQ_PROC_REGS_SIZE, + HIF_RD_ASYNC_BYTE_INC, + pIOPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Async IO issued to get interrupt status...\n")); + } while (FALSE); + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevCheckPendingRecvMsgsAsync \n")); + + return status; +} + +/* process pending interrupts synchronously */ +static A_STATUS ProcessPendingIRQs(AR6K_DEVICE *pDev, A_BOOL *pDone, A_BOOL *pASyncProcessing) +{ + A_STATUS status = A_OK; + A_UINT8 host_int_status = 0; + A_UINT32 lookAhead = 0; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+ProcessPendingIRQs: (dev: 0x%X)\n", (A_UINT32)pDev)); + + /*** NOTE: the HIF implementation guarantees that the context of this call allows + * us to perform SYNCHRONOUS I/O, that is we can block, sleep or call any API that + * can block or switch thread/task ontexts. + * This is a fully schedulable context. + * */ + do { + + if (pDev->IrqEnableRegisters.int_status_enable == 0) { + /* interrupt enables have been cleared, do not try to process any pending interrupts that + * may result in more bus transactions. The target may be unresponsive at this + * point. */ + break; + } + + if (pDev->GetPendingEventsFunc != NULL) { + HIF_PENDING_EVENTS_INFO events; + + /* the HIF layer uses a special mechanism to get events + * get this synchronously */ + status = pDev->GetPendingEventsFunc(pDev->HIFDevice, + &events, + NULL); + + if (A_FAILED(status)) { + break; + } + + if (events.Events & HIF_RECV_MSG_AVAIL) { + lookAhead = events.LookAhead; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs1 lookAhead is zero! \n")); + } + } + + if (!(events.Events & HIF_OTHER_EVENTS) || + !(pDev->IrqEnableRegisters.int_status_enable & OTHER_INTS_ENABLED)) { + /* no need to read the register table, no other interesting interrupts. + * Some interfaces (like SPI) can shadow interrupt sources without + * requiring the host to do a full table read */ + break; + } + + /* otherwise fall through and read the register table */ + } + + /* + * Read the first 28 bytes of the HTC register table. This will yield us + * the value of different int status registers and the lookahead + * registers. + * length = sizeof(int_status) + sizeof(cpu_int_status) + + * sizeof(error_int_status) + sizeof(counter_int_status) + + * sizeof(mbox_frame) + sizeof(rx_lookahead_valid) + + * sizeof(hole) + sizeof(rx_lookahead) + + * sizeof(int_status_enable) + sizeof(cpu_int_status_enable) + + * sizeof(error_status_enable) + + * sizeof(counter_int_status_enable); + * + */ + status = HIFReadWrite(pDev->HIFDevice, + HOST_INT_STATUS_ADDRESS, + (A_UINT8 *)&pDev->IrqProcRegisters, + AR6K_IRQ_PROC_REGS_SIZE, + HIF_RD_SYNC_BYTE_INC, + NULL); + + if (A_FAILED(status)) { + break; + } + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_IRQ)) { + DevDumpRegisters(&pDev->IrqProcRegisters, + &pDev->IrqEnableRegisters); + } + + /* Update only those registers that are enabled */ + host_int_status = pDev->IrqProcRegisters.host_int_status & + pDev->IrqEnableRegisters.int_status_enable; + + if (NULL == pDev->GetPendingEventsFunc) { + /* only look at mailbox status if the HIF layer did not provide this function, + * on some HIF interfaces reading the RX lookahead is not valid to do */ + if (host_int_status & (1 << HTC_MAILBOX)) { + /* mask out pending mailbox value, we use "lookAhead" as the real flag for + * mailbox processing below */ + host_int_status &= ~(1 << HTC_MAILBOX); + if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) { + /* mailbox has a message and the look ahead is valid */ + lookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX]; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs2, lookAhead is zero! \n")); + } + } + } + } else { + /* not valid to check if the HIF has another mechanism for reading mailbox pending status*/ + host_int_status &= ~(1 << HTC_MAILBOX); + } + + } while (FALSE); + + + do { + + /* did the interrupt status fetches succeed? */ + if (A_FAILED(status)) { + break; + } + + if ((0 == host_int_status) && (0 == lookAhead)) { + /* nothing to process, the caller can use this to break out of a loop */ + *pDone = TRUE; + break; + } + + if (lookAhead != 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Pending mailbox message, LookAhead: 0x%X\n",lookAhead)); + /* Mailbox Interrupt, the HTC layer may issue async requests to empty the + * mailbox... + * When emptying the recv mailbox we use the async handler above called from the + * completion routine of the callers read request. This can improve performance + * by reducing context switching when we rapidly pull packets */ + status = pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, pASyncProcessing); + if (A_FAILED(status)) { + break; + } + /* if sync processing of Rx packets is enabled and lookahead of last packet is 0, then + * we can avoid extra CMD53 16-byte read above by setting pDone = TRUE */ + if ((lookAhead == 0) && (*pASyncProcessing == FALSE)) { + *pDone = TRUE; + } + } + + /* now handle the rest of them */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + (" Valid interrupt source(s) for OTHER interrupts: 0x%x\n", + host_int_status)); + + if (HOST_INT_STATUS_CPU_GET(host_int_status)) { + /* CPU Interrupt */ + status = DevServiceCPUInterrupt(pDev); + if (A_FAILED(status)){ + break; + } + } + + if (HOST_INT_STATUS_ERROR_GET(host_int_status)) { + /* Error Interrupt */ + status = DevServiceErrorInterrupt(pDev); + if (A_FAILED(status)){ + break; + } + } + + if (HOST_INT_STATUS_COUNTER_GET(host_int_status)) { + /* Counter Interrupt */ + status = DevServiceCounterInterrupt(pDev); + if (A_FAILED(status)){ + break; + } + } + + } while (FALSE); + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-ProcessPendingIRQs: (done:%d, async:%d) status=%d \n", + *pDone, *pASyncProcessing, status)); + + return status; +} + + +/* Synchronousinterrupt handler, this handler kicks off all interrupt processing.*/ +A_STATUS DevDsrHandler(void *context) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)context; + A_STATUS status = A_OK; + A_BOOL done = FALSE; + A_BOOL asyncProc = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDsrHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); + + + while (!done) { + status = ProcessPendingIRQs(pDev, &done, &asyncProc); + if (A_FAILED(status)) { + break; + } + + if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) { + /* the HIF layer does not allow async IRQ processing, override the asyncProc flag */ + asyncProc = FALSE; + /* this will cause us to re-enter ProcessPendingIRQ() and re-read interrupt status registers. + * this has a nice side effect of blocking us until all async read requests are completed. + * This behavior is required on some HIF implementations that do not allow ASYNC + * processing in interrupt handlers (like Windows CE) */ + } + + if (asyncProc) { + /* the function performed some async I/O for performance, we + need to exit the ISR immediately, the check below will prevent the interrupt from being + Ack'd while we handle it asynchronously */ + break; + } + + } + + if (A_SUCCESS(status) && !asyncProc) { + /* Ack the interrupt only if : + * 1. we did not get any errors in processing interrupts + * 2. there are no outstanding async processing requests */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Acking interrupt from DevDsrHandler \n")); + HIFAckInterrupt(pDev->HIFDevice); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDsrHandler \n")); + return status; +} + + diff -urN linux-2.6.26/drivers/net/wireless/ath6k/ar6kap_common.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6kap_common.h --- linux-2.6.26/drivers/net/wireless/ath6k/ar6kap_common.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6kap_common.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,40 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions of common AP mode data structures. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _AR6KAP_COMMON_H_ +#define _AR6KAP_COMMON_H_ + +/* + * Used with AR6000_XIOCTL_AP_GET_STA_LIST + */ +typedef struct { + A_UINT8 mac[ATH_MAC_LEN]; + A_UINT8 aid; +} station_t; + +typedef struct { + station_t sta[AP_MAX_NUM_STA]; +} ap_get_sta_t; + +#endif /* _AR6KAP_COMMON_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/ar6xapi_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6xapi_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k/ar6xapi_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/ar6xapi_linux.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,158 @@ +#ifndef _AR6XAPI_LINUX_H +#define _AR6XAPI_LINUX_H +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifdef __cplusplus +extern "C" { +#endif + +struct ar6_softc; + +void ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap, + A_UINT32 ver); +A_STATUS ar6000_control_tx(void *devt, void *osbuf, HTC_ENDPOINT_ID eid); +void ar6000_connect_event(struct ar6_softc *ar, A_UINT16 channel, + A_UINT8 *bssid, A_UINT16 listenInterval, + A_UINT16 beaconInterval, NETWORK_TYPE networkType, + A_UINT8 beaconIeLen, A_UINT8 assocReqLen, + A_UINT8 assocRespLen,A_UINT8 *assocInfo); +void ar6000_disconnect_event(struct ar6_softc *ar, A_UINT8 reason, + A_UINT8 *bssid, A_UINT8 assocRespLen, + A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus); +void ar6000_tkip_micerr_event(struct ar6_softc *ar, A_UINT8 keyid, + A_BOOL ismcast); +void ar6000_bitrate_rx(void *devt, A_INT32 rateKbps); +void ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList); +void ar6000_regDomain_event(struct ar6_softc *ar, A_UINT32 regCode); +void ar6000_txPwr_rx(void *devt, A_UINT8 txPwr); +void ar6000_keepalive_rx(void *devt, A_UINT8 configured); +void ar6000_neighborReport_event(struct ar6_softc *ar, int numAps, + WMI_NEIGHBOR_INFO *info); +void ar6000_set_numdataendpts(struct ar6_softc *ar, A_UINT32 num); +void ar6000_scanComplete_event(struct ar6_softc *ar, A_STATUS status); +void ar6000_targetStats_event(struct ar6_softc *ar, WMI_TARGET_STATS *pStats); +void ar6000_rssiThreshold_event(struct ar6_softc *ar, + WMI_RSSI_THRESHOLD_VAL newThreshold, + A_INT16 rssi); +void ar6000_reportError_event(struct ar6_softc *, WMI_TARGET_ERROR_VAL errorVal); +void ar6000_cac_event(struct ar6_softc *ar, A_UINT8 ac, A_UINT8 cac_indication, + A_UINT8 statusCode, A_UINT8 *tspecSuggestion); +void ar6000_channel_change_event(struct ar6_softc *ar, A_UINT16 oldChannel, A_UINT16 newChannel); +void ar6000_hbChallengeResp_event(struct ar6_softc *, A_UINT32 cookie, A_UINT32 source); +void +ar6000_roam_tbl_event(struct ar6_softc *ar, WMI_TARGET_ROAM_TBL *pTbl); + +void +ar6000_roam_data_event(struct ar6_softc *ar, WMI_TARGET_ROAM_DATA *p); + +void +ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters, + WMI_GET_WOW_LIST_REPLY *wow_reply); + +void ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID, + WMI_PMKID *pmkidList, A_UINT8 *bssidList); + +void ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values); +void ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value); +void ar6000_gpio_ack_rx(void); + +void ar6000_dbglog_init_done(struct ar6_softc *ar); + +#ifdef SEND_EVENT_TO_APP +void ar6000_send_event_to_app(struct ar6_softc *ar, A_UINT16 eventId, A_UINT8 *datap, int len); +#endif + +#ifdef CONFIG_HOST_TCMD_SUPPORT +void ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len); +#endif + +void ar6000_tx_retry_err_event(void *devt); + +void ar6000_snrThresholdEvent_rx(void *devt, + WMI_SNR_THRESHOLD_VAL newThreshold, + A_UINT8 snr); + +void ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL range, A_UINT8 lqVal); + + +void ar6000_ratemask_rx(void *devt, A_UINT16 ratemask); + +A_STATUS ar6000_get_driver_cfg(struct net_device *dev, + A_UINT16 cfgParam, + void *result); +void ar6000_bssInfo_event_rx(struct ar6_softc *ar, A_UINT8 *data, int len); + +void ar6000_dbglog_event(struct ar6_softc *ar, A_UINT32 dropped, + A_INT8 *buffer, A_UINT32 length); + +int ar6000_dbglog_get_debug_logs(struct ar6_softc *ar); + +void ar6000_peer_event(void *devt, A_UINT8 eventCode, A_UINT8 *bssid); + +void ar6000_indicate_tx_activity(void *devt, A_UINT8 trafficClass, A_BOOL Active); +HTC_ENDPOINT_ID ar6000_ac2_endpoint_id ( void * devt, A_UINT8 ac); +A_UINT8 ar6000_endpoint_id2_ac (void * devt, HTC_ENDPOINT_ID ep ); + +void ar6000_dset_open_req(void *devt, + A_UINT32 id, + A_UINT32 targ_handle, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); +void ar6000_dset_close(void *devt, A_UINT32 access_cookie); +void ar6000_dset_data_req(void *devt, + A_UINT32 access_cookie, + A_UINT32 offset, + A_UINT32 length, + A_UINT32 targ_buf, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); + + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +void prof_count_rx(unsigned int addr, unsigned int count); +#endif + +A_UINT32 ar6000_getnodeAge (void); + +A_UINT32 ar6000_getclkfreq (void); + +int ar6000_ap_mode_profile_commit(struct ar6_softc *ar); + +struct ieee80211req_wpaie; +A_STATUS +ar6000_ap_mode_get_wpa_ie(struct ar6_softc *ar, struct ieee80211req_wpaie *wpaie); + +A_STATUS is_iwioctl_allowed(A_UINT8 mode, A_UINT16 cmd); + +A_STATUS is_xioctl_allowed(A_UINT8 mode, int cmd); + +void ar6000_pspoll_event(struct ar6_softc *ar,A_UINT8 aid); + +void ar6000_dtimexpiry_event(struct ar6_softc *ar); + +#ifdef __cplusplus +} +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k/athbtfilter.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/athbtfilter.h --- linux-2.6.26/drivers/net/wireless/ath6k/athbtfilter.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/athbtfilter.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,131 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Public Bluetooth filter APIs +// Author(s): ="Atheros" +//============================================================================== +#ifndef ATHBTFILTER_H_ +#define ATHBTFILTER_H_ + + +typedef enum _ATHBT_HCI_CTRL_TYPE { + ATHBT_HCI_COMMAND = 0, + ATHBT_HCI_EVENT = 1, +} ATHBT_HCI_CTRL_TYPE; + +typedef enum _ATHBT_STATE_INDICATION { + ATH_BT_NOOP = 0, + ATH_BT_INQUIRY = 1, + ATH_BT_CONNECT = 2, + ATH_BT_SCO = 3, + ATH_BT_ACL = 4, + ATH_BT_A2DP = 5, + ATH_BT_ESCO = 6, + /* new states go here.. */ + + ATH_BT_MAX_STATE_INDICATION +} ATHBT_STATE_INDICATION; + + /* filter function for OUTGOING commands and INCOMMING events */ +typedef void (*ATHBT_FILTER_CMD_EVENTS_FN)(void *pContext, ATHBT_HCI_CTRL_TYPE Type, unsigned char *pBuffer, int Length); + + /* filter function for OUTGOING data HCI packets */ +typedef void (*ATHBT_FILTER_DATA_FN)(void *pContext, unsigned char *pBuffer, int Length); + +typedef enum _ATHBT_STATE { + STATE_OFF = 0, + STATE_ON = 1, + STATE_MAX +} ATHBT_STATE; + + /* BT state indication (when filter functions are not used) */ + +typedef void (*ATHBT_INDICATE_STATE_FN)(void *pContext, ATHBT_STATE_INDICATION Indication, ATHBT_STATE State, unsigned char LMPVersion); + +typedef struct _ATHBT_FILTER_INSTANCE { +#ifdef UNDER_CE + WCHAR *pWlanAdapterName; /* filled in by user */ +#endif + int FilterEnabled; /* filtering is enabled */ + int Attached; /* filter library is attached */ + void *pContext; /* private context for filter library */ + ATHBT_FILTER_CMD_EVENTS_FN pFilterCmdEvents; /* function ptr to filter a command or event */ + ATHBT_FILTER_DATA_FN pFilterAclDataOut; /* function ptr to filter ACL data out (to radio) */ + ATHBT_FILTER_DATA_FN pFilterAclDataIn; /* function ptr to filter ACL data in (from radio) */ + ATHBT_INDICATE_STATE_FN pIndicateState; /* function ptr to indicate a state */ +} ATH_BT_FILTER_INSTANCE; + + +/* API MACROS */ + +#define AthBtFilterHciCommand(instance,packet,length) \ + if ((instance)->FilterEnabled) { \ + (instance)->pFilterCmdEvents((instance)->pContext, \ + ATHBT_HCI_COMMAND, \ + (unsigned char *)(packet), \ + (length)); \ + } + +#define AthBtFilterHciEvent(instance,packet,length) \ + if ((instance)->FilterEnabled) { \ + (instance)->pFilterCmdEvents((instance)->pContext, \ + ATHBT_HCI_EVENT, \ + (unsigned char *)(packet), \ + (length)); \ + } + +#define AthBtFilterHciAclDataOut(instance,packet,length) \ + if ((instance)->FilterEnabled) { \ + (instance)->pFilterAclDataOut((instance)->pContext, \ + (unsigned char *)(packet), \ + (length)); \ + } + +#define AthBtFilterHciAclDataIn(instance,packet,length) \ + if ((instance)->FilterEnabled) { \ + (instance)->pFilterAclDataIn((instance)->pContext, \ + (unsigned char *)(packet), \ + (length)); \ + } + +/* if filtering is not desired, the application can indicate the state directly using this + * macro: + */ +#define AthBtIndicateState(instance,indication,state) \ + if ((instance)->FilterEnabled) { \ + (instance)->pIndicateState((instance)->pContext, \ + (indication), \ + (state), \ + 0); \ + } + +#ifdef __cplusplus +extern "C" { +#endif + +/* API prototypes */ +int AthBtFilter_Attach(ATH_BT_FILTER_INSTANCE *pInstance); +void AthBtFilter_Detach(ATH_BT_FILTER_INSTANCE *pInstance); + +#ifdef __cplusplus +} +#endif + +#endif /*ATHBTFILTER_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/athdefs.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/athdefs.h --- linux-2.6.26/drivers/net/wireless/ath6k/athdefs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/athdefs.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,84 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef __ATHDEFS_H__ +#define __ATHDEFS_H__ + +/* + * This file contains definitions that may be used across both + * Host and Target software. Nothing here is module-dependent + * or platform-dependent. + */ + +/* + * Generic error codes that can be used by hw, sta, ap, sim, dk + * and any other environments. Since these are enums, feel free to + * add any more codes that you need. + */ + +typedef enum { + A_ERROR = -1, /* Generic error return */ + A_OK = 0, /* success */ + /* Following values start at 1 */ + A_DEVICE_NOT_FOUND, /* not able to find PCI device */ + A_NO_MEMORY, /* not able to allocate memory, not available */ + A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */ + A_NO_FREE_DESC, /* no free descriptors available */ + A_BAD_ADDRESS, /* address does not match descriptor */ + A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */ + A_REGS_NOT_MAPPED, /* registers not correctly mapped */ + A_EPERM, /* Not superuser */ + A_EACCES, /* Access denied */ + A_ENOENT, /* No such entry, search failed, etc. */ + A_EEXIST, /* The object already exists (can't create) */ + A_EFAULT, /* Bad address fault */ + A_EBUSY, /* Object is busy */ + A_EINVAL, /* Invalid parameter */ + A_EMSGSIZE, /* Inappropriate message buffer length */ + A_ECANCELED, /* Operation canceled */ + A_ENOTSUP, /* Operation not supported */ + A_ECOMM, /* Communication error on send */ + A_EPROTO, /* Protocol error */ + A_ENODEV, /* No such device */ + A_EDEVNOTUP, /* device is not UP */ + A_NO_RESOURCE, /* No resources for requested operation */ + A_HARDWARE, /* Hardware failure */ + A_PENDING, /* Asynchronous routine; will send up results la +ter (typically in callback) */ + A_EBADCHANNEL, /* The channel cannot be used */ + A_DECRYPT_ERROR, /* Decryption error */ + A_PHY_ERROR, /* RX PHY error */ + A_CONSUMED /* Object was consumed */ +} A_STATUS; + +#define A_SUCCESS(x) (x == A_OK) +#define A_FAILED(x) (!A_SUCCESS(x)) + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#endif /* __ATHDEFS_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/athdrv.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/athdrv.h --- linux-2.6.26/drivers/net/wireless/ath6k/athdrv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/athdrv.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,35 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _ATHDRV_H_ +#define _ATHDRV_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* _ATHDRV_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/athdrv_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/athdrv_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k/athdrv_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/athdrv_linux.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,1091 @@ +/* + * Copyright (c) 2004-2006 Atheros Communications Inc. + * All rights reserved. + * + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _ATHDRV_LINUX_H +#define _ATHDRV_LINUX_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* + * There are two types of ioctl's here: Standard ioctls and + * eXtended ioctls. All extended ioctls (XIOCTL) are multiplexed + * off of the single ioctl command, AR6000_IOCTL_EXTENDED. The + * arguments for every XIOCTL starts with a 32-bit command word + * that is used to select which extended ioctl is in use. After + * the command word are command-specific arguments. + */ + +/* Linux standard Wireless Extensions, private ioctl interfaces */ +#define IEEE80211_IOCTL_SETPARAM (SIOCIWFIRSTPRIV+0) +#define IEEE80211_IOCTL_SETKEY (SIOCIWFIRSTPRIV+1) +#define IEEE80211_IOCTL_DELKEY (SIOCIWFIRSTPRIV+2) +#define IEEE80211_IOCTL_SETMLME (SIOCIWFIRSTPRIV+3) +#define IEEE80211_IOCTL_ADDPMKID (SIOCIWFIRSTPRIV+4) +#define IEEE80211_IOCTL_SETOPTIE (SIOCIWFIRSTPRIV+5) +//#define IEEE80211_IOCTL_GETPARAM (SIOCIWFIRSTPRIV+6) +//#define IEEE80211_IOCTL_SETWMMPARAMS (SIOCIWFIRSTPRIV+7) +//#define IEEE80211_IOCTL_GETWMMPARAMS (SIOCIWFIRSTPRIV+8) +//#define IEEE80211_IOCTL_GETOPTIE (SIOCIWFIRSTPRIV+9) +//#define IEEE80211_IOCTL_SETAUTHALG (SIOCIWFIRSTPRIV+10) +#define IEEE80211_IOCTL_LASTONE (SIOCIWFIRSTPRIV+10) + + + +/* ====WMI Ioctls==== */ +/* + * + * Many ioctls simply provide WMI services to application code: + * an application makes such an ioctl call with a set of arguments + * that are packaged into the corresponding WMI message, and sent + * to the Target. + */ + +#define AR6000_IOCTL_WMI_GETREV (SIOCIWFIRSTPRIV+11) +/* + * arguments: + * ar6000_version *revision + */ + +#define AR6000_IOCTL_WMI_SETPWR (SIOCIWFIRSTPRIV+12) +/* + * arguments: + * WMI_POWER_MODE_CMD pwrModeCmd (see include/wmi.h) + * uses: WMI_SET_POWER_MODE_CMDID + */ + +#define AR6000_IOCTL_WMI_SETSCAN (SIOCIWFIRSTPRIV+13) +/* + * arguments: + * WMI_SCAN_PARAMS_CMD scanParams (see include/wmi.h) + * uses: WMI_SET_SCAN_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SETLISTENINT (SIOCIWFIRSTPRIV+14) +/* + * arguments: + * UINT32 listenInterval + * uses: WMI_SET_LISTEN_INT_CMDID + */ + +#define AR6000_IOCTL_WMI_SETBSSFILTER (SIOCIWFIRSTPRIV+15) +/* + * arguments: + * WMI_BSS_FILTER filter (see include/wmi.h) + * uses: WMI_SET_BSS_FILTER_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_CHANNELPARAMS (SIOCIWFIRSTPRIV+16) +/* + * arguments: + * WMI_CHANNEL_PARAMS_CMD chParams + * uses: WMI_SET_CHANNEL_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_PROBEDSSID (SIOCIWFIRSTPRIV+17) +/* + * arguments: + * WMI_PROBED_SSID_CMD probedSsids (see include/wmi.h) + * uses: WMI_SETPROBED_SSID_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_PMPARAMS (SIOCIWFIRSTPRIV+18) +/* + * arguments: + * WMI_POWER_PARAMS_CMD powerParams (see include/wmi.h) + * uses: WMI_SET_POWER_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_BADAP (SIOCIWFIRSTPRIV+19) +/* + * arguments: + * WMI_ADD_BAD_AP_CMD badAPs (see include/wmi.h) + * uses: WMI_ADD_BAD_AP_CMDID + */ + +#define AR6000_IOCTL_WMI_GET_QOS_QUEUE (SIOCIWFIRSTPRIV+20) +/* + * arguments: + * ar6000_queuereq queueRequest (see below) + */ + +#define AR6000_IOCTL_WMI_CREATE_QOS (SIOCIWFIRSTPRIV+21) +/* + * arguments: + * WMI_CREATE_PSTREAM createPstreamCmd (see include/wmi.h) + * uses: WMI_CREATE_PSTREAM_CMDID + */ + +#define AR6000_IOCTL_WMI_DELETE_QOS (SIOCIWFIRSTPRIV+22) +/* + * arguments: + * WMI_DELETE_PSTREAM_CMD deletePstreamCmd (see include/wmi.h) + * uses: WMI_DELETE_PSTREAM_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_SNRTHRESHOLD (SIOCIWFIRSTPRIV+23) +/* + * arguments: + * WMI_SNR_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h) + * uses: WMI_SNR_THRESHOLD_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24) +/* + * arguments: + * WMI_TARGET_ERROR_REPORT_BITMASK errorReportBitMask (see include/wmi.h) + * uses: WMI_TARGET_ERROR_REPORT_BITMASK_CMDID + */ + +#define AR6000_IOCTL_WMI_GET_TARGET_STATS (SIOCIWFIRSTPRIV+25) +/* + * arguments: + * TARGET_STATS *targetStats (see below) + * uses: WMI_GET_STATISTICS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_ASSOC_INFO (SIOCIWFIRSTPRIV+26) +/* + * arguments: + * WMI_SET_ASSOC_INFO_CMD setAssocInfoCmd + * uses: WMI_SET_ASSOC_INFO_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_ACCESS_PARAMS (SIOCIWFIRSTPRIV+27) +/* + * arguments: + * WMI_SET_ACCESS_PARAMS_CMD setAccessParams (see include/wmi.h) + * uses: WMI_SET_ACCESS_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_BMISS_TIME (SIOCIWFIRSTPRIV+28) +/* + * arguments: + * UINT32 beaconMissTime + * uses: WMI_SET_BMISS_TIME_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_DISC_TIMEOUT (SIOCIWFIRSTPRIV+29) +/* + * arguments: + * WMI_DISC_TIMEOUT_CMD disconnectTimeoutCmd (see include/wmi.h) + * uses: WMI_SET_DISC_TIMEOUT_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS (SIOCIWFIRSTPRIV+30) +/* + * arguments: + * WMI_IBSS_PM_CAPS_CMD ibssPowerMgmtCapsCmd + * uses: WMI_SET_IBSS_PM_CAPS_CMDID + */ + +/* + * There is a very small space available for driver-private + * wireless ioctls. In order to circumvent this limitation, + * we multiplex a bunch of ioctls (XIOCTLs) on top of a + * single AR6000_IOCTL_EXTENDED ioctl. + */ +#define AR6000_IOCTL_EXTENDED (SIOCIWFIRSTPRIV+31) + + +/* ====BMI Extended Ioctls==== */ + +#define AR6000_XIOCTL_BMI_DONE 1 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_DONE) + * uses: BMI_DONE + */ + +#define AR6000_XIOCTL_BMI_READ_MEMORY 2 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_READ_MEMORY) + * UINT32 address + * UINT32 length + * } + * char results[length] + * } + * uses: BMI_READ_MEMORY + */ + +#define AR6000_XIOCTL_BMI_WRITE_MEMORY 3 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_MEMORY) + * UINT32 address + * UINT32 length + * char data[length] + * uses: BMI_WRITE_MEMORY + */ + +#define AR6000_XIOCTL_BMI_EXECUTE 4 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_EXECUTE) + * UINT32 TargetAddress + * UINT32 parameter + * uses: BMI_EXECUTE + */ + +#define AR6000_XIOCTL_BMI_SET_APP_START 5 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_SET_APP_START) + * UINT32 TargetAddress + * uses: BMI_SET_APP_START + */ + +#define AR6000_XIOCTL_BMI_READ_SOC_REGISTER 6 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_READ_SOC_REGISTER) + * UINT32 TargetAddress, 32-bit aligned + * } + * UINT32 result + * } + * uses: BMI_READ_SOC_REGISTER + */ + +#define AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER 7 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER) + * UINT32 TargetAddress, 32-bit aligned + * UINT32 newValue + * } + * uses: BMI_WRITE_SOC_REGISTER + */ + +#define AR6000_XIOCTL_BMI_TEST 8 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_TEST) + * UINT32 address + * UINT32 length + * UINT32 count + */ + + + +/* Historical Host-side DataSet support */ +#define AR6000_XIOCTL_UNUSED9 9 +#define AR6000_XIOCTL_UNUSED10 10 +#define AR6000_XIOCTL_UNUSED11 11 + +/* ====Misc Extended Ioctls==== */ + +#define AR6000_XIOCTL_FORCE_TARGET_RESET 12 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_FORCE_TARGET_RESET) + */ + + +#ifdef HTC_RAW_INTERFACE +/* HTC Raw Interface Ioctls */ +#define AR6000_XIOCTL_HTC_RAW_OPEN 13 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_OPEN) + */ + +#define AR6000_XIOCTL_HTC_RAW_CLOSE 14 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_CLOSE) + */ + +#define AR6000_XIOCTL_HTC_RAW_READ 15 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_READ) + * UINT32 mailboxID + * UINT32 length + * } + * results[length] + * } + */ + +#define AR6000_XIOCTL_HTC_RAW_WRITE 16 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_WRITE) + * UINT32 mailboxID + * UINT32 length + * char buffer[length] + */ +#endif /* HTC_RAW_INTERFACE */ + +#define AR6000_XIOCTL_CHECK_TARGET_READY 17 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_CHECK_TARGET_READY) + */ + + + +/* ====GPIO (General Purpose I/O) Extended Ioctls==== */ + +#define AR6000_XIOCTL_GPIO_OUTPUT_SET 18 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_OUTPUT_SET) + * ar6000_gpio_output_set_cmd_s (see below) + * uses: WMIX_GPIO_OUTPUT_SET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_INPUT_GET 19 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_INPUT_GET) + * uses: WMIX_GPIO_INPUT_GET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_REGISTER_SET 20 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_SET) + * ar6000_gpio_register_cmd_s (see below) + * uses: WMIX_GPIO_REGISTER_SET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_REGISTER_GET 21 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_GET) + * ar6000_gpio_register_cmd_s (see below) + * uses: WMIX_GPIO_REGISTER_GET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_INTR_ACK 22 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_ACK) + * ar6000_cpio_intr_ack_cmd_s (see below) + * uses: WMIX_GPIO_INTR_ACK_CMDID + */ + +#define AR6000_XIOCTL_GPIO_INTR_WAIT 23 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_WAIT) + */ + + + +/* ====more wireless commands==== */ + +#define AR6000_XIOCTL_SET_ADHOC_BSSID 24 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_ADHOC_BSSID) + * WMI_SET_ADHOC_BSSID_CMD setAdHocBssidCmd (see include/wmi.h) + */ + +#define AR6000_XIOCTL_SET_OPT_MODE 25 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_OPT_MODE) + * WMI_SET_OPT_MODE_CMD setOptModeCmd (see include/wmi.h) + * uses: WMI_SET_OPT_MODE_CMDID + */ + +#define AR6000_XIOCTL_OPT_SEND_FRAME 26 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_OPT_SEND_FRAME) + * WMI_OPT_TX_FRAME_CMD optTxFrameCmd (see include/wmi.h) + * uses: WMI_OPT_TX_FRAME_CMDID + */ + +#define AR6000_XIOCTL_SET_BEACON_INTVAL 27 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_BEACON_INTVAL) + * WMI_BEACON_INT_CMD beaconIntCmd (see include/wmi.h) + * uses: WMI_SET_BEACON_INT_CMDID + */ + + +#define IEEE80211_IOCTL_SETAUTHALG 28 + + +#define AR6000_XIOCTL_SET_VOICE_PKT_SIZE 29 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_VOICE_PKT_SIZE) + * WMI_SET_VOICE_PKT_SIZE_CMD setVoicePktSizeCmd (see include/wmi.h) + * uses: WMI_SET_VOICE_PKT_SIZE_CMDID + */ + + +#define AR6000_XIOCTL_SET_MAX_SP 30 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_MAX_SP) + * WMI_SET_MAX_SP_LEN_CMD maxSPLen(see include/wmi.h) + * uses: WMI_SET_MAX_SP_LEN_CMDID + */ + +#define AR6000_XIOCTL_WMI_GET_ROAM_TBL 31 + +#define AR6000_XIOCTL_WMI_SET_ROAM_CTRL 32 + +#define AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS 33 + + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS) + * WMI_SET_POWERSAVE_TIMERS_CMD powerSaveTimers(see include/wmi.h) + * WMI_SET_POWERSAVE_TIMERS_CMDID + */ + +#define AR6000_XIOCTRL_WMI_GET_POWER_MODE 34 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTRL_WMI_GET_POWER_MODE) + */ + +#define AR6000_XIOCTRL_WMI_SET_WLAN_STATE 35 +typedef enum { + WLAN_DISABLED, + WLAN_ENABLED +} AR6000_WLAN_STATE; +/* + * arguments: + * enable/disable + */ + +#define AR6000_XIOCTL_WMI_GET_ROAM_DATA 36 + +#define AR6000_XIOCTL_WMI_SETRETRYLIMITS 37 +/* + * arguments: + * WMI_SET_RETRY_LIMITS_CMD ibssSetRetryLimitsCmd + * uses: WMI_SET_RETRY_LIMITS_CMDID + */ + +#ifdef CONFIG_HOST_TCMD_SUPPORT +/* ====extended commands for radio test ==== */ + +#define AR6000_XIOCTL_TCMD_CONT_TX 38 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_TX) + * WMI_TCMD_CONT_TX_CMD contTxCmd (see include/wmi.h) + * uses: WMI_TCMD_CONT_TX_CMDID + */ + +#define AR6000_XIOCTL_TCMD_CONT_RX 39 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_RX) + * WMI_TCMD_CONT_RX_CMD rxCmd (see include/wmi.h) + * uses: WMI_TCMD_CONT_RX_CMDID + */ + +#define AR6000_XIOCTL_TCMD_PM 40 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TCMD_PM) + * WMI_TCMD_PM_CMD pmCmd (see include/wmi.h) + * uses: WMI_TCMD_PM_CMDID + */ + +#endif /* CONFIG_HOST_TCMD_SUPPORT */ + +#define AR6000_XIOCTL_WMI_STARTSCAN 41 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_STARTSCAN) + * UINT8 scanType + * UINT8 scanConnected + * A_BOOL forceFgScan + * uses: WMI_START_SCAN_CMDID + */ + +#define AR6000_XIOCTL_WMI_SETFIXRATES 42 + +#define AR6000_XIOCTL_WMI_GETFIXRATES 43 + + +#define AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD 44 +/* + * arguments: + * WMI_RSSI_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h) + * uses: WMI_RSSI_THRESHOLD_PARAMS_CMDID + */ + +#define AR6000_XIOCTL_WMI_CLR_RSSISNR 45 +/* + * arguments: + * WMI_CLR_RSSISNR_CMD thresholdParams (see include/wmi.h) + * uses: WMI_CLR_RSSISNR_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_LQTHRESHOLD 46 +/* + * arguments: + * WMI_LQ_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h) + * uses: WMI_LQ_THRESHOLD_PARAMS_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_RTS 47 +/* + * arguments: + * WMI_SET_RTS_MODE_CMD (see include/wmi.h) + * uses: WMI_SET_RTS_MODE_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_LPREAMBLE 48 + +#define AR6000_XIOCTL_WMI_SET_AUTHMODE 49 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_AUTHMODE) + * UINT8 mode + * uses: WMI_SET_RECONNECT_AUTH_MODE_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_REASSOCMODE 50 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_WMM) + * UINT8 mode + * uses: WMI_SET_WMM_CMDID + */ +#define AR6000_XIOCTL_WMI_SET_WMM 51 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS) + * UINT32 frequency + * UINT8 threshold + */ +#define AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS 52 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP) + * UINT32 cookie + */ +#define AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP 53 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_GET_RD) + * UINT32 regDomain + */ +#define AR6000_XIOCTL_WMI_GET_RD 54 + +#define AR6000_XIOCTL_DIAG_READ 55 + +#define AR6000_XIOCTL_DIAG_WRITE 56 + +/* + * arguments cmd (AR6000_XIOCTL_SET_TXOP) + * WMI_TXOP_CFG txopEnable + */ +#define AR6000_XIOCTL_WMI_SET_TXOP 57 + +#ifdef USER_KEYS +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_USER_SETKEYS) + * UINT32 keyOpCtrl + * uses AR6000_USER_SETKEYS_INFO + */ +#define AR6000_XIOCTL_USER_SETKEYS 58 +#endif /* USER_KEYS */ + +#define AR6000_XIOCTL_WMI_SET_KEEPALIVE 59 +/* + * arguments: + * UINT8 cmd (AR6000_XIOCTL_WMI_SET_KEEPALIVE) + * UINT8 keepaliveInterval + * uses: WMI_SET_KEEPALIVE_CMDID + */ + +#define AR6000_XIOCTL_WMI_GET_KEEPALIVE 60 +/* + * arguments: + * UINT8 cmd (AR6000_XIOCTL_WMI_GET_KEEPALIVE) + * UINT8 keepaliveInterval + * A_BOOL configured + * uses: WMI_GET_KEEPALIVE_CMDID + */ + +/* ====ROM Patching Extended Ioctls==== */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_INSTALL 61 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_INSTALL) + * UINT32 ROM Address + * UINT32 RAM Address + * UINT32 number of bytes + * UINT32 activate? (0 or 1) + * } + * A_UINT32 resulting rompatch ID + * } + * uses: BMI_ROMPATCH_INSTALL + */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL 62 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL) + * UINT32 rompatch ID + * } + * uses: BMI_ROMPATCH_UNINSTALL + */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE 63 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE) + * UINT32 rompatch count + * UINT32 rompatch IDs[rompatch count] + * } + * uses: BMI_ROMPATCH_ACTIVATE + */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE 64 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE) + * UINT32 rompatch count + * UINT32 rompatch IDs[rompatch count] + * } + * uses: BMI_ROMPATCH_DEACTIVATE + */ + +#define AR6000_XIOCTL_WMI_SET_APPIE 65 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_APPIE) + * UINT32 app_frmtype; + * UINT32 app_buflen; + * UINT8 app_buf[]; + * } + */ +#define AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER 66 +/* + * arguments: + * A_UINT32 filter_type; + */ + +#define AR6000_XIOCTL_DBGLOG_CFG_MODULE 67 + +#define AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS 68 + +#define AR6000_XIOCTL_WMI_SET_WSC_STATUS 70 +/* + * arguments: + * A_UINT32 wsc_status; + * (WSC_REG_INACTIVE or WSC_REG_ACTIVE) + */ + +/* + * arguments: + * struct { + * A_UINT8 streamType; + * A_UINT8 status; + * } + * uses: WMI_SET_BT_STATUS_CMDID + */ +#define AR6000_XIOCTL_WMI_SET_BT_STATUS 71 + +/* + * arguments: + * struct { + * A_UINT8 paramType; + * union { + * A_UINT8 noSCOPkts; + * BT_PARAMS_A2DP a2dpParams; + * BT_COEX_REGS regs; + * }; + * } + * uses: WMI_SET_BT_PARAM_CMDID + */ +#define AR6000_XIOCTL_WMI_SET_BT_PARAMS 72 + +#define AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE 73 +#define AR6000_XIOCTL_WMI_SET_WOW_MODE 74 +#define AR6000_XIOCTL_WMI_GET_WOW_LIST 75 +#define AR6000_XIOCTL_WMI_ADD_WOW_PATTERN 76 +#define AR6000_XIOCTL_WMI_DEL_WOW_PATTERN 77 + + + +#define AR6000_XIOCTL_TARGET_INFO 78 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TARGET_INFO) + * A_UINT32 TargetVersion (returned) + * A_UINT32 TargetType (returned) + * (See also bmi_msg.h target_ver and target_type) + */ + +#define AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE 79 +/* + * arguments: + * none + */ + +#define AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE 80 +/* + * This ioctl is used to emulate traffic activity + * timeouts. Activity/inactivity will trigger the driver + * to re-balance credits. + * + * arguments: + * ar6000_traffic_activity_change + */ + +#define AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS 81 +/* + * This ioctl is used to set the connect control flags + * + * arguments: + * A_UINT32 connectCtrlFlags + */ + +#define AR6000_XIOCTL_WMI_SET_AKMP_PARAMS 82 +/* + * This IOCTL sets any Authentication,Key Management and Protection + * related parameters. This is used along with the information set in + * Connect Command. + * Currently this enables Multiple PMKIDs to an AP. + * + * arguments: + * struct { + * A_UINT32 akmpInfo; + * } + * uses: WMI_SET_AKMP_PARAMS_CMD + */ + +#define AR6000_XIOCTL_WMI_GET_PMKID_LIST 83 + +#define AR6000_XIOCTL_WMI_SET_PMKID_LIST 84 +/* + * This IOCTL is used to set a list of PMKIDs. This list of + * PMKIDs is used in the [Re]AssocReq Frame. This list is used + * only if the MultiPMKID option is enabled via the + * AR6000_XIOCTL_WMI_SET_AKMP_PARAMS IOCTL. + * + * arguments: + * struct { + * A_UINT32 numPMKID; + * WMI_PMKID pmkidList[WMI_MAX_PMKID_CACHE]; + * } + * uses: WMI_SET_PMKIDLIST_CMD + */ + +#define AR6000_XIOCTL_WMI_SET_PARAMS 85 +#define AR6000_XIOCTL_WMI_SET_MCAST_FILTER 86 +#define AR6000_XIOCTL_WMI_DEL_MCAST_FILTER 87 + + +/* Historical DSETPATCH support for INI patches */ +#define AR6000_XIOCTL_UNUSED90 90 + + +/* Support LZ-compressed firmware download */ +#define AR6000_XIOCTL_BMI_LZ_STREAM_START 91 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_LZ_STREAM_START) + * UINT32 address + * uses: BMI_LZ_STREAM_START + */ + +#define AR6000_XIOCTL_BMI_LZ_DATA 92 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_LZ_DATA) + * UINT32 length + * char data[length] + * uses: BMI_LZ_DATA + */ + +#define AR6000_XIOCTL_PROF_CFG 93 +/* + * arguments: + * A_UINT32 period + * A_UINT32 nbins + */ + +#define AR6000_XIOCTL_PROF_ADDR_SET 94 +/* + * arguments: + * A_UINT32 Target address + */ + +#define AR6000_XIOCTL_PROF_START 95 + +#define AR6000_XIOCTL_PROF_STOP 96 + +#define AR6000_XIOCTL_PROF_COUNT_GET 97 + +#define AR6000_XIOCTL_WMI_ABORT_SCAN 98 + +/* + * AP mode + */ +#define AR6000_XIOCTL_AP_GET_STA_LIST 99 + +#define AR6000_XIOCTL_AP_HIDDEN_SSID 100 + +#define AR6000_XIOCTL_AP_SET_NUM_STA 101 + +#define AR6000_XIOCTL_AP_SET_ACL_MAC 102 + +#define AR6000_XIOCTL_AP_GET_ACL_LIST 103 + +#define AR6000_XIOCTL_AP_COMMIT_CONFIG 104 + +#define IEEE80211_IOCTL_GETWPAIE 105 + +#define AR6000_XIOCTL_AP_CONN_INACT_TIME 106 + +#define AR6000_XIOCTL_AP_PROT_SCAN_TIME 107 + +#define AR6000_XIOCTL_AP_SET_COUNTRY 108 + +#define AR6000_XIOCTL_AP_SET_DTIM 109 + + + + +#define AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT 110 + +#define AR6000_XIOCTL_SET_IP 111 + +#define AR6000_XIOCTL_AP_SET_ACL_POLICY 112 + +#define AR6000_XIOCTL_AP_INTRA_BSS_COMM 113 + +/* used by AR6000_IOCTL_WMI_GETREV */ +struct ar6000_version { + A_UINT32 host_ver; + A_UINT32 target_ver; + A_UINT32 wlan_ver; +}; + +/* used by AR6000_IOCTL_WMI_GET_QOS_QUEUE */ +struct ar6000_queuereq { + A_UINT8 trafficClass; + A_UINT16 activeTsids; +}; + +/* used by AR6000_IOCTL_WMI_GET_TARGET_STATS */ +typedef struct targetStats_t { + A_UINT64 tx_packets; + A_UINT64 tx_bytes; + A_UINT64 tx_unicast_pkts; + A_UINT64 tx_unicast_bytes; + A_UINT64 tx_multicast_pkts; + A_UINT64 tx_multicast_bytes; + A_UINT64 tx_broadcast_pkts; + A_UINT64 tx_broadcast_bytes; + A_UINT64 tx_rts_success_cnt; + A_UINT64 tx_packet_per_ac[4]; + + A_UINT64 tx_errors; + A_UINT64 tx_failed_cnt; + A_UINT64 tx_retry_cnt; + A_UINT64 tx_mult_retry_cnt; + A_UINT64 tx_rts_fail_cnt; + + A_UINT64 rx_packets; + A_UINT64 rx_bytes; + A_UINT64 rx_unicast_pkts; + A_UINT64 rx_unicast_bytes; + A_UINT64 rx_multicast_pkts; + A_UINT64 rx_multicast_bytes; + A_UINT64 rx_broadcast_pkts; + A_UINT64 rx_broadcast_bytes; + A_UINT64 rx_fragment_pkt; + + A_UINT64 rx_errors; + A_UINT64 rx_crcerr; + A_UINT64 rx_key_cache_miss; + A_UINT64 rx_decrypt_err; + A_UINT64 rx_duplicate_frames; + + A_UINT64 tkip_local_mic_failure; + A_UINT64 tkip_counter_measures_invoked; + A_UINT64 tkip_replays; + A_UINT64 tkip_format_errors; + A_UINT64 ccmp_format_errors; + A_UINT64 ccmp_replays; + + A_UINT64 power_save_failure_cnt; + + A_UINT64 cs_bmiss_cnt; + A_UINT64 cs_lowRssi_cnt; + A_UINT64 cs_connect_cnt; + A_UINT64 cs_disconnect_cnt; + + A_INT32 tx_unicast_rate; + A_INT32 rx_unicast_rate; + + A_UINT32 lq_val; + + A_UINT32 wow_num_pkts_dropped; + A_UINT16 wow_num_events_discarded; + + A_INT16 noise_floor_calibation; + A_INT16 cs_rssi; + A_INT16 cs_aveBeacon_rssi; + A_UINT8 cs_aveBeacon_snr; + A_UINT8 cs_lastRoam_msec; + A_UINT8 cs_snr; + + A_UINT8 wow_num_host_pkt_wakeups; + A_UINT8 wow_num_host_event_wakeups; + + A_UINT32 arp_received; + A_UINT32 arp_matched; + A_UINT32 arp_replied; +}TARGET_STATS; + +typedef struct targetStats_cmd_t { + TARGET_STATS targetStats; + int clearStats; +} TARGET_STATS_CMD; + +/* used by AR6000_XIOCTL_USER_SETKEYS */ + +/* + * Setting this bit to 1 doesnot initialize the RSC on the firmware + */ +#define AR6000_XIOCTL_USER_SETKEYS_RSC_CTRL 1 +#define AR6000_USER_SETKEYS_RSC_UNCHANGED 0x00000002 + +typedef struct { + A_UINT32 keyOpCtrl; /* Bit Map of Key Mgmt Ctrl Flags */ +} AR6000_USER_SETKEYS_INFO; + + +/* used by AR6000_XIOCTL_GPIO_OUTPUT_SET */ +struct ar6000_gpio_output_set_cmd_s { + A_UINT32 set_mask; + A_UINT32 clear_mask; + A_UINT32 enable_mask; + A_UINT32 disable_mask; +}; + +/* + * used by AR6000_XIOCTL_GPIO_REGISTER_GET and AR6000_XIOCTL_GPIO_REGISTER_SET + */ +struct ar6000_gpio_register_cmd_s { + A_UINT32 gpioreg_id; + A_UINT32 value; +}; + +/* used by AR6000_XIOCTL_GPIO_INTR_ACK */ +struct ar6000_gpio_intr_ack_cmd_s { + A_UINT32 ack_mask; +}; + +/* used by AR6000_XIOCTL_GPIO_INTR_WAIT */ +struct ar6000_gpio_intr_wait_cmd_s { + A_UINT32 intr_mask; + A_UINT32 input_values; +}; + +/* used by the AR6000_XIOCTL_DBGLOG_CFG_MODULE */ +typedef struct ar6000_dbglog_module_config_s { + A_UINT32 valid; + A_UINT16 mmask; + A_UINT16 tsr; + A_BOOL rep; + A_UINT16 size; +} DBGLOG_MODULE_CONFIG; + +typedef struct user_rssi_thold_t { + A_INT16 tag; + A_INT16 rssi; +} USER_RSSI_THOLD; + +typedef struct user_rssi_params_t { + A_UINT8 weight; + A_UINT32 pollTime; + USER_RSSI_THOLD tholds[12]; +} USER_RSSI_PARAMS; + +/* + * Host driver may have some config parameters. Typically, these + * config params are one time config parameters. These could + * correspond to any of the underlying modules. Host driver exposes + * an api for the underlying modules to get this config. + */ +#define AR6000_DRIVER_CFG_BASE 0x8000 + +/* Should driver perform wlan node caching? */ +#define AR6000_DRIVER_CFG_GET_WLANNODECACHING 0x8001 +/*Should we log raw WMI msgs */ +#define AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS 0x8002 + +/* used by AR6000_XIOCTL_DIAG_READ & AR6000_XIOCTL_DIAG_WRITE */ +struct ar6000_diag_window_cmd_s { + unsigned int addr; + unsigned int value; +}; + + +struct ar6000_traffic_activity_change { + A_UINT32 StreamID; /* stream ID to indicate activity change */ + A_UINT32 Active; /* active (1) or inactive (0) */ +}; + +/* Used with AR6000_XIOCTL_PROF_COUNT_GET */ +struct prof_count_s { + A_UINT32 addr; /* bin start address */ + A_UINT32 count; /* hit count */ +}; + +#ifdef __cplusplus +} +#endif +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k/athendpack.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/athendpack.h --- linux-2.6.26/drivers/net/wireless/ath6k/athendpack.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/athendpack.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,49 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// end compiler-specific structure packing +// +// Author(s): ="Atheros" +//============================================================================== +#ifdef VXWORKS +#endif /* VXWORKS */ + +#if defined(LINUX) || defined(__linux__) +#endif /* LINUX */ + +#ifdef QNX +#endif /* QNX */ + +#ifdef INTEGRITY +#include "integrity/athendpack_integrity.h" +#endif /* INTEGRITY */ + +#ifdef NUCLEUS +#endif /* NUCLEUS */ + + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/athendpack_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/athendpack_wince.h" +#endif /* WINCE */ + diff -urN linux-2.6.26/drivers/net/wireless/ath6k/athstartpack.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/athstartpack.h --- linux-2.6.26/drivers/net/wireless/ath6k/athstartpack.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/athstartpack.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,48 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// start compiler-specific structure packing +// +// Author(s): ="Atheros" +//============================================================================== +#ifdef VXWORKS +#endif /* VXWORKS */ + +#if defined(LINUX) || defined(__linux__) +#endif /* LINUX */ + +#ifdef QNX +#endif /* QNX */ + +#ifdef INTEGRITY +#include "integrity/athstartpack_integrity.h" +#endif /* INTEGRITY */ + +#ifdef NUCLEUS +#endif /* NUCLEUS */ + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/athstartpack_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/athstartpack_wince.h" +#endif /* WINCE */ + diff -urN linux-2.6.26/drivers/net/wireless/ath6k/athtypes_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/athtypes_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k/athtypes_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/athtypes_linux.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,56 @@ +/* + * $Id: //depot/sw/releases/olca2.2/host/os/linux/include/athtypes_linux.h#2 $ + * + * This file contains the definitions of the basic atheros data types. + * It is used to map the data types in atheros files to a platform specific + * type. + * + * Copyright 2003-2005 Atheros Communications, Inc., All Rights Reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _ATHTYPES_LINUX_H_ +#define _ATHTYPES_LINUX_H_ + +#ifdef ANDROID +#include +#include +#else +#ifdef __KERNEL__ +#include +#endif +#endif + +typedef int8_t A_INT8; +typedef int16_t A_INT16; +typedef int32_t A_INT32; +typedef int64_t A_INT64; + +typedef u_int8_t A_UINT8; +typedef u_int16_t A_UINT16; +typedef u_int32_t A_UINT32; +typedef u_int64_t A_UINT64; + +typedef int A_BOOL; +typedef char A_CHAR; +typedef unsigned char A_UCHAR; +typedef unsigned long A_ATH_TIMER; + + +#endif /* _ATHTYPES_LINUX_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/bmi.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/bmi.c --- linux-2.6.26/drivers/net/wireless/ath6k/bmi.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/bmi.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,879 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// +// Author(s): ="Atheros" +//============================================================================== + +#include "hif.h" +#include "bmi.h" +#include "htc_api.h" +#include "bmi_internal.h" + +/* +Although we had envisioned BMI to run on top of HTC, this is not how the +final implementation ended up. On the Target side, BMI is a part of the BSP +and does not use the HTC protocol nor even DMA -- it is intentionally kept +very simple. +*/ + +static A_BOOL pendingEventsFuncCheck = FALSE; + +/* APIs visible to the driver */ +void +BMIInit(void) +{ + bmiDone = FALSE; + pendingEventsFuncCheck = FALSE; +} + +A_STATUS +BMIDone(HIF_DEVICE *device) +{ + A_STATUS status; + A_UINT32 cid; + + if (bmiDone) { + AR_DEBUG_PRINTF (ATH_DEBUG_BMI, ("BMIDone skipped\n")); + return A_OK; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Enter (device: 0x%p)\n", device)); + bmiDone = TRUE; + cid = BMI_DONE; + + status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid)); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Exit\n")); + + return A_OK; +} + +A_STATUS +BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info) +{ + A_STATUS status; + A_UINT32 cid; + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Enter (device: 0x%p)\n", device)); + cid = BMI_GET_TARGET_INFO; + + status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid)); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_ver, + sizeof(targ_info->target_ver), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Version from the device\n")); + return A_ERROR; + } + + if (targ_info->target_ver == TARGET_VERSION_SENTINAL) { + /* Determine how many bytes are in the Target's targ_info */ + status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_info_byte_count, + sizeof(targ_info->target_info_byte_count), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info Byte Count from the device\n")); + return A_ERROR; + } + + /* + * The Target's targ_info doesn't match the Host's targ_info. + * We need to do some backwards compatibility work to make this OK. + */ + A_ASSERT(targ_info->target_info_byte_count == sizeof(*targ_info)); + + /* Read the remainder of the targ_info */ + status = bmiBufferReceive(device, + ((A_UCHAR *)targ_info)+sizeof(targ_info->target_info_byte_count), + sizeof(*targ_info)-sizeof(targ_info->target_info_byte_count), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info (%d bytes) from the device\n", + targ_info->target_info_byte_count)); + return A_ERROR; + } + } else { + /* + * Target must be an AR6001 whose firmware does not + * support BMI_GET_TARGET_INFO. Construct the data + * that it would have sent. + */ + targ_info->target_info_byte_count=sizeof(*targ_info); + targ_info->target_type=TARGET_TYPE_AR6001; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Exit (ver: 0x%x type: 0x%x)\n", + targ_info->target_ver, targ_info->target_type)); + + return A_OK; +} + +A_STATUS +BMIReadMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + A_UINT32 remaining, rxlen; + static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)]; + memset (&data, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Read Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n", + device, address, length)); + + cid = BMI_READ_MEMORY; + + remaining = length; + + while (remaining) + { + rxlen = (remaining < BMI_DATASZ_MAX) ? remaining : BMI_DATASZ_MAX; + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&data[offset], &rxlen, sizeof(rxlen)); + offset += sizeof(length); + + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + status = bmiBufferReceive(device, data, rxlen, TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + A_MEMCPY(&buffer[length - remaining], data, rxlen); + remaining -= rxlen; address += rxlen; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read Memory: Exit\n")); + return A_OK; +} + +A_STATUS +BMIWriteMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + A_UINT32 remaining, txlen; + const A_UINT32 header = sizeof(cid) + sizeof(address) + sizeof(length); + static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)]; + memset (&data, 0, BMI_DATASZ_MAX+header); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Write Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n", + device, address, length)); + + cid = BMI_WRITE_MEMORY; + + remaining = length; + while (remaining) + { + txlen = (remaining < (BMI_DATASZ_MAX - header)) ? + remaining : (BMI_DATASZ_MAX - header); + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&data[offset], &txlen, sizeof(txlen)); + offset += sizeof(txlen); + A_MEMCPY(&data[offset], &buffer[length - remaining], txlen); + offset += txlen; + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + remaining -= txlen; address += txlen; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Write Memory: Exit\n")); + + return A_OK; +} + +A_STATUS +BMIExecute(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address) + sizeof(*param)]; + memset (&data, 0, sizeof(cid) + sizeof(address) + sizeof(*param)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Execute: Enter (device: 0x%p, address: 0x%x, param: %d)\n", + device, address, *param)); + + cid = BMI_EXECUTE; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&data[offset], param, sizeof(*param)); + offset += sizeof(*param); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, data, sizeof(*param), FALSE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + + A_MEMCPY(param, data, sizeof(*param)); + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Execute: Exit (param: %d)\n", *param)); + return A_OK; +} + +A_STATUS +BMISetAppStart(HIF_DEVICE *device, + A_UINT32 address) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address)]; + memset (&data, 0, sizeof(cid) + sizeof(address)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Set App Start: Enter (device: 0x%p, address: 0x%x)\n", + device, address)); + + cid = BMI_SET_APP_START; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Set App Start: Exit\n")); + return A_OK; +} + +A_STATUS +BMIReadSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address)]; + memset (&data, 0, sizeof(cid) + sizeof(address)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Read SOC Register: Enter (device: 0x%p, address: 0x%x)\n", + device, address)); + + cid = BMI_READ_SOC_REGISTER; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, data, sizeof(*param), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + A_MEMCPY(param, data, sizeof(*param)); + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit (value: %d)\n", *param)); + return A_OK; +} + +A_STATUS +BMIWriteSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 param) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address) + sizeof(param)]; + + memset (&data, 0, sizeof(cid) + sizeof(address) + sizeof(param)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Write SOC Register: Enter (device: 0x%p, address: 0x%x, param: %d)\n", + device, address, param)); + + cid = BMI_WRITE_SOC_REGISTER; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&data[offset], ¶m, sizeof(param)); + offset += sizeof(param); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit\n")); + return A_OK; +} + +A_STATUS +BMIrompatchInstall(HIF_DEVICE *device, + A_UINT32 ROM_addr, + A_UINT32 RAM_addr, + A_UINT32 nbytes, + A_UINT32 do_activate, + A_UINT32 *rompatch_id) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) + + sizeof(nbytes) + sizeof(do_activate)]; + + memset (&data, 0, sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) + + sizeof(nbytes) + sizeof(do_activate)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI rompatch Install: Enter (device: 0x%p, ROMaddr: 0x%x, RAMaddr: 0x%x length: %d activate: %d)\n", + device, ROM_addr, RAM_addr, nbytes, do_activate)); + + cid = BMI_ROMPATCH_INSTALL; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &ROM_addr, sizeof(ROM_addr)); + offset += sizeof(ROM_addr); + A_MEMCPY(&data[offset], &RAM_addr, sizeof(RAM_addr)); + offset += sizeof(RAM_addr); + A_MEMCPY(&data[offset], &nbytes, sizeof(nbytes)); + offset += sizeof(nbytes); + A_MEMCPY(&data[offset], &do_activate, sizeof(do_activate)); + offset += sizeof(do_activate); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, (A_UCHAR *)rompatch_id, sizeof(*rompatch_id), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch Install: (rompatch_id=%d)\n", *rompatch_id)); + return A_OK; +} + +A_STATUS +BMIrompatchUninstall(HIF_DEVICE *device, + A_UINT32 rompatch_id) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(rompatch_id)]; + memset (&data, 0, sizeof(cid) + sizeof(rompatch_id)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI rompatch Uninstall: Enter (device: 0x%p, rompatch_id: %d)\n", + device, rompatch_id)); + + cid = BMI_ROMPATCH_UNINSTALL; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &rompatch_id, sizeof(rompatch_id)); + offset += sizeof(rompatch_id); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch UNinstall: (rompatch_id=0x%x)\n", rompatch_id)); + return A_OK; +} + +static A_STATUS +_BMIrompatchChangeActivation(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list, + A_UINT32 do_activate) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count)]; + A_UINT32 length; + + memset (&data, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Change rompatch Activation: Enter (device: 0x%p, count: %d)\n", + device, rompatch_count)); + + cid = do_activate ? BMI_ROMPATCH_ACTIVATE : BMI_ROMPATCH_DEACTIVATE; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &rompatch_count, sizeof(rompatch_count)); + offset += sizeof(rompatch_count); + length = rompatch_count * sizeof(*rompatch_list); + A_MEMCPY(&data[offset], rompatch_list, length); + offset += length; + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Change rompatch Activation: Exit\n")); + + return A_OK; +} + +A_STATUS +BMIrompatchActivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list) +{ + return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 1); +} + +A_STATUS +BMIrompatchDeactivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list) +{ + return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 0); +} + +A_STATUS +BMILZData(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + A_UINT32 remaining, txlen; + const A_UINT32 header = sizeof(cid) + sizeof(length); + static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(length)]; + + memset (&data, 0, BMI_DATASZ_MAX+header); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Send LZ Data: Enter (device: 0x%p, length: %d)\n", + device, length)); + + cid = BMI_LZ_DATA; + + remaining = length; + while (remaining) + { + txlen = (remaining < (BMI_DATASZ_MAX - header)) ? + remaining : (BMI_DATASZ_MAX - header); + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &txlen, sizeof(txlen)); + offset += sizeof(txlen); + A_MEMCPY(&data[offset], &buffer[length - remaining], txlen); + offset += txlen; + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + remaining -= txlen; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI LZ Data: Exit\n")); + + return A_OK; +} + +A_STATUS +BMILZStreamStart(HIF_DEVICE *device, + A_UINT32 address) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address)]; + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI LZ Stream Start: Enter (device: 0x%p, address: 0x%x)\n", + device, address)); + + cid = BMI_LZ_STREAM_START; + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to Start LZ Stream to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI LZ Stream Start: Exit\n")); + + return A_OK; +} + +/* BMI Access routines */ +A_STATUS +bmiBufferSend(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_STATUS status; + A_UINT32 timeout; + A_UINT32 address; + static A_UINT32 cmdCredits; + A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX]; + + HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR, + &mboxAddress[0], sizeof(mboxAddress)); + + cmdCredits = 0; + timeout = BMI_COMMUNICATION_TIMEOUT; + + while(timeout-- && !cmdCredits) { + /* Read the counter register to get the command credits */ + address = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4; + /* hit the credit counter with a 4-byte access, the first byte read will hit the counter and cause + * a decrement, while the remaining 3 bytes has no effect. The rationale behind this is to + * make all HIF accesses 4-byte aligned */ + status = HIFReadWrite(device, address, (A_UINT8 *)&cmdCredits, 4, + HIF_RD_SYNC_BYTE_INC, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to decrement the command credit count register\n")); + return A_ERROR; + } + /* the counter is only 8=bits, ignore anything in the upper 3 bytes */ + cmdCredits &= 0xFF; + } + + if (cmdCredits) { + address = mboxAddress[ENDPOINT1]; + status = HIFReadWrite(device, address, buffer, length, + HIF_WR_SYNC_BYTE_INC, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to send the BMI data to the device\n")); + return A_ERROR; + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout - bmiBufferSend\n")); + return A_ERROR; + } + + return status; +} + +A_STATUS +bmiBufferReceive(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length, + A_BOOL want_timeout) +{ + A_STATUS status; + A_UINT32 address; + A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX]; + HIF_PENDING_EVENTS_INFO hifPendingEvents; + static HIF_PENDING_EVENTS_FUNC getPendingEventsFunc = NULL; + + if (!pendingEventsFuncCheck) { + /* see if the HIF layer implements an alternative function to get pending events + * do this only once! */ + HIFConfigureDevice(device, + HIF_DEVICE_GET_PENDING_EVENTS_FUNC, + &getPendingEventsFunc, + sizeof(getPendingEventsFunc)); + pendingEventsFuncCheck = TRUE; + } + + HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR, + &mboxAddress[0], sizeof(mboxAddress)); + + /* + * During normal bootup, small reads may be required. + * Rather than issue an HIF Read and then wait as the Target + * adds successive bytes to the FIFO, we wait here until + * we know that response data is available. + * + * This allows us to cleanly timeout on an unexpected + * Target failure rather than risk problems at the HIF level. In + * particular, this avoids SDIO timeouts and possibly garbage + * data on some host controllers. And on an interconnect + * such as Compact Flash (as well as some SDIO masters) which + * does not provide any indication on data timeout, it avoids + * a potential hang or garbage response. + * + * Synchronization is more difficult for reads larger than the + * size of the MBOX FIFO (128B), because the Target is unable + * to push the 129th byte of data until AFTER the Host posts an + * HIF Read and removes some FIFO data. So for large reads the + * Host proceeds to post an HIF Read BEFORE all the data is + * actually available to read. Fortunately, large BMI reads do + * not occur in practice -- they're supported for debug/development. + * + * So Host/Target BMI synchronization is divided into these cases: + * CASE 1: length < 4 + * Should not happen + * + * CASE 2: 4 <= length <= 128 + * Wait for first 4 bytes to be in FIFO + * If CONSERVATIVE_BMI_READ is enabled, also wait for + * a BMI command credit, which indicates that the ENTIRE + * response is available in the the FIFO + * + * CASE 3: length > 128 + * Wait for the first 4 bytes to be in FIFO + * + * For most uses, a small timeout should be sufficient and we will + * usually see a response quickly; but there may be some unusual + * (debug) cases of BMI_EXECUTE where we want an larger timeout. + * For now, we use an unbounded busy loop while waiting for + * BMI_EXECUTE. + * + * If BMI_EXECUTE ever needs to support longer-latency execution, + * especially in production, this code needs to be enhanced to sleep + * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently + * a function of Host processor speed. + */ + if (length >= 4) { /* NB: Currently, always true */ + /* + * NB: word_available is declared static for esoteric reasons + * having to do with protection on some OSes. + */ + static A_UINT32 word_available; + A_UINT32 timeout; + + word_available = 0; + timeout = BMI_COMMUNICATION_TIMEOUT; + while((!want_timeout || timeout--) && !word_available) { + + if (getPendingEventsFunc != NULL) { + status = getPendingEventsFunc(device, + &hifPendingEvents, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMI: Failed to get pending events \n")); + break; + } + + if (hifPendingEvents.AvailableRecvBytes >= sizeof(A_UINT32)) { + word_available = 1; + } + continue; + } + + status = HIFReadWrite(device, RX_LOOKAHEAD_VALID_ADDRESS, (A_UINT8 *)&word_available, + sizeof(word_available), HIF_RD_SYNC_BYTE_INC, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read RX_LOOKAHEAD_VALID register\n")); + return A_ERROR; + } + /* We did a 4-byte read to the same register; all we really want is one bit */ + word_available &= (1 << ENDPOINT1); + } + + if (!word_available) { + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Communication timeout - bmiBufferReceive FIFO empty\n")); + return A_ERROR; + } + } + +#define CONSERVATIVE_BMI_READ 0 +#if CONSERVATIVE_BMI_READ + /* + * This is an extra-conservative CREDIT check. It guarantees + * that ALL data is available in the FIFO before we start to + * read from the interconnect. + * + * This credit check is useless when firmware chooses to + * allow multiple outstanding BMI Command Credits, since the next + * credit will already be present. To restrict the Target to one + * BMI Command Credit, see HI_OPTION_BMI_CRED_LIMIT. + * + * And for large reads (when HI_OPTION_BMI_CRED_LIMIT is set) + * we cannot wait for the next credit because the Target's FIFO + * will not hold the entire response. So we need the Host to + * start to empty the FIFO sooner. (And again, large reads are + * not used in practice; they are for debug/development only.) + * + * For a more conservative Host implementation (which would be + * safer for a Compact Flash interconnect): + * Set CONSERVATIVE_BMI_READ (above) to 1 + * Set HI_OPTION_BMI_CRED_LIMIT and + * reduce BMI_DATASZ_MAX to 32 or 64 + */ + if ((length > 4) && (length < 128)) { /* check against MBOX FIFO size */ + /* + * NB: cmdCredits is declared static for esoteric reasons + * having to do with protection on some OSes. + */ + static A_UINT32 cmdCredits; + A_UINT32 timeout; + + cmdCredits = 0; + timeout = BMI_COMMUNICATION_TIMEOUT; + while((!want_timeout || timeout--) && !cmdCredits) { + /* Read the counter register to get the command credits */ + address = COUNT_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 1; + /* read the counter using a 4-byte read. Since the counter is NOT auto-decrementing, + * we can read this counter multiple times using a non-incrementing address mode. + * The rationale here is to make all HIF accesses a multiple of 4 bytes */ + status = HIFReadWrite(device, address, (A_UINT8 *)&cmdCredits, sizeof(cmdCredits), + HIF_RD_SYNC_BYTE_FIX, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the command credit count register\n")); + return A_ERROR; + } + /* we did a 4-byte read to the same count register so mask off upper bytes */ + cmdCredits &= 0xFF; + } + + if (!cmdCredits) { + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Communication timeout- bmiBufferReceive no credit\n")); + return A_ERROR; + } + } +#endif + + address = mboxAddress[ENDPOINT1]; + status = HIFReadWrite(device, address, buffer, length, HIF_RD_SYNC_BYTE_INC, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the BMI data from the device\n")); + return A_ERROR; + } + + return A_OK; +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k/bmi.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/bmi.h --- linux-2.6.26/drivers/net/wireless/ath6k/bmi.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/bmi.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,115 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// BMI declarations and prototypes +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _BMI_H_ +#define _BMI_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Header files */ +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "hif.h" +#include "a_osapi.h" +#include "bmi_msg.h" + +void +BMIInit(void); + +A_STATUS +BMIDone(HIF_DEVICE *device); + +A_STATUS +BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info); + +A_STATUS +BMIReadMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length); + +A_STATUS +BMIWriteMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length); + +A_STATUS +BMIExecute(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param); + +A_STATUS +BMISetAppStart(HIF_DEVICE *device, + A_UINT32 address); + +A_STATUS +BMIReadSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param); + +A_STATUS +BMIWriteSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 param); + +A_STATUS +BMIrompatchInstall(HIF_DEVICE *device, + A_UINT32 ROM_addr, + A_UINT32 RAM_addr, + A_UINT32 nbytes, + A_UINT32 do_activate, + A_UINT32 *patch_id); + +A_STATUS +BMIrompatchUninstall(HIF_DEVICE *device, + A_UINT32 rompatch_id); + +A_STATUS +BMIrompatchActivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list); + +A_STATUS +BMIrompatchDeactivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list); + +A_STATUS +BMILZStreamStart(HIF_DEVICE *device, + A_UINT32 address); + +A_STATUS +BMILZData(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length); + +#ifdef __cplusplus +} +#endif + +#endif /* _BMI_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/bmi_internal.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/bmi_internal.h --- linux-2.6.26/drivers/net/wireless/ath6k/bmi_internal.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/bmi_internal.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,51 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef BMI_INTERNAL_H +#define BMI_INTERNAL_H + +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "a_debug.h" +#include "mbox_host_reg.h" +#include "bmi_msg.h" + +#define BMI_COMMUNICATION_TIMEOUT 100000 + +/* ------ Global Variable Declarations ------- */ +A_BOOL bmiDone; + +A_STATUS +bmiBufferSend(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length); + +A_STATUS +bmiBufferReceive(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length, + A_BOOL want_timeout); + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k/bmi_msg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/bmi_msg.h --- linux-2.6.26/drivers/net/wireless/ath6k/bmi_msg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/bmi_msg.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,235 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __BMI_MSG_H__ +#define __BMI_MSG_H__ + +/* + * Bootloader Messaging Interface (BMI) + * + * BMI is a very simple messaging interface used during initialization + * to read memory, write memory, execute code, and to define an + * application entry PC. + * + * It is used to download an application to AR6K, to provide + * patches to code that is already resident on AR6K, and generally + * to examine and modify state. The Host has an opportunity to use + * BMI only once during bootup. Once the Host issues a BMI_DONE + * command, this opportunity ends. + * + * The Host writes BMI requests to mailbox0, and reads BMI responses + * from mailbox0. BMI requests all begin with a command + * (see below for specific commands), and are followed by + * command-specific data. + * + * Flow control: + * The Host can only issue a command once the Target gives it a + * "BMI Command Credit", using AR6K Counter #4. As soon as the + * Target has completed a command, it issues another BMI Command + * Credit (so the Host can issue the next command). + * + * BMI handles all required Target-side cache flushing. + */ + + +/* Maximum data size used for BMI transfers */ +#define BMI_DATASZ_MAX 256 + +/* BMI Commands */ + +#define BMI_NO_COMMAND 0 + +#define BMI_DONE 1 + /* + * Semantics: Host is done using BMI + * Request format: + * A_UINT32 command (BMI_DONE) + * Response format: none + */ + +#define BMI_READ_MEMORY 2 + /* + * Semantics: Host reads AR6K memory + * Request format: + * A_UINT32 command (BMI_READ_MEMORY) + * A_UINT32 address + * A_UINT32 length, at most BMI_DATASZ_MAX + * Response format: + * A_UINT8 data[length] + */ + +#define BMI_WRITE_MEMORY 3 + /* + * Semantics: Host writes AR6K memory + * Request format: + * A_UINT32 command (BMI_WRITE_MEMORY) + * A_UINT32 address + * A_UINT32 length, at most BMI_DATASZ_MAX + * A_UINT8 data[length] + * Response format: none + */ + +#define BMI_EXECUTE 4 + /* + * Semantics: Causes AR6K to execute code + * Request format: + * A_UINT32 command (BMI_EXECUTE) + * A_UINT32 address + * A_UINT32 parameter + * Response format: + * A_UINT32 return value + */ + +#define BMI_SET_APP_START 5 + /* + * Semantics: Set Target application starting address + * Request format: + * A_UINT32 command (BMI_SET_APP_START) + * A_UINT32 address + * Response format: none + */ + +#define BMI_READ_SOC_REGISTER 6 + /* + * Semantics: Read a 32-bit Target SOC register. + * Request format: + * A_UINT32 command (BMI_READ_REGISTER) + * A_UINT32 address + * Response format: + * A_UINT32 value + */ + +#define BMI_WRITE_SOC_REGISTER 7 + /* + * Semantics: Write a 32-bit Target SOC register. + * Request format: + * A_UINT32 command (BMI_WRITE_REGISTER) + * A_UINT32 address + * A_UINT32 value + * + * Response format: none + */ + +#define BMI_GET_TARGET_ID 8 +#define BMI_GET_TARGET_INFO 8 + /* + * Semantics: Fetch the 4-byte Target information + * Request format: + * A_UINT32 command (BMI_GET_TARGET_ID/INFO) + * Response format1 (old firmware): + * A_UINT32 TargetVersionID + * Response format2 (newer firmware): + * A_UINT32 TARGET_VERSION_SENTINAL + * struct bmi_target_info; + */ + +struct bmi_target_info { + A_UINT32 target_info_byte_count; /* size of this structure */ + A_UINT32 target_ver; /* Target Version ID */ + A_UINT32 target_type; /* Target type */ +}; +#define TARGET_VERSION_SENTINAL 0xffffffff +#define TARGET_TYPE_AR6001 1 +#define TARGET_TYPE_AR6002 2 +#define TARGET_TYPE_AR6003 3 + + +#define BMI_ROMPATCH_INSTALL 9 + /* + * Semantics: Install a ROM Patch. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_INSTALL) + * A_UINT32 Target ROM Address + * A_UINT32 Target RAM Address + * A_UINT32 Size, in bytes + * A_UINT32 Activate? 1-->activate; + * 0-->install but do not activate + * Response format: + * A_UINT32 PatchID + */ + +#define BMI_ROMPATCH_UNINSTALL 10 + /* + * Semantics: Uninstall a previously-installed ROM Patch, + * automatically deactivating, if necessary. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_UNINSTALL) + * A_UINT32 PatchID + * + * Response format: none + */ + +#define BMI_ROMPATCH_ACTIVATE 11 + /* + * Semantics: Activate a list of previously-installed ROM Patches. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_ACTIVATE) + * A_UINT32 rompatch_count + * A_UINT32 PatchID[rompatch_count] + * + * Response format: none + */ + +#define BMI_ROMPATCH_DEACTIVATE 12 + /* + * Semantics: Deactivate a list of active ROM Patches. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_DEACTIVATE) + * A_UINT32 rompatch_count + * A_UINT32 PatchID[rompatch_count] + * + * Response format: none + */ + + +#define BMI_LZ_STREAM_START 13 + /* + * Semantics: Begin an LZ-compressed stream of input + * which is to be uncompressed by the Target to an + * output buffer at address. The output buffer must + * be sufficiently large to hold the uncompressed + * output from the compressed input stream. This BMI + * command should be followed by a series of 1 or more + * BMI_LZ_DATA commands. + * A_UINT32 command (BMI_LZ_STREAM_START) + * A_UINT32 address + * Note: Not supported on all versions of ROM firmware. + */ + +#define BMI_LZ_DATA 14 + /* + * Semantics: Host writes AR6K memory with LZ-compressed + * data which is uncompressed by the Target. This command + * must be preceded by a BMI_LZ_STREAM_START command. A series + * of BMI_LZ_DATA commands are considered part of a single + * input stream until another BMI_LZ_STREAM_START is issued. + * Request format: + * A_UINT32 command (BMI_LZ_DATA) + * A_UINT32 length (of compressed data), + * at most BMI_DATASZ_MAX + * A_UINT8 CompressedData[length] + * Response format: none + * Note: Not supported on all versions of ROM firmware. + */ + +#endif /* __BMI_MSG_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/cnxmgmt.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/cnxmgmt.h --- linux-2.6.26/drivers/net/wireless/ath6k/cnxmgmt.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/cnxmgmt.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,33 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _CNXMGMT_H_ +#define _CNXMGMT_H_ + +typedef enum { + CM_CONNECT_WITHOUT_SCAN = 0x0001, + CM_CONNECT_ASSOC_POLICY_USER = 0x0002, + CM_CONNECT_SEND_REASSOC = 0x0004, +} CM_CONNECT_TYPE; + +#endif /* _CNXMGMT_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/common_drv.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/common_drv.c --- linux-2.6.26/drivers/net/wireless/ath6k/common_drv.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/common_drv.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,663 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" + +#include "mbox_host_reg.h" +#include "apb_map.h" +#include "si_reg.h" +#include "gpio_reg.h" +#include "rtc_reg.h" +#include "vmc_reg.h" +#include "mbox_reg.h" + +#include "targaddrs.h" +#include "a_osapi.h" +#include "hif.h" +#include "htc_api.h" +#include "wmi.h" +#include "bmi.h" +#include "bmi_msg.h" +#include "common_drv.h" +#include "a_debug.h" + +#define HOST_INTEREST_ITEM_ADDRESS(target, item) \ + (((target) == TARGET_TYPE_AR6001) ? AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((target) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((target) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : 0))) + + +#define AR6001_LOCAL_COUNT_ADDRESS 0x0c014080 +#define AR6002_LOCAL_COUNT_ADDRESS 0x00018080 +#define AR6003_LOCAL_COUNT_ADDRESS 0x00018080 + +/* Compile the 4BYTE version of the window register setup routine, + * This mitigates host interconnect issues with non-4byte aligned bus requests, some + * interconnects use bus adapters that impose strict limitations. + * Since diag window access is not intended for performance critical operations, the 4byte mode should + * be satisfactory even though it generates 4X the bus activity. */ + +#ifdef USE_4BYTE_REGISTER_ACCESS + + /* set the window address register (using 4-byte register access ). */ +A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address) +{ + A_STATUS status; + A_UINT8 addrValue[4]; + A_INT32 i; + + /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written + * last to initiate the access cycle */ + + for (i = 1; i <= 3; i++) { + /* fill the buffer with the address byte value we want to hit 4 times*/ + addrValue[0] = ((A_UINT8 *)&Address)[i]; + addrValue[1] = addrValue[0]; + addrValue[2] = addrValue[0]; + addrValue[3] = addrValue[0]; + + /* hit each byte of the register address with a 4-byte write operation to the same address, + * this is a harmless operation */ + status = HIFReadWrite(hifDevice, + RegisterAddr+i, + addrValue, + 4, + HIF_WR_SYNC_BYTE_FIX, + NULL); + if (status != A_OK) { + break; + } + } + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n", + RegisterAddr, Address)); + return status; + } + + /* write the address register again, this time write the whole 4-byte value. + * The effect here is that the LSB write causes the cycle to start, the extra + * 3 byte write to bytes 1,2,3 has no effect since we are writing the same values again */ + status = HIFReadWrite(hifDevice, + RegisterAddr, + (A_UCHAR *)(&Address), + 4, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n", + RegisterAddr, Address)); + return status; + } + + return A_OK; + + + +} + + +#else + + /* set the window address register */ +A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address) +{ + A_STATUS status; + + /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written + * last to initiate the access cycle */ + status = HIFReadWrite(hifDevice, + RegisterAddr+1, /* write upper 3 bytes */ + ((A_UCHAR *)(&Address))+1, + sizeof(A_UINT32)-1, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n", + RegisterAddr, Address)); + return status; + } + + /* write the LSB of the register, this initiates the operation */ + status = HIFReadWrite(hifDevice, + RegisterAddr, + (A_UCHAR *)(&Address), + sizeof(A_UINT8), + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n", + RegisterAddr, Address)); + return status; + } + + return A_OK; +} + +#endif + +/* + * Read from the AR6000 through its diagnostic window. + * No cooperation from the Target is required for this. + */ +A_STATUS +ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data) +{ + A_STATUS status; + + /* set window register to start read cycle */ + status = ar6000_SetAddressWindowRegister(hifDevice, + WINDOW_READ_ADDR_ADDRESS, + *address); + + if (status != A_OK) { + return status; + } + + /* read the data */ + status = HIFReadWrite(hifDevice, + WINDOW_DATA_ADDRESS, + (A_UCHAR *)data, + sizeof(A_UINT32), + HIF_RD_SYNC_BYTE_INC, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from WINDOW_DATA_ADDRESS\n")); + return status; + } + + return status; +} + + +/* + * Write to the AR6000 through its diagnostic window. + * No cooperation from the Target is required for this. + */ +A_STATUS +ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data) +{ + A_STATUS status; + + /* set write data */ + status = HIFReadWrite(hifDevice, + WINDOW_DATA_ADDRESS, + (A_UCHAR *)data, + sizeof(A_UINT32), + HIF_WR_SYNC_BYTE_INC, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to WINDOW_DATA_ADDRESS\n", *data)); + return status; + } + + /* set window register, which starts the write cycle */ + return ar6000_SetAddressWindowRegister(hifDevice, + WINDOW_WRITE_ADDR_ADDRESS, + *address); + } + +A_STATUS +ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length) +{ + A_UINT32 count; + A_STATUS status = A_OK; + + for (count = 0; count < length; count += 4, address += 4) { + if ((status = ar6000_ReadRegDiag(hifDevice, &address, + (A_UINT32 *)&data[count])) != A_OK) + { + break; + } + } + + return status; +} + +A_STATUS +ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length) +{ + A_UINT32 count; + A_STATUS status = A_OK; + + for (count = 0; count < length; count += 4, address += 4) { + if ((status = ar6000_WriteRegDiag(hifDevice, &address, + (A_UINT32 *)&data[count])) != A_OK) + { + break; + } + } + + return status; +} + +#if 0 +static A_STATUS +_do_write_diag(HIF_DEVICE *hifDevice, A_UINT32 addr, A_UINT32 value) +{ + A_STATUS status; + + status = ar6000_WriteRegDiag(hifDevice, &addr, &value); + if (status != A_OK) + { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot force Target to execute ROM!\n")); + } + + return status; +} +#endif + + +/* + * Delay up to wait_msecs millisecs to allow Target to enter BMI phase, + * which is a good sign that it's alive and well. This is used after + * explicitly forcing the Target to reset. + * + * The wait_msecs time should be sufficiently long to cover any reasonable + * boot-time delay. For instance, AR6001 firmware allow one second for a + * low frequency crystal to settle before it calibrates the refclk frequency. + * + * TBD: Might want to add special handling for AR6K_OPTION_BMI_DISABLE. + */ +static A_STATUS +_delay_until_target_alive(HIF_DEVICE *hifDevice, A_INT32 wait_msecs, A_UINT32 TargetType) +{ + A_INT32 actual_wait; + A_INT32 i; + A_UINT32 address; + + actual_wait = 0; + + /* Hardcode the address of LOCAL_COUNT_ADDRESS based on the target type */ + if (TargetType == TARGET_TYPE_AR6001) { + address = AR6001_LOCAL_COUNT_ADDRESS; + } else if (TargetType == TARGET_TYPE_AR6002) { + address = AR6002_LOCAL_COUNT_ADDRESS; + } else if (TargetType == TARGET_TYPE_AR6003) { + address = AR6003_LOCAL_COUNT_ADDRESS; + } else { + A_ASSERT(0); + } + address += 0x10; + for (i=0; actual_wait < wait_msecs; i++) { + A_UINT32 data; + + A_MDELAY(100); + actual_wait += 100; + + data = 0; + if (ar6000_ReadRegDiag(hifDevice, &address, &data) != A_OK) { + return A_ERROR; + } + + if (data != 0) { + /* No need to wait longer -- we have a BMI credit */ + return A_OK; + } + } + return A_ERROR; /* timed out */ +} + +#define AR6001_RESET_CONTROL_ADDRESS 0x0C000000 +#define AR6002_RESET_CONTROL_ADDRESS 0x00004000 +#define AR6003_RESET_CONTROL_ADDRESS 0x00004000 +/* reset device */ +A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType, A_BOOL waitForCompletion) +{ + A_STATUS status = A_OK; + A_UINT32 address; + A_UINT32 data; + + do { + + // address = RESET_CONTROL_ADDRESS; + data = RESET_CONTROL_COLD_RST_MASK; + + /* Hardcode the address of RESET_CONTROL_ADDRESS based on the target type */ + if (TargetType == TARGET_TYPE_AR6001) { + address = AR6001_RESET_CONTROL_ADDRESS; + } else if (TargetType == TARGET_TYPE_AR6002) { + address = AR6002_RESET_CONTROL_ADDRESS; + } else if (TargetType == TARGET_TYPE_AR6003) { + address = AR6003_RESET_CONTROL_ADDRESS; + } else { + A_ASSERT(0); + } + + + status = ar6000_WriteRegDiag(hifDevice, &address, &data); + + if (A_FAILED(status)) { + break; + } + + if (!waitForCompletion) { + break; + } + + + /* Up to 2 second delay to allow things to settle down */ + (void)_delay_until_target_alive(hifDevice, 2000, TargetType); + + /* + * Read back the RESET CAUSE register to ensure that the cold reset + * went through. + */ + + // address = RESET_CAUSE_ADDRESS; + /* Hardcode the address of RESET_CAUSE_ADDRESS based on the target type */ + if (TargetType == TARGET_TYPE_AR6001) { + address = 0x0C0000CC; + } else if (TargetType == TARGET_TYPE_AR6002) { + address = 0x000040C0; + } else if (TargetType == TARGET_TYPE_AR6003) { + address = 0x000040C0; + } else { + A_ASSERT(0); + } + + data = 0; + status = ar6000_ReadRegDiag(hifDevice, &address, &data); + + if (A_FAILED(status)) { + break; + } + + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Reset Cause readback: 0x%X \n",data)); + data &= RESET_CAUSE_LAST_MASK; + if (data != 2) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Unable to cold reset the target \n")); + } + + } while (FALSE); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Failed to reset target \n")); + } + + return A_OK; +} + +#define REG_DUMP_COUNT_AR6001 38 /* WORDs, derived from AR600x_regdump.h */ +#define REG_DUMP_COUNT_AR6002 32 +#define REG_DUMP_COUNT_AR6003 32 +#define REGISTER_DUMP_LEN_MAX 38 +#if REG_DUMP_COUNT_AR6001 > REGISTER_DUMP_LEN_MAX +#error "REG_DUMP_COUNT_AR6001 too large" +#endif +#if REG_DUMP_COUNT_AR6002 > REGISTER_DUMP_LEN_MAX +#error "REG_DUMP_COUNT_AR6002 too large" +#endif +#if REG_DUMP_COUNT_AR6003 > REGISTER_DUMP_LEN_MAX +#error "REG_DUMP_COUNT_AR6003 too large" +#endif + + +void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType) +{ + A_UINT32 address; + A_UINT32 regDumpArea = 0; + A_STATUS status; + A_UINT32 regDumpValues[REGISTER_DUMP_LEN_MAX]; + A_UINT32 regDumpCount = 0; + A_UINT32 i; + + do { + + /* the reg dump pointer is copied to the host interest area */ + address = HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_failure_state); + address = TARG_VTOP(TargetType, address); + + if (TargetType == TARGET_TYPE_AR6001) { + /* for AR6001, this is a fixed location because the ptr is actually stuck in cache, + * this may be fixed in later firmware versions */ + address = 0x18a0; + regDumpCount = REG_DUMP_COUNT_AR6001; + } else if (TargetType == TARGET_TYPE_AR6002) { + regDumpCount = REG_DUMP_COUNT_AR6002; + } else if (TargetType == TARGET_TYPE_AR6003) { + regDumpCount = REG_DUMP_COUNT_AR6003; + } else { + A_ASSERT(0); + } + + /* read RAM location through diagnostic window */ + status = ar6000_ReadRegDiag(hifDevice, &address, ®DumpArea); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get ptr to register dump area \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Location of register dump data: 0x%X \n",regDumpArea)); + + if (regDumpArea == 0) { + /* no reg dump */ + break; + } + + regDumpArea = TARG_VTOP(TargetType, regDumpArea); + + /* fetch register dump data */ + status = ar6000_ReadDataDiag(hifDevice, + regDumpArea, + (A_UCHAR *)®DumpValues[0], + regDumpCount * (sizeof(A_UINT32))); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get register dump \n")); + break; + } + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Register Dump: \n")); + + for (i = 0; i < regDumpCount; i++) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" %d : 0x%8.8X \n",i, regDumpValues[i])); +#ifdef UNDER_CE + logPrintf(ATH_DEBUG_ERR," %d: 0x%8.8X \n",i, regDumpValues[i]); +#endif + } + + } while (FALSE); + +} + +/* set HTC/Mbox operational parameters, this can only be called when the target is in the + * BMI phase */ +A_STATUS ar6000_set_htc_params(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 MboxIsrYieldValue, + A_UINT8 HtcControlBuffers) +{ + A_STATUS status; + A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX]; + + do { + /* get the block sizes */ + status = HIFConfigureDevice(hifDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + blocksizes, sizeof(blocksizes)); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_LOG_ERR,("Failed to get block size info from HIF layer...\n")); + break; + } + /* note: we actually get the block size for mailbox 1, for SDIO the block + * size on mailbox 0 is artificially set to 1 */ + /* must be a power of 2 */ + A_ASSERT((blocksizes[1] & (blocksizes[1] - 1)) == 0); + + if (HtcControlBuffers != 0) { + /* set override for number of control buffers to use */ + blocksizes[1] |= ((A_UINT32)HtcControlBuffers) << 16; + } + + /* set the host interest area for the block size */ + status = BMIWriteMemory(hifDevice, + HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz), + (A_UCHAR *)&blocksizes[1], + 4); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for IO block size failed \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_LOG_INF,("Block Size Set: %d (target address:0x%X)\n", + blocksizes[1], HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz))); + + if (MboxIsrYieldValue != 0) { + /* set the host interest area for the mbox ISR yield limit */ + status = BMIWriteMemory(hifDevice, + HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_isr_yield_limit), + (A_UCHAR *)&MboxIsrYieldValue, + 4); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for yield limit failed \n")); + break; + } + } + + } while (FALSE); + + return status; +} + + +static A_STATUS prepare_ar6002(HIF_DEVICE *hifDevice, A_UINT32 TargetVersion) +{ + A_STATUS status = A_OK; + + /* placeholder */ + + return status; +} + +static A_STATUS prepare_ar6003(HIF_DEVICE *hifDevice, A_UINT32 TargetVersion) +{ + A_STATUS status = A_OK; + + /* placeholder */ + + return status; +} + +/* this function assumes the caller has already initialized the BMI APIs */ +A_STATUS ar6000_prepare_target(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 TargetVersion) +{ + if (TargetType == TARGET_TYPE_AR6002) { + /* do any preparations for AR6002 devices */ + return prepare_ar6002(hifDevice,TargetVersion); + } else if (TargetType == TARGET_TYPE_AR6003) { + return prepare_ar6003(hifDevice,TargetVersion); + } + + return A_OK; +} + +#if defined(CONFIG_AR6002_REV1_FORCE_HOST) +/* + * Call this function just before the call to BMIInit + * in order to force* AR6002 rev 1.x firmware to detect a Host. + * THIS IS FOR USE ONLY WITH AR6002 REV 1.x. + * TBDXXX: Remove this function when REV 1.x is desupported. + */ +A_STATUS +ar6002_REV1_reset_force_host (HIF_DEVICE *hifDevice) +{ + A_INT32 i; + struct forceROM_s { + A_UINT32 addr; + A_UINT32 data; + }; + struct forceROM_s *ForceROM; + A_INT32 szForceROM; + A_STATUS status = A_OK; + A_UINT32 address; + A_UINT32 data; + + /* Force AR6002 REV1.x to recognize Host presence. + * + * Note: Use RAM at 0x52df80..0x52dfa0 with ROM Remap entry 0 + * so that this workaround functions with AR6002.war1.sh. We + * could fold that entire workaround into this one, but it's not + * worth the effort at this point. This workaround cannot be + * merged into the other workaround because this must be done + * before BMI. + */ + + static struct forceROM_s ForceROM_NEW[] = { + {0x52df80, 0x20f31c07}, + {0x52df84, 0x92374420}, + {0x52df88, 0x1d120c03}, + {0x52df8c, 0xff8216f0}, + {0x52df90, 0xf01d120c}, + {0x52df94, 0x81004136}, + {0x52df98, 0xbc9100bd}, + {0x52df9c, 0x00bba100}, + + {0x00008000|MC_TCAM_TARGET_ADDRESS, 0x0012dfe0}, /* Use remap entry 0 */ + {0x00008000|MC_TCAM_COMPARE_ADDRESS, 0x000e2380}, + {0x00008000|MC_TCAM_MASK_ADDRESS, 0x00000000}, + {0x00008000|MC_TCAM_VALID_ADDRESS, 0x00000001}, + + {0x00018000|(LOCAL_COUNT_ADDRESS+0x10), 0}, /* clear BMI credit counter */ + + {0x00004000|AR6002_RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK}, + }; + + address = 0x004ed4b0; /* REV1 target software ID is stored here */ + status = ar6000_ReadRegDiag(hifDevice, &address, &data); + if (A_FAILED(status) || (data != AR6002_VERSION_REV1)) { + return A_ERROR; /* Not AR6002 REV1 */ + } + + ForceROM = ForceROM_NEW; + szForceROM = sizeof(ForceROM_NEW)/sizeof(*ForceROM); + + ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Force Target to recognize Host....\n")); + for (i = 0; i < szForceROM; i++) + { + if (ar6000_WriteRegDiag(hifDevice, + &ForceROM[i].addr, + &ForceROM[i].data) != A_OK) + { + ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Cannot force Target to recognize Host!\n")); + return A_ERROR; + } + } + + A_MDELAY(1000); + + return A_OK; +} +#endif /* CONFIG_AR6002_REV1_FORCE_HOST */ + + diff -urN linux-2.6.26/drivers/net/wireless/ath6k/common_drv.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/common_drv.h --- linux-2.6.26/drivers/net/wireless/ath6k/common_drv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/common_drv.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,79 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef COMMON_DRV_H_ +#define COMMON_DRV_H_ + +#include "hif.h" +#include "htc_packet.h" + +/* structure that is the state information for the default credit distribution callback + * drivers should instantiate (zero-init as well) this structure in their driver instance + * and pass it as a context to the HTC credit distribution functions */ +typedef struct _COMMON_CREDIT_STATE_INFO { + int TotalAvailableCredits; /* total credits in the system at startup */ + int CurrentFreeCredits; /* credits available in the pool that have not been + given out to endpoints */ + HTC_ENDPOINT_CREDIT_DIST *pLowestPriEpDist; /* pointer to the lowest priority endpoint dist struct */ +} COMMON_CREDIT_STATE_INFO; + + +/* HTC TX packet tagging definitions */ +#define AR6K_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED +#define AR6K_DATA_PKT_TAG (AR6K_CONTROL_PKT_TAG + 1) + +#define AR6002_VERSION_REV1 0x20000086 +#define AR6002_VERSION_REV2 0x20000188 + +#ifdef __cplusplus +extern "C" { +#endif + +/* OS-independent APIs */ +A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo); + +A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, A_UCHAR *data, A_UINT32 length); + +A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType, A_BOOL waitForCompletion); + +void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType); + +A_STATUS ar6000_reset_device_skipflash(HIF_DEVICE *hifDevice); + +A_STATUS ar6000_set_htc_params(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 MboxIsrYieldValue, + A_UINT8 HtcControlBuffers); + +A_STATUS ar6000_prepare_target(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 TargetVersion); + +#ifdef __cplusplus +} +#endif + +#endif /*COMMON_DRV_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/config_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/config_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k/config_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/config_linux.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _CONFIG_LINUX_H_ +#define _CONFIG_LINUX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Host-side GPIO support is optional. + * If run-time access to GPIO pins is not required, then + * this should be changed to #undef. + */ +#define CONFIG_HOST_GPIO_SUPPORT + +/* + * Host side Test Command support + */ +#define CONFIG_HOST_TCMD_SUPPORT + +#define USE_4BYTE_REGISTER_ACCESS + +/* Host-side support for Target-side profiling */ +#undef CONFIG_TARGET_PROFILE_SUPPORT + +#ifdef __cplusplus +} +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k/credit_dist.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/credit_dist.c --- linux-2.6.26/drivers/net/wireless/ath6k/credit_dist.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/credit_dist.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,373 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "a_debug.h" +#include "htc_api.h" +#include "common_drv.h" + +/********* CREDIT DISTRIBUTION FUNCTIONS ******************************************/ + +#define NO_VO_SERVICE 1 /* currently WMI only uses 3 data streams, so we leave VO service inactive */ + +#ifdef NO_VO_SERVICE +#define DATA_SVCS_USED 3 +#else +#define DATA_SVCS_USED 4 +#endif + +static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList); + +static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList); + +/* reduce an ep's credits back to a set limit */ +static INLINE void ReduceCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEpDist, + int Limit) +{ + int credits; + + /* set the new limit */ + pEpDist->TxCreditsAssigned = Limit; + + if (pEpDist->TxCredits <= Limit) { + return; + } + + /* figure out how much to take away */ + credits = pEpDist->TxCredits - Limit; + /* take them away */ + pEpDist->TxCredits -= credits; + pCredInfo->CurrentFreeCredits += credits; +} + +/* give an endpoint some credits from the free credit pool */ +#define GiveCredits(pCredInfo,pEpDist,credits) \ +{ \ + (pEpDist)->TxCredits += (credits); \ + (pEpDist)->TxCreditsAssigned += (credits); \ + (pCredInfo)->CurrentFreeCredits -= (credits); \ +} + + +/* default credit init callback. + * This function is called in the context of HTCStart() to setup initial (application-specific) + * credit distributions */ +static void ar6000_credit_init(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + int TotalCredits) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + int count; + COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context; + + pCredInfo->CurrentFreeCredits = TotalCredits; + pCredInfo->TotalAvailableCredits = TotalCredits; + + pCurEpDist = pEPList; + + /* run through the list and initialize */ + while (pCurEpDist != NULL) { + + /* set minimums for each endpoint */ + pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg; + + if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) { + /* give control service some credits */ + GiveCredits(pCredInfo,pCurEpDist,pCurEpDist->TxCreditsMin); + /* control service is always marked active, it never goes inactive EVER */ + SET_EP_ACTIVE(pCurEpDist); + } else if (pCurEpDist->ServiceID == WMI_DATA_BK_SVC) { + /* this is the lowest priority data endpoint, save this off for easy access */ + pCredInfo->pLowestPriEpDist = pCurEpDist; + } + + /* Streams have to be created (explicit | implicit)for all kinds + * of traffic. BE endpoints are also inactive in the beginning. + * When BE traffic starts it creates implicit streams that + * redistributes credits. + */ + + /* note, all other endpoints have minimums set but are initially given NO credits. + * Credits will be distributed as traffic activity demands */ + pCurEpDist = pCurEpDist->pNext; + } + + if (pCredInfo->CurrentFreeCredits <= 0) { + AR_DEBUG_PRINTF(ATH_LOG_INF, ("Not enough credits (%d) to do credit distributions \n", TotalCredits)); + A_ASSERT(FALSE); + return; + } + + /* reset list */ + pCurEpDist = pEPList; + /* now run through the list and set max operating credit limits for everyone */ + while (pCurEpDist != NULL) { + if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) { + /* control service max is just 1 max message */ + pCurEpDist->TxCreditsNorm = pCurEpDist->TxCreditsPerMaxMsg; + } else { + /* for the remaining data endpoints, we assume that each TxCreditsPerMaxMsg are + * the same. + * We use a simple calculation here, we take the remaining credits and + * determine how many max messages this can cover and then set each endpoint's + * normal value equal to 3/4 this amount. + * */ + count = (pCredInfo->CurrentFreeCredits/pCurEpDist->TxCreditsPerMaxMsg) * pCurEpDist->TxCreditsPerMaxMsg; + count = (count * 3) >> 2; + count = max(count,pCurEpDist->TxCreditsPerMaxMsg); + /* set normal */ + pCurEpDist->TxCreditsNorm = count; + + } + pCurEpDist = pCurEpDist->pNext; + } + +} + + +/* default credit distribution callback + * This callback is invoked whenever endpoints require credit distributions. + * A lock is held while this function is invoked, this function shall NOT block. + * The pEPDistList is a list of distribution structures in prioritized order as + * defined by the call to the HTCSetCreditDistribution() api. + * + */ +static void ar6000_credit_distribute(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList, + HTC_CREDIT_DIST_REASON Reason) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context; + + switch (Reason) { + case HTC_CREDIT_DIST_SEND_COMPLETE : + pCurEpDist = pEPDistList; + /* we are given the start of the endpoint distribution list. + * There may be one or more endpoints to service. + * Run through the list and distribute credits */ + while (pCurEpDist != NULL) { + + if (pCurEpDist->TxCreditsToDist > 0) { + /* return the credits back to the endpoint */ + pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist; + /* always zero out when we are done */ + pCurEpDist->TxCreditsToDist = 0; + + if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsAssigned) { + /* reduce to the assigned limit, previous credit reductions + * could have caused the limit to change */ + ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsAssigned); + } + + if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsNorm) { + /* oversubscribed endpoints need to reduce back to normal */ + ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsNorm); + } + + if (!IS_EP_ACTIVE(pCurEpDist)) { + /* endpoint is inactive, now check for messages waiting for credits */ + if (pCurEpDist->TxQueueDepth == 0) { + /* EP is inactive and there are no pending messages, + * reduce credits back to zero to recover credits */ + ReduceCredits(pCredInfo, pCurEpDist, 0); + } + } + } + + pCurEpDist = pCurEpDist->pNext; + } + + break; + + case HTC_CREDIT_DIST_ACTIVITY_CHANGE : + RedistributeCredits(pCredInfo,pEPDistList); + break; + case HTC_CREDIT_DIST_SEEK_CREDITS : + SeekCredits(pCredInfo,pEPDistList); + break; + case HTC_DUMP_CREDIT_STATE : + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Credit Distribution, total : %d, free : %d\n", + pCredInfo->TotalAvailableCredits, pCredInfo->CurrentFreeCredits)); + break; + default: + break; + + } + + /* sanity checks done after each distribution action */ + A_ASSERT(pCredInfo->CurrentFreeCredits <= pCredInfo->TotalAvailableCredits); + A_ASSERT(pCredInfo->CurrentFreeCredits >= 0); + +} + +/* redistribute credits based on activity change */ +static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist = pEPDistList; + + /* walk through the list and remove credits from inactive endpoints */ + while (pCurEpDist != NULL) { + + if (pCurEpDist->ServiceID != WMI_CONTROL_SVC) { + if (!IS_EP_ACTIVE(pCurEpDist)) { + if (pCurEpDist->TxQueueDepth == 0) { + /* EP is inactive and there are no pending messages, reduce credits back to zero */ + ReduceCredits(pCredInfo, pCurEpDist, 0); + } else { + /* we cannot zero the credits assigned to this EP, but to keep + * the credits available for these leftover packets, reduce to + * a minimum */ + ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsMin); + } + } + } + + /* NOTE in the active case, we do not need to do anything further, + * when an EP goes active and needs credits, HTC will call into + * our distribution function using a reason code of HTC_CREDIT_DIST_SEEK_CREDITS */ + + pCurEpDist = pCurEpDist->pNext; + } + +} + +/* HTC has an endpoint that needs credits, pEPDist is the endpoint in question */ +static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDist) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + int credits = 0; + int need; + + do { + + if (pEPDist->ServiceID == WMI_CONTROL_SVC) { + /* we never oversubscribe on the control service, this is not + * a high performance path and the target never holds onto control + * credits for too long */ + break; + } + + if (pEPDist->ServiceID == WMI_DATA_VI_SVC) { + if (pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm) { + /* limit VI service from oversubscribing */ + break; + } + } + + if (pEPDist->ServiceID == WMI_DATA_VO_SVC) { + if (pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm) { + /* limit VO service from oversubscribing */ + break; + } + } + + /* for all other services, we follow a simple algorithm of + * 1. checking the free pool for credits + * 2. checking lower priority endpoints for credits to take */ + + /* give what we can */ + credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek); + + if (credits >= pEPDist->TxCreditsSeek) { + /* we found some to fullfill the seek request */ + break; + } + + /* we don't have enough in the free pool, try taking away from lower priority services + * + * The rule for taking away credits: + * 1. Only take from lower priority endpoints + * 2. Only take what is allocated above the minimum (never starve an endpoint completely) + * 3. Only take what you need. + * + * */ + + /* starting at the lowest priority */ + pCurEpDist = pCredInfo->pLowestPriEpDist; + + /* work backwards until we hit the endpoint again */ + while (pCurEpDist != pEPDist) { + /* calculate how many we need so far */ + need = pEPDist->TxCreditsSeek - pCredInfo->CurrentFreeCredits; + + if ((pCurEpDist->TxCreditsAssigned - need) >= pCurEpDist->TxCreditsMin) { + /* the current one has been allocated more than it's minimum and it + * has enough credits assigned above it's minimum to fullfill our need + * try to take away just enough to fullfill our need */ + ReduceCredits(pCredInfo, + pCurEpDist, + pCurEpDist->TxCreditsAssigned - need); + + if (pCredInfo->CurrentFreeCredits >= pEPDist->TxCreditsSeek) { + /* we have enough */ + break; + } + } + + pCurEpDist = pCurEpDist->pPrev; + } + + /* return what we can get */ + credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek); + + } while (FALSE); + + /* did we find some credits? */ + if (credits) { + /* give what we can */ + GiveCredits(pCredInfo, pEPDist, credits); + } + +} + +/* initialize and setup credit distribution */ +A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo) +{ + HTC_SERVICE_ID servicepriority[5]; + + A_MEMZERO(pCredInfo,sizeof(COMMON_CREDIT_STATE_INFO)); + + servicepriority[0] = WMI_CONTROL_SVC; /* highest */ + servicepriority[1] = WMI_DATA_VO_SVC; + servicepriority[2] = WMI_DATA_VI_SVC; + servicepriority[3] = WMI_DATA_BE_SVC; + servicepriority[4] = WMI_DATA_BK_SVC; /* lowest */ + + /* set callbacks and priority list */ + HTCSetCreditDistribution(HTCHandle, + pCredInfo, + ar6000_credit_distribute, + ar6000_credit_init, + servicepriority, + 5); + + return A_OK; +} + diff -urN linux-2.6.26/drivers/net/wireless/ath6k/dbglog.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/dbglog.h --- linux-2.6.26/drivers/net/wireless/ath6k/dbglog.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/dbglog.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,126 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _DBGLOG_H_ +#define _DBGLOG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define DBGLOG_TIMESTAMP_OFFSET 0 +#define DBGLOG_TIMESTAMP_MASK 0x0000FFFF /* Bit 0-15. Contains bit + 8-23 of the LF0 timer */ +#define DBGLOG_DBGID_OFFSET 16 +#define DBGLOG_DBGID_MASK 0x03FF0000 /* Bit 16-25 */ +#define DBGLOG_DBGID_NUM_MAX 256 /* Upper limit is width of mask */ + +#define DBGLOG_MODULEID_OFFSET 26 +#define DBGLOG_MODULEID_MASK 0x3C000000 /* Bit 26-29 */ +#define DBGLOG_MODULEID_NUM_MAX 16 /* Upper limit is width of mask */ + +/* + * Please ensure that the definition of any new module intrduced is captured + * between the DBGLOG_MODULEID_START and DBGLOG_MODULEID_END defines. The + * structure is required for the parser to correctly pick up the values for + * different modules. + */ +#define DBGLOG_MODULEID_START +#define DBGLOG_MODULEID_INF 0 +#define DBGLOG_MODULEID_WMI 1 +#define DBGLOG_MODULEID_CSERV 2 +#define DBGLOG_MODULEID_PM 3 +#define DBGLOG_MODULEID_TXRX_MGMTBUF 4 +#define DBGLOG_MODULEID_TXRX_TXBUF 5 +#define DBGLOG_MODULEID_TXRX_RXBUF 6 +#define DBGLOG_MODULEID_WOW 7 +#define DBGLOG_MODULEID_WHAL 8 +#define DBGLOG_MODULEID_DC 9 +#define DBGLOG_MODULEID_CO 10 +#define DBGLOG_MODULEID_RO 11 +#define DBGLOG_MODULEID_CM 12 +#define DBGLOG_MODULEID_PY 13 +#define DBGLOG_MODULEID_TMR 14 +#define DBGLOG_MODULEID_BTCOEX 15 +#define DBGLOG_MODULEID_END + +#define DBGLOG_NUM_ARGS_OFFSET 30 +#define DBGLOG_NUM_ARGS_MASK 0xC0000000 /* Bit 30-31 */ +#define DBGLOG_NUM_ARGS_MAX 2 /* Upper limit is width of mask */ + +#define DBGLOG_MODULE_LOG_ENABLE_OFFSET 0 +#define DBGLOG_MODULE_LOG_ENABLE_MASK 0x0000FFFF + +#define DBGLOG_REPORTING_ENABLED_OFFSET 16 +#define DBGLOG_REPORTING_ENABLED_MASK 0x00010000 + +#define DBGLOG_TIMESTAMP_RESOLUTION_OFFSET 17 +#define DBGLOG_TIMESTAMP_RESOLUTION_MASK 0x000E0000 + +#define DBGLOG_REPORT_SIZE_OFFSET 20 +#define DBGLOG_REPORT_SIZE_MASK 0x3FF00000 + +#define DBGLOG_LOG_BUFFER_SIZE 1500 +#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90 + +struct dbglog_buf_s { + struct dbglog_buf_s *next; + A_INT8 *buffer; + A_UINT32 bufsize; + A_UINT32 length; + A_UINT32 count; + A_UINT32 free; +}; + +struct dbglog_hdr_s { + struct dbglog_buf_s *dbuf; + A_UINT32 dropped; +}; + +struct dbglog_config_s { + A_UINT32 cfgvalid; /* Mask with valid config bits */ + union { + /* TODO: Take care of endianness */ + struct { + A_UINT32 mmask:16; /* Mask of modules with logging on */ + A_UINT32 rep:1; /* Reporting enabled or not */ + A_UINT32 tsr:3; /* Time stamp resolution. Def: 1 ms */ + A_UINT32 size:10; /* Report size in number of messages */ + A_UINT32 reserved:2; + } dbglog_config; + + A_UINT32 value; + } u; +}; + +#define cfgmmask u.dbglog_config.mmask +#define cfgrep u.dbglog_config.rep +#define cfgtsr u.dbglog_config.tsr +#define cfgsize u.dbglog_config.size +#define cfgvalue u.value + +#ifdef __cplusplus +} +#endif + +#endif /* _DBGLOG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/dbglog_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/dbglog_api.h --- linux-2.6.26/drivers/net/wireless/ath6k/dbglog_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/dbglog_api.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains host side debug primitives. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _DBGLOG_API_H_ +#define _DBGLOG_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbglog.h" + +#define DBGLOG_HOST_LOG_BUFFER_SIZE DBGLOG_LOG_BUFFER_SIZE + +#define DBGLOG_GET_DBGID(arg) \ + ((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET) + +#define DBGLOG_GET_MODULEID(arg) \ + ((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET) + +#define DBGLOG_GET_NUMARGS(arg) \ + ((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET) + +#define DBGLOG_GET_TIMESTAMP(arg) \ + ((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET) + +#ifdef __cplusplus +} +#endif + +#endif /* _DBGLOG_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/dbglog_id.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/dbglog_id.h --- linux-2.6.26/drivers/net/wireless/ath6k/dbglog_id.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/dbglog_id.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,491 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _DBGLOG_ID_H_ +#define _DBGLOG_ID_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * The nomenclature for the debug identifiers is MODULE_DESCRIPTION. + * Please ensure that the definition of any new debugid introduced is captured + * between the _DBGID_DEFINITION_START and + * _DBGID_DEFINITION_END defines. The structure is required for the + * parser to correctly pick up the values for different debug identifiers. + */ + +/* INF debug identifier definitions */ +#define INF_DBGID_DEFINITION_START +#define INF_ASSERTION_FAILED 1 +#define INF_TARGET_ID 2 +#define INF_DBGID_DEFINITION_END + +/* WMI debug identifier definitions */ +#define WMI_DBGID_DEFINITION_START +#define WMI_CMD_RX_XTND_PKT_TOO_SHORT 1 +#define WMI_EXTENDED_CMD_NOT_HANDLED 2 +#define WMI_CMD_RX_PKT_TOO_SHORT 3 +#define WMI_CALLING_WMI_EXTENSION_FN 4 +#define WMI_CMD_NOT_HANDLED 5 +#define WMI_IN_SYNC 6 +#define WMI_TARGET_WMI_SYNC_CMD 7 +#define WMI_SET_SNR_THRESHOLD_PARAMS 8 +#define WMI_SET_RSSI_THRESHOLD_PARAMS 9 +#define WMI_SET_LQ_TRESHOLD_PARAMS 10 +#define WMI_TARGET_CREATE_PSTREAM_CMD 11 +#define WMI_WI_DTM_INUSE 12 +#define WMI_TARGET_DELETE_PSTREAM_CMD 13 +#define WMI_TARGET_IMPLICIT_DELETE_PSTREAM_CMD 14 +#define WMI_TARGET_GET_BIT_RATE_CMD 15 +#define WMI_GET_RATE_MASK_CMD_FIX_RATE_MASK_IS 16 +#define WMI_TARGET_GET_AVAILABLE_CHANNELS_CMD 17 +#define WMI_TARGET_GET_TX_PWR_CMD 18 +#define WMI_FREE_EVBUF_WMIBUF 19 +#define WMI_FREE_EVBUF_DATABUF 20 +#define WMI_FREE_EVBUF_BADFLAG 21 +#define WMI_HTC_RX_ERROR_DATA_PACKET 22 +#define WMI_HTC_RX_SYNC_PAUSING_FOR_MBOX 23 +#define WMI_INCORRECT_WMI_DATA_HDR_DROPPING_PKT 24 +#define WMI_SENDING_READY_EVENT 25 +#define WMI_SETPOWER_MDOE_TO_MAXPERF 26 +#define WMI_SETPOWER_MDOE_TO_REC 27 +#define WMI_BSSINFO_EVENT_FROM 28 +#define WMI_TARGET_GET_STATS_CMD 29 +#define WMI_SENDING_SCAN_COMPLETE_EVENT 30 +#define WMI_SENDING_RSSI_INDB_THRESHOLD_EVENT 31 +#define WMI_SENDING_RSSI_INDBM_THRESHOLD_EVENT 32 +#define WMI_SENDING_LINK_QUALITY_THRESHOLD_EVENT 33 +#define WMI_SENDING_ERROR_REPORT_EVENT 34 +#define WMI_SENDING_CAC_EVENT 35 +#define WMI_TARGET_GET_ROAM_TABLE_CMD 36 +#define WMI_TARGET_GET_ROAM_DATA_CMD 37 +#define WMI_SENDING_GPIO_INTR_EVENT 38 +#define WMI_SENDING_GPIO_ACK_EVENT 39 +#define WMI_SENDING_GPIO_DATA_EVENT 40 +#define WMI_CMD_RX 41 +#define WMI_CMD_RX_XTND 42 +#define WMI_EVENT_SEND 43 +#define WMI_EVENT_SEND_XTND 44 +#define WMI_CMD_PARAMS_DUMP_START 45 +#define WMI_CMD_PARAMS_DUMP_END 46 +#define WMI_CMD_PARAMS 47 +#define WMI_DBGID_DEFINITION_END + +/* CSERV debug identifier definitions */ +#define CSERV_DBGID_DEFINITION_START +#define CSERV_BEGIN_SCAN1 1 +#define CSERV_BEGIN_SCAN2 2 +#define CSERV_END_SCAN1 3 +#define CSERV_END_SCAN2 4 +#define CSERV_CHAN_SCAN_START 5 +#define CSERV_CHAN_SCAN_STOP 6 +#define CSERV_CHANNEL_OPPPORTUNITY 7 +#define CSERV_NC_TIMEOUT 8 +#define CSERV_BACK_HOME 10 +#define CSERV_CHMGR_CH_CALLBACK1 11 +#define CSERV_CHMGR_CH_CALLBACK2 12 +#define CSERV_CHMGR_CH_CALLBACK3 13 +#define CSERV_SET_SCAN_PARAMS1 14 +#define CSERV_SET_SCAN_PARAMS2 15 +#define CSERV_SET_SCAN_PARAMS3 16 +#define CSERV_SET_SCAN_PARAMS4 17 +#define CSERV_ABORT_SCAN 18 +#define CSERV_NEWSTATE 19 +#define CSERV_MINCHMGR_OP_END 20 +#define CSERV_CHMGR_OP_END 21 +#define CSERV_DISCONNECT_TIMEOUT 22 +#define CSERV_ROAM_TIMEOUT 23 +#define CSERV_FORCE_SCAN1 24 +#define CSERV_FORCE_SCAN2 25 +#define CSERV_FORCE_SCAN3 26 +#define CSERV_UTIL_TIMEOUT 27 +#define CSERV_RSSIPOLLER 28 +#define CSERV_RETRY_CONNECT_TIMEOUT 29 +#define CSERV_RSSIINDBMPOLLER 30 +#define CSERV_BGSCAN_ENABLE 31 +#define CSERV_BGSCAN_DISABLE 32 +#define CSERV_WLAN_START_SCAN_CMD1 33 +#define CSERV_WLAN_START_SCAN_CMD2 34 +#define CSERV_WLAN_START_SCAN_CMD3 35 +#define CSERV_START_SCAN_CMD 36 +#define CSERV_START_FORCE_SCAN 37 +#define CSERV_NEXT_CHAN 38 +#define CSERV_SET_REGCODE 39 +#define CSERV_START_ADHOC 40 +#define CSERV_ADHOC_AT_HOME 41 +#define CSERV_OPT_AT_HOME 42 +#define CSERV_WLAN_CONNECT_CMD 43 +#define CSERV_WLAN_RECONNECT_CMD 44 +#define CSERV_WLAN_DISCONNECT_CMD 45 +#define CSERV_BSS_CHANGE_CHANNEL 46 +#define CSERV_BEACON_RX 47 +#define CSERV_KEEPALIVE_CHECK 48 +#define CSERV_RC_BEGIN_SCAN 49 +#define CSERV_RC_SCAN_START 50 +#define CSERV_RC_SCAN_STOP 51 +#define CSERV_RC_NEXT 52 +#define CSERV_RC_SCAN_END 53 +#define CSERV_PROBE_CALLBACK 54 +#define CSERV_ROAM1 55 +#define CSERV_ROAM2 56 +#define CSERV_ROAM3 57 +#define CSERV_CONNECT_EVENT 58 +#define CSERV_DISCONNECT_EVENT 59 +#define CSERV_BMISS_HANDLER1 60 +#define CSERV_BMISS_HANDLER2 61 +#define CSERV_BMISS_HANDLER3 62 +#define CSERV_LOWRSSI_HANDLER 63 +#define CSERV_WLAN_SET_PMKID_CMD 64 +#define CSERV_RECONNECT_REQUEST 65 +#define CSERV_KEYSPLUMBED_EVENT 66 +#define CSERV_NEW_REG 67 +#define CSERV_SET_RSSI_THOLD 68 +#define CSERV_RSSITHRESHOLDCHECK 69 +#define CSERV_RSSIINDBMTHRESHOLDCHECK 70 +#define CSERV_WLAN_SET_OPT_CMD1 71 +#define CSERV_WLAN_SET_OPT_CMD2 72 +#define CSERV_WLAN_SET_OPT_CMD3 73 +#define CSERV_WLAN_SET_OPT_CMD4 74 +#define CSERV_SCAN_CONNECT_STOP 75 +#define CSERV_BMISS_HANDLER4 76 +#define CSERV_INITIALIZE_TIMER 77 +#define CSERV_ARM_TIMER 78 +#define CSERV_DISARM_TIMER 79 +#define CSERV_UNINITIALIZE_TIMER 80 +#define CSERV_DISCONNECT_EVENT2 81 +#define CSERV_SCAN_CONNECT_START 82 +#define CSERV_BSSINFO_MEMORY_ALLOC_FAILED 83 +#define CSERV_SET_SCAN_PARAMS5 84 +#define CSERV_DBGID_DEFINITION_END + +/* TXRX debug identifier definitions */ +#define TXRX_TXBUF_DBGID_DEFINITION_START +#define TXRX_TXBUF_ALLOCATE_BUF 1 +#define TXRX_TXBUF_QUEUE_BUF_TO_MBOX 2 +#define TXRX_TXBUF_QUEUE_BUF_TO_TXQ 3 +#define TXRX_TXBUF_TXQ_DEPTH 4 +#define TXRX_TXBUF_IBSS_QUEUE_TO_SFQ 5 +#define TXRX_TXBUF_IBSS_QUEUE_TO_TXQ_FRM_SFQ 6 +#define TXRX_TXBUF_INITIALIZE_TIMER 7 +#define TXRX_TXBUF_ARM_TIMER 8 +#define TXRX_TXBUF_DISARM_TIMER 9 +#define TXRX_TXBUF_UNINITIALIZE_TIMER 10 +#define TXRX_TXBUF_DBGID_DEFINITION_END + +#define TXRX_RXBUF_DBGID_DEFINITION_START +#define TXRX_RXBUF_ALLOCATE_BUF 1 +#define TXRX_RXBUF_QUEUE_TO_HOST 2 +#define TXRX_RXBUF_QUEUE_TO_WLAN 3 +#define TXRX_RXBUF_ZERO_LEN_BUF 4 +#define TXRX_RXBUF_QUEUE_TO_HOST_LASTBUF_IN_RXCHAIN 5 +#define TXRX_RXBUF_LASTBUF_IN_RXCHAIN_ZEROBUF 6 +#define TXRX_RXBUF_QUEUE_EMPTY_QUEUE_TO_WLAN 7 +#define TXRX_RXBUF_SEND_TO_RECV_MGMT 8 +#define TXRX_RXBUF_SEND_TO_IEEE_LAYER 9 +#define TXRX_RXBUF_DBGID_DEFINITION_END + +#define TXRX_MGMTBUF_DBGID_DEFINITION_START +#define TXRX_MGMTBUF_ALLOCATE_BUF 1 +#define TXRX_MGMTBUF_ALLOCATE_SM_BUF 2 +#define TXRX_MGMTBUF_ALLOCATE_RMBUF 3 +#define TXRX_MGMTBUF_GET_BUF 4 +#define TXRX_MGMTBUF_GET_SM_BUF 5 +#define TXRX_MGMTBUF_QUEUE_BUF_TO_TXQ 6 +#define TXRX_MGMTBUF_REAPED_BUF 7 +#define TXRX_MGMTBUF_REAPED_SM_BUF 8 +#define TXRX_MGMTBUF_WAIT_FOR_TXQ_DRAIN 9 +#define TXRX_MGMTBUF_WAIT_FOR_TXQ_SFQ_DRAIN 10 +#define TXRX_MGMTBUF_ENQUEUE_INTO_DATA_SFQ 11 +#define TXRX_MGMTBUF_DEQUEUE_FROM_DATA_SFQ 12 +#define TXRX_MGMTBUF_PAUSE_DATA_TXQ 13 +#define TXRX_MGMTBUF_RESUME_DATA_TXQ 14 +#define TXRX_MGMTBUF_WAIT_FORTXQ_DRAIN_TIMEOUT 15 +#define TXRX_MGMTBUF_DRAINQ 16 +#define TXRX_MGMTBUF_INDICATE_Q_DRAINED 17 +#define TXRX_MGMTBUF_ENQUEUE_INTO_HW_SFQ 18 +#define TXRX_MGMTBUF_DEQUEUE_FROM_HW_SFQ 19 +#define TXRX_MGMTBUF_PAUSE_HW_TXQ 20 +#define TXRX_MGMTBUF_RESUME_HW_TXQ 21 +#define TXRX_MGMTBUF_DBGID_DEFINITION_END + +/* PM (Power Module) debug identifier definitions */ +#define PM_DBGID_DEFINITION_START +#define PM_INIT 1 +#define PM_ENABLE 2 +#define PM_SET_STATE 3 +#define PM_SET_POWERMODE 4 +#define PM_CONN_NOTIFY 5 +#define PM_REF_COUNT_NEGATIVE 6 +#define PM_APSD_ENABLE 7 +#define PM_UPDATE_APSD_STATE 8 +#define PM_CHAN_OP_REQ 9 +#define PM_SET_MY_BEACON_POLICY 10 +#define PM_SET_ALL_BEACON_POLICY 11 +#define PM_SET_PM_PARAMS1 12 +#define PM_SET_PM_PARAMS2 13 +#define PM_ADHOC_SET_PM_CAPS_FAIL 14 +#define PM_ADHOC_UNKNOWN_IBSS_ATTRIB_ID 15 +#define PM_DBGID_DEFINITION_END + +/* Wake on Wireless debug identifier definitions */ +#define WOW_DBGID_DEFINITION_START +#define WOW_INIT 1 +#define WOW_GET_CONFIG_DSET 2 +#define WOW_NO_CONFIG_DSET 3 +#define WOW_INVALID_CONFIG_DSET 4 +#define WOW_USE_DEFAULT_CONFIG 5 +#define WOW_SETUP_GPIO 6 +#define WOW_INIT_DONE 7 +#define WOW_SET_GPIO_PIN 8 +#define WOW_CLEAR_GPIO_PIN 9 +#define WOW_SET_WOW_MODE_CMD 10 +#define WOW_SET_HOST_MODE_CMD 11 +#define WOW_ADD_WOW_PATTERN_CMD 12 +#define WOW_NEW_WOW_PATTERN_AT_INDEX 13 +#define WOW_DEL_WOW_PATTERN_CMD 14 +#define WOW_LIST_CONTAINS_PATTERNS 15 +#define WOW_GET_WOW_LIST_CMD 16 +#define WOW_INVALID_FILTER_ID 17 +#define WOW_INVALID_FILTER_LISTID 18 +#define WOW_NO_VALID_FILTER_AT_ID 19 +#define WOW_NO_VALID_LIST_AT_ID 20 +#define WOW_NUM_PATTERNS_EXCEEDED 21 +#define WOW_NUM_LISTS_EXCEEDED 22 +#define WOW_GET_WOW_STATS 23 +#define WOW_CLEAR_WOW_STATS 24 +#define WOW_WAKEUP_HOST 25 +#define WOW_EVENT_WAKEUP_HOST 26 +#define WOW_EVENT_DISCARD 27 +#define WOW_PATTERN_MATCH 28 +#define WOW_PATTERN_NOT_MATCH 29 +#define WOW_PATTERN_NOT_MATCH_OFFSET 30 +#define WOW_DISABLED_HOST_ASLEEP 31 +#define WOW_ENABLED_HOST_ASLEEP_NO_PATTERNS 32 +#define WOW_ENABLED_HOST_ASLEEP_NO_MATCH_FOUND 33 +#define WOW_DBGID_DEFINITION_END + +/* WHAL debug identifier definitions */ +#define WHAL_DBGID_DEFINITION_START +#define WHAL_ERROR_ANI_CONTROL 1 +#define WHAL_ERROR_CHIP_TEST1 2 +#define WHAL_ERROR_CHIP_TEST2 3 +#define WHAL_ERROR_EEPROM_CHECKSUM 4 +#define WHAL_ERROR_EEPROM_MACADDR 5 +#define WHAL_ERROR_INTERRUPT_HIU 6 +#define WHAL_ERROR_KEYCACHE_RESET 7 +#define WHAL_ERROR_KEYCACHE_SET 8 +#define WHAL_ERROR_KEYCACHE_TYPE 9 +#define WHAL_ERROR_KEYCACHE_TKIPENTRY 10 +#define WHAL_ERROR_KEYCACHE_WEPLENGTH 11 +#define WHAL_ERROR_PHY_INVALID_CHANNEL 12 +#define WHAL_ERROR_POWER_AWAKE 13 +#define WHAL_ERROR_POWER_SET 14 +#define WHAL_ERROR_RECV_STOPDMA 15 +#define WHAL_ERROR_RECV_STOPPCU 16 +#define WHAL_ERROR_RESET_CHANNF1 17 +#define WHAL_ERROR_RESET_CHANNF2 18 +#define WHAL_ERROR_RESET_PM 19 +#define WHAL_ERROR_RESET_OFFSETCAL 20 +#define WHAL_ERROR_RESET_RFGRANT 21 +#define WHAL_ERROR_RESET_RXFRAME 22 +#define WHAL_ERROR_RESET_STOPDMA 23 +#define WHAL_ERROR_RESET_RECOVER 24 +#define WHAL_ERROR_XMIT_COMPUTE 25 +#define WHAL_ERROR_XMIT_NOQUEUE 26 +#define WHAL_ERROR_XMIT_ACTIVEQUEUE 27 +#define WHAL_ERROR_XMIT_BADTYPE 28 +#define WHAL_DBGID_DEFINITION_END + +/* DC debug identifier definitions */ +#define DC_DBGID_DEFINITION_START +#define DC_SCAN_CHAN_START 1 +#define DC_SCAN_CHAN_FINISH 2 +#define DC_BEACON_RECEIVE7 3 +#define DC_SSID_PROBE_CB 4 +#define DC_SEND_NEXT_SSID_PROBE 5 +#define DC_START_SEARCH 6 +#define DC_CANCEL_SEARCH_CB 7 +#define DC_STOP_SEARCH 8 +#define DC_END_SEARCH 9 +#define DC_MIN_CHDWELL_TIMEOUT 10 +#define DC_START_SEARCH_CANCELED 11 +#define DC_SET_POWER_MODE 12 +#define DC_INIT 13 +#define DC_SEARCH_OPPORTUNITY 14 +#define DC_RECEIVED_ANY_BEACON 15 +#define DC_RECEIVED_MY_BEACON 16 +#define DC_PROFILE_IS_ADHOC_BUT_BSS_IS_INFRA 17 +#define DC_PS_ENABLED_BUT_ATHEROS_IE_ABSENT 18 +#define DC_BSS_ADHOC_CHANNEL_NOT_ALLOWED 19 +#define DC_SET_BEACON_UPDATE 20 +#define DC_BEACON_UPDATE_COMPLETE 21 +#define DC_END_SEARCH_BEACON_UPDATE_COMP_CB 22 +#define DC_BSSINFO_EVENT_DROPPED 23 +#define DC_DBGID_DEFINITION_END + +/* CO debug identifier definitions */ +#define CO_DBGID_DEFINITION_START +#define CO_INIT 1 +#define CO_ACQUIRE_LOCK 2 +#define CO_START_OP1 3 +#define CO_START_OP2 4 +#define CO_DRAIN_TX_COMPLETE_CB 5 +#define CO_CHANGE_CHANNEL_CB 6 +#define CO_RETURN_TO_HOME_CHANNEL 7 +#define CO_FINISH_OP_TIMEOUT 8 +#define CO_OP_END 9 +#define CO_CANCEL_OP 10 +#define CO_CHANGE_CHANNEL 11 +#define CO_RELEASE_LOCK 12 +#define CO_CHANGE_STATE 13 +#define CO_DBGID_DEFINITION_END + +/* RO debug identifier definitions */ +#define RO_DBGID_DEFINITION_START +#define RO_REFRESH_ROAM_TABLE 1 +#define RO_UPDATE_ROAM_CANDIDATE 2 +#define RO_UPDATE_ROAM_CANDIDATE_CB 3 +#define RO_UPDATE_ROAM_CANDIDATE_FINISH 4 +#define RO_REFRESH_ROAM_TABLE_DONE 5 +#define RO_PERIODIC_SEARCH_CB 6 +#define RO_PERIODIC_SEARCH_TIMEOUT 7 +#define RO_INIT 8 +#define RO_BMISS_STATE1 9 +#define RO_BMISS_STATE2 10 +#define RO_SET_PERIODIC_SEARCH_ENABLE 11 +#define RO_SET_PERIODIC_SEARCH_DISABLE 12 +#define RO_ENABLE_SQ_THRESHOLD 13 +#define RO_DISABLE_SQ_THRESHOLD 14 +#define RO_ADD_BSS_TO_ROAM_TABLE 15 +#define RO_SET_PERIODIC_SEARCH_MODE 16 +#define RO_CONFIGURE_SQ_THRESHOLD1 17 +#define RO_CONFIGURE_SQ_THRESHOLD2 18 +#define RO_CONFIGURE_SQ_PARAMS 19 +#define RO_LOW_SIGNAL_QUALITY_EVENT 20 +#define RO_HIGH_SIGNAL_QUALITY_EVENT 21 +#define RO_REMOVE_BSS_FROM_ROAM_TABLE 22 +#define RO_UPDATE_CONNECTION_STATE_METRIC 23 +#define RO_DBGID_DEFINITION_END + +/* CM debug identifier definitions */ +#define CM_DBGID_DEFINITION_START +#define CM_INITIATE_HANDOFF 1 +#define CM_INITIATE_HANDOFF_CB 2 +#define CM_CONNECT_EVENT 3 +#define CM_DISCONNECT_EVENT 4 +#define CM_INIT 5 +#define CM_HANDOFF_SOURCE 6 +#define CM_SET_HANDOFF_TRIGGERS 7 +#define CM_CONNECT_REQUEST 8 +#define CM_CONNECT_REQUEST_CB 9 +#define CM_CONTINUE_SCAN_CB 10 +#define CM_DBGID_DEFINITION_END + +/* PY debug identifier definitions */ +#define PY_DBGID_DEFINITION_START +#define PY_DEVICE_DISCOVER 1 +#define PY_DEVICE_CONNECT 2 +#define PY_DEVICE_DISCONNECT 3 +#define PY_CONNECT_NOTIFY 4 +#define PY_DATA_WINDOW_NOTIFY 5 +#define PY_CANCEL_OP 6 +#define PY_DISCOVERY_WINDOW_NOTIFY 7 +#define PY_PROCESS_PYXIS_MSGTYPE 8 +#define PY_SEND_PYXIS_MSGTYPE 9 +#define PY_DBGID_DEFINITION_END + +/* TMR debug identifier definitions */ +#define TMR_DBGID_DEFINITION_START +#define TMR_HANG_DETECTED 1 +#define TMR_WDT_TRIGGERED 2 +#define TMR_WDT_RESET 3 +#define TMR_HANDLER_ENTRY 4 +#define TMR_HANDLER_EXIT 5 +#define TMR_SAVED_START 6 +#define TMR_SAVED_END 7 +#define TMR_DBGID_DEFINITION_END + +/* BTCOEX debug identifier definitions */ +#define BTCOEX_DBGID_DEFINITION_START +#define BTCOEX_STATUS_CMD 1 +#define BTCOEX_PARAMS_CMD 2 +#define BTCOEX_ANT_CONFIG 3 +#define BTCOEX_COLOCATED_BT_DEVICE 4 +#define BTCOEX_CLOSE_RANGE_SCO_ON 5 +#define BTCOEX_CLOSE_RANGE_SCO_OFF 6 +#define BTCOEX_CLOSE_RANGE_A2DP_ON 7 +#define BTCOEX_CLOSE_RANGE_A2DP_OFF 8 +#define BTCOEX_A2DP_PROTECT_ON 9 +#define BTCOEX_A2DP_PROTECT_OFF 10 +#define BTCOEX_SCO_PROTECT_ON 11 +#define BTCOEX_SCO_PROTECT_OFF 12 +#define BTCOEX_CLOSE_RANGE_DETECTOR_START 13 +#define BTCOEX_CLOSE_RANGE_DETECTOR_STOP 14 +#define BTCOEX_CLOSE_RANGE_TOGGLE 15 +#define BTCOEX_CLOSE_RANGE_TOGGLE_RSSI_LRCNT 16 +#define BTCOEX_CLOSE_RANGE_RSSI_THRESH 17 +#define BTCOEX_CLOSE_RANGE_LOW_RATE_THRESH 18 +#define BTCOEX_WEIGHTS 19 +#define BTCOEX_A2DP_DWNLINK 20 +#define BTCOEX_BMISS_PROTECT 21 +#define BTCOEX_BMISS_PROTECT_OFF 22 +#define BTCOEX_DATA_RES_TIMEOUT 23 +#define BTCOEX_DATA_ACTIVITY_TIMEOUT_HANDLER 24 +#define BTCOEX_BCN_INTRVL_TIMEOUT 25 +#define BTCOEX_A2DP_TRIGGER 26 +#define BTCOEX_OBS_REG 27 +#define BTCOEX_PHY_REG 28 +#define BTCOEX_RESET_RADIO 29 +#define BTCOEX_BMISS_NOTIFY 30 +#define BTCOEX_PSPOLL_CALLBACK 31 +#define BTCOEX_WLAN_STATE 32 +#define BTCOEX_CONNECT_START 33 +#define BTCOEX_SCAN_START 34 +#define BTCOEX_SCAN_END 35 +#define BTCOEX_RESET_WHAL 36 +#define BTCOEX_RX_FRAME_COUNTER 37 +#define BTCOEX_RX_FRAME_CLR_CNTR 38 +#define BTCOEX_RX_DP 39 +#define BTCOEX_RX_ABRT 40 +#define BTCOEX_RX_FRAME_SET_CNT 41 +#define BTCOEX_AGCCCA_REG 42 +#define BTCOEX_RSSI_REG 43 +#define BTCOEX_A2DP_PARAM_VAL 44 +#define BTCOEX_MODE 45 +#define BTCOEX_SEND_PSPOLL 46 +#define BTCOEX_SET_UPLINK_RATE 47 +#define BTCOEX_SLEEP_STATUS 49 +#define BTCOEX_RECONNECT_REQ 49 +#define BTCOEX_RECEIVE_NOTIFY 50 +#define BTCOEX_PACKET_COUNT 51 +#define BTCOEX_A2DP_START_WLAN_TRIG 52 +#define BTCOEX_A2DP_HANDLER_TRIG 53 +#define BTCOEX_DBGID_DEFINITION_END + +#ifdef __cplusplus +} +#endif + +#endif /* _DBGLOG_ID_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/debug_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/debug_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k/debug_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/debug_linux.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2004-2006 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _DEBUG_LINUX_H_ +#define _DEBUG_LINUX_H_ + +#define DBG_DEFAULTS (DBG_ERROR|DBG_WARNING) + +extern A_UINT32 g_dbg_flags; + +#define DBGFMT "%s() : " +#define DBGARG __func__ +#define DBGFN A_PRINTF + +/* ------- Debug related stuff ------- */ +enum { + ATH_DEBUG_SEND = 0x0001, + ATH_DEBUG_RECV = 0x0002, + ATH_DEBUG_SYNC = 0x0004, + ATH_DEBUG_DUMP = 0x0008, + ATH_DEBUG_IRQ = 0x0010, + ATH_DEBUG_TRC = 0x0020, + ATH_DEBUG_WARN = 0x0040, + ATH_DEBUG_ERR = 0x0080, + ATH_LOG_INF = 0x0100, + ATH_DEBUG_BMI = 0x0110, + ATH_DEBUG_WMI = 0x0120, + ATH_DEBUG_HIF = 0x0140, + ATH_DEBUG_HTC = 0x0180, + ATH_DEBUG_WLAN = 0x1000, + ATH_LOG_ERR = 0x1010, + ATH_DEBUG_ANY = 0xFFFF, +}; + +#ifdef DEBUG +#define A_DPRINTF(f, a) \ + if(g_dbg_flags & (f)) \ + { \ + DBGFN a ; \ + } + + +// TODO FIX usage of A_PRINTF! +#define AR_DEBUG_LVL_CHECK(lvl) (debughtc & (lvl)) +#define AR_DEBUG_PRINTBUF(buffer, length, desc) do { \ + if (debughtc & ATH_DEBUG_DUMP) { \ + DebugDumpBytes(buffer, length,desc); \ + } \ +} while(0) +#define PRINTX_ARG(arg...) arg +#define AR_DEBUG_PRINTF(flags, args) do { \ + if (debughtc & (flags)) { \ + A_PRINTF(KERN_ALERT PRINTX_ARG args); \ + } \ +} while (0) +#define AR_DEBUG_ASSERT(test) do { \ + if (!(test)) { \ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test)); \ + } \ +} while(0) +extern int debughtc; +#else +#define AR_DEBUG_PRINTF(flags, args) +#define AR_DEBUG_PRINTBUF(buffer, length, desc) +#define AR_DEBUG_ASSERT(test) +#define AR_DEBUG_LVL_CHECK(lvl) 0 +#define A_DPRINTF(f, a) +#endif + +#endif /* _DEBUG_LINUX_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/discovery.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/discovery.h --- linux-2.6.26/drivers/net/wireless/ath6k/discovery.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/discovery.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,74 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _DISCOVERY_H_ +#define _DISCOVERY_H_ + +/* + * DC_SCAN_PRIORITY is an 8-bit bitmap of the scan priority of a channel + */ +typedef enum { + DEFAULT_SCPRI = 0x01, + POPULAR_SCPRI = 0x02, + SSIDS_SCPRI = 0x04, + PROF_SCPRI = 0x08, +} DC_SCAN_PRIORITY; + +/* The following search type construct can be used to manipulate the behavior of the search module based on different bits set */ +typedef enum { + SCAN_RESET = 0, + SCAN_ALL = (DEFAULT_SCPRI | POPULAR_SCPRI | \ + SSIDS_SCPRI | PROF_SCPRI), + + SCAN_POPULAR = (POPULAR_SCPRI | SSIDS_SCPRI | PROF_SCPRI), + SCAN_SSIDS = (SSIDS_SCPRI | PROF_SCPRI), + SCAN_PROF_MASK = (PROF_SCPRI), + SCAN_MULTI_CHANNEL = 0x000100, + SCAN_DETERMINISTIC = 0x000200, + SCAN_PROFILE_MATCH_TERMINATED = 0x000400, + SCAN_HOME_CHANNEL_SKIP = 0x000800, + SCAN_CHANNEL_LIST_CONTINUE = 0x001000, + SCAN_CURRENT_SSID_SKIP = 0x002000, + SCAN_ACTIVE_PROBE_DISABLE = 0x004000, + SCAN_CHANNEL_HINT_ONLY = 0x008000, + SCAN_ACTIVE_CHANNELS_ONLY = 0x010000, + SCAN_PYXIS_DISCOVERY = 0x020000, + SCAN_PERIODIC = 0x040200, + SCAN_FIXED_DURATION = 0x080000, +} DC_SCAN_TYPE; + +typedef enum { + BSS_REPORTING_DEFAULT = 0x0, + EXCLUDE_NON_SCAN_RESULTS = 0x1, /* Exclude results outside of scan */ +} DC_BSS_REPORTING_POLICY; + +typedef enum { + DC_IGNORE_WPAx_GROUP_CIPHER = 0x01, + DC_PROFILE_MATCH_DONE = 0x02, + DC_IGNORE_AAC_BEACON = 0x04, + DC_CSA_FOLLOW_BSS = 0x08, +} DC_PROFILE_FILTER; + +#define DEFAULT_DC_PROFILE_FILTER (DC_CSA_FOLLOW_BSS) + +#endif /* _DISCOVERY_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/dl_list.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/dl_list.h --- linux-2.6.26/drivers/net/wireless/ath6k/dl_list.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/dl_list.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,119 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Double-link list definitions (adapted from Atheros SDIO stack) +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef __DL_LIST_H___ +#define __DL_LIST_H___ + + +#define A_CONTAINING_STRUCT(address, struct_type, field_name)\ + ((struct_type *)((A_UINT32)(address) - (A_UINT32)(&((struct_type *)0)->field_name))) + +/* list functions */ +/* pointers for the list */ +typedef struct _DL_LIST { + struct _DL_LIST *pPrev; + struct _DL_LIST *pNext; +}DL_LIST, *PDL_LIST; +/* + * DL_LIST_INIT , initialize doubly linked list +*/ +#define DL_LIST_INIT(pList)\ + {(pList)->pPrev = pList; (pList)->pNext = pList;} + +#define DL_LIST_IS_EMPTY(pList) (((pList)->pPrev == (pList)) && ((pList)->pNext == (pList))) +#define DL_LIST_GET_ITEM_AT_HEAD(pList) (pList)->pNext +#define DL_LIST_GET_ITEM_AT_TAIL(pList) (pList)->pPrev +/* + * ITERATE_OVER_LIST pStart is the list, pTemp is a temp list member + * NOT: do not use this function if the items in the list are deleted inside the + * iteration loop +*/ +#define ITERATE_OVER_LIST(pStart, pTemp) \ + for((pTemp) =(pStart)->pNext; pTemp != (pStart); (pTemp) = (pTemp)->pNext) + + +/* safe iterate macro that allows the item to be removed from the list + * the iteration continues to the next item in the list + */ +#define ITERATE_OVER_LIST_ALLOW_REMOVE(pStart,pItem,st,offset) \ +{ \ + PDL_LIST pTemp; \ + pTemp = (pStart)->pNext; \ + while (pTemp != (pStart)) { \ + (pItem) = A_CONTAINING_STRUCT(pTemp,st,offset); \ + pTemp = pTemp->pNext; \ + +#define ITERATE_END }} + +/* + * DL_ListInsertTail - insert pAdd to the end of the list +*/ +static INLINE PDL_LIST DL_ListInsertTail(PDL_LIST pList, PDL_LIST pAdd) { + /* insert at tail */ + pAdd->pPrev = pList->pPrev; + pAdd->pNext = pList; + pList->pPrev->pNext = pAdd; + pList->pPrev = pAdd; + return pAdd; +} + +/* + * DL_ListInsertHead - insert pAdd into the head of the list +*/ +static INLINE PDL_LIST DL_ListInsertHead(PDL_LIST pList, PDL_LIST pAdd) { + /* insert at head */ + pAdd->pPrev = pList; + pAdd->pNext = pList->pNext; + pList->pNext->pPrev = pAdd; + pList->pNext = pAdd; + return pAdd; +} + +#define DL_ListAdd(pList,pItem) DL_ListInsertHead((pList),(pItem)) +/* + * DL_ListRemove - remove pDel from list +*/ +static INLINE PDL_LIST DL_ListRemove(PDL_LIST pDel) { + pDel->pNext->pPrev = pDel->pPrev; + pDel->pPrev->pNext = pDel->pNext; + /* point back to itself just to be safe, incase remove is called again */ + pDel->pNext = pDel; + pDel->pPrev = pDel; + return pDel; +} + +/* + * DL_ListRemoveItemFromHead - get a list item from the head +*/ +static INLINE PDL_LIST DL_ListRemoveItemFromHead(PDL_LIST pList) { + PDL_LIST pItem = NULL; + if (pList->pNext != pList) { + pItem = pList->pNext; + /* remove the first item from head */ + DL_ListRemove(pItem); + } + return pItem; +} + +#endif /* __DL_LIST_H___ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/dset_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/dset_api.h --- linux-2.6.26/drivers/net/wireless/ath6k/dset_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/dset_api.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,65 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Host-side DataSet API. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _DSET_API_H_ +#define _DSET_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* + * Host-side DataSet support is optional, and is not + * currently required for correct operation. To disable + * Host-side DataSet support, set this to 0. + */ +#ifndef CONFIG_HOST_DSET_SUPPORT +#define CONFIG_HOST_DSET_SUPPORT 1 +#endif + +/* Called to send a DataSet Open Reply back to the Target. */ +A_STATUS wmi_dset_open_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT32 access_cookie, + A_UINT32 size, + A_UINT32 version, + A_UINT32 targ_handle, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); + +/* Called to send a DataSet Data Reply back to the Target. */ +A_STATUS wmi_dset_data_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT8 *host_buf, + A_UINT32 length, + A_UINT32 targ_buf, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* _DSET_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/dset_internal.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/dset_internal.h --- linux-2.6.26/drivers/net/wireless/ath6k/dset_internal.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/dset_internal.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,55 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + + +#ifndef __DSET_INTERNAL_H__ +#define __DSET_INTERNAL_H__ + +/* + * Internal dset definitions, common for DataSet layer. + */ + +#define DSET_TYPE_STANDARD 0 +#define DSET_TYPE_BPATCHED 1 +#define DSET_TYPE_COMPRESSED 2 + +/* Dataset descriptor */ + +typedef struct dset_descriptor_s { + struct dset_descriptor_s *next; /* List link. NULL only at the last + descriptor */ + A_UINT16 id; /* Dset ID */ + A_UINT16 size; /* Dset size. */ + void *DataPtr; /* Pointer to raw data for standard + DataSet or pointer to original + dset_descriptor for patched + DataSet */ + A_UINT32 data_type; /* DSET_TYPE_*, above */ + + void *AuxPtr; /* Additional data that might + needed for data_type. For + example, pointer to patch + Dataset descriptor for BPatch. */ +} dset_descriptor_t; + +#endif /* __DSET_INTERNAL_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/dsetid.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/dsetid.h --- linux-2.6.26/drivers/net/wireless/ath6k/dsetid.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/dsetid.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,126 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + + +#ifndef __DSETID_H__ +#define __DSETID_H__ + +/* Well-known DataSet IDs */ +#define DSETID_UNUSED 0x00000000 +#define DSETID_BOARD_DATA 0x00000001 /* Cal and board data */ +#define DSETID_REGDB 0x00000002 /* Regulatory Database */ +#define DSETID_POWER_CONTROL 0x00000003 /* TX Pwr Lim & Ant Gain */ +#define DSETID_USER_CONFIG 0x00000004 /* User Configuration */ + +#define DSETID_ANALOG_CONTROL_DATA_START 0x00000005 +#define DSETID_ANALOG_CONTROL_DATA_END 0x00000025 +/* + * Get DSETID for various reference clock speeds. + * For each speed there are three DataSets that correspond + * to the three columns of bank6 data (addr, 11a, 11b/g). + * This macro returns the dsetid of the first of those + * three DataSets. + */ +#define ANALOG_CONTROL_DATA_DSETID(refclk) \ + (DSETID_ANALOG_CONTROL_DATA_START + 3*refclk) + +/* + * There are TWO STARTUP_PATCH DataSets. + * DSETID_STARTUP_PATCH is historical, and was applied before BMI on + * earlier systems. On AR6002, it is applied after BMI, just like + * DSETID_STARTUP_PATCH2. + */ +#define DSETID_STARTUP_PATCH 0x00000026 +#define DSETID_GPIO_CONFIG_PATCH 0x00000027 +#define DSETID_WLANREGS 0x00000028 /* override wlan regs */ +#define DSETID_STARTUP_PATCH2 0x00000029 + +#define DSETID_WOW_CONFIG 0x00000090 /* WoW Configuration */ + +/* Add WHAL_INI_DATA_ID to DSETID_INI_DATA for a specific WHAL INI table. */ +#define DSETID_INI_DATA 0x00000100 +/* Reserved for WHAL INI Tables: 0x100..0x11f */ +#define DSETID_INI_DATA_END 0x0000011f + +#define DSETID_VENDOR_START 0x00010000 /* Vendor-defined DataSets */ + +#define DSETID_INDEX_END 0xfffffffe /* Reserved to indicate the + end of a memory-based + DataSet Index */ +#define DSETID_INDEX_FREE 0xffffffff /* An unused index entry */ + +/* + * PATCH DataSet format: + * A list of patches, terminated by a patch with + * address=PATCH_END. + * + * This allows for patches to be stored in flash. + */ +struct patch_s { + A_UINT32 *address; + A_UINT32 data; +}; + +/* + * Skip some patches. Can be used to erase a single patch in a + * patch DataSet without having to re-write the DataSet. May + * also be used to embed information for use by subsequent + * patch code. The "data" in a PATCH_SKIP tells how many + * bytes of length "patch_s" to skip. + */ +#define PATCH_SKIP ((A_UINT32 *)0x00000000) + +/* + * Execute code at the address specified by "data". + * The address of the patch structure is passed as + * the one parameter. + */ +#define PATCH_CODE_ABS ((A_UINT32 *)0x00000001) + +/* + * Same as PATCH_CODE_ABS, but treat "data" as an + * offset from the start of the patch word. + */ +#define PATCH_CODE_REL ((A_UINT32 *)0x00000002) + +/* Mark the end of this patch DataSet. */ +#define PATCH_END ((A_UINT32 *)0xffffffff) + +/* + * A DataSet which contains a Binary Patch to some other DataSet + * uses the original dsetid with the DSETID_BPATCH_FLAG bit set. + * Such a BPatch DataSet consists of BPatch metadata followed by + * the bdiff bytes. BPatch metadata consists of a single 32-bit + * word that contains the size of the BPatched final image. + * + * To create a suitable bdiff DataSet, use bdiff in host/tools/bdiff + * to create "diffs": + * bdiff -q -O -nooldmd5 -nonewmd5 -d ORIGfile NEWfile diffs + * Then add BPatch metadata to the start of "diffs". + * + * NB: There are some implementation-induced restrictions + * on which DataSets can be BPatched. + */ +#define DSETID_BPATCH_FLAG 0x80000000 + +#endif /* __DSETID_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/eeprom.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/eeprom.c --- linux-2.6.26/drivers/net/wireless/ath6k/eeprom.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/eeprom.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,586 @@ +/* + * Copyright (c) 2006 Atheros Communications, Inc. + * All rights reserved. + * + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#include "ar6000_drv.h" +#include "htc.h" +#include + +#include "AR6002/hw2.0/hw/apb_map.h" +#include "AR6002/hw2.0/hw/gpio_reg.h" +#include "AR6002/hw2.0/hw/rtc_reg.h" +#include "AR6002/hw2.0/hw/si_reg.h" + +// +// defines +// + +#define MAX_FILENAME 1023 +#define EEPROM_WAIT_LIMIT 16 + +#define HOST_INTEREST_ITEM_ADDRESS(item) \ + (AR6002_HOST_INTEREST_ITEM_ADDRESS(item)) + +#define EEPROM_SZ 768 + +/* soft mac */ +#define ATH_MAC_LEN 6 +#define ATH_SOFT_MAC_TMP_BUF_LEN 64 +unsigned char mac_addr[ATH_MAC_LEN]; +unsigned char soft_mac_tmp_buf[ATH_SOFT_MAC_TMP_BUF_LEN]; +char *p_mac = NULL; +/* soft mac */ + +// +// static variables +// + +static A_UCHAR eeprom_data[EEPROM_SZ]; +static A_UINT32 sys_sleep_reg; +static HIF_DEVICE *p_bmi_device; + +// +// Functions +// + +/* soft mac */ +static int +wmic_ether_aton(const char *orig, A_UINT8 *eth) +{ + const char *bufp; + int i; + + i = 0; + for(bufp = orig; *bufp != '\0'; ++bufp) { + unsigned int val; + unsigned char c = *bufp++; + if (c >= '0' && c <= '9') val = c - '0'; + else if (c >= 'a' && c <= 'f') val = c - 'a' + 10; + else if (c >= 'A' && c <= 'F') val = c - 'A' + 10; + else { + printk("%s: MAC value is invalid\n", __FUNCTION__); + break; + } + + val <<= 4; + c = *bufp++; + if (c >= '0' && c <= '9') val |= c - '0'; + else if (c >= 'a' && c <= 'f') val |= c - 'a' + 10; + else if (c >= 'A' && c <= 'F') val |= c - 'A' + 10; + else { + printk("%s: MAC value is invalid\n", __FUNCTION__); + break; + } + + eth[i] = (unsigned char) (val & 0377); + if(++i == ATH_MAC_LEN) { + /* That's it. Any trailing junk? */ + if (*bufp != '\0') { + return 0; + } + return 1; + } + if (*bufp != ':') + break; + } + return 0; +} + +static void +update_mac(unsigned char* eeprom, int size, unsigned char* macaddr) +{ + int i; + A_UINT16* ptr = (A_UINT16*)(eeprom+4); + A_UINT16 checksum = 0; + + memcpy(eeprom+10,macaddr,6); + + *ptr = 0; + ptr = (A_UINT16*)eeprom; + + for (i=0; i>7)); + + BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval); + + regval = SI_CS_START_SET(1) | + SI_CS_RX_CNT_SET(8) | + SI_CS_TX_CNT_SET(3); + BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval); +} + +/* + * Tell the Target to start a 4-byte write to EEPROM, + * writing values from Target TX_DATA registers. + */ +static void +request_4byte_write(int offset, A_UINT32 data) +{ + A_UINT32 regval; + + printk("%s: request_4byte_write (0x%x) to offset 0x%x\n", __FUNCTION__, data, offset); + + /* SI_TX_DATA0 = write data to offset */ + regval = ((data & 0xffff) <<16) | + ((offset & 0xff)<<8) | + (0xa0 | ((offset & 0xff00)>>7)); + BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval); + + regval = data >> 16; + BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA1_OFFSET, regval); + + regval = SI_CS_START_SET(1) | + SI_CS_RX_CNT_SET(0) | + SI_CS_TX_CNT_SET(6); + BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval); +} + +/* + * Check whether or not an EEPROM request that was started + * earlier has completed yet. + */ +static A_BOOL +request_in_progress(void) +{ + A_UINT32 regval; + + /* Wait for DONE_INT in SI_CS */ + BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, ®val); + +// printk("%s: request in progress SI_CS=0x%x\n", __FUNCTION__, regval); + if (regval & SI_CS_DONE_ERR_MASK) { + printk("%s: EEPROM signaled ERROR (0x%x)\n", __FUNCTION__, regval); + } + + return (!(regval & SI_CS_DONE_INT_MASK)); +} + +/* + * try to detect the type of EEPROM,16bit address or 8bit address + */ + +static void eeprom_type_detect(void) +{ + A_UINT32 regval; + A_UINT8 i = 0; + + request_8byte_read(0x100); + /* Wait for DONE_INT in SI_CS */ + do{ + BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, ®val); + if (regval & SI_CS_DONE_ERR_MASK) { + printk("%s: ERROR : address type was wrongly set\n", __FUNCTION__); + break; + } + if (i++ == EEPROM_WAIT_LIMIT) { + printk("%s: EEPROM not responding\n", __FUNCTION__); + } + } while(!(regval & SI_CS_DONE_INT_MASK)); +} + +/* + * Extract the results of a completed EEPROM Read request + * and return them to the caller. + */ +inline void +read_8byte_results(A_UINT32 *data) +{ + /* Read SI_RX_DATA0 and SI_RX_DATA1 */ + BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA0_OFFSET, &data[0]); + BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA1_OFFSET, &data[1]); +} + + +/* + * Wait for a previously started command to complete. + * Timeout if the command is takes "too long". + */ +static void +wait_for_eeprom_completion(void) +{ + int i=0; + + while (request_in_progress()) { + if (i++ == EEPROM_WAIT_LIMIT) { + printk("%s: EEPROM not responding\n", __FUNCTION__); + } + } +} + +/* + * High-level function which starts an 8-byte read, + * waits for it to complete, and returns the result. + */ +static void +fetch_8bytes(int offset, A_UINT32 *data) +{ + request_8byte_read(offset); + wait_for_eeprom_completion(); + read_8byte_results(data); + + /* Clear any pending intr */ + BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, SI_CS_DONE_INT_MASK); +} + +/* + * High-level function which starts a 4-byte write, + * and waits for it to complete. + */ +inline void +commit_4bytes(int offset, A_UINT32 data) +{ + request_4byte_write(offset, data); + wait_for_eeprom_completion(); +} +/* ATHENV */ +#ifdef ANDROID_ENV +void eeprom_ar6000_transfer(HIF_DEVICE *device, char *fake_file, char *p_mac) +{ + A_UINT32 first_word; + A_UINT32 board_data_addr; + int i; + + printk("%s: Enter\n", __FUNCTION__); + + enable_SI(device); + eeprom_type_detect(); + + if (fake_file) { + /* + * Transfer from file to Target RAM. + * Fetch source data from file. + */ + mm_segment_t oldfs; + struct file *filp; + struct inode *inode = NULL; + int length; + + /* open file */ + oldfs = get_fs(); + set_fs(KERNEL_DS); + filp = filp_open(fake_file, O_RDONLY, S_IRUSR); + + if (IS_ERR(filp)) { + printk("%s: file %s filp_open error\n", __FUNCTION__, fake_file); + set_fs(oldfs); + return; + } + + if (!filp->f_op) { + printk("%s: File Operation Method Error\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + inode = filp->f_path.dentry->d_inode; +#else + inode = flip->dentry->d_inode; +#endif + + if (!inode) { + printk("%s: Get inode from filp failed\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos); + + /* file's size */ + length = i_size_read(inode->i_mapping->host); + printk("%s: length=%d\n", __FUNCTION__, length); + if (length != EEPROM_SZ) { + printk("%s: The file's size is not as expected\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + /* read data */ + if (filp->f_op->read(filp, eeprom_data, length, &filp->f_pos) != length) { + printk("%s: file read error\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + /* read data out successfully */ + filp_close(filp, NULL); + set_fs(oldfs); + } else { + /* + * Read from EEPROM to file OR transfer from EEPROM to Target RAM. + * Fetch EEPROM_SZ Bytes of Board Data, 8 bytes at a time. + */ + + fetch_8bytes(0, (A_UINT32 *)(&eeprom_data[0])); + + /* Check the first word of EEPROM for validity */ + first_word = *((A_UINT32 *)eeprom_data); + + if ((first_word == 0) || (first_word == 0xffffffff)) { + printk("Did not find EEPROM with valid Board Data.\n"); + } + + for (i=8; if_op) { + printk("%s: File Operation Method Error\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + inode = filp->f_path.dentry->d_inode; +#else + inode = flip->dentry->d_inode; +#endif + if (!inode) { + printk("%s: Get inode from filp failed\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos); + + /* file's size */ + length = i_size_read(inode->i_mapping->host); + printk("%s: length=%d\n", __FUNCTION__, length); + if (length > ATH_SOFT_MAC_TMP_BUF_LEN) { + printk("%s: MAC file's size is not as expected\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + /* read data */ + if (filp->f_op->read(filp, soft_mac_tmp_buf, length, &filp->f_pos) != length) { + printk("%s: file read error\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + +#if 0 + /* the data we just read */ + printk("%s: mac address from the file:\n", __FUNCTION__); + for (i = 0; i < length; i++) + printk("[%c(0x%x)],", soft_mac_tmp_buf[i], soft_mac_tmp_buf[i]); + printk("\n"); +#endif + + /* read data out successfully */ + filp_close(filp, NULL); + set_fs(oldfs); + + /* convert mac address */ + if (!wmic_ether_aton(soft_mac_tmp_buf, mac_addr)) { + printk("%s: convert mac value fail\n", __FUNCTION__); + return; + } + +#if 0 + /* the converted mac address */ + printk("%s: the converted mac value\n", __FUNCTION__); + for (i = 0; i < ATH_MAC_LEN; i++) + printk("[0x%x],", mac_addr[i]); + printk("\n"); +#endif + } + /* soft mac */ + + /* Determine where in Target RAM to write Board Data */ + BMI_read_mem( HOST_INTEREST_ITEM_ADDRESS(hi_board_data), &board_data_addr); + if (board_data_addr == 0) { + printk("hi_board_data is zero\n"); + } + + /* soft mac */ +#if 1 + /* Update MAC address in RAM */ + if (p_mac) { + update_mac(eeprom_data, EEPROM_SZ, mac_addr); + } +#endif +#if 0 + /* mac address in eeprom array */ + printk("%s: mac values in eeprom array\n", __FUNCTION__); + for (i = 10; i < 10 + 6; i++) + printk("[0x%x],", eeprom_data[i]); + printk("\n"); +#endif + /* soft mac */ + + /* Write EEPROM data to Target RAM */ + BMI_write_mem(board_data_addr, ((A_UINT8 *)eeprom_data), EEPROM_SZ); + + /* Record the fact that Board Data IS initialized */ + { + A_UINT32 one = 1; + BMI_write_mem(HOST_INTEREST_ITEM_ADDRESS(hi_board_data_initialized), + (A_UINT8 *)&one, sizeof(A_UINT32)); + } + + disable_SI(); +} +#endif +/* ATHENV */ + diff -urN linux-2.6.26/drivers/net/wireless/ath6k/engine.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/engine.c --- linux-2.6.26/drivers/net/wireless/ath6k/engine.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/engine.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,278 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ +#include "engine.h" + +#define ACC regs[0] + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +static unsigned int regs[16]; +static int offset; +static unsigned char *cp; + +int ar6k_reg_preload( int reg, unsigned int value ) +{ + if( (reg < 0) || (reg > 16) ) + return(-1); /* Illegal register */ + + regs[ reg ] = value; + return(0); +} + +static int getoffset( void ) +{ + int i = 0; + + cp++; + offset++; + + i |= (*cp & 0xFF); cp++; offset++; + i |= (*cp & 0xFF) << 8; cp++; offset++; + i |= (*cp & 0xFF) << 16; cp++; offset++; + i |= (*cp & 0xFF) << 24; cp++; offset++; + + return(i); +} + +static int getarg( void ) +{ + int i; + + if( *cp & 0x0F ) + { + i = regs[ *cp & 0xF ]; + cp++; offset++; + return(i); + } + return( getoffset() ); +} + +static void dumpregs( void ) +{ + int i; + + sysprint("Acc: 0x%X\n", ACC); + + for(i=1; i<16; i++) + sysprint("r%x : 0x%X\n", i, regs[ i ]); + +} + +int fwengine( unsigned char *img, int size, void *ar) +{ + unsigned int crc; + int i; + + /* 14 is the minimal size of an empty image */ + if( ! (*img) || (*img != 0xFF) || (size <14) ) + { + syserr("Wrong image or no image\n"); + return -1; + } + + /* Check crc32 */ + cp = img + size - 4; + + *cp = ~(*cp) & 0xFF ; cp++; + *cp = ~(*cp) & 0xFF ; cp++; + *cp = ~(*cp) & 0xFF ; cp++; + *cp = ~(*cp) & 0xFF ; + + crc = crc32( ~0, img, size ); + + if( crc ) + { + syserr("Image CRC error\n"); + return -1; + } + + if( *(img+1) > VERSION ) + { + syserr("Image version is newer than the driver\n"); + return -1; + } + + /* Basic checks complete, we can print greeting and FW_ID here if desired */ + + /* Get to the first opcode */ + + cp = img + 2; /* Skip magic and version */ + offset = 2; + + while( (offset < size) && (*cp) ) + { + cp++; /* Skip build host name */ + offset++; + } + + cp += 6; /* Skip build date */ + offset += 6; + + while( (cp > img) && (cp < (img+size-4)) ) /* just an additional bounds check */ + { + /* First, find out opcode class */ + switch( (*cp & 0xF0) ) + { + case RLoad : + ACC = getarg( ); + break; + case Ror : + ACC |= getarg( ); + break; + case Rand : + ACC &= getarg( ); + break; + case Add : + ACC += getarg( ); + break; + case Rstor : + regs[ *cp & 0xF ] = ACC; + cp++; + offset++; + break; + case Shift : + i = getarg( ); + if(i < 0) + ACC >>= -i; + else + ACC <<= i; + break; + case Nneg : + if( *cp & 0xF ) + regs[ *cp & 0xF ] = ~regs[ *cp & 0xF ]; + else + ACC = -ACC; + cp++; + offset++; + break; + case Trr : + ACC = get_target_reg( getarg(), ar ); + break; + case Trw : + write_target_reg( getarg(), ACC , ar ); + break; + case Trx : + ACC = execute_on_target( getarg(), ACC, ar ); + break; + case Exit : + if( *cp & 0xF ) /* abort with code */ + return( regs[ *cp & 0xF ] ); + else{ /* clean exit */ + bmidone( ar ); + return(0); + } + break; + case Cmp : + ACC -= getarg(); + break; + case Ldprn : + if( ! (*cp & 0xF) ) /* register dump */ + dumpregs(); + else + { + int ret; + + ret = load_binary(ACC, cp, ar); + if( ret < 0 ) + return( -1 ); /* Error */ + cp += ret; + offset += ret; + } + break; + case Jump : + if( !(*cp & 0xF) || + ((*cp == 0xE1) && (ACC)) || + ((*cp == 0xE2) && !(ACC)) ) + + offset = getoffset(); + cp = img + offset; + + break; + default: + syserr("Image format error\n"); + break; + + } + } + return(0); +} +#ifdef UNIT_TEST +#include + +unsigned char fwbuf[ 4 * 1024 * 1024 ]; + +void bmidone( void *ar ) +{ + printf("BMI done.\n"); +} +int load_binary( unsigned int addr, unsigned char *cp, void *ar ) +{ + int size = 0; + int adv = 5; + + cp++; + size |= ( *cp & 0xFF ); cp++; + size |= ( *cp & 0xFF ) << 8; cp++; + size |= ( *cp & 0xFF ) << 16; cp++; + size |= ( *cp & 0xFF ) << 24; cp++; + + printf("Loading binary to address 0x%X, size %d\n", addr, size); + adv += size; + return(adv); +} + +int execute_on_target( unsigned address, unsigned arg, void *ar ) +{ + printf("Start target execution at address 0x%X with argument 0x%X\n", address, arg); + return(0); +} + +int write_target_reg( unsigned address, unsigned value, void *ar ) +{ + printf("Writing target register 0x%X with 0x%X\n", address, value); + return(0); +} + +unsigned int get_target_reg( unsigned address, void *ar ) +{ + unsigned int ret = 1; + + printf("Reading target register 0x%X, returning 0x%X\n", address, ret ); + return (ret); +} +int main() +{ + int ch, ret; + unsigned char *bufptr = fwbuf; + + init_crc32(); + + printf("Reading firmware image\n"); + while( (ch = getchar()) != EOF) + *bufptr++ = ch; + + printf("Calling firmware engine for image size: %d\n", bufptr - fwbuf + 1); + ret = engine( fwbuf, bufptr - fwbuf, NULL ); + printf("Engine returned with code %d\n", ret); +} +#endif /* UNIT_TEST */ +#endif /* KERNEL_VERSION 2.6 only */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/engine.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/engine.h --- linux-2.6.26/drivers/net/wireless/ath6k/engine.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/engine.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,75 @@ +/* + * athloader.h - definitions for atheros firmware loader. + * + * Firmware image format: + * + * unsigned char 0xFF // "magic" + * unsigned char version // fw loader / tool version, not fw version major/minor 4 bits each + * char hostname[variable] // zero delimited hostname where the image was built + * unsigned char month // + * unsigned char day // Date and time when the image was built + * unsigned char year // year is a number of years after 2008, i.e. 2008 is coided as 0 + * unsigned char hour // + * unsigned char min // + * // the rest are optional blocks that may be repeated and/or mixed + * unsigned char instruction + * unsigned char argument[4] // optional constant, mask or offset + * unsigned char image[variable] // optional loadable image + * // repeated as necessary + * unsigned char crc32[4] // inverted crc32 + * + */ +#ifndef ATHLOADER_IS_SEEN +#define ATHLOADER_IS_SEEN + +#include + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +#define FW_AUTOLOAD +/* Uncomment the following to build standalone application for testing + +#define UNIT_TEST +#define syserr printf +#define sysprint printf +#include "crc32.h" +#include + */ + +#ifndef UNIT_TEST +#if defined(__linux__) || defined(LINUX) +#include +#include +#include +#include +#include +#include +#define syserr(arg...) printk( KERN_ERR arg) +#define sysprint(arg...) printk( KERN_INFO arg) +#endif /* __linux__ */ +#endif /* UNIT_TEST */ + +#define VERSION (0x01) + +/* Opcodes */ +#define RLoad (0x10) +#define Ror (0x20) +#define Rand (0x30) +#define Add (0x40) +#define Rstor (0x50) +#define Shift (0x60) +#define Nneg (0x70) +#define Trr (0x80) +#define Trw (0x90) +#define Trx (0xA0) +#define Exit (0xB0) +#define Cmp (0xC0) +#define Ldprn (0xD0) +#define Jump (0xE0) + +extern unsigned int get_target_reg( unsigned address, void *ar ); +extern int write_target_reg( unsigned address, unsigned value, void *ar ); +extern int execute_on_target( unsigned int address, unsigned int arg, void *ar ); +extern int load_binary(unsigned int addr, unsigned char *data, void *ar ); +extern void bmidone( void *ar ); +#endif /* KERNEL 2.6 only */ +#endif /* ATHLOADER_IS_SEEN */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/gpio.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/gpio.h --- linux-2.6.26/drivers/net/wireless/ath6k/gpio.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/gpio.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,49 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2005 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#if defined(AR6001) +#define GPIO_PIN_COUNT 18 +#else +#define GPIO_PIN_COUNT 18 +#endif + +/* + * Possible values for WMIX_GPIO_SET_REGISTER_CMDID. + * NB: These match hardware order, so that addresses can + * easily be computed. + */ +#define GPIO_ID_OUT 0x00000000 +#define GPIO_ID_OUT_W1TS 0x00000001 +#define GPIO_ID_OUT_W1TC 0x00000002 +#define GPIO_ID_ENABLE 0x00000003 +#define GPIO_ID_ENABLE_W1TS 0x00000004 +#define GPIO_ID_ENABLE_W1TC 0x00000005 +#define GPIO_ID_IN 0x00000006 +#define GPIO_ID_STATUS 0x00000007 +#define GPIO_ID_STATUS_W1TS 0x00000008 +#define GPIO_ID_STATUS_W1TC 0x00000009 +#define GPIO_ID_PIN0 0x0000000a +#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) + +#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(17) +#define GPIO_ID_NONE 0xffffffff diff -urN linux-2.6.26/drivers/net/wireless/ath6k/gpio_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/gpio_api.h --- linux-2.6.26/drivers/net/wireless/ath6k/gpio_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/gpio_api.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,59 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Host-side General Purpose I/O API. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _GPIO_API_H_ +#define _GPIO_API_H_ + +/* + * Send a command to the Target in order to change output on GPIO pins. + */ +A_STATUS wmi_gpio_output_set(struct wmi_t *wmip, + A_UINT32 set_mask, + A_UINT32 clear_mask, + A_UINT32 enable_mask, + A_UINT32 disable_mask); + +/* + * Send a command to the Target requesting input state of GPIO pins. + */ +A_STATUS wmi_gpio_input_get(struct wmi_t *wmip); + +/* + * Send a command to the Target to change the value of a GPIO register. + */ +A_STATUS wmi_gpio_register_set(struct wmi_t *wmip, + A_UINT32 gpioreg_id, + A_UINT32 value); + +/* + * Send a command to the Target to fetch the value of a GPIO register. + */ +A_STATUS wmi_gpio_register_get(struct wmi_t *wmip, A_UINT32 gpioreg_id); + +/* + * Send a command to the Target, acknowledging some GPIO interrupts. + */ +A_STATUS wmi_gpio_intr_ack(struct wmi_t *wmip, A_UINT32 ack_mask); + +#endif /* _GPIO_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/gpio_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/gpio_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k/gpio_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/gpio_reg.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,1000 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _GPIO_REG_REG_H_ +#define _GPIO_REG_REG_H_ + +#define GPIO_OUT_ADDRESS 0x00000000 +#define GPIO_OUT_OFFSET 0x00000000 +#define GPIO_OUT_DATA_MSB 17 +#define GPIO_OUT_DATA_LSB 0 +#define GPIO_OUT_DATA_MASK 0x0003ffff +#define GPIO_OUT_DATA_GET(x) (((x) & GPIO_OUT_DATA_MASK) >> GPIO_OUT_DATA_LSB) +#define GPIO_OUT_DATA_SET(x) (((x) << GPIO_OUT_DATA_LSB) & GPIO_OUT_DATA_MASK) + +#define GPIO_OUT_W1TS_ADDRESS 0x00000004 +#define GPIO_OUT_W1TS_OFFSET 0x00000004 +#define GPIO_OUT_W1TS_DATA_MSB 17 +#define GPIO_OUT_W1TS_DATA_LSB 0 +#define GPIO_OUT_W1TS_DATA_MASK 0x0003ffff +#define GPIO_OUT_W1TS_DATA_GET(x) (((x) & GPIO_OUT_W1TS_DATA_MASK) >> GPIO_OUT_W1TS_DATA_LSB) +#define GPIO_OUT_W1TS_DATA_SET(x) (((x) << GPIO_OUT_W1TS_DATA_LSB) & GPIO_OUT_W1TS_DATA_MASK) + +#define GPIO_OUT_W1TC_ADDRESS 0x00000008 +#define GPIO_OUT_W1TC_OFFSET 0x00000008 +#define GPIO_OUT_W1TC_DATA_MSB 17 +#define GPIO_OUT_W1TC_DATA_LSB 0 +#define GPIO_OUT_W1TC_DATA_MASK 0x0003ffff +#define GPIO_OUT_W1TC_DATA_GET(x) (((x) & GPIO_OUT_W1TC_DATA_MASK) >> GPIO_OUT_W1TC_DATA_LSB) +#define GPIO_OUT_W1TC_DATA_SET(x) (((x) << GPIO_OUT_W1TC_DATA_LSB) & GPIO_OUT_W1TC_DATA_MASK) + +#define GPIO_ENABLE_ADDRESS 0x0000000c +#define GPIO_ENABLE_OFFSET 0x0000000c +#define GPIO_ENABLE_DATA_MSB 17 +#define GPIO_ENABLE_DATA_LSB 0 +#define GPIO_ENABLE_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_DATA_GET(x) (((x) & GPIO_ENABLE_DATA_MASK) >> GPIO_ENABLE_DATA_LSB) +#define GPIO_ENABLE_DATA_SET(x) (((x) << GPIO_ENABLE_DATA_LSB) & GPIO_ENABLE_DATA_MASK) + +#define GPIO_ENABLE_W1TS_ADDRESS 0x00000010 +#define GPIO_ENABLE_W1TS_OFFSET 0x00000010 +#define GPIO_ENABLE_W1TS_DATA_MSB 17 +#define GPIO_ENABLE_W1TS_DATA_LSB 0 +#define GPIO_ENABLE_W1TS_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_W1TS_DATA_GET(x) (((x) & GPIO_ENABLE_W1TS_DATA_MASK) >> GPIO_ENABLE_W1TS_DATA_LSB) +#define GPIO_ENABLE_W1TS_DATA_SET(x) (((x) << GPIO_ENABLE_W1TS_DATA_LSB) & GPIO_ENABLE_W1TS_DATA_MASK) + +#define GPIO_ENABLE_W1TC_ADDRESS 0x00000014 +#define GPIO_ENABLE_W1TC_OFFSET 0x00000014 +#define GPIO_ENABLE_W1TC_DATA_MSB 17 +#define GPIO_ENABLE_W1TC_DATA_LSB 0 +#define GPIO_ENABLE_W1TC_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_W1TC_DATA_GET(x) (((x) & GPIO_ENABLE_W1TC_DATA_MASK) >> GPIO_ENABLE_W1TC_DATA_LSB) +#define GPIO_ENABLE_W1TC_DATA_SET(x) (((x) << GPIO_ENABLE_W1TC_DATA_LSB) & GPIO_ENABLE_W1TC_DATA_MASK) + +#define GPIO_IN_ADDRESS 0x00000018 +#define GPIO_IN_OFFSET 0x00000018 +#define GPIO_IN_DATA_MSB 17 +#define GPIO_IN_DATA_LSB 0 +#define GPIO_IN_DATA_MASK 0x0003ffff +#define GPIO_IN_DATA_GET(x) (((x) & GPIO_IN_DATA_MASK) >> GPIO_IN_DATA_LSB) +#define GPIO_IN_DATA_SET(x) (((x) << GPIO_IN_DATA_LSB) & GPIO_IN_DATA_MASK) + +#define GPIO_STATUS_ADDRESS 0x0000001c +#define GPIO_STATUS_OFFSET 0x0000001c +#define GPIO_STATUS_INTERRUPT_MSB 17 +#define GPIO_STATUS_INTERRUPT_LSB 0 +#define GPIO_STATUS_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_INTERRUPT_MASK) >> GPIO_STATUS_INTERRUPT_LSB) +#define GPIO_STATUS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_INTERRUPT_LSB) & GPIO_STATUS_INTERRUPT_MASK) + +#define GPIO_STATUS_W1TS_ADDRESS 0x00000020 +#define GPIO_STATUS_W1TS_OFFSET 0x00000020 +#define GPIO_STATUS_W1TS_INTERRUPT_MSB 17 +#define GPIO_STATUS_W1TS_INTERRUPT_LSB 0 +#define GPIO_STATUS_W1TS_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_W1TS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TS_INTERRUPT_MASK) >> GPIO_STATUS_W1TS_INTERRUPT_LSB) +#define GPIO_STATUS_W1TS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TS_INTERRUPT_LSB) & GPIO_STATUS_W1TS_INTERRUPT_MASK) + +#define GPIO_STATUS_W1TC_ADDRESS 0x00000024 +#define GPIO_STATUS_W1TC_OFFSET 0x00000024 +#define GPIO_STATUS_W1TC_INTERRUPT_MSB 17 +#define GPIO_STATUS_W1TC_INTERRUPT_LSB 0 +#define GPIO_STATUS_W1TC_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_W1TC_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TC_INTERRUPT_MASK) >> GPIO_STATUS_W1TC_INTERRUPT_LSB) +#define GPIO_STATUS_W1TC_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TC_INTERRUPT_LSB) & GPIO_STATUS_W1TC_INTERRUPT_MASK) + +#define GPIO_PIN0_ADDRESS 0x00000028 +#define GPIO_PIN0_OFFSET 0x00000028 +#define GPIO_PIN0_CONFIG_MSB 12 +#define GPIO_PIN0_CONFIG_LSB 11 +#define GPIO_PIN0_CONFIG_MASK 0x00001800 +#define GPIO_PIN0_CONFIG_GET(x) (((x) & GPIO_PIN0_CONFIG_MASK) >> GPIO_PIN0_CONFIG_LSB) +#define GPIO_PIN0_CONFIG_SET(x) (((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK) +#define GPIO_PIN0_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN0_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN0_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN0_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN0_WAKEUP_ENABLE_MASK) >> GPIO_PIN0_WAKEUP_ENABLE_LSB) +#define GPIO_PIN0_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN0_WAKEUP_ENABLE_LSB) & GPIO_PIN0_WAKEUP_ENABLE_MASK) +#define GPIO_PIN0_INT_TYPE_MSB 9 +#define GPIO_PIN0_INT_TYPE_LSB 7 +#define GPIO_PIN0_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN0_INT_TYPE_GET(x) (((x) & GPIO_PIN0_INT_TYPE_MASK) >> GPIO_PIN0_INT_TYPE_LSB) +#define GPIO_PIN0_INT_TYPE_SET(x) (((x) << GPIO_PIN0_INT_TYPE_LSB) & GPIO_PIN0_INT_TYPE_MASK) +#define GPIO_PIN0_PAD_DRIVER_MSB 2 +#define GPIO_PIN0_PAD_DRIVER_LSB 2 +#define GPIO_PIN0_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN0_PAD_DRIVER_GET(x) (((x) & GPIO_PIN0_PAD_DRIVER_MASK) >> GPIO_PIN0_PAD_DRIVER_LSB) +#define GPIO_PIN0_PAD_DRIVER_SET(x) (((x) << GPIO_PIN0_PAD_DRIVER_LSB) & GPIO_PIN0_PAD_DRIVER_MASK) +#define GPIO_PIN0_SOURCE_MSB 0 +#define GPIO_PIN0_SOURCE_LSB 0 +#define GPIO_PIN0_SOURCE_MASK 0x00000001 +#define GPIO_PIN0_SOURCE_GET(x) (((x) & GPIO_PIN0_SOURCE_MASK) >> GPIO_PIN0_SOURCE_LSB) +#define GPIO_PIN0_SOURCE_SET(x) (((x) << GPIO_PIN0_SOURCE_LSB) & GPIO_PIN0_SOURCE_MASK) + +#define GPIO_PIN1_ADDRESS 0x0000002c +#define GPIO_PIN1_OFFSET 0x0000002c +#define GPIO_PIN1_CONFIG_MSB 12 +#define GPIO_PIN1_CONFIG_LSB 11 +#define GPIO_PIN1_CONFIG_MASK 0x00001800 +#define GPIO_PIN1_CONFIG_GET(x) (((x) & GPIO_PIN1_CONFIG_MASK) >> GPIO_PIN1_CONFIG_LSB) +#define GPIO_PIN1_CONFIG_SET(x) (((x) << GPIO_PIN1_CONFIG_LSB) & GPIO_PIN1_CONFIG_MASK) +#define GPIO_PIN1_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN1_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN1_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN1_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN1_WAKEUP_ENABLE_MASK) >> GPIO_PIN1_WAKEUP_ENABLE_LSB) +#define GPIO_PIN1_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN1_WAKEUP_ENABLE_LSB) & GPIO_PIN1_WAKEUP_ENABLE_MASK) +#define GPIO_PIN1_INT_TYPE_MSB 9 +#define GPIO_PIN1_INT_TYPE_LSB 7 +#define GPIO_PIN1_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN1_INT_TYPE_GET(x) (((x) & GPIO_PIN1_INT_TYPE_MASK) >> GPIO_PIN1_INT_TYPE_LSB) +#define GPIO_PIN1_INT_TYPE_SET(x) (((x) << GPIO_PIN1_INT_TYPE_LSB) & GPIO_PIN1_INT_TYPE_MASK) +#define GPIO_PIN1_PAD_DRIVER_MSB 2 +#define GPIO_PIN1_PAD_DRIVER_LSB 2 +#define GPIO_PIN1_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN1_PAD_DRIVER_GET(x) (((x) & GPIO_PIN1_PAD_DRIVER_MASK) >> GPIO_PIN1_PAD_DRIVER_LSB) +#define GPIO_PIN1_PAD_DRIVER_SET(x) (((x) << GPIO_PIN1_PAD_DRIVER_LSB) & GPIO_PIN1_PAD_DRIVER_MASK) +#define GPIO_PIN1_SOURCE_MSB 0 +#define GPIO_PIN1_SOURCE_LSB 0 +#define GPIO_PIN1_SOURCE_MASK 0x00000001 +#define GPIO_PIN1_SOURCE_GET(x) (((x) & GPIO_PIN1_SOURCE_MASK) >> GPIO_PIN1_SOURCE_LSB) +#define GPIO_PIN1_SOURCE_SET(x) (((x) << GPIO_PIN1_SOURCE_LSB) & GPIO_PIN1_SOURCE_MASK) + +#define GPIO_PIN2_ADDRESS 0x00000030 +#define GPIO_PIN2_OFFSET 0x00000030 +#define GPIO_PIN2_CONFIG_MSB 12 +#define GPIO_PIN2_CONFIG_LSB 11 +#define GPIO_PIN2_CONFIG_MASK 0x00001800 +#define GPIO_PIN2_CONFIG_GET(x) (((x) & GPIO_PIN2_CONFIG_MASK) >> GPIO_PIN2_CONFIG_LSB) +#define GPIO_PIN2_CONFIG_SET(x) (((x) << GPIO_PIN2_CONFIG_LSB) & GPIO_PIN2_CONFIG_MASK) +#define GPIO_PIN2_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN2_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN2_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN2_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN2_WAKEUP_ENABLE_MASK) >> GPIO_PIN2_WAKEUP_ENABLE_LSB) +#define GPIO_PIN2_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN2_WAKEUP_ENABLE_LSB) & GPIO_PIN2_WAKEUP_ENABLE_MASK) +#define GPIO_PIN2_INT_TYPE_MSB 9 +#define GPIO_PIN2_INT_TYPE_LSB 7 +#define GPIO_PIN2_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN2_INT_TYPE_GET(x) (((x) & GPIO_PIN2_INT_TYPE_MASK) >> GPIO_PIN2_INT_TYPE_LSB) +#define GPIO_PIN2_INT_TYPE_SET(x) (((x) << GPIO_PIN2_INT_TYPE_LSB) & GPIO_PIN2_INT_TYPE_MASK) +#define GPIO_PIN2_PAD_DRIVER_MSB 2 +#define GPIO_PIN2_PAD_DRIVER_LSB 2 +#define GPIO_PIN2_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN2_PAD_DRIVER_GET(x) (((x) & GPIO_PIN2_PAD_DRIVER_MASK) >> GPIO_PIN2_PAD_DRIVER_LSB) +#define GPIO_PIN2_PAD_DRIVER_SET(x) (((x) << GPIO_PIN2_PAD_DRIVER_LSB) & GPIO_PIN2_PAD_DRIVER_MASK) +#define GPIO_PIN2_SOURCE_MSB 0 +#define GPIO_PIN2_SOURCE_LSB 0 +#define GPIO_PIN2_SOURCE_MASK 0x00000001 +#define GPIO_PIN2_SOURCE_GET(x) (((x) & GPIO_PIN2_SOURCE_MASK) >> GPIO_PIN2_SOURCE_LSB) +#define GPIO_PIN2_SOURCE_SET(x) (((x) << GPIO_PIN2_SOURCE_LSB) & GPIO_PIN2_SOURCE_MASK) + +#define GPIO_PIN3_ADDRESS 0x00000034 +#define GPIO_PIN3_OFFSET 0x00000034 +#define GPIO_PIN3_CONFIG_MSB 12 +#define GPIO_PIN3_CONFIG_LSB 11 +#define GPIO_PIN3_CONFIG_MASK 0x00001800 +#define GPIO_PIN3_CONFIG_GET(x) (((x) & GPIO_PIN3_CONFIG_MASK) >> GPIO_PIN3_CONFIG_LSB) +#define GPIO_PIN3_CONFIG_SET(x) (((x) << GPIO_PIN3_CONFIG_LSB) & GPIO_PIN3_CONFIG_MASK) +#define GPIO_PIN3_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN3_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN3_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN3_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN3_WAKEUP_ENABLE_MASK) >> GPIO_PIN3_WAKEUP_ENABLE_LSB) +#define GPIO_PIN3_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN3_WAKEUP_ENABLE_LSB) & GPIO_PIN3_WAKEUP_ENABLE_MASK) +#define GPIO_PIN3_INT_TYPE_MSB 9 +#define GPIO_PIN3_INT_TYPE_LSB 7 +#define GPIO_PIN3_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN3_INT_TYPE_GET(x) (((x) & GPIO_PIN3_INT_TYPE_MASK) >> GPIO_PIN3_INT_TYPE_LSB) +#define GPIO_PIN3_INT_TYPE_SET(x) (((x) << GPIO_PIN3_INT_TYPE_LSB) & GPIO_PIN3_INT_TYPE_MASK) +#define GPIO_PIN3_PAD_DRIVER_MSB 2 +#define GPIO_PIN3_PAD_DRIVER_LSB 2 +#define GPIO_PIN3_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN3_PAD_DRIVER_GET(x) (((x) & GPIO_PIN3_PAD_DRIVER_MASK) >> GPIO_PIN3_PAD_DRIVER_LSB) +#define GPIO_PIN3_PAD_DRIVER_SET(x) (((x) << GPIO_PIN3_PAD_DRIVER_LSB) & GPIO_PIN3_PAD_DRIVER_MASK) +#define GPIO_PIN3_SOURCE_MSB 0 +#define GPIO_PIN3_SOURCE_LSB 0 +#define GPIO_PIN3_SOURCE_MASK 0x00000001 +#define GPIO_PIN3_SOURCE_GET(x) (((x) & GPIO_PIN3_SOURCE_MASK) >> GPIO_PIN3_SOURCE_LSB) +#define GPIO_PIN3_SOURCE_SET(x) (((x) << GPIO_PIN3_SOURCE_LSB) & GPIO_PIN3_SOURCE_MASK) + +#define GPIO_PIN4_ADDRESS 0x00000038 +#define GPIO_PIN4_OFFSET 0x00000038 +#define GPIO_PIN4_CONFIG_MSB 12 +#define GPIO_PIN4_CONFIG_LSB 11 +#define GPIO_PIN4_CONFIG_MASK 0x00001800 +#define GPIO_PIN4_CONFIG_GET(x) (((x) & GPIO_PIN4_CONFIG_MASK) >> GPIO_PIN4_CONFIG_LSB) +#define GPIO_PIN4_CONFIG_SET(x) (((x) << GPIO_PIN4_CONFIG_LSB) & GPIO_PIN4_CONFIG_MASK) +#define GPIO_PIN4_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN4_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN4_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN4_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN4_WAKEUP_ENABLE_MASK) >> GPIO_PIN4_WAKEUP_ENABLE_LSB) +#define GPIO_PIN4_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN4_WAKEUP_ENABLE_LSB) & GPIO_PIN4_WAKEUP_ENABLE_MASK) +#define GPIO_PIN4_INT_TYPE_MSB 9 +#define GPIO_PIN4_INT_TYPE_LSB 7 +#define GPIO_PIN4_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN4_INT_TYPE_GET(x) (((x) & GPIO_PIN4_INT_TYPE_MASK) >> GPIO_PIN4_INT_TYPE_LSB) +#define GPIO_PIN4_INT_TYPE_SET(x) (((x) << GPIO_PIN4_INT_TYPE_LSB) & GPIO_PIN4_INT_TYPE_MASK) +#define GPIO_PIN4_PAD_DRIVER_MSB 2 +#define GPIO_PIN4_PAD_DRIVER_LSB 2 +#define GPIO_PIN4_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN4_PAD_DRIVER_GET(x) (((x) & GPIO_PIN4_PAD_DRIVER_MASK) >> GPIO_PIN4_PAD_DRIVER_LSB) +#define GPIO_PIN4_PAD_DRIVER_SET(x) (((x) << GPIO_PIN4_PAD_DRIVER_LSB) & GPIO_PIN4_PAD_DRIVER_MASK) +#define GPIO_PIN4_SOURCE_MSB 0 +#define GPIO_PIN4_SOURCE_LSB 0 +#define GPIO_PIN4_SOURCE_MASK 0x00000001 +#define GPIO_PIN4_SOURCE_GET(x) (((x) & GPIO_PIN4_SOURCE_MASK) >> GPIO_PIN4_SOURCE_LSB) +#define GPIO_PIN4_SOURCE_SET(x) (((x) << GPIO_PIN4_SOURCE_LSB) & GPIO_PIN4_SOURCE_MASK) + +#define GPIO_PIN5_ADDRESS 0x0000003c +#define GPIO_PIN5_OFFSET 0x0000003c +#define GPIO_PIN5_CONFIG_MSB 12 +#define GPIO_PIN5_CONFIG_LSB 11 +#define GPIO_PIN5_CONFIG_MASK 0x00001800 +#define GPIO_PIN5_CONFIG_GET(x) (((x) & GPIO_PIN5_CONFIG_MASK) >> GPIO_PIN5_CONFIG_LSB) +#define GPIO_PIN5_CONFIG_SET(x) (((x) << GPIO_PIN5_CONFIG_LSB) & GPIO_PIN5_CONFIG_MASK) +#define GPIO_PIN5_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN5_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN5_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN5_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN5_WAKEUP_ENABLE_MASK) >> GPIO_PIN5_WAKEUP_ENABLE_LSB) +#define GPIO_PIN5_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN5_WAKEUP_ENABLE_LSB) & GPIO_PIN5_WAKEUP_ENABLE_MASK) +#define GPIO_PIN5_INT_TYPE_MSB 9 +#define GPIO_PIN5_INT_TYPE_LSB 7 +#define GPIO_PIN5_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN5_INT_TYPE_GET(x) (((x) & GPIO_PIN5_INT_TYPE_MASK) >> GPIO_PIN5_INT_TYPE_LSB) +#define GPIO_PIN5_INT_TYPE_SET(x) (((x) << GPIO_PIN5_INT_TYPE_LSB) & GPIO_PIN5_INT_TYPE_MASK) +#define GPIO_PIN5_PAD_DRIVER_MSB 2 +#define GPIO_PIN5_PAD_DRIVER_LSB 2 +#define GPIO_PIN5_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN5_PAD_DRIVER_GET(x) (((x) & GPIO_PIN5_PAD_DRIVER_MASK) >> GPIO_PIN5_PAD_DRIVER_LSB) +#define GPIO_PIN5_PAD_DRIVER_SET(x) (((x) << GPIO_PIN5_PAD_DRIVER_LSB) & GPIO_PIN5_PAD_DRIVER_MASK) +#define GPIO_PIN5_SOURCE_MSB 0 +#define GPIO_PIN5_SOURCE_LSB 0 +#define GPIO_PIN5_SOURCE_MASK 0x00000001 +#define GPIO_PIN5_SOURCE_GET(x) (((x) & GPIO_PIN5_SOURCE_MASK) >> GPIO_PIN5_SOURCE_LSB) +#define GPIO_PIN5_SOURCE_SET(x) (((x) << GPIO_PIN5_SOURCE_LSB) & GPIO_PIN5_SOURCE_MASK) + +#define GPIO_PIN6_ADDRESS 0x00000040 +#define GPIO_PIN6_OFFSET 0x00000040 +#define GPIO_PIN6_CONFIG_MSB 12 +#define GPIO_PIN6_CONFIG_LSB 11 +#define GPIO_PIN6_CONFIG_MASK 0x00001800 +#define GPIO_PIN6_CONFIG_GET(x) (((x) & GPIO_PIN6_CONFIG_MASK) >> GPIO_PIN6_CONFIG_LSB) +#define GPIO_PIN6_CONFIG_SET(x) (((x) << GPIO_PIN6_CONFIG_LSB) & GPIO_PIN6_CONFIG_MASK) +#define GPIO_PIN6_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN6_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN6_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN6_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN6_WAKEUP_ENABLE_MASK) >> GPIO_PIN6_WAKEUP_ENABLE_LSB) +#define GPIO_PIN6_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN6_WAKEUP_ENABLE_LSB) & GPIO_PIN6_WAKEUP_ENABLE_MASK) +#define GPIO_PIN6_INT_TYPE_MSB 9 +#define GPIO_PIN6_INT_TYPE_LSB 7 +#define GPIO_PIN6_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN6_INT_TYPE_GET(x) (((x) & GPIO_PIN6_INT_TYPE_MASK) >> GPIO_PIN6_INT_TYPE_LSB) +#define GPIO_PIN6_INT_TYPE_SET(x) (((x) << GPIO_PIN6_INT_TYPE_LSB) & GPIO_PIN6_INT_TYPE_MASK) +#define GPIO_PIN6_PAD_DRIVER_MSB 2 +#define GPIO_PIN6_PAD_DRIVER_LSB 2 +#define GPIO_PIN6_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN6_PAD_DRIVER_GET(x) (((x) & GPIO_PIN6_PAD_DRIVER_MASK) >> GPIO_PIN6_PAD_DRIVER_LSB) +#define GPIO_PIN6_PAD_DRIVER_SET(x) (((x) << GPIO_PIN6_PAD_DRIVER_LSB) & GPIO_PIN6_PAD_DRIVER_MASK) +#define GPIO_PIN6_SOURCE_MSB 0 +#define GPIO_PIN6_SOURCE_LSB 0 +#define GPIO_PIN6_SOURCE_MASK 0x00000001 +#define GPIO_PIN6_SOURCE_GET(x) (((x) & GPIO_PIN6_SOURCE_MASK) >> GPIO_PIN6_SOURCE_LSB) +#define GPIO_PIN6_SOURCE_SET(x) (((x) << GPIO_PIN6_SOURCE_LSB) & GPIO_PIN6_SOURCE_MASK) + +#define GPIO_PIN7_ADDRESS 0x00000044 +#define GPIO_PIN7_OFFSET 0x00000044 +#define GPIO_PIN7_CONFIG_MSB 12 +#define GPIO_PIN7_CONFIG_LSB 11 +#define GPIO_PIN7_CONFIG_MASK 0x00001800 +#define GPIO_PIN7_CONFIG_GET(x) (((x) & GPIO_PIN7_CONFIG_MASK) >> GPIO_PIN7_CONFIG_LSB) +#define GPIO_PIN7_CONFIG_SET(x) (((x) << GPIO_PIN7_CONFIG_LSB) & GPIO_PIN7_CONFIG_MASK) +#define GPIO_PIN7_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN7_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN7_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN7_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN7_WAKEUP_ENABLE_MASK) >> GPIO_PIN7_WAKEUP_ENABLE_LSB) +#define GPIO_PIN7_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN7_WAKEUP_ENABLE_LSB) & GPIO_PIN7_WAKEUP_ENABLE_MASK) +#define GPIO_PIN7_INT_TYPE_MSB 9 +#define GPIO_PIN7_INT_TYPE_LSB 7 +#define GPIO_PIN7_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN7_INT_TYPE_GET(x) (((x) & GPIO_PIN7_INT_TYPE_MASK) >> GPIO_PIN7_INT_TYPE_LSB) +#define GPIO_PIN7_INT_TYPE_SET(x) (((x) << GPIO_PIN7_INT_TYPE_LSB) & GPIO_PIN7_INT_TYPE_MASK) +#define GPIO_PIN7_PAD_DRIVER_MSB 2 +#define GPIO_PIN7_PAD_DRIVER_LSB 2 +#define GPIO_PIN7_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN7_PAD_DRIVER_GET(x) (((x) & GPIO_PIN7_PAD_DRIVER_MASK) >> GPIO_PIN7_PAD_DRIVER_LSB) +#define GPIO_PIN7_PAD_DRIVER_SET(x) (((x) << GPIO_PIN7_PAD_DRIVER_LSB) & GPIO_PIN7_PAD_DRIVER_MASK) +#define GPIO_PIN7_SOURCE_MSB 0 +#define GPIO_PIN7_SOURCE_LSB 0 +#define GPIO_PIN7_SOURCE_MASK 0x00000001 +#define GPIO_PIN7_SOURCE_GET(x) (((x) & GPIO_PIN7_SOURCE_MASK) >> GPIO_PIN7_SOURCE_LSB) +#define GPIO_PIN7_SOURCE_SET(x) (((x) << GPIO_PIN7_SOURCE_LSB) & GPIO_PIN7_SOURCE_MASK) + +#define GPIO_PIN8_ADDRESS 0x00000048 +#define GPIO_PIN8_OFFSET 0x00000048 +#define GPIO_PIN8_CONFIG_MSB 12 +#define GPIO_PIN8_CONFIG_LSB 11 +#define GPIO_PIN8_CONFIG_MASK 0x00001800 +#define GPIO_PIN8_CONFIG_GET(x) (((x) & GPIO_PIN8_CONFIG_MASK) >> GPIO_PIN8_CONFIG_LSB) +#define GPIO_PIN8_CONFIG_SET(x) (((x) << GPIO_PIN8_CONFIG_LSB) & GPIO_PIN8_CONFIG_MASK) +#define GPIO_PIN8_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN8_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN8_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN8_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN8_WAKEUP_ENABLE_MASK) >> GPIO_PIN8_WAKEUP_ENABLE_LSB) +#define GPIO_PIN8_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN8_WAKEUP_ENABLE_LSB) & GPIO_PIN8_WAKEUP_ENABLE_MASK) +#define GPIO_PIN8_INT_TYPE_MSB 9 +#define GPIO_PIN8_INT_TYPE_LSB 7 +#define GPIO_PIN8_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN8_INT_TYPE_GET(x) (((x) & GPIO_PIN8_INT_TYPE_MASK) >> GPIO_PIN8_INT_TYPE_LSB) +#define GPIO_PIN8_INT_TYPE_SET(x) (((x) << GPIO_PIN8_INT_TYPE_LSB) & GPIO_PIN8_INT_TYPE_MASK) +#define GPIO_PIN8_PAD_DRIVER_MSB 2 +#define GPIO_PIN8_PAD_DRIVER_LSB 2 +#define GPIO_PIN8_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN8_PAD_DRIVER_GET(x) (((x) & GPIO_PIN8_PAD_DRIVER_MASK) >> GPIO_PIN8_PAD_DRIVER_LSB) +#define GPIO_PIN8_PAD_DRIVER_SET(x) (((x) << GPIO_PIN8_PAD_DRIVER_LSB) & GPIO_PIN8_PAD_DRIVER_MASK) +#define GPIO_PIN8_SOURCE_MSB 0 +#define GPIO_PIN8_SOURCE_LSB 0 +#define GPIO_PIN8_SOURCE_MASK 0x00000001 +#define GPIO_PIN8_SOURCE_GET(x) (((x) & GPIO_PIN8_SOURCE_MASK) >> GPIO_PIN8_SOURCE_LSB) +#define GPIO_PIN8_SOURCE_SET(x) (((x) << GPIO_PIN8_SOURCE_LSB) & GPIO_PIN8_SOURCE_MASK) + +#define GPIO_PIN9_ADDRESS 0x0000004c +#define GPIO_PIN9_OFFSET 0x0000004c +#define GPIO_PIN9_CONFIG_MSB 12 +#define GPIO_PIN9_CONFIG_LSB 11 +#define GPIO_PIN9_CONFIG_MASK 0x00001800 +#define GPIO_PIN9_CONFIG_GET(x) (((x) & GPIO_PIN9_CONFIG_MASK) >> GPIO_PIN9_CONFIG_LSB) +#define GPIO_PIN9_CONFIG_SET(x) (((x) << GPIO_PIN9_CONFIG_LSB) & GPIO_PIN9_CONFIG_MASK) +#define GPIO_PIN9_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN9_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN9_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN9_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN9_WAKEUP_ENABLE_MASK) >> GPIO_PIN9_WAKEUP_ENABLE_LSB) +#define GPIO_PIN9_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN9_WAKEUP_ENABLE_LSB) & GPIO_PIN9_WAKEUP_ENABLE_MASK) +#define GPIO_PIN9_INT_TYPE_MSB 9 +#define GPIO_PIN9_INT_TYPE_LSB 7 +#define GPIO_PIN9_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN9_INT_TYPE_GET(x) (((x) & GPIO_PIN9_INT_TYPE_MASK) >> GPIO_PIN9_INT_TYPE_LSB) +#define GPIO_PIN9_INT_TYPE_SET(x) (((x) << GPIO_PIN9_INT_TYPE_LSB) & GPIO_PIN9_INT_TYPE_MASK) +#define GPIO_PIN9_PAD_DRIVER_MSB 2 +#define GPIO_PIN9_PAD_DRIVER_LSB 2 +#define GPIO_PIN9_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN9_PAD_DRIVER_GET(x) (((x) & GPIO_PIN9_PAD_DRIVER_MASK) >> GPIO_PIN9_PAD_DRIVER_LSB) +#define GPIO_PIN9_PAD_DRIVER_SET(x) (((x) << GPIO_PIN9_PAD_DRIVER_LSB) & GPIO_PIN9_PAD_DRIVER_MASK) +#define GPIO_PIN9_SOURCE_MSB 0 +#define GPIO_PIN9_SOURCE_LSB 0 +#define GPIO_PIN9_SOURCE_MASK 0x00000001 +#define GPIO_PIN9_SOURCE_GET(x) (((x) & GPIO_PIN9_SOURCE_MASK) >> GPIO_PIN9_SOURCE_LSB) +#define GPIO_PIN9_SOURCE_SET(x) (((x) << GPIO_PIN9_SOURCE_LSB) & GPIO_PIN9_SOURCE_MASK) + +#define GPIO_PIN10_ADDRESS 0x00000050 +#define GPIO_PIN10_OFFSET 0x00000050 +#define GPIO_PIN10_CONFIG_MSB 12 +#define GPIO_PIN10_CONFIG_LSB 11 +#define GPIO_PIN10_CONFIG_MASK 0x00001800 +#define GPIO_PIN10_CONFIG_GET(x) (((x) & GPIO_PIN10_CONFIG_MASK) >> GPIO_PIN10_CONFIG_LSB) +#define GPIO_PIN10_CONFIG_SET(x) (((x) << GPIO_PIN10_CONFIG_LSB) & GPIO_PIN10_CONFIG_MASK) +#define GPIO_PIN10_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN10_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN10_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN10_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN10_WAKEUP_ENABLE_MASK) >> GPIO_PIN10_WAKEUP_ENABLE_LSB) +#define GPIO_PIN10_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN10_WAKEUP_ENABLE_LSB) & GPIO_PIN10_WAKEUP_ENABLE_MASK) +#define GPIO_PIN10_INT_TYPE_MSB 9 +#define GPIO_PIN10_INT_TYPE_LSB 7 +#define GPIO_PIN10_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN10_INT_TYPE_GET(x) (((x) & GPIO_PIN10_INT_TYPE_MASK) >> GPIO_PIN10_INT_TYPE_LSB) +#define GPIO_PIN10_INT_TYPE_SET(x) (((x) << GPIO_PIN10_INT_TYPE_LSB) & GPIO_PIN10_INT_TYPE_MASK) +#define GPIO_PIN10_PAD_DRIVER_MSB 2 +#define GPIO_PIN10_PAD_DRIVER_LSB 2 +#define GPIO_PIN10_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN10_PAD_DRIVER_GET(x) (((x) & GPIO_PIN10_PAD_DRIVER_MASK) >> GPIO_PIN10_PAD_DRIVER_LSB) +#define GPIO_PIN10_PAD_DRIVER_SET(x) (((x) << GPIO_PIN10_PAD_DRIVER_LSB) & GPIO_PIN10_PAD_DRIVER_MASK) +#define GPIO_PIN10_SOURCE_MSB 0 +#define GPIO_PIN10_SOURCE_LSB 0 +#define GPIO_PIN10_SOURCE_MASK 0x00000001 +#define GPIO_PIN10_SOURCE_GET(x) (((x) & GPIO_PIN10_SOURCE_MASK) >> GPIO_PIN10_SOURCE_LSB) +#define GPIO_PIN10_SOURCE_SET(x) (((x) << GPIO_PIN10_SOURCE_LSB) & GPIO_PIN10_SOURCE_MASK) + +#define GPIO_PIN11_ADDRESS 0x00000054 +#define GPIO_PIN11_OFFSET 0x00000054 +#define GPIO_PIN11_CONFIG_MSB 12 +#define GPIO_PIN11_CONFIG_LSB 11 +#define GPIO_PIN11_CONFIG_MASK 0x00001800 +#define GPIO_PIN11_CONFIG_GET(x) (((x) & GPIO_PIN11_CONFIG_MASK) >> GPIO_PIN11_CONFIG_LSB) +#define GPIO_PIN11_CONFIG_SET(x) (((x) << GPIO_PIN11_CONFIG_LSB) & GPIO_PIN11_CONFIG_MASK) +#define GPIO_PIN11_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN11_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN11_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN11_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN11_WAKEUP_ENABLE_MASK) >> GPIO_PIN11_WAKEUP_ENABLE_LSB) +#define GPIO_PIN11_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN11_WAKEUP_ENABLE_LSB) & GPIO_PIN11_WAKEUP_ENABLE_MASK) +#define GPIO_PIN11_INT_TYPE_MSB 9 +#define GPIO_PIN11_INT_TYPE_LSB 7 +#define GPIO_PIN11_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN11_INT_TYPE_GET(x) (((x) & GPIO_PIN11_INT_TYPE_MASK) >> GPIO_PIN11_INT_TYPE_LSB) +#define GPIO_PIN11_INT_TYPE_SET(x) (((x) << GPIO_PIN11_INT_TYPE_LSB) & GPIO_PIN11_INT_TYPE_MASK) +#define GPIO_PIN11_PAD_DRIVER_MSB 2 +#define GPIO_PIN11_PAD_DRIVER_LSB 2 +#define GPIO_PIN11_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN11_PAD_DRIVER_GET(x) (((x) & GPIO_PIN11_PAD_DRIVER_MASK) >> GPIO_PIN11_PAD_DRIVER_LSB) +#define GPIO_PIN11_PAD_DRIVER_SET(x) (((x) << GPIO_PIN11_PAD_DRIVER_LSB) & GPIO_PIN11_PAD_DRIVER_MASK) +#define GPIO_PIN11_SOURCE_MSB 0 +#define GPIO_PIN11_SOURCE_LSB 0 +#define GPIO_PIN11_SOURCE_MASK 0x00000001 +#define GPIO_PIN11_SOURCE_GET(x) (((x) & GPIO_PIN11_SOURCE_MASK) >> GPIO_PIN11_SOURCE_LSB) +#define GPIO_PIN11_SOURCE_SET(x) (((x) << GPIO_PIN11_SOURCE_LSB) & GPIO_PIN11_SOURCE_MASK) + +#define GPIO_PIN12_ADDRESS 0x00000058 +#define GPIO_PIN12_OFFSET 0x00000058 +#define GPIO_PIN12_CONFIG_MSB 12 +#define GPIO_PIN12_CONFIG_LSB 11 +#define GPIO_PIN12_CONFIG_MASK 0x00001800 +#define GPIO_PIN12_CONFIG_GET(x) (((x) & GPIO_PIN12_CONFIG_MASK) >> GPIO_PIN12_CONFIG_LSB) +#define GPIO_PIN12_CONFIG_SET(x) (((x) << GPIO_PIN12_CONFIG_LSB) & GPIO_PIN12_CONFIG_MASK) +#define GPIO_PIN12_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN12_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN12_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN12_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN12_WAKEUP_ENABLE_MASK) >> GPIO_PIN12_WAKEUP_ENABLE_LSB) +#define GPIO_PIN12_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN12_WAKEUP_ENABLE_LSB) & GPIO_PIN12_WAKEUP_ENABLE_MASK) +#define GPIO_PIN12_INT_TYPE_MSB 9 +#define GPIO_PIN12_INT_TYPE_LSB 7 +#define GPIO_PIN12_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN12_INT_TYPE_GET(x) (((x) & GPIO_PIN12_INT_TYPE_MASK) >> GPIO_PIN12_INT_TYPE_LSB) +#define GPIO_PIN12_INT_TYPE_SET(x) (((x) << GPIO_PIN12_INT_TYPE_LSB) & GPIO_PIN12_INT_TYPE_MASK) +#define GPIO_PIN12_PAD_DRIVER_MSB 2 +#define GPIO_PIN12_PAD_DRIVER_LSB 2 +#define GPIO_PIN12_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN12_PAD_DRIVER_GET(x) (((x) & GPIO_PIN12_PAD_DRIVER_MASK) >> GPIO_PIN12_PAD_DRIVER_LSB) +#define GPIO_PIN12_PAD_DRIVER_SET(x) (((x) << GPIO_PIN12_PAD_DRIVER_LSB) & GPIO_PIN12_PAD_DRIVER_MASK) +#define GPIO_PIN12_SOURCE_MSB 0 +#define GPIO_PIN12_SOURCE_LSB 0 +#define GPIO_PIN12_SOURCE_MASK 0x00000001 +#define GPIO_PIN12_SOURCE_GET(x) (((x) & GPIO_PIN12_SOURCE_MASK) >> GPIO_PIN12_SOURCE_LSB) +#define GPIO_PIN12_SOURCE_SET(x) (((x) << GPIO_PIN12_SOURCE_LSB) & GPIO_PIN12_SOURCE_MASK) + +#define GPIO_PIN13_ADDRESS 0x0000005c +#define GPIO_PIN13_OFFSET 0x0000005c +#define GPIO_PIN13_CONFIG_MSB 12 +#define GPIO_PIN13_CONFIG_LSB 11 +#define GPIO_PIN13_CONFIG_MASK 0x00001800 +#define GPIO_PIN13_CONFIG_GET(x) (((x) & GPIO_PIN13_CONFIG_MASK) >> GPIO_PIN13_CONFIG_LSB) +#define GPIO_PIN13_CONFIG_SET(x) (((x) << GPIO_PIN13_CONFIG_LSB) & GPIO_PIN13_CONFIG_MASK) +#define GPIO_PIN13_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN13_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN13_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN13_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN13_WAKEUP_ENABLE_MASK) >> GPIO_PIN13_WAKEUP_ENABLE_LSB) +#define GPIO_PIN13_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN13_WAKEUP_ENABLE_LSB) & GPIO_PIN13_WAKEUP_ENABLE_MASK) +#define GPIO_PIN13_INT_TYPE_MSB 9 +#define GPIO_PIN13_INT_TYPE_LSB 7 +#define GPIO_PIN13_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN13_INT_TYPE_GET(x) (((x) & GPIO_PIN13_INT_TYPE_MASK) >> GPIO_PIN13_INT_TYPE_LSB) +#define GPIO_PIN13_INT_TYPE_SET(x) (((x) << GPIO_PIN13_INT_TYPE_LSB) & GPIO_PIN13_INT_TYPE_MASK) +#define GPIO_PIN13_PAD_DRIVER_MSB 2 +#define GPIO_PIN13_PAD_DRIVER_LSB 2 +#define GPIO_PIN13_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN13_PAD_DRIVER_GET(x) (((x) & GPIO_PIN13_PAD_DRIVER_MASK) >> GPIO_PIN13_PAD_DRIVER_LSB) +#define GPIO_PIN13_PAD_DRIVER_SET(x) (((x) << GPIO_PIN13_PAD_DRIVER_LSB) & GPIO_PIN13_PAD_DRIVER_MASK) +#define GPIO_PIN13_SOURCE_MSB 0 +#define GPIO_PIN13_SOURCE_LSB 0 +#define GPIO_PIN13_SOURCE_MASK 0x00000001 +#define GPIO_PIN13_SOURCE_GET(x) (((x) & GPIO_PIN13_SOURCE_MASK) >> GPIO_PIN13_SOURCE_LSB) +#define GPIO_PIN13_SOURCE_SET(x) (((x) << GPIO_PIN13_SOURCE_LSB) & GPIO_PIN13_SOURCE_MASK) + +#define GPIO_PIN14_ADDRESS 0x00000060 +#define GPIO_PIN14_OFFSET 0x00000060 +#define GPIO_PIN14_CONFIG_MSB 12 +#define GPIO_PIN14_CONFIG_LSB 11 +#define GPIO_PIN14_CONFIG_MASK 0x00001800 +#define GPIO_PIN14_CONFIG_GET(x) (((x) & GPIO_PIN14_CONFIG_MASK) >> GPIO_PIN14_CONFIG_LSB) +#define GPIO_PIN14_CONFIG_SET(x) (((x) << GPIO_PIN14_CONFIG_LSB) & GPIO_PIN14_CONFIG_MASK) +#define GPIO_PIN14_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN14_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN14_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN14_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN14_WAKEUP_ENABLE_MASK) >> GPIO_PIN14_WAKEUP_ENABLE_LSB) +#define GPIO_PIN14_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN14_WAKEUP_ENABLE_LSB) & GPIO_PIN14_WAKEUP_ENABLE_MASK) +#define GPIO_PIN14_INT_TYPE_MSB 9 +#define GPIO_PIN14_INT_TYPE_LSB 7 +#define GPIO_PIN14_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN14_INT_TYPE_GET(x) (((x) & GPIO_PIN14_INT_TYPE_MASK) >> GPIO_PIN14_INT_TYPE_LSB) +#define GPIO_PIN14_INT_TYPE_SET(x) (((x) << GPIO_PIN14_INT_TYPE_LSB) & GPIO_PIN14_INT_TYPE_MASK) +#define GPIO_PIN14_PAD_DRIVER_MSB 2 +#define GPIO_PIN14_PAD_DRIVER_LSB 2 +#define GPIO_PIN14_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN14_PAD_DRIVER_GET(x) (((x) & GPIO_PIN14_PAD_DRIVER_MASK) >> GPIO_PIN14_PAD_DRIVER_LSB) +#define GPIO_PIN14_PAD_DRIVER_SET(x) (((x) << GPIO_PIN14_PAD_DRIVER_LSB) & GPIO_PIN14_PAD_DRIVER_MASK) +#define GPIO_PIN14_SOURCE_MSB 0 +#define GPIO_PIN14_SOURCE_LSB 0 +#define GPIO_PIN14_SOURCE_MASK 0x00000001 +#define GPIO_PIN14_SOURCE_GET(x) (((x) & GPIO_PIN14_SOURCE_MASK) >> GPIO_PIN14_SOURCE_LSB) +#define GPIO_PIN14_SOURCE_SET(x) (((x) << GPIO_PIN14_SOURCE_LSB) & GPIO_PIN14_SOURCE_MASK) + +#define GPIO_PIN15_ADDRESS 0x00000064 +#define GPIO_PIN15_OFFSET 0x00000064 +#define GPIO_PIN15_CONFIG_MSB 12 +#define GPIO_PIN15_CONFIG_LSB 11 +#define GPIO_PIN15_CONFIG_MASK 0x00001800 +#define GPIO_PIN15_CONFIG_GET(x) (((x) & GPIO_PIN15_CONFIG_MASK) >> GPIO_PIN15_CONFIG_LSB) +#define GPIO_PIN15_CONFIG_SET(x) (((x) << GPIO_PIN15_CONFIG_LSB) & GPIO_PIN15_CONFIG_MASK) +#define GPIO_PIN15_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN15_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN15_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN15_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN15_WAKEUP_ENABLE_MASK) >> GPIO_PIN15_WAKEUP_ENABLE_LSB) +#define GPIO_PIN15_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN15_WAKEUP_ENABLE_LSB) & GPIO_PIN15_WAKEUP_ENABLE_MASK) +#define GPIO_PIN15_INT_TYPE_MSB 9 +#define GPIO_PIN15_INT_TYPE_LSB 7 +#define GPIO_PIN15_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN15_INT_TYPE_GET(x) (((x) & GPIO_PIN15_INT_TYPE_MASK) >> GPIO_PIN15_INT_TYPE_LSB) +#define GPIO_PIN15_INT_TYPE_SET(x) (((x) << GPIO_PIN15_INT_TYPE_LSB) & GPIO_PIN15_INT_TYPE_MASK) +#define GPIO_PIN15_PAD_DRIVER_MSB 2 +#define GPIO_PIN15_PAD_DRIVER_LSB 2 +#define GPIO_PIN15_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN15_PAD_DRIVER_GET(x) (((x) & GPIO_PIN15_PAD_DRIVER_MASK) >> GPIO_PIN15_PAD_DRIVER_LSB) +#define GPIO_PIN15_PAD_DRIVER_SET(x) (((x) << GPIO_PIN15_PAD_DRIVER_LSB) & GPIO_PIN15_PAD_DRIVER_MASK) +#define GPIO_PIN15_SOURCE_MSB 0 +#define GPIO_PIN15_SOURCE_LSB 0 +#define GPIO_PIN15_SOURCE_MASK 0x00000001 +#define GPIO_PIN15_SOURCE_GET(x) (((x) & GPIO_PIN15_SOURCE_MASK) >> GPIO_PIN15_SOURCE_LSB) +#define GPIO_PIN15_SOURCE_SET(x) (((x) << GPIO_PIN15_SOURCE_LSB) & GPIO_PIN15_SOURCE_MASK) + +#define GPIO_PIN16_ADDRESS 0x00000068 +#define GPIO_PIN16_OFFSET 0x00000068 +#define GPIO_PIN16_CONFIG_MSB 12 +#define GPIO_PIN16_CONFIG_LSB 11 +#define GPIO_PIN16_CONFIG_MASK 0x00001800 +#define GPIO_PIN16_CONFIG_GET(x) (((x) & GPIO_PIN16_CONFIG_MASK) >> GPIO_PIN16_CONFIG_LSB) +#define GPIO_PIN16_CONFIG_SET(x) (((x) << GPIO_PIN16_CONFIG_LSB) & GPIO_PIN16_CONFIG_MASK) +#define GPIO_PIN16_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN16_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN16_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN16_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN16_WAKEUP_ENABLE_MASK) >> GPIO_PIN16_WAKEUP_ENABLE_LSB) +#define GPIO_PIN16_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN16_WAKEUP_ENABLE_LSB) & GPIO_PIN16_WAKEUP_ENABLE_MASK) +#define GPIO_PIN16_INT_TYPE_MSB 9 +#define GPIO_PIN16_INT_TYPE_LSB 7 +#define GPIO_PIN16_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN16_INT_TYPE_GET(x) (((x) & GPIO_PIN16_INT_TYPE_MASK) >> GPIO_PIN16_INT_TYPE_LSB) +#define GPIO_PIN16_INT_TYPE_SET(x) (((x) << GPIO_PIN16_INT_TYPE_LSB) & GPIO_PIN16_INT_TYPE_MASK) +#define GPIO_PIN16_PAD_DRIVER_MSB 2 +#define GPIO_PIN16_PAD_DRIVER_LSB 2 +#define GPIO_PIN16_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN16_PAD_DRIVER_GET(x) (((x) & GPIO_PIN16_PAD_DRIVER_MASK) >> GPIO_PIN16_PAD_DRIVER_LSB) +#define GPIO_PIN16_PAD_DRIVER_SET(x) (((x) << GPIO_PIN16_PAD_DRIVER_LSB) & GPIO_PIN16_PAD_DRIVER_MASK) +#define GPIO_PIN16_SOURCE_MSB 0 +#define GPIO_PIN16_SOURCE_LSB 0 +#define GPIO_PIN16_SOURCE_MASK 0x00000001 +#define GPIO_PIN16_SOURCE_GET(x) (((x) & GPIO_PIN16_SOURCE_MASK) >> GPIO_PIN16_SOURCE_LSB) +#define GPIO_PIN16_SOURCE_SET(x) (((x) << GPIO_PIN16_SOURCE_LSB) & GPIO_PIN16_SOURCE_MASK) + +#define GPIO_PIN17_ADDRESS 0x0000006c +#define GPIO_PIN17_OFFSET 0x0000006c +#define GPIO_PIN17_CONFIG_MSB 12 +#define GPIO_PIN17_CONFIG_LSB 11 +#define GPIO_PIN17_CONFIG_MASK 0x00001800 +#define GPIO_PIN17_CONFIG_GET(x) (((x) & GPIO_PIN17_CONFIG_MASK) >> GPIO_PIN17_CONFIG_LSB) +#define GPIO_PIN17_CONFIG_SET(x) (((x) << GPIO_PIN17_CONFIG_LSB) & GPIO_PIN17_CONFIG_MASK) +#define GPIO_PIN17_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN17_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN17_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN17_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN17_WAKEUP_ENABLE_MASK) >> GPIO_PIN17_WAKEUP_ENABLE_LSB) +#define GPIO_PIN17_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN17_WAKEUP_ENABLE_LSB) & GPIO_PIN17_WAKEUP_ENABLE_MASK) +#define GPIO_PIN17_INT_TYPE_MSB 9 +#define GPIO_PIN17_INT_TYPE_LSB 7 +#define GPIO_PIN17_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN17_INT_TYPE_GET(x) (((x) & GPIO_PIN17_INT_TYPE_MASK) >> GPIO_PIN17_INT_TYPE_LSB) +#define GPIO_PIN17_INT_TYPE_SET(x) (((x) << GPIO_PIN17_INT_TYPE_LSB) & GPIO_PIN17_INT_TYPE_MASK) +#define GPIO_PIN17_PAD_DRIVER_MSB 2 +#define GPIO_PIN17_PAD_DRIVER_LSB 2 +#define GPIO_PIN17_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN17_PAD_DRIVER_GET(x) (((x) & GPIO_PIN17_PAD_DRIVER_MASK) >> GPIO_PIN17_PAD_DRIVER_LSB) +#define GPIO_PIN17_PAD_DRIVER_SET(x) (((x) << GPIO_PIN17_PAD_DRIVER_LSB) & GPIO_PIN17_PAD_DRIVER_MASK) +#define GPIO_PIN17_SOURCE_MSB 0 +#define GPIO_PIN17_SOURCE_LSB 0 +#define GPIO_PIN17_SOURCE_MASK 0x00000001 +#define GPIO_PIN17_SOURCE_GET(x) (((x) & GPIO_PIN17_SOURCE_MASK) >> GPIO_PIN17_SOURCE_LSB) +#define GPIO_PIN17_SOURCE_SET(x) (((x) << GPIO_PIN17_SOURCE_LSB) & GPIO_PIN17_SOURCE_MASK) + +#define SDIO_PIN_ADDRESS 0x00000070 +#define SDIO_PIN_OFFSET 0x00000070 +#define SDIO_PIN_PAD_PULL_MSB 3 +#define SDIO_PIN_PAD_PULL_LSB 2 +#define SDIO_PIN_PAD_PULL_MASK 0x0000000c +#define SDIO_PIN_PAD_PULL_GET(x) (((x) & SDIO_PIN_PAD_PULL_MASK) >> SDIO_PIN_PAD_PULL_LSB) +#define SDIO_PIN_PAD_PULL_SET(x) (((x) << SDIO_PIN_PAD_PULL_LSB) & SDIO_PIN_PAD_PULL_MASK) +#define SDIO_PIN_PAD_STRENGTH_MSB 1 +#define SDIO_PIN_PAD_STRENGTH_LSB 0 +#define SDIO_PIN_PAD_STRENGTH_MASK 0x00000003 +#define SDIO_PIN_PAD_STRENGTH_GET(x) (((x) & SDIO_PIN_PAD_STRENGTH_MASK) >> SDIO_PIN_PAD_STRENGTH_LSB) +#define SDIO_PIN_PAD_STRENGTH_SET(x) (((x) << SDIO_PIN_PAD_STRENGTH_LSB) & SDIO_PIN_PAD_STRENGTH_MASK) + +#define CLK_REQ_PIN_ADDRESS 0x00000074 +#define CLK_REQ_PIN_OFFSET 0x00000074 +#define CLK_REQ_PIN_ATE_OE_L_MSB 4 +#define CLK_REQ_PIN_ATE_OE_L_LSB 4 +#define CLK_REQ_PIN_ATE_OE_L_MASK 0x00000010 +#define CLK_REQ_PIN_ATE_OE_L_GET(x) (((x) & CLK_REQ_PIN_ATE_OE_L_MASK) >> CLK_REQ_PIN_ATE_OE_L_LSB) +#define CLK_REQ_PIN_ATE_OE_L_SET(x) (((x) << CLK_REQ_PIN_ATE_OE_L_LSB) & CLK_REQ_PIN_ATE_OE_L_MASK) +#define CLK_REQ_PIN_PAD_PULL_MSB 3 +#define CLK_REQ_PIN_PAD_PULL_LSB 2 +#define CLK_REQ_PIN_PAD_PULL_MASK 0x0000000c +#define CLK_REQ_PIN_PAD_PULL_GET(x) (((x) & CLK_REQ_PIN_PAD_PULL_MASK) >> CLK_REQ_PIN_PAD_PULL_LSB) +#define CLK_REQ_PIN_PAD_PULL_SET(x) (((x) << CLK_REQ_PIN_PAD_PULL_LSB) & CLK_REQ_PIN_PAD_PULL_MASK) +#define CLK_REQ_PIN_PAD_STRENGTH_MSB 1 +#define CLK_REQ_PIN_PAD_STRENGTH_LSB 0 +#define CLK_REQ_PIN_PAD_STRENGTH_MASK 0x00000003 +#define CLK_REQ_PIN_PAD_STRENGTH_GET(x) (((x) & CLK_REQ_PIN_PAD_STRENGTH_MASK) >> CLK_REQ_PIN_PAD_STRENGTH_LSB) +#define CLK_REQ_PIN_PAD_STRENGTH_SET(x) (((x) << CLK_REQ_PIN_PAD_STRENGTH_LSB) & CLK_REQ_PIN_PAD_STRENGTH_MASK) + +#define SIGMA_DELTA_ADDRESS 0x00000078 +#define SIGMA_DELTA_OFFSET 0x00000078 +#define SIGMA_DELTA_ENABLE_MSB 16 +#define SIGMA_DELTA_ENABLE_LSB 16 +#define SIGMA_DELTA_ENABLE_MASK 0x00010000 +#define SIGMA_DELTA_ENABLE_GET(x) (((x) & SIGMA_DELTA_ENABLE_MASK) >> SIGMA_DELTA_ENABLE_LSB) +#define SIGMA_DELTA_ENABLE_SET(x) (((x) << SIGMA_DELTA_ENABLE_LSB) & SIGMA_DELTA_ENABLE_MASK) +#define SIGMA_DELTA_PRESCALAR_MSB 15 +#define SIGMA_DELTA_PRESCALAR_LSB 8 +#define SIGMA_DELTA_PRESCALAR_MASK 0x0000ff00 +#define SIGMA_DELTA_PRESCALAR_GET(x) (((x) & SIGMA_DELTA_PRESCALAR_MASK) >> SIGMA_DELTA_PRESCALAR_LSB) +#define SIGMA_DELTA_PRESCALAR_SET(x) (((x) << SIGMA_DELTA_PRESCALAR_LSB) & SIGMA_DELTA_PRESCALAR_MASK) +#define SIGMA_DELTA_TARGET_MSB 7 +#define SIGMA_DELTA_TARGET_LSB 0 +#define SIGMA_DELTA_TARGET_MASK 0x000000ff +#define SIGMA_DELTA_TARGET_GET(x) (((x) & SIGMA_DELTA_TARGET_MASK) >> SIGMA_DELTA_TARGET_LSB) +#define SIGMA_DELTA_TARGET_SET(x) (((x) << SIGMA_DELTA_TARGET_LSB) & SIGMA_DELTA_TARGET_MASK) + +#define DEBUG_CONTROL_ADDRESS 0x0000007c +#define DEBUG_CONTROL_OFFSET 0x0000007c +#define DEBUG_CONTROL_OBS_OE_L_MSB 1 +#define DEBUG_CONTROL_OBS_OE_L_LSB 1 +#define DEBUG_CONTROL_OBS_OE_L_MASK 0x00000002 +#define DEBUG_CONTROL_OBS_OE_L_GET(x) (((x) & DEBUG_CONTROL_OBS_OE_L_MASK) >> DEBUG_CONTROL_OBS_OE_L_LSB) +#define DEBUG_CONTROL_OBS_OE_L_SET(x) (((x) << DEBUG_CONTROL_OBS_OE_L_LSB) & DEBUG_CONTROL_OBS_OE_L_MASK) +#define DEBUG_CONTROL_ENABLE_MSB 0 +#define DEBUG_CONTROL_ENABLE_LSB 0 +#define DEBUG_CONTROL_ENABLE_MASK 0x00000001 +#define DEBUG_CONTROL_ENABLE_GET(x) (((x) & DEBUG_CONTROL_ENABLE_MASK) >> DEBUG_CONTROL_ENABLE_LSB) +#define DEBUG_CONTROL_ENABLE_SET(x) (((x) << DEBUG_CONTROL_ENABLE_LSB) & DEBUG_CONTROL_ENABLE_MASK) + +#define DEBUG_INPUT_SEL_ADDRESS 0x00000080 +#define DEBUG_INPUT_SEL_OFFSET 0x00000080 +#define DEBUG_INPUT_SEL_SRC_MSB 3 +#define DEBUG_INPUT_SEL_SRC_LSB 0 +#define DEBUG_INPUT_SEL_SRC_MASK 0x0000000f +#define DEBUG_INPUT_SEL_SRC_GET(x) (((x) & DEBUG_INPUT_SEL_SRC_MASK) >> DEBUG_INPUT_SEL_SRC_LSB) +#define DEBUG_INPUT_SEL_SRC_SET(x) (((x) << DEBUG_INPUT_SEL_SRC_LSB) & DEBUG_INPUT_SEL_SRC_MASK) + +#define DEBUG_OUT_ADDRESS 0x00000084 +#define DEBUG_OUT_OFFSET 0x00000084 +#define DEBUG_OUT_DATA_MSB 17 +#define DEBUG_OUT_DATA_LSB 0 +#define DEBUG_OUT_DATA_MASK 0x0003ffff +#define DEBUG_OUT_DATA_GET(x) (((x) & DEBUG_OUT_DATA_MASK) >> DEBUG_OUT_DATA_LSB) +#define DEBUG_OUT_DATA_SET(x) (((x) << DEBUG_OUT_DATA_LSB) & DEBUG_OUT_DATA_MASK) + +#define LA_CONTROL_ADDRESS 0x00000088 +#define LA_CONTROL_OFFSET 0x00000088 +#define LA_CONTROL_RUN_MSB 1 +#define LA_CONTROL_RUN_LSB 1 +#define LA_CONTROL_RUN_MASK 0x00000002 +#define LA_CONTROL_RUN_GET(x) (((x) & LA_CONTROL_RUN_MASK) >> LA_CONTROL_RUN_LSB) +#define LA_CONTROL_RUN_SET(x) (((x) << LA_CONTROL_RUN_LSB) & LA_CONTROL_RUN_MASK) +#define LA_CONTROL_TRIGGERED_MSB 0 +#define LA_CONTROL_TRIGGERED_LSB 0 +#define LA_CONTROL_TRIGGERED_MASK 0x00000001 +#define LA_CONTROL_TRIGGERED_GET(x) (((x) & LA_CONTROL_TRIGGERED_MASK) >> LA_CONTROL_TRIGGERED_LSB) +#define LA_CONTROL_TRIGGERED_SET(x) (((x) << LA_CONTROL_TRIGGERED_LSB) & LA_CONTROL_TRIGGERED_MASK) + +#define LA_CLOCK_ADDRESS 0x0000008c +#define LA_CLOCK_OFFSET 0x0000008c +#define LA_CLOCK_DIV_MSB 7 +#define LA_CLOCK_DIV_LSB 0 +#define LA_CLOCK_DIV_MASK 0x000000ff +#define LA_CLOCK_DIV_GET(x) (((x) & LA_CLOCK_DIV_MASK) >> LA_CLOCK_DIV_LSB) +#define LA_CLOCK_DIV_SET(x) (((x) << LA_CLOCK_DIV_LSB) & LA_CLOCK_DIV_MASK) + +#define LA_STATUS_ADDRESS 0x00000090 +#define LA_STATUS_OFFSET 0x00000090 +#define LA_STATUS_INTERRUPT_MSB 0 +#define LA_STATUS_INTERRUPT_LSB 0 +#define LA_STATUS_INTERRUPT_MASK 0x00000001 +#define LA_STATUS_INTERRUPT_GET(x) (((x) & LA_STATUS_INTERRUPT_MASK) >> LA_STATUS_INTERRUPT_LSB) +#define LA_STATUS_INTERRUPT_SET(x) (((x) << LA_STATUS_INTERRUPT_LSB) & LA_STATUS_INTERRUPT_MASK) + +#define LA_TRIGGER_SAMPLE_ADDRESS 0x00000094 +#define LA_TRIGGER_SAMPLE_OFFSET 0x00000094 +#define LA_TRIGGER_SAMPLE_COUNT_MSB 15 +#define LA_TRIGGER_SAMPLE_COUNT_LSB 0 +#define LA_TRIGGER_SAMPLE_COUNT_MASK 0x0000ffff +#define LA_TRIGGER_SAMPLE_COUNT_GET(x) (((x) & LA_TRIGGER_SAMPLE_COUNT_MASK) >> LA_TRIGGER_SAMPLE_COUNT_LSB) +#define LA_TRIGGER_SAMPLE_COUNT_SET(x) (((x) << LA_TRIGGER_SAMPLE_COUNT_LSB) & LA_TRIGGER_SAMPLE_COUNT_MASK) + +#define LA_TRIGGER_POSITION_ADDRESS 0x00000098 +#define LA_TRIGGER_POSITION_OFFSET 0x00000098 +#define LA_TRIGGER_POSITION_VALUE_MSB 15 +#define LA_TRIGGER_POSITION_VALUE_LSB 0 +#define LA_TRIGGER_POSITION_VALUE_MASK 0x0000ffff +#define LA_TRIGGER_POSITION_VALUE_GET(x) (((x) & LA_TRIGGER_POSITION_VALUE_MASK) >> LA_TRIGGER_POSITION_VALUE_LSB) +#define LA_TRIGGER_POSITION_VALUE_SET(x) (((x) << LA_TRIGGER_POSITION_VALUE_LSB) & LA_TRIGGER_POSITION_VALUE_MASK) + +#define LA_PRE_TRIGGER_ADDRESS 0x0000009c +#define LA_PRE_TRIGGER_OFFSET 0x0000009c +#define LA_PRE_TRIGGER_COUNT_MSB 15 +#define LA_PRE_TRIGGER_COUNT_LSB 0 +#define LA_PRE_TRIGGER_COUNT_MASK 0x0000ffff +#define LA_PRE_TRIGGER_COUNT_GET(x) (((x) & LA_PRE_TRIGGER_COUNT_MASK) >> LA_PRE_TRIGGER_COUNT_LSB) +#define LA_PRE_TRIGGER_COUNT_SET(x) (((x) << LA_PRE_TRIGGER_COUNT_LSB) & LA_PRE_TRIGGER_COUNT_MASK) + +#define LA_POST_TRIGGER_ADDRESS 0x000000a0 +#define LA_POST_TRIGGER_OFFSET 0x000000a0 +#define LA_POST_TRIGGER_COUNT_MSB 15 +#define LA_POST_TRIGGER_COUNT_LSB 0 +#define LA_POST_TRIGGER_COUNT_MASK 0x0000ffff +#define LA_POST_TRIGGER_COUNT_GET(x) (((x) & LA_POST_TRIGGER_COUNT_MASK) >> LA_POST_TRIGGER_COUNT_LSB) +#define LA_POST_TRIGGER_COUNT_SET(x) (((x) << LA_POST_TRIGGER_COUNT_LSB) & LA_POST_TRIGGER_COUNT_MASK) + +#define LA_FILTER_CONTROL_ADDRESS 0x000000a4 +#define LA_FILTER_CONTROL_OFFSET 0x000000a4 +#define LA_FILTER_CONTROL_DELTA_MSB 0 +#define LA_FILTER_CONTROL_DELTA_LSB 0 +#define LA_FILTER_CONTROL_DELTA_MASK 0x00000001 +#define LA_FILTER_CONTROL_DELTA_GET(x) (((x) & LA_FILTER_CONTROL_DELTA_MASK) >> LA_FILTER_CONTROL_DELTA_LSB) +#define LA_FILTER_CONTROL_DELTA_SET(x) (((x) << LA_FILTER_CONTROL_DELTA_LSB) & LA_FILTER_CONTROL_DELTA_MASK) + +#define LA_FILTER_DATA_ADDRESS 0x000000a8 +#define LA_FILTER_DATA_OFFSET 0x000000a8 +#define LA_FILTER_DATA_MATCH_MSB 17 +#define LA_FILTER_DATA_MATCH_LSB 0 +#define LA_FILTER_DATA_MATCH_MASK 0x0003ffff +#define LA_FILTER_DATA_MATCH_GET(x) (((x) & LA_FILTER_DATA_MATCH_MASK) >> LA_FILTER_DATA_MATCH_LSB) +#define LA_FILTER_DATA_MATCH_SET(x) (((x) << LA_FILTER_DATA_MATCH_LSB) & LA_FILTER_DATA_MATCH_MASK) + +#define LA_FILTER_WILDCARD_ADDRESS 0x000000ac +#define LA_FILTER_WILDCARD_OFFSET 0x000000ac +#define LA_FILTER_WILDCARD_MATCH_MSB 17 +#define LA_FILTER_WILDCARD_MATCH_LSB 0 +#define LA_FILTER_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_FILTER_WILDCARD_MATCH_GET(x) (((x) & LA_FILTER_WILDCARD_MATCH_MASK) >> LA_FILTER_WILDCARD_MATCH_LSB) +#define LA_FILTER_WILDCARD_MATCH_SET(x) (((x) << LA_FILTER_WILDCARD_MATCH_LSB) & LA_FILTER_WILDCARD_MATCH_MASK) + +#define LA_TRIGGERA_DATA_ADDRESS 0x000000b0 +#define LA_TRIGGERA_DATA_OFFSET 0x000000b0 +#define LA_TRIGGERA_DATA_MATCH_MSB 17 +#define LA_TRIGGERA_DATA_MATCH_LSB 0 +#define LA_TRIGGERA_DATA_MATCH_MASK 0x0003ffff +#define LA_TRIGGERA_DATA_MATCH_GET(x) (((x) & LA_TRIGGERA_DATA_MATCH_MASK) >> LA_TRIGGERA_DATA_MATCH_LSB) +#define LA_TRIGGERA_DATA_MATCH_SET(x) (((x) << LA_TRIGGERA_DATA_MATCH_LSB) & LA_TRIGGERA_DATA_MATCH_MASK) + +#define LA_TRIGGERA_WILDCARD_ADDRESS 0x000000b4 +#define LA_TRIGGERA_WILDCARD_OFFSET 0x000000b4 +#define LA_TRIGGERA_WILDCARD_MATCH_MSB 17 +#define LA_TRIGGERA_WILDCARD_MATCH_LSB 0 +#define LA_TRIGGERA_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_TRIGGERA_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERA_WILDCARD_MATCH_MASK) >> LA_TRIGGERA_WILDCARD_MATCH_LSB) +#define LA_TRIGGERA_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERA_WILDCARD_MATCH_LSB) & LA_TRIGGERA_WILDCARD_MATCH_MASK) + +#define LA_TRIGGERB_DATA_ADDRESS 0x000000b8 +#define LA_TRIGGERB_DATA_OFFSET 0x000000b8 +#define LA_TRIGGERB_DATA_MATCH_MSB 17 +#define LA_TRIGGERB_DATA_MATCH_LSB 0 +#define LA_TRIGGERB_DATA_MATCH_MASK 0x0003ffff +#define LA_TRIGGERB_DATA_MATCH_GET(x) (((x) & LA_TRIGGERB_DATA_MATCH_MASK) >> LA_TRIGGERB_DATA_MATCH_LSB) +#define LA_TRIGGERB_DATA_MATCH_SET(x) (((x) << LA_TRIGGERB_DATA_MATCH_LSB) & LA_TRIGGERB_DATA_MATCH_MASK) + +#define LA_TRIGGERB_WILDCARD_ADDRESS 0x000000bc +#define LA_TRIGGERB_WILDCARD_OFFSET 0x000000bc +#define LA_TRIGGERB_WILDCARD_MATCH_MSB 17 +#define LA_TRIGGERB_WILDCARD_MATCH_LSB 0 +#define LA_TRIGGERB_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_TRIGGERB_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERB_WILDCARD_MATCH_MASK) >> LA_TRIGGERB_WILDCARD_MATCH_LSB) +#define LA_TRIGGERB_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERB_WILDCARD_MATCH_LSB) & LA_TRIGGERB_WILDCARD_MATCH_MASK) + +#define LA_TRIGGER_ADDRESS 0x000000c0 +#define LA_TRIGGER_OFFSET 0x000000c0 +#define LA_TRIGGER_EVENT_MSB 2 +#define LA_TRIGGER_EVENT_LSB 0 +#define LA_TRIGGER_EVENT_MASK 0x00000007 +#define LA_TRIGGER_EVENT_GET(x) (((x) & LA_TRIGGER_EVENT_MASK) >> LA_TRIGGER_EVENT_LSB) +#define LA_TRIGGER_EVENT_SET(x) (((x) << LA_TRIGGER_EVENT_LSB) & LA_TRIGGER_EVENT_MASK) + +#define LA_FIFO_ADDRESS 0x000000c4 +#define LA_FIFO_OFFSET 0x000000c4 +#define LA_FIFO_FULL_MSB 1 +#define LA_FIFO_FULL_LSB 1 +#define LA_FIFO_FULL_MASK 0x00000002 +#define LA_FIFO_FULL_GET(x) (((x) & LA_FIFO_FULL_MASK) >> LA_FIFO_FULL_LSB) +#define LA_FIFO_FULL_SET(x) (((x) << LA_FIFO_FULL_LSB) & LA_FIFO_FULL_MASK) +#define LA_FIFO_EMPTY_MSB 0 +#define LA_FIFO_EMPTY_LSB 0 +#define LA_FIFO_EMPTY_MASK 0x00000001 +#define LA_FIFO_EMPTY_GET(x) (((x) & LA_FIFO_EMPTY_MASK) >> LA_FIFO_EMPTY_LSB) +#define LA_FIFO_EMPTY_SET(x) (((x) << LA_FIFO_EMPTY_LSB) & LA_FIFO_EMPTY_MASK) + +#define LA_ADDRESS 0x000000c8 +#define LA_OFFSET 0x000000c8 +#define LA_DATA_MSB 17 +#define LA_DATA_LSB 0 +#define LA_DATA_MASK 0x0003ffff +#define LA_DATA_GET(x) (((x) & LA_DATA_MASK) >> LA_DATA_LSB) +#define LA_DATA_SET(x) (((x) << LA_DATA_LSB) & LA_DATA_MASK) + +#define ANT_PIN_ADDRESS 0x000000d0 +#define ANT_PIN_OFFSET 0x000000d0 +#define ANT_PIN_PAD_PULL_MSB 3 +#define ANT_PIN_PAD_PULL_LSB 2 +#define ANT_PIN_PAD_PULL_MASK 0x0000000c +#define ANT_PIN_PAD_PULL_GET(x) (((x) & ANT_PIN_PAD_PULL_MASK) >> ANT_PIN_PAD_PULL_LSB) +#define ANT_PIN_PAD_PULL_SET(x) (((x) << ANT_PIN_PAD_PULL_LSB) & ANT_PIN_PAD_PULL_MASK) +#define ANT_PIN_PAD_STRENGTH_MSB 1 +#define ANT_PIN_PAD_STRENGTH_LSB 0 +#define ANT_PIN_PAD_STRENGTH_MASK 0x00000003 +#define ANT_PIN_PAD_STRENGTH_GET(x) (((x) & ANT_PIN_PAD_STRENGTH_MASK) >> ANT_PIN_PAD_STRENGTH_LSB) +#define ANT_PIN_PAD_STRENGTH_SET(x) (((x) << ANT_PIN_PAD_STRENGTH_LSB) & ANT_PIN_PAD_STRENGTH_MASK) + +#define ANTD_PIN_ADDRESS 0x000000d4 +#define ANTD_PIN_OFFSET 0x000000d4 +#define ANTD_PIN_PAD_PULL_MSB 1 +#define ANTD_PIN_PAD_PULL_LSB 0 +#define ANTD_PIN_PAD_PULL_MASK 0x00000003 +#define ANTD_PIN_PAD_PULL_GET(x) (((x) & ANTD_PIN_PAD_PULL_MASK) >> ANTD_PIN_PAD_PULL_LSB) +#define ANTD_PIN_PAD_PULL_SET(x) (((x) << ANTD_PIN_PAD_PULL_LSB) & ANTD_PIN_PAD_PULL_MASK) + +#define GPIO_PIN_ADDRESS 0x000000d8 +#define GPIO_PIN_OFFSET 0x000000d8 +#define GPIO_PIN_PAD_PULL_MSB 3 +#define GPIO_PIN_PAD_PULL_LSB 2 +#define GPIO_PIN_PAD_PULL_MASK 0x0000000c +#define GPIO_PIN_PAD_PULL_GET(x) (((x) & GPIO_PIN_PAD_PULL_MASK) >> GPIO_PIN_PAD_PULL_LSB) +#define GPIO_PIN_PAD_PULL_SET(x) (((x) << GPIO_PIN_PAD_PULL_LSB) & GPIO_PIN_PAD_PULL_MASK) +#define GPIO_PIN_PAD_STRENGTH_MSB 1 +#define GPIO_PIN_PAD_STRENGTH_LSB 0 +#define GPIO_PIN_PAD_STRENGTH_MASK 0x00000003 +#define GPIO_PIN_PAD_STRENGTH_GET(x) (((x) & GPIO_PIN_PAD_STRENGTH_MASK) >> GPIO_PIN_PAD_STRENGTH_LSB) +#define GPIO_PIN_PAD_STRENGTH_SET(x) (((x) << GPIO_PIN_PAD_STRENGTH_LSB) & GPIO_PIN_PAD_STRENGTH_MASK) + +#define GPIO_H_PIN_ADDRESS 0x000000dc +#define GPIO_H_PIN_OFFSET 0x000000dc +#define GPIO_H_PIN_PAD_PULL_MSB 1 +#define GPIO_H_PIN_PAD_PULL_LSB 0 +#define GPIO_H_PIN_PAD_PULL_MASK 0x00000003 +#define GPIO_H_PIN_PAD_PULL_GET(x) (((x) & GPIO_H_PIN_PAD_PULL_MASK) >> GPIO_H_PIN_PAD_PULL_LSB) +#define GPIO_H_PIN_PAD_PULL_SET(x) (((x) << GPIO_H_PIN_PAD_PULL_LSB) & GPIO_H_PIN_PAD_PULL_MASK) + +#define BT_PIN_ADDRESS 0x000000e0 +#define BT_PIN_OFFSET 0x000000e0 +#define BT_PIN_PAD_PULL_MSB 3 +#define BT_PIN_PAD_PULL_LSB 2 +#define BT_PIN_PAD_PULL_MASK 0x0000000c +#define BT_PIN_PAD_PULL_GET(x) (((x) & BT_PIN_PAD_PULL_MASK) >> BT_PIN_PAD_PULL_LSB) +#define BT_PIN_PAD_PULL_SET(x) (((x) << BT_PIN_PAD_PULL_LSB) & BT_PIN_PAD_PULL_MASK) +#define BT_PIN_PAD_STRENGTH_MSB 1 +#define BT_PIN_PAD_STRENGTH_LSB 0 +#define BT_PIN_PAD_STRENGTH_MASK 0x00000003 +#define BT_PIN_PAD_STRENGTH_GET(x) (((x) & BT_PIN_PAD_STRENGTH_MASK) >> BT_PIN_PAD_STRENGTH_LSB) +#define BT_PIN_PAD_STRENGTH_SET(x) (((x) << BT_PIN_PAD_STRENGTH_LSB) & BT_PIN_PAD_STRENGTH_MASK) + +#define BT_WLAN_PIN_ADDRESS 0x000000e4 +#define BT_WLAN_PIN_OFFSET 0x000000e4 +#define BT_WLAN_PIN_PAD_PULL_MSB 1 +#define BT_WLAN_PIN_PAD_PULL_LSB 0 +#define BT_WLAN_PIN_PAD_PULL_MASK 0x00000003 +#define BT_WLAN_PIN_PAD_PULL_GET(x) (((x) & BT_WLAN_PIN_PAD_PULL_MASK) >> BT_WLAN_PIN_PAD_PULL_LSB) +#define BT_WLAN_PIN_PAD_PULL_SET(x) (((x) << BT_WLAN_PIN_PAD_PULL_LSB) & BT_WLAN_PIN_PAD_PULL_MASK) + +#define SI_UART_PIN_ADDRESS 0x000000e8 +#define SI_UART_PIN_OFFSET 0x000000e8 +#define SI_UART_PIN_PAD_PULL_MSB 3 +#define SI_UART_PIN_PAD_PULL_LSB 2 +#define SI_UART_PIN_PAD_PULL_MASK 0x0000000c +#define SI_UART_PIN_PAD_PULL_GET(x) (((x) & SI_UART_PIN_PAD_PULL_MASK) >> SI_UART_PIN_PAD_PULL_LSB) +#define SI_UART_PIN_PAD_PULL_SET(x) (((x) << SI_UART_PIN_PAD_PULL_LSB) & SI_UART_PIN_PAD_PULL_MASK) +#define SI_UART_PIN_PAD_STRENGTH_MSB 1 +#define SI_UART_PIN_PAD_STRENGTH_LSB 0 +#define SI_UART_PIN_PAD_STRENGTH_MASK 0x00000003 +#define SI_UART_PIN_PAD_STRENGTH_GET(x) (((x) & SI_UART_PIN_PAD_STRENGTH_MASK) >> SI_UART_PIN_PAD_STRENGTH_LSB) +#define SI_UART_PIN_PAD_STRENGTH_SET(x) (((x) << SI_UART_PIN_PAD_STRENGTH_LSB) & SI_UART_PIN_PAD_STRENGTH_MASK) + +#define CLK32K_PIN_ADDRESS 0x000000ec +#define CLK32K_PIN_OFFSET 0x000000ec +#define CLK32K_PIN_PAD_PULL_MSB 1 +#define CLK32K_PIN_PAD_PULL_LSB 0 +#define CLK32K_PIN_PAD_PULL_MASK 0x00000003 +#define CLK32K_PIN_PAD_PULL_GET(x) (((x) & CLK32K_PIN_PAD_PULL_MASK) >> CLK32K_PIN_PAD_PULL_LSB) +#define CLK32K_PIN_PAD_PULL_SET(x) (((x) << CLK32K_PIN_PAD_PULL_LSB) & CLK32K_PIN_PAD_PULL_MASK) + +#define RESET_TUPLE_STATUS_ADDRESS 0x000000f0 +#define RESET_TUPLE_STATUS_OFFSET 0x000000f0 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7 +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0 +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct gpio_reg_reg_s { + volatile unsigned int gpio_out; + volatile unsigned int gpio_out_w1ts; + volatile unsigned int gpio_out_w1tc; + volatile unsigned int gpio_enable; + volatile unsigned int gpio_enable_w1ts; + volatile unsigned int gpio_enable_w1tc; + volatile unsigned int gpio_in; + volatile unsigned int gpio_status; + volatile unsigned int gpio_status_w1ts; + volatile unsigned int gpio_status_w1tc; + volatile unsigned int gpio_pin0; + volatile unsigned int gpio_pin1; + volatile unsigned int gpio_pin2; + volatile unsigned int gpio_pin3; + volatile unsigned int gpio_pin4; + volatile unsigned int gpio_pin5; + volatile unsigned int gpio_pin6; + volatile unsigned int gpio_pin7; + volatile unsigned int gpio_pin8; + volatile unsigned int gpio_pin9; + volatile unsigned int gpio_pin10; + volatile unsigned int gpio_pin11; + volatile unsigned int gpio_pin12; + volatile unsigned int gpio_pin13; + volatile unsigned int gpio_pin14; + volatile unsigned int gpio_pin15; + volatile unsigned int gpio_pin16; + volatile unsigned int gpio_pin17; + volatile unsigned int sdio_pin; + volatile unsigned int clk_req_pin; + volatile unsigned int sigma_delta; + volatile unsigned int debug_control; + volatile unsigned int debug_input_sel; + volatile unsigned int debug_out; + volatile unsigned int la_control; + volatile unsigned int la_clock; + volatile unsigned int la_status; + volatile unsigned int la_trigger_sample; + volatile unsigned int la_trigger_position; + volatile unsigned int la_pre_trigger; + volatile unsigned int la_post_trigger; + volatile unsigned int la_filter_control; + volatile unsigned int la_filter_data; + volatile unsigned int la_filter_wildcard; + volatile unsigned int la_triggera_data; + volatile unsigned int la_triggera_wildcard; + volatile unsigned int la_triggerb_data; + volatile unsigned int la_triggerb_wildcard; + volatile unsigned int la_trigger; + volatile unsigned int la_fifo; + volatile unsigned int la[2]; + volatile unsigned int ant_pin; + volatile unsigned int antd_pin; + volatile unsigned int gpio_pin; + volatile unsigned int gpio_h_pin; + volatile unsigned int bt_pin; + volatile unsigned int bt_wlan_pin; + volatile unsigned int si_uart_pin; + volatile unsigned int clk32k_pin; + volatile unsigned int reset_tuple_status; +} gpio_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _GPIO_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/hif.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/hif.c --- linux-2.6.26/drivers/net/wireless/ath6k/hif.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/hif.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,737 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// HIF layer reference implementation for Linux Native MMC stack +// +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include +/* by default setup a bounce buffer for the data packets, if the underlying host controller driver + does not use DMA you may be able to skip this step and save the memory allocation and transfer time */ +#define HIF_USE_DMA_BOUNCE_BUFFER 1 +#include "hif_internal.h" + + +static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id); +static void hifDeviceRemoved(struct sdio_func *func); +static HIF_DEVICE *addHifDevice(struct sdio_func *func); +static HIF_DEVICE *getHifDevice(struct sdio_func *func); +static void delHifDevice(HIF_DEVICE * device); + + + +/* ------ Static Variables ------ */ +static const struct sdio_device_id ar6k_id_table[] = { + { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x0)) }, + { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x1)) }, + { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0)) }, + { /* null */ }, +}; +MODULE_DEVICE_TABLE(sdio, ar6k_id_table); + +static struct sdio_driver ar6k_driver = { + .name = "ar6k_wlan", + .id_table = ar6k_id_table, + .probe = hifDeviceInserted, + .remove = hifDeviceRemoved, +}; +/* make sure we only unregister when registered. */ +static int registered = 0; + +OSDRV_CALLBACKS osdrvCallbacks; +extern A_UINT32 onebitmode; +extern A_UINT32 busspeedlow; +extern A_UINT32 debughif; + +#ifdef DEBUG +#define ATH_DEBUG_ERROR 1 +#define ATH_DEBUG_WARN 2 +#define ATH_DEBUG_TRACE 3 +#define _AR_DEBUG_PRINTX_ARG(arg...) arg +#define AR_DEBUG_PRINTF(lvl, args)\ + {if (lvl <= debughif)\ + A_PRINTF(KERN_ALERT _AR_DEBUG_PRINTX_ARG args);\ + } +#define AR_DEBUG_ASSERT(test) do { \ + if (!(test)) { \ + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test)); \ + } \ +} while(0) +#else +#define AR_DEBUG_PRINTF(lvl, args) +#define AR_DEBUG_ASSERT(test) +#endif + +static BUS_REQUEST *hifAllocateBusRequest(HIF_DEVICE *device); +static void hifFreeBusRequest(HIF_DEVICE *device, BUS_REQUEST *busrequest); +static void ResetAllCards(void); + +/* ------ Functions ------ */ +A_STATUS HIFInit(OSDRV_CALLBACKS *callbacks) +{ + int status; + AR_DEBUG_ASSERT(callbacks != NULL); + + /* store the callback handlers */ + osdrvCallbacks = *callbacks; + + /* Register with bus driver core */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFInit registering\n")); + registered = 1; + status = sdio_register_driver(&ar6k_driver); + AR_DEBUG_ASSERT(status==0); + + if (status != 0) { + return A_ERROR; + } + + return A_OK; + +} + +static A_STATUS +__HIFReadWrite(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length, + A_UINT32 request, + void *context) +{ + A_UINT8 opcode; + A_STATUS status = A_OK; + int ret; + A_UINT8 *tbuffer; + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device: 0x%p, buffer:0x%p\n", device, buffer)); + + do { + if (request & HIF_EXTENDED_IO) { + //AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Command type: CMD53\n")); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid command type: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + + if (request & HIF_BLOCK_BASIS) { + /* round to whole block length size */ + length = (length / HIF_MBOX_BLOCK_SIZE) * HIF_MBOX_BLOCK_SIZE; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Block mode (BlockLen: %d)\n", + length)); + } else if (request & HIF_BYTE_BASIS) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Byte mode (BlockLen: %d)\n", + length)); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid data mode: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + +#if 0 + /* useful for checking register accesses */ + if (length & 0x3) { + A_PRINTF(KERN_ALERT"AR6000: HIF (%s) is not a multiple of 4 bytes, addr:0x%X, len:%d\n", + request & HIF_WRITE ? "write":"read", address, length); + } +#endif + + if ((address >= HIF_MBOX_START_ADDR(0)) && + (address <= HIF_MBOX_END_ADDR(3))) + { + + AR_DEBUG_ASSERT(length <= HIF_MBOX_WIDTH); + + /* + * Mailbox write. Adjust the address so that the last byte + * falls on the EOM address. + */ + address += (HIF_MBOX_WIDTH - length); + } + + if (request & HIF_FIXED_ADDRESS) { + opcode = CMD53_FIXED_ADDRESS; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Address mode: Fixed 0x%X\n", address)); + } else if (request & HIF_INCREMENTAL_ADDRESS) { + opcode = CMD53_INCR_ADDRESS; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Address mode: Incremental 0x%X\n", address)); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid address mode: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + + if (request & HIF_WRITE) { +#if HIF_USE_DMA_BOUNCE_BUFFER + AR_DEBUG_ASSERT(device->dma_buffer != NULL); + tbuffer = device->dma_buffer; + /* copy the write data to the dma buffer */ + AR_DEBUG_ASSERT(length <= HIF_DMA_BUFFER_SIZE); + memcpy(tbuffer, buffer, length); +#else + tbuffer = buffer; +#endif + if (opcode == CMD53_FIXED_ADDRESS) { + ret = sdio_writesb(device->func, address, tbuffer, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: writesb ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } else { + ret = sdio_memcpy_toio(device->func, address, tbuffer, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: writeio ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } + } else if (request & HIF_READ) { +#if HIF_USE_DMA_BOUNCE_BUFFER + AR_DEBUG_ASSERT(device->dma_buffer != NULL); + AR_DEBUG_ASSERT(length <= HIF_DMA_BUFFER_SIZE); + tbuffer = device->dma_buffer; +#else + tbuffer = buffer; +#endif + if (opcode == CMD53_FIXED_ADDRESS) { + ret = sdio_readsb(device->func, tbuffer, address, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: readsb ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } else { + ret = sdio_memcpy_fromio(device->func, tbuffer, address, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: readio ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } +#if HIF_USE_DMA_BOUNCE_BUFFER + /* copy the read data from the dma buffer */ + memcpy(buffer, tbuffer, length); +#endif + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid direction: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + + if (ret) { + status = A_ERROR; + } + } while (FALSE); + + return status; +} + +/* queue a read/write request */ +A_STATUS +HIFReadWrite(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length, + A_UINT32 request, + void *context) +{ + A_STATUS status = A_OK; + unsigned long flags; + BUS_REQUEST *busrequest; + BUS_REQUEST *async; + BUS_REQUEST *active; + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device: %p\n", device)); + + do { + if ((request & HIF_ASYNCHRONOUS) || (request & HIF_SYNCHRONOUS)){ + /* serialize all requests through the async thread */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Execution mode: %s\n", (request & HIF_ASYNCHRONOUS)?"Async":"Synch")); + busrequest = hifAllocateBusRequest(device); + if (busrequest == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: no async bus requests available\n")); + return A_ERROR; + } + spin_lock_irqsave(&device->asynclock, flags); + busrequest->address = address; + busrequest->buffer = buffer; + busrequest->length = length; + busrequest->request = request; + busrequest->context = context; + /* add to async list */ + active = device->asyncreq; + if (active == NULL) { + device->asyncreq = busrequest; + device->asyncreq->inusenext = NULL; + } else { + for (async = device->asyncreq; + async != NULL; + async = async->inusenext) { + active = async; + } + active->inusenext = busrequest; + busrequest->inusenext = NULL; + } + spin_unlock_irqrestore(&device->asynclock, flags); + if (request & HIF_SYNCHRONOUS) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: queued sync req: 0x%X\n", (unsigned int)busrequest)); + + /* wait for completion */ + up(&device->sem_async); + if (down_interruptible(&busrequest->sem_req) != 0) { + /* interrupted, exit */ + return A_ERROR; + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: sync return freeing 0x%X: 0x%X\n", + (unsigned int)busrequest, busrequest->status)); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: freeing req: 0x%X\n", (unsigned int)request)); + hifFreeBusRequest(device, busrequest); + return busrequest->status; + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: queued async req: 0x%X\n", (unsigned int)busrequest)); + up(&device->sem_async); + return A_PENDING; + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid execution mode: 0x%08x\n", (unsigned int)request)); + status = A_EINVAL; + break; + } + } while(0); + + return status; +} +/* thread to serialize all requests, both sync and async */ +static int async_task(void *param) + { + HIF_DEVICE *device; + BUS_REQUEST *request; + A_STATUS status; + unsigned long flags; + + device = (HIF_DEVICE *)param; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task\n")); + set_current_state(TASK_INTERRUPTIBLE); + while(!device->async_shutdown) { + /* wait for work */ + if (down_interruptible(&device->sem_async) != 0) { + /* interrupted, exit */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task interrupted\n")); + break; + } + if (device->async_shutdown) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task stopping\n")); + break; + } + /* we want to hold the host over multiple cmds if possible, but holding the host blocks card interrupts */ + sdio_claim_host(device->func); + spin_lock_irqsave(&device->asynclock, flags); + /* pull the request to work on */ + while (device->asyncreq != NULL) { + request = device->asyncreq; + if (request->inusenext != NULL) { + device->asyncreq = request->inusenext; + } else { + device->asyncreq = NULL; + } + spin_unlock_irqrestore(&device->asynclock, flags); + /* call HIFReadWrite in sync mode to do the work */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task processing req: 0x%X\n", (unsigned int)request)); + status = __HIFReadWrite(device, request->address, request->buffer, + request->length, request->request & ~HIF_SYNCHRONOUS, NULL); + if (request->request & HIF_ASYNCHRONOUS) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task completion routine req: 0x%X\n", (unsigned int)request)); + device->htcCallbacks.rwCompletionHandler(request->context, status); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task freeing req: 0x%X\n", (unsigned int)request)); + hifFreeBusRequest(device, request); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task upping req: 0x%X\n", (unsigned int)request)); + request->status = status; + up(&request->sem_req); + } + spin_lock_irqsave(&device->asynclock, flags); + } + spin_unlock_irqrestore(&device->asynclock, flags); + sdio_release_host(device->func); + } + + complete_and_exit(&device->async_completion, 0); + return 0; + } + +A_STATUS +HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode, + void *config, A_UINT32 configLen) +{ + A_UINT32 count; + + switch(opcode) { + case HIF_DEVICE_GET_MBOX_BLOCK_SIZE: + ((A_UINT32 *)config)[0] = HIF_MBOX0_BLOCK_SIZE; + ((A_UINT32 *)config)[1] = HIF_MBOX1_BLOCK_SIZE; + ((A_UINT32 *)config)[2] = HIF_MBOX2_BLOCK_SIZE; + ((A_UINT32 *)config)[3] = HIF_MBOX3_BLOCK_SIZE; + break; + + case HIF_DEVICE_GET_MBOX_ADDR: + for (count = 0; count < 4; count ++) { + ((A_UINT32 *)config)[count] = HIF_MBOX_START_ADDR(count); + } + break; + case HIF_DEVICE_GET_IRQ_PROC_MODE: + *((HIF_DEVICE_IRQ_PROCESSING_MODE *)config) = HIF_DEVICE_IRQ_SYNC_ONLY; + break; + default: + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, + ("AR6000: Unsupported configuration opcode: %d\n", opcode)); + return A_ERROR; + } + + return A_OK; +} + +void +HIFShutDownDevice(HIF_DEVICE *device) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +HIFShutDownDevice\n")); + if (device != NULL) { + AR_DEBUG_ASSERT(device->func != NULL); + } else { + /* since we are unloading the driver anyways, reset all cards in case the SDIO card + * is externally powered and we are unloading the SDIO stack. This avoids the problem when + * the SDIO stack is reloaded and attempts are made to re-enumerate a card that is already + * enumerated */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFShutDownDevice, resetting\n")); + ResetAllCards(); + } + /* Unregister with bus driver core */ + if (registered) { + registered = 0; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Unregistering with the bus driver\n")); + sdio_unregister_driver(&ar6k_driver); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Unregistered\n")); + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -HIFShutDownDevice\n")); +} + +static void +hifIRQHandler(struct sdio_func *func) +{ + A_STATUS status; + HIF_DEVICE *device; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifIRQHandler\n")); + + device = getHifDevice(func); + /* release the host during ints so we can pick it back up when we process cmds */ + sdio_release_host(device->func); + status = device->htcCallbacks.dsrHandler(device->htcCallbacks.context); + sdio_claim_host(device->func); + AR_DEBUG_ASSERT(status == A_OK); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifIRQHandler\n")); +} + +/* handle HTC startup via thread*/ +static int startup_task(void *param) +{ + HIF_DEVICE *device; + + device = (HIF_DEVICE *)param; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: call HTC from startup_task\n")); + /* start up inform DRV layer */ + if ((osdrvCallbacks.deviceInsertedHandler(osdrvCallbacks.context,device)) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device rejected\n")); + } + return 0; +} + +static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id) +{ + int ret; + HIF_DEVICE * device; + int count; + struct task_struct* startup_task_struct; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: hifDeviceInserted, Function: 0x%X, Vendor ID: 0x%X, Device ID: 0x%X, block size: 0x%X/0x%X\n", + func->num, func->vendor, func->device, func->max_blksize, func->cur_blksize)); + + addHifDevice(func); + device = getHifDevice(func); + + spin_lock_init(&device->lock); + spin_lock_init(&device->asynclock); + + /* enable the SDIO function */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: claim\n")); + sdio_claim_host(func); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: enable\n")); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + /* give us some time to enable, in ms */ + func->enable_timeout = 100; +#endif + + ret = sdio_enable_func(func); + if (ret) { + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to enable AR6K: 0x%X, timeout: %d\n", + __FUNCTION__, ret, func->enable_timeout)); +#else + + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to enable AR6K: 0x%X\n", + __FUNCTION__, ret)); +#endif + sdio_release_host(func); + return ret; + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: set block size 0x%X\n", HIF_MBOX_BLOCK_SIZE)); + ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE); + sdio_release_host(func); + if (ret) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to set block size 0x%x AR6K: 0x%X\n", + __FUNCTION__, HIF_MBOX_BLOCK_SIZE, ret)); + sdio_release_host(func); + return ret; + } + /* Initialize the bus requests to be used later */ + A_MEMZERO(device->busRequest, sizeof(device->busRequest)); + for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) { + sema_init(&device->busRequest[count].sem_req, 0); + hifFreeBusRequest(device, &device->busRequest[count]); + } + + /* create async I/O thread */ + device->async_shutdown = 0; + device->async_task = kthread_create(async_task, + (void *)device, + "AR6K Async"); + if (device->async_task == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create async task\n", __FUNCTION__)); + sdio_release_host(func); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start async task\n")); + sema_init(&device->sem_async, 0); + wake_up_process(device->async_task ); + + /* create startup thread */ + startup_task_struct = kthread_create(startup_task, + (void *)device, + "AR6K startup"); + if (startup_task_struct == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create startup task\n", __FUNCTION__)); + sdio_release_host(func); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start startup task\n")); + wake_up_process(startup_task_struct); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: return %d\n", ret)); + return ret; +} + + +void +HIFAckInterrupt(HIF_DEVICE *device) +{ + AR_DEBUG_ASSERT(device != NULL); + + /* Acknowledge our function IRQ */ +} + +void +HIFUnMaskInterrupt(HIF_DEVICE *device) +{ + int ret;; + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFUnMaskInterrupt\n")); + + /* Register the IRQ Handler */ + sdio_claim_host(device->func); + ret = sdio_claim_irq(device->func, hifIRQHandler); + sdio_release_host(device->func); + AR_DEBUG_ASSERT(ret == 0); +} + +void HIFMaskInterrupt(HIF_DEVICE *device) +{ + int ret;; + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFMaskInterrupt\n")); + + /* Mask our function IRQ */ + sdio_claim_host(device->func); + ret = sdio_release_irq(device->func); + sdio_release_host(device->func); + AR_DEBUG_ASSERT(ret == 0); +} + +static BUS_REQUEST *hifAllocateBusRequest(HIF_DEVICE *device) +{ + BUS_REQUEST *busrequest; + unsigned long flag; + + /* Acquire lock */ + spin_lock_irqsave(&device->lock, flag); + + /* Remove first in list */ + if((busrequest = device->s_busRequestFreeQueue) != NULL) + { + device->s_busRequestFreeQueue = busrequest->next; + } + + /* Release lock */ + spin_unlock_irqrestore(&device->lock, flag); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: hifAllocateBusRequest: 0x%p\n", busrequest)); + return busrequest; +} + +static void +hifFreeBusRequest(HIF_DEVICE *device, BUS_REQUEST *busrequest) +{ + unsigned long flag; + + AR_DEBUG_ASSERT(busrequest != NULL); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: hifFreeBusRequest: 0x%p\n", busrequest)); + /* Acquire lock */ + spin_lock_irqsave(&device->lock, flag); + + + /* Insert first in list */ + busrequest->next = device->s_busRequestFreeQueue; + busrequest->inusenext = NULL; + device->s_busRequestFreeQueue = busrequest; + + /* Release lock */ + spin_unlock_irqrestore(&device->lock, flag); +} + +static void hifDeviceRemoved(struct sdio_func *func) +{ + A_STATUS status = A_OK; + HIF_DEVICE *device; + int ret; + AR_DEBUG_ASSERT(func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDeviceRemoved\n")); + device = getHifDevice(func); + if (device->claimedContext != NULL) { + status = osdrvCallbacks.deviceRemovedHandler(device->claimedContext, device); + } + + if (device->async_task != NULL) { + init_completion(&device->async_completion); + device->async_shutdown = 1; + up(&device->sem_async); + wait_for_completion(&device->async_completion); + device->async_task = NULL; + } + /* Disable the card */ + sdio_claim_host(device->func); + ret = sdio_disable_func(device->func); + sdio_release_host(device->func); + delHifDevice(device); + AR_DEBUG_ASSERT(status == A_OK); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifDeviceRemoved\n")); +} + + +static HIF_DEVICE * +addHifDevice(struct sdio_func *func) +{ + HIF_DEVICE *hifdevice; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice\n")); + AR_DEBUG_ASSERT(func != NULL); + hifdevice = (HIF_DEVICE *)kzalloc(sizeof(HIF_DEVICE), GFP_KERNEL); + AR_DEBUG_ASSERT(hifdevice != NULL); +#if HIF_USE_DMA_BOUNCE_BUFFER + hifdevice->dma_buffer = kmalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL); + AR_DEBUG_ASSERT(hifdevice->dma_buffer != NULL); +#endif + hifdevice->func = func; + sdio_set_drvdata(func, hifdevice); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice; 0x%p\n", hifdevice)); + return hifdevice; +} + +static HIF_DEVICE * +getHifDevice(struct sdio_func *func) +{ + AR_DEBUG_ASSERT(func != NULL); + return (HIF_DEVICE *)sdio_get_drvdata(func); +} + +static void +delHifDevice(HIF_DEVICE * device) +{ + AR_DEBUG_ASSERT(device!= NULL); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: delHifDevice; 0x%p\n", device)); + if (device->dma_buffer != NULL) { + kfree(device->dma_buffer); + } + kfree(device); +} + +static void ResetAllCards(void) +{ +} + +void HIFClaimDevice(HIF_DEVICE *device, void *context) +{ + device->claimedContext = context; +} + +void HIFReleaseDevice(HIF_DEVICE *device) +{ + device->claimedContext = NULL; +} + +A_STATUS HIFAttachHTC(HIF_DEVICE *device, HTC_CALLBACKS *callbacks) +{ + if (device->htcCallbacks.context != NULL) { + /* already in use! */ + return A_ERROR; + } + device->htcCallbacks = *callbacks; + return A_OK; +} + +void HIFDetachHTC(HIF_DEVICE *device) +{ + A_MEMZERO(&device->htcCallbacks,sizeof(device->htcCallbacks)); +} + + + + diff -urN linux-2.6.26/drivers/net/wireless/ath6k/hif.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/hif.h --- linux-2.6.26/drivers/net/wireless/ath6k/hif.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/hif.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,323 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// HIF specific declarations and prototypes +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HIF_H_ +#define _HIF_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Header files */ +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" + + +typedef struct htc_callbacks HTC_CALLBACKS; +typedef struct hif_device HIF_DEVICE; + +/* + * direction - Direction of transfer (HIF_READ/HIF_WRITE). + */ +#define HIF_READ 0x00000001 +#define HIF_WRITE 0x00000002 +#define HIF_DIR_MASK (HIF_READ | HIF_WRITE) + +/* + * type - An interface may support different kind of read/write commands. + * For example: SDIO supports CMD52/CMD53s. In case of MSIO it + * translates to using different kinds of TPCs. The command type + * is thus divided into a basic and an extended command and can + * be specified using HIF_BASIC_IO/HIF_EXTENDED_IO. + */ +#define HIF_BASIC_IO 0x00000004 +#define HIF_EXTENDED_IO 0x00000008 +#define HIF_TYPE_MASK (HIF_BASIC_IO | HIF_EXTENDED_IO) + +/* + * emode - This indicates the whether the command is to be executed in a + * blocking or non-blocking fashion (HIF_SYNCHRONOUS/ + * HIF_ASYNCHRONOUS). The read/write data paths in HTC have been + * implemented using the asynchronous mode allowing the the bus + * driver to indicate the completion of operation through the + * registered callback routine. The requirement primarily comes + * from the contexts these operations get called from (a driver's + * transmit context or the ISR context in case of receive). + * Support for both of these modes is essential. + */ +#define HIF_SYNCHRONOUS 0x00000010 +#define HIF_ASYNCHRONOUS 0x00000020 +#define HIF_EMODE_MASK (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS) + +/* + * dmode - An interface may support different kinds of commands based on + * the tradeoff between the amount of data it can carry and the + * setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/ + * HIF_BLOCK_BASIS). In case of latter, the data is rounded off + * to the nearest block size by padding. The size of the block is + * configurable at compile time using the HIF_BLOCK_SIZE and is + * negotiated with the target during initialization after the + * AR6000 interrupts are enabled. + */ +#define HIF_BYTE_BASIS 0x00000040 +#define HIF_BLOCK_BASIS 0x00000080 +#define HIF_DMODE_MASK (HIF_BYTE_BASIS | HIF_BLOCK_BASIS) + +/* + * amode - This indicates if the address has to be incremented on AR6000 + * after every read/write operation (HIF?FIXED_ADDRESS/ + * HIF_INCREMENTAL_ADDRESS). + */ +#define HIF_FIXED_ADDRESS 0x00000100 +#define HIF_INCREMENTAL_ADDRESS 0x00000200 +#define HIF_AMODE_MASK (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS) + +#define HIF_WR_ASYNC_BYTE_FIX \ + (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_WR_ASYNC_BYTE_INC \ + (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_WR_ASYNC_BLOCK_INC \ + (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_WR_SYNC_BYTE_FIX \ + (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_WR_SYNC_BYTE_INC \ + (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_WR_SYNC_BLOCK_INC \ + (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_SYNC_BYTE_INC \ + (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_SYNC_BYTE_FIX \ + (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_RD_ASYNC_BYTE_FIX \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_RD_ASYNC_BLOCK_FIX \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS) +#define HIF_RD_ASYNC_BYTE_INC \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_ASYNC_BLOCK_INC \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_SYNC_BLOCK_INC \ + (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) + + +typedef enum { + HIF_DEVICE_POWER_STATE = 0, + HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + HIF_DEVICE_GET_MBOX_ADDR, + HIF_DEVICE_GET_PENDING_EVENTS_FUNC, + HIF_DEVICE_GET_IRQ_PROC_MODE, + HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC, + HIF_DEVICE_POWER_STATE_CHANGE, +} HIF_DEVICE_CONFIG_OPCODE; + +/* + * HIF CONFIGURE definitions: + * + * HIF_DEVICE_GET_MBOX_BLOCK_SIZE + * input : none + * output : array of 4 A_UINT32s + * notes: block size is returned for each mailbox (4) + * + * HIF_DEVICE_GET_MBOX_ADDR + * input : none + * output : array of 4 A_UINT32 + * notes: address is returned for each mailbox (4) in the array + * + * HIF_DEVICE_GET_PENDING_EVENTS_FUNC + * input : none + * output: HIF_PENDING_EVENTS_FUNC function pointer + * notes: this is optional for the HIF layer, if the request is + * not handled then it indicates that the upper layer can use + * the standard device methods to get pending events (IRQs, mailbox messages etc..) + * otherwise it can call the function pointer to check pending events. + * + * HIF_DEVICE_GET_IRQ_PROC_MODE + * input : none + * output : HIF_DEVICE_IRQ_PROCESSING_MODE (interrupt processing mode) + * note: the hif layer interfaces with the underlying OS-specific bus driver. The HIF + * layer can report whether IRQ processing is requires synchronous behavior or + * can be processed using asynchronous bus requests (typically faster). + * + * HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC + * input : + * output : HIF_MASK_UNMASK_RECV_EVENT function pointer + * notes: this is optional for the HIF layer. The HIF layer may require a special mechanism + * to mask receive message events. The upper layer can call this pointer when it needs + * to mask/unmask receive events (in case it runs out of buffers). + * + * HIF_DEVICE_POWER_STATE_CHANGE + * + * input : HIF_DEVICE_POWER_CHANGE_TYPE + * output : none + * note: this is optional for the HIF layer. The HIF layer can handle power on/off state change + * requests in an interconnect specific way. This is highly OS and bus driver dependent. + * The caller must guarantee that no HIF read/write requests will be made after the device + * is powered down. + * + * + * + */ + +typedef enum { + HIF_DEVICE_IRQ_SYNC_ONLY, /* for HIF implementations that require the DSR to process all + interrupts before returning */ + HIF_DEVICE_IRQ_ASYNC_SYNC, /* for HIF implementations that allow DSR to process interrupts + using ASYNC I/O (that is HIFAckInterrupt can be called at a + later time */ +} HIF_DEVICE_IRQ_PROCESSING_MODE; + +typedef enum { + HIF_DEVICE_POWER_UP, /* HIF layer should power up interface and/or module */ + HIF_DEVICE_POWER_DOWN, /* HIF layer should initiate bus-specific measures to minimize power */ + HIF_DEVICE_POWER_CUT /* HIF layer should initiate bus-specific AND/OR platform-specific measures + to completely power-off the module and associated hardware (i.e. cut power supplies) + */ +} HIF_DEVICE_POWER_CHANGE_TYPE; + +#define HIF_MAX_DEVICES 1 + +struct htc_callbacks { + void *context; /* context to pass to the dsrhandler + note : rwCompletionHandler is provided the context passed to HIFReadWrite */ + A_STATUS (* rwCompletionHandler)(void *rwContext, A_STATUS status); + A_STATUS (* dsrHandler)(void *context); +}; + +typedef struct osdrv_callbacks { + void *context; /* context to pass for all callbacks except deviceRemovedHandler + the deviceRemovedHandler is only called if the device is claimed */ + A_STATUS (* deviceInsertedHandler)(void *context, void *hif_handle); + A_STATUS (* deviceRemovedHandler)(void *claimedContext, void *hif_handle); + A_STATUS (* deviceSuspendHandler)(void *context); + A_STATUS (* deviceResumeHandler)(void *context); + A_STATUS (* deviceWakeupHandler)(void *context); +} OSDRV_CALLBACKS; + +#define HIF_OTHER_EVENTS (1 << 0) /* other interrupts (non-Recv) are pending, host + needs to read the register table to figure out what */ +#define HIF_RECV_MSG_AVAIL (1 << 1) /* pending recv packet */ + +typedef struct _HIF_PENDING_EVENTS_INFO { + A_UINT32 Events; + A_UINT32 LookAhead; + A_UINT32 AvailableRecvBytes; +} HIF_PENDING_EVENTS_INFO; + + /* function to get pending events , some HIF modules use special mechanisms + * to detect packet available and other interrupts */ +typedef A_STATUS ( *HIF_PENDING_EVENTS_FUNC)(HIF_DEVICE *device, + HIF_PENDING_EVENTS_INFO *pEvents, + void *AsyncContext); + +#define HIF_MASK_RECV TRUE +#define HIF_UNMASK_RECV FALSE + /* function to mask recv events */ +typedef A_STATUS ( *HIF_MASK_UNMASK_RECV_EVENT)(HIF_DEVICE *device, + A_BOOL Mask, + void *AsyncContext); + + +/* + * This API is used to perform any global initialization of the HIF layer + * and to set OS driver callbacks (i.e. insertion/removal) to the HIF layer + * + */ +A_STATUS HIFInit(OSDRV_CALLBACKS *callbacks); + +/* This API claims the HIF device and provides a context for handling removal. + * The device removal callback is only called when the OSDRV layer claims + * a device. The claimed context must be non-NULL */ +void HIFClaimDevice(HIF_DEVICE *device, void *claimedContext); +/* release the claimed device */ +void HIFReleaseDevice(HIF_DEVICE *device); + +/* This API allows the HTC layer to attach to the HIF device */ +A_STATUS HIFAttachHTC(HIF_DEVICE *device, HTC_CALLBACKS *callbacks); +/* This API detaches the HTC layer from the HIF device */ +void HIFDetachHTC(HIF_DEVICE *device); + +/* + * This API is used to provide the read/write interface over the specific bus + * interface. + * address - Starting address in the AR6000's address space. For mailbox + * writes, it refers to the start of the mbox boundary. It should + * be ensured that the last byte falls on the mailbox's EOM. For + * mailbox reads, it refers to the end of the mbox boundary. + * buffer - Pointer to the buffer containg the data to be transmitted or + * received. + * length - Amount of data to be transmitted or received. + * request - Characterizes the attributes of the command. + */ +A_STATUS +HIFReadWrite(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length, + A_UINT32 request, + void *context); + +/* + * This can be initiated from the unload driver context when the OSDRV layer has no more use for + * the device. + */ +void HIFShutDownDevice(HIF_DEVICE *device); + +/* + * This should translate to an acknowledgment to the bus driver indicating that + * the previous interrupt request has been serviced and the all the relevant + * sources have been cleared. HTC is ready to process more interrupts. + * This should prevent the bus driver from raising an interrupt unless the + * previous one has been serviced and acknowledged using the previous API. + */ +void HIFAckInterrupt(HIF_DEVICE *device); + +void HIFMaskInterrupt(HIF_DEVICE *device); + +void HIFUnMaskInterrupt(HIF_DEVICE *device); + +/* + * This set of functions are to be used by the bus driver to notify + * the HIF module about various events. + * These are not implemented if the bus driver provides an alternative + * way for this notification though callbacks for instance. + */ +int HIFInsertEventNotify(void); + +int HIFRemoveEventNotify(void); + +int HIFIRQEventNotify(void); + +int HIFRWCompleteEventNotify(void); + +A_STATUS +HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode, + void *config, A_UINT32 configLen); + +#ifdef __cplusplus +} +#endif + +#endif /* _HIF_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/hif_internal.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/hif_internal.h --- linux-2.6.26/drivers/net/wireless/ath6k/hif_internal.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/hif_internal.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,89 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// internal header file for hif layer +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "hif.h" + +#define MANUFACTURER_ID_AR6001_BASE 0x100 +#define MANUFACTURER_ID_AR6002_BASE 0x200 +#define MANUFACTURER_ID_AR6003_BASE 0x300 +#define FUNCTION_CLASS 0x0 +#define MANUFACTURER_CODE 0x271 + +#define BUS_REQUEST_MAX_NUM 64 + +#define SDIO_CLOCK_FREQUENCY_DEFAULT 25000000 +#define SDWLAN_ENABLE_DISABLE_TIMEOUT 20 +#define FLAGS_CARD_ENAB 0x02 +#define FLAGS_CARD_IRQ_UNMSK 0x04 + +#define HIF_MBOX_BLOCK_SIZE 128 +#define HIF_MBOX_BASE_ADDR 0x800 +#define HIF_MBOX_WIDTH 0x800 +#define HIF_MBOX0_BLOCK_SIZE 1 +#define HIF_MBOX1_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE +#define HIF_MBOX2_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE +#define HIF_MBOX3_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE + +#define HIF_MBOX_START_ADDR(mbox) \ + HIF_MBOX_BASE_ADDR + mbox * HIF_MBOX_WIDTH + +#define HIF_MBOX_END_ADDR(mbox) \ + HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1 + +typedef struct bus_request { + struct bus_request *next; /* link list of available requests */ + struct bus_request *inusenext; /* link list of in use requests */ + struct compat_semaphore sem_req; + A_UINT32 address; /* request data */ + A_UCHAR *buffer; + A_UINT32 length; + A_UINT32 request; + void *context; + A_STATUS status; +} BUS_REQUEST; + +struct hif_device { + struct sdio_func *func; + spinlock_t asynclock; + struct task_struct* async_task; /* task to handle async commands */ + struct compat_semaphore sem_async; /* wake up for async task */ + int async_shutdown; /* stop the async task */ + struct completion async_completion; /* thread completion */ + BUS_REQUEST *asyncreq; /* request for async tasklet */ + BUS_REQUEST *taskreq; /* async tasklet data */ + spinlock_t lock; + BUS_REQUEST *s_busRequestFreeQueue; /* free list */ + BUS_REQUEST busRequest[BUS_REQUEST_MAX_NUM]; /* available bus requests */ + void *claimedContext; + HTC_CALLBACKS htcCallbacks; + A_UINT8 *dma_buffer; +}; + +#define HIF_DMA_BUFFER_SIZE (32 * 1024) +#define CMD53_FIXED_ADDRESS 1 +#define CMD53_INCR_ADDRESS 2 diff -urN linux-2.6.26/drivers/net/wireless/ath6k/host_version.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/host_version.h --- linux-2.6.26/drivers/net/wireless/ath6k/host_version.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/host_version.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains version information for the sample host driver for the +// AR6000 chip +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HOST_VERSION_H_ +#define _HOST_VERSION_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "AR6K_version.h" + +/* + * The version number is made up of major, minor, patch and build + * numbers. These are 16 bit numbers. The build and release script will + * set the build number using a Perforce counter. Here the build number is + * set to 9999 so that builds done without the build-release script are easily + * identifiable. + */ + +#define ATH_SW_VER_MAJOR __VER_MAJOR_ +#define ATH_SW_VER_MINOR __VER_MINOR_ +#define ATH_SW_VER_PATCH __VER_PATCH_ +#define ATH_SW_VER_BUILD __BUILD_NUMBER_ + +#ifdef __cplusplus +} +#endif + +#endif /* _HOST_VERSION_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/htc.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc.c --- linux-2.6.26/drivers/net/wireless/ath6k/htc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,525 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + + +static void HTCReportFailure(void *Context, AR6K_TARGET_FAILURE_TYPE Type); + + +void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList) +{ + LOCK_HTC(target); + HTC_PACKET_ENQUEUE(pList,pPacket); + UNLOCK_HTC(target); +} + +HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList) +{ + HTC_PACKET *pPacket; + + LOCK_HTC(target); + pPacket = HTC_PACKET_DEQUEUE(pList); + UNLOCK_HTC(target); + + return pPacket; +} + +/* cleanup the HTC instance */ +static void HTCCleanup(HTC_TARGET *target) +{ + A_INT32 i; + + DevCleanup(&target->Device); + + for (i = 0;i < NUM_CONTROL_BUFFERS;i++) { + if (target->HTCControlBuffers[i].Buffer) { + A_FREE(target->HTCControlBuffers[i].Buffer); + } + } + + if (A_IS_MUTEX_VALID(&target->HTCLock)) { + A_MUTEX_DELETE(&target->HTCLock); + } + + if (A_IS_MUTEX_VALID(&target->HTCRxLock)) { + A_MUTEX_DELETE(&target->HTCRxLock); + } + + if (A_IS_MUTEX_VALID(&target->HTCTxLock)) { + A_MUTEX_DELETE(&target->HTCTxLock); + } + /* free our instance */ + A_FREE(target); +} + +/* registered target arrival callback from the HIF layer */ +HTC_HANDLE HTCCreate(void *hif_handle, HTC_INIT_INFO *pInfo) +{ + HTC_TARGET *target = NULL; + A_STATUS status = A_OK; + int i; + A_UINT32 ctrl_bufsz; + A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX]; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Enter\n")); + + do { + + /* allocate target memory */ + if ((target = (HTC_TARGET *)A_MALLOC(sizeof(HTC_TARGET))) == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n")); + status = A_ERROR; + break; + } + + A_MEMZERO(target, sizeof(HTC_TARGET)); + A_MUTEX_INIT(&target->HTCLock); + A_MUTEX_INIT(&target->HTCRxLock); + A_MUTEX_INIT(&target->HTCTxLock); + INIT_HTC_PACKET_QUEUE(&target->ControlBufferTXFreeList); + INIT_HTC_PACKET_QUEUE(&target->ControlBufferRXFreeList); + + /* give device layer the hif device handle */ + target->Device.HIFDevice = hif_handle; + /* give the device layer our context (for event processing) + * the device layer will register it's own context with HIF + * so we need to set this so we can fetch it in the target remove handler */ + target->Device.HTCContext = target; + /* set device layer target failure callback */ + target->Device.TargetFailureCallback = HTCReportFailure; + /* set device layer recv message pending callback */ + target->Device.MessagePendingCallback = HTCRecvMessagePendingHandler; + target->EpWaitingForBuffers = ENDPOINT_MAX; + + A_MEMCPY(&target->HTCInitInfo,pInfo,sizeof(HTC_INIT_INFO)); + + /* setup device layer */ + status = DevSetup(&target->Device); + + if (A_FAILED(status)) { + break; + } + + + /* get the block sizes */ + status = HIFConfigureDevice(hif_handle, HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + blocksizes, sizeof(blocksizes)); + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get block size info from HIF layer...\n")); + break; + } + + /* Set the control buffer size based on the block size */ + if (blocksizes[1] > HTC_MAX_CONTROL_MESSAGE_LENGTH) { + ctrl_bufsz = blocksizes[1] + HTC_HDR_LENGTH; + } else { + ctrl_bufsz = HTC_MAX_CONTROL_MESSAGE_LENGTH + HTC_HDR_LENGTH; + } + for (i = 0;i < NUM_CONTROL_BUFFERS;i++) { + target->HTCControlBuffers[i].Buffer = A_MALLOC(ctrl_bufsz); + if (target->HTCControlBuffers[i].Buffer == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n")); + status = A_ERROR; + break; + } + } + + if (A_FAILED(status)) { + break; + } + + /* carve up buffers/packets for control messages */ + for (i = 0; i < NUM_CONTROL_RX_BUFFERS; i++) { + HTC_PACKET *pControlPacket; + pControlPacket = &target->HTCControlBuffers[i].HtcPacket; + SET_HTC_PACKET_INFO_RX_REFILL(pControlPacket, + target, + target->HTCControlBuffers[i].Buffer, + ctrl_bufsz, + ENDPOINT_0); + HTC_FREE_CONTROL_RX(target,pControlPacket); + } + + for (;i < NUM_CONTROL_BUFFERS;i++) { + HTC_PACKET *pControlPacket; + pControlPacket = &target->HTCControlBuffers[i].HtcPacket; + INIT_HTC_PACKET_INFO(pControlPacket, + target->HTCControlBuffers[i].Buffer, + ctrl_bufsz); + HTC_FREE_CONTROL_TX(target,pControlPacket); + } + + } while (FALSE); + + if (A_FAILED(status)) { + if (target != NULL) { + HTCCleanup(target); + target = NULL; + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Exit\n")); + + return target; +} + +void HTCDestroy(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCDestroy .. Destroying :0x%X \n",(A_UINT32)target)); + HTCCleanup(target); + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCDestroy \n")); +} + +/* get the low level HIF device for the caller , the caller may wish to do low level + * HIF requests */ +void *HTCGetHifDevice(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + return target->Device.HIFDevice; +} + +/* wait for the target to arrive (sends HTC Ready message) + * this operation is fully synchronous and the message is polled for */ +A_STATUS HTCWaitTarget(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_STATUS status; + HTC_PACKET *pPacket = NULL; + HTC_READY_MSG *pRdyMsg; + HTC_SERVICE_CONNECT_REQ connect; + HTC_SERVICE_CONNECT_RESP resp; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Enter (target:0x%X) \n", (A_UINT32)target)); + + do { + +#ifdef MBOXHW_UNIT_TEST + + status = DoMboxHWTest(&target->Device); + + if (status != A_OK) { + break; + } + +#endif + + /* we should be getting 1 control message that the target is ready */ + status = HTCWaitforControlMessage(target, &pPacket); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Target Not Available!!\n")); + break; + } + + /* we controlled the buffer creation so it has to be properly aligned */ + pRdyMsg = (HTC_READY_MSG *)pPacket->pBuffer; + + if ((pRdyMsg->MessageID != HTC_MSG_READY_ID) || + (pPacket->ActualLength < sizeof(HTC_READY_MSG))) { + /* this message is not valid */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + if (pRdyMsg->CreditCount == 0 || pRdyMsg->CreditSize == 0) { + /* this message is not valid */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + target->TargetCredits = pRdyMsg->CreditCount; + target->TargetCreditSize = pRdyMsg->CreditSize; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" Target Ready: credits: %d credit size: %d\n", + target->TargetCredits, target->TargetCreditSize)); + + /* setup our pseudo HTC control endpoint connection */ + A_MEMZERO(&connect,sizeof(connect)); + A_MEMZERO(&resp,sizeof(resp)); + connect.EpCallbacks.pContext = target; + connect.EpCallbacks.EpTxComplete = HTCControlTxComplete; + connect.EpCallbacks.EpRecv = HTCControlRecv; + connect.EpCallbacks.EpRecvRefill = NULL; /* not needed */ + connect.EpCallbacks.EpSendFull = NULL; /* not nedded */ + connect.MaxSendQueueDepth = NUM_CONTROL_BUFFERS; + connect.ServiceID = HTC_CTRL_RSVD_SVC; + + /* connect fake service */ + status = HTCConnectService((HTC_HANDLE)target, + &connect, + &resp); + + if (!A_FAILED(status)) { + break; + } + + } while (FALSE); + + if (pPacket != NULL) { + HTC_FREE_CONTROL_RX(target,pPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Exit\n")); + + return status; +} + + + +/* Start HTC, enable interrupts and let the target know host has finished setup */ +A_STATUS HTCStart(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_PACKET *pPacket; + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Enter\n")); + + /* make sure interrupts are disabled at the chip level, + * this function can be called again from a reboot of the target without shutting down HTC */ + DevDisableInterrupts(&target->Device); + /* make sure state is cleared again */ + target->HTCStateFlags = 0; + + /* now that we are starting, push control receive buffers into the + * HTC control endpoint */ + + while (1) { + pPacket = HTC_ALLOC_CONTROL_RX(target); + if (NULL == pPacket) { + break; + } + HTCAddReceivePkt((HTC_HANDLE)target,pPacket); + } + + do { + + AR_DEBUG_ASSERT(target->InitCredits != NULL); + AR_DEBUG_ASSERT(target->EpCreditDistributionListHead != NULL); + AR_DEBUG_ASSERT(target->EpCreditDistributionListHead->pNext != NULL); + + /* call init credits callback to do the distribution , + * NOTE: the first entry in the distribution list is ENDPOINT_0, so + * we pass the start of the list after this one. */ + target->InitCredits(target->pCredDistContext, + target->EpCreditDistributionListHead->pNext, + target->TargetCredits); + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_TRC)) { + DumpCreditDistStates(target); + } + + /* the caller is done connecting to services, so we can indicate to the + * target that the setup phase is complete */ + status = HTCSendSetupComplete(target); + + if (A_FAILED(status)) { + break; + } + + /* unmask interrupts */ + status = DevUnmaskInterrupts(&target->Device); + + if (A_FAILED(status)) { + HTCStop(target); + } + + } while (FALSE); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Exit\n")); + return status; +} + +static void ResetEndpointStates(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + int i; + + for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) { + pEndpoint = &target->EndPoint[i]; + + A_MEMZERO(&pEndpoint->CreditDist, sizeof(pEndpoint->CreditDist)); + pEndpoint->ServiceID = 0; + pEndpoint->CurrentTxQueueDepth = 0; + pEndpoint->MaxMsgLength = 0; + pEndpoint->MaxTxQueueDepth = 0; +#ifdef HTC_EP_STAT_PROFILING + A_MEMZERO(&pEndpoint->EndPointStats,sizeof(pEndpoint->EndPointStats)); +#endif + INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBuffers); + INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue); + } + /* reset distribution list */ + target->EpCreditDistributionListHead = NULL; +} + +/* stop HTC communications, i.e. stop interrupt reception, and flush all queued buffers */ +void HTCStop(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCStop \n")); + + LOCK_HTC_RX(target); + /* mark that we are shutting down .. */ + target->HTCStateFlags |= HTC_STATE_STOPPING; + UNLOCK_HTC_RX(target); + + /* Masking interrupts is a synchronous operation, when this function returns + * all pending HIF I/O has completed, we can safely flush the queues */ + DevMaskInterrupts(&target->Device); + + /* flush all send packets */ + HTCFlushSendPkts(target); + /* flush all recv buffers */ + HTCFlushRecvBuffers(target); + + ResetEndpointStates(target); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCStop \n")); +} + +void HTCDumpCreditStates(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + + LOCK_HTC_TX(target); + + DumpCreditDistStates(target); + + UNLOCK_HTC_TX(target); +} + +/* report a target failure from the device, this is a callback from the device layer + * which uses a mechanism to report errors from the target (i.e. special interrupts) */ +static void HTCReportFailure(void *Context, AR6K_TARGET_FAILURE_TYPE Type) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + + target->TargetFailure = TRUE; + + switch (Type) { + + case AR6K_TARGET_TX_ERROR: + /* could be a credit problem */ + DumpCreditDistStates(target); + break; + case AR6K_TARGET_RX_ERROR: + + break; + case AR6K_TARGET_ASSERT: + if (target->HTCInitInfo.TargetFailure != NULL) { + /* let upper layer know, it needs to call HTCStop() */ + target->HTCInitInfo.TargetFailure(target->HTCInitInfo.pContext, A_ERROR); + } + break; + default: + break; + + } + +} + +void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription) +{ + A_CHAR stream[60]; + A_UINT32 i; + A_UINT16 offset, count; + + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("<---------Dumping %d Bytes : %s ------>\n", length, pDescription)); + + count = 0; + offset = 0; + for(i = 0; i < length; i++) { + A_SPRINTF(stream + offset, "%2.2X ", buffer[i]); + count ++; + offset += 3; + + if(count == 16) { + count = 0; + offset = 0; + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("[H]: %s\n", stream)); + A_MEMZERO(stream, 60); + } + } + + if(offset != 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("[H]: %s\n", stream)); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("<------------------------------------------------->\n")); +} + +A_BOOL HTCGetEndpointStatistics(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + HTC_ENDPOINT_STAT_ACTION Action, + HTC_ENDPOINT_STATS *pStats) +{ + +#ifdef HTC_EP_STAT_PROFILING + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_BOOL clearStats = FALSE; + A_BOOL sample = FALSE; + + switch (Action) { + case HTC_EP_STAT_SAMPLE : + sample = TRUE; + break; + case HTC_EP_STAT_SAMPLE_AND_CLEAR : + sample = TRUE; + clearStats = TRUE; + break; + case HTC_EP_STAT_CLEAR : + clearStats = TRUE; + break; + default: + break; + } + + A_ASSERT(Endpoint < ENDPOINT_MAX); + + /* lock out TX and RX while we sample and/or clear */ + LOCK_HTC_TX(target); + LOCK_HTC_RX(target); + + if (sample) { + A_ASSERT(pStats != NULL); + /* return the stats to the caller */ + A_MEMCPY(pStats, &target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS)); + } + + if (clearStats) { + /* reset stats */ + A_MEMZERO(&target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS)); + } + + UNLOCK_HTC_RX(target); + UNLOCK_HTC_TX(target); + + return TRUE; +#else + return FALSE; +#endif +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k/htc.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc.h --- linux-2.6.26/drivers/net/wireless/ath6k/htc.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,204 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __HTC_H__ +#define __HTC_H__ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field)) + +#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \ + (((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)])) + +/* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a + * structure using only the type and field name. + * Use these macros if there is the potential for unaligned buffer accesses. */ +#define A_GET_UINT16_FIELD(p,type,field) \ + ASSEMBLE_UNALIGNED_UINT16(p,\ + A_OFFSETOF(type,field) + 1, \ + A_OFFSETOF(type,field)) + +#define A_SET_UINT16_FIELD(p,type,field,value) \ +{ \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (A_UINT8)(value); \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field) + 1] = (A_UINT8)((value) >> 8); \ +} + +#define A_GET_UINT8_FIELD(p,type,field) \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] + +#define A_SET_UINT8_FIELD(p,type,field,value) \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (value) + +/****** DANGER DANGER *************** + * + * The frame header length and message formats defined herein were + * selected to accommodate optimal alignment for target processing. This reduces code + * size and improves performance. + * + * Any changes to the header length may alter the alignment and cause exceptions + * on the target. When adding to the message structures insure that fields are + * properly aligned. + * + */ + +/* HTC frame header */ +typedef PREPACK struct _HTC_FRAME_HDR{ + /* do not remove or re-arrange these fields, these are minimally required + * to take advantage of 4-byte lookaheads in some hardware implementations */ + A_UINT8 EndpointID; + A_UINT8 Flags; + A_UINT16 PayloadLen; /* length of data (including trailer) that follows the header */ + + /***** end of 4-byte lookahead ****/ + + A_UINT8 ControlBytes[2]; + + /* message payload starts after the header */ + +} POSTPACK HTC_FRAME_HDR; + +/* frame header flags */ +#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0) +#define HTC_FLAGS_RECV_TRAILER (1 << 1) + + +#define HTC_HDR_LENGTH (sizeof(HTC_FRAME_HDR)) +#define HTC_MAX_TRAILER_LENGTH 255 +#define HTC_MAX_PAYLOAD_LENGTH (2048 - sizeof(HTC_FRAME_HDR)) + +/* HTC control message IDs */ +typedef enum { + HTC_MSG_READY_ID = 1, + HTC_MSG_CONNECT_SERVICE_ID = 2, + HTC_MSG_CONNECT_SERVICE_RESPONSE_ID = 3, + HTC_MSG_SETUP_COMPLETE_ID = 4, +} HTC_MSG_IDS; + +#define HTC_MAX_CONTROL_MESSAGE_LENGTH 256 + +/* base message ID header */ +typedef PREPACK struct { + A_UINT16 MessageID; +} POSTPACK HTC_UNKNOWN_MSG; + +/* HTC ready message + * direction : target-to-host */ +typedef PREPACK struct { + A_UINT16 MessageID; /* ID */ + A_UINT16 CreditCount; /* number of credits the target can offer */ + A_UINT16 CreditSize; /* size of each credit */ + A_UINT8 MaxEndpoints; /* maximum number of endpoints the target has resources for */ + A_UINT8 _Pad1; +} POSTPACK HTC_READY_MSG; + +#define HTC_SERVICE_META_DATA_MAX_LENGTH 128 + +/* connect service + * direction : host-to-target */ +typedef PREPACK struct { + A_UINT16 MessageID; + A_UINT16 ServiceID; /* service ID of the service to connect to */ + A_UINT16 ConnectionFlags; /* connection flags */ + +#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) /* reduce credit dribbling when + the host needs credits */ +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3) +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3 + + A_UINT8 ServiceMetaLength; /* length of meta data that follows */ + A_UINT8 _Pad1; + + /* service-specific meta data starts after the header */ + +} POSTPACK HTC_CONNECT_SERVICE_MSG; + +/* connect response + * direction : target-to-host */ +typedef PREPACK struct { + A_UINT16 MessageID; + A_UINT16 ServiceID; /* service ID that the connection request was made */ + A_UINT8 Status; /* service connection status */ + A_UINT8 EndpointID; /* assigned endpoint ID */ + A_UINT16 MaxMsgSize; /* maximum expected message size on this endpoint */ + A_UINT8 ServiceMetaLength; /* length of meta data that follows */ + A_UINT8 _Pad1; + + /* service-specific meta data starts after the header */ + +} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG; + +typedef PREPACK struct { + A_UINT16 MessageID; + /* currently, no other fields */ +} POSTPACK HTC_SETUP_COMPLETE_MSG; + + +/* connect response status codes */ +#define HTC_SERVICE_SUCCESS 0 /* success */ +#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */ +#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */ +#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */ +#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more + endpoints */ + +/* report record IDs */ +typedef enum { + HTC_RECORD_NULL = 0, + HTC_RECORD_CREDITS = 1, + HTC_RECORD_LOOKAHEAD = 2, +} HTC_RPT_IDS; + +typedef PREPACK struct { + A_UINT8 RecordID; /* Record ID */ + A_UINT8 Length; /* Length of record */ +} POSTPACK HTC_RECORD_HDR; + +typedef PREPACK struct { + A_UINT8 EndpointID; /* Endpoint that owns these credits */ + A_UINT8 Credits; /* credits to report since last report */ +} POSTPACK HTC_CREDIT_REPORT; + +typedef PREPACK struct { + A_UINT8 PreValid; /* pre valid guard */ + A_UINT8 LookAhead[4]; /* 4 byte lookahead */ + A_UINT8 PostValid; /* post valid guard */ + + /* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes. + * The PreValid bytes must equal the inverse of the PostValid byte */ + +} POSTPACK HTC_LOOKAHEAD_REPORT; + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + + +#endif /* __HTC_H__ */ + diff -urN linux-2.6.26/drivers/net/wireless/ath6k/htc_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc_api.h --- linux-2.6.26/drivers/net/wireless/ath6k/htc_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc_api.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,463 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HTC_API_H_ +#define _HTC_API_H_ + +#include "htc.h" +#include "htc_services.h" +#include "htc_packet.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* TODO.. for BMI */ +#define ENDPOINT1 0 +// TODO -remove me, but we have to fix BMI first +#define HTC_MAILBOX_NUM_MAX 4 + +/* this is the amount of header room required by users of HTC */ +#define HTC_HEADER_LEN HTC_HDR_LENGTH + +typedef void *HTC_HANDLE; + +typedef A_UINT16 HTC_SERVICE_ID; + +typedef struct _HTC_INIT_INFO { + void *pContext; /* context for target failure notification */ + void (*TargetFailure)(void *Instance, A_STATUS Status); +} HTC_INIT_INFO; + +/* per service connection send completion */ +typedef void (*HTC_EP_SEND_PKT_COMPLETE)(void *,HTC_PACKET *); +/* per service connection pkt received */ +typedef void (*HTC_EP_RECV_PKT)(void *,HTC_PACKET *); + +/* Optional per service connection receive buffer re-fill callback, + * On some OSes (like Linux) packets are allocated from a global pool and indicated up + * to the network stack. The driver never gets the packets back from the OS. For these OSes + * a refill callback can be used to allocate and re-queue buffers into HTC. + * + * On other OSes, the network stack can call into the driver's OS-specifc "return_packet" handler and + * the driver can re-queue these buffers into HTC. In this regard a refill callback is + * unnecessary */ +typedef void (*HTC_EP_RECV_REFILL)(void *, HTC_ENDPOINT_ID Endpoint); + +/* Optional per service connection receive buffer allocation callback. + * On some systems packet buffers are an extremely limited resource. Rather than + * queue largest-possible-sized buffers to HTC, some systems would rather + * allocate a specific size as the packet is received. The trade off is + * slightly more processing (callback invoked for each RX packet) + * for the benefit of committing fewer buffer resources into HTC. + * + * The callback is provided the length of the pending packet to fetch. This includes the + * HTC header length plus the length of payload. The callback can return a pointer to + * the allocated HTC packet for immediate use. + * + * NOTE*** This callback is mutually exclusive with the the refill callback above. + * + * */ +typedef HTC_PACKET *(*HTC_EP_RECV_ALLOC)(void *, HTC_ENDPOINT_ID Endpoint, int Length); + +typedef enum _HTC_SEND_FULL_ACTION { + HTC_SEND_FULL_KEEP = 0, /* packet that overflowed should be kept in the queue */ + HTC_SEND_FULL_DROP = 1, /* packet that overflowed should be dropped */ +} HTC_SEND_FULL_ACTION; + +/* Optional per service connection callback when a send queue is full. This can occur if the + * host continues queueing up TX packets faster than credits can arrive + * To prevent the host (on some Oses like Linux) from continuously queueing packets + * and consuming resources, this callback is provided so that that the host + * can disable TX in the subsystem (i.e. network stack). + * This callback is invoked for each packet that "overflows" the HTC queue. The callback can + * determine whether the new packet that overflowed the queue can be kept (HTC_SEND_FULL_KEEP) or + * dropped (HTC_SEND_FULL_DROP). If a packet is dropped, the EpTxComplete handler will be called + * and the packet's status field will be set to A_NO_RESOURCE. + * Other OSes require a "per-packet" indication for each completed TX packet, this + * closed loop mechanism will prevent the network stack from overunning the NIC + * The packet to keep or drop is passed for inspection to the registered handler the handler + * must ONLY inspect the packet, it may not free or reclaim the packet. */ +typedef HTC_SEND_FULL_ACTION (*HTC_EP_SEND_QUEUE_FULL)(void *, HTC_PACKET *pPacket); + +typedef struct _HTC_EP_CALLBACKS { + void *pContext; /* context for each callback */ + HTC_EP_SEND_PKT_COMPLETE EpTxComplete; /* tx completion callback for connected endpoint */ + HTC_EP_RECV_PKT EpRecv; /* receive callback for connected endpoint */ + HTC_EP_RECV_REFILL EpRecvRefill; /* OPTIONAL receive re-fill callback for connected endpoint */ + HTC_EP_SEND_QUEUE_FULL EpSendFull; /* OPTIONAL send full callback */ + HTC_EP_RECV_ALLOC EpRecvAlloc; /* OPTIONAL recv allocation callback */ +} HTC_EP_CALLBACKS; + +/* service connection information */ +typedef struct _HTC_SERVICE_CONNECT_REQ { + HTC_SERVICE_ID ServiceID; /* service ID to connect to */ + A_UINT16 ConnectionFlags; /* connection flags, see htc protocol definition */ + A_UINT8 *pMetaData; /* ptr to optional service-specific meta-data */ + A_UINT8 MetaDataLength; /* optional meta data length */ + HTC_EP_CALLBACKS EpCallbacks; /* endpoint callbacks */ + int MaxSendQueueDepth; /* maximum depth of any send queue */ +} HTC_SERVICE_CONNECT_REQ; + +/* service connection response information */ +typedef struct _HTC_SERVICE_CONNECT_RESP { + A_UINT8 *pMetaData; /* caller supplied buffer to optional meta-data */ + A_UINT8 BufferLength; /* length of caller supplied buffer */ + A_UINT8 ActualLength; /* actual length of meta data */ + HTC_ENDPOINT_ID Endpoint; /* endpoint to communicate over */ + int MaxMsgLength; /* max length of all messages over this endpoint */ + A_UINT8 ConnectRespCode; /* connect response code from target */ +} HTC_SERVICE_CONNECT_RESP; + +/* endpoint distribution structure */ +typedef struct _HTC_ENDPOINT_CREDIT_DIST { + struct _HTC_ENDPOINT_CREDIT_DIST *pNext; + struct _HTC_ENDPOINT_CREDIT_DIST *pPrev; + HTC_SERVICE_ID ServiceID; /* Service ID (set by HTC) */ + HTC_ENDPOINT_ID Endpoint; /* endpoint for this distribution struct (set by HTC) */ + A_UINT32 DistFlags; /* distribution flags, distribution function can + set default activity using SET_EP_ACTIVE() macro */ + int TxCreditsNorm; /* credits for normal operation, anything above this + indicates the endpoint is over-subscribed, this field + is only relevant to the credit distribution function */ + int TxCreditsMin; /* floor for credit distribution, this field is + only relevant to the credit distribution function */ + int TxCreditsAssigned; /* number of credits assigned to this EP, this field + is only relevant to the credit dist function */ + int TxCredits; /* current credits available, this field is used by + HTC to determine whether a message can be sent or + must be queued */ + int TxCreditsToDist; /* pending credits to distribute on this endpoint, this + is set by HTC when credit reports arrive. + The credit distribution functions sets this to zero + when it distributes the credits */ + int TxCreditsSeek; /* this is the number of credits that the current pending TX + packet needs to transmit. This is set by HTC when + and endpoint needs credits in order to transmit */ + int TxCreditSize; /* size in bytes of each credit (set by HTC) */ + int TxCreditsPerMaxMsg; /* credits required for a maximum sized messages (set by HTC) */ + void *pHTCReserved; /* reserved for HTC use */ + int TxQueueDepth; /* current depth of TX queue , i.e. messages waiting for credits + This field is valid only when HTC_CREDIT_DIST_ACTIVITY_CHANGE + or HTC_CREDIT_DIST_SEND_COMPLETE is indicated on an endpoint + that has non-zero credits to recover + */ +} HTC_ENDPOINT_CREDIT_DIST; + +#define HTC_EP_ACTIVE ((A_UINT32) (1 << 31)) + +/* macro to check if an endpoint has gone active, useful for credit + * distributions */ +#define IS_EP_ACTIVE(epDist) ((epDist)->DistFlags & HTC_EP_ACTIVE) +#define SET_EP_ACTIVE(epDist) (epDist)->DistFlags |= HTC_EP_ACTIVE + + /* credit distibution code that is passed into the distrbution function, + * there are mandatory and optional codes that must be handled */ +typedef enum _HTC_CREDIT_DIST_REASON { + HTC_CREDIT_DIST_SEND_COMPLETE = 0, /* credits available as a result of completed + send operations (MANDATORY) resulting in credit reports */ + HTC_CREDIT_DIST_ACTIVITY_CHANGE = 1, /* a change in endpoint activity occured (OPTIONAL) */ + HTC_CREDIT_DIST_SEEK_CREDITS, /* an endpoint needs to "seek" credits (OPTIONAL) */ + HTC_DUMP_CREDIT_STATE /* for debugging, dump any state information that is kept by + the distribution function */ +} HTC_CREDIT_DIST_REASON; + +typedef void (*HTC_CREDIT_DIST_CALLBACK)(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + HTC_CREDIT_DIST_REASON Reason); + +typedef void (*HTC_CREDIT_INIT_CALLBACK)(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + int TotalCredits); + + /* endpoint statistics action */ +typedef enum _HTC_ENDPOINT_STAT_ACTION { + HTC_EP_STAT_SAMPLE = 0, /* only read statistics */ + HTC_EP_STAT_SAMPLE_AND_CLEAR = 1, /* sample and immediately clear statistics */ + HTC_EP_STAT_CLEAR /* clear only */ +} HTC_ENDPOINT_STAT_ACTION; + + /* endpoint statistics */ +typedef struct _HTC_ENDPOINT_STATS { + A_UINT32 TxCreditLowIndications; /* number of times the host set the credit-low flag in a send message on + this endpoint */ + A_UINT32 TxIssued; /* running count of TX packets issued */ + A_UINT32 TxDropped; /* tx packets that were dropped */ + A_UINT32 TxCreditRpts; /* running count of total credit reports received for this endpoint */ + A_UINT32 TxCreditRptsFromRx; /* credit reports received from this endpoint's RX packets */ + A_UINT32 TxCreditRptsFromOther; /* credit reports received from RX packets of other endpoints */ + A_UINT32 TxCreditRptsFromEp0; /* credit reports received from endpoint 0 RX packets */ + A_UINT32 TxCreditsFromRx; /* count of credits received via Rx packets on this endpoint */ + A_UINT32 TxCreditsFromOther; /* count of credits received via another endpoint */ + A_UINT32 TxCreditsFromEp0; /* count of credits received via another endpoint */ + A_UINT32 TxCreditsConsummed; /* count of consummed credits */ + A_UINT32 TxCreditsReturned; /* count of credits returned */ + A_UINT32 RxReceived; /* count of RX packets received */ + A_UINT32 RxLookAheads; /* count of lookahead records + found in messages received on this endpoint */ +} HTC_ENDPOINT_STATS; + +/* ------ Function Prototypes ------ */ +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Create an instance of HTC over the underlying HIF device + @function name: HTCCreate + @input: HifDevice - hif device handle, + pInfo - initialization information + @output: + @return: HTC_HANDLE on success, NULL on failure + @notes: + @example: + @see also: HTCDestroy ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +HTC_HANDLE HTCCreate(void *HifDevice, HTC_INIT_INFO *pInfo); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Get the underlying HIF device handle + @function name: HTCGetHifDevice + @input: HTCHandle - handle passed into the AddInstance callback + @output: + @return: opaque HIF device handle usable in HIF API calls. + @notes: + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void *HTCGetHifDevice(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Set credit distribution parameters + @function name: HTCSetCreditDistribution + @input: HTCHandle - HTC handle + pCreditDistCont - caller supplied context to pass into distribution functions + CreditDistFunc - Distribution function callback + CreditDistInit - Credit Distribution initialization callback + ServicePriorityOrder - Array containing list of service IDs, lowest index is highest + priority + ListLength - number of elements in ServicePriorityOrder + @output: + @return: + @notes: The user can set a custom credit distribution function to handle special requirements + for each endpoint. A default credit distribution routine can be used by setting + CreditInitFunc to NULL. The default credit distribution is only provided for simple + "fair" credit distribution without regard to any prioritization. + + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCSetCreditDistribution(HTC_HANDLE HTCHandle, + void *pCreditDistContext, + HTC_CREDIT_DIST_CALLBACK CreditDistFunc, + HTC_CREDIT_INIT_CALLBACK CreditInitFunc, + HTC_SERVICE_ID ServicePriorityOrder[], + int ListLength); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Wait for the target to indicate the HTC layer is ready + @function name: HTCWaitTarget + @input: HTCHandle - HTC handle + @output: + @return: + @notes: This API blocks until the target responds with an HTC ready message. + The caller should not connect services until the target has indicated it is + ready. + @example: + @see also: HTCConnectService ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCWaitTarget(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Start target service communications + @function name: HTCStart + @input: HTCHandle - HTC handle + @output: + @return: + @notes: This API indicates to the target that the service connection phase is complete + and the target can freely start all connected services. This API should only be + called AFTER all service connections have been made. TCStart will issue a + SETUP_COMPLETE message to the target to indicate that all service connections + have been made and the target can start communicating over the endpoints. + @example: + @see also: HTCConnectService ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCStart(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Add receive packet to HTC + @function name: HTCAddReceivePkt + @input: HTCHandle - HTC handle + pPacket - HTC receive packet to add + @output: + @return: A_OK on success + @notes: user must supply HTC packets for capturing incomming HTC frames. The caller + must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL() + macro. + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Connect to an HTC service + @function name: HTCConnectService + @input: HTCHandle - HTC handle + pReq - connection details + @output: pResp - connection response + @return: + @notes: Service connections must be performed before HTCStart. User provides callback handlers + for various endpoint events. + @example: + @see also: HTCStart ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCConnectService(HTC_HANDLE HTCHandle, + HTC_SERVICE_CONNECT_REQ *pReq, + HTC_SERVICE_CONNECT_RESP *pResp); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Send an HTC packet + @function name: HTCSendPkt + @input: HTCHandle - HTC handle + pPacket - packet to send + @output: + @return: A_OK + @notes: Caller must initialize packet using SET_HTC_PACKET_INFO_TX() macro. + This interface is fully asynchronous. On error, HTC SendPkt will + call the registered Endpoint callback to cleanup the packet. + @example: + @see also: HTCFlushEndpoint ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Stop HTC service communications + @function name: HTCStop + @input: HTCHandle - HTC handle + @output: + @return: + @notes: HTC communications is halted. All receive and pending TX packets will + be flushed. + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCStop(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Destory HTC service + @function name: HTCDestroy + @input: HTCHandle + @output: + @return: + @notes: This cleans up all resources allocated by HTCCreate(). + @example: + @see also: HTCCreate ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCDestroy(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Flush pending TX packets + @function name: HTCFlushEndpoint + @input: HTCHandle - HTC handle + Endpoint - Endpoint to flush + Tag - flush tag + @output: + @return: + @notes: The Tag parameter is used to selectively flush packets with matching tags. + The value of 0 forces all packets to be flush regardless of tag. + @example: + @see also: HTCSendPkt ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Dump credit distribution state + @function name: HTCDumpCreditStates + @input: HTCHandle - HTC handle + @output: + @return: + @notes: This dumps all credit distribution information to the debugger + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCDumpCreditStates(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Indicate a traffic activity change on an endpoint + @function name: HTCIndicateActivityChange + @input: HTCHandle - HTC handle + Endpoint - endpoint in which activity has changed + Active - TRUE if active, FALSE if it has become inactive + @output: + @return: + @notes: This triggers the registered credit distribution function to + re-adjust credits for active/inactive endpoints. + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCIndicateActivityChange(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + A_BOOL Active); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Get endpoint statistics + @function name: HTCGetEndpointStatistics + @input: HTCHandle - HTC handle + Endpoint - Endpoint identifier + Action - action to take with statistics + @output: + pStats - statistics that were sampled (can be NULL if Action is HTC_EP_STAT_CLEAR) + + @return: TRUE if statistics profiling is enabled, otherwise FALSE. + + @notes: Statistics is a compile-time option and this function may return FALSE + if HTC is not compiled with profiling. + + The caller can specify the statistic "action" to take when sampling + the statistics. This includes: + + HTC_EP_STAT_SAMPLE: The pStats structure is filled with the current values. + HTC_EP_STAT_SAMPLE_AND_CLEAR: The structure is filled and the current statistics + are cleared. + HTC_EP_STAT_CLEA : the statistics are cleared, the called can pass a NULL value for + pStats + + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_BOOL HTCGetEndpointStatistics(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + HTC_ENDPOINT_STAT_ACTION Action, + HTC_ENDPOINT_STATS *pStats); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Unblock HTC message reception + @function name: HTCUnblockRecv + @input: HTCHandle - HTC handle + @output: + @return: + @notes: + HTC will block the receiver if the EpRecvAlloc callback fails to provide a packet. + The caller can use this API to indicate to HTC when resources (buffers) are available + such that the receiver can be unblocked and HTC may re-attempt fetching the pending message. + + This API is not required if the user uses the EpRecvRefill callback or uses the HTCAddReceivePacket() + API to recycle or provide receive packets to HTC. + + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCUnblockRecv(HTC_HANDLE HTCHandle); + +/* internally used functions for testing... */ +void HTCEnableRecv(HTC_HANDLE HTCHandle); +void HTCDisableRecv(HTC_HANDLE HTCHandle); + +#ifdef __cplusplus +} +#endif + +#endif /* _HTC_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/htc_debug.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc_debug.h --- linux-2.6.26/drivers/net/wireless/ath6k/htc_debug.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc_debug.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,69 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef HTC_DEBUG_H_ +#define HTC_DEBUG_H_ + +/* ------- Debug related stuff ------- */ +enum { + ATH_DEBUG_SEND = 0x0001, + ATH_DEBUG_RECV = 0x0002, + ATH_DEBUG_SYNC = 0x0004, + ATH_DEBUG_DUMP = 0x0008, + ATH_DEBUG_IRQ = 0x0010, + ATH_DEBUG_TRC = 0x0020, + ATH_DEBUG_WARN = 0x0040, + ATH_DEBUG_ERR = 0x0080, + ATH_DEBUG_ANY = 0xFFFF, +}; + +#ifdef DEBUG + +// TODO FIX usage of A_PRINTF! +#define AR_DEBUG_LVL_CHECK(lvl) (debughtc & (lvl)) +#define AR_DEBUG_PRINTBUF(buffer, length, desc) do { \ + if (debughtc & ATH_DEBUG_DUMP) { \ + DebugDumpBytes(buffer, length,desc); \ + } \ +} while(0) +#define PRINTX_ARG(arg...) arg +#define AR_DEBUG_PRINTF(flags, args) do { \ + if (debughtc & (flags)) { \ + A_PRINTF(KERN_ALERT PRINTX_ARG args); \ + } \ +} while (0) +//#define AR_DEBUG_ASSERT(test) do { \ + //if (!(test)) { \ + //AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test)); \ + //} \ +//} while(0) +extern int debughtc; +#else +#define AR_DEBUG_PRINTF(flags, args) +#define AR_DEBUG_PRINTBUF(buffer, length, desc) +#define AR_DEBUG_ASSERT(test) +#define AR_DEBUG_LVL_CHECK(lvl) 0 +#endif + +void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription); + +#endif /*HTC_DEBUG_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/htc_internal.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc_internal.h --- linux-2.6.26/drivers/net/wireless/ath6k/htc_internal.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc_internal.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,177 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HTC_INTERNAL_H_ +#define _HTC_INTERNAL_H_ + +/* for debugging, uncomment this to capture the last frame header, on frame header + * processing errors, the last frame header is dump for comparison */ +//#define HTC_CAPTURE_LAST_FRAME + +//#define HTC_EP_STAT_PROFILING + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Header files */ +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "a_debug.h" +#include "htc.h" +#include "htc_api.h" +#include "bmi_msg.h" +#include "hif.h" +#include "ar6k.h" + +/* HTC operational parameters */ +#define HTC_TARGET_RESPONSE_TIMEOUT 2000 /* in ms */ +#define HTC_TARGET_DEBUG_INTR_MASK 0x01 +#define HTC_TARGET_CREDIT_INTR_MASK 0xF0 + +typedef struct _HTC_ENDPOINT { + HTC_SERVICE_ID ServiceID; /* service ID this endpoint is bound to + non-zero value means this endpoint is in use */ + HTC_PACKET_QUEUE TxQueue; /* HTC frame buffer TX queue */ + HTC_PACKET_QUEUE RxBuffers; /* HTC frame buffer RX list */ + HTC_ENDPOINT_CREDIT_DIST CreditDist; /* credit distribution structure (exposed to driver layer) */ + HTC_EP_CALLBACKS EpCallBacks; /* callbacks associated with this endpoint */ + int MaxTxQueueDepth; /* max depth of the TX queue before we need to + call driver's full handler */ + int CurrentTxQueueDepth; /* current TX queue depth */ + int MaxMsgLength; /* max length of endpoint message */ +#ifdef HTC_EP_STAT_PROFILING + HTC_ENDPOINT_STATS EndPointStats; /* endpoint statistics */ +#endif + int TxProcessCount; +} HTC_ENDPOINT; + +#ifdef HTC_EP_STAT_PROFILING +#define INC_HTC_EP_STAT(p,stat,count) (p)->EndPointStats.stat += (count); +#else +#define INC_HTC_EP_STAT(p,stat,count) +#endif + +#define HTC_SERVICE_TX_PACKET_TAG HTC_TX_PACKET_TAG_INTERNAL + +#define NUM_CONTROL_BUFFERS 8 +#define NUM_CONTROL_TX_BUFFERS 2 +#define NUM_CONTROL_RX_BUFFERS (NUM_CONTROL_BUFFERS - NUM_CONTROL_TX_BUFFERS) + +typedef struct HTC_CONTROL_BUFFER { + HTC_PACKET HtcPacket; + A_UINT8 *Buffer; +} HTC_CONTROL_BUFFER; + +/* our HTC target state */ +typedef struct _HTC_TARGET { + HTC_ENDPOINT EndPoint[ENDPOINT_MAX]; + HTC_CONTROL_BUFFER HTCControlBuffers[NUM_CONTROL_BUFFERS]; + HTC_ENDPOINT_CREDIT_DIST *EpCreditDistributionListHead; + HTC_PACKET_QUEUE ControlBufferTXFreeList; + HTC_PACKET_QUEUE ControlBufferRXFreeList; + HTC_CREDIT_DIST_CALLBACK DistributeCredits; + HTC_CREDIT_INIT_CALLBACK InitCredits; + void *pCredDistContext; + int TargetCredits; + int TargetCreditSize; + A_MUTEX_T HTCLock; + A_MUTEX_T HTCRxLock; + A_MUTEX_T HTCTxLock; + AR6K_DEVICE Device; /* AR6K - specific state */ + A_UINT32 HTCStateFlags; + HTC_ENDPOINT_ID EpWaitingForBuffers; + A_BOOL TargetFailure; +#define HTC_STATE_WAIT_BUFFERS (1 << 0) +#define HTC_STATE_STOPPING (1 << 1) +#ifdef HTC_CAPTURE_LAST_FRAME + HTC_FRAME_HDR LastFrameHdr; /* useful for debugging */ + A_UINT8 LastTrailer[256]; + A_UINT8 LastTrailerLength; +#endif + HTC_INIT_INFO HTCInitInfo; +} HTC_TARGET; + +#define HTC_STOPPING(t) ((t)->HTCStateFlags & HTC_STATE_STOPPING) +#define LOCK_HTC(t) A_MUTEX_LOCK(&(t)->HTCLock); +#define UNLOCK_HTC(t) A_MUTEX_UNLOCK(&(t)->HTCLock); +#define LOCK_HTC_RX(t) A_MUTEX_LOCK(&(t)->HTCRxLock); +#define UNLOCK_HTC_RX(t) A_MUTEX_UNLOCK(&(t)->HTCRxLock); +#define LOCK_HTC_TX(t) A_MUTEX_LOCK(&(t)->HTCTxLock); +#define UNLOCK_HTC_TX(t) A_MUTEX_UNLOCK(&(t)->HTCTxLock); + +#define GET_HTC_TARGET_FROM_HANDLE(hnd) ((HTC_TARGET *)(hnd)) +#define HTC_RECYCLE_RX_PKT(target,p,e) \ +{ \ + if ((e)->EpCallBacks.EpRecvAlloc != NULL) { \ + HTC_PACKET_RESET_RX(pPacket); \ + pPacket->Status = A_ECANCELED; \ + (e)->EpCallBacks.EpRecv((e)->EpCallBacks.pContext, \ + (p)); \ + } else { \ + HTC_PACKET_RESET_RX(pPacket); \ + HTCAddReceivePkt((HTC_HANDLE)(target),(p)); \ + } \ +} + +/* internal HTC functions */ +void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket); +void HTCControlRecv(void *Context, HTC_PACKET *pPacket); +A_STATUS HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket); +HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList); +void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList); +A_STATUS HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT8 Flags); +A_STATUS HTCIssueRecv(HTC_TARGET *target, HTC_PACKET *pPacket); +void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket); +A_STATUS HTCRecvMessagePendingHandler(void *Context, A_UINT32* LookAhead, A_BOOL *pAsyncProc); +void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint); +A_STATUS HTCSendSetupComplete(HTC_TARGET *target); +void HTCFlushRecvBuffers(HTC_TARGET *target); +void HTCFlushSendPkts(HTC_TARGET *target); +void DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist); +void DumpCreditDistStates(HTC_TARGET *target); +void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription); + +static INLINE HTC_PACKET *HTC_ALLOC_CONTROL_TX(HTC_TARGET *target) { + HTC_PACKET *pPacket = HTCAllocControlBuffer(target,&target->ControlBufferTXFreeList); + if (pPacket != NULL) { + /* set payload pointer area with some headroom */ + pPacket->pBuffer = pPacket->pBufferStart + HTC_HDR_LENGTH; + } + return pPacket; +} + +#define HTC_FREE_CONTROL_TX(t,p) HTCFreeControlBuffer((t),(p),&(t)->ControlBufferTXFreeList) +#define HTC_ALLOC_CONTROL_RX(t) HTCAllocControlBuffer((t),&(t)->ControlBufferRXFreeList) +#define HTC_FREE_CONTROL_RX(t,p) \ +{ \ + HTC_PACKET_RESET_RX(p); \ + HTCFreeControlBuffer((t),(p),&(t)->ControlBufferRXFreeList); \ +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HTC_INTERNAL_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/htc_packet.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc_packet.h --- linux-2.6.26/drivers/net/wireless/ath6k/htc_packet.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc_packet.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,162 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef HTC_PACKET_H_ +#define HTC_PACKET_H_ + + +#include "dl_list.h" + +/* ------ Endpoint IDS ------ */ +typedef enum +{ + ENDPOINT_UNUSED = -1, + ENDPOINT_0 = 0, + ENDPOINT_1 = 1, + ENDPOINT_2 = 2, + ENDPOINT_3, + ENDPOINT_4, + ENDPOINT_5, + ENDPOINT_6, + ENDPOINT_7, + ENDPOINT_8, + ENDPOINT_MAX, +} HTC_ENDPOINT_ID; + +struct _HTC_PACKET; + +typedef void (* HTC_PACKET_COMPLETION)(void *,struct _HTC_PACKET *); + +typedef A_UINT16 HTC_TX_TAG; + +typedef struct _HTC_TX_PACKET_INFO { + HTC_TX_TAG Tag; /* tag used to selective flush packets */ +} HTC_TX_PACKET_INFO; + +#define HTC_TX_PACKET_TAG_ALL 0 /* a tag of zero is reserved and used to flush ALL packets */ +#define HTC_TX_PACKET_TAG_INTERNAL 1 /* internal tags start here */ +#define HTC_TX_PACKET_TAG_USER_DEFINED (HTC_TX_PACKET_TAG_INTERNAL + 9) /* user-defined tags start here */ + +typedef struct _HTC_RX_PACKET_INFO { + A_UINT32 IndicationFlags; +} HTC_RX_PACKET_INFO; + +#define HTC_RX_FLAGS_INDICATE_MORE_PKTS (1 << 0) + +/* wrapper around endpoint-specific packets */ +typedef struct _HTC_PACKET { + DL_LIST ListLink; /* double link */ + void *pPktContext; /* caller's per packet specific context */ + + A_UINT8 *pBufferStart; /* the true buffer start , the caller can + store the real buffer start here. In + receive callbacks, the HTC layer sets pBuffer + to the start of the payload past the header. This + field allows the caller to reset pBuffer when it + recycles receive packets back to HTC */ + /* + * Pointer to the start of the buffer. In the transmit + * direction this points to the start of the payload. In the + * receive direction, however, the buffer when queued up + * points to the start of the HTC header but when returned + * to the caller points to the start of the payload + */ + A_UINT8 *pBuffer; /* payload start (RX/TX) */ + A_UINT32 BufferLength; /* length of buffer */ + A_UINT32 ActualLength; /* actual length of payload */ + HTC_ENDPOINT_ID Endpoint; /* endpoint that this packet was sent/recv'd from */ + A_STATUS Status; /* completion status */ + union { + HTC_TX_PACKET_INFO AsTx; /* Tx Packet specific info */ + HTC_RX_PACKET_INFO AsRx; /* Rx Packet specific info */ + } PktInfo; + + /* the following fields are for internal HTC use */ + HTC_PACKET_COMPLETION Completion; /* completion */ + void *pContext; /* HTC private completion context */ + A_UINT32 HTCReserved; /* reserved */ +} HTC_PACKET; + + + +#define COMPLETE_HTC_PACKET(p,status) \ +{ \ + (p)->Status = (status); \ + (p)->Completion((p)->pContext,(p)); \ +} + +#define INIT_HTC_PACKET_INFO(p,b,len) \ +{ \ + (p)->pBufferStart = (b); \ + (p)->BufferLength = (len); \ +} + +/* macro to set an initial RX packet for refilling HTC */ +#define SET_HTC_PACKET_INFO_RX_REFILL(p,c,b,len,ep) \ +{ \ + (p)->pPktContext = (c); \ + (p)->pBuffer = (b); \ + (p)->pBufferStart = (b); \ + (p)->BufferLength = (len); \ + (p)->Endpoint = (ep); \ +} + +/* fast macro to recycle an RX packet that will be re-queued to HTC */ +#define HTC_PACKET_RESET_RX(p) \ + (p)->pBuffer = (p)->pBufferStart + +/* macro to set packet parameters for TX */ +#define SET_HTC_PACKET_INFO_TX(p,c,b,len,ep,tag) \ +{ \ + (p)->pPktContext = (c); \ + (p)->pBuffer = (b); \ + (p)->ActualLength = (len); \ + (p)->Endpoint = (ep); \ + (p)->PktInfo.AsTx.Tag = (tag); \ +} + +/* HTC Packet Queueing Macros */ +typedef DL_LIST HTC_PACKET_QUEUE; +/* initialize queue */ +#define INIT_HTC_PACKET_QUEUE(pQ) DL_LIST_INIT((pQ)) +/* enqueue HTC packet to the tail of the queue */ +#define HTC_PACKET_ENQUEUE(pQ,p) DL_ListInsertTail((pQ),&(p)->ListLink) +/* test if a queue is empty */ +#define HTC_QUEUE_EMPTY(pQ) DL_LIST_IS_EMPTY((pQ)) +/* get packet at head without removing it */ +#define HTC_GET_PKT_AT_HEAD(pQ) A_CONTAINING_STRUCT((DL_LIST_GET_ITEM_AT_HEAD(pQ)),HTC_PACKET,ListLink); +/* remove a packet from the current list it is linked to */ +#define HTC_PACKET_REMOVE(p) DL_ListRemove(&(p)->ListLink) + +/* dequeue an HTC packet from the head of the queue */ +static INLINE HTC_PACKET *HTC_PACKET_DEQUEUE(HTC_PACKET_QUEUE *queue) { + DL_LIST *pItem = DL_ListRemoveItemFromHead(queue); + if (pItem != NULL) { + return A_CONTAINING_STRUCT(pItem, HTC_PACKET, ListLink); + } + return NULL; +} + +#define HTC_GET_ENDPOINT_FROM_PKT(p) (p)->Endpoint +#define HTC_GET_TAG_FROM_PKT(p) (p)->PktInfo.AsTx.Tag + +#endif /*HTC_PACKET_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/htc_recv.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc_recv.c --- linux-2.6.26/drivers/net/wireless/ath6k/htc_recv.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc_recv.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,785 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + +#define HTCIssueRecv(t, p) \ + DevRecvPacket(&(t)->Device, \ + (p), \ + (p)->ActualLength) + +#define DO_RCV_COMPLETION(t,p,e) \ +{ \ + if ((p)->ActualLength > 0) { \ + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" completing packet 0x%X (%d bytes) on ep : %d \n", \ + (A_UINT32)(p), (p)->ActualLength, (p)->Endpoint)); \ + (e)->EpCallBacks.EpRecv((e)->EpCallBacks.pContext, \ + (p)); \ + } else { \ + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" recycling empty packet \n")); \ + HTC_RECYCLE_RX_PKT((t), (p), (e)); \ + } \ +} + +#ifdef HTC_EP_STAT_PROFILING +#define HTC_RX_STAT_PROFILE(t,ep,lookAhead) \ +{ \ + LOCK_HTC_RX((t)); \ + INC_HTC_EP_STAT((ep), RxReceived, 1); \ + if ((lookAhead) != 0) { \ + INC_HTC_EP_STAT((ep), RxLookAheads, 1); \ + } \ + UNLOCK_HTC_RX((t)); \ +} +#else +#define HTC_RX_STAT_PROFILE(t,ep,lookAhead) +#endif + +static INLINE A_STATUS HTCProcessTrailer(HTC_TARGET *target, + A_UINT8 *pBuffer, + int Length, + A_UINT32 *pNextLookAhead, + HTC_ENDPOINT_ID FromEndpoint) +{ + HTC_RECORD_HDR *pRecord; + A_UINT8 *pRecordBuf; + HTC_LOOKAHEAD_REPORT *pLookAhead; + A_UINT8 *pOrigBuffer; + int origLength; + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessTrailer (length:%d) \n", Length)); + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + AR_DEBUG_PRINTBUF(pBuffer,Length,"Recv Trailer"); + } + + pOrigBuffer = pBuffer; + origLength = Length; + status = A_OK; + + while (Length > 0) { + + if (Length < sizeof(HTC_RECORD_HDR)) { + status = A_EPROTO; + break; + } + /* these are byte aligned structs */ + pRecord = (HTC_RECORD_HDR *)pBuffer; + Length -= sizeof(HTC_RECORD_HDR); + pBuffer += sizeof(HTC_RECORD_HDR); + + if (pRecord->Length > Length) { + /* no room left in buffer for record */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" invalid record length: %d (id:%d) buffer has: %d bytes left \n", + pRecord->Length, pRecord->RecordID, Length)); + status = A_EPROTO; + break; + } + /* start of record follows the header */ + pRecordBuf = pBuffer; + + switch (pRecord->RecordID) { + case HTC_RECORD_CREDITS: + AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_CREDIT_REPORT)); + HTCProcessCreditRpt(target, + (HTC_CREDIT_REPORT *)pRecordBuf, + pRecord->Length / (sizeof(HTC_CREDIT_REPORT)), + FromEndpoint); + break; + case HTC_RECORD_LOOKAHEAD: + AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_LOOKAHEAD_REPORT)); + pLookAhead = (HTC_LOOKAHEAD_REPORT *)pRecordBuf; + if ((pLookAhead->PreValid == ((~pLookAhead->PostValid) & 0xFF)) && + (pNextLookAhead != NULL)) { + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + (" LookAhead Report Found (pre valid:0x%X, post valid:0x%X) \n", + pLookAhead->PreValid, + pLookAhead->PostValid)); + + /* look ahead bytes are valid, copy them over */ + ((A_UINT8 *)pNextLookAhead)[0] = pLookAhead->LookAhead[0]; + ((A_UINT8 *)pNextLookAhead)[1] = pLookAhead->LookAhead[1]; + ((A_UINT8 *)pNextLookAhead)[2] = pLookAhead->LookAhead[2]; + ((A_UINT8 *)pNextLookAhead)[3] = pLookAhead->LookAhead[3]; + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + DebugDumpBytes((A_UINT8 *)pNextLookAhead,4,"Next Look Ahead"); + } + } + break; + default: + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" unhandled record: id:%d length:%d \n", + pRecord->RecordID, pRecord->Length)); + break; + } + + if (A_FAILED(status)) { + break; + } + + /* advance buffer past this record for next time around */ + pBuffer += pRecord->Length; + Length -= pRecord->Length; + } + + if (A_FAILED(status)) { + DebugDumpBytes(pOrigBuffer,origLength,"BAD Recv Trailer"); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessTrailer \n")); + return status; + +} + +/* process a received message (i.e. strip off header, process any trailer data) + * note : locks must be released when this function is called */ +static A_STATUS HTCProcessRecvHeader(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT32 *pNextLookAhead) +{ + A_UINT8 temp; + A_UINT8 *pBuf; + A_STATUS status = A_OK; + A_UINT16 payloadLen; + A_UINT32 lookAhead; + + pBuf = pPacket->pBuffer; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessRecvHeader \n")); + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + AR_DEBUG_PRINTBUF(pBuf,pPacket->ActualLength,"HTC Recv PKT"); + } + + do { + /* note, we cannot assume the alignment of pBuffer, so we use the safe macros to + * retrieve 16 bit fields */ + payloadLen = A_GET_UINT16_FIELD(pBuf, HTC_FRAME_HDR, PayloadLen); + + ((A_UINT8 *)&lookAhead)[0] = pBuf[0]; + ((A_UINT8 *)&lookAhead)[1] = pBuf[1]; + ((A_UINT8 *)&lookAhead)[2] = pBuf[2]; + ((A_UINT8 *)&lookAhead)[3] = pBuf[3]; + + if (lookAhead != pPacket->HTCReserved) { + /* somehow the lookahead that gave us the full read length did not + * reflect the actual header in the pending message */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCProcessRecvHeader, lookahead mismatch! \n")); + DebugDumpBytes((A_UINT8 *)&pPacket->HTCReserved,4,"Expected Message LookAhead"); + DebugDumpBytes(pBuf,sizeof(HTC_FRAME_HDR),"Current Frame Header"); +#ifdef HTC_CAPTURE_LAST_FRAME + DebugDumpBytes((A_UINT8 *)&target->LastFrameHdr,sizeof(HTC_FRAME_HDR),"Last Frame Header"); + if (target->LastTrailerLength != 0) { + DebugDumpBytes(target->LastTrailer, + target->LastTrailerLength, + "Last trailer"); + } +#endif + status = A_EPROTO; + break; + } + + /* get flags */ + temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, Flags); + + if (temp & HTC_FLAGS_RECV_TRAILER) { + /* this packet has a trailer */ + + /* extract the trailer length in control byte 0 */ + temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, ControlBytes[0]); + + if ((temp < sizeof(HTC_RECORD_HDR)) || (temp > payloadLen)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCProcessRecvHeader, invalid header (payloadlength should be :%d, CB[0] is:%d) \n", + payloadLen, temp)); + status = A_EPROTO; + break; + } + + /* process trailer data that follows HDR + application payload */ + status = HTCProcessTrailer(target, + (pBuf + HTC_HDR_LENGTH + payloadLen - temp), + temp, + pNextLookAhead, + pPacket->Endpoint); + + if (A_FAILED(status)) { + break; + } + +#ifdef HTC_CAPTURE_LAST_FRAME + A_MEMCPY(target->LastTrailer, (pBuf + HTC_HDR_LENGTH + payloadLen - temp), temp); + target->LastTrailerLength = temp; +#endif + /* trim length by trailer bytes */ + pPacket->ActualLength -= temp; + } +#ifdef HTC_CAPTURE_LAST_FRAME + else { + target->LastTrailerLength = 0; + } +#endif + + /* if we get to this point, the packet is good */ + /* remove header and adjust length */ + pPacket->pBuffer += HTC_HDR_LENGTH; + pPacket->ActualLength -= HTC_HDR_LENGTH; + + } while (FALSE); + + if (A_FAILED(status)) { + /* dump the whole packet */ + DebugDumpBytes(pBuf,pPacket->ActualLength,"BAD HTC Recv PKT"); + } else { +#ifdef HTC_CAPTURE_LAST_FRAME + A_MEMCPY(&target->LastFrameHdr,pBuf,sizeof(HTC_FRAME_HDR)); +#endif + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + if (pPacket->ActualLength > 0) { + AR_DEBUG_PRINTBUF(pPacket->pBuffer,pPacket->ActualLength,"HTC - Application Msg"); + } + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessRecvHeader \n")); + return status; +} + +/* asynchronous completion handler for recv packet fetching, when the device layer + * completes a read request, it will call this completion handler */ +void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + HTC_ENDPOINT *pEndpoint; + A_UINT32 nextLookAhead = 0; + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCRecvCompleteHandler (status:%d, ep:%d) \n", + pPacket->Status, pPacket->Endpoint)); + + AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX); + pEndpoint = &target->EndPoint[pPacket->Endpoint]; + pPacket->Completion = NULL; + + /* get completion status */ + status = pPacket->Status; + + do { + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HTCRecvCompleteHandler: request failed (status:%d, ep:%d) \n", + pPacket->Status, pPacket->Endpoint)); + break; + } + /* process the header for any trailer data */ + status = HTCProcessRecvHeader(target,pPacket,&nextLookAhead); + + if (A_FAILED(status)) { + break; + } + /* was there a lookahead for the next packet? */ + if (nextLookAhead != 0) { + A_STATUS nextStatus; + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("HTCRecvCompleteHandler - next look ahead was non-zero : 0x%X \n", + nextLookAhead)); + /* we have another packet, get the next packet fetch started (pipelined) before + * we call into the endpoint's callback, this will start another async request */ + nextStatus = HTCRecvMessagePendingHandler(target,&nextLookAhead,NULL); + if (A_EPROTO == nextStatus) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Next look ahead from recv header was INVALID\n")); + DebugDumpBytes((A_UINT8 *)&nextLookAhead, + 4, + "BAD lookahead from lookahead report"); + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("HTCRecvCompleteHandler - rechecking for more messages...\n")); + /* if we did not get anything on the look-ahead, + * call device layer to asynchronously re-check for messages. If we can keep the async + * processing going we get better performance. If there is a pending message we will keep processing + * messages asynchronously which should pipeline things nicely */ + DevCheckPendingRecvMsgsAsync(&target->Device); + } + + HTC_RX_STAT_PROFILE(target,pEndpoint,nextLookAhead); + DO_RCV_COMPLETION(target,pPacket,pEndpoint); + + } while (FALSE); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCRecvCompleteHandler , message fetch failed (status = %d) \n", + status)); + /* recyle this packet */ + HTC_RECYCLE_RX_PKT(target, pPacket, pEndpoint); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCRecvCompleteHandler\n")); +} + +/* synchronously wait for a control message from the target, + * This function is used at initialization time ONLY. At init messages + * on ENDPOINT 0 are expected. */ +A_STATUS HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket) +{ + A_STATUS status; + A_UINT32 lookAhead; + HTC_PACKET *pPacket = NULL; + HTC_FRAME_HDR *pHdr; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCWaitforControlMessage \n")); + + do { + + *ppControlPacket = NULL; + + /* call the polling function to see if we have a message */ + status = DevPollMboxMsgRecv(&target->Device, + &lookAhead, + HTC_TARGET_RESPONSE_TIMEOUT); + + if (A_FAILED(status)) { + break; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("HTCWaitforControlMessage : lookAhead : 0x%X \n", lookAhead)); + + /* check the lookahead */ + pHdr = (HTC_FRAME_HDR *)&lookAhead; + + if (pHdr->EndpointID != ENDPOINT_0) { + /* unexpected endpoint number, should be zero */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + if (A_FAILED(status)) { + /* bad message */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + pPacket = HTC_ALLOC_CONTROL_RX(target); + + if (pPacket == NULL) { + AR_DEBUG_ASSERT(FALSE); + status = A_NO_MEMORY; + break; + } + + pPacket->HTCReserved = lookAhead; + pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH; + + if (pPacket->ActualLength > pPacket->BufferLength) { + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + /* we want synchronous operation */ + pPacket->Completion = NULL; + + /* get the message from the device, this will block */ + status = HTCIssueRecv(target, pPacket); + + if (A_FAILED(status)) { + break; + } + + /* process receive header */ + status = HTCProcessRecvHeader(target,pPacket,NULL); + + pPacket->Status = status; + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCWaitforControlMessage, HTCProcessRecvHeader failed (status = %d) \n", + status)); + break; + } + + /* give the caller this control message packet, they are responsible to free */ + *ppControlPacket = pPacket; + + } while (FALSE); + + if (A_FAILED(status)) { + if (pPacket != NULL) { + /* cleanup buffer on error */ + HTC_FREE_CONTROL_RX(target,pPacket); + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCWaitforControlMessage \n")); + + return status; +} + +/* callback when device layer or lookahead report parsing detects a pending message */ +A_STATUS HTCRecvMessagePendingHandler(void *Context, A_UINT32 *LookAhead, A_BOOL *pAsyncProc) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + A_STATUS status = A_OK; + HTC_PACKET *pPacket = NULL; + HTC_FRAME_HDR *pHdr = NULL; + HTC_ENDPOINT *pEndpoint = NULL; + A_BOOL asyncProc = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCRecvMessagePendingHandler LookAhead:0x%X \n", *LookAhead)); + + if (IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(&target->Device)) { + /* We use async mode to get the packets if the device layer supports it. + * The device layer interfaces with HIF in which HIF may have restrictions on + * how interrupts are processed */ + asyncProc = TRUE; + } + + if (pAsyncProc != NULL) { + /* indicate to caller how we decided to process this */ + *pAsyncProc = asyncProc; + } + + while (TRUE) { + pHdr = (HTC_FRAME_HDR *)LookAhead; + + if (pHdr->EndpointID >= ENDPOINT_MAX) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Endpoint in look-ahead: %d \n",pHdr->EndpointID)); + /* invalid endpoint */ + status = A_EPROTO; + break; + } + + if (pHdr->PayloadLen > HTC_MAX_PAYLOAD_LENGTH) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Payload length %d exceeds max HTC : %d !\n", + pHdr->PayloadLen, HTC_MAX_PAYLOAD_LENGTH)); + status = A_EPROTO; + break; + } + + pEndpoint = &target->EndPoint[pHdr->EndpointID]; + + if (0 == pEndpoint->ServiceID) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Endpoint %d is not connected !\n",pHdr->EndpointID)); + /* endpoint isn't even connected */ + status = A_EPROTO; + break; + } + + if (pEndpoint->EpCallBacks.EpRecvAlloc != NULL) { + /* user is using a per-packet allocation callback */ + pPacket = pEndpoint->EpCallBacks.EpRecvAlloc(pEndpoint->EpCallBacks.pContext, + (HTC_ENDPOINT_ID) pHdr->EndpointID, + pHdr->PayloadLen + sizeof(HTC_FRAME_HDR)); + + /* lock RX, in case this allocation fails, we need to update internal state below */ + + LOCK_HTC_RX(target); + + } else { + /* user is using a refill handler that can refill multiple HTC buffers */ + /* lock RX to get a buffer */ + LOCK_HTC_RX(target); + + /* get a packet from the endpoint recv queue */ + pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers); + + if (NULL == pPacket) { + /* check for refill handler */ + if (pEndpoint->EpCallBacks.EpRecvRefill != NULL) { + UNLOCK_HTC_RX(target); + /* call the re-fill handler */ + pEndpoint->EpCallBacks.EpRecvRefill(pEndpoint->EpCallBacks.pContext, + (HTC_ENDPOINT_ID) pHdr->EndpointID); + LOCK_HTC_RX(target); + /* check if we have more buffers */ + pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers); + /* fall through */ + } + } + } + + if (NULL == pPacket) { + /* this is not an error, we simply need to mark that we are waiting for buffers.*/ + target->HTCStateFlags |= HTC_STATE_WAIT_BUFFERS; + target->EpWaitingForBuffers = (HTC_ENDPOINT_ID) pHdr->EndpointID; + status = A_NO_MEMORY; + } + + if (HTC_STOPPING(target)) { + status = A_ECANCELED; + } + + UNLOCK_HTC_RX(target); + + if (A_FAILED(status)) { + /* no buffers or stopping */ + break; + } + + pPacket->PktInfo.AsRx.IndicationFlags = 0; + + AR_DEBUG_ASSERT(pPacket->Endpoint == pHdr->EndpointID); + + /* make sure this message can fit in the endpoint buffer */ + if ((pHdr->PayloadLen + HTC_HDR_LENGTH) > pPacket->BufferLength) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Payload Length Error : header reports payload of: %d, endpoint buffer size: %d \n", + pHdr->PayloadLen, pPacket->BufferLength)); + status = A_EPROTO; + break; + } + + pPacket->HTCReserved = *LookAhead; /* set expected look ahead */ + /* set the amount of data to fetch */ + pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH; + + if (asyncProc) { + /* we use async mode to get the packet if the device layer supports it + * set our callback and context */ + pPacket->Completion = HTCRecvCompleteHandler; + pPacket->pContext = target; + } else { + /* fully synchronous */ + pPacket->Completion = NULL; + } + + /* go fetch the packet */ + status = HTCIssueRecv(target, pPacket); + + if (A_FAILED(status)) { + break; + } + + if (asyncProc) { + /* we did this asynchronously so we can get out of the loop, the asynch processing + * creates a chain of requests to continue processing pending messages in the + * context of callbacks */ + break; + } + + /* in the sync case, we process the packet, check lookaheads and then repeat */ + + *LookAhead = 0; + status = HTCProcessRecvHeader(target,pPacket,LookAhead); + + if (A_FAILED(status)) { + break; + } + + HTC_RX_STAT_PROFILE(target,pEndpoint,*LookAhead); + + /* check lookahead to see if we can indicate next packet hint to recv callback */ + if (LookAhead != 0) { + pHdr = (HTC_FRAME_HDR *)&LookAhead; + /* check to see if the "next" packet is from the same endpoint of the + completing packet */ + if (pHdr->EndpointID == pPacket->Endpoint) { + /* check that there is a buffer available to actually fetch it + * NOTE: no need to lock RX here , since we are synchronously processing RX + * and we are only looking at the queue (not modifying it) */ + if (!HTC_QUEUE_EMPTY(&pEndpoint->RxBuffers)) { + /* provide a hint that there are more RX packets to fetch */ + pPacket->PktInfo.AsRx.IndicationFlags |= HTC_RX_FLAGS_INDICATE_MORE_PKTS; + } + } + } + + DO_RCV_COMPLETION(target,pPacket,pEndpoint); + + pPacket = NULL; + + if (0 == *LookAhead) { + break; + } + + /* check whether other OS contexts have queued any WMI command/data for WLAN. + * This check is needed only if WLAN Tx and Rx happens in same thread context */ + A_CHECK_DRV_TX(); + } + + if (A_NO_MEMORY == status) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" Endpoint :%d has no buffers, blocking receiver to prevent overrun.. \n", + (pHdr != NULL) ? pHdr->EndpointID : 0xFFFF)); + /* try to stop receive at the device layer */ + DevStopRecv(&target->Device, asyncProc ? DEV_STOP_RECV_ASYNC : DEV_STOP_RECV_SYNC); + status = A_OK; + } else if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Failed to get pending message : LookAhead Value: 0x%X (status = %d) \n", + *LookAhead, status)); + if (pPacket != NULL) { + /* clean up packet on error */ + HTC_RECYCLE_RX_PKT(target, pPacket, pEndpoint); + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCRecvMessagePendingHandler \n")); + + return status; +} + +/* Makes a buffer available to the HTC module */ +A_STATUS HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint; + A_BOOL unblockRecv = FALSE; + A_STATUS status = A_OK; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("+- HTCAddReceivePkt: endPointId: %d, buffer: 0x%X, length: %d\n", + pPacket->Endpoint, (A_UINT32)pPacket->pBuffer, pPacket->BufferLength)); + + do { + AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX); + + pEndpoint = &target->EndPoint[pPacket->Endpoint]; + + LOCK_HTC_RX(target); + + if (HTC_STOPPING(target)) { + pPacket->Status = A_ECANCELED; + status = A_ECANCELED; + UNLOCK_HTC_RX(target); + pEndpoint->EpCallBacks.EpRecv(pEndpoint->EpCallBacks.pContext, pPacket); + break; + } + + /* store receive packet */ + HTC_PACKET_ENQUEUE(&pEndpoint->RxBuffers, pPacket); + + /* check if we are blocked waiting for a new buffer */ + if (target->HTCStateFlags & HTC_STATE_WAIT_BUFFERS) { + if (target->EpWaitingForBuffers == pPacket->Endpoint) { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" receiver was blocked on ep:%d, unblocking.. \n", + target->EpWaitingForBuffers)); + target->HTCStateFlags &= ~HTC_STATE_WAIT_BUFFERS; + target->EpWaitingForBuffers = ENDPOINT_MAX; + unblockRecv = TRUE; + } + } + + UNLOCK_HTC_RX(target); + + if (unblockRecv && !HTC_STOPPING(target)) { + /* TODO : implement a buffer threshold count? */ + DevEnableRecv(&target->Device,DEV_ENABLE_RECV_SYNC); + } + + } while (FALSE); + + return status; +} + +void HTCUnblockRecv(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_BOOL unblockRecv = FALSE; + + LOCK_HTC_RX(target); + + /* check if we are blocked waiting for a new buffer */ + if (target->HTCStateFlags & HTC_STATE_WAIT_BUFFERS) { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HTCUnblockRx : receiver was blocked on ep:%d, unblocking.. \n", + target->EpWaitingForBuffers)); + target->HTCStateFlags &= ~HTC_STATE_WAIT_BUFFERS; + target->EpWaitingForBuffers = ENDPOINT_MAX; + unblockRecv = TRUE; + } + + UNLOCK_HTC_RX(target); + + if (unblockRecv && !HTC_STOPPING(target)) { + /* re-enable */ + DevEnableRecv(&target->Device,DEV_ENABLE_RECV_ASYNC); + } +} + +static void HTCFlushEndpointRX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint) +{ + HTC_PACKET *pPacket; + + LOCK_HTC_RX(target); + + while (1) { + pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers); + if (NULL == pPacket) { + break; + } + UNLOCK_HTC_RX(target); + pPacket->Status = A_ECANCELED; + pPacket->ActualLength = 0; + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" Flushing RX packet:0x%X, length:%d, ep:%d \n", + (A_UINT32)pPacket, pPacket->BufferLength, pPacket->Endpoint)); + /* give the packet back */ + pEndpoint->EpCallBacks.EpRecv(pEndpoint->EpCallBacks.pContext, + pPacket); + LOCK_HTC_RX(target); + } + + UNLOCK_HTC_RX(target); + + +} + +void HTCFlushRecvBuffers(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + int i; + + for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) { + pEndpoint = &target->EndPoint[i]; + if (pEndpoint->ServiceID == 0) { + /* not in use.. */ + continue; + } + HTCFlushEndpointRX(target,pEndpoint); + } +} + + +void HTCEnableRecv(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + + if (!HTC_STOPPING(target)) { + /* re-enable */ + DevEnableRecv(&target->Device,DEV_ENABLE_RECV_SYNC); + } +} + +void HTCDisableRecv(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + + if (!HTC_STOPPING(target)) { + /* disable */ + DevStopRecv(&target->Device,DEV_ENABLE_RECV_SYNC); + } +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k/htc_send.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc_send.c --- linux-2.6.26/drivers/net/wireless/ath6k/htc_send.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc_send.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,612 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + +typedef enum _HTC_SEND_QUEUE_RESULT { + HTC_SEND_QUEUE_OK = 0, /* packet was queued */ + HTC_SEND_QUEUE_DROP = 1, /* this packet should be dropped */ +} HTC_SEND_QUEUE_RESULT; + +#define DO_EP_TX_COMPLETION(ep,p) \ +{ \ + (p)->Completion = NULL; \ + (ep)->EpCallBacks.EpTxComplete((ep)->EpCallBacks.pContext,(p)); \ +} + + +/* call the distribute credits callback with the distribution */ +#define DO_DISTRIBUTION(t,reason,description,pList) \ +{ \ + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, \ + (" calling distribute function (%s) (dfn:0x%X, ctxt:0x%X, dist:0x%X) \n", \ + (description), \ + (A_UINT32)(t)->DistributeCredits, \ + (A_UINT32)(t)->pCredDistContext, \ + (A_UINT32)pList)); \ + (t)->DistributeCredits((t)->pCredDistContext, \ + (pList), \ + (reason)); \ +} + +/* our internal send packet completion handler when packets are submited to the AR6K device + * layer */ +static void HTCSendPktCompletionHandler(void *Context, HTC_PACKET *pPacket) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + HTC_ENDPOINT *pEndpoint = &target->EndPoint[pPacket->Endpoint]; + + + if (A_FAILED(pPacket->Status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCSendPktCompletionHandler: request failed (status:%d, ep:%d) \n", + pPacket->Status, pPacket->Endpoint)); + } + /* first, fixup the head room we allocated */ + pPacket->pBuffer += HTC_HDR_LENGTH; + /* do completion */ + DO_EP_TX_COMPLETION(pEndpoint,pPacket); +} + +A_STATUS HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT8 SendFlags) +{ + A_STATUS status; + A_UINT8 *pHdrBuf; + A_BOOL sync = FALSE; + + /* caller always provides headrooom */ + pPacket->pBuffer -= HTC_HDR_LENGTH; + pHdrBuf = pPacket->pBuffer; + /* setup frame header */ + A_SET_UINT16_FIELD(pHdrBuf,HTC_FRAME_HDR,PayloadLen,(A_UINT16)pPacket->ActualLength); + A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,Flags,SendFlags); + A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,EndpointID, (A_UINT8)pPacket->Endpoint); + + if (pPacket->Completion == NULL) { + /* mark that this request was synchronously issued */ + sync = TRUE; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("+-HTCIssueSend: transmit length : %d (%s) \n", + pPacket->ActualLength + HTC_HDR_LENGTH, + sync ? "SYNC" : "ASYNC" )); + + /* send message to device */ + status = DevSendPacket(&target->Device, + pPacket, + pPacket->ActualLength + HTC_HDR_LENGTH); + + if (sync) { + /* use local sync variable. If this was issued asynchronously, pPacket is no longer + * safe to access. */ + pPacket->pBuffer += HTC_HDR_LENGTH; + } + + /* if this request was asynchronous, the packet completion routine will be invoked by + * the device layer when the HIF layer completes the request */ + + return status; +} + +/* try to send the current packet or a packet at the head of the TX queue, + * if there are no credits, the packet remains in the queue. + * this function returns the result of the attempt to send the HTC packet */ +static HTC_SEND_QUEUE_RESULT HTCTrySend(HTC_TARGET *target, + HTC_ENDPOINT *pEndpoint, + HTC_PACKET *pPacketToSend) +{ + HTC_PACKET *pPacket; + int creditsRequired; + int remainder; + A_UINT8 sendFlags; + HTC_SEND_QUEUE_RESULT result; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HTCTrySend (pPkt:0x%X)\n",(A_UINT32)pPacketToSend)); + + if (pPacketToSend != NULL) { + /* see if adding this packet hits the max depth */ + if ((pEndpoint->CurrentTxQueueDepth + 1) >= pEndpoint->MaxTxQueueDepth) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d, TX queue is full, Depth:%d, Max:%d \n", + pPacketToSend->Endpoint, pEndpoint->CurrentTxQueueDepth, pEndpoint->MaxTxQueueDepth)); + /* queue will be full, invoke any callbacks to determine what action to take */ + if (pEndpoint->EpCallBacks.EpSendFull != NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Calling driver's send full callback.... \n")); + if (pEndpoint->EpCallBacks.EpSendFull(pEndpoint->EpCallBacks.pContext, + pPacketToSend) == HTC_SEND_FULL_DROP) { + /* callback wants the packet dropped */ + INC_HTC_EP_STAT(pEndpoint, TxDropped, 1); + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend: \n")); + return HTC_SEND_QUEUE_DROP; + } + } + } + } + + LOCK_HTC_TX(target); + + result = HTC_SEND_QUEUE_OK; + + if (pPacketToSend != NULL) { + /* packet was supplied to be queued */ + HTC_PACKET_ENQUEUE(&pEndpoint->TxQueue,pPacketToSend); + pEndpoint->CurrentTxQueueDepth++; + } + + pEndpoint->TxProcessCount++; + if (pEndpoint->TxProcessCount > 1) { + /* another thread is draining the queues, get out */ + pEndpoint->TxProcessCount--; + UNLOCK_HTC_TX(target); + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend: \n")); + return HTC_SEND_QUEUE_OK; + } + + /* at this point, only 1 thread may enter to drain this endpoint queue */ + + /* now drain the TX queue for transmission as long as we have enough + * credits */ + + while (1) { + + if (HTC_QUEUE_EMPTY(&pEndpoint->TxQueue)) { + /* nothing in the queue */ + break; + } + + if (HTC_STOPPING(target)) { + if (pPacketToSend != NULL) { + HTC_PACKET_REMOVE(pPacketToSend); + pEndpoint->CurrentTxQueueDepth--; + result = HTC_SEND_QUEUE_DROP; + } + break; + } + + sendFlags = 0; + + /* get packet at head, but don't remove it */ + pPacket = HTC_GET_PKT_AT_HEAD(&pEndpoint->TxQueue); + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Got head packet:0x%X , Queue Depth: %d\n", + (A_UINT32)pPacket, pEndpoint->CurrentTxQueueDepth)); + + /* figure out how many credits this message requires */ + creditsRequired = (pPacket->ActualLength + HTC_HDR_LENGTH) / target->TargetCreditSize; + remainder = (pPacket->ActualLength + HTC_HDR_LENGTH) % target->TargetCreditSize; + + if (remainder) { + creditsRequired++; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Creds Required:%d Got:%d\n", + creditsRequired, pEndpoint->CreditDist.TxCredits)); + + if (pEndpoint->CreditDist.TxCredits < creditsRequired) { + + /* not enough credits */ + + if (pPacket->Endpoint == ENDPOINT_0) { + /* leave it in the queue */ + break; + } + /* invoke the registered distribution function only if this is not + * endpoint 0, we let the driver layer provide more credits if it can. + * We pass the credit distribution list starting at the endpoint in question + * */ + + /* set how many credits we need */ + pEndpoint->CreditDist.TxCreditsSeek = + creditsRequired - pEndpoint->CreditDist.TxCredits; + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_SEEK_CREDITS, + "Seek Credits", + &pEndpoint->CreditDist); + pEndpoint->CreditDist.TxCreditsSeek = 0; + + if (pEndpoint->CreditDist.TxCredits < creditsRequired) { + /* still not enough credits to send, leave packet in the queue */ + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + (" Not enough credits for ep %d leaving packet in queue..\n", + pPacket->Endpoint)); + break; + } + + } + + pEndpoint->CreditDist.TxCredits -= creditsRequired; + INC_HTC_EP_STAT(pEndpoint, TxCreditsConsummed, creditsRequired); + + /* check if we need credits back from the target */ + if (pEndpoint->CreditDist.TxCredits < pEndpoint->CreditDist.TxCreditsPerMaxMsg) { + /* we are getting low on credits, see if we can ask for more from the distribution function */ + pEndpoint->CreditDist.TxCreditsSeek = + pEndpoint->CreditDist.TxCreditsPerMaxMsg - pEndpoint->CreditDist.TxCredits; + + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_SEEK_CREDITS, + "Seek Credits", + &pEndpoint->CreditDist); + + pEndpoint->CreditDist.TxCreditsSeek = 0; + /* see if we were successful in getting more */ + if (pEndpoint->CreditDist.TxCredits < pEndpoint->CreditDist.TxCreditsPerMaxMsg) { + /* tell the target we need credits ASAP! */ + sendFlags |= HTC_FLAGS_NEED_CREDIT_UPDATE; + INC_HTC_EP_STAT(pEndpoint, TxCreditLowIndications, 1); + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Host Needs Credits \n")); + } + } + + /* now we can fully dequeue */ + pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->TxQueue); + pEndpoint->CurrentTxQueueDepth--; + + INC_HTC_EP_STAT(pEndpoint, TxIssued, 1); + + UNLOCK_HTC_TX(target); + + HTCIssueSend(target, pPacket, sendFlags); + + LOCK_HTC_TX(target); + + /* go back and check for more messages */ + } + + /* we're done, clear count */ + pEndpoint->TxProcessCount = 0; + UNLOCK_HTC_TX(target); + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend: \n")); + + return result; +} + +/* HTC API - HTCSendPkt */ +A_STATUS HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint; + HTC_ENDPOINT_ID ep; + A_STATUS status = A_OK; + HTC_SEND_QUEUE_RESULT result; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("+HTCSendPkt: Enter endPointId: %d, buffer: 0x%X, length: %d \n", + pPacket->Endpoint, (A_UINT32)pPacket->pBuffer, pPacket->ActualLength)); + + ep = pPacket->Endpoint; + AR_DEBUG_ASSERT(ep < ENDPOINT_MAX); + pEndpoint = &target->EndPoint[ep]; + + do { + + /* everything sent through this interface is asynchronous */ + /* fill in HTC completion routines */ + pPacket->Completion = HTCSendPktCompletionHandler; + pPacket->pContext = target; + + result = HTCTrySend(target, pEndpoint, pPacket); + + if (HTC_SEND_QUEUE_DROP == result) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d, TX packet dropped \n", ep)); + if (HTC_STOPPING(target)) { + status = A_ECANCELED; + } else { + status = A_NO_RESOURCE; + } + } + + } while (FALSE); + + if (A_FAILED(status)) { + pPacket->Status = status; + DO_EP_TX_COMPLETION(pEndpoint,pPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCSendPkt \n")); + + return status; +} + + +/* check TX queues to drain because of credit distribution update */ +static INLINE void HTCCheckEndpointTxQueues(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + HTC_ENDPOINT_CREDIT_DIST *pDistItem; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCCheckEndpointTxQueues \n")); + pDistItem = target->EpCreditDistributionListHead; + + /* run through the credit distribution list to see + * if there are packets queued + * NOTE: no locks need to be taken since the distribution list + * is not dynamic (cannot be re-ordered) and we are not modifying any state */ + while (pDistItem != NULL) { + pEndpoint = (HTC_ENDPOINT *)pDistItem->pHTCReserved; + + if (pEndpoint->CurrentTxQueueDepth > 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Ep %d has %d credits and %d Packets in TX Queue \n", + pDistItem->Endpoint, pEndpoint->CreditDist.TxCredits, pEndpoint->CurrentTxQueueDepth)); + /* try to start the stalled queue, this list is ordered by priority. + * Highest priority queue get's processed first, if there are credits available the + * highest priority queue will get a chance to reclaim credits from lower priority + * ones */ + HTCTrySend(target, pEndpoint, NULL); + } + + pDistItem = pDistItem->pNext; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCCheckEndpointTxQueues \n")); +} + +/* process credit reports and call distribution function */ +void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint) +{ + int i; + HTC_ENDPOINT *pEndpoint; + int totalCredits = 0; + A_BOOL doDist = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCProcessCreditRpt, Credit Report Entries:%d \n", NumEntries)); + + /* lock out TX while we update credits */ + LOCK_HTC_TX(target); + + for (i = 0; i < NumEntries; i++, pRpt++) { + if (pRpt->EndpointID >= ENDPOINT_MAX) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + pEndpoint = &target->EndPoint[pRpt->EndpointID]; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d got %d credits \n", + pRpt->EndpointID, pRpt->Credits)); + + +#ifdef HTC_EP_STAT_PROFILING + + INC_HTC_EP_STAT(pEndpoint, TxCreditRpts, 1); + INC_HTC_EP_STAT(pEndpoint, TxCreditsReturned, pRpt->Credits); + + if (FromEndpoint == pRpt->EndpointID) { + /* this credit report arrived on the same endpoint indicating it arrived in an RX + * packet */ + INC_HTC_EP_STAT(pEndpoint, TxCreditsFromRx, pRpt->Credits); + INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromRx, 1); + } else if (FromEndpoint == ENDPOINT_0) { + /* this credit arrived on endpoint 0 as a NULL message */ + INC_HTC_EP_STAT(pEndpoint, TxCreditsFromEp0, pRpt->Credits); + INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromEp0, 1); + } else { + /* arrived on another endpoint */ + INC_HTC_EP_STAT(pEndpoint, TxCreditsFromOther, pRpt->Credits); + INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromOther, 1); + } + +#endif + + if (ENDPOINT_0 == pRpt->EndpointID) { + /* always give endpoint 0 credits back */ + pEndpoint->CreditDist.TxCredits += pRpt->Credits; + } else { + /* for all other endpoints, update credits to distribute, the distribution function + * will handle giving out credits back to the endpoints */ + pEndpoint->CreditDist.TxCreditsToDist += pRpt->Credits; + /* flag that we have to do the distribution */ + doDist = TRUE; + } + + /* refresh tx depth for distribution function that will recover these credits + * NOTE: this is only valid when there are credits to recover! */ + pEndpoint->CreditDist.TxQueueDepth = pEndpoint->CurrentTxQueueDepth; + + totalCredits += pRpt->Credits; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Report indicated %d credits to distribute \n", totalCredits)); + + if (doDist) { + /* this was a credit return based on a completed send operations + * note, this is done with the lock held */ + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_SEND_COMPLETE, + "Send Complete", + target->EpCreditDistributionListHead->pNext); + } + + UNLOCK_HTC_TX(target); + + if (totalCredits) { + HTCCheckEndpointTxQueues(target); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCProcessCreditRpt \n")); +} + +/* flush endpoint TX queue */ +static void HTCFlushEndpointTX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint, HTC_TX_TAG Tag) +{ + HTC_PACKET *pPacket; + HTC_PACKET_QUEUE discardQueue; + + /* initialize the discard queue */ + INIT_HTC_PACKET_QUEUE(&discardQueue); + + LOCK_HTC_TX(target); + + /* interate from the front of the TX queue and flush out packets */ + ITERATE_OVER_LIST_ALLOW_REMOVE(&pEndpoint->TxQueue, pPacket, HTC_PACKET, ListLink) { + + /* check for removal */ + if ((HTC_TX_PACKET_TAG_ALL == Tag) || (Tag == pPacket->PktInfo.AsTx.Tag)) { + /* remove from queue */ + HTC_PACKET_REMOVE(pPacket); + /* add it to the discard pile */ + HTC_PACKET_ENQUEUE(&discardQueue, pPacket); + pEndpoint->CurrentTxQueueDepth--; + } + + } ITERATE_END; + + UNLOCK_HTC_TX(target); + + /* empty the discard queue */ + while (1) { + pPacket = HTC_PACKET_DEQUEUE(&discardQueue); + if (NULL == pPacket) { + break; + } + pPacket->Status = A_ECANCELED; + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" Flushing TX packet:0x%X, length:%d, ep:%d tag:0x%X \n", + (A_UINT32)pPacket, pPacket->ActualLength, pPacket->Endpoint, pPacket->PktInfo.AsTx.Tag)); + DO_EP_TX_COMPLETION(pEndpoint,pPacket); + } + +} + +void DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("--- EP : %d ServiceID: 0x%X --------------\n", + pEPDist->Endpoint, pEPDist->ServiceID)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" this:0x%X next:0x%X prev:0x%X\n", + (A_UINT32)pEPDist, (A_UINT32)pEPDist->pNext, (A_UINT32)pEPDist->pPrev)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" DistFlags : 0x%X \n", pEPDist->DistFlags)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsNorm : %d \n", pEPDist->TxCreditsNorm)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsMin : %d \n", pEPDist->TxCreditsMin)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCredits : %d \n", pEPDist->TxCredits)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsAssigned : %d \n", pEPDist->TxCreditsAssigned)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsSeek : %d \n", pEPDist->TxCreditsSeek)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditSize : %d \n", pEPDist->TxCreditSize)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsPerMaxMsg : %d \n", pEPDist->TxCreditsPerMaxMsg)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsToDist : %d \n", pEPDist->TxCreditsToDist)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxQueueDepth : %d \n", + ((HTC_ENDPOINT *) pEPDist->pHTCReserved)->CurrentTxQueueDepth)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("----------------------------------------------------\n")); +} + +void DumpCreditDistStates(HTC_TARGET *target) +{ + HTC_ENDPOINT_CREDIT_DIST *pEPList = target->EpCreditDistributionListHead; + + while (pEPList != NULL) { + DumpCreditDist(pEPList); + pEPList = pEPList->pNext; + } + + if (target->DistributeCredits != NULL) { + DO_DISTRIBUTION(target, + HTC_DUMP_CREDIT_STATE, + "Dump State", + NULL); + } +} + +/* flush all send packets from all endpoint queues */ +void HTCFlushSendPkts(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + int i; + + DumpCreditDistStates(target); + + for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) { + pEndpoint = &target->EndPoint[i]; + if (pEndpoint->ServiceID == 0) { + /* not in use.. */ + continue; + } + HTCFlushEndpointTX(target,pEndpoint,HTC_TX_PACKET_TAG_ALL); + } + + +} + +/* HTC API to flush an endpoint's TX queue*/ +void HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint = &target->EndPoint[Endpoint]; + + if (pEndpoint->ServiceID == 0) { + AR_DEBUG_ASSERT(FALSE); + /* not in use.. */ + return; + } + + HTCFlushEndpointTX(target, pEndpoint, Tag); +} + +/* HTC API to indicate activity to the credit distribution function */ +void HTCIndicateActivityChange(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + A_BOOL Active) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint = &target->EndPoint[Endpoint]; + A_BOOL doDist = FALSE; + + if (pEndpoint->ServiceID == 0) { + AR_DEBUG_ASSERT(FALSE); + /* not in use.. */ + return; + } + + LOCK_HTC_TX(target); + + if (Active) { + if (!(pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE)) { + /* mark active now */ + pEndpoint->CreditDist.DistFlags |= HTC_EP_ACTIVE; + doDist = TRUE; + } + } else { + if (pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE) { + /* mark inactive now */ + pEndpoint->CreditDist.DistFlags &= ~HTC_EP_ACTIVE; + doDist = TRUE; + } + } + + if (doDist) { + /* indicate current Tx Queue depth to the credit distribution function */ + pEndpoint->CreditDist.TxQueueDepth = pEndpoint->CurrentTxQueueDepth; + /* do distribution again based on activity change + * note, this is done with the lock held */ + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_ACTIVITY_CHANGE, + "Activity Change", + target->EpCreditDistributionListHead->pNext); + } + + UNLOCK_HTC_TX(target); + + if (doDist && !Active) { + /* if a stream went inactive and this resulted in a credit distribution change, + * some credits may now be available for HTC packets that are stuck in + * HTC queues */ + HTCCheckEndpointTxQueues(target); + } +} + diff -urN linux-2.6.26/drivers/net/wireless/ath6k/htc_services.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc_services.c --- linux-2.6.26/drivers/net/wireless/ath6k/htc_services.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc_services.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,412 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + +void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket) +{ + /* not implemented + * we do not send control TX frames during normal runtime, only during setup */ + AR_DEBUG_ASSERT(FALSE); +} + + /* callback when a control message arrives on this endpoint */ +void HTCControlRecv(void *Context, HTC_PACKET *pPacket) +{ + AR_DEBUG_ASSERT(pPacket->Endpoint == ENDPOINT_0); + + if (pPacket->Status == A_ECANCELED) { + /* this is a flush operation, return the control packet back to the pool */ + HTC_FREE_CONTROL_RX((HTC_TARGET*)Context,pPacket); + return; + } + + /* the only control messages we are expecting are NULL messages (credit resports), which should + * never get here */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCControlRecv, got message with length:%d \n", + pPacket->ActualLength + HTC_HDR_LENGTH)); + + /* dump header and message */ + DebugDumpBytes(pPacket->pBuffer - HTC_HDR_LENGTH, + pPacket->ActualLength + HTC_HDR_LENGTH, + "Unexpected ENDPOINT 0 Message"); + + HTC_RECYCLE_RX_PKT((HTC_TARGET*)Context,pPacket,&((HTC_TARGET*)Context)->EndPoint[0]); +} + +A_STATUS HTCSendSetupComplete(HTC_TARGET *target) +{ + HTC_PACKET *pSendPacket = NULL; + A_STATUS status; + HTC_SETUP_COMPLETE_MSG *pSetupComplete; + + do { + /* allocate a packet to send to the target */ + pSendPacket = HTC_ALLOC_CONTROL_TX(target); + + if (NULL == pSendPacket) { + status = A_NO_MEMORY; + break; + } + + /* assemble setup complete message */ + pSetupComplete = (HTC_SETUP_COMPLETE_MSG *)pSendPacket->pBuffer; + A_MEMZERO(pSetupComplete,sizeof(HTC_SETUP_COMPLETE_MSG)); + pSetupComplete->MessageID = HTC_MSG_SETUP_COMPLETE_ID; + + SET_HTC_PACKET_INFO_TX(pSendPacket, + NULL, + (A_UINT8 *)pSetupComplete, + sizeof(HTC_SETUP_COMPLETE_MSG), + ENDPOINT_0, + HTC_SERVICE_TX_PACKET_TAG); + + /* we want synchronous operation */ + pSendPacket->Completion = NULL; + /* send the message */ + status = HTCIssueSend(target,pSendPacket,0); + + } while (FALSE); + + if (pSendPacket != NULL) { + HTC_FREE_CONTROL_TX(target,pSendPacket); + } + + return status; +} + + +A_STATUS HTCConnectService(HTC_HANDLE HTCHandle, + HTC_SERVICE_CONNECT_REQ *pConnectReq, + HTC_SERVICE_CONNECT_RESP *pConnectResp) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_STATUS status = A_OK; + HTC_PACKET *pRecvPacket = NULL; + HTC_PACKET *pSendPacket = NULL; + HTC_CONNECT_SERVICE_RESPONSE_MSG *pResponseMsg; + HTC_CONNECT_SERVICE_MSG *pConnectMsg; + HTC_ENDPOINT_ID assignedEndpoint = ENDPOINT_MAX; + HTC_ENDPOINT *pEndpoint; + int maxMsgSize = 0; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCConnectService, target:0x%X SvcID:0x%X \n", + (A_UINT32)target, pConnectReq->ServiceID)); + + do { + + AR_DEBUG_ASSERT(pConnectReq->ServiceID != 0); + + if (HTC_CTRL_RSVD_SVC == pConnectReq->ServiceID) { + /* special case for pseudo control service */ + assignedEndpoint = ENDPOINT_0; + maxMsgSize = HTC_MAX_CONTROL_MESSAGE_LENGTH; + } else { + /* allocate a packet to send to the target */ + pSendPacket = HTC_ALLOC_CONTROL_TX(target); + + if (NULL == pSendPacket) { + AR_DEBUG_ASSERT(FALSE); + status = A_NO_MEMORY; + break; + } + /* assemble connect service message */ + pConnectMsg = (HTC_CONNECT_SERVICE_MSG *)pSendPacket->pBuffer; + AR_DEBUG_ASSERT(pConnectMsg != NULL); + A_MEMZERO(pConnectMsg,sizeof(HTC_CONNECT_SERVICE_MSG)); + pConnectMsg->MessageID = HTC_MSG_CONNECT_SERVICE_ID; + pConnectMsg->ServiceID = pConnectReq->ServiceID; + pConnectMsg->ConnectionFlags = pConnectReq->ConnectionFlags; + /* check caller if it wants to transfer meta data */ + if ((pConnectReq->pMetaData != NULL) && + (pConnectReq->MetaDataLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) { + /* copy meta data into message buffer (after header ) */ + A_MEMCPY((A_UINT8 *)pConnectMsg + sizeof(HTC_CONNECT_SERVICE_MSG), + pConnectReq->pMetaData, + pConnectReq->MetaDataLength); + pConnectMsg->ServiceMetaLength = pConnectReq->MetaDataLength; + } + + SET_HTC_PACKET_INFO_TX(pSendPacket, + NULL, + (A_UINT8 *)pConnectMsg, + sizeof(HTC_CONNECT_SERVICE_MSG) + pConnectMsg->ServiceMetaLength, + ENDPOINT_0, + HTC_SERVICE_TX_PACKET_TAG); + + /* we want synchronous operation */ + pSendPacket->Completion = NULL; + + status = HTCIssueSend(target,pSendPacket,0); + + if (A_FAILED(status)) { + break; + } + + /* wait for response */ + status = HTCWaitforControlMessage(target, &pRecvPacket); + + if (A_FAILED(status)) { + break; + } + /* we controlled the buffer creation so it has to be properly aligned */ + pResponseMsg = (HTC_CONNECT_SERVICE_RESPONSE_MSG *)pRecvPacket->pBuffer; + + if ((pResponseMsg->MessageID != HTC_MSG_CONNECT_SERVICE_RESPONSE_ID) || + (pRecvPacket->ActualLength < sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG))) { + /* this message is not valid */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + pConnectResp->ConnectRespCode = pResponseMsg->Status; + /* check response status */ + if (pResponseMsg->Status != HTC_SERVICE_SUCCESS) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" Target failed service 0x%X connect request (status:%d)\n", + pResponseMsg->ServiceID, pResponseMsg->Status)); + status = A_EPROTO; + break; + } + + assignedEndpoint = (HTC_ENDPOINT_ID) pResponseMsg->EndpointID; + maxMsgSize = pResponseMsg->MaxMsgSize; + + if ((pConnectResp->pMetaData != NULL) && + (pResponseMsg->ServiceMetaLength > 0) && + (pResponseMsg->ServiceMetaLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) { + /* caller supplied a buffer and the target responded with data */ + int copyLength = min((int)pConnectResp->BufferLength, (int)pResponseMsg->ServiceMetaLength); + /* copy the meta data */ + A_MEMCPY(pConnectResp->pMetaData, + ((A_UINT8 *)pResponseMsg) + sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG), + copyLength); + pConnectResp->ActualLength = copyLength; + } + + } + + /* the rest of these are parameter checks so set the error status */ + status = A_EPROTO; + + if (assignedEndpoint >= ENDPOINT_MAX) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + if (0 == maxMsgSize) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + pEndpoint = &target->EndPoint[assignedEndpoint]; + + if (pEndpoint->ServiceID != 0) { + /* endpoint already in use! */ + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* return assigned endpoint to caller */ + pConnectResp->Endpoint = assignedEndpoint; + pConnectResp->MaxMsgLength = maxMsgSize; + + /* setup the endpoint */ + pEndpoint->ServiceID = pConnectReq->ServiceID; /* this marks the endpoint in use */ + pEndpoint->MaxTxQueueDepth = pConnectReq->MaxSendQueueDepth; + pEndpoint->MaxMsgLength = maxMsgSize; + /* copy all the callbacks */ + pEndpoint->EpCallBacks = pConnectReq->EpCallbacks; + INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBuffers); + INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue); + /* set the credit distribution info for this endpoint, this information is + * passed back to the credit distribution callback function */ + pEndpoint->CreditDist.ServiceID = pConnectReq->ServiceID; + pEndpoint->CreditDist.pHTCReserved = pEndpoint; + pEndpoint->CreditDist.Endpoint = assignedEndpoint; + pEndpoint->CreditDist.TxCreditSize = target->TargetCreditSize; + pEndpoint->CreditDist.TxCreditsPerMaxMsg = maxMsgSize / target->TargetCreditSize; + + if (0 == pEndpoint->CreditDist.TxCreditsPerMaxMsg) { + pEndpoint->CreditDist.TxCreditsPerMaxMsg = 1; + } + + status = A_OK; + + } while (FALSE); + + if (pSendPacket != NULL) { + HTC_FREE_CONTROL_TX(target,pSendPacket); + } + + if (pRecvPacket != NULL) { + HTC_FREE_CONTROL_RX(target,pRecvPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCConnectService \n")); + + return status; +} + +static void AddToEndpointDistList(HTC_TARGET *target, HTC_ENDPOINT_CREDIT_DIST *pEpDist) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEntry,*pLastEntry; + + if (NULL == target->EpCreditDistributionListHead) { + target->EpCreditDistributionListHead = pEpDist; + pEpDist->pNext = NULL; + pEpDist->pPrev = NULL; + return; + } + + /* queue to the end of the list, this does not have to be very + * fast since this list is built at startup time */ + pCurEntry = target->EpCreditDistributionListHead; + + while (pCurEntry) { + pLastEntry = pCurEntry; + pCurEntry = pCurEntry->pNext; + } + + pLastEntry->pNext = pEpDist; + pEpDist->pPrev = pLastEntry; + pEpDist->pNext = NULL; +} + + + +/* default credit init callback */ +static void HTCDefaultCreditInit(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + int TotalCredits) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + int totalEps = 0; + int creditsPerEndpoint; + + pCurEpDist = pEPList; + /* first run through the list and figure out how many endpoints we are dealing with */ + while (pCurEpDist != NULL) { + pCurEpDist = pCurEpDist->pNext; + totalEps++; + } + + /* even distribution */ + creditsPerEndpoint = TotalCredits/totalEps; + + pCurEpDist = pEPList; + /* run through the list and set minimum and normal credits and + * provide the endpoint with some credits to start */ + while (pCurEpDist != NULL) { + + if (creditsPerEndpoint < pCurEpDist->TxCreditsPerMaxMsg) { + /* too many endpoints and not enough credits */ + AR_DEBUG_ASSERT(FALSE); + break; + } + /* our minimum is set for at least 1 max message */ + pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg; + /* this value is ignored by our credit alg, since we do + * not dynamically adjust credits, this is the policy of + * the "default" credit distribution, something simple and easy */ + pCurEpDist->TxCreditsNorm = 0xFFFF; + /* give the endpoint minimum credits */ + pCurEpDist->TxCredits = creditsPerEndpoint; + pCurEpDist->TxCreditsAssigned = creditsPerEndpoint; + pCurEpDist = pCurEpDist->pNext; + } + +} + +/* default credit distribution callback, NOTE, this callback holds the TX lock */ +void HTCDefaultCreditDist(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList, + HTC_CREDIT_DIST_REASON Reason) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + + if (Reason == HTC_CREDIT_DIST_SEND_COMPLETE) { + pCurEpDist = pEPDistList; + /* simple distribution */ + while (pCurEpDist != NULL) { + if (pCurEpDist->TxCreditsToDist > 0) { + /* just give the endpoint back the credits */ + pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist; + pCurEpDist->TxCreditsToDist = 0; + } + pCurEpDist = pCurEpDist->pNext; + } + } + + /* note we do not need to handle the other reason codes as this is a very + * simple distribution scheme, no need to seek for more credits or handle inactivity */ +} + +void HTCSetCreditDistribution(HTC_HANDLE HTCHandle, + void *pCreditDistContext, + HTC_CREDIT_DIST_CALLBACK CreditDistFunc, + HTC_CREDIT_INIT_CALLBACK CreditInitFunc, + HTC_SERVICE_ID ServicePriorityOrder[], + int ListLength) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + int i; + int ep; + + if (CreditInitFunc != NULL) { + /* caller has supplied their own distribution functions */ + target->InitCredits = CreditInitFunc; + AR_DEBUG_ASSERT(CreditDistFunc != NULL); + target->DistributeCredits = CreditDistFunc; + target->pCredDistContext = pCreditDistContext; + } else { + /* caller wants HTC to do distribution */ + /* if caller wants service to handle distributions then + * it must set both of these to NULL! */ + AR_DEBUG_ASSERT(CreditDistFunc == NULL); + target->InitCredits = HTCDefaultCreditInit; + target->DistributeCredits = HTCDefaultCreditDist; + target->pCredDistContext = target; + } + + /* always add HTC control endpoint first, we only expose the list after the + * first one, this is added for TX queue checking */ + AddToEndpointDistList(target, &target->EndPoint[ENDPOINT_0].CreditDist); + + /* build the list of credit distribution structures in priority order + * supplied by the caller, these will follow endpoint 0 */ + for (i = 0; i < ListLength; i++) { + /* match services with endpoints and add the endpoints to the distribution list + * in FIFO order */ + for (ep = ENDPOINT_1; ep < ENDPOINT_MAX; ep++) { + if (target->EndPoint[ep].ServiceID == ServicePriorityOrder[i]) { + /* queue this one to the list */ + AddToEndpointDistList(target, &target->EndPoint[ep].CreditDist); + break; + } + } + AR_DEBUG_ASSERT(ep < ENDPOINT_MAX); + } + +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k/htc_services.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc_services.h --- linux-2.6.26/drivers/net/wireless/ath6k/htc_services.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/htc_services.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __HTC_SERVICES_H__ +#define __HTC_SERVICES_H__ + +/* Current service IDs */ + +typedef enum { + RSVD_SERVICE_GROUP = 0, + WMI_SERVICE_GROUP = 1, + + HTC_TEST_GROUP = 254, + HTC_SERVICE_GROUP_LAST = 255 +}HTC_SERVICE_GROUP_IDS; + +#define MAKE_SERVICE_ID(group,index) \ + (int)(((int)group << 8) | (int)(index)) + +/* NOTE: service ID of 0x0000 is reserved and should never be used */ +#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1) +#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0) +#define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1) +#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2) +#define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3) +#define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4) +#define WMI_MAX_SERVICES 5 + +/* raw stream service (i.e. flash, tcmd, calibration apps) */ +#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0) + +#endif /*HTC_SERVICES_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/ieee80211.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/ieee80211.h --- linux-2.6.26/drivers/net/wireless/ath6k/ieee80211.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/ieee80211.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,404 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _NET80211_IEEE80211_H_ +#define _NET80211_IEEE80211_H_ + +#include "athstartpack.h" + +/* + * 802.11 protocol definitions. + */ +#define IEEE80211_WEP_KEYLEN 5 /* 40bit */ +#define IEEE80211_WEP_IVLEN 3 /* 24bit */ +#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ +#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ +#define IEEE80211_WEP_NKID 4 /* number of key ids */ + +/* + * 802.11i defines an extended IV for use with non-WEP ciphers. + * When the EXTIV bit is set in the key id byte an additional + * 4 bytes immediately follow the IV for TKIP. For CCMP the + * EXTIV bit is likewise set but the 8 bytes represent the + * CCMP header rather than IV+extended-IV. + */ +#define IEEE80211_WEP_EXTIV 0x20 +#define IEEE80211_WEP_EXTIVLEN 4 /* extended IV length */ +#define IEEE80211_WEP_MICLEN 8 /* trailing MIC */ + +#define IEEE80211_CRC_LEN 4 + +#ifdef WAPI_ENABLE +#define IEEE80211_WAPI_EXTIVLEN 10 /* extended IV length */ +#endif /* WAPI ENABLE */ + + +#define IEEE80211_ADDR_LEN 6 /* size of 802.11 address */ +/* is 802.11 address multicast/broadcast? */ +#define IEEE80211_IS_MULTICAST(_a) (*(_a) & 0x01) +#define IEEE80211_IS_BROADCAST(_a) (*(_a) == 0xFF) +#define WEP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN) +#define WEP_TRAILER IEEE80211_WEP_CRCLEN +#define CCMP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + \ + IEEE80211_WEP_EXTIVLEN) +#define CCMP_TRAILER IEEE80211_WEP_MICLEN +#define TKIP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + \ + IEEE80211_WEP_EXTIVLEN) +#define TKIP_TRAILER IEEE80211_WEP_CRCLEN +#define TKIP_MICLEN IEEE80211_WEP_MICLEN + + +#define IEEE80211_ADDR_EQ(addr1, addr2) \ + (A_MEMCMP(addr1, addr2, IEEE80211_ADDR_LEN) == 0) + +#define IEEE80211_ADDR_COPY(dst,src) A_MEMCPY(dst,src,IEEE80211_ADDR_LEN) + +#define IEEE80211_KEYBUF_SIZE 16 +#define IEEE80211_MICBUF_SIZE (8+8) /* space for both tx and rx */ + +/* + * NB: these values are ordered carefully; there are lots of + * of implications in any reordering. In particular beware + * that 4 is not used to avoid conflicting with IEEE80211_F_PRIVACY. + */ +#define IEEE80211_CIPHER_WEP 0 +#define IEEE80211_CIPHER_TKIP 1 +#define IEEE80211_CIPHER_AES_OCB 2 +#define IEEE80211_CIPHER_AES_CCM 3 +#define IEEE80211_CIPHER_CKIP 5 +#define IEEE80211_CIPHER_CCKM_KRK 6 +#define IEEE80211_CIPHER_NONE 7 /* pseudo value */ + +#define IEEE80211_CIPHER_MAX (IEEE80211_CIPHER_NONE+1) + +#define IEEE80211_IS_VALID_WEP_CIPHER_LEN(len) \ + (((len) == 5) || ((len) == 13) || ((len) == 16)) + + + +/* + * generic definitions for IEEE 802.11 frames + */ +PREPACK struct ieee80211_frame { + A_UINT8 i_fc[2]; + A_UINT8 i_dur[2]; + A_UINT8 i_addr1[IEEE80211_ADDR_LEN]; + A_UINT8 i_addr2[IEEE80211_ADDR_LEN]; + A_UINT8 i_addr3[IEEE80211_ADDR_LEN]; + A_UINT8 i_seq[2]; + /* possibly followed by addr4[IEEE80211_ADDR_LEN]; */ + /* see below */ +} POSTPACK; + +PREPACK struct ieee80211_qosframe { + A_UINT8 i_fc[2]; + A_UINT8 i_dur[2]; + A_UINT8 i_addr1[IEEE80211_ADDR_LEN]; + A_UINT8 i_addr2[IEEE80211_ADDR_LEN]; + A_UINT8 i_addr3[IEEE80211_ADDR_LEN]; + A_UINT8 i_seq[2]; + A_UINT8 i_qos[2]; +} POSTPACK; + +#define IEEE80211_FC0_VERSION_MASK 0x03 +#define IEEE80211_FC0_VERSION_SHIFT 0 +#define IEEE80211_FC0_VERSION_0 0x00 +#define IEEE80211_FC0_TYPE_MASK 0x0c +#define IEEE80211_FC0_TYPE_SHIFT 2 +#define IEEE80211_FC0_TYPE_MGT 0x00 +#define IEEE80211_FC0_TYPE_CTL 0x04 +#define IEEE80211_FC0_TYPE_DATA 0x08 + +#define IEEE80211_FC0_SUBTYPE_MASK 0xf0 +#define IEEE80211_FC0_SUBTYPE_SHIFT 4 +/* for TYPE_MGT */ +#define IEEE80211_FC0_SUBTYPE_ASSOC_REQ 0x00 +#define IEEE80211_FC0_SUBTYPE_ASSOC_RESP 0x10 +#define IEEE80211_FC0_SUBTYPE_REASSOC_REQ 0x20 +#define IEEE80211_FC0_SUBTYPE_REASSOC_RESP 0x30 +#define IEEE80211_FC0_SUBTYPE_PROBE_REQ 0x40 +#define IEEE80211_FC0_SUBTYPE_PROBE_RESP 0x50 +#define IEEE80211_FC0_SUBTYPE_BEACON 0x80 +#define IEEE80211_FC0_SUBTYPE_ATIM 0x90 +#define IEEE80211_FC0_SUBTYPE_DISASSOC 0xa0 +#define IEEE80211_FC0_SUBTYPE_AUTH 0xb0 +#define IEEE80211_FC0_SUBTYPE_DEAUTH 0xc0 +/* for TYPE_CTL */ +#define IEEE80211_FC0_SUBTYPE_PS_POLL 0xa0 +#define IEEE80211_FC0_SUBTYPE_RTS 0xb0 +#define IEEE80211_FC0_SUBTYPE_CTS 0xc0 +#define IEEE80211_FC0_SUBTYPE_ACK 0xd0 +#define IEEE80211_FC0_SUBTYPE_CF_END 0xe0 +#define IEEE80211_FC0_SUBTYPE_CF_END_ACK 0xf0 +/* for TYPE_DATA (bit combination) */ +#define IEEE80211_FC0_SUBTYPE_DATA 0x00 +#define IEEE80211_FC0_SUBTYPE_CF_ACK 0x10 +#define IEEE80211_FC0_SUBTYPE_CF_POLL 0x20 +#define IEEE80211_FC0_SUBTYPE_CF_ACPL 0x30 +#define IEEE80211_FC0_SUBTYPE_NODATA 0x40 +#define IEEE80211_FC0_SUBTYPE_CFACK 0x50 +#define IEEE80211_FC0_SUBTYPE_CFPOLL 0x60 +#define IEEE80211_FC0_SUBTYPE_CF_ACK_CF_ACK 0x70 +#define IEEE80211_FC0_SUBTYPE_QOS 0x80 +#define IEEE80211_FC0_SUBTYPE_QOS_NULL 0xc0 + +#define IEEE80211_FC1_DIR_MASK 0x03 +#define IEEE80211_FC1_DIR_NODS 0x00 /* STA->STA */ +#define IEEE80211_FC1_DIR_TODS 0x01 /* STA->AP */ +#define IEEE80211_FC1_DIR_FROMDS 0x02 /* AP ->STA */ +#define IEEE80211_FC1_DIR_DSTODS 0x03 /* AP ->AP */ + +#define IEEE80211_FC1_MORE_FRAG 0x04 +#define IEEE80211_FC1_RETRY 0x08 +#define IEEE80211_FC1_PWR_MGT 0x10 +#define IEEE80211_FC1_MORE_DATA 0x20 +#define IEEE80211_FC1_WEP 0x40 +#define IEEE80211_FC1_ORDER 0x80 + +#define IEEE80211_SEQ_FRAG_MASK 0x000f +#define IEEE80211_SEQ_FRAG_SHIFT 0 +#define IEEE80211_SEQ_SEQ_MASK 0xfff0 +#define IEEE80211_SEQ_SEQ_SHIFT 4 + +#define IEEE80211_NWID_LEN 32 + +/* + * 802.11 rate set. + */ +#define IEEE80211_RATE_SIZE 8 /* 802.11 standard */ +#define IEEE80211_RATE_MAXSIZE 15 /* max rates we'll handle */ + +#define WMM_NUM_AC 4 /* 4 AC categories */ + +#define WMM_PARAM_ACI_M 0x60 /* Mask for ACI field */ +#define WMM_PARAM_ACI_S 5 /* Shift for ACI field */ +#define WMM_PARAM_ACM_M 0x10 /* Mask for ACM bit */ +#define WMM_PARAM_ACM_S 4 /* Shift for ACM bit */ +#define WMM_PARAM_AIFSN_M 0x0f /* Mask for aifsn field */ +#define WMM_PARAM_LOGCWMIN_M 0x0f /* Mask for CwMin field (in log) */ +#define WMM_PARAM_LOGCWMAX_M 0xf0 /* Mask for CwMax field (in log) */ +#define WMM_PARAM_LOGCWMAX_S 4 /* Shift for CwMax field */ + +#define WMM_AC_TO_TID(_ac) ( \ + ((_ac) == WMM_AC_VO) ? 6 : \ + ((_ac) == WMM_AC_VI) ? 5 : \ + ((_ac) == WMM_AC_BK) ? 1 : \ + 0) + +#define TID_TO_WMM_AC(_tid) ( \ + ((_tid) < 1) ? WMM_AC_BE : \ + ((_tid) < 3) ? WMM_AC_BK : \ + ((_tid) < 6) ? WMM_AC_VI : \ + WMM_AC_VO) +/* + * Management information element payloads. + */ + +enum { + IEEE80211_ELEMID_SSID = 0, + IEEE80211_ELEMID_RATES = 1, + IEEE80211_ELEMID_FHPARMS = 2, + IEEE80211_ELEMID_DSPARMS = 3, + IEEE80211_ELEMID_CFPARMS = 4, + IEEE80211_ELEMID_TIM = 5, + IEEE80211_ELEMID_IBSSPARMS = 6, + IEEE80211_ELEMID_COUNTRY = 7, + IEEE80211_ELEMID_CHALLENGE = 16, + /* 17-31 reserved for challenge text extension */ + IEEE80211_ELEMID_PWRCNSTR = 32, + IEEE80211_ELEMID_PWRCAP = 33, + IEEE80211_ELEMID_TPCREQ = 34, + IEEE80211_ELEMID_TPCREP = 35, + IEEE80211_ELEMID_SUPPCHAN = 36, + IEEE80211_ELEMID_CHANSWITCH = 37, + IEEE80211_ELEMID_MEASREQ = 38, + IEEE80211_ELEMID_MEASREP = 39, + IEEE80211_ELEMID_QUIET = 40, + IEEE80211_ELEMID_IBSSDFS = 41, + IEEE80211_ELEMID_ERP = 42, + IEEE80211_ELEMID_RSN = 48, + IEEE80211_ELEMID_XRATES = 50, +#ifdef WAPI_ENABLE + IEEE80211_ELEMID_WAPI = 68, +#endif + IEEE80211_ELEMID_TPC = 150, + IEEE80211_ELEMID_CCKM = 156, + IEEE80211_ELEMID_VENDOR = 221, /* vendor private */ +}; + +#define ATH_OUI 0x7f0300 /* Atheros OUI */ +#define ATH_OUI_TYPE 0x01 +#define ATH_OUI_SUBTYPE 0x01 +#define ATH_OUI_VERSION 0x00 + +#define WPA_OUI 0xf25000 +#define WPA_OUI_TYPE 0x01 +#define WPA_VERSION 1 /* current supported version */ + +#define WPA_CSE_NULL 0x00 +#define WPA_CSE_WEP40 0x01 +#define WPA_CSE_TKIP 0x02 +#define WPA_CSE_CCMP 0x04 +#define WPA_CSE_WEP104 0x05 + +#define WPA_ASE_NONE 0x00 +#define WPA_ASE_8021X_UNSPEC 0x01 +#define WPA_ASE_8021X_PSK 0x02 + +#define RSN_OUI 0xac0f00 +#define RSN_VERSION 1 /* current supported version */ + +#define RSN_CSE_NULL 0x00 +#define RSN_CSE_WEP40 0x01 +#define RSN_CSE_TKIP 0x02 +#define RSN_CSE_WRAP 0x03 +#define RSN_CSE_CCMP 0x04 +#define RSN_CSE_WEP104 0x05 + +#define RSN_ASE_NONE 0x00 +#define RSN_ASE_8021X_UNSPEC 0x01 +#define RSN_ASE_8021X_PSK 0x02 + +#define RSN_CAP_PREAUTH 0x01 + +#define WMM_OUI 0xf25000 +#define WMM_OUI_TYPE 0x02 +#define WMM_INFO_OUI_SUBTYPE 0x00 +#define WMM_PARAM_OUI_SUBTYPE 0x01 +#define WMM_VERSION 1 + +#ifdef PYXIS_ADHOC +#define PYXIS_OUI 0xf25000 /* Pyxis OUI 00-50-F2*/ +#define PYXIS_OUI_TYPE 0x06 +#endif + +/* WMM stream classes */ +#define WMM_NUM_AC 4 +#define WMM_AC_BE 0 /* best effort */ +#define WMM_AC_BK 1 /* background */ +#define WMM_AC_VI 2 /* video */ +#define WMM_AC_VO 3 /* voice */ + +/* TSPEC related */ +#define ACTION_CATEGORY_CODE_TSPEC 17 +#define ACTION_CODE_TSPEC_ADDTS 0 +#define ACTION_CODE_TSPEC_ADDTS_RESP 1 +#define ACTION_CODE_TSPEC_DELTS 2 + +typedef enum { + TSPEC_STATUS_CODE_ADMISSION_ACCEPTED = 0, + TSPEC_STATUS_CODE_ADDTS_INVALID_PARAMS = 0x1, + TSPEC_STATUS_CODE_ADDTS_REQUEST_REFUSED = 0x3, + TSPEC_STATUS_CODE_UNSPECIFIED_QOS_RELATED_FAILURE = 0xC8, + TSPEC_STATUS_CODE_REQUESTED_REFUSED_POLICY_CONFIGURATION = 0xC9, + TSPEC_STATUS_CODE_INSUFFCIENT_BANDWIDTH = 0xCA, + TSPEC_STATUS_CODE_INVALID_PARAMS = 0xCB, + TSPEC_STATUS_CODE_DELTS_SENT = 0x30, + TSPEC_STATUS_CODE_DELTS_RECV = 0x31, +} TSPEC_STATUS_CODE; + +#define TSPEC_TSID_MASK 0xF +#define TSPEC_TSID_S 1 + +/* + * WMM/802.11e Tspec Element + */ +typedef PREPACK struct wmm_tspec_ie_t { + A_UINT8 elementId; + A_UINT8 len; + A_UINT8 oui[3]; + A_UINT8 ouiType; + A_UINT8 ouiSubType; + A_UINT8 version; + A_UINT16 tsInfo_info; + A_UINT8 tsInfo_reserved; + A_UINT16 nominalMSDU; + A_UINT16 maxMSDU; + A_UINT32 minServiceInt; + A_UINT32 maxServiceInt; + A_UINT32 inactivityInt; + A_UINT32 suspensionInt; + A_UINT32 serviceStartTime; + A_UINT32 minDataRate; + A_UINT32 meanDataRate; + A_UINT32 peakDataRate; + A_UINT32 maxBurstSize; + A_UINT32 delayBound; + A_UINT32 minPhyRate; + A_UINT16 sba; + A_UINT16 mediumTime; +} POSTPACK WMM_TSPEC_IE; + + +/* + * BEACON management packets + * + * octet timestamp[8] + * octet beacon interval[2] + * octet capability information[2] + * information element + * octet elemid + * octet length + * octet information[length] + */ + +#define IEEE80211_BEACON_INTERVAL(beacon) \ + ((beacon)[8] | ((beacon)[9] << 8)) +#define IEEE80211_BEACON_CAPABILITY(beacon) \ + ((beacon)[10] | ((beacon)[11] << 8)) + +#define IEEE80211_CAPINFO_ESS 0x0001 +#define IEEE80211_CAPINFO_IBSS 0x0002 +#define IEEE80211_CAPINFO_CF_POLLABLE 0x0004 +#define IEEE80211_CAPINFO_CF_POLLREQ 0x0008 +#define IEEE80211_CAPINFO_PRIVACY 0x0010 +#define IEEE80211_CAPINFO_SHORT_PREAMBLE 0x0020 +#define IEEE80211_CAPINFO_PBCC 0x0040 +#define IEEE80211_CAPINFO_CHNL_AGILITY 0x0080 +/* bits 8-9 are reserved */ +#define IEEE80211_CAPINFO_SHORT_SLOTTIME 0x0400 +#define IEEE80211_CAPINFO_APSD 0x0800 +/* bit 12 is reserved */ +#define IEEE80211_CAPINFO_DSSSOFDM 0x2000 +/* bits 14-15 are reserved */ + +/* + * Authentication Modes + */ + +enum ieee80211_authmode { + IEEE80211_AUTH_NONE = 0, + IEEE80211_AUTH_OPEN = 1, + IEEE80211_AUTH_SHARED = 2, + IEEE80211_AUTH_8021X = 3, + IEEE80211_AUTH_AUTO = 4, /* auto-select/accept */ + /* NB: these are used only for ioctls */ + IEEE80211_AUTH_WPA = 5, /* WPA/RSN w/ 802.1x */ + IEEE80211_AUTH_WPA_PSK = 6, /* WPA/RSN w/ PSK */ + IEEE80211_AUTH_WPA_CCKM = 7, /* WPA/RSN IE w/ CCKM */ +}; + +#define IEEE80211_PS_MAX_QUEUE 50 /*Maximum no of buffers that can be queues for PS*/ + +#include "athendpack.h" + +#endif /* _NET80211_IEEE80211_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/ieee80211_ioctl.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/ieee80211_ioctl.h --- linux-2.6.26/drivers/net/wireless/ath6k/ieee80211_ioctl.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/ieee80211_ioctl.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2004-2005 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + * + * $Id: //depot/sw/releases/olca2.2/host/os/linux/include/ieee80211_ioctl.h#1 $ + */ + +#ifndef _IEEE80211_IOCTL_H_ +#define _IEEE80211_IOCTL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Extracted from the MADWIFI net80211/ieee80211_ioctl.h + */ + +/* + * WPA/RSN get/set key request. Specify the key/cipher + * type and whether the key is to be used for sending and/or + * receiving. The key index should be set only when working + * with global keys (use IEEE80211_KEYIX_NONE for ``no index''). + * Otherwise a unicast/pairwise key is specified by the bssid + * (on a station) or mac address (on an ap). They key length + * must include any MIC key data; otherwise it should be no + more than IEEE80211_KEYBUF_SIZE. + */ +struct ieee80211req_key { + u_int8_t ik_type; /* key/cipher type */ + u_int8_t ik_pad; + u_int16_t ik_keyix; /* key index */ + u_int8_t ik_keylen; /* key length in bytes */ + u_int8_t ik_flags; +#define IEEE80211_KEY_XMIT 0x01 +#define IEEE80211_KEY_RECV 0x02 +#define IEEE80211_KEY_DEFAULT 0x80 /* default xmit key */ + u_int8_t ik_macaddr[IEEE80211_ADDR_LEN]; + u_int64_t ik_keyrsc; /* key receive sequence counter */ + u_int64_t ik_keytsc; /* key transmit sequence counter */ + u_int8_t ik_keydata[IEEE80211_KEYBUF_SIZE+IEEE80211_MICBUF_SIZE]; +}; +/* + * Delete a key either by index or address. Set the index + * to IEEE80211_KEYIX_NONE when deleting a unicast key. + */ +struct ieee80211req_del_key { + u_int8_t idk_keyix; /* key index */ + u_int8_t idk_macaddr[IEEE80211_ADDR_LEN]; +}; +/* + * MLME state manipulation request. IEEE80211_MLME_ASSOC + * only makes sense when operating as a station. The other + * requests can be used when operating as a station or an + * ap (to effect a station). + */ +struct ieee80211req_mlme { + u_int8_t im_op; /* operation to perform */ +#define IEEE80211_MLME_ASSOC 1 /* associate station */ +#define IEEE80211_MLME_DISASSOC 2 /* disassociate station */ +#define IEEE80211_MLME_DEAUTH 3 /* deauthenticate station */ +#define IEEE80211_MLME_AUTHORIZE 4 /* authorize station */ +#define IEEE80211_MLME_UNAUTHORIZE 5 /* unauthorize station */ + u_int16_t im_reason; /* 802.11 reason code */ + u_int8_t im_macaddr[IEEE80211_ADDR_LEN]; +}; + +struct ieee80211req_addpmkid { + u_int8_t pi_bssid[IEEE80211_ADDR_LEN]; + u_int8_t pi_enable; + u_int8_t pi_pmkid[16]; +}; + +#define AUTH_ALG_OPEN_SYSTEM 0x01 +#define AUTH_ALG_SHARED_KEY 0x02 +#define AUTH_ALG_LEAP 0x04 + +struct ieee80211req_authalg { + u_int8_t auth_alg; +}; + +/* + * Request to add an IE to a Management Frame + */ +enum{ + IEEE80211_APPIE_FRAME_BEACON = 0, + IEEE80211_APPIE_FRAME_PROBE_REQ = 1, + IEEE80211_APPIE_FRAME_PROBE_RESP = 2, + IEEE80211_APPIE_FRAME_ASSOC_REQ = 3, + IEEE80211_APPIE_FRAME_ASSOC_RESP = 4, + IEEE80211_APPIE_NUM_OF_FRAME = 5 +}; + +/* + * The Maximum length of the IE that can be added to a Management frame + */ +#define IEEE80211_APPIE_FRAME_MAX_LEN 200 + +struct ieee80211req_getset_appiebuf { + u_int32_t app_frmtype; /* management frame type for which buffer is added */ + u_int32_t app_buflen; /*application supplied buffer length */ + u_int8_t app_buf[]; +}; + +/* + * The following definitions are used by an application to set filter + * for receiving management frames + */ +enum { + IEEE80211_FILTER_TYPE_BEACON = 0x1, + IEEE80211_FILTER_TYPE_PROBE_REQ = 0x2, + IEEE80211_FILTER_TYPE_PROBE_RESP = 0x4, + IEEE80211_FILTER_TYPE_ASSOC_REQ = 0x8, + IEEE80211_FILTER_TYPE_ASSOC_RESP = 0x10, + IEEE80211_FILTER_TYPE_AUTH = 0x20, + IEEE80211_FILTER_TYPE_DEAUTH = 0x40, + IEEE80211_FILTER_TYPE_DISASSOC = 0x80, + IEEE80211_FILTER_TYPE_ALL = 0xFF /* used to check the valid filter bits */ +}; + +struct ieee80211req_set_filter { + u_int32_t app_filterype; /* management frame filter type */ +}; + +enum { + IEEE80211_PARAM_AUTHMODE = 3, /* Authentication Mode */ + IEEE80211_PARAM_MCASTCIPHER = 5, + IEEE80211_PARAM_MCASTKEYLEN = 6, /* multicast key length */ + IEEE80211_PARAM_UCASTCIPHER = 8, + IEEE80211_PARAM_UCASTKEYLEN = 9, /* unicast key length */ + IEEE80211_PARAM_WPA = 10, /* WPA mode (0,1,2) */ + IEEE80211_PARAM_ROAMING = 12, /* roaming mode */ + IEEE80211_PARAM_PRIVACY = 13, /* privacy invoked */ + IEEE80211_PARAM_COUNTERMEASURES = 14, /* WPA/TKIP countermeasures */ + IEEE80211_PARAM_DROPUNENCRYPTED = 15, /* discard unencrypted frames */ +}; + +/* + * Values for IEEE80211_PARAM_WPA + */ +#define WPA_MODE_WPA1 1 +#define WPA_MODE_WPA2 2 +#define WPA_MODE_AUTO 3 +#define WPA_MODE_NONE 4 + +struct ieee80211req_wpaie { + u_int8_t wpa_macaddr[IEEE80211_ADDR_LEN]; + u_int8_t wpa_ie[IEEE80211_MAX_IE]; + u_int8_t rsn_ie[IEEE80211_MAX_IE]; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* _IEEE80211_IOCTL_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/ieee80211_node.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/ieee80211_node.h --- linux-2.6.26/drivers/net/wireless/ath6k/ieee80211_node.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/ieee80211_node.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,85 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _IEEE80211_NODE_H_ +#define _IEEE80211_NODE_H_ + +/* + * Node locking definitions. + */ +#define IEEE80211_NODE_LOCK_INIT(_nt) A_MUTEX_INIT(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_LOCK_DESTROY(_nt) if (A_IS_MUTEX_VALID(&(_nt)->nt_nodelock)) { \ + A_MUTEX_DELETE(&(_nt)->nt_nodelock); } + +#define IEEE80211_NODE_LOCK(_nt) A_MUTEX_LOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_UNLOCK(_nt) A_MUTEX_UNLOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_LOCK_BH(_nt) A_MUTEX_LOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_UNLOCK_BH(_nt) A_MUTEX_UNLOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_LOCK_ASSERT(_nt) + +/* + * Node reference counting definitions. + * + * ieee80211_node_initref initialize the reference count to 1 + * ieee80211_node_incref add a reference + * ieee80211_node_decref remove a reference + * ieee80211_node_dectestref remove a reference and return 1 if this + * is the last reference, otherwise 0 + * ieee80211_node_refcnt reference count for printing (only) + */ +#define ieee80211_node_initref(_ni) ((_ni)->ni_refcnt = 1) +#define ieee80211_node_incref(_ni) ((_ni)->ni_refcnt++) +#define ieee80211_node_decref(_ni) ((_ni)->ni_refcnt--) +#define ieee80211_node_dectestref(_ni) (((_ni)->ni_refcnt--) == 1) +#define ieee80211_node_refcnt(_ni) ((_ni)->ni_refcnt) + +#define IEEE80211_NODE_HASHSIZE 32 +/* simple hash is enough for variation of macaddr */ +#define IEEE80211_NODE_HASH(addr) \ + (((const A_UINT8 *)(addr))[IEEE80211_ADDR_LEN - 1] % \ + IEEE80211_NODE_HASHSIZE) + +/* + * Table of ieee80211_node instances. Each ieee80211com + * has at least one for holding the scan candidates. + * When operating as an access point or in ibss mode there + * is a second table for associated stations or neighbors. + */ +struct ieee80211_node_table { + void *nt_wmip; /* back reference */ + A_MUTEX_T nt_nodelock; /* on node table */ + struct bss *nt_node_first; /* information of all nodes */ + struct bss *nt_node_last; /* information of all nodes */ + struct bss *nt_hash[IEEE80211_NODE_HASHSIZE]; + const char *nt_name; /* for debugging */ + A_UINT32 nt_scangen; /* gen# for timeout scan */ + A_TIMER nt_inact_timer; + A_UINT8 isTimerArmed; /* is the node timer armed */ + A_UINT32 nt_nodeAge; /* node aging time */ +#ifdef OS_ROAM_MANAGEMENT + A_UINT32 nt_si_gen; /* gen# for scan indication*/ +#endif +}; + +#define WLAN_NODE_INACT_TIMEOUT_MSEC 120000 + +#endif /* _IEEE80211_NODE_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/ini_dset.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/ini_dset.h --- linux-2.6.26/drivers/net/wireless/ath6k/ini_dset.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/ini_dset.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,90 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _INI_DSET_H_ +#define _INI_DSET_H_ + +/* + * Each of these represents a WHAL INI table, which consists + * of an "address column" followed by 1 or more "value columns". + * + * Software uses the base WHAL_INI_DATA_ID+column to access a + * DataSet that holds a particular column of data. + */ +typedef enum { +#if defined(AR6002_REV4) || defined(AR6003) +#ifdef FPGA + WHAL_INI_DATA_ID_NULL =0, + WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3,4,5 */ + WHAL_INI_DATA_ID_COMMON =6, /* 7 */ + WHAL_INI_DATA_ID_BB_RFGAIN =8, /* 9,10 */ +/* Only one LNA for FPGA */ +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 WHAL_INI_DATA_ID_BB_RFGAIN + WHAL_INI_DATA_ID_ANALOG_BANK0 =11, /* 12 */ + WHAL_INI_DATA_ID_ANALOG_BANK1 =13, /* 14 */ + WHAL_INI_DATA_ID_ANALOG_BANK2 =15, /* 16 */ + WHAL_INI_DATA_ID_ANALOG_BANK3 =17, /* 18, 19 */ + WHAL_INI_DATA_ID_ANALOG_BANK6 =20, /* 21,22 */ + WHAL_INI_DATA_ID_ANALOG_BANK7 =23, /* 24 */ +#else + WHAL_INI_DATA_ID_NULL =0, + WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3,4,5 */ + WHAL_INI_DATA_ID_COMMON =6, /* 7 */ + WHAL_INI_DATA_ID_BB_RFGAIN =8, /* 9,10 */ +/* Add these definitions for compatability */ +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 WHAL_INI_DATA_ID_BB_RFGAIN + WHAL_INI_DATA_ID_ANALOG_COMMON =11, /* 12 */ + WHAL_INI_DATA_ID_ANALOG_MODE_SPECIFIC=13, /* 14,15 */ + WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17,18 */ + WHAL_INI_DATA_ID_MODE_OVERRIDES =19, /* 20,21 */ + WHAL_INI_DATA_ID_COMMON_OVERRIDES =22, /* 23 */ + WHAL_INI_DATA_ID_ANALOG_OVERRIDES =24, /* 25,26 */ +#endif +#else + WHAL_INI_DATA_ID_NULL =0, + WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3 */ + WHAL_INI_DATA_ID_COMMON =4, /* 5 */ + WHAL_INI_DATA_ID_BB_RFGAIN =6, /* 7,8 */ +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN + WHAL_INI_DATA_ID_ANALOG_BANK1 =9, /* 10 */ + WHAL_INI_DATA_ID_ANALOG_BANK2 =11, /* 12 */ + WHAL_INI_DATA_ID_ANALOG_BANK3 =13, /* 14, 15 */ + WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17, 18 */ + WHAL_INI_DATA_ID_ANALOG_BANK7 =19, /* 20 */ + WHAL_INI_DATA_ID_MODE_OVERRIDES =21, /* 22,23 */ + WHAL_INI_DATA_ID_COMMON_OVERRIDES =24, /* 25 */ + WHAL_INI_DATA_ID_ANALOG_OVERRIDES =26, /* 27,28 */ + WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 =29, /* 30,31 */ +#endif + WHAL_INI_DATA_ID_MAX =31 +} WHAL_INI_DATA_ID; + +typedef PREPACK struct { + A_UINT16 freqIndex; // 1 - A mode 2 - B or G mode 0 - common + A_UINT16 offset; + A_UINT32 newValue; +} POSTPACK INI_DSET_REG_OVERRIDE; + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k/ioctl.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/ioctl.c --- linux-2.6.26/drivers/net/wireless/ath6k/ioctl.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/ioctl.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,3381 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#include "ar6000_drv.h" +#include "ieee80211_ioctl.h" +#include "ar6kap_common.h" + +static A_UINT8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; +static A_UINT8 null_mac[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; +extern unsigned int wmitimeout; +extern A_WAITQUEUE_HEAD arEvent; +extern int tspecCompliance; +extern int bmienable; +extern int bypasswmi; + +static int +ar6000_ioctl_get_roam_tbl(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if(wmi_get_roam_tbl_cmd(ar->arWmi) != A_OK) { + return -EIO; + } + + return 0; +} + +static int +ar6000_ioctl_get_roam_data(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + /* currently assume only roam times are required */ + if(wmi_get_roam_data_cmd(ar->arWmi, ROAM_DATA_TIME) != A_OK) { + return -EIO; + } + + + return 0; +} + +static int +ar6000_ioctl_set_roam_ctrl(struct net_device *dev, char *userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_ROAM_CTRL_CMD cmd; + A_UINT8 size = sizeof(cmd); + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if (cmd.roamCtrlType == WMI_SET_HOST_BIAS) { + if (cmd.info.bssBiasInfo.numBss > 1) { + size += (cmd.info.bssBiasInfo.numBss - 1) * sizeof(WMI_BSS_BIAS); + } + } + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if(wmi_set_roam_ctrl_cmd(ar->arWmi, &cmd, size) != A_OK) { + return -EIO; + } + + return 0; +} + +static int +ar6000_ioctl_set_powersave_timers(struct net_device *dev, char *userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_POWERSAVE_TIMERS_POLICY_CMD cmd; + A_UINT8 size = sizeof(cmd); + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if(wmi_set_powersave_timers_cmd(ar->arWmi, &cmd, size) != A_OK) { + return -EIO; + } + + return 0; +} + +static int +ar6000_ioctl_set_wmm(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_WMM_CMD cmd; + A_STATUS ret; + + if ((dev->flags & IFF_UP) != IFF_UP) { + return -EIO; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1), + sizeof(cmd))) + { + return -EFAULT; + } + + if (cmd.status == WMI_WMM_ENABLED) { + ar->arWmmEnabled = TRUE; + } else { + ar->arWmmEnabled = FALSE; + } + + ret = wmi_set_wmm_cmd(ar->arWmi, cmd.status); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_set_txop(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_WMM_TXOP_CMD cmd; + A_STATUS ret; + + if ((dev->flags & IFF_UP) != IFF_UP) { + return -EIO; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1), + sizeof(cmd))) + { + return -EFAULT; + } + + ret = wmi_set_wmm_txop(ar->arWmi, cmd.txopEnable); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_get_rd(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_STATUS ret = 0; + + if ((dev->flags & IFF_UP) != IFF_UP || ar->arWmiReady == FALSE) { + return -EIO; + } + + if(copy_to_user((char *)((unsigned int*)rq->ifr_data + 1), + &ar->arRegCode, sizeof(ar->arRegCode))) + ret = -EFAULT; + + return ret; +} + +static int +ar6000_ioctl_set_country(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_AP_SET_COUNTRY_CMD cmd; + A_STATUS ret; + + if ((dev->flags & IFF_UP) != IFF_UP) { + return -EIO; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1), + sizeof(cmd))) + { + return -EFAULT; + } + + ar->ap_profile_flag = 1; /* There is a change in profile */ + + ret = wmi_set_country(ar->arWmi, cmd.countryCode); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + + +/* Get power mode command */ +static int +ar6000_ioctl_get_power_mode(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_POWER_MODE_CMD power_mode; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + power_mode.powerMode = wmi_get_power_mode_cmd(ar->arWmi); + if (copy_to_user(rq->ifr_data, &power_mode, sizeof(WMI_POWER_MODE_CMD))) { + ret = -EFAULT; + } + + return ret; +} + + +static int +ar6000_ioctl_set_channelParams(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_CHANNEL_PARAMS_CMD cmd, *cmdp; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if( (ar->arNextMode == AP_NETWORK) && (cmd.numChannels || cmd.scanParam) ) { + A_PRINTF("ERROR: Only wmode is allowed in AP mode\n"); + return -EIO; + } + + if (cmd.numChannels > 1) { + cmdp = A_MALLOC(130); + if (copy_from_user(cmdp, rq->ifr_data, + sizeof (*cmdp) + + ((cmd.numChannels - 1) * sizeof(A_UINT16)))) + { + kfree(cmdp); + return -EFAULT; + } + } else { + cmdp = &cmd; + } + + if ((ar->arPhyCapability == WMI_11G_CAPABILITY) && + ((cmdp->phyMode == WMI_11A_MODE) || (cmdp->phyMode == WMI_11AG_MODE))) + { + ret = -EINVAL; + } + + if (!ret && + (wmi_set_channelParams_cmd(ar->arWmi, cmdp->scanParam, cmdp->phyMode, + cmdp->numChannels, cmdp->channelList) + != A_OK)) + { + ret = -EIO; + } + + if (cmd.numChannels > 1) { + kfree(cmdp); + } + + /* Set the profile change flag to allow a commit cmd */ + ar->ap_profile_flag = 1; + + return ret; +} + + +static int +ar6000_ioctl_set_snr_threshold(struct net_device *dev, struct ifreq *rq) +{ + + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SNR_THRESHOLD_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if( wmi_set_snr_threshold_params(ar->arWmi, &cmd) != A_OK ) { + ret = -EIO; + } + + return ret; +} + +static int +ar6000_ioctl_set_rssi_threshold(struct net_device *dev, struct ifreq *rq) +{ +#define SWAP_THOLD(thold1, thold2) do { \ + USER_RSSI_THOLD tmpThold; \ + tmpThold.tag = thold1.tag; \ + tmpThold.rssi = thold1.rssi; \ + thold1.tag = thold2.tag; \ + thold1.rssi = thold2.rssi; \ + thold2.tag = tmpThold.tag; \ + thold2.rssi = tmpThold.rssi; \ +} while (0) + + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_RSSI_THRESHOLD_PARAMS_CMD cmd; + USER_RSSI_PARAMS rssiParams; + A_INT32 i, j; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user((char *)&rssiParams, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(USER_RSSI_PARAMS))) { + return -EFAULT; + } + cmd.weight = rssiParams.weight; + cmd.pollTime = rssiParams.pollTime; + + A_MEMCPY(ar->rssi_map, &rssiParams.tholds, sizeof(ar->rssi_map)); + /* + * only 6 elements, so use bubble sorting, in ascending order + */ + for (i = 5; i > 0; i--) { + for (j = 0; j < i; j++) { /* above tholds */ + if (ar->rssi_map[j+1].rssi < ar->rssi_map[j].rssi) { + SWAP_THOLD(ar->rssi_map[j+1], ar->rssi_map[j]); + } else if (ar->rssi_map[j+1].rssi == ar->rssi_map[j].rssi) { + return EFAULT; + } + } + } + for (i = 11; i > 6; i--) { + for (j = 6; j < i; j++) { /* below tholds */ + if (ar->rssi_map[j+1].rssi < ar->rssi_map[j].rssi) { + SWAP_THOLD(ar->rssi_map[j+1], ar->rssi_map[j]); + } else if (ar->rssi_map[j+1].rssi == ar->rssi_map[j].rssi) { + return EFAULT; + } + } + } + +#ifdef DEBUG + for (i = 0; i < 12; i++) { + AR_DEBUG2_PRINTF("thold[%d].tag: %d, thold[%d].rssi: %d \n", + i, ar->rssi_map[i].tag, i, ar->rssi_map[i].rssi); + } +#endif + cmd.thresholdAbove1_Val = ar->rssi_map[0].rssi; + cmd.thresholdAbove2_Val = ar->rssi_map[1].rssi; + cmd.thresholdAbove3_Val = ar->rssi_map[2].rssi; + cmd.thresholdAbove4_Val = ar->rssi_map[3].rssi; + cmd.thresholdAbove5_Val = ar->rssi_map[4].rssi; + cmd.thresholdAbove6_Val = ar->rssi_map[5].rssi; + cmd.thresholdBelow1_Val = ar->rssi_map[6].rssi; + cmd.thresholdBelow2_Val = ar->rssi_map[7].rssi; + cmd.thresholdBelow3_Val = ar->rssi_map[8].rssi; + cmd.thresholdBelow4_Val = ar->rssi_map[9].rssi; + cmd.thresholdBelow5_Val = ar->rssi_map[10].rssi; + cmd.thresholdBelow6_Val = ar->rssi_map[11].rssi; + + if( wmi_set_rssi_threshold_params(ar->arWmi, &cmd) != A_OK ) { + ret = -EIO; + } + + return ret; +} + +static int +ar6000_ioctl_set_lq_threshold(struct net_device *dev, struct ifreq *rq) +{ + + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_LQ_THRESHOLD_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(cmd))) { + return -EFAULT; + } + + if( wmi_set_lq_threshold_params(ar->arWmi, &cmd) != A_OK ) { + ret = -EIO; + } + + return ret; +} + + +static int +ar6000_ioctl_set_probedSsid(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_PROBED_SSID_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_probedSsid_cmd(ar->arWmi, cmd.entryIndex, cmd.flag, cmd.ssidLength, + cmd.ssid) != A_OK) + { + ret = -EIO; + } + + return ret; +} + +static int +ar6000_ioctl_set_badAp(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_ADD_BAD_AP_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (cmd.badApIndex > WMI_MAX_BAD_AP_INDEX) { + return -EIO; + } + + if (A_MEMCMP(cmd.bssid, null_mac, AR6000_ETH_ADDR_LEN) == 0) { + /* + * This is a delete badAP. + */ + if (wmi_deleteBadAp_cmd(ar->arWmi, cmd.badApIndex) != A_OK) { + ret = -EIO; + } + } else { + if (wmi_addBadAp_cmd(ar->arWmi, cmd.badApIndex, cmd.bssid) != A_OK) { + ret = -EIO; + } + } + + return ret; +} + +static int +ar6000_ioctl_create_qos(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_CREATE_PSTREAM_CMD cmd; + A_STATUS ret; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + ret = wmi_verify_tspec_params(&cmd, tspecCompliance); + if (ret == A_OK) + ret = wmi_create_pstream_cmd(ar->arWmi, &cmd); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_delete_qos(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_DELETE_PSTREAM_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + ret = wmi_delete_pstream_cmd(ar->arWmi, cmd.trafficClass, cmd.tsid); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_get_qos_queue(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + struct ar6000_queuereq qreq; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if( copy_from_user(&qreq, rq->ifr_data, + sizeof(struct ar6000_queuereq))) + return -EFAULT; + + qreq.activeTsids = wmi_get_mapped_qos_queue(ar->arWmi, qreq.trafficClass); + + if (copy_to_user(rq->ifr_data, &qreq, + sizeof(struct ar6000_queuereq))) + { + ret = -EFAULT; + } + + return ret; +} + +#ifdef CONFIG_HOST_TCMD_SUPPORT +static A_STATUS +ar6000_ioctl_tcmd_get_rx_report(struct net_device *dev, + struct ifreq *rq, A_UINT8 *data, A_UINT32 len) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_UINT32 buf[4]; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + ar->tcmdRxReport = 0; + if (wmi_test_cmd(ar->arWmi, data, len) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->tcmdRxReport != 0, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + + buf[0] = ar->tcmdRxTotalPkt; + buf[1] = ar->tcmdRxRssi; + buf[2] = ar->tcmdRxcrcErrPkt; + buf[3] = ar->tcmdRxsecErrPkt; + if (!ret && copy_to_user(rq->ifr_data, buf, sizeof(buf))) { + ret = -EFAULT; + } + + up(&ar->arSem); + + return ret; +} + +void +ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + TCMD_CONT_RX * rx_rep = (TCMD_CONT_RX *)results; + + ar->tcmdRxTotalPkt = rx_rep->u.report.totalPkt; + ar->tcmdRxRssi = rx_rep->u.report.rssiInDBm; + ar->tcmdRxcrcErrPkt = rx_rep->u.report.crcErrPkt; + ar->tcmdRxsecErrPkt = rx_rep->u.report.secErrPkt; + ar->tcmdRxReport = 1; + + wake_up(&arEvent); +} +#endif /* CONFIG_HOST_TCMD_SUPPORT*/ + +static int +ar6000_ioctl_set_error_report_bitmask(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_TARGET_ERROR_REPORT_BITMASK cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + ret = wmi_set_error_report_bitmask(ar->arWmi, cmd.bitmask); + + return (ret==0 ? ret : -EINVAL); +} + +static int +ar6000_clear_target_stats(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + TARGET_STATS *pStats = &ar->arTargetStats; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + AR6000_SPIN_LOCK(&ar->arLock, 0); + A_MEMZERO(pStats, sizeof(TARGET_STATS)); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + return ret; +} + +static int +ar6000_ioctl_get_target_stats(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + TARGET_STATS_CMD cmd; + TARGET_STATS *pStats = &ar->arTargetStats; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + ar->statsUpdatePending = TRUE; + + if(wmi_get_stats_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + + if (!ret && copy_to_user(rq->ifr_data, pStats, sizeof(*pStats))) { + ret = -EFAULT; + } + + if (cmd.clearStats == 1) { + ret = ar6000_clear_target_stats(dev); + } + + up(&ar->arSem); + + return ret; +} + +static int +ar6000_ioctl_set_access_params(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_ACCESS_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_access_params_cmd(ar->arWmi, cmd.txop, cmd.eCWmin, cmd.eCWmax, + cmd.aifsn) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +static int +ar6000_ioctl_set_disconnect_timeout(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_DISC_TIMEOUT_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_disctimeout_cmd(ar->arWmi, cmd.disconnectTimeout) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +static int +ar6000_xioctl_set_voice_pkt_size(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_VOICE_PKT_SIZE_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_voice_pkt_size_cmd(ar->arWmi, cmd.voicePktSize) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + + return (ret); +} + +static int +ar6000_xioctl_set_max_sp_len(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_MAX_SP_LEN_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_max_sp_len_cmd(ar->arWmi, cmd.maxSPLen) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + + +static int +ar6000_xioctl_set_bt_status_cmd(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_BT_STATUS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_bt_status_cmd(ar->arWmi, cmd.streamType, cmd.status) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +static int +ar6000_xioctl_set_bt_params_cmd(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_BT_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_bt_params_cmd(ar->arWmi, &cmd) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +#ifdef CONFIG_HOST_GPIO_SUPPORT +struct ar6000_gpio_intr_wait_cmd_s gpio_intr_results; +/* gpio_reg_results and gpio_data_available are protected by arSem */ +static struct ar6000_gpio_register_cmd_s gpio_reg_results; +static A_BOOL gpio_data_available; /* Requested GPIO data available */ +static A_BOOL gpio_intr_available; /* GPIO interrupt info available */ +static A_BOOL gpio_ack_received; /* GPIO ack was received */ + +/* Host-side initialization for General Purpose I/O support */ +void ar6000_gpio_init(void) +{ + gpio_intr_available = FALSE; + gpio_data_available = FALSE; + gpio_ack_received = FALSE; +} + +/* + * Called when a GPIO interrupt is received from the Target. + * intr_values shows which GPIO pins have interrupted. + * input_values shows a recent value of GPIO pins. + */ +void +ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values) +{ + gpio_intr_results.intr_mask = intr_mask; + gpio_intr_results.input_values = input_values; + *((volatile A_BOOL *)&gpio_intr_available) = TRUE; + wake_up(&arEvent); +} + +/* + * This is called when a response is received from the Target + * for a previous or ar6000_gpio_input_get or ar6000_gpio_register_get + * call. + */ +void +ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value) +{ + gpio_reg_results.gpioreg_id = reg_id; + gpio_reg_results.value = value; + *((volatile A_BOOL *)&gpio_data_available) = TRUE; + wake_up(&arEvent); +} + +/* + * This is called when an acknowledgement is received from the Target + * for a previous or ar6000_gpio_output_set or ar6000_gpio_register_set + * call. + */ +void +ar6000_gpio_ack_rx(void) +{ + gpio_ack_received = TRUE; + wake_up(&arEvent); +} + +A_STATUS +ar6000_gpio_output_set(struct net_device *dev, + A_UINT32 set_mask, + A_UINT32 clear_mask, + A_UINT32 enable_mask, + A_UINT32 disable_mask) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + gpio_ack_received = FALSE; + return wmi_gpio_output_set(ar->arWmi, + set_mask, clear_mask, enable_mask, disable_mask); +} + +static A_STATUS +ar6000_gpio_input_get(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + *((volatile A_BOOL *)&gpio_data_available) = FALSE; + return wmi_gpio_input_get(ar->arWmi); +} + +static A_STATUS +ar6000_gpio_register_set(struct net_device *dev, + A_UINT32 gpioreg_id, + A_UINT32 value) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + gpio_ack_received = FALSE; + return wmi_gpio_register_set(ar->arWmi, gpioreg_id, value); +} + +static A_STATUS +ar6000_gpio_register_get(struct net_device *dev, + A_UINT32 gpioreg_id) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + *((volatile A_BOOL *)&gpio_data_available) = FALSE; + return wmi_gpio_register_get(ar->arWmi, gpioreg_id); +} + +static A_STATUS +ar6000_gpio_intr_ack(struct net_device *dev, + A_UINT32 ack_mask) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + gpio_intr_available = FALSE; + return wmi_gpio_intr_ack(ar->arWmi, ack_mask); +} +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +static struct prof_count_s prof_count_results; +static A_BOOL prof_count_available; /* Requested GPIO data available */ + +static A_STATUS +prof_count_get(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + *((volatile A_BOOL *)&prof_count_available) = FALSE; + return wmi_prof_count_get_cmd(ar->arWmi); +} + +/* + * This is called when a response is received from the Target + * for a previous prof_count_get call. + */ +void +prof_count_rx(A_UINT32 addr, A_UINT32 count) +{ + prof_count_results.addr = addr; + prof_count_results.count = count; + *((volatile A_BOOL *)&prof_count_available) = TRUE; + wake_up(&arEvent); +} +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + +int +ar6000_ioctl_setparam(AR_SOFTC_T *ar, int param, int value) +{ + A_BOOL profChanged = FALSE; + int ret=0; + + switch (param) { + case IEEE80211_PARAM_WPA: + switch (value) { + case WPA_MODE_WPA1: + ar->arAuthMode = WPA_AUTH; + profChanged = TRUE; + break; + case WPA_MODE_WPA2: + ar->arAuthMode = WPA2_AUTH; + profChanged = TRUE; + break; + case WPA_MODE_NONE: + ar->arAuthMode = NONE_AUTH; + profChanged = TRUE; + break; + } + break; + case IEEE80211_PARAM_AUTHMODE: + switch(value) { + case IEEE80211_AUTH_WPA_PSK: + if (WPA_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA_PSK_AUTH; + profChanged = TRUE; + } else if (WPA2_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA2_PSK_AUTH; + profChanged = TRUE; + } else { + AR_DEBUG_PRINTF("Error - Setting PSK "\ + "mode when WPA param was set to %d\n", + ar->arAuthMode); + ret = -EIO; + } + break; + case IEEE80211_AUTH_WPA_CCKM: + if (WPA2_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA2_AUTH_CCKM; + } else { + ar->arAuthMode = WPA_AUTH_CCKM; + } + break; + default: + break; + } + break; + case IEEE80211_PARAM_UCASTCIPHER: + switch (value) { + case IEEE80211_CIPHER_AES_CCM: + ar->arPairwiseCrypto = AES_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_TKIP: + ar->arPairwiseCrypto = TKIP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_WEP: + ar->arPairwiseCrypto = WEP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_NONE: + ar->arPairwiseCrypto = NONE_CRYPT; + profChanged = TRUE; + break; + } + break; + case IEEE80211_PARAM_UCASTKEYLEN: + if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) { + ret = -EIO; + } else { + ar->arPairwiseCryptoLen = value; + } + break; + case IEEE80211_PARAM_MCASTCIPHER: + switch (value) { + case IEEE80211_CIPHER_AES_CCM: + ar->arGroupCrypto = AES_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_TKIP: + ar->arGroupCrypto = TKIP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_WEP: + ar->arGroupCrypto = WEP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_NONE: + ar->arGroupCrypto = NONE_CRYPT; + profChanged = TRUE; + break; + } + break; + case IEEE80211_PARAM_MCASTKEYLEN: + if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) { + ret = -EIO; + } else { + ar->arGroupCryptoLen = value; + } + break; + case IEEE80211_PARAM_COUNTERMEASURES: + if (ar->arWmiReady == FALSE) { + return -EIO; + } + wmi_set_tkip_countermeasures_cmd(ar->arWmi, value); + break; + default: + break; + } + if ((ar->arNextMode != AP_NETWORK) && (profChanged == TRUE)) { + /* + * profile has changed. Erase ssid to signal change + */ + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + } + ar->ap_profile_flag = 1; /* There is a change in profile */ + + return ret; +} + +int +ar6000_ioctl_setkey(AR_SOFTC_T *ar, struct ieee80211req_key *ik) +{ + KEY_USAGE keyUsage; + A_STATUS status; + CRYPTO_TYPE keyType = NONE_CRYPT; + A_UINT8 null_addr[]={0x0,0x0,0x0,0x0,0x0,0x0}; + A_UINT8 bcast_addr[]={0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}; + +#ifdef USER_KEYS + ar->user_saved_keys.keyOk = FALSE; +#endif + if ( (0 == memcmp(ik->ik_macaddr, null_addr, IEEE80211_ADDR_LEN)) || + (0 == memcmp(ik->ik_macaddr, bcast_addr, IEEE80211_ADDR_LEN)) ) { + keyUsage = GROUP_USAGE; + if(ar->arNextMode == AP_NETWORK) { + A_MEMCPY(&ar->ap_mode_bkey, ik, + sizeof(struct ieee80211req_key)); + } +#ifdef USER_KEYS + A_MEMCPY(&ar->user_saved_keys.bcast_ik, ik, + sizeof(struct ieee80211req_key)); +#endif + } else { + keyUsage = PAIRWISE_USAGE; +#ifdef USER_KEYS + A_MEMCPY(&ar->user_saved_keys.ucast_ik, ik, + sizeof(struct ieee80211req_key)); +#endif + } + + switch (ik->ik_type) { + case IEEE80211_CIPHER_WEP: + keyType = WEP_CRYPT; + break; + case IEEE80211_CIPHER_TKIP: + keyType = TKIP_CRYPT; + break; + case IEEE80211_CIPHER_AES_CCM: + keyType = AES_CRYPT; + break; + default: + break; + } +#ifdef USER_KEYS + ar->user_saved_keys.keyType = keyType; +#endif + if (IEEE80211_CIPHER_CCKM_KRK != ik->ik_type) { + if (NONE_CRYPT == keyType) { + return -EIO; + } + + status = wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, keyUsage, + ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc, + ik->ik_keydata, KEY_OP_INIT_VAL, ik->ik_macaddr, + SYNC_BOTH_WMIFLAG); + + if (status != A_OK) { + return -EIO; + } + } else { + status = wmi_add_krk_cmd(ar->arWmi, ik->ik_keydata); + } + +#ifdef USER_KEYS + ar->user_saved_keys.keyOk = TRUE; +#endif + + return 0; +} + +int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + HIF_DEVICE *hifDevice = ar->arHifDevice; + int ret, param; + unsigned int address = 0; + unsigned int length = 0; + unsigned char *buffer; + char *userdata; + A_UINT32 connectCtrlFlags; + + + static WMI_SCAN_PARAMS_CMD scParams = {0, 0, 0, 0, 0, + WMI_SHORTSCANRATIO_DEFAULT, + DEFAULT_SCAN_CTRL_FLAGS, + 0}; + WMI_SET_AKMP_PARAMS_CMD akmpParams; + WMI_SET_PMKID_LIST_CMD pmkidInfo; + + if (cmd == AR6000_IOCTL_EXTENDED) { + /* + * This allows for many more wireless ioctls than would otherwise + * be available. Applications embed the actual ioctl command in + * the first word of the parameter block, and use the command + * AR6000_IOCTL_EXTENDED_CMD on the ioctl call. + */ + get_user(cmd, (int *)rq->ifr_data); + userdata = (char *)(((unsigned int *)rq->ifr_data)+1); + + if(is_xioctl_allowed(ar->arNextMode, cmd) != A_OK) { + A_PRINTF("xioctl: cmd=%d not allowed in this mode\n",cmd); + return -EOPNOTSUPP; + } + } else { + A_STATUS ret = is_iwioctl_allowed(ar->arNextMode, cmd); + if(ret == A_ENOTSUP) { + A_PRINTF("iwioctl: cmd=0x%x not allowed in this mode\n", cmd); + return -EOPNOTSUPP; + } else if (ret == A_ERROR) { + /* It is not our ioctl (out of range ioctl) */ + return -EOPNOTSUPP; + } + userdata = (char *)rq->ifr_data; + } + + if ((ar->arWlanState == WLAN_DISABLED) && + ((cmd != AR6000_XIOCTRL_WMI_SET_WLAN_STATE) && + (cmd != AR6000_XIOCTL_DIAG_READ) && + (cmd != AR6000_XIOCTL_DIAG_WRITE))) + { + return -EIO; + } + + ret = 0; + switch(cmd) + { + case IEEE80211_IOCTL_SETPARAM: + { + int param, value; + int *ptr = (int *)rq->ifr_ifru.ifru_newname; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + param = *ptr++; + value = *ptr; + ret = ar6000_ioctl_setparam(ar,param,value); + } + break; + } + case IEEE80211_IOCTL_SETKEY: + { + struct ieee80211req_key keydata; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&keydata, userdata, + sizeof(struct ieee80211req_key))) { + ret = -EFAULT; + } else { + ar6000_ioctl_setkey(ar, &keydata); + } + break; + } + case IEEE80211_IOCTL_DELKEY: + case IEEE80211_IOCTL_SETOPTIE: + { + //ret = -EIO; + break; + } + case IEEE80211_IOCTL_SETMLME: + { + struct ieee80211req_mlme mlme; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&mlme, userdata, + sizeof(struct ieee80211req_mlme))) { + ret = -EFAULT; + } else { + switch (mlme.im_op) { + case IEEE80211_MLME_AUTHORIZE: + A_PRINTF("setmlme AUTHORIZE %02X:%02X\n", + mlme.im_macaddr[4], mlme.im_macaddr[5]); + break; + case IEEE80211_MLME_UNAUTHORIZE: + A_PRINTF("setmlme UNAUTHORIZE %02X:%02X\n", + mlme.im_macaddr[4], mlme.im_macaddr[5]); + break; + case IEEE80211_MLME_DEAUTH: + A_PRINTF("setmlme DEAUTH %02X:%02X\n", + mlme.im_macaddr[4], mlme.im_macaddr[5]); + //remove_sta(ar, mlme.im_macaddr); + break; + case IEEE80211_MLME_DISASSOC: + A_PRINTF("setmlme DISASSOC %02X:%02X\n", + mlme.im_macaddr[4], mlme.im_macaddr[5]); + //remove_sta(ar, mlme.im_macaddr); + break; + default: + return 0; + } + + wmi_ap_set_mlme(ar->arWmi, mlme.im_op, mlme.im_macaddr, + mlme.im_reason); + } + break; + } + case IEEE80211_IOCTL_ADDPMKID: + { + struct ieee80211req_addpmkid req; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&req, userdata, sizeof(struct ieee80211req_addpmkid))) { + ret = -EFAULT; + } else { + A_STATUS status; + + AR_DEBUG_PRINTF("Add pmkid for %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x en=%d\n", + req.pi_bssid[0], req.pi_bssid[1], req.pi_bssid[2], + req.pi_bssid[3], req.pi_bssid[4], req.pi_bssid[5], + req.pi_enable); + + status = wmi_setPmkid_cmd(ar->arWmi, req.pi_bssid, req.pi_pmkid, + req.pi_enable); + + if (status != A_OK) { + return -EIO; + } + } + break; + } +#ifdef CONFIG_HOST_TCMD_SUPPORT + case AR6000_XIOCTL_TCMD_CONT_TX: + { + TCMD_CONT_TX txCmd; + + if (ar->tcmdPm == TCMD_PM_SLEEP) { + A_PRINTF("Can NOT send tx tcmd when target is asleep! \n"); + return -EFAULT; + } + + if(copy_from_user(&txCmd, userdata, sizeof(TCMD_CONT_TX))) + return -EFAULT; + wmi_test_cmd(ar->arWmi,(A_UINT8 *)&txCmd, sizeof(TCMD_CONT_TX)); + } + break; + case AR6000_XIOCTL_TCMD_CONT_RX: + { + TCMD_CONT_RX rxCmd; + + if (ar->tcmdPm == TCMD_PM_SLEEP) { + A_PRINTF("Can NOT send rx tcmd when target is asleep! \n"); + return -EFAULT; + } + if(copy_from_user(&rxCmd, userdata, sizeof(TCMD_CONT_RX))) + return -EFAULT; + switch(rxCmd.act) + { + case TCMD_CONT_RX_PROMIS: + case TCMD_CONT_RX_FILTER: + case TCMD_CONT_RX_SETMAC: + case TCMD_CONT_RX_SET_ANT_SWITCH_TABLE: + wmi_test_cmd(ar->arWmi,(A_UINT8 *)&rxCmd, + sizeof(TCMD_CONT_RX)); + break; + case TCMD_CONT_RX_REPORT: + ar6000_ioctl_tcmd_get_rx_report(dev, rq, + (A_UINT8 *)&rxCmd, sizeof(TCMD_CONT_RX)); + break; + default: + A_PRINTF("Unknown Cont Rx mode: %d\n",rxCmd.act); + return -EINVAL; + } + } + break; + case AR6000_XIOCTL_TCMD_PM: + { + TCMD_PM pmCmd; + + if(copy_from_user(&pmCmd, userdata, sizeof(TCMD_PM))) + return -EFAULT; + ar->tcmdPm = pmCmd.mode; + wmi_test_cmd(ar->arWmi, (A_UINT8*)&pmCmd, sizeof(TCMD_PM)); + } + break; +#endif /* CONFIG_HOST_TCMD_SUPPORT */ + + case AR6000_XIOCTL_BMI_DONE: + if(bmienable) + { + ret = ar6000_init(dev); + } + else + { + ret = BMIDone(hifDevice); + } + break; + + case AR6000_XIOCTL_BMI_READ_MEMORY: + get_user(address, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + AR_DEBUG_PRINTF("Read Memory (address: 0x%x, length: %d)\n", + address, length); + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + ret = BMIReadMemory(hifDevice, address, buffer, length); + if (copy_to_user(rq->ifr_data, buffer, length)) { + ret = -EFAULT; + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + break; + + case AR6000_XIOCTL_BMI_WRITE_MEMORY: + get_user(address, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + AR_DEBUG_PRINTF("Write Memory (address: 0x%x, length: %d)\n", + address, length); + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + if (copy_from_user(buffer, &userdata[sizeof(address) + + sizeof(length)], length)) + { + ret = -EFAULT; + } else { + ret = BMIWriteMemory(hifDevice, address, buffer, length); + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + break; + + case AR6000_XIOCTL_BMI_TEST: + AR_DEBUG_PRINTF("No longer supported\n"); + ret = -EOPNOTSUPP; + break; + + case AR6000_XIOCTL_BMI_EXECUTE: + get_user(address, (unsigned int *)userdata); + get_user(param, (unsigned int *)userdata + 1); + AR_DEBUG_PRINTF("Execute (address: 0x%x, param: %d)\n", + address, param); + ret = BMIExecute(hifDevice, address, ¶m); + put_user(param, (unsigned int *)rq->ifr_data); /* return value */ + break; + + case AR6000_XIOCTL_BMI_SET_APP_START: + get_user(address, (unsigned int *)userdata); + AR_DEBUG_PRINTF("Set App Start (address: 0x%x)\n", address); + ret = BMISetAppStart(hifDevice, address); + break; + + case AR6000_XIOCTL_BMI_READ_SOC_REGISTER: + get_user(address, (unsigned int *)userdata); + ret = BMIReadSOCRegister(hifDevice, address, ¶m); + put_user(param, (unsigned int *)rq->ifr_data); /* return value */ + break; + + case AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER: + get_user(address, (unsigned int *)userdata); + get_user(param, (unsigned int *)userdata + 1); + ret = BMIWriteSOCRegister(hifDevice, address, param); + break; + +#ifdef HTC_RAW_INTERFACE + case AR6000_XIOCTL_HTC_RAW_OPEN: + ret = A_OK; + if (!arRawIfEnabled(ar)) { + /* make sure block size is set in case the target was reset since last + * BMI phase (i.e. flashup downloads) */ + ret = ar6000_set_htc_params(ar->arHifDevice, + ar->arTargetType, + 0, /* use default yield */ + 0 /* use default number of HTC ctrl buffers */ + ); + if (A_FAILED(ret)) { + break; + } + /* Terminate the BMI phase */ + ret = BMIDone(hifDevice); + if (ret == A_OK) { + ret = ar6000_htc_raw_open(ar); + } + } + break; + + case AR6000_XIOCTL_HTC_RAW_CLOSE: + if (arRawIfEnabled(ar)) { + ret = ar6000_htc_raw_close(ar); + arRawIfEnabled(ar) = FALSE; + } else { + ret = A_ERROR; + } + break; + + case AR6000_XIOCTL_HTC_RAW_READ: + if (arRawIfEnabled(ar)) { + unsigned int streamID; + get_user(streamID, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + mb(); /* Memory barrier */ + buffer = rq->ifr_data + sizeof(length); + ret = ar6000_htc_raw_read(ar, (HTC_RAW_STREAM_ID)streamID, + buffer, length); + put_user(ret, (unsigned int *)rq->ifr_data); + } else { + ret = A_ERROR; + } + break; + + case AR6000_XIOCTL_HTC_RAW_WRITE: + if (arRawIfEnabled(ar)) { + unsigned int streamID; + get_user(streamID, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + mb(); /* Memory barrier */ + buffer = userdata + sizeof(streamID) + sizeof(length); + ret = ar6000_htc_raw_write(ar, (HTC_RAW_STREAM_ID)streamID, + buffer, length); + put_user(ret, (unsigned int *)rq->ifr_data); + } else { + ret = A_ERROR; + } + break; +#endif /* HTC_RAW_INTERFACE */ + + case AR6000_XIOCTL_BMI_LZ_STREAM_START: + get_user(address, (unsigned int *)userdata); + AR_DEBUG_PRINTF("Start Compressed Stream (address: 0x%x)\n", address); + ret = BMILZStreamStart(hifDevice, address); + break; + + case AR6000_XIOCTL_BMI_LZ_DATA: + get_user(length, (unsigned int *)userdata); + AR_DEBUG_PRINTF("Send Compressed Data (length: %d)\n", length); + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + if (copy_from_user(buffer, &userdata[sizeof(length)], length)) + { + ret = -EFAULT; + } else { + ret = BMILZData(hifDevice, buffer, length); + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + break; + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) + /* + * Optional support for Target-side profiling. + * Not needed in production. + */ + + /* Configure Target-side profiling */ + case AR6000_XIOCTL_PROF_CFG: + { + A_UINT32 period; + A_UINT32 nbins; + get_user(period, (unsigned int *)userdata); + get_user(nbins, (unsigned int *)userdata + 1); + + if (wmi_prof_cfg_cmd(ar->arWmi, period, nbins) != A_OK) { + ret = -EIO; + } + + break; + } + + /* Start a profiling bucket/bin at the specified address */ + case AR6000_XIOCTL_PROF_ADDR_SET: + { + A_UINT32 addr; + get_user(addr, (unsigned int *)userdata); + + if (wmi_prof_addr_set_cmd(ar->arWmi, addr) != A_OK) { + ret = -EIO; + } + + break; + } + + /* START Target-side profiling */ + case AR6000_XIOCTL_PROF_START: + wmi_prof_start_cmd(ar->arWmi); + break; + + /* STOP Target-side profiling */ + case AR6000_XIOCTL_PROF_STOP: + wmi_prof_stop_cmd(ar->arWmi); + break; + case AR6000_XIOCTL_PROF_COUNT_GET: + { + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + prof_count_available = FALSE; + ret = prof_count_get(dev); + if (ret != A_OK) { + up(&ar->arSem); + return -EIO; + } + + /* Wait for Target to respond. */ + wait_event_interruptible(arEvent, prof_count_available); + if (signal_pending(current)) { + ret = -EINTR; + } else { + if (copy_to_user(userdata, &prof_count_results, + sizeof(prof_count_results))) + { + ret = -EFAULT; + } + } + up(&ar->arSem); + break; + } +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + + case AR6000_IOCTL_WMI_GETREV: + { + if (copy_to_user(rq->ifr_data, &ar->arVersion, + sizeof(ar->arVersion))) + { + ret = -EFAULT; + } + break; + } + case AR6000_IOCTL_WMI_SETPWR: + { + WMI_POWER_MODE_CMD pwrModeCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&pwrModeCmd, userdata, + sizeof(pwrModeCmd))) + { + ret = -EFAULT; + } else { + if (wmi_powermode_cmd(ar->arWmi, pwrModeCmd.powerMode) + != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS: + { + WMI_IBSS_PM_CAPS_CMD ibssPmCaps; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&ibssPmCaps, userdata, + sizeof(ibssPmCaps))) + { + ret = -EFAULT; + } else { + if (wmi_ibsspmcaps_cmd(ar->arWmi, ibssPmCaps.power_saving, ibssPmCaps.ttl, + ibssPmCaps.atim_windows, ibssPmCaps.timeout_value) != A_OK) + { + ret = -EIO; + } + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arIbssPsEnable = ibssPmCaps.power_saving; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + break; + } + case AR6000_IOCTL_WMI_SET_PMPARAMS: + { + WMI_POWER_PARAMS_CMD pmParams; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&pmParams, userdata, + sizeof(pmParams))) + { + ret = -EFAULT; + } else { + if (wmi_pmparams_cmd(ar->arWmi, pmParams.idle_period, + pmParams.pspoll_number, + pmParams.dtim_policy) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SETSCAN: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&scParams, userdata, + sizeof(scParams))) + { + ret = -EFAULT; + } else { + if (CAN_SCAN_IN_CONNECT(scParams.scanCtrlFlags)) { + ar->arSkipScan = FALSE; + } else { + ar->arSkipScan = TRUE; + } + + if (wmi_scanparams_cmd(ar->arWmi, scParams.fg_start_period, + scParams.fg_end_period, + scParams.bg_period, + scParams.minact_chdwell_time, + scParams.maxact_chdwell_time, + scParams.pas_chdwell_time, + scParams.shortScanRatio, + scParams.scanCtrlFlags, + scParams.max_dfsch_act_time, + scParams.maxact_scan_per_ssid) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SETLISTENINT: + { + WMI_LISTEN_INT_CMD listenCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&listenCmd, userdata, + sizeof(listenCmd))) + { + ret = -EFAULT; + } else { + if (wmi_listeninterval_cmd(ar->arWmi, listenCmd.listenInterval, listenCmd.numBeacons) != A_OK) { + ret = -EIO; + } else { + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arListenInterval = param; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + + } + break; + } + case AR6000_IOCTL_WMI_SET_BMISS_TIME: + { + WMI_BMISS_TIME_CMD bmissCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&bmissCmd, userdata, + sizeof(bmissCmd))) + { + ret = -EFAULT; + } else { + if (wmi_bmisstime_cmd(ar->arWmi, bmissCmd.bmissTime, bmissCmd.numBeacons) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SETBSSFILTER: + { + WMI_BSS_FILTER_CMD filt; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&filt, userdata, + sizeof(filt))) + { + ret = -EFAULT; + } else { + if (wmi_bssfilter_cmd(ar->arWmi, filt.bssFilter, filt.ieMask) + != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SET_SNRTHRESHOLD: + { + ret = ar6000_ioctl_set_snr_threshold(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD: + { + ret = ar6000_ioctl_set_rssi_threshold(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_CLR_RSSISNR: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } + ret = wmi_clr_rssi_snr(ar->arWmi); + break; + } + case AR6000_XIOCTL_WMI_SET_LQTHRESHOLD: + { + ret = ar6000_ioctl_set_lq_threshold(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_SET_LPREAMBLE: + { + WMI_SET_LPREAMBLE_CMD setLpreambleCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setLpreambleCmd, userdata, + sizeof(setLpreambleCmd))) + { + ret = -EFAULT; + } else { + if (wmi_set_lpreamble_cmd(ar->arWmi, setLpreambleCmd.status) + != A_OK) + { + ret = -EIO; + } + } + + break; + } + case AR6000_XIOCTL_WMI_SET_RTS: + { + WMI_SET_RTS_CMD rtsCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&rtsCmd, userdata, + sizeof(rtsCmd))) + { + ret = -EFAULT; + } else { + if (wmi_set_rts_cmd(ar->arWmi, rtsCmd.threshold) + != A_OK) + { + ret = -EIO; + } + } + + break; + } + case AR6000_XIOCTL_WMI_SET_WMM: + { + ret = ar6000_ioctl_set_wmm(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_SET_TXOP: + { + ret = ar6000_ioctl_set_txop(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_GET_RD: + { + ret = ar6000_ioctl_get_rd(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_CHANNELPARAMS: + { + ret = ar6000_ioctl_set_channelParams(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_PROBEDSSID: + { + ret = ar6000_ioctl_set_probedSsid(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_BADAP: + { + ret = ar6000_ioctl_set_badAp(dev, rq); + break; + } + case AR6000_IOCTL_WMI_CREATE_QOS: + { + ret = ar6000_ioctl_create_qos(dev, rq); + break; + } + case AR6000_IOCTL_WMI_DELETE_QOS: + { + ret = ar6000_ioctl_delete_qos(dev, rq); + break; + } + case AR6000_IOCTL_WMI_GET_QOS_QUEUE: + { + ret = ar6000_ioctl_get_qos_queue(dev, rq); + break; + } + case AR6000_IOCTL_WMI_GET_TARGET_STATS: + { + ret = ar6000_ioctl_get_target_stats(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK: + { + ret = ar6000_ioctl_set_error_report_bitmask(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_ASSOC_INFO: + { + WMI_SET_ASSOC_INFO_CMD cmd; + A_UINT8 assocInfo[WMI_MAX_ASSOC_INFO_LEN]; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + get_user(cmd.ieType, userdata); + if (cmd.ieType >= WMI_MAX_ASSOC_INFO_TYPE) { + ret = -EIO; + } else { + get_user(cmd.bufferSize, userdata + 1); + if (cmd.bufferSize > WMI_MAX_ASSOC_INFO_LEN) { + ret = -EFAULT; + break; + } + if (copy_from_user(assocInfo, userdata + 2, + cmd.bufferSize)) + { + ret = -EFAULT; + } else { + if (wmi_associnfo_cmd(ar->arWmi, cmd.ieType, + cmd.bufferSize, + assocInfo) != A_OK) + { + ret = -EIO; + } + } + } + } + break; + } + case AR6000_IOCTL_WMI_SET_ACCESS_PARAMS: + { + ret = ar6000_ioctl_set_access_params(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_DISC_TIMEOUT: + { + ret = ar6000_ioctl_set_disconnect_timeout(dev, rq); + break; + } + case AR6000_XIOCTL_FORCE_TARGET_RESET: + { + if (ar->arHtcTarget) + { +// HTCForceReset(htcTarget); + } + else + { + AR_DEBUG_PRINTF("ar6000_ioctl cannot attempt reset.\n"); + } + break; + } + case AR6000_XIOCTL_TARGET_INFO: + case AR6000_XIOCTL_CHECK_TARGET_READY: /* backwards compatibility */ + { + /* If we made it to here, then the Target exists and is ready. */ + + if (cmd == AR6000_XIOCTL_TARGET_INFO) { + if (copy_to_user((A_UINT32 *)rq->ifr_data, &ar->arVersion.target_ver, + sizeof(ar->arVersion.target_ver))) + { + ret = -EFAULT; + } + if (copy_to_user(((A_UINT32 *)rq->ifr_data)+1, &ar->arTargetType, + sizeof(ar->arTargetType))) + { + ret = -EFAULT; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS: + { + WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD hbparam; + + if (copy_from_user(&hbparam, userdata, sizeof(hbparam))) + { + ret = -EFAULT; + } else { + AR6000_SPIN_LOCK(&ar->arLock, 0); + /* Start a cyclic timer with the parameters provided. */ + if (hbparam.frequency) { + ar->arHBChallengeResp.frequency = hbparam.frequency; + } + if (hbparam.threshold) { + ar->arHBChallengeResp.missThres = hbparam.threshold; + } + + /* Delete the pending timer and start a new one */ + if (timer_pending(&ar->arHBChallengeResp.timer)) { + A_UNTIMEOUT(&ar->arHBChallengeResp.timer); + } + A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + break; + } + case AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP: + { + A_UINT32 cookie; + + if (copy_from_user(&cookie, userdata, sizeof(cookie))) { + return -EFAULT; + } + + /* Send the challenge on the control channel */ + if (wmi_get_challenge_resp_cmd(ar->arWmi, cookie, APP_HB_CHALLENGE) != A_OK) { + return -EIO; + } + break; + } +#ifdef USER_KEYS + case AR6000_XIOCTL_USER_SETKEYS: + { + + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_RUN; + + if (copy_from_user(&ar->user_key_ctrl, userdata, + sizeof(ar->user_key_ctrl))) + { + return -EFAULT; + } + + A_PRINTF("ar6000 USER set key %x\n", ar->user_key_ctrl); + break; + } +#endif /* USER_KEYS */ + +#ifdef CONFIG_HOST_GPIO_SUPPORT + case AR6000_XIOCTL_GPIO_OUTPUT_SET: + { + struct ar6000_gpio_output_set_cmd_s gpio_output_set_cmd; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (copy_from_user(&gpio_output_set_cmd, userdata, + sizeof(gpio_output_set_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_output_set(dev, + gpio_output_set_cmd.set_mask, + gpio_output_set_cmd.clear_mask, + gpio_output_set_cmd.enable_mask, + gpio_output_set_cmd.disable_mask); + if (ret != A_OK) { + ret = EIO; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_INPUT_GET: + { + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + ret = ar6000_gpio_input_get(dev); + if (ret != A_OK) { + up(&ar->arSem); + return -EIO; + } + + /* Wait for Target to respond. */ + wait_event_interruptible(arEvent, gpio_data_available); + if (signal_pending(current)) { + ret = -EINTR; + } else { + A_ASSERT(gpio_reg_results.gpioreg_id == GPIO_ID_NONE); + + if (copy_to_user(userdata, &gpio_reg_results.value, + sizeof(gpio_reg_results.value))) + { + ret = -EFAULT; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_REGISTER_SET: + { + struct ar6000_gpio_register_cmd_s gpio_register_cmd; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (copy_from_user(&gpio_register_cmd, userdata, + sizeof(gpio_register_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_register_set(dev, + gpio_register_cmd.gpioreg_id, + gpio_register_cmd.value); + if (ret != A_OK) { + ret = EIO; + } + + /* Wait for acknowledgement from Target */ + wait_event_interruptible(arEvent, gpio_ack_received); + if (signal_pending(current)) { + ret = -EINTR; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_REGISTER_GET: + { + struct ar6000_gpio_register_cmd_s gpio_register_cmd; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (copy_from_user(&gpio_register_cmd, userdata, + sizeof(gpio_register_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_register_get(dev, gpio_register_cmd.gpioreg_id); + if (ret != A_OK) { + up(&ar->arSem); + return -EIO; + } + + /* Wait for Target to respond. */ + wait_event_interruptible(arEvent, gpio_data_available); + if (signal_pending(current)) { + ret = -EINTR; + } else { + A_ASSERT(gpio_register_cmd.gpioreg_id == gpio_reg_results.gpioreg_id); + if (copy_to_user(userdata, &gpio_reg_results, + sizeof(gpio_reg_results))) + { + ret = -EFAULT; + } + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_INTR_ACK: + { + struct ar6000_gpio_intr_ack_cmd_s gpio_intr_ack_cmd; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (copy_from_user(&gpio_intr_ack_cmd, userdata, + sizeof(gpio_intr_ack_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_intr_ack(dev, gpio_intr_ack_cmd.ack_mask); + if (ret != A_OK) { + ret = EIO; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_INTR_WAIT: + { + /* Wait for Target to report an interrupt. */ + dev_hold(dev); + rtnl_unlock(); + wait_event_interruptible(arEvent, gpio_intr_available); + rtnl_lock(); + __dev_put(dev); + + if (signal_pending(current)) { + ret = -EINTR; + } else { + if (copy_to_user(userdata, &gpio_intr_results, + sizeof(gpio_intr_results))) + { + ret = -EFAULT; + } + } + break; + } +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + + case AR6000_XIOCTL_DBGLOG_CFG_MODULE: + { + struct ar6000_dbglog_module_config_s config; + + if (copy_from_user(&config, userdata, sizeof(config))) { + return -EFAULT; + } + + /* Send the challenge on the control channel */ + if (wmi_config_debug_module_cmd(ar->arWmi, config.mmask, + config.tsr, config.rep, + config.size, config.valid) != A_OK) + { + return -EIO; + } + break; + } + + case AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS: + { + /* Send the challenge on the control channel */ + if (ar6000_dbglog_get_debug_logs(ar) != A_OK) + { + return -EIO; + } + break; + } + + case AR6000_XIOCTL_SET_ADHOC_BSSID: + { + WMI_SET_ADHOC_BSSID_CMD adhocBssid; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&adhocBssid, userdata, + sizeof(adhocBssid))) + { + ret = -EFAULT; + } else if (A_MEMCMP(adhocBssid.bssid, bcast_mac, + AR6000_ETH_ADDR_LEN) == 0) + { + ret = -EFAULT; + } else { + + A_MEMCPY(ar->arReqBssid, adhocBssid.bssid, sizeof(ar->arReqBssid)); + } + break; + } + + case AR6000_XIOCTL_SET_OPT_MODE: + { + WMI_SET_OPT_MODE_CMD optModeCmd; + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&optModeCmd, userdata, + sizeof(optModeCmd))) + { + ret = -EFAULT; + } else if (ar->arConnected && optModeCmd.optMode == SPECIAL_ON) { + ret = -EFAULT; + + } else if (wmi_set_opt_mode_cmd(ar->arWmi, optModeCmd.optMode) + != A_OK) + { + ret = -EIO; + } + break; + } + + case AR6000_XIOCTL_OPT_SEND_FRAME: + { + WMI_OPT_TX_FRAME_CMD optTxFrmCmd; + A_UINT8 data[MAX_OPT_DATA_LEN]; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&optTxFrmCmd, userdata, + sizeof(optTxFrmCmd))) + { + ret = -EFAULT; + } else if (copy_from_user(data, + userdata+sizeof(WMI_OPT_TX_FRAME_CMD)-1, + optTxFrmCmd.optIEDataLen)) + { + ret = -EFAULT; + } else { + ret = wmi_opt_tx_frame_cmd(ar->arWmi, + optTxFrmCmd.frmType, + optTxFrmCmd.dstAddr, + optTxFrmCmd.bssid, + optTxFrmCmd.optIEDataLen, + data); + } + + break; + } + case AR6000_XIOCTL_WMI_SETRETRYLIMITS: + { + WMI_SET_RETRY_LIMITS_CMD setRetryParams; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setRetryParams, userdata, + sizeof(setRetryParams))) + { + ret = -EFAULT; + } else { + if (wmi_set_retry_limits_cmd(ar->arWmi, setRetryParams.frameType, + setRetryParams.trafficClass, + setRetryParams.maxRetries, + setRetryParams.enableNotify) != A_OK) + { + ret = -EIO; + } + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arMaxRetries = setRetryParams.maxRetries; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + break; + } + + case AR6000_XIOCTL_SET_BEACON_INTVAL: + { + WMI_BEACON_INT_CMD bIntvlCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&bIntvlCmd, userdata, + sizeof(bIntvlCmd))) + { + ret = -EFAULT; + } else if (wmi_set_adhoc_bconIntvl_cmd(ar->arWmi, bIntvlCmd.beaconInterval) + != A_OK) + { + ret = -EIO; + } + if(ret == 0) { + ar->ap_profile_flag = 1; /* There is a change in profile */ + } + break; + } + case IEEE80211_IOCTL_SETAUTHALG: + { + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + struct ieee80211req_authalg req; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&req, userdata, + sizeof(struct ieee80211req_authalg))) + { + ret = -EFAULT; + } else if (req.auth_alg == AUTH_ALG_OPEN_SYSTEM) { + ar->arDot11AuthMode = OPEN_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arGroupCrypto = NONE_CRYPT; + } else if (req.auth_alg == AUTH_ALG_SHARED_KEY) { + ar->arDot11AuthMode = SHARED_AUTH; + ar->arPairwiseCrypto = WEP_CRYPT; + ar->arGroupCrypto = WEP_CRYPT; + } else if (req.auth_alg == AUTH_ALG_LEAP) { + ar->arDot11AuthMode = LEAP_AUTH; + } else { + ret = -EIO; + } + break; + } + + case AR6000_XIOCTL_SET_VOICE_PKT_SIZE: + ret = ar6000_xioctl_set_voice_pkt_size(dev, userdata); + break; + + case AR6000_XIOCTL_SET_MAX_SP: + ret = ar6000_xioctl_set_max_sp_len(dev, userdata); + break; + + case AR6000_XIOCTL_WMI_GET_ROAM_TBL: + ret = ar6000_ioctl_get_roam_tbl(dev, rq); + break; + case AR6000_XIOCTL_WMI_SET_ROAM_CTRL: + ret = ar6000_ioctl_set_roam_ctrl(dev, userdata); + break; + case AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS: + ret = ar6000_ioctl_set_powersave_timers(dev, userdata); + break; + case AR6000_XIOCTRL_WMI_GET_POWER_MODE: + ret = ar6000_ioctl_get_power_mode(dev, rq); + break; + case AR6000_XIOCTRL_WMI_SET_WLAN_STATE: + get_user(ar->arWlanState, (unsigned int *)userdata); + if (ar->arWmiReady == FALSE) { + ret = -EIO; + break; + } + + if (ar->arWlanState == WLAN_ENABLED) { + /* Enable foreground scanning */ + if (wmi_scanparams_cmd(ar->arWmi, scParams.fg_start_period, + scParams.fg_end_period, + scParams.bg_period, + scParams.minact_chdwell_time, + scParams.maxact_chdwell_time, + scParams.pas_chdwell_time, + scParams.shortScanRatio, + scParams.scanCtrlFlags, + scParams.max_dfsch_act_time, + scParams.maxact_scan_per_ssid) != A_OK) + { + ret = -EIO; + } + if (ar->arSsidLen) { + ar->arConnectPending = TRUE; + if (wmi_connect_cmd(ar->arWmi, ar->arNetworkType, + ar->arDot11AuthMode, ar->arAuthMode, + ar->arPairwiseCrypto, + ar->arPairwiseCryptoLen, + ar->arGroupCrypto, ar->arGroupCryptoLen, + ar->arSsidLen, ar->arSsid, + ar->arReqBssid, ar->arChannelHint, + ar->arConnectCtrlFlags) != A_OK) + { + ret = -EIO; + ar->arConnectPending = FALSE; + } + } + } else { + /* Disconnect from the AP and disable foreground scanning */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) { + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + wmi_disconnect_cmd(ar->arWmi); + } else { + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + + if (wmi_scanparams_cmd(ar->arWmi, 0xFFFF, 0, 0, 0, 0, 0, 0, 0xFF, 0, 0) != A_OK) + { + ret = -EIO; + } + } + break; + case AR6000_XIOCTL_WMI_GET_ROAM_DATA: + ret = ar6000_ioctl_get_roam_data(dev, rq); + break; + case AR6000_XIOCTL_WMI_SET_BT_STATUS: + ret = ar6000_xioctl_set_bt_status_cmd(dev, userdata); + break; + case AR6000_XIOCTL_WMI_SET_BT_PARAMS: + ret = ar6000_xioctl_set_bt_params_cmd(dev, userdata); + break; + case AR6000_XIOCTL_WMI_STARTSCAN: + { + WMI_START_SCAN_CMD setStartScanCmd, *cmdp; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setStartScanCmd, userdata, + sizeof(setStartScanCmd))) + { + ret = -EFAULT; + } else { + if (setStartScanCmd.numChannels > 1) { + cmdp = A_MALLOC(130); + if (copy_from_user(cmdp, userdata, + sizeof (*cmdp) + + ((setStartScanCmd.numChannels - 1) * + sizeof(A_UINT16)))) + { + kfree(cmdp); + return -EFAULT; + } + } else { + cmdp = &setStartScanCmd; + } + + if (wmi_startscan_cmd(ar->arWmi, cmdp->scanType, + cmdp->forceFgScan, + cmdp->isLegacy, + cmdp->homeDwellTime, + cmdp->forceScanInterval, + cmdp->numChannels, + cmdp->channelList) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SETFIXRATES: + { + WMI_FIX_RATES_CMD setFixRatesCmd; + A_STATUS returnStatus; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setFixRatesCmd, userdata, + sizeof(setFixRatesCmd))) + { + ret = -EFAULT; + } else { + returnStatus = wmi_set_fixrates_cmd(ar->arWmi, setFixRatesCmd.fixRateMask); + if (returnStatus == A_EINVAL) { + ret = -EINVAL; + } else if(returnStatus != A_OK) { + ret = -EIO; + } else { + ar->ap_profile_flag = 1; /* There is a change in profile */ + } + } + break; + } + + case AR6000_XIOCTL_WMI_GETFIXRATES: + { + WMI_FIX_RATES_CMD getFixRatesCmd; + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + /* Used copy_from_user/copy_to_user to access user space data */ + if (copy_from_user(&getFixRatesCmd, userdata, sizeof(getFixRatesCmd))) { + ret = -EFAULT; + } else { + ar->arRateMask = 0xFFFF; + + if (wmi_get_ratemask_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->arRateMask != 0xFFFF, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + + if (!ret) { + getFixRatesCmd.fixRateMask = ar->arRateMask; + } + + if(copy_to_user(userdata, &getFixRatesCmd, sizeof(getFixRatesCmd))) { + ret = -EFAULT; + } + + up(&ar->arSem); + } + break; + } + case AR6000_XIOCTL_WMI_SET_AUTHMODE: + { + WMI_SET_AUTH_MODE_CMD setAuthMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setAuthMode, userdata, + sizeof(setAuthMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_authmode_cmd(ar->arWmi, setAuthMode.mode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_REASSOCMODE: + { + WMI_SET_REASSOC_MODE_CMD setReassocMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setReassocMode, userdata, + sizeof(setReassocMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_reassocmode_cmd(ar->arWmi, setReassocMode.mode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_DIAG_READ: + { + A_UINT32 addr, data; + get_user(addr, (unsigned int *)userdata); + addr = TARG_VTOP(ar->arTargetType, addr); + if (ar6000_ReadRegDiag(ar->arHifDevice, &addr, &data) != A_OK) { + ret = -EIO; + } + put_user(data, (unsigned int *)userdata + 1); + break; + } + case AR6000_XIOCTL_DIAG_WRITE: + { + A_UINT32 addr, data; + get_user(addr, (unsigned int *)userdata); + get_user(data, (unsigned int *)userdata + 1); + addr = TARG_VTOP(ar->arTargetType, addr); + if (ar6000_WriteRegDiag(ar->arHifDevice, &addr, &data) != A_OK) { + ret = -EIO; + } + break; + } + case AR6000_XIOCTL_WMI_SET_KEEPALIVE: + { + WMI_SET_KEEPALIVE_CMD setKeepAlive; + if (ar->arWmiReady == FALSE) { + return -EIO; + } else if (copy_from_user(&setKeepAlive, userdata, + sizeof(setKeepAlive))){ + ret = -EFAULT; + } else { + if (wmi_set_keepalive_cmd(ar->arWmi, setKeepAlive.keepaliveInterval) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_PARAMS: + { + WMI_SET_PARAMS_CMD cmd; + if (ar->arWmiReady == FALSE) { + return -EIO; + } else if (copy_from_user(&cmd, userdata, + sizeof(cmd))){ + ret = -EFAULT; + } else if (copy_from_user(&cmd, userdata, + sizeof(cmd) + cmd.length)) + { + ret = -EFAULT; + } else { + if (wmi_set_params_cmd(ar->arWmi, cmd.opcode, cmd.length, cmd.buffer) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_MCAST_FILTER: + { + WMI_SET_MCAST_FILTER_CMD cmd; + if (ar->arWmiReady == FALSE) { + return -EIO; + } else if (copy_from_user(&cmd, userdata, + sizeof(cmd))){ + ret = -EFAULT; + } else { + if (wmi_set_mcast_filter_cmd(ar->arWmi, cmd.multicast_mac[0], + cmd.multicast_mac[1], + cmd.multicast_mac[2], + cmd.multicast_mac[3]) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_DEL_MCAST_FILTER: + { + WMI_SET_MCAST_FILTER_CMD cmd; + if (ar->arWmiReady == FALSE) { + return -EIO; + } else if (copy_from_user(&cmd, userdata, + sizeof(cmd))){ + ret = -EFAULT; + } else { + if (wmi_del_mcast_filter_cmd(ar->arWmi, cmd.multicast_mac[0], + cmd.multicast_mac[1], + cmd.multicast_mac[2], + cmd.multicast_mac[3]) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_GET_KEEPALIVE: + { + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_GET_KEEPALIVE_CMD getKeepAlive; + int ret = 0; + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (copy_from_user(&getKeepAlive, userdata,sizeof(getKeepAlive))) { + ret = -EFAULT; + } else { + getKeepAlive.keepaliveInterval = wmi_get_keepalive_cmd(ar->arWmi); + ar->arKeepaliveConfigured = 0xFF; + if (wmi_get_keepalive_configured(ar->arWmi) != A_OK){ + up(&ar->arSem); + return -EIO; + } + wait_event_interruptible_timeout(arEvent, ar->arKeepaliveConfigured != 0xFF, wmitimeout * HZ); + if (signal_pending(current)) { + ret = -EINTR; + } + + if (!ret) { + getKeepAlive.configured = ar->arKeepaliveConfigured; + } + if (copy_to_user(userdata, &getKeepAlive, sizeof(getKeepAlive))) { + ret = -EFAULT; + } + up(&ar->arSem); + } + break; + } + case AR6000_XIOCTL_WMI_SET_APPIE: + { + WMI_SET_APPIE_CMD appIEcmd; + A_UINT8 appIeInfo[IEEE80211_APPIE_FRAME_MAX_LEN]; + A_UINT32 fType,ieLen; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + get_user(fType, (A_UINT32 *)userdata); + appIEcmd.mgmtFrmType = fType; + if (appIEcmd.mgmtFrmType >= IEEE80211_APPIE_NUM_OF_FRAME) { + ret = -EIO; + } else { + get_user(ieLen, (A_UINT32 *)(userdata + 4)); + appIEcmd.ieLen = ieLen; + if (appIEcmd.ieLen > IEEE80211_APPIE_FRAME_MAX_LEN) { + ret = -EIO; + break; + } + if (copy_from_user(appIeInfo, userdata + 8, appIEcmd.ieLen)) { + ret = -EFAULT; + } else { + if (wmi_set_appie_cmd(ar->arWmi, appIEcmd.mgmtFrmType, + appIEcmd.ieLen, appIeInfo) != A_OK) + { + ret = -EIO; + } + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER: + { + WMI_BSS_FILTER_CMD cmd; + A_UINT32 filterType; + + if (copy_from_user(&filterType, userdata, sizeof(A_UINT32))) + { + return -EFAULT; + } + if (filterType & (IEEE80211_FILTER_TYPE_BEACON | + IEEE80211_FILTER_TYPE_PROBE_RESP)) + { + cmd.bssFilter = ALL_BSS_FILTER; + } else { + cmd.bssFilter = NONE_BSS_FILTER; + } + if (wmi_bssfilter_cmd(ar->arWmi, cmd.bssFilter, 0) != A_OK) { + ret = -EIO; + } + + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arMgmtFilter = filterType; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + break; + } + case AR6000_XIOCTL_WMI_SET_WSC_STATUS: + { + A_UINT32 wsc_status; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } else if (copy_from_user(&wsc_status, userdata, sizeof(A_UINT32))) + { + return -EFAULT; + } + if (wmi_set_wsc_status_cmd(ar->arWmi, wsc_status) != A_OK) { + ret = -EIO; + } + break; + } + case AR6000_XIOCTL_BMI_ROMPATCH_INSTALL: + { + A_UINT32 ROM_addr; + A_UINT32 RAM_addr; + A_UINT32 nbytes; + A_UINT32 do_activate; + A_UINT32 rompatch_id; + + get_user(ROM_addr, (A_UINT32 *)userdata); + get_user(RAM_addr, (A_UINT32 *)userdata + 1); + get_user(nbytes, (A_UINT32 *)userdata + 2); + get_user(do_activate, (A_UINT32 *)userdata + 3); + AR_DEBUG_PRINTF("Install rompatch from ROM: 0x%x to RAM: 0x%x length: %d\n", + ROM_addr, RAM_addr, nbytes); + ret = BMIrompatchInstall(hifDevice, ROM_addr, RAM_addr, + nbytes, do_activate, &rompatch_id); + if (ret == A_OK) { + put_user(rompatch_id, (unsigned int *)rq->ifr_data); /* return value */ + } + break; + } + + case AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL: + { + A_UINT32 rompatch_id; + + get_user(rompatch_id, (A_UINT32 *)userdata); + AR_DEBUG_PRINTF("UNinstall rompatch_id %d\n", rompatch_id); + ret = BMIrompatchUninstall(hifDevice, rompatch_id); + break; + } + + case AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE: + case AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE: + { + A_UINT32 rompatch_count; + + get_user(rompatch_count, (A_UINT32 *)userdata); + AR_DEBUG_PRINTF("Change rompatch activation count=%d\n", rompatch_count); + length = sizeof(A_UINT32) * rompatch_count; + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + if (copy_from_user(buffer, &userdata[sizeof(rompatch_count)], length)) + { + ret = -EFAULT; + } else { + if (cmd == AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE) { + ret = BMIrompatchActivate(hifDevice, rompatch_count, (A_UINT32 *)buffer); + } else { + ret = BMIrompatchDeactivate(hifDevice, rompatch_count, (A_UINT32 *)buffer); + } + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + + break; + } + case AR6000_XIOCTL_SET_IP: + { + WMI_SET_IP_CMD setIP; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setIP, userdata, + sizeof(setIP))) + { + ret = -EFAULT; + } else { + if (wmi_set_ip_cmd(ar->arWmi, + &setIP) != A_OK) + { + ret = -EIO; + } + } + break; + } + + case AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE: + { + WMI_SET_HOST_SLEEP_MODE_CMD setHostSleepMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setHostSleepMode, userdata, + sizeof(setHostSleepMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_host_sleep_mode_cmd(ar->arWmi, + &setHostSleepMode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_WOW_MODE: + { + WMI_SET_WOW_MODE_CMD setWowMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setWowMode, userdata, + sizeof(setWowMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_wow_mode_cmd(ar->arWmi, + &setWowMode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_GET_WOW_LIST: + { + WMI_GET_WOW_LIST_CMD getWowList; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&getWowList, userdata, + sizeof(getWowList))) + { + ret = -EFAULT; + } else { + if (wmi_get_wow_list_cmd(ar->arWmi, + &getWowList) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_ADD_WOW_PATTERN: + { +#define WOW_PATTERN_SIZE 64 +#define WOW_MASK_SIZE 64 + + WMI_ADD_WOW_PATTERN_CMD cmd; + A_UINT8 mask_data[WOW_PATTERN_SIZE]={0}; + A_UINT8 pattern_data[WOW_PATTERN_SIZE]={0}; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + + if(copy_from_user(&cmd, userdata, + sizeof(WMI_ADD_WOW_PATTERN_CMD))) + return -EFAULT; + if (copy_from_user(pattern_data, + userdata + 3, + cmd.filter_size)){ + ret = -EFAULT; + break; + } + if (copy_from_user(mask_data, + (userdata + 3 + cmd.filter_size), + cmd.filter_size)){ + ret = -EFAULT; + break; + } else { + if (wmi_add_wow_pattern_cmd(ar->arWmi, + &cmd, pattern_data, mask_data, cmd.filter_size) != A_OK){ + ret = -EIO; + } + } + } +#undef WOW_PATTERN_SIZE +#undef WOW_MASK_SIZE + break; + } + case AR6000_XIOCTL_WMI_DEL_WOW_PATTERN: + { + WMI_DEL_WOW_PATTERN_CMD delWowPattern; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&delWowPattern, userdata, + sizeof(delWowPattern))) + { + ret = -EFAULT; + } else { + if (wmi_del_wow_pattern_cmd(ar->arWmi, + &delWowPattern) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE: + if (ar->arHtcTarget != NULL) { + HTCDumpCreditStates(ar->arHtcTarget); + } + break; + case AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE: + if (ar->arHtcTarget != NULL) { + struct ar6000_traffic_activity_change data; + + if (copy_from_user(&data, userdata, sizeof(data))) + { + return -EFAULT; + } + /* note, this is used for testing (mbox ping testing), indicate activity + * change using the stream ID as the traffic class */ + ar6000_indicate_tx_activity(ar, + (A_UINT8)data.StreamID, + data.Active ? TRUE : FALSE); + } + break; + case AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&connectCtrlFlags, userdata, + sizeof(connectCtrlFlags))) + { + ret = -EFAULT; + } else { + ar->arConnectCtrlFlags = connectCtrlFlags; + } + break; + case AR6000_XIOCTL_WMI_SET_AKMP_PARAMS: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&akmpParams, userdata, + sizeof(WMI_SET_AKMP_PARAMS_CMD))) + { + ret = -EFAULT; + } else { + if (wmi_set_akmp_params_cmd(ar->arWmi, &akmpParams) != A_OK) { + ret = -EIO; + } + } + break; + case AR6000_XIOCTL_WMI_SET_PMKID_LIST: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + if (copy_from_user(&pmkidInfo.numPMKID, userdata, + sizeof(pmkidInfo.numPMKID))) + { + ret = -EFAULT; + break; + } + if (copy_from_user(&pmkidInfo.pmkidList, + userdata + sizeof(pmkidInfo.numPMKID), + pmkidInfo.numPMKID * sizeof(WMI_PMKID))) + { + ret = -EFAULT; + break; + } + if (wmi_set_pmkid_list_cmd(ar->arWmi, &pmkidInfo) != A_OK) { + ret = -EIO; + } + } + break; + case AR6000_XIOCTL_WMI_GET_PMKID_LIST: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + if (wmi_get_pmkid_list_cmd(ar->arWmi) != A_OK) { + ret = -EIO; + } + } + break; + case AR6000_XIOCTL_WMI_ABORT_SCAN: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } + ret = wmi_abort_scan_cmd(ar->arWmi); + break; + case AR6000_XIOCTL_AP_HIDDEN_SSID: + { + A_UINT8 hidden_ssid; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&hidden_ssid, userdata, sizeof(hidden_ssid))) { + ret = -EFAULT; + } else { + wmi_ap_set_hidden_ssid(ar->arWmi, hidden_ssid); + ar->ap_profile_flag = 1; /* There is a change in profile */ + } + break; + } + case AR6000_XIOCTL_AP_GET_STA_LIST: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + A_UINT8 i; + ap_get_sta_t temp; + A_MEMZERO(&temp, sizeof(temp)); + for(i=0;ista_list[i].mac, ATH_MAC_LEN); + temp.sta[i].aid = ar->sta_list[i].aid; + } + if(copy_to_user((ap_get_sta_t *)rq->ifr_data, &temp, + sizeof(ar->sta_list))) { + ret = -EFAULT; + } + } + break; + } + case AR6000_XIOCTL_AP_SET_NUM_STA: + { + A_UINT8 num_sta; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&num_sta, userdata, sizeof(num_sta))) { + ret = -EFAULT; + } else if(num_sta > AP_MAX_NUM_STA) { + /* value out of range */ + ret = -EINVAL; + } else { + wmi_ap_set_num_sta(ar->arWmi, num_sta); + } + break; + } + case AR6000_XIOCTL_AP_SET_ACL_POLICY: + { + A_UINT8 policy; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&policy, userdata, sizeof(policy))) { + ret = -EFAULT; + } else if(policy == ar->g_acl.policy) { + /* No change in policy */ + } else { + if(!(policy & AP_ACL_RETAIN_LIST_MASK)) { + /* clear ACL list */ + memset(&ar->g_acl,0,sizeof(WMI_AP_ACL)); + } + ar->g_acl.policy = policy; + wmi_ap_set_acl_policy(ar->arWmi, policy); + } + break; + } + case AR6000_XIOCTL_AP_SET_ACL_MAC: + { + WMI_AP_ACL_MAC_CMD acl; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&acl, userdata, sizeof(acl))) { + ret = -EFAULT; + } else { + if(acl_add_del_mac(&ar->g_acl, &acl)) { + wmi_ap_acl_mac_list(ar->arWmi, &acl); + } else { + A_PRINTF("ACL list error\n"); + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_AP_GET_ACL_LIST: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if(copy_to_user((WMI_AP_ACL *)rq->ifr_data, &ar->g_acl, + sizeof(WMI_AP_ACL))) { + ret = -EFAULT; + } + break; + } + case AR6000_XIOCTL_AP_COMMIT_CONFIG: + { + ret = ar6000_ap_mode_profile_commit(ar); + break; + } + case IEEE80211_IOCTL_GETWPAIE: + { + struct ieee80211req_wpaie wpaie; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&wpaie, userdata, sizeof(wpaie))) { + ret = -EFAULT; + } else if (ar6000_ap_mode_get_wpa_ie(ar, &wpaie)) { + ret = -EFAULT; + } else if(copy_to_user(userdata, &wpaie, sizeof(wpaie))) { + ret = -EFAULT; + } + break; + } + case AR6000_XIOCTL_AP_CONN_INACT_TIME: + { + A_UINT32 period; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&period, userdata, sizeof(period))) { + ret = -EFAULT; + } else { + wmi_ap_conn_inact_time(ar->arWmi, period); + } + break; + } + case AR6000_XIOCTL_AP_PROT_SCAN_TIME: + { + WMI_AP_PROT_SCAN_TIME_CMD bgscan; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&bgscan, userdata, sizeof(bgscan))) { + ret = -EFAULT; + } else { + wmi_ap_bgscan_time(ar->arWmi, bgscan.period_min, bgscan.dwell_ms); + } + break; + } + case AR6000_XIOCTL_AP_SET_COUNTRY: + { + ret = ar6000_ioctl_set_country(dev, rq); + break; + } + case AR6000_XIOCTL_AP_SET_DTIM: + { + WMI_AP_SET_DTIM_CMD d; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&d, userdata, sizeof(d))) { + ret = -EFAULT; + } else { + if(d.dtim > 0 && d.dtim < 11) { + wmi_ap_set_dtim(ar->arWmi, d.dtim); + ar->ap_profile_flag = 1; /* There is a change in profile */ + } else { + A_PRINTF("DTIM out of range. Valid range is [1-10]\n"); + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT: + { + WMI_SET_TARGET_EVENT_REPORT_CMD evtCfgCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } + if (copy_from_user(&evtCfgCmd, userdata, + sizeof(evtCfgCmd))) { + ret = -EFAULT; + break; + } + ret = wmi_set_target_event_report_cmd(ar->arWmi, &evtCfgCmd); + break; + } + case AR6000_XIOCTL_AP_INTRA_BSS_COMM: + { + A_UINT8 intra=0; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&intra, userdata, sizeof(intra))) { + ret = -EFAULT; + } else { + ar->intra_bss = (intra?1:0); + } + break; + } + default: + ret = -EOPNOTSUPP; + } + return ret; +} + +A_UINT8 mac_cmp_wild(A_UINT8 *mac, A_UINT8 *new_mac, A_UINT8 wild, A_UINT8 new_wild) +{ + A_UINT8 i; + + for(i=0;i=0;i--) + { + if(mac_cmp_wild(a->acl_mac[i], acl->mac, a->wildcard[i], + acl->wildcard)==0) + already_avail = i; + + if(!((1 << i) & a->index)) + free_slot = i; + } + + if(acl->action == ADD_MAC_ADDR) + { + /* Dont add mac if it is already available */ + if((already_avail >= 0) || (free_slot == -1)) + return 0; + + A_MEMCPY(a->acl_mac[free_slot], acl->mac, ATH_MAC_LEN); + a->index = a->index | (1 << free_slot); + acl->index = free_slot; + a->wildcard[free_slot] = acl->wildcard; + return 1; + } + else if(acl->action == DEL_MAC_ADDR) + { + if(acl->index > AP_ACL_SIZE) + return 0; + + if(!(a->index & (1 << acl->index))) + return 0; + + A_MEMZERO(a->acl_mac[acl->index],ATH_MAC_LEN); + a->index = a->index & ~(1 << acl->index); + a->wildcard[acl->index] = 0; + return 1; + } + + return 0; +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k/mbox_host_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/mbox_host_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k/mbox_host_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/mbox_host_reg.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,409 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MBOX_HOST_REG_REG_H_ +#define _MBOX_HOST_REG_REG_H_ + +#define HOST_INT_STATUS_ADDRESS 0x00000400 +#define HOST_INT_STATUS_OFFSET 0x00000400 +#define HOST_INT_STATUS_ERROR_MSB 7 +#define HOST_INT_STATUS_ERROR_LSB 7 +#define HOST_INT_STATUS_ERROR_MASK 0x00000080 +#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB) +#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK) +#define HOST_INT_STATUS_CPU_MSB 6 +#define HOST_INT_STATUS_CPU_LSB 6 +#define HOST_INT_STATUS_CPU_MASK 0x00000040 +#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB) +#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK) +#define HOST_INT_STATUS_DRAGON_INT_MSB 5 +#define HOST_INT_STATUS_DRAGON_INT_LSB 5 +#define HOST_INT_STATUS_DRAGON_INT_MASK 0x00000020 +#define HOST_INT_STATUS_DRAGON_INT_GET(x) (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB) +#define HOST_INT_STATUS_DRAGON_INT_SET(x) (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK) +#define HOST_INT_STATUS_COUNTER_MSB 4 +#define HOST_INT_STATUS_COUNTER_LSB 4 +#define HOST_INT_STATUS_COUNTER_MASK 0x00000010 +#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB) +#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK) +#define HOST_INT_STATUS_MBOX_DATA_MSB 3 +#define HOST_INT_STATUS_MBOX_DATA_LSB 0 +#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f +#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB) +#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ADDRESS 0x00000401 +#define CPU_INT_STATUS_OFFSET 0x00000401 +#define CPU_INT_STATUS_BIT_MSB 7 +#define CPU_INT_STATUS_BIT_LSB 0 +#define CPU_INT_STATUS_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB) +#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK) + +#define ERROR_INT_STATUS_ADDRESS 0x00000402 +#define ERROR_INT_STATUS_OFFSET 0x00000402 +#define ERROR_INT_STATUS_SPI_MSB 3 +#define ERROR_INT_STATUS_SPI_LSB 3 +#define ERROR_INT_STATUS_SPI_MASK 0x00000008 +#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB) +#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK) +#define ERROR_INT_STATUS_WAKEUP_MSB 2 +#define ERROR_INT_STATUS_WAKEUP_LSB 2 +#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 +#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB) +#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK) +#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB) +#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) +#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB) +#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ADDRESS 0x00000403 +#define COUNTER_INT_STATUS_OFFSET 0x00000403 +#define COUNTER_INT_STATUS_COUNTER_MSB 7 +#define COUNTER_INT_STATUS_COUNTER_LSB 0 +#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff +#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB) +#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK) + +#define MBOX_FRAME_ADDRESS 0x00000404 +#define MBOX_FRAME_OFFSET 0x00000404 +#define MBOX_FRAME_RX_EOM_MSB 7 +#define MBOX_FRAME_RX_EOM_LSB 4 +#define MBOX_FRAME_RX_EOM_MASK 0x000000f0 +#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB) +#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK) +#define MBOX_FRAME_RX_SOM_MSB 3 +#define MBOX_FRAME_RX_SOM_LSB 0 +#define MBOX_FRAME_RX_SOM_MASK 0x0000000f +#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB) +#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK) + +#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405 +#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405 +#define RX_LOOKAHEAD_VALID_MBOX_MSB 3 +#define RX_LOOKAHEAD_VALID_MBOX_LSB 0 +#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f +#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB) +#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK) + +#define RX_LOOKAHEAD0_ADDRESS 0x00000408 +#define RX_LOOKAHEAD0_OFFSET 0x00000408 +#define RX_LOOKAHEAD0_DATA_MSB 7 +#define RX_LOOKAHEAD0_DATA_LSB 0 +#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB) +#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK) + +#define RX_LOOKAHEAD1_ADDRESS 0x0000040c +#define RX_LOOKAHEAD1_OFFSET 0x0000040c +#define RX_LOOKAHEAD1_DATA_MSB 7 +#define RX_LOOKAHEAD1_DATA_LSB 0 +#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB) +#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK) + +#define RX_LOOKAHEAD2_ADDRESS 0x00000410 +#define RX_LOOKAHEAD2_OFFSET 0x00000410 +#define RX_LOOKAHEAD2_DATA_MSB 7 +#define RX_LOOKAHEAD2_DATA_LSB 0 +#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB) +#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK) + +#define RX_LOOKAHEAD3_ADDRESS 0x00000414 +#define RX_LOOKAHEAD3_OFFSET 0x00000414 +#define RX_LOOKAHEAD3_DATA_MSB 7 +#define RX_LOOKAHEAD3_DATA_LSB 0 +#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB) +#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK) + +#define INT_STATUS_ENABLE_ADDRESS 0x00000418 +#define INT_STATUS_ENABLE_OFFSET 0x00000418 +#define INT_STATUS_ENABLE_ERROR_MSB 7 +#define INT_STATUS_ENABLE_ERROR_LSB 7 +#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080 +#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB) +#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK) +#define INT_STATUS_ENABLE_CPU_MSB 6 +#define INT_STATUS_ENABLE_CPU_LSB 6 +#define INT_STATUS_ENABLE_CPU_MASK 0x00000040 +#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB) +#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK) +#define INT_STATUS_ENABLE_DRAGON_INT_MSB 5 +#define INT_STATUS_ENABLE_DRAGON_INT_LSB 5 +#define INT_STATUS_ENABLE_DRAGON_INT_MASK 0x00000020 +#define INT_STATUS_ENABLE_DRAGON_INT_GET(x) (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB) +#define INT_STATUS_ENABLE_DRAGON_INT_SET(x) (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK) +#define INT_STATUS_ENABLE_COUNTER_MSB 4 +#define INT_STATUS_ENABLE_COUNTER_LSB 4 +#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 +#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB) +#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK) +#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3 +#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0 +#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f +#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB) +#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 +#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419 +#define CPU_INT_STATUS_ENABLE_BIT_MSB 7 +#define CPU_INT_STATUS_ENABLE_BIT_LSB 0 +#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB) +#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK) + +#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a +#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a +#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004 +#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB) +#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7 +#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 +#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB) +#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) + +#define COUNT_ADDRESS 0x00000420 +#define COUNT_OFFSET 0x00000420 +#define COUNT_VALUE_MSB 7 +#define COUNT_VALUE_LSB 0 +#define COUNT_VALUE_MASK 0x000000ff +#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB) +#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK) + +#define COUNT_DEC_ADDRESS 0x00000440 +#define COUNT_DEC_OFFSET 0x00000440 +#define COUNT_DEC_VALUE_MSB 7 +#define COUNT_DEC_VALUE_LSB 0 +#define COUNT_DEC_VALUE_MASK 0x000000ff +#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB) +#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK) + +#define SCRATCH_ADDRESS 0x00000460 +#define SCRATCH_OFFSET 0x00000460 +#define SCRATCH_VALUE_MSB 7 +#define SCRATCH_VALUE_LSB 0 +#define SCRATCH_VALUE_MASK 0x000000ff +#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB) +#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK) + +#define FIFO_TIMEOUT_ADDRESS 0x00000468 +#define FIFO_TIMEOUT_OFFSET 0x00000468 +#define FIFO_TIMEOUT_VALUE_MSB 7 +#define FIFO_TIMEOUT_VALUE_LSB 0 +#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff +#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB) +#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK) + +#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469 +#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469 +#define FIFO_TIMEOUT_ENABLE_SET_MSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_LSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001 +#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB) +#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK) + +#define DISABLE_SLEEP_ADDRESS 0x0000046a +#define DISABLE_SLEEP_OFFSET 0x0000046a +#define DISABLE_SLEEP_FOR_INT_MSB 1 +#define DISABLE_SLEEP_FOR_INT_LSB 1 +#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002 +#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB) +#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK) +#define DISABLE_SLEEP_ON_MSB 0 +#define DISABLE_SLEEP_ON_LSB 0 +#define DISABLE_SLEEP_ON_MASK 0x00000001 +#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB) +#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK) + +#define LOCAL_BUS_ADDRESS 0x00000470 +#define LOCAL_BUS_OFFSET 0x00000470 +#define LOCAL_BUS_STATE_MSB 1 +#define LOCAL_BUS_STATE_LSB 0 +#define LOCAL_BUS_STATE_MASK 0x00000003 +#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB) +#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK) + +#define INT_WLAN_ADDRESS 0x00000472 +#define INT_WLAN_OFFSET 0x00000472 +#define INT_WLAN_VECTOR_MSB 7 +#define INT_WLAN_VECTOR_LSB 0 +#define INT_WLAN_VECTOR_MASK 0x000000ff +#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB) +#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK) + +#define WINDOW_DATA_ADDRESS 0x00000474 +#define WINDOW_DATA_OFFSET 0x00000474 +#define WINDOW_DATA_DATA_MSB 7 +#define WINDOW_DATA_DATA_LSB 0 +#define WINDOW_DATA_DATA_MASK 0x000000ff +#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB) +#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK) + +#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 +#define WINDOW_WRITE_ADDR_OFFSET 0x00000478 +#define WINDOW_WRITE_ADDR_ADDR_MSB 7 +#define WINDOW_WRITE_ADDR_ADDR_LSB 0 +#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB) +#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK) + +#define WINDOW_READ_ADDR_ADDRESS 0x0000047c +#define WINDOW_READ_ADDR_OFFSET 0x0000047c +#define WINDOW_READ_ADDR_ADDR_MSB 7 +#define WINDOW_READ_ADDR_ADDR_LSB 0 +#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB) +#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK) + +#define SPI_CONFIG_ADDRESS 0x00000480 +#define SPI_CONFIG_OFFSET 0x00000480 +#define SPI_CONFIG_SPI_RESET_MSB 4 +#define SPI_CONFIG_SPI_RESET_LSB 4 +#define SPI_CONFIG_SPI_RESET_MASK 0x00000010 +#define SPI_CONFIG_SPI_RESET_GET(x) (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB) +#define SPI_CONFIG_SPI_RESET_SET(x) (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK) +#define SPI_CONFIG_INTERRUPT_ENABLE_MSB 3 +#define SPI_CONFIG_INTERRUPT_ENABLE_LSB 3 +#define SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008 +#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB) +#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) +#define SPI_CONFIG_TEST_MODE_MSB 2 +#define SPI_CONFIG_TEST_MODE_LSB 2 +#define SPI_CONFIG_TEST_MODE_MASK 0x00000004 +#define SPI_CONFIG_TEST_MODE_GET(x) (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB) +#define SPI_CONFIG_TEST_MODE_SET(x) (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK) +#define SPI_CONFIG_DATA_SIZE_MSB 1 +#define SPI_CONFIG_DATA_SIZE_LSB 0 +#define SPI_CONFIG_DATA_SIZE_MASK 0x00000003 +#define SPI_CONFIG_DATA_SIZE_GET(x) (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB) +#define SPI_CONFIG_DATA_SIZE_SET(x) (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK) + +#define SPI_STATUS_ADDRESS 0x00000481 +#define SPI_STATUS_OFFSET 0x00000481 +#define SPI_STATUS_ADDR_ERR_MSB 3 +#define SPI_STATUS_ADDR_ERR_LSB 3 +#define SPI_STATUS_ADDR_ERR_MASK 0x00000008 +#define SPI_STATUS_ADDR_ERR_GET(x) (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB) +#define SPI_STATUS_ADDR_ERR_SET(x) (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK) +#define SPI_STATUS_RD_ERR_MSB 2 +#define SPI_STATUS_RD_ERR_LSB 2 +#define SPI_STATUS_RD_ERR_MASK 0x00000004 +#define SPI_STATUS_RD_ERR_GET(x) (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB) +#define SPI_STATUS_RD_ERR_SET(x) (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK) +#define SPI_STATUS_WR_ERR_MSB 1 +#define SPI_STATUS_WR_ERR_LSB 1 +#define SPI_STATUS_WR_ERR_MASK 0x00000002 +#define SPI_STATUS_WR_ERR_GET(x) (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB) +#define SPI_STATUS_WR_ERR_SET(x) (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK) +#define SPI_STATUS_READY_MSB 0 +#define SPI_STATUS_READY_LSB 0 +#define SPI_STATUS_READY_MASK 0x00000001 +#define SPI_STATUS_READY_GET(x) (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB) +#define SPI_STATUS_READY_SET(x) (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK) + +#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482 +#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482 +#define NON_ASSOC_SLEEP_EN_BIT_MSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_LSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001 +#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB) +#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK) + +#define CIS_WINDOW_ADDRESS 0x00000600 +#define CIS_WINDOW_OFFSET 0x00000600 +#define CIS_WINDOW_DATA_MSB 7 +#define CIS_WINDOW_DATA_LSB 0 +#define CIS_WINDOW_DATA_MASK 0x000000ff +#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB) +#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mbox_host_reg_reg_s { + unsigned char pad0[1024]; /* pad to 0x400 */ + volatile unsigned char host_int_status; + volatile unsigned char cpu_int_status; + volatile unsigned char error_int_status; + volatile unsigned char counter_int_status; + volatile unsigned char mbox_frame; + volatile unsigned char rx_lookahead_valid; + unsigned char pad1[2]; /* pad to 0x408 */ + volatile unsigned char rx_lookahead0[4]; + volatile unsigned char rx_lookahead1[4]; + volatile unsigned char rx_lookahead2[4]; + volatile unsigned char rx_lookahead3[4]; + volatile unsigned char int_status_enable; + volatile unsigned char cpu_int_status_enable; + volatile unsigned char error_status_enable; + volatile unsigned char counter_int_status_enable; + unsigned char pad2[4]; /* pad to 0x420 */ + volatile unsigned char count[8]; + unsigned char pad3[24]; /* pad to 0x440 */ + volatile unsigned char count_dec[32]; + volatile unsigned char scratch[8]; + volatile unsigned char fifo_timeout; + volatile unsigned char fifo_timeout_enable; + volatile unsigned char disable_sleep; + unsigned char pad4[5]; /* pad to 0x470 */ + volatile unsigned char local_bus; + unsigned char pad5[1]; /* pad to 0x472 */ + volatile unsigned char int_wlan; + unsigned char pad6[1]; /* pad to 0x474 */ + volatile unsigned char window_data[4]; + volatile unsigned char window_write_addr[4]; + volatile unsigned char window_read_addr[4]; + volatile unsigned char spi_config; + volatile unsigned char spi_status; + volatile unsigned char non_assoc_sleep_en; + unsigned char pad7[381]; /* pad to 0x600 */ + volatile unsigned char cis_window[512]; +} mbox_host_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_HOST_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/mbox_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/mbox_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k/mbox_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/mbox_reg.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,504 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MBOX_REG_REG_H_ +#define _MBOX_REG_REG_H_ + +#define MBOX_FIFO_ADDRESS 0x00000000 +#define MBOX_FIFO_OFFSET 0x00000000 +#define MBOX_FIFO_DATA_MSB 19 +#define MBOX_FIFO_DATA_LSB 0 +#define MBOX_FIFO_DATA_MASK 0x000fffff +#define MBOX_FIFO_DATA_GET(x) (((x) & MBOX_FIFO_DATA_MASK) >> MBOX_FIFO_DATA_LSB) +#define MBOX_FIFO_DATA_SET(x) (((x) << MBOX_FIFO_DATA_LSB) & MBOX_FIFO_DATA_MASK) + +#define MBOX_FIFO_STATUS_ADDRESS 0x00000010 +#define MBOX_FIFO_STATUS_OFFSET 0x00000010 +#define MBOX_FIFO_STATUS_EMPTY_MSB 19 +#define MBOX_FIFO_STATUS_EMPTY_LSB 16 +#define MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000 +#define MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & MBOX_FIFO_STATUS_EMPTY_MASK) >> MBOX_FIFO_STATUS_EMPTY_LSB) +#define MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << MBOX_FIFO_STATUS_EMPTY_LSB) & MBOX_FIFO_STATUS_EMPTY_MASK) +#define MBOX_FIFO_STATUS_FULL_MSB 15 +#define MBOX_FIFO_STATUS_FULL_LSB 12 +#define MBOX_FIFO_STATUS_FULL_MASK 0x0000f000 +#define MBOX_FIFO_STATUS_FULL_GET(x) (((x) & MBOX_FIFO_STATUS_FULL_MASK) >> MBOX_FIFO_STATUS_FULL_LSB) +#define MBOX_FIFO_STATUS_FULL_SET(x) (((x) << MBOX_FIFO_STATUS_FULL_LSB) & MBOX_FIFO_STATUS_FULL_MASK) + +#define MBOX_DMA_POLICY_ADDRESS 0x00000014 +#define MBOX_DMA_POLICY_OFFSET 0x00000014 +#define MBOX_DMA_POLICY_TX_QUANTUM_MSB 3 +#define MBOX_DMA_POLICY_TX_QUANTUM_LSB 3 +#define MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008 +#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> MBOX_DMA_POLICY_TX_QUANTUM_LSB) +#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_TX_QUANTUM_LSB) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) +#define MBOX_DMA_POLICY_TX_ORDER_MSB 2 +#define MBOX_DMA_POLICY_TX_ORDER_LSB 2 +#define MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004 +#define MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_TX_ORDER_MASK) >> MBOX_DMA_POLICY_TX_ORDER_LSB) +#define MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_TX_ORDER_LSB) & MBOX_DMA_POLICY_TX_ORDER_MASK) +#define MBOX_DMA_POLICY_RX_QUANTUM_MSB 1 +#define MBOX_DMA_POLICY_RX_QUANTUM_LSB 1 +#define MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002 +#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> MBOX_DMA_POLICY_RX_QUANTUM_LSB) +#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_RX_QUANTUM_LSB) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) +#define MBOX_DMA_POLICY_RX_ORDER_MSB 0 +#define MBOX_DMA_POLICY_RX_ORDER_LSB 0 +#define MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001 +#define MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_RX_ORDER_MASK) >> MBOX_DMA_POLICY_RX_ORDER_LSB) +#define MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_RX_ORDER_LSB) & MBOX_DMA_POLICY_RX_ORDER_MASK) + +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c +#define MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c +#define MBOX0_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX0_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> MBOX0_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_RESUME_LSB) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX0_DMA_RX_CONTROL_START_MSB 1 +#define MBOX0_DMA_RX_CONTROL_START_LSB 1 +#define MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_START_MASK) >> MBOX0_DMA_RX_CONTROL_START_LSB) +#define MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_START_LSB) & MBOX0_DMA_RX_CONTROL_START_MASK) +#define MBOX0_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX0_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_STOP_MASK) >> MBOX0_DMA_RX_CONTROL_STOP_LSB) +#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_STOP_LSB) & MBOX0_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024 +#define MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024 +#define MBOX0_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX0_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> MBOX0_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_RESUME_LSB) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX0_DMA_TX_CONTROL_START_MSB 1 +#define MBOX0_DMA_TX_CONTROL_START_LSB 1 +#define MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_START_MASK) >> MBOX0_DMA_TX_CONTROL_START_LSB) +#define MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_START_LSB) & MBOX0_DMA_TX_CONTROL_START_MASK) +#define MBOX0_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX0_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_STOP_MASK) >> MBOX0_DMA_TX_CONTROL_STOP_LSB) +#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_STOP_LSB) & MBOX0_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c +#define MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c +#define MBOX1_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX1_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> MBOX1_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_RESUME_LSB) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX1_DMA_RX_CONTROL_START_MSB 1 +#define MBOX1_DMA_RX_CONTROL_START_LSB 1 +#define MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_START_MASK) >> MBOX1_DMA_RX_CONTROL_START_LSB) +#define MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_START_LSB) & MBOX1_DMA_RX_CONTROL_START_MASK) +#define MBOX1_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX1_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_STOP_MASK) >> MBOX1_DMA_RX_CONTROL_STOP_LSB) +#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_STOP_LSB) & MBOX1_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034 +#define MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034 +#define MBOX1_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX1_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> MBOX1_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_RESUME_LSB) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX1_DMA_TX_CONTROL_START_MSB 1 +#define MBOX1_DMA_TX_CONTROL_START_LSB 1 +#define MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_START_MASK) >> MBOX1_DMA_TX_CONTROL_START_LSB) +#define MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_START_LSB) & MBOX1_DMA_TX_CONTROL_START_MASK) +#define MBOX1_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX1_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_STOP_MASK) >> MBOX1_DMA_TX_CONTROL_STOP_LSB) +#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_STOP_LSB) & MBOX1_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c +#define MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c +#define MBOX2_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX2_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> MBOX2_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_RESUME_LSB) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX2_DMA_RX_CONTROL_START_MSB 1 +#define MBOX2_DMA_RX_CONTROL_START_LSB 1 +#define MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_START_MASK) >> MBOX2_DMA_RX_CONTROL_START_LSB) +#define MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_START_LSB) & MBOX2_DMA_RX_CONTROL_START_MASK) +#define MBOX2_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX2_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_STOP_MASK) >> MBOX2_DMA_RX_CONTROL_STOP_LSB) +#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_STOP_LSB) & MBOX2_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044 +#define MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044 +#define MBOX2_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX2_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> MBOX2_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_RESUME_LSB) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX2_DMA_TX_CONTROL_START_MSB 1 +#define MBOX2_DMA_TX_CONTROL_START_LSB 1 +#define MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_START_MASK) >> MBOX2_DMA_TX_CONTROL_START_LSB) +#define MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_START_LSB) & MBOX2_DMA_TX_CONTROL_START_MASK) +#define MBOX2_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX2_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_STOP_MASK) >> MBOX2_DMA_TX_CONTROL_STOP_LSB) +#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_STOP_LSB) & MBOX2_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c +#define MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c +#define MBOX3_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX3_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> MBOX3_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_RESUME_LSB) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX3_DMA_RX_CONTROL_START_MSB 1 +#define MBOX3_DMA_RX_CONTROL_START_LSB 1 +#define MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_START_MASK) >> MBOX3_DMA_RX_CONTROL_START_LSB) +#define MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_START_LSB) & MBOX3_DMA_RX_CONTROL_START_MASK) +#define MBOX3_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX3_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_STOP_MASK) >> MBOX3_DMA_RX_CONTROL_STOP_LSB) +#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_STOP_LSB) & MBOX3_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054 +#define MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054 +#define MBOX3_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX3_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> MBOX3_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_RESUME_LSB) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX3_DMA_TX_CONTROL_START_MSB 1 +#define MBOX3_DMA_TX_CONTROL_START_LSB 1 +#define MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_START_MASK) >> MBOX3_DMA_TX_CONTROL_START_LSB) +#define MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_START_LSB) & MBOX3_DMA_TX_CONTROL_START_MASK) +#define MBOX3_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX3_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_STOP_MASK) >> MBOX3_DMA_TX_CONTROL_STOP_LSB) +#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_STOP_LSB) & MBOX3_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX_INT_STATUS_ADDRESS 0x00000058 +#define MBOX_INT_STATUS_OFFSET 0x00000058 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_OVERFLOW_MSB 17 +#define MBOX_INT_STATUS_TX_OVERFLOW_LSB 17 +#define MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000 +#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> MBOX_INT_STATUS_TX_OVERFLOW_LSB) +#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_STATUS_TX_OVERFLOW_LSB) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) +#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16 +#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16 +#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000 +#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> MBOX_INT_STATUS_RX_UNDERFLOW_LSB) +#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) +#define MBOX_INT_STATUS_RX_NOT_FULL_MSB 11 +#define MBOX_INT_STATUS_RX_NOT_FULL_LSB 8 +#define MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00 +#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> MBOX_INT_STATUS_RX_NOT_FULL_LSB) +#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_STATUS_RX_NOT_FULL_LSB) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) +#define MBOX_INT_STATUS_HOST_MSB 7 +#define MBOX_INT_STATUS_HOST_LSB 0 +#define MBOX_INT_STATUS_HOST_MASK 0x000000ff +#define MBOX_INT_STATUS_HOST_GET(x) (((x) & MBOX_INT_STATUS_HOST_MASK) >> MBOX_INT_STATUS_HOST_LSB) +#define MBOX_INT_STATUS_HOST_SET(x) (((x) << MBOX_INT_STATUS_HOST_LSB) & MBOX_INT_STATUS_HOST_MASK) + +#define MBOX_INT_ENABLE_ADDRESS 0x0000005c +#define MBOX_INT_ENABLE_OFFSET 0x0000005c +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17 +#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17 +#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000 +#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> MBOX_INT_ENABLE_TX_OVERFLOW_LSB) +#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) +#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11 +#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8 +#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00 +#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> MBOX_INT_ENABLE_RX_NOT_FULL_LSB) +#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) +#define MBOX_INT_ENABLE_HOST_MSB 7 +#define MBOX_INT_ENABLE_HOST_LSB 0 +#define MBOX_INT_ENABLE_HOST_MASK 0x000000ff +#define MBOX_INT_ENABLE_HOST_GET(x) (((x) & MBOX_INT_ENABLE_HOST_MASK) >> MBOX_INT_ENABLE_HOST_LSB) +#define MBOX_INT_ENABLE_HOST_SET(x) (((x) << MBOX_INT_ENABLE_HOST_LSB) & MBOX_INT_ENABLE_HOST_MASK) + +#define INT_HOST_ADDRESS 0x00000060 +#define INT_HOST_OFFSET 0x00000060 +#define INT_HOST_VECTOR_MSB 7 +#define INT_HOST_VECTOR_LSB 0 +#define INT_HOST_VECTOR_MASK 0x000000ff +#define INT_HOST_VECTOR_GET(x) (((x) & INT_HOST_VECTOR_MASK) >> INT_HOST_VECTOR_LSB) +#define INT_HOST_VECTOR_SET(x) (((x) << INT_HOST_VECTOR_LSB) & INT_HOST_VECTOR_MASK) + +#define LOCAL_COUNT_ADDRESS 0x00000080 +#define LOCAL_COUNT_OFFSET 0x00000080 +#define LOCAL_COUNT_VALUE_MSB 7 +#define LOCAL_COUNT_VALUE_LSB 0 +#define LOCAL_COUNT_VALUE_MASK 0x000000ff +#define LOCAL_COUNT_VALUE_GET(x) (((x) & LOCAL_COUNT_VALUE_MASK) >> LOCAL_COUNT_VALUE_LSB) +#define LOCAL_COUNT_VALUE_SET(x) (((x) << LOCAL_COUNT_VALUE_LSB) & LOCAL_COUNT_VALUE_MASK) + +#define COUNT_INC_ADDRESS 0x000000a0 +#define COUNT_INC_OFFSET 0x000000a0 +#define COUNT_INC_VALUE_MSB 7 +#define COUNT_INC_VALUE_LSB 0 +#define COUNT_INC_VALUE_MASK 0x000000ff +#define COUNT_INC_VALUE_GET(x) (((x) & COUNT_INC_VALUE_MASK) >> COUNT_INC_VALUE_LSB) +#define COUNT_INC_VALUE_SET(x) (((x) << COUNT_INC_VALUE_LSB) & COUNT_INC_VALUE_MASK) + +#define LOCAL_SCRATCH_ADDRESS 0x000000c0 +#define LOCAL_SCRATCH_OFFSET 0x000000c0 +#define LOCAL_SCRATCH_VALUE_MSB 7 +#define LOCAL_SCRATCH_VALUE_LSB 0 +#define LOCAL_SCRATCH_VALUE_MASK 0x000000ff +#define LOCAL_SCRATCH_VALUE_GET(x) (((x) & LOCAL_SCRATCH_VALUE_MASK) >> LOCAL_SCRATCH_VALUE_LSB) +#define LOCAL_SCRATCH_VALUE_SET(x) (((x) << LOCAL_SCRATCH_VALUE_LSB) & LOCAL_SCRATCH_VALUE_MASK) + +#define USE_LOCAL_BUS_ADDRESS 0x000000e0 +#define USE_LOCAL_BUS_OFFSET 0x000000e0 +#define USE_LOCAL_BUS_PIN_INIT_MSB 0 +#define USE_LOCAL_BUS_PIN_INIT_LSB 0 +#define USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001 +#define USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & USE_LOCAL_BUS_PIN_INIT_MASK) >> USE_LOCAL_BUS_PIN_INIT_LSB) +#define USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << USE_LOCAL_BUS_PIN_INIT_LSB) & USE_LOCAL_BUS_PIN_INIT_MASK) + +#define SDIO_CONFIG_ADDRESS 0x000000e4 +#define SDIO_CONFIG_OFFSET 0x000000e4 +#define SDIO_CONFIG_CCCR_IOR1_MSB 0 +#define SDIO_CONFIG_CCCR_IOR1_LSB 0 +#define SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001 +#define SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & SDIO_CONFIG_CCCR_IOR1_MASK) >> SDIO_CONFIG_CCCR_IOR1_LSB) +#define SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << SDIO_CONFIG_CCCR_IOR1_LSB) & SDIO_CONFIG_CCCR_IOR1_MASK) + +#define MBOX_DEBUG_ADDRESS 0x000000e8 +#define MBOX_DEBUG_OFFSET 0x000000e8 +#define MBOX_DEBUG_SEL_MSB 2 +#define MBOX_DEBUG_SEL_LSB 0 +#define MBOX_DEBUG_SEL_MASK 0x00000007 +#define MBOX_DEBUG_SEL_GET(x) (((x) & MBOX_DEBUG_SEL_MASK) >> MBOX_DEBUG_SEL_LSB) +#define MBOX_DEBUG_SEL_SET(x) (((x) << MBOX_DEBUG_SEL_LSB) & MBOX_DEBUG_SEL_MASK) + +#define MBOX_FIFO_RESET_ADDRESS 0x000000ec +#define MBOX_FIFO_RESET_OFFSET 0x000000ec +#define MBOX_FIFO_RESET_INIT_MSB 0 +#define MBOX_FIFO_RESET_INIT_LSB 0 +#define MBOX_FIFO_RESET_INIT_MASK 0x00000001 +#define MBOX_FIFO_RESET_INIT_GET(x) (((x) & MBOX_FIFO_RESET_INIT_MASK) >> MBOX_FIFO_RESET_INIT_LSB) +#define MBOX_FIFO_RESET_INIT_SET(x) (((x) << MBOX_FIFO_RESET_INIT_LSB) & MBOX_FIFO_RESET_INIT_MASK) + +#define MBOX_TXFIFO_POP_ADDRESS 0x000000f0 +#define MBOX_TXFIFO_POP_OFFSET 0x000000f0 +#define MBOX_TXFIFO_POP_DATA_MSB 0 +#define MBOX_TXFIFO_POP_DATA_LSB 0 +#define MBOX_TXFIFO_POP_DATA_MASK 0x00000001 +#define MBOX_TXFIFO_POP_DATA_GET(x) (((x) & MBOX_TXFIFO_POP_DATA_MASK) >> MBOX_TXFIFO_POP_DATA_LSB) +#define MBOX_TXFIFO_POP_DATA_SET(x) (((x) << MBOX_TXFIFO_POP_DATA_LSB) & MBOX_TXFIFO_POP_DATA_MASK) + +#define MBOX_RXFIFO_POP_ADDRESS 0x00000100 +#define MBOX_RXFIFO_POP_OFFSET 0x00000100 +#define MBOX_RXFIFO_POP_DATA_MSB 0 +#define MBOX_RXFIFO_POP_DATA_LSB 0 +#define MBOX_RXFIFO_POP_DATA_MASK 0x00000001 +#define MBOX_RXFIFO_POP_DATA_GET(x) (((x) & MBOX_RXFIFO_POP_DATA_MASK) >> MBOX_RXFIFO_POP_DATA_LSB) +#define MBOX_RXFIFO_POP_DATA_SET(x) (((x) << MBOX_RXFIFO_POP_DATA_LSB) & MBOX_RXFIFO_POP_DATA_MASK) + +#define SDIO_DEBUG_ADDRESS 0x00000110 +#define SDIO_DEBUG_OFFSET 0x00000110 +#define SDIO_DEBUG_SEL_MSB 3 +#define SDIO_DEBUG_SEL_LSB 0 +#define SDIO_DEBUG_SEL_MASK 0x0000000f +#define SDIO_DEBUG_SEL_GET(x) (((x) & SDIO_DEBUG_SEL_MASK) >> SDIO_DEBUG_SEL_LSB) +#define SDIO_DEBUG_SEL_SET(x) (((x) << SDIO_DEBUG_SEL_LSB) & SDIO_DEBUG_SEL_MASK) + +#define HOST_IF_WINDOW_ADDRESS 0x00002000 +#define HOST_IF_WINDOW_OFFSET 0x00002000 +#define HOST_IF_WINDOW_DATA_MSB 7 +#define HOST_IF_WINDOW_DATA_LSB 0 +#define HOST_IF_WINDOW_DATA_MASK 0x000000ff +#define HOST_IF_WINDOW_DATA_GET(x) (((x) & HOST_IF_WINDOW_DATA_MASK) >> HOST_IF_WINDOW_DATA_LSB) +#define HOST_IF_WINDOW_DATA_SET(x) (((x) << HOST_IF_WINDOW_DATA_LSB) & HOST_IF_WINDOW_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mbox_reg_reg_s { + volatile unsigned int mbox_fifo[4]; + volatile unsigned int mbox_fifo_status; + volatile unsigned int mbox_dma_policy; + volatile unsigned int mbox0_dma_rx_descriptor_base; + volatile unsigned int mbox0_dma_rx_control; + volatile unsigned int mbox0_dma_tx_descriptor_base; + volatile unsigned int mbox0_dma_tx_control; + volatile unsigned int mbox1_dma_rx_descriptor_base; + volatile unsigned int mbox1_dma_rx_control; + volatile unsigned int mbox1_dma_tx_descriptor_base; + volatile unsigned int mbox1_dma_tx_control; + volatile unsigned int mbox2_dma_rx_descriptor_base; + volatile unsigned int mbox2_dma_rx_control; + volatile unsigned int mbox2_dma_tx_descriptor_base; + volatile unsigned int mbox2_dma_tx_control; + volatile unsigned int mbox3_dma_rx_descriptor_base; + volatile unsigned int mbox3_dma_rx_control; + volatile unsigned int mbox3_dma_tx_descriptor_base; + volatile unsigned int mbox3_dma_tx_control; + volatile unsigned int mbox_int_status; + volatile unsigned int mbox_int_enable; + volatile unsigned int int_host; + unsigned char pad0[28]; /* pad to 0x80 */ + volatile unsigned int local_count[8]; + volatile unsigned int count_inc[8]; + volatile unsigned int local_scratch[8]; + volatile unsigned int use_local_bus; + volatile unsigned int sdio_config; + volatile unsigned int mbox_debug; + volatile unsigned int mbox_fifo_reset; + volatile unsigned int mbox_txfifo_pop[4]; + volatile unsigned int mbox_rxfifo_pop[4]; + volatile unsigned int sdio_debug; + unsigned char pad1[7916]; /* pad to 0x2000 */ + volatile unsigned int host_if_window[2048]; +} mbox_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/netbuf.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/netbuf.c --- linux-2.6.26/drivers/net/wireless/ath6k/netbuf.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/netbuf.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,229 @@ + +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ +#include +#include +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "htc_packet.h" + +#define AR6000_DATA_OFFSET 64 + +void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt) +{ + skb_queue_tail((struct sk_buff_head *) q, (struct sk_buff *) pkt); +} + +void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt) +{ + skb_queue_head((struct sk_buff_head *) q, (struct sk_buff *) pkt); +} + +void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q) +{ + return((void *) skb_dequeue((struct sk_buff_head *) q)); +} + +int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q) +{ + return(skb_queue_len((struct sk_buff_head *) q)); +} + +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q) +{ + return(skb_queue_empty((struct sk_buff_head *) q)); +} + +void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q) +{ + skb_queue_head_init((struct sk_buff_head *) q); +} + +void * +a_netbuf_alloc(int size) +{ + struct sk_buff *skb; + skb = dev_alloc_skb(AR6000_DATA_OFFSET + sizeof(HTC_PACKET) + size); + skb_reserve(skb, AR6000_DATA_OFFSET + sizeof(HTC_PACKET)); + return ((void *)skb); +} + +/* + * Allocate an SKB w.o. any encapsulation requirement. + */ +void * +a_netbuf_alloc_raw(int size) +{ + struct sk_buff *skb; + + skb = dev_alloc_skb(size); + + return ((void *)skb); +} + +void +a_netbuf_free(void *bufPtr) +{ + struct sk_buff *skb = (struct sk_buff *)bufPtr; + + dev_kfree_skb(skb); +} + +A_UINT32 +a_netbuf_to_len(void *bufPtr) +{ + return (((struct sk_buff *)bufPtr)->len); +} + +void * +a_netbuf_to_data(void *bufPtr) +{ + return (((struct sk_buff *)bufPtr)->data); +} + +/* + * Add len # of bytes to the beginning of the network buffer + * pointed to by bufPtr + */ +A_STATUS +a_netbuf_push(void *bufPtr, A_INT32 len) +{ + skb_push((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Add len # of bytes to the beginning of the network buffer + * pointed to by bufPtr and also fill with data + */ +A_STATUS +a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len) +{ + skb_push((struct sk_buff *) bufPtr, len); + A_MEMCPY(((struct sk_buff *)bufPtr)->data, srcPtr, len); + + return A_OK; +} + +/* + * Add len # of bytes to the end of the network buffer + * pointed to by bufPtr + */ +A_STATUS +a_netbuf_put(void *bufPtr, A_INT32 len) +{ + skb_put((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Add len # of bytes to the end of the network buffer + * pointed to by bufPtr and also fill with data + */ +A_STATUS +a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len) +{ + char *start = ((struct sk_buff *)bufPtr)->data + + ((struct sk_buff *)bufPtr)->len; + skb_put((struct sk_buff *)bufPtr, len); + A_MEMCPY(start, srcPtr, len); + + return A_OK; +} + + +/* + * Trim the network buffer pointed to by bufPtr to len # of bytes + */ +A_STATUS +a_netbuf_setlen(void *bufPtr, A_INT32 len) +{ + skb_trim((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Chop of len # of bytes from the end of the buffer. + */ +A_STATUS +a_netbuf_trim(void *bufPtr, A_INT32 len) +{ + skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len); + + return A_OK; +} + +/* + * Chop of len # of bytes from the end of the buffer and return the data. + */ +A_STATUS +a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len) +{ + char *start = ((struct sk_buff *)bufPtr)->data + + (((struct sk_buff *)bufPtr)->len - len); + + A_MEMCPY(dstPtr, start, len); + skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len); + + return A_OK; +} + + +/* + * Returns the number of bytes available to a a_netbuf_push() + */ +A_INT32 +a_netbuf_headroom(void *bufPtr) +{ + return (skb_headroom((struct sk_buff *)bufPtr)); +} + +/* + * Removes specified number of bytes from the beginning of the buffer + */ +A_STATUS +a_netbuf_pull(void *bufPtr, A_INT32 len) +{ + skb_pull((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Removes specified number of bytes from the beginning of the buffer + * and return the data + */ +A_STATUS +a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len) +{ + A_MEMCPY(dstPtr, ((struct sk_buff *)bufPtr)->data, len); + skb_pull((struct sk_buff *)bufPtr, len); + + return A_OK; +} + diff -urN linux-2.6.26/drivers/net/wireless/ath6k/osapi_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/osapi_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k/osapi_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/osapi_linux.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,333 @@ +/* + * $Id: //depot/sw/releases/olca2.2/host/os/linux/include/osapi_linux.h#1 $ + * + * This file contains the definitions of the basic atheros data types. + * It is used to map the data types in atheros files to a platform specific + * type. + * + * Copyright 2003-2005 Atheros Communications, Inc., All Rights Reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _OSAPI_LINUX_H_ +#define _OSAPI_LINUX_H_ + +#ifdef __KERNEL__ + +#include +#include +#include +#include +#include +#include +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +#include +#endif +#include +#include +#include +#ifdef KERNEL_2_4 +#include +#include +#endif + +#ifdef __GNUC__ +#define __ATTRIB_PACK __attribute__ ((packed)) +#define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2))) +#define __ATTRIB_NORETURN __attribute__ ((noreturn)) +#ifndef INLINE +#define INLINE __inline__ +#endif +#else /* Not GCC */ +#define __ATTRIB_PACK +#define __ATTRIB_PRINTF +#define __ATTRIB_NORETURN +#ifndef INLINE +#define INLINE __inline +#endif +#endif /* End __GNUC__ */ + +#define PREPACK +#define POSTPACK __ATTRIB_PACK + +/* + * Endianes macros + */ +#define A_BE2CPU8(x) ntohb(x) +#define A_BE2CPU16(x) ntohs(x) +#define A_BE2CPU32(x) ntohl(x) + +#define A_LE2CPU8(x) (x) +#define A_LE2CPU16(x) (x) +#define A_LE2CPU32(x) (x) + +#define A_CPU2BE8(x) htonb(x) +#define A_CPU2BE16(x) htons(x) +#define A_CPU2BE32(x) htonl(x) + +#define A_MEMCPY(dst, src, len) memcpy((A_UINT8 *)(dst), (src), (len)) +#define A_MEMZERO(addr, len) memset(addr, 0, len) +#define A_MEMCMP(addr1, addr2, len) memcmp((addr1), (addr2), (len)) +#define A_MALLOC(size) kmalloc((size), GFP_KERNEL) +#define A_MALLOC_NOWAIT(size) kmalloc((size), GFP_ATOMIC) +#define A_FREE(addr) kfree(addr) +#define A_PRINTF(args...) printk(args) +#define A_SPRINTF(buf, args...) sprintf (buf, args) + +/* Mutual Exclusion */ +typedef spinlock_t A_MUTEX_T; +#define A_MUTEX_INIT(mutex) spin_lock_init(mutex) +#define A_MUTEX_LOCK(mutex) spin_lock_bh(mutex) +#define A_MUTEX_UNLOCK(mutex) spin_unlock_bh(mutex) +#define A_IS_MUTEX_VALID(mutex) TRUE /* okay to return true, since A_MUTEX_DELETE does nothing */ +#define A_MUTEX_DELETE(mutex) /* spin locks are not kernel resources so nothing to free.. */ + +/* Get current time in ms adding a constant offset (in ms) */ +#define A_GET_MS(offset) \ + (jiffies + ((offset) / 1000) * HZ) + +/* + * Timer Functions + */ +#define A_MDELAY(msecs) mdelay(msecs) +typedef struct timer_list A_TIMER; + +#define A_INIT_TIMER(pTimer, pFunction, pArg) do { \ + init_timer(pTimer); \ + (pTimer)->function = (pFunction); \ + (pTimer)->data = (unsigned long)(pArg); \ +} while (0) + +/* + * Start a Timer that elapses after 'periodMSec' milli-seconds + * Support is provided for a one-shot timer. The 'repeatFlag' is + * ignored. + */ +#define A_TIMEOUT_MS(pTimer, periodMSec, repeatFlag) do { \ + if (repeatFlag) { \ + printk("\n" __FILE__ ":%d: Timer Repeat requested\n",__LINE__); \ + panic("Timer Repeat"); \ + } \ + mod_timer((pTimer), jiffies + HZ * (periodMSec) / 1000); \ +} while (0) + +/* + * Cancel the Timer. + */ +#define A_UNTIMEOUT(pTimer) do { \ + del_timer((pTimer)); \ +} while (0) + +#define A_DELETE_TIMER(pTimer) do { \ +} while (0) + +/* + * Wait Queue related functions + */ +typedef wait_queue_head_t A_WAITQUEUE_HEAD; +#define A_INIT_WAITQUEUE_HEAD(head) init_waitqueue_head(head) +#ifndef wait_event_interruptible_timeout +#define __wait_event_interruptible_timeout(wq, condition, ret) \ +do { \ + wait_queue_t __wait; \ + init_waitqueue_entry(&__wait, current); \ + \ + add_wait_queue(&wq, &__wait); \ + for (;;) { \ + set_current_state(TASK_INTERRUPTIBLE); \ + if (condition) \ + break; \ + if (!signal_pending(current)) { \ + ret = schedule_timeout(ret); \ + if (!ret) \ + break; \ + continue; \ + } \ + ret = -ERESTARTSYS; \ + break; \ + } \ + current->state = TASK_RUNNING; \ + remove_wait_queue(&wq, &__wait); \ +} while (0) + +#define wait_event_interruptible_timeout(wq, condition, timeout) \ +({ \ + long __ret = timeout; \ + if (!(condition)) \ + __wait_event_interruptible_timeout(wq, condition, __ret); \ + __ret; \ +}) +#endif /* wait_event_interruptible_timeout */ + +#define A_WAIT_EVENT_INTERRUPTIBLE_TIMEOUT(head, condition, timeout) do { \ + wait_event_interruptible_timeout(head, condition, timeout); \ +} while (0) + +#define A_WAKE_UP(head) wake_up(head) + +#ifdef DEBUG +#define A_ASSERT(expr) \ + if (!(expr)) { \ + printk(KERN_ALERT "\n" __FILE__ ":%d: Assertion " #expr " failed!\n",__LINE__); \ + panic(#expr); \ + } + +#else +#define A_ASSERT(expr) +#endif /* DEBUG */ + +/* + * Initialization of the network buffer subsystem + */ +#define A_NETBUF_INIT() + +/* + * Network buffer queue support + */ +typedef struct sk_buff_head A_NETBUF_QUEUE_T; + +#define A_NETBUF_QUEUE_INIT(q) \ + a_netbuf_queue_init(q) + +#define A_NETBUF_ENQUEUE(q, pkt) \ + a_netbuf_enqueue((q), (pkt)) +#define A_NETBUF_PREQUEUE(q, pkt) \ + a_netbuf_prequeue((q), (pkt)) +#define A_NETBUF_DEQUEUE(q) \ + (a_netbuf_dequeue(q)) +#define A_NETBUF_QUEUE_SIZE(q) \ + a_netbuf_queue_size(q) +#define A_NETBUF_QUEUE_EMPTY(q) \ + a_netbuf_queue_empty(q) + +/* + * Network buffer support + */ +#define A_NETBUF_ALLOC(size) \ + a_netbuf_alloc(size) +#define A_NETBUF_ALLOC_RAW(size) \ + a_netbuf_alloc_raw(size) +#define A_NETBUF_FREE(bufPtr) \ + a_netbuf_free(bufPtr) +#define A_NETBUF_DATA(bufPtr) \ + a_netbuf_to_data(bufPtr) +#define A_NETBUF_LEN(bufPtr) \ + a_netbuf_to_len(bufPtr) +#define A_NETBUF_PUSH(bufPtr, len) \ + a_netbuf_push(bufPtr, len) +#define A_NETBUF_PUT(bufPtr, len) \ + a_netbuf_put(bufPtr, len) +#define A_NETBUF_TRIM(bufPtr,len) \ + a_netbuf_trim(bufPtr, len) +#define A_NETBUF_PULL(bufPtr, len) \ + a_netbuf_pull(bufPtr, len) +#define A_NETBUF_HEADROOM(bufPtr)\ + a_netbuf_headroom(bufPtr) +#define A_NETBUF_SETLEN(bufPtr,len) \ + a_netbuf_setlen(bufPtr, len) + +/* Add data to end of a buffer */ +#define A_NETBUF_PUT_DATA(bufPtr, srcPtr, len) \ + a_netbuf_put_data(bufPtr, srcPtr, len) + +/* Add data to start of the buffer */ +#define A_NETBUF_PUSH_DATA(bufPtr, srcPtr, len) \ + a_netbuf_push_data(bufPtr, srcPtr, len) + +/* Remove data at start of the buffer */ +#define A_NETBUF_PULL_DATA(bufPtr, dstPtr, len) \ + a_netbuf_pull_data(bufPtr, dstPtr, len) + +/* Remove data from the end of the buffer */ +#define A_NETBUF_TRIM_DATA(bufPtr, dstPtr, len) \ + a_netbuf_trim_data(bufPtr, dstPtr, len) + +/* View data as "size" contiguous bytes of type "t" */ +#define A_NETBUF_VIEW_DATA(bufPtr, t, size) \ + (t )( ((struct skbuf *)(bufPtr))->data) + +/* return the beginning of the headroom for the buffer */ +#define A_NETBUF_HEAD(bufPtr) \ + ((((struct sk_buff *)(bufPtr))->head)) + +/* + * OS specific network buffer access routines + */ +void *a_netbuf_alloc(int size); +void *a_netbuf_alloc_raw(int size); +void a_netbuf_free(void *bufPtr); +void *a_netbuf_to_data(void *bufPtr); +A_UINT32 a_netbuf_to_len(void *bufPtr); +A_STATUS a_netbuf_push(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len); +A_STATUS a_netbuf_put(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len); +A_STATUS a_netbuf_pull(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len); +A_STATUS a_netbuf_trim(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len); +A_STATUS a_netbuf_setlen(void *bufPtr, A_INT32 len); +A_INT32 a_netbuf_headroom(void *bufPtr); +void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt); +void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt); +void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q); +int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q); +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q); +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q); +void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q); + +/* + * Kernel v.s User space functions + */ +A_UINT32 a_copy_to_user(void *to, const void *from, A_UINT32 n); +A_UINT32 a_copy_from_user(void *to, const void *from, A_UINT32 n); + +/* In linux, WLAN Rx and Tx run in different contexts, so no need to check + * for any commands/data queued for WLAN */ +#define A_CHECK_DRV_TX() + +#else /* __KERNEL__ */ + +#ifdef __GNUC__ +#define __ATTRIB_PACK __attribute__ ((packed)) +#define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2))) +#define __ATTRIB_NORETURN __attribute__ ((noreturn)) +#ifndef INLINE +#define INLINE __inline__ +#endif +#else /* Not GCC */ +#define __ATTRIB_PACK +#define __ATTRIB_PRINTF +#define __ATTRIB_NORETURN +#ifndef INLINE +#define INLINE __inline +#endif +#endif /* End __GNUC__ */ + +#define PREPACK +#define POSTPACK __ATTRIB_PACK + +#define A_MEMCPY(dst, src, len) memcpy((dst), (src), (len)) +#define A_MEMZERO(addr, len) memset((addr), 0, (len)) +#define A_MEMCMP(addr1, addr2, len) memcmp((addr1), (addr2), (len)) +#define A_MALLOC(size) malloc(size) +#define A_FREE(addr) free(addr) +#endif /* __KERNEL__ */ + +#endif /* _OSAPI_LINUX_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/regDb.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/regDb.h --- linux-2.6.26/drivers/net/wireless/ath6k/regDb.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/regDb.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,30 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2005 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __REG_DB_H__ +#define __REG_DB_H__ + +#include "./regulatory/reg_dbschema.h" +#include "./regulatory/reg_dbvalues.h" + +#endif /* __REG_DB_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/reg_dbschema.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/reg_dbschema.h --- linux-2.6.26/drivers/net/wireless/ath6k/reg_dbschema.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/reg_dbschema.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,211 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2005 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __REG_DBSCHEMA_H__ +#define __REG_DBSCHEMA_H__ + +/* + * This file describes the regulatory DB schema, which is common between the + * 'generator' and 'parser'. The 'generator' runs on a host(typically a x86 + * Linux) and spits outs two binary files, which follow the DB file + * format(described below). The resultant output "regulatoryData_AG.bin" + * is binary file which has information regarding A and G regulatory + * information, while the "regulatoryData_G.bin" consists of G-ONLY regulatory + * information. This binary file is parsed in the target for extracting + * regulatory information. + * + * The DB values used to populate the regulatory DB are defined in + * reg_dbvalues.h + * + */ + +/* Binary data file - Representation of Regulatory DB*/ +#define REG_DATA_FILE_AG "./regulatoryData_AG.bin" +#define REG_DATA_FILE_G "./regulatoryData_G.bin" + + +/* Table tags used to encode different tables in the database */ +enum data_tags_t{ + REG_DMN_PAIR_MAPPING_TAG = 0, + REG_COUNTRY_CODE_TO_ENUM_RD_TAG, + REG_DMN_FREQ_BAND_regDmn5GhzFreq_TAG, + REG_DMN_FREQ_BAND_regDmn2Ghz11_BG_Freq_TAG, + REG_DOMAIN_TAG, + MAX_DB_TABLE_TAGS + }; + + + +/* + **************************************************************************** + * Regulatory DB file format : + * 4-bytes : "RGDB" (Magic Key) + * 4-bytes : version (Default is 5379(my extn)) + * 4-bytes : length of file + * dbType(4) + * TAG(4) + * Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data.... + * TAG(4) + * Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data.... + * TAG(4) + * Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data.... + * ... + * ... + **************************************************************************** + * + */ + +/* + * Length of the file would be filled in when the file is created and + * it would include the header size. + */ + +#define REG_DB_KEY "RGDB" /* Should be EXACTLY 4-bytes */ +#define REG_DB_VER 5379 /* Between 0-9999 */ + +#define MAGIC_KEY_OFFSET 0 +#define VERSION_OFFSET 4 +#define FILE_SZ_OFFSET 8 +#define DB_TYPE_OFFSET 12 + +#define MAGIC_KEY_SZ 4 +#define VERSION_SZ 4 +#define FILE_SZ_SZ 4 +#define DB_TYPE_SZ 4 +#define DB_TAG_SZ 4 + +#define REGDB_GET_MAGICKEY(x) ((char *)x + MAGIC_KEY_OFFSET) +#define REGDB_GET_VERSION(x) ((char *)x + VERSION_OFFSET) +#define REGDB_GET_FILESIZE(x) *((unsigned int *)((char *)x + FILE_SZ_OFFSET)) +#define REGDB_GET_DBTYPE(x) *((char *)x + DB_TYPE_OFFSET) + +#define REGDB_SET_FILESIZE(x, sz_) *((unsigned int *)((char *)x + FILE_SZ_OFFSET)) = (sz_) +#define REGDB_IS_EOF(cur, begin) ( REGDB_GET_FILESIZE(begin) > ((cur) - (begin)) ) + + +/* A Table can be search based on key as a parameter or accessed directly + * by giving its index in to the table. + */ +enum searchType { + KEY_BASED_TABLE_SEARCH = 1, + INDEX_BASED_TABLE_ACCESS + }; + + +/* Data is organised as different tables. There is a Master table, which + * holds information regarding all the tables. It does not have any + * knowledge about the attributes of the table it is holding + * but has external view of the same(for ex, how many entries, record size, + * how to search the table, total table size and reference to the data + * instance of table). + */ +typedef PREPACK struct dbMasterTable_t { /* Hold ptrs to Table data structures */ + A_CHAR numOfEntries; + A_CHAR entrySize; /* Entry size per table row */ + A_CHAR searchType; /* Index based access or key based */ + A_CHAR reserved[3]; /* for alignment */ + A_UINT16 tableSize; /* Size of this table */ + A_CHAR *dataPtr; /* Ptr to the actual Table */ +} POSTPACK dbMasterTable; /* Master table - table of tables */ + + +/* used to get the number of rows in a table */ +#define REGDB_NUM_OF_ROWS(a) (sizeof (a) / sizeof (a[0])) + +/* + * Used to set the RegDomain bitmask which chooses which frequency + * band specs are used. + */ + +#define BMLEN 2 /* Use 2 32-bit uint for channel bitmask */ +#define BMZERO {0,0} /* BMLEN zeros */ + +#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh) \ + {((((_fa >= 0) && (_fa < 32)) ? (((A_UINT32) 1) << _fa) : 0) | \ + (((_fb >= 0) && (_fb < 32)) ? (((A_UINT32) 1) << _fb) : 0) | \ + (((_fc >= 0) && (_fc < 32)) ? (((A_UINT32) 1) << _fc) : 0) | \ + (((_fd >= 0) && (_fd < 32)) ? (((A_UINT32) 1) << _fd) : 0) | \ + (((_fe >= 0) && (_fe < 32)) ? (((A_UINT32) 1) << _fe) : 0) | \ + (((_ff >= 0) && (_ff < 32)) ? (((A_UINT32) 1) << _ff) : 0) | \ + (((_fg >= 0) && (_fg < 32)) ? (((A_UINT32) 1) << _fg) : 0) | \ + (((_fh >= 0) && (_fh < 32)) ? (((A_UINT32) 1) << _fh) : 0)), \ + ((((_fa > 31) && (_fa < 64)) ? (((A_UINT32) 1) << (_fa - 32)) : 0) | \ + (((_fb > 31) && (_fb < 64)) ? (((A_UINT32) 1) << (_fb - 32)) : 0) | \ + (((_fc > 31) && (_fc < 64)) ? (((A_UINT32) 1) << (_fc - 32)) : 0) | \ + (((_fd > 31) && (_fd < 64)) ? (((A_UINT32) 1) << (_fd - 32)) : 0) | \ + (((_fe > 31) && (_fe < 64)) ? (((A_UINT32) 1) << (_fe - 32)) : 0) | \ + (((_ff > 31) && (_ff < 64)) ? (((A_UINT32) 1) << (_ff - 32)) : 0) | \ + (((_fg > 31) && (_fg < 64)) ? (((A_UINT32) 1) << (_fg - 32)) : 0) | \ + (((_fh > 31) && (_fh < 64)) ? (((A_UINT32) 1) << (_fh - 32)) : 0))} + + +/* + * THE following table is the mapping of regdomain pairs specified by + * a regdomain value to the individual unitary reg domains + */ + +typedef PREPACK struct reg_dmn_pair_mapping { + A_UINT16 regDmnEnum; /* 16 bit reg domain pair */ + A_UINT16 regDmn5GHz; /* 5GHz reg domain */ + A_UINT16 regDmn2GHz; /* 2GHz reg domain */ + A_UINT8 flags5GHz; /* Requirements flags (AdHoc disallow etc) */ + A_UINT8 flags2GHz; /* Requirements flags (AdHoc disallow etc) */ + A_UINT32 pscanMask; /* Passive Scan flags which can override unitary domain passive scan + flags. This value is used as a mask on the unitary flags*/ +} POSTPACK REG_DMN_PAIR_MAPPING; + +#define REGDB_YES 1 +#define REGDB_NO 0 + +typedef PREPACK struct { + A_UINT16 countryCode; + A_UINT16 regDmnEnum; + A_CHAR isoName[3]; + A_CHAR allow11g; +} POSTPACK COUNTRY_CODE_TO_ENUM_RD; + +typedef PREPACK struct RegDmnFreqBand { + A_UINT16 lowChannel; /* Low channel center in MHz */ + A_UINT16 highChannel; /* High Channel center in MHz */ + A_UINT8 power; /* Max power (dBm) for channel range */ + A_UINT8 channelSep; /* Channel separation within the band */ + A_UINT8 useDfs; /* Use DFS in the RegDomain if corresponding bit is set */ + A_UINT8 mode; /* Mode of operation */ + A_UINT32 usePassScan; /* Use Passive Scan in the RegDomain if corresponding bit is set */ +} POSTPACK REG_DMN_FREQ_BAND; + + + +typedef PREPACK struct regDomain { + A_UINT16 regDmnEnum; /* value from EnumRd table */ + A_UINT8 rdCTL; + A_UINT8 maxAntGain; + A_UINT8 dfsMask; /* DFS bitmask for 5Ghz tables */ + A_UINT8 flags; /* Requirement flags (AdHoc disallow etc) */ + A_UINT16 reserved; /* for alignment */ + A_UINT32 pscan; /* Bitmask for passive scan */ + A_UINT32 chan11a[BMLEN]; /* 64 bit bitmask for channel/band selection */ + A_UINT32 chan11bg[BMLEN];/* 64 bit bitmask for channel/band selection */ +} POSTPACK REG_DOMAIN; + +#endif /* __REG_DBSCHEMA_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/reg_dbvalues.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/reg_dbvalues.h --- linux-2.6.26/drivers/net/wireless/ath6k/reg_dbvalues.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/reg_dbvalues.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,476 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2005 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + + +#ifndef __REG_DBVALUE_H__ +#define __REG_DBVALUE_H__ + +/* + * Numbering from ISO 3166 + */ +enum CountryCode { + CTRY_ALBANIA = 8, /* Albania */ + CTRY_ALGERIA = 12, /* Algeria */ + CTRY_ARGENTINA = 32, /* Argentina */ + CTRY_ARMENIA = 51, /* Armenia */ + CTRY_AUSTRALIA = 36, /* Australia */ + CTRY_AUSTRIA = 40, /* Austria */ + CTRY_AZERBAIJAN = 31, /* Azerbaijan */ + CTRY_BAHRAIN = 48, /* Bahrain */ + CTRY_BELARUS = 112, /* Belarus */ + CTRY_BELGIUM = 56, /* Belgium */ + CTRY_BELIZE = 84, /* Belize */ + CTRY_BOLIVIA = 68, /* Bolivia */ + CTRY_BOSNIA_HERZEGOWANIA = 70, /* Bosnia & Herzegowania */ + CTRY_BRAZIL = 76, /* Brazil */ + CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */ + CTRY_BULGARIA = 100, /* Bulgaria */ + CTRY_CANADA = 124, /* Canada */ + CTRY_CHILE = 152, /* Chile */ + CTRY_CHINA = 156, /* People's Republic of China */ + CTRY_COLOMBIA = 170, /* Colombia */ + CTRY_COSTA_RICA = 188, /* Costa Rica */ + CTRY_CROATIA = 191, /* Croatia */ + CTRY_CYPRUS = 196, + CTRY_CZECH = 203, /* Czech Republic */ + CTRY_DENMARK = 208, /* Denmark */ + CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */ + CTRY_ECUADOR = 218, /* Ecuador */ + CTRY_EGYPT = 818, /* Egypt */ + CTRY_EL_SALVADOR = 222, /* El Salvador */ + CTRY_ESTONIA = 233, /* Estonia */ + CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */ + CTRY_FINLAND = 246, /* Finland */ + CTRY_FRANCE = 250, /* France */ + CTRY_FRANCE2 = 255, /* France2 */ + CTRY_GEORGIA = 268, /* Georgia */ + CTRY_GERMANY = 276, /* Germany */ + CTRY_GREECE = 300, /* Greece */ + CTRY_GUATEMALA = 320, /* Guatemala */ + CTRY_HONDURAS = 340, /* Honduras */ + CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */ + CTRY_HUNGARY = 348, /* Hungary */ + CTRY_ICELAND = 352, /* Iceland */ + CTRY_INDIA = 356, /* India */ + CTRY_INDONESIA = 360, /* Indonesia */ + CTRY_IRAN = 364, /* Iran */ + CTRY_IRAQ = 368, /* Iraq */ + CTRY_IRELAND = 372, /* Ireland */ + CTRY_ISRAEL = 376, /* Israel */ + CTRY_ITALY = 380, /* Italy */ + CTRY_JAMAICA = 388, /* Jamaica */ + CTRY_JAPAN = 392, /* Japan */ + CTRY_JAPAN1 = 393, /* Japan (JP1) */ + CTRY_JAPAN2 = 394, /* Japan (JP0) */ + CTRY_JAPAN3 = 395, /* Japan (JP1-1) */ + CTRY_JAPAN4 = 396, /* Japan (JE1) */ + CTRY_JAPAN5 = 397, /* Japan (JE2) */ + CTRY_JAPAN6 = 399, /* Japan (JP6) */ + CTRY_JORDAN = 400, /* Jordan */ + CTRY_KAZAKHSTAN = 398, /* Kazakhstan */ + CTRY_KENYA = 404, /* Kenya */ + CTRY_KOREA_NORTH = 408, /* North Korea */ + CTRY_KOREA_ROC = 410, /* South Korea */ + CTRY_KOREA_ROC2 = 411, /* South Korea */ + CTRY_KOREA_ROC3 = 412, /* South Korea */ + CTRY_KUWAIT = 414, /* Kuwait */ + CTRY_LATVIA = 428, /* Latvia */ + CTRY_LEBANON = 422, /* Lebanon */ + CTRY_LIBYA = 434, /* Libya */ + CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */ + CTRY_LITHUANIA = 440, /* Lithuania */ + CTRY_LUXEMBOURG = 442, /* Luxembourg */ + CTRY_MACAU = 446, /* Macau */ + CTRY_MACEDONIA = 807, /* the Former Yugoslav Republic of Macedonia */ + CTRY_MALAYSIA = 458, /* Malaysia */ + CTRY_MALTA = 470, /* Malta */ + CTRY_MEXICO = 484, /* Mexico */ + CTRY_MONACO = 492, /* Principality of Monaco */ + CTRY_MOROCCO = 504, /* Morocco */ + CTRY_NETHERLANDS = 528, /* Netherlands */ + CTRY_NETHERLAND_ANTILLES = 530, /* Netherlands-Antilles */ + CTRY_NEW_ZEALAND = 554, /* New Zealand */ + CTRY_NICARAGUA = 558, /* Nicaragua */ + CTRY_NORWAY = 578, /* Norway */ + CTRY_OMAN = 512, /* Oman */ + CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */ + CTRY_PANAMA = 591, /* Panama */ + CTRY_PARAGUAY = 600, /* Paraguay */ + CTRY_PERU = 604, /* Peru */ + CTRY_PHILIPPINES = 608, /* Republic of the Philippines */ + CTRY_POLAND = 616, /* Poland */ + CTRY_PORTUGAL = 620, /* Portugal */ + CTRY_PUERTO_RICO = 630, /* Puerto Rico */ + CTRY_QATAR = 634, /* Qatar */ + CTRY_ROMANIA = 642, /* Romania */ + CTRY_RUSSIA = 643, /* Russia */ + CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */ + CTRY_MONTENEGRO = 891, /* Montenegro */ + CTRY_SINGAPORE = 702, /* Singapore */ + CTRY_SLOVAKIA = 703, /* Slovak Republic */ + CTRY_SLOVENIA = 705, /* Slovenia */ + CTRY_SOUTH_AFRICA = 710, /* South Africa */ + CTRY_SPAIN = 724, /* Spain */ + CTRY_SRILANKA = 144, /* Sri Lanka */ + CTRY_SWEDEN = 752, /* Sweden */ + CTRY_SWITZERLAND = 756, /* Switzerland */ + CTRY_SYRIA = 760, /* Syria */ + CTRY_TAIWAN = 158, /* Taiwan */ + CTRY_THAILAND = 764, /* Thailand */ + CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */ + CTRY_TUNISIA = 788, /* Tunisia */ + CTRY_TURKEY = 792, /* Turkey */ + CTRY_UAE = 784, /* U.A.E. */ + CTRY_UKRAINE = 804, /* Ukraine */ + CTRY_UNITED_KINGDOM = 826, /* United Kingdom */ + CTRY_UNITED_STATES = 840, /* United States */ + CTRY_UNITED_STATES_PS = 842, /* United States - public safety */ + CTRY_URUGUAY = 858, /* Uruguay */ + CTRY_UZBEKISTAN = 860, /* Uzbekistan */ + CTRY_VENEZUELA = 862, /* Venezuela */ + CTRY_VIET_NAM = 704, /* Viet Nam */ + CTRY_YEMEN = 887, /* Yemen */ + CTRY_ZIMBABWE = 716 /* Zimbabwe */ +}; + +#define CTRY_DEBUG 0 +#define CTRY_DEFAULT 0x1ff + +/* + * The following regulatory domain definitions are + * found in the EEPROM. Each regulatory domain + * can operate in either a 5GHz or 2.4GHz wireless mode or + * both 5GHz and 2.4GHz wireless modes. + * In general, the value holds no special + * meaning and is used to decode into either specific + * 2.4GHz or 5GHz wireless mode for that particular + * regulatory domain. + * + * Enumerated Regulatory Domain Information 8 bit values indicate that + * the regdomain is really a pair of unitary regdomains. 12 bit values + * are the real unitary regdomains and are the only ones which have the + * frequency bitmasks and flags set. + */ + +enum EnumRd { + NO_ENUMRD = 0x00, + NULL1_WORLD = 0x03, /* For 11b-only countries (no 11a allowed) */ + NULL1_ETSIB = 0x07, /* Israel */ + NULL1_ETSIC = 0x08, + + FCC1_FCCA = 0x10, /* USA */ + FCC1_WORLD = 0x11, /* Hong Kong */ + FCC2_FCCA = 0x20, /* Canada */ + FCC2_WORLD = 0x21, /* Australia & HK */ + FCC2_ETSIC = 0x22, + FCC3_FCCA = 0x3A, /* USA & Canada w/5470 band, 11h, DFS enabled */ + FCC3_WORLD = 0x3B, /* USA & Canada w/5470 band, 11h, DFS enabled */ + FCC4_FCCA = 0x12, /* FCC public safety plus UNII bands */ + FCC5_FCCA = 0x13, /* US with no DFS */ + + ETSI1_WORLD = 0x37, + + ETSI2_WORLD = 0x35, /* Hungary & others */ + ETSI3_WORLD = 0x36, /* France & others */ + ETSI4_WORLD = 0x30, + ETSI4_ETSIC = 0x38, + ETSI5_WORLD = 0x39, + ETSI6_WORLD = 0x34, /* Bulgaria */ + ETSI_RESERVED = 0x33, /* Reserved (Do not used) */ + FRANCE_RES = 0x31, /* Legacy France for OEM */ + + APL6_WORLD = 0x5B, /* Singapore */ + APL4_WORLD = 0x42, /* Singapore */ + APL3_FCCA = 0x50, + APL_RESERVED = 0x44, /* Reserved (Do not used) */ + APL2_WORLD = 0x45, /* Korea */ + APL2_APLC = 0x46, + APL3_WORLD = 0x47, + APL2_APLD = 0x49, /* Korea with 2.3G channels */ + APL1_WORLD = 0x52, /* Latin America */ + APL1_FCCA = 0x53, + APL1_ETSIC = 0x55, + APL2_ETSIC = 0x56, /* Venezuela */ + APL5_WORLD = 0x58, /* Chile */ + APL7_FCCA = 0x5C, + APL8_WORLD = 0x5D, + APL9_WORLD = 0x5E, + + + MKK5_MKKA = 0x99, /* This is a temporary value. MG and DQ have to give official one */ + MKK5_FCCA = 0x9A, /* This is a temporary value. MG and DQ have to give official one */ + MKK5_MKKC = 0x88, + MKK11_MKKA = 0xD4, + MKK11_FCCA = 0xD5, + MKK11_MKKC = 0xD7, + + /* + * World mode SKUs + */ + WOR0_WORLD = 0x60, /* World0 (WO0 SKU) */ + WOR1_WORLD = 0x61, /* World1 (WO1 SKU) */ + WOR2_WORLD = 0x62, /* World2 (WO2 SKU) */ + WOR3_WORLD = 0x63, /* World3 (WO3 SKU) */ + WOR4_WORLD = 0x64, /* World4 (WO4 SKU) */ + WOR5_ETSIC = 0x65, /* World5 (WO5 SKU) */ + + WOR01_WORLD = 0x66, /* World0-1 (WW0-1 SKU) */ + WOR02_WORLD = 0x67, /* World0-2 (WW0-2 SKU) */ + EU1_WORLD = 0x68, /* Same as World0-2 (WW0-2 SKU), except active scan ch1-13. No ch14 */ + + WOR9_WORLD = 0x69, /* World9 (WO9 SKU) */ + WORA_WORLD = 0x6A, /* WorldA (WOA SKU) */ + + /* + * Regulator domains ending in a number (e.g. APL1, + * MK1, ETSI4, etc) apply to 5GHz channel and power + * information. Regulator domains ending in a letter + * (e.g. APLA, FCCA, etc) apply to 2.4GHz channel and + * power information. + */ + APL1 = 0x0150, /* LAT & Asia */ + APL2 = 0x0250, /* LAT & Asia */ + APL3 = 0x0350, /* Taiwan */ + APL4 = 0x0450, /* Jordan */ + APL5 = 0x0550, /* Chile */ + APL6 = 0x0650, /* Singapore */ + APL7 = 0x0750, /* Taiwan */ + APL8 = 0x0850, /* Malaysia */ + APL9 = 0x0950, /* Korea */ + + ETSI1 = 0x0130, /* Europe & others */ + ETSI2 = 0x0230, /* Europe & others */ + ETSI3 = 0x0330, /* Europe & others */ + ETSI4 = 0x0430, /* Europe & others */ + ETSI5 = 0x0530, /* Europe & others */ + ETSI6 = 0x0630, /* Europe & others */ + ETSIB = 0x0B30, /* Israel */ + ETSIC = 0x0C30, /* Latin America */ + + FCC1 = 0x0110, /* US & others */ + FCC2 = 0x0120, /* Canada, Australia & New Zealand */ + FCC3 = 0x0160, /* US w/new middle band & DFS */ + FCC5 = 0x0180, + FCCA = 0x0A10, + + APLD = 0x0D50, /* South Korea */ + + MKK1 = 0x0140, /* Japan */ + MKK2 = 0x0240, /* Japan Extended */ + MKK3 = 0x0340, /* Japan new 5GHz */ + MKK4 = 0x0440, /* Japan new 5GHz */ + MKK5 = 0x0540, /* Japan new 5GHz */ + MKK6 = 0x0640, /* Japan new 5GHz */ + MKK7 = 0x0740, /* Japan new 5GHz */ + MKK8 = 0x0840, /* Japan new 5GHz */ + MKK9 = 0x0940, /* Japan new 5GHz */ + MKK10 = 0x1040, /* Japan new 5GHz */ + MKK11 = 0x1140, /* Japan new 5GHz */ + MKK12 = 0x1240, /* Japan new 5GHz */ + + MKKA = 0x0A40, /* Japan */ + MKKC = 0x0A50, + + NULL1 = 0x0198, + WORLD = 0x0199, + DEBUG_REG_DMN = 0x01ff, + UNINIT_REG_DMN = 0x0fff, +}; + +enum { /* conformance test limits */ + FCC = 0x10, + MKK = 0x40, + ETSI = 0x30, + NO_CTL = 0xff, + CTL_11B = 1, + CTL_11G = 2 +}; + + +/* + * The following are flags for different requirements per reg domain. + * These requirements are either inhereted from the reg domain pair or + * from the unitary reg domain if the reg domain pair flags value is + * 0 + */ + +enum { + NO_REQ = 0x00, + DISALLOW_ADHOC_11A = 0x01, + ADHOC_PER_11D = 0x02, + ADHOC_NO_11A = 0x04, + DISALLOW_ADHOC_11G = 0x08 +}; + + + + +/* + * The following describe the bit masks for different passive scan + * capability/requirements per regdomain. + */ +#define NO_PSCAN 0x00000000 +#define PSCAN_FCC 0x00000001 +#define PSCAN_ETSI 0x00000002 +#define PSCAN_MKK 0x00000004 +#define PSCAN_ETSIB 0x00000008 +#define PSCAN_ETSIC 0x00000010 +#define PSCAN_WWR 0x00000020 +#define PSCAN_DEFER 0xFFFFFFFF + +/* Bit masks for DFS per regdomain */ + +enum { + NO_DFS = 0x00, + DFS_FCC3 = 0x01, + DFS_ETSI = 0x02, + DFS_MKK = 0x04 +}; + + +#define DEF_REGDMN FCC1_FCCA + +/* + * The following table is the master list for all different freqeuncy + * bands with the complete matrix of all possible flags and settings + * for each band if it is used in ANY reg domain. + * + * The table of frequency bands is indexed by a bitmask. The ordering + * must be consistent with the enum below. When adding a new + * frequency band, be sure to match the location in the enum with the + * comments + */ + +/* + * These frequency values are as per channel tags and regulatory domain + * info. Please update them as database is updated. + */ +#define A_FREQ_MIN 4920 +#define A_FREQ_MAX 5825 + +#define A_CHAN0_FREQ 5000 +#define A_CHAN_MAX ((A_FREQ_MAX - A_CHAN0_FREQ)/5) + +#define BG_FREQ_MIN 2412 +#define BG_FREQ_MAX 2484 + +#define BG_CHAN0_FREQ 2407 +#define BG_CHAN_MIN ((BG_FREQ_MIN - BG_CHAN0_FREQ)/5) +#define BG_CHAN_MAX 14 /* corresponding to 2484 MHz */ + +#define A_20MHZ_BAND_FREQ_MAX 5000 + + +/* + * 5GHz 11A channel tags + */ + +enum { + F1_4920_4980, + F1_5040_5080, + + F1_5120_5240, + + F1_5180_5240, + F2_5180_5240, + F3_5180_5240, + F4_5180_5240, + F5_5180_5240, + F6_5180_5240, + + F1_5260_5280, + + F1_5260_5320, + F2_5260_5320, + F3_5260_5320, + F4_5260_5320, + + F1_5260_5700, + + F1_5280_5320, + + F1_5500_5620, + + F1_5500_5700, + F2_5500_5700, + F3_5500_5700, + F4_5500_5700, + F5_5500_5700, + + F1_5745_5805, + F2_5745_5805, + + F1_5745_5825, + F2_5745_5825, + F3_5745_5825, + F4_5745_5825, + F5_5745_5825, + + W1_4920_4980, + W1_5040_5080, + W1_5170_5230, + W1_5180_5240, + W1_5260_5320, + W1_5745_5825, + W1_5500_5700, +}; + + +/* 2.4 GHz table - for 11b and 11g info */ +enum { + BG1_2312_2372, + BG2_2312_2372, + + BG1_2412_2472, + BG2_2412_2472, + BG3_2412_2472, + + BG1_2412_2462, + BG2_2412_2462, + + BG1_2432_2442, + + BG1_2457_2472, + + BG1_2467_2472, + + BG1_2484_2484, /* No G */ + BG2_2484_2484, /* No G */ + + BG1_2512_2732, + + WBG1_2312_2372, + WBG1_2412_2412, + WBG1_2417_2432, + WBG1_2437_2442, + WBG1_2447_2457, + WBG1_2462_2462, + WBG1_2467_2467, + WBG2_2467_2467, + WBG1_2472_2472, + WBG2_2472_2472, + WBG1_2484_2484, /* No G */ + WBG2_2484_2484 /* No G */ +}; + +#endif /* __REG_DBVALUE_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/regdump.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/regdump.h --- linux-2.6.26/drivers/net/wireless/ath6k/regdump.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/regdump.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,49 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __REGDUMP_H__ +#define __REGDUMP_H__ +#if defined(AR6001) +#include "AR6001/AR6001_regdump.h" +#endif +#if defined(AR6002) +#include "AR6002/AR6002_regdump.h" +#endif + +#if !defined(__ASSEMBLER__) +/* + * Target CPU state at the time of failure is reflected + * in a register dump, which the Host can fetch through + * the diagnostic window. + */ +struct register_dump_s { + A_UINT32 target_id; /* Target ID */ + A_UINT32 assline; /* Line number (if assertion failure) */ + A_UINT32 pc; /* Program Counter at time of exception */ + A_UINT32 badvaddr; /* Virtual address causing exception */ + CPU_exception_frame_t exc_frame; /* CPU-specific exception info */ + + /* Could copy top of stack here, too.... */ +}; +#endif /* __ASSEMBLER__ */ +#endif /* __REGDUMP_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/roaming.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/roaming.h --- linux-2.6.26/drivers/net/wireless/ath6k/roaming.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/roaming.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,41 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _ROAMING_H_ +#define _ROAMING_H_ + +/* + * The signal quality could be in terms of either snr or rssi. We should + * have an enum for both of them. For the time being, we are going to move + * it to wmi.h that is shared by both host and the target, since we are + * repartitioning the code to the host + */ +#define SIGNAL_QUALITY_NOISE_FLOOR -96 +#define SIGNAL_QUALITY_METRICS_NUM_MAX 2 +typedef enum { + SIGNAL_QUALITY_METRICS_SNR = 0, + SIGNAL_QUALITY_METRICS_RSSI, + SIGNAL_QUALITY_METRICS_ALL, +} SIGNAL_QUALITY_METRICS_TYPE; + +#endif /* _ROAMING_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/rtc_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/rtc_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k/rtc_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/rtc_reg.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,1186 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _RTC_REG_REG_H_ +#define _RTC_REG_REG_H_ + +#define RESET_CONTROL_ADDRESS 0x00000000 +#define RESET_CONTROL_OFFSET 0x00000000 +#define RESET_CONTROL_CPU_INIT_RESET_MSB 11 +#define RESET_CONTROL_CPU_INIT_RESET_LSB 11 +#define RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800 +#define RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & RESET_CONTROL_CPU_INIT_RESET_MASK) >> RESET_CONTROL_CPU_INIT_RESET_LSB) +#define RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << RESET_CONTROL_CPU_INIT_RESET_LSB) & RESET_CONTROL_CPU_INIT_RESET_MASK) +#define RESET_CONTROL_VMC_REMAP_RESET_MSB 10 +#define RESET_CONTROL_VMC_REMAP_RESET_LSB 10 +#define RESET_CONTROL_VMC_REMAP_RESET_MASK 0x00000400 +#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) (((x) & RESET_CONTROL_VMC_REMAP_RESET_MASK) >> RESET_CONTROL_VMC_REMAP_RESET_LSB) +#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) (((x) << RESET_CONTROL_VMC_REMAP_RESET_LSB) & RESET_CONTROL_VMC_REMAP_RESET_MASK) +#define RESET_CONTROL_RST_OUT_MSB 9 +#define RESET_CONTROL_RST_OUT_LSB 9 +#define RESET_CONTROL_RST_OUT_MASK 0x00000200 +#define RESET_CONTROL_RST_OUT_GET(x) (((x) & RESET_CONTROL_RST_OUT_MASK) >> RESET_CONTROL_RST_OUT_LSB) +#define RESET_CONTROL_RST_OUT_SET(x) (((x) << RESET_CONTROL_RST_OUT_LSB) & RESET_CONTROL_RST_OUT_MASK) +#define RESET_CONTROL_COLD_RST_MSB 8 +#define RESET_CONTROL_COLD_RST_LSB 8 +#define RESET_CONTROL_COLD_RST_MASK 0x00000100 +#define RESET_CONTROL_COLD_RST_GET(x) (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB) +#define RESET_CONTROL_COLD_RST_SET(x) (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK) +#define RESET_CONTROL_WARM_RST_MSB 7 +#define RESET_CONTROL_WARM_RST_LSB 7 +#define RESET_CONTROL_WARM_RST_MASK 0x00000080 +#define RESET_CONTROL_WARM_RST_GET(x) (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB) +#define RESET_CONTROL_WARM_RST_SET(x) (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK) +#define RESET_CONTROL_CPU_WARM_RST_MSB 6 +#define RESET_CONTROL_CPU_WARM_RST_LSB 6 +#define RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 +#define RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & RESET_CONTROL_CPU_WARM_RST_MASK) >> RESET_CONTROL_CPU_WARM_RST_LSB) +#define RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << RESET_CONTROL_CPU_WARM_RST_LSB) & RESET_CONTROL_CPU_WARM_RST_MASK) +#define RESET_CONTROL_MAC_COLD_RST_MSB 5 +#define RESET_CONTROL_MAC_COLD_RST_LSB 5 +#define RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020 +#define RESET_CONTROL_MAC_COLD_RST_GET(x) (((x) & RESET_CONTROL_MAC_COLD_RST_MASK) >> RESET_CONTROL_MAC_COLD_RST_LSB) +#define RESET_CONTROL_MAC_COLD_RST_SET(x) (((x) << RESET_CONTROL_MAC_COLD_RST_LSB) & RESET_CONTROL_MAC_COLD_RST_MASK) +#define RESET_CONTROL_MAC_WARM_RST_MSB 4 +#define RESET_CONTROL_MAC_WARM_RST_LSB 4 +#define RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010 +#define RESET_CONTROL_MAC_WARM_RST_GET(x) (((x) & RESET_CONTROL_MAC_WARM_RST_MASK) >> RESET_CONTROL_MAC_WARM_RST_LSB) +#define RESET_CONTROL_MAC_WARM_RST_SET(x) (((x) << RESET_CONTROL_MAC_WARM_RST_LSB) & RESET_CONTROL_MAC_WARM_RST_MASK) +#define RESET_CONTROL_MBOX_RST_MSB 2 +#define RESET_CONTROL_MBOX_RST_LSB 2 +#define RESET_CONTROL_MBOX_RST_MASK 0x00000004 +#define RESET_CONTROL_MBOX_RST_GET(x) (((x) & RESET_CONTROL_MBOX_RST_MASK) >> RESET_CONTROL_MBOX_RST_LSB) +#define RESET_CONTROL_MBOX_RST_SET(x) (((x) << RESET_CONTROL_MBOX_RST_LSB) & RESET_CONTROL_MBOX_RST_MASK) +#define RESET_CONTROL_UART_RST_MSB 1 +#define RESET_CONTROL_UART_RST_LSB 1 +#define RESET_CONTROL_UART_RST_MASK 0x00000002 +#define RESET_CONTROL_UART_RST_GET(x) (((x) & RESET_CONTROL_UART_RST_MASK) >> RESET_CONTROL_UART_RST_LSB) +#define RESET_CONTROL_UART_RST_SET(x) (((x) << RESET_CONTROL_UART_RST_LSB) & RESET_CONTROL_UART_RST_MASK) +#define RESET_CONTROL_SI0_RST_MSB 0 +#define RESET_CONTROL_SI0_RST_LSB 0 +#define RESET_CONTROL_SI0_RST_MASK 0x00000001 +#define RESET_CONTROL_SI0_RST_GET(x) (((x) & RESET_CONTROL_SI0_RST_MASK) >> RESET_CONTROL_SI0_RST_LSB) +#define RESET_CONTROL_SI0_RST_SET(x) (((x) << RESET_CONTROL_SI0_RST_LSB) & RESET_CONTROL_SI0_RST_MASK) + +#define XTAL_CONTROL_ADDRESS 0x00000004 +#define XTAL_CONTROL_OFFSET 0x00000004 +#define XTAL_CONTROL_TCXO_MSB 0 +#define XTAL_CONTROL_TCXO_LSB 0 +#define XTAL_CONTROL_TCXO_MASK 0x00000001 +#define XTAL_CONTROL_TCXO_GET(x) (((x) & XTAL_CONTROL_TCXO_MASK) >> XTAL_CONTROL_TCXO_LSB) +#define XTAL_CONTROL_TCXO_SET(x) (((x) << XTAL_CONTROL_TCXO_LSB) & XTAL_CONTROL_TCXO_MASK) + +#define TCXO_DETECT_ADDRESS 0x00000008 +#define TCXO_DETECT_OFFSET 0x00000008 +#define TCXO_DETECT_PRESENT_MSB 0 +#define TCXO_DETECT_PRESENT_LSB 0 +#define TCXO_DETECT_PRESENT_MASK 0x00000001 +#define TCXO_DETECT_PRESENT_GET(x) (((x) & TCXO_DETECT_PRESENT_MASK) >> TCXO_DETECT_PRESENT_LSB) +#define TCXO_DETECT_PRESENT_SET(x) (((x) << TCXO_DETECT_PRESENT_LSB) & TCXO_DETECT_PRESENT_MASK) + +#define XTAL_TEST_ADDRESS 0x0000000c +#define XTAL_TEST_OFFSET 0x0000000c +#define XTAL_TEST_NOTCXODET_MSB 0 +#define XTAL_TEST_NOTCXODET_LSB 0 +#define XTAL_TEST_NOTCXODET_MASK 0x00000001 +#define XTAL_TEST_NOTCXODET_GET(x) (((x) & XTAL_TEST_NOTCXODET_MASK) >> XTAL_TEST_NOTCXODET_LSB) +#define XTAL_TEST_NOTCXODET_SET(x) (((x) << XTAL_TEST_NOTCXODET_LSB) & XTAL_TEST_NOTCXODET_MASK) + +#define QUADRATURE_ADDRESS 0x00000010 +#define QUADRATURE_OFFSET 0x00000010 +#define QUADRATURE_ADC_MSB 5 +#define QUADRATURE_ADC_LSB 4 +#define QUADRATURE_ADC_MASK 0x00000030 +#define QUADRATURE_ADC_GET(x) (((x) & QUADRATURE_ADC_MASK) >> QUADRATURE_ADC_LSB) +#define QUADRATURE_ADC_SET(x) (((x) << QUADRATURE_ADC_LSB) & QUADRATURE_ADC_MASK) +#define QUADRATURE_SEL_MSB 2 +#define QUADRATURE_SEL_LSB 2 +#define QUADRATURE_SEL_MASK 0x00000004 +#define QUADRATURE_SEL_GET(x) (((x) & QUADRATURE_SEL_MASK) >> QUADRATURE_SEL_LSB) +#define QUADRATURE_SEL_SET(x) (((x) << QUADRATURE_SEL_LSB) & QUADRATURE_SEL_MASK) +#define QUADRATURE_DAC_MSB 1 +#define QUADRATURE_DAC_LSB 0 +#define QUADRATURE_DAC_MASK 0x00000003 +#define QUADRATURE_DAC_GET(x) (((x) & QUADRATURE_DAC_MASK) >> QUADRATURE_DAC_LSB) +#define QUADRATURE_DAC_SET(x) (((x) << QUADRATURE_DAC_LSB) & QUADRATURE_DAC_MASK) + +#define PLL_CONTROL_ADDRESS 0x00000014 +#define PLL_CONTROL_OFFSET 0x00000014 +#define PLL_CONTROL_DIG_TEST_CLK_MSB 20 +#define PLL_CONTROL_DIG_TEST_CLK_LSB 20 +#define PLL_CONTROL_DIG_TEST_CLK_MASK 0x00100000 +#define PLL_CONTROL_DIG_TEST_CLK_GET(x) (((x) & PLL_CONTROL_DIG_TEST_CLK_MASK) >> PLL_CONTROL_DIG_TEST_CLK_LSB) +#define PLL_CONTROL_DIG_TEST_CLK_SET(x) (((x) << PLL_CONTROL_DIG_TEST_CLK_LSB) & PLL_CONTROL_DIG_TEST_CLK_MASK) +#define PLL_CONTROL_MAC_OVERRIDE_MSB 19 +#define PLL_CONTROL_MAC_OVERRIDE_LSB 19 +#define PLL_CONTROL_MAC_OVERRIDE_MASK 0x00080000 +#define PLL_CONTROL_MAC_OVERRIDE_GET(x) (((x) & PLL_CONTROL_MAC_OVERRIDE_MASK) >> PLL_CONTROL_MAC_OVERRIDE_LSB) +#define PLL_CONTROL_MAC_OVERRIDE_SET(x) (((x) << PLL_CONTROL_MAC_OVERRIDE_LSB) & PLL_CONTROL_MAC_OVERRIDE_MASK) +#define PLL_CONTROL_NOPWD_MSB 18 +#define PLL_CONTROL_NOPWD_LSB 18 +#define PLL_CONTROL_NOPWD_MASK 0x00040000 +#define PLL_CONTROL_NOPWD_GET(x) (((x) & PLL_CONTROL_NOPWD_MASK) >> PLL_CONTROL_NOPWD_LSB) +#define PLL_CONTROL_NOPWD_SET(x) (((x) << PLL_CONTROL_NOPWD_LSB) & PLL_CONTROL_NOPWD_MASK) +#define PLL_CONTROL_UPDATING_MSB 17 +#define PLL_CONTROL_UPDATING_LSB 17 +#define PLL_CONTROL_UPDATING_MASK 0x00020000 +#define PLL_CONTROL_UPDATING_GET(x) (((x) & PLL_CONTROL_UPDATING_MASK) >> PLL_CONTROL_UPDATING_LSB) +#define PLL_CONTROL_UPDATING_SET(x) (((x) << PLL_CONTROL_UPDATING_LSB) & PLL_CONTROL_UPDATING_MASK) +#define PLL_CONTROL_BYPASS_MSB 16 +#define PLL_CONTROL_BYPASS_LSB 16 +#define PLL_CONTROL_BYPASS_MASK 0x00010000 +#define PLL_CONTROL_BYPASS_GET(x) (((x) & PLL_CONTROL_BYPASS_MASK) >> PLL_CONTROL_BYPASS_LSB) +#define PLL_CONTROL_BYPASS_SET(x) (((x) << PLL_CONTROL_BYPASS_LSB) & PLL_CONTROL_BYPASS_MASK) +#define PLL_CONTROL_REFDIV_MSB 15 +#define PLL_CONTROL_REFDIV_LSB 12 +#define PLL_CONTROL_REFDIV_MASK 0x0000f000 +#define PLL_CONTROL_REFDIV_GET(x) (((x) & PLL_CONTROL_REFDIV_MASK) >> PLL_CONTROL_REFDIV_LSB) +#define PLL_CONTROL_REFDIV_SET(x) (((x) << PLL_CONTROL_REFDIV_LSB) & PLL_CONTROL_REFDIV_MASK) +#define PLL_CONTROL_DIV_MSB 9 +#define PLL_CONTROL_DIV_LSB 0 +#define PLL_CONTROL_DIV_MASK 0x000003ff +#define PLL_CONTROL_DIV_GET(x) (((x) & PLL_CONTROL_DIV_MASK) >> PLL_CONTROL_DIV_LSB) +#define PLL_CONTROL_DIV_SET(x) (((x) << PLL_CONTROL_DIV_LSB) & PLL_CONTROL_DIV_MASK) + +#define PLL_SETTLE_ADDRESS 0x00000018 +#define PLL_SETTLE_OFFSET 0x00000018 +#define PLL_SETTLE_TIME_MSB 11 +#define PLL_SETTLE_TIME_LSB 0 +#define PLL_SETTLE_TIME_MASK 0x00000fff +#define PLL_SETTLE_TIME_GET(x) (((x) & PLL_SETTLE_TIME_MASK) >> PLL_SETTLE_TIME_LSB) +#define PLL_SETTLE_TIME_SET(x) (((x) << PLL_SETTLE_TIME_LSB) & PLL_SETTLE_TIME_MASK) + +#define XTAL_SETTLE_ADDRESS 0x0000001c +#define XTAL_SETTLE_OFFSET 0x0000001c +#define XTAL_SETTLE_TIME_MSB 7 +#define XTAL_SETTLE_TIME_LSB 0 +#define XTAL_SETTLE_TIME_MASK 0x000000ff +#define XTAL_SETTLE_TIME_GET(x) (((x) & XTAL_SETTLE_TIME_MASK) >> XTAL_SETTLE_TIME_LSB) +#define XTAL_SETTLE_TIME_SET(x) (((x) << XTAL_SETTLE_TIME_LSB) & XTAL_SETTLE_TIME_MASK) + +#define CPU_CLOCK_ADDRESS 0x00000020 +#define CPU_CLOCK_OFFSET 0x00000020 +#define CPU_CLOCK_STANDARD_MSB 1 +#define CPU_CLOCK_STANDARD_LSB 0 +#define CPU_CLOCK_STANDARD_MASK 0x00000003 +#define CPU_CLOCK_STANDARD_GET(x) (((x) & CPU_CLOCK_STANDARD_MASK) >> CPU_CLOCK_STANDARD_LSB) +#define CPU_CLOCK_STANDARD_SET(x) (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK) + +#define CLOCK_OUT_ADDRESS 0x00000024 +#define CLOCK_OUT_OFFSET 0x00000024 +#define CLOCK_OUT_SELECT_MSB 3 +#define CLOCK_OUT_SELECT_LSB 0 +#define CLOCK_OUT_SELECT_MASK 0x0000000f +#define CLOCK_OUT_SELECT_GET(x) (((x) & CLOCK_OUT_SELECT_MASK) >> CLOCK_OUT_SELECT_LSB) +#define CLOCK_OUT_SELECT_SET(x) (((x) << CLOCK_OUT_SELECT_LSB) & CLOCK_OUT_SELECT_MASK) + +#define CLOCK_CONTROL_ADDRESS 0x00000028 +#define CLOCK_CONTROL_OFFSET 0x00000028 +#define CLOCK_CONTROL_LF_CLK32_MSB 2 +#define CLOCK_CONTROL_LF_CLK32_LSB 2 +#define CLOCK_CONTROL_LF_CLK32_MASK 0x00000004 +#define CLOCK_CONTROL_LF_CLK32_GET(x) (((x) & CLOCK_CONTROL_LF_CLK32_MASK) >> CLOCK_CONTROL_LF_CLK32_LSB) +#define CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << CLOCK_CONTROL_LF_CLK32_LSB) & CLOCK_CONTROL_LF_CLK32_MASK) +#define CLOCK_CONTROL_UART_CLK_MSB 1 +#define CLOCK_CONTROL_UART_CLK_LSB 1 +#define CLOCK_CONTROL_UART_CLK_MASK 0x00000002 +#define CLOCK_CONTROL_UART_CLK_GET(x) (((x) & CLOCK_CONTROL_UART_CLK_MASK) >> CLOCK_CONTROL_UART_CLK_LSB) +#define CLOCK_CONTROL_UART_CLK_SET(x) (((x) << CLOCK_CONTROL_UART_CLK_LSB) & CLOCK_CONTROL_UART_CLK_MASK) +#define CLOCK_CONTROL_SI0_CLK_MSB 0 +#define CLOCK_CONTROL_SI0_CLK_LSB 0 +#define CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 +#define CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & CLOCK_CONTROL_SI0_CLK_MASK) >> CLOCK_CONTROL_SI0_CLK_LSB) +#define CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << CLOCK_CONTROL_SI0_CLK_LSB) & CLOCK_CONTROL_SI0_CLK_MASK) + +#define BIAS_OVERRIDE_ADDRESS 0x0000002c +#define BIAS_OVERRIDE_OFFSET 0x0000002c +#define BIAS_OVERRIDE_ON_MSB 0 +#define BIAS_OVERRIDE_ON_LSB 0 +#define BIAS_OVERRIDE_ON_MASK 0x00000001 +#define BIAS_OVERRIDE_ON_GET(x) (((x) & BIAS_OVERRIDE_ON_MASK) >> BIAS_OVERRIDE_ON_LSB) +#define BIAS_OVERRIDE_ON_SET(x) (((x) << BIAS_OVERRIDE_ON_LSB) & BIAS_OVERRIDE_ON_MASK) + +#define WDT_CONTROL_ADDRESS 0x00000030 +#define WDT_CONTROL_OFFSET 0x00000030 +#define WDT_CONTROL_ACTION_MSB 2 +#define WDT_CONTROL_ACTION_LSB 0 +#define WDT_CONTROL_ACTION_MASK 0x00000007 +#define WDT_CONTROL_ACTION_GET(x) (((x) & WDT_CONTROL_ACTION_MASK) >> WDT_CONTROL_ACTION_LSB) +#define WDT_CONTROL_ACTION_SET(x) (((x) << WDT_CONTROL_ACTION_LSB) & WDT_CONTROL_ACTION_MASK) + +#define WDT_STATUS_ADDRESS 0x00000034 +#define WDT_STATUS_OFFSET 0x00000034 +#define WDT_STATUS_INTERRUPT_MSB 0 +#define WDT_STATUS_INTERRUPT_LSB 0 +#define WDT_STATUS_INTERRUPT_MASK 0x00000001 +#define WDT_STATUS_INTERRUPT_GET(x) (((x) & WDT_STATUS_INTERRUPT_MASK) >> WDT_STATUS_INTERRUPT_LSB) +#define WDT_STATUS_INTERRUPT_SET(x) (((x) << WDT_STATUS_INTERRUPT_LSB) & WDT_STATUS_INTERRUPT_MASK) + +#define WDT_ADDRESS 0x00000038 +#define WDT_OFFSET 0x00000038 +#define WDT_TARGET_MSB 21 +#define WDT_TARGET_LSB 0 +#define WDT_TARGET_MASK 0x003fffff +#define WDT_TARGET_GET(x) (((x) & WDT_TARGET_MASK) >> WDT_TARGET_LSB) +#define WDT_TARGET_SET(x) (((x) << WDT_TARGET_LSB) & WDT_TARGET_MASK) + +#define WDT_COUNT_ADDRESS 0x0000003c +#define WDT_COUNT_OFFSET 0x0000003c +#define WDT_COUNT_VALUE_MSB 21 +#define WDT_COUNT_VALUE_LSB 0 +#define WDT_COUNT_VALUE_MASK 0x003fffff +#define WDT_COUNT_VALUE_GET(x) (((x) & WDT_COUNT_VALUE_MASK) >> WDT_COUNT_VALUE_LSB) +#define WDT_COUNT_VALUE_SET(x) (((x) << WDT_COUNT_VALUE_LSB) & WDT_COUNT_VALUE_MASK) + +#define WDT_RESET_ADDRESS 0x00000040 +#define WDT_RESET_OFFSET 0x00000040 +#define WDT_RESET_VALUE_MSB 0 +#define WDT_RESET_VALUE_LSB 0 +#define WDT_RESET_VALUE_MASK 0x00000001 +#define WDT_RESET_VALUE_GET(x) (((x) & WDT_RESET_VALUE_MASK) >> WDT_RESET_VALUE_LSB) +#define WDT_RESET_VALUE_SET(x) (((x) << WDT_RESET_VALUE_LSB) & WDT_RESET_VALUE_MASK) + +#define INT_STATUS_ADDRESS 0x00000044 +#define INT_STATUS_OFFSET 0x00000044 +#define INT_STATUS_RTC_POWER_MSB 14 +#define INT_STATUS_RTC_POWER_LSB 14 +#define INT_STATUS_RTC_POWER_MASK 0x00004000 +#define INT_STATUS_RTC_POWER_GET(x) (((x) & INT_STATUS_RTC_POWER_MASK) >> INT_STATUS_RTC_POWER_LSB) +#define INT_STATUS_RTC_POWER_SET(x) (((x) << INT_STATUS_RTC_POWER_LSB) & INT_STATUS_RTC_POWER_MASK) +#define INT_STATUS_MAC_MSB 13 +#define INT_STATUS_MAC_LSB 13 +#define INT_STATUS_MAC_MASK 0x00002000 +#define INT_STATUS_MAC_GET(x) (((x) & INT_STATUS_MAC_MASK) >> INT_STATUS_MAC_LSB) +#define INT_STATUS_MAC_SET(x) (((x) << INT_STATUS_MAC_LSB) & INT_STATUS_MAC_MASK) +#define INT_STATUS_MAILBOX_MSB 12 +#define INT_STATUS_MAILBOX_LSB 12 +#define INT_STATUS_MAILBOX_MASK 0x00001000 +#define INT_STATUS_MAILBOX_GET(x) (((x) & INT_STATUS_MAILBOX_MASK) >> INT_STATUS_MAILBOX_LSB) +#define INT_STATUS_MAILBOX_SET(x) (((x) << INT_STATUS_MAILBOX_LSB) & INT_STATUS_MAILBOX_MASK) +#define INT_STATUS_RTC_ALARM_MSB 11 +#define INT_STATUS_RTC_ALARM_LSB 11 +#define INT_STATUS_RTC_ALARM_MASK 0x00000800 +#define INT_STATUS_RTC_ALARM_GET(x) (((x) & INT_STATUS_RTC_ALARM_MASK) >> INT_STATUS_RTC_ALARM_LSB) +#define INT_STATUS_RTC_ALARM_SET(x) (((x) << INT_STATUS_RTC_ALARM_LSB) & INT_STATUS_RTC_ALARM_MASK) +#define INT_STATUS_HF_TIMER_MSB 10 +#define INT_STATUS_HF_TIMER_LSB 10 +#define INT_STATUS_HF_TIMER_MASK 0x00000400 +#define INT_STATUS_HF_TIMER_GET(x) (((x) & INT_STATUS_HF_TIMER_MASK) >> INT_STATUS_HF_TIMER_LSB) +#define INT_STATUS_HF_TIMER_SET(x) (((x) << INT_STATUS_HF_TIMER_LSB) & INT_STATUS_HF_TIMER_MASK) +#define INT_STATUS_LF_TIMER3_MSB 9 +#define INT_STATUS_LF_TIMER3_LSB 9 +#define INT_STATUS_LF_TIMER3_MASK 0x00000200 +#define INT_STATUS_LF_TIMER3_GET(x) (((x) & INT_STATUS_LF_TIMER3_MASK) >> INT_STATUS_LF_TIMER3_LSB) +#define INT_STATUS_LF_TIMER3_SET(x) (((x) << INT_STATUS_LF_TIMER3_LSB) & INT_STATUS_LF_TIMER3_MASK) +#define INT_STATUS_LF_TIMER2_MSB 8 +#define INT_STATUS_LF_TIMER2_LSB 8 +#define INT_STATUS_LF_TIMER2_MASK 0x00000100 +#define INT_STATUS_LF_TIMER2_GET(x) (((x) & INT_STATUS_LF_TIMER2_MASK) >> INT_STATUS_LF_TIMER2_LSB) +#define INT_STATUS_LF_TIMER2_SET(x) (((x) << INT_STATUS_LF_TIMER2_LSB) & INT_STATUS_LF_TIMER2_MASK) +#define INT_STATUS_LF_TIMER1_MSB 7 +#define INT_STATUS_LF_TIMER1_LSB 7 +#define INT_STATUS_LF_TIMER1_MASK 0x00000080 +#define INT_STATUS_LF_TIMER1_GET(x) (((x) & INT_STATUS_LF_TIMER1_MASK) >> INT_STATUS_LF_TIMER1_LSB) +#define INT_STATUS_LF_TIMER1_SET(x) (((x) << INT_STATUS_LF_TIMER1_LSB) & INT_STATUS_LF_TIMER1_MASK) +#define INT_STATUS_LF_TIMER0_MSB 6 +#define INT_STATUS_LF_TIMER0_LSB 6 +#define INT_STATUS_LF_TIMER0_MASK 0x00000040 +#define INT_STATUS_LF_TIMER0_GET(x) (((x) & INT_STATUS_LF_TIMER0_MASK) >> INT_STATUS_LF_TIMER0_LSB) +#define INT_STATUS_LF_TIMER0_SET(x) (((x) << INT_STATUS_LF_TIMER0_LSB) & INT_STATUS_LF_TIMER0_MASK) +#define INT_STATUS_KEYPAD_MSB 5 +#define INT_STATUS_KEYPAD_LSB 5 +#define INT_STATUS_KEYPAD_MASK 0x00000020 +#define INT_STATUS_KEYPAD_GET(x) (((x) & INT_STATUS_KEYPAD_MASK) >> INT_STATUS_KEYPAD_LSB) +#define INT_STATUS_KEYPAD_SET(x) (((x) << INT_STATUS_KEYPAD_LSB) & INT_STATUS_KEYPAD_MASK) +#define INT_STATUS_SI_MSB 4 +#define INT_STATUS_SI_LSB 4 +#define INT_STATUS_SI_MASK 0x00000010 +#define INT_STATUS_SI_GET(x) (((x) & INT_STATUS_SI_MASK) >> INT_STATUS_SI_LSB) +#define INT_STATUS_SI_SET(x) (((x) << INT_STATUS_SI_LSB) & INT_STATUS_SI_MASK) +#define INT_STATUS_GPIO_MSB 3 +#define INT_STATUS_GPIO_LSB 3 +#define INT_STATUS_GPIO_MASK 0x00000008 +#define INT_STATUS_GPIO_GET(x) (((x) & INT_STATUS_GPIO_MASK) >> INT_STATUS_GPIO_LSB) +#define INT_STATUS_GPIO_SET(x) (((x) << INT_STATUS_GPIO_LSB) & INT_STATUS_GPIO_MASK) +#define INT_STATUS_UART_MSB 2 +#define INT_STATUS_UART_LSB 2 +#define INT_STATUS_UART_MASK 0x00000004 +#define INT_STATUS_UART_GET(x) (((x) & INT_STATUS_UART_MASK) >> INT_STATUS_UART_LSB) +#define INT_STATUS_UART_SET(x) (((x) << INT_STATUS_UART_LSB) & INT_STATUS_UART_MASK) +#define INT_STATUS_ERROR_MSB 1 +#define INT_STATUS_ERROR_LSB 1 +#define INT_STATUS_ERROR_MASK 0x00000002 +#define INT_STATUS_ERROR_GET(x) (((x) & INT_STATUS_ERROR_MASK) >> INT_STATUS_ERROR_LSB) +#define INT_STATUS_ERROR_SET(x) (((x) << INT_STATUS_ERROR_LSB) & INT_STATUS_ERROR_MASK) +#define INT_STATUS_WDT_INT_MSB 0 +#define INT_STATUS_WDT_INT_LSB 0 +#define INT_STATUS_WDT_INT_MASK 0x00000001 +#define INT_STATUS_WDT_INT_GET(x) (((x) & INT_STATUS_WDT_INT_MASK) >> INT_STATUS_WDT_INT_LSB) +#define INT_STATUS_WDT_INT_SET(x) (((x) << INT_STATUS_WDT_INT_LSB) & INT_STATUS_WDT_INT_MASK) + +#define LF_TIMER0_ADDRESS 0x00000048 +#define LF_TIMER0_OFFSET 0x00000048 +#define LF_TIMER0_TARGET_MSB 31 +#define LF_TIMER0_TARGET_LSB 0 +#define LF_TIMER0_TARGET_MASK 0xffffffff +#define LF_TIMER0_TARGET_GET(x) (((x) & LF_TIMER0_TARGET_MASK) >> LF_TIMER0_TARGET_LSB) +#define LF_TIMER0_TARGET_SET(x) (((x) << LF_TIMER0_TARGET_LSB) & LF_TIMER0_TARGET_MASK) + +#define LF_TIMER_COUNT0_ADDRESS 0x0000004c +#define LF_TIMER_COUNT0_OFFSET 0x0000004c +#define LF_TIMER_COUNT0_VALUE_MSB 31 +#define LF_TIMER_COUNT0_VALUE_LSB 0 +#define LF_TIMER_COUNT0_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT0_VALUE_GET(x) (((x) & LF_TIMER_COUNT0_VALUE_MASK) >> LF_TIMER_COUNT0_VALUE_LSB) +#define LF_TIMER_COUNT0_VALUE_SET(x) (((x) << LF_TIMER_COUNT0_VALUE_LSB) & LF_TIMER_COUNT0_VALUE_MASK) + +#define LF_TIMER_CONTROL0_ADDRESS 0x00000050 +#define LF_TIMER_CONTROL0_OFFSET 0x00000050 +#define LF_TIMER_CONTROL0_ENABLE_MSB 2 +#define LF_TIMER_CONTROL0_ENABLE_LSB 2 +#define LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL0_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL0_ENABLE_MASK) >> LF_TIMER_CONTROL0_ENABLE_LSB) +#define LF_TIMER_CONTROL0_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL0_ENABLE_LSB) & LF_TIMER_CONTROL0_ENABLE_MASK) +#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL0_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL0_RESET_MSB 0 +#define LF_TIMER_CONTROL0_RESET_LSB 0 +#define LF_TIMER_CONTROL0_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL0_RESET_GET(x) (((x) & LF_TIMER_CONTROL0_RESET_MASK) >> LF_TIMER_CONTROL0_RESET_LSB) +#define LF_TIMER_CONTROL0_RESET_SET(x) (((x) << LF_TIMER_CONTROL0_RESET_LSB) & LF_TIMER_CONTROL0_RESET_MASK) + +#define LF_TIMER_STATUS0_ADDRESS 0x00000054 +#define LF_TIMER_STATUS0_OFFSET 0x00000054 +#define LF_TIMER_STATUS0_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS0_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS0_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS0_INTERRUPT_MASK) >> LF_TIMER_STATUS0_INTERRUPT_LSB) +#define LF_TIMER_STATUS0_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS0_INTERRUPT_LSB) & LF_TIMER_STATUS0_INTERRUPT_MASK) + +#define LF_TIMER1_ADDRESS 0x00000058 +#define LF_TIMER1_OFFSET 0x00000058 +#define LF_TIMER1_TARGET_MSB 31 +#define LF_TIMER1_TARGET_LSB 0 +#define LF_TIMER1_TARGET_MASK 0xffffffff +#define LF_TIMER1_TARGET_GET(x) (((x) & LF_TIMER1_TARGET_MASK) >> LF_TIMER1_TARGET_LSB) +#define LF_TIMER1_TARGET_SET(x) (((x) << LF_TIMER1_TARGET_LSB) & LF_TIMER1_TARGET_MASK) + +#define LF_TIMER_COUNT1_ADDRESS 0x0000005c +#define LF_TIMER_COUNT1_OFFSET 0x0000005c +#define LF_TIMER_COUNT1_VALUE_MSB 31 +#define LF_TIMER_COUNT1_VALUE_LSB 0 +#define LF_TIMER_COUNT1_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT1_VALUE_GET(x) (((x) & LF_TIMER_COUNT1_VALUE_MASK) >> LF_TIMER_COUNT1_VALUE_LSB) +#define LF_TIMER_COUNT1_VALUE_SET(x) (((x) << LF_TIMER_COUNT1_VALUE_LSB) & LF_TIMER_COUNT1_VALUE_MASK) + +#define LF_TIMER_CONTROL1_ADDRESS 0x00000060 +#define LF_TIMER_CONTROL1_OFFSET 0x00000060 +#define LF_TIMER_CONTROL1_ENABLE_MSB 2 +#define LF_TIMER_CONTROL1_ENABLE_LSB 2 +#define LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL1_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL1_ENABLE_MASK) >> LF_TIMER_CONTROL1_ENABLE_LSB) +#define LF_TIMER_CONTROL1_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL1_ENABLE_LSB) & LF_TIMER_CONTROL1_ENABLE_MASK) +#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL1_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL1_RESET_MSB 0 +#define LF_TIMER_CONTROL1_RESET_LSB 0 +#define LF_TIMER_CONTROL1_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL1_RESET_GET(x) (((x) & LF_TIMER_CONTROL1_RESET_MASK) >> LF_TIMER_CONTROL1_RESET_LSB) +#define LF_TIMER_CONTROL1_RESET_SET(x) (((x) << LF_TIMER_CONTROL1_RESET_LSB) & LF_TIMER_CONTROL1_RESET_MASK) + +#define LF_TIMER_STATUS1_ADDRESS 0x00000064 +#define LF_TIMER_STATUS1_OFFSET 0x00000064 +#define LF_TIMER_STATUS1_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS1_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS1_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS1_INTERRUPT_MASK) >> LF_TIMER_STATUS1_INTERRUPT_LSB) +#define LF_TIMER_STATUS1_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS1_INTERRUPT_LSB) & LF_TIMER_STATUS1_INTERRUPT_MASK) + +#define LF_TIMER2_ADDRESS 0x00000068 +#define LF_TIMER2_OFFSET 0x00000068 +#define LF_TIMER2_TARGET_MSB 31 +#define LF_TIMER2_TARGET_LSB 0 +#define LF_TIMER2_TARGET_MASK 0xffffffff +#define LF_TIMER2_TARGET_GET(x) (((x) & LF_TIMER2_TARGET_MASK) >> LF_TIMER2_TARGET_LSB) +#define LF_TIMER2_TARGET_SET(x) (((x) << LF_TIMER2_TARGET_LSB) & LF_TIMER2_TARGET_MASK) + +#define LF_TIMER_COUNT2_ADDRESS 0x0000006c +#define LF_TIMER_COUNT2_OFFSET 0x0000006c +#define LF_TIMER_COUNT2_VALUE_MSB 31 +#define LF_TIMER_COUNT2_VALUE_LSB 0 +#define LF_TIMER_COUNT2_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT2_VALUE_GET(x) (((x) & LF_TIMER_COUNT2_VALUE_MASK) >> LF_TIMER_COUNT2_VALUE_LSB) +#define LF_TIMER_COUNT2_VALUE_SET(x) (((x) << LF_TIMER_COUNT2_VALUE_LSB) & LF_TIMER_COUNT2_VALUE_MASK) + +#define LF_TIMER_CONTROL2_ADDRESS 0x00000070 +#define LF_TIMER_CONTROL2_OFFSET 0x00000070 +#define LF_TIMER_CONTROL2_ENABLE_MSB 2 +#define LF_TIMER_CONTROL2_ENABLE_LSB 2 +#define LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL2_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL2_ENABLE_MASK) >> LF_TIMER_CONTROL2_ENABLE_LSB) +#define LF_TIMER_CONTROL2_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL2_ENABLE_LSB) & LF_TIMER_CONTROL2_ENABLE_MASK) +#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL2_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL2_RESET_MSB 0 +#define LF_TIMER_CONTROL2_RESET_LSB 0 +#define LF_TIMER_CONTROL2_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL2_RESET_GET(x) (((x) & LF_TIMER_CONTROL2_RESET_MASK) >> LF_TIMER_CONTROL2_RESET_LSB) +#define LF_TIMER_CONTROL2_RESET_SET(x) (((x) << LF_TIMER_CONTROL2_RESET_LSB) & LF_TIMER_CONTROL2_RESET_MASK) + +#define LF_TIMER_STATUS2_ADDRESS 0x00000074 +#define LF_TIMER_STATUS2_OFFSET 0x00000074 +#define LF_TIMER_STATUS2_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS2_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS2_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS2_INTERRUPT_MASK) >> LF_TIMER_STATUS2_INTERRUPT_LSB) +#define LF_TIMER_STATUS2_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS2_INTERRUPT_LSB) & LF_TIMER_STATUS2_INTERRUPT_MASK) + +#define LF_TIMER3_ADDRESS 0x00000078 +#define LF_TIMER3_OFFSET 0x00000078 +#define LF_TIMER3_TARGET_MSB 31 +#define LF_TIMER3_TARGET_LSB 0 +#define LF_TIMER3_TARGET_MASK 0xffffffff +#define LF_TIMER3_TARGET_GET(x) (((x) & LF_TIMER3_TARGET_MASK) >> LF_TIMER3_TARGET_LSB) +#define LF_TIMER3_TARGET_SET(x) (((x) << LF_TIMER3_TARGET_LSB) & LF_TIMER3_TARGET_MASK) + +#define LF_TIMER_COUNT3_ADDRESS 0x0000007c +#define LF_TIMER_COUNT3_OFFSET 0x0000007c +#define LF_TIMER_COUNT3_VALUE_MSB 31 +#define LF_TIMER_COUNT3_VALUE_LSB 0 +#define LF_TIMER_COUNT3_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT3_VALUE_GET(x) (((x) & LF_TIMER_COUNT3_VALUE_MASK) >> LF_TIMER_COUNT3_VALUE_LSB) +#define LF_TIMER_COUNT3_VALUE_SET(x) (((x) << LF_TIMER_COUNT3_VALUE_LSB) & LF_TIMER_COUNT3_VALUE_MASK) + +#define LF_TIMER_CONTROL3_ADDRESS 0x00000080 +#define LF_TIMER_CONTROL3_OFFSET 0x00000080 +#define LF_TIMER_CONTROL3_ENABLE_MSB 2 +#define LF_TIMER_CONTROL3_ENABLE_LSB 2 +#define LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL3_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL3_ENABLE_MASK) >> LF_TIMER_CONTROL3_ENABLE_LSB) +#define LF_TIMER_CONTROL3_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL3_ENABLE_LSB) & LF_TIMER_CONTROL3_ENABLE_MASK) +#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL3_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL3_RESET_MSB 0 +#define LF_TIMER_CONTROL3_RESET_LSB 0 +#define LF_TIMER_CONTROL3_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL3_RESET_GET(x) (((x) & LF_TIMER_CONTROL3_RESET_MASK) >> LF_TIMER_CONTROL3_RESET_LSB) +#define LF_TIMER_CONTROL3_RESET_SET(x) (((x) << LF_TIMER_CONTROL3_RESET_LSB) & LF_TIMER_CONTROL3_RESET_MASK) + +#define LF_TIMER_STATUS3_ADDRESS 0x00000084 +#define LF_TIMER_STATUS3_OFFSET 0x00000084 +#define LF_TIMER_STATUS3_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS3_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS3_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS3_INTERRUPT_MASK) >> LF_TIMER_STATUS3_INTERRUPT_LSB) +#define LF_TIMER_STATUS3_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS3_INTERRUPT_LSB) & LF_TIMER_STATUS3_INTERRUPT_MASK) + +#define HF_TIMER_ADDRESS 0x00000088 +#define HF_TIMER_OFFSET 0x00000088 +#define HF_TIMER_TARGET_MSB 31 +#define HF_TIMER_TARGET_LSB 12 +#define HF_TIMER_TARGET_MASK 0xfffff000 +#define HF_TIMER_TARGET_GET(x) (((x) & HF_TIMER_TARGET_MASK) >> HF_TIMER_TARGET_LSB) +#define HF_TIMER_TARGET_SET(x) (((x) << HF_TIMER_TARGET_LSB) & HF_TIMER_TARGET_MASK) + +#define HF_TIMER_COUNT_ADDRESS 0x0000008c +#define HF_TIMER_COUNT_OFFSET 0x0000008c +#define HF_TIMER_COUNT_VALUE_MSB 31 +#define HF_TIMER_COUNT_VALUE_LSB 12 +#define HF_TIMER_COUNT_VALUE_MASK 0xfffff000 +#define HF_TIMER_COUNT_VALUE_GET(x) (((x) & HF_TIMER_COUNT_VALUE_MASK) >> HF_TIMER_COUNT_VALUE_LSB) +#define HF_TIMER_COUNT_VALUE_SET(x) (((x) << HF_TIMER_COUNT_VALUE_LSB) & HF_TIMER_COUNT_VALUE_MASK) + +#define HF_LF_COUNT_ADDRESS 0x00000090 +#define HF_LF_COUNT_OFFSET 0x00000090 +#define HF_LF_COUNT_VALUE_MSB 31 +#define HF_LF_COUNT_VALUE_LSB 0 +#define HF_LF_COUNT_VALUE_MASK 0xffffffff +#define HF_LF_COUNT_VALUE_GET(x) (((x) & HF_LF_COUNT_VALUE_MASK) >> HF_LF_COUNT_VALUE_LSB) +#define HF_LF_COUNT_VALUE_SET(x) (((x) << HF_LF_COUNT_VALUE_LSB) & HF_LF_COUNT_VALUE_MASK) + +#define HF_TIMER_CONTROL_ADDRESS 0x00000094 +#define HF_TIMER_CONTROL_OFFSET 0x00000094 +#define HF_TIMER_CONTROL_ENABLE_MSB 3 +#define HF_TIMER_CONTROL_ENABLE_LSB 3 +#define HF_TIMER_CONTROL_ENABLE_MASK 0x00000008 +#define HF_TIMER_CONTROL_ENABLE_GET(x) (((x) & HF_TIMER_CONTROL_ENABLE_MASK) >> HF_TIMER_CONTROL_ENABLE_LSB) +#define HF_TIMER_CONTROL_ENABLE_SET(x) (((x) << HF_TIMER_CONTROL_ENABLE_LSB) & HF_TIMER_CONTROL_ENABLE_MASK) +#define HF_TIMER_CONTROL_ON_MSB 2 +#define HF_TIMER_CONTROL_ON_LSB 2 +#define HF_TIMER_CONTROL_ON_MASK 0x00000004 +#define HF_TIMER_CONTROL_ON_GET(x) (((x) & HF_TIMER_CONTROL_ON_MASK) >> HF_TIMER_CONTROL_ON_LSB) +#define HF_TIMER_CONTROL_ON_SET(x) (((x) << HF_TIMER_CONTROL_ON_LSB) & HF_TIMER_CONTROL_ON_MASK) +#define HF_TIMER_CONTROL_AUTO_RESTART_MSB 1 +#define HF_TIMER_CONTROL_AUTO_RESTART_LSB 1 +#define HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002 +#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> HF_TIMER_CONTROL_AUTO_RESTART_LSB) +#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << HF_TIMER_CONTROL_AUTO_RESTART_LSB) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) +#define HF_TIMER_CONTROL_RESET_MSB 0 +#define HF_TIMER_CONTROL_RESET_LSB 0 +#define HF_TIMER_CONTROL_RESET_MASK 0x00000001 +#define HF_TIMER_CONTROL_RESET_GET(x) (((x) & HF_TIMER_CONTROL_RESET_MASK) >> HF_TIMER_CONTROL_RESET_LSB) +#define HF_TIMER_CONTROL_RESET_SET(x) (((x) << HF_TIMER_CONTROL_RESET_LSB) & HF_TIMER_CONTROL_RESET_MASK) + +#define HF_TIMER_STATUS_ADDRESS 0x00000098 +#define HF_TIMER_STATUS_OFFSET 0x00000098 +#define HF_TIMER_STATUS_INTERRUPT_MSB 0 +#define HF_TIMER_STATUS_INTERRUPT_LSB 0 +#define HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001 +#define HF_TIMER_STATUS_INTERRUPT_GET(x) (((x) & HF_TIMER_STATUS_INTERRUPT_MASK) >> HF_TIMER_STATUS_INTERRUPT_LSB) +#define HF_TIMER_STATUS_INTERRUPT_SET(x) (((x) << HF_TIMER_STATUS_INTERRUPT_LSB) & HF_TIMER_STATUS_INTERRUPT_MASK) + +#define RTC_CONTROL_ADDRESS 0x0000009c +#define RTC_CONTROL_OFFSET 0x0000009c +#define RTC_CONTROL_ENABLE_MSB 2 +#define RTC_CONTROL_ENABLE_LSB 2 +#define RTC_CONTROL_ENABLE_MASK 0x00000004 +#define RTC_CONTROL_ENABLE_GET(x) (((x) & RTC_CONTROL_ENABLE_MASK) >> RTC_CONTROL_ENABLE_LSB) +#define RTC_CONTROL_ENABLE_SET(x) (((x) << RTC_CONTROL_ENABLE_LSB) & RTC_CONTROL_ENABLE_MASK) +#define RTC_CONTROL_LOAD_RTC_MSB 1 +#define RTC_CONTROL_LOAD_RTC_LSB 1 +#define RTC_CONTROL_LOAD_RTC_MASK 0x00000002 +#define RTC_CONTROL_LOAD_RTC_GET(x) (((x) & RTC_CONTROL_LOAD_RTC_MASK) >> RTC_CONTROL_LOAD_RTC_LSB) +#define RTC_CONTROL_LOAD_RTC_SET(x) (((x) << RTC_CONTROL_LOAD_RTC_LSB) & RTC_CONTROL_LOAD_RTC_MASK) +#define RTC_CONTROL_LOAD_ALARM_MSB 0 +#define RTC_CONTROL_LOAD_ALARM_LSB 0 +#define RTC_CONTROL_LOAD_ALARM_MASK 0x00000001 +#define RTC_CONTROL_LOAD_ALARM_GET(x) (((x) & RTC_CONTROL_LOAD_ALARM_MASK) >> RTC_CONTROL_LOAD_ALARM_LSB) +#define RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << RTC_CONTROL_LOAD_ALARM_LSB) & RTC_CONTROL_LOAD_ALARM_MASK) + +#define RTC_TIME_ADDRESS 0x000000a0 +#define RTC_TIME_OFFSET 0x000000a0 +#define RTC_TIME_WEEK_DAY_MSB 26 +#define RTC_TIME_WEEK_DAY_LSB 24 +#define RTC_TIME_WEEK_DAY_MASK 0x07000000 +#define RTC_TIME_WEEK_DAY_GET(x) (((x) & RTC_TIME_WEEK_DAY_MASK) >> RTC_TIME_WEEK_DAY_LSB) +#define RTC_TIME_WEEK_DAY_SET(x) (((x) << RTC_TIME_WEEK_DAY_LSB) & RTC_TIME_WEEK_DAY_MASK) +#define RTC_TIME_HOUR_MSB 21 +#define RTC_TIME_HOUR_LSB 16 +#define RTC_TIME_HOUR_MASK 0x003f0000 +#define RTC_TIME_HOUR_GET(x) (((x) & RTC_TIME_HOUR_MASK) >> RTC_TIME_HOUR_LSB) +#define RTC_TIME_HOUR_SET(x) (((x) << RTC_TIME_HOUR_LSB) & RTC_TIME_HOUR_MASK) +#define RTC_TIME_MINUTE_MSB 14 +#define RTC_TIME_MINUTE_LSB 8 +#define RTC_TIME_MINUTE_MASK 0x00007f00 +#define RTC_TIME_MINUTE_GET(x) (((x) & RTC_TIME_MINUTE_MASK) >> RTC_TIME_MINUTE_LSB) +#define RTC_TIME_MINUTE_SET(x) (((x) << RTC_TIME_MINUTE_LSB) & RTC_TIME_MINUTE_MASK) +#define RTC_TIME_SECOND_MSB 6 +#define RTC_TIME_SECOND_LSB 0 +#define RTC_TIME_SECOND_MASK 0x0000007f +#define RTC_TIME_SECOND_GET(x) (((x) & RTC_TIME_SECOND_MASK) >> RTC_TIME_SECOND_LSB) +#define RTC_TIME_SECOND_SET(x) (((x) << RTC_TIME_SECOND_LSB) & RTC_TIME_SECOND_MASK) + +#define RTC_DATE_ADDRESS 0x000000a4 +#define RTC_DATE_OFFSET 0x000000a4 +#define RTC_DATE_YEAR_MSB 23 +#define RTC_DATE_YEAR_LSB 16 +#define RTC_DATE_YEAR_MASK 0x00ff0000 +#define RTC_DATE_YEAR_GET(x) (((x) & RTC_DATE_YEAR_MASK) >> RTC_DATE_YEAR_LSB) +#define RTC_DATE_YEAR_SET(x) (((x) << RTC_DATE_YEAR_LSB) & RTC_DATE_YEAR_MASK) +#define RTC_DATE_MONTH_MSB 12 +#define RTC_DATE_MONTH_LSB 8 +#define RTC_DATE_MONTH_MASK 0x00001f00 +#define RTC_DATE_MONTH_GET(x) (((x) & RTC_DATE_MONTH_MASK) >> RTC_DATE_MONTH_LSB) +#define RTC_DATE_MONTH_SET(x) (((x) << RTC_DATE_MONTH_LSB) & RTC_DATE_MONTH_MASK) +#define RTC_DATE_MONTH_DAY_MSB 5 +#define RTC_DATE_MONTH_DAY_LSB 0 +#define RTC_DATE_MONTH_DAY_MASK 0x0000003f +#define RTC_DATE_MONTH_DAY_GET(x) (((x) & RTC_DATE_MONTH_DAY_MASK) >> RTC_DATE_MONTH_DAY_LSB) +#define RTC_DATE_MONTH_DAY_SET(x) (((x) << RTC_DATE_MONTH_DAY_LSB) & RTC_DATE_MONTH_DAY_MASK) + +#define RTC_SET_TIME_ADDRESS 0x000000a8 +#define RTC_SET_TIME_OFFSET 0x000000a8 +#define RTC_SET_TIME_WEEK_DAY_MSB 26 +#define RTC_SET_TIME_WEEK_DAY_LSB 24 +#define RTC_SET_TIME_WEEK_DAY_MASK 0x07000000 +#define RTC_SET_TIME_WEEK_DAY_GET(x) (((x) & RTC_SET_TIME_WEEK_DAY_MASK) >> RTC_SET_TIME_WEEK_DAY_LSB) +#define RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << RTC_SET_TIME_WEEK_DAY_LSB) & RTC_SET_TIME_WEEK_DAY_MASK) +#define RTC_SET_TIME_HOUR_MSB 21 +#define RTC_SET_TIME_HOUR_LSB 16 +#define RTC_SET_TIME_HOUR_MASK 0x003f0000 +#define RTC_SET_TIME_HOUR_GET(x) (((x) & RTC_SET_TIME_HOUR_MASK) >> RTC_SET_TIME_HOUR_LSB) +#define RTC_SET_TIME_HOUR_SET(x) (((x) << RTC_SET_TIME_HOUR_LSB) & RTC_SET_TIME_HOUR_MASK) +#define RTC_SET_TIME_MINUTE_MSB 14 +#define RTC_SET_TIME_MINUTE_LSB 8 +#define RTC_SET_TIME_MINUTE_MASK 0x00007f00 +#define RTC_SET_TIME_MINUTE_GET(x) (((x) & RTC_SET_TIME_MINUTE_MASK) >> RTC_SET_TIME_MINUTE_LSB) +#define RTC_SET_TIME_MINUTE_SET(x) (((x) << RTC_SET_TIME_MINUTE_LSB) & RTC_SET_TIME_MINUTE_MASK) +#define RTC_SET_TIME_SECOND_MSB 6 +#define RTC_SET_TIME_SECOND_LSB 0 +#define RTC_SET_TIME_SECOND_MASK 0x0000007f +#define RTC_SET_TIME_SECOND_GET(x) (((x) & RTC_SET_TIME_SECOND_MASK) >> RTC_SET_TIME_SECOND_LSB) +#define RTC_SET_TIME_SECOND_SET(x) (((x) << RTC_SET_TIME_SECOND_LSB) & RTC_SET_TIME_SECOND_MASK) + +#define RTC_SET_DATE_ADDRESS 0x000000ac +#define RTC_SET_DATE_OFFSET 0x000000ac +#define RTC_SET_DATE_YEAR_MSB 23 +#define RTC_SET_DATE_YEAR_LSB 16 +#define RTC_SET_DATE_YEAR_MASK 0x00ff0000 +#define RTC_SET_DATE_YEAR_GET(x) (((x) & RTC_SET_DATE_YEAR_MASK) >> RTC_SET_DATE_YEAR_LSB) +#define RTC_SET_DATE_YEAR_SET(x) (((x) << RTC_SET_DATE_YEAR_LSB) & RTC_SET_DATE_YEAR_MASK) +#define RTC_SET_DATE_MONTH_MSB 12 +#define RTC_SET_DATE_MONTH_LSB 8 +#define RTC_SET_DATE_MONTH_MASK 0x00001f00 +#define RTC_SET_DATE_MONTH_GET(x) (((x) & RTC_SET_DATE_MONTH_MASK) >> RTC_SET_DATE_MONTH_LSB) +#define RTC_SET_DATE_MONTH_SET(x) (((x) << RTC_SET_DATE_MONTH_LSB) & RTC_SET_DATE_MONTH_MASK) +#define RTC_SET_DATE_MONTH_DAY_MSB 5 +#define RTC_SET_DATE_MONTH_DAY_LSB 0 +#define RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f +#define RTC_SET_DATE_MONTH_DAY_GET(x) (((x) & RTC_SET_DATE_MONTH_DAY_MASK) >> RTC_SET_DATE_MONTH_DAY_LSB) +#define RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << RTC_SET_DATE_MONTH_DAY_LSB) & RTC_SET_DATE_MONTH_DAY_MASK) + +#define RTC_SET_ALARM_ADDRESS 0x000000b0 +#define RTC_SET_ALARM_OFFSET 0x000000b0 +#define RTC_SET_ALARM_HOUR_MSB 21 +#define RTC_SET_ALARM_HOUR_LSB 16 +#define RTC_SET_ALARM_HOUR_MASK 0x003f0000 +#define RTC_SET_ALARM_HOUR_GET(x) (((x) & RTC_SET_ALARM_HOUR_MASK) >> RTC_SET_ALARM_HOUR_LSB) +#define RTC_SET_ALARM_HOUR_SET(x) (((x) << RTC_SET_ALARM_HOUR_LSB) & RTC_SET_ALARM_HOUR_MASK) +#define RTC_SET_ALARM_MINUTE_MSB 14 +#define RTC_SET_ALARM_MINUTE_LSB 8 +#define RTC_SET_ALARM_MINUTE_MASK 0x00007f00 +#define RTC_SET_ALARM_MINUTE_GET(x) (((x) & RTC_SET_ALARM_MINUTE_MASK) >> RTC_SET_ALARM_MINUTE_LSB) +#define RTC_SET_ALARM_MINUTE_SET(x) (((x) << RTC_SET_ALARM_MINUTE_LSB) & RTC_SET_ALARM_MINUTE_MASK) +#define RTC_SET_ALARM_SECOND_MSB 6 +#define RTC_SET_ALARM_SECOND_LSB 0 +#define RTC_SET_ALARM_SECOND_MASK 0x0000007f +#define RTC_SET_ALARM_SECOND_GET(x) (((x) & RTC_SET_ALARM_SECOND_MASK) >> RTC_SET_ALARM_SECOND_LSB) +#define RTC_SET_ALARM_SECOND_SET(x) (((x) << RTC_SET_ALARM_SECOND_LSB) & RTC_SET_ALARM_SECOND_MASK) + +#define RTC_CONFIG_ADDRESS 0x000000b4 +#define RTC_CONFIG_OFFSET 0x000000b4 +#define RTC_CONFIG_BCD_MSB 2 +#define RTC_CONFIG_BCD_LSB 2 +#define RTC_CONFIG_BCD_MASK 0x00000004 +#define RTC_CONFIG_BCD_GET(x) (((x) & RTC_CONFIG_BCD_MASK) >> RTC_CONFIG_BCD_LSB) +#define RTC_CONFIG_BCD_SET(x) (((x) << RTC_CONFIG_BCD_LSB) & RTC_CONFIG_BCD_MASK) +#define RTC_CONFIG_TWELVE_HOUR_MSB 1 +#define RTC_CONFIG_TWELVE_HOUR_LSB 1 +#define RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002 +#define RTC_CONFIG_TWELVE_HOUR_GET(x) (((x) & RTC_CONFIG_TWELVE_HOUR_MASK) >> RTC_CONFIG_TWELVE_HOUR_LSB) +#define RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << RTC_CONFIG_TWELVE_HOUR_LSB) & RTC_CONFIG_TWELVE_HOUR_MASK) +#define RTC_CONFIG_DSE_MSB 0 +#define RTC_CONFIG_DSE_LSB 0 +#define RTC_CONFIG_DSE_MASK 0x00000001 +#define RTC_CONFIG_DSE_GET(x) (((x) & RTC_CONFIG_DSE_MASK) >> RTC_CONFIG_DSE_LSB) +#define RTC_CONFIG_DSE_SET(x) (((x) << RTC_CONFIG_DSE_LSB) & RTC_CONFIG_DSE_MASK) + +#define RTC_ALARM_STATUS_ADDRESS 0x000000b8 +#define RTC_ALARM_STATUS_OFFSET 0x000000b8 +#define RTC_ALARM_STATUS_ENABLE_MSB 1 +#define RTC_ALARM_STATUS_ENABLE_LSB 1 +#define RTC_ALARM_STATUS_ENABLE_MASK 0x00000002 +#define RTC_ALARM_STATUS_ENABLE_GET(x) (((x) & RTC_ALARM_STATUS_ENABLE_MASK) >> RTC_ALARM_STATUS_ENABLE_LSB) +#define RTC_ALARM_STATUS_ENABLE_SET(x) (((x) << RTC_ALARM_STATUS_ENABLE_LSB) & RTC_ALARM_STATUS_ENABLE_MASK) +#define RTC_ALARM_STATUS_INTERRUPT_MSB 0 +#define RTC_ALARM_STATUS_INTERRUPT_LSB 0 +#define RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001 +#define RTC_ALARM_STATUS_INTERRUPT_GET(x) (((x) & RTC_ALARM_STATUS_INTERRUPT_MASK) >> RTC_ALARM_STATUS_INTERRUPT_LSB) +#define RTC_ALARM_STATUS_INTERRUPT_SET(x) (((x) << RTC_ALARM_STATUS_INTERRUPT_LSB) & RTC_ALARM_STATUS_INTERRUPT_MASK) + +#define UART_WAKEUP_ADDRESS 0x000000bc +#define UART_WAKEUP_OFFSET 0x000000bc +#define UART_WAKEUP_ENABLE_MSB 0 +#define UART_WAKEUP_ENABLE_LSB 0 +#define UART_WAKEUP_ENABLE_MASK 0x00000001 +#define UART_WAKEUP_ENABLE_GET(x) (((x) & UART_WAKEUP_ENABLE_MASK) >> UART_WAKEUP_ENABLE_LSB) +#define UART_WAKEUP_ENABLE_SET(x) (((x) << UART_WAKEUP_ENABLE_LSB) & UART_WAKEUP_ENABLE_MASK) + +#define RESET_CAUSE_ADDRESS 0x000000c0 +#define RESET_CAUSE_OFFSET 0x000000c0 +#define RESET_CAUSE_LAST_MSB 2 +#define RESET_CAUSE_LAST_LSB 0 +#define RESET_CAUSE_LAST_MASK 0x00000007 +#define RESET_CAUSE_LAST_GET(x) (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB) +#define RESET_CAUSE_LAST_SET(x) (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK) + +#define SYSTEM_SLEEP_ADDRESS 0x000000c4 +#define SYSTEM_SLEEP_OFFSET 0x000000c4 +#define SYSTEM_SLEEP_HOST_IF_MSB 4 +#define SYSTEM_SLEEP_HOST_IF_LSB 4 +#define SYSTEM_SLEEP_HOST_IF_MASK 0x00000010 +#define SYSTEM_SLEEP_HOST_IF_GET(x) (((x) & SYSTEM_SLEEP_HOST_IF_MASK) >> SYSTEM_SLEEP_HOST_IF_LSB) +#define SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << SYSTEM_SLEEP_HOST_IF_LSB) & SYSTEM_SLEEP_HOST_IF_MASK) +#define SYSTEM_SLEEP_MBOX_MSB 3 +#define SYSTEM_SLEEP_MBOX_LSB 3 +#define SYSTEM_SLEEP_MBOX_MASK 0x00000008 +#define SYSTEM_SLEEP_MBOX_GET(x) (((x) & SYSTEM_SLEEP_MBOX_MASK) >> SYSTEM_SLEEP_MBOX_LSB) +#define SYSTEM_SLEEP_MBOX_SET(x) (((x) << SYSTEM_SLEEP_MBOX_LSB) & SYSTEM_SLEEP_MBOX_MASK) +#define SYSTEM_SLEEP_MAC_IF_MSB 2 +#define SYSTEM_SLEEP_MAC_IF_LSB 2 +#define SYSTEM_SLEEP_MAC_IF_MASK 0x00000004 +#define SYSTEM_SLEEP_MAC_IF_GET(x) (((x) & SYSTEM_SLEEP_MAC_IF_MASK) >> SYSTEM_SLEEP_MAC_IF_LSB) +#define SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << SYSTEM_SLEEP_MAC_IF_LSB) & SYSTEM_SLEEP_MAC_IF_MASK) +#define SYSTEM_SLEEP_LIGHT_MSB 1 +#define SYSTEM_SLEEP_LIGHT_LSB 1 +#define SYSTEM_SLEEP_LIGHT_MASK 0x00000002 +#define SYSTEM_SLEEP_LIGHT_GET(x) (((x) & SYSTEM_SLEEP_LIGHT_MASK) >> SYSTEM_SLEEP_LIGHT_LSB) +#define SYSTEM_SLEEP_LIGHT_SET(x) (((x) << SYSTEM_SLEEP_LIGHT_LSB) & SYSTEM_SLEEP_LIGHT_MASK) +#define SYSTEM_SLEEP_DISABLE_MSB 0 +#define SYSTEM_SLEEP_DISABLE_LSB 0 +#define SYSTEM_SLEEP_DISABLE_MASK 0x00000001 +#define SYSTEM_SLEEP_DISABLE_GET(x) (((x) & SYSTEM_SLEEP_DISABLE_MASK) >> SYSTEM_SLEEP_DISABLE_LSB) +#define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK) + +#define SDIO_WRAPPER_ADDRESS 0x000000c8 +#define SDIO_WRAPPER_OFFSET 0x000000c8 +#define SDIO_WRAPPER_SLEEP_MSB 3 +#define SDIO_WRAPPER_SLEEP_LSB 3 +#define SDIO_WRAPPER_SLEEP_MASK 0x00000008 +#define SDIO_WRAPPER_SLEEP_GET(x) (((x) & SDIO_WRAPPER_SLEEP_MASK) >> SDIO_WRAPPER_SLEEP_LSB) +#define SDIO_WRAPPER_SLEEP_SET(x) (((x) << SDIO_WRAPPER_SLEEP_LSB) & SDIO_WRAPPER_SLEEP_MASK) +#define SDIO_WRAPPER_WAKEUP_MSB 2 +#define SDIO_WRAPPER_WAKEUP_LSB 2 +#define SDIO_WRAPPER_WAKEUP_MASK 0x00000004 +#define SDIO_WRAPPER_WAKEUP_GET(x) (((x) & SDIO_WRAPPER_WAKEUP_MASK) >> SDIO_WRAPPER_WAKEUP_LSB) +#define SDIO_WRAPPER_WAKEUP_SET(x) (((x) << SDIO_WRAPPER_WAKEUP_LSB) & SDIO_WRAPPER_WAKEUP_MASK) +#define SDIO_WRAPPER_SOC_ON_MSB 1 +#define SDIO_WRAPPER_SOC_ON_LSB 1 +#define SDIO_WRAPPER_SOC_ON_MASK 0x00000002 +#define SDIO_WRAPPER_SOC_ON_GET(x) (((x) & SDIO_WRAPPER_SOC_ON_MASK) >> SDIO_WRAPPER_SOC_ON_LSB) +#define SDIO_WRAPPER_SOC_ON_SET(x) (((x) << SDIO_WRAPPER_SOC_ON_LSB) & SDIO_WRAPPER_SOC_ON_MASK) +#define SDIO_WRAPPER_ON_MSB 0 +#define SDIO_WRAPPER_ON_LSB 0 +#define SDIO_WRAPPER_ON_MASK 0x00000001 +#define SDIO_WRAPPER_ON_GET(x) (((x) & SDIO_WRAPPER_ON_MASK) >> SDIO_WRAPPER_ON_LSB) +#define SDIO_WRAPPER_ON_SET(x) (((x) << SDIO_WRAPPER_ON_LSB) & SDIO_WRAPPER_ON_MASK) + +#define MAC_SLEEP_CONTROL_ADDRESS 0x000000cc +#define MAC_SLEEP_CONTROL_OFFSET 0x000000cc +#define MAC_SLEEP_CONTROL_ENABLE_MSB 1 +#define MAC_SLEEP_CONTROL_ENABLE_LSB 0 +#define MAC_SLEEP_CONTROL_ENABLE_MASK 0x00000003 +#define MAC_SLEEP_CONTROL_ENABLE_GET(x) (((x) & MAC_SLEEP_CONTROL_ENABLE_MASK) >> MAC_SLEEP_CONTROL_ENABLE_LSB) +#define MAC_SLEEP_CONTROL_ENABLE_SET(x) (((x) << MAC_SLEEP_CONTROL_ENABLE_LSB) & MAC_SLEEP_CONTROL_ENABLE_MASK) + +#define KEEP_AWAKE_ADDRESS 0x000000d0 +#define KEEP_AWAKE_OFFSET 0x000000d0 +#define KEEP_AWAKE_COUNT_MSB 7 +#define KEEP_AWAKE_COUNT_LSB 0 +#define KEEP_AWAKE_COUNT_MASK 0x000000ff +#define KEEP_AWAKE_COUNT_GET(x) (((x) & KEEP_AWAKE_COUNT_MASK) >> KEEP_AWAKE_COUNT_LSB) +#define KEEP_AWAKE_COUNT_SET(x) (((x) << KEEP_AWAKE_COUNT_LSB) & KEEP_AWAKE_COUNT_MASK) + +#define LPO_CAL_TIME_ADDRESS 0x000000d4 +#define LPO_CAL_TIME_OFFSET 0x000000d4 +#define LPO_CAL_TIME_LENGTH_MSB 13 +#define LPO_CAL_TIME_LENGTH_LSB 0 +#define LPO_CAL_TIME_LENGTH_MASK 0x00003fff +#define LPO_CAL_TIME_LENGTH_GET(x) (((x) & LPO_CAL_TIME_LENGTH_MASK) >> LPO_CAL_TIME_LENGTH_LSB) +#define LPO_CAL_TIME_LENGTH_SET(x) (((x) << LPO_CAL_TIME_LENGTH_LSB) & LPO_CAL_TIME_LENGTH_MASK) + +#define LPO_INIT_DIVIDEND_INT_ADDRESS 0x000000d8 +#define LPO_INIT_DIVIDEND_INT_OFFSET 0x000000d8 +#define LPO_INIT_DIVIDEND_INT_VALUE_MSB 23 +#define LPO_INIT_DIVIDEND_INT_VALUE_LSB 0 +#define LPO_INIT_DIVIDEND_INT_VALUE_MASK 0x00ffffff +#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> LPO_INIT_DIVIDEND_INT_VALUE_LSB) +#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_INT_VALUE_LSB) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) + +#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS 0x000000dc +#define LPO_INIT_DIVIDEND_FRACTION_OFFSET 0x000000dc +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10 +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0 +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) + +#define LPO_CAL_ADDRESS 0x000000e0 +#define LPO_CAL_OFFSET 0x000000e0 +#define LPO_CAL_ENABLE_MSB 20 +#define LPO_CAL_ENABLE_LSB 20 +#define LPO_CAL_ENABLE_MASK 0x00100000 +#define LPO_CAL_ENABLE_GET(x) (((x) & LPO_CAL_ENABLE_MASK) >> LPO_CAL_ENABLE_LSB) +#define LPO_CAL_ENABLE_SET(x) (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK) +#define LPO_CAL_COUNT_MSB 19 +#define LPO_CAL_COUNT_LSB 0 +#define LPO_CAL_COUNT_MASK 0x000fffff +#define LPO_CAL_COUNT_GET(x) (((x) & LPO_CAL_COUNT_MASK) >> LPO_CAL_COUNT_LSB) +#define LPO_CAL_COUNT_SET(x) (((x) << LPO_CAL_COUNT_LSB) & LPO_CAL_COUNT_MASK) + +#define LPO_CAL_TEST_CONTROL_ADDRESS 0x000000e4 +#define LPO_CAL_TEST_CONTROL_OFFSET 0x000000e4 +#define LPO_CAL_TEST_CONTROL_ENABLE_MSB 5 +#define LPO_CAL_TEST_CONTROL_ENABLE_LSB 5 +#define LPO_CAL_TEST_CONTROL_ENABLE_MASK 0x00000020 +#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) (((x) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> LPO_CAL_TEST_CONTROL_ENABLE_LSB) +#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) (((x) << LPO_CAL_TEST_CONTROL_ENABLE_LSB) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4 +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0 +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) + +#define LPO_CAL_TEST_STATUS_ADDRESS 0x000000e8 +#define LPO_CAL_TEST_STATUS_OFFSET 0x000000e8 +#define LPO_CAL_TEST_STATUS_READY_MSB 16 +#define LPO_CAL_TEST_STATUS_READY_LSB 16 +#define LPO_CAL_TEST_STATUS_READY_MASK 0x00010000 +#define LPO_CAL_TEST_STATUS_READY_GET(x) (((x) & LPO_CAL_TEST_STATUS_READY_MASK) >> LPO_CAL_TEST_STATUS_READY_LSB) +#define LPO_CAL_TEST_STATUS_READY_SET(x) (((x) << LPO_CAL_TEST_STATUS_READY_LSB) & LPO_CAL_TEST_STATUS_READY_MASK) +#define LPO_CAL_TEST_STATUS_COUNT_MSB 15 +#define LPO_CAL_TEST_STATUS_COUNT_LSB 0 +#define LPO_CAL_TEST_STATUS_COUNT_MASK 0x0000ffff +#define LPO_CAL_TEST_STATUS_COUNT_GET(x) (((x) & LPO_CAL_TEST_STATUS_COUNT_MASK) >> LPO_CAL_TEST_STATUS_COUNT_LSB) +#define LPO_CAL_TEST_STATUS_COUNT_SET(x) (((x) << LPO_CAL_TEST_STATUS_COUNT_LSB) & LPO_CAL_TEST_STATUS_COUNT_MASK) + +#define CHIP_ID_ADDRESS 0x000000ec +#define CHIP_ID_OFFSET 0x000000ec +#define CHIP_ID_DEVICE_ID_MSB 31 +#define CHIP_ID_DEVICE_ID_LSB 16 +#define CHIP_ID_DEVICE_ID_MASK 0xffff0000 +#define CHIP_ID_DEVICE_ID_GET(x) (((x) & CHIP_ID_DEVICE_ID_MASK) >> CHIP_ID_DEVICE_ID_LSB) +#define CHIP_ID_DEVICE_ID_SET(x) (((x) << CHIP_ID_DEVICE_ID_LSB) & CHIP_ID_DEVICE_ID_MASK) +#define CHIP_ID_CONFIG_ID_MSB 15 +#define CHIP_ID_CONFIG_ID_LSB 4 +#define CHIP_ID_CONFIG_ID_MASK 0x0000fff0 +#define CHIP_ID_CONFIG_ID_GET(x) (((x) & CHIP_ID_CONFIG_ID_MASK) >> CHIP_ID_CONFIG_ID_LSB) +#define CHIP_ID_CONFIG_ID_SET(x) (((x) << CHIP_ID_CONFIG_ID_LSB) & CHIP_ID_CONFIG_ID_MASK) +#define CHIP_ID_VERSION_ID_MSB 3 +#define CHIP_ID_VERSION_ID_LSB 0 +#define CHIP_ID_VERSION_ID_MASK 0x0000000f +#define CHIP_ID_VERSION_ID_GET(x) (((x) & CHIP_ID_VERSION_ID_MASK) >> CHIP_ID_VERSION_ID_LSB) +#define CHIP_ID_VERSION_ID_SET(x) (((x) << CHIP_ID_VERSION_ID_LSB) & CHIP_ID_VERSION_ID_MASK) + +#define DERIVED_RTC_CLK_ADDRESS 0x000000f0 +#define DERIVED_RTC_CLK_OFFSET 0x000000f0 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) +#define DERIVED_RTC_CLK_FORCE_MSB 17 +#define DERIVED_RTC_CLK_FORCE_LSB 16 +#define DERIVED_RTC_CLK_FORCE_MASK 0x00030000 +#define DERIVED_RTC_CLK_FORCE_GET(x) (((x) & DERIVED_RTC_CLK_FORCE_MASK) >> DERIVED_RTC_CLK_FORCE_LSB) +#define DERIVED_RTC_CLK_FORCE_SET(x) (((x) << DERIVED_RTC_CLK_FORCE_LSB) & DERIVED_RTC_CLK_FORCE_MASK) +#define DERIVED_RTC_CLK_PERIOD_MSB 15 +#define DERIVED_RTC_CLK_PERIOD_LSB 1 +#define DERIVED_RTC_CLK_PERIOD_MASK 0x0000fffe +#define DERIVED_RTC_CLK_PERIOD_GET(x) (((x) & DERIVED_RTC_CLK_PERIOD_MASK) >> DERIVED_RTC_CLK_PERIOD_LSB) +#define DERIVED_RTC_CLK_PERIOD_SET(x) (((x) << DERIVED_RTC_CLK_PERIOD_LSB) & DERIVED_RTC_CLK_PERIOD_MASK) + +#define MAC_PCU_SLP32_MODE_ADDRESS 0x000000f4 +#define MAC_PCU_SLP32_MODE_OFFSET 0x000000f4 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK 0x00200000 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB 19 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB 0 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) + +#define MAC_PCU_SLP32_WAKE_ADDRESS 0x000000f8 +#define MAC_PCU_SLP32_WAKE_OFFSET 0x000000f8 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB 15 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB 0 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK 0x0000ffff +#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x) (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) +#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x) (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) + +#define MAC_PCU_SLP32_INC_ADDRESS 0x000000fc +#define MAC_PCU_SLP32_INC_OFFSET 0x000000fc +#define MAC_PCU_SLP32_INC_TSF_INC_MSB 19 +#define MAC_PCU_SLP32_INC_TSF_INC_LSB 0 +#define MAC_PCU_SLP32_INC_TSF_INC_MASK 0x000fffff +#define MAC_PCU_SLP32_INC_TSF_INC_GET(x) (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB) +#define MAC_PCU_SLP32_INC_TSF_INC_SET(x) (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK) + +#define MAC_PCU_SLP_MIB1_ADDRESS 0x00000100 +#define MAC_PCU_SLP_MIB1_OFFSET 0x00000100 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB 31 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB 0 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) + +#define MAC_PCU_SLP_MIB2_ADDRESS 0x00000104 +#define MAC_PCU_SLP_MIB2_OFFSET 0x00000104 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB 31 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB 0 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) + +#define MAC_PCU_SLP_MIB3_ADDRESS 0x00000108 +#define MAC_PCU_SLP_MIB3_OFFSET 0x00000108 +#define MAC_PCU_SLP_MIB3_PENDING_MSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_LSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_MASK 0x00000002 +#define MAC_PCU_SLP_MIB3_PENDING_GET(x) (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB) +#define MAC_PCU_SLP_MIB3_PENDING_SET(x) (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK) +#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK 0x00000001 +#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB) +#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) + +#define MAC_PCU_SLP_BEACON_ADDRESS 0x0000010c +#define MAC_PCU_SLP_BEACON_OFFSET 0x0000010c +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MSB 24 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB 24 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK 0x01000000 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MSB 23 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB 0 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK 0x00ffffff +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) + +#define POWER_REG_ADDRESS 0x00000110 +#define POWER_REG_OFFSET 0x00000110 +#define POWER_REG_VLVL_MSB 11 +#define POWER_REG_VLVL_LSB 8 +#define POWER_REG_VLVL_MASK 0x00000f00 +#define POWER_REG_VLVL_GET(x) (((x) & POWER_REG_VLVL_MASK) >> POWER_REG_VLVL_LSB) +#define POWER_REG_VLVL_SET(x) (((x) << POWER_REG_VLVL_LSB) & POWER_REG_VLVL_MASK) +#define POWER_REG_CPU_INT_ENABLE_MSB 7 +#define POWER_REG_CPU_INT_ENABLE_LSB 7 +#define POWER_REG_CPU_INT_ENABLE_MASK 0x00000080 +#define POWER_REG_CPU_INT_ENABLE_GET(x) (((x) & POWER_REG_CPU_INT_ENABLE_MASK) >> POWER_REG_CPU_INT_ENABLE_LSB) +#define POWER_REG_CPU_INT_ENABLE_SET(x) (((x) << POWER_REG_CPU_INT_ENABLE_LSB) & POWER_REG_CPU_INT_ENABLE_MASK) +#define POWER_REG_WLAN_ISO_DIS_MSB 6 +#define POWER_REG_WLAN_ISO_DIS_LSB 6 +#define POWER_REG_WLAN_ISO_DIS_MASK 0x00000040 +#define POWER_REG_WLAN_ISO_DIS_GET(x) (((x) & POWER_REG_WLAN_ISO_DIS_MASK) >> POWER_REG_WLAN_ISO_DIS_LSB) +#define POWER_REG_WLAN_ISO_DIS_SET(x) (((x) << POWER_REG_WLAN_ISO_DIS_LSB) & POWER_REG_WLAN_ISO_DIS_MASK) +#define POWER_REG_WLAN_ISO_CNTL_MSB 5 +#define POWER_REG_WLAN_ISO_CNTL_LSB 5 +#define POWER_REG_WLAN_ISO_CNTL_MASK 0x00000020 +#define POWER_REG_WLAN_ISO_CNTL_GET(x) (((x) & POWER_REG_WLAN_ISO_CNTL_MASK) >> POWER_REG_WLAN_ISO_CNTL_LSB) +#define POWER_REG_WLAN_ISO_CNTL_SET(x) (((x) << POWER_REG_WLAN_ISO_CNTL_LSB) & POWER_REG_WLAN_ISO_CNTL_MASK) +#define POWER_REG_RADIO_PWD_EN_MSB 4 +#define POWER_REG_RADIO_PWD_EN_LSB 4 +#define POWER_REG_RADIO_PWD_EN_MASK 0x00000010 +#define POWER_REG_RADIO_PWD_EN_GET(x) (((x) & POWER_REG_RADIO_PWD_EN_MASK) >> POWER_REG_RADIO_PWD_EN_LSB) +#define POWER_REG_RADIO_PWD_EN_SET(x) (((x) << POWER_REG_RADIO_PWD_EN_LSB) & POWER_REG_RADIO_PWD_EN_MASK) +#define POWER_REG_SOC_SCALE_EN_MSB 3 +#define POWER_REG_SOC_SCALE_EN_LSB 3 +#define POWER_REG_SOC_SCALE_EN_MASK 0x00000008 +#define POWER_REG_SOC_SCALE_EN_GET(x) (((x) & POWER_REG_SOC_SCALE_EN_MASK) >> POWER_REG_SOC_SCALE_EN_LSB) +#define POWER_REG_SOC_SCALE_EN_SET(x) (((x) << POWER_REG_SOC_SCALE_EN_LSB) & POWER_REG_SOC_SCALE_EN_MASK) +#define POWER_REG_WLAN_SCALE_EN_MSB 2 +#define POWER_REG_WLAN_SCALE_EN_LSB 2 +#define POWER_REG_WLAN_SCALE_EN_MASK 0x00000004 +#define POWER_REG_WLAN_SCALE_EN_GET(x) (((x) & POWER_REG_WLAN_SCALE_EN_MASK) >> POWER_REG_WLAN_SCALE_EN_LSB) +#define POWER_REG_WLAN_SCALE_EN_SET(x) (((x) << POWER_REG_WLAN_SCALE_EN_LSB) & POWER_REG_WLAN_SCALE_EN_MASK) +#define POWER_REG_WLAN_PWD_EN_MSB 1 +#define POWER_REG_WLAN_PWD_EN_LSB 1 +#define POWER_REG_WLAN_PWD_EN_MASK 0x00000002 +#define POWER_REG_WLAN_PWD_EN_GET(x) (((x) & POWER_REG_WLAN_PWD_EN_MASK) >> POWER_REG_WLAN_PWD_EN_LSB) +#define POWER_REG_WLAN_PWD_EN_SET(x) (((x) << POWER_REG_WLAN_PWD_EN_LSB) & POWER_REG_WLAN_PWD_EN_MASK) +#define POWER_REG_POWER_EN_MSB 0 +#define POWER_REG_POWER_EN_LSB 0 +#define POWER_REG_POWER_EN_MASK 0x00000001 +#define POWER_REG_POWER_EN_GET(x) (((x) & POWER_REG_POWER_EN_MASK) >> POWER_REG_POWER_EN_LSB) +#define POWER_REG_POWER_EN_SET(x) (((x) << POWER_REG_POWER_EN_LSB) & POWER_REG_POWER_EN_MASK) + +#define CORE_CLK_CTRL_ADDRESS 0x00000114 +#define CORE_CLK_CTRL_OFFSET 0x00000114 +#define CORE_CLK_CTRL_DIV_MSB 2 +#define CORE_CLK_CTRL_DIV_LSB 0 +#define CORE_CLK_CTRL_DIV_MASK 0x00000007 +#define CORE_CLK_CTRL_DIV_GET(x) (((x) & CORE_CLK_CTRL_DIV_MASK) >> CORE_CLK_CTRL_DIV_LSB) +#define CORE_CLK_CTRL_DIV_SET(x) (((x) << CORE_CLK_CTRL_DIV_LSB) & CORE_CLK_CTRL_DIV_MASK) + +#define SDIO_SETUP_CIRCUIT_ADDRESS 0x00000120 +#define SDIO_SETUP_CIRCUIT_OFFSET 0x00000120 +#define SDIO_SETUP_CIRCUIT_VECTOR_MSB 7 +#define SDIO_SETUP_CIRCUIT_VECTOR_LSB 0 +#define SDIO_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define SDIO_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) >> SDIO_SETUP_CIRCUIT_VECTOR_LSB) +#define SDIO_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << SDIO_SETUP_CIRCUIT_VECTOR_LSB) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) + +#define SDIO_SETUP_CONFIG_ADDRESS 0x00000140 +#define SDIO_SETUP_CONFIG_OFFSET 0x00000140 +#define SDIO_SETUP_CONFIG_ENABLE_MSB 1 +#define SDIO_SETUP_CONFIG_ENABLE_LSB 1 +#define SDIO_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define SDIO_SETUP_CONFIG_ENABLE_GET(x) (((x) & SDIO_SETUP_CONFIG_ENABLE_MASK) >> SDIO_SETUP_CONFIG_ENABLE_LSB) +#define SDIO_SETUP_CONFIG_ENABLE_SET(x) (((x) << SDIO_SETUP_CONFIG_ENABLE_LSB) & SDIO_SETUP_CONFIG_ENABLE_MASK) +#define SDIO_SETUP_CONFIG_CLEAR_MSB 0 +#define SDIO_SETUP_CONFIG_CLEAR_LSB 0 +#define SDIO_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define SDIO_SETUP_CONFIG_CLEAR_GET(x) (((x) & SDIO_SETUP_CONFIG_CLEAR_MASK) >> SDIO_SETUP_CONFIG_CLEAR_LSB) +#define SDIO_SETUP_CONFIG_CLEAR_SET(x) (((x) << SDIO_SETUP_CONFIG_CLEAR_LSB) & SDIO_SETUP_CONFIG_CLEAR_MASK) + +#define CPU_SETUP_CONFIG_ADDRESS 0x00000144 +#define CPU_SETUP_CONFIG_OFFSET 0x00000144 +#define CPU_SETUP_CONFIG_ENABLE_MSB 1 +#define CPU_SETUP_CONFIG_ENABLE_LSB 1 +#define CPU_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define CPU_SETUP_CONFIG_ENABLE_GET(x) (((x) & CPU_SETUP_CONFIG_ENABLE_MASK) >> CPU_SETUP_CONFIG_ENABLE_LSB) +#define CPU_SETUP_CONFIG_ENABLE_SET(x) (((x) << CPU_SETUP_CONFIG_ENABLE_LSB) & CPU_SETUP_CONFIG_ENABLE_MASK) +#define CPU_SETUP_CONFIG_CLEAR_MSB 0 +#define CPU_SETUP_CONFIG_CLEAR_LSB 0 +#define CPU_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define CPU_SETUP_CONFIG_CLEAR_GET(x) (((x) & CPU_SETUP_CONFIG_CLEAR_MASK) >> CPU_SETUP_CONFIG_CLEAR_LSB) +#define CPU_SETUP_CONFIG_CLEAR_SET(x) (((x) << CPU_SETUP_CONFIG_CLEAR_LSB) & CPU_SETUP_CONFIG_CLEAR_MASK) + +#define CPU_SETUP_CIRCUIT_ADDRESS 0x00000160 +#define CPU_SETUP_CIRCUIT_OFFSET 0x00000160 +#define CPU_SETUP_CIRCUIT_VECTOR_MSB 7 +#define CPU_SETUP_CIRCUIT_VECTOR_LSB 0 +#define CPU_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define CPU_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & CPU_SETUP_CIRCUIT_VECTOR_MASK) >> CPU_SETUP_CIRCUIT_VECTOR_LSB) +#define CPU_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << CPU_SETUP_CIRCUIT_VECTOR_LSB) & CPU_SETUP_CIRCUIT_VECTOR_MASK) + +#define BB_SETUP_CONFIG_ADDRESS 0x00000180 +#define BB_SETUP_CONFIG_OFFSET 0x00000180 +#define BB_SETUP_CONFIG_ENABLE_MSB 1 +#define BB_SETUP_CONFIG_ENABLE_LSB 1 +#define BB_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define BB_SETUP_CONFIG_ENABLE_GET(x) (((x) & BB_SETUP_CONFIG_ENABLE_MASK) >> BB_SETUP_CONFIG_ENABLE_LSB) +#define BB_SETUP_CONFIG_ENABLE_SET(x) (((x) << BB_SETUP_CONFIG_ENABLE_LSB) & BB_SETUP_CONFIG_ENABLE_MASK) +#define BB_SETUP_CONFIG_CLEAR_MSB 0 +#define BB_SETUP_CONFIG_CLEAR_LSB 0 +#define BB_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define BB_SETUP_CONFIG_CLEAR_GET(x) (((x) & BB_SETUP_CONFIG_CLEAR_MASK) >> BB_SETUP_CONFIG_CLEAR_LSB) +#define BB_SETUP_CONFIG_CLEAR_SET(x) (((x) << BB_SETUP_CONFIG_CLEAR_LSB) & BB_SETUP_CONFIG_CLEAR_MASK) + +#define BB_SETUP_CIRCUIT_ADDRESS 0x000001a0 +#define BB_SETUP_CIRCUIT_OFFSET 0x000001a0 +#define BB_SETUP_CIRCUIT_VECTOR_MSB 7 +#define BB_SETUP_CIRCUIT_VECTOR_LSB 0 +#define BB_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define BB_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & BB_SETUP_CIRCUIT_VECTOR_MASK) >> BB_SETUP_CIRCUIT_VECTOR_LSB) +#define BB_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << BB_SETUP_CIRCUIT_VECTOR_LSB) & BB_SETUP_CIRCUIT_VECTOR_MASK) + +#define GPIO_WAKEUP_CONTROL_ADDRESS 0x000001c0 +#define GPIO_WAKEUP_CONTROL_OFFSET 0x000001c0 +#define GPIO_WAKEUP_CONTROL_ENABLE_MSB 0 +#define GPIO_WAKEUP_CONTROL_ENABLE_LSB 0 +#define GPIO_WAKEUP_CONTROL_ENABLE_MASK 0x00000001 +#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) (((x) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> GPIO_WAKEUP_CONTROL_ENABLE_LSB) +#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) (((x) << GPIO_WAKEUP_CONTROL_ENABLE_LSB) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct rtc_reg_reg_s { + volatile unsigned int reset_control; + volatile unsigned int xtal_control; + volatile unsigned int tcxo_detect; + volatile unsigned int xtal_test; + volatile unsigned int quadrature; + volatile unsigned int pll_control; + volatile unsigned int pll_settle; + volatile unsigned int xtal_settle; + volatile unsigned int cpu_clock; + volatile unsigned int clock_out; + volatile unsigned int clock_control; + volatile unsigned int bias_override; + volatile unsigned int wdt_control; + volatile unsigned int wdt_status; + volatile unsigned int wdt; + volatile unsigned int wdt_count; + volatile unsigned int wdt_reset; + volatile unsigned int int_status; + volatile unsigned int lf_timer0; + volatile unsigned int lf_timer_count0; + volatile unsigned int lf_timer_control0; + volatile unsigned int lf_timer_status0; + volatile unsigned int lf_timer1; + volatile unsigned int lf_timer_count1; + volatile unsigned int lf_timer_control1; + volatile unsigned int lf_timer_status1; + volatile unsigned int lf_timer2; + volatile unsigned int lf_timer_count2; + volatile unsigned int lf_timer_control2; + volatile unsigned int lf_timer_status2; + volatile unsigned int lf_timer3; + volatile unsigned int lf_timer_count3; + volatile unsigned int lf_timer_control3; + volatile unsigned int lf_timer_status3; + volatile unsigned int hf_timer; + volatile unsigned int hf_timer_count; + volatile unsigned int hf_lf_count; + volatile unsigned int hf_timer_control; + volatile unsigned int hf_timer_status; + volatile unsigned int rtc_control; + volatile unsigned int rtc_time; + volatile unsigned int rtc_date; + volatile unsigned int rtc_set_time; + volatile unsigned int rtc_set_date; + volatile unsigned int rtc_set_alarm; + volatile unsigned int rtc_config; + volatile unsigned int rtc_alarm_status; + volatile unsigned int uart_wakeup; + volatile unsigned int reset_cause; + volatile unsigned int system_sleep; + volatile unsigned int sdio_wrapper; + volatile unsigned int mac_sleep_control; + volatile unsigned int keep_awake; + volatile unsigned int lpo_cal_time; + volatile unsigned int lpo_init_dividend_int; + volatile unsigned int lpo_init_dividend_fraction; + volatile unsigned int lpo_cal; + volatile unsigned int lpo_cal_test_control; + volatile unsigned int lpo_cal_test_status; + volatile unsigned int chip_id; + volatile unsigned int derived_rtc_clk; + volatile unsigned int mac_pcu_slp32_mode; + volatile unsigned int mac_pcu_slp32_wake; + volatile unsigned int mac_pcu_slp32_inc; + volatile unsigned int mac_pcu_slp_mib1; + volatile unsigned int mac_pcu_slp_mib2; + volatile unsigned int mac_pcu_slp_mib3; + volatile unsigned int mac_pcu_slp_beacon; + volatile unsigned int power_reg; + volatile unsigned int core_clk_ctrl; + unsigned char pad0[8]; /* pad to 0x120 */ + volatile unsigned int sdio_setup_circuit[8]; + volatile unsigned int sdio_setup_config; + volatile unsigned int cpu_setup_config; + unsigned char pad1[24]; /* pad to 0x160 */ + volatile unsigned int cpu_setup_circuit[8]; + volatile unsigned int bb_setup_config; + unsigned char pad2[28]; /* pad to 0x1a0 */ + volatile unsigned int bb_setup_circuit[8]; + volatile unsigned int gpio_wakeup_control; +} rtc_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _RTC_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/si_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/si_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k/si_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/si_reg.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,209 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _SI_REG_REG_H_ +#define _SI_REG_REG_H_ + +#define SI_CONFIG_ADDRESS 0x00000000 +#define SI_CONFIG_OFFSET 0x00000000 +#define SI_CONFIG_ERR_INT_MSB 19 +#define SI_CONFIG_ERR_INT_LSB 19 +#define SI_CONFIG_ERR_INT_MASK 0x00080000 +#define SI_CONFIG_ERR_INT_GET(x) (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB) +#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK) +#define SI_CONFIG_BIDIR_OD_DATA_MSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_LSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 +#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB) +#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK) +#define SI_CONFIG_I2C_MSB 16 +#define SI_CONFIG_I2C_LSB 16 +#define SI_CONFIG_I2C_MASK 0x00010000 +#define SI_CONFIG_I2C_GET(x) (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB) +#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) +#define SI_CONFIG_POS_SAMPLE_MSB 7 +#define SI_CONFIG_POS_SAMPLE_LSB 7 +#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 +#define SI_CONFIG_POS_SAMPLE_GET(x) (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB) +#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK) +#define SI_CONFIG_POS_DRIVE_MSB 6 +#define SI_CONFIG_POS_DRIVE_LSB 6 +#define SI_CONFIG_POS_DRIVE_MASK 0x00000040 +#define SI_CONFIG_POS_DRIVE_GET(x) (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB) +#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK) +#define SI_CONFIG_INACTIVE_DATA_MSB 5 +#define SI_CONFIG_INACTIVE_DATA_LSB 5 +#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 +#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB) +#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK) +#define SI_CONFIG_INACTIVE_CLK_MSB 4 +#define SI_CONFIG_INACTIVE_CLK_LSB 4 +#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 +#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB) +#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK) +#define SI_CONFIG_DIVIDER_MSB 3 +#define SI_CONFIG_DIVIDER_LSB 0 +#define SI_CONFIG_DIVIDER_MASK 0x0000000f +#define SI_CONFIG_DIVIDER_GET(x) (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB) +#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) + +#define SI_CS_ADDRESS 0x00000004 +#define SI_CS_OFFSET 0x00000004 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) +#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) +#define SI_CS_DONE_ERR_MSB 10 +#define SI_CS_DONE_ERR_LSB 10 +#define SI_CS_DONE_ERR_MASK 0x00000400 +#define SI_CS_DONE_ERR_GET(x) (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB) +#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK) +#define SI_CS_DONE_INT_MSB 9 +#define SI_CS_DONE_INT_LSB 9 +#define SI_CS_DONE_INT_MASK 0x00000200 +#define SI_CS_DONE_INT_GET(x) (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB) +#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK) +#define SI_CS_START_MSB 8 +#define SI_CS_START_LSB 8 +#define SI_CS_START_MASK 0x00000100 +#define SI_CS_START_GET(x) (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB) +#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) +#define SI_CS_RX_CNT_MSB 7 +#define SI_CS_RX_CNT_LSB 4 +#define SI_CS_RX_CNT_MASK 0x000000f0 +#define SI_CS_RX_CNT_GET(x) (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB) +#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) +#define SI_CS_TX_CNT_MSB 3 +#define SI_CS_TX_CNT_LSB 0 +#define SI_CS_TX_CNT_MASK 0x0000000f +#define SI_CS_TX_CNT_GET(x) (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB) +#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) + +#define SI_TX_DATA0_ADDRESS 0x00000008 +#define SI_TX_DATA0_OFFSET 0x00000008 +#define SI_TX_DATA0_DATA3_MSB 31 +#define SI_TX_DATA0_DATA3_LSB 24 +#define SI_TX_DATA0_DATA3_MASK 0xff000000 +#define SI_TX_DATA0_DATA3_GET(x) (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB) +#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK) +#define SI_TX_DATA0_DATA2_MSB 23 +#define SI_TX_DATA0_DATA2_LSB 16 +#define SI_TX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_TX_DATA0_DATA2_GET(x) (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB) +#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK) +#define SI_TX_DATA0_DATA1_MSB 15 +#define SI_TX_DATA0_DATA1_LSB 8 +#define SI_TX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_TX_DATA0_DATA1_GET(x) (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB) +#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK) +#define SI_TX_DATA0_DATA0_MSB 7 +#define SI_TX_DATA0_DATA0_LSB 0 +#define SI_TX_DATA0_DATA0_MASK 0x000000ff +#define SI_TX_DATA0_DATA0_GET(x) (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB) +#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK) + +#define SI_TX_DATA1_ADDRESS 0x0000000c +#define SI_TX_DATA1_OFFSET 0x0000000c +#define SI_TX_DATA1_DATA7_MSB 31 +#define SI_TX_DATA1_DATA7_LSB 24 +#define SI_TX_DATA1_DATA7_MASK 0xff000000 +#define SI_TX_DATA1_DATA7_GET(x) (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB) +#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK) +#define SI_TX_DATA1_DATA6_MSB 23 +#define SI_TX_DATA1_DATA6_LSB 16 +#define SI_TX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_TX_DATA1_DATA6_GET(x) (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB) +#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK) +#define SI_TX_DATA1_DATA5_MSB 15 +#define SI_TX_DATA1_DATA5_LSB 8 +#define SI_TX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_TX_DATA1_DATA5_GET(x) (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB) +#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK) +#define SI_TX_DATA1_DATA4_MSB 7 +#define SI_TX_DATA1_DATA4_LSB 0 +#define SI_TX_DATA1_DATA4_MASK 0x000000ff +#define SI_TX_DATA1_DATA4_GET(x) (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB) +#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK) + +#define SI_RX_DATA0_ADDRESS 0x00000010 +#define SI_RX_DATA0_OFFSET 0x00000010 +#define SI_RX_DATA0_DATA3_MSB 31 +#define SI_RX_DATA0_DATA3_LSB 24 +#define SI_RX_DATA0_DATA3_MASK 0xff000000 +#define SI_RX_DATA0_DATA3_GET(x) (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB) +#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK) +#define SI_RX_DATA0_DATA2_MSB 23 +#define SI_RX_DATA0_DATA2_LSB 16 +#define SI_RX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_RX_DATA0_DATA2_GET(x) (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB) +#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK) +#define SI_RX_DATA0_DATA1_MSB 15 +#define SI_RX_DATA0_DATA1_LSB 8 +#define SI_RX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_RX_DATA0_DATA1_GET(x) (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB) +#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK) +#define SI_RX_DATA0_DATA0_MSB 7 +#define SI_RX_DATA0_DATA0_LSB 0 +#define SI_RX_DATA0_DATA0_MASK 0x000000ff +#define SI_RX_DATA0_DATA0_GET(x) (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB) +#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK) + +#define SI_RX_DATA1_ADDRESS 0x00000014 +#define SI_RX_DATA1_OFFSET 0x00000014 +#define SI_RX_DATA1_DATA7_MSB 31 +#define SI_RX_DATA1_DATA7_LSB 24 +#define SI_RX_DATA1_DATA7_MASK 0xff000000 +#define SI_RX_DATA1_DATA7_GET(x) (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB) +#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK) +#define SI_RX_DATA1_DATA6_MSB 23 +#define SI_RX_DATA1_DATA6_LSB 16 +#define SI_RX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_RX_DATA1_DATA6_GET(x) (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB) +#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK) +#define SI_RX_DATA1_DATA5_MSB 15 +#define SI_RX_DATA1_DATA5_LSB 8 +#define SI_RX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_RX_DATA1_DATA5_GET(x) (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB) +#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK) +#define SI_RX_DATA1_DATA4_MSB 7 +#define SI_RX_DATA1_DATA4_LSB 0 +#define SI_RX_DATA1_DATA4_MASK 0x000000ff +#define SI_RX_DATA1_DATA4_GET(x) (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB) +#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct si_reg_reg_s { + volatile unsigned int si_config; + volatile unsigned int si_cs; + volatile unsigned int si_tx_data0; + volatile unsigned int si_tx_data1; + volatile unsigned int si_rx_data0; + volatile unsigned int si_rx_data1; +} si_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _SI_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/targaddrs.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/targaddrs.h --- linux-2.6.26/drivers/net/wireless/ath6k/targaddrs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/targaddrs.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,202 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __TARGADDRS_H__ +#define __TARGADDRS_H__ +#if defined(AR6001) +#include "AR6001/addrs.h" +#endif +#if defined(AR6002) +#include "AR6002/addrs.h" +#endif + +/* + * AR6K option bits, to enable/disable various features. + * By default, all option bits are 0. + * These bits can be set in LOCAL_SCRATCH register 0. + */ +#define AR6K_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */ +#define AR6K_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */ +#define AR6K_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */ +#define AR6K_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */ +#define AR6K_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */ +#define AR6K_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */ +#define AR6K_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */ +#define AR6K_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */ + +/* + * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the + * host_interest structure. It must match the address of the _host_interest + * symbol (see linker script). + * + * Host Interest is shared between Host and Target in order to coordinate + * between the two, and is intended to remain constant (with additions only + * at the end) across software releases. + * + * All addresses are available here so that it's possible to + * write a single binary that works with all Target Types. + * May be used in assembler code as well as C. + */ +#define AR6001_HOST_INTEREST_ADDRESS 0x80000600 +#define AR6002_HOST_INTEREST_ADDRESS 0x00500400 +#define AR6003_HOST_INTEREST_ADDRESS 0x00540400 + + +#define HOST_INTEREST_MAX_SIZE 0x100 + +#if !defined(__ASSEMBLER__) +struct register_dump_s; +struct dbglog_hdr_s; + +/* + * These are items that the Host may need to access + * via BMI or via the Diagnostic Window. The position + * of items in this structure must remain constant + * across firmware revisions! + * + * Types for each item must be fixed size across + * target and host platforms. + * + * More items may be added at the end. + */ +struct host_interest_s { + /* + * Pointer to application-defined area, if any. + * Set by Target application during startup. + */ + A_UINT32 hi_app_host_interest; /* 0x00 */ + + /* Pointer to register dump area, valid after Target crash. */ + A_UINT32 hi_failure_state; /* 0x04 */ + + /* Pointer to debug logging header */ + A_UINT32 hi_dbglog_hdr; /* 0x08 */ + + /* Indicates whether or not flash is present on Target. + * NB: flash_is_present indicator is here not just + * because it might be of interest to the Host; but + * also because it's set early on by Target's startup + * asm code and we need it to have a special RAM address + * so that it doesn't get reinitialized with the rest + * of data. + */ + A_UINT32 hi_flash_is_present; /* 0x0c */ + + /* + * General-purpose flag bits, similar to AR6000_OPTION_* flags. + * Can be used by application rather than by OS. + */ + A_UINT32 hi_option_flag; /* 0x10 */ + + /* + * Boolean that determines whether or not to + * display messages on the serial port. + */ + A_UINT32 hi_serial_enable; /* 0x14 */ + + /* Start address of Flash DataSet index, if any */ + A_UINT32 hi_dset_list_head; /* 0x18 */ + + /* Override Target application start address */ + A_UINT32 hi_app_start; /* 0x1c */ + + /* Clock and voltage tuning */ + A_UINT32 hi_skip_clock_init; /* 0x20 */ + A_UINT32 hi_core_clock_setting; /* 0x24 */ + A_UINT32 hi_cpu_clock_setting; /* 0x28 */ + A_UINT32 hi_system_sleep_setting; /* 0x2c */ + A_UINT32 hi_xtal_control_setting; /* 0x30 */ + A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ + A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ + A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */ + A_UINT32 hi_clock_info; /* 0x40 */ + + /* + * Flash configuration overrides, used only + * when firmware is not executing from flash. + * (When using flash, modify the global variables + * with equivalent names.) + */ + A_UINT32 hi_bank0_addr_value; /* 0x44 */ + A_UINT32 hi_bank0_read_value; /* 0x48 */ + A_UINT32 hi_bank0_write_value; /* 0x4c */ + A_UINT32 hi_bank0_config_value; /* 0x50 */ + + /* Pointer to Board Data */ + A_UINT32 hi_board_data; /* 0x54 */ + A_UINT32 hi_board_data_initialized; /* 0x58 */ + + A_UINT32 hi_dset_RAM_index_table; /* 0x5c */ + + A_UINT32 hi_desired_baud_rate; /* 0x60 */ + A_UINT32 hi_dbglog_config; /* 0x64 */ + A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */ + A_UINT32 hi_mbox_io_block_sz; /* 0x6c */ + + A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */ + A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */ + + A_UINT32 hi_refclk_hz; /* 0x78 */ + A_UINT32 hi_ext_clk_detected; /* 0x7c */ +}; + +/* Bits defined in hi_option_flag */ +#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */ +#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */ +#define HI_OPTION_RELAY_DOT11_HDR 0x04 /*Relay Dot11 hdr to/from host */ + +/* 2 bits of hi_option_flag are used to represent 3 modes */ +#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */ +#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */ +#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */ + +/* Fw Mode Mask */ +#define HI_OPTION_FW_MODE_MASK 0x3 +#define HI_OPTION_FW_MODE_SHIFT 0x3 + +/* + * Intended for use by Host software, this macro returns the Target RAM + * address of any item in the host_interest structure. + * Example: target_addr = AR6001_HOST_INTEREST_ITEM_ADDRESS(hi_board_data); + */ +#define AR6001_HOST_INTEREST_ITEM_ADDRESS(item) \ + ((A_UINT32)&((((struct host_interest_s *)(AR6001_HOST_INTEREST_ADDRESS))->item))) + +#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \ + ((A_UINT32)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item))) + +#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \ + ((A_UINT32)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item))) + +/* Convert a Target virtual address into a Target physical address */ +#define AR6001_VTOP(vaddr) ((vaddr) & 0x0fffffff) +#define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff) +#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff) +#define TARG_VTOP(TargetType, vaddr) \ + (((TargetType) == TARGET_TYPE_AR6001) ? AR6001_VTOP(vaddr) : \ + (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : AR6003_VTOP(vaddr))) + + +#endif /* !__ASSEMBLER__ */ + +#endif /* __TARGADDRS_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/testcmd.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/testcmd.h --- linux-2.6.26/drivers/net/wireless/ath6k/testcmd.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/testcmd.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,165 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2005 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef TESTCMD_H_ +#define TESTCMD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ZEROES_PATTERN = 0, + ONES_PATTERN, + REPEATING_10, + PN7_PATTERN, + PN9_PATTERN, + PN15_PATTERN +}TX_DATA_PATTERN; + +/* Continous tx + mode : TCMD_CONT_TX_OFF - Disabling continous tx + TCMD_CONT_TX_SINE - Enable continuous unmodulated tx + TCMD_CONT_TX_FRAME- Enable continuous modulated tx + freq : Channel freq in Mhz. (e.g 2412 for channel 1 in 11 g) +dataRate: 0 - 1 Mbps + 1 - 2 Mbps + 2 - 5.5 Mbps + 3 - 11 Mbps + 4 - 6 Mbps + 5 - 9 Mbps + 6 - 12 Mbps + 7 - 18 Mbps + 8 - 24 Mbps + 9 - 36 Mbps + 10 - 28 Mbps + 11 - 54 Mbps + txPwr: Tx power in dBm[5 -11] for unmod Tx, [5-14] for mod Tx +antenna: 1 - one antenna + 2 - two antenna +Note : Enable/disable continuous tx test cmd works only when target is awake. +*/ + +typedef enum { + TCMD_CONT_TX_OFF = 0, + TCMD_CONT_TX_SINE, + TCMD_CONT_TX_FRAME, + TCMD_CONT_TX_TX99, + TCMD_CONT_TX_TX100 +} TCMD_CONT_TX_MODE; + +typedef PREPACK struct { + A_UINT32 testCmdId; + A_UINT32 mode; + A_UINT32 freq; + A_UINT32 dataRate; + A_INT32 txPwr; + A_UINT32 antenna; + A_UINT32 enANI; + A_UINT32 scramblerOff; + A_UINT32 aifsn; + A_UINT16 pktSz; + A_UINT16 txPattern; +} POSTPACK TCMD_CONT_TX; + +#define TCMD_TXPATTERN_ZERONE 0x1 +#define TCMD_TXPATTERN_ZERONE_DIS_SCRAMBLE 0x2 + +/* Continuous Rx + act: TCMD_CONT_RX_PROMIS - promiscuous mode (accept all incoming frames) + TCMD_CONT_RX_FILTER - filter mode (accept only frames with dest + address equal specified + mac address (set via act =3) + TCMD_CONT_RX_REPORT off mode (disable cont rx mode and get the + report from the last cont + Rx test) + + TCMD_CONT_RX_SETMAC - set MacAddr mode (sets the MAC address for the + target. This Overrides + the default MAC address.) + +*/ +typedef enum { + TCMD_CONT_RX_PROMIS =0, + TCMD_CONT_RX_FILTER, + TCMD_CONT_RX_REPORT, + TCMD_CONT_RX_SETMAC, + TCMD_CONT_RX_SET_ANT_SWITCH_TABLE +} TCMD_CONT_RX_ACT; + +typedef PREPACK struct { + A_UINT32 testCmdId; + A_UINT32 act; + A_UINT32 enANI; + PREPACK union { + struct PREPACK TCMD_CONT_RX_PARA { + A_UINT32 freq; + A_UINT32 antenna; + } POSTPACK para; + struct PREPACK TCMD_CONT_RX_REPORT { + A_UINT32 totalPkt; + A_INT32 rssiInDBm; + A_UINT32 crcErrPkt; + A_UINT32 secErrPkt; + } POSTPACK report; + struct PREPACK TCMD_CONT_RX_MAC { + A_UCHAR addr[ATH_MAC_LEN]; + } POSTPACK mac; + struct PREPACK TCMD_CONT_RX_ANT_SWITCH_TABLE { + A_UINT32 antswitch1; + A_UINT32 antswitch2; + }POSTPACK antswitchtable; + } POSTPACK u; +} POSTPACK TCMD_CONT_RX; + +/* Force sleep/wake test cmd + mode: TCMD_PM_WAKEUP - Wakeup the target + TCMD_PM_SLEEP - Force the target to sleep. + */ +typedef enum { + TCMD_PM_WAKEUP = 1, /* be consistent with target */ + TCMD_PM_SLEEP +} TCMD_PM_MODE; + +typedef PREPACK struct { + A_UINT32 testCmdId; + A_UINT32 mode; +} POSTPACK TCMD_PM; + +typedef enum { + TCMD_CONT_TX_ID, + TCMD_CONT_RX_ID, + TCMD_PM_ID +} TCMD_ID; + +typedef PREPACK union { + TCMD_CONT_TX contTx; + TCMD_CONT_RX contRx; + TCMD_PM pm; +} POSTPACK TEST_CMD; + +#ifdef __cplusplus +} +#endif + +#endif /* TESTCMD_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/uart_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/uart_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k/uart_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/uart_reg.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,350 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _UART_REG_REG_H_ +#define _UART_REG_REG_H_ + +#define RBR_ADDRESS 0x00000000 +#define RBR_OFFSET 0x00000000 +#define RBR_RBR_MSB 7 +#define RBR_RBR_LSB 0 +#define RBR_RBR_MASK 0x000000ff +#define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB) +#define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK) + +#define THR_ADDRESS 0x00000000 +#define THR_OFFSET 0x00000000 +#define THR_THR_MSB 7 +#define THR_THR_LSB 0 +#define THR_THR_MASK 0x000000ff +#define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_THR_LSB) +#define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK) + +#define DLL_ADDRESS 0x00000000 +#define DLL_OFFSET 0x00000000 +#define DLL_DLL_MSB 7 +#define DLL_DLL_LSB 0 +#define DLL_DLL_MASK 0x000000ff +#define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB) +#define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK) + +#define DLH_ADDRESS 0x00000004 +#define DLH_OFFSET 0x00000004 +#define DLH_DLH_MSB 7 +#define DLH_DLH_LSB 0 +#define DLH_DLH_MASK 0x000000ff +#define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB) +#define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK) + +#define IER_ADDRESS 0x00000004 +#define IER_OFFSET 0x00000004 +#define IER_EDDSI_MSB 3 +#define IER_EDDSI_LSB 3 +#define IER_EDDSI_MASK 0x00000008 +#define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB) +#define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK) +#define IER_ELSI_MSB 2 +#define IER_ELSI_LSB 2 +#define IER_ELSI_MASK 0x00000004 +#define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB) +#define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK) +#define IER_ETBEI_MSB 1 +#define IER_ETBEI_LSB 1 +#define IER_ETBEI_MASK 0x00000002 +#define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB) +#define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK) +#define IER_ERBFI_MSB 0 +#define IER_ERBFI_LSB 0 +#define IER_ERBFI_MASK 0x00000001 +#define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB) +#define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK) + +#define IIR_ADDRESS 0x00000008 +#define IIR_OFFSET 0x00000008 +#define IIR_FIFO_STATUS_MSB 7 +#define IIR_FIFO_STATUS_LSB 6 +#define IIR_FIFO_STATUS_MASK 0x000000c0 +#define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB) +#define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK) +#define IIR_IID_MSB 3 +#define IIR_IID_LSB 0 +#define IIR_IID_MASK 0x0000000f +#define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_IID_LSB) +#define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK) + +#define FCR_ADDRESS 0x00000008 +#define FCR_OFFSET 0x00000008 +#define FCR_RCVR_TRIG_MSB 7 +#define FCR_RCVR_TRIG_LSB 6 +#define FCR_RCVR_TRIG_MASK 0x000000c0 +#define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB) +#define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK) +#define FCR_DMA_MODE_MSB 3 +#define FCR_DMA_MODE_LSB 3 +#define FCR_DMA_MODE_MASK 0x00000008 +#define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB) +#define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK) +#define FCR_XMIT_FIFO_RST_MSB 2 +#define FCR_XMIT_FIFO_RST_LSB 2 +#define FCR_XMIT_FIFO_RST_MASK 0x00000004 +#define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB) +#define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK) +#define FCR_RCVR_FIFO_RST_MSB 1 +#define FCR_RCVR_FIFO_RST_LSB 1 +#define FCR_RCVR_FIFO_RST_MASK 0x00000002 +#define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB) +#define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK) +#define FCR_FIFO_EN_MSB 0 +#define FCR_FIFO_EN_LSB 0 +#define FCR_FIFO_EN_MASK 0x00000001 +#define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB) +#define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK) + +#define LCR_ADDRESS 0x0000000c +#define LCR_OFFSET 0x0000000c +#define LCR_DLAB_MSB 7 +#define LCR_DLAB_LSB 7 +#define LCR_DLAB_MASK 0x00000080 +#define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB) +#define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK) +#define LCR_BREAK_MSB 6 +#define LCR_BREAK_LSB 6 +#define LCR_BREAK_MASK 0x00000040 +#define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB) +#define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK) +#define LCR_EPS_MSB 4 +#define LCR_EPS_LSB 4 +#define LCR_EPS_MASK 0x00000010 +#define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB) +#define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK) +#define LCR_PEN_MSB 3 +#define LCR_PEN_LSB 3 +#define LCR_PEN_MASK 0x00000008 +#define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB) +#define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK) +#define LCR_STOP_MSB 2 +#define LCR_STOP_LSB 2 +#define LCR_STOP_MASK 0x00000004 +#define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB) +#define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK) +#define LCR_CLS_MSB 1 +#define LCR_CLS_LSB 0 +#define LCR_CLS_MASK 0x00000003 +#define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB) +#define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK) + +#define MCR_ADDRESS 0x00000010 +#define MCR_OFFSET 0x00000010 +#define MCR_LOOPBACK_MSB 5 +#define MCR_LOOPBACK_LSB 5 +#define MCR_LOOPBACK_MASK 0x00000020 +#define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB) +#define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK) +#define MCR_OUT2_MSB 3 +#define MCR_OUT2_LSB 3 +#define MCR_OUT2_MASK 0x00000008 +#define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB) +#define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK) +#define MCR_OUT1_MSB 2 +#define MCR_OUT1_LSB 2 +#define MCR_OUT1_MASK 0x00000004 +#define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB) +#define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK) +#define MCR_RTS_MSB 1 +#define MCR_RTS_LSB 1 +#define MCR_RTS_MASK 0x00000002 +#define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB) +#define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK) +#define MCR_DTR_MSB 0 +#define MCR_DTR_LSB 0 +#define MCR_DTR_MASK 0x00000001 +#define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB) +#define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK) + +#define LSR_ADDRESS 0x00000014 +#define LSR_OFFSET 0x00000014 +#define LSR_FERR_MSB 7 +#define LSR_FERR_LSB 7 +#define LSR_FERR_MASK 0x00000080 +#define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB) +#define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK) +#define LSR_TEMT_MSB 6 +#define LSR_TEMT_LSB 6 +#define LSR_TEMT_MASK 0x00000040 +#define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB) +#define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK) +#define LSR_THRE_MSB 5 +#define LSR_THRE_LSB 5 +#define LSR_THRE_MASK 0x00000020 +#define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB) +#define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK) +#define LSR_BI_MSB 4 +#define LSR_BI_LSB 4 +#define LSR_BI_MASK 0x00000010 +#define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_LSB) +#define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK) +#define LSR_FE_MSB 3 +#define LSR_FE_LSB 3 +#define LSR_FE_MASK 0x00000008 +#define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_LSB) +#define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK) +#define LSR_PE_MSB 2 +#define LSR_PE_LSB 2 +#define LSR_PE_MASK 0x00000004 +#define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_LSB) +#define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK) +#define LSR_OE_MSB 1 +#define LSR_OE_LSB 1 +#define LSR_OE_MASK 0x00000002 +#define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_LSB) +#define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK) +#define LSR_DR_MSB 0 +#define LSR_DR_LSB 0 +#define LSR_DR_MASK 0x00000001 +#define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_LSB) +#define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK) + +#define MSR_ADDRESS 0x00000018 +#define MSR_OFFSET 0x00000018 +#define MSR_DCD_MSB 7 +#define MSR_DCD_LSB 7 +#define MSR_DCD_MASK 0x00000080 +#define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB) +#define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK) +#define MSR_RI_MSB 6 +#define MSR_RI_LSB 6 +#define MSR_RI_MASK 0x00000040 +#define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_LSB) +#define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK) +#define MSR_DSR_MSB 5 +#define MSR_DSR_LSB 5 +#define MSR_DSR_MASK 0x00000020 +#define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB) +#define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK) +#define MSR_CTS_MSB 4 +#define MSR_CTS_LSB 4 +#define MSR_CTS_MASK 0x00000010 +#define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB) +#define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK) +#define MSR_DDCD_MSB 3 +#define MSR_DDCD_LSB 3 +#define MSR_DDCD_MASK 0x00000008 +#define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB) +#define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK) +#define MSR_TERI_MSB 2 +#define MSR_TERI_LSB 2 +#define MSR_TERI_MASK 0x00000004 +#define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB) +#define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK) +#define MSR_DDSR_MSB 1 +#define MSR_DDSR_LSB 1 +#define MSR_DDSR_MASK 0x00000002 +#define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB) +#define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK) +#define MSR_DCTS_MSB 0 +#define MSR_DCTS_LSB 0 +#define MSR_DCTS_MASK 0x00000001 +#define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB) +#define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK) + +#define SCR_ADDRESS 0x0000001c +#define SCR_OFFSET 0x0000001c +#define SCR_SCR_MSB 7 +#define SCR_SCR_LSB 0 +#define SCR_SCR_MASK 0x000000ff +#define SCR_SCR_GET(x) (((x) & SCR_SCR_MASK) >> SCR_SCR_LSB) +#define SCR_SCR_SET(x) (((x) << SCR_SCR_LSB) & SCR_SCR_MASK) + +#define SRBR_ADDRESS 0x00000020 +#define SRBR_OFFSET 0x00000020 +#define SRBR_SRBR_MSB 7 +#define SRBR_SRBR_LSB 0 +#define SRBR_SRBR_MASK 0x000000ff +#define SRBR_SRBR_GET(x) (((x) & SRBR_SRBR_MASK) >> SRBR_SRBR_LSB) +#define SRBR_SRBR_SET(x) (((x) << SRBR_SRBR_LSB) & SRBR_SRBR_MASK) + +#define SIIR_ADDRESS 0x00000028 +#define SIIR_OFFSET 0x00000028 +#define SIIR_SIIR_MSB 7 +#define SIIR_SIIR_LSB 0 +#define SIIR_SIIR_MASK 0x000000ff +#define SIIR_SIIR_GET(x) (((x) & SIIR_SIIR_MASK) >> SIIR_SIIR_LSB) +#define SIIR_SIIR_SET(x) (((x) << SIIR_SIIR_LSB) & SIIR_SIIR_MASK) + +#define MWR_ADDRESS 0x0000002c +#define MWR_OFFSET 0x0000002c +#define MWR_MWR_MSB 31 +#define MWR_MWR_LSB 0 +#define MWR_MWR_MASK 0xffffffff +#define MWR_MWR_GET(x) (((x) & MWR_MWR_MASK) >> MWR_MWR_LSB) +#define MWR_MWR_SET(x) (((x) << MWR_MWR_LSB) & MWR_MWR_MASK) + +#define SLSR_ADDRESS 0x00000034 +#define SLSR_OFFSET 0x00000034 +#define SLSR_SLSR_MSB 7 +#define SLSR_SLSR_LSB 0 +#define SLSR_SLSR_MASK 0x000000ff +#define SLSR_SLSR_GET(x) (((x) & SLSR_SLSR_MASK) >> SLSR_SLSR_LSB) +#define SLSR_SLSR_SET(x) (((x) << SLSR_SLSR_LSB) & SLSR_SLSR_MASK) + +#define SMSR_ADDRESS 0x00000038 +#define SMSR_OFFSET 0x00000038 +#define SMSR_SMSR_MSB 7 +#define SMSR_SMSR_LSB 0 +#define SMSR_SMSR_MASK 0x000000ff +#define SMSR_SMSR_GET(x) (((x) & SMSR_SMSR_MASK) >> SMSR_SMSR_LSB) +#define SMSR_SMSR_SET(x) (((x) << SMSR_SMSR_LSB) & SMSR_SMSR_MASK) + +#define MRR_ADDRESS 0x0000003c +#define MRR_OFFSET 0x0000003c +#define MRR_MRR_MSB 31 +#define MRR_MRR_LSB 0 +#define MRR_MRR_MASK 0xffffffff +#define MRR_MRR_GET(x) (((x) & MRR_MRR_MASK) >> MRR_MRR_LSB) +#define MRR_MRR_SET(x) (((x) << MRR_MRR_LSB) & MRR_MRR_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct uart_reg_reg_s { + volatile unsigned int rbr; + volatile unsigned int dlh; + volatile unsigned int iir; + volatile unsigned int lcr; + volatile unsigned int mcr; + volatile unsigned int lsr; + volatile unsigned int msr; + volatile unsigned int scr; + volatile unsigned int srbr; + unsigned char pad0[4]; /* pad to 0x28 */ + volatile unsigned int siir; + volatile unsigned int mwr; + unsigned char pad1[4]; /* pad to 0x34 */ + volatile unsigned int slsr; + volatile unsigned int smsr; + volatile unsigned int mrr; +} uart_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _UART_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/vmc_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/vmc_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k/vmc_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/vmc_reg.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,99 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _VMC_REG_REG_H_ +#define _VMC_REG_REG_H_ + +#define MC_TCAM_VALID_ADDRESS 0x00000000 +#define MC_TCAM_VALID_OFFSET 0x00000000 +#define MC_TCAM_VALID_BIT_MSB 0 +#define MC_TCAM_VALID_BIT_LSB 0 +#define MC_TCAM_VALID_BIT_MASK 0x00000001 +#define MC_TCAM_VALID_BIT_GET(x) (((x) & MC_TCAM_VALID_BIT_MASK) >> MC_TCAM_VALID_BIT_LSB) +#define MC_TCAM_VALID_BIT_SET(x) (((x) << MC_TCAM_VALID_BIT_LSB) & MC_TCAM_VALID_BIT_MASK) + +#define MC_TCAM_MASK_ADDRESS 0x00000080 +#define MC_TCAM_MASK_OFFSET 0x00000080 +#define MC_TCAM_MASK_SIZE_MSB 2 +#define MC_TCAM_MASK_SIZE_LSB 0 +#define MC_TCAM_MASK_SIZE_MASK 0x00000007 +#define MC_TCAM_MASK_SIZE_GET(x) (((x) & MC_TCAM_MASK_SIZE_MASK) >> MC_TCAM_MASK_SIZE_LSB) +#define MC_TCAM_MASK_SIZE_SET(x) (((x) << MC_TCAM_MASK_SIZE_LSB) & MC_TCAM_MASK_SIZE_MASK) + +#define MC_TCAM_COMPARE_ADDRESS 0x00000100 +#define MC_TCAM_COMPARE_OFFSET 0x00000100 +#define MC_TCAM_COMPARE_KEY_MSB 21 +#define MC_TCAM_COMPARE_KEY_LSB 5 +#define MC_TCAM_COMPARE_KEY_MASK 0x003fffe0 +#define MC_TCAM_COMPARE_KEY_GET(x) (((x) & MC_TCAM_COMPARE_KEY_MASK) >> MC_TCAM_COMPARE_KEY_LSB) +#define MC_TCAM_COMPARE_KEY_SET(x) (((x) << MC_TCAM_COMPARE_KEY_LSB) & MC_TCAM_COMPARE_KEY_MASK) + +#define MC_TCAM_TARGET_ADDRESS 0x00000180 +#define MC_TCAM_TARGET_OFFSET 0x00000180 +#define MC_TCAM_TARGET_ADDR_MSB 21 +#define MC_TCAM_TARGET_ADDR_LSB 5 +#define MC_TCAM_TARGET_ADDR_MASK 0x003fffe0 +#define MC_TCAM_TARGET_ADDR_GET(x) (((x) & MC_TCAM_TARGET_ADDR_MASK) >> MC_TCAM_TARGET_ADDR_LSB) +#define MC_TCAM_TARGET_ADDR_SET(x) (((x) << MC_TCAM_TARGET_ADDR_LSB) & MC_TCAM_TARGET_ADDR_MASK) + +#define ADDR_ERROR_CONTROL_ADDRESS 0x00000200 +#define ADDR_ERROR_CONTROL_OFFSET 0x00000200 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) +#define ADDR_ERROR_CONTROL_ENABLE_MSB 0 +#define ADDR_ERROR_CONTROL_ENABLE_LSB 0 +#define ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001 +#define ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_ENABLE_LSB) +#define ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_ENABLE_LSB) & ADDR_ERROR_CONTROL_ENABLE_MASK) + +#define ADDR_ERROR_STATUS_ADDRESS 0x00000204 +#define ADDR_ERROR_STATUS_OFFSET 0x00000204 +#define ADDR_ERROR_STATUS_WRITE_MSB 25 +#define ADDR_ERROR_STATUS_WRITE_LSB 25 +#define ADDR_ERROR_STATUS_WRITE_MASK 0x02000000 +#define ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & ADDR_ERROR_STATUS_WRITE_MASK) >> ADDR_ERROR_STATUS_WRITE_LSB) +#define ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << ADDR_ERROR_STATUS_WRITE_LSB) & ADDR_ERROR_STATUS_WRITE_MASK) +#define ADDR_ERROR_STATUS_ADDRESS_MSB 24 +#define ADDR_ERROR_STATUS_ADDRESS_LSB 0 +#define ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff +#define ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & ADDR_ERROR_STATUS_ADDRESS_MASK) >> ADDR_ERROR_STATUS_ADDRESS_LSB) +#define ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << ADDR_ERROR_STATUS_ADDRESS_LSB) & ADDR_ERROR_STATUS_ADDRESS_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct vmc_reg_reg_s { + volatile unsigned int mc_tcam_valid[32]; + volatile unsigned int mc_tcam_mask[32]; + volatile unsigned int mc_tcam_compare[32]; + volatile unsigned int mc_tcam_target[32]; + volatile unsigned int addr_error_control; + volatile unsigned int addr_error_status; +} vmc_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _VMC_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/wireless_ext.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/wireless_ext.c --- linux-2.6.26/drivers/net/wireless/ath6k/wireless_ext.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/wireless_ext.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,2077 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#include "ar6000_drv.h" + +static A_UINT8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; +static void ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi); +extern unsigned int wmitimeout; +extern A_WAITQUEUE_HEAD arEvent; + + +#if WIRELESS_EXT > 14 +/* + * Encode a WPA or RSN information element as a custom + * element using the hostap format. + */ +static u_int +encode_ie(void *buf, size_t bufsize, + const u_int8_t *ie, size_t ielen, + const char *leader, size_t leader_len) +{ + u_int8_t *p; + int i; + + if (bufsize < leader_len) + return 0; + p = buf; + memcpy(p, leader, leader_len); + bufsize -= leader_len; + p += leader_len; + for (i = 0; i < ielen && bufsize > 2; i++) + { + p += sprintf(p, "%02x", ie[i]); + bufsize -= 2; + } + return (i == ielen ? p - (u_int8_t *)buf : 0); +} +#endif /* WIRELESS_EXT > 14 */ + +void +ar6000_scan_node(void *arg, bss_t *ni) +{ + struct iw_event iwe; +#if WIRELESS_EXT > 14 + char buf[256]; +#endif + struct ar_giwscan_param *param; + A_CHAR *current_ev; + A_CHAR *end_buf; + struct ieee80211_common_ie *cie; + A_CHAR *current_val; + A_INT32 j; + A_UINT32 rate_len, data_len = 0; + + param = (struct ar_giwscan_param *)arg; + + current_ev = param->current_ev; + end_buf = param->end_buf; + + cie = &ni->ni_cie; + + if ((end_buf - current_ev) > IW_EV_ADDR_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWAP; + iwe.u.ap_addr.sa_family = ARPHRD_ETHER; + A_MEMCPY(iwe.u.ap_addr.sa_data, ni->ni_macaddr, 6); + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + IW_EV_ADDR_LEN); + } + param->bytes_needed += IW_EV_ADDR_LEN; + + data_len = cie->ie_ssid[1] + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWESSID; + iwe.u.data.flags = 1; + iwe.u.data.length = cie->ie_ssid[1]; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + &cie->ie_ssid[2]); + } + param->bytes_needed += data_len; + + if (cie->ie_capInfo & (IEEE80211_CAPINFO_ESS|IEEE80211_CAPINFO_IBSS)) { + if ((end_buf - current_ev) > IW_EV_UINT_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWMODE; + iwe.u.mode = cie->ie_capInfo & IEEE80211_CAPINFO_ESS ? + IW_MODE_MASTER : IW_MODE_ADHOC; + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + IW_EV_UINT_LEN); + } + param->bytes_needed += IW_EV_UINT_LEN; + } + + if ((end_buf - current_ev) > IW_EV_FREQ_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWFREQ; + iwe.u.freq.m = cie->ie_chan * 100000; + iwe.u.freq.e = 1; + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + IW_EV_FREQ_LEN); + } + param->bytes_needed += IW_EV_FREQ_LEN; + + if ((end_buf - current_ev) > IW_EV_QUAL_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVQUAL; + ar6000_set_quality(&iwe.u.qual, ni->ni_snr); + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + IW_EV_QUAL_LEN); + } + param->bytes_needed += IW_EV_QUAL_LEN; + + if ((end_buf - current_ev) > IW_EV_POINT_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWENCODE; + if (cie->ie_capInfo & IEEE80211_CAPINFO_PRIVACY) { + iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; + } else { + iwe.u.data.flags = IW_ENCODE_DISABLED; + } + iwe.u.data.length = 0; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, ""); + } + param->bytes_needed += IW_EV_POINT_LEN; + + /* supported bit rate */ + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWRATE; + iwe.u.bitrate.fixed = 0; + iwe.u.bitrate.disabled = 0; + iwe.u.bitrate.value = 0; + current_val = current_ev + IW_EV_LCP_LEN; + param->bytes_needed += IW_EV_LCP_LEN; + + if (cie->ie_rates != NULL) { + rate_len = cie->ie_rates[1]; + data_len = (rate_len * (IW_EV_PARAM_LEN - IW_EV_LCP_LEN)); + if ((end_buf - current_ev) > data_len) + { + for (j = 0; j < rate_len; j++) { + unsigned char val; + val = cie->ie_rates[2 + j]; + iwe.u.bitrate.value = + (val >= 0x80)? ((val - 0x80) * 500000): (val * 500000); + current_val = iwe_stream_add_value( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, + current_val, + end_buf, + &iwe, + IW_EV_PARAM_LEN); + } + } + param->bytes_needed += data_len; + } + + if (cie->ie_xrates != NULL) { + rate_len = cie->ie_xrates[1]; + data_len = (rate_len * (IW_EV_PARAM_LEN - IW_EV_LCP_LEN)); + if ((end_buf - current_ev) > data_len) + { + for (j = 0; j < rate_len; j++) { + unsigned char val; + val = cie->ie_xrates[2 + j]; + iwe.u.bitrate.value = + (val >= 0x80)? ((val - 0x80) * 500000): (val * 500000); + current_val = iwe_stream_add_value( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, + current_val, + end_buf, + &iwe, + IW_EV_PARAM_LEN); + } + } + param->bytes_needed += data_len; + } + /* remove fixed header if no rates were added */ + if ((current_val - current_ev) > IW_EV_LCP_LEN) + current_ev = current_val; + +#if WIRELESS_EXT >= 18 + /* IE */ + if (cie->ie_wpa != NULL) { + data_len = cie->ie_wpa[1] + 2 + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVGENIE; + iwe.u.data.length = cie->ie_wpa[1] + 2; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, cie->ie_wpa); + } + param->bytes_needed += data_len; + } + + if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) { + data_len = cie->ie_rsn[1] + 2 + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVGENIE; + iwe.u.data.length = cie->ie_rsn[1] + 2; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, cie->ie_rsn); + } + param->bytes_needed += data_len; + } + +#endif /* WIRELESS_EXT >= 18 */ + + if ((end_buf - current_ev) > IW_EV_CHAR_LEN) + { + /* protocol */ + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWNAME; +#define CHAN_IS_11A(x) (!((x >= 2412) && (x <= 2484))) + if (CHAN_IS_11A(cie->ie_chan)) { + /* 11a */ + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11a"); + } else if ((cie->ie_erp) || (cie->ie_xrates)) { + /* 11g */ + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11g"); + } else { + /* 11b */ + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11b"); + } + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, IW_EV_CHAR_LEN); + } + param->bytes_needed += IW_EV_CHAR_LEN; + +#if WIRELESS_EXT > 14 + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = snprintf(buf, sizeof(buf), "bcn_int=%d", cie->ie_beaconInt); + data_len = iwe.u.data.length + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + param->bytes_needed += data_len; + +#if WIRELESS_EXT < 18 + if (cie->ie_wpa != NULL) { + static const char wpa_leader[] = "wpa_ie="; + data_len = (sizeof(wpa_leader) - 1) + ((cie->ie_wpa[1]+2) * 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wpa, + cie->ie_wpa[1]+2, + wpa_leader, sizeof(wpa_leader)-1); + + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + } + param->bytes_needed += data_len; + } + + if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) { + static const char rsn_leader[] = "rsn_ie="; + data_len = (sizeof(rsn_leader) - 1) + ((cie->ie_rsn[1]+2) * 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_rsn, + cie->ie_rsn[1]+2, + rsn_leader, sizeof(rsn_leader)-1); + + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + } + param->bytes_needed += data_len; + } +#endif /* WIRELESS_EXT < 18 */ + + if (cie->ie_wmm != NULL) { + static const char wmm_leader[] = "wmm_ie="; + data_len = (sizeof(wmm_leader) - 1) + ((cie->ie_wmm[1]+2) * 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wmm, + cie->ie_wmm[1]+2, + wmm_leader, sizeof(wmm_leader)-1); + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + } + param->bytes_needed += data_len; + } + + if (cie->ie_ath != NULL) { + static const char ath_leader[] = "ath_ie="; + data_len = (sizeof(ath_leader) - 1) + ((cie->ie_ath[1]+2) * 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_ath, + cie->ie_ath[1]+2, + ath_leader, sizeof(ath_leader)-1); + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + } + param->bytes_needed += data_len; + } + +#endif /* WIRELESS_EXT > 14 */ + +#if WIRELESS_EXT >= 18 + if (cie->ie_wsc != NULL) { + data_len = (cie->ie_wsc[1] + 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVGENIE; + iwe.u.data.length = cie->ie_wsc[1] + 2; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, cie->ie_wsc); + } + param->bytes_needed += data_len; + } +#endif /* WIRELESS_EXT >= 18 */ + + param->current_ev = current_ev; +} + +int +ar6000_ioctl_giwscan(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + struct ar_giwscan_param param; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + param.current_ev = extra; + param.end_buf = extra + data->length; + param.bytes_needed = 0; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param.info = info; +#endif + + /* Translate data to WE format */ + wmi_iterate_nodes(ar->arWmi, ar6000_scan_node, ¶m); + + /* check if bytes needed is greater than bytes consumed */ + if (param.bytes_needed > (param.current_ev - extra)) + { + /* Request one byte more than needed, because when "data->length" equals bytes_needed, + it is not possible to add the last event data as all iwe_stream_add_xxxxx() functions + checks whether (cur_ptr + ev_len) < end_ptr, due to this one more retry would happen*/ + data->length = param.bytes_needed + 1; + + return -E2BIG; + } + + return 0; +} + +extern int reconnect_flag; +/* SIOCSIWESSID */ +static int +ar6000_ioctl_siwessid(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *ssid) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_STATUS status; + A_UINT8 arNetworkType; + A_UINT8 prevMode = ar->arNetworkType; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + +#if defined(WIRELESS_EXT) + if (WIRELESS_EXT >= 20) { + data->length += 1; + } +#endif + + /* + * iwconfig passes a null terminated string with length including this + * so we need to account for this + */ + if (data->flags && (!data->length || (data->length == 1) || + ((data->length - 1) > sizeof(ar->arSsid)))) + { + /* + * ssid is invalid + */ + return -EINVAL; + } + + if (ar->arNextMode == AP_NETWORK) { + /* SSID change for AP network - Will take effect on commit */ + if(A_MEMCMP(ar->arSsid,ssid,32) != 0) { + ar->arSsidLen = data->length - 1; + A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen); + ar->ap_profile_flag = 1; /* There is a change in profile */ + } + return 0; + } else if(ar->arNetworkType == AP_NETWORK) { + A_UINT8 ctr; + struct sk_buff *skb; + + /* We are switching from AP to STA | IBSS mode, cleanup the AP state */ + for (ctr=0; ctr < AP_MAX_NUM_STA; ctr++) { + remove_sta(ar, ar->sta_list[ctr].mac, 0); + } + A_MUTEX_LOCK(&ar->mcastpsqLock); + while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) { + skb = A_NETBUF_DEQUEUE(&ar->mcastpsq); + A_NETBUF_FREE(skb); + } + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + } + + /* Added for bug 25178, return an IOCTL error instead of target returning + Illegal parameter error when either the BSSID or channel is missing + and we cannot scan during connect. + */ + if (data->flags) { + if (ar->arSkipScan == TRUE && + (ar->arChannelHint == 0 || + (!ar->arReqBssid[0] && !ar->arReqBssid[1] && !ar->arReqBssid[2] && + !ar->arReqBssid[3] && !ar->arReqBssid[4] && !ar->arReqBssid[5]))) + { + return -EINVAL; + } + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (ar->arTxPending[wmi_get_control_ep(ar->arWmi)]) { + /* + * sleep until the command queue drains + */ + wait_event_interruptible_timeout(arEvent, + ar->arTxPending[wmi_get_control_ep(ar->arWmi)] == 0, wmitimeout * HZ); + if (signal_pending(current)) { + return -EINTR; + } + } + + if (!data->flags) { + arNetworkType = ar->arNetworkType; + ar6000_init_profile_info(ar); + ar->arNetworkType = arNetworkType; + } + + /* Update the arNetworkType */ + ar->arNetworkType = ar->arNextMode; + + + if ((prevMode != AP_NETWORK) && ((ar->arSsidLen) || (!data->flags))) + { + if ((!data->flags) || + (A_MEMCMP(ar->arSsid, ssid, ar->arSsidLen) != 0) || + (ar->arSsidLen != (data->length - 1))) + { + /* + * SSID set previously or essid off has been issued. + * + * Disconnect Command is issued in two cases after wmi is ready + * (1) ssid is different from the previous setting + * (2) essid off has been issued + * + */ + if (ar->arWmiReady == TRUE) { + reconnect_flag = 0; + status = wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0); + status = wmi_disconnect_cmd(ar->arWmi); + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = 0; + if (ar->arSkipScan == FALSE) { + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + } + if (!data->flags) { + up(&ar->arSem); + return 0; + } + } else { + up(&ar->arSem); + } + } + else + { + /* + * SSID is same, so we assume profile hasn't changed. + * If the interface is up and wmi is ready, we issue + * a reconnect cmd. Issue a reconnect only we are already + * connected. + */ + if((ar->arConnected == TRUE) && (ar->arWmiReady == TRUE)) + { + reconnect_flag = TRUE; + status = wmi_reconnect_cmd(ar->arWmi,ar->arReqBssid, + ar->arChannelHint); + up(&ar->arSem); + if (status != A_OK) { + return -EIO; + } + return 0; + } + else{ + /* + * Dont return if connect is pending. + */ + if(!(ar->arConnectPending)) { + up(&ar->arSem); + return 0; + } + } + } + } + + ar->arSsidLen = data->length - 1; + A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen); + + /* The ssid length check prevents second "essid off" from the user, + to be treated as a connect cmd. The second "essid off" is ignored. + */ + if((ar->arWmiReady == TRUE) && (ar->arSsidLen > 0) ) + { + if (SHARED_AUTH == ar->arDot11AuthMode) { + ar6000_install_static_wep_keys(ar); + } + AR_DEBUG_PRINTF("Connect called with authmode %d dot11 auth %d"\ + " PW crypto %d PW crypto Len %d GRP crypto %d"\ + " GRP crypto Len %d\n", + ar->arAuthMode, ar->arDot11AuthMode, + ar->arPairwiseCrypto, ar->arPairwiseCryptoLen, + ar->arGroupCrypto, ar->arGroupCryptoLen); + reconnect_flag = 0; + status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType, + ar->arDot11AuthMode, ar->arAuthMode, + ar->arPairwiseCrypto, ar->arPairwiseCryptoLen, + ar->arGroupCrypto,ar->arGroupCryptoLen, + ar->arSsidLen, ar->arSsid, + ar->arReqBssid, ar->arChannelHint, + ar->arConnectCtrlFlags | CONNECT_IGNORE_WPAx_GROUP_CIPHER); + + + up(&ar->arSem); + + if (status != A_OK) { + return -EIO; + } + ar->arConnectPending = TRUE; + }else{ + up(&ar->arSem); + } + return 0; +} + +/* SIOCGIWESSID */ +static int +ar6000_ioctl_giwessid(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *essid) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (!ar->arSsidLen) { + return -EINVAL; + } + + data->flags = 1; + data->length = ar->arSsidLen; + A_MEMCPY(essid, ar->arSsid, ar->arSsidLen); + + return 0; +} + + +void ar6000_install_static_wep_keys(AR_SOFTC_T *ar) +{ + A_UINT8 index; + A_UINT8 keyUsage; + + for (index = WMI_MIN_KEY_INDEX; index <= WMI_MAX_KEY_INDEX; index++) { + if (ar->arWepKeyList[index].arKeyLen) { + keyUsage = GROUP_USAGE; + if (index == ar->arDefTxKeyIndex) { + keyUsage |= TX_USAGE; + } + wmi_addKey_cmd(ar->arWmi, + index, + WEP_CRYPT, + keyUsage, + ar->arWepKeyList[index].arKeyLen, + NULL, + ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL, NULL, + NO_SYNC_WMIFLAG); + } + } +} + +/* + * SIOCSIWRATE + */ +int +ar6000_ioctl_siwrate(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_UINT32 kbps; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (rrq->fixed) { + kbps = rrq->value / 1000; /* rrq->value is in bps */ + } else { + kbps = -1; /* -1 indicates auto rate */ + } + if(kbps != -1 && wmi_validate_bitrate(ar->arWmi, kbps) == A_EINVAL) + { + AR_DEBUG_PRINTF("BitRate is not Valid %d\n", kbps); + return -EINVAL; + } + ar->arBitRate = kbps; + if(ar->arWmiReady == TRUE) + { + if (wmi_set_bitrate_cmd(ar->arWmi, kbps, -1, -1) != A_OK) { + return -EINVAL; + } + } + return 0; +} + +/* + * SIOCGIWRATE + */ +int +ar6000_ioctl_giwrate(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + int ret = 0; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if(ar->arWmiReady == TRUE) + { + ar->arBitRate = 0xFFFF; + if (wmi_get_bitrate_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + wait_event_interruptible_timeout(arEvent, ar->arBitRate != 0xFFFF, wmitimeout * HZ); + if (signal_pending(current)) { + ret = -EINTR; + } + } + /* If the interface is down or wmi is not ready or the target is not + connected - return the value stored in the device structure */ + if (!ret) { + if (ar->arBitRate == -1) { + rrq->fixed = TRUE; + rrq->value = 0; + } else { + rrq->value = ar->arBitRate * 1000; + } + } + + up(&ar->arSem); + + return ret; +} + +/* + * SIOCSIWTXPOW + */ +static int +ar6000_ioctl_siwtxpow(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_UINT8 dbM; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (rrq->disabled) { + return -EOPNOTSUPP; + } + + if (rrq->fixed) { + if (rrq->flags != IW_TXPOW_DBM) { + return -EOPNOTSUPP; + } + ar->arTxPwr= dbM = rrq->value; + ar->arTxPwrSet = TRUE; + } else { + ar->arTxPwr = dbM = 0; + ar->arTxPwrSet = FALSE; + } + if(ar->arWmiReady == TRUE) + { + AR_DEBUG_PRINTF("Set tx pwr cmd %d dbM\n", dbM); + wmi_set_txPwr_cmd(ar->arWmi, dbM); + } + return 0; +} + +/* + * SIOCGIWTXPOW + */ +int +ar6000_ioctl_giwtxpow(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + int ret = 0; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if((ar->arWmiReady == TRUE) && (ar->arConnected == TRUE)) + { + ar->arTxPwr = 0; + + if (wmi_get_txPwr_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->arTxPwr != 0, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + } + /* If the interace is down or wmi is not ready or target is not connected + then return value stored in the device structure */ + + if (!ret) { + if (ar->arTxPwrSet == TRUE) { + rrq->fixed = TRUE; + } + rrq->value = ar->arTxPwr; + rrq->flags = IW_TXPOW_DBM; + // + // IWLIST need this flag to get TxPower + // + rrq->disabled = 0; + } + + up(&ar->arSem); + + return ret; +} + +/* + * SIOCSIWRETRY + * since iwconfig only provides us with one max retry value, we use it + * to apply to data frames of the BE traffic class. + */ +static int +ar6000_ioctl_siwretry(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (rrq->disabled) { + return -EOPNOTSUPP; + } + + if ((rrq->flags & IW_RETRY_TYPE) != IW_RETRY_LIMIT) { + return -EOPNOTSUPP; + } + + if ( !(rrq->value >= WMI_MIN_RETRIES) || !(rrq->value <= WMI_MAX_RETRIES)) { + return - EINVAL; + } + if(ar->arWmiReady == TRUE) + { + if (wmi_set_retry_limits_cmd(ar->arWmi, DATA_FRAMETYPE, WMM_AC_BE, + rrq->value, 0) != A_OK){ + return -EINVAL; + } + } + ar->arMaxRetries = rrq->value; + return 0; +} + +/* + * SIOCGIWRETRY + */ +static int +ar6000_ioctl_giwretry(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + rrq->disabled = 0; + switch (rrq->flags & IW_RETRY_TYPE) { + case IW_RETRY_LIFETIME: + return -EOPNOTSUPP; + break; + case IW_RETRY_LIMIT: + rrq->flags = IW_RETRY_LIMIT; + switch (rrq->flags & IW_RETRY_MODIFIER) { + case IW_RETRY_MIN: + rrq->flags |= IW_RETRY_MIN; + rrq->value = WMI_MIN_RETRIES; + break; + case IW_RETRY_MAX: + rrq->flags |= IW_RETRY_MAX; + rrq->value = ar->arMaxRetries; + break; + } + break; + } + return 0; +} + +/* + * SIOCSIWENCODE + */ +static int +ar6000_ioctl_siwencode(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, char *keybuf) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + int index; + A_INT32 auth = ar->arDot11AuthMode; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if(ar->arNextMode != AP_NETWORK) { + /* + * Static WEP Keys should be configured before setting the SSID + */ + if (ar->arSsidLen) { + return -EIO; + } + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + index = erq->flags & IW_ENCODE_INDEX; + + if (index && (((index - 1) < WMI_MIN_KEY_INDEX) || + ((index - 1) > WMI_MAX_KEY_INDEX))) + { + return -EIO; + } + + if (erq->flags & IW_ENCODE_DISABLED) { + /* + * Encryption disabled + */ + if (index) { + /* + * If key index was specified then clear the specified key + */ + index--; + A_MEMZERO(ar->arWepKeyList[index].arKey, + sizeof(ar->arWepKeyList[index].arKey)); + ar->arWepKeyList[index].arKeyLen = 0; + } + ar->arDot11AuthMode = OPEN_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arGroupCrypto = NONE_CRYPT; + ar->arAuthMode = NONE_AUTH; + } else { + /* + * Enabling WEP encryption + */ + if (index) { + index--; /* keyindex is off base 1 in iwconfig */ + } + + if (erq->flags & IW_ENCODE_OPEN) { + auth = OPEN_AUTH; + } else if (erq->flags & IW_ENCODE_RESTRICTED) { + auth = SHARED_AUTH; + } + + if (erq->length) { + if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(erq->length)) { + return -EIO; + } + + A_MEMZERO(ar->arWepKeyList[index].arKey, + sizeof(ar->arWepKeyList[index].arKey)); + A_MEMCPY(ar->arWepKeyList[index].arKey, keybuf, erq->length); + ar->arWepKeyList[index].arKeyLen = erq->length; + } else { + if (ar->arWepKeyList[index].arKeyLen == 0) { + return -EIO; + } + ar->arDefTxKeyIndex = index; + } + + ar->arPairwiseCrypto = WEP_CRYPT; + ar->arGroupCrypto = WEP_CRYPT; + ar->arDot11AuthMode = auth; + ar->arAuthMode = NONE_AUTH; + } + + if(ar->arNextMode != AP_NETWORK) { + /* + * profile has changed. Erase ssid to signal change + */ + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + } + ar->ap_profile_flag = 1; /* There is a change in profile */ + return 0; +} + +static int +ar6000_ioctl_giwencode(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, char *key) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_UINT8 keyIndex; + struct ar_wep_key *wk; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arPairwiseCrypto == NONE_CRYPT) { + erq->length = 0; + erq->flags = IW_ENCODE_DISABLED; + } else { + /* get the keyIndex */ + keyIndex = erq->flags & IW_ENCODE_INDEX; + if (0 == keyIndex) { + keyIndex = ar->arDefTxKeyIndex; + } else if ((keyIndex - 1 < WMI_MIN_KEY_INDEX) || + (keyIndex - 1 > WMI_MAX_KEY_INDEX)) + { + keyIndex = WMI_MIN_KEY_INDEX; + } else { + keyIndex--; + } + erq->flags = keyIndex + 1; + erq->flags |= IW_ENCODE_ENABLED; + wk = &ar->arWepKeyList[keyIndex]; + if (erq->length > wk->arKeyLen) { + erq->length = wk->arKeyLen; + } + if (wk->arKeyLen) { + A_MEMCPY(key, wk->arKey, erq->length); + } + if (ar->arDot11AuthMode == OPEN_AUTH) { + erq->flags |= IW_ENCODE_OPEN; + } else if (ar->arDot11AuthMode == SHARED_AUTH) { + erq->flags |= IW_ENCODE_RESTRICTED; + } + } + + return 0; +} + +static int ar6000_ioctl_siwpower(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ +#if defined(WIRELESS_EXT) && WIRELESS_EXT > 20 + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_POWER_MODE power_mode; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (wrqu->power.disabled) + power_mode = MAX_PERF_POWER; + else + power_mode = REC_POWER; + + if (wmi_powermode_cmd(ar->arWmi, power_mode) < 0) + return -EIO; +#endif + return 0; +} + +static int ar6000_ioctl_giwpower(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ +#if defined(WIRELESS_EXT) && WIRELESS_EXT > 20 + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + return wmi_get_power_mode_cmd(ar->arWmi); +#else + return 0; +#endif +} + +static int ar6000_ioctl_siwgenie(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *dwrq, + char *extra) +{ + /* The target does that for us */ + return 0; +} + +static int ar6000_ioctl_giwgenie(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *dwrq, + char *extra) +{ + return 0; +} + +static int ar6000_ioctl_siwauth(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *param, + char *extra) +{ +#if defined(WIRELESS_EXT) && WIRELESS_EXT > 20 + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + int reset = 0; + + switch (param->flags & IW_AUTH_INDEX) { + case IW_AUTH_WPA_VERSION: + if (param->value & IW_AUTH_WPA_VERSION_DISABLED) { + ar->arAuthMode = NONE_AUTH; + } + if (param->value & IW_AUTH_WPA_VERSION_WPA) { + ar->arAuthMode = WPA_AUTH; + } + if (param->value & IW_AUTH_WPA_VERSION_WPA2) { + ar->arAuthMode = WPA2_AUTH; + } + + reset = 1; + break; + case IW_AUTH_CIPHER_PAIRWISE: + if (param->value & IW_AUTH_CIPHER_NONE) { + ar->arPairwiseCrypto = NONE_CRYPT; + } + if (param->value & IW_AUTH_CIPHER_WEP40) { + ar->arPairwiseCrypto = WEP_CRYPT; + } + if (param->value & IW_AUTH_CIPHER_TKIP) { + ar->arPairwiseCrypto = TKIP_CRYPT; + } + if (param->value & IW_AUTH_CIPHER_CCMP) { + ar->arPairwiseCrypto = AES_CRYPT; + } + + reset = 1; + break; + case IW_AUTH_CIPHER_GROUP: + if (param->value & IW_AUTH_CIPHER_NONE) { + ar->arGroupCrypto = NONE_CRYPT; + } + if (param->value & IW_AUTH_CIPHER_WEP40) { + ar->arGroupCrypto = WEP_CRYPT; + } + if (param->value & IW_AUTH_CIPHER_TKIP) { + ar->arGroupCrypto = TKIP_CRYPT; + } + if (param->value & IW_AUTH_CIPHER_CCMP) { + ar->arGroupCrypto = AES_CRYPT; + } + + reset = 1; + break; + case IW_AUTH_KEY_MGMT: + if (param->value & IW_AUTH_KEY_MGMT_PSK) { + if (ar->arAuthMode == WPA_AUTH) { + ar->arAuthMode = WPA_PSK_AUTH; + } else if (ar->arAuthMode == WPA2_AUTH) { + ar->arAuthMode = WPA2_PSK_AUTH; + } + + reset = 1; + } + break; + + case IW_AUTH_TKIP_COUNTERMEASURES: + if (ar->arWmiReady == FALSE) { + return -EIO; + } + wmi_set_tkip_countermeasures_cmd(ar->arWmi, param->value); + break; + + case IW_AUTH_DROP_UNENCRYPTED: + break; + + case IW_AUTH_80211_AUTH_ALG: + if (param->value & IW_AUTH_ALG_OPEN_SYSTEM) { + ar->arDot11AuthMode = OPEN_AUTH; + } + if (param->value & IW_AUTH_ALG_SHARED_KEY) { + ar->arDot11AuthMode = SHARED_AUTH; + } + if (param->value & IW_AUTH_ALG_LEAP) { + ar->arDot11AuthMode = LEAP_AUTH; + ar->arPairwiseCrypto = WEP_CRYPT; + ar->arGroupCrypto = WEP_CRYPT; + } + + reset = 1; + break; + + case IW_AUTH_WPA_ENABLED: + reset = 1; + break; + + case IW_AUTH_RX_UNENCRYPTED_EAPOL: + break; + + case IW_AUTH_PRIVACY_INVOKED: + break; + + default: + printk("%s(): Unknown flag 0x%x\n", __FUNCTION__, param->flags); + return -EOPNOTSUPP; + } + + if (reset) + memset(ar->arSsid, 0, sizeof(ar->arSsid)); +#endif + return 0; +} + +static int ar6000_ioctl_giwauth(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *dwrq, + char *extra) +{ + return 0; +} + +static int ar6000_ioctl_siwencodeext(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, + char *extra) +{ +#if defined(WIRELESS_EXT) && WIRELESS_EXT > 20 + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + struct iw_point *encoding = &wrqu->encoding; + struct iw_encode_ext *ext = (struct iw_encode_ext *)extra; + int alg = ext->alg, idx; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + /* Determine and validate the key index */ + idx = (encoding->flags & IW_ENCODE_INDEX) - 1; + if (idx) { + if (idx < 0 || idx > 3) + return -EINVAL; + } + + if ((alg == IW_ENCODE_ALG_TKIP) || (alg == IW_ENCODE_ALG_CCMP)) { + struct ieee80211req_key ik; + KEY_USAGE key_usage; + CRYPTO_TYPE key_type = NONE_CRYPT; + int status; + +#ifdef USER_KEYS + ar->user_saved_keys.keyOk = FALSE; +#endif + + if (alg == IW_ENCODE_ALG_TKIP) { + key_type = TKIP_CRYPT; + ik.ik_type = IEEE80211_CIPHER_TKIP; + } else { + key_type = AES_CRYPT; + ik.ik_type = IEEE80211_CIPHER_AES_CCM; + } + + ik.ik_keyix = idx; + ik.ik_keylen = ext->key_len; + ik.ik_flags = IEEE80211_KEY_RECV; + if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) { + ik.ik_flags |= IEEE80211_KEY_XMIT + | IEEE80211_KEY_DEFAULT; + } + + if (ext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) { + memcpy(&ik.ik_keyrsc, ext->rx_seq, 8); + } + + memcpy(ik.ik_keydata, ext->key, ext->key_len); + +#ifdef USER_KEYS + ar->user_saved_keys.keyType = key_type; +#endif + if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) { + key_usage = GROUP_USAGE; + memset(ik.ik_macaddr, 0, ETH_ALEN); +#ifdef USER_KEYS + memcpy(&ar->user_saved_keys.bcast_ik, &ik, + sizeof(struct ieee80211req_key)); +#endif + } else { + key_usage = PAIRWISE_USAGE; + memcpy(ik.ik_macaddr, ext->addr.sa_data, ETH_ALEN); +#ifdef USER_KEYS + memcpy(&ar->user_saved_keys.ucast_ik, &ik, + sizeof(struct ieee80211req_key)); +#endif + } + + status = wmi_addKey_cmd(ar->arWmi, ik.ik_keyix, key_type, + key_usage, ik.ik_keylen, + (A_UINT8 *)&ik.ik_keyrsc, + ik.ik_keydata, + KEY_OP_INIT_VAL, ik.ik_macaddr, + SYNC_BEFORE_WMIFLAG); + + if (status < 0) + return -EIO; + +#ifdef USER_KEYS + ar->user_saved_keys.keyOk = TRUE; +#endif + + return 0; + + } else { + /* WEP falls back to SIWENCODE */ + return -EOPNOTSUPP; + } +#endif + return 0; +} + + +static int ar6000_ioctl_giwencodeext(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *dwrq, + char *extra) +{ + return 0; +} + + +/* + * SIOCGIWNAME + */ +int +ar6000_ioctl_giwname(struct net_device *dev, + struct iw_request_info *info, + char *name, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + switch (ar->arPhyCapability) { + case (WMI_11A_CAPABILITY): + strncpy(name, "AR6000 802.11a", IFNAMSIZ); + break; + case (WMI_11G_CAPABILITY): + strncpy(name, "AR6000 802.11g", IFNAMSIZ); + break; + case (WMI_11AG_CAPABILITY): + strncpy(name, "AR6000 802.11ag", IFNAMSIZ); + break; + default: + strncpy(name, "AR6000 802.11", IFNAMSIZ); + break; + } + + return 0; +} + +/* + * SIOCSIWFREQ + */ +int +ar6000_ioctl_siwfreq(struct net_device *dev, + struct iw_request_info *info, + struct iw_freq *freq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + /* + * We support limiting the channels via wmiconfig. + * + * We use this command to configure the channel hint for the connect cmd + * so it is possible the target will end up connecting to a different + * channel. + */ + if (freq->e > 1) { + return -EINVAL; + } else if (freq->e == 1) { + ar->arChannelHint = freq->m / 100000; + } else { + ar->arChannelHint = wlan_ieee2freq(freq->m); + } + + ar->ap_profile_flag = 1; /* There is a change in profile */ + + A_PRINTF("channel hint set to %d\n", ar->arChannelHint); + return 0; +} + +/* + * SIOCGIWFREQ + */ +int +ar6000_ioctl_giwfreq(struct net_device *dev, + struct iw_request_info *info, + struct iw_freq *freq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arConnected != TRUE) { + return -EINVAL; + } + if (ar->arNetworkType == AP_NETWORK) { + freq->m = ar->arChannelHint * 100000; + } else { + freq->m = ar->arBssChannel * 100000; + } + + freq->e = 1; + + return 0; +} + +/* + * SIOCSIWMODE + */ +int +ar6000_ioctl_siwmode(struct net_device *dev, + struct iw_request_info *info, + __u32 *mode, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + switch (*mode) { + case IW_MODE_INFRA: + ar->arNextMode = INFRA_NETWORK; + break; + case IW_MODE_ADHOC: + ar->arNextMode = ADHOC_NETWORK; + break; + case IW_MODE_MASTER: + ar->arNextMode = AP_NETWORK; + break; + default: + return -EINVAL; + } + + /* clear all shared parameters between AP and STA|IBSS modes when we + * switch between them. Switch between STA & IBSS modes does'nt clear + * the shared profile. This is as per the original design for switching + * between STA & IBSS. + */ + if (ar->arNetworkType == AP_NETWORK || ar->arNextMode == AP_NETWORK) { + ar->arDot11AuthMode = OPEN_AUTH; + ar->arAuthMode = NONE_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arPairwiseCryptoLen = 0; + ar->arGroupCrypto = NONE_CRYPT; + ar->arGroupCryptoLen = 0; + ar->arChannelHint = 0; + ar->arBssChannel = 0; + A_MEMZERO(ar->arBssid, sizeof(ar->arBssid)); + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = 0; + } + + /* SSID has to be cleared to trigger a profile change while switching + * between STA & IBSS modes having the same SSID + */ + if (ar->arNetworkType != ar->arNextMode) { + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + } + + return 0; +} + +/* + * SIOCGIWMODE + */ +int +ar6000_ioctl_giwmode(struct net_device *dev, + struct iw_request_info *info, + __u32 *mode, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + switch (ar->arNetworkType) { + case INFRA_NETWORK: + *mode = IW_MODE_INFRA; + break; + case ADHOC_NETWORK: + *mode = IW_MODE_ADHOC; + break; + case AP_NETWORK: + *mode = IW_MODE_MASTER; + break; + default: + return -EIO; + } + return 0; +} + +/* + * SIOCSIWSENS + */ +int +ar6000_ioctl_siwsens(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *sens, char *extra) +{ + return 0; +} + +/* + * SIOCGIWSENS + */ +int +ar6000_ioctl_giwsens(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *sens, char *extra) +{ + sens->value = 0; + sens->fixed = 1; + + return 0; +} + +/* + * SIOCGIWRANGE + */ +int +ar6000_ioctl_giwrange(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + struct iw_range *range = (struct iw_range *) extra; + int i, ret = 0; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + ar->arNumChannels = -1; + A_MEMZERO(ar->arChannelList, sizeof (ar->arChannelList)); + + if (wmi_get_channelList_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->arNumChannels != -1, wmitimeout * HZ); + + if (signal_pending(current)) { + up(&ar->arSem); + return -EINTR; + } + + data->length = sizeof(struct iw_range); + A_MEMZERO(range, sizeof(struct iw_range)); + + range->txpower_capa = 0; + + range->min_pmp = 1 * 1024; + range->max_pmp = 65535 * 1024; + range->min_pmt = 1 * 1024; + range->max_pmt = 1000 * 1024; + range->pmp_flags = IW_POWER_PERIOD; + range->pmt_flags = IW_POWER_TIMEOUT; + range->pm_capa = 0; + + range->we_version_compiled = WIRELESS_EXT; + range->we_version_source = 13; + + range->retry_capa = IW_RETRY_LIMIT; + range->retry_flags = IW_RETRY_LIMIT; + range->min_retry = 0; + range->max_retry = 255; + + range->num_frequency = range->num_channels = ar->arNumChannels; + for (i = 0; i < ar->arNumChannels; i++) { + range->freq[i].i = wlan_freq2ieee(ar->arChannelList[i]); + range->freq[i].m = ar->arChannelList[i] * 100000; + range->freq[i].e = 1; + /* + * Linux supports max of 32 channels, bail out once you + * reach the max. + */ + if (i == IW_MAX_FREQUENCIES) { + break; + } + } + + /* Max quality is max field value minus noise floor */ + range->max_qual.qual = 0xff - 161; + + /* + * In order to use dBm measurements, 'level' must be lower + * than any possible measurement (see iw_print_stats() in + * wireless tools). It's unclear how this is meant to be + * done, but setting zero in these values forces dBm and + * the actual numbers are not used. + */ + range->max_qual.level = 0; + range->max_qual.noise = 0; + + range->sensitivity = 3; + + range->max_encoding_tokens = 4; + /* XXX query driver to find out supported key sizes */ + range->num_encoding_sizes = 3; + range->encoding_size[0] = 5; /* 40-bit */ + range->encoding_size[1] = 13; /* 104-bit */ + range->encoding_size[2] = 16; /* 128-bit */ + + range->num_bitrates = 0; + + /* estimated maximum TCP throughput values (bps) */ + range->throughput = 22000000; + + range->min_rts = 0; + range->max_rts = 2347; + range->min_frag = 256; + range->max_frag = 2346; + + up(&ar->arSem); + + return ret; +} + + +/* + * SIOCSIWAP + * This ioctl is used to set the desired bssid for the connect command. + */ +int +ar6000_ioctl_siwap(struct net_device *dev, + struct iw_request_info *info, + struct sockaddr *ap_addr, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ap_addr->sa_family != ARPHRD_ETHER) { + return -EIO; + } + + if (A_MEMCMP(&ap_addr->sa_data, bcast_mac, AR6000_ETH_ADDR_LEN) == 0) { + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + } else { + A_MEMCPY(ar->arReqBssid, &ap_addr->sa_data, sizeof(ar->arReqBssid)); + } + + return 0; +} + +/* + * SIOCGIWAP + */ +int +ar6000_ioctl_giwap(struct net_device *dev, + struct iw_request_info *info, + struct sockaddr *ap_addr, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arConnected != TRUE) { + return -EINVAL; + } + + if (ar->arNetworkType == AP_NETWORK) { + return -EINVAL; + } + + A_MEMCPY(&ap_addr->sa_data, ar->arBssid, sizeof(ar->arBssid)); + ap_addr->sa_family = ARPHRD_ETHER; + + return 0; +} + +/* + * SIOCGIWAPLIST + */ +int +ar6000_ioctl_iwaplist(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + return -EIO; /* for now */ +} + +/* + * SIOCSIWSCAN + */ +int +ar6000_ioctl_siwscan(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ +#define ACT_DWELLTIME_DEFAULT 105 +#define HOME_TXDRAIN_TIME 100 +#define SCAN_INT HOME_TXDRAIN_TIME + ACT_DWELLTIME_DEFAULT + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + int ret = 0; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + /* We ask for everything from the target */ + if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != A_OK) { + printk("Couldn't set filtering\n"); + ret = -EIO; + } + +#if WIRELESS_EXT >= 18 + if (data->pointer && (data->length == sizeof(struct iw_scan_req))) + { + if ((data->flags & IW_SCAN_THIS_ESSID) == IW_SCAN_THIS_ESSID) + { + struct iw_scan_req req; + if (copy_from_user(&req, data->pointer, sizeof(struct iw_scan_req))) + return -EIO; + if (wmi_probedSsid_cmd(ar->arWmi, 1, SPECIFIC_SSID_FLAG, req.essid_len, req.essid) != A_OK) + return -EIO; + } + else + { + if (wmi_probedSsid_cmd(ar->arWmi, 1, DISABLE_SSID_FLAG, 0, NULL) != A_OK) + return -EIO; + } + } + else + { + if (wmi_probedSsid_cmd(ar->arWmi, 1, DISABLE_SSID_FLAG, 0, NULL) != A_OK) + return -EIO; + } +#endif + + if (wmi_startscan_cmd(ar->arWmi, WMI_LONG_SCAN, FALSE, FALSE, \ + 0, 0, 0, NULL) != A_OK) { + ret = -EIO; + } + + return ret; +#undef ACT_DWELLTIME_DEFAULT +#undef HOME_TXDRAIN_TIME +#undef SCAN_INT +} + + +/* + * Units are in db above the noise floor. That means the + * rssi values reported in the tx/rx descriptors in the + * driver are the SNR expressed in db. + * + * If you assume that the noise floor is -95, which is an + * excellent assumption 99.5 % of the time, then you can + * derive the absolute signal level (i.e. -95 + rssi). + * There are some other slight factors to take into account + * depending on whether the rssi measurement is from 11b, + * 11g, or 11a. These differences are at most 2db and + * can be documented. + * + * NB: various calculations are based on the orinoco/wavelan + * drivers for compatibility + */ +static void +ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi) +{ + if (rssi < 0) { + iq->qual = 0; + } else { + iq->qual = rssi; + } + + /* NB: max is 94 because noise is hardcoded to 161 */ + if (iq->qual > 94) + iq->qual = 94; + + iq->noise = 161; /* -95dBm */ + iq->level = iq->noise + iq->qual; + iq->updated = 7; +} + + +int +ar6000_ioctl_siwcommit(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + AR_DEBUG_PRINTF("AP: SSID %s freq %d authmode %d dot11 auth %d"\ + " PW crypto %d GRP crypto %d\n", + ar->arSsid, ar->arChannelHint, + ar->arAuthMode, ar->arDot11AuthMode, + ar->arPairwiseCrypto, ar->arGroupCrypto); + + ar6000_ap_mode_profile_commit(ar); + + /* if there is a profile switch from STA|IBSS mode to AP mode, + * update the host driver association state for the STA|IBSS mode. + */ + if (ar->arNetworkType != AP_NETWORK && ar->arNextMode == AP_NETWORK) { + ar->arConnectPending = FALSE; + ar->arConnected = FALSE; + /* Stop getting pkts from upper stack */ + netif_stop_queue(ar->arNetDev); + A_MEMZERO(ar->arBssid, sizeof(ar->arBssid)); + ar->arBssChannel = 0; + ar->arBeaconInterval = 0; + + /* Flush the Tx queues */ + ar6000_TxDataCleanup(ar); + + /* Start getting pkts from upper stack */ + netif_wake_queue(ar->arNetDev); + } + + return 0; +} + +/* Structures to export the Wireless Handlers */ +static const iw_handler ath_handlers[] = { + (iw_handler) ar6000_ioctl_siwcommit, /* SIOCSIWCOMMIT */ + (iw_handler) ar6000_ioctl_giwname, /* SIOCGIWNAME */ + (iw_handler) NULL, /* SIOCSIWNWID */ + (iw_handler) NULL, /* SIOCGIWNWID */ + (iw_handler) ar6000_ioctl_siwfreq, /* SIOCSIWFREQ */ + (iw_handler) ar6000_ioctl_giwfreq, /* SIOCGIWFREQ */ + (iw_handler) ar6000_ioctl_siwmode, /* SIOCSIWMODE */ + (iw_handler) ar6000_ioctl_giwmode, /* SIOCGIWMODE */ + (iw_handler) ar6000_ioctl_siwsens, /* SIOCSIWSENS */ + (iw_handler) ar6000_ioctl_giwsens, /* SIOCGIWSENS */ + (iw_handler) NULL /* not _used */, /* SIOCSIWRANGE */ + (iw_handler) ar6000_ioctl_giwrange, /* SIOCGIWRANGE */ + (iw_handler) NULL /* not used */, /* SIOCSIWPRIV */ + (iw_handler) NULL /* kernel code */, /* SIOCGIWPRIV */ + (iw_handler) NULL /* not used */, /* SIOCSIWSTATS */ + (iw_handler) NULL /* kernel code */, /* SIOCGIWSTATS */ + (iw_handler) NULL, /* SIOCSIWSPY */ + (iw_handler) NULL, /* SIOCGIWSPY */ + (iw_handler) NULL, /* SIOCSIWTHRSPY */ + (iw_handler) NULL, /* SIOCGIWTHRSPY */ + (iw_handler) ar6000_ioctl_siwap, /* SIOCSIWAP */ + (iw_handler) ar6000_ioctl_giwap, /* SIOCGIWAP */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) ar6000_ioctl_iwaplist, /* SIOCGIWAPLIST */ + (iw_handler) ar6000_ioctl_siwscan, /* SIOCSIWSCAN */ + (iw_handler) ar6000_ioctl_giwscan, /* SIOCGIWSCAN */ + (iw_handler) ar6000_ioctl_siwessid, /* SIOCSIWESSID */ + (iw_handler) ar6000_ioctl_giwessid, /* SIOCGIWESSID */ + (iw_handler) NULL, /* SIOCSIWNICKN */ + (iw_handler) NULL, /* SIOCGIWNICKN */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) ar6000_ioctl_siwrate, /* SIOCSIWRATE */ + (iw_handler) ar6000_ioctl_giwrate, /* SIOCGIWRATE */ + (iw_handler) NULL, /* SIOCSIWRTS */ + (iw_handler) NULL, /* SIOCGIWRTS */ + (iw_handler) NULL, /* SIOCSIWFRAG */ + (iw_handler) NULL, /* SIOCGIWFRAG */ + (iw_handler) ar6000_ioctl_siwtxpow, /* SIOCSIWTXPOW */ + (iw_handler) ar6000_ioctl_giwtxpow, /* SIOCGIWTXPOW */ + (iw_handler) ar6000_ioctl_siwretry, /* SIOCSIWRETRY */ + (iw_handler) ar6000_ioctl_giwretry, /* SIOCGIWRETRY */ + (iw_handler) ar6000_ioctl_siwencode, /* SIOCSIWENCODE */ + (iw_handler) ar6000_ioctl_giwencode, /* SIOCGIWENCODE */ + (iw_handler) ar6000_ioctl_siwpower, /* SIOCSIWPOWER */ + (iw_handler) ar6000_ioctl_giwpower, /* SIOCGIWPOWER */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) ar6000_ioctl_siwgenie, /* SIOCSIWGENIE */ + (iw_handler) ar6000_ioctl_giwgenie, /* SIOCGIWGENIE */ + (iw_handler) ar6000_ioctl_siwauth, /* SIOCSIWAUTH */ + (iw_handler) ar6000_ioctl_giwauth, /* SIOCGIWAUTH */ + (iw_handler) ar6000_ioctl_siwencodeext,/* SIOCSIWENCODEEXT */ + (iw_handler) ar6000_ioctl_giwencodeext,/* SIOCGIWENCODEEXT */ + (iw_handler) NULL, /* SIOCSIWPMKSA */ +}; + +struct iw_handler_def ath_iw_handler_def = { + .standard = (iw_handler *)ath_handlers, + .num_standard = ARRAY_SIZE(ath_handlers), + .private = NULL, + .num_private = 0, +}; diff -urN linux-2.6.26/drivers/net/wireless/ath6k/wlan_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/wlan_api.h --- linux-2.6.26/drivers/net/wireless/ath6k/wlan_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/wlan_api.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,119 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the API for the host wlan module +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HOST_WLAN_API_H_ +#define _HOST_WLAN_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +struct ieee80211_node_table; +struct ieee80211_frame; + +struct ieee80211_common_ie { + A_UINT16 ie_chan; + A_UINT8 *ie_tstamp; + A_UINT8 *ie_ssid; + A_UINT8 *ie_rates; + A_UINT8 *ie_xrates; + A_UINT8 *ie_country; + A_UINT8 *ie_wpa; + A_UINT8 *ie_rsn; + A_UINT8 *ie_wmm; + A_UINT8 *ie_ath; + A_UINT16 ie_capInfo; + A_UINT16 ie_beaconInt; + A_UINT8 *ie_tim; + A_UINT8 *ie_chswitch; + A_UINT8 ie_erp; + A_UINT8 *ie_wsc; +#ifdef PYXIS_ADHOC + A_UINT8 *ie_pyxis; +#endif +#ifdef WAPI_ENABLE + A_UINT8 *ie_wapi; +#endif +}; + +typedef struct bss { + A_UINT8 ni_macaddr[6]; + A_UINT8 ni_snr; + A_INT16 ni_rssi; + struct bss *ni_list_next; + struct bss *ni_list_prev; + struct bss *ni_hash_next; + struct bss *ni_hash_prev; + struct ieee80211_common_ie ni_cie; + A_UINT8 *ni_buf; + struct ieee80211_node_table *ni_table; + A_UINT32 ni_refcnt; + int ni_scangen; + + A_UINT32 ni_tstamp; +#ifdef OS_ROAM_MANAGEMENT + A_UINT32 ni_si_gen; +#endif +} bss_t; + +typedef void wlan_node_iter_func(void *arg, bss_t *); + +bss_t *wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size); +void wlan_node_free(bss_t *ni); +void wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni, + const A_UINT8 *macaddr); +bss_t *wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr); +void wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni); +void wlan_free_allnodes(struct ieee80211_node_table *nt); +void wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f, + void *arg); + +void wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt); +void wlan_node_table_reset(struct ieee80211_node_table *nt); +void wlan_node_table_cleanup(struct ieee80211_node_table *nt); + +A_STATUS wlan_parse_beacon(A_UINT8 *buf, int framelen, + struct ieee80211_common_ie *cie); + +A_UINT16 wlan_ieee2freq(int chan); +A_UINT32 wlan_freq2ieee(A_UINT16 freq); + +void wlan_set_nodeage(struct ieee80211_node_table *nt, A_UINT32 nodeAge); + + +bss_t * +wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID); + +void +wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni); + +bss_t *wlan_node_remove(struct ieee80211_node_table *nt, A_UINT8 *bssid); + +#ifdef __cplusplus +} +#endif + +#endif /* _HOST_WLAN_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/wlan_defs.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/wlan_defs.h --- linux-2.6.26/drivers/net/wireless/ath6k/wlan_defs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/wlan_defs.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,55 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef __WLAN_DEFS_H__ +#define __WLAN_DEFS_H__ + +/* + * This file contains WLAN definitions that may be used across both + * Host and Target software. + */ + +typedef enum { + MODE_11A = 0, /* 11a Mode */ + MODE_11G = 1, /* 11b/g Mode */ + MODE_11B = 2, /* 11b Mode */ + MODE_11GONLY = 3, /* 11g only Mode */ +#ifdef SUPPORT_11N + MODE_11A_HT20 = 4, /* 11a HT20 mode */ + MODE_11G_HT20 = 5, /* 11g HT20 mode */ + MODE_11A_HT40 = 6, /* 11a HT40 mode */ + MODE_11G_HT40 = 7, /* 11g HT40 mode */ + MODE_UNKNOWN = 8, + MODE_MAX = 8 +#else + MODE_UNKNOWN = 4, + MODE_MAX = 4 +#endif +} WLAN_PHY_MODE; + +typedef enum { + WLAN_11A_CAPABILITY = 1, + WLAN_11G_CAPABILITY = 2, + WLAN_11AG_CAPABILITY = 3, +}WLAN_CAPABILITY; + +#endif /* __ATHDEFS_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/wlan_dset.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/wlan_dset.h --- linux-2.6.26/drivers/net/wireless/ath6k/wlan_dset.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/wlan_dset.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,34 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __WLAN_DSET_H__ +#define __WKAN_DSET_H__ + +typedef PREPACK struct wow_config_dset { + + A_UINT8 valid_dset; + A_UINT8 gpio_enable; + A_UINT16 gpio_pin; +} POSTPACK WOW_CONFIG_DSET; + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k/wlan_node.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/wlan_node.c --- linux-2.6.26/drivers/net/wireless/ath6k/wlan_node.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/wlan_node.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,470 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// IEEE 802.11 node handling support. +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "a_debug.h" +#include "htc.h" +#include "htc_api.h" +#include "wmi.h" +#include "ieee80211.h" +#include "wlan_api.h" +#include "wmi_api.h" +#include "ieee80211_node.h" + +static void wlan_node_timeout(A_ATH_TIMER arg); + +static bss_t * _ieee80211_find_node (struct ieee80211_node_table *nt, + const A_UINT8 *macaddr); + +bss_t * +wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size) +{ + bss_t *ni; + + ni = A_MALLOC_NOWAIT(sizeof(bss_t)); + + if (ni != NULL) { + if (wh_size) + { + ni->ni_buf = A_MALLOC_NOWAIT(wh_size); + if (ni->ni_buf == NULL) { + A_FREE(ni); + ni = NULL; + return ni; + } + } + } else { + return ni; + } + + /* Make sure our lists are clean */ + ni->ni_list_next = NULL; + ni->ni_list_prev = NULL; + ni->ni_hash_next = NULL; + ni->ni_hash_prev = NULL; + + // + // ni_scangen never initialized before and during suspend/resume of winmobile, + // that some junk has been stored in this, due to this scan list didn't properly updated + // + ni->ni_scangen = 0; + +#ifdef OS_ROAM_MANAGEMENT + ni->ni_si_gen = 0; +#endif + + return ni; +} + +void +wlan_node_free(bss_t *ni) +{ + if (ni->ni_buf != NULL) { + A_FREE(ni->ni_buf); + } + A_FREE(ni); +} + +void +wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni, + const A_UINT8 *macaddr) +{ + int hash; + A_UINT32 timeoutValue = 0; + + A_MEMCPY(ni->ni_macaddr, macaddr, IEEE80211_ADDR_LEN); + hash = IEEE80211_NODE_HASH (macaddr); + ieee80211_node_initref (ni); /* mark referenced */ + + timeoutValue = nt->nt_nodeAge; + + ni->ni_tstamp = A_GET_MS (timeoutValue); + + IEEE80211_NODE_LOCK_BH(nt); + + /* Insert at the end of the node list */ + ni->ni_list_next = NULL; + ni->ni_list_prev = nt->nt_node_last; + if(nt->nt_node_last != NULL) + { + nt->nt_node_last->ni_list_next = ni; + } + nt->nt_node_last = ni; + if(nt->nt_node_first == NULL) + { + nt->nt_node_first = ni; + } + + /* Insert into the hash list i.e. the bucket */ + if((ni->ni_hash_next = nt->nt_hash[hash]) != NULL) + { + nt->nt_hash[hash]->ni_hash_prev = ni; + } + ni->ni_hash_prev = NULL; + nt->nt_hash[hash] = ni; + + if (!nt->isTimerArmed) { + A_TIMEOUT_MS(&nt->nt_inact_timer, timeoutValue, 0); + nt->isTimerArmed = TRUE; + } + + IEEE80211_NODE_UNLOCK_BH(nt); +} + +static bss_t * +_ieee80211_find_node(struct ieee80211_node_table *nt, + const A_UINT8 *macaddr) +{ + bss_t *ni; + int hash; + + IEEE80211_NODE_LOCK_ASSERT(nt); + + hash = IEEE80211_NODE_HASH(macaddr); + for(ni = nt->nt_hash[hash]; ni; ni = ni->ni_hash_next) { + if (IEEE80211_ADDR_EQ(ni->ni_macaddr, macaddr)) { + ieee80211_node_incref(ni); /* mark referenced */ + return ni; + } + } + return NULL; +} + +bss_t * +wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr) +{ + bss_t *ni; + + IEEE80211_NODE_LOCK(nt); + ni = _ieee80211_find_node(nt, macaddr); + IEEE80211_NODE_UNLOCK(nt); + return ni; +} + +/* + * Reclaim a node. If this is the last reference count then + * do the normal free work. Otherwise remove it from the node + * table and mark it gone by clearing the back-reference. + */ +void +wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni) +{ + IEEE80211_NODE_LOCK(nt); + + if(ni->ni_list_prev == NULL) + { + /* First in list so fix the list head */ + nt->nt_node_first = ni->ni_list_next; + } + else + { + ni->ni_list_prev->ni_list_next = ni->ni_list_next; + } + + if(ni->ni_list_next == NULL) + { + /* Last in list so fix list tail */ + nt->nt_node_last = ni->ni_list_prev; + } + else + { + ni->ni_list_next->ni_list_prev = ni->ni_list_prev; + } + + if(ni->ni_hash_prev == NULL) + { + /* First in list so fix the list head */ + int hash; + hash = IEEE80211_NODE_HASH(ni->ni_macaddr); + nt->nt_hash[hash] = ni->ni_hash_next; + } + else + { + ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next; + } + + if(ni->ni_hash_next != NULL) + { + ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev; + } + wlan_node_free(ni); + + IEEE80211_NODE_UNLOCK(nt); +} + +static void +wlan_node_dec_free(bss_t *ni) +{ + if (ieee80211_node_dectestref(ni)) { + wlan_node_free(ni); + } +} + +void +wlan_free_allnodes(struct ieee80211_node_table *nt) +{ + bss_t *ni; + + while ((ni = nt->nt_node_first) != NULL) { + wlan_node_reclaim(nt, ni); + } +} + +void +wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f, + void *arg) +{ + bss_t *ni; + A_UINT32 gen; + + gen = ++nt->nt_scangen; + + IEEE80211_NODE_LOCK(nt); + for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) { + if (ni->ni_scangen != gen) { + ni->ni_scangen = gen; + (void) ieee80211_node_incref(ni); + (*f)(arg, ni); + wlan_node_dec_free(ni); + } + } + IEEE80211_NODE_UNLOCK(nt); +} + +/* + * Node table support. + */ +void +wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt) +{ + int i; + + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN, ("node table = 0x%x\n", (A_UINT32)nt)); + IEEE80211_NODE_LOCK_INIT(nt); + + nt->nt_node_first = nt->nt_node_last = NULL; + for(i = 0; i < IEEE80211_NODE_HASHSIZE; i++) + { + nt->nt_hash[i] = NULL; + } + + A_INIT_TIMER(&nt->nt_inact_timer, wlan_node_timeout, nt); + nt->isTimerArmed = FALSE; + nt->nt_wmip = wmip; + nt->nt_nodeAge = WLAN_NODE_INACT_TIMEOUT_MSEC; + + // + // nt_scangen never initialized before and during suspend/resume of winmobile, customer (LG/SEMCO) identified + // that some junk has been stored in this, due to this scan list didn't properly updated + // + nt->nt_scangen = 0; + +#ifdef OS_ROAM_MANAGEMENT + nt->nt_si_gen = 0; +#endif +} + +void +wlan_set_nodeage(struct ieee80211_node_table *nt, A_UINT32 nodeAge) +{ + nt->nt_nodeAge = nodeAge; + return; +} +static void +wlan_node_timeout (A_ATH_TIMER arg) +{ + struct ieee80211_node_table *nt = (struct ieee80211_node_table *)arg; + bss_t *bss, *nextBss; + A_UINT8 myBssid[IEEE80211_ADDR_LEN], reArmTimer = FALSE; + A_UINT32 timeoutValue = 0; + + timeoutValue = nt->nt_nodeAge; + + wmi_get_current_bssid(nt->nt_wmip, myBssid); + + bss = nt->nt_node_first; + while (bss != NULL) + { + nextBss = bss->ni_list_next; + if (A_MEMCMP(myBssid, bss->ni_macaddr, sizeof(myBssid)) != 0) + { + + if (bss->ni_tstamp <= A_GET_MS(0)) + { + /* + * free up all but the current bss - if set + */ + wlan_node_reclaim(nt, bss); + } + else + { + /* + * Re-arm timer, only when we have a bss other than + * current bss AND it is not aged-out. + */ + reArmTimer = TRUE; + } + } + bss = nextBss; + } + + if (reArmTimer) + A_TIMEOUT_MS (&nt->nt_inact_timer, timeoutValue, 0); + + nt->isTimerArmed = reArmTimer; +} + +void +wlan_node_table_cleanup(struct ieee80211_node_table *nt) +{ + A_UNTIMEOUT(&nt->nt_inact_timer); + A_DELETE_TIMER(&nt->nt_inact_timer); + wlan_free_allnodes(nt); + IEEE80211_NODE_LOCK_DESTROY(nt); +} + +bss_t * +wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID) +{ + bss_t *ni = NULL; + A_UCHAR *pIESsid = NULL; + + IEEE80211_NODE_LOCK (nt); + + for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) { + pIESsid = ni->ni_cie.ie_ssid; + if (pIESsid[1] <= 32) { + + // Step 1 : Check SSID + if (0x00 == memcmp (pSsid, &pIESsid[2], ssidLength)) { + + // + // Step 2.1 : Check MatchSSID is TRUE, if so, return Matched SSID + // Profile, otherwise check whether WPA2 or WPA + // + if (TRUE == bMatchSSID) { + ieee80211_node_incref (ni); /* mark referenced */ + IEEE80211_NODE_UNLOCK (nt); + return ni; + } + + // Step 2 : if SSID matches, check WPA or WPA2 + if (TRUE == bIsWPA2 && NULL != ni->ni_cie.ie_rsn) { + ieee80211_node_incref (ni); /* mark referenced */ + IEEE80211_NODE_UNLOCK (nt); + return ni; + } + if (FALSE == bIsWPA2 && NULL != ni->ni_cie.ie_wpa) { + ieee80211_node_incref(ni); /* mark referenced */ + IEEE80211_NODE_UNLOCK (nt); + return ni; + } + } + } + } + + IEEE80211_NODE_UNLOCK (nt); + + return NULL; +} + +void +wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni) +{ + IEEE80211_NODE_LOCK (nt); + wlan_node_dec_free (ni); + IEEE80211_NODE_UNLOCK (nt); +} + +void +wlan_node_remove_core (struct ieee80211_node_table *nt, bss_t *ni) +{ + if(ni->ni_list_prev == NULL) + { + /* First in list so fix the list head */ + nt->nt_node_first = ni->ni_list_next; + } + else + { + ni->ni_list_prev->ni_list_next = ni->ni_list_next; + } + + if(ni->ni_list_next == NULL) + { + /* Last in list so fix list tail */ + nt->nt_node_last = ni->ni_list_prev; + } + else + { + ni->ni_list_next->ni_list_prev = ni->ni_list_prev; + } + + if(ni->ni_hash_prev == NULL) + { + /* First in list so fix the list head */ + int hash; + hash = IEEE80211_NODE_HASH(ni->ni_macaddr); + nt->nt_hash[hash] = ni->ni_hash_next; + } + else + { + ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next; + } + + if(ni->ni_hash_next != NULL) + { + ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev; + } +} + +bss_t * +wlan_node_remove(struct ieee80211_node_table *nt, A_UINT8 *bssid) +{ + bss_t *bss, *nextBss; + + IEEE80211_NODE_LOCK(nt); + + bss = nt->nt_node_first; + + while (bss != NULL) + { + nextBss = bss->ni_list_next; + + if (A_MEMCMP(bssid, bss->ni_macaddr, 6) == 0) + { + wlan_node_remove_core (nt, bss); + IEEE80211_NODE_UNLOCK(nt); + return bss; + } + + bss = nextBss; + } + + IEEE80211_NODE_UNLOCK(nt); + return NULL; +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k/wlan_recv_beacon.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/wlan_recv_beacon.c --- linux-2.6.26/drivers/net/wireless/ath6k/wlan_recv_beacon.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/wlan_recv_beacon.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,203 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// IEEE 802.11 input handling. +// +// Author(s): ="Atheros" +//============================================================================== + +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "wmi.h" +#include "ieee80211.h" +#include "wlan_api.h" + +#define IEEE80211_VERIFY_LENGTH(_len, _minlen) do { \ + if ((_len) < (_minlen)) { \ + return A_EINVAL; \ + } \ +} while (0) + +#define IEEE80211_VERIFY_ELEMENT(__elem, __maxlen) do { \ + if ((__elem) == NULL) { \ + return A_EINVAL; \ + } \ + if ((__elem)[1] > (__maxlen)) { \ + return A_EINVAL; \ + } \ +} while (0) + + +/* unaligned little endian access */ +#define LE_READ_2(p) \ + ((A_UINT16) \ + ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8))) + +#define LE_READ_4(p) \ + ((A_UINT32) \ + ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8) | \ + (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24))) + + +static int __inline +iswpaoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((WPA_OUI_TYPE<<24)|WPA_OUI); +} + +static int __inline +iswmmoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((WMM_OUI_TYPE<<24)|WMM_OUI); +} + +/* unused functions for now */ +#if 0 +static int __inline +iswmmparam(const A_UINT8 *frm) +{ + return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE; +} + +static int __inline +iswmminfo(const A_UINT8 *frm) +{ + return frm[1] > 5 && frm[6] == WMM_INFO_OUI_SUBTYPE; +} +#endif + +static int __inline +isatherosoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((ATH_OUI_TYPE<<24)|ATH_OUI); +} + +static int __inline +iswscoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((0x04<<24)|WPA_OUI); +} + +#ifdef PYXIS_ADHOC +static int __inline +ispyxisoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((PYXIS_OUI_TYPE<<24)|PYXIS_OUI); +} +#endif + +A_STATUS +wlan_parse_beacon(A_UINT8 *buf, int framelen, struct ieee80211_common_ie *cie) +{ + A_UINT8 *frm, *efrm; + + frm = buf; + efrm = (A_UINT8 *) (frm + framelen); + + /* + * beacon/probe response frame format + * [8] time stamp + * [2] beacon interval + * [2] capability information + * [tlv] ssid + * [tlv] supported rates + * [tlv] country information + * [tlv] parameter set (FH/DS) + * [tlv] erp information + * [tlv] extended supported rates + * [tlv] WMM + * [tlv] WPA or RSN + * [tlv] Atheros Advanced Capabilities + */ + IEEE80211_VERIFY_LENGTH(efrm - frm, 12); + A_MEMZERO(cie, sizeof(*cie)); + + cie->ie_tstamp = frm; frm += 8; + cie->ie_beaconInt = A_LE2CPU16(*(A_UINT16 *)frm); frm += 2; + cie->ie_capInfo = A_LE2CPU16(*(A_UINT16 *)frm); frm += 2; + cie->ie_chan = 0; + + while (frm < efrm) { + switch (*frm) { + case IEEE80211_ELEMID_SSID: + cie->ie_ssid = frm; + break; + case IEEE80211_ELEMID_RATES: + cie->ie_rates = frm; + break; + case IEEE80211_ELEMID_COUNTRY: + cie->ie_country = frm; + break; + case IEEE80211_ELEMID_FHPARMS: + break; + case IEEE80211_ELEMID_DSPARMS: + cie->ie_chan = frm[2]; + break; + case IEEE80211_ELEMID_TIM: + cie->ie_tim = frm; + break; + case IEEE80211_ELEMID_IBSSPARMS: + break; + case IEEE80211_ELEMID_XRATES: + cie->ie_xrates = frm; + break; + case IEEE80211_ELEMID_ERP: + if (frm[1] != 1) { + //A_PRINTF("Discarding ERP Element - Bad Len\n"); + return A_EINVAL; + } + cie->ie_erp = frm[2]; + break; + case IEEE80211_ELEMID_RSN: + cie->ie_rsn = frm; + break; +#ifdef WAPI_ENABLE + case IEEE80211_ELEMID_WAPI: + cie->ie_wapi = frm; + break; +#endif + case IEEE80211_ELEMID_VENDOR: + if (iswpaoui(frm)) { + cie->ie_wpa = frm; + } else if (iswmmoui(frm)) { + cie->ie_wmm = frm; + } else if (isatherosoui(frm)) { + cie->ie_ath = frm; + } else if(iswscoui(frm)) { + cie->ie_wsc = frm; + } +#ifdef PYXIS_ADHOC + else if(ispyxisoui(frm)) { + cie->ie_pyxis= frm; + } +#endif + break; + default: + break; + } + frm += frm[1] + 2; + } + IEEE80211_VERIFY_ELEMENT(cie->ie_rates, IEEE80211_RATE_MAXSIZE); + IEEE80211_VERIFY_ELEMENT(cie->ie_ssid, IEEE80211_NWID_LEN); + + return A_OK; +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k/wlan_utils.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/wlan_utils.c --- linux-2.6.26/drivers/net/wireless/ath6k/wlan_utils.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/wlan_utils.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,61 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This module implements frequently used wlan utilies +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" + +/* + * converts ieee channel number to frequency + */ +A_UINT16 +wlan_ieee2freq(int chan) +{ + if (chan == 14) { + return 2484; + } + if (chan < 14) { /* 0-13 */ + return (2407 + (chan*5)); + } + if (chan < 27) { /* 15-26 */ + return (2512 + ((chan-15)*20)); + } + return (5000 + (chan*5)); +} + +/* + * Converts MHz frequency to IEEE channel number. + */ +A_UINT32 +wlan_freq2ieee(A_UINT16 freq) +{ + if (freq == 2484) + return 14; + if (freq < 2484) + return (freq - 2407) / 5; + if (freq < 5000) + return 15 + ((freq - 2512) / 20); + return (freq - 5000) / 5; +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k/wmi.c linux-2.6.26-lab126/drivers/net/wireless/ath6k/wmi.c --- linux-2.6.26/drivers/net/wireless/ath6k/wmi.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/wmi.c 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,5805 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This module implements the hardware independent layer of the +// Wireless Module Interface (WMI) protocol. +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "htc.h" +#include "htc_api.h" +#include "wmi.h" +#include "wlan_api.h" +#include "wmi_api.h" +#include "ieee80211.h" +#include "ieee80211_node.h" +#include "dset_api.h" +#include "gpio_api.h" +#include "wmi_host.h" +#include "a_drv.h" +#include "a_drv_api.h" +#include "a_debug.h" +#include "dbglog_api.h" +#include "roaming.h" + +static A_STATUS wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); + +static A_STATUS wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_sync_point(struct wmi_t *wmip); + +static A_STATUS wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); + +static A_STATUS wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +#ifdef CONFIG_HOST_DSET_SUPPORT +static A_STATUS wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +#endif /* CONFIG_HOST_DSET_SUPPORT */ + + +static A_STATUS wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_channel_change_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS +wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len); + +static A_STATUS +wmi_set_params_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len); + +#ifdef CONFIG_HOST_GPIO_SUPPORT +static A_STATUS wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +#ifdef CONFIG_HOST_TCMD_SUPPORT +static A_STATUS +wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +#endif + +static A_STATUS +wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS +wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS +wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_BOOL +wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_INT32 rateIndex); + +static A_STATUS +wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS +wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +A_STATUS wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMIX_COMMAND_ID cmdId, + WMI_SYNC_FLAG syncflag); + +A_UINT8 ar6000_get_upper_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, A_UINT32 size); +A_UINT8 ar6000_get_lower_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, A_UINT32 size); + +void wmi_cache_configure_rssithreshold(struct wmi_t *wmip, WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd); +void wmi_cache_configure_snrthreshold(struct wmi_t *wmip, WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd); +static A_STATUS wmi_send_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd); +static A_STATUS wmi_send_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd); +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +static A_STATUS +wmi_prof_count_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + +static A_STATUS wmi_pspoll_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_dtimexpiry_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); + +static A_STATUS wmi_peer_node_event_rx (struct wmi_t *wmip, A_UINT8 *datap, + int len); + +#if defined(UNDER_CE) +#if defined(NDIS51_MINIPORT) +unsigned int processDot11Hdr = 0; +#else +unsigned int processDot11Hdr = 1; +#endif +#else +extern unsigned int processDot11Hdr; +#endif + +static const A_INT32 wmi_rateTable[] = { + 1000, + 2000, + 5500, + 11000, + 6000, + 9000, + 12000, + 18000, + 24000, + 36000, + 48000, + 54000, + 0}; + +#define MODE_A_SUPPORT_RATE_START ((A_INT32) 4) +#define MODE_A_SUPPORT_RATE_STOP ((A_INT32) 11) + +#define MODE_GONLY_SUPPORT_RATE_START MODE_A_SUPPORT_RATE_START +#define MODE_GONLY_SUPPORT_RATE_STOP MODE_A_SUPPORT_RATE_STOP + +#define MODE_B_SUPPORT_RATE_START ((A_INT32) 0) +#define MODE_B_SUPPORT_RATE_STOP ((A_INT32) 3) + +#define MODE_G_SUPPORT_RATE_START ((A_INT32) 0) +#define MODE_G_SUPPORT_RATE_STOP ((A_INT32) 11) + +#define MAX_NUMBER_OF_SUPPORT_RATES (MODE_G_SUPPORT_RATE_STOP + 1) + +/* 802.1d to AC mapping. Refer pg 57 of WMM-test-plan-v1.2 */ +const A_UINT8 up_to_ac[]= { + WMM_AC_BE, + WMM_AC_BK, + WMM_AC_BK, + WMM_AC_BE, + WMM_AC_VI, + WMM_AC_VI, + WMM_AC_VO, + WMM_AC_VO, + }; + +#include "athstartpack.h" + +/* This stuff is used when we want a simple layer-3 visibility */ +typedef PREPACK struct _iphdr { + A_UINT8 ip_ver_hdrlen; /* version and hdr length */ + A_UINT8 ip_tos; /* type of service */ + A_UINT16 ip_len; /* total length */ + A_UINT16 ip_id; /* identification */ + A_INT16 ip_off; /* fragment offset field */ +#define IP_DF 0x4000 /* dont fragment flag */ +#define IP_MF 0x2000 /* more fragments flag */ +#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */ + A_UINT8 ip_ttl; /* time to live */ + A_UINT8 ip_p; /* protocol */ + A_UINT16 ip_sum; /* checksum */ + A_UINT8 ip_src[4]; /* source and dest address */ + A_UINT8 ip_dst[4]; +} POSTPACK iphdr; + +#include "athendpack.h" + +A_INT16 rssi_event_value = 0; +A_INT16 snr_event_value = 0; + +void * +wmi_init(void *devt) +{ + struct wmi_t *wmip; + + wmip = A_MALLOC (sizeof(struct wmi_t)); + if (wmip == NULL) { + return (NULL); + } + A_MEMZERO(wmip, sizeof(*wmip)); + A_MUTEX_INIT(&wmip->wmi_lock); + wmip->wmi_devt = devt; + wlan_node_table_init(wmip, &wmip->wmi_scan_table); + wmi_qos_state_init(wmip); + + wmip->wmi_powerMode = REC_POWER; + wmip->wmi_phyMode = WMI_11G_MODE; + + wmip->wmi_pair_crypto_type = NONE_CRYPT; + wmip->wmi_grp_crypto_type = NONE_CRYPT; + + return (wmip); +} + +void +wmi_qos_state_init(struct wmi_t *wmip) +{ + A_UINT8 i; + + if (wmip == NULL) { + return; + } + LOCK_WMI(wmip); + + /* Initialize QoS States */ + wmip->wmi_numQoSStream = 0; + + wmip->wmi_fatPipeExists = 0; + + for (i=0; i < WMM_NUM_AC; i++) { + wmip->wmi_streamExistsForAC[i]=0; + } + + UNLOCK_WMI(wmip); + + A_WMI_SET_NUMDATAENDPTS(wmip->wmi_devt, 1); +} + +void +wmi_set_control_ep(struct wmi_t * wmip, HTC_ENDPOINT_ID eid) +{ + A_ASSERT( eid != ENDPOINT_UNUSED); + wmip->wmi_endpoint_id = eid; +} + +HTC_ENDPOINT_ID +wmi_get_control_ep(struct wmi_t * wmip) +{ + return(wmip->wmi_endpoint_id); +} + +void +wmi_shutdown(struct wmi_t *wmip) +{ + if (wmip != NULL) { + wlan_node_table_cleanup(&wmip->wmi_scan_table); + if (A_IS_MUTEX_VALID(&wmip->wmi_lock)) { + A_MUTEX_DELETE(&wmip->wmi_lock); + } + A_FREE(wmip); + } +} + +/* + * performs DIX to 802.3 encapsulation for transmit packets. + * uses passed in buffer. Returns buffer or NULL if failed. + * Assumes the entire DIX header is contigous and that there is + * enough room in the buffer for a 802.3 mac header and LLC+SNAP headers. + */ +A_STATUS +wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf) +{ + A_UINT8 *datap; + A_UINT16 typeorlen; + ATH_MAC_HDR macHdr; + ATH_LLC_SNAP_HDR *llcHdr; + + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_HEADROOM(osbuf) < + (sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR))) + { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + typeorlen = *(A_UINT16 *)(datap + ATH_MAC_LEN + ATH_MAC_LEN); + + if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) { + /* + * packet is already in 802.3 format - return success + */ + A_DPRINTF(DBG_WMI, (DBGFMT "packet already 802.3\n", DBGARG)); + return (A_OK); + } + + /* + * Save mac fields and length to be inserted later + */ + A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN); + A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN); + macHdr.typeOrLen = A_CPU2BE16(A_NETBUF_LEN(osbuf) - sizeof(ATH_MAC_HDR) + + sizeof(ATH_LLC_SNAP_HDR)); + + /* + * Make room for LLC+SNAP headers + */ + if (A_NETBUF_PUSH(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR)); + + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR)); + llcHdr->dsap = 0xAA; + llcHdr->ssap = 0xAA; + llcHdr->cntl = 0x03; + llcHdr->orgCode[0] = 0x0; + llcHdr->orgCode[1] = 0x0; + llcHdr->orgCode[2] = 0x0; + llcHdr->etherType = typeorlen; + + return (A_OK); +} + +/* + * Adds a WMI data header + * Assumes there is enough room in the buffer to add header. + */ +A_STATUS +wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType, A_BOOL bMoreData) +{ + WMI_DATA_HDR *dtHdr; + + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf); + dtHdr->info = msgType; + if (bMoreData) { + WMI_DATA_HDR_SET_MORE_BIT(dtHdr); + } + dtHdr->rssi = 0; + + return (A_OK); +} + +A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT32 layer2Priority, A_BOOL wmmEnabled) +{ + A_UINT8 *datap; + A_UINT8 trafficClass = WMM_AC_BE; + A_UINT16 ipType = IP_ETHERTYPE; + WMI_DATA_HDR *dtHdr; + A_BOOL streamExists = FALSE; + A_UINT8 userPriority; + A_UINT32 hdrsize; + ATH_LLC_SNAP_HDR *llcHdr; + + WMI_CREATE_PSTREAM_CMD cmd; + + A_ASSERT(osbuf != NULL); + + // + // Initialize header size + // + hdrsize = 0; + + datap = A_NETBUF_DATA(osbuf); + + if (!wmmEnabled) + { + /* If WMM is disabled all traffic goes as BE traffic */ + userPriority = 0; + } + else + { + if (processDot11Hdr) + { + hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32)); + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) + + hdrsize); + } + else + { + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) + + sizeof(ATH_MAC_HDR)); + } + + if (llcHdr->etherType == A_CPU2BE16(ipType)) + { + /* Extract the endpoint info from the TOS field in the IP header */ + + userPriority = wmi_determine_userPriority (((A_UINT8 *)llcHdr) + sizeof(ATH_LLC_SNAP_HDR),layer2Priority); + } + else + { + userPriority = layer2Priority & 0x7; + } + } + + trafficClass = convert_userPriority_to_trafficClass(userPriority); + + dtHdr = (WMI_DATA_HDR *)datap; + dtHdr->info |= (userPriority & WMI_DATA_HDR_UP_MASK) << WMI_DATA_HDR_UP_SHIFT; /* lower 3-bits are 802.1d priority */ + + LOCK_WMI(wmip); + streamExists = wmip->wmi_fatPipeExists; + UNLOCK_WMI(wmip); + + if (!(streamExists & (1 << trafficClass))) + { + + A_MEMZERO (&cmd, sizeof(cmd)); + cmd.trafficClass = trafficClass; + cmd.userPriority = userPriority; + cmd.inactivityInt = WMI_IMPLICIT_PSTREAM_INACTIVITY_INT; + /* Implicit streams are created with TSID 0xFF */ + + cmd.tsid = WMI_IMPLICIT_PSTREAM; + wmi_create_pstream_cmd (wmip, &cmd); + } + + return trafficClass; +} + +A_STATUS +wmi_dot11_hdr_add (struct wmi_t *wmip, void *osbuf, NETWORK_TYPE mode) +{ + A_UINT8 *datap; + A_UINT16 typeorlen; + ATH_MAC_HDR macHdr; + ATH_LLC_SNAP_HDR *llcHdr; + struct ieee80211_frame *wh; + A_UINT32 hdrsize; + + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_HEADROOM(osbuf) < + (sizeof(struct ieee80211_qosframe) + sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR))) + { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + typeorlen = *(A_UINT16 *)(datap + ATH_MAC_LEN + ATH_MAC_LEN); + + if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) { + /* + * packet is already in 802.3 format - return success + */ + A_DPRINTF(DBG_WMI, (DBGFMT "packet already 802.3\n", DBGARG)); + goto AddDot11Hdr; + } + + /* + * Save mac fields and length to be inserted later + */ + A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN); + A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN); + macHdr.typeOrLen = A_CPU2BE16(A_NETBUF_LEN(osbuf) - sizeof(ATH_MAC_HDR) + + sizeof(ATH_LLC_SNAP_HDR)); + + // Remove the Ethernet hdr + A_NETBUF_PULL(osbuf, sizeof(ATH_MAC_HDR)); + + /* + * Make room for LLC+SNAP headers + */ + if (A_NETBUF_PUSH(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + llcHdr = (ATH_LLC_SNAP_HDR *)(datap); + llcHdr->dsap = 0xAA; + llcHdr->ssap = 0xAA; + llcHdr->cntl = 0x03; + llcHdr->orgCode[0] = 0x0; + llcHdr->orgCode[1] = 0x0; + llcHdr->orgCode[2] = 0x0; + llcHdr->etherType = typeorlen; + +AddDot11Hdr: + /* Make room for 802.11 hdr */ + if (wmip->wmi_is_wmm_enabled) + { + hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32)); + if (A_NETBUF_PUSH(osbuf, hdrsize) != A_OK) + { + return A_NO_MEMORY; + } + wh = (struct ieee80211_frame *) A_NETBUF_DATA(osbuf); + wh->i_fc[0] = IEEE80211_FC0_SUBTYPE_QOS; + } + else + { + hdrsize = A_ROUND_UP(sizeof(struct ieee80211_frame),sizeof(A_UINT32)); + if (A_NETBUF_PUSH(osbuf, hdrsize) != A_OK) + { + return A_NO_MEMORY; + } + wh = (struct ieee80211_frame *) A_NETBUF_DATA(osbuf); + wh->i_fc[0] = IEEE80211_FC0_SUBTYPE_DATA; + } + /* Setup the SA & DA */ + IEEE80211_ADDR_COPY(wh->i_addr2, macHdr.srcMac); + + if (mode == INFRA_NETWORK) { + IEEE80211_ADDR_COPY(wh->i_addr3, macHdr.dstMac); + } + else if (mode == ADHOC_NETWORK) { + IEEE80211_ADDR_COPY(wh->i_addr1, macHdr.dstMac); + } + + return (A_OK); +} + +A_STATUS +wmi_dot11_hdr_remove(struct wmi_t *wmip, void *osbuf) +{ + A_UINT8 *datap; + struct ieee80211_frame *pwh,wh; + A_UINT8 type,subtype; + ATH_LLC_SNAP_HDR *llcHdr; + ATH_MAC_HDR macHdr; + A_UINT32 hdrsize; + + A_ASSERT(osbuf != NULL); + datap = A_NETBUF_DATA(osbuf); + + pwh = (struct ieee80211_frame *)datap; + type = pwh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; + subtype = pwh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; + + A_MEMCPY((A_UINT8 *)&wh, datap, sizeof(struct ieee80211_frame)); + + /* strip off the 802.11 hdr*/ + if (subtype == IEEE80211_FC0_SUBTYPE_QOS) { + hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32)); + A_NETBUF_PULL(osbuf, hdrsize); + } else if (subtype == IEEE80211_FC0_SUBTYPE_DATA) { + A_NETBUF_PULL(osbuf, sizeof(struct ieee80211_frame)); + } + + datap = A_NETBUF_DATA(osbuf); + llcHdr = (ATH_LLC_SNAP_HDR *)(datap); + + macHdr.typeOrLen = llcHdr->etherType; + + switch (wh.i_fc[1] & IEEE80211_FC1_DIR_MASK) { + case IEEE80211_FC1_DIR_NODS: + IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr1); + IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr2); + break; + case IEEE80211_FC1_DIR_TODS: + IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr3); + IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr2); + break; + case IEEE80211_FC1_DIR_FROMDS: + IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr1); + IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr3); + break; + case IEEE80211_FC1_DIR_DSTODS: + break; + } + + // Remove the LLC Hdr. + A_NETBUF_PULL(osbuf, sizeof(ATH_LLC_SNAP_HDR)); + + // Insert the ATH MAC hdr. + + A_NETBUF_PUSH(osbuf, sizeof(ATH_MAC_HDR)); + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY (datap, &macHdr, sizeof(ATH_MAC_HDR)); + + return A_OK; +} + +/* + * performs 802.3 to DIX encapsulation for received packets. + * Assumes the entire 802.3 header is contigous. + */ +A_STATUS +wmi_dot3_2_dix(struct wmi_t *wmip, void *osbuf) +{ + A_UINT8 *datap; + ATH_MAC_HDR macHdr; + ATH_LLC_SNAP_HDR *llcHdr; + + A_ASSERT(osbuf != NULL); + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY(&macHdr, datap, sizeof(ATH_MAC_HDR)); + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR)); + macHdr.typeOrLen = llcHdr->etherType; + + if (A_NETBUF_PULL(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR)); + + return (A_OK); +} + +/* + * Removes a WMI data header + */ +A_STATUS +wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf) +{ + A_ASSERT(osbuf != NULL); + + return (A_NETBUF_PULL(osbuf, sizeof(WMI_DATA_HDR))); +} + +void +wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg) +{ + wlan_iterate_nodes(&wmip->wmi_scan_table, f, arg); +} + +/* + * WMI Extended Event received from Target. + */ +A_STATUS +wmi_control_rx_xtnd(struct wmi_t *wmip, void *osbuf) +{ + WMIX_CMD_HDR *cmd; + A_UINT16 id; + A_UINT8 *datap; + A_UINT32 len; + A_STATUS status = A_OK; + + if (A_NETBUF_LEN(osbuf) < sizeof(WMIX_CMD_HDR)) { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + A_NETBUF_FREE(osbuf); + return A_ERROR; + } + + cmd = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf); + id = cmd->commandId; + + if (A_NETBUF_PULL(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + A_NETBUF_FREE(osbuf); + return A_ERROR; + } + + datap = A_NETBUF_DATA(osbuf); + len = A_NETBUF_LEN(osbuf); + + switch (id) { + case (WMIX_DSETOPENREQ_EVENTID): + status = wmi_dset_open_req_rx(wmip, datap, len); + break; +#ifdef CONFIG_HOST_DSET_SUPPORT + case (WMIX_DSETCLOSE_EVENTID): + status = wmi_dset_close_rx(wmip, datap, len); + break; + case (WMIX_DSETDATAREQ_EVENTID): + status = wmi_dset_data_req_rx(wmip, datap, len); + break; +#endif /* CONFIG_HOST_DSET_SUPPORT */ +#ifdef CONFIG_HOST_GPIO_SUPPORT + case (WMIX_GPIO_INTR_EVENTID): + wmi_gpio_intr_rx(wmip, datap, len); + break; + case (WMIX_GPIO_DATA_EVENTID): + wmi_gpio_data_rx(wmip, datap, len); + break; + case (WMIX_GPIO_ACK_EVENTID): + wmi_gpio_ack_rx(wmip, datap, len); + break; +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + case (WMIX_HB_CHALLENGE_RESP_EVENTID): + wmi_hbChallengeResp_rx(wmip, datap, len); + break; + case (WMIX_DBGLOG_EVENTID): + wmi_dbglog_event_rx(wmip, datap, len); + break; +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) + case (WMIX_PROF_COUNT_EVENTID): + wmi_prof_count_rx(wmip, datap, len); + break; +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + default: + A_DPRINTF(DBG_WMI|DBG_ERROR, + (DBGFMT "Unknown id 0x%x\n", DBGARG, id)); + wmip->wmi_stats.cmd_id_err++; + status = A_ERROR; + break; + } + + return status; +} + +/* + * Control Path + */ +A_UINT32 cmdRecvNum; + +A_STATUS +wmi_control_rx(struct wmi_t *wmip, void *osbuf) +{ + WMI_CMD_HDR *cmd; + A_UINT16 id; + A_UINT8 *datap; + A_UINT32 len, i, loggingReq; + A_STATUS status = A_OK; + + A_ASSERT(osbuf != NULL); + if (A_NETBUF_LEN(osbuf) < sizeof(WMI_CMD_HDR)) { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + A_NETBUF_FREE(osbuf); + return A_ERROR; + } + + cmd = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf); + id = cmd->commandId; + + if (A_NETBUF_PULL(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + A_NETBUF_FREE(osbuf); + return A_ERROR; + } + + datap = A_NETBUF_DATA(osbuf); + len = A_NETBUF_LEN(osbuf); + + loggingReq = 0; + + ar6000_get_driver_cfg(wmip->wmi_devt, + AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS, + &loggingReq); + + if(loggingReq) { + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI %d \n",id)); + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI recv, MsgNo %d : ", cmdRecvNum)); + for(i = 0; i < len; i++) + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("%x ", datap[i])); + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("\n")); + } + + LOCK_WMI(wmip); + cmdRecvNum++; + UNLOCK_WMI(wmip); + + switch (id) { + case (WMI_GET_BITRATE_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_BITRATE_CMDID\n", DBGARG)); + status = wmi_bitrate_reply_rx(wmip, datap, len); + break; + case (WMI_GET_CHANNEL_LIST_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_CHANNEL_LIST_CMDID\n", DBGARG)); + status = wmi_channelList_reply_rx(wmip, datap, len); + break; + case (WMI_GET_TX_PWR_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_TX_PWR_CMDID\n", DBGARG)); + status = wmi_txPwr_reply_rx(wmip, datap, len); + break; + case (WMI_READY_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_READY_EVENTID\n", DBGARG)); + status = wmi_ready_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + A_WMI_DBGLOG_INIT_DONE(wmip->wmi_devt); + break; + case (WMI_CONNECT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CONNECT_EVENTID\n", DBGARG)); + status = wmi_connect_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_DISCONNECT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_DISCONNECT_EVENTID\n", DBGARG)); + status = wmi_disconnect_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_PEER_NODE_EVENTID): + A_DPRINTF (DBG_WMI, (DBGFMT "WMI_PEER_NODE_EVENTID\n", DBGARG)); + status = wmi_peer_node_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_TKIP_MICERR_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TKIP_MICERR_EVENTID\n", DBGARG)); + status = wmi_tkip_micerr_event_rx(wmip, datap, len); + break; + case (WMI_BSSINFO_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BSSINFO_EVENTID\n", DBGARG)); + status = wmi_bssInfo_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_REGDOMAIN_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REGDOMAIN_EVENTID\n", DBGARG)); + status = wmi_regDomain_event_rx(wmip, datap, len); + break; + case (WMI_PSTREAM_TIMEOUT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_PSTREAM_TIMEOUT_EVENTID\n", DBGARG)); + status = wmi_pstream_timeout_event_rx(wmip, datap, len); + /* pstreams are fatpipe abstractions that get implicitly created. + * User apps only deal with thinstreams. creation of a thinstream + * by the user or data traffic flow in an AC triggers implicit + * pstream creation. Do we need to send this event to App..? + * no harm in sending it. + */ + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_NEIGHBOR_REPORT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_NEIGHBOR_REPORT_EVENTID\n", DBGARG)); + status = wmi_neighborReport_event_rx(wmip, datap, len); + break; + case (WMI_SCAN_COMPLETE_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SCAN_COMPLETE_EVENTID\n", DBGARG)); + status = wmi_scanComplete_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_CMDERROR_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CMDERROR_EVENTID\n", DBGARG)); + status = wmi_errorEvent_rx(wmip, datap, len); + break; + case (WMI_REPORT_STATISTICS_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_STATISTICS_EVENTID\n", DBGARG)); + status = wmi_statsEvent_rx(wmip, datap, len); + break; + case (WMI_RSSI_THRESHOLD_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_RSSI_THRESHOLD_EVENTID\n", DBGARG)); + status = wmi_rssiThresholdEvent_rx(wmip, datap, len); + break; + case (WMI_ERROR_REPORT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_ERROR_REPORT_EVENTID\n", DBGARG)); + status = wmi_reportErrorEvent_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_OPT_RX_FRAME_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_OPT_RX_FRAME_EVENTID\n", DBGARG)); + status = wmi_opt_frame_event_rx(wmip, datap, len); + break; + case (WMI_REPORT_ROAM_TBL_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_TBL_EVENTID\n", DBGARG)); + status = wmi_roam_tbl_event_rx(wmip, datap, len); + break; + case (WMI_EXTENSION_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_EXTENSION_EVENTID\n", DBGARG)); + status = wmi_control_rx_xtnd(wmip, osbuf); + break; + case (WMI_CAC_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CAC_EVENTID\n", DBGARG)); + status = wmi_cac_event_rx(wmip, datap, len); + break; + case (WMI_CHANNEL_CHANGE_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CHANNEL_CHANGE_EVENTID\n", DBGARG)); + status = wmi_channel_change_event_rx(wmip, datap, len); + break; + case (WMI_REPORT_ROAM_DATA_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_DATA_EVENTID\n", DBGARG)); + status = wmi_roam_data_event_rx(wmip, datap, len); + break; +#ifdef CONFIG_HOST_TCMD_SUPPORT + case (WMI_TEST_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TEST_EVENTID\n", DBGARG)); + status = wmi_tcmd_test_report_rx(wmip, datap, len); + break; +#endif + case (WMI_GET_FIXRATES_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_FIXRATES_CMDID\n", DBGARG)); + status = wmi_ratemask_reply_rx(wmip, datap, len); + break; + case (WMI_TX_RETRY_ERR_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TX_RETRY_ERR_EVENTID\n", DBGARG)); + status = wmi_txRetryErrEvent_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_SNR_THRESHOLD_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SNR_THRESHOLD_EVENTID\n", DBGARG)); + status = wmi_snrThresholdEvent_rx(wmip, datap, len); + break; + case (WMI_LQ_THRESHOLD_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_LQ_THRESHOLD_EVENTID\n", DBGARG)); + status = wmi_lqThresholdEvent_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_APLIST_EVENTID): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Received APLIST Event\n")); + status = wmi_aplistEvent_rx(wmip, datap, len); + break; + case (WMI_GET_KEEPALIVE_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_KEEPALIVE_CMDID\n", DBGARG)); + status = wmi_keepalive_reply_rx(wmip, datap, len); + break; + case (WMI_GET_WOW_LIST_EVENTID): + status = wmi_get_wow_list_event_rx(wmip, datap, len); + break; + case (WMI_GET_PMKID_LIST_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_PMKID_LIST Event\n", DBGARG)); + status = wmi_get_pmkid_list_event_rx(wmip, datap, len); + break; + case (WMI_PSPOLL_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_PSPOLL_EVENT\n", DBGARG)); + status = wmi_pspoll_event_rx(wmip, datap, len); + break; + case (WMI_DTIMEXPIRY_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_DTIMEXPIRY_EVENT\n", DBGARG)); + status = wmi_dtimexpiry_event_rx(wmip, datap, len); + break; + case (WMI_SET_PARAMS_REPLY_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SET_PARAMS_REPLY Event\n", DBGARG)); + status = wmi_set_params_event_rx(wmip, datap, len); + break; + default: + A_DPRINTF(DBG_WMI|DBG_ERROR, + (DBGFMT "Unknown id 0x%x\n", DBGARG, id)); + wmip->wmi_stats.cmd_id_err++; + status = A_ERROR; + break; + } + + A_NETBUF_FREE(osbuf); + + return status; +} + +/* Send a "simple" wmi command -- one with no arguments */ +static A_STATUS +wmi_simple_cmd(struct wmi_t *wmip, WMI_COMMAND_ID cmdid) +{ + void *osbuf; + + osbuf = A_NETBUF_ALLOC(0); + + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + return (wmi_cmd_send(wmip, osbuf, cmdid, NO_SYNC_WMIFLAG)); +} + +/* Send a "simple" extended wmi command -- one with no arguments. + Enabling this command only if GPIO or profiling support is enabled. + This is to suppress warnings on some platforms */ +#if defined(CONFIG_HOST_GPIO_SUPPORT) || defined(CONFIG_TARGET_PROFILE_SUPPORT) +static A_STATUS +wmi_simple_cmd_xtnd(struct wmi_t *wmip, WMIX_COMMAND_ID cmdid) +{ + void *osbuf; + + osbuf = A_NETBUF_ALLOC(0); + + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + return (wmi_cmd_send_xtnd(wmip, osbuf, cmdid, NO_SYNC_WMIFLAG)); +} +#endif + +static A_STATUS +wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_READY_EVENT *ev = (WMI_READY_EVENT *)datap; + + if (len < sizeof(WMI_READY_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + wmip->wmi_ready = TRUE; + A_WMI_READY_EVENT(wmip->wmi_devt, ev->macaddr, ev->phyCapability, + ev->version); + + return A_OK; +} + +#define LE_READ_4(p) \ + ((A_UINT32) \ + ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8) | \ + (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24))) + +static int __inline +iswmmoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((WMM_OUI_TYPE<<24)|WMM_OUI); +} + +static int __inline +iswmmparam(const A_UINT8 *frm) +{ + return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE; +} + + +static A_STATUS +wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CONNECT_EVENT *ev; + A_UINT8 *pie,*peie; + + if (len < sizeof(WMI_CONNECT_EVENT)) + { + return A_EINVAL; + } + ev = (WMI_CONNECT_EVENT *)datap; + + A_DPRINTF(DBG_WMI, + (DBGFMT "freq %d bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", + DBGARG, ev->channel, + ev->bssid[0], ev->bssid[1], ev->bssid[2], + ev->bssid[3], ev->bssid[4], ev->bssid[5])); + + A_MEMCPY(wmip->wmi_bssid, ev->bssid, ATH_MAC_LEN); + + /* initialize pointer to start of assoc rsp IEs */ + pie = ev->assocInfo + ev->beaconIeLen + ev->assocReqLen + + sizeof(A_UINT16) + /* capinfo*/ + sizeof(A_UINT16) + /* status Code */ + sizeof(A_UINT16) ; /* associd */ + + /* initialize pointer to end of assoc rsp IEs */ + peie = ev->assocInfo + ev->beaconIeLen + ev->assocReqLen + ev->assocRespLen; + + while (pie < peie) + { + switch (*pie) + { + case IEEE80211_ELEMID_VENDOR: + if (iswmmoui(pie)) + { + if(iswmmparam (pie)) + { + wmip->wmi_is_wmm_enabled = TRUE; + } + } + break; + } + + if (wmip->wmi_is_wmm_enabled) + { + break; + } + pie += pie[1] + 2; + } + + A_WMI_CONNECT_EVENT (wmip->wmi_devt, ev->channel, ev->bssid, + ev->listenInterval, ev->beaconInterval, + (NETWORK_TYPE) ev->networkType, ev->beaconIeLen, + ev->assocReqLen, ev->assocRespLen, + ev->assocInfo); + + return A_OK; +} + +static A_STATUS +wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_REG_DOMAIN_EVENT *ev; + + if (len < sizeof(*ev)) { + return A_EINVAL; + } + ev = (WMI_REG_DOMAIN_EVENT *)datap; + + A_WMI_REGDOMAIN_EVENT(wmip->wmi_devt, ev->regDomain); + + return A_OK; +} + +static A_STATUS +wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_NEIGHBOR_REPORT_EVENT *ev; + int numAps; + + if (len < sizeof(*ev)) { + return A_EINVAL; + } + ev = (WMI_NEIGHBOR_REPORT_EVENT *)datap; + numAps = ev->numberOfAps; + + if (len < (int)(sizeof(*ev) + ((numAps - 1) * sizeof(WMI_NEIGHBOR_INFO)))) { + return A_EINVAL; + } + + A_WMI_NEIGHBORREPORT_EVENT(wmip->wmi_devt, numAps, ev->neighbor); + + return A_OK; +} + +static A_STATUS +wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_DISCONNECT_EVENT *ev; + + if (len < sizeof(WMI_DISCONNECT_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + ev = (WMI_DISCONNECT_EVENT *)datap; + + A_MEMZERO(wmip->wmi_bssid, sizeof(wmip->wmi_bssid)); + + wmip->wmi_is_wmm_enabled = FALSE; + wmip->wmi_pair_crypto_type = NONE_CRYPT; + wmip->wmi_grp_crypto_type = NONE_CRYPT; + + A_WMI_DISCONNECT_EVENT(wmip->wmi_devt, ev->disconnectReason, ev->bssid, + ev->assocRespLen, ev->assocInfo, ev->protocolReasonStatus); + + return A_OK; +} + +static A_STATUS +wmi_peer_node_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_PEER_NODE_EVENT *ev; + + if (len < sizeof(WMI_PEER_NODE_EVENT)) { + return A_EINVAL; + } + ev = (WMI_PEER_NODE_EVENT *)datap; + if (ev->eventCode == PEER_NODE_JOIN_EVENT) { + A_DPRINTF (DBG_WMI, (DBGFMT "Joined node with Macaddr: ", DBGARG)); + } else if(ev->eventCode == PEER_NODE_LEAVE_EVENT) { + A_DPRINTF (DBG_WMI, (DBGFMT "left node with Macaddr: ", DBGARG)); + } + + A_WMI_PEER_EVENT (wmip->wmi_devt, ev->eventCode, ev->peerMacAddr); + + return A_OK; +} + +static A_STATUS +wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TKIP_MICERR_EVENT *ev; + + if (len < sizeof(*ev)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + ev = (WMI_TKIP_MICERR_EVENT *)datap; + A_WMI_TKIP_MICERR_EVENT(wmip->wmi_devt, ev->keyid, ev->ismcast); + + return A_OK; +} + +static A_STATUS +wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + bss_t *bss = NULL; + WMI_BSS_INFO_HDR *bih; + A_UINT8 *buf; + A_UINT32 nodeCachingAllowed = 1; + + if (len <= sizeof(WMI_BSS_INFO_HDR)) { + return A_EINVAL; + } + + bih = (WMI_BSS_INFO_HDR *)datap; + bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid); + + if (bih->rssi > 0) { + if (NULL == bss) + return A_OK; //no node found in the table, just drop the node with incorrect RSSI + else + bih->rssi = bss->ni_rssi; //Adjust RSSI in datap in case it is used in A_WMI_BSSINFO_EVENT_RX + } + + A_WMI_BSSINFO_EVENT_RX(wmip->wmi_devt, datap, len); + /* What is driver config for wlan node caching? */ + if(ar6000_get_driver_cfg(wmip->wmi_devt, + AR6000_DRIVER_CFG_GET_WLANNODECACHING, + &nodeCachingAllowed) != A_OK) { + return A_EINVAL; + } + + if(!nodeCachingAllowed) { + return A_OK; + } + + buf = datap + sizeof(WMI_BSS_INFO_HDR); + len -= sizeof(WMI_BSS_INFO_HDR); + + A_DPRINTF(DBG_WMI2, (DBGFMT "bssInfo event - ch %u, rssi %02x, " + "bssid \"%02x:%02x:%02x:%02x:%02x:%02x\"\n", DBGARG, + bih->channel, (unsigned char) bih->rssi, bih->bssid[0], + bih->bssid[1], bih->bssid[2], bih->bssid[3], bih->bssid[4], + bih->bssid[5])); + + if (bss != NULL) { + /* + * Free up the node. Not the most efficient process given + * we are about to allocate a new node but it is simple and should be + * adequate. + */ + wlan_node_reclaim(&wmip->wmi_scan_table, bss); + } + + bss = wlan_node_alloc(&wmip->wmi_scan_table, len); + if (bss == NULL) { + return A_NO_MEMORY; + } + + bss->ni_snr = bih->snr; + bss->ni_rssi = bih->rssi; + A_ASSERT(bss->ni_buf != NULL); + A_MEMCPY(bss->ni_buf, buf, len); + + if (wlan_parse_beacon(bss->ni_buf, len, &bss->ni_cie) != A_OK) { + wlan_node_free(bss); + return A_EINVAL; + } + + /* + * Update the frequency in ie_chan, overwriting of channel number + * which is done in wlan_parse_beacon + */ + bss->ni_cie.ie_chan = bih->channel; + wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid); + + return A_OK; +} + +static A_STATUS +wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + bss_t *bss; + WMI_OPT_RX_INFO_HDR *bih; + A_UINT8 *buf; + + if (len <= sizeof(WMI_OPT_RX_INFO_HDR)) { + return A_EINVAL; + } + + bih = (WMI_OPT_RX_INFO_HDR *)datap; + buf = datap + sizeof(WMI_OPT_RX_INFO_HDR); + len -= sizeof(WMI_OPT_RX_INFO_HDR); + + A_DPRINTF(DBG_WMI2, (DBGFMT "opt frame event %2.2x:%2.2x\n", DBGARG, + bih->bssid[4], bih->bssid[5])); + + bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid); + if (bss != NULL) { + /* + * Free up the node. Not the most efficient process given + * we are about to allocate a new node but it is simple and should be + * adequate. + */ + wlan_node_reclaim(&wmip->wmi_scan_table, bss); + } + + bss = wlan_node_alloc(&wmip->wmi_scan_table, len); + if (bss == NULL) { + return A_NO_MEMORY; + } + + bss->ni_snr = bih->snr; + bss->ni_cie.ie_chan = bih->channel; + A_ASSERT(bss->ni_buf != NULL); + A_MEMCPY(bss->ni_buf, buf, len); + wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid); + + return A_OK; +} + + /* This event indicates inactivity timeout of a fatpipe(pstream) + * at the target + */ +static A_STATUS +wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_PSTREAM_TIMEOUT_EVENT *ev; + + if (len < sizeof(WMI_PSTREAM_TIMEOUT_EVENT)) { + return A_EINVAL; + } + + A_DPRINTF(DBG_WMI, (DBGFMT "wmi_pstream_timeout_event_rx\n", DBGARG)); + + ev = (WMI_PSTREAM_TIMEOUT_EVENT *)datap; + + /* When the pstream (fat pipe == AC) timesout, it means there were no + * thinStreams within this pstream & it got implicitly created due to + * data flow on this AC. We start the inactivity timer only for + * implicitly created pstream. Just reset the host state. + */ + /* Set the activeTsids for this AC to 0 */ + LOCK_WMI(wmip); + wmip->wmi_streamExistsForAC[ev->trafficClass]=0; + wmip->wmi_fatPipeExists &= ~(1 << ev->trafficClass); + UNLOCK_WMI(wmip); + + /*Indicate inactivity to driver layer for this fatpipe (pstream)*/ + A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, ev->trafficClass); + + return A_OK; +} + +static A_STATUS +wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_BIT_RATE_REPLY *reply; + A_INT32 rate; + /* 54149: + * WMI_BIT_RATE_CMD structure is changed to WMI_BIT_RATE_REPLY. + * since there is difference in the length and to avoid returning + * error value. + */ + if (len < sizeof(WMI_BIT_RATE_REPLY)) { + return A_EINVAL; + } + reply = (WMI_BIT_RATE_REPLY *)datap; + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - rateindex %d\n", DBGARG, reply->rateIndex)); + + if (reply->rateIndex == (A_INT8) RATE_AUTO) { + rate = RATE_AUTO; + } else { + rate = wmi_rateTable[(A_UINT32) reply->rateIndex]; + } + + A_WMI_BITRATE_RX(wmip->wmi_devt, rate); + + return A_OK; +} + +static A_STATUS +wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_FIX_RATES_CMD *reply; + + if (len < sizeof(WMI_BIT_RATE_CMD)) { + return A_EINVAL; + } + reply = (WMI_FIX_RATES_CMD *)datap; + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - fixed rate mask %x\n", DBGARG, reply->fixRateMask)); + + A_WMI_RATEMASK_RX(wmip->wmi_devt, reply->fixRateMask); + + return A_OK; +} + +static A_STATUS +wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CHANNEL_LIST_REPLY *reply; + + if (len < sizeof(WMI_CHANNEL_LIST_REPLY)) { + return A_EINVAL; + } + reply = (WMI_CHANNEL_LIST_REPLY *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_CHANNELLIST_RX(wmip->wmi_devt, reply->numChannels, + reply->channelList); + + return A_OK; +} + +static A_STATUS +wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TX_PWR_REPLY *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TX_PWR_REPLY *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TXPWR_RX(wmip->wmi_devt, reply->dbM); + + return A_OK; +} +static A_STATUS +wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_GET_KEEPALIVE_CMD *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_GET_KEEPALIVE_CMD *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_KEEPALIVE_RX(wmip->wmi_devt, reply->configured); + + return A_OK; +} + + +static A_STATUS +wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_DSETOPENREQ_EVENT *dsetopenreq; + + if (len < sizeof(WMIX_DSETOPENREQ_EVENT)) { + return A_EINVAL; + } + dsetopenreq = (WMIX_DSETOPENREQ_EVENT *)datap; + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - dset_id=0x%x\n", DBGARG, dsetopenreq->dset_id)); + A_WMI_DSET_OPEN_REQ(wmip->wmi_devt, + dsetopenreq->dset_id, + dsetopenreq->targ_dset_handle, + dsetopenreq->targ_reply_fn, + dsetopenreq->targ_reply_arg); + + return A_OK; +} + +#ifdef CONFIG_HOST_DSET_SUPPORT +static A_STATUS +wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_DSETCLOSE_EVENT *dsetclose; + + if (len < sizeof(WMIX_DSETCLOSE_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + dsetclose = (WMIX_DSETCLOSE_EVENT *)datap; + A_WMI_DSET_CLOSE(wmip->wmi_devt, dsetclose->access_cookie); + + return A_OK; +} + +static A_STATUS +wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_DSETDATAREQ_EVENT *dsetdatareq; + + if (len < sizeof(WMIX_DSETDATAREQ_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + dsetdatareq = (WMIX_DSETDATAREQ_EVENT *)datap; + A_WMI_DSET_DATA_REQ(wmip->wmi_devt, + dsetdatareq->access_cookie, + dsetdatareq->offset, + dsetdatareq->length, + dsetdatareq->targ_buf, + dsetdatareq->targ_reply_fn, + dsetdatareq->targ_reply_arg); + + return A_OK; +} +#endif /* CONFIG_HOST_DSET_SUPPORT */ + +static A_STATUS +wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_SCAN_COMPLETE_EVENT *ev; + + ev = (WMI_SCAN_COMPLETE_EVENT *)datap; + A_WMI_SCANCOMPLETE_EVENT(wmip->wmi_devt, (A_STATUS) ev->status); + + return A_OK; +} + +/* + * Target is reporting a programming error. This is for + * developer aid only. Target only checks a few common violations + * and it is responsibility of host to do all error checking. + * Behavior of target after wmi error event is undefined. + * A reset is recommended. + */ +static A_STATUS +wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CMD_ERROR_EVENT *ev; + + ev = (WMI_CMD_ERROR_EVENT *)datap; + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Programming Error: cmd=%d ", ev->commandId)); + switch (ev->errorCode) { + case (INVALID_PARAM): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal Parameter\n")); + break; + case (ILLEGAL_STATE): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal State\n")); + break; + case (INTERNAL_ERROR): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Internal Error\n")); + break; + } + + return A_OK; +} + + +static A_STATUS +wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TARGET_STATS *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TARGET_STATS *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TARGETSTATS_EVENT(wmip->wmi_devt, reply); + + return A_OK; +} + +static A_STATUS +wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_RSSI_THRESHOLD_EVENT *reply; + WMI_RSSI_THRESHOLD_VAL newThreshold; + WMI_RSSI_THRESHOLD_PARAMS_CMD cmd; + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_RSSI]; + A_UINT8 upper_rssi_threshold, lower_rssi_threshold; + A_INT16 rssi; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_RSSI_THRESHOLD_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + newThreshold = (WMI_RSSI_THRESHOLD_VAL) reply->range; + rssi = reply->rssi; + + /* + * Identify the threshold breached and communicate that to the app. After + * that install a new set of thresholds based on the signal quality + * reported by the target + */ + if (newThreshold) { + /* Upper threshold breached */ + if (rssi < sq_thresh->upper_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious upper RSSI threshold event: " + " %d\n", DBGARG, rssi)); + } else if ((rssi < sq_thresh->upper_threshold[1]) && + (rssi >= sq_thresh->upper_threshold[0])) + { + newThreshold = WMI_RSSI_THRESHOLD1_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[2]) && + (rssi >= sq_thresh->upper_threshold[1])) + { + newThreshold = WMI_RSSI_THRESHOLD2_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[3]) && + (rssi >= sq_thresh->upper_threshold[2])) + { + newThreshold = WMI_RSSI_THRESHOLD3_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[4]) && + (rssi >= sq_thresh->upper_threshold[3])) + { + newThreshold = WMI_RSSI_THRESHOLD4_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[5]) && + (rssi >= sq_thresh->upper_threshold[4])) + { + newThreshold = WMI_RSSI_THRESHOLD5_ABOVE; + } else if (rssi >= sq_thresh->upper_threshold[5]) { + newThreshold = WMI_RSSI_THRESHOLD6_ABOVE; + } + } else { + /* Lower threshold breached */ + if (rssi > sq_thresh->lower_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious lower RSSI threshold event: " + "%d %d\n", DBGARG, rssi, sq_thresh->lower_threshold[0])); + } else if ((rssi > sq_thresh->lower_threshold[1]) && + (rssi <= sq_thresh->lower_threshold[0])) + { + newThreshold = WMI_RSSI_THRESHOLD6_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[2]) && + (rssi <= sq_thresh->lower_threshold[1])) + { + newThreshold = WMI_RSSI_THRESHOLD5_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[3]) && + (rssi <= sq_thresh->lower_threshold[2])) + { + newThreshold = WMI_RSSI_THRESHOLD4_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[4]) && + (rssi <= sq_thresh->lower_threshold[3])) + { + newThreshold = WMI_RSSI_THRESHOLD3_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[5]) && + (rssi <= sq_thresh->lower_threshold[4])) + { + newThreshold = WMI_RSSI_THRESHOLD2_BELOW; + } else if (rssi <= sq_thresh->lower_threshold[5]) { + newThreshold = WMI_RSSI_THRESHOLD1_BELOW; + } + } + /* Calculate and install the next set of thresholds */ + lower_rssi_threshold = ar6000_get_lower_threshold(rssi, sq_thresh, + sq_thresh->lower_threshold_valid_count); + upper_rssi_threshold = ar6000_get_upper_threshold(rssi, sq_thresh, + sq_thresh->upper_threshold_valid_count); + /* Issue a wmi command to install the thresholds */ + cmd.thresholdAbove1_Val = upper_rssi_threshold; + cmd.thresholdBelow1_Val = lower_rssi_threshold; + cmd.weight = sq_thresh->weight; + cmd.pollTime = sq_thresh->polling_interval; + + rssi_event_value = rssi; + + if (wmi_send_rssi_threshold_params(wmip, &cmd) != A_OK) { + A_DPRINTF(DBG_WMI, (DBGFMT "Unable to configure the RSSI thresholds\n", + DBGARG)); + } + + A_WMI_RSSI_THRESHOLD_EVENT(wmip->wmi_devt, newThreshold, reply->rssi); + + return A_OK; +} + + +static A_STATUS +wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TARGET_ERROR_REPORT_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TARGET_ERROR_REPORT_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_REPORT_ERROR_EVENT(wmip->wmi_devt, (WMI_TARGET_ERROR_VAL) reply->errorVal); + + return A_OK; +} + +static A_STATUS +wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CAC_EVENT *reply; + WMM_TSPEC_IE *tspec_ie; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_CAC_EVENT *)datap; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + if ((reply->cac_indication == CAC_INDICATION_ADMISSION_RESP) && + (reply->statusCode != TSPEC_STATUS_CODE_ADMISSION_ACCEPTED)) { + tspec_ie = (WMM_TSPEC_IE *) &(reply->tspecSuggestion); + + wmi_delete_pstream_cmd(wmip, reply->ac, + (tspec_ie->tsInfo_info >> TSPEC_TSID_S) & TSPEC_TSID_MASK); + } + else if (reply->cac_indication == CAC_INDICATION_NO_RESP) { + A_UINT16 activeTsids; + A_UINT8 i; + + /* following assumes that there is only one outstanding ADDTS request + when this event is received */ + LOCK_WMI(wmip); + activeTsids = wmip->wmi_streamExistsForAC[reply->ac]; + UNLOCK_WMI(wmip); + + for (i = 0; i < sizeof(activeTsids) * 8; i++) { + if ((activeTsids >> i) & 1) { + break; + } + } + if (i < (sizeof(activeTsids) * 8)) { + wmi_delete_pstream_cmd(wmip, reply->ac, i); + } + } + + A_WMI_CAC_EVENT(wmip->wmi_devt, reply->ac, + reply->cac_indication, reply->statusCode, + reply->tspecSuggestion); + + return A_OK; +} + +static A_STATUS +wmi_channel_change_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CHANNEL_CHANGE_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_CHANNEL_CHANGE_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_CHANNEL_CHANGE_EVENT(wmip->wmi_devt, reply->oldChannel, + reply->newChannel); + + return A_OK; +} + +static A_STATUS +wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_HB_CHALLENGE_RESP_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMIX_HB_CHALLENGE_RESP_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "wmi: challenge response event\n", DBGARG)); + + A_WMI_HBCHALLENGERESP_EVENT(wmip->wmi_devt, reply->cookie, reply->source); + + return A_OK; +} + +static A_STATUS +wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TARGET_ROAM_TBL *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TARGET_ROAM_TBL *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_ROAM_TABLE_EVENT(wmip->wmi_devt, reply); + + return A_OK; +} + +static A_STATUS +wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TARGET_ROAM_DATA *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TARGET_ROAM_DATA *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_ROAM_DATA_EVENT(wmip->wmi_devt, reply); + + return A_OK; +} + +static A_STATUS +wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + if (len < sizeof(WMI_TX_RETRY_ERR_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TX_RETRY_ERR_EVENT(wmip->wmi_devt); + + return A_OK; +} + +static A_STATUS +wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_SNR_THRESHOLD_EVENT *reply; + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_SNR]; + WMI_SNR_THRESHOLD_VAL newThreshold; + WMI_SNR_THRESHOLD_PARAMS_CMD cmd; + A_UINT8 upper_snr_threshold, lower_snr_threshold; + A_INT16 snr; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_SNR_THRESHOLD_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + newThreshold = (WMI_SNR_THRESHOLD_VAL) reply->range; + snr = reply->snr; + /* + * Identify the threshold breached and communicate that to the app. After + * that install a new set of thresholds based on the signal quality + * reported by the target + */ + if (newThreshold) { + /* Upper threshold breached */ + if (snr < sq_thresh->upper_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious upper SNR threshold event: " + "%d\n", DBGARG, snr)); + } else if ((snr < sq_thresh->upper_threshold[1]) && + (snr >= sq_thresh->upper_threshold[0])) + { + newThreshold = WMI_SNR_THRESHOLD1_ABOVE; + } else if ((snr < sq_thresh->upper_threshold[2]) && + (snr >= sq_thresh->upper_threshold[1])) + { + newThreshold = WMI_SNR_THRESHOLD2_ABOVE; + } else if ((snr < sq_thresh->upper_threshold[3]) && + (snr >= sq_thresh->upper_threshold[2])) + { + newThreshold = WMI_SNR_THRESHOLD3_ABOVE; + } else if (snr >= sq_thresh->upper_threshold[3]) { + newThreshold = WMI_SNR_THRESHOLD4_ABOVE; + } + } else { + /* Lower threshold breached */ + if (snr > sq_thresh->lower_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious lower SNR threshold event: " + "%d %d\n", DBGARG, snr, sq_thresh->lower_threshold[0])); + } else if ((snr > sq_thresh->lower_threshold[1]) && + (snr <= sq_thresh->lower_threshold[0])) + { + newThreshold = WMI_SNR_THRESHOLD4_BELOW; + } else if ((snr > sq_thresh->lower_threshold[2]) && + (snr <= sq_thresh->lower_threshold[1])) + { + newThreshold = WMI_SNR_THRESHOLD3_BELOW; + } else if ((snr > sq_thresh->lower_threshold[3]) && + (snr <= sq_thresh->lower_threshold[2])) + { + newThreshold = WMI_SNR_THRESHOLD2_BELOW; + } else if (snr <= sq_thresh->lower_threshold[3]) { + newThreshold = WMI_SNR_THRESHOLD1_BELOW; + } + } + + /* Calculate and install the next set of thresholds */ + lower_snr_threshold = ar6000_get_lower_threshold(snr, sq_thresh, + sq_thresh->lower_threshold_valid_count); + upper_snr_threshold = ar6000_get_upper_threshold(snr, sq_thresh, + sq_thresh->upper_threshold_valid_count); + + /* Issue a wmi command to install the thresholds */ + cmd.thresholdAbove1_Val = upper_snr_threshold; + cmd.thresholdBelow1_Val = lower_snr_threshold; + cmd.weight = sq_thresh->weight; + cmd.pollTime = sq_thresh->polling_interval; + + A_DPRINTF(DBG_WMI, (DBGFMT "snr: %d, threshold: %d, lower: %d, upper: %d\n" + ,DBGARG, snr, newThreshold, lower_snr_threshold, + upper_snr_threshold)); + + snr_event_value = snr; + + if (wmi_send_snr_threshold_params(wmip, &cmd) != A_OK) { + A_DPRINTF(DBG_WMI, (DBGFMT "Unable to configure the SNR thresholds\n", + DBGARG)); + } + A_WMI_SNR_THRESHOLD_EVENT_RX(wmip->wmi_devt, newThreshold, reply->snr); + + return A_OK; +} + +static A_STATUS +wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_LQ_THRESHOLD_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_LQ_THRESHOLD_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_LQ_THRESHOLD_EVENT_RX(wmip->wmi_devt, + (WMI_LQ_THRESHOLD_VAL) reply->range, + reply->lq); + + return A_OK; +} + +static A_STATUS +wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + A_UINT16 ap_info_entry_size; + WMI_APLIST_EVENT *ev = (WMI_APLIST_EVENT *)datap; + WMI_AP_INFO_V1 *ap_info_v1; + A_UINT8 i; + + if (len < sizeof(WMI_APLIST_EVENT)) { + return A_EINVAL; + } + + if (ev->apListVer == APLIST_VER1) { + ap_info_entry_size = sizeof(WMI_AP_INFO_V1); + ap_info_v1 = (WMI_AP_INFO_V1 *)ev->apList; + } else { + return A_EINVAL; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Number of APs in APLIST Event is %d\n", ev->numAP)); + if (len < (int)(sizeof(WMI_APLIST_EVENT) + + (ev->numAP - 1) * ap_info_entry_size)) + { + return A_EINVAL; + } + + /* + * AP List Ver1 Contents + */ + for (i = 0; i < ev->numAP; i++) { + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("AP#%d BSSID %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x "\ + "Channel %d\n", i, + ap_info_v1->bssid[0], ap_info_v1->bssid[1], + ap_info_v1->bssid[2], ap_info_v1->bssid[3], + ap_info_v1->bssid[4], ap_info_v1->bssid[5], + ap_info_v1->channel)); + ap_info_v1++; + } + return A_OK; +} + +static A_STATUS +wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + A_UINT32 dropped; + + dropped = *((A_UINT32 *)datap); + datap += sizeof(dropped); + len -= sizeof(dropped); + A_WMI_DBGLOG_EVENT(wmip->wmi_devt, dropped, datap, len); + return A_OK; +} + +#ifdef CONFIG_HOST_GPIO_SUPPORT +static A_STATUS +wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_GPIO_INTR_EVENT *gpio_intr = (WMIX_GPIO_INTR_EVENT *)datap; + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - intrmask=0x%x input=0x%x.\n", DBGARG, + gpio_intr->intr_mask, gpio_intr->input_values)); + + A_WMI_GPIO_INTR_RX(gpio_intr->intr_mask, gpio_intr->input_values); + + return A_OK; +} + +static A_STATUS +wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_GPIO_DATA_EVENT *gpio_data = (WMIX_GPIO_DATA_EVENT *)datap; + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG, + gpio_data->reg_id, gpio_data->value)); + + A_WMI_GPIO_DATA_RX(gpio_data->reg_id, gpio_data->value); + + return A_OK; +} + +static A_STATUS +wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_GPIO_ACK_RX(); + + return A_OK; +} +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +/* + * Called to send a wmi command. Command specific data is already built + * on osbuf and current osbuf->data points to it. + */ +A_STATUS +wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId, + WMI_SYNC_FLAG syncflag) +{ +#define IS_OPT_TX_CMD(cmdId) ((cmdId == WMI_OPT_TX_FRAME_CMDID)) + WMI_CMD_HDR *cHdr; + HTC_ENDPOINT_ID eid = wmip->wmi_endpoint_id; + + A_ASSERT(osbuf != NULL); + + if (syncflag >= END_WMIFLAG) { + return A_EINVAL; + } + + if ((syncflag == SYNC_BEFORE_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) { + /* + * We want to make sure all data currently queued is transmitted before + * the cmd execution. Establish a new sync point. + */ + wmi_sync_point(wmip); + } + + if (A_NETBUF_PUSH(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + cHdr = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf); + cHdr->commandId = (A_UINT16) cmdId; + + /* + * Only for OPT_TX_CMD, use BE endpoint. + */ + if (IS_OPT_TX_CMD(cmdId)) { + wmi_data_hdr_add(wmip, osbuf, OPT_MSGTYPE, FALSE); + eid = A_WMI_Ac2EndpointID(wmip->wmi_devt, WMM_AC_BE); + } + A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, eid); + + if ((syncflag == SYNC_AFTER_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) { + /* + * We want to make sure all new data queued waits for the command to + * execute. Establish a new sync point. + */ + wmi_sync_point(wmip); + } + return (A_OK); +#undef IS_OPT_TX_CMD +} + +A_STATUS +wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMIX_COMMAND_ID cmdId, + WMI_SYNC_FLAG syncflag) +{ + WMIX_CMD_HDR *cHdr; + + if (A_NETBUF_PUSH(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + cHdr = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf); + cHdr->commandId = (A_UINT32) cmdId; + + return wmi_cmd_send(wmip, osbuf, WMI_EXTENSION_CMDID, syncflag); +} + +A_STATUS +wmi_connect_cmd(struct wmi_t *wmip, NETWORK_TYPE netType, + DOT11_AUTH_MODE dot11AuthMode, AUTH_MODE authMode, + CRYPTO_TYPE pairwiseCrypto, A_UINT8 pairwiseCryptoLen, + CRYPTO_TYPE groupCrypto, A_UINT8 groupCryptoLen, + int ssidLength, A_UCHAR *ssid, + A_UINT8 *bssid, A_UINT16 channel, A_UINT32 ctrl_flags) +{ + void *osbuf; + WMI_CONNECT_CMD *cc; + + if ((pairwiseCrypto == NONE_CRYPT) && (groupCrypto != NONE_CRYPT)) { + return A_EINVAL; + } + if ((pairwiseCrypto != NONE_CRYPT) && (groupCrypto == NONE_CRYPT)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_CONNECT_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_CONNECT_CMD)); + + cc = (WMI_CONNECT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cc, sizeof(*cc)); + + if (ssidLength) + { + A_MEMCPY(cc->ssid, ssid, ssidLength); + } + + cc->ssidLength = ssidLength; + cc->networkType = netType; + cc->dot11AuthMode = dot11AuthMode; + cc->authMode = authMode; + cc->pairwiseCryptoType = pairwiseCrypto; + cc->pairwiseCryptoLen = pairwiseCryptoLen; + cc->groupCryptoType = groupCrypto; + cc->groupCryptoLen = groupCryptoLen; + cc->channel = channel; + cc->ctrl_flags = ctrl_flags; + + if (bssid != NULL) { + A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN); + } + if (wmi_set_keepalive_cmd(wmip, wmip->wmi_keepaliveInterval) != A_OK) { + return(A_ERROR); + } + + wmip->wmi_pair_crypto_type = pairwiseCrypto; + wmip->wmi_grp_crypto_type = groupCrypto; + + return (wmi_cmd_send(wmip, osbuf, WMI_CONNECT_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_reconnect_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT16 channel) +{ + void *osbuf; + WMI_RECONNECT_CMD *cc; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_RECONNECT_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_RECONNECT_CMD)); + + cc = (WMI_RECONNECT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cc, sizeof(*cc)); + + cc->channel = channel; + + if (bssid != NULL) { + A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_RECONNECT_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_disconnect_cmd(struct wmi_t *wmip) +{ + A_STATUS status; + + /* Bug fix for 24817(elevator bug) - the disconnect command does not + need to do a SYNC before.*/ + status = wmi_simple_cmd(wmip, WMI_DISCONNECT_CMDID); + + return status; +} + +A_STATUS +wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType, + A_BOOL forceFgScan, A_BOOL isLegacy, + A_UINT32 homeDwellTime, A_UINT32 forceScanInterval, + A_INT8 numChan, A_UINT16 *channelList) +{ + void *osbuf; + WMI_START_SCAN_CMD *sc; + A_INT8 size; + + size = sizeof (*sc); + + if ((scanType != WMI_LONG_SCAN) && (scanType != WMI_SHORT_SCAN)) { + return A_EINVAL; + } + + if (numChan) { + if (numChan > WMI_MAX_CHANNELS) { + return A_EINVAL; + } + size += sizeof(A_UINT16) * (numChan - 1); + } + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + sc = (WMI_START_SCAN_CMD *)(A_NETBUF_DATA(osbuf)); + sc->scanType = scanType; + sc->forceFgScan = forceFgScan; + sc->isLegacy = isLegacy; + sc->homeDwellTime = homeDwellTime; + sc->forceScanInterval = forceScanInterval; + sc->numChannels = numChan; + if (numChan) { + A_MEMCPY(sc->channelList, channelList, numChan * sizeof(A_UINT16)); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_START_SCAN_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec, + A_UINT16 fg_end_sec, A_UINT16 bg_sec, + A_UINT16 minact_chdw_msec, A_UINT16 maxact_chdw_msec, + A_UINT16 pas_chdw_msec, + A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags, + A_UINT32 max_dfsch_act_time, A_UINT16 maxact_scan_per_ssid) +{ + void *osbuf; + WMI_SCAN_PARAMS_CMD *sc; + + osbuf = A_NETBUF_ALLOC(sizeof(*sc)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*sc)); + + sc = (WMI_SCAN_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(sc, sizeof(*sc)); + sc->fg_start_period = fg_start_sec; + sc->fg_end_period = fg_end_sec; + sc->bg_period = bg_sec; + sc->minact_chdwell_time = minact_chdw_msec; + sc->maxact_chdwell_time = maxact_chdw_msec; + sc->pas_chdwell_time = pas_chdw_msec; + sc->shortScanRatio = shScanRatio; + sc->scanCtrlFlags = scanCtrlFlags; + sc->max_dfsch_act_time = max_dfsch_act_time; + sc->maxact_scan_per_ssid = maxact_scan_per_ssid; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_SCAN_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask) +{ + void *osbuf; + WMI_BSS_FILTER_CMD *cmd; + + if (filter >= LAST_BSS_FILTER) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_BSS_FILTER_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->bssFilter = filter; + cmd->ieMask = ieMask; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BSS_FILTER_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag, + A_UINT8 ssidLength, A_UCHAR *ssid) +{ + void *osbuf; + WMI_PROBED_SSID_CMD *cmd; + + if (index > MAX_PROBED_SSID_INDEX) { + return A_EINVAL; + } + if (ssidLength > sizeof(cmd->ssid)) { + return A_EINVAL; + } + if ((flag & (DISABLE_SSID_FLAG | ANY_SSID_FLAG)) && (ssidLength > 0)) { + return A_EINVAL; + } + if ((flag & SPECIFIC_SSID_FLAG) && !ssidLength) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_PROBED_SSID_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->entryIndex = index; + cmd->flag = flag; + cmd->ssidLength = ssidLength; + A_MEMCPY(cmd->ssid, ssid, ssidLength); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PROBED_SSID_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons) +{ + void *osbuf; + WMI_LISTEN_INT_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_LISTEN_INT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->listenInterval = listenInterval; + cmd->numBeacons = listenBeacons; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_LISTEN_INT_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmissTime, A_UINT16 bmissBeacons) +{ + void *osbuf; + WMI_BMISS_TIME_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_BMISS_TIME_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->bmissTime = bmissTime; + cmd->numBeacons = bmissBeacons; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BMISS_TIME_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType, + A_UINT8 ieLen, A_UINT8 *ieInfo) +{ + void *osbuf; + WMI_SET_ASSOC_INFO_CMD *cmd; + A_UINT16 cmdLen; + + cmdLen = sizeof(*cmd) + ieLen - 1; + osbuf = A_NETBUF_ALLOC(cmdLen); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, cmdLen); + + cmd = (WMI_SET_ASSOC_INFO_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + cmd->ieType = ieType; + cmd->bufferSize = ieLen; + A_MEMCPY(cmd->assocInfo, ieInfo, ieLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_ASSOC_INFO_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode) +{ + void *osbuf; + WMI_POWER_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_POWER_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->powerMode = powerMode; + wmip->wmi_powerMode = powerMode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl, + A_UINT16 atim_windows, A_UINT16 timeout_value) +{ + void *osbuf; + WMI_IBSS_PM_CAPS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_IBSS_PM_CAPS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->power_saving = pmEnable; + cmd->ttl = ttl; + cmd->atim_windows = atim_windows; + cmd->timeout_value = timeout_value; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_IBSS_PM_CAPS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod, + A_UINT16 psPollNum, A_UINT16 dtimPolicy) +{ + void *osbuf; + WMI_POWER_PARAMS_CMD *pm; + + osbuf = A_NETBUF_ALLOC(sizeof(*pm)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*pm)); + + pm = (WMI_POWER_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(pm, sizeof(*pm)); + pm->idle_period = idlePeriod; + pm->pspoll_number = psPollNum; + pm->dtim_policy = dtimPolicy; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout) +{ + void *osbuf; + WMI_DISC_TIMEOUT_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DISC_TIMEOUT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->disconnectTimeout = timeout; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_DISC_TIMEOUT_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex, CRYPTO_TYPE keyType, + A_UINT8 keyUsage, A_UINT8 keyLength, A_UINT8 *keyRSC, + A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl, A_UINT8 *macAddr, + WMI_SYNC_FLAG sync_flag) +{ + void *osbuf; + WMI_ADD_CIPHER_KEY_CMD *cmd; + + if ((keyIndex > WMI_MAX_KEY_INDEX) || (keyLength > WMI_MAX_KEY_LEN) || + (keyMaterial == NULL)) + { + return A_EINVAL; + } + + if ((WEP_CRYPT != keyType) && (NULL == keyRSC)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_ADD_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->keyIndex = keyIndex; + cmd->keyType = keyType; + cmd->keyUsage = keyUsage; + cmd->keyLength = keyLength; + A_MEMCPY(cmd->key, keyMaterial, keyLength); +#ifdef WAPI_ENABLE + if (NULL != keyRSC && key_op_ctrl != KEY_OP_INIT_WAPIPN) { +#else + if (NULL != keyRSC) { +#endif // WAPI_ENABLE + A_MEMCPY(cmd->keyRSC, keyRSC, sizeof(cmd->keyRSC)); + } + cmd->key_op_ctrl = key_op_ctrl; + + if(macAddr) { + A_MEMCPY(cmd->key_macaddr,macAddr,IEEE80211_ADDR_LEN); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_CIPHER_KEY_CMDID, sync_flag)); +} + +A_STATUS +wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk) +{ + void *osbuf; + WMI_ADD_KRK_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_ADD_KRK_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + A_MEMCPY(cmd->krk, krk, WMI_KRK_LEN); + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_KRK_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_delete_krk_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_DELETE_KRK_CMDID); +} + +A_STATUS +wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex) +{ + void *osbuf; + WMI_DELETE_CIPHER_KEY_CMD *cmd; + + if (keyIndex > WMI_MAX_KEY_INDEX) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DELETE_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->keyIndex = keyIndex; + + return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_CIPHER_KEY_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId, + A_BOOL set) +{ + void *osbuf; + WMI_SET_PMKID_CMD *cmd; + + if (bssid == NULL) { + return A_EINVAL; + } + + if ((set == TRUE) && (pmkId == NULL)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_PMKID_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid)); + if (set == TRUE) { + A_MEMCPY(cmd->pmkid, pmkId, sizeof(cmd->pmkid)); + cmd->enable = PMKID_ENABLE; + } else { + A_MEMZERO(cmd->pmkid, sizeof(cmd->pmkid)); + cmd->enable = PMKID_DISABLE; + } + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en) +{ + void *osbuf; + WMI_SET_TKIP_COUNTERMEASURES_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_TKIP_COUNTERMEASURES_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->cm_en = (en == TRUE)? WMI_TKIP_CM_ENABLE : WMI_TKIP_CM_DISABLE; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_TKIP_COUNTERMEASURES_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_akmp_params_cmd(struct wmi_t *wmip, + WMI_SET_AKMP_PARAMS_CMD *akmpParams) +{ + void *osbuf; + WMI_SET_AKMP_PARAMS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + cmd = (WMI_SET_AKMP_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->akmpInfo = akmpParams->akmpInfo; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_AKMP_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_pmkid_list_cmd(struct wmi_t *wmip, + WMI_SET_PMKID_LIST_CMD *pmkInfo) +{ + void *osbuf; + WMI_SET_PMKID_LIST_CMD *cmd; + A_UINT16 cmdLen; + A_UINT8 i; + + cmdLen = sizeof(pmkInfo->numPMKID) + + pmkInfo->numPMKID * sizeof(WMI_PMKID); + + osbuf = A_NETBUF_ALLOC(cmdLen); + + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, cmdLen); + cmd = (WMI_SET_PMKID_LIST_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->numPMKID = pmkInfo->numPMKID; + + for (i = 0; i < cmd->numPMKID; i++) { + A_MEMCPY(&cmd->pmkidList[i], &pmkInfo->pmkidList[i], + WMI_PMKID_LEN); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_LIST_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_pmkid_list_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_PMKID_LIST_CMDID); +} + +A_STATUS +wmi_dataSync_send(struct wmi_t *wmip, void *osbuf, HTC_ENDPOINT_ID eid) +{ + WMI_DATA_HDR *dtHdr; + + A_ASSERT( eid != wmip->wmi_endpoint_id); + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf); + dtHdr->info = + (SYNC_MSGTYPE & WMI_DATA_HDR_MSG_TYPE_MASK) << WMI_DATA_HDR_MSG_TYPE_SHIFT; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter - eid %d\n", DBGARG, eid)); + + return (A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, eid)); +} + +typedef struct _WMI_DATA_SYNC_BUFS { + A_UINT8 trafficClass; + void *osbuf; +}WMI_DATA_SYNC_BUFS; + +static A_STATUS +wmi_sync_point(struct wmi_t *wmip) +{ + void *cmd_osbuf; + WMI_SYNC_CMD *cmd; + WMI_DATA_SYNC_BUFS dataSyncBufs[WMM_NUM_AC]; + A_UINT8 i,numPriStreams=0; + A_STATUS status = A_OK; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + memset(dataSyncBufs,0,sizeof(dataSyncBufs)); + + /* lock out while we walk through the priority list and assemble our local array */ + LOCK_WMI(wmip); + + for (i=0; i < WMM_NUM_AC ; i++) { + if (wmip->wmi_fatPipeExists & (1 << i)) { + numPriStreams++; + dataSyncBufs[numPriStreams-1].trafficClass = i; + } + } + + UNLOCK_WMI(wmip); + + /* dataSyncBufs is now filled with entries (starting at index 0) containing valid streamIDs */ + + do { + /* + * We allocate all network buffers needed so we will be able to + * send all required frames. + */ + cmd_osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (cmd_osbuf == NULL) { + status = A_NO_MEMORY; + break; + } + + A_NETBUF_PUT(cmd_osbuf, sizeof(*cmd)); + + cmd = (WMI_SYNC_CMD *)(A_NETBUF_DATA(cmd_osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + /* In the SYNC cmd sent on the control Ep, send a bitmap of the data + * eps on which the Data Sync will be sent + */ + cmd->dataSyncMap = wmip->wmi_fatPipeExists; + + for (i=0; i < numPriStreams ; i++) { + dataSyncBufs[i].osbuf = A_NETBUF_ALLOC(0); + if (dataSyncBufs[i].osbuf == NULL) { + status = A_NO_MEMORY; + break; + } + } //end for + + /* if Buffer allocation for any of the dataSync fails, then do not + * send the Synchronize cmd on the control ep + */ + if (A_FAILED(status)) { + break; + } + + /* + * Send sync cmd followed by sync data messages on all endpoints being + * used + */ + status = wmi_cmd_send(wmip, cmd_osbuf, WMI_SYNCHRONIZE_CMDID, + NO_SYNC_WMIFLAG); + + if (A_FAILED(status)) { + break; + } + /* cmd buffer sent, we no longer own it */ + cmd_osbuf = NULL; + + for(i=0; i < numPriStreams; i++) { + A_ASSERT(dataSyncBufs[i].osbuf != NULL); + status = wmi_dataSync_send(wmip, + dataSyncBufs[i].osbuf, + A_WMI_Ac2EndpointID(wmip->wmi_devt, + dataSyncBufs[i]. + trafficClass) + ); + + if (A_FAILED(status)) { + break; + } + /* we don't own this buffer anymore, NULL it out of the array so it + * won't get cleaned up */ + dataSyncBufs[i].osbuf = NULL; + } //end for + + } while(FALSE); + + /* free up any resources left over (possibly due to an error) */ + + if (cmd_osbuf != NULL) { + A_NETBUF_FREE(cmd_osbuf); + } + + for (i = 0; i < numPriStreams; i++) { + if (dataSyncBufs[i].osbuf != NULL) { + A_NETBUF_FREE(dataSyncBufs[i].osbuf); + } + } + + return (status); +} + +A_STATUS +wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *params) +{ + void *osbuf; + WMI_CREATE_PSTREAM_CMD *cmd; + A_UINT8 fatPipeExistsForAC=0; + A_INT32 minimalPHY = 0; + A_INT32 nominalPHY = 0; + + /* Validate all the parameters. */ + if( !((params->userPriority < 8) && + (params->userPriority <= 0x7) && + (convert_userPriority_to_trafficClass(params->userPriority) == params->trafficClass) && + (params->trafficDirection == UPLINK_TRAFFIC || + params->trafficDirection == DNLINK_TRAFFIC || + params->trafficDirection == BIDIR_TRAFFIC) && + (params->trafficType == TRAFFIC_TYPE_APERIODIC || + params->trafficType == TRAFFIC_TYPE_PERIODIC ) && + (params->voicePSCapability == DISABLE_FOR_THIS_AC || + params->voicePSCapability == ENABLE_FOR_THIS_AC || + params->voicePSCapability == ENABLE_FOR_ALL_AC) && + (params->tsid == WMI_IMPLICIT_PSTREAM || params->tsid <= WMI_MAX_THINSTREAM)) ) + { + return A_EINVAL; + } + + // + // check nominal PHY rate is >= minimalPHY, so that DUT + // can allow TSRS IE + // + + // get the physical rate + minimalPHY = ((params->minPhyRate / 1000)/1000); // unit of bps + + // check minimal phy < nominal phy rate + // + if (params->nominalPHY >= minimalPHY) + { + nominalPHY = (params->nominalPHY * 1000)/500; // unit of 500 kbps + A_DPRINTF(DBG_WMI, + (DBGFMT "TSRS IE Enabled::MinPhy %x->NominalPhy ===> %x\n", DBGARG, + minimalPHY, nominalPHY)); + + params->nominalPHY = nominalPHY; + } + else + { + params->nominalPHY = 0; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + A_DPRINTF(DBG_WMI, + (DBGFMT "Sending create_pstream_cmd: ac=%d tsid:%d\n", DBGARG, + params->trafficClass, params->tsid)); + + cmd = (WMI_CREATE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + A_MEMCPY(cmd, params, sizeof(*cmd)); + + /* this is an implicitly created Fat pipe */ + if (params->tsid == WMI_IMPLICIT_PSTREAM) { + LOCK_WMI(wmip); + fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass)); + wmip->wmi_fatPipeExists |= (1<trafficClass); + UNLOCK_WMI(wmip); + } else { + /* this is an explicitly created thin stream within a fat pipe */ + LOCK_WMI(wmip); + fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass)); + wmip->wmi_streamExistsForAC[params->trafficClass] |= (1<tsid); + /* if a thinstream becomes active, the fat pipe automatically + * becomes active + */ + wmip->wmi_fatPipeExists |= (1<trafficClass); + UNLOCK_WMI(wmip); + } + + /* Indicate activty change to driver layer only if this is the + * first TSID to get created in this AC explicitly or an implicit + * fat pipe is getting created. + */ + if (!fatPipeExistsForAC) { + A_WMI_STREAM_TX_ACTIVE(wmip->wmi_devt, params->trafficClass); + } + + /* mike: should be SYNC_BEFORE_WMIFLAG */ + return (wmi_cmd_send(wmip, osbuf, WMI_CREATE_PSTREAM_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 tsid) +{ + void *osbuf; + WMI_DELETE_PSTREAM_CMD *cmd; + A_STATUS status; + A_UINT16 activeTsids=0; + + /* validate the parameters */ + if (trafficClass > 3) { + A_DPRINTF(DBG_WMI, (DBGFMT "Invalid trafficClass: %d\n", DBGARG, trafficClass)); + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DELETE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->trafficClass = trafficClass; + cmd->tsid = tsid; + + LOCK_WMI(wmip); + activeTsids = wmip->wmi_streamExistsForAC[trafficClass]; + UNLOCK_WMI(wmip); + + /* Check if the tsid was created & exists */ + if (!(activeTsids & (1<wmi_streamExistsForAC[trafficClass] &= ~(1<wmi_streamExistsForAC[trafficClass]; + UNLOCK_WMI(wmip); + + + /* Indicate stream inactivity to driver layer only if all tsids + * within this AC are deleted. + */ + if(!activeTsids) { + A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, trafficClass); + wmip->wmi_fatPipeExists &= ~(1< 15)){ + + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_FRAME_RATES_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + frameType = (A_UINT8)((subType << 4) | type); + + cmd->bEnableMask = bEnable; + cmd->frameType = frameType; + cmd->frameRateMask = rateMask; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_FRAMERATES_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * used to set the bit rate. rate is in Kbps. If rate == -1 + * then auto selection is used. + */ +A_STATUS +wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 dataRate, A_INT32 mgmtRate, A_INT32 ctlRate) +{ + void *osbuf; + WMI_BIT_RATE_CMD *cmd; + A_INT8 drix, mrix, crix; + + if (dataRate != -1) { + drix = wmi_validate_bitrate(wmip, dataRate); + if(drix == A_EINVAL){ + return A_EINVAL; + } + } else { + drix = -1; + } + + if (mgmtRate != -1) { + mrix = wmi_validate_bitrate(wmip, mgmtRate); + if(mrix == A_EINVAL){ + return A_EINVAL; + } + } else { + mrix = -1; + } + if (ctlRate != -1) { + crix = wmi_validate_bitrate(wmip, ctlRate); + if(crix == A_EINVAL){ + return A_EINVAL; + } + } else { + crix = -1; + } + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_BIT_RATE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->rateIndex = drix; + cmd->mgmtRateIndex = mrix; + cmd->ctlRateIndex = crix; + + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BITRATE_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_bitrate_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_BITRATE_CMDID); +} + +/* + * Returns TRUE iff the given rate index is legal in the current PHY mode. + */ +A_BOOL +wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_INT32 rateIndex) +{ + WMI_PHY_MODE phyMode = (WMI_PHY_MODE) wmip->wmi_phyMode; + A_BOOL isValid = TRUE; + switch(phyMode) { + case WMI_11A_MODE: + if ((rateIndex < MODE_A_SUPPORT_RATE_START) || (rateIndex > MODE_A_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + + case WMI_11B_MODE: + if ((rateIndex < MODE_B_SUPPORT_RATE_START) || (rateIndex > MODE_B_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + + case WMI_11GONLY_MODE: + if ((rateIndex < MODE_GONLY_SUPPORT_RATE_START) || (rateIndex > MODE_GONLY_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + + case WMI_11G_MODE: + case WMI_11AG_MODE: + if ((rateIndex < MODE_G_SUPPORT_RATE_START) || (rateIndex > MODE_G_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + + default: + A_ASSERT(FALSE); + break; + } + + return isValid; +} + +A_INT8 +wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate) +{ + A_INT8 i; + if (rate != -1) + { + for (i=0;;i++) + { + if (wmi_rateTable[(A_UINT32) i] == 0) { + return A_EINVAL; + } + if (wmi_rateTable[(A_UINT32) i] == rate) { + break; + } + } + } + else{ + i = -1; + } + + if(wmi_is_bitrate_index_valid(wmip, (A_INT32) i) != TRUE) { + return A_EINVAL; + } + + return i; +} + +A_STATUS +wmi_set_fixrates_cmd(struct wmi_t *wmip, A_INT16 fixRatesMask) +{ + void *osbuf; + WMI_FIX_RATES_CMD *cmd; + A_INT32 rateIndex; + + /* Make sure all rates in the mask are valid in the current PHY mode */ + for(rateIndex = 0; rateIndex < MAX_NUMBER_OF_SUPPORT_RATES; rateIndex++) { + if((1 << rateIndex) & (A_UINT32)fixRatesMask) { + if(wmi_is_bitrate_index_valid(wmip, rateIndex) != TRUE) { + A_DPRINTF(DBG_WMI, (DBGFMT "Set Fix Rates command failed: Given rate is illegal in current PHY mode\n", DBGARG)); + return A_EINVAL; + } + } + } + + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_FIX_RATES_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->fixRateMask = fixRatesMask; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_FIXRATES_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_ratemask_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_FIXRATES_CMDID); +} + +A_STATUS +wmi_get_channelList_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_CHANNEL_LIST_CMDID); +} + +/* + * used to generate a wmi sey channel Parameters cmd. + * mode should always be specified and corresponds to the phy mode of the + * wlan. + * numChan should alway sbe specified. If zero indicates that all available + * channels should be used. + * channelList is an array of channel frequencies (in Mhz) which the radio + * should limit its operation to. It should be NULL if numChan == 0. Size of + * array should correspond to numChan entries. + */ +A_STATUS +wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam, + WMI_PHY_MODE mode, A_INT8 numChan, + A_UINT16 *channelList) +{ + void *osbuf; + WMI_CHANNEL_PARAMS_CMD *cmd; + A_INT8 size; + + size = sizeof (*cmd); + + if (numChan) { + if (numChan > WMI_MAX_CHANNELS) { + return A_EINVAL; + } + size += sizeof(A_UINT16) * (numChan - 1); + } + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_CHANNEL_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + wmip->wmi_phyMode = mode; + cmd->scanParam = scanParam; + cmd->phyMode = mode; + cmd->numChannels = numChan; + A_MEMCPY(cmd->channelList, channelList, numChan * sizeof(A_UINT16)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_CHANNEL_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +void +wmi_cache_configure_rssithreshold(struct wmi_t *wmip, WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd) +{ + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_RSSI]; + /* + * Parse the command and store the threshold values here. The checks + * for valid values can be put here + */ + sq_thresh->weight = rssiCmd->weight; + sq_thresh->polling_interval = rssiCmd->pollTime; + + sq_thresh->upper_threshold[0] = rssiCmd->thresholdAbove1_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[1] = rssiCmd->thresholdAbove2_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[2] = rssiCmd->thresholdAbove3_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[3] = rssiCmd->thresholdAbove4_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[4] = rssiCmd->thresholdAbove5_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[5] = rssiCmd->thresholdAbove6_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold_valid_count = 6; + + /* List sorted in descending order */ + sq_thresh->lower_threshold[0] = rssiCmd->thresholdBelow6_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[1] = rssiCmd->thresholdBelow5_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[2] = rssiCmd->thresholdBelow4_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[3] = rssiCmd->thresholdBelow3_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[4] = rssiCmd->thresholdBelow2_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[5] = rssiCmd->thresholdBelow1_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold_valid_count = 6; + + if (!rssi_event_value) { + /* + * Configuring the thresholds to their extremes allows the host to get an + * event from the target which is used for the configuring the correct + * thresholds + */ + rssiCmd->thresholdAbove1_Val = sq_thresh->upper_threshold[0]; + rssiCmd->thresholdBelow1_Val = sq_thresh->lower_threshold[0]; + } else { + /* + * In case the user issues multiple times of rssi_threshold_setting, + * we should not use the extreames anymore, the target does not expect that. + */ + rssiCmd->thresholdAbove1_Val = ar6000_get_upper_threshold(rssi_event_value, sq_thresh, + sq_thresh->upper_threshold_valid_count); + rssiCmd->thresholdBelow1_Val = ar6000_get_lower_threshold(rssi_event_value, sq_thresh, + sq_thresh->lower_threshold_valid_count); + } +} + +A_STATUS +wmi_set_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd) +{ + + /* Check these values are in ascending order */ + if( rssiCmd->thresholdAbove6_Val <= rssiCmd->thresholdAbove5_Val || + rssiCmd->thresholdAbove5_Val <= rssiCmd->thresholdAbove4_Val || + rssiCmd->thresholdAbove4_Val <= rssiCmd->thresholdAbove3_Val || + rssiCmd->thresholdAbove3_Val <= rssiCmd->thresholdAbove2_Val || + rssiCmd->thresholdAbove2_Val <= rssiCmd->thresholdAbove1_Val || + rssiCmd->thresholdBelow6_Val <= rssiCmd->thresholdBelow5_Val || + rssiCmd->thresholdBelow5_Val <= rssiCmd->thresholdBelow4_Val || + rssiCmd->thresholdBelow4_Val <= rssiCmd->thresholdBelow3_Val || + rssiCmd->thresholdBelow3_Val <= rssiCmd->thresholdBelow2_Val || + rssiCmd->thresholdBelow2_Val <= rssiCmd->thresholdBelow1_Val) + { + return A_EINVAL; + } + + wmi_cache_configure_rssithreshold(wmip, rssiCmd); + + return (wmi_send_rssi_threshold_params(wmip, rssiCmd)); +} + +A_STATUS +wmi_set_ip_cmd(struct wmi_t *wmip, WMI_SET_IP_CMD *ipCmd) +{ + void *osbuf; + WMI_SET_IP_CMD *cmd; + + /* Multicast address are not valid */ + if((*((A_UINT8*)&ipCmd->ips[0]) >= 0xE0) || + (*((A_UINT8*)&ipCmd->ips[1]) >= 0xE0)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_SET_IP_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_SET_IP_CMD)); + cmd = (WMI_SET_IP_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMCPY(cmd, ipCmd, sizeof(WMI_SET_IP_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_IP_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip, + WMI_SET_HOST_SLEEP_MODE_CMD *hostModeCmd) +{ + void *osbuf; + A_INT8 size; + WMI_SET_HOST_SLEEP_MODE_CMD *cmd; + A_UINT16 activeTsids=0; + A_UINT8 streamExists=0; + A_UINT8 i; + + if( hostModeCmd->awake == hostModeCmd->asleep) { + return A_EINVAL; + } + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_SET_HOST_SLEEP_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, hostModeCmd, sizeof(WMI_SET_HOST_SLEEP_MODE_CMD)); + + if(hostModeCmd->asleep) { + /* + * Relinquish credits from all implicitly created pstreams since when we + * go to sleep. If user created explicit thinstreams exists with in a + * fatpipe leave them intact for the user to delete + */ + LOCK_WMI(wmip); + streamExists = wmip->wmi_fatPipeExists; + UNLOCK_WMI(wmip); + + for(i=0;i< WMM_NUM_AC;i++) { + if (streamExists & (1<wmi_streamExistsForAC[i]; + UNLOCK_WMI(wmip); + /* If there are no user created thin streams delete the fatpipe */ + if(!activeTsids) { + streamExists &= ~(1<wmi_devt,i); + } + } + } + + /* Update the fatpipes that exists*/ + LOCK_WMI(wmip); + wmip->wmi_fatPipeExists = streamExists; + UNLOCK_WMI(wmip); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_HOST_SLEEP_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_wow_mode_cmd(struct wmi_t *wmip, + WMI_SET_WOW_MODE_CMD *wowModeCmd) +{ + void *osbuf; + A_INT8 size; + WMI_SET_WOW_MODE_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_SET_WOW_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, wowModeCmd, sizeof(WMI_SET_WOW_MODE_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WOW_MODE_CMDID, + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_get_wow_list_cmd(struct wmi_t *wmip, + WMI_GET_WOW_LIST_CMD *wowListCmd) +{ + void *osbuf; + A_INT8 size; + WMI_GET_WOW_LIST_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_GET_WOW_LIST_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, wowListCmd, sizeof(WMI_GET_WOW_LIST_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_GET_WOW_LIST_CMDID, + NO_SYNC_WMIFLAG)); + +} + +static A_STATUS +wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_GET_WOW_LIST_REPLY *reply; + + if (len < sizeof(WMI_GET_WOW_LIST_REPLY)) { + return A_EINVAL; + } + reply = (WMI_GET_WOW_LIST_REPLY *)datap; + + A_WMI_WOW_LIST_EVENT(wmip->wmi_devt, reply->num_filters, + reply); + + return A_OK; +} + +A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip, + WMI_ADD_WOW_PATTERN_CMD *addWowCmd, + A_UINT8* pattern, A_UINT8* mask, + A_UINT8 pattern_size) +{ + void *osbuf; + A_INT8 size; + WMI_ADD_WOW_PATTERN_CMD *cmd; + A_UINT8 *filter_mask = NULL; + + size = sizeof (*cmd); + + size += ((2 * addWowCmd->filter_size)* sizeof(A_UINT8)); + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_ADD_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->filter_list_id = addWowCmd->filter_list_id; + cmd->filter_offset = addWowCmd->filter_offset; + cmd->filter_size = addWowCmd->filter_size; + + A_MEMCPY(cmd->filter, pattern, addWowCmd->filter_size); + + filter_mask = (A_UINT8*)(cmd->filter + cmd->filter_size); + A_MEMCPY(filter_mask, mask, addWowCmd->filter_size); + + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_WOW_PATTERN_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_del_wow_pattern_cmd(struct wmi_t *wmip, + WMI_DEL_WOW_PATTERN_CMD *delWowCmd) +{ + void *osbuf; + A_INT8 size; + WMI_DEL_WOW_PATTERN_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_DEL_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, delWowCmd, sizeof(WMI_DEL_WOW_PATTERN_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_DEL_WOW_PATTERN_CMDID, + NO_SYNC_WMIFLAG)); + +} + +void +wmi_cache_configure_snrthreshold(struct wmi_t *wmip, WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd) +{ + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_SNR]; + /* + * Parse the command and store the threshold values here. The checks + * for valid values can be put here + */ + sq_thresh->weight = snrCmd->weight; + sq_thresh->polling_interval = snrCmd->pollTime; + + sq_thresh->upper_threshold[0] = snrCmd->thresholdAbove1_Val; + sq_thresh->upper_threshold[1] = snrCmd->thresholdAbove2_Val; + sq_thresh->upper_threshold[2] = snrCmd->thresholdAbove3_Val; + sq_thresh->upper_threshold[3] = snrCmd->thresholdAbove4_Val; + sq_thresh->upper_threshold_valid_count = 4; + + /* List sorted in descending order */ + sq_thresh->lower_threshold[0] = snrCmd->thresholdBelow4_Val; + sq_thresh->lower_threshold[1] = snrCmd->thresholdBelow3_Val; + sq_thresh->lower_threshold[2] = snrCmd->thresholdBelow2_Val; + sq_thresh->lower_threshold[3] = snrCmd->thresholdBelow1_Val; + sq_thresh->lower_threshold_valid_count = 4; + + if (!snr_event_value) { + /* + * Configuring the thresholds to their extremes allows the host to get an + * event from the target which is used for the configuring the correct + * thresholds + */ + snrCmd->thresholdAbove1_Val = (A_UINT8)sq_thresh->upper_threshold[0]; + snrCmd->thresholdBelow1_Val = (A_UINT8)sq_thresh->lower_threshold[0]; + } else { + /* + * In case the user issues multiple times of snr_threshold_setting, + * we should not use the extreames anymore, the target does not expect that. + */ + snrCmd->thresholdAbove1_Val = ar6000_get_upper_threshold(snr_event_value, sq_thresh, + sq_thresh->upper_threshold_valid_count); + snrCmd->thresholdBelow1_Val = ar6000_get_lower_threshold(snr_event_value, sq_thresh, + sq_thresh->lower_threshold_valid_count); + } + +} +A_STATUS +wmi_set_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd) +{ + if( snrCmd->thresholdAbove4_Val <= snrCmd->thresholdAbove3_Val || + snrCmd->thresholdAbove3_Val <= snrCmd->thresholdAbove2_Val || + snrCmd->thresholdAbove2_Val <= snrCmd->thresholdAbove1_Val || + snrCmd->thresholdBelow4_Val <= snrCmd->thresholdBelow3_Val || + snrCmd->thresholdBelow3_Val <= snrCmd->thresholdBelow2_Val || + snrCmd->thresholdBelow2_Val <= snrCmd->thresholdBelow1_Val) + { + return A_EINVAL; + } + wmi_cache_configure_snrthreshold(wmip, snrCmd); + return (wmi_send_snr_threshold_params(wmip, snrCmd)); +} + +A_STATUS +wmi_clr_rssi_snr(struct wmi_t *wmip) +{ + void *osbuf; + + osbuf = A_NETBUF_ALLOC(sizeof(int)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + return (wmi_cmd_send(wmip, osbuf, WMI_CLR_RSSI_SNR_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_lq_threshold_params(struct wmi_t *wmip, + WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd) +{ + void *osbuf; + A_INT8 size; + WMI_LQ_THRESHOLD_PARAMS_CMD *cmd; + /* These values are in ascending order */ + if( lqCmd->thresholdAbove4_Val <= lqCmd->thresholdAbove3_Val || + lqCmd->thresholdAbove3_Val <= lqCmd->thresholdAbove2_Val || + lqCmd->thresholdAbove2_Val <= lqCmd->thresholdAbove1_Val || + lqCmd->thresholdBelow4_Val <= lqCmd->thresholdBelow3_Val || + lqCmd->thresholdBelow3_Val <= lqCmd->thresholdBelow2_Val || + lqCmd->thresholdBelow2_Val <= lqCmd->thresholdBelow1_Val ) { + + return A_EINVAL; + } + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_LQ_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, lqCmd, sizeof(WMI_LQ_THRESHOLD_PARAMS_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_LQ_THRESHOLD_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 mask) +{ + void *osbuf; + A_INT8 size; + WMI_TARGET_ERROR_REPORT_BITMASK *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_TARGET_ERROR_REPORT_BITMASK *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + cmd->bitmask = mask; + + return (wmi_cmd_send(wmip, osbuf, WMI_TARGET_ERROR_REPORT_BITMASK_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie, A_UINT32 source) +{ + void *osbuf; + WMIX_HB_CHALLENGE_RESP_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_HB_CHALLENGE_RESP_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->cookie = cookie; + cmd->source = source; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_HB_CHALLENGE_RESP_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask, + A_UINT16 tsr, A_BOOL rep, A_UINT16 size, + A_UINT32 valid) +{ + void *osbuf; + WMIX_DBGLOG_CFG_MODULE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_DBGLOG_CFG_MODULE_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->config.cfgmmask = mmask; + cmd->config.cfgtsr = tsr; + cmd->config.cfgrep = rep; + cmd->config.cfgsize = size; + cmd->config.cfgvalid = valid; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DBGLOG_CFG_MODULE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_stats_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_STATISTICS_CMDID); +} + +A_STATUS +wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid) +{ + void *osbuf; + WMI_ADD_BAD_AP_CMD *cmd; + + if ((bssid == NULL) || (apIndex > WMI_MAX_BAD_AP_INDEX)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_ADD_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->badApIndex = apIndex; + A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid)); + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_BAD_AP_CMDID, SYNC_BEFORE_WMIFLAG)); +} + +A_STATUS +wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex) +{ + void *osbuf; + WMI_DELETE_BAD_AP_CMD *cmd; + + if (apIndex > WMI_MAX_BAD_AP_INDEX) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DELETE_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->badApIndex = apIndex; + + return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_BAD_AP_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_abort_scan_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_ABORT_SCAN_CMDID); +} + +A_STATUS +wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM) +{ + void *osbuf; + WMI_SET_TX_PWR_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_TX_PWR_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->dbM = dbM; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_TX_PWR_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_txPwr_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_TX_PWR_CMDID); +} + +A_UINT16 +wmi_get_mapped_qos_queue(struct wmi_t *wmip, A_UINT8 trafficClass) +{ + A_UINT16 activeTsids=0; + + LOCK_WMI(wmip); + activeTsids = wmip->wmi_streamExistsForAC[trafficClass]; + UNLOCK_WMI(wmip); + + return activeTsids; +} + +A_STATUS +wmi_get_roam_tbl_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_ROAM_TBL_CMDID); +} + +A_STATUS +wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType) +{ + void *osbuf; + A_UINT32 size = sizeof(A_UINT8); + WMI_TARGET_ROAM_DATA *cmd; + + osbuf = A_NETBUF_ALLOC(size); /* no payload */ + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_TARGET_ROAM_DATA *)(A_NETBUF_DATA(osbuf)); + cmd->roamDataType = roamDataType; + + return (wmi_cmd_send(wmip, osbuf, WMI_GET_ROAM_DATA_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p, + A_UINT8 size) +{ + void *osbuf; + WMI_SET_ROAM_CTRL_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_SET_ROAM_CTRL_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + A_MEMCPY(cmd, p, size); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_ROAM_CTRL_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_powersave_timers_cmd(struct wmi_t *wmip, + WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd, + A_UINT8 size) +{ + void *osbuf; + WMI_POWERSAVE_TIMERS_POLICY_CMD *cmd; + + /* These timers can't be zero */ + if(!pCmd->psPollTimeout || !pCmd->triggerTimeout || + !(pCmd->apsdTimPolicy == IGNORE_TIM_ALL_QUEUES_APSD || + pCmd->apsdTimPolicy == PROCESS_TIM_ALL_QUEUES_APSD) || + !(pCmd->simulatedAPSDTimPolicy == IGNORE_TIM_SIMULATED_APSD || + pCmd->simulatedAPSDTimPolicy == PROCESS_TIM_SIMULATED_APSD)) + return A_EINVAL; + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_POWERSAVE_TIMERS_POLICY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + A_MEMCPY(cmd, pCmd, size); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID, + NO_SYNC_WMIFLAG)); +} + +#ifdef CONFIG_HOST_GPIO_SUPPORT +/* Send a command to Target to change GPIO output pins. */ +A_STATUS +wmi_gpio_output_set(struct wmi_t *wmip, + A_UINT32 set_mask, + A_UINT32 clear_mask, + A_UINT32 enable_mask, + A_UINT32 disable_mask) +{ + void *osbuf; + WMIX_GPIO_OUTPUT_SET_CMD *output_set; + int size; + + size = sizeof(*output_set); + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - set=0x%x clear=0x%x enb=0x%x dis=0x%x\n", DBGARG, + set_mask, clear_mask, enable_mask, disable_mask)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + output_set = (WMIX_GPIO_OUTPUT_SET_CMD *)(A_NETBUF_DATA(osbuf)); + + output_set->set_mask = set_mask; + output_set->clear_mask = clear_mask; + output_set->enable_mask = enable_mask; + output_set->disable_mask = disable_mask; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_OUTPUT_SET_CMDID, + NO_SYNC_WMIFLAG)); +} + +/* Send a command to the Target requesting state of the GPIO input pins */ +A_STATUS +wmi_gpio_input_get(struct wmi_t *wmip) +{ + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + return wmi_simple_cmd_xtnd(wmip, WMIX_GPIO_INPUT_GET_CMDID); +} + +/* Send a command to the Target that changes the value of a GPIO register. */ +A_STATUS +wmi_gpio_register_set(struct wmi_t *wmip, + A_UINT32 gpioreg_id, + A_UINT32 value) +{ + void *osbuf; + WMIX_GPIO_REGISTER_SET_CMD *register_set; + int size; + + size = sizeof(*register_set); + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG, gpioreg_id, value)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + register_set = (WMIX_GPIO_REGISTER_SET_CMD *)(A_NETBUF_DATA(osbuf)); + + register_set->gpioreg_id = gpioreg_id; + register_set->value = value; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_SET_CMDID, + NO_SYNC_WMIFLAG)); +} + +/* Send a command to the Target to fetch the value of a GPIO register. */ +A_STATUS +wmi_gpio_register_get(struct wmi_t *wmip, + A_UINT32 gpioreg_id) +{ + void *osbuf; + WMIX_GPIO_REGISTER_GET_CMD *register_get; + int size; + + size = sizeof(*register_get); + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter - reg=%d\n", DBGARG, gpioreg_id)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + register_get = (WMIX_GPIO_REGISTER_GET_CMD *)(A_NETBUF_DATA(osbuf)); + + register_get->gpioreg_id = gpioreg_id; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_GET_CMDID, + NO_SYNC_WMIFLAG)); +} + +/* Send a command to the Target acknowledging some GPIO interrupts. */ +A_STATUS +wmi_gpio_intr_ack(struct wmi_t *wmip, + A_UINT32 ack_mask) +{ + void *osbuf; + WMIX_GPIO_INTR_ACK_CMD *intr_ack; + int size; + + size = sizeof(*intr_ack); + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter ack_mask=0x%x\n", DBGARG, ack_mask)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + intr_ack = (WMIX_GPIO_INTR_ACK_CMD *)(A_NETBUF_DATA(osbuf)); + + intr_ack->ack_mask = ack_mask; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_INTR_ACK_CMDID, + NO_SYNC_WMIFLAG)); +} +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +A_STATUS +wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT16 txop, A_UINT8 eCWmin, + A_UINT8 eCWmax, A_UINT8 aifsn) +{ + void *osbuf; + WMI_SET_ACCESS_PARAMS_CMD *cmd; + + if ((eCWmin > WMI_MAX_CW_ACPARAM) || (eCWmax > WMI_MAX_CW_ACPARAM) || + (aifsn > WMI_MAX_AIFSN_ACPARAM)) + { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_ACCESS_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->txop = txop; + cmd->eCWmin = eCWmin; + cmd->eCWmax = eCWmax; + cmd->aifsn = aifsn; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_ACCESS_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType, + A_UINT8 trafficClass, A_UINT8 maxRetries, + A_UINT8 enableNotify) +{ + void *osbuf; + WMI_SET_RETRY_LIMITS_CMD *cmd; + + if ((frameType != MGMT_FRAMETYPE) && (frameType != CONTROL_FRAMETYPE) && + (frameType != DATA_FRAMETYPE)) + { + return A_EINVAL; + } + + if (maxRetries > WMI_MAX_RETRIES) { + return A_EINVAL; + } + + if (frameType != DATA_FRAMETYPE) { + trafficClass = 0; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_RETRY_LIMITS_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->frameType = frameType; + cmd->trafficClass = trafficClass; + cmd->maxRetries = maxRetries; + cmd->enableNotify = enableNotify; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_RETRY_LIMITS_CMDID, + NO_SYNC_WMIFLAG)); +} + +void +wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid) +{ + if (bssid != NULL) { + A_MEMCPY(bssid, wmip->wmi_bssid, ATH_MAC_LEN); + } +} + +A_STATUS +wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode) +{ + void *osbuf; + WMI_SET_OPT_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_OPT_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->optMode = optMode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_OPT_MODE_CMDID, + SYNC_BOTH_WMIFLAG)); +} + +A_STATUS +wmi_opt_tx_frame_cmd(struct wmi_t *wmip, + A_UINT8 frmType, + A_UINT8 *dstMacAddr, + A_UINT8 *bssid, + A_UINT16 optIEDataLen, + A_UINT8 *optIEData) +{ + void *osbuf; + WMI_OPT_TX_FRAME_CMD *cmd; + osbuf = A_NETBUF_ALLOC(optIEDataLen + sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, (optIEDataLen + sizeof(*cmd))); + + cmd = (WMI_OPT_TX_FRAME_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, (optIEDataLen + sizeof(*cmd)-1)); + + cmd->frmType = frmType; + cmd->optIEDataLen = optIEDataLen; + //cmd->optIEData = (A_UINT8 *)((int)cmd + sizeof(*cmd)); + A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid)); + A_MEMCPY(cmd->dstAddr, dstMacAddr, sizeof(cmd->dstAddr)); + A_MEMCPY(&cmd->optIEData[0], optIEData, optIEDataLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_OPT_TX_FRAME_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl) +{ + void *osbuf; + WMI_BEACON_INT_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_BEACON_INT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->beaconInterval = intvl; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BEACON_INT_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize) +{ + void *osbuf; + WMI_SET_VOICE_PKT_SIZE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_VOICE_PKT_SIZE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->voicePktSize = voicePktSize; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_VOICE_PKT_SIZE_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSPLen) +{ + void *osbuf; + WMI_SET_MAX_SP_LEN_CMD *cmd; + + /* maxSPLen is a two-bit value. If user trys to set anything + * other than this, then its invalid + */ + if(maxSPLen & ~0x03) + return A_EINVAL; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_MAX_SP_LEN_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->maxSPLen = maxSPLen; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_MAX_SP_LEN_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_UINT8 +wmi_determine_userPriority( + A_UINT8 *pkt, + A_UINT32 layer2Pri) +{ + A_UINT8 ipPri; + iphdr *ipHdr = (iphdr *)pkt; + + /* Determine IPTOS priority */ + /* + * IP Tos format : + * (Refer Pg 57 WMM-test-plan-v1.2) + * IP-TOS - 8bits + * : DSCP(6-bits) ECN(2-bits) + * : DSCP - P2 P1 P0 X X X + * where (P2 P1 P0) form 802.1D + */ + ipPri = ipHdr->ip_tos >> 5; + ipPri &= 0x7; + + if ((layer2Pri & 0x7) > ipPri) + return ((A_UINT8)layer2Pri & 0x7); + else + return ipPri; +} + +A_UINT8 +convert_userPriority_to_trafficClass(A_UINT8 userPriority) +{ + return (up_to_ac[userPriority & 0x7]); +} + +A_UINT8 +wmi_get_power_mode_cmd(struct wmi_t *wmip) +{ + return wmip->wmi_powerMode; +} + +A_STATUS +wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance) +{ + A_STATUS ret = A_OK; + +#define TSPEC_SUSPENSION_INTERVAL_ATHEROS_DEF (~0) +#define TSPEC_SERVICE_START_TIME_ATHEROS_DEF 0 +#define TSPEC_MAX_BURST_SIZE_ATHEROS_DEF 0 +#define TSPEC_DELAY_BOUND_ATHEROS_DEF 0 +#define TSPEC_MEDIUM_TIME_ATHEROS_DEF 0 +#define TSPEC_SBA_ATHEROS_DEF 0x2000 /* factor is 1 */ + + /* Verify TSPEC params for ATHEROS compliance */ + if(tspecCompliance == ATHEROS_COMPLIANCE) { + if ((pCmd->suspensionInt != TSPEC_SUSPENSION_INTERVAL_ATHEROS_DEF) || + (pCmd->serviceStartTime != TSPEC_SERVICE_START_TIME_ATHEROS_DEF) || + (pCmd->minDataRate != pCmd->meanDataRate) || + (pCmd->minDataRate != pCmd->peakDataRate) || + (pCmd->maxBurstSize != TSPEC_MAX_BURST_SIZE_ATHEROS_DEF) || + (pCmd->delayBound != TSPEC_DELAY_BOUND_ATHEROS_DEF) || + (pCmd->sba != TSPEC_SBA_ATHEROS_DEF) || + (pCmd->mediumTime != TSPEC_MEDIUM_TIME_ATHEROS_DEF)) { + + A_DPRINTF(DBG_WMI, (DBGFMT "Invalid TSPEC params\n", DBGARG)); + //A_PRINTF("%s: Invalid TSPEC params\n", __func__); + ret = A_EINVAL; + } + } + + return ret; +} + +#ifdef CONFIG_HOST_TCMD_SUPPORT +static A_STATUS +wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TCMD_RX_REPORT_EVENT(wmip->wmi_devt, datap, len); + + return A_OK; +} + +#endif /* CONFIG_HOST_TCMD_SUPPORT*/ + +A_STATUS +wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode) +{ + void *osbuf; + WMI_SET_AUTH_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_AUTH_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->mode = mode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_AUTH_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode) +{ + void *osbuf; + WMI_SET_REASSOC_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_REASSOC_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->mode = mode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_REASSOC_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status) +{ + void *osbuf; + WMI_SET_LPREAMBLE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_LPREAMBLE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->status = status; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_LPREAMBLE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold) +{ + void *osbuf; + WMI_SET_RTS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_RTS_CMD*)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->threshold = threshold; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_RTS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status) +{ + void *osbuf; + WMI_SET_WMM_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_WMM_CMD*)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->status = status; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_CMDID, + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG cfg) +{ + void *osbuf; + WMI_SET_WMM_TXOP_CMD *cmd; + + if( !((cfg == WMI_TXOP_DISABLED) || (cfg == WMI_TXOP_ENABLED)) ) + return A_EINVAL; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_WMM_TXOP_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->txopEnable = cfg; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_TXOP_CMDID, + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_set_country(struct wmi_t *wmip, A_UCHAR *countryCode) +{ + void *osbuf; + WMI_AP_SET_COUNTRY_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_AP_SET_COUNTRY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + A_MEMCPY(cmd->countryCode,countryCode,3); + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_COUNTRY_CMDID, + NO_SYNC_WMIFLAG)); +} + +#ifdef CONFIG_HOST_TCMD_SUPPORT +/* WMI layer doesn't need to know the data type of the test cmd. + This would be beneficial for customers like Qualcomm, who might + have different test command requirements from differnt manufacturers + */ +A_STATUS +wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32 len) +{ + void *osbuf; + char *data; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + osbuf= A_NETBUF_ALLOC(len); + if(osbuf == NULL) + { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, len); + data = A_NETBUF_DATA(osbuf); + A_MEMCPY(data, buf, len); + + return(wmi_cmd_send(wmip, osbuf, WMI_TEST_CMDID, + NO_SYNC_WMIFLAG)); +} + +#endif + +A_STATUS +wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status) +{ + void *osbuf; + WMI_SET_BT_STATUS_CMD *cmd; + +#ifdef ANDROID_DEBUG + printk("Enter - streamType=%d, status=%d\n", streamType, status); +#endif + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_BT_STATUS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->streamType = streamType; + cmd->status = status; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_STATUS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd) +{ + void *osbuf; + WMI_SET_BT_PARAMS_CMD* alloc_cmd; + +#ifdef ANDROID_DEBUG + printk("cmd params is %d\n", cmd->paramType); + + if (cmd->paramType == BT_PARAM_SCO) { + printk("sco params %d %d %d %d %d %d %d %d %d %d %d %d\n", cmd->info.scoParams.numScoCyclesForceTrigger, + cmd->info.scoParams.dataResponseTimeout, + cmd->info.scoParams.stompScoRules, + cmd->info.scoParams.scoOptFlags, + cmd->info.scoParams.stompDutyCyleVal, + cmd->info.scoParams.stompDutyCyleMaxVal, + cmd->info.scoParams.psPollLatencyFraction, + cmd->info.scoParams.noSCOSlots, + cmd->info.scoParams.noIdleSlots, + cmd->info.scoParams.scoOptOffRssi, + cmd->info.scoParams.scoOptOnRssi, + cmd->info.scoParams.scoOptRtsCount); + } + else if (cmd->paramType == BT_PARAM_A2DP) { + printk("A2DP params %d %d %d %d %d %d %d %d\n", cmd->info.a2dpParams.a2dpWlanUsageLimit, + cmd->info.a2dpParams.a2dpBurstCntMin, + cmd->info.a2dpParams.a2dpDataRespTimeout, + cmd->info.a2dpParams.a2dpOptFlags, + cmd->info.a2dpParams.isCoLocatedBtRoleMaster, + cmd->info.a2dpParams.a2dpOptOffRssi, + cmd->info.a2dpParams.a2dpOptOnRssi, + cmd->info.a2dpParams.a2dpOptRtsCount); + } + else if (cmd->paramType == BT_PARAM_ANTENNA_CONFIG) { + printk("Ant config %d\n", cmd->info.antType); + } + else if (cmd->paramType == BT_PARAM_COLOCATED_BT_DEVICE) { + printk("co-located BT %d\n", cmd->info.coLocatedBtDev); + } + else if (cmd->paramType == BT_PARAM_ACLCOEX) { + printk("ACL params %d %d %d\n", cmd->info.aclCoexParams.aclWlanMediumUsageTime, + cmd->info.aclCoexParams.aclBtMediumUsageTime, + cmd->info.aclCoexParams.aclDataRespTimeout); + } + else if (cmd->paramType == BT_PARAM_11A_SEPARATE_ANT) { + A_DPRINTF(DBG_WMI, (DBGFMT "11A ant\n", DBGARG)); + } +#endif + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + alloc_cmd = (WMI_SET_BT_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(alloc_cmd, sizeof(*cmd)); + A_MEMCPY(alloc_cmd, cmd, sizeof(*cmd)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_keepalive_configured(struct wmi_t *wmip) +{ + void *osbuf; + WMI_GET_KEEPALIVE_CMD *cmd; + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + cmd = (WMI_GET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + return (wmi_cmd_send(wmip, osbuf, WMI_GET_KEEPALIVE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_UINT8 +wmi_get_keepalive_cmd(struct wmi_t *wmip) +{ + return wmip->wmi_keepaliveInterval; +} + +A_STATUS +wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval) +{ + void *osbuf; + WMI_SET_KEEPALIVE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->keepaliveInterval = keepaliveInterval; + wmip->wmi_keepaliveInterval = keepaliveInterval; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_KEEPALIVE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_params_cmd(struct wmi_t *wmip, A_UINT32 opcode, A_UINT32 length, A_CHAR* buffer) +{ + void *osbuf; + WMI_SET_PARAMS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd) + length); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd) + length); + + cmd = (WMI_SET_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->opcode = opcode; + cmd->length = length; + A_MEMCPY(cmd->buffer, buffer, length); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4) +{ + void *osbuf; + WMI_SET_MCAST_FILTER_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->multicast_mac[0] = 0x01; + cmd->multicast_mac[1] = 0x00; + cmd->multicast_mac[2] = 0x5e; + cmd->multicast_mac[3] = dot2&0x7F; + cmd->multicast_mac[4] = dot3; + cmd->multicast_mac[5] = dot4; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_MCAST_FILTER_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_del_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4) +{ + void *osbuf; + WMI_SET_MCAST_FILTER_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->multicast_mac[0] = 0x01; + cmd->multicast_mac[1] = 0x00; + cmd->multicast_mac[2] = 0x5e; + cmd->multicast_mac[3] = dot2&0x7F; + cmd->multicast_mac[4] = dot3; + cmd->multicast_mac[5] = dot4; + + return (wmi_cmd_send(wmip, osbuf, WMI_DEL_MCAST_FILTER_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType, A_UINT8 ieLen, + A_UINT8 *ieInfo) +{ + void *osbuf; + WMI_SET_APPIE_CMD *cmd; + A_UINT16 cmdLen; + + cmdLen = sizeof(*cmd) + ieLen - 1; + osbuf = A_NETBUF_ALLOC(cmdLen); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, cmdLen); + + cmd = (WMI_SET_APPIE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + + cmd->mgmtFrmType = mgmtFrmType; + cmd->ieLen = ieLen; + A_MEMCPY(cmd->ieInfo, ieInfo, ieLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_APPIE_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen) +{ + void *osbuf; + A_UINT8 *data; + + osbuf = A_NETBUF_ALLOC(dataLen); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, dataLen); + + data = A_NETBUF_DATA(osbuf); + + A_MEMCPY(data, cmd, dataLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WHALPARAM_CMDID, NO_SYNC_WMIFLAG)); +} + +A_INT32 +wmi_get_rate(A_INT8 rateindex) +{ + if (rateindex == RATE_AUTO) { + return 0; + } else { + return(wmi_rateTable[(A_UINT32) rateindex]); + } +} + +void +wmi_node_return (struct wmi_t *wmip, bss_t *bss) +{ + if (NULL != bss) + { + wlan_node_return (&wmip->wmi_scan_table, bss); + } +} + +void +wmi_set_nodeage(struct wmi_t *wmip, A_UINT32 nodeAge) +{ + wlan_set_nodeage(&wmip->wmi_scan_table,nodeAge); +} + +bss_t * +wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID) +{ + bss_t *node = NULL; + node = wlan_find_Ssidnode (&wmip->wmi_scan_table, pSsid, + ssidLength, bIsWPA2, bMatchSSID); + return node; +} + + +void +wmi_free_allnodes(struct wmi_t *wmip) +{ + wlan_free_allnodes(&wmip->wmi_scan_table); +} + +bss_t * +wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr) +{ + bss_t *ni=NULL; + ni=wlan_find_node(&wmip->wmi_scan_table,macaddr); + return ni; +} + +void +wmi_free_node(struct wmi_t *wmip, const A_UINT8 *macaddr) +{ + bss_t *ni=NULL; + + ni=wlan_find_node(&wmip->wmi_scan_table,macaddr); + if (ni != NULL) { + wlan_node_reclaim(&wmip->wmi_scan_table, ni); + } + + return; +} + +A_STATUS +wmi_dset_open_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT32 access_cookie, + A_UINT32 dset_size, + A_UINT32 dset_version, + A_UINT32 targ_handle, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg) +{ + void *osbuf; + WMIX_DSETOPEN_REPLY_CMD *open_reply; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter - wmip=0x%x\n", DBGARG, (int)wmip)); + + osbuf = A_NETBUF_ALLOC(sizeof(*open_reply)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*open_reply)); + open_reply = (WMIX_DSETOPEN_REPLY_CMD *)(A_NETBUF_DATA(osbuf)); + + open_reply->status = status; + open_reply->targ_dset_handle = targ_handle; + open_reply->targ_reply_fn = targ_reply_fn; + open_reply->targ_reply_arg = targ_reply_arg; + open_reply->access_cookie = access_cookie; + open_reply->size = dset_size; + open_reply->version = dset_version; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETOPEN_REPLY_CMDID, + NO_SYNC_WMIFLAG)); +} + +static A_STATUS +wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len) +{ + WMI_PMKID_LIST_REPLY *reply; + A_UINT32 expected_len; + + if (len < sizeof(WMI_PMKID_LIST_REPLY)) { + return A_EINVAL; + } + reply = (WMI_PMKID_LIST_REPLY *)datap; + expected_len = sizeof(reply->numPMKID) + reply->numPMKID * WMI_PMKID_LEN; + + if (len < expected_len) { + return A_EINVAL; + } + + A_WMI_PMKID_LIST_EVENT(wmip->wmi_devt, reply->numPMKID, + reply->pmkidList, reply->bssidList[0]); + + return A_OK; +} + + +static A_STATUS +wmi_set_params_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len) +{ + WMI_SET_PARAMS_REPLY *reply; + + if (len < sizeof(WMI_SET_PARAMS_REPLY)) { + return A_EINVAL; + } + reply = (WMI_SET_PARAMS_REPLY *)datap; + + if (A_OK == reply->status) + { + + } + else + { + + } + + return A_OK; +} + + + +#ifdef CONFIG_HOST_DSET_SUPPORT +A_STATUS +wmi_dset_data_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT8 *user_buf, + A_UINT32 length, + A_UINT32 targ_buf, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg) +{ + void *osbuf; + WMIX_DSETDATA_REPLY_CMD *data_reply; + int size; + + size = sizeof(*data_reply) + length; + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - length=%d status=%d\n", DBGARG, length, status)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + data_reply = (WMIX_DSETDATA_REPLY_CMD *)(A_NETBUF_DATA(osbuf)); + + data_reply->status = status; + data_reply->targ_buf = targ_buf; + data_reply->targ_reply_fn = targ_reply_fn; + data_reply->targ_reply_arg = targ_reply_arg; + data_reply->length = length; + + if (status == A_OK) { + if (a_copy_from_user(data_reply->buf, user_buf, length)) { + return A_ERROR; + } + } + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETDATA_REPLY_CMDID, + NO_SYNC_WMIFLAG)); +} +#endif /* CONFIG_HOST_DSET_SUPPORT */ + +A_STATUS +wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status) +{ + void *osbuf; + char *cmd; + + osbuf = a_netbuf_alloc(sizeof(1)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + a_netbuf_put(osbuf, sizeof(1)); + + cmd = (char *)(a_netbuf_to_data(osbuf)); + + A_MEMZERO(cmd, sizeof(*cmd)); + cmd[0] = (status?1:0); + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WSC_STATUS_CMDID, + NO_SYNC_WMIFLAG)); +} + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +A_STATUS +wmi_prof_cfg_cmd(struct wmi_t *wmip, + A_UINT32 period, + A_UINT32 nbins) +{ + void *osbuf; + WMIX_PROF_CFG_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_PROF_CFG_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->period = period; + cmd->nbins = nbins; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_PROF_CFG_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_prof_addr_set_cmd(struct wmi_t *wmip, A_UINT32 addr) +{ + void *osbuf; + WMIX_PROF_ADDR_SET_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_PROF_ADDR_SET_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->addr = addr; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_PROF_ADDR_SET_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_prof_start_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_START_CMDID); +} + +A_STATUS +wmi_prof_stop_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_STOP_CMDID); +} + +A_STATUS +wmi_prof_count_get_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_COUNT_GET_CMDID); +} + +/* Called to handle WMIX_PROF_CONT_EVENTID */ +static A_STATUS +wmi_prof_count_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_PROF_COUNT_EVENT *prof_data = (WMIX_PROF_COUNT_EVENT *)datap; + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - addr=0x%x count=%d\n", DBGARG, + prof_data->addr, prof_data->count)); + + A_WMI_PROF_COUNT_RX(prof_data->addr, prof_data->count); + + return A_OK; +} +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + +#ifdef OS_ROAM_MANAGEMENT + +#define ETHERNET_MAC_ADDRESS_LENGTH 6 + +void +wmi_scan_indication (struct wmi_t *wmip) +{ + struct ieee80211_node_table *nt; + A_UINT32 gen; + A_UINT32 size; + A_UINT32 bsssize; + bss_t *bss; + A_UINT32 numbss; + PNDIS_802_11_BSSID_SCAN_INFO psi; + PBYTE pie; + NDIS_802_11_FIXED_IEs *pFixed; + NDIS_802_11_VARIABLE_IEs *pVar; + A_UINT32 RateSize; + + struct ar6kScanIndication + { + NDIS_802_11_STATUS_INDICATION ind; + NDIS_802_11_BSSID_SCAN_INFO_LIST slist; + } *pAr6kScanIndEvent; + + nt = &wmip->wmi_scan_table; + + ++nt->nt_si_gen; + + + gen = nt->nt_si_gen; + + size = offsetof(struct ar6kScanIndication, slist) + + offsetof(NDIS_802_11_BSSID_SCAN_INFO_LIST, BssidScanInfo); + + numbss = 0; + + IEEE80211_NODE_LOCK(nt); + + //calc size + for (bss = nt->nt_node_first; bss; bss = bss->ni_list_next) { + if (bss->ni_si_gen != gen) { + bsssize = offsetof(NDIS_802_11_BSSID_SCAN_INFO, Bssid) + offsetof(NDIS_WLAN_BSSID_EX, IEs); + bsssize = bsssize + sizeof(NDIS_802_11_FIXED_IEs); + +#ifdef SUPPORT_WPA2 + if (bss->ni_cie.ie_rsn) { + bsssize = bsssize + bss->ni_cie.ie_rsn[1] + 2; + } +#endif + if (bss->ni_cie.ie_wpa) { + bsssize = bsssize + bss->ni_cie.ie_wpa[1] + 2; + } + + // bsssize must be a multiple of 4 to maintain alignment. + bsssize = (bsssize + 3) & ~3; + + size += bsssize; + + numbss++; + } + } + + if (0 == numbss) + { +// RETAILMSG(1, (L"AR6K: scan indication: 0 bss\n")); + ar6000_scan_indication (wmip->wmi_devt, NULL, 0); + IEEE80211_NODE_UNLOCK (nt); + return; + } + + pAr6kScanIndEvent = A_MALLOC(size); + + if (NULL == pAr6kScanIndEvent) + { + IEEE80211_NODE_UNLOCK(nt); + return; + } + + A_MEMZERO(pAr6kScanIndEvent, size); + + //copy data + pAr6kScanIndEvent->ind.StatusType = Ndis802_11StatusType_BssidScanInfoList; + pAr6kScanIndEvent->slist.Version = 1; + pAr6kScanIndEvent->slist.NumItems = numbss; + + psi = &pAr6kScanIndEvent->slist.BssidScanInfo[0]; + + for (bss = nt->nt_node_first; bss; bss = bss->ni_list_next) { + if (bss->ni_si_gen != gen) { + + bss->ni_si_gen = gen; + + //Set scan time + psi->ScanTime = bss->ni_tstamp - WLAN_NODE_INACT_TIMEOUT_MSEC; + + // Copy data to bssid_ex + bsssize = offsetof(NDIS_WLAN_BSSID_EX, IEs); + bsssize = bsssize + sizeof(NDIS_802_11_FIXED_IEs); + +#ifdef SUPPORT_WPA2 + if (bss->ni_cie.ie_rsn) { + bsssize = bsssize + bss->ni_cie.ie_rsn[1] + 2; + } +#endif + if (bss->ni_cie.ie_wpa) { + bsssize = bsssize + bss->ni_cie.ie_wpa[1] + 2; + } + + // bsssize must be a multiple of 4 to maintain alignment. + bsssize = (bsssize + 3) & ~3; + + psi->Bssid.Length = bsssize; + + memcpy (psi->Bssid.MacAddress, bss->ni_macaddr, ETHERNET_MAC_ADDRESS_LENGTH); + + +//if (((bss->ni_macaddr[3] == 0xCE) && (bss->ni_macaddr[4] == 0xF0) && (bss->ni_macaddr[5] == 0xE7)) || +// ((bss->ni_macaddr[3] == 0x03) && (bss->ni_macaddr[4] == 0xE2) && (bss->ni_macaddr[5] == 0x70))) +// RETAILMSG (1, (L"%x\n",bss->ni_macaddr[5])); + + psi->Bssid.Ssid.SsidLength = 0; + pie = bss->ni_cie.ie_ssid; + + if (pie) { + // Format of SSID IE is: + // Type (1 octet) + // Length (1 octet) + // SSID (Length octets) + // + // Validation of the IE should have occurred within WMI. + // + if (pie[1] <= 32) { + psi->Bssid.Ssid.SsidLength = pie[1]; + memcpy(psi->Bssid.Ssid.Ssid, &pie[2], psi->Bssid.Ssid.SsidLength); + } + } + psi->Bssid.Privacy = (bss->ni_cie.ie_capInfo & 0x10) ? 1 : 0; + + //Post the RSSI value relative to the Standard Noise floor value. + psi->Bssid.Rssi = bss->ni_rssi; + + if (bss->ni_cie.ie_chan >= 2412 && bss->ni_cie.ie_chan <= 2484) { + + if (bss->ni_cie.ie_rates && bss->ni_cie.ie_xrates) { + psi->Bssid.NetworkTypeInUse = Ndis802_11OFDM24; + } + else { + psi->Bssid.NetworkTypeInUse = Ndis802_11DS; + } + } + else { + psi->Bssid.NetworkTypeInUse = Ndis802_11OFDM5; + } + + psi->Bssid.Configuration.Length = sizeof(psi->Bssid.Configuration); + psi->Bssid.Configuration.BeaconPeriod = bss->ni_cie.ie_beaconInt; // Units are Kmicroseconds (1024 us) + psi->Bssid.Configuration.ATIMWindow = 0; + psi->Bssid.Configuration.DSConfig = bss->ni_cie.ie_chan * 1000; + psi->Bssid.InfrastructureMode = ((bss->ni_cie.ie_capInfo & 0x03) == 0x01 ) ? Ndis802_11Infrastructure : Ndis802_11IBSS; + + RateSize = 0; + pie = bss->ni_cie.ie_rates; + if (pie) { + RateSize = (pie[1] < NDIS_802_11_LENGTH_RATES_EX) ? pie[1] : NDIS_802_11_LENGTH_RATES_EX; + memcpy(psi->Bssid.SupportedRates, &pie[2], RateSize); + } + pie = bss->ni_cie.ie_xrates; + if (pie && RateSize < NDIS_802_11_LENGTH_RATES_EX) { + memcpy(psi->Bssid.SupportedRates + RateSize, &pie[2], + (pie[1] < (NDIS_802_11_LENGTH_RATES_EX - RateSize)) ? pie[1] : (NDIS_802_11_LENGTH_RATES_EX - RateSize)); + } + + // Copy the fixed IEs + psi->Bssid.IELength = sizeof(NDIS_802_11_FIXED_IEs); + + pFixed = (NDIS_802_11_FIXED_IEs *)psi->Bssid.IEs; + memcpy(pFixed->Timestamp, bss->ni_cie.ie_tstamp, sizeof(pFixed->Timestamp)); + pFixed->BeaconInterval = bss->ni_cie.ie_beaconInt; + pFixed->Capabilities = bss->ni_cie.ie_capInfo; + + // Copy selected variable IEs + + pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pFixed + sizeof(NDIS_802_11_FIXED_IEs)); + +#ifdef SUPPORT_WPA2 + // Copy the WPAv2 IE + if (bss->ni_cie.ie_rsn) { + pie = bss->ni_cie.ie_rsn; + psi->Bssid.IELength += pie[1] + 2; + memcpy(pVar, pie, pie[1] + 2); + pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pVar + pie[1] + 2); + } +#endif + // Copy the WPAv1 IE + if (bss->ni_cie.ie_wpa) { + pie = bss->ni_cie.ie_wpa; + psi->Bssid.IELength += pie[1] + 2; + memcpy(pVar, pie, pie[1] + 2); + pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pVar + pie[1] + 2); + } + + // Advance buffer pointer + psi = (PNDIS_802_11_BSSID_SCAN_INFO)((BYTE*)psi + bsssize + FIELD_OFFSET(NDIS_802_11_BSSID_SCAN_INFO, Bssid)); + } + } + + IEEE80211_NODE_UNLOCK(nt); + +// wmi_free_allnodes(wmip); + +// RETAILMSG(1, (L"AR6K: scan indication: %u bss\n", numbss)); + + ar6000_scan_indication (wmip->wmi_devt, pAr6kScanIndEvent, size); + + A_FREE(pAr6kScanIndEvent); +} +#endif + +A_UINT8 +ar6000_get_upper_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, + A_UINT32 size) +{ + A_UINT32 index; + A_UINT8 threshold = (A_UINT8)sq_thresh->upper_threshold[size - 1]; + + /* The list is already in sorted order. Get the next lower value */ + for (index = 0; index < size; index ++) { + if (rssi < sq_thresh->upper_threshold[index]) { + threshold = (A_UINT8)sq_thresh->upper_threshold[index]; + break; + } + } + + return threshold; +} + +A_UINT8 +ar6000_get_lower_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, + A_UINT32 size) +{ + A_UINT32 index; + A_UINT8 threshold = (A_UINT8)sq_thresh->lower_threshold[size - 1]; + + /* The list is already in sorted order. Get the next lower value */ + for (index = 0; index < size; index ++) { + if (rssi > sq_thresh->lower_threshold[index]) { + threshold = (A_UINT8)sq_thresh->lower_threshold[index]; + break; + } + } + + return threshold; +} +static A_STATUS +wmi_send_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd) +{ + void *osbuf; + A_INT8 size; + WMI_RSSI_THRESHOLD_PARAMS_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_RSSI_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, rssiCmd, sizeof(WMI_RSSI_THRESHOLD_PARAMS_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_RSSI_THRESHOLD_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} +static A_STATUS +wmi_send_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd) +{ + void *osbuf; + A_INT8 size; + WMI_SNR_THRESHOLD_PARAMS_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + cmd = (WMI_SNR_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, snrCmd, sizeof(WMI_SNR_THRESHOLD_PARAMS_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SNR_THRESHOLD_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_target_event_report_cmd(struct wmi_t *wmip, WMI_SET_TARGET_EVENT_REPORT_CMD* cmd) +{ + void *osbuf; + WMI_SET_TARGET_EVENT_REPORT_CMD* alloc_cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + alloc_cmd = (WMI_SET_TARGET_EVENT_REPORT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(alloc_cmd, sizeof(*cmd)); + A_MEMCPY(alloc_cmd, cmd, sizeof(*cmd)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_TARGET_EVENT_REPORT_CMDID, + NO_SYNC_WMIFLAG)); +} + +#ifdef PYXIS_ADHOC +A_STATUS +wmi_set_pyxis_gen_config (struct wmi_t *wmip, A_UINT32 dataWindowSizeMin, A_UINT32 dataWindowSizeMax, A_UINT8 maxJoiners) +{ + void *osbuf; + WMI_PYXIS_GEN_CONFIG *cmd = NULL; + A_UINT16 cmdLen; + + cmdLen = sizeof (WMI_PYXIS_CONFIG_HDR) + sizeof (dataWindowSizeMin) + sizeof (dataWindowSizeMax) + sizeof (maxJoiners); + + osbuf = A_NETBUF_ALLOC (cmdLen); + + if (osbuf == NULL) + { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, cmdLen); + + cmd = (WMI_PYXIS_GEN_CONFIG *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + + cmd->hdr.pyxisConfigType = WMI_PYXIS_GEN_PARAMS; + cmd->hdr.pyxisConfigLen = sizeof (dataWindowSizeMin) + sizeof (dataWindowSizeMax) + sizeof (maxJoiners); + cmd->dataWindowSizeMin = dataWindowSizeMin; + cmd->dataWindowSizeMax = dataWindowSizeMax; + cmd->maxJoiners = maxJoiners; + + return (wmi_cmd_send (wmip, osbuf, WMI_PYXIS_CONFIG_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_pyxis_dscvr_config (struct wmi_t *wmip, A_UINT32 dscvrWindow, A_UINT32 dscvrInterval, + A_UINT32 probeInterval, A_UINT32 probePeriod, A_UINT16 dscvrChannel) +{ + void *osbuf; + WMI_PYXIS_DSCVR_CONFIG *cmd = NULL; + A_UINT16 cmdLen; + + cmdLen = sizeof (WMI_PYXIS_DSCVR_CONFIG); + + osbuf = A_NETBUF_ALLOC (cmdLen); + + if (osbuf == NULL) + { + return A_NO_MEMORY; + } + + A_NETBUF_PUT (osbuf, cmdLen); + + cmd = (WMI_PYXIS_DSCVR_CONFIG *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + + cmd->hdr.pyxisConfigType = WMI_PYXIS_DSCVR_PARAMS; + cmd->hdr.pyxisConfigLen = sizeof (WMI_PYXIS_DSCVR_CONFIG) - sizeof (WMI_PYXIS_CONFIG_HDR); + cmd->dscvrWindow = dscvrWindow; + cmd->dscvrInterval = dscvrInterval; + cmd->dscvrLife = 0; // to be defined + cmd->probeInterval = probeInterval; + cmd->probePeriod = probePeriod; + cmd->dscvrChannel = dscvrChannel; + + return (wmi_cmd_send(wmip, osbuf, WMI_PYXIS_CONFIG_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_pyxis_join_cmd (struct wmi_t *wmip, NETWORK_TYPE wmiNetworkType, + DOT11_AUTH_MODE dot11AuthMode, AUTH_MODE authMode, + CRYPTO_TYPE pairwiseCrypto, A_UINT8 pairwiseCryptoLen, + CRYPTO_TYPE groupCrypto, A_UINT8 groupCryptoLen, + A_UINT8 *bssid, A_UINT8 *nwBSSID, A_UINT16 channel, A_UINT32 ctrl_flags + ) +{ + void *osbuf; + WMI_PYXIS_JOIN_CMD *cmd = NULL; + A_UINT16 cmdLen; + + if ((pairwiseCrypto == NONE_CRYPT) && (groupCrypto != NONE_CRYPT)) { + return A_EINVAL; + } + + if ((pairwiseCrypto != NONE_CRYPT) && (groupCrypto == NONE_CRYPT)) { + return A_EINVAL; + } + + cmdLen = sizeof (WMI_PYXIS_JOIN_CMD); + + osbuf = A_NETBUF_ALLOC (cmdLen); + + if (osbuf == NULL) + { + return A_NO_MEMORY; + } + + A_NETBUF_PUT (osbuf, cmdLen); + + cmd = (WMI_PYXIS_JOIN_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + + cmd->hdr.pyxisCmd = WMI_PYXIS_JOIN_PEER; + cmd->hdr.pyxisCmdLen = sizeof (WMI_PYXIS_JOIN_CMD) - sizeof (WMI_PYXIS_CMD_HDR); + + if (NULL != cmd->peerMacAddr) + { + memcpy (cmd->peerMacAddr, bssid, ATH_MAC_LEN); + } + if (NULL != cmd->nwBSSID) + { + memcpy (cmd->nwBSSID, nwBSSID, ATH_MAC_LEN); + } + + cmd->networkType = wmiNetworkType; + cmd->dot11AuthMode = dot11AuthMode; + cmd->authMode = authMode; + cmd->pairwiseCryptoType = pairwiseCrypto; + cmd->pairwiseCryptoLen = pairwiseCryptoLen; + cmd->groupCryptoType = groupCrypto; + cmd->groupCryptoLen = groupCryptoLen; + cmd->channel = channel; + cmd->ctrl_flags = ctrl_flags; + + if (wmi_set_keepalive_cmd(wmip, wmip->wmi_keepaliveInterval) != A_OK) { + return(A_ERROR); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_PYXIS_OPERATION_CMDID, NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_pyxis_disconnect_cmd (struct wmi_t *wmip, A_UINT8 *bssid) +{ + void *osbuf; + WMI_PYXIS_DISCONNECT_CMD *cmd = NULL; + A_UINT16 cmdLen; + + cmdLen = sizeof (WMI_PYXIS_DISCONNECT_CMD); + + osbuf = A_NETBUF_ALLOC (cmdLen); + + if (osbuf == NULL) + { + return A_NO_MEMORY; + } + + A_NETBUF_PUT (osbuf, cmdLen); + + cmd = (WMI_PYXIS_DISCONNECT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + + cmd->hdr.pyxisCmd = WMI_PYXIS_DISC_PEER; + cmd->hdr.pyxisCmdLen = ATH_MAC_LEN; + memcpy (cmd->peerMacAddr, bssid, ATH_MAC_LEN); + + return (wmi_cmd_send (wmip, osbuf, WMI_PYXIS_OPERATION_CMDID, NO_SYNC_WMIFLAG)); +} + +#endif +bss_t *wmi_rm_current_bss (struct wmi_t *wmip, A_UINT8 *id) +{ + wmi_get_current_bssid (wmip, id); + return wlan_node_remove (&wmip->wmi_scan_table, id); +} + +A_STATUS wmi_add_current_bss (struct wmi_t *wmip, A_UINT8 *id, bss_t *bss) +{ + wlan_setup_node (&wmip->wmi_scan_table, bss, id); + return A_OK; +} + +//////////////////////////////////////////////////////////////////////////////// +//// //// +//// AP mode functions //// +//// //// +//////////////////////////////////////////////////////////////////////////////// +/* + * IOCTL: AR6000_XIOCTL_AP_COMMIT_CONFIG + * + * When AR6K in AP mode, This command will be called after + * changing ssid, channel etc. It will pass the profile to + * target with a flag which will indicate which parameter changed, + * also if this flag is 0, there was no change in parametes, so + * commit cmd will not be sent to target. Without calling this IOCTL + * the changes will not take effect. + */ +A_STATUS +wmi_ap_profile_commit(struct wmi_t *wmip, WMI_CONNECT_CMD *p) +{ + void *osbuf; + WMI_CONNECT_CMD *cm; + + osbuf = A_NETBUF_ALLOC(sizeof(*cm)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cm)); + cm = (WMI_CONNECT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cm, sizeof(*cm)); + + A_MEMCPY(cm,p,sizeof(*cm)); + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_CONFIG_COMMIT_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_HIDDEN_SSID + * + * This command will be used to enable/disable hidden ssid functioanlity of + * beacon. If it is enabled, ssid will be NULL in beacon. + */ +A_STATUS +wmi_ap_set_hidden_ssid(struct wmi_t *wmip, A_UINT8 hidden_ssid) +{ + void *osbuf; + WMI_AP_HIDDEN_SSID_CMD *hs; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_HIDDEN_SSID_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_HIDDEN_SSID_CMD)); + hs = (WMI_AP_HIDDEN_SSID_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(hs, sizeof(*hs)); + + hs->hidden_ssid = hidden_ssid; + + A_DPRINTF(DBG_WMI, (DBGFMT "AR6000_XIOCTL_AP_HIDDEN_SSID %d\n", DBGARG , hidden_ssid)); + return (wmi_cmd_send(wmip, osbuf, WMI_AP_HIDDEN_SSID_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_SET_MAX_NUM_STA + * + * This command is used to limit max num of STA that can connect + * with this AP. This value should not exceed AP_MAX_NUM_STA (this + * is max num of STA supported by AP). Value was already validated + * in ioctl.c + */ +A_STATUS +wmi_ap_set_num_sta(struct wmi_t *wmip, A_UINT8 num_sta) +{ + void *osbuf; + WMI_AP_SET_NUM_STA_CMD *ns; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_NUM_STA_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_NUM_STA_CMD)); + ns = (WMI_AP_SET_NUM_STA_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(ns, sizeof(*ns)); + + ns->num_sta = num_sta; + + A_DPRINTF(DBG_WMI, (DBGFMT "AR6000_XIOCTL_AP_SET_MAX_NUM_STA %d\n", DBGARG , num_sta)); + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_NUM_STA_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_SET_ACL_MAC + * + * This command is used to send list of mac of STAs which will + * be allowed to connect with this AP. When this list is empty + * firware will allow all STAs till the count reaches AP_MAX_NUM_STA. + */ +A_STATUS +wmi_ap_acl_mac_list(struct wmi_t *wmip, WMI_AP_ACL_MAC_CMD *acl) +{ + void *osbuf; + WMI_AP_ACL_MAC_CMD *a; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_ACL_MAC_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_ACL_MAC_CMD)); + a = (WMI_AP_ACL_MAC_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(a, sizeof(*a)); + A_MEMCPY(a,acl,sizeof(*acl)); + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_ACL_MAC_LIST_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_SET_MLME + * + * This command is used to send list of mac of STAs which will + * be allowed to connect with this AP. When this list is empty + * firware will allow all STAs till the count reaches AP_MAX_NUM_STA. + */ +A_STATUS +wmi_ap_set_mlme(struct wmi_t *wmip, A_UINT8 cmd, A_UINT8 *mac, A_UINT16 reason) +{ + void *osbuf; + WMI_AP_SET_MLME_CMD *mlme; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_MLME_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_MLME_CMD)); + mlme = (WMI_AP_SET_MLME_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(mlme, sizeof(*mlme)); + + mlme->cmd = cmd; + A_MEMCPY(mlme->mac, mac, ATH_MAC_LEN); + mlme->reason = reason; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_MLME_CMDID, NO_SYNC_WMIFLAG)); +} + +static A_STATUS +wmi_pspoll_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_PSPOLL_EVENT *ev; + + if (len < sizeof(WMI_PSPOLL_EVENT)) { + return A_EINVAL; + } + ev = (WMI_PSPOLL_EVENT *)datap; + + A_WMI_PSPOLL_EVENT(wmip->wmi_devt, ev->aid); + return A_OK; +} + +static A_STATUS +wmi_dtimexpiry_event_rx(struct wmi_t *wmip, A_UINT8 *datap,int len) +{ + A_WMI_DTIMEXPIRY_EVENT(wmip->wmi_devt); + return A_OK; +} + +A_STATUS +wmi_set_pvb_cmd(struct wmi_t *wmip, A_UINT16 aid, A_BOOL flag) +{ + WMI_AP_SET_PVB_CMD *cmd; + void *osbuf = NULL; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_PVB_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_PVB_CMD)); + cmd = (WMI_AP_SET_PVB_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->aid = aid; + cmd->flag = flag; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_PVB_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_ap_conn_inact_time(struct wmi_t *wmip, A_UINT32 period) +{ + WMI_AP_CONN_INACT_CMD *cmd; + void *osbuf = NULL; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_CONN_INACT_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_CONN_INACT_CMD)); + cmd = (WMI_AP_CONN_INACT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->period = period; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_CONN_INACT_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_ap_bgscan_time(struct wmi_t *wmip, A_UINT32 period, A_UINT32 dwell) +{ + WMI_AP_PROT_SCAN_TIME_CMD *cmd; + void *osbuf = NULL; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_PROT_SCAN_TIME_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_PROT_SCAN_TIME_CMD)); + cmd = (WMI_AP_PROT_SCAN_TIME_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->period_min = period; + cmd->dwell_ms = dwell; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_PROT_SCAN_TIME_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_ap_set_dtim(struct wmi_t *wmip, A_UINT8 dtim) +{ + WMI_AP_SET_DTIM_CMD *cmd; + void *osbuf = NULL; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_DTIM_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_DTIM_CMD)); + cmd = (WMI_AP_SET_DTIM_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->dtim = dtim; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_DTIM_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_SET_ACL_POLICY + * + * This command is used to set ACL policay. While changing policy, if you + * want to retain the existing MAC addresses in the ACL list, policy should be + * OR with AP_ACL_RETAIN_LIST_MASK, else the existing list will be cleared. + * If there is no chage in policy, the list will be intact. + */ +A_STATUS +wmi_ap_set_acl_policy(struct wmi_t *wmip, A_UINT8 policy) +{ + void *osbuf; + WMI_AP_ACL_POLICY_CMD *po; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_ACL_POLICY_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_ACL_POLICY_CMD)); + po = (WMI_AP_ACL_POLICY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(po, sizeof(*po)); + + po->policy = policy; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_ACL_POLICY_CMDID, NO_SYNC_WMIFLAG)); +} + diff -urN linux-2.6.26/drivers/net/wireless/ath6k/wmi.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/wmi.h --- linux-2.6.26/drivers/net/wireless/ath6k/wmi.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/wmi.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,2263 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +/* + * This file contains the definitions of the WMI protocol specified in the + * Wireless Module Interface (WMI). It includes definitions of all the + * commands and events. Commands are messages from the host to the WM. + * Events and Replies are messages from the WM to the host. + * + * Ownership of correctness in regards to WMI commands + * belongs to the host driver and the WM is not required to validate + * parameters for value, proper range, or any other checking. + * + */ + +#ifndef _WMI_H_ +#define _WMI_H_ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#include "wmix.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HTC_PROTOCOL_VERSION 0x0002 +#define HTC_PROTOCOL_REVISION 0x0000 + +#define WMI_PROTOCOL_VERSION 0x0002 +#define WMI_PROTOCOL_REVISION 0x0000 + +#define ATH_MAC_LEN 6 /* length of mac in bytes */ +#define WMI_CMD_MAX_LEN 100 +#define WMI_CONTROL_MSG_MAX_LEN 256 +#define WMI_OPT_CONTROL_MSG_MAX_LEN 1536 +#define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600) +#define RFC1042OUI {0x00, 0x00, 0x00} + +#define IP_ETHERTYPE 0x0800 + +#define WMI_IMPLICIT_PSTREAM 0xFF +#define WMI_MAX_THINSTREAM 15 + +struct host_app_area_s { + A_UINT32 wmi_protocol_ver; +}; + +/* + * Data Path + */ +typedef PREPACK struct { + A_UINT8 dstMac[ATH_MAC_LEN]; + A_UINT8 srcMac[ATH_MAC_LEN]; + A_UINT16 typeOrLen; +} POSTPACK ATH_MAC_HDR; + +typedef PREPACK struct { + A_UINT8 dsap; + A_UINT8 ssap; + A_UINT8 cntl; + A_UINT8 orgCode[3]; + A_UINT16 etherType; +} POSTPACK ATH_LLC_SNAP_HDR; + +typedef enum { + DATA_MSGTYPE = 0x0, + CNTL_MSGTYPE, + SYNC_MSGTYPE, + OPT_MSGTYPE, +} WMI_MSG_TYPE; + + +typedef PREPACK struct { + A_INT8 rssi; + A_UINT8 info; /* WMI_MSG_TYPE in lower 2 bits - b1b0 */ + /* UP in next 3 bits - b4b3b2 */ +#define WMI_DATA_HDR_MSG_TYPE_MASK 0x03 +#define WMI_DATA_HDR_MSG_TYPE_SHIFT 0 +#define WMI_DATA_HDR_UP_MASK 0x07 +#define WMI_DATA_HDR_UP_SHIFT 2 +#define WMI_DATA_HDR_IS_MSG_TYPE(h, t) (((h)->info & (WMI_DATA_HDR_MSG_TYPE_MASK)) == (t)) +/* In AP mode, the same bit (b5) is used to indicate Power save state in + * the Rx dir and More data bit state in the tx direction. + */ +#define WMI_DATA_HDR_PS_MASK 0x1 +#define WMI_DATA_HDR_PS_SHIFT 5 + +#define WMI_DATA_HDR_MORE_MASK 0x1 +#define WMI_DATA_HDR_MORE_SHIFT 5 + +#define WMI_DATA_HDR_SET_MORE_BIT(h) ((h)->info |= (WMI_DATA_HDR_MORE_MASK << WMI_DATA_HDR_MORE_SHIFT)) + +} POSTPACK WMI_DATA_HDR; + + +#define WMI_DATA_HDR_SET_MSG_TYPE(h, t) (h)->info = (((h)->info & ~(WMI_DATA_HDR_MSG_TYPE_MASK << WMI_DATA_HDR_MSG_TYPE_SHIFT)) | (t << WMI_DATA_HDR_MSG_TYPE_SHIFT)) +#define WMI_DATA_HDR_SET_UP(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_UP_MASK << WMI_DATA_HDR_UP_SHIFT)) | (p << WMI_DATA_HDR_UP_SHIFT)) + +/* + * Control Path + */ +typedef PREPACK struct { + A_UINT16 commandId; +} POSTPACK WMI_CMD_HDR; /* used for commands and events */ + +/* + * List of Commnands + */ +typedef enum { + WMI_CONNECT_CMDID = 0x0001, + WMI_RECONNECT_CMDID, + WMI_DISCONNECT_CMDID, + WMI_SYNCHRONIZE_CMDID, + WMI_CREATE_PSTREAM_CMDID, + WMI_DELETE_PSTREAM_CMDID, + WMI_START_SCAN_CMDID, + WMI_SET_SCAN_PARAMS_CMDID, + WMI_SET_BSS_FILTER_CMDID, + WMI_SET_PROBED_SSID_CMDID, /* 10 */ + WMI_SET_LISTEN_INT_CMDID, + WMI_SET_BMISS_TIME_CMDID, + WMI_SET_DISC_TIMEOUT_CMDID, + WMI_GET_CHANNEL_LIST_CMDID, + WMI_SET_BEACON_INT_CMDID, + WMI_GET_STATISTICS_CMDID, + WMI_SET_CHANNEL_PARAMS_CMDID, + WMI_SET_POWER_MODE_CMDID, + WMI_SET_IBSS_PM_CAPS_CMDID, + WMI_SET_POWER_PARAMS_CMDID, /* 20 */ + WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID, + WMI_ADD_CIPHER_KEY_CMDID, + WMI_DELETE_CIPHER_KEY_CMDID, + WMI_ADD_KRK_CMDID, + WMI_DELETE_KRK_CMDID, + WMI_SET_PMKID_CMDID, + WMI_SET_TX_PWR_CMDID, + WMI_GET_TX_PWR_CMDID, + WMI_SET_ASSOC_INFO_CMDID, + WMI_ADD_BAD_AP_CMDID, /* 30 */ + WMI_DELETE_BAD_AP_CMDID, + WMI_SET_TKIP_COUNTERMEASURES_CMDID, + WMI_RSSI_THRESHOLD_PARAMS_CMDID, + WMI_TARGET_ERROR_REPORT_BITMASK_CMDID, + WMI_SET_ACCESS_PARAMS_CMDID, + WMI_SET_RETRY_LIMITS_CMDID, + WMI_SET_OPT_MODE_CMDID, + WMI_OPT_TX_FRAME_CMDID, + WMI_SET_VOICE_PKT_SIZE_CMDID, + WMI_SET_MAX_SP_LEN_CMDID, /* 40 */ + WMI_SET_ROAM_CTRL_CMDID, + WMI_GET_ROAM_TBL_CMDID, + WMI_GET_ROAM_DATA_CMDID, + WMI_ENABLE_RM_CMDID, + WMI_SET_MAX_OFFHOME_DURATION_CMDID, + WMI_EXTENSION_CMDID, /* Non-wireless extensions */ + WMI_SNR_THRESHOLD_PARAMS_CMDID, + WMI_LQ_THRESHOLD_PARAMS_CMDID, + WMI_SET_LPREAMBLE_CMDID, + WMI_SET_RTS_CMDID, /* 50 */ + WMI_CLR_RSSI_SNR_CMDID, + WMI_SET_FIXRATES_CMDID, + WMI_GET_FIXRATES_CMDID, + WMI_SET_AUTH_MODE_CMDID, + WMI_SET_REASSOC_MODE_CMDID, + WMI_SET_WMM_CMDID, + WMI_SET_WMM_TXOP_CMDID, + WMI_TEST_CMDID, + WMI_SET_BT_STATUS_CMDID, + WMI_SET_BT_PARAMS_CMDID, /* 60 */ + + WMI_SET_KEEPALIVE_CMDID, + WMI_GET_KEEPALIVE_CMDID, + WMI_SET_APPIE_CMDID, + WMI_GET_APPIE_CMDID, + WMI_SET_WSC_STATUS_CMDID, + + /* Wake on Wireless */ + WMI_SET_HOST_SLEEP_MODE_CMDID, + WMI_SET_WOW_MODE_CMDID, + WMI_GET_WOW_LIST_CMDID, + WMI_ADD_WOW_PATTERN_CMDID, + WMI_DEL_WOW_PATTERN_CMDID, /* 70 */ + + WMI_SET_FRAMERATES_CMDID, + /* + * Developer commands starts at 0xF000 + */ + WMI_SET_BITRATE_CMDID = 0xF000, + WMI_GET_BITRATE_CMDID, + WMI_SET_WHALPARAM_CMDID, + + + /*Should add the new command to the tail for compatible with + * etna. + */ + WMI_SET_MAC_ADDRESS_CMDID, + WMI_SET_AKMP_PARAMS_CMDID, + WMI_SET_PMKID_LIST_CMDID, + WMI_GET_PMKID_LIST_CMDID, + WMI_ABORT_SCAN_CMDID, + WMI_SET_TARGET_EVENT_REPORT_CMDID, + + // Pyxis specific Command IDs + WMI_PYXIS_CONFIG_CMDID, + WMI_PYXIS_OPERATION_CMDID, /* 0xF00A */ + + /* + * AP mode commands + */ + WMI_AP_HIDDEN_SSID_CMDID, + WMI_AP_SET_NUM_STA_CMDID, + WMI_AP_ACL_POLICY_CMDID, + WMI_AP_ACL_MAC_LIST_CMDID, + WMI_AP_CONFIG_COMMIT_CMDID, + WMI_AP_SET_MLME_CMDID, + WMI_AP_SET_PVB_CMDID, + WMI_AP_CONN_INACT_CMDID, + WMI_AP_PROT_SCAN_TIME_CMDID, + WMI_AP_SET_COUNTRY_CMDID, /* 0xF014 */ + WMI_AP_SET_DTIM_CMDID, + + WMI_SET_IP_CMDID, + WMI_SET_PARAMS_CMDID, + WMI_SET_MCAST_FILTER_CMDID, + WMI_DEL_MCAST_FILTER_CMDID +} WMI_COMMAND_ID; + +/* + * Frame Types + */ +typedef enum { + WMI_FRAME_BEACON = 0, + WMI_FRAME_PROBE_REQ, + WMI_FRAME_PROBE_RESP, + WMI_FRAME_ASSOC_REQ, + WMI_FRAME_ASSOC_RESP, + WMI_NUM_MGMT_FRAME +} WMI_MGMT_FRAME_TYPE; + +/* + * Connect Command + */ +typedef enum { + INFRA_NETWORK = 0x01, + ADHOC_NETWORK = 0x02, + ADHOC_CREATOR = 0x04, + OPT_NETWORK = 0x08, + AP_NETWORK = 0x10, +} NETWORK_TYPE; + +typedef enum { + OPEN_AUTH = 0x01, + SHARED_AUTH = 0x02, + LEAP_AUTH = 0x04, /* different from IEEE_AUTH_MODE definitions */ +} DOT11_AUTH_MODE; + +typedef enum { + NONE_AUTH = 0x01, + WPA_AUTH = 0x02, + WPA_PSK_AUTH = 0x03, + WPA2_AUTH = 0x04, + WPA2_PSK_AUTH = 0x05, + WPA_AUTH_CCKM = 0x06, + WPA2_AUTH_CCKM = 0x07, +} AUTH_MODE; + +typedef enum { + NONE_CRYPT = 0x01, + WEP_CRYPT = 0x02, + TKIP_CRYPT = 0x03, + AES_CRYPT = 0x04, +#ifdef WAPI_ENABLE + WAPI_CRYPT = 0x05, +#endif /* WAPI_ENABLE */ +} CRYPTO_TYPE; + +#define WMI_MIN_CRYPTO_TYPE NONE_CRYPT +#ifndef WAPI_ENABLE +#define WMI_MAX_CRYPTO_TYPE (AES_CRYPT + 1) +#else +#define WMI_MAX_CRYPTO_TYPE (WAPI_CRYPT + 1) +#endif /* WAPI_ENABLE */ + +#define WMI_MIN_KEY_INDEX 0 +#ifndef WAPI_ENABLE +#define WMI_MAX_KEY_INDEX 3 +#else +#define WMI_MAX_KEY_INDEX 7 /* wapi grpKey 0-3, prwKey 4-7 */ +#endif + +#define WMI_MAX_KEY_LEN 32 + +#define WMI_MAX_SSID_LEN 32 + +typedef enum { + CONNECT_ASSOC_POLICY_USER = 0x0001, + CONNECT_SEND_REASSOC = 0x0002, + CONNECT_IGNORE_WPAx_GROUP_CIPHER = 0x0004, + CONNECT_PROFILE_MATCH_DONE = 0x0008, + CONNECT_IGNORE_AAC_BEACON = 0x0010, + CONNECT_CSA_FOLLOW_BSS = 0x0020, + CONNECT_PYXIS_REMOTE = 0x0040, +} WMI_CONNECT_CTRL_FLAGS_BITS; + +#define DEFAULT_CONNECT_CTRL_FLAGS (CONNECT_CSA_FOLLOW_BSS) + +typedef PREPACK struct { + A_UINT8 networkType; + A_UINT8 dot11AuthMode; + A_UINT8 authMode; + A_UINT8 pairwiseCryptoType; + A_UINT8 pairwiseCryptoLen; + A_UINT8 groupCryptoType; + A_UINT8 groupCryptoLen; + A_UINT8 ssidLength; + A_UCHAR ssid[WMI_MAX_SSID_LEN]; + A_UINT16 channel; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT32 ctrl_flags; +} POSTPACK WMI_CONNECT_CMD; + +/* + * WMI_RECONNECT_CMDID + */ +typedef PREPACK struct { + A_UINT16 channel; /* hint */ + A_UINT8 bssid[ATH_MAC_LEN]; /* mandatory if set */ +} POSTPACK WMI_RECONNECT_CMD; + +/* + * WMI_ADD_CIPHER_KEY_CMDID + */ +typedef enum { + PAIRWISE_USAGE = 0x00, + GROUP_USAGE = 0x01, + TX_USAGE = 0x02, /* default Tx Key - Static WEP only */ +} KEY_USAGE; + +/* + * Bit Flag + * Bit 0 - Initialise TSC - default is Initialize + */ +#define KEY_OP_INIT_TSC 0x01 +#define KEY_OP_INIT_RSC 0x02 +#ifdef WAPI_ENABLE +#define KEY_OP_INIT_WAPIPN 0x10 +#endif + +#define KEY_OP_INIT_VAL 0x03 /* Default Initialise the TSC & RSC */ +#define KEY_OP_VALID_MASK 0x03 + +typedef PREPACK struct { + A_UINT8 keyIndex; + A_UINT8 keyType; + A_UINT8 keyUsage; /* KEY_USAGE */ + A_UINT8 keyLength; + A_UINT8 keyRSC[8]; /* key replay sequence counter */ + A_UINT8 key[WMI_MAX_KEY_LEN]; + A_UINT8 key_op_ctrl; /* Additional Key Control information */ + A_UINT8 key_macaddr[ATH_MAC_LEN]; +} POSTPACK WMI_ADD_CIPHER_KEY_CMD; + +/* + * WMI_DELETE_CIPHER_KEY_CMDID + */ +typedef PREPACK struct { + A_UINT8 keyIndex; +} POSTPACK WMI_DELETE_CIPHER_KEY_CMD; + +#define WMI_KRK_LEN 16 +/* + * WMI_ADD_KRK_CMDID + */ +typedef PREPACK struct { + A_UINT8 krk[WMI_KRK_LEN]; +} POSTPACK WMI_ADD_KRK_CMD; + +/* + * WMI_SET_TKIP_COUNTERMEASURES_CMDID + */ +typedef enum { + WMI_TKIP_CM_DISABLE = 0x0, + WMI_TKIP_CM_ENABLE = 0x1, +} WMI_TKIP_CM_CONTROL; + +typedef PREPACK struct { + A_UINT8 cm_en; /* WMI_TKIP_CM_CONTROL */ +} POSTPACK WMI_SET_TKIP_COUNTERMEASURES_CMD; + +/* + * WMI_SET_PMKID_CMDID + */ + +#define WMI_PMKID_LEN 16 + +typedef enum { + PMKID_DISABLE = 0, + PMKID_ENABLE = 1, +} PMKID_ENABLE_FLG; + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT8 enable; /* PMKID_ENABLE_FLG */ + A_UINT8 pmkid[WMI_PMKID_LEN]; +} POSTPACK WMI_SET_PMKID_CMD; + +/* + * WMI_START_SCAN_CMD + */ +typedef enum { + WMI_LONG_SCAN = 0, + WMI_SHORT_SCAN = 1, + WMI_PYXIS_PAS_DSCVR = 0, + WMI_PYXIS_ACT_DSCVR = 1, +} WMI_SCAN_TYPE; + +typedef PREPACK struct { + A_BOOL forceFgScan; + A_BOOL isLegacy; /* For Legacy Cisco AP compatibility */ + A_UINT32 homeDwellTime; /* Maximum duration in the home channel(milliseconds) */ + A_UINT32 forceScanInterval; /* Time interval between scans (milliseconds)*/ + A_UINT8 scanType; /* WMI_SCAN_TYPE */ + A_UINT8 numChannels; /* how many channels follow */ + A_UINT16 channelList[1]; /* channels in Mhz */ +} POSTPACK WMI_START_SCAN_CMD; + +/* + * WMI_SET_SCAN_PARAMS_CMDID + */ +#define WMI_SHORTSCANRATIO_DEFAULT 3 +typedef enum { + CONNECT_SCAN_CTRL_FLAGS = 0x01, /* set if can scan in the Connect cmd */ + SCAN_CONNECTED_CTRL_FLAGS = 0x02, /* set if scan for the SSID it is */ + /* already connected to */ + ACTIVE_SCAN_CTRL_FLAGS = 0x04, /* set if enable active scan */ + ROAM_SCAN_CTRL_FLAGS = 0x08, /* set if enable roam scan when bmiss and lowrssi */ + REPORT_BSSINFO_CTRL_FLAGS = 0x10, /* set if follows customer BSSINFO reporting rule */ + ENABLE_AUTO_CTRL_FLAGS = 0x20, /* if disabled, target doesn't + scan after a disconnect event */ + ENABLE_SCAN_ABORT_EVENT = 0x40 /* Scan complete event with canceled status will be generated when a scan is prempted before it gets completed */ + +} WMI_SCAN_CTRL_FLAGS_BITS; + +#define CAN_SCAN_IN_CONNECT(flags) (flags & CONNECT_SCAN_CTRL_FLAGS) +#define CAN_SCAN_CONNECTED(flags) (flags & SCAN_CONNECTED_CTRL_FLAGS) +#define ENABLE_ACTIVE_SCAN(flags) (flags & ACTIVE_SCAN_CTRL_FLAGS) +#define ENABLE_ROAM_SCAN(flags) (flags & ROAM_SCAN_CTRL_FLAGS) +#define CONFIG_REPORT_BSSINFO(flags) (flags & REPORT_BSSINFO_CTRL_FLAGS) +#define IS_AUTO_SCAN_ENABLED(flags) (flags & ENABLE_AUTO_CTRL_FLAGS) +#define SCAN_ABORT_EVENT_ENABLED(flags) (flags & ENABLE_SCAN_ABORT_EVENT) + +#define DEFAULT_SCAN_CTRL_FLAGS (CONNECT_SCAN_CTRL_FLAGS| SCAN_CONNECTED_CTRL_FLAGS| ACTIVE_SCAN_CTRL_FLAGS| ROAM_SCAN_CTRL_FLAGS | ENABLE_AUTO_CTRL_FLAGS) + + +typedef PREPACK struct { + A_UINT16 fg_start_period; /* seconds */ + A_UINT16 fg_end_period; /* seconds */ + A_UINT16 bg_period; /* seconds */ + A_UINT16 maxact_chdwell_time; /* msec */ + A_UINT16 pas_chdwell_time; /* msec */ + A_UINT8 shortScanRatio; /* how many shorts scan for one long */ + A_UINT8 scanCtrlFlags; + A_UINT16 minact_chdwell_time; /* msec */ + A_UINT16 maxact_scan_per_ssid; /* max active scans per ssid */ + A_UINT32 max_dfsch_act_time; /* msecs */ +} POSTPACK WMI_SCAN_PARAMS_CMD; + +/* + * WMI_SET_BSS_FILTER_CMDID + */ +typedef enum { + NONE_BSS_FILTER = 0x0, /* no beacons forwarded */ + ALL_BSS_FILTER, /* all beacons forwarded */ + PROFILE_FILTER, /* only beacons matching profile */ + ALL_BUT_PROFILE_FILTER, /* all but beacons matching profile */ + CURRENT_BSS_FILTER, /* only beacons matching current BSS */ + ALL_BUT_BSS_FILTER, /* all but beacons matching BSS */ + PROBED_SSID_FILTER, /* beacons matching probed ssid */ + LAST_BSS_FILTER, /* marker only */ +} WMI_BSS_FILTER; + +typedef PREPACK struct { + A_UINT8 bssFilter; /* see WMI_BSS_FILTER */ + A_UINT8 reserved1; /* For alignment */ + A_UINT16 reserved2; /* For alignment */ + A_UINT32 ieMask; +} POSTPACK WMI_BSS_FILTER_CMD; + +/* + * WMI_SET_PROBED_SSID_CMDID + */ +#define MAX_PROBED_SSID_INDEX 5 + +typedef enum { + DISABLE_SSID_FLAG = 0, /* disables entry */ + SPECIFIC_SSID_FLAG = 0x01, /* probes specified ssid */ + ANY_SSID_FLAG = 0x02, /* probes for any ssid */ +} WMI_SSID_FLAG; + +typedef PREPACK struct { + A_UINT8 entryIndex; /* 0 to MAX_PROBED_SSID_INDEX */ + A_UINT8 flag; /* WMI_SSID_FLG */ + A_UINT8 ssidLength; + A_UINT8 ssid[32]; +} POSTPACK WMI_PROBED_SSID_CMD; + +/* + * WMI_SET_LISTEN_INT_CMDID + * The Listen interval is between 15 and 3000 TUs + */ +#define MIN_LISTEN_INTERVAL 15 +#define MAX_LISTEN_INTERVAL 5000 +#define MIN_LISTEN_BEACONS 1 +#define MAX_LISTEN_BEACONS 50 + +typedef PREPACK struct { + A_UINT16 listenInterval; + A_UINT16 numBeacons; +} POSTPACK WMI_LISTEN_INT_CMD; + +/* + * WMI_SET_BEACON_INT_CMDID + */ +typedef PREPACK struct { + A_UINT16 beaconInterval; +} POSTPACK WMI_BEACON_INT_CMD; + +/* + * WMI_SET_BMISS_TIME_CMDID + * valid values are between 1000 and 5000 TUs + */ + +#define MIN_BMISS_TIME 1000 +#define MAX_BMISS_TIME 5000 +#define MIN_BMISS_BEACONS 1 +#define MAX_BMISS_BEACONS 50 + +typedef PREPACK struct { + A_UINT16 bmissTime; + A_UINT16 numBeacons; +} POSTPACK WMI_BMISS_TIME_CMD; + +/* + * WMI_SET_POWER_MODE_CMDID + */ +typedef enum { + REC_POWER = 0x01, + MAX_PERF_POWER, +} WMI_POWER_MODE; + +typedef PREPACK struct { + A_UINT8 powerMode; /* WMI_POWER_MODE */ +} POSTPACK WMI_POWER_MODE_CMD; + +typedef PREPACK struct { + A_INT8 status; /* WMI_SET_PARAMS_REPLY */ +} POSTPACK WMI_SET_PARAMS_REPLY; + +typedef PREPACK struct { + A_UINT32 opcode; + A_UINT32 length; + A_CHAR buffer[1]; /* WMI_SET_PARAMS */ +} POSTPACK WMI_SET_PARAMS_CMD; + +typedef PREPACK struct { + A_UINT8 multicast_mac[ATH_MAC_LEN]; /* WMI_SET_MCAST_FILTER */ +} POSTPACK WMI_SET_MCAST_FILTER_CMD; + +/* + * WMI_SET_POWER_PARAMS_CMDID + */ +typedef enum { + IGNORE_DTIM = 0x01, + NORMAL_DTIM = 0x02, + STICK_DTIM = 0x03, +} WMI_DTIM_POLICY; + +typedef PREPACK struct { + A_UINT16 idle_period; /* msec */ + A_UINT16 pspoll_number; + A_UINT16 dtim_policy; +} POSTPACK WMI_POWER_PARAMS_CMD; + +typedef PREPACK struct { + A_UINT8 power_saving; + A_UINT8 ttl; /* number of beacon periods */ + A_UINT16 atim_windows; /* msec */ + A_UINT16 timeout_value; /* msec */ +} POSTPACK WMI_IBSS_PM_CAPS_CMD; + +/* + * WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID + */ +typedef enum { + IGNORE_TIM_ALL_QUEUES_APSD = 0, + PROCESS_TIM_ALL_QUEUES_APSD = 1, + IGNORE_TIM_SIMULATED_APSD = 2, + PROCESS_TIM_SIMULATED_APSD = 3, +} APSD_TIM_POLICY; + +typedef PREPACK struct { + A_UINT16 psPollTimeout; /* msec */ + A_UINT16 triggerTimeout; /* msec */ + A_UINT32 apsdTimPolicy; /* TIM behavior with ques APSD enabled. Default is IGNORE_TIM_ALL_QUEUES_APSD */ + A_UINT32 simulatedAPSDTimPolicy; /* TIM behavior with simulated APSD enabled. Default is PROCESS_TIM_SIMULATED_APSD */ +} POSTPACK WMI_POWERSAVE_TIMERS_POLICY_CMD; + +/* + * WMI_SET_VOICE_PKT_SIZE_CMDID + */ +typedef PREPACK struct { + A_UINT16 voicePktSize; +} POSTPACK WMI_SET_VOICE_PKT_SIZE_CMD; + +/* + * WMI_SET_MAX_SP_LEN_CMDID + */ +typedef enum { + DELIVER_ALL_PKT = 0x0, + DELIVER_2_PKT = 0x1, + DELIVER_4_PKT = 0x2, + DELIVER_6_PKT = 0x3, +} APSD_SP_LEN_TYPE; + +typedef PREPACK struct { + A_UINT8 maxSPLen; +} POSTPACK WMI_SET_MAX_SP_LEN_CMD; + +/* + * WMI_SET_DISC_TIMEOUT_CMDID + */ +typedef PREPACK struct { + A_UINT8 disconnectTimeout; /* seconds */ +} POSTPACK WMI_DISC_TIMEOUT_CMD; + +typedef enum { + UPLINK_TRAFFIC = 0, + DNLINK_TRAFFIC = 1, + BIDIR_TRAFFIC = 2, +} DIR_TYPE; + +typedef enum { + DISABLE_FOR_THIS_AC = 0, + ENABLE_FOR_THIS_AC = 1, + ENABLE_FOR_ALL_AC = 2, +} VOICEPS_CAP_TYPE; + +typedef enum { + TRAFFIC_TYPE_APERIODIC = 0, + TRAFFIC_TYPE_PERIODIC = 1, +}TRAFFIC_TYPE; + +/* + * WMI_SYNCHRONIZE_CMDID + */ +typedef PREPACK struct { + A_UINT8 dataSyncMap; +} POSTPACK WMI_SYNC_CMD; + +/* + * WMI_CREATE_PSTREAM_CMDID + */ +typedef PREPACK struct { + A_UINT32 minServiceInt; /* in milli-sec */ + A_UINT32 maxServiceInt; /* in milli-sec */ + A_UINT32 inactivityInt; /* in milli-sec */ + A_UINT32 suspensionInt; /* in milli-sec */ + A_UINT32 serviceStartTime; + A_UINT32 minDataRate; /* in bps */ + A_UINT32 meanDataRate; /* in bps */ + A_UINT32 peakDataRate; /* in bps */ + A_UINT32 maxBurstSize; + A_UINT32 delayBound; + A_UINT32 minPhyRate; /* in bps */ + A_UINT32 sba; + A_UINT32 mediumTime; + A_UINT16 nominalMSDU; /* in octects */ + A_UINT16 maxMSDU; /* in octects */ + A_UINT8 trafficClass; + A_UINT8 trafficDirection; /* DIR_TYPE */ + A_UINT8 rxQueueNum; + A_UINT8 trafficType; /* TRAFFIC_TYPE */ + A_UINT8 voicePSCapability; /* VOICEPS_CAP_TYPE */ + A_UINT8 tsid; + A_UINT8 userPriority; /* 802.1D user priority */ + A_UINT8 nominalPHY; /* nominal phy rate */ +} POSTPACK WMI_CREATE_PSTREAM_CMD; + +/* + * WMI_DELETE_PSTREAM_CMDID + */ +typedef PREPACK struct { + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficDirection; + A_UINT8 trafficClass; + A_UINT8 tsid; +} POSTPACK WMI_DELETE_PSTREAM_CMD; + +/* + * WMI_SET_CHANNEL_PARAMS_CMDID + */ +typedef enum { + WMI_11A_MODE = 0x1, + WMI_11G_MODE = 0x2, + WMI_11AG_MODE = 0x3, + WMI_11B_MODE = 0x4, + WMI_11GONLY_MODE = 0x5, +} WMI_PHY_MODE; + +#define WMI_MAX_CHANNELS 32 + +typedef PREPACK struct { + A_UINT8 reserved1; + A_UINT8 scanParam; /* set if enable scan */ + A_UINT8 phyMode; /* see WMI_PHY_MODE */ + A_UINT8 numChannels; /* how many channels follow */ + A_UINT16 channelList[1]; /* channels in Mhz */ +} POSTPACK WMI_CHANNEL_PARAMS_CMD; + + +/* + * WMI_RSSI_THRESHOLD_PARAMS_CMDID + * Setting the polltime to 0 would disable polling. + * Threshold values are in the ascending order, and should agree to: + * (lowThreshold_lowerVal < lowThreshold_upperVal < highThreshold_lowerVal + * < highThreshold_upperVal) + */ + +typedef PREPACK struct WMI_RSSI_THRESHOLD_PARAMS{ + A_UINT32 pollTime; /* Polling time as a factor of LI */ + A_INT16 thresholdAbove1_Val; /* lowest of upper */ + A_INT16 thresholdAbove2_Val; + A_INT16 thresholdAbove3_Val; + A_INT16 thresholdAbove4_Val; + A_INT16 thresholdAbove5_Val; + A_INT16 thresholdAbove6_Val; /* highest of upper */ + A_INT16 thresholdBelow1_Val; /* lowest of bellow */ + A_INT16 thresholdBelow2_Val; + A_INT16 thresholdBelow3_Val; + A_INT16 thresholdBelow4_Val; + A_INT16 thresholdBelow5_Val; + A_INT16 thresholdBelow6_Val; /* highest of bellow */ + A_UINT8 weight; /* "alpha" */ + A_UINT8 reserved[3]; +} POSTPACK WMI_RSSI_THRESHOLD_PARAMS_CMD; + +/* + * WMI_SNR_THRESHOLD_PARAMS_CMDID + * Setting the polltime to 0 would disable polling. + */ + +typedef PREPACK struct WMI_SNR_THRESHOLD_PARAMS{ + A_UINT32 pollTime; /* Polling time as a factor of LI */ + A_UINT8 weight; /* "alpha" */ + A_UINT8 thresholdAbove1_Val; /* lowest of uppper*/ + A_UINT8 thresholdAbove2_Val; + A_UINT8 thresholdAbove3_Val; + A_UINT8 thresholdAbove4_Val; /* highest of upper */ + A_UINT8 thresholdBelow1_Val; /* lowest of bellow */ + A_UINT8 thresholdBelow2_Val; + A_UINT8 thresholdBelow3_Val; + A_UINT8 thresholdBelow4_Val; /* highest of bellow */ + A_UINT8 reserved[3]; +} POSTPACK WMI_SNR_THRESHOLD_PARAMS_CMD; + +/* + * WMI_LQ_THRESHOLD_PARAMS_CMDID + */ +typedef PREPACK struct WMI_LQ_THRESHOLD_PARAMS { + A_UINT8 enable; + A_UINT8 thresholdAbove1_Val; + A_UINT8 thresholdAbove2_Val; + A_UINT8 thresholdAbove3_Val; + A_UINT8 thresholdAbove4_Val; + A_UINT8 thresholdBelow1_Val; + A_UINT8 thresholdBelow2_Val; + A_UINT8 thresholdBelow3_Val; + A_UINT8 thresholdBelow4_Val; + A_UINT8 reserved[3]; +} POSTPACK WMI_LQ_THRESHOLD_PARAMS_CMD; + +typedef enum { + WMI_LPREAMBLE_DISABLED = 0, + WMI_LPREAMBLE_ENABLED +} WMI_LPREAMBLE_STATUS; + +typedef PREPACK struct { + A_UINT8 status; +}POSTPACK WMI_SET_LPREAMBLE_CMD; + +typedef PREPACK struct { + A_UINT16 threshold; +}POSTPACK WMI_SET_RTS_CMD; + +/* + * WMI_TARGET_ERROR_REPORT_BITMASK_CMDID + * Sets the error reporting event bitmask in target. Target clears it + * upon an error. Subsequent errors are counted, but not reported + * via event, unless the bitmask is set again. + */ +typedef PREPACK struct { + A_UINT32 bitmask; +} POSTPACK WMI_TARGET_ERROR_REPORT_BITMASK; + +/* + * WMI_SET_TX_PWR_CMDID + */ +typedef PREPACK struct { + A_UINT8 dbM; /* in dbM units */ +} POSTPACK WMI_SET_TX_PWR_CMD, WMI_TX_PWR_REPLY; + +/* + * WMI_SET_ASSOC_INFO_CMDID + * + * A maximum of 2 private IEs can be sent in the [Re]Assoc request. + * A 3rd one, the CCX version IE can also be set from the host. + */ +#define WMI_MAX_ASSOC_INFO_TYPE 2 +#define WMI_CCX_VER_IE 2 /* ieType to set CCX Version IE */ + +#define WMI_MAX_ASSOC_INFO_LEN 240 + +typedef PREPACK struct { + A_UINT8 ieType; + A_UINT8 bufferSize; + A_UINT8 assocInfo[1]; /* up to WMI_MAX_ASSOC_INFO_LEN */ +} POSTPACK WMI_SET_ASSOC_INFO_CMD; + + +/* + * WMI_GET_TX_PWR_CMDID does not take any parameters + */ + +/* + * WMI_ADD_BAD_AP_CMDID + */ +#define WMI_MAX_BAD_AP_INDEX 1 + +typedef PREPACK struct { + A_UINT8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */ + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_ADD_BAD_AP_CMD; + +/* + * WMI_DELETE_BAD_AP_CMDID + */ +typedef PREPACK struct { + A_UINT8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */ +} POSTPACK WMI_DELETE_BAD_AP_CMD; + +/* + * WMI_SET_ACCESS_PARAMS_CMDID + */ +#define WMI_DEFAULT_TXOP_ACPARAM 0 /* implies one MSDU */ +#define WMI_DEFAULT_ECWMIN_ACPARAM 4 /* corresponds to CWmin of 15 */ +#define WMI_DEFAULT_ECWMAX_ACPARAM 10 /* corresponds to CWmax of 1023 */ +#define WMI_MAX_CW_ACPARAM 15 /* maximum eCWmin or eCWmax */ +#define WMI_DEFAULT_AIFSN_ACPARAM 2 +#define WMI_MAX_AIFSN_ACPARAM 15 +typedef PREPACK struct { + A_UINT16 txop; /* in units of 32 usec */ + A_UINT8 eCWmin; + A_UINT8 eCWmax; + A_UINT8 aifsn; +} POSTPACK WMI_SET_ACCESS_PARAMS_CMD; + + +/* + * WMI_SET_RETRY_LIMITS_CMDID + * + * This command is used to customize the number of retries the + * wlan device will perform on a given frame. + */ +#define WMI_MIN_RETRIES 2 +#define WMI_MAX_RETRIES 13 +typedef enum { + MGMT_FRAMETYPE = 0, + CONTROL_FRAMETYPE = 1, + DATA_FRAMETYPE = 2 +} WMI_FRAMETYPE; + +typedef PREPACK struct { + A_UINT8 frameType; /* WMI_FRAMETYPE */ + A_UINT8 trafficClass; /* applies only to DATA_FRAMETYPE */ + A_UINT8 maxRetries; + A_UINT8 enableNotify; +} POSTPACK WMI_SET_RETRY_LIMITS_CMD; + +/* + * WMI_SET_ROAM_CTRL_CMDID + * + * This command is used to influence the Roaming behaviour + * Set the host biases of the BSSs before setting the roam mode as bias + * based. + */ + +/* + * Different types of Roam Control + */ + +typedef enum { + WMI_FORCE_ROAM = 1, /* Roam to the specified BSSID */ + WMI_SET_ROAM_MODE = 2, /* default ,progd bias, no roam */ + WMI_SET_HOST_BIAS = 3, /* Set the Host Bias */ + WMI_SET_LOWRSSI_SCAN_PARAMS = 4, /* Set lowrssi Scan parameters */ +} WMI_ROAM_CTRL_TYPE; + +#define WMI_MIN_ROAM_CTRL_TYPE WMI_FORCE_ROAM +#define WMI_MAX_ROAM_CTRL_TYPE WMI_SET_LOWRSSI_SCAN_PARAMS + +/* + * ROAM MODES + */ + +typedef enum { + WMI_DEFAULT_ROAM_MODE = 1, /* RSSI based ROAM */ + WMI_HOST_BIAS_ROAM_MODE = 2, /* HOST BIAS based ROAM */ + WMI_LOCK_BSS_MODE = 3 /* Lock to the Current BSS - no Roam */ +} WMI_ROAM_MODE; + +/* + * BSS HOST BIAS INFO + */ + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_INT8 bias; +} POSTPACK WMI_BSS_BIAS; + +typedef PREPACK struct { + A_UINT8 numBss; + WMI_BSS_BIAS bssBias[1]; +} POSTPACK WMI_BSS_BIAS_INFO; + +typedef PREPACK struct WMI_LOWRSSI_SCAN_PARAMS { + A_UINT16 lowrssi_scan_period; + A_INT16 lowrssi_scan_threshold; + A_INT16 lowrssi_roam_threshold; + A_UINT8 roam_rssi_floor; + A_UINT8 reserved[1]; /* For alignment */ +} POSTPACK WMI_LOWRSSI_SCAN_PARAMS; + +typedef PREPACK struct { + PREPACK union { + A_UINT8 bssid[ATH_MAC_LEN]; /* WMI_FORCE_ROAM */ + A_UINT8 roamMode; /* WMI_SET_ROAM_MODE */ + WMI_BSS_BIAS_INFO bssBiasInfo; /* WMI_SET_HOST_BIAS */ + WMI_LOWRSSI_SCAN_PARAMS lrScanParams; + } POSTPACK info; + A_UINT8 roamCtrlType ; +} POSTPACK WMI_SET_ROAM_CTRL_CMD; + +/* + * WMI_ENABLE_RM_CMDID + */ +typedef PREPACK struct { + A_BOOL enable_radio_measurements; +} POSTPACK WMI_ENABLE_RM_CMD; + +/* + * WMI_SET_MAX_OFFHOME_DURATION_CMDID + */ +typedef PREPACK struct { + A_UINT8 max_offhome_duration; +} POSTPACK WMI_SET_MAX_OFFHOME_DURATION_CMD; + +typedef PREPACK struct { + A_UINT32 frequency; + A_UINT8 threshold; +} POSTPACK WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD; + +typedef enum { + BT_STREAM_UNDEF = 0, + BT_STREAM_SCO, /* SCO stream */ + BT_STREAM_A2DP, /* A2DP stream */ + BT_STREAM_SCAN, /* BT Discovery or Page */ + BT_STREAM_ESCO, + BT_STREAM_MAX +} BT_STREAM_TYPE; + +typedef enum { + BT_PARAM_SCO = 1, /* SCO stream parameters */ + BT_PARAM_A2DP , + BT_PARAM_ANTENNA_CONFIG, + BT_PARAM_COLOCATED_BT_DEVICE, + BT_PARAM_ACLCOEX, + BT_PARAM_11A_SEPARATE_ANT, + BT_PARAM_MAX +} BT_PARAM_TYPE; + +typedef enum { + BT_PARAM_SCO_PSPOLL_LATENCY_ONE_FOURTH =1, + BT_PARAM_SCO_PSPOLL_LATENCY_HALF, + BT_PARAM_SCO_PSPOLL_LATENCY_THREE_FOURTH, +} BT_PARAMS_SCO_PSPOLL_LATENCY; + +typedef enum { + BT_PARAMS_SCO_STOMP_SCO_NEVER =1, + BT_PARAMS_SCO_STOMP_SCO_ALWAYS, + BT_PARAMS_SCO_STOMP_SCO_IN_LOWRSSI, +} BT_PARAMS_SCO_STOMP_RULES; + +typedef enum { + BT_STATUS_UNDEF = 0, + BT_STATUS_START, + BT_STATUS_STOP, + BT_STATUS_RESUME, + BT_STATUS_SUSPEND, + BT_STATUS_MAX +} BT_STREAM_STATUS; + +typedef PREPACK struct { + A_UINT8 streamType; + A_UINT8 status; +} POSTPACK WMI_SET_BT_STATUS_CMD; + +typedef enum { + BT_ANT_TYPE_UNDEF=0, + BT_ANT_TYPE_DUAL, + BT_ANT_TYPE_SPLITTER, + BT_ANT_TYPE_SWITCH +} BT_ANT_FRONTEND_CONFIG; + +typedef enum { + BT_COLOCATED_DEV_BTS4020=0, + BT_COLCATED_DEV_CSR , + BT_COLOCATED_DEV_VALKYRIE +} BT_COLOCATED_DEV_TYPE; + +#define BT_SCO_ALLOW_CLOSE_RANGE_OPT (1 << 0) +#define BT_SCO_FORCE_AWAKE_OPT (1 << 1) +#define BT_SCO_SET_RSSI_OVERRIDE(flags) ((flags) |= (1 << 2)) +#define BT_SCO_GET_RSSI_OVERRIDE(flags) (((flags) >> 2) & 0x1) +#define BT_SCO_SET_RTS_OVERRIDE(flags) ((flags) |= (1 << 3)) +#define BT_SCO_GET_RTS_OVERRIDE(flags) (((flags) >> 3) & 0x1) +#define BT_SCO_GET_MIN_LOW_RATE_CNT(flags) (((flags) >> 8) & 0xFF) +#define BT_SCO_GET_MAX_LOW_RATE_CNT(flags) (((flags) >> 16) & 0xFF) +#define BT_SCO_SET_MIN_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 8) +#define BT_SCO_SET_MAX_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 16) + +typedef PREPACK struct { + A_UINT32 numScoCyclesForceTrigger; /* Number SCO cycles after which + force a pspoll. default = 10 */ + A_UINT32 dataResponseTimeout; /* Timeout Waiting for Downlink pkt + in response for ps-poll, + default = 10 msecs */ + A_UINT32 stompScoRules; + A_UINT32 scoOptFlags; /* SCO Options Flags : + bits: meaning: + 0 Allow Close Range Optimization + 1 Force awake during close range + 2 If set use host supplied RSSI for OPT + 3 If set use host supplied RTS COUNT for OPT + 4..7 Unused + 8..15 Low Data Rate Min Cnt + 16..23 Low Data Rate Max Cnt + */ + + A_UINT8 stompDutyCyleVal; /* Sco cycles to limit ps-poll queuing + if stomped */ + A_UINT8 stompDutyCyleMaxVal; /*firm ware increases stomp duty cycle + gradually uptill this value on need basis*/ + A_UINT8 psPollLatencyFraction; /* Fraction of idle + period, within which + additional ps-polls + can be queued */ + A_UINT8 noSCOSlots; /* Number of SCO Tx/Rx slots. + HVx, EV3, 2EV3 = 2 */ + A_UINT8 noIdleSlots; /* Number of Bluetooth idle slots between + consecutive SCO Tx/Rx slots + HVx, EV3 = 4 + 2EV3 = 10 */ + A_UINT8 scoOptOffRssi;/*RSSI value below which we go to ps poll*/ + A_UINT8 scoOptOnRssi; /*RSSI value above which we reenter opt mode*/ + A_UINT8 scoOptRtsCount; +} POSTPACK BT_PARAMS_SCO; + +#define BT_A2DP_ALLOW_CLOSE_RANGE_OPT (1 << 0) +#define BT_A2DP_FORCE_AWAKE_OPT (1 << 1) +#define BT_A2DP_SET_RSSI_OVERRIDE(flags) ((flags) |= (1 << 2)) +#define BT_A2DP_GET_RSSI_OVERRIDE(flags) (((flags) >> 2) & 0x1) +#define BT_A2DP_SET_RTS_OVERRIDE(flags) ((flags) |= (1 << 3)) +#define BT_A2DP_GET_RTS_OVERRIDE(flags) (((flags) >> 3) & 0x1) +#define BT_A2DP_GET_MIN_LOW_RATE_CNT(flags) (((flags) >> 8) & 0xFF) +#define BT_A2DP_GET_MAX_LOW_RATE_CNT(flags) (((flags) >> 16) & 0xFF) +#define BT_A2DP_SET_MIN_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 8) +#define BT_A2DP_SET_MAX_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 16) + +typedef PREPACK struct { + A_UINT32 a2dpWlanUsageLimit; /* MAX time firmware uses the medium for + wlan, after it identifies the idle time + default (30 msecs) */ + A_UINT32 a2dpBurstCntMin; /* Minimum number of bluetooth data frames + to replenish Wlan Usage limit (default 3) */ + A_UINT32 a2dpDataRespTimeout; + A_UINT32 a2dpOptFlags; /* A2DP Option flags: + bits: meaning: + 0 Allow Close Range Optimization + 1 Force awake during close range + 2 If set use host supplied RSSI for OPT + 3 If set use host supplied RTS COUNT for OPT + 4..7 Unused + 8..15 Low Data Rate Min Cnt + 16..23 Low Data Rate Max Cnt + */ + A_UINT8 isCoLocatedBtRoleMaster; + A_UINT8 a2dpOptOffRssi;/*RSSI value below which we go to ps poll*/ + A_UINT8 a2dpOptOnRssi; /*RSSI value above which we reenter opt mode*/ + A_UINT8 a2dpOptRtsCount; +}POSTPACK BT_PARAMS_A2DP; + +/* During BT ftp/ BT OPP or any another data based acl profile on bluetooth + (non a2dp).*/ +typedef PREPACK struct { + A_UINT32 aclWlanMediumUsageTime; /* Wlan usage time during Acl (non-a2dp) + coexistence (default 30 msecs) */ + A_UINT32 aclBtMediumUsageTime; /* Bt usage time during acl coexistence + (default 30 msecs)*/ + A_UINT32 aclDataRespTimeout; + A_UINT32 aclDetectTimeout; /* ACL coexistence enabled if we get + 10 Pkts in X msec(default 100 msecs) */ + A_UINT32 aclmaxPktCnt; /* No of ACL pkts to receive before + enabling ACL coex */ + +}POSTPACK BT_PARAMS_ACLCOEX; + +typedef PREPACK struct { + A_UINT32 mode; + A_UINT32 scoWghts; + A_UINT32 a2dpWghts; + A_UINT32 genWghts; + A_UINT32 mode2; + A_UINT8 setVal; +} POSTPACK BT_COEX_REGS; + +typedef enum { + WLAN_PROTECT_POLICY = 1, + WLAN_COEX_CTRL_FLAGS +} BT_PARAMS_MISC_TYPE; + +typedef enum { + WLAN_PROTECT_PER_STREAM = 0x01, /* default */ + WLAN_PROTECT_ANY_TX = 0x02 +} WLAN_PROTECT_FLAGS; + + +#define WLAN_DISABLE_COEX_IN_DISCONNECT 0x01 /* default */ +#define WLAN_KEEP_COEX_IN_DISCONNECT 0x02 +#define WLAN_STOMPBT_IN_DISCONNECT 0x04 + +#define WLAN_DISABLE_COEX_IN_ROAM 0x10 /* default */ +#define WLAN_KEEP_COEX_IN_ROAM 0x20 +#define WLAN_STOMPBT_IN_ROAM 0x40 + +#define WLAN_DISABLE_COEX_IN_SCAN 0x100 /* default */ +#define WLAN_KEEP_COEX_IN_SCAN 0x200 +#define WLAN_STOMPBT_IN_SCAN 0x400 + +#define WLAN_DISABLE_COEX_BT_OFF 0x1000 /* default */ +#define WLAN_KEEP_COEX_BT_OFF 0x2000 +#define WLAN_STOMPBT_BT_OFF 0x4000 + +typedef PREPACK struct { + A_UINT32 period; + A_UINT32 dutycycle; + A_UINT8 stompbt; + A_UINT8 policy; +} POSTPACK WLAN_PROTECT_POLICY_TYPE; + +typedef PREPACK struct { + PREPACK union { + WLAN_PROTECT_POLICY_TYPE protectParams; + A_UINT16 configCtrlFlags; + } POSTPACK info; + A_UINT8 paramType; +} POSTPACK BT_PARAMS_MISC; + +typedef PREPACK struct { + PREPACK union { + BT_PARAMS_SCO scoParams; + BT_PARAMS_A2DP a2dpParams; + BT_PARAMS_ACLCOEX aclCoexParams; + A_UINT8 antType; /* 0 -Disabled (default) + 1 - BT_ANT_TYPE_DUAL + 2 - BT_ANT_TYPE_SPLITTER + 3 - BT_ANT_TYPE_SWITCH */ + A_UINT8 coLocatedBtDev; /* 0 - BT_COLOCATED_DEV_BTS4020 (default) + 1 - BT_COLCATED_DEV_CSR + 2 - BT_COLOCATED_DEV_VALKYRIe + */ + } POSTPACK info; + A_UINT8 paramType ; +} POSTPACK WMI_SET_BT_PARAMS_CMD; + +typedef enum { + DISCONN_EVT_IN_RECONN = 0, /* default */ + NO_DISCONN_EVT_IN_RECONN +} TARGET_EVENT_REPORT_CONFIG; + +typedef PREPACK struct { + A_UINT32 evtConfig; +} POSTPACK WMI_SET_TARGET_EVENT_REPORT_CMD; + + +/* + * Command Replies + */ + +/* + * WMI_GET_CHANNEL_LIST_CMDID reply + */ +typedef PREPACK struct { + A_UINT8 reserved1; + A_UINT8 numChannels; /* number of channels in reply */ + A_UINT16 channelList[1]; /* channel in Mhz */ +} POSTPACK WMI_CHANNEL_LIST_REPLY; + +typedef enum { + A_SUCCEEDED = A_OK, + A_FAILED_DELETE_STREAM_DOESNOT_EXIST=250, + A_SUCCEEDED_MODIFY_STREAM=251, + A_FAILED_INVALID_STREAM = 252, + A_FAILED_MAX_THINSTREAMS = 253, + A_FAILED_CREATE_REMOVE_PSTREAM_FIRST = 254, +} PSTREAM_REPLY_STATUS; + +typedef PREPACK struct { + A_UINT8 status; /* PSTREAM_REPLY_STATUS */ + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficClass; + A_UINT8 trafficDirection; /* DIR_TYPE */ +} POSTPACK WMI_CRE_PRIORITY_STREAM_REPLY; + +typedef PREPACK struct { + A_UINT8 status; /* PSTREAM_REPLY_STATUS */ + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficDirection; /* DIR_TYPE */ + A_UINT8 trafficClass; +} POSTPACK WMI_DEL_PRIORITY_STREAM_REPLY; + +/* + * List of Events (target to host) + */ +typedef enum { + WMI_READY_EVENTID = 0x1001, + WMI_CONNECT_EVENTID, + WMI_DISCONNECT_EVENTID, + WMI_BSSINFO_EVENTID, + WMI_CMDERROR_EVENTID, + WMI_REGDOMAIN_EVENTID, + WMI_PSTREAM_TIMEOUT_EVENTID, + WMI_NEIGHBOR_REPORT_EVENTID, + WMI_TKIP_MICERR_EVENTID, + WMI_SCAN_COMPLETE_EVENTID, /* 0x100a */ + WMI_REPORT_STATISTICS_EVENTID, + WMI_RSSI_THRESHOLD_EVENTID, + WMI_ERROR_REPORT_EVENTID, + WMI_OPT_RX_FRAME_EVENTID, + WMI_REPORT_ROAM_TBL_EVENTID, + WMI_EXTENSION_EVENTID, + WMI_CAC_EVENTID, + WMI_SNR_THRESHOLD_EVENTID, + WMI_LQ_THRESHOLD_EVENTID, + WMI_TX_RETRY_ERR_EVENTID, /* 0x1014 */ + WMI_REPORT_ROAM_DATA_EVENTID, + WMI_TEST_EVENTID, + WMI_APLIST_EVENTID, + WMI_GET_WOW_LIST_EVENTID, + WMI_GET_PMKID_LIST_EVENTID, + WMI_CHANNEL_CHANGE_EVENTID, + WMI_PEER_NODE_EVENTID, + WMI_PSPOLL_EVENTID, + WMI_DTIMEXPIRY_EVENTID, + WMI_WLAN_VERSION_EVENTID, + WMI_SET_PARAMS_REPLY_EVENTID +} WMI_EVENT_ID; + +typedef enum { + WMI_11A_CAPABILITY = 1, + WMI_11G_CAPABILITY = 2, + WMI_11AG_CAPABILITY = 3, +} WMI_PHY_CAPABILITY; + +typedef PREPACK struct { + A_UINT8 macaddr[ATH_MAC_LEN]; + A_UINT8 phyCapability; /* WMI_PHY_CAPABILITY */ +} POSTPACK WMI_READY_EVENT_1; + +typedef PREPACK struct { + A_UINT32 version; + A_UINT8 macaddr[ATH_MAC_LEN]; + A_UINT8 phyCapability; /* WMI_PHY_CAPABILITY */ +} POSTPACK WMI_READY_EVENT_2; + +#if defined(ATH_TARGET) +#ifdef AR6002_REV2 +#define WMI_READY_EVENT WMI_READY_EVENT_1 /* AR6002_REV2 target code */ +#else +#define WMI_READY_EVENT WMI_READY_EVENT_2 /* AR6002_REV4 and AR6001 */ +#endif +#else +#define WMI_READY_EVENT WMI_READY_EVENT_2 /* host code */ +#endif + + +/* + * Connect Event + */ +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT16 listenInterval; + A_UINT16 beaconInterval; + A_UINT32 networkType; + A_UINT8 beaconIeLen; + A_UINT8 assocReqLen; + A_UINT8 assocRespLen; + A_UINT8 assocInfo[1]; +} POSTPACK WMI_CONNECT_EVENT; + +/* + * Disconnect Event + */ +typedef enum { + NO_NETWORK_AVAIL = 0x01, + LOST_LINK = 0x02, /* bmiss */ + DISCONNECT_CMD = 0x03, + BSS_DISCONNECTED = 0x04, + AUTH_FAILED = 0x05, + ASSOC_FAILED = 0x06, + NO_RESOURCES_AVAIL = 0x07, + CSERV_DISCONNECT = 0x08, + INVALID_PROFILE = 0x0a, + DOT11H_CHANNEL_SWITCH = 0x0b, + PROFILE_MISMATCH = 0x0c, + PYXIS_VIRT_ADHOC_DISC = 0x0d, +} WMI_DISCONNECT_REASON; + +typedef PREPACK struct { + A_UINT16 protocolReasonStatus; /* reason code, see 802.11 spec. */ + A_UINT8 bssid[ATH_MAC_LEN]; /* set if known */ + A_UINT8 disconnectReason ; /* see WMI_DISCONNECT_REASON */ + A_UINT8 assocRespLen; + A_UINT8 assocInfo[1]; +} POSTPACK WMI_DISCONNECT_EVENT; + +/* + * BSS Info Event. + * Mechanism used to inform host of the presence and characteristic of + * wireless networks present. Consists of bss info header followed by + * the beacon or probe-response frame body. The 802.11 header is not included. + */ +typedef enum { + BEACON_FTYPE = 0x1, + PROBERESP_FTYPE, + ACTION_MGMT_FTYPE, + PROBEREQ_FTYPE, +} WMI_BI_FTYPE; + +enum { + BSS_ELEMID_CHANSWITCH = 0x01, + BSS_ELEMID_ATHEROS = 0x02, +}; + +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 frameType; /* see WMI_BI_FTYPE */ + A_UINT8 snr; + A_INT16 rssi; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT32 ieMask; +} POSTPACK WMI_BSS_INFO_HDR; + +/* + * Command Error Event + */ +typedef enum { + INVALID_PARAM = 0x01, + ILLEGAL_STATE = 0x02, + INTERNAL_ERROR = 0x03, +} WMI_ERROR_CODE; + +typedef PREPACK struct { + A_UINT16 commandId; + A_UINT8 errorCode; +} POSTPACK WMI_CMD_ERROR_EVENT; + +/* + * New Regulatory Domain Event + */ +typedef PREPACK struct { + A_UINT32 regDomain; +} POSTPACK WMI_REG_DOMAIN_EVENT; + +typedef PREPACK struct { + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficDirection; + A_UINT8 trafficClass; +} POSTPACK WMI_PSTREAM_TIMEOUT_EVENT; + +/* + * The WMI_NEIGHBOR_REPORT Event is generated by the target to inform + * the host of BSS's it has found that matches the current profile. + * It can be used by the host to cache PMKs and/to initiate pre-authentication + * if the BSS supports it. The first bssid is always the current associated + * BSS. + * The bssid and bssFlags information repeats according to the number + * or APs reported. + */ +typedef enum { + WMI_DEFAULT_BSS_FLAGS = 0x00, + WMI_PREAUTH_CAPABLE_BSS = 0x01, + WMI_PMKID_VALID_BSS = 0x02, +} WMI_BSS_FLAGS; + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT8 bssFlags; /* see WMI_BSS_FLAGS */ +} POSTPACK WMI_NEIGHBOR_INFO; + +typedef PREPACK struct { + A_INT8 numberOfAps; + WMI_NEIGHBOR_INFO neighbor[1]; +} POSTPACK WMI_NEIGHBOR_REPORT_EVENT; + +/* + * TKIP MIC Error Event + */ +typedef PREPACK struct { + A_UINT8 keyid; + A_UINT8 ismcast; +} POSTPACK WMI_TKIP_MICERR_EVENT; + +/* + * WMI_SCAN_COMPLETE_EVENTID - no parameters (old), staus parameter (new) + */ +typedef PREPACK struct { + A_INT32 status; +} POSTPACK WMI_SCAN_COMPLETE_EVENT; + +#define MAX_OPT_DATA_LEN 1400 + +/* + * WMI_SET_ADHOC_BSSID_CMDID + */ +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_SET_ADHOC_BSSID_CMD; + +/* + * WMI_SET_OPT_MODE_CMDID + */ +typedef enum { + SPECIAL_OFF, + SPECIAL_ON, + PYXIS_ADHOC_ON, + PYXIS_ADHOC_OFF, +} OPT_MODE_TYPE; + +typedef PREPACK struct { + A_UINT8 optMode; +} POSTPACK WMI_SET_OPT_MODE_CMD; + +/* + * WMI_TX_OPT_FRAME_CMDID + */ +typedef enum { + OPT_PROBE_REQ = 0x01, + OPT_PROBE_RESP = 0x02, + OPT_CPPP_START = 0x03, + OPT_CPPP_STOP = 0x04, +} WMI_OPT_FTYPE; + +typedef PREPACK struct { + A_UINT16 optIEDataLen; + A_UINT8 frmType; + A_UINT8 dstAddr[ATH_MAC_LEN]; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT8 reserved; /* For alignment */ + A_UINT8 optIEData[1]; +} POSTPACK WMI_OPT_TX_FRAME_CMD; + +/* + * Special frame receive Event. + * Mechanism used to inform host of the receiption of the special frames. + * Consists of special frame info header followed by special frame body. + * The 802.11 header is not included. + */ +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 frameType; /* see WMI_OPT_FTYPE */ + A_INT8 snr; + A_UINT8 srcAddr[ATH_MAC_LEN]; + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_OPT_RX_INFO_HDR; + +/* + * Reporting statistics. + */ +typedef PREPACK struct { + A_UINT32 tx_packets; + A_UINT32 tx_bytes; + A_UINT32 tx_unicast_pkts; + A_UINT32 tx_unicast_bytes; + A_UINT32 tx_multicast_pkts; + A_UINT32 tx_multicast_bytes; + A_UINT32 tx_broadcast_pkts; + A_UINT32 tx_broadcast_bytes; + A_UINT32 tx_rts_success_cnt; + A_UINT32 tx_packet_per_ac[4]; + A_UINT32 tx_errors_per_ac[4]; + + A_UINT32 tx_errors; + A_UINT32 tx_failed_cnt; + A_UINT32 tx_retry_cnt; + A_UINT32 tx_mult_retry_cnt; + A_UINT32 tx_rts_fail_cnt; + A_INT32 tx_unicast_rate; +}POSTPACK tx_stats_t; + +typedef PREPACK struct { + A_UINT32 rx_packets; + A_UINT32 rx_bytes; + A_UINT32 rx_unicast_pkts; + A_UINT32 rx_unicast_bytes; + A_UINT32 rx_multicast_pkts; + A_UINT32 rx_multicast_bytes; + A_UINT32 rx_broadcast_pkts; + A_UINT32 rx_broadcast_bytes; + A_UINT32 rx_fragment_pkt; + + A_UINT32 rx_errors; + A_UINT32 rx_crcerr; + A_UINT32 rx_key_cache_miss; + A_UINT32 rx_decrypt_err; + A_UINT32 rx_duplicate_frames; + A_INT32 rx_unicast_rate; +}POSTPACK rx_stats_t; + +typedef PREPACK struct { + A_UINT32 tkip_local_mic_failure; + A_UINT32 tkip_counter_measures_invoked; + A_UINT32 tkip_replays; + A_UINT32 tkip_format_errors; + A_UINT32 ccmp_format_errors; + A_UINT32 ccmp_replays; +}POSTPACK tkip_ccmp_stats_t; + +typedef PREPACK struct { + A_UINT32 power_save_failure_cnt; +}POSTPACK pm_stats_t; + +typedef PREPACK struct { + A_UINT32 cs_bmiss_cnt; + A_UINT32 cs_lowRssi_cnt; + A_UINT16 cs_connect_cnt; + A_UINT16 cs_disconnect_cnt; + A_INT16 cs_aveBeacon_rssi; + A_UINT16 cs_roam_count; + A_INT16 cs_rssi; + A_UINT8 cs_snr; + A_UINT8 cs_aveBeacon_snr; + A_UINT8 cs_lastRoam_msec; +} POSTPACK cserv_stats_t; + +typedef PREPACK struct { + tx_stats_t tx_stats; + rx_stats_t rx_stats; + tkip_ccmp_stats_t tkipCcmpStats; +}POSTPACK wlan_net_stats_t; + +typedef PREPACK struct { + A_UINT32 arp_received; + A_UINT32 arp_matched; + A_UINT32 arp_replied; +} POSTPACK arp_stats_t; + +typedef PREPACK struct { + A_UINT32 wow_num_pkts_dropped; + A_UINT16 wow_num_events_discarded; + A_UINT8 wow_num_host_pkt_wakeups; + A_UINT8 wow_num_host_event_wakeups; +} POSTPACK wlan_wow_stats_t; + +typedef PREPACK struct { + A_UINT32 lqVal; + A_INT32 noise_floor_calibation; + pm_stats_t pmStats; + wlan_net_stats_t txrxStats; + wlan_wow_stats_t wowStats; + arp_stats_t arpStats; + cserv_stats_t cservStats; +} POSTPACK WMI_TARGET_STATS; + +/* + * WMI_RSSI_THRESHOLD_EVENTID. + * Indicate the RSSI events to host. Events are indicated when we breach a + * thresold value. + */ +typedef enum{ + WMI_RSSI_THRESHOLD1_ABOVE = 0, + WMI_RSSI_THRESHOLD2_ABOVE, + WMI_RSSI_THRESHOLD3_ABOVE, + WMI_RSSI_THRESHOLD4_ABOVE, + WMI_RSSI_THRESHOLD5_ABOVE, + WMI_RSSI_THRESHOLD6_ABOVE, + WMI_RSSI_THRESHOLD1_BELOW, + WMI_RSSI_THRESHOLD2_BELOW, + WMI_RSSI_THRESHOLD3_BELOW, + WMI_RSSI_THRESHOLD4_BELOW, + WMI_RSSI_THRESHOLD5_BELOW, + WMI_RSSI_THRESHOLD6_BELOW +}WMI_RSSI_THRESHOLD_VAL; + +typedef PREPACK struct { + A_INT16 rssi; + A_UINT8 range; +}POSTPACK WMI_RSSI_THRESHOLD_EVENT; + +/* + * WMI_ERROR_REPORT_EVENTID + */ +typedef enum{ + WMI_TARGET_PM_ERR_FAIL = 0x00000001, + WMI_TARGET_KEY_NOT_FOUND = 0x00000002, + WMI_TARGET_DECRYPTION_ERR = 0x00000004, + WMI_TARGET_BMISS = 0x00000008, + WMI_PSDISABLE_NODE_JOIN = 0x00000010, + WMI_TARGET_COM_ERR = 0x00000020, + WMI_TARGET_FATAL_ERR = 0x00000040 +} WMI_TARGET_ERROR_VAL; + +typedef PREPACK struct { + A_UINT32 errorVal; +}POSTPACK WMI_TARGET_ERROR_REPORT_EVENT; + +typedef PREPACK struct { + A_UINT8 retrys; +}POSTPACK WMI_TX_RETRY_ERR_EVENT; + +typedef enum{ + WMI_SNR_THRESHOLD1_ABOVE = 1, + WMI_SNR_THRESHOLD1_BELOW, + WMI_SNR_THRESHOLD2_ABOVE, + WMI_SNR_THRESHOLD2_BELOW, + WMI_SNR_THRESHOLD3_ABOVE, + WMI_SNR_THRESHOLD3_BELOW, + WMI_SNR_THRESHOLD4_ABOVE, + WMI_SNR_THRESHOLD4_BELOW +} WMI_SNR_THRESHOLD_VAL; + +typedef PREPACK struct { + A_UINT8 range; /* WMI_SNR_THRESHOLD_VAL */ + A_UINT8 snr; +}POSTPACK WMI_SNR_THRESHOLD_EVENT; + +typedef enum{ + WMI_LQ_THRESHOLD1_ABOVE = 1, + WMI_LQ_THRESHOLD1_BELOW, + WMI_LQ_THRESHOLD2_ABOVE, + WMI_LQ_THRESHOLD2_BELOW, + WMI_LQ_THRESHOLD3_ABOVE, + WMI_LQ_THRESHOLD3_BELOW, + WMI_LQ_THRESHOLD4_ABOVE, + WMI_LQ_THRESHOLD4_BELOW +} WMI_LQ_THRESHOLD_VAL; + +typedef PREPACK struct { + A_INT32 lq; + A_UINT8 range; /* WMI_LQ_THRESHOLD_VAL */ +}POSTPACK WMI_LQ_THRESHOLD_EVENT; +/* + * WMI_REPORT_ROAM_TBL_EVENTID + */ +#define MAX_ROAM_TBL_CAND 5 + +typedef PREPACK struct { + A_INT32 roam_util; + A_UINT8 bssid[ATH_MAC_LEN]; + A_INT8 rssi; + A_INT8 rssidt; + A_INT8 last_rssi; + A_INT8 util; + A_INT8 bias; + A_UINT8 reserved; /* For alignment */ +} POSTPACK WMI_BSS_ROAM_INFO; + + +typedef PREPACK struct { + A_UINT16 roamMode; + A_UINT16 numEntries; + WMI_BSS_ROAM_INFO bssRoamInfo[1]; +} POSTPACK WMI_TARGET_ROAM_TBL; + +/* + * WMI_CAC_EVENTID + */ +typedef enum { + CAC_INDICATION_ADMISSION = 0x00, + CAC_INDICATION_ADMISSION_RESP = 0x01, + CAC_INDICATION_DELETE = 0x02, + CAC_INDICATION_NO_RESP = 0x03, +}CAC_INDICATION; + +#define WMM_TSPEC_IE_LEN 63 + +typedef PREPACK struct { + A_UINT8 ac; + A_UINT8 cac_indication; + A_UINT8 statusCode; + A_UINT8 tspecSuggestion[WMM_TSPEC_IE_LEN]; +}POSTPACK WMI_CAC_EVENT; + +/* + * WMI_APLIST_EVENTID + */ + +typedef enum { + APLIST_VER1 = 1, +} APLIST_VER; + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT16 channel; +} POSTPACK WMI_AP_INFO_V1; + +typedef PREPACK union { + WMI_AP_INFO_V1 apInfoV1; +} POSTPACK WMI_AP_INFO; + +typedef PREPACK struct { + A_UINT8 apListVer; + A_UINT8 numAP; + WMI_AP_INFO apList[1]; +} POSTPACK WMI_APLIST_EVENT; + +/* + * developer commands + */ + +/* + * WMI_SET_BITRATE_CMDID + * + * Get bit rate cmd uses same definition as set bit rate cmd + */ +typedef enum { + RATE_AUTO = -1, + RATE_1Mb = 0, + RATE_2Mb = 1, + RATE_5_5Mb = 2, + RATE_11Mb = 3, + RATE_6Mb = 4, + RATE_9Mb = 5, + RATE_12Mb = 6, + RATE_18Mb = 7, + RATE_24Mb = 8, + RATE_36Mb = 9, + RATE_48Mb = 10, + RATE_54Mb = 11, +} WMI_BIT_RATE; + +typedef PREPACK struct { + A_INT8 rateIndex; /* see WMI_BIT_RATE */ + A_INT8 mgmtRateIndex; + A_INT8 ctlRateIndex; +} POSTPACK WMI_BIT_RATE_CMD; + + +typedef PREPACK struct { + A_INT8 rateIndex; /* see WMI_BIT_RATE */ +} POSTPACK WMI_BIT_RATE_REPLY; + + +/* + * WMI_SET_FIXRATES_CMDID + * + * Get fix rates cmd uses same definition as set fix rates cmd + */ +typedef enum { + FIX_RATE_1Mb = 0x1, + FIX_RATE_2Mb = 0x2, + FIX_RATE_5_5Mb = 0x4, + FIX_RATE_11Mb = 0x8, + FIX_RATE_6Mb = 0x10, + FIX_RATE_9Mb = 0x20, + FIX_RATE_12Mb = 0x40, + FIX_RATE_18Mb = 0x80, + FIX_RATE_24Mb = 0x100, + FIX_RATE_36Mb = 0x200, + FIX_RATE_48Mb = 0x400, + FIX_RATE_54Mb = 0x800, +} WMI_FIX_RATES_MASK; + +typedef PREPACK struct { + A_UINT16 fixRateMask; /* see WMI_BIT_RATE */ +} POSTPACK WMI_FIX_RATES_CMD, WMI_FIX_RATES_REPLY; + +typedef PREPACK struct { + A_UINT8 bEnableMask; + A_UINT8 frameType; /*type and subtype*/ + A_UINT16 frameRateMask; /* see WMI_BIT_RATE */ +} POSTPACK WMI_FRAME_RATES_CMD, WMI_FRAME_RATES_REPLY; + +/* + * WMI_SET_RECONNECT_AUTH_MODE_CMDID + * + * Set authentication mode + */ +typedef enum { + RECONN_DO_AUTH = 0x00, + RECONN_NOT_AUTH = 0x01 +} WMI_AUTH_MODE; + +typedef PREPACK struct { + A_UINT8 mode; +} POSTPACK WMI_SET_AUTH_MODE_CMD; + +/* + * WMI_SET_REASSOC_MODE_CMDID + * + * Set authentication mode + */ +typedef enum { + REASSOC_DO_DISASSOC = 0x00, + REASSOC_DONOT_DISASSOC = 0x01 +} WMI_REASSOC_MODE; + +typedef PREPACK struct { + A_UINT8 mode; +}POSTPACK WMI_SET_REASSOC_MODE_CMD; + +typedef enum { + ROAM_DATA_TIME = 1, /* Get The Roam Time Data */ +} ROAM_DATA_TYPE; + +typedef PREPACK struct { + A_UINT32 disassoc_time; + A_UINT32 no_txrx_time; + A_UINT32 assoc_time; + A_UINT32 allow_txrx_time; + A_UINT32 last_data_txrx_time; + A_UINT32 first_data_txrx_time; + A_UINT8 disassoc_bssid[ATH_MAC_LEN]; + A_INT8 disassoc_bss_rssi; + A_UINT8 assoc_bssid[ATH_MAC_LEN]; + A_INT8 assoc_bss_rssi; +} POSTPACK WMI_TARGET_ROAM_TIME; + +typedef PREPACK struct { + PREPACK union { + WMI_TARGET_ROAM_TIME roamTime; + } POSTPACK u; + A_UINT8 roamDataType ; +} POSTPACK WMI_TARGET_ROAM_DATA; + +typedef enum { + WMI_WMM_DISABLED = 0, + WMI_WMM_ENABLED +} WMI_WMM_STATUS; + +typedef PREPACK struct { + A_UINT8 status; +}POSTPACK WMI_SET_WMM_CMD; + +typedef enum { + WMI_TXOP_DISABLED = 0, + WMI_TXOP_ENABLED +} WMI_TXOP_CFG; + +typedef PREPACK struct { + A_UINT8 txopEnable; +}POSTPACK WMI_SET_WMM_TXOP_CMD; + +typedef PREPACK struct { + A_UINT8 keepaliveInterval; +} POSTPACK WMI_SET_KEEPALIVE_CMD; + +typedef PREPACK struct { + A_BOOL configured; + A_UINT8 keepaliveInterval; +} POSTPACK WMI_GET_KEEPALIVE_CMD; + +/* + * Add Application specified IE to a management frame + */ +#define WMI_MAX_IE_LEN 255 + +typedef PREPACK struct { + A_UINT8 mgmtFrmType; /* one of WMI_MGMT_FRAME_TYPE */ + A_UINT8 ieLen; /* Length of the IE that should be added to the MGMT frame */ + A_UINT8 ieInfo[1]; +} POSTPACK WMI_SET_APPIE_CMD; + +/* + * Notify the WSC registration status to the target + */ +#define WSC_REG_ACTIVE 1 +#define WSC_REG_INACTIVE 0 +/* Generic Hal Interface for setting hal paramters. */ +/* Add new Set HAL Param cmdIds here for newer params */ +typedef enum { + WHAL_SETCABTO_CMDID = 1, +}WHAL_CMDID; + +typedef PREPACK struct { + A_UINT8 cabTimeOut; +} POSTPACK WHAL_SETCABTO_PARAM; + +typedef PREPACK struct { + A_UINT8 whalCmdId; + A_UINT8 data[1]; +} POSTPACK WHAL_PARAMCMD; + + +#define WOW_MAX_FILTER_LISTS 1 /*4*/ +#define WOW_MAX_FILTERS_PER_LIST 4 +#define WOW_PATTERN_SIZE 64 +#define WOW_MASK_SIZE 64 + +#define MAC_MAX_FILTERS_PER_LIST 4 + +typedef PREPACK struct { + A_UINT8 wow_valid_filter; + A_UINT8 wow_filter_id; + A_UINT8 wow_filter_size; + A_UINT8 wow_filter_offset; + A_UINT8 wow_filter_mask[WOW_MASK_SIZE]; + A_UINT8 wow_filter_pattern[WOW_PATTERN_SIZE]; +} POSTPACK WOW_FILTER; + + +typedef PREPACK struct { + A_UINT8 wow_valid_list; + A_UINT8 wow_list_id; + A_UINT8 wow_num_filters; + A_UINT8 wow_total_list_size; + WOW_FILTER list[WOW_MAX_FILTERS_PER_LIST]; +} POSTPACK WOW_FILTER_LIST; + +typedef PREPACK struct { + A_UINT8 valid_filter; + A_UINT8 mac_addr[ATH_MAC_LEN]; +} POSTPACK MAC_FILTER; + + +typedef PREPACK struct { + A_UINT8 total_list_size; + MAC_FILTER list[MAC_MAX_FILTERS_PER_LIST]; +} POSTPACK MAC_FILTER_LIST; + +#define MAX_IP_ADDRS 2 +typedef PREPACK struct { + A_UINT32 ips[MAX_IP_ADDRS]; /* IP in Network Byte Order */ +} POSTPACK WMI_SET_IP_CMD; + +typedef PREPACK struct { + A_BOOL awake; + A_BOOL asleep; +} POSTPACK WMI_SET_HOST_SLEEP_MODE_CMD; + +typedef PREPACK struct { + A_BOOL enable_wow; +} POSTPACK WMI_SET_WOW_MODE_CMD; + +typedef PREPACK struct { + A_UINT8 filter_list_id; +} POSTPACK WMI_GET_WOW_LIST_CMD; + +/* + * WMI_GET_WOW_LIST_CMD reply + */ +typedef PREPACK struct { + A_UINT8 num_filters; /* number of patterns in reply */ + A_UINT8 this_filter_num; /* this is filter # x of total num_filters */ + A_UINT8 wow_mode; + A_UINT8 host_mode; + WOW_FILTER wow_filters[1]; +} POSTPACK WMI_GET_WOW_LIST_REPLY; + +typedef PREPACK struct { + A_UINT8 filter_list_id; + A_UINT8 filter_size; + A_UINT8 filter_offset; + A_UINT8 filter[1]; +} POSTPACK WMI_ADD_WOW_PATTERN_CMD; + +typedef PREPACK struct { + A_UINT16 filter_list_id; + A_UINT16 filter_id; +} POSTPACK WMI_DEL_WOW_PATTERN_CMD; + +typedef PREPACK struct { + A_UINT8 macaddr[ATH_MAC_LEN]; +} POSTPACK WMI_SET_MAC_ADDRESS_CMD; + +/* + * WMI_SET_AKMP_PARAMS_CMD + */ + +#define WMI_AKMP_MULTI_PMKID_EN 0x000001 + +typedef PREPACK struct { + A_UINT32 akmpInfo; +} POSTPACK WMI_SET_AKMP_PARAMS_CMD; + +typedef PREPACK struct { + A_UINT8 pmkid[WMI_PMKID_LEN]; +} POSTPACK WMI_PMKID; + +/* + * WMI_SET_PMKID_LIST_CMD + */ +#define WMI_MAX_PMKID_CACHE 8 + +typedef PREPACK struct { + A_UINT32 numPMKID; + WMI_PMKID pmkidList[WMI_MAX_PMKID_CACHE]; +} POSTPACK WMI_SET_PMKID_LIST_CMD; + +/* + * WMI_GET_PMKID_LIST_CMD Reply + * Following the Number of PMKIDs is the list of PMKIDs + */ +typedef PREPACK struct { + A_UINT32 numPMKID; + A_UINT8 bssidList[ATH_MAC_LEN][1]; + WMI_PMKID pmkidList[1]; +} POSTPACK WMI_PMKID_LIST_REPLY; + +typedef PREPACK struct { + A_UINT16 oldChannel; + A_UINT32 newChannel; +} POSTPACK WMI_CHANNEL_CHANGE_EVENT; + +typedef PREPACK struct { + A_UINT32 version; +} POSTPACK WMI_WLAN_VERSION_EVENT; + +#define PEER_NODE_JOIN_EVENT 0x00 +#define PEER_NODE_LEAVE_EVENT 0x01 +typedef PREPACK struct { + A_UINT8 eventCode; + A_UINT8 peerMacAddr[ATH_MAC_LEN]; +} POSTPACK WMI_PEER_NODE_EVENT; + +#define IEEE80211_FRAME_TYPE_MGT 0x00 +#define IEEE80211_FRAME_TYPE_CTL 0x04 + + +typedef enum { + WMI_PYXIS_GEN_PARAMS = 0, + WMI_PYXIS_DSCVR_PARAMS, + WMI_PYXIS_SET_TX_MODE, +} WMI_PYXIS_CONFIG_TYPE; + +typedef PREPACK struct { + A_UINT16 pyxisConfigType; // One of WMI_PYXIS_CONFIG_TYPE + A_UINT16 pyxisConfigLen; // Length in Bytes of Information that follows +} POSTPACK WMI_PYXIS_CONFIG_HDR; + +typedef PREPACK struct { + WMI_PYXIS_CONFIG_HDR hdr; + A_UINT32 dscvrWindow; + A_UINT32 dscvrInterval; + A_UINT32 dscvrLife; + A_UINT32 probeInterval; + A_UINT32 probePeriod; + A_UINT16 dscvrChannel; +} POSTPACK WMI_PYXIS_DSCVR_CONFIG; + +typedef PREPACK struct { + WMI_PYXIS_CONFIG_HDR hdr; + A_UINT32 dataWindowSizeMin; + A_UINT32 dataWindowSizeMax; + A_UINT8 maxJoiners; +} POSTPACK WMI_PYXIS_GEN_CONFIG; + +typedef PREPACK struct { + WMI_PYXIS_CONFIG_HDR hdr; + A_BOOL mode; +} POSTPACK WMI_PYXIS_TX_MODE; + +typedef enum { + WMI_PYXIS_DISC_PEER = 0, + WMI_PYXIS_JOIN_PEER, +} WMI_PYXIS_CMD_TYPE; + +typedef PREPACK struct { + A_UINT16 pyxisCmd; + A_UINT16 pyxisCmdLen; // Length following this header +} POSTPACK WMI_PYXIS_CMD_HDR; + +typedef PREPACK struct { + WMI_PYXIS_CMD_HDR hdr; + A_UINT8 peerMacAddr[ATH_MAC_LEN]; +} POSTPACK WMI_PYXIS_DISCONNECT_CMD; + +typedef PREPACK struct { + WMI_PYXIS_CMD_HDR hdr; + A_UINT32 ctrl_flags; /* One of the Bits determines if it + * is Virt Adhoc/the device is to + * join a BSS */ + A_UINT16 channel; /* Data Channel */ + A_UINT8 networkType; /* network type */ + A_UINT8 dot11AuthMode; /* OPEN_AUTH */ + A_UINT8 authMode; /* NONE_AUTH */ + A_UINT8 pairwiseCryptoType; /* One of NONE_CRYPT, AES_CRYPT */ + A_UINT8 pairwiseCryptoLen; /* 0 since ADD_KEY passes the length */ + A_UINT8 groupCryptoType; /* One of NONE_CRYPT, AES_CRYPT */ + A_UINT8 groupCryptoLen; /* 0 since ADD_KEY passes the length */ + A_UINT8 peerMacAddr[ATH_MAC_LEN]; /* BSSID of peer network*/ + A_UINT8 nwBSSID[ATH_MAC_LEN]; /* BSSID of the Pyxis Adhoc Network */ +} POSTPACK WMI_PYXIS_JOIN_CMD; + +typedef PREPACK struct { + WMI_PYXIS_CMD_HDR hdr; + A_BOOL mode; +} POSTPACK WMI_PYXIS_SET_TX_MODE_CMD; + +/* + * ------- AP Mode definitions -------------- + */ + +#define AP_MAX_NUM_STA 8 +#define AP_ACL_SIZE 10 +#define IEEE80211_MAX_IE 256 +#define MCAST_AID 0xFF /* Spl. AID used to set DTIM flag in the beacons */ + +/* AP mode disconnect reasons */ +#define AP_DISCONNECT_STA_LEFT 101 +#define AP_DISCONNECT_FROM_HOST 102 +#define AP_DISCONNECT_COMM_TIMEOUT 103 + +/* + * Used with WMI_AP_HIDDEN_SSID_CMDID + */ +#define HIDDEN_SSID_FALSE 0 +#define HIDDEN_SSID_TRUE 1 +typedef PREPACK struct { + A_UINT8 hidden_ssid; +} POSTPACK WMI_AP_HIDDEN_SSID_CMD; + +/* + * Used with WMI_AP_ACL_POLICY_CMDID + */ +#define AP_ACL_DISABLE 0x00 +#define AP_ACL_ALLOW_MAC 0x01 +#define AP_ACL_DENY_MAC 0x02 +#define AP_ACL_RETAIN_LIST_MASK 0x80 +typedef PREPACK struct { + A_UINT8 policy; +} POSTPACK WMI_AP_ACL_POLICY_CMD; + +/* + * Used with WMI_AP_ACL_MAC_LIST_CMDID + */ +#define ADD_MAC_ADDR 1 +#define DEL_MAC_ADDR 2 +typedef PREPACK struct { + A_UINT8 action; + A_UINT8 index; + A_UINT8 mac[ATH_MAC_LEN]; + A_UINT8 wildcard; +} POSTPACK WMI_AP_ACL_MAC_CMD; + +typedef PREPACK struct { + A_UINT16 index; + A_UINT8 acl_mac[AP_ACL_SIZE][ATH_MAC_LEN]; + A_UINT8 wildcard[AP_ACL_SIZE]; + A_UINT8 policy; +} POSTPACK WMI_AP_ACL; + +/* + * Used with WMI_AP_SET_NUM_STA_CMDID + */ +typedef PREPACK struct { + A_UINT8 num_sta; +} POSTPACK WMI_AP_SET_NUM_STA_CMD; + +/* + * Used with WMI_AP_SET_MLME_CMDID + */ +typedef PREPACK struct { + A_UINT8 mac[ATH_MAC_LEN]; + A_UINT16 reason; /* 802.11 reason code */ + A_UINT8 cmd; /* operation to perform */ +#define WMI_AP_MLME_ASSOC 1 /* associate station */ +#define WMI_AP_DISASSOC 2 /* disassociate station */ +#define WMI_AP_DEAUTH 3 /* deauthenticate station */ +#define WMI_AP_MLME_AUTHORIZE 4 /* authorize station */ +#define WMI_AP_MLME_UNAUTHORIZE 5 /* unauthorize station */ +} POSTPACK WMI_AP_SET_MLME_CMD; + +typedef PREPACK struct { + A_UINT32 period; +} POSTPACK WMI_AP_CONN_INACT_CMD; + +typedef PREPACK struct { + A_UINT32 period_min; + A_UINT32 dwell_ms; +} POSTPACK WMI_AP_PROT_SCAN_TIME_CMD; + +typedef PREPACK struct { + A_BOOL flag; + A_UINT16 aid; +} POSTPACK WMI_AP_SET_PVB_CMD; + +#define WMI_DISABLE_REGULATORY_CODE "FF" + +typedef PREPACK struct { + A_UCHAR countryCode[3]; +} POSTPACK WMI_AP_SET_COUNTRY_CMD; + +typedef PREPACK struct { + A_UINT8 dtim; +} POSTPACK WMI_AP_SET_DTIM_CMD; + +/* AP mode events */ +/* WMI_PS_POLL_EVENT */ +typedef PREPACK struct { + A_UINT16 aid; +} POSTPACK WMI_PSPOLL_EVENT; + +/* + * End of AP mode definitions + */ + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/wmi_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/wmi_api.h --- linux-2.6.26/drivers/net/wireless/ath6k/wmi_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/wmi_api.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,367 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions for the Wireless Module Interface (WMI). +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _WMI_API_H_ +#define _WMI_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * IP QoS Field definitions according to 802.1p + */ +#define BEST_EFFORT_PRI 0 +#define BACKGROUND_PRI 1 +#define EXCELLENT_EFFORT_PRI 3 +#define CONTROLLED_LOAD_PRI 4 +#define VIDEO_PRI 5 +#define VOICE_PRI 6 +#define NETWORK_CONTROL_PRI 7 +#define MAX_NUM_PRI 8 + +#define UNDEFINED_PRI (0xff) + +#define WMI_IMPLICIT_PSTREAM_INACTIVITY_INT 5000 /* 5 seconds */ + +#define A_ROUND_UP(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) + +typedef enum { + ATHEROS_COMPLIANCE = 0x1, +}TSPEC_PARAM_COMPLIANCE; + +struct wmi_t; + +void *wmi_init(void *devt); + +void wmi_qos_state_init(struct wmi_t *wmip); +void wmi_shutdown(struct wmi_t *wmip); +HTC_ENDPOINT_ID wmi_get_control_ep(struct wmi_t * wmip); +void wmi_set_control_ep(struct wmi_t * wmip, HTC_ENDPOINT_ID eid); +A_UINT16 wmi_get_mapped_qos_queue(struct wmi_t *, A_UINT8); +A_STATUS wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf); +A_STATUS wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType, A_BOOL bMoreData); +A_STATUS wmi_dot3_2_dix(struct wmi_t *wmip, void *osbuf); + +A_STATUS wmi_dot11_hdr_remove (struct wmi_t *wmip, void *osbuf); +A_STATUS wmi_dot11_hdr_add(struct wmi_t *wmip, void *osbuf, NETWORK_TYPE mode); + +A_STATUS wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf); +A_STATUS wmi_syncpoint(struct wmi_t *wmip); +A_STATUS wmi_syncpoint_reset(struct wmi_t *wmip); +A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT32 layer2Priority, A_BOOL wmmEnabled); + +A_UINT8 wmi_determine_userPriority (A_UINT8 *pkt, A_UINT32 layer2Pri); + +A_STATUS wmi_control_rx(struct wmi_t *wmip, void *osbuf); +void wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg); +void wmi_free_allnodes(struct wmi_t *wmip); +bss_t *wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr); +void wmi_free_node(struct wmi_t *wmip, const A_UINT8 *macaddr); + + +typedef enum { + NO_SYNC_WMIFLAG = 0, + SYNC_BEFORE_WMIFLAG, /* transmit all queued data before cmd */ + SYNC_AFTER_WMIFLAG, /* any new data waits until cmd execs */ + SYNC_BOTH_WMIFLAG, + END_WMIFLAG /* end marker */ +} WMI_SYNC_FLAG; + +A_STATUS wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId, + WMI_SYNC_FLAG flag); + +A_STATUS wmi_connect_cmd(struct wmi_t *wmip, + NETWORK_TYPE netType, + DOT11_AUTH_MODE dot11AuthMode, + AUTH_MODE authMode, + CRYPTO_TYPE pairwiseCrypto, + A_UINT8 pairwiseCryptoLen, + CRYPTO_TYPE groupCrypto, + A_UINT8 groupCryptoLen, + int ssidLength, + A_UCHAR *ssid, + A_UINT8 *bssid, + A_UINT16 channel, + A_UINT32 ctrl_flags); + +A_STATUS wmi_reconnect_cmd(struct wmi_t *wmip, + A_UINT8 *bssid, + A_UINT16 channel); +A_STATUS wmi_disconnect_cmd(struct wmi_t *wmip); +A_STATUS wmi_getrev_cmd(struct wmi_t *wmip); +A_STATUS wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType, + A_BOOL forceFgScan, A_BOOL isLegacy, + A_UINT32 homeDwellTime, A_UINT32 forceScanInterval, + A_INT8 numChan, A_UINT16 *channelList); +A_STATUS wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec, + A_UINT16 fg_end_sec, A_UINT16 bg_sec, + A_UINT16 minact_chdw_msec, + A_UINT16 maxact_chdw_msec, A_UINT16 pas_chdw_msec, + A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags, + A_UINT32 max_dfsch_act_time, + A_UINT16 maxact_scan_per_ssid); +A_STATUS wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask); +A_STATUS wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag, + A_UINT8 ssidLength, A_UCHAR *ssid); +A_STATUS wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons); +A_STATUS wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmisstime, A_UINT16 bmissbeacons); +A_STATUS wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType, + A_UINT8 ieLen, A_UINT8 *ieInfo); +A_STATUS wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode); +A_STATUS wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl, + A_UINT16 atim_windows, A_UINT16 timeout_value); +A_STATUS wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod, + A_UINT16 psPollNum, A_UINT16 dtimPolicy); +A_STATUS wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout); +A_STATUS wmi_sync_cmd(struct wmi_t *wmip, A_UINT8 syncNumber); +A_STATUS wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *pstream); +A_STATUS wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 streamID); +A_STATUS wmi_set_framerate_cmd(struct wmi_t *wmip, A_UINT8 bEnable, A_UINT8 type, A_UINT8 subType, A_UINT16 rateMask); +A_STATUS wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 dataRate, A_INT32 mgmtRate, A_INT32 ctlRate); +A_STATUS wmi_get_bitrate_cmd(struct wmi_t *wmip); +A_INT8 wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate); +A_STATUS wmi_get_regDomain_cmd(struct wmi_t *wmip); +A_STATUS wmi_get_channelList_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam, + WMI_PHY_MODE mode, A_INT8 numChan, + A_UINT16 *channelList); + +A_STATUS wmi_set_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd); +A_STATUS wmi_set_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd); +A_STATUS wmi_clr_rssi_snr(struct wmi_t *wmip); +A_STATUS wmi_set_lq_threshold_params(struct wmi_t *wmip, + WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd); +A_STATUS wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold); +A_STATUS wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status); + +A_STATUS wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 bitmask); + +A_STATUS wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie, + A_UINT32 source); + +A_STATUS wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask, + A_UINT16 tsr, A_BOOL rep, A_UINT16 size, + A_UINT32 valid); + +A_STATUS wmi_get_stats_cmd (struct wmi_t *wmip); + +A_STATUS wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex, + CRYPTO_TYPE keyType, A_UINT8 keyUsage, + A_UINT8 keyLength,A_UINT8 *keyRSC, + A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl, A_UINT8 *mac, + WMI_SYNC_FLAG sync_flag); +A_STATUS wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk); +A_STATUS wmi_delete_krk_cmd(struct wmi_t *wmip); +A_STATUS wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex); +A_STATUS wmi_set_akmp_params_cmd(struct wmi_t *wmip, + WMI_SET_AKMP_PARAMS_CMD *akmpParams); +A_STATUS wmi_get_pmkid_list_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_pmkid_list_cmd(struct wmi_t *wmip, + WMI_SET_PMKID_LIST_CMD *pmkInfo); +A_STATUS wmi_abort_scan_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM); +A_STATUS wmi_get_txPwr_cmd(struct wmi_t *wmip); +A_STATUS wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid); +A_STATUS wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex); +A_STATUS wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en); +A_STATUS wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId, + A_BOOL set); +A_STATUS wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT16 txop, + A_UINT8 eCWmin, A_UINT8 eCWmax, + A_UINT8 aifsn); +A_STATUS wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType, + A_UINT8 trafficClass, A_UINT8 maxRetries, + A_UINT8 enableNotify); + +void wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid); + +A_STATUS wmi_get_roam_tbl_cmd(struct wmi_t *wmip); +A_STATUS wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType); +A_STATUS wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p, + A_UINT8 size); +A_STATUS wmi_set_powersave_timers_cmd(struct wmi_t *wmip, + WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd, + A_UINT8 size); + +A_STATUS wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode); +A_STATUS wmi_opt_tx_frame_cmd(struct wmi_t *wmip, + A_UINT8 frmType, + A_UINT8 *dstMacAddr, + A_UINT8 *bssid, + A_UINT16 optIEDataLen, + A_UINT8 *optIEData); + +A_STATUS wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl); +A_STATUS wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize); +A_STATUS wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSpLen); +A_UINT8 convert_userPriority_to_trafficClass(A_UINT8 userPriority); +A_UINT8 wmi_get_power_mode_cmd(struct wmi_t *wmip); +A_STATUS wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance); + +#ifdef CONFIG_HOST_TCMD_SUPPORT +A_STATUS wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32 len); +#endif + +A_STATUS wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status); +A_STATUS wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd); + + +/* + * This function is used to configure the fix rates mask to the target. + */ +A_STATUS wmi_set_fixrates_cmd(struct wmi_t *wmip, A_INT16 fixRatesMask); +A_STATUS wmi_get_ratemask_cmd(struct wmi_t *wmip); + +A_STATUS wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode); + +A_STATUS wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode); + +A_STATUS wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status); +A_STATUS wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG txEnable); +A_STATUS wmi_set_country(struct wmi_t *wmip, A_UCHAR *countryCode); + +A_STATUS wmi_get_keepalive_configured(struct wmi_t *wmip); +A_UINT8 wmi_get_keepalive_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval); + +A_STATUS wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType, + A_UINT8 ieLen,A_UINT8 *ieInfo); + +A_STATUS wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen); + +A_INT32 wmi_get_rate(A_INT8 rateindex); + +A_STATUS wmi_set_ip_cmd(struct wmi_t *wmip, WMI_SET_IP_CMD *cmd); + +/*Wake on Wireless WMI commands*/ +A_STATUS wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip, WMI_SET_HOST_SLEEP_MODE_CMD *cmd); +A_STATUS wmi_set_wow_mode_cmd(struct wmi_t *wmip, WMI_SET_WOW_MODE_CMD *cmd); +A_STATUS wmi_get_wow_list_cmd(struct wmi_t *wmip, WMI_GET_WOW_LIST_CMD *cmd); +A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip, + WMI_ADD_WOW_PATTERN_CMD *cmd, A_UINT8* pattern, A_UINT8* mask, A_UINT8 pattern_size); +A_STATUS wmi_del_wow_pattern_cmd(struct wmi_t *wmip, + WMI_DEL_WOW_PATTERN_CMD *cmd); +A_STATUS wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status); + +A_STATUS +wmi_set_params_cmd(struct wmi_t *wmip, A_UINT32 opcode, A_UINT32 length, A_CHAR* buffer); + +A_STATUS +wmi_set_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4); + +A_STATUS +wmi_del_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4); + +bss_t * +wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID); + + +void +wmi_node_return (struct wmi_t *wmip, bss_t *bss); + +void +wmi_set_nodeage(struct wmi_t *wmip, A_UINT32 nodeAge); + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +A_STATUS wmi_prof_cfg_cmd(struct wmi_t *wmip, A_UINT32 period, A_UINT32 nbins); +A_STATUS wmi_prof_addr_set_cmd(struct wmi_t *wmip, A_UINT32 addr); +A_STATUS wmi_prof_start_cmd(struct wmi_t *wmip); +A_STATUS wmi_prof_stop_cmd(struct wmi_t *wmip); +A_STATUS wmi_prof_count_get_cmd(struct wmi_t *wmip); +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ +#ifdef OS_ROAM_MANAGEMENT +void wmi_scan_indication (struct wmi_t *wmip); +#endif + +A_STATUS +wmi_set_target_event_report_cmd(struct wmi_t *wmip, WMI_SET_TARGET_EVENT_REPORT_CMD* cmd); + +#ifdef PYXIS_ADHOC +A_STATUS +wmi_set_pyxis_gen_config (struct wmi_t *wmip, A_UINT32 dataWindowSizeMin, A_UINT32 dataWindowSizeMax, A_UINT8 maxJoiners); + +A_STATUS +wmi_set_pyxis_dscvr_config (struct wmi_t *wmip, A_UINT32 dscvrWindow, A_UINT32 dscvrInterval, + A_UINT32 probeInterval, A_UINT32 probePeriod, A_UINT16 dscvrChannel); +A_STATUS +wmi_pyxis_disconnect_cmd (struct wmi_t *wmip, A_UINT8 *bssid); + +A_STATUS +wmi_pyxis_join_cmd (struct wmi_t *wmip, NETWORK_TYPE wmiNetworkType, + DOT11_AUTH_MODE dot11AuthMode, AUTH_MODE authMode, + CRYPTO_TYPE pairwiseCrypto, A_UINT8 pairwiseCryptoLen, + CRYPTO_TYPE groupCrypto, A_UINT8 groupCryptoLen, + A_UINT8 *bssid, A_UINT8 *nwBSSID, A_UINT16 channel, A_UINT32 ctrl_flags + ); +#endif + +bss_t *wmi_rm_current_bss (struct wmi_t *wmip, A_UINT8 *id); +A_STATUS wmi_add_current_bss (struct wmi_t *wmip, A_UINT8 *id, bss_t *bss); + + +/* + * AP mode + */ +A_STATUS +wmi_ap_profile_commit(struct wmi_t *wmip, WMI_CONNECT_CMD *p); + +A_STATUS +wmi_ap_set_hidden_ssid(struct wmi_t *wmip, A_UINT8 hidden_ssid); + +A_STATUS +wmi_ap_set_num_sta(struct wmi_t *wmip, A_UINT8 num_sta); + +A_STATUS +wmi_ap_set_acl_policy(struct wmi_t *wmip, A_UINT8 policy); + +A_STATUS +wmi_ap_acl_mac_list(struct wmi_t *wmip, WMI_AP_ACL_MAC_CMD *a); + +A_UINT8 +acl_add_del_mac(WMI_AP_ACL *a, WMI_AP_ACL_MAC_CMD *acl); + +A_STATUS +wmi_ap_set_mlme(struct wmi_t *wmip, A_UINT8 cmd, A_UINT8 *mac, A_UINT16 reason); + +A_STATUS +wmi_set_pvb_cmd(struct wmi_t *wmip, A_UINT16 aid, A_BOOL flag); + +A_STATUS +wmi_ap_conn_inact_time(struct wmi_t *wmip, A_UINT32 period); + +A_STATUS +wmi_ap_bgscan_time(struct wmi_t *wmip, A_UINT32 period, A_UINT32 dwell); + +A_STATUS +wmi_ap_set_dtim(struct wmi_t *wmip, A_UINT8 dtim); + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/wmi_filter_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/wmi_filter_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k/wmi_filter_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/wmi_filter_linux.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,246 @@ +/* + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + */ + +#ifndef _WMI_FILTER_LINUX_H_ +#define _WMI_FILTER_LINUX_H_ + +/* + * sioctl_filter - Standard ioctl + * pioctl_filter - Priv ioctl + * xioctl_filter - eXtended ioctl + * + * ---- Possible values for the WMI filter --------------- + * (0) - Block this cmd always (or) not implemented + * (INFRA_NETWORK) - Allow this cmd only in STA mode + * (ADHOC_NETWORK) - Allow this cmd only in IBSS mode + * (AP_NETWORK) - Allow this cmd only in AP mode + * (INFRA_NETWORK | ADHOC_NETWORK) - Block this cmd in AP mode + * (ADHOC_NETWORK | AP_NETWORK) - Block this cmd in STA mode + * (INFRA_NETWORK | AP_NETWORK) - Block this cmd in IBSS mode + * (INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK)- allow only when mode is set + * (0xFF) - Allow this cmd always irrespective of mode + */ + +A_UINT8 sioctl_filter[] = { +(AP_NETWORK), /* SIOCSIWCOMMIT 0x8B00 */ +(0xFF), /* SIOCGIWNAME 0x8B01 */ +(0), /* SIOCSIWNWID 0x8B02 */ +(0), /* SIOCGIWNWID 0x8B03 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWFREQ 0x8B04 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWFREQ 0x8B05 */ +(0xFF), /* SIOCSIWMODE 0x8B06 */ +(0xFF), /* SIOCGIWMODE 0x8B07 */ +(0), /* SIOCSIWSENS 0x8B08 */ +(0), /* SIOCGIWSENS 0x8B09 */ +(0), /* SIOCSIWRANGE 0x8B0A */ +(0xFF), /* SIOCGIWRANGE 0x8B0B */ +(0), /* SIOCSIWPRIV 0x8B0C */ +(0), /* SIOCGIWPRIV 0x8B0D */ +(0), /* SIOCSIWSTATS 0x8B0E */ +(0), /* SIOCGIWSTATS 0x8B0F */ +(0), /* SIOCSIWSPY 0x8B10 */ +(0), /* SIOCGIWSPY 0x8B11 */ +(0), /* SIOCSIWTHRSPY 0x8B12 */ +(0), /* SIOCGIWTHRSPY 0x8B13 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWAP 0x8B14 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWAP 0x8B15 */ +(0), /* Dummy 0 */ +(0), /* SIOCGIWAPLIST 0x8B17 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCSIWSCAN 0x8B18 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCGIWSCAN 0x8B19 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWESSID 0x8B1A */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWESSID 0x8B1B */ +(0), /* SIOCSIWNICKN 0x8B1C */ +(0), /* SIOCGIWNICKN 0x8B1D */ +(0), /* Dummy 0 */ +(0), /* Dummy 0 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWRATE 0x8B20 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWRATE 0x8B21 */ +(0), /* SIOCSIWRTS 0x8B22 */ +(0), /* SIOCGIWRTS 0x8B23 */ +(0), /* SIOCSIWFRAG 0x8B24 */ +(0), /* SIOCGIWFRAG 0x8B25 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWTXPOW 0x8B26 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWTXPOW 0x8B27 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCSIWRETRY 0x8B28 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCGIWRETRY 0x8B29 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWENCODE 0x8B2A */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWENCODE 0x8B2B */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCSIWPOWER 0x8B2C */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCGIWPOWER 0x8B2D */ +}; + + + +A_UINT8 pioctl_filter[] = { +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_SETPARAM (SIOCIWFIRSTPRIV+0) */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_SETKEY (SIOCIWFIRSTPRIV+1) */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_DELKEY (SIOCIWFIRSTPRIV+2) */ +(AP_NETWORK), /* IEEE80211_IOCTL_SETMLME (SIOCIWFIRSTPRIV+3) */ +(INFRA_NETWORK), /* IEEE80211_IOCTL_ADDPMKID (SIOCIWFIRSTPRIV+4) */ +(0), /* IEEE80211_IOCTL_SETOPTIE (SIOCIWFIRSTPRIV+5) */ +(0), /* (SIOCIWFIRSTPRIV+6) */ +(0), /* (SIOCIWFIRSTPRIV+7) */ +(0), /* (SIOCIWFIRSTPRIV+8) */ +(0), /* (SIOCIWFIRSTPRIV+9) */ +(0), /* IEEE80211_IOCTL_LASTONE (SIOCIWFIRSTPRIV+10) */ +(0xFF), /* AR6000_IOCTL_WMI_GETREV (SIOCIWFIRSTPRIV+11) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SETPWR (SIOCIWFIRSTPRIV+12) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SETSCAN (SIOCIWFIRSTPRIV+13) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SETLISTENINT (SIOCIWFIRSTPRIV+14) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SETBSSFILTER (SIOCIWFIRSTPRIV+15) */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_IOCTL_WMI_SET_CHANNELPARAMS (SIOCIWFIRSTPRIV+16) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_PROBEDSSID (SIOCIWFIRSTPRIV+17) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_PMPARAMS (SIOCIWFIRSTPRIV+18) */ +(INFRA_NETWORK), /* AR6000_IOCTL_WMI_SET_BADAP (SIOCIWFIRSTPRIV+19) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_GET_QOS_QUEUE (SIOCIWFIRSTPRIV+20) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_CREATE_QOS (SIOCIWFIRSTPRIV+21) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_DELETE_QOS (SIOCIWFIRSTPRIV+22) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_SNRTHRESHOLD (SIOCIWFIRSTPRIV+23) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24)*/ +(0xFF), /* AR6000_IOCTL_WMI_GET_TARGET_STATS (SIOCIWFIRSTPRIV+25) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_ASSOC_INFO (SIOCIWFIRSTPRIV+26) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_ACCESS_PARAMS (SIOCIWFIRSTPRIV+27) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_BMISS_TIME (SIOCIWFIRSTPRIV+28) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_DISC_TIMEOUT (SIOCIWFIRSTPRIV+29) */ +(ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS (SIOCIWFIRSTPRIV+30) */ +}; + + + +A_UINT8 xioctl_filter[] = { +(0xFF), /* Dummy 0 */ +(0xFF), /* AR6000_XIOCTL_BMI_DONE 1 */ +(0xFF), /* AR6000_XIOCTL_BMI_READ_MEMORY 2 */ +(0xFF), /* AR6000_XIOCTL_BMI_WRITE_MEMORY 3 */ +(0xFF), /* AR6000_XIOCTL_BMI_EXECUTE 4 */ +(0xFF), /* AR6000_XIOCTL_BMI_SET_APP_START 5 */ +(0xFF), /* AR6000_XIOCTL_BMI_READ_SOC_REGISTER 6 */ +(0xFF), /* AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER 7 */ +(0xFF), /* AR6000_XIOCTL_BMI_TEST 8 */ +(0xFF), /* AR6000_XIOCTL_UNUSED9 9 */ +(0xFF), /* AR6000_XIOCTL_UNUSED10 10 */ +(0xFF), /* AR6000_XIOCTL_UNUSED11 11 */ +(0xFF), /* AR6000_XIOCTL_FORCE_TARGET_RESET 12 */ +(0xFF), /* AR6000_XIOCTL_HTC_RAW_OPEN 13 */ +(0xFF), /* AR6000_XIOCTL_HTC_RAW_CLOSE 14 */ +(0xFF), /* AR6000_XIOCTL_HTC_RAW_READ 15 */ +(0xFF), /* AR6000_XIOCTL_HTC_RAW_WRITE 16 */ +(0xFF), /* AR6000_XIOCTL_CHECK_TARGET_READY 17 */ +(0xFF), /* AR6000_XIOCTL_GPIO_OUTPUT_SET 18 */ +(0xFF), /* AR6000_XIOCTL_GPIO_INPUT_GET 19 */ +(0xFF), /* AR6000_XIOCTL_GPIO_REGISTER_SET 20 */ +(0xFF), /* AR6000_XIOCTL_GPIO_REGISTER_GET 21 */ +(0xFF), /* AR6000_XIOCTL_GPIO_INTR_ACK 22 */ +(0xFF), /* AR6000_XIOCTL_GPIO_INTR_WAIT 23 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_ADHOC_BSSID 24 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_OPT_MODE 25 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_OPT_SEND_FRAME 26 */ +(ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_SET_BEACON_INTVAL 27 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_SETAUTHALG 28 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_VOICE_PKT_SIZE 29 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_MAX_SP 30 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_ROAM_TBL 31 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_ROAM_CTRL 32 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS 33 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTRL_WMI_GET_POWER_MODE 34 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTRL_WMI_SET_WLAN_STATE 35 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_ROAM_DATA 36 */ +(0xFF), /* AR6000_XIOCTL_WMI_SETRETRYLIMITS 37 */ +(0xFF), /* AR6000_XIOCTL_TCMD_CONT_TX 38 */ +(0xFF), /* AR6000_XIOCTL_TCMD_CONT_RX 39 */ +(0xFF), /* AR6000_XIOCTL_TCMD_PM 40 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_STARTSCAN 41 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SETFIXRATES 42 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_GETFIXRATES 43 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD 44 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_CLR_RSSISNR 45 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_LQTHRESHOLD 46 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_RTS 47 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_LPREAMBLE 48 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_AUTHMODE 49 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_REASSOCMODE 50 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_WMM 51 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS 52 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP 53 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_GET_RD 54 */ +(0xFF), /* AR6000_XIOCTL_DIAG_READ 55 */ +(0xFF), /* AR6000_XIOCTL_DIAG_WRITE 56 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_TXOP 57 */ +(INFRA_NETWORK), /* AR6000_XIOCTL_USER_SETKEYS 58 */ +(INFRA_NETWORK), /* AR6000_XIOCTL_WMI_SET_KEEPALIVE 59 */ +(INFRA_NETWORK), /* AR6000_XIOCTL_WMI_GET_KEEPALIVE 60 */ +(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_INSTALL 61 */ +(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL 62 */ +(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE 63 */ +(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE 64 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_APPIE 65 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER 66 */ +(0xFF), /* AR6000_XIOCTL_DBGLOG_CFG_MODULE 67 */ +(0xFF), /* AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS 68 */ +(0xFF), /* Dummy 69 */ +(INFRA_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_WSC_STATUS 70 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BT_STATUS 71 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BT_PARAMS 72 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE 73 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_WOW_MODE 74 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_WOW_LIST 75 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_ADD_WOW_PATTERN 76 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_DEL_WOW_PATTERN 77 */ +(0xFF), /* AR6000_XIOCTL_TARGET_INFO 78 */ +(0xFF), /* AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE 79 */ +(0xFF), /* AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE 80 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS 81 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_AKMP_PARAMS 82 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_PMKID_LIST 83 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_PMKID_LIST 84 */ +(0xFF), /* Dummy 85 */ +(0xFF), /* Dummy 86 */ +(0xFF), /* Dummy 87 */ +(0xFF), /* Dummy 88 */ +(0xFF), /* Dummy 89 */ +(0xFF), /* AR6000_XIOCTL_UNUSED90 90 */ +(0xFF), /* AR6000_XIOCTL_BMI_LZ_STREAM_START 91 */ +(0xFF), /* AR6000_XIOCTL_BMI_LZ_DATA 92 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_CFG 93 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_ADDR_SET 94 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_START 95 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_STOP 96 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_COUNT_GET 97 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_ABORT_SCAN 98 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_STA_LIST 99 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_HIDDEN_SSID 100 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_NUM_STA 101 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_ACL_MAC 102 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_ACL_LIST 103 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_COMMIT_CONFIG 104 */ +(AP_NETWORK), /* IEEE80211_IOCTL_GETWPAIE 105 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_CONN_INACT_TIME 106 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_PROT_SCAN_TIME 107 */ +(AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_COUNTRY 108 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_DTIM 109 */ +(0xFF), /* AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT 110 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_IP 111 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_ACL_POLICY 112 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_INTRA_BSS_COMM 113 */ +}; + +#endif /*_WMI_FILTER_LINUX_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/wmi_host.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/wmi_host.h --- linux-2.6.26/drivers/net/wireless/ath6k/wmi_host.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/wmi_host.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,80 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains local definitios for the wmi host module. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _WMI_HOST_H_ +#define _WMI_HOST_H_ + +#include "roaming.h" +#ifdef __cplusplus +extern "C" { +#endif + +struct wmi_stats { + A_UINT32 cmd_len_err; + A_UINT32 cmd_id_err; +}; + +/* Host side link management data structures */ +#define SIGNAL_QUALITY_THRESHOLD_LEVELS 6 +#define SIGNAL_QUALITY_UPPER_THRESHOLD_LEVELS SIGNAL_QUALITY_THRESHOLD_LEVELS +#define SIGNAL_QUALITY_LOWER_THRESHOLD_LEVELS SIGNAL_QUALITY_THRESHOLD_LEVELS +typedef struct sq_threshold_params_s { + A_INT16 upper_threshold[SIGNAL_QUALITY_UPPER_THRESHOLD_LEVELS]; + A_INT16 lower_threshold[SIGNAL_QUALITY_LOWER_THRESHOLD_LEVELS]; + A_UINT32 upper_threshold_valid_count; + A_UINT32 lower_threshold_valid_count; + A_UINT32 polling_interval; + A_UINT8 weight; + A_UINT8 last_rssi; //normally you would expect this to be bss specific but we keep only one instance because its only valid when the device is in a connected state. Not sure if it belongs to host or target. + A_UINT8 last_rssi_poll_event; //Not sure if it belongs to host or target +} SQ_THRESHOLD_PARAMS; +struct wmi_t { + A_BOOL wmi_ready; + A_BOOL wmi_numQoSStream; + A_UINT16 wmi_streamExistsForAC[WMM_NUM_AC]; + A_UINT8 wmi_fatPipeExists; + void *wmi_devt; + struct wmi_stats wmi_stats; + struct ieee80211_node_table wmi_scan_table; + A_UINT8 wmi_bssid[ATH_MAC_LEN]; + A_UINT8 wmi_powerMode; + A_UINT8 wmi_phyMode; + A_UINT8 wmi_keepaliveInterval; + A_MUTEX_T wmi_lock; + HTC_ENDPOINT_ID wmi_endpoint_id; + SQ_THRESHOLD_PARAMS wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_NUM_MAX]; + CRYPTO_TYPE wmi_pair_crypto_type; + CRYPTO_TYPE wmi_grp_crypto_type; + A_BOOL wmi_is_wmm_enabled; +}; + + +#define LOCK_WMI(w) A_MUTEX_LOCK(&(w)->wmi_lock); +#define UNLOCK_WMI(w) A_MUTEX_UNLOCK(&(w)->wmi_lock); + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_HOST_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k/wmix.h linux-2.6.26-lab126/drivers/net/wireless/ath6k/wmix.h --- linux-2.6.26/drivers/net/wireless/ath6k/wmix.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k/wmix.h 2010-08-10 04:16:33.000000000 -0400 @@ -0,0 +1,279 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +/* + * This file contains extensions of the WMI protocol specified in the + * Wireless Module Interface (WMI). It includes definitions of all + * extended commands and events. Extensions include useful commands + * that are not directly related to wireless activities. They may + * be hardware-specific, and they might not be supported on all + * implementations. + * + * Extended WMIX commands are encapsulated in a WMI message with + * cmd=WMI_EXTENSION_CMD. + */ + +#ifndef _WMIX_H_ +#define _WMIX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#include "dbglog.h" + +/* + * Extended WMI commands are those that are needed during wireless + * operation, but which are not really wireless commands. This allows, + * for instance, platform-specific commands. Extended WMI commands are + * embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID. + * Extended WMI events are similarly embedded in a WMI event message with + * WMI_EVENT_ID=WMI_EXTENSION_EVENTID. + */ +typedef PREPACK struct { + A_UINT32 commandId; +} POSTPACK WMIX_CMD_HDR; + +typedef enum { + WMIX_DSETOPEN_REPLY_CMDID = 0x2001, + WMIX_DSETDATA_REPLY_CMDID, + WMIX_GPIO_OUTPUT_SET_CMDID, + WMIX_GPIO_INPUT_GET_CMDID, + WMIX_GPIO_REGISTER_SET_CMDID, + WMIX_GPIO_REGISTER_GET_CMDID, + WMIX_GPIO_INTR_ACK_CMDID, + WMIX_HB_CHALLENGE_RESP_CMDID, + WMIX_DBGLOG_CFG_MODULE_CMDID, + WMIX_PROF_CFG_CMDID, /* 0x200a */ + WMIX_PROF_ADDR_SET_CMDID, + WMIX_PROF_START_CMDID, + WMIX_PROF_STOP_CMDID, + WMIX_PROF_COUNT_GET_CMDID, +} WMIX_COMMAND_ID; + +typedef enum { + WMIX_DSETOPENREQ_EVENTID = 0x3001, + WMIX_DSETCLOSE_EVENTID, + WMIX_DSETDATAREQ_EVENTID, + WMIX_GPIO_INTR_EVENTID, + WMIX_GPIO_DATA_EVENTID, + WMIX_GPIO_ACK_EVENTID, + WMIX_HB_CHALLENGE_RESP_EVENTID, + WMIX_DBGLOG_EVENTID, + WMIX_PROF_COUNT_EVENTID, +} WMIX_EVENT_ID; + +/* + * =============DataSet support================= + */ + +/* + * WMIX_DSETOPENREQ_EVENTID + * DataSet Open Request Event + */ +typedef PREPACK struct { + A_UINT32 dset_id; + A_UINT32 targ_dset_handle; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */ +} POSTPACK WMIX_DSETOPENREQ_EVENT; + +/* + * WMIX_DSETCLOSE_EVENTID + * DataSet Close Event + */ +typedef PREPACK struct { + A_UINT32 access_cookie; +} POSTPACK WMIX_DSETCLOSE_EVENT; + +/* + * WMIX_DSETDATAREQ_EVENTID + * DataSet Data Request Event + */ +typedef PREPACK struct { + A_UINT32 access_cookie; + A_UINT32 offset; + A_UINT32 length; + A_UINT32 targ_buf; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */ +} POSTPACK WMIX_DSETDATAREQ_EVENT; + +typedef PREPACK struct { + A_UINT32 status; + A_UINT32 targ_dset_handle; + A_UINT32 targ_reply_fn; + A_UINT32 targ_reply_arg; + A_UINT32 access_cookie; + A_UINT32 size; + A_UINT32 version; +} POSTPACK WMIX_DSETOPEN_REPLY_CMD; + +typedef PREPACK struct { + A_UINT32 status; + A_UINT32 targ_buf; + A_UINT32 targ_reply_fn; + A_UINT32 targ_reply_arg; + A_UINT32 length; + A_UINT8 buf[1]; +} POSTPACK WMIX_DSETDATA_REPLY_CMD; + + +/* + * =============GPIO support================= + * All masks are 18-bit masks with bit N operating on GPIO pin N. + */ + +#include "gpio.h" + +/* + * Set GPIO pin output state. + * In order for output to be driven, a pin must be enabled for output. + * This can be done during initialization through the GPIO Configuration + * DataSet, or during operation with the enable_mask. + * + * If a request is made to simultaneously set/clear or set/disable or + * clear/disable or disable/enable, results are undefined. + */ +typedef PREPACK struct { + A_UINT32 set_mask; /* pins to set */ + A_UINT32 clear_mask; /* pins to clear */ + A_UINT32 enable_mask; /* pins to enable for output */ + A_UINT32 disable_mask; /* pins to disable/tristate */ +} POSTPACK WMIX_GPIO_OUTPUT_SET_CMD; + +/* + * Set a GPIO register. For debug/exceptional cases. + * Values for gpioreg_id are GPIO_REGISTER_IDs, defined in a + * platform-dependent header. + */ +typedef PREPACK struct { + A_UINT32 gpioreg_id; /* GPIO register ID */ + A_UINT32 value; /* value to write */ +} POSTPACK WMIX_GPIO_REGISTER_SET_CMD; + +/* Get a GPIO register. For debug/exceptional cases. */ +typedef PREPACK struct { + A_UINT32 gpioreg_id; /* GPIO register to read */ +} POSTPACK WMIX_GPIO_REGISTER_GET_CMD; + +/* + * Host acknowledges and re-arms GPIO interrupts. A single + * message should be used to acknowledge all interrupts that + * were delivered in an earlier WMIX_GPIO_INTR_EVENT message. + */ +typedef PREPACK struct { + A_UINT32 ack_mask; /* interrupts to acknowledge */ +} POSTPACK WMIX_GPIO_INTR_ACK_CMD; + +/* + * Target informs Host of GPIO interrupts that have ocurred since the + * last WMIX_GIPO_INTR_ACK_CMD was received. Additional information -- + * the current GPIO input values is provided -- in order to support + * use of a GPIO interrupt as a Data Valid signal for other GPIO pins. + */ +typedef PREPACK struct { + A_UINT32 intr_mask; /* pending GPIO interrupts */ + A_UINT32 input_values; /* recent GPIO input values */ +} POSTPACK WMIX_GPIO_INTR_EVENT; + +/* + * Target responds to Host's earlier WMIX_GPIO_INPUT_GET_CMDID request + * using a GPIO_DATA_EVENT with + * value set to the mask of GPIO pin inputs and + * reg_id set to GPIO_ID_NONE + * + * + * Target responds to Hosts's earlier WMIX_GPIO_REGISTER_GET_CMDID request + * using a GPIO_DATA_EVENT with + * value set to the value of the requested register and + * reg_id identifying the register (reflects the original request) + * NB: reg_id supports the future possibility of unsolicited + * WMIX_GPIO_DATA_EVENTs (for polling GPIO input), and it may + * simplify Host GPIO support. + */ +typedef PREPACK struct { + A_UINT32 value; + A_UINT32 reg_id; +} POSTPACK WMIX_GPIO_DATA_EVENT; + +/* + * =============Error Detection support================= + */ + +/* + * WMIX_HB_CHALLENGE_RESP_CMDID + * Heartbeat Challenge Response command + */ +typedef PREPACK struct { + A_UINT32 cookie; + A_UINT32 source; +} POSTPACK WMIX_HB_CHALLENGE_RESP_CMD; + +/* + * WMIX_HB_CHALLENGE_RESP_EVENTID + * Heartbeat Challenge Response Event + */ +#define WMIX_HB_CHALLENGE_RESP_EVENT WMIX_HB_CHALLENGE_RESP_CMD + +typedef PREPACK struct { + struct dbglog_config_s config; +} POSTPACK WMIX_DBGLOG_CFG_MODULE_CMD; + +/* + * =============Target Profiling support================= + */ + +typedef PREPACK struct { + A_UINT32 period; /* Time (in 30.5us ticks) between samples */ + A_UINT32 nbins; +} POSTPACK WMIX_PROF_CFG_CMD; + +typedef PREPACK struct { + A_UINT32 addr; +} POSTPACK WMIX_PROF_ADDR_SET_CMD; + +/* + * Target responds to Hosts's earlier WMIX_PROF_COUNT_GET_CMDID request + * using a WMIX_PROF_COUNT_EVENT with + * addr set to the next address + * count set to the corresponding count + */ +typedef PREPACK struct { + A_UINT32 addr; + A_UINT32 count; +} POSTPACK WMIX_PROF_COUNT_EVENT; + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _WMIX_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/AR6002_regdump.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/AR6002_regdump.h --- linux-2.6.26/drivers/net/wireless/ath6k22/AR6002_regdump.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/AR6002_regdump.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,59 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2006 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __AR6002_REGDUMP_H__ +#define __AR6002_REGDUMP_H__ + +#if !defined(__ASSEMBLER__) +/* + * XTensa CPU state + * This must match the state saved by the target exception handler. + */ +struct XTensa_exception_frame_s { + A_UINT32 xt_pc; + A_UINT32 xt_ps; + A_UINT32 xt_sar; + A_UINT32 xt_vpri; + A_UINT32 xt_a2; + A_UINT32 xt_a3; + A_UINT32 xt_a4; + A_UINT32 xt_a5; + A_UINT32 xt_exccause; + A_UINT32 xt_lcount; + A_UINT32 xt_lbeg; + A_UINT32 xt_lend; + + /* Extra info to simplify post-mortem stack walkback */ +#define AR6002_REGDUMP_FRAMES 5 + struct { + A_UINT32 a0; /* pc */ + A_UINT32 a1; /* sp */ + A_UINT32 a2; + A_UINT32 a3; + } wb[AR6002_REGDUMP_FRAMES]; +}; +typedef struct XTensa_exception_frame_s CPU_exception_frame_t; +#define RD_SIZE sizeof(CPU_exception_frame_t) + +#endif +#endif /* __AR6002_REGDUMP_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/AR6K_version.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/AR6K_version.h --- linux-2.6.26/drivers/net/wireless/ath6k22/AR6K_version.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/AR6K_version.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#define __VER_MAJOR_ 2 +#define __VER_MINOR_ 2 +#define __VER_PATCH_ 0 + + +/* The makear6ksdk script (used for release builds) modifies the following line. */ +#define __BUILD_NUMBER_ 124 + + +/* Format of the version number. */ +#define VER_MAJOR_BIT_OFFSET 28 +#define VER_MINOR_BIT_OFFSET 24 +#define VER_PATCH_BIT_OFFSET 16 +#define VER_BUILD_NUM_BIT_OFFSET 0 + + +/* + * The version has the following format: + * Bits 28-31: Major version + * Bits 24-27: Minor version + * Bits 16-23: Patch version + * Bits 0-15: Build number (automatically generated during build process ) + * E.g. Build 1.1.3.7 would be represented as 0x11030007. + * + * DO NOT split the following macro into multiple lines as this may confuse the build scripts. + */ +#define AR6K_SW_VERSION ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) ) + + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/Makefile linux-2.6.26-lab126/drivers/net/wireless/ath6k22/Makefile --- linux-2.6.26/drivers/net/wireless/ath6k22/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/Makefile 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,20 @@ +# +# Atheros WiFi driver +# + +EXTRA_CFLAGS += -DSEND_EVENT_TO_APP -DHTC_RAW_INTERFACE -DAR6000REV2 + +obj-$(CONFIG_ATHEROS_AR6000) += ar6000.o + +ar6000-objs := hif.o ar6k.o ar6k_events.o htc_send.o htc_recv.o \ + htc_services.o htc.o bmi.o ar6000_drv.o ar6000_raw_if.o \ + netbuf.o wireless_ext.o ioctl.o engine.o common_drv.o \ + credit_dist.o wmi.o wlan_node.o wlan_recv_beacon.o \ + wlan_utils.o + +ATH_BUILD_TYPE := NATIVEMMC +ATH_BUS_TYPE := SDIO +ATH_BUS_SUBTYPE := linux_sdio +ATH_OS_SUB_TYPE := linux_2_6 +export ATH_BUS_SUBTYPE + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/a_config.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/a_config.h --- linux-2.6.26/drivers/net/wireless/ath6k22/a_config.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/a_config.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,45 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains software configuration options that enables +// specific software "features" +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_CONFIG_H_ +#define _A_CONFIG_H_ + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/config_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/config_wince.h" +#endif + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "config_linux.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/config_rexos.h" +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/a_debug.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/a_debug.h --- linux-2.6.26/drivers/net/wireless/ath6k22/a_debug.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/a_debug.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,59 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_DEBUG_H_ +#define _A_DEBUG_H_ + +#include "a_types.h" +#include "a_osapi.h" + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/debug_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/debug_wince.h" +#endif + +#ifndef UNDER_CE +#define DBG_INFO 0x00000001 +#define DBG_ERROR 0x00000002 +#define DBG_WARNING 0x00000004 +#define DBG_SDIO 0x00000008 +#define DBG_HIF 0x00000010 +#define DBG_HTC 0x00000020 +#define DBG_WMI 0x00000040 +#define DBG_WMI2 0x00000080 +#define DBG_DRIVER 0x00000100 + +#define DBG_DEFAULTS (DBG_ERROR|DBG_WARNING) +#endif + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "debug_linux.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/debug_rexos.h" +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/a_drv.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/a_drv.h --- linux-2.6.26/drivers/net/wireless/ath6k22/a_drv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/a_drv.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,46 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions of the basic atheros data types. +// It is used to map the data types in atheros files to a platform specific +// type. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_DRV_H_ +#define _A_DRV_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "athdrv_linux.h" +#endif + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/athdrv_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/athdrv_wince.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/athdrv_rexos.h" +#endif + +#endif /* _ADRV_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/a_drv_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/a_drv_api.h --- linux-2.6.26/drivers/net/wireless/ath6k22/a_drv_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/a_drv_api.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,211 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_DRV_API_H_ +#define _A_DRV_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************/ +/****************************************************************************/ +/** **/ +/** WMI related hooks **/ +/** **/ +/****************************************************************************/ +/****************************************************************************/ + +#include "ar6000_api.h" + +#define A_WMI_CHANNELLIST_RX(devt, numChan, chanList) \ + ar6000_channelList_rx((devt), (numChan), (chanList)) + +#define A_WMI_SET_NUMDATAENDPTS(devt, num) \ + ar6000_set_numdataendpts((devt), (num)) + +#define A_WMI_CONTROL_TX(devt, osbuf, streamID) \ + ar6000_control_tx((devt), (osbuf), (streamID)) + +#define A_WMI_TARGETSTATS_EVENT(devt, pStats) \ + ar6000_targetStats_event((devt), (pStats)) + +#define A_WMI_SCANCOMPLETE_EVENT(devt, status) \ + ar6000_scanComplete_event((devt), (status)) + +#ifdef CONFIG_HOST_DSET_SUPPORT + +#define A_WMI_DSET_DATA_REQ(devt, access_cookie, offset, length, targ_buf, targ_reply_fn, targ_reply_arg) \ + ar6000_dset_data_req((devt), (access_cookie), (offset), (length), (targ_buf), (targ_reply_fn), (targ_reply_arg)) + +#define A_WMI_DSET_CLOSE(devt, access_cookie) \ + ar6000_dset_close((devt), (access_cookie)) + +#endif + +#define A_WMI_DSET_OPEN_REQ(devt, id, targ_handle, targ_reply_fn, targ_reply_arg) \ + ar6000_dset_open_req((devt), (id), (targ_handle), (targ_reply_fn), (targ_reply_arg)) + +#define A_WMI_CONNECT_EVENT(devt, channel, bssid, listenInterval, beaconInterval, networkType, beaconIeLen, assocReqLen, assocRespLen, assocInfo) \ + ar6000_connect_event((devt), (channel), (bssid), (listenInterval), (beaconInterval), (networkType), (beaconIeLen), (assocReqLen), (assocRespLen), (assocInfo)) + +#define A_WMI_PSPOLL_EVENT(devt, aid)\ + ar6000_pspoll_event((devt),(aid)) + +#define A_WMI_DTIMEXPIRY_EVENT(devt)\ + ar6000_dtimexpiry_event((devt)) + +#define A_WMI_REGDOMAIN_EVENT(devt, regCode) \ + ar6000_regDomain_event((devt), (regCode)) + +#define A_WMI_NEIGHBORREPORT_EVENT(devt, numAps, info) \ + ar6000_neighborReport_event((devt), (numAps), (info)) + +#define A_WMI_DISCONNECT_EVENT(devt, reason, bssid, assocRespLen, assocInfo, protocolReasonStatus) \ + ar6000_disconnect_event((devt), (reason), (bssid), (assocRespLen), (assocInfo), (protocolReasonStatus)) + +#define A_WMI_TKIP_MICERR_EVENT(devt, keyid, ismcast) \ + ar6000_tkip_micerr_event((devt), (keyid), (ismcast)) + +#define A_WMI_BITRATE_RX(devt, rateKbps) \ + ar6000_bitrate_rx((devt), (rateKbps)) + +#define A_WMI_TXPWR_RX(devt, txPwr) \ + ar6000_txPwr_rx((devt), (txPwr)) + +#define A_WMI_READY_EVENT(devt, datap, phyCap, ver) \ + ar6000_ready_event((devt), (datap), (phyCap), (ver)) + +#define A_WMI_DBGLOG_INIT_DONE(ar) \ + ar6000_dbglog_init_done(ar); + +#define A_WMI_RSSI_THRESHOLD_EVENT(devt, newThreshold, rssi) \ + ar6000_rssiThreshold_event((devt), (newThreshold), (rssi)) + +#define A_WMI_REPORT_ERROR_EVENT(devt, errorVal) \ + ar6000_reportError_event((devt), (errorVal)) + +#define A_WMI_ROAM_TABLE_EVENT(devt, pTbl) \ + ar6000_roam_tbl_event((devt), (pTbl)) + +#define A_WMI_ROAM_DATA_EVENT(devt, p) \ + ar6000_roam_data_event((devt), (p)) + +#define A_WMI_WOW_LIST_EVENT(devt, num_filters, wow_filters) \ + ar6000_wow_list_event((devt), (num_filters), (wow_filters)) + +#define A_WMI_CAC_EVENT(devt, ac, cac_indication, statusCode, tspecSuggestion) \ + ar6000_cac_event((devt), (ac), (cac_indication), (statusCode), (tspecSuggestion)) + +#define A_WMI_CHANNEL_CHANGE_EVENT(devt, oldChannel, newChannel) \ + ar6000_channel_change_event((devt), (oldChannel), (newChannel)) + +#define A_WMI_PMKID_LIST_EVENT(devt, num_pmkid, pmkid_list, bssid_list) \ + ar6000_pmkid_list_event((devt), (num_pmkid), (pmkid_list), (bssid_list)) + +#define A_WMI_PEER_EVENT(devt, eventCode, bssid) \ + ar6000_peer_event ((devt), (eventCode), (bssid)) + +#ifdef CONFIG_HOST_GPIO_SUPPORT + +#define A_WMI_GPIO_INTR_RX(intr_mask, input_values) \ + ar6000_gpio_intr_rx((intr_mask), (input_values)) + +#define A_WMI_GPIO_DATA_RX(reg_id, value) \ + ar6000_gpio_data_rx((reg_id), (value)) + +#define A_WMI_GPIO_ACK_RX() \ + ar6000_gpio_ack_rx() + +#endif + +#ifdef SEND_EVENT_TO_APP + +#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) \ + ar6000_send_event_to_app((ar), (eventId), (datap), (len)) + +#define A_WMI_SEND_GENERIC_EVENT_TO_APP(ar, eventId, datap, len) \ + ar6000_send_generic_event_to_app((ar), (eventId), (datap), (len)) + +#else + +#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) +#define A_WMI_SEND_GENERIC_EVENT_TO_APP(ar, eventId, datap, len) + +#endif + +#ifdef CONFIG_HOST_TCMD_SUPPORT +#define A_WMI_TCMD_RX_REPORT_EVENT(devt, results, len) \ + ar6000_tcmd_rx_report_event((devt), (results), (len)) +#endif + +#define A_WMI_HBCHALLENGERESP_EVENT(devt, cookie, source) \ + ar6000_hbChallengeResp_event((devt), (cookie), (source)) + +#define A_WMI_TX_RETRY_ERR_EVENT(devt) \ + ar6000_tx_retry_err_event((devt)) + +#define A_WMI_SNR_THRESHOLD_EVENT_RX(devt, newThreshold, snr) \ + ar6000_snrThresholdEvent_rx((devt), (newThreshold), (snr)) + +#define A_WMI_LQ_THRESHOLD_EVENT_RX(devt, range, lqVal) \ + ar6000_lqThresholdEvent_rx((devt), (range), (lqVal)) + +#define A_WMI_RATEMASK_RX(devt, ratemask) \ + ar6000_ratemask_rx((devt), (ratemask)) + +#define A_WMI_KEEPALIVE_RX(devt, configured) \ + ar6000_keepalive_rx((devt), (configured)) + +#define A_WMI_BSSINFO_EVENT_RX(ar, datp, len) \ + ar6000_bssInfo_event_rx((ar), (datap), (len)) + +#define A_WMI_DBGLOG_EVENT(ar, dropped, buffer, length) \ + ar6000_dbglog_event((ar), (dropped), (buffer), (length)); + +#define A_WMI_STREAM_TX_ACTIVE(devt,trafficClass) \ + ar6000_indicate_tx_activity((devt),(trafficClass), TRUE) + +#define A_WMI_STREAM_TX_INACTIVE(devt,trafficClass) \ + ar6000_indicate_tx_activity((devt),(trafficClass), FALSE) +#define A_WMI_Ac2EndpointID(devht, ac)\ + ar6000_ac2_endpoint_id((devht), (ac)) + +#define A_WMI_Endpoint2Ac(devt, ep) \ + ar6000_endpoint_id2_ac((devt), (ep)) +/****************************************************************************/ +/****************************************************************************/ +/** **/ +/** HTC related hooks **/ +/** **/ +/****************************************************************************/ +/****************************************************************************/ + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +#define A_WMI_PROF_COUNT_RX(addr, count) prof_count_rx((addr), (count)) +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + +#ifdef __cplusplus +} +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/a_osapi.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/a_osapi.h --- linux-2.6.26/drivers/net/wireless/ath6k22/a_osapi.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/a_osapi.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,56 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions of the basic atheros data types. +// It is used to map the data types in atheros files to a platform specific +// type. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_OSAPI_H_ +#define _A_OSAPI_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "osapi_linux.h" +#endif + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/osapi_wince.h" +#include "../os/windows/common/include/netbuf.h" +#if defined __cplusplus || defined __STDC__ +extern "C" +#endif +A_UINT32 a_copy_from_user(void *to, const void *from, A_UINT32 n); +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/osapi_wince.h" +#include "../os/wince/include/netbuf.h" +#if defined __cplusplus || defined __STDC__ +extern "C" +#endif +A_UINT32 a_copy_from_user(void *to, const void *from, A_UINT32 n); +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/osapi_rexos.h" +#endif + +#endif /* _OSAPI_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/a_pyxis.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/a_pyxis.h --- linux-2.6.26/drivers/net/wireless/ath6k22/a_pyxis.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/a_pyxis.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,60 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// +//The software source and binaries included in this development package are +//licensed, not sold. You, or your company, received the package under one +//or more license agreements. The rights granted to you are specifically +//listed in these license agreement(s). All other rights remain with Atheros +//Communications, Inc., its subsidiaries, or the respective owner including +//those listed on the included copyright notices.. Distribution of any +//portion of this package must be in strict compliance with the license +//agreement(s) terms. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the Pyxis definitions for host +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_PYXIS_H_ +#define _A_PYXIS_H_ +/* + * Copyright (c) 2004-2005 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +/* + * This file contains software key stream pyxis adhoc mode options that enables + * specific software "features" + */ +#ifdef UNDER_CE +#include "../os/wince/include/ks_custom_ndis.h" +#endif + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#endif + +#ifdef REXOS +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/a_types.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/a_types.h --- linux-2.6.26/drivers/net/wireless/ath6k22/a_types.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/a_types.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,46 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions of the basic atheros data types. +// It is used to map the data types in atheros files to a platform specific +// type. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_TYPES_H_ +#define _A_TYPES_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "athtypes_linux.h" +#endif + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/athtypes_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/athtypes_wince.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/athtypes_rexos.h" +#endif + +#endif /* _ATHTYPES_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/addrs.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/addrs.h --- linux-2.6.26/drivers/net/wireless/ath6k22/addrs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/addrs.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,85 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __ADDRS_H__ +#define __ADDRS_H__ + +/* + * Special AR6002 Addresses that may be needed by special + * applications (e.g. ART) on the Host as well as Target. + */ + +#if defined(AR6002_REV2) +#define AR6K_RAM_START 0x00500000 +#define TARG_RAM_OFFSET(vaddr) ((A_UINT32)(vaddr) & 0xfffff) +#define TARG_RAM_SZ (184*1024) +#define TARG_ROM_SZ (80*1024) +#endif +#if defined(AR6002_REV4) || defined(AR6003) +#define AR6K_RAM_START 0x00540000 +#define TARG_RAM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0xfffff) - 0x40000) +#define TARG_RAM_SZ (256*1024) +#define TARG_ROM_SZ (256*1024) +#endif + +#define AR6002_BOARD_DATA_SZ 768 +#define AR6003_BOARD_DATA_SZ 1504 + +#define AR6K_RAM_ADDR(byte_offset) (AR6K_RAM_START+(byte_offset)) +#define TARG_RAM_ADDRS(byte_offset) AR6K_RAM_ADDR(byte_offset) + +#define AR6K_ROM_START 0x004e0000 +#define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset)) +#define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset) + +/* + * At this ROM address is a pointer to the start of the ROM DataSet Index. + * If there are no ROM DataSets, there's a 0 at this address. + */ +#define ROM_DATASET_INDEX_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-8) +#define ROM_MBIST_CKSUM_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-4) + +/* + * The API A_BOARD_DATA_ADDR() is the proper way to get a read pointer to + * board data. + */ + +/* Size of Board Data, in bytes */ +#if defined(AR6002_REV4) || defined(AR6003) +#define BOARD_DATA_SZ AR6003_BOARD_DATA_SZ +#else +#define BOARD_DATA_SZ AR6002_BOARD_DATA_SZ +#endif + + +/* + * Constants used by ASM code to access fields of host_interest_s, + * which is at a fixed location in RAM. + */ +#define HOST_INTEREST_FLASH_IS_PRESENT_ADDR (AR6K_RAM_START + 0x40c) +#define FLASH_IS_PRESENT_TARGADDR HOST_INTEREST_FLASH_IS_PRESENT_ADDR + +/* override REV2 ROM's app start address */ +#define AR6002_REV2_APP_START_OVERRIDE 0x913950 + +#endif /* __ADDRS_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/analog_intf_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/analog_intf_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k22/analog_intf_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/analog_intf_reg.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,87 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _ANALOG_INTF_REG_REG_H_ +#define _ANALOG_INTF_REG_REG_H_ + +#define SW_OVERRIDE_ADDRESS 0x00000080 +#define SW_OVERRIDE_OFFSET 0x00000080 +#define SW_OVERRIDE_SUPDATE_DELAY_MSB 1 +#define SW_OVERRIDE_SUPDATE_DELAY_LSB 1 +#define SW_OVERRIDE_SUPDATE_DELAY_MASK 0x00000002 +#define SW_OVERRIDE_SUPDATE_DELAY_GET(x) (((x) & SW_OVERRIDE_SUPDATE_DELAY_MASK) >> SW_OVERRIDE_SUPDATE_DELAY_LSB) +#define SW_OVERRIDE_SUPDATE_DELAY_SET(x) (((x) << SW_OVERRIDE_SUPDATE_DELAY_LSB) & SW_OVERRIDE_SUPDATE_DELAY_MASK) +#define SW_OVERRIDE_ENABLE_MSB 0 +#define SW_OVERRIDE_ENABLE_LSB 0 +#define SW_OVERRIDE_ENABLE_MASK 0x00000001 +#define SW_OVERRIDE_ENABLE_GET(x) (((x) & SW_OVERRIDE_ENABLE_MASK) >> SW_OVERRIDE_ENABLE_LSB) +#define SW_OVERRIDE_ENABLE_SET(x) (((x) << SW_OVERRIDE_ENABLE_LSB) & SW_OVERRIDE_ENABLE_MASK) + +#define SIN_VAL_ADDRESS 0x00000084 +#define SIN_VAL_OFFSET 0x00000084 +#define SIN_VAL_SIN_MSB 0 +#define SIN_VAL_SIN_LSB 0 +#define SIN_VAL_SIN_MASK 0x00000001 +#define SIN_VAL_SIN_GET(x) (((x) & SIN_VAL_SIN_MASK) >> SIN_VAL_SIN_LSB) +#define SIN_VAL_SIN_SET(x) (((x) << SIN_VAL_SIN_LSB) & SIN_VAL_SIN_MASK) + +#define SW_SCLK_ADDRESS 0x00000088 +#define SW_SCLK_OFFSET 0x00000088 +#define SW_SCLK_SW_SCLK_MSB 0 +#define SW_SCLK_SW_SCLK_LSB 0 +#define SW_SCLK_SW_SCLK_MASK 0x00000001 +#define SW_SCLK_SW_SCLK_GET(x) (((x) & SW_SCLK_SW_SCLK_MASK) >> SW_SCLK_SW_SCLK_LSB) +#define SW_SCLK_SW_SCLK_SET(x) (((x) << SW_SCLK_SW_SCLK_LSB) & SW_SCLK_SW_SCLK_MASK) + +#define SW_CNTL_ADDRESS 0x0000008c +#define SW_CNTL_OFFSET 0x0000008c +#define SW_CNTL_SW_SCAPTURE_MSB 2 +#define SW_CNTL_SW_SCAPTURE_LSB 2 +#define SW_CNTL_SW_SCAPTURE_MASK 0x00000004 +#define SW_CNTL_SW_SCAPTURE_GET(x) (((x) & SW_CNTL_SW_SCAPTURE_MASK) >> SW_CNTL_SW_SCAPTURE_LSB) +#define SW_CNTL_SW_SCAPTURE_SET(x) (((x) << SW_CNTL_SW_SCAPTURE_LSB) & SW_CNTL_SW_SCAPTURE_MASK) +#define SW_CNTL_SW_SUPDATE_MSB 1 +#define SW_CNTL_SW_SUPDATE_LSB 1 +#define SW_CNTL_SW_SUPDATE_MASK 0x00000002 +#define SW_CNTL_SW_SUPDATE_GET(x) (((x) & SW_CNTL_SW_SUPDATE_MASK) >> SW_CNTL_SW_SUPDATE_LSB) +#define SW_CNTL_SW_SUPDATE_SET(x) (((x) << SW_CNTL_SW_SUPDATE_LSB) & SW_CNTL_SW_SUPDATE_MASK) +#define SW_CNTL_SW_SOUT_MSB 0 +#define SW_CNTL_SW_SOUT_LSB 0 +#define SW_CNTL_SW_SOUT_MASK 0x00000001 +#define SW_CNTL_SW_SOUT_GET(x) (((x) & SW_CNTL_SW_SOUT_MASK) >> SW_CNTL_SW_SOUT_LSB) +#define SW_CNTL_SW_SOUT_SET(x) (((x) << SW_CNTL_SW_SOUT_LSB) & SW_CNTL_SW_SOUT_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct analog_intf_reg_reg_s { + unsigned char pad0[128]; /* pad to 0x80 */ + volatile unsigned int sw_override; + volatile unsigned int sin_val; + volatile unsigned int sw_sclk; + volatile unsigned int sw_cntl; +} analog_intf_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _ANALOG_INTF_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/analog_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/analog_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k22/analog_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/analog_reg.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,1955 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _ANALOG_REG_REG_H_ +#define _ANALOG_REG_REG_H_ + +#define SYNTH_SYNTH1_ADDRESS 0x00000000 +#define SYNTH_SYNTH1_OFFSET 0x00000000 +#define SYNTH_SYNTH1_PWD_BIAS_MSB 31 +#define SYNTH_SYNTH1_PWD_BIAS_LSB 31 +#define SYNTH_SYNTH1_PWD_BIAS_MASK 0x80000000 +#define SYNTH_SYNTH1_PWD_BIAS_GET(x) (((x) & SYNTH_SYNTH1_PWD_BIAS_MASK) >> SYNTH_SYNTH1_PWD_BIAS_LSB) +#define SYNTH_SYNTH1_PWD_BIAS_SET(x) (((x) << SYNTH_SYNTH1_PWD_BIAS_LSB) & SYNTH_SYNTH1_PWD_BIAS_MASK) +#define SYNTH_SYNTH1_PWD_CP_MSB 30 +#define SYNTH_SYNTH1_PWD_CP_LSB 30 +#define SYNTH_SYNTH1_PWD_CP_MASK 0x40000000 +#define SYNTH_SYNTH1_PWD_CP_GET(x) (((x) & SYNTH_SYNTH1_PWD_CP_MASK) >> SYNTH_SYNTH1_PWD_CP_LSB) +#define SYNTH_SYNTH1_PWD_CP_SET(x) (((x) << SYNTH_SYNTH1_PWD_CP_LSB) & SYNTH_SYNTH1_PWD_CP_MASK) +#define SYNTH_SYNTH1_PWD_VCMON_MSB 29 +#define SYNTH_SYNTH1_PWD_VCMON_LSB 29 +#define SYNTH_SYNTH1_PWD_VCMON_MASK 0x20000000 +#define SYNTH_SYNTH1_PWD_VCMON_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCMON_MASK) >> SYNTH_SYNTH1_PWD_VCMON_LSB) +#define SYNTH_SYNTH1_PWD_VCMON_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCMON_LSB) & SYNTH_SYNTH1_PWD_VCMON_MASK) +#define SYNTH_SYNTH1_PWD_VCO_MSB 28 +#define SYNTH_SYNTH1_PWD_VCO_LSB 28 +#define SYNTH_SYNTH1_PWD_VCO_MASK 0x10000000 +#define SYNTH_SYNTH1_PWD_VCO_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCO_MASK) >> SYNTH_SYNTH1_PWD_VCO_LSB) +#define SYNTH_SYNTH1_PWD_VCO_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCO_LSB) & SYNTH_SYNTH1_PWD_VCO_MASK) +#define SYNTH_SYNTH1_PWD_PRESC_MSB 27 +#define SYNTH_SYNTH1_PWD_PRESC_LSB 27 +#define SYNTH_SYNTH1_PWD_PRESC_MASK 0x08000000 +#define SYNTH_SYNTH1_PWD_PRESC_GET(x) (((x) & SYNTH_SYNTH1_PWD_PRESC_MASK) >> SYNTH_SYNTH1_PWD_PRESC_LSB) +#define SYNTH_SYNTH1_PWD_PRESC_SET(x) (((x) << SYNTH_SYNTH1_PWD_PRESC_LSB) & SYNTH_SYNTH1_PWD_PRESC_MASK) +#define SYNTH_SYNTH1_PWD_LODIV_MSB 26 +#define SYNTH_SYNTH1_PWD_LODIV_LSB 26 +#define SYNTH_SYNTH1_PWD_LODIV_MASK 0x04000000 +#define SYNTH_SYNTH1_PWD_LODIV_GET(x) (((x) & SYNTH_SYNTH1_PWD_LODIV_MASK) >> SYNTH_SYNTH1_PWD_LODIV_LSB) +#define SYNTH_SYNTH1_PWD_LODIV_SET(x) (((x) << SYNTH_SYNTH1_PWD_LODIV_LSB) & SYNTH_SYNTH1_PWD_LODIV_MASK) +#define SYNTH_SYNTH1_PWD_LOMIX_MSB 25 +#define SYNTH_SYNTH1_PWD_LOMIX_LSB 25 +#define SYNTH_SYNTH1_PWD_LOMIX_MASK 0x02000000 +#define SYNTH_SYNTH1_PWD_LOMIX_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOMIX_MASK) >> SYNTH_SYNTH1_PWD_LOMIX_LSB) +#define SYNTH_SYNTH1_PWD_LOMIX_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOMIX_LSB) & SYNTH_SYNTH1_PWD_LOMIX_MASK) +#define SYNTH_SYNTH1_FORCE_LO_ON_MSB 24 +#define SYNTH_SYNTH1_FORCE_LO_ON_LSB 24 +#define SYNTH_SYNTH1_FORCE_LO_ON_MASK 0x01000000 +#define SYNTH_SYNTH1_FORCE_LO_ON_GET(x) (((x) & SYNTH_SYNTH1_FORCE_LO_ON_MASK) >> SYNTH_SYNTH1_FORCE_LO_ON_LSB) +#define SYNTH_SYNTH1_FORCE_LO_ON_SET(x) (((x) << SYNTH_SYNTH1_FORCE_LO_ON_LSB) & SYNTH_SYNTH1_FORCE_LO_ON_MASK) +#define SYNTH_SYNTH1_PWD_LOBUF5G_MSB 23 +#define SYNTH_SYNTH1_PWD_LOBUF5G_LSB 23 +#define SYNTH_SYNTH1_PWD_LOBUF5G_MASK 0x00800000 +#define SYNTH_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK) >> SYNTH_SYNTH1_PWD_LOBUF5G_LSB) +#define SYNTH_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOBUF5G_LSB) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK) +#define SYNTH_SYNTH1_VCOREGBYPASS_MSB 22 +#define SYNTH_SYNTH1_VCOREGBYPASS_LSB 22 +#define SYNTH_SYNTH1_VCOREGBYPASS_MASK 0x00400000 +#define SYNTH_SYNTH1_VCOREGBYPASS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBYPASS_MASK) >> SYNTH_SYNTH1_VCOREGBYPASS_LSB) +#define SYNTH_SYNTH1_VCOREGBYPASS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBYPASS_LSB) & SYNTH_SYNTH1_VCOREGBYPASS_MASK) +#define SYNTH_SYNTH1_VCOREGLEVEL_MSB 21 +#define SYNTH_SYNTH1_VCOREGLEVEL_LSB 20 +#define SYNTH_SYNTH1_VCOREGLEVEL_MASK 0x00300000 +#define SYNTH_SYNTH1_VCOREGLEVEL_GET(x) (((x) & SYNTH_SYNTH1_VCOREGLEVEL_MASK) >> SYNTH_SYNTH1_VCOREGLEVEL_LSB) +#define SYNTH_SYNTH1_VCOREGLEVEL_SET(x) (((x) << SYNTH_SYNTH1_VCOREGLEVEL_LSB) & SYNTH_SYNTH1_VCOREGLEVEL_MASK) +#define SYNTH_SYNTH1_VCOREGBIAS_MSB 19 +#define SYNTH_SYNTH1_VCOREGBIAS_LSB 18 +#define SYNTH_SYNTH1_VCOREGBIAS_MASK 0x000c0000 +#define SYNTH_SYNTH1_VCOREGBIAS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBIAS_MASK) >> SYNTH_SYNTH1_VCOREGBIAS_LSB) +#define SYNTH_SYNTH1_VCOREGBIAS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBIAS_LSB) & SYNTH_SYNTH1_VCOREGBIAS_MASK) +#define SYNTH_SYNTH1_SLIDINGIF_MSB 17 +#define SYNTH_SYNTH1_SLIDINGIF_LSB 17 +#define SYNTH_SYNTH1_SLIDINGIF_MASK 0x00020000 +#define SYNTH_SYNTH1_SLIDINGIF_GET(x) (((x) & SYNTH_SYNTH1_SLIDINGIF_MASK) >> SYNTH_SYNTH1_SLIDINGIF_LSB) +#define SYNTH_SYNTH1_SLIDINGIF_SET(x) (((x) << SYNTH_SYNTH1_SLIDINGIF_LSB) & SYNTH_SYNTH1_SLIDINGIF_MASK) +#define SYNTH_SYNTH1_SPARE_PWD_MSB 16 +#define SYNTH_SYNTH1_SPARE_PWD_LSB 16 +#define SYNTH_SYNTH1_SPARE_PWD_MASK 0x00010000 +#define SYNTH_SYNTH1_SPARE_PWD_GET(x) (((x) & SYNTH_SYNTH1_SPARE_PWD_MASK) >> SYNTH_SYNTH1_SPARE_PWD_LSB) +#define SYNTH_SYNTH1_SPARE_PWD_SET(x) (((x) << SYNTH_SYNTH1_SPARE_PWD_LSB) & SYNTH_SYNTH1_SPARE_PWD_MASK) +#define SYNTH_SYNTH1_CON_VDDVCOREG_MSB 15 +#define SYNTH_SYNTH1_CON_VDDVCOREG_LSB 15 +#define SYNTH_SYNTH1_CON_VDDVCOREG_MASK 0x00008000 +#define SYNTH_SYNTH1_CON_VDDVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK) >> SYNTH_SYNTH1_CON_VDDVCOREG_LSB) +#define SYNTH_SYNTH1_CON_VDDVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_VDDVCOREG_LSB) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK) +#define SYNTH_SYNTH1_CON_IVCOREG_MSB 14 +#define SYNTH_SYNTH1_CON_IVCOREG_LSB 14 +#define SYNTH_SYNTH1_CON_IVCOREG_MASK 0x00004000 +#define SYNTH_SYNTH1_CON_IVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCOREG_MASK) >> SYNTH_SYNTH1_CON_IVCOREG_LSB) +#define SYNTH_SYNTH1_CON_IVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOREG_LSB) & SYNTH_SYNTH1_CON_IVCOREG_MASK) +#define SYNTH_SYNTH1_CON_IVCOBUF_MSB 13 +#define SYNTH_SYNTH1_CON_IVCOBUF_LSB 13 +#define SYNTH_SYNTH1_CON_IVCOBUF_MASK 0x00002000 +#define SYNTH_SYNTH1_CON_IVCOBUF_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCOBUF_MASK) >> SYNTH_SYNTH1_CON_IVCOBUF_LSB) +#define SYNTH_SYNTH1_CON_IVCOBUF_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOBUF_LSB) & SYNTH_SYNTH1_CON_IVCOBUF_MASK) +#define SYNTH_SYNTH1_SEL_VCMONABUS_MSB 12 +#define SYNTH_SYNTH1_SEL_VCMONABUS_LSB 10 +#define SYNTH_SYNTH1_SEL_VCMONABUS_MASK 0x00001c00 +#define SYNTH_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK) >> SYNTH_SYNTH1_SEL_VCMONABUS_LSB) +#define SYNTH_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << SYNTH_SYNTH1_SEL_VCMONABUS_LSB) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK) +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MSB 9 +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB 9 +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK 0x00000200 +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK) >> SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB) +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK) +#define SYNTH_SYNTH1_PWUP_LODIV_PD_MSB 8 +#define SYNTH_SYNTH1_PWUP_LODIV_PD_LSB 8 +#define SYNTH_SYNTH1_PWUP_LODIV_PD_MASK 0x00000100 +#define SYNTH_SYNTH1_PWUP_LODIV_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK) >> SYNTH_SYNTH1_PWUP_LODIV_PD_LSB) +#define SYNTH_SYNTH1_PWUP_LODIV_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LODIV_PD_LSB) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK) +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MSB 7 +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB 7 +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK 0x00000080 +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB) +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK) +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MSB 6 +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB 6 +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK 0x00000040 +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB) +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK) +#define SYNTH_SYNTH1_MONITOR_FB_MSB 5 +#define SYNTH_SYNTH1_MONITOR_FB_LSB 5 +#define SYNTH_SYNTH1_MONITOR_FB_MASK 0x00000020 +#define SYNTH_SYNTH1_MONITOR_FB_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB_MASK) >> SYNTH_SYNTH1_MONITOR_FB_LSB) +#define SYNTH_SYNTH1_MONITOR_FB_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_FB_LSB) & SYNTH_SYNTH1_MONITOR_FB_MASK) +#define SYNTH_SYNTH1_MONITOR_REF_MSB 4 +#define SYNTH_SYNTH1_MONITOR_REF_LSB 4 +#define SYNTH_SYNTH1_MONITOR_REF_MASK 0x00000010 +#define SYNTH_SYNTH1_MONITOR_REF_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_REF_MASK) >> SYNTH_SYNTH1_MONITOR_REF_LSB) +#define SYNTH_SYNTH1_MONITOR_REF_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_REF_LSB) & SYNTH_SYNTH1_MONITOR_REF_MASK) +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MSB 3 +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB 3 +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000008 +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK) >> SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB) +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK) +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MSB 2 +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB 2 +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000004 +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK) >> SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB) +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK) +#define SYNTH_SYNTH1_MONITOR_VC2LOW_MSB 1 +#define SYNTH_SYNTH1_MONITOR_VC2LOW_LSB 1 +#define SYNTH_SYNTH1_MONITOR_VC2LOW_MASK 0x00000002 +#define SYNTH_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK) >> SYNTH_SYNTH1_MONITOR_VC2LOW_LSB) +#define SYNTH_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_VC2LOW_LSB) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK) +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 0 +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 0 +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000001 +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK) >> SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB) +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK) + +#define SYNTH_SYNTH2_ADDRESS 0x00000004 +#define SYNTH_SYNTH2_OFFSET 0x00000004 +#define SYNTH_SYNTH2_VC_CAL_REF_MSB 31 +#define SYNTH_SYNTH2_VC_CAL_REF_LSB 29 +#define SYNTH_SYNTH2_VC_CAL_REF_MASK 0xe0000000 +#define SYNTH_SYNTH2_VC_CAL_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_CAL_REF_MASK) >> SYNTH_SYNTH2_VC_CAL_REF_LSB) +#define SYNTH_SYNTH2_VC_CAL_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_CAL_REF_LSB) & SYNTH_SYNTH2_VC_CAL_REF_MASK) +#define SYNTH_SYNTH2_VC_HI_REF_MSB 28 +#define SYNTH_SYNTH2_VC_HI_REF_LSB 26 +#define SYNTH_SYNTH2_VC_HI_REF_MASK 0x1c000000 +#define SYNTH_SYNTH2_VC_HI_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_HI_REF_MASK) >> SYNTH_SYNTH2_VC_HI_REF_LSB) +#define SYNTH_SYNTH2_VC_HI_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_HI_REF_LSB) & SYNTH_SYNTH2_VC_HI_REF_MASK) +#define SYNTH_SYNTH2_VC_MID_REF_MSB 25 +#define SYNTH_SYNTH2_VC_MID_REF_LSB 23 +#define SYNTH_SYNTH2_VC_MID_REF_MASK 0x03800000 +#define SYNTH_SYNTH2_VC_MID_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_MID_REF_MASK) >> SYNTH_SYNTH2_VC_MID_REF_LSB) +#define SYNTH_SYNTH2_VC_MID_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_MID_REF_LSB) & SYNTH_SYNTH2_VC_MID_REF_MASK) +#define SYNTH_SYNTH2_VC_LOW_REF_MSB 22 +#define SYNTH_SYNTH2_VC_LOW_REF_LSB 20 +#define SYNTH_SYNTH2_VC_LOW_REF_MASK 0x00700000 +#define SYNTH_SYNTH2_VC_LOW_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_LOW_REF_MASK) >> SYNTH_SYNTH2_VC_LOW_REF_LSB) +#define SYNTH_SYNTH2_VC_LOW_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_LOW_REF_LSB) & SYNTH_SYNTH2_VC_LOW_REF_MASK) +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MSB 19 +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB 15 +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK 0x000f8000 +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_GET(x) (((x) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK) >> SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB) +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_SET(x) (((x) << SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK) +#define SYNTH_SYNTH2_LOOP_CP_MSB 14 +#define SYNTH_SYNTH2_LOOP_CP_LSB 10 +#define SYNTH_SYNTH2_LOOP_CP_MASK 0x00007c00 +#define SYNTH_SYNTH2_LOOP_CP_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CP_MASK) >> SYNTH_SYNTH2_LOOP_CP_LSB) +#define SYNTH_SYNTH2_LOOP_CP_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CP_LSB) & SYNTH_SYNTH2_LOOP_CP_MASK) +#define SYNTH_SYNTH2_LOOP_RS_MSB 9 +#define SYNTH_SYNTH2_LOOP_RS_LSB 5 +#define SYNTH_SYNTH2_LOOP_RS_MASK 0x000003e0 +#define SYNTH_SYNTH2_LOOP_RS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_RS_MASK) >> SYNTH_SYNTH2_LOOP_RS_LSB) +#define SYNTH_SYNTH2_LOOP_RS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_RS_LSB) & SYNTH_SYNTH2_LOOP_RS_MASK) +#define SYNTH_SYNTH2_LOOP_CS_MSB 4 +#define SYNTH_SYNTH2_LOOP_CS_LSB 3 +#define SYNTH_SYNTH2_LOOP_CS_MASK 0x00000018 +#define SYNTH_SYNTH2_LOOP_CS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CS_MASK) >> SYNTH_SYNTH2_LOOP_CS_LSB) +#define SYNTH_SYNTH2_LOOP_CS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CS_LSB) & SYNTH_SYNTH2_LOOP_CS_MASK) +#define SYNTH_SYNTH2_SPARE_BITS_MSB 2 +#define SYNTH_SYNTH2_SPARE_BITS_LSB 0 +#define SYNTH_SYNTH2_SPARE_BITS_MASK 0x00000007 +#define SYNTH_SYNTH2_SPARE_BITS_GET(x) (((x) & SYNTH_SYNTH2_SPARE_BITS_MASK) >> SYNTH_SYNTH2_SPARE_BITS_LSB) +#define SYNTH_SYNTH2_SPARE_BITS_SET(x) (((x) << SYNTH_SYNTH2_SPARE_BITS_LSB) & SYNTH_SYNTH2_SPARE_BITS_MASK) + +#define SYNTH_SYNTH3_ADDRESS 0x00000008 +#define SYNTH_SYNTH3_OFFSET 0x00000008 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_MSB 31 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_LSB 31 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK) >> SYNTH_SYNTH3_DIS_CLK_XTAL_LSB) +#define SYNTH_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << SYNTH_SYNTH3_DIS_CLK_XTAL_LSB) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK) +#define SYNTH_SYNTH3_SEL_CLK_DIV2_MSB 30 +#define SYNTH_SYNTH3_SEL_CLK_DIV2_LSB 30 +#define SYNTH_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000 +#define SYNTH_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK) >> SYNTH_SYNTH3_SEL_CLK_DIV2_LSB) +#define SYNTH_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << SYNTH_SYNTH3_SEL_CLK_DIV2_LSB) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK) +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29 +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24 +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000 +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB) +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK) +#define SYNTH_SYNTH3_WAIT_PWRUP_MSB 23 +#define SYNTH_SYNTH3_WAIT_PWRUP_LSB 18 +#define SYNTH_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000 +#define SYNTH_SYNTH3_WAIT_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_PWRUP_LSB) +#define SYNTH_SYNTH3_WAIT_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_PWRUP_MASK) +#define SYNTH_SYNTH3_WAIT_CAL_BIN_MSB 17 +#define SYNTH_SYNTH3_WAIT_CAL_BIN_LSB 12 +#define SYNTH_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000 +#define SYNTH_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_BIN_LSB) +#define SYNTH_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_BIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK) +#define SYNTH_SYNTH3_WAIT_CAL_LIN_MSB 11 +#define SYNTH_SYNTH3_WAIT_CAL_LIN_LSB 6 +#define SYNTH_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0 +#define SYNTH_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_LIN_LSB) +#define SYNTH_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_LIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK) +#define SYNTH_SYNTH3_WAIT_VC_CHECK_MSB 5 +#define SYNTH_SYNTH3_WAIT_VC_CHECK_LSB 0 +#define SYNTH_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f +#define SYNTH_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK) >> SYNTH_SYNTH3_WAIT_VC_CHECK_LSB) +#define SYNTH_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << SYNTH_SYNTH3_WAIT_VC_CHECK_LSB) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK) + +#define SYNTH_SYNTH4_ADDRESS 0x0000000c +#define SYNTH_SYNTH4_OFFSET 0x0000000c +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31 +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31 +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000 +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK) >> SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB) +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK) +#define SYNTH_SYNTH4_DIS_LOSTVC_MSB 30 +#define SYNTH_SYNTH4_DIS_LOSTVC_LSB 30 +#define SYNTH_SYNTH4_DIS_LOSTVC_MASK 0x40000000 +#define SYNTH_SYNTH4_DIS_LOSTVC_GET(x) (((x) & SYNTH_SYNTH4_DIS_LOSTVC_MASK) >> SYNTH_SYNTH4_DIS_LOSTVC_LSB) +#define SYNTH_SYNTH4_DIS_LOSTVC_SET(x) (((x) << SYNTH_SYNTH4_DIS_LOSTVC_LSB) & SYNTH_SYNTH4_DIS_LOSTVC_MASK) +#define SYNTH_SYNTH4_ALWAYS_SHORTR_MSB 29 +#define SYNTH_SYNTH4_ALWAYS_SHORTR_LSB 29 +#define SYNTH_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000 +#define SYNTH_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK) >> SYNTH_SYNTH4_ALWAYS_SHORTR_LSB) +#define SYNTH_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << SYNTH_SYNTH4_ALWAYS_SHORTR_LSB) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK) +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28 +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28 +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000 +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK) >> SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB) +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK) +#define SYNTH_SYNTH4_FORCE_PINVC_MSB 27 +#define SYNTH_SYNTH4_FORCE_PINVC_LSB 27 +#define SYNTH_SYNTH4_FORCE_PINVC_MASK 0x08000000 +#define SYNTH_SYNTH4_FORCE_PINVC_GET(x) (((x) & SYNTH_SYNTH4_FORCE_PINVC_MASK) >> SYNTH_SYNTH4_FORCE_PINVC_LSB) +#define SYNTH_SYNTH4_FORCE_PINVC_SET(x) (((x) << SYNTH_SYNTH4_FORCE_PINVC_LSB) & SYNTH_SYNTH4_FORCE_PINVC_MASK) +#define SYNTH_SYNTH4_FORCE_VCOCAP_MSB 26 +#define SYNTH_SYNTH4_FORCE_VCOCAP_LSB 26 +#define SYNTH_SYNTH4_FORCE_VCOCAP_MASK 0x04000000 +#define SYNTH_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK) >> SYNTH_SYNTH4_FORCE_VCOCAP_LSB) +#define SYNTH_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << SYNTH_SYNTH4_FORCE_VCOCAP_LSB) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK) +#define SYNTH_SYNTH4_VCOCAP_OVR_MSB 25 +#define SYNTH_SYNTH4_VCOCAP_OVR_LSB 18 +#define SYNTH_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000 +#define SYNTH_SYNTH4_VCOCAP_OVR_GET(x) (((x) & SYNTH_SYNTH4_VCOCAP_OVR_MASK) >> SYNTH_SYNTH4_VCOCAP_OVR_LSB) +#define SYNTH_SYNTH4_VCOCAP_OVR_SET(x) (((x) << SYNTH_SYNTH4_VCOCAP_OVR_LSB) & SYNTH_SYNTH4_VCOCAP_OVR_MASK) +#define SYNTH_SYNTH4_VCOCAPPULLUP_MSB 17 +#define SYNTH_SYNTH4_VCOCAPPULLUP_LSB 17 +#define SYNTH_SYNTH4_VCOCAPPULLUP_MASK 0x00020000 +#define SYNTH_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK) >> SYNTH_SYNTH4_VCOCAPPULLUP_LSB) +#define SYNTH_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << SYNTH_SYNTH4_VCOCAPPULLUP_LSB) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK) +#define SYNTH_SYNTH4_REFDIVSEL_MSB 16 +#define SYNTH_SYNTH4_REFDIVSEL_LSB 15 +#define SYNTH_SYNTH4_REFDIVSEL_MASK 0x00018000 +#define SYNTH_SYNTH4_REFDIVSEL_GET(x) (((x) & SYNTH_SYNTH4_REFDIVSEL_MASK) >> SYNTH_SYNTH4_REFDIVSEL_LSB) +#define SYNTH_SYNTH4_REFDIVSEL_SET(x) (((x) << SYNTH_SYNTH4_REFDIVSEL_LSB) & SYNTH_SYNTH4_REFDIVSEL_MASK) +#define SYNTH_SYNTH4_PFDDELAY_MSB 14 +#define SYNTH_SYNTH4_PFDDELAY_LSB 14 +#define SYNTH_SYNTH4_PFDDELAY_MASK 0x00004000 +#define SYNTH_SYNTH4_PFDDELAY_GET(x) (((x) & SYNTH_SYNTH4_PFDDELAY_MASK) >> SYNTH_SYNTH4_PFDDELAY_LSB) +#define SYNTH_SYNTH4_PFDDELAY_SET(x) (((x) << SYNTH_SYNTH4_PFDDELAY_LSB) & SYNTH_SYNTH4_PFDDELAY_MASK) +#define SYNTH_SYNTH4_PFD_DISABLE_MSB 13 +#define SYNTH_SYNTH4_PFD_DISABLE_LSB 13 +#define SYNTH_SYNTH4_PFD_DISABLE_MASK 0x00002000 +#define SYNTH_SYNTH4_PFD_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_PFD_DISABLE_MASK) >> SYNTH_SYNTH4_PFD_DISABLE_LSB) +#define SYNTH_SYNTH4_PFD_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_PFD_DISABLE_LSB) & SYNTH_SYNTH4_PFD_DISABLE_MASK) +#define SYNTH_SYNTH4_PRESCSEL_MSB 12 +#define SYNTH_SYNTH4_PRESCSEL_LSB 11 +#define SYNTH_SYNTH4_PRESCSEL_MASK 0x00001800 +#define SYNTH_SYNTH4_PRESCSEL_GET(x) (((x) & SYNTH_SYNTH4_PRESCSEL_MASK) >> SYNTH_SYNTH4_PRESCSEL_LSB) +#define SYNTH_SYNTH4_PRESCSEL_SET(x) (((x) << SYNTH_SYNTH4_PRESCSEL_LSB) & SYNTH_SYNTH4_PRESCSEL_MASK) +#define SYNTH_SYNTH4_RESET_PRESC_MSB 10 +#define SYNTH_SYNTH4_RESET_PRESC_LSB 10 +#define SYNTH_SYNTH4_RESET_PRESC_MASK 0x00000400 +#define SYNTH_SYNTH4_RESET_PRESC_GET(x) (((x) & SYNTH_SYNTH4_RESET_PRESC_MASK) >> SYNTH_SYNTH4_RESET_PRESC_LSB) +#define SYNTH_SYNTH4_RESET_PRESC_SET(x) (((x) << SYNTH_SYNTH4_RESET_PRESC_LSB) & SYNTH_SYNTH4_RESET_PRESC_MASK) +#define SYNTH_SYNTH4_SDM_DISABLE_MSB 9 +#define SYNTH_SYNTH4_SDM_DISABLE_LSB 9 +#define SYNTH_SYNTH4_SDM_DISABLE_MASK 0x00000200 +#define SYNTH_SYNTH4_SDM_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_SDM_DISABLE_MASK) >> SYNTH_SYNTH4_SDM_DISABLE_LSB) +#define SYNTH_SYNTH4_SDM_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_SDM_DISABLE_LSB) & SYNTH_SYNTH4_SDM_DISABLE_MASK) +#define SYNTH_SYNTH4_SDM_MODE_MSB 8 +#define SYNTH_SYNTH4_SDM_MODE_LSB 8 +#define SYNTH_SYNTH4_SDM_MODE_MASK 0x00000100 +#define SYNTH_SYNTH4_SDM_MODE_GET(x) (((x) & SYNTH_SYNTH4_SDM_MODE_MASK) >> SYNTH_SYNTH4_SDM_MODE_LSB) +#define SYNTH_SYNTH4_SDM_MODE_SET(x) (((x) << SYNTH_SYNTH4_SDM_MODE_LSB) & SYNTH_SYNTH4_SDM_MODE_MASK) +#define SYNTH_SYNTH4_SDM_DITHER_MSB 7 +#define SYNTH_SYNTH4_SDM_DITHER_LSB 6 +#define SYNTH_SYNTH4_SDM_DITHER_MASK 0x000000c0 +#define SYNTH_SYNTH4_SDM_DITHER_GET(x) (((x) & SYNTH_SYNTH4_SDM_DITHER_MASK) >> SYNTH_SYNTH4_SDM_DITHER_LSB) +#define SYNTH_SYNTH4_SDM_DITHER_SET(x) (((x) << SYNTH_SYNTH4_SDM_DITHER_LSB) & SYNTH_SYNTH4_SDM_DITHER_MASK) +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MSB 5 +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB 5 +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020 +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK) >> SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB) +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK) +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MSB 4 +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB 4 +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK 0x00000010 +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_GET(x) (((x) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK) >> SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB) +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_SET(x) (((x) << SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK) +#define SYNTH_SYNTH4_SPARE_MISC_MSB 3 +#define SYNTH_SYNTH4_SPARE_MISC_LSB 2 +#define SYNTH_SYNTH4_SPARE_MISC_MASK 0x0000000c +#define SYNTH_SYNTH4_SPARE_MISC_GET(x) (((x) & SYNTH_SYNTH4_SPARE_MISC_MASK) >> SYNTH_SYNTH4_SPARE_MISC_LSB) +#define SYNTH_SYNTH4_SPARE_MISC_SET(x) (((x) << SYNTH_SYNTH4_SPARE_MISC_LSB) & SYNTH_SYNTH4_SPARE_MISC_MASK) +#define SYNTH_SYNTH4_LONGSHIFTSEL_MSB 1 +#define SYNTH_SYNTH4_LONGSHIFTSEL_LSB 1 +#define SYNTH_SYNTH4_LONGSHIFTSEL_MASK 0x00000002 +#define SYNTH_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK) >> SYNTH_SYNTH4_LONGSHIFTSEL_LSB) +#define SYNTH_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << SYNTH_SYNTH4_LONGSHIFTSEL_LSB) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK) +#define SYNTH_SYNTH4_FORCE_SHIFTREG_MSB 0 +#define SYNTH_SYNTH4_FORCE_SHIFTREG_LSB 0 +#define SYNTH_SYNTH4_FORCE_SHIFTREG_MASK 0x00000001 +#define SYNTH_SYNTH4_FORCE_SHIFTREG_GET(x) (((x) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK) >> SYNTH_SYNTH4_FORCE_SHIFTREG_LSB) +#define SYNTH_SYNTH4_FORCE_SHIFTREG_SET(x) (((x) << SYNTH_SYNTH4_FORCE_SHIFTREG_LSB) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK) + +#define SYNTH_SYNTH5_ADDRESS 0x00000010 +#define SYNTH_SYNTH5_OFFSET 0x00000010 +#define SYNTH_SYNTH5_LOOP_IP0_MSB 31 +#define SYNTH_SYNTH5_LOOP_IP0_LSB 28 +#define SYNTH_SYNTH5_LOOP_IP0_MASK 0xf0000000 +#define SYNTH_SYNTH5_LOOP_IP0_GET(x) (((x) & SYNTH_SYNTH5_LOOP_IP0_MASK) >> SYNTH_SYNTH5_LOOP_IP0_LSB) +#define SYNTH_SYNTH5_LOOP_IP0_SET(x) (((x) << SYNTH_SYNTH5_LOOP_IP0_LSB) & SYNTH_SYNTH5_LOOP_IP0_MASK) +#define SYNTH_SYNTH5_SLOPE_IP_MSB 27 +#define SYNTH_SYNTH5_SLOPE_IP_LSB 25 +#define SYNTH_SYNTH5_SLOPE_IP_MASK 0x0e000000 +#define SYNTH_SYNTH5_SLOPE_IP_GET(x) (((x) & SYNTH_SYNTH5_SLOPE_IP_MASK) >> SYNTH_SYNTH5_SLOPE_IP_LSB) +#define SYNTH_SYNTH5_SLOPE_IP_SET(x) (((x) << SYNTH_SYNTH5_SLOPE_IP_LSB) & SYNTH_SYNTH5_SLOPE_IP_MASK) +#define SYNTH_SYNTH5_CPBIAS_MSB 24 +#define SYNTH_SYNTH5_CPBIAS_LSB 23 +#define SYNTH_SYNTH5_CPBIAS_MASK 0x01800000 +#define SYNTH_SYNTH5_CPBIAS_GET(x) (((x) & SYNTH_SYNTH5_CPBIAS_MASK) >> SYNTH_SYNTH5_CPBIAS_LSB) +#define SYNTH_SYNTH5_CPBIAS_SET(x) (((x) << SYNTH_SYNTH5_CPBIAS_LSB) & SYNTH_SYNTH5_CPBIAS_MASK) +#define SYNTH_SYNTH5_CPSTEERING_EN_MSB 22 +#define SYNTH_SYNTH5_CPSTEERING_EN_LSB 22 +#define SYNTH_SYNTH5_CPSTEERING_EN_MASK 0x00400000 +#define SYNTH_SYNTH5_CPSTEERING_EN_GET(x) (((x) & SYNTH_SYNTH5_CPSTEERING_EN_MASK) >> SYNTH_SYNTH5_CPSTEERING_EN_LSB) +#define SYNTH_SYNTH5_CPSTEERING_EN_SET(x) (((x) << SYNTH_SYNTH5_CPSTEERING_EN_LSB) & SYNTH_SYNTH5_CPSTEERING_EN_MASK) +#define SYNTH_SYNTH5_CPLOWLK_MSB 21 +#define SYNTH_SYNTH5_CPLOWLK_LSB 21 +#define SYNTH_SYNTH5_CPLOWLK_MASK 0x00200000 +#define SYNTH_SYNTH5_CPLOWLK_GET(x) (((x) & SYNTH_SYNTH5_CPLOWLK_MASK) >> SYNTH_SYNTH5_CPLOWLK_LSB) +#define SYNTH_SYNTH5_CPLOWLK_SET(x) (((x) << SYNTH_SYNTH5_CPLOWLK_LSB) & SYNTH_SYNTH5_CPLOWLK_MASK) +#define SYNTH_SYNTH5_LOOPLEAKCUR_MSB 20 +#define SYNTH_SYNTH5_LOOPLEAKCUR_LSB 17 +#define SYNTH_SYNTH5_LOOPLEAKCUR_MASK 0x001e0000 +#define SYNTH_SYNTH5_LOOPLEAKCUR_GET(x) (((x) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK) >> SYNTH_SYNTH5_LOOPLEAKCUR_LSB) +#define SYNTH_SYNTH5_LOOPLEAKCUR_SET(x) (((x) << SYNTH_SYNTH5_LOOPLEAKCUR_LSB) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK) +#define SYNTH_SYNTH5_CAPRANGE1_MSB 16 +#define SYNTH_SYNTH5_CAPRANGE1_LSB 13 +#define SYNTH_SYNTH5_CAPRANGE1_MASK 0x0001e000 +#define SYNTH_SYNTH5_CAPRANGE1_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE1_MASK) >> SYNTH_SYNTH5_CAPRANGE1_LSB) +#define SYNTH_SYNTH5_CAPRANGE1_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE1_LSB) & SYNTH_SYNTH5_CAPRANGE1_MASK) +#define SYNTH_SYNTH5_CAPRANGE2_MSB 12 +#define SYNTH_SYNTH5_CAPRANGE2_LSB 9 +#define SYNTH_SYNTH5_CAPRANGE2_MASK 0x00001e00 +#define SYNTH_SYNTH5_CAPRANGE2_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE2_MASK) >> SYNTH_SYNTH5_CAPRANGE2_LSB) +#define SYNTH_SYNTH5_CAPRANGE2_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE2_LSB) & SYNTH_SYNTH5_CAPRANGE2_MASK) +#define SYNTH_SYNTH5_CAPRANGE3_MSB 8 +#define SYNTH_SYNTH5_CAPRANGE3_LSB 5 +#define SYNTH_SYNTH5_CAPRANGE3_MASK 0x000001e0 +#define SYNTH_SYNTH5_CAPRANGE3_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE3_MASK) >> SYNTH_SYNTH5_CAPRANGE3_LSB) +#define SYNTH_SYNTH5_CAPRANGE3_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE3_LSB) & SYNTH_SYNTH5_CAPRANGE3_MASK) +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MSB 4 +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB 4 +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK 0x00000010 +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB) +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK) +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MSB 3 +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB 2 +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK 0x0000000c +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_GET(x) (((x) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK) >> SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB) +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_SET(x) (((x) << SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK) +#define SYNTH_SYNTH5_SPARE_MSB 1 +#define SYNTH_SYNTH5_SPARE_LSB 0 +#define SYNTH_SYNTH5_SPARE_MASK 0x00000003 +#define SYNTH_SYNTH5_SPARE_GET(x) (((x) & SYNTH_SYNTH5_SPARE_MASK) >> SYNTH_SYNTH5_SPARE_LSB) +#define SYNTH_SYNTH5_SPARE_SET(x) (((x) << SYNTH_SYNTH5_SPARE_LSB) & SYNTH_SYNTH5_SPARE_MASK) + +#define SYNTH_SYNTH6_ADDRESS 0x00000014 +#define SYNTH_SYNTH6_OFFSET 0x00000014 +#define SYNTH_SYNTH6_IRCP_MSB 31 +#define SYNTH_SYNTH6_IRCP_LSB 29 +#define SYNTH_SYNTH6_IRCP_MASK 0xe0000000 +#define SYNTH_SYNTH6_IRCP_GET(x) (((x) & SYNTH_SYNTH6_IRCP_MASK) >> SYNTH_SYNTH6_IRCP_LSB) +#define SYNTH_SYNTH6_IRCP_SET(x) (((x) << SYNTH_SYNTH6_IRCP_LSB) & SYNTH_SYNTH6_IRCP_MASK) +#define SYNTH_SYNTH6_IRVCMON_MSB 28 +#define SYNTH_SYNTH6_IRVCMON_LSB 26 +#define SYNTH_SYNTH6_IRVCMON_MASK 0x1c000000 +#define SYNTH_SYNTH6_IRVCMON_GET(x) (((x) & SYNTH_SYNTH6_IRVCMON_MASK) >> SYNTH_SYNTH6_IRVCMON_LSB) +#define SYNTH_SYNTH6_IRVCMON_SET(x) (((x) << SYNTH_SYNTH6_IRVCMON_LSB) & SYNTH_SYNTH6_IRVCMON_MASK) +#define SYNTH_SYNTH6_IRSPARE_MSB 25 +#define SYNTH_SYNTH6_IRSPARE_LSB 23 +#define SYNTH_SYNTH6_IRSPARE_MASK 0x03800000 +#define SYNTH_SYNTH6_IRSPARE_GET(x) (((x) & SYNTH_SYNTH6_IRSPARE_MASK) >> SYNTH_SYNTH6_IRSPARE_LSB) +#define SYNTH_SYNTH6_IRSPARE_SET(x) (((x) << SYNTH_SYNTH6_IRSPARE_LSB) & SYNTH_SYNTH6_IRSPARE_MASK) +#define SYNTH_SYNTH6_ICPRESC_MSB 22 +#define SYNTH_SYNTH6_ICPRESC_LSB 20 +#define SYNTH_SYNTH6_ICPRESC_MASK 0x00700000 +#define SYNTH_SYNTH6_ICPRESC_GET(x) (((x) & SYNTH_SYNTH6_ICPRESC_MASK) >> SYNTH_SYNTH6_ICPRESC_LSB) +#define SYNTH_SYNTH6_ICPRESC_SET(x) (((x) << SYNTH_SYNTH6_ICPRESC_LSB) & SYNTH_SYNTH6_ICPRESC_MASK) +#define SYNTH_SYNTH6_ICLODIV_MSB 19 +#define SYNTH_SYNTH6_ICLODIV_LSB 17 +#define SYNTH_SYNTH6_ICLODIV_MASK 0x000e0000 +#define SYNTH_SYNTH6_ICLODIV_GET(x) (((x) & SYNTH_SYNTH6_ICLODIV_MASK) >> SYNTH_SYNTH6_ICLODIV_LSB) +#define SYNTH_SYNTH6_ICLODIV_SET(x) (((x) << SYNTH_SYNTH6_ICLODIV_LSB) & SYNTH_SYNTH6_ICLODIV_MASK) +#define SYNTH_SYNTH6_ICLOMIX_MSB 16 +#define SYNTH_SYNTH6_ICLOMIX_LSB 14 +#define SYNTH_SYNTH6_ICLOMIX_MASK 0x0001c000 +#define SYNTH_SYNTH6_ICLOMIX_GET(x) (((x) & SYNTH_SYNTH6_ICLOMIX_MASK) >> SYNTH_SYNTH6_ICLOMIX_LSB) +#define SYNTH_SYNTH6_ICLOMIX_SET(x) (((x) << SYNTH_SYNTH6_ICLOMIX_LSB) & SYNTH_SYNTH6_ICLOMIX_MASK) +#define SYNTH_SYNTH6_ICSPAREA_MSB 13 +#define SYNTH_SYNTH6_ICSPAREA_LSB 11 +#define SYNTH_SYNTH6_ICSPAREA_MASK 0x00003800 +#define SYNTH_SYNTH6_ICSPAREA_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREA_MASK) >> SYNTH_SYNTH6_ICSPAREA_LSB) +#define SYNTH_SYNTH6_ICSPAREA_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREA_LSB) & SYNTH_SYNTH6_ICSPAREA_MASK) +#define SYNTH_SYNTH6_ICSPAREB_MSB 10 +#define SYNTH_SYNTH6_ICSPAREB_LSB 8 +#define SYNTH_SYNTH6_ICSPAREB_MASK 0x00000700 +#define SYNTH_SYNTH6_ICSPAREB_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREB_MASK) >> SYNTH_SYNTH6_ICSPAREB_LSB) +#define SYNTH_SYNTH6_ICSPAREB_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREB_LSB) & SYNTH_SYNTH6_ICSPAREB_MASK) +#define SYNTH_SYNTH6_ICVCO_MSB 7 +#define SYNTH_SYNTH6_ICVCO_LSB 5 +#define SYNTH_SYNTH6_ICVCO_MASK 0x000000e0 +#define SYNTH_SYNTH6_ICVCO_GET(x) (((x) & SYNTH_SYNTH6_ICVCO_MASK) >> SYNTH_SYNTH6_ICVCO_LSB) +#define SYNTH_SYNTH6_ICVCO_SET(x) (((x) << SYNTH_SYNTH6_ICVCO_LSB) & SYNTH_SYNTH6_ICVCO_MASK) +#define SYNTH_SYNTH6_VCOBUFBIAS_MSB 4 +#define SYNTH_SYNTH6_VCOBUFBIAS_LSB 3 +#define SYNTH_SYNTH6_VCOBUFBIAS_MASK 0x00000018 +#define SYNTH_SYNTH6_VCOBUFBIAS_GET(x) (((x) & SYNTH_SYNTH6_VCOBUFBIAS_MASK) >> SYNTH_SYNTH6_VCOBUFBIAS_LSB) +#define SYNTH_SYNTH6_VCOBUFBIAS_SET(x) (((x) << SYNTH_SYNTH6_VCOBUFBIAS_LSB) & SYNTH_SYNTH6_VCOBUFBIAS_MASK) +#define SYNTH_SYNTH6_SPARE_BIAS_MSB 2 +#define SYNTH_SYNTH6_SPARE_BIAS_LSB 0 +#define SYNTH_SYNTH6_SPARE_BIAS_MASK 0x00000007 +#define SYNTH_SYNTH6_SPARE_BIAS_GET(x) (((x) & SYNTH_SYNTH6_SPARE_BIAS_MASK) >> SYNTH_SYNTH6_SPARE_BIAS_LSB) +#define SYNTH_SYNTH6_SPARE_BIAS_SET(x) (((x) << SYNTH_SYNTH6_SPARE_BIAS_LSB) & SYNTH_SYNTH6_SPARE_BIAS_MASK) + +#define SYNTH_SYNTH7_ADDRESS 0x00000018 +#define SYNTH_SYNTH7_OFFSET 0x00000018 +#define SYNTH_SYNTH7_SYNTH_ON_MSB 31 +#define SYNTH_SYNTH7_SYNTH_ON_LSB 31 +#define SYNTH_SYNTH7_SYNTH_ON_MASK 0x80000000 +#define SYNTH_SYNTH7_SYNTH_ON_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_ON_MASK) >> SYNTH_SYNTH7_SYNTH_ON_LSB) +#define SYNTH_SYNTH7_SYNTH_ON_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_ON_LSB) & SYNTH_SYNTH7_SYNTH_ON_MASK) +#define SYNTH_SYNTH7_SYNTH_SM_STATE_MSB 30 +#define SYNTH_SYNTH7_SYNTH_SM_STATE_LSB 27 +#define SYNTH_SYNTH7_SYNTH_SM_STATE_MASK 0x78000000 +#define SYNTH_SYNTH7_SYNTH_SM_STATE_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK) >> SYNTH_SYNTH7_SYNTH_SM_STATE_LSB) +#define SYNTH_SYNTH7_SYNTH_SM_STATE_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_SM_STATE_LSB) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK) +#define SYNTH_SYNTH7_CAP_SEARCH_MSB 26 +#define SYNTH_SYNTH7_CAP_SEARCH_LSB 26 +#define SYNTH_SYNTH7_CAP_SEARCH_MASK 0x04000000 +#define SYNTH_SYNTH7_CAP_SEARCH_GET(x) (((x) & SYNTH_SYNTH7_CAP_SEARCH_MASK) >> SYNTH_SYNTH7_CAP_SEARCH_LSB) +#define SYNTH_SYNTH7_CAP_SEARCH_SET(x) (((x) << SYNTH_SYNTH7_CAP_SEARCH_LSB) & SYNTH_SYNTH7_CAP_SEARCH_MASK) +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MSB 25 +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB 25 +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK 0x02000000 +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK) >> SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB) +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK) +#define SYNTH_SYNTH7_PIN_VC_MSB 24 +#define SYNTH_SYNTH7_PIN_VC_LSB 24 +#define SYNTH_SYNTH7_PIN_VC_MASK 0x01000000 +#define SYNTH_SYNTH7_PIN_VC_GET(x) (((x) & SYNTH_SYNTH7_PIN_VC_MASK) >> SYNTH_SYNTH7_PIN_VC_LSB) +#define SYNTH_SYNTH7_PIN_VC_SET(x) (((x) << SYNTH_SYNTH7_PIN_VC_LSB) & SYNTH_SYNTH7_PIN_VC_MASK) +#define SYNTH_SYNTH7_VCO_CAP_ST_MSB 23 +#define SYNTH_SYNTH7_VCO_CAP_ST_LSB 16 +#define SYNTH_SYNTH7_VCO_CAP_ST_MASK 0x00ff0000 +#define SYNTH_SYNTH7_VCO_CAP_ST_GET(x) (((x) & SYNTH_SYNTH7_VCO_CAP_ST_MASK) >> SYNTH_SYNTH7_VCO_CAP_ST_LSB) +#define SYNTH_SYNTH7_VCO_CAP_ST_SET(x) (((x) << SYNTH_SYNTH7_VCO_CAP_ST_LSB) & SYNTH_SYNTH7_VCO_CAP_ST_MASK) +#define SYNTH_SYNTH7_SHORT_R_MSB 15 +#define SYNTH_SYNTH7_SHORT_R_LSB 15 +#define SYNTH_SYNTH7_SHORT_R_MASK 0x00008000 +#define SYNTH_SYNTH7_SHORT_R_GET(x) (((x) & SYNTH_SYNTH7_SHORT_R_MASK) >> SYNTH_SYNTH7_SHORT_R_LSB) +#define SYNTH_SYNTH7_SHORT_R_SET(x) (((x) << SYNTH_SYNTH7_SHORT_R_LSB) & SYNTH_SYNTH7_SHORT_R_MASK) +#define SYNTH_SYNTH7_RESET_RFD_MSB 14 +#define SYNTH_SYNTH7_RESET_RFD_LSB 14 +#define SYNTH_SYNTH7_RESET_RFD_MASK 0x00004000 +#define SYNTH_SYNTH7_RESET_RFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_RFD_MASK) >> SYNTH_SYNTH7_RESET_RFD_LSB) +#define SYNTH_SYNTH7_RESET_RFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_RFD_LSB) & SYNTH_SYNTH7_RESET_RFD_MASK) +#define SYNTH_SYNTH7_RESET_PFD_MSB 13 +#define SYNTH_SYNTH7_RESET_PFD_LSB 13 +#define SYNTH_SYNTH7_RESET_PFD_MASK 0x00002000 +#define SYNTH_SYNTH7_RESET_PFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_PFD_MASK) >> SYNTH_SYNTH7_RESET_PFD_LSB) +#define SYNTH_SYNTH7_RESET_PFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_PFD_LSB) & SYNTH_SYNTH7_RESET_PFD_MASK) +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MSB 12 +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB 12 +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK 0x00001000 +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_GET(x) (((x) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK) >> SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB) +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_SET(x) (((x) << SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK) +#define SYNTH_SYNTH7_RESET_SDM_B_MSB 11 +#define SYNTH_SYNTH7_RESET_SDM_B_LSB 11 +#define SYNTH_SYNTH7_RESET_SDM_B_MASK 0x00000800 +#define SYNTH_SYNTH7_RESET_SDM_B_GET(x) (((x) & SYNTH_SYNTH7_RESET_SDM_B_MASK) >> SYNTH_SYNTH7_RESET_SDM_B_LSB) +#define SYNTH_SYNTH7_RESET_SDM_B_SET(x) (((x) << SYNTH_SYNTH7_RESET_SDM_B_LSB) & SYNTH_SYNTH7_RESET_SDM_B_MASK) +#define SYNTH_SYNTH7_VC2HIGH_MSB 10 +#define SYNTH_SYNTH7_VC2HIGH_LSB 10 +#define SYNTH_SYNTH7_VC2HIGH_MASK 0x00000400 +#define SYNTH_SYNTH7_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH7_VC2HIGH_MASK) >> SYNTH_SYNTH7_VC2HIGH_LSB) +#define SYNTH_SYNTH7_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH7_VC2HIGH_LSB) & SYNTH_SYNTH7_VC2HIGH_MASK) +#define SYNTH_SYNTH7_VC2LOW_MSB 9 +#define SYNTH_SYNTH7_VC2LOW_LSB 9 +#define SYNTH_SYNTH7_VC2LOW_MASK 0x00000200 +#define SYNTH_SYNTH7_VC2LOW_GET(x) (((x) & SYNTH_SYNTH7_VC2LOW_MASK) >> SYNTH_SYNTH7_VC2LOW_LSB) +#define SYNTH_SYNTH7_VC2LOW_SET(x) (((x) << SYNTH_SYNTH7_VC2LOW_LSB) & SYNTH_SYNTH7_VC2LOW_MASK) +#define SYNTH_SYNTH7_LOOP_IP_MSB 8 +#define SYNTH_SYNTH7_LOOP_IP_LSB 5 +#define SYNTH_SYNTH7_LOOP_IP_MASK 0x000001e0 +#define SYNTH_SYNTH7_LOOP_IP_GET(x) (((x) & SYNTH_SYNTH7_LOOP_IP_MASK) >> SYNTH_SYNTH7_LOOP_IP_LSB) +#define SYNTH_SYNTH7_LOOP_IP_SET(x) (((x) << SYNTH_SYNTH7_LOOP_IP_LSB) & SYNTH_SYNTH7_LOOP_IP_MASK) +#define SYNTH_SYNTH7_LOBUF5GTUNE_MSB 4 +#define SYNTH_SYNTH7_LOBUF5GTUNE_LSB 3 +#define SYNTH_SYNTH7_LOBUF5GTUNE_MASK 0x00000018 +#define SYNTH_SYNTH7_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH7_LOBUF5GTUNE_LSB) +#define SYNTH_SYNTH7_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH7_LOBUF5GTUNE_LSB) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK) +#define SYNTH_SYNTH7_SPARE_READ_MSB 2 +#define SYNTH_SYNTH7_SPARE_READ_LSB 0 +#define SYNTH_SYNTH7_SPARE_READ_MASK 0x00000007 +#define SYNTH_SYNTH7_SPARE_READ_GET(x) (((x) & SYNTH_SYNTH7_SPARE_READ_MASK) >> SYNTH_SYNTH7_SPARE_READ_LSB) +#define SYNTH_SYNTH7_SPARE_READ_SET(x) (((x) << SYNTH_SYNTH7_SPARE_READ_LSB) & SYNTH_SYNTH7_SPARE_READ_MASK) + +#define SYNTH_SYNTH8_ADDRESS 0x0000001c +#define SYNTH_SYNTH8_OFFSET 0x0000001c +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MSB 31 +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB 31 +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK 0x80000000 +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_GET(x) (((x) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK) >> SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB) +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_SET(x) (((x) << SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK) +#define SYNTH_SYNTH8_FRACMODE_MSB 30 +#define SYNTH_SYNTH8_FRACMODE_LSB 30 +#define SYNTH_SYNTH8_FRACMODE_MASK 0x40000000 +#define SYNTH_SYNTH8_FRACMODE_GET(x) (((x) & SYNTH_SYNTH8_FRACMODE_MASK) >> SYNTH_SYNTH8_FRACMODE_LSB) +#define SYNTH_SYNTH8_FRACMODE_SET(x) (((x) << SYNTH_SYNTH8_FRACMODE_LSB) & SYNTH_SYNTH8_FRACMODE_MASK) +#define SYNTH_SYNTH8_AMODEREFSEL_MSB 29 +#define SYNTH_SYNTH8_AMODEREFSEL_LSB 28 +#define SYNTH_SYNTH8_AMODEREFSEL_MASK 0x30000000 +#define SYNTH_SYNTH8_AMODEREFSEL_GET(x) (((x) & SYNTH_SYNTH8_AMODEREFSEL_MASK) >> SYNTH_SYNTH8_AMODEREFSEL_LSB) +#define SYNTH_SYNTH8_AMODEREFSEL_SET(x) (((x) << SYNTH_SYNTH8_AMODEREFSEL_LSB) & SYNTH_SYNTH8_AMODEREFSEL_MASK) +#define SYNTH_SYNTH8_SPARE_MSB 27 +#define SYNTH_SYNTH8_SPARE_LSB 27 +#define SYNTH_SYNTH8_SPARE_MASK 0x08000000 +#define SYNTH_SYNTH8_SPARE_GET(x) (((x) & SYNTH_SYNTH8_SPARE_MASK) >> SYNTH_SYNTH8_SPARE_LSB) +#define SYNTH_SYNTH8_SPARE_SET(x) (((x) << SYNTH_SYNTH8_SPARE_LSB) & SYNTH_SYNTH8_SPARE_MASK) +#define SYNTH_SYNTH8_CHANSEL_MSB 26 +#define SYNTH_SYNTH8_CHANSEL_LSB 18 +#define SYNTH_SYNTH8_CHANSEL_MASK 0x07fc0000 +#define SYNTH_SYNTH8_CHANSEL_GET(x) (((x) & SYNTH_SYNTH8_CHANSEL_MASK) >> SYNTH_SYNTH8_CHANSEL_LSB) +#define SYNTH_SYNTH8_CHANSEL_SET(x) (((x) << SYNTH_SYNTH8_CHANSEL_LSB) & SYNTH_SYNTH8_CHANSEL_MASK) +#define SYNTH_SYNTH8_CHANFRAC_MSB 17 +#define SYNTH_SYNTH8_CHANFRAC_LSB 1 +#define SYNTH_SYNTH8_CHANFRAC_MASK 0x0003fffe +#define SYNTH_SYNTH8_CHANFRAC_GET(x) (((x) & SYNTH_SYNTH8_CHANFRAC_MASK) >> SYNTH_SYNTH8_CHANFRAC_LSB) +#define SYNTH_SYNTH8_CHANFRAC_SET(x) (((x) << SYNTH_SYNTH8_CHANFRAC_LSB) & SYNTH_SYNTH8_CHANFRAC_MASK) +#define SYNTH_SYNTH8_FORCE_FRACLSB_MSB 0 +#define SYNTH_SYNTH8_FORCE_FRACLSB_LSB 0 +#define SYNTH_SYNTH8_FORCE_FRACLSB_MASK 0x00000001 +#define SYNTH_SYNTH8_FORCE_FRACLSB_GET(x) (((x) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK) >> SYNTH_SYNTH8_FORCE_FRACLSB_LSB) +#define SYNTH_SYNTH8_FORCE_FRACLSB_SET(x) (((x) << SYNTH_SYNTH8_FORCE_FRACLSB_LSB) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK) + +#define RF5G_RF5G1_ADDRESS 0x00000020 +#define RF5G_RF5G1_OFFSET 0x00000020 +#define RF5G_RF5G1_PDTXLO5_MSB 31 +#define RF5G_RF5G1_PDTXLO5_LSB 31 +#define RF5G_RF5G1_PDTXLO5_MASK 0x80000000 +#define RF5G_RF5G1_PDTXLO5_GET(x) (((x) & RF5G_RF5G1_PDTXLO5_MASK) >> RF5G_RF5G1_PDTXLO5_LSB) +#define RF5G_RF5G1_PDTXLO5_SET(x) (((x) << RF5G_RF5G1_PDTXLO5_LSB) & RF5G_RF5G1_PDTXLO5_MASK) +#define RF5G_RF5G1_PDTXMIX5_MSB 30 +#define RF5G_RF5G1_PDTXMIX5_LSB 30 +#define RF5G_RF5G1_PDTXMIX5_MASK 0x40000000 +#define RF5G_RF5G1_PDTXMIX5_GET(x) (((x) & RF5G_RF5G1_PDTXMIX5_MASK) >> RF5G_RF5G1_PDTXMIX5_LSB) +#define RF5G_RF5G1_PDTXMIX5_SET(x) (((x) << RF5G_RF5G1_PDTXMIX5_LSB) & RF5G_RF5G1_PDTXMIX5_MASK) +#define RF5G_RF5G1_PDTXBUF5_MSB 29 +#define RF5G_RF5G1_PDTXBUF5_LSB 29 +#define RF5G_RF5G1_PDTXBUF5_MASK 0x20000000 +#define RF5G_RF5G1_PDTXBUF5_GET(x) (((x) & RF5G_RF5G1_PDTXBUF5_MASK) >> RF5G_RF5G1_PDTXBUF5_LSB) +#define RF5G_RF5G1_PDTXBUF5_SET(x) (((x) << RF5G_RF5G1_PDTXBUF5_LSB) & RF5G_RF5G1_PDTXBUF5_MASK) +#define RF5G_RF5G1_PDPADRV5_MSB 28 +#define RF5G_RF5G1_PDPADRV5_LSB 28 +#define RF5G_RF5G1_PDPADRV5_MASK 0x10000000 +#define RF5G_RF5G1_PDPADRV5_GET(x) (((x) & RF5G_RF5G1_PDPADRV5_MASK) >> RF5G_RF5G1_PDPADRV5_LSB) +#define RF5G_RF5G1_PDPADRV5_SET(x) (((x) << RF5G_RF5G1_PDPADRV5_LSB) & RF5G_RF5G1_PDPADRV5_MASK) +#define RF5G_RF5G1_PDPAOUT5_MSB 27 +#define RF5G_RF5G1_PDPAOUT5_LSB 27 +#define RF5G_RF5G1_PDPAOUT5_MASK 0x08000000 +#define RF5G_RF5G1_PDPAOUT5_GET(x) (((x) & RF5G_RF5G1_PDPAOUT5_MASK) >> RF5G_RF5G1_PDPAOUT5_LSB) +#define RF5G_RF5G1_PDPAOUT5_SET(x) (((x) << RF5G_RF5G1_PDPAOUT5_LSB) & RF5G_RF5G1_PDPAOUT5_MASK) +#define RF5G_RF5G1_TUNE_PADRV5_MSB 26 +#define RF5G_RF5G1_TUNE_PADRV5_LSB 24 +#define RF5G_RF5G1_TUNE_PADRV5_MASK 0x07000000 +#define RF5G_RF5G1_TUNE_PADRV5_GET(x) (((x) & RF5G_RF5G1_TUNE_PADRV5_MASK) >> RF5G_RF5G1_TUNE_PADRV5_LSB) +#define RF5G_RF5G1_TUNE_PADRV5_SET(x) (((x) << RF5G_RF5G1_TUNE_PADRV5_LSB) & RF5G_RF5G1_TUNE_PADRV5_MASK) +#define RF5G_RF5G1_PWDTXPKD_MSB 23 +#define RF5G_RF5G1_PWDTXPKD_LSB 21 +#define RF5G_RF5G1_PWDTXPKD_MASK 0x00e00000 +#define RF5G_RF5G1_PWDTXPKD_GET(x) (((x) & RF5G_RF5G1_PWDTXPKD_MASK) >> RF5G_RF5G1_PWDTXPKD_LSB) +#define RF5G_RF5G1_PWDTXPKD_SET(x) (((x) << RF5G_RF5G1_PWDTXPKD_LSB) & RF5G_RF5G1_PWDTXPKD_MASK) +#define RF5G_RF5G1_DB5_MSB 20 +#define RF5G_RF5G1_DB5_LSB 18 +#define RF5G_RF5G1_DB5_MASK 0x001c0000 +#define RF5G_RF5G1_DB5_GET(x) (((x) & RF5G_RF5G1_DB5_MASK) >> RF5G_RF5G1_DB5_LSB) +#define RF5G_RF5G1_DB5_SET(x) (((x) << RF5G_RF5G1_DB5_LSB) & RF5G_RF5G1_DB5_MASK) +#define RF5G_RF5G1_OB5_MSB 17 +#define RF5G_RF5G1_OB5_LSB 15 +#define RF5G_RF5G1_OB5_MASK 0x00038000 +#define RF5G_RF5G1_OB5_GET(x) (((x) & RF5G_RF5G1_OB5_MASK) >> RF5G_RF5G1_OB5_LSB) +#define RF5G_RF5G1_OB5_SET(x) (((x) << RF5G_RF5G1_OB5_LSB) & RF5G_RF5G1_OB5_MASK) +#define RF5G_RF5G1_TX5_ATB_SEL_MSB 14 +#define RF5G_RF5G1_TX5_ATB_SEL_LSB 12 +#define RF5G_RF5G1_TX5_ATB_SEL_MASK 0x00007000 +#define RF5G_RF5G1_TX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_TX5_ATB_SEL_MASK) >> RF5G_RF5G1_TX5_ATB_SEL_LSB) +#define RF5G_RF5G1_TX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_TX5_ATB_SEL_LSB) & RF5G_RF5G1_TX5_ATB_SEL_MASK) +#define RF5G_RF5G1_PDLO5DIV_MSB 11 +#define RF5G_RF5G1_PDLO5DIV_LSB 11 +#define RF5G_RF5G1_PDLO5DIV_MASK 0x00000800 +#define RF5G_RF5G1_PDLO5DIV_GET(x) (((x) & RF5G_RF5G1_PDLO5DIV_MASK) >> RF5G_RF5G1_PDLO5DIV_LSB) +#define RF5G_RF5G1_PDLO5DIV_SET(x) (((x) << RF5G_RF5G1_PDLO5DIV_LSB) & RF5G_RF5G1_PDLO5DIV_MASK) +#define RF5G_RF5G1_PDLO5MIX_MSB 10 +#define RF5G_RF5G1_PDLO5MIX_LSB 10 +#define RF5G_RF5G1_PDLO5MIX_MASK 0x00000400 +#define RF5G_RF5G1_PDLO5MIX_GET(x) (((x) & RF5G_RF5G1_PDLO5MIX_MASK) >> RF5G_RF5G1_PDLO5MIX_LSB) +#define RF5G_RF5G1_PDLO5MIX_SET(x) (((x) << RF5G_RF5G1_PDLO5MIX_LSB) & RF5G_RF5G1_PDLO5MIX_MASK) +#define RF5G_RF5G1_PDQBUF5_MSB 9 +#define RF5G_RF5G1_PDQBUF5_LSB 9 +#define RF5G_RF5G1_PDQBUF5_MASK 0x00000200 +#define RF5G_RF5G1_PDQBUF5_GET(x) (((x) & RF5G_RF5G1_PDQBUF5_MASK) >> RF5G_RF5G1_PDQBUF5_LSB) +#define RF5G_RF5G1_PDQBUF5_SET(x) (((x) << RF5G_RF5G1_PDQBUF5_LSB) & RF5G_RF5G1_PDQBUF5_MASK) +#define RF5G_RF5G1_PDLO5AGC_MSB 8 +#define RF5G_RF5G1_PDLO5AGC_LSB 8 +#define RF5G_RF5G1_PDLO5AGC_MASK 0x00000100 +#define RF5G_RF5G1_PDLO5AGC_GET(x) (((x) & RF5G_RF5G1_PDLO5AGC_MASK) >> RF5G_RF5G1_PDLO5AGC_LSB) +#define RF5G_RF5G1_PDLO5AGC_SET(x) (((x) << RF5G_RF5G1_PDLO5AGC_LSB) & RF5G_RF5G1_PDLO5AGC_MASK) +#define RF5G_RF5G1_PDREGLO5_MSB 7 +#define RF5G_RF5G1_PDREGLO5_LSB 7 +#define RF5G_RF5G1_PDREGLO5_MASK 0x00000080 +#define RF5G_RF5G1_PDREGLO5_GET(x) (((x) & RF5G_RF5G1_PDREGLO5_MASK) >> RF5G_RF5G1_PDREGLO5_LSB) +#define RF5G_RF5G1_PDREGLO5_SET(x) (((x) << RF5G_RF5G1_PDREGLO5_LSB) & RF5G_RF5G1_PDREGLO5_MASK) +#define RF5G_RF5G1_LO5_ATB_SEL_MSB 6 +#define RF5G_RF5G1_LO5_ATB_SEL_LSB 4 +#define RF5G_RF5G1_LO5_ATB_SEL_MASK 0x00000070 +#define RF5G_RF5G1_LO5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_LO5_ATB_SEL_MASK) >> RF5G_RF5G1_LO5_ATB_SEL_LSB) +#define RF5G_RF5G1_LO5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_LO5_ATB_SEL_LSB) & RF5G_RF5G1_LO5_ATB_SEL_MASK) +#define RF5G_RF5G1_LO5CONTROL_MSB 3 +#define RF5G_RF5G1_LO5CONTROL_LSB 3 +#define RF5G_RF5G1_LO5CONTROL_MASK 0x00000008 +#define RF5G_RF5G1_LO5CONTROL_GET(x) (((x) & RF5G_RF5G1_LO5CONTROL_MASK) >> RF5G_RF5G1_LO5CONTROL_LSB) +#define RF5G_RF5G1_LO5CONTROL_SET(x) (((x) << RF5G_RF5G1_LO5CONTROL_LSB) & RF5G_RF5G1_LO5CONTROL_MASK) +#define RF5G_RF5G1_REGLO_BYPASS5_MSB 2 +#define RF5G_RF5G1_REGLO_BYPASS5_LSB 2 +#define RF5G_RF5G1_REGLO_BYPASS5_MASK 0x00000004 +#define RF5G_RF5G1_REGLO_BYPASS5_GET(x) (((x) & RF5G_RF5G1_REGLO_BYPASS5_MASK) >> RF5G_RF5G1_REGLO_BYPASS5_LSB) +#define RF5G_RF5G1_REGLO_BYPASS5_SET(x) (((x) << RF5G_RF5G1_REGLO_BYPASS5_LSB) & RF5G_RF5G1_REGLO_BYPASS5_MASK) +#define RF5G_RF5G1_SPARE_MSB 1 +#define RF5G_RF5G1_SPARE_LSB 0 +#define RF5G_RF5G1_SPARE_MASK 0x00000003 +#define RF5G_RF5G1_SPARE_GET(x) (((x) & RF5G_RF5G1_SPARE_MASK) >> RF5G_RF5G1_SPARE_LSB) +#define RF5G_RF5G1_SPARE_SET(x) (((x) << RF5G_RF5G1_SPARE_LSB) & RF5G_RF5G1_SPARE_MASK) + +#define RF5G_RF5G2_ADDRESS 0x00000024 +#define RF5G_RF5G2_OFFSET 0x00000024 +#define RF5G_RF5G2_AGCLO_B_MSB 31 +#define RF5G_RF5G2_AGCLO_B_LSB 29 +#define RF5G_RF5G2_AGCLO_B_MASK 0xe0000000 +#define RF5G_RF5G2_AGCLO_B_GET(x) (((x) & RF5G_RF5G2_AGCLO_B_MASK) >> RF5G_RF5G2_AGCLO_B_LSB) +#define RF5G_RF5G2_AGCLO_B_SET(x) (((x) << RF5G_RF5G2_AGCLO_B_LSB) & RF5G_RF5G2_AGCLO_B_MASK) +#define RF5G_RF5G2_RX5_ATB_SEL_MSB 28 +#define RF5G_RF5G2_RX5_ATB_SEL_LSB 26 +#define RF5G_RF5G2_RX5_ATB_SEL_MASK 0x1c000000 +#define RF5G_RF5G2_RX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G2_RX5_ATB_SEL_MASK) >> RF5G_RF5G2_RX5_ATB_SEL_LSB) +#define RF5G_RF5G2_RX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G2_RX5_ATB_SEL_LSB) & RF5G_RF5G2_RX5_ATB_SEL_MASK) +#define RF5G_RF5G2_PDCMOSLO5_MSB 25 +#define RF5G_RF5G2_PDCMOSLO5_LSB 25 +#define RF5G_RF5G2_PDCMOSLO5_MASK 0x02000000 +#define RF5G_RF5G2_PDCMOSLO5_GET(x) (((x) & RF5G_RF5G2_PDCMOSLO5_MASK) >> RF5G_RF5G2_PDCMOSLO5_LSB) +#define RF5G_RF5G2_PDCMOSLO5_SET(x) (((x) << RF5G_RF5G2_PDCMOSLO5_LSB) & RF5G_RF5G2_PDCMOSLO5_MASK) +#define RF5G_RF5G2_PDVGM5_MSB 24 +#define RF5G_RF5G2_PDVGM5_LSB 24 +#define RF5G_RF5G2_PDVGM5_MASK 0x01000000 +#define RF5G_RF5G2_PDVGM5_GET(x) (((x) & RF5G_RF5G2_PDVGM5_MASK) >> RF5G_RF5G2_PDVGM5_LSB) +#define RF5G_RF5G2_PDVGM5_SET(x) (((x) << RF5G_RF5G2_PDVGM5_LSB) & RF5G_RF5G2_PDVGM5_MASK) +#define RF5G_RF5G2_PDCSLNA5_MSB 23 +#define RF5G_RF5G2_PDCSLNA5_LSB 23 +#define RF5G_RF5G2_PDCSLNA5_MASK 0x00800000 +#define RF5G_RF5G2_PDCSLNA5_GET(x) (((x) & RF5G_RF5G2_PDCSLNA5_MASK) >> RF5G_RF5G2_PDCSLNA5_LSB) +#define RF5G_RF5G2_PDCSLNA5_SET(x) (((x) << RF5G_RF5G2_PDCSLNA5_LSB) & RF5G_RF5G2_PDCSLNA5_MASK) +#define RF5G_RF5G2_PDRFVGA5_MSB 22 +#define RF5G_RF5G2_PDRFVGA5_LSB 22 +#define RF5G_RF5G2_PDRFVGA5_MASK 0x00400000 +#define RF5G_RF5G2_PDRFVGA5_GET(x) (((x) & RF5G_RF5G2_PDRFVGA5_MASK) >> RF5G_RF5G2_PDRFVGA5_LSB) +#define RF5G_RF5G2_PDRFVGA5_SET(x) (((x) << RF5G_RF5G2_PDRFVGA5_LSB) & RF5G_RF5G2_PDRFVGA5_MASK) +#define RF5G_RF5G2_PDREGFE5_MSB 21 +#define RF5G_RF5G2_PDREGFE5_LSB 21 +#define RF5G_RF5G2_PDREGFE5_MASK 0x00200000 +#define RF5G_RF5G2_PDREGFE5_GET(x) (((x) & RF5G_RF5G2_PDREGFE5_MASK) >> RF5G_RF5G2_PDREGFE5_LSB) +#define RF5G_RF5G2_PDREGFE5_SET(x) (((x) << RF5G_RF5G2_PDREGFE5_LSB) & RF5G_RF5G2_PDREGFE5_MASK) +#define RF5G_RF5G2_TUNE_RFVGA5_MSB 20 +#define RF5G_RF5G2_TUNE_RFVGA5_LSB 18 +#define RF5G_RF5G2_TUNE_RFVGA5_MASK 0x001c0000 +#define RF5G_RF5G2_TUNE_RFVGA5_GET(x) (((x) & RF5G_RF5G2_TUNE_RFVGA5_MASK) >> RF5G_RF5G2_TUNE_RFVGA5_LSB) +#define RF5G_RF5G2_TUNE_RFVGA5_SET(x) (((x) << RF5G_RF5G2_TUNE_RFVGA5_LSB) & RF5G_RF5G2_TUNE_RFVGA5_MASK) +#define RF5G_RF5G2_BRFVGA5_MSB 17 +#define RF5G_RF5G2_BRFVGA5_LSB 15 +#define RF5G_RF5G2_BRFVGA5_MASK 0x00038000 +#define RF5G_RF5G2_BRFVGA5_GET(x) (((x) & RF5G_RF5G2_BRFVGA5_MASK) >> RF5G_RF5G2_BRFVGA5_LSB) +#define RF5G_RF5G2_BRFVGA5_SET(x) (((x) << RF5G_RF5G2_BRFVGA5_LSB) & RF5G_RF5G2_BRFVGA5_MASK) +#define RF5G_RF5G2_BCSLNA5_MSB 14 +#define RF5G_RF5G2_BCSLNA5_LSB 12 +#define RF5G_RF5G2_BCSLNA5_MASK 0x00007000 +#define RF5G_RF5G2_BCSLNA5_GET(x) (((x) & RF5G_RF5G2_BCSLNA5_MASK) >> RF5G_RF5G2_BCSLNA5_LSB) +#define RF5G_RF5G2_BCSLNA5_SET(x) (((x) << RF5G_RF5G2_BCSLNA5_LSB) & RF5G_RF5G2_BCSLNA5_MASK) +#define RF5G_RF5G2_BVGM5_MSB 11 +#define RF5G_RF5G2_BVGM5_LSB 9 +#define RF5G_RF5G2_BVGM5_MASK 0x00000e00 +#define RF5G_RF5G2_BVGM5_GET(x) (((x) & RF5G_RF5G2_BVGM5_MASK) >> RF5G_RF5G2_BVGM5_LSB) +#define RF5G_RF5G2_BVGM5_SET(x) (((x) << RF5G_RF5G2_BVGM5_LSB) & RF5G_RF5G2_BVGM5_MASK) +#define RF5G_RF5G2_REGFE_BYPASS5_MSB 8 +#define RF5G_RF5G2_REGFE_BYPASS5_LSB 8 +#define RF5G_RF5G2_REGFE_BYPASS5_MASK 0x00000100 +#define RF5G_RF5G2_REGFE_BYPASS5_GET(x) (((x) & RF5G_RF5G2_REGFE_BYPASS5_MASK) >> RF5G_RF5G2_REGFE_BYPASS5_LSB) +#define RF5G_RF5G2_REGFE_BYPASS5_SET(x) (((x) << RF5G_RF5G2_REGFE_BYPASS5_LSB) & RF5G_RF5G2_REGFE_BYPASS5_MASK) +#define RF5G_RF5G2_LNA5_ATTENMODE_MSB 7 +#define RF5G_RF5G2_LNA5_ATTENMODE_LSB 6 +#define RF5G_RF5G2_LNA5_ATTENMODE_MASK 0x000000c0 +#define RF5G_RF5G2_LNA5_ATTENMODE_GET(x) (((x) & RF5G_RF5G2_LNA5_ATTENMODE_MASK) >> RF5G_RF5G2_LNA5_ATTENMODE_LSB) +#define RF5G_RF5G2_LNA5_ATTENMODE_SET(x) (((x) << RF5G_RF5G2_LNA5_ATTENMODE_LSB) & RF5G_RF5G2_LNA5_ATTENMODE_MASK) +#define RF5G_RF5G2_ENABLE_PCA_MSB 5 +#define RF5G_RF5G2_ENABLE_PCA_LSB 5 +#define RF5G_RF5G2_ENABLE_PCA_MASK 0x00000020 +#define RF5G_RF5G2_ENABLE_PCA_GET(x) (((x) & RF5G_RF5G2_ENABLE_PCA_MASK) >> RF5G_RF5G2_ENABLE_PCA_LSB) +#define RF5G_RF5G2_ENABLE_PCA_SET(x) (((x) << RF5G_RF5G2_ENABLE_PCA_LSB) & RF5G_RF5G2_ENABLE_PCA_MASK) +#define RF5G_RF5G2_TUNE_LO_MSB 4 +#define RF5G_RF5G2_TUNE_LO_LSB 2 +#define RF5G_RF5G2_TUNE_LO_MASK 0x0000001c +#define RF5G_RF5G2_TUNE_LO_GET(x) (((x) & RF5G_RF5G2_TUNE_LO_MASK) >> RF5G_RF5G2_TUNE_LO_LSB) +#define RF5G_RF5G2_TUNE_LO_SET(x) (((x) << RF5G_RF5G2_TUNE_LO_LSB) & RF5G_RF5G2_TUNE_LO_MASK) +#define RF5G_RF5G2_SPARE_MSB 1 +#define RF5G_RF5G2_SPARE_LSB 0 +#define RF5G_RF5G2_SPARE_MASK 0x00000003 +#define RF5G_RF5G2_SPARE_GET(x) (((x) & RF5G_RF5G2_SPARE_MASK) >> RF5G_RF5G2_SPARE_LSB) +#define RF5G_RF5G2_SPARE_SET(x) (((x) << RF5G_RF5G2_SPARE_LSB) & RF5G_RF5G2_SPARE_MASK) + +#define RF2G_RF2G1_ADDRESS 0x00000028 +#define RF2G_RF2G1_OFFSET 0x00000028 +#define RF2G_RF2G1_BLNA1_MSB 31 +#define RF2G_RF2G1_BLNA1_LSB 29 +#define RF2G_RF2G1_BLNA1_MASK 0xe0000000 +#define RF2G_RF2G1_BLNA1_GET(x) (((x) & RF2G_RF2G1_BLNA1_MASK) >> RF2G_RF2G1_BLNA1_LSB) +#define RF2G_RF2G1_BLNA1_SET(x) (((x) << RF2G_RF2G1_BLNA1_LSB) & RF2G_RF2G1_BLNA1_MASK) +#define RF2G_RF2G1_BLNA1F_MSB 28 +#define RF2G_RF2G1_BLNA1F_LSB 26 +#define RF2G_RF2G1_BLNA1F_MASK 0x1c000000 +#define RF2G_RF2G1_BLNA1F_GET(x) (((x) & RF2G_RF2G1_BLNA1F_MASK) >> RF2G_RF2G1_BLNA1F_LSB) +#define RF2G_RF2G1_BLNA1F_SET(x) (((x) << RF2G_RF2G1_BLNA1F_LSB) & RF2G_RF2G1_BLNA1F_MASK) +#define RF2G_RF2G1_BLNA1BUF_MSB 25 +#define RF2G_RF2G1_BLNA1BUF_LSB 23 +#define RF2G_RF2G1_BLNA1BUF_MASK 0x03800000 +#define RF2G_RF2G1_BLNA1BUF_GET(x) (((x) & RF2G_RF2G1_BLNA1BUF_MASK) >> RF2G_RF2G1_BLNA1BUF_LSB) +#define RF2G_RF2G1_BLNA1BUF_SET(x) (((x) << RF2G_RF2G1_BLNA1BUF_LSB) & RF2G_RF2G1_BLNA1BUF_MASK) +#define RF2G_RF2G1_BLNA2_MSB 22 +#define RF2G_RF2G1_BLNA2_LSB 20 +#define RF2G_RF2G1_BLNA2_MASK 0x00700000 +#define RF2G_RF2G1_BLNA2_GET(x) (((x) & RF2G_RF2G1_BLNA2_MASK) >> RF2G_RF2G1_BLNA2_LSB) +#define RF2G_RF2G1_BLNA2_SET(x) (((x) << RF2G_RF2G1_BLNA2_LSB) & RF2G_RF2G1_BLNA2_MASK) +#define RF2G_RF2G1_DB_MSB 19 +#define RF2G_RF2G1_DB_LSB 17 +#define RF2G_RF2G1_DB_MASK 0x000e0000 +#define RF2G_RF2G1_DB_GET(x) (((x) & RF2G_RF2G1_DB_MASK) >> RF2G_RF2G1_DB_LSB) +#define RF2G_RF2G1_DB_SET(x) (((x) << RF2G_RF2G1_DB_LSB) & RF2G_RF2G1_DB_MASK) +#define RF2G_RF2G1_OB_MSB 16 +#define RF2G_RF2G1_OB_LSB 14 +#define RF2G_RF2G1_OB_MASK 0x0001c000 +#define RF2G_RF2G1_OB_GET(x) (((x) & RF2G_RF2G1_OB_MASK) >> RF2G_RF2G1_OB_LSB) +#define RF2G_RF2G1_OB_SET(x) (((x) << RF2G_RF2G1_OB_LSB) & RF2G_RF2G1_OB_MASK) +#define RF2G_RF2G1_FE_ATB_SEL_MSB 13 +#define RF2G_RF2G1_FE_ATB_SEL_LSB 11 +#define RF2G_RF2G1_FE_ATB_SEL_MASK 0x00003800 +#define RF2G_RF2G1_FE_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_FE_ATB_SEL_MASK) >> RF2G_RF2G1_FE_ATB_SEL_LSB) +#define RF2G_RF2G1_FE_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_FE_ATB_SEL_LSB) & RF2G_RF2G1_FE_ATB_SEL_MASK) +#define RF2G_RF2G1_RF_ATB_SEL_MSB 10 +#define RF2G_RF2G1_RF_ATB_SEL_LSB 8 +#define RF2G_RF2G1_RF_ATB_SEL_MASK 0x00000700 +#define RF2G_RF2G1_RF_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_RF_ATB_SEL_MASK) >> RF2G_RF2G1_RF_ATB_SEL_LSB) +#define RF2G_RF2G1_RF_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_RF_ATB_SEL_LSB) & RF2G_RF2G1_RF_ATB_SEL_MASK) +#define RF2G_RF2G1_SELLNA_MSB 7 +#define RF2G_RF2G1_SELLNA_LSB 7 +#define RF2G_RF2G1_SELLNA_MASK 0x00000080 +#define RF2G_RF2G1_SELLNA_GET(x) (((x) & RF2G_RF2G1_SELLNA_MASK) >> RF2G_RF2G1_SELLNA_LSB) +#define RF2G_RF2G1_SELLNA_SET(x) (((x) << RF2G_RF2G1_SELLNA_LSB) & RF2G_RF2G1_SELLNA_MASK) +#define RF2G_RF2G1_LOCONTROL_MSB 6 +#define RF2G_RF2G1_LOCONTROL_LSB 6 +#define RF2G_RF2G1_LOCONTROL_MASK 0x00000040 +#define RF2G_RF2G1_LOCONTROL_GET(x) (((x) & RF2G_RF2G1_LOCONTROL_MASK) >> RF2G_RF2G1_LOCONTROL_LSB) +#define RF2G_RF2G1_LOCONTROL_SET(x) (((x) << RF2G_RF2G1_LOCONTROL_LSB) & RF2G_RF2G1_LOCONTROL_MASK) +#define RF2G_RF2G1_SHORTLNA2_MSB 5 +#define RF2G_RF2G1_SHORTLNA2_LSB 5 +#define RF2G_RF2G1_SHORTLNA2_MASK 0x00000020 +#define RF2G_RF2G1_SHORTLNA2_GET(x) (((x) & RF2G_RF2G1_SHORTLNA2_MASK) >> RF2G_RF2G1_SHORTLNA2_LSB) +#define RF2G_RF2G1_SHORTLNA2_SET(x) (((x) << RF2G_RF2G1_SHORTLNA2_LSB) & RF2G_RF2G1_SHORTLNA2_MASK) +#define RF2G_RF2G1_SPARE_MSB 4 +#define RF2G_RF2G1_SPARE_LSB 0 +#define RF2G_RF2G1_SPARE_MASK 0x0000001f +#define RF2G_RF2G1_SPARE_GET(x) (((x) & RF2G_RF2G1_SPARE_MASK) >> RF2G_RF2G1_SPARE_LSB) +#define RF2G_RF2G1_SPARE_SET(x) (((x) << RF2G_RF2G1_SPARE_LSB) & RF2G_RF2G1_SPARE_MASK) + +#define RF2G_RF2G2_ADDRESS 0x0000002c +#define RF2G_RF2G2_OFFSET 0x0000002c +#define RF2G_RF2G2_PDCGLNA_MSB 31 +#define RF2G_RF2G2_PDCGLNA_LSB 31 +#define RF2G_RF2G2_PDCGLNA_MASK 0x80000000 +#define RF2G_RF2G2_PDCGLNA_GET(x) (((x) & RF2G_RF2G2_PDCGLNA_MASK) >> RF2G_RF2G2_PDCGLNA_LSB) +#define RF2G_RF2G2_PDCGLNA_SET(x) (((x) << RF2G_RF2G2_PDCGLNA_LSB) & RF2G_RF2G2_PDCGLNA_MASK) +#define RF2G_RF2G2_PDCGLNABUF_MSB 30 +#define RF2G_RF2G2_PDCGLNABUF_LSB 30 +#define RF2G_RF2G2_PDCGLNABUF_MASK 0x40000000 +#define RF2G_RF2G2_PDCGLNABUF_GET(x) (((x) & RF2G_RF2G2_PDCGLNABUF_MASK) >> RF2G_RF2G2_PDCGLNABUF_LSB) +#define RF2G_RF2G2_PDCGLNABUF_SET(x) (((x) << RF2G_RF2G2_PDCGLNABUF_LSB) & RF2G_RF2G2_PDCGLNABUF_MASK) +#define RF2G_RF2G2_PDCSLNA_MSB 29 +#define RF2G_RF2G2_PDCSLNA_LSB 29 +#define RF2G_RF2G2_PDCSLNA_MASK 0x20000000 +#define RF2G_RF2G2_PDCSLNA_GET(x) (((x) & RF2G_RF2G2_PDCSLNA_MASK) >> RF2G_RF2G2_PDCSLNA_LSB) +#define RF2G_RF2G2_PDCSLNA_SET(x) (((x) << RF2G_RF2G2_PDCSLNA_LSB) & RF2G_RF2G2_PDCSLNA_MASK) +#define RF2G_RF2G2_PDDIV_MSB 28 +#define RF2G_RF2G2_PDDIV_LSB 28 +#define RF2G_RF2G2_PDDIV_MASK 0x10000000 +#define RF2G_RF2G2_PDDIV_GET(x) (((x) & RF2G_RF2G2_PDDIV_MASK) >> RF2G_RF2G2_PDDIV_LSB) +#define RF2G_RF2G2_PDDIV_SET(x) (((x) << RF2G_RF2G2_PDDIV_LSB) & RF2G_RF2G2_PDDIV_MASK) +#define RF2G_RF2G2_PDPADRV_MSB 27 +#define RF2G_RF2G2_PDPADRV_LSB 27 +#define RF2G_RF2G2_PDPADRV_MASK 0x08000000 +#define RF2G_RF2G2_PDPADRV_GET(x) (((x) & RF2G_RF2G2_PDPADRV_MASK) >> RF2G_RF2G2_PDPADRV_LSB) +#define RF2G_RF2G2_PDPADRV_SET(x) (((x) << RF2G_RF2G2_PDPADRV_LSB) & RF2G_RF2G2_PDPADRV_MASK) +#define RF2G_RF2G2_PDPAOUT_MSB 26 +#define RF2G_RF2G2_PDPAOUT_LSB 26 +#define RF2G_RF2G2_PDPAOUT_MASK 0x04000000 +#define RF2G_RF2G2_PDPAOUT_GET(x) (((x) & RF2G_RF2G2_PDPAOUT_MASK) >> RF2G_RF2G2_PDPAOUT_LSB) +#define RF2G_RF2G2_PDPAOUT_SET(x) (((x) << RF2G_RF2G2_PDPAOUT_LSB) & RF2G_RF2G2_PDPAOUT_MASK) +#define RF2G_RF2G2_PDREGLNA_MSB 25 +#define RF2G_RF2G2_PDREGLNA_LSB 25 +#define RF2G_RF2G2_PDREGLNA_MASK 0x02000000 +#define RF2G_RF2G2_PDREGLNA_GET(x) (((x) & RF2G_RF2G2_PDREGLNA_MASK) >> RF2G_RF2G2_PDREGLNA_LSB) +#define RF2G_RF2G2_PDREGLNA_SET(x) (((x) << RF2G_RF2G2_PDREGLNA_LSB) & RF2G_RF2G2_PDREGLNA_MASK) +#define RF2G_RF2G2_PDREGLO_MSB 24 +#define RF2G_RF2G2_PDREGLO_LSB 24 +#define RF2G_RF2G2_PDREGLO_MASK 0x01000000 +#define RF2G_RF2G2_PDREGLO_GET(x) (((x) & RF2G_RF2G2_PDREGLO_MASK) >> RF2G_RF2G2_PDREGLO_LSB) +#define RF2G_RF2G2_PDREGLO_SET(x) (((x) << RF2G_RF2G2_PDREGLO_LSB) & RF2G_RF2G2_PDREGLO_MASK) +#define RF2G_RF2G2_PDRFGM_MSB 23 +#define RF2G_RF2G2_PDRFGM_LSB 23 +#define RF2G_RF2G2_PDRFGM_MASK 0x00800000 +#define RF2G_RF2G2_PDRFGM_GET(x) (((x) & RF2G_RF2G2_PDRFGM_MASK) >> RF2G_RF2G2_PDRFGM_LSB) +#define RF2G_RF2G2_PDRFGM_SET(x) (((x) << RF2G_RF2G2_PDRFGM_LSB) & RF2G_RF2G2_PDRFGM_MASK) +#define RF2G_RF2G2_PDRXLO_MSB 22 +#define RF2G_RF2G2_PDRXLO_LSB 22 +#define RF2G_RF2G2_PDRXLO_MASK 0x00400000 +#define RF2G_RF2G2_PDRXLO_GET(x) (((x) & RF2G_RF2G2_PDRXLO_MASK) >> RF2G_RF2G2_PDRXLO_LSB) +#define RF2G_RF2G2_PDRXLO_SET(x) (((x) << RF2G_RF2G2_PDRXLO_LSB) & RF2G_RF2G2_PDRXLO_MASK) +#define RF2G_RF2G2_PDTXLO_MSB 21 +#define RF2G_RF2G2_PDTXLO_LSB 21 +#define RF2G_RF2G2_PDTXLO_MASK 0x00200000 +#define RF2G_RF2G2_PDTXLO_GET(x) (((x) & RF2G_RF2G2_PDTXLO_MASK) >> RF2G_RF2G2_PDTXLO_LSB) +#define RF2G_RF2G2_PDTXLO_SET(x) (((x) << RF2G_RF2G2_PDTXLO_LSB) & RF2G_RF2G2_PDTXLO_MASK) +#define RF2G_RF2G2_PDTXMIX_MSB 20 +#define RF2G_RF2G2_PDTXMIX_LSB 20 +#define RF2G_RF2G2_PDTXMIX_MASK 0x00100000 +#define RF2G_RF2G2_PDTXMIX_GET(x) (((x) & RF2G_RF2G2_PDTXMIX_MASK) >> RF2G_RF2G2_PDTXMIX_LSB) +#define RF2G_RF2G2_PDTXMIX_SET(x) (((x) << RF2G_RF2G2_PDTXMIX_LSB) & RF2G_RF2G2_PDTXMIX_MASK) +#define RF2G_RF2G2_REGLNA_BYPASS_MSB 19 +#define RF2G_RF2G2_REGLNA_BYPASS_LSB 19 +#define RF2G_RF2G2_REGLNA_BYPASS_MASK 0x00080000 +#define RF2G_RF2G2_REGLNA_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLNA_BYPASS_MASK) >> RF2G_RF2G2_REGLNA_BYPASS_LSB) +#define RF2G_RF2G2_REGLNA_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLNA_BYPASS_LSB) & RF2G_RF2G2_REGLNA_BYPASS_MASK) +#define RF2G_RF2G2_REGLO_BYPASS_MSB 18 +#define RF2G_RF2G2_REGLO_BYPASS_LSB 18 +#define RF2G_RF2G2_REGLO_BYPASS_MASK 0x00040000 +#define RF2G_RF2G2_REGLO_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLO_BYPASS_MASK) >> RF2G_RF2G2_REGLO_BYPASS_LSB) +#define RF2G_RF2G2_REGLO_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLO_BYPASS_LSB) & RF2G_RF2G2_REGLO_BYPASS_MASK) +#define RF2G_RF2G2_ENABLE_PCB_MSB 17 +#define RF2G_RF2G2_ENABLE_PCB_LSB 17 +#define RF2G_RF2G2_ENABLE_PCB_MASK 0x00020000 +#define RF2G_RF2G2_ENABLE_PCB_GET(x) (((x) & RF2G_RF2G2_ENABLE_PCB_MASK) >> RF2G_RF2G2_ENABLE_PCB_LSB) +#define RF2G_RF2G2_ENABLE_PCB_SET(x) (((x) << RF2G_RF2G2_ENABLE_PCB_LSB) & RF2G_RF2G2_ENABLE_PCB_MASK) +#define RF2G_RF2G2_SPARE_MSB 16 +#define RF2G_RF2G2_SPARE_LSB 0 +#define RF2G_RF2G2_SPARE_MASK 0x0001ffff +#define RF2G_RF2G2_SPARE_GET(x) (((x) & RF2G_RF2G2_SPARE_MASK) >> RF2G_RF2G2_SPARE_LSB) +#define RF2G_RF2G2_SPARE_SET(x) (((x) << RF2G_RF2G2_SPARE_LSB) & RF2G_RF2G2_SPARE_MASK) + +#define TOP_GAIN_ADDRESS 0x00000030 +#define TOP_GAIN_OFFSET 0x00000030 +#define TOP_GAIN_TX6DBLOQGAIN_MSB 31 +#define TOP_GAIN_TX6DBLOQGAIN_LSB 30 +#define TOP_GAIN_TX6DBLOQGAIN_MASK 0xc0000000 +#define TOP_GAIN_TX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX6DBLOQGAIN_MASK) >> TOP_GAIN_TX6DBLOQGAIN_LSB) +#define TOP_GAIN_TX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX6DBLOQGAIN_LSB) & TOP_GAIN_TX6DBLOQGAIN_MASK) +#define TOP_GAIN_TX1DBLOQGAIN_MSB 29 +#define TOP_GAIN_TX1DBLOQGAIN_LSB 27 +#define TOP_GAIN_TX1DBLOQGAIN_MASK 0x38000000 +#define TOP_GAIN_TX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX1DBLOQGAIN_MASK) >> TOP_GAIN_TX1DBLOQGAIN_LSB) +#define TOP_GAIN_TX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX1DBLOQGAIN_LSB) & TOP_GAIN_TX1DBLOQGAIN_MASK) +#define TOP_GAIN_TXV2IGAIN_MSB 26 +#define TOP_GAIN_TXV2IGAIN_LSB 25 +#define TOP_GAIN_TXV2IGAIN_MASK 0x06000000 +#define TOP_GAIN_TXV2IGAIN_GET(x) (((x) & TOP_GAIN_TXV2IGAIN_MASK) >> TOP_GAIN_TXV2IGAIN_LSB) +#define TOP_GAIN_TXV2IGAIN_SET(x) (((x) << TOP_GAIN_TXV2IGAIN_LSB) & TOP_GAIN_TXV2IGAIN_MASK) +#define TOP_GAIN_PABUF5GN_MSB 24 +#define TOP_GAIN_PABUF5GN_LSB 24 +#define TOP_GAIN_PABUF5GN_MASK 0x01000000 +#define TOP_GAIN_PABUF5GN_GET(x) (((x) & TOP_GAIN_PABUF5GN_MASK) >> TOP_GAIN_PABUF5GN_LSB) +#define TOP_GAIN_PABUF5GN_SET(x) (((x) << TOP_GAIN_PABUF5GN_LSB) & TOP_GAIN_PABUF5GN_MASK) +#define TOP_GAIN_PADRVGN_MSB 23 +#define TOP_GAIN_PADRVGN_LSB 21 +#define TOP_GAIN_PADRVGN_MASK 0x00e00000 +#define TOP_GAIN_PADRVGN_GET(x) (((x) & TOP_GAIN_PADRVGN_MASK) >> TOP_GAIN_PADRVGN_LSB) +#define TOP_GAIN_PADRVGN_SET(x) (((x) << TOP_GAIN_PADRVGN_LSB) & TOP_GAIN_PADRVGN_MASK) +#define TOP_GAIN_PAOUT2GN_MSB 20 +#define TOP_GAIN_PAOUT2GN_LSB 18 +#define TOP_GAIN_PAOUT2GN_MASK 0x001c0000 +#define TOP_GAIN_PAOUT2GN_GET(x) (((x) & TOP_GAIN_PAOUT2GN_MASK) >> TOP_GAIN_PAOUT2GN_LSB) +#define TOP_GAIN_PAOUT2GN_SET(x) (((x) << TOP_GAIN_PAOUT2GN_LSB) & TOP_GAIN_PAOUT2GN_MASK) +#define TOP_GAIN_LNAON_MSB 17 +#define TOP_GAIN_LNAON_LSB 17 +#define TOP_GAIN_LNAON_MASK 0x00020000 +#define TOP_GAIN_LNAON_GET(x) (((x) & TOP_GAIN_LNAON_MASK) >> TOP_GAIN_LNAON_LSB) +#define TOP_GAIN_LNAON_SET(x) (((x) << TOP_GAIN_LNAON_LSB) & TOP_GAIN_LNAON_MASK) +#define TOP_GAIN_LNAGAIN_MSB 16 +#define TOP_GAIN_LNAGAIN_LSB 13 +#define TOP_GAIN_LNAGAIN_MASK 0x0001e000 +#define TOP_GAIN_LNAGAIN_GET(x) (((x) & TOP_GAIN_LNAGAIN_MASK) >> TOP_GAIN_LNAGAIN_LSB) +#define TOP_GAIN_LNAGAIN_SET(x) (((x) << TOP_GAIN_LNAGAIN_LSB) & TOP_GAIN_LNAGAIN_MASK) +#define TOP_GAIN_RFVGA5GAIN_MSB 12 +#define TOP_GAIN_RFVGA5GAIN_LSB 11 +#define TOP_GAIN_RFVGA5GAIN_MASK 0x00001800 +#define TOP_GAIN_RFVGA5GAIN_GET(x) (((x) & TOP_GAIN_RFVGA5GAIN_MASK) >> TOP_GAIN_RFVGA5GAIN_LSB) +#define TOP_GAIN_RFVGA5GAIN_SET(x) (((x) << TOP_GAIN_RFVGA5GAIN_LSB) & TOP_GAIN_RFVGA5GAIN_MASK) +#define TOP_GAIN_RFGMGN_MSB 10 +#define TOP_GAIN_RFGMGN_LSB 8 +#define TOP_GAIN_RFGMGN_MASK 0x00000700 +#define TOP_GAIN_RFGMGN_GET(x) (((x) & TOP_GAIN_RFGMGN_MASK) >> TOP_GAIN_RFGMGN_LSB) +#define TOP_GAIN_RFGMGN_SET(x) (((x) << TOP_GAIN_RFGMGN_LSB) & TOP_GAIN_RFGMGN_MASK) +#define TOP_GAIN_RX6DBLOQGAIN_MSB 7 +#define TOP_GAIN_RX6DBLOQGAIN_LSB 6 +#define TOP_GAIN_RX6DBLOQGAIN_MASK 0x000000c0 +#define TOP_GAIN_RX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBLOQGAIN_MASK) >> TOP_GAIN_RX6DBLOQGAIN_LSB) +#define TOP_GAIN_RX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBLOQGAIN_LSB) & TOP_GAIN_RX6DBLOQGAIN_MASK) +#define TOP_GAIN_RX1DBLOQGAIN_MSB 5 +#define TOP_GAIN_RX1DBLOQGAIN_LSB 3 +#define TOP_GAIN_RX1DBLOQGAIN_MASK 0x00000038 +#define TOP_GAIN_RX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX1DBLOQGAIN_MASK) >> TOP_GAIN_RX1DBLOQGAIN_LSB) +#define TOP_GAIN_RX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX1DBLOQGAIN_LSB) & TOP_GAIN_RX1DBLOQGAIN_MASK) +#define TOP_GAIN_RX6DBHIQGAIN_MSB 2 +#define TOP_GAIN_RX6DBHIQGAIN_LSB 1 +#define TOP_GAIN_RX6DBHIQGAIN_MASK 0x00000006 +#define TOP_GAIN_RX6DBHIQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBHIQGAIN_MASK) >> TOP_GAIN_RX6DBHIQGAIN_LSB) +#define TOP_GAIN_RX6DBHIQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBHIQGAIN_LSB) & TOP_GAIN_RX6DBHIQGAIN_MASK) +#define TOP_GAIN_SPARE_MSB 0 +#define TOP_GAIN_SPARE_LSB 0 +#define TOP_GAIN_SPARE_MASK 0x00000001 +#define TOP_GAIN_SPARE_GET(x) (((x) & TOP_GAIN_SPARE_MASK) >> TOP_GAIN_SPARE_LSB) +#define TOP_GAIN_SPARE_SET(x) (((x) << TOP_GAIN_SPARE_LSB) & TOP_GAIN_SPARE_MASK) + +#define TOP_TOP_ADDRESS 0x00000034 +#define TOP_TOP_OFFSET 0x00000034 +#define TOP_TOP_LOCALTXGAIN_MSB 31 +#define TOP_TOP_LOCALTXGAIN_LSB 31 +#define TOP_TOP_LOCALTXGAIN_MASK 0x80000000 +#define TOP_TOP_LOCALTXGAIN_GET(x) (((x) & TOP_TOP_LOCALTXGAIN_MASK) >> TOP_TOP_LOCALTXGAIN_LSB) +#define TOP_TOP_LOCALTXGAIN_SET(x) (((x) << TOP_TOP_LOCALTXGAIN_LSB) & TOP_TOP_LOCALTXGAIN_MASK) +#define TOP_TOP_LOCALRXGAIN_MSB 30 +#define TOP_TOP_LOCALRXGAIN_LSB 30 +#define TOP_TOP_LOCALRXGAIN_MASK 0x40000000 +#define TOP_TOP_LOCALRXGAIN_GET(x) (((x) & TOP_TOP_LOCALRXGAIN_MASK) >> TOP_TOP_LOCALRXGAIN_LSB) +#define TOP_TOP_LOCALRXGAIN_SET(x) (((x) << TOP_TOP_LOCALRXGAIN_LSB) & TOP_TOP_LOCALRXGAIN_MASK) +#define TOP_TOP_LOCALMODE_MSB 29 +#define TOP_TOP_LOCALMODE_LSB 29 +#define TOP_TOP_LOCALMODE_MASK 0x20000000 +#define TOP_TOP_LOCALMODE_GET(x) (((x) & TOP_TOP_LOCALMODE_MASK) >> TOP_TOP_LOCALMODE_LSB) +#define TOP_TOP_LOCALMODE_SET(x) (((x) << TOP_TOP_LOCALMODE_LSB) & TOP_TOP_LOCALMODE_MASK) +#define TOP_TOP_CALFC_MSB 28 +#define TOP_TOP_CALFC_LSB 28 +#define TOP_TOP_CALFC_MASK 0x10000000 +#define TOP_TOP_CALFC_GET(x) (((x) & TOP_TOP_CALFC_MASK) >> TOP_TOP_CALFC_LSB) +#define TOP_TOP_CALFC_SET(x) (((x) << TOP_TOP_CALFC_LSB) & TOP_TOP_CALFC_MASK) +#define TOP_TOP_CALDC_MSB 27 +#define TOP_TOP_CALDC_LSB 27 +#define TOP_TOP_CALDC_MASK 0x08000000 +#define TOP_TOP_CALDC_GET(x) (((x) & TOP_TOP_CALDC_MASK) >> TOP_TOP_CALDC_LSB) +#define TOP_TOP_CALDC_SET(x) (((x) << TOP_TOP_CALDC_LSB) & TOP_TOP_CALDC_MASK) +#define TOP_TOP_CAL_RESIDUE_MSB 26 +#define TOP_TOP_CAL_RESIDUE_LSB 26 +#define TOP_TOP_CAL_RESIDUE_MASK 0x04000000 +#define TOP_TOP_CAL_RESIDUE_GET(x) (((x) & TOP_TOP_CAL_RESIDUE_MASK) >> TOP_TOP_CAL_RESIDUE_LSB) +#define TOP_TOP_CAL_RESIDUE_SET(x) (((x) << TOP_TOP_CAL_RESIDUE_LSB) & TOP_TOP_CAL_RESIDUE_MASK) +#define TOP_TOP_BMODE_MSB 25 +#define TOP_TOP_BMODE_LSB 25 +#define TOP_TOP_BMODE_MASK 0x02000000 +#define TOP_TOP_BMODE_GET(x) (((x) & TOP_TOP_BMODE_MASK) >> TOP_TOP_BMODE_LSB) +#define TOP_TOP_BMODE_SET(x) (((x) << TOP_TOP_BMODE_LSB) & TOP_TOP_BMODE_MASK) +#define TOP_TOP_SYNTHON_MSB 24 +#define TOP_TOP_SYNTHON_LSB 24 +#define TOP_TOP_SYNTHON_MASK 0x01000000 +#define TOP_TOP_SYNTHON_GET(x) (((x) & TOP_TOP_SYNTHON_MASK) >> TOP_TOP_SYNTHON_LSB) +#define TOP_TOP_SYNTHON_SET(x) (((x) << TOP_TOP_SYNTHON_LSB) & TOP_TOP_SYNTHON_MASK) +#define TOP_TOP_RXON_MSB 23 +#define TOP_TOP_RXON_LSB 23 +#define TOP_TOP_RXON_MASK 0x00800000 +#define TOP_TOP_RXON_GET(x) (((x) & TOP_TOP_RXON_MASK) >> TOP_TOP_RXON_LSB) +#define TOP_TOP_RXON_SET(x) (((x) << TOP_TOP_RXON_LSB) & TOP_TOP_RXON_MASK) +#define TOP_TOP_TXON_MSB 22 +#define TOP_TOP_TXON_LSB 22 +#define TOP_TOP_TXON_MASK 0x00400000 +#define TOP_TOP_TXON_GET(x) (((x) & TOP_TOP_TXON_MASK) >> TOP_TOP_TXON_LSB) +#define TOP_TOP_TXON_SET(x) (((x) << TOP_TOP_TXON_LSB) & TOP_TOP_TXON_MASK) +#define TOP_TOP_PAON_MSB 21 +#define TOP_TOP_PAON_LSB 21 +#define TOP_TOP_PAON_MASK 0x00200000 +#define TOP_TOP_PAON_GET(x) (((x) & TOP_TOP_PAON_MASK) >> TOP_TOP_PAON_LSB) +#define TOP_TOP_PAON_SET(x) (((x) << TOP_TOP_PAON_LSB) & TOP_TOP_PAON_MASK) +#define TOP_TOP_CALTX_MSB 20 +#define TOP_TOP_CALTX_LSB 20 +#define TOP_TOP_CALTX_MASK 0x00100000 +#define TOP_TOP_CALTX_GET(x) (((x) & TOP_TOP_CALTX_MASK) >> TOP_TOP_CALTX_LSB) +#define TOP_TOP_CALTX_SET(x) (((x) << TOP_TOP_CALTX_LSB) & TOP_TOP_CALTX_MASK) +#define TOP_TOP_LOCALADDAC_MSB 19 +#define TOP_TOP_LOCALADDAC_LSB 19 +#define TOP_TOP_LOCALADDAC_MASK 0x00080000 +#define TOP_TOP_LOCALADDAC_GET(x) (((x) & TOP_TOP_LOCALADDAC_MASK) >> TOP_TOP_LOCALADDAC_LSB) +#define TOP_TOP_LOCALADDAC_SET(x) (((x) << TOP_TOP_LOCALADDAC_LSB) & TOP_TOP_LOCALADDAC_MASK) +#define TOP_TOP_PWDPLL_MSB 18 +#define TOP_TOP_PWDPLL_LSB 18 +#define TOP_TOP_PWDPLL_MASK 0x00040000 +#define TOP_TOP_PWDPLL_GET(x) (((x) & TOP_TOP_PWDPLL_MASK) >> TOP_TOP_PWDPLL_LSB) +#define TOP_TOP_PWDPLL_SET(x) (((x) << TOP_TOP_PWDPLL_LSB) & TOP_TOP_PWDPLL_MASK) +#define TOP_TOP_PWDADC_MSB 17 +#define TOP_TOP_PWDADC_LSB 17 +#define TOP_TOP_PWDADC_MASK 0x00020000 +#define TOP_TOP_PWDADC_GET(x) (((x) & TOP_TOP_PWDADC_MASK) >> TOP_TOP_PWDADC_LSB) +#define TOP_TOP_PWDADC_SET(x) (((x) << TOP_TOP_PWDADC_LSB) & TOP_TOP_PWDADC_MASK) +#define TOP_TOP_PWDDAC_MSB 16 +#define TOP_TOP_PWDDAC_LSB 16 +#define TOP_TOP_PWDDAC_MASK 0x00010000 +#define TOP_TOP_PWDDAC_GET(x) (((x) & TOP_TOP_PWDDAC_MASK) >> TOP_TOP_PWDDAC_LSB) +#define TOP_TOP_PWDDAC_SET(x) (((x) << TOP_TOP_PWDDAC_LSB) & TOP_TOP_PWDDAC_MASK) +#define TOP_TOP_LOCALXTAL_MSB 15 +#define TOP_TOP_LOCALXTAL_LSB 15 +#define TOP_TOP_LOCALXTAL_MASK 0x00008000 +#define TOP_TOP_LOCALXTAL_GET(x) (((x) & TOP_TOP_LOCALXTAL_MASK) >> TOP_TOP_LOCALXTAL_LSB) +#define TOP_TOP_LOCALXTAL_SET(x) (((x) << TOP_TOP_LOCALXTAL_LSB) & TOP_TOP_LOCALXTAL_MASK) +#define TOP_TOP_PWDCLKIN_MSB 14 +#define TOP_TOP_PWDCLKIN_LSB 14 +#define TOP_TOP_PWDCLKIN_MASK 0x00004000 +#define TOP_TOP_PWDCLKIN_GET(x) (((x) & TOP_TOP_PWDCLKIN_MASK) >> TOP_TOP_PWDCLKIN_LSB) +#define TOP_TOP_PWDCLKIN_SET(x) (((x) << TOP_TOP_PWDCLKIN_LSB) & TOP_TOP_PWDCLKIN_MASK) +#define TOP_TOP_OSCON_MSB 13 +#define TOP_TOP_OSCON_LSB 13 +#define TOP_TOP_OSCON_MASK 0x00002000 +#define TOP_TOP_OSCON_GET(x) (((x) & TOP_TOP_OSCON_MASK) >> TOP_TOP_OSCON_LSB) +#define TOP_TOP_OSCON_SET(x) (((x) << TOP_TOP_OSCON_LSB) & TOP_TOP_OSCON_MASK) +#define TOP_TOP_SCLKEN_FORCE_MSB 12 +#define TOP_TOP_SCLKEN_FORCE_LSB 12 +#define TOP_TOP_SCLKEN_FORCE_MASK 0x00001000 +#define TOP_TOP_SCLKEN_FORCE_GET(x) (((x) & TOP_TOP_SCLKEN_FORCE_MASK) >> TOP_TOP_SCLKEN_FORCE_LSB) +#define TOP_TOP_SCLKEN_FORCE_SET(x) (((x) << TOP_TOP_SCLKEN_FORCE_LSB) & TOP_TOP_SCLKEN_FORCE_MASK) +#define TOP_TOP_SYNTHON_FORCE_MSB 11 +#define TOP_TOP_SYNTHON_FORCE_LSB 11 +#define TOP_TOP_SYNTHON_FORCE_MASK 0x00000800 +#define TOP_TOP_SYNTHON_FORCE_GET(x) (((x) & TOP_TOP_SYNTHON_FORCE_MASK) >> TOP_TOP_SYNTHON_FORCE_LSB) +#define TOP_TOP_SYNTHON_FORCE_SET(x) (((x) << TOP_TOP_SYNTHON_FORCE_LSB) & TOP_TOP_SYNTHON_FORCE_MASK) +#define TOP_TOP_PDBIAS_MSB 10 +#define TOP_TOP_PDBIAS_LSB 10 +#define TOP_TOP_PDBIAS_MASK 0x00000400 +#define TOP_TOP_PDBIAS_GET(x) (((x) & TOP_TOP_PDBIAS_MASK) >> TOP_TOP_PDBIAS_LSB) +#define TOP_TOP_PDBIAS_SET(x) (((x) << TOP_TOP_PDBIAS_LSB) & TOP_TOP_PDBIAS_MASK) +#define TOP_TOP_DATAOUTSEL_MSB 9 +#define TOP_TOP_DATAOUTSEL_LSB 8 +#define TOP_TOP_DATAOUTSEL_MASK 0x00000300 +#define TOP_TOP_DATAOUTSEL_GET(x) (((x) & TOP_TOP_DATAOUTSEL_MASK) >> TOP_TOP_DATAOUTSEL_LSB) +#define TOP_TOP_DATAOUTSEL_SET(x) (((x) << TOP_TOP_DATAOUTSEL_LSB) & TOP_TOP_DATAOUTSEL_MASK) +#define TOP_TOP_REVID_MSB 7 +#define TOP_TOP_REVID_LSB 5 +#define TOP_TOP_REVID_MASK 0x000000e0 +#define TOP_TOP_REVID_GET(x) (((x) & TOP_TOP_REVID_MASK) >> TOP_TOP_REVID_LSB) +#define TOP_TOP_REVID_SET(x) (((x) << TOP_TOP_REVID_LSB) & TOP_TOP_REVID_MASK) +#define TOP_TOP_INT2PAD_MSB 4 +#define TOP_TOP_INT2PAD_LSB 4 +#define TOP_TOP_INT2PAD_MASK 0x00000010 +#define TOP_TOP_INT2PAD_GET(x) (((x) & TOP_TOP_INT2PAD_MASK) >> TOP_TOP_INT2PAD_LSB) +#define TOP_TOP_INT2PAD_SET(x) (((x) << TOP_TOP_INT2PAD_LSB) & TOP_TOP_INT2PAD_MASK) +#define TOP_TOP_INTH2PAD_MSB 3 +#define TOP_TOP_INTH2PAD_LSB 3 +#define TOP_TOP_INTH2PAD_MASK 0x00000008 +#define TOP_TOP_INTH2PAD_GET(x) (((x) & TOP_TOP_INTH2PAD_MASK) >> TOP_TOP_INTH2PAD_LSB) +#define TOP_TOP_INTH2PAD_SET(x) (((x) << TOP_TOP_INTH2PAD_LSB) & TOP_TOP_INTH2PAD_MASK) +#define TOP_TOP_PAD2GND_MSB 2 +#define TOP_TOP_PAD2GND_LSB 2 +#define TOP_TOP_PAD2GND_MASK 0x00000004 +#define TOP_TOP_PAD2GND_GET(x) (((x) & TOP_TOP_PAD2GND_MASK) >> TOP_TOP_PAD2GND_LSB) +#define TOP_TOP_PAD2GND_SET(x) (((x) << TOP_TOP_PAD2GND_LSB) & TOP_TOP_PAD2GND_MASK) +#define TOP_TOP_INT2GND_MSB 1 +#define TOP_TOP_INT2GND_LSB 1 +#define TOP_TOP_INT2GND_MASK 0x00000002 +#define TOP_TOP_INT2GND_GET(x) (((x) & TOP_TOP_INT2GND_MASK) >> TOP_TOP_INT2GND_LSB) +#define TOP_TOP_INT2GND_SET(x) (((x) << TOP_TOP_INT2GND_LSB) & TOP_TOP_INT2GND_MASK) +#define TOP_TOP_FORCE_XPAON_MSB 0 +#define TOP_TOP_FORCE_XPAON_LSB 0 +#define TOP_TOP_FORCE_XPAON_MASK 0x00000001 +#define TOP_TOP_FORCE_XPAON_GET(x) (((x) & TOP_TOP_FORCE_XPAON_MASK) >> TOP_TOP_FORCE_XPAON_LSB) +#define TOP_TOP_FORCE_XPAON_SET(x) (((x) << TOP_TOP_FORCE_XPAON_LSB) & TOP_TOP_FORCE_XPAON_MASK) + +#define BIAS_BIAS_SEL_ADDRESS 0x00000038 +#define BIAS_BIAS_SEL_OFFSET 0x00000038 +#define BIAS_BIAS_SEL_PADON_MSB 31 +#define BIAS_BIAS_SEL_PADON_LSB 31 +#define BIAS_BIAS_SEL_PADON_MASK 0x80000000 +#define BIAS_BIAS_SEL_PADON_GET(x) (((x) & BIAS_BIAS_SEL_PADON_MASK) >> BIAS_BIAS_SEL_PADON_LSB) +#define BIAS_BIAS_SEL_PADON_SET(x) (((x) << BIAS_BIAS_SEL_PADON_LSB) & BIAS_BIAS_SEL_PADON_MASK) +#define BIAS_BIAS_SEL_SEL_BIAS_MSB 30 +#define BIAS_BIAS_SEL_SEL_BIAS_LSB 25 +#define BIAS_BIAS_SEL_SEL_BIAS_MASK 0x7e000000 +#define BIAS_BIAS_SEL_SEL_BIAS_GET(x) (((x) & BIAS_BIAS_SEL_SEL_BIAS_MASK) >> BIAS_BIAS_SEL_SEL_BIAS_LSB) +#define BIAS_BIAS_SEL_SEL_BIAS_SET(x) (((x) << BIAS_BIAS_SEL_SEL_BIAS_LSB) & BIAS_BIAS_SEL_SEL_BIAS_MASK) +#define BIAS_BIAS_SEL_SEL_SPARE_MSB 24 +#define BIAS_BIAS_SEL_SEL_SPARE_LSB 21 +#define BIAS_BIAS_SEL_SEL_SPARE_MASK 0x01e00000 +#define BIAS_BIAS_SEL_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SEL_SPARE_LSB) +#define BIAS_BIAS_SEL_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SEL_SPARE_MASK) +#define BIAS_BIAS_SEL_SPARE_MSB 20 +#define BIAS_BIAS_SEL_SPARE_LSB 20 +#define BIAS_BIAS_SEL_SPARE_MASK 0x00100000 +#define BIAS_BIAS_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SPARE_LSB) +#define BIAS_BIAS_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SPARE_MASK) +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MSB 19 +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB 17 +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK 0x000e0000 +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB) +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK) +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MSB 16 +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB 16 +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK 0x00010000 +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB) +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK) +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MSB 15 +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB 15 +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK 0x00008000 +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB) +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK) +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MSB 14 +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB 14 +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK 0x00004000 +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB) +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK) +#define BIAS_BIAS_SEL_PWD_ICCPLL25_MSB 13 +#define BIAS_BIAS_SEL_PWD_ICCPLL25_LSB 13 +#define BIAS_BIAS_SEL_PWD_ICCPLL25_MASK 0x00002000 +#define BIAS_BIAS_SEL_PWD_ICCPLL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK) >> BIAS_BIAS_SEL_PWD_ICCPLL25_LSB) +#define BIAS_BIAS_SEL_PWD_ICCPLL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCPLL25_LSB) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK) +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MSB 12 +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB 10 +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK 0x00001c00 +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB) +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK) +#define BIAS_BIAS_SEL_PWD_ICXTAL25_MSB 9 +#define BIAS_BIAS_SEL_PWD_ICXTAL25_LSB 7 +#define BIAS_BIAS_SEL_PWD_ICXTAL25_MASK 0x00000380 +#define BIAS_BIAS_SEL_PWD_ICXTAL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK) >> BIAS_BIAS_SEL_PWD_ICXTAL25_LSB) +#define BIAS_BIAS_SEL_PWD_ICXTAL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICXTAL25_LSB) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK) +#define BIAS_BIAS_SEL_PWD_ICTSENS25_MSB 6 +#define BIAS_BIAS_SEL_PWD_ICTSENS25_LSB 4 +#define BIAS_BIAS_SEL_PWD_ICTSENS25_MASK 0x00000070 +#define BIAS_BIAS_SEL_PWD_ICTSENS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK) >> BIAS_BIAS_SEL_PWD_ICTSENS25_LSB) +#define BIAS_BIAS_SEL_PWD_ICTSENS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTSENS25_LSB) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK) +#define BIAS_BIAS_SEL_PWD_ICTXPC25_MSB 3 +#define BIAS_BIAS_SEL_PWD_ICTXPC25_LSB 1 +#define BIAS_BIAS_SEL_PWD_ICTXPC25_MASK 0x0000000e +#define BIAS_BIAS_SEL_PWD_ICTXPC25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK) >> BIAS_BIAS_SEL_PWD_ICTXPC25_LSB) +#define BIAS_BIAS_SEL_PWD_ICTXPC25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTXPC25_LSB) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK) +#define BIAS_BIAS_SEL_PWD_ICLDO25_MSB 0 +#define BIAS_BIAS_SEL_PWD_ICLDO25_LSB 0 +#define BIAS_BIAS_SEL_PWD_ICLDO25_MASK 0x00000001 +#define BIAS_BIAS_SEL_PWD_ICLDO25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK) >> BIAS_BIAS_SEL_PWD_ICLDO25_LSB) +#define BIAS_BIAS_SEL_PWD_ICLDO25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICLDO25_LSB) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK) + +#define BIAS_BIAS1_ADDRESS 0x0000003c +#define BIAS_BIAS1_OFFSET 0x0000003c +#define BIAS_BIAS1_PWD_ICDAC2BB25_MSB 31 +#define BIAS_BIAS1_PWD_ICDAC2BB25_LSB 29 +#define BIAS_BIAS1_PWD_ICDAC2BB25_MASK 0xe0000000 +#define BIAS_BIAS1_PWD_ICDAC2BB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK) >> BIAS_BIAS1_PWD_ICDAC2BB25_LSB) +#define BIAS_BIAS1_PWD_ICDAC2BB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDAC2BB25_LSB) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK) +#define BIAS_BIAS1_PWD_IC2GVGM25_MSB 28 +#define BIAS_BIAS1_PWD_IC2GVGM25_LSB 26 +#define BIAS_BIAS1_PWD_IC2GVGM25_MASK 0x1c000000 +#define BIAS_BIAS1_PWD_IC2GVGM25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GVGM25_MASK) >> BIAS_BIAS1_PWD_IC2GVGM25_LSB) +#define BIAS_BIAS1_PWD_IC2GVGM25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GVGM25_LSB) & BIAS_BIAS1_PWD_IC2GVGM25_MASK) +#define BIAS_BIAS1_PWD_IC2GRFFE25_MSB 25 +#define BIAS_BIAS1_PWD_IC2GRFFE25_LSB 23 +#define BIAS_BIAS1_PWD_IC2GRFFE25_MASK 0x03800000 +#define BIAS_BIAS1_PWD_IC2GRFFE25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK) >> BIAS_BIAS1_PWD_IC2GRFFE25_LSB) +#define BIAS_BIAS1_PWD_IC2GRFFE25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GRFFE25_LSB) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK) +#define BIAS_BIAS1_PWD_IC2GLOREG25_MSB 22 +#define BIAS_BIAS1_PWD_IC2GLOREG25_LSB 20 +#define BIAS_BIAS1_PWD_IC2GLOREG25_MASK 0x00700000 +#define BIAS_BIAS1_PWD_IC2GLOREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLOREG25_LSB) +#define BIAS_BIAS1_PWD_IC2GLOREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLOREG25_LSB) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK) +#define BIAS_BIAS1_PWD_IC2GLNAREG25_MSB 19 +#define BIAS_BIAS1_PWD_IC2GLNAREG25_LSB 17 +#define BIAS_BIAS1_PWD_IC2GLNAREG25_MASK 0x000e0000 +#define BIAS_BIAS1_PWD_IC2GLNAREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLNAREG25_LSB) +#define BIAS_BIAS1_PWD_IC2GLNAREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLNAREG25_LSB) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK) +#define BIAS_BIAS1_PWD_ICDETECTORB25_MSB 16 +#define BIAS_BIAS1_PWD_ICDETECTORB25_LSB 16 +#define BIAS_BIAS1_PWD_ICDETECTORB25_MASK 0x00010000 +#define BIAS_BIAS1_PWD_ICDETECTORB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORB25_LSB) +#define BIAS_BIAS1_PWD_ICDETECTORB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETECTORB25_LSB) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK) +#define BIAS_BIAS1_PWD_ICDETECTORA25_MSB 15 +#define BIAS_BIAS1_PWD_ICDETECTORA25_LSB 15 +#define BIAS_BIAS1_PWD_ICDETECTORA25_MASK 0x00008000 +#define BIAS_BIAS1_PWD_ICDETECTORA25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORA25_LSB) +#define BIAS_BIAS1_PWD_ICDETECTORA25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETECTORA25_LSB) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK) +#define BIAS_BIAS1_PWD_IC5GRXRF25_MSB 14 +#define BIAS_BIAS1_PWD_IC5GRXRF25_LSB 14 +#define BIAS_BIAS1_PWD_IC5GRXRF25_MASK 0x00004000 +#define BIAS_BIAS1_PWD_IC5GRXRF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK) >> BIAS_BIAS1_PWD_IC5GRXRF25_LSB) +#define BIAS_BIAS1_PWD_IC5GRXRF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GRXRF25_LSB) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK) +#define BIAS_BIAS1_PWD_IC5GTXPA25_MSB 13 +#define BIAS_BIAS1_PWD_IC5GTXPA25_LSB 11 +#define BIAS_BIAS1_PWD_IC5GTXPA25_MASK 0x00003800 +#define BIAS_BIAS1_PWD_IC5GTXPA25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK) >> BIAS_BIAS1_PWD_IC5GTXPA25_LSB) +#define BIAS_BIAS1_PWD_IC5GTXPA25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXPA25_LSB) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK) +#define BIAS_BIAS1_PWD_IC5GTXBUF25_MSB 10 +#define BIAS_BIAS1_PWD_IC5GTXBUF25_LSB 8 +#define BIAS_BIAS1_PWD_IC5GTXBUF25_MASK 0x00000700 +#define BIAS_BIAS1_PWD_IC5GTXBUF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK) >> BIAS_BIAS1_PWD_IC5GTXBUF25_LSB) +#define BIAS_BIAS1_PWD_IC5GTXBUF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXBUF25_LSB) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK) +#define BIAS_BIAS1_PWD_IC5GQB25_MSB 7 +#define BIAS_BIAS1_PWD_IC5GQB25_LSB 5 +#define BIAS_BIAS1_PWD_IC5GQB25_MASK 0x000000e0 +#define BIAS_BIAS1_PWD_IC5GQB25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GQB25_MASK) >> BIAS_BIAS1_PWD_IC5GQB25_LSB) +#define BIAS_BIAS1_PWD_IC5GQB25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GQB25_LSB) & BIAS_BIAS1_PWD_IC5GQB25_MASK) +#define BIAS_BIAS1_PWD_IC5GMIXQ25_MSB 4 +#define BIAS_BIAS1_PWD_IC5GMIXQ25_LSB 2 +#define BIAS_BIAS1_PWD_IC5GMIXQ25_MASK 0x0000001c +#define BIAS_BIAS1_PWD_IC5GMIXQ25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK) >> BIAS_BIAS1_PWD_IC5GMIXQ25_LSB) +#define BIAS_BIAS1_PWD_IC5GMIXQ25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GMIXQ25_LSB) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK) +#define BIAS_BIAS1_SPARE_MSB 1 +#define BIAS_BIAS1_SPARE_LSB 0 +#define BIAS_BIAS1_SPARE_MASK 0x00000003 +#define BIAS_BIAS1_SPARE_GET(x) (((x) & BIAS_BIAS1_SPARE_MASK) >> BIAS_BIAS1_SPARE_LSB) +#define BIAS_BIAS1_SPARE_SET(x) (((x) << BIAS_BIAS1_SPARE_LSB) & BIAS_BIAS1_SPARE_MASK) + +#define BIAS_BIAS2_ADDRESS 0x00000040 +#define BIAS_BIAS2_OFFSET 0x00000040 +#define BIAS_BIAS2_PWD_IC5GMIXI25_MSB 31 +#define BIAS_BIAS2_PWD_IC5GMIXI25_LSB 29 +#define BIAS_BIAS2_PWD_IC5GMIXI25_MASK 0xe0000000 +#define BIAS_BIAS2_PWD_IC5GMIXI25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK) >> BIAS_BIAS2_PWD_IC5GMIXI25_LSB) +#define BIAS_BIAS2_PWD_IC5GMIXI25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GMIXI25_LSB) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK) +#define BIAS_BIAS2_PWD_IC5GDIV25_MSB 28 +#define BIAS_BIAS2_PWD_IC5GDIV25_LSB 26 +#define BIAS_BIAS2_PWD_IC5GDIV25_MASK 0x1c000000 +#define BIAS_BIAS2_PWD_IC5GDIV25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GDIV25_MASK) >> BIAS_BIAS2_PWD_IC5GDIV25_LSB) +#define BIAS_BIAS2_PWD_IC5GDIV25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GDIV25_LSB) & BIAS_BIAS2_PWD_IC5GDIV25_MASK) +#define BIAS_BIAS2_PWD_IC5GLOREG25_MSB 25 +#define BIAS_BIAS2_PWD_IC5GLOREG25_LSB 23 +#define BIAS_BIAS2_PWD_IC5GLOREG25_MASK 0x03800000 +#define BIAS_BIAS2_PWD_IC5GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK) >> BIAS_BIAS2_PWD_IC5GLOREG25_LSB) +#define BIAS_BIAS2_PWD_IC5GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GLOREG25_LSB) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK) +#define BIAS_BIAS2_PWD_IRPLL25_MSB 22 +#define BIAS_BIAS2_PWD_IRPLL25_LSB 22 +#define BIAS_BIAS2_PWD_IRPLL25_MASK 0x00400000 +#define BIAS_BIAS2_PWD_IRPLL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRPLL25_MASK) >> BIAS_BIAS2_PWD_IRPLL25_LSB) +#define BIAS_BIAS2_PWD_IRPLL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRPLL25_LSB) & BIAS_BIAS2_PWD_IRPLL25_MASK) +#define BIAS_BIAS2_PWD_IRXTAL25_MSB 21 +#define BIAS_BIAS2_PWD_IRXTAL25_LSB 19 +#define BIAS_BIAS2_PWD_IRXTAL25_MASK 0x00380000 +#define BIAS_BIAS2_PWD_IRXTAL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRXTAL25_MASK) >> BIAS_BIAS2_PWD_IRXTAL25_LSB) +#define BIAS_BIAS2_PWD_IRXTAL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRXTAL25_LSB) & BIAS_BIAS2_PWD_IRXTAL25_MASK) +#define BIAS_BIAS2_PWD_IRTSENS25_MSB 18 +#define BIAS_BIAS2_PWD_IRTSENS25_LSB 16 +#define BIAS_BIAS2_PWD_IRTSENS25_MASK 0x00070000 +#define BIAS_BIAS2_PWD_IRTSENS25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTSENS25_MASK) >> BIAS_BIAS2_PWD_IRTSENS25_LSB) +#define BIAS_BIAS2_PWD_IRTSENS25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTSENS25_LSB) & BIAS_BIAS2_PWD_IRTSENS25_MASK) +#define BIAS_BIAS2_PWD_IRTXPC25_MSB 15 +#define BIAS_BIAS2_PWD_IRTXPC25_LSB 13 +#define BIAS_BIAS2_PWD_IRTXPC25_MASK 0x0000e000 +#define BIAS_BIAS2_PWD_IRTXPC25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTXPC25_MASK) >> BIAS_BIAS2_PWD_IRTXPC25_LSB) +#define BIAS_BIAS2_PWD_IRTXPC25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTXPC25_LSB) & BIAS_BIAS2_PWD_IRTXPC25_MASK) +#define BIAS_BIAS2_PWD_IRLDO25_MSB 12 +#define BIAS_BIAS2_PWD_IRLDO25_LSB 12 +#define BIAS_BIAS2_PWD_IRLDO25_MASK 0x00001000 +#define BIAS_BIAS2_PWD_IRLDO25_GET(x) (((x) & BIAS_BIAS2_PWD_IRLDO25_MASK) >> BIAS_BIAS2_PWD_IRLDO25_LSB) +#define BIAS_BIAS2_PWD_IRLDO25_SET(x) (((x) << BIAS_BIAS2_PWD_IRLDO25_LSB) & BIAS_BIAS2_PWD_IRLDO25_MASK) +#define BIAS_BIAS2_PWD_IR2GTXMIX25_MSB 11 +#define BIAS_BIAS2_PWD_IR2GTXMIX25_LSB 9 +#define BIAS_BIAS2_PWD_IR2GTXMIX25_MASK 0x00000e00 +#define BIAS_BIAS2_PWD_IR2GTXMIX25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK) >> BIAS_BIAS2_PWD_IR2GTXMIX25_LSB) +#define BIAS_BIAS2_PWD_IR2GTXMIX25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GTXMIX25_LSB) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK) +#define BIAS_BIAS2_PWD_IR2GLOREG25_MSB 8 +#define BIAS_BIAS2_PWD_IR2GLOREG25_LSB 6 +#define BIAS_BIAS2_PWD_IR2GLOREG25_MASK 0x000001c0 +#define BIAS_BIAS2_PWD_IR2GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLOREG25_LSB) +#define BIAS_BIAS2_PWD_IR2GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLOREG25_LSB) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK) +#define BIAS_BIAS2_PWD_IR2GLNAREG25_MSB 5 +#define BIAS_BIAS2_PWD_IR2GLNAREG25_LSB 3 +#define BIAS_BIAS2_PWD_IR2GLNAREG25_MASK 0x00000038 +#define BIAS_BIAS2_PWD_IR2GLNAREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLNAREG25_LSB) +#define BIAS_BIAS2_PWD_IR2GLNAREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLNAREG25_LSB) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK) +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MSB 2 +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB 0 +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK 0x00000007 +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_GET(x) (((x) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK) >> BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB) +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_SET(x) (((x) << BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK) + +#define BIAS_BIAS3_ADDRESS 0x00000044 +#define BIAS_BIAS3_OFFSET 0x00000044 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_MSB 31 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_LSB 29 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_MASK 0xe0000000 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK) >> BIAS_BIAS3_PWD_IR5GTXMIX25_LSB) +#define BIAS_BIAS3_PWD_IR5GTXMIX25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GTXMIX25_LSB) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK) +#define BIAS_BIAS3_PWD_IR5GAGC25_MSB 28 +#define BIAS_BIAS3_PWD_IR5GAGC25_LSB 26 +#define BIAS_BIAS3_PWD_IR5GAGC25_MASK 0x1c000000 +#define BIAS_BIAS3_PWD_IR5GAGC25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GAGC25_MASK) >> BIAS_BIAS3_PWD_IR5GAGC25_LSB) +#define BIAS_BIAS3_PWD_IR5GAGC25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GAGC25_LSB) & BIAS_BIAS3_PWD_IR5GAGC25_MASK) +#define BIAS_BIAS3_PWD_ICDAC50_MSB 25 +#define BIAS_BIAS3_PWD_ICDAC50_LSB 23 +#define BIAS_BIAS3_PWD_ICDAC50_MASK 0x03800000 +#define BIAS_BIAS3_PWD_ICDAC50_GET(x) (((x) & BIAS_BIAS3_PWD_ICDAC50_MASK) >> BIAS_BIAS3_PWD_ICDAC50_LSB) +#define BIAS_BIAS3_PWD_ICDAC50_SET(x) (((x) << BIAS_BIAS3_PWD_ICDAC50_LSB) & BIAS_BIAS3_PWD_ICDAC50_MASK) +#define BIAS_BIAS3_PWD_ICSYNTH50_MSB 22 +#define BIAS_BIAS3_PWD_ICSYNTH50_LSB 22 +#define BIAS_BIAS3_PWD_ICSYNTH50_MASK 0x00400000 +#define BIAS_BIAS3_PWD_ICSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_ICSYNTH50_MASK) >> BIAS_BIAS3_PWD_ICSYNTH50_LSB) +#define BIAS_BIAS3_PWD_ICSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_ICSYNTH50_LSB) & BIAS_BIAS3_PWD_ICSYNTH50_MASK) +#define BIAS_BIAS3_PWD_ICBB50_MSB 21 +#define BIAS_BIAS3_PWD_ICBB50_LSB 21 +#define BIAS_BIAS3_PWD_ICBB50_MASK 0x00200000 +#define BIAS_BIAS3_PWD_ICBB50_GET(x) (((x) & BIAS_BIAS3_PWD_ICBB50_MASK) >> BIAS_BIAS3_PWD_ICBB50_LSB) +#define BIAS_BIAS3_PWD_ICBB50_SET(x) (((x) << BIAS_BIAS3_PWD_ICBB50_LSB) & BIAS_BIAS3_PWD_ICBB50_MASK) +#define BIAS_BIAS3_PWD_IC2GDIV50_MSB 20 +#define BIAS_BIAS3_PWD_IC2GDIV50_LSB 18 +#define BIAS_BIAS3_PWD_IC2GDIV50_MASK 0x001c0000 +#define BIAS_BIAS3_PWD_IC2GDIV50_GET(x) (((x) & BIAS_BIAS3_PWD_IC2GDIV50_MASK) >> BIAS_BIAS3_PWD_IC2GDIV50_LSB) +#define BIAS_BIAS3_PWD_IC2GDIV50_SET(x) (((x) << BIAS_BIAS3_PWD_IC2GDIV50_LSB) & BIAS_BIAS3_PWD_IC2GDIV50_MASK) +#define BIAS_BIAS3_PWD_IRSYNTH50_MSB 17 +#define BIAS_BIAS3_PWD_IRSYNTH50_LSB 17 +#define BIAS_BIAS3_PWD_IRSYNTH50_MASK 0x00020000 +#define BIAS_BIAS3_PWD_IRSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_IRSYNTH50_MASK) >> BIAS_BIAS3_PWD_IRSYNTH50_LSB) +#define BIAS_BIAS3_PWD_IRSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_IRSYNTH50_LSB) & BIAS_BIAS3_PWD_IRSYNTH50_MASK) +#define BIAS_BIAS3_PWD_IRBB50_MSB 16 +#define BIAS_BIAS3_PWD_IRBB50_LSB 16 +#define BIAS_BIAS3_PWD_IRBB50_MASK 0x00010000 +#define BIAS_BIAS3_PWD_IRBB50_GET(x) (((x) & BIAS_BIAS3_PWD_IRBB50_MASK) >> BIAS_BIAS3_PWD_IRBB50_LSB) +#define BIAS_BIAS3_PWD_IRBB50_SET(x) (((x) << BIAS_BIAS3_PWD_IRBB50_LSB) & BIAS_BIAS3_PWD_IRBB50_MASK) +#define BIAS_BIAS3_PWD_IC25SPARE1_MSB 15 +#define BIAS_BIAS3_PWD_IC25SPARE1_LSB 13 +#define BIAS_BIAS3_PWD_IC25SPARE1_MASK 0x0000e000 +#define BIAS_BIAS3_PWD_IC25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPARE1_MASK) >> BIAS_BIAS3_PWD_IC25SPARE1_LSB) +#define BIAS_BIAS3_PWD_IC25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPARE1_LSB) & BIAS_BIAS3_PWD_IC25SPARE1_MASK) +#define BIAS_BIAS3_PWD_IC25SPARE2_MSB 12 +#define BIAS_BIAS3_PWD_IC25SPARE2_LSB 10 +#define BIAS_BIAS3_PWD_IC25SPARE2_MASK 0x00001c00 +#define BIAS_BIAS3_PWD_IC25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPARE2_MASK) >> BIAS_BIAS3_PWD_IC25SPARE2_LSB) +#define BIAS_BIAS3_PWD_IC25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPARE2_LSB) & BIAS_BIAS3_PWD_IC25SPARE2_MASK) +#define BIAS_BIAS3_PWD_IR25SPARE1_MSB 9 +#define BIAS_BIAS3_PWD_IR25SPARE1_LSB 7 +#define BIAS_BIAS3_PWD_IR25SPARE1_MASK 0x00000380 +#define BIAS_BIAS3_PWD_IR25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPARE1_MASK) >> BIAS_BIAS3_PWD_IR25SPARE1_LSB) +#define BIAS_BIAS3_PWD_IR25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPARE1_LSB) & BIAS_BIAS3_PWD_IR25SPARE1_MASK) +#define BIAS_BIAS3_PWD_IR25SPARE2_MSB 6 +#define BIAS_BIAS3_PWD_IR25SPARE2_LSB 4 +#define BIAS_BIAS3_PWD_IR25SPARE2_MASK 0x00000070 +#define BIAS_BIAS3_PWD_IR25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPARE2_MASK) >> BIAS_BIAS3_PWD_IR25SPARE2_LSB) +#define BIAS_BIAS3_PWD_IR25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPARE2_LSB) & BIAS_BIAS3_PWD_IR25SPARE2_MASK) +#define BIAS_BIAS3_PWD_ICDACREG12P5_MSB 3 +#define BIAS_BIAS3_PWD_ICDACREG12P5_LSB 1 +#define BIAS_BIAS3_PWD_ICDACREG12P5_MASK 0x0000000e +#define BIAS_BIAS3_PWD_ICDACREG12P5_GET(x) (((x) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK) >> BIAS_BIAS3_PWD_ICDACREG12P5_LSB) +#define BIAS_BIAS3_PWD_ICDACREG12P5_SET(x) (((x) << BIAS_BIAS3_PWD_ICDACREG12P5_LSB) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK) +#define BIAS_BIAS3_SPARE_MSB 0 +#define BIAS_BIAS3_SPARE_LSB 0 +#define BIAS_BIAS3_SPARE_MASK 0x00000001 +#define BIAS_BIAS3_SPARE_GET(x) (((x) & BIAS_BIAS3_SPARE_MASK) >> BIAS_BIAS3_SPARE_LSB) +#define BIAS_BIAS3_SPARE_SET(x) (((x) << BIAS_BIAS3_SPARE_LSB) & BIAS_BIAS3_SPARE_MASK) + +#define TXPC_TXPC_ADDRESS 0x00000048 +#define TXPC_TXPC_OFFSET 0x00000048 +#define TXPC_TXPC_SELINTPD_MSB 31 +#define TXPC_TXPC_SELINTPD_LSB 31 +#define TXPC_TXPC_SELINTPD_MASK 0x80000000 +#define TXPC_TXPC_SELINTPD_GET(x) (((x) & TXPC_TXPC_SELINTPD_MASK) >> TXPC_TXPC_SELINTPD_LSB) +#define TXPC_TXPC_SELINTPD_SET(x) (((x) << TXPC_TXPC_SELINTPD_LSB) & TXPC_TXPC_SELINTPD_MASK) +#define TXPC_TXPC_TEST_MSB 30 +#define TXPC_TXPC_TEST_LSB 30 +#define TXPC_TXPC_TEST_MASK 0x40000000 +#define TXPC_TXPC_TEST_GET(x) (((x) & TXPC_TXPC_TEST_MASK) >> TXPC_TXPC_TEST_LSB) +#define TXPC_TXPC_TEST_SET(x) (((x) << TXPC_TXPC_TEST_LSB) & TXPC_TXPC_TEST_MASK) +#define TXPC_TXPC_TESTGAIN_MSB 29 +#define TXPC_TXPC_TESTGAIN_LSB 28 +#define TXPC_TXPC_TESTGAIN_MASK 0x30000000 +#define TXPC_TXPC_TESTGAIN_GET(x) (((x) & TXPC_TXPC_TESTGAIN_MASK) >> TXPC_TXPC_TESTGAIN_LSB) +#define TXPC_TXPC_TESTGAIN_SET(x) (((x) << TXPC_TXPC_TESTGAIN_LSB) & TXPC_TXPC_TESTGAIN_MASK) +#define TXPC_TXPC_TESTDAC_MSB 27 +#define TXPC_TXPC_TESTDAC_LSB 22 +#define TXPC_TXPC_TESTDAC_MASK 0x0fc00000 +#define TXPC_TXPC_TESTDAC_GET(x) (((x) & TXPC_TXPC_TESTDAC_MASK) >> TXPC_TXPC_TESTDAC_LSB) +#define TXPC_TXPC_TESTDAC_SET(x) (((x) << TXPC_TXPC_TESTDAC_LSB) & TXPC_TXPC_TESTDAC_MASK) +#define TXPC_TXPC_TESTPWDPC_MSB 21 +#define TXPC_TXPC_TESTPWDPC_LSB 21 +#define TXPC_TXPC_TESTPWDPC_MASK 0x00200000 +#define TXPC_TXPC_TESTPWDPC_GET(x) (((x) & TXPC_TXPC_TESTPWDPC_MASK) >> TXPC_TXPC_TESTPWDPC_LSB) +#define TXPC_TXPC_TESTPWDPC_SET(x) (((x) << TXPC_TXPC_TESTPWDPC_LSB) & TXPC_TXPC_TESTPWDPC_MASK) +#define TXPC_TXPC_CURHALF_MSB 20 +#define TXPC_TXPC_CURHALF_LSB 20 +#define TXPC_TXPC_CURHALF_MASK 0x00100000 +#define TXPC_TXPC_CURHALF_GET(x) (((x) & TXPC_TXPC_CURHALF_MASK) >> TXPC_TXPC_CURHALF_LSB) +#define TXPC_TXPC_CURHALF_SET(x) (((x) << TXPC_TXPC_CURHALF_LSB) & TXPC_TXPC_CURHALF_MASK) +#define TXPC_TXPC_NEGOUT_MSB 19 +#define TXPC_TXPC_NEGOUT_LSB 19 +#define TXPC_TXPC_NEGOUT_MASK 0x00080000 +#define TXPC_TXPC_NEGOUT_GET(x) (((x) & TXPC_TXPC_NEGOUT_MASK) >> TXPC_TXPC_NEGOUT_LSB) +#define TXPC_TXPC_NEGOUT_SET(x) (((x) << TXPC_TXPC_NEGOUT_LSB) & TXPC_TXPC_NEGOUT_MASK) +#define TXPC_TXPC_CLKDELAY_MSB 18 +#define TXPC_TXPC_CLKDELAY_LSB 18 +#define TXPC_TXPC_CLKDELAY_MASK 0x00040000 +#define TXPC_TXPC_CLKDELAY_GET(x) (((x) & TXPC_TXPC_CLKDELAY_MASK) >> TXPC_TXPC_CLKDELAY_LSB) +#define TXPC_TXPC_CLKDELAY_SET(x) (((x) << TXPC_TXPC_CLKDELAY_LSB) & TXPC_TXPC_CLKDELAY_MASK) +#define TXPC_TXPC_SELMODREF_MSB 17 +#define TXPC_TXPC_SELMODREF_LSB 17 +#define TXPC_TXPC_SELMODREF_MASK 0x00020000 +#define TXPC_TXPC_SELMODREF_GET(x) (((x) & TXPC_TXPC_SELMODREF_MASK) >> TXPC_TXPC_SELMODREF_LSB) +#define TXPC_TXPC_SELMODREF_SET(x) (((x) << TXPC_TXPC_SELMODREF_LSB) & TXPC_TXPC_SELMODREF_MASK) +#define TXPC_TXPC_SELCMOUT_MSB 16 +#define TXPC_TXPC_SELCMOUT_LSB 16 +#define TXPC_TXPC_SELCMOUT_MASK 0x00010000 +#define TXPC_TXPC_SELCMOUT_GET(x) (((x) & TXPC_TXPC_SELCMOUT_MASK) >> TXPC_TXPC_SELCMOUT_LSB) +#define TXPC_TXPC_SELCMOUT_SET(x) (((x) << TXPC_TXPC_SELCMOUT_LSB) & TXPC_TXPC_SELCMOUT_MASK) +#define TXPC_TXPC_TSMODE_MSB 15 +#define TXPC_TXPC_TSMODE_LSB 14 +#define TXPC_TXPC_TSMODE_MASK 0x0000c000 +#define TXPC_TXPC_TSMODE_GET(x) (((x) & TXPC_TXPC_TSMODE_MASK) >> TXPC_TXPC_TSMODE_LSB) +#define TXPC_TXPC_TSMODE_SET(x) (((x) << TXPC_TXPC_TSMODE_LSB) & TXPC_TXPC_TSMODE_MASK) +#define TXPC_TXPC_N_MSB 13 +#define TXPC_TXPC_N_LSB 6 +#define TXPC_TXPC_N_MASK 0x00003fc0 +#define TXPC_TXPC_N_GET(x) (((x) & TXPC_TXPC_N_MASK) >> TXPC_TXPC_N_LSB) +#define TXPC_TXPC_N_SET(x) (((x) << TXPC_TXPC_N_LSB) & TXPC_TXPC_N_MASK) +#define TXPC_TXPC_ON1STSYNTHON_MSB 5 +#define TXPC_TXPC_ON1STSYNTHON_LSB 5 +#define TXPC_TXPC_ON1STSYNTHON_MASK 0x00000020 +#define TXPC_TXPC_ON1STSYNTHON_GET(x) (((x) & TXPC_TXPC_ON1STSYNTHON_MASK) >> TXPC_TXPC_ON1STSYNTHON_LSB) +#define TXPC_TXPC_ON1STSYNTHON_SET(x) (((x) << TXPC_TXPC_ON1STSYNTHON_LSB) & TXPC_TXPC_ON1STSYNTHON_MASK) +#define TXPC_TXPC_SELINIT_MSB 4 +#define TXPC_TXPC_SELINIT_LSB 3 +#define TXPC_TXPC_SELINIT_MASK 0x00000018 +#define TXPC_TXPC_SELINIT_GET(x) (((x) & TXPC_TXPC_SELINIT_MASK) >> TXPC_TXPC_SELINIT_LSB) +#define TXPC_TXPC_SELINIT_SET(x) (((x) << TXPC_TXPC_SELINIT_LSB) & TXPC_TXPC_SELINIT_MASK) +#define TXPC_TXPC_SELCOUNT_MSB 2 +#define TXPC_TXPC_SELCOUNT_LSB 2 +#define TXPC_TXPC_SELCOUNT_MASK 0x00000004 +#define TXPC_TXPC_SELCOUNT_GET(x) (((x) & TXPC_TXPC_SELCOUNT_MASK) >> TXPC_TXPC_SELCOUNT_LSB) +#define TXPC_TXPC_SELCOUNT_SET(x) (((x) << TXPC_TXPC_SELCOUNT_LSB) & TXPC_TXPC_SELCOUNT_MASK) +#define TXPC_TXPC_ATBSEL_MSB 1 +#define TXPC_TXPC_ATBSEL_LSB 0 +#define TXPC_TXPC_ATBSEL_MASK 0x00000003 +#define TXPC_TXPC_ATBSEL_GET(x) (((x) & TXPC_TXPC_ATBSEL_MASK) >> TXPC_TXPC_ATBSEL_LSB) +#define TXPC_TXPC_ATBSEL_SET(x) (((x) << TXPC_TXPC_ATBSEL_LSB) & TXPC_TXPC_ATBSEL_MASK) + +#define TXPC_MISC_ADDRESS 0x0000004c +#define TXPC_MISC_OFFSET 0x0000004c +#define TXPC_MISC_FLIPBMODE_MSB 31 +#define TXPC_MISC_FLIPBMODE_LSB 31 +#define TXPC_MISC_FLIPBMODE_MASK 0x80000000 +#define TXPC_MISC_FLIPBMODE_GET(x) (((x) & TXPC_MISC_FLIPBMODE_MASK) >> TXPC_MISC_FLIPBMODE_LSB) +#define TXPC_MISC_FLIPBMODE_SET(x) (((x) << TXPC_MISC_FLIPBMODE_LSB) & TXPC_MISC_FLIPBMODE_MASK) +#define TXPC_MISC_LEVEL_MSB 30 +#define TXPC_MISC_LEVEL_LSB 29 +#define TXPC_MISC_LEVEL_MASK 0x60000000 +#define TXPC_MISC_LEVEL_GET(x) (((x) & TXPC_MISC_LEVEL_MASK) >> TXPC_MISC_LEVEL_LSB) +#define TXPC_MISC_LEVEL_SET(x) (((x) << TXPC_MISC_LEVEL_LSB) & TXPC_MISC_LEVEL_MASK) +#define TXPC_MISC_LDO_TEST_MODE_MSB 28 +#define TXPC_MISC_LDO_TEST_MODE_LSB 28 +#define TXPC_MISC_LDO_TEST_MODE_MASK 0x10000000 +#define TXPC_MISC_LDO_TEST_MODE_GET(x) (((x) & TXPC_MISC_LDO_TEST_MODE_MASK) >> TXPC_MISC_LDO_TEST_MODE_LSB) +#define TXPC_MISC_LDO_TEST_MODE_SET(x) (((x) << TXPC_MISC_LDO_TEST_MODE_LSB) & TXPC_MISC_LDO_TEST_MODE_MASK) +#define TXPC_MISC_NOTCXODET_MSB 27 +#define TXPC_MISC_NOTCXODET_LSB 27 +#define TXPC_MISC_NOTCXODET_MASK 0x08000000 +#define TXPC_MISC_NOTCXODET_GET(x) (((x) & TXPC_MISC_NOTCXODET_MASK) >> TXPC_MISC_NOTCXODET_LSB) +#define TXPC_MISC_NOTCXODET_SET(x) (((x) << TXPC_MISC_NOTCXODET_LSB) & TXPC_MISC_NOTCXODET_MASK) +#define TXPC_MISC_PWDCLKIND_MSB 26 +#define TXPC_MISC_PWDCLKIND_LSB 26 +#define TXPC_MISC_PWDCLKIND_MASK 0x04000000 +#define TXPC_MISC_PWDCLKIND_GET(x) (((x) & TXPC_MISC_PWDCLKIND_MASK) >> TXPC_MISC_PWDCLKIND_LSB) +#define TXPC_MISC_PWDCLKIND_SET(x) (((x) << TXPC_MISC_PWDCLKIND_LSB) & TXPC_MISC_PWDCLKIND_MASK) +#define TXPC_MISC_PWDXINPAD_MSB 25 +#define TXPC_MISC_PWDXINPAD_LSB 25 +#define TXPC_MISC_PWDXINPAD_MASK 0x02000000 +#define TXPC_MISC_PWDXINPAD_GET(x) (((x) & TXPC_MISC_PWDXINPAD_MASK) >> TXPC_MISC_PWDXINPAD_LSB) +#define TXPC_MISC_PWDXINPAD_SET(x) (((x) << TXPC_MISC_PWDXINPAD_LSB) & TXPC_MISC_PWDXINPAD_MASK) +#define TXPC_MISC_LOCALBIAS_MSB 24 +#define TXPC_MISC_LOCALBIAS_LSB 24 +#define TXPC_MISC_LOCALBIAS_MASK 0x01000000 +#define TXPC_MISC_LOCALBIAS_GET(x) (((x) & TXPC_MISC_LOCALBIAS_MASK) >> TXPC_MISC_LOCALBIAS_LSB) +#define TXPC_MISC_LOCALBIAS_SET(x) (((x) << TXPC_MISC_LOCALBIAS_LSB) & TXPC_MISC_LOCALBIAS_MASK) +#define TXPC_MISC_LOCALBIAS2X_MSB 23 +#define TXPC_MISC_LOCALBIAS2X_LSB 23 +#define TXPC_MISC_LOCALBIAS2X_MASK 0x00800000 +#define TXPC_MISC_LOCALBIAS2X_GET(x) (((x) & TXPC_MISC_LOCALBIAS2X_MASK) >> TXPC_MISC_LOCALBIAS2X_LSB) +#define TXPC_MISC_LOCALBIAS2X_SET(x) (((x) << TXPC_MISC_LOCALBIAS2X_LSB) & TXPC_MISC_LOCALBIAS2X_MASK) +#define TXPC_MISC_SELTSP_MSB 22 +#define TXPC_MISC_SELTSP_LSB 22 +#define TXPC_MISC_SELTSP_MASK 0x00400000 +#define TXPC_MISC_SELTSP_GET(x) (((x) & TXPC_MISC_SELTSP_MASK) >> TXPC_MISC_SELTSP_LSB) +#define TXPC_MISC_SELTSP_SET(x) (((x) << TXPC_MISC_SELTSP_LSB) & TXPC_MISC_SELTSP_MASK) +#define TXPC_MISC_SELTSN_MSB 21 +#define TXPC_MISC_SELTSN_LSB 21 +#define TXPC_MISC_SELTSN_MASK 0x00200000 +#define TXPC_MISC_SELTSN_GET(x) (((x) & TXPC_MISC_SELTSN_MASK) >> TXPC_MISC_SELTSN_LSB) +#define TXPC_MISC_SELTSN_SET(x) (((x) << TXPC_MISC_SELTSN_LSB) & TXPC_MISC_SELTSN_MASK) +#define TXPC_MISC_SPARE_A_MSB 20 +#define TXPC_MISC_SPARE_A_LSB 18 +#define TXPC_MISC_SPARE_A_MASK 0x001c0000 +#define TXPC_MISC_SPARE_A_GET(x) (((x) & TXPC_MISC_SPARE_A_MASK) >> TXPC_MISC_SPARE_A_LSB) +#define TXPC_MISC_SPARE_A_SET(x) (((x) << TXPC_MISC_SPARE_A_LSB) & TXPC_MISC_SPARE_A_MASK) +#define TXPC_MISC_DECOUT_MSB 17 +#define TXPC_MISC_DECOUT_LSB 8 +#define TXPC_MISC_DECOUT_MASK 0x0003ff00 +#define TXPC_MISC_DECOUT_GET(x) (((x) & TXPC_MISC_DECOUT_MASK) >> TXPC_MISC_DECOUT_LSB) +#define TXPC_MISC_DECOUT_SET(x) (((x) << TXPC_MISC_DECOUT_LSB) & TXPC_MISC_DECOUT_MASK) +#define TXPC_MISC_XTALDIV_MSB 7 +#define TXPC_MISC_XTALDIV_LSB 6 +#define TXPC_MISC_XTALDIV_MASK 0x000000c0 +#define TXPC_MISC_XTALDIV_GET(x) (((x) & TXPC_MISC_XTALDIV_MASK) >> TXPC_MISC_XTALDIV_LSB) +#define TXPC_MISC_XTALDIV_SET(x) (((x) << TXPC_MISC_XTALDIV_LSB) & TXPC_MISC_XTALDIV_MASK) +#define TXPC_MISC_SPARE_MSB 5 +#define TXPC_MISC_SPARE_LSB 0 +#define TXPC_MISC_SPARE_MASK 0x0000003f +#define TXPC_MISC_SPARE_GET(x) (((x) & TXPC_MISC_SPARE_MASK) >> TXPC_MISC_SPARE_LSB) +#define TXPC_MISC_SPARE_SET(x) (((x) << TXPC_MISC_SPARE_LSB) & TXPC_MISC_SPARE_MASK) + +#define RXTXBB_RXTXBB1_ADDRESS 0x00000050 +#define RXTXBB_RXTXBB1_OFFSET 0x00000050 +#define RXTXBB_RXTXBB1_SPARE_MSB 31 +#define RXTXBB_RXTXBB1_SPARE_LSB 19 +#define RXTXBB_RXTXBB1_SPARE_MASK 0xfff80000 +#define RXTXBB_RXTXBB1_SPARE_GET(x) (((x) & RXTXBB_RXTXBB1_SPARE_MASK) >> RXTXBB_RXTXBB1_SPARE_LSB) +#define RXTXBB_RXTXBB1_SPARE_SET(x) (((x) << RXTXBB_RXTXBB1_SPARE_LSB) & RXTXBB_RXTXBB1_SPARE_MASK) +#define RXTXBB_RXTXBB1_FNOTCH_MSB 18 +#define RXTXBB_RXTXBB1_FNOTCH_LSB 17 +#define RXTXBB_RXTXBB1_FNOTCH_MASK 0x00060000 +#define RXTXBB_RXTXBB1_FNOTCH_GET(x) (((x) & RXTXBB_RXTXBB1_FNOTCH_MASK) >> RXTXBB_RXTXBB1_FNOTCH_LSB) +#define RXTXBB_RXTXBB1_FNOTCH_SET(x) (((x) << RXTXBB_RXTXBB1_FNOTCH_LSB) & RXTXBB_RXTXBB1_FNOTCH_MASK) +#define RXTXBB_RXTXBB1_SEL_ATB_MSB 16 +#define RXTXBB_RXTXBB1_SEL_ATB_LSB 9 +#define RXTXBB_RXTXBB1_SEL_ATB_MASK 0x0001fe00 +#define RXTXBB_RXTXBB1_SEL_ATB_GET(x) (((x) & RXTXBB_RXTXBB1_SEL_ATB_MASK) >> RXTXBB_RXTXBB1_SEL_ATB_LSB) +#define RXTXBB_RXTXBB1_SEL_ATB_SET(x) (((x) << RXTXBB_RXTXBB1_SEL_ATB_LSB) & RXTXBB_RXTXBB1_SEL_ATB_MASK) +#define RXTXBB_RXTXBB1_PDDACINTERFACE_MSB 8 +#define RXTXBB_RXTXBB1_PDDACINTERFACE_LSB 8 +#define RXTXBB_RXTXBB1_PDDACINTERFACE_MASK 0x00000100 +#define RXTXBB_RXTXBB1_PDDACINTERFACE_GET(x) (((x) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK) >> RXTXBB_RXTXBB1_PDDACINTERFACE_LSB) +#define RXTXBB_RXTXBB1_PDDACINTERFACE_SET(x) (((x) << RXTXBB_RXTXBB1_PDDACINTERFACE_LSB) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK) +#define RXTXBB_RXTXBB1_PDV2I_MSB 7 +#define RXTXBB_RXTXBB1_PDV2I_LSB 7 +#define RXTXBB_RXTXBB1_PDV2I_MASK 0x00000080 +#define RXTXBB_RXTXBB1_PDV2I_GET(x) (((x) & RXTXBB_RXTXBB1_PDV2I_MASK) >> RXTXBB_RXTXBB1_PDV2I_LSB) +#define RXTXBB_RXTXBB1_PDV2I_SET(x) (((x) << RXTXBB_RXTXBB1_PDV2I_LSB) & RXTXBB_RXTXBB1_PDV2I_MASK) +#define RXTXBB_RXTXBB1_PDI2V_MSB 6 +#define RXTXBB_RXTXBB1_PDI2V_LSB 6 +#define RXTXBB_RXTXBB1_PDI2V_MASK 0x00000040 +#define RXTXBB_RXTXBB1_PDI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDI2V_MASK) >> RXTXBB_RXTXBB1_PDI2V_LSB) +#define RXTXBB_RXTXBB1_PDI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDI2V_LSB) & RXTXBB_RXTXBB1_PDI2V_MASK) +#define RXTXBB_RXTXBB1_PDRXTXBB_MSB 5 +#define RXTXBB_RXTXBB1_PDRXTXBB_LSB 5 +#define RXTXBB_RXTXBB1_PDRXTXBB_MASK 0x00000020 +#define RXTXBB_RXTXBB1_PDRXTXBB_GET(x) (((x) & RXTXBB_RXTXBB1_PDRXTXBB_MASK) >> RXTXBB_RXTXBB1_PDRXTXBB_LSB) +#define RXTXBB_RXTXBB1_PDRXTXBB_SET(x) (((x) << RXTXBB_RXTXBB1_PDRXTXBB_LSB) & RXTXBB_RXTXBB1_PDRXTXBB_MASK) +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MSB 4 +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB 4 +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK 0x00000010 +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB) +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK) +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MSB 3 +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB 3 +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK 0x00000008 +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB) +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK) +#define RXTXBB_RXTXBB1_PDOFFSETI2V_MSB 2 +#define RXTXBB_RXTXBB1_PDOFFSETI2V_LSB 2 +#define RXTXBB_RXTXBB1_PDOFFSETI2V_MASK 0x00000004 +#define RXTXBB_RXTXBB1_PDOFFSETI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK) >> RXTXBB_RXTXBB1_PDOFFSETI2V_LSB) +#define RXTXBB_RXTXBB1_PDOFFSETI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETI2V_LSB) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK) +#define RXTXBB_RXTXBB1_PDLOQ_MSB 1 +#define RXTXBB_RXTXBB1_PDLOQ_LSB 1 +#define RXTXBB_RXTXBB1_PDLOQ_MASK 0x00000002 +#define RXTXBB_RXTXBB1_PDLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDLOQ_MASK) >> RXTXBB_RXTXBB1_PDLOQ_LSB) +#define RXTXBB_RXTXBB1_PDLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDLOQ_LSB) & RXTXBB_RXTXBB1_PDLOQ_MASK) +#define RXTXBB_RXTXBB1_PDHIQ_MSB 0 +#define RXTXBB_RXTXBB1_PDHIQ_LSB 0 +#define RXTXBB_RXTXBB1_PDHIQ_MASK 0x00000001 +#define RXTXBB_RXTXBB1_PDHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDHIQ_MASK) >> RXTXBB_RXTXBB1_PDHIQ_LSB) +#define RXTXBB_RXTXBB1_PDHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDHIQ_LSB) & RXTXBB_RXTXBB1_PDHIQ_MASK) + +#define RXTXBB_RXTXBB2_ADDRESS 0x00000054 +#define RXTXBB_RXTXBB2_OFFSET 0x00000054 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MSB 31 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB 29 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK 0xe0000000 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB) +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK) +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MSB 28 +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB 26 +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK 0x1c000000 +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB) +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK) +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MSB 25 +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB 23 +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK 0x03800000 +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB) +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK) +#define RXTXBB_RXTXBB2_SPARE_MSB 22 +#define RXTXBB_RXTXBB2_SPARE_LSB 21 +#define RXTXBB_RXTXBB2_SPARE_MASK 0x00600000 +#define RXTXBB_RXTXBB2_SPARE_GET(x) (((x) & RXTXBB_RXTXBB2_SPARE_MASK) >> RXTXBB_RXTXBB2_SPARE_LSB) +#define RXTXBB_RXTXBB2_SPARE_SET(x) (((x) << RXTXBB_RXTXBB2_SPARE_LSB) & RXTXBB_RXTXBB2_SPARE_MASK) +#define RXTXBB_RXTXBB2_SHORTBUFFER_MSB 20 +#define RXTXBB_RXTXBB2_SHORTBUFFER_LSB 20 +#define RXTXBB_RXTXBB2_SHORTBUFFER_MASK 0x00100000 +#define RXTXBB_RXTXBB2_SHORTBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK) >> RXTXBB_RXTXBB2_SHORTBUFFER_LSB) +#define RXTXBB_RXTXBB2_SHORTBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SHORTBUFFER_LSB) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK) +#define RXTXBB_RXTXBB2_SELBUFFER_MSB 19 +#define RXTXBB_RXTXBB2_SELBUFFER_LSB 19 +#define RXTXBB_RXTXBB2_SELBUFFER_MASK 0x00080000 +#define RXTXBB_RXTXBB2_SELBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SELBUFFER_MASK) >> RXTXBB_RXTXBB2_SELBUFFER_LSB) +#define RXTXBB_RXTXBB2_SELBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SELBUFFER_LSB) & RXTXBB_RXTXBB2_SELBUFFER_MASK) +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MSB 18 +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB 18 +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK 0x00040000 +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK) +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MSB 17 +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB 17 +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK 0x00020000 +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK) +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MSB 16 +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB 16 +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK 0x00010000 +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK) +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MSB 15 +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB 15 +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK 0x00008000 +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK) +#define RXTXBB_RXTXBB2_CMSEL_MSB 14 +#define RXTXBB_RXTXBB2_CMSEL_LSB 13 +#define RXTXBB_RXTXBB2_CMSEL_MASK 0x00006000 +#define RXTXBB_RXTXBB2_CMSEL_GET(x) (((x) & RXTXBB_RXTXBB2_CMSEL_MASK) >> RXTXBB_RXTXBB2_CMSEL_LSB) +#define RXTXBB_RXTXBB2_CMSEL_SET(x) (((x) << RXTXBB_RXTXBB2_CMSEL_LSB) & RXTXBB_RXTXBB2_CMSEL_MASK) +#define RXTXBB_RXTXBB2_FILTERFC_MSB 12 +#define RXTXBB_RXTXBB2_FILTERFC_LSB 8 +#define RXTXBB_RXTXBB2_FILTERFC_MASK 0x00001f00 +#define RXTXBB_RXTXBB2_FILTERFC_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERFC_MASK) >> RXTXBB_RXTXBB2_FILTERFC_LSB) +#define RXTXBB_RXTXBB2_FILTERFC_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERFC_LSB) & RXTXBB_RXTXBB2_FILTERFC_MASK) +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MSB 7 +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB 7 +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK 0x00000080 +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_GET(x) (((x) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK) >> RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB) +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_SET(x) (((x) << RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK) +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MSB 6 +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB 6 +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK 0x00000040 +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK) >> RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB) +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK) +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MSB 5 +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB 5 +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK 0x00000020 +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MSB 4 +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB 4 +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK 0x00000010 +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MSB 3 +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB 3 +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK 0x00000008 +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MSB 2 +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB 2 +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK 0x00000004 +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MSB 1 +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB 1 +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK 0x00000002 +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MSB 0 +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB 0 +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK 0x00000001 +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_GET(x) (((x) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK) >> RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB) +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_SET(x) (((x) << RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK) + +#define RXTXBB_RXTXBB3_ADDRESS 0x00000058 +#define RXTXBB_RXTXBB3_OFFSET 0x00000058 +#define RXTXBB_RXTXBB3_SPARE_MSB 31 +#define RXTXBB_RXTXBB3_SPARE_LSB 27 +#define RXTXBB_RXTXBB3_SPARE_MASK 0xf8000000 +#define RXTXBB_RXTXBB3_SPARE_GET(x) (((x) & RXTXBB_RXTXBB3_SPARE_MASK) >> RXTXBB_RXTXBB3_SPARE_LSB) +#define RXTXBB_RXTXBB3_SPARE_SET(x) (((x) << RXTXBB_RXTXBB3_SPARE_LSB) & RXTXBB_RXTXBB3_SPARE_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MSB 26 +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB 24 +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK 0x07000000 +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MSB 23 +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB 21 +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK 0x00e00000 +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MSB 20 +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB 18 +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK 0x001c0000 +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MSB 17 +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB 15 +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK 0x00038000 +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MSB 14 +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB 12 +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK 0x00007000 +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MSB 11 +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB 9 +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK 0x00000e00 +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MSB 8 +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB 6 +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK 0x000001c0 +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MSB 5 +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB 3 +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK 0x00000038 +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK) >> RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MSB 2 +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB 0 +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK 0x00000007 +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK) + +#define RXTXBB_RXTXBB4_ADDRESS 0x0000005c +#define RXTXBB_RXTXBB4_OFFSET 0x0000005c +#define RXTXBB_RXTXBB4_SPARE_MSB 31 +#define RXTXBB_RXTXBB4_SPARE_LSB 31 +#define RXTXBB_RXTXBB4_SPARE_MASK 0x80000000 +#define RXTXBB_RXTXBB4_SPARE_GET(x) (((x) & RXTXBB_RXTXBB4_SPARE_MASK) >> RXTXBB_RXTXBB4_SPARE_LSB) +#define RXTXBB_RXTXBB4_SPARE_SET(x) (((x) << RXTXBB_RXTXBB4_SPARE_LSB) & RXTXBB_RXTXBB4_SPARE_MASK) +#define RXTXBB_RXTXBB4_LOCALOFFSET_MSB 30 +#define RXTXBB_RXTXBB4_LOCALOFFSET_LSB 30 +#define RXTXBB_RXTXBB4_LOCALOFFSET_MASK 0x40000000 +#define RXTXBB_RXTXBB4_LOCALOFFSET_GET(x) (((x) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK) >> RXTXBB_RXTXBB4_LOCALOFFSET_LSB) +#define RXTXBB_RXTXBB4_LOCALOFFSET_SET(x) (((x) << RXTXBB_RXTXBB4_LOCALOFFSET_LSB) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRHII_MSB 29 +#define RXTXBB_RXTXBB4_OFSTCORRHII_LSB 25 +#define RXTXBB_RXTXBB4_OFSTCORRHII_MASK 0x3e000000 +#define RXTXBB_RXTXBB4_OFSTCORRHII_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHII_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRHII_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRHII_LSB) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MSB 24 +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB 20 +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK 0x01f00000 +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRLOI_MSB 19 +#define RXTXBB_RXTXBB4_OFSTCORRLOI_LSB 15 +#define RXTXBB_RXTXBB4_OFSTCORRLOI_MASK 0x000f8000 +#define RXTXBB_RXTXBB4_OFSTCORRLOI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOI_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRLOI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRLOI_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MSB 14 +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB 10 +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK 0x00007c00 +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MSB 9 +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB 5 +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK 0x000003e0 +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MSB 4 +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB 0 +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK 0x0000001f +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK) + +#define ADDAC_ADDAC1_ADDRESS 0x00000060 +#define ADDAC_ADDAC1_OFFSET 0x00000060 +#define ADDAC_ADDAC1_PLL_SVREG_MSB 31 +#define ADDAC_ADDAC1_PLL_SVREG_LSB 31 +#define ADDAC_ADDAC1_PLL_SVREG_MASK 0x80000000 +#define ADDAC_ADDAC1_PLL_SVREG_GET(x) (((x) & ADDAC_ADDAC1_PLL_SVREG_MASK) >> ADDAC_ADDAC1_PLL_SVREG_LSB) +#define ADDAC_ADDAC1_PLL_SVREG_SET(x) (((x) << ADDAC_ADDAC1_PLL_SVREG_LSB) & ADDAC_ADDAC1_PLL_SVREG_MASK) +#define ADDAC_ADDAC1_PLL_SCLAMP_MSB 30 +#define ADDAC_ADDAC1_PLL_SCLAMP_LSB 28 +#define ADDAC_ADDAC1_PLL_SCLAMP_MASK 0x70000000 +#define ADDAC_ADDAC1_PLL_SCLAMP_GET(x) (((x) & ADDAC_ADDAC1_PLL_SCLAMP_MASK) >> ADDAC_ADDAC1_PLL_SCLAMP_LSB) +#define ADDAC_ADDAC1_PLL_SCLAMP_SET(x) (((x) << ADDAC_ADDAC1_PLL_SCLAMP_LSB) & ADDAC_ADDAC1_PLL_SCLAMP_MASK) +#define ADDAC_ADDAC1_PLL_ATB_MSB 27 +#define ADDAC_ADDAC1_PLL_ATB_LSB 26 +#define ADDAC_ADDAC1_PLL_ATB_MASK 0x0c000000 +#define ADDAC_ADDAC1_PLL_ATB_GET(x) (((x) & ADDAC_ADDAC1_PLL_ATB_MASK) >> ADDAC_ADDAC1_PLL_ATB_LSB) +#define ADDAC_ADDAC1_PLL_ATB_SET(x) (((x) << ADDAC_ADDAC1_PLL_ATB_LSB) & ADDAC_ADDAC1_PLL_ATB_MASK) +#define ADDAC_ADDAC1_PLL_ICP_MSB 25 +#define ADDAC_ADDAC1_PLL_ICP_LSB 23 +#define ADDAC_ADDAC1_PLL_ICP_MASK 0x03800000 +#define ADDAC_ADDAC1_PLL_ICP_GET(x) (((x) & ADDAC_ADDAC1_PLL_ICP_MASK) >> ADDAC_ADDAC1_PLL_ICP_LSB) +#define ADDAC_ADDAC1_PLL_ICP_SET(x) (((x) << ADDAC_ADDAC1_PLL_ICP_LSB) & ADDAC_ADDAC1_PLL_ICP_MASK) +#define ADDAC_ADDAC1_PLL_FILTER_MSB 22 +#define ADDAC_ADDAC1_PLL_FILTER_LSB 15 +#define ADDAC_ADDAC1_PLL_FILTER_MASK 0x007f8000 +#define ADDAC_ADDAC1_PLL_FILTER_GET(x) (((x) & ADDAC_ADDAC1_PLL_FILTER_MASK) >> ADDAC_ADDAC1_PLL_FILTER_LSB) +#define ADDAC_ADDAC1_PLL_FILTER_SET(x) (((x) << ADDAC_ADDAC1_PLL_FILTER_LSB) & ADDAC_ADDAC1_PLL_FILTER_MASK) +#define ADDAC_ADDAC1_PWDPLL_MSB 14 +#define ADDAC_ADDAC1_PWDPLL_LSB 14 +#define ADDAC_ADDAC1_PWDPLL_MASK 0x00004000 +#define ADDAC_ADDAC1_PWDPLL_GET(x) (((x) & ADDAC_ADDAC1_PWDPLL_MASK) >> ADDAC_ADDAC1_PWDPLL_LSB) +#define ADDAC_ADDAC1_PWDPLL_SET(x) (((x) << ADDAC_ADDAC1_PWDPLL_LSB) & ADDAC_ADDAC1_PWDPLL_MASK) +#define ADDAC_ADDAC1_PWDADC_MSB 13 +#define ADDAC_ADDAC1_PWDADC_LSB 13 +#define ADDAC_ADDAC1_PWDADC_MASK 0x00002000 +#define ADDAC_ADDAC1_PWDADC_GET(x) (((x) & ADDAC_ADDAC1_PWDADC_MASK) >> ADDAC_ADDAC1_PWDADC_LSB) +#define ADDAC_ADDAC1_PWDADC_SET(x) (((x) << ADDAC_ADDAC1_PWDADC_LSB) & ADDAC_ADDAC1_PWDADC_MASK) +#define ADDAC_ADDAC1_PWDDAC_MSB 12 +#define ADDAC_ADDAC1_PWDDAC_LSB 12 +#define ADDAC_ADDAC1_PWDDAC_MASK 0x00001000 +#define ADDAC_ADDAC1_PWDDAC_GET(x) (((x) & ADDAC_ADDAC1_PWDDAC_MASK) >> ADDAC_ADDAC1_PWDDAC_LSB) +#define ADDAC_ADDAC1_PWDDAC_SET(x) (((x) << ADDAC_ADDAC1_PWDDAC_LSB) & ADDAC_ADDAC1_PWDDAC_MASK) +#define ADDAC_ADDAC1_FORCEMSBLOW_MSB 11 +#define ADDAC_ADDAC1_FORCEMSBLOW_LSB 11 +#define ADDAC_ADDAC1_FORCEMSBLOW_MASK 0x00000800 +#define ADDAC_ADDAC1_FORCEMSBLOW_GET(x) (((x) & ADDAC_ADDAC1_FORCEMSBLOW_MASK) >> ADDAC_ADDAC1_FORCEMSBLOW_LSB) +#define ADDAC_ADDAC1_FORCEMSBLOW_SET(x) (((x) << ADDAC_ADDAC1_FORCEMSBLOW_LSB) & ADDAC_ADDAC1_FORCEMSBLOW_MASK) +#define ADDAC_ADDAC1_SELMANPWDS_MSB 10 +#define ADDAC_ADDAC1_SELMANPWDS_LSB 10 +#define ADDAC_ADDAC1_SELMANPWDS_MASK 0x00000400 +#define ADDAC_ADDAC1_SELMANPWDS_GET(x) (((x) & ADDAC_ADDAC1_SELMANPWDS_MASK) >> ADDAC_ADDAC1_SELMANPWDS_LSB) +#define ADDAC_ADDAC1_SELMANPWDS_SET(x) (((x) << ADDAC_ADDAC1_SELMANPWDS_LSB) & ADDAC_ADDAC1_SELMANPWDS_MASK) +#define ADDAC_ADDAC1_INV_CLK160_ADC_MSB 9 +#define ADDAC_ADDAC1_INV_CLK160_ADC_LSB 9 +#define ADDAC_ADDAC1_INV_CLK160_ADC_MASK 0x00000200 +#define ADDAC_ADDAC1_INV_CLK160_ADC_GET(x) (((x) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK) >> ADDAC_ADDAC1_INV_CLK160_ADC_LSB) +#define ADDAC_ADDAC1_INV_CLK160_ADC_SET(x) (((x) << ADDAC_ADDAC1_INV_CLK160_ADC_LSB) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK) +#define ADDAC_ADDAC1_CM_SEL_MSB 8 +#define ADDAC_ADDAC1_CM_SEL_LSB 7 +#define ADDAC_ADDAC1_CM_SEL_MASK 0x00000180 +#define ADDAC_ADDAC1_CM_SEL_GET(x) (((x) & ADDAC_ADDAC1_CM_SEL_MASK) >> ADDAC_ADDAC1_CM_SEL_LSB) +#define ADDAC_ADDAC1_CM_SEL_SET(x) (((x) << ADDAC_ADDAC1_CM_SEL_LSB) & ADDAC_ADDAC1_CM_SEL_MASK) +#define ADDAC_ADDAC1_DISABLE_DAC_REG_MSB 6 +#define ADDAC_ADDAC1_DISABLE_DAC_REG_LSB 6 +#define ADDAC_ADDAC1_DISABLE_DAC_REG_MASK 0x00000040 +#define ADDAC_ADDAC1_DISABLE_DAC_REG_GET(x) (((x) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK) >> ADDAC_ADDAC1_DISABLE_DAC_REG_LSB) +#define ADDAC_ADDAC1_DISABLE_DAC_REG_SET(x) (((x) << ADDAC_ADDAC1_DISABLE_DAC_REG_LSB) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK) +#define ADDAC_ADDAC1_SPARE_MSB 5 +#define ADDAC_ADDAC1_SPARE_LSB 0 +#define ADDAC_ADDAC1_SPARE_MASK 0x0000003f +#define ADDAC_ADDAC1_SPARE_GET(x) (((x) & ADDAC_ADDAC1_SPARE_MASK) >> ADDAC_ADDAC1_SPARE_LSB) +#define ADDAC_ADDAC1_SPARE_SET(x) (((x) << ADDAC_ADDAC1_SPARE_LSB) & ADDAC_ADDAC1_SPARE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct analog_reg_reg_s { + volatile unsigned int synth_synth1; + volatile unsigned int synth_synth2; + volatile unsigned int synth_synth3; + volatile unsigned int synth_synth4; + volatile unsigned int synth_synth5; + volatile unsigned int synth_synth6; + volatile unsigned int synth_synth7; + volatile unsigned int synth_synth8; + volatile unsigned int rf5g_rf5g1; + volatile unsigned int rf5g_rf5g2; + volatile unsigned int rf2g_rf2g1; + volatile unsigned int rf2g_rf2g2; + volatile unsigned int top_gain; + volatile unsigned int top_top; + volatile unsigned int bias_bias_sel; + volatile unsigned int bias_bias1; + volatile unsigned int bias_bias2; + volatile unsigned int bias_bias3; + volatile unsigned int txpc_txpc; + volatile unsigned int txpc_misc; + volatile unsigned int rxtxbb_rxtxbb1; + volatile unsigned int rxtxbb_rxtxbb2; + volatile unsigned int rxtxbb_rxtxbb3; + volatile unsigned int rxtxbb_rxtxbb4; + volatile unsigned int addac_addac1; +} analog_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _ANALOG_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/apb_map.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/apb_map.h --- linux-2.6.26/drivers/net/wireless/ath6k22/apb_map.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/apb_map.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,36 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _APB_MAP_H_ +#define _APB_MAP_H_ + +#define RTC_BASE_ADDRESS 0x00004000 +#define VMC_BASE_ADDRESS 0x00008000 +#define UART_BASE_ADDRESS 0x0000c000 +#define SI_BASE_ADDRESS 0x00010000 +#define GPIO_BASE_ADDRESS 0x00014000 +#define MBOX_BASE_ADDRESS 0x00018000 +#define ANALOG_INTF_BASE_ADDRESS 0x0001c000 +#define MAC_BASE_ADDRESS 0x00020000 + +#endif /* _APB_MAP_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/ar6000_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6000_api.h --- linux-2.6.26/drivers/net/wireless/ath6k22/ar6000_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6000_api.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,46 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the API to access the OS dependent atheros host driver +// by the WMI or WLAN generic modules. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _AR6000_API_H_ +#define _AR6000_API_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "ar6xapi_linux.h" +#endif + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/ar6xapi_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/ar6xapi_wince.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/ar6xapi_rexos.h" +#endif + +#endif /* _AR6000_API_H */ + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/ar6000_diag.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6000_diag.h --- linux-2.6.26/drivers/net/wireless/ath6k22/ar6000_diag.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6000_diag.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,42 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef AR6000_DIAG_H_ +#define AR6000_DIAG_H_ + + +A_STATUS +ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS +ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS +ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length); + +A_STATUS +ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length); + +#endif /*AR6000_DIAG_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/ar6000_drv.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6000_drv.c --- linux-2.6.26/drivers/net/wireless/ath6k22/ar6000_drv.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6000_drv.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,4475 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +/* + * This driver is a pseudo ethernet driver to access the Atheros AR6000 + * WLAN Device + */ +static const char athId[] __attribute__ ((unused)) = "$Id: //depot/sw/releases/olca2.2/host/os/linux/ar6000_drv.c#28 $"; + +/* ATHENV */ +#include +/* ATHENV */ + +#include "ar6000_drv.h" +#include "htc.h" +#include "engine.h" +#include "wmi_filter_linux.h" + +#define IS_MAC_NULL(mac) (mac[0]==0 && mac[1]==0 && mac[2]==0 && mac[3]==0 && mac[4]==0 && mac[5]==0) + +MODULE_LICENSE("GPL and additional rights"); + +#ifndef REORG_APTC_HEURISTICS +#undef ADAPTIVE_POWER_THROUGHPUT_CONTROL +#endif /* REORG_APTC_HEURISTICS */ + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +#define APTC_TRAFFIC_SAMPLING_INTERVAL 100 /* msec */ +#define APTC_UPPER_THROUGHPUT_THRESHOLD 3000 /* Kbps */ +#define APTC_LOWER_THROUGHPUT_THRESHOLD 2000 /* Kbps */ + +typedef struct aptc_traffic_record { + A_BOOL timerScheduled; + struct timeval samplingTS; + unsigned long bytesReceived; + unsigned long bytesTransmitted; +} APTC_TRAFFIC_RECORD; + +A_TIMER aptcTimer; +APTC_TRAFFIC_RECORD aptcTR; +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +unsigned int processDot11Hdr = 0; +/* ATHENV */ +#ifdef ANDROID_ENV +int bmienable = 1; +#else +int bmienable = 0; +#endif +/* ATHENV */ + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +char ifname[IFNAMSIZ] = {0,}; +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) */ + +int fwloadenable = 0; +unsigned int bypasswmi = 0; +unsigned int debuglevel = 0; +int tspecCompliance = ATHEROS_COMPLIANCE; +unsigned int busspeedlow = 0; +unsigned int onebitmode = 0; +unsigned int skipflash = 0; +unsigned int wmitimeout = 2; +unsigned int wlanNodeCaching = 1; +unsigned int enableuartprint = 0; +unsigned int logWmiRawMsgs = 0; +unsigned int enabletimerwar = 0; +unsigned int fwmode = 1; +unsigned int mbox_yield_limit = 99; +int reduce_credit_dribble = 1 + HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF; +int allow_trace_signal = 0; +/* ATHENV */ +#ifdef ANDROID_ENV +int work_mode = 0; +char *tgt_fw = "/system/wifi/athwlan.bin.z77"; +char *tgt_patch = "/system/wifi/data.patch.hw2_0.bin"; +char *tcmd_fw = "/system/wifi/athtcmd_ram.bin"; +static char *art_fw = "/system/wifi/device.bin"; +char *eeprom_bin = "/system/wifi/eeprom.bin"; +#ifdef FAKE_EEPROM_USED +char *eeprom_data = "/system/wifi/fakeBoardData_AR6002.bin"; +#else +char *eeprom_data = "/system/wifi/eeprom.data"; +#endif +#endif /* ANDROID_ENV */ +char *fm_path=NULL; +/* ATHENV */ +#ifdef CONFIG_HOST_TCMD_SUPPORT +unsigned int testmode =0; +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param_string(ifname, ifname, sizeof(ifname), 0644); +module_param(fwloadenable, int, 0644); +module_param(bmienable, int, 0644); +module_param(bypasswmi, int, 0644); +module_param(debuglevel, int, 0644); +module_param(tspecCompliance, int, 0644); +module_param(onebitmode, int, 0644); +module_param(busspeedlow, int, 0644); +module_param(skipflash, int, 0644); +module_param(wmitimeout, int, 0644); +module_param(wlanNodeCaching, int, 0644); +module_param(logWmiRawMsgs, int, 0644); +module_param(enableuartprint, int, 0644); +module_param(enabletimerwar, int, 0644); +module_param(fwmode, int, 0644); +module_param(mbox_yield_limit, int, 0644); +module_param(reduce_credit_dribble, int, 0644); +module_param(allow_trace_signal, int, 0644); +module_param(processDot11Hdr, int, 0644); +/* ATHENV */ +#ifdef ANDROID_ENV +module_param(work_mode, int, 0644); +module_param(tgt_fw, charp, S_IRUGO); +module_param(tgt_patch, charp, S_IRUGO); +module_param(eeprom_bin, charp, S_IRUGO); +module_param(eeprom_data, charp, S_IRUGO); +#endif +module_param(fm_path,charp,S_IRUGO); +/* ATHENV */ +#ifdef CONFIG_HOST_TCMD_SUPPORT +module_param(testmode, int, 0644); +#endif +#else + +#define __user +/* for linux 2.4 and lower */ +MODULE_PARM(bmienable,"i"); +MODULE_PARM(fwloadenable,"i"); +MODULE_PARM(bypasswmi,"i"); +MODULE_PARM(debuglevel, "i"); +MODULE_PARM(onebitmode,"i"); +MODULE_PARM(busspeedlow, "i"); +MODULE_PARM(skipflash, "i"); +MODULE_PARM(wmitimeout, "i"); +MODULE_PARM(wlanNodeCaching, "i"); +MODULE_PARM(enableuartprint,"i"); +MODULE_PARM(logWmiRawMsgs, "i"); +MODULE_PARM(enabletimerwar,"i"); +MODULE_PARM(fwmode,"i"); +MODULE_PARM(mbox_yield_limit,"i"); +MODULE_PARM(reduce_credit_dribble,"i"); +MODULE_PARM(allow_trace_signal,"i"); +MODULE_PARM(processDot11Hdr,"i"); +#ifdef CONFIG_HOST_TCMD_SUPPORT +MODULE_PARM(testmode, "i"); +#endif +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10) +/* in 2.6.10 and later this is now a pointer to a uint */ +unsigned int _mboxnum = HTC_MAILBOX_NUM_MAX; +#define mboxnum &_mboxnum +#else +unsigned int mboxnum = HTC_MAILBOX_NUM_MAX; +#endif + +#ifdef DEBUG +A_UINT32 g_dbg_flags = DBG_DEFAULTS; +unsigned int debugflags = 0; +int debugdriver = 1; +unsigned int debughtc = 128; +unsigned int debugbmi = 1; +unsigned int debughif = 2; +unsigned int txcreditsavailable[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int txcreditsconsumed[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int txcreditintrenable[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int txcreditintrenableaggregate[HTC_MAILBOX_NUM_MAX] = {0}; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param(debugflags, int, 0644); +module_param(debugdriver, int, 0644); +module_param(debughtc, int, 0644); +module_param(debugbmi, int, 0644); +module_param(debughif, int, 0644); +module_param_array(txcreditsavailable, int, mboxnum, 0644); +module_param_array(txcreditsconsumed, int, mboxnum, 0644); +module_param_array(txcreditintrenable, int, mboxnum, 0644); +module_param_array(txcreditintrenableaggregate, int, mboxnum, 0644); +#else +/* linux 2.4 and lower */ +MODULE_PARM(debugflags,"i"); +MODULE_PARM(debugdriver, "i"); +MODULE_PARM(debughtc, "i"); +MODULE_PARM(debugbmi, "i"); +MODULE_PARM(debughif, "i"); +MODULE_PARM(txcreditsavailable, "0-3i"); +MODULE_PARM(txcreditsconsumed, "0-3i"); +MODULE_PARM(txcreditintrenable, "0-3i"); +MODULE_PARM(txcreditintrenableaggregate, "0-3i"); +#endif + +#endif /* DEBUG */ + +unsigned int resetok = 1; +unsigned int tx_attempt[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int tx_post[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int tx_complete[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int hifBusRequestNumMax = 40; +unsigned int war23838_disabled = 0; +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +unsigned int enableAPTCHeuristics = 1; +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param_array(tx_attempt, int, mboxnum, 0644); +module_param_array(tx_post, int, mboxnum, 0644); +module_param_array(tx_complete, int, mboxnum, 0644); +module_param(hifBusRequestNumMax, int, 0644); +module_param(war23838_disabled, int, 0644); +module_param(resetok, int, 0644); +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +module_param(enableAPTCHeuristics, int, 0644); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ +#else +MODULE_PARM(tx_attempt, "0-3i"); +MODULE_PARM(tx_post, "0-3i"); +MODULE_PARM(tx_complete, "0-3i"); +MODULE_PARM(hifBusRequestNumMax, "i"); +MODULE_PARM(war23838_disabled, "i"); +MODULE_PARM(resetok, "i"); +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +MODULE_PARM(enableAPTCHeuristics, "i"); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ +#endif + +#ifdef BLOCK_TX_PATH_FLAG +int blocktx = 0; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param(blocktx, int, 0644); +#else +MODULE_PARM(blocktx, "i"); +#endif +#endif /* BLOCK_TX_PATH_FLAG */ + + +int reconnect_flag = 0; + +char tgt_fw_path[100]; +char tgt_patch_path[100]; +char eeprom_bin_path[100]; +char eeprom_data_path[100]; + +/* Function declarations */ +static int ar6000_init_module(void); +static void ar6000_cleanup_module(void); + +int ar6000_init(struct net_device *dev); +static int ar6000_open(struct net_device *dev); +static int ar6000_close(struct net_device *dev); +static void ar6000_init_control_info(AR_SOFTC_T *ar); +static int ar6000_data_tx(struct sk_buff *skb, struct net_device *dev); + +static void ar6000_destroy(struct net_device *dev, unsigned int unregister); +static void ar6000_detect_error(unsigned long ptr); +static struct net_device_stats *ar6000_get_stats(struct net_device *dev); +static struct iw_statistics *ar6000_get_iwstats(struct net_device * dev); + +static void disconnect_timer_handler(unsigned long ptr); + +/* + * HTC service connection handlers + */ +static A_STATUS ar6000_avail_ev(void *context, void *hif_handle); + +static A_STATUS ar6000_unavail_ev(void *context, void *hif_handle); + +static void ar6000_target_failure(void *Instance, A_STATUS Status); + +static void ar6000_rx(void *Context, HTC_PACKET *pPacket); + +static void ar6000_rx_refill(void *Context,HTC_ENDPOINT_ID Endpoint); + +static void ar6000_tx_complete(void *Context, HTC_PACKET *pPacket); + +static HTC_SEND_FULL_ACTION ar6000_tx_queue_full(void *Context, HTC_PACKET *pPacket); + +static void deliver_frames_to_nw_stack(struct sk_buff *skb); + +/* + * Static variables + */ + +static struct net_device *ar6000_devices[MAX_AR6000]; +extern struct iw_handler_def ath_iw_handler_def; +DECLARE_WAIT_QUEUE_HEAD(arEvent); +DECLARE_WAIT_QUEUE_HEAD(ar6000_scan_queue); +static void ar6000_cookie_init(AR_SOFTC_T *ar); +static void ar6000_cookie_cleanup(AR_SOFTC_T *ar); +static void ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie); +static struct ar_cookie *ar6000_alloc_cookie(AR_SOFTC_T *ar); + +#ifdef USER_KEYS +static A_STATUS ar6000_reinstall_keys(AR_SOFTC_T *ar,A_UINT8 key_op_ctrl); +#endif + + +static struct ar_cookie s_ar_cookie_mem[MAX_COOKIE_NUM]; + +#define HOST_INTEREST_ITEM_ADDRESS(ar, item) \ + (((ar)->arTargetType == TARGET_TYPE_AR6001) ? AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((ar)->arTargetType == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((ar)->arTargetType == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : 0))) + + +/* Debug log support */ + +/* + * Flag to govern whether the debug logs should be parsed in the kernel + * or reported to the application. + */ +#define REPORT_DEBUG_LOGS_TO_APP + +A_STATUS +ar6000_set_host_app_area(AR_SOFTC_T *ar) +{ + A_UINT32 address, data; + struct host_app_area_s host_app_area; + + /* Fetch the address of the host_app_area_s instance in the host interest area */ + address = TARG_VTOP(ar->arTargetType, HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest)); + if (ar6000_ReadRegDiag(ar->arHifDevice, &address, &data) != A_OK) { + return A_ERROR; + } + address = TARG_VTOP(ar->arTargetType, data); + host_app_area.wmi_protocol_ver = WMI_PROTOCOL_VERSION; + if (ar6000_WriteDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&host_app_area, + sizeof(struct host_app_area_s)) != A_OK) + { + return A_ERROR; + } + + return A_OK; +} + +A_UINT32 +dbglog_get_debug_hdr_ptr(AR_SOFTC_T *ar) +{ + A_UINT32 param; + A_UINT32 address; + A_STATUS status; + + address = TARG_VTOP(ar->arTargetType, HOST_INTEREST_ITEM_ADDRESS(ar, hi_dbglog_hdr)); + if ((status = ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)¶m, 4)) != A_OK) + { + param = 0; + } + + return param; +} + +/* + * The dbglog module has been initialized. Its ok to access the relevant + * data stuctures over the diagnostic window. + */ +void +ar6000_dbglog_init_done(AR_SOFTC_T *ar) +{ + ar->dbglog_init_done = TRUE; +} + +A_UINT32 +dbglog_get_debug_fragment(A_INT8 *datap, A_UINT32 len, A_UINT32 limit) +{ + A_INT32 *buffer; + A_UINT32 count; + A_UINT32 numargs; + A_UINT32 length; + A_UINT32 fraglen; + + count = fraglen = 0; + buffer = (A_INT32 *)datap; + length = (limit >> 2); + + if (len <= limit) { + fraglen = len; + } else { + while (count < length) { + numargs = DBGLOG_GET_NUMARGS(buffer[count]); + fraglen = (count << 2); + count += numargs + 1; + } + } + + return fraglen; +} + +void +dbglog_parse_debug_logs(A_INT8 *datap, A_UINT32 len) +{ + A_INT32 *buffer; + A_UINT32 count; + A_UINT32 timestamp; + A_UINT32 debugid; + A_UINT32 moduleid; + A_UINT32 numargs; + A_UINT32 length; + + count = 0; + buffer = (A_INT32 *)datap; + length = (len >> 2); + while (count < length) { + debugid = DBGLOG_GET_DBGID(buffer[count]); + moduleid = DBGLOG_GET_MODULEID(buffer[count]); + numargs = DBGLOG_GET_NUMARGS(buffer[count]); + timestamp = DBGLOG_GET_TIMESTAMP(buffer[count]); + switch (numargs) { + case 0: + AR_DEBUG_PRINTF("%d %d (%d)\n", moduleid, debugid, timestamp); + break; + + case 1: + AR_DEBUG_PRINTF("%d %d (%d): 0x%x\n", moduleid, debugid, + timestamp, buffer[count+1]); + break; + + case 2: + AR_DEBUG_PRINTF("%d %d (%d): 0x%x, 0x%x\n", moduleid, debugid, + timestamp, buffer[count+1], buffer[count+2]); + break; + + default: + AR_DEBUG_PRINTF("Invalid args: %d\n", numargs); + } + count += numargs + 1; + } +} + +int +ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar) +{ + struct dbglog_hdr_s debug_hdr; + struct dbglog_buf_s debug_buf; + A_UINT32 address; + A_UINT32 length; + A_UINT32 dropped; + A_UINT32 firstbuf; + A_UINT32 debug_hdr_ptr; + + if (!ar->dbglog_init_done) return A_ERROR; + + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + if (ar->dbgLogFetchInProgress) { + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + return A_EBUSY; + } + + /* block out others */ + ar->dbgLogFetchInProgress = TRUE; + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + debug_hdr_ptr = dbglog_get_debug_hdr_ptr(ar); + printk("debug_hdr_ptr: 0x%x\n", debug_hdr_ptr); + + /* Get the contents of the ring buffer */ + if (debug_hdr_ptr) { + address = TARG_VTOP(ar->arTargetType, debug_hdr_ptr); + length = sizeof(struct dbglog_hdr_s); + ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&debug_hdr, length); + address = TARG_VTOP(ar->arTargetType, (A_UINT32)debug_hdr.dbuf); + firstbuf = address; + dropped = debug_hdr.dropped; + length = sizeof(struct dbglog_buf_s); + ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&debug_buf, length); + + do { + address = TARG_VTOP(ar->arTargetType, (A_UINT32)debug_buf.buffer); + length = debug_buf.length; + if ((length) && (debug_buf.length <= debug_buf.bufsize)) { + /* Rewind the index if it is about to overrun the buffer */ + if (ar->log_cnt > (DBGLOG_HOST_LOG_BUFFER_SIZE - length)) { + ar->log_cnt = 0; + } + if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&ar->log_buffer[ar->log_cnt], length)) + { + break; + } + ar6000_dbglog_event(ar, dropped, &ar->log_buffer[ar->log_cnt], length); + ar->log_cnt += length; + } else { + AR_DEBUG_PRINTF("Length: %d (Total size: %d)\n", + debug_buf.length, debug_buf.bufsize); + } + + address = TARG_VTOP(ar->arTargetType, (A_UINT32)debug_buf.next); + length = sizeof(struct dbglog_buf_s); + if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&debug_buf, length)) + { + break; + } + + } while (address != firstbuf); + } + + ar->dbgLogFetchInProgress = FALSE; + + return A_OK; +} + +void +ar6000_dbglog_event(AR_SOFTC_T *ar, A_UINT32 dropped, + A_INT8 *buffer, A_UINT32 length) +{ +#ifdef REPORT_DEBUG_LOGS_TO_APP + #define MAX_WIRELESS_EVENT_SIZE 252 + /* + * Break it up into chunks of MAX_WIRELESS_EVENT_SIZE bytes of messages. + * There seems to be a limitation on the length of message that could be + * transmitted to the user app via this mechanism. + */ + A_UINT32 send, sent; + + sent = 0; + send = dbglog_get_debug_fragment(&buffer[sent], length - sent, + MAX_WIRELESS_EVENT_SIZE); + while (send) { + ar6000_send_event_to_app(ar, WMIX_DBGLOG_EVENTID, &buffer[sent], send); + sent += send; + send = dbglog_get_debug_fragment(&buffer[sent], length - sent, + MAX_WIRELESS_EVENT_SIZE); + } +#else + AR_DEBUG_PRINTF("Dropped logs: 0x%x\nDebug info length: %d\n", + dropped, length); + + /* Interpret the debug logs */ + dbglog_parse_debug_logs(buffer, length); +#endif /* REPORT_DEBUG_LOGS_TO_APP */ +} + + + +static int __init +ar6000_init_module(void) +{ + static int probed = 0; + A_STATUS status; + OSDRV_CALLBACKS osdrvCallbacks; + +/* ATHENV */ +#ifdef ANDROID_ENV + if (work_mode == 1) { + printk("TCMD mode.\n"); + testmode = 1; + tgt_fw = tcmd_fw; + } else if (work_mode == 2) { + printk("ART mode.\n"); + enableuartprint = 1; + resetok = 0; + bypasswmi = 1; + tgt_fw = art_fw; + }else { + if(fm_path) { + strcat(tgt_fw_path,fm_path); + tgt_fw=strcat(tgt_fw_path,"/target/AR6002/hw2.0/bin/athwlan.bin.z77"); + strcat(tgt_patch_path,fm_path); + tgt_patch=strcat(tgt_patch_path,"/target/AR6002/hw2.0/bin/data.patch.hw2_0.bin"); + strcat(eeprom_bin_path,fm_path); + eeprom_bin=strcat(eeprom_bin_path,"/target/AR6002/hw2.0/bin/eeprom.bin"); + strcat(eeprom_data_path,fm_path); + eeprom_data=strcat(eeprom_data_path,"/target/AR6002/hw2.0/bin/eeprom.data"); + }else{ + tgt_fw = NULL; /* Indicate Avail routine to load fw from bmi loader */ + } + } +#endif +/* ATHENV */ + + A_MEMZERO(&osdrvCallbacks,sizeof(osdrvCallbacks)); + osdrvCallbacks.deviceInsertedHandler = ar6000_avail_ev; + osdrvCallbacks.deviceRemovedHandler = ar6000_unavail_ev; + + printk(KERN_INFO "ar6000_init_module\n"); + +#ifdef DEBUG + /* Set the debug flags if specified at load time */ + if(debugflags != 0) + { + g_dbg_flags = debugflags; + } +#endif + + if (probed) { + return -ENODEV; + } + probed++; + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + memset(&aptcTR, 0, sizeof(APTC_TRAFFIC_RECORD)); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +#ifdef CONFIG_HOST_GPIO_SUPPORT + ar6000_gpio_init(); +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + + status = HIFInit(&osdrvCallbacks); + if(status != A_OK) + return -ENODEV; + + return 0; +} + +static void __exit +ar6000_cleanup_module(void) +{ + int i = 0; + struct net_device *ar6000_netdev; + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + /* Delete the Adaptive Power Control timer */ + if (timer_pending(&aptcTimer)) { + del_timer_sync(&aptcTimer); + } +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + + for (i=0; i < MAX_AR6000; i++) { + if (ar6000_devices[i] != NULL) { + ar6000_netdev = ar6000_devices[i]; + ar6000_devices[i] = NULL; + ar6000_destroy(ar6000_netdev, 1); + } + } + + HIFShutDownDevice(NULL); + + AR_DEBUG_PRINTF("ar6000_cleanup: success\n"); +} + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +void +aptcTimerHandler(unsigned long arg) +{ + A_UINT32 numbytes; + A_UINT32 throughput; + AR_SOFTC_T *ar; + A_STATUS status; + + ar = (AR_SOFTC_T *)arg; + A_ASSERT(ar != NULL); + A_ASSERT(!timer_pending(&aptcTimer)); + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + /* Get the number of bytes transferred */ + numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived; + aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0; + + /* Calculate and decide based on throughput thresholds */ + throughput = ((numbytes * 8)/APTC_TRAFFIC_SAMPLING_INTERVAL); /* Kbps */ + if (throughput < APTC_LOWER_THROUGHPUT_THRESHOLD) { + /* Enable Sleep and delete the timer */ + A_ASSERT(ar->arWmiReady == TRUE); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + status = wmi_powermode_cmd(ar->arWmi, REC_POWER); + AR6000_SPIN_LOCK(&ar->arLock, 0); + A_ASSERT(status == A_OK); + aptcTR.timerScheduled = FALSE; + } else { + A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0); + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); +} +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +/* ATHENV */ + +/* ATHENV */ +#ifdef ANDROID_ENV +extern void eeprom_ar6000_transfer(HIF_DEVICE *device, char *fake_file); +#endif +/* ATHENV */ + +#define MAX_BUF (8*1024) +/* #define A_ROUND_UP(x, y) ((((x)+((y)-1))/(y))*(y)) */ /* already defined in wmi_api.h */ + +/* ATHENV */ +#ifdef ANDROID_ENV +char * fw_buf; +static void firmware_transfer(HIF_DEVICE *device, char* filename, A_UINT32 address, A_BOOL isCompressed) +{ + struct file *filp; + struct inode *inode = NULL; + int length, remaining; + int length1; + A_STATUS ret; + mm_segment_t oldfs; + + + printk("%s: Enter, filename=%s\n", __FUNCTION__, filename); + + // Open file + oldfs = get_fs(); + set_fs(KERNEL_DS); + + filp = filp_open(filename, O_RDONLY, S_IRUSR); + if ( IS_ERR(filp) ) { + printk("%s: file %s filp_open error\n", __FUNCTION__, filename); + return; + } + if (!filp->f_op) { + printk("%s: File Operation Method Error\n", __FUNCTION__); + return; + } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + inode = filp->f_path.dentry->d_inode; +#else + inode = filp->f_dentry->d_inode; +#endif + + if (!inode) { + printk("%s: Get inode from filp failed\n", __FUNCTION__); + filp_close(filp, NULL); + return; + } + + printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos); + + fw_buf = (char*)kmalloc((MAX_BUF+12), GFP_KERNEL); + if (fw_buf==NULL) { + printk("%s: kernel memory alloc error\n", __FUNCTION__); + filp_close(filp, NULL); + return; + } + + length = i_size_read(inode->i_mapping->host); + if (length==0 ) { + printk("%s: Try to get file size error\n", __FUNCTION__); + goto Transfer_DONE; + } + printk("%s: length=%d, address=0x%x\n", __FUNCTION__, length, address); + + if ( isCompressed) { + ret = BMILZStreamStart(device, address); + if (ret != A_OK) { + printk("%s: BMILZStreamStart failed, ret=%d\n", __FUNCTION__, ret); + goto Transfer_DONE; + } + } + + remaining = length; + + while (remaining>0) { + length = (remaining > MAX_BUF)? MAX_BUF : remaining; + + if ( isCompressed ) { + ((A_UINT32 *)fw_buf)[((length-1)/4)] = 0; + } + + if (filp->f_op->read(filp, fw_buf, length, &filp->f_pos) != length) { + printk("%s: file read error, remaining=%d\n", __FUNCTION__, remaining); + goto Transfer_DONE; + } + + length1 = A_ROUND_UP(length, 4); + + if ( isCompressed ) { + printk("%s: BMILZData: len=%d, org_len=%d\n", __FUNCTION__, length1, length); + ret = BMILZData(device, fw_buf, length1); + if (ret != A_OK) { + printk("%s: BMILZData failed, ret=%d\n", __FUNCTION__, ret); + goto Transfer_DONE; + } + } else { + ret = BMIWriteMemory(device, address, fw_buf, length1); + if (ret != A_OK) { + printk("%s: BMIWriteMemory failed, ret=%d\n", __FUNCTION__, ret); + goto Transfer_DONE; + } + } + + remaining -= length; + address += length; + } + +Transfer_DONE: + kfree(fw_buf); + filp_close(filp, NULL); + set_fs(oldfs); +} + +#endif +/* ATHENV */ + + +#ifdef FW_AUTOLOAD +extern int fwengine( unsigned char *img, int size, void *ar); +extern int ar6k_reg_preload( int reg, unsigned int value ); + +/* Linux driver dependent utilities for fwengine */ +int load_binary( unsigned int addr, unsigned char *cp, void *arg ) +{ + int size = 0; + int adv = 5; + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + + cp++; + size |= ( *cp & 0xFF ); cp++; + size |= ( *cp & 0xFF ) << 8; cp++; + size |= ( *cp & 0xFF ) << 16; cp++; + size |= ( *cp & 0xFF ) << 24; cp++; + + if (BMIWriteMemory(ar->arHifDevice, addr, cp, size) != A_OK) + return(-1); + + adv += size; + return(adv); +} + +int execute_on_target( unsigned int address, unsigned int parm, void *arg ) +{ + int ret ; + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + ret = BMIExecute(ar->arHifDevice, address, &parm); + + return(ret); +} + +unsigned int get_target_reg( unsigned address, void *arg ) +{ + int ret ; + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + if (BMIReadMemory(ar->arHifDevice, address, (A_UCHAR *)&ret, 4)!= A_OK) { + /* And what am I supposed to do? */; + return( -1 ); + } + return( ret ); + +} + +int write_target_reg( unsigned address, unsigned value, void *arg ) +{ + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + if (BMIWriteMemory(ar->arHifDevice, address, (A_UCHAR *)&value, 4) != A_OK) + return(-1); + return(0); +} + +void bmidone( void *arg ) +{ + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + BMIDone(ar->arHifDevice); +} +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) +static struct device ar6kfwdev = { + .bus_id = "sdio0", +}; +#endif +#endif /* FW_AUTOLOAD */ + +/* + * HTC Event handlers + */ +static A_STATUS +ar6000_avail_ev(void *context, void *hif_handle) +{ + int i; + struct net_device *dev; + void *ar_netif; + AR_SOFTC_T *ar; + int device_index = 0; + A_UINT32 param; + HTC_INIT_INFO htcInfo; + + AR_DEBUG_PRINTF("ar6000_available\n"); + + for (i=0; i < MAX_AR6000; i++) { + if (ar6000_devices[i] == NULL) { + break; + } + } + + if (i == MAX_AR6000) { + AR_DEBUG_PRINTF("ar6000_available: max devices reached\n"); + return A_ERROR; + } + + /* Save this. It gives a bit better readability especially since */ + /* we use another local "i" variable below. */ + device_index = i; + +#ifdef CONFIG_MACH_LUIGI_LAB126 + dev = alloc_etherdev_ar6000(sizeof(AR_SOFTC_T)); +#else + dev = alloc_etherdev(sizeof(AR_SOFTC_T)); +#endif + if (dev == NULL) { + AR_DEBUG_PRINTF("ar6000_available: can't alloc etherdev\n"); + return A_ERROR; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + if (ifname[0]) + { + strcpy(dev->name, ifname); + } +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) */ + +#ifdef SET_MODULE_OWNER + SET_MODULE_OWNER(dev); +#endif + ether_setup(dev); + + ar_netif = netdev_priv(dev); + if (ar_netif == NULL) { + printk(KERN_CRIT "ar6000_available: Could not allocate memory\n"); + return A_ERROR; + } + + A_MEMZERO(ar_netif, sizeof(AR_SOFTC_T)); + + ar = (AR_SOFTC_T *)ar_netif; + ar->arNetDev = dev; + ar->arHifDevice = hif_handle; + ar->arWlanState = WLAN_ENABLED; + ar->arDeviceIndex = device_index; + + A_INIT_TIMER(&ar->arHBChallengeResp.timer, ar6000_detect_error, dev); + ar->arHBChallengeResp.seqNum = 0; + ar->arHBChallengeResp.outstanding = FALSE; + ar->arHBChallengeResp.missCnt = 0; + ar->arHBChallengeResp.frequency = AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT; + ar->arHBChallengeResp.missThres = AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT; + + ar6000_init_control_info(ar); + init_waitqueue_head(&arEvent); + sema_init(&ar->arSem, 1); + ar->bIsDestroyProgress = FALSE; + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + A_INIT_TIMER(&aptcTimer, aptcTimerHandler, ar); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + + A_INIT_TIMER(&ar->disconnect_timer, disconnect_timer_handler, dev); + + /* + * If requested, perform some magic which requires no cooperation from + * the Target. It causes the Target to ignore flash and execute to the + * OS from ROM. + * + * This is intended to support recovery from a corrupted flash on Targets + * that support flash. + */ + if (skipflash) + { + AR_DEBUG_PRINTF("Skip flash feature not supported\n"); + return A_ERROR; + } + + BMIInit(); + { + struct bmi_target_info targ_info; + + if (BMIGetTargetInfo(ar->arHifDevice, &targ_info) != A_OK) { + return A_ERROR; + } + + ar->arVersion.target_ver = targ_info.target_ver; + ar->arTargetType = targ_info.target_type; + + /* do any target-specific preparation that can be done through BMI */ + if (ar6000_prepare_target(ar->arHifDevice, + targ_info.target_type, + targ_info.target_ver) != A_OK) { + return A_ERROR; + } + + } + + if (enableuartprint) { + param = 1; + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_serial_enable), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for enableuartprint failed \n"); + return A_ERROR; + } + AR_DEBUG_PRINTF("Serial console prints enabled\n"); + } + + /* Tell target which HTC version it is used*/ + param = HTC_PROTOCOL_VERSION; + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for htc version failed \n"); + return A_ERROR; + } + +#ifdef CONFIG_HOST_TCMD_SUPPORT + if(testmode) { + ar->arTargetMode = AR6000_TCMD_MODE; + }else { + ar->arTargetMode = AR6000_WLAN_MODE; + } +#endif + if (enabletimerwar) { + A_UINT32 param; + + if (BMIReadMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIReadMemory for enabletimerwar failed \n"); + return A_ERROR; + } + + param |= HI_OPTION_TIMER_WAR; + + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for enabletimerwar failed \n"); + return A_ERROR; + } + AR_DEBUG_PRINTF("Timer WAR enabled\n"); + } + + /* set the firmware mode to STA/IBSS/AP */ + { + A_UINT32 param; + + if (BMIReadMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIReadMemory for setting fwmode failed \n"); + return A_ERROR; + } + + param |= (fwmode << HI_OPTION_FW_MODE_SHIFT); + + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for setting fwmode failed \n"); + return A_ERROR; + } + AR_DEBUG_PRINTF("Firmware mode set\n"); + } + + if (processDot11Hdr) { + A_UINT32 param; + + if (BMIReadMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIReadMemory for processDot11Hdr failed \n"); + return A_ERROR; + } + + param |= HI_OPTION_RELAY_DOT11_HDR; + + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for processDot11Hdr failed \n"); + return A_ERROR; + } + AR_DEBUG_PRINTF("processDot11Hdr enabled\n"); + } + + + // No need to reserve RAM space for patch as olca/dragon is flash based + if (ar->arTargetType == TARGET_TYPE_AR6001) { + param = 0; + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_end_RAM_reserve_sz), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for hi_end_RAM_reserve_sz failed \n"); + return A_ERROR; + } + } + + + /* since BMIInit is called in the driver layer, we have to set the block + * size here for the target */ + + if (A_FAILED(ar6000_set_htc_params(ar->arHifDevice, + ar->arTargetType, + mbox_yield_limit, + 0 /* use default number of control buffers */ + ))) { + return A_ERROR; + } + + A_MEMZERO(&htcInfo,sizeof(htcInfo)); + htcInfo.pContext = ar; + htcInfo.TargetFailure = ar6000_target_failure; + + ar->arHtcTarget = HTCCreate(ar->arHifDevice,&htcInfo); + + if (ar->arHtcTarget == NULL) { + return A_ERROR; + } + + spin_lock_init(&ar->arLock); + + /* Don't install the init function if BMI is requested */ + if(!bmienable) + { + dev->init = ar6000_init; + } else { + AR_DEBUG_PRINTF(" BMI enabled \n"); + } + + dev->open = &ar6000_open; + dev->stop = &ar6000_close; + dev->hard_start_xmit = &ar6000_data_tx; + dev->get_stats = &ar6000_get_stats; + + /* dev->tx_timeout = ar6000_tx_timeout; */ + dev->do_ioctl = &ar6000_ioctl; + dev->watchdog_timeo = AR6000_TX_TIMEOUT; + dev->wireless_handlers = &ath_iw_handler_def; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) + dev->get_wireless_stats = ar6000_get_iwstats; /*Displayed via proc fs */ +#else + ath_iw_handler_def.get_wireless_stats = ar6000_get_iwstats; /*Displayed via proc fs */ +#endif + + if (processDot11Hdr) { + dev->hard_header_len = sizeof(struct ieee80211_qosframe) + sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN; + } else { + /* + * We need the OS to provide us with more headroom in order to + * perform dix to 802.3, WMI header encap, and the HTC header + */ + dev->hard_header_len = ETH_HLEN + sizeof(ATH_LLC_SNAP_HDR) + + sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN; + } + + /* This runs the init function */ + if (register_netdev(dev)) { + AR_DEBUG_PRINTF("ar6000_avail: register_netdev failed\n"); + ar6000_destroy(dev, 0); + return A_ERROR; + } + + HIFClaimDevice(ar->arHifDevice, ar); + + /* We only register the device in the global list if we succeed. */ + /* If the device is in the global list, it will be destroyed */ + /* when the module is unloaded. */ + ar6000_devices[device_index] = dev; + + AR_DEBUG_PRINTF("ar6000_avail: name=%s hifdevice=0x%x, dev=0x%x (%d), ar=0x%x\n", + dev->name, (A_UINT32)ar->arHifDevice, (A_UINT32)dev, device_index, + (A_UINT32)ar); +/* ATHENV */ +#ifdef ANDROID_ENV + if (tgt_fw != NULL) { + A_UINT32 value, old_options, old_sleep; + A_STATUS ret; + + /* temporarily disable system sleep */ + value = 0; + BMIReadSOCRegister(ar->arHifDevice, 0x180c0, &value); + old_options = value; + value |= 0x08; + BMIWriteSOCRegister(ar->arHifDevice, 0x180c0, value); + value = 0; + BMIReadSOCRegister(ar->arHifDevice, 0x40c4, &value); + old_sleep = value; + value |= 0x01; + BMIWriteSOCRegister(ar->arHifDevice, 0x40c4, value); + printk("old options [%d] old sleep [%d]\n", old_options, old_sleep); + + /* run at 40/44MHz by default */ + value = 0; + BMIWriteSOCRegister(ar->arHifDevice, 0x4020, value); + + /* use internal clock? */ + BMIReadSOCRegister(ar->arHifDevice, 0x50047c, &value); + if (value == 0) { + printk("use internal clock\n"); + value = 0x100000; + BMIWriteSOCRegister(ar->arHifDevice, 0x40e0, value); + } + + /* eeprom */ +#ifdef FAKE_EEPROM_USED + printk("AR6000: download fake eeprom\n"); + eeprom_ar6000_transfer(ar->arHifDevice, eeprom_data, NULL); +#else + printk("AR6000: eeprom transfer\n"); + firmware_transfer(ar->arHifDevice, eeprom_data, 0x502070, FALSE); + firmware_transfer(ar->arHifDevice, eeprom_bin, 0x513950, FALSE); + value = 1; + printk("AR6000: BMIExecute\n"); + BMIExecute(ar->arHifDevice, 0x913950, &value); +#endif + printk("AR6000: BMISetAppStart\n"); + BMISetAppStart(ar->arHifDevice, 0x913950); + + /* enable HI_OPTION_TIMER_WAR */ + printk("AR6000: enable HI_OPTION_TIMER_WAR\n"); + value = 0; + BMIReadSOCRegister(ar->arHifDevice, 0x500410, &value); + value |= 0x01; + BMIWriteSOCRegister(ar->arHifDevice, 0x500410, value); + + /* fw */ + printk("AR6000: firmware_transfer\n"); + if ((tgt_fw[strlen(tgt_fw) - 3] == 'z') + && (tgt_fw[strlen(tgt_fw) - 2] == '7') + && (tgt_fw[strlen(tgt_fw) - 1] == '7')) { + firmware_transfer(ar->arHifDevice, tgt_fw, 0x502070, TRUE); + } else { + firmware_transfer(ar->arHifDevice, tgt_fw, 0x502070, FALSE); + } + + /* WLAN patch DataSets */ + firmware_transfer(ar->arHifDevice, tgt_patch, 0x52d6c8, FALSE); + BMIWriteSOCRegister(ar->arHifDevice, 0x500418, 0x52d6c8); + + /* restore system sleep */ + BMIWriteSOCRegister(ar->arHifDevice, 0x40c4, old_sleep); + BMIWriteSOCRegister(ar->arHifDevice, 0x180c0, old_options); + + if (work_mode == 2) { + /* art mode */ + BMIWriteSOCRegister(ar->arHifDevice, 0x500478, 26000000); + BMIWriteSOCRegister(ar->arHifDevice, 0x500458, 0x1); + } else { + /* normal WIFI or TCMD mode, done */ + ret = ar6000_init(dev); + if ( ret!= A_OK ) { + printk("%s: ar6000_init failed, ret=%d\n", __FUNCTION__, ret); + } + } + } +#endif +/* ATHENV */ + +#ifdef FW_AUTOLOAD + if( fwloadenable ) { + /* To compile firmware into driver the following struct should + * be declared static, it's field 'data' initialised with ptr to + * image and field 'size' with image size. 'request_firmware call + * in that case should be bypassed. TODO: #ifdef that + */ + const struct firmware *fw_entry; + int ret; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) + if(request_firmware(&fw_entry, "ar6k_firmware", &ar6kfwdev)!=0) { +#else + if(request_firmware(&fw_entry, "ar6k_firmware", &dev->dev)!=0) { +#endif +// if(request_firmware(NULL, "ar6k_firmware", &dev->dev)!=0) { + printk(KERN_ERR "ar6000_fwload: ar6k_firmware not available\n"); + ar6000_destroy(dev, 0); + return A_ERROR; + } else { + ar6k_reg_preload( 14, ar->arTargetType ); + ar6k_reg_preload( 15, ar->arVersion.target_ver ); + ret = fwengine(fw_entry->data, fw_entry->size, (void *)ar); + release_firmware(fw_entry); + if( ret ) { + printk(KERN_ERR "ar600_fwload: error loading firmware\n"); + ar6000_destroy(dev, 0); + return A_ERROR; + } + } + } +#endif /* FW_AUTOLOAD */ + + return A_OK; +} + +static void ar6000_target_failure(void *Instance, A_STATUS Status) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Instance; + WMI_TARGET_ERROR_REPORT_EVENT errEvent; + static A_BOOL sip = FALSE; + char buf[WMI_CONTROL_MSG_MAX_LEN]; + union iwreq_data wrqu; + + if (Status != A_OK) { + + printk(KERN_ERR "ar6000_target_failure: target asserted \n"); + + if (timer_pending(&ar->arHBChallengeResp.timer)) { + A_UNTIMEOUT(&ar->arHBChallengeResp.timer); + } + + /* try dumping target assertion information (if any) */ + ar6000_dump_target_assert_info(ar->arHifDevice,ar->arTargetType); + + /* + * Fetch the logs from the target via the diagnostic + * window. + */ + ar6000_dbglog_get_debug_logs(ar); + + /* Report the error only once */ + if (!sip) { + sip = TRUE; + errEvent.errorVal = WMI_TARGET_COM_ERR | + WMI_TARGET_FATAL_ERR; + + /* + * Send a generic event to supplicant. + */ + A_MEMZERO(buf, sizeof(buf)); + A_MEMZERO(&wrqu, sizeof(wrqu)); + sprintf(buf, "Driver Fatal Error= %d\n", errEvent.errorVal); + wrqu.data.length= strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + + /* + * This sends an AR600 specific event to the atheros debug app + */ + ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID, + (A_UINT8 *)&errEvent, + sizeof(WMI_TARGET_ERROR_REPORT_EVENT)); + } + } +} + +static A_STATUS +ar6000_unavail_ev(void *context, void *hif_handle) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)context; + /* NULL out it's entry in the global list */ + ar6000_devices[ar->arDeviceIndex] = NULL; + ar6000_destroy(ar->arNetDev, 1); + + return A_OK; +} + +/* + * We need to differentiate between the surprise and planned removal of the + * device because of the following consideration: + * - In case of surprise removal, the hcd already frees up the pending + * for the device and hence there is no need to unregister the function + * driver inorder to get these requests. For planned removal, the function + * driver has to explictly unregister itself to have the hcd return all the + * pending requests before the data structures for the devices are freed up. + * Note that as per the current implementation, the function driver will + * end up releasing all the devices since there is no API to selectively + * release a particular device. + * - Certain commands issued to the target can be skipped for surprise + * removal since they will anyway not go through. + */ +static void +ar6000_destroy(struct net_device *dev, unsigned int unregister) +{ + AR_SOFTC_T *ar; + + AR_DEBUG_PRINTF("+ar6000_destroy \n"); + + if((dev == NULL) || ((ar = netdev_priv(dev)) == NULL)) + { + AR_DEBUG_PRINTF("%s(): Failed to get device structure.\n", __func__); + return; + } + + ar->bIsDestroyProgress = TRUE; + + if (down_interruptible(&ar->arSem)) { + AR_DEBUG_PRINTF("%s(): down_interruptible failed \n", __func__); + return; + } + + /* Stop the transmit queues */ + netif_stop_queue(dev); + + /* Disable the target and the interrupts associated with it */ + if (ar->arWmiReady == TRUE) + { + if (!bypasswmi) + { + if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) + { + AR_DEBUG_PRINTF("%s(): Disconnect\n", __func__); + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar6000_init_profile_info(ar); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + wmi_disconnect_cmd(ar->arWmi); + } + + ar6000_dbglog_get_debug_logs(ar); + ar->arWmiReady = FALSE; + ar->arConnected = FALSE; + ar->arConnectPending = FALSE; + wmi_shutdown(ar->arWmi); + ar->arWmiEnabled = FALSE; + ar->arWmi = NULL; + ar->arWlanState = WLAN_ENABLED; +#ifdef USER_KEYS + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT; + ar->user_key_ctrl = 0; +#endif + } + + AR_DEBUG_PRINTF("%s(): WMI stopped\n", __func__); + } + else + { + AR_DEBUG_PRINTF("%s(): WMI not ready 0x%08x 0x%08x\n", + __func__, (unsigned int) ar, (unsigned int) ar->arWmi); + + /* Shut down WMI if we have started it */ + if(ar->arWmiEnabled == TRUE) + { + AR_DEBUG_PRINTF("%s(): Shut down WMI\n", __func__); + wmi_shutdown(ar->arWmi); + ar->arWmiEnabled = FALSE; + ar->arWmi = NULL; + } + } + + if (ar->arHtcTarget != NULL) { + AR_DEBUG_PRINTF(" Shuting down HTC .... \n"); + /* stop HTC */ + HTCStop(ar->arHtcTarget); + /* destroy HTC */ + HTCDestroy(ar->arHtcTarget); + } + + if (resetok) { + /* try to reset the device if we can + * The driver may have been configure NOT to reset the target during + * a debug session */ + AR_DEBUG_PRINTF(" Attempting to reset target on instance destroy.... \n"); + if (ar->arHifDevice != NULL) { + ar6000_reset_device(ar->arHifDevice, ar->arTargetType, TRUE); + } + } else { + AR_DEBUG_PRINTF(" Host does not want target reset. \n"); + } + + if (ar->arHifDevice != NULL) { + /*release the device so we do not get called back on remove incase we + * we're explicity destroyed by module unload */ + HIFReleaseDevice(ar->arHifDevice); + HIFShutDownDevice(ar->arHifDevice); + } + + /* Done with cookies */ + ar6000_cookie_cleanup(ar); + + /* Cleanup BMI */ + BMIInit(); + + /* Clear the tx counters */ + memset(tx_attempt, 0, sizeof(tx_attempt)); + memset(tx_post, 0, sizeof(tx_post)); + memset(tx_complete, 0, sizeof(tx_complete)); + + + /* Free up the device data structure */ + if( unregister ) + unregister_netdev(dev); +#ifndef free_netdev + kfree(dev); +#else + free_netdev(dev); +#endif + + AR_DEBUG_PRINTF("-ar6000_destroy \n"); +} + +static void disconnect_timer_handler(unsigned long ptr) +{ + struct net_device *dev = (struct net_device *)ptr; + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + A_UNTIMEOUT(&ar->disconnect_timer); + + ar6000_init_profile_info(ar); + wmi_disconnect_cmd(ar->arWmi); +} + +static void ar6000_detect_error(unsigned long ptr) +{ + struct net_device *dev = (struct net_device *)ptr; + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_TARGET_ERROR_REPORT_EVENT errEvent; + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + if (ar->arHBChallengeResp.outstanding) { + ar->arHBChallengeResp.missCnt++; + } else { + ar->arHBChallengeResp.missCnt = 0; + } + + if (ar->arHBChallengeResp.missCnt > ar->arHBChallengeResp.missThres) { + /* Send Error Detect event to the application layer and do not reschedule the error detection module timer */ + ar->arHBChallengeResp.missCnt = 0; + ar->arHBChallengeResp.seqNum = 0; + errEvent.errorVal = WMI_TARGET_COM_ERR | WMI_TARGET_FATAL_ERR; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID, + (A_UINT8 *)&errEvent, + sizeof(WMI_TARGET_ERROR_REPORT_EVENT)); + return; + } + + /* Generate the sequence number for the next challenge */ + ar->arHBChallengeResp.seqNum++; + ar->arHBChallengeResp.outstanding = TRUE; + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + /* Send the challenge on the control channel */ + if (wmi_get_challenge_resp_cmd(ar->arWmi, ar->arHBChallengeResp.seqNum, DRV_HB_CHALLENGE) != A_OK) { + AR_DEBUG_PRINTF("Unable to send heart beat challenge\n"); + } + + + /* Reschedule the timer for the next challenge */ + A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0); +} + +void ar6000_init_profile_info(AR_SOFTC_T *ar) +{ + ar->arSsidLen = 0; + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + + switch(fwmode) { + case HI_OPTION_FW_MODE_IBSS: + ar->arNetworkType = ar->arNextMode = ADHOC_NETWORK; + break; + case HI_OPTION_FW_MODE_BSS_STA: + ar->arNetworkType = ar->arNextMode = INFRA_NETWORK; + break; + case HI_OPTION_FW_MODE_AP: + ar->arNetworkType = ar->arNextMode = AP_NETWORK; + break; + } + + ar->arDot11AuthMode = OPEN_AUTH; + ar->arAuthMode = NONE_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arPairwiseCryptoLen = 0; + ar->arGroupCrypto = NONE_CRYPT; + ar->arGroupCryptoLen = 0; + A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList)); + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + A_MEMZERO(ar->arBssid, sizeof(ar->arBssid)); + ar->arBssChannel = 0; +} + +static void +ar6000_init_control_info(AR_SOFTC_T *ar) +{ + ar->arWmiEnabled = FALSE; + ar6000_init_profile_info(ar); + ar->arDefTxKeyIndex = 0; + A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList)); + ar->arChannelHint = 0; + ar->arListenInterval = MAX_LISTEN_INTERVAL; + ar->arVersion.host_ver = AR6K_SW_VERSION; + ar->arRssi = 0; + ar->arTxPwr = 0; + ar->arTxPwrSet = FALSE; + ar->arSkipScan = 0; + ar->arBeaconInterval = 0; + ar->arBitRate = 0; + ar->arMaxRetries = 0; + ar->arWmmEnabled = TRUE; + ar->intra_bss = 1; + + /* Initialize the AP mode state info */ + { + A_UINT8 ctr; + A_MEMZERO((A_UINT8 *)ar->sta_list, AP_MAX_NUM_STA * sizeof(sta_t)); + + /* init the Mutexes */ + A_MUTEX_INIT(&ar->mcastpsqLock); + + /* Init the PS queues */ + for (ctr=0; ctr < AP_MAX_NUM_STA ; ctr++) { + A_MUTEX_INIT(&ar->sta_list[ctr].psqLock); + A_NETBUF_QUEUE_INIT(&ar->sta_list[ctr].psq); + } + + ar->ap_profile_flag = 0; + A_NETBUF_QUEUE_INIT(&ar->mcastpsq); + } +} + +static int +ar6000_open(struct net_device *dev) +{ + unsigned long flags; + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + spin_lock_irqsave(&ar->arLock, flags); + if( ar->arConnected || bypasswmi) { + netif_carrier_on(dev); + /* Wake up the queues */ + netif_wake_queue(dev); + } + else + netif_carrier_off(dev); + + spin_unlock_irqrestore(&ar->arLock, flags); + return 0; +} + +static int +ar6000_close(struct net_device *dev) +{ + netif_stop_queue(dev); + + return 0; +} + +/* connect to a service */ +static A_STATUS ar6000_connectservice(AR_SOFTC_T *ar, + HTC_SERVICE_CONNECT_REQ *pConnect, + char *pDesc) +{ + A_STATUS status; + HTC_SERVICE_CONNECT_RESP response; + + do { + + A_MEMZERO(&response,sizeof(response)); + + status = HTCConnectService(ar->arHtcTarget, + pConnect, + &response); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(" Failed to connect to %s service status:%d \n", + pDesc, status); + break; + } + switch (pConnect->ServiceID) { + case WMI_CONTROL_SVC : + if (ar->arWmiEnabled) { + /* set control endpoint for WMI use */ + wmi_set_control_ep(ar->arWmi, response.Endpoint); + } + /* save EP for fast lookup */ + ar->arControlEp = response.Endpoint; + break; + case WMI_DATA_BE_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_BE, response.Endpoint); + break; + case WMI_DATA_BK_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_BK, response.Endpoint); + break; + case WMI_DATA_VI_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_VI, response.Endpoint); + break; + case WMI_DATA_VO_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_VO, response.Endpoint); + break; + default: + AR_DEBUG_PRINTF("ServiceID not mapped %d\n", pConnect->ServiceID); + status = A_EINVAL; + break; + } + + } while (FALSE); + + return status; +} + +void ar6000_TxDataCleanup(AR_SOFTC_T *ar) +{ + /* flush all the data (non-control) streams + * we only flush packets that are tagged as data, we leave any control packets that + * were in the TX queues alone */ + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_BE), + AR6K_DATA_PKT_TAG); + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_BK), + AR6K_DATA_PKT_TAG); + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_VI), + AR6K_DATA_PKT_TAG); + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_VO), + AR6K_DATA_PKT_TAG); +} + +HTC_ENDPOINT_ID +ar6000_ac2_endpoint_id ( void * devt, A_UINT8 ac) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *) devt; + return(arAc2EndpointID(ar, ac)); +} + +A_UINT8 +ar6000_endpoint_id2_ac(void * devt, HTC_ENDPOINT_ID ep ) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *) devt; + return(arEndpoint2Ac(ar, ep )); +} + +/* This function does one time initialization for the lifetime of the device */ +int ar6000_init(struct net_device *dev) +{ + AR_SOFTC_T *ar; + A_STATUS status; + A_INT32 timeleft; + + if((ar = netdev_priv(dev)) == NULL) + { + return(-EIO); + } + + /* Do we need to finish the BMI phase */ + if(BMIDone(ar->arHifDevice) != A_OK) + { + return -EIO; + } + + if (!bypasswmi) + { +#if 0 /* TBDXXX */ + if (ar->arVersion.host_ver != ar->arVersion.target_ver) { + A_PRINTF("WARNING: Host version 0x%x does not match Target " + " version 0x%x!\n", + ar->arVersion.host_ver, ar->arVersion.target_ver); + } +#endif + + /* Indicate that WMI is enabled (although not ready yet) */ + ar->arWmiEnabled = TRUE; + if ((ar->arWmi = wmi_init((void *) ar)) == NULL) + { + AR_DEBUG_PRINTF("%s() Failed to initialize WMI.\n", __func__); + return(-EIO); + } + + AR_DEBUG_PRINTF("%s() Got WMI @ 0x%08x.\n", __func__, + (unsigned int) ar->arWmi); + } + + do { + HTC_SERVICE_CONNECT_REQ connect; + + /* the reason we have to wait for the target here is that the driver layer + * has to init BMI in order to set the host block size, + */ + status = HTCWaitTarget(ar->arHtcTarget); + + if (A_FAILED(status)) { + break; + } + + A_MEMZERO(&connect,sizeof(connect)); + /* meta data is unused for now */ + connect.pMetaData = NULL; + connect.MetaDataLength = 0; + /* these fields are the same for all service endpoints */ + connect.EpCallbacks.pContext = ar; + connect.EpCallbacks.EpTxComplete = ar6000_tx_complete; + connect.EpCallbacks.EpRecv = ar6000_rx; + connect.EpCallbacks.EpRecvRefill = ar6000_rx_refill; + connect.EpCallbacks.EpSendFull = ar6000_tx_queue_full; + /* set the max queue depth so that our ar6000_tx_queue_full handler gets called. + * Linux has the peculiarity of not providing flow control between the + * NIC and the network stack. There is no API to indicate that a TX packet + * was sent which could provide some back pressure to the network stack. + * Under linux you would have to wait till the network stack consumed all sk_buffs + * before any back-flow kicked in. Which isn't very friendly. + * So we have to manage this ourselves */ + connect.MaxSendQueueDepth = 32; + + /* connect to control service */ + connect.ServiceID = WMI_CONTROL_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI CONTROL"); + if (A_FAILED(status)) { + break; + } + + /* for the remaining data services set the connection flag to reduce dribbling, + * if configured to do so */ + if (reduce_credit_dribble) { + connect.ConnectionFlags |= HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE; + /* the credit dribble trigger threshold is (reduce_credit_dribble - 1) for a value + * of 0-3 */ + connect.ConnectionFlags &= ~HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK; + connect.ConnectionFlags |= + ((A_UINT16)reduce_credit_dribble - 1) & HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK; + } + /* connect to best-effort service */ + connect.ServiceID = WMI_DATA_BE_SVC; + + status = ar6000_connectservice(ar, + &connect, + "WMI DATA BE"); + if (A_FAILED(status)) { + break; + } + + /* connect to back-ground + * map this to WMI LOW_PRI */ + connect.ServiceID = WMI_DATA_BK_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI DATA BK"); + if (A_FAILED(status)) { + break; + } + + /* connect to Video service, map this to + * to HI PRI */ + connect.ServiceID = WMI_DATA_VI_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI DATA VI"); + if (A_FAILED(status)) { + break; + } + + /* connect to VO service, this is currently not + * mapped to a WMI priority stream due to historical reasons. + * WMI originally defined 3 priorities over 3 mailboxes + * We can change this when WMI is reworked so that priorities are not + * dependent on mailboxes */ + connect.ServiceID = WMI_DATA_VO_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI DATA VO"); + if (A_FAILED(status)) { + break; + } + + A_ASSERT(arAc2EndpointID(ar,WMM_AC_BE) != 0); + A_ASSERT(arAc2EndpointID(ar,WMM_AC_BK) != 0); + A_ASSERT(arAc2EndpointID(ar,WMM_AC_VI) != 0); + A_ASSERT(arAc2EndpointID(ar,WMM_AC_VO) != 0); + + /* setup access class priority mappings */ + ar->arAcStreamPriMap[WMM_AC_BK] = 0; /* lowest */ + ar->arAcStreamPriMap[WMM_AC_BE] = 1; /* */ + ar->arAcStreamPriMap[WMM_AC_VI] = 2; /* */ + ar->arAcStreamPriMap[WMM_AC_VO] = 3; /* highest */ + + } while (FALSE); + + if (A_FAILED(status)) { + return (-EIO); + } + + /* + * give our connected endpoints some buffers + */ + + ar6000_rx_refill(ar, ar->arControlEp); + ar6000_rx_refill(ar, arAc2EndpointID(ar,WMM_AC_BE)); + + /* + * We will post the receive buffers only for SPE or endpoint ping testing so we are + * making it conditional on the 'bypasswmi' flag. + */ + if (bypasswmi) { + ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_BK)); + ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_VI)); + ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_VO)); + } + + /* setup credit distribution */ + ar6000_setup_credit_dist(ar->arHtcTarget, &ar->arCreditStateInfo); + + /* Since cookies are used for HTC transports, they should be */ + /* initialized prior to enabling HTC. */ + ar6000_cookie_init(ar); + + /* start HTC */ + status = HTCStart(ar->arHtcTarget); + + if (status != A_OK) { + if (ar->arWmiEnabled == TRUE) { + wmi_shutdown(ar->arWmi); + ar->arWmiEnabled = FALSE; + ar->arWmi = NULL; + } + ar6000_cookie_cleanup(ar); + return -EIO; + } + + if (!bypasswmi) { + /* Wait for Wmi event to be ready */ + timeleft = wait_event_interruptible_timeout(arEvent, + (ar->arWmiReady == TRUE), wmitimeout * HZ); + + if(!timeleft || signal_pending(current)) + { + AR_DEBUG_PRINTF("WMI is not ready or wait was interrupted\n"); + return -EIO; + } + + AR_DEBUG_PRINTF("%s() WMI is ready\n", __func__); + + /* Communicate the wmi protocol verision to the target */ + if ((ar6000_set_host_app_area(ar)) != A_OK) { + AR_DEBUG_PRINTF("Unable to set the host app area\n"); + } + } + + ar->arNumDataEndPts = 1; + + if (bypasswmi) { + /* for tests like endpoint ping, the MAC address needs to be non-zero otherwise + * the data path through a raw socket is disabled */ + dev->dev_addr[0] = 0x00; + dev->dev_addr[1] = 0x01; + dev->dev_addr[2] = 0x02; + dev->dev_addr[3] = 0xAA; + dev->dev_addr[4] = 0xBB; + dev->dev_addr[5] = 0xCC; + } + + return(0); +} + + +void +ar6000_bitrate_rx(void *devt, A_INT32 rateKbps) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arBitRate = rateKbps; + wake_up(&arEvent); +} + +void +ar6000_ratemask_rx(void *devt, A_UINT16 ratemask) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arRateMask = ratemask; + wake_up(&arEvent); +} + +void +ar6000_txPwr_rx(void *devt, A_UINT8 txPwr) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arTxPwr = txPwr; + wake_up(&arEvent); +} + + +void +ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + A_MEMCPY(ar->arChannelList, chanList, numChan * sizeof (A_UINT16)); + ar->arNumChannels = numChan; + + wake_up(&arEvent); +} + +A_UINT8 +ar6000_ibss_map_epid(struct sk_buff *skb, struct net_device *dev, A_UINT32 * mapNo) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_UINT8 *datap; + ATH_MAC_HDR *macHdr; + A_UINT32 i, eptMap; + + (*mapNo) = 0; + datap = A_NETBUF_DATA(skb); + macHdr = (ATH_MAC_HDR *)(datap + sizeof(WMI_DATA_HDR)); + if (IEEE80211_IS_MULTICAST(macHdr->dstMac)) { + return ENDPOINT_2; + } + + eptMap = -1; + for (i = 0; i < ar->arNodeNum; i ++) { + if (IEEE80211_ADDR_EQ(macHdr->dstMac, ar->arNodeMap[i].macAddress)) { + (*mapNo) = i + 1; + ar->arNodeMap[i].txPending ++; + return ar->arNodeMap[i].epId; + } + + if ((eptMap == -1) && !ar->arNodeMap[i].txPending) { + eptMap = i; + } + } + + if (eptMap == -1) { + eptMap = ar->arNodeNum; + ar->arNodeNum ++; + A_ASSERT(ar->arNodeNum <= MAX_NODE_NUM); + } + + A_MEMCPY(ar->arNodeMap[eptMap].macAddress, macHdr->dstMac, IEEE80211_ADDR_LEN); + + for (i = ENDPOINT_2; i <= ENDPOINT_5; i ++) { + if (!ar->arTxPending[i]) { + ar->arNodeMap[eptMap].epId = i; + break; + } + // No free endpoint is available, start redistribution on the inuse endpoints. + if (i == ENDPOINT_5) { + ar->arNodeMap[eptMap].epId = ar->arNexEpId; + ar->arNexEpId ++; + if (ar->arNexEpId > ENDPOINT_5) { + ar->arNexEpId = ENDPOINT_2; + } + } + } + + (*mapNo) = eptMap + 1; + ar->arNodeMap[eptMap].txPending ++; + + return ar->arNodeMap[eptMap].epId; +} + +#ifdef DEBUG +static void ar6000_dump_skb(struct sk_buff *skb) +{ + u_char *ch; + for (ch = A_NETBUF_DATA(skb); + (A_UINT32)ch < ((A_UINT32)A_NETBUF_DATA(skb) + + A_NETBUF_LEN(skb)); ch++) + { + AR_DEBUG_PRINTF("%2.2x ", *ch); + } + AR_DEBUG_PRINTF("\n"); +} +#endif + +static int +ar6000_data_tx(struct sk_buff *skb, struct net_device *dev) +{ +#define AC_NOT_MAPPED 99 + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_UINT8 ac = AC_NOT_MAPPED; + HTC_ENDPOINT_ID eid = ENDPOINT_UNUSED; + A_UINT32 mapNo = 0; + int len; + struct ar_cookie *cookie; + A_BOOL checkAdHocPsMapping = FALSE,bMoreData = FALSE; + +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,13) + skb->list = NULL; +#endif + + AR_DEBUG2_PRINTF("ar6000_data_tx start - skb=0x%x, data=0x%x, len=0x%x\n", + (A_UINT32)skb, (A_UINT32)A_NETBUF_DATA(skb), + A_NETBUF_LEN(skb)); + + /* If target is not associated */ + if( (!ar->arConnected && !bypasswmi) +#ifdef CONFIG_HOST_TCMD_SUPPORT + /* TCMD doesnt support any data, free the buf and return */ + || (ar->arTargetMode == AR6000_TCMD_MODE) +#endif + ) { + A_NETBUF_FREE(skb); + return 0; + } + + do { + + if (ar->arWmiReady == FALSE && bypasswmi == 0) { + break; + } + +#ifdef BLOCK_TX_PATH_FLAG + if (blocktx) { + break; + } +#endif /* BLOCK_TX_PATH_FLAG */ + + /* AP mode Power save processing */ + /* If the dst STA is in sleep state, queue the pkt in its PS queue */ + + if (ar->arNetworkType == AP_NETWORK) { + ATH_MAC_HDR *datap = (ATH_MAC_HDR *)A_NETBUF_DATA(skb); + sta_t *conn = NULL; + + /* If the dstMac is a Multicast address & atleast one of the + * associated STA is in PS mode, then queue the pkt to the + * mcastq + */ + if (IEEE80211_IS_MULTICAST(datap->dstMac)) { + A_UINT8 ctr=0; + A_BOOL qMcast=FALSE; + + for (ctr=0; ctrsta_list[ctr]))) { + qMcast = TRUE; + } + } + if(qMcast) { + /* If this transmit is not because of a Dtim Expiry q it */ + if (ar->DTIMExpired == FALSE) { + A_BOOL isMcastqEmpty = FALSE; + + A_MUTEX_LOCK(&ar->mcastpsqLock); + isMcastqEmpty = A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq); + A_NETBUF_ENQUEUE(&ar->mcastpsq, skb); + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + + /* If this is the first Mcast pkt getting queued + * indicate to the target to set the BitmapControl LSB + * of the TIM IE. + */ + if (isMcastqEmpty) { + wmi_set_pvb_cmd(ar->arWmi, MCAST_AID, 1); + } + return 0; + } else { + /* This transmit is because of Dtim expiry. Determine if + * MoreData bit has to be set. + */ + A_MUTEX_LOCK(&ar->mcastpsqLock); + if(!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) { + bMoreData = TRUE; + } + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + } + } + } else { + conn = ieee80211_find_conn(ar, datap->dstMac); + if (conn) { + if (STA_IS_PWR_SLEEP(conn)) { + /* If this transmit is not because of a PsPoll q it*/ + if (!STA_IS_PS_POLLED(conn)) { + A_BOOL isPsqEmpty = FALSE; + /* Queue the frames if the STA is sleeping */ + A_MUTEX_LOCK(&conn->psqLock); + isPsqEmpty = A_NETBUF_QUEUE_EMPTY(&conn->psq); + A_NETBUF_ENQUEUE(&conn->psq, skb); + A_MUTEX_UNLOCK(&conn->psqLock); + + /* If this is the first pkt getting queued + * for this STA, update the PVB for this STA + */ + if (isPsqEmpty) { + wmi_set_pvb_cmd(ar->arWmi, conn->aid, 1); + } + + return 0; + } else { + /* This tx is because of a PsPoll. Determine if + * MoreData bit has to be set + */ + A_MUTEX_LOCK(&conn->psqLock); + if (!A_NETBUF_QUEUE_EMPTY(&conn->psq)) { + bMoreData = TRUE; + } + A_MUTEX_UNLOCK(&conn->psqLock); + } + } + } else { + + /* non existent STA. drop the frame */ + A_NETBUF_FREE(skb); + return 0; + } + } + } + + if (ar->arWmiEnabled) { + if (A_NETBUF_HEADROOM(skb) < dev->hard_header_len) { + struct sk_buff *newbuf; + + /* + * We really should have gotten enough headroom but sometimes + * we still get packets with not enough headroom. Copy the packet. + */ + len = A_NETBUF_LEN(skb); + newbuf = A_NETBUF_ALLOC(len); + if (newbuf == NULL) { + break; + } + A_NETBUF_PUT(newbuf, len); + A_MEMCPY(A_NETBUF_DATA(newbuf), A_NETBUF_DATA(skb), len); + A_NETBUF_FREE(skb); + skb = newbuf; + /* fall through and assemble header */ + } + + if (processDot11Hdr) { + if (wmi_dot11_hdr_add(ar->arWmi,skb,ar->arNetworkType) != A_OK) { + AR_DEBUG_PRINTF("ar6000_data_tx-wmi_dot11_hdr_add failed\n"); + break; + } + } else { + if (wmi_dix_2_dot3(ar->arWmi, skb) != A_OK) { + AR_DEBUG_PRINTF("ar6000_data_tx - wmi_dix_2_dot3 failed\n"); + break; + } + } + + if (wmi_data_hdr_add(ar->arWmi, skb, DATA_MSGTYPE, bMoreData) != A_OK) { + AR_DEBUG_PRINTF("ar6000_data_tx - wmi_data_hdr_add failed\n"); + break; + } + + if ((ar->arNetworkType == ADHOC_NETWORK) && + ar->arIbssPsEnable && ar->arConnected) { + /* flag to check adhoc mapping once we take the lock below: */ + checkAdHocPsMapping = TRUE; + + } else { + /* get the stream mapping */ + ac = wmi_implicit_create_pstream(ar->arWmi, skb, 0, ar->arWmmEnabled); + } + + } else { + struct iphdr *ipHdr; + /* + * the endpoint is directly based on the TOS field in the IP + * header **** only for testing ****** + */ + ipHdr = A_NETBUF_DATA(skb) + sizeof(ATH_MAC_HDR); + /* here we map the TOS field to an access class, this is for + * the endpointping test application. The application uses 0,1,2,3 + * for the TOS field to emulate writing to mailboxes. The number is + * used to map directly to an access class */ + ac = (ipHdr->tos >> 1) & 0x3; + } + + } while (FALSE); + + /* did we succeed ? */ + if ((ac == AC_NOT_MAPPED) && !checkAdHocPsMapping) { + /* cleanup and exit */ + A_NETBUF_FREE(skb); + AR6000_STAT_INC(ar, tx_dropped); + AR6000_STAT_INC(ar, tx_aborted_errors); + return 0; + } + + cookie = NULL; + + /* take the lock to protect driver data */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + do { + + if (checkAdHocPsMapping) { + eid = ar6000_ibss_map_epid(skb, dev, &mapNo); + }else { + eid = arAc2EndpointID (ar, ac); + } + /* validate that the endpoint is connected */ + if (eid == 0 || eid == ENDPOINT_UNUSED ) { + AR_DEBUG_PRINTF(" eid %d is NOT mapped!\n", eid); + break; + } + /* allocate resource for this packet */ + cookie = ar6000_alloc_cookie(ar); + + if (cookie != NULL) { + /* update counts while the lock is held */ + ar->arTxPending[eid]++; + ar->arTotalTxDataPending++; + } + + } while (FALSE); + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + if (cookie != NULL) { + cookie->arc_bp[0] = (A_UINT32)skb; + cookie->arc_bp[1] = mapNo; + SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt, + cookie, + A_NETBUF_DATA(skb), + A_NETBUF_LEN(skb), + eid, + AR6K_DATA_PKT_TAG); + +#ifdef DEBUG + if (debugdriver >= 3) { + ar6000_dump_skb(skb); + } +#endif + /* HTC interface is asynchronous, if this fails, cleanup will happen in + * the ar6000_tx_complete callback */ + HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt); + } else { + /* no packet to send, cleanup */ + A_NETBUF_FREE(skb); + AR6000_STAT_INC(ar, tx_dropped); + AR6000_STAT_INC(ar, tx_aborted_errors); + } + + return 0; +} + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +static void +tvsub(register struct timeval *out, register struct timeval *in) +{ + if((out->tv_usec -= in->tv_usec) < 0) { + out->tv_sec--; + out->tv_usec += 1000000; + } + out->tv_sec -= in->tv_sec; +} + +void +applyAPTCHeuristics(AR_SOFTC_T *ar) +{ + A_UINT32 duration; + A_UINT32 numbytes; + A_UINT32 throughput; + struct timeval ts; + A_STATUS status; + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + if ((enableAPTCHeuristics) && (!aptcTR.timerScheduled)) { + do_gettimeofday(&ts); + tvsub(&ts, &aptcTR.samplingTS); + duration = ts.tv_sec * 1000 + ts.tv_usec / 1000; /* ms */ + numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived; + + if (duration > APTC_TRAFFIC_SAMPLING_INTERVAL) { + /* Initialize the time stamp and byte count */ + aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0; + do_gettimeofday(&aptcTR.samplingTS); + + /* Calculate and decide based on throughput thresholds */ + throughput = ((numbytes * 8) / duration); + if (throughput > APTC_UPPER_THROUGHPUT_THRESHOLD) { + /* Disable Sleep and schedule a timer */ + A_ASSERT(ar->arWmiReady == TRUE); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + status = wmi_powermode_cmd(ar->arWmi, MAX_PERF_POWER); + AR6000_SPIN_LOCK(&ar->arLock, 0); + A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0); + aptcTR.timerScheduled = TRUE; + } + } + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); +} +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +static HTC_SEND_FULL_ACTION ar6000_tx_queue_full(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + HTC_SEND_FULL_ACTION action = HTC_SEND_FULL_KEEP; + A_BOOL stopNet = FALSE; + HTC_ENDPOINT_ID Endpoint = HTC_GET_ENDPOINT_FROM_PKT(pPacket); + + do { + + if (bypasswmi) { + /* for endpointping testing no other checks need to be made + * we can however still allow the network to stop */ + stopNet = TRUE; + break; + } + + if (Endpoint == ar->arControlEp) { + /* under normal WMI if this is getting full, then something is running rampant + * the host should not be exhausting the WMI queue with too many commands + * the only exception to this is during testing using endpointping */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + /* set flag to handle subsequent messages */ + ar->arWMIControlEpFull = TRUE; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + AR_DEBUG_PRINTF("WMI Control Endpoint is FULL!!! \n"); + /* no need to stop the network */ + stopNet = FALSE; + /* + * target is stuck - treat it as a target assert + */ + ar6000_target_failure(ar, A_ERROR); + + break; + } + + /* if we get here, we are dealing with data endpoints getting full */ + + if (HTC_GET_TAG_FROM_PKT(pPacket) == AR6K_CONTROL_PKT_TAG) { + /* don't drop control packets issued on ANY data endpoint */ + break; + } + + if (ar->arNetworkType == ADHOC_NETWORK) { + /* in adhoc mode, we cannot differentiate traffic priorities so there is no need to + * continue, however we should stop the network */ + stopNet = TRUE; + break; + } + + if (ar->arAcStreamPriMap[arEndpoint2Ac(ar,Endpoint)] < ar->arHiAcStreamActivePri) { + /* this stream's priority is less than the highest active priority, we + * give preference to the highest priority stream by directing + * HTC to drop the packet that overflowed */ + action = HTC_SEND_FULL_DROP; + /* since we are dropping packets, no need to stop the network */ + stopNet = FALSE; + break; + } + + } while (FALSE); + + if (stopNet) { + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arNetQueueStopped = TRUE; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + /* one of the data endpoints queues is getting full..need to stop network stack + * the queue will resume in ar6000_tx_complete() */ + netif_stop_queue(ar->arNetDev); + } + + return action; +} + + +static void +ar6000_tx_complete(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + void *cookie = (void *)pPacket->pPktContext; + struct sk_buff *skb = NULL; + A_UINT32 mapNo = 0; + A_STATUS status; + struct ar_cookie * ar_cookie; + HTC_ENDPOINT_ID eid; + A_BOOL wakeEvent = FALSE; + + status = pPacket->Status; + ar_cookie = (struct ar_cookie *)cookie; + skb = (struct sk_buff *)ar_cookie->arc_bp[0]; + eid = pPacket->Endpoint ; + mapNo = ar_cookie->arc_bp[1]; + + A_ASSERT(skb); + A_ASSERT(pPacket->pBuffer == A_NETBUF_DATA(skb)); + + if (A_SUCCESS(status)) { + A_ASSERT(pPacket->ActualLength == A_NETBUF_LEN(skb)); + } + + AR_DEBUG2_PRINTF("ar6000_tx_complete skb=0x%x data=0x%x len=0x%x eid=%d ", + (A_UINT32)skb, (A_UINT32)pPacket->pBuffer, + pPacket->ActualLength, + eid); + + /* lock the driver as we update internal state */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + ar->arTxPending[eid]--; + + if ((eid != ar->arControlEp) || bypasswmi) { + ar->arTotalTxDataPending--; + } + + if (eid == ar->arControlEp) + { + if (ar->arWMIControlEpFull) { + /* since this packet completed, the WMI EP is no longer full */ + ar->arWMIControlEpFull = FALSE; + } + + if (ar->arTxPending[eid] == 0) { + wakeEvent = TRUE; + } + } + + if (A_FAILED(status)) { + AR6000_STAT_INC(ar, tx_errors); + if (status != A_NO_RESOURCE) { + AR_DEBUG_PRINTF("%s() -TX ERROR, status: 0x%x\n", __func__, + status); + } + } else { + AR_DEBUG2_PRINTF("OK\n"); + AR6000_STAT_INC(ar, tx_packets); + ar->arNetStats.tx_bytes += A_NETBUF_LEN(skb); +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + aptcTR.bytesTransmitted += a_netbuf_to_len(skb); + applyAPTCHeuristics(ar); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + } + + // TODO this needs to be looked at + if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable + && (eid != ar->arControlEp) && mapNo) + { + mapNo --; + ar->arNodeMap[mapNo].txPending --; + + if (!ar->arNodeMap[mapNo].txPending && (mapNo == (ar->arNodeNum - 1))) { + A_UINT32 i; + for (i = ar->arNodeNum; i > 0; i --) { + if (!ar->arNodeMap[i - 1].txPending) { + A_MEMZERO(&ar->arNodeMap[i - 1], sizeof(struct ar_node_mapping)); + ar->arNodeNum --; + } else { + break; + } + } + } + } + + /* Freeing a cookie should not be contingent on either of */ + /* these flags, just if we have a cookie or not. */ + /* Can we even get here without a cookie? Fix later. */ + if (ar->arWmiReady == TRUE || (bypasswmi)) + { + ar6000_free_cookie(ar, cookie); + } + + if (ar->arNetQueueStopped) { + ar->arNetQueueStopped = FALSE; + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + /* lock is released, we can freely call other kernel APIs */ + + A_NETBUF_FREE(skb); + + if ((ar->arConnected == TRUE) || (bypasswmi)) { + if (status != A_ECANCELED) { + /* don't wake the queue if we are flushing, other wise it will just + * keep queueing packets, which will keep failing */ + netif_wake_queue(ar->arNetDev); + } + } + + if (wakeEvent) { + wake_up(&arEvent); + } + +} + +sta_t * +ieee80211_find_conn(AR_SOFTC_T *ar, A_UINT8 *node_addr) +{ + sta_t *conn = NULL; + A_UINT8 i, max_conn; + + switch(ar->arNetworkType) { + case AP_NETWORK: + max_conn = AP_MAX_NUM_STA; + break; + default: + max_conn=0; + break; + } + + for (i = 0; i < max_conn; i++) { + if (IEEE80211_ADDR_EQ(node_addr, ar->sta_list[i].mac)) { + conn = &ar->sta_list[i]; + break; + } + } + + return conn; +} + +sta_t *ieee80211_find_conn_for_aid(AR_SOFTC_T *ar, A_UINT8 aid) +{ + sta_t *conn = NULL; + A_UINT8 ctr; + + for (ctr = 0; ctr < AP_MAX_NUM_STA; ctr++) { + if (ar->sta_list[ctr].aid == aid) { + conn = &ar->sta_list[ctr]; + break; + } + } + return conn; +} + +/* + * Receive event handler. This is called by HTC when a packet is received + */ +int pktcount; +static void +ar6000_rx(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + struct sk_buff *skb = (struct sk_buff *)pPacket->pPktContext; + int minHdrLen; + A_STATUS status = pPacket->Status; + HTC_ENDPOINT_ID ept = pPacket->Endpoint; + + A_ASSERT((status != A_OK) || + (pPacket->pBuffer == (A_NETBUF_DATA(skb) + HTC_HEADER_LEN))); + + AR_DEBUG2_PRINTF("ar6000_rx ar=0x%x eid=%d, skb=0x%x, data=0x%x, len=0x%x ", + (A_UINT32)ar, ept, (A_UINT32)skb, (A_UINT32)pPacket->pBuffer, + pPacket->ActualLength); + if (status != A_OK) { + AR_DEBUG2_PRINTF("ERR\n"); + } else { + AR_DEBUG2_PRINTF("OK\n"); + } + + /* take lock to protect buffer counts + * and adaptive power throughput state */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + ar->arRxBuffers[ept]--; + + if (A_SUCCESS(status)) { + AR6000_STAT_INC(ar, rx_packets); + ar->arNetStats.rx_bytes += pPacket->ActualLength; +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + aptcTR.bytesReceived += a_netbuf_to_len(skb); + applyAPTCHeuristics(ar); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + + A_NETBUF_PUT(skb, pPacket->ActualLength + HTC_HEADER_LEN); + A_NETBUF_PULL(skb, HTC_HEADER_LEN); + +#ifdef DEBUG + if (debugdriver >= 2) { + ar6000_dump_skb(skb); + } +#endif /* DEBUG */ + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + skb->dev = ar->arNetDev; + if (status != A_OK) { + AR6000_STAT_INC(ar, rx_errors); + A_NETBUF_FREE(skb); + } else if (ar->arWmiEnabled == TRUE) { + if (ept == ar->arControlEp) { + /* + * this is a wmi control msg + */ + wmi_control_rx(ar->arWmi, skb); + } else { + /* + * this is a wmi data packet + */ + // NWF + + if (processDot11Hdr) { + minHdrLen = sizeof(WMI_DATA_HDR) + sizeof(struct ieee80211_frame) + sizeof(ATH_LLC_SNAP_HDR); + } else { + minHdrLen = sizeof (WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + + sizeof(ATH_LLC_SNAP_HDR); + } + + /* In the case of AP mode we may receive NULL data frames + * that do not have LLC hdr. They are 16 bytes in size. + * Allow these frames in the AP mode. + */ + if (ar->arNetworkType != AP_NETWORK && ((pPacket->ActualLength < minHdrLen) || + (pPacket->ActualLength > AR6000_BUFFER_SIZE))) + { + /* + * packet is too short or too long + */ + AR_DEBUG_PRINTF("TOO SHORT or TOO LONG\n"); + AR6000_STAT_INC(ar, rx_errors); + AR6000_STAT_INC(ar, rx_length_errors); + A_NETBUF_FREE(skb); + } else { +#if 0 + /* Access RSSI values here */ + AR_DEBUG_PRINTF("RSSI %d\n", + ((WMI_DATA_HDR *) A_NETBUF_DATA(skb))->rssi); +#endif + /* Get the Power save state of the STA */ + if (ar->arNetworkType == AP_NETWORK) { + sta_t *conn = NULL; + A_UINT8 psState=0,prevPsState; + ATH_MAC_HDR *datap=NULL; + + psState = (((WMI_DATA_HDR *)A_NETBUF_DATA(skb))->info + >> WMI_DATA_HDR_PS_SHIFT) & WMI_DATA_HDR_PS_MASK; + datap = (ATH_MAC_HDR *)(A_NETBUF_DATA(skb)+sizeof(WMI_DATA_HDR)); + conn = ieee80211_find_conn(ar, datap->srcMac); + + + if (conn) { + /* if there is a change in PS state of the STA, + * take appropriate steps. + * 1. If Sleep-->Awake, flush the psq for the STA + * Clear the PVB for the STA. + * 2. If Awake-->Sleep, Starting queueing frames + * the STA. + */ + prevPsState = STA_IS_PWR_SLEEP(conn); + if (psState) { + STA_SET_PWR_SLEEP(conn); + } else { + STA_CLR_PWR_SLEEP(conn); + } + + if (prevPsState ^ STA_IS_PWR_SLEEP(conn)) { + + if (!STA_IS_PWR_SLEEP(conn)) { + + A_MUTEX_LOCK(&conn->psqLock); + while (!A_NETBUF_QUEUE_EMPTY(&conn->psq)) { + struct sk_buff *skb=NULL; + + skb = A_NETBUF_DEQUEUE(&conn->psq); + A_MUTEX_UNLOCK(&conn->psqLock); + ar6000_data_tx(skb,ar->arNetDev); + A_MUTEX_LOCK(&conn->psqLock); + } + A_MUTEX_UNLOCK(&conn->psqLock); + /* Clear the PVB for this STA */ + wmi_set_pvb_cmd(ar->arWmi, conn->aid, 0); + } + } + } else { + /* This frame is from a STA that is not associated*/ + A_ASSERT(FALSE); + } + + /* Drop NULL data frames here */ + if((pPacket->ActualLength < minHdrLen) || + (pPacket->ActualLength > AR6000_BUFFER_SIZE)) { + A_NETBUF_FREE(skb); + goto refill; + } + } + + wmi_data_hdr_remove(ar->arWmi, skb); + /* NWF: print the 802.11 hdr bytes */ + if(processDot11Hdr) { + wmi_dot11_hdr_remove(ar->arWmi,skb); + } else { + wmi_dot3_2_dix(ar->arWmi, skb); + } + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + /* + * extra push and memcpy, for eth_type_trans() of 2.4 kernel + * will pull out hard_header_len bytes of the skb. + */ + A_NETBUF_PUSH(skb, sizeof(WMI_DATA_HDR) + sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN); + A_MEMCPY(A_NETBUF_DATA(skb), A_NETBUF_DATA(skb) + sizeof(WMI_DATA_HDR) + + sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN, sizeof(ATH_MAC_HDR)); +#endif + if ((ar->arNetDev->flags & IFF_UP) == IFF_UP) { + if (ar->arNetworkType == AP_NETWORK) { + struct sk_buff *skb1 = NULL; + ATH_MAC_HDR *datap; + + datap = (ATH_MAC_HDR *)A_NETBUF_DATA(skb); + if (IEEE80211_IS_MULTICAST(datap->dstMac)) { + /* Bcast/Mcast frames should be sent to the OS + * stack as well as on the air. + */ + skb1 = skb_copy(skb,GFP_ATOMIC); + } else { + /* Search for a connected STA with dstMac as + * the Mac address. If found send the frame to + * it on the air else send the frame up the + * stack + */ + sta_t *conn = NULL; + conn = ieee80211_find_conn(ar, datap->dstMac); + + if (conn && ar->intra_bss) { + skb1 = skb; + skb = NULL; + } else if(conn && !ar->intra_bss) { + A_NETBUF_FREE(skb); + skb = NULL; + } + } + if (skb1) { + ar6000_data_tx(skb1, ar->arNetDev); + } + } + } + deliver_frames_to_nw_stack(skb); + } + } + } else { + deliver_frames_to_nw_stack(skb); + } +refill: + if (status != A_ECANCELED) { + /* + * HTC provides A_ECANCELED status when it doesn't want to be refilled + * (probably due to a shutdown) + */ + ar6000_rx_refill(Context, ept); + } + + +} + +static void +deliver_frames_to_nw_stack(struct sk_buff *skb) +{ + if(skb) { + if ((skb->dev->flags & IFF_UP) == IFF_UP) { + skb->protocol = eth_type_trans(skb, skb->dev); + netif_rx(skb); + } else { + A_NETBUF_FREE(skb); + } + } +} + + +static void +ar6000_rx_refill(void *Context, HTC_ENDPOINT_ID Endpoint) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + void *osBuf; + int RxBuffers; + int buffersToRefill; + HTC_PACKET *pPacket; + + buffersToRefill = (int)AR6000_MAX_RX_BUFFERS - + (int)ar->arRxBuffers[Endpoint]; + + if (buffersToRefill <= 0) { + /* fast return, nothing to fill */ + return; + } + + AR_DEBUG2_PRINTF("ar6000_rx_refill: providing htc with %d buffers at eid=%d\n", + buffersToRefill, Endpoint); + + for (RxBuffers = 0; RxBuffers < buffersToRefill; RxBuffers++) { + osBuf = A_NETBUF_ALLOC(AR6000_BUFFER_SIZE); + if (NULL == osBuf) { + break; + } + /* the HTC packet wrapper is at the head of the reserved area + * in the skb */ + pPacket = (HTC_PACKET *)(A_NETBUF_HEAD(osBuf)); + /* set re-fill info */ + SET_HTC_PACKET_INFO_RX_REFILL(pPacket,osBuf,A_NETBUF_DATA(osBuf),AR6000_BUFFER_SIZE,Endpoint); + /* add this packet */ + HTCAddReceivePkt(ar->arHtcTarget, pPacket); + } + + /* update count */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arRxBuffers[Endpoint] += RxBuffers; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); +} + +static struct net_device_stats * +ar6000_get_stats(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + return &ar->arNetStats; +} + +static struct iw_statistics * +ar6000_get_iwstats(struct net_device * dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + TARGET_STATS *pStats = &ar->arTargetStats; + struct iw_statistics * pIwStats = &ar->arIwStats; + + if (ar->bIsDestroyProgress || ar->arWmiReady == FALSE) + { + pIwStats->status = 0; + pIwStats->qual.qual = 0; + pIwStats->qual.level =0; + pIwStats->qual.noise = 0; + pIwStats->discard.code =0; + pIwStats->discard.retries=0; + pIwStats->miss.beacon =0; + return pIwStats; + } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + /* + * The in_atomic function is used to determine if the scheduling is + * allowed in the current context or not. This was introduced in 2.6 + * From what I have read on the differences between 2.4 and 2.6, the + * 2.4 kernel did not support preemption and so this check might not + * be required for 2.4 kernels. + */ + if (in_atomic()) + { + wmi_get_stats_cmd(ar->arWmi); + + pIwStats->status = 1 ; + pIwStats->qual.qual = pStats->cs_aveBeacon_rssi - 161; + pIwStats->qual.level =pStats->cs_aveBeacon_rssi; /* noise is -95 dBm */ + pIwStats->qual.noise = pStats->noise_floor_calibation; + pIwStats->discard.code = pStats->rx_decrypt_err; + pIwStats->discard.retries = pStats->tx_retry_cnt; + pIwStats->miss.beacon = pStats->cs_bmiss_cnt; + return pIwStats; + } +#endif /* LINUX_VERSION_CODE */ + + if (down_interruptible(&ar->arSem)) { + pIwStats->status = 0; + return pIwStats; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + pIwStats->status = 0; + return pIwStats; + } + + ar->statsUpdatePending = TRUE; + + if(wmi_get_stats_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + pIwStats->status = 0; + return pIwStats; + } + + wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ); + + if (signal_pending(current)) { + AR_DEBUG_PRINTF("ar6000 : WMI get stats timeout \n"); + up(&ar->arSem); + pIwStats->status = 0; + return pIwStats; + } + pIwStats->status = 1 ; + pIwStats->qual.qual = pStats->cs_aveBeacon_rssi - 161; + pIwStats->qual.level =pStats->cs_aveBeacon_rssi; /* noise is -95 dBm */ + pIwStats->qual.noise = pStats->noise_floor_calibation; + pIwStats->discard.code = pStats->rx_decrypt_err; + pIwStats->discard.retries = pStats->tx_retry_cnt; + pIwStats->miss.beacon = pStats->cs_bmiss_cnt; + up(&ar->arSem); + return pIwStats; +} + +void +ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap, A_UINT32 vers) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + struct net_device *dev = ar->arNetDev; + + ar->arWmiReady = TRUE; + wake_up(&arEvent); + A_MEMCPY(dev->dev_addr, datap, AR6000_ETH_ADDR_LEN); + AR_DEBUG_PRINTF("mac address = %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", + dev->dev_addr[0], dev->dev_addr[1], + dev->dev_addr[2], dev->dev_addr[3], + dev->dev_addr[4], dev->dev_addr[5]); + + ar->arPhyCapability = phyCap; + ar->arVersion.wlan_ver = vers; +} + +A_UINT8 +add_new_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 aid, A_UINT8 *wpaie, A_UINT8 ielen) +{ + A_INT8 free_slot=-1, i; + + for(i=0; i < AP_MAX_NUM_STA; i++) { + if(A_MEMCMP(ar->sta_list[i].mac, mac, ATH_MAC_LEN)==0) { + /* it is already available */ + return 0; + } + + if(!((1 << i) & ar->sta_list_index)) { + free_slot = i; + break; + } + } + + if(free_slot >= 0) { + A_MEMCPY(ar->sta_list[free_slot].mac, mac, ATH_MAC_LEN); + A_MEMCPY(ar->sta_list[free_slot].wpa_ie, wpaie, ielen); + ar->sta_list[free_slot].aid = aid; + ar->sta_list_index = ar->sta_list_index | (1 << free_slot); + return 1; + } + return 0; /* not added */ +} + +void +ar6000_connect_event(AR_SOFTC_T *ar, A_UINT16 channel, A_UINT8 *bssid, + A_UINT16 listenInterval, A_UINT16 beaconInterval, + NETWORK_TYPE networkType, A_UINT8 beaconIeLen, + A_UINT8 assocReqLen, A_UINT8 assocRespLen, + A_UINT8 *assocInfo) +{ + union iwreq_data wrqu; + int i, beacon_ie_pos, assoc_resp_ie_pos, assoc_req_ie_pos; + static const char *tag1 = "ASSOCINFO(ReqIEs="; + static const char *tag2 = "ASSOCRESPIE="; + static const char *beaconIetag = "BEACONIE="; + char buf[WMI_CONTROL_MSG_MAX_LEN * 2 + strlen(tag1) + 1]; + char *pos; + unsigned long flags; + + if(ar->arNetworkType & AP_NETWORK) { + A_PRINTF("NEW STA %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x " + " aid=%d WPAIE=%d\n", bssid[0], bssid[1], bssid[2], + bssid[3], bssid[4], bssid[5], channel, assocRespLen); + add_new_sta(ar, bssid, channel /*aid*/, + assocInfo /* WPA IE */, assocRespLen /* IE len */); + + /* Send event to application */ + A_MEMZERO(&wrqu, sizeof(wrqu)); + A_MEMCPY(wrqu.addr.sa_data, bssid, ATH_MAC_LEN); + wireless_send_event(ar->arNetDev, IWEVREGISTERED, &wrqu, NULL); + /* In case the queue is stopped when we switch modes, this will + * wake it up + */ + netif_wake_queue(ar->arNetDev); + return; + } + + if (FALSE == ar->arConnected && + ((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode))) + { + A_TIMEOUT_MS(&ar->disconnect_timer, A_DISCONNECT_TIMER_INTERVAL, 0); + } + + A_MEMCPY(ar->arBssid, bssid, sizeof(ar->arBssid)); + ar->arBssChannel = channel; + + A_PRINTF("AR6000 connected event on freq %d ", channel); + A_PRINTF("with bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x " + " listenInterval=%d, beaconInterval = %d, beaconIeLen = %d assocReqLen=%d" + " assocRespLen =%d\n", + bssid[0], bssid[1], bssid[2], + bssid[3], bssid[4], bssid[5], + listenInterval, beaconInterval, + beaconIeLen, assocReqLen, assocRespLen); + if (networkType & ADHOC_NETWORK) { + if (networkType & ADHOC_CREATOR) { + A_PRINTF("Network: Adhoc (Creator)\n"); + } else { + A_PRINTF("Network: Adhoc (Joiner)\n"); + } + } + + if (beaconIeLen && (sizeof(buf) > (9 + beaconIeLen * 2))) { + AR_DEBUG_PRINTF("\nBeaconIEs= "); + + beacon_ie_pos = 0; + A_MEMZERO(buf, sizeof(buf)); + sprintf(buf, "%s", beaconIetag); + pos = buf + 9; + for (i = beacon_ie_pos; i < beacon_ie_pos + beaconIeLen; i++) { + AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]); + sprintf(pos, "%2.2x", assocInfo[i]); + pos += 2; + } + AR_DEBUG_PRINTF("\n"); + + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + } + + if (assocRespLen && (sizeof(buf) > (12 + (assocRespLen * 2)))) + { + assoc_resp_ie_pos = beaconIeLen + assocReqLen + + sizeof(A_UINT16) + /* capinfo*/ + sizeof(A_UINT16) + /* status Code */ + sizeof(A_UINT16) ; /* associd */ + A_MEMZERO(buf, sizeof(buf)); + sprintf(buf, "%s", tag2); + pos = buf + 12; + AR_DEBUG_PRINTF("\nAssocRespIEs= "); + /* + * The Association Response Frame w.o. the WLAN header is delivered to + * the host, so skip over to the IEs + */ + for (i = assoc_resp_ie_pos; i < assoc_resp_ie_pos + assocRespLen - 6; i++) + { + AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]); + sprintf(pos, "%2.2x", assocInfo[i]); + pos += 2; + } + AR_DEBUG_PRINTF("\n"); + + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + } + + if (assocReqLen && (sizeof(buf) > (17 + (assocReqLen * 2)))) { + /* + * assoc Request includes capability and listen interval. Skip these. + */ + assoc_req_ie_pos = beaconIeLen + + sizeof(A_UINT16) + /* capinfo*/ + sizeof(A_UINT16); /* listen interval */ + + A_MEMZERO(buf, sizeof(buf)); + sprintf(buf, "%s", tag1); + pos = buf + 17; + AR_DEBUG_PRINTF("AssocReqIEs= "); + for (i = assoc_req_ie_pos; i < assoc_req_ie_pos + assocReqLen - 4; i++) { + AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]); + sprintf(pos, "%2.2x", assocInfo[i]); + pos += 2;; + } + AR_DEBUG_PRINTF("\n"); + + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + } + +#ifdef USER_KEYS + if (ar->user_savedkeys_stat == USER_SAVEDKEYS_STAT_RUN && + ar->user_saved_keys.keyOk == TRUE) + { + key_op_ctrl = KEY_OP_VALID_MASK & ~KEY_OP_INIT_TSC; + + if (ar->user_key_ctrl & AR6000_USER_SETKEYS_RSC_UNCHANGED) { + key_op_ctrl &= ~KEY_OP_INIT_RSC; + } else { + key_op_ctrl |= KEY_OP_INIT_RSC; + } + ar6000_reinstall_keys(ar, key_op_ctrl); + } +#endif /* USER_KEYS */ + + netif_wake_queue(ar->arNetDev); + + if ((networkType & ADHOC_NETWORK) && + (OPEN_AUTH == ar->arDot11AuthMode) && + (NONE_AUTH == ar->arAuthMode) && + (WEP_CRYPT == ar->arPairwiseCrypto)) + { + if (!ar->arConnected) { + wmi_addKey_cmd(ar->arWmi, + ar->arDefTxKeyIndex, + WEP_CRYPT, + GROUP_USAGE | TX_USAGE, + ar->arWepKeyList[ar->arDefTxKeyIndex].arKeyLen, + NULL, + ar->arWepKeyList[ar->arDefTxKeyIndex].arKey, KEY_OP_INIT_VAL, NULL, + NO_SYNC_WMIFLAG); + } + } + + /* Update connect & link status atomically */ + spin_lock_irqsave(&ar->arLock, flags); + ar->arConnected = TRUE; + ar->arConnectPending = FALSE; + netif_carrier_on(ar->arNetDev); + spin_unlock_irqrestore(&ar->arLock, flags); + + reconnect_flag = 0; + + A_MEMZERO(&wrqu, sizeof(wrqu)); + A_MEMCPY(wrqu.addr.sa_data, bssid, IEEE80211_ADDR_LEN); + wrqu.addr.sa_family = ARPHRD_ETHER; + wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL); + if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable) { + A_MEMZERO(ar->arNodeMap, sizeof(ar->arNodeMap)); + ar->arNodeNum = 0; + ar->arNexEpId = ENDPOINT_2; + } +} + +void ar6000_set_numdataendpts(AR_SOFTC_T *ar, A_UINT32 num) +{ + A_ASSERT(num <= (HTC_MAILBOX_NUM_MAX - 1)); + ar->arNumDataEndPts = num; +} + +A_UINT8 +remove_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 reason) +{ + A_INT8 i; + struct sk_buff *skb; + + if(IS_MAC_NULL(mac)) { + return 0; + } + + for(i=0; i < AP_MAX_NUM_STA; i++) { + if(A_MEMCMP(ar->sta_list[i].mac, mac, ATH_MAC_LEN)==0) { + + /* empty the queued pkts in the PS queue if any */ + A_MUTEX_LOCK(&ar->sta_list[i].psqLock); + while (!A_NETBUF_QUEUE_EMPTY(&ar->sta_list[i].psq)) { + skb = A_NETBUF_DEQUEUE(&ar->sta_list[i].psq); + A_NETBUF_FREE(skb); + } + A_MUTEX_UNLOCK(&ar->sta_list[i].psqLock); + + A_PRINTF("DEL STA %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x " + " aid=%d REASON=%d\n", mac[0], mac[1], mac[2], + mac[3], mac[4], mac[5], ar->sta_list[i].aid, reason); + + /* Zero out the state fields */ + A_MEMZERO(&ar->sta_list[i].mac, ATH_MAC_LEN); + A_MEMZERO(&ar->sta_list[i].wpa_ie, IEEE80211_MAX_IE); + ar->sta_list[i].aid = 0; + ar->sta_list[i].flags = 0; + + ar->sta_list_index = ar->sta_list_index & ~(1 << i); + return 1; + } + } + + return 0; /* not removed */ +} + +void +ar6000_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason, A_UINT8 *bssid, + A_UINT8 assocRespLen, A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus) +{ + A_UINT8 i; + unsigned long flags; + union iwreq_data wrqu; + + if(ar->arNetworkType & AP_NETWORK) { + struct sk_buff *skb; + + if(!remove_sta(ar, bssid, protocolReasonStatus)) { + return; + } + + /* If there are no more associated STAs, empty the mcast PS q */ + if (ar->sta_list_index == 0) { + A_MUTEX_LOCK(&ar->mcastpsqLock); + while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) { + skb = A_NETBUF_DEQUEUE(&ar->mcastpsq); + A_NETBUF_FREE(skb); + } + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + } + + /* Send event to application */ + A_MEMZERO(&wrqu, sizeof(wrqu)); + A_MEMCPY(wrqu.addr.sa_data, bssid, ATH_MAC_LEN); + wireless_send_event(ar->arNetDev, IWEVEXPIRED, &wrqu, NULL); + return; + } + + /* Always send a DEL_LINK event */ + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.addr.sa_family = ARPHRD_ETHER; + + /* Send disconnect event to supplicant */ + wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL); + + A_UNTIMEOUT(&ar->disconnect_timer); + + A_PRINTF("AR6000 disconnected. Reason is %d\n", reason); + if (bssid[0] || bssid[1] || bssid[2] || bssid[3] || bssid[4] || bssid[5]) { + A_PRINTF(" from %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", + bssid[0], bssid[1], bssid[2], bssid[3], bssid[4], bssid[5]); + } + + AR_DEBUG_PRINTF("\nDisconnect Reason is %d", reason); + AR_DEBUG_PRINTF("\nProtocol Reason/Status Code is %d", protocolReasonStatus); + AR_DEBUG_PRINTF("\nAssocResp Frame = %s", + assocRespLen ? " " : "NULL"); + for (i = 0; i < assocRespLen; i++) { + if (!(i % 0x10)) { + AR_DEBUG_PRINTF("\n"); + } + AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]); + } + AR_DEBUG_PRINTF("\n"); + /* + * If the event is due to disconnect cmd from the host, only they the target + * would stop trying to connect. Under any other condition, target would + * keep trying to connect. + * + */ + if( reason == DISCONNECT_CMD) + { + ar->arConnectPending = FALSE; + } else { + ar->arConnectPending = TRUE; + if (((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x11)) || + ((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x0) && (reconnect_flag == 1))) { + ar->arConnected = TRUE; + return; + } + } + + if (reason == NO_NETWORK_AVAIL) + { + bss_t *pWmiSsidnode = NULL; + + /* remove the current associated bssid node */ + wmi_free_node (ar->arWmi, bssid); + + /* + * In case any other same SSID nodes are present + * remove it, since those nodes also not available now + */ + do + { + /* + * Find the nodes based on SSID and remove it + * NOTE :: This case will not work out for Hidden-SSID + */ + pWmiSsidnode = wmi_find_Ssidnode (ar->arWmi, ar->arSsid, ar->arSsidLen, FALSE, TRUE); + + if (pWmiSsidnode) + { + wmi_free_node (ar->arWmi, pWmiSsidnode->ni_macaddr); + } + + }while (pWmiSsidnode); + + ar6000_init_profile_info(ar); + wmi_disconnect_cmd(ar->arWmi); + } + + /* Update connect & link status atomically */ + spin_lock_irqsave(&ar->arLock, flags); + ar->arConnected = FALSE; + netif_carrier_off(ar->arNetDev); + spin_unlock_irqrestore(&ar->arLock, flags); + + if( (reason != CSERV_DISCONNECT) || (reconnect_flag != 1) ) { + reconnect_flag = 0; + } + +#ifdef USER_KEYS + if (reason != CSERV_DISCONNECT) + { + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT; + ar->user_key_ctrl = 0; + } +#endif /* USER_KEYS */ + + netif_stop_queue(ar->arNetDev); + A_MEMZERO(ar->arBssid, sizeof(ar->arBssid)); + ar->arBssChannel = 0; + ar->arBeaconInterval = 0; + + ar6000_TxDataCleanup(ar); +} + +void +ar6000_regDomain_event(AR_SOFTC_T *ar, A_UINT32 regCode) +{ + A_PRINTF("AR6000 Reg Code = 0x%x\n", regCode); + ar->arRegCode = regCode; +} + +void +ar6000_neighborReport_event(AR_SOFTC_T *ar, int numAps, WMI_NEIGHBOR_INFO *info) +{ + static const char *tag = "PRE-AUTH"; + char buf[128]; + union iwreq_data wrqu; + int i; + + AR_DEBUG_PRINTF("AR6000 Neighbor Report Event\n"); + for (i=0; i < numAps; info++, i++) { + AR_DEBUG_PRINTF("bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", + info->bssid[0], info->bssid[1], info->bssid[2], + info->bssid[3], info->bssid[4], info->bssid[5]); + if (info->bssFlags & WMI_PREAUTH_CAPABLE_BSS) { + AR_DEBUG_PRINTF("preauth-cap"); + } + if (info->bssFlags & WMI_PMKID_VALID_BSS) { + AR_DEBUG_PRINTF(" pmkid-valid\n"); + continue; /* we skip bss if the pmkid is already valid */ + } + AR_DEBUG_PRINTF("\n"); + snprintf(buf, sizeof(buf), "%s%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x", + tag, + info->bssid[0], info->bssid[1], info->bssid[2], + info->bssid[3], info->bssid[4], info->bssid[5], + i, info->bssFlags); + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + } +} + +void +ar6000_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast) +{ + static const char *tag = "MLME-MICHAELMICFAILURE.indication"; + char buf[128]; + union iwreq_data wrqu; + + /* + * For AP case, keyid will have aid of STA which sent pkt with + * MIC error. Use this aid to get MAC & send it to hostapd. + */ + if (ar->arNetworkType == AP_NETWORK) { + sta_t *s = ieee80211_find_conn_for_aid(ar, keyid); + A_PRINTF("AP TKIP MIC error received from aid=%d\n", keyid); + snprintf(buf,sizeof(buf), "%s addr=%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x", + tag, s->mac[0],s->mac[1],s->mac[2],s->mac[3],s->mac[4],s->mac[5]); + } else { + A_PRINTF("AR6000 TKIP MIC error received for keyid %d %scast\n", + keyid, ismcast ? "multi": "uni"); + snprintf(buf, sizeof(buf), "%s(keyid=%d %sicast)", tag, keyid, + ismcast ? "mult" : "un"); + } + + memset(&wrqu, 0, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); +} + +void +ar6000_scanComplete_event(AR_SOFTC_T *ar, A_STATUS status) +{ + AR_DEBUG_PRINTF("AR6000 scan complete: %d\n", status); + ar->scan_complete = 1; + wake_up_interruptible(&ar6000_scan_queue); +} + +void +ar6000_targetStats_event(AR_SOFTC_T *ar, WMI_TARGET_STATS *pTarget) +{ + TARGET_STATS *pStats = &ar->arTargetStats; + A_UINT8 ac; + + pStats->tx_packets += pTarget->txrxStats.tx_stats.tx_packets; + pStats->tx_bytes += pTarget->txrxStats.tx_stats.tx_bytes; + pStats->tx_unicast_pkts += pTarget->txrxStats.tx_stats.tx_unicast_pkts; + pStats->tx_unicast_bytes += pTarget->txrxStats.tx_stats.tx_unicast_bytes; + pStats->tx_multicast_pkts += pTarget->txrxStats.tx_stats.tx_multicast_pkts; + pStats->tx_multicast_bytes += pTarget->txrxStats.tx_stats.tx_multicast_bytes; + pStats->tx_broadcast_pkts += pTarget->txrxStats.tx_stats.tx_broadcast_pkts; + pStats->tx_broadcast_bytes += pTarget->txrxStats.tx_stats.tx_broadcast_bytes; + pStats->tx_rts_success_cnt += pTarget->txrxStats.tx_stats.tx_rts_success_cnt; + for(ac = 0; ac < WMM_NUM_AC; ac++) + pStats->tx_packet_per_ac[ac] += pTarget->txrxStats.tx_stats.tx_packet_per_ac[ac]; + pStats->tx_errors += pTarget->txrxStats.tx_stats.tx_errors; + pStats->tx_failed_cnt += pTarget->txrxStats.tx_stats.tx_failed_cnt; + pStats->tx_retry_cnt += pTarget->txrxStats.tx_stats.tx_retry_cnt; + pStats->tx_mult_retry_cnt += pTarget->txrxStats.tx_stats.tx_mult_retry_cnt; + pStats->tx_rts_fail_cnt += pTarget->txrxStats.tx_stats.tx_rts_fail_cnt; + pStats->tx_unicast_rate = wmi_get_rate(pTarget->txrxStats.tx_stats.tx_unicast_rate); + + pStats->rx_packets += pTarget->txrxStats.rx_stats.rx_packets; + pStats->rx_bytes += pTarget->txrxStats.rx_stats.rx_bytes; + pStats->rx_unicast_pkts += pTarget->txrxStats.rx_stats.rx_unicast_pkts; + pStats->rx_unicast_bytes += pTarget->txrxStats.rx_stats.rx_unicast_bytes; + pStats->rx_multicast_pkts += pTarget->txrxStats.rx_stats.rx_multicast_pkts; + pStats->rx_multicast_bytes += pTarget->txrxStats.rx_stats.rx_multicast_bytes; + pStats->rx_broadcast_pkts += pTarget->txrxStats.rx_stats.rx_broadcast_pkts; + pStats->rx_broadcast_bytes += pTarget->txrxStats.rx_stats.rx_broadcast_bytes; + pStats->rx_fragment_pkt += pTarget->txrxStats.rx_stats.rx_fragment_pkt; + pStats->rx_errors += pTarget->txrxStats.rx_stats.rx_errors; + pStats->rx_crcerr += pTarget->txrxStats.rx_stats.rx_crcerr; + pStats->rx_key_cache_miss += pTarget->txrxStats.rx_stats.rx_key_cache_miss; + pStats->rx_decrypt_err += pTarget->txrxStats.rx_stats.rx_decrypt_err; + pStats->rx_duplicate_frames += pTarget->txrxStats.rx_stats.rx_duplicate_frames; + pStats->rx_unicast_rate = wmi_get_rate(pTarget->txrxStats.rx_stats.rx_unicast_rate); + + + pStats->tkip_local_mic_failure + += pTarget->txrxStats.tkipCcmpStats.tkip_local_mic_failure; + pStats->tkip_counter_measures_invoked + += pTarget->txrxStats.tkipCcmpStats.tkip_counter_measures_invoked; + pStats->tkip_replays += pTarget->txrxStats.tkipCcmpStats.tkip_replays; + pStats->tkip_format_errors += pTarget->txrxStats.tkipCcmpStats.tkip_format_errors; + pStats->ccmp_format_errors += pTarget->txrxStats.tkipCcmpStats.ccmp_format_errors; + pStats->ccmp_replays += pTarget->txrxStats.tkipCcmpStats.ccmp_replays; + + + pStats->power_save_failure_cnt += pTarget->pmStats.power_save_failure_cnt; + pStats->noise_floor_calibation = pTarget->noise_floor_calibation; + + pStats->cs_bmiss_cnt += pTarget->cservStats.cs_bmiss_cnt; + pStats->cs_lowRssi_cnt += pTarget->cservStats.cs_lowRssi_cnt; + pStats->cs_connect_cnt += pTarget->cservStats.cs_connect_cnt; + pStats->cs_disconnect_cnt += pTarget->cservStats.cs_disconnect_cnt; + pStats->cs_aveBeacon_snr = pTarget->cservStats.cs_aveBeacon_snr; + pStats->cs_aveBeacon_rssi = pTarget->cservStats.cs_aveBeacon_rssi; + pStats->cs_lastRoam_msec = pTarget->cservStats.cs_lastRoam_msec; + pStats->cs_snr = pTarget->cservStats.cs_snr; + pStats->cs_rssi = pTarget->cservStats.cs_rssi; + + pStats->lq_val = pTarget->lqVal; + + pStats->wow_num_pkts_dropped += pTarget->wowStats.wow_num_pkts_dropped; + pStats->wow_num_host_pkt_wakeups += pTarget->wowStats.wow_num_host_pkt_wakeups; + pStats->wow_num_host_event_wakeups += pTarget->wowStats.wow_num_host_event_wakeups; + pStats->wow_num_events_discarded += pTarget->wowStats.wow_num_events_discarded; + + pStats->arp_received += pTarget->arpStats.arp_received; + pStats->arp_matched += pTarget->arpStats.arp_matched; + pStats->arp_replied += pTarget->arpStats.arp_replied; + + ar->statsUpdatePending = FALSE; + wake_up(&arEvent); +} + +void +ar6000_rssiThreshold_event(AR_SOFTC_T *ar, WMI_RSSI_THRESHOLD_VAL newThreshold, A_INT16 rssi) +{ + USER_RSSI_THOLD userRssiThold; + + /* Send an event to the app */ + userRssiThold.tag = ar->rssi_map[newThreshold].tag; + userRssiThold.rssi = rssi + SIGNAL_QUALITY_NOISE_FLOOR; + A_PRINTF("rssi Threshold range = %d tag = %d rssi = %d\n", newThreshold, + userRssiThold.tag, userRssiThold.rssi); + + ar6000_send_event_to_app(ar, WMI_RSSI_THRESHOLD_EVENTID,(A_UINT8 *)&userRssiThold, sizeof(USER_RSSI_THOLD)); +} + + +void +ar6000_hbChallengeResp_event(AR_SOFTC_T *ar, A_UINT32 cookie, A_UINT32 source) +{ + if (source == APP_HB_CHALLENGE) { + /* Report it to the app in case it wants a positive acknowledgement */ + ar6000_send_event_to_app(ar, WMIX_HB_CHALLENGE_RESP_EVENTID, + (A_UINT8 *)&cookie, sizeof(cookie)); + } else { + /* This would ignore the replys that come in after their due time */ + if (cookie == ar->arHBChallengeResp.seqNum) { + ar->arHBChallengeResp.outstanding = FALSE; + } + } +} + + +void +ar6000_reportError_event(AR_SOFTC_T *ar, WMI_TARGET_ERROR_VAL errorVal) +{ + char *errString[] = { + [WMI_TARGET_PM_ERR_FAIL] "WMI_TARGET_PM_ERR_FAIL", + [WMI_TARGET_KEY_NOT_FOUND] "WMI_TARGET_KEY_NOT_FOUND", + [WMI_TARGET_DECRYPTION_ERR] "WMI_TARGET_DECRYPTION_ERR", + [WMI_TARGET_BMISS] "WMI_TARGET_BMISS", + [WMI_PSDISABLE_NODE_JOIN] "WMI_PSDISABLE_NODE_JOIN" + }; + + A_PRINTF("AR6000 Error on Target. Error = 0x%x\n", errorVal); + + /* One error is reported at a time, and errorval is a bitmask */ + if(errorVal & (errorVal - 1)) + return; + + A_PRINTF("AR6000 Error type = "); + switch(errorVal) + { + case WMI_TARGET_PM_ERR_FAIL: + case WMI_TARGET_KEY_NOT_FOUND: + case WMI_TARGET_DECRYPTION_ERR: + case WMI_TARGET_BMISS: + case WMI_PSDISABLE_NODE_JOIN: + A_PRINTF("%s\n", errString[errorVal]); + break; + default: + A_PRINTF("INVALID\n"); + break; + } + +} + + +void +ar6000_cac_event(AR_SOFTC_T *ar, A_UINT8 ac, A_UINT8 cacIndication, + A_UINT8 statusCode, A_UINT8 *tspecSuggestion) +{ + WMM_TSPEC_IE *tspecIe; + + /* + * This is the TSPEC IE suggestion from AP. + * Suggestion provided by AP under some error + * cases, could be helpful for the host app. + * Check documentation. + */ + tspecIe = (WMM_TSPEC_IE *)tspecSuggestion; + + /* + * What do we do, if we get TSPEC rejection? One thought + * that comes to mind is implictly delete the pstream... + */ + A_PRINTF("AR6000 CAC notification. " + "AC = %d, cacIndication = 0x%x, statusCode = 0x%x\n", + ac, cacIndication, statusCode); +} + +void +ar6000_channel_change_event(AR_SOFTC_T *ar, A_UINT16 oldChannel, + A_UINT16 newChannel) +{ + A_PRINTF("Channel Change notification\nOld Channel: %d, New Channel: %d\n", + oldChannel, newChannel); +} + +#define AR6000_PRINT_BSSID(_pBss) do { \ + A_PRINTF("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",\ + (_pBss)[0],(_pBss)[1],(_pBss)[2],(_pBss)[3],\ + (_pBss)[4],(_pBss)[5]); \ +} while(0) + +void +ar6000_roam_tbl_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_TBL *pTbl) +{ + A_UINT8 i; + + A_PRINTF("ROAM TABLE NO OF ENTRIES is %d ROAM MODE is %d\n", + pTbl->numEntries, pTbl->roamMode); + for (i= 0; i < pTbl->numEntries; i++) { + A_PRINTF("[%d]bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", i, + pTbl->bssRoamInfo[i].bssid[0], pTbl->bssRoamInfo[i].bssid[1], + pTbl->bssRoamInfo[i].bssid[2], + pTbl->bssRoamInfo[i].bssid[3], + pTbl->bssRoamInfo[i].bssid[4], + pTbl->bssRoamInfo[i].bssid[5]); + A_PRINTF("RSSI %d RSSIDT %d LAST RSSI %d UTIL %d ROAM_UTIL %d" + " BIAS %d\n", + pTbl->bssRoamInfo[i].rssi, + pTbl->bssRoamInfo[i].rssidt, + pTbl->bssRoamInfo[i].last_rssi, + pTbl->bssRoamInfo[i].util, + pTbl->bssRoamInfo[i].roam_util, + pTbl->bssRoamInfo[i].bias); + } +} + +void +ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters, WMI_GET_WOW_LIST_REPLY *wow_reply) +{ + A_UINT8 i,j; + + /*Each event now contains exactly one filter, see bug 26613*/ + A_PRINTF("WOW pattern %d of %d patterns\n", wow_reply->this_filter_num, wow_reply->num_filters); + A_PRINTF("wow mode = %s host mode = %s\n", + (wow_reply->wow_mode == 0? "disabled":"enabled"), + (wow_reply->host_mode == 1 ? "awake":"asleep")); + + + /*If there are no patterns, the reply will only contain generic + WoW information. Pattern information will exist only if there are + patterns present. Bug 26716*/ + + /* If this event contains pattern information, display it*/ + if (wow_reply->this_filter_num) { + i=0; + A_PRINTF("id=%d size=%d offset=%d\n", + wow_reply->wow_filters[i].wow_filter_id, + wow_reply->wow_filters[i].wow_filter_size, + wow_reply->wow_filters[i].wow_filter_offset); + A_PRINTF("wow pattern = "); + for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) { + A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_pattern[j]); + } + + A_PRINTF("\nwow mask = "); + for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) { + A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_mask[j]); + } + A_PRINTF("\n"); + } +} + +/* + * Report the Roaming related data collected on the target + */ +void +ar6000_display_roam_time(WMI_TARGET_ROAM_TIME *p) +{ + A_PRINTF("Disconnect Data : BSSID: "); + AR6000_PRINT_BSSID(p->disassoc_bssid); + A_PRINTF(" RSSI %d DISASSOC Time %d NO_TXRX_TIME %d\n", + p->disassoc_bss_rssi,p->disassoc_time, + p->no_txrx_time); + A_PRINTF("Connect Data: BSSID: "); + AR6000_PRINT_BSSID(p->assoc_bssid); + A_PRINTF(" RSSI %d ASSOC Time %d TXRX_TIME %d\n", + p->assoc_bss_rssi,p->assoc_time, + p->allow_txrx_time); + A_PRINTF("Last Data Tx Time (b4 Disassoc) %d "\ + "First Data Tx Time (after Assoc) %d\n", + p->last_data_txrx_time, p->first_data_txrx_time); +} + +void +ar6000_roam_data_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_DATA *p) +{ + switch (p->roamDataType) { + case ROAM_DATA_TIME: + ar6000_display_roam_time(&p->u.roamTime); + break; + default: + break; + } +} + +void +ar6000_bssInfo_event_rx(AR_SOFTC_T *ar, A_UINT8 *datap, int len) +{ + struct sk_buff *skb; + WMI_BSS_INFO_HDR *bih = (WMI_BSS_INFO_HDR *)datap; + + + if (!ar->arMgmtFilter) { + return; + } + if (((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_BEACON) && + (bih->frameType != BEACON_FTYPE)) || + ((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_PROBE_RESP) && + (bih->frameType != PROBERESP_FTYPE))) + { + return; + } + + if ((skb = A_NETBUF_ALLOC_RAW(len)) != NULL) { + + A_NETBUF_PUT(skb, len); + A_MEMCPY(A_NETBUF_DATA(skb), datap, len); + skb->dev = ar->arNetDev; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) + A_MEMCPY(skb_mac_header(skb), A_NETBUF_DATA(skb), 6); +#else + skb->mac.raw = A_NETBUF_DATA(skb); +#endif + skb->ip_summed = CHECKSUM_NONE; + skb->pkt_type = PACKET_OTHERHOST; + skb->protocol = __constant_htons(0x0019); + netif_rx(skb); + } +} + +A_UINT32 wmiSendCmdNum; + +A_STATUS +ar6000_control_tx(void *devt, void *osbuf, HTC_ENDPOINT_ID eid) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + A_STATUS status = A_OK; + struct ar_cookie *cookie = NULL; + int i; + + /* take lock to protect ar6000_alloc_cookie() */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + do { + + AR_DEBUG2_PRINTF("ar_contrstatus = ol_tx: skb=0x%x, len=0x%x eid =%d\n", + (A_UINT32)osbuf, A_NETBUF_LEN(osbuf), eid); + + if (ar->arWMIControlEpFull && (eid == ar->arControlEp)) { + /* control endpoint is full, don't allocate resources, we + * are just going to drop this packet */ + cookie = NULL; + AR_DEBUG_PRINTF(" WMI Control EP full, dropping packet : 0x%X, len:%d \n", + (A_UINT32)osbuf, A_NETBUF_LEN(osbuf)); + } else { + cookie = ar6000_alloc_cookie(ar); + } + + if (cookie == NULL) { + status = A_NO_MEMORY; + break; + } + + if(logWmiRawMsgs) { + A_PRINTF("WMI cmd send, msgNo %d :", wmiSendCmdNum); + for(i = 0; i < a_netbuf_to_len(osbuf); i++) + A_PRINTF("%x ", ((A_UINT8 *)a_netbuf_to_data(osbuf))[i]); + A_PRINTF("\n"); + } + + wmiSendCmdNum++; + + } while (FALSE); + + if (cookie != NULL) { + /* got a structure to send it out on */ + ar->arTxPending[eid]++; + + if (eid != ar->arControlEp) { + ar->arTotalTxDataPending++; + } + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + if (cookie != NULL) { + cookie->arc_bp[0] = (A_UINT32)osbuf; + cookie->arc_bp[1] = 0; + SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt, + cookie, + A_NETBUF_DATA(osbuf), + A_NETBUF_LEN(osbuf), + eid, + AR6K_CONTROL_PKT_TAG); + /* this interface is asynchronous, if there is an error, cleanup will happen in the + * TX completion callback */ + HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt); + status = A_OK; + } + + return status; +} + +/* indicate tx activity or inactivity on a WMI stream */ +void ar6000_indicate_tx_activity(void *devt, A_UINT8 TrafficClass, A_BOOL Active) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + HTC_ENDPOINT_ID eid ; + int i; + + if (ar->arWmiEnabled) { + eid = arAc2EndpointID(ar, TrafficClass); + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + ar->arAcStreamActive[TrafficClass] = Active; + + if (Active) { + /* when a stream goes active, keep track of the active stream with the highest priority */ + + if (ar->arAcStreamPriMap[TrafficClass] > ar->arHiAcStreamActivePri) { + /* set the new highest active priority */ + ar->arHiAcStreamActivePri = ar->arAcStreamPriMap[TrafficClass]; + } + + } else { + /* when a stream goes inactive, we may have to search for the next active stream + * that is the highest priority */ + + if (ar->arHiAcStreamActivePri == ar->arAcStreamPriMap[TrafficClass]) { + + /* the highest priority stream just went inactive */ + + /* reset and search for the "next" highest "active" priority stream */ + ar->arHiAcStreamActivePri = 0; + for (i = 0; i < WMM_NUM_AC; i++) { + if (ar->arAcStreamActive[i]) { + if (ar->arAcStreamPriMap[i] > ar->arHiAcStreamActivePri) { + /* set the new highest active priority */ + ar->arHiAcStreamActivePri = ar->arAcStreamPriMap[i]; + } + } + } + } + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + } else { + /* for mbox ping testing, the traffic class is mapped directly as a stream ID, + * see handling of AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE in ioctl.c */ + eid = (HTC_ENDPOINT_ID)TrafficClass; + } + + /* notify HTC, this may cause credit distribution changes */ + + HTCIndicateActivityChange(ar->arHtcTarget, + eid, + Active); + +} + +module_init(ar6000_init_module); +module_exit(ar6000_cleanup_module); + +/* Init cookie queue */ +static void +ar6000_cookie_init(AR_SOFTC_T *ar) +{ + A_UINT32 i; + + ar->arCookieList = NULL; + A_MEMZERO(s_ar_cookie_mem, sizeof(s_ar_cookie_mem)); + + for (i = 0; i < MAX_COOKIE_NUM; i++) { + ar6000_free_cookie(ar, &s_ar_cookie_mem[i]); + } +} + +/* cleanup cookie queue */ +static void +ar6000_cookie_cleanup(AR_SOFTC_T *ar) +{ + /* It is gone .... */ + ar->arCookieList = NULL; +} + +/* Init cookie queue */ +static void +ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie) +{ + /* Insert first */ + A_ASSERT(ar != NULL); + A_ASSERT(cookie != NULL); + cookie->arc_list_next = ar->arCookieList; + ar->arCookieList = cookie; +} + +/* cleanup cookie queue */ +static struct ar_cookie * +ar6000_alloc_cookie(AR_SOFTC_T *ar) +{ + struct ar_cookie *cookie; + + cookie = ar->arCookieList; + if(cookie != NULL) + { + ar->arCookieList = cookie->arc_list_next; + } + + return cookie; +} + +#ifdef SEND_EVENT_TO_APP +/* + * This function is used to send event which come from taget to + * the application. The buf which send to application is include + * the event ID and event content. + */ +#define EVENT_ID_LEN 2 +void ar6000_send_event_to_app(AR_SOFTC_T *ar, A_UINT16 eventId, + A_UINT8 *datap, int len) +{ + +#if (WIRELESS_EXT >= 15) + +/* note: IWEVCUSTOM only exists in wireless extensions after version 15 */ + + char *buf; + A_UINT16 size; + union iwreq_data wrqu; + + size = len + EVENT_ID_LEN; + + if (size > IW_CUSTOM_MAX) { + AR_DEBUG_PRINTF("WMI event ID : 0x%4.4X, len = %d too big for IWEVCUSTOM (max=%d) \n", + eventId, size, IW_CUSTOM_MAX); + return; + } + + buf = A_MALLOC_NOWAIT(size); + if (NULL == buf){ + AR_DEBUG_PRINTF("%s: failed to allocate %d bytes\n", __func__, size); + return; + } + + A_MEMZERO(buf, size); + A_MEMCPY(buf, &eventId, EVENT_ID_LEN); + A_MEMCPY(buf+EVENT_ID_LEN, datap, len); + + //AR_DEBUG_PRINTF("event ID = %d,len = %d\n",*(A_UINT16*)buf, size); + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = size; + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + + A_FREE(buf); +#endif + + +} + +/* + * This function is used to send events larger than 256 bytes + * to the application. The buf which is sent to application + * includes the event ID and event content. + */ +void ar6000_send_generic_event_to_app(AR_SOFTC_T *ar, A_UINT16 eventId, + A_UINT8 *datap, int len) +{ + +#if (WIRELESS_EXT >= 18) + +/* IWEVGENIE exists in wireless extensions version 18 onwards */ + + char *buf; + A_UINT16 size; + union iwreq_data wrqu; + + size = len + EVENT_ID_LEN; + + if (size > IW_GENERIC_IE_MAX) { + AR_DEBUG_PRINTF("WMI event ID : 0x%4.4X, len = %d too big for IWEVGENIE (max=%d) \n", + eventId, size, IW_GENERIC_IE_MAX); + return; + } + + buf = A_MALLOC_NOWAIT(size); + if (NULL == buf){ + AR_DEBUG_PRINTF("%s: failed to allocate %d bytes\n", __func__, size); + return; + } + + A_MEMZERO(buf, size); + A_MEMCPY(buf, &eventId, EVENT_ID_LEN); + A_MEMCPY(buf+EVENT_ID_LEN, datap, len); + + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = size; + wireless_send_event(ar->arNetDev, IWEVGENIE, &wrqu, buf); + + A_FREE(buf); + +#endif /* (WIRELESS_EXT >= 18) */ + +} +#endif /* SEND_EVENT_TO_APP */ + + +void +ar6000_tx_retry_err_event(void *devt) +{ + AR_DEBUG2_PRINTF("Tx retries reach maximum!\n"); +} + +void +ar6000_snrThresholdEvent_rx(void *devt, WMI_SNR_THRESHOLD_VAL newThreshold, A_UINT8 snr) +{ + WMI_SNR_THRESHOLD_EVENT event; + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + event.range = newThreshold; + event.snr = snr; + + ar6000_send_event_to_app(ar, WMI_SNR_THRESHOLD_EVENTID, (A_UINT8 *)&event, + sizeof(WMI_SNR_THRESHOLD_EVENT)); +} + +void +ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL newThreshold, A_UINT8 lq) +{ + AR_DEBUG2_PRINTF("lq threshold range %d, lq %d\n", newThreshold, lq); +} + + + +A_UINT32 +a_copy_to_user(void *to, const void *from, A_UINT32 n) +{ + return(copy_to_user(to, from, n)); +} + +A_UINT32 +a_copy_from_user(void *to, const void *from, A_UINT32 n) +{ + return(copy_from_user(to, from, n)); +} + + +A_STATUS +ar6000_get_driver_cfg(struct net_device *dev, + A_UINT16 cfgParam, + void *result) +{ + + A_STATUS ret = 0; + + switch(cfgParam) + { + case AR6000_DRIVER_CFG_GET_WLANNODECACHING: + *((A_UINT32 *)result) = wlanNodeCaching; + break; + case AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS: + *((A_UINT32 *)result) = logWmiRawMsgs; + break; + default: + ret = EINVAL; + break; + } + + return ret; +} + +void +ar6000_keepalive_rx(void *devt, A_UINT8 configured) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arKeepaliveConfigured = configured; + wake_up(&arEvent); +} + +void +ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID, WMI_PMKID *pmkidList, + A_UINT8 *bssidList) +{ + A_UINT8 i, j; + + A_PRINTF("Number of Cached PMKIDs is %d\n", numPMKID); + + for (i = 0; i < numPMKID; i++) { + A_PRINTF("\nBSSID %d ", i); + for (j = 0; j < ATH_MAC_LEN; j++) { + A_PRINTF("%2.2x", bssidList[j]); + } + bssidList += (ATH_MAC_LEN + WMI_PMKID_LEN); + A_PRINTF("\nPMKID %d ", i); + for (j = 0; j < WMI_PMKID_LEN; j++) { + A_PRINTF("%2.2x", pmkidList->pmkid[j]); + } + pmkidList = (WMI_PMKID *)((A_UINT8 *)pmkidList + ATH_MAC_LEN + + WMI_PMKID_LEN); + } +} + +void ar6000_pspoll_event(AR_SOFTC_T *ar,A_UINT8 aid) +{ + sta_t *conn=NULL; + A_BOOL isPsqEmpty = FALSE; + + conn = ieee80211_find_conn_for_aid(ar, aid); + + /* If the PS q for this STA is not empty, dequeue and send a pkt from + * the head of the q. Also update the More data bit in the WMI_DATA_HDR + * if there are more pkts for this STA in the PS q. If there are no more + * pkts for this STA, update the PVB for this STA. + */ + A_MUTEX_LOCK(&conn->psqLock); + isPsqEmpty = A_NETBUF_QUEUE_EMPTY(&conn->psq); + A_MUTEX_UNLOCK(&conn->psqLock); + + if (isPsqEmpty) { + /* TODO:No buffered pkts for this STA. Send out a NULL data frame */ + } else { + struct sk_buff *skb = NULL; + + A_MUTEX_LOCK(&conn->psqLock); + skb = A_NETBUF_DEQUEUE(&conn->psq); + A_MUTEX_UNLOCK(&conn->psqLock); + /* Set the STA flag to PSPolled, so that the frame will go out */ + STA_SET_PS_POLLED(conn); + ar6000_data_tx(skb, ar->arNetDev); + STA_CLR_PS_POLLED(conn); + + /* Clear the PVB for this STA if the queue has become empty */ + A_MUTEX_LOCK(&conn->psqLock); + isPsqEmpty = A_NETBUF_QUEUE_EMPTY(&conn->psq); + A_MUTEX_UNLOCK(&conn->psqLock); + + if (isPsqEmpty) { + wmi_set_pvb_cmd(ar->arWmi, conn->aid, 0); + } + } +} + +void ar6000_dtimexpiry_event(AR_SOFTC_T *ar) +{ + A_BOOL isMcastQueued = FALSE; + struct sk_buff *skb = NULL; + + A_MUTEX_LOCK(&ar->mcastpsqLock); + isMcastQueued = A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq); + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + + A_ASSERT(isMcastQueued == FALSE); + + /* Flush the mcast psq to the target */ + /* Set the STA flag to DTIMExpired, so that the frame will go out */ + ar->DTIMExpired = TRUE; + + A_MUTEX_LOCK(&ar->mcastpsqLock); + while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) { + skb = A_NETBUF_DEQUEUE(&ar->mcastpsq); + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + + ar6000_data_tx(skb, ar->arNetDev); + + A_MUTEX_LOCK(&ar->mcastpsqLock); + } + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + + /* Reset the DTIMExpired flag back to 0 */ + ar->DTIMExpired = FALSE; + + /* Clear the LSB of the BitMapCtl field of the TIM IE */ + wmi_set_pvb_cmd(ar->arWmi, MCAST_AID, 0); +} + +#ifdef USER_KEYS +static A_STATUS + +ar6000_reinstall_keys(AR_SOFTC_T *ar, A_UINT8 key_op_ctrl) +{ + A_STATUS status = A_OK; + struct ieee80211req_key *uik = &ar->user_saved_keys.ucast_ik; + struct ieee80211req_key *bik = &ar->user_saved_keys.bcast_ik; + CRYPTO_TYPE keyType = ar->user_saved_keys.keyType; + + if (IEEE80211_CIPHER_CCKM_KRK != uik->ik_type) { + if (NONE_CRYPT == keyType) { + goto _reinstall_keys_out; + } + + if (uik->ik_keylen) { + status = wmi_addKey_cmd(ar->arWmi, uik->ik_keyix, + ar->user_saved_keys.keyType, PAIRWISE_USAGE, + uik->ik_keylen, (A_UINT8 *)&uik->ik_keyrsc, + uik->ik_keydata, key_op_ctrl, uik->ik_macaddr, SYNC_BEFORE_WMIFLAG); + } + + } else { + status = wmi_add_krk_cmd(ar->arWmi, uik->ik_keydata); + } + + if (IEEE80211_CIPHER_CCKM_KRK != bik->ik_type) { + if (NONE_CRYPT == keyType) { + goto _reinstall_keys_out; + } + + if (bik->ik_keylen) { + status = wmi_addKey_cmd(ar->arWmi, bik->ik_keyix, + ar->user_saved_keys.keyType, GROUP_USAGE, + bik->ik_keylen, (A_UINT8 *)&bik->ik_keyrsc, + bik->ik_keydata, key_op_ctrl, bik->ik_macaddr, NO_SYNC_WMIFLAG); + } + } else { + status = wmi_add_krk_cmd(ar->arWmi, bik->ik_keydata); + } + +_reinstall_keys_out: + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT; + ar->user_key_ctrl = 0; + + return status; +} +#endif /* USER_KEYS */ + + +void +ar6000_dset_open_req( + void *context, + A_UINT32 id, + A_UINT32 targHandle, + A_UINT32 targReplyFn, + A_UINT32 targReplyArg) +{ +} + +void +ar6000_dset_close( + void *context, + A_UINT32 access_cookie) +{ + return; +} + +void +ar6000_dset_data_req( + void *context, + A_UINT32 accessCookie, + A_UINT32 offset, + A_UINT32 length, + A_UINT32 targBuf, + A_UINT32 targReplyFn, + A_UINT32 targReplyArg) +{ +} + +int +ar6000_ap_mode_profile_commit(struct ar6_softc *ar) +{ + WMI_CONNECT_CMD p; + struct ieee80211req_key *ik; + CRYPTO_TYPE keyType = NONE_CRYPT; + + /* No change in AP's profile configuration */ + if(ar->ap_profile_flag==0) { + A_PRINTF("COMMIT: No change in profile!!!\n"); + return -ENODATA; + } + + if(!ar->arSsidLen) { + A_PRINTF("SSID not set!!!\n"); + return -ECHRNG; + } + + if(!ar->arChannelHint) { + /* Without channel info, can't start AP */ + A_PRINTF("Channel not set!!!\n"); + return -ECHRNG; + } + + if(ar->arPairwiseCrypto != ar->arGroupCrypto) { + A_PRINTF("Mixed cipher not supported in AP mode\n"); + return -EOPNOTSUPP; + } + + switch(ar->arAuthMode) { + case NONE_AUTH: + if((ar->arPairwiseCrypto != NONE_CRYPT) && + (ar->arPairwiseCrypto != WEP_CRYPT)) { + A_PRINTF("Cipher not supported in AP mode Open auth\n"); + return -EOPNOTSUPP; + } + break; + case WPA_PSK_AUTH: + if(ar->arPairwiseCrypto != TKIP_CRYPT) { + A_PRINTF("Cipher not supported in AP mode WPA\n"); + return -EOPNOTSUPP; + } + break; + case WPA2_PSK_AUTH: + if(ar->arPairwiseCrypto != AES_CRYPT) { + A_PRINTF("Cipher not supported in AP mode WPA2\n"); + return -EOPNOTSUPP; + } + break; + case WPA_AUTH: + case WPA2_AUTH: + case WPA_AUTH_CCKM: + case WPA2_AUTH_CCKM: + A_PRINTF("This key mgmt type not supported in AP mode\n"); + return -EOPNOTSUPP; + } + + /* Update the arNetworkType */ + ar->arNetworkType = ar->arNextMode; + + A_MEMZERO(&p,sizeof(p)); + p.ssidLength = ar->arSsidLen; + A_MEMCPY(p.ssid,ar->arSsid,p.ssidLength); + p.channel = ar->arChannelHint; + p.networkType = ar->arNetworkType; + + p.dot11AuthMode = ar->arDot11AuthMode; + p.authMode = ar->arAuthMode; + p.pairwiseCryptoType = ar->arPairwiseCrypto; + p.pairwiseCryptoLen = ar->arPairwiseCryptoLen; + p.groupCryptoType = ar->arGroupCrypto; + p.groupCryptoLen = ar->arGroupCryptoLen; + p.ctrl_flags = ar->arConnectCtrlFlags; + + wmi_ap_profile_commit(ar->arWmi, &p); + ar->arConnected = TRUE; + ar->ap_profile_flag = 0; + + switch(ar->arAuthMode) { + case NONE_AUTH: + if(ar->arPairwiseCrypto == WEP_CRYPT) { + ar6000_install_static_wep_keys(ar); + } + break; + case WPA_PSK_AUTH: + case WPA2_PSK_AUTH: + ik = &ar->ap_mode_bkey; + switch (ik->ik_type) { + case IEEE80211_CIPHER_TKIP: + keyType = TKIP_CRYPT; + break; + case IEEE80211_CIPHER_AES_CCM: + keyType = AES_CRYPT; + break; + default: + goto skip_key; + } + wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, GROUP_USAGE, + ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc, + ik->ik_keydata, KEY_OP_INIT_VAL, ik->ik_macaddr, + SYNC_BOTH_WMIFLAG); + + break; + } + +skip_key: + return 0; +} + +A_STATUS +ar6000_ap_mode_get_wpa_ie(struct ar6_softc *ar, struct ieee80211req_wpaie *wpaie) +{ + sta_t *conn = NULL; + conn = ieee80211_find_conn(ar, wpaie->wpa_macaddr); + + A_MEMZERO(wpaie->wpa_ie, IEEE80211_MAX_IE); + A_MEMZERO(wpaie->rsn_ie, IEEE80211_MAX_IE); + + if(conn) { + A_MEMCPY(wpaie->wpa_ie, conn->wpa_ie, IEEE80211_MAX_IE); + } + + return 0; +} + +A_STATUS +is_iwioctl_allowed(A_UINT8 mode, A_UINT16 cmd) +{ + if(cmd >= SIOCSIWCOMMIT && cmd <= SIOCGIWPOWER) { + cmd -= SIOCSIWCOMMIT; + if(sioctl_filter[cmd] == 0xFF) return A_OK; + if(sioctl_filter[cmd] & mode) return A_OK; + } else if(cmd >= SIOCIWFIRSTPRIV && cmd <= (SIOCIWFIRSTPRIV+30)) { + cmd -= SIOCIWFIRSTPRIV; + if(pioctl_filter[cmd] == 0xFF) return A_OK; + if(pioctl_filter[cmd] & mode) return A_OK; + } else { + return A_ERROR; + } + return A_ENOTSUP; +} + +A_STATUS +is_xioctl_allowed(A_UINT8 mode, int cmd) +{ + if(sizeof(xioctl_filter)-1 < cmd) { + A_PRINTF("Filter for this cmd=%d not defined\n",cmd); + return 0; + } + if(xioctl_filter[cmd] == 0xFF) return A_OK; + if(xioctl_filter[cmd] & mode) return A_OK; + return A_ERROR; +} +void ar6000_peer_event( + void *context, + A_UINT8 eventCode, + A_UINT8 *macAddr) +{ + A_UINT8 pos; + + for (pos=0;pos<6;pos++) + printk("%02x: ",*(macAddr+pos)); + printk("\n"); +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/ar6000_drv.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6000_drv.h --- linux-2.6.26/drivers/net/wireless/ath6k22/ar6000_drv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6000_drv.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,447 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _AR6000_H_ +#define _AR6000_H_ + +#include + + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,17) +#include +#else +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) +#include +#else +#include +#endif +#include +#include +#include + +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "htc_api.h" +#include "wmi.h" +#include "a_drv.h" +#include "bmi.h" +#include "ieee80211.h" +#include "ieee80211_ioctl.h" +#include "wlan_api.h" +#include "wmi_api.h" +#include "gpio_api.h" +#include "gpio.h" +#include "host_version.h" +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +#include +#else +#include +#include +#endif +#include "mbox_host_reg.h" +#include "mbox_reg.h" +#include "rtc_reg.h" +#include "ar6000_api.h" +#ifdef CONFIG_HOST_TCMD_SUPPORT +#include "testcmd.h" +#endif + +#include "targaddrs.h" +#include "dbglog_api.h" +#include "ar6000_diag.h" +#include "common_drv.h" +#include "roaming.h" + +#ifndef __dev_put +#define __dev_put(dev) dev_put(dev) +#endif + + +#ifdef USER_KEYS + +#define USER_SAVEDKEYS_STAT_INIT 0 +#define USER_SAVEDKEYS_STAT_RUN 1 + +// TODO this needs to move into the AR_SOFTC struct +struct USER_SAVEDKEYS { + struct ieee80211req_key ucast_ik; + struct ieee80211req_key bcast_ik; + CRYPTO_TYPE keyType; + A_BOOL keyOk; +}; +#endif + +#define DBG_INFO 0x00000001 +#define DBG_ERROR 0x00000002 +#define DBG_WARNING 0x00000004 +#define DBG_SDIO 0x00000008 +#define DBG_HIF 0x00000010 +#define DBG_HTC 0x00000020 +#define DBG_WMI 0x00000040 +#define DBG_WMI2 0x00000080 +#define DBG_DRIVER 0x00000100 + +#define DBG_DEFAULTS (DBG_ERROR|DBG_WARNING) + + +#ifdef DEBUG +#define AR_DEBUG_PRINTF(args...) if (debugdriver) A_PRINTF(args); +#define AR_DEBUG2_PRINTF(args...) if (debugdriver >= 2) A_PRINTF(args); +extern int debugdriver; +#else +#define AR_DEBUG_PRINTF(args...) +#define AR_DEBUG2_PRINTF(args...) +#endif + +A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); +A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAX_AR6000 1 +#define AR6000_MAX_RX_BUFFERS 16 +#define AR6000_BUFFER_SIZE 1664 +#define AR6000_TX_TIMEOUT 10 +#define AR6000_ETH_ADDR_LEN 6 +#define AR6000_MAX_ENDPOINTS 4 +#define MAX_NODE_NUM 15 +#define MAX_COOKIE_NUM 150 +#define AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT 1 +#define AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT 1 +#define A_DISCONNECT_TIMER_INTERVAL 5 * 1000 + +enum { + DRV_HB_CHALLENGE = 0, + APP_HB_CHALLENGE +}; + +/* HTC RAW streams */ +typedef enum _HTC_RAW_STREAM_ID { + HTC_RAW_STREAM_NOT_MAPPED = -1, + HTC_RAW_STREAM_0 = 0, + HTC_RAW_STREAM_1 = 1, + HTC_RAW_STREAM_2 = 2, + HTC_RAW_STREAM_3 = 3, + HTC_RAW_STREAM_NUM_MAX +} HTC_RAW_STREAM_ID; + +#define RAW_HTC_READ_BUFFERS_NUM 4 +#define RAW_HTC_WRITE_BUFFERS_NUM 4 + +typedef struct { + int currPtr; + int length; + unsigned char data[AR6000_BUFFER_SIZE]; + HTC_PACKET HTCPacket; +} raw_htc_buffer; + +#ifdef CONFIG_HOST_TCMD_SUPPORT +/* + * add TCMD_MODE besides wmi and bypasswmi + * in TCMD_MODE, only few TCMD releated wmi commands + * counld be hanlder + */ +enum { + AR6000_WMI_MODE = 0, + AR6000_BYPASS_MODE, + AR6000_TCMD_MODE, + AR6000_WLAN_MODE +}; +#endif /* CONFIG_HOST_TCMD_SUPPORT */ + +struct ar_wep_key { + A_UINT8 arKeyIndex; + A_UINT8 arKeyLen; + A_UINT8 arKey[64]; +} ; + +struct ar_node_mapping { + A_UINT8 macAddress[6]; + A_UINT8 epId; + A_UINT8 txPending; +}; + +struct ar_cookie { + A_UINT32 arc_bp[2]; /* Must be first field */ + HTC_PACKET HtcPkt; /* HTC packet wrapper */ + struct ar_cookie *arc_list_next; +}; + +struct ar_hb_chlng_resp { + A_TIMER timer; + A_UINT32 frequency; + A_UINT32 seqNum; + A_BOOL outstanding; + A_UINT8 missCnt; + A_UINT8 missThres; +}; + +/* Per STA data, used in AP mode */ +/*TODO: All this should move to OS independent dir */ + +#define STA_PWR_MGMT_MASK 0x1 +#define STA_PWR_MGMT_SHIFT 0x0 +#define STA_PWR_MGMT_AWAKE 0x0 +#define STA_PWR_MGMT_SLEEP 0x1 + +#define STA_SET_PWR_SLEEP(sta) (sta->flags |= (STA_PWR_MGMT_MASK << STA_PWR_MGMT_SHIFT)) +#define STA_CLR_PWR_SLEEP(sta) (sta->flags &= ~(STA_PWR_MGMT_MASK << STA_PWR_MGMT_SHIFT)) +#define STA_IS_PWR_SLEEP(sta) ((sta->flags >> STA_PWR_MGMT_SHIFT) & STA_PWR_MGMT_MASK) + +#define STA_PS_POLLED_MASK 0x1 +#define STA_PS_POLLED_SHIFT 0x1 +#define STA_SET_PS_POLLED(sta) (sta->flags |= (STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT)) +#define STA_CLR_PS_POLLED(sta) (sta->flags &= ~(STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT)) +#define STA_IS_PS_POLLED(sta) (sta->flags & (STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT)) + +typedef struct { + A_UINT16 flags; + A_UINT8 mac[ATH_MAC_LEN]; + A_UINT8 aid; + A_UINT8 wpa_ie[IEEE80211_MAX_IE]; + A_NETBUF_QUEUE_T psq; /* power save q */ + A_MUTEX_T psqLock; +} sta_t; + +typedef struct ar6_softc { + struct net_device *arNetDev; /* net_device pointer */ + void *arWmi; + int arTxPending[ENDPOINT_MAX]; + int arTotalTxDataPending; + A_UINT8 arNumDataEndPts; + A_BOOL arWmiEnabled; + A_BOOL arWmiReady; + A_BOOL arConnected; + HTC_HANDLE arHtcTarget; + void *arHifDevice; + spinlock_t arLock; + struct compat_semaphore arSem; + int arRxBuffers[ENDPOINT_MAX]; + int arSsidLen; + u_char arSsid[32]; + A_UINT8 arNextMode; + A_UINT8 arNetworkType; + A_UINT8 arDot11AuthMode; + A_UINT8 arAuthMode; + A_UINT8 arPairwiseCrypto; + A_UINT8 arPairwiseCryptoLen; + A_UINT8 arGroupCrypto; + A_UINT8 arGroupCryptoLen; + A_UINT8 arDefTxKeyIndex; + struct ar_wep_key arWepKeyList[WMI_MAX_KEY_INDEX + 1]; + A_UINT8 arBssid[6]; + A_UINT8 arReqBssid[6]; + A_UINT16 arChannelHint; + A_UINT16 arBssChannel; + A_UINT16 arListenInterval; + struct ar6000_version arVersion; + A_UINT32 arTargetType; + A_INT8 arRssi; + A_UINT8 arTxPwr; + A_BOOL arTxPwrSet; + A_INT32 arBitRate; + struct net_device_stats arNetStats; + struct iw_statistics arIwStats; + A_INT8 arNumChannels; + A_UINT16 arChannelList[32]; + A_UINT32 arRegCode; + A_BOOL statsUpdatePending; + TARGET_STATS arTargetStats; + A_INT8 arMaxRetries; + A_UINT8 arPhyCapability; +#ifdef CONFIG_HOST_TCMD_SUPPORT + A_UINT8 tcmdRxReport; + A_UINT32 tcmdRxTotalPkt; + A_INT32 tcmdRxRssi; + A_UINT32 tcmdPm; + A_UINT32 arTargetMode; + A_UINT32 tcmdRxcrcErrPkt; + A_UINT32 tcmdRxsecErrPkt; +#endif + AR6000_WLAN_STATE arWlanState; + struct ar_node_mapping arNodeMap[MAX_NODE_NUM]; + A_UINT8 arIbssPsEnable; + A_UINT8 arNodeNum; + A_UINT8 arNexEpId; + struct ar_cookie *arCookieList; + A_UINT16 arRateMask; + A_UINT8 arSkipScan; + A_UINT16 arBeaconInterval; + A_BOOL arConnectPending; + A_BOOL arWmmEnabled; + struct ar_hb_chlng_resp arHBChallengeResp; + A_UINT8 arKeepaliveConfigured; + A_UINT32 arMgmtFilter; + HTC_ENDPOINT_ID arAc2EpMapping[WMM_NUM_AC]; + A_BOOL arAcStreamActive[WMM_NUM_AC]; + A_UINT8 arAcStreamPriMap[WMM_NUM_AC]; + A_UINT8 arHiAcStreamActivePri; + A_UINT8 arEp2AcMapping[ENDPOINT_MAX]; + HTC_ENDPOINT_ID arControlEp; +#ifdef HTC_RAW_INTERFACE + HTC_ENDPOINT_ID arRaw2EpMapping[HTC_RAW_STREAM_NUM_MAX]; + HTC_RAW_STREAM_ID arEp2RawMapping[ENDPOINT_MAX]; + struct compat_semaphore raw_htc_read_sem[HTC_RAW_STREAM_NUM_MAX]; + struct compat_semaphore raw_htc_write_sem[HTC_RAW_STREAM_NUM_MAX]; + wait_queue_head_t raw_htc_read_queue[HTC_RAW_STREAM_NUM_MAX]; + wait_queue_head_t raw_htc_write_queue[HTC_RAW_STREAM_NUM_MAX]; + raw_htc_buffer raw_htc_read_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_READ_BUFFERS_NUM]; + raw_htc_buffer raw_htc_write_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_WRITE_BUFFERS_NUM]; + A_BOOL write_buffer_available[HTC_RAW_STREAM_NUM_MAX]; + A_BOOL read_buffer_available[HTC_RAW_STREAM_NUM_MAX]; +#endif + A_BOOL arNetQueueStopped; + A_BOOL arRawIfInit; + int arDeviceIndex; + COMMON_CREDIT_STATE_INFO arCreditStateInfo; + A_BOOL arWMIControlEpFull; + A_BOOL dbgLogFetchInProgress; + A_UCHAR log_buffer[DBGLOG_HOST_LOG_BUFFER_SIZE]; + A_UINT32 log_cnt; + A_UINT32 dbglog_init_done; + A_UINT32 arConnectCtrlFlags; +#ifdef USER_KEYS + A_INT32 user_savedkeys_stat; + A_UINT32 user_key_ctrl; + struct USER_SAVEDKEYS user_saved_keys; +#endif + A_UINT32 scan_complete; + USER_RSSI_THOLD rssi_map[12]; + A_UINT16 ap_profile_flag; /* AP mode */ + WMI_AP_ACL g_acl; /* AP mode */ + sta_t sta_list[AP_MAX_NUM_STA]; /* AP mode */ + A_UINT8 sta_list_index; /* AP mode */ + struct ieee80211req_key ap_mode_bkey; /* AP mode */ + A_NETBUF_QUEUE_T mcastpsq; /* power save q for Mcast frames */ + A_MUTEX_T mcastpsqLock; + A_BOOL DTIMExpired; /* flag to indicate DTIM expired */ + A_UINT8 intra_bss; /* enable/disable intra bss data forward */ + A_BOOL bIsDestroyProgress; /* flag to indicate ar6k destroy is in progress */ + A_TIMER disconnect_timer; +} AR_SOFTC_T; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +/* Looks like we need this for 2.4 kernels */ +static inline void *netdev_priv(struct net_device *dev) +{ + return(dev->priv); +} +#endif + +#define arAc2EndpointID(ar,ac) (ar)->arAc2EpMapping[(ac)] +#define arSetAc2EndpointIDMap(ar,ac,ep) \ +{ (ar)->arAc2EpMapping[(ac)] = (ep); \ + (ar)->arEp2AcMapping[(ep)] = (ac); } +#define arEndpoint2Ac(ar,ep) (ar)->arEp2AcMapping[(ep)] + +#define arRawIfEnabled(ar) (ar)->arRawIfInit +#define arRawStream2EndpointID(ar,raw) (ar)->arRaw2EpMapping[(raw)] +#define arSetRawStream2EndpointIDMap(ar,raw,ep) \ +{ (ar)->arRaw2EpMapping[(raw)] = (ep); \ + (ar)->arEp2RawMapping[(ep)] = (raw); } +#define arEndpoint2RawStreamID(ar,ep) (ar)->arEp2RawMapping[(ep)] + +struct ar_giwscan_param { + char *current_ev; + char *end_buf; + A_UINT32 bytes_needed; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + struct iw_request_info *info; +#endif +}; + +#define AR6000_STAT_INC(ar, stat) (ar->arNetStats.stat++) + +#define AR6000_SPIN_LOCK(lock, param) do { \ + if (irqs_disabled()) { \ + AR_DEBUG_PRINTF("IRQs disabled:AR6000_LOCK\n"); \ + } \ + spin_lock_bh(lock); \ +} while (0) + +#define AR6000_SPIN_UNLOCK(lock, param) do { \ + if (irqs_disabled()) { \ + AR_DEBUG_PRINTF("IRQs disabled: AR6000_UNLOCK\n"); \ + } \ + spin_unlock_bh(lock); \ +} while (0) + +int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); +int ar6000_ioctl_dispatcher(struct net_device *dev, struct ifreq *rq, int cmd); +void ar6000_gpio_init(void); +void ar6000_init_profile_info(AR_SOFTC_T *ar); +void ar6000_install_static_wep_keys(AR_SOFTC_T *ar); +int ar6000_init(struct net_device *dev); +int ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar); +void ar6000_TxDataCleanup(AR_SOFTC_T *ar); + +#ifdef HTC_RAW_INTERFACE + +#ifndef __user +#define __user +#endif + +int ar6000_htc_raw_open(AR_SOFTC_T *ar); +int ar6000_htc_raw_close(AR_SOFTC_T *ar); +ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar, + HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t count); +ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar, + HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t count); + +#endif /* HTC_RAW_INTERFACE */ + +/* AP mode */ +/*TODO: These routines should be moved to a file that is common across OS */ +sta_t * +ieee80211_find_conn(AR_SOFTC_T *ar, A_UINT8 *node_addr); + +sta_t * +ieee80211_find_conn_for_aid(AR_SOFTC_T *ar, A_UINT8 aid); + +A_UINT8 +remove_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 reason); + +#ifdef __cplusplus +} +#endif + +#endif /* _AR6000_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/ar6000_raw_if.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6000_raw_if.c --- linux-2.6.26/drivers/net/wireless/ath6k22/ar6000_raw_if.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6000_raw_if.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,443 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#include "ar6000_drv.h" + +#ifdef HTC_RAW_INTERFACE + +static void +ar6000_htc_raw_read_cb(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + raw_htc_buffer *busy; + HTC_RAW_STREAM_ID streamID; + + busy = (raw_htc_buffer *)pPacket->pPktContext; + A_ASSERT(busy != NULL); + + if (pPacket->Status == A_ECANCELED) { + /* + * HTC provides A_ECANCELED status when it doesn't want to be refilled + * (probably due to a shutdown) + */ + return; + } + + streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint); + A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED); + +#ifdef CF + if (down_trylock(&ar->raw_htc_read_sem[streamID])) { +#else + if (down_interruptible(&ar->raw_htc_read_sem[streamID])) { +#endif /* CF */ + AR_DEBUG2_PRINTF("Unable to down the semaphore\n"); + } + + A_ASSERT((pPacket->Status != A_OK) || + (pPacket->pBuffer == (busy->data + HTC_HEADER_LEN))); + + busy->length = pPacket->ActualLength + HTC_HEADER_LEN; + busy->currPtr = HTC_HEADER_LEN; + ar->read_buffer_available[streamID] = TRUE; + //AR_DEBUG_PRINTF("raw read cb: 0x%X 0x%X \n", busy->currPtr,busy->length); + up(&ar->raw_htc_read_sem[streamID]); + + /* Signal the waiting process */ + AR_DEBUG2_PRINTF("Waking up the StreamID(%d) read process\n", streamID); + wake_up_interruptible(&ar->raw_htc_read_queue[streamID]); +} + +static void +ar6000_htc_raw_write_cb(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + raw_htc_buffer *free; + HTC_RAW_STREAM_ID streamID; + + free = (raw_htc_buffer *)pPacket->pPktContext; + A_ASSERT(free != NULL); + + if (pPacket->Status == A_ECANCELED) { + /* + * HTC provides A_ECANCELED status when it doesn't want to be refilled + * (probably due to a shutdown) + */ + return; + } + + streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint); + A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED); + +#ifdef CF + if (down_trylock(&ar->raw_htc_write_sem[streamID])) { +#else + if (down_interruptible(&ar->raw_htc_write_sem[streamID])) { +#endif + AR_DEBUG2_PRINTF("Unable to down the semaphore\n"); + } + + A_ASSERT(pPacket->pBuffer == (free->data + HTC_HEADER_LEN)); + + free->length = 0; + ar->write_buffer_available[streamID] = TRUE; + up(&ar->raw_htc_write_sem[streamID]); + + /* Signal the waiting process */ + AR_DEBUG2_PRINTF("Waking up the StreamID(%d) write process\n", streamID); + wake_up_interruptible(&ar->raw_htc_write_queue[streamID]); +} + +/* connect to a service */ +static A_STATUS ar6000_connect_raw_service(AR_SOFTC_T *ar, + HTC_RAW_STREAM_ID StreamID) +{ + A_STATUS status; + HTC_SERVICE_CONNECT_RESP response; + A_UINT8 streamNo; + HTC_SERVICE_CONNECT_REQ connect; + + do { + + A_MEMZERO(&connect,sizeof(connect)); + /* pass the stream ID as meta data to the RAW streams service */ + streamNo = (A_UINT8)StreamID; + connect.pMetaData = &streamNo; + connect.MetaDataLength = sizeof(A_UINT8); + /* these fields are the same for all endpoints */ + connect.EpCallbacks.pContext = ar; + connect.EpCallbacks.EpTxComplete = ar6000_htc_raw_write_cb; + connect.EpCallbacks.EpRecv = ar6000_htc_raw_read_cb; + /* simple interface, we don't need these optional callbacks */ + connect.EpCallbacks.EpRecvRefill = NULL; + connect.EpCallbacks.EpSendFull = NULL; + connect.MaxSendQueueDepth = RAW_HTC_WRITE_BUFFERS_NUM; + + /* connect to the raw streams service, we may be able to get 1 or more + * connections, depending on WHAT is running on the target */ + connect.ServiceID = HTC_RAW_STREAMS_SVC; + + A_MEMZERO(&response,sizeof(response)); + + /* try to connect to the raw stream, it is okay if this fails with + * status HTC_SERVICE_NO_MORE_EP */ + status = HTCConnectService(ar->arHtcTarget, + &connect, + &response); + + if (A_FAILED(status)) { + if (response.ConnectRespCode == HTC_SERVICE_NO_MORE_EP) { + AR_DEBUG_PRINTF("HTC RAW , No more streams allowed \n"); + status = A_OK; + } + break; + } + + /* set endpoint mapping for the RAW HTC streams */ + arSetRawStream2EndpointIDMap(ar,StreamID,response.Endpoint); + + AR_DEBUG_PRINTF("HTC RAW : stream ID: %d, endpoint: %d\n", + StreamID, arRawStream2EndpointID(ar,StreamID)); + + } while (FALSE); + + return status; +} + +int ar6000_htc_raw_open(AR_SOFTC_T *ar) +{ + A_STATUS status; + int streamID, endPt, count2; + raw_htc_buffer *buffer; + HTC_SERVICE_ID servicepriority; + + A_ASSERT(ar->arHtcTarget != NULL); + + /* wait for target */ + status = HTCWaitTarget(ar->arHtcTarget); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF("HTCWaitTarget failed (%d)\n", status); + return -ENODEV; + } + + for (endPt = 0; endPt < ENDPOINT_MAX; endPt++) { + ar->arEp2RawMapping[endPt] = HTC_RAW_STREAM_NOT_MAPPED; + } + + for (streamID = HTC_RAW_STREAM_0; streamID < HTC_RAW_STREAM_NUM_MAX; streamID++) { + /* Initialize the data structures */ + init_MUTEX(&ar->raw_htc_read_sem[streamID]); + init_MUTEX(&ar->raw_htc_write_sem[streamID]); + init_waitqueue_head(&ar->raw_htc_read_queue[streamID]); + init_waitqueue_head(&ar->raw_htc_write_queue[streamID]); + + /* try to connect to the raw service */ + status = ar6000_connect_raw_service(ar,streamID); + + if (A_FAILED(status)) { + break; + } + + if (arRawStream2EndpointID(ar,streamID) == 0) { + break; + } + + for (count2 = 0; count2 < RAW_HTC_READ_BUFFERS_NUM; count2 ++) { + /* Initialize the receive buffers */ + buffer = &ar->raw_htc_write_buffer[streamID][count2]; + memset(buffer, 0, sizeof(raw_htc_buffer)); + buffer = &ar->raw_htc_read_buffer[streamID][count2]; + memset(buffer, 0, sizeof(raw_htc_buffer)); + + SET_HTC_PACKET_INFO_RX_REFILL(&buffer->HTCPacket, + buffer, + buffer->data, + AR6000_BUFFER_SIZE, + arRawStream2EndpointID(ar,streamID)); + + /* Queue buffers to HTC for receive */ + if ((status = HTCAddReceivePkt(ar->arHtcTarget, &buffer->HTCPacket)) != A_OK) + { + BMIInit(); + return -EIO; + } + } + + for (count2 = 0; count2 < RAW_HTC_WRITE_BUFFERS_NUM; count2 ++) { + /* Initialize the receive buffers */ + buffer = &ar->raw_htc_write_buffer[streamID][count2]; + memset(buffer, 0, sizeof(raw_htc_buffer)); + } + + ar->read_buffer_available[streamID] = FALSE; + ar->write_buffer_available[streamID] = TRUE; + } + + if (A_FAILED(status)) { + return -EIO; + } + + AR_DEBUG_PRINTF("HTC RAW, number of streams the target supports: %d \n", streamID); + + servicepriority = HTC_RAW_STREAMS_SVC; /* only 1 */ + + /* set callbacks and priority list */ + HTCSetCreditDistribution(ar->arHtcTarget, + ar, + NULL, /* use default */ + NULL, /* use default */ + &servicepriority, + 1); + + /* Start the HTC component */ + if ((status = HTCStart(ar->arHtcTarget)) != A_OK) { + BMIInit(); + return -EIO; + } + + (ar)->arRawIfInit = TRUE; + + return 0; +} + +int ar6000_htc_raw_close(AR_SOFTC_T *ar) +{ + A_PRINTF("ar6000_htc_raw_close called \n"); + HTCStop(ar->arHtcTarget); + + /* reset the device */ + ar6000_reset_device(ar->arHifDevice, ar->arTargetType, TRUE); + /* Initialize the BMI component */ + BMIInit(); + + return 0; +} + +raw_htc_buffer * +get_filled_buffer(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID) +{ + int count; + raw_htc_buffer *busy; + + /* Check for data */ + for (count = 0; count < RAW_HTC_READ_BUFFERS_NUM; count ++) { + busy = &ar->raw_htc_read_buffer[StreamID][count]; + if (busy->length) { + break; + } + } + if (busy->length) { + ar->read_buffer_available[StreamID] = TRUE; + } else { + ar->read_buffer_available[StreamID] = FALSE; + } + + return busy; +} + +ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t length) +{ + int readPtr; + raw_htc_buffer *busy; + + if (arRawStream2EndpointID(ar,StreamID) == 0) { + AR_DEBUG_PRINTF("StreamID(%d) not connected! \n", StreamID); + return -EFAULT; + } + + if (down_interruptible(&ar->raw_htc_read_sem[StreamID])) { + return -ERESTARTSYS; + } + + busy = get_filled_buffer(ar,StreamID); + while (!ar->read_buffer_available[StreamID]) { + up(&ar->raw_htc_read_sem[StreamID]); + + /* Wait for the data */ + AR_DEBUG2_PRINTF("Sleeping StreamID(%d) read process\n", StreamID); + if (wait_event_interruptible(ar->raw_htc_read_queue[StreamID], + ar->read_buffer_available[StreamID])) + { + return -EINTR; + } + if (down_interruptible(&ar->raw_htc_read_sem[StreamID])) { + return -ERESTARTSYS; + } + busy = get_filled_buffer(ar,StreamID); + } + + /* Read the data */ + readPtr = busy->currPtr; + if (length > busy->length - HTC_HEADER_LEN) { + length = busy->length - HTC_HEADER_LEN; + } + if (copy_to_user(buffer, &busy->data[readPtr], length)) { + up(&ar->raw_htc_read_sem[StreamID]); + return -EFAULT; + } + + busy->currPtr += length; + + //AR_DEBUG_PRINTF("raw read ioctl: currPTR : 0x%X 0x%X \n", busy->currPtr,busy->length); + + if (busy->currPtr == busy->length) + { + busy->currPtr = 0; + busy->length = 0; + HTC_PACKET_RESET_RX(&busy->HTCPacket); + //AR_DEBUG_PRINTF("raw read ioctl: ep for packet:%d \n", busy->HTCPacket.Endpoint); + HTCAddReceivePkt(ar->arHtcTarget, &busy->HTCPacket); + } + ar->read_buffer_available[StreamID] = FALSE; + up(&ar->raw_htc_read_sem[StreamID]); + + return length; +} + +static raw_htc_buffer * +get_free_buffer(AR_SOFTC_T *ar, HTC_ENDPOINT_ID StreamID) +{ + int count; + raw_htc_buffer *free; + + free = NULL; + for (count = 0; count < RAW_HTC_WRITE_BUFFERS_NUM; count ++) { + free = &ar->raw_htc_write_buffer[StreamID][count]; + if (free->length == 0) { + break; + } + } + if (!free->length) { + ar->write_buffer_available[StreamID] = TRUE; + } else { + ar->write_buffer_available[StreamID] = FALSE; + } + + return free; +} + +ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t length) +{ + int writePtr; + raw_htc_buffer *free; + + if (arRawStream2EndpointID(ar,StreamID) == 0) { + AR_DEBUG_PRINTF("StreamID(%d) not connected! \n", StreamID); + return -EFAULT; + } + + if (down_interruptible(&ar->raw_htc_write_sem[StreamID])) { + return -ERESTARTSYS; + } + + /* Search for a free buffer */ + free = get_free_buffer(ar,StreamID); + + /* Check if there is space to write else wait */ + while (!ar->write_buffer_available[StreamID]) { + up(&ar->raw_htc_write_sem[StreamID]); + + /* Wait for buffer to become free */ + AR_DEBUG2_PRINTF("Sleeping StreamID(%d) write process\n", StreamID); + if (wait_event_interruptible(ar->raw_htc_write_queue[StreamID], + ar->write_buffer_available[StreamID])) + { + return -EINTR; + } + if (down_interruptible(&ar->raw_htc_write_sem[StreamID])) { + return -ERESTARTSYS; + } + free = get_free_buffer(ar,StreamID); + } + + /* Send the data */ + writePtr = HTC_HEADER_LEN; + if (length > (AR6000_BUFFER_SIZE - HTC_HEADER_LEN)) { + length = AR6000_BUFFER_SIZE - HTC_HEADER_LEN; + } + + if (copy_from_user(&free->data[writePtr], buffer, length)) { + up(&ar->raw_htc_read_sem[StreamID]); + return -EFAULT; + } + + free->length = length; + + SET_HTC_PACKET_INFO_TX(&free->HTCPacket, + free, + &free->data[writePtr], + length, + arRawStream2EndpointID(ar,StreamID), + AR6K_DATA_PKT_TAG); + + HTCSendPkt(ar->arHtcTarget,&free->HTCPacket); + + ar->write_buffer_available[StreamID] = FALSE; + up(&ar->raw_htc_write_sem[StreamID]); + + return length; +} +#endif /* HTC_RAW_INTERFACE */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/ar6k.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6k.c --- linux-2.6.26/drivers/net/wireless/ath6k22/ar6k.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6k.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,1033 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// AR6K device layer that handles register level I/O +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "mbox_host_reg.h" +#include "a_osapi.h" +#include "a_debug.h" +#include "hif.h" +#include "htc_packet.h" +#include "ar6k.h" + +#define MAILBOX_FOR_BLOCK_SIZE 1 + +extern A_UINT32 resetok; + +A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev); + +#define LOCK_AR6K(p) A_MUTEX_LOCK(&(p)->Lock); +#define UNLOCK_AR6K(p) A_MUTEX_UNLOCK(&(p)->Lock); + +void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket) +{ + LOCK_AR6K(pDev); + HTC_PACKET_ENQUEUE(&pDev->RegisterIOList,pPacket); + UNLOCK_AR6K(pDev); +} + +HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev) +{ + HTC_PACKET *pPacket; + + LOCK_AR6K(pDev); + pPacket = HTC_PACKET_DEQUEUE(&pDev->RegisterIOList); + UNLOCK_AR6K(pDev); + + return pPacket; +} + +void DevCleanup(AR6K_DEVICE *pDev) +{ + if (A_IS_MUTEX_VALID(&pDev->Lock)) { + A_MUTEX_DELETE(&pDev->Lock); + } + + if (pDev->HifAttached) { + HIFDetachHTC(pDev->HIFDevice); + pDev->HifAttached = FALSE; + } + +} + +A_STATUS DevSetup(AR6K_DEVICE *pDev) +{ + A_UINT32 mailboxaddrs[AR6K_MAILBOXES]; + A_UINT32 blocksizes[AR6K_MAILBOXES]; + A_STATUS status = A_OK; + int i; + HTC_CALLBACKS htcCallbacks; + + AR_DEBUG_ASSERT(AR6K_IRQ_PROC_REGS_SIZE == 16); + AR_DEBUG_ASSERT(AR6K_IRQ_ENABLE_REGS_SIZE == 4); + + do { + + A_MEMZERO(&htcCallbacks, sizeof(HTC_CALLBACKS)); + /* the device layer handles these */ + htcCallbacks.rwCompletionHandler = DevRWCompletionHandler; + htcCallbacks.dsrHandler = DevDsrHandler; + htcCallbacks.context = pDev; + + status = HIFAttachHTC(pDev->HIFDevice, &htcCallbacks); + + if (A_FAILED(status)) { + break; + } + + pDev->HifAttached = TRUE; + + /* initialize our free list of IO packets */ + INIT_HTC_PACKET_QUEUE(&pDev->RegisterIOList); + A_MUTEX_INIT(&pDev->Lock); + + /* get the addresses for all 4 mailboxes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR, + mailboxaddrs, sizeof(mailboxaddrs)); + + if (status != A_OK) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* carve up register I/O packets (these are for ASYNC register I/O ) */ + for (i = 0; i < AR6K_MAX_REG_IO_BUFFERS; i++) { + HTC_PACKET *pIOPacket; + pIOPacket = &pDev->RegIOBuffers[i].HtcPacket; + SET_HTC_PACKET_INFO_RX_REFILL(pIOPacket, + pDev, + pDev->RegIOBuffers[i].Buffer, + AR6K_REG_IO_BUFFER_SIZE, + 0); /* don't care */ + AR6KFreeIOPacket(pDev,pIOPacket); + } + + /* get the address of the mailbox we are using */ + pDev->MailboxAddress = mailboxaddrs[HTC_MAILBOX]; + + /* get the block sizes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + blocksizes, sizeof(blocksizes)); + + if (status != A_OK) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* note: we actually get the block size of a mailbox other than 0, for SDIO the block + * size on mailbox 0 is artificially set to 1. So we use the block size that is set + * for the other 3 mailboxes */ + pDev->BlockSize = blocksizes[MAILBOX_FOR_BLOCK_SIZE]; + /* must be a power of 2 */ + AR_DEBUG_ASSERT((pDev->BlockSize & (pDev->BlockSize - 1)) == 0); + + /* assemble mask, used for padding to a block */ + pDev->BlockMask = pDev->BlockSize - 1; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("BlockSize: %d, MailboxAddress:0x%X \n", + pDev->BlockSize, pDev->MailboxAddress)); + + pDev->GetPendingEventsFunc = NULL; + /* see if the HIF layer implements the get pending events function */ + HIFConfigureDevice(pDev->HIFDevice, + HIF_DEVICE_GET_PENDING_EVENTS_FUNC, + &pDev->GetPendingEventsFunc, + sizeof(pDev->GetPendingEventsFunc)); + + /* assume we can process HIF interrupt events asynchronously */ + pDev->HifIRQProcessingMode = HIF_DEVICE_IRQ_ASYNC_SYNC; + + /* see if the HIF layer overrides this assumption */ + HIFConfigureDevice(pDev->HIFDevice, + HIF_DEVICE_GET_IRQ_PROC_MODE, + &pDev->HifIRQProcessingMode, + sizeof(pDev->HifIRQProcessingMode)); + + switch (pDev->HifIRQProcessingMode) { + case HIF_DEVICE_IRQ_SYNC_ONLY: + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is SYNC ONLY\n")); + break; + case HIF_DEVICE_IRQ_ASYNC_SYNC: + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is ASYNC and SYNC\n")); + break; + default: + AR_DEBUG_ASSERT(FALSE); + } + + pDev->HifMaskUmaskRecvEvent = NULL; + + /* see if the HIF layer implements the mask/unmask recv events function */ + HIFConfigureDevice(pDev->HIFDevice, + HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC, + &pDev->HifMaskUmaskRecvEvent, + sizeof(pDev->HifMaskUmaskRecvEvent)); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF special overrides : 0x%X , 0x%X\n", + (A_UINT32)pDev->GetPendingEventsFunc, (A_UINT32)pDev->HifMaskUmaskRecvEvent)); + + status = DevDisableInterrupts(pDev); + + } while (FALSE); + + if (A_FAILED(status)) { + if (pDev->HifAttached) { + HIFDetachHTC(pDev->HIFDevice); + pDev->HifAttached = FALSE; + } + } + + return status; + +} + +A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev) +{ + A_STATUS status; + AR6K_IRQ_ENABLE_REGISTERS regs; + + LOCK_AR6K(pDev); + + /* Enable all the interrupts except for the internal AR6000 CPU interrupt */ + pDev->IrqEnableRegisters.int_status_enable = INT_STATUS_ENABLE_ERROR_SET(0x01) | + INT_STATUS_ENABLE_CPU_SET(0x01) | + INT_STATUS_ENABLE_COUNTER_SET(0x01); + + if (NULL == pDev->GetPendingEventsFunc) { + pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } else { + /* The HIF layer provided us with a pending events function which means that + * the detection of pending mbox messages is handled in the HIF layer. + * This is the case for the SPI2 interface. + * In the normal case we enable MBOX interrupts, for the case + * with HIFs that offer this mechanism, we keep these interrupts + * masked */ + pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } + + + /* Set up the CPU Interrupt Status Register */ + pDev->IrqEnableRegisters.cpu_int_status_enable = CPU_INT_STATUS_ENABLE_BIT_SET(0x00); + + /* Set up the Error Interrupt Status Register */ + pDev->IrqEnableRegisters.error_status_enable = + ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(0x01) | + ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(0x01); + + /* Set up the Counter Interrupt Status Register (only for debug interrupt to catch fatal errors) */ + pDev->IrqEnableRegisters.counter_int_status_enable = + COUNTER_INT_STATUS_ENABLE_BIT_SET(AR6K_TARGET_DEBUG_INTR_MASK); + + /* copy into our temp area */ + A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE); + + UNLOCK_AR6K(pDev); + +/* ATHENV */ +#ifdef ANDROID_ENV + mdelay(100); +#endif +/* ATHENV */ + /* always synchronous */ + status = HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + ®s.int_status_enable, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + /* Can't write it for some reason */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Failed to update interrupt control registers err: %d\n", status)); + + } + + return status; +} + +A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev) +{ + AR6K_IRQ_ENABLE_REGISTERS regs; + + LOCK_AR6K(pDev); + /* Disable all interrupts */ + pDev->IrqEnableRegisters.int_status_enable = 0; + pDev->IrqEnableRegisters.cpu_int_status_enable = 0; + pDev->IrqEnableRegisters.error_status_enable = 0; + pDev->IrqEnableRegisters.counter_int_status_enable = 0; + /* copy into our temp area */ + A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE); + + UNLOCK_AR6K(pDev); + + /* always synchronous */ + return HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + ®s.int_status_enable, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_SYNC_BYTE_INC, + NULL); +} + +/* enable device interrupts */ +A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev) +{ + /* for good measure, make sure interrupt are disabled before unmasking at the HIF + * layer. + * The rationale here is that between device insertion (where we clear the interrupts the first time) + * and when HTC is finally ready to handle interrupts, other software can perform target "soft" resets. + * The AR6K interrupt enables reset back to an "enabled" state when this happens. + * */ + DevDisableInterrupts(pDev); + + /* Unmask the host controller interrupts */ + HIFUnMaskInterrupt(pDev->HIFDevice); + + return DevEnableInterrupts(pDev); +} + +/* disable all device interrupts */ +A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev) +{ + /* mask the interrupt at the HIF layer, we don't want a stray interrupt taken while + * we zero out our shadow registers in DevDisableInterrupts()*/ + HIFMaskInterrupt(pDev->HIFDevice); + + return DevDisableInterrupts(pDev); +} + +/* callback when our fetch to enable/disable completes */ +static void DevDoEnableDisableRecvAsyncHandler(void *Context, HTC_PACKET *pPacket) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDoEnableDisableRecvAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); + + if (A_FAILED(pPacket->Status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" Failed to disable receiver, status:%d \n", pPacket->Status)); + } + /* free this IO packet */ + AR6KFreeIOPacket(pDev,pPacket); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDoEnableDisableRecvAsyncHandler \n")); +} + +/* disable packet reception (used in case the host runs out of buffers) + * this is the "override" method when the HIF reports another methods to + * disable recv events */ +static A_STATUS DevDoEnableDisableRecvOverride(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode) +{ + A_STATUS status = A_OK; + HTC_PACKET *pIOPacket = NULL; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("DevDoEnableDisableRecvOverride: Enable:%d Mode:%d\n", + EnableRecv,AsyncMode)); + + do { + + if (AsyncMode) { + + pIOPacket = AR6KAllocIOPacket(pDev); + + if (NULL == pIOPacket) { + status = A_NO_MEMORY; + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* stick in our completion routine when the I/O operation completes */ + pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler; + pIOPacket->pContext = pDev; + + /* call the HIF layer override and do this asynchronously */ + status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice, + EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV, + pIOPacket); + break; + } + + /* if we get here we are doing it synchronously */ + status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice, + EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV, + NULL); + + } while (FALSE); + + if (A_FAILED(status) && (pIOPacket != NULL)) { + AR6KFreeIOPacket(pDev,pIOPacket); + } + + return status; +} + +/* disable packet reception (used in case the host runs out of buffers) + * this is the "normal" method using the interrupt enable registers through + * the host I/F */ +static A_STATUS DevDoEnableDisableRecvNormal(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode) +{ + A_STATUS status = A_OK; + HTC_PACKET *pIOPacket = NULL; + AR6K_IRQ_ENABLE_REGISTERS regs; + + /* take the lock to protect interrupt enable shadows */ + LOCK_AR6K(pDev); + + if (EnableRecv) { + pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } else { + pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } + + /* copy into our temp area */ + A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE); + UNLOCK_AR6K(pDev); + + do { + + if (AsyncMode) { + + pIOPacket = AR6KAllocIOPacket(pDev); + + if (NULL == pIOPacket) { + status = A_NO_MEMORY; + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* copy values to write to our async I/O buffer */ + A_MEMCPY(pIOPacket->pBuffer,®s,AR6K_IRQ_ENABLE_REGS_SIZE); + + /* stick in our completion routine when the I/O operation completes */ + pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler; + pIOPacket->pContext = pDev; + + /* write it out asynchronously */ + HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + pIOPacket->pBuffer, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_ASYNC_BYTE_INC, + pIOPacket); + break; + } + + /* if we get here we are doing it synchronously */ + + status = HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + ®s.int_status_enable, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_SYNC_BYTE_INC, + NULL); + + } while (FALSE); + + if (A_FAILED(status) && (pIOPacket != NULL)) { + AR6KFreeIOPacket(pDev,pIOPacket); + } + + return status; +} + + +A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode) +{ + if (NULL == pDev->HifMaskUmaskRecvEvent) { + return DevDoEnableDisableRecvNormal(pDev,FALSE,AsyncMode); + } else { + return DevDoEnableDisableRecvOverride(pDev,FALSE,AsyncMode); + } +} + +A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode) +{ + if (NULL == pDev->HifMaskUmaskRecvEvent) { + return DevDoEnableDisableRecvNormal(pDev,TRUE,AsyncMode); + } else { + return DevDoEnableDisableRecvOverride(pDev,TRUE,AsyncMode); + } +} + +void DevDumpRegisters(AR6K_IRQ_PROC_REGISTERS *pIrqProcRegs, + AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs) +{ + + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("\n<------- Register Table -------->\n")); + + if (pIrqProcRegs != NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Int Status: 0x%x\n",pIrqProcRegs->host_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("CPU Int Status: 0x%x\n",pIrqProcRegs->cpu_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Error Int Status: 0x%x\n",pIrqProcRegs->error_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Counter Int Status: 0x%x\n",pIrqProcRegs->counter_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Mbox Frame: 0x%x\n",pIrqProcRegs->mbox_frame)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Rx Lookahead Valid: 0x%x\n",pIrqProcRegs->rx_lookahead_valid)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Rx Lookahead 0: 0x%x\n",pIrqProcRegs->rx_lookahead[0])); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Rx Lookahead 1: 0x%x\n",pIrqProcRegs->rx_lookahead[1])); + } + + if (pIrqEnableRegs != NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Int Status Enable: 0x%x\n",pIrqEnableRegs->int_status_enable)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Counter Int Status Enable: 0x%x\n",pIrqEnableRegs->counter_int_status_enable)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("<------------------------------->\n")); + } +} + + +#ifdef MBOXHW_UNIT_TEST + + +/* This is a mailbox hardware unit test that must be called in a schedulable context + * This test is very simple, it will send a list of buffers with a counting pattern + * and the target will invert the data and send the message back + * + * the unit test has the following constraints: + * + * The target has at least 8 buffers of 256 bytes each. The host will send + * the following pattern of buffers in rapid succession : + * + * 1 buffer - 128 bytes + * 1 buffer - 256 bytes + * 1 buffer - 512 bytes + * 1 buffer - 1024 bytes + * + * The host will send the buffers to one mailbox and wait for buffers to be reflected + * back from the same mailbox. The target sends the buffers FIFO order. + * Once the final buffer has been received for a mailbox, the next mailbox is tested. + * + * + * Note: To simplifythe test , we assume that the chosen buffer sizes + * will fall on a nice block pad + * + * It is expected that higher-order tests will be written to stress the mailboxes using + * a message-based protocol (with some performance timming) that can create more + * randomness in the packets sent over mailboxes. + * + * */ + +#define A_ROUND_UP_PWR2(x, align) (((int) (x) + ((align)-1)) & ~((align)-1)) + +#define BUFFER_BLOCK_PAD 128 + +#if 0 +#define BUFFER1 128 +#define BUFFER2 256 +#define BUFFER3 512 +#define BUFFER4 1024 +#endif + +#if 1 +#define BUFFER1 80 +#define BUFFER2 200 +#define BUFFER3 444 +#define BUFFER4 800 +#endif + +#define TOTAL_BYTES (A_ROUND_UP_PWR2(BUFFER1,BUFFER_BLOCK_PAD) + \ + A_ROUND_UP_PWR2(BUFFER2,BUFFER_BLOCK_PAD) + \ + A_ROUND_UP_PWR2(BUFFER3,BUFFER_BLOCK_PAD) + \ + A_ROUND_UP_PWR2(BUFFER4,BUFFER_BLOCK_PAD) ) + +#define TEST_BYTES (BUFFER1 + BUFFER2 + BUFFER3 + BUFFER4) + +#define TEST_CREDITS_RECV_TIMEOUT 100 + +static A_UINT8 g_Buffer[TOTAL_BYTES]; +static A_UINT32 g_MailboxAddrs[AR6K_MAILBOXES]; +static A_UINT32 g_BlockSizes[AR6K_MAILBOXES]; + +#define BUFFER_PROC_LIST_DEPTH 4 + +typedef struct _BUFFER_PROC_LIST{ + A_UINT8 *pBuffer; + A_UINT32 length; +}BUFFER_PROC_LIST; + + +#define PUSH_BUFF_PROC_ENTRY(pList,len,pCurrpos) \ +{ \ + (pList)->pBuffer = (pCurrpos); \ + (pList)->length = (len); \ + (pCurrpos) += (len); \ + (pList)++; \ +} + +/* a simple and crude way to send different "message" sizes */ +static void AssembleBufferList(BUFFER_PROC_LIST *pList) +{ + A_UINT8 *pBuffer = g_Buffer; + +#if BUFFER_PROC_LIST_DEPTH < 4 +#error "Buffer processing list depth is not deep enough!!" +#endif + + PUSH_BUFF_PROC_ENTRY(pList,BUFFER1,pBuffer); + PUSH_BUFF_PROC_ENTRY(pList,BUFFER2,pBuffer); + PUSH_BUFF_PROC_ENTRY(pList,BUFFER3,pBuffer); + PUSH_BUFF_PROC_ENTRY(pList,BUFFER4,pBuffer); + +} + +#define FILL_ZERO TRUE +#define FILL_COUNTING FALSE +static void InitBuffers(A_BOOL Zero) +{ + A_UINT16 *pBuffer16 = (A_UINT16 *)g_Buffer; + int i; + + /* fill buffer with 16 bit counting pattern or zeros */ + for (i = 0; i < (TOTAL_BYTES / 2) ; i++) { + if (!Zero) { + pBuffer16[i] = (A_UINT16)i; + } else { + pBuffer16[i] = 0; + } + } +} + + +static A_BOOL CheckOneBuffer(A_UINT16 *pBuffer16, int Length) +{ + int i; + A_UINT16 startCount; + A_BOOL success = TRUE; + + /* get the starting count */ + startCount = pBuffer16[0]; + /* invert it, this is the expected value */ + startCount = ~startCount; + /* scan the buffer and verify */ + for (i = 0; i < (Length / 2) ; i++,startCount++) { + /* target will invert all the data */ + if ((A_UINT16)pBuffer16[i] != (A_UINT16)~startCount) { + success = FALSE; + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Invalid Data Got:0x%X, Expecting:0x%X (offset:%d, total:%d) \n", + pBuffer16[i], ((A_UINT16)~startCount), i, Length)); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("0x%X 0x%X 0x%X 0x%X \n", + pBuffer16[i], pBuffer16[i + 1], pBuffer16[i + 2],pBuffer16[i+3])); + break; + } + } + + return success; +} + +static A_BOOL CheckBuffers(void) +{ + int i; + A_BOOL success = TRUE; + BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH]; + + /* assemble the list */ + AssembleBufferList(checkList); + + /* scan the buffers and verify */ + for (i = 0; i < BUFFER_PROC_LIST_DEPTH ; i++) { + success = CheckOneBuffer((A_UINT16 *)checkList[i].pBuffer, checkList[i].length); + if (!success) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer : 0x%X, Length:%d failed verify \n", + (A_UINT32)checkList[i].pBuffer, checkList[i].length)); + break; + } + } + + return success; +} + + /* find the end marker for the last buffer we will be sending */ +static A_UINT16 GetEndMarker(void) +{ + A_UINT8 *pBuffer; + BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH]; + + /* fill up buffers with the normal counting pattern */ + InitBuffers(FILL_COUNTING); + + /* assemble the list we will be sending down */ + AssembleBufferList(checkList); + /* point to the last 2 bytes of the last buffer */ + pBuffer = &(checkList[BUFFER_PROC_LIST_DEPTH - 1].pBuffer[(checkList[BUFFER_PROC_LIST_DEPTH - 1].length) - 2]); + + /* the last count in the last buffer is the marker */ + return (A_UINT16)pBuffer[0] | ((A_UINT16)pBuffer[1] << 8); +} + +#define ATH_PRINT_OUT_ZONE ATH_DEBUG_ERR + +/* send the ordered buffers to the target */ +static A_STATUS SendBuffers(AR6K_DEVICE *pDev, int mbox) +{ + A_STATUS status = A_OK; + A_UINT32 request = HIF_WR_SYNC_BLOCK_INC; + BUFFER_PROC_LIST sendList[BUFFER_PROC_LIST_DEPTH]; + int i; + int totalBytes = 0; + int paddedLength; + int totalwPadding = 0; + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sending buffers on mailbox : %d \n",mbox)); + + /* fill buffer with counting pattern */ + InitBuffers(FILL_COUNTING); + + /* assemble the order in which we send */ + AssembleBufferList(sendList); + + for (i = 0; i < BUFFER_PROC_LIST_DEPTH; i++) { + + /* we are doing block transfers, so we need to pad everything to a block size */ + paddedLength = (sendList[i].length + (g_BlockSizes[mbox] - 1)) & + (~(g_BlockSizes[mbox] - 1)); + + /* send each buffer synchronously */ + status = HIFReadWrite(pDev->HIFDevice, + g_MailboxAddrs[mbox], + sendList[i].pBuffer, + paddedLength, + request, + NULL); + if (status != A_OK) { + break; + } + totalBytes += sendList[i].length; + totalwPadding += paddedLength; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sent %d bytes (%d padded bytes) to mailbox : %d \n",totalBytes,totalwPadding,mbox)); + + return status; +} + +/* poll the mailbox credit counter until we get a credit or timeout */ +static A_STATUS GetCredits(AR6K_DEVICE *pDev, int mbox, int *pCredits) +{ + A_STATUS status = A_OK; + int timeout = TEST_CREDITS_RECV_TIMEOUT; + A_UINT8 credits = 0; + A_UINT32 address; + + while (TRUE) { + + /* Read the counter register to get credits, this auto-decrements */ + address = COUNT_DEC_ADDRESS + (AR6K_MAILBOXES + mbox) * 4; + status = HIFReadWrite(pDev->HIFDevice, address, &credits, sizeof(credits), + HIF_RD_SYNC_BYTE_FIX, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Unable to decrement the command credit count register (mbox=%d)\n",mbox)); + status = A_ERROR; + break; + } + + if (credits) { + break; + } + + timeout--; + + if (timeout <= 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" Timeout reading credit registers (mbox=%d, address:0x%X) \n",mbox,address)); + status = A_ERROR; + break; + } + + /* delay a little, target may not be ready */ + A_MDELAY(1000); + + } + + if (status == A_OK) { + *pCredits = credits; + } + + return status; +} + + +/* wait for the buffers to come back */ +static A_STATUS RecvBuffers(AR6K_DEVICE *pDev, int mbox) +{ + A_STATUS status = A_OK; + A_UINT32 request = HIF_RD_SYNC_BLOCK_INC; + BUFFER_PROC_LIST recvList[BUFFER_PROC_LIST_DEPTH]; + int curBuffer; + int credits; + int i; + int totalBytes = 0; + int paddedLength; + int totalwPadding = 0; + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for buffers on mailbox : %d \n",mbox)); + + /* zero the buffers */ + InitBuffers(FILL_ZERO); + + /* assemble the order in which we should receive */ + AssembleBufferList(recvList); + + curBuffer = 0; + + while (curBuffer < BUFFER_PROC_LIST_DEPTH) { + + /* get number of buffers that have been completed, this blocks + * until we get at least 1 credit or it times out */ + status = GetCredits(pDev, mbox, &credits); + + if (status != A_OK) { + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got %d messages on mailbox : %d \n",credits, mbox)); + + /* get all the buffers that are sitting on the queue */ + for (i = 0; i < credits; i++) { + AR_DEBUG_ASSERT(curBuffer < BUFFER_PROC_LIST_DEPTH); + /* recv the current buffer synchronously, the buffers should come back in + * order... with padding applied by the target */ + paddedLength = (recvList[curBuffer].length + (g_BlockSizes[mbox] - 1)) & + (~(g_BlockSizes[mbox] - 1)); + + status = HIFReadWrite(pDev->HIFDevice, + g_MailboxAddrs[mbox], + recvList[curBuffer].pBuffer, + paddedLength, + request, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to read %d bytes on mailbox:%d : address:0x%X \n", + recvList[curBuffer].length, mbox, g_MailboxAddrs[mbox])); + break; + } + + totalwPadding += paddedLength; + totalBytes += recvList[curBuffer].length; + curBuffer++; + } + + if (status != A_OK) { + break; + } + /* go back and get some more */ + credits = 0; + } + + if (totalBytes != TEST_BYTES) { + AR_DEBUG_ASSERT(FALSE); + } else { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got all buffers on mbox:%d total recv :%d (w/Padding : %d) \n", + mbox, totalBytes, totalwPadding)); + } + + return status; + + +} + +static A_STATUS DoOneMboxHWTest(AR6K_DEVICE *pDev, int mbox) +{ + A_STATUS status; + + do { + /* send out buffers */ + status = SendBuffers(pDev,mbox); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Sending buffers Failed : %d mbox:%d\n",status,mbox)); + break; + } + + /* go get them, this will block */ + status = RecvBuffers(pDev, mbox); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Recv buffers Failed : %d mbox:%d\n",status,mbox)); + break; + } + + /* check the returned data patterns */ + if (!CheckBuffers()) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer Verify Failed : mbox:%d\n",mbox)); + status = A_ERROR; + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" Send/Recv success! mailbox : %d \n",mbox)); + + } while (FALSE); + + return status; +} + +/* here is where the test starts */ +A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev) +{ + int i; + A_STATUS status; + int credits = 0; + A_UINT8 params[4]; + int numBufs; + int bufferSize; + A_UINT16 temp; + + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest START - \n")); + + do { + /* get the addresses for all 4 mailboxes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR, + g_MailboxAddrs, sizeof(g_MailboxAddrs)); + + if (status != A_OK) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* get the block sizes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + g_BlockSizes, sizeof(g_BlockSizes)); + + if (status != A_OK) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* note, the HIF layer usually reports mbox 0 to have a block size of + * 1, but our test wants to run in block-mode for all mailboxes, so we treat all mailboxes + * the same. */ + g_BlockSizes[0] = g_BlockSizes[1]; + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Block Size to use: %d \n",g_BlockSizes[0])); + + if (g_BlockSizes[1] > BUFFER_BLOCK_PAD) { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("%d Block size is too large for buffer pad %d\n", + g_BlockSizes[1], BUFFER_BLOCK_PAD)); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for target.... \n")); + + /* the target lets us know it is ready by giving us 1 credit on + * mailbox 0 */ + status = GetCredits(pDev, 0, &credits); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait for target ready \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Target is ready ...\n")); + + /* read the first 4 scratch registers */ + status = HIFReadWrite(pDev->HIFDevice, + SCRATCH_ADDRESS, + params, + 4, + HIF_RD_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait get parameters \n")); + break; + } + + numBufs = params[0]; + bufferSize = (int)(((A_UINT16)params[2] << 8) | (A_UINT16)params[1]); + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, + ("Target parameters: bufs per mailbox:%d, buffer size:%d bytes (total space: %d, minimum required space (w/padding): %d) \n", + numBufs, bufferSize, (numBufs * bufferSize), TOTAL_BYTES)); + + if ((numBufs * bufferSize) < TOTAL_BYTES) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Not Enough buffer space to run test! need:%d, got:%d \n", + TOTAL_BYTES, (numBufs*bufferSize))); + status = A_ERROR; + break; + } + + temp = GetEndMarker(); + + status = HIFReadWrite(pDev->HIFDevice, + SCRATCH_ADDRESS + 4, + (A_UINT8 *)&temp, + 2, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write end marker \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("End Marker: 0x%X \n",temp)); + + temp = (A_UINT16)g_BlockSizes[1]; + /* convert to a mask */ + temp = temp - 1; + status = HIFReadWrite(pDev->HIFDevice, + SCRATCH_ADDRESS + 6, + (A_UINT8 *)&temp, + 2, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write block mask \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Set Block Mask: 0x%X \n",temp)); + + /* execute the test on each mailbox */ + for (i = 0; i < AR6K_MAILBOXES; i++) { + status = DoOneMboxHWTest(pDev, i); + if (status != A_OK) { + break; + } + } + + } while (FALSE); + + if (status == A_OK) { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - SUCCESS! - \n")); + } else { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - FAILED! - \n")); + } + /* don't let HTC_Start continue, the target is actually not running any HTC code */ + return A_ERROR; +} +#endif + + + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/ar6k.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6k.h --- linux-2.6.26/drivers/net/wireless/ath6k22/ar6k.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6k.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,206 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// AR6K device layer that handles register level I/O +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef AR6K_H_ +#define AR6K_H_ + +#define AR6K_MAILBOXES 4 + +/* HTC runs over mailbox 0 */ +#define HTC_MAILBOX 0 + +#define AR6K_TARGET_DEBUG_INTR_MASK 0x01 + +#define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK | \ + INT_STATUS_ENABLE_CPU_MASK | \ + INT_STATUS_ENABLE_COUNTER_MASK) + +//#define MBOXHW_UNIT_TEST 1 + +#include "athstartpack.h" +typedef PREPACK struct _AR6K_IRQ_PROC_REGISTERS { + A_UINT8 host_int_status; + A_UINT8 cpu_int_status; + A_UINT8 error_int_status; + A_UINT8 counter_int_status; + A_UINT8 mbox_frame; + A_UINT8 rx_lookahead_valid; + A_UINT8 hole[2]; + A_UINT32 rx_lookahead[2]; +} POSTPACK AR6K_IRQ_PROC_REGISTERS; + +#define AR6K_IRQ_PROC_REGS_SIZE sizeof(AR6K_IRQ_PROC_REGISTERS) + + + +typedef PREPACK struct _AR6K_IRQ_ENABLE_REGISTERS { + A_UINT8 int_status_enable; + A_UINT8 cpu_int_status_enable; + A_UINT8 error_status_enable; + A_UINT8 counter_int_status_enable; +} POSTPACK AR6K_IRQ_ENABLE_REGISTERS; + +#include "athendpack.h" + +#define AR6K_IRQ_ENABLE_REGS_SIZE sizeof(AR6K_IRQ_ENABLE_REGISTERS) + +#define AR6K_REG_IO_BUFFER_SIZE 32 +#define AR6K_MAX_REG_IO_BUFFERS 8 + +/* buffers for ASYNC I/O */ +typedef struct _AR6K_ASYNC_REG_IO_BUFFER { + HTC_PACKET HtcPacket; /* we use an HTC packet as a wrapper for our async register-based I/O */ + A_UINT8 Buffer[AR6K_REG_IO_BUFFER_SIZE]; +} AR6K_ASYNC_REG_IO_BUFFER; + +typedef enum _AR6K_TARGET_FAILURE_TYPE { + AR6K_TARGET_ASSERT = 1, + AR6K_TARGET_RX_ERROR, + AR6K_TARGET_TX_ERROR +} AR6K_TARGET_FAILURE_TYPE; + +typedef struct _AR6K_DEVICE { + A_MUTEX_T Lock; + AR6K_IRQ_PROC_REGISTERS IrqProcRegisters; + AR6K_IRQ_ENABLE_REGISTERS IrqEnableRegisters; + void *HIFDevice; + A_UINT32 BlockSize; + A_UINT32 BlockMask; + A_UINT32 MailboxAddress; + HIF_PENDING_EVENTS_FUNC GetPendingEventsFunc; + void *HTCContext; + HTC_PACKET_QUEUE RegisterIOList; + AR6K_ASYNC_REG_IO_BUFFER RegIOBuffers[AR6K_MAX_REG_IO_BUFFERS]; + void (*TargetFailureCallback)(void *Context, AR6K_TARGET_FAILURE_TYPE Type); + A_STATUS (*MessagePendingCallback)(void *Context, A_UINT32 *LookAhead, A_BOOL *pAsyncProc); + HIF_DEVICE_IRQ_PROCESSING_MODE HifIRQProcessingMode; + HIF_MASK_UNMASK_RECV_EVENT HifMaskUmaskRecvEvent; + A_BOOL HifAttached; +} AR6K_DEVICE; + +#define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) ((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY) + +A_STATUS DevSetup(AR6K_DEVICE *pDev); +void DevCleanup(AR6K_DEVICE *pDev); +A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev, + A_UINT32 *pLookAhead, + int TimeoutMS); +A_STATUS DevRWCompletionHandler(void *context, A_STATUS status); +A_STATUS DevDsrHandler(void *context); +A_STATUS DevCheckPendingRecvMsgsAsync(void *context); +void DevDumpRegisters(AR6K_IRQ_PROC_REGISTERS *pIrqProcRegs, + AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs); + +#define DEV_STOP_RECV_ASYNC TRUE +#define DEV_STOP_RECV_SYNC FALSE +#define DEV_ENABLE_RECV_ASYNC TRUE +#define DEV_ENABLE_RECV_SYNC FALSE +A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode); +A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode); +A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev); + +static INLINE A_STATUS DevSendPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 SendLength) { + A_UINT32 paddedLength; + A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE; + A_STATUS status; + + /* adjust the length to be a multiple of block size if appropriate */ + paddedLength = (SendLength + (pDev->BlockMask)) & + (~(pDev->BlockMask)); +#if 0 // BufferLength may not be set in , fix this... + if (paddedLength > pPacket->BufferLength) { + AR_DEBUG_ASSERT(FALSE); + if (pPacket->Completion != NULL) { + COMPLETE_HTC_PACKET(pPacket,A_EINVAL); + } + return A_EINVAL; + } +#endif + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("DevSendPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n", + paddedLength, + pDev->MailboxAddress, + sync ? "SYNC" : "ASYNC")); + + status = HIFReadWrite(pDev->HIFDevice, + pDev->MailboxAddress, + pPacket->pBuffer, + paddedLength, /* the padded length */ + sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC, + sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */ + + if (sync) { + pPacket->Status = status; + } + + return status; +} + +static INLINE A_STATUS DevRecvPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 RecvLength) { + A_UINT32 paddedLength; + A_STATUS status; + A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE; + + /* adjust the length to be a multiple of block size if appropriate */ + paddedLength = (RecvLength + (pDev->BlockMask)) & + (~(pDev->BlockMask)); + if (paddedLength > pPacket->BufferLength) { + AR_DEBUG_ASSERT(FALSE); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("DevRecvPacket, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n", + paddedLength,RecvLength,pPacket->BufferLength)); + if (pPacket->Completion != NULL) { + COMPLETE_HTC_PACKET(pPacket,A_EINVAL); + } + return A_EINVAL; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("DevRecvPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n", + paddedLength, + pDev->MailboxAddress, + sync ? "SYNC" : "ASYNC")); + + status = HIFReadWrite(pDev->HIFDevice, + pDev->MailboxAddress, + pPacket->pBuffer, + paddedLength, + sync ? HIF_RD_SYNC_BLOCK_INC : HIF_RD_ASYNC_BLOCK_INC, + sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */ + + if (sync) { + pPacket->Status = status; + } + + return status; +} + +#ifdef MBOXHW_UNIT_TEST +A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev); +#endif + +#endif /*AR6K_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/ar6k_events.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6k_events.c --- linux-2.6.26/drivers/net/wireless/ath6k22/ar6k_events.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6k_events.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,665 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// AR6K Driver layer event handling (i.e. interrupts, message polling) +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" + +#include "mbox_host_reg.h" +#include "rtc_reg.h" + +#include "a_osapi.h" +#include "a_debug.h" +#include "hif.h" +#include "htc_packet.h" +#include "ar6k.h" + + +extern void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket); +extern HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev); + +static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev); + +#define DELAY_PER_INTERVAL_MS 10 /* 10 MS delay per polling interval */ + +/* completion routine for ALL HIF layer async I/O */ +A_STATUS DevRWCompletionHandler(void *context, A_STATUS status) +{ + HTC_PACKET *pPacket = (HTC_PACKET *)context; + + COMPLETE_HTC_PACKET(pPacket,status); + + return A_OK; +} + +/* mailbox recv message polling */ +A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev, + A_UINT32 *pLookAhead, + int TimeoutMS) +{ + A_STATUS status = A_OK; + int timeout = TimeoutMS/DELAY_PER_INTERVAL_MS; + + AR_DEBUG_ASSERT(timeout > 0); + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevPollMboxMsgRecv \n")); + + while (TRUE) { + + if (pDev->GetPendingEventsFunc != NULL) + { + + HIF_PENDING_EVENTS_INFO events; + + /* the HIF layer uses a special mechanism to get events, do this + * synchronously */ + status = pDev->GetPendingEventsFunc(pDev->HIFDevice, + &events, + NULL); + if (A_FAILED(status)) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get pending events \n")); + break; + } + + if (events.Events & HIF_RECV_MSG_AVAIL) + { + /* there is a message available, the lookahead should be valid now */ + *pLookAhead = events.LookAhead; + + break; + } + } + else + { + + /* this is the standard HIF way.... */ + /* load the register table */ + status = HIFReadWrite(pDev->HIFDevice, + HOST_INT_STATUS_ADDRESS, + (A_UINT8 *)&pDev->IrqProcRegisters, + AR6K_IRQ_PROC_REGS_SIZE, + HIF_RD_SYNC_BYTE_INC, + NULL); + + if (A_FAILED(status)) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to read register table \n")); + break; + } + + /* check for MBOX data and valid lookahead */ + if (pDev->IrqProcRegisters.host_int_status & (1 << HTC_MAILBOX)) + { + if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) + { + /* mailbox has a message and the look ahead is valid */ + *pLookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX]; + break; + } + } + + } + + timeout--; + + if (timeout <= 0) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Timeout waiting for recv message \n")); + status = A_ERROR; + + /* check if the target asserted */ + if ( pDev->IrqProcRegisters.counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) { + /* target signaled an assert, process this pending interrupt + * this will call the target failure handler */ + DevServiceDebugInterrupt(pDev); + } + + break; + } + + /* delay a little */ + A_MDELAY(DELAY_PER_INTERVAL_MS); + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Retry Mbox Poll : %d \n",timeout)); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevPollMboxMsgRecv \n")); + + return status; +} + +static A_STATUS DevServiceCPUInterrupt(AR6K_DEVICE *pDev) +{ + A_STATUS status; + A_UINT8 cpu_int_status; + A_UINT8 regBuffer[4]; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("CPU Interrupt\n")); + cpu_int_status = pDev->IrqProcRegisters.cpu_int_status & + pDev->IrqEnableRegisters.cpu_int_status_enable; + AR_DEBUG_ASSERT(cpu_int_status); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + ("Valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n", + cpu_int_status)); + + /* Clear the interrupt */ + pDev->IrqProcRegisters.cpu_int_status &= ~cpu_int_status; /* W1C */ + + /* set up the register transfer buffer to hit the register 4 times , this is done + * to make the access 4-byte aligned to mitigate issues with host bus interconnects that + * restrict bus transfer lengths to be a multiple of 4-bytes */ + + /* set W1C value to clear the interrupt, this hits the register first */ + regBuffer[0] = cpu_int_status; + /* the remaining 4 values are set to zero which have no-effect */ + regBuffer[1] = 0; + regBuffer[2] = 0; + regBuffer[3] = 0; + + status = HIFReadWrite(pDev->HIFDevice, + CPU_INT_STATUS_ADDRESS, + regBuffer, + 4, + HIF_WR_SYNC_BYTE_FIX, + NULL); + + AR_DEBUG_ASSERT(status == A_OK); + return status; +} + + +static A_STATUS DevServiceErrorInterrupt(AR6K_DEVICE *pDev) +{ + A_STATUS status; + A_UINT8 error_int_status; + A_UINT8 regBuffer[4]; + + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error Interrupt\n")); + error_int_status = pDev->IrqProcRegisters.error_int_status & 0x0F; + AR_DEBUG_ASSERT(error_int_status); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n", + error_int_status)); + + if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) { + /* Wakeup */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error : Wakeup\n")); + } + + if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) { + /* Rx Underflow */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Rx Underflow\n")); + if (pDev->TargetFailureCallback != NULL) { + pDev->TargetFailureCallback(pDev->HTCContext, AR6K_TARGET_RX_ERROR); + } + } + + if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) { + /* Tx Overflow */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Tx Overflow\n")); + if (pDev->TargetFailureCallback != NULL) { + pDev->TargetFailureCallback(pDev->HTCContext, AR6K_TARGET_TX_ERROR); + } + } + + /* Clear the interrupt */ + pDev->IrqProcRegisters.error_int_status &= ~error_int_status; /* W1C */ + + /* set up the register transfer buffer to hit the register 4 times , this is done + * to make the access 4-byte aligned to mitigate issues with host bus interconnects that + * restrict bus transfer lengths to be a multiple of 4-bytes */ + + /* set W1C value to clear the interrupt, this hits the register first */ + regBuffer[0] = error_int_status; + /* the remaining 4 values are set to zero which have no-effect */ + regBuffer[1] = 0; + regBuffer[2] = 0; + regBuffer[3] = 0; + + status = HIFReadWrite(pDev->HIFDevice, + ERROR_INT_STATUS_ADDRESS, + regBuffer, + 4, + HIF_WR_SYNC_BYTE_FIX, + NULL); + + AR_DEBUG_ASSERT(status == A_OK); + return status; +} + +static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev) +{ + A_UINT32 dummy; + A_STATUS status; + + /* Send a target failure event to the application */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Target debug interrupt\n")); + + if (pDev->TargetFailureCallback != NULL) { + pDev->TargetFailureCallback(pDev->HTCContext, AR6K_TARGET_ASSERT); + } + + /* clear the interrupt , the debug error interrupt is + * counter 0 */ + /* read counter to clear interrupt */ + status = HIFReadWrite(pDev->HIFDevice, + COUNT_DEC_ADDRESS, + (A_UINT8 *)&dummy, + 4, + HIF_RD_SYNC_BYTE_INC, + NULL); + + AR_DEBUG_ASSERT(status == A_OK); + return status; +} + +static A_STATUS DevServiceCounterInterrupt(AR6K_DEVICE *pDev) +{ + A_UINT8 counter_int_status; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Counter Interrupt\n")); + + counter_int_status = pDev->IrqProcRegisters.counter_int_status & + pDev->IrqEnableRegisters.counter_int_status_enable; + + AR_DEBUG_ASSERT(counter_int_status); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + ("Valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n", + counter_int_status)); + + /* Check if the debug interrupt is pending */ + if (counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) { + return DevServiceDebugInterrupt(pDev); + } + + return A_OK; +} + +/* callback when our fetch to get interrupt status registers completes */ +static void DevGetEventAsyncHandler(void *Context, HTC_PACKET *pPacket) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context; + A_UINT32 lookAhead = 0; + A_BOOL otherInts = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGetEventAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); + + do { + + if (A_FAILED(pPacket->Status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" GetEvents I/O request failed, status:%d \n", pPacket->Status)); + /* bail out, don't unmask HIF interrupt */ + break; + } + + if (pDev->GetPendingEventsFunc != NULL) { + /* the HIF layer collected the information for us */ + HIF_PENDING_EVENTS_INFO *pEvents = (HIF_PENDING_EVENTS_INFO *)pPacket->pBuffer; + if (pEvents->Events & HIF_RECV_MSG_AVAIL) { + lookAhead = pEvents->LookAhead; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler1, lookAhead is zero! \n")); + } + } + if (pEvents->Events & HIF_OTHER_EVENTS) { + otherInts = TRUE; + } + } else { + /* standard interrupt table handling.... */ + AR6K_IRQ_PROC_REGISTERS *pReg = (AR6K_IRQ_PROC_REGISTERS *)pPacket->pBuffer; + A_UINT8 host_int_status; + + host_int_status = pReg->host_int_status & pDev->IrqEnableRegisters.int_status_enable; + + if (host_int_status & (1 << HTC_MAILBOX)) { + host_int_status &= ~(1 << HTC_MAILBOX); + if (pReg->rx_lookahead_valid & (1 << HTC_MAILBOX)) { + /* mailbox has a message and the look ahead is valid */ + lookAhead = pReg->rx_lookahead[HTC_MAILBOX]; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler2, lookAhead is zero! \n")); + } + } + } + + if (host_int_status) { + /* there are other interrupts to handle */ + otherInts = TRUE; + } + } + + if (otherInts || (lookAhead == 0)) { + /* if there are other interrupts to process, we cannot do this in the async handler so + * ack the interrupt which will cause our sync handler to run again + * if however there are no more messages, we can now ack the interrupt */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + (" Acking interrupt from DevGetEventAsyncHandler (otherints:%d, lookahead:0x%X)\n", + otherInts, lookAhead)); + HIFAckInterrupt(pDev->HIFDevice); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + (" DevGetEventAsyncHandler : detected another message, lookahead :0x%X \n", + lookAhead)); + /* lookahead is non-zero and there are no other interrupts to service, + * go get the next message */ + pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, NULL); + } + + } while (FALSE); + + /* free this IO packet */ + AR6KFreeIOPacket(pDev,pPacket); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGetEventAsyncHandler \n")); +} + +/* called by the HTC layer when it wants us to check if the device has any more pending + * recv messages, this starts off a series of async requests to read interrupt registers */ +A_STATUS DevCheckPendingRecvMsgsAsync(void *context) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)context; + A_STATUS status = A_OK; + HTC_PACKET *pIOPacket; + + /* this is called in an ASYNC only context, we may NOT block, sleep or call any apis that can + * cause us to switch contexts */ + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevCheckPendingRecvMsgsAsync: (dev: 0x%X)\n", (A_UINT32)pDev)); + + do { + + if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) { + /* break the async processing chain right here, no need to continue. + * The DevDsrHandler() will handle things in a loop when things are driven + * synchronously */ + break; + } + /* first allocate one of our HTC packets we created for async I/O + * we reuse HTC packet definitions so that we can use the completion mechanism + * in DevRWCompletionHandler() */ + pIOPacket = AR6KAllocIOPacket(pDev); + + if (NULL == pIOPacket) { + /* there should be only 1 asynchronous request out at a time to read these registers + * so this should actually never happen */ + status = A_NO_MEMORY; + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* stick in our completion routine when the I/O operation completes */ + pIOPacket->Completion = DevGetEventAsyncHandler; + pIOPacket->pContext = pDev; + + if (pDev->GetPendingEventsFunc) { + /* HIF layer has it's own mechanism, pass the IO to it.. */ + status = pDev->GetPendingEventsFunc(pDev->HIFDevice, + (HIF_PENDING_EVENTS_INFO *)pIOPacket->pBuffer, + pIOPacket); + + } else { + /* standard way, read the interrupt register table asynchronously again */ + status = HIFReadWrite(pDev->HIFDevice, + HOST_INT_STATUS_ADDRESS, + pIOPacket->pBuffer, + AR6K_IRQ_PROC_REGS_SIZE, + HIF_RD_ASYNC_BYTE_INC, + pIOPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Async IO issued to get interrupt status...\n")); + } while (FALSE); + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevCheckPendingRecvMsgsAsync \n")); + + return status; +} + +/* process pending interrupts synchronously */ +static A_STATUS ProcessPendingIRQs(AR6K_DEVICE *pDev, A_BOOL *pDone, A_BOOL *pASyncProcessing) +{ + A_STATUS status = A_OK; + A_UINT8 host_int_status = 0; + A_UINT32 lookAhead = 0; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+ProcessPendingIRQs: (dev: 0x%X)\n", (A_UINT32)pDev)); + + /*** NOTE: the HIF implementation guarantees that the context of this call allows + * us to perform SYNCHRONOUS I/O, that is we can block, sleep or call any API that + * can block or switch thread/task ontexts. + * This is a fully schedulable context. + * */ + do { + + if (pDev->IrqEnableRegisters.int_status_enable == 0) { + /* interrupt enables have been cleared, do not try to process any pending interrupts that + * may result in more bus transactions. The target may be unresponsive at this + * point. */ + break; + } + + if (pDev->GetPendingEventsFunc != NULL) { + HIF_PENDING_EVENTS_INFO events; + + /* the HIF layer uses a special mechanism to get events + * get this synchronously */ + status = pDev->GetPendingEventsFunc(pDev->HIFDevice, + &events, + NULL); + + if (A_FAILED(status)) { + break; + } + + if (events.Events & HIF_RECV_MSG_AVAIL) { + lookAhead = events.LookAhead; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs1 lookAhead is zero! \n")); + } + } + + if (!(events.Events & HIF_OTHER_EVENTS) || + !(pDev->IrqEnableRegisters.int_status_enable & OTHER_INTS_ENABLED)) { + /* no need to read the register table, no other interesting interrupts. + * Some interfaces (like SPI) can shadow interrupt sources without + * requiring the host to do a full table read */ + break; + } + + /* otherwise fall through and read the register table */ + } + + /* + * Read the first 28 bytes of the HTC register table. This will yield us + * the value of different int status registers and the lookahead + * registers. + * length = sizeof(int_status) + sizeof(cpu_int_status) + + * sizeof(error_int_status) + sizeof(counter_int_status) + + * sizeof(mbox_frame) + sizeof(rx_lookahead_valid) + + * sizeof(hole) + sizeof(rx_lookahead) + + * sizeof(int_status_enable) + sizeof(cpu_int_status_enable) + + * sizeof(error_status_enable) + + * sizeof(counter_int_status_enable); + * + */ + status = HIFReadWrite(pDev->HIFDevice, + HOST_INT_STATUS_ADDRESS, + (A_UINT8 *)&pDev->IrqProcRegisters, + AR6K_IRQ_PROC_REGS_SIZE, + HIF_RD_SYNC_BYTE_INC, + NULL); + + if (A_FAILED(status)) { + break; + } + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_IRQ)) { + DevDumpRegisters(&pDev->IrqProcRegisters, + &pDev->IrqEnableRegisters); + } + + /* Update only those registers that are enabled */ + host_int_status = pDev->IrqProcRegisters.host_int_status & + pDev->IrqEnableRegisters.int_status_enable; + + if (NULL == pDev->GetPendingEventsFunc) { + /* only look at mailbox status if the HIF layer did not provide this function, + * on some HIF interfaces reading the RX lookahead is not valid to do */ + if (host_int_status & (1 << HTC_MAILBOX)) { + /* mask out pending mailbox value, we use "lookAhead" as the real flag for + * mailbox processing below */ + host_int_status &= ~(1 << HTC_MAILBOX); + if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) { + /* mailbox has a message and the look ahead is valid */ + lookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX]; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs2, lookAhead is zero! \n")); + } + } + } + } else { + /* not valid to check if the HIF has another mechanism for reading mailbox pending status*/ + host_int_status &= ~(1 << HTC_MAILBOX); + } + + } while (FALSE); + + + do { + + /* did the interrupt status fetches succeed? */ + if (A_FAILED(status)) { + break; + } + + if ((0 == host_int_status) && (0 == lookAhead)) { + /* nothing to process, the caller can use this to break out of a loop */ + *pDone = TRUE; + break; + } + + if (lookAhead != 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Pending mailbox message, LookAhead: 0x%X\n",lookAhead)); + /* Mailbox Interrupt, the HTC layer may issue async requests to empty the + * mailbox... + * When emptying the recv mailbox we use the async handler above called from the + * completion routine of the callers read request. This can improve performance + * by reducing context switching when we rapidly pull packets */ + status = pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, pASyncProcessing); + if (A_FAILED(status)) { + break; + } + /* if sync processing of Rx packets is enabled and lookahead of last packet is 0, then + * we can avoid extra CMD53 16-byte read above by setting pDone = TRUE */ + if ((lookAhead == 0) && (*pASyncProcessing == FALSE)) { + *pDone = TRUE; + } + } + + /* now handle the rest of them */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + (" Valid interrupt source(s) for OTHER interrupts: 0x%x\n", + host_int_status)); + + if (HOST_INT_STATUS_CPU_GET(host_int_status)) { + /* CPU Interrupt */ + status = DevServiceCPUInterrupt(pDev); + if (A_FAILED(status)){ + break; + } + } + + if (HOST_INT_STATUS_ERROR_GET(host_int_status)) { + /* Error Interrupt */ + status = DevServiceErrorInterrupt(pDev); + if (A_FAILED(status)){ + break; + } + } + + if (HOST_INT_STATUS_COUNTER_GET(host_int_status)) { + /* Counter Interrupt */ + status = DevServiceCounterInterrupt(pDev); + if (A_FAILED(status)){ + break; + } + } + + } while (FALSE); + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-ProcessPendingIRQs: (done:%d, async:%d) status=%d \n", + *pDone, *pASyncProcessing, status)); + + return status; +} + + +/* Synchronousinterrupt handler, this handler kicks off all interrupt processing.*/ +A_STATUS DevDsrHandler(void *context) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)context; + A_STATUS status = A_OK; + A_BOOL done = FALSE; + A_BOOL asyncProc = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDsrHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); + + + while (!done) { + status = ProcessPendingIRQs(pDev, &done, &asyncProc); + if (A_FAILED(status)) { + break; + } + + if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) { + /* the HIF layer does not allow async IRQ processing, override the asyncProc flag */ + asyncProc = FALSE; + /* this will cause us to re-enter ProcessPendingIRQ() and re-read interrupt status registers. + * this has a nice side effect of blocking us until all async read requests are completed. + * This behavior is required on some HIF implementations that do not allow ASYNC + * processing in interrupt handlers (like Windows CE) */ + } + + if (asyncProc) { + /* the function performed some async I/O for performance, we + need to exit the ISR immediately, the check below will prevent the interrupt from being + Ack'd while we handle it asynchronously */ + break; + } + + } + + if (A_SUCCESS(status) && !asyncProc) { + /* Ack the interrupt only if : + * 1. we did not get any errors in processing interrupts + * 2. there are no outstanding async processing requests */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Acking interrupt from DevDsrHandler \n")); + HIFAckInterrupt(pDev->HIFDevice); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDsrHandler \n")); + return status; +} + + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/ar6kap_common.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6kap_common.h --- linux-2.6.26/drivers/net/wireless/ath6k22/ar6kap_common.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6kap_common.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,40 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions of common AP mode data structures. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _AR6KAP_COMMON_H_ +#define _AR6KAP_COMMON_H_ + +/* + * Used with AR6000_XIOCTL_AP_GET_STA_LIST + */ +typedef struct { + A_UINT8 mac[ATH_MAC_LEN]; + A_UINT8 aid; +} station_t; + +typedef struct { + station_t sta[AP_MAX_NUM_STA]; +} ap_get_sta_t; + +#endif /* _AR6KAP_COMMON_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/ar6xapi_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6xapi_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k22/ar6xapi_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ar6xapi_linux.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,159 @@ +#ifndef _AR6XAPI_LINUX_H +#define _AR6XAPI_LINUX_H +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifdef __cplusplus +extern "C" { +#endif + +struct ar6_softc; + +void ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap, + A_UINT32 ver); +A_STATUS ar6000_control_tx(void *devt, void *osbuf, HTC_ENDPOINT_ID eid); +void ar6000_connect_event(struct ar6_softc *ar, A_UINT16 channel, + A_UINT8 *bssid, A_UINT16 listenInterval, + A_UINT16 beaconInterval, NETWORK_TYPE networkType, + A_UINT8 beaconIeLen, A_UINT8 assocReqLen, + A_UINT8 assocRespLen,A_UINT8 *assocInfo); +void ar6000_disconnect_event(struct ar6_softc *ar, A_UINT8 reason, + A_UINT8 *bssid, A_UINT8 assocRespLen, + A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus); +void ar6000_tkip_micerr_event(struct ar6_softc *ar, A_UINT8 keyid, + A_BOOL ismcast); +void ar6000_bitrate_rx(void *devt, A_INT32 rateKbps); +void ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList); +void ar6000_regDomain_event(struct ar6_softc *ar, A_UINT32 regCode); +void ar6000_txPwr_rx(void *devt, A_UINT8 txPwr); +void ar6000_keepalive_rx(void *devt, A_UINT8 configured); +void ar6000_neighborReport_event(struct ar6_softc *ar, int numAps, + WMI_NEIGHBOR_INFO *info); +void ar6000_set_numdataendpts(struct ar6_softc *ar, A_UINT32 num); +void ar6000_scanComplete_event(struct ar6_softc *ar, A_STATUS status); +void ar6000_targetStats_event(struct ar6_softc *ar, WMI_TARGET_STATS *pStats); +void ar6000_rssiThreshold_event(struct ar6_softc *ar, + WMI_RSSI_THRESHOLD_VAL newThreshold, + A_INT16 rssi); +void ar6000_reportError_event(struct ar6_softc *, WMI_TARGET_ERROR_VAL errorVal); +void ar6000_cac_event(struct ar6_softc *ar, A_UINT8 ac, A_UINT8 cac_indication, + A_UINT8 statusCode, A_UINT8 *tspecSuggestion); +void ar6000_channel_change_event(struct ar6_softc *ar, A_UINT16 oldChannel, A_UINT16 newChannel); +void ar6000_hbChallengeResp_event(struct ar6_softc *, A_UINT32 cookie, A_UINT32 source); +void +ar6000_roam_tbl_event(struct ar6_softc *ar, WMI_TARGET_ROAM_TBL *pTbl); + +void +ar6000_roam_data_event(struct ar6_softc *ar, WMI_TARGET_ROAM_DATA *p); + +void +ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters, + WMI_GET_WOW_LIST_REPLY *wow_reply); + +void ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID, + WMI_PMKID *pmkidList, A_UINT8 *bssidList); + +void ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values); +void ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value); +void ar6000_gpio_ack_rx(void); + +void ar6000_dbglog_init_done(struct ar6_softc *ar); + +#ifdef SEND_EVENT_TO_APP +void ar6000_send_event_to_app(struct ar6_softc *ar, A_UINT16 eventId, A_UINT8 *datap, int len); +void ar6000_send_generic_event_to_app(struct ar6_softc *ar, A_UINT16 eventId, A_UINT8 *datap, int len); +#endif + +#ifdef CONFIG_HOST_TCMD_SUPPORT +void ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len); +#endif + +void ar6000_tx_retry_err_event(void *devt); + +void ar6000_snrThresholdEvent_rx(void *devt, + WMI_SNR_THRESHOLD_VAL newThreshold, + A_UINT8 snr); + +void ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL range, A_UINT8 lqVal); + + +void ar6000_ratemask_rx(void *devt, A_UINT16 ratemask); + +A_STATUS ar6000_get_driver_cfg(struct net_device *dev, + A_UINT16 cfgParam, + void *result); +void ar6000_bssInfo_event_rx(struct ar6_softc *ar, A_UINT8 *data, int len); + +void ar6000_dbglog_event(struct ar6_softc *ar, A_UINT32 dropped, + A_INT8 *buffer, A_UINT32 length); + +int ar6000_dbglog_get_debug_logs(struct ar6_softc *ar); + +void ar6000_peer_event(void *devt, A_UINT8 eventCode, A_UINT8 *bssid); + +void ar6000_indicate_tx_activity(void *devt, A_UINT8 trafficClass, A_BOOL Active); +HTC_ENDPOINT_ID ar6000_ac2_endpoint_id ( void * devt, A_UINT8 ac); +A_UINT8 ar6000_endpoint_id2_ac (void * devt, HTC_ENDPOINT_ID ep ); + +void ar6000_dset_open_req(void *devt, + A_UINT32 id, + A_UINT32 targ_handle, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); +void ar6000_dset_close(void *devt, A_UINT32 access_cookie); +void ar6000_dset_data_req(void *devt, + A_UINT32 access_cookie, + A_UINT32 offset, + A_UINT32 length, + A_UINT32 targ_buf, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); + + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +void prof_count_rx(unsigned int addr, unsigned int count); +#endif + +A_UINT32 ar6000_getnodeAge (void); + +A_UINT32 ar6000_getclkfreq (void); + +int ar6000_ap_mode_profile_commit(struct ar6_softc *ar); + +struct ieee80211req_wpaie; +A_STATUS +ar6000_ap_mode_get_wpa_ie(struct ar6_softc *ar, struct ieee80211req_wpaie *wpaie); + +A_STATUS is_iwioctl_allowed(A_UINT8 mode, A_UINT16 cmd); + +A_STATUS is_xioctl_allowed(A_UINT8 mode, int cmd); + +void ar6000_pspoll_event(struct ar6_softc *ar,A_UINT8 aid); + +void ar6000_dtimexpiry_event(struct ar6_softc *ar); + +#ifdef __cplusplus +} +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/athbtfilter.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/athbtfilter.h --- linux-2.6.26/drivers/net/wireless/ath6k22/athbtfilter.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/athbtfilter.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,131 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Public Bluetooth filter APIs +// Author(s): ="Atheros" +//============================================================================== +#ifndef ATHBTFILTER_H_ +#define ATHBTFILTER_H_ + + +typedef enum _ATHBT_HCI_CTRL_TYPE { + ATHBT_HCI_COMMAND = 0, + ATHBT_HCI_EVENT = 1, +} ATHBT_HCI_CTRL_TYPE; + +typedef enum _ATHBT_STATE_INDICATION { + ATH_BT_NOOP = 0, + ATH_BT_INQUIRY = 1, + ATH_BT_CONNECT = 2, + ATH_BT_SCO = 3, + ATH_BT_ACL = 4, + ATH_BT_A2DP = 5, + ATH_BT_ESCO = 6, + /* new states go here.. */ + + ATH_BT_MAX_STATE_INDICATION +} ATHBT_STATE_INDICATION; + + /* filter function for OUTGOING commands and INCOMMING events */ +typedef void (*ATHBT_FILTER_CMD_EVENTS_FN)(void *pContext, ATHBT_HCI_CTRL_TYPE Type, unsigned char *pBuffer, int Length); + + /* filter function for OUTGOING data HCI packets */ +typedef void (*ATHBT_FILTER_DATA_FN)(void *pContext, unsigned char *pBuffer, int Length); + +typedef enum _ATHBT_STATE { + STATE_OFF = 0, + STATE_ON = 1, + STATE_MAX +} ATHBT_STATE; + + /* BT state indication (when filter functions are not used) */ + +typedef void (*ATHBT_INDICATE_STATE_FN)(void *pContext, ATHBT_STATE_INDICATION Indication, ATHBT_STATE State, unsigned char LMPVersion); + +typedef struct _ATHBT_FILTER_INSTANCE { +#ifdef UNDER_CE + WCHAR *pWlanAdapterName; /* filled in by user */ +#endif + int FilterEnabled; /* filtering is enabled */ + int Attached; /* filter library is attached */ + void *pContext; /* private context for filter library */ + ATHBT_FILTER_CMD_EVENTS_FN pFilterCmdEvents; /* function ptr to filter a command or event */ + ATHBT_FILTER_DATA_FN pFilterAclDataOut; /* function ptr to filter ACL data out (to radio) */ + ATHBT_FILTER_DATA_FN pFilterAclDataIn; /* function ptr to filter ACL data in (from radio) */ + ATHBT_INDICATE_STATE_FN pIndicateState; /* function ptr to indicate a state */ +} ATH_BT_FILTER_INSTANCE; + + +/* API MACROS */ + +#define AthBtFilterHciCommand(instance,packet,length) \ + if ((instance)->FilterEnabled) { \ + (instance)->pFilterCmdEvents((instance)->pContext, \ + ATHBT_HCI_COMMAND, \ + (unsigned char *)(packet), \ + (length)); \ + } + +#define AthBtFilterHciEvent(instance,packet,length) \ + if ((instance)->FilterEnabled) { \ + (instance)->pFilterCmdEvents((instance)->pContext, \ + ATHBT_HCI_EVENT, \ + (unsigned char *)(packet), \ + (length)); \ + } + +#define AthBtFilterHciAclDataOut(instance,packet,length) \ + if ((instance)->FilterEnabled) { \ + (instance)->pFilterAclDataOut((instance)->pContext, \ + (unsigned char *)(packet), \ + (length)); \ + } + +#define AthBtFilterHciAclDataIn(instance,packet,length) \ + if ((instance)->FilterEnabled) { \ + (instance)->pFilterAclDataIn((instance)->pContext, \ + (unsigned char *)(packet), \ + (length)); \ + } + +/* if filtering is not desired, the application can indicate the state directly using this + * macro: + */ +#define AthBtIndicateState(instance,indication,state) \ + if ((instance)->FilterEnabled) { \ + (instance)->pIndicateState((instance)->pContext, \ + (indication), \ + (state), \ + 0); \ + } + +#ifdef __cplusplus +extern "C" { +#endif + +/* API prototypes */ +int AthBtFilter_Attach(ATH_BT_FILTER_INSTANCE *pInstance); +void AthBtFilter_Detach(ATH_BT_FILTER_INSTANCE *pInstance); + +#ifdef __cplusplus +} +#endif + +#endif /*ATHBTFILTER_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/athdefs.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/athdefs.h --- linux-2.6.26/drivers/net/wireless/ath6k22/athdefs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/athdefs.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,84 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef __ATHDEFS_H__ +#define __ATHDEFS_H__ + +/* + * This file contains definitions that may be used across both + * Host and Target software. Nothing here is module-dependent + * or platform-dependent. + */ + +/* + * Generic error codes that can be used by hw, sta, ap, sim, dk + * and any other environments. Since these are enums, feel free to + * add any more codes that you need. + */ + +typedef enum { + A_ERROR = -1, /* Generic error return */ + A_OK = 0, /* success */ + /* Following values start at 1 */ + A_DEVICE_NOT_FOUND, /* not able to find PCI device */ + A_NO_MEMORY, /* not able to allocate memory, not available */ + A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */ + A_NO_FREE_DESC, /* no free descriptors available */ + A_BAD_ADDRESS, /* address does not match descriptor */ + A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */ + A_REGS_NOT_MAPPED, /* registers not correctly mapped */ + A_EPERM, /* Not superuser */ + A_EACCES, /* Access denied */ + A_ENOENT, /* No such entry, search failed, etc. */ + A_EEXIST, /* The object already exists (can't create) */ + A_EFAULT, /* Bad address fault */ + A_EBUSY, /* Object is busy */ + A_EINVAL, /* Invalid parameter */ + A_EMSGSIZE, /* Inappropriate message buffer length */ + A_ECANCELED, /* Operation canceled */ + A_ENOTSUP, /* Operation not supported */ + A_ECOMM, /* Communication error on send */ + A_EPROTO, /* Protocol error */ + A_ENODEV, /* No such device */ + A_EDEVNOTUP, /* device is not UP */ + A_NO_RESOURCE, /* No resources for requested operation */ + A_HARDWARE, /* Hardware failure */ + A_PENDING, /* Asynchronous routine; will send up results la +ter (typically in callback) */ + A_EBADCHANNEL, /* The channel cannot be used */ + A_DECRYPT_ERROR, /* Decryption error */ + A_PHY_ERROR, /* RX PHY error */ + A_CONSUMED /* Object was consumed */ +} A_STATUS; + +#define A_SUCCESS(x) (x == A_OK) +#define A_FAILED(x) (!A_SUCCESS(x)) + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#endif /* __ATHDEFS_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/athdrv.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/athdrv.h --- linux-2.6.26/drivers/net/wireless/ath6k22/athdrv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/athdrv.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,35 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _ATHDRV_H_ +#define _ATHDRV_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* _ATHDRV_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/athdrv_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/athdrv_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k22/athdrv_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/athdrv_linux.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,1091 @@ +/* + * Copyright (c) 2004-2006 Atheros Communications Inc. + * All rights reserved. + * + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _ATHDRV_LINUX_H +#define _ATHDRV_LINUX_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* + * There are two types of ioctl's here: Standard ioctls and + * eXtended ioctls. All extended ioctls (XIOCTL) are multiplexed + * off of the single ioctl command, AR6000_IOCTL_EXTENDED. The + * arguments for every XIOCTL starts with a 32-bit command word + * that is used to select which extended ioctl is in use. After + * the command word are command-specific arguments. + */ + +/* Linux standard Wireless Extensions, private ioctl interfaces */ +#define IEEE80211_IOCTL_SETPARAM (SIOCIWFIRSTPRIV+0) +#define IEEE80211_IOCTL_SETKEY (SIOCIWFIRSTPRIV+1) +#define IEEE80211_IOCTL_DELKEY (SIOCIWFIRSTPRIV+2) +#define IEEE80211_IOCTL_SETMLME (SIOCIWFIRSTPRIV+3) +#define IEEE80211_IOCTL_ADDPMKID (SIOCIWFIRSTPRIV+4) +#define IEEE80211_IOCTL_SETOPTIE (SIOCIWFIRSTPRIV+5) +//#define IEEE80211_IOCTL_GETPARAM (SIOCIWFIRSTPRIV+6) +//#define IEEE80211_IOCTL_SETWMMPARAMS (SIOCIWFIRSTPRIV+7) +//#define IEEE80211_IOCTL_GETWMMPARAMS (SIOCIWFIRSTPRIV+8) +//#define IEEE80211_IOCTL_GETOPTIE (SIOCIWFIRSTPRIV+9) +//#define IEEE80211_IOCTL_SETAUTHALG (SIOCIWFIRSTPRIV+10) +#define IEEE80211_IOCTL_LASTONE (SIOCIWFIRSTPRIV+10) + + + +/* ====WMI Ioctls==== */ +/* + * + * Many ioctls simply provide WMI services to application code: + * an application makes such an ioctl call with a set of arguments + * that are packaged into the corresponding WMI message, and sent + * to the Target. + */ + +#define AR6000_IOCTL_WMI_GETREV (SIOCIWFIRSTPRIV+11) +/* + * arguments: + * ar6000_version *revision + */ + +#define AR6000_IOCTL_WMI_SETPWR (SIOCIWFIRSTPRIV+12) +/* + * arguments: + * WMI_POWER_MODE_CMD pwrModeCmd (see include/wmi.h) + * uses: WMI_SET_POWER_MODE_CMDID + */ + +#define AR6000_IOCTL_WMI_SETSCAN (SIOCIWFIRSTPRIV+13) +/* + * arguments: + * WMI_SCAN_PARAMS_CMD scanParams (see include/wmi.h) + * uses: WMI_SET_SCAN_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SETLISTENINT (SIOCIWFIRSTPRIV+14) +/* + * arguments: + * UINT32 listenInterval + * uses: WMI_SET_LISTEN_INT_CMDID + */ + +#define AR6000_IOCTL_WMI_SETBSSFILTER (SIOCIWFIRSTPRIV+15) +/* + * arguments: + * WMI_BSS_FILTER filter (see include/wmi.h) + * uses: WMI_SET_BSS_FILTER_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_CHANNELPARAMS (SIOCIWFIRSTPRIV+16) +/* + * arguments: + * WMI_CHANNEL_PARAMS_CMD chParams + * uses: WMI_SET_CHANNEL_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_PROBEDSSID (SIOCIWFIRSTPRIV+17) +/* + * arguments: + * WMI_PROBED_SSID_CMD probedSsids (see include/wmi.h) + * uses: WMI_SETPROBED_SSID_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_PMPARAMS (SIOCIWFIRSTPRIV+18) +/* + * arguments: + * WMI_POWER_PARAMS_CMD powerParams (see include/wmi.h) + * uses: WMI_SET_POWER_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_BADAP (SIOCIWFIRSTPRIV+19) +/* + * arguments: + * WMI_ADD_BAD_AP_CMD badAPs (see include/wmi.h) + * uses: WMI_ADD_BAD_AP_CMDID + */ + +#define AR6000_IOCTL_WMI_GET_QOS_QUEUE (SIOCIWFIRSTPRIV+20) +/* + * arguments: + * ar6000_queuereq queueRequest (see below) + */ + +#define AR6000_IOCTL_WMI_CREATE_QOS (SIOCIWFIRSTPRIV+21) +/* + * arguments: + * WMI_CREATE_PSTREAM createPstreamCmd (see include/wmi.h) + * uses: WMI_CREATE_PSTREAM_CMDID + */ + +#define AR6000_IOCTL_WMI_DELETE_QOS (SIOCIWFIRSTPRIV+22) +/* + * arguments: + * WMI_DELETE_PSTREAM_CMD deletePstreamCmd (see include/wmi.h) + * uses: WMI_DELETE_PSTREAM_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_SNRTHRESHOLD (SIOCIWFIRSTPRIV+23) +/* + * arguments: + * WMI_SNR_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h) + * uses: WMI_SNR_THRESHOLD_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24) +/* + * arguments: + * WMI_TARGET_ERROR_REPORT_BITMASK errorReportBitMask (see include/wmi.h) + * uses: WMI_TARGET_ERROR_REPORT_BITMASK_CMDID + */ + +#define AR6000_IOCTL_WMI_GET_TARGET_STATS (SIOCIWFIRSTPRIV+25) +/* + * arguments: + * TARGET_STATS *targetStats (see below) + * uses: WMI_GET_STATISTICS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_ASSOC_INFO (SIOCIWFIRSTPRIV+26) +/* + * arguments: + * WMI_SET_ASSOC_INFO_CMD setAssocInfoCmd + * uses: WMI_SET_ASSOC_INFO_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_ACCESS_PARAMS (SIOCIWFIRSTPRIV+27) +/* + * arguments: + * WMI_SET_ACCESS_PARAMS_CMD setAccessParams (see include/wmi.h) + * uses: WMI_SET_ACCESS_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_BMISS_TIME (SIOCIWFIRSTPRIV+28) +/* + * arguments: + * UINT32 beaconMissTime + * uses: WMI_SET_BMISS_TIME_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_DISC_TIMEOUT (SIOCIWFIRSTPRIV+29) +/* + * arguments: + * WMI_DISC_TIMEOUT_CMD disconnectTimeoutCmd (see include/wmi.h) + * uses: WMI_SET_DISC_TIMEOUT_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS (SIOCIWFIRSTPRIV+30) +/* + * arguments: + * WMI_IBSS_PM_CAPS_CMD ibssPowerMgmtCapsCmd + * uses: WMI_SET_IBSS_PM_CAPS_CMDID + */ + +/* + * There is a very small space available for driver-private + * wireless ioctls. In order to circumvent this limitation, + * we multiplex a bunch of ioctls (XIOCTLs) on top of a + * single AR6000_IOCTL_EXTENDED ioctl. + */ +#define AR6000_IOCTL_EXTENDED (SIOCIWFIRSTPRIV+31) + + +/* ====BMI Extended Ioctls==== */ + +#define AR6000_XIOCTL_BMI_DONE 1 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_DONE) + * uses: BMI_DONE + */ + +#define AR6000_XIOCTL_BMI_READ_MEMORY 2 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_READ_MEMORY) + * UINT32 address + * UINT32 length + * } + * char results[length] + * } + * uses: BMI_READ_MEMORY + */ + +#define AR6000_XIOCTL_BMI_WRITE_MEMORY 3 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_MEMORY) + * UINT32 address + * UINT32 length + * char data[length] + * uses: BMI_WRITE_MEMORY + */ + +#define AR6000_XIOCTL_BMI_EXECUTE 4 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_EXECUTE) + * UINT32 TargetAddress + * UINT32 parameter + * uses: BMI_EXECUTE + */ + +#define AR6000_XIOCTL_BMI_SET_APP_START 5 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_SET_APP_START) + * UINT32 TargetAddress + * uses: BMI_SET_APP_START + */ + +#define AR6000_XIOCTL_BMI_READ_SOC_REGISTER 6 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_READ_SOC_REGISTER) + * UINT32 TargetAddress, 32-bit aligned + * } + * UINT32 result + * } + * uses: BMI_READ_SOC_REGISTER + */ + +#define AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER 7 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER) + * UINT32 TargetAddress, 32-bit aligned + * UINT32 newValue + * } + * uses: BMI_WRITE_SOC_REGISTER + */ + +#define AR6000_XIOCTL_BMI_TEST 8 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_TEST) + * UINT32 address + * UINT32 length + * UINT32 count + */ + + + +/* Historical Host-side DataSet support */ +#define AR6000_XIOCTL_UNUSED9 9 +#define AR6000_XIOCTL_UNUSED10 10 +#define AR6000_XIOCTL_UNUSED11 11 + +/* ====Misc Extended Ioctls==== */ + +#define AR6000_XIOCTL_FORCE_TARGET_RESET 12 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_FORCE_TARGET_RESET) + */ + + +#ifdef HTC_RAW_INTERFACE +/* HTC Raw Interface Ioctls */ +#define AR6000_XIOCTL_HTC_RAW_OPEN 13 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_OPEN) + */ + +#define AR6000_XIOCTL_HTC_RAW_CLOSE 14 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_CLOSE) + */ + +#define AR6000_XIOCTL_HTC_RAW_READ 15 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_READ) + * UINT32 mailboxID + * UINT32 length + * } + * results[length] + * } + */ + +#define AR6000_XIOCTL_HTC_RAW_WRITE 16 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_WRITE) + * UINT32 mailboxID + * UINT32 length + * char buffer[length] + */ +#endif /* HTC_RAW_INTERFACE */ + +#define AR6000_XIOCTL_CHECK_TARGET_READY 17 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_CHECK_TARGET_READY) + */ + + + +/* ====GPIO (General Purpose I/O) Extended Ioctls==== */ + +#define AR6000_XIOCTL_GPIO_OUTPUT_SET 18 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_OUTPUT_SET) + * ar6000_gpio_output_set_cmd_s (see below) + * uses: WMIX_GPIO_OUTPUT_SET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_INPUT_GET 19 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_INPUT_GET) + * uses: WMIX_GPIO_INPUT_GET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_REGISTER_SET 20 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_SET) + * ar6000_gpio_register_cmd_s (see below) + * uses: WMIX_GPIO_REGISTER_SET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_REGISTER_GET 21 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_GET) + * ar6000_gpio_register_cmd_s (see below) + * uses: WMIX_GPIO_REGISTER_GET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_INTR_ACK 22 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_ACK) + * ar6000_cpio_intr_ack_cmd_s (see below) + * uses: WMIX_GPIO_INTR_ACK_CMDID + */ + +#define AR6000_XIOCTL_GPIO_INTR_WAIT 23 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_WAIT) + */ + + + +/* ====more wireless commands==== */ + +#define AR6000_XIOCTL_SET_ADHOC_BSSID 24 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_ADHOC_BSSID) + * WMI_SET_ADHOC_BSSID_CMD setAdHocBssidCmd (see include/wmi.h) + */ + +#define AR6000_XIOCTL_SET_OPT_MODE 25 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_OPT_MODE) + * WMI_SET_OPT_MODE_CMD setOptModeCmd (see include/wmi.h) + * uses: WMI_SET_OPT_MODE_CMDID + */ + +#define AR6000_XIOCTL_OPT_SEND_FRAME 26 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_OPT_SEND_FRAME) + * WMI_OPT_TX_FRAME_CMD optTxFrameCmd (see include/wmi.h) + * uses: WMI_OPT_TX_FRAME_CMDID + */ + +#define AR6000_XIOCTL_SET_BEACON_INTVAL 27 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_BEACON_INTVAL) + * WMI_BEACON_INT_CMD beaconIntCmd (see include/wmi.h) + * uses: WMI_SET_BEACON_INT_CMDID + */ + + +#define IEEE80211_IOCTL_SETAUTHALG 28 + + +#define AR6000_XIOCTL_SET_VOICE_PKT_SIZE 29 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_VOICE_PKT_SIZE) + * WMI_SET_VOICE_PKT_SIZE_CMD setVoicePktSizeCmd (see include/wmi.h) + * uses: WMI_SET_VOICE_PKT_SIZE_CMDID + */ + + +#define AR6000_XIOCTL_SET_MAX_SP 30 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_MAX_SP) + * WMI_SET_MAX_SP_LEN_CMD maxSPLen(see include/wmi.h) + * uses: WMI_SET_MAX_SP_LEN_CMDID + */ + +#define AR6000_XIOCTL_WMI_GET_ROAM_TBL 31 + +#define AR6000_XIOCTL_WMI_SET_ROAM_CTRL 32 + +#define AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS 33 + + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS) + * WMI_SET_POWERSAVE_TIMERS_CMD powerSaveTimers(see include/wmi.h) + * WMI_SET_POWERSAVE_TIMERS_CMDID + */ + +#define AR6000_XIOCTRL_WMI_GET_POWER_MODE 34 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTRL_WMI_GET_POWER_MODE) + */ + +#define AR6000_XIOCTRL_WMI_SET_WLAN_STATE 35 +typedef enum { + WLAN_DISABLED, + WLAN_ENABLED +} AR6000_WLAN_STATE; +/* + * arguments: + * enable/disable + */ + +#define AR6000_XIOCTL_WMI_GET_ROAM_DATA 36 + +#define AR6000_XIOCTL_WMI_SETRETRYLIMITS 37 +/* + * arguments: + * WMI_SET_RETRY_LIMITS_CMD ibssSetRetryLimitsCmd + * uses: WMI_SET_RETRY_LIMITS_CMDID + */ + +#ifdef CONFIG_HOST_TCMD_SUPPORT +/* ====extended commands for radio test ==== */ + +#define AR6000_XIOCTL_TCMD_CONT_TX 38 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_TX) + * WMI_TCMD_CONT_TX_CMD contTxCmd (see include/wmi.h) + * uses: WMI_TCMD_CONT_TX_CMDID + */ + +#define AR6000_XIOCTL_TCMD_CONT_RX 39 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_RX) + * WMI_TCMD_CONT_RX_CMD rxCmd (see include/wmi.h) + * uses: WMI_TCMD_CONT_RX_CMDID + */ + +#define AR6000_XIOCTL_TCMD_PM 40 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TCMD_PM) + * WMI_TCMD_PM_CMD pmCmd (see include/wmi.h) + * uses: WMI_TCMD_PM_CMDID + */ + +#endif /* CONFIG_HOST_TCMD_SUPPORT */ + +#define AR6000_XIOCTL_WMI_STARTSCAN 41 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_STARTSCAN) + * UINT8 scanType + * UINT8 scanConnected + * A_BOOL forceFgScan + * uses: WMI_START_SCAN_CMDID + */ + +#define AR6000_XIOCTL_WMI_SETFIXRATES 42 + +#define AR6000_XIOCTL_WMI_GETFIXRATES 43 + + +#define AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD 44 +/* + * arguments: + * WMI_RSSI_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h) + * uses: WMI_RSSI_THRESHOLD_PARAMS_CMDID + */ + +#define AR6000_XIOCTL_WMI_CLR_RSSISNR 45 +/* + * arguments: + * WMI_CLR_RSSISNR_CMD thresholdParams (see include/wmi.h) + * uses: WMI_CLR_RSSISNR_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_LQTHRESHOLD 46 +/* + * arguments: + * WMI_LQ_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h) + * uses: WMI_LQ_THRESHOLD_PARAMS_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_RTS 47 +/* + * arguments: + * WMI_SET_RTS_MODE_CMD (see include/wmi.h) + * uses: WMI_SET_RTS_MODE_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_LPREAMBLE 48 + +#define AR6000_XIOCTL_WMI_SET_AUTHMODE 49 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_AUTHMODE) + * UINT8 mode + * uses: WMI_SET_RECONNECT_AUTH_MODE_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_REASSOCMODE 50 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_WMM) + * UINT8 mode + * uses: WMI_SET_WMM_CMDID + */ +#define AR6000_XIOCTL_WMI_SET_WMM 51 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS) + * UINT32 frequency + * UINT8 threshold + */ +#define AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS 52 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP) + * UINT32 cookie + */ +#define AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP 53 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_GET_RD) + * UINT32 regDomain + */ +#define AR6000_XIOCTL_WMI_GET_RD 54 + +#define AR6000_XIOCTL_DIAG_READ 55 + +#define AR6000_XIOCTL_DIAG_WRITE 56 + +/* + * arguments cmd (AR6000_XIOCTL_SET_TXOP) + * WMI_TXOP_CFG txopEnable + */ +#define AR6000_XIOCTL_WMI_SET_TXOP 57 + +#ifdef USER_KEYS +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_USER_SETKEYS) + * UINT32 keyOpCtrl + * uses AR6000_USER_SETKEYS_INFO + */ +#define AR6000_XIOCTL_USER_SETKEYS 58 +#endif /* USER_KEYS */ + +#define AR6000_XIOCTL_WMI_SET_KEEPALIVE 59 +/* + * arguments: + * UINT8 cmd (AR6000_XIOCTL_WMI_SET_KEEPALIVE) + * UINT8 keepaliveInterval + * uses: WMI_SET_KEEPALIVE_CMDID + */ + +#define AR6000_XIOCTL_WMI_GET_KEEPALIVE 60 +/* + * arguments: + * UINT8 cmd (AR6000_XIOCTL_WMI_GET_KEEPALIVE) + * UINT8 keepaliveInterval + * A_BOOL configured + * uses: WMI_GET_KEEPALIVE_CMDID + */ + +/* ====ROM Patching Extended Ioctls==== */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_INSTALL 61 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_INSTALL) + * UINT32 ROM Address + * UINT32 RAM Address + * UINT32 number of bytes + * UINT32 activate? (0 or 1) + * } + * A_UINT32 resulting rompatch ID + * } + * uses: BMI_ROMPATCH_INSTALL + */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL 62 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL) + * UINT32 rompatch ID + * } + * uses: BMI_ROMPATCH_UNINSTALL + */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE 63 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE) + * UINT32 rompatch count + * UINT32 rompatch IDs[rompatch count] + * } + * uses: BMI_ROMPATCH_ACTIVATE + */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE 64 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE) + * UINT32 rompatch count + * UINT32 rompatch IDs[rompatch count] + * } + * uses: BMI_ROMPATCH_DEACTIVATE + */ + +#define AR6000_XIOCTL_WMI_SET_APPIE 65 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_APPIE) + * UINT32 app_frmtype; + * UINT32 app_buflen; + * UINT8 app_buf[]; + * } + */ +#define AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER 66 +/* + * arguments: + * A_UINT32 filter_type; + */ + +#define AR6000_XIOCTL_DBGLOG_CFG_MODULE 67 + +#define AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS 68 + +#define AR6000_XIOCTL_WMI_SET_WSC_STATUS 70 +/* + * arguments: + * A_UINT32 wsc_status; + * (WSC_REG_INACTIVE or WSC_REG_ACTIVE) + */ + +/* + * arguments: + * struct { + * A_UINT8 streamType; + * A_UINT8 status; + * } + * uses: WMI_SET_BT_STATUS_CMDID + */ +#define AR6000_XIOCTL_WMI_SET_BT_STATUS 71 + +/* + * arguments: + * struct { + * A_UINT8 paramType; + * union { + * A_UINT8 noSCOPkts; + * BT_PARAMS_A2DP a2dpParams; + * BT_COEX_REGS regs; + * }; + * } + * uses: WMI_SET_BT_PARAM_CMDID + */ +#define AR6000_XIOCTL_WMI_SET_BT_PARAMS 72 + +#define AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE 73 +#define AR6000_XIOCTL_WMI_SET_WOW_MODE 74 +#define AR6000_XIOCTL_WMI_GET_WOW_LIST 75 +#define AR6000_XIOCTL_WMI_ADD_WOW_PATTERN 76 +#define AR6000_XIOCTL_WMI_DEL_WOW_PATTERN 77 + + + +#define AR6000_XIOCTL_TARGET_INFO 78 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TARGET_INFO) + * A_UINT32 TargetVersion (returned) + * A_UINT32 TargetType (returned) + * (See also bmi_msg.h target_ver and target_type) + */ + +#define AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE 79 +/* + * arguments: + * none + */ + +#define AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE 80 +/* + * This ioctl is used to emulate traffic activity + * timeouts. Activity/inactivity will trigger the driver + * to re-balance credits. + * + * arguments: + * ar6000_traffic_activity_change + */ + +#define AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS 81 +/* + * This ioctl is used to set the connect control flags + * + * arguments: + * A_UINT32 connectCtrlFlags + */ + +#define AR6000_XIOCTL_WMI_SET_AKMP_PARAMS 82 +/* + * This IOCTL sets any Authentication,Key Management and Protection + * related parameters. This is used along with the information set in + * Connect Command. + * Currently this enables Multiple PMKIDs to an AP. + * + * arguments: + * struct { + * A_UINT32 akmpInfo; + * } + * uses: WMI_SET_AKMP_PARAMS_CMD + */ + +#define AR6000_XIOCTL_WMI_GET_PMKID_LIST 83 + +#define AR6000_XIOCTL_WMI_SET_PMKID_LIST 84 +/* + * This IOCTL is used to set a list of PMKIDs. This list of + * PMKIDs is used in the [Re]AssocReq Frame. This list is used + * only if the MultiPMKID option is enabled via the + * AR6000_XIOCTL_WMI_SET_AKMP_PARAMS IOCTL. + * + * arguments: + * struct { + * A_UINT32 numPMKID; + * WMI_PMKID pmkidList[WMI_MAX_PMKID_CACHE]; + * } + * uses: WMI_SET_PMKIDLIST_CMD + */ + +#define AR6000_XIOCTL_WMI_SET_PARAMS 85 +#define AR6000_XIOCTL_WMI_SET_MCAST_FILTER 86 +#define AR6000_XIOCTL_WMI_DEL_MCAST_FILTER 87 + + +/* Historical DSETPATCH support for INI patches */ +#define AR6000_XIOCTL_UNUSED90 90 + + +/* Support LZ-compressed firmware download */ +#define AR6000_XIOCTL_BMI_LZ_STREAM_START 91 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_LZ_STREAM_START) + * UINT32 address + * uses: BMI_LZ_STREAM_START + */ + +#define AR6000_XIOCTL_BMI_LZ_DATA 92 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_LZ_DATA) + * UINT32 length + * char data[length] + * uses: BMI_LZ_DATA + */ + +#define AR6000_XIOCTL_PROF_CFG 93 +/* + * arguments: + * A_UINT32 period + * A_UINT32 nbins + */ + +#define AR6000_XIOCTL_PROF_ADDR_SET 94 +/* + * arguments: + * A_UINT32 Target address + */ + +#define AR6000_XIOCTL_PROF_START 95 + +#define AR6000_XIOCTL_PROF_STOP 96 + +#define AR6000_XIOCTL_PROF_COUNT_GET 97 + +#define AR6000_XIOCTL_WMI_ABORT_SCAN 98 + +/* + * AP mode + */ +#define AR6000_XIOCTL_AP_GET_STA_LIST 99 + +#define AR6000_XIOCTL_AP_HIDDEN_SSID 100 + +#define AR6000_XIOCTL_AP_SET_NUM_STA 101 + +#define AR6000_XIOCTL_AP_SET_ACL_MAC 102 + +#define AR6000_XIOCTL_AP_GET_ACL_LIST 103 + +#define AR6000_XIOCTL_AP_COMMIT_CONFIG 104 + +#define IEEE80211_IOCTL_GETWPAIE 105 + +#define AR6000_XIOCTL_AP_CONN_INACT_TIME 106 + +#define AR6000_XIOCTL_AP_PROT_SCAN_TIME 107 + +#define AR6000_XIOCTL_AP_SET_COUNTRY 108 + +#define AR6000_XIOCTL_AP_SET_DTIM 109 + + + + +#define AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT 110 + +#define AR6000_XIOCTL_SET_IP 111 + +#define AR6000_XIOCTL_AP_SET_ACL_POLICY 112 + +#define AR6000_XIOCTL_AP_INTRA_BSS_COMM 113 + +/* used by AR6000_IOCTL_WMI_GETREV */ +struct ar6000_version { + A_UINT32 host_ver; + A_UINT32 target_ver; + A_UINT32 wlan_ver; +}; + +/* used by AR6000_IOCTL_WMI_GET_QOS_QUEUE */ +struct ar6000_queuereq { + A_UINT8 trafficClass; + A_UINT16 activeTsids; +}; + +/* used by AR6000_IOCTL_WMI_GET_TARGET_STATS */ +typedef struct targetStats_t { + A_UINT64 tx_packets; + A_UINT64 tx_bytes; + A_UINT64 tx_unicast_pkts; + A_UINT64 tx_unicast_bytes; + A_UINT64 tx_multicast_pkts; + A_UINT64 tx_multicast_bytes; + A_UINT64 tx_broadcast_pkts; + A_UINT64 tx_broadcast_bytes; + A_UINT64 tx_rts_success_cnt; + A_UINT64 tx_packet_per_ac[4]; + + A_UINT64 tx_errors; + A_UINT64 tx_failed_cnt; + A_UINT64 tx_retry_cnt; + A_UINT64 tx_mult_retry_cnt; + A_UINT64 tx_rts_fail_cnt; + + A_UINT64 rx_packets; + A_UINT64 rx_bytes; + A_UINT64 rx_unicast_pkts; + A_UINT64 rx_unicast_bytes; + A_UINT64 rx_multicast_pkts; + A_UINT64 rx_multicast_bytes; + A_UINT64 rx_broadcast_pkts; + A_UINT64 rx_broadcast_bytes; + A_UINT64 rx_fragment_pkt; + + A_UINT64 rx_errors; + A_UINT64 rx_crcerr; + A_UINT64 rx_key_cache_miss; + A_UINT64 rx_decrypt_err; + A_UINT64 rx_duplicate_frames; + + A_UINT64 tkip_local_mic_failure; + A_UINT64 tkip_counter_measures_invoked; + A_UINT64 tkip_replays; + A_UINT64 tkip_format_errors; + A_UINT64 ccmp_format_errors; + A_UINT64 ccmp_replays; + + A_UINT64 power_save_failure_cnt; + + A_UINT64 cs_bmiss_cnt; + A_UINT64 cs_lowRssi_cnt; + A_UINT64 cs_connect_cnt; + A_UINT64 cs_disconnect_cnt; + + A_INT32 tx_unicast_rate; + A_INT32 rx_unicast_rate; + + A_UINT32 lq_val; + + A_UINT32 wow_num_pkts_dropped; + A_UINT16 wow_num_events_discarded; + + A_INT16 noise_floor_calibation; + A_INT16 cs_rssi; + A_INT16 cs_aveBeacon_rssi; + A_UINT8 cs_aveBeacon_snr; + A_UINT8 cs_lastRoam_msec; + A_UINT8 cs_snr; + + A_UINT8 wow_num_host_pkt_wakeups; + A_UINT8 wow_num_host_event_wakeups; + + A_UINT32 arp_received; + A_UINT32 arp_matched; + A_UINT32 arp_replied; +}TARGET_STATS; + +typedef struct targetStats_cmd_t { + TARGET_STATS targetStats; + int clearStats; +} TARGET_STATS_CMD; + +/* used by AR6000_XIOCTL_USER_SETKEYS */ + +/* + * Setting this bit to 1 doesnot initialize the RSC on the firmware + */ +#define AR6000_XIOCTL_USER_SETKEYS_RSC_CTRL 1 +#define AR6000_USER_SETKEYS_RSC_UNCHANGED 0x00000002 + +typedef struct { + A_UINT32 keyOpCtrl; /* Bit Map of Key Mgmt Ctrl Flags */ +} AR6000_USER_SETKEYS_INFO; + + +/* used by AR6000_XIOCTL_GPIO_OUTPUT_SET */ +struct ar6000_gpio_output_set_cmd_s { + A_UINT32 set_mask; + A_UINT32 clear_mask; + A_UINT32 enable_mask; + A_UINT32 disable_mask; +}; + +/* + * used by AR6000_XIOCTL_GPIO_REGISTER_GET and AR6000_XIOCTL_GPIO_REGISTER_SET + */ +struct ar6000_gpio_register_cmd_s { + A_UINT32 gpioreg_id; + A_UINT32 value; +}; + +/* used by AR6000_XIOCTL_GPIO_INTR_ACK */ +struct ar6000_gpio_intr_ack_cmd_s { + A_UINT32 ack_mask; +}; + +/* used by AR6000_XIOCTL_GPIO_INTR_WAIT */ +struct ar6000_gpio_intr_wait_cmd_s { + A_UINT32 intr_mask; + A_UINT32 input_values; +}; + +/* used by the AR6000_XIOCTL_DBGLOG_CFG_MODULE */ +typedef struct ar6000_dbglog_module_config_s { + A_UINT32 valid; + A_UINT16 mmask; + A_UINT16 tsr; + A_BOOL rep; + A_UINT16 size; +} DBGLOG_MODULE_CONFIG; + +typedef struct user_rssi_thold_t { + A_INT16 tag; + A_INT16 rssi; +} USER_RSSI_THOLD; + +typedef struct user_rssi_params_t { + A_UINT8 weight; + A_UINT32 pollTime; + USER_RSSI_THOLD tholds[12]; +} USER_RSSI_PARAMS; + +/* + * Host driver may have some config parameters. Typically, these + * config params are one time config parameters. These could + * correspond to any of the underlying modules. Host driver exposes + * an api for the underlying modules to get this config. + */ +#define AR6000_DRIVER_CFG_BASE 0x8000 + +/* Should driver perform wlan node caching? */ +#define AR6000_DRIVER_CFG_GET_WLANNODECACHING 0x8001 +/*Should we log raw WMI msgs */ +#define AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS 0x8002 + +/* used by AR6000_XIOCTL_DIAG_READ & AR6000_XIOCTL_DIAG_WRITE */ +struct ar6000_diag_window_cmd_s { + unsigned int addr; + unsigned int value; +}; + + +struct ar6000_traffic_activity_change { + A_UINT32 StreamID; /* stream ID to indicate activity change */ + A_UINT32 Active; /* active (1) or inactive (0) */ +}; + +/* Used with AR6000_XIOCTL_PROF_COUNT_GET */ +struct prof_count_s { + A_UINT32 addr; /* bin start address */ + A_UINT32 count; /* hit count */ +}; + +#ifdef __cplusplus +} +#endif +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/athendpack.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/athendpack.h --- linux-2.6.26/drivers/net/wireless/ath6k22/athendpack.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/athendpack.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,49 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// end compiler-specific structure packing +// +// Author(s): ="Atheros" +//============================================================================== +#ifdef VXWORKS +#endif /* VXWORKS */ + +#if defined(LINUX) || defined(__linux__) +#endif /* LINUX */ + +#ifdef QNX +#endif /* QNX */ + +#ifdef INTEGRITY +#include "integrity/athendpack_integrity.h" +#endif /* INTEGRITY */ + +#ifdef NUCLEUS +#endif /* NUCLEUS */ + + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/athendpack_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/athendpack_wince.h" +#endif /* WINCE */ + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/athstartpack.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/athstartpack.h --- linux-2.6.26/drivers/net/wireless/ath6k22/athstartpack.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/athstartpack.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,48 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// start compiler-specific structure packing +// +// Author(s): ="Atheros" +//============================================================================== +#ifdef VXWORKS +#endif /* VXWORKS */ + +#if defined(LINUX) || defined(__linux__) +#endif /* LINUX */ + +#ifdef QNX +#endif /* QNX */ + +#ifdef INTEGRITY +#include "integrity/athstartpack_integrity.h" +#endif /* INTEGRITY */ + +#ifdef NUCLEUS +#endif /* NUCLEUS */ + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/athstartpack_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/athstartpack_wince.h" +#endif /* WINCE */ + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/athtypes_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/athtypes_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k22/athtypes_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/athtypes_linux.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,56 @@ +/* + * $Id: //depot/sw/releases/olca2.2/host/os/linux/include/athtypes_linux.h#2 $ + * + * This file contains the definitions of the basic atheros data types. + * It is used to map the data types in atheros files to a platform specific + * type. + * + * Copyright 2003-2005 Atheros Communications, Inc., All Rights Reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _ATHTYPES_LINUX_H_ +#define _ATHTYPES_LINUX_H_ + +#ifdef ANDROID +#include +#include +#else +#ifdef __KERNEL__ +#include +#endif +#endif + +typedef int8_t A_INT8; +typedef int16_t A_INT16; +typedef int32_t A_INT32; +typedef int64_t A_INT64; + +typedef u_int8_t A_UINT8; +typedef u_int16_t A_UINT16; +typedef u_int32_t A_UINT32; +typedef u_int64_t A_UINT64; + +typedef int A_BOOL; +typedef char A_CHAR; +typedef unsigned char A_UCHAR; +typedef unsigned long A_ATH_TIMER; + + +#endif /* _ATHTYPES_LINUX_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/bmi.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/bmi.c --- linux-2.6.26/drivers/net/wireless/ath6k22/bmi.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/bmi.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,879 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// +// Author(s): ="Atheros" +//============================================================================== + +#include "hif.h" +#include "bmi.h" +#include "htc_api.h" +#include "bmi_internal.h" + +/* +Although we had envisioned BMI to run on top of HTC, this is not how the +final implementation ended up. On the Target side, BMI is a part of the BSP +and does not use the HTC protocol nor even DMA -- it is intentionally kept +very simple. +*/ + +static A_BOOL pendingEventsFuncCheck = FALSE; + +/* APIs visible to the driver */ +void +BMIInit(void) +{ + bmiDone = FALSE; + pendingEventsFuncCheck = FALSE; +} + +A_STATUS +BMIDone(HIF_DEVICE *device) +{ + A_STATUS status; + A_UINT32 cid; + + if (bmiDone) { + AR_DEBUG_PRINTF (ATH_DEBUG_BMI, ("BMIDone skipped\n")); + return A_OK; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Enter (device: 0x%p)\n", device)); + bmiDone = TRUE; + cid = BMI_DONE; + + status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid)); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Exit\n")); + + return A_OK; +} + +A_STATUS +BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info) +{ + A_STATUS status; + A_UINT32 cid; + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Enter (device: 0x%p)\n", device)); + cid = BMI_GET_TARGET_INFO; + + status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid)); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_ver, + sizeof(targ_info->target_ver), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Version from the device\n")); + return A_ERROR; + } + + if (targ_info->target_ver == TARGET_VERSION_SENTINAL) { + /* Determine how many bytes are in the Target's targ_info */ + status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_info_byte_count, + sizeof(targ_info->target_info_byte_count), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info Byte Count from the device\n")); + return A_ERROR; + } + + /* + * The Target's targ_info doesn't match the Host's targ_info. + * We need to do some backwards compatibility work to make this OK. + */ + A_ASSERT(targ_info->target_info_byte_count == sizeof(*targ_info)); + + /* Read the remainder of the targ_info */ + status = bmiBufferReceive(device, + ((A_UCHAR *)targ_info)+sizeof(targ_info->target_info_byte_count), + sizeof(*targ_info)-sizeof(targ_info->target_info_byte_count), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info (%d bytes) from the device\n", + targ_info->target_info_byte_count)); + return A_ERROR; + } + } else { + /* + * Target must be an AR6001 whose firmware does not + * support BMI_GET_TARGET_INFO. Construct the data + * that it would have sent. + */ + targ_info->target_info_byte_count=sizeof(*targ_info); + targ_info->target_type=TARGET_TYPE_AR6001; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Exit (ver: 0x%x type: 0x%x)\n", + targ_info->target_ver, targ_info->target_type)); + + return A_OK; +} + +A_STATUS +BMIReadMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + A_UINT32 remaining, rxlen; + static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)]; + memset (&data, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Read Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n", + device, address, length)); + + cid = BMI_READ_MEMORY; + + remaining = length; + + while (remaining) + { + rxlen = (remaining < BMI_DATASZ_MAX) ? remaining : BMI_DATASZ_MAX; + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&data[offset], &rxlen, sizeof(rxlen)); + offset += sizeof(length); + + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + status = bmiBufferReceive(device, data, rxlen, TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + A_MEMCPY(&buffer[length - remaining], data, rxlen); + remaining -= rxlen; address += rxlen; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read Memory: Exit\n")); + return A_OK; +} + +A_STATUS +BMIWriteMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + A_UINT32 remaining, txlen; + const A_UINT32 header = sizeof(cid) + sizeof(address) + sizeof(length); + static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)]; + memset (&data, 0, BMI_DATASZ_MAX+header); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Write Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n", + device, address, length)); + + cid = BMI_WRITE_MEMORY; + + remaining = length; + while (remaining) + { + txlen = (remaining < (BMI_DATASZ_MAX - header)) ? + remaining : (BMI_DATASZ_MAX - header); + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&data[offset], &txlen, sizeof(txlen)); + offset += sizeof(txlen); + A_MEMCPY(&data[offset], &buffer[length - remaining], txlen); + offset += txlen; + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + remaining -= txlen; address += txlen; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Write Memory: Exit\n")); + + return A_OK; +} + +A_STATUS +BMIExecute(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address) + sizeof(*param)]; + memset (&data, 0, sizeof(cid) + sizeof(address) + sizeof(*param)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Execute: Enter (device: 0x%p, address: 0x%x, param: %d)\n", + device, address, *param)); + + cid = BMI_EXECUTE; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&data[offset], param, sizeof(*param)); + offset += sizeof(*param); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, data, sizeof(*param), FALSE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + + A_MEMCPY(param, data, sizeof(*param)); + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Execute: Exit (param: %d)\n", *param)); + return A_OK; +} + +A_STATUS +BMISetAppStart(HIF_DEVICE *device, + A_UINT32 address) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address)]; + memset (&data, 0, sizeof(cid) + sizeof(address)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Set App Start: Enter (device: 0x%p, address: 0x%x)\n", + device, address)); + + cid = BMI_SET_APP_START; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Set App Start: Exit\n")); + return A_OK; +} + +A_STATUS +BMIReadSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address)]; + memset (&data, 0, sizeof(cid) + sizeof(address)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Read SOC Register: Enter (device: 0x%p, address: 0x%x)\n", + device, address)); + + cid = BMI_READ_SOC_REGISTER; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, data, sizeof(*param), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + A_MEMCPY(param, data, sizeof(*param)); + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit (value: %d)\n", *param)); + return A_OK; +} + +A_STATUS +BMIWriteSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 param) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address) + sizeof(param)]; + + memset (&data, 0, sizeof(cid) + sizeof(address) + sizeof(param)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Write SOC Register: Enter (device: 0x%p, address: 0x%x, param: %d)\n", + device, address, param)); + + cid = BMI_WRITE_SOC_REGISTER; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&data[offset], ¶m, sizeof(param)); + offset += sizeof(param); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit\n")); + return A_OK; +} + +A_STATUS +BMIrompatchInstall(HIF_DEVICE *device, + A_UINT32 ROM_addr, + A_UINT32 RAM_addr, + A_UINT32 nbytes, + A_UINT32 do_activate, + A_UINT32 *rompatch_id) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) + + sizeof(nbytes) + sizeof(do_activate)]; + + memset (&data, 0, sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) + + sizeof(nbytes) + sizeof(do_activate)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI rompatch Install: Enter (device: 0x%p, ROMaddr: 0x%x, RAMaddr: 0x%x length: %d activate: %d)\n", + device, ROM_addr, RAM_addr, nbytes, do_activate)); + + cid = BMI_ROMPATCH_INSTALL; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &ROM_addr, sizeof(ROM_addr)); + offset += sizeof(ROM_addr); + A_MEMCPY(&data[offset], &RAM_addr, sizeof(RAM_addr)); + offset += sizeof(RAM_addr); + A_MEMCPY(&data[offset], &nbytes, sizeof(nbytes)); + offset += sizeof(nbytes); + A_MEMCPY(&data[offset], &do_activate, sizeof(do_activate)); + offset += sizeof(do_activate); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, (A_UCHAR *)rompatch_id, sizeof(*rompatch_id), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch Install: (rompatch_id=%d)\n", *rompatch_id)); + return A_OK; +} + +A_STATUS +BMIrompatchUninstall(HIF_DEVICE *device, + A_UINT32 rompatch_id) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(rompatch_id)]; + memset (&data, 0, sizeof(cid) + sizeof(rompatch_id)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI rompatch Uninstall: Enter (device: 0x%p, rompatch_id: %d)\n", + device, rompatch_id)); + + cid = BMI_ROMPATCH_UNINSTALL; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &rompatch_id, sizeof(rompatch_id)); + offset += sizeof(rompatch_id); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch UNinstall: (rompatch_id=0x%x)\n", rompatch_id)); + return A_OK; +} + +static A_STATUS +_BMIrompatchChangeActivation(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list, + A_UINT32 do_activate) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count)]; + A_UINT32 length; + + memset (&data, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Change rompatch Activation: Enter (device: 0x%p, count: %d)\n", + device, rompatch_count)); + + cid = do_activate ? BMI_ROMPATCH_ACTIVATE : BMI_ROMPATCH_DEACTIVATE; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &rompatch_count, sizeof(rompatch_count)); + offset += sizeof(rompatch_count); + length = rompatch_count * sizeof(*rompatch_list); + A_MEMCPY(&data[offset], rompatch_list, length); + offset += length; + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Change rompatch Activation: Exit\n")); + + return A_OK; +} + +A_STATUS +BMIrompatchActivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list) +{ + return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 1); +} + +A_STATUS +BMIrompatchDeactivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list) +{ + return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 0); +} + +A_STATUS +BMILZData(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + A_UINT32 remaining, txlen; + const A_UINT32 header = sizeof(cid) + sizeof(length); + static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(length)]; + + memset (&data, 0, BMI_DATASZ_MAX+header); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Send LZ Data: Enter (device: 0x%p, length: %d)\n", + device, length)); + + cid = BMI_LZ_DATA; + + remaining = length; + while (remaining) + { + txlen = (remaining < (BMI_DATASZ_MAX - header)) ? + remaining : (BMI_DATASZ_MAX - header); + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &txlen, sizeof(txlen)); + offset += sizeof(txlen); + A_MEMCPY(&data[offset], &buffer[length - remaining], txlen); + offset += txlen; + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + remaining -= txlen; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI LZ Data: Exit\n")); + + return A_OK; +} + +A_STATUS +BMILZStreamStart(HIF_DEVICE *device, + A_UINT32 address) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address)]; + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI LZ Stream Start: Enter (device: 0x%p, address: 0x%x)\n", + device, address)); + + cid = BMI_LZ_STREAM_START; + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to Start LZ Stream to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI LZ Stream Start: Exit\n")); + + return A_OK; +} + +/* BMI Access routines */ +A_STATUS +bmiBufferSend(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_STATUS status; + A_UINT32 timeout; + A_UINT32 address; + static A_UINT32 cmdCredits; + A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX]; + + HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR, + &mboxAddress[0], sizeof(mboxAddress)); + + cmdCredits = 0; + timeout = BMI_COMMUNICATION_TIMEOUT; + + while(timeout-- && !cmdCredits) { + /* Read the counter register to get the command credits */ + address = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4; + /* hit the credit counter with a 4-byte access, the first byte read will hit the counter and cause + * a decrement, while the remaining 3 bytes has no effect. The rationale behind this is to + * make all HIF accesses 4-byte aligned */ + status = HIFReadWrite(device, address, (A_UINT8 *)&cmdCredits, 4, + HIF_RD_SYNC_BYTE_INC, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to decrement the command credit count register\n")); + return A_ERROR; + } + /* the counter is only 8=bits, ignore anything in the upper 3 bytes */ + cmdCredits &= 0xFF; + } + + if (cmdCredits) { + address = mboxAddress[ENDPOINT1]; + status = HIFReadWrite(device, address, buffer, length, + HIF_WR_SYNC_BYTE_INC, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to send the BMI data to the device\n")); + return A_ERROR; + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout - bmiBufferSend\n")); + return A_ERROR; + } + + return status; +} + +A_STATUS +bmiBufferReceive(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length, + A_BOOL want_timeout) +{ + A_STATUS status; + A_UINT32 address; + A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX]; + HIF_PENDING_EVENTS_INFO hifPendingEvents; + static HIF_PENDING_EVENTS_FUNC getPendingEventsFunc = NULL; + + if (!pendingEventsFuncCheck) { + /* see if the HIF layer implements an alternative function to get pending events + * do this only once! */ + HIFConfigureDevice(device, + HIF_DEVICE_GET_PENDING_EVENTS_FUNC, + &getPendingEventsFunc, + sizeof(getPendingEventsFunc)); + pendingEventsFuncCheck = TRUE; + } + + HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR, + &mboxAddress[0], sizeof(mboxAddress)); + + /* + * During normal bootup, small reads may be required. + * Rather than issue an HIF Read and then wait as the Target + * adds successive bytes to the FIFO, we wait here until + * we know that response data is available. + * + * This allows us to cleanly timeout on an unexpected + * Target failure rather than risk problems at the HIF level. In + * particular, this avoids SDIO timeouts and possibly garbage + * data on some host controllers. And on an interconnect + * such as Compact Flash (as well as some SDIO masters) which + * does not provide any indication on data timeout, it avoids + * a potential hang or garbage response. + * + * Synchronization is more difficult for reads larger than the + * size of the MBOX FIFO (128B), because the Target is unable + * to push the 129th byte of data until AFTER the Host posts an + * HIF Read and removes some FIFO data. So for large reads the + * Host proceeds to post an HIF Read BEFORE all the data is + * actually available to read. Fortunately, large BMI reads do + * not occur in practice -- they're supported for debug/development. + * + * So Host/Target BMI synchronization is divided into these cases: + * CASE 1: length < 4 + * Should not happen + * + * CASE 2: 4 <= length <= 128 + * Wait for first 4 bytes to be in FIFO + * If CONSERVATIVE_BMI_READ is enabled, also wait for + * a BMI command credit, which indicates that the ENTIRE + * response is available in the the FIFO + * + * CASE 3: length > 128 + * Wait for the first 4 bytes to be in FIFO + * + * For most uses, a small timeout should be sufficient and we will + * usually see a response quickly; but there may be some unusual + * (debug) cases of BMI_EXECUTE where we want an larger timeout. + * For now, we use an unbounded busy loop while waiting for + * BMI_EXECUTE. + * + * If BMI_EXECUTE ever needs to support longer-latency execution, + * especially in production, this code needs to be enhanced to sleep + * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently + * a function of Host processor speed. + */ + if (length >= 4) { /* NB: Currently, always true */ + /* + * NB: word_available is declared static for esoteric reasons + * having to do with protection on some OSes. + */ + static A_UINT32 word_available; + A_UINT32 timeout; + + word_available = 0; + timeout = BMI_COMMUNICATION_TIMEOUT; + while((!want_timeout || timeout--) && !word_available) { + + if (getPendingEventsFunc != NULL) { + status = getPendingEventsFunc(device, + &hifPendingEvents, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMI: Failed to get pending events \n")); + break; + } + + if (hifPendingEvents.AvailableRecvBytes >= sizeof(A_UINT32)) { + word_available = 1; + } + continue; + } + + status = HIFReadWrite(device, RX_LOOKAHEAD_VALID_ADDRESS, (A_UINT8 *)&word_available, + sizeof(word_available), HIF_RD_SYNC_BYTE_INC, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read RX_LOOKAHEAD_VALID register\n")); + return A_ERROR; + } + /* We did a 4-byte read to the same register; all we really want is one bit */ + word_available &= (1 << ENDPOINT1); + } + + if (!word_available) { + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Communication timeout - bmiBufferReceive FIFO empty\n")); + return A_ERROR; + } + } + +#define CONSERVATIVE_BMI_READ 0 +#if CONSERVATIVE_BMI_READ + /* + * This is an extra-conservative CREDIT check. It guarantees + * that ALL data is available in the FIFO before we start to + * read from the interconnect. + * + * This credit check is useless when firmware chooses to + * allow multiple outstanding BMI Command Credits, since the next + * credit will already be present. To restrict the Target to one + * BMI Command Credit, see HI_OPTION_BMI_CRED_LIMIT. + * + * And for large reads (when HI_OPTION_BMI_CRED_LIMIT is set) + * we cannot wait for the next credit because the Target's FIFO + * will not hold the entire response. So we need the Host to + * start to empty the FIFO sooner. (And again, large reads are + * not used in practice; they are for debug/development only.) + * + * For a more conservative Host implementation (which would be + * safer for a Compact Flash interconnect): + * Set CONSERVATIVE_BMI_READ (above) to 1 + * Set HI_OPTION_BMI_CRED_LIMIT and + * reduce BMI_DATASZ_MAX to 32 or 64 + */ + if ((length > 4) && (length < 128)) { /* check against MBOX FIFO size */ + /* + * NB: cmdCredits is declared static for esoteric reasons + * having to do with protection on some OSes. + */ + static A_UINT32 cmdCredits; + A_UINT32 timeout; + + cmdCredits = 0; + timeout = BMI_COMMUNICATION_TIMEOUT; + while((!want_timeout || timeout--) && !cmdCredits) { + /* Read the counter register to get the command credits */ + address = COUNT_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 1; + /* read the counter using a 4-byte read. Since the counter is NOT auto-decrementing, + * we can read this counter multiple times using a non-incrementing address mode. + * The rationale here is to make all HIF accesses a multiple of 4 bytes */ + status = HIFReadWrite(device, address, (A_UINT8 *)&cmdCredits, sizeof(cmdCredits), + HIF_RD_SYNC_BYTE_FIX, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the command credit count register\n")); + return A_ERROR; + } + /* we did a 4-byte read to the same count register so mask off upper bytes */ + cmdCredits &= 0xFF; + } + + if (!cmdCredits) { + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Communication timeout- bmiBufferReceive no credit\n")); + return A_ERROR; + } + } +#endif + + address = mboxAddress[ENDPOINT1]; + status = HIFReadWrite(device, address, buffer, length, HIF_RD_SYNC_BYTE_INC, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the BMI data from the device\n")); + return A_ERROR; + } + + return A_OK; +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/bmi.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/bmi.h --- linux-2.6.26/drivers/net/wireless/ath6k22/bmi.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/bmi.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,115 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// BMI declarations and prototypes +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _BMI_H_ +#define _BMI_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Header files */ +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "hif.h" +#include "a_osapi.h" +#include "bmi_msg.h" + +void +BMIInit(void); + +A_STATUS +BMIDone(HIF_DEVICE *device); + +A_STATUS +BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info); + +A_STATUS +BMIReadMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length); + +A_STATUS +BMIWriteMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length); + +A_STATUS +BMIExecute(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param); + +A_STATUS +BMISetAppStart(HIF_DEVICE *device, + A_UINT32 address); + +A_STATUS +BMIReadSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param); + +A_STATUS +BMIWriteSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 param); + +A_STATUS +BMIrompatchInstall(HIF_DEVICE *device, + A_UINT32 ROM_addr, + A_UINT32 RAM_addr, + A_UINT32 nbytes, + A_UINT32 do_activate, + A_UINT32 *patch_id); + +A_STATUS +BMIrompatchUninstall(HIF_DEVICE *device, + A_UINT32 rompatch_id); + +A_STATUS +BMIrompatchActivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list); + +A_STATUS +BMIrompatchDeactivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list); + +A_STATUS +BMILZStreamStart(HIF_DEVICE *device, + A_UINT32 address); + +A_STATUS +BMILZData(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length); + +#ifdef __cplusplus +} +#endif + +#endif /* _BMI_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/bmi_internal.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/bmi_internal.h --- linux-2.6.26/drivers/net/wireless/ath6k22/bmi_internal.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/bmi_internal.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,51 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef BMI_INTERNAL_H +#define BMI_INTERNAL_H + +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "a_debug.h" +#include "mbox_host_reg.h" +#include "bmi_msg.h" + +#define BMI_COMMUNICATION_TIMEOUT 100000 + +/* ------ Global Variable Declarations ------- */ +A_BOOL bmiDone; + +A_STATUS +bmiBufferSend(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length); + +A_STATUS +bmiBufferReceive(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length, + A_BOOL want_timeout); + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/bmi_msg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/bmi_msg.h --- linux-2.6.26/drivers/net/wireless/ath6k22/bmi_msg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/bmi_msg.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,235 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __BMI_MSG_H__ +#define __BMI_MSG_H__ + +/* + * Bootloader Messaging Interface (BMI) + * + * BMI is a very simple messaging interface used during initialization + * to read memory, write memory, execute code, and to define an + * application entry PC. + * + * It is used to download an application to AR6K, to provide + * patches to code that is already resident on AR6K, and generally + * to examine and modify state. The Host has an opportunity to use + * BMI only once during bootup. Once the Host issues a BMI_DONE + * command, this opportunity ends. + * + * The Host writes BMI requests to mailbox0, and reads BMI responses + * from mailbox0. BMI requests all begin with a command + * (see below for specific commands), and are followed by + * command-specific data. + * + * Flow control: + * The Host can only issue a command once the Target gives it a + * "BMI Command Credit", using AR6K Counter #4. As soon as the + * Target has completed a command, it issues another BMI Command + * Credit (so the Host can issue the next command). + * + * BMI handles all required Target-side cache flushing. + */ + + +/* Maximum data size used for BMI transfers */ +#define BMI_DATASZ_MAX 256 + +/* BMI Commands */ + +#define BMI_NO_COMMAND 0 + +#define BMI_DONE 1 + /* + * Semantics: Host is done using BMI + * Request format: + * A_UINT32 command (BMI_DONE) + * Response format: none + */ + +#define BMI_READ_MEMORY 2 + /* + * Semantics: Host reads AR6K memory + * Request format: + * A_UINT32 command (BMI_READ_MEMORY) + * A_UINT32 address + * A_UINT32 length, at most BMI_DATASZ_MAX + * Response format: + * A_UINT8 data[length] + */ + +#define BMI_WRITE_MEMORY 3 + /* + * Semantics: Host writes AR6K memory + * Request format: + * A_UINT32 command (BMI_WRITE_MEMORY) + * A_UINT32 address + * A_UINT32 length, at most BMI_DATASZ_MAX + * A_UINT8 data[length] + * Response format: none + */ + +#define BMI_EXECUTE 4 + /* + * Semantics: Causes AR6K to execute code + * Request format: + * A_UINT32 command (BMI_EXECUTE) + * A_UINT32 address + * A_UINT32 parameter + * Response format: + * A_UINT32 return value + */ + +#define BMI_SET_APP_START 5 + /* + * Semantics: Set Target application starting address + * Request format: + * A_UINT32 command (BMI_SET_APP_START) + * A_UINT32 address + * Response format: none + */ + +#define BMI_READ_SOC_REGISTER 6 + /* + * Semantics: Read a 32-bit Target SOC register. + * Request format: + * A_UINT32 command (BMI_READ_REGISTER) + * A_UINT32 address + * Response format: + * A_UINT32 value + */ + +#define BMI_WRITE_SOC_REGISTER 7 + /* + * Semantics: Write a 32-bit Target SOC register. + * Request format: + * A_UINT32 command (BMI_WRITE_REGISTER) + * A_UINT32 address + * A_UINT32 value + * + * Response format: none + */ + +#define BMI_GET_TARGET_ID 8 +#define BMI_GET_TARGET_INFO 8 + /* + * Semantics: Fetch the 4-byte Target information + * Request format: + * A_UINT32 command (BMI_GET_TARGET_ID/INFO) + * Response format1 (old firmware): + * A_UINT32 TargetVersionID + * Response format2 (newer firmware): + * A_UINT32 TARGET_VERSION_SENTINAL + * struct bmi_target_info; + */ + +struct bmi_target_info { + A_UINT32 target_info_byte_count; /* size of this structure */ + A_UINT32 target_ver; /* Target Version ID */ + A_UINT32 target_type; /* Target type */ +}; +#define TARGET_VERSION_SENTINAL 0xffffffff +#define TARGET_TYPE_AR6001 1 +#define TARGET_TYPE_AR6002 2 +#define TARGET_TYPE_AR6003 3 + + +#define BMI_ROMPATCH_INSTALL 9 + /* + * Semantics: Install a ROM Patch. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_INSTALL) + * A_UINT32 Target ROM Address + * A_UINT32 Target RAM Address + * A_UINT32 Size, in bytes + * A_UINT32 Activate? 1-->activate; + * 0-->install but do not activate + * Response format: + * A_UINT32 PatchID + */ + +#define BMI_ROMPATCH_UNINSTALL 10 + /* + * Semantics: Uninstall a previously-installed ROM Patch, + * automatically deactivating, if necessary. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_UNINSTALL) + * A_UINT32 PatchID + * + * Response format: none + */ + +#define BMI_ROMPATCH_ACTIVATE 11 + /* + * Semantics: Activate a list of previously-installed ROM Patches. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_ACTIVATE) + * A_UINT32 rompatch_count + * A_UINT32 PatchID[rompatch_count] + * + * Response format: none + */ + +#define BMI_ROMPATCH_DEACTIVATE 12 + /* + * Semantics: Deactivate a list of active ROM Patches. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_DEACTIVATE) + * A_UINT32 rompatch_count + * A_UINT32 PatchID[rompatch_count] + * + * Response format: none + */ + + +#define BMI_LZ_STREAM_START 13 + /* + * Semantics: Begin an LZ-compressed stream of input + * which is to be uncompressed by the Target to an + * output buffer at address. The output buffer must + * be sufficiently large to hold the uncompressed + * output from the compressed input stream. This BMI + * command should be followed by a series of 1 or more + * BMI_LZ_DATA commands. + * A_UINT32 command (BMI_LZ_STREAM_START) + * A_UINT32 address + * Note: Not supported on all versions of ROM firmware. + */ + +#define BMI_LZ_DATA 14 + /* + * Semantics: Host writes AR6K memory with LZ-compressed + * data which is uncompressed by the Target. This command + * must be preceded by a BMI_LZ_STREAM_START command. A series + * of BMI_LZ_DATA commands are considered part of a single + * input stream until another BMI_LZ_STREAM_START is issued. + * Request format: + * A_UINT32 command (BMI_LZ_DATA) + * A_UINT32 length (of compressed data), + * at most BMI_DATASZ_MAX + * A_UINT8 CompressedData[length] + * Response format: none + * Note: Not supported on all versions of ROM firmware. + */ + +#endif /* __BMI_MSG_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/cnxmgmt.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/cnxmgmt.h --- linux-2.6.26/drivers/net/wireless/ath6k22/cnxmgmt.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/cnxmgmt.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,33 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _CNXMGMT_H_ +#define _CNXMGMT_H_ + +typedef enum { + CM_CONNECT_WITHOUT_SCAN = 0x0001, + CM_CONNECT_ASSOC_POLICY_USER = 0x0002, + CM_CONNECT_SEND_REASSOC = 0x0004, +} CM_CONNECT_TYPE; + +#endif /* _CNXMGMT_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/common_drv.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/common_drv.c --- linux-2.6.26/drivers/net/wireless/ath6k22/common_drv.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/common_drv.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,663 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" + +#include "mbox_host_reg.h" +#include "apb_map.h" +#include "si_reg.h" +#include "gpio_reg.h" +#include "rtc_reg.h" +#include "vmc_reg.h" +#include "mbox_reg.h" + +#include "targaddrs.h" +#include "a_osapi.h" +#include "hif.h" +#include "htc_api.h" +#include "wmi.h" +#include "bmi.h" +#include "bmi_msg.h" +#include "common_drv.h" +#include "a_debug.h" + +#define HOST_INTEREST_ITEM_ADDRESS(target, item) \ + (((target) == TARGET_TYPE_AR6001) ? AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((target) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((target) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : 0))) + + +#define AR6001_LOCAL_COUNT_ADDRESS 0x0c014080 +#define AR6002_LOCAL_COUNT_ADDRESS 0x00018080 +#define AR6003_LOCAL_COUNT_ADDRESS 0x00018080 + +/* Compile the 4BYTE version of the window register setup routine, + * This mitigates host interconnect issues with non-4byte aligned bus requests, some + * interconnects use bus adapters that impose strict limitations. + * Since diag window access is not intended for performance critical operations, the 4byte mode should + * be satisfactory even though it generates 4X the bus activity. */ + +#ifdef USE_4BYTE_REGISTER_ACCESS + + /* set the window address register (using 4-byte register access ). */ +A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address) +{ + A_STATUS status; + A_UINT8 addrValue[4]; + A_INT32 i; + + /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written + * last to initiate the access cycle */ + + for (i = 1; i <= 3; i++) { + /* fill the buffer with the address byte value we want to hit 4 times*/ + addrValue[0] = ((A_UINT8 *)&Address)[i]; + addrValue[1] = addrValue[0]; + addrValue[2] = addrValue[0]; + addrValue[3] = addrValue[0]; + + /* hit each byte of the register address with a 4-byte write operation to the same address, + * this is a harmless operation */ + status = HIFReadWrite(hifDevice, + RegisterAddr+i, + addrValue, + 4, + HIF_WR_SYNC_BYTE_FIX, + NULL); + if (status != A_OK) { + break; + } + } + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n", + RegisterAddr, Address)); + return status; + } + + /* write the address register again, this time write the whole 4-byte value. + * The effect here is that the LSB write causes the cycle to start, the extra + * 3 byte write to bytes 1,2,3 has no effect since we are writing the same values again */ + status = HIFReadWrite(hifDevice, + RegisterAddr, + (A_UCHAR *)(&Address), + 4, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n", + RegisterAddr, Address)); + return status; + } + + return A_OK; + + + +} + + +#else + + /* set the window address register */ +A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address) +{ + A_STATUS status; + + /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written + * last to initiate the access cycle */ + status = HIFReadWrite(hifDevice, + RegisterAddr+1, /* write upper 3 bytes */ + ((A_UCHAR *)(&Address))+1, + sizeof(A_UINT32)-1, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n", + RegisterAddr, Address)); + return status; + } + + /* write the LSB of the register, this initiates the operation */ + status = HIFReadWrite(hifDevice, + RegisterAddr, + (A_UCHAR *)(&Address), + sizeof(A_UINT8), + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n", + RegisterAddr, Address)); + return status; + } + + return A_OK; +} + +#endif + +/* + * Read from the AR6000 through its diagnostic window. + * No cooperation from the Target is required for this. + */ +A_STATUS +ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data) +{ + A_STATUS status; + + /* set window register to start read cycle */ + status = ar6000_SetAddressWindowRegister(hifDevice, + WINDOW_READ_ADDR_ADDRESS, + *address); + + if (status != A_OK) { + return status; + } + + /* read the data */ + status = HIFReadWrite(hifDevice, + WINDOW_DATA_ADDRESS, + (A_UCHAR *)data, + sizeof(A_UINT32), + HIF_RD_SYNC_BYTE_INC, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from WINDOW_DATA_ADDRESS\n")); + return status; + } + + return status; +} + + +/* + * Write to the AR6000 through its diagnostic window. + * No cooperation from the Target is required for this. + */ +A_STATUS +ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data) +{ + A_STATUS status; + + /* set write data */ + status = HIFReadWrite(hifDevice, + WINDOW_DATA_ADDRESS, + (A_UCHAR *)data, + sizeof(A_UINT32), + HIF_WR_SYNC_BYTE_INC, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to WINDOW_DATA_ADDRESS\n", *data)); + return status; + } + + /* set window register, which starts the write cycle */ + return ar6000_SetAddressWindowRegister(hifDevice, + WINDOW_WRITE_ADDR_ADDRESS, + *address); + } + +A_STATUS +ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length) +{ + A_UINT32 count; + A_STATUS status = A_OK; + + for (count = 0; count < length; count += 4, address += 4) { + if ((status = ar6000_ReadRegDiag(hifDevice, &address, + (A_UINT32 *)&data[count])) != A_OK) + { + break; + } + } + + return status; +} + +A_STATUS +ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length) +{ + A_UINT32 count; + A_STATUS status = A_OK; + + for (count = 0; count < length; count += 4, address += 4) { + if ((status = ar6000_WriteRegDiag(hifDevice, &address, + (A_UINT32 *)&data[count])) != A_OK) + { + break; + } + } + + return status; +} + +#if 0 +static A_STATUS +_do_write_diag(HIF_DEVICE *hifDevice, A_UINT32 addr, A_UINT32 value) +{ + A_STATUS status; + + status = ar6000_WriteRegDiag(hifDevice, &addr, &value); + if (status != A_OK) + { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot force Target to execute ROM!\n")); + } + + return status; +} +#endif + + +/* + * Delay up to wait_msecs millisecs to allow Target to enter BMI phase, + * which is a good sign that it's alive and well. This is used after + * explicitly forcing the Target to reset. + * + * The wait_msecs time should be sufficiently long to cover any reasonable + * boot-time delay. For instance, AR6001 firmware allow one second for a + * low frequency crystal to settle before it calibrates the refclk frequency. + * + * TBD: Might want to add special handling for AR6K_OPTION_BMI_DISABLE. + */ +static A_STATUS +_delay_until_target_alive(HIF_DEVICE *hifDevice, A_INT32 wait_msecs, A_UINT32 TargetType) +{ + A_INT32 actual_wait; + A_INT32 i; + A_UINT32 address; + + actual_wait = 0; + + /* Hardcode the address of LOCAL_COUNT_ADDRESS based on the target type */ + if (TargetType == TARGET_TYPE_AR6001) { + address = AR6001_LOCAL_COUNT_ADDRESS; + } else if (TargetType == TARGET_TYPE_AR6002) { + address = AR6002_LOCAL_COUNT_ADDRESS; + } else if (TargetType == TARGET_TYPE_AR6003) { + address = AR6003_LOCAL_COUNT_ADDRESS; + } else { + A_ASSERT(0); + } + address += 0x10; + for (i=0; actual_wait < wait_msecs; i++) { + A_UINT32 data; + + A_MDELAY(100); + actual_wait += 100; + + data = 0; + if (ar6000_ReadRegDiag(hifDevice, &address, &data) != A_OK) { + return A_ERROR; + } + + if (data != 0) { + /* No need to wait longer -- we have a BMI credit */ + return A_OK; + } + } + return A_ERROR; /* timed out */ +} + +#define AR6001_RESET_CONTROL_ADDRESS 0x0C000000 +#define AR6002_RESET_CONTROL_ADDRESS 0x00004000 +#define AR6003_RESET_CONTROL_ADDRESS 0x00004000 +/* reset device */ +A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType, A_BOOL waitForCompletion) +{ + A_STATUS status = A_OK; + A_UINT32 address; + A_UINT32 data; + + do { + + // address = RESET_CONTROL_ADDRESS; + data = RESET_CONTROL_COLD_RST_MASK; + + /* Hardcode the address of RESET_CONTROL_ADDRESS based on the target type */ + if (TargetType == TARGET_TYPE_AR6001) { + address = AR6001_RESET_CONTROL_ADDRESS; + } else if (TargetType == TARGET_TYPE_AR6002) { + address = AR6002_RESET_CONTROL_ADDRESS; + } else if (TargetType == TARGET_TYPE_AR6003) { + address = AR6003_RESET_CONTROL_ADDRESS; + } else { + A_ASSERT(0); + } + + + status = ar6000_WriteRegDiag(hifDevice, &address, &data); + + if (A_FAILED(status)) { + break; + } + + if (!waitForCompletion) { + break; + } + + + /* Up to 2 second delay to allow things to settle down */ + (void)_delay_until_target_alive(hifDevice, 2000, TargetType); + + /* + * Read back the RESET CAUSE register to ensure that the cold reset + * went through. + */ + + // address = RESET_CAUSE_ADDRESS; + /* Hardcode the address of RESET_CAUSE_ADDRESS based on the target type */ + if (TargetType == TARGET_TYPE_AR6001) { + address = 0x0C0000CC; + } else if (TargetType == TARGET_TYPE_AR6002) { + address = 0x000040C0; + } else if (TargetType == TARGET_TYPE_AR6003) { + address = 0x000040C0; + } else { + A_ASSERT(0); + } + + data = 0; + status = ar6000_ReadRegDiag(hifDevice, &address, &data); + + if (A_FAILED(status)) { + break; + } + + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Reset Cause readback: 0x%X \n",data)); + data &= RESET_CAUSE_LAST_MASK; + if (data != 2) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Unable to cold reset the target \n")); + } + + } while (FALSE); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Failed to reset target \n")); + } + + return A_OK; +} + +#define REG_DUMP_COUNT_AR6001 38 /* WORDs, derived from AR600x_regdump.h */ +#define REG_DUMP_COUNT_AR6002 32 +#define REG_DUMP_COUNT_AR6003 32 +#define REGISTER_DUMP_LEN_MAX 38 +#if REG_DUMP_COUNT_AR6001 > REGISTER_DUMP_LEN_MAX +#error "REG_DUMP_COUNT_AR6001 too large" +#endif +#if REG_DUMP_COUNT_AR6002 > REGISTER_DUMP_LEN_MAX +#error "REG_DUMP_COUNT_AR6002 too large" +#endif +#if REG_DUMP_COUNT_AR6003 > REGISTER_DUMP_LEN_MAX +#error "REG_DUMP_COUNT_AR6003 too large" +#endif + + +void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType) +{ + A_UINT32 address; + A_UINT32 regDumpArea = 0; + A_STATUS status; + A_UINT32 regDumpValues[REGISTER_DUMP_LEN_MAX]; + A_UINT32 regDumpCount = 0; + A_UINT32 i; + + do { + + /* the reg dump pointer is copied to the host interest area */ + address = HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_failure_state); + address = TARG_VTOP(TargetType, address); + + if (TargetType == TARGET_TYPE_AR6001) { + /* for AR6001, this is a fixed location because the ptr is actually stuck in cache, + * this may be fixed in later firmware versions */ + address = 0x18a0; + regDumpCount = REG_DUMP_COUNT_AR6001; + } else if (TargetType == TARGET_TYPE_AR6002) { + regDumpCount = REG_DUMP_COUNT_AR6002; + } else if (TargetType == TARGET_TYPE_AR6003) { + regDumpCount = REG_DUMP_COUNT_AR6003; + } else { + A_ASSERT(0); + } + + /* read RAM location through diagnostic window */ + status = ar6000_ReadRegDiag(hifDevice, &address, ®DumpArea); + + if (A_FAILED(status)) { + A_PRINTF("AR6K: Failed to get ptr to register dump area: %d \n", status); + break; + } + + A_PRINTF("AR6K: Location of register dump data: 0x%X \n",regDumpArea); + + if (regDumpArea == 0) { + /* no reg dump */ + break; + } + + regDumpArea = TARG_VTOP(TargetType, regDumpArea); + + /* fetch register dump data */ + status = ar6000_ReadDataDiag(hifDevice, + regDumpArea, + (A_UCHAR *)®DumpValues[0], + regDumpCount * (sizeof(A_UINT32))); + + if (A_FAILED(status)) { + A_PRINTF("AR6K: Failed to get register dump: %d \n", status); + break; + } + A_PRINTF("AR6K: Register Dump: \n"); + + for (i = 0; i < regDumpCount; i++) { + A_PRINTF(" %d : 0x%8.8X \n",i, regDumpValues[i]); +#ifdef UNDER_CE + logPrintf(ATH_DEBUG_ERR," %d: 0x%8.8X \n",i, regDumpValues[i]); +#endif + } + + } while (FALSE); + +} + +/* set HTC/Mbox operational parameters, this can only be called when the target is in the + * BMI phase */ +A_STATUS ar6000_set_htc_params(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 MboxIsrYieldValue, + A_UINT8 HtcControlBuffers) +{ + A_STATUS status; + A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX]; + + do { + /* get the block sizes */ + status = HIFConfigureDevice(hifDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + blocksizes, sizeof(blocksizes)); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_LOG_ERR,("Failed to get block size info from HIF layer...\n")); + break; + } + /* note: we actually get the block size for mailbox 1, for SDIO the block + * size on mailbox 0 is artificially set to 1 */ + /* must be a power of 2 */ + A_ASSERT((blocksizes[1] & (blocksizes[1] - 1)) == 0); + + if (HtcControlBuffers != 0) { + /* set override for number of control buffers to use */ + blocksizes[1] |= ((A_UINT32)HtcControlBuffers) << 16; + } + + /* set the host interest area for the block size */ + status = BMIWriteMemory(hifDevice, + HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz), + (A_UCHAR *)&blocksizes[1], + 4); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for IO block size failed \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_LOG_INF,("Block Size Set: %d (target address:0x%X)\n", + blocksizes[1], HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz))); + + if (MboxIsrYieldValue != 0) { + /* set the host interest area for the mbox ISR yield limit */ + status = BMIWriteMemory(hifDevice, + HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_isr_yield_limit), + (A_UCHAR *)&MboxIsrYieldValue, + 4); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for yield limit failed \n")); + break; + } + } + + } while (FALSE); + + return status; +} + + +static A_STATUS prepare_ar6002(HIF_DEVICE *hifDevice, A_UINT32 TargetVersion) +{ + A_STATUS status = A_OK; + + /* placeholder */ + + return status; +} + +static A_STATUS prepare_ar6003(HIF_DEVICE *hifDevice, A_UINT32 TargetVersion) +{ + A_STATUS status = A_OK; + + /* placeholder */ + + return status; +} + +/* this function assumes the caller has already initialized the BMI APIs */ +A_STATUS ar6000_prepare_target(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 TargetVersion) +{ + if (TargetType == TARGET_TYPE_AR6002) { + /* do any preparations for AR6002 devices */ + return prepare_ar6002(hifDevice,TargetVersion); + } else if (TargetType == TARGET_TYPE_AR6003) { + return prepare_ar6003(hifDevice,TargetVersion); + } + + return A_OK; +} + +#if defined(CONFIG_AR6002_REV1_FORCE_HOST) +/* + * Call this function just before the call to BMIInit + * in order to force* AR6002 rev 1.x firmware to detect a Host. + * THIS IS FOR USE ONLY WITH AR6002 REV 1.x. + * TBDXXX: Remove this function when REV 1.x is desupported. + */ +A_STATUS +ar6002_REV1_reset_force_host (HIF_DEVICE *hifDevice) +{ + A_INT32 i; + struct forceROM_s { + A_UINT32 addr; + A_UINT32 data; + }; + struct forceROM_s *ForceROM; + A_INT32 szForceROM; + A_STATUS status = A_OK; + A_UINT32 address; + A_UINT32 data; + + /* Force AR6002 REV1.x to recognize Host presence. + * + * Note: Use RAM at 0x52df80..0x52dfa0 with ROM Remap entry 0 + * so that this workaround functions with AR6002.war1.sh. We + * could fold that entire workaround into this one, but it's not + * worth the effort at this point. This workaround cannot be + * merged into the other workaround because this must be done + * before BMI. + */ + + static struct forceROM_s ForceROM_NEW[] = { + {0x52df80, 0x20f31c07}, + {0x52df84, 0x92374420}, + {0x52df88, 0x1d120c03}, + {0x52df8c, 0xff8216f0}, + {0x52df90, 0xf01d120c}, + {0x52df94, 0x81004136}, + {0x52df98, 0xbc9100bd}, + {0x52df9c, 0x00bba100}, + + {0x00008000|MC_TCAM_TARGET_ADDRESS, 0x0012dfe0}, /* Use remap entry 0 */ + {0x00008000|MC_TCAM_COMPARE_ADDRESS, 0x000e2380}, + {0x00008000|MC_TCAM_MASK_ADDRESS, 0x00000000}, + {0x00008000|MC_TCAM_VALID_ADDRESS, 0x00000001}, + + {0x00018000|(LOCAL_COUNT_ADDRESS+0x10), 0}, /* clear BMI credit counter */ + + {0x00004000|AR6002_RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK}, + }; + + address = 0x004ed4b0; /* REV1 target software ID is stored here */ + status = ar6000_ReadRegDiag(hifDevice, &address, &data); + if (A_FAILED(status) || (data != AR6002_VERSION_REV1)) { + return A_ERROR; /* Not AR6002 REV1 */ + } + + ForceROM = ForceROM_NEW; + szForceROM = sizeof(ForceROM_NEW)/sizeof(*ForceROM); + + ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Force Target to recognize Host....\n")); + for (i = 0; i < szForceROM; i++) + { + if (ar6000_WriteRegDiag(hifDevice, + &ForceROM[i].addr, + &ForceROM[i].data) != A_OK) + { + ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Cannot force Target to recognize Host!\n")); + return A_ERROR; + } + } + + A_MDELAY(1000); + + return A_OK; +} +#endif /* CONFIG_AR6002_REV1_FORCE_HOST */ + + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/common_drv.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/common_drv.h --- linux-2.6.26/drivers/net/wireless/ath6k22/common_drv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/common_drv.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,79 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef COMMON_DRV_H_ +#define COMMON_DRV_H_ + +#include "hif.h" +#include "htc_packet.h" + +/* structure that is the state information for the default credit distribution callback + * drivers should instantiate (zero-init as well) this structure in their driver instance + * and pass it as a context to the HTC credit distribution functions */ +typedef struct _COMMON_CREDIT_STATE_INFO { + int TotalAvailableCredits; /* total credits in the system at startup */ + int CurrentFreeCredits; /* credits available in the pool that have not been + given out to endpoints */ + HTC_ENDPOINT_CREDIT_DIST *pLowestPriEpDist; /* pointer to the lowest priority endpoint dist struct */ +} COMMON_CREDIT_STATE_INFO; + + +/* HTC TX packet tagging definitions */ +#define AR6K_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED +#define AR6K_DATA_PKT_TAG (AR6K_CONTROL_PKT_TAG + 1) + +#define AR6002_VERSION_REV1 0x20000086 +#define AR6002_VERSION_REV2 0x20000188 + +#ifdef __cplusplus +extern "C" { +#endif + +/* OS-independent APIs */ +A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo); + +A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, A_UCHAR *data, A_UINT32 length); + +A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType, A_BOOL waitForCompletion); + +void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType); + +A_STATUS ar6000_reset_device_skipflash(HIF_DEVICE *hifDevice); + +A_STATUS ar6000_set_htc_params(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 MboxIsrYieldValue, + A_UINT8 HtcControlBuffers); + +A_STATUS ar6000_prepare_target(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 TargetVersion); + +#ifdef __cplusplus +} +#endif + +#endif /*COMMON_DRV_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/config_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/config_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k22/config_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/config_linux.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _CONFIG_LINUX_H_ +#define _CONFIG_LINUX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Host-side GPIO support is optional. + * If run-time access to GPIO pins is not required, then + * this should be changed to #undef. + */ +#define CONFIG_HOST_GPIO_SUPPORT + +/* + * Host side Test Command support + */ +#define CONFIG_HOST_TCMD_SUPPORT + +#define USE_4BYTE_REGISTER_ACCESS + +/* Host-side support for Target-side profiling */ +#undef CONFIG_TARGET_PROFILE_SUPPORT + +#ifdef __cplusplus +} +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/credit_dist.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/credit_dist.c --- linux-2.6.26/drivers/net/wireless/ath6k22/credit_dist.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/credit_dist.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,373 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "a_debug.h" +#include "htc_api.h" +#include "common_drv.h" + +/********* CREDIT DISTRIBUTION FUNCTIONS ******************************************/ + +#define NO_VO_SERVICE 1 /* currently WMI only uses 3 data streams, so we leave VO service inactive */ + +#ifdef NO_VO_SERVICE +#define DATA_SVCS_USED 3 +#else +#define DATA_SVCS_USED 4 +#endif + +static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList); + +static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList); + +/* reduce an ep's credits back to a set limit */ +static INLINE void ReduceCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEpDist, + int Limit) +{ + int credits; + + /* set the new limit */ + pEpDist->TxCreditsAssigned = Limit; + + if (pEpDist->TxCredits <= Limit) { + return; + } + + /* figure out how much to take away */ + credits = pEpDist->TxCredits - Limit; + /* take them away */ + pEpDist->TxCredits -= credits; + pCredInfo->CurrentFreeCredits += credits; +} + +/* give an endpoint some credits from the free credit pool */ +#define GiveCredits(pCredInfo,pEpDist,credits) \ +{ \ + (pEpDist)->TxCredits += (credits); \ + (pEpDist)->TxCreditsAssigned += (credits); \ + (pCredInfo)->CurrentFreeCredits -= (credits); \ +} + + +/* default credit init callback. + * This function is called in the context of HTCStart() to setup initial (application-specific) + * credit distributions */ +static void ar6000_credit_init(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + int TotalCredits) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + int count; + COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context; + + pCredInfo->CurrentFreeCredits = TotalCredits; + pCredInfo->TotalAvailableCredits = TotalCredits; + + pCurEpDist = pEPList; + + /* run through the list and initialize */ + while (pCurEpDist != NULL) { + + /* set minimums for each endpoint */ + pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg; + + if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) { + /* give control service some credits */ + GiveCredits(pCredInfo,pCurEpDist,pCurEpDist->TxCreditsMin); + /* control service is always marked active, it never goes inactive EVER */ + SET_EP_ACTIVE(pCurEpDist); + } else if (pCurEpDist->ServiceID == WMI_DATA_BK_SVC) { + /* this is the lowest priority data endpoint, save this off for easy access */ + pCredInfo->pLowestPriEpDist = pCurEpDist; + } + + /* Streams have to be created (explicit | implicit)for all kinds + * of traffic. BE endpoints are also inactive in the beginning. + * When BE traffic starts it creates implicit streams that + * redistributes credits. + */ + + /* note, all other endpoints have minimums set but are initially given NO credits. + * Credits will be distributed as traffic activity demands */ + pCurEpDist = pCurEpDist->pNext; + } + + if (pCredInfo->CurrentFreeCredits <= 0) { + AR_DEBUG_PRINTF(ATH_LOG_INF, ("Not enough credits (%d) to do credit distributions \n", TotalCredits)); + A_ASSERT(FALSE); + return; + } + + /* reset list */ + pCurEpDist = pEPList; + /* now run through the list and set max operating credit limits for everyone */ + while (pCurEpDist != NULL) { + if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) { + /* control service max is just 1 max message */ + pCurEpDist->TxCreditsNorm = pCurEpDist->TxCreditsPerMaxMsg; + } else { + /* for the remaining data endpoints, we assume that each TxCreditsPerMaxMsg are + * the same. + * We use a simple calculation here, we take the remaining credits and + * determine how many max messages this can cover and then set each endpoint's + * normal value equal to 3/4 this amount. + * */ + count = (pCredInfo->CurrentFreeCredits/pCurEpDist->TxCreditsPerMaxMsg) * pCurEpDist->TxCreditsPerMaxMsg; + count = (count * 3) >> 2; + count = max(count,pCurEpDist->TxCreditsPerMaxMsg); + /* set normal */ + pCurEpDist->TxCreditsNorm = count; + + } + pCurEpDist = pCurEpDist->pNext; + } + +} + + +/* default credit distribution callback + * This callback is invoked whenever endpoints require credit distributions. + * A lock is held while this function is invoked, this function shall NOT block. + * The pEPDistList is a list of distribution structures in prioritized order as + * defined by the call to the HTCSetCreditDistribution() api. + * + */ +static void ar6000_credit_distribute(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList, + HTC_CREDIT_DIST_REASON Reason) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context; + + switch (Reason) { + case HTC_CREDIT_DIST_SEND_COMPLETE : + pCurEpDist = pEPDistList; + /* we are given the start of the endpoint distribution list. + * There may be one or more endpoints to service. + * Run through the list and distribute credits */ + while (pCurEpDist != NULL) { + + if (pCurEpDist->TxCreditsToDist > 0) { + /* return the credits back to the endpoint */ + pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist; + /* always zero out when we are done */ + pCurEpDist->TxCreditsToDist = 0; + + if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsAssigned) { + /* reduce to the assigned limit, previous credit reductions + * could have caused the limit to change */ + ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsAssigned); + } + + if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsNorm) { + /* oversubscribed endpoints need to reduce back to normal */ + ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsNorm); + } + + if (!IS_EP_ACTIVE(pCurEpDist)) { + /* endpoint is inactive, now check for messages waiting for credits */ + if (pCurEpDist->TxQueueDepth == 0) { + /* EP is inactive and there are no pending messages, + * reduce credits back to zero to recover credits */ + ReduceCredits(pCredInfo, pCurEpDist, 0); + } + } + } + + pCurEpDist = pCurEpDist->pNext; + } + + break; + + case HTC_CREDIT_DIST_ACTIVITY_CHANGE : + RedistributeCredits(pCredInfo,pEPDistList); + break; + case HTC_CREDIT_DIST_SEEK_CREDITS : + SeekCredits(pCredInfo,pEPDistList); + break; + case HTC_DUMP_CREDIT_STATE : + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Credit Distribution, total : %d, free : %d\n", + pCredInfo->TotalAvailableCredits, pCredInfo->CurrentFreeCredits)); + break; + default: + break; + + } + + /* sanity checks done after each distribution action */ + A_ASSERT(pCredInfo->CurrentFreeCredits <= pCredInfo->TotalAvailableCredits); + A_ASSERT(pCredInfo->CurrentFreeCredits >= 0); + +} + +/* redistribute credits based on activity change */ +static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist = pEPDistList; + + /* walk through the list and remove credits from inactive endpoints */ + while (pCurEpDist != NULL) { + + if (pCurEpDist->ServiceID != WMI_CONTROL_SVC) { + if (!IS_EP_ACTIVE(pCurEpDist)) { + if (pCurEpDist->TxQueueDepth == 0) { + /* EP is inactive and there are no pending messages, reduce credits back to zero */ + ReduceCredits(pCredInfo, pCurEpDist, 0); + } else { + /* we cannot zero the credits assigned to this EP, but to keep + * the credits available for these leftover packets, reduce to + * a minimum */ + ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsMin); + } + } + } + + /* NOTE in the active case, we do not need to do anything further, + * when an EP goes active and needs credits, HTC will call into + * our distribution function using a reason code of HTC_CREDIT_DIST_SEEK_CREDITS */ + + pCurEpDist = pCurEpDist->pNext; + } + +} + +/* HTC has an endpoint that needs credits, pEPDist is the endpoint in question */ +static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDist) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + int credits = 0; + int need; + + do { + + if (pEPDist->ServiceID == WMI_CONTROL_SVC) { + /* we never oversubscribe on the control service, this is not + * a high performance path and the target never holds onto control + * credits for too long */ + break; + } + + if (pEPDist->ServiceID == WMI_DATA_VI_SVC) { + if (pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm) { + /* limit VI service from oversubscribing */ + break; + } + } + + if (pEPDist->ServiceID == WMI_DATA_VO_SVC) { + if (pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm) { + /* limit VO service from oversubscribing */ + break; + } + } + + /* for all other services, we follow a simple algorithm of + * 1. checking the free pool for credits + * 2. checking lower priority endpoints for credits to take */ + + /* give what we can */ + credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek); + + if (credits >= pEPDist->TxCreditsSeek) { + /* we found some to fullfill the seek request */ + break; + } + + /* we don't have enough in the free pool, try taking away from lower priority services + * + * The rule for taking away credits: + * 1. Only take from lower priority endpoints + * 2. Only take what is allocated above the minimum (never starve an endpoint completely) + * 3. Only take what you need. + * + * */ + + /* starting at the lowest priority */ + pCurEpDist = pCredInfo->pLowestPriEpDist; + + /* work backwards until we hit the endpoint again */ + while (pCurEpDist != pEPDist) { + /* calculate how many we need so far */ + need = pEPDist->TxCreditsSeek - pCredInfo->CurrentFreeCredits; + + if ((pCurEpDist->TxCreditsAssigned - need) >= pCurEpDist->TxCreditsMin) { + /* the current one has been allocated more than it's minimum and it + * has enough credits assigned above it's minimum to fullfill our need + * try to take away just enough to fullfill our need */ + ReduceCredits(pCredInfo, + pCurEpDist, + pCurEpDist->TxCreditsAssigned - need); + + if (pCredInfo->CurrentFreeCredits >= pEPDist->TxCreditsSeek) { + /* we have enough */ + break; + } + } + + pCurEpDist = pCurEpDist->pPrev; + } + + /* return what we can get */ + credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek); + + } while (FALSE); + + /* did we find some credits? */ + if (credits) { + /* give what we can */ + GiveCredits(pCredInfo, pEPDist, credits); + } + +} + +/* initialize and setup credit distribution */ +A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo) +{ + HTC_SERVICE_ID servicepriority[5]; + + A_MEMZERO(pCredInfo,sizeof(COMMON_CREDIT_STATE_INFO)); + + servicepriority[0] = WMI_CONTROL_SVC; /* highest */ + servicepriority[1] = WMI_DATA_VO_SVC; + servicepriority[2] = WMI_DATA_VI_SVC; + servicepriority[3] = WMI_DATA_BE_SVC; + servicepriority[4] = WMI_DATA_BK_SVC; /* lowest */ + + /* set callbacks and priority list */ + HTCSetCreditDistribution(HTCHandle, + pCredInfo, + ar6000_credit_distribute, + ar6000_credit_init, + servicepriority, + 5); + + return A_OK; +} + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/dbglog.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/dbglog.h --- linux-2.6.26/drivers/net/wireless/ath6k22/dbglog.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/dbglog.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,126 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _DBGLOG_H_ +#define _DBGLOG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define DBGLOG_TIMESTAMP_OFFSET 0 +#define DBGLOG_TIMESTAMP_MASK 0x0000FFFF /* Bit 0-15. Contains bit + 8-23 of the LF0 timer */ +#define DBGLOG_DBGID_OFFSET 16 +#define DBGLOG_DBGID_MASK 0x03FF0000 /* Bit 16-25 */ +#define DBGLOG_DBGID_NUM_MAX 256 /* Upper limit is width of mask */ + +#define DBGLOG_MODULEID_OFFSET 26 +#define DBGLOG_MODULEID_MASK 0x3C000000 /* Bit 26-29 */ +#define DBGLOG_MODULEID_NUM_MAX 16 /* Upper limit is width of mask */ + +/* + * Please ensure that the definition of any new module intrduced is captured + * between the DBGLOG_MODULEID_START and DBGLOG_MODULEID_END defines. The + * structure is required for the parser to correctly pick up the values for + * different modules. + */ +#define DBGLOG_MODULEID_START +#define DBGLOG_MODULEID_INF 0 +#define DBGLOG_MODULEID_WMI 1 +#define DBGLOG_MODULEID_CSERV 2 +#define DBGLOG_MODULEID_PM 3 +#define DBGLOG_MODULEID_TXRX_MGMTBUF 4 +#define DBGLOG_MODULEID_TXRX_TXBUF 5 +#define DBGLOG_MODULEID_TXRX_RXBUF 6 +#define DBGLOG_MODULEID_WOW 7 +#define DBGLOG_MODULEID_WHAL 8 +#define DBGLOG_MODULEID_DC 9 +#define DBGLOG_MODULEID_CO 10 +#define DBGLOG_MODULEID_RO 11 +#define DBGLOG_MODULEID_CM 12 +#define DBGLOG_MODULEID_PY 13 +#define DBGLOG_MODULEID_TMR 14 +#define DBGLOG_MODULEID_BTCOEX 15 +#define DBGLOG_MODULEID_END + +#define DBGLOG_NUM_ARGS_OFFSET 30 +#define DBGLOG_NUM_ARGS_MASK 0xC0000000 /* Bit 30-31 */ +#define DBGLOG_NUM_ARGS_MAX 2 /* Upper limit is width of mask */ + +#define DBGLOG_MODULE_LOG_ENABLE_OFFSET 0 +#define DBGLOG_MODULE_LOG_ENABLE_MASK 0x0000FFFF + +#define DBGLOG_REPORTING_ENABLED_OFFSET 16 +#define DBGLOG_REPORTING_ENABLED_MASK 0x00010000 + +#define DBGLOG_TIMESTAMP_RESOLUTION_OFFSET 17 +#define DBGLOG_TIMESTAMP_RESOLUTION_MASK 0x000E0000 + +#define DBGLOG_REPORT_SIZE_OFFSET 20 +#define DBGLOG_REPORT_SIZE_MASK 0x3FF00000 + +#define DBGLOG_LOG_BUFFER_SIZE 1500 +#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90 + +struct dbglog_buf_s { + struct dbglog_buf_s *next; + A_INT8 *buffer; + A_UINT32 bufsize; + A_UINT32 length; + A_UINT32 count; + A_UINT32 free; +}; + +struct dbglog_hdr_s { + struct dbglog_buf_s *dbuf; + A_UINT32 dropped; +}; + +struct dbglog_config_s { + A_UINT32 cfgvalid; /* Mask with valid config bits */ + union { + /* TODO: Take care of endianness */ + struct { + A_UINT32 mmask:16; /* Mask of modules with logging on */ + A_UINT32 rep:1; /* Reporting enabled or not */ + A_UINT32 tsr:3; /* Time stamp resolution. Def: 1 ms */ + A_UINT32 size:10; /* Report size in number of messages */ + A_UINT32 reserved:2; + } dbglog_config; + + A_UINT32 value; + } u; +}; + +#define cfgmmask u.dbglog_config.mmask +#define cfgrep u.dbglog_config.rep +#define cfgtsr u.dbglog_config.tsr +#define cfgsize u.dbglog_config.size +#define cfgvalue u.value + +#ifdef __cplusplus +} +#endif + +#endif /* _DBGLOG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/dbglog_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/dbglog_api.h --- linux-2.6.26/drivers/net/wireless/ath6k22/dbglog_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/dbglog_api.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains host side debug primitives. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _DBGLOG_API_H_ +#define _DBGLOG_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbglog.h" + +#define DBGLOG_HOST_LOG_BUFFER_SIZE DBGLOG_LOG_BUFFER_SIZE + +#define DBGLOG_GET_DBGID(arg) \ + ((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET) + +#define DBGLOG_GET_MODULEID(arg) \ + ((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET) + +#define DBGLOG_GET_NUMARGS(arg) \ + ((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET) + +#define DBGLOG_GET_TIMESTAMP(arg) \ + ((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET) + +#ifdef __cplusplus +} +#endif + +#endif /* _DBGLOG_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/dbglog_id.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/dbglog_id.h --- linux-2.6.26/drivers/net/wireless/ath6k22/dbglog_id.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/dbglog_id.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,505 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _DBGLOG_ID_H_ +#define _DBGLOG_ID_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * The nomenclature for the debug identifiers is MODULE_DESCRIPTION. + * Please ensure that the definition of any new debugid introduced is captured + * between the _DBGID_DEFINITION_START and + * _DBGID_DEFINITION_END defines. The structure is required for the + * parser to correctly pick up the values for different debug identifiers. + */ + +/* INF debug identifier definitions */ +#define INF_DBGID_DEFINITION_START +#define INF_ASSERTION_FAILED 1 +#define INF_TARGET_ID 2 +#define INF_DBGID_DEFINITION_END + +/* WMI debug identifier definitions */ +#define WMI_DBGID_DEFINITION_START +#define WMI_CMD_RX_XTND_PKT_TOO_SHORT 1 +#define WMI_EXTENDED_CMD_NOT_HANDLED 2 +#define WMI_CMD_RX_PKT_TOO_SHORT 3 +#define WMI_CALLING_WMI_EXTENSION_FN 4 +#define WMI_CMD_NOT_HANDLED 5 +#define WMI_IN_SYNC 6 +#define WMI_TARGET_WMI_SYNC_CMD 7 +#define WMI_SET_SNR_THRESHOLD_PARAMS 8 +#define WMI_SET_RSSI_THRESHOLD_PARAMS 9 +#define WMI_SET_LQ_TRESHOLD_PARAMS 10 +#define WMI_TARGET_CREATE_PSTREAM_CMD 11 +#define WMI_WI_DTM_INUSE 12 +#define WMI_TARGET_DELETE_PSTREAM_CMD 13 +#define WMI_TARGET_IMPLICIT_DELETE_PSTREAM_CMD 14 +#define WMI_TARGET_GET_BIT_RATE_CMD 15 +#define WMI_GET_RATE_MASK_CMD_FIX_RATE_MASK_IS 16 +#define WMI_TARGET_GET_AVAILABLE_CHANNELS_CMD 17 +#define WMI_TARGET_GET_TX_PWR_CMD 18 +#define WMI_FREE_EVBUF_WMIBUF 19 +#define WMI_FREE_EVBUF_DATABUF 20 +#define WMI_FREE_EVBUF_BADFLAG 21 +#define WMI_HTC_RX_ERROR_DATA_PACKET 22 +#define WMI_HTC_RX_SYNC_PAUSING_FOR_MBOX 23 +#define WMI_INCORRECT_WMI_DATA_HDR_DROPPING_PKT 24 +#define WMI_SENDING_READY_EVENT 25 +#define WMI_SETPOWER_MDOE_TO_MAXPERF 26 +#define WMI_SETPOWER_MDOE_TO_REC 27 +#define WMI_BSSINFO_EVENT_FROM 28 +#define WMI_TARGET_GET_STATS_CMD 29 +#define WMI_SENDING_SCAN_COMPLETE_EVENT 30 +#define WMI_SENDING_RSSI_INDB_THRESHOLD_EVENT 31 +#define WMI_SENDING_RSSI_INDBM_THRESHOLD_EVENT 32 +#define WMI_SENDING_LINK_QUALITY_THRESHOLD_EVENT 33 +#define WMI_SENDING_ERROR_REPORT_EVENT 34 +#define WMI_SENDING_CAC_EVENT 35 +#define WMI_TARGET_GET_ROAM_TABLE_CMD 36 +#define WMI_TARGET_GET_ROAM_DATA_CMD 37 +#define WMI_SENDING_GPIO_INTR_EVENT 38 +#define WMI_SENDING_GPIO_ACK_EVENT 39 +#define WMI_SENDING_GPIO_DATA_EVENT 40 +#define WMI_CMD_RX 41 +#define WMI_CMD_RX_XTND 42 +#define WMI_EVENT_SEND 43 +#define WMI_EVENT_SEND_XTND 44 +#define WMI_CMD_PARAMS_DUMP_START 45 +#define WMI_CMD_PARAMS_DUMP_END 46 +#define WMI_CMD_PARAMS 47 +#define WMI_DBGID_DEFINITION_END + +/* CSERV debug identifier definitions */ +#define CSERV_DBGID_DEFINITION_START +#define CSERV_BEGIN_SCAN1 1 +#define CSERV_BEGIN_SCAN2 2 +#define CSERV_END_SCAN1 3 +#define CSERV_END_SCAN2 4 +#define CSERV_CHAN_SCAN_START 5 +#define CSERV_CHAN_SCAN_STOP 6 +#define CSERV_CHANNEL_OPPPORTUNITY 7 +#define CSERV_NC_TIMEOUT 8 +#define CSERV_BACK_HOME 10 +#define CSERV_CHMGR_CH_CALLBACK1 11 +#define CSERV_CHMGR_CH_CALLBACK2 12 +#define CSERV_CHMGR_CH_CALLBACK3 13 +#define CSERV_SET_SCAN_PARAMS1 14 +#define CSERV_SET_SCAN_PARAMS2 15 +#define CSERV_SET_SCAN_PARAMS3 16 +#define CSERV_SET_SCAN_PARAMS4 17 +#define CSERV_ABORT_SCAN 18 +#define CSERV_NEWSTATE 19 +#define CSERV_MINCHMGR_OP_END 20 +#define CSERV_CHMGR_OP_END 21 +#define CSERV_DISCONNECT_TIMEOUT 22 +#define CSERV_ROAM_TIMEOUT 23 +#define CSERV_FORCE_SCAN1 24 +#define CSERV_FORCE_SCAN2 25 +#define CSERV_FORCE_SCAN3 26 +#define CSERV_UTIL_TIMEOUT 27 +#define CSERV_RSSIPOLLER 28 +#define CSERV_RETRY_CONNECT_TIMEOUT 29 +#define CSERV_RSSIINDBMPOLLER 30 +#define CSERV_BGSCAN_ENABLE 31 +#define CSERV_BGSCAN_DISABLE 32 +#define CSERV_WLAN_START_SCAN_CMD1 33 +#define CSERV_WLAN_START_SCAN_CMD2 34 +#define CSERV_WLAN_START_SCAN_CMD3 35 +#define CSERV_START_SCAN_CMD 36 +#define CSERV_START_FORCE_SCAN 37 +#define CSERV_NEXT_CHAN 38 +#define CSERV_SET_REGCODE 39 +#define CSERV_START_ADHOC 40 +#define CSERV_ADHOC_AT_HOME 41 +#define CSERV_OPT_AT_HOME 42 +#define CSERV_WLAN_CONNECT_CMD 43 +#define CSERV_WLAN_RECONNECT_CMD 44 +#define CSERV_WLAN_DISCONNECT_CMD 45 +#define CSERV_BSS_CHANGE_CHANNEL 46 +#define CSERV_BEACON_RX 47 +#define CSERV_KEEPALIVE_CHECK 48 +#define CSERV_RC_BEGIN_SCAN 49 +#define CSERV_RC_SCAN_START 50 +#define CSERV_RC_SCAN_STOP 51 +#define CSERV_RC_NEXT 52 +#define CSERV_RC_SCAN_END 53 +#define CSERV_PROBE_CALLBACK 54 +#define CSERV_ROAM1 55 +#define CSERV_ROAM2 56 +#define CSERV_ROAM3 57 +#define CSERV_CONNECT_EVENT 58 +#define CSERV_DISCONNECT_EVENT 59 +#define CSERV_BMISS_HANDLER1 60 +#define CSERV_BMISS_HANDLER2 61 +#define CSERV_BMISS_HANDLER3 62 +#define CSERV_LOWRSSI_HANDLER 63 +#define CSERV_WLAN_SET_PMKID_CMD 64 +#define CSERV_RECONNECT_REQUEST 65 +#define CSERV_KEYSPLUMBED_EVENT 66 +#define CSERV_NEW_REG 67 +#define CSERV_SET_RSSI_THOLD 68 +#define CSERV_RSSITHRESHOLDCHECK 69 +#define CSERV_RSSIINDBMTHRESHOLDCHECK 70 +#define CSERV_WLAN_SET_OPT_CMD1 71 +#define CSERV_WLAN_SET_OPT_CMD2 72 +#define CSERV_WLAN_SET_OPT_CMD3 73 +#define CSERV_WLAN_SET_OPT_CMD4 74 +#define CSERV_SCAN_CONNECT_STOP 75 +#define CSERV_BMISS_HANDLER4 76 +#define CSERV_INITIALIZE_TIMER 77 +#define CSERV_ARM_TIMER 78 +#define CSERV_DISARM_TIMER 79 +#define CSERV_UNINITIALIZE_TIMER 80 +#define CSERV_DISCONNECT_EVENT2 81 +#define CSERV_SCAN_CONNECT_START 82 +#define CSERV_BSSINFO_MEMORY_ALLOC_FAILED 83 +#define CSERV_SET_SCAN_PARAMS5 84 +#define CSERV_DBGID_DEFINITION_END + +/* TXRX debug identifier definitions */ +#define TXRX_TXBUF_DBGID_DEFINITION_START +#define TXRX_TXBUF_ALLOCATE_BUF 1 +#define TXRX_TXBUF_QUEUE_BUF_TO_MBOX 2 +#define TXRX_TXBUF_QUEUE_BUF_TO_TXQ 3 +#define TXRX_TXBUF_TXQ_DEPTH 4 +#define TXRX_TXBUF_IBSS_QUEUE_TO_SFQ 5 +#define TXRX_TXBUF_IBSS_QUEUE_TO_TXQ_FRM_SFQ 6 +#define TXRX_TXBUF_INITIALIZE_TIMER 7 +#define TXRX_TXBUF_ARM_TIMER 8 +#define TXRX_TXBUF_DISARM_TIMER 9 +#define TXRX_TXBUF_UNINITIALIZE_TIMER 10 +#define TXRX_TXBUF_DBGID_DEFINITION_END + +#define TXRX_RXBUF_DBGID_DEFINITION_START +#define TXRX_RXBUF_ALLOCATE_BUF 1 +#define TXRX_RXBUF_QUEUE_TO_HOST 2 +#define TXRX_RXBUF_QUEUE_TO_WLAN 3 +#define TXRX_RXBUF_ZERO_LEN_BUF 4 +#define TXRX_RXBUF_QUEUE_TO_HOST_LASTBUF_IN_RXCHAIN 5 +#define TXRX_RXBUF_LASTBUF_IN_RXCHAIN_ZEROBUF 6 +#define TXRX_RXBUF_QUEUE_EMPTY_QUEUE_TO_WLAN 7 +#define TXRX_RXBUF_SEND_TO_RECV_MGMT 8 +#define TXRX_RXBUF_SEND_TO_IEEE_LAYER 9 +#define TXRX_RXBUF_DBGID_DEFINITION_END + +#define TXRX_MGMTBUF_DBGID_DEFINITION_START +#define TXRX_MGMTBUF_ALLOCATE_BUF 1 +#define TXRX_MGMTBUF_ALLOCATE_SM_BUF 2 +#define TXRX_MGMTBUF_ALLOCATE_RMBUF 3 +#define TXRX_MGMTBUF_GET_BUF 4 +#define TXRX_MGMTBUF_GET_SM_BUF 5 +#define TXRX_MGMTBUF_QUEUE_BUF_TO_TXQ 6 +#define TXRX_MGMTBUF_REAPED_BUF 7 +#define TXRX_MGMTBUF_REAPED_SM_BUF 8 +#define TXRX_MGMTBUF_WAIT_FOR_TXQ_DRAIN 9 +#define TXRX_MGMTBUF_WAIT_FOR_TXQ_SFQ_DRAIN 10 +#define TXRX_MGMTBUF_ENQUEUE_INTO_DATA_SFQ 11 +#define TXRX_MGMTBUF_DEQUEUE_FROM_DATA_SFQ 12 +#define TXRX_MGMTBUF_PAUSE_DATA_TXQ 13 +#define TXRX_MGMTBUF_RESUME_DATA_TXQ 14 +#define TXRX_MGMTBUF_WAIT_FORTXQ_DRAIN_TIMEOUT 15 +#define TXRX_MGMTBUF_DRAINQ 16 +#define TXRX_MGMTBUF_INDICATE_Q_DRAINED 17 +#define TXRX_MGMTBUF_ENQUEUE_INTO_HW_SFQ 18 +#define TXRX_MGMTBUF_DEQUEUE_FROM_HW_SFQ 19 +#define TXRX_MGMTBUF_PAUSE_HW_TXQ 20 +#define TXRX_MGMTBUF_RESUME_HW_TXQ 21 +#define TXRX_MGMTBUF_DBGID_DEFINITION_END + +/* PM (Power Module) debug identifier definitions */ +#define PM_DBGID_DEFINITION_START +#define PM_INIT 1 +#define PM_ENABLE 2 +#define PM_SET_STATE 3 +#define PM_SET_POWERMODE 4 +#define PM_CONN_NOTIFY 5 +#define PM_REF_COUNT_NEGATIVE 6 +#define PM_APSD_ENABLE 7 +#define PM_UPDATE_APSD_STATE 8 +#define PM_CHAN_OP_REQ 9 +#define PM_SET_MY_BEACON_POLICY 10 +#define PM_SET_ALL_BEACON_POLICY 11 +#define PM_SET_PM_PARAMS1 12 +#define PM_SET_PM_PARAMS2 13 +#define PM_ADHOC_SET_PM_CAPS_FAIL 14 +#define PM_ADHOC_UNKNOWN_IBSS_ATTRIB_ID 15 +#define PM_DBGID_DEFINITION_END + +/* Wake on Wireless debug identifier definitions */ +#define WOW_DBGID_DEFINITION_START +#define WOW_INIT 1 +#define WOW_GET_CONFIG_DSET 2 +#define WOW_NO_CONFIG_DSET 3 +#define WOW_INVALID_CONFIG_DSET 4 +#define WOW_USE_DEFAULT_CONFIG 5 +#define WOW_SETUP_GPIO 6 +#define WOW_INIT_DONE 7 +#define WOW_SET_GPIO_PIN 8 +#define WOW_CLEAR_GPIO_PIN 9 +#define WOW_SET_WOW_MODE_CMD 10 +#define WOW_SET_HOST_MODE_CMD 11 +#define WOW_ADD_WOW_PATTERN_CMD 12 +#define WOW_NEW_WOW_PATTERN_AT_INDEX 13 +#define WOW_DEL_WOW_PATTERN_CMD 14 +#define WOW_LIST_CONTAINS_PATTERNS 15 +#define WOW_GET_WOW_LIST_CMD 16 +#define WOW_INVALID_FILTER_ID 17 +#define WOW_INVALID_FILTER_LISTID 18 +#define WOW_NO_VALID_FILTER_AT_ID 19 +#define WOW_NO_VALID_LIST_AT_ID 20 +#define WOW_NUM_PATTERNS_EXCEEDED 21 +#define WOW_NUM_LISTS_EXCEEDED 22 +#define WOW_GET_WOW_STATS 23 +#define WOW_CLEAR_WOW_STATS 24 +#define WOW_WAKEUP_HOST 25 +#define WOW_EVENT_WAKEUP_HOST 26 +#define WOW_EVENT_DISCARD 27 +#define WOW_PATTERN_MATCH 28 +#define WOW_PATTERN_NOT_MATCH 29 +#define WOW_PATTERN_NOT_MATCH_OFFSET 30 +#define WOW_DISABLED_HOST_ASLEEP 31 +#define WOW_ENABLED_HOST_ASLEEP_NO_PATTERNS 32 +#define WOW_ENABLED_HOST_ASLEEP_NO_MATCH_FOUND 33 +#define WOW_DBGID_DEFINITION_END + +/* WHAL debug identifier definitions */ +#define WHAL_DBGID_DEFINITION_START +#define WHAL_ERROR_ANI_CONTROL 1 +#define WHAL_ERROR_CHIP_TEST1 2 +#define WHAL_ERROR_CHIP_TEST2 3 +#define WHAL_ERROR_EEPROM_CHECKSUM 4 +#define WHAL_ERROR_EEPROM_MACADDR 5 +#define WHAL_ERROR_INTERRUPT_HIU 6 +#define WHAL_ERROR_KEYCACHE_RESET 7 +#define WHAL_ERROR_KEYCACHE_SET 8 +#define WHAL_ERROR_KEYCACHE_TYPE 9 +#define WHAL_ERROR_KEYCACHE_TKIPENTRY 10 +#define WHAL_ERROR_KEYCACHE_WEPLENGTH 11 +#define WHAL_ERROR_PHY_INVALID_CHANNEL 12 +#define WHAL_ERROR_POWER_AWAKE 13 +#define WHAL_ERROR_POWER_SET 14 +#define WHAL_ERROR_RECV_STOPDMA 15 +#define WHAL_ERROR_RECV_STOPPCU 16 +#define WHAL_ERROR_RESET_CHANNF1 17 +#define WHAL_ERROR_RESET_CHANNF2 18 +#define WHAL_ERROR_RESET_PM 19 +#define WHAL_ERROR_RESET_OFFSETCAL 20 +#define WHAL_ERROR_RESET_RFGRANT 21 +#define WHAL_ERROR_RESET_RXFRAME 22 +#define WHAL_ERROR_RESET_STOPDMA 23 +#define WHAL_ERROR_RESET_RECOVER 24 +#define WHAL_ERROR_XMIT_COMPUTE 25 +#define WHAL_ERROR_XMIT_NOQUEUE 26 +#define WHAL_ERROR_XMIT_ACTIVEQUEUE 27 +#define WHAL_ERROR_XMIT_BADTYPE 28 +#define WHAL_DBGID_DEFINITION_END + +/* DC debug identifier definitions */ +#define DC_DBGID_DEFINITION_START +#define DC_SCAN_CHAN_START 1 +#define DC_SCAN_CHAN_FINISH 2 +#define DC_BEACON_RECEIVE7 3 +#define DC_SSID_PROBE_CB 4 +#define DC_SEND_NEXT_SSID_PROBE 5 +#define DC_START_SEARCH 6 +#define DC_CANCEL_SEARCH_CB 7 +#define DC_STOP_SEARCH 8 +#define DC_END_SEARCH 9 +#define DC_MIN_CHDWELL_TIMEOUT 10 +#define DC_START_SEARCH_CANCELED 11 +#define DC_SET_POWER_MODE 12 +#define DC_INIT 13 +#define DC_SEARCH_OPPORTUNITY 14 +#define DC_RECEIVED_ANY_BEACON 15 +#define DC_RECEIVED_MY_BEACON 16 +#define DC_PROFILE_IS_ADHOC_BUT_BSS_IS_INFRA 17 +#define DC_PS_ENABLED_BUT_ATHEROS_IE_ABSENT 18 +#define DC_BSS_ADHOC_CHANNEL_NOT_ALLOWED 19 +#define DC_SET_BEACON_UPDATE 20 +#define DC_BEACON_UPDATE_COMPLETE 21 +#define DC_END_SEARCH_BEACON_UPDATE_COMP_CB 22 +#define DC_BSSINFO_EVENT_DROPPED 23 +#define DC_DBGID_DEFINITION_END + +/* CO debug identifier definitions */ +#define CO_DBGID_DEFINITION_START +#define CO_INIT 1 +#define CO_ACQUIRE_LOCK 2 +#define CO_START_OP1 3 +#define CO_START_OP2 4 +#define CO_DRAIN_TX_COMPLETE_CB 5 +#define CO_CHANGE_CHANNEL_CB 6 +#define CO_RETURN_TO_HOME_CHANNEL 7 +#define CO_FINISH_OP_TIMEOUT 8 +#define CO_OP_END 9 +#define CO_CANCEL_OP 10 +#define CO_CHANGE_CHANNEL 11 +#define CO_RELEASE_LOCK 12 +#define CO_CHANGE_STATE 13 +#define CO_DBGID_DEFINITION_END + +/* RO debug identifier definitions */ +#define RO_DBGID_DEFINITION_START +#define RO_REFRESH_ROAM_TABLE 1 +#define RO_UPDATE_ROAM_CANDIDATE 2 +#define RO_UPDATE_ROAM_CANDIDATE_CB 3 +#define RO_UPDATE_ROAM_CANDIDATE_FINISH 4 +#define RO_REFRESH_ROAM_TABLE_DONE 5 +#define RO_PERIODIC_SEARCH_CB 6 +#define RO_PERIODIC_SEARCH_TIMEOUT 7 +#define RO_INIT 8 +#define RO_BMISS_STATE1 9 +#define RO_BMISS_STATE2 10 +#define RO_SET_PERIODIC_SEARCH_ENABLE 11 +#define RO_SET_PERIODIC_SEARCH_DISABLE 12 +#define RO_ENABLE_SQ_THRESHOLD 13 +#define RO_DISABLE_SQ_THRESHOLD 14 +#define RO_ADD_BSS_TO_ROAM_TABLE 15 +#define RO_SET_PERIODIC_SEARCH_MODE 16 +#define RO_CONFIGURE_SQ_THRESHOLD1 17 +#define RO_CONFIGURE_SQ_THRESHOLD2 18 +#define RO_CONFIGURE_SQ_PARAMS 19 +#define RO_LOW_SIGNAL_QUALITY_EVENT 20 +#define RO_HIGH_SIGNAL_QUALITY_EVENT 21 +#define RO_REMOVE_BSS_FROM_ROAM_TABLE 22 +#define RO_UPDATE_CONNECTION_STATE_METRIC 23 +#define RO_LOWRSSI_SCAN_PARAMS 24 +#define RO_LOWRSSI_SCAN_START 25 +#define RO_LOWRSSI_SCAN_END 26 +#define RO_LOWRSSI_SCAN_CANCEL 27 +#define RO_LOWRSSI_ROAM_CANCEL 28 +#define RO_DBGID_DEFINITION_END + +/* CM debug identifier definitions */ +#define CM_DBGID_DEFINITION_START +#define CM_INITIATE_HANDOFF 1 +#define CM_INITIATE_HANDOFF_CB 2 +#define CM_CONNECT_EVENT 3 +#define CM_DISCONNECT_EVENT 4 +#define CM_INIT 5 +#define CM_HANDOFF_SOURCE 6 +#define CM_SET_HANDOFF_TRIGGERS 7 +#define CM_CONNECT_REQUEST 8 +#define CM_CONNECT_REQUEST_CB 9 +#define CM_CONTINUE_SCAN_CB 10 +#define CM_DBGID_DEFINITION_END + +/* PY debug identifier definitions */ +#define PY_DBGID_DEFINITION_START +#define PY_DEVICE_DISCOVER 1 +#define PY_DEVICE_CONNECT 2 +#define PY_DEVICE_DISCONNECT 3 +#define PY_CONNECT_NOTIFY 4 +#define PY_DATA_WINDOW_NOTIFY 5 +#define PY_CANCEL_OP 6 +#define PY_DISCOVERY_WINDOW_NOTIFY 7 +#define PY_PROCESS_PYXIS_MSGTYPE 8 +#define PY_SEND_PYXIS_MSGTYPE 9 +#define PY_DBGID_DEFINITION_END + +/* TMR debug identifier definitions */ +#define TMR_DBGID_DEFINITION_START +#define TMR_HANG_DETECTED 1 +#define TMR_WDT_TRIGGERED 2 +#define TMR_WDT_RESET 3 +#define TMR_HANDLER_ENTRY 4 +#define TMR_HANDLER_EXIT 5 +#define TMR_SAVED_START 6 +#define TMR_SAVED_END 7 +#define TMR_DBGID_DEFINITION_END + +/* BTCOEX debug identifier definitions */ +#define BTCOEX_DBGID_DEFINITION_START +#define BTCOEX_STATUS_CMD 1 +#define BTCOEX_PARAMS_CMD 2 +#define BTCOEX_ANT_CONFIG 3 +#define BTCOEX_COLOCATED_BT_DEVICE 4 +#define BTCOEX_CLOSE_RANGE_SCO_ON 5 +#define BTCOEX_CLOSE_RANGE_SCO_OFF 6 +#define BTCOEX_CLOSE_RANGE_A2DP_ON 7 +#define BTCOEX_CLOSE_RANGE_A2DP_OFF 8 +#define BTCOEX_A2DP_PROTECT_ON 9 +#define BTCOEX_A2DP_PROTECT_OFF 10 +#define BTCOEX_SCO_PROTECT_ON 11 +#define BTCOEX_SCO_PROTECT_OFF 12 +#define BTCOEX_CLOSE_RANGE_DETECTOR_START 13 +#define BTCOEX_CLOSE_RANGE_DETECTOR_STOP 14 +#define BTCOEX_CLOSE_RANGE_TOGGLE 15 +#define BTCOEX_CLOSE_RANGE_TOGGLE_RSSI_LRCNT 16 +#define BTCOEX_CLOSE_RANGE_RSSI_THRESH 17 +#define BTCOEX_CLOSE_RANGE_LOW_RATE_THRESH 18 +#define BTCOEX_WEIGHTS 19 +#define BTCOEX_A2DP_DWNLINK 20 +#define BTCOEX_BMISS_PROTECT 21 +#define BTCOEX_BMISS_PROTECT_OFF 22 +#define BTCOEX_DATA_RES_TIMEOUT 23 +#define BTCOEX_DATA_ACTIVITY_TIMEOUT_HANDLER 24 +#define BTCOEX_BCN_INTRVL_TIMEOUT 25 +#define BTCOEX_A2DP_TRIGGER 26 +#define BTCOEX_OBS_REG 27 +#define BTCOEX_PHY_REG 28 +#define BTCOEX_RESET_RADIO 29 +#define BTCOEX_BMISS_NOTIFY 30 +#define BTCOEX_PSPOLL_CALLBACK 31 +#define BTCOEX_WLAN_STATE 32 +#define BTCOEX_CONNECT_START 33 +#define BTCOEX_SCAN_START 34 +#define BTCOEX_SCAN_END 35 +#define BTCOEX_RESET_WHAL 36 +#define BTCOEX_RX_FRAME_COUNTER 37 +#define BTCOEX_RX_FRAME_CLR_CNTR 38 +#define BTCOEX_RX_DP 39 +#define BTCOEX_RX_ABRT 40 +#define BTCOEX_RX_FRAME_SET_CNT 41 +#define BTCOEX_AGCCCA_REG 42 +#define BTCOEX_RSSI_REG 43 +#define BTCOEX_A2DP_PARAM_VAL 44 +#define BTCOEX_MODE 45 +#define BTCOEX_SEND_PSPOLL 46 +#define BTCOEX_SET_UPLINK_RATE 47 +#define BTCOEX_SLEEP_STATUS 48 +#define BTCOEX_RECONNECT_REQ 49 +#define BTCOEX_RECEIVE_NOTIFY 50 +#define BTCOEX_PACKET_COUNT 51 +#define BTCOEX_A2DP_START_WLAN_TRIG 52 +#define BTCOEX_A2DP_HANDLER_TRIG 53 +#define BTCOEX_PM_AWAKE_CNT 54 +#define BTCOEX_PM_SLEEP_CNT 55 +#define BTCOEX_BB_REG 56 +#define BTCOEX_MAC_REG 57 +#define BTCOEX_ACL_PARAM_VAL 58 +#define BTCOEX_SCO_HOST_BOUNDS 60 +#define BTCOEX_A2DP_HOST_BOUNDS 61 +#define BTCOEX_CLOSE_RANGE_BOUNDS 62 +#define BTCOEX_TOGGLE_VALUES 63 +#define BTCOEX_DBGID_DEFINITION_END + +#ifdef __cplusplus +} +#endif + +#endif /* _DBGLOG_ID_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/debug_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/debug_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k22/debug_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/debug_linux.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2004-2006 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _DEBUG_LINUX_H_ +#define _DEBUG_LINUX_H_ + +#define DBG_DEFAULTS (DBG_ERROR|DBG_WARNING) + +extern A_UINT32 g_dbg_flags; + +#define DBGFMT "%s() : " +#define DBGARG __func__ +#define DBGFN A_PRINTF + +#define ATHR_DISPLAY_MSG printk +#define _T(x) x + +/* ------- Debug related stuff ------- */ +enum { + ATH_DEBUG_SEND = 0x0001, + ATH_DEBUG_RECV = 0x0002, + ATH_DEBUG_SYNC = 0x0004, + ATH_DEBUG_DUMP = 0x0008, + ATH_DEBUG_IRQ = 0x0010, + ATH_DEBUG_TRC = 0x0020, + ATH_DEBUG_WARN = 0x0040, + ATH_DEBUG_ERR = 0x0080, + ATH_LOG_INF = 0x0100, + ATH_DEBUG_BMI = 0x0110, + ATH_DEBUG_WMI = 0x0120, + ATH_DEBUG_HIF = 0x0140, + ATH_DEBUG_HTC = 0x0180, + ATH_DEBUG_WLAN = 0x1000, + ATH_LOG_ERR = 0x1010, + ATH_DEBUG_ANY = 0xFFFF, +}; + +#ifdef DEBUG +#define A_DPRINTF(f, a) \ + if(g_dbg_flags & (f)) \ + { \ + DBGFN a ; \ + } + + +// TODO FIX usage of A_PRINTF! +#define AR_DEBUG_LVL_CHECK(lvl) (debughtc & (lvl)) +#define AR_DEBUG_PRINTBUF(buffer, length, desc) do { \ + if (debughtc & ATH_DEBUG_DUMP) { \ + DebugDumpBytes(buffer, length,desc); \ + } \ +} while(0) +#define PRINTX_ARG(arg...) arg +#define AR_DEBUG_PRINTF(flags, args) do { \ + if (debughtc & (flags)) { \ + A_PRINTF(KERN_ALERT PRINTX_ARG args); \ + } \ +} while (0) +#define AR_DEBUG_ASSERT(test) do { \ + if (!(test)) { \ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test)); \ + } \ +} while(0) +extern int debughtc; +#else +#define AR_DEBUG_PRINTF(flags, args) +#define AR_DEBUG_PRINTBUF(buffer, length, desc) +#define AR_DEBUG_ASSERT(test) +#define AR_DEBUG_LVL_CHECK(lvl) 0 +#define A_DPRINTF(f, a) +#endif + +#endif /* _DEBUG_LINUX_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/discovery.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/discovery.h --- linux-2.6.26/drivers/net/wireless/ath6k22/discovery.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/discovery.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,74 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _DISCOVERY_H_ +#define _DISCOVERY_H_ + +/* + * DC_SCAN_PRIORITY is an 8-bit bitmap of the scan priority of a channel + */ +typedef enum { + DEFAULT_SCPRI = 0x01, + POPULAR_SCPRI = 0x02, + SSIDS_SCPRI = 0x04, + PROF_SCPRI = 0x08, +} DC_SCAN_PRIORITY; + +/* The following search type construct can be used to manipulate the behavior of the search module based on different bits set */ +typedef enum { + SCAN_RESET = 0, + SCAN_ALL = (DEFAULT_SCPRI | POPULAR_SCPRI | \ + SSIDS_SCPRI | PROF_SCPRI), + + SCAN_POPULAR = (POPULAR_SCPRI | SSIDS_SCPRI | PROF_SCPRI), + SCAN_SSIDS = (SSIDS_SCPRI | PROF_SCPRI), + SCAN_PROF_MASK = (PROF_SCPRI), + SCAN_MULTI_CHANNEL = 0x000100, + SCAN_DETERMINISTIC = 0x000200, + SCAN_PROFILE_MATCH_TERMINATED = 0x000400, + SCAN_HOME_CHANNEL_SKIP = 0x000800, + SCAN_CHANNEL_LIST_CONTINUE = 0x001000, + SCAN_CURRENT_SSID_SKIP = 0x002000, + SCAN_ACTIVE_PROBE_DISABLE = 0x004000, + SCAN_CHANNEL_HINT_ONLY = 0x008000, + SCAN_ACTIVE_CHANNELS_ONLY = 0x010000, + SCAN_PYXIS_DISCOVERY = 0x020000, + SCAN_PERIODIC = 0x040200, + SCAN_FIXED_DURATION = 0x080000, +} DC_SCAN_TYPE; + +typedef enum { + BSS_REPORTING_DEFAULT = 0x0, + EXCLUDE_NON_SCAN_RESULTS = 0x1, /* Exclude results outside of scan */ +} DC_BSS_REPORTING_POLICY; + +typedef enum { + DC_IGNORE_WPAx_GROUP_CIPHER = 0x01, + DC_PROFILE_MATCH_DONE = 0x02, + DC_IGNORE_AAC_BEACON = 0x04, + DC_CSA_FOLLOW_BSS = 0x08, +} DC_PROFILE_FILTER; + +#define DEFAULT_DC_PROFILE_FILTER (DC_CSA_FOLLOW_BSS) + +#endif /* _DISCOVERY_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/dl_list.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/dl_list.h --- linux-2.6.26/drivers/net/wireless/ath6k22/dl_list.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/dl_list.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,119 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Double-link list definitions (adapted from Atheros SDIO stack) +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef __DL_LIST_H___ +#define __DL_LIST_H___ + + +#define A_CONTAINING_STRUCT(address, struct_type, field_name)\ + ((struct_type *)((A_UINT32)(address) - (A_UINT32)(&((struct_type *)0)->field_name))) + +/* list functions */ +/* pointers for the list */ +typedef struct _DL_LIST { + struct _DL_LIST *pPrev; + struct _DL_LIST *pNext; +}DL_LIST, *PDL_LIST; +/* + * DL_LIST_INIT , initialize doubly linked list +*/ +#define DL_LIST_INIT(pList)\ + {(pList)->pPrev = pList; (pList)->pNext = pList;} + +#define DL_LIST_IS_EMPTY(pList) (((pList)->pPrev == (pList)) && ((pList)->pNext == (pList))) +#define DL_LIST_GET_ITEM_AT_HEAD(pList) (pList)->pNext +#define DL_LIST_GET_ITEM_AT_TAIL(pList) (pList)->pPrev +/* + * ITERATE_OVER_LIST pStart is the list, pTemp is a temp list member + * NOT: do not use this function if the items in the list are deleted inside the + * iteration loop +*/ +#define ITERATE_OVER_LIST(pStart, pTemp) \ + for((pTemp) =(pStart)->pNext; pTemp != (pStart); (pTemp) = (pTemp)->pNext) + + +/* safe iterate macro that allows the item to be removed from the list + * the iteration continues to the next item in the list + */ +#define ITERATE_OVER_LIST_ALLOW_REMOVE(pStart,pItem,st,offset) \ +{ \ + PDL_LIST pTemp; \ + pTemp = (pStart)->pNext; \ + while (pTemp != (pStart)) { \ + (pItem) = A_CONTAINING_STRUCT(pTemp,st,offset); \ + pTemp = pTemp->pNext; \ + +#define ITERATE_END }} + +/* + * DL_ListInsertTail - insert pAdd to the end of the list +*/ +static INLINE PDL_LIST DL_ListInsertTail(PDL_LIST pList, PDL_LIST pAdd) { + /* insert at tail */ + pAdd->pPrev = pList->pPrev; + pAdd->pNext = pList; + pList->pPrev->pNext = pAdd; + pList->pPrev = pAdd; + return pAdd; +} + +/* + * DL_ListInsertHead - insert pAdd into the head of the list +*/ +static INLINE PDL_LIST DL_ListInsertHead(PDL_LIST pList, PDL_LIST pAdd) { + /* insert at head */ + pAdd->pPrev = pList; + pAdd->pNext = pList->pNext; + pList->pNext->pPrev = pAdd; + pList->pNext = pAdd; + return pAdd; +} + +#define DL_ListAdd(pList,pItem) DL_ListInsertHead((pList),(pItem)) +/* + * DL_ListRemove - remove pDel from list +*/ +static INLINE PDL_LIST DL_ListRemove(PDL_LIST pDel) { + pDel->pNext->pPrev = pDel->pPrev; + pDel->pPrev->pNext = pDel->pNext; + /* point back to itself just to be safe, incase remove is called again */ + pDel->pNext = pDel; + pDel->pPrev = pDel; + return pDel; +} + +/* + * DL_ListRemoveItemFromHead - get a list item from the head +*/ +static INLINE PDL_LIST DL_ListRemoveItemFromHead(PDL_LIST pList) { + PDL_LIST pItem = NULL; + if (pList->pNext != pList) { + pItem = pList->pNext; + /* remove the first item from head */ + DL_ListRemove(pItem); + } + return pItem; +} + +#endif /* __DL_LIST_H___ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/dset_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/dset_api.h --- linux-2.6.26/drivers/net/wireless/ath6k22/dset_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/dset_api.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,65 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Host-side DataSet API. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _DSET_API_H_ +#define _DSET_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* + * Host-side DataSet support is optional, and is not + * currently required for correct operation. To disable + * Host-side DataSet support, set this to 0. + */ +#ifndef CONFIG_HOST_DSET_SUPPORT +#define CONFIG_HOST_DSET_SUPPORT 1 +#endif + +/* Called to send a DataSet Open Reply back to the Target. */ +A_STATUS wmi_dset_open_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT32 access_cookie, + A_UINT32 size, + A_UINT32 version, + A_UINT32 targ_handle, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); + +/* Called to send a DataSet Data Reply back to the Target. */ +A_STATUS wmi_dset_data_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT8 *host_buf, + A_UINT32 length, + A_UINT32 targ_buf, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* _DSET_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/dset_internal.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/dset_internal.h --- linux-2.6.26/drivers/net/wireless/ath6k22/dset_internal.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/dset_internal.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,55 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + + +#ifndef __DSET_INTERNAL_H__ +#define __DSET_INTERNAL_H__ + +/* + * Internal dset definitions, common for DataSet layer. + */ + +#define DSET_TYPE_STANDARD 0 +#define DSET_TYPE_BPATCHED 1 +#define DSET_TYPE_COMPRESSED 2 + +/* Dataset descriptor */ + +typedef struct dset_descriptor_s { + struct dset_descriptor_s *next; /* List link. NULL only at the last + descriptor */ + A_UINT16 id; /* Dset ID */ + A_UINT16 size; /* Dset size. */ + void *DataPtr; /* Pointer to raw data for standard + DataSet or pointer to original + dset_descriptor for patched + DataSet */ + A_UINT32 data_type; /* DSET_TYPE_*, above */ + + void *AuxPtr; /* Additional data that might + needed for data_type. For + example, pointer to patch + Dataset descriptor for BPatch. */ +} dset_descriptor_t; + +#endif /* __DSET_INTERNAL_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/dsetid.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/dsetid.h --- linux-2.6.26/drivers/net/wireless/ath6k22/dsetid.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/dsetid.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,126 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + + +#ifndef __DSETID_H__ +#define __DSETID_H__ + +/* Well-known DataSet IDs */ +#define DSETID_UNUSED 0x00000000 +#define DSETID_BOARD_DATA 0x00000001 /* Cal and board data */ +#define DSETID_REGDB 0x00000002 /* Regulatory Database */ +#define DSETID_POWER_CONTROL 0x00000003 /* TX Pwr Lim & Ant Gain */ +#define DSETID_USER_CONFIG 0x00000004 /* User Configuration */ + +#define DSETID_ANALOG_CONTROL_DATA_START 0x00000005 +#define DSETID_ANALOG_CONTROL_DATA_END 0x00000025 +/* + * Get DSETID for various reference clock speeds. + * For each speed there are three DataSets that correspond + * to the three columns of bank6 data (addr, 11a, 11b/g). + * This macro returns the dsetid of the first of those + * three DataSets. + */ +#define ANALOG_CONTROL_DATA_DSETID(refclk) \ + (DSETID_ANALOG_CONTROL_DATA_START + 3*refclk) + +/* + * There are TWO STARTUP_PATCH DataSets. + * DSETID_STARTUP_PATCH is historical, and was applied before BMI on + * earlier systems. On AR6002, it is applied after BMI, just like + * DSETID_STARTUP_PATCH2. + */ +#define DSETID_STARTUP_PATCH 0x00000026 +#define DSETID_GPIO_CONFIG_PATCH 0x00000027 +#define DSETID_WLANREGS 0x00000028 /* override wlan regs */ +#define DSETID_STARTUP_PATCH2 0x00000029 + +#define DSETID_WOW_CONFIG 0x00000090 /* WoW Configuration */ + +/* Add WHAL_INI_DATA_ID to DSETID_INI_DATA for a specific WHAL INI table. */ +#define DSETID_INI_DATA 0x00000100 +/* Reserved for WHAL INI Tables: 0x100..0x11f */ +#define DSETID_INI_DATA_END 0x0000011f + +#define DSETID_VENDOR_START 0x00010000 /* Vendor-defined DataSets */ + +#define DSETID_INDEX_END 0xfffffffe /* Reserved to indicate the + end of a memory-based + DataSet Index */ +#define DSETID_INDEX_FREE 0xffffffff /* An unused index entry */ + +/* + * PATCH DataSet format: + * A list of patches, terminated by a patch with + * address=PATCH_END. + * + * This allows for patches to be stored in flash. + */ +struct patch_s { + A_UINT32 *address; + A_UINT32 data; +}; + +/* + * Skip some patches. Can be used to erase a single patch in a + * patch DataSet without having to re-write the DataSet. May + * also be used to embed information for use by subsequent + * patch code. The "data" in a PATCH_SKIP tells how many + * bytes of length "patch_s" to skip. + */ +#define PATCH_SKIP ((A_UINT32 *)0x00000000) + +/* + * Execute code at the address specified by "data". + * The address of the patch structure is passed as + * the one parameter. + */ +#define PATCH_CODE_ABS ((A_UINT32 *)0x00000001) + +/* + * Same as PATCH_CODE_ABS, but treat "data" as an + * offset from the start of the patch word. + */ +#define PATCH_CODE_REL ((A_UINT32 *)0x00000002) + +/* Mark the end of this patch DataSet. */ +#define PATCH_END ((A_UINT32 *)0xffffffff) + +/* + * A DataSet which contains a Binary Patch to some other DataSet + * uses the original dsetid with the DSETID_BPATCH_FLAG bit set. + * Such a BPatch DataSet consists of BPatch metadata followed by + * the bdiff bytes. BPatch metadata consists of a single 32-bit + * word that contains the size of the BPatched final image. + * + * To create a suitable bdiff DataSet, use bdiff in host/tools/bdiff + * to create "diffs": + * bdiff -q -O -nooldmd5 -nonewmd5 -d ORIGfile NEWfile diffs + * Then add BPatch metadata to the start of "diffs". + * + * NB: There are some implementation-induced restrictions + * on which DataSets can be BPatched. + */ +#define DSETID_BPATCH_FLAG 0x80000000 + +#endif /* __DSETID_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/eeprom.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/eeprom.c --- linux-2.6.26/drivers/net/wireless/ath6k22/eeprom.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/eeprom.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,588 @@ +/* + * Copyright (c) 2006 Atheros Communications, Inc. + * All rights reserved. + * + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#include "ar6000_drv.h" +#include "htc.h" +#include + +#include "AR6002/hw2.0/hw/apb_map.h" +#include "AR6002/hw2.0/hw/gpio_reg.h" +#ifndef ANDROID_ENV +#include "AR6002/hw2.0/hw/rtc_reg.h" +#endif +#include "AR6002/hw2.0/hw/si_reg.h" + +// +// defines +// + +#define MAX_FILENAME 1023 +#define EEPROM_WAIT_LIMIT 16 + +#define HOST_INTEREST_ITEM_ADDRESS(item) \ + (AR6002_HOST_INTEREST_ITEM_ADDRESS(item)) + +#define EEPROM_SZ 768 + +/* soft mac */ +#define ATH_MAC_LEN 6 +#define ATH_SOFT_MAC_TMP_BUF_LEN 64 +unsigned char mac_addr[ATH_MAC_LEN]; +unsigned char soft_mac_tmp_buf[ATH_SOFT_MAC_TMP_BUF_LEN]; +char *p_mac = NULL; +/* soft mac */ + +// +// static variables +// + +static A_UCHAR eeprom_data[EEPROM_SZ]; +static A_UINT32 sys_sleep_reg; +static HIF_DEVICE *p_bmi_device; + +// +// Functions +// + +/* soft mac */ +static int +wmic_ether_aton(const char *orig, A_UINT8 *eth) +{ + const char *bufp; + int i; + + i = 0; + for(bufp = orig; *bufp != '\0'; ++bufp) { + unsigned int val; + unsigned char c = *bufp++; + if (c >= '0' && c <= '9') val = c - '0'; + else if (c >= 'a' && c <= 'f') val = c - 'a' + 10; + else if (c >= 'A' && c <= 'F') val = c - 'A' + 10; + else { + printk("%s: MAC value is invalid\n", __FUNCTION__); + break; + } + + val <<= 4; + c = *bufp++; + if (c >= '0' && c <= '9') val |= c - '0'; + else if (c >= 'a' && c <= 'f') val |= c - 'a' + 10; + else if (c >= 'A' && c <= 'F') val |= c - 'A' + 10; + else { + printk("%s: MAC value is invalid\n", __FUNCTION__); + break; + } + + eth[i] = (unsigned char) (val & 0377); + if(++i == ATH_MAC_LEN) { + /* That's it. Any trailing junk? */ + if (*bufp != '\0') { + return 0; + } + return 1; + } + if (*bufp != ':') + break; + } + return 0; +} + +static void +update_mac(unsigned char* eeprom, int size, unsigned char* macaddr) +{ + int i; + A_UINT16* ptr = (A_UINT16*)(eeprom+4); + A_UINT16 checksum = 0; + + memcpy(eeprom+10,macaddr,6); + + *ptr = 0; + ptr = (A_UINT16*)eeprom; + + for (i=0; i>7)); + + BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval); + + regval = SI_CS_START_SET(1) | + SI_CS_RX_CNT_SET(8) | + SI_CS_TX_CNT_SET(3); + BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval); +} + +/* + * Tell the Target to start a 4-byte write to EEPROM, + * writing values from Target TX_DATA registers. + */ +static void +request_4byte_write(int offset, A_UINT32 data) +{ + A_UINT32 regval; + + printk("%s: request_4byte_write (0x%x) to offset 0x%x\n", __FUNCTION__, data, offset); + + /* SI_TX_DATA0 = write data to offset */ + regval = ((data & 0xffff) <<16) | + ((offset & 0xff)<<8) | + (0xa0 | ((offset & 0xff00)>>7)); + BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval); + + regval = data >> 16; + BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA1_OFFSET, regval); + + regval = SI_CS_START_SET(1) | + SI_CS_RX_CNT_SET(0) | + SI_CS_TX_CNT_SET(6); + BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval); +} + +/* + * Check whether or not an EEPROM request that was started + * earlier has completed yet. + */ +static A_BOOL +request_in_progress(void) +{ + A_UINT32 regval; + + /* Wait for DONE_INT in SI_CS */ + BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, ®val); + +// printk("%s: request in progress SI_CS=0x%x\n", __FUNCTION__, regval); + if (regval & SI_CS_DONE_ERR_MASK) { + printk("%s: EEPROM signaled ERROR (0x%x)\n", __FUNCTION__, regval); + } + + return (!(regval & SI_CS_DONE_INT_MASK)); +} + +/* + * try to detect the type of EEPROM,16bit address or 8bit address + */ + +static void eeprom_type_detect(void) +{ + A_UINT32 regval; + A_UINT8 i = 0; + + request_8byte_read(0x100); + /* Wait for DONE_INT in SI_CS */ + do{ + BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, ®val); + if (regval & SI_CS_DONE_ERR_MASK) { + printk("%s: ERROR : address type was wrongly set\n", __FUNCTION__); + break; + } + if (i++ == EEPROM_WAIT_LIMIT) { + printk("%s: EEPROM not responding\n", __FUNCTION__); + } + } while(!(regval & SI_CS_DONE_INT_MASK)); +} + +/* + * Extract the results of a completed EEPROM Read request + * and return them to the caller. + */ +inline void +read_8byte_results(A_UINT32 *data) +{ + /* Read SI_RX_DATA0 and SI_RX_DATA1 */ + BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA0_OFFSET, &data[0]); + BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA1_OFFSET, &data[1]); +} + + +/* + * Wait for a previously started command to complete. + * Timeout if the command is takes "too long". + */ +static void +wait_for_eeprom_completion(void) +{ + int i=0; + + while (request_in_progress()) { + if (i++ == EEPROM_WAIT_LIMIT) { + printk("%s: EEPROM not responding\n", __FUNCTION__); + } + } +} + +/* + * High-level function which starts an 8-byte read, + * waits for it to complete, and returns the result. + */ +static void +fetch_8bytes(int offset, A_UINT32 *data) +{ + request_8byte_read(offset); + wait_for_eeprom_completion(); + read_8byte_results(data); + + /* Clear any pending intr */ + BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, SI_CS_DONE_INT_MASK); +} + +/* + * High-level function which starts a 4-byte write, + * and waits for it to complete. + */ +inline void +commit_4bytes(int offset, A_UINT32 data) +{ + request_4byte_write(offset, data); + wait_for_eeprom_completion(); +} +/* ATHENV */ +#ifdef ANDROID_ENV +void eeprom_ar6000_transfer(HIF_DEVICE *device, char *fake_file, char *p_mac) +{ + A_UINT32 first_word; + A_UINT32 board_data_addr; + int i; + + printk("%s: Enter\n", __FUNCTION__); + + enable_SI(device); + eeprom_type_detect(); + + if (fake_file) { + /* + * Transfer from file to Target RAM. + * Fetch source data from file. + */ + mm_segment_t oldfs; + struct file *filp; + struct inode *inode = NULL; + int length; + + /* open file */ + oldfs = get_fs(); + set_fs(KERNEL_DS); + filp = filp_open(fake_file, O_RDONLY, S_IRUSR); + + if (IS_ERR(filp)) { + printk("%s: file %s filp_open error\n", __FUNCTION__, fake_file); + set_fs(oldfs); + return; + } + + if (!filp->f_op) { + printk("%s: File Operation Method Error\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + inode = filp->f_path.dentry->d_inode; +#else + inode = filp->f_dentry->d_inode; +#endif + + if (!inode) { + printk("%s: Get inode from filp failed\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos); + + /* file's size */ + length = i_size_read(inode->i_mapping->host); + printk("%s: length=%d\n", __FUNCTION__, length); + if (length != EEPROM_SZ) { + printk("%s: The file's size is not as expected\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + /* read data */ + if (filp->f_op->read(filp, eeprom_data, length, &filp->f_pos) != length) { + printk("%s: file read error\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + /* read data out successfully */ + filp_close(filp, NULL); + set_fs(oldfs); + } else { + /* + * Read from EEPROM to file OR transfer from EEPROM to Target RAM. + * Fetch EEPROM_SZ Bytes of Board Data, 8 bytes at a time. + */ + + fetch_8bytes(0, (A_UINT32 *)(&eeprom_data[0])); + + /* Check the first word of EEPROM for validity */ + first_word = *((A_UINT32 *)eeprom_data); + + if ((first_word == 0) || (first_word == 0xffffffff)) { + printk("Did not find EEPROM with valid Board Data.\n"); + } + + for (i=8; if_op) { + printk("%s: File Operation Method Error\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + inode = filp->f_path.dentry->d_inode; +#else + inode = filp->f_dentry->d_inode; +#endif + if (!inode) { + printk("%s: Get inode from filp failed\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos); + + /* file's size */ + length = i_size_read(inode->i_mapping->host); + printk("%s: length=%d\n", __FUNCTION__, length); + if (length > ATH_SOFT_MAC_TMP_BUF_LEN) { + printk("%s: MAC file's size is not as expected\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + /* read data */ + if (filp->f_op->read(filp, soft_mac_tmp_buf, length, &filp->f_pos) != length) { + printk("%s: file read error\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + +#if 0 + /* the data we just read */ + printk("%s: mac address from the file:\n", __FUNCTION__); + for (i = 0; i < length; i++) + printk("[%c(0x%x)],", soft_mac_tmp_buf[i], soft_mac_tmp_buf[i]); + printk("\n"); +#endif + + /* read data out successfully */ + filp_close(filp, NULL); + set_fs(oldfs); + + /* convert mac address */ + if (!wmic_ether_aton(soft_mac_tmp_buf, mac_addr)) { + printk("%s: convert mac value fail\n", __FUNCTION__); + return; + } + +#if 0 + /* the converted mac address */ + printk("%s: the converted mac value\n", __FUNCTION__); + for (i = 0; i < ATH_MAC_LEN; i++) + printk("[0x%x],", mac_addr[i]); + printk("\n"); +#endif + } + /* soft mac */ + + /* Determine where in Target RAM to write Board Data */ + BMI_read_mem( HOST_INTEREST_ITEM_ADDRESS(hi_board_data), &board_data_addr); + if (board_data_addr == 0) { + printk("hi_board_data is zero\n"); + } + + /* soft mac */ +#if 1 + /* Update MAC address in RAM */ + if (p_mac) { + update_mac(eeprom_data, EEPROM_SZ, mac_addr); + } +#endif +#if 0 + /* mac address in eeprom array */ + printk("%s: mac values in eeprom array\n", __FUNCTION__); + for (i = 10; i < 10 + 6; i++) + printk("[0x%x],", eeprom_data[i]); + printk("\n"); +#endif + /* soft mac */ + + /* Write EEPROM data to Target RAM */ + BMI_write_mem(board_data_addr, ((A_UINT8 *)eeprom_data), EEPROM_SZ); + + /* Record the fact that Board Data IS initialized */ + { + A_UINT32 one = 1; + BMI_write_mem(HOST_INTEREST_ITEM_ADDRESS(hi_board_data_initialized), + (A_UINT8 *)&one, sizeof(A_UINT32)); + } + + disable_SI(); +} +#endif +/* ATHENV */ + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/engine.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/engine.c --- linux-2.6.26/drivers/net/wireless/ath6k22/engine.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/engine.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,278 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ +#include "engine.h" + +#define ACC regs[0] + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +static unsigned int regs[16]; +static int offset; +static unsigned char *cp; + +int ar6k_reg_preload( int reg, unsigned int value ) +{ + if( (reg < 0) || (reg > 16) ) + return(-1); /* Illegal register */ + + regs[ reg ] = value; + return(0); +} + +static int getoffset( void ) +{ + int i = 0; + + cp++; + offset++; + + i |= (*cp & 0xFF); cp++; offset++; + i |= (*cp & 0xFF) << 8; cp++; offset++; + i |= (*cp & 0xFF) << 16; cp++; offset++; + i |= (*cp & 0xFF) << 24; cp++; offset++; + + return(i); +} + +static int getarg( void ) +{ + int i; + + if( *cp & 0x0F ) + { + i = regs[ *cp & 0xF ]; + cp++; offset++; + return(i); + } + return( getoffset() ); +} + +static void dumpregs( void ) +{ + int i; + + sysprint("Acc: 0x%X\n", ACC); + + for(i=1; i<16; i++) + sysprint("r%x : 0x%X\n", i, regs[ i ]); + +} + +int fwengine( unsigned char *img, int size, void *ar) +{ + unsigned int crc; + int i; + + /* 14 is the minimal size of an empty image */ + if( ! (*img) || (*img != 0xFF) || (size <14) ) + { + syserr("Wrong image or no image\n"); + return -1; + } + + /* Check crc32 */ + cp = img + size - 4; + + *cp = ~(*cp) & 0xFF ; cp++; + *cp = ~(*cp) & 0xFF ; cp++; + *cp = ~(*cp) & 0xFF ; cp++; + *cp = ~(*cp) & 0xFF ; + + crc = crc32( ~0, img, size ); + + if( crc ) + { + syserr("Image CRC error\n"); + return -1; + } + + if( *(img+1) > VERSION ) + { + syserr("Image version is newer than the driver\n"); + return -1; + } + + /* Basic checks complete, we can print greeting and FW_ID here if desired */ + + /* Get to the first opcode */ + + cp = img + 2; /* Skip magic and version */ + offset = 2; + + while( (offset < size) && (*cp) ) + { + cp++; /* Skip build host name */ + offset++; + } + + cp += 6; /* Skip build date */ + offset += 6; + + while( (cp > img) && (cp < (img+size-4)) ) /* just an additional bounds check */ + { + /* First, find out opcode class */ + switch( (*cp & 0xF0) ) + { + case RLoad : + ACC = getarg( ); + break; + case Ror : + ACC |= getarg( ); + break; + case Rand : + ACC &= getarg( ); + break; + case Add : + ACC += getarg( ); + break; + case Rstor : + regs[ *cp & 0xF ] = ACC; + cp++; + offset++; + break; + case Shift : + i = getarg( ); + if(i < 0) + ACC >>= -i; + else + ACC <<= i; + break; + case Nneg : + if( *cp & 0xF ) + regs[ *cp & 0xF ] = ~regs[ *cp & 0xF ]; + else + ACC = -ACC; + cp++; + offset++; + break; + case Trr : + ACC = get_target_reg( getarg(), ar ); + break; + case Trw : + write_target_reg( getarg(), ACC , ar ); + break; + case Trx : + ACC = execute_on_target( getarg(), ACC, ar ); + break; + case Exit : + if( *cp & 0xF ) /* abort with code */ + return( regs[ *cp & 0xF ] ); + else{ /* clean exit */ + bmidone( ar ); + return(0); + } + break; + case Cmp : + ACC -= getarg(); + break; + case Ldprn : + if( ! (*cp & 0xF) ) /* register dump */ + dumpregs(); + else + { + int ret; + + ret = load_binary(ACC, cp, ar); + if( ret < 0 ) + return( -1 ); /* Error */ + cp += ret; + offset += ret; + } + break; + case Jump : + if( !(*cp & 0xF) || + ((*cp == 0xE1) && (ACC)) || + ((*cp == 0xE2) && !(ACC)) ) + + offset = getoffset(); + cp = img + offset; + + break; + default: + syserr("Image format error\n"); + break; + + } + } + return(0); +} +#ifdef UNIT_TEST +#include + +unsigned char fwbuf[ 4 * 1024 * 1024 ]; + +void bmidone( void *ar ) +{ + printf("BMI done.\n"); +} +int load_binary( unsigned int addr, unsigned char *cp, void *ar ) +{ + int size = 0; + int adv = 5; + + cp++; + size |= ( *cp & 0xFF ); cp++; + size |= ( *cp & 0xFF ) << 8; cp++; + size |= ( *cp & 0xFF ) << 16; cp++; + size |= ( *cp & 0xFF ) << 24; cp++; + + printf("Loading binary to address 0x%X, size %d\n", addr, size); + adv += size; + return(adv); +} + +int execute_on_target( unsigned address, unsigned arg, void *ar ) +{ + printf("Start target execution at address 0x%X with argument 0x%X\n", address, arg); + return(0); +} + +int write_target_reg( unsigned address, unsigned value, void *ar ) +{ + printf("Writing target register 0x%X with 0x%X\n", address, value); + return(0); +} + +unsigned int get_target_reg( unsigned address, void *ar ) +{ + unsigned int ret = 1; + + printf("Reading target register 0x%X, returning 0x%X\n", address, ret ); + return (ret); +} +int main() +{ + int ch, ret; + unsigned char *bufptr = fwbuf; + + init_crc32(); + + printf("Reading firmware image\n"); + while( (ch = getchar()) != EOF) + *bufptr++ = ch; + + printf("Calling firmware engine for image size: %d\n", bufptr - fwbuf + 1); + ret = engine( fwbuf, bufptr - fwbuf, NULL ); + printf("Engine returned with code %d\n", ret); +} +#endif /* UNIT_TEST */ +#endif /* KERNEL_VERSION 2.6 only */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/engine.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/engine.h --- linux-2.6.26/drivers/net/wireless/ath6k22/engine.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/engine.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,75 @@ +/* + * athloader.h - definitions for atheros firmware loader. + * + * Firmware image format: + * + * unsigned char 0xFF // "magic" + * unsigned char version // fw loader / tool version, not fw version major/minor 4 bits each + * char hostname[variable] // zero delimited hostname where the image was built + * unsigned char month // + * unsigned char day // Date and time when the image was built + * unsigned char year // year is a number of years after 2008, i.e. 2008 is coided as 0 + * unsigned char hour // + * unsigned char min // + * // the rest are optional blocks that may be repeated and/or mixed + * unsigned char instruction + * unsigned char argument[4] // optional constant, mask or offset + * unsigned char image[variable] // optional loadable image + * // repeated as necessary + * unsigned char crc32[4] // inverted crc32 + * + */ +#ifndef ATHLOADER_IS_SEEN +#define ATHLOADER_IS_SEEN + +#include + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +#define FW_AUTOLOAD +/* Uncomment the following to build standalone application for testing + +#define UNIT_TEST +#define syserr printf +#define sysprint printf +#include "crc32.h" +#include + */ + +#ifndef UNIT_TEST +#if defined(__linux__) || defined(LINUX) +#include +#include +#include +#include +#include +#include +#define syserr(arg...) printk( KERN_ERR arg) +#define sysprint(arg...) printk( KERN_INFO arg) +#endif /* __linux__ */ +#endif /* UNIT_TEST */ + +#define VERSION (0x01) + +/* Opcodes */ +#define RLoad (0x10) +#define Ror (0x20) +#define Rand (0x30) +#define Add (0x40) +#define Rstor (0x50) +#define Shift (0x60) +#define Nneg (0x70) +#define Trr (0x80) +#define Trw (0x90) +#define Trx (0xA0) +#define Exit (0xB0) +#define Cmp (0xC0) +#define Ldprn (0xD0) +#define Jump (0xE0) + +extern unsigned int get_target_reg( unsigned address, void *ar ); +extern int write_target_reg( unsigned address, unsigned value, void *ar ); +extern int execute_on_target( unsigned int address, unsigned int arg, void *ar ); +extern int load_binary(unsigned int addr, unsigned char *data, void *ar ); +extern void bmidone( void *ar ); +#endif /* KERNEL 2.6 only */ +#endif /* ATHLOADER_IS_SEEN */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/gpio.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/gpio.h --- linux-2.6.26/drivers/net/wireless/ath6k22/gpio.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/gpio.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,49 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2005 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#if defined(AR6001) +#define GPIO_PIN_COUNT 18 +#else +#define GPIO_PIN_COUNT 18 +#endif + +/* + * Possible values for WMIX_GPIO_SET_REGISTER_CMDID. + * NB: These match hardware order, so that addresses can + * easily be computed. + */ +#define GPIO_ID_OUT 0x00000000 +#define GPIO_ID_OUT_W1TS 0x00000001 +#define GPIO_ID_OUT_W1TC 0x00000002 +#define GPIO_ID_ENABLE 0x00000003 +#define GPIO_ID_ENABLE_W1TS 0x00000004 +#define GPIO_ID_ENABLE_W1TC 0x00000005 +#define GPIO_ID_IN 0x00000006 +#define GPIO_ID_STATUS 0x00000007 +#define GPIO_ID_STATUS_W1TS 0x00000008 +#define GPIO_ID_STATUS_W1TC 0x00000009 +#define GPIO_ID_PIN0 0x0000000a +#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) + +#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(17) +#define GPIO_ID_NONE 0xffffffff diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/gpio_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/gpio_api.h --- linux-2.6.26/drivers/net/wireless/ath6k22/gpio_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/gpio_api.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,59 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Host-side General Purpose I/O API. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _GPIO_API_H_ +#define _GPIO_API_H_ + +/* + * Send a command to the Target in order to change output on GPIO pins. + */ +A_STATUS wmi_gpio_output_set(struct wmi_t *wmip, + A_UINT32 set_mask, + A_UINT32 clear_mask, + A_UINT32 enable_mask, + A_UINT32 disable_mask); + +/* + * Send a command to the Target requesting input state of GPIO pins. + */ +A_STATUS wmi_gpio_input_get(struct wmi_t *wmip); + +/* + * Send a command to the Target to change the value of a GPIO register. + */ +A_STATUS wmi_gpio_register_set(struct wmi_t *wmip, + A_UINT32 gpioreg_id, + A_UINT32 value); + +/* + * Send a command to the Target to fetch the value of a GPIO register. + */ +A_STATUS wmi_gpio_register_get(struct wmi_t *wmip, A_UINT32 gpioreg_id); + +/* + * Send a command to the Target, acknowledging some GPIO interrupts. + */ +A_STATUS wmi_gpio_intr_ack(struct wmi_t *wmip, A_UINT32 ack_mask); + +#endif /* _GPIO_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/gpio_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/gpio_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k22/gpio_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/gpio_reg.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,1000 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _GPIO_REG_REG_H_ +#define _GPIO_REG_REG_H_ + +#define GPIO_OUT_ADDRESS 0x00000000 +#define GPIO_OUT_OFFSET 0x00000000 +#define GPIO_OUT_DATA_MSB 17 +#define GPIO_OUT_DATA_LSB 0 +#define GPIO_OUT_DATA_MASK 0x0003ffff +#define GPIO_OUT_DATA_GET(x) (((x) & GPIO_OUT_DATA_MASK) >> GPIO_OUT_DATA_LSB) +#define GPIO_OUT_DATA_SET(x) (((x) << GPIO_OUT_DATA_LSB) & GPIO_OUT_DATA_MASK) + +#define GPIO_OUT_W1TS_ADDRESS 0x00000004 +#define GPIO_OUT_W1TS_OFFSET 0x00000004 +#define GPIO_OUT_W1TS_DATA_MSB 17 +#define GPIO_OUT_W1TS_DATA_LSB 0 +#define GPIO_OUT_W1TS_DATA_MASK 0x0003ffff +#define GPIO_OUT_W1TS_DATA_GET(x) (((x) & GPIO_OUT_W1TS_DATA_MASK) >> GPIO_OUT_W1TS_DATA_LSB) +#define GPIO_OUT_W1TS_DATA_SET(x) (((x) << GPIO_OUT_W1TS_DATA_LSB) & GPIO_OUT_W1TS_DATA_MASK) + +#define GPIO_OUT_W1TC_ADDRESS 0x00000008 +#define GPIO_OUT_W1TC_OFFSET 0x00000008 +#define GPIO_OUT_W1TC_DATA_MSB 17 +#define GPIO_OUT_W1TC_DATA_LSB 0 +#define GPIO_OUT_W1TC_DATA_MASK 0x0003ffff +#define GPIO_OUT_W1TC_DATA_GET(x) (((x) & GPIO_OUT_W1TC_DATA_MASK) >> GPIO_OUT_W1TC_DATA_LSB) +#define GPIO_OUT_W1TC_DATA_SET(x) (((x) << GPIO_OUT_W1TC_DATA_LSB) & GPIO_OUT_W1TC_DATA_MASK) + +#define GPIO_ENABLE_ADDRESS 0x0000000c +#define GPIO_ENABLE_OFFSET 0x0000000c +#define GPIO_ENABLE_DATA_MSB 17 +#define GPIO_ENABLE_DATA_LSB 0 +#define GPIO_ENABLE_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_DATA_GET(x) (((x) & GPIO_ENABLE_DATA_MASK) >> GPIO_ENABLE_DATA_LSB) +#define GPIO_ENABLE_DATA_SET(x) (((x) << GPIO_ENABLE_DATA_LSB) & GPIO_ENABLE_DATA_MASK) + +#define GPIO_ENABLE_W1TS_ADDRESS 0x00000010 +#define GPIO_ENABLE_W1TS_OFFSET 0x00000010 +#define GPIO_ENABLE_W1TS_DATA_MSB 17 +#define GPIO_ENABLE_W1TS_DATA_LSB 0 +#define GPIO_ENABLE_W1TS_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_W1TS_DATA_GET(x) (((x) & GPIO_ENABLE_W1TS_DATA_MASK) >> GPIO_ENABLE_W1TS_DATA_LSB) +#define GPIO_ENABLE_W1TS_DATA_SET(x) (((x) << GPIO_ENABLE_W1TS_DATA_LSB) & GPIO_ENABLE_W1TS_DATA_MASK) + +#define GPIO_ENABLE_W1TC_ADDRESS 0x00000014 +#define GPIO_ENABLE_W1TC_OFFSET 0x00000014 +#define GPIO_ENABLE_W1TC_DATA_MSB 17 +#define GPIO_ENABLE_W1TC_DATA_LSB 0 +#define GPIO_ENABLE_W1TC_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_W1TC_DATA_GET(x) (((x) & GPIO_ENABLE_W1TC_DATA_MASK) >> GPIO_ENABLE_W1TC_DATA_LSB) +#define GPIO_ENABLE_W1TC_DATA_SET(x) (((x) << GPIO_ENABLE_W1TC_DATA_LSB) & GPIO_ENABLE_W1TC_DATA_MASK) + +#define GPIO_IN_ADDRESS 0x00000018 +#define GPIO_IN_OFFSET 0x00000018 +#define GPIO_IN_DATA_MSB 17 +#define GPIO_IN_DATA_LSB 0 +#define GPIO_IN_DATA_MASK 0x0003ffff +#define GPIO_IN_DATA_GET(x) (((x) & GPIO_IN_DATA_MASK) >> GPIO_IN_DATA_LSB) +#define GPIO_IN_DATA_SET(x) (((x) << GPIO_IN_DATA_LSB) & GPIO_IN_DATA_MASK) + +#define GPIO_STATUS_ADDRESS 0x0000001c +#define GPIO_STATUS_OFFSET 0x0000001c +#define GPIO_STATUS_INTERRUPT_MSB 17 +#define GPIO_STATUS_INTERRUPT_LSB 0 +#define GPIO_STATUS_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_INTERRUPT_MASK) >> GPIO_STATUS_INTERRUPT_LSB) +#define GPIO_STATUS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_INTERRUPT_LSB) & GPIO_STATUS_INTERRUPT_MASK) + +#define GPIO_STATUS_W1TS_ADDRESS 0x00000020 +#define GPIO_STATUS_W1TS_OFFSET 0x00000020 +#define GPIO_STATUS_W1TS_INTERRUPT_MSB 17 +#define GPIO_STATUS_W1TS_INTERRUPT_LSB 0 +#define GPIO_STATUS_W1TS_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_W1TS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TS_INTERRUPT_MASK) >> GPIO_STATUS_W1TS_INTERRUPT_LSB) +#define GPIO_STATUS_W1TS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TS_INTERRUPT_LSB) & GPIO_STATUS_W1TS_INTERRUPT_MASK) + +#define GPIO_STATUS_W1TC_ADDRESS 0x00000024 +#define GPIO_STATUS_W1TC_OFFSET 0x00000024 +#define GPIO_STATUS_W1TC_INTERRUPT_MSB 17 +#define GPIO_STATUS_W1TC_INTERRUPT_LSB 0 +#define GPIO_STATUS_W1TC_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_W1TC_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TC_INTERRUPT_MASK) >> GPIO_STATUS_W1TC_INTERRUPT_LSB) +#define GPIO_STATUS_W1TC_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TC_INTERRUPT_LSB) & GPIO_STATUS_W1TC_INTERRUPT_MASK) + +#define GPIO_PIN0_ADDRESS 0x00000028 +#define GPIO_PIN0_OFFSET 0x00000028 +#define GPIO_PIN0_CONFIG_MSB 12 +#define GPIO_PIN0_CONFIG_LSB 11 +#define GPIO_PIN0_CONFIG_MASK 0x00001800 +#define GPIO_PIN0_CONFIG_GET(x) (((x) & GPIO_PIN0_CONFIG_MASK) >> GPIO_PIN0_CONFIG_LSB) +#define GPIO_PIN0_CONFIG_SET(x) (((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK) +#define GPIO_PIN0_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN0_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN0_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN0_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN0_WAKEUP_ENABLE_MASK) >> GPIO_PIN0_WAKEUP_ENABLE_LSB) +#define GPIO_PIN0_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN0_WAKEUP_ENABLE_LSB) & GPIO_PIN0_WAKEUP_ENABLE_MASK) +#define GPIO_PIN0_INT_TYPE_MSB 9 +#define GPIO_PIN0_INT_TYPE_LSB 7 +#define GPIO_PIN0_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN0_INT_TYPE_GET(x) (((x) & GPIO_PIN0_INT_TYPE_MASK) >> GPIO_PIN0_INT_TYPE_LSB) +#define GPIO_PIN0_INT_TYPE_SET(x) (((x) << GPIO_PIN0_INT_TYPE_LSB) & GPIO_PIN0_INT_TYPE_MASK) +#define GPIO_PIN0_PAD_DRIVER_MSB 2 +#define GPIO_PIN0_PAD_DRIVER_LSB 2 +#define GPIO_PIN0_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN0_PAD_DRIVER_GET(x) (((x) & GPIO_PIN0_PAD_DRIVER_MASK) >> GPIO_PIN0_PAD_DRIVER_LSB) +#define GPIO_PIN0_PAD_DRIVER_SET(x) (((x) << GPIO_PIN0_PAD_DRIVER_LSB) & GPIO_PIN0_PAD_DRIVER_MASK) +#define GPIO_PIN0_SOURCE_MSB 0 +#define GPIO_PIN0_SOURCE_LSB 0 +#define GPIO_PIN0_SOURCE_MASK 0x00000001 +#define GPIO_PIN0_SOURCE_GET(x) (((x) & GPIO_PIN0_SOURCE_MASK) >> GPIO_PIN0_SOURCE_LSB) +#define GPIO_PIN0_SOURCE_SET(x) (((x) << GPIO_PIN0_SOURCE_LSB) & GPIO_PIN0_SOURCE_MASK) + +#define GPIO_PIN1_ADDRESS 0x0000002c +#define GPIO_PIN1_OFFSET 0x0000002c +#define GPIO_PIN1_CONFIG_MSB 12 +#define GPIO_PIN1_CONFIG_LSB 11 +#define GPIO_PIN1_CONFIG_MASK 0x00001800 +#define GPIO_PIN1_CONFIG_GET(x) (((x) & GPIO_PIN1_CONFIG_MASK) >> GPIO_PIN1_CONFIG_LSB) +#define GPIO_PIN1_CONFIG_SET(x) (((x) << GPIO_PIN1_CONFIG_LSB) & GPIO_PIN1_CONFIG_MASK) +#define GPIO_PIN1_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN1_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN1_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN1_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN1_WAKEUP_ENABLE_MASK) >> GPIO_PIN1_WAKEUP_ENABLE_LSB) +#define GPIO_PIN1_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN1_WAKEUP_ENABLE_LSB) & GPIO_PIN1_WAKEUP_ENABLE_MASK) +#define GPIO_PIN1_INT_TYPE_MSB 9 +#define GPIO_PIN1_INT_TYPE_LSB 7 +#define GPIO_PIN1_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN1_INT_TYPE_GET(x) (((x) & GPIO_PIN1_INT_TYPE_MASK) >> GPIO_PIN1_INT_TYPE_LSB) +#define GPIO_PIN1_INT_TYPE_SET(x) (((x) << GPIO_PIN1_INT_TYPE_LSB) & GPIO_PIN1_INT_TYPE_MASK) +#define GPIO_PIN1_PAD_DRIVER_MSB 2 +#define GPIO_PIN1_PAD_DRIVER_LSB 2 +#define GPIO_PIN1_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN1_PAD_DRIVER_GET(x) (((x) & GPIO_PIN1_PAD_DRIVER_MASK) >> GPIO_PIN1_PAD_DRIVER_LSB) +#define GPIO_PIN1_PAD_DRIVER_SET(x) (((x) << GPIO_PIN1_PAD_DRIVER_LSB) & GPIO_PIN1_PAD_DRIVER_MASK) +#define GPIO_PIN1_SOURCE_MSB 0 +#define GPIO_PIN1_SOURCE_LSB 0 +#define GPIO_PIN1_SOURCE_MASK 0x00000001 +#define GPIO_PIN1_SOURCE_GET(x) (((x) & GPIO_PIN1_SOURCE_MASK) >> GPIO_PIN1_SOURCE_LSB) +#define GPIO_PIN1_SOURCE_SET(x) (((x) << GPIO_PIN1_SOURCE_LSB) & GPIO_PIN1_SOURCE_MASK) + +#define GPIO_PIN2_ADDRESS 0x00000030 +#define GPIO_PIN2_OFFSET 0x00000030 +#define GPIO_PIN2_CONFIG_MSB 12 +#define GPIO_PIN2_CONFIG_LSB 11 +#define GPIO_PIN2_CONFIG_MASK 0x00001800 +#define GPIO_PIN2_CONFIG_GET(x) (((x) & GPIO_PIN2_CONFIG_MASK) >> GPIO_PIN2_CONFIG_LSB) +#define GPIO_PIN2_CONFIG_SET(x) (((x) << GPIO_PIN2_CONFIG_LSB) & GPIO_PIN2_CONFIG_MASK) +#define GPIO_PIN2_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN2_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN2_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN2_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN2_WAKEUP_ENABLE_MASK) >> GPIO_PIN2_WAKEUP_ENABLE_LSB) +#define GPIO_PIN2_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN2_WAKEUP_ENABLE_LSB) & GPIO_PIN2_WAKEUP_ENABLE_MASK) +#define GPIO_PIN2_INT_TYPE_MSB 9 +#define GPIO_PIN2_INT_TYPE_LSB 7 +#define GPIO_PIN2_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN2_INT_TYPE_GET(x) (((x) & GPIO_PIN2_INT_TYPE_MASK) >> GPIO_PIN2_INT_TYPE_LSB) +#define GPIO_PIN2_INT_TYPE_SET(x) (((x) << GPIO_PIN2_INT_TYPE_LSB) & GPIO_PIN2_INT_TYPE_MASK) +#define GPIO_PIN2_PAD_DRIVER_MSB 2 +#define GPIO_PIN2_PAD_DRIVER_LSB 2 +#define GPIO_PIN2_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN2_PAD_DRIVER_GET(x) (((x) & GPIO_PIN2_PAD_DRIVER_MASK) >> GPIO_PIN2_PAD_DRIVER_LSB) +#define GPIO_PIN2_PAD_DRIVER_SET(x) (((x) << GPIO_PIN2_PAD_DRIVER_LSB) & GPIO_PIN2_PAD_DRIVER_MASK) +#define GPIO_PIN2_SOURCE_MSB 0 +#define GPIO_PIN2_SOURCE_LSB 0 +#define GPIO_PIN2_SOURCE_MASK 0x00000001 +#define GPIO_PIN2_SOURCE_GET(x) (((x) & GPIO_PIN2_SOURCE_MASK) >> GPIO_PIN2_SOURCE_LSB) +#define GPIO_PIN2_SOURCE_SET(x) (((x) << GPIO_PIN2_SOURCE_LSB) & GPIO_PIN2_SOURCE_MASK) + +#define GPIO_PIN3_ADDRESS 0x00000034 +#define GPIO_PIN3_OFFSET 0x00000034 +#define GPIO_PIN3_CONFIG_MSB 12 +#define GPIO_PIN3_CONFIG_LSB 11 +#define GPIO_PIN3_CONFIG_MASK 0x00001800 +#define GPIO_PIN3_CONFIG_GET(x) (((x) & GPIO_PIN3_CONFIG_MASK) >> GPIO_PIN3_CONFIG_LSB) +#define GPIO_PIN3_CONFIG_SET(x) (((x) << GPIO_PIN3_CONFIG_LSB) & GPIO_PIN3_CONFIG_MASK) +#define GPIO_PIN3_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN3_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN3_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN3_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN3_WAKEUP_ENABLE_MASK) >> GPIO_PIN3_WAKEUP_ENABLE_LSB) +#define GPIO_PIN3_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN3_WAKEUP_ENABLE_LSB) & GPIO_PIN3_WAKEUP_ENABLE_MASK) +#define GPIO_PIN3_INT_TYPE_MSB 9 +#define GPIO_PIN3_INT_TYPE_LSB 7 +#define GPIO_PIN3_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN3_INT_TYPE_GET(x) (((x) & GPIO_PIN3_INT_TYPE_MASK) >> GPIO_PIN3_INT_TYPE_LSB) +#define GPIO_PIN3_INT_TYPE_SET(x) (((x) << GPIO_PIN3_INT_TYPE_LSB) & GPIO_PIN3_INT_TYPE_MASK) +#define GPIO_PIN3_PAD_DRIVER_MSB 2 +#define GPIO_PIN3_PAD_DRIVER_LSB 2 +#define GPIO_PIN3_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN3_PAD_DRIVER_GET(x) (((x) & GPIO_PIN3_PAD_DRIVER_MASK) >> GPIO_PIN3_PAD_DRIVER_LSB) +#define GPIO_PIN3_PAD_DRIVER_SET(x) (((x) << GPIO_PIN3_PAD_DRIVER_LSB) & GPIO_PIN3_PAD_DRIVER_MASK) +#define GPIO_PIN3_SOURCE_MSB 0 +#define GPIO_PIN3_SOURCE_LSB 0 +#define GPIO_PIN3_SOURCE_MASK 0x00000001 +#define GPIO_PIN3_SOURCE_GET(x) (((x) & GPIO_PIN3_SOURCE_MASK) >> GPIO_PIN3_SOURCE_LSB) +#define GPIO_PIN3_SOURCE_SET(x) (((x) << GPIO_PIN3_SOURCE_LSB) & GPIO_PIN3_SOURCE_MASK) + +#define GPIO_PIN4_ADDRESS 0x00000038 +#define GPIO_PIN4_OFFSET 0x00000038 +#define GPIO_PIN4_CONFIG_MSB 12 +#define GPIO_PIN4_CONFIG_LSB 11 +#define GPIO_PIN4_CONFIG_MASK 0x00001800 +#define GPIO_PIN4_CONFIG_GET(x) (((x) & GPIO_PIN4_CONFIG_MASK) >> GPIO_PIN4_CONFIG_LSB) +#define GPIO_PIN4_CONFIG_SET(x) (((x) << GPIO_PIN4_CONFIG_LSB) & GPIO_PIN4_CONFIG_MASK) +#define GPIO_PIN4_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN4_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN4_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN4_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN4_WAKEUP_ENABLE_MASK) >> GPIO_PIN4_WAKEUP_ENABLE_LSB) +#define GPIO_PIN4_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN4_WAKEUP_ENABLE_LSB) & GPIO_PIN4_WAKEUP_ENABLE_MASK) +#define GPIO_PIN4_INT_TYPE_MSB 9 +#define GPIO_PIN4_INT_TYPE_LSB 7 +#define GPIO_PIN4_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN4_INT_TYPE_GET(x) (((x) & GPIO_PIN4_INT_TYPE_MASK) >> GPIO_PIN4_INT_TYPE_LSB) +#define GPIO_PIN4_INT_TYPE_SET(x) (((x) << GPIO_PIN4_INT_TYPE_LSB) & GPIO_PIN4_INT_TYPE_MASK) +#define GPIO_PIN4_PAD_DRIVER_MSB 2 +#define GPIO_PIN4_PAD_DRIVER_LSB 2 +#define GPIO_PIN4_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN4_PAD_DRIVER_GET(x) (((x) & GPIO_PIN4_PAD_DRIVER_MASK) >> GPIO_PIN4_PAD_DRIVER_LSB) +#define GPIO_PIN4_PAD_DRIVER_SET(x) (((x) << GPIO_PIN4_PAD_DRIVER_LSB) & GPIO_PIN4_PAD_DRIVER_MASK) +#define GPIO_PIN4_SOURCE_MSB 0 +#define GPIO_PIN4_SOURCE_LSB 0 +#define GPIO_PIN4_SOURCE_MASK 0x00000001 +#define GPIO_PIN4_SOURCE_GET(x) (((x) & GPIO_PIN4_SOURCE_MASK) >> GPIO_PIN4_SOURCE_LSB) +#define GPIO_PIN4_SOURCE_SET(x) (((x) << GPIO_PIN4_SOURCE_LSB) & GPIO_PIN4_SOURCE_MASK) + +#define GPIO_PIN5_ADDRESS 0x0000003c +#define GPIO_PIN5_OFFSET 0x0000003c +#define GPIO_PIN5_CONFIG_MSB 12 +#define GPIO_PIN5_CONFIG_LSB 11 +#define GPIO_PIN5_CONFIG_MASK 0x00001800 +#define GPIO_PIN5_CONFIG_GET(x) (((x) & GPIO_PIN5_CONFIG_MASK) >> GPIO_PIN5_CONFIG_LSB) +#define GPIO_PIN5_CONFIG_SET(x) (((x) << GPIO_PIN5_CONFIG_LSB) & GPIO_PIN5_CONFIG_MASK) +#define GPIO_PIN5_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN5_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN5_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN5_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN5_WAKEUP_ENABLE_MASK) >> GPIO_PIN5_WAKEUP_ENABLE_LSB) +#define GPIO_PIN5_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN5_WAKEUP_ENABLE_LSB) & GPIO_PIN5_WAKEUP_ENABLE_MASK) +#define GPIO_PIN5_INT_TYPE_MSB 9 +#define GPIO_PIN5_INT_TYPE_LSB 7 +#define GPIO_PIN5_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN5_INT_TYPE_GET(x) (((x) & GPIO_PIN5_INT_TYPE_MASK) >> GPIO_PIN5_INT_TYPE_LSB) +#define GPIO_PIN5_INT_TYPE_SET(x) (((x) << GPIO_PIN5_INT_TYPE_LSB) & GPIO_PIN5_INT_TYPE_MASK) +#define GPIO_PIN5_PAD_DRIVER_MSB 2 +#define GPIO_PIN5_PAD_DRIVER_LSB 2 +#define GPIO_PIN5_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN5_PAD_DRIVER_GET(x) (((x) & GPIO_PIN5_PAD_DRIVER_MASK) >> GPIO_PIN5_PAD_DRIVER_LSB) +#define GPIO_PIN5_PAD_DRIVER_SET(x) (((x) << GPIO_PIN5_PAD_DRIVER_LSB) & GPIO_PIN5_PAD_DRIVER_MASK) +#define GPIO_PIN5_SOURCE_MSB 0 +#define GPIO_PIN5_SOURCE_LSB 0 +#define GPIO_PIN5_SOURCE_MASK 0x00000001 +#define GPIO_PIN5_SOURCE_GET(x) (((x) & GPIO_PIN5_SOURCE_MASK) >> GPIO_PIN5_SOURCE_LSB) +#define GPIO_PIN5_SOURCE_SET(x) (((x) << GPIO_PIN5_SOURCE_LSB) & GPIO_PIN5_SOURCE_MASK) + +#define GPIO_PIN6_ADDRESS 0x00000040 +#define GPIO_PIN6_OFFSET 0x00000040 +#define GPIO_PIN6_CONFIG_MSB 12 +#define GPIO_PIN6_CONFIG_LSB 11 +#define GPIO_PIN6_CONFIG_MASK 0x00001800 +#define GPIO_PIN6_CONFIG_GET(x) (((x) & GPIO_PIN6_CONFIG_MASK) >> GPIO_PIN6_CONFIG_LSB) +#define GPIO_PIN6_CONFIG_SET(x) (((x) << GPIO_PIN6_CONFIG_LSB) & GPIO_PIN6_CONFIG_MASK) +#define GPIO_PIN6_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN6_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN6_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN6_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN6_WAKEUP_ENABLE_MASK) >> GPIO_PIN6_WAKEUP_ENABLE_LSB) +#define GPIO_PIN6_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN6_WAKEUP_ENABLE_LSB) & GPIO_PIN6_WAKEUP_ENABLE_MASK) +#define GPIO_PIN6_INT_TYPE_MSB 9 +#define GPIO_PIN6_INT_TYPE_LSB 7 +#define GPIO_PIN6_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN6_INT_TYPE_GET(x) (((x) & GPIO_PIN6_INT_TYPE_MASK) >> GPIO_PIN6_INT_TYPE_LSB) +#define GPIO_PIN6_INT_TYPE_SET(x) (((x) << GPIO_PIN6_INT_TYPE_LSB) & GPIO_PIN6_INT_TYPE_MASK) +#define GPIO_PIN6_PAD_DRIVER_MSB 2 +#define GPIO_PIN6_PAD_DRIVER_LSB 2 +#define GPIO_PIN6_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN6_PAD_DRIVER_GET(x) (((x) & GPIO_PIN6_PAD_DRIVER_MASK) >> GPIO_PIN6_PAD_DRIVER_LSB) +#define GPIO_PIN6_PAD_DRIVER_SET(x) (((x) << GPIO_PIN6_PAD_DRIVER_LSB) & GPIO_PIN6_PAD_DRIVER_MASK) +#define GPIO_PIN6_SOURCE_MSB 0 +#define GPIO_PIN6_SOURCE_LSB 0 +#define GPIO_PIN6_SOURCE_MASK 0x00000001 +#define GPIO_PIN6_SOURCE_GET(x) (((x) & GPIO_PIN6_SOURCE_MASK) >> GPIO_PIN6_SOURCE_LSB) +#define GPIO_PIN6_SOURCE_SET(x) (((x) << GPIO_PIN6_SOURCE_LSB) & GPIO_PIN6_SOURCE_MASK) + +#define GPIO_PIN7_ADDRESS 0x00000044 +#define GPIO_PIN7_OFFSET 0x00000044 +#define GPIO_PIN7_CONFIG_MSB 12 +#define GPIO_PIN7_CONFIG_LSB 11 +#define GPIO_PIN7_CONFIG_MASK 0x00001800 +#define GPIO_PIN7_CONFIG_GET(x) (((x) & GPIO_PIN7_CONFIG_MASK) >> GPIO_PIN7_CONFIG_LSB) +#define GPIO_PIN7_CONFIG_SET(x) (((x) << GPIO_PIN7_CONFIG_LSB) & GPIO_PIN7_CONFIG_MASK) +#define GPIO_PIN7_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN7_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN7_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN7_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN7_WAKEUP_ENABLE_MASK) >> GPIO_PIN7_WAKEUP_ENABLE_LSB) +#define GPIO_PIN7_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN7_WAKEUP_ENABLE_LSB) & GPIO_PIN7_WAKEUP_ENABLE_MASK) +#define GPIO_PIN7_INT_TYPE_MSB 9 +#define GPIO_PIN7_INT_TYPE_LSB 7 +#define GPIO_PIN7_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN7_INT_TYPE_GET(x) (((x) & GPIO_PIN7_INT_TYPE_MASK) >> GPIO_PIN7_INT_TYPE_LSB) +#define GPIO_PIN7_INT_TYPE_SET(x) (((x) << GPIO_PIN7_INT_TYPE_LSB) & GPIO_PIN7_INT_TYPE_MASK) +#define GPIO_PIN7_PAD_DRIVER_MSB 2 +#define GPIO_PIN7_PAD_DRIVER_LSB 2 +#define GPIO_PIN7_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN7_PAD_DRIVER_GET(x) (((x) & GPIO_PIN7_PAD_DRIVER_MASK) >> GPIO_PIN7_PAD_DRIVER_LSB) +#define GPIO_PIN7_PAD_DRIVER_SET(x) (((x) << GPIO_PIN7_PAD_DRIVER_LSB) & GPIO_PIN7_PAD_DRIVER_MASK) +#define GPIO_PIN7_SOURCE_MSB 0 +#define GPIO_PIN7_SOURCE_LSB 0 +#define GPIO_PIN7_SOURCE_MASK 0x00000001 +#define GPIO_PIN7_SOURCE_GET(x) (((x) & GPIO_PIN7_SOURCE_MASK) >> GPIO_PIN7_SOURCE_LSB) +#define GPIO_PIN7_SOURCE_SET(x) (((x) << GPIO_PIN7_SOURCE_LSB) & GPIO_PIN7_SOURCE_MASK) + +#define GPIO_PIN8_ADDRESS 0x00000048 +#define GPIO_PIN8_OFFSET 0x00000048 +#define GPIO_PIN8_CONFIG_MSB 12 +#define GPIO_PIN8_CONFIG_LSB 11 +#define GPIO_PIN8_CONFIG_MASK 0x00001800 +#define GPIO_PIN8_CONFIG_GET(x) (((x) & GPIO_PIN8_CONFIG_MASK) >> GPIO_PIN8_CONFIG_LSB) +#define GPIO_PIN8_CONFIG_SET(x) (((x) << GPIO_PIN8_CONFIG_LSB) & GPIO_PIN8_CONFIG_MASK) +#define GPIO_PIN8_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN8_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN8_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN8_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN8_WAKEUP_ENABLE_MASK) >> GPIO_PIN8_WAKEUP_ENABLE_LSB) +#define GPIO_PIN8_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN8_WAKEUP_ENABLE_LSB) & GPIO_PIN8_WAKEUP_ENABLE_MASK) +#define GPIO_PIN8_INT_TYPE_MSB 9 +#define GPIO_PIN8_INT_TYPE_LSB 7 +#define GPIO_PIN8_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN8_INT_TYPE_GET(x) (((x) & GPIO_PIN8_INT_TYPE_MASK) >> GPIO_PIN8_INT_TYPE_LSB) +#define GPIO_PIN8_INT_TYPE_SET(x) (((x) << GPIO_PIN8_INT_TYPE_LSB) & GPIO_PIN8_INT_TYPE_MASK) +#define GPIO_PIN8_PAD_DRIVER_MSB 2 +#define GPIO_PIN8_PAD_DRIVER_LSB 2 +#define GPIO_PIN8_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN8_PAD_DRIVER_GET(x) (((x) & GPIO_PIN8_PAD_DRIVER_MASK) >> GPIO_PIN8_PAD_DRIVER_LSB) +#define GPIO_PIN8_PAD_DRIVER_SET(x) (((x) << GPIO_PIN8_PAD_DRIVER_LSB) & GPIO_PIN8_PAD_DRIVER_MASK) +#define GPIO_PIN8_SOURCE_MSB 0 +#define GPIO_PIN8_SOURCE_LSB 0 +#define GPIO_PIN8_SOURCE_MASK 0x00000001 +#define GPIO_PIN8_SOURCE_GET(x) (((x) & GPIO_PIN8_SOURCE_MASK) >> GPIO_PIN8_SOURCE_LSB) +#define GPIO_PIN8_SOURCE_SET(x) (((x) << GPIO_PIN8_SOURCE_LSB) & GPIO_PIN8_SOURCE_MASK) + +#define GPIO_PIN9_ADDRESS 0x0000004c +#define GPIO_PIN9_OFFSET 0x0000004c +#define GPIO_PIN9_CONFIG_MSB 12 +#define GPIO_PIN9_CONFIG_LSB 11 +#define GPIO_PIN9_CONFIG_MASK 0x00001800 +#define GPIO_PIN9_CONFIG_GET(x) (((x) & GPIO_PIN9_CONFIG_MASK) >> GPIO_PIN9_CONFIG_LSB) +#define GPIO_PIN9_CONFIG_SET(x) (((x) << GPIO_PIN9_CONFIG_LSB) & GPIO_PIN9_CONFIG_MASK) +#define GPIO_PIN9_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN9_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN9_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN9_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN9_WAKEUP_ENABLE_MASK) >> GPIO_PIN9_WAKEUP_ENABLE_LSB) +#define GPIO_PIN9_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN9_WAKEUP_ENABLE_LSB) & GPIO_PIN9_WAKEUP_ENABLE_MASK) +#define GPIO_PIN9_INT_TYPE_MSB 9 +#define GPIO_PIN9_INT_TYPE_LSB 7 +#define GPIO_PIN9_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN9_INT_TYPE_GET(x) (((x) & GPIO_PIN9_INT_TYPE_MASK) >> GPIO_PIN9_INT_TYPE_LSB) +#define GPIO_PIN9_INT_TYPE_SET(x) (((x) << GPIO_PIN9_INT_TYPE_LSB) & GPIO_PIN9_INT_TYPE_MASK) +#define GPIO_PIN9_PAD_DRIVER_MSB 2 +#define GPIO_PIN9_PAD_DRIVER_LSB 2 +#define GPIO_PIN9_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN9_PAD_DRIVER_GET(x) (((x) & GPIO_PIN9_PAD_DRIVER_MASK) >> GPIO_PIN9_PAD_DRIVER_LSB) +#define GPIO_PIN9_PAD_DRIVER_SET(x) (((x) << GPIO_PIN9_PAD_DRIVER_LSB) & GPIO_PIN9_PAD_DRIVER_MASK) +#define GPIO_PIN9_SOURCE_MSB 0 +#define GPIO_PIN9_SOURCE_LSB 0 +#define GPIO_PIN9_SOURCE_MASK 0x00000001 +#define GPIO_PIN9_SOURCE_GET(x) (((x) & GPIO_PIN9_SOURCE_MASK) >> GPIO_PIN9_SOURCE_LSB) +#define GPIO_PIN9_SOURCE_SET(x) (((x) << GPIO_PIN9_SOURCE_LSB) & GPIO_PIN9_SOURCE_MASK) + +#define GPIO_PIN10_ADDRESS 0x00000050 +#define GPIO_PIN10_OFFSET 0x00000050 +#define GPIO_PIN10_CONFIG_MSB 12 +#define GPIO_PIN10_CONFIG_LSB 11 +#define GPIO_PIN10_CONFIG_MASK 0x00001800 +#define GPIO_PIN10_CONFIG_GET(x) (((x) & GPIO_PIN10_CONFIG_MASK) >> GPIO_PIN10_CONFIG_LSB) +#define GPIO_PIN10_CONFIG_SET(x) (((x) << GPIO_PIN10_CONFIG_LSB) & GPIO_PIN10_CONFIG_MASK) +#define GPIO_PIN10_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN10_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN10_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN10_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN10_WAKEUP_ENABLE_MASK) >> GPIO_PIN10_WAKEUP_ENABLE_LSB) +#define GPIO_PIN10_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN10_WAKEUP_ENABLE_LSB) & GPIO_PIN10_WAKEUP_ENABLE_MASK) +#define GPIO_PIN10_INT_TYPE_MSB 9 +#define GPIO_PIN10_INT_TYPE_LSB 7 +#define GPIO_PIN10_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN10_INT_TYPE_GET(x) (((x) & GPIO_PIN10_INT_TYPE_MASK) >> GPIO_PIN10_INT_TYPE_LSB) +#define GPIO_PIN10_INT_TYPE_SET(x) (((x) << GPIO_PIN10_INT_TYPE_LSB) & GPIO_PIN10_INT_TYPE_MASK) +#define GPIO_PIN10_PAD_DRIVER_MSB 2 +#define GPIO_PIN10_PAD_DRIVER_LSB 2 +#define GPIO_PIN10_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN10_PAD_DRIVER_GET(x) (((x) & GPIO_PIN10_PAD_DRIVER_MASK) >> GPIO_PIN10_PAD_DRIVER_LSB) +#define GPIO_PIN10_PAD_DRIVER_SET(x) (((x) << GPIO_PIN10_PAD_DRIVER_LSB) & GPIO_PIN10_PAD_DRIVER_MASK) +#define GPIO_PIN10_SOURCE_MSB 0 +#define GPIO_PIN10_SOURCE_LSB 0 +#define GPIO_PIN10_SOURCE_MASK 0x00000001 +#define GPIO_PIN10_SOURCE_GET(x) (((x) & GPIO_PIN10_SOURCE_MASK) >> GPIO_PIN10_SOURCE_LSB) +#define GPIO_PIN10_SOURCE_SET(x) (((x) << GPIO_PIN10_SOURCE_LSB) & GPIO_PIN10_SOURCE_MASK) + +#define GPIO_PIN11_ADDRESS 0x00000054 +#define GPIO_PIN11_OFFSET 0x00000054 +#define GPIO_PIN11_CONFIG_MSB 12 +#define GPIO_PIN11_CONFIG_LSB 11 +#define GPIO_PIN11_CONFIG_MASK 0x00001800 +#define GPIO_PIN11_CONFIG_GET(x) (((x) & GPIO_PIN11_CONFIG_MASK) >> GPIO_PIN11_CONFIG_LSB) +#define GPIO_PIN11_CONFIG_SET(x) (((x) << GPIO_PIN11_CONFIG_LSB) & GPIO_PIN11_CONFIG_MASK) +#define GPIO_PIN11_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN11_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN11_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN11_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN11_WAKEUP_ENABLE_MASK) >> GPIO_PIN11_WAKEUP_ENABLE_LSB) +#define GPIO_PIN11_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN11_WAKEUP_ENABLE_LSB) & GPIO_PIN11_WAKEUP_ENABLE_MASK) +#define GPIO_PIN11_INT_TYPE_MSB 9 +#define GPIO_PIN11_INT_TYPE_LSB 7 +#define GPIO_PIN11_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN11_INT_TYPE_GET(x) (((x) & GPIO_PIN11_INT_TYPE_MASK) >> GPIO_PIN11_INT_TYPE_LSB) +#define GPIO_PIN11_INT_TYPE_SET(x) (((x) << GPIO_PIN11_INT_TYPE_LSB) & GPIO_PIN11_INT_TYPE_MASK) +#define GPIO_PIN11_PAD_DRIVER_MSB 2 +#define GPIO_PIN11_PAD_DRIVER_LSB 2 +#define GPIO_PIN11_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN11_PAD_DRIVER_GET(x) (((x) & GPIO_PIN11_PAD_DRIVER_MASK) >> GPIO_PIN11_PAD_DRIVER_LSB) +#define GPIO_PIN11_PAD_DRIVER_SET(x) (((x) << GPIO_PIN11_PAD_DRIVER_LSB) & GPIO_PIN11_PAD_DRIVER_MASK) +#define GPIO_PIN11_SOURCE_MSB 0 +#define GPIO_PIN11_SOURCE_LSB 0 +#define GPIO_PIN11_SOURCE_MASK 0x00000001 +#define GPIO_PIN11_SOURCE_GET(x) (((x) & GPIO_PIN11_SOURCE_MASK) >> GPIO_PIN11_SOURCE_LSB) +#define GPIO_PIN11_SOURCE_SET(x) (((x) << GPIO_PIN11_SOURCE_LSB) & GPIO_PIN11_SOURCE_MASK) + +#define GPIO_PIN12_ADDRESS 0x00000058 +#define GPIO_PIN12_OFFSET 0x00000058 +#define GPIO_PIN12_CONFIG_MSB 12 +#define GPIO_PIN12_CONFIG_LSB 11 +#define GPIO_PIN12_CONFIG_MASK 0x00001800 +#define GPIO_PIN12_CONFIG_GET(x) (((x) & GPIO_PIN12_CONFIG_MASK) >> GPIO_PIN12_CONFIG_LSB) +#define GPIO_PIN12_CONFIG_SET(x) (((x) << GPIO_PIN12_CONFIG_LSB) & GPIO_PIN12_CONFIG_MASK) +#define GPIO_PIN12_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN12_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN12_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN12_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN12_WAKEUP_ENABLE_MASK) >> GPIO_PIN12_WAKEUP_ENABLE_LSB) +#define GPIO_PIN12_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN12_WAKEUP_ENABLE_LSB) & GPIO_PIN12_WAKEUP_ENABLE_MASK) +#define GPIO_PIN12_INT_TYPE_MSB 9 +#define GPIO_PIN12_INT_TYPE_LSB 7 +#define GPIO_PIN12_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN12_INT_TYPE_GET(x) (((x) & GPIO_PIN12_INT_TYPE_MASK) >> GPIO_PIN12_INT_TYPE_LSB) +#define GPIO_PIN12_INT_TYPE_SET(x) (((x) << GPIO_PIN12_INT_TYPE_LSB) & GPIO_PIN12_INT_TYPE_MASK) +#define GPIO_PIN12_PAD_DRIVER_MSB 2 +#define GPIO_PIN12_PAD_DRIVER_LSB 2 +#define GPIO_PIN12_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN12_PAD_DRIVER_GET(x) (((x) & GPIO_PIN12_PAD_DRIVER_MASK) >> GPIO_PIN12_PAD_DRIVER_LSB) +#define GPIO_PIN12_PAD_DRIVER_SET(x) (((x) << GPIO_PIN12_PAD_DRIVER_LSB) & GPIO_PIN12_PAD_DRIVER_MASK) +#define GPIO_PIN12_SOURCE_MSB 0 +#define GPIO_PIN12_SOURCE_LSB 0 +#define GPIO_PIN12_SOURCE_MASK 0x00000001 +#define GPIO_PIN12_SOURCE_GET(x) (((x) & GPIO_PIN12_SOURCE_MASK) >> GPIO_PIN12_SOURCE_LSB) +#define GPIO_PIN12_SOURCE_SET(x) (((x) << GPIO_PIN12_SOURCE_LSB) & GPIO_PIN12_SOURCE_MASK) + +#define GPIO_PIN13_ADDRESS 0x0000005c +#define GPIO_PIN13_OFFSET 0x0000005c +#define GPIO_PIN13_CONFIG_MSB 12 +#define GPIO_PIN13_CONFIG_LSB 11 +#define GPIO_PIN13_CONFIG_MASK 0x00001800 +#define GPIO_PIN13_CONFIG_GET(x) (((x) & GPIO_PIN13_CONFIG_MASK) >> GPIO_PIN13_CONFIG_LSB) +#define GPIO_PIN13_CONFIG_SET(x) (((x) << GPIO_PIN13_CONFIG_LSB) & GPIO_PIN13_CONFIG_MASK) +#define GPIO_PIN13_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN13_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN13_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN13_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN13_WAKEUP_ENABLE_MASK) >> GPIO_PIN13_WAKEUP_ENABLE_LSB) +#define GPIO_PIN13_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN13_WAKEUP_ENABLE_LSB) & GPIO_PIN13_WAKEUP_ENABLE_MASK) +#define GPIO_PIN13_INT_TYPE_MSB 9 +#define GPIO_PIN13_INT_TYPE_LSB 7 +#define GPIO_PIN13_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN13_INT_TYPE_GET(x) (((x) & GPIO_PIN13_INT_TYPE_MASK) >> GPIO_PIN13_INT_TYPE_LSB) +#define GPIO_PIN13_INT_TYPE_SET(x) (((x) << GPIO_PIN13_INT_TYPE_LSB) & GPIO_PIN13_INT_TYPE_MASK) +#define GPIO_PIN13_PAD_DRIVER_MSB 2 +#define GPIO_PIN13_PAD_DRIVER_LSB 2 +#define GPIO_PIN13_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN13_PAD_DRIVER_GET(x) (((x) & GPIO_PIN13_PAD_DRIVER_MASK) >> GPIO_PIN13_PAD_DRIVER_LSB) +#define GPIO_PIN13_PAD_DRIVER_SET(x) (((x) << GPIO_PIN13_PAD_DRIVER_LSB) & GPIO_PIN13_PAD_DRIVER_MASK) +#define GPIO_PIN13_SOURCE_MSB 0 +#define GPIO_PIN13_SOURCE_LSB 0 +#define GPIO_PIN13_SOURCE_MASK 0x00000001 +#define GPIO_PIN13_SOURCE_GET(x) (((x) & GPIO_PIN13_SOURCE_MASK) >> GPIO_PIN13_SOURCE_LSB) +#define GPIO_PIN13_SOURCE_SET(x) (((x) << GPIO_PIN13_SOURCE_LSB) & GPIO_PIN13_SOURCE_MASK) + +#define GPIO_PIN14_ADDRESS 0x00000060 +#define GPIO_PIN14_OFFSET 0x00000060 +#define GPIO_PIN14_CONFIG_MSB 12 +#define GPIO_PIN14_CONFIG_LSB 11 +#define GPIO_PIN14_CONFIG_MASK 0x00001800 +#define GPIO_PIN14_CONFIG_GET(x) (((x) & GPIO_PIN14_CONFIG_MASK) >> GPIO_PIN14_CONFIG_LSB) +#define GPIO_PIN14_CONFIG_SET(x) (((x) << GPIO_PIN14_CONFIG_LSB) & GPIO_PIN14_CONFIG_MASK) +#define GPIO_PIN14_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN14_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN14_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN14_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN14_WAKEUP_ENABLE_MASK) >> GPIO_PIN14_WAKEUP_ENABLE_LSB) +#define GPIO_PIN14_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN14_WAKEUP_ENABLE_LSB) & GPIO_PIN14_WAKEUP_ENABLE_MASK) +#define GPIO_PIN14_INT_TYPE_MSB 9 +#define GPIO_PIN14_INT_TYPE_LSB 7 +#define GPIO_PIN14_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN14_INT_TYPE_GET(x) (((x) & GPIO_PIN14_INT_TYPE_MASK) >> GPIO_PIN14_INT_TYPE_LSB) +#define GPIO_PIN14_INT_TYPE_SET(x) (((x) << GPIO_PIN14_INT_TYPE_LSB) & GPIO_PIN14_INT_TYPE_MASK) +#define GPIO_PIN14_PAD_DRIVER_MSB 2 +#define GPIO_PIN14_PAD_DRIVER_LSB 2 +#define GPIO_PIN14_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN14_PAD_DRIVER_GET(x) (((x) & GPIO_PIN14_PAD_DRIVER_MASK) >> GPIO_PIN14_PAD_DRIVER_LSB) +#define GPIO_PIN14_PAD_DRIVER_SET(x) (((x) << GPIO_PIN14_PAD_DRIVER_LSB) & GPIO_PIN14_PAD_DRIVER_MASK) +#define GPIO_PIN14_SOURCE_MSB 0 +#define GPIO_PIN14_SOURCE_LSB 0 +#define GPIO_PIN14_SOURCE_MASK 0x00000001 +#define GPIO_PIN14_SOURCE_GET(x) (((x) & GPIO_PIN14_SOURCE_MASK) >> GPIO_PIN14_SOURCE_LSB) +#define GPIO_PIN14_SOURCE_SET(x) (((x) << GPIO_PIN14_SOURCE_LSB) & GPIO_PIN14_SOURCE_MASK) + +#define GPIO_PIN15_ADDRESS 0x00000064 +#define GPIO_PIN15_OFFSET 0x00000064 +#define GPIO_PIN15_CONFIG_MSB 12 +#define GPIO_PIN15_CONFIG_LSB 11 +#define GPIO_PIN15_CONFIG_MASK 0x00001800 +#define GPIO_PIN15_CONFIG_GET(x) (((x) & GPIO_PIN15_CONFIG_MASK) >> GPIO_PIN15_CONFIG_LSB) +#define GPIO_PIN15_CONFIG_SET(x) (((x) << GPIO_PIN15_CONFIG_LSB) & GPIO_PIN15_CONFIG_MASK) +#define GPIO_PIN15_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN15_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN15_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN15_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN15_WAKEUP_ENABLE_MASK) >> GPIO_PIN15_WAKEUP_ENABLE_LSB) +#define GPIO_PIN15_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN15_WAKEUP_ENABLE_LSB) & GPIO_PIN15_WAKEUP_ENABLE_MASK) +#define GPIO_PIN15_INT_TYPE_MSB 9 +#define GPIO_PIN15_INT_TYPE_LSB 7 +#define GPIO_PIN15_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN15_INT_TYPE_GET(x) (((x) & GPIO_PIN15_INT_TYPE_MASK) >> GPIO_PIN15_INT_TYPE_LSB) +#define GPIO_PIN15_INT_TYPE_SET(x) (((x) << GPIO_PIN15_INT_TYPE_LSB) & GPIO_PIN15_INT_TYPE_MASK) +#define GPIO_PIN15_PAD_DRIVER_MSB 2 +#define GPIO_PIN15_PAD_DRIVER_LSB 2 +#define GPIO_PIN15_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN15_PAD_DRIVER_GET(x) (((x) & GPIO_PIN15_PAD_DRIVER_MASK) >> GPIO_PIN15_PAD_DRIVER_LSB) +#define GPIO_PIN15_PAD_DRIVER_SET(x) (((x) << GPIO_PIN15_PAD_DRIVER_LSB) & GPIO_PIN15_PAD_DRIVER_MASK) +#define GPIO_PIN15_SOURCE_MSB 0 +#define GPIO_PIN15_SOURCE_LSB 0 +#define GPIO_PIN15_SOURCE_MASK 0x00000001 +#define GPIO_PIN15_SOURCE_GET(x) (((x) & GPIO_PIN15_SOURCE_MASK) >> GPIO_PIN15_SOURCE_LSB) +#define GPIO_PIN15_SOURCE_SET(x) (((x) << GPIO_PIN15_SOURCE_LSB) & GPIO_PIN15_SOURCE_MASK) + +#define GPIO_PIN16_ADDRESS 0x00000068 +#define GPIO_PIN16_OFFSET 0x00000068 +#define GPIO_PIN16_CONFIG_MSB 12 +#define GPIO_PIN16_CONFIG_LSB 11 +#define GPIO_PIN16_CONFIG_MASK 0x00001800 +#define GPIO_PIN16_CONFIG_GET(x) (((x) & GPIO_PIN16_CONFIG_MASK) >> GPIO_PIN16_CONFIG_LSB) +#define GPIO_PIN16_CONFIG_SET(x) (((x) << GPIO_PIN16_CONFIG_LSB) & GPIO_PIN16_CONFIG_MASK) +#define GPIO_PIN16_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN16_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN16_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN16_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN16_WAKEUP_ENABLE_MASK) >> GPIO_PIN16_WAKEUP_ENABLE_LSB) +#define GPIO_PIN16_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN16_WAKEUP_ENABLE_LSB) & GPIO_PIN16_WAKEUP_ENABLE_MASK) +#define GPIO_PIN16_INT_TYPE_MSB 9 +#define GPIO_PIN16_INT_TYPE_LSB 7 +#define GPIO_PIN16_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN16_INT_TYPE_GET(x) (((x) & GPIO_PIN16_INT_TYPE_MASK) >> GPIO_PIN16_INT_TYPE_LSB) +#define GPIO_PIN16_INT_TYPE_SET(x) (((x) << GPIO_PIN16_INT_TYPE_LSB) & GPIO_PIN16_INT_TYPE_MASK) +#define GPIO_PIN16_PAD_DRIVER_MSB 2 +#define GPIO_PIN16_PAD_DRIVER_LSB 2 +#define GPIO_PIN16_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN16_PAD_DRIVER_GET(x) (((x) & GPIO_PIN16_PAD_DRIVER_MASK) >> GPIO_PIN16_PAD_DRIVER_LSB) +#define GPIO_PIN16_PAD_DRIVER_SET(x) (((x) << GPIO_PIN16_PAD_DRIVER_LSB) & GPIO_PIN16_PAD_DRIVER_MASK) +#define GPIO_PIN16_SOURCE_MSB 0 +#define GPIO_PIN16_SOURCE_LSB 0 +#define GPIO_PIN16_SOURCE_MASK 0x00000001 +#define GPIO_PIN16_SOURCE_GET(x) (((x) & GPIO_PIN16_SOURCE_MASK) >> GPIO_PIN16_SOURCE_LSB) +#define GPIO_PIN16_SOURCE_SET(x) (((x) << GPIO_PIN16_SOURCE_LSB) & GPIO_PIN16_SOURCE_MASK) + +#define GPIO_PIN17_ADDRESS 0x0000006c +#define GPIO_PIN17_OFFSET 0x0000006c +#define GPIO_PIN17_CONFIG_MSB 12 +#define GPIO_PIN17_CONFIG_LSB 11 +#define GPIO_PIN17_CONFIG_MASK 0x00001800 +#define GPIO_PIN17_CONFIG_GET(x) (((x) & GPIO_PIN17_CONFIG_MASK) >> GPIO_PIN17_CONFIG_LSB) +#define GPIO_PIN17_CONFIG_SET(x) (((x) << GPIO_PIN17_CONFIG_LSB) & GPIO_PIN17_CONFIG_MASK) +#define GPIO_PIN17_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN17_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN17_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN17_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN17_WAKEUP_ENABLE_MASK) >> GPIO_PIN17_WAKEUP_ENABLE_LSB) +#define GPIO_PIN17_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN17_WAKEUP_ENABLE_LSB) & GPIO_PIN17_WAKEUP_ENABLE_MASK) +#define GPIO_PIN17_INT_TYPE_MSB 9 +#define GPIO_PIN17_INT_TYPE_LSB 7 +#define GPIO_PIN17_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN17_INT_TYPE_GET(x) (((x) & GPIO_PIN17_INT_TYPE_MASK) >> GPIO_PIN17_INT_TYPE_LSB) +#define GPIO_PIN17_INT_TYPE_SET(x) (((x) << GPIO_PIN17_INT_TYPE_LSB) & GPIO_PIN17_INT_TYPE_MASK) +#define GPIO_PIN17_PAD_DRIVER_MSB 2 +#define GPIO_PIN17_PAD_DRIVER_LSB 2 +#define GPIO_PIN17_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN17_PAD_DRIVER_GET(x) (((x) & GPIO_PIN17_PAD_DRIVER_MASK) >> GPIO_PIN17_PAD_DRIVER_LSB) +#define GPIO_PIN17_PAD_DRIVER_SET(x) (((x) << GPIO_PIN17_PAD_DRIVER_LSB) & GPIO_PIN17_PAD_DRIVER_MASK) +#define GPIO_PIN17_SOURCE_MSB 0 +#define GPIO_PIN17_SOURCE_LSB 0 +#define GPIO_PIN17_SOURCE_MASK 0x00000001 +#define GPIO_PIN17_SOURCE_GET(x) (((x) & GPIO_PIN17_SOURCE_MASK) >> GPIO_PIN17_SOURCE_LSB) +#define GPIO_PIN17_SOURCE_SET(x) (((x) << GPIO_PIN17_SOURCE_LSB) & GPIO_PIN17_SOURCE_MASK) + +#define SDIO_PIN_ADDRESS 0x00000070 +#define SDIO_PIN_OFFSET 0x00000070 +#define SDIO_PIN_PAD_PULL_MSB 3 +#define SDIO_PIN_PAD_PULL_LSB 2 +#define SDIO_PIN_PAD_PULL_MASK 0x0000000c +#define SDIO_PIN_PAD_PULL_GET(x) (((x) & SDIO_PIN_PAD_PULL_MASK) >> SDIO_PIN_PAD_PULL_LSB) +#define SDIO_PIN_PAD_PULL_SET(x) (((x) << SDIO_PIN_PAD_PULL_LSB) & SDIO_PIN_PAD_PULL_MASK) +#define SDIO_PIN_PAD_STRENGTH_MSB 1 +#define SDIO_PIN_PAD_STRENGTH_LSB 0 +#define SDIO_PIN_PAD_STRENGTH_MASK 0x00000003 +#define SDIO_PIN_PAD_STRENGTH_GET(x) (((x) & SDIO_PIN_PAD_STRENGTH_MASK) >> SDIO_PIN_PAD_STRENGTH_LSB) +#define SDIO_PIN_PAD_STRENGTH_SET(x) (((x) << SDIO_PIN_PAD_STRENGTH_LSB) & SDIO_PIN_PAD_STRENGTH_MASK) + +#define CLK_REQ_PIN_ADDRESS 0x00000074 +#define CLK_REQ_PIN_OFFSET 0x00000074 +#define CLK_REQ_PIN_ATE_OE_L_MSB 4 +#define CLK_REQ_PIN_ATE_OE_L_LSB 4 +#define CLK_REQ_PIN_ATE_OE_L_MASK 0x00000010 +#define CLK_REQ_PIN_ATE_OE_L_GET(x) (((x) & CLK_REQ_PIN_ATE_OE_L_MASK) >> CLK_REQ_PIN_ATE_OE_L_LSB) +#define CLK_REQ_PIN_ATE_OE_L_SET(x) (((x) << CLK_REQ_PIN_ATE_OE_L_LSB) & CLK_REQ_PIN_ATE_OE_L_MASK) +#define CLK_REQ_PIN_PAD_PULL_MSB 3 +#define CLK_REQ_PIN_PAD_PULL_LSB 2 +#define CLK_REQ_PIN_PAD_PULL_MASK 0x0000000c +#define CLK_REQ_PIN_PAD_PULL_GET(x) (((x) & CLK_REQ_PIN_PAD_PULL_MASK) >> CLK_REQ_PIN_PAD_PULL_LSB) +#define CLK_REQ_PIN_PAD_PULL_SET(x) (((x) << CLK_REQ_PIN_PAD_PULL_LSB) & CLK_REQ_PIN_PAD_PULL_MASK) +#define CLK_REQ_PIN_PAD_STRENGTH_MSB 1 +#define CLK_REQ_PIN_PAD_STRENGTH_LSB 0 +#define CLK_REQ_PIN_PAD_STRENGTH_MASK 0x00000003 +#define CLK_REQ_PIN_PAD_STRENGTH_GET(x) (((x) & CLK_REQ_PIN_PAD_STRENGTH_MASK) >> CLK_REQ_PIN_PAD_STRENGTH_LSB) +#define CLK_REQ_PIN_PAD_STRENGTH_SET(x) (((x) << CLK_REQ_PIN_PAD_STRENGTH_LSB) & CLK_REQ_PIN_PAD_STRENGTH_MASK) + +#define SIGMA_DELTA_ADDRESS 0x00000078 +#define SIGMA_DELTA_OFFSET 0x00000078 +#define SIGMA_DELTA_ENABLE_MSB 16 +#define SIGMA_DELTA_ENABLE_LSB 16 +#define SIGMA_DELTA_ENABLE_MASK 0x00010000 +#define SIGMA_DELTA_ENABLE_GET(x) (((x) & SIGMA_DELTA_ENABLE_MASK) >> SIGMA_DELTA_ENABLE_LSB) +#define SIGMA_DELTA_ENABLE_SET(x) (((x) << SIGMA_DELTA_ENABLE_LSB) & SIGMA_DELTA_ENABLE_MASK) +#define SIGMA_DELTA_PRESCALAR_MSB 15 +#define SIGMA_DELTA_PRESCALAR_LSB 8 +#define SIGMA_DELTA_PRESCALAR_MASK 0x0000ff00 +#define SIGMA_DELTA_PRESCALAR_GET(x) (((x) & SIGMA_DELTA_PRESCALAR_MASK) >> SIGMA_DELTA_PRESCALAR_LSB) +#define SIGMA_DELTA_PRESCALAR_SET(x) (((x) << SIGMA_DELTA_PRESCALAR_LSB) & SIGMA_DELTA_PRESCALAR_MASK) +#define SIGMA_DELTA_TARGET_MSB 7 +#define SIGMA_DELTA_TARGET_LSB 0 +#define SIGMA_DELTA_TARGET_MASK 0x000000ff +#define SIGMA_DELTA_TARGET_GET(x) (((x) & SIGMA_DELTA_TARGET_MASK) >> SIGMA_DELTA_TARGET_LSB) +#define SIGMA_DELTA_TARGET_SET(x) (((x) << SIGMA_DELTA_TARGET_LSB) & SIGMA_DELTA_TARGET_MASK) + +#define DEBUG_CONTROL_ADDRESS 0x0000007c +#define DEBUG_CONTROL_OFFSET 0x0000007c +#define DEBUG_CONTROL_OBS_OE_L_MSB 1 +#define DEBUG_CONTROL_OBS_OE_L_LSB 1 +#define DEBUG_CONTROL_OBS_OE_L_MASK 0x00000002 +#define DEBUG_CONTROL_OBS_OE_L_GET(x) (((x) & DEBUG_CONTROL_OBS_OE_L_MASK) >> DEBUG_CONTROL_OBS_OE_L_LSB) +#define DEBUG_CONTROL_OBS_OE_L_SET(x) (((x) << DEBUG_CONTROL_OBS_OE_L_LSB) & DEBUG_CONTROL_OBS_OE_L_MASK) +#define DEBUG_CONTROL_ENABLE_MSB 0 +#define DEBUG_CONTROL_ENABLE_LSB 0 +#define DEBUG_CONTROL_ENABLE_MASK 0x00000001 +#define DEBUG_CONTROL_ENABLE_GET(x) (((x) & DEBUG_CONTROL_ENABLE_MASK) >> DEBUG_CONTROL_ENABLE_LSB) +#define DEBUG_CONTROL_ENABLE_SET(x) (((x) << DEBUG_CONTROL_ENABLE_LSB) & DEBUG_CONTROL_ENABLE_MASK) + +#define DEBUG_INPUT_SEL_ADDRESS 0x00000080 +#define DEBUG_INPUT_SEL_OFFSET 0x00000080 +#define DEBUG_INPUT_SEL_SRC_MSB 3 +#define DEBUG_INPUT_SEL_SRC_LSB 0 +#define DEBUG_INPUT_SEL_SRC_MASK 0x0000000f +#define DEBUG_INPUT_SEL_SRC_GET(x) (((x) & DEBUG_INPUT_SEL_SRC_MASK) >> DEBUG_INPUT_SEL_SRC_LSB) +#define DEBUG_INPUT_SEL_SRC_SET(x) (((x) << DEBUG_INPUT_SEL_SRC_LSB) & DEBUG_INPUT_SEL_SRC_MASK) + +#define DEBUG_OUT_ADDRESS 0x00000084 +#define DEBUG_OUT_OFFSET 0x00000084 +#define DEBUG_OUT_DATA_MSB 17 +#define DEBUG_OUT_DATA_LSB 0 +#define DEBUG_OUT_DATA_MASK 0x0003ffff +#define DEBUG_OUT_DATA_GET(x) (((x) & DEBUG_OUT_DATA_MASK) >> DEBUG_OUT_DATA_LSB) +#define DEBUG_OUT_DATA_SET(x) (((x) << DEBUG_OUT_DATA_LSB) & DEBUG_OUT_DATA_MASK) + +#define LA_CONTROL_ADDRESS 0x00000088 +#define LA_CONTROL_OFFSET 0x00000088 +#define LA_CONTROL_RUN_MSB 1 +#define LA_CONTROL_RUN_LSB 1 +#define LA_CONTROL_RUN_MASK 0x00000002 +#define LA_CONTROL_RUN_GET(x) (((x) & LA_CONTROL_RUN_MASK) >> LA_CONTROL_RUN_LSB) +#define LA_CONTROL_RUN_SET(x) (((x) << LA_CONTROL_RUN_LSB) & LA_CONTROL_RUN_MASK) +#define LA_CONTROL_TRIGGERED_MSB 0 +#define LA_CONTROL_TRIGGERED_LSB 0 +#define LA_CONTROL_TRIGGERED_MASK 0x00000001 +#define LA_CONTROL_TRIGGERED_GET(x) (((x) & LA_CONTROL_TRIGGERED_MASK) >> LA_CONTROL_TRIGGERED_LSB) +#define LA_CONTROL_TRIGGERED_SET(x) (((x) << LA_CONTROL_TRIGGERED_LSB) & LA_CONTROL_TRIGGERED_MASK) + +#define LA_CLOCK_ADDRESS 0x0000008c +#define LA_CLOCK_OFFSET 0x0000008c +#define LA_CLOCK_DIV_MSB 7 +#define LA_CLOCK_DIV_LSB 0 +#define LA_CLOCK_DIV_MASK 0x000000ff +#define LA_CLOCK_DIV_GET(x) (((x) & LA_CLOCK_DIV_MASK) >> LA_CLOCK_DIV_LSB) +#define LA_CLOCK_DIV_SET(x) (((x) << LA_CLOCK_DIV_LSB) & LA_CLOCK_DIV_MASK) + +#define LA_STATUS_ADDRESS 0x00000090 +#define LA_STATUS_OFFSET 0x00000090 +#define LA_STATUS_INTERRUPT_MSB 0 +#define LA_STATUS_INTERRUPT_LSB 0 +#define LA_STATUS_INTERRUPT_MASK 0x00000001 +#define LA_STATUS_INTERRUPT_GET(x) (((x) & LA_STATUS_INTERRUPT_MASK) >> LA_STATUS_INTERRUPT_LSB) +#define LA_STATUS_INTERRUPT_SET(x) (((x) << LA_STATUS_INTERRUPT_LSB) & LA_STATUS_INTERRUPT_MASK) + +#define LA_TRIGGER_SAMPLE_ADDRESS 0x00000094 +#define LA_TRIGGER_SAMPLE_OFFSET 0x00000094 +#define LA_TRIGGER_SAMPLE_COUNT_MSB 15 +#define LA_TRIGGER_SAMPLE_COUNT_LSB 0 +#define LA_TRIGGER_SAMPLE_COUNT_MASK 0x0000ffff +#define LA_TRIGGER_SAMPLE_COUNT_GET(x) (((x) & LA_TRIGGER_SAMPLE_COUNT_MASK) >> LA_TRIGGER_SAMPLE_COUNT_LSB) +#define LA_TRIGGER_SAMPLE_COUNT_SET(x) (((x) << LA_TRIGGER_SAMPLE_COUNT_LSB) & LA_TRIGGER_SAMPLE_COUNT_MASK) + +#define LA_TRIGGER_POSITION_ADDRESS 0x00000098 +#define LA_TRIGGER_POSITION_OFFSET 0x00000098 +#define LA_TRIGGER_POSITION_VALUE_MSB 15 +#define LA_TRIGGER_POSITION_VALUE_LSB 0 +#define LA_TRIGGER_POSITION_VALUE_MASK 0x0000ffff +#define LA_TRIGGER_POSITION_VALUE_GET(x) (((x) & LA_TRIGGER_POSITION_VALUE_MASK) >> LA_TRIGGER_POSITION_VALUE_LSB) +#define LA_TRIGGER_POSITION_VALUE_SET(x) (((x) << LA_TRIGGER_POSITION_VALUE_LSB) & LA_TRIGGER_POSITION_VALUE_MASK) + +#define LA_PRE_TRIGGER_ADDRESS 0x0000009c +#define LA_PRE_TRIGGER_OFFSET 0x0000009c +#define LA_PRE_TRIGGER_COUNT_MSB 15 +#define LA_PRE_TRIGGER_COUNT_LSB 0 +#define LA_PRE_TRIGGER_COUNT_MASK 0x0000ffff +#define LA_PRE_TRIGGER_COUNT_GET(x) (((x) & LA_PRE_TRIGGER_COUNT_MASK) >> LA_PRE_TRIGGER_COUNT_LSB) +#define LA_PRE_TRIGGER_COUNT_SET(x) (((x) << LA_PRE_TRIGGER_COUNT_LSB) & LA_PRE_TRIGGER_COUNT_MASK) + +#define LA_POST_TRIGGER_ADDRESS 0x000000a0 +#define LA_POST_TRIGGER_OFFSET 0x000000a0 +#define LA_POST_TRIGGER_COUNT_MSB 15 +#define LA_POST_TRIGGER_COUNT_LSB 0 +#define LA_POST_TRIGGER_COUNT_MASK 0x0000ffff +#define LA_POST_TRIGGER_COUNT_GET(x) (((x) & LA_POST_TRIGGER_COUNT_MASK) >> LA_POST_TRIGGER_COUNT_LSB) +#define LA_POST_TRIGGER_COUNT_SET(x) (((x) << LA_POST_TRIGGER_COUNT_LSB) & LA_POST_TRIGGER_COUNT_MASK) + +#define LA_FILTER_CONTROL_ADDRESS 0x000000a4 +#define LA_FILTER_CONTROL_OFFSET 0x000000a4 +#define LA_FILTER_CONTROL_DELTA_MSB 0 +#define LA_FILTER_CONTROL_DELTA_LSB 0 +#define LA_FILTER_CONTROL_DELTA_MASK 0x00000001 +#define LA_FILTER_CONTROL_DELTA_GET(x) (((x) & LA_FILTER_CONTROL_DELTA_MASK) >> LA_FILTER_CONTROL_DELTA_LSB) +#define LA_FILTER_CONTROL_DELTA_SET(x) (((x) << LA_FILTER_CONTROL_DELTA_LSB) & LA_FILTER_CONTROL_DELTA_MASK) + +#define LA_FILTER_DATA_ADDRESS 0x000000a8 +#define LA_FILTER_DATA_OFFSET 0x000000a8 +#define LA_FILTER_DATA_MATCH_MSB 17 +#define LA_FILTER_DATA_MATCH_LSB 0 +#define LA_FILTER_DATA_MATCH_MASK 0x0003ffff +#define LA_FILTER_DATA_MATCH_GET(x) (((x) & LA_FILTER_DATA_MATCH_MASK) >> LA_FILTER_DATA_MATCH_LSB) +#define LA_FILTER_DATA_MATCH_SET(x) (((x) << LA_FILTER_DATA_MATCH_LSB) & LA_FILTER_DATA_MATCH_MASK) + +#define LA_FILTER_WILDCARD_ADDRESS 0x000000ac +#define LA_FILTER_WILDCARD_OFFSET 0x000000ac +#define LA_FILTER_WILDCARD_MATCH_MSB 17 +#define LA_FILTER_WILDCARD_MATCH_LSB 0 +#define LA_FILTER_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_FILTER_WILDCARD_MATCH_GET(x) (((x) & LA_FILTER_WILDCARD_MATCH_MASK) >> LA_FILTER_WILDCARD_MATCH_LSB) +#define LA_FILTER_WILDCARD_MATCH_SET(x) (((x) << LA_FILTER_WILDCARD_MATCH_LSB) & LA_FILTER_WILDCARD_MATCH_MASK) + +#define LA_TRIGGERA_DATA_ADDRESS 0x000000b0 +#define LA_TRIGGERA_DATA_OFFSET 0x000000b0 +#define LA_TRIGGERA_DATA_MATCH_MSB 17 +#define LA_TRIGGERA_DATA_MATCH_LSB 0 +#define LA_TRIGGERA_DATA_MATCH_MASK 0x0003ffff +#define LA_TRIGGERA_DATA_MATCH_GET(x) (((x) & LA_TRIGGERA_DATA_MATCH_MASK) >> LA_TRIGGERA_DATA_MATCH_LSB) +#define LA_TRIGGERA_DATA_MATCH_SET(x) (((x) << LA_TRIGGERA_DATA_MATCH_LSB) & LA_TRIGGERA_DATA_MATCH_MASK) + +#define LA_TRIGGERA_WILDCARD_ADDRESS 0x000000b4 +#define LA_TRIGGERA_WILDCARD_OFFSET 0x000000b4 +#define LA_TRIGGERA_WILDCARD_MATCH_MSB 17 +#define LA_TRIGGERA_WILDCARD_MATCH_LSB 0 +#define LA_TRIGGERA_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_TRIGGERA_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERA_WILDCARD_MATCH_MASK) >> LA_TRIGGERA_WILDCARD_MATCH_LSB) +#define LA_TRIGGERA_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERA_WILDCARD_MATCH_LSB) & LA_TRIGGERA_WILDCARD_MATCH_MASK) + +#define LA_TRIGGERB_DATA_ADDRESS 0x000000b8 +#define LA_TRIGGERB_DATA_OFFSET 0x000000b8 +#define LA_TRIGGERB_DATA_MATCH_MSB 17 +#define LA_TRIGGERB_DATA_MATCH_LSB 0 +#define LA_TRIGGERB_DATA_MATCH_MASK 0x0003ffff +#define LA_TRIGGERB_DATA_MATCH_GET(x) (((x) & LA_TRIGGERB_DATA_MATCH_MASK) >> LA_TRIGGERB_DATA_MATCH_LSB) +#define LA_TRIGGERB_DATA_MATCH_SET(x) (((x) << LA_TRIGGERB_DATA_MATCH_LSB) & LA_TRIGGERB_DATA_MATCH_MASK) + +#define LA_TRIGGERB_WILDCARD_ADDRESS 0x000000bc +#define LA_TRIGGERB_WILDCARD_OFFSET 0x000000bc +#define LA_TRIGGERB_WILDCARD_MATCH_MSB 17 +#define LA_TRIGGERB_WILDCARD_MATCH_LSB 0 +#define LA_TRIGGERB_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_TRIGGERB_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERB_WILDCARD_MATCH_MASK) >> LA_TRIGGERB_WILDCARD_MATCH_LSB) +#define LA_TRIGGERB_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERB_WILDCARD_MATCH_LSB) & LA_TRIGGERB_WILDCARD_MATCH_MASK) + +#define LA_TRIGGER_ADDRESS 0x000000c0 +#define LA_TRIGGER_OFFSET 0x000000c0 +#define LA_TRIGGER_EVENT_MSB 2 +#define LA_TRIGGER_EVENT_LSB 0 +#define LA_TRIGGER_EVENT_MASK 0x00000007 +#define LA_TRIGGER_EVENT_GET(x) (((x) & LA_TRIGGER_EVENT_MASK) >> LA_TRIGGER_EVENT_LSB) +#define LA_TRIGGER_EVENT_SET(x) (((x) << LA_TRIGGER_EVENT_LSB) & LA_TRIGGER_EVENT_MASK) + +#define LA_FIFO_ADDRESS 0x000000c4 +#define LA_FIFO_OFFSET 0x000000c4 +#define LA_FIFO_FULL_MSB 1 +#define LA_FIFO_FULL_LSB 1 +#define LA_FIFO_FULL_MASK 0x00000002 +#define LA_FIFO_FULL_GET(x) (((x) & LA_FIFO_FULL_MASK) >> LA_FIFO_FULL_LSB) +#define LA_FIFO_FULL_SET(x) (((x) << LA_FIFO_FULL_LSB) & LA_FIFO_FULL_MASK) +#define LA_FIFO_EMPTY_MSB 0 +#define LA_FIFO_EMPTY_LSB 0 +#define LA_FIFO_EMPTY_MASK 0x00000001 +#define LA_FIFO_EMPTY_GET(x) (((x) & LA_FIFO_EMPTY_MASK) >> LA_FIFO_EMPTY_LSB) +#define LA_FIFO_EMPTY_SET(x) (((x) << LA_FIFO_EMPTY_LSB) & LA_FIFO_EMPTY_MASK) + +#define LA_ADDRESS 0x000000c8 +#define LA_OFFSET 0x000000c8 +#define LA_DATA_MSB 17 +#define LA_DATA_LSB 0 +#define LA_DATA_MASK 0x0003ffff +#define LA_DATA_GET(x) (((x) & LA_DATA_MASK) >> LA_DATA_LSB) +#define LA_DATA_SET(x) (((x) << LA_DATA_LSB) & LA_DATA_MASK) + +#define ANT_PIN_ADDRESS 0x000000d0 +#define ANT_PIN_OFFSET 0x000000d0 +#define ANT_PIN_PAD_PULL_MSB 3 +#define ANT_PIN_PAD_PULL_LSB 2 +#define ANT_PIN_PAD_PULL_MASK 0x0000000c +#define ANT_PIN_PAD_PULL_GET(x) (((x) & ANT_PIN_PAD_PULL_MASK) >> ANT_PIN_PAD_PULL_LSB) +#define ANT_PIN_PAD_PULL_SET(x) (((x) << ANT_PIN_PAD_PULL_LSB) & ANT_PIN_PAD_PULL_MASK) +#define ANT_PIN_PAD_STRENGTH_MSB 1 +#define ANT_PIN_PAD_STRENGTH_LSB 0 +#define ANT_PIN_PAD_STRENGTH_MASK 0x00000003 +#define ANT_PIN_PAD_STRENGTH_GET(x) (((x) & ANT_PIN_PAD_STRENGTH_MASK) >> ANT_PIN_PAD_STRENGTH_LSB) +#define ANT_PIN_PAD_STRENGTH_SET(x) (((x) << ANT_PIN_PAD_STRENGTH_LSB) & ANT_PIN_PAD_STRENGTH_MASK) + +#define ANTD_PIN_ADDRESS 0x000000d4 +#define ANTD_PIN_OFFSET 0x000000d4 +#define ANTD_PIN_PAD_PULL_MSB 1 +#define ANTD_PIN_PAD_PULL_LSB 0 +#define ANTD_PIN_PAD_PULL_MASK 0x00000003 +#define ANTD_PIN_PAD_PULL_GET(x) (((x) & ANTD_PIN_PAD_PULL_MASK) >> ANTD_PIN_PAD_PULL_LSB) +#define ANTD_PIN_PAD_PULL_SET(x) (((x) << ANTD_PIN_PAD_PULL_LSB) & ANTD_PIN_PAD_PULL_MASK) + +#define GPIO_PIN_ADDRESS 0x000000d8 +#define GPIO_PIN_OFFSET 0x000000d8 +#define GPIO_PIN_PAD_PULL_MSB 3 +#define GPIO_PIN_PAD_PULL_LSB 2 +#define GPIO_PIN_PAD_PULL_MASK 0x0000000c +#define GPIO_PIN_PAD_PULL_GET(x) (((x) & GPIO_PIN_PAD_PULL_MASK) >> GPIO_PIN_PAD_PULL_LSB) +#define GPIO_PIN_PAD_PULL_SET(x) (((x) << GPIO_PIN_PAD_PULL_LSB) & GPIO_PIN_PAD_PULL_MASK) +#define GPIO_PIN_PAD_STRENGTH_MSB 1 +#define GPIO_PIN_PAD_STRENGTH_LSB 0 +#define GPIO_PIN_PAD_STRENGTH_MASK 0x00000003 +#define GPIO_PIN_PAD_STRENGTH_GET(x) (((x) & GPIO_PIN_PAD_STRENGTH_MASK) >> GPIO_PIN_PAD_STRENGTH_LSB) +#define GPIO_PIN_PAD_STRENGTH_SET(x) (((x) << GPIO_PIN_PAD_STRENGTH_LSB) & GPIO_PIN_PAD_STRENGTH_MASK) + +#define GPIO_H_PIN_ADDRESS 0x000000dc +#define GPIO_H_PIN_OFFSET 0x000000dc +#define GPIO_H_PIN_PAD_PULL_MSB 1 +#define GPIO_H_PIN_PAD_PULL_LSB 0 +#define GPIO_H_PIN_PAD_PULL_MASK 0x00000003 +#define GPIO_H_PIN_PAD_PULL_GET(x) (((x) & GPIO_H_PIN_PAD_PULL_MASK) >> GPIO_H_PIN_PAD_PULL_LSB) +#define GPIO_H_PIN_PAD_PULL_SET(x) (((x) << GPIO_H_PIN_PAD_PULL_LSB) & GPIO_H_PIN_PAD_PULL_MASK) + +#define BT_PIN_ADDRESS 0x000000e0 +#define BT_PIN_OFFSET 0x000000e0 +#define BT_PIN_PAD_PULL_MSB 3 +#define BT_PIN_PAD_PULL_LSB 2 +#define BT_PIN_PAD_PULL_MASK 0x0000000c +#define BT_PIN_PAD_PULL_GET(x) (((x) & BT_PIN_PAD_PULL_MASK) >> BT_PIN_PAD_PULL_LSB) +#define BT_PIN_PAD_PULL_SET(x) (((x) << BT_PIN_PAD_PULL_LSB) & BT_PIN_PAD_PULL_MASK) +#define BT_PIN_PAD_STRENGTH_MSB 1 +#define BT_PIN_PAD_STRENGTH_LSB 0 +#define BT_PIN_PAD_STRENGTH_MASK 0x00000003 +#define BT_PIN_PAD_STRENGTH_GET(x) (((x) & BT_PIN_PAD_STRENGTH_MASK) >> BT_PIN_PAD_STRENGTH_LSB) +#define BT_PIN_PAD_STRENGTH_SET(x) (((x) << BT_PIN_PAD_STRENGTH_LSB) & BT_PIN_PAD_STRENGTH_MASK) + +#define BT_WLAN_PIN_ADDRESS 0x000000e4 +#define BT_WLAN_PIN_OFFSET 0x000000e4 +#define BT_WLAN_PIN_PAD_PULL_MSB 1 +#define BT_WLAN_PIN_PAD_PULL_LSB 0 +#define BT_WLAN_PIN_PAD_PULL_MASK 0x00000003 +#define BT_WLAN_PIN_PAD_PULL_GET(x) (((x) & BT_WLAN_PIN_PAD_PULL_MASK) >> BT_WLAN_PIN_PAD_PULL_LSB) +#define BT_WLAN_PIN_PAD_PULL_SET(x) (((x) << BT_WLAN_PIN_PAD_PULL_LSB) & BT_WLAN_PIN_PAD_PULL_MASK) + +#define SI_UART_PIN_ADDRESS 0x000000e8 +#define SI_UART_PIN_OFFSET 0x000000e8 +#define SI_UART_PIN_PAD_PULL_MSB 3 +#define SI_UART_PIN_PAD_PULL_LSB 2 +#define SI_UART_PIN_PAD_PULL_MASK 0x0000000c +#define SI_UART_PIN_PAD_PULL_GET(x) (((x) & SI_UART_PIN_PAD_PULL_MASK) >> SI_UART_PIN_PAD_PULL_LSB) +#define SI_UART_PIN_PAD_PULL_SET(x) (((x) << SI_UART_PIN_PAD_PULL_LSB) & SI_UART_PIN_PAD_PULL_MASK) +#define SI_UART_PIN_PAD_STRENGTH_MSB 1 +#define SI_UART_PIN_PAD_STRENGTH_LSB 0 +#define SI_UART_PIN_PAD_STRENGTH_MASK 0x00000003 +#define SI_UART_PIN_PAD_STRENGTH_GET(x) (((x) & SI_UART_PIN_PAD_STRENGTH_MASK) >> SI_UART_PIN_PAD_STRENGTH_LSB) +#define SI_UART_PIN_PAD_STRENGTH_SET(x) (((x) << SI_UART_PIN_PAD_STRENGTH_LSB) & SI_UART_PIN_PAD_STRENGTH_MASK) + +#define CLK32K_PIN_ADDRESS 0x000000ec +#define CLK32K_PIN_OFFSET 0x000000ec +#define CLK32K_PIN_PAD_PULL_MSB 1 +#define CLK32K_PIN_PAD_PULL_LSB 0 +#define CLK32K_PIN_PAD_PULL_MASK 0x00000003 +#define CLK32K_PIN_PAD_PULL_GET(x) (((x) & CLK32K_PIN_PAD_PULL_MASK) >> CLK32K_PIN_PAD_PULL_LSB) +#define CLK32K_PIN_PAD_PULL_SET(x) (((x) << CLK32K_PIN_PAD_PULL_LSB) & CLK32K_PIN_PAD_PULL_MASK) + +#define RESET_TUPLE_STATUS_ADDRESS 0x000000f0 +#define RESET_TUPLE_STATUS_OFFSET 0x000000f0 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7 +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0 +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct gpio_reg_reg_s { + volatile unsigned int gpio_out; + volatile unsigned int gpio_out_w1ts; + volatile unsigned int gpio_out_w1tc; + volatile unsigned int gpio_enable; + volatile unsigned int gpio_enable_w1ts; + volatile unsigned int gpio_enable_w1tc; + volatile unsigned int gpio_in; + volatile unsigned int gpio_status; + volatile unsigned int gpio_status_w1ts; + volatile unsigned int gpio_status_w1tc; + volatile unsigned int gpio_pin0; + volatile unsigned int gpio_pin1; + volatile unsigned int gpio_pin2; + volatile unsigned int gpio_pin3; + volatile unsigned int gpio_pin4; + volatile unsigned int gpio_pin5; + volatile unsigned int gpio_pin6; + volatile unsigned int gpio_pin7; + volatile unsigned int gpio_pin8; + volatile unsigned int gpio_pin9; + volatile unsigned int gpio_pin10; + volatile unsigned int gpio_pin11; + volatile unsigned int gpio_pin12; + volatile unsigned int gpio_pin13; + volatile unsigned int gpio_pin14; + volatile unsigned int gpio_pin15; + volatile unsigned int gpio_pin16; + volatile unsigned int gpio_pin17; + volatile unsigned int sdio_pin; + volatile unsigned int clk_req_pin; + volatile unsigned int sigma_delta; + volatile unsigned int debug_control; + volatile unsigned int debug_input_sel; + volatile unsigned int debug_out; + volatile unsigned int la_control; + volatile unsigned int la_clock; + volatile unsigned int la_status; + volatile unsigned int la_trigger_sample; + volatile unsigned int la_trigger_position; + volatile unsigned int la_pre_trigger; + volatile unsigned int la_post_trigger; + volatile unsigned int la_filter_control; + volatile unsigned int la_filter_data; + volatile unsigned int la_filter_wildcard; + volatile unsigned int la_triggera_data; + volatile unsigned int la_triggera_wildcard; + volatile unsigned int la_triggerb_data; + volatile unsigned int la_triggerb_wildcard; + volatile unsigned int la_trigger; + volatile unsigned int la_fifo; + volatile unsigned int la[2]; + volatile unsigned int ant_pin; + volatile unsigned int antd_pin; + volatile unsigned int gpio_pin; + volatile unsigned int gpio_h_pin; + volatile unsigned int bt_pin; + volatile unsigned int bt_wlan_pin; + volatile unsigned int si_uart_pin; + volatile unsigned int clk32k_pin; + volatile unsigned int reset_tuple_status; +} gpio_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _GPIO_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/hif.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/hif.c --- linux-2.6.26/drivers/net/wireless/ath6k22/hif.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/hif.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,739 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// HIF layer reference implementation for Linux Native MMC stack +// +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include +/* by default setup a bounce buffer for the data packets, if the underlying host controller driver + does not use DMA you may be able to skip this step and save the memory allocation and transfer time */ +#define HIF_USE_DMA_BOUNCE_BUFFER 1 +#include "hif_internal.h" + + +static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id); +static void hifDeviceRemoved(struct sdio_func *func); +static HIF_DEVICE *addHifDevice(struct sdio_func *func); +static HIF_DEVICE *getHifDevice(struct sdio_func *func); +static void delHifDevice(HIF_DEVICE * device); + + + +/* ------ Static Variables ------ */ +static const struct sdio_device_id ar6k_id_table[] = { + { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x0)) }, + { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x1)) }, + { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0)) }, + { /* null */ }, +}; +MODULE_DEVICE_TABLE(sdio, ar6k_id_table); + +static struct sdio_driver ar6k_driver = { + .name = "ar6k_wlan", + .id_table = ar6k_id_table, + .probe = hifDeviceInserted, + .remove = hifDeviceRemoved, +}; +/* make sure we only unregister when registered. */ +static int registered = 0; + +OSDRV_CALLBACKS osdrvCallbacks; +extern A_UINT32 onebitmode; +extern A_UINT32 busspeedlow; +extern A_UINT32 debughif; + +#ifdef DEBUG +#define ATH_DEBUG_ERROR 1 +#define ATH_DEBUG_WARN 2 +#define ATH_DEBUG_TRACE 3 +#define _AR_DEBUG_PRINTX_ARG(arg...) arg +#define AR_DEBUG_PRINTF(lvl, args)\ + {if (lvl <= debughif)\ + A_PRINTF(KERN_ALERT _AR_DEBUG_PRINTX_ARG args);\ + } +#define AR_DEBUG_ASSERT(test) do { \ + if (!(test)) { \ + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test)); \ + } \ +} while(0) +#else +#define AR_DEBUG_PRINTF(lvl, args) +#define AR_DEBUG_ASSERT(test) +#endif + +static BUS_REQUEST *hifAllocateBusRequest(HIF_DEVICE *device); +static void hifFreeBusRequest(HIF_DEVICE *device, BUS_REQUEST *busrequest); +static void ResetAllCards(void); + +/* ------ Functions ------ */ +A_STATUS HIFInit(OSDRV_CALLBACKS *callbacks) +{ + int status; + AR_DEBUG_ASSERT(callbacks != NULL); + + /* store the callback handlers */ + osdrvCallbacks = *callbacks; + + /* Register with bus driver core */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFInit registering\n")); + registered = 1; + status = sdio_register_driver(&ar6k_driver); + AR_DEBUG_ASSERT(status==0); + + if (status != 0) { + return A_ERROR; + } + + return A_OK; + +} + +static A_STATUS +__HIFReadWrite(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length, + A_UINT32 request, + void *context) +{ + A_UINT8 opcode; + A_STATUS status = A_OK; + int ret; + A_UINT8 *tbuffer; + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device: 0x%p, buffer:0x%p\n", device, buffer)); + + do { + if (request & HIF_EXTENDED_IO) { + //AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Command type: CMD53\n")); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid command type: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + + if (request & HIF_BLOCK_BASIS) { + /* round to whole block length size */ + length = (length / HIF_MBOX_BLOCK_SIZE) * HIF_MBOX_BLOCK_SIZE; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Block mode (BlockLen: %d)\n", + length)); + } else if (request & HIF_BYTE_BASIS) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Byte mode (BlockLen: %d)\n", + length)); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid data mode: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + +#if 0 + /* useful for checking register accesses */ + if (length & 0x3) { + A_PRINTF(KERN_ALERT"AR6000: HIF (%s) is not a multiple of 4 bytes, addr:0x%X, len:%d\n", + request & HIF_WRITE ? "write":"read", address, length); + } +#endif + + if ((address >= HIF_MBOX_START_ADDR(0)) && + (address <= HIF_MBOX_END_ADDR(3))) + { + + AR_DEBUG_ASSERT(length <= HIF_MBOX_WIDTH); + + /* + * Mailbox write. Adjust the address so that the last byte + * falls on the EOM address. + */ + address += (HIF_MBOX_WIDTH - length); + } + + if (request & HIF_FIXED_ADDRESS) { + opcode = CMD53_FIXED_ADDRESS; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Address mode: Fixed 0x%X\n", address)); + } else if (request & HIF_INCREMENTAL_ADDRESS) { + opcode = CMD53_INCR_ADDRESS; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Address mode: Incremental 0x%X\n", address)); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid address mode: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + + if (request & HIF_WRITE) { +#if HIF_USE_DMA_BOUNCE_BUFFER + AR_DEBUG_ASSERT(device->dma_buffer != NULL); + tbuffer = device->dma_buffer; + /* copy the write data to the dma buffer */ + AR_DEBUG_ASSERT(length <= HIF_DMA_BUFFER_SIZE); + memcpy(tbuffer, buffer, length); +#else + tbuffer = buffer; +#endif + if (opcode == CMD53_FIXED_ADDRESS) { + ret = sdio_writesb(device->func, address, tbuffer, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: writesb ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } else { + ret = sdio_memcpy_toio(device->func, address, tbuffer, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: writeio ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } + } else if (request & HIF_READ) { +#if HIF_USE_DMA_BOUNCE_BUFFER + AR_DEBUG_ASSERT(device->dma_buffer != NULL); + AR_DEBUG_ASSERT(length <= HIF_DMA_BUFFER_SIZE); + tbuffer = device->dma_buffer; +#else + tbuffer = buffer; +#endif + if (opcode == CMD53_FIXED_ADDRESS) { + ret = sdio_readsb(device->func, tbuffer, address, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: readsb ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } else { + ret = sdio_memcpy_fromio(device->func, tbuffer, address, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: readio ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } +#if HIF_USE_DMA_BOUNCE_BUFFER + /* copy the read data from the dma buffer */ + memcpy(buffer, tbuffer, length); +#endif + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid direction: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + + if (ret) { + status = A_ERROR; + } + } while (FALSE); + + return status; +} + +/* queue a read/write request */ +A_STATUS +HIFReadWrite(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length, + A_UINT32 request, + void *context) +{ + A_STATUS status = A_OK; + unsigned long flags; + BUS_REQUEST *busrequest; + BUS_REQUEST *async; + BUS_REQUEST *active; + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device: %p\n", device)); + + do { + if ((request & HIF_ASYNCHRONOUS) || (request & HIF_SYNCHRONOUS)){ + /* serialize all requests through the async thread */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Execution mode: %s\n", (request & HIF_ASYNCHRONOUS)?"Async":"Synch")); + busrequest = hifAllocateBusRequest(device); + if (busrequest == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: no async bus requests available\n")); + return A_ERROR; + } + spin_lock_irqsave(&device->asynclock, flags); + busrequest->address = address; + busrequest->buffer = buffer; + busrequest->length = length; + busrequest->request = request; + busrequest->context = context; + /* add to async list */ + active = device->asyncreq; + if (active == NULL) { + device->asyncreq = busrequest; + device->asyncreq->inusenext = NULL; + } else { + for (async = device->asyncreq; + async != NULL; + async = async->inusenext) { + active = async; + } + active->inusenext = busrequest; + busrequest->inusenext = NULL; + } + spin_unlock_irqrestore(&device->asynclock, flags); + if (request & HIF_SYNCHRONOUS) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: queued sync req: 0x%X\n", (unsigned int)busrequest)); + + /* wait for completion */ + up(&device->sem_async); + if (down_interruptible(&busrequest->sem_req) != 0) { + /* interrupted, exit */ + return A_ERROR; + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: sync return freeing 0x%X: 0x%X\n", + (unsigned int)busrequest, busrequest->status)); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: freeing req: 0x%X\n", (unsigned int)request)); + hifFreeBusRequest(device, busrequest); + return busrequest->status; + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: queued async req: 0x%X\n", (unsigned int)busrequest)); + up(&device->sem_async); + return A_PENDING; + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid execution mode: 0x%08x\n", (unsigned int)request)); + status = A_EINVAL; + break; + } + } while(0); + + return status; +} +/* thread to serialize all requests, both sync and async */ +static int async_task(void *param) + { + HIF_DEVICE *device; + BUS_REQUEST *request; + A_STATUS status; + unsigned long flags; + + device = (HIF_DEVICE *)param; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task\n")); + set_current_state(TASK_INTERRUPTIBLE); + while(!device->async_shutdown) { + /* wait for work */ + if (down_interruptible(&device->sem_async) != 0) { + /* interrupted, exit */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task interrupted\n")); + break; + } + if (device->async_shutdown) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task stopping\n")); + break; + } + /* we want to hold the host over multiple cmds if possible, but holding the host blocks card interrupts */ + sdio_claim_host(device->func); + spin_lock_irqsave(&device->asynclock, flags); + /* pull the request to work on */ + while (device->asyncreq != NULL) { + request = device->asyncreq; + if (request->inusenext != NULL) { + device->asyncreq = request->inusenext; + } else { + device->asyncreq = NULL; + } + spin_unlock_irqrestore(&device->asynclock, flags); + /* call HIFReadWrite in sync mode to do the work */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task processing req: 0x%X\n", (unsigned int)request)); + status = __HIFReadWrite(device, request->address, request->buffer, + request->length, request->request & ~HIF_SYNCHRONOUS, NULL); + if (request->request & HIF_ASYNCHRONOUS) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task completion routine req: 0x%X\n", (unsigned int)request)); + device->htcCallbacks.rwCompletionHandler(request->context, status); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task freeing req: 0x%X\n", (unsigned int)request)); + hifFreeBusRequest(device, request); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task upping req: 0x%X\n", (unsigned int)request)); + request->status = status; + up(&request->sem_req); + } + spin_lock_irqsave(&device->asynclock, flags); + } + spin_unlock_irqrestore(&device->asynclock, flags); + sdio_release_host(device->func); + } + + complete_and_exit(&device->async_completion, 0); + return 0; + } + +A_STATUS +HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode, + void *config, A_UINT32 configLen) +{ + A_UINT32 count; + + switch(opcode) { + case HIF_DEVICE_GET_MBOX_BLOCK_SIZE: + ((A_UINT32 *)config)[0] = HIF_MBOX0_BLOCK_SIZE; + ((A_UINT32 *)config)[1] = HIF_MBOX1_BLOCK_SIZE; + ((A_UINT32 *)config)[2] = HIF_MBOX2_BLOCK_SIZE; + ((A_UINT32 *)config)[3] = HIF_MBOX3_BLOCK_SIZE; + break; + + case HIF_DEVICE_GET_MBOX_ADDR: + for (count = 0; count < 4; count ++) { + ((A_UINT32 *)config)[count] = HIF_MBOX_START_ADDR(count); + } + break; + case HIF_DEVICE_GET_IRQ_PROC_MODE: + *((HIF_DEVICE_IRQ_PROCESSING_MODE *)config) = HIF_DEVICE_IRQ_SYNC_ONLY; + break; + default: + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, + ("AR6000: Unsupported configuration opcode: %d\n", opcode)); + return A_ERROR; + } + + return A_OK; +} + +void +HIFShutDownDevice(HIF_DEVICE *device) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +HIFShutDownDevice\n")); + if (device != NULL) { + AR_DEBUG_ASSERT(device->func != NULL); + } else { + /* since we are unloading the driver anyways, reset all cards in case the SDIO card + * is externally powered and we are unloading the SDIO stack. This avoids the problem when + * the SDIO stack is reloaded and attempts are made to re-enumerate a card that is already + * enumerated */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFShutDownDevice, resetting\n")); + ResetAllCards(); + + /* Unregister with bus driver core */ + if (registered) { + registered = 0; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Unregistering with the bus driver\n")); + sdio_unregister_driver(&ar6k_driver); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Unregistered\n")); + } + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -HIFShutDownDevice\n")); +} + +static void +hifIRQHandler(struct sdio_func *func) +{ + A_STATUS status; + HIF_DEVICE *device; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifIRQHandler\n")); + + device = getHifDevice(func); + /* release the host during ints so we can pick it back up when we process cmds */ + sdio_release_host(device->func); + status = device->htcCallbacks.dsrHandler(device->htcCallbacks.context); + sdio_claim_host(device->func); + AR_DEBUG_ASSERT(status == A_OK); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifIRQHandler\n")); +} + +/* handle HTC startup via thread*/ +static int startup_task(void *param) +{ + HIF_DEVICE *device; + + device = (HIF_DEVICE *)param; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: call HTC from startup_task\n")); + /* start up inform DRV layer */ + if ((osdrvCallbacks.deviceInsertedHandler(osdrvCallbacks.context,device)) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device rejected\n")); + } + return 0; +} + +static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id) +{ + int ret; + HIF_DEVICE * device; + int count; + struct task_struct* startup_task_struct; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: hifDeviceInserted, Function: 0x%X, Vendor ID: 0x%X, Device ID: 0x%X, block size: 0x%X/0x%X\n", + func->num, func->vendor, func->device, func->max_blksize, func->cur_blksize)); + + addHifDevice(func); + device = getHifDevice(func); + + spin_lock_init(&device->lock); + + spin_lock_init(&device->asynclock); + + /* enable the SDIO function */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: claim\n")); + sdio_claim_host(func); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: enable\n")); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + /* give us some time to enable, in ms */ + func->enable_timeout = 100; +#endif + + ret = sdio_enable_func(func); + if (ret) { + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to enable AR6K: 0x%X, timeout: %d\n", + __FUNCTION__, ret, func->enable_timeout)); +#else + + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to enable AR6K: 0x%X\n", + __FUNCTION__, ret)); +#endif + sdio_release_host(func); + return ret; + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: set block size 0x%X\n", HIF_MBOX_BLOCK_SIZE)); + ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE); + sdio_release_host(func); + if (ret) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to set block size 0x%x AR6K: 0x%X\n", + __FUNCTION__, HIF_MBOX_BLOCK_SIZE, ret)); + sdio_release_host(func); + return ret; + } + /* Initialize the bus requests to be used later */ + A_MEMZERO(device->busRequest, sizeof(device->busRequest)); + for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) { + sema_init(&device->busRequest[count].sem_req, 0); + hifFreeBusRequest(device, &device->busRequest[count]); + } + + /* create async I/O thread */ + device->async_shutdown = 0; + device->async_task = kthread_create(async_task, + (void *)device, + "AR6K Async"); + if (device->async_task == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create async task\n", __FUNCTION__)); + sdio_release_host(func); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start async task\n")); + sema_init(&device->sem_async, 0); + wake_up_process(device->async_task ); + + /* create startup thread */ + startup_task_struct = kthread_create(startup_task, + (void *)device, + "AR6K startup"); + if (startup_task_struct == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create startup task\n", __FUNCTION__)); + sdio_release_host(func); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start startup task\n")); + wake_up_process(startup_task_struct); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: return %d\n", ret)); + return ret; +} + + +void +HIFAckInterrupt(HIF_DEVICE *device) +{ + AR_DEBUG_ASSERT(device != NULL); + + /* Acknowledge our function IRQ */ +} + +void +HIFUnMaskInterrupt(HIF_DEVICE *device) +{ + int ret;; + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFUnMaskInterrupt\n")); + + /* Register the IRQ Handler */ + sdio_claim_host(device->func); + ret = sdio_claim_irq(device->func, hifIRQHandler); + sdio_release_host(device->func); + AR_DEBUG_ASSERT(ret == 0); +} + +void HIFMaskInterrupt(HIF_DEVICE *device) +{ + int ret;; + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFMaskInterrupt\n")); + + /* Mask our function IRQ */ + sdio_claim_host(device->func); + ret = sdio_release_irq(device->func); + sdio_release_host(device->func); + AR_DEBUG_ASSERT(ret == 0); +} + +static BUS_REQUEST *hifAllocateBusRequest(HIF_DEVICE *device) +{ + BUS_REQUEST *busrequest; + unsigned long flag; + + /* Acquire lock */ + spin_lock_irqsave(&device->lock, flag); + + /* Remove first in list */ + if((busrequest = device->s_busRequestFreeQueue) != NULL) + { + device->s_busRequestFreeQueue = busrequest->next; + } + + /* Release lock */ + spin_unlock_irqrestore(&device->lock, flag); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: hifAllocateBusRequest: 0x%p\n", busrequest)); + return busrequest; +} + +static void +hifFreeBusRequest(HIF_DEVICE *device, BUS_REQUEST *busrequest) +{ + unsigned long flag; + + AR_DEBUG_ASSERT(busrequest != NULL); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: hifFreeBusRequest: 0x%p\n", busrequest)); + /* Acquire lock */ + spin_lock_irqsave(&device->lock, flag); + + + /* Insert first in list */ + busrequest->next = device->s_busRequestFreeQueue; + busrequest->inusenext = NULL; + device->s_busRequestFreeQueue = busrequest; + + /* Release lock */ + spin_unlock_irqrestore(&device->lock, flag); +} + +static void hifDeviceRemoved(struct sdio_func *func) +{ + A_STATUS status = A_OK; + HIF_DEVICE *device; + int ret; + AR_DEBUG_ASSERT(func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDeviceRemoved\n")); + device = getHifDevice(func); + if (device->claimedContext != NULL) { + status = osdrvCallbacks.deviceRemovedHandler(device->claimedContext, device); + } + + if (device->async_task != NULL) { + init_completion(&device->async_completion); + device->async_shutdown = 1; + up(&device->sem_async); + wait_for_completion(&device->async_completion); + device->async_task = NULL; + } + /* Disable the card */ + sdio_claim_host(device->func); + ret = sdio_disable_func(device->func); + sdio_release_host(device->func); + delHifDevice(device); + AR_DEBUG_ASSERT(status == A_OK); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifDeviceRemoved\n")); +} + + +static HIF_DEVICE * +addHifDevice(struct sdio_func *func) +{ + HIF_DEVICE *hifdevice; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice\n")); + AR_DEBUG_ASSERT(func != NULL); + hifdevice = (HIF_DEVICE *)kzalloc(sizeof(HIF_DEVICE), GFP_KERNEL); + AR_DEBUG_ASSERT(hifdevice != NULL); +#if HIF_USE_DMA_BOUNCE_BUFFER + hifdevice->dma_buffer = kmalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL); + AR_DEBUG_ASSERT(hifdevice->dma_buffer != NULL); +#endif + hifdevice->func = func; + sdio_set_drvdata(func, hifdevice); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice; 0x%p\n", hifdevice)); + return hifdevice; +} + +static HIF_DEVICE * +getHifDevice(struct sdio_func *func) +{ + AR_DEBUG_ASSERT(func != NULL); + return (HIF_DEVICE *)sdio_get_drvdata(func); +} + +static void +delHifDevice(HIF_DEVICE * device) +{ + AR_DEBUG_ASSERT(device!= NULL); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: delHifDevice; 0x%p\n", device)); + if (device->dma_buffer != NULL) { + kfree(device->dma_buffer); + } + kfree(device); +} + +static void ResetAllCards(void) +{ +} + +void HIFClaimDevice(HIF_DEVICE *device, void *context) +{ + device->claimedContext = context; +} + +void HIFReleaseDevice(HIF_DEVICE *device) +{ + device->claimedContext = NULL; +} + +A_STATUS HIFAttachHTC(HIF_DEVICE *device, HTC_CALLBACKS *callbacks) +{ + if (device->htcCallbacks.context != NULL) { + /* already in use! */ + return A_ERROR; + } + device->htcCallbacks = *callbacks; + return A_OK; +} + +void HIFDetachHTC(HIF_DEVICE *device) +{ + A_MEMZERO(&device->htcCallbacks,sizeof(device->htcCallbacks)); +} + + + + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/hif.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/hif.h --- linux-2.6.26/drivers/net/wireless/ath6k22/hif.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/hif.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,323 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// HIF specific declarations and prototypes +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HIF_H_ +#define _HIF_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Header files */ +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" + + +typedef struct htc_callbacks HTC_CALLBACKS; +typedef struct hif_device HIF_DEVICE; + +/* + * direction - Direction of transfer (HIF_READ/HIF_WRITE). + */ +#define HIF_READ 0x00000001 +#define HIF_WRITE 0x00000002 +#define HIF_DIR_MASK (HIF_READ | HIF_WRITE) + +/* + * type - An interface may support different kind of read/write commands. + * For example: SDIO supports CMD52/CMD53s. In case of MSIO it + * translates to using different kinds of TPCs. The command type + * is thus divided into a basic and an extended command and can + * be specified using HIF_BASIC_IO/HIF_EXTENDED_IO. + */ +#define HIF_BASIC_IO 0x00000004 +#define HIF_EXTENDED_IO 0x00000008 +#define HIF_TYPE_MASK (HIF_BASIC_IO | HIF_EXTENDED_IO) + +/* + * emode - This indicates the whether the command is to be executed in a + * blocking or non-blocking fashion (HIF_SYNCHRONOUS/ + * HIF_ASYNCHRONOUS). The read/write data paths in HTC have been + * implemented using the asynchronous mode allowing the the bus + * driver to indicate the completion of operation through the + * registered callback routine. The requirement primarily comes + * from the contexts these operations get called from (a driver's + * transmit context or the ISR context in case of receive). + * Support for both of these modes is essential. + */ +#define HIF_SYNCHRONOUS 0x00000010 +#define HIF_ASYNCHRONOUS 0x00000020 +#define HIF_EMODE_MASK (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS) + +/* + * dmode - An interface may support different kinds of commands based on + * the tradeoff between the amount of data it can carry and the + * setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/ + * HIF_BLOCK_BASIS). In case of latter, the data is rounded off + * to the nearest block size by padding. The size of the block is + * configurable at compile time using the HIF_BLOCK_SIZE and is + * negotiated with the target during initialization after the + * AR6000 interrupts are enabled. + */ +#define HIF_BYTE_BASIS 0x00000040 +#define HIF_BLOCK_BASIS 0x00000080 +#define HIF_DMODE_MASK (HIF_BYTE_BASIS | HIF_BLOCK_BASIS) + +/* + * amode - This indicates if the address has to be incremented on AR6000 + * after every read/write operation (HIF?FIXED_ADDRESS/ + * HIF_INCREMENTAL_ADDRESS). + */ +#define HIF_FIXED_ADDRESS 0x00000100 +#define HIF_INCREMENTAL_ADDRESS 0x00000200 +#define HIF_AMODE_MASK (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS) + +#define HIF_WR_ASYNC_BYTE_FIX \ + (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_WR_ASYNC_BYTE_INC \ + (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_WR_ASYNC_BLOCK_INC \ + (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_WR_SYNC_BYTE_FIX \ + (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_WR_SYNC_BYTE_INC \ + (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_WR_SYNC_BLOCK_INC \ + (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_SYNC_BYTE_INC \ + (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_SYNC_BYTE_FIX \ + (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_RD_ASYNC_BYTE_FIX \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_RD_ASYNC_BLOCK_FIX \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS) +#define HIF_RD_ASYNC_BYTE_INC \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_ASYNC_BLOCK_INC \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_SYNC_BLOCK_INC \ + (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) + + +typedef enum { + HIF_DEVICE_POWER_STATE = 0, + HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + HIF_DEVICE_GET_MBOX_ADDR, + HIF_DEVICE_GET_PENDING_EVENTS_FUNC, + HIF_DEVICE_GET_IRQ_PROC_MODE, + HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC, + HIF_DEVICE_POWER_STATE_CHANGE, +} HIF_DEVICE_CONFIG_OPCODE; + +/* + * HIF CONFIGURE definitions: + * + * HIF_DEVICE_GET_MBOX_BLOCK_SIZE + * input : none + * output : array of 4 A_UINT32s + * notes: block size is returned for each mailbox (4) + * + * HIF_DEVICE_GET_MBOX_ADDR + * input : none + * output : array of 4 A_UINT32 + * notes: address is returned for each mailbox (4) in the array + * + * HIF_DEVICE_GET_PENDING_EVENTS_FUNC + * input : none + * output: HIF_PENDING_EVENTS_FUNC function pointer + * notes: this is optional for the HIF layer, if the request is + * not handled then it indicates that the upper layer can use + * the standard device methods to get pending events (IRQs, mailbox messages etc..) + * otherwise it can call the function pointer to check pending events. + * + * HIF_DEVICE_GET_IRQ_PROC_MODE + * input : none + * output : HIF_DEVICE_IRQ_PROCESSING_MODE (interrupt processing mode) + * note: the hif layer interfaces with the underlying OS-specific bus driver. The HIF + * layer can report whether IRQ processing is requires synchronous behavior or + * can be processed using asynchronous bus requests (typically faster). + * + * HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC + * input : + * output : HIF_MASK_UNMASK_RECV_EVENT function pointer + * notes: this is optional for the HIF layer. The HIF layer may require a special mechanism + * to mask receive message events. The upper layer can call this pointer when it needs + * to mask/unmask receive events (in case it runs out of buffers). + * + * HIF_DEVICE_POWER_STATE_CHANGE + * + * input : HIF_DEVICE_POWER_CHANGE_TYPE + * output : none + * note: this is optional for the HIF layer. The HIF layer can handle power on/off state change + * requests in an interconnect specific way. This is highly OS and bus driver dependent. + * The caller must guarantee that no HIF read/write requests will be made after the device + * is powered down. + * + * + * + */ + +typedef enum { + HIF_DEVICE_IRQ_SYNC_ONLY, /* for HIF implementations that require the DSR to process all + interrupts before returning */ + HIF_DEVICE_IRQ_ASYNC_SYNC, /* for HIF implementations that allow DSR to process interrupts + using ASYNC I/O (that is HIFAckInterrupt can be called at a + later time */ +} HIF_DEVICE_IRQ_PROCESSING_MODE; + +typedef enum { + HIF_DEVICE_POWER_UP, /* HIF layer should power up interface and/or module */ + HIF_DEVICE_POWER_DOWN, /* HIF layer should initiate bus-specific measures to minimize power */ + HIF_DEVICE_POWER_CUT /* HIF layer should initiate bus-specific AND/OR platform-specific measures + to completely power-off the module and associated hardware (i.e. cut power supplies) + */ +} HIF_DEVICE_POWER_CHANGE_TYPE; + +#define HIF_MAX_DEVICES 1 + +struct htc_callbacks { + void *context; /* context to pass to the dsrhandler + note : rwCompletionHandler is provided the context passed to HIFReadWrite */ + A_STATUS (* rwCompletionHandler)(void *rwContext, A_STATUS status); + A_STATUS (* dsrHandler)(void *context); +}; + +typedef struct osdrv_callbacks { + void *context; /* context to pass for all callbacks except deviceRemovedHandler + the deviceRemovedHandler is only called if the device is claimed */ + A_STATUS (* deviceInsertedHandler)(void *context, void *hif_handle); + A_STATUS (* deviceRemovedHandler)(void *claimedContext, void *hif_handle); + A_STATUS (* deviceSuspendHandler)(void *context); + A_STATUS (* deviceResumeHandler)(void *context); + A_STATUS (* deviceWakeupHandler)(void *context); +} OSDRV_CALLBACKS; + +#define HIF_OTHER_EVENTS (1 << 0) /* other interrupts (non-Recv) are pending, host + needs to read the register table to figure out what */ +#define HIF_RECV_MSG_AVAIL (1 << 1) /* pending recv packet */ + +typedef struct _HIF_PENDING_EVENTS_INFO { + A_UINT32 Events; + A_UINT32 LookAhead; + A_UINT32 AvailableRecvBytes; +} HIF_PENDING_EVENTS_INFO; + + /* function to get pending events , some HIF modules use special mechanisms + * to detect packet available and other interrupts */ +typedef A_STATUS ( *HIF_PENDING_EVENTS_FUNC)(HIF_DEVICE *device, + HIF_PENDING_EVENTS_INFO *pEvents, + void *AsyncContext); + +#define HIF_MASK_RECV TRUE +#define HIF_UNMASK_RECV FALSE + /* function to mask recv events */ +typedef A_STATUS ( *HIF_MASK_UNMASK_RECV_EVENT)(HIF_DEVICE *device, + A_BOOL Mask, + void *AsyncContext); + + +/* + * This API is used to perform any global initialization of the HIF layer + * and to set OS driver callbacks (i.e. insertion/removal) to the HIF layer + * + */ +A_STATUS HIFInit(OSDRV_CALLBACKS *callbacks); + +/* This API claims the HIF device and provides a context for handling removal. + * The device removal callback is only called when the OSDRV layer claims + * a device. The claimed context must be non-NULL */ +void HIFClaimDevice(HIF_DEVICE *device, void *claimedContext); +/* release the claimed device */ +void HIFReleaseDevice(HIF_DEVICE *device); + +/* This API allows the HTC layer to attach to the HIF device */ +A_STATUS HIFAttachHTC(HIF_DEVICE *device, HTC_CALLBACKS *callbacks); +/* This API detaches the HTC layer from the HIF device */ +void HIFDetachHTC(HIF_DEVICE *device); + +/* + * This API is used to provide the read/write interface over the specific bus + * interface. + * address - Starting address in the AR6000's address space. For mailbox + * writes, it refers to the start of the mbox boundary. It should + * be ensured that the last byte falls on the mailbox's EOM. For + * mailbox reads, it refers to the end of the mbox boundary. + * buffer - Pointer to the buffer containg the data to be transmitted or + * received. + * length - Amount of data to be transmitted or received. + * request - Characterizes the attributes of the command. + */ +A_STATUS +HIFReadWrite(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length, + A_UINT32 request, + void *context); + +/* + * This can be initiated from the unload driver context when the OSDRV layer has no more use for + * the device. + */ +void HIFShutDownDevice(HIF_DEVICE *device); + +/* + * This should translate to an acknowledgment to the bus driver indicating that + * the previous interrupt request has been serviced and the all the relevant + * sources have been cleared. HTC is ready to process more interrupts. + * This should prevent the bus driver from raising an interrupt unless the + * previous one has been serviced and acknowledged using the previous API. + */ +void HIFAckInterrupt(HIF_DEVICE *device); + +void HIFMaskInterrupt(HIF_DEVICE *device); + +void HIFUnMaskInterrupt(HIF_DEVICE *device); + +/* + * This set of functions are to be used by the bus driver to notify + * the HIF module about various events. + * These are not implemented if the bus driver provides an alternative + * way for this notification though callbacks for instance. + */ +int HIFInsertEventNotify(void); + +int HIFRemoveEventNotify(void); + +int HIFIRQEventNotify(void); + +int HIFRWCompleteEventNotify(void); + +A_STATUS +HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode, + void *config, A_UINT32 configLen); + +#ifdef __cplusplus +} +#endif + +#endif /* _HIF_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/hif_internal.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/hif_internal.h --- linux-2.6.26/drivers/net/wireless/ath6k22/hif_internal.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/hif_internal.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,89 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// internal header file for hif layer +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "hif.h" + +#define MANUFACTURER_ID_AR6001_BASE 0x100 +#define MANUFACTURER_ID_AR6002_BASE 0x200 +#define MANUFACTURER_ID_AR6003_BASE 0x300 +#define FUNCTION_CLASS 0x0 +#define MANUFACTURER_CODE 0x271 + +#define BUS_REQUEST_MAX_NUM 64 + +#define SDIO_CLOCK_FREQUENCY_DEFAULT 25000000 +#define SDWLAN_ENABLE_DISABLE_TIMEOUT 20 +#define FLAGS_CARD_ENAB 0x02 +#define FLAGS_CARD_IRQ_UNMSK 0x04 + +#define HIF_MBOX_BLOCK_SIZE 128 +#define HIF_MBOX_BASE_ADDR 0x800 +#define HIF_MBOX_WIDTH 0x800 +#define HIF_MBOX0_BLOCK_SIZE 1 +#define HIF_MBOX1_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE +#define HIF_MBOX2_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE +#define HIF_MBOX3_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE + +#define HIF_MBOX_START_ADDR(mbox) \ + HIF_MBOX_BASE_ADDR + mbox * HIF_MBOX_WIDTH + +#define HIF_MBOX_END_ADDR(mbox) \ + HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1 + +typedef struct bus_request { + struct bus_request *next; /* link list of available requests */ + struct bus_request *inusenext; /* link list of in use requests */ + struct compat_semaphore sem_req; + A_UINT32 address; /* request data */ + A_UCHAR *buffer; + A_UINT32 length; + A_UINT32 request; + void *context; + A_STATUS status; +} BUS_REQUEST; + +struct hif_device { + struct sdio_func *func; + spinlock_t asynclock; + struct task_struct* async_task; /* task to handle async commands */ + struct compat_semaphore sem_async; /* wake up for async task */ + int async_shutdown; /* stop the async task */ + struct completion async_completion; /* thread completion */ + BUS_REQUEST *asyncreq; /* request for async tasklet */ + BUS_REQUEST *taskreq; /* async tasklet data */ + spinlock_t lock; + BUS_REQUEST *s_busRequestFreeQueue; /* free list */ + BUS_REQUEST busRequest[BUS_REQUEST_MAX_NUM]; /* available bus requests */ + void *claimedContext; + HTC_CALLBACKS htcCallbacks; + A_UINT8 *dma_buffer; +}; + +#define HIF_DMA_BUFFER_SIZE (32 * 1024) +#define CMD53_FIXED_ADDRESS 1 +#define CMD53_INCR_ADDRESS 2 diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/host_version.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/host_version.h --- linux-2.6.26/drivers/net/wireless/ath6k22/host_version.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/host_version.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains version information for the sample host driver for the +// AR6000 chip +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HOST_VERSION_H_ +#define _HOST_VERSION_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "AR6K_version.h" + +/* + * The version number is made up of major, minor, patch and build + * numbers. These are 16 bit numbers. The build and release script will + * set the build number using a Perforce counter. Here the build number is + * set to 9999 so that builds done without the build-release script are easily + * identifiable. + */ + +#define ATH_SW_VER_MAJOR __VER_MAJOR_ +#define ATH_SW_VER_MINOR __VER_MINOR_ +#define ATH_SW_VER_PATCH __VER_PATCH_ +#define ATH_SW_VER_BUILD __BUILD_NUMBER_ + +#ifdef __cplusplus +} +#endif + +#endif /* _HOST_VERSION_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/htc.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc.c --- linux-2.6.26/drivers/net/wireless/ath6k22/htc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,525 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + + +static void HTCReportFailure(void *Context, AR6K_TARGET_FAILURE_TYPE Type); + + +void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList) +{ + LOCK_HTC(target); + HTC_PACKET_ENQUEUE(pList,pPacket); + UNLOCK_HTC(target); +} + +HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList) +{ + HTC_PACKET *pPacket; + + LOCK_HTC(target); + pPacket = HTC_PACKET_DEQUEUE(pList); + UNLOCK_HTC(target); + + return pPacket; +} + +/* cleanup the HTC instance */ +static void HTCCleanup(HTC_TARGET *target) +{ + A_INT32 i; + + DevCleanup(&target->Device); + + for (i = 0;i < NUM_CONTROL_BUFFERS;i++) { + if (target->HTCControlBuffers[i].Buffer) { + A_FREE(target->HTCControlBuffers[i].Buffer); + } + } + + if (A_IS_MUTEX_VALID(&target->HTCLock)) { + A_MUTEX_DELETE(&target->HTCLock); + } + + if (A_IS_MUTEX_VALID(&target->HTCRxLock)) { + A_MUTEX_DELETE(&target->HTCRxLock); + } + + if (A_IS_MUTEX_VALID(&target->HTCTxLock)) { + A_MUTEX_DELETE(&target->HTCTxLock); + } + /* free our instance */ + A_FREE(target); +} + +/* registered target arrival callback from the HIF layer */ +HTC_HANDLE HTCCreate(void *hif_handle, HTC_INIT_INFO *pInfo) +{ + HTC_TARGET *target = NULL; + A_STATUS status = A_OK; + int i; + A_UINT32 ctrl_bufsz; + A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX]; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Enter\n")); + + do { + + /* allocate target memory */ + if ((target = (HTC_TARGET *)A_MALLOC(sizeof(HTC_TARGET))) == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n")); + status = A_ERROR; + break; + } + + A_MEMZERO(target, sizeof(HTC_TARGET)); + A_MUTEX_INIT(&target->HTCLock); + A_MUTEX_INIT(&target->HTCRxLock); + A_MUTEX_INIT(&target->HTCTxLock); + INIT_HTC_PACKET_QUEUE(&target->ControlBufferTXFreeList); + INIT_HTC_PACKET_QUEUE(&target->ControlBufferRXFreeList); + + /* give device layer the hif device handle */ + target->Device.HIFDevice = hif_handle; + /* give the device layer our context (for event processing) + * the device layer will register it's own context with HIF + * so we need to set this so we can fetch it in the target remove handler */ + target->Device.HTCContext = target; + /* set device layer target failure callback */ + target->Device.TargetFailureCallback = HTCReportFailure; + /* set device layer recv message pending callback */ + target->Device.MessagePendingCallback = HTCRecvMessagePendingHandler; + target->EpWaitingForBuffers = ENDPOINT_MAX; + + A_MEMCPY(&target->HTCInitInfo,pInfo,sizeof(HTC_INIT_INFO)); + + /* setup device layer */ + status = DevSetup(&target->Device); + + if (A_FAILED(status)) { + break; + } + + + /* get the block sizes */ + status = HIFConfigureDevice(hif_handle, HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + blocksizes, sizeof(blocksizes)); + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get block size info from HIF layer...\n")); + break; + } + + /* Set the control buffer size based on the block size */ + if (blocksizes[1] > HTC_MAX_CONTROL_MESSAGE_LENGTH) { + ctrl_bufsz = blocksizes[1] + HTC_HDR_LENGTH; + } else { + ctrl_bufsz = HTC_MAX_CONTROL_MESSAGE_LENGTH + HTC_HDR_LENGTH; + } + for (i = 0;i < NUM_CONTROL_BUFFERS;i++) { + target->HTCControlBuffers[i].Buffer = A_MALLOC(ctrl_bufsz); + if (target->HTCControlBuffers[i].Buffer == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n")); + status = A_ERROR; + break; + } + } + + if (A_FAILED(status)) { + break; + } + + /* carve up buffers/packets for control messages */ + for (i = 0; i < NUM_CONTROL_RX_BUFFERS; i++) { + HTC_PACKET *pControlPacket; + pControlPacket = &target->HTCControlBuffers[i].HtcPacket; + SET_HTC_PACKET_INFO_RX_REFILL(pControlPacket, + target, + target->HTCControlBuffers[i].Buffer, + ctrl_bufsz, + ENDPOINT_0); + HTC_FREE_CONTROL_RX(target,pControlPacket); + } + + for (;i < NUM_CONTROL_BUFFERS;i++) { + HTC_PACKET *pControlPacket; + pControlPacket = &target->HTCControlBuffers[i].HtcPacket; + INIT_HTC_PACKET_INFO(pControlPacket, + target->HTCControlBuffers[i].Buffer, + ctrl_bufsz); + HTC_FREE_CONTROL_TX(target,pControlPacket); + } + + } while (FALSE); + + if (A_FAILED(status)) { + if (target != NULL) { + HTCCleanup(target); + target = NULL; + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Exit\n")); + + return target; +} + +void HTCDestroy(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCDestroy .. Destroying :0x%X \n",(A_UINT32)target)); + HTCCleanup(target); + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCDestroy \n")); +} + +/* get the low level HIF device for the caller , the caller may wish to do low level + * HIF requests */ +void *HTCGetHifDevice(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + return target->Device.HIFDevice; +} + +/* wait for the target to arrive (sends HTC Ready message) + * this operation is fully synchronous and the message is polled for */ +A_STATUS HTCWaitTarget(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_STATUS status; + HTC_PACKET *pPacket = NULL; + HTC_READY_MSG *pRdyMsg; + HTC_SERVICE_CONNECT_REQ connect; + HTC_SERVICE_CONNECT_RESP resp; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Enter (target:0x%X) \n", (A_UINT32)target)); + + do { + +#ifdef MBOXHW_UNIT_TEST + + status = DoMboxHWTest(&target->Device); + + if (status != A_OK) { + break; + } + +#endif + + /* we should be getting 1 control message that the target is ready */ + status = HTCWaitforControlMessage(target, &pPacket); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Target Not Available!!\n")); + break; + } + + /* we controlled the buffer creation so it has to be properly aligned */ + pRdyMsg = (HTC_READY_MSG *)pPacket->pBuffer; + + if ((pRdyMsg->MessageID != HTC_MSG_READY_ID) || + (pPacket->ActualLength < sizeof(HTC_READY_MSG))) { + /* this message is not valid */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + if (pRdyMsg->CreditCount == 0 || pRdyMsg->CreditSize == 0) { + /* this message is not valid */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + target->TargetCredits = pRdyMsg->CreditCount; + target->TargetCreditSize = pRdyMsg->CreditSize; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" Target Ready: credits: %d credit size: %d\n", + target->TargetCredits, target->TargetCreditSize)); + + /* setup our pseudo HTC control endpoint connection */ + A_MEMZERO(&connect,sizeof(connect)); + A_MEMZERO(&resp,sizeof(resp)); + connect.EpCallbacks.pContext = target; + connect.EpCallbacks.EpTxComplete = HTCControlTxComplete; + connect.EpCallbacks.EpRecv = HTCControlRecv; + connect.EpCallbacks.EpRecvRefill = NULL; /* not needed */ + connect.EpCallbacks.EpSendFull = NULL; /* not nedded */ + connect.MaxSendQueueDepth = NUM_CONTROL_BUFFERS; + connect.ServiceID = HTC_CTRL_RSVD_SVC; + + /* connect fake service */ + status = HTCConnectService((HTC_HANDLE)target, + &connect, + &resp); + + if (!A_FAILED(status)) { + break; + } + + } while (FALSE); + + if (pPacket != NULL) { + HTC_FREE_CONTROL_RX(target,pPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Exit\n")); + + return status; +} + + + +/* Start HTC, enable interrupts and let the target know host has finished setup */ +A_STATUS HTCStart(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_PACKET *pPacket; + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Enter\n")); + + /* make sure interrupts are disabled at the chip level, + * this function can be called again from a reboot of the target without shutting down HTC */ + DevDisableInterrupts(&target->Device); + /* make sure state is cleared again */ + target->HTCStateFlags = 0; + + /* now that we are starting, push control receive buffers into the + * HTC control endpoint */ + + while (1) { + pPacket = HTC_ALLOC_CONTROL_RX(target); + if (NULL == pPacket) { + break; + } + HTCAddReceivePkt((HTC_HANDLE)target,pPacket); + } + + do { + + AR_DEBUG_ASSERT(target->InitCredits != NULL); + AR_DEBUG_ASSERT(target->EpCreditDistributionListHead != NULL); + AR_DEBUG_ASSERT(target->EpCreditDistributionListHead->pNext != NULL); + + /* call init credits callback to do the distribution , + * NOTE: the first entry in the distribution list is ENDPOINT_0, so + * we pass the start of the list after this one. */ + target->InitCredits(target->pCredDistContext, + target->EpCreditDistributionListHead->pNext, + target->TargetCredits); + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_TRC)) { + DumpCreditDistStates(target); + } + + /* the caller is done connecting to services, so we can indicate to the + * target that the setup phase is complete */ + status = HTCSendSetupComplete(target); + + if (A_FAILED(status)) { + break; + } + + /* unmask interrupts */ + status = DevUnmaskInterrupts(&target->Device); + + if (A_FAILED(status)) { + HTCStop(target); + } + + } while (FALSE); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Exit\n")); + return status; +} + +static void ResetEndpointStates(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + int i; + + for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) { + pEndpoint = &target->EndPoint[i]; + + A_MEMZERO(&pEndpoint->CreditDist, sizeof(pEndpoint->CreditDist)); + pEndpoint->ServiceID = 0; + pEndpoint->CurrentTxQueueDepth = 0; + pEndpoint->MaxMsgLength = 0; + pEndpoint->MaxTxQueueDepth = 0; +#ifdef HTC_EP_STAT_PROFILING + A_MEMZERO(&pEndpoint->EndPointStats,sizeof(pEndpoint->EndPointStats)); +#endif + INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBuffers); + INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue); + } + /* reset distribution list */ + target->EpCreditDistributionListHead = NULL; +} + +/* stop HTC communications, i.e. stop interrupt reception, and flush all queued buffers */ +void HTCStop(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCStop \n")); + + LOCK_HTC_RX(target); + /* mark that we are shutting down .. */ + target->HTCStateFlags |= HTC_STATE_STOPPING; + UNLOCK_HTC_RX(target); + + /* Masking interrupts is a synchronous operation, when this function returns + * all pending HIF I/O has completed, we can safely flush the queues */ + DevMaskInterrupts(&target->Device); + + /* flush all send packets */ + HTCFlushSendPkts(target); + /* flush all recv buffers */ + HTCFlushRecvBuffers(target); + + ResetEndpointStates(target); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCStop \n")); +} + +void HTCDumpCreditStates(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + + LOCK_HTC_TX(target); + + DumpCreditDistStates(target); + + UNLOCK_HTC_TX(target); +} + +/* report a target failure from the device, this is a callback from the device layer + * which uses a mechanism to report errors from the target (i.e. special interrupts) */ +static void HTCReportFailure(void *Context, AR6K_TARGET_FAILURE_TYPE Type) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + + target->TargetFailure = TRUE; + + switch (Type) { + + case AR6K_TARGET_TX_ERROR: + /* could be a credit problem */ + DumpCreditDistStates(target); + break; + case AR6K_TARGET_RX_ERROR: + + break; + case AR6K_TARGET_ASSERT: + if (target->HTCInitInfo.TargetFailure != NULL) { + /* let upper layer know, it needs to call HTCStop() */ + target->HTCInitInfo.TargetFailure(target->HTCInitInfo.pContext, A_ERROR); + } + break; + default: + break; + + } + +} + +void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription) +{ + A_CHAR stream[60]; + A_UINT32 i; + A_UINT16 offset, count; + + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("<---------Dumping %d Bytes : %s ------>\n", length, pDescription)); + + count = 0; + offset = 0; + for(i = 0; i < length; i++) { + A_SPRINTF(stream + offset, "%2.2X ", buffer[i]); + count ++; + offset += 3; + + if(count == 16) { + count = 0; + offset = 0; + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("[H]: %s\n", stream)); + A_MEMZERO(stream, 60); + } + } + + if(offset != 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("[H]: %s\n", stream)); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("<------------------------------------------------->\n")); +} + +A_BOOL HTCGetEndpointStatistics(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + HTC_ENDPOINT_STAT_ACTION Action, + HTC_ENDPOINT_STATS *pStats) +{ + +#ifdef HTC_EP_STAT_PROFILING + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_BOOL clearStats = FALSE; + A_BOOL sample = FALSE; + + switch (Action) { + case HTC_EP_STAT_SAMPLE : + sample = TRUE; + break; + case HTC_EP_STAT_SAMPLE_AND_CLEAR : + sample = TRUE; + clearStats = TRUE; + break; + case HTC_EP_STAT_CLEAR : + clearStats = TRUE; + break; + default: + break; + } + + A_ASSERT(Endpoint < ENDPOINT_MAX); + + /* lock out TX and RX while we sample and/or clear */ + LOCK_HTC_TX(target); + LOCK_HTC_RX(target); + + if (sample) { + A_ASSERT(pStats != NULL); + /* return the stats to the caller */ + A_MEMCPY(pStats, &target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS)); + } + + if (clearStats) { + /* reset stats */ + A_MEMZERO(&target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS)); + } + + UNLOCK_HTC_RX(target); + UNLOCK_HTC_TX(target); + + return TRUE; +#else + return FALSE; +#endif +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/htc.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc.h --- linux-2.6.26/drivers/net/wireless/ath6k22/htc.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,204 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __HTC_H__ +#define __HTC_H__ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field)) + +#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \ + (((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)])) + +/* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a + * structure using only the type and field name. + * Use these macros if there is the potential for unaligned buffer accesses. */ +#define A_GET_UINT16_FIELD(p,type,field) \ + ASSEMBLE_UNALIGNED_UINT16(p,\ + A_OFFSETOF(type,field) + 1, \ + A_OFFSETOF(type,field)) + +#define A_SET_UINT16_FIELD(p,type,field,value) \ +{ \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (A_UINT8)(value); \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field) + 1] = (A_UINT8)((value) >> 8); \ +} + +#define A_GET_UINT8_FIELD(p,type,field) \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] + +#define A_SET_UINT8_FIELD(p,type,field,value) \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (value) + +/****** DANGER DANGER *************** + * + * The frame header length and message formats defined herein were + * selected to accommodate optimal alignment for target processing. This reduces code + * size and improves performance. + * + * Any changes to the header length may alter the alignment and cause exceptions + * on the target. When adding to the message structures insure that fields are + * properly aligned. + * + */ + +/* HTC frame header */ +typedef PREPACK struct _HTC_FRAME_HDR{ + /* do not remove or re-arrange these fields, these are minimally required + * to take advantage of 4-byte lookaheads in some hardware implementations */ + A_UINT8 EndpointID; + A_UINT8 Flags; + A_UINT16 PayloadLen; /* length of data (including trailer) that follows the header */ + + /***** end of 4-byte lookahead ****/ + + A_UINT8 ControlBytes[2]; + + /* message payload starts after the header */ + +} POSTPACK HTC_FRAME_HDR; + +/* frame header flags */ +#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0) +#define HTC_FLAGS_RECV_TRAILER (1 << 1) + + +#define HTC_HDR_LENGTH (sizeof(HTC_FRAME_HDR)) +#define HTC_MAX_TRAILER_LENGTH 255 +#define HTC_MAX_PAYLOAD_LENGTH (2048 - sizeof(HTC_FRAME_HDR)) + +/* HTC control message IDs */ +typedef enum { + HTC_MSG_READY_ID = 1, + HTC_MSG_CONNECT_SERVICE_ID = 2, + HTC_MSG_CONNECT_SERVICE_RESPONSE_ID = 3, + HTC_MSG_SETUP_COMPLETE_ID = 4, +} HTC_MSG_IDS; + +#define HTC_MAX_CONTROL_MESSAGE_LENGTH 256 + +/* base message ID header */ +typedef PREPACK struct { + A_UINT16 MessageID; +} POSTPACK HTC_UNKNOWN_MSG; + +/* HTC ready message + * direction : target-to-host */ +typedef PREPACK struct { + A_UINT16 MessageID; /* ID */ + A_UINT16 CreditCount; /* number of credits the target can offer */ + A_UINT16 CreditSize; /* size of each credit */ + A_UINT8 MaxEndpoints; /* maximum number of endpoints the target has resources for */ + A_UINT8 _Pad1; +} POSTPACK HTC_READY_MSG; + +#define HTC_SERVICE_META_DATA_MAX_LENGTH 128 + +/* connect service + * direction : host-to-target */ +typedef PREPACK struct { + A_UINT16 MessageID; + A_UINT16 ServiceID; /* service ID of the service to connect to */ + A_UINT16 ConnectionFlags; /* connection flags */ + +#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) /* reduce credit dribbling when + the host needs credits */ +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3) +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3 + + A_UINT8 ServiceMetaLength; /* length of meta data that follows */ + A_UINT8 _Pad1; + + /* service-specific meta data starts after the header */ + +} POSTPACK HTC_CONNECT_SERVICE_MSG; + +/* connect response + * direction : target-to-host */ +typedef PREPACK struct { + A_UINT16 MessageID; + A_UINT16 ServiceID; /* service ID that the connection request was made */ + A_UINT8 Status; /* service connection status */ + A_UINT8 EndpointID; /* assigned endpoint ID */ + A_UINT16 MaxMsgSize; /* maximum expected message size on this endpoint */ + A_UINT8 ServiceMetaLength; /* length of meta data that follows */ + A_UINT8 _Pad1; + + /* service-specific meta data starts after the header */ + +} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG; + +typedef PREPACK struct { + A_UINT16 MessageID; + /* currently, no other fields */ +} POSTPACK HTC_SETUP_COMPLETE_MSG; + + +/* connect response status codes */ +#define HTC_SERVICE_SUCCESS 0 /* success */ +#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */ +#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */ +#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */ +#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more + endpoints */ + +/* report record IDs */ +typedef enum { + HTC_RECORD_NULL = 0, + HTC_RECORD_CREDITS = 1, + HTC_RECORD_LOOKAHEAD = 2, +} HTC_RPT_IDS; + +typedef PREPACK struct { + A_UINT8 RecordID; /* Record ID */ + A_UINT8 Length; /* Length of record */ +} POSTPACK HTC_RECORD_HDR; + +typedef PREPACK struct { + A_UINT8 EndpointID; /* Endpoint that owns these credits */ + A_UINT8 Credits; /* credits to report since last report */ +} POSTPACK HTC_CREDIT_REPORT; + +typedef PREPACK struct { + A_UINT8 PreValid; /* pre valid guard */ + A_UINT8 LookAhead[4]; /* 4 byte lookahead */ + A_UINT8 PostValid; /* post valid guard */ + + /* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes. + * The PreValid bytes must equal the inverse of the PostValid byte */ + +} POSTPACK HTC_LOOKAHEAD_REPORT; + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + + +#endif /* __HTC_H__ */ + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/htc_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc_api.h --- linux-2.6.26/drivers/net/wireless/ath6k22/htc_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc_api.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,463 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HTC_API_H_ +#define _HTC_API_H_ + +#include "htc.h" +#include "htc_services.h" +#include "htc_packet.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* TODO.. for BMI */ +#define ENDPOINT1 0 +// TODO -remove me, but we have to fix BMI first +#define HTC_MAILBOX_NUM_MAX 4 + +/* this is the amount of header room required by users of HTC */ +#define HTC_HEADER_LEN HTC_HDR_LENGTH + +typedef void *HTC_HANDLE; + +typedef A_UINT16 HTC_SERVICE_ID; + +typedef struct _HTC_INIT_INFO { + void *pContext; /* context for target failure notification */ + void (*TargetFailure)(void *Instance, A_STATUS Status); +} HTC_INIT_INFO; + +/* per service connection send completion */ +typedef void (*HTC_EP_SEND_PKT_COMPLETE)(void *,HTC_PACKET *); +/* per service connection pkt received */ +typedef void (*HTC_EP_RECV_PKT)(void *,HTC_PACKET *); + +/* Optional per service connection receive buffer re-fill callback, + * On some OSes (like Linux) packets are allocated from a global pool and indicated up + * to the network stack. The driver never gets the packets back from the OS. For these OSes + * a refill callback can be used to allocate and re-queue buffers into HTC. + * + * On other OSes, the network stack can call into the driver's OS-specifc "return_packet" handler and + * the driver can re-queue these buffers into HTC. In this regard a refill callback is + * unnecessary */ +typedef void (*HTC_EP_RECV_REFILL)(void *, HTC_ENDPOINT_ID Endpoint); + +/* Optional per service connection receive buffer allocation callback. + * On some systems packet buffers are an extremely limited resource. Rather than + * queue largest-possible-sized buffers to HTC, some systems would rather + * allocate a specific size as the packet is received. The trade off is + * slightly more processing (callback invoked for each RX packet) + * for the benefit of committing fewer buffer resources into HTC. + * + * The callback is provided the length of the pending packet to fetch. This includes the + * HTC header length plus the length of payload. The callback can return a pointer to + * the allocated HTC packet for immediate use. + * + * NOTE*** This callback is mutually exclusive with the the refill callback above. + * + * */ +typedef HTC_PACKET *(*HTC_EP_RECV_ALLOC)(void *, HTC_ENDPOINT_ID Endpoint, int Length); + +typedef enum _HTC_SEND_FULL_ACTION { + HTC_SEND_FULL_KEEP = 0, /* packet that overflowed should be kept in the queue */ + HTC_SEND_FULL_DROP = 1, /* packet that overflowed should be dropped */ +} HTC_SEND_FULL_ACTION; + +/* Optional per service connection callback when a send queue is full. This can occur if the + * host continues queueing up TX packets faster than credits can arrive + * To prevent the host (on some Oses like Linux) from continuously queueing packets + * and consuming resources, this callback is provided so that that the host + * can disable TX in the subsystem (i.e. network stack). + * This callback is invoked for each packet that "overflows" the HTC queue. The callback can + * determine whether the new packet that overflowed the queue can be kept (HTC_SEND_FULL_KEEP) or + * dropped (HTC_SEND_FULL_DROP). If a packet is dropped, the EpTxComplete handler will be called + * and the packet's status field will be set to A_NO_RESOURCE. + * Other OSes require a "per-packet" indication for each completed TX packet, this + * closed loop mechanism will prevent the network stack from overunning the NIC + * The packet to keep or drop is passed for inspection to the registered handler the handler + * must ONLY inspect the packet, it may not free or reclaim the packet. */ +typedef HTC_SEND_FULL_ACTION (*HTC_EP_SEND_QUEUE_FULL)(void *, HTC_PACKET *pPacket); + +typedef struct _HTC_EP_CALLBACKS { + void *pContext; /* context for each callback */ + HTC_EP_SEND_PKT_COMPLETE EpTxComplete; /* tx completion callback for connected endpoint */ + HTC_EP_RECV_PKT EpRecv; /* receive callback for connected endpoint */ + HTC_EP_RECV_REFILL EpRecvRefill; /* OPTIONAL receive re-fill callback for connected endpoint */ + HTC_EP_SEND_QUEUE_FULL EpSendFull; /* OPTIONAL send full callback */ + HTC_EP_RECV_ALLOC EpRecvAlloc; /* OPTIONAL recv allocation callback */ +} HTC_EP_CALLBACKS; + +/* service connection information */ +typedef struct _HTC_SERVICE_CONNECT_REQ { + HTC_SERVICE_ID ServiceID; /* service ID to connect to */ + A_UINT16 ConnectionFlags; /* connection flags, see htc protocol definition */ + A_UINT8 *pMetaData; /* ptr to optional service-specific meta-data */ + A_UINT8 MetaDataLength; /* optional meta data length */ + HTC_EP_CALLBACKS EpCallbacks; /* endpoint callbacks */ + int MaxSendQueueDepth; /* maximum depth of any send queue */ +} HTC_SERVICE_CONNECT_REQ; + +/* service connection response information */ +typedef struct _HTC_SERVICE_CONNECT_RESP { + A_UINT8 *pMetaData; /* caller supplied buffer to optional meta-data */ + A_UINT8 BufferLength; /* length of caller supplied buffer */ + A_UINT8 ActualLength; /* actual length of meta data */ + HTC_ENDPOINT_ID Endpoint; /* endpoint to communicate over */ + int MaxMsgLength; /* max length of all messages over this endpoint */ + A_UINT8 ConnectRespCode; /* connect response code from target */ +} HTC_SERVICE_CONNECT_RESP; + +/* endpoint distribution structure */ +typedef struct _HTC_ENDPOINT_CREDIT_DIST { + struct _HTC_ENDPOINT_CREDIT_DIST *pNext; + struct _HTC_ENDPOINT_CREDIT_DIST *pPrev; + HTC_SERVICE_ID ServiceID; /* Service ID (set by HTC) */ + HTC_ENDPOINT_ID Endpoint; /* endpoint for this distribution struct (set by HTC) */ + A_UINT32 DistFlags; /* distribution flags, distribution function can + set default activity using SET_EP_ACTIVE() macro */ + int TxCreditsNorm; /* credits for normal operation, anything above this + indicates the endpoint is over-subscribed, this field + is only relevant to the credit distribution function */ + int TxCreditsMin; /* floor for credit distribution, this field is + only relevant to the credit distribution function */ + int TxCreditsAssigned; /* number of credits assigned to this EP, this field + is only relevant to the credit dist function */ + int TxCredits; /* current credits available, this field is used by + HTC to determine whether a message can be sent or + must be queued */ + int TxCreditsToDist; /* pending credits to distribute on this endpoint, this + is set by HTC when credit reports arrive. + The credit distribution functions sets this to zero + when it distributes the credits */ + int TxCreditsSeek; /* this is the number of credits that the current pending TX + packet needs to transmit. This is set by HTC when + and endpoint needs credits in order to transmit */ + int TxCreditSize; /* size in bytes of each credit (set by HTC) */ + int TxCreditsPerMaxMsg; /* credits required for a maximum sized messages (set by HTC) */ + void *pHTCReserved; /* reserved for HTC use */ + int TxQueueDepth; /* current depth of TX queue , i.e. messages waiting for credits + This field is valid only when HTC_CREDIT_DIST_ACTIVITY_CHANGE + or HTC_CREDIT_DIST_SEND_COMPLETE is indicated on an endpoint + that has non-zero credits to recover + */ +} HTC_ENDPOINT_CREDIT_DIST; + +#define HTC_EP_ACTIVE ((A_UINT32) (((A_UINT32) 1) << 31)) + +/* macro to check if an endpoint has gone active, useful for credit + * distributions */ +#define IS_EP_ACTIVE(epDist) ((epDist)->DistFlags & HTC_EP_ACTIVE) +#define SET_EP_ACTIVE(epDist) (epDist)->DistFlags |= HTC_EP_ACTIVE + + /* credit distibution code that is passed into the distrbution function, + * there are mandatory and optional codes that must be handled */ +typedef enum _HTC_CREDIT_DIST_REASON { + HTC_CREDIT_DIST_SEND_COMPLETE = 0, /* credits available as a result of completed + send operations (MANDATORY) resulting in credit reports */ + HTC_CREDIT_DIST_ACTIVITY_CHANGE = 1, /* a change in endpoint activity occured (OPTIONAL) */ + HTC_CREDIT_DIST_SEEK_CREDITS, /* an endpoint needs to "seek" credits (OPTIONAL) */ + HTC_DUMP_CREDIT_STATE /* for debugging, dump any state information that is kept by + the distribution function */ +} HTC_CREDIT_DIST_REASON; + +typedef void (*HTC_CREDIT_DIST_CALLBACK)(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + HTC_CREDIT_DIST_REASON Reason); + +typedef void (*HTC_CREDIT_INIT_CALLBACK)(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + int TotalCredits); + + /* endpoint statistics action */ +typedef enum _HTC_ENDPOINT_STAT_ACTION { + HTC_EP_STAT_SAMPLE = 0, /* only read statistics */ + HTC_EP_STAT_SAMPLE_AND_CLEAR = 1, /* sample and immediately clear statistics */ + HTC_EP_STAT_CLEAR /* clear only */ +} HTC_ENDPOINT_STAT_ACTION; + + /* endpoint statistics */ +typedef struct _HTC_ENDPOINT_STATS { + A_UINT32 TxCreditLowIndications; /* number of times the host set the credit-low flag in a send message on + this endpoint */ + A_UINT32 TxIssued; /* running count of TX packets issued */ + A_UINT32 TxDropped; /* tx packets that were dropped */ + A_UINT32 TxCreditRpts; /* running count of total credit reports received for this endpoint */ + A_UINT32 TxCreditRptsFromRx; /* credit reports received from this endpoint's RX packets */ + A_UINT32 TxCreditRptsFromOther; /* credit reports received from RX packets of other endpoints */ + A_UINT32 TxCreditRptsFromEp0; /* credit reports received from endpoint 0 RX packets */ + A_UINT32 TxCreditsFromRx; /* count of credits received via Rx packets on this endpoint */ + A_UINT32 TxCreditsFromOther; /* count of credits received via another endpoint */ + A_UINT32 TxCreditsFromEp0; /* count of credits received via another endpoint */ + A_UINT32 TxCreditsConsummed; /* count of consummed credits */ + A_UINT32 TxCreditsReturned; /* count of credits returned */ + A_UINT32 RxReceived; /* count of RX packets received */ + A_UINT32 RxLookAheads; /* count of lookahead records + found in messages received on this endpoint */ +} HTC_ENDPOINT_STATS; + +/* ------ Function Prototypes ------ */ +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Create an instance of HTC over the underlying HIF device + @function name: HTCCreate + @input: HifDevice - hif device handle, + pInfo - initialization information + @output: + @return: HTC_HANDLE on success, NULL on failure + @notes: + @example: + @see also: HTCDestroy ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +HTC_HANDLE HTCCreate(void *HifDevice, HTC_INIT_INFO *pInfo); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Get the underlying HIF device handle + @function name: HTCGetHifDevice + @input: HTCHandle - handle passed into the AddInstance callback + @output: + @return: opaque HIF device handle usable in HIF API calls. + @notes: + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void *HTCGetHifDevice(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Set credit distribution parameters + @function name: HTCSetCreditDistribution + @input: HTCHandle - HTC handle + pCreditDistCont - caller supplied context to pass into distribution functions + CreditDistFunc - Distribution function callback + CreditDistInit - Credit Distribution initialization callback + ServicePriorityOrder - Array containing list of service IDs, lowest index is highest + priority + ListLength - number of elements in ServicePriorityOrder + @output: + @return: + @notes: The user can set a custom credit distribution function to handle special requirements + for each endpoint. A default credit distribution routine can be used by setting + CreditInitFunc to NULL. The default credit distribution is only provided for simple + "fair" credit distribution without regard to any prioritization. + + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCSetCreditDistribution(HTC_HANDLE HTCHandle, + void *pCreditDistContext, + HTC_CREDIT_DIST_CALLBACK CreditDistFunc, + HTC_CREDIT_INIT_CALLBACK CreditInitFunc, + HTC_SERVICE_ID ServicePriorityOrder[], + int ListLength); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Wait for the target to indicate the HTC layer is ready + @function name: HTCWaitTarget + @input: HTCHandle - HTC handle + @output: + @return: + @notes: This API blocks until the target responds with an HTC ready message. + The caller should not connect services until the target has indicated it is + ready. + @example: + @see also: HTCConnectService ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCWaitTarget(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Start target service communications + @function name: HTCStart + @input: HTCHandle - HTC handle + @output: + @return: + @notes: This API indicates to the target that the service connection phase is complete + and the target can freely start all connected services. This API should only be + called AFTER all service connections have been made. TCStart will issue a + SETUP_COMPLETE message to the target to indicate that all service connections + have been made and the target can start communicating over the endpoints. + @example: + @see also: HTCConnectService ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCStart(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Add receive packet to HTC + @function name: HTCAddReceivePkt + @input: HTCHandle - HTC handle + pPacket - HTC receive packet to add + @output: + @return: A_OK on success + @notes: user must supply HTC packets for capturing incomming HTC frames. The caller + must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL() + macro. + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Connect to an HTC service + @function name: HTCConnectService + @input: HTCHandle - HTC handle + pReq - connection details + @output: pResp - connection response + @return: + @notes: Service connections must be performed before HTCStart. User provides callback handlers + for various endpoint events. + @example: + @see also: HTCStart ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCConnectService(HTC_HANDLE HTCHandle, + HTC_SERVICE_CONNECT_REQ *pReq, + HTC_SERVICE_CONNECT_RESP *pResp); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Send an HTC packet + @function name: HTCSendPkt + @input: HTCHandle - HTC handle + pPacket - packet to send + @output: + @return: A_OK + @notes: Caller must initialize packet using SET_HTC_PACKET_INFO_TX() macro. + This interface is fully asynchronous. On error, HTC SendPkt will + call the registered Endpoint callback to cleanup the packet. + @example: + @see also: HTCFlushEndpoint ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Stop HTC service communications + @function name: HTCStop + @input: HTCHandle - HTC handle + @output: + @return: + @notes: HTC communications is halted. All receive and pending TX packets will + be flushed. + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCStop(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Destory HTC service + @function name: HTCDestroy + @input: HTCHandle + @output: + @return: + @notes: This cleans up all resources allocated by HTCCreate(). + @example: + @see also: HTCCreate ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCDestroy(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Flush pending TX packets + @function name: HTCFlushEndpoint + @input: HTCHandle - HTC handle + Endpoint - Endpoint to flush + Tag - flush tag + @output: + @return: + @notes: The Tag parameter is used to selectively flush packets with matching tags. + The value of 0 forces all packets to be flush regardless of tag. + @example: + @see also: HTCSendPkt ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Dump credit distribution state + @function name: HTCDumpCreditStates + @input: HTCHandle - HTC handle + @output: + @return: + @notes: This dumps all credit distribution information to the debugger + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCDumpCreditStates(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Indicate a traffic activity change on an endpoint + @function name: HTCIndicateActivityChange + @input: HTCHandle - HTC handle + Endpoint - endpoint in which activity has changed + Active - TRUE if active, FALSE if it has become inactive + @output: + @return: + @notes: This triggers the registered credit distribution function to + re-adjust credits for active/inactive endpoints. + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCIndicateActivityChange(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + A_BOOL Active); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Get endpoint statistics + @function name: HTCGetEndpointStatistics + @input: HTCHandle - HTC handle + Endpoint - Endpoint identifier + Action - action to take with statistics + @output: + pStats - statistics that were sampled (can be NULL if Action is HTC_EP_STAT_CLEAR) + + @return: TRUE if statistics profiling is enabled, otherwise FALSE. + + @notes: Statistics is a compile-time option and this function may return FALSE + if HTC is not compiled with profiling. + + The caller can specify the statistic "action" to take when sampling + the statistics. This includes: + + HTC_EP_STAT_SAMPLE: The pStats structure is filled with the current values. + HTC_EP_STAT_SAMPLE_AND_CLEAR: The structure is filled and the current statistics + are cleared. + HTC_EP_STAT_CLEA : the statistics are cleared, the called can pass a NULL value for + pStats + + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_BOOL HTCGetEndpointStatistics(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + HTC_ENDPOINT_STAT_ACTION Action, + HTC_ENDPOINT_STATS *pStats); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Unblock HTC message reception + @function name: HTCUnblockRecv + @input: HTCHandle - HTC handle + @output: + @return: + @notes: + HTC will block the receiver if the EpRecvAlloc callback fails to provide a packet. + The caller can use this API to indicate to HTC when resources (buffers) are available + such that the receiver can be unblocked and HTC may re-attempt fetching the pending message. + + This API is not required if the user uses the EpRecvRefill callback or uses the HTCAddReceivePacket() + API to recycle or provide receive packets to HTC. + + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCUnblockRecv(HTC_HANDLE HTCHandle); + +/* internally used functions for testing... */ +void HTCEnableRecv(HTC_HANDLE HTCHandle); +void HTCDisableRecv(HTC_HANDLE HTCHandle); + +#ifdef __cplusplus +} +#endif + +#endif /* _HTC_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/htc_debug.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc_debug.h --- linux-2.6.26/drivers/net/wireless/ath6k22/htc_debug.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc_debug.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,69 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef HTC_DEBUG_H_ +#define HTC_DEBUG_H_ + +/* ------- Debug related stuff ------- */ +enum { + ATH_DEBUG_SEND = 0x0001, + ATH_DEBUG_RECV = 0x0002, + ATH_DEBUG_SYNC = 0x0004, + ATH_DEBUG_DUMP = 0x0008, + ATH_DEBUG_IRQ = 0x0010, + ATH_DEBUG_TRC = 0x0020, + ATH_DEBUG_WARN = 0x0040, + ATH_DEBUG_ERR = 0x0080, + ATH_DEBUG_ANY = 0xFFFF, +}; + +#ifdef DEBUG + +// TODO FIX usage of A_PRINTF! +#define AR_DEBUG_LVL_CHECK(lvl) (debughtc & (lvl)) +#define AR_DEBUG_PRINTBUF(buffer, length, desc) do { \ + if (debughtc & ATH_DEBUG_DUMP) { \ + DebugDumpBytes(buffer, length,desc); \ + } \ +} while(0) +#define PRINTX_ARG(arg...) arg +#define AR_DEBUG_PRINTF(flags, args) do { \ + if (debughtc & (flags)) { \ + A_PRINTF(KERN_ALERT PRINTX_ARG args); \ + } \ +} while (0) +//#define AR_DEBUG_ASSERT(test) do { \ + //if (!(test)) { \ + //AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test)); \ + //} \ +//} while(0) +extern int debughtc; +#else +#define AR_DEBUG_PRINTF(flags, args) +#define AR_DEBUG_PRINTBUF(buffer, length, desc) +#define AR_DEBUG_ASSERT(test) +#define AR_DEBUG_LVL_CHECK(lvl) 0 +#endif + +void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription); + +#endif /*HTC_DEBUG_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/htc_internal.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc_internal.h --- linux-2.6.26/drivers/net/wireless/ath6k22/htc_internal.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc_internal.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,177 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HTC_INTERNAL_H_ +#define _HTC_INTERNAL_H_ + +/* for debugging, uncomment this to capture the last frame header, on frame header + * processing errors, the last frame header is dump for comparison */ +//#define HTC_CAPTURE_LAST_FRAME + +//#define HTC_EP_STAT_PROFILING + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Header files */ +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "a_debug.h" +#include "htc.h" +#include "htc_api.h" +#include "bmi_msg.h" +#include "hif.h" +#include "ar6k.h" + +/* HTC operational parameters */ +#define HTC_TARGET_RESPONSE_TIMEOUT 2000 /* in ms */ +#define HTC_TARGET_DEBUG_INTR_MASK 0x01 +#define HTC_TARGET_CREDIT_INTR_MASK 0xF0 + +typedef struct _HTC_ENDPOINT { + HTC_SERVICE_ID ServiceID; /* service ID this endpoint is bound to + non-zero value means this endpoint is in use */ + HTC_PACKET_QUEUE TxQueue; /* HTC frame buffer TX queue */ + HTC_PACKET_QUEUE RxBuffers; /* HTC frame buffer RX list */ + HTC_ENDPOINT_CREDIT_DIST CreditDist; /* credit distribution structure (exposed to driver layer) */ + HTC_EP_CALLBACKS EpCallBacks; /* callbacks associated with this endpoint */ + int MaxTxQueueDepth; /* max depth of the TX queue before we need to + call driver's full handler */ + int CurrentTxQueueDepth; /* current TX queue depth */ + int MaxMsgLength; /* max length of endpoint message */ +#ifdef HTC_EP_STAT_PROFILING + HTC_ENDPOINT_STATS EndPointStats; /* endpoint statistics */ +#endif + int TxProcessCount; +} HTC_ENDPOINT; + +#ifdef HTC_EP_STAT_PROFILING +#define INC_HTC_EP_STAT(p,stat,count) (p)->EndPointStats.stat += (count); +#else +#define INC_HTC_EP_STAT(p,stat,count) +#endif + +#define HTC_SERVICE_TX_PACKET_TAG HTC_TX_PACKET_TAG_INTERNAL + +#define NUM_CONTROL_BUFFERS 8 +#define NUM_CONTROL_TX_BUFFERS 2 +#define NUM_CONTROL_RX_BUFFERS (NUM_CONTROL_BUFFERS - NUM_CONTROL_TX_BUFFERS) + +typedef struct HTC_CONTROL_BUFFER { + HTC_PACKET HtcPacket; + A_UINT8 *Buffer; +} HTC_CONTROL_BUFFER; + +/* our HTC target state */ +typedef struct _HTC_TARGET { + HTC_ENDPOINT EndPoint[ENDPOINT_MAX]; + HTC_CONTROL_BUFFER HTCControlBuffers[NUM_CONTROL_BUFFERS]; + HTC_ENDPOINT_CREDIT_DIST *EpCreditDistributionListHead; + HTC_PACKET_QUEUE ControlBufferTXFreeList; + HTC_PACKET_QUEUE ControlBufferRXFreeList; + HTC_CREDIT_DIST_CALLBACK DistributeCredits; + HTC_CREDIT_INIT_CALLBACK InitCredits; + void *pCredDistContext; + int TargetCredits; + int TargetCreditSize; + A_MUTEX_T HTCLock; + A_MUTEX_T HTCRxLock; + A_MUTEX_T HTCTxLock; + AR6K_DEVICE Device; /* AR6K - specific state */ + A_UINT32 HTCStateFlags; + HTC_ENDPOINT_ID EpWaitingForBuffers; + A_BOOL TargetFailure; +#define HTC_STATE_WAIT_BUFFERS (1 << 0) +#define HTC_STATE_STOPPING (1 << 1) +#ifdef HTC_CAPTURE_LAST_FRAME + HTC_FRAME_HDR LastFrameHdr; /* useful for debugging */ + A_UINT8 LastTrailer[256]; + A_UINT8 LastTrailerLength; +#endif + HTC_INIT_INFO HTCInitInfo; +} HTC_TARGET; + +#define HTC_STOPPING(t) ((t)->HTCStateFlags & HTC_STATE_STOPPING) +#define LOCK_HTC(t) A_MUTEX_LOCK(&(t)->HTCLock); +#define UNLOCK_HTC(t) A_MUTEX_UNLOCK(&(t)->HTCLock); +#define LOCK_HTC_RX(t) A_MUTEX_LOCK(&(t)->HTCRxLock); +#define UNLOCK_HTC_RX(t) A_MUTEX_UNLOCK(&(t)->HTCRxLock); +#define LOCK_HTC_TX(t) A_MUTEX_LOCK(&(t)->HTCTxLock); +#define UNLOCK_HTC_TX(t) A_MUTEX_UNLOCK(&(t)->HTCTxLock); + +#define GET_HTC_TARGET_FROM_HANDLE(hnd) ((HTC_TARGET *)(hnd)) +#define HTC_RECYCLE_RX_PKT(target,p,e) \ +{ \ + if ((e)->EpCallBacks.EpRecvAlloc != NULL) { \ + HTC_PACKET_RESET_RX(pPacket); \ + pPacket->Status = A_ECANCELED; \ + (e)->EpCallBacks.EpRecv((e)->EpCallBacks.pContext, \ + (p)); \ + } else { \ + HTC_PACKET_RESET_RX(pPacket); \ + HTCAddReceivePkt((HTC_HANDLE)(target),(p)); \ + } \ +} + +/* internal HTC functions */ +void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket); +void HTCControlRecv(void *Context, HTC_PACKET *pPacket); +A_STATUS HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket); +HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList); +void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList); +A_STATUS HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT8 Flags); +A_STATUS HTCIssueRecv(HTC_TARGET *target, HTC_PACKET *pPacket); +void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket); +A_STATUS HTCRecvMessagePendingHandler(void *Context, A_UINT32* LookAhead, A_BOOL *pAsyncProc); +void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint); +A_STATUS HTCSendSetupComplete(HTC_TARGET *target); +void HTCFlushRecvBuffers(HTC_TARGET *target); +void HTCFlushSendPkts(HTC_TARGET *target); +void DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist); +void DumpCreditDistStates(HTC_TARGET *target); +void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription); + +static INLINE HTC_PACKET *HTC_ALLOC_CONTROL_TX(HTC_TARGET *target) { + HTC_PACKET *pPacket = HTCAllocControlBuffer(target,&target->ControlBufferTXFreeList); + if (pPacket != NULL) { + /* set payload pointer area with some headroom */ + pPacket->pBuffer = pPacket->pBufferStart + HTC_HDR_LENGTH; + } + return pPacket; +} + +#define HTC_FREE_CONTROL_TX(t,p) HTCFreeControlBuffer((t),(p),&(t)->ControlBufferTXFreeList) +#define HTC_ALLOC_CONTROL_RX(t) HTCAllocControlBuffer((t),&(t)->ControlBufferRXFreeList) +#define HTC_FREE_CONTROL_RX(t,p) \ +{ \ + HTC_PACKET_RESET_RX(p); \ + HTCFreeControlBuffer((t),(p),&(t)->ControlBufferRXFreeList); \ +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HTC_INTERNAL_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/htc_packet.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc_packet.h --- linux-2.6.26/drivers/net/wireless/ath6k22/htc_packet.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc_packet.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,162 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef HTC_PACKET_H_ +#define HTC_PACKET_H_ + + +#include "dl_list.h" + +/* ------ Endpoint IDS ------ */ +typedef enum +{ + ENDPOINT_UNUSED = -1, + ENDPOINT_0 = 0, + ENDPOINT_1 = 1, + ENDPOINT_2 = 2, + ENDPOINT_3, + ENDPOINT_4, + ENDPOINT_5, + ENDPOINT_6, + ENDPOINT_7, + ENDPOINT_8, + ENDPOINT_MAX, +} HTC_ENDPOINT_ID; + +struct _HTC_PACKET; + +typedef void (* HTC_PACKET_COMPLETION)(void *,struct _HTC_PACKET *); + +typedef A_UINT16 HTC_TX_TAG; + +typedef struct _HTC_TX_PACKET_INFO { + HTC_TX_TAG Tag; /* tag used to selective flush packets */ +} HTC_TX_PACKET_INFO; + +#define HTC_TX_PACKET_TAG_ALL 0 /* a tag of zero is reserved and used to flush ALL packets */ +#define HTC_TX_PACKET_TAG_INTERNAL 1 /* internal tags start here */ +#define HTC_TX_PACKET_TAG_USER_DEFINED (HTC_TX_PACKET_TAG_INTERNAL + 9) /* user-defined tags start here */ + +typedef struct _HTC_RX_PACKET_INFO { + A_UINT32 IndicationFlags; +} HTC_RX_PACKET_INFO; + +#define HTC_RX_FLAGS_INDICATE_MORE_PKTS (1 << 0) + +/* wrapper around endpoint-specific packets */ +typedef struct _HTC_PACKET { + DL_LIST ListLink; /* double link */ + void *pPktContext; /* caller's per packet specific context */ + + A_UINT8 *pBufferStart; /* the true buffer start , the caller can + store the real buffer start here. In + receive callbacks, the HTC layer sets pBuffer + to the start of the payload past the header. This + field allows the caller to reset pBuffer when it + recycles receive packets back to HTC */ + /* + * Pointer to the start of the buffer. In the transmit + * direction this points to the start of the payload. In the + * receive direction, however, the buffer when queued up + * points to the start of the HTC header but when returned + * to the caller points to the start of the payload + */ + A_UINT8 *pBuffer; /* payload start (RX/TX) */ + A_UINT32 BufferLength; /* length of buffer */ + A_UINT32 ActualLength; /* actual length of payload */ + HTC_ENDPOINT_ID Endpoint; /* endpoint that this packet was sent/recv'd from */ + A_STATUS Status; /* completion status */ + union { + HTC_TX_PACKET_INFO AsTx; /* Tx Packet specific info */ + HTC_RX_PACKET_INFO AsRx; /* Rx Packet specific info */ + } PktInfo; + + /* the following fields are for internal HTC use */ + HTC_PACKET_COMPLETION Completion; /* completion */ + void *pContext; /* HTC private completion context */ + A_UINT32 HTCReserved; /* reserved */ +} HTC_PACKET; + + + +#define COMPLETE_HTC_PACKET(p,status) \ +{ \ + (p)->Status = (status); \ + (p)->Completion((p)->pContext,(p)); \ +} + +#define INIT_HTC_PACKET_INFO(p,b,len) \ +{ \ + (p)->pBufferStart = (b); \ + (p)->BufferLength = (len); \ +} + +/* macro to set an initial RX packet for refilling HTC */ +#define SET_HTC_PACKET_INFO_RX_REFILL(p,c,b,len,ep) \ +{ \ + (p)->pPktContext = (c); \ + (p)->pBuffer = (b); \ + (p)->pBufferStart = (b); \ + (p)->BufferLength = (len); \ + (p)->Endpoint = (ep); \ +} + +/* fast macro to recycle an RX packet that will be re-queued to HTC */ +#define HTC_PACKET_RESET_RX(p) \ + (p)->pBuffer = (p)->pBufferStart + +/* macro to set packet parameters for TX */ +#define SET_HTC_PACKET_INFO_TX(p,c,b,len,ep,tag) \ +{ \ + (p)->pPktContext = (c); \ + (p)->pBuffer = (b); \ + (p)->ActualLength = (len); \ + (p)->Endpoint = (ep); \ + (p)->PktInfo.AsTx.Tag = (tag); \ +} + +/* HTC Packet Queueing Macros */ +typedef DL_LIST HTC_PACKET_QUEUE; +/* initialize queue */ +#define INIT_HTC_PACKET_QUEUE(pQ) DL_LIST_INIT((pQ)) +/* enqueue HTC packet to the tail of the queue */ +#define HTC_PACKET_ENQUEUE(pQ,p) DL_ListInsertTail((pQ),&(p)->ListLink) +/* test if a queue is empty */ +#define HTC_QUEUE_EMPTY(pQ) DL_LIST_IS_EMPTY((pQ)) +/* get packet at head without removing it */ +#define HTC_GET_PKT_AT_HEAD(pQ) A_CONTAINING_STRUCT((DL_LIST_GET_ITEM_AT_HEAD(pQ)),HTC_PACKET,ListLink); +/* remove a packet from the current list it is linked to */ +#define HTC_PACKET_REMOVE(p) DL_ListRemove(&(p)->ListLink) + +/* dequeue an HTC packet from the head of the queue */ +static INLINE HTC_PACKET *HTC_PACKET_DEQUEUE(HTC_PACKET_QUEUE *queue) { + DL_LIST *pItem = DL_ListRemoveItemFromHead(queue); + if (pItem != NULL) { + return A_CONTAINING_STRUCT(pItem, HTC_PACKET, ListLink); + } + return NULL; +} + +#define HTC_GET_ENDPOINT_FROM_PKT(p) (p)->Endpoint +#define HTC_GET_TAG_FROM_PKT(p) (p)->PktInfo.AsTx.Tag + +#endif /*HTC_PACKET_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/htc_recv.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc_recv.c --- linux-2.6.26/drivers/net/wireless/ath6k22/htc_recv.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc_recv.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,785 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + +#define HTCIssueRecv(t, p) \ + DevRecvPacket(&(t)->Device, \ + (p), \ + (p)->ActualLength) + +#define DO_RCV_COMPLETION(t,p,e) \ +{ \ + if ((p)->ActualLength > 0) { \ + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" completing packet 0x%X (%d bytes) on ep : %d \n", \ + (A_UINT32)(p), (p)->ActualLength, (p)->Endpoint)); \ + (e)->EpCallBacks.EpRecv((e)->EpCallBacks.pContext, \ + (p)); \ + } else { \ + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" recycling empty packet \n")); \ + HTC_RECYCLE_RX_PKT((t), (p), (e)); \ + } \ +} + +#ifdef HTC_EP_STAT_PROFILING +#define HTC_RX_STAT_PROFILE(t,ep,lookAhead) \ +{ \ + LOCK_HTC_RX((t)); \ + INC_HTC_EP_STAT((ep), RxReceived, 1); \ + if ((lookAhead) != 0) { \ + INC_HTC_EP_STAT((ep), RxLookAheads, 1); \ + } \ + UNLOCK_HTC_RX((t)); \ +} +#else +#define HTC_RX_STAT_PROFILE(t,ep,lookAhead) +#endif + +static INLINE A_STATUS HTCProcessTrailer(HTC_TARGET *target, + A_UINT8 *pBuffer, + int Length, + A_UINT32 *pNextLookAhead, + HTC_ENDPOINT_ID FromEndpoint) +{ + HTC_RECORD_HDR *pRecord; + A_UINT8 *pRecordBuf; + HTC_LOOKAHEAD_REPORT *pLookAhead; + A_UINT8 *pOrigBuffer; + int origLength; + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessTrailer (length:%d) \n", Length)); + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + AR_DEBUG_PRINTBUF(pBuffer,Length,"Recv Trailer"); + } + + pOrigBuffer = pBuffer; + origLength = Length; + status = A_OK; + + while (Length > 0) { + + if (Length < sizeof(HTC_RECORD_HDR)) { + status = A_EPROTO; + break; + } + /* these are byte aligned structs */ + pRecord = (HTC_RECORD_HDR *)pBuffer; + Length -= sizeof(HTC_RECORD_HDR); + pBuffer += sizeof(HTC_RECORD_HDR); + + if (pRecord->Length > Length) { + /* no room left in buffer for record */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" invalid record length: %d (id:%d) buffer has: %d bytes left \n", + pRecord->Length, pRecord->RecordID, Length)); + status = A_EPROTO; + break; + } + /* start of record follows the header */ + pRecordBuf = pBuffer; + + switch (pRecord->RecordID) { + case HTC_RECORD_CREDITS: + AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_CREDIT_REPORT)); + HTCProcessCreditRpt(target, + (HTC_CREDIT_REPORT *)pRecordBuf, + pRecord->Length / (sizeof(HTC_CREDIT_REPORT)), + FromEndpoint); + break; + case HTC_RECORD_LOOKAHEAD: + AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_LOOKAHEAD_REPORT)); + pLookAhead = (HTC_LOOKAHEAD_REPORT *)pRecordBuf; + if ((pLookAhead->PreValid == ((~pLookAhead->PostValid) & 0xFF)) && + (pNextLookAhead != NULL)) { + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + (" LookAhead Report Found (pre valid:0x%X, post valid:0x%X) \n", + pLookAhead->PreValid, + pLookAhead->PostValid)); + + /* look ahead bytes are valid, copy them over */ + ((A_UINT8 *)pNextLookAhead)[0] = pLookAhead->LookAhead[0]; + ((A_UINT8 *)pNextLookAhead)[1] = pLookAhead->LookAhead[1]; + ((A_UINT8 *)pNextLookAhead)[2] = pLookAhead->LookAhead[2]; + ((A_UINT8 *)pNextLookAhead)[3] = pLookAhead->LookAhead[3]; + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + DebugDumpBytes((A_UINT8 *)pNextLookAhead,4,"Next Look Ahead"); + } + } + break; + default: + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" unhandled record: id:%d length:%d \n", + pRecord->RecordID, pRecord->Length)); + break; + } + + if (A_FAILED(status)) { + break; + } + + /* advance buffer past this record for next time around */ + pBuffer += pRecord->Length; + Length -= pRecord->Length; + } + + if (A_FAILED(status)) { + DebugDumpBytes(pOrigBuffer,origLength,"BAD Recv Trailer"); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessTrailer \n")); + return status; + +} + +/* process a received message (i.e. strip off header, process any trailer data) + * note : locks must be released when this function is called */ +static A_STATUS HTCProcessRecvHeader(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT32 *pNextLookAhead) +{ + A_UINT8 temp; + A_UINT8 *pBuf; + A_STATUS status = A_OK; + A_UINT16 payloadLen; + A_UINT32 lookAhead; + + pBuf = pPacket->pBuffer; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessRecvHeader \n")); + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + AR_DEBUG_PRINTBUF(pBuf,pPacket->ActualLength,"HTC Recv PKT"); + } + + do { + /* note, we cannot assume the alignment of pBuffer, so we use the safe macros to + * retrieve 16 bit fields */ + payloadLen = A_GET_UINT16_FIELD(pBuf, HTC_FRAME_HDR, PayloadLen); + + ((A_UINT8 *)&lookAhead)[0] = pBuf[0]; + ((A_UINT8 *)&lookAhead)[1] = pBuf[1]; + ((A_UINT8 *)&lookAhead)[2] = pBuf[2]; + ((A_UINT8 *)&lookAhead)[3] = pBuf[3]; + + if (lookAhead != pPacket->HTCReserved) { + /* somehow the lookahead that gave us the full read length did not + * reflect the actual header in the pending message */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCProcessRecvHeader, lookahead mismatch! \n")); + DebugDumpBytes((A_UINT8 *)&pPacket->HTCReserved,4,"Expected Message LookAhead"); + DebugDumpBytes(pBuf,sizeof(HTC_FRAME_HDR),"Current Frame Header"); +#ifdef HTC_CAPTURE_LAST_FRAME + DebugDumpBytes((A_UINT8 *)&target->LastFrameHdr,sizeof(HTC_FRAME_HDR),"Last Frame Header"); + if (target->LastTrailerLength != 0) { + DebugDumpBytes(target->LastTrailer, + target->LastTrailerLength, + "Last trailer"); + } +#endif + status = A_EPROTO; + break; + } + + /* get flags */ + temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, Flags); + + if (temp & HTC_FLAGS_RECV_TRAILER) { + /* this packet has a trailer */ + + /* extract the trailer length in control byte 0 */ + temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, ControlBytes[0]); + + if ((temp < sizeof(HTC_RECORD_HDR)) || (temp > payloadLen)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCProcessRecvHeader, invalid header (payloadlength should be :%d, CB[0] is:%d) \n", + payloadLen, temp)); + status = A_EPROTO; + break; + } + + /* process trailer data that follows HDR + application payload */ + status = HTCProcessTrailer(target, + (pBuf + HTC_HDR_LENGTH + payloadLen - temp), + temp, + pNextLookAhead, + pPacket->Endpoint); + + if (A_FAILED(status)) { + break; + } + +#ifdef HTC_CAPTURE_LAST_FRAME + A_MEMCPY(target->LastTrailer, (pBuf + HTC_HDR_LENGTH + payloadLen - temp), temp); + target->LastTrailerLength = temp; +#endif + /* trim length by trailer bytes */ + pPacket->ActualLength -= temp; + } +#ifdef HTC_CAPTURE_LAST_FRAME + else { + target->LastTrailerLength = 0; + } +#endif + + /* if we get to this point, the packet is good */ + /* remove header and adjust length */ + pPacket->pBuffer += HTC_HDR_LENGTH; + pPacket->ActualLength -= HTC_HDR_LENGTH; + + } while (FALSE); + + if (A_FAILED(status)) { + /* dump the whole packet */ + DebugDumpBytes(pBuf,pPacket->ActualLength,"BAD HTC Recv PKT"); + } else { +#ifdef HTC_CAPTURE_LAST_FRAME + A_MEMCPY(&target->LastFrameHdr,pBuf,sizeof(HTC_FRAME_HDR)); +#endif + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + if (pPacket->ActualLength > 0) { + AR_DEBUG_PRINTBUF(pPacket->pBuffer,pPacket->ActualLength,"HTC - Application Msg"); + } + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessRecvHeader \n")); + return status; +} + +/* asynchronous completion handler for recv packet fetching, when the device layer + * completes a read request, it will call this completion handler */ +void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + HTC_ENDPOINT *pEndpoint; + A_UINT32 nextLookAhead = 0; + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCRecvCompleteHandler (status:%d, ep:%d) \n", + pPacket->Status, pPacket->Endpoint)); + + AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX); + pEndpoint = &target->EndPoint[pPacket->Endpoint]; + pPacket->Completion = NULL; + + /* get completion status */ + status = pPacket->Status; + + do { + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HTCRecvCompleteHandler: request failed (status:%d, ep:%d) \n", + pPacket->Status, pPacket->Endpoint)); + break; + } + /* process the header for any trailer data */ + status = HTCProcessRecvHeader(target,pPacket,&nextLookAhead); + + if (A_FAILED(status)) { + break; + } + /* was there a lookahead for the next packet? */ + if (nextLookAhead != 0) { + A_STATUS nextStatus; + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("HTCRecvCompleteHandler - next look ahead was non-zero : 0x%X \n", + nextLookAhead)); + /* we have another packet, get the next packet fetch started (pipelined) before + * we call into the endpoint's callback, this will start another async request */ + nextStatus = HTCRecvMessagePendingHandler(target,&nextLookAhead,NULL); + if (A_EPROTO == nextStatus) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Next look ahead from recv header was INVALID\n")); + DebugDumpBytes((A_UINT8 *)&nextLookAhead, + 4, + "BAD lookahead from lookahead report"); + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("HTCRecvCompleteHandler - rechecking for more messages...\n")); + /* if we did not get anything on the look-ahead, + * call device layer to asynchronously re-check for messages. If we can keep the async + * processing going we get better performance. If there is a pending message we will keep processing + * messages asynchronously which should pipeline things nicely */ + DevCheckPendingRecvMsgsAsync(&target->Device); + } + + HTC_RX_STAT_PROFILE(target,pEndpoint,nextLookAhead); + DO_RCV_COMPLETION(target,pPacket,pEndpoint); + + } while (FALSE); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCRecvCompleteHandler , message fetch failed (status = %d) \n", + status)); + /* recyle this packet */ + HTC_RECYCLE_RX_PKT(target, pPacket, pEndpoint); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCRecvCompleteHandler\n")); +} + +/* synchronously wait for a control message from the target, + * This function is used at initialization time ONLY. At init messages + * on ENDPOINT 0 are expected. */ +A_STATUS HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket) +{ + A_STATUS status; + A_UINT32 lookAhead; + HTC_PACKET *pPacket = NULL; + HTC_FRAME_HDR *pHdr; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCWaitforControlMessage \n")); + + do { + + *ppControlPacket = NULL; + + /* call the polling function to see if we have a message */ + status = DevPollMboxMsgRecv(&target->Device, + &lookAhead, + HTC_TARGET_RESPONSE_TIMEOUT); + + if (A_FAILED(status)) { + break; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("HTCWaitforControlMessage : lookAhead : 0x%X \n", lookAhead)); + + /* check the lookahead */ + pHdr = (HTC_FRAME_HDR *)&lookAhead; + + if (pHdr->EndpointID != ENDPOINT_0) { + /* unexpected endpoint number, should be zero */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + if (A_FAILED(status)) { + /* bad message */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + pPacket = HTC_ALLOC_CONTROL_RX(target); + + if (pPacket == NULL) { + AR_DEBUG_ASSERT(FALSE); + status = A_NO_MEMORY; + break; + } + + pPacket->HTCReserved = lookAhead; + pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH; + + if (pPacket->ActualLength > pPacket->BufferLength) { + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + /* we want synchronous operation */ + pPacket->Completion = NULL; + + /* get the message from the device, this will block */ + status = HTCIssueRecv(target, pPacket); + + if (A_FAILED(status)) { + break; + } + + /* process receive header */ + status = HTCProcessRecvHeader(target,pPacket,NULL); + + pPacket->Status = status; + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCWaitforControlMessage, HTCProcessRecvHeader failed (status = %d) \n", + status)); + break; + } + + /* give the caller this control message packet, they are responsible to free */ + *ppControlPacket = pPacket; + + } while (FALSE); + + if (A_FAILED(status)) { + if (pPacket != NULL) { + /* cleanup buffer on error */ + HTC_FREE_CONTROL_RX(target,pPacket); + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCWaitforControlMessage \n")); + + return status; +} + +/* callback when device layer or lookahead report parsing detects a pending message */ +A_STATUS HTCRecvMessagePendingHandler(void *Context, A_UINT32 *LookAhead, A_BOOL *pAsyncProc) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + A_STATUS status = A_OK; + HTC_PACKET *pPacket = NULL; + HTC_FRAME_HDR *pHdr = NULL; + HTC_ENDPOINT *pEndpoint = NULL; + A_BOOL asyncProc = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCRecvMessagePendingHandler LookAhead:0x%X \n", *LookAhead)); + + if (IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(&target->Device)) { + /* We use async mode to get the packets if the device layer supports it. + * The device layer interfaces with HIF in which HIF may have restrictions on + * how interrupts are processed */ + asyncProc = TRUE; + } + + if (pAsyncProc != NULL) { + /* indicate to caller how we decided to process this */ + *pAsyncProc = asyncProc; + } + + while (TRUE) { + pHdr = (HTC_FRAME_HDR *)LookAhead; + + if (pHdr->EndpointID >= ENDPOINT_MAX) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Endpoint in look-ahead: %d \n",pHdr->EndpointID)); + /* invalid endpoint */ + status = A_EPROTO; + break; + } + + if (pHdr->PayloadLen > HTC_MAX_PAYLOAD_LENGTH) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Payload length %d exceeds max HTC : %d !\n", + pHdr->PayloadLen, HTC_MAX_PAYLOAD_LENGTH)); + status = A_EPROTO; + break; + } + + pEndpoint = &target->EndPoint[pHdr->EndpointID]; + + if (0 == pEndpoint->ServiceID) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Endpoint %d is not connected !\n",pHdr->EndpointID)); + /* endpoint isn't even connected */ + status = A_EPROTO; + break; + } + + if (pEndpoint->EpCallBacks.EpRecvAlloc != NULL) { + /* user is using a per-packet allocation callback */ + pPacket = pEndpoint->EpCallBacks.EpRecvAlloc(pEndpoint->EpCallBacks.pContext, + (HTC_ENDPOINT_ID) pHdr->EndpointID, + pHdr->PayloadLen + sizeof(HTC_FRAME_HDR)); + + /* lock RX, in case this allocation fails, we need to update internal state below */ + + LOCK_HTC_RX(target); + + } else { + /* user is using a refill handler that can refill multiple HTC buffers */ + /* lock RX to get a buffer */ + LOCK_HTC_RX(target); + + /* get a packet from the endpoint recv queue */ + pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers); + + if (NULL == pPacket) { + /* check for refill handler */ + if (pEndpoint->EpCallBacks.EpRecvRefill != NULL) { + UNLOCK_HTC_RX(target); + /* call the re-fill handler */ + pEndpoint->EpCallBacks.EpRecvRefill(pEndpoint->EpCallBacks.pContext, + (HTC_ENDPOINT_ID) pHdr->EndpointID); + LOCK_HTC_RX(target); + /* check if we have more buffers */ + pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers); + /* fall through */ + } + } + } + + if (NULL == pPacket) { + /* this is not an error, we simply need to mark that we are waiting for buffers.*/ + target->HTCStateFlags |= HTC_STATE_WAIT_BUFFERS; + target->EpWaitingForBuffers = (HTC_ENDPOINT_ID) pHdr->EndpointID; + status = A_NO_MEMORY; + } + + if (HTC_STOPPING(target)) { + status = A_ECANCELED; + } + + UNLOCK_HTC_RX(target); + + if (A_FAILED(status)) { + /* no buffers or stopping */ + break; + } + + pPacket->PktInfo.AsRx.IndicationFlags = 0; + + AR_DEBUG_ASSERT(pPacket->Endpoint == pHdr->EndpointID); + + /* make sure this message can fit in the endpoint buffer */ + if ((pHdr->PayloadLen + HTC_HDR_LENGTH) > pPacket->BufferLength) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Payload Length Error : header reports payload of: %d, endpoint buffer size: %d \n", + pHdr->PayloadLen, pPacket->BufferLength)); + status = A_EPROTO; + break; + } + + pPacket->HTCReserved = *LookAhead; /* set expected look ahead */ + /* set the amount of data to fetch */ + pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH; + + if (asyncProc) { + /* we use async mode to get the packet if the device layer supports it + * set our callback and context */ + pPacket->Completion = HTCRecvCompleteHandler; + pPacket->pContext = target; + } else { + /* fully synchronous */ + pPacket->Completion = NULL; + } + + /* go fetch the packet */ + status = HTCIssueRecv(target, pPacket); + + if (A_FAILED(status)) { + break; + } + + if (asyncProc) { + /* we did this asynchronously so we can get out of the loop, the asynch processing + * creates a chain of requests to continue processing pending messages in the + * context of callbacks */ + break; + } + + /* in the sync case, we process the packet, check lookaheads and then repeat */ + + *LookAhead = 0; + status = HTCProcessRecvHeader(target,pPacket,LookAhead); + + if (A_FAILED(status)) { + break; + } + + HTC_RX_STAT_PROFILE(target,pEndpoint,*LookAhead); + + /* check lookahead to see if we can indicate next packet hint to recv callback */ + if (LookAhead != 0) { + pHdr = (HTC_FRAME_HDR *)&LookAhead; + /* check to see if the "next" packet is from the same endpoint of the + completing packet */ + if (pHdr->EndpointID == pPacket->Endpoint) { + /* check that there is a buffer available to actually fetch it + * NOTE: no need to lock RX here , since we are synchronously processing RX + * and we are only looking at the queue (not modifying it) */ + if (!HTC_QUEUE_EMPTY(&pEndpoint->RxBuffers)) { + /* provide a hint that there are more RX packets to fetch */ + pPacket->PktInfo.AsRx.IndicationFlags |= HTC_RX_FLAGS_INDICATE_MORE_PKTS; + } + } + } + + DO_RCV_COMPLETION(target,pPacket,pEndpoint); + + pPacket = NULL; + + if (0 == *LookAhead) { + break; + } + + /* check whether other OS contexts have queued any WMI command/data for WLAN. + * This check is needed only if WLAN Tx and Rx happens in same thread context */ + A_CHECK_DRV_TX(); + } + + if (A_NO_MEMORY == status) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" Endpoint :%d has no buffers, blocking receiver to prevent overrun.. \n", + (pHdr != NULL) ? pHdr->EndpointID : 0xFFFF)); + /* try to stop receive at the device layer */ + DevStopRecv(&target->Device, asyncProc ? DEV_STOP_RECV_ASYNC : DEV_STOP_RECV_SYNC); + status = A_OK; + } else if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Failed to get pending message : LookAhead Value: 0x%X (status = %d) \n", + *LookAhead, status)); + if (pPacket != NULL) { + /* clean up packet on error */ + HTC_RECYCLE_RX_PKT(target, pPacket, pEndpoint); + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCRecvMessagePendingHandler \n")); + + return status; +} + +/* Makes a buffer available to the HTC module */ +A_STATUS HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint; + A_BOOL unblockRecv = FALSE; + A_STATUS status = A_OK; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("+- HTCAddReceivePkt: endPointId: %d, buffer: 0x%X, length: %d\n", + pPacket->Endpoint, (A_UINT32)pPacket->pBuffer, pPacket->BufferLength)); + + do { + AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX); + + pEndpoint = &target->EndPoint[pPacket->Endpoint]; + + LOCK_HTC_RX(target); + + if (HTC_STOPPING(target)) { + pPacket->Status = A_ECANCELED; + status = A_ECANCELED; + UNLOCK_HTC_RX(target); + pEndpoint->EpCallBacks.EpRecv(pEndpoint->EpCallBacks.pContext, pPacket); + break; + } + + /* store receive packet */ + HTC_PACKET_ENQUEUE(&pEndpoint->RxBuffers, pPacket); + + /* check if we are blocked waiting for a new buffer */ + if (target->HTCStateFlags & HTC_STATE_WAIT_BUFFERS) { + if (target->EpWaitingForBuffers == pPacket->Endpoint) { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" receiver was blocked on ep:%d, unblocking.. \n", + target->EpWaitingForBuffers)); + target->HTCStateFlags &= ~HTC_STATE_WAIT_BUFFERS; + target->EpWaitingForBuffers = ENDPOINT_MAX; + unblockRecv = TRUE; + } + } + + UNLOCK_HTC_RX(target); + + if (unblockRecv && !HTC_STOPPING(target)) { + /* TODO : implement a buffer threshold count? */ + DevEnableRecv(&target->Device,DEV_ENABLE_RECV_SYNC); + } + + } while (FALSE); + + return status; +} + +void HTCUnblockRecv(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_BOOL unblockRecv = FALSE; + + LOCK_HTC_RX(target); + + /* check if we are blocked waiting for a new buffer */ + if (target->HTCStateFlags & HTC_STATE_WAIT_BUFFERS) { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HTCUnblockRx : receiver was blocked on ep:%d, unblocking.. \n", + target->EpWaitingForBuffers)); + target->HTCStateFlags &= ~HTC_STATE_WAIT_BUFFERS; + target->EpWaitingForBuffers = ENDPOINT_MAX; + unblockRecv = TRUE; + } + + UNLOCK_HTC_RX(target); + + if (unblockRecv && !HTC_STOPPING(target)) { + /* re-enable */ + DevEnableRecv(&target->Device,DEV_ENABLE_RECV_ASYNC); + } +} + +static void HTCFlushEndpointRX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint) +{ + HTC_PACKET *pPacket; + + LOCK_HTC_RX(target); + + while (1) { + pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers); + if (NULL == pPacket) { + break; + } + UNLOCK_HTC_RX(target); + pPacket->Status = A_ECANCELED; + pPacket->ActualLength = 0; + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" Flushing RX packet:0x%X, length:%d, ep:%d \n", + (A_UINT32)pPacket, pPacket->BufferLength, pPacket->Endpoint)); + /* give the packet back */ + pEndpoint->EpCallBacks.EpRecv(pEndpoint->EpCallBacks.pContext, + pPacket); + LOCK_HTC_RX(target); + } + + UNLOCK_HTC_RX(target); + + +} + +void HTCFlushRecvBuffers(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + int i; + + for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) { + pEndpoint = &target->EndPoint[i]; + if (pEndpoint->ServiceID == 0) { + /* not in use.. */ + continue; + } + HTCFlushEndpointRX(target,pEndpoint); + } +} + + +void HTCEnableRecv(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + + if (!HTC_STOPPING(target)) { + /* re-enable */ + DevEnableRecv(&target->Device,DEV_ENABLE_RECV_SYNC); + } +} + +void HTCDisableRecv(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + + if (!HTC_STOPPING(target)) { + /* disable */ + DevStopRecv(&target->Device,DEV_ENABLE_RECV_SYNC); + } +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/htc_send.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc_send.c --- linux-2.6.26/drivers/net/wireless/ath6k22/htc_send.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc_send.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,612 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + +typedef enum _HTC_SEND_QUEUE_RESULT { + HTC_SEND_QUEUE_OK = 0, /* packet was queued */ + HTC_SEND_QUEUE_DROP = 1, /* this packet should be dropped */ +} HTC_SEND_QUEUE_RESULT; + +#define DO_EP_TX_COMPLETION(ep,p) \ +{ \ + (p)->Completion = NULL; \ + (ep)->EpCallBacks.EpTxComplete((ep)->EpCallBacks.pContext,(p)); \ +} + + +/* call the distribute credits callback with the distribution */ +#define DO_DISTRIBUTION(t,reason,description,pList) \ +{ \ + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, \ + (" calling distribute function (%s) (dfn:0x%X, ctxt:0x%X, dist:0x%X) \n", \ + (description), \ + (A_UINT32)(t)->DistributeCredits, \ + (A_UINT32)(t)->pCredDistContext, \ + (A_UINT32)pList)); \ + (t)->DistributeCredits((t)->pCredDistContext, \ + (pList), \ + (reason)); \ +} + +/* our internal send packet completion handler when packets are submited to the AR6K device + * layer */ +static void HTCSendPktCompletionHandler(void *Context, HTC_PACKET *pPacket) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + HTC_ENDPOINT *pEndpoint = &target->EndPoint[pPacket->Endpoint]; + + + if (A_FAILED(pPacket->Status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCSendPktCompletionHandler: request failed (status:%d, ep:%d) \n", + pPacket->Status, pPacket->Endpoint)); + } + /* first, fixup the head room we allocated */ + pPacket->pBuffer += HTC_HDR_LENGTH; + /* do completion */ + DO_EP_TX_COMPLETION(pEndpoint,pPacket); +} + +A_STATUS HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT8 SendFlags) +{ + A_STATUS status; + A_UINT8 *pHdrBuf; + A_BOOL sync = FALSE; + + /* caller always provides headrooom */ + pPacket->pBuffer -= HTC_HDR_LENGTH; + pHdrBuf = pPacket->pBuffer; + /* setup frame header */ + A_SET_UINT16_FIELD(pHdrBuf,HTC_FRAME_HDR,PayloadLen,(A_UINT16)pPacket->ActualLength); + A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,Flags,SendFlags); + A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,EndpointID, (A_UINT8)pPacket->Endpoint); + + if (pPacket->Completion == NULL) { + /* mark that this request was synchronously issued */ + sync = TRUE; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("+-HTCIssueSend: transmit length : %d (%s) \n", + pPacket->ActualLength + HTC_HDR_LENGTH, + sync ? "SYNC" : "ASYNC" )); + + /* send message to device */ + status = DevSendPacket(&target->Device, + pPacket, + pPacket->ActualLength + HTC_HDR_LENGTH); + + if (sync) { + /* use local sync variable. If this was issued asynchronously, pPacket is no longer + * safe to access. */ + pPacket->pBuffer += HTC_HDR_LENGTH; + } + + /* if this request was asynchronous, the packet completion routine will be invoked by + * the device layer when the HIF layer completes the request */ + + return status; +} + +/* try to send the current packet or a packet at the head of the TX queue, + * if there are no credits, the packet remains in the queue. + * this function returns the result of the attempt to send the HTC packet */ +static HTC_SEND_QUEUE_RESULT HTCTrySend(HTC_TARGET *target, + HTC_ENDPOINT *pEndpoint, + HTC_PACKET *pPacketToSend) +{ + HTC_PACKET *pPacket; + int creditsRequired; + int remainder; + A_UINT8 sendFlags; + HTC_SEND_QUEUE_RESULT result; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HTCTrySend (pPkt:0x%X)\n",(A_UINT32)pPacketToSend)); + + if (pPacketToSend != NULL) { + /* see if adding this packet hits the max depth */ + if ((pEndpoint->CurrentTxQueueDepth + 1) >= pEndpoint->MaxTxQueueDepth) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d, TX queue is full, Depth:%d, Max:%d \n", + pPacketToSend->Endpoint, pEndpoint->CurrentTxQueueDepth, pEndpoint->MaxTxQueueDepth)); + /* queue will be full, invoke any callbacks to determine what action to take */ + if (pEndpoint->EpCallBacks.EpSendFull != NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Calling driver's send full callback.... \n")); + if (pEndpoint->EpCallBacks.EpSendFull(pEndpoint->EpCallBacks.pContext, + pPacketToSend) == HTC_SEND_FULL_DROP) { + /* callback wants the packet dropped */ + INC_HTC_EP_STAT(pEndpoint, TxDropped, 1); + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend: \n")); + return HTC_SEND_QUEUE_DROP; + } + } + } + } + + LOCK_HTC_TX(target); + + result = HTC_SEND_QUEUE_OK; + + if (pPacketToSend != NULL) { + /* packet was supplied to be queued */ + HTC_PACKET_ENQUEUE(&pEndpoint->TxQueue,pPacketToSend); + pEndpoint->CurrentTxQueueDepth++; + } + + pEndpoint->TxProcessCount++; + if (pEndpoint->TxProcessCount > 1) { + /* another thread is draining the queues, get out */ + pEndpoint->TxProcessCount--; + UNLOCK_HTC_TX(target); + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend: \n")); + return HTC_SEND_QUEUE_OK; + } + + /* at this point, only 1 thread may enter to drain this endpoint queue */ + + /* now drain the TX queue for transmission as long as we have enough + * credits */ + + while (1) { + + if (HTC_QUEUE_EMPTY(&pEndpoint->TxQueue)) { + /* nothing in the queue */ + break; + } + + if (HTC_STOPPING(target)) { + if (pPacketToSend != NULL) { + HTC_PACKET_REMOVE(pPacketToSend); + pEndpoint->CurrentTxQueueDepth--; + result = HTC_SEND_QUEUE_DROP; + } + break; + } + + sendFlags = 0; + + /* get packet at head, but don't remove it */ + pPacket = HTC_GET_PKT_AT_HEAD(&pEndpoint->TxQueue); + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Got head packet:0x%X , Queue Depth: %d\n", + (A_UINT32)pPacket, pEndpoint->CurrentTxQueueDepth)); + + /* figure out how many credits this message requires */ + creditsRequired = (pPacket->ActualLength + HTC_HDR_LENGTH) / target->TargetCreditSize; + remainder = (pPacket->ActualLength + HTC_HDR_LENGTH) % target->TargetCreditSize; + + if (remainder) { + creditsRequired++; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Creds Required:%d Got:%d\n", + creditsRequired, pEndpoint->CreditDist.TxCredits)); + + if (pEndpoint->CreditDist.TxCredits < creditsRequired) { + + /* not enough credits */ + + if (pPacket->Endpoint == ENDPOINT_0) { + /* leave it in the queue */ + break; + } + /* invoke the registered distribution function only if this is not + * endpoint 0, we let the driver layer provide more credits if it can. + * We pass the credit distribution list starting at the endpoint in question + * */ + + /* set how many credits we need */ + pEndpoint->CreditDist.TxCreditsSeek = + creditsRequired - pEndpoint->CreditDist.TxCredits; + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_SEEK_CREDITS, + "Seek Credits", + &pEndpoint->CreditDist); + pEndpoint->CreditDist.TxCreditsSeek = 0; + + if (pEndpoint->CreditDist.TxCredits < creditsRequired) { + /* still not enough credits to send, leave packet in the queue */ + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + (" Not enough credits for ep %d leaving packet in queue..\n", + pPacket->Endpoint)); + break; + } + + } + + pEndpoint->CreditDist.TxCredits -= creditsRequired; + INC_HTC_EP_STAT(pEndpoint, TxCreditsConsummed, creditsRequired); + + /* check if we need credits back from the target */ + if (pEndpoint->CreditDist.TxCredits < pEndpoint->CreditDist.TxCreditsPerMaxMsg) { + /* we are getting low on credits, see if we can ask for more from the distribution function */ + pEndpoint->CreditDist.TxCreditsSeek = + pEndpoint->CreditDist.TxCreditsPerMaxMsg - pEndpoint->CreditDist.TxCredits; + + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_SEEK_CREDITS, + "Seek Credits", + &pEndpoint->CreditDist); + + pEndpoint->CreditDist.TxCreditsSeek = 0; + /* see if we were successful in getting more */ + if (pEndpoint->CreditDist.TxCredits < pEndpoint->CreditDist.TxCreditsPerMaxMsg) { + /* tell the target we need credits ASAP! */ + sendFlags |= HTC_FLAGS_NEED_CREDIT_UPDATE; + INC_HTC_EP_STAT(pEndpoint, TxCreditLowIndications, 1); + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Host Needs Credits \n")); + } + } + + /* now we can fully dequeue */ + pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->TxQueue); + pEndpoint->CurrentTxQueueDepth--; + + INC_HTC_EP_STAT(pEndpoint, TxIssued, 1); + + UNLOCK_HTC_TX(target); + + HTCIssueSend(target, pPacket, sendFlags); + + LOCK_HTC_TX(target); + + /* go back and check for more messages */ + } + + /* we're done, clear count */ + pEndpoint->TxProcessCount = 0; + UNLOCK_HTC_TX(target); + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend: \n")); + + return result; +} + +/* HTC API - HTCSendPkt */ +A_STATUS HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint; + HTC_ENDPOINT_ID ep; + A_STATUS status = A_OK; + HTC_SEND_QUEUE_RESULT result; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("+HTCSendPkt: Enter endPointId: %d, buffer: 0x%X, length: %d \n", + pPacket->Endpoint, (A_UINT32)pPacket->pBuffer, pPacket->ActualLength)); + + ep = pPacket->Endpoint; + AR_DEBUG_ASSERT(ep < ENDPOINT_MAX); + pEndpoint = &target->EndPoint[ep]; + + do { + + /* everything sent through this interface is asynchronous */ + /* fill in HTC completion routines */ + pPacket->Completion = HTCSendPktCompletionHandler; + pPacket->pContext = target; + + result = HTCTrySend(target, pEndpoint, pPacket); + + if (HTC_SEND_QUEUE_DROP == result) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d, TX packet dropped \n", ep)); + if (HTC_STOPPING(target)) { + status = A_ECANCELED; + } else { + status = A_NO_RESOURCE; + } + } + + } while (FALSE); + + if (A_FAILED(status)) { + pPacket->Status = status; + DO_EP_TX_COMPLETION(pEndpoint,pPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCSendPkt \n")); + + return status; +} + + +/* check TX queues to drain because of credit distribution update */ +static INLINE void HTCCheckEndpointTxQueues(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + HTC_ENDPOINT_CREDIT_DIST *pDistItem; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCCheckEndpointTxQueues \n")); + pDistItem = target->EpCreditDistributionListHead; + + /* run through the credit distribution list to see + * if there are packets queued + * NOTE: no locks need to be taken since the distribution list + * is not dynamic (cannot be re-ordered) and we are not modifying any state */ + while (pDistItem != NULL) { + pEndpoint = (HTC_ENDPOINT *)pDistItem->pHTCReserved; + + if (pEndpoint->CurrentTxQueueDepth > 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Ep %d has %d credits and %d Packets in TX Queue \n", + pDistItem->Endpoint, pEndpoint->CreditDist.TxCredits, pEndpoint->CurrentTxQueueDepth)); + /* try to start the stalled queue, this list is ordered by priority. + * Highest priority queue get's processed first, if there are credits available the + * highest priority queue will get a chance to reclaim credits from lower priority + * ones */ + HTCTrySend(target, pEndpoint, NULL); + } + + pDistItem = pDistItem->pNext; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCCheckEndpointTxQueues \n")); +} + +/* process credit reports and call distribution function */ +void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint) +{ + int i; + HTC_ENDPOINT *pEndpoint; + int totalCredits = 0; + A_BOOL doDist = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCProcessCreditRpt, Credit Report Entries:%d \n", NumEntries)); + + /* lock out TX while we update credits */ + LOCK_HTC_TX(target); + + for (i = 0; i < NumEntries; i++, pRpt++) { + if (pRpt->EndpointID >= ENDPOINT_MAX) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + pEndpoint = &target->EndPoint[pRpt->EndpointID]; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d got %d credits \n", + pRpt->EndpointID, pRpt->Credits)); + + +#ifdef HTC_EP_STAT_PROFILING + + INC_HTC_EP_STAT(pEndpoint, TxCreditRpts, 1); + INC_HTC_EP_STAT(pEndpoint, TxCreditsReturned, pRpt->Credits); + + if (FromEndpoint == pRpt->EndpointID) { + /* this credit report arrived on the same endpoint indicating it arrived in an RX + * packet */ + INC_HTC_EP_STAT(pEndpoint, TxCreditsFromRx, pRpt->Credits); + INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromRx, 1); + } else if (FromEndpoint == ENDPOINT_0) { + /* this credit arrived on endpoint 0 as a NULL message */ + INC_HTC_EP_STAT(pEndpoint, TxCreditsFromEp0, pRpt->Credits); + INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromEp0, 1); + } else { + /* arrived on another endpoint */ + INC_HTC_EP_STAT(pEndpoint, TxCreditsFromOther, pRpt->Credits); + INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromOther, 1); + } + +#endif + + if (ENDPOINT_0 == pRpt->EndpointID) { + /* always give endpoint 0 credits back */ + pEndpoint->CreditDist.TxCredits += pRpt->Credits; + } else { + /* for all other endpoints, update credits to distribute, the distribution function + * will handle giving out credits back to the endpoints */ + pEndpoint->CreditDist.TxCreditsToDist += pRpt->Credits; + /* flag that we have to do the distribution */ + doDist = TRUE; + } + + /* refresh tx depth for distribution function that will recover these credits + * NOTE: this is only valid when there are credits to recover! */ + pEndpoint->CreditDist.TxQueueDepth = pEndpoint->CurrentTxQueueDepth; + + totalCredits += pRpt->Credits; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Report indicated %d credits to distribute \n", totalCredits)); + + if (doDist) { + /* this was a credit return based on a completed send operations + * note, this is done with the lock held */ + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_SEND_COMPLETE, + "Send Complete", + target->EpCreditDistributionListHead->pNext); + } + + UNLOCK_HTC_TX(target); + + if (totalCredits) { + HTCCheckEndpointTxQueues(target); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCProcessCreditRpt \n")); +} + +/* flush endpoint TX queue */ +static void HTCFlushEndpointTX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint, HTC_TX_TAG Tag) +{ + HTC_PACKET *pPacket; + HTC_PACKET_QUEUE discardQueue; + + /* initialize the discard queue */ + INIT_HTC_PACKET_QUEUE(&discardQueue); + + LOCK_HTC_TX(target); + + /* interate from the front of the TX queue and flush out packets */ + ITERATE_OVER_LIST_ALLOW_REMOVE(&pEndpoint->TxQueue, pPacket, HTC_PACKET, ListLink) { + + /* check for removal */ + if ((HTC_TX_PACKET_TAG_ALL == Tag) || (Tag == pPacket->PktInfo.AsTx.Tag)) { + /* remove from queue */ + HTC_PACKET_REMOVE(pPacket); + /* add it to the discard pile */ + HTC_PACKET_ENQUEUE(&discardQueue, pPacket); + pEndpoint->CurrentTxQueueDepth--; + } + + } ITERATE_END; + + UNLOCK_HTC_TX(target); + + /* empty the discard queue */ + while (1) { + pPacket = HTC_PACKET_DEQUEUE(&discardQueue); + if (NULL == pPacket) { + break; + } + pPacket->Status = A_ECANCELED; + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" Flushing TX packet:0x%X, length:%d, ep:%d tag:0x%X \n", + (A_UINT32)pPacket, pPacket->ActualLength, pPacket->Endpoint, pPacket->PktInfo.AsTx.Tag)); + DO_EP_TX_COMPLETION(pEndpoint,pPacket); + } + +} + +void DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("--- EP : %d ServiceID: 0x%X --------------\n", + pEPDist->Endpoint, pEPDist->ServiceID)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" this:0x%X next:0x%X prev:0x%X\n", + (A_UINT32)pEPDist, (A_UINT32)pEPDist->pNext, (A_UINT32)pEPDist->pPrev)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" DistFlags : 0x%X \n", pEPDist->DistFlags)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsNorm : %d \n", pEPDist->TxCreditsNorm)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsMin : %d \n", pEPDist->TxCreditsMin)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCredits : %d \n", pEPDist->TxCredits)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsAssigned : %d \n", pEPDist->TxCreditsAssigned)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsSeek : %d \n", pEPDist->TxCreditsSeek)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditSize : %d \n", pEPDist->TxCreditSize)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsPerMaxMsg : %d \n", pEPDist->TxCreditsPerMaxMsg)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsToDist : %d \n", pEPDist->TxCreditsToDist)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxQueueDepth : %d \n", + ((HTC_ENDPOINT *) pEPDist->pHTCReserved)->CurrentTxQueueDepth)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("----------------------------------------------------\n")); +} + +void DumpCreditDistStates(HTC_TARGET *target) +{ + HTC_ENDPOINT_CREDIT_DIST *pEPList = target->EpCreditDistributionListHead; + + while (pEPList != NULL) { + DumpCreditDist(pEPList); + pEPList = pEPList->pNext; + } + + if (target->DistributeCredits != NULL) { + DO_DISTRIBUTION(target, + HTC_DUMP_CREDIT_STATE, + "Dump State", + NULL); + } +} + +/* flush all send packets from all endpoint queues */ +void HTCFlushSendPkts(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + int i; + + DumpCreditDistStates(target); + + for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) { + pEndpoint = &target->EndPoint[i]; + if (pEndpoint->ServiceID == 0) { + /* not in use.. */ + continue; + } + HTCFlushEndpointTX(target,pEndpoint,HTC_TX_PACKET_TAG_ALL); + } + + +} + +/* HTC API to flush an endpoint's TX queue*/ +void HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint = &target->EndPoint[Endpoint]; + + if (pEndpoint->ServiceID == 0) { + AR_DEBUG_ASSERT(FALSE); + /* not in use.. */ + return; + } + + HTCFlushEndpointTX(target, pEndpoint, Tag); +} + +/* HTC API to indicate activity to the credit distribution function */ +void HTCIndicateActivityChange(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + A_BOOL Active) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint = &target->EndPoint[Endpoint]; + A_BOOL doDist = FALSE; + + if (pEndpoint->ServiceID == 0) { + AR_DEBUG_ASSERT(FALSE); + /* not in use.. */ + return; + } + + LOCK_HTC_TX(target); + + if (Active) { + if (!(pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE)) { + /* mark active now */ + pEndpoint->CreditDist.DistFlags |= HTC_EP_ACTIVE; + doDist = TRUE; + } + } else { + if (pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE) { + /* mark inactive now */ + pEndpoint->CreditDist.DistFlags &= ~HTC_EP_ACTIVE; + doDist = TRUE; + } + } + + if (doDist) { + /* indicate current Tx Queue depth to the credit distribution function */ + pEndpoint->CreditDist.TxQueueDepth = pEndpoint->CurrentTxQueueDepth; + /* do distribution again based on activity change + * note, this is done with the lock held */ + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_ACTIVITY_CHANGE, + "Activity Change", + target->EpCreditDistributionListHead->pNext); + } + + UNLOCK_HTC_TX(target); + + if (doDist && !Active) { + /* if a stream went inactive and this resulted in a credit distribution change, + * some credits may now be available for HTC packets that are stuck in + * HTC queues */ + HTCCheckEndpointTxQueues(target); + } +} + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/htc_services.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc_services.c --- linux-2.6.26/drivers/net/wireless/ath6k22/htc_services.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc_services.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,412 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + +void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket) +{ + /* not implemented + * we do not send control TX frames during normal runtime, only during setup */ + AR_DEBUG_ASSERT(FALSE); +} + + /* callback when a control message arrives on this endpoint */ +void HTCControlRecv(void *Context, HTC_PACKET *pPacket) +{ + AR_DEBUG_ASSERT(pPacket->Endpoint == ENDPOINT_0); + + if (pPacket->Status == A_ECANCELED) { + /* this is a flush operation, return the control packet back to the pool */ + HTC_FREE_CONTROL_RX((HTC_TARGET*)Context,pPacket); + return; + } + + /* the only control messages we are expecting are NULL messages (credit resports), which should + * never get here */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCControlRecv, got message with length:%d \n", + pPacket->ActualLength + HTC_HDR_LENGTH)); + + /* dump header and message */ + DebugDumpBytes(pPacket->pBuffer - HTC_HDR_LENGTH, + pPacket->ActualLength + HTC_HDR_LENGTH, + "Unexpected ENDPOINT 0 Message"); + + HTC_RECYCLE_RX_PKT((HTC_TARGET*)Context,pPacket,&((HTC_TARGET*)Context)->EndPoint[0]); +} + +A_STATUS HTCSendSetupComplete(HTC_TARGET *target) +{ + HTC_PACKET *pSendPacket = NULL; + A_STATUS status; + HTC_SETUP_COMPLETE_MSG *pSetupComplete; + + do { + /* allocate a packet to send to the target */ + pSendPacket = HTC_ALLOC_CONTROL_TX(target); + + if (NULL == pSendPacket) { + status = A_NO_MEMORY; + break; + } + + /* assemble setup complete message */ + pSetupComplete = (HTC_SETUP_COMPLETE_MSG *)pSendPacket->pBuffer; + A_MEMZERO(pSetupComplete,sizeof(HTC_SETUP_COMPLETE_MSG)); + pSetupComplete->MessageID = HTC_MSG_SETUP_COMPLETE_ID; + + SET_HTC_PACKET_INFO_TX(pSendPacket, + NULL, + (A_UINT8 *)pSetupComplete, + sizeof(HTC_SETUP_COMPLETE_MSG), + ENDPOINT_0, + HTC_SERVICE_TX_PACKET_TAG); + + /* we want synchronous operation */ + pSendPacket->Completion = NULL; + /* send the message */ + status = HTCIssueSend(target,pSendPacket,0); + + } while (FALSE); + + if (pSendPacket != NULL) { + HTC_FREE_CONTROL_TX(target,pSendPacket); + } + + return status; +} + + +A_STATUS HTCConnectService(HTC_HANDLE HTCHandle, + HTC_SERVICE_CONNECT_REQ *pConnectReq, + HTC_SERVICE_CONNECT_RESP *pConnectResp) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_STATUS status = A_OK; + HTC_PACKET *pRecvPacket = NULL; + HTC_PACKET *pSendPacket = NULL; + HTC_CONNECT_SERVICE_RESPONSE_MSG *pResponseMsg; + HTC_CONNECT_SERVICE_MSG *pConnectMsg; + HTC_ENDPOINT_ID assignedEndpoint = ENDPOINT_MAX; + HTC_ENDPOINT *pEndpoint; + int maxMsgSize = 0; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCConnectService, target:0x%X SvcID:0x%X \n", + (A_UINT32)target, pConnectReq->ServiceID)); + + do { + + AR_DEBUG_ASSERT(pConnectReq->ServiceID != 0); + + if (HTC_CTRL_RSVD_SVC == pConnectReq->ServiceID) { + /* special case for pseudo control service */ + assignedEndpoint = ENDPOINT_0; + maxMsgSize = HTC_MAX_CONTROL_MESSAGE_LENGTH; + } else { + /* allocate a packet to send to the target */ + pSendPacket = HTC_ALLOC_CONTROL_TX(target); + + if (NULL == pSendPacket) { + AR_DEBUG_ASSERT(FALSE); + status = A_NO_MEMORY; + break; + } + /* assemble connect service message */ + pConnectMsg = (HTC_CONNECT_SERVICE_MSG *)pSendPacket->pBuffer; + AR_DEBUG_ASSERT(pConnectMsg != NULL); + A_MEMZERO(pConnectMsg,sizeof(HTC_CONNECT_SERVICE_MSG)); + pConnectMsg->MessageID = HTC_MSG_CONNECT_SERVICE_ID; + pConnectMsg->ServiceID = pConnectReq->ServiceID; + pConnectMsg->ConnectionFlags = pConnectReq->ConnectionFlags; + /* check caller if it wants to transfer meta data */ + if ((pConnectReq->pMetaData != NULL) && + (pConnectReq->MetaDataLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) { + /* copy meta data into message buffer (after header ) */ + A_MEMCPY((A_UINT8 *)pConnectMsg + sizeof(HTC_CONNECT_SERVICE_MSG), + pConnectReq->pMetaData, + pConnectReq->MetaDataLength); + pConnectMsg->ServiceMetaLength = pConnectReq->MetaDataLength; + } + + SET_HTC_PACKET_INFO_TX(pSendPacket, + NULL, + (A_UINT8 *)pConnectMsg, + sizeof(HTC_CONNECT_SERVICE_MSG) + pConnectMsg->ServiceMetaLength, + ENDPOINT_0, + HTC_SERVICE_TX_PACKET_TAG); + + /* we want synchronous operation */ + pSendPacket->Completion = NULL; + + status = HTCIssueSend(target,pSendPacket,0); + + if (A_FAILED(status)) { + break; + } + + /* wait for response */ + status = HTCWaitforControlMessage(target, &pRecvPacket); + + if (A_FAILED(status)) { + break; + } + /* we controlled the buffer creation so it has to be properly aligned */ + pResponseMsg = (HTC_CONNECT_SERVICE_RESPONSE_MSG *)pRecvPacket->pBuffer; + + if ((pResponseMsg->MessageID != HTC_MSG_CONNECT_SERVICE_RESPONSE_ID) || + (pRecvPacket->ActualLength < sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG))) { + /* this message is not valid */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + pConnectResp->ConnectRespCode = pResponseMsg->Status; + /* check response status */ + if (pResponseMsg->Status != HTC_SERVICE_SUCCESS) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" Target failed service 0x%X connect request (status:%d)\n", + pResponseMsg->ServiceID, pResponseMsg->Status)); + status = A_EPROTO; + break; + } + + assignedEndpoint = (HTC_ENDPOINT_ID) pResponseMsg->EndpointID; + maxMsgSize = pResponseMsg->MaxMsgSize; + + if ((pConnectResp->pMetaData != NULL) && + (pResponseMsg->ServiceMetaLength > 0) && + (pResponseMsg->ServiceMetaLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) { + /* caller supplied a buffer and the target responded with data */ + int copyLength = min((int)pConnectResp->BufferLength, (int)pResponseMsg->ServiceMetaLength); + /* copy the meta data */ + A_MEMCPY(pConnectResp->pMetaData, + ((A_UINT8 *)pResponseMsg) + sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG), + copyLength); + pConnectResp->ActualLength = copyLength; + } + + } + + /* the rest of these are parameter checks so set the error status */ + status = A_EPROTO; + + if (assignedEndpoint >= ENDPOINT_MAX) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + if (0 == maxMsgSize) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + pEndpoint = &target->EndPoint[assignedEndpoint]; + + if (pEndpoint->ServiceID != 0) { + /* endpoint already in use! */ + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* return assigned endpoint to caller */ + pConnectResp->Endpoint = assignedEndpoint; + pConnectResp->MaxMsgLength = maxMsgSize; + + /* setup the endpoint */ + pEndpoint->ServiceID = pConnectReq->ServiceID; /* this marks the endpoint in use */ + pEndpoint->MaxTxQueueDepth = pConnectReq->MaxSendQueueDepth; + pEndpoint->MaxMsgLength = maxMsgSize; + /* copy all the callbacks */ + pEndpoint->EpCallBacks = pConnectReq->EpCallbacks; + INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBuffers); + INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue); + /* set the credit distribution info for this endpoint, this information is + * passed back to the credit distribution callback function */ + pEndpoint->CreditDist.ServiceID = pConnectReq->ServiceID; + pEndpoint->CreditDist.pHTCReserved = pEndpoint; + pEndpoint->CreditDist.Endpoint = assignedEndpoint; + pEndpoint->CreditDist.TxCreditSize = target->TargetCreditSize; + pEndpoint->CreditDist.TxCreditsPerMaxMsg = maxMsgSize / target->TargetCreditSize; + + if (0 == pEndpoint->CreditDist.TxCreditsPerMaxMsg) { + pEndpoint->CreditDist.TxCreditsPerMaxMsg = 1; + } + + status = A_OK; + + } while (FALSE); + + if (pSendPacket != NULL) { + HTC_FREE_CONTROL_TX(target,pSendPacket); + } + + if (pRecvPacket != NULL) { + HTC_FREE_CONTROL_RX(target,pRecvPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCConnectService \n")); + + return status; +} + +static void AddToEndpointDistList(HTC_TARGET *target, HTC_ENDPOINT_CREDIT_DIST *pEpDist) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEntry,*pLastEntry; + + if (NULL == target->EpCreditDistributionListHead) { + target->EpCreditDistributionListHead = pEpDist; + pEpDist->pNext = NULL; + pEpDist->pPrev = NULL; + return; + } + + /* queue to the end of the list, this does not have to be very + * fast since this list is built at startup time */ + pCurEntry = target->EpCreditDistributionListHead; + + while (pCurEntry) { + pLastEntry = pCurEntry; + pCurEntry = pCurEntry->pNext; + } + + pLastEntry->pNext = pEpDist; + pEpDist->pPrev = pLastEntry; + pEpDist->pNext = NULL; +} + + + +/* default credit init callback */ +static void HTCDefaultCreditInit(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + int TotalCredits) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + int totalEps = 0; + int creditsPerEndpoint; + + pCurEpDist = pEPList; + /* first run through the list and figure out how many endpoints we are dealing with */ + while (pCurEpDist != NULL) { + pCurEpDist = pCurEpDist->pNext; + totalEps++; + } + + /* even distribution */ + creditsPerEndpoint = TotalCredits/totalEps; + + pCurEpDist = pEPList; + /* run through the list and set minimum and normal credits and + * provide the endpoint with some credits to start */ + while (pCurEpDist != NULL) { + + if (creditsPerEndpoint < pCurEpDist->TxCreditsPerMaxMsg) { + /* too many endpoints and not enough credits */ + AR_DEBUG_ASSERT(FALSE); + break; + } + /* our minimum is set for at least 1 max message */ + pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg; + /* this value is ignored by our credit alg, since we do + * not dynamically adjust credits, this is the policy of + * the "default" credit distribution, something simple and easy */ + pCurEpDist->TxCreditsNorm = 0xFFFF; + /* give the endpoint minimum credits */ + pCurEpDist->TxCredits = creditsPerEndpoint; + pCurEpDist->TxCreditsAssigned = creditsPerEndpoint; + pCurEpDist = pCurEpDist->pNext; + } + +} + +/* default credit distribution callback, NOTE, this callback holds the TX lock */ +void HTCDefaultCreditDist(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList, + HTC_CREDIT_DIST_REASON Reason) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + + if (Reason == HTC_CREDIT_DIST_SEND_COMPLETE) { + pCurEpDist = pEPDistList; + /* simple distribution */ + while (pCurEpDist != NULL) { + if (pCurEpDist->TxCreditsToDist > 0) { + /* just give the endpoint back the credits */ + pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist; + pCurEpDist->TxCreditsToDist = 0; + } + pCurEpDist = pCurEpDist->pNext; + } + } + + /* note we do not need to handle the other reason codes as this is a very + * simple distribution scheme, no need to seek for more credits or handle inactivity */ +} + +void HTCSetCreditDistribution(HTC_HANDLE HTCHandle, + void *pCreditDistContext, + HTC_CREDIT_DIST_CALLBACK CreditDistFunc, + HTC_CREDIT_INIT_CALLBACK CreditInitFunc, + HTC_SERVICE_ID ServicePriorityOrder[], + int ListLength) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + int i; + int ep; + + if (CreditInitFunc != NULL) { + /* caller has supplied their own distribution functions */ + target->InitCredits = CreditInitFunc; + AR_DEBUG_ASSERT(CreditDistFunc != NULL); + target->DistributeCredits = CreditDistFunc; + target->pCredDistContext = pCreditDistContext; + } else { + /* caller wants HTC to do distribution */ + /* if caller wants service to handle distributions then + * it must set both of these to NULL! */ + AR_DEBUG_ASSERT(CreditDistFunc == NULL); + target->InitCredits = HTCDefaultCreditInit; + target->DistributeCredits = HTCDefaultCreditDist; + target->pCredDistContext = target; + } + + /* always add HTC control endpoint first, we only expose the list after the + * first one, this is added for TX queue checking */ + AddToEndpointDistList(target, &target->EndPoint[ENDPOINT_0].CreditDist); + + /* build the list of credit distribution structures in priority order + * supplied by the caller, these will follow endpoint 0 */ + for (i = 0; i < ListLength; i++) { + /* match services with endpoints and add the endpoints to the distribution list + * in FIFO order */ + for (ep = ENDPOINT_1; ep < ENDPOINT_MAX; ep++) { + if (target->EndPoint[ep].ServiceID == ServicePriorityOrder[i]) { + /* queue this one to the list */ + AddToEndpointDistList(target, &target->EndPoint[ep].CreditDist); + break; + } + } + AR_DEBUG_ASSERT(ep < ENDPOINT_MAX); + } + +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/htc_services.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc_services.h --- linux-2.6.26/drivers/net/wireless/ath6k22/htc_services.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/htc_services.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __HTC_SERVICES_H__ +#define __HTC_SERVICES_H__ + +/* Current service IDs */ + +typedef enum { + RSVD_SERVICE_GROUP = 0, + WMI_SERVICE_GROUP = 1, + + HTC_TEST_GROUP = 254, + HTC_SERVICE_GROUP_LAST = 255 +}HTC_SERVICE_GROUP_IDS; + +#define MAKE_SERVICE_ID(group,index) \ + (int)(((int)group << 8) | (int)(index)) + +/* NOTE: service ID of 0x0000 is reserved and should never be used */ +#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1) +#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0) +#define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1) +#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2) +#define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3) +#define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4) +#define WMI_MAX_SERVICES 5 + +/* raw stream service (i.e. flash, tcmd, calibration apps) */ +#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0) + +#endif /*HTC_SERVICES_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/ieee80211.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ieee80211.h --- linux-2.6.26/drivers/net/wireless/ath6k22/ieee80211.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ieee80211.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,404 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _NET80211_IEEE80211_H_ +#define _NET80211_IEEE80211_H_ + +#include "athstartpack.h" + +/* + * 802.11 protocol definitions. + */ +#define IEEE80211_WEP_KEYLEN 5 /* 40bit */ +#define IEEE80211_WEP_IVLEN 3 /* 24bit */ +#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ +#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ +#define IEEE80211_WEP_NKID 4 /* number of key ids */ + +/* + * 802.11i defines an extended IV for use with non-WEP ciphers. + * When the EXTIV bit is set in the key id byte an additional + * 4 bytes immediately follow the IV for TKIP. For CCMP the + * EXTIV bit is likewise set but the 8 bytes represent the + * CCMP header rather than IV+extended-IV. + */ +#define IEEE80211_WEP_EXTIV 0x20 +#define IEEE80211_WEP_EXTIVLEN 4 /* extended IV length */ +#define IEEE80211_WEP_MICLEN 8 /* trailing MIC */ + +#define IEEE80211_CRC_LEN 4 + +#ifdef WAPI_ENABLE +#define IEEE80211_WAPI_EXTIVLEN 10 /* extended IV length */ +#endif /* WAPI ENABLE */ + + +#define IEEE80211_ADDR_LEN 6 /* size of 802.11 address */ +/* is 802.11 address multicast/broadcast? */ +#define IEEE80211_IS_MULTICAST(_a) (*(_a) & 0x01) +#define IEEE80211_IS_BROADCAST(_a) (*(_a) == 0xFF) +#define WEP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN) +#define WEP_TRAILER IEEE80211_WEP_CRCLEN +#define CCMP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + \ + IEEE80211_WEP_EXTIVLEN) +#define CCMP_TRAILER IEEE80211_WEP_MICLEN +#define TKIP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + \ + IEEE80211_WEP_EXTIVLEN) +#define TKIP_TRAILER IEEE80211_WEP_CRCLEN +#define TKIP_MICLEN IEEE80211_WEP_MICLEN + + +#define IEEE80211_ADDR_EQ(addr1, addr2) \ + (A_MEMCMP(addr1, addr2, IEEE80211_ADDR_LEN) == 0) + +#define IEEE80211_ADDR_COPY(dst,src) A_MEMCPY(dst,src,IEEE80211_ADDR_LEN) + +#define IEEE80211_KEYBUF_SIZE 16 +#define IEEE80211_MICBUF_SIZE (8+8) /* space for both tx and rx */ + +/* + * NB: these values are ordered carefully; there are lots of + * of implications in any reordering. In particular beware + * that 4 is not used to avoid conflicting with IEEE80211_F_PRIVACY. + */ +#define IEEE80211_CIPHER_WEP 0 +#define IEEE80211_CIPHER_TKIP 1 +#define IEEE80211_CIPHER_AES_OCB 2 +#define IEEE80211_CIPHER_AES_CCM 3 +#define IEEE80211_CIPHER_CKIP 5 +#define IEEE80211_CIPHER_CCKM_KRK 6 +#define IEEE80211_CIPHER_NONE 7 /* pseudo value */ + +#define IEEE80211_CIPHER_MAX (IEEE80211_CIPHER_NONE+1) + +#define IEEE80211_IS_VALID_WEP_CIPHER_LEN(len) \ + (((len) == 5) || ((len) == 13) || ((len) == 16)) + + + +/* + * generic definitions for IEEE 802.11 frames + */ +PREPACK struct ieee80211_frame { + A_UINT8 i_fc[2]; + A_UINT8 i_dur[2]; + A_UINT8 i_addr1[IEEE80211_ADDR_LEN]; + A_UINT8 i_addr2[IEEE80211_ADDR_LEN]; + A_UINT8 i_addr3[IEEE80211_ADDR_LEN]; + A_UINT8 i_seq[2]; + /* possibly followed by addr4[IEEE80211_ADDR_LEN]; */ + /* see below */ +} POSTPACK; + +PREPACK struct ieee80211_qosframe { + A_UINT8 i_fc[2]; + A_UINT8 i_dur[2]; + A_UINT8 i_addr1[IEEE80211_ADDR_LEN]; + A_UINT8 i_addr2[IEEE80211_ADDR_LEN]; + A_UINT8 i_addr3[IEEE80211_ADDR_LEN]; + A_UINT8 i_seq[2]; + A_UINT8 i_qos[2]; +} POSTPACK; + +#define IEEE80211_FC0_VERSION_MASK 0x03 +#define IEEE80211_FC0_VERSION_SHIFT 0 +#define IEEE80211_FC0_VERSION_0 0x00 +#define IEEE80211_FC0_TYPE_MASK 0x0c +#define IEEE80211_FC0_TYPE_SHIFT 2 +#define IEEE80211_FC0_TYPE_MGT 0x00 +#define IEEE80211_FC0_TYPE_CTL 0x04 +#define IEEE80211_FC0_TYPE_DATA 0x08 + +#define IEEE80211_FC0_SUBTYPE_MASK 0xf0 +#define IEEE80211_FC0_SUBTYPE_SHIFT 4 +/* for TYPE_MGT */ +#define IEEE80211_FC0_SUBTYPE_ASSOC_REQ 0x00 +#define IEEE80211_FC0_SUBTYPE_ASSOC_RESP 0x10 +#define IEEE80211_FC0_SUBTYPE_REASSOC_REQ 0x20 +#define IEEE80211_FC0_SUBTYPE_REASSOC_RESP 0x30 +#define IEEE80211_FC0_SUBTYPE_PROBE_REQ 0x40 +#define IEEE80211_FC0_SUBTYPE_PROBE_RESP 0x50 +#define IEEE80211_FC0_SUBTYPE_BEACON 0x80 +#define IEEE80211_FC0_SUBTYPE_ATIM 0x90 +#define IEEE80211_FC0_SUBTYPE_DISASSOC 0xa0 +#define IEEE80211_FC0_SUBTYPE_AUTH 0xb0 +#define IEEE80211_FC0_SUBTYPE_DEAUTH 0xc0 +/* for TYPE_CTL */ +#define IEEE80211_FC0_SUBTYPE_PS_POLL 0xa0 +#define IEEE80211_FC0_SUBTYPE_RTS 0xb0 +#define IEEE80211_FC0_SUBTYPE_CTS 0xc0 +#define IEEE80211_FC0_SUBTYPE_ACK 0xd0 +#define IEEE80211_FC0_SUBTYPE_CF_END 0xe0 +#define IEEE80211_FC0_SUBTYPE_CF_END_ACK 0xf0 +/* for TYPE_DATA (bit combination) */ +#define IEEE80211_FC0_SUBTYPE_DATA 0x00 +#define IEEE80211_FC0_SUBTYPE_CF_ACK 0x10 +#define IEEE80211_FC0_SUBTYPE_CF_POLL 0x20 +#define IEEE80211_FC0_SUBTYPE_CF_ACPL 0x30 +#define IEEE80211_FC0_SUBTYPE_NODATA 0x40 +#define IEEE80211_FC0_SUBTYPE_CFACK 0x50 +#define IEEE80211_FC0_SUBTYPE_CFPOLL 0x60 +#define IEEE80211_FC0_SUBTYPE_CF_ACK_CF_ACK 0x70 +#define IEEE80211_FC0_SUBTYPE_QOS 0x80 +#define IEEE80211_FC0_SUBTYPE_QOS_NULL 0xc0 + +#define IEEE80211_FC1_DIR_MASK 0x03 +#define IEEE80211_FC1_DIR_NODS 0x00 /* STA->STA */ +#define IEEE80211_FC1_DIR_TODS 0x01 /* STA->AP */ +#define IEEE80211_FC1_DIR_FROMDS 0x02 /* AP ->STA */ +#define IEEE80211_FC1_DIR_DSTODS 0x03 /* AP ->AP */ + +#define IEEE80211_FC1_MORE_FRAG 0x04 +#define IEEE80211_FC1_RETRY 0x08 +#define IEEE80211_FC1_PWR_MGT 0x10 +#define IEEE80211_FC1_MORE_DATA 0x20 +#define IEEE80211_FC1_WEP 0x40 +#define IEEE80211_FC1_ORDER 0x80 + +#define IEEE80211_SEQ_FRAG_MASK 0x000f +#define IEEE80211_SEQ_FRAG_SHIFT 0 +#define IEEE80211_SEQ_SEQ_MASK 0xfff0 +#define IEEE80211_SEQ_SEQ_SHIFT 4 + +#define IEEE80211_NWID_LEN 32 + +/* + * 802.11 rate set. + */ +#define IEEE80211_RATE_SIZE 8 /* 802.11 standard */ +#define IEEE80211_RATE_MAXSIZE 15 /* max rates we'll handle */ + +#define WMM_NUM_AC 4 /* 4 AC categories */ + +#define WMM_PARAM_ACI_M 0x60 /* Mask for ACI field */ +#define WMM_PARAM_ACI_S 5 /* Shift for ACI field */ +#define WMM_PARAM_ACM_M 0x10 /* Mask for ACM bit */ +#define WMM_PARAM_ACM_S 4 /* Shift for ACM bit */ +#define WMM_PARAM_AIFSN_M 0x0f /* Mask for aifsn field */ +#define WMM_PARAM_LOGCWMIN_M 0x0f /* Mask for CwMin field (in log) */ +#define WMM_PARAM_LOGCWMAX_M 0xf0 /* Mask for CwMax field (in log) */ +#define WMM_PARAM_LOGCWMAX_S 4 /* Shift for CwMax field */ + +#define WMM_AC_TO_TID(_ac) ( \ + ((_ac) == WMM_AC_VO) ? 6 : \ + ((_ac) == WMM_AC_VI) ? 5 : \ + ((_ac) == WMM_AC_BK) ? 1 : \ + 0) + +#define TID_TO_WMM_AC(_tid) ( \ + ((_tid) < 1) ? WMM_AC_BE : \ + ((_tid) < 3) ? WMM_AC_BK : \ + ((_tid) < 6) ? WMM_AC_VI : \ + WMM_AC_VO) +/* + * Management information element payloads. + */ + +enum { + IEEE80211_ELEMID_SSID = 0, + IEEE80211_ELEMID_RATES = 1, + IEEE80211_ELEMID_FHPARMS = 2, + IEEE80211_ELEMID_DSPARMS = 3, + IEEE80211_ELEMID_CFPARMS = 4, + IEEE80211_ELEMID_TIM = 5, + IEEE80211_ELEMID_IBSSPARMS = 6, + IEEE80211_ELEMID_COUNTRY = 7, + IEEE80211_ELEMID_CHALLENGE = 16, + /* 17-31 reserved for challenge text extension */ + IEEE80211_ELEMID_PWRCNSTR = 32, + IEEE80211_ELEMID_PWRCAP = 33, + IEEE80211_ELEMID_TPCREQ = 34, + IEEE80211_ELEMID_TPCREP = 35, + IEEE80211_ELEMID_SUPPCHAN = 36, + IEEE80211_ELEMID_CHANSWITCH = 37, + IEEE80211_ELEMID_MEASREQ = 38, + IEEE80211_ELEMID_MEASREP = 39, + IEEE80211_ELEMID_QUIET = 40, + IEEE80211_ELEMID_IBSSDFS = 41, + IEEE80211_ELEMID_ERP = 42, + IEEE80211_ELEMID_RSN = 48, + IEEE80211_ELEMID_XRATES = 50, +#ifdef WAPI_ENABLE + IEEE80211_ELEMID_WAPI = 68, +#endif + IEEE80211_ELEMID_TPC = 150, + IEEE80211_ELEMID_CCKM = 156, + IEEE80211_ELEMID_VENDOR = 221, /* vendor private */ +}; + +#define ATH_OUI 0x7f0300 /* Atheros OUI */ +#define ATH_OUI_TYPE 0x01 +#define ATH_OUI_SUBTYPE 0x01 +#define ATH_OUI_VERSION 0x00 + +#define WPA_OUI 0xf25000 +#define WPA_OUI_TYPE 0x01 +#define WPA_VERSION 1 /* current supported version */ + +#define WPA_CSE_NULL 0x00 +#define WPA_CSE_WEP40 0x01 +#define WPA_CSE_TKIP 0x02 +#define WPA_CSE_CCMP 0x04 +#define WPA_CSE_WEP104 0x05 + +#define WPA_ASE_NONE 0x00 +#define WPA_ASE_8021X_UNSPEC 0x01 +#define WPA_ASE_8021X_PSK 0x02 + +#define RSN_OUI 0xac0f00 +#define RSN_VERSION 1 /* current supported version */ + +#define RSN_CSE_NULL 0x00 +#define RSN_CSE_WEP40 0x01 +#define RSN_CSE_TKIP 0x02 +#define RSN_CSE_WRAP 0x03 +#define RSN_CSE_CCMP 0x04 +#define RSN_CSE_WEP104 0x05 + +#define RSN_ASE_NONE 0x00 +#define RSN_ASE_8021X_UNSPEC 0x01 +#define RSN_ASE_8021X_PSK 0x02 + +#define RSN_CAP_PREAUTH 0x01 + +#define WMM_OUI 0xf25000 +#define WMM_OUI_TYPE 0x02 +#define WMM_INFO_OUI_SUBTYPE 0x00 +#define WMM_PARAM_OUI_SUBTYPE 0x01 +#define WMM_VERSION 1 + +#ifdef PYXIS_ADHOC +#define PYXIS_OUI 0xf25000 /* Pyxis OUI 00-50-F2*/ +#define PYXIS_OUI_TYPE 0x06 +#endif + +/* WMM stream classes */ +#define WMM_NUM_AC 4 +#define WMM_AC_BE 0 /* best effort */ +#define WMM_AC_BK 1 /* background */ +#define WMM_AC_VI 2 /* video */ +#define WMM_AC_VO 3 /* voice */ + +/* TSPEC related */ +#define ACTION_CATEGORY_CODE_TSPEC 17 +#define ACTION_CODE_TSPEC_ADDTS 0 +#define ACTION_CODE_TSPEC_ADDTS_RESP 1 +#define ACTION_CODE_TSPEC_DELTS 2 + +typedef enum { + TSPEC_STATUS_CODE_ADMISSION_ACCEPTED = 0, + TSPEC_STATUS_CODE_ADDTS_INVALID_PARAMS = 0x1, + TSPEC_STATUS_CODE_ADDTS_REQUEST_REFUSED = 0x3, + TSPEC_STATUS_CODE_UNSPECIFIED_QOS_RELATED_FAILURE = 0xC8, + TSPEC_STATUS_CODE_REQUESTED_REFUSED_POLICY_CONFIGURATION = 0xC9, + TSPEC_STATUS_CODE_INSUFFCIENT_BANDWIDTH = 0xCA, + TSPEC_STATUS_CODE_INVALID_PARAMS = 0xCB, + TSPEC_STATUS_CODE_DELTS_SENT = 0x30, + TSPEC_STATUS_CODE_DELTS_RECV = 0x31, +} TSPEC_STATUS_CODE; + +#define TSPEC_TSID_MASK 0xF +#define TSPEC_TSID_S 1 + +/* + * WMM/802.11e Tspec Element + */ +typedef PREPACK struct wmm_tspec_ie_t { + A_UINT8 elementId; + A_UINT8 len; + A_UINT8 oui[3]; + A_UINT8 ouiType; + A_UINT8 ouiSubType; + A_UINT8 version; + A_UINT16 tsInfo_info; + A_UINT8 tsInfo_reserved; + A_UINT16 nominalMSDU; + A_UINT16 maxMSDU; + A_UINT32 minServiceInt; + A_UINT32 maxServiceInt; + A_UINT32 inactivityInt; + A_UINT32 suspensionInt; + A_UINT32 serviceStartTime; + A_UINT32 minDataRate; + A_UINT32 meanDataRate; + A_UINT32 peakDataRate; + A_UINT32 maxBurstSize; + A_UINT32 delayBound; + A_UINT32 minPhyRate; + A_UINT16 sba; + A_UINT16 mediumTime; +} POSTPACK WMM_TSPEC_IE; + + +/* + * BEACON management packets + * + * octet timestamp[8] + * octet beacon interval[2] + * octet capability information[2] + * information element + * octet elemid + * octet length + * octet information[length] + */ + +#define IEEE80211_BEACON_INTERVAL(beacon) \ + ((beacon)[8] | ((beacon)[9] << 8)) +#define IEEE80211_BEACON_CAPABILITY(beacon) \ + ((beacon)[10] | ((beacon)[11] << 8)) + +#define IEEE80211_CAPINFO_ESS 0x0001 +#define IEEE80211_CAPINFO_IBSS 0x0002 +#define IEEE80211_CAPINFO_CF_POLLABLE 0x0004 +#define IEEE80211_CAPINFO_CF_POLLREQ 0x0008 +#define IEEE80211_CAPINFO_PRIVACY 0x0010 +#define IEEE80211_CAPINFO_SHORT_PREAMBLE 0x0020 +#define IEEE80211_CAPINFO_PBCC 0x0040 +#define IEEE80211_CAPINFO_CHNL_AGILITY 0x0080 +/* bits 8-9 are reserved */ +#define IEEE80211_CAPINFO_SHORT_SLOTTIME 0x0400 +#define IEEE80211_CAPINFO_APSD 0x0800 +/* bit 12 is reserved */ +#define IEEE80211_CAPINFO_DSSSOFDM 0x2000 +/* bits 14-15 are reserved */ + +/* + * Authentication Modes + */ + +enum ieee80211_authmode { + IEEE80211_AUTH_NONE = 0, + IEEE80211_AUTH_OPEN = 1, + IEEE80211_AUTH_SHARED = 2, + IEEE80211_AUTH_8021X = 3, + IEEE80211_AUTH_AUTO = 4, /* auto-select/accept */ + /* NB: these are used only for ioctls */ + IEEE80211_AUTH_WPA = 5, /* WPA/RSN w/ 802.1x */ + IEEE80211_AUTH_WPA_PSK = 6, /* WPA/RSN w/ PSK */ + IEEE80211_AUTH_WPA_CCKM = 7, /* WPA/RSN IE w/ CCKM */ +}; + +#define IEEE80211_PS_MAX_QUEUE 50 /*Maximum no of buffers that can be queues for PS*/ + +#include "athendpack.h" + +#endif /* _NET80211_IEEE80211_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/ieee80211_ioctl.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ieee80211_ioctl.h --- linux-2.6.26/drivers/net/wireless/ath6k22/ieee80211_ioctl.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ieee80211_ioctl.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2004-2005 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + * + * $Id: //depot/sw/releases/olca2.2/host/os/linux/include/ieee80211_ioctl.h#1 $ + */ + +#ifndef _IEEE80211_IOCTL_H_ +#define _IEEE80211_IOCTL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Extracted from the MADWIFI net80211/ieee80211_ioctl.h + */ + +/* + * WPA/RSN get/set key request. Specify the key/cipher + * type and whether the key is to be used for sending and/or + * receiving. The key index should be set only when working + * with global keys (use IEEE80211_KEYIX_NONE for ``no index''). + * Otherwise a unicast/pairwise key is specified by the bssid + * (on a station) or mac address (on an ap). They key length + * must include any MIC key data; otherwise it should be no + more than IEEE80211_KEYBUF_SIZE. + */ +struct ieee80211req_key { + u_int8_t ik_type; /* key/cipher type */ + u_int8_t ik_pad; + u_int16_t ik_keyix; /* key index */ + u_int8_t ik_keylen; /* key length in bytes */ + u_int8_t ik_flags; +#define IEEE80211_KEY_XMIT 0x01 +#define IEEE80211_KEY_RECV 0x02 +#define IEEE80211_KEY_DEFAULT 0x80 /* default xmit key */ + u_int8_t ik_macaddr[IEEE80211_ADDR_LEN]; + u_int64_t ik_keyrsc; /* key receive sequence counter */ + u_int64_t ik_keytsc; /* key transmit sequence counter */ + u_int8_t ik_keydata[IEEE80211_KEYBUF_SIZE+IEEE80211_MICBUF_SIZE]; +}; +/* + * Delete a key either by index or address. Set the index + * to IEEE80211_KEYIX_NONE when deleting a unicast key. + */ +struct ieee80211req_del_key { + u_int8_t idk_keyix; /* key index */ + u_int8_t idk_macaddr[IEEE80211_ADDR_LEN]; +}; +/* + * MLME state manipulation request. IEEE80211_MLME_ASSOC + * only makes sense when operating as a station. The other + * requests can be used when operating as a station or an + * ap (to effect a station). + */ +struct ieee80211req_mlme { + u_int8_t im_op; /* operation to perform */ +#define IEEE80211_MLME_ASSOC 1 /* associate station */ +#define IEEE80211_MLME_DISASSOC 2 /* disassociate station */ +#define IEEE80211_MLME_DEAUTH 3 /* deauthenticate station */ +#define IEEE80211_MLME_AUTHORIZE 4 /* authorize station */ +#define IEEE80211_MLME_UNAUTHORIZE 5 /* unauthorize station */ + u_int16_t im_reason; /* 802.11 reason code */ + u_int8_t im_macaddr[IEEE80211_ADDR_LEN]; +}; + +struct ieee80211req_addpmkid { + u_int8_t pi_bssid[IEEE80211_ADDR_LEN]; + u_int8_t pi_enable; + u_int8_t pi_pmkid[16]; +}; + +#define AUTH_ALG_OPEN_SYSTEM 0x01 +#define AUTH_ALG_SHARED_KEY 0x02 +#define AUTH_ALG_LEAP 0x04 + +struct ieee80211req_authalg { + u_int8_t auth_alg; +}; + +/* + * Request to add an IE to a Management Frame + */ +enum{ + IEEE80211_APPIE_FRAME_BEACON = 0, + IEEE80211_APPIE_FRAME_PROBE_REQ = 1, + IEEE80211_APPIE_FRAME_PROBE_RESP = 2, + IEEE80211_APPIE_FRAME_ASSOC_REQ = 3, + IEEE80211_APPIE_FRAME_ASSOC_RESP = 4, + IEEE80211_APPIE_NUM_OF_FRAME = 5 +}; + +/* + * The Maximum length of the IE that can be added to a Management frame + */ +#define IEEE80211_APPIE_FRAME_MAX_LEN 200 + +struct ieee80211req_getset_appiebuf { + u_int32_t app_frmtype; /* management frame type for which buffer is added */ + u_int32_t app_buflen; /*application supplied buffer length */ + u_int8_t app_buf[]; +}; + +/* + * The following definitions are used by an application to set filter + * for receiving management frames + */ +enum { + IEEE80211_FILTER_TYPE_BEACON = 0x1, + IEEE80211_FILTER_TYPE_PROBE_REQ = 0x2, + IEEE80211_FILTER_TYPE_PROBE_RESP = 0x4, + IEEE80211_FILTER_TYPE_ASSOC_REQ = 0x8, + IEEE80211_FILTER_TYPE_ASSOC_RESP = 0x10, + IEEE80211_FILTER_TYPE_AUTH = 0x20, + IEEE80211_FILTER_TYPE_DEAUTH = 0x40, + IEEE80211_FILTER_TYPE_DISASSOC = 0x80, + IEEE80211_FILTER_TYPE_ALL = 0xFF /* used to check the valid filter bits */ +}; + +struct ieee80211req_set_filter { + u_int32_t app_filterype; /* management frame filter type */ +}; + +enum { + IEEE80211_PARAM_AUTHMODE = 3, /* Authentication Mode */ + IEEE80211_PARAM_MCASTCIPHER = 5, + IEEE80211_PARAM_MCASTKEYLEN = 6, /* multicast key length */ + IEEE80211_PARAM_UCASTCIPHER = 8, + IEEE80211_PARAM_UCASTKEYLEN = 9, /* unicast key length */ + IEEE80211_PARAM_WPA = 10, /* WPA mode (0,1,2) */ + IEEE80211_PARAM_ROAMING = 12, /* roaming mode */ + IEEE80211_PARAM_PRIVACY = 13, /* privacy invoked */ + IEEE80211_PARAM_COUNTERMEASURES = 14, /* WPA/TKIP countermeasures */ + IEEE80211_PARAM_DROPUNENCRYPTED = 15, /* discard unencrypted frames */ +}; + +/* + * Values for IEEE80211_PARAM_WPA + */ +#define WPA_MODE_WPA1 1 +#define WPA_MODE_WPA2 2 +#define WPA_MODE_AUTO 3 +#define WPA_MODE_NONE 4 + +struct ieee80211req_wpaie { + u_int8_t wpa_macaddr[IEEE80211_ADDR_LEN]; + u_int8_t wpa_ie[IEEE80211_MAX_IE]; + u_int8_t rsn_ie[IEEE80211_MAX_IE]; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* _IEEE80211_IOCTL_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/ieee80211_node.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ieee80211_node.h --- linux-2.6.26/drivers/net/wireless/ath6k22/ieee80211_node.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ieee80211_node.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,85 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _IEEE80211_NODE_H_ +#define _IEEE80211_NODE_H_ + +/* + * Node locking definitions. + */ +#define IEEE80211_NODE_LOCK_INIT(_nt) A_MUTEX_INIT(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_LOCK_DESTROY(_nt) if (A_IS_MUTEX_VALID(&(_nt)->nt_nodelock)) { \ + A_MUTEX_DELETE(&(_nt)->nt_nodelock); } + +#define IEEE80211_NODE_LOCK(_nt) A_MUTEX_LOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_UNLOCK(_nt) A_MUTEX_UNLOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_LOCK_BH(_nt) A_MUTEX_LOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_UNLOCK_BH(_nt) A_MUTEX_UNLOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_LOCK_ASSERT(_nt) + +/* + * Node reference counting definitions. + * + * ieee80211_node_initref initialize the reference count to 1 + * ieee80211_node_incref add a reference + * ieee80211_node_decref remove a reference + * ieee80211_node_dectestref remove a reference and return 1 if this + * is the last reference, otherwise 0 + * ieee80211_node_refcnt reference count for printing (only) + */ +#define ieee80211_node_initref(_ni) ((_ni)->ni_refcnt = 1) +#define ieee80211_node_incref(_ni) ((_ni)->ni_refcnt++) +#define ieee80211_node_decref(_ni) ((_ni)->ni_refcnt--) +#define ieee80211_node_dectestref(_ni) (((_ni)->ni_refcnt--) == 1) +#define ieee80211_node_refcnt(_ni) ((_ni)->ni_refcnt) + +#define IEEE80211_NODE_HASHSIZE 32 +/* simple hash is enough for variation of macaddr */ +#define IEEE80211_NODE_HASH(addr) \ + (((const A_UINT8 *)(addr))[IEEE80211_ADDR_LEN - 1] % \ + IEEE80211_NODE_HASHSIZE) + +/* + * Table of ieee80211_node instances. Each ieee80211com + * has at least one for holding the scan candidates. + * When operating as an access point or in ibss mode there + * is a second table for associated stations or neighbors. + */ +struct ieee80211_node_table { + void *nt_wmip; /* back reference */ + A_MUTEX_T nt_nodelock; /* on node table */ + struct bss *nt_node_first; /* information of all nodes */ + struct bss *nt_node_last; /* information of all nodes */ + struct bss *nt_hash[IEEE80211_NODE_HASHSIZE]; + const char *nt_name; /* for debugging */ + A_UINT32 nt_scangen; /* gen# for timeout scan */ + A_TIMER nt_inact_timer; + A_UINT8 isTimerArmed; /* is the node timer armed */ + A_UINT32 nt_nodeAge; /* node aging time */ +#ifdef OS_ROAM_MANAGEMENT + A_UINT32 nt_si_gen; /* gen# for scan indication*/ +#endif +}; + +#define WLAN_NODE_INACT_TIMEOUT_MSEC 120000 + +#endif /* _IEEE80211_NODE_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/ini_dset.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ini_dset.h --- linux-2.6.26/drivers/net/wireless/ath6k22/ini_dset.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ini_dset.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,90 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _INI_DSET_H_ +#define _INI_DSET_H_ + +/* + * Each of these represents a WHAL INI table, which consists + * of an "address column" followed by 1 or more "value columns". + * + * Software uses the base WHAL_INI_DATA_ID+column to access a + * DataSet that holds a particular column of data. + */ +typedef enum { +#if defined(AR6002_REV4) || defined(AR6003) +#ifdef FPGA + WHAL_INI_DATA_ID_NULL =0, + WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3,4,5 */ + WHAL_INI_DATA_ID_COMMON =6, /* 7 */ + WHAL_INI_DATA_ID_BB_RFGAIN =8, /* 9,10 */ +/* Only one LNA for FPGA */ +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 WHAL_INI_DATA_ID_BB_RFGAIN + WHAL_INI_DATA_ID_ANALOG_BANK0 =11, /* 12 */ + WHAL_INI_DATA_ID_ANALOG_BANK1 =13, /* 14 */ + WHAL_INI_DATA_ID_ANALOG_BANK2 =15, /* 16 */ + WHAL_INI_DATA_ID_ANALOG_BANK3 =17, /* 18, 19 */ + WHAL_INI_DATA_ID_ANALOG_BANK6 =20, /* 21,22 */ + WHAL_INI_DATA_ID_ANALOG_BANK7 =23, /* 24 */ +#else + WHAL_INI_DATA_ID_NULL =0, + WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3,4,5 */ + WHAL_INI_DATA_ID_COMMON =6, /* 7 */ + WHAL_INI_DATA_ID_BB_RFGAIN =8, /* 9,10 */ +/* Add these definitions for compatability */ +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 WHAL_INI_DATA_ID_BB_RFGAIN + WHAL_INI_DATA_ID_ANALOG_COMMON =11, /* 12 */ + WHAL_INI_DATA_ID_ANALOG_MODE_SPECIFIC=13, /* 14,15 */ + WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17,18 */ + WHAL_INI_DATA_ID_MODE_OVERRIDES =19, /* 20,21 */ + WHAL_INI_DATA_ID_COMMON_OVERRIDES =22, /* 23 */ + WHAL_INI_DATA_ID_ANALOG_OVERRIDES =24, /* 25,26 */ +#endif +#else + WHAL_INI_DATA_ID_NULL =0, + WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3 */ + WHAL_INI_DATA_ID_COMMON =4, /* 5 */ + WHAL_INI_DATA_ID_BB_RFGAIN =6, /* 7,8 */ +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN + WHAL_INI_DATA_ID_ANALOG_BANK1 =9, /* 10 */ + WHAL_INI_DATA_ID_ANALOG_BANK2 =11, /* 12 */ + WHAL_INI_DATA_ID_ANALOG_BANK3 =13, /* 14, 15 */ + WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17, 18 */ + WHAL_INI_DATA_ID_ANALOG_BANK7 =19, /* 20 */ + WHAL_INI_DATA_ID_MODE_OVERRIDES =21, /* 22,23 */ + WHAL_INI_DATA_ID_COMMON_OVERRIDES =24, /* 25 */ + WHAL_INI_DATA_ID_ANALOG_OVERRIDES =26, /* 27,28 */ + WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 =29, /* 30,31 */ +#endif + WHAL_INI_DATA_ID_MAX =31 +} WHAL_INI_DATA_ID; + +typedef PREPACK struct { + A_UINT16 freqIndex; // 1 - A mode 2 - B or G mode 0 - common + A_UINT16 offset; + A_UINT32 newValue; +} POSTPACK INI_DSET_REG_OVERRIDE; + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/ioctl.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ioctl.c --- linux-2.6.26/drivers/net/wireless/ath6k22/ioctl.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/ioctl.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,3466 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#include "ar6000_drv.h" +#include "ieee80211_ioctl.h" +#include "ar6kap_common.h" + +static A_UINT8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; +static A_UINT8 null_mac[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; +extern unsigned int wmitimeout; +extern A_WAITQUEUE_HEAD arEvent; +extern int tspecCompliance; +extern int bmienable; +extern int bypasswmi; + +static int +ar6000_ioctl_get_roam_tbl(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if(wmi_get_roam_tbl_cmd(ar->arWmi) != A_OK) { + return -EIO; + } + + return 0; +} + +static int +ar6000_ioctl_get_roam_data(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + /* currently assume only roam times are required */ + if(wmi_get_roam_data_cmd(ar->arWmi, ROAM_DATA_TIME) != A_OK) { + return -EIO; + } + + + return 0; +} + +static int +ar6000_ioctl_set_roam_ctrl(struct net_device *dev, char *userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_ROAM_CTRL_CMD cmd; + A_UINT8 size = sizeof(cmd); + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if (cmd.roamCtrlType == WMI_SET_HOST_BIAS) { + if (cmd.info.bssBiasInfo.numBss > 1) { + size += (cmd.info.bssBiasInfo.numBss - 1) * sizeof(WMI_BSS_BIAS); + } + } + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if(wmi_set_roam_ctrl_cmd(ar->arWmi, &cmd, size) != A_OK) { + return -EIO; + } + + return 0; +} + +static int +ar6000_ioctl_set_powersave_timers(struct net_device *dev, char *userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_POWERSAVE_TIMERS_POLICY_CMD cmd; + A_UINT8 size = sizeof(cmd); + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if(wmi_set_powersave_timers_cmd(ar->arWmi, &cmd, size) != A_OK) { + return -EIO; + } + + return 0; +} + +static int +ar6000_ioctl_set_wmm(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_WMM_CMD cmd; + A_STATUS ret; + + if ((dev->flags & IFF_UP) != IFF_UP) { + return -EIO; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1), + sizeof(cmd))) + { + return -EFAULT; + } + + if (cmd.status == WMI_WMM_ENABLED) { + ar->arWmmEnabled = TRUE; + } else { + ar->arWmmEnabled = FALSE; + } + + ret = wmi_set_wmm_cmd(ar->arWmi, cmd.status); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_set_txop(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_WMM_TXOP_CMD cmd; + A_STATUS ret; + + if ((dev->flags & IFF_UP) != IFF_UP) { + return -EIO; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1), + sizeof(cmd))) + { + return -EFAULT; + } + + ret = wmi_set_wmm_txop(ar->arWmi, cmd.txopEnable); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_get_rd(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_STATUS ret = 0; + + if ((dev->flags & IFF_UP) != IFF_UP || ar->arWmiReady == FALSE) { + return -EIO; + } + + if(copy_to_user((char *)((unsigned int*)rq->ifr_data + 1), + &ar->arRegCode, sizeof(ar->arRegCode))) + ret = -EFAULT; + + return ret; +} + +static int +ar6000_ioctl_set_country(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_AP_SET_COUNTRY_CMD cmd; + A_STATUS ret; + + if ((dev->flags & IFF_UP) != IFF_UP) { + return -EIO; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1), + sizeof(cmd))) + { + return -EFAULT; + } + + ar->ap_profile_flag = 1; /* There is a change in profile */ + + ret = wmi_set_country(ar->arWmi, cmd.countryCode); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + + +/* Get power mode command */ +static int +ar6000_ioctl_get_power_mode(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_POWER_MODE_CMD power_mode; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + power_mode.powerMode = wmi_get_power_mode_cmd(ar->arWmi); + if (copy_to_user(rq->ifr_data, &power_mode, sizeof(WMI_POWER_MODE_CMD))) { + ret = -EFAULT; + } + + return ret; +} + + +static int +ar6000_ioctl_set_channelParams(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_CHANNEL_PARAMS_CMD cmd, *cmdp; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if( (ar->arNextMode == AP_NETWORK) && (cmd.numChannels || cmd.scanParam) ) { + A_PRINTF("ERROR: Only wmode is allowed in AP mode\n"); + return -EIO; + } + + if (cmd.numChannels > 1) { + cmdp = A_MALLOC(130); + if (copy_from_user(cmdp, rq->ifr_data, + sizeof (*cmdp) + + ((cmd.numChannels - 1) * sizeof(A_UINT16)))) + { + kfree(cmdp); + return -EFAULT; + } + } else { + cmdp = &cmd; + } + + if ((ar->arPhyCapability == WMI_11G_CAPABILITY) && + ((cmdp->phyMode == WMI_11A_MODE) || (cmdp->phyMode == WMI_11AG_MODE))) + { + ret = -EINVAL; + } + + if (!ret && + (wmi_set_channelParams_cmd(ar->arWmi, cmdp->scanParam, cmdp->phyMode, + cmdp->numChannels, cmdp->channelList) + != A_OK)) + { + ret = -EIO; + } + + if (cmd.numChannels > 1) { + kfree(cmdp); + } + + /* Set the profile change flag to allow a commit cmd */ + ar->ap_profile_flag = 1; + + return ret; +} + + +static int +ar6000_ioctl_set_snr_threshold(struct net_device *dev, struct ifreq *rq) +{ + + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SNR_THRESHOLD_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if( wmi_set_snr_threshold_params(ar->arWmi, &cmd) != A_OK ) { + ret = -EIO; + } + + return ret; +} + +static int +ar6000_ioctl_set_rssi_threshold(struct net_device *dev, struct ifreq *rq) +{ +#define SWAP_THOLD(thold1, thold2) do { \ + USER_RSSI_THOLD tmpThold; \ + tmpThold.tag = thold1.tag; \ + tmpThold.rssi = thold1.rssi; \ + thold1.tag = thold2.tag; \ + thold1.rssi = thold2.rssi; \ + thold2.tag = tmpThold.tag; \ + thold2.rssi = tmpThold.rssi; \ +} while (0) + + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_RSSI_THRESHOLD_PARAMS_CMD cmd; + USER_RSSI_PARAMS rssiParams; + A_INT32 i, j; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user((char *)&rssiParams, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(USER_RSSI_PARAMS))) { + return -EFAULT; + } + cmd.weight = rssiParams.weight; + cmd.pollTime = rssiParams.pollTime; + + A_MEMCPY(ar->rssi_map, &rssiParams.tholds, sizeof(ar->rssi_map)); + /* + * only 6 elements, so use bubble sorting, in ascending order + */ + for (i = 5; i > 0; i--) { + for (j = 0; j < i; j++) { /* above tholds */ + if (ar->rssi_map[j+1].rssi < ar->rssi_map[j].rssi) { + SWAP_THOLD(ar->rssi_map[j+1], ar->rssi_map[j]); + } else if (ar->rssi_map[j+1].rssi == ar->rssi_map[j].rssi) { + return EFAULT; + } + } + } + for (i = 11; i > 6; i--) { + for (j = 6; j < i; j++) { /* below tholds */ + if (ar->rssi_map[j+1].rssi < ar->rssi_map[j].rssi) { + SWAP_THOLD(ar->rssi_map[j+1], ar->rssi_map[j]); + } else if (ar->rssi_map[j+1].rssi == ar->rssi_map[j].rssi) { + return EFAULT; + } + } + } + +#ifdef DEBUG + for (i = 0; i < 12; i++) { + AR_DEBUG2_PRINTF("thold[%d].tag: %d, thold[%d].rssi: %d \n", + i, ar->rssi_map[i].tag, i, ar->rssi_map[i].rssi); + } +#endif + cmd.thresholdAbove1_Val = ar->rssi_map[0].rssi; + cmd.thresholdAbove2_Val = ar->rssi_map[1].rssi; + cmd.thresholdAbove3_Val = ar->rssi_map[2].rssi; + cmd.thresholdAbove4_Val = ar->rssi_map[3].rssi; + cmd.thresholdAbove5_Val = ar->rssi_map[4].rssi; + cmd.thresholdAbove6_Val = ar->rssi_map[5].rssi; + cmd.thresholdBelow1_Val = ar->rssi_map[6].rssi; + cmd.thresholdBelow2_Val = ar->rssi_map[7].rssi; + cmd.thresholdBelow3_Val = ar->rssi_map[8].rssi; + cmd.thresholdBelow4_Val = ar->rssi_map[9].rssi; + cmd.thresholdBelow5_Val = ar->rssi_map[10].rssi; + cmd.thresholdBelow6_Val = ar->rssi_map[11].rssi; + + if( wmi_set_rssi_threshold_params(ar->arWmi, &cmd) != A_OK ) { + ret = -EIO; + } + + return ret; +} + +static int +ar6000_ioctl_set_lq_threshold(struct net_device *dev, struct ifreq *rq) +{ + + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_LQ_THRESHOLD_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(cmd))) { + return -EFAULT; + } + + if( wmi_set_lq_threshold_params(ar->arWmi, &cmd) != A_OK ) { + ret = -EIO; + } + + return ret; +} + + +static int +ar6000_ioctl_set_probedSsid(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_PROBED_SSID_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_probedSsid_cmd(ar->arWmi, cmd.entryIndex, cmd.flag, cmd.ssidLength, + cmd.ssid) != A_OK) + { + ret = -EIO; + } + + return ret; +} + +static int +ar6000_ioctl_set_badAp(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_ADD_BAD_AP_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (cmd.badApIndex > WMI_MAX_BAD_AP_INDEX) { + return -EIO; + } + + if (A_MEMCMP(cmd.bssid, null_mac, AR6000_ETH_ADDR_LEN) == 0) { + /* + * This is a delete badAP. + */ + if (wmi_deleteBadAp_cmd(ar->arWmi, cmd.badApIndex) != A_OK) { + ret = -EIO; + } + } else { + if (wmi_addBadAp_cmd(ar->arWmi, cmd.badApIndex, cmd.bssid) != A_OK) { + ret = -EIO; + } + } + + return ret; +} + +static int +ar6000_ioctl_create_qos(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_CREATE_PSTREAM_CMD cmd; + A_STATUS ret; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + ret = wmi_verify_tspec_params(&cmd, tspecCompliance); + if (ret == A_OK) + ret = wmi_create_pstream_cmd(ar->arWmi, &cmd); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_delete_qos(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_DELETE_PSTREAM_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + ret = wmi_delete_pstream_cmd(ar->arWmi, cmd.trafficClass, cmd.tsid); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_get_qos_queue(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + struct ar6000_queuereq qreq; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if( copy_from_user(&qreq, rq->ifr_data, + sizeof(struct ar6000_queuereq))) + return -EFAULT; + + qreq.activeTsids = wmi_get_mapped_qos_queue(ar->arWmi, qreq.trafficClass); + + if (copy_to_user(rq->ifr_data, &qreq, + sizeof(struct ar6000_queuereq))) + { + ret = -EFAULT; + } + + return ret; +} + +#ifdef CONFIG_HOST_TCMD_SUPPORT +static A_STATUS +ar6000_ioctl_tcmd_get_rx_report(struct net_device *dev, + struct ifreq *rq, A_UINT8 *data, A_UINT32 len) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_UINT32 buf[4]; + int ret = 0; + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + ar->tcmdRxReport = 0; + if (wmi_test_cmd(ar->arWmi, data, len) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->tcmdRxReport != 0, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + + buf[0] = ar->tcmdRxTotalPkt; + buf[1] = ar->tcmdRxRssi; + buf[2] = ar->tcmdRxcrcErrPkt; + buf[3] = ar->tcmdRxsecErrPkt; + if (!ret && copy_to_user(rq->ifr_data, buf, sizeof(buf))) { + ret = -EFAULT; + } + + up(&ar->arSem); + + return ret; +} + +void +ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + TCMD_CONT_RX * rx_rep = (TCMD_CONT_RX *)results; + + ar->tcmdRxTotalPkt = rx_rep->u.report.totalPkt; + ar->tcmdRxRssi = rx_rep->u.report.rssiInDBm; + ar->tcmdRxcrcErrPkt = rx_rep->u.report.crcErrPkt; + ar->tcmdRxsecErrPkt = rx_rep->u.report.secErrPkt; + ar->tcmdRxReport = 1; + + wake_up(&arEvent); +} +#endif /* CONFIG_HOST_TCMD_SUPPORT*/ + +static int +ar6000_ioctl_set_error_report_bitmask(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_TARGET_ERROR_REPORT_BITMASK cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + ret = wmi_set_error_report_bitmask(ar->arWmi, cmd.bitmask); + + return (ret==0 ? ret : -EINVAL); +} + +static int +ar6000_clear_target_stats(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + TARGET_STATS *pStats = &ar->arTargetStats; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + AR6000_SPIN_LOCK(&ar->arLock, 0); + A_MEMZERO(pStats, sizeof(TARGET_STATS)); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + return ret; +} + +static int +ar6000_ioctl_get_target_stats(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + TARGET_STATS_CMD cmd; + TARGET_STATS *pStats = &ar->arTargetStats; + int ret = 0; + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + ar->statsUpdatePending = TRUE; + + if(wmi_get_stats_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + + if (!ret && copy_to_user(rq->ifr_data, pStats, sizeof(*pStats))) { + ret = -EFAULT; + } + + if (cmd.clearStats == 1) { + ret = ar6000_clear_target_stats(dev); + } + + up(&ar->arSem); + + return ret; +} + +static int +ar6000_ioctl_set_access_params(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_ACCESS_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_access_params_cmd(ar->arWmi, cmd.txop, cmd.eCWmin, cmd.eCWmax, + cmd.aifsn) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +static int +ar6000_ioctl_set_disconnect_timeout(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_DISC_TIMEOUT_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_disctimeout_cmd(ar->arWmi, cmd.disconnectTimeout) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +static int +ar6000_xioctl_set_voice_pkt_size(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_VOICE_PKT_SIZE_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_voice_pkt_size_cmd(ar->arWmi, cmd.voicePktSize) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + + return (ret); +} + +static int +ar6000_xioctl_set_max_sp_len(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_MAX_SP_LEN_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_max_sp_len_cmd(ar->arWmi, cmd.maxSPLen) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + + +static int +ar6000_xioctl_set_bt_status_cmd(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_BT_STATUS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_bt_status_cmd(ar->arWmi, cmd.streamType, cmd.status) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +static int +ar6000_xioctl_set_bt_params_cmd(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_BT_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_bt_params_cmd(ar->arWmi, &cmd) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +#ifdef CONFIG_HOST_GPIO_SUPPORT +struct ar6000_gpio_intr_wait_cmd_s gpio_intr_results; +/* gpio_reg_results and gpio_data_available are protected by arSem */ +static struct ar6000_gpio_register_cmd_s gpio_reg_results; +static A_BOOL gpio_data_available; /* Requested GPIO data available */ +static A_BOOL gpio_intr_available; /* GPIO interrupt info available */ +static A_BOOL gpio_ack_received; /* GPIO ack was received */ + +/* Host-side initialization for General Purpose I/O support */ +void ar6000_gpio_init(void) +{ + gpio_intr_available = FALSE; + gpio_data_available = FALSE; + gpio_ack_received = FALSE; +} + +/* + * Called when a GPIO interrupt is received from the Target. + * intr_values shows which GPIO pins have interrupted. + * input_values shows a recent value of GPIO pins. + */ +void +ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values) +{ + gpio_intr_results.intr_mask = intr_mask; + gpio_intr_results.input_values = input_values; + *((volatile A_BOOL *)&gpio_intr_available) = TRUE; + wake_up(&arEvent); +} + +/* + * This is called when a response is received from the Target + * for a previous or ar6000_gpio_input_get or ar6000_gpio_register_get + * call. + */ +void +ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value) +{ + gpio_reg_results.gpioreg_id = reg_id; + gpio_reg_results.value = value; + *((volatile A_BOOL *)&gpio_data_available) = TRUE; + wake_up(&arEvent); +} + +/* + * This is called when an acknowledgement is received from the Target + * for a previous or ar6000_gpio_output_set or ar6000_gpio_register_set + * call. + */ +void +ar6000_gpio_ack_rx(void) +{ + gpio_ack_received = TRUE; + wake_up(&arEvent); +} + +A_STATUS +ar6000_gpio_output_set(struct net_device *dev, + A_UINT32 set_mask, + A_UINT32 clear_mask, + A_UINT32 enable_mask, + A_UINT32 disable_mask) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + gpio_ack_received = FALSE; + return wmi_gpio_output_set(ar->arWmi, + set_mask, clear_mask, enable_mask, disable_mask); +} + +static A_STATUS +ar6000_gpio_input_get(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + *((volatile A_BOOL *)&gpio_data_available) = FALSE; + return wmi_gpio_input_get(ar->arWmi); +} + +static A_STATUS +ar6000_gpio_register_set(struct net_device *dev, + A_UINT32 gpioreg_id, + A_UINT32 value) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + gpio_ack_received = FALSE; + return wmi_gpio_register_set(ar->arWmi, gpioreg_id, value); +} + +static A_STATUS +ar6000_gpio_register_get(struct net_device *dev, + A_UINT32 gpioreg_id) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + *((volatile A_BOOL *)&gpio_data_available) = FALSE; + return wmi_gpio_register_get(ar->arWmi, gpioreg_id); +} + +static A_STATUS +ar6000_gpio_intr_ack(struct net_device *dev, + A_UINT32 ack_mask) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + gpio_intr_available = FALSE; + return wmi_gpio_intr_ack(ar->arWmi, ack_mask); +} +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +static struct prof_count_s prof_count_results; +static A_BOOL prof_count_available; /* Requested GPIO data available */ + +static A_STATUS +prof_count_get(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + *((volatile A_BOOL *)&prof_count_available) = FALSE; + return wmi_prof_count_get_cmd(ar->arWmi); +} + +/* + * This is called when a response is received from the Target + * for a previous prof_count_get call. + */ +void +prof_count_rx(A_UINT32 addr, A_UINT32 count) +{ + prof_count_results.addr = addr; + prof_count_results.count = count; + *((volatile A_BOOL *)&prof_count_available) = TRUE; + wake_up(&arEvent); +} +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + +int +ar6000_ioctl_setparam(AR_SOFTC_T *ar, int param, int value) +{ + A_BOOL profChanged = FALSE; + int ret=0; + + switch (param) { + case IEEE80211_PARAM_WPA: + switch (value) { + case WPA_MODE_WPA1: + ar->arAuthMode = WPA_AUTH; + profChanged = TRUE; + break; + case WPA_MODE_WPA2: + ar->arAuthMode = WPA2_AUTH; + profChanged = TRUE; + break; + case WPA_MODE_NONE: + ar->arAuthMode = NONE_AUTH; + profChanged = TRUE; + break; + } + break; + case IEEE80211_PARAM_AUTHMODE: + switch(value) { + case IEEE80211_AUTH_WPA_PSK: + if (WPA_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA_PSK_AUTH; + profChanged = TRUE; + } else if (WPA2_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA2_PSK_AUTH; + profChanged = TRUE; + } else { + AR_DEBUG_PRINTF("Error - Setting PSK "\ + "mode when WPA param was set to %d\n", + ar->arAuthMode); + ret = -EIO; + } + break; + case IEEE80211_AUTH_WPA_CCKM: + if (WPA2_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA2_AUTH_CCKM; + } else { + ar->arAuthMode = WPA_AUTH_CCKM; + } + break; + default: + break; + } + break; + case IEEE80211_PARAM_UCASTCIPHER: + switch (value) { + case IEEE80211_CIPHER_AES_CCM: + ar->arPairwiseCrypto = AES_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_TKIP: + ar->arPairwiseCrypto = TKIP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_WEP: + ar->arPairwiseCrypto = WEP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_NONE: + ar->arPairwiseCrypto = NONE_CRYPT; + profChanged = TRUE; + break; + } + break; + case IEEE80211_PARAM_UCASTKEYLEN: + if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) { + ret = -EIO; + } else { + ar->arPairwiseCryptoLen = value; + } + break; + case IEEE80211_PARAM_MCASTCIPHER: + switch (value) { + case IEEE80211_CIPHER_AES_CCM: + ar->arGroupCrypto = AES_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_TKIP: + ar->arGroupCrypto = TKIP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_WEP: + ar->arGroupCrypto = WEP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_NONE: + ar->arGroupCrypto = NONE_CRYPT; + profChanged = TRUE; + break; + } + break; + case IEEE80211_PARAM_MCASTKEYLEN: + if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) { + ret = -EIO; + } else { + ar->arGroupCryptoLen = value; + } + break; + case IEEE80211_PARAM_COUNTERMEASURES: + if (ar->arWmiReady == FALSE) { + return -EIO; + } + wmi_set_tkip_countermeasures_cmd(ar->arWmi, value); + break; + default: + break; + } + if ((ar->arNextMode != AP_NETWORK) && (profChanged == TRUE)) { + /* + * profile has changed. Erase ssid to signal change + */ + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + } + ar->ap_profile_flag = 1; /* There is a change in profile */ + + return ret; +} + +int +ar6000_ioctl_setkey(AR_SOFTC_T *ar, struct ieee80211req_key *ik) +{ + KEY_USAGE keyUsage; + A_STATUS status; + CRYPTO_TYPE keyType = NONE_CRYPT; + A_UINT8 null_addr[]={0x0,0x0,0x0,0x0,0x0,0x0}; + A_UINT8 bcast_addr[]={0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}; + +#ifdef USER_KEYS + ar->user_saved_keys.keyOk = FALSE; +#endif + if ( (0 == memcmp(ik->ik_macaddr, null_addr, IEEE80211_ADDR_LEN)) || + (0 == memcmp(ik->ik_macaddr, bcast_addr, IEEE80211_ADDR_LEN)) ) { + keyUsage = GROUP_USAGE; + if(ar->arNextMode == AP_NETWORK) { + A_MEMCPY(&ar->ap_mode_bkey, ik, + sizeof(struct ieee80211req_key)); + } +#ifdef USER_KEYS + A_MEMCPY(&ar->user_saved_keys.bcast_ik, ik, + sizeof(struct ieee80211req_key)); +#endif + } else { + keyUsage = PAIRWISE_USAGE; +#ifdef USER_KEYS + A_MEMCPY(&ar->user_saved_keys.ucast_ik, ik, + sizeof(struct ieee80211req_key)); +#endif + } + + switch (ik->ik_type) { + case IEEE80211_CIPHER_WEP: + keyType = WEP_CRYPT; + break; + case IEEE80211_CIPHER_TKIP: + keyType = TKIP_CRYPT; + break; + case IEEE80211_CIPHER_AES_CCM: + keyType = AES_CRYPT; + break; + default: + break; + } + if ((ik->ik_type == IEEE80211_CIPHER_WEP) && (ik->ik_flags & IEEE80211_KEY_XMIT)) + { + keyUsage |= TX_USAGE; + } +#ifdef USER_KEYS + ar->user_saved_keys.keyType = keyType; +#endif + if (IEEE80211_CIPHER_CCKM_KRK != ik->ik_type) { + if (NONE_CRYPT == keyType) { + return -EIO; + } + + if (((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)) && + (GROUP_USAGE == keyUsage)) + { + A_UNTIMEOUT(&ar->disconnect_timer); + } + + status = wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, keyUsage, + ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc, + ik->ik_keydata, KEY_OP_INIT_VAL, ik->ik_macaddr, + SYNC_BOTH_WMIFLAG); + + if (status != A_OK) { + return -EIO; + } + } else { + status = wmi_add_krk_cmd(ar->arWmi, ik->ik_keydata); + } + +#ifdef USER_KEYS + ar->user_saved_keys.keyOk = TRUE; +#endif + + return 0; +} + +int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + HIF_DEVICE *hifDevice = ar->arHifDevice; + int ret, param; + unsigned int address = 0; + unsigned int length = 0; + unsigned char *buffer; + char *userdata; + A_UINT32 connectCtrlFlags; + + + static WMI_SCAN_PARAMS_CMD scParams = {0, 0, 0, 0, 0, + WMI_SHORTSCANRATIO_DEFAULT, + DEFAULT_SCAN_CTRL_FLAGS, + 0}; + WMI_SET_AKMP_PARAMS_CMD akmpParams; + WMI_SET_PMKID_LIST_CMD pmkidInfo; + + if (cmd == AR6000_IOCTL_EXTENDED) { + /* + * This allows for many more wireless ioctls than would otherwise + * be available. Applications embed the actual ioctl command in + * the first word of the parameter block, and use the command + * AR6000_IOCTL_EXTENDED_CMD on the ioctl call. + */ + get_user(cmd, (int *)rq->ifr_data); + userdata = (char *)(((unsigned int *)rq->ifr_data)+1); + + if(is_xioctl_allowed(ar->arNextMode, cmd) != A_OK) { + A_PRINTF("xioctl: cmd=%d not allowed in this mode\n",cmd); + return -EOPNOTSUPP; + } + } else { + A_STATUS ret = is_iwioctl_allowed(ar->arNextMode, cmd); + if(ret == A_ENOTSUP) { + A_PRINTF("iwioctl: cmd=0x%x not allowed in this mode\n", cmd); + return -EOPNOTSUPP; + } else if (ret == A_ERROR) { + /* It is not our ioctl (out of range ioctl) */ + return -EOPNOTSUPP; + } + userdata = (char *)rq->ifr_data; + } + + if ((ar->arWlanState == WLAN_DISABLED) && + ((cmd != AR6000_XIOCTRL_WMI_SET_WLAN_STATE) && + (cmd != AR6000_XIOCTL_DIAG_READ) && + (cmd != AR6000_XIOCTL_DIAG_WRITE))) + { + return -EIO; + } + + ret = 0; + switch(cmd) + { + case IEEE80211_IOCTL_SETPARAM: + { + int param, value; + int *ptr = (int *)rq->ifr_ifru.ifru_newname; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + param = *ptr++; + value = *ptr; + ret = ar6000_ioctl_setparam(ar,param,value); + } + break; + } + case IEEE80211_IOCTL_SETKEY: + { + struct ieee80211req_key keydata; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&keydata, userdata, + sizeof(struct ieee80211req_key))) { + ret = -EFAULT; + } else { + ar6000_ioctl_setkey(ar, &keydata); + } + break; + } + case IEEE80211_IOCTL_DELKEY: + case IEEE80211_IOCTL_SETOPTIE: + { + //ret = -EIO; + break; + } + case IEEE80211_IOCTL_SETMLME: + { + struct ieee80211req_mlme mlme; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&mlme, userdata, + sizeof(struct ieee80211req_mlme))) { + ret = -EFAULT; + } else { + switch (mlme.im_op) { + case IEEE80211_MLME_AUTHORIZE: + A_PRINTF("setmlme AUTHORIZE %02X:%02X\n", + mlme.im_macaddr[4], mlme.im_macaddr[5]); + break; + case IEEE80211_MLME_UNAUTHORIZE: + A_PRINTF("setmlme UNAUTHORIZE %02X:%02X\n", + mlme.im_macaddr[4], mlme.im_macaddr[5]); + break; + case IEEE80211_MLME_DEAUTH: + A_PRINTF("setmlme DEAUTH %02X:%02X\n", + mlme.im_macaddr[4], mlme.im_macaddr[5]); + //remove_sta(ar, mlme.im_macaddr); + break; + case IEEE80211_MLME_DISASSOC: + A_PRINTF("setmlme DISASSOC %02X:%02X\n", + mlme.im_macaddr[4], mlme.im_macaddr[5]); + //remove_sta(ar, mlme.im_macaddr); + break; + default: + return 0; + } + + wmi_ap_set_mlme(ar->arWmi, mlme.im_op, mlme.im_macaddr, + mlme.im_reason); + } + break; + } + case IEEE80211_IOCTL_ADDPMKID: + { + struct ieee80211req_addpmkid req; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&req, userdata, sizeof(struct ieee80211req_addpmkid))) { + ret = -EFAULT; + } else { + A_STATUS status; + + AR_DEBUG_PRINTF("Add pmkid for %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x en=%d\n", + req.pi_bssid[0], req.pi_bssid[1], req.pi_bssid[2], + req.pi_bssid[3], req.pi_bssid[4], req.pi_bssid[5], + req.pi_enable); + + status = wmi_setPmkid_cmd(ar->arWmi, req.pi_bssid, req.pi_pmkid, + req.pi_enable); + + if (status != A_OK) { + return -EIO; + } + } + break; + } +#ifdef CONFIG_HOST_TCMD_SUPPORT + case AR6000_XIOCTL_TCMD_CONT_TX: + { + TCMD_CONT_TX txCmd; + + if (ar->tcmdPm == TCMD_PM_SLEEP) { + A_PRINTF("Can NOT send tx tcmd when target is asleep! \n"); + return -EFAULT; + } + + if(copy_from_user(&txCmd, userdata, sizeof(TCMD_CONT_TX))) + return -EFAULT; + wmi_test_cmd(ar->arWmi,(A_UINT8 *)&txCmd, sizeof(TCMD_CONT_TX)); + } + break; + case AR6000_XIOCTL_TCMD_CONT_RX: + { + TCMD_CONT_RX rxCmd; + + if (ar->tcmdPm == TCMD_PM_SLEEP) { + A_PRINTF("Can NOT send rx tcmd when target is asleep! \n"); + return -EFAULT; + } + if(copy_from_user(&rxCmd, userdata, sizeof(TCMD_CONT_RX))) + return -EFAULT; + switch(rxCmd.act) + { + case TCMD_CONT_RX_PROMIS: + case TCMD_CONT_RX_FILTER: + case TCMD_CONT_RX_SETMAC: + case TCMD_CONT_RX_SET_ANT_SWITCH_TABLE: + wmi_test_cmd(ar->arWmi,(A_UINT8 *)&rxCmd, + sizeof(TCMD_CONT_RX)); + break; + case TCMD_CONT_RX_REPORT: + ar6000_ioctl_tcmd_get_rx_report(dev, rq, + (A_UINT8 *)&rxCmd, sizeof(TCMD_CONT_RX)); + break; + default: + A_PRINTF("Unknown Cont Rx mode: %d\n",rxCmd.act); + return -EINVAL; + } + } + break; + case AR6000_XIOCTL_TCMD_PM: + { + TCMD_PM pmCmd; + + if(copy_from_user(&pmCmd, userdata, sizeof(TCMD_PM))) + return -EFAULT; + ar->tcmdPm = pmCmd.mode; + wmi_test_cmd(ar->arWmi, (A_UINT8*)&pmCmd, sizeof(TCMD_PM)); + } + break; +#endif /* CONFIG_HOST_TCMD_SUPPORT */ + + case AR6000_XIOCTL_BMI_DONE: + if(bmienable) + { + ret = ar6000_init(dev); + } + else + { + ret = BMIDone(hifDevice); + } + break; + + case AR6000_XIOCTL_BMI_READ_MEMORY: + get_user(address, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + AR_DEBUG_PRINTF("Read Memory (address: 0x%x, length: %d)\n", + address, length); + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + ret = BMIReadMemory(hifDevice, address, buffer, length); + if (copy_to_user(rq->ifr_data, buffer, length)) { + ret = -EFAULT; + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + break; + + case AR6000_XIOCTL_BMI_WRITE_MEMORY: + get_user(address, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + AR_DEBUG_PRINTF("Write Memory (address: 0x%x, length: %d)\n", + address, length); + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + if (copy_from_user(buffer, &userdata[sizeof(address) + + sizeof(length)], length)) + { + ret = -EFAULT; + } else { + ret = BMIWriteMemory(hifDevice, address, buffer, length); + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + break; + + case AR6000_XIOCTL_BMI_TEST: + AR_DEBUG_PRINTF("No longer supported\n"); + ret = -EOPNOTSUPP; + break; + + case AR6000_XIOCTL_BMI_EXECUTE: + get_user(address, (unsigned int *)userdata); + get_user(param, (unsigned int *)userdata + 1); + AR_DEBUG_PRINTF("Execute (address: 0x%x, param: %d)\n", + address, param); + ret = BMIExecute(hifDevice, address, ¶m); + put_user(param, (unsigned int *)rq->ifr_data); /* return value */ + break; + + case AR6000_XIOCTL_BMI_SET_APP_START: + get_user(address, (unsigned int *)userdata); + AR_DEBUG_PRINTF("Set App Start (address: 0x%x)\n", address); + ret = BMISetAppStart(hifDevice, address); + break; + + case AR6000_XIOCTL_BMI_READ_SOC_REGISTER: + get_user(address, (unsigned int *)userdata); + ret = BMIReadSOCRegister(hifDevice, address, ¶m); + put_user(param, (unsigned int *)rq->ifr_data); /* return value */ + break; + + case AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER: + get_user(address, (unsigned int *)userdata); + get_user(param, (unsigned int *)userdata + 1); + ret = BMIWriteSOCRegister(hifDevice, address, param); + break; + +#ifdef HTC_RAW_INTERFACE + case AR6000_XIOCTL_HTC_RAW_OPEN: + ret = A_OK; + if (!arRawIfEnabled(ar)) { + /* make sure block size is set in case the target was reset since last + * BMI phase (i.e. flashup downloads) */ + ret = ar6000_set_htc_params(ar->arHifDevice, + ar->arTargetType, + 0, /* use default yield */ + 0 /* use default number of HTC ctrl buffers */ + ); + if (A_FAILED(ret)) { + break; + } + /* Terminate the BMI phase */ + ret = BMIDone(hifDevice); + if (ret == A_OK) { + ret = ar6000_htc_raw_open(ar); + } + } + break; + + case AR6000_XIOCTL_HTC_RAW_CLOSE: + if (arRawIfEnabled(ar)) { + ret = ar6000_htc_raw_close(ar); + arRawIfEnabled(ar) = FALSE; + } else { + ret = A_ERROR; + } + break; + + case AR6000_XIOCTL_HTC_RAW_READ: + if (arRawIfEnabled(ar)) { + unsigned int streamID; + get_user(streamID, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + mb(); /* Memory barrier */ + buffer = rq->ifr_data + sizeof(length); + ret = ar6000_htc_raw_read(ar, (HTC_RAW_STREAM_ID)streamID, + buffer, length); + put_user(ret, (unsigned int *)rq->ifr_data); + } else { + ret = A_ERROR; + } + break; + + case AR6000_XIOCTL_HTC_RAW_WRITE: + if (arRawIfEnabled(ar)) { + unsigned int streamID; + get_user(streamID, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + mb(); /* Memory barrier */ + buffer = userdata + sizeof(streamID) + sizeof(length); + ret = ar6000_htc_raw_write(ar, (HTC_RAW_STREAM_ID)streamID, + buffer, length); + put_user(ret, (unsigned int *)rq->ifr_data); + } else { + ret = A_ERROR; + } + break; +#endif /* HTC_RAW_INTERFACE */ + + case AR6000_XIOCTL_BMI_LZ_STREAM_START: + get_user(address, (unsigned int *)userdata); + AR_DEBUG_PRINTF("Start Compressed Stream (address: 0x%x)\n", address); + ret = BMILZStreamStart(hifDevice, address); + break; + + case AR6000_XIOCTL_BMI_LZ_DATA: + get_user(length, (unsigned int *)userdata); + AR_DEBUG_PRINTF("Send Compressed Data (length: %d)\n", length); + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + if (copy_from_user(buffer, &userdata[sizeof(length)], length)) + { + ret = -EFAULT; + } else { + ret = BMILZData(hifDevice, buffer, length); + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + break; + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) + /* + * Optional support for Target-side profiling. + * Not needed in production. + */ + + /* Configure Target-side profiling */ + case AR6000_XIOCTL_PROF_CFG: + { + A_UINT32 period; + A_UINT32 nbins; + get_user(period, (unsigned int *)userdata); + get_user(nbins, (unsigned int *)userdata + 1); + + if (wmi_prof_cfg_cmd(ar->arWmi, period, nbins) != A_OK) { + ret = -EIO; + } + + break; + } + + /* Start a profiling bucket/bin at the specified address */ + case AR6000_XIOCTL_PROF_ADDR_SET: + { + A_UINT32 addr; + get_user(addr, (unsigned int *)userdata); + + if (wmi_prof_addr_set_cmd(ar->arWmi, addr) != A_OK) { + ret = -EIO; + } + + break; + } + + /* START Target-side profiling */ + case AR6000_XIOCTL_PROF_START: + wmi_prof_start_cmd(ar->arWmi); + break; + + /* STOP Target-side profiling */ + case AR6000_XIOCTL_PROF_STOP: + wmi_prof_stop_cmd(ar->arWmi); + break; + case AR6000_XIOCTL_PROF_COUNT_GET: + { + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + prof_count_available = FALSE; + ret = prof_count_get(dev); + if (ret != A_OK) { + up(&ar->arSem); + return -EIO; + } + + /* Wait for Target to respond. */ + wait_event_interruptible(arEvent, prof_count_available); + if (signal_pending(current)) { + ret = -EINTR; + } else { + if (copy_to_user(userdata, &prof_count_results, + sizeof(prof_count_results))) + { + ret = -EFAULT; + } + } + up(&ar->arSem); + break; + } +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + + case AR6000_IOCTL_WMI_GETREV: + { + if (copy_to_user(rq->ifr_data, &ar->arVersion, + sizeof(ar->arVersion))) + { + ret = -EFAULT; + } + break; + } + case AR6000_IOCTL_WMI_SETPWR: + { + WMI_POWER_MODE_CMD pwrModeCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&pwrModeCmd, userdata, + sizeof(pwrModeCmd))) + { + ret = -EFAULT; + } else { + if (wmi_powermode_cmd(ar->arWmi, pwrModeCmd.powerMode) + != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS: + { + WMI_IBSS_PM_CAPS_CMD ibssPmCaps; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&ibssPmCaps, userdata, + sizeof(ibssPmCaps))) + { + ret = -EFAULT; + } else { + if (wmi_ibsspmcaps_cmd(ar->arWmi, ibssPmCaps.power_saving, ibssPmCaps.ttl, + ibssPmCaps.atim_windows, ibssPmCaps.timeout_value) != A_OK) + { + ret = -EIO; + } + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arIbssPsEnable = ibssPmCaps.power_saving; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + break; + } + case AR6000_IOCTL_WMI_SET_PMPARAMS: + { + WMI_POWER_PARAMS_CMD pmParams; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&pmParams, userdata, + sizeof(pmParams))) + { + ret = -EFAULT; + } else { + if (wmi_pmparams_cmd(ar->arWmi, pmParams.idle_period, + pmParams.pspoll_number, + pmParams.dtim_policy) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SETSCAN: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&scParams, userdata, + sizeof(scParams))) + { + ret = -EFAULT; + } else { + if (CAN_SCAN_IN_CONNECT(scParams.scanCtrlFlags)) { + ar->arSkipScan = FALSE; + } else { + ar->arSkipScan = TRUE; + } + + if (wmi_scanparams_cmd(ar->arWmi, scParams.fg_start_period, + scParams.fg_end_period, + scParams.bg_period, + scParams.minact_chdwell_time, + scParams.maxact_chdwell_time, + scParams.pas_chdwell_time, + scParams.shortScanRatio, + scParams.scanCtrlFlags, + scParams.max_dfsch_act_time, + scParams.maxact_scan_per_ssid) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SETLISTENINT: + { + WMI_LISTEN_INT_CMD listenCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&listenCmd, userdata, + sizeof(listenCmd))) + { + ret = -EFAULT; + } else { + if (wmi_listeninterval_cmd(ar->arWmi, listenCmd.listenInterval, listenCmd.numBeacons) != A_OK) { + ret = -EIO; + } else { + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arListenInterval = param; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + + } + break; + } + case AR6000_IOCTL_WMI_SET_BMISS_TIME: + { + WMI_BMISS_TIME_CMD bmissCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&bmissCmd, userdata, + sizeof(bmissCmd))) + { + ret = -EFAULT; + } else { + if (wmi_bmisstime_cmd(ar->arWmi, bmissCmd.bmissTime, bmissCmd.numBeacons) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SETBSSFILTER: + { + WMI_BSS_FILTER_CMD filt; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&filt, userdata, + sizeof(filt))) + { + ret = -EFAULT; + } else { + if (wmi_bssfilter_cmd(ar->arWmi, filt.bssFilter, filt.ieMask) + != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SET_SNRTHRESHOLD: + { + ret = ar6000_ioctl_set_snr_threshold(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD: + { + ret = ar6000_ioctl_set_rssi_threshold(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_CLR_RSSISNR: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } + ret = wmi_clr_rssi_snr(ar->arWmi); + break; + } + case AR6000_XIOCTL_WMI_SET_LQTHRESHOLD: + { + ret = ar6000_ioctl_set_lq_threshold(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_SET_LPREAMBLE: + { + WMI_SET_LPREAMBLE_CMD setLpreambleCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setLpreambleCmd, userdata, + sizeof(setLpreambleCmd))) + { + ret = -EFAULT; + } else { + if (wmi_set_lpreamble_cmd(ar->arWmi, setLpreambleCmd.status) + != A_OK) + { + ret = -EIO; + } + } + + break; + } + case AR6000_XIOCTL_WMI_SET_RTS: + { + WMI_SET_RTS_CMD rtsCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&rtsCmd, userdata, + sizeof(rtsCmd))) + { + ret = -EFAULT; + } else { + if (wmi_set_rts_cmd(ar->arWmi, rtsCmd.threshold) + != A_OK) + { + ret = -EIO; + } + } + + break; + } + case AR6000_XIOCTL_WMI_SET_WMM: + { + ret = ar6000_ioctl_set_wmm(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_SET_TXOP: + { + ret = ar6000_ioctl_set_txop(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_GET_RD: + { + ret = ar6000_ioctl_get_rd(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_CHANNELPARAMS: + { + ret = ar6000_ioctl_set_channelParams(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_PROBEDSSID: + { + ret = ar6000_ioctl_set_probedSsid(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_BADAP: + { + ret = ar6000_ioctl_set_badAp(dev, rq); + break; + } + case AR6000_IOCTL_WMI_CREATE_QOS: + { + ret = ar6000_ioctl_create_qos(dev, rq); + break; + } + case AR6000_IOCTL_WMI_DELETE_QOS: + { + ret = ar6000_ioctl_delete_qos(dev, rq); + break; + } + case AR6000_IOCTL_WMI_GET_QOS_QUEUE: + { + ret = ar6000_ioctl_get_qos_queue(dev, rq); + break; + } + case AR6000_IOCTL_WMI_GET_TARGET_STATS: + { + ret = ar6000_ioctl_get_target_stats(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK: + { + ret = ar6000_ioctl_set_error_report_bitmask(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_ASSOC_INFO: + { + WMI_SET_ASSOC_INFO_CMD cmd; + A_UINT8 assocInfo[WMI_MAX_ASSOC_INFO_LEN]; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + get_user(cmd.ieType, userdata); + if (cmd.ieType >= WMI_MAX_ASSOC_INFO_TYPE) { + ret = -EIO; + } else { + get_user(cmd.bufferSize, userdata + 1); + if (cmd.bufferSize > WMI_MAX_ASSOC_INFO_LEN) { + ret = -EFAULT; + break; + } + if (copy_from_user(assocInfo, userdata + 2, + cmd.bufferSize)) + { + ret = -EFAULT; + } else { + if (wmi_associnfo_cmd(ar->arWmi, cmd.ieType, + cmd.bufferSize, + assocInfo) != A_OK) + { + ret = -EIO; + } + } + } + } + break; + } + case AR6000_IOCTL_WMI_SET_ACCESS_PARAMS: + { + ret = ar6000_ioctl_set_access_params(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_DISC_TIMEOUT: + { + ret = ar6000_ioctl_set_disconnect_timeout(dev, rq); + break; + } + case AR6000_XIOCTL_FORCE_TARGET_RESET: + { + if (ar->arHtcTarget) + { +// HTCForceReset(htcTarget); + } + else + { + AR_DEBUG_PRINTF("ar6000_ioctl cannot attempt reset.\n"); + } + break; + } + case AR6000_XIOCTL_TARGET_INFO: + case AR6000_XIOCTL_CHECK_TARGET_READY: /* backwards compatibility */ + { + /* If we made it to here, then the Target exists and is ready. */ + + if (cmd == AR6000_XIOCTL_TARGET_INFO) { + if (copy_to_user((A_UINT32 *)rq->ifr_data, &ar->arVersion.target_ver, + sizeof(ar->arVersion.target_ver))) + { + ret = -EFAULT; + } + if (copy_to_user(((A_UINT32 *)rq->ifr_data)+1, &ar->arTargetType, + sizeof(ar->arTargetType))) + { + ret = -EFAULT; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS: + { + WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD hbparam; + + if (copy_from_user(&hbparam, userdata, sizeof(hbparam))) + { + ret = -EFAULT; + } else { + AR6000_SPIN_LOCK(&ar->arLock, 0); + /* Start a cyclic timer with the parameters provided. */ + if (hbparam.frequency) { + ar->arHBChallengeResp.frequency = hbparam.frequency; + } + if (hbparam.threshold) { + ar->arHBChallengeResp.missThres = hbparam.threshold; + } + + /* Delete the pending timer and start a new one */ + if (timer_pending(&ar->arHBChallengeResp.timer)) { + A_UNTIMEOUT(&ar->arHBChallengeResp.timer); + } + A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + break; + } + case AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP: + { + A_UINT32 cookie; + + if (copy_from_user(&cookie, userdata, sizeof(cookie))) { + return -EFAULT; + } + + /* Send the challenge on the control channel */ + if (wmi_get_challenge_resp_cmd(ar->arWmi, cookie, APP_HB_CHALLENGE) != A_OK) { + return -EIO; + } + break; + } +#ifdef USER_KEYS + case AR6000_XIOCTL_USER_SETKEYS: + { + + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_RUN; + + if (copy_from_user(&ar->user_key_ctrl, userdata, + sizeof(ar->user_key_ctrl))) + { + return -EFAULT; + } + + A_PRINTF("ar6000 USER set key %x\n", ar->user_key_ctrl); + break; + } +#endif /* USER_KEYS */ + +#ifdef CONFIG_HOST_GPIO_SUPPORT + case AR6000_XIOCTL_GPIO_OUTPUT_SET: + { + struct ar6000_gpio_output_set_cmd_s gpio_output_set_cmd; + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + if (copy_from_user(&gpio_output_set_cmd, userdata, + sizeof(gpio_output_set_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_output_set(dev, + gpio_output_set_cmd.set_mask, + gpio_output_set_cmd.clear_mask, + gpio_output_set_cmd.enable_mask, + gpio_output_set_cmd.disable_mask); + if (ret != A_OK) { + ret = EIO; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_INPUT_GET: + { + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + ret = ar6000_gpio_input_get(dev); + if (ret != A_OK) { + up(&ar->arSem); + return -EIO; + } + + /* Wait for Target to respond. */ + wait_event_interruptible(arEvent, gpio_data_available); + if (signal_pending(current)) { + ret = -EINTR; + } else { + A_ASSERT(gpio_reg_results.gpioreg_id == GPIO_ID_NONE); + + if (copy_to_user(userdata, &gpio_reg_results.value, + sizeof(gpio_reg_results.value))) + { + ret = -EFAULT; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_REGISTER_SET: + { + struct ar6000_gpio_register_cmd_s gpio_register_cmd; + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + if (copy_from_user(&gpio_register_cmd, userdata, + sizeof(gpio_register_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_register_set(dev, + gpio_register_cmd.gpioreg_id, + gpio_register_cmd.value); + if (ret != A_OK) { + ret = EIO; + } + + /* Wait for acknowledgement from Target */ + wait_event_interruptible(arEvent, gpio_ack_received); + if (signal_pending(current)) { + ret = -EINTR; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_REGISTER_GET: + { + struct ar6000_gpio_register_cmd_s gpio_register_cmd; + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + if (copy_from_user(&gpio_register_cmd, userdata, + sizeof(gpio_register_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_register_get(dev, gpio_register_cmd.gpioreg_id); + if (ret != A_OK) { + up(&ar->arSem); + return -EIO; + } + + /* Wait for Target to respond. */ + wait_event_interruptible(arEvent, gpio_data_available); + if (signal_pending(current)) { + ret = -EINTR; + } else { + A_ASSERT(gpio_register_cmd.gpioreg_id == gpio_reg_results.gpioreg_id); + if (copy_to_user(userdata, &gpio_reg_results, + sizeof(gpio_reg_results))) + { + ret = -EFAULT; + } + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_INTR_ACK: + { + struct ar6000_gpio_intr_ack_cmd_s gpio_intr_ack_cmd; + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + if (copy_from_user(&gpio_intr_ack_cmd, userdata, + sizeof(gpio_intr_ack_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_intr_ack(dev, gpio_intr_ack_cmd.ack_mask); + if (ret != A_OK) { + ret = EIO; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_INTR_WAIT: + { + /* Wait for Target to report an interrupt. */ + dev_hold(dev); + rtnl_unlock(); + wait_event_interruptible(arEvent, gpio_intr_available); + rtnl_lock(); + __dev_put(dev); + + if (signal_pending(current)) { + ret = -EINTR; + } else { + if (copy_to_user(userdata, &gpio_intr_results, + sizeof(gpio_intr_results))) + { + ret = -EFAULT; + } + } + break; + } +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + + case AR6000_XIOCTL_DBGLOG_CFG_MODULE: + { + struct ar6000_dbglog_module_config_s config; + + if (copy_from_user(&config, userdata, sizeof(config))) { + return -EFAULT; + } + + /* Send the challenge on the control channel */ + if (wmi_config_debug_module_cmd(ar->arWmi, config.mmask, + config.tsr, config.rep, + config.size, config.valid) != A_OK) + { + return -EIO; + } + break; + } + + case AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS: + { + /* Send the challenge on the control channel */ + if (ar6000_dbglog_get_debug_logs(ar) != A_OK) + { + return -EIO; + } + break; + } + + case AR6000_XIOCTL_SET_ADHOC_BSSID: + { + WMI_SET_ADHOC_BSSID_CMD adhocBssid; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&adhocBssid, userdata, + sizeof(adhocBssid))) + { + ret = -EFAULT; + } else if (A_MEMCMP(adhocBssid.bssid, bcast_mac, + AR6000_ETH_ADDR_LEN) == 0) + { + ret = -EFAULT; + } else { + + A_MEMCPY(ar->arReqBssid, adhocBssid.bssid, sizeof(ar->arReqBssid)); + } + break; + } + + case AR6000_XIOCTL_SET_OPT_MODE: + { + WMI_SET_OPT_MODE_CMD optModeCmd; + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&optModeCmd, userdata, + sizeof(optModeCmd))) + { + ret = -EFAULT; + } else if (ar->arConnected && optModeCmd.optMode == SPECIAL_ON) { + ret = -EFAULT; + + } else if (wmi_set_opt_mode_cmd(ar->arWmi, optModeCmd.optMode) + != A_OK) + { + ret = -EIO; + } + break; + } + + case AR6000_XIOCTL_OPT_SEND_FRAME: + { + WMI_OPT_TX_FRAME_CMD optTxFrmCmd; + A_UINT8 data[MAX_OPT_DATA_LEN]; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&optTxFrmCmd, userdata, + sizeof(optTxFrmCmd))) + { + ret = -EFAULT; + } else if (copy_from_user(data, + userdata+sizeof(WMI_OPT_TX_FRAME_CMD)-1, + optTxFrmCmd.optIEDataLen)) + { + ret = -EFAULT; + } else { + ret = wmi_opt_tx_frame_cmd(ar->arWmi, + optTxFrmCmd.frmType, + optTxFrmCmd.dstAddr, + optTxFrmCmd.bssid, + optTxFrmCmd.optIEDataLen, + data); + } + + break; + } + case AR6000_XIOCTL_WMI_SETRETRYLIMITS: + { + WMI_SET_RETRY_LIMITS_CMD setRetryParams; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setRetryParams, userdata, + sizeof(setRetryParams))) + { + ret = -EFAULT; + } else { + if (wmi_set_retry_limits_cmd(ar->arWmi, setRetryParams.frameType, + setRetryParams.trafficClass, + setRetryParams.maxRetries, + setRetryParams.enableNotify) != A_OK) + { + ret = -EIO; + } + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arMaxRetries = setRetryParams.maxRetries; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + break; + } + + case AR6000_XIOCTL_SET_BEACON_INTVAL: + { + WMI_BEACON_INT_CMD bIntvlCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&bIntvlCmd, userdata, + sizeof(bIntvlCmd))) + { + ret = -EFAULT; + } else if (wmi_set_adhoc_bconIntvl_cmd(ar->arWmi, bIntvlCmd.beaconInterval) + != A_OK) + { + ret = -EIO; + } + if(ret == 0) { + ar->ap_profile_flag = 1; /* There is a change in profile */ + } + break; + } + case IEEE80211_IOCTL_SETAUTHALG: + { + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + struct ieee80211req_authalg req; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&req, userdata, + sizeof(struct ieee80211req_authalg))) + { + ret = -EFAULT; + } else { + if (req.auth_alg & AUTH_ALG_OPEN_SYSTEM) { + ar->arDot11AuthMode |= OPEN_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arGroupCrypto = NONE_CRYPT; + } + if (req.auth_alg & AUTH_ALG_SHARED_KEY) { + ar->arDot11AuthMode |= SHARED_AUTH; + ar->arPairwiseCrypto = WEP_CRYPT; + ar->arGroupCrypto = WEP_CRYPT; + } + if (req.auth_alg == AUTH_ALG_LEAP) { + ar->arDot11AuthMode = LEAP_AUTH; + } + } + break; + } + + case AR6000_XIOCTL_SET_VOICE_PKT_SIZE: + ret = ar6000_xioctl_set_voice_pkt_size(dev, userdata); + break; + + case AR6000_XIOCTL_SET_MAX_SP: + ret = ar6000_xioctl_set_max_sp_len(dev, userdata); + break; + + case AR6000_XIOCTL_WMI_GET_ROAM_TBL: + ret = ar6000_ioctl_get_roam_tbl(dev, rq); + break; + case AR6000_XIOCTL_WMI_SET_ROAM_CTRL: + ret = ar6000_ioctl_set_roam_ctrl(dev, userdata); + break; + case AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS: + ret = ar6000_ioctl_set_powersave_timers(dev, userdata); + break; + case AR6000_XIOCTRL_WMI_GET_POWER_MODE: + ret = ar6000_ioctl_get_power_mode(dev, rq); + break; + case AR6000_XIOCTRL_WMI_SET_WLAN_STATE: + get_user(ar->arWlanState, (unsigned int *)userdata); + if (ar->arWmiReady == FALSE) { + ret = -EIO; + break; + } + + if (ar->arWlanState == WLAN_ENABLED) { + /* Enable foreground scanning */ + if (wmi_scanparams_cmd(ar->arWmi, scParams.fg_start_period, + scParams.fg_end_period, + scParams.bg_period, + scParams.minact_chdwell_time, + scParams.maxact_chdwell_time, + scParams.pas_chdwell_time, + scParams.shortScanRatio, + scParams.scanCtrlFlags, + scParams.max_dfsch_act_time, + scParams.maxact_scan_per_ssid) != A_OK) + { + ret = -EIO; + } + if (ar->arSsidLen) { + ar->arConnectPending = TRUE; + if (wmi_connect_cmd(ar->arWmi, ar->arNetworkType, + ar->arDot11AuthMode, ar->arAuthMode, + ar->arPairwiseCrypto, + ar->arPairwiseCryptoLen, + ar->arGroupCrypto, ar->arGroupCryptoLen, + ar->arSsidLen, ar->arSsid, + ar->arReqBssid, ar->arChannelHint, + ar->arConnectCtrlFlags) != A_OK) + { + ret = -EIO; + ar->arConnectPending = FALSE; + } + } + } else { + /* Disconnect from the AP and disable foreground scanning */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) { + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + wmi_disconnect_cmd(ar->arWmi); + } else { + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + + if (wmi_scanparams_cmd(ar->arWmi, 0xFFFF, 0, 0, 0, 0, 0, 0, 0xFF, 0, 0) != A_OK) + { + ret = -EIO; + } + } + break; + case AR6000_XIOCTL_WMI_GET_ROAM_DATA: + ret = ar6000_ioctl_get_roam_data(dev, rq); + break; + case AR6000_XIOCTL_WMI_SET_BT_STATUS: + ret = ar6000_xioctl_set_bt_status_cmd(dev, userdata); + break; + case AR6000_XIOCTL_WMI_SET_BT_PARAMS: + ret = ar6000_xioctl_set_bt_params_cmd(dev, userdata); + break; + case AR6000_XIOCTL_WMI_STARTSCAN: + { + WMI_START_SCAN_CMD setStartScanCmd, *cmdp; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setStartScanCmd, userdata, + sizeof(setStartScanCmd))) + { + ret = -EFAULT; + } else { + if (setStartScanCmd.numChannels > 1) { + cmdp = A_MALLOC(130); + if (copy_from_user(cmdp, userdata, + sizeof (*cmdp) + + ((setStartScanCmd.numChannels - 1) * + sizeof(A_UINT16)))) + { + kfree(cmdp); + return -EFAULT; + } + } else { + cmdp = &setStartScanCmd; + } + + if (wmi_startscan_cmd(ar->arWmi, cmdp->scanType, + cmdp->forceFgScan, + cmdp->isLegacy, + cmdp->homeDwellTime, + cmdp->forceScanInterval, + cmdp->numChannels, + cmdp->channelList) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SETFIXRATES: + { + WMI_FIX_RATES_CMD setFixRatesCmd; + A_STATUS returnStatus; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setFixRatesCmd, userdata, + sizeof(setFixRatesCmd))) + { + ret = -EFAULT; + } else { + returnStatus = wmi_set_fixrates_cmd(ar->arWmi, setFixRatesCmd.fixRateMask); + if (returnStatus == A_EINVAL) { + ret = -EINVAL; + } else if(returnStatus != A_OK) { + ret = -EIO; + } else { + ar->ap_profile_flag = 1; /* There is a change in profile */ + } + } + break; + } + + case AR6000_XIOCTL_WMI_GETFIXRATES: + { + WMI_FIX_RATES_CMD getFixRatesCmd; + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + int ret = 0; + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + /* Used copy_from_user/copy_to_user to access user space data */ + if (copy_from_user(&getFixRatesCmd, userdata, sizeof(getFixRatesCmd))) { + ret = -EFAULT; + } else { + ar->arRateMask = 0xFFFF; + + if (wmi_get_ratemask_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->arRateMask != 0xFFFF, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + + if (!ret) { + getFixRatesCmd.fixRateMask = ar->arRateMask; + } + + if(copy_to_user(userdata, &getFixRatesCmd, sizeof(getFixRatesCmd))) { + ret = -EFAULT; + } + + up(&ar->arSem); + } + break; + } + case AR6000_XIOCTL_WMI_SET_AUTHMODE: + { + WMI_SET_AUTH_MODE_CMD setAuthMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setAuthMode, userdata, + sizeof(setAuthMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_authmode_cmd(ar->arWmi, setAuthMode.mode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_REASSOCMODE: + { + WMI_SET_REASSOC_MODE_CMD setReassocMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setReassocMode, userdata, + sizeof(setReassocMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_reassocmode_cmd(ar->arWmi, setReassocMode.mode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_DIAG_READ: + { + A_UINT32 addr, data; + get_user(addr, (unsigned int *)userdata); + addr = TARG_VTOP(ar->arTargetType, addr); + if (ar6000_ReadRegDiag(ar->arHifDevice, &addr, &data) != A_OK) { + ret = -EIO; + } + put_user(data, (unsigned int *)userdata + 1); + break; + } + case AR6000_XIOCTL_DIAG_WRITE: + { + A_UINT32 addr, data; + get_user(addr, (unsigned int *)userdata); + get_user(data, (unsigned int *)userdata + 1); + addr = TARG_VTOP(ar->arTargetType, addr); + if (ar6000_WriteRegDiag(ar->arHifDevice, &addr, &data) != A_OK) { + ret = -EIO; + } + break; + } + case AR6000_XIOCTL_WMI_SET_KEEPALIVE: + { + WMI_SET_KEEPALIVE_CMD setKeepAlive; + if (ar->arWmiReady == FALSE) { + return -EIO; + } else if (copy_from_user(&setKeepAlive, userdata, + sizeof(setKeepAlive))){ + ret = -EFAULT; + } else { + if (wmi_set_keepalive_cmd(ar->arWmi, setKeepAlive.keepaliveInterval) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_PARAMS: + { + WMI_SET_PARAMS_CMD cmd; + if (ar->arWmiReady == FALSE) { + return -EIO; + } else if (copy_from_user(&cmd, userdata, + sizeof(cmd))){ + ret = -EFAULT; + } else if (copy_from_user(&cmd, userdata, + sizeof(cmd) + cmd.length)) + { + ret = -EFAULT; + } else { + if (wmi_set_params_cmd(ar->arWmi, cmd.opcode, cmd.length, cmd.buffer) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_MCAST_FILTER: + { + WMI_SET_MCAST_FILTER_CMD cmd; + if (ar->arWmiReady == FALSE) { + return -EIO; + } else if (copy_from_user(&cmd, userdata, + sizeof(cmd))){ + ret = -EFAULT; + } else { + if (wmi_set_mcast_filter_cmd(ar->arWmi, cmd.multicast_mac[0], + cmd.multicast_mac[1], + cmd.multicast_mac[2], + cmd.multicast_mac[3]) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_DEL_MCAST_FILTER: + { + WMI_SET_MCAST_FILTER_CMD cmd; + if (ar->arWmiReady == FALSE) { + return -EIO; + } else if (copy_from_user(&cmd, userdata, + sizeof(cmd))){ + ret = -EFAULT; + } else { + if (wmi_del_mcast_filter_cmd(ar->arWmi, cmd.multicast_mac[0], + cmd.multicast_mac[1], + cmd.multicast_mac[2], + cmd.multicast_mac[3]) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_GET_KEEPALIVE: + { + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_GET_KEEPALIVE_CMD getKeepAlive; + int ret = 0; + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + if (copy_from_user(&getKeepAlive, userdata,sizeof(getKeepAlive))) { + ret = -EFAULT; + } else { + getKeepAlive.keepaliveInterval = wmi_get_keepalive_cmd(ar->arWmi); + ar->arKeepaliveConfigured = 0xFF; + if (wmi_get_keepalive_configured(ar->arWmi) != A_OK){ + up(&ar->arSem); + return -EIO; + } + wait_event_interruptible_timeout(arEvent, ar->arKeepaliveConfigured != 0xFF, wmitimeout * HZ); + if (signal_pending(current)) { + ret = -EINTR; + } + + if (!ret) { + getKeepAlive.configured = ar->arKeepaliveConfigured; + } + if (copy_to_user(userdata, &getKeepAlive, sizeof(getKeepAlive))) { + ret = -EFAULT; + } + up(&ar->arSem); + } + break; + } + case AR6000_XIOCTL_WMI_SET_APPIE: + { + WMI_SET_APPIE_CMD appIEcmd; + A_UINT8 appIeInfo[IEEE80211_APPIE_FRAME_MAX_LEN]; + A_UINT32 fType,ieLen; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + get_user(fType, (A_UINT32 *)userdata); + appIEcmd.mgmtFrmType = fType; + if (appIEcmd.mgmtFrmType >= IEEE80211_APPIE_NUM_OF_FRAME) { + ret = -EIO; + } else { + get_user(ieLen, (A_UINT32 *)(userdata + 4)); + appIEcmd.ieLen = ieLen; + if (appIEcmd.ieLen > IEEE80211_APPIE_FRAME_MAX_LEN) { + ret = -EIO; + break; + } + if (copy_from_user(appIeInfo, userdata + 8, appIEcmd.ieLen)) { + ret = -EFAULT; + } else { + if (wmi_set_appie_cmd(ar->arWmi, appIEcmd.mgmtFrmType, + appIEcmd.ieLen, appIeInfo) != A_OK) + { + ret = -EIO; + } + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER: + { + WMI_BSS_FILTER_CMD cmd; + A_UINT32 filterType; + + if (copy_from_user(&filterType, userdata, sizeof(A_UINT32))) + { + return -EFAULT; + } + if (filterType & (IEEE80211_FILTER_TYPE_BEACON | + IEEE80211_FILTER_TYPE_PROBE_RESP)) + { + cmd.bssFilter = ALL_BSS_FILTER; + } else { + cmd.bssFilter = NONE_BSS_FILTER; + } + if (wmi_bssfilter_cmd(ar->arWmi, cmd.bssFilter, 0) != A_OK) { + ret = -EIO; + } + + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arMgmtFilter = filterType; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + break; + } + case AR6000_XIOCTL_WMI_SET_WSC_STATUS: + { + A_UINT32 wsc_status; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } else if (copy_from_user(&wsc_status, userdata, sizeof(A_UINT32))) + { + return -EFAULT; + } + if (wmi_set_wsc_status_cmd(ar->arWmi, wsc_status) != A_OK) { + ret = -EIO; + } + break; + } + case AR6000_XIOCTL_BMI_ROMPATCH_INSTALL: + { + A_UINT32 ROM_addr; + A_UINT32 RAM_addr; + A_UINT32 nbytes; + A_UINT32 do_activate; + A_UINT32 rompatch_id; + + get_user(ROM_addr, (A_UINT32 *)userdata); + get_user(RAM_addr, (A_UINT32 *)userdata + 1); + get_user(nbytes, (A_UINT32 *)userdata + 2); + get_user(do_activate, (A_UINT32 *)userdata + 3); + AR_DEBUG_PRINTF("Install rompatch from ROM: 0x%x to RAM: 0x%x length: %d\n", + ROM_addr, RAM_addr, nbytes); + ret = BMIrompatchInstall(hifDevice, ROM_addr, RAM_addr, + nbytes, do_activate, &rompatch_id); + if (ret == A_OK) { + put_user(rompatch_id, (unsigned int *)rq->ifr_data); /* return value */ + } + break; + } + + case AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL: + { + A_UINT32 rompatch_id; + + get_user(rompatch_id, (A_UINT32 *)userdata); + AR_DEBUG_PRINTF("UNinstall rompatch_id %d\n", rompatch_id); + ret = BMIrompatchUninstall(hifDevice, rompatch_id); + break; + } + + case AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE: + case AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE: + { + A_UINT32 rompatch_count; + + get_user(rompatch_count, (A_UINT32 *)userdata); + AR_DEBUG_PRINTF("Change rompatch activation count=%d\n", rompatch_count); + length = sizeof(A_UINT32) * rompatch_count; + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + if (copy_from_user(buffer, &userdata[sizeof(rompatch_count)], length)) + { + ret = -EFAULT; + } else { + if (cmd == AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE) { + ret = BMIrompatchActivate(hifDevice, rompatch_count, (A_UINT32 *)buffer); + } else { + ret = BMIrompatchDeactivate(hifDevice, rompatch_count, (A_UINT32 *)buffer); + } + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + + break; + } + case AR6000_XIOCTL_SET_IP: + { + WMI_SET_IP_CMD setIP; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setIP, userdata, + sizeof(setIP))) + { + ret = -EFAULT; + } else { + if (wmi_set_ip_cmd(ar->arWmi, + &setIP) != A_OK) + { + ret = -EIO; + } + } + break; + } + + case AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE: + { + WMI_SET_HOST_SLEEP_MODE_CMD setHostSleepMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setHostSleepMode, userdata, + sizeof(setHostSleepMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_host_sleep_mode_cmd(ar->arWmi, + &setHostSleepMode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_WOW_MODE: + { + WMI_SET_WOW_MODE_CMD setWowMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setWowMode, userdata, + sizeof(setWowMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_wow_mode_cmd(ar->arWmi, + &setWowMode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_GET_WOW_LIST: + { + WMI_GET_WOW_LIST_CMD getWowList; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&getWowList, userdata, + sizeof(getWowList))) + { + ret = -EFAULT; + } else { + if (wmi_get_wow_list_cmd(ar->arWmi, + &getWowList) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_ADD_WOW_PATTERN: + { +#define WOW_PATTERN_SIZE 64 +#define WOW_MASK_SIZE 64 + + WMI_ADD_WOW_PATTERN_CMD cmd; + A_UINT8 mask_data[WOW_PATTERN_SIZE]={0}; + A_UINT8 pattern_data[WOW_PATTERN_SIZE]={0}; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + + if(copy_from_user(&cmd, userdata, + sizeof(WMI_ADD_WOW_PATTERN_CMD))) + return -EFAULT; + if (copy_from_user(pattern_data, + userdata + 3, + cmd.filter_size)){ + ret = -EFAULT; + break; + } + if (copy_from_user(mask_data, + (userdata + 3 + cmd.filter_size), + cmd.filter_size)){ + ret = -EFAULT; + break; + } else { + if (wmi_add_wow_pattern_cmd(ar->arWmi, + &cmd, pattern_data, mask_data, cmd.filter_size) != A_OK){ + ret = -EIO; + } + } + } +#undef WOW_PATTERN_SIZE +#undef WOW_MASK_SIZE + break; + } + case AR6000_XIOCTL_WMI_DEL_WOW_PATTERN: + { + WMI_DEL_WOW_PATTERN_CMD delWowPattern; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&delWowPattern, userdata, + sizeof(delWowPattern))) + { + ret = -EFAULT; + } else { + if (wmi_del_wow_pattern_cmd(ar->arWmi, + &delWowPattern) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE: + if (ar->arHtcTarget != NULL) { + HTCDumpCreditStates(ar->arHtcTarget); + } + break; + case AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE: + if (ar->arHtcTarget != NULL) { + struct ar6000_traffic_activity_change data; + + if (copy_from_user(&data, userdata, sizeof(data))) + { + return -EFAULT; + } + /* note, this is used for testing (mbox ping testing), indicate activity + * change using the stream ID as the traffic class */ + ar6000_indicate_tx_activity(ar, + (A_UINT8)data.StreamID, + data.Active ? TRUE : FALSE); + } + break; + case AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&connectCtrlFlags, userdata, + sizeof(connectCtrlFlags))) + { + ret = -EFAULT; + } else { + ar->arConnectCtrlFlags = connectCtrlFlags; + } + break; + case AR6000_XIOCTL_WMI_SET_AKMP_PARAMS: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&akmpParams, userdata, + sizeof(WMI_SET_AKMP_PARAMS_CMD))) + { + ret = -EFAULT; + } else { + if (wmi_set_akmp_params_cmd(ar->arWmi, &akmpParams) != A_OK) { + ret = -EIO; + } + } + break; + case AR6000_XIOCTL_WMI_SET_PMKID_LIST: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + if (copy_from_user(&pmkidInfo.numPMKID, userdata, + sizeof(pmkidInfo.numPMKID))) + { + ret = -EFAULT; + break; + } + if (copy_from_user(&pmkidInfo.pmkidList, + userdata + sizeof(pmkidInfo.numPMKID), + pmkidInfo.numPMKID * sizeof(WMI_PMKID))) + { + ret = -EFAULT; + break; + } + if (wmi_set_pmkid_list_cmd(ar->arWmi, &pmkidInfo) != A_OK) { + ret = -EIO; + } + } + break; + case AR6000_XIOCTL_WMI_GET_PMKID_LIST: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + if (wmi_get_pmkid_list_cmd(ar->arWmi) != A_OK) { + ret = -EIO; + } + } + break; + case AR6000_XIOCTL_WMI_ABORT_SCAN: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } + ret = wmi_abort_scan_cmd(ar->arWmi); + break; + case AR6000_XIOCTL_AP_HIDDEN_SSID: + { + A_UINT8 hidden_ssid; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&hidden_ssid, userdata, sizeof(hidden_ssid))) { + ret = -EFAULT; + } else { + wmi_ap_set_hidden_ssid(ar->arWmi, hidden_ssid); + ar->ap_profile_flag = 1; /* There is a change in profile */ + } + break; + } + case AR6000_XIOCTL_AP_GET_STA_LIST: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + A_UINT8 i; + ap_get_sta_t temp; + A_MEMZERO(&temp, sizeof(temp)); + for(i=0;ista_list[i].mac, ATH_MAC_LEN); + temp.sta[i].aid = ar->sta_list[i].aid; + } + if(copy_to_user((ap_get_sta_t *)rq->ifr_data, &temp, + sizeof(ar->sta_list))) { + ret = -EFAULT; + } + } + break; + } + case AR6000_XIOCTL_AP_SET_NUM_STA: + { + A_UINT8 num_sta; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&num_sta, userdata, sizeof(num_sta))) { + ret = -EFAULT; + } else if(num_sta > AP_MAX_NUM_STA) { + /* value out of range */ + ret = -EINVAL; + } else { + wmi_ap_set_num_sta(ar->arWmi, num_sta); + } + break; + } + case AR6000_XIOCTL_AP_SET_ACL_POLICY: + { + A_UINT8 policy; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&policy, userdata, sizeof(policy))) { + ret = -EFAULT; + } else if(policy == ar->g_acl.policy) { + /* No change in policy */ + } else { + if(!(policy & AP_ACL_RETAIN_LIST_MASK)) { + /* clear ACL list */ + memset(&ar->g_acl,0,sizeof(WMI_AP_ACL)); + } + ar->g_acl.policy = policy; + wmi_ap_set_acl_policy(ar->arWmi, policy); + } + break; + } + case AR6000_XIOCTL_AP_SET_ACL_MAC: + { + WMI_AP_ACL_MAC_CMD acl; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&acl, userdata, sizeof(acl))) { + ret = -EFAULT; + } else { + if(acl_add_del_mac(&ar->g_acl, &acl)) { + wmi_ap_acl_mac_list(ar->arWmi, &acl); + } else { + A_PRINTF("ACL list error\n"); + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_AP_GET_ACL_LIST: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if(copy_to_user((WMI_AP_ACL *)rq->ifr_data, &ar->g_acl, + sizeof(WMI_AP_ACL))) { + ret = -EFAULT; + } + break; + } + case AR6000_XIOCTL_AP_COMMIT_CONFIG: + { + ret = ar6000_ap_mode_profile_commit(ar); + break; + } + case IEEE80211_IOCTL_GETWPAIE: + { + struct ieee80211req_wpaie wpaie; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&wpaie, userdata, sizeof(wpaie))) { + ret = -EFAULT; + } else if (ar6000_ap_mode_get_wpa_ie(ar, &wpaie)) { + ret = -EFAULT; + } else if(copy_to_user(userdata, &wpaie, sizeof(wpaie))) { + ret = -EFAULT; + } + break; + } + case AR6000_XIOCTL_AP_CONN_INACT_TIME: + { + A_UINT32 period; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&period, userdata, sizeof(period))) { + ret = -EFAULT; + } else { + wmi_ap_conn_inact_time(ar->arWmi, period); + } + break; + } + case AR6000_XIOCTL_AP_PROT_SCAN_TIME: + { + WMI_AP_PROT_SCAN_TIME_CMD bgscan; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&bgscan, userdata, sizeof(bgscan))) { + ret = -EFAULT; + } else { + wmi_ap_bgscan_time(ar->arWmi, bgscan.period_min, bgscan.dwell_ms); + } + break; + } + case AR6000_XIOCTL_AP_SET_COUNTRY: + { + ret = ar6000_ioctl_set_country(dev, rq); + break; + } + case AR6000_XIOCTL_AP_SET_DTIM: + { + WMI_AP_SET_DTIM_CMD d; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&d, userdata, sizeof(d))) { + ret = -EFAULT; + } else { + if(d.dtim > 0 && d.dtim < 11) { + wmi_ap_set_dtim(ar->arWmi, d.dtim); + ar->ap_profile_flag = 1; /* There is a change in profile */ + } else { + A_PRINTF("DTIM out of range. Valid range is [1-10]\n"); + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT: + { + WMI_SET_TARGET_EVENT_REPORT_CMD evtCfgCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } + if (copy_from_user(&evtCfgCmd, userdata, + sizeof(evtCfgCmd))) { + ret = -EFAULT; + break; + } + ret = wmi_set_target_event_report_cmd(ar->arWmi, &evtCfgCmd); + break; + } + case AR6000_XIOCTL_AP_INTRA_BSS_COMM: + { + A_UINT8 intra=0; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&intra, userdata, sizeof(intra))) { + ret = -EFAULT; + } else { + ar->intra_bss = (intra?1:0); + } + break; + } + default: + ret = -EOPNOTSUPP; + } + return ret; +} + +A_UINT8 mac_cmp_wild(A_UINT8 *mac, A_UINT8 *new_mac, A_UINT8 wild, A_UINT8 new_wild) +{ + A_UINT8 i; + + for(i=0;i=0;i--) + { + if(mac_cmp_wild(a->acl_mac[i], acl->mac, a->wildcard[i], + acl->wildcard)==0) + already_avail = i; + + if(!((1 << i) & a->index)) + free_slot = i; + } + + if(acl->action == ADD_MAC_ADDR) + { + /* Dont add mac if it is already available */ + if((already_avail >= 0) || (free_slot == -1)) + return 0; + + A_MEMCPY(a->acl_mac[free_slot], acl->mac, ATH_MAC_LEN); + a->index = a->index | (1 << free_slot); + acl->index = free_slot; + a->wildcard[free_slot] = acl->wildcard; + return 1; + } + else if(acl->action == DEL_MAC_ADDR) + { + if(acl->index > AP_ACL_SIZE) + return 0; + + if(!(a->index & (1 << acl->index))) + return 0; + + A_MEMZERO(a->acl_mac[acl->index],ATH_MAC_LEN); + a->index = a->index & ~(1 << acl->index); + a->wildcard[acl->index] = 0; + return 1; + } + + return 0; +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/mbox_host_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/mbox_host_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k22/mbox_host_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/mbox_host_reg.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,409 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MBOX_HOST_REG_REG_H_ +#define _MBOX_HOST_REG_REG_H_ + +#define HOST_INT_STATUS_ADDRESS 0x00000400 +#define HOST_INT_STATUS_OFFSET 0x00000400 +#define HOST_INT_STATUS_ERROR_MSB 7 +#define HOST_INT_STATUS_ERROR_LSB 7 +#define HOST_INT_STATUS_ERROR_MASK 0x00000080 +#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB) +#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK) +#define HOST_INT_STATUS_CPU_MSB 6 +#define HOST_INT_STATUS_CPU_LSB 6 +#define HOST_INT_STATUS_CPU_MASK 0x00000040 +#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB) +#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK) +#define HOST_INT_STATUS_DRAGON_INT_MSB 5 +#define HOST_INT_STATUS_DRAGON_INT_LSB 5 +#define HOST_INT_STATUS_DRAGON_INT_MASK 0x00000020 +#define HOST_INT_STATUS_DRAGON_INT_GET(x) (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB) +#define HOST_INT_STATUS_DRAGON_INT_SET(x) (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK) +#define HOST_INT_STATUS_COUNTER_MSB 4 +#define HOST_INT_STATUS_COUNTER_LSB 4 +#define HOST_INT_STATUS_COUNTER_MASK 0x00000010 +#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB) +#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK) +#define HOST_INT_STATUS_MBOX_DATA_MSB 3 +#define HOST_INT_STATUS_MBOX_DATA_LSB 0 +#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f +#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB) +#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ADDRESS 0x00000401 +#define CPU_INT_STATUS_OFFSET 0x00000401 +#define CPU_INT_STATUS_BIT_MSB 7 +#define CPU_INT_STATUS_BIT_LSB 0 +#define CPU_INT_STATUS_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB) +#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK) + +#define ERROR_INT_STATUS_ADDRESS 0x00000402 +#define ERROR_INT_STATUS_OFFSET 0x00000402 +#define ERROR_INT_STATUS_SPI_MSB 3 +#define ERROR_INT_STATUS_SPI_LSB 3 +#define ERROR_INT_STATUS_SPI_MASK 0x00000008 +#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB) +#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK) +#define ERROR_INT_STATUS_WAKEUP_MSB 2 +#define ERROR_INT_STATUS_WAKEUP_LSB 2 +#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 +#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB) +#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK) +#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB) +#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) +#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB) +#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ADDRESS 0x00000403 +#define COUNTER_INT_STATUS_OFFSET 0x00000403 +#define COUNTER_INT_STATUS_COUNTER_MSB 7 +#define COUNTER_INT_STATUS_COUNTER_LSB 0 +#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff +#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB) +#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK) + +#define MBOX_FRAME_ADDRESS 0x00000404 +#define MBOX_FRAME_OFFSET 0x00000404 +#define MBOX_FRAME_RX_EOM_MSB 7 +#define MBOX_FRAME_RX_EOM_LSB 4 +#define MBOX_FRAME_RX_EOM_MASK 0x000000f0 +#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB) +#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK) +#define MBOX_FRAME_RX_SOM_MSB 3 +#define MBOX_FRAME_RX_SOM_LSB 0 +#define MBOX_FRAME_RX_SOM_MASK 0x0000000f +#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB) +#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK) + +#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405 +#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405 +#define RX_LOOKAHEAD_VALID_MBOX_MSB 3 +#define RX_LOOKAHEAD_VALID_MBOX_LSB 0 +#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f +#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB) +#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK) + +#define RX_LOOKAHEAD0_ADDRESS 0x00000408 +#define RX_LOOKAHEAD0_OFFSET 0x00000408 +#define RX_LOOKAHEAD0_DATA_MSB 7 +#define RX_LOOKAHEAD0_DATA_LSB 0 +#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB) +#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK) + +#define RX_LOOKAHEAD1_ADDRESS 0x0000040c +#define RX_LOOKAHEAD1_OFFSET 0x0000040c +#define RX_LOOKAHEAD1_DATA_MSB 7 +#define RX_LOOKAHEAD1_DATA_LSB 0 +#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB) +#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK) + +#define RX_LOOKAHEAD2_ADDRESS 0x00000410 +#define RX_LOOKAHEAD2_OFFSET 0x00000410 +#define RX_LOOKAHEAD2_DATA_MSB 7 +#define RX_LOOKAHEAD2_DATA_LSB 0 +#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB) +#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK) + +#define RX_LOOKAHEAD3_ADDRESS 0x00000414 +#define RX_LOOKAHEAD3_OFFSET 0x00000414 +#define RX_LOOKAHEAD3_DATA_MSB 7 +#define RX_LOOKAHEAD3_DATA_LSB 0 +#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB) +#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK) + +#define INT_STATUS_ENABLE_ADDRESS 0x00000418 +#define INT_STATUS_ENABLE_OFFSET 0x00000418 +#define INT_STATUS_ENABLE_ERROR_MSB 7 +#define INT_STATUS_ENABLE_ERROR_LSB 7 +#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080 +#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB) +#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK) +#define INT_STATUS_ENABLE_CPU_MSB 6 +#define INT_STATUS_ENABLE_CPU_LSB 6 +#define INT_STATUS_ENABLE_CPU_MASK 0x00000040 +#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB) +#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK) +#define INT_STATUS_ENABLE_DRAGON_INT_MSB 5 +#define INT_STATUS_ENABLE_DRAGON_INT_LSB 5 +#define INT_STATUS_ENABLE_DRAGON_INT_MASK 0x00000020 +#define INT_STATUS_ENABLE_DRAGON_INT_GET(x) (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB) +#define INT_STATUS_ENABLE_DRAGON_INT_SET(x) (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK) +#define INT_STATUS_ENABLE_COUNTER_MSB 4 +#define INT_STATUS_ENABLE_COUNTER_LSB 4 +#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 +#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB) +#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK) +#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3 +#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0 +#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f +#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB) +#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 +#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419 +#define CPU_INT_STATUS_ENABLE_BIT_MSB 7 +#define CPU_INT_STATUS_ENABLE_BIT_LSB 0 +#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB) +#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK) + +#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a +#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a +#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004 +#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB) +#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7 +#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 +#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB) +#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) + +#define COUNT_ADDRESS 0x00000420 +#define COUNT_OFFSET 0x00000420 +#define COUNT_VALUE_MSB 7 +#define COUNT_VALUE_LSB 0 +#define COUNT_VALUE_MASK 0x000000ff +#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB) +#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK) + +#define COUNT_DEC_ADDRESS 0x00000440 +#define COUNT_DEC_OFFSET 0x00000440 +#define COUNT_DEC_VALUE_MSB 7 +#define COUNT_DEC_VALUE_LSB 0 +#define COUNT_DEC_VALUE_MASK 0x000000ff +#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB) +#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK) + +#define SCRATCH_ADDRESS 0x00000460 +#define SCRATCH_OFFSET 0x00000460 +#define SCRATCH_VALUE_MSB 7 +#define SCRATCH_VALUE_LSB 0 +#define SCRATCH_VALUE_MASK 0x000000ff +#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB) +#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK) + +#define FIFO_TIMEOUT_ADDRESS 0x00000468 +#define FIFO_TIMEOUT_OFFSET 0x00000468 +#define FIFO_TIMEOUT_VALUE_MSB 7 +#define FIFO_TIMEOUT_VALUE_LSB 0 +#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff +#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB) +#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK) + +#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469 +#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469 +#define FIFO_TIMEOUT_ENABLE_SET_MSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_LSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001 +#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB) +#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK) + +#define DISABLE_SLEEP_ADDRESS 0x0000046a +#define DISABLE_SLEEP_OFFSET 0x0000046a +#define DISABLE_SLEEP_FOR_INT_MSB 1 +#define DISABLE_SLEEP_FOR_INT_LSB 1 +#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002 +#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB) +#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK) +#define DISABLE_SLEEP_ON_MSB 0 +#define DISABLE_SLEEP_ON_LSB 0 +#define DISABLE_SLEEP_ON_MASK 0x00000001 +#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB) +#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK) + +#define LOCAL_BUS_ADDRESS 0x00000470 +#define LOCAL_BUS_OFFSET 0x00000470 +#define LOCAL_BUS_STATE_MSB 1 +#define LOCAL_BUS_STATE_LSB 0 +#define LOCAL_BUS_STATE_MASK 0x00000003 +#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB) +#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK) + +#define INT_WLAN_ADDRESS 0x00000472 +#define INT_WLAN_OFFSET 0x00000472 +#define INT_WLAN_VECTOR_MSB 7 +#define INT_WLAN_VECTOR_LSB 0 +#define INT_WLAN_VECTOR_MASK 0x000000ff +#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB) +#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK) + +#define WINDOW_DATA_ADDRESS 0x00000474 +#define WINDOW_DATA_OFFSET 0x00000474 +#define WINDOW_DATA_DATA_MSB 7 +#define WINDOW_DATA_DATA_LSB 0 +#define WINDOW_DATA_DATA_MASK 0x000000ff +#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB) +#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK) + +#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 +#define WINDOW_WRITE_ADDR_OFFSET 0x00000478 +#define WINDOW_WRITE_ADDR_ADDR_MSB 7 +#define WINDOW_WRITE_ADDR_ADDR_LSB 0 +#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB) +#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK) + +#define WINDOW_READ_ADDR_ADDRESS 0x0000047c +#define WINDOW_READ_ADDR_OFFSET 0x0000047c +#define WINDOW_READ_ADDR_ADDR_MSB 7 +#define WINDOW_READ_ADDR_ADDR_LSB 0 +#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB) +#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK) + +#define SPI_CONFIG_ADDRESS 0x00000480 +#define SPI_CONFIG_OFFSET 0x00000480 +#define SPI_CONFIG_SPI_RESET_MSB 4 +#define SPI_CONFIG_SPI_RESET_LSB 4 +#define SPI_CONFIG_SPI_RESET_MASK 0x00000010 +#define SPI_CONFIG_SPI_RESET_GET(x) (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB) +#define SPI_CONFIG_SPI_RESET_SET(x) (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK) +#define SPI_CONFIG_INTERRUPT_ENABLE_MSB 3 +#define SPI_CONFIG_INTERRUPT_ENABLE_LSB 3 +#define SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008 +#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB) +#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) +#define SPI_CONFIG_TEST_MODE_MSB 2 +#define SPI_CONFIG_TEST_MODE_LSB 2 +#define SPI_CONFIG_TEST_MODE_MASK 0x00000004 +#define SPI_CONFIG_TEST_MODE_GET(x) (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB) +#define SPI_CONFIG_TEST_MODE_SET(x) (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK) +#define SPI_CONFIG_DATA_SIZE_MSB 1 +#define SPI_CONFIG_DATA_SIZE_LSB 0 +#define SPI_CONFIG_DATA_SIZE_MASK 0x00000003 +#define SPI_CONFIG_DATA_SIZE_GET(x) (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB) +#define SPI_CONFIG_DATA_SIZE_SET(x) (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK) + +#define SPI_STATUS_ADDRESS 0x00000481 +#define SPI_STATUS_OFFSET 0x00000481 +#define SPI_STATUS_ADDR_ERR_MSB 3 +#define SPI_STATUS_ADDR_ERR_LSB 3 +#define SPI_STATUS_ADDR_ERR_MASK 0x00000008 +#define SPI_STATUS_ADDR_ERR_GET(x) (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB) +#define SPI_STATUS_ADDR_ERR_SET(x) (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK) +#define SPI_STATUS_RD_ERR_MSB 2 +#define SPI_STATUS_RD_ERR_LSB 2 +#define SPI_STATUS_RD_ERR_MASK 0x00000004 +#define SPI_STATUS_RD_ERR_GET(x) (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB) +#define SPI_STATUS_RD_ERR_SET(x) (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK) +#define SPI_STATUS_WR_ERR_MSB 1 +#define SPI_STATUS_WR_ERR_LSB 1 +#define SPI_STATUS_WR_ERR_MASK 0x00000002 +#define SPI_STATUS_WR_ERR_GET(x) (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB) +#define SPI_STATUS_WR_ERR_SET(x) (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK) +#define SPI_STATUS_READY_MSB 0 +#define SPI_STATUS_READY_LSB 0 +#define SPI_STATUS_READY_MASK 0x00000001 +#define SPI_STATUS_READY_GET(x) (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB) +#define SPI_STATUS_READY_SET(x) (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK) + +#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482 +#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482 +#define NON_ASSOC_SLEEP_EN_BIT_MSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_LSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001 +#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB) +#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK) + +#define CIS_WINDOW_ADDRESS 0x00000600 +#define CIS_WINDOW_OFFSET 0x00000600 +#define CIS_WINDOW_DATA_MSB 7 +#define CIS_WINDOW_DATA_LSB 0 +#define CIS_WINDOW_DATA_MASK 0x000000ff +#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB) +#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mbox_host_reg_reg_s { + unsigned char pad0[1024]; /* pad to 0x400 */ + volatile unsigned char host_int_status; + volatile unsigned char cpu_int_status; + volatile unsigned char error_int_status; + volatile unsigned char counter_int_status; + volatile unsigned char mbox_frame; + volatile unsigned char rx_lookahead_valid; + unsigned char pad1[2]; /* pad to 0x408 */ + volatile unsigned char rx_lookahead0[4]; + volatile unsigned char rx_lookahead1[4]; + volatile unsigned char rx_lookahead2[4]; + volatile unsigned char rx_lookahead3[4]; + volatile unsigned char int_status_enable; + volatile unsigned char cpu_int_status_enable; + volatile unsigned char error_status_enable; + volatile unsigned char counter_int_status_enable; + unsigned char pad2[4]; /* pad to 0x420 */ + volatile unsigned char count[8]; + unsigned char pad3[24]; /* pad to 0x440 */ + volatile unsigned char count_dec[32]; + volatile unsigned char scratch[8]; + volatile unsigned char fifo_timeout; + volatile unsigned char fifo_timeout_enable; + volatile unsigned char disable_sleep; + unsigned char pad4[5]; /* pad to 0x470 */ + volatile unsigned char local_bus; + unsigned char pad5[1]; /* pad to 0x472 */ + volatile unsigned char int_wlan; + unsigned char pad6[1]; /* pad to 0x474 */ + volatile unsigned char window_data[4]; + volatile unsigned char window_write_addr[4]; + volatile unsigned char window_read_addr[4]; + volatile unsigned char spi_config; + volatile unsigned char spi_status; + volatile unsigned char non_assoc_sleep_en; + unsigned char pad7[381]; /* pad to 0x600 */ + volatile unsigned char cis_window[512]; +} mbox_host_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_HOST_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/mbox_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/mbox_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k22/mbox_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/mbox_reg.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,504 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MBOX_REG_REG_H_ +#define _MBOX_REG_REG_H_ + +#define MBOX_FIFO_ADDRESS 0x00000000 +#define MBOX_FIFO_OFFSET 0x00000000 +#define MBOX_FIFO_DATA_MSB 19 +#define MBOX_FIFO_DATA_LSB 0 +#define MBOX_FIFO_DATA_MASK 0x000fffff +#define MBOX_FIFO_DATA_GET(x) (((x) & MBOX_FIFO_DATA_MASK) >> MBOX_FIFO_DATA_LSB) +#define MBOX_FIFO_DATA_SET(x) (((x) << MBOX_FIFO_DATA_LSB) & MBOX_FIFO_DATA_MASK) + +#define MBOX_FIFO_STATUS_ADDRESS 0x00000010 +#define MBOX_FIFO_STATUS_OFFSET 0x00000010 +#define MBOX_FIFO_STATUS_EMPTY_MSB 19 +#define MBOX_FIFO_STATUS_EMPTY_LSB 16 +#define MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000 +#define MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & MBOX_FIFO_STATUS_EMPTY_MASK) >> MBOX_FIFO_STATUS_EMPTY_LSB) +#define MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << MBOX_FIFO_STATUS_EMPTY_LSB) & MBOX_FIFO_STATUS_EMPTY_MASK) +#define MBOX_FIFO_STATUS_FULL_MSB 15 +#define MBOX_FIFO_STATUS_FULL_LSB 12 +#define MBOX_FIFO_STATUS_FULL_MASK 0x0000f000 +#define MBOX_FIFO_STATUS_FULL_GET(x) (((x) & MBOX_FIFO_STATUS_FULL_MASK) >> MBOX_FIFO_STATUS_FULL_LSB) +#define MBOX_FIFO_STATUS_FULL_SET(x) (((x) << MBOX_FIFO_STATUS_FULL_LSB) & MBOX_FIFO_STATUS_FULL_MASK) + +#define MBOX_DMA_POLICY_ADDRESS 0x00000014 +#define MBOX_DMA_POLICY_OFFSET 0x00000014 +#define MBOX_DMA_POLICY_TX_QUANTUM_MSB 3 +#define MBOX_DMA_POLICY_TX_QUANTUM_LSB 3 +#define MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008 +#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> MBOX_DMA_POLICY_TX_QUANTUM_LSB) +#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_TX_QUANTUM_LSB) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) +#define MBOX_DMA_POLICY_TX_ORDER_MSB 2 +#define MBOX_DMA_POLICY_TX_ORDER_LSB 2 +#define MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004 +#define MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_TX_ORDER_MASK) >> MBOX_DMA_POLICY_TX_ORDER_LSB) +#define MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_TX_ORDER_LSB) & MBOX_DMA_POLICY_TX_ORDER_MASK) +#define MBOX_DMA_POLICY_RX_QUANTUM_MSB 1 +#define MBOX_DMA_POLICY_RX_QUANTUM_LSB 1 +#define MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002 +#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> MBOX_DMA_POLICY_RX_QUANTUM_LSB) +#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_RX_QUANTUM_LSB) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) +#define MBOX_DMA_POLICY_RX_ORDER_MSB 0 +#define MBOX_DMA_POLICY_RX_ORDER_LSB 0 +#define MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001 +#define MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_RX_ORDER_MASK) >> MBOX_DMA_POLICY_RX_ORDER_LSB) +#define MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_RX_ORDER_LSB) & MBOX_DMA_POLICY_RX_ORDER_MASK) + +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c +#define MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c +#define MBOX0_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX0_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> MBOX0_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_RESUME_LSB) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX0_DMA_RX_CONTROL_START_MSB 1 +#define MBOX0_DMA_RX_CONTROL_START_LSB 1 +#define MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_START_MASK) >> MBOX0_DMA_RX_CONTROL_START_LSB) +#define MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_START_LSB) & MBOX0_DMA_RX_CONTROL_START_MASK) +#define MBOX0_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX0_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_STOP_MASK) >> MBOX0_DMA_RX_CONTROL_STOP_LSB) +#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_STOP_LSB) & MBOX0_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024 +#define MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024 +#define MBOX0_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX0_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> MBOX0_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_RESUME_LSB) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX0_DMA_TX_CONTROL_START_MSB 1 +#define MBOX0_DMA_TX_CONTROL_START_LSB 1 +#define MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_START_MASK) >> MBOX0_DMA_TX_CONTROL_START_LSB) +#define MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_START_LSB) & MBOX0_DMA_TX_CONTROL_START_MASK) +#define MBOX0_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX0_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_STOP_MASK) >> MBOX0_DMA_TX_CONTROL_STOP_LSB) +#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_STOP_LSB) & MBOX0_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c +#define MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c +#define MBOX1_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX1_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> MBOX1_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_RESUME_LSB) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX1_DMA_RX_CONTROL_START_MSB 1 +#define MBOX1_DMA_RX_CONTROL_START_LSB 1 +#define MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_START_MASK) >> MBOX1_DMA_RX_CONTROL_START_LSB) +#define MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_START_LSB) & MBOX1_DMA_RX_CONTROL_START_MASK) +#define MBOX1_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX1_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_STOP_MASK) >> MBOX1_DMA_RX_CONTROL_STOP_LSB) +#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_STOP_LSB) & MBOX1_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034 +#define MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034 +#define MBOX1_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX1_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> MBOX1_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_RESUME_LSB) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX1_DMA_TX_CONTROL_START_MSB 1 +#define MBOX1_DMA_TX_CONTROL_START_LSB 1 +#define MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_START_MASK) >> MBOX1_DMA_TX_CONTROL_START_LSB) +#define MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_START_LSB) & MBOX1_DMA_TX_CONTROL_START_MASK) +#define MBOX1_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX1_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_STOP_MASK) >> MBOX1_DMA_TX_CONTROL_STOP_LSB) +#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_STOP_LSB) & MBOX1_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c +#define MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c +#define MBOX2_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX2_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> MBOX2_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_RESUME_LSB) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX2_DMA_RX_CONTROL_START_MSB 1 +#define MBOX2_DMA_RX_CONTROL_START_LSB 1 +#define MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_START_MASK) >> MBOX2_DMA_RX_CONTROL_START_LSB) +#define MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_START_LSB) & MBOX2_DMA_RX_CONTROL_START_MASK) +#define MBOX2_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX2_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_STOP_MASK) >> MBOX2_DMA_RX_CONTROL_STOP_LSB) +#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_STOP_LSB) & MBOX2_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044 +#define MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044 +#define MBOX2_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX2_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> MBOX2_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_RESUME_LSB) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX2_DMA_TX_CONTROL_START_MSB 1 +#define MBOX2_DMA_TX_CONTROL_START_LSB 1 +#define MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_START_MASK) >> MBOX2_DMA_TX_CONTROL_START_LSB) +#define MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_START_LSB) & MBOX2_DMA_TX_CONTROL_START_MASK) +#define MBOX2_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX2_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_STOP_MASK) >> MBOX2_DMA_TX_CONTROL_STOP_LSB) +#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_STOP_LSB) & MBOX2_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c +#define MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c +#define MBOX3_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX3_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> MBOX3_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_RESUME_LSB) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX3_DMA_RX_CONTROL_START_MSB 1 +#define MBOX3_DMA_RX_CONTROL_START_LSB 1 +#define MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_START_MASK) >> MBOX3_DMA_RX_CONTROL_START_LSB) +#define MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_START_LSB) & MBOX3_DMA_RX_CONTROL_START_MASK) +#define MBOX3_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX3_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_STOP_MASK) >> MBOX3_DMA_RX_CONTROL_STOP_LSB) +#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_STOP_LSB) & MBOX3_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054 +#define MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054 +#define MBOX3_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX3_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> MBOX3_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_RESUME_LSB) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX3_DMA_TX_CONTROL_START_MSB 1 +#define MBOX3_DMA_TX_CONTROL_START_LSB 1 +#define MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_START_MASK) >> MBOX3_DMA_TX_CONTROL_START_LSB) +#define MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_START_LSB) & MBOX3_DMA_TX_CONTROL_START_MASK) +#define MBOX3_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX3_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_STOP_MASK) >> MBOX3_DMA_TX_CONTROL_STOP_LSB) +#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_STOP_LSB) & MBOX3_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX_INT_STATUS_ADDRESS 0x00000058 +#define MBOX_INT_STATUS_OFFSET 0x00000058 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_OVERFLOW_MSB 17 +#define MBOX_INT_STATUS_TX_OVERFLOW_LSB 17 +#define MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000 +#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> MBOX_INT_STATUS_TX_OVERFLOW_LSB) +#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_STATUS_TX_OVERFLOW_LSB) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) +#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16 +#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16 +#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000 +#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> MBOX_INT_STATUS_RX_UNDERFLOW_LSB) +#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) +#define MBOX_INT_STATUS_RX_NOT_FULL_MSB 11 +#define MBOX_INT_STATUS_RX_NOT_FULL_LSB 8 +#define MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00 +#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> MBOX_INT_STATUS_RX_NOT_FULL_LSB) +#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_STATUS_RX_NOT_FULL_LSB) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) +#define MBOX_INT_STATUS_HOST_MSB 7 +#define MBOX_INT_STATUS_HOST_LSB 0 +#define MBOX_INT_STATUS_HOST_MASK 0x000000ff +#define MBOX_INT_STATUS_HOST_GET(x) (((x) & MBOX_INT_STATUS_HOST_MASK) >> MBOX_INT_STATUS_HOST_LSB) +#define MBOX_INT_STATUS_HOST_SET(x) (((x) << MBOX_INT_STATUS_HOST_LSB) & MBOX_INT_STATUS_HOST_MASK) + +#define MBOX_INT_ENABLE_ADDRESS 0x0000005c +#define MBOX_INT_ENABLE_OFFSET 0x0000005c +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17 +#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17 +#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000 +#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> MBOX_INT_ENABLE_TX_OVERFLOW_LSB) +#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) +#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11 +#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8 +#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00 +#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> MBOX_INT_ENABLE_RX_NOT_FULL_LSB) +#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) +#define MBOX_INT_ENABLE_HOST_MSB 7 +#define MBOX_INT_ENABLE_HOST_LSB 0 +#define MBOX_INT_ENABLE_HOST_MASK 0x000000ff +#define MBOX_INT_ENABLE_HOST_GET(x) (((x) & MBOX_INT_ENABLE_HOST_MASK) >> MBOX_INT_ENABLE_HOST_LSB) +#define MBOX_INT_ENABLE_HOST_SET(x) (((x) << MBOX_INT_ENABLE_HOST_LSB) & MBOX_INT_ENABLE_HOST_MASK) + +#define INT_HOST_ADDRESS 0x00000060 +#define INT_HOST_OFFSET 0x00000060 +#define INT_HOST_VECTOR_MSB 7 +#define INT_HOST_VECTOR_LSB 0 +#define INT_HOST_VECTOR_MASK 0x000000ff +#define INT_HOST_VECTOR_GET(x) (((x) & INT_HOST_VECTOR_MASK) >> INT_HOST_VECTOR_LSB) +#define INT_HOST_VECTOR_SET(x) (((x) << INT_HOST_VECTOR_LSB) & INT_HOST_VECTOR_MASK) + +#define LOCAL_COUNT_ADDRESS 0x00000080 +#define LOCAL_COUNT_OFFSET 0x00000080 +#define LOCAL_COUNT_VALUE_MSB 7 +#define LOCAL_COUNT_VALUE_LSB 0 +#define LOCAL_COUNT_VALUE_MASK 0x000000ff +#define LOCAL_COUNT_VALUE_GET(x) (((x) & LOCAL_COUNT_VALUE_MASK) >> LOCAL_COUNT_VALUE_LSB) +#define LOCAL_COUNT_VALUE_SET(x) (((x) << LOCAL_COUNT_VALUE_LSB) & LOCAL_COUNT_VALUE_MASK) + +#define COUNT_INC_ADDRESS 0x000000a0 +#define COUNT_INC_OFFSET 0x000000a0 +#define COUNT_INC_VALUE_MSB 7 +#define COUNT_INC_VALUE_LSB 0 +#define COUNT_INC_VALUE_MASK 0x000000ff +#define COUNT_INC_VALUE_GET(x) (((x) & COUNT_INC_VALUE_MASK) >> COUNT_INC_VALUE_LSB) +#define COUNT_INC_VALUE_SET(x) (((x) << COUNT_INC_VALUE_LSB) & COUNT_INC_VALUE_MASK) + +#define LOCAL_SCRATCH_ADDRESS 0x000000c0 +#define LOCAL_SCRATCH_OFFSET 0x000000c0 +#define LOCAL_SCRATCH_VALUE_MSB 7 +#define LOCAL_SCRATCH_VALUE_LSB 0 +#define LOCAL_SCRATCH_VALUE_MASK 0x000000ff +#define LOCAL_SCRATCH_VALUE_GET(x) (((x) & LOCAL_SCRATCH_VALUE_MASK) >> LOCAL_SCRATCH_VALUE_LSB) +#define LOCAL_SCRATCH_VALUE_SET(x) (((x) << LOCAL_SCRATCH_VALUE_LSB) & LOCAL_SCRATCH_VALUE_MASK) + +#define USE_LOCAL_BUS_ADDRESS 0x000000e0 +#define USE_LOCAL_BUS_OFFSET 0x000000e0 +#define USE_LOCAL_BUS_PIN_INIT_MSB 0 +#define USE_LOCAL_BUS_PIN_INIT_LSB 0 +#define USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001 +#define USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & USE_LOCAL_BUS_PIN_INIT_MASK) >> USE_LOCAL_BUS_PIN_INIT_LSB) +#define USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << USE_LOCAL_BUS_PIN_INIT_LSB) & USE_LOCAL_BUS_PIN_INIT_MASK) + +#define SDIO_CONFIG_ADDRESS 0x000000e4 +#define SDIO_CONFIG_OFFSET 0x000000e4 +#define SDIO_CONFIG_CCCR_IOR1_MSB 0 +#define SDIO_CONFIG_CCCR_IOR1_LSB 0 +#define SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001 +#define SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & SDIO_CONFIG_CCCR_IOR1_MASK) >> SDIO_CONFIG_CCCR_IOR1_LSB) +#define SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << SDIO_CONFIG_CCCR_IOR1_LSB) & SDIO_CONFIG_CCCR_IOR1_MASK) + +#define MBOX_DEBUG_ADDRESS 0x000000e8 +#define MBOX_DEBUG_OFFSET 0x000000e8 +#define MBOX_DEBUG_SEL_MSB 2 +#define MBOX_DEBUG_SEL_LSB 0 +#define MBOX_DEBUG_SEL_MASK 0x00000007 +#define MBOX_DEBUG_SEL_GET(x) (((x) & MBOX_DEBUG_SEL_MASK) >> MBOX_DEBUG_SEL_LSB) +#define MBOX_DEBUG_SEL_SET(x) (((x) << MBOX_DEBUG_SEL_LSB) & MBOX_DEBUG_SEL_MASK) + +#define MBOX_FIFO_RESET_ADDRESS 0x000000ec +#define MBOX_FIFO_RESET_OFFSET 0x000000ec +#define MBOX_FIFO_RESET_INIT_MSB 0 +#define MBOX_FIFO_RESET_INIT_LSB 0 +#define MBOX_FIFO_RESET_INIT_MASK 0x00000001 +#define MBOX_FIFO_RESET_INIT_GET(x) (((x) & MBOX_FIFO_RESET_INIT_MASK) >> MBOX_FIFO_RESET_INIT_LSB) +#define MBOX_FIFO_RESET_INIT_SET(x) (((x) << MBOX_FIFO_RESET_INIT_LSB) & MBOX_FIFO_RESET_INIT_MASK) + +#define MBOX_TXFIFO_POP_ADDRESS 0x000000f0 +#define MBOX_TXFIFO_POP_OFFSET 0x000000f0 +#define MBOX_TXFIFO_POP_DATA_MSB 0 +#define MBOX_TXFIFO_POP_DATA_LSB 0 +#define MBOX_TXFIFO_POP_DATA_MASK 0x00000001 +#define MBOX_TXFIFO_POP_DATA_GET(x) (((x) & MBOX_TXFIFO_POP_DATA_MASK) >> MBOX_TXFIFO_POP_DATA_LSB) +#define MBOX_TXFIFO_POP_DATA_SET(x) (((x) << MBOX_TXFIFO_POP_DATA_LSB) & MBOX_TXFIFO_POP_DATA_MASK) + +#define MBOX_RXFIFO_POP_ADDRESS 0x00000100 +#define MBOX_RXFIFO_POP_OFFSET 0x00000100 +#define MBOX_RXFIFO_POP_DATA_MSB 0 +#define MBOX_RXFIFO_POP_DATA_LSB 0 +#define MBOX_RXFIFO_POP_DATA_MASK 0x00000001 +#define MBOX_RXFIFO_POP_DATA_GET(x) (((x) & MBOX_RXFIFO_POP_DATA_MASK) >> MBOX_RXFIFO_POP_DATA_LSB) +#define MBOX_RXFIFO_POP_DATA_SET(x) (((x) << MBOX_RXFIFO_POP_DATA_LSB) & MBOX_RXFIFO_POP_DATA_MASK) + +#define SDIO_DEBUG_ADDRESS 0x00000110 +#define SDIO_DEBUG_OFFSET 0x00000110 +#define SDIO_DEBUG_SEL_MSB 3 +#define SDIO_DEBUG_SEL_LSB 0 +#define SDIO_DEBUG_SEL_MASK 0x0000000f +#define SDIO_DEBUG_SEL_GET(x) (((x) & SDIO_DEBUG_SEL_MASK) >> SDIO_DEBUG_SEL_LSB) +#define SDIO_DEBUG_SEL_SET(x) (((x) << SDIO_DEBUG_SEL_LSB) & SDIO_DEBUG_SEL_MASK) + +#define HOST_IF_WINDOW_ADDRESS 0x00002000 +#define HOST_IF_WINDOW_OFFSET 0x00002000 +#define HOST_IF_WINDOW_DATA_MSB 7 +#define HOST_IF_WINDOW_DATA_LSB 0 +#define HOST_IF_WINDOW_DATA_MASK 0x000000ff +#define HOST_IF_WINDOW_DATA_GET(x) (((x) & HOST_IF_WINDOW_DATA_MASK) >> HOST_IF_WINDOW_DATA_LSB) +#define HOST_IF_WINDOW_DATA_SET(x) (((x) << HOST_IF_WINDOW_DATA_LSB) & HOST_IF_WINDOW_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mbox_reg_reg_s { + volatile unsigned int mbox_fifo[4]; + volatile unsigned int mbox_fifo_status; + volatile unsigned int mbox_dma_policy; + volatile unsigned int mbox0_dma_rx_descriptor_base; + volatile unsigned int mbox0_dma_rx_control; + volatile unsigned int mbox0_dma_tx_descriptor_base; + volatile unsigned int mbox0_dma_tx_control; + volatile unsigned int mbox1_dma_rx_descriptor_base; + volatile unsigned int mbox1_dma_rx_control; + volatile unsigned int mbox1_dma_tx_descriptor_base; + volatile unsigned int mbox1_dma_tx_control; + volatile unsigned int mbox2_dma_rx_descriptor_base; + volatile unsigned int mbox2_dma_rx_control; + volatile unsigned int mbox2_dma_tx_descriptor_base; + volatile unsigned int mbox2_dma_tx_control; + volatile unsigned int mbox3_dma_rx_descriptor_base; + volatile unsigned int mbox3_dma_rx_control; + volatile unsigned int mbox3_dma_tx_descriptor_base; + volatile unsigned int mbox3_dma_tx_control; + volatile unsigned int mbox_int_status; + volatile unsigned int mbox_int_enable; + volatile unsigned int int_host; + unsigned char pad0[28]; /* pad to 0x80 */ + volatile unsigned int local_count[8]; + volatile unsigned int count_inc[8]; + volatile unsigned int local_scratch[8]; + volatile unsigned int use_local_bus; + volatile unsigned int sdio_config; + volatile unsigned int mbox_debug; + volatile unsigned int mbox_fifo_reset; + volatile unsigned int mbox_txfifo_pop[4]; + volatile unsigned int mbox_rxfifo_pop[4]; + volatile unsigned int sdio_debug; + unsigned char pad1[7916]; /* pad to 0x2000 */ + volatile unsigned int host_if_window[2048]; +} mbox_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/miscdrv.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/miscdrv.h --- linux-2.6.26/drivers/net/wireless/ath6k22/miscdrv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/miscdrv.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,44 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _MISCDRV_H +#define _MISCDRV_H + + +#define HOST_INTEREST_ITEM_ADDRESS(target, item) \ +(((target) == TARGET_TYPE_AR6001) ? \ + AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \ + AR6002_HOST_INTEREST_ITEM_ADDRESS(item)) + +A_UINT32 ar6kRev2Array[][128] = { + {0xFFFF, 0xFFFF}, // No Patches + }; + +#define CFG_REV2_ITEMS 0 // no patches so far +#define AR6K_RESET_ADDR 0x4000 +#define AR6K_RESET_VAL 0x100 + +#define EEPROM_SZ 768 +#define EEPROM_WAIT_LIMIT 4 + +#endif + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/netbuf.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/netbuf.c --- linux-2.6.26/drivers/net/wireless/ath6k22/netbuf.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/netbuf.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,229 @@ + +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ +#include +#include +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "htc_packet.h" + +#define AR6000_DATA_OFFSET 64 + +void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt) +{ + skb_queue_tail((struct sk_buff_head *) q, (struct sk_buff *) pkt); +} + +void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt) +{ + skb_queue_head((struct sk_buff_head *) q, (struct sk_buff *) pkt); +} + +void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q) +{ + return((void *) skb_dequeue((struct sk_buff_head *) q)); +} + +int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q) +{ + return(skb_queue_len((struct sk_buff_head *) q)); +} + +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q) +{ + return(skb_queue_empty((struct sk_buff_head *) q)); +} + +void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q) +{ + skb_queue_head_init((struct sk_buff_head *) q); +} + +void * +a_netbuf_alloc(int size) +{ + struct sk_buff *skb; + skb = dev_alloc_skb(AR6000_DATA_OFFSET + sizeof(HTC_PACKET) + size); + skb_reserve(skb, AR6000_DATA_OFFSET + sizeof(HTC_PACKET)); + return ((void *)skb); +} + +/* + * Allocate an SKB w.o. any encapsulation requirement. + */ +void * +a_netbuf_alloc_raw(int size) +{ + struct sk_buff *skb; + + skb = dev_alloc_skb(size); + + return ((void *)skb); +} + +void +a_netbuf_free(void *bufPtr) +{ + struct sk_buff *skb = (struct sk_buff *)bufPtr; + + dev_kfree_skb(skb); +} + +A_UINT32 +a_netbuf_to_len(void *bufPtr) +{ + return (((struct sk_buff *)bufPtr)->len); +} + +void * +a_netbuf_to_data(void *bufPtr) +{ + return (((struct sk_buff *)bufPtr)->data); +} + +/* + * Add len # of bytes to the beginning of the network buffer + * pointed to by bufPtr + */ +A_STATUS +a_netbuf_push(void *bufPtr, A_INT32 len) +{ + skb_push((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Add len # of bytes to the beginning of the network buffer + * pointed to by bufPtr and also fill with data + */ +A_STATUS +a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len) +{ + skb_push((struct sk_buff *) bufPtr, len); + A_MEMCPY(((struct sk_buff *)bufPtr)->data, srcPtr, len); + + return A_OK; +} + +/* + * Add len # of bytes to the end of the network buffer + * pointed to by bufPtr + */ +A_STATUS +a_netbuf_put(void *bufPtr, A_INT32 len) +{ + skb_put((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Add len # of bytes to the end of the network buffer + * pointed to by bufPtr and also fill with data + */ +A_STATUS +a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len) +{ + char *start = ((struct sk_buff *)bufPtr)->data + + ((struct sk_buff *)bufPtr)->len; + skb_put((struct sk_buff *)bufPtr, len); + A_MEMCPY(start, srcPtr, len); + + return A_OK; +} + + +/* + * Trim the network buffer pointed to by bufPtr to len # of bytes + */ +A_STATUS +a_netbuf_setlen(void *bufPtr, A_INT32 len) +{ + skb_trim((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Chop of len # of bytes from the end of the buffer. + */ +A_STATUS +a_netbuf_trim(void *bufPtr, A_INT32 len) +{ + skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len); + + return A_OK; +} + +/* + * Chop of len # of bytes from the end of the buffer and return the data. + */ +A_STATUS +a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len) +{ + char *start = ((struct sk_buff *)bufPtr)->data + + (((struct sk_buff *)bufPtr)->len - len); + + A_MEMCPY(dstPtr, start, len); + skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len); + + return A_OK; +} + + +/* + * Returns the number of bytes available to a a_netbuf_push() + */ +A_INT32 +a_netbuf_headroom(void *bufPtr) +{ + return (skb_headroom((struct sk_buff *)bufPtr)); +} + +/* + * Removes specified number of bytes from the beginning of the buffer + */ +A_STATUS +a_netbuf_pull(void *bufPtr, A_INT32 len) +{ + skb_pull((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Removes specified number of bytes from the beginning of the buffer + * and return the data + */ +A_STATUS +a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len) +{ + A_MEMCPY(dstPtr, ((struct sk_buff *)bufPtr)->data, len); + skb_pull((struct sk_buff *)bufPtr, len); + + return A_OK; +} + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/osapi_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/osapi_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k22/osapi_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/osapi_linux.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,333 @@ +/* + * $Id: //depot/sw/releases/olca2.2/host/os/linux/include/osapi_linux.h#1 $ + * + * This file contains the definitions of the basic atheros data types. + * It is used to map the data types in atheros files to a platform specific + * type. + * + * Copyright 2003-2005 Atheros Communications, Inc., All Rights Reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _OSAPI_LINUX_H_ +#define _OSAPI_LINUX_H_ + +#ifdef __KERNEL__ + +#include +#include +#include +#include +#include +#include +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +#include +#endif +#include +#include +#include +#ifdef KERNEL_2_4 +#include +#include +#endif + +#ifdef __GNUC__ +#define __ATTRIB_PACK __attribute__ ((packed)) +#define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2))) +#define __ATTRIB_NORETURN __attribute__ ((noreturn)) +#ifndef INLINE +#define INLINE __inline__ +#endif +#else /* Not GCC */ +#define __ATTRIB_PACK +#define __ATTRIB_PRINTF +#define __ATTRIB_NORETURN +#ifndef INLINE +#define INLINE __inline +#endif +#endif /* End __GNUC__ */ + +#define PREPACK +#define POSTPACK __ATTRIB_PACK + +/* + * Endianes macros + */ +#define A_BE2CPU8(x) ntohb(x) +#define A_BE2CPU16(x) ntohs(x) +#define A_BE2CPU32(x) ntohl(x) + +#define A_LE2CPU8(x) (x) +#define A_LE2CPU16(x) (x) +#define A_LE2CPU32(x) (x) + +#define A_CPU2BE8(x) htonb(x) +#define A_CPU2BE16(x) htons(x) +#define A_CPU2BE32(x) htonl(x) + +#define A_MEMCPY(dst, src, len) memcpy((A_UINT8 *)(dst), (src), (len)) +#define A_MEMZERO(addr, len) memset(addr, 0, len) +#define A_MEMCMP(addr1, addr2, len) memcmp((addr1), (addr2), (len)) +#define A_MALLOC(size) kmalloc((size), GFP_KERNEL) +#define A_MALLOC_NOWAIT(size) kmalloc((size), GFP_ATOMIC) +#define A_FREE(addr) kfree(addr) +#define A_PRINTF(args...) printk(args) +#define A_SPRINTF(buf, args...) sprintf (buf, args) + +/* Mutual Exclusion */ +typedef spinlock_t A_MUTEX_T; +#define A_MUTEX_INIT(mutex) spin_lock_init(mutex) +#define A_MUTEX_LOCK(mutex) spin_lock_bh(mutex) +#define A_MUTEX_UNLOCK(mutex) spin_unlock_bh(mutex) +#define A_IS_MUTEX_VALID(mutex) TRUE /* okay to return true, since A_MUTEX_DELETE does nothing */ +#define A_MUTEX_DELETE(mutex) /* spin locks are not kernel resources so nothing to free.. */ + +/* Get current time in ms adding a constant offset (in ms) */ +#define A_GET_MS(offset) \ + (jiffies + ((offset) / 1000) * HZ) + +/* + * Timer Functions + */ +#define A_MDELAY(msecs) mdelay(msecs) +typedef struct timer_list A_TIMER; + +#define A_INIT_TIMER(pTimer, pFunction, pArg) do { \ + init_timer(pTimer); \ + (pTimer)->function = (pFunction); \ + (pTimer)->data = (unsigned long)(pArg); \ +} while (0) + +/* + * Start a Timer that elapses after 'periodMSec' milli-seconds + * Support is provided for a one-shot timer. The 'repeatFlag' is + * ignored. + */ +#define A_TIMEOUT_MS(pTimer, periodMSec, repeatFlag) do { \ + if (repeatFlag) { \ + printk("\n" __FILE__ ":%d: Timer Repeat requested\n",__LINE__); \ + panic("Timer Repeat"); \ + } \ + mod_timer((pTimer), jiffies + HZ * (periodMSec) / 1000); \ +} while (0) + +/* + * Cancel the Timer. + */ +#define A_UNTIMEOUT(pTimer) do { \ + del_timer((pTimer)); \ +} while (0) + +#define A_DELETE_TIMER(pTimer) do { \ +} while (0) + +/* + * Wait Queue related functions + */ +typedef wait_queue_head_t A_WAITQUEUE_HEAD; +#define A_INIT_WAITQUEUE_HEAD(head) init_waitqueue_head(head) +#ifndef wait_event_interruptible_timeout +#define __wait_event_interruptible_timeout(wq, condition, ret) \ +do { \ + wait_queue_t __wait; \ + init_waitqueue_entry(&__wait, current); \ + \ + add_wait_queue(&wq, &__wait); \ + for (;;) { \ + set_current_state(TASK_INTERRUPTIBLE); \ + if (condition) \ + break; \ + if (!signal_pending(current)) { \ + ret = schedule_timeout(ret); \ + if (!ret) \ + break; \ + continue; \ + } \ + ret = -ERESTARTSYS; \ + break; \ + } \ + current->state = TASK_RUNNING; \ + remove_wait_queue(&wq, &__wait); \ +} while (0) + +#define wait_event_interruptible_timeout(wq, condition, timeout) \ +({ \ + long __ret = timeout; \ + if (!(condition)) \ + __wait_event_interruptible_timeout(wq, condition, __ret); \ + __ret; \ +}) +#endif /* wait_event_interruptible_timeout */ + +#define A_WAIT_EVENT_INTERRUPTIBLE_TIMEOUT(head, condition, timeout) do { \ + wait_event_interruptible_timeout(head, condition, timeout); \ +} while (0) + +#define A_WAKE_UP(head) wake_up(head) + +#ifdef DEBUG +#define A_ASSERT(expr) \ + if (!(expr)) { \ + printk(KERN_ALERT "\n" __FILE__ ":%d: Assertion " #expr " failed!\n",__LINE__); \ + panic(#expr); \ + } + +#else +#define A_ASSERT(expr) +#endif /* DEBUG */ + +/* + * Initialization of the network buffer subsystem + */ +#define A_NETBUF_INIT() + +/* + * Network buffer queue support + */ +typedef struct sk_buff_head A_NETBUF_QUEUE_T; + +#define A_NETBUF_QUEUE_INIT(q) \ + a_netbuf_queue_init(q) + +#define A_NETBUF_ENQUEUE(q, pkt) \ + a_netbuf_enqueue((q), (pkt)) +#define A_NETBUF_PREQUEUE(q, pkt) \ + a_netbuf_prequeue((q), (pkt)) +#define A_NETBUF_DEQUEUE(q) \ + (a_netbuf_dequeue(q)) +#define A_NETBUF_QUEUE_SIZE(q) \ + a_netbuf_queue_size(q) +#define A_NETBUF_QUEUE_EMPTY(q) \ + a_netbuf_queue_empty(q) + +/* + * Network buffer support + */ +#define A_NETBUF_ALLOC(size) \ + a_netbuf_alloc(size) +#define A_NETBUF_ALLOC_RAW(size) \ + a_netbuf_alloc_raw(size) +#define A_NETBUF_FREE(bufPtr) \ + a_netbuf_free(bufPtr) +#define A_NETBUF_DATA(bufPtr) \ + a_netbuf_to_data(bufPtr) +#define A_NETBUF_LEN(bufPtr) \ + a_netbuf_to_len(bufPtr) +#define A_NETBUF_PUSH(bufPtr, len) \ + a_netbuf_push(bufPtr, len) +#define A_NETBUF_PUT(bufPtr, len) \ + a_netbuf_put(bufPtr, len) +#define A_NETBUF_TRIM(bufPtr,len) \ + a_netbuf_trim(bufPtr, len) +#define A_NETBUF_PULL(bufPtr, len) \ + a_netbuf_pull(bufPtr, len) +#define A_NETBUF_HEADROOM(bufPtr)\ + a_netbuf_headroom(bufPtr) +#define A_NETBUF_SETLEN(bufPtr,len) \ + a_netbuf_setlen(bufPtr, len) + +/* Add data to end of a buffer */ +#define A_NETBUF_PUT_DATA(bufPtr, srcPtr, len) \ + a_netbuf_put_data(bufPtr, srcPtr, len) + +/* Add data to start of the buffer */ +#define A_NETBUF_PUSH_DATA(bufPtr, srcPtr, len) \ + a_netbuf_push_data(bufPtr, srcPtr, len) + +/* Remove data at start of the buffer */ +#define A_NETBUF_PULL_DATA(bufPtr, dstPtr, len) \ + a_netbuf_pull_data(bufPtr, dstPtr, len) + +/* Remove data from the end of the buffer */ +#define A_NETBUF_TRIM_DATA(bufPtr, dstPtr, len) \ + a_netbuf_trim_data(bufPtr, dstPtr, len) + +/* View data as "size" contiguous bytes of type "t" */ +#define A_NETBUF_VIEW_DATA(bufPtr, t, size) \ + (t )( ((struct skbuf *)(bufPtr))->data) + +/* return the beginning of the headroom for the buffer */ +#define A_NETBUF_HEAD(bufPtr) \ + ((((struct sk_buff *)(bufPtr))->head)) + +/* + * OS specific network buffer access routines + */ +void *a_netbuf_alloc(int size); +void *a_netbuf_alloc_raw(int size); +void a_netbuf_free(void *bufPtr); +void *a_netbuf_to_data(void *bufPtr); +A_UINT32 a_netbuf_to_len(void *bufPtr); +A_STATUS a_netbuf_push(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len); +A_STATUS a_netbuf_put(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len); +A_STATUS a_netbuf_pull(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len); +A_STATUS a_netbuf_trim(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len); +A_STATUS a_netbuf_setlen(void *bufPtr, A_INT32 len); +A_INT32 a_netbuf_headroom(void *bufPtr); +void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt); +void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt); +void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q); +int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q); +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q); +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q); +void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q); + +/* + * Kernel v.s User space functions + */ +A_UINT32 a_copy_to_user(void *to, const void *from, A_UINT32 n); +A_UINT32 a_copy_from_user(void *to, const void *from, A_UINT32 n); + +/* In linux, WLAN Rx and Tx run in different contexts, so no need to check + * for any commands/data queued for WLAN */ +#define A_CHECK_DRV_TX() + +#else /* __KERNEL__ */ + +#ifdef __GNUC__ +#define __ATTRIB_PACK __attribute__ ((packed)) +#define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2))) +#define __ATTRIB_NORETURN __attribute__ ((noreturn)) +#ifndef INLINE +#define INLINE __inline__ +#endif +#else /* Not GCC */ +#define __ATTRIB_PACK +#define __ATTRIB_PRINTF +#define __ATTRIB_NORETURN +#ifndef INLINE +#define INLINE __inline +#endif +#endif /* End __GNUC__ */ + +#define PREPACK +#define POSTPACK __ATTRIB_PACK + +#define A_MEMCPY(dst, src, len) memcpy((dst), (src), (len)) +#define A_MEMZERO(addr, len) memset((addr), 0, (len)) +#define A_MEMCMP(addr1, addr2, len) memcmp((addr1), (addr2), (len)) +#define A_MALLOC(size) malloc(size) +#define A_FREE(addr) free(addr) +#endif /* __KERNEL__ */ + +#endif /* _OSAPI_LINUX_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/regDb.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/regDb.h --- linux-2.6.26/drivers/net/wireless/ath6k22/regDb.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/regDb.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,30 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2005 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __REG_DB_H__ +#define __REG_DB_H__ + +#include "./regulatory/reg_dbschema.h" +#include "./regulatory/reg_dbvalues.h" + +#endif /* __REG_DB_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/regdump.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/regdump.h --- linux-2.6.26/drivers/net/wireless/ath6k22/regdump.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/regdump.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,49 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __REGDUMP_H__ +#define __REGDUMP_H__ +#if defined(AR6001) +#include "AR6001/AR6001_regdump.h" +#endif +#if defined(AR6002) +#include "AR6002/AR6002_regdump.h" +#endif + +#if !defined(__ASSEMBLER__) +/* + * Target CPU state at the time of failure is reflected + * in a register dump, which the Host can fetch through + * the diagnostic window. + */ +struct register_dump_s { + A_UINT32 target_id; /* Target ID */ + A_UINT32 assline; /* Line number (if assertion failure) */ + A_UINT32 pc; /* Program Counter at time of exception */ + A_UINT32 badvaddr; /* Virtual address causing exception */ + CPU_exception_frame_t exc_frame; /* CPU-specific exception info */ + + /* Could copy top of stack here, too.... */ +}; +#endif /* __ASSEMBLER__ */ +#endif /* __REGDUMP_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/roaming.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/roaming.h --- linux-2.6.26/drivers/net/wireless/ath6k22/roaming.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/roaming.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,41 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _ROAMING_H_ +#define _ROAMING_H_ + +/* + * The signal quality could be in terms of either snr or rssi. We should + * have an enum for both of them. For the time being, we are going to move + * it to wmi.h that is shared by both host and the target, since we are + * repartitioning the code to the host + */ +#define SIGNAL_QUALITY_NOISE_FLOOR -96 +#define SIGNAL_QUALITY_METRICS_NUM_MAX 2 +typedef enum { + SIGNAL_QUALITY_METRICS_SNR = 0, + SIGNAL_QUALITY_METRICS_RSSI, + SIGNAL_QUALITY_METRICS_ALL, +} SIGNAL_QUALITY_METRICS_TYPE; + +#endif /* _ROAMING_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/rtc_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/rtc_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k22/rtc_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/rtc_reg.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,1186 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _RTC_REG_REG_H_ +#define _RTC_REG_REG_H_ + +#define RESET_CONTROL_ADDRESS 0x00000000 +#define RESET_CONTROL_OFFSET 0x00000000 +#define RESET_CONTROL_CPU_INIT_RESET_MSB 11 +#define RESET_CONTROL_CPU_INIT_RESET_LSB 11 +#define RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800 +#define RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & RESET_CONTROL_CPU_INIT_RESET_MASK) >> RESET_CONTROL_CPU_INIT_RESET_LSB) +#define RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << RESET_CONTROL_CPU_INIT_RESET_LSB) & RESET_CONTROL_CPU_INIT_RESET_MASK) +#define RESET_CONTROL_VMC_REMAP_RESET_MSB 10 +#define RESET_CONTROL_VMC_REMAP_RESET_LSB 10 +#define RESET_CONTROL_VMC_REMAP_RESET_MASK 0x00000400 +#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) (((x) & RESET_CONTROL_VMC_REMAP_RESET_MASK) >> RESET_CONTROL_VMC_REMAP_RESET_LSB) +#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) (((x) << RESET_CONTROL_VMC_REMAP_RESET_LSB) & RESET_CONTROL_VMC_REMAP_RESET_MASK) +#define RESET_CONTROL_RST_OUT_MSB 9 +#define RESET_CONTROL_RST_OUT_LSB 9 +#define RESET_CONTROL_RST_OUT_MASK 0x00000200 +#define RESET_CONTROL_RST_OUT_GET(x) (((x) & RESET_CONTROL_RST_OUT_MASK) >> RESET_CONTROL_RST_OUT_LSB) +#define RESET_CONTROL_RST_OUT_SET(x) (((x) << RESET_CONTROL_RST_OUT_LSB) & RESET_CONTROL_RST_OUT_MASK) +#define RESET_CONTROL_COLD_RST_MSB 8 +#define RESET_CONTROL_COLD_RST_LSB 8 +#define RESET_CONTROL_COLD_RST_MASK 0x00000100 +#define RESET_CONTROL_COLD_RST_GET(x) (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB) +#define RESET_CONTROL_COLD_RST_SET(x) (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK) +#define RESET_CONTROL_WARM_RST_MSB 7 +#define RESET_CONTROL_WARM_RST_LSB 7 +#define RESET_CONTROL_WARM_RST_MASK 0x00000080 +#define RESET_CONTROL_WARM_RST_GET(x) (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB) +#define RESET_CONTROL_WARM_RST_SET(x) (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK) +#define RESET_CONTROL_CPU_WARM_RST_MSB 6 +#define RESET_CONTROL_CPU_WARM_RST_LSB 6 +#define RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 +#define RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & RESET_CONTROL_CPU_WARM_RST_MASK) >> RESET_CONTROL_CPU_WARM_RST_LSB) +#define RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << RESET_CONTROL_CPU_WARM_RST_LSB) & RESET_CONTROL_CPU_WARM_RST_MASK) +#define RESET_CONTROL_MAC_COLD_RST_MSB 5 +#define RESET_CONTROL_MAC_COLD_RST_LSB 5 +#define RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020 +#define RESET_CONTROL_MAC_COLD_RST_GET(x) (((x) & RESET_CONTROL_MAC_COLD_RST_MASK) >> RESET_CONTROL_MAC_COLD_RST_LSB) +#define RESET_CONTROL_MAC_COLD_RST_SET(x) (((x) << RESET_CONTROL_MAC_COLD_RST_LSB) & RESET_CONTROL_MAC_COLD_RST_MASK) +#define RESET_CONTROL_MAC_WARM_RST_MSB 4 +#define RESET_CONTROL_MAC_WARM_RST_LSB 4 +#define RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010 +#define RESET_CONTROL_MAC_WARM_RST_GET(x) (((x) & RESET_CONTROL_MAC_WARM_RST_MASK) >> RESET_CONTROL_MAC_WARM_RST_LSB) +#define RESET_CONTROL_MAC_WARM_RST_SET(x) (((x) << RESET_CONTROL_MAC_WARM_RST_LSB) & RESET_CONTROL_MAC_WARM_RST_MASK) +#define RESET_CONTROL_MBOX_RST_MSB 2 +#define RESET_CONTROL_MBOX_RST_LSB 2 +#define RESET_CONTROL_MBOX_RST_MASK 0x00000004 +#define RESET_CONTROL_MBOX_RST_GET(x) (((x) & RESET_CONTROL_MBOX_RST_MASK) >> RESET_CONTROL_MBOX_RST_LSB) +#define RESET_CONTROL_MBOX_RST_SET(x) (((x) << RESET_CONTROL_MBOX_RST_LSB) & RESET_CONTROL_MBOX_RST_MASK) +#define RESET_CONTROL_UART_RST_MSB 1 +#define RESET_CONTROL_UART_RST_LSB 1 +#define RESET_CONTROL_UART_RST_MASK 0x00000002 +#define RESET_CONTROL_UART_RST_GET(x) (((x) & RESET_CONTROL_UART_RST_MASK) >> RESET_CONTROL_UART_RST_LSB) +#define RESET_CONTROL_UART_RST_SET(x) (((x) << RESET_CONTROL_UART_RST_LSB) & RESET_CONTROL_UART_RST_MASK) +#define RESET_CONTROL_SI0_RST_MSB 0 +#define RESET_CONTROL_SI0_RST_LSB 0 +#define RESET_CONTROL_SI0_RST_MASK 0x00000001 +#define RESET_CONTROL_SI0_RST_GET(x) (((x) & RESET_CONTROL_SI0_RST_MASK) >> RESET_CONTROL_SI0_RST_LSB) +#define RESET_CONTROL_SI0_RST_SET(x) (((x) << RESET_CONTROL_SI0_RST_LSB) & RESET_CONTROL_SI0_RST_MASK) + +#define XTAL_CONTROL_ADDRESS 0x00000004 +#define XTAL_CONTROL_OFFSET 0x00000004 +#define XTAL_CONTROL_TCXO_MSB 0 +#define XTAL_CONTROL_TCXO_LSB 0 +#define XTAL_CONTROL_TCXO_MASK 0x00000001 +#define XTAL_CONTROL_TCXO_GET(x) (((x) & XTAL_CONTROL_TCXO_MASK) >> XTAL_CONTROL_TCXO_LSB) +#define XTAL_CONTROL_TCXO_SET(x) (((x) << XTAL_CONTROL_TCXO_LSB) & XTAL_CONTROL_TCXO_MASK) + +#define TCXO_DETECT_ADDRESS 0x00000008 +#define TCXO_DETECT_OFFSET 0x00000008 +#define TCXO_DETECT_PRESENT_MSB 0 +#define TCXO_DETECT_PRESENT_LSB 0 +#define TCXO_DETECT_PRESENT_MASK 0x00000001 +#define TCXO_DETECT_PRESENT_GET(x) (((x) & TCXO_DETECT_PRESENT_MASK) >> TCXO_DETECT_PRESENT_LSB) +#define TCXO_DETECT_PRESENT_SET(x) (((x) << TCXO_DETECT_PRESENT_LSB) & TCXO_DETECT_PRESENT_MASK) + +#define XTAL_TEST_ADDRESS 0x0000000c +#define XTAL_TEST_OFFSET 0x0000000c +#define XTAL_TEST_NOTCXODET_MSB 0 +#define XTAL_TEST_NOTCXODET_LSB 0 +#define XTAL_TEST_NOTCXODET_MASK 0x00000001 +#define XTAL_TEST_NOTCXODET_GET(x) (((x) & XTAL_TEST_NOTCXODET_MASK) >> XTAL_TEST_NOTCXODET_LSB) +#define XTAL_TEST_NOTCXODET_SET(x) (((x) << XTAL_TEST_NOTCXODET_LSB) & XTAL_TEST_NOTCXODET_MASK) + +#define QUADRATURE_ADDRESS 0x00000010 +#define QUADRATURE_OFFSET 0x00000010 +#define QUADRATURE_ADC_MSB 5 +#define QUADRATURE_ADC_LSB 4 +#define QUADRATURE_ADC_MASK 0x00000030 +#define QUADRATURE_ADC_GET(x) (((x) & QUADRATURE_ADC_MASK) >> QUADRATURE_ADC_LSB) +#define QUADRATURE_ADC_SET(x) (((x) << QUADRATURE_ADC_LSB) & QUADRATURE_ADC_MASK) +#define QUADRATURE_SEL_MSB 2 +#define QUADRATURE_SEL_LSB 2 +#define QUADRATURE_SEL_MASK 0x00000004 +#define QUADRATURE_SEL_GET(x) (((x) & QUADRATURE_SEL_MASK) >> QUADRATURE_SEL_LSB) +#define QUADRATURE_SEL_SET(x) (((x) << QUADRATURE_SEL_LSB) & QUADRATURE_SEL_MASK) +#define QUADRATURE_DAC_MSB 1 +#define QUADRATURE_DAC_LSB 0 +#define QUADRATURE_DAC_MASK 0x00000003 +#define QUADRATURE_DAC_GET(x) (((x) & QUADRATURE_DAC_MASK) >> QUADRATURE_DAC_LSB) +#define QUADRATURE_DAC_SET(x) (((x) << QUADRATURE_DAC_LSB) & QUADRATURE_DAC_MASK) + +#define PLL_CONTROL_ADDRESS 0x00000014 +#define PLL_CONTROL_OFFSET 0x00000014 +#define PLL_CONTROL_DIG_TEST_CLK_MSB 20 +#define PLL_CONTROL_DIG_TEST_CLK_LSB 20 +#define PLL_CONTROL_DIG_TEST_CLK_MASK 0x00100000 +#define PLL_CONTROL_DIG_TEST_CLK_GET(x) (((x) & PLL_CONTROL_DIG_TEST_CLK_MASK) >> PLL_CONTROL_DIG_TEST_CLK_LSB) +#define PLL_CONTROL_DIG_TEST_CLK_SET(x) (((x) << PLL_CONTROL_DIG_TEST_CLK_LSB) & PLL_CONTROL_DIG_TEST_CLK_MASK) +#define PLL_CONTROL_MAC_OVERRIDE_MSB 19 +#define PLL_CONTROL_MAC_OVERRIDE_LSB 19 +#define PLL_CONTROL_MAC_OVERRIDE_MASK 0x00080000 +#define PLL_CONTROL_MAC_OVERRIDE_GET(x) (((x) & PLL_CONTROL_MAC_OVERRIDE_MASK) >> PLL_CONTROL_MAC_OVERRIDE_LSB) +#define PLL_CONTROL_MAC_OVERRIDE_SET(x) (((x) << PLL_CONTROL_MAC_OVERRIDE_LSB) & PLL_CONTROL_MAC_OVERRIDE_MASK) +#define PLL_CONTROL_NOPWD_MSB 18 +#define PLL_CONTROL_NOPWD_LSB 18 +#define PLL_CONTROL_NOPWD_MASK 0x00040000 +#define PLL_CONTROL_NOPWD_GET(x) (((x) & PLL_CONTROL_NOPWD_MASK) >> PLL_CONTROL_NOPWD_LSB) +#define PLL_CONTROL_NOPWD_SET(x) (((x) << PLL_CONTROL_NOPWD_LSB) & PLL_CONTROL_NOPWD_MASK) +#define PLL_CONTROL_UPDATING_MSB 17 +#define PLL_CONTROL_UPDATING_LSB 17 +#define PLL_CONTROL_UPDATING_MASK 0x00020000 +#define PLL_CONTROL_UPDATING_GET(x) (((x) & PLL_CONTROL_UPDATING_MASK) >> PLL_CONTROL_UPDATING_LSB) +#define PLL_CONTROL_UPDATING_SET(x) (((x) << PLL_CONTROL_UPDATING_LSB) & PLL_CONTROL_UPDATING_MASK) +#define PLL_CONTROL_BYPASS_MSB 16 +#define PLL_CONTROL_BYPASS_LSB 16 +#define PLL_CONTROL_BYPASS_MASK 0x00010000 +#define PLL_CONTROL_BYPASS_GET(x) (((x) & PLL_CONTROL_BYPASS_MASK) >> PLL_CONTROL_BYPASS_LSB) +#define PLL_CONTROL_BYPASS_SET(x) (((x) << PLL_CONTROL_BYPASS_LSB) & PLL_CONTROL_BYPASS_MASK) +#define PLL_CONTROL_REFDIV_MSB 15 +#define PLL_CONTROL_REFDIV_LSB 12 +#define PLL_CONTROL_REFDIV_MASK 0x0000f000 +#define PLL_CONTROL_REFDIV_GET(x) (((x) & PLL_CONTROL_REFDIV_MASK) >> PLL_CONTROL_REFDIV_LSB) +#define PLL_CONTROL_REFDIV_SET(x) (((x) << PLL_CONTROL_REFDIV_LSB) & PLL_CONTROL_REFDIV_MASK) +#define PLL_CONTROL_DIV_MSB 9 +#define PLL_CONTROL_DIV_LSB 0 +#define PLL_CONTROL_DIV_MASK 0x000003ff +#define PLL_CONTROL_DIV_GET(x) (((x) & PLL_CONTROL_DIV_MASK) >> PLL_CONTROL_DIV_LSB) +#define PLL_CONTROL_DIV_SET(x) (((x) << PLL_CONTROL_DIV_LSB) & PLL_CONTROL_DIV_MASK) + +#define PLL_SETTLE_ADDRESS 0x00000018 +#define PLL_SETTLE_OFFSET 0x00000018 +#define PLL_SETTLE_TIME_MSB 11 +#define PLL_SETTLE_TIME_LSB 0 +#define PLL_SETTLE_TIME_MASK 0x00000fff +#define PLL_SETTLE_TIME_GET(x) (((x) & PLL_SETTLE_TIME_MASK) >> PLL_SETTLE_TIME_LSB) +#define PLL_SETTLE_TIME_SET(x) (((x) << PLL_SETTLE_TIME_LSB) & PLL_SETTLE_TIME_MASK) + +#define XTAL_SETTLE_ADDRESS 0x0000001c +#define XTAL_SETTLE_OFFSET 0x0000001c +#define XTAL_SETTLE_TIME_MSB 7 +#define XTAL_SETTLE_TIME_LSB 0 +#define XTAL_SETTLE_TIME_MASK 0x000000ff +#define XTAL_SETTLE_TIME_GET(x) (((x) & XTAL_SETTLE_TIME_MASK) >> XTAL_SETTLE_TIME_LSB) +#define XTAL_SETTLE_TIME_SET(x) (((x) << XTAL_SETTLE_TIME_LSB) & XTAL_SETTLE_TIME_MASK) + +#define CPU_CLOCK_ADDRESS 0x00000020 +#define CPU_CLOCK_OFFSET 0x00000020 +#define CPU_CLOCK_STANDARD_MSB 1 +#define CPU_CLOCK_STANDARD_LSB 0 +#define CPU_CLOCK_STANDARD_MASK 0x00000003 +#define CPU_CLOCK_STANDARD_GET(x) (((x) & CPU_CLOCK_STANDARD_MASK) >> CPU_CLOCK_STANDARD_LSB) +#define CPU_CLOCK_STANDARD_SET(x) (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK) + +#define CLOCK_OUT_ADDRESS 0x00000024 +#define CLOCK_OUT_OFFSET 0x00000024 +#define CLOCK_OUT_SELECT_MSB 3 +#define CLOCK_OUT_SELECT_LSB 0 +#define CLOCK_OUT_SELECT_MASK 0x0000000f +#define CLOCK_OUT_SELECT_GET(x) (((x) & CLOCK_OUT_SELECT_MASK) >> CLOCK_OUT_SELECT_LSB) +#define CLOCK_OUT_SELECT_SET(x) (((x) << CLOCK_OUT_SELECT_LSB) & CLOCK_OUT_SELECT_MASK) + +#define CLOCK_CONTROL_ADDRESS 0x00000028 +#define CLOCK_CONTROL_OFFSET 0x00000028 +#define CLOCK_CONTROL_LF_CLK32_MSB 2 +#define CLOCK_CONTROL_LF_CLK32_LSB 2 +#define CLOCK_CONTROL_LF_CLK32_MASK 0x00000004 +#define CLOCK_CONTROL_LF_CLK32_GET(x) (((x) & CLOCK_CONTROL_LF_CLK32_MASK) >> CLOCK_CONTROL_LF_CLK32_LSB) +#define CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << CLOCK_CONTROL_LF_CLK32_LSB) & CLOCK_CONTROL_LF_CLK32_MASK) +#define CLOCK_CONTROL_UART_CLK_MSB 1 +#define CLOCK_CONTROL_UART_CLK_LSB 1 +#define CLOCK_CONTROL_UART_CLK_MASK 0x00000002 +#define CLOCK_CONTROL_UART_CLK_GET(x) (((x) & CLOCK_CONTROL_UART_CLK_MASK) >> CLOCK_CONTROL_UART_CLK_LSB) +#define CLOCK_CONTROL_UART_CLK_SET(x) (((x) << CLOCK_CONTROL_UART_CLK_LSB) & CLOCK_CONTROL_UART_CLK_MASK) +#define CLOCK_CONTROL_SI0_CLK_MSB 0 +#define CLOCK_CONTROL_SI0_CLK_LSB 0 +#define CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 +#define CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & CLOCK_CONTROL_SI0_CLK_MASK) >> CLOCK_CONTROL_SI0_CLK_LSB) +#define CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << CLOCK_CONTROL_SI0_CLK_LSB) & CLOCK_CONTROL_SI0_CLK_MASK) + +#define BIAS_OVERRIDE_ADDRESS 0x0000002c +#define BIAS_OVERRIDE_OFFSET 0x0000002c +#define BIAS_OVERRIDE_ON_MSB 0 +#define BIAS_OVERRIDE_ON_LSB 0 +#define BIAS_OVERRIDE_ON_MASK 0x00000001 +#define BIAS_OVERRIDE_ON_GET(x) (((x) & BIAS_OVERRIDE_ON_MASK) >> BIAS_OVERRIDE_ON_LSB) +#define BIAS_OVERRIDE_ON_SET(x) (((x) << BIAS_OVERRIDE_ON_LSB) & BIAS_OVERRIDE_ON_MASK) + +#define WDT_CONTROL_ADDRESS 0x00000030 +#define WDT_CONTROL_OFFSET 0x00000030 +#define WDT_CONTROL_ACTION_MSB 2 +#define WDT_CONTROL_ACTION_LSB 0 +#define WDT_CONTROL_ACTION_MASK 0x00000007 +#define WDT_CONTROL_ACTION_GET(x) (((x) & WDT_CONTROL_ACTION_MASK) >> WDT_CONTROL_ACTION_LSB) +#define WDT_CONTROL_ACTION_SET(x) (((x) << WDT_CONTROL_ACTION_LSB) & WDT_CONTROL_ACTION_MASK) + +#define WDT_STATUS_ADDRESS 0x00000034 +#define WDT_STATUS_OFFSET 0x00000034 +#define WDT_STATUS_INTERRUPT_MSB 0 +#define WDT_STATUS_INTERRUPT_LSB 0 +#define WDT_STATUS_INTERRUPT_MASK 0x00000001 +#define WDT_STATUS_INTERRUPT_GET(x) (((x) & WDT_STATUS_INTERRUPT_MASK) >> WDT_STATUS_INTERRUPT_LSB) +#define WDT_STATUS_INTERRUPT_SET(x) (((x) << WDT_STATUS_INTERRUPT_LSB) & WDT_STATUS_INTERRUPT_MASK) + +#define WDT_ADDRESS 0x00000038 +#define WDT_OFFSET 0x00000038 +#define WDT_TARGET_MSB 21 +#define WDT_TARGET_LSB 0 +#define WDT_TARGET_MASK 0x003fffff +#define WDT_TARGET_GET(x) (((x) & WDT_TARGET_MASK) >> WDT_TARGET_LSB) +#define WDT_TARGET_SET(x) (((x) << WDT_TARGET_LSB) & WDT_TARGET_MASK) + +#define WDT_COUNT_ADDRESS 0x0000003c +#define WDT_COUNT_OFFSET 0x0000003c +#define WDT_COUNT_VALUE_MSB 21 +#define WDT_COUNT_VALUE_LSB 0 +#define WDT_COUNT_VALUE_MASK 0x003fffff +#define WDT_COUNT_VALUE_GET(x) (((x) & WDT_COUNT_VALUE_MASK) >> WDT_COUNT_VALUE_LSB) +#define WDT_COUNT_VALUE_SET(x) (((x) << WDT_COUNT_VALUE_LSB) & WDT_COUNT_VALUE_MASK) + +#define WDT_RESET_ADDRESS 0x00000040 +#define WDT_RESET_OFFSET 0x00000040 +#define WDT_RESET_VALUE_MSB 0 +#define WDT_RESET_VALUE_LSB 0 +#define WDT_RESET_VALUE_MASK 0x00000001 +#define WDT_RESET_VALUE_GET(x) (((x) & WDT_RESET_VALUE_MASK) >> WDT_RESET_VALUE_LSB) +#define WDT_RESET_VALUE_SET(x) (((x) << WDT_RESET_VALUE_LSB) & WDT_RESET_VALUE_MASK) + +#define INT_STATUS_ADDRESS 0x00000044 +#define INT_STATUS_OFFSET 0x00000044 +#define INT_STATUS_RTC_POWER_MSB 14 +#define INT_STATUS_RTC_POWER_LSB 14 +#define INT_STATUS_RTC_POWER_MASK 0x00004000 +#define INT_STATUS_RTC_POWER_GET(x) (((x) & INT_STATUS_RTC_POWER_MASK) >> INT_STATUS_RTC_POWER_LSB) +#define INT_STATUS_RTC_POWER_SET(x) (((x) << INT_STATUS_RTC_POWER_LSB) & INT_STATUS_RTC_POWER_MASK) +#define INT_STATUS_MAC_MSB 13 +#define INT_STATUS_MAC_LSB 13 +#define INT_STATUS_MAC_MASK 0x00002000 +#define INT_STATUS_MAC_GET(x) (((x) & INT_STATUS_MAC_MASK) >> INT_STATUS_MAC_LSB) +#define INT_STATUS_MAC_SET(x) (((x) << INT_STATUS_MAC_LSB) & INT_STATUS_MAC_MASK) +#define INT_STATUS_MAILBOX_MSB 12 +#define INT_STATUS_MAILBOX_LSB 12 +#define INT_STATUS_MAILBOX_MASK 0x00001000 +#define INT_STATUS_MAILBOX_GET(x) (((x) & INT_STATUS_MAILBOX_MASK) >> INT_STATUS_MAILBOX_LSB) +#define INT_STATUS_MAILBOX_SET(x) (((x) << INT_STATUS_MAILBOX_LSB) & INT_STATUS_MAILBOX_MASK) +#define INT_STATUS_RTC_ALARM_MSB 11 +#define INT_STATUS_RTC_ALARM_LSB 11 +#define INT_STATUS_RTC_ALARM_MASK 0x00000800 +#define INT_STATUS_RTC_ALARM_GET(x) (((x) & INT_STATUS_RTC_ALARM_MASK) >> INT_STATUS_RTC_ALARM_LSB) +#define INT_STATUS_RTC_ALARM_SET(x) (((x) << INT_STATUS_RTC_ALARM_LSB) & INT_STATUS_RTC_ALARM_MASK) +#define INT_STATUS_HF_TIMER_MSB 10 +#define INT_STATUS_HF_TIMER_LSB 10 +#define INT_STATUS_HF_TIMER_MASK 0x00000400 +#define INT_STATUS_HF_TIMER_GET(x) (((x) & INT_STATUS_HF_TIMER_MASK) >> INT_STATUS_HF_TIMER_LSB) +#define INT_STATUS_HF_TIMER_SET(x) (((x) << INT_STATUS_HF_TIMER_LSB) & INT_STATUS_HF_TIMER_MASK) +#define INT_STATUS_LF_TIMER3_MSB 9 +#define INT_STATUS_LF_TIMER3_LSB 9 +#define INT_STATUS_LF_TIMER3_MASK 0x00000200 +#define INT_STATUS_LF_TIMER3_GET(x) (((x) & INT_STATUS_LF_TIMER3_MASK) >> INT_STATUS_LF_TIMER3_LSB) +#define INT_STATUS_LF_TIMER3_SET(x) (((x) << INT_STATUS_LF_TIMER3_LSB) & INT_STATUS_LF_TIMER3_MASK) +#define INT_STATUS_LF_TIMER2_MSB 8 +#define INT_STATUS_LF_TIMER2_LSB 8 +#define INT_STATUS_LF_TIMER2_MASK 0x00000100 +#define INT_STATUS_LF_TIMER2_GET(x) (((x) & INT_STATUS_LF_TIMER2_MASK) >> INT_STATUS_LF_TIMER2_LSB) +#define INT_STATUS_LF_TIMER2_SET(x) (((x) << INT_STATUS_LF_TIMER2_LSB) & INT_STATUS_LF_TIMER2_MASK) +#define INT_STATUS_LF_TIMER1_MSB 7 +#define INT_STATUS_LF_TIMER1_LSB 7 +#define INT_STATUS_LF_TIMER1_MASK 0x00000080 +#define INT_STATUS_LF_TIMER1_GET(x) (((x) & INT_STATUS_LF_TIMER1_MASK) >> INT_STATUS_LF_TIMER1_LSB) +#define INT_STATUS_LF_TIMER1_SET(x) (((x) << INT_STATUS_LF_TIMER1_LSB) & INT_STATUS_LF_TIMER1_MASK) +#define INT_STATUS_LF_TIMER0_MSB 6 +#define INT_STATUS_LF_TIMER0_LSB 6 +#define INT_STATUS_LF_TIMER0_MASK 0x00000040 +#define INT_STATUS_LF_TIMER0_GET(x) (((x) & INT_STATUS_LF_TIMER0_MASK) >> INT_STATUS_LF_TIMER0_LSB) +#define INT_STATUS_LF_TIMER0_SET(x) (((x) << INT_STATUS_LF_TIMER0_LSB) & INT_STATUS_LF_TIMER0_MASK) +#define INT_STATUS_KEYPAD_MSB 5 +#define INT_STATUS_KEYPAD_LSB 5 +#define INT_STATUS_KEYPAD_MASK 0x00000020 +#define INT_STATUS_KEYPAD_GET(x) (((x) & INT_STATUS_KEYPAD_MASK) >> INT_STATUS_KEYPAD_LSB) +#define INT_STATUS_KEYPAD_SET(x) (((x) << INT_STATUS_KEYPAD_LSB) & INT_STATUS_KEYPAD_MASK) +#define INT_STATUS_SI_MSB 4 +#define INT_STATUS_SI_LSB 4 +#define INT_STATUS_SI_MASK 0x00000010 +#define INT_STATUS_SI_GET(x) (((x) & INT_STATUS_SI_MASK) >> INT_STATUS_SI_LSB) +#define INT_STATUS_SI_SET(x) (((x) << INT_STATUS_SI_LSB) & INT_STATUS_SI_MASK) +#define INT_STATUS_GPIO_MSB 3 +#define INT_STATUS_GPIO_LSB 3 +#define INT_STATUS_GPIO_MASK 0x00000008 +#define INT_STATUS_GPIO_GET(x) (((x) & INT_STATUS_GPIO_MASK) >> INT_STATUS_GPIO_LSB) +#define INT_STATUS_GPIO_SET(x) (((x) << INT_STATUS_GPIO_LSB) & INT_STATUS_GPIO_MASK) +#define INT_STATUS_UART_MSB 2 +#define INT_STATUS_UART_LSB 2 +#define INT_STATUS_UART_MASK 0x00000004 +#define INT_STATUS_UART_GET(x) (((x) & INT_STATUS_UART_MASK) >> INT_STATUS_UART_LSB) +#define INT_STATUS_UART_SET(x) (((x) << INT_STATUS_UART_LSB) & INT_STATUS_UART_MASK) +#define INT_STATUS_ERROR_MSB 1 +#define INT_STATUS_ERROR_LSB 1 +#define INT_STATUS_ERROR_MASK 0x00000002 +#define INT_STATUS_ERROR_GET(x) (((x) & INT_STATUS_ERROR_MASK) >> INT_STATUS_ERROR_LSB) +#define INT_STATUS_ERROR_SET(x) (((x) << INT_STATUS_ERROR_LSB) & INT_STATUS_ERROR_MASK) +#define INT_STATUS_WDT_INT_MSB 0 +#define INT_STATUS_WDT_INT_LSB 0 +#define INT_STATUS_WDT_INT_MASK 0x00000001 +#define INT_STATUS_WDT_INT_GET(x) (((x) & INT_STATUS_WDT_INT_MASK) >> INT_STATUS_WDT_INT_LSB) +#define INT_STATUS_WDT_INT_SET(x) (((x) << INT_STATUS_WDT_INT_LSB) & INT_STATUS_WDT_INT_MASK) + +#define LF_TIMER0_ADDRESS 0x00000048 +#define LF_TIMER0_OFFSET 0x00000048 +#define LF_TIMER0_TARGET_MSB 31 +#define LF_TIMER0_TARGET_LSB 0 +#define LF_TIMER0_TARGET_MASK 0xffffffff +#define LF_TIMER0_TARGET_GET(x) (((x) & LF_TIMER0_TARGET_MASK) >> LF_TIMER0_TARGET_LSB) +#define LF_TIMER0_TARGET_SET(x) (((x) << LF_TIMER0_TARGET_LSB) & LF_TIMER0_TARGET_MASK) + +#define LF_TIMER_COUNT0_ADDRESS 0x0000004c +#define LF_TIMER_COUNT0_OFFSET 0x0000004c +#define LF_TIMER_COUNT0_VALUE_MSB 31 +#define LF_TIMER_COUNT0_VALUE_LSB 0 +#define LF_TIMER_COUNT0_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT0_VALUE_GET(x) (((x) & LF_TIMER_COUNT0_VALUE_MASK) >> LF_TIMER_COUNT0_VALUE_LSB) +#define LF_TIMER_COUNT0_VALUE_SET(x) (((x) << LF_TIMER_COUNT0_VALUE_LSB) & LF_TIMER_COUNT0_VALUE_MASK) + +#define LF_TIMER_CONTROL0_ADDRESS 0x00000050 +#define LF_TIMER_CONTROL0_OFFSET 0x00000050 +#define LF_TIMER_CONTROL0_ENABLE_MSB 2 +#define LF_TIMER_CONTROL0_ENABLE_LSB 2 +#define LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL0_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL0_ENABLE_MASK) >> LF_TIMER_CONTROL0_ENABLE_LSB) +#define LF_TIMER_CONTROL0_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL0_ENABLE_LSB) & LF_TIMER_CONTROL0_ENABLE_MASK) +#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL0_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL0_RESET_MSB 0 +#define LF_TIMER_CONTROL0_RESET_LSB 0 +#define LF_TIMER_CONTROL0_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL0_RESET_GET(x) (((x) & LF_TIMER_CONTROL0_RESET_MASK) >> LF_TIMER_CONTROL0_RESET_LSB) +#define LF_TIMER_CONTROL0_RESET_SET(x) (((x) << LF_TIMER_CONTROL0_RESET_LSB) & LF_TIMER_CONTROL0_RESET_MASK) + +#define LF_TIMER_STATUS0_ADDRESS 0x00000054 +#define LF_TIMER_STATUS0_OFFSET 0x00000054 +#define LF_TIMER_STATUS0_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS0_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS0_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS0_INTERRUPT_MASK) >> LF_TIMER_STATUS0_INTERRUPT_LSB) +#define LF_TIMER_STATUS0_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS0_INTERRUPT_LSB) & LF_TIMER_STATUS0_INTERRUPT_MASK) + +#define LF_TIMER1_ADDRESS 0x00000058 +#define LF_TIMER1_OFFSET 0x00000058 +#define LF_TIMER1_TARGET_MSB 31 +#define LF_TIMER1_TARGET_LSB 0 +#define LF_TIMER1_TARGET_MASK 0xffffffff +#define LF_TIMER1_TARGET_GET(x) (((x) & LF_TIMER1_TARGET_MASK) >> LF_TIMER1_TARGET_LSB) +#define LF_TIMER1_TARGET_SET(x) (((x) << LF_TIMER1_TARGET_LSB) & LF_TIMER1_TARGET_MASK) + +#define LF_TIMER_COUNT1_ADDRESS 0x0000005c +#define LF_TIMER_COUNT1_OFFSET 0x0000005c +#define LF_TIMER_COUNT1_VALUE_MSB 31 +#define LF_TIMER_COUNT1_VALUE_LSB 0 +#define LF_TIMER_COUNT1_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT1_VALUE_GET(x) (((x) & LF_TIMER_COUNT1_VALUE_MASK) >> LF_TIMER_COUNT1_VALUE_LSB) +#define LF_TIMER_COUNT1_VALUE_SET(x) (((x) << LF_TIMER_COUNT1_VALUE_LSB) & LF_TIMER_COUNT1_VALUE_MASK) + +#define LF_TIMER_CONTROL1_ADDRESS 0x00000060 +#define LF_TIMER_CONTROL1_OFFSET 0x00000060 +#define LF_TIMER_CONTROL1_ENABLE_MSB 2 +#define LF_TIMER_CONTROL1_ENABLE_LSB 2 +#define LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL1_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL1_ENABLE_MASK) >> LF_TIMER_CONTROL1_ENABLE_LSB) +#define LF_TIMER_CONTROL1_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL1_ENABLE_LSB) & LF_TIMER_CONTROL1_ENABLE_MASK) +#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL1_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL1_RESET_MSB 0 +#define LF_TIMER_CONTROL1_RESET_LSB 0 +#define LF_TIMER_CONTROL1_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL1_RESET_GET(x) (((x) & LF_TIMER_CONTROL1_RESET_MASK) >> LF_TIMER_CONTROL1_RESET_LSB) +#define LF_TIMER_CONTROL1_RESET_SET(x) (((x) << LF_TIMER_CONTROL1_RESET_LSB) & LF_TIMER_CONTROL1_RESET_MASK) + +#define LF_TIMER_STATUS1_ADDRESS 0x00000064 +#define LF_TIMER_STATUS1_OFFSET 0x00000064 +#define LF_TIMER_STATUS1_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS1_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS1_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS1_INTERRUPT_MASK) >> LF_TIMER_STATUS1_INTERRUPT_LSB) +#define LF_TIMER_STATUS1_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS1_INTERRUPT_LSB) & LF_TIMER_STATUS1_INTERRUPT_MASK) + +#define LF_TIMER2_ADDRESS 0x00000068 +#define LF_TIMER2_OFFSET 0x00000068 +#define LF_TIMER2_TARGET_MSB 31 +#define LF_TIMER2_TARGET_LSB 0 +#define LF_TIMER2_TARGET_MASK 0xffffffff +#define LF_TIMER2_TARGET_GET(x) (((x) & LF_TIMER2_TARGET_MASK) >> LF_TIMER2_TARGET_LSB) +#define LF_TIMER2_TARGET_SET(x) (((x) << LF_TIMER2_TARGET_LSB) & LF_TIMER2_TARGET_MASK) + +#define LF_TIMER_COUNT2_ADDRESS 0x0000006c +#define LF_TIMER_COUNT2_OFFSET 0x0000006c +#define LF_TIMER_COUNT2_VALUE_MSB 31 +#define LF_TIMER_COUNT2_VALUE_LSB 0 +#define LF_TIMER_COUNT2_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT2_VALUE_GET(x) (((x) & LF_TIMER_COUNT2_VALUE_MASK) >> LF_TIMER_COUNT2_VALUE_LSB) +#define LF_TIMER_COUNT2_VALUE_SET(x) (((x) << LF_TIMER_COUNT2_VALUE_LSB) & LF_TIMER_COUNT2_VALUE_MASK) + +#define LF_TIMER_CONTROL2_ADDRESS 0x00000070 +#define LF_TIMER_CONTROL2_OFFSET 0x00000070 +#define LF_TIMER_CONTROL2_ENABLE_MSB 2 +#define LF_TIMER_CONTROL2_ENABLE_LSB 2 +#define LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL2_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL2_ENABLE_MASK) >> LF_TIMER_CONTROL2_ENABLE_LSB) +#define LF_TIMER_CONTROL2_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL2_ENABLE_LSB) & LF_TIMER_CONTROL2_ENABLE_MASK) +#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL2_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL2_RESET_MSB 0 +#define LF_TIMER_CONTROL2_RESET_LSB 0 +#define LF_TIMER_CONTROL2_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL2_RESET_GET(x) (((x) & LF_TIMER_CONTROL2_RESET_MASK) >> LF_TIMER_CONTROL2_RESET_LSB) +#define LF_TIMER_CONTROL2_RESET_SET(x) (((x) << LF_TIMER_CONTROL2_RESET_LSB) & LF_TIMER_CONTROL2_RESET_MASK) + +#define LF_TIMER_STATUS2_ADDRESS 0x00000074 +#define LF_TIMER_STATUS2_OFFSET 0x00000074 +#define LF_TIMER_STATUS2_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS2_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS2_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS2_INTERRUPT_MASK) >> LF_TIMER_STATUS2_INTERRUPT_LSB) +#define LF_TIMER_STATUS2_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS2_INTERRUPT_LSB) & LF_TIMER_STATUS2_INTERRUPT_MASK) + +#define LF_TIMER3_ADDRESS 0x00000078 +#define LF_TIMER3_OFFSET 0x00000078 +#define LF_TIMER3_TARGET_MSB 31 +#define LF_TIMER3_TARGET_LSB 0 +#define LF_TIMER3_TARGET_MASK 0xffffffff +#define LF_TIMER3_TARGET_GET(x) (((x) & LF_TIMER3_TARGET_MASK) >> LF_TIMER3_TARGET_LSB) +#define LF_TIMER3_TARGET_SET(x) (((x) << LF_TIMER3_TARGET_LSB) & LF_TIMER3_TARGET_MASK) + +#define LF_TIMER_COUNT3_ADDRESS 0x0000007c +#define LF_TIMER_COUNT3_OFFSET 0x0000007c +#define LF_TIMER_COUNT3_VALUE_MSB 31 +#define LF_TIMER_COUNT3_VALUE_LSB 0 +#define LF_TIMER_COUNT3_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT3_VALUE_GET(x) (((x) & LF_TIMER_COUNT3_VALUE_MASK) >> LF_TIMER_COUNT3_VALUE_LSB) +#define LF_TIMER_COUNT3_VALUE_SET(x) (((x) << LF_TIMER_COUNT3_VALUE_LSB) & LF_TIMER_COUNT3_VALUE_MASK) + +#define LF_TIMER_CONTROL3_ADDRESS 0x00000080 +#define LF_TIMER_CONTROL3_OFFSET 0x00000080 +#define LF_TIMER_CONTROL3_ENABLE_MSB 2 +#define LF_TIMER_CONTROL3_ENABLE_LSB 2 +#define LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL3_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL3_ENABLE_MASK) >> LF_TIMER_CONTROL3_ENABLE_LSB) +#define LF_TIMER_CONTROL3_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL3_ENABLE_LSB) & LF_TIMER_CONTROL3_ENABLE_MASK) +#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL3_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL3_RESET_MSB 0 +#define LF_TIMER_CONTROL3_RESET_LSB 0 +#define LF_TIMER_CONTROL3_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL3_RESET_GET(x) (((x) & LF_TIMER_CONTROL3_RESET_MASK) >> LF_TIMER_CONTROL3_RESET_LSB) +#define LF_TIMER_CONTROL3_RESET_SET(x) (((x) << LF_TIMER_CONTROL3_RESET_LSB) & LF_TIMER_CONTROL3_RESET_MASK) + +#define LF_TIMER_STATUS3_ADDRESS 0x00000084 +#define LF_TIMER_STATUS3_OFFSET 0x00000084 +#define LF_TIMER_STATUS3_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS3_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS3_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS3_INTERRUPT_MASK) >> LF_TIMER_STATUS3_INTERRUPT_LSB) +#define LF_TIMER_STATUS3_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS3_INTERRUPT_LSB) & LF_TIMER_STATUS3_INTERRUPT_MASK) + +#define HF_TIMER_ADDRESS 0x00000088 +#define HF_TIMER_OFFSET 0x00000088 +#define HF_TIMER_TARGET_MSB 31 +#define HF_TIMER_TARGET_LSB 12 +#define HF_TIMER_TARGET_MASK 0xfffff000 +#define HF_TIMER_TARGET_GET(x) (((x) & HF_TIMER_TARGET_MASK) >> HF_TIMER_TARGET_LSB) +#define HF_TIMER_TARGET_SET(x) (((x) << HF_TIMER_TARGET_LSB) & HF_TIMER_TARGET_MASK) + +#define HF_TIMER_COUNT_ADDRESS 0x0000008c +#define HF_TIMER_COUNT_OFFSET 0x0000008c +#define HF_TIMER_COUNT_VALUE_MSB 31 +#define HF_TIMER_COUNT_VALUE_LSB 12 +#define HF_TIMER_COUNT_VALUE_MASK 0xfffff000 +#define HF_TIMER_COUNT_VALUE_GET(x) (((x) & HF_TIMER_COUNT_VALUE_MASK) >> HF_TIMER_COUNT_VALUE_LSB) +#define HF_TIMER_COUNT_VALUE_SET(x) (((x) << HF_TIMER_COUNT_VALUE_LSB) & HF_TIMER_COUNT_VALUE_MASK) + +#define HF_LF_COUNT_ADDRESS 0x00000090 +#define HF_LF_COUNT_OFFSET 0x00000090 +#define HF_LF_COUNT_VALUE_MSB 31 +#define HF_LF_COUNT_VALUE_LSB 0 +#define HF_LF_COUNT_VALUE_MASK 0xffffffff +#define HF_LF_COUNT_VALUE_GET(x) (((x) & HF_LF_COUNT_VALUE_MASK) >> HF_LF_COUNT_VALUE_LSB) +#define HF_LF_COUNT_VALUE_SET(x) (((x) << HF_LF_COUNT_VALUE_LSB) & HF_LF_COUNT_VALUE_MASK) + +#define HF_TIMER_CONTROL_ADDRESS 0x00000094 +#define HF_TIMER_CONTROL_OFFSET 0x00000094 +#define HF_TIMER_CONTROL_ENABLE_MSB 3 +#define HF_TIMER_CONTROL_ENABLE_LSB 3 +#define HF_TIMER_CONTROL_ENABLE_MASK 0x00000008 +#define HF_TIMER_CONTROL_ENABLE_GET(x) (((x) & HF_TIMER_CONTROL_ENABLE_MASK) >> HF_TIMER_CONTROL_ENABLE_LSB) +#define HF_TIMER_CONTROL_ENABLE_SET(x) (((x) << HF_TIMER_CONTROL_ENABLE_LSB) & HF_TIMER_CONTROL_ENABLE_MASK) +#define HF_TIMER_CONTROL_ON_MSB 2 +#define HF_TIMER_CONTROL_ON_LSB 2 +#define HF_TIMER_CONTROL_ON_MASK 0x00000004 +#define HF_TIMER_CONTROL_ON_GET(x) (((x) & HF_TIMER_CONTROL_ON_MASK) >> HF_TIMER_CONTROL_ON_LSB) +#define HF_TIMER_CONTROL_ON_SET(x) (((x) << HF_TIMER_CONTROL_ON_LSB) & HF_TIMER_CONTROL_ON_MASK) +#define HF_TIMER_CONTROL_AUTO_RESTART_MSB 1 +#define HF_TIMER_CONTROL_AUTO_RESTART_LSB 1 +#define HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002 +#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> HF_TIMER_CONTROL_AUTO_RESTART_LSB) +#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << HF_TIMER_CONTROL_AUTO_RESTART_LSB) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) +#define HF_TIMER_CONTROL_RESET_MSB 0 +#define HF_TIMER_CONTROL_RESET_LSB 0 +#define HF_TIMER_CONTROL_RESET_MASK 0x00000001 +#define HF_TIMER_CONTROL_RESET_GET(x) (((x) & HF_TIMER_CONTROL_RESET_MASK) >> HF_TIMER_CONTROL_RESET_LSB) +#define HF_TIMER_CONTROL_RESET_SET(x) (((x) << HF_TIMER_CONTROL_RESET_LSB) & HF_TIMER_CONTROL_RESET_MASK) + +#define HF_TIMER_STATUS_ADDRESS 0x00000098 +#define HF_TIMER_STATUS_OFFSET 0x00000098 +#define HF_TIMER_STATUS_INTERRUPT_MSB 0 +#define HF_TIMER_STATUS_INTERRUPT_LSB 0 +#define HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001 +#define HF_TIMER_STATUS_INTERRUPT_GET(x) (((x) & HF_TIMER_STATUS_INTERRUPT_MASK) >> HF_TIMER_STATUS_INTERRUPT_LSB) +#define HF_TIMER_STATUS_INTERRUPT_SET(x) (((x) << HF_TIMER_STATUS_INTERRUPT_LSB) & HF_TIMER_STATUS_INTERRUPT_MASK) + +#define RTC_CONTROL_ADDRESS 0x0000009c +#define RTC_CONTROL_OFFSET 0x0000009c +#define RTC_CONTROL_ENABLE_MSB 2 +#define RTC_CONTROL_ENABLE_LSB 2 +#define RTC_CONTROL_ENABLE_MASK 0x00000004 +#define RTC_CONTROL_ENABLE_GET(x) (((x) & RTC_CONTROL_ENABLE_MASK) >> RTC_CONTROL_ENABLE_LSB) +#define RTC_CONTROL_ENABLE_SET(x) (((x) << RTC_CONTROL_ENABLE_LSB) & RTC_CONTROL_ENABLE_MASK) +#define RTC_CONTROL_LOAD_RTC_MSB 1 +#define RTC_CONTROL_LOAD_RTC_LSB 1 +#define RTC_CONTROL_LOAD_RTC_MASK 0x00000002 +#define RTC_CONTROL_LOAD_RTC_GET(x) (((x) & RTC_CONTROL_LOAD_RTC_MASK) >> RTC_CONTROL_LOAD_RTC_LSB) +#define RTC_CONTROL_LOAD_RTC_SET(x) (((x) << RTC_CONTROL_LOAD_RTC_LSB) & RTC_CONTROL_LOAD_RTC_MASK) +#define RTC_CONTROL_LOAD_ALARM_MSB 0 +#define RTC_CONTROL_LOAD_ALARM_LSB 0 +#define RTC_CONTROL_LOAD_ALARM_MASK 0x00000001 +#define RTC_CONTROL_LOAD_ALARM_GET(x) (((x) & RTC_CONTROL_LOAD_ALARM_MASK) >> RTC_CONTROL_LOAD_ALARM_LSB) +#define RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << RTC_CONTROL_LOAD_ALARM_LSB) & RTC_CONTROL_LOAD_ALARM_MASK) + +#define RTC_TIME_ADDRESS 0x000000a0 +#define RTC_TIME_OFFSET 0x000000a0 +#define RTC_TIME_WEEK_DAY_MSB 26 +#define RTC_TIME_WEEK_DAY_LSB 24 +#define RTC_TIME_WEEK_DAY_MASK 0x07000000 +#define RTC_TIME_WEEK_DAY_GET(x) (((x) & RTC_TIME_WEEK_DAY_MASK) >> RTC_TIME_WEEK_DAY_LSB) +#define RTC_TIME_WEEK_DAY_SET(x) (((x) << RTC_TIME_WEEK_DAY_LSB) & RTC_TIME_WEEK_DAY_MASK) +#define RTC_TIME_HOUR_MSB 21 +#define RTC_TIME_HOUR_LSB 16 +#define RTC_TIME_HOUR_MASK 0x003f0000 +#define RTC_TIME_HOUR_GET(x) (((x) & RTC_TIME_HOUR_MASK) >> RTC_TIME_HOUR_LSB) +#define RTC_TIME_HOUR_SET(x) (((x) << RTC_TIME_HOUR_LSB) & RTC_TIME_HOUR_MASK) +#define RTC_TIME_MINUTE_MSB 14 +#define RTC_TIME_MINUTE_LSB 8 +#define RTC_TIME_MINUTE_MASK 0x00007f00 +#define RTC_TIME_MINUTE_GET(x) (((x) & RTC_TIME_MINUTE_MASK) >> RTC_TIME_MINUTE_LSB) +#define RTC_TIME_MINUTE_SET(x) (((x) << RTC_TIME_MINUTE_LSB) & RTC_TIME_MINUTE_MASK) +#define RTC_TIME_SECOND_MSB 6 +#define RTC_TIME_SECOND_LSB 0 +#define RTC_TIME_SECOND_MASK 0x0000007f +#define RTC_TIME_SECOND_GET(x) (((x) & RTC_TIME_SECOND_MASK) >> RTC_TIME_SECOND_LSB) +#define RTC_TIME_SECOND_SET(x) (((x) << RTC_TIME_SECOND_LSB) & RTC_TIME_SECOND_MASK) + +#define RTC_DATE_ADDRESS 0x000000a4 +#define RTC_DATE_OFFSET 0x000000a4 +#define RTC_DATE_YEAR_MSB 23 +#define RTC_DATE_YEAR_LSB 16 +#define RTC_DATE_YEAR_MASK 0x00ff0000 +#define RTC_DATE_YEAR_GET(x) (((x) & RTC_DATE_YEAR_MASK) >> RTC_DATE_YEAR_LSB) +#define RTC_DATE_YEAR_SET(x) (((x) << RTC_DATE_YEAR_LSB) & RTC_DATE_YEAR_MASK) +#define RTC_DATE_MONTH_MSB 12 +#define RTC_DATE_MONTH_LSB 8 +#define RTC_DATE_MONTH_MASK 0x00001f00 +#define RTC_DATE_MONTH_GET(x) (((x) & RTC_DATE_MONTH_MASK) >> RTC_DATE_MONTH_LSB) +#define RTC_DATE_MONTH_SET(x) (((x) << RTC_DATE_MONTH_LSB) & RTC_DATE_MONTH_MASK) +#define RTC_DATE_MONTH_DAY_MSB 5 +#define RTC_DATE_MONTH_DAY_LSB 0 +#define RTC_DATE_MONTH_DAY_MASK 0x0000003f +#define RTC_DATE_MONTH_DAY_GET(x) (((x) & RTC_DATE_MONTH_DAY_MASK) >> RTC_DATE_MONTH_DAY_LSB) +#define RTC_DATE_MONTH_DAY_SET(x) (((x) << RTC_DATE_MONTH_DAY_LSB) & RTC_DATE_MONTH_DAY_MASK) + +#define RTC_SET_TIME_ADDRESS 0x000000a8 +#define RTC_SET_TIME_OFFSET 0x000000a8 +#define RTC_SET_TIME_WEEK_DAY_MSB 26 +#define RTC_SET_TIME_WEEK_DAY_LSB 24 +#define RTC_SET_TIME_WEEK_DAY_MASK 0x07000000 +#define RTC_SET_TIME_WEEK_DAY_GET(x) (((x) & RTC_SET_TIME_WEEK_DAY_MASK) >> RTC_SET_TIME_WEEK_DAY_LSB) +#define RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << RTC_SET_TIME_WEEK_DAY_LSB) & RTC_SET_TIME_WEEK_DAY_MASK) +#define RTC_SET_TIME_HOUR_MSB 21 +#define RTC_SET_TIME_HOUR_LSB 16 +#define RTC_SET_TIME_HOUR_MASK 0x003f0000 +#define RTC_SET_TIME_HOUR_GET(x) (((x) & RTC_SET_TIME_HOUR_MASK) >> RTC_SET_TIME_HOUR_LSB) +#define RTC_SET_TIME_HOUR_SET(x) (((x) << RTC_SET_TIME_HOUR_LSB) & RTC_SET_TIME_HOUR_MASK) +#define RTC_SET_TIME_MINUTE_MSB 14 +#define RTC_SET_TIME_MINUTE_LSB 8 +#define RTC_SET_TIME_MINUTE_MASK 0x00007f00 +#define RTC_SET_TIME_MINUTE_GET(x) (((x) & RTC_SET_TIME_MINUTE_MASK) >> RTC_SET_TIME_MINUTE_LSB) +#define RTC_SET_TIME_MINUTE_SET(x) (((x) << RTC_SET_TIME_MINUTE_LSB) & RTC_SET_TIME_MINUTE_MASK) +#define RTC_SET_TIME_SECOND_MSB 6 +#define RTC_SET_TIME_SECOND_LSB 0 +#define RTC_SET_TIME_SECOND_MASK 0x0000007f +#define RTC_SET_TIME_SECOND_GET(x) (((x) & RTC_SET_TIME_SECOND_MASK) >> RTC_SET_TIME_SECOND_LSB) +#define RTC_SET_TIME_SECOND_SET(x) (((x) << RTC_SET_TIME_SECOND_LSB) & RTC_SET_TIME_SECOND_MASK) + +#define RTC_SET_DATE_ADDRESS 0x000000ac +#define RTC_SET_DATE_OFFSET 0x000000ac +#define RTC_SET_DATE_YEAR_MSB 23 +#define RTC_SET_DATE_YEAR_LSB 16 +#define RTC_SET_DATE_YEAR_MASK 0x00ff0000 +#define RTC_SET_DATE_YEAR_GET(x) (((x) & RTC_SET_DATE_YEAR_MASK) >> RTC_SET_DATE_YEAR_LSB) +#define RTC_SET_DATE_YEAR_SET(x) (((x) << RTC_SET_DATE_YEAR_LSB) & RTC_SET_DATE_YEAR_MASK) +#define RTC_SET_DATE_MONTH_MSB 12 +#define RTC_SET_DATE_MONTH_LSB 8 +#define RTC_SET_DATE_MONTH_MASK 0x00001f00 +#define RTC_SET_DATE_MONTH_GET(x) (((x) & RTC_SET_DATE_MONTH_MASK) >> RTC_SET_DATE_MONTH_LSB) +#define RTC_SET_DATE_MONTH_SET(x) (((x) << RTC_SET_DATE_MONTH_LSB) & RTC_SET_DATE_MONTH_MASK) +#define RTC_SET_DATE_MONTH_DAY_MSB 5 +#define RTC_SET_DATE_MONTH_DAY_LSB 0 +#define RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f +#define RTC_SET_DATE_MONTH_DAY_GET(x) (((x) & RTC_SET_DATE_MONTH_DAY_MASK) >> RTC_SET_DATE_MONTH_DAY_LSB) +#define RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << RTC_SET_DATE_MONTH_DAY_LSB) & RTC_SET_DATE_MONTH_DAY_MASK) + +#define RTC_SET_ALARM_ADDRESS 0x000000b0 +#define RTC_SET_ALARM_OFFSET 0x000000b0 +#define RTC_SET_ALARM_HOUR_MSB 21 +#define RTC_SET_ALARM_HOUR_LSB 16 +#define RTC_SET_ALARM_HOUR_MASK 0x003f0000 +#define RTC_SET_ALARM_HOUR_GET(x) (((x) & RTC_SET_ALARM_HOUR_MASK) >> RTC_SET_ALARM_HOUR_LSB) +#define RTC_SET_ALARM_HOUR_SET(x) (((x) << RTC_SET_ALARM_HOUR_LSB) & RTC_SET_ALARM_HOUR_MASK) +#define RTC_SET_ALARM_MINUTE_MSB 14 +#define RTC_SET_ALARM_MINUTE_LSB 8 +#define RTC_SET_ALARM_MINUTE_MASK 0x00007f00 +#define RTC_SET_ALARM_MINUTE_GET(x) (((x) & RTC_SET_ALARM_MINUTE_MASK) >> RTC_SET_ALARM_MINUTE_LSB) +#define RTC_SET_ALARM_MINUTE_SET(x) (((x) << RTC_SET_ALARM_MINUTE_LSB) & RTC_SET_ALARM_MINUTE_MASK) +#define RTC_SET_ALARM_SECOND_MSB 6 +#define RTC_SET_ALARM_SECOND_LSB 0 +#define RTC_SET_ALARM_SECOND_MASK 0x0000007f +#define RTC_SET_ALARM_SECOND_GET(x) (((x) & RTC_SET_ALARM_SECOND_MASK) >> RTC_SET_ALARM_SECOND_LSB) +#define RTC_SET_ALARM_SECOND_SET(x) (((x) << RTC_SET_ALARM_SECOND_LSB) & RTC_SET_ALARM_SECOND_MASK) + +#define RTC_CONFIG_ADDRESS 0x000000b4 +#define RTC_CONFIG_OFFSET 0x000000b4 +#define RTC_CONFIG_BCD_MSB 2 +#define RTC_CONFIG_BCD_LSB 2 +#define RTC_CONFIG_BCD_MASK 0x00000004 +#define RTC_CONFIG_BCD_GET(x) (((x) & RTC_CONFIG_BCD_MASK) >> RTC_CONFIG_BCD_LSB) +#define RTC_CONFIG_BCD_SET(x) (((x) << RTC_CONFIG_BCD_LSB) & RTC_CONFIG_BCD_MASK) +#define RTC_CONFIG_TWELVE_HOUR_MSB 1 +#define RTC_CONFIG_TWELVE_HOUR_LSB 1 +#define RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002 +#define RTC_CONFIG_TWELVE_HOUR_GET(x) (((x) & RTC_CONFIG_TWELVE_HOUR_MASK) >> RTC_CONFIG_TWELVE_HOUR_LSB) +#define RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << RTC_CONFIG_TWELVE_HOUR_LSB) & RTC_CONFIG_TWELVE_HOUR_MASK) +#define RTC_CONFIG_DSE_MSB 0 +#define RTC_CONFIG_DSE_LSB 0 +#define RTC_CONFIG_DSE_MASK 0x00000001 +#define RTC_CONFIG_DSE_GET(x) (((x) & RTC_CONFIG_DSE_MASK) >> RTC_CONFIG_DSE_LSB) +#define RTC_CONFIG_DSE_SET(x) (((x) << RTC_CONFIG_DSE_LSB) & RTC_CONFIG_DSE_MASK) + +#define RTC_ALARM_STATUS_ADDRESS 0x000000b8 +#define RTC_ALARM_STATUS_OFFSET 0x000000b8 +#define RTC_ALARM_STATUS_ENABLE_MSB 1 +#define RTC_ALARM_STATUS_ENABLE_LSB 1 +#define RTC_ALARM_STATUS_ENABLE_MASK 0x00000002 +#define RTC_ALARM_STATUS_ENABLE_GET(x) (((x) & RTC_ALARM_STATUS_ENABLE_MASK) >> RTC_ALARM_STATUS_ENABLE_LSB) +#define RTC_ALARM_STATUS_ENABLE_SET(x) (((x) << RTC_ALARM_STATUS_ENABLE_LSB) & RTC_ALARM_STATUS_ENABLE_MASK) +#define RTC_ALARM_STATUS_INTERRUPT_MSB 0 +#define RTC_ALARM_STATUS_INTERRUPT_LSB 0 +#define RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001 +#define RTC_ALARM_STATUS_INTERRUPT_GET(x) (((x) & RTC_ALARM_STATUS_INTERRUPT_MASK) >> RTC_ALARM_STATUS_INTERRUPT_LSB) +#define RTC_ALARM_STATUS_INTERRUPT_SET(x) (((x) << RTC_ALARM_STATUS_INTERRUPT_LSB) & RTC_ALARM_STATUS_INTERRUPT_MASK) + +#define UART_WAKEUP_ADDRESS 0x000000bc +#define UART_WAKEUP_OFFSET 0x000000bc +#define UART_WAKEUP_ENABLE_MSB 0 +#define UART_WAKEUP_ENABLE_LSB 0 +#define UART_WAKEUP_ENABLE_MASK 0x00000001 +#define UART_WAKEUP_ENABLE_GET(x) (((x) & UART_WAKEUP_ENABLE_MASK) >> UART_WAKEUP_ENABLE_LSB) +#define UART_WAKEUP_ENABLE_SET(x) (((x) << UART_WAKEUP_ENABLE_LSB) & UART_WAKEUP_ENABLE_MASK) + +#define RESET_CAUSE_ADDRESS 0x000000c0 +#define RESET_CAUSE_OFFSET 0x000000c0 +#define RESET_CAUSE_LAST_MSB 2 +#define RESET_CAUSE_LAST_LSB 0 +#define RESET_CAUSE_LAST_MASK 0x00000007 +#define RESET_CAUSE_LAST_GET(x) (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB) +#define RESET_CAUSE_LAST_SET(x) (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK) + +#define SYSTEM_SLEEP_ADDRESS 0x000000c4 +#define SYSTEM_SLEEP_OFFSET 0x000000c4 +#define SYSTEM_SLEEP_HOST_IF_MSB 4 +#define SYSTEM_SLEEP_HOST_IF_LSB 4 +#define SYSTEM_SLEEP_HOST_IF_MASK 0x00000010 +#define SYSTEM_SLEEP_HOST_IF_GET(x) (((x) & SYSTEM_SLEEP_HOST_IF_MASK) >> SYSTEM_SLEEP_HOST_IF_LSB) +#define SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << SYSTEM_SLEEP_HOST_IF_LSB) & SYSTEM_SLEEP_HOST_IF_MASK) +#define SYSTEM_SLEEP_MBOX_MSB 3 +#define SYSTEM_SLEEP_MBOX_LSB 3 +#define SYSTEM_SLEEP_MBOX_MASK 0x00000008 +#define SYSTEM_SLEEP_MBOX_GET(x) (((x) & SYSTEM_SLEEP_MBOX_MASK) >> SYSTEM_SLEEP_MBOX_LSB) +#define SYSTEM_SLEEP_MBOX_SET(x) (((x) << SYSTEM_SLEEP_MBOX_LSB) & SYSTEM_SLEEP_MBOX_MASK) +#define SYSTEM_SLEEP_MAC_IF_MSB 2 +#define SYSTEM_SLEEP_MAC_IF_LSB 2 +#define SYSTEM_SLEEP_MAC_IF_MASK 0x00000004 +#define SYSTEM_SLEEP_MAC_IF_GET(x) (((x) & SYSTEM_SLEEP_MAC_IF_MASK) >> SYSTEM_SLEEP_MAC_IF_LSB) +#define SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << SYSTEM_SLEEP_MAC_IF_LSB) & SYSTEM_SLEEP_MAC_IF_MASK) +#define SYSTEM_SLEEP_LIGHT_MSB 1 +#define SYSTEM_SLEEP_LIGHT_LSB 1 +#define SYSTEM_SLEEP_LIGHT_MASK 0x00000002 +#define SYSTEM_SLEEP_LIGHT_GET(x) (((x) & SYSTEM_SLEEP_LIGHT_MASK) >> SYSTEM_SLEEP_LIGHT_LSB) +#define SYSTEM_SLEEP_LIGHT_SET(x) (((x) << SYSTEM_SLEEP_LIGHT_LSB) & SYSTEM_SLEEP_LIGHT_MASK) +#define SYSTEM_SLEEP_DISABLE_MSB 0 +#define SYSTEM_SLEEP_DISABLE_LSB 0 +#define SYSTEM_SLEEP_DISABLE_MASK 0x00000001 +#define SYSTEM_SLEEP_DISABLE_GET(x) (((x) & SYSTEM_SLEEP_DISABLE_MASK) >> SYSTEM_SLEEP_DISABLE_LSB) +#define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK) + +#define SDIO_WRAPPER_ADDRESS 0x000000c8 +#define SDIO_WRAPPER_OFFSET 0x000000c8 +#define SDIO_WRAPPER_SLEEP_MSB 3 +#define SDIO_WRAPPER_SLEEP_LSB 3 +#define SDIO_WRAPPER_SLEEP_MASK 0x00000008 +#define SDIO_WRAPPER_SLEEP_GET(x) (((x) & SDIO_WRAPPER_SLEEP_MASK) >> SDIO_WRAPPER_SLEEP_LSB) +#define SDIO_WRAPPER_SLEEP_SET(x) (((x) << SDIO_WRAPPER_SLEEP_LSB) & SDIO_WRAPPER_SLEEP_MASK) +#define SDIO_WRAPPER_WAKEUP_MSB 2 +#define SDIO_WRAPPER_WAKEUP_LSB 2 +#define SDIO_WRAPPER_WAKEUP_MASK 0x00000004 +#define SDIO_WRAPPER_WAKEUP_GET(x) (((x) & SDIO_WRAPPER_WAKEUP_MASK) >> SDIO_WRAPPER_WAKEUP_LSB) +#define SDIO_WRAPPER_WAKEUP_SET(x) (((x) << SDIO_WRAPPER_WAKEUP_LSB) & SDIO_WRAPPER_WAKEUP_MASK) +#define SDIO_WRAPPER_SOC_ON_MSB 1 +#define SDIO_WRAPPER_SOC_ON_LSB 1 +#define SDIO_WRAPPER_SOC_ON_MASK 0x00000002 +#define SDIO_WRAPPER_SOC_ON_GET(x) (((x) & SDIO_WRAPPER_SOC_ON_MASK) >> SDIO_WRAPPER_SOC_ON_LSB) +#define SDIO_WRAPPER_SOC_ON_SET(x) (((x) << SDIO_WRAPPER_SOC_ON_LSB) & SDIO_WRAPPER_SOC_ON_MASK) +#define SDIO_WRAPPER_ON_MSB 0 +#define SDIO_WRAPPER_ON_LSB 0 +#define SDIO_WRAPPER_ON_MASK 0x00000001 +#define SDIO_WRAPPER_ON_GET(x) (((x) & SDIO_WRAPPER_ON_MASK) >> SDIO_WRAPPER_ON_LSB) +#define SDIO_WRAPPER_ON_SET(x) (((x) << SDIO_WRAPPER_ON_LSB) & SDIO_WRAPPER_ON_MASK) + +#define MAC_SLEEP_CONTROL_ADDRESS 0x000000cc +#define MAC_SLEEP_CONTROL_OFFSET 0x000000cc +#define MAC_SLEEP_CONTROL_ENABLE_MSB 1 +#define MAC_SLEEP_CONTROL_ENABLE_LSB 0 +#define MAC_SLEEP_CONTROL_ENABLE_MASK 0x00000003 +#define MAC_SLEEP_CONTROL_ENABLE_GET(x) (((x) & MAC_SLEEP_CONTROL_ENABLE_MASK) >> MAC_SLEEP_CONTROL_ENABLE_LSB) +#define MAC_SLEEP_CONTROL_ENABLE_SET(x) (((x) << MAC_SLEEP_CONTROL_ENABLE_LSB) & MAC_SLEEP_CONTROL_ENABLE_MASK) + +#define KEEP_AWAKE_ADDRESS 0x000000d0 +#define KEEP_AWAKE_OFFSET 0x000000d0 +#define KEEP_AWAKE_COUNT_MSB 7 +#define KEEP_AWAKE_COUNT_LSB 0 +#define KEEP_AWAKE_COUNT_MASK 0x000000ff +#define KEEP_AWAKE_COUNT_GET(x) (((x) & KEEP_AWAKE_COUNT_MASK) >> KEEP_AWAKE_COUNT_LSB) +#define KEEP_AWAKE_COUNT_SET(x) (((x) << KEEP_AWAKE_COUNT_LSB) & KEEP_AWAKE_COUNT_MASK) + +#define LPO_CAL_TIME_ADDRESS 0x000000d4 +#define LPO_CAL_TIME_OFFSET 0x000000d4 +#define LPO_CAL_TIME_LENGTH_MSB 13 +#define LPO_CAL_TIME_LENGTH_LSB 0 +#define LPO_CAL_TIME_LENGTH_MASK 0x00003fff +#define LPO_CAL_TIME_LENGTH_GET(x) (((x) & LPO_CAL_TIME_LENGTH_MASK) >> LPO_CAL_TIME_LENGTH_LSB) +#define LPO_CAL_TIME_LENGTH_SET(x) (((x) << LPO_CAL_TIME_LENGTH_LSB) & LPO_CAL_TIME_LENGTH_MASK) + +#define LPO_INIT_DIVIDEND_INT_ADDRESS 0x000000d8 +#define LPO_INIT_DIVIDEND_INT_OFFSET 0x000000d8 +#define LPO_INIT_DIVIDEND_INT_VALUE_MSB 23 +#define LPO_INIT_DIVIDEND_INT_VALUE_LSB 0 +#define LPO_INIT_DIVIDEND_INT_VALUE_MASK 0x00ffffff +#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> LPO_INIT_DIVIDEND_INT_VALUE_LSB) +#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_INT_VALUE_LSB) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) + +#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS 0x000000dc +#define LPO_INIT_DIVIDEND_FRACTION_OFFSET 0x000000dc +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10 +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0 +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) + +#define LPO_CAL_ADDRESS 0x000000e0 +#define LPO_CAL_OFFSET 0x000000e0 +#define LPO_CAL_ENABLE_MSB 20 +#define LPO_CAL_ENABLE_LSB 20 +#define LPO_CAL_ENABLE_MASK 0x00100000 +#define LPO_CAL_ENABLE_GET(x) (((x) & LPO_CAL_ENABLE_MASK) >> LPO_CAL_ENABLE_LSB) +#define LPO_CAL_ENABLE_SET(x) (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK) +#define LPO_CAL_COUNT_MSB 19 +#define LPO_CAL_COUNT_LSB 0 +#define LPO_CAL_COUNT_MASK 0x000fffff +#define LPO_CAL_COUNT_GET(x) (((x) & LPO_CAL_COUNT_MASK) >> LPO_CAL_COUNT_LSB) +#define LPO_CAL_COUNT_SET(x) (((x) << LPO_CAL_COUNT_LSB) & LPO_CAL_COUNT_MASK) + +#define LPO_CAL_TEST_CONTROL_ADDRESS 0x000000e4 +#define LPO_CAL_TEST_CONTROL_OFFSET 0x000000e4 +#define LPO_CAL_TEST_CONTROL_ENABLE_MSB 5 +#define LPO_CAL_TEST_CONTROL_ENABLE_LSB 5 +#define LPO_CAL_TEST_CONTROL_ENABLE_MASK 0x00000020 +#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) (((x) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> LPO_CAL_TEST_CONTROL_ENABLE_LSB) +#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) (((x) << LPO_CAL_TEST_CONTROL_ENABLE_LSB) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4 +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0 +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) + +#define LPO_CAL_TEST_STATUS_ADDRESS 0x000000e8 +#define LPO_CAL_TEST_STATUS_OFFSET 0x000000e8 +#define LPO_CAL_TEST_STATUS_READY_MSB 16 +#define LPO_CAL_TEST_STATUS_READY_LSB 16 +#define LPO_CAL_TEST_STATUS_READY_MASK 0x00010000 +#define LPO_CAL_TEST_STATUS_READY_GET(x) (((x) & LPO_CAL_TEST_STATUS_READY_MASK) >> LPO_CAL_TEST_STATUS_READY_LSB) +#define LPO_CAL_TEST_STATUS_READY_SET(x) (((x) << LPO_CAL_TEST_STATUS_READY_LSB) & LPO_CAL_TEST_STATUS_READY_MASK) +#define LPO_CAL_TEST_STATUS_COUNT_MSB 15 +#define LPO_CAL_TEST_STATUS_COUNT_LSB 0 +#define LPO_CAL_TEST_STATUS_COUNT_MASK 0x0000ffff +#define LPO_CAL_TEST_STATUS_COUNT_GET(x) (((x) & LPO_CAL_TEST_STATUS_COUNT_MASK) >> LPO_CAL_TEST_STATUS_COUNT_LSB) +#define LPO_CAL_TEST_STATUS_COUNT_SET(x) (((x) << LPO_CAL_TEST_STATUS_COUNT_LSB) & LPO_CAL_TEST_STATUS_COUNT_MASK) + +#define CHIP_ID_ADDRESS 0x000000ec +#define CHIP_ID_OFFSET 0x000000ec +#define CHIP_ID_DEVICE_ID_MSB 31 +#define CHIP_ID_DEVICE_ID_LSB 16 +#define CHIP_ID_DEVICE_ID_MASK 0xffff0000 +#define CHIP_ID_DEVICE_ID_GET(x) (((x) & CHIP_ID_DEVICE_ID_MASK) >> CHIP_ID_DEVICE_ID_LSB) +#define CHIP_ID_DEVICE_ID_SET(x) (((x) << CHIP_ID_DEVICE_ID_LSB) & CHIP_ID_DEVICE_ID_MASK) +#define CHIP_ID_CONFIG_ID_MSB 15 +#define CHIP_ID_CONFIG_ID_LSB 4 +#define CHIP_ID_CONFIG_ID_MASK 0x0000fff0 +#define CHIP_ID_CONFIG_ID_GET(x) (((x) & CHIP_ID_CONFIG_ID_MASK) >> CHIP_ID_CONFIG_ID_LSB) +#define CHIP_ID_CONFIG_ID_SET(x) (((x) << CHIP_ID_CONFIG_ID_LSB) & CHIP_ID_CONFIG_ID_MASK) +#define CHIP_ID_VERSION_ID_MSB 3 +#define CHIP_ID_VERSION_ID_LSB 0 +#define CHIP_ID_VERSION_ID_MASK 0x0000000f +#define CHIP_ID_VERSION_ID_GET(x) (((x) & CHIP_ID_VERSION_ID_MASK) >> CHIP_ID_VERSION_ID_LSB) +#define CHIP_ID_VERSION_ID_SET(x) (((x) << CHIP_ID_VERSION_ID_LSB) & CHIP_ID_VERSION_ID_MASK) + +#define DERIVED_RTC_CLK_ADDRESS 0x000000f0 +#define DERIVED_RTC_CLK_OFFSET 0x000000f0 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) +#define DERIVED_RTC_CLK_FORCE_MSB 17 +#define DERIVED_RTC_CLK_FORCE_LSB 16 +#define DERIVED_RTC_CLK_FORCE_MASK 0x00030000 +#define DERIVED_RTC_CLK_FORCE_GET(x) (((x) & DERIVED_RTC_CLK_FORCE_MASK) >> DERIVED_RTC_CLK_FORCE_LSB) +#define DERIVED_RTC_CLK_FORCE_SET(x) (((x) << DERIVED_RTC_CLK_FORCE_LSB) & DERIVED_RTC_CLK_FORCE_MASK) +#define DERIVED_RTC_CLK_PERIOD_MSB 15 +#define DERIVED_RTC_CLK_PERIOD_LSB 1 +#define DERIVED_RTC_CLK_PERIOD_MASK 0x0000fffe +#define DERIVED_RTC_CLK_PERIOD_GET(x) (((x) & DERIVED_RTC_CLK_PERIOD_MASK) >> DERIVED_RTC_CLK_PERIOD_LSB) +#define DERIVED_RTC_CLK_PERIOD_SET(x) (((x) << DERIVED_RTC_CLK_PERIOD_LSB) & DERIVED_RTC_CLK_PERIOD_MASK) + +#define MAC_PCU_SLP32_MODE_ADDRESS 0x000000f4 +#define MAC_PCU_SLP32_MODE_OFFSET 0x000000f4 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK 0x00200000 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB 19 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB 0 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) + +#define MAC_PCU_SLP32_WAKE_ADDRESS 0x000000f8 +#define MAC_PCU_SLP32_WAKE_OFFSET 0x000000f8 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB 15 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB 0 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK 0x0000ffff +#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x) (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) +#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x) (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) + +#define MAC_PCU_SLP32_INC_ADDRESS 0x000000fc +#define MAC_PCU_SLP32_INC_OFFSET 0x000000fc +#define MAC_PCU_SLP32_INC_TSF_INC_MSB 19 +#define MAC_PCU_SLP32_INC_TSF_INC_LSB 0 +#define MAC_PCU_SLP32_INC_TSF_INC_MASK 0x000fffff +#define MAC_PCU_SLP32_INC_TSF_INC_GET(x) (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB) +#define MAC_PCU_SLP32_INC_TSF_INC_SET(x) (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK) + +#define MAC_PCU_SLP_MIB1_ADDRESS 0x00000100 +#define MAC_PCU_SLP_MIB1_OFFSET 0x00000100 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB 31 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB 0 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) + +#define MAC_PCU_SLP_MIB2_ADDRESS 0x00000104 +#define MAC_PCU_SLP_MIB2_OFFSET 0x00000104 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB 31 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB 0 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) + +#define MAC_PCU_SLP_MIB3_ADDRESS 0x00000108 +#define MAC_PCU_SLP_MIB3_OFFSET 0x00000108 +#define MAC_PCU_SLP_MIB3_PENDING_MSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_LSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_MASK 0x00000002 +#define MAC_PCU_SLP_MIB3_PENDING_GET(x) (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB) +#define MAC_PCU_SLP_MIB3_PENDING_SET(x) (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK) +#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK 0x00000001 +#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB) +#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) + +#define MAC_PCU_SLP_BEACON_ADDRESS 0x0000010c +#define MAC_PCU_SLP_BEACON_OFFSET 0x0000010c +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MSB 24 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB 24 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK 0x01000000 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MSB 23 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB 0 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK 0x00ffffff +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) + +#define POWER_REG_ADDRESS 0x00000110 +#define POWER_REG_OFFSET 0x00000110 +#define POWER_REG_VLVL_MSB 11 +#define POWER_REG_VLVL_LSB 8 +#define POWER_REG_VLVL_MASK 0x00000f00 +#define POWER_REG_VLVL_GET(x) (((x) & POWER_REG_VLVL_MASK) >> POWER_REG_VLVL_LSB) +#define POWER_REG_VLVL_SET(x) (((x) << POWER_REG_VLVL_LSB) & POWER_REG_VLVL_MASK) +#define POWER_REG_CPU_INT_ENABLE_MSB 7 +#define POWER_REG_CPU_INT_ENABLE_LSB 7 +#define POWER_REG_CPU_INT_ENABLE_MASK 0x00000080 +#define POWER_REG_CPU_INT_ENABLE_GET(x) (((x) & POWER_REG_CPU_INT_ENABLE_MASK) >> POWER_REG_CPU_INT_ENABLE_LSB) +#define POWER_REG_CPU_INT_ENABLE_SET(x) (((x) << POWER_REG_CPU_INT_ENABLE_LSB) & POWER_REG_CPU_INT_ENABLE_MASK) +#define POWER_REG_WLAN_ISO_DIS_MSB 6 +#define POWER_REG_WLAN_ISO_DIS_LSB 6 +#define POWER_REG_WLAN_ISO_DIS_MASK 0x00000040 +#define POWER_REG_WLAN_ISO_DIS_GET(x) (((x) & POWER_REG_WLAN_ISO_DIS_MASK) >> POWER_REG_WLAN_ISO_DIS_LSB) +#define POWER_REG_WLAN_ISO_DIS_SET(x) (((x) << POWER_REG_WLAN_ISO_DIS_LSB) & POWER_REG_WLAN_ISO_DIS_MASK) +#define POWER_REG_WLAN_ISO_CNTL_MSB 5 +#define POWER_REG_WLAN_ISO_CNTL_LSB 5 +#define POWER_REG_WLAN_ISO_CNTL_MASK 0x00000020 +#define POWER_REG_WLAN_ISO_CNTL_GET(x) (((x) & POWER_REG_WLAN_ISO_CNTL_MASK) >> POWER_REG_WLAN_ISO_CNTL_LSB) +#define POWER_REG_WLAN_ISO_CNTL_SET(x) (((x) << POWER_REG_WLAN_ISO_CNTL_LSB) & POWER_REG_WLAN_ISO_CNTL_MASK) +#define POWER_REG_RADIO_PWD_EN_MSB 4 +#define POWER_REG_RADIO_PWD_EN_LSB 4 +#define POWER_REG_RADIO_PWD_EN_MASK 0x00000010 +#define POWER_REG_RADIO_PWD_EN_GET(x) (((x) & POWER_REG_RADIO_PWD_EN_MASK) >> POWER_REG_RADIO_PWD_EN_LSB) +#define POWER_REG_RADIO_PWD_EN_SET(x) (((x) << POWER_REG_RADIO_PWD_EN_LSB) & POWER_REG_RADIO_PWD_EN_MASK) +#define POWER_REG_SOC_SCALE_EN_MSB 3 +#define POWER_REG_SOC_SCALE_EN_LSB 3 +#define POWER_REG_SOC_SCALE_EN_MASK 0x00000008 +#define POWER_REG_SOC_SCALE_EN_GET(x) (((x) & POWER_REG_SOC_SCALE_EN_MASK) >> POWER_REG_SOC_SCALE_EN_LSB) +#define POWER_REG_SOC_SCALE_EN_SET(x) (((x) << POWER_REG_SOC_SCALE_EN_LSB) & POWER_REG_SOC_SCALE_EN_MASK) +#define POWER_REG_WLAN_SCALE_EN_MSB 2 +#define POWER_REG_WLAN_SCALE_EN_LSB 2 +#define POWER_REG_WLAN_SCALE_EN_MASK 0x00000004 +#define POWER_REG_WLAN_SCALE_EN_GET(x) (((x) & POWER_REG_WLAN_SCALE_EN_MASK) >> POWER_REG_WLAN_SCALE_EN_LSB) +#define POWER_REG_WLAN_SCALE_EN_SET(x) (((x) << POWER_REG_WLAN_SCALE_EN_LSB) & POWER_REG_WLAN_SCALE_EN_MASK) +#define POWER_REG_WLAN_PWD_EN_MSB 1 +#define POWER_REG_WLAN_PWD_EN_LSB 1 +#define POWER_REG_WLAN_PWD_EN_MASK 0x00000002 +#define POWER_REG_WLAN_PWD_EN_GET(x) (((x) & POWER_REG_WLAN_PWD_EN_MASK) >> POWER_REG_WLAN_PWD_EN_LSB) +#define POWER_REG_WLAN_PWD_EN_SET(x) (((x) << POWER_REG_WLAN_PWD_EN_LSB) & POWER_REG_WLAN_PWD_EN_MASK) +#define POWER_REG_POWER_EN_MSB 0 +#define POWER_REG_POWER_EN_LSB 0 +#define POWER_REG_POWER_EN_MASK 0x00000001 +#define POWER_REG_POWER_EN_GET(x) (((x) & POWER_REG_POWER_EN_MASK) >> POWER_REG_POWER_EN_LSB) +#define POWER_REG_POWER_EN_SET(x) (((x) << POWER_REG_POWER_EN_LSB) & POWER_REG_POWER_EN_MASK) + +#define CORE_CLK_CTRL_ADDRESS 0x00000114 +#define CORE_CLK_CTRL_OFFSET 0x00000114 +#define CORE_CLK_CTRL_DIV_MSB 2 +#define CORE_CLK_CTRL_DIV_LSB 0 +#define CORE_CLK_CTRL_DIV_MASK 0x00000007 +#define CORE_CLK_CTRL_DIV_GET(x) (((x) & CORE_CLK_CTRL_DIV_MASK) >> CORE_CLK_CTRL_DIV_LSB) +#define CORE_CLK_CTRL_DIV_SET(x) (((x) << CORE_CLK_CTRL_DIV_LSB) & CORE_CLK_CTRL_DIV_MASK) + +#define SDIO_SETUP_CIRCUIT_ADDRESS 0x00000120 +#define SDIO_SETUP_CIRCUIT_OFFSET 0x00000120 +#define SDIO_SETUP_CIRCUIT_VECTOR_MSB 7 +#define SDIO_SETUP_CIRCUIT_VECTOR_LSB 0 +#define SDIO_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define SDIO_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) >> SDIO_SETUP_CIRCUIT_VECTOR_LSB) +#define SDIO_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << SDIO_SETUP_CIRCUIT_VECTOR_LSB) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) + +#define SDIO_SETUP_CONFIG_ADDRESS 0x00000140 +#define SDIO_SETUP_CONFIG_OFFSET 0x00000140 +#define SDIO_SETUP_CONFIG_ENABLE_MSB 1 +#define SDIO_SETUP_CONFIG_ENABLE_LSB 1 +#define SDIO_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define SDIO_SETUP_CONFIG_ENABLE_GET(x) (((x) & SDIO_SETUP_CONFIG_ENABLE_MASK) >> SDIO_SETUP_CONFIG_ENABLE_LSB) +#define SDIO_SETUP_CONFIG_ENABLE_SET(x) (((x) << SDIO_SETUP_CONFIG_ENABLE_LSB) & SDIO_SETUP_CONFIG_ENABLE_MASK) +#define SDIO_SETUP_CONFIG_CLEAR_MSB 0 +#define SDIO_SETUP_CONFIG_CLEAR_LSB 0 +#define SDIO_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define SDIO_SETUP_CONFIG_CLEAR_GET(x) (((x) & SDIO_SETUP_CONFIG_CLEAR_MASK) >> SDIO_SETUP_CONFIG_CLEAR_LSB) +#define SDIO_SETUP_CONFIG_CLEAR_SET(x) (((x) << SDIO_SETUP_CONFIG_CLEAR_LSB) & SDIO_SETUP_CONFIG_CLEAR_MASK) + +#define CPU_SETUP_CONFIG_ADDRESS 0x00000144 +#define CPU_SETUP_CONFIG_OFFSET 0x00000144 +#define CPU_SETUP_CONFIG_ENABLE_MSB 1 +#define CPU_SETUP_CONFIG_ENABLE_LSB 1 +#define CPU_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define CPU_SETUP_CONFIG_ENABLE_GET(x) (((x) & CPU_SETUP_CONFIG_ENABLE_MASK) >> CPU_SETUP_CONFIG_ENABLE_LSB) +#define CPU_SETUP_CONFIG_ENABLE_SET(x) (((x) << CPU_SETUP_CONFIG_ENABLE_LSB) & CPU_SETUP_CONFIG_ENABLE_MASK) +#define CPU_SETUP_CONFIG_CLEAR_MSB 0 +#define CPU_SETUP_CONFIG_CLEAR_LSB 0 +#define CPU_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define CPU_SETUP_CONFIG_CLEAR_GET(x) (((x) & CPU_SETUP_CONFIG_CLEAR_MASK) >> CPU_SETUP_CONFIG_CLEAR_LSB) +#define CPU_SETUP_CONFIG_CLEAR_SET(x) (((x) << CPU_SETUP_CONFIG_CLEAR_LSB) & CPU_SETUP_CONFIG_CLEAR_MASK) + +#define CPU_SETUP_CIRCUIT_ADDRESS 0x00000160 +#define CPU_SETUP_CIRCUIT_OFFSET 0x00000160 +#define CPU_SETUP_CIRCUIT_VECTOR_MSB 7 +#define CPU_SETUP_CIRCUIT_VECTOR_LSB 0 +#define CPU_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define CPU_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & CPU_SETUP_CIRCUIT_VECTOR_MASK) >> CPU_SETUP_CIRCUIT_VECTOR_LSB) +#define CPU_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << CPU_SETUP_CIRCUIT_VECTOR_LSB) & CPU_SETUP_CIRCUIT_VECTOR_MASK) + +#define BB_SETUP_CONFIG_ADDRESS 0x00000180 +#define BB_SETUP_CONFIG_OFFSET 0x00000180 +#define BB_SETUP_CONFIG_ENABLE_MSB 1 +#define BB_SETUP_CONFIG_ENABLE_LSB 1 +#define BB_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define BB_SETUP_CONFIG_ENABLE_GET(x) (((x) & BB_SETUP_CONFIG_ENABLE_MASK) >> BB_SETUP_CONFIG_ENABLE_LSB) +#define BB_SETUP_CONFIG_ENABLE_SET(x) (((x) << BB_SETUP_CONFIG_ENABLE_LSB) & BB_SETUP_CONFIG_ENABLE_MASK) +#define BB_SETUP_CONFIG_CLEAR_MSB 0 +#define BB_SETUP_CONFIG_CLEAR_LSB 0 +#define BB_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define BB_SETUP_CONFIG_CLEAR_GET(x) (((x) & BB_SETUP_CONFIG_CLEAR_MASK) >> BB_SETUP_CONFIG_CLEAR_LSB) +#define BB_SETUP_CONFIG_CLEAR_SET(x) (((x) << BB_SETUP_CONFIG_CLEAR_LSB) & BB_SETUP_CONFIG_CLEAR_MASK) + +#define BB_SETUP_CIRCUIT_ADDRESS 0x000001a0 +#define BB_SETUP_CIRCUIT_OFFSET 0x000001a0 +#define BB_SETUP_CIRCUIT_VECTOR_MSB 7 +#define BB_SETUP_CIRCUIT_VECTOR_LSB 0 +#define BB_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define BB_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & BB_SETUP_CIRCUIT_VECTOR_MASK) >> BB_SETUP_CIRCUIT_VECTOR_LSB) +#define BB_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << BB_SETUP_CIRCUIT_VECTOR_LSB) & BB_SETUP_CIRCUIT_VECTOR_MASK) + +#define GPIO_WAKEUP_CONTROL_ADDRESS 0x000001c0 +#define GPIO_WAKEUP_CONTROL_OFFSET 0x000001c0 +#define GPIO_WAKEUP_CONTROL_ENABLE_MSB 0 +#define GPIO_WAKEUP_CONTROL_ENABLE_LSB 0 +#define GPIO_WAKEUP_CONTROL_ENABLE_MASK 0x00000001 +#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) (((x) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> GPIO_WAKEUP_CONTROL_ENABLE_LSB) +#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) (((x) << GPIO_WAKEUP_CONTROL_ENABLE_LSB) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct rtc_reg_reg_s { + volatile unsigned int reset_control; + volatile unsigned int xtal_control; + volatile unsigned int tcxo_detect; + volatile unsigned int xtal_test; + volatile unsigned int quadrature; + volatile unsigned int pll_control; + volatile unsigned int pll_settle; + volatile unsigned int xtal_settle; + volatile unsigned int cpu_clock; + volatile unsigned int clock_out; + volatile unsigned int clock_control; + volatile unsigned int bias_override; + volatile unsigned int wdt_control; + volatile unsigned int wdt_status; + volatile unsigned int wdt; + volatile unsigned int wdt_count; + volatile unsigned int wdt_reset; + volatile unsigned int int_status; + volatile unsigned int lf_timer0; + volatile unsigned int lf_timer_count0; + volatile unsigned int lf_timer_control0; + volatile unsigned int lf_timer_status0; + volatile unsigned int lf_timer1; + volatile unsigned int lf_timer_count1; + volatile unsigned int lf_timer_control1; + volatile unsigned int lf_timer_status1; + volatile unsigned int lf_timer2; + volatile unsigned int lf_timer_count2; + volatile unsigned int lf_timer_control2; + volatile unsigned int lf_timer_status2; + volatile unsigned int lf_timer3; + volatile unsigned int lf_timer_count3; + volatile unsigned int lf_timer_control3; + volatile unsigned int lf_timer_status3; + volatile unsigned int hf_timer; + volatile unsigned int hf_timer_count; + volatile unsigned int hf_lf_count; + volatile unsigned int hf_timer_control; + volatile unsigned int hf_timer_status; + volatile unsigned int rtc_control; + volatile unsigned int rtc_time; + volatile unsigned int rtc_date; + volatile unsigned int rtc_set_time; + volatile unsigned int rtc_set_date; + volatile unsigned int rtc_set_alarm; + volatile unsigned int rtc_config; + volatile unsigned int rtc_alarm_status; + volatile unsigned int uart_wakeup; + volatile unsigned int reset_cause; + volatile unsigned int system_sleep; + volatile unsigned int sdio_wrapper; + volatile unsigned int mac_sleep_control; + volatile unsigned int keep_awake; + volatile unsigned int lpo_cal_time; + volatile unsigned int lpo_init_dividend_int; + volatile unsigned int lpo_init_dividend_fraction; + volatile unsigned int lpo_cal; + volatile unsigned int lpo_cal_test_control; + volatile unsigned int lpo_cal_test_status; + volatile unsigned int chip_id; + volatile unsigned int derived_rtc_clk; + volatile unsigned int mac_pcu_slp32_mode; + volatile unsigned int mac_pcu_slp32_wake; + volatile unsigned int mac_pcu_slp32_inc; + volatile unsigned int mac_pcu_slp_mib1; + volatile unsigned int mac_pcu_slp_mib2; + volatile unsigned int mac_pcu_slp_mib3; + volatile unsigned int mac_pcu_slp_beacon; + volatile unsigned int power_reg; + volatile unsigned int core_clk_ctrl; + unsigned char pad0[8]; /* pad to 0x120 */ + volatile unsigned int sdio_setup_circuit[8]; + volatile unsigned int sdio_setup_config; + volatile unsigned int cpu_setup_config; + unsigned char pad1[24]; /* pad to 0x160 */ + volatile unsigned int cpu_setup_circuit[8]; + volatile unsigned int bb_setup_config; + unsigned char pad2[28]; /* pad to 0x1a0 */ + volatile unsigned int bb_setup_circuit[8]; + volatile unsigned int gpio_wakeup_control; +} rtc_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _RTC_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/si_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/si_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k22/si_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/si_reg.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,209 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _SI_REG_REG_H_ +#define _SI_REG_REG_H_ + +#define SI_CONFIG_ADDRESS 0x00000000 +#define SI_CONFIG_OFFSET 0x00000000 +#define SI_CONFIG_ERR_INT_MSB 19 +#define SI_CONFIG_ERR_INT_LSB 19 +#define SI_CONFIG_ERR_INT_MASK 0x00080000 +#define SI_CONFIG_ERR_INT_GET(x) (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB) +#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK) +#define SI_CONFIG_BIDIR_OD_DATA_MSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_LSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 +#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB) +#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK) +#define SI_CONFIG_I2C_MSB 16 +#define SI_CONFIG_I2C_LSB 16 +#define SI_CONFIG_I2C_MASK 0x00010000 +#define SI_CONFIG_I2C_GET(x) (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB) +#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) +#define SI_CONFIG_POS_SAMPLE_MSB 7 +#define SI_CONFIG_POS_SAMPLE_LSB 7 +#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 +#define SI_CONFIG_POS_SAMPLE_GET(x) (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB) +#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK) +#define SI_CONFIG_POS_DRIVE_MSB 6 +#define SI_CONFIG_POS_DRIVE_LSB 6 +#define SI_CONFIG_POS_DRIVE_MASK 0x00000040 +#define SI_CONFIG_POS_DRIVE_GET(x) (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB) +#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK) +#define SI_CONFIG_INACTIVE_DATA_MSB 5 +#define SI_CONFIG_INACTIVE_DATA_LSB 5 +#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 +#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB) +#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK) +#define SI_CONFIG_INACTIVE_CLK_MSB 4 +#define SI_CONFIG_INACTIVE_CLK_LSB 4 +#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 +#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB) +#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK) +#define SI_CONFIG_DIVIDER_MSB 3 +#define SI_CONFIG_DIVIDER_LSB 0 +#define SI_CONFIG_DIVIDER_MASK 0x0000000f +#define SI_CONFIG_DIVIDER_GET(x) (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB) +#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) + +#define SI_CS_ADDRESS 0x00000004 +#define SI_CS_OFFSET 0x00000004 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) +#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) +#define SI_CS_DONE_ERR_MSB 10 +#define SI_CS_DONE_ERR_LSB 10 +#define SI_CS_DONE_ERR_MASK 0x00000400 +#define SI_CS_DONE_ERR_GET(x) (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB) +#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK) +#define SI_CS_DONE_INT_MSB 9 +#define SI_CS_DONE_INT_LSB 9 +#define SI_CS_DONE_INT_MASK 0x00000200 +#define SI_CS_DONE_INT_GET(x) (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB) +#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK) +#define SI_CS_START_MSB 8 +#define SI_CS_START_LSB 8 +#define SI_CS_START_MASK 0x00000100 +#define SI_CS_START_GET(x) (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB) +#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) +#define SI_CS_RX_CNT_MSB 7 +#define SI_CS_RX_CNT_LSB 4 +#define SI_CS_RX_CNT_MASK 0x000000f0 +#define SI_CS_RX_CNT_GET(x) (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB) +#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) +#define SI_CS_TX_CNT_MSB 3 +#define SI_CS_TX_CNT_LSB 0 +#define SI_CS_TX_CNT_MASK 0x0000000f +#define SI_CS_TX_CNT_GET(x) (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB) +#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) + +#define SI_TX_DATA0_ADDRESS 0x00000008 +#define SI_TX_DATA0_OFFSET 0x00000008 +#define SI_TX_DATA0_DATA3_MSB 31 +#define SI_TX_DATA0_DATA3_LSB 24 +#define SI_TX_DATA0_DATA3_MASK 0xff000000 +#define SI_TX_DATA0_DATA3_GET(x) (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB) +#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK) +#define SI_TX_DATA0_DATA2_MSB 23 +#define SI_TX_DATA0_DATA2_LSB 16 +#define SI_TX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_TX_DATA0_DATA2_GET(x) (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB) +#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK) +#define SI_TX_DATA0_DATA1_MSB 15 +#define SI_TX_DATA0_DATA1_LSB 8 +#define SI_TX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_TX_DATA0_DATA1_GET(x) (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB) +#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK) +#define SI_TX_DATA0_DATA0_MSB 7 +#define SI_TX_DATA0_DATA0_LSB 0 +#define SI_TX_DATA0_DATA0_MASK 0x000000ff +#define SI_TX_DATA0_DATA0_GET(x) (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB) +#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK) + +#define SI_TX_DATA1_ADDRESS 0x0000000c +#define SI_TX_DATA1_OFFSET 0x0000000c +#define SI_TX_DATA1_DATA7_MSB 31 +#define SI_TX_DATA1_DATA7_LSB 24 +#define SI_TX_DATA1_DATA7_MASK 0xff000000 +#define SI_TX_DATA1_DATA7_GET(x) (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB) +#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK) +#define SI_TX_DATA1_DATA6_MSB 23 +#define SI_TX_DATA1_DATA6_LSB 16 +#define SI_TX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_TX_DATA1_DATA6_GET(x) (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB) +#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK) +#define SI_TX_DATA1_DATA5_MSB 15 +#define SI_TX_DATA1_DATA5_LSB 8 +#define SI_TX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_TX_DATA1_DATA5_GET(x) (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB) +#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK) +#define SI_TX_DATA1_DATA4_MSB 7 +#define SI_TX_DATA1_DATA4_LSB 0 +#define SI_TX_DATA1_DATA4_MASK 0x000000ff +#define SI_TX_DATA1_DATA4_GET(x) (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB) +#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK) + +#define SI_RX_DATA0_ADDRESS 0x00000010 +#define SI_RX_DATA0_OFFSET 0x00000010 +#define SI_RX_DATA0_DATA3_MSB 31 +#define SI_RX_DATA0_DATA3_LSB 24 +#define SI_RX_DATA0_DATA3_MASK 0xff000000 +#define SI_RX_DATA0_DATA3_GET(x) (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB) +#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK) +#define SI_RX_DATA0_DATA2_MSB 23 +#define SI_RX_DATA0_DATA2_LSB 16 +#define SI_RX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_RX_DATA0_DATA2_GET(x) (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB) +#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK) +#define SI_RX_DATA0_DATA1_MSB 15 +#define SI_RX_DATA0_DATA1_LSB 8 +#define SI_RX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_RX_DATA0_DATA1_GET(x) (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB) +#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK) +#define SI_RX_DATA0_DATA0_MSB 7 +#define SI_RX_DATA0_DATA0_LSB 0 +#define SI_RX_DATA0_DATA0_MASK 0x000000ff +#define SI_RX_DATA0_DATA0_GET(x) (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB) +#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK) + +#define SI_RX_DATA1_ADDRESS 0x00000014 +#define SI_RX_DATA1_OFFSET 0x00000014 +#define SI_RX_DATA1_DATA7_MSB 31 +#define SI_RX_DATA1_DATA7_LSB 24 +#define SI_RX_DATA1_DATA7_MASK 0xff000000 +#define SI_RX_DATA1_DATA7_GET(x) (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB) +#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK) +#define SI_RX_DATA1_DATA6_MSB 23 +#define SI_RX_DATA1_DATA6_LSB 16 +#define SI_RX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_RX_DATA1_DATA6_GET(x) (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB) +#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK) +#define SI_RX_DATA1_DATA5_MSB 15 +#define SI_RX_DATA1_DATA5_LSB 8 +#define SI_RX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_RX_DATA1_DATA5_GET(x) (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB) +#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK) +#define SI_RX_DATA1_DATA4_MSB 7 +#define SI_RX_DATA1_DATA4_LSB 0 +#define SI_RX_DATA1_DATA4_MASK 0x000000ff +#define SI_RX_DATA1_DATA4_GET(x) (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB) +#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct si_reg_reg_s { + volatile unsigned int si_config; + volatile unsigned int si_cs; + volatile unsigned int si_tx_data0; + volatile unsigned int si_tx_data1; + volatile unsigned int si_rx_data0; + volatile unsigned int si_rx_data1; +} si_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _SI_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/targaddrs.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/targaddrs.h --- linux-2.6.26/drivers/net/wireless/ath6k22/targaddrs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/targaddrs.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,202 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __TARGADDRS_H__ +#define __TARGADDRS_H__ +#if defined(AR6001) +#include "AR6001/addrs.h" +#endif +#if defined(AR6002) +#include "AR6002/addrs.h" +#endif + +/* + * AR6K option bits, to enable/disable various features. + * By default, all option bits are 0. + * These bits can be set in LOCAL_SCRATCH register 0. + */ +#define AR6K_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */ +#define AR6K_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */ +#define AR6K_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */ +#define AR6K_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */ +#define AR6K_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */ +#define AR6K_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */ +#define AR6K_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */ +#define AR6K_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */ + +/* + * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the + * host_interest structure. It must match the address of the _host_interest + * symbol (see linker script). + * + * Host Interest is shared between Host and Target in order to coordinate + * between the two, and is intended to remain constant (with additions only + * at the end) across software releases. + * + * All addresses are available here so that it's possible to + * write a single binary that works with all Target Types. + * May be used in assembler code as well as C. + */ +#define AR6001_HOST_INTEREST_ADDRESS 0x80000600 +#define AR6002_HOST_INTEREST_ADDRESS 0x00500400 +#define AR6003_HOST_INTEREST_ADDRESS 0x00540400 + + +#define HOST_INTEREST_MAX_SIZE 0x100 + +#if !defined(__ASSEMBLER__) +struct register_dump_s; +struct dbglog_hdr_s; + +/* + * These are items that the Host may need to access + * via BMI or via the Diagnostic Window. The position + * of items in this structure must remain constant + * across firmware revisions! + * + * Types for each item must be fixed size across + * target and host platforms. + * + * More items may be added at the end. + */ +struct host_interest_s { + /* + * Pointer to application-defined area, if any. + * Set by Target application during startup. + */ + A_UINT32 hi_app_host_interest; /* 0x00 */ + + /* Pointer to register dump area, valid after Target crash. */ + A_UINT32 hi_failure_state; /* 0x04 */ + + /* Pointer to debug logging header */ + A_UINT32 hi_dbglog_hdr; /* 0x08 */ + + /* Indicates whether or not flash is present on Target. + * NB: flash_is_present indicator is here not just + * because it might be of interest to the Host; but + * also because it's set early on by Target's startup + * asm code and we need it to have a special RAM address + * so that it doesn't get reinitialized with the rest + * of data. + */ + A_UINT32 hi_flash_is_present; /* 0x0c */ + + /* + * General-purpose flag bits, similar to AR6000_OPTION_* flags. + * Can be used by application rather than by OS. + */ + A_UINT32 hi_option_flag; /* 0x10 */ + + /* + * Boolean that determines whether or not to + * display messages on the serial port. + */ + A_UINT32 hi_serial_enable; /* 0x14 */ + + /* Start address of Flash DataSet index, if any */ + A_UINT32 hi_dset_list_head; /* 0x18 */ + + /* Override Target application start address */ + A_UINT32 hi_app_start; /* 0x1c */ + + /* Clock and voltage tuning */ + A_UINT32 hi_skip_clock_init; /* 0x20 */ + A_UINT32 hi_core_clock_setting; /* 0x24 */ + A_UINT32 hi_cpu_clock_setting; /* 0x28 */ + A_UINT32 hi_system_sleep_setting; /* 0x2c */ + A_UINT32 hi_xtal_control_setting; /* 0x30 */ + A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ + A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ + A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */ + A_UINT32 hi_clock_info; /* 0x40 */ + + /* + * Flash configuration overrides, used only + * when firmware is not executing from flash. + * (When using flash, modify the global variables + * with equivalent names.) + */ + A_UINT32 hi_bank0_addr_value; /* 0x44 */ + A_UINT32 hi_bank0_read_value; /* 0x48 */ + A_UINT32 hi_bank0_write_value; /* 0x4c */ + A_UINT32 hi_bank0_config_value; /* 0x50 */ + + /* Pointer to Board Data */ + A_UINT32 hi_board_data; /* 0x54 */ + A_UINT32 hi_board_data_initialized; /* 0x58 */ + + A_UINT32 hi_dset_RAM_index_table; /* 0x5c */ + + A_UINT32 hi_desired_baud_rate; /* 0x60 */ + A_UINT32 hi_dbglog_config; /* 0x64 */ + A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */ + A_UINT32 hi_mbox_io_block_sz; /* 0x6c */ + + A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */ + A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */ + + A_UINT32 hi_refclk_hz; /* 0x78 */ + A_UINT32 hi_ext_clk_detected; /* 0x7c */ +}; + +/* Bits defined in hi_option_flag */ +#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */ +#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */ +#define HI_OPTION_RELAY_DOT11_HDR 0x04 /*Relay Dot11 hdr to/from host */ + +/* 2 bits of hi_option_flag are used to represent 3 modes */ +#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */ +#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */ +#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */ + +/* Fw Mode Mask */ +#define HI_OPTION_FW_MODE_MASK 0x3 +#define HI_OPTION_FW_MODE_SHIFT 0x3 + +/* + * Intended for use by Host software, this macro returns the Target RAM + * address of any item in the host_interest structure. + * Example: target_addr = AR6001_HOST_INTEREST_ITEM_ADDRESS(hi_board_data); + */ +#define AR6001_HOST_INTEREST_ITEM_ADDRESS(item) \ + ((A_UINT32)&((((struct host_interest_s *)(AR6001_HOST_INTEREST_ADDRESS))->item))) + +#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \ + ((A_UINT32)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item))) + +#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \ + ((A_UINT32)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item))) + +/* Convert a Target virtual address into a Target physical address */ +#define AR6001_VTOP(vaddr) ((vaddr) & 0x0fffffff) +#define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff) +#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff) +#define TARG_VTOP(TargetType, vaddr) \ + (((TargetType) == TARGET_TYPE_AR6001) ? AR6001_VTOP(vaddr) : \ + (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : AR6003_VTOP(vaddr))) + + +#endif /* !__ASSEMBLER__ */ + +#endif /* __TARGADDRS_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/testcmd.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/testcmd.h --- linux-2.6.26/drivers/net/wireless/ath6k22/testcmd.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/testcmd.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,165 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2005 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef TESTCMD_H_ +#define TESTCMD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ZEROES_PATTERN = 0, + ONES_PATTERN, + REPEATING_10, + PN7_PATTERN, + PN9_PATTERN, + PN15_PATTERN +}TX_DATA_PATTERN; + +/* Continous tx + mode : TCMD_CONT_TX_OFF - Disabling continous tx + TCMD_CONT_TX_SINE - Enable continuous unmodulated tx + TCMD_CONT_TX_FRAME- Enable continuous modulated tx + freq : Channel freq in Mhz. (e.g 2412 for channel 1 in 11 g) +dataRate: 0 - 1 Mbps + 1 - 2 Mbps + 2 - 5.5 Mbps + 3 - 11 Mbps + 4 - 6 Mbps + 5 - 9 Mbps + 6 - 12 Mbps + 7 - 18 Mbps + 8 - 24 Mbps + 9 - 36 Mbps + 10 - 28 Mbps + 11 - 54 Mbps + txPwr: Tx power in dBm[5 -11] for unmod Tx, [5-14] for mod Tx +antenna: 1 - one antenna + 2 - two antenna +Note : Enable/disable continuous tx test cmd works only when target is awake. +*/ + +typedef enum { + TCMD_CONT_TX_OFF = 0, + TCMD_CONT_TX_SINE, + TCMD_CONT_TX_FRAME, + TCMD_CONT_TX_TX99, + TCMD_CONT_TX_TX100 +} TCMD_CONT_TX_MODE; + +typedef PREPACK struct { + A_UINT32 testCmdId; + A_UINT32 mode; + A_UINT32 freq; + A_UINT32 dataRate; + A_INT32 txPwr; + A_UINT32 antenna; + A_UINT32 enANI; + A_UINT32 scramblerOff; + A_UINT32 aifsn; + A_UINT16 pktSz; + A_UINT16 txPattern; +} POSTPACK TCMD_CONT_TX; + +#define TCMD_TXPATTERN_ZERONE 0x1 +#define TCMD_TXPATTERN_ZERONE_DIS_SCRAMBLE 0x2 + +/* Continuous Rx + act: TCMD_CONT_RX_PROMIS - promiscuous mode (accept all incoming frames) + TCMD_CONT_RX_FILTER - filter mode (accept only frames with dest + address equal specified + mac address (set via act =3) + TCMD_CONT_RX_REPORT off mode (disable cont rx mode and get the + report from the last cont + Rx test) + + TCMD_CONT_RX_SETMAC - set MacAddr mode (sets the MAC address for the + target. This Overrides + the default MAC address.) + +*/ +typedef enum { + TCMD_CONT_RX_PROMIS =0, + TCMD_CONT_RX_FILTER, + TCMD_CONT_RX_REPORT, + TCMD_CONT_RX_SETMAC, + TCMD_CONT_RX_SET_ANT_SWITCH_TABLE +} TCMD_CONT_RX_ACT; + +typedef PREPACK struct { + A_UINT32 testCmdId; + A_UINT32 act; + A_UINT32 enANI; + PREPACK union { + struct PREPACK TCMD_CONT_RX_PARA { + A_UINT32 freq; + A_UINT32 antenna; + } POSTPACK para; + struct PREPACK TCMD_CONT_RX_REPORT { + A_UINT32 totalPkt; + A_INT32 rssiInDBm; + A_UINT32 crcErrPkt; + A_UINT32 secErrPkt; + } POSTPACK report; + struct PREPACK TCMD_CONT_RX_MAC { + A_UCHAR addr[ATH_MAC_LEN]; + } POSTPACK mac; + struct PREPACK TCMD_CONT_RX_ANT_SWITCH_TABLE { + A_UINT32 antswitch1; + A_UINT32 antswitch2; + }POSTPACK antswitchtable; + } POSTPACK u; +} POSTPACK TCMD_CONT_RX; + +/* Force sleep/wake test cmd + mode: TCMD_PM_WAKEUP - Wakeup the target + TCMD_PM_SLEEP - Force the target to sleep. + */ +typedef enum { + TCMD_PM_WAKEUP = 1, /* be consistent with target */ + TCMD_PM_SLEEP +} TCMD_PM_MODE; + +typedef PREPACK struct { + A_UINT32 testCmdId; + A_UINT32 mode; +} POSTPACK TCMD_PM; + +typedef enum { + TCMD_CONT_TX_ID, + TCMD_CONT_RX_ID, + TCMD_PM_ID +} TCMD_ID; + +typedef PREPACK union { + TCMD_CONT_TX contTx; + TCMD_CONT_RX contRx; + TCMD_PM pm; +} POSTPACK TEST_CMD; + +#ifdef __cplusplus +} +#endif + +#endif /* TESTCMD_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/uart_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/uart_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k22/uart_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/uart_reg.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,350 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _UART_REG_REG_H_ +#define _UART_REG_REG_H_ + +#define RBR_ADDRESS 0x00000000 +#define RBR_OFFSET 0x00000000 +#define RBR_RBR_MSB 7 +#define RBR_RBR_LSB 0 +#define RBR_RBR_MASK 0x000000ff +#define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB) +#define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK) + +#define THR_ADDRESS 0x00000000 +#define THR_OFFSET 0x00000000 +#define THR_THR_MSB 7 +#define THR_THR_LSB 0 +#define THR_THR_MASK 0x000000ff +#define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_THR_LSB) +#define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK) + +#define DLL_ADDRESS 0x00000000 +#define DLL_OFFSET 0x00000000 +#define DLL_DLL_MSB 7 +#define DLL_DLL_LSB 0 +#define DLL_DLL_MASK 0x000000ff +#define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB) +#define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK) + +#define DLH_ADDRESS 0x00000004 +#define DLH_OFFSET 0x00000004 +#define DLH_DLH_MSB 7 +#define DLH_DLH_LSB 0 +#define DLH_DLH_MASK 0x000000ff +#define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB) +#define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK) + +#define IER_ADDRESS 0x00000004 +#define IER_OFFSET 0x00000004 +#define IER_EDDSI_MSB 3 +#define IER_EDDSI_LSB 3 +#define IER_EDDSI_MASK 0x00000008 +#define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB) +#define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK) +#define IER_ELSI_MSB 2 +#define IER_ELSI_LSB 2 +#define IER_ELSI_MASK 0x00000004 +#define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB) +#define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK) +#define IER_ETBEI_MSB 1 +#define IER_ETBEI_LSB 1 +#define IER_ETBEI_MASK 0x00000002 +#define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB) +#define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK) +#define IER_ERBFI_MSB 0 +#define IER_ERBFI_LSB 0 +#define IER_ERBFI_MASK 0x00000001 +#define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB) +#define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK) + +#define IIR_ADDRESS 0x00000008 +#define IIR_OFFSET 0x00000008 +#define IIR_FIFO_STATUS_MSB 7 +#define IIR_FIFO_STATUS_LSB 6 +#define IIR_FIFO_STATUS_MASK 0x000000c0 +#define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB) +#define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK) +#define IIR_IID_MSB 3 +#define IIR_IID_LSB 0 +#define IIR_IID_MASK 0x0000000f +#define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_IID_LSB) +#define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK) + +#define FCR_ADDRESS 0x00000008 +#define FCR_OFFSET 0x00000008 +#define FCR_RCVR_TRIG_MSB 7 +#define FCR_RCVR_TRIG_LSB 6 +#define FCR_RCVR_TRIG_MASK 0x000000c0 +#define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB) +#define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK) +#define FCR_DMA_MODE_MSB 3 +#define FCR_DMA_MODE_LSB 3 +#define FCR_DMA_MODE_MASK 0x00000008 +#define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB) +#define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK) +#define FCR_XMIT_FIFO_RST_MSB 2 +#define FCR_XMIT_FIFO_RST_LSB 2 +#define FCR_XMIT_FIFO_RST_MASK 0x00000004 +#define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB) +#define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK) +#define FCR_RCVR_FIFO_RST_MSB 1 +#define FCR_RCVR_FIFO_RST_LSB 1 +#define FCR_RCVR_FIFO_RST_MASK 0x00000002 +#define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB) +#define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK) +#define FCR_FIFO_EN_MSB 0 +#define FCR_FIFO_EN_LSB 0 +#define FCR_FIFO_EN_MASK 0x00000001 +#define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB) +#define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK) + +#define LCR_ADDRESS 0x0000000c +#define LCR_OFFSET 0x0000000c +#define LCR_DLAB_MSB 7 +#define LCR_DLAB_LSB 7 +#define LCR_DLAB_MASK 0x00000080 +#define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB) +#define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK) +#define LCR_BREAK_MSB 6 +#define LCR_BREAK_LSB 6 +#define LCR_BREAK_MASK 0x00000040 +#define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB) +#define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK) +#define LCR_EPS_MSB 4 +#define LCR_EPS_LSB 4 +#define LCR_EPS_MASK 0x00000010 +#define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB) +#define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK) +#define LCR_PEN_MSB 3 +#define LCR_PEN_LSB 3 +#define LCR_PEN_MASK 0x00000008 +#define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB) +#define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK) +#define LCR_STOP_MSB 2 +#define LCR_STOP_LSB 2 +#define LCR_STOP_MASK 0x00000004 +#define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB) +#define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK) +#define LCR_CLS_MSB 1 +#define LCR_CLS_LSB 0 +#define LCR_CLS_MASK 0x00000003 +#define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB) +#define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK) + +#define MCR_ADDRESS 0x00000010 +#define MCR_OFFSET 0x00000010 +#define MCR_LOOPBACK_MSB 5 +#define MCR_LOOPBACK_LSB 5 +#define MCR_LOOPBACK_MASK 0x00000020 +#define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB) +#define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK) +#define MCR_OUT2_MSB 3 +#define MCR_OUT2_LSB 3 +#define MCR_OUT2_MASK 0x00000008 +#define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB) +#define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK) +#define MCR_OUT1_MSB 2 +#define MCR_OUT1_LSB 2 +#define MCR_OUT1_MASK 0x00000004 +#define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB) +#define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK) +#define MCR_RTS_MSB 1 +#define MCR_RTS_LSB 1 +#define MCR_RTS_MASK 0x00000002 +#define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB) +#define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK) +#define MCR_DTR_MSB 0 +#define MCR_DTR_LSB 0 +#define MCR_DTR_MASK 0x00000001 +#define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB) +#define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK) + +#define LSR_ADDRESS 0x00000014 +#define LSR_OFFSET 0x00000014 +#define LSR_FERR_MSB 7 +#define LSR_FERR_LSB 7 +#define LSR_FERR_MASK 0x00000080 +#define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB) +#define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK) +#define LSR_TEMT_MSB 6 +#define LSR_TEMT_LSB 6 +#define LSR_TEMT_MASK 0x00000040 +#define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB) +#define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK) +#define LSR_THRE_MSB 5 +#define LSR_THRE_LSB 5 +#define LSR_THRE_MASK 0x00000020 +#define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB) +#define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK) +#define LSR_BI_MSB 4 +#define LSR_BI_LSB 4 +#define LSR_BI_MASK 0x00000010 +#define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_LSB) +#define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK) +#define LSR_FE_MSB 3 +#define LSR_FE_LSB 3 +#define LSR_FE_MASK 0x00000008 +#define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_LSB) +#define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK) +#define LSR_PE_MSB 2 +#define LSR_PE_LSB 2 +#define LSR_PE_MASK 0x00000004 +#define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_LSB) +#define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK) +#define LSR_OE_MSB 1 +#define LSR_OE_LSB 1 +#define LSR_OE_MASK 0x00000002 +#define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_LSB) +#define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK) +#define LSR_DR_MSB 0 +#define LSR_DR_LSB 0 +#define LSR_DR_MASK 0x00000001 +#define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_LSB) +#define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK) + +#define MSR_ADDRESS 0x00000018 +#define MSR_OFFSET 0x00000018 +#define MSR_DCD_MSB 7 +#define MSR_DCD_LSB 7 +#define MSR_DCD_MASK 0x00000080 +#define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB) +#define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK) +#define MSR_RI_MSB 6 +#define MSR_RI_LSB 6 +#define MSR_RI_MASK 0x00000040 +#define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_LSB) +#define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK) +#define MSR_DSR_MSB 5 +#define MSR_DSR_LSB 5 +#define MSR_DSR_MASK 0x00000020 +#define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB) +#define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK) +#define MSR_CTS_MSB 4 +#define MSR_CTS_LSB 4 +#define MSR_CTS_MASK 0x00000010 +#define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB) +#define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK) +#define MSR_DDCD_MSB 3 +#define MSR_DDCD_LSB 3 +#define MSR_DDCD_MASK 0x00000008 +#define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB) +#define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK) +#define MSR_TERI_MSB 2 +#define MSR_TERI_LSB 2 +#define MSR_TERI_MASK 0x00000004 +#define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB) +#define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK) +#define MSR_DDSR_MSB 1 +#define MSR_DDSR_LSB 1 +#define MSR_DDSR_MASK 0x00000002 +#define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB) +#define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK) +#define MSR_DCTS_MSB 0 +#define MSR_DCTS_LSB 0 +#define MSR_DCTS_MASK 0x00000001 +#define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB) +#define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK) + +#define SCR_ADDRESS 0x0000001c +#define SCR_OFFSET 0x0000001c +#define SCR_SCR_MSB 7 +#define SCR_SCR_LSB 0 +#define SCR_SCR_MASK 0x000000ff +#define SCR_SCR_GET(x) (((x) & SCR_SCR_MASK) >> SCR_SCR_LSB) +#define SCR_SCR_SET(x) (((x) << SCR_SCR_LSB) & SCR_SCR_MASK) + +#define SRBR_ADDRESS 0x00000020 +#define SRBR_OFFSET 0x00000020 +#define SRBR_SRBR_MSB 7 +#define SRBR_SRBR_LSB 0 +#define SRBR_SRBR_MASK 0x000000ff +#define SRBR_SRBR_GET(x) (((x) & SRBR_SRBR_MASK) >> SRBR_SRBR_LSB) +#define SRBR_SRBR_SET(x) (((x) << SRBR_SRBR_LSB) & SRBR_SRBR_MASK) + +#define SIIR_ADDRESS 0x00000028 +#define SIIR_OFFSET 0x00000028 +#define SIIR_SIIR_MSB 7 +#define SIIR_SIIR_LSB 0 +#define SIIR_SIIR_MASK 0x000000ff +#define SIIR_SIIR_GET(x) (((x) & SIIR_SIIR_MASK) >> SIIR_SIIR_LSB) +#define SIIR_SIIR_SET(x) (((x) << SIIR_SIIR_LSB) & SIIR_SIIR_MASK) + +#define MWR_ADDRESS 0x0000002c +#define MWR_OFFSET 0x0000002c +#define MWR_MWR_MSB 31 +#define MWR_MWR_LSB 0 +#define MWR_MWR_MASK 0xffffffff +#define MWR_MWR_GET(x) (((x) & MWR_MWR_MASK) >> MWR_MWR_LSB) +#define MWR_MWR_SET(x) (((x) << MWR_MWR_LSB) & MWR_MWR_MASK) + +#define SLSR_ADDRESS 0x00000034 +#define SLSR_OFFSET 0x00000034 +#define SLSR_SLSR_MSB 7 +#define SLSR_SLSR_LSB 0 +#define SLSR_SLSR_MASK 0x000000ff +#define SLSR_SLSR_GET(x) (((x) & SLSR_SLSR_MASK) >> SLSR_SLSR_LSB) +#define SLSR_SLSR_SET(x) (((x) << SLSR_SLSR_LSB) & SLSR_SLSR_MASK) + +#define SMSR_ADDRESS 0x00000038 +#define SMSR_OFFSET 0x00000038 +#define SMSR_SMSR_MSB 7 +#define SMSR_SMSR_LSB 0 +#define SMSR_SMSR_MASK 0x000000ff +#define SMSR_SMSR_GET(x) (((x) & SMSR_SMSR_MASK) >> SMSR_SMSR_LSB) +#define SMSR_SMSR_SET(x) (((x) << SMSR_SMSR_LSB) & SMSR_SMSR_MASK) + +#define MRR_ADDRESS 0x0000003c +#define MRR_OFFSET 0x0000003c +#define MRR_MRR_MSB 31 +#define MRR_MRR_LSB 0 +#define MRR_MRR_MASK 0xffffffff +#define MRR_MRR_GET(x) (((x) & MRR_MRR_MASK) >> MRR_MRR_LSB) +#define MRR_MRR_SET(x) (((x) << MRR_MRR_LSB) & MRR_MRR_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct uart_reg_reg_s { + volatile unsigned int rbr; + volatile unsigned int dlh; + volatile unsigned int iir; + volatile unsigned int lcr; + volatile unsigned int mcr; + volatile unsigned int lsr; + volatile unsigned int msr; + volatile unsigned int scr; + volatile unsigned int srbr; + unsigned char pad0[4]; /* pad to 0x28 */ + volatile unsigned int siir; + volatile unsigned int mwr; + unsigned char pad1[4]; /* pad to 0x34 */ + volatile unsigned int slsr; + volatile unsigned int smsr; + volatile unsigned int mrr; +} uart_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _UART_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/vmc_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/vmc_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k22/vmc_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/vmc_reg.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,99 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _VMC_REG_REG_H_ +#define _VMC_REG_REG_H_ + +#define MC_TCAM_VALID_ADDRESS 0x00000000 +#define MC_TCAM_VALID_OFFSET 0x00000000 +#define MC_TCAM_VALID_BIT_MSB 0 +#define MC_TCAM_VALID_BIT_LSB 0 +#define MC_TCAM_VALID_BIT_MASK 0x00000001 +#define MC_TCAM_VALID_BIT_GET(x) (((x) & MC_TCAM_VALID_BIT_MASK) >> MC_TCAM_VALID_BIT_LSB) +#define MC_TCAM_VALID_BIT_SET(x) (((x) << MC_TCAM_VALID_BIT_LSB) & MC_TCAM_VALID_BIT_MASK) + +#define MC_TCAM_MASK_ADDRESS 0x00000080 +#define MC_TCAM_MASK_OFFSET 0x00000080 +#define MC_TCAM_MASK_SIZE_MSB 2 +#define MC_TCAM_MASK_SIZE_LSB 0 +#define MC_TCAM_MASK_SIZE_MASK 0x00000007 +#define MC_TCAM_MASK_SIZE_GET(x) (((x) & MC_TCAM_MASK_SIZE_MASK) >> MC_TCAM_MASK_SIZE_LSB) +#define MC_TCAM_MASK_SIZE_SET(x) (((x) << MC_TCAM_MASK_SIZE_LSB) & MC_TCAM_MASK_SIZE_MASK) + +#define MC_TCAM_COMPARE_ADDRESS 0x00000100 +#define MC_TCAM_COMPARE_OFFSET 0x00000100 +#define MC_TCAM_COMPARE_KEY_MSB 21 +#define MC_TCAM_COMPARE_KEY_LSB 5 +#define MC_TCAM_COMPARE_KEY_MASK 0x003fffe0 +#define MC_TCAM_COMPARE_KEY_GET(x) (((x) & MC_TCAM_COMPARE_KEY_MASK) >> MC_TCAM_COMPARE_KEY_LSB) +#define MC_TCAM_COMPARE_KEY_SET(x) (((x) << MC_TCAM_COMPARE_KEY_LSB) & MC_TCAM_COMPARE_KEY_MASK) + +#define MC_TCAM_TARGET_ADDRESS 0x00000180 +#define MC_TCAM_TARGET_OFFSET 0x00000180 +#define MC_TCAM_TARGET_ADDR_MSB 21 +#define MC_TCAM_TARGET_ADDR_LSB 5 +#define MC_TCAM_TARGET_ADDR_MASK 0x003fffe0 +#define MC_TCAM_TARGET_ADDR_GET(x) (((x) & MC_TCAM_TARGET_ADDR_MASK) >> MC_TCAM_TARGET_ADDR_LSB) +#define MC_TCAM_TARGET_ADDR_SET(x) (((x) << MC_TCAM_TARGET_ADDR_LSB) & MC_TCAM_TARGET_ADDR_MASK) + +#define ADDR_ERROR_CONTROL_ADDRESS 0x00000200 +#define ADDR_ERROR_CONTROL_OFFSET 0x00000200 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) +#define ADDR_ERROR_CONTROL_ENABLE_MSB 0 +#define ADDR_ERROR_CONTROL_ENABLE_LSB 0 +#define ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001 +#define ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_ENABLE_LSB) +#define ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_ENABLE_LSB) & ADDR_ERROR_CONTROL_ENABLE_MASK) + +#define ADDR_ERROR_STATUS_ADDRESS 0x00000204 +#define ADDR_ERROR_STATUS_OFFSET 0x00000204 +#define ADDR_ERROR_STATUS_WRITE_MSB 25 +#define ADDR_ERROR_STATUS_WRITE_LSB 25 +#define ADDR_ERROR_STATUS_WRITE_MASK 0x02000000 +#define ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & ADDR_ERROR_STATUS_WRITE_MASK) >> ADDR_ERROR_STATUS_WRITE_LSB) +#define ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << ADDR_ERROR_STATUS_WRITE_LSB) & ADDR_ERROR_STATUS_WRITE_MASK) +#define ADDR_ERROR_STATUS_ADDRESS_MSB 24 +#define ADDR_ERROR_STATUS_ADDRESS_LSB 0 +#define ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff +#define ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & ADDR_ERROR_STATUS_ADDRESS_MASK) >> ADDR_ERROR_STATUS_ADDRESS_LSB) +#define ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << ADDR_ERROR_STATUS_ADDRESS_LSB) & ADDR_ERROR_STATUS_ADDRESS_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct vmc_reg_reg_s { + volatile unsigned int mc_tcam_valid[32]; + volatile unsigned int mc_tcam_mask[32]; + volatile unsigned int mc_tcam_compare[32]; + volatile unsigned int mc_tcam_target[32]; + volatile unsigned int addr_error_control; + volatile unsigned int addr_error_status; +} vmc_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _VMC_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/wireless_ext.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wireless_ext.c --- linux-2.6.26/drivers/net/wireless/ath6k22/wireless_ext.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wireless_ext.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,2240 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#include "ar6000_drv.h" + +static A_UINT8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; +static void ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi); +extern unsigned int wmitimeout; +extern A_WAITQUEUE_HEAD arEvent; + + +#if WIRELESS_EXT > 14 +/* + * Encode a WPA or RSN information element as a custom + * element using the hostap format. + */ +static u_int +encode_ie(void *buf, size_t bufsize, + const u_int8_t *ie, size_t ielen, + const char *leader, size_t leader_len) +{ + u_int8_t *p; + int i; + + if (bufsize < leader_len) + return 0; + p = buf; + memcpy(p, leader, leader_len); + bufsize -= leader_len; + p += leader_len; + for (i = 0; i < ielen && bufsize > 2; i++) + { + p += sprintf(p, "%02x", ie[i]); + bufsize -= 2; + } + return (i == ielen ? p - (u_int8_t *)buf : 0); +} +#endif /* WIRELESS_EXT > 14 */ + +void +ar6000_scan_node(void *arg, bss_t *ni) +{ + struct iw_event iwe; +#if WIRELESS_EXT > 14 + char buf[600]; +#endif + struct ar_giwscan_param *param; + A_CHAR *current_ev; + A_CHAR *end_buf; + struct ieee80211_common_ie *cie; + A_CHAR *current_val; + A_INT32 j; + A_UINT32 rate_len, data_len = 0; + + param = (struct ar_giwscan_param *)arg; + + current_ev = param->current_ev; + end_buf = param->end_buf; + + cie = &ni->ni_cie; + + if ((end_buf - current_ev) > IW_EV_ADDR_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWAP; + iwe.u.ap_addr.sa_family = ARPHRD_ETHER; + A_MEMCPY(iwe.u.ap_addr.sa_data, ni->ni_macaddr, 6); + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + IW_EV_ADDR_LEN); + } + param->bytes_needed += IW_EV_ADDR_LEN; + + data_len = cie->ie_ssid[1] + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWESSID; + iwe.u.data.flags = 1; + iwe.u.data.length = cie->ie_ssid[1]; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + &cie->ie_ssid[2]); + } + param->bytes_needed += data_len; + + if (cie->ie_capInfo & (IEEE80211_CAPINFO_ESS|IEEE80211_CAPINFO_IBSS)) { + if ((end_buf - current_ev) > IW_EV_UINT_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWMODE; + iwe.u.mode = cie->ie_capInfo & IEEE80211_CAPINFO_ESS ? + IW_MODE_MASTER : IW_MODE_ADHOC; + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + IW_EV_UINT_LEN); + } + param->bytes_needed += IW_EV_UINT_LEN; + } + + if ((end_buf - current_ev) > IW_EV_FREQ_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWFREQ; + iwe.u.freq.m = cie->ie_chan * 100000; + iwe.u.freq.e = 1; + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + IW_EV_FREQ_LEN); + } + param->bytes_needed += IW_EV_FREQ_LEN; + + if ((end_buf - current_ev) > IW_EV_QUAL_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVQUAL; + ar6000_set_quality(&iwe.u.qual, ni->ni_snr); + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + IW_EV_QUAL_LEN); + } + param->bytes_needed += IW_EV_QUAL_LEN; + + if ((end_buf - current_ev) > IW_EV_POINT_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWENCODE; + if (cie->ie_capInfo & IEEE80211_CAPINFO_PRIVACY) { + iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; + } else { + iwe.u.data.flags = IW_ENCODE_DISABLED; + } + iwe.u.data.length = 0; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, ""); + } + param->bytes_needed += IW_EV_POINT_LEN; + + /* supported bit rate */ + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWRATE; + iwe.u.bitrate.fixed = 0; + iwe.u.bitrate.disabled = 0; + iwe.u.bitrate.value = 0; + current_val = current_ev + IW_EV_LCP_LEN; + param->bytes_needed += IW_EV_LCP_LEN; + + if (cie->ie_rates != NULL) { + rate_len = cie->ie_rates[1]; + data_len = (rate_len * (IW_EV_PARAM_LEN - IW_EV_LCP_LEN)); + if ((end_buf - current_ev) > data_len) + { + for (j = 0; j < rate_len; j++) { + unsigned char val; + val = cie->ie_rates[2 + j]; + iwe.u.bitrate.value = + (val >= 0x80)? ((val - 0x80) * 500000): (val * 500000); + current_val = iwe_stream_add_value( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, + current_val, + end_buf, + &iwe, + IW_EV_PARAM_LEN); + } + } + param->bytes_needed += data_len; + } + + if (cie->ie_xrates != NULL) { + rate_len = cie->ie_xrates[1]; + data_len = (rate_len * (IW_EV_PARAM_LEN - IW_EV_LCP_LEN)); + if ((end_buf - current_ev) > data_len) + { + for (j = 0; j < rate_len; j++) { + unsigned char val; + val = cie->ie_xrates[2 + j]; + iwe.u.bitrate.value = + (val >= 0x80)? ((val - 0x80) * 500000): (val * 500000); + current_val = iwe_stream_add_value( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, + current_val, + end_buf, + &iwe, + IW_EV_PARAM_LEN); + } + } + param->bytes_needed += data_len; + } + /* remove fixed header if no rates were added */ + if ((current_val - current_ev) > IW_EV_LCP_LEN) + current_ev = current_val; + +#if WIRELESS_EXT >= 18 + /* IE */ + if (cie->ie_wpa != NULL) { + data_len = cie->ie_wpa[1] + 2 + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVGENIE; + iwe.u.data.length = cie->ie_wpa[1] + 2; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, cie->ie_wpa); + } + param->bytes_needed += data_len; + } + + if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) { + data_len = cie->ie_rsn[1] + 2 + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVGENIE; + iwe.u.data.length = cie->ie_rsn[1] + 2; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, cie->ie_rsn); + } + param->bytes_needed += data_len; + } + +#endif /* WIRELESS_EXT >= 18 */ + + if ((end_buf - current_ev) > IW_EV_CHAR_LEN) + { + /* protocol */ + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWNAME; +#define CHAN_IS_11A(x) (!((x >= 2412) && (x <= 2484))) + if (CHAN_IS_11A(cie->ie_chan)) { + /* 11a */ + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11a"); + } else if ((cie->ie_erp) || (cie->ie_xrates)) { + /* 11g */ + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11g"); + } else { + /* 11b */ + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11b"); + } + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, IW_EV_CHAR_LEN); + } + param->bytes_needed += IW_EV_CHAR_LEN; + +#if WIRELESS_EXT > 14 + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = snprintf(buf, sizeof(buf), "bcn_int=%d", cie->ie_beaconInt); + data_len = iwe.u.data.length + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + param->bytes_needed += data_len; + +#if WIRELESS_EXT < 18 + if (cie->ie_wpa != NULL) { + static const char wpa_leader[] = "wpa_ie="; + data_len = (sizeof(wpa_leader) - 1) + ((cie->ie_wpa[1]+2) * 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wpa, + cie->ie_wpa[1]+2, + wpa_leader, sizeof(wpa_leader)-1); + + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + } + param->bytes_needed += data_len; + } + + if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) { + static const char rsn_leader[] = "rsn_ie="; + data_len = (sizeof(rsn_leader) - 1) + ((cie->ie_rsn[1]+2) * 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_rsn, + cie->ie_rsn[1]+2, + rsn_leader, sizeof(rsn_leader)-1); + + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + } + param->bytes_needed += data_len; + } +#endif /* WIRELESS_EXT < 18 */ + + if (cie->ie_wmm != NULL) { + static const char wmm_leader[] = "wmm_ie="; + data_len = (sizeof(wmm_leader) - 1) + ((cie->ie_wmm[1]+2) * 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wmm, + cie->ie_wmm[1]+2, + wmm_leader, sizeof(wmm_leader)-1); + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + } + param->bytes_needed += data_len; + } + + if (cie->ie_ath != NULL) { + static const char ath_leader[] = "ath_ie="; + data_len = (sizeof(ath_leader) - 1) + ((cie->ie_ath[1]+2) * 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_ath, + cie->ie_ath[1]+2, + ath_leader, sizeof(ath_leader)-1); + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + } + param->bytes_needed += data_len; + } + +#endif /* WIRELESS_EXT > 14 */ + +#if WIRELESS_EXT >= 18 + if (cie->ie_wsc != NULL) { + data_len = (cie->ie_wsc[1] + 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVGENIE; + iwe.u.data.length = cie->ie_wsc[1] + 2; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, cie->ie_wsc); + } + param->bytes_needed += data_len; + } +#endif /* WIRELESS_EXT >= 18 */ + + param->current_ev = current_ev; +} + +int +ar6000_ioctl_giwscan(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + struct ar_giwscan_param param; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + param.current_ev = extra; + param.end_buf = extra + data->length; + param.bytes_needed = 0; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param.info = info; +#endif + + /* Translate data to WE format */ + wmi_iterate_nodes(ar->arWmi, ar6000_scan_node, ¶m); + + /* check if bytes needed is greater than bytes consumed */ + if (param.bytes_needed > (param.current_ev - extra)) + { + /* Request one byte more than needed, because when "data->length" equals bytes_needed, + it is not possible to add the last event data as all iwe_stream_add_xxxxx() functions + checks whether (cur_ptr + ev_len) < end_ptr, due to this one more retry would happen*/ + data->length = param.bytes_needed + 1; + + return -E2BIG; + } + + return 0; +} + +extern int reconnect_flag; +/* SIOCSIWESSID */ +static int +ar6000_ioctl_siwessid(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *ssid) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_STATUS status; + A_UINT8 arNetworkType; + A_UINT8 prevMode = ar->arNetworkType; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + +#if defined(WIRELESS_EXT) + if (WIRELESS_EXT >= 20) { + data->length += 1; + } +#endif + + /* + * iwconfig passes a null terminated string with length including this + * so we need to account for this + */ + if (data->flags && (!data->length || (data->length == 1) || + ((data->length - 1) > sizeof(ar->arSsid)))) + { + /* + * ssid is invalid + */ + return -EINVAL; + } + + if (ar->arNextMode == AP_NETWORK) { + /* SSID change for AP network - Will take effect on commit */ + if(A_MEMCMP(ar->arSsid,ssid,32) != 0) { + ar->arSsidLen = data->length - 1; + A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen); + ar->ap_profile_flag = 1; /* There is a change in profile */ + } + return 0; + } else if(ar->arNetworkType == AP_NETWORK) { + A_UINT8 ctr; + struct sk_buff *skb; + + /* We are switching from AP to STA | IBSS mode, cleanup the AP state */ + for (ctr=0; ctr < AP_MAX_NUM_STA; ctr++) { + remove_sta(ar, ar->sta_list[ctr].mac, 0); + } + A_MUTEX_LOCK(&ar->mcastpsqLock); + while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) { + skb = A_NETBUF_DEQUEUE(&ar->mcastpsq); + A_NETBUF_FREE(skb); + } + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + } + + /* Added for bug 25178, return an IOCTL error instead of target returning + Illegal parameter error when either the BSSID or channel is missing + and we cannot scan during connect. + */ + if (data->flags) { + if (ar->arSkipScan == TRUE && + (ar->arChannelHint == 0 || + (!ar->arReqBssid[0] && !ar->arReqBssid[1] && !ar->arReqBssid[2] && + !ar->arReqBssid[3] && !ar->arReqBssid[4] && !ar->arReqBssid[5]))) + { + return -EINVAL; + } + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + if (ar->arTxPending[wmi_get_control_ep(ar->arWmi)]) { + /* + * sleep until the command queue drains + */ + wait_event_interruptible_timeout(arEvent, + ar->arTxPending[wmi_get_control_ep(ar->arWmi)] == 0, wmitimeout * HZ); + if (signal_pending(current)) { + return -EINTR; + } + } + + if (!data->flags) { + arNetworkType = ar->arNetworkType; + ar6000_init_profile_info(ar); + ar->arNetworkType = arNetworkType; + } + + /* Update the arNetworkType */ + ar->arNetworkType = ar->arNextMode; + + + if ((prevMode != AP_NETWORK) && ((ar->arSsidLen) || (!data->flags))) + { + if ((!data->flags) || + (A_MEMCMP(ar->arSsid, ssid, ar->arSsidLen) != 0) || + (ar->arSsidLen != (data->length - 1))) + { + /* + * SSID set previously or essid off has been issued. + * + * Disconnect Command is issued in two cases after wmi is ready + * (1) ssid is different from the previous setting + * (2) essid off has been issued + * + */ + if (ar->arWmiReady == TRUE) { + reconnect_flag = 0; + status = wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0); + status = wmi_disconnect_cmd(ar->arWmi); + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = 0; + if (ar->arSkipScan == FALSE) { + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + } + if (!data->flags) { + up(&ar->arSem); + return 0; + } + } else { + up(&ar->arSem); + } + } + else + { + /* + * SSID is same, so we assume profile hasn't changed. + * If the interface is up and wmi is ready, we issue + * a reconnect cmd. Issue a reconnect only we are already + * connected. + */ + if((ar->arConnected == TRUE) && (ar->arWmiReady == TRUE)) + { + reconnect_flag = TRUE; + status = wmi_reconnect_cmd(ar->arWmi,ar->arReqBssid, + ar->arChannelHint); + up(&ar->arSem); + if (status != A_OK) { + return -EIO; + } + return 0; + } + else{ + /* + * Dont return if connect is pending. + */ + if(!(ar->arConnectPending)) { + up(&ar->arSem); + return 0; + } + } + } + } + + ar->arSsidLen = data->length - 1; + A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen); + + /* The ssid length check prevents second "essid off" from the user, + to be treated as a connect cmd. The second "essid off" is ignored. + */ + if((ar->arWmiReady == TRUE) && (ar->arSsidLen > 0) ) + { + if((ADHOC_NETWORK != ar->arNetworkType) && + (NONE_AUTH==ar->arAuthMode) && + (WEP_CRYPT==ar->arPairwiseCrypto)) { + ar6000_install_static_wep_keys(ar); + } + + AR_DEBUG_PRINTF("Connect called with authmode %d dot11 auth %d"\ + " PW crypto %d PW crypto Len %d GRP crypto %d"\ + " GRP crypto Len %d ssid=%s\n", + ar->arAuthMode, ar->arDot11AuthMode, + ar->arPairwiseCrypto, ar->arPairwiseCryptoLen, + ar->arGroupCrypto, ar->arGroupCryptoLen, ar->arSsid); + reconnect_flag = 0; + status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType, + ar->arDot11AuthMode, ar->arAuthMode, + ar->arPairwiseCrypto, ar->arPairwiseCryptoLen, + ar->arGroupCrypto,ar->arGroupCryptoLen, + ar->arSsidLen, ar->arSsid, + ar->arReqBssid, ar->arChannelHint, + ar->arConnectCtrlFlags | CONNECT_IGNORE_WPAx_GROUP_CIPHER); + + + up(&ar->arSem); + + if (status != A_OK) { + return -EIO; + } + ar->arConnectPending = TRUE; + }else{ + up(&ar->arSem); + } + return 0; +} + +/* SIOCGIWESSID */ +static int +ar6000_ioctl_giwessid(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *essid) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (!ar->arSsidLen) { + return -EINVAL; + } + + data->flags = 1; + data->length = ar->arSsidLen; + A_MEMCPY(essid, ar->arSsid, ar->arSsidLen); + + return 0; +} + + +void ar6000_install_static_wep_keys(AR_SOFTC_T *ar) +{ + A_UINT8 index; + A_UINT8 keyUsage; + + for (index = WMI_MIN_KEY_INDEX; index <= WMI_MAX_KEY_INDEX; index++) { + if (ar->arWepKeyList[index].arKeyLen) { + keyUsage = GROUP_USAGE; + if (index == ar->arDefTxKeyIndex) { + keyUsage |= TX_USAGE; + } + wmi_addKey_cmd(ar->arWmi, + index, + WEP_CRYPT, + keyUsage, + ar->arWepKeyList[index].arKeyLen, + NULL, + ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL, NULL, + NO_SYNC_WMIFLAG); + } + } +} + +/* + * SIOCSIWRATE + */ +int +ar6000_ioctl_siwrate(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_UINT32 kbps; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (rrq->fixed) { + kbps = rrq->value / 1000; /* rrq->value is in bps */ + } else { + kbps = -1; /* -1 indicates auto rate */ + } + if(kbps != -1 && wmi_validate_bitrate(ar->arWmi, kbps) == A_EINVAL) + { + AR_DEBUG_PRINTF("BitRate is not Valid %d\n", kbps); + return -EINVAL; + } + ar->arBitRate = kbps; + if(ar->arWmiReady == TRUE) + { + if (wmi_set_bitrate_cmd(ar->arWmi, kbps, -1, -1) != A_OK) { + return -EINVAL; + } + } + return 0; +} + +/* + * SIOCGIWRATE + */ +int +ar6000_ioctl_giwrate(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + int ret = 0; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + if(ar->arWmiReady == TRUE) + { + ar->arBitRate = 0xFFFF; + if (wmi_get_bitrate_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + wait_event_interruptible_timeout(arEvent, ar->arBitRate != 0xFFFF, wmitimeout * HZ); + if (signal_pending(current)) { + ret = -EINTR; + } + } + /* If the interface is down or wmi is not ready or the target is not + connected - return the value stored in the device structure */ + if (!ret) { + if (ar->arBitRate == -1) { + rrq->fixed = TRUE; + rrq->value = 0; + } else { + rrq->value = ar->arBitRate * 1000; + } + } + + up(&ar->arSem); + + return ret; +} + +/* + * SIOCSIWTXPOW + */ +static int +ar6000_ioctl_siwtxpow(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_UINT8 dbM; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (rrq->disabled) { + return -EOPNOTSUPP; + } + + if (rrq->fixed) { + if (rrq->flags != IW_TXPOW_DBM) { + return -EOPNOTSUPP; + } + ar->arTxPwr= dbM = rrq->value; + ar->arTxPwrSet = TRUE; + } else { + ar->arTxPwr = dbM = 0; + ar->arTxPwrSet = FALSE; + } + if(ar->arWmiReady == TRUE) + { + AR_DEBUG_PRINTF("Set tx pwr cmd %d dbM\n", dbM); + wmi_set_txPwr_cmd(ar->arWmi, dbM); + } + return 0; +} + +/* + * SIOCGIWTXPOW + */ +int +ar6000_ioctl_giwtxpow(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + int ret = 0; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + if((ar->arWmiReady == TRUE) && (ar->arConnected == TRUE)) + { + ar->arTxPwr = 0; + + if (wmi_get_txPwr_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->arTxPwr != 0, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + } + /* If the interace is down or wmi is not ready or target is not connected + then return value stored in the device structure */ + + if (!ret) { + if (ar->arTxPwrSet == TRUE) { + rrq->fixed = TRUE; + } + rrq->value = ar->arTxPwr; + rrq->flags = IW_TXPOW_DBM; + // + // IWLIST need this flag to get TxPower + // + rrq->disabled = 0; + } + + up(&ar->arSem); + + return ret; +} + +/* + * SIOCSIWRETRY + * since iwconfig only provides us with one max retry value, we use it + * to apply to data frames of the BE traffic class. + */ +static int +ar6000_ioctl_siwretry(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (rrq->disabled) { + return -EOPNOTSUPP; + } + + if ((rrq->flags & IW_RETRY_TYPE) != IW_RETRY_LIMIT) { + return -EOPNOTSUPP; + } + + if ( !(rrq->value >= WMI_MIN_RETRIES) || !(rrq->value <= WMI_MAX_RETRIES)) { + return - EINVAL; + } + if(ar->arWmiReady == TRUE) + { + if (wmi_set_retry_limits_cmd(ar->arWmi, DATA_FRAMETYPE, WMM_AC_BE, + rrq->value, 0) != A_OK){ + return -EINVAL; + } + } + ar->arMaxRetries = rrq->value; + return 0; +} + +/* + * SIOCGIWRETRY + */ +static int +ar6000_ioctl_giwretry(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + rrq->disabled = 0; + switch (rrq->flags & IW_RETRY_TYPE) { + case IW_RETRY_LIFETIME: + return -EOPNOTSUPP; + break; + case IW_RETRY_LIMIT: + rrq->flags = IW_RETRY_LIMIT; + switch (rrq->flags & IW_RETRY_MODIFIER) { + case IW_RETRY_MIN: + rrq->flags |= IW_RETRY_MIN; + rrq->value = WMI_MIN_RETRIES; + break; + case IW_RETRY_MAX: + rrq->flags |= IW_RETRY_MAX; + rrq->value = ar->arMaxRetries; + break; + } + break; + } + return 0; +} + +/* + * SIOCSIWENCODE + */ +static int +ar6000_ioctl_siwencode(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, char *keybuf) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + int index; + A_INT32 auth = 0; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if(ar->arNextMode != AP_NETWORK) { + /* + * Static WEP Keys should be configured before setting the SSID + */ + if (ar->arSsid[0] && erq->length) { + return -EIO; + } + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + index = erq->flags & IW_ENCODE_INDEX; + + if (index && (((index - 1) < WMI_MIN_KEY_INDEX) || + ((index - 1) > WMI_MAX_KEY_INDEX))) + { + return -EIO; + } + + if (erq->flags & IW_ENCODE_DISABLED) { + /* + * Encryption disabled + */ + if (index) { + /* + * If key index was specified then clear the specified key + */ + index--; + A_MEMZERO(ar->arWepKeyList[index].arKey, + sizeof(ar->arWepKeyList[index].arKey)); + ar->arWepKeyList[index].arKeyLen = 0; + } + ar->arDot11AuthMode = OPEN_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arGroupCrypto = NONE_CRYPT; + ar->arAuthMode = NONE_AUTH; + } else { + /* + * Enabling WEP encryption + */ + if (index) { + index--; /* keyindex is off base 1 in iwconfig */ + } + + if (erq->flags & IW_ENCODE_OPEN) { + auth |= OPEN_AUTH; + ar->arDefTxKeyIndex = index; + } + if (erq->flags & IW_ENCODE_RESTRICTED) { + auth |= SHARED_AUTH; + } + + if(!auth) { + auth = ar->arDot11AuthMode; + } + + if (erq->length) { + if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(erq->length)) { + return -EIO; + } + + A_MEMZERO(ar->arWepKeyList[index].arKey, + sizeof(ar->arWepKeyList[index].arKey)); + A_MEMCPY(ar->arWepKeyList[index].arKey, keybuf, erq->length); + ar->arWepKeyList[index].arKeyLen = erq->length; + } else { + if (ar->arWepKeyList[index].arKeyLen == 0) { + return -EIO; + } + ar->arDefTxKeyIndex = index; + + if(ar->arSsidLen && ar->arWepKeyList[index].arKeyLen) { + wmi_addKey_cmd(ar->arWmi, + index, + WEP_CRYPT, + GROUP_USAGE | TX_USAGE, + ar->arWepKeyList[index].arKeyLen, + NULL, + ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL, NULL, + NO_SYNC_WMIFLAG); + } + } + + ar->arPairwiseCrypto = WEP_CRYPT; + ar->arGroupCrypto = WEP_CRYPT; + ar->arDot11AuthMode = auth; + ar->arAuthMode = NONE_AUTH; + } + + if(ar->arNextMode != AP_NETWORK) { + /* + * profile has changed. Erase ssid to signal change + */ + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + } + ar->ap_profile_flag = 1; /* There is a change in profile */ + return 0; +} + +static int +ar6000_ioctl_giwencode(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, char *key) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_UINT8 keyIndex; + struct ar_wep_key *wk; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arPairwiseCrypto == NONE_CRYPT) { + erq->length = 0; + erq->flags = IW_ENCODE_DISABLED; + } else { + /* get the keyIndex */ + keyIndex = erq->flags & IW_ENCODE_INDEX; + if (0 == keyIndex) { + keyIndex = ar->arDefTxKeyIndex; + } else if ((keyIndex - 1 < WMI_MIN_KEY_INDEX) || + (keyIndex - 1 > WMI_MAX_KEY_INDEX)) + { + keyIndex = WMI_MIN_KEY_INDEX; + } else { + keyIndex--; + } + erq->flags = keyIndex + 1; + erq->flags |= IW_ENCODE_ENABLED; + wk = &ar->arWepKeyList[keyIndex]; + if (erq->length > wk->arKeyLen) { + erq->length = wk->arKeyLen; + } + if (wk->arKeyLen) { + A_MEMCPY(key, wk->arKey, erq->length); + } + if (ar->arDot11AuthMode & OPEN_AUTH) { + erq->flags |= IW_ENCODE_OPEN; + } + if (ar->arDot11AuthMode & SHARED_AUTH) { + erq->flags |= IW_ENCODE_RESTRICTED; + } + } + + return 0; +} + +static int ar6000_ioctl_siwpower(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ +#if defined(WIRELESS_EXT) && WIRELESS_EXT > 20 + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_POWER_MODE power_mode; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (wrqu->power.disabled) + power_mode = MAX_PERF_POWER; + else + power_mode = REC_POWER; + + if (wmi_powermode_cmd(ar->arWmi, power_mode) < 0) + return -EIO; +#endif + return 0; +} + +static int ar6000_ioctl_giwpower(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ +#if defined(WIRELESS_EXT) && WIRELESS_EXT > 20 + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + if(!ar->arWmi){ + return -EIO; + } + return wmi_get_power_mode_cmd(ar->arWmi); +#else + return 0; +#endif +} + +static int ar6000_ioctl_siwgenie(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *dwrq, + char *extra) +{ + /* The target does that for us */ + return 0; +} + +static int ar6000_ioctl_giwgenie(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *dwrq, + char *extra) +{ + return 0; +} + +static int ar6000_ioctl_siwauth(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *param, + char *extra) +{ +#if defined(WIRELESS_EXT) && WIRELESS_EXT > 20 + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + int reset = 0; + + switch (param->flags & IW_AUTH_INDEX) { + case IW_AUTH_WPA_VERSION: + if (param->value & IW_AUTH_WPA_VERSION_DISABLED) { + ar->arAuthMode = NONE_AUTH; + } + if (param->value & IW_AUTH_WPA_VERSION_WPA) { + ar->arAuthMode = WPA_AUTH; + } + if (param->value & IW_AUTH_WPA_VERSION_WPA2) { + ar->arAuthMode = WPA2_AUTH; + } + + reset = 1; + break; + case IW_AUTH_CIPHER_PAIRWISE: + if (param->value & IW_AUTH_CIPHER_NONE) { + ar->arPairwiseCrypto = NONE_CRYPT; + } + if (param->value & IW_AUTH_CIPHER_WEP40) { + ar->arPairwiseCrypto = WEP_CRYPT; + } + if (param->value & IW_AUTH_CIPHER_TKIP) { + ar->arPairwiseCrypto = TKIP_CRYPT; + } + if (param->value & IW_AUTH_CIPHER_CCMP) { + ar->arPairwiseCrypto = AES_CRYPT; + } + + reset = 1; + break; + case IW_AUTH_CIPHER_GROUP: + if (param->value & IW_AUTH_CIPHER_NONE) { + ar->arGroupCrypto = NONE_CRYPT; + } + if ((param->value & IW_AUTH_CIPHER_WEP40) || + (param->value & IW_AUTH_CIPHER_WEP104)) { + ar->arGroupCrypto = WEP_CRYPT; + } + if (param->value & IW_AUTH_CIPHER_TKIP) { + ar->arGroupCrypto = TKIP_CRYPT; + } + if (param->value & IW_AUTH_CIPHER_CCMP) { + ar->arGroupCrypto = AES_CRYPT; + } + + reset = 1; + break; + case IW_AUTH_KEY_MGMT: + if (param->value & IW_AUTH_KEY_MGMT_PSK) { + if (ar->arAuthMode == WPA_AUTH) { + ar->arAuthMode = WPA_PSK_AUTH; + } else if (ar->arAuthMode == WPA2_AUTH) { + ar->arAuthMode = WPA2_PSK_AUTH; + } + + reset = 1; + } + break; + + case IW_AUTH_TKIP_COUNTERMEASURES: + if (ar->arWmiReady == FALSE) { + return -EIO; + } + wmi_set_tkip_countermeasures_cmd(ar->arWmi, param->value); + break; + + case IW_AUTH_DROP_UNENCRYPTED: + break; + + case IW_AUTH_80211_AUTH_ALG: + ar->arDot11AuthMode = 0; + if (param->value & IW_AUTH_ALG_OPEN_SYSTEM) { + ar->arDot11AuthMode |= OPEN_AUTH; + } + if (param->value & IW_AUTH_ALG_SHARED_KEY) { + ar->arDot11AuthMode |= SHARED_AUTH; + } + if (param->value & IW_AUTH_ALG_LEAP) { + ar->arDot11AuthMode = LEAP_AUTH; + ar->arPairwiseCrypto = WEP_CRYPT; + ar->arGroupCrypto = WEP_CRYPT; + } + reset = 1; + break; + + case IW_AUTH_WPA_ENABLED: + reset = 1; + break; + + case IW_AUTH_RX_UNENCRYPTED_EAPOL: + break; + + case IW_AUTH_PRIVACY_INVOKED: + break; + + default: + printk("%s(): Unknown flag 0x%x\n", __FUNCTION__, param->flags); + return -EOPNOTSUPP; + } + + if (reset) + memset(ar->arSsid, 0, sizeof(ar->arSsid)); +#endif + return 0; +} + +static int ar6000_ioctl_giwauth(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *dwrq, + char *extra) +{ + return 0; +} + +static int ar6000_ioctl_siwencodeext(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, + char *extra) +{ +#if defined(WIRELESS_EXT) && WIRELESS_EXT > 20 + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + struct iw_point *encoding = &wrqu->encoding; + struct iw_encode_ext *ext = (struct iw_encode_ext *)extra; + int alg = ext->alg, idx; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + /* Determine and validate the key index */ + idx = (encoding->flags & IW_ENCODE_INDEX) - 1; + if (idx) { + if (idx < 0 || idx > 3) + return -EINVAL; + } + + if ((alg == IW_ENCODE_ALG_TKIP) || (alg == IW_ENCODE_ALG_CCMP)) { + struct ieee80211req_key ik; + KEY_USAGE key_usage; + CRYPTO_TYPE key_type = NONE_CRYPT; + int status; + +#ifdef USER_KEYS + ar->user_saved_keys.keyOk = FALSE; +#endif + + if (alg == IW_ENCODE_ALG_TKIP) { + key_type = TKIP_CRYPT; + ik.ik_type = IEEE80211_CIPHER_TKIP; + } else { + key_type = AES_CRYPT; + ik.ik_type = IEEE80211_CIPHER_AES_CCM; + } + + ik.ik_keyix = idx; + ik.ik_keylen = ext->key_len; + ik.ik_flags = IEEE80211_KEY_RECV; + if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) { + ik.ik_flags |= IEEE80211_KEY_XMIT + | IEEE80211_KEY_DEFAULT; + } + + if (ext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) { + memcpy(&ik.ik_keyrsc, ext->rx_seq, 8); + } + + memcpy(ik.ik_keydata, ext->key, ext->key_len); + +#ifdef USER_KEYS + ar->user_saved_keys.keyType = key_type; +#endif + if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) { + key_usage = GROUP_USAGE; + memset(ik.ik_macaddr, 0, ETH_ALEN); +#ifdef USER_KEYS + memcpy(&ar->user_saved_keys.bcast_ik, &ik, + sizeof(struct ieee80211req_key)); +#endif + } else { + key_usage = PAIRWISE_USAGE; + memcpy(ik.ik_macaddr, ext->addr.sa_data, ETH_ALEN); +#ifdef USER_KEYS + memcpy(&ar->user_saved_keys.ucast_ik, &ik, + sizeof(struct ieee80211req_key)); +#endif + } + + if (((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)) && + (GROUP_USAGE == key_usage)) + { + A_UNTIMEOUT(&ar->disconnect_timer); + } + + status = wmi_addKey_cmd(ar->arWmi, ik.ik_keyix, key_type, + key_usage, ik.ik_keylen, + (A_UINT8 *)&ik.ik_keyrsc, + ik.ik_keydata, + KEY_OP_INIT_VAL, ik.ik_macaddr, + SYNC_BEFORE_WMIFLAG); + + if (status < 0) + return -EIO; + +#ifdef USER_KEYS + ar->user_saved_keys.keyOk = TRUE; +#endif + + return 0; + + } else { + /* WEP falls back to SIWENCODE */ + return -EOPNOTSUPP; + } +#endif + return 0; +} + + +static int ar6000_ioctl_giwencodeext(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *dwrq, + char *extra) +{ + return 0; +} + + +/* + * SIOCGIWNAME + */ +int +ar6000_ioctl_giwname(struct net_device *dev, + struct iw_request_info *info, + char *name, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + switch (ar->arPhyCapability) { + case (WMI_11A_CAPABILITY): + strncpy(name, "AR6000 802.11a", IFNAMSIZ); + break; + case (WMI_11G_CAPABILITY): + strncpy(name, "AR6000 802.11g", IFNAMSIZ); + break; + case (WMI_11AG_CAPABILITY): + strncpy(name, "AR6000 802.11ag", IFNAMSIZ); + break; + default: + strncpy(name, "AR6000 802.11", IFNAMSIZ); + break; + } + + return 0; +} + +/* + * SIOCSIWFREQ + */ +int +ar6000_ioctl_siwfreq(struct net_device *dev, + struct iw_request_info *info, + struct iw_freq *freq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + /* + * We support limiting the channels via wmiconfig. + * + * We use this command to configure the channel hint for the connect cmd + * so it is possible the target will end up connecting to a different + * channel. + */ + if (freq->e > 1) { + return -EINVAL; + } else if (freq->e == 1) { + ar->arChannelHint = freq->m / 100000; + } else { + ar->arChannelHint = wlan_ieee2freq(freq->m); + } + + ar->ap_profile_flag = 1; /* There is a change in profile */ + + A_PRINTF("channel hint set to %d\n", ar->arChannelHint); + return 0; +} + +/* + * SIOCGIWFREQ + */ +int +ar6000_ioctl_giwfreq(struct net_device *dev, + struct iw_request_info *info, + struct iw_freq *freq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arConnected != TRUE) { + return -EINVAL; + } + if (ar->arNetworkType == AP_NETWORK) { + freq->m = ar->arChannelHint * 100000; + } else { + freq->m = ar->arBssChannel * 100000; + } + + freq->e = 1; + + return 0; +} + +/* + * SIOCSIWMODE + */ +int +ar6000_ioctl_siwmode(struct net_device *dev, + struct iw_request_info *info, + __u32 *mode, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + switch (*mode) { + case IW_MODE_INFRA: + ar->arNextMode = INFRA_NETWORK; + break; + case IW_MODE_ADHOC: + ar->arNextMode = ADHOC_NETWORK; + break; + case IW_MODE_MASTER: + ar->arNextMode = AP_NETWORK; + break; + default: + return -EINVAL; + } + + /* clear all shared parameters between AP and STA|IBSS modes when we + * switch between them. Switch between STA & IBSS modes does'nt clear + * the shared profile. This is as per the original design for switching + * between STA & IBSS. + */ + if (ar->arNetworkType == AP_NETWORK || ar->arNextMode == AP_NETWORK) { + ar->arDot11AuthMode = OPEN_AUTH; + ar->arAuthMode = NONE_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arPairwiseCryptoLen = 0; + ar->arGroupCrypto = NONE_CRYPT; + ar->arGroupCryptoLen = 0; + ar->arChannelHint = 0; + ar->arBssChannel = 0; + A_MEMZERO(ar->arBssid, sizeof(ar->arBssid)); + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = 0; + } + + /* SSID has to be cleared to trigger a profile change while switching + * between STA & IBSS modes having the same SSID + */ + if (ar->arNetworkType != ar->arNextMode) { + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + } + + return 0; +} + +/* + * SIOCGIWMODE + */ +int +ar6000_ioctl_giwmode(struct net_device *dev, + struct iw_request_info *info, + __u32 *mode, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + switch (ar->arNetworkType) { + case INFRA_NETWORK: + *mode = IW_MODE_INFRA; + break; + case ADHOC_NETWORK: + *mode = IW_MODE_ADHOC; + break; + case AP_NETWORK: + *mode = IW_MODE_MASTER; + break; + default: + return -EIO; + } + return 0; +} + +/* + * SIOCSIWSENS + */ +int +ar6000_ioctl_siwsens(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *sens, char *extra) +{ + return 0; +} + +/* + * SIOCGIWSENS + */ +int +ar6000_ioctl_giwsens(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *sens, char *extra) +{ + sens->value = 0; + sens->fixed = 1; + + return 0; +} + +/* + * SIOCGIWRANGE + */ +int +ar6000_ioctl_giwrange(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + struct iw_range *range = (struct iw_range *) extra; + int i, ret = 0; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + ar->arNumChannels = -1; + A_MEMZERO(ar->arChannelList, sizeof (ar->arChannelList)); + + if (wmi_get_channelList_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->arNumChannels != -1, wmitimeout * HZ); + + if (signal_pending(current)) { + up(&ar->arSem); + return -EINTR; + } + + data->length = sizeof(struct iw_range); + A_MEMZERO(range, sizeof(struct iw_range)); + + range->txpower_capa = 0; + + range->min_pmp = 1 * 1024; + range->max_pmp = 65535 * 1024; + range->min_pmt = 1 * 1024; + range->max_pmt = 1000 * 1024; + range->pmp_flags = IW_POWER_PERIOD; + range->pmt_flags = IW_POWER_TIMEOUT; + range->pm_capa = 0; + + range->we_version_compiled = WIRELESS_EXT; + range->we_version_source = 13; + + range->retry_capa = IW_RETRY_LIMIT; + range->retry_flags = IW_RETRY_LIMIT; + range->min_retry = 0; + range->max_retry = 255; + + range->num_frequency = range->num_channels = ar->arNumChannels; + for (i = 0; i < ar->arNumChannels; i++) { + range->freq[i].i = wlan_freq2ieee(ar->arChannelList[i]); + range->freq[i].m = ar->arChannelList[i] * 100000; + range->freq[i].e = 1; + /* + * Linux supports max of 32 channels, bail out once you + * reach the max. + */ + if (i == IW_MAX_FREQUENCIES) { + break; + } + } + + /* Max quality is max field value minus noise floor */ + range->max_qual.qual = 0xff - 161; + + /* + * In order to use dBm measurements, 'level' must be lower + * than any possible measurement (see iw_print_stats() in + * wireless tools). It's unclear how this is meant to be + * done, but setting zero in these values forces dBm and + * the actual numbers are not used. + */ + range->max_qual.level = 0; + range->max_qual.noise = 0; + + range->sensitivity = 3; + + range->max_encoding_tokens = 4; + /* XXX query driver to find out supported key sizes */ + range->num_encoding_sizes = 3; + range->encoding_size[0] = 5; /* 40-bit */ + range->encoding_size[1] = 13; /* 104-bit */ + range->encoding_size[2] = 16; /* 128-bit */ + + range->num_bitrates = 0; + + /* estimated maximum TCP throughput values (bps) */ + range->throughput = 22000000; + + range->min_rts = 0; + range->max_rts = 2347; + range->min_frag = 256; + range->max_frag = 2346; + + up(&ar->arSem); + + return ret; +} + + +/* + * SIOCSIWAP + * This ioctl is used to set the desired bssid for the connect command. + */ +int +ar6000_ioctl_siwap(struct net_device *dev, + struct iw_request_info *info, + struct sockaddr *ap_addr, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ap_addr->sa_family != ARPHRD_ETHER) { + return -EIO; + } + + if (A_MEMCMP(&ap_addr->sa_data, bcast_mac, AR6000_ETH_ADDR_LEN) == 0) { + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + } else { + A_MEMCPY(ar->arReqBssid, &ap_addr->sa_data, sizeof(ar->arReqBssid)); + } + + return 0; +} + +/* + * SIOCGIWAP + */ +int +ar6000_ioctl_giwap(struct net_device *dev, + struct iw_request_info *info, + struct sockaddr *ap_addr, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arConnected != TRUE) { + return -EINVAL; + } + + if (ar->arNetworkType == AP_NETWORK) { + return -EINVAL; + } + + A_MEMCPY(&ap_addr->sa_data, ar->arBssid, sizeof(ar->arBssid)); + ap_addr->sa_family = ARPHRD_ETHER; + + return 0; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,13) +/* + * SIOCSIWMLME + */ +int +ar6000_ioctl_siwmlme(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arNetworkType == AP_NETWORK) { + return -EINVAL; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + if (data->pointer && data->length == sizeof(struct iw_mlme)) { + + A_UINT8 arNetworkType; + struct iw_mlme mlme; + + if (copy_from_user(&mlme, data->pointer, sizeof(struct iw_mlme))) + return -EIO; + + switch (mlme.cmd) { + + case IW_MLME_DEAUTH: + /* ignore it */ + break; + + case IW_MLME_DISASSOC: + if ((ar->arConnected != TRUE) || + (memcmp(ar->arBssid, mlme.addr.sa_data, 6) != 0)) { + + up(&ar->arSem); + return -EINVAL; + } + wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0); + arNetworkType = ar->arNetworkType; + ar6000_init_profile_info(ar); + ar->arNetworkType = arNetworkType; + reconnect_flag = 0; + wmi_disconnect_cmd(ar->arWmi); + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = 0; + if (ar->arSkipScan == FALSE) { + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + } + break; + + case IW_MLME_AUTH: + /* fall through */ + case IW_MLME_ASSOC: + /* fall through */ + default: + up(&ar->arSem); + return -EOPNOTSUPP; + } + } + + up(&ar->arSem); + return 0; +} +#endif /* LINUX_VERSION_CODE */ + +/* + * SIOCGIWAPLIST + */ +int +ar6000_ioctl_iwaplist(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + return -EIO; /* for now */ +} + +/* + * SIOCSIWSCAN + */ +int +ar6000_ioctl_siwscan(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ +#define ACT_DWELLTIME_DEFAULT 105 +#define HOME_TXDRAIN_TIME 100 +#define SCAN_INT HOME_TXDRAIN_TIME + ACT_DWELLTIME_DEFAULT + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + int ret = 0; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + /* We ask for everything from the target */ + if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != A_OK) { + printk("Couldn't set filtering\n"); + ret = -EIO; + } + +#if WIRELESS_EXT >= 18 + if (data->pointer && (data->length == sizeof(struct iw_scan_req))) + { + if ((data->flags & IW_SCAN_THIS_ESSID) == IW_SCAN_THIS_ESSID) + { + struct iw_scan_req req; + if (copy_from_user(&req, data->pointer, sizeof(struct iw_scan_req))) + return -EIO; + if (wmi_probedSsid_cmd(ar->arWmi, 1, SPECIFIC_SSID_FLAG, req.essid_len, req.essid) != A_OK) + return -EIO; + } + else + { + if (wmi_probedSsid_cmd(ar->arWmi, 1, DISABLE_SSID_FLAG, 0, NULL) != A_OK) + return -EIO; + } + } + else + { + if (wmi_probedSsid_cmd(ar->arWmi, 1, DISABLE_SSID_FLAG, 0, NULL) != A_OK) + return -EIO; + } +#endif + + if (wmi_startscan_cmd(ar->arWmi, WMI_LONG_SCAN, FALSE, FALSE, \ + 0, 0, 0, NULL) != A_OK) { + ret = -EIO; + } + + return ret; +#undef ACT_DWELLTIME_DEFAULT +#undef HOME_TXDRAIN_TIME +#undef SCAN_INT +} + + +/* + * Units are in db above the noise floor. That means the + * rssi values reported in the tx/rx descriptors in the + * driver are the SNR expressed in db. + * + * If you assume that the noise floor is -95, which is an + * excellent assumption 99.5 % of the time, then you can + * derive the absolute signal level (i.e. -95 + rssi). + * There are some other slight factors to take into account + * depending on whether the rssi measurement is from 11b, + * 11g, or 11a. These differences are at most 2db and + * can be documented. + * + * NB: various calculations are based on the orinoco/wavelan + * drivers for compatibility + */ +static void +ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi) +{ + if (rssi < 0) { + iq->qual = 0; + } else { + iq->qual = rssi; + } + + /* NB: max is 94 because noise is hardcoded to 161 */ + if (iq->qual > 94) + iq->qual = 94; + + iq->noise = 161; /* -95dBm */ + iq->level = iq->noise + iq->qual; + iq->updated = 7; +} + + +int +ar6000_ioctl_siwcommit(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + AR_DEBUG_PRINTF("AP: SSID %s freq %d authmode %d dot11 auth %d"\ + " PW crypto %d GRP crypto %d\n", + ar->arSsid, ar->arChannelHint, + ar->arAuthMode, ar->arDot11AuthMode, + ar->arPairwiseCrypto, ar->arGroupCrypto); + + ar6000_ap_mode_profile_commit(ar); + + /* if there is a profile switch from STA|IBSS mode to AP mode, + * update the host driver association state for the STA|IBSS mode. + */ + if (ar->arNetworkType != AP_NETWORK && ar->arNextMode == AP_NETWORK) { + ar->arConnectPending = FALSE; + ar->arConnected = FALSE; + /* Stop getting pkts from upper stack */ + netif_stop_queue(ar->arNetDev); + A_MEMZERO(ar->arBssid, sizeof(ar->arBssid)); + ar->arBssChannel = 0; + ar->arBeaconInterval = 0; + + /* Flush the Tx queues */ + ar6000_TxDataCleanup(ar); + + /* Start getting pkts from upper stack */ + netif_wake_queue(ar->arNetDev); + } + + return 0; +} + +/* Structures to export the Wireless Handlers */ +static const iw_handler ath_handlers[] = { + (iw_handler) ar6000_ioctl_siwcommit, /* SIOCSIWCOMMIT */ + (iw_handler) ar6000_ioctl_giwname, /* SIOCGIWNAME */ + (iw_handler) NULL, /* SIOCSIWNWID */ + (iw_handler) NULL, /* SIOCGIWNWID */ + (iw_handler) ar6000_ioctl_siwfreq, /* SIOCSIWFREQ */ + (iw_handler) ar6000_ioctl_giwfreq, /* SIOCGIWFREQ */ + (iw_handler) ar6000_ioctl_siwmode, /* SIOCSIWMODE */ + (iw_handler) ar6000_ioctl_giwmode, /* SIOCGIWMODE */ + (iw_handler) ar6000_ioctl_siwsens, /* SIOCSIWSENS */ + (iw_handler) ar6000_ioctl_giwsens, /* SIOCGIWSENS */ + (iw_handler) NULL /* not _used */, /* SIOCSIWRANGE */ + (iw_handler) ar6000_ioctl_giwrange, /* SIOCGIWRANGE */ + (iw_handler) NULL /* not used */, /* SIOCSIWPRIV */ + (iw_handler) NULL /* kernel code */, /* SIOCGIWPRIV */ + (iw_handler) NULL /* not used */, /* SIOCSIWSTATS */ + (iw_handler) NULL /* kernel code */, /* SIOCGIWSTATS */ + (iw_handler) NULL, /* SIOCSIWSPY */ + (iw_handler) NULL, /* SIOCGIWSPY */ + (iw_handler) NULL, /* SIOCSIWTHRSPY */ + (iw_handler) NULL, /* SIOCGIWTHRSPY */ + (iw_handler) ar6000_ioctl_siwap, /* SIOCSIWAP */ + (iw_handler) ar6000_ioctl_giwap, /* SIOCGIWAP */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,13) + (iw_handler) ar6000_ioctl_siwmlme, /* SIOCSIWMLME */ +#else + (iw_handler) NULL, /* -- hole -- */ +#endif /* LINUX_VERSION_CODE */ + (iw_handler) ar6000_ioctl_iwaplist, /* SIOCGIWAPLIST */ + (iw_handler) ar6000_ioctl_siwscan, /* SIOCSIWSCAN */ + (iw_handler) ar6000_ioctl_giwscan, /* SIOCGIWSCAN */ + (iw_handler) ar6000_ioctl_siwessid, /* SIOCSIWESSID */ + (iw_handler) ar6000_ioctl_giwessid, /* SIOCGIWESSID */ + (iw_handler) NULL, /* SIOCSIWNICKN */ + (iw_handler) NULL, /* SIOCGIWNICKN */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) ar6000_ioctl_siwrate, /* SIOCSIWRATE */ + (iw_handler) ar6000_ioctl_giwrate, /* SIOCGIWRATE */ + (iw_handler) NULL, /* SIOCSIWRTS */ + (iw_handler) NULL, /* SIOCGIWRTS */ + (iw_handler) NULL, /* SIOCSIWFRAG */ + (iw_handler) NULL, /* SIOCGIWFRAG */ + (iw_handler) ar6000_ioctl_siwtxpow, /* SIOCSIWTXPOW */ + (iw_handler) ar6000_ioctl_giwtxpow, /* SIOCGIWTXPOW */ + (iw_handler) ar6000_ioctl_siwretry, /* SIOCSIWRETRY */ + (iw_handler) ar6000_ioctl_giwretry, /* SIOCGIWRETRY */ + (iw_handler) ar6000_ioctl_siwencode, /* SIOCSIWENCODE */ + (iw_handler) ar6000_ioctl_giwencode, /* SIOCGIWENCODE */ + (iw_handler) ar6000_ioctl_siwpower, /* SIOCSIWPOWER */ + (iw_handler) ar6000_ioctl_giwpower, /* SIOCGIWPOWER */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) ar6000_ioctl_siwgenie, /* SIOCSIWGENIE */ + (iw_handler) ar6000_ioctl_giwgenie, /* SIOCGIWGENIE */ + (iw_handler) ar6000_ioctl_siwauth, /* SIOCSIWAUTH */ + (iw_handler) ar6000_ioctl_giwauth, /* SIOCGIWAUTH */ + (iw_handler) ar6000_ioctl_siwencodeext,/* SIOCSIWENCODEEXT */ + (iw_handler) ar6000_ioctl_giwencodeext,/* SIOCGIWENCODEEXT */ + (iw_handler) NULL, /* SIOCSIWPMKSA */ +}; + +struct iw_handler_def ath_iw_handler_def = { + .standard = (iw_handler *)ath_handlers, + .num_standard = ARRAY_SIZE(ath_handlers), + .private = NULL, + .num_private = 0, +}; diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/wlan_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wlan_api.h --- linux-2.6.26/drivers/net/wireless/ath6k22/wlan_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wlan_api.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,119 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the API for the host wlan module +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HOST_WLAN_API_H_ +#define _HOST_WLAN_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +struct ieee80211_node_table; +struct ieee80211_frame; + +struct ieee80211_common_ie { + A_UINT16 ie_chan; + A_UINT8 *ie_tstamp; + A_UINT8 *ie_ssid; + A_UINT8 *ie_rates; + A_UINT8 *ie_xrates; + A_UINT8 *ie_country; + A_UINT8 *ie_wpa; + A_UINT8 *ie_rsn; + A_UINT8 *ie_wmm; + A_UINT8 *ie_ath; + A_UINT16 ie_capInfo; + A_UINT16 ie_beaconInt; + A_UINT8 *ie_tim; + A_UINT8 *ie_chswitch; + A_UINT8 ie_erp; + A_UINT8 *ie_wsc; +#ifdef PYXIS_ADHOC + A_UINT8 *ie_pyxis; +#endif +#ifdef WAPI_ENABLE + A_UINT8 *ie_wapi; +#endif +}; + +typedef struct bss { + A_UINT8 ni_macaddr[6]; + A_UINT8 ni_snr; + A_INT16 ni_rssi; + struct bss *ni_list_next; + struct bss *ni_list_prev; + struct bss *ni_hash_next; + struct bss *ni_hash_prev; + struct ieee80211_common_ie ni_cie; + A_UINT8 *ni_buf; + struct ieee80211_node_table *ni_table; + A_UINT32 ni_refcnt; + int ni_scangen; + + A_UINT32 ni_tstamp; +#ifdef OS_ROAM_MANAGEMENT + A_UINT32 ni_si_gen; +#endif +} bss_t; + +typedef void wlan_node_iter_func(void *arg, bss_t *); + +bss_t *wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size); +void wlan_node_free(bss_t *ni); +void wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni, + const A_UINT8 *macaddr); +bss_t *wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr); +void wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni); +void wlan_free_allnodes(struct ieee80211_node_table *nt); +void wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f, + void *arg); + +void wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt); +void wlan_node_table_reset(struct ieee80211_node_table *nt); +void wlan_node_table_cleanup(struct ieee80211_node_table *nt); + +A_STATUS wlan_parse_beacon(A_UINT8 *buf, int framelen, + struct ieee80211_common_ie *cie); + +A_UINT16 wlan_ieee2freq(int chan); +A_UINT32 wlan_freq2ieee(A_UINT16 freq); + +void wlan_set_nodeage(struct ieee80211_node_table *nt, A_UINT32 nodeAge); + + +bss_t * +wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID); + +void +wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni); + +bss_t *wlan_node_remove(struct ieee80211_node_table *nt, A_UINT8 *bssid); + +#ifdef __cplusplus +} +#endif + +#endif /* _HOST_WLAN_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/wlan_defs.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wlan_defs.h --- linux-2.6.26/drivers/net/wireless/ath6k22/wlan_defs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wlan_defs.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,55 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef __WLAN_DEFS_H__ +#define __WLAN_DEFS_H__ + +/* + * This file contains WLAN definitions that may be used across both + * Host and Target software. + */ + +typedef enum { + MODE_11A = 0, /* 11a Mode */ + MODE_11G = 1, /* 11b/g Mode */ + MODE_11B = 2, /* 11b Mode */ + MODE_11GONLY = 3, /* 11g only Mode */ +#ifdef SUPPORT_11N + MODE_11A_HT20 = 4, /* 11a HT20 mode */ + MODE_11G_HT20 = 5, /* 11g HT20 mode */ + MODE_11A_HT40 = 6, /* 11a HT40 mode */ + MODE_11G_HT40 = 7, /* 11g HT40 mode */ + MODE_UNKNOWN = 8, + MODE_MAX = 8 +#else + MODE_UNKNOWN = 4, + MODE_MAX = 4 +#endif +} WLAN_PHY_MODE; + +typedef enum { + WLAN_11A_CAPABILITY = 1, + WLAN_11G_CAPABILITY = 2, + WLAN_11AG_CAPABILITY = 3, +}WLAN_CAPABILITY; + +#endif /* __ATHDEFS_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/wlan_dset.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wlan_dset.h --- linux-2.6.26/drivers/net/wireless/ath6k22/wlan_dset.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wlan_dset.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,34 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __WLAN_DSET_H__ +#define __WKAN_DSET_H__ + +typedef PREPACK struct wow_config_dset { + + A_UINT8 valid_dset; + A_UINT8 gpio_enable; + A_UINT16 gpio_pin; +} POSTPACK WOW_CONFIG_DSET; + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/wlan_node.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wlan_node.c --- linux-2.6.26/drivers/net/wireless/ath6k22/wlan_node.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wlan_node.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,470 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// IEEE 802.11 node handling support. +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "a_debug.h" +#include "htc.h" +#include "htc_api.h" +#include "wmi.h" +#include "ieee80211.h" +#include "wlan_api.h" +#include "wmi_api.h" +#include "ieee80211_node.h" + +static void wlan_node_timeout(A_ATH_TIMER arg); + +static bss_t * _ieee80211_find_node (struct ieee80211_node_table *nt, + const A_UINT8 *macaddr); + +bss_t * +wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size) +{ + bss_t *ni; + + ni = A_MALLOC_NOWAIT(sizeof(bss_t)); + + if (ni != NULL) { + if (wh_size) + { + ni->ni_buf = A_MALLOC_NOWAIT(wh_size); + if (ni->ni_buf == NULL) { + A_FREE(ni); + ni = NULL; + return ni; + } + } + } else { + return ni; + } + + /* Make sure our lists are clean */ + ni->ni_list_next = NULL; + ni->ni_list_prev = NULL; + ni->ni_hash_next = NULL; + ni->ni_hash_prev = NULL; + + // + // ni_scangen never initialized before and during suspend/resume of winmobile, + // that some junk has been stored in this, due to this scan list didn't properly updated + // + ni->ni_scangen = 0; + +#ifdef OS_ROAM_MANAGEMENT + ni->ni_si_gen = 0; +#endif + + return ni; +} + +void +wlan_node_free(bss_t *ni) +{ + if (ni->ni_buf != NULL) { + A_FREE(ni->ni_buf); + } + A_FREE(ni); +} + +void +wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni, + const A_UINT8 *macaddr) +{ + int hash; + A_UINT32 timeoutValue = 0; + + A_MEMCPY(ni->ni_macaddr, macaddr, IEEE80211_ADDR_LEN); + hash = IEEE80211_NODE_HASH (macaddr); + ieee80211_node_initref (ni); /* mark referenced */ + + timeoutValue = nt->nt_nodeAge; + + ni->ni_tstamp = A_GET_MS (timeoutValue); + + IEEE80211_NODE_LOCK_BH(nt); + + /* Insert at the end of the node list */ + ni->ni_list_next = NULL; + ni->ni_list_prev = nt->nt_node_last; + if(nt->nt_node_last != NULL) + { + nt->nt_node_last->ni_list_next = ni; + } + nt->nt_node_last = ni; + if(nt->nt_node_first == NULL) + { + nt->nt_node_first = ni; + } + + /* Insert into the hash list i.e. the bucket */ + if((ni->ni_hash_next = nt->nt_hash[hash]) != NULL) + { + nt->nt_hash[hash]->ni_hash_prev = ni; + } + ni->ni_hash_prev = NULL; + nt->nt_hash[hash] = ni; + + if (!nt->isTimerArmed) { + A_TIMEOUT_MS(&nt->nt_inact_timer, timeoutValue, 0); + nt->isTimerArmed = TRUE; + } + + IEEE80211_NODE_UNLOCK_BH(nt); +} + +static bss_t * +_ieee80211_find_node(struct ieee80211_node_table *nt, + const A_UINT8 *macaddr) +{ + bss_t *ni; + int hash; + + IEEE80211_NODE_LOCK_ASSERT(nt); + + hash = IEEE80211_NODE_HASH(macaddr); + for(ni = nt->nt_hash[hash]; ni; ni = ni->ni_hash_next) { + if (IEEE80211_ADDR_EQ(ni->ni_macaddr, macaddr)) { + ieee80211_node_incref(ni); /* mark referenced */ + return ni; + } + } + return NULL; +} + +bss_t * +wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr) +{ + bss_t *ni; + + IEEE80211_NODE_LOCK(nt); + ni = _ieee80211_find_node(nt, macaddr); + IEEE80211_NODE_UNLOCK(nt); + return ni; +} + +/* + * Reclaim a node. If this is the last reference count then + * do the normal free work. Otherwise remove it from the node + * table and mark it gone by clearing the back-reference. + */ +void +wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni) +{ + IEEE80211_NODE_LOCK(nt); + + if(ni->ni_list_prev == NULL) + { + /* First in list so fix the list head */ + nt->nt_node_first = ni->ni_list_next; + } + else + { + ni->ni_list_prev->ni_list_next = ni->ni_list_next; + } + + if(ni->ni_list_next == NULL) + { + /* Last in list so fix list tail */ + nt->nt_node_last = ni->ni_list_prev; + } + else + { + ni->ni_list_next->ni_list_prev = ni->ni_list_prev; + } + + if(ni->ni_hash_prev == NULL) + { + /* First in list so fix the list head */ + int hash; + hash = IEEE80211_NODE_HASH(ni->ni_macaddr); + nt->nt_hash[hash] = ni->ni_hash_next; + } + else + { + ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next; + } + + if(ni->ni_hash_next != NULL) + { + ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev; + } + wlan_node_free(ni); + + IEEE80211_NODE_UNLOCK(nt); +} + +static void +wlan_node_dec_free(bss_t *ni) +{ + if (ieee80211_node_dectestref(ni)) { + wlan_node_free(ni); + } +} + +void +wlan_free_allnodes(struct ieee80211_node_table *nt) +{ + bss_t *ni; + + while ((ni = nt->nt_node_first) != NULL) { + wlan_node_reclaim(nt, ni); + } +} + +void +wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f, + void *arg) +{ + bss_t *ni; + A_UINT32 gen; + + gen = ++nt->nt_scangen; + + IEEE80211_NODE_LOCK(nt); + for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) { + if (ni->ni_scangen != gen) { + ni->ni_scangen = gen; + (void) ieee80211_node_incref(ni); + (*f)(arg, ni); + wlan_node_dec_free(ni); + } + } + IEEE80211_NODE_UNLOCK(nt); +} + +/* + * Node table support. + */ +void +wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt) +{ + int i; + + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN, ("node table = 0x%x\n", (A_UINT32)nt)); + IEEE80211_NODE_LOCK_INIT(nt); + + nt->nt_node_first = nt->nt_node_last = NULL; + for(i = 0; i < IEEE80211_NODE_HASHSIZE; i++) + { + nt->nt_hash[i] = NULL; + } + + A_INIT_TIMER(&nt->nt_inact_timer, wlan_node_timeout, nt); + nt->isTimerArmed = FALSE; + nt->nt_wmip = wmip; + nt->nt_nodeAge = WLAN_NODE_INACT_TIMEOUT_MSEC; + + // + // nt_scangen never initialized before and during suspend/resume of winmobile, + // that some junk has been stored in this, due to this scan list didn't properly updated + // + nt->nt_scangen = 0; + +#ifdef OS_ROAM_MANAGEMENT + nt->nt_si_gen = 0; +#endif +} + +void +wlan_set_nodeage(struct ieee80211_node_table *nt, A_UINT32 nodeAge) +{ + nt->nt_nodeAge = nodeAge; + return; +} +static void +wlan_node_timeout (A_ATH_TIMER arg) +{ + struct ieee80211_node_table *nt = (struct ieee80211_node_table *)arg; + bss_t *bss, *nextBss; + A_UINT8 myBssid[IEEE80211_ADDR_LEN], reArmTimer = FALSE; + A_UINT32 timeoutValue = 0; + + timeoutValue = nt->nt_nodeAge; + + wmi_get_current_bssid(nt->nt_wmip, myBssid); + + bss = nt->nt_node_first; + while (bss != NULL) + { + nextBss = bss->ni_list_next; + if (A_MEMCMP(myBssid, bss->ni_macaddr, sizeof(myBssid)) != 0) + { + + if (bss->ni_tstamp <= A_GET_MS(0)) + { + /* + * free up all but the current bss - if set + */ + wlan_node_reclaim(nt, bss); + } + else + { + /* + * Re-arm timer, only when we have a bss other than + * current bss AND it is not aged-out. + */ + reArmTimer = TRUE; + } + } + bss = nextBss; + } + + if (reArmTimer) + A_TIMEOUT_MS (&nt->nt_inact_timer, timeoutValue, 0); + + nt->isTimerArmed = reArmTimer; +} + +void +wlan_node_table_cleanup(struct ieee80211_node_table *nt) +{ + A_UNTIMEOUT(&nt->nt_inact_timer); + A_DELETE_TIMER(&nt->nt_inact_timer); + wlan_free_allnodes(nt); + IEEE80211_NODE_LOCK_DESTROY(nt); +} + +bss_t * +wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID) +{ + bss_t *ni = NULL; + A_UCHAR *pIESsid = NULL; + + IEEE80211_NODE_LOCK (nt); + + for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) { + pIESsid = ni->ni_cie.ie_ssid; + if (pIESsid[1] <= 32) { + + // Step 1 : Check SSID + if (0x00 == memcmp (pSsid, &pIESsid[2], ssidLength)) { + + // + // Step 2.1 : Check MatchSSID is TRUE, if so, return Matched SSID + // Profile, otherwise check whether WPA2 or WPA + // + if (TRUE == bMatchSSID) { + ieee80211_node_incref (ni); /* mark referenced */ + IEEE80211_NODE_UNLOCK (nt); + return ni; + } + + // Step 2 : if SSID matches, check WPA or WPA2 + if (TRUE == bIsWPA2 && NULL != ni->ni_cie.ie_rsn) { + ieee80211_node_incref (ni); /* mark referenced */ + IEEE80211_NODE_UNLOCK (nt); + return ni; + } + if (FALSE == bIsWPA2 && NULL != ni->ni_cie.ie_wpa) { + ieee80211_node_incref(ni); /* mark referenced */ + IEEE80211_NODE_UNLOCK (nt); + return ni; + } + } + } + } + + IEEE80211_NODE_UNLOCK (nt); + + return NULL; +} + +void +wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni) +{ + IEEE80211_NODE_LOCK (nt); + wlan_node_dec_free (ni); + IEEE80211_NODE_UNLOCK (nt); +} + +void +wlan_node_remove_core (struct ieee80211_node_table *nt, bss_t *ni) +{ + if(ni->ni_list_prev == NULL) + { + /* First in list so fix the list head */ + nt->nt_node_first = ni->ni_list_next; + } + else + { + ni->ni_list_prev->ni_list_next = ni->ni_list_next; + } + + if(ni->ni_list_next == NULL) + { + /* Last in list so fix list tail */ + nt->nt_node_last = ni->ni_list_prev; + } + else + { + ni->ni_list_next->ni_list_prev = ni->ni_list_prev; + } + + if(ni->ni_hash_prev == NULL) + { + /* First in list so fix the list head */ + int hash; + hash = IEEE80211_NODE_HASH(ni->ni_macaddr); + nt->nt_hash[hash] = ni->ni_hash_next; + } + else + { + ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next; + } + + if(ni->ni_hash_next != NULL) + { + ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev; + } +} + +bss_t * +wlan_node_remove(struct ieee80211_node_table *nt, A_UINT8 *bssid) +{ + bss_t *bss, *nextBss; + + IEEE80211_NODE_LOCK(nt); + + bss = nt->nt_node_first; + + while (bss != NULL) + { + nextBss = bss->ni_list_next; + + if (A_MEMCMP(bssid, bss->ni_macaddr, 6) == 0) + { + wlan_node_remove_core (nt, bss); + IEEE80211_NODE_UNLOCK(nt); + return bss; + } + + bss = nextBss; + } + + IEEE80211_NODE_UNLOCK(nt); + return NULL; +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/wlan_recv_beacon.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wlan_recv_beacon.c --- linux-2.6.26/drivers/net/wireless/ath6k22/wlan_recv_beacon.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wlan_recv_beacon.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,207 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// IEEE 802.11 input handling. +// +// Author(s): ="Atheros" +//============================================================================== + +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "wmi.h" +#include "ieee80211.h" +#include "wlan_api.h" + +#define IEEE80211_VERIFY_LENGTH(_len, _minlen) do { \ + if ((_len) < (_minlen)) { \ + return A_EINVAL; \ + } \ +} while (0) + +#define IEEE80211_VERIFY_ELEMENT(__elem, __maxlen) do { \ + if ((__elem) == NULL) { \ + return A_EINVAL; \ + } \ + if ((__elem)[1] > (__maxlen)) { \ + return A_EINVAL; \ + } \ +} while (0) + + +/* unaligned little endian access */ +#define LE_READ_2(p) \ + ((A_UINT16) \ + ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8))) + +#define LE_READ_4(p) \ + ((A_UINT32) \ + ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8) | \ + (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24))) + + +static int __inline +iswpaoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((WPA_OUI_TYPE<<24)|WPA_OUI); +} + +static int __inline +iswmmoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((WMM_OUI_TYPE<<24)|WMM_OUI); +} + +/* unused functions for now */ +#if 0 +static int __inline +iswmmparam(const A_UINT8 *frm) +{ + return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE; +} + +static int __inline +iswmminfo(const A_UINT8 *frm) +{ + return frm[1] > 5 && frm[6] == WMM_INFO_OUI_SUBTYPE; +} +#endif + +static int __inline +isatherosoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((ATH_OUI_TYPE<<24)|ATH_OUI); +} + +static int __inline +iswscoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((0x04<<24)|WPA_OUI); +} + +#ifdef PYXIS_ADHOC +static int __inline +ispyxisoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((PYXIS_OUI_TYPE<<24)|PYXIS_OUI); +} +#endif + +A_STATUS +wlan_parse_beacon(A_UINT8 *buf, int framelen, struct ieee80211_common_ie *cie) +{ + A_UINT8 *frm, *efrm; + A_UINT8 elemid_ssid = FALSE; + + frm = buf; + efrm = (A_UINT8 *) (frm + framelen); + + /* + * beacon/probe response frame format + * [8] time stamp + * [2] beacon interval + * [2] capability information + * [tlv] ssid + * [tlv] supported rates + * [tlv] country information + * [tlv] parameter set (FH/DS) + * [tlv] erp information + * [tlv] extended supported rates + * [tlv] WMM + * [tlv] WPA or RSN + * [tlv] Atheros Advanced Capabilities + */ + IEEE80211_VERIFY_LENGTH(efrm - frm, 12); + A_MEMZERO(cie, sizeof(*cie)); + + cie->ie_tstamp = frm; frm += 8; + cie->ie_beaconInt = A_LE2CPU16(*(A_UINT16 *)frm); frm += 2; + cie->ie_capInfo = A_LE2CPU16(*(A_UINT16 *)frm); frm += 2; + cie->ie_chan = 0; + + while (frm < efrm) { + switch (*frm) { + case IEEE80211_ELEMID_SSID: + if (!elemid_ssid) { + cie->ie_ssid = frm; + elemid_ssid = TRUE; + } + break; + case IEEE80211_ELEMID_RATES: + cie->ie_rates = frm; + break; + case IEEE80211_ELEMID_COUNTRY: + cie->ie_country = frm; + break; + case IEEE80211_ELEMID_FHPARMS: + break; + case IEEE80211_ELEMID_DSPARMS: + cie->ie_chan = frm[2]; + break; + case IEEE80211_ELEMID_TIM: + cie->ie_tim = frm; + break; + case IEEE80211_ELEMID_IBSSPARMS: + break; + case IEEE80211_ELEMID_XRATES: + cie->ie_xrates = frm; + break; + case IEEE80211_ELEMID_ERP: + if (frm[1] != 1) { + //A_PRINTF("Discarding ERP Element - Bad Len\n"); + return A_EINVAL; + } + cie->ie_erp = frm[2]; + break; + case IEEE80211_ELEMID_RSN: + cie->ie_rsn = frm; + break; +#ifdef WAPI_ENABLE + case IEEE80211_ELEMID_WAPI: + cie->ie_wapi = frm; + break; +#endif + case IEEE80211_ELEMID_VENDOR: + if (iswpaoui(frm)) { + cie->ie_wpa = frm; + } else if (iswmmoui(frm)) { + cie->ie_wmm = frm; + } else if (isatherosoui(frm)) { + cie->ie_ath = frm; + } else if(iswscoui(frm)) { + cie->ie_wsc = frm; + } +#ifdef PYXIS_ADHOC + else if(ispyxisoui(frm)) { + cie->ie_pyxis= frm; + } +#endif + break; + default: + break; + } + frm += frm[1] + 2; + } + IEEE80211_VERIFY_ELEMENT(cie->ie_rates, IEEE80211_RATE_MAXSIZE); + IEEE80211_VERIFY_ELEMENT(cie->ie_ssid, IEEE80211_NWID_LEN); + + return A_OK; +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/wlan_utils.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wlan_utils.c --- linux-2.6.26/drivers/net/wireless/ath6k22/wlan_utils.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wlan_utils.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,61 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This module implements frequently used wlan utilies +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" + +/* + * converts ieee channel number to frequency + */ +A_UINT16 +wlan_ieee2freq(int chan) +{ + if (chan == 14) { + return 2484; + } + if (chan < 14) { /* 0-13 */ + return (2407 + (chan*5)); + } + if (chan < 27) { /* 15-26 */ + return (2512 + ((chan-15)*20)); + } + return (5000 + (chan*5)); +} + +/* + * Converts MHz frequency to IEEE channel number. + */ +A_UINT32 +wlan_freq2ieee(A_UINT16 freq) +{ + if (freq == 2484) + return 14; + if (freq < 2484) + return (freq - 2407) / 5; + if (freq < 5000) + return 15 + ((freq - 2512) / 20); + return (freq - 5000) / 5; +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/wmi.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wmi.c --- linux-2.6.26/drivers/net/wireless/ath6k22/wmi.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wmi.c 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,5873 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This module implements the hardware independent layer of the +// Wireless Module Interface (WMI) protocol. +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "htc.h" +#include "htc_api.h" +#include "wmi.h" +#include "wlan_api.h" +#include "wmi_api.h" +#include "ieee80211.h" +#include "ieee80211_node.h" +#include "dset_api.h" +#include "gpio_api.h" +#include "wmi_host.h" +#include "a_drv.h" +#include "a_drv_api.h" +#include "a_debug.h" +#include "dbglog_api.h" +#include "roaming.h" + +static A_STATUS wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); + +static A_STATUS wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_sync_point(struct wmi_t *wmip); + +static A_STATUS wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); + +static A_STATUS wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +#ifdef CONFIG_HOST_DSET_SUPPORT +static A_STATUS wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +#endif /* CONFIG_HOST_DSET_SUPPORT */ + + +static A_STATUS wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_channel_change_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS +wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len); + +static A_STATUS +wmi_set_params_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len); + +#ifdef CONFIG_HOST_GPIO_SUPPORT +static A_STATUS wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +#ifdef CONFIG_HOST_TCMD_SUPPORT +static A_STATUS +wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +#endif + +static A_STATUS +wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS +wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS +wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_BOOL +wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_INT32 rateIndex); + +static A_STATUS +wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS +wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +A_STATUS wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMIX_COMMAND_ID cmdId, + WMI_SYNC_FLAG syncflag); + +A_UINT8 ar6000_get_upper_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, A_UINT32 size); +A_UINT8 ar6000_get_lower_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, A_UINT32 size); + +void wmi_cache_configure_rssithreshold(struct wmi_t *wmip, WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd); +void wmi_cache_configure_snrthreshold(struct wmi_t *wmip, WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd); +static A_STATUS wmi_send_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd); +static A_STATUS wmi_send_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd); +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +static A_STATUS +wmi_prof_count_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + +static A_STATUS wmi_pspoll_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_dtimexpiry_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); + +static A_STATUS wmi_peer_node_event_rx (struct wmi_t *wmip, A_UINT8 *datap, + int len); + +#if defined(UNDER_CE) +#if defined(NDIS51_MINIPORT) +unsigned int processDot11Hdr = 0; +#else +unsigned int processDot11Hdr = 1; +#endif +#else +extern unsigned int processDot11Hdr; +#endif + +static const A_INT32 wmi_rateTable[] = { + 1000, + 2000, + 5500, + 11000, + 6000, + 9000, + 12000, + 18000, + 24000, + 36000, + 48000, + 54000, + 0}; + +#define MODE_A_SUPPORT_RATE_START ((A_INT32) 4) +#define MODE_A_SUPPORT_RATE_STOP ((A_INT32) 11) + +#define MODE_GONLY_SUPPORT_RATE_START MODE_A_SUPPORT_RATE_START +#define MODE_GONLY_SUPPORT_RATE_STOP MODE_A_SUPPORT_RATE_STOP + +#define MODE_B_SUPPORT_RATE_START ((A_INT32) 0) +#define MODE_B_SUPPORT_RATE_STOP ((A_INT32) 3) + +#define MODE_G_SUPPORT_RATE_START ((A_INT32) 0) +#define MODE_G_SUPPORT_RATE_STOP ((A_INT32) 11) + +#define MAX_NUMBER_OF_SUPPORT_RATES (MODE_G_SUPPORT_RATE_STOP + 1) + +/* 802.1d to AC mapping. Refer pg 57 of WMM-test-plan-v1.2 */ +const A_UINT8 up_to_ac[]= { + WMM_AC_BE, + WMM_AC_BK, + WMM_AC_BK, + WMM_AC_BE, + WMM_AC_VI, + WMM_AC_VI, + WMM_AC_VO, + WMM_AC_VO, + }; + +#include "athstartpack.h" + +/* This stuff is used when we want a simple layer-3 visibility */ +typedef PREPACK struct _iphdr { + A_UINT8 ip_ver_hdrlen; /* version and hdr length */ + A_UINT8 ip_tos; /* type of service */ + A_UINT16 ip_len; /* total length */ + A_UINT16 ip_id; /* identification */ + A_INT16 ip_off; /* fragment offset field */ +#define IP_DF 0x4000 /* dont fragment flag */ +#define IP_MF 0x2000 /* more fragments flag */ +#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */ + A_UINT8 ip_ttl; /* time to live */ + A_UINT8 ip_p; /* protocol */ + A_UINT16 ip_sum; /* checksum */ + A_UINT8 ip_src[4]; /* source and dest address */ + A_UINT8 ip_dst[4]; +} POSTPACK iphdr; + +#include "athendpack.h" + +A_INT16 rssi_event_value = 0; +A_INT16 snr_event_value = 0; + +void * +wmi_init(void *devt) +{ + struct wmi_t *wmip; + + wmip = A_MALLOC (sizeof(struct wmi_t)); + if (wmip == NULL) { + return (NULL); + } + A_MEMZERO(wmip, sizeof(*wmip)); + A_MUTEX_INIT(&wmip->wmi_lock); + wmip->wmi_devt = devt; + wlan_node_table_init(wmip, &wmip->wmi_scan_table); + wmi_qos_state_init(wmip); + + wmip->wmi_powerMode = REC_POWER; + wmip->wmi_phyMode = WMI_11G_MODE; + + wmip->wmi_pair_crypto_type = NONE_CRYPT; + wmip->wmi_grp_crypto_type = NONE_CRYPT; + + return (wmip); +} + +void +wmi_qos_state_init(struct wmi_t *wmip) +{ + A_UINT8 i; + + if (wmip == NULL) { + return; + } + LOCK_WMI(wmip); + + /* Initialize QoS States */ + wmip->wmi_numQoSStream = 0; + + wmip->wmi_fatPipeExists = 0; + + for (i=0; i < WMM_NUM_AC; i++) { + wmip->wmi_streamExistsForAC[i]=0; + } + + UNLOCK_WMI(wmip); + + A_WMI_SET_NUMDATAENDPTS(wmip->wmi_devt, 1); +} + +void +wmi_set_control_ep(struct wmi_t * wmip, HTC_ENDPOINT_ID eid) +{ + A_ASSERT( eid != ENDPOINT_UNUSED); + wmip->wmi_endpoint_id = eid; +} + +HTC_ENDPOINT_ID +wmi_get_control_ep(struct wmi_t * wmip) +{ + return(wmip->wmi_endpoint_id); +} + +void +wmi_shutdown(struct wmi_t *wmip) +{ + if (wmip != NULL) { + wlan_node_table_cleanup(&wmip->wmi_scan_table); + if (A_IS_MUTEX_VALID(&wmip->wmi_lock)) { + A_MUTEX_DELETE(&wmip->wmi_lock); + } + A_FREE(wmip); + } +} + +/* + * performs DIX to 802.3 encapsulation for transmit packets. + * uses passed in buffer. Returns buffer or NULL if failed. + * Assumes the entire DIX header is contigous and that there is + * enough room in the buffer for a 802.3 mac header and LLC+SNAP headers. + */ +A_STATUS +wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf) +{ + A_UINT8 *datap; + A_UINT16 typeorlen; + ATH_MAC_HDR macHdr; + ATH_LLC_SNAP_HDR *llcHdr; + + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_HEADROOM(osbuf) < + (sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR))) + { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + typeorlen = *(A_UINT16 *)(datap + ATH_MAC_LEN + ATH_MAC_LEN); + + if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) { + /* + * packet is already in 802.3 format - return success + */ + A_DPRINTF(DBG_WMI, (DBGFMT "packet already 802.3\n", DBGARG)); + return (A_OK); + } + + /* + * Save mac fields and length to be inserted later + */ + A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN); + A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN); + macHdr.typeOrLen = A_CPU2BE16(A_NETBUF_LEN(osbuf) - sizeof(ATH_MAC_HDR) + + sizeof(ATH_LLC_SNAP_HDR)); + + /* + * Make room for LLC+SNAP headers + */ + if (A_NETBUF_PUSH(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR)); + + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR)); + llcHdr->dsap = 0xAA; + llcHdr->ssap = 0xAA; + llcHdr->cntl = 0x03; + llcHdr->orgCode[0] = 0x0; + llcHdr->orgCode[1] = 0x0; + llcHdr->orgCode[2] = 0x0; + llcHdr->etherType = typeorlen; + + return (A_OK); +} + +/* + * Adds a WMI data header + * Assumes there is enough room in the buffer to add header. + */ +A_STATUS +wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType, A_BOOL bMoreData) +{ + WMI_DATA_HDR *dtHdr; + + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf); + dtHdr->info = msgType; + if (bMoreData) { + WMI_DATA_HDR_SET_MORE_BIT(dtHdr); + } + dtHdr->rssi = 0; + + return (A_OK); +} + +A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT32 layer2Priority, A_BOOL wmmEnabled) +{ + A_UINT8 *datap; + A_UINT8 trafficClass = WMM_AC_BE; + A_UINT16 ipType = IP_ETHERTYPE; + WMI_DATA_HDR *dtHdr; + A_BOOL streamExists = FALSE; + A_UINT8 userPriority; + A_UINT32 hdrsize; + ATH_LLC_SNAP_HDR *llcHdr; + + WMI_CREATE_PSTREAM_CMD cmd; + + A_ASSERT(osbuf != NULL); + + // + // Initialize header size + // + hdrsize = 0; + + datap = A_NETBUF_DATA(osbuf); + + if (!wmmEnabled) + { + /* If WMM is disabled all traffic goes as BE traffic */ + userPriority = 0; + } + else + { + if (processDot11Hdr) + { + hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32)); + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) + + hdrsize); + } + else + { + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) + + sizeof(ATH_MAC_HDR)); + } + + if (llcHdr->etherType == A_CPU2BE16(ipType)) + { + /* Extract the endpoint info from the TOS field in the IP header */ + + userPriority = wmi_determine_userPriority (((A_UINT8 *)llcHdr) + sizeof(ATH_LLC_SNAP_HDR),layer2Priority); + } + else + { + userPriority = layer2Priority & 0x7; + } + } + + trafficClass = convert_userPriority_to_trafficClass(userPriority); + + dtHdr = (WMI_DATA_HDR *)datap; + dtHdr->info |= (userPriority & WMI_DATA_HDR_UP_MASK) << WMI_DATA_HDR_UP_SHIFT; /* lower 3-bits are 802.1d priority */ + + LOCK_WMI(wmip); + streamExists = wmip->wmi_fatPipeExists; + UNLOCK_WMI(wmip); + + if (!(streamExists & (1 << trafficClass))) + { + + A_MEMZERO (&cmd, sizeof(cmd)); + cmd.trafficClass = trafficClass; + cmd.userPriority = userPriority; + cmd.inactivityInt = WMI_IMPLICIT_PSTREAM_INACTIVITY_INT; + /* Implicit streams are created with TSID 0xFF */ + + cmd.tsid = WMI_IMPLICIT_PSTREAM; + wmi_create_pstream_cmd (wmip, &cmd); + } + + return trafficClass; +} + +A_STATUS +wmi_dot11_hdr_add (struct wmi_t *wmip, void *osbuf, NETWORK_TYPE mode) +{ + A_UINT8 *datap; + A_UINT16 typeorlen; + ATH_MAC_HDR macHdr; + ATH_LLC_SNAP_HDR *llcHdr; + struct ieee80211_frame *wh; + A_UINT32 hdrsize; + + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_HEADROOM(osbuf) < + (sizeof(struct ieee80211_qosframe) + sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR))) + { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + typeorlen = *(A_UINT16 *)(datap + ATH_MAC_LEN + ATH_MAC_LEN); + + if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) { + /* + * packet is already in 802.3 format - return success + */ + A_DPRINTF(DBG_WMI, (DBGFMT "packet already 802.3\n", DBGARG)); + goto AddDot11Hdr; + } + + /* + * Save mac fields and length to be inserted later + */ + A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN); + A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN); + macHdr.typeOrLen = A_CPU2BE16(A_NETBUF_LEN(osbuf) - sizeof(ATH_MAC_HDR) + + sizeof(ATH_LLC_SNAP_HDR)); + + // Remove the Ethernet hdr + A_NETBUF_PULL(osbuf, sizeof(ATH_MAC_HDR)); + + /* + * Make room for LLC+SNAP headers + */ + if (A_NETBUF_PUSH(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + llcHdr = (ATH_LLC_SNAP_HDR *)(datap); + llcHdr->dsap = 0xAA; + llcHdr->ssap = 0xAA; + llcHdr->cntl = 0x03; + llcHdr->orgCode[0] = 0x0; + llcHdr->orgCode[1] = 0x0; + llcHdr->orgCode[2] = 0x0; + llcHdr->etherType = typeorlen; + +AddDot11Hdr: + /* Make room for 802.11 hdr */ + if (wmip->wmi_is_wmm_enabled) + { + hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32)); + if (A_NETBUF_PUSH(osbuf, hdrsize) != A_OK) + { + return A_NO_MEMORY; + } + wh = (struct ieee80211_frame *) A_NETBUF_DATA(osbuf); + wh->i_fc[0] = IEEE80211_FC0_SUBTYPE_QOS; + } + else + { + hdrsize = A_ROUND_UP(sizeof(struct ieee80211_frame),sizeof(A_UINT32)); + if (A_NETBUF_PUSH(osbuf, hdrsize) != A_OK) + { + return A_NO_MEMORY; + } + wh = (struct ieee80211_frame *) A_NETBUF_DATA(osbuf); + wh->i_fc[0] = IEEE80211_FC0_SUBTYPE_DATA; + } + /* Setup the SA & DA */ + IEEE80211_ADDR_COPY(wh->i_addr2, macHdr.srcMac); + + if (mode == INFRA_NETWORK) { + IEEE80211_ADDR_COPY(wh->i_addr3, macHdr.dstMac); + } + else if (mode == ADHOC_NETWORK) { + IEEE80211_ADDR_COPY(wh->i_addr1, macHdr.dstMac); + } + + return (A_OK); +} + +A_STATUS +wmi_dot11_hdr_remove(struct wmi_t *wmip, void *osbuf) +{ + A_UINT8 *datap; + struct ieee80211_frame *pwh,wh; + A_UINT8 type,subtype; + ATH_LLC_SNAP_HDR *llcHdr; + ATH_MAC_HDR macHdr; + A_UINT32 hdrsize; + + A_ASSERT(osbuf != NULL); + datap = A_NETBUF_DATA(osbuf); + + pwh = (struct ieee80211_frame *)datap; + type = pwh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; + subtype = pwh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; + + A_MEMCPY((A_UINT8 *)&wh, datap, sizeof(struct ieee80211_frame)); + + /* strip off the 802.11 hdr*/ + if (subtype == IEEE80211_FC0_SUBTYPE_QOS) { + hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32)); + A_NETBUF_PULL(osbuf, hdrsize); + } else if (subtype == IEEE80211_FC0_SUBTYPE_DATA) { + A_NETBUF_PULL(osbuf, sizeof(struct ieee80211_frame)); + } + + datap = A_NETBUF_DATA(osbuf); + llcHdr = (ATH_LLC_SNAP_HDR *)(datap); + + macHdr.typeOrLen = llcHdr->etherType; + + switch (wh.i_fc[1] & IEEE80211_FC1_DIR_MASK) { + case IEEE80211_FC1_DIR_NODS: + IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr1); + IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr2); + break; + case IEEE80211_FC1_DIR_TODS: + IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr3); + IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr2); + break; + case IEEE80211_FC1_DIR_FROMDS: + IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr1); + IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr3); + break; + case IEEE80211_FC1_DIR_DSTODS: + break; + } + + // Remove the LLC Hdr. + A_NETBUF_PULL(osbuf, sizeof(ATH_LLC_SNAP_HDR)); + + // Insert the ATH MAC hdr. + + A_NETBUF_PUSH(osbuf, sizeof(ATH_MAC_HDR)); + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY (datap, &macHdr, sizeof(ATH_MAC_HDR)); + + return A_OK; +} + +/* + * performs 802.3 to DIX encapsulation for received packets. + * Assumes the entire 802.3 header is contigous. + */ +A_STATUS +wmi_dot3_2_dix(struct wmi_t *wmip, void *osbuf) +{ + A_UINT8 *datap; + ATH_MAC_HDR macHdr; + ATH_LLC_SNAP_HDR *llcHdr; + + A_ASSERT(osbuf != NULL); + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY(&macHdr, datap, sizeof(ATH_MAC_HDR)); + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR)); + macHdr.typeOrLen = llcHdr->etherType; + + if (A_NETBUF_PULL(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR)); + + return (A_OK); +} + +/* + * Removes a WMI data header + */ +A_STATUS +wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf) +{ + A_ASSERT(osbuf != NULL); + + return (A_NETBUF_PULL(osbuf, sizeof(WMI_DATA_HDR))); +} + +void +wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg) +{ + wlan_iterate_nodes(&wmip->wmi_scan_table, f, arg); +} + +/* + * WMI Extended Event received from Target. + */ +A_STATUS +wmi_control_rx_xtnd(struct wmi_t *wmip, void *osbuf) +{ + WMIX_CMD_HDR *cmd; + A_UINT16 id; + A_UINT8 *datap; + A_UINT32 len; + A_STATUS status = A_OK; + + if (A_NETBUF_LEN(osbuf) < sizeof(WMIX_CMD_HDR)) { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + A_NETBUF_FREE(osbuf); + return A_ERROR; + } + + cmd = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf); + id = cmd->commandId; + + if (A_NETBUF_PULL(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + A_NETBUF_FREE(osbuf); + return A_ERROR; + } + + datap = A_NETBUF_DATA(osbuf); + len = A_NETBUF_LEN(osbuf); + + switch (id) { + case (WMIX_DSETOPENREQ_EVENTID): + status = wmi_dset_open_req_rx(wmip, datap, len); + break; +#ifdef CONFIG_HOST_DSET_SUPPORT + case (WMIX_DSETCLOSE_EVENTID): + status = wmi_dset_close_rx(wmip, datap, len); + break; + case (WMIX_DSETDATAREQ_EVENTID): + status = wmi_dset_data_req_rx(wmip, datap, len); + break; +#endif /* CONFIG_HOST_DSET_SUPPORT */ +#ifdef CONFIG_HOST_GPIO_SUPPORT + case (WMIX_GPIO_INTR_EVENTID): + wmi_gpio_intr_rx(wmip, datap, len); + break; + case (WMIX_GPIO_DATA_EVENTID): + wmi_gpio_data_rx(wmip, datap, len); + break; + case (WMIX_GPIO_ACK_EVENTID): + wmi_gpio_ack_rx(wmip, datap, len); + break; +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + case (WMIX_HB_CHALLENGE_RESP_EVENTID): + wmi_hbChallengeResp_rx(wmip, datap, len); + break; + case (WMIX_DBGLOG_EVENTID): + wmi_dbglog_event_rx(wmip, datap, len); + break; +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) + case (WMIX_PROF_COUNT_EVENTID): + wmi_prof_count_rx(wmip, datap, len); + break; +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + default: + A_DPRINTF(DBG_WMI|DBG_ERROR, + (DBGFMT "Unknown id 0x%x\n", DBGARG, id)); + wmip->wmi_stats.cmd_id_err++; + status = A_ERROR; + break; + } + + return status; +} + +/* + * Control Path + */ +A_UINT32 cmdRecvNum; + +A_STATUS +wmi_control_rx(struct wmi_t *wmip, void *osbuf) +{ + WMI_CMD_HDR *cmd; + A_UINT16 id; + A_UINT8 *datap; + A_UINT32 len, i, loggingReq; + A_STATUS status = A_OK; + + A_ASSERT(osbuf != NULL); + if (A_NETBUF_LEN(osbuf) < sizeof(WMI_CMD_HDR)) { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + A_NETBUF_FREE(osbuf); + return A_ERROR; + } + + cmd = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf); + id = cmd->commandId; + + if (A_NETBUF_PULL(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + A_NETBUF_FREE(osbuf); + return A_ERROR; + } + + datap = A_NETBUF_DATA(osbuf); + len = A_NETBUF_LEN(osbuf); + + loggingReq = 0; + + ar6000_get_driver_cfg(wmip->wmi_devt, + AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS, + &loggingReq); + + if(loggingReq) { + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI %d \n",id)); + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI recv, MsgNo %d : ", cmdRecvNum)); + for(i = 0; i < len; i++) + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("%x ", datap[i])); + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("\n")); + } + + LOCK_WMI(wmip); + cmdRecvNum++; + UNLOCK_WMI(wmip); + + switch (id) { + case (WMI_GET_BITRATE_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_BITRATE_CMDID\n", DBGARG)); + status = wmi_bitrate_reply_rx(wmip, datap, len); + break; + case (WMI_GET_CHANNEL_LIST_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_CHANNEL_LIST_CMDID\n", DBGARG)); + status = wmi_channelList_reply_rx(wmip, datap, len); + break; + case (WMI_GET_TX_PWR_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_TX_PWR_CMDID\n", DBGARG)); + status = wmi_txPwr_reply_rx(wmip, datap, len); + break; + case (WMI_READY_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_READY_EVENTID\n", DBGARG)); + status = wmi_ready_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + A_WMI_DBGLOG_INIT_DONE(wmip->wmi_devt); + break; + case (WMI_CONNECT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CONNECT_EVENTID\n", DBGARG)); + status = wmi_connect_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_DISCONNECT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_DISCONNECT_EVENTID\n", DBGARG)); + status = wmi_disconnect_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_PEER_NODE_EVENTID): + A_DPRINTF (DBG_WMI, (DBGFMT "WMI_PEER_NODE_EVENTID\n", DBGARG)); + status = wmi_peer_node_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_TKIP_MICERR_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TKIP_MICERR_EVENTID\n", DBGARG)); + status = wmi_tkip_micerr_event_rx(wmip, datap, len); + break; + case (WMI_BSSINFO_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BSSINFO_EVENTID\n", DBGARG)); + status = wmi_bssInfo_event_rx(wmip, datap, len); + A_WMI_SEND_GENERIC_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_REGDOMAIN_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REGDOMAIN_EVENTID\n", DBGARG)); + status = wmi_regDomain_event_rx(wmip, datap, len); + break; + case (WMI_PSTREAM_TIMEOUT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_PSTREAM_TIMEOUT_EVENTID\n", DBGARG)); + status = wmi_pstream_timeout_event_rx(wmip, datap, len); + /* pstreams are fatpipe abstractions that get implicitly created. + * User apps only deal with thinstreams. creation of a thinstream + * by the user or data traffic flow in an AC triggers implicit + * pstream creation. Do we need to send this event to App..? + * no harm in sending it. + */ + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_NEIGHBOR_REPORT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_NEIGHBOR_REPORT_EVENTID\n", DBGARG)); + status = wmi_neighborReport_event_rx(wmip, datap, len); + break; + case (WMI_SCAN_COMPLETE_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SCAN_COMPLETE_EVENTID\n", DBGARG)); + status = wmi_scanComplete_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_CMDERROR_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CMDERROR_EVENTID\n", DBGARG)); + status = wmi_errorEvent_rx(wmip, datap, len); + break; + case (WMI_REPORT_STATISTICS_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_STATISTICS_EVENTID\n", DBGARG)); + status = wmi_statsEvent_rx(wmip, datap, len); + break; + case (WMI_RSSI_THRESHOLD_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_RSSI_THRESHOLD_EVENTID\n", DBGARG)); + status = wmi_rssiThresholdEvent_rx(wmip, datap, len); + break; + case (WMI_ERROR_REPORT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_ERROR_REPORT_EVENTID\n", DBGARG)); + status = wmi_reportErrorEvent_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_OPT_RX_FRAME_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_OPT_RX_FRAME_EVENTID\n", DBGARG)); + status = wmi_opt_frame_event_rx(wmip, datap, len); + break; + case (WMI_REPORT_ROAM_TBL_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_TBL_EVENTID\n", DBGARG)); + status = wmi_roam_tbl_event_rx(wmip, datap, len); + break; + case (WMI_EXTENSION_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_EXTENSION_EVENTID\n", DBGARG)); + status = wmi_control_rx_xtnd(wmip, osbuf); + break; + case (WMI_CAC_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CAC_EVENTID\n", DBGARG)); + status = wmi_cac_event_rx(wmip, datap, len); + break; + case (WMI_CHANNEL_CHANGE_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CHANNEL_CHANGE_EVENTID\n", DBGARG)); + status = wmi_channel_change_event_rx(wmip, datap, len); + break; + case (WMI_REPORT_ROAM_DATA_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_DATA_EVENTID\n", DBGARG)); + status = wmi_roam_data_event_rx(wmip, datap, len); + break; +#ifdef CONFIG_HOST_TCMD_SUPPORT + case (WMI_TEST_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TEST_EVENTID\n", DBGARG)); + status = wmi_tcmd_test_report_rx(wmip, datap, len); + break; +#endif + case (WMI_GET_FIXRATES_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_FIXRATES_CMDID\n", DBGARG)); + status = wmi_ratemask_reply_rx(wmip, datap, len); + break; + case (WMI_TX_RETRY_ERR_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TX_RETRY_ERR_EVENTID\n", DBGARG)); + status = wmi_txRetryErrEvent_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_SNR_THRESHOLD_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SNR_THRESHOLD_EVENTID\n", DBGARG)); + status = wmi_snrThresholdEvent_rx(wmip, datap, len); + break; + case (WMI_LQ_THRESHOLD_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_LQ_THRESHOLD_EVENTID\n", DBGARG)); + status = wmi_lqThresholdEvent_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_APLIST_EVENTID): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Received APLIST Event\n")); + status = wmi_aplistEvent_rx(wmip, datap, len); + break; + case (WMI_GET_KEEPALIVE_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_KEEPALIVE_CMDID\n", DBGARG)); + status = wmi_keepalive_reply_rx(wmip, datap, len); + break; + case (WMI_GET_WOW_LIST_EVENTID): + status = wmi_get_wow_list_event_rx(wmip, datap, len); + break; + case (WMI_GET_PMKID_LIST_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_PMKID_LIST Event\n", DBGARG)); + status = wmi_get_pmkid_list_event_rx(wmip, datap, len); + break; + case (WMI_PSPOLL_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_PSPOLL_EVENT\n", DBGARG)); + status = wmi_pspoll_event_rx(wmip, datap, len); + break; + case (WMI_DTIMEXPIRY_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_DTIMEXPIRY_EVENT\n", DBGARG)); + status = wmi_dtimexpiry_event_rx(wmip, datap, len); + break; + case (WMI_SET_PARAMS_REPLY_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SET_PARAMS_REPLY Event\n", DBGARG)); + status = wmi_set_params_event_rx(wmip, datap, len); + break; + default: + A_DPRINTF(DBG_WMI|DBG_ERROR, + (DBGFMT "Unknown id 0x%x\n", DBGARG, id)); + wmip->wmi_stats.cmd_id_err++; + status = A_ERROR; + break; + } + + A_NETBUF_FREE(osbuf); + + return status; +} + +/* Send a "simple" wmi command -- one with no arguments */ +static A_STATUS +wmi_simple_cmd(struct wmi_t *wmip, WMI_COMMAND_ID cmdid) +{ + void *osbuf; + + osbuf = A_NETBUF_ALLOC(0); + + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + return (wmi_cmd_send(wmip, osbuf, cmdid, NO_SYNC_WMIFLAG)); +} + +/* Send a "simple" extended wmi command -- one with no arguments. + Enabling this command only if GPIO or profiling support is enabled. + This is to suppress warnings on some platforms */ +#if defined(CONFIG_HOST_GPIO_SUPPORT) || defined(CONFIG_TARGET_PROFILE_SUPPORT) +static A_STATUS +wmi_simple_cmd_xtnd(struct wmi_t *wmip, WMIX_COMMAND_ID cmdid) +{ + void *osbuf; + + osbuf = A_NETBUF_ALLOC(0); + + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + return (wmi_cmd_send_xtnd(wmip, osbuf, cmdid, NO_SYNC_WMIFLAG)); +} +#endif + +static A_STATUS +wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_READY_EVENT *ev = (WMI_READY_EVENT *)datap; + + if (len < sizeof(WMI_READY_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + wmip->wmi_ready = TRUE; + A_WMI_READY_EVENT(wmip->wmi_devt, ev->macaddr, ev->phyCapability, + ev->version); + + return A_OK; +} + +#define LE_READ_4(p) \ + ((A_UINT32) \ + ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8) | \ + (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24))) + +static int __inline +iswmmoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((WMM_OUI_TYPE<<24)|WMM_OUI); +} + +static int __inline +iswmmparam(const A_UINT8 *frm) +{ + return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE; +} + + +static A_STATUS +wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CONNECT_EVENT *ev; + A_UINT8 *pie,*peie; + + if (len < sizeof(WMI_CONNECT_EVENT)) + { + return A_EINVAL; + } + ev = (WMI_CONNECT_EVENT *)datap; + + A_DPRINTF(DBG_WMI, + (DBGFMT "freq %d bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", + DBGARG, ev->channel, + ev->bssid[0], ev->bssid[1], ev->bssid[2], + ev->bssid[3], ev->bssid[4], ev->bssid[5])); + + A_MEMCPY(wmip->wmi_bssid, ev->bssid, ATH_MAC_LEN); + + /* initialize pointer to start of assoc rsp IEs */ + pie = ev->assocInfo + ev->beaconIeLen + ev->assocReqLen + + sizeof(A_UINT16) + /* capinfo*/ + sizeof(A_UINT16) + /* status Code */ + sizeof(A_UINT16) ; /* associd */ + + /* initialize pointer to end of assoc rsp IEs */ + peie = ev->assocInfo + ev->beaconIeLen + ev->assocReqLen + ev->assocRespLen; + + while (pie < peie) + { + switch (*pie) + { + case IEEE80211_ELEMID_VENDOR: + if (iswmmoui(pie)) + { + if(iswmmparam (pie)) + { + wmip->wmi_is_wmm_enabled = TRUE; + } + } + break; + } + + if (wmip->wmi_is_wmm_enabled) + { + break; + } + pie += pie[1] + 2; + } + + A_WMI_CONNECT_EVENT (wmip->wmi_devt, ev->channel, ev->bssid, + ev->listenInterval, ev->beaconInterval, + (NETWORK_TYPE) ev->networkType, ev->beaconIeLen, + ev->assocReqLen, ev->assocRespLen, + ev->assocInfo); + + return A_OK; +} + +static A_STATUS +wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_REG_DOMAIN_EVENT *ev; + + if (len < sizeof(*ev)) { + return A_EINVAL; + } + ev = (WMI_REG_DOMAIN_EVENT *)datap; + + A_WMI_REGDOMAIN_EVENT(wmip->wmi_devt, ev->regDomain); + + return A_OK; +} + +static A_STATUS +wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_NEIGHBOR_REPORT_EVENT *ev; + int numAps; + + if (len < sizeof(*ev)) { + return A_EINVAL; + } + ev = (WMI_NEIGHBOR_REPORT_EVENT *)datap; + numAps = ev->numberOfAps; + + if (len < (int)(sizeof(*ev) + ((numAps - 1) * sizeof(WMI_NEIGHBOR_INFO)))) { + return A_EINVAL; + } + + A_WMI_NEIGHBORREPORT_EVENT(wmip->wmi_devt, numAps, ev->neighbor); + + return A_OK; +} + +static A_STATUS +wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_DISCONNECT_EVENT *ev; + + if (len < sizeof(WMI_DISCONNECT_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + ev = (WMI_DISCONNECT_EVENT *)datap; + + A_MEMZERO(wmip->wmi_bssid, sizeof(wmip->wmi_bssid)); + + wmip->wmi_is_wmm_enabled = FALSE; + wmip->wmi_pair_crypto_type = NONE_CRYPT; + wmip->wmi_grp_crypto_type = NONE_CRYPT; + + A_WMI_DISCONNECT_EVENT(wmip->wmi_devt, ev->disconnectReason, ev->bssid, + ev->assocRespLen, ev->assocInfo, ev->protocolReasonStatus); + + return A_OK; +} + +static A_STATUS +wmi_peer_node_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_PEER_NODE_EVENT *ev; + + if (len < sizeof(WMI_PEER_NODE_EVENT)) { + return A_EINVAL; + } + ev = (WMI_PEER_NODE_EVENT *)datap; + if (ev->eventCode == PEER_NODE_JOIN_EVENT) { + A_DPRINTF (DBG_WMI, (DBGFMT "Joined node with Macaddr: ", DBGARG)); + } else if(ev->eventCode == PEER_NODE_LEAVE_EVENT) { + A_DPRINTF (DBG_WMI, (DBGFMT "left node with Macaddr: ", DBGARG)); + } + + A_WMI_PEER_EVENT (wmip->wmi_devt, ev->eventCode, ev->peerMacAddr); + + return A_OK; +} + +static A_STATUS +wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TKIP_MICERR_EVENT *ev; + + if (len < sizeof(*ev)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + ev = (WMI_TKIP_MICERR_EVENT *)datap; + A_WMI_TKIP_MICERR_EVENT(wmip->wmi_devt, ev->keyid, ev->ismcast); + + return A_OK; +} + +static A_STATUS +wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + bss_t *bss = NULL; + WMI_BSS_INFO_HDR *bih; + A_UINT8 *buf; + A_UINT32 nodeCachingAllowed = 1; + A_UCHAR cached_ssid_len = 0; + A_UCHAR cached_ssid_buf[IEEE80211_NWID_LEN] = {0}; + A_UINT8 beacon_ssid_len = 0; + + if (len <= sizeof(WMI_BSS_INFO_HDR)) { + return A_EINVAL; + } + + bih = (WMI_BSS_INFO_HDR *)datap; + bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid); + + if (bih->rssi > 0) { + if (NULL == bss) + return A_OK; //no node found in the table, just drop the node with incorrect RSSI + else + bih->rssi = bss->ni_rssi; //Adjust RSSI in datap in case it is used in A_WMI_BSSINFO_EVENT_RX + } + + A_WMI_BSSINFO_EVENT_RX(wmip->wmi_devt, datap, len); + /* What is driver config for wlan node caching? */ + if(ar6000_get_driver_cfg(wmip->wmi_devt, + AR6000_DRIVER_CFG_GET_WLANNODECACHING, + &nodeCachingAllowed) != A_OK) { + return A_EINVAL; + } + + if(!nodeCachingAllowed) { + return A_OK; + } + + buf = datap + sizeof(WMI_BSS_INFO_HDR); + len -= sizeof(WMI_BSS_INFO_HDR); + + A_DPRINTF(DBG_WMI2, (DBGFMT "bssInfo event - ch %u, rssi %02x, " + "bssid \"%02x:%02x:%02x:%02x:%02x:%02x\"\n", DBGARG, + bih->channel, (unsigned char) bih->rssi, bih->bssid[0], + bih->bssid[1], bih->bssid[2], bih->bssid[3], bih->bssid[4], + bih->bssid[5])); + + if (bss != NULL) { + /* + * Free up the node. Not the most efficient process given + * we are about to allocate a new node but it is simple and should be + * adequate. + */ + + /* In case of hidden AP, beacon will not have ssid, + * but a directed probe response will have it, + * so cache the probe-resp-ssid if already present. */ + if (BEACON_FTYPE == bih->frameType) + { + A_UCHAR *ie_ssid; + + ie_ssid = bss->ni_cie.ie_ssid; + if(ie_ssid && (ie_ssid[1] <= IEEE80211_NWID_LEN) && (ie_ssid[2] != 0)) + { + cached_ssid_len = ie_ssid[1]; + memcpy(cached_ssid_buf, ie_ssid + 2, cached_ssid_len); + } + } + + wlan_node_reclaim(&wmip->wmi_scan_table, bss); + } + + /* beacon/probe response frame format + * [8] time stamp + * [2] beacon interval + * [2] capability information + * [tlv] ssid */ + beacon_ssid_len = buf[SSID_IE_LEN_INDEX]; + + /* If ssid is cached for this hidden AP, then change buffer len accordingly. */ + if ((BEACON_FTYPE == bih->frameType) && + (0 != cached_ssid_len) && + (0 == beacon_ssid_len || (cached_ssid_len > beacon_ssid_len && 0 == buf[SSID_IE_LEN_INDEX + 1]))) + { + len += (cached_ssid_len - beacon_ssid_len); + } + + bss = wlan_node_alloc(&wmip->wmi_scan_table, len); + if (bss == NULL) { + return A_NO_MEMORY; + } + + bss->ni_snr = bih->snr; + bss->ni_rssi = bih->rssi; + A_ASSERT(bss->ni_buf != NULL); + + /* In case of hidden AP, beacon will not have ssid, + * but a directed probe response will have it, + * so place the cached-ssid(probe-resp) in the bssinfo. */ + if ((BEACON_FTYPE == bih->frameType) && + (0 != cached_ssid_len) && + (0 == beacon_ssid_len || (beacon_ssid_len && 0 == buf[SSID_IE_LEN_INDEX + 1]))) + { + A_UINT8 *ni_buf = bss->ni_buf; + int buf_len = len; + + /* copy the first 14 bytes such as + * time-stamp(8), beacon-interval(2), cap-info(2), ssid-id(1), ssid-len(1). */ + A_MEMCPY(ni_buf, buf, SSID_IE_LEN_INDEX + 1); + + ni_buf[SSID_IE_LEN_INDEX] = cached_ssid_len; + ni_buf += (SSID_IE_LEN_INDEX + 1); + + buf += (SSID_IE_LEN_INDEX + 1); + buf_len -= (SSID_IE_LEN_INDEX + 1); + + /* copy the cached ssid */ + A_MEMCPY(ni_buf, cached_ssid_buf, cached_ssid_len); + ni_buf += cached_ssid_len; + + buf += beacon_ssid_len; + buf_len -= beacon_ssid_len; + + if (cached_ssid_len > beacon_ssid_len) + buf_len -= (cached_ssid_len - beacon_ssid_len); + + /* now copy the rest of bytes */ + A_MEMCPY(ni_buf, buf, buf_len); + } + else + A_MEMCPY(bss->ni_buf, buf, len); + + if (wlan_parse_beacon(bss->ni_buf, len, &bss->ni_cie) != A_OK) { + wlan_node_free(bss); + return A_EINVAL; + } + + /* + * Update the frequency in ie_chan, overwriting of channel number + * which is done in wlan_parse_beacon + */ + bss->ni_cie.ie_chan = bih->channel; + wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid); + + return A_OK; +} + +static A_STATUS +wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + bss_t *bss; + WMI_OPT_RX_INFO_HDR *bih; + A_UINT8 *buf; + + if (len <= sizeof(WMI_OPT_RX_INFO_HDR)) { + return A_EINVAL; + } + + bih = (WMI_OPT_RX_INFO_HDR *)datap; + buf = datap + sizeof(WMI_OPT_RX_INFO_HDR); + len -= sizeof(WMI_OPT_RX_INFO_HDR); + + A_DPRINTF(DBG_WMI2, (DBGFMT "opt frame event %2.2x:%2.2x\n", DBGARG, + bih->bssid[4], bih->bssid[5])); + + bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid); + if (bss != NULL) { + /* + * Free up the node. Not the most efficient process given + * we are about to allocate a new node but it is simple and should be + * adequate. + */ + wlan_node_reclaim(&wmip->wmi_scan_table, bss); + } + + bss = wlan_node_alloc(&wmip->wmi_scan_table, len); + if (bss == NULL) { + return A_NO_MEMORY; + } + + bss->ni_snr = bih->snr; + bss->ni_cie.ie_chan = bih->channel; + A_ASSERT(bss->ni_buf != NULL); + A_MEMCPY(bss->ni_buf, buf, len); + wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid); + + return A_OK; +} + + /* This event indicates inactivity timeout of a fatpipe(pstream) + * at the target + */ +static A_STATUS +wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_PSTREAM_TIMEOUT_EVENT *ev; + + if (len < sizeof(WMI_PSTREAM_TIMEOUT_EVENT)) { + return A_EINVAL; + } + + A_DPRINTF(DBG_WMI, (DBGFMT "wmi_pstream_timeout_event_rx\n", DBGARG)); + + ev = (WMI_PSTREAM_TIMEOUT_EVENT *)datap; + + /* When the pstream (fat pipe == AC) timesout, it means there were no + * thinStreams within this pstream & it got implicitly created due to + * data flow on this AC. We start the inactivity timer only for + * implicitly created pstream. Just reset the host state. + */ + /* Set the activeTsids for this AC to 0 */ + LOCK_WMI(wmip); + wmip->wmi_streamExistsForAC[ev->trafficClass]=0; + wmip->wmi_fatPipeExists &= ~(1 << ev->trafficClass); + UNLOCK_WMI(wmip); + + /*Indicate inactivity to driver layer for this fatpipe (pstream)*/ + A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, ev->trafficClass); + + return A_OK; +} + +static A_STATUS +wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_BIT_RATE_REPLY *reply; + A_INT32 rate; + /* 54149: + * WMI_BIT_RATE_CMD structure is changed to WMI_BIT_RATE_REPLY. + * since there is difference in the length and to avoid returning + * error value. + */ + if (len < sizeof(WMI_BIT_RATE_REPLY)) { + return A_EINVAL; + } + reply = (WMI_BIT_RATE_REPLY *)datap; + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - rateindex %d\n", DBGARG, reply->rateIndex)); + + if (reply->rateIndex == (A_INT8) RATE_AUTO) { + rate = RATE_AUTO; + } else { + rate = wmi_rateTable[(A_UINT32) reply->rateIndex]; + } + + A_WMI_BITRATE_RX(wmip->wmi_devt, rate); + + return A_OK; +} + +static A_STATUS +wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_FIX_RATES_CMD *reply; + + if (len < sizeof(WMI_BIT_RATE_CMD)) { + return A_EINVAL; + } + reply = (WMI_FIX_RATES_CMD *)datap; + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - fixed rate mask %x\n", DBGARG, reply->fixRateMask)); + + A_WMI_RATEMASK_RX(wmip->wmi_devt, reply->fixRateMask); + + return A_OK; +} + +static A_STATUS +wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CHANNEL_LIST_REPLY *reply; + + if (len < sizeof(WMI_CHANNEL_LIST_REPLY)) { + return A_EINVAL; + } + reply = (WMI_CHANNEL_LIST_REPLY *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_CHANNELLIST_RX(wmip->wmi_devt, reply->numChannels, + reply->channelList); + + return A_OK; +} + +static A_STATUS +wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TX_PWR_REPLY *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TX_PWR_REPLY *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TXPWR_RX(wmip->wmi_devt, reply->dbM); + + return A_OK; +} +static A_STATUS +wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_GET_KEEPALIVE_CMD *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_GET_KEEPALIVE_CMD *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_KEEPALIVE_RX(wmip->wmi_devt, reply->configured); + + return A_OK; +} + + +static A_STATUS +wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_DSETOPENREQ_EVENT *dsetopenreq; + + if (len < sizeof(WMIX_DSETOPENREQ_EVENT)) { + return A_EINVAL; + } + dsetopenreq = (WMIX_DSETOPENREQ_EVENT *)datap; + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - dset_id=0x%x\n", DBGARG, dsetopenreq->dset_id)); + A_WMI_DSET_OPEN_REQ(wmip->wmi_devt, + dsetopenreq->dset_id, + dsetopenreq->targ_dset_handle, + dsetopenreq->targ_reply_fn, + dsetopenreq->targ_reply_arg); + + return A_OK; +} + +#ifdef CONFIG_HOST_DSET_SUPPORT +static A_STATUS +wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_DSETCLOSE_EVENT *dsetclose; + + if (len < sizeof(WMIX_DSETCLOSE_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + dsetclose = (WMIX_DSETCLOSE_EVENT *)datap; + A_WMI_DSET_CLOSE(wmip->wmi_devt, dsetclose->access_cookie); + + return A_OK; +} + +static A_STATUS +wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_DSETDATAREQ_EVENT *dsetdatareq; + + if (len < sizeof(WMIX_DSETDATAREQ_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + dsetdatareq = (WMIX_DSETDATAREQ_EVENT *)datap; + A_WMI_DSET_DATA_REQ(wmip->wmi_devt, + dsetdatareq->access_cookie, + dsetdatareq->offset, + dsetdatareq->length, + dsetdatareq->targ_buf, + dsetdatareq->targ_reply_fn, + dsetdatareq->targ_reply_arg); + + return A_OK; +} +#endif /* CONFIG_HOST_DSET_SUPPORT */ + +static A_STATUS +wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_SCAN_COMPLETE_EVENT *ev; + + ev = (WMI_SCAN_COMPLETE_EVENT *)datap; + A_WMI_SCANCOMPLETE_EVENT(wmip->wmi_devt, (A_STATUS) ev->status); + + return A_OK; +} + +/* + * Target is reporting a programming error. This is for + * developer aid only. Target only checks a few common violations + * and it is responsibility of host to do all error checking. + * Behavior of target after wmi error event is undefined. + * A reset is recommended. + */ +static A_STATUS +wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CMD_ERROR_EVENT *ev; + + ev = (WMI_CMD_ERROR_EVENT *)datap; + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Programming Error: cmd=%d ", ev->commandId)); + switch (ev->errorCode) { + case (INVALID_PARAM): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal Parameter\n")); + break; + case (ILLEGAL_STATE): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal State\n")); + break; + case (INTERNAL_ERROR): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Internal Error\n")); + break; + } + + return A_OK; +} + + +static A_STATUS +wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TARGET_STATS *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TARGET_STATS *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TARGETSTATS_EVENT(wmip->wmi_devt, reply); + + return A_OK; +} + +static A_STATUS +wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_RSSI_THRESHOLD_EVENT *reply; + WMI_RSSI_THRESHOLD_VAL newThreshold; + WMI_RSSI_THRESHOLD_PARAMS_CMD cmd; + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_RSSI]; + A_UINT8 upper_rssi_threshold, lower_rssi_threshold; + A_INT16 rssi; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_RSSI_THRESHOLD_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + newThreshold = (WMI_RSSI_THRESHOLD_VAL) reply->range; + rssi = reply->rssi; + + /* + * Identify the threshold breached and communicate that to the app. After + * that install a new set of thresholds based on the signal quality + * reported by the target + */ + if (newThreshold) { + /* Upper threshold breached */ + if (rssi < sq_thresh->upper_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious upper RSSI threshold event: " + " %d\n", DBGARG, rssi)); + } else if ((rssi < sq_thresh->upper_threshold[1]) && + (rssi >= sq_thresh->upper_threshold[0])) + { + newThreshold = WMI_RSSI_THRESHOLD1_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[2]) && + (rssi >= sq_thresh->upper_threshold[1])) + { + newThreshold = WMI_RSSI_THRESHOLD2_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[3]) && + (rssi >= sq_thresh->upper_threshold[2])) + { + newThreshold = WMI_RSSI_THRESHOLD3_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[4]) && + (rssi >= sq_thresh->upper_threshold[3])) + { + newThreshold = WMI_RSSI_THRESHOLD4_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[5]) && + (rssi >= sq_thresh->upper_threshold[4])) + { + newThreshold = WMI_RSSI_THRESHOLD5_ABOVE; + } else if (rssi >= sq_thresh->upper_threshold[5]) { + newThreshold = WMI_RSSI_THRESHOLD6_ABOVE; + } + } else { + /* Lower threshold breached */ + if (rssi > sq_thresh->lower_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious lower RSSI threshold event: " + "%d %d\n", DBGARG, rssi, sq_thresh->lower_threshold[0])); + } else if ((rssi > sq_thresh->lower_threshold[1]) && + (rssi <= sq_thresh->lower_threshold[0])) + { + newThreshold = WMI_RSSI_THRESHOLD6_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[2]) && + (rssi <= sq_thresh->lower_threshold[1])) + { + newThreshold = WMI_RSSI_THRESHOLD5_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[3]) && + (rssi <= sq_thresh->lower_threshold[2])) + { + newThreshold = WMI_RSSI_THRESHOLD4_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[4]) && + (rssi <= sq_thresh->lower_threshold[3])) + { + newThreshold = WMI_RSSI_THRESHOLD3_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[5]) && + (rssi <= sq_thresh->lower_threshold[4])) + { + newThreshold = WMI_RSSI_THRESHOLD2_BELOW; + } else if (rssi <= sq_thresh->lower_threshold[5]) { + newThreshold = WMI_RSSI_THRESHOLD1_BELOW; + } + } + /* Calculate and install the next set of thresholds */ + lower_rssi_threshold = ar6000_get_lower_threshold(rssi, sq_thresh, + sq_thresh->lower_threshold_valid_count); + upper_rssi_threshold = ar6000_get_upper_threshold(rssi, sq_thresh, + sq_thresh->upper_threshold_valid_count); + /* Issue a wmi command to install the thresholds */ + cmd.thresholdAbove1_Val = upper_rssi_threshold; + cmd.thresholdBelow1_Val = lower_rssi_threshold; + cmd.weight = sq_thresh->weight; + cmd.pollTime = sq_thresh->polling_interval; + + rssi_event_value = rssi; + + if (wmi_send_rssi_threshold_params(wmip, &cmd) != A_OK) { + A_DPRINTF(DBG_WMI, (DBGFMT "Unable to configure the RSSI thresholds\n", + DBGARG)); + } + + A_WMI_RSSI_THRESHOLD_EVENT(wmip->wmi_devt, newThreshold, reply->rssi); + + return A_OK; +} + + +static A_STATUS +wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TARGET_ERROR_REPORT_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TARGET_ERROR_REPORT_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_REPORT_ERROR_EVENT(wmip->wmi_devt, (WMI_TARGET_ERROR_VAL) reply->errorVal); + + return A_OK; +} + +static A_STATUS +wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CAC_EVENT *reply; + WMM_TSPEC_IE *tspec_ie; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_CAC_EVENT *)datap; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + if ((reply->cac_indication == CAC_INDICATION_ADMISSION_RESP) && + (reply->statusCode != TSPEC_STATUS_CODE_ADMISSION_ACCEPTED)) { + tspec_ie = (WMM_TSPEC_IE *) &(reply->tspecSuggestion); + + wmi_delete_pstream_cmd(wmip, reply->ac, + (tspec_ie->tsInfo_info >> TSPEC_TSID_S) & TSPEC_TSID_MASK); + } + else if (reply->cac_indication == CAC_INDICATION_NO_RESP) { + A_UINT16 activeTsids; + A_UINT8 i; + + /* following assumes that there is only one outstanding ADDTS request + when this event is received */ + LOCK_WMI(wmip); + activeTsids = wmip->wmi_streamExistsForAC[reply->ac]; + UNLOCK_WMI(wmip); + + for (i = 0; i < sizeof(activeTsids) * 8; i++) { + if ((activeTsids >> i) & 1) { + break; + } + } + if (i < (sizeof(activeTsids) * 8)) { + wmi_delete_pstream_cmd(wmip, reply->ac, i); + } + } + + A_WMI_CAC_EVENT(wmip->wmi_devt, reply->ac, + reply->cac_indication, reply->statusCode, + reply->tspecSuggestion); + + return A_OK; +} + +static A_STATUS +wmi_channel_change_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CHANNEL_CHANGE_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_CHANNEL_CHANGE_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_CHANNEL_CHANGE_EVENT(wmip->wmi_devt, reply->oldChannel, + reply->newChannel); + + return A_OK; +} + +static A_STATUS +wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_HB_CHALLENGE_RESP_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMIX_HB_CHALLENGE_RESP_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "wmi: challenge response event\n", DBGARG)); + + A_WMI_HBCHALLENGERESP_EVENT(wmip->wmi_devt, reply->cookie, reply->source); + + return A_OK; +} + +static A_STATUS +wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TARGET_ROAM_TBL *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TARGET_ROAM_TBL *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_ROAM_TABLE_EVENT(wmip->wmi_devt, reply); + + return A_OK; +} + +static A_STATUS +wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TARGET_ROAM_DATA *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TARGET_ROAM_DATA *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_ROAM_DATA_EVENT(wmip->wmi_devt, reply); + + return A_OK; +} + +static A_STATUS +wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + if (len < sizeof(WMI_TX_RETRY_ERR_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TX_RETRY_ERR_EVENT(wmip->wmi_devt); + + return A_OK; +} + +static A_STATUS +wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_SNR_THRESHOLD_EVENT *reply; + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_SNR]; + WMI_SNR_THRESHOLD_VAL newThreshold; + WMI_SNR_THRESHOLD_PARAMS_CMD cmd; + A_UINT8 upper_snr_threshold, lower_snr_threshold; + A_INT16 snr; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_SNR_THRESHOLD_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + newThreshold = (WMI_SNR_THRESHOLD_VAL) reply->range; + snr = reply->snr; + /* + * Identify the threshold breached and communicate that to the app. After + * that install a new set of thresholds based on the signal quality + * reported by the target + */ + if (newThreshold) { + /* Upper threshold breached */ + if (snr < sq_thresh->upper_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious upper SNR threshold event: " + "%d\n", DBGARG, snr)); + } else if ((snr < sq_thresh->upper_threshold[1]) && + (snr >= sq_thresh->upper_threshold[0])) + { + newThreshold = WMI_SNR_THRESHOLD1_ABOVE; + } else if ((snr < sq_thresh->upper_threshold[2]) && + (snr >= sq_thresh->upper_threshold[1])) + { + newThreshold = WMI_SNR_THRESHOLD2_ABOVE; + } else if ((snr < sq_thresh->upper_threshold[3]) && + (snr >= sq_thresh->upper_threshold[2])) + { + newThreshold = WMI_SNR_THRESHOLD3_ABOVE; + } else if (snr >= sq_thresh->upper_threshold[3]) { + newThreshold = WMI_SNR_THRESHOLD4_ABOVE; + } + } else { + /* Lower threshold breached */ + if (snr > sq_thresh->lower_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious lower SNR threshold event: " + "%d %d\n", DBGARG, snr, sq_thresh->lower_threshold[0])); + } else if ((snr > sq_thresh->lower_threshold[1]) && + (snr <= sq_thresh->lower_threshold[0])) + { + newThreshold = WMI_SNR_THRESHOLD4_BELOW; + } else if ((snr > sq_thresh->lower_threshold[2]) && + (snr <= sq_thresh->lower_threshold[1])) + { + newThreshold = WMI_SNR_THRESHOLD3_BELOW; + } else if ((snr > sq_thresh->lower_threshold[3]) && + (snr <= sq_thresh->lower_threshold[2])) + { + newThreshold = WMI_SNR_THRESHOLD2_BELOW; + } else if (snr <= sq_thresh->lower_threshold[3]) { + newThreshold = WMI_SNR_THRESHOLD1_BELOW; + } + } + + /* Calculate and install the next set of thresholds */ + lower_snr_threshold = ar6000_get_lower_threshold(snr, sq_thresh, + sq_thresh->lower_threshold_valid_count); + upper_snr_threshold = ar6000_get_upper_threshold(snr, sq_thresh, + sq_thresh->upper_threshold_valid_count); + + /* Issue a wmi command to install the thresholds */ + cmd.thresholdAbove1_Val = upper_snr_threshold; + cmd.thresholdBelow1_Val = lower_snr_threshold; + cmd.weight = sq_thresh->weight; + cmd.pollTime = sq_thresh->polling_interval; + + A_DPRINTF(DBG_WMI, (DBGFMT "snr: %d, threshold: %d, lower: %d, upper: %d\n" + ,DBGARG, snr, newThreshold, lower_snr_threshold, + upper_snr_threshold)); + + snr_event_value = snr; + + if (wmi_send_snr_threshold_params(wmip, &cmd) != A_OK) { + A_DPRINTF(DBG_WMI, (DBGFMT "Unable to configure the SNR thresholds\n", + DBGARG)); + } + A_WMI_SNR_THRESHOLD_EVENT_RX(wmip->wmi_devt, newThreshold, reply->snr); + + return A_OK; +} + +static A_STATUS +wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_LQ_THRESHOLD_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_LQ_THRESHOLD_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_LQ_THRESHOLD_EVENT_RX(wmip->wmi_devt, + (WMI_LQ_THRESHOLD_VAL) reply->range, + reply->lq); + + return A_OK; +} + +static A_STATUS +wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + A_UINT16 ap_info_entry_size; + WMI_APLIST_EVENT *ev = (WMI_APLIST_EVENT *)datap; + WMI_AP_INFO_V1 *ap_info_v1; + A_UINT8 i; + + if (len < sizeof(WMI_APLIST_EVENT)) { + return A_EINVAL; + } + + if (ev->apListVer == APLIST_VER1) { + ap_info_entry_size = sizeof(WMI_AP_INFO_V1); + ap_info_v1 = (WMI_AP_INFO_V1 *)ev->apList; + } else { + return A_EINVAL; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Number of APs in APLIST Event is %d\n", ev->numAP)); + if (len < (int)(sizeof(WMI_APLIST_EVENT) + + (ev->numAP - 1) * ap_info_entry_size)) + { + return A_EINVAL; + } + + /* + * AP List Ver1 Contents + */ + for (i = 0; i < ev->numAP; i++) { + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("AP#%d BSSID %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x "\ + "Channel %d\n", i, + ap_info_v1->bssid[0], ap_info_v1->bssid[1], + ap_info_v1->bssid[2], ap_info_v1->bssid[3], + ap_info_v1->bssid[4], ap_info_v1->bssid[5], + ap_info_v1->channel)); + ap_info_v1++; + } + return A_OK; +} + +static A_STATUS +wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + A_UINT32 dropped; + + dropped = *((A_UINT32 *)datap); + datap += sizeof(dropped); + len -= sizeof(dropped); + A_WMI_DBGLOG_EVENT(wmip->wmi_devt, dropped, datap, len); + return A_OK; +} + +#ifdef CONFIG_HOST_GPIO_SUPPORT +static A_STATUS +wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_GPIO_INTR_EVENT *gpio_intr = (WMIX_GPIO_INTR_EVENT *)datap; + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - intrmask=0x%x input=0x%x.\n", DBGARG, + gpio_intr->intr_mask, gpio_intr->input_values)); + + A_WMI_GPIO_INTR_RX(gpio_intr->intr_mask, gpio_intr->input_values); + + return A_OK; +} + +static A_STATUS +wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_GPIO_DATA_EVENT *gpio_data = (WMIX_GPIO_DATA_EVENT *)datap; + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG, + gpio_data->reg_id, gpio_data->value)); + + A_WMI_GPIO_DATA_RX(gpio_data->reg_id, gpio_data->value); + + return A_OK; +} + +static A_STATUS +wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_GPIO_ACK_RX(); + + return A_OK; +} +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +/* + * Called to send a wmi command. Command specific data is already built + * on osbuf and current osbuf->data points to it. + */ +A_STATUS +wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId, + WMI_SYNC_FLAG syncflag) +{ +#define IS_OPT_TX_CMD(cmdId) ((cmdId == WMI_OPT_TX_FRAME_CMDID)) + WMI_CMD_HDR *cHdr; + HTC_ENDPOINT_ID eid = wmip->wmi_endpoint_id; + + A_ASSERT(osbuf != NULL); + + if (syncflag >= END_WMIFLAG) { + return A_EINVAL; + } + + if ((syncflag == SYNC_BEFORE_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) { + /* + * We want to make sure all data currently queued is transmitted before + * the cmd execution. Establish a new sync point. + */ + wmi_sync_point(wmip); + } + + if (A_NETBUF_PUSH(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + cHdr = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf); + cHdr->commandId = (A_UINT16) cmdId; + + /* + * Only for OPT_TX_CMD, use BE endpoint. + */ + if (IS_OPT_TX_CMD(cmdId)) { + wmi_data_hdr_add(wmip, osbuf, OPT_MSGTYPE, FALSE); + eid = A_WMI_Ac2EndpointID(wmip->wmi_devt, WMM_AC_BE); + } + A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, eid); + + if ((syncflag == SYNC_AFTER_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) { + /* + * We want to make sure all new data queued waits for the command to + * execute. Establish a new sync point. + */ + wmi_sync_point(wmip); + } + return (A_OK); +#undef IS_OPT_TX_CMD +} + +A_STATUS +wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMIX_COMMAND_ID cmdId, + WMI_SYNC_FLAG syncflag) +{ + WMIX_CMD_HDR *cHdr; + + if (A_NETBUF_PUSH(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + cHdr = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf); + cHdr->commandId = (A_UINT32) cmdId; + + return wmi_cmd_send(wmip, osbuf, WMI_EXTENSION_CMDID, syncflag); +} + +A_STATUS +wmi_connect_cmd(struct wmi_t *wmip, NETWORK_TYPE netType, + DOT11_AUTH_MODE dot11AuthMode, AUTH_MODE authMode, + CRYPTO_TYPE pairwiseCrypto, A_UINT8 pairwiseCryptoLen, + CRYPTO_TYPE groupCrypto, A_UINT8 groupCryptoLen, + int ssidLength, A_UCHAR *ssid, + A_UINT8 *bssid, A_UINT16 channel, A_UINT32 ctrl_flags) +{ + void *osbuf; + WMI_CONNECT_CMD *cc; + + if ((pairwiseCrypto == NONE_CRYPT) && (groupCrypto != NONE_CRYPT)) { + return A_EINVAL; + } + if ((pairwiseCrypto != NONE_CRYPT) && (groupCrypto == NONE_CRYPT)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_CONNECT_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_CONNECT_CMD)); + + cc = (WMI_CONNECT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cc, sizeof(*cc)); + + if (ssidLength) + { + A_MEMCPY(cc->ssid, ssid, ssidLength); + } + + cc->ssidLength = ssidLength; + cc->networkType = netType; + cc->dot11AuthMode = dot11AuthMode; + cc->authMode = authMode; + cc->pairwiseCryptoType = pairwiseCrypto; + cc->pairwiseCryptoLen = pairwiseCryptoLen; + cc->groupCryptoType = groupCrypto; + cc->groupCryptoLen = groupCryptoLen; + cc->channel = channel; + cc->ctrl_flags = ctrl_flags; + + if (bssid != NULL) { + A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN); + } + if (wmi_set_keepalive_cmd(wmip, wmip->wmi_keepaliveInterval) != A_OK) { + return(A_ERROR); + } + + wmip->wmi_pair_crypto_type = pairwiseCrypto; + wmip->wmi_grp_crypto_type = groupCrypto; + + return (wmi_cmd_send(wmip, osbuf, WMI_CONNECT_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_reconnect_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT16 channel) +{ + void *osbuf; + WMI_RECONNECT_CMD *cc; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_RECONNECT_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_RECONNECT_CMD)); + + cc = (WMI_RECONNECT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cc, sizeof(*cc)); + + cc->channel = channel; + + if (bssid != NULL) { + A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_RECONNECT_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_disconnect_cmd(struct wmi_t *wmip) +{ + A_STATUS status; + + /* Bug fix for 24817(elevator bug) - the disconnect command does not + need to do a SYNC before.*/ + status = wmi_simple_cmd(wmip, WMI_DISCONNECT_CMDID); + + return status; +} + +A_STATUS +wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType, + A_BOOL forceFgScan, A_BOOL isLegacy, + A_UINT32 homeDwellTime, A_UINT32 forceScanInterval, + A_INT8 numChan, A_UINT16 *channelList) +{ + void *osbuf; + WMI_START_SCAN_CMD *sc; + A_INT8 size; + + size = sizeof (*sc); + + if ((scanType != WMI_LONG_SCAN) && (scanType != WMI_SHORT_SCAN)) { + return A_EINVAL; + } + + if (numChan) { + if (numChan > WMI_MAX_CHANNELS) { + return A_EINVAL; + } + size += sizeof(A_UINT16) * (numChan - 1); + } + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + sc = (WMI_START_SCAN_CMD *)(A_NETBUF_DATA(osbuf)); + sc->scanType = scanType; + sc->forceFgScan = forceFgScan; + sc->isLegacy = isLegacy; + sc->homeDwellTime = homeDwellTime; + sc->forceScanInterval = forceScanInterval; + sc->numChannels = numChan; + if (numChan) { + A_MEMCPY(sc->channelList, channelList, numChan * sizeof(A_UINT16)); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_START_SCAN_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec, + A_UINT16 fg_end_sec, A_UINT16 bg_sec, + A_UINT16 minact_chdw_msec, A_UINT16 maxact_chdw_msec, + A_UINT16 pas_chdw_msec, + A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags, + A_UINT32 max_dfsch_act_time, A_UINT16 maxact_scan_per_ssid) +{ + void *osbuf; + WMI_SCAN_PARAMS_CMD *sc; + + osbuf = A_NETBUF_ALLOC(sizeof(*sc)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*sc)); + + sc = (WMI_SCAN_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(sc, sizeof(*sc)); + sc->fg_start_period = fg_start_sec; + sc->fg_end_period = fg_end_sec; + sc->bg_period = bg_sec; + sc->minact_chdwell_time = minact_chdw_msec; + sc->maxact_chdwell_time = maxact_chdw_msec; + sc->pas_chdwell_time = pas_chdw_msec; + sc->shortScanRatio = shScanRatio; + sc->scanCtrlFlags = scanCtrlFlags; + sc->max_dfsch_act_time = max_dfsch_act_time; + sc->maxact_scan_per_ssid = maxact_scan_per_ssid; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_SCAN_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask) +{ + void *osbuf; + WMI_BSS_FILTER_CMD *cmd; + + if (filter >= LAST_BSS_FILTER) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_BSS_FILTER_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->bssFilter = filter; + cmd->ieMask = ieMask; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BSS_FILTER_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag, + A_UINT8 ssidLength, A_UCHAR *ssid) +{ + void *osbuf; + WMI_PROBED_SSID_CMD *cmd; + + if (index > MAX_PROBED_SSID_INDEX) { + return A_EINVAL; + } + if (ssidLength > sizeof(cmd->ssid)) { + return A_EINVAL; + } + if ((flag & (DISABLE_SSID_FLAG | ANY_SSID_FLAG)) && (ssidLength > 0)) { + return A_EINVAL; + } + if ((flag & SPECIFIC_SSID_FLAG) && !ssidLength) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_PROBED_SSID_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->entryIndex = index; + cmd->flag = flag; + cmd->ssidLength = ssidLength; + A_MEMCPY(cmd->ssid, ssid, ssidLength); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PROBED_SSID_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons) +{ + void *osbuf; + WMI_LISTEN_INT_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_LISTEN_INT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->listenInterval = listenInterval; + cmd->numBeacons = listenBeacons; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_LISTEN_INT_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmissTime, A_UINT16 bmissBeacons) +{ + void *osbuf; + WMI_BMISS_TIME_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_BMISS_TIME_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->bmissTime = bmissTime; + cmd->numBeacons = bmissBeacons; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BMISS_TIME_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType, + A_UINT8 ieLen, A_UINT8 *ieInfo) +{ + void *osbuf; + WMI_SET_ASSOC_INFO_CMD *cmd; + A_UINT16 cmdLen; + + cmdLen = sizeof(*cmd) + ieLen - 1; + osbuf = A_NETBUF_ALLOC(cmdLen); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, cmdLen); + + cmd = (WMI_SET_ASSOC_INFO_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + cmd->ieType = ieType; + cmd->bufferSize = ieLen; + A_MEMCPY(cmd->assocInfo, ieInfo, ieLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_ASSOC_INFO_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode) +{ + void *osbuf; + WMI_POWER_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_POWER_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->powerMode = powerMode; + wmip->wmi_powerMode = powerMode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl, + A_UINT16 atim_windows, A_UINT16 timeout_value) +{ + void *osbuf; + WMI_IBSS_PM_CAPS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_IBSS_PM_CAPS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->power_saving = pmEnable; + cmd->ttl = ttl; + cmd->atim_windows = atim_windows; + cmd->timeout_value = timeout_value; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_IBSS_PM_CAPS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod, + A_UINT16 psPollNum, A_UINT16 dtimPolicy) +{ + void *osbuf; + WMI_POWER_PARAMS_CMD *pm; + + osbuf = A_NETBUF_ALLOC(sizeof(*pm)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*pm)); + + pm = (WMI_POWER_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(pm, sizeof(*pm)); + pm->idle_period = idlePeriod; + pm->pspoll_number = psPollNum; + pm->dtim_policy = dtimPolicy; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout) +{ + void *osbuf; + WMI_DISC_TIMEOUT_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DISC_TIMEOUT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->disconnectTimeout = timeout; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_DISC_TIMEOUT_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex, CRYPTO_TYPE keyType, + A_UINT8 keyUsage, A_UINT8 keyLength, A_UINT8 *keyRSC, + A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl, A_UINT8 *macAddr, + WMI_SYNC_FLAG sync_flag) +{ + void *osbuf; + WMI_ADD_CIPHER_KEY_CMD *cmd; + + if ((keyIndex > WMI_MAX_KEY_INDEX) || (keyLength > WMI_MAX_KEY_LEN) || + (keyMaterial == NULL)) + { + return A_EINVAL; + } + + if ((WEP_CRYPT != keyType) && (NULL == keyRSC)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_ADD_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->keyIndex = keyIndex; + cmd->keyType = keyType; + cmd->keyUsage = keyUsage; + cmd->keyLength = keyLength; + A_MEMCPY(cmd->key, keyMaterial, keyLength); +#ifdef WAPI_ENABLE + if (NULL != keyRSC && key_op_ctrl != KEY_OP_INIT_WAPIPN) { +#else + if (NULL != keyRSC) { +#endif // WAPI_ENABLE + A_MEMCPY(cmd->keyRSC, keyRSC, sizeof(cmd->keyRSC)); + } + cmd->key_op_ctrl = key_op_ctrl; + + if(macAddr) { + A_MEMCPY(cmd->key_macaddr,macAddr,IEEE80211_ADDR_LEN); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_CIPHER_KEY_CMDID, sync_flag)); +} + +A_STATUS +wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk) +{ + void *osbuf; + WMI_ADD_KRK_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_ADD_KRK_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + A_MEMCPY(cmd->krk, krk, WMI_KRK_LEN); + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_KRK_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_delete_krk_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_DELETE_KRK_CMDID); +} + +A_STATUS +wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex) +{ + void *osbuf; + WMI_DELETE_CIPHER_KEY_CMD *cmd; + + if (keyIndex > WMI_MAX_KEY_INDEX) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DELETE_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->keyIndex = keyIndex; + + return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_CIPHER_KEY_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId, + A_BOOL set) +{ + void *osbuf; + WMI_SET_PMKID_CMD *cmd; + + if (bssid == NULL) { + return A_EINVAL; + } + + if ((set == TRUE) && (pmkId == NULL)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_PMKID_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid)); + if (set == TRUE) { + A_MEMCPY(cmd->pmkid, pmkId, sizeof(cmd->pmkid)); + cmd->enable = PMKID_ENABLE; + } else { + A_MEMZERO(cmd->pmkid, sizeof(cmd->pmkid)); + cmd->enable = PMKID_DISABLE; + } + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en) +{ + void *osbuf; + WMI_SET_TKIP_COUNTERMEASURES_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_TKIP_COUNTERMEASURES_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->cm_en = (en == TRUE)? WMI_TKIP_CM_ENABLE : WMI_TKIP_CM_DISABLE; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_TKIP_COUNTERMEASURES_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_akmp_params_cmd(struct wmi_t *wmip, + WMI_SET_AKMP_PARAMS_CMD *akmpParams) +{ + void *osbuf; + WMI_SET_AKMP_PARAMS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + cmd = (WMI_SET_AKMP_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->akmpInfo = akmpParams->akmpInfo; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_AKMP_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_pmkid_list_cmd(struct wmi_t *wmip, + WMI_SET_PMKID_LIST_CMD *pmkInfo) +{ + void *osbuf; + WMI_SET_PMKID_LIST_CMD *cmd; + A_UINT16 cmdLen; + A_UINT8 i; + + cmdLen = sizeof(pmkInfo->numPMKID) + + pmkInfo->numPMKID * sizeof(WMI_PMKID); + + osbuf = A_NETBUF_ALLOC(cmdLen); + + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, cmdLen); + cmd = (WMI_SET_PMKID_LIST_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->numPMKID = pmkInfo->numPMKID; + + for (i = 0; i < cmd->numPMKID; i++) { + A_MEMCPY(&cmd->pmkidList[i], &pmkInfo->pmkidList[i], + WMI_PMKID_LEN); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_LIST_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_pmkid_list_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_PMKID_LIST_CMDID); +} + +A_STATUS +wmi_dataSync_send(struct wmi_t *wmip, void *osbuf, HTC_ENDPOINT_ID eid) +{ + WMI_DATA_HDR *dtHdr; + + A_ASSERT( eid != wmip->wmi_endpoint_id); + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf); + dtHdr->info = + (SYNC_MSGTYPE & WMI_DATA_HDR_MSG_TYPE_MASK) << WMI_DATA_HDR_MSG_TYPE_SHIFT; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter - eid %d\n", DBGARG, eid)); + + return (A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, eid)); +} + +typedef struct _WMI_DATA_SYNC_BUFS { + A_UINT8 trafficClass; + void *osbuf; +}WMI_DATA_SYNC_BUFS; + +static A_STATUS +wmi_sync_point(struct wmi_t *wmip) +{ + void *cmd_osbuf; + WMI_SYNC_CMD *cmd; + WMI_DATA_SYNC_BUFS dataSyncBufs[WMM_NUM_AC]; + A_UINT8 i,numPriStreams=0; + A_STATUS status = A_OK; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + memset(dataSyncBufs,0,sizeof(dataSyncBufs)); + + /* lock out while we walk through the priority list and assemble our local array */ + LOCK_WMI(wmip); + + for (i=0; i < WMM_NUM_AC ; i++) { + if (wmip->wmi_fatPipeExists & (1 << i)) { + numPriStreams++; + dataSyncBufs[numPriStreams-1].trafficClass = i; + } + } + + UNLOCK_WMI(wmip); + + /* dataSyncBufs is now filled with entries (starting at index 0) containing valid streamIDs */ + + do { + /* + * We allocate all network buffers needed so we will be able to + * send all required frames. + */ + cmd_osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (cmd_osbuf == NULL) { + status = A_NO_MEMORY; + break; + } + + A_NETBUF_PUT(cmd_osbuf, sizeof(*cmd)); + + cmd = (WMI_SYNC_CMD *)(A_NETBUF_DATA(cmd_osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + /* In the SYNC cmd sent on the control Ep, send a bitmap of the data + * eps on which the Data Sync will be sent + */ + cmd->dataSyncMap = wmip->wmi_fatPipeExists; + + for (i=0; i < numPriStreams ; i++) { + dataSyncBufs[i].osbuf = A_NETBUF_ALLOC(0); + if (dataSyncBufs[i].osbuf == NULL) { + status = A_NO_MEMORY; + break; + } + } //end for + + /* if Buffer allocation for any of the dataSync fails, then do not + * send the Synchronize cmd on the control ep + */ + if (A_FAILED(status)) { + break; + } + + /* + * Send sync cmd followed by sync data messages on all endpoints being + * used + */ + status = wmi_cmd_send(wmip, cmd_osbuf, WMI_SYNCHRONIZE_CMDID, + NO_SYNC_WMIFLAG); + + if (A_FAILED(status)) { + break; + } + /* cmd buffer sent, we no longer own it */ + cmd_osbuf = NULL; + + for(i=0; i < numPriStreams; i++) { + A_ASSERT(dataSyncBufs[i].osbuf != NULL); + status = wmi_dataSync_send(wmip, + dataSyncBufs[i].osbuf, + A_WMI_Ac2EndpointID(wmip->wmi_devt, + dataSyncBufs[i]. + trafficClass) + ); + + if (A_FAILED(status)) { + break; + } + /* we don't own this buffer anymore, NULL it out of the array so it + * won't get cleaned up */ + dataSyncBufs[i].osbuf = NULL; + } //end for + + } while(FALSE); + + /* free up any resources left over (possibly due to an error) */ + + if (cmd_osbuf != NULL) { + A_NETBUF_FREE(cmd_osbuf); + } + + for (i = 0; i < numPriStreams; i++) { + if (dataSyncBufs[i].osbuf != NULL) { + A_NETBUF_FREE(dataSyncBufs[i].osbuf); + } + } + + return (status); +} + +A_STATUS +wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *params) +{ + void *osbuf; + WMI_CREATE_PSTREAM_CMD *cmd; + A_UINT8 fatPipeExistsForAC=0; + A_INT32 minimalPHY = 0; + A_INT32 nominalPHY = 0; + + /* Validate all the parameters. */ + if( !((params->userPriority < 8) && + (params->userPriority <= 0x7) && + (convert_userPriority_to_trafficClass(params->userPriority) == params->trafficClass) && + (params->trafficDirection == UPLINK_TRAFFIC || + params->trafficDirection == DNLINK_TRAFFIC || + params->trafficDirection == BIDIR_TRAFFIC) && + (params->trafficType == TRAFFIC_TYPE_APERIODIC || + params->trafficType == TRAFFIC_TYPE_PERIODIC ) && + (params->voicePSCapability == DISABLE_FOR_THIS_AC || + params->voicePSCapability == ENABLE_FOR_THIS_AC || + params->voicePSCapability == ENABLE_FOR_ALL_AC) && + (params->tsid == WMI_IMPLICIT_PSTREAM || params->tsid <= WMI_MAX_THINSTREAM)) ) + { + return A_EINVAL; + } + + // + // check nominal PHY rate is >= minimalPHY, so that DUT + // can allow TSRS IE + // + + // get the physical rate + minimalPHY = ((params->minPhyRate / 1000)/1000); // unit of bps + + // check minimal phy < nominal phy rate + // + if (params->nominalPHY >= minimalPHY) + { + nominalPHY = (params->nominalPHY * 1000)/500; // unit of 500 kbps + A_DPRINTF(DBG_WMI, + (DBGFMT "TSRS IE Enabled::MinPhy %x->NominalPhy ===> %x\n", DBGARG, + minimalPHY, nominalPHY)); + + params->nominalPHY = nominalPHY; + } + else + { + params->nominalPHY = 0; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + A_DPRINTF(DBG_WMI, + (DBGFMT "Sending create_pstream_cmd: ac=%d tsid:%d\n", DBGARG, + params->trafficClass, params->tsid)); + + cmd = (WMI_CREATE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + A_MEMCPY(cmd, params, sizeof(*cmd)); + + /* this is an implicitly created Fat pipe */ + if (params->tsid == WMI_IMPLICIT_PSTREAM) { + LOCK_WMI(wmip); + fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass)); + wmip->wmi_fatPipeExists |= (1<trafficClass); + UNLOCK_WMI(wmip); + } else { + /* this is an explicitly created thin stream within a fat pipe */ + LOCK_WMI(wmip); + fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass)); + wmip->wmi_streamExistsForAC[params->trafficClass] |= (1<tsid); + /* if a thinstream becomes active, the fat pipe automatically + * becomes active + */ + wmip->wmi_fatPipeExists |= (1<trafficClass); + UNLOCK_WMI(wmip); + } + + /* Indicate activty change to driver layer only if this is the + * first TSID to get created in this AC explicitly or an implicit + * fat pipe is getting created. + */ + if (!fatPipeExistsForAC) { + A_WMI_STREAM_TX_ACTIVE(wmip->wmi_devt, params->trafficClass); + } + + /* mike: should be SYNC_BEFORE_WMIFLAG */ + return (wmi_cmd_send(wmip, osbuf, WMI_CREATE_PSTREAM_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 tsid) +{ + void *osbuf; + WMI_DELETE_PSTREAM_CMD *cmd; + A_STATUS status; + A_UINT16 activeTsids=0; + + /* validate the parameters */ + if (trafficClass > 3) { + A_DPRINTF(DBG_WMI, (DBGFMT "Invalid trafficClass: %d\n", DBGARG, trafficClass)); + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DELETE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->trafficClass = trafficClass; + cmd->tsid = tsid; + + LOCK_WMI(wmip); + activeTsids = wmip->wmi_streamExistsForAC[trafficClass]; + UNLOCK_WMI(wmip); + + /* Check if the tsid was created & exists */ + if (!(activeTsids & (1<wmi_streamExistsForAC[trafficClass] &= ~(1<wmi_streamExistsForAC[trafficClass]; + UNLOCK_WMI(wmip); + + + /* Indicate stream inactivity to driver layer only if all tsids + * within this AC are deleted. + */ + if(!activeTsids) { + A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, trafficClass); + wmip->wmi_fatPipeExists &= ~(1< 15)){ + + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_FRAME_RATES_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + frameType = (A_UINT8)((subType << 4) | type); + + cmd->bEnableMask = bEnable; + cmd->frameType = frameType; + cmd->frameRateMask = rateMask; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_FRAMERATES_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * used to set the bit rate. rate is in Kbps. If rate == -1 + * then auto selection is used. + */ +A_STATUS +wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 dataRate, A_INT32 mgmtRate, A_INT32 ctlRate) +{ + void *osbuf; + WMI_BIT_RATE_CMD *cmd; + A_INT8 drix, mrix, crix; + + if (dataRate != -1) { + drix = wmi_validate_bitrate(wmip, dataRate); + if(drix == A_EINVAL){ + return A_EINVAL; + } + } else { + drix = (A_INT8) -1; + } + + if (mgmtRate != -1) { + mrix = wmi_validate_bitrate(wmip, mgmtRate); + if(mrix == A_EINVAL){ + return A_EINVAL; + } + } else { + mrix = (A_INT8) -1; + } + if (ctlRate != -1) { + crix = wmi_validate_bitrate(wmip, ctlRate); + if(crix == A_EINVAL){ + return A_EINVAL; + } + } else { + crix = (A_INT8) -1; + } + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_BIT_RATE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->rateIndex = drix; + cmd->mgmtRateIndex = mrix; + cmd->ctlRateIndex = crix; + + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BITRATE_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_bitrate_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_BITRATE_CMDID); +} + +/* + * Returns TRUE iff the given rate index is legal in the current PHY mode. + */ +A_BOOL +wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_INT32 rateIndex) +{ + WMI_PHY_MODE phyMode = (WMI_PHY_MODE) wmip->wmi_phyMode; + A_BOOL isValid = TRUE; + switch(phyMode) { + case WMI_11A_MODE: + if ((rateIndex < MODE_A_SUPPORT_RATE_START) || (rateIndex > MODE_A_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + + case WMI_11B_MODE: + if ((rateIndex < MODE_B_SUPPORT_RATE_START) || (rateIndex > MODE_B_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + + case WMI_11GONLY_MODE: + if ((rateIndex < MODE_GONLY_SUPPORT_RATE_START) || (rateIndex > MODE_GONLY_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + + case WMI_11G_MODE: + case WMI_11AG_MODE: + if ((rateIndex < MODE_G_SUPPORT_RATE_START) || (rateIndex > MODE_G_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + + default: + A_ASSERT(FALSE); + break; + } + + return isValid; +} + +A_INT8 +wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate) +{ + A_INT8 i; + if (rate != -1) + { + for (i=0;;i++) + { + if (wmi_rateTable[(A_UINT32) i] == 0) { + return A_EINVAL; + } + if (wmi_rateTable[(A_UINT32) i] == rate) { + break; + } + } + } + else{ + i = -1; + } + + if(wmi_is_bitrate_index_valid(wmip, (A_INT32) i) != TRUE) { + return A_EINVAL; + } + + return i; +} + +A_STATUS +wmi_set_fixrates_cmd(struct wmi_t *wmip, A_INT16 fixRatesMask) +{ + void *osbuf; + WMI_FIX_RATES_CMD *cmd; + A_INT32 rateIndex; + + /* Make sure all rates in the mask are valid in the current PHY mode */ + for(rateIndex = 0; rateIndex < MAX_NUMBER_OF_SUPPORT_RATES; rateIndex++) { + if((1 << rateIndex) & (A_UINT32)fixRatesMask) { + if(wmi_is_bitrate_index_valid(wmip, rateIndex) != TRUE) { + A_DPRINTF(DBG_WMI, (DBGFMT "Set Fix Rates command failed: Given rate is illegal in current PHY mode\n", DBGARG)); + return A_EINVAL; + } + } + } + + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_FIX_RATES_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->fixRateMask = fixRatesMask; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_FIXRATES_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_ratemask_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_FIXRATES_CMDID); +} + +A_STATUS +wmi_get_channelList_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_CHANNEL_LIST_CMDID); +} + +/* + * used to generate a wmi sey channel Parameters cmd. + * mode should always be specified and corresponds to the phy mode of the + * wlan. + * numChan should alway sbe specified. If zero indicates that all available + * channels should be used. + * channelList is an array of channel frequencies (in Mhz) which the radio + * should limit its operation to. It should be NULL if numChan == 0. Size of + * array should correspond to numChan entries. + */ +A_STATUS +wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam, + WMI_PHY_MODE mode, A_INT8 numChan, + A_UINT16 *channelList) +{ + void *osbuf; + WMI_CHANNEL_PARAMS_CMD *cmd; + A_INT8 size; + + size = sizeof (*cmd); + + if (numChan) { + if (numChan > WMI_MAX_CHANNELS) { + return A_EINVAL; + } + size += sizeof(A_UINT16) * (numChan - 1); + } + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_CHANNEL_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + wmip->wmi_phyMode = mode; + cmd->scanParam = scanParam; + cmd->phyMode = mode; + cmd->numChannels = numChan; + A_MEMCPY(cmd->channelList, channelList, numChan * sizeof(A_UINT16)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_CHANNEL_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +void +wmi_cache_configure_rssithreshold(struct wmi_t *wmip, WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd) +{ + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_RSSI]; + /* + * Parse the command and store the threshold values here. The checks + * for valid values can be put here + */ + sq_thresh->weight = rssiCmd->weight; + sq_thresh->polling_interval = rssiCmd->pollTime; + + sq_thresh->upper_threshold[0] = rssiCmd->thresholdAbove1_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[1] = rssiCmd->thresholdAbove2_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[2] = rssiCmd->thresholdAbove3_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[3] = rssiCmd->thresholdAbove4_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[4] = rssiCmd->thresholdAbove5_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[5] = rssiCmd->thresholdAbove6_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold_valid_count = 6; + + /* List sorted in descending order */ + sq_thresh->lower_threshold[0] = rssiCmd->thresholdBelow6_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[1] = rssiCmd->thresholdBelow5_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[2] = rssiCmd->thresholdBelow4_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[3] = rssiCmd->thresholdBelow3_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[4] = rssiCmd->thresholdBelow2_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[5] = rssiCmd->thresholdBelow1_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold_valid_count = 6; + + if (!rssi_event_value) { + /* + * Configuring the thresholds to their extremes allows the host to get an + * event from the target which is used for the configuring the correct + * thresholds + */ + rssiCmd->thresholdAbove1_Val = sq_thresh->upper_threshold[0]; + rssiCmd->thresholdBelow1_Val = sq_thresh->lower_threshold[0]; + } else { + /* + * In case the user issues multiple times of rssi_threshold_setting, + * we should not use the extreames anymore, the target does not expect that. + */ + rssiCmd->thresholdAbove1_Val = ar6000_get_upper_threshold(rssi_event_value, sq_thresh, + sq_thresh->upper_threshold_valid_count); + rssiCmd->thresholdBelow1_Val = ar6000_get_lower_threshold(rssi_event_value, sq_thresh, + sq_thresh->lower_threshold_valid_count); + } +} + +A_STATUS +wmi_set_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd) +{ + + /* Check these values are in ascending order */ + if( rssiCmd->thresholdAbove6_Val <= rssiCmd->thresholdAbove5_Val || + rssiCmd->thresholdAbove5_Val <= rssiCmd->thresholdAbove4_Val || + rssiCmd->thresholdAbove4_Val <= rssiCmd->thresholdAbove3_Val || + rssiCmd->thresholdAbove3_Val <= rssiCmd->thresholdAbove2_Val || + rssiCmd->thresholdAbove2_Val <= rssiCmd->thresholdAbove1_Val || + rssiCmd->thresholdBelow6_Val <= rssiCmd->thresholdBelow5_Val || + rssiCmd->thresholdBelow5_Val <= rssiCmd->thresholdBelow4_Val || + rssiCmd->thresholdBelow4_Val <= rssiCmd->thresholdBelow3_Val || + rssiCmd->thresholdBelow3_Val <= rssiCmd->thresholdBelow2_Val || + rssiCmd->thresholdBelow2_Val <= rssiCmd->thresholdBelow1_Val) + { + return A_EINVAL; + } + + wmi_cache_configure_rssithreshold(wmip, rssiCmd); + + return (wmi_send_rssi_threshold_params(wmip, rssiCmd)); +} + +A_STATUS +wmi_set_ip_cmd(struct wmi_t *wmip, WMI_SET_IP_CMD *ipCmd) +{ + void *osbuf; + WMI_SET_IP_CMD *cmd; + + /* Multicast address are not valid */ + if((*((A_UINT8*)&ipCmd->ips[0]) >= 0xE0) || + (*((A_UINT8*)&ipCmd->ips[1]) >= 0xE0)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_SET_IP_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_SET_IP_CMD)); + cmd = (WMI_SET_IP_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMCPY(cmd, ipCmd, sizeof(WMI_SET_IP_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_IP_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip, + WMI_SET_HOST_SLEEP_MODE_CMD *hostModeCmd) +{ + void *osbuf; + A_INT8 size; + WMI_SET_HOST_SLEEP_MODE_CMD *cmd; + A_UINT16 activeTsids=0; + A_UINT8 streamExists=0; + A_UINT8 i; + + if( hostModeCmd->awake == hostModeCmd->asleep) { + return A_EINVAL; + } + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_SET_HOST_SLEEP_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, hostModeCmd, sizeof(WMI_SET_HOST_SLEEP_MODE_CMD)); + + if(hostModeCmd->asleep) { + /* + * Relinquish credits from all implicitly created pstreams since when we + * go to sleep. If user created explicit thinstreams exists with in a + * fatpipe leave them intact for the user to delete + */ + LOCK_WMI(wmip); + streamExists = wmip->wmi_fatPipeExists; + UNLOCK_WMI(wmip); + + for(i=0;i< WMM_NUM_AC;i++) { + if (streamExists & (1<wmi_streamExistsForAC[i]; + UNLOCK_WMI(wmip); + /* If there are no user created thin streams delete the fatpipe */ + if(!activeTsids) { + streamExists &= ~(1<wmi_devt,i); + } + } + } + + /* Update the fatpipes that exists*/ + LOCK_WMI(wmip); + wmip->wmi_fatPipeExists = streamExists; + UNLOCK_WMI(wmip); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_HOST_SLEEP_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_wow_mode_cmd(struct wmi_t *wmip, + WMI_SET_WOW_MODE_CMD *wowModeCmd) +{ + void *osbuf; + A_INT8 size; + WMI_SET_WOW_MODE_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_SET_WOW_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, wowModeCmd, sizeof(WMI_SET_WOW_MODE_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WOW_MODE_CMDID, + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_get_wow_list_cmd(struct wmi_t *wmip, + WMI_GET_WOW_LIST_CMD *wowListCmd) +{ + void *osbuf; + A_INT8 size; + WMI_GET_WOW_LIST_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_GET_WOW_LIST_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, wowListCmd, sizeof(WMI_GET_WOW_LIST_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_GET_WOW_LIST_CMDID, + NO_SYNC_WMIFLAG)); + +} + +static A_STATUS +wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_GET_WOW_LIST_REPLY *reply; + + if (len < sizeof(WMI_GET_WOW_LIST_REPLY)) { + return A_EINVAL; + } + reply = (WMI_GET_WOW_LIST_REPLY *)datap; + + A_WMI_WOW_LIST_EVENT(wmip->wmi_devt, reply->num_filters, + reply); + + return A_OK; +} + +A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip, + WMI_ADD_WOW_PATTERN_CMD *addWowCmd, + A_UINT8* pattern, A_UINT8* mask, + A_UINT8 pattern_size) +{ + void *osbuf; + A_INT8 size; + WMI_ADD_WOW_PATTERN_CMD *cmd; + A_UINT8 *filter_mask = NULL; + + size = sizeof (*cmd); + + size += ((2 * addWowCmd->filter_size)* sizeof(A_UINT8)); + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_ADD_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->filter_list_id = addWowCmd->filter_list_id; + cmd->filter_offset = addWowCmd->filter_offset; + cmd->filter_size = addWowCmd->filter_size; + + A_MEMCPY(cmd->filter, pattern, addWowCmd->filter_size); + + filter_mask = (A_UINT8*)(cmd->filter + cmd->filter_size); + A_MEMCPY(filter_mask, mask, addWowCmd->filter_size); + + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_WOW_PATTERN_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_del_wow_pattern_cmd(struct wmi_t *wmip, + WMI_DEL_WOW_PATTERN_CMD *delWowCmd) +{ + void *osbuf; + A_INT8 size; + WMI_DEL_WOW_PATTERN_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_DEL_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, delWowCmd, sizeof(WMI_DEL_WOW_PATTERN_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_DEL_WOW_PATTERN_CMDID, + NO_SYNC_WMIFLAG)); + +} + +void +wmi_cache_configure_snrthreshold(struct wmi_t *wmip, WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd) +{ + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_SNR]; + /* + * Parse the command and store the threshold values here. The checks + * for valid values can be put here + */ + sq_thresh->weight = snrCmd->weight; + sq_thresh->polling_interval = snrCmd->pollTime; + + sq_thresh->upper_threshold[0] = snrCmd->thresholdAbove1_Val; + sq_thresh->upper_threshold[1] = snrCmd->thresholdAbove2_Val; + sq_thresh->upper_threshold[2] = snrCmd->thresholdAbove3_Val; + sq_thresh->upper_threshold[3] = snrCmd->thresholdAbove4_Val; + sq_thresh->upper_threshold_valid_count = 4; + + /* List sorted in descending order */ + sq_thresh->lower_threshold[0] = snrCmd->thresholdBelow4_Val; + sq_thresh->lower_threshold[1] = snrCmd->thresholdBelow3_Val; + sq_thresh->lower_threshold[2] = snrCmd->thresholdBelow2_Val; + sq_thresh->lower_threshold[3] = snrCmd->thresholdBelow1_Val; + sq_thresh->lower_threshold_valid_count = 4; + + if (!snr_event_value) { + /* + * Configuring the thresholds to their extremes allows the host to get an + * event from the target which is used for the configuring the correct + * thresholds + */ + snrCmd->thresholdAbove1_Val = (A_UINT8)sq_thresh->upper_threshold[0]; + snrCmd->thresholdBelow1_Val = (A_UINT8)sq_thresh->lower_threshold[0]; + } else { + /* + * In case the user issues multiple times of snr_threshold_setting, + * we should not use the extreames anymore, the target does not expect that. + */ + snrCmd->thresholdAbove1_Val = ar6000_get_upper_threshold(snr_event_value, sq_thresh, + sq_thresh->upper_threshold_valid_count); + snrCmd->thresholdBelow1_Val = ar6000_get_lower_threshold(snr_event_value, sq_thresh, + sq_thresh->lower_threshold_valid_count); + } + +} +A_STATUS +wmi_set_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd) +{ + if( snrCmd->thresholdAbove4_Val <= snrCmd->thresholdAbove3_Val || + snrCmd->thresholdAbove3_Val <= snrCmd->thresholdAbove2_Val || + snrCmd->thresholdAbove2_Val <= snrCmd->thresholdAbove1_Val || + snrCmd->thresholdBelow4_Val <= snrCmd->thresholdBelow3_Val || + snrCmd->thresholdBelow3_Val <= snrCmd->thresholdBelow2_Val || + snrCmd->thresholdBelow2_Val <= snrCmd->thresholdBelow1_Val) + { + return A_EINVAL; + } + wmi_cache_configure_snrthreshold(wmip, snrCmd); + return (wmi_send_snr_threshold_params(wmip, snrCmd)); +} + +A_STATUS +wmi_clr_rssi_snr(struct wmi_t *wmip) +{ + void *osbuf; + + osbuf = A_NETBUF_ALLOC(sizeof(int)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + return (wmi_cmd_send(wmip, osbuf, WMI_CLR_RSSI_SNR_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_lq_threshold_params(struct wmi_t *wmip, + WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd) +{ + void *osbuf; + A_INT8 size; + WMI_LQ_THRESHOLD_PARAMS_CMD *cmd; + /* These values are in ascending order */ + if( lqCmd->thresholdAbove4_Val <= lqCmd->thresholdAbove3_Val || + lqCmd->thresholdAbove3_Val <= lqCmd->thresholdAbove2_Val || + lqCmd->thresholdAbove2_Val <= lqCmd->thresholdAbove1_Val || + lqCmd->thresholdBelow4_Val <= lqCmd->thresholdBelow3_Val || + lqCmd->thresholdBelow3_Val <= lqCmd->thresholdBelow2_Val || + lqCmd->thresholdBelow2_Val <= lqCmd->thresholdBelow1_Val ) { + + return A_EINVAL; + } + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_LQ_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, lqCmd, sizeof(WMI_LQ_THRESHOLD_PARAMS_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_LQ_THRESHOLD_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 mask) +{ + void *osbuf; + A_INT8 size; + WMI_TARGET_ERROR_REPORT_BITMASK *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_TARGET_ERROR_REPORT_BITMASK *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + cmd->bitmask = mask; + + return (wmi_cmd_send(wmip, osbuf, WMI_TARGET_ERROR_REPORT_BITMASK_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie, A_UINT32 source) +{ + void *osbuf; + WMIX_HB_CHALLENGE_RESP_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_HB_CHALLENGE_RESP_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->cookie = cookie; + cmd->source = source; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_HB_CHALLENGE_RESP_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask, + A_UINT16 tsr, A_BOOL rep, A_UINT16 size, + A_UINT32 valid) +{ + void *osbuf; + WMIX_DBGLOG_CFG_MODULE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_DBGLOG_CFG_MODULE_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->config.cfgmmask = mmask; + cmd->config.cfgtsr = tsr; + cmd->config.cfgrep = rep; + cmd->config.cfgsize = size; + cmd->config.cfgvalid = valid; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DBGLOG_CFG_MODULE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_stats_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_STATISTICS_CMDID); +} + +A_STATUS +wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid) +{ + void *osbuf; + WMI_ADD_BAD_AP_CMD *cmd; + + if ((bssid == NULL) || (apIndex > WMI_MAX_BAD_AP_INDEX)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_ADD_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->badApIndex = apIndex; + A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid)); + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_BAD_AP_CMDID, SYNC_BEFORE_WMIFLAG)); +} + +A_STATUS +wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex) +{ + void *osbuf; + WMI_DELETE_BAD_AP_CMD *cmd; + + if (apIndex > WMI_MAX_BAD_AP_INDEX) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DELETE_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->badApIndex = apIndex; + + return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_BAD_AP_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_abort_scan_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_ABORT_SCAN_CMDID); +} + +A_STATUS +wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM) +{ + void *osbuf; + WMI_SET_TX_PWR_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_TX_PWR_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->dbM = dbM; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_TX_PWR_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_txPwr_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_TX_PWR_CMDID); +} + +A_UINT16 +wmi_get_mapped_qos_queue(struct wmi_t *wmip, A_UINT8 trafficClass) +{ + A_UINT16 activeTsids=0; + + LOCK_WMI(wmip); + activeTsids = wmip->wmi_streamExistsForAC[trafficClass]; + UNLOCK_WMI(wmip); + + return activeTsids; +} + +A_STATUS +wmi_get_roam_tbl_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_ROAM_TBL_CMDID); +} + +A_STATUS +wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType) +{ + void *osbuf; + A_UINT32 size = sizeof(A_UINT8); + WMI_TARGET_ROAM_DATA *cmd; + + osbuf = A_NETBUF_ALLOC(size); /* no payload */ + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_TARGET_ROAM_DATA *)(A_NETBUF_DATA(osbuf)); + cmd->roamDataType = roamDataType; + + return (wmi_cmd_send(wmip, osbuf, WMI_GET_ROAM_DATA_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p, + A_UINT8 size) +{ + void *osbuf; + WMI_SET_ROAM_CTRL_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_SET_ROAM_CTRL_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + A_MEMCPY(cmd, p, size); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_ROAM_CTRL_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_powersave_timers_cmd(struct wmi_t *wmip, + WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd, + A_UINT8 size) +{ + void *osbuf; + WMI_POWERSAVE_TIMERS_POLICY_CMD *cmd; + + /* These timers can't be zero */ + if(!pCmd->psPollTimeout || !pCmd->triggerTimeout || + !(pCmd->apsdTimPolicy == IGNORE_TIM_ALL_QUEUES_APSD || + pCmd->apsdTimPolicy == PROCESS_TIM_ALL_QUEUES_APSD) || + !(pCmd->simulatedAPSDTimPolicy == IGNORE_TIM_SIMULATED_APSD || + pCmd->simulatedAPSDTimPolicy == PROCESS_TIM_SIMULATED_APSD)) + return A_EINVAL; + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_POWERSAVE_TIMERS_POLICY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + A_MEMCPY(cmd, pCmd, size); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID, + NO_SYNC_WMIFLAG)); +} + +#ifdef CONFIG_HOST_GPIO_SUPPORT +/* Send a command to Target to change GPIO output pins. */ +A_STATUS +wmi_gpio_output_set(struct wmi_t *wmip, + A_UINT32 set_mask, + A_UINT32 clear_mask, + A_UINT32 enable_mask, + A_UINT32 disable_mask) +{ + void *osbuf; + WMIX_GPIO_OUTPUT_SET_CMD *output_set; + int size; + + size = sizeof(*output_set); + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - set=0x%x clear=0x%x enb=0x%x dis=0x%x\n", DBGARG, + set_mask, clear_mask, enable_mask, disable_mask)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + output_set = (WMIX_GPIO_OUTPUT_SET_CMD *)(A_NETBUF_DATA(osbuf)); + + output_set->set_mask = set_mask; + output_set->clear_mask = clear_mask; + output_set->enable_mask = enable_mask; + output_set->disable_mask = disable_mask; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_OUTPUT_SET_CMDID, + NO_SYNC_WMIFLAG)); +} + +/* Send a command to the Target requesting state of the GPIO input pins */ +A_STATUS +wmi_gpio_input_get(struct wmi_t *wmip) +{ + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + return wmi_simple_cmd_xtnd(wmip, WMIX_GPIO_INPUT_GET_CMDID); +} + +/* Send a command to the Target that changes the value of a GPIO register. */ +A_STATUS +wmi_gpio_register_set(struct wmi_t *wmip, + A_UINT32 gpioreg_id, + A_UINT32 value) +{ + void *osbuf; + WMIX_GPIO_REGISTER_SET_CMD *register_set; + int size; + + size = sizeof(*register_set); + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG, gpioreg_id, value)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + register_set = (WMIX_GPIO_REGISTER_SET_CMD *)(A_NETBUF_DATA(osbuf)); + + register_set->gpioreg_id = gpioreg_id; + register_set->value = value; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_SET_CMDID, + NO_SYNC_WMIFLAG)); +} + +/* Send a command to the Target to fetch the value of a GPIO register. */ +A_STATUS +wmi_gpio_register_get(struct wmi_t *wmip, + A_UINT32 gpioreg_id) +{ + void *osbuf; + WMIX_GPIO_REGISTER_GET_CMD *register_get; + int size; + + size = sizeof(*register_get); + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter - reg=%d\n", DBGARG, gpioreg_id)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + register_get = (WMIX_GPIO_REGISTER_GET_CMD *)(A_NETBUF_DATA(osbuf)); + + register_get->gpioreg_id = gpioreg_id; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_GET_CMDID, + NO_SYNC_WMIFLAG)); +} + +/* Send a command to the Target acknowledging some GPIO interrupts. */ +A_STATUS +wmi_gpio_intr_ack(struct wmi_t *wmip, + A_UINT32 ack_mask) +{ + void *osbuf; + WMIX_GPIO_INTR_ACK_CMD *intr_ack; + int size; + + size = sizeof(*intr_ack); + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter ack_mask=0x%x\n", DBGARG, ack_mask)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + intr_ack = (WMIX_GPIO_INTR_ACK_CMD *)(A_NETBUF_DATA(osbuf)); + + intr_ack->ack_mask = ack_mask; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_INTR_ACK_CMDID, + NO_SYNC_WMIFLAG)); +} +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +A_STATUS +wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT16 txop, A_UINT8 eCWmin, + A_UINT8 eCWmax, A_UINT8 aifsn) +{ + void *osbuf; + WMI_SET_ACCESS_PARAMS_CMD *cmd; + + if ((eCWmin > WMI_MAX_CW_ACPARAM) || (eCWmax > WMI_MAX_CW_ACPARAM) || + (aifsn > WMI_MAX_AIFSN_ACPARAM)) + { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_ACCESS_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->txop = txop; + cmd->eCWmin = eCWmin; + cmd->eCWmax = eCWmax; + cmd->aifsn = aifsn; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_ACCESS_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType, + A_UINT8 trafficClass, A_UINT8 maxRetries, + A_UINT8 enableNotify) +{ + void *osbuf; + WMI_SET_RETRY_LIMITS_CMD *cmd; + + if ((frameType != MGMT_FRAMETYPE) && (frameType != CONTROL_FRAMETYPE) && + (frameType != DATA_FRAMETYPE)) + { + return A_EINVAL; + } + + if (maxRetries > WMI_MAX_RETRIES) { + return A_EINVAL; + } + + if (frameType != DATA_FRAMETYPE) { + trafficClass = 0; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_RETRY_LIMITS_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->frameType = frameType; + cmd->trafficClass = trafficClass; + cmd->maxRetries = maxRetries; + cmd->enableNotify = enableNotify; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_RETRY_LIMITS_CMDID, + NO_SYNC_WMIFLAG)); +} + +void +wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid) +{ + if (bssid != NULL) { + A_MEMCPY(bssid, wmip->wmi_bssid, ATH_MAC_LEN); + } +} + +A_STATUS +wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode) +{ + void *osbuf; + WMI_SET_OPT_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_OPT_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->optMode = optMode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_OPT_MODE_CMDID, + SYNC_BOTH_WMIFLAG)); +} + +A_STATUS +wmi_opt_tx_frame_cmd(struct wmi_t *wmip, + A_UINT8 frmType, + A_UINT8 *dstMacAddr, + A_UINT8 *bssid, + A_UINT16 optIEDataLen, + A_UINT8 *optIEData) +{ + void *osbuf; + WMI_OPT_TX_FRAME_CMD *cmd; + osbuf = A_NETBUF_ALLOC(optIEDataLen + sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, (optIEDataLen + sizeof(*cmd))); + + cmd = (WMI_OPT_TX_FRAME_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, (optIEDataLen + sizeof(*cmd)-1)); + + cmd->frmType = frmType; + cmd->optIEDataLen = optIEDataLen; + //cmd->optIEData = (A_UINT8 *)((int)cmd + sizeof(*cmd)); + A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid)); + A_MEMCPY(cmd->dstAddr, dstMacAddr, sizeof(cmd->dstAddr)); + A_MEMCPY(&cmd->optIEData[0], optIEData, optIEDataLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_OPT_TX_FRAME_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl) +{ + void *osbuf; + WMI_BEACON_INT_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_BEACON_INT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->beaconInterval = intvl; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BEACON_INT_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize) +{ + void *osbuf; + WMI_SET_VOICE_PKT_SIZE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_VOICE_PKT_SIZE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->voicePktSize = voicePktSize; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_VOICE_PKT_SIZE_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSPLen) +{ + void *osbuf; + WMI_SET_MAX_SP_LEN_CMD *cmd; + + /* maxSPLen is a two-bit value. If user trys to set anything + * other than this, then its invalid + */ + if(maxSPLen & ~0x03) + return A_EINVAL; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_MAX_SP_LEN_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->maxSPLen = maxSPLen; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_MAX_SP_LEN_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_UINT8 +wmi_determine_userPriority( + A_UINT8 *pkt, + A_UINT32 layer2Pri) +{ + A_UINT8 ipPri; + iphdr *ipHdr = (iphdr *)pkt; + + /* Determine IPTOS priority */ + /* + * IP Tos format : + * (Refer Pg 57 WMM-test-plan-v1.2) + * IP-TOS - 8bits + * : DSCP(6-bits) ECN(2-bits) + * : DSCP - P2 P1 P0 X X X + * where (P2 P1 P0) form 802.1D + */ + ipPri = ipHdr->ip_tos >> 5; + ipPri &= 0x7; + + if ((layer2Pri & 0x7) > ipPri) + return ((A_UINT8)layer2Pri & 0x7); + else + return ipPri; +} + +A_UINT8 +convert_userPriority_to_trafficClass(A_UINT8 userPriority) +{ + return (up_to_ac[userPriority & 0x7]); +} + +A_UINT8 +wmi_get_power_mode_cmd(struct wmi_t *wmip) +{ + return wmip->wmi_powerMode; +} + +A_STATUS +wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance) +{ + A_STATUS ret = A_OK; + +#define TSPEC_SUSPENSION_INTERVAL_ATHEROS_DEF (~0) +#define TSPEC_SERVICE_START_TIME_ATHEROS_DEF 0 +#define TSPEC_MAX_BURST_SIZE_ATHEROS_DEF 0 +#define TSPEC_DELAY_BOUND_ATHEROS_DEF 0 +#define TSPEC_MEDIUM_TIME_ATHEROS_DEF 0 +#define TSPEC_SBA_ATHEROS_DEF 0x2000 /* factor is 1 */ + + /* Verify TSPEC params for ATHEROS compliance */ + if(tspecCompliance == ATHEROS_COMPLIANCE) { + if ((pCmd->suspensionInt != TSPEC_SUSPENSION_INTERVAL_ATHEROS_DEF) || + (pCmd->serviceStartTime != TSPEC_SERVICE_START_TIME_ATHEROS_DEF) || + (pCmd->minDataRate != pCmd->meanDataRate) || + (pCmd->minDataRate != pCmd->peakDataRate) || + (pCmd->maxBurstSize != TSPEC_MAX_BURST_SIZE_ATHEROS_DEF) || + (pCmd->delayBound != TSPEC_DELAY_BOUND_ATHEROS_DEF) || + (pCmd->sba != TSPEC_SBA_ATHEROS_DEF) || + (pCmd->mediumTime != TSPEC_MEDIUM_TIME_ATHEROS_DEF)) { + + A_DPRINTF(DBG_WMI, (DBGFMT "Invalid TSPEC params\n", DBGARG)); + //A_PRINTF("%s: Invalid TSPEC params\n", __func__); + ret = A_EINVAL; + } + } + + return ret; +} + +#ifdef CONFIG_HOST_TCMD_SUPPORT +static A_STATUS +wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TCMD_RX_REPORT_EVENT(wmip->wmi_devt, datap, len); + + return A_OK; +} + +#endif /* CONFIG_HOST_TCMD_SUPPORT*/ + +A_STATUS +wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode) +{ + void *osbuf; + WMI_SET_AUTH_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_AUTH_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->mode = mode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_AUTH_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode) +{ + void *osbuf; + WMI_SET_REASSOC_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_REASSOC_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->mode = mode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_REASSOC_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status) +{ + void *osbuf; + WMI_SET_LPREAMBLE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_LPREAMBLE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->status = status; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_LPREAMBLE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold) +{ + void *osbuf; + WMI_SET_RTS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_RTS_CMD*)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->threshold = threshold; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_RTS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status) +{ + void *osbuf; + WMI_SET_WMM_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_WMM_CMD*)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->status = status; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_CMDID, + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG cfg) +{ + void *osbuf; + WMI_SET_WMM_TXOP_CMD *cmd; + + if( !((cfg == WMI_TXOP_DISABLED) || (cfg == WMI_TXOP_ENABLED)) ) + return A_EINVAL; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_WMM_TXOP_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->txopEnable = cfg; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_TXOP_CMDID, + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_set_country(struct wmi_t *wmip, A_UCHAR *countryCode) +{ + void *osbuf; + WMI_AP_SET_COUNTRY_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_AP_SET_COUNTRY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + A_MEMCPY(cmd->countryCode,countryCode,3); + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_COUNTRY_CMDID, + NO_SYNC_WMIFLAG)); +} + +#ifdef CONFIG_HOST_TCMD_SUPPORT +/* WMI layer doesn't need to know the data type of the test cmd. + This would be beneficial for customers like Qualcomm, who might + have different test command requirements from differnt manufacturers + */ +A_STATUS +wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32 len) +{ + void *osbuf; + char *data; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + osbuf= A_NETBUF_ALLOC(len); + if(osbuf == NULL) + { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, len); + data = A_NETBUF_DATA(osbuf); + A_MEMCPY(data, buf, len); + + return(wmi_cmd_send(wmip, osbuf, WMI_TEST_CMDID, + NO_SYNC_WMIFLAG)); +} + +#endif + +A_STATUS +wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status) +{ + void *osbuf; + WMI_SET_BT_STATUS_CMD *cmd; + + ATHR_DISPLAY_MSG (_T("Enter - streamType=%d, status=%d\n"), streamType, status); + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_BT_STATUS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->streamType = streamType; + cmd->status = status; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_STATUS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd) +{ + void *osbuf; + WMI_SET_BT_PARAMS_CMD* alloc_cmd; + + ATHR_DISPLAY_MSG (_T("cmd params is %d\n"), cmd->paramType); + + if (cmd->paramType == BT_PARAM_SCO) { + ATHR_DISPLAY_MSG (_T("sco params %d %d %d %d %d %d %d %d %d %d %d %d\n"), + cmd->info.scoParams.numScoCyclesForceTrigger, + cmd->info.scoParams.dataResponseTimeout, + cmd->info.scoParams.stompScoRules, + cmd->info.scoParams.scoOptFlags, + cmd->info.scoParams.p2lrpOptModeBound, + cmd->info.scoParams.p2lrpNonOptModeBound, + cmd->info.scoParams.stompDutyCyleVal, + cmd->info.scoParams.stompDutyCyleMaxVal, + cmd->info.scoParams.psPollLatencyFraction, + cmd->info.scoParams.noSCOSlots, + cmd->info.scoParams.noIdleSlots, + cmd->info.scoParams.reserved8); + } + else if (cmd->paramType == BT_PARAM_A2DP) { + ATHR_DISPLAY_MSG (_T("A2DP params %d %d %d %d %d %d %d %d %d\n"), + cmd->info.a2dpParams.a2dpWlanUsageLimit, + cmd->info.a2dpParams.a2dpBurstCntMin, + cmd->info.a2dpParams.a2dpDataRespTimeout, + cmd->info.a2dpParams.a2dpOptFlags, + cmd->info.a2dpParams.p2lrpOptModeBound, + cmd->info.a2dpParams.p2lrpNonOptModeBound, + cmd->info.a2dpParams.reserved16, + cmd->info.a2dpParams.isCoLocatedBtRoleMaster, + cmd->info.a2dpParams.reserved8); + } + else if (cmd->paramType == BT_PARAM_ANTENNA_CONFIG) { + ATHR_DISPLAY_MSG (_T("Ant config %d\n"), cmd->info.antType); + } + else if (cmd->paramType == BT_PARAM_COLOCATED_BT_DEVICE) { + ATHR_DISPLAY_MSG (_T("co-located BT %d\n"), cmd->info.coLocatedBtDev); + } + else if (cmd->paramType == BT_PARAM_ACLCOEX) { + ATHR_DISPLAY_MSG (_T("ACL params %d %d %d\n"), cmd->info.aclCoexParams.aclWlanMediumUsageTime, + cmd->info.aclCoexParams.aclBtMediumUsageTime, + cmd->info.aclCoexParams.aclDataRespTimeout); + } + else if (cmd->paramType == BT_PARAM_11A_SEPARATE_ANT) { + A_DPRINTF(DBG_WMI, (DBGFMT "11A ant\n", DBGARG)); + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + alloc_cmd = (WMI_SET_BT_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(alloc_cmd, sizeof(*cmd)); + A_MEMCPY(alloc_cmd, cmd, sizeof(*cmd)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_keepalive_configured(struct wmi_t *wmip) +{ + void *osbuf; + WMI_GET_KEEPALIVE_CMD *cmd; + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + cmd = (WMI_GET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + return (wmi_cmd_send(wmip, osbuf, WMI_GET_KEEPALIVE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_UINT8 +wmi_get_keepalive_cmd(struct wmi_t *wmip) +{ + return wmip->wmi_keepaliveInterval; +} + +A_STATUS +wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval) +{ + void *osbuf; + WMI_SET_KEEPALIVE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->keepaliveInterval = keepaliveInterval; + wmip->wmi_keepaliveInterval = keepaliveInterval; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_KEEPALIVE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_params_cmd(struct wmi_t *wmip, A_UINT32 opcode, A_UINT32 length, A_CHAR* buffer) +{ + void *osbuf; + WMI_SET_PARAMS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd) + length); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd) + length); + + cmd = (WMI_SET_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->opcode = opcode; + cmd->length = length; + A_MEMCPY(cmd->buffer, buffer, length); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4) +{ + void *osbuf; + WMI_SET_MCAST_FILTER_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->multicast_mac[0] = 0x01; + cmd->multicast_mac[1] = 0x00; + cmd->multicast_mac[2] = 0x5e; + cmd->multicast_mac[3] = dot2&0x7F; + cmd->multicast_mac[4] = dot3; + cmd->multicast_mac[5] = dot4; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_MCAST_FILTER_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_del_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4) +{ + void *osbuf; + WMI_SET_MCAST_FILTER_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->multicast_mac[0] = 0x01; + cmd->multicast_mac[1] = 0x00; + cmd->multicast_mac[2] = 0x5e; + cmd->multicast_mac[3] = dot2&0x7F; + cmd->multicast_mac[4] = dot3; + cmd->multicast_mac[5] = dot4; + + return (wmi_cmd_send(wmip, osbuf, WMI_DEL_MCAST_FILTER_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType, A_UINT8 ieLen, + A_UINT8 *ieInfo) +{ + void *osbuf; + WMI_SET_APPIE_CMD *cmd; + A_UINT16 cmdLen; + + cmdLen = sizeof(*cmd) + ieLen - 1; + osbuf = A_NETBUF_ALLOC(cmdLen); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, cmdLen); + + cmd = (WMI_SET_APPIE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + + cmd->mgmtFrmType = mgmtFrmType; + cmd->ieLen = ieLen; + A_MEMCPY(cmd->ieInfo, ieInfo, ieLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_APPIE_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen) +{ + void *osbuf; + A_UINT8 *data; + + osbuf = A_NETBUF_ALLOC(dataLen); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, dataLen); + + data = A_NETBUF_DATA(osbuf); + + A_MEMCPY(data, cmd, dataLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WHALPARAM_CMDID, NO_SYNC_WMIFLAG)); +} + +A_INT32 +wmi_get_rate(A_INT8 rateindex) +{ + if (rateindex == RATE_AUTO) { + return 0; + } else { + return(wmi_rateTable[(A_UINT32) rateindex]); + } +} + +void +wmi_node_return (struct wmi_t *wmip, bss_t *bss) +{ + if (NULL != bss) + { + wlan_node_return (&wmip->wmi_scan_table, bss); + } +} + +void +wmi_set_nodeage(struct wmi_t *wmip, A_UINT32 nodeAge) +{ + wlan_set_nodeage(&wmip->wmi_scan_table,nodeAge); +} + +bss_t * +wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID) +{ + bss_t *node = NULL; + node = wlan_find_Ssidnode (&wmip->wmi_scan_table, pSsid, + ssidLength, bIsWPA2, bMatchSSID); + return node; +} + + +void +wmi_free_allnodes(struct wmi_t *wmip) +{ + wlan_free_allnodes(&wmip->wmi_scan_table); +} + +bss_t * +wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr) +{ + bss_t *ni=NULL; + ni=wlan_find_node(&wmip->wmi_scan_table,macaddr); + return ni; +} + +void +wmi_free_node(struct wmi_t *wmip, const A_UINT8 *macaddr) +{ + bss_t *ni=NULL; + + ni=wlan_find_node(&wmip->wmi_scan_table,macaddr); + if (ni != NULL) { + wlan_node_reclaim(&wmip->wmi_scan_table, ni); + } + + return; +} + +A_STATUS +wmi_dset_open_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT32 access_cookie, + A_UINT32 dset_size, + A_UINT32 dset_version, + A_UINT32 targ_handle, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg) +{ + void *osbuf; + WMIX_DSETOPEN_REPLY_CMD *open_reply; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter - wmip=0x%x\n", DBGARG, (int)wmip)); + + osbuf = A_NETBUF_ALLOC(sizeof(*open_reply)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*open_reply)); + open_reply = (WMIX_DSETOPEN_REPLY_CMD *)(A_NETBUF_DATA(osbuf)); + + open_reply->status = status; + open_reply->targ_dset_handle = targ_handle; + open_reply->targ_reply_fn = targ_reply_fn; + open_reply->targ_reply_arg = targ_reply_arg; + open_reply->access_cookie = access_cookie; + open_reply->size = dset_size; + open_reply->version = dset_version; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETOPEN_REPLY_CMDID, + NO_SYNC_WMIFLAG)); +} + +static A_STATUS +wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len) +{ + WMI_PMKID_LIST_REPLY *reply; + A_UINT32 expected_len; + + if (len < sizeof(WMI_PMKID_LIST_REPLY)) { + return A_EINVAL; + } + reply = (WMI_PMKID_LIST_REPLY *)datap; + expected_len = sizeof(reply->numPMKID) + reply->numPMKID * WMI_PMKID_LEN; + + if (len < expected_len) { + return A_EINVAL; + } + + A_WMI_PMKID_LIST_EVENT(wmip->wmi_devt, reply->numPMKID, + reply->pmkidList, reply->bssidList[0]); + + return A_OK; +} + + +static A_STATUS +wmi_set_params_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len) +{ + WMI_SET_PARAMS_REPLY *reply; + + if (len < sizeof(WMI_SET_PARAMS_REPLY)) { + return A_EINVAL; + } + reply = (WMI_SET_PARAMS_REPLY *)datap; + + if (A_OK == reply->status) + { + + } + else + { + + } + + return A_OK; +} + + + +#ifdef CONFIG_HOST_DSET_SUPPORT +A_STATUS +wmi_dset_data_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT8 *user_buf, + A_UINT32 length, + A_UINT32 targ_buf, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg) +{ + void *osbuf; + WMIX_DSETDATA_REPLY_CMD *data_reply; + int size; + + size = sizeof(*data_reply) + length; + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - length=%d status=%d\n", DBGARG, length, status)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + data_reply = (WMIX_DSETDATA_REPLY_CMD *)(A_NETBUF_DATA(osbuf)); + + data_reply->status = status; + data_reply->targ_buf = targ_buf; + data_reply->targ_reply_fn = targ_reply_fn; + data_reply->targ_reply_arg = targ_reply_arg; + data_reply->length = length; + + if (status == A_OK) { + if (a_copy_from_user(data_reply->buf, user_buf, length)) { + return A_ERROR; + } + } + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETDATA_REPLY_CMDID, + NO_SYNC_WMIFLAG)); +} +#endif /* CONFIG_HOST_DSET_SUPPORT */ + +A_STATUS +wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status) +{ + void *osbuf; + char *cmd; + + osbuf = a_netbuf_alloc(sizeof(1)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + a_netbuf_put(osbuf, sizeof(1)); + + cmd = (char *)(a_netbuf_to_data(osbuf)); + + A_MEMZERO(cmd, sizeof(*cmd)); + cmd[0] = (status?1:0); + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WSC_STATUS_CMDID, + NO_SYNC_WMIFLAG)); +} + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +A_STATUS +wmi_prof_cfg_cmd(struct wmi_t *wmip, + A_UINT32 period, + A_UINT32 nbins) +{ + void *osbuf; + WMIX_PROF_CFG_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_PROF_CFG_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->period = period; + cmd->nbins = nbins; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_PROF_CFG_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_prof_addr_set_cmd(struct wmi_t *wmip, A_UINT32 addr) +{ + void *osbuf; + WMIX_PROF_ADDR_SET_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_PROF_ADDR_SET_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->addr = addr; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_PROF_ADDR_SET_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_prof_start_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_START_CMDID); +} + +A_STATUS +wmi_prof_stop_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_STOP_CMDID); +} + +A_STATUS +wmi_prof_count_get_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_COUNT_GET_CMDID); +} + +/* Called to handle WMIX_PROF_CONT_EVENTID */ +static A_STATUS +wmi_prof_count_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_PROF_COUNT_EVENT *prof_data = (WMIX_PROF_COUNT_EVENT *)datap; + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - addr=0x%x count=%d\n", DBGARG, + prof_data->addr, prof_data->count)); + + A_WMI_PROF_COUNT_RX(prof_data->addr, prof_data->count); + + return A_OK; +} +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + +#ifdef OS_ROAM_MANAGEMENT + +#define ETHERNET_MAC_ADDRESS_LENGTH 6 + +void +wmi_scan_indication (struct wmi_t *wmip) +{ + struct ieee80211_node_table *nt; + A_UINT32 gen; + A_UINT32 size; + A_UINT32 bsssize; + bss_t *bss; + A_UINT32 numbss; + PNDIS_802_11_BSSID_SCAN_INFO psi; + PBYTE pie; + NDIS_802_11_FIXED_IEs *pFixed; + NDIS_802_11_VARIABLE_IEs *pVar; + A_UINT32 RateSize; + + struct ar6kScanIndication + { + NDIS_802_11_STATUS_INDICATION ind; + NDIS_802_11_BSSID_SCAN_INFO_LIST slist; + } *pAr6kScanIndEvent; + + nt = &wmip->wmi_scan_table; + + ++nt->nt_si_gen; + + + gen = nt->nt_si_gen; + + size = offsetof(struct ar6kScanIndication, slist) + + offsetof(NDIS_802_11_BSSID_SCAN_INFO_LIST, BssidScanInfo); + + numbss = 0; + + IEEE80211_NODE_LOCK(nt); + + //calc size + for (bss = nt->nt_node_first; bss; bss = bss->ni_list_next) { + if (bss->ni_si_gen != gen) { + bsssize = offsetof(NDIS_802_11_BSSID_SCAN_INFO, Bssid) + offsetof(NDIS_WLAN_BSSID_EX, IEs); + bsssize = bsssize + sizeof(NDIS_802_11_FIXED_IEs); + +#ifdef SUPPORT_WPA2 + if (bss->ni_cie.ie_rsn) { + bsssize = bsssize + bss->ni_cie.ie_rsn[1] + 2; + } +#endif + if (bss->ni_cie.ie_wpa) { + bsssize = bsssize + bss->ni_cie.ie_wpa[1] + 2; + } + + // bsssize must be a multiple of 4 to maintain alignment. + bsssize = (bsssize + 3) & ~3; + + size += bsssize; + + numbss++; + } + } + + if (0 == numbss) + { +// RETAILMSG(1, (L"AR6K: scan indication: 0 bss\n")); + ar6000_scan_indication (wmip->wmi_devt, NULL, 0); + IEEE80211_NODE_UNLOCK (nt); + return; + } + + pAr6kScanIndEvent = A_MALLOC(size); + + if (NULL == pAr6kScanIndEvent) + { + IEEE80211_NODE_UNLOCK(nt); + return; + } + + A_MEMZERO(pAr6kScanIndEvent, size); + + //copy data + pAr6kScanIndEvent->ind.StatusType = Ndis802_11StatusType_BssidScanInfoList; + pAr6kScanIndEvent->slist.Version = 1; + pAr6kScanIndEvent->slist.NumItems = numbss; + + psi = &pAr6kScanIndEvent->slist.BssidScanInfo[0]; + + for (bss = nt->nt_node_first; bss; bss = bss->ni_list_next) { + if (bss->ni_si_gen != gen) { + + bss->ni_si_gen = gen; + + //Set scan time + psi->ScanTime = bss->ni_tstamp - WLAN_NODE_INACT_TIMEOUT_MSEC; + + // Copy data to bssid_ex + bsssize = offsetof(NDIS_WLAN_BSSID_EX, IEs); + bsssize = bsssize + sizeof(NDIS_802_11_FIXED_IEs); + +#ifdef SUPPORT_WPA2 + if (bss->ni_cie.ie_rsn) { + bsssize = bsssize + bss->ni_cie.ie_rsn[1] + 2; + } +#endif + if (bss->ni_cie.ie_wpa) { + bsssize = bsssize + bss->ni_cie.ie_wpa[1] + 2; + } + + // bsssize must be a multiple of 4 to maintain alignment. + bsssize = (bsssize + 3) & ~3; + + psi->Bssid.Length = bsssize; + + memcpy (psi->Bssid.MacAddress, bss->ni_macaddr, ETHERNET_MAC_ADDRESS_LENGTH); + + +//if (((bss->ni_macaddr[3] == 0xCE) && (bss->ni_macaddr[4] == 0xF0) && (bss->ni_macaddr[5] == 0xE7)) || +// ((bss->ni_macaddr[3] == 0x03) && (bss->ni_macaddr[4] == 0xE2) && (bss->ni_macaddr[5] == 0x70))) +// RETAILMSG (1, (L"%x\n",bss->ni_macaddr[5])); + + psi->Bssid.Ssid.SsidLength = 0; + pie = bss->ni_cie.ie_ssid; + + if (pie) { + // Format of SSID IE is: + // Type (1 octet) + // Length (1 octet) + // SSID (Length octets) + // + // Validation of the IE should have occurred within WMI. + // + if (pie[1] <= 32) { + psi->Bssid.Ssid.SsidLength = pie[1]; + memcpy(psi->Bssid.Ssid.Ssid, &pie[2], psi->Bssid.Ssid.SsidLength); + } + } + psi->Bssid.Privacy = (bss->ni_cie.ie_capInfo & 0x10) ? 1 : 0; + + //Post the RSSI value relative to the Standard Noise floor value. + psi->Bssid.Rssi = bss->ni_rssi; + + if (bss->ni_cie.ie_chan >= 2412 && bss->ni_cie.ie_chan <= 2484) { + + if (bss->ni_cie.ie_rates && bss->ni_cie.ie_xrates) { + psi->Bssid.NetworkTypeInUse = Ndis802_11OFDM24; + } + else { + psi->Bssid.NetworkTypeInUse = Ndis802_11DS; + } + } + else { + psi->Bssid.NetworkTypeInUse = Ndis802_11OFDM5; + } + + psi->Bssid.Configuration.Length = sizeof(psi->Bssid.Configuration); + psi->Bssid.Configuration.BeaconPeriod = bss->ni_cie.ie_beaconInt; // Units are Kmicroseconds (1024 us) + psi->Bssid.Configuration.ATIMWindow = 0; + psi->Bssid.Configuration.DSConfig = bss->ni_cie.ie_chan * 1000; + psi->Bssid.InfrastructureMode = ((bss->ni_cie.ie_capInfo & 0x03) == 0x01 ) ? Ndis802_11Infrastructure : Ndis802_11IBSS; + + RateSize = 0; + pie = bss->ni_cie.ie_rates; + if (pie) { + RateSize = (pie[1] < NDIS_802_11_LENGTH_RATES_EX) ? pie[1] : NDIS_802_11_LENGTH_RATES_EX; + memcpy(psi->Bssid.SupportedRates, &pie[2], RateSize); + } + pie = bss->ni_cie.ie_xrates; + if (pie && RateSize < NDIS_802_11_LENGTH_RATES_EX) { + memcpy(psi->Bssid.SupportedRates + RateSize, &pie[2], + (pie[1] < (NDIS_802_11_LENGTH_RATES_EX - RateSize)) ? pie[1] : (NDIS_802_11_LENGTH_RATES_EX - RateSize)); + } + + // Copy the fixed IEs + psi->Bssid.IELength = sizeof(NDIS_802_11_FIXED_IEs); + + pFixed = (NDIS_802_11_FIXED_IEs *)psi->Bssid.IEs; + memcpy(pFixed->Timestamp, bss->ni_cie.ie_tstamp, sizeof(pFixed->Timestamp)); + pFixed->BeaconInterval = bss->ni_cie.ie_beaconInt; + pFixed->Capabilities = bss->ni_cie.ie_capInfo; + + // Copy selected variable IEs + + pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pFixed + sizeof(NDIS_802_11_FIXED_IEs)); + +#ifdef SUPPORT_WPA2 + // Copy the WPAv2 IE + if (bss->ni_cie.ie_rsn) { + pie = bss->ni_cie.ie_rsn; + psi->Bssid.IELength += pie[1] + 2; + memcpy(pVar, pie, pie[1] + 2); + pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pVar + pie[1] + 2); + } +#endif + // Copy the WPAv1 IE + if (bss->ni_cie.ie_wpa) { + pie = bss->ni_cie.ie_wpa; + psi->Bssid.IELength += pie[1] + 2; + memcpy(pVar, pie, pie[1] + 2); + pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pVar + pie[1] + 2); + } + + // Advance buffer pointer + psi = (PNDIS_802_11_BSSID_SCAN_INFO)((BYTE*)psi + bsssize + FIELD_OFFSET(NDIS_802_11_BSSID_SCAN_INFO, Bssid)); + } + } + + IEEE80211_NODE_UNLOCK(nt); + +// wmi_free_allnodes(wmip); + +// RETAILMSG(1, (L"AR6K: scan indication: %u bss\n", numbss)); + + ar6000_scan_indication (wmip->wmi_devt, pAr6kScanIndEvent, size); + + A_FREE(pAr6kScanIndEvent); +} +#endif + +A_UINT8 +ar6000_get_upper_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, + A_UINT32 size) +{ + A_UINT32 index; + A_UINT8 threshold = (A_UINT8)sq_thresh->upper_threshold[size - 1]; + + /* The list is already in sorted order. Get the next lower value */ + for (index = 0; index < size; index ++) { + if (rssi < sq_thresh->upper_threshold[index]) { + threshold = (A_UINT8)sq_thresh->upper_threshold[index]; + break; + } + } + + return threshold; +} + +A_UINT8 +ar6000_get_lower_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, + A_UINT32 size) +{ + A_UINT32 index; + A_UINT8 threshold = (A_UINT8)sq_thresh->lower_threshold[size - 1]; + + /* The list is already in sorted order. Get the next lower value */ + for (index = 0; index < size; index ++) { + if (rssi > sq_thresh->lower_threshold[index]) { + threshold = (A_UINT8)sq_thresh->lower_threshold[index]; + break; + } + } + + return threshold; +} +static A_STATUS +wmi_send_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd) +{ + void *osbuf; + A_INT8 size; + WMI_RSSI_THRESHOLD_PARAMS_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_RSSI_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, rssiCmd, sizeof(WMI_RSSI_THRESHOLD_PARAMS_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_RSSI_THRESHOLD_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} +static A_STATUS +wmi_send_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd) +{ + void *osbuf; + A_INT8 size; + WMI_SNR_THRESHOLD_PARAMS_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + cmd = (WMI_SNR_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, snrCmd, sizeof(WMI_SNR_THRESHOLD_PARAMS_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SNR_THRESHOLD_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_target_event_report_cmd(struct wmi_t *wmip, WMI_SET_TARGET_EVENT_REPORT_CMD* cmd) +{ + void *osbuf; + WMI_SET_TARGET_EVENT_REPORT_CMD* alloc_cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + alloc_cmd = (WMI_SET_TARGET_EVENT_REPORT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(alloc_cmd, sizeof(*cmd)); + A_MEMCPY(alloc_cmd, cmd, sizeof(*cmd)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_TARGET_EVENT_REPORT_CMDID, + NO_SYNC_WMIFLAG)); +} + +#ifdef PYXIS_ADHOC +A_STATUS +wmi_set_pyxis_gen_config (struct wmi_t *wmip, A_UINT32 dataWindowSizeMin, A_UINT32 dataWindowSizeMax, A_UINT8 maxJoiners) +{ + void *osbuf; + WMI_PYXIS_GEN_CONFIG *cmd = NULL; + A_UINT16 cmdLen; + + cmdLen = sizeof (WMI_PYXIS_CONFIG_HDR) + sizeof (dataWindowSizeMin) + sizeof (dataWindowSizeMax) + sizeof (maxJoiners); + + osbuf = A_NETBUF_ALLOC (cmdLen); + + if (osbuf == NULL) + { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, cmdLen); + + cmd = (WMI_PYXIS_GEN_CONFIG *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + + cmd->hdr.pyxisConfigType = WMI_PYXIS_GEN_PARAMS; + cmd->hdr.pyxisConfigLen = sizeof (dataWindowSizeMin) + sizeof (dataWindowSizeMax) + sizeof (maxJoiners); + cmd->dataWindowSizeMin = dataWindowSizeMin; + cmd->dataWindowSizeMax = dataWindowSizeMax; + cmd->maxJoiners = maxJoiners; + + return (wmi_cmd_send (wmip, osbuf, WMI_PYXIS_CONFIG_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_pyxis_dscvr_config (struct wmi_t *wmip, A_UINT32 dscvrWindow, A_UINT32 dscvrInterval, + A_UINT32 probeInterval, A_UINT32 probePeriod, A_UINT16 dscvrChannel) +{ + void *osbuf; + WMI_PYXIS_DSCVR_CONFIG *cmd = NULL; + A_UINT16 cmdLen; + + cmdLen = sizeof (WMI_PYXIS_DSCVR_CONFIG); + + osbuf = A_NETBUF_ALLOC (cmdLen); + + if (osbuf == NULL) + { + return A_NO_MEMORY; + } + + A_NETBUF_PUT (osbuf, cmdLen); + + cmd = (WMI_PYXIS_DSCVR_CONFIG *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + + cmd->hdr.pyxisConfigType = WMI_PYXIS_DSCVR_PARAMS; + cmd->hdr.pyxisConfigLen = sizeof (WMI_PYXIS_DSCVR_CONFIG) - sizeof (WMI_PYXIS_CONFIG_HDR); + cmd->dscvrWindow = dscvrWindow; + cmd->dscvrInterval = dscvrInterval; + cmd->dscvrLife = 0; // to be defined + cmd->probeInterval = probeInterval; + cmd->probePeriod = probePeriod; + cmd->dscvrChannel = dscvrChannel; + + return (wmi_cmd_send(wmip, osbuf, WMI_PYXIS_CONFIG_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_pyxis_join_cmd (struct wmi_t *wmip, NETWORK_TYPE wmiNetworkType, + DOT11_AUTH_MODE dot11AuthMode, AUTH_MODE authMode, + CRYPTO_TYPE pairwiseCrypto, A_UINT8 pairwiseCryptoLen, + CRYPTO_TYPE groupCrypto, A_UINT8 groupCryptoLen, + A_UINT8 *bssid, A_UINT8 *nwBSSID, A_UINT16 channel, A_UINT32 ctrl_flags + ) +{ + void *osbuf; + WMI_PYXIS_JOIN_CMD *cmd = NULL; + A_UINT16 cmdLen; + + if ((pairwiseCrypto == NONE_CRYPT) && (groupCrypto != NONE_CRYPT)) { + return A_EINVAL; + } + + if ((pairwiseCrypto != NONE_CRYPT) && (groupCrypto == NONE_CRYPT)) { + return A_EINVAL; + } + + cmdLen = sizeof (WMI_PYXIS_JOIN_CMD); + + osbuf = A_NETBUF_ALLOC (cmdLen); + + if (osbuf == NULL) + { + return A_NO_MEMORY; + } + + A_NETBUF_PUT (osbuf, cmdLen); + + cmd = (WMI_PYXIS_JOIN_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + + cmd->hdr.pyxisCmd = WMI_PYXIS_JOIN_PEER; + cmd->hdr.pyxisCmdLen = sizeof (WMI_PYXIS_JOIN_CMD) - sizeof (WMI_PYXIS_CMD_HDR); + + if (NULL != cmd->peerMacAddr) + { + memcpy (cmd->peerMacAddr, bssid, ATH_MAC_LEN); + } + if (NULL != cmd->nwBSSID) + { + memcpy (cmd->nwBSSID, nwBSSID, ATH_MAC_LEN); + } + + cmd->networkType = wmiNetworkType; + cmd->dot11AuthMode = dot11AuthMode; + cmd->authMode = authMode; + cmd->pairwiseCryptoType = pairwiseCrypto; + cmd->pairwiseCryptoLen = pairwiseCryptoLen; + cmd->groupCryptoType = groupCrypto; + cmd->groupCryptoLen = groupCryptoLen; + cmd->channel = channel; + cmd->ctrl_flags = ctrl_flags; + + if (wmi_set_keepalive_cmd(wmip, wmip->wmi_keepaliveInterval) != A_OK) { + return(A_ERROR); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_PYXIS_OPERATION_CMDID, NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_pyxis_disconnect_cmd (struct wmi_t *wmip, A_UINT8 *bssid) +{ + void *osbuf; + WMI_PYXIS_DISCONNECT_CMD *cmd = NULL; + A_UINT16 cmdLen; + + cmdLen = sizeof (WMI_PYXIS_DISCONNECT_CMD); + + osbuf = A_NETBUF_ALLOC (cmdLen); + + if (osbuf == NULL) + { + return A_NO_MEMORY; + } + + A_NETBUF_PUT (osbuf, cmdLen); + + cmd = (WMI_PYXIS_DISCONNECT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + + cmd->hdr.pyxisCmd = WMI_PYXIS_DISC_PEER; + cmd->hdr.pyxisCmdLen = ATH_MAC_LEN; + memcpy (cmd->peerMacAddr, bssid, ATH_MAC_LEN); + + return (wmi_cmd_send (wmip, osbuf, WMI_PYXIS_OPERATION_CMDID, NO_SYNC_WMIFLAG)); +} + +#endif +bss_t *wmi_rm_current_bss (struct wmi_t *wmip, A_UINT8 *id) +{ + wmi_get_current_bssid (wmip, id); + return wlan_node_remove (&wmip->wmi_scan_table, id); +} + +A_STATUS wmi_add_current_bss (struct wmi_t *wmip, A_UINT8 *id, bss_t *bss) +{ + wlan_setup_node (&wmip->wmi_scan_table, bss, id); + return A_OK; +} + +//////////////////////////////////////////////////////////////////////////////// +//// //// +//// AP mode functions //// +//// //// +//////////////////////////////////////////////////////////////////////////////// +/* + * IOCTL: AR6000_XIOCTL_AP_COMMIT_CONFIG + * + * When AR6K in AP mode, This command will be called after + * changing ssid, channel etc. It will pass the profile to + * target with a flag which will indicate which parameter changed, + * also if this flag is 0, there was no change in parametes, so + * commit cmd will not be sent to target. Without calling this IOCTL + * the changes will not take effect. + */ +A_STATUS +wmi_ap_profile_commit(struct wmi_t *wmip, WMI_CONNECT_CMD *p) +{ + void *osbuf; + WMI_CONNECT_CMD *cm; + + osbuf = A_NETBUF_ALLOC(sizeof(*cm)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cm)); + cm = (WMI_CONNECT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cm, sizeof(*cm)); + + A_MEMCPY(cm,p,sizeof(*cm)); + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_CONFIG_COMMIT_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_HIDDEN_SSID + * + * This command will be used to enable/disable hidden ssid functioanlity of + * beacon. If it is enabled, ssid will be NULL in beacon. + */ +A_STATUS +wmi_ap_set_hidden_ssid(struct wmi_t *wmip, A_UINT8 hidden_ssid) +{ + void *osbuf; + WMI_AP_HIDDEN_SSID_CMD *hs; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_HIDDEN_SSID_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_HIDDEN_SSID_CMD)); + hs = (WMI_AP_HIDDEN_SSID_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(hs, sizeof(*hs)); + + hs->hidden_ssid = hidden_ssid; + + A_DPRINTF(DBG_WMI, (DBGFMT "AR6000_XIOCTL_AP_HIDDEN_SSID %d\n", DBGARG , hidden_ssid)); + return (wmi_cmd_send(wmip, osbuf, WMI_AP_HIDDEN_SSID_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_SET_MAX_NUM_STA + * + * This command is used to limit max num of STA that can connect + * with this AP. This value should not exceed AP_MAX_NUM_STA (this + * is max num of STA supported by AP). Value was already validated + * in ioctl.c + */ +A_STATUS +wmi_ap_set_num_sta(struct wmi_t *wmip, A_UINT8 num_sta) +{ + void *osbuf; + WMI_AP_SET_NUM_STA_CMD *ns; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_NUM_STA_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_NUM_STA_CMD)); + ns = (WMI_AP_SET_NUM_STA_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(ns, sizeof(*ns)); + + ns->num_sta = num_sta; + + A_DPRINTF(DBG_WMI, (DBGFMT "AR6000_XIOCTL_AP_SET_MAX_NUM_STA %d\n", DBGARG , num_sta)); + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_NUM_STA_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_SET_ACL_MAC + * + * This command is used to send list of mac of STAs which will + * be allowed to connect with this AP. When this list is empty + * firware will allow all STAs till the count reaches AP_MAX_NUM_STA. + */ +A_STATUS +wmi_ap_acl_mac_list(struct wmi_t *wmip, WMI_AP_ACL_MAC_CMD *acl) +{ + void *osbuf; + WMI_AP_ACL_MAC_CMD *a; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_ACL_MAC_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_ACL_MAC_CMD)); + a = (WMI_AP_ACL_MAC_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(a, sizeof(*a)); + A_MEMCPY(a,acl,sizeof(*acl)); + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_ACL_MAC_LIST_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_SET_MLME + * + * This command is used to send list of mac of STAs which will + * be allowed to connect with this AP. When this list is empty + * firware will allow all STAs till the count reaches AP_MAX_NUM_STA. + */ +A_STATUS +wmi_ap_set_mlme(struct wmi_t *wmip, A_UINT8 cmd, A_UINT8 *mac, A_UINT16 reason) +{ + void *osbuf; + WMI_AP_SET_MLME_CMD *mlme; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_MLME_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_MLME_CMD)); + mlme = (WMI_AP_SET_MLME_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(mlme, sizeof(*mlme)); + + mlme->cmd = cmd; + A_MEMCPY(mlme->mac, mac, ATH_MAC_LEN); + mlme->reason = reason; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_MLME_CMDID, NO_SYNC_WMIFLAG)); +} + +static A_STATUS +wmi_pspoll_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_PSPOLL_EVENT *ev; + + if (len < sizeof(WMI_PSPOLL_EVENT)) { + return A_EINVAL; + } + ev = (WMI_PSPOLL_EVENT *)datap; + + A_WMI_PSPOLL_EVENT(wmip->wmi_devt, ev->aid); + return A_OK; +} + +static A_STATUS +wmi_dtimexpiry_event_rx(struct wmi_t *wmip, A_UINT8 *datap,int len) +{ + A_WMI_DTIMEXPIRY_EVENT(wmip->wmi_devt); + return A_OK; +} + +A_STATUS +wmi_set_pvb_cmd(struct wmi_t *wmip, A_UINT16 aid, A_BOOL flag) +{ + WMI_AP_SET_PVB_CMD *cmd; + void *osbuf = NULL; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_PVB_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_PVB_CMD)); + cmd = (WMI_AP_SET_PVB_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->aid = aid; + cmd->flag = flag; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_PVB_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_ap_conn_inact_time(struct wmi_t *wmip, A_UINT32 period) +{ + WMI_AP_CONN_INACT_CMD *cmd; + void *osbuf = NULL; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_CONN_INACT_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_CONN_INACT_CMD)); + cmd = (WMI_AP_CONN_INACT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->period = period; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_CONN_INACT_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_ap_bgscan_time(struct wmi_t *wmip, A_UINT32 period, A_UINT32 dwell) +{ + WMI_AP_PROT_SCAN_TIME_CMD *cmd; + void *osbuf = NULL; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_PROT_SCAN_TIME_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_PROT_SCAN_TIME_CMD)); + cmd = (WMI_AP_PROT_SCAN_TIME_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->period_min = period; + cmd->dwell_ms = dwell; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_PROT_SCAN_TIME_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_ap_set_dtim(struct wmi_t *wmip, A_UINT8 dtim) +{ + WMI_AP_SET_DTIM_CMD *cmd; + void *osbuf = NULL; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_DTIM_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_DTIM_CMD)); + cmd = (WMI_AP_SET_DTIM_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->dtim = dtim; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_DTIM_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_SET_ACL_POLICY + * + * This command is used to set ACL policay. While changing policy, if you + * want to retain the existing MAC addresses in the ACL list, policy should be + * OR with AP_ACL_RETAIN_LIST_MASK, else the existing list will be cleared. + * If there is no chage in policy, the list will be intact. + */ +A_STATUS +wmi_ap_set_acl_policy(struct wmi_t *wmip, A_UINT8 policy) +{ + void *osbuf; + WMI_AP_ACL_POLICY_CMD *po; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_ACL_POLICY_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_ACL_POLICY_CMD)); + po = (WMI_AP_ACL_POLICY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(po, sizeof(*po)); + + po->policy = policy; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_ACL_POLICY_CMDID, NO_SYNC_WMIFLAG)); +} + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/wmi.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wmi.h --- linux-2.6.26/drivers/net/wireless/ath6k22/wmi.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wmi.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,2255 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +/* + * This file contains the definitions of the WMI protocol specified in the + * Wireless Module Interface (WMI). It includes definitions of all the + * commands and events. Commands are messages from the host to the WM. + * Events and Replies are messages from the WM to the host. + * + * Ownership of correctness in regards to WMI commands + * belongs to the host driver and the WM is not required to validate + * parameters for value, proper range, or any other checking. + * + */ + +#ifndef _WMI_H_ +#define _WMI_H_ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#include "wmix.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HTC_PROTOCOL_VERSION 0x0002 +#define HTC_PROTOCOL_REVISION 0x0000 + +#define WMI_PROTOCOL_VERSION 0x0002 +#define WMI_PROTOCOL_REVISION 0x0000 + +#define ATH_MAC_LEN 6 /* length of mac in bytes */ +#define WMI_CMD_MAX_LEN 100 +#define WMI_CONTROL_MSG_MAX_LEN 256 +#define WMI_OPT_CONTROL_MSG_MAX_LEN 1536 +#define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600) +#define RFC1042OUI {0x00, 0x00, 0x00} + +#define IP_ETHERTYPE 0x0800 + +#define WMI_IMPLICIT_PSTREAM 0xFF +#define WMI_MAX_THINSTREAM 15 + +struct host_app_area_s { + A_UINT32 wmi_protocol_ver; +}; + +/* + * Data Path + */ +typedef PREPACK struct { + A_UINT8 dstMac[ATH_MAC_LEN]; + A_UINT8 srcMac[ATH_MAC_LEN]; + A_UINT16 typeOrLen; +} POSTPACK ATH_MAC_HDR; + +typedef PREPACK struct { + A_UINT8 dsap; + A_UINT8 ssap; + A_UINT8 cntl; + A_UINT8 orgCode[3]; + A_UINT16 etherType; +} POSTPACK ATH_LLC_SNAP_HDR; + +typedef enum { + DATA_MSGTYPE = 0x0, + CNTL_MSGTYPE, + SYNC_MSGTYPE, + OPT_MSGTYPE, +} WMI_MSG_TYPE; + + +typedef PREPACK struct { + A_INT8 rssi; + A_UINT8 info; /* WMI_MSG_TYPE in lower 2 bits - b1b0 */ + /* UP in next 3 bits - b4b3b2 */ +#define WMI_DATA_HDR_MSG_TYPE_MASK 0x03 +#define WMI_DATA_HDR_MSG_TYPE_SHIFT 0 +#define WMI_DATA_HDR_UP_MASK 0x07 +#define WMI_DATA_HDR_UP_SHIFT 2 +#define WMI_DATA_HDR_IS_MSG_TYPE(h, t) (((h)->info & (WMI_DATA_HDR_MSG_TYPE_MASK)) == (t)) +/* In AP mode, the same bit (b5) is used to indicate Power save state in + * the Rx dir and More data bit state in the tx direction. + */ +#define WMI_DATA_HDR_PS_MASK 0x1 +#define WMI_DATA_HDR_PS_SHIFT 5 + +#define WMI_DATA_HDR_MORE_MASK 0x1 +#define WMI_DATA_HDR_MORE_SHIFT 5 + +#define WMI_DATA_HDR_SET_MORE_BIT(h) ((h)->info |= (WMI_DATA_HDR_MORE_MASK << WMI_DATA_HDR_MORE_SHIFT)) + +} POSTPACK WMI_DATA_HDR; + + +#define WMI_DATA_HDR_SET_MSG_TYPE(h, t) (h)->info = (((h)->info & ~(WMI_DATA_HDR_MSG_TYPE_MASK << WMI_DATA_HDR_MSG_TYPE_SHIFT)) | (t << WMI_DATA_HDR_MSG_TYPE_SHIFT)) +#define WMI_DATA_HDR_SET_UP(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_UP_MASK << WMI_DATA_HDR_UP_SHIFT)) | (p << WMI_DATA_HDR_UP_SHIFT)) + +/* + * Control Path + */ +typedef PREPACK struct { + A_UINT16 commandId; +} POSTPACK WMI_CMD_HDR; /* used for commands and events */ + +/* + * List of Commnands + */ +typedef enum { + WMI_CONNECT_CMDID = 0x0001, + WMI_RECONNECT_CMDID, + WMI_DISCONNECT_CMDID, + WMI_SYNCHRONIZE_CMDID, + WMI_CREATE_PSTREAM_CMDID, + WMI_DELETE_PSTREAM_CMDID, + WMI_START_SCAN_CMDID, + WMI_SET_SCAN_PARAMS_CMDID, + WMI_SET_BSS_FILTER_CMDID, + WMI_SET_PROBED_SSID_CMDID, /* 10 */ + WMI_SET_LISTEN_INT_CMDID, + WMI_SET_BMISS_TIME_CMDID, + WMI_SET_DISC_TIMEOUT_CMDID, + WMI_GET_CHANNEL_LIST_CMDID, + WMI_SET_BEACON_INT_CMDID, + WMI_GET_STATISTICS_CMDID, + WMI_SET_CHANNEL_PARAMS_CMDID, + WMI_SET_POWER_MODE_CMDID, + WMI_SET_IBSS_PM_CAPS_CMDID, + WMI_SET_POWER_PARAMS_CMDID, /* 20 */ + WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID, + WMI_ADD_CIPHER_KEY_CMDID, + WMI_DELETE_CIPHER_KEY_CMDID, + WMI_ADD_KRK_CMDID, + WMI_DELETE_KRK_CMDID, + WMI_SET_PMKID_CMDID, + WMI_SET_TX_PWR_CMDID, + WMI_GET_TX_PWR_CMDID, + WMI_SET_ASSOC_INFO_CMDID, + WMI_ADD_BAD_AP_CMDID, /* 30 */ + WMI_DELETE_BAD_AP_CMDID, + WMI_SET_TKIP_COUNTERMEASURES_CMDID, + WMI_RSSI_THRESHOLD_PARAMS_CMDID, + WMI_TARGET_ERROR_REPORT_BITMASK_CMDID, + WMI_SET_ACCESS_PARAMS_CMDID, + WMI_SET_RETRY_LIMITS_CMDID, + WMI_SET_OPT_MODE_CMDID, + WMI_OPT_TX_FRAME_CMDID, + WMI_SET_VOICE_PKT_SIZE_CMDID, + WMI_SET_MAX_SP_LEN_CMDID, /* 40 */ + WMI_SET_ROAM_CTRL_CMDID, + WMI_GET_ROAM_TBL_CMDID, + WMI_GET_ROAM_DATA_CMDID, + WMI_ENABLE_RM_CMDID, + WMI_SET_MAX_OFFHOME_DURATION_CMDID, + WMI_EXTENSION_CMDID, /* Non-wireless extensions */ + WMI_SNR_THRESHOLD_PARAMS_CMDID, + WMI_LQ_THRESHOLD_PARAMS_CMDID, + WMI_SET_LPREAMBLE_CMDID, + WMI_SET_RTS_CMDID, /* 50 */ + WMI_CLR_RSSI_SNR_CMDID, + WMI_SET_FIXRATES_CMDID, + WMI_GET_FIXRATES_CMDID, + WMI_SET_AUTH_MODE_CMDID, + WMI_SET_REASSOC_MODE_CMDID, + WMI_SET_WMM_CMDID, + WMI_SET_WMM_TXOP_CMDID, + WMI_TEST_CMDID, + WMI_SET_BT_STATUS_CMDID, + WMI_SET_BT_PARAMS_CMDID, /* 60 */ + + WMI_SET_KEEPALIVE_CMDID, + WMI_GET_KEEPALIVE_CMDID, + WMI_SET_APPIE_CMDID, + WMI_GET_APPIE_CMDID, + WMI_SET_WSC_STATUS_CMDID, + + /* Wake on Wireless */ + WMI_SET_HOST_SLEEP_MODE_CMDID, + WMI_SET_WOW_MODE_CMDID, + WMI_GET_WOW_LIST_CMDID, + WMI_ADD_WOW_PATTERN_CMDID, + WMI_DEL_WOW_PATTERN_CMDID, /* 70 */ + + WMI_SET_FRAMERATES_CMDID, + /* + * Developer commands starts at 0xF000 + */ + WMI_SET_BITRATE_CMDID = 0xF000, + WMI_GET_BITRATE_CMDID, + WMI_SET_WHALPARAM_CMDID, + + + /*Should add the new command to the tail for compatible with + * etna. + */ + WMI_SET_MAC_ADDRESS_CMDID, + WMI_SET_AKMP_PARAMS_CMDID, + WMI_SET_PMKID_LIST_CMDID, + WMI_GET_PMKID_LIST_CMDID, + WMI_ABORT_SCAN_CMDID, + WMI_SET_TARGET_EVENT_REPORT_CMDID, + + // Pyxis specific Command IDs + WMI_PYXIS_CONFIG_CMDID, + WMI_PYXIS_OPERATION_CMDID, /* 0xF00A */ + + /* + * AP mode commands + */ + WMI_AP_HIDDEN_SSID_CMDID, + WMI_AP_SET_NUM_STA_CMDID, + WMI_AP_ACL_POLICY_CMDID, + WMI_AP_ACL_MAC_LIST_CMDID, + WMI_AP_CONFIG_COMMIT_CMDID, + WMI_AP_SET_MLME_CMDID, + WMI_AP_SET_PVB_CMDID, + WMI_AP_CONN_INACT_CMDID, + WMI_AP_PROT_SCAN_TIME_CMDID, + WMI_AP_SET_COUNTRY_CMDID, /* 0xF014 */ + WMI_AP_SET_DTIM_CMDID, + + WMI_SET_IP_CMDID, + WMI_SET_PARAMS_CMDID, + WMI_SET_MCAST_FILTER_CMDID, + WMI_DEL_MCAST_FILTER_CMDID +} WMI_COMMAND_ID; + +/* + * Frame Types + */ +typedef enum { + WMI_FRAME_BEACON = 0, + WMI_FRAME_PROBE_REQ, + WMI_FRAME_PROBE_RESP, + WMI_FRAME_ASSOC_REQ, + WMI_FRAME_ASSOC_RESP, + WMI_NUM_MGMT_FRAME +} WMI_MGMT_FRAME_TYPE; + +/* + * Connect Command + */ +typedef enum { + INFRA_NETWORK = 0x01, + ADHOC_NETWORK = 0x02, + ADHOC_CREATOR = 0x04, + OPT_NETWORK = 0x08, + AP_NETWORK = 0x10, +} NETWORK_TYPE; + +typedef enum { + OPEN_AUTH = 0x01, + SHARED_AUTH = 0x02, + LEAP_AUTH = 0x04, /* different from IEEE_AUTH_MODE definitions */ +} DOT11_AUTH_MODE; + +typedef enum { + NONE_AUTH = 0x01, + WPA_AUTH = 0x02, + WPA_PSK_AUTH = 0x03, + WPA2_AUTH = 0x04, + WPA2_PSK_AUTH = 0x05, + WPA_AUTH_CCKM = 0x06, + WPA2_AUTH_CCKM = 0x07, +} AUTH_MODE; + +typedef enum { + NONE_CRYPT = 0x01, + WEP_CRYPT = 0x02, + TKIP_CRYPT = 0x03, + AES_CRYPT = 0x04, +#ifdef WAPI_ENABLE + WAPI_CRYPT = 0x05, +#endif /* WAPI_ENABLE */ +} CRYPTO_TYPE; + +#define WMI_MIN_CRYPTO_TYPE NONE_CRYPT +#ifndef WAPI_ENABLE +#define WMI_MAX_CRYPTO_TYPE (AES_CRYPT + 1) +#else +#define WMI_MAX_CRYPTO_TYPE (WAPI_CRYPT + 1) +#endif /* WAPI_ENABLE */ + +#define WMI_MIN_KEY_INDEX 0 +#ifndef WAPI_ENABLE +#define WMI_MAX_KEY_INDEX 3 +#else +#define WMI_MAX_KEY_INDEX 7 /* wapi grpKey 0-3, prwKey 4-7 */ +#endif + +#define WMI_MAX_KEY_LEN 32 + +#define WMI_MAX_SSID_LEN 32 + +typedef enum { + CONNECT_ASSOC_POLICY_USER = 0x0001, + CONNECT_SEND_REASSOC = 0x0002, + CONNECT_IGNORE_WPAx_GROUP_CIPHER = 0x0004, + CONNECT_PROFILE_MATCH_DONE = 0x0008, + CONNECT_IGNORE_AAC_BEACON = 0x0010, + CONNECT_CSA_FOLLOW_BSS = 0x0020, + CONNECT_PYXIS_REMOTE = 0x0040, +} WMI_CONNECT_CTRL_FLAGS_BITS; + +#define DEFAULT_CONNECT_CTRL_FLAGS (CONNECT_CSA_FOLLOW_BSS) + +typedef PREPACK struct { + A_UINT8 networkType; + A_UINT8 dot11AuthMode; + A_UINT8 authMode; + A_UINT8 pairwiseCryptoType; + A_UINT8 pairwiseCryptoLen; + A_UINT8 groupCryptoType; + A_UINT8 groupCryptoLen; + A_UINT8 ssidLength; + A_UCHAR ssid[WMI_MAX_SSID_LEN]; + A_UINT16 channel; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT32 ctrl_flags; +} POSTPACK WMI_CONNECT_CMD; + +/* + * WMI_RECONNECT_CMDID + */ +typedef PREPACK struct { + A_UINT16 channel; /* hint */ + A_UINT8 bssid[ATH_MAC_LEN]; /* mandatory if set */ +} POSTPACK WMI_RECONNECT_CMD; + +/* + * WMI_ADD_CIPHER_KEY_CMDID + */ +typedef enum { + PAIRWISE_USAGE = 0x00, + GROUP_USAGE = 0x01, + TX_USAGE = 0x02, /* default Tx Key - Static WEP only */ +} KEY_USAGE; + +/* + * Bit Flag + * Bit 0 - Initialise TSC - default is Initialize + */ +#define KEY_OP_INIT_TSC 0x01 +#define KEY_OP_INIT_RSC 0x02 +#ifdef WAPI_ENABLE +#define KEY_OP_INIT_WAPIPN 0x10 +#endif + +#define KEY_OP_INIT_VAL 0x03 /* Default Initialise the TSC & RSC */ +#define KEY_OP_VALID_MASK 0x03 + +typedef PREPACK struct { + A_UINT8 keyIndex; + A_UINT8 keyType; + A_UINT8 keyUsage; /* KEY_USAGE */ + A_UINT8 keyLength; + A_UINT8 keyRSC[8]; /* key replay sequence counter */ + A_UINT8 key[WMI_MAX_KEY_LEN]; + A_UINT8 key_op_ctrl; /* Additional Key Control information */ + A_UINT8 key_macaddr[ATH_MAC_LEN]; +} POSTPACK WMI_ADD_CIPHER_KEY_CMD; + +/* + * WMI_DELETE_CIPHER_KEY_CMDID + */ +typedef PREPACK struct { + A_UINT8 keyIndex; +} POSTPACK WMI_DELETE_CIPHER_KEY_CMD; + +#define WMI_KRK_LEN 16 +/* + * WMI_ADD_KRK_CMDID + */ +typedef PREPACK struct { + A_UINT8 krk[WMI_KRK_LEN]; +} POSTPACK WMI_ADD_KRK_CMD; + +/* + * WMI_SET_TKIP_COUNTERMEASURES_CMDID + */ +typedef enum { + WMI_TKIP_CM_DISABLE = 0x0, + WMI_TKIP_CM_ENABLE = 0x1, +} WMI_TKIP_CM_CONTROL; + +typedef PREPACK struct { + A_UINT8 cm_en; /* WMI_TKIP_CM_CONTROL */ +} POSTPACK WMI_SET_TKIP_COUNTERMEASURES_CMD; + +/* + * WMI_SET_PMKID_CMDID + */ + +#define WMI_PMKID_LEN 16 + +typedef enum { + PMKID_DISABLE = 0, + PMKID_ENABLE = 1, +} PMKID_ENABLE_FLG; + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT8 enable; /* PMKID_ENABLE_FLG */ + A_UINT8 pmkid[WMI_PMKID_LEN]; +} POSTPACK WMI_SET_PMKID_CMD; + +/* + * WMI_START_SCAN_CMD + */ +typedef enum { + WMI_LONG_SCAN = 0, + WMI_SHORT_SCAN = 1, + WMI_PYXIS_PAS_DSCVR = 0, + WMI_PYXIS_ACT_DSCVR = 1, +} WMI_SCAN_TYPE; + +typedef PREPACK struct { + A_BOOL forceFgScan; + A_BOOL isLegacy; /* For Legacy Cisco AP compatibility */ + A_UINT32 homeDwellTime; /* Maximum duration in the home channel(milliseconds) */ + A_UINT32 forceScanInterval; /* Time interval between scans (milliseconds)*/ + A_UINT8 scanType; /* WMI_SCAN_TYPE */ + A_UINT8 numChannels; /* how many channels follow */ + A_UINT16 channelList[1]; /* channels in Mhz */ +} POSTPACK WMI_START_SCAN_CMD; + +/* + * WMI_SET_SCAN_PARAMS_CMDID + */ +#define WMI_SHORTSCANRATIO_DEFAULT 3 +typedef enum { + CONNECT_SCAN_CTRL_FLAGS = 0x01, /* set if can scan in the Connect cmd */ + SCAN_CONNECTED_CTRL_FLAGS = 0x02, /* set if scan for the SSID it is */ + /* already connected to */ + ACTIVE_SCAN_CTRL_FLAGS = 0x04, /* set if enable active scan */ + ROAM_SCAN_CTRL_FLAGS = 0x08, /* set if enable roam scan when bmiss and lowrssi */ + REPORT_BSSINFO_CTRL_FLAGS = 0x10, /* set if follows customer BSSINFO reporting rule */ + ENABLE_AUTO_CTRL_FLAGS = 0x20, /* if disabled, target doesn't + scan after a disconnect event */ + ENABLE_SCAN_ABORT_EVENT = 0x40 /* Scan complete event with canceled status will be generated when a scan is prempted before it gets completed */ + +} WMI_SCAN_CTRL_FLAGS_BITS; + +#define CAN_SCAN_IN_CONNECT(flags) (flags & CONNECT_SCAN_CTRL_FLAGS) +#define CAN_SCAN_CONNECTED(flags) (flags & SCAN_CONNECTED_CTRL_FLAGS) +#define ENABLE_ACTIVE_SCAN(flags) (flags & ACTIVE_SCAN_CTRL_FLAGS) +#define ENABLE_ROAM_SCAN(flags) (flags & ROAM_SCAN_CTRL_FLAGS) +#define CONFIG_REPORT_BSSINFO(flags) (flags & REPORT_BSSINFO_CTRL_FLAGS) +#define IS_AUTO_SCAN_ENABLED(flags) (flags & ENABLE_AUTO_CTRL_FLAGS) +#define SCAN_ABORT_EVENT_ENABLED(flags) (flags & ENABLE_SCAN_ABORT_EVENT) + +#define DEFAULT_SCAN_CTRL_FLAGS (CONNECT_SCAN_CTRL_FLAGS| SCAN_CONNECTED_CTRL_FLAGS| ACTIVE_SCAN_CTRL_FLAGS| ROAM_SCAN_CTRL_FLAGS | ENABLE_AUTO_CTRL_FLAGS) + + +typedef PREPACK struct { + A_UINT16 fg_start_period; /* seconds */ + A_UINT16 fg_end_period; /* seconds */ + A_UINT16 bg_period; /* seconds */ + A_UINT16 maxact_chdwell_time; /* msec */ + A_UINT16 pas_chdwell_time; /* msec */ + A_UINT8 shortScanRatio; /* how many shorts scan for one long */ + A_UINT8 scanCtrlFlags; + A_UINT16 minact_chdwell_time; /* msec */ + A_UINT16 maxact_scan_per_ssid; /* max active scans per ssid */ + A_UINT32 max_dfsch_act_time; /* msecs */ +} POSTPACK WMI_SCAN_PARAMS_CMD; + +/* + * WMI_SET_BSS_FILTER_CMDID + */ +typedef enum { + NONE_BSS_FILTER = 0x0, /* no beacons forwarded */ + ALL_BSS_FILTER, /* all beacons forwarded */ + PROFILE_FILTER, /* only beacons matching profile */ + ALL_BUT_PROFILE_FILTER, /* all but beacons matching profile */ + CURRENT_BSS_FILTER, /* only beacons matching current BSS */ + ALL_BUT_BSS_FILTER, /* all but beacons matching BSS */ + PROBED_SSID_FILTER, /* beacons matching probed ssid */ + LAST_BSS_FILTER, /* marker only */ +} WMI_BSS_FILTER; + +typedef PREPACK struct { + A_UINT8 bssFilter; /* see WMI_BSS_FILTER */ + A_UINT8 reserved1; /* For alignment */ + A_UINT16 reserved2; /* For alignment */ + A_UINT32 ieMask; +} POSTPACK WMI_BSS_FILTER_CMD; + +/* + * WMI_SET_PROBED_SSID_CMDID + */ +#define MAX_PROBED_SSID_INDEX 5 + +typedef enum { + DISABLE_SSID_FLAG = 0, /* disables entry */ + SPECIFIC_SSID_FLAG = 0x01, /* probes specified ssid */ + ANY_SSID_FLAG = 0x02, /* probes for any ssid */ +} WMI_SSID_FLAG; + +typedef PREPACK struct { + A_UINT8 entryIndex; /* 0 to MAX_PROBED_SSID_INDEX */ + A_UINT8 flag; /* WMI_SSID_FLG */ + A_UINT8 ssidLength; + A_UINT8 ssid[32]; +} POSTPACK WMI_PROBED_SSID_CMD; + +/* + * WMI_SET_LISTEN_INT_CMDID + * The Listen interval is between 15 and 3000 TUs + */ +#define MIN_LISTEN_INTERVAL 15 +#define MAX_LISTEN_INTERVAL 5000 +#define MIN_LISTEN_BEACONS 1 +#define MAX_LISTEN_BEACONS 50 + +typedef PREPACK struct { + A_UINT16 listenInterval; + A_UINT16 numBeacons; +} POSTPACK WMI_LISTEN_INT_CMD; + +/* + * WMI_SET_BEACON_INT_CMDID + */ +typedef PREPACK struct { + A_UINT16 beaconInterval; +} POSTPACK WMI_BEACON_INT_CMD; + +/* + * WMI_SET_BMISS_TIME_CMDID + * valid values are between 1000 and 5000 TUs + */ + +#define MIN_BMISS_TIME 1000 +#define MAX_BMISS_TIME 5000 +#define MIN_BMISS_BEACONS 1 +#define MAX_BMISS_BEACONS 50 + +typedef PREPACK struct { + A_UINT16 bmissTime; + A_UINT16 numBeacons; +} POSTPACK WMI_BMISS_TIME_CMD; + +/* + * WMI_SET_POWER_MODE_CMDID + */ +typedef enum { + REC_POWER = 0x01, + MAX_PERF_POWER, +} WMI_POWER_MODE; + +typedef PREPACK struct { + A_UINT8 powerMode; /* WMI_POWER_MODE */ +} POSTPACK WMI_POWER_MODE_CMD; + +typedef PREPACK struct { + A_INT8 status; /* WMI_SET_PARAMS_REPLY */ +} POSTPACK WMI_SET_PARAMS_REPLY; + +typedef PREPACK struct { + A_UINT32 opcode; + A_UINT32 length; + A_CHAR buffer[1]; /* WMI_SET_PARAMS */ +} POSTPACK WMI_SET_PARAMS_CMD; + +typedef PREPACK struct { + A_UINT8 multicast_mac[ATH_MAC_LEN]; /* WMI_SET_MCAST_FILTER */ +} POSTPACK WMI_SET_MCAST_FILTER_CMD; + +/* + * WMI_SET_POWER_PARAMS_CMDID + */ +typedef enum { + IGNORE_DTIM = 0x01, + NORMAL_DTIM = 0x02, + STICK_DTIM = 0x03, +} WMI_DTIM_POLICY; + +typedef PREPACK struct { + A_UINT16 idle_period; /* msec */ + A_UINT16 pspoll_number; + A_UINT16 dtim_policy; +} POSTPACK WMI_POWER_PARAMS_CMD; + +typedef PREPACK struct { + A_UINT8 power_saving; + A_UINT8 ttl; /* number of beacon periods */ + A_UINT16 atim_windows; /* msec */ + A_UINT16 timeout_value; /* msec */ +} POSTPACK WMI_IBSS_PM_CAPS_CMD; + +/* + * WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID + */ +typedef enum { + IGNORE_TIM_ALL_QUEUES_APSD = 0, + PROCESS_TIM_ALL_QUEUES_APSD = 1, + IGNORE_TIM_SIMULATED_APSD = 2, + PROCESS_TIM_SIMULATED_APSD = 3, +} APSD_TIM_POLICY; + +typedef PREPACK struct { + A_UINT16 psPollTimeout; /* msec */ + A_UINT16 triggerTimeout; /* msec */ + A_UINT32 apsdTimPolicy; /* TIM behavior with ques APSD enabled. Default is IGNORE_TIM_ALL_QUEUES_APSD */ + A_UINT32 simulatedAPSDTimPolicy; /* TIM behavior with simulated APSD enabled. Default is PROCESS_TIM_SIMULATED_APSD */ +} POSTPACK WMI_POWERSAVE_TIMERS_POLICY_CMD; + +/* + * WMI_SET_VOICE_PKT_SIZE_CMDID + */ +typedef PREPACK struct { + A_UINT16 voicePktSize; +} POSTPACK WMI_SET_VOICE_PKT_SIZE_CMD; + +/* + * WMI_SET_MAX_SP_LEN_CMDID + */ +typedef enum { + DELIVER_ALL_PKT = 0x0, + DELIVER_2_PKT = 0x1, + DELIVER_4_PKT = 0x2, + DELIVER_6_PKT = 0x3, +} APSD_SP_LEN_TYPE; + +typedef PREPACK struct { + A_UINT8 maxSPLen; +} POSTPACK WMI_SET_MAX_SP_LEN_CMD; + +/* + * WMI_SET_DISC_TIMEOUT_CMDID + */ +typedef PREPACK struct { + A_UINT8 disconnectTimeout; /* seconds */ +} POSTPACK WMI_DISC_TIMEOUT_CMD; + +typedef enum { + UPLINK_TRAFFIC = 0, + DNLINK_TRAFFIC = 1, + BIDIR_TRAFFIC = 2, +} DIR_TYPE; + +typedef enum { + DISABLE_FOR_THIS_AC = 0, + ENABLE_FOR_THIS_AC = 1, + ENABLE_FOR_ALL_AC = 2, +} VOICEPS_CAP_TYPE; + +typedef enum { + TRAFFIC_TYPE_APERIODIC = 0, + TRAFFIC_TYPE_PERIODIC = 1, +}TRAFFIC_TYPE; + +/* + * WMI_SYNCHRONIZE_CMDID + */ +typedef PREPACK struct { + A_UINT8 dataSyncMap; +} POSTPACK WMI_SYNC_CMD; + +/* + * WMI_CREATE_PSTREAM_CMDID + */ +typedef PREPACK struct { + A_UINT32 minServiceInt; /* in milli-sec */ + A_UINT32 maxServiceInt; /* in milli-sec */ + A_UINT32 inactivityInt; /* in milli-sec */ + A_UINT32 suspensionInt; /* in milli-sec */ + A_UINT32 serviceStartTime; + A_UINT32 minDataRate; /* in bps */ + A_UINT32 meanDataRate; /* in bps */ + A_UINT32 peakDataRate; /* in bps */ + A_UINT32 maxBurstSize; + A_UINT32 delayBound; + A_UINT32 minPhyRate; /* in bps */ + A_UINT32 sba; + A_UINT32 mediumTime; + A_UINT16 nominalMSDU; /* in octects */ + A_UINT16 maxMSDU; /* in octects */ + A_UINT8 trafficClass; + A_UINT8 trafficDirection; /* DIR_TYPE */ + A_UINT8 rxQueueNum; + A_UINT8 trafficType; /* TRAFFIC_TYPE */ + A_UINT8 voicePSCapability; /* VOICEPS_CAP_TYPE */ + A_UINT8 tsid; + A_UINT8 userPriority; /* 802.1D user priority */ + A_UINT8 nominalPHY; /* nominal phy rate */ +} POSTPACK WMI_CREATE_PSTREAM_CMD; + +/* + * WMI_DELETE_PSTREAM_CMDID + */ +typedef PREPACK struct { + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficDirection; + A_UINT8 trafficClass; + A_UINT8 tsid; +} POSTPACK WMI_DELETE_PSTREAM_CMD; + +/* + * WMI_SET_CHANNEL_PARAMS_CMDID + */ +typedef enum { + WMI_11A_MODE = 0x1, + WMI_11G_MODE = 0x2, + WMI_11AG_MODE = 0x3, + WMI_11B_MODE = 0x4, + WMI_11GONLY_MODE = 0x5, +} WMI_PHY_MODE; + +#define WMI_MAX_CHANNELS 32 + +typedef PREPACK struct { + A_UINT8 reserved1; + A_UINT8 scanParam; /* set if enable scan */ + A_UINT8 phyMode; /* see WMI_PHY_MODE */ + A_UINT8 numChannels; /* how many channels follow */ + A_UINT16 channelList[1]; /* channels in Mhz */ +} POSTPACK WMI_CHANNEL_PARAMS_CMD; + + +/* + * WMI_RSSI_THRESHOLD_PARAMS_CMDID + * Setting the polltime to 0 would disable polling. + * Threshold values are in the ascending order, and should agree to: + * (lowThreshold_lowerVal < lowThreshold_upperVal < highThreshold_lowerVal + * < highThreshold_upperVal) + */ + +typedef PREPACK struct WMI_RSSI_THRESHOLD_PARAMS{ + A_UINT32 pollTime; /* Polling time as a factor of LI */ + A_INT16 thresholdAbove1_Val; /* lowest of upper */ + A_INT16 thresholdAbove2_Val; + A_INT16 thresholdAbove3_Val; + A_INT16 thresholdAbove4_Val; + A_INT16 thresholdAbove5_Val; + A_INT16 thresholdAbove6_Val; /* highest of upper */ + A_INT16 thresholdBelow1_Val; /* lowest of bellow */ + A_INT16 thresholdBelow2_Val; + A_INT16 thresholdBelow3_Val; + A_INT16 thresholdBelow4_Val; + A_INT16 thresholdBelow5_Val; + A_INT16 thresholdBelow6_Val; /* highest of bellow */ + A_UINT8 weight; /* "alpha" */ + A_UINT8 reserved[3]; +} POSTPACK WMI_RSSI_THRESHOLD_PARAMS_CMD; + +/* + * WMI_SNR_THRESHOLD_PARAMS_CMDID + * Setting the polltime to 0 would disable polling. + */ + +typedef PREPACK struct WMI_SNR_THRESHOLD_PARAMS{ + A_UINT32 pollTime; /* Polling time as a factor of LI */ + A_UINT8 weight; /* "alpha" */ + A_UINT8 thresholdAbove1_Val; /* lowest of uppper*/ + A_UINT8 thresholdAbove2_Val; + A_UINT8 thresholdAbove3_Val; + A_UINT8 thresholdAbove4_Val; /* highest of upper */ + A_UINT8 thresholdBelow1_Val; /* lowest of bellow */ + A_UINT8 thresholdBelow2_Val; + A_UINT8 thresholdBelow3_Val; + A_UINT8 thresholdBelow4_Val; /* highest of bellow */ + A_UINT8 reserved[3]; +} POSTPACK WMI_SNR_THRESHOLD_PARAMS_CMD; + +/* + * WMI_LQ_THRESHOLD_PARAMS_CMDID + */ +typedef PREPACK struct WMI_LQ_THRESHOLD_PARAMS { + A_UINT8 enable; + A_UINT8 thresholdAbove1_Val; + A_UINT8 thresholdAbove2_Val; + A_UINT8 thresholdAbove3_Val; + A_UINT8 thresholdAbove4_Val; + A_UINT8 thresholdBelow1_Val; + A_UINT8 thresholdBelow2_Val; + A_UINT8 thresholdBelow3_Val; + A_UINT8 thresholdBelow4_Val; + A_UINT8 reserved[3]; +} POSTPACK WMI_LQ_THRESHOLD_PARAMS_CMD; + +typedef enum { + WMI_LPREAMBLE_DISABLED = 0, + WMI_LPREAMBLE_ENABLED +} WMI_LPREAMBLE_STATUS; + +typedef PREPACK struct { + A_UINT8 status; +}POSTPACK WMI_SET_LPREAMBLE_CMD; + +typedef PREPACK struct { + A_UINT16 threshold; +}POSTPACK WMI_SET_RTS_CMD; + +/* + * WMI_TARGET_ERROR_REPORT_BITMASK_CMDID + * Sets the error reporting event bitmask in target. Target clears it + * upon an error. Subsequent errors are counted, but not reported + * via event, unless the bitmask is set again. + */ +typedef PREPACK struct { + A_UINT32 bitmask; +} POSTPACK WMI_TARGET_ERROR_REPORT_BITMASK; + +/* + * WMI_SET_TX_PWR_CMDID + */ +typedef PREPACK struct { + A_UINT8 dbM; /* in dbM units */ +} POSTPACK WMI_SET_TX_PWR_CMD, WMI_TX_PWR_REPLY; + +/* + * WMI_SET_ASSOC_INFO_CMDID + * + * A maximum of 2 private IEs can be sent in the [Re]Assoc request. + * A 3rd one, the CCX version IE can also be set from the host. + */ +#define WMI_MAX_ASSOC_INFO_TYPE 2 +#define WMI_CCX_VER_IE 2 /* ieType to set CCX Version IE */ + +#define WMI_MAX_ASSOC_INFO_LEN 240 + +typedef PREPACK struct { + A_UINT8 ieType; + A_UINT8 bufferSize; + A_UINT8 assocInfo[1]; /* up to WMI_MAX_ASSOC_INFO_LEN */ +} POSTPACK WMI_SET_ASSOC_INFO_CMD; + + +/* + * WMI_GET_TX_PWR_CMDID does not take any parameters + */ + +/* + * WMI_ADD_BAD_AP_CMDID + */ +#define WMI_MAX_BAD_AP_INDEX 1 + +typedef PREPACK struct { + A_UINT8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */ + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_ADD_BAD_AP_CMD; + +/* + * WMI_DELETE_BAD_AP_CMDID + */ +typedef PREPACK struct { + A_UINT8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */ +} POSTPACK WMI_DELETE_BAD_AP_CMD; + +/* + * WMI_SET_ACCESS_PARAMS_CMDID + */ +#define WMI_DEFAULT_TXOP_ACPARAM 0 /* implies one MSDU */ +#define WMI_DEFAULT_ECWMIN_ACPARAM 4 /* corresponds to CWmin of 15 */ +#define WMI_DEFAULT_ECWMAX_ACPARAM 10 /* corresponds to CWmax of 1023 */ +#define WMI_MAX_CW_ACPARAM 15 /* maximum eCWmin or eCWmax */ +#define WMI_DEFAULT_AIFSN_ACPARAM 2 +#define WMI_MAX_AIFSN_ACPARAM 15 +typedef PREPACK struct { + A_UINT16 txop; /* in units of 32 usec */ + A_UINT8 eCWmin; + A_UINT8 eCWmax; + A_UINT8 aifsn; +} POSTPACK WMI_SET_ACCESS_PARAMS_CMD; + + +/* + * WMI_SET_RETRY_LIMITS_CMDID + * + * This command is used to customize the number of retries the + * wlan device will perform on a given frame. + */ +#define WMI_MIN_RETRIES 2 +#define WMI_MAX_RETRIES 13 +typedef enum { + MGMT_FRAMETYPE = 0, + CONTROL_FRAMETYPE = 1, + DATA_FRAMETYPE = 2 +} WMI_FRAMETYPE; + +typedef PREPACK struct { + A_UINT8 frameType; /* WMI_FRAMETYPE */ + A_UINT8 trafficClass; /* applies only to DATA_FRAMETYPE */ + A_UINT8 maxRetries; + A_UINT8 enableNotify; +} POSTPACK WMI_SET_RETRY_LIMITS_CMD; + +/* + * WMI_SET_ROAM_CTRL_CMDID + * + * This command is used to influence the Roaming behaviour + * Set the host biases of the BSSs before setting the roam mode as bias + * based. + */ + +/* + * Different types of Roam Control + */ + +typedef enum { + WMI_FORCE_ROAM = 1, /* Roam to the specified BSSID */ + WMI_SET_ROAM_MODE = 2, /* default ,progd bias, no roam */ + WMI_SET_HOST_BIAS = 3, /* Set the Host Bias */ + WMI_SET_LOWRSSI_SCAN_PARAMS = 4, /* Set lowrssi Scan parameters */ +} WMI_ROAM_CTRL_TYPE; + +#define WMI_MIN_ROAM_CTRL_TYPE WMI_FORCE_ROAM +#define WMI_MAX_ROAM_CTRL_TYPE WMI_SET_LOWRSSI_SCAN_PARAMS + +/* + * ROAM MODES + */ + +typedef enum { + WMI_DEFAULT_ROAM_MODE = 1, /* RSSI based ROAM */ + WMI_HOST_BIAS_ROAM_MODE = 2, /* HOST BIAS based ROAM */ + WMI_LOCK_BSS_MODE = 3 /* Lock to the Current BSS - no Roam */ +} WMI_ROAM_MODE; + +/* + * BSS HOST BIAS INFO + */ + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_INT8 bias; +} POSTPACK WMI_BSS_BIAS; + +typedef PREPACK struct { + A_UINT8 numBss; + WMI_BSS_BIAS bssBias[1]; +} POSTPACK WMI_BSS_BIAS_INFO; + +typedef PREPACK struct WMI_LOWRSSI_SCAN_PARAMS { + A_UINT16 lowrssi_scan_period; + A_INT16 lowrssi_scan_threshold; + A_INT16 lowrssi_roam_threshold; + A_UINT8 roam_rssi_floor; + A_UINT8 reserved[1]; /* For alignment */ +} POSTPACK WMI_LOWRSSI_SCAN_PARAMS; + +typedef PREPACK struct { + PREPACK union { + A_UINT8 bssid[ATH_MAC_LEN]; /* WMI_FORCE_ROAM */ + A_UINT8 roamMode; /* WMI_SET_ROAM_MODE */ + WMI_BSS_BIAS_INFO bssBiasInfo; /* WMI_SET_HOST_BIAS */ + WMI_LOWRSSI_SCAN_PARAMS lrScanParams; + } POSTPACK info; + A_UINT8 roamCtrlType ; +} POSTPACK WMI_SET_ROAM_CTRL_CMD; + +/* + * WMI_ENABLE_RM_CMDID + */ +typedef PREPACK struct { + A_BOOL enable_radio_measurements; +} POSTPACK WMI_ENABLE_RM_CMD; + +/* + * WMI_SET_MAX_OFFHOME_DURATION_CMDID + */ +typedef PREPACK struct { + A_UINT8 max_offhome_duration; +} POSTPACK WMI_SET_MAX_OFFHOME_DURATION_CMD; + +typedef PREPACK struct { + A_UINT32 frequency; + A_UINT8 threshold; +} POSTPACK WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD; + +typedef enum { + BT_STREAM_UNDEF = 0, + BT_STREAM_SCO, /* SCO stream */ + BT_STREAM_A2DP, /* A2DP stream */ + BT_STREAM_SCAN, /* BT Discovery or Page */ + BT_STREAM_ESCO, + BT_STREAM_MAX +} BT_STREAM_TYPE; + +typedef enum { + BT_PARAM_SCO = 1, /* SCO stream parameters */ + BT_PARAM_A2DP , + BT_PARAM_ANTENNA_CONFIG, + BT_PARAM_COLOCATED_BT_DEVICE, + BT_PARAM_ACLCOEX, + BT_PARAM_11A_SEPARATE_ANT, + BT_PARAM_MAX +} BT_PARAM_TYPE; + +typedef enum { + BT_PARAM_SCO_PSPOLL_LATENCY_ONE_FOURTH =1, + BT_PARAM_SCO_PSPOLL_LATENCY_HALF, + BT_PARAM_SCO_PSPOLL_LATENCY_THREE_FOURTH, +} BT_PARAMS_SCO_PSPOLL_LATENCY; + +typedef enum { + BT_PARAMS_SCO_STOMP_SCO_NEVER =1, + BT_PARAMS_SCO_STOMP_SCO_ALWAYS, + BT_PARAMS_SCO_STOMP_SCO_IN_LOWRSSI, +} BT_PARAMS_SCO_STOMP_RULES; + +typedef enum { + BT_STATUS_UNDEF = 0, + BT_STATUS_START, + BT_STATUS_STOP, + BT_STATUS_RESUME, + BT_STATUS_SUSPEND, + BT_STATUS_MAX +} BT_STREAM_STATUS; + +typedef PREPACK struct { + A_UINT8 streamType; + A_UINT8 status; +} POSTPACK WMI_SET_BT_STATUS_CMD; + +typedef enum { + BT_ANT_TYPE_UNDEF=0, + BT_ANT_TYPE_DUAL, + BT_ANT_TYPE_SPLITTER, + BT_ANT_TYPE_SWITCH +} BT_ANT_FRONTEND_CONFIG; + +typedef enum { + BT_COLOCATED_DEV_BTS4020=0, + BT_COLCATED_DEV_CSR , + BT_COLOCATED_DEV_VALKYRIE +} BT_COLOCATED_DEV_TYPE; + +#define BT_SCO_ALLOW_CLOSE_RANGE_OPT (1 << 0) +#define BT_SCO_FORCE_AWAKE_OPT (1 << 1) +#define BT_SCO_SET_DEFAULT_OVERRIDE(flags) ((flags) |= (1 << 2)) +#define BT_SCO_GET_DEFAULT_OVERRIDE(flags) (((flags) >> 2) & 0x1) +typedef PREPACK struct { + A_UINT32 numScoCyclesForceTrigger; /* Number SCO cycles after which + force a pspoll. default = 10 */ + A_UINT32 dataResponseTimeout; /* Timeout Waiting for Downlink pkt + in response for ps-poll, + default = 10 msecs */ + A_UINT32 stompScoRules; + A_UINT32 scoOptFlags; /* SCO Options Flags : + bits: meaning: + 0 Allow Close Range Optimization + 1 Force awake during close range + 2 If set use host supplied threshold + 3 Unused + 4..7 Unused + 8..15 Unused + 16..23 Unused + */ + A_UINT32 p2lrpOptModeBound; /*p2lrp=packetToLowRatePacketRatio. In opt mode + minimum ratio required to continue in opt mode*/ + A_UINT32 p2lrpNonOptModeBound; /*In Non opt mode minimum ratio required to switch + to opt mode*/ + A_UINT8 stompDutyCyleVal; /* Sco cycles to limit ps-poll queuing + if stomped */ + A_UINT8 stompDutyCyleMaxVal; /*firm ware increases stomp duty cycle + gradually uptill this value on need basis*/ + A_UINT8 psPollLatencyFraction; /* Fraction of idle + period, within which + additional ps-polls + can be queued */ + A_UINT8 noSCOSlots; /* Number of SCO Tx/Rx slots. + HVx, EV3, 2EV3 = 2 */ + A_UINT8 noIdleSlots; /* Number of Bluetooth idle slots between + consecutive SCO Tx/Rx slots + HVx, EV3 = 4 + 2EV3 = 10 */ + A_UINT8 reserved8; /* maintain word algnment*/ +} POSTPACK BT_PARAMS_SCO; + +#define BT_A2DP_ALLOW_CLOSE_RANGE_OPT (1 << 0) +#define BT_A2DP_FORCE_AWAKE_OPT (1 << 1) +#define BT_A2DP_SET_DEFAULT_OVERRIDE(flags) ((flags) |= (1 << 2)) +#define BT_A2DP_GET_DEFAULT_OVERRIDE(flags) (((flags) >> 2) & 0x1) +typedef PREPACK struct { + A_UINT32 a2dpWlanUsageLimit; /* MAX time firmware uses the medium for + wlan, after it identifies the idle time + default (30 msecs) */ + A_UINT32 a2dpBurstCntMin; /* Minimum number of bluetooth data frames + to replenish Wlan Usage limit (default 3) */ + A_UINT32 a2dpDataRespTimeout; + A_UINT32 a2dpOptFlags; /* A2DP Option flags: + bits: meaning: + 0 Allow Close Range Optimization + 1 Force awake during close range + 2 If set use host threshold + 3 Unused + 4..7 Unused + 8..15 Unused + 16..23 Unused + */ + A_UINT32 p2lrpOptModeBound; /*p2lrp=packetToLowRatePacketRatio. In opt mode + minimum ratio required to continue in opt mode*/ + A_UINT32 p2lrpNonOptModeBound; /*In Non opt mode minimum ratio required to switch + to opt mode*/ + A_UINT16 reserved16; /*maintain word alignment*/ + A_UINT8 isCoLocatedBtRoleMaster; + A_UINT8 reserved8; /*maintain word alignment*/ +}POSTPACK BT_PARAMS_A2DP; + +/* During BT ftp/ BT OPP or any another data based acl profile on bluetooth + (non a2dp).*/ +typedef PREPACK struct { + A_UINT32 aclWlanMediumUsageTime; /* Wlan usage time during Acl (non-a2dp) + coexistence (default 30 msecs) */ + A_UINT32 aclBtMediumUsageTime; /* Bt usage time during acl coexistence + (default 30 msecs)*/ + A_UINT32 aclDataRespTimeout; + A_UINT32 aclDetectTimeout; /* ACL coexistence enabled if we get + 10 Pkts in X msec(default 100 msecs) */ + A_UINT32 aclmaxPktCnt; /* No of ACL pkts to receive before + enabling ACL coex */ + +}POSTPACK BT_PARAMS_ACLCOEX; + +typedef PREPACK struct { + A_UINT32 mode; + A_UINT32 scoWghts; + A_UINT32 a2dpWghts; + A_UINT32 genWghts; + A_UINT32 mode2; + A_UINT8 setVal; +} POSTPACK BT_COEX_REGS; + +typedef enum { + WLAN_PROTECT_POLICY = 1, + WLAN_COEX_CTRL_FLAGS +} BT_PARAMS_MISC_TYPE; + +typedef enum { + WLAN_PROTECT_PER_STREAM = 0x01, /* default */ + WLAN_PROTECT_ANY_TX = 0x02 +} WLAN_PROTECT_FLAGS; + + +#define WLAN_DISABLE_COEX_IN_DISCONNECT 0x01 /* default */ +#define WLAN_KEEP_COEX_IN_DISCONNECT 0x02 +#define WLAN_STOMPBT_IN_DISCONNECT 0x04 + +#define WLAN_DISABLE_COEX_IN_ROAM 0x10 /* default */ +#define WLAN_KEEP_COEX_IN_ROAM 0x20 +#define WLAN_STOMPBT_IN_ROAM 0x40 + +#define WLAN_DISABLE_COEX_IN_SCAN 0x100 /* default */ +#define WLAN_KEEP_COEX_IN_SCAN 0x200 +#define WLAN_STOMPBT_IN_SCAN 0x400 + +#define WLAN_DISABLE_COEX_BT_OFF 0x1000 /* default */ +#define WLAN_KEEP_COEX_BT_OFF 0x2000 +#define WLAN_STOMPBT_BT_OFF 0x4000 + +typedef PREPACK struct { + A_UINT32 period; + A_UINT32 dutycycle; + A_UINT8 stompbt; + A_UINT8 policy; +} POSTPACK WLAN_PROTECT_POLICY_TYPE; + +typedef PREPACK struct { + PREPACK union { + WLAN_PROTECT_POLICY_TYPE protectParams; + A_UINT16 configCtrlFlags; + } POSTPACK info; + A_UINT8 paramType; +} POSTPACK BT_PARAMS_MISC; + +typedef PREPACK struct { + PREPACK union { + BT_PARAMS_SCO scoParams; + BT_PARAMS_A2DP a2dpParams; + BT_PARAMS_ACLCOEX aclCoexParams; + A_UINT8 antType; /* 0 -Disabled (default) + 1 - BT_ANT_TYPE_DUAL + 2 - BT_ANT_TYPE_SPLITTER + 3 - BT_ANT_TYPE_SWITCH */ + A_UINT8 coLocatedBtDev; /* 0 - BT_COLOCATED_DEV_BTS4020 (default) + 1 - BT_COLCATED_DEV_CSR + 2 - BT_COLOCATED_DEV_VALKYRIe + */ + } POSTPACK info; + A_UINT8 paramType ; +} POSTPACK WMI_SET_BT_PARAMS_CMD; + +typedef enum { + DISCONN_EVT_IN_RECONN = 0, /* default */ + NO_DISCONN_EVT_IN_RECONN +} TARGET_EVENT_REPORT_CONFIG; + +typedef PREPACK struct { + A_UINT32 evtConfig; +} POSTPACK WMI_SET_TARGET_EVENT_REPORT_CMD; + + +/* + * Command Replies + */ + +/* + * WMI_GET_CHANNEL_LIST_CMDID reply + */ +typedef PREPACK struct { + A_UINT8 reserved1; + A_UINT8 numChannels; /* number of channels in reply */ + A_UINT16 channelList[1]; /* channel in Mhz */ +} POSTPACK WMI_CHANNEL_LIST_REPLY; + +typedef enum { + A_SUCCEEDED = A_OK, + A_FAILED_DELETE_STREAM_DOESNOT_EXIST=250, + A_SUCCEEDED_MODIFY_STREAM=251, + A_FAILED_INVALID_STREAM = 252, + A_FAILED_MAX_THINSTREAMS = 253, + A_FAILED_CREATE_REMOVE_PSTREAM_FIRST = 254, +} PSTREAM_REPLY_STATUS; + +typedef PREPACK struct { + A_UINT8 status; /* PSTREAM_REPLY_STATUS */ + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficClass; + A_UINT8 trafficDirection; /* DIR_TYPE */ +} POSTPACK WMI_CRE_PRIORITY_STREAM_REPLY; + +typedef PREPACK struct { + A_UINT8 status; /* PSTREAM_REPLY_STATUS */ + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficDirection; /* DIR_TYPE */ + A_UINT8 trafficClass; +} POSTPACK WMI_DEL_PRIORITY_STREAM_REPLY; + +/* + * List of Events (target to host) + */ +typedef enum { + WMI_READY_EVENTID = 0x1001, + WMI_CONNECT_EVENTID, + WMI_DISCONNECT_EVENTID, + WMI_BSSINFO_EVENTID, + WMI_CMDERROR_EVENTID, + WMI_REGDOMAIN_EVENTID, + WMI_PSTREAM_TIMEOUT_EVENTID, + WMI_NEIGHBOR_REPORT_EVENTID, + WMI_TKIP_MICERR_EVENTID, + WMI_SCAN_COMPLETE_EVENTID, /* 0x100a */ + WMI_REPORT_STATISTICS_EVENTID, + WMI_RSSI_THRESHOLD_EVENTID, + WMI_ERROR_REPORT_EVENTID, + WMI_OPT_RX_FRAME_EVENTID, + WMI_REPORT_ROAM_TBL_EVENTID, + WMI_EXTENSION_EVENTID, + WMI_CAC_EVENTID, + WMI_SNR_THRESHOLD_EVENTID, + WMI_LQ_THRESHOLD_EVENTID, + WMI_TX_RETRY_ERR_EVENTID, /* 0x1014 */ + WMI_REPORT_ROAM_DATA_EVENTID, + WMI_TEST_EVENTID, + WMI_APLIST_EVENTID, + WMI_GET_WOW_LIST_EVENTID, + WMI_GET_PMKID_LIST_EVENTID, + WMI_CHANNEL_CHANGE_EVENTID, + WMI_PEER_NODE_EVENTID, + WMI_PSPOLL_EVENTID, + WMI_DTIMEXPIRY_EVENTID, + WMI_WLAN_VERSION_EVENTID, + WMI_SET_PARAMS_REPLY_EVENTID +} WMI_EVENT_ID; + +typedef enum { + WMI_11A_CAPABILITY = 1, + WMI_11G_CAPABILITY = 2, + WMI_11AG_CAPABILITY = 3, +} WMI_PHY_CAPABILITY; + +typedef PREPACK struct { + A_UINT8 macaddr[ATH_MAC_LEN]; + A_UINT8 phyCapability; /* WMI_PHY_CAPABILITY */ +} POSTPACK WMI_READY_EVENT_1; + +typedef PREPACK struct { + A_UINT32 version; + A_UINT8 macaddr[ATH_MAC_LEN]; + A_UINT8 phyCapability; /* WMI_PHY_CAPABILITY */ +} POSTPACK WMI_READY_EVENT_2; + +#if defined(ATH_TARGET) +#ifdef AR6002_REV2 +#define WMI_READY_EVENT WMI_READY_EVENT_1 /* AR6002_REV2 target code */ +#else +#define WMI_READY_EVENT WMI_READY_EVENT_2 /* AR6002_REV4 and AR6001 */ +#endif +#else +#define WMI_READY_EVENT WMI_READY_EVENT_2 /* host code */ +#endif + + +/* + * Connect Event + */ +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT16 listenInterval; + A_UINT16 beaconInterval; + A_UINT32 networkType; + A_UINT8 beaconIeLen; + A_UINT8 assocReqLen; + A_UINT8 assocRespLen; + A_UINT8 assocInfo[1]; +} POSTPACK WMI_CONNECT_EVENT; + +/* + * Disconnect Event + */ +typedef enum { + NO_NETWORK_AVAIL = 0x01, + LOST_LINK = 0x02, /* bmiss */ + DISCONNECT_CMD = 0x03, + BSS_DISCONNECTED = 0x04, + AUTH_FAILED = 0x05, + ASSOC_FAILED = 0x06, + NO_RESOURCES_AVAIL = 0x07, + CSERV_DISCONNECT = 0x08, + INVALID_PROFILE = 0x0a, + DOT11H_CHANNEL_SWITCH = 0x0b, + PROFILE_MISMATCH = 0x0c, + PYXIS_VIRT_ADHOC_DISC = 0x0d, +} WMI_DISCONNECT_REASON; + +typedef PREPACK struct { + A_UINT16 protocolReasonStatus; /* reason code, see 802.11 spec. */ + A_UINT8 bssid[ATH_MAC_LEN]; /* set if known */ + A_UINT8 disconnectReason ; /* see WMI_DISCONNECT_REASON */ + A_UINT8 assocRespLen; + A_UINT8 assocInfo[1]; +} POSTPACK WMI_DISCONNECT_EVENT; + +/* + * BSS Info Event. + * Mechanism used to inform host of the presence and characteristic of + * wireless networks present. Consists of bss info header followed by + * the beacon or probe-response frame body. The 802.11 header is not included. + */ +typedef enum { + BEACON_FTYPE = 0x1, + PROBERESP_FTYPE, + ACTION_MGMT_FTYPE, + PROBEREQ_FTYPE, +} WMI_BI_FTYPE; + +enum { + BSS_ELEMID_CHANSWITCH = 0x01, + BSS_ELEMID_ATHEROS = 0x02, +}; + +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 frameType; /* see WMI_BI_FTYPE */ + A_UINT8 snr; + A_INT16 rssi; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT32 ieMask; +} POSTPACK WMI_BSS_INFO_HDR; + +/* + * Command Error Event + */ +typedef enum { + INVALID_PARAM = 0x01, + ILLEGAL_STATE = 0x02, + INTERNAL_ERROR = 0x03, +} WMI_ERROR_CODE; + +typedef PREPACK struct { + A_UINT16 commandId; + A_UINT8 errorCode; +} POSTPACK WMI_CMD_ERROR_EVENT; + +/* + * New Regulatory Domain Event + */ +typedef PREPACK struct { + A_UINT32 regDomain; +} POSTPACK WMI_REG_DOMAIN_EVENT; + +typedef PREPACK struct { + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficDirection; + A_UINT8 trafficClass; +} POSTPACK WMI_PSTREAM_TIMEOUT_EVENT; + +/* + * The WMI_NEIGHBOR_REPORT Event is generated by the target to inform + * the host of BSS's it has found that matches the current profile. + * It can be used by the host to cache PMKs and/to initiate pre-authentication + * if the BSS supports it. The first bssid is always the current associated + * BSS. + * The bssid and bssFlags information repeats according to the number + * or APs reported. + */ +typedef enum { + WMI_DEFAULT_BSS_FLAGS = 0x00, + WMI_PREAUTH_CAPABLE_BSS = 0x01, + WMI_PMKID_VALID_BSS = 0x02, +} WMI_BSS_FLAGS; + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT8 bssFlags; /* see WMI_BSS_FLAGS */ +} POSTPACK WMI_NEIGHBOR_INFO; + +typedef PREPACK struct { + A_INT8 numberOfAps; + WMI_NEIGHBOR_INFO neighbor[1]; +} POSTPACK WMI_NEIGHBOR_REPORT_EVENT; + +/* + * TKIP MIC Error Event + */ +typedef PREPACK struct { + A_UINT8 keyid; + A_UINT8 ismcast; +} POSTPACK WMI_TKIP_MICERR_EVENT; + +/* + * WMI_SCAN_COMPLETE_EVENTID - no parameters (old), staus parameter (new) + */ +typedef PREPACK struct { + A_INT32 status; +} POSTPACK WMI_SCAN_COMPLETE_EVENT; + +#define MAX_OPT_DATA_LEN 1400 + +/* + * WMI_SET_ADHOC_BSSID_CMDID + */ +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_SET_ADHOC_BSSID_CMD; + +/* + * WMI_SET_OPT_MODE_CMDID + */ +typedef enum { + SPECIAL_OFF, + SPECIAL_ON, + PYXIS_ADHOC_ON, + PYXIS_ADHOC_OFF, +} OPT_MODE_TYPE; + +typedef PREPACK struct { + A_UINT8 optMode; +} POSTPACK WMI_SET_OPT_MODE_CMD; + +/* + * WMI_TX_OPT_FRAME_CMDID + */ +typedef enum { + OPT_PROBE_REQ = 0x01, + OPT_PROBE_RESP = 0x02, + OPT_CPPP_START = 0x03, + OPT_CPPP_STOP = 0x04, +} WMI_OPT_FTYPE; + +typedef PREPACK struct { + A_UINT16 optIEDataLen; + A_UINT8 frmType; + A_UINT8 dstAddr[ATH_MAC_LEN]; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT8 reserved; /* For alignment */ + A_UINT8 optIEData[1]; +} POSTPACK WMI_OPT_TX_FRAME_CMD; + +/* + * Special frame receive Event. + * Mechanism used to inform host of the receiption of the special frames. + * Consists of special frame info header followed by special frame body. + * The 802.11 header is not included. + */ +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 frameType; /* see WMI_OPT_FTYPE */ + A_INT8 snr; + A_UINT8 srcAddr[ATH_MAC_LEN]; + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_OPT_RX_INFO_HDR; + +/* + * Reporting statistics. + */ +typedef PREPACK struct { + A_UINT32 tx_packets; + A_UINT32 tx_bytes; + A_UINT32 tx_unicast_pkts; + A_UINT32 tx_unicast_bytes; + A_UINT32 tx_multicast_pkts; + A_UINT32 tx_multicast_bytes; + A_UINT32 tx_broadcast_pkts; + A_UINT32 tx_broadcast_bytes; + A_UINT32 tx_rts_success_cnt; + A_UINT32 tx_packet_per_ac[4]; + A_UINT32 tx_errors_per_ac[4]; + + A_UINT32 tx_errors; + A_UINT32 tx_failed_cnt; + A_UINT32 tx_retry_cnt; + A_UINT32 tx_mult_retry_cnt; + A_UINT32 tx_rts_fail_cnt; + A_INT32 tx_unicast_rate; +}POSTPACK tx_stats_t; + +typedef PREPACK struct { + A_UINT32 rx_packets; + A_UINT32 rx_bytes; + A_UINT32 rx_unicast_pkts; + A_UINT32 rx_unicast_bytes; + A_UINT32 rx_multicast_pkts; + A_UINT32 rx_multicast_bytes; + A_UINT32 rx_broadcast_pkts; + A_UINT32 rx_broadcast_bytes; + A_UINT32 rx_fragment_pkt; + + A_UINT32 rx_errors; + A_UINT32 rx_crcerr; + A_UINT32 rx_key_cache_miss; + A_UINT32 rx_decrypt_err; + A_UINT32 rx_duplicate_frames; + A_INT32 rx_unicast_rate; +}POSTPACK rx_stats_t; + +typedef PREPACK struct { + A_UINT32 tkip_local_mic_failure; + A_UINT32 tkip_counter_measures_invoked; + A_UINT32 tkip_replays; + A_UINT32 tkip_format_errors; + A_UINT32 ccmp_format_errors; + A_UINT32 ccmp_replays; +}POSTPACK tkip_ccmp_stats_t; + +typedef PREPACK struct { + A_UINT32 power_save_failure_cnt; +}POSTPACK pm_stats_t; + +typedef PREPACK struct { + A_UINT32 cs_bmiss_cnt; + A_UINT32 cs_lowRssi_cnt; + A_UINT16 cs_connect_cnt; + A_UINT16 cs_disconnect_cnt; + A_INT16 cs_aveBeacon_rssi; + A_UINT16 cs_roam_count; + A_INT16 cs_rssi; + A_UINT8 cs_snr; + A_UINT8 cs_aveBeacon_snr; + A_UINT8 cs_lastRoam_msec; +} POSTPACK cserv_stats_t; + +typedef PREPACK struct { + tx_stats_t tx_stats; + rx_stats_t rx_stats; + tkip_ccmp_stats_t tkipCcmpStats; +}POSTPACK wlan_net_stats_t; + +typedef PREPACK struct { + A_UINT32 arp_received; + A_UINT32 arp_matched; + A_UINT32 arp_replied; +} POSTPACK arp_stats_t; + +typedef PREPACK struct { + A_UINT32 wow_num_pkts_dropped; + A_UINT16 wow_num_events_discarded; + A_UINT8 wow_num_host_pkt_wakeups; + A_UINT8 wow_num_host_event_wakeups; +} POSTPACK wlan_wow_stats_t; + +typedef PREPACK struct { + A_UINT32 lqVal; + A_INT32 noise_floor_calibation; + pm_stats_t pmStats; + wlan_net_stats_t txrxStats; + wlan_wow_stats_t wowStats; + arp_stats_t arpStats; + cserv_stats_t cservStats; +} POSTPACK WMI_TARGET_STATS; + +/* + * WMI_RSSI_THRESHOLD_EVENTID. + * Indicate the RSSI events to host. Events are indicated when we breach a + * thresold value. + */ +typedef enum{ + WMI_RSSI_THRESHOLD1_ABOVE = 0, + WMI_RSSI_THRESHOLD2_ABOVE, + WMI_RSSI_THRESHOLD3_ABOVE, + WMI_RSSI_THRESHOLD4_ABOVE, + WMI_RSSI_THRESHOLD5_ABOVE, + WMI_RSSI_THRESHOLD6_ABOVE, + WMI_RSSI_THRESHOLD1_BELOW, + WMI_RSSI_THRESHOLD2_BELOW, + WMI_RSSI_THRESHOLD3_BELOW, + WMI_RSSI_THRESHOLD4_BELOW, + WMI_RSSI_THRESHOLD5_BELOW, + WMI_RSSI_THRESHOLD6_BELOW +}WMI_RSSI_THRESHOLD_VAL; + +typedef PREPACK struct { + A_INT16 rssi; + A_UINT8 range; +}POSTPACK WMI_RSSI_THRESHOLD_EVENT; + +/* + * WMI_ERROR_REPORT_EVENTID + */ +typedef enum{ + WMI_TARGET_PM_ERR_FAIL = 0x00000001, + WMI_TARGET_KEY_NOT_FOUND = 0x00000002, + WMI_TARGET_DECRYPTION_ERR = 0x00000004, + WMI_TARGET_BMISS = 0x00000008, + WMI_PSDISABLE_NODE_JOIN = 0x00000010, + WMI_TARGET_COM_ERR = 0x00000020, + WMI_TARGET_FATAL_ERR = 0x00000040 +} WMI_TARGET_ERROR_VAL; + +typedef PREPACK struct { + A_UINT32 errorVal; +}POSTPACK WMI_TARGET_ERROR_REPORT_EVENT; + +typedef PREPACK struct { + A_UINT8 retrys; +}POSTPACK WMI_TX_RETRY_ERR_EVENT; + +typedef enum{ + WMI_SNR_THRESHOLD1_ABOVE = 1, + WMI_SNR_THRESHOLD1_BELOW, + WMI_SNR_THRESHOLD2_ABOVE, + WMI_SNR_THRESHOLD2_BELOW, + WMI_SNR_THRESHOLD3_ABOVE, + WMI_SNR_THRESHOLD3_BELOW, + WMI_SNR_THRESHOLD4_ABOVE, + WMI_SNR_THRESHOLD4_BELOW +} WMI_SNR_THRESHOLD_VAL; + +typedef PREPACK struct { + A_UINT8 range; /* WMI_SNR_THRESHOLD_VAL */ + A_UINT8 snr; +}POSTPACK WMI_SNR_THRESHOLD_EVENT; + +typedef enum{ + WMI_LQ_THRESHOLD1_ABOVE = 1, + WMI_LQ_THRESHOLD1_BELOW, + WMI_LQ_THRESHOLD2_ABOVE, + WMI_LQ_THRESHOLD2_BELOW, + WMI_LQ_THRESHOLD3_ABOVE, + WMI_LQ_THRESHOLD3_BELOW, + WMI_LQ_THRESHOLD4_ABOVE, + WMI_LQ_THRESHOLD4_BELOW +} WMI_LQ_THRESHOLD_VAL; + +typedef PREPACK struct { + A_INT32 lq; + A_UINT8 range; /* WMI_LQ_THRESHOLD_VAL */ +}POSTPACK WMI_LQ_THRESHOLD_EVENT; +/* + * WMI_REPORT_ROAM_TBL_EVENTID + */ +#define MAX_ROAM_TBL_CAND 5 + +typedef PREPACK struct { + A_INT32 roam_util; + A_UINT8 bssid[ATH_MAC_LEN]; + A_INT8 rssi; + A_INT8 rssidt; + A_INT8 last_rssi; + A_INT8 util; + A_INT8 bias; + A_UINT8 reserved; /* For alignment */ +} POSTPACK WMI_BSS_ROAM_INFO; + + +typedef PREPACK struct { + A_UINT16 roamMode; + A_UINT16 numEntries; + WMI_BSS_ROAM_INFO bssRoamInfo[1]; +} POSTPACK WMI_TARGET_ROAM_TBL; + +/* + * WMI_CAC_EVENTID + */ +typedef enum { + CAC_INDICATION_ADMISSION = 0x00, + CAC_INDICATION_ADMISSION_RESP = 0x01, + CAC_INDICATION_DELETE = 0x02, + CAC_INDICATION_NO_RESP = 0x03, +}CAC_INDICATION; + +#define WMM_TSPEC_IE_LEN 63 + +typedef PREPACK struct { + A_UINT8 ac; + A_UINT8 cac_indication; + A_UINT8 statusCode; + A_UINT8 tspecSuggestion[WMM_TSPEC_IE_LEN]; +}POSTPACK WMI_CAC_EVENT; + +/* + * WMI_APLIST_EVENTID + */ + +typedef enum { + APLIST_VER1 = 1, +} APLIST_VER; + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT16 channel; +} POSTPACK WMI_AP_INFO_V1; + +typedef PREPACK union { + WMI_AP_INFO_V1 apInfoV1; +} POSTPACK WMI_AP_INFO; + +typedef PREPACK struct { + A_UINT8 apListVer; + A_UINT8 numAP; + WMI_AP_INFO apList[1]; +} POSTPACK WMI_APLIST_EVENT; + +/* + * developer commands + */ + +/* + * WMI_SET_BITRATE_CMDID + * + * Get bit rate cmd uses same definition as set bit rate cmd + */ +typedef enum { + RATE_AUTO = -1, + RATE_1Mb = 0, + RATE_2Mb = 1, + RATE_5_5Mb = 2, + RATE_11Mb = 3, + RATE_6Mb = 4, + RATE_9Mb = 5, + RATE_12Mb = 6, + RATE_18Mb = 7, + RATE_24Mb = 8, + RATE_36Mb = 9, + RATE_48Mb = 10, + RATE_54Mb = 11, +} WMI_BIT_RATE; + +typedef PREPACK struct { + A_INT8 rateIndex; /* see WMI_BIT_RATE */ + A_INT8 mgmtRateIndex; + A_INT8 ctlRateIndex; +} POSTPACK WMI_BIT_RATE_CMD; + + +typedef PREPACK struct { + A_INT8 rateIndex; /* see WMI_BIT_RATE */ +} POSTPACK WMI_BIT_RATE_REPLY; + + +/* + * WMI_SET_FIXRATES_CMDID + * + * Get fix rates cmd uses same definition as set fix rates cmd + */ +typedef enum { + FIX_RATE_1Mb = 0x1, + FIX_RATE_2Mb = 0x2, + FIX_RATE_5_5Mb = 0x4, + FIX_RATE_11Mb = 0x8, + FIX_RATE_6Mb = 0x10, + FIX_RATE_9Mb = 0x20, + FIX_RATE_12Mb = 0x40, + FIX_RATE_18Mb = 0x80, + FIX_RATE_24Mb = 0x100, + FIX_RATE_36Mb = 0x200, + FIX_RATE_48Mb = 0x400, + FIX_RATE_54Mb = 0x800, +} WMI_FIX_RATES_MASK; + +typedef PREPACK struct { + A_UINT16 fixRateMask; /* see WMI_BIT_RATE */ +} POSTPACK WMI_FIX_RATES_CMD, WMI_FIX_RATES_REPLY; + +typedef PREPACK struct { + A_UINT8 bEnableMask; + A_UINT8 frameType; /*type and subtype*/ + A_UINT16 frameRateMask; /* see WMI_BIT_RATE */ +} POSTPACK WMI_FRAME_RATES_CMD, WMI_FRAME_RATES_REPLY; + +/* + * WMI_SET_RECONNECT_AUTH_MODE_CMDID + * + * Set authentication mode + */ +typedef enum { + RECONN_DO_AUTH = 0x00, + RECONN_NOT_AUTH = 0x01 +} WMI_AUTH_MODE; + +typedef PREPACK struct { + A_UINT8 mode; +} POSTPACK WMI_SET_AUTH_MODE_CMD; + +/* + * WMI_SET_REASSOC_MODE_CMDID + * + * Set authentication mode + */ +typedef enum { + REASSOC_DO_DISASSOC = 0x00, + REASSOC_DONOT_DISASSOC = 0x01 +} WMI_REASSOC_MODE; + +typedef PREPACK struct { + A_UINT8 mode; +}POSTPACK WMI_SET_REASSOC_MODE_CMD; + +typedef enum { + ROAM_DATA_TIME = 1, /* Get The Roam Time Data */ +} ROAM_DATA_TYPE; + +typedef PREPACK struct { + A_UINT32 disassoc_time; + A_UINT32 no_txrx_time; + A_UINT32 assoc_time; + A_UINT32 allow_txrx_time; + A_UINT32 last_data_txrx_time; + A_UINT32 first_data_txrx_time; + A_UINT8 disassoc_bssid[ATH_MAC_LEN]; + A_INT8 disassoc_bss_rssi; + A_UINT8 assoc_bssid[ATH_MAC_LEN]; + A_INT8 assoc_bss_rssi; +} POSTPACK WMI_TARGET_ROAM_TIME; + +typedef PREPACK struct { + PREPACK union { + WMI_TARGET_ROAM_TIME roamTime; + } POSTPACK u; + A_UINT8 roamDataType ; +} POSTPACK WMI_TARGET_ROAM_DATA; + +typedef enum { + WMI_WMM_DISABLED = 0, + WMI_WMM_ENABLED +} WMI_WMM_STATUS; + +typedef PREPACK struct { + A_UINT8 status; +}POSTPACK WMI_SET_WMM_CMD; + +typedef enum { + WMI_TXOP_DISABLED = 0, + WMI_TXOP_ENABLED +} WMI_TXOP_CFG; + +typedef PREPACK struct { + A_UINT8 txopEnable; +}POSTPACK WMI_SET_WMM_TXOP_CMD; + +typedef PREPACK struct { + A_UINT8 keepaliveInterval; +} POSTPACK WMI_SET_KEEPALIVE_CMD; + +typedef PREPACK struct { + A_BOOL configured; + A_UINT8 keepaliveInterval; +} POSTPACK WMI_GET_KEEPALIVE_CMD; + +/* + * Add Application specified IE to a management frame + */ +#define WMI_MAX_IE_LEN 255 + +typedef PREPACK struct { + A_UINT8 mgmtFrmType; /* one of WMI_MGMT_FRAME_TYPE */ + A_UINT8 ieLen; /* Length of the IE that should be added to the MGMT frame */ + A_UINT8 ieInfo[1]; +} POSTPACK WMI_SET_APPIE_CMD; + +/* + * Notify the WSC registration status to the target + */ +#define WSC_REG_ACTIVE 1 +#define WSC_REG_INACTIVE 0 +/* Generic Hal Interface for setting hal paramters. */ +/* Add new Set HAL Param cmdIds here for newer params */ +typedef enum { + WHAL_SETCABTO_CMDID = 1, +}WHAL_CMDID; + +typedef PREPACK struct { + A_UINT8 cabTimeOut; +} POSTPACK WHAL_SETCABTO_PARAM; + +typedef PREPACK struct { + A_UINT8 whalCmdId; + A_UINT8 data[1]; +} POSTPACK WHAL_PARAMCMD; + + +#define WOW_MAX_FILTER_LISTS 1 /*4*/ +#define WOW_MAX_FILTERS_PER_LIST 4 +#define WOW_PATTERN_SIZE 64 +#define WOW_MASK_SIZE 64 + +#define MAC_MAX_FILTERS_PER_LIST 4 + +typedef PREPACK struct { + A_UINT8 wow_valid_filter; + A_UINT8 wow_filter_id; + A_UINT8 wow_filter_size; + A_UINT8 wow_filter_offset; + A_UINT8 wow_filter_mask[WOW_MASK_SIZE]; + A_UINT8 wow_filter_pattern[WOW_PATTERN_SIZE]; +} POSTPACK WOW_FILTER; + + +typedef PREPACK struct { + A_UINT8 wow_valid_list; + A_UINT8 wow_list_id; + A_UINT8 wow_num_filters; + A_UINT8 wow_total_list_size; + WOW_FILTER list[WOW_MAX_FILTERS_PER_LIST]; +} POSTPACK WOW_FILTER_LIST; + +typedef PREPACK struct { + A_UINT8 valid_filter; + A_UINT8 mac_addr[ATH_MAC_LEN]; +} POSTPACK MAC_FILTER; + + +typedef PREPACK struct { + A_UINT8 total_list_size; + MAC_FILTER list[MAC_MAX_FILTERS_PER_LIST]; +} POSTPACK MAC_FILTER_LIST; + +#define MAX_IP_ADDRS 2 +typedef PREPACK struct { + A_UINT32 ips[MAX_IP_ADDRS]; /* IP in Network Byte Order */ +} POSTPACK WMI_SET_IP_CMD; + +typedef PREPACK struct { + A_BOOL awake; + A_BOOL asleep; +} POSTPACK WMI_SET_HOST_SLEEP_MODE_CMD; + +typedef PREPACK struct { + A_BOOL enable_wow; +} POSTPACK WMI_SET_WOW_MODE_CMD; + +typedef PREPACK struct { + A_UINT8 filter_list_id; +} POSTPACK WMI_GET_WOW_LIST_CMD; + +/* + * WMI_GET_WOW_LIST_CMD reply + */ +typedef PREPACK struct { + A_UINT8 num_filters; /* number of patterns in reply */ + A_UINT8 this_filter_num; /* this is filter # x of total num_filters */ + A_UINT8 wow_mode; + A_UINT8 host_mode; + WOW_FILTER wow_filters[1]; +} POSTPACK WMI_GET_WOW_LIST_REPLY; + +typedef PREPACK struct { + A_UINT8 filter_list_id; + A_UINT8 filter_size; + A_UINT8 filter_offset; + A_UINT8 filter[1]; +} POSTPACK WMI_ADD_WOW_PATTERN_CMD; + +typedef PREPACK struct { + A_UINT16 filter_list_id; + A_UINT16 filter_id; +} POSTPACK WMI_DEL_WOW_PATTERN_CMD; + +typedef PREPACK struct { + A_UINT8 macaddr[ATH_MAC_LEN]; +} POSTPACK WMI_SET_MAC_ADDRESS_CMD; + +/* + * WMI_SET_AKMP_PARAMS_CMD + */ + +#define WMI_AKMP_MULTI_PMKID_EN 0x000001 + +typedef PREPACK struct { + A_UINT32 akmpInfo; +} POSTPACK WMI_SET_AKMP_PARAMS_CMD; + +typedef PREPACK struct { + A_UINT8 pmkid[WMI_PMKID_LEN]; +} POSTPACK WMI_PMKID; + +/* + * WMI_SET_PMKID_LIST_CMD + */ +#define WMI_MAX_PMKID_CACHE 8 + +typedef PREPACK struct { + A_UINT32 numPMKID; + WMI_PMKID pmkidList[WMI_MAX_PMKID_CACHE]; +} POSTPACK WMI_SET_PMKID_LIST_CMD; + +/* + * WMI_GET_PMKID_LIST_CMD Reply + * Following the Number of PMKIDs is the list of PMKIDs + */ +typedef PREPACK struct { + A_UINT32 numPMKID; + A_UINT8 bssidList[ATH_MAC_LEN][1]; + WMI_PMKID pmkidList[1]; +} POSTPACK WMI_PMKID_LIST_REPLY; + +typedef PREPACK struct { + A_UINT16 oldChannel; + A_UINT32 newChannel; +} POSTPACK WMI_CHANNEL_CHANGE_EVENT; + +typedef PREPACK struct { + A_UINT32 version; +} POSTPACK WMI_WLAN_VERSION_EVENT; + +#define PEER_NODE_JOIN_EVENT 0x00 +#define PEER_NODE_LEAVE_EVENT 0x01 +#define PEER_FIRST_NODE_JOIN_EVENT 0x10 +#define PEER_LAST_NODE_LEAVE_EVENT 0x11 +typedef PREPACK struct { + A_UINT8 eventCode; + A_UINT8 peerMacAddr[ATH_MAC_LEN]; +} POSTPACK WMI_PEER_NODE_EVENT; + +#define IEEE80211_FRAME_TYPE_MGT 0x00 +#define IEEE80211_FRAME_TYPE_CTL 0x04 + + +typedef enum { + WMI_PYXIS_GEN_PARAMS = 0, + WMI_PYXIS_DSCVR_PARAMS, + WMI_PYXIS_SET_TX_MODE, +} WMI_PYXIS_CONFIG_TYPE; + +typedef PREPACK struct { + A_UINT16 pyxisConfigType; // One of WMI_PYXIS_CONFIG_TYPE + A_UINT16 pyxisConfigLen; // Length in Bytes of Information that follows +} POSTPACK WMI_PYXIS_CONFIG_HDR; + +typedef PREPACK struct { + WMI_PYXIS_CONFIG_HDR hdr; + A_UINT32 dscvrWindow; + A_UINT32 dscvrInterval; + A_UINT32 dscvrLife; + A_UINT32 probeInterval; + A_UINT32 probePeriod; + A_UINT16 dscvrChannel; +} POSTPACK WMI_PYXIS_DSCVR_CONFIG; + +typedef PREPACK struct { + WMI_PYXIS_CONFIG_HDR hdr; + A_UINT32 dataWindowSizeMin; + A_UINT32 dataWindowSizeMax; + A_UINT8 maxJoiners; +} POSTPACK WMI_PYXIS_GEN_CONFIG; + +typedef PREPACK struct { + WMI_PYXIS_CONFIG_HDR hdr; + A_BOOL mode; +} POSTPACK WMI_PYXIS_TX_MODE; + +typedef enum { + WMI_PYXIS_DISC_PEER = 0, + WMI_PYXIS_JOIN_PEER, +} WMI_PYXIS_CMD_TYPE; + +typedef PREPACK struct { + A_UINT16 pyxisCmd; + A_UINT16 pyxisCmdLen; // Length following this header +} POSTPACK WMI_PYXIS_CMD_HDR; + +typedef PREPACK struct { + WMI_PYXIS_CMD_HDR hdr; + A_UINT8 peerMacAddr[ATH_MAC_LEN]; +} POSTPACK WMI_PYXIS_DISCONNECT_CMD; + +typedef PREPACK struct { + WMI_PYXIS_CMD_HDR hdr; + A_UINT32 ctrl_flags; /* One of the Bits determines if it + * is Virt Adhoc/the device is to + * join a BSS */ + A_UINT16 channel; /* Data Channel */ + A_UINT8 networkType; /* network type */ + A_UINT8 dot11AuthMode; /* OPEN_AUTH */ + A_UINT8 authMode; /* NONE_AUTH */ + A_UINT8 pairwiseCryptoType; /* One of NONE_CRYPT, AES_CRYPT */ + A_UINT8 pairwiseCryptoLen; /* 0 since ADD_KEY passes the length */ + A_UINT8 groupCryptoType; /* One of NONE_CRYPT, AES_CRYPT */ + A_UINT8 groupCryptoLen; /* 0 since ADD_KEY passes the length */ + A_UINT8 peerMacAddr[ATH_MAC_LEN]; /* BSSID of peer network*/ + A_UINT8 nwBSSID[ATH_MAC_LEN]; /* BSSID of the Pyxis Adhoc Network */ +} POSTPACK WMI_PYXIS_JOIN_CMD; + +typedef PREPACK struct { + WMI_PYXIS_CMD_HDR hdr; + A_BOOL mode; +} POSTPACK WMI_PYXIS_SET_TX_MODE_CMD; + +/* + * ------- AP Mode definitions -------------- + */ + +#define AP_MAX_NUM_STA 8 +#define AP_ACL_SIZE 10 +#define IEEE80211_MAX_IE 256 +#define MCAST_AID 0xFF /* Spl. AID used to set DTIM flag in the beacons */ + +/* AP mode disconnect reasons */ +#define AP_DISCONNECT_STA_LEFT 101 +#define AP_DISCONNECT_FROM_HOST 102 +#define AP_DISCONNECT_COMM_TIMEOUT 103 + +/* + * Used with WMI_AP_HIDDEN_SSID_CMDID + */ +#define HIDDEN_SSID_FALSE 0 +#define HIDDEN_SSID_TRUE 1 +typedef PREPACK struct { + A_UINT8 hidden_ssid; +} POSTPACK WMI_AP_HIDDEN_SSID_CMD; + +/* + * Used with WMI_AP_ACL_POLICY_CMDID + */ +#define AP_ACL_DISABLE 0x00 +#define AP_ACL_ALLOW_MAC 0x01 +#define AP_ACL_DENY_MAC 0x02 +#define AP_ACL_RETAIN_LIST_MASK 0x80 +typedef PREPACK struct { + A_UINT8 policy; +} POSTPACK WMI_AP_ACL_POLICY_CMD; + +/* + * Used with WMI_AP_ACL_MAC_LIST_CMDID + */ +#define ADD_MAC_ADDR 1 +#define DEL_MAC_ADDR 2 +typedef PREPACK struct { + A_UINT8 action; + A_UINT8 index; + A_UINT8 mac[ATH_MAC_LEN]; + A_UINT8 wildcard; +} POSTPACK WMI_AP_ACL_MAC_CMD; + +typedef PREPACK struct { + A_UINT16 index; + A_UINT8 acl_mac[AP_ACL_SIZE][ATH_MAC_LEN]; + A_UINT8 wildcard[AP_ACL_SIZE]; + A_UINT8 policy; +} POSTPACK WMI_AP_ACL; + +/* + * Used with WMI_AP_SET_NUM_STA_CMDID + */ +typedef PREPACK struct { + A_UINT8 num_sta; +} POSTPACK WMI_AP_SET_NUM_STA_CMD; + +/* + * Used with WMI_AP_SET_MLME_CMDID + */ +typedef PREPACK struct { + A_UINT8 mac[ATH_MAC_LEN]; + A_UINT16 reason; /* 802.11 reason code */ + A_UINT8 cmd; /* operation to perform */ +#define WMI_AP_MLME_ASSOC 1 /* associate station */ +#define WMI_AP_DISASSOC 2 /* disassociate station */ +#define WMI_AP_DEAUTH 3 /* deauthenticate station */ +#define WMI_AP_MLME_AUTHORIZE 4 /* authorize station */ +#define WMI_AP_MLME_UNAUTHORIZE 5 /* unauthorize station */ +} POSTPACK WMI_AP_SET_MLME_CMD; + +typedef PREPACK struct { + A_UINT32 period; +} POSTPACK WMI_AP_CONN_INACT_CMD; + +typedef PREPACK struct { + A_UINT32 period_min; + A_UINT32 dwell_ms; +} POSTPACK WMI_AP_PROT_SCAN_TIME_CMD; + +typedef PREPACK struct { + A_BOOL flag; + A_UINT16 aid; +} POSTPACK WMI_AP_SET_PVB_CMD; + +#define WMI_DISABLE_REGULATORY_CODE "FF" + +typedef PREPACK struct { + A_UCHAR countryCode[3]; +} POSTPACK WMI_AP_SET_COUNTRY_CMD; + +typedef PREPACK struct { + A_UINT8 dtim; +} POSTPACK WMI_AP_SET_DTIM_CMD; + +/* AP mode events */ +/* WMI_PS_POLL_EVENT */ +typedef PREPACK struct { + A_UINT16 aid; +} POSTPACK WMI_PSPOLL_EVENT; + +/* + * End of AP mode definitions + */ + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/wmi_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wmi_api.h --- linux-2.6.26/drivers/net/wireless/ath6k22/wmi_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wmi_api.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,367 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions for the Wireless Module Interface (WMI). +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _WMI_API_H_ +#define _WMI_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * IP QoS Field definitions according to 802.1p + */ +#define BEST_EFFORT_PRI 0 +#define BACKGROUND_PRI 1 +#define EXCELLENT_EFFORT_PRI 3 +#define CONTROLLED_LOAD_PRI 4 +#define VIDEO_PRI 5 +#define VOICE_PRI 6 +#define NETWORK_CONTROL_PRI 7 +#define MAX_NUM_PRI 8 + +#define UNDEFINED_PRI (0xff) + +#define WMI_IMPLICIT_PSTREAM_INACTIVITY_INT 5000 /* 5 seconds */ + +#define A_ROUND_UP(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) + +typedef enum { + ATHEROS_COMPLIANCE = 0x1, +}TSPEC_PARAM_COMPLIANCE; + +struct wmi_t; + +void *wmi_init(void *devt); + +void wmi_qos_state_init(struct wmi_t *wmip); +void wmi_shutdown(struct wmi_t *wmip); +HTC_ENDPOINT_ID wmi_get_control_ep(struct wmi_t * wmip); +void wmi_set_control_ep(struct wmi_t * wmip, HTC_ENDPOINT_ID eid); +A_UINT16 wmi_get_mapped_qos_queue(struct wmi_t *, A_UINT8); +A_STATUS wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf); +A_STATUS wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType, A_BOOL bMoreData); +A_STATUS wmi_dot3_2_dix(struct wmi_t *wmip, void *osbuf); + +A_STATUS wmi_dot11_hdr_remove (struct wmi_t *wmip, void *osbuf); +A_STATUS wmi_dot11_hdr_add(struct wmi_t *wmip, void *osbuf, NETWORK_TYPE mode); + +A_STATUS wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf); +A_STATUS wmi_syncpoint(struct wmi_t *wmip); +A_STATUS wmi_syncpoint_reset(struct wmi_t *wmip); +A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT32 layer2Priority, A_BOOL wmmEnabled); + +A_UINT8 wmi_determine_userPriority (A_UINT8 *pkt, A_UINT32 layer2Pri); + +A_STATUS wmi_control_rx(struct wmi_t *wmip, void *osbuf); +void wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg); +void wmi_free_allnodes(struct wmi_t *wmip); +bss_t *wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr); +void wmi_free_node(struct wmi_t *wmip, const A_UINT8 *macaddr); + + +typedef enum { + NO_SYNC_WMIFLAG = 0, + SYNC_BEFORE_WMIFLAG, /* transmit all queued data before cmd */ + SYNC_AFTER_WMIFLAG, /* any new data waits until cmd execs */ + SYNC_BOTH_WMIFLAG, + END_WMIFLAG /* end marker */ +} WMI_SYNC_FLAG; + +A_STATUS wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId, + WMI_SYNC_FLAG flag); + +A_STATUS wmi_connect_cmd(struct wmi_t *wmip, + NETWORK_TYPE netType, + DOT11_AUTH_MODE dot11AuthMode, + AUTH_MODE authMode, + CRYPTO_TYPE pairwiseCrypto, + A_UINT8 pairwiseCryptoLen, + CRYPTO_TYPE groupCrypto, + A_UINT8 groupCryptoLen, + int ssidLength, + A_UCHAR *ssid, + A_UINT8 *bssid, + A_UINT16 channel, + A_UINT32 ctrl_flags); + +A_STATUS wmi_reconnect_cmd(struct wmi_t *wmip, + A_UINT8 *bssid, + A_UINT16 channel); +A_STATUS wmi_disconnect_cmd(struct wmi_t *wmip); +A_STATUS wmi_getrev_cmd(struct wmi_t *wmip); +A_STATUS wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType, + A_BOOL forceFgScan, A_BOOL isLegacy, + A_UINT32 homeDwellTime, A_UINT32 forceScanInterval, + A_INT8 numChan, A_UINT16 *channelList); +A_STATUS wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec, + A_UINT16 fg_end_sec, A_UINT16 bg_sec, + A_UINT16 minact_chdw_msec, + A_UINT16 maxact_chdw_msec, A_UINT16 pas_chdw_msec, + A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags, + A_UINT32 max_dfsch_act_time, + A_UINT16 maxact_scan_per_ssid); +A_STATUS wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask); +A_STATUS wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag, + A_UINT8 ssidLength, A_UCHAR *ssid); +A_STATUS wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons); +A_STATUS wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmisstime, A_UINT16 bmissbeacons); +A_STATUS wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType, + A_UINT8 ieLen, A_UINT8 *ieInfo); +A_STATUS wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode); +A_STATUS wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl, + A_UINT16 atim_windows, A_UINT16 timeout_value); +A_STATUS wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod, + A_UINT16 psPollNum, A_UINT16 dtimPolicy); +A_STATUS wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout); +A_STATUS wmi_sync_cmd(struct wmi_t *wmip, A_UINT8 syncNumber); +A_STATUS wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *pstream); +A_STATUS wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 streamID); +A_STATUS wmi_set_framerate_cmd(struct wmi_t *wmip, A_UINT8 bEnable, A_UINT8 type, A_UINT8 subType, A_UINT16 rateMask); +A_STATUS wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 dataRate, A_INT32 mgmtRate, A_INT32 ctlRate); +A_STATUS wmi_get_bitrate_cmd(struct wmi_t *wmip); +A_INT8 wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate); +A_STATUS wmi_get_regDomain_cmd(struct wmi_t *wmip); +A_STATUS wmi_get_channelList_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam, + WMI_PHY_MODE mode, A_INT8 numChan, + A_UINT16 *channelList); + +A_STATUS wmi_set_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd); +A_STATUS wmi_set_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd); +A_STATUS wmi_clr_rssi_snr(struct wmi_t *wmip); +A_STATUS wmi_set_lq_threshold_params(struct wmi_t *wmip, + WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd); +A_STATUS wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold); +A_STATUS wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status); + +A_STATUS wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 bitmask); + +A_STATUS wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie, + A_UINT32 source); + +A_STATUS wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask, + A_UINT16 tsr, A_BOOL rep, A_UINT16 size, + A_UINT32 valid); + +A_STATUS wmi_get_stats_cmd (struct wmi_t *wmip); + +A_STATUS wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex, + CRYPTO_TYPE keyType, A_UINT8 keyUsage, + A_UINT8 keyLength,A_UINT8 *keyRSC, + A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl, A_UINT8 *mac, + WMI_SYNC_FLAG sync_flag); +A_STATUS wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk); +A_STATUS wmi_delete_krk_cmd(struct wmi_t *wmip); +A_STATUS wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex); +A_STATUS wmi_set_akmp_params_cmd(struct wmi_t *wmip, + WMI_SET_AKMP_PARAMS_CMD *akmpParams); +A_STATUS wmi_get_pmkid_list_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_pmkid_list_cmd(struct wmi_t *wmip, + WMI_SET_PMKID_LIST_CMD *pmkInfo); +A_STATUS wmi_abort_scan_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM); +A_STATUS wmi_get_txPwr_cmd(struct wmi_t *wmip); +A_STATUS wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid); +A_STATUS wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex); +A_STATUS wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en); +A_STATUS wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId, + A_BOOL set); +A_STATUS wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT16 txop, + A_UINT8 eCWmin, A_UINT8 eCWmax, + A_UINT8 aifsn); +A_STATUS wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType, + A_UINT8 trafficClass, A_UINT8 maxRetries, + A_UINT8 enableNotify); + +void wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid); + +A_STATUS wmi_get_roam_tbl_cmd(struct wmi_t *wmip); +A_STATUS wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType); +A_STATUS wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p, + A_UINT8 size); +A_STATUS wmi_set_powersave_timers_cmd(struct wmi_t *wmip, + WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd, + A_UINT8 size); + +A_STATUS wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode); +A_STATUS wmi_opt_tx_frame_cmd(struct wmi_t *wmip, + A_UINT8 frmType, + A_UINT8 *dstMacAddr, + A_UINT8 *bssid, + A_UINT16 optIEDataLen, + A_UINT8 *optIEData); + +A_STATUS wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl); +A_STATUS wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize); +A_STATUS wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSpLen); +A_UINT8 convert_userPriority_to_trafficClass(A_UINT8 userPriority); +A_UINT8 wmi_get_power_mode_cmd(struct wmi_t *wmip); +A_STATUS wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance); + +#ifdef CONFIG_HOST_TCMD_SUPPORT +A_STATUS wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32 len); +#endif + +A_STATUS wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status); +A_STATUS wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd); + + +/* + * This function is used to configure the fix rates mask to the target. + */ +A_STATUS wmi_set_fixrates_cmd(struct wmi_t *wmip, A_INT16 fixRatesMask); +A_STATUS wmi_get_ratemask_cmd(struct wmi_t *wmip); + +A_STATUS wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode); + +A_STATUS wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode); + +A_STATUS wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status); +A_STATUS wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG txEnable); +A_STATUS wmi_set_country(struct wmi_t *wmip, A_UCHAR *countryCode); + +A_STATUS wmi_get_keepalive_configured(struct wmi_t *wmip); +A_UINT8 wmi_get_keepalive_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval); + +A_STATUS wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType, + A_UINT8 ieLen,A_UINT8 *ieInfo); + +A_STATUS wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen); + +A_INT32 wmi_get_rate(A_INT8 rateindex); + +A_STATUS wmi_set_ip_cmd(struct wmi_t *wmip, WMI_SET_IP_CMD *cmd); + +/*Wake on Wireless WMI commands*/ +A_STATUS wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip, WMI_SET_HOST_SLEEP_MODE_CMD *cmd); +A_STATUS wmi_set_wow_mode_cmd(struct wmi_t *wmip, WMI_SET_WOW_MODE_CMD *cmd); +A_STATUS wmi_get_wow_list_cmd(struct wmi_t *wmip, WMI_GET_WOW_LIST_CMD *cmd); +A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip, + WMI_ADD_WOW_PATTERN_CMD *cmd, A_UINT8* pattern, A_UINT8* mask, A_UINT8 pattern_size); +A_STATUS wmi_del_wow_pattern_cmd(struct wmi_t *wmip, + WMI_DEL_WOW_PATTERN_CMD *cmd); +A_STATUS wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status); + +A_STATUS +wmi_set_params_cmd(struct wmi_t *wmip, A_UINT32 opcode, A_UINT32 length, A_CHAR* buffer); + +A_STATUS +wmi_set_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4); + +A_STATUS +wmi_del_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4); + +bss_t * +wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID); + + +void +wmi_node_return (struct wmi_t *wmip, bss_t *bss); + +void +wmi_set_nodeage(struct wmi_t *wmip, A_UINT32 nodeAge); + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +A_STATUS wmi_prof_cfg_cmd(struct wmi_t *wmip, A_UINT32 period, A_UINT32 nbins); +A_STATUS wmi_prof_addr_set_cmd(struct wmi_t *wmip, A_UINT32 addr); +A_STATUS wmi_prof_start_cmd(struct wmi_t *wmip); +A_STATUS wmi_prof_stop_cmd(struct wmi_t *wmip); +A_STATUS wmi_prof_count_get_cmd(struct wmi_t *wmip); +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ +#ifdef OS_ROAM_MANAGEMENT +void wmi_scan_indication (struct wmi_t *wmip); +#endif + +A_STATUS +wmi_set_target_event_report_cmd(struct wmi_t *wmip, WMI_SET_TARGET_EVENT_REPORT_CMD* cmd); + +#ifdef PYXIS_ADHOC +A_STATUS +wmi_set_pyxis_gen_config (struct wmi_t *wmip, A_UINT32 dataWindowSizeMin, A_UINT32 dataWindowSizeMax, A_UINT8 maxJoiners); + +A_STATUS +wmi_set_pyxis_dscvr_config (struct wmi_t *wmip, A_UINT32 dscvrWindow, A_UINT32 dscvrInterval, + A_UINT32 probeInterval, A_UINT32 probePeriod, A_UINT16 dscvrChannel); +A_STATUS +wmi_pyxis_disconnect_cmd (struct wmi_t *wmip, A_UINT8 *bssid); + +A_STATUS +wmi_pyxis_join_cmd (struct wmi_t *wmip, NETWORK_TYPE wmiNetworkType, + DOT11_AUTH_MODE dot11AuthMode, AUTH_MODE authMode, + CRYPTO_TYPE pairwiseCrypto, A_UINT8 pairwiseCryptoLen, + CRYPTO_TYPE groupCrypto, A_UINT8 groupCryptoLen, + A_UINT8 *bssid, A_UINT8 *nwBSSID, A_UINT16 channel, A_UINT32 ctrl_flags + ); +#endif + +bss_t *wmi_rm_current_bss (struct wmi_t *wmip, A_UINT8 *id); +A_STATUS wmi_add_current_bss (struct wmi_t *wmip, A_UINT8 *id, bss_t *bss); + + +/* + * AP mode + */ +A_STATUS +wmi_ap_profile_commit(struct wmi_t *wmip, WMI_CONNECT_CMD *p); + +A_STATUS +wmi_ap_set_hidden_ssid(struct wmi_t *wmip, A_UINT8 hidden_ssid); + +A_STATUS +wmi_ap_set_num_sta(struct wmi_t *wmip, A_UINT8 num_sta); + +A_STATUS +wmi_ap_set_acl_policy(struct wmi_t *wmip, A_UINT8 policy); + +A_STATUS +wmi_ap_acl_mac_list(struct wmi_t *wmip, WMI_AP_ACL_MAC_CMD *a); + +A_UINT8 +acl_add_del_mac(WMI_AP_ACL *a, WMI_AP_ACL_MAC_CMD *acl); + +A_STATUS +wmi_ap_set_mlme(struct wmi_t *wmip, A_UINT8 cmd, A_UINT8 *mac, A_UINT16 reason); + +A_STATUS +wmi_set_pvb_cmd(struct wmi_t *wmip, A_UINT16 aid, A_BOOL flag); + +A_STATUS +wmi_ap_conn_inact_time(struct wmi_t *wmip, A_UINT32 period); + +A_STATUS +wmi_ap_bgscan_time(struct wmi_t *wmip, A_UINT32 period, A_UINT32 dwell); + +A_STATUS +wmi_ap_set_dtim(struct wmi_t *wmip, A_UINT8 dtim); + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/wmi_filter_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wmi_filter_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k22/wmi_filter_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wmi_filter_linux.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + */ + +#ifndef _WMI_FILTER_LINUX_H_ +#define _WMI_FILTER_LINUX_H_ + +/* + * sioctl_filter - Standard ioctl + * pioctl_filter - Priv ioctl + * xioctl_filter - eXtended ioctl + * + * ---- Possible values for the WMI filter --------------- + * (0) - Block this cmd always (or) not implemented + * (INFRA_NETWORK) - Allow this cmd only in STA mode + * (ADHOC_NETWORK) - Allow this cmd only in IBSS mode + * (AP_NETWORK) - Allow this cmd only in AP mode + * (INFRA_NETWORK | ADHOC_NETWORK) - Block this cmd in AP mode + * (ADHOC_NETWORK | AP_NETWORK) - Block this cmd in STA mode + * (INFRA_NETWORK | AP_NETWORK) - Block this cmd in IBSS mode + * (INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK)- allow only when mode is set + * (0xFF) - Allow this cmd always irrespective of mode + */ + +A_UINT8 sioctl_filter[] = { +(AP_NETWORK), /* SIOCSIWCOMMIT 0x8B00 */ +(0xFF), /* SIOCGIWNAME 0x8B01 */ +(0), /* SIOCSIWNWID 0x8B02 */ +(0), /* SIOCGIWNWID 0x8B03 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWFREQ 0x8B04 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWFREQ 0x8B05 */ +(0xFF), /* SIOCSIWMODE 0x8B06 */ +(0xFF), /* SIOCGIWMODE 0x8B07 */ +(0), /* SIOCSIWSENS 0x8B08 */ +(0), /* SIOCGIWSENS 0x8B09 */ +(0), /* SIOCSIWRANGE 0x8B0A */ +(0xFF), /* SIOCGIWRANGE 0x8B0B */ +(0), /* SIOCSIWPRIV 0x8B0C */ +(0), /* SIOCGIWPRIV 0x8B0D */ +(0), /* SIOCSIWSTATS 0x8B0E */ +(0), /* SIOCGIWSTATS 0x8B0F */ +(0), /* SIOCSIWSPY 0x8B10 */ +(0), /* SIOCGIWSPY 0x8B11 */ +(0), /* SIOCSIWTHRSPY 0x8B12 */ +(0), /* SIOCGIWTHRSPY 0x8B13 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWAP 0x8B14 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWAP 0x8B15 */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,13) +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCSIWMLME 0X8B16 */ +#else +(0), /* Dummy 0 */ +#endif /* LINUX_VERSION_CODE */ +(0), /* SIOCGIWAPLIST 0x8B17 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCSIWSCAN 0x8B18 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCGIWSCAN 0x8B19 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWESSID 0x8B1A */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWESSID 0x8B1B */ +(0), /* SIOCSIWNICKN 0x8B1C */ +(0), /* SIOCGIWNICKN 0x8B1D */ +(0), /* Dummy 0 */ +(0), /* Dummy 0 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWRATE 0x8B20 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWRATE 0x8B21 */ +(0), /* SIOCSIWRTS 0x8B22 */ +(0), /* SIOCGIWRTS 0x8B23 */ +(0), /* SIOCSIWFRAG 0x8B24 */ +(0), /* SIOCGIWFRAG 0x8B25 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWTXPOW 0x8B26 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWTXPOW 0x8B27 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCSIWRETRY 0x8B28 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCGIWRETRY 0x8B29 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWENCODE 0x8B2A */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWENCODE 0x8B2B */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCSIWPOWER 0x8B2C */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCGIWPOWER 0x8B2D */ +}; + + + +A_UINT8 pioctl_filter[] = { +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_SETPARAM (SIOCIWFIRSTPRIV+0) */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_SETKEY (SIOCIWFIRSTPRIV+1) */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_DELKEY (SIOCIWFIRSTPRIV+2) */ +(AP_NETWORK), /* IEEE80211_IOCTL_SETMLME (SIOCIWFIRSTPRIV+3) */ +(INFRA_NETWORK), /* IEEE80211_IOCTL_ADDPMKID (SIOCIWFIRSTPRIV+4) */ +(0), /* IEEE80211_IOCTL_SETOPTIE (SIOCIWFIRSTPRIV+5) */ +(0), /* (SIOCIWFIRSTPRIV+6) */ +(0), /* (SIOCIWFIRSTPRIV+7) */ +(0), /* (SIOCIWFIRSTPRIV+8) */ +(0), /* (SIOCIWFIRSTPRIV+9) */ +(0), /* IEEE80211_IOCTL_LASTONE (SIOCIWFIRSTPRIV+10) */ +(0xFF), /* AR6000_IOCTL_WMI_GETREV (SIOCIWFIRSTPRIV+11) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SETPWR (SIOCIWFIRSTPRIV+12) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SETSCAN (SIOCIWFIRSTPRIV+13) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SETLISTENINT (SIOCIWFIRSTPRIV+14) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SETBSSFILTER (SIOCIWFIRSTPRIV+15) */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_IOCTL_WMI_SET_CHANNELPARAMS (SIOCIWFIRSTPRIV+16) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_PROBEDSSID (SIOCIWFIRSTPRIV+17) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_PMPARAMS (SIOCIWFIRSTPRIV+18) */ +(INFRA_NETWORK), /* AR6000_IOCTL_WMI_SET_BADAP (SIOCIWFIRSTPRIV+19) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_GET_QOS_QUEUE (SIOCIWFIRSTPRIV+20) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_CREATE_QOS (SIOCIWFIRSTPRIV+21) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_DELETE_QOS (SIOCIWFIRSTPRIV+22) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_SNRTHRESHOLD (SIOCIWFIRSTPRIV+23) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24)*/ +(0xFF), /* AR6000_IOCTL_WMI_GET_TARGET_STATS (SIOCIWFIRSTPRIV+25) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_ASSOC_INFO (SIOCIWFIRSTPRIV+26) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_ACCESS_PARAMS (SIOCIWFIRSTPRIV+27) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_BMISS_TIME (SIOCIWFIRSTPRIV+28) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_DISC_TIMEOUT (SIOCIWFIRSTPRIV+29) */ +(ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS (SIOCIWFIRSTPRIV+30) */ +}; + + + +A_UINT8 xioctl_filter[] = { +(0xFF), /* Dummy 0 */ +(0xFF), /* AR6000_XIOCTL_BMI_DONE 1 */ +(0xFF), /* AR6000_XIOCTL_BMI_READ_MEMORY 2 */ +(0xFF), /* AR6000_XIOCTL_BMI_WRITE_MEMORY 3 */ +(0xFF), /* AR6000_XIOCTL_BMI_EXECUTE 4 */ +(0xFF), /* AR6000_XIOCTL_BMI_SET_APP_START 5 */ +(0xFF), /* AR6000_XIOCTL_BMI_READ_SOC_REGISTER 6 */ +(0xFF), /* AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER 7 */ +(0xFF), /* AR6000_XIOCTL_BMI_TEST 8 */ +(0xFF), /* AR6000_XIOCTL_UNUSED9 9 */ +(0xFF), /* AR6000_XIOCTL_UNUSED10 10 */ +(0xFF), /* AR6000_XIOCTL_UNUSED11 11 */ +(0xFF), /* AR6000_XIOCTL_FORCE_TARGET_RESET 12 */ +(0xFF), /* AR6000_XIOCTL_HTC_RAW_OPEN 13 */ +(0xFF), /* AR6000_XIOCTL_HTC_RAW_CLOSE 14 */ +(0xFF), /* AR6000_XIOCTL_HTC_RAW_READ 15 */ +(0xFF), /* AR6000_XIOCTL_HTC_RAW_WRITE 16 */ +(0xFF), /* AR6000_XIOCTL_CHECK_TARGET_READY 17 */ +(0xFF), /* AR6000_XIOCTL_GPIO_OUTPUT_SET 18 */ +(0xFF), /* AR6000_XIOCTL_GPIO_INPUT_GET 19 */ +(0xFF), /* AR6000_XIOCTL_GPIO_REGISTER_SET 20 */ +(0xFF), /* AR6000_XIOCTL_GPIO_REGISTER_GET 21 */ +(0xFF), /* AR6000_XIOCTL_GPIO_INTR_ACK 22 */ +(0xFF), /* AR6000_XIOCTL_GPIO_INTR_WAIT 23 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_ADHOC_BSSID 24 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_OPT_MODE 25 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_OPT_SEND_FRAME 26 */ +(ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_SET_BEACON_INTVAL 27 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_SETAUTHALG 28 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_VOICE_PKT_SIZE 29 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_MAX_SP 30 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_ROAM_TBL 31 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_ROAM_CTRL 32 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS 33 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTRL_WMI_GET_POWER_MODE 34 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTRL_WMI_SET_WLAN_STATE 35 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_ROAM_DATA 36 */ +(0xFF), /* AR6000_XIOCTL_WMI_SETRETRYLIMITS 37 */ +(0xFF), /* AR6000_XIOCTL_TCMD_CONT_TX 38 */ +(0xFF), /* AR6000_XIOCTL_TCMD_CONT_RX 39 */ +(0xFF), /* AR6000_XIOCTL_TCMD_PM 40 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_STARTSCAN 41 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SETFIXRATES 42 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_GETFIXRATES 43 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD 44 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_CLR_RSSISNR 45 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_LQTHRESHOLD 46 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_RTS 47 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_LPREAMBLE 48 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_AUTHMODE 49 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_REASSOCMODE 50 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_WMM 51 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS 52 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP 53 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_GET_RD 54 */ +(0xFF), /* AR6000_XIOCTL_DIAG_READ 55 */ +(0xFF), /* AR6000_XIOCTL_DIAG_WRITE 56 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_TXOP 57 */ +(INFRA_NETWORK), /* AR6000_XIOCTL_USER_SETKEYS 58 */ +(INFRA_NETWORK), /* AR6000_XIOCTL_WMI_SET_KEEPALIVE 59 */ +(INFRA_NETWORK), /* AR6000_XIOCTL_WMI_GET_KEEPALIVE 60 */ +(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_INSTALL 61 */ +(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL 62 */ +(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE 63 */ +(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE 64 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_APPIE 65 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER 66 */ +(0xFF), /* AR6000_XIOCTL_DBGLOG_CFG_MODULE 67 */ +(0xFF), /* AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS 68 */ +(0xFF), /* Dummy 69 */ +(INFRA_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_WSC_STATUS 70 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BT_STATUS 71 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BT_PARAMS 72 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE 73 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_WOW_MODE 74 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_WOW_LIST 75 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_ADD_WOW_PATTERN 76 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_DEL_WOW_PATTERN 77 */ +(0xFF), /* AR6000_XIOCTL_TARGET_INFO 78 */ +(0xFF), /* AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE 79 */ +(0xFF), /* AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE 80 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS 81 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_AKMP_PARAMS 82 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_PMKID_LIST 83 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_PMKID_LIST 84 */ +(0xFF), /* Dummy 85 */ +(0xFF), /* Dummy 86 */ +(0xFF), /* Dummy 87 */ +(0xFF), /* Dummy 88 */ +(0xFF), /* Dummy 89 */ +(0xFF), /* AR6000_XIOCTL_UNUSED90 90 */ +(0xFF), /* AR6000_XIOCTL_BMI_LZ_STREAM_START 91 */ +(0xFF), /* AR6000_XIOCTL_BMI_LZ_DATA 92 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_CFG 93 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_ADDR_SET 94 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_START 95 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_STOP 96 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_COUNT_GET 97 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_ABORT_SCAN 98 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_STA_LIST 99 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_HIDDEN_SSID 100 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_NUM_STA 101 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_ACL_MAC 102 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_ACL_LIST 103 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_COMMIT_CONFIG 104 */ +(AP_NETWORK), /* IEEE80211_IOCTL_GETWPAIE 105 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_CONN_INACT_TIME 106 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_PROT_SCAN_TIME 107 */ +(AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_COUNTRY 108 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_DTIM 109 */ +(0xFF), /* AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT 110 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_IP 111 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_ACL_POLICY 112 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_INTRA_BSS_COMM 113 */ +}; + +#endif /*_WMI_FILTER_LINUX_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/wmi_host.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wmi_host.h --- linux-2.6.26/drivers/net/wireless/ath6k22/wmi_host.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wmi_host.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,82 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains local definitios for the wmi host module. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _WMI_HOST_H_ +#define _WMI_HOST_H_ + +#include "roaming.h" +#ifdef __cplusplus +extern "C" { +#endif + +struct wmi_stats { + A_UINT32 cmd_len_err; + A_UINT32 cmd_id_err; +}; + +#define SSID_IE_LEN_INDEX 13 + +/* Host side link management data structures */ +#define SIGNAL_QUALITY_THRESHOLD_LEVELS 6 +#define SIGNAL_QUALITY_UPPER_THRESHOLD_LEVELS SIGNAL_QUALITY_THRESHOLD_LEVELS +#define SIGNAL_QUALITY_LOWER_THRESHOLD_LEVELS SIGNAL_QUALITY_THRESHOLD_LEVELS +typedef struct sq_threshold_params_s { + A_INT16 upper_threshold[SIGNAL_QUALITY_UPPER_THRESHOLD_LEVELS]; + A_INT16 lower_threshold[SIGNAL_QUALITY_LOWER_THRESHOLD_LEVELS]; + A_UINT32 upper_threshold_valid_count; + A_UINT32 lower_threshold_valid_count; + A_UINT32 polling_interval; + A_UINT8 weight; + A_UINT8 last_rssi; //normally you would expect this to be bss specific but we keep only one instance because its only valid when the device is in a connected state. Not sure if it belongs to host or target. + A_UINT8 last_rssi_poll_event; //Not sure if it belongs to host or target +} SQ_THRESHOLD_PARAMS; +struct wmi_t { + A_BOOL wmi_ready; + A_BOOL wmi_numQoSStream; + A_UINT16 wmi_streamExistsForAC[WMM_NUM_AC]; + A_UINT8 wmi_fatPipeExists; + void *wmi_devt; + struct wmi_stats wmi_stats; + struct ieee80211_node_table wmi_scan_table; + A_UINT8 wmi_bssid[ATH_MAC_LEN]; + A_UINT8 wmi_powerMode; + A_UINT8 wmi_phyMode; + A_UINT8 wmi_keepaliveInterval; + A_MUTEX_T wmi_lock; + HTC_ENDPOINT_ID wmi_endpoint_id; + SQ_THRESHOLD_PARAMS wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_NUM_MAX]; + CRYPTO_TYPE wmi_pair_crypto_type; + CRYPTO_TYPE wmi_grp_crypto_type; + A_BOOL wmi_is_wmm_enabled; +}; + + +#define LOCK_WMI(w) A_MUTEX_LOCK(&(w)->wmi_lock); +#define UNLOCK_WMI(w) A_MUTEX_UNLOCK(&(w)->wmi_lock); + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_HOST_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22/wmix.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wmix.h --- linux-2.6.26/drivers/net/wireless/ath6k22/wmix.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22/wmix.h 2010-08-10 04:16:37.000000000 -0400 @@ -0,0 +1,279 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +/* + * This file contains extensions of the WMI protocol specified in the + * Wireless Module Interface (WMI). It includes definitions of all + * extended commands and events. Extensions include useful commands + * that are not directly related to wireless activities. They may + * be hardware-specific, and they might not be supported on all + * implementations. + * + * Extended WMIX commands are encapsulated in a WMI message with + * cmd=WMI_EXTENSION_CMD. + */ + +#ifndef _WMIX_H_ +#define _WMIX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#include "dbglog.h" + +/* + * Extended WMI commands are those that are needed during wireless + * operation, but which are not really wireless commands. This allows, + * for instance, platform-specific commands. Extended WMI commands are + * embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID. + * Extended WMI events are similarly embedded in a WMI event message with + * WMI_EVENT_ID=WMI_EXTENSION_EVENTID. + */ +typedef PREPACK struct { + A_UINT32 commandId; +} POSTPACK WMIX_CMD_HDR; + +typedef enum { + WMIX_DSETOPEN_REPLY_CMDID = 0x2001, + WMIX_DSETDATA_REPLY_CMDID, + WMIX_GPIO_OUTPUT_SET_CMDID, + WMIX_GPIO_INPUT_GET_CMDID, + WMIX_GPIO_REGISTER_SET_CMDID, + WMIX_GPIO_REGISTER_GET_CMDID, + WMIX_GPIO_INTR_ACK_CMDID, + WMIX_HB_CHALLENGE_RESP_CMDID, + WMIX_DBGLOG_CFG_MODULE_CMDID, + WMIX_PROF_CFG_CMDID, /* 0x200a */ + WMIX_PROF_ADDR_SET_CMDID, + WMIX_PROF_START_CMDID, + WMIX_PROF_STOP_CMDID, + WMIX_PROF_COUNT_GET_CMDID, +} WMIX_COMMAND_ID; + +typedef enum { + WMIX_DSETOPENREQ_EVENTID = 0x3001, + WMIX_DSETCLOSE_EVENTID, + WMIX_DSETDATAREQ_EVENTID, + WMIX_GPIO_INTR_EVENTID, + WMIX_GPIO_DATA_EVENTID, + WMIX_GPIO_ACK_EVENTID, + WMIX_HB_CHALLENGE_RESP_EVENTID, + WMIX_DBGLOG_EVENTID, + WMIX_PROF_COUNT_EVENTID, +} WMIX_EVENT_ID; + +/* + * =============DataSet support================= + */ + +/* + * WMIX_DSETOPENREQ_EVENTID + * DataSet Open Request Event + */ +typedef PREPACK struct { + A_UINT32 dset_id; + A_UINT32 targ_dset_handle; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */ +} POSTPACK WMIX_DSETOPENREQ_EVENT; + +/* + * WMIX_DSETCLOSE_EVENTID + * DataSet Close Event + */ +typedef PREPACK struct { + A_UINT32 access_cookie; +} POSTPACK WMIX_DSETCLOSE_EVENT; + +/* + * WMIX_DSETDATAREQ_EVENTID + * DataSet Data Request Event + */ +typedef PREPACK struct { + A_UINT32 access_cookie; + A_UINT32 offset; + A_UINT32 length; + A_UINT32 targ_buf; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */ +} POSTPACK WMIX_DSETDATAREQ_EVENT; + +typedef PREPACK struct { + A_UINT32 status; + A_UINT32 targ_dset_handle; + A_UINT32 targ_reply_fn; + A_UINT32 targ_reply_arg; + A_UINT32 access_cookie; + A_UINT32 size; + A_UINT32 version; +} POSTPACK WMIX_DSETOPEN_REPLY_CMD; + +typedef PREPACK struct { + A_UINT32 status; + A_UINT32 targ_buf; + A_UINT32 targ_reply_fn; + A_UINT32 targ_reply_arg; + A_UINT32 length; + A_UINT8 buf[1]; +} POSTPACK WMIX_DSETDATA_REPLY_CMD; + + +/* + * =============GPIO support================= + * All masks are 18-bit masks with bit N operating on GPIO pin N. + */ + +#include "gpio.h" + +/* + * Set GPIO pin output state. + * In order for output to be driven, a pin must be enabled for output. + * This can be done during initialization through the GPIO Configuration + * DataSet, or during operation with the enable_mask. + * + * If a request is made to simultaneously set/clear or set/disable or + * clear/disable or disable/enable, results are undefined. + */ +typedef PREPACK struct { + A_UINT32 set_mask; /* pins to set */ + A_UINT32 clear_mask; /* pins to clear */ + A_UINT32 enable_mask; /* pins to enable for output */ + A_UINT32 disable_mask; /* pins to disable/tristate */ +} POSTPACK WMIX_GPIO_OUTPUT_SET_CMD; + +/* + * Set a GPIO register. For debug/exceptional cases. + * Values for gpioreg_id are GPIO_REGISTER_IDs, defined in a + * platform-dependent header. + */ +typedef PREPACK struct { + A_UINT32 gpioreg_id; /* GPIO register ID */ + A_UINT32 value; /* value to write */ +} POSTPACK WMIX_GPIO_REGISTER_SET_CMD; + +/* Get a GPIO register. For debug/exceptional cases. */ +typedef PREPACK struct { + A_UINT32 gpioreg_id; /* GPIO register to read */ +} POSTPACK WMIX_GPIO_REGISTER_GET_CMD; + +/* + * Host acknowledges and re-arms GPIO interrupts. A single + * message should be used to acknowledge all interrupts that + * were delivered in an earlier WMIX_GPIO_INTR_EVENT message. + */ +typedef PREPACK struct { + A_UINT32 ack_mask; /* interrupts to acknowledge */ +} POSTPACK WMIX_GPIO_INTR_ACK_CMD; + +/* + * Target informs Host of GPIO interrupts that have ocurred since the + * last WMIX_GIPO_INTR_ACK_CMD was received. Additional information -- + * the current GPIO input values is provided -- in order to support + * use of a GPIO interrupt as a Data Valid signal for other GPIO pins. + */ +typedef PREPACK struct { + A_UINT32 intr_mask; /* pending GPIO interrupts */ + A_UINT32 input_values; /* recent GPIO input values */ +} POSTPACK WMIX_GPIO_INTR_EVENT; + +/* + * Target responds to Host's earlier WMIX_GPIO_INPUT_GET_CMDID request + * using a GPIO_DATA_EVENT with + * value set to the mask of GPIO pin inputs and + * reg_id set to GPIO_ID_NONE + * + * + * Target responds to Hosts's earlier WMIX_GPIO_REGISTER_GET_CMDID request + * using a GPIO_DATA_EVENT with + * value set to the value of the requested register and + * reg_id identifying the register (reflects the original request) + * NB: reg_id supports the future possibility of unsolicited + * WMIX_GPIO_DATA_EVENTs (for polling GPIO input), and it may + * simplify Host GPIO support. + */ +typedef PREPACK struct { + A_UINT32 value; + A_UINT32 reg_id; +} POSTPACK WMIX_GPIO_DATA_EVENT; + +/* + * =============Error Detection support================= + */ + +/* + * WMIX_HB_CHALLENGE_RESP_CMDID + * Heartbeat Challenge Response command + */ +typedef PREPACK struct { + A_UINT32 cookie; + A_UINT32 source; +} POSTPACK WMIX_HB_CHALLENGE_RESP_CMD; + +/* + * WMIX_HB_CHALLENGE_RESP_EVENTID + * Heartbeat Challenge Response Event + */ +#define WMIX_HB_CHALLENGE_RESP_EVENT WMIX_HB_CHALLENGE_RESP_CMD + +typedef PREPACK struct { + struct dbglog_config_s config; +} POSTPACK WMIX_DBGLOG_CFG_MODULE_CMD; + +/* + * =============Target Profiling support================= + */ + +typedef PREPACK struct { + A_UINT32 period; /* Time (in 30.5us ticks) between samples */ + A_UINT32 nbins; +} POSTPACK WMIX_PROF_CFG_CMD; + +typedef PREPACK struct { + A_UINT32 addr; +} POSTPACK WMIX_PROF_ADDR_SET_CMD; + +/* + * Target responds to Hosts's earlier WMIX_PROF_COUNT_GET_CMDID request + * using a WMIX_PROF_COUNT_EVENT with + * addr set to the next address + * count set to the corresponding count + */ +typedef PREPACK struct { + A_UINT32 addr; + A_UINT32 count; +} POSTPACK WMIX_PROF_COUNT_EVENT; + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _WMIX_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/AR6002_regdump.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/AR6002_regdump.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/AR6002_regdump.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/AR6002_regdump.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,59 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2006 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __AR6002_REGDUMP_H__ +#define __AR6002_REGDUMP_H__ + +#if !defined(__ASSEMBLER__) +/* + * XTensa CPU state + * This must match the state saved by the target exception handler. + */ +struct XTensa_exception_frame_s { + A_UINT32 xt_pc; + A_UINT32 xt_ps; + A_UINT32 xt_sar; + A_UINT32 xt_vpri; + A_UINT32 xt_a2; + A_UINT32 xt_a3; + A_UINT32 xt_a4; + A_UINT32 xt_a5; + A_UINT32 xt_exccause; + A_UINT32 xt_lcount; + A_UINT32 xt_lbeg; + A_UINT32 xt_lend; + + /* Extra info to simplify post-mortem stack walkback */ +#define AR6002_REGDUMP_FRAMES 5 + struct { + A_UINT32 a0; /* pc */ + A_UINT32 a1; /* sp */ + A_UINT32 a2; + A_UINT32 a3; + } wb[AR6002_REGDUMP_FRAMES]; +}; +typedef struct XTensa_exception_frame_s CPU_exception_frame_t; +#define RD_SIZE sizeof(CPU_exception_frame_t) + +#endif +#endif /* __AR6002_REGDUMP_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/AR6K_version.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/AR6K_version.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/AR6K_version.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/AR6K_version.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#define __VER_MAJOR_ 2 +#define __VER_MINOR_ 2 +#define __VER_PATCH_ 0 + + +/* The makear6ksdk script (used for release builds) modifies the following line. */ +#define __BUILD_NUMBER_ 151 + + +/* Format of the version number. */ +#define VER_MAJOR_BIT_OFFSET 28 +#define VER_MINOR_BIT_OFFSET 24 +#define VER_PATCH_BIT_OFFSET 16 +#define VER_BUILD_NUM_BIT_OFFSET 0 + + +/* + * The version has the following format: + * Bits 28-31: Major version + * Bits 24-27: Minor version + * Bits 16-23: Patch version + * Bits 0-15: Build number (automatically generated during build process ) + * E.g. Build 1.1.3.7 would be represented as 0x11030007. + * + * DO NOT split the following macro into multiple lines as this may confuse the build scripts. + */ +#define AR6K_SW_VERSION ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) ) + + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/Makefile linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/Makefile --- linux-2.6.26/drivers/net/wireless/ath6k22.133/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/Makefile 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,37 @@ +# +# Atheros WiFi driver +# + +EXTRA_CFLAGS += -DSEND_EVENT_TO_APP -DHTC_RAW_INTERFACE -DAR6000REV2 -Idrivers/net/wireless/ath6k22.133/ + +obj-$(CONFIG_ATHEROS_AR6000) += ar6000.o + +ar6000-objs := \ + ar6000_drv.o \ + ar6000_raw_if.o \ + ar6k.o \ + ar6k_events.o \ + bmi.o \ + common_drv.o \ + credit_dist.o \ + eeprom.o \ + engine.o \ + hif.o \ + htc.o \ + htc_recv.o \ + htc_send.o \ + htc_services.o \ + ioctl.o \ + netbuf.o \ + wireless_ext.o \ + wlan_node.o \ + wlan_recv_beacon.o \ + wlan_utils.o \ + wmi.o + +ATH_BUILD_TYPE := NATIVEMMC +ATH_BUS_TYPE := SDIO +ATH_BUS_SUBTYPE := linux_sdio +ATH_OS_SUB_TYPE := linux_2_6 +export ATH_BUS_SUBTYPE + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/a_config.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/a_config.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/a_config.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/a_config.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,46 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains software configuration options that enables +// specific software "features" +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_CONFIG_H_ +#define _A_CONFIG_H_ + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/config_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/config_wince.h" +#endif + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "config_linux.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/config_rexos.h" +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/a_debug.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/a_debug.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/a_debug.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/a_debug.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,59 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_DEBUG_H_ +#define _A_DEBUG_H_ + +#include +#include + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/debug_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/debug_wince.h" +#endif + +#ifndef UNDER_CE +#define DBG_INFO 0x00000001 +#define DBG_ERROR 0x00000002 +#define DBG_WARNING 0x00000004 +#define DBG_SDIO 0x00000008 +#define DBG_HIF 0x00000010 +#define DBG_HTC 0x00000020 +#define DBG_WMI 0x00000040 +#define DBG_WMI2 0x00000080 +#define DBG_DRIVER 0x00000100 + +#define DBG_DEFAULTS (DBG_ERROR|DBG_WARNING) +#endif + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "debug_linux.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/debug_rexos.h" +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/a_drv.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/a_drv.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/a_drv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/a_drv.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,46 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions of the basic atheros data types. +// It is used to map the data types in atheros files to a platform specific +// type. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_DRV_H_ +#define _A_DRV_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "athdrv_linux.h" +#endif + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/athdrv_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/athdrv_wince.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/athdrv_rexos.h" +#endif + +#endif /* _ADRV_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/a_drv_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/a_drv_api.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/a_drv_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/a_drv_api.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,211 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_DRV_API_H_ +#define _A_DRV_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************/ +/****************************************************************************/ +/** **/ +/** WMI related hooks **/ +/** **/ +/****************************************************************************/ +/****************************************************************************/ + +#include + +#define A_WMI_CHANNELLIST_RX(devt, numChan, chanList) \ + ar6000_channelList_rx((devt), (numChan), (chanList)) + +#define A_WMI_SET_NUMDATAENDPTS(devt, num) \ + ar6000_set_numdataendpts((devt), (num)) + +#define A_WMI_CONTROL_TX(devt, osbuf, streamID) \ + ar6000_control_tx((devt), (osbuf), (streamID)) + +#define A_WMI_TARGETSTATS_EVENT(devt, pStats) \ + ar6000_targetStats_event((devt), (pStats)) + +#define A_WMI_SCANCOMPLETE_EVENT(devt, status) \ + ar6000_scanComplete_event((devt), (status)) + +#ifdef CONFIG_HOST_DSET_SUPPORT + +#define A_WMI_DSET_DATA_REQ(devt, access_cookie, offset, length, targ_buf, targ_reply_fn, targ_reply_arg) \ + ar6000_dset_data_req((devt), (access_cookie), (offset), (length), (targ_buf), (targ_reply_fn), (targ_reply_arg)) + +#define A_WMI_DSET_CLOSE(devt, access_cookie) \ + ar6000_dset_close((devt), (access_cookie)) + +#endif + +#define A_WMI_DSET_OPEN_REQ(devt, id, targ_handle, targ_reply_fn, targ_reply_arg) \ + ar6000_dset_open_req((devt), (id), (targ_handle), (targ_reply_fn), (targ_reply_arg)) + +#define A_WMI_CONNECT_EVENT(devt, channel, bssid, listenInterval, beaconInterval, networkType, beaconIeLen, assocReqLen, assocRespLen, assocInfo) \ + ar6000_connect_event((devt), (channel), (bssid), (listenInterval), (beaconInterval), (networkType), (beaconIeLen), (assocReqLen), (assocRespLen), (assocInfo)) + +#define A_WMI_PSPOLL_EVENT(devt, aid)\ + ar6000_pspoll_event((devt),(aid)) + +#define A_WMI_DTIMEXPIRY_EVENT(devt)\ + ar6000_dtimexpiry_event((devt)) + +#define A_WMI_REGDOMAIN_EVENT(devt, regCode) \ + ar6000_regDomain_event((devt), (regCode)) + +#define A_WMI_NEIGHBORREPORT_EVENT(devt, numAps, info) \ + ar6000_neighborReport_event((devt), (numAps), (info)) + +#define A_WMI_DISCONNECT_EVENT(devt, reason, bssid, assocRespLen, assocInfo, protocolReasonStatus) \ + ar6000_disconnect_event((devt), (reason), (bssid), (assocRespLen), (assocInfo), (protocolReasonStatus)) + +#define A_WMI_TKIP_MICERR_EVENT(devt, keyid, ismcast) \ + ar6000_tkip_micerr_event((devt), (keyid), (ismcast)) + +#define A_WMI_BITRATE_RX(devt, rateKbps) \ + ar6000_bitrate_rx((devt), (rateKbps)) + +#define A_WMI_TXPWR_RX(devt, txPwr) \ + ar6000_txPwr_rx((devt), (txPwr)) + +#define A_WMI_READY_EVENT(devt, datap, phyCap, ver) \ + ar6000_ready_event((devt), (datap), (phyCap), (ver)) + +#define A_WMI_DBGLOG_INIT_DONE(ar) \ + ar6000_dbglog_init_done(ar); + +#define A_WMI_RSSI_THRESHOLD_EVENT(devt, newThreshold, rssi) \ + ar6000_rssiThreshold_event((devt), (newThreshold), (rssi)) + +#define A_WMI_REPORT_ERROR_EVENT(devt, errorVal) \ + ar6000_reportError_event((devt), (errorVal)) + +#define A_WMI_ROAM_TABLE_EVENT(devt, pTbl) \ + ar6000_roam_tbl_event((devt), (pTbl)) + +#define A_WMI_ROAM_DATA_EVENT(devt, p) \ + ar6000_roam_data_event((devt), (p)) + +#define A_WMI_WOW_LIST_EVENT(devt, num_filters, wow_filters) \ + ar6000_wow_list_event((devt), (num_filters), (wow_filters)) + +#define A_WMI_CAC_EVENT(devt, ac, cac_indication, statusCode, tspecSuggestion) \ + ar6000_cac_event((devt), (ac), (cac_indication), (statusCode), (tspecSuggestion)) + +#define A_WMI_CHANNEL_CHANGE_EVENT(devt, oldChannel, newChannel) \ + ar6000_channel_change_event((devt), (oldChannel), (newChannel)) + +#define A_WMI_PMKID_LIST_EVENT(devt, num_pmkid, pmkid_list, bssid_list) \ + ar6000_pmkid_list_event((devt), (num_pmkid), (pmkid_list), (bssid_list)) + +#define A_WMI_PEER_EVENT(devt, eventCode, bssid) \ + ar6000_peer_event ((devt), (eventCode), (bssid)) + +#ifdef CONFIG_HOST_GPIO_SUPPORT + +#define A_WMI_GPIO_INTR_RX(intr_mask, input_values) \ + ar6000_gpio_intr_rx((intr_mask), (input_values)) + +#define A_WMI_GPIO_DATA_RX(reg_id, value) \ + ar6000_gpio_data_rx((reg_id), (value)) + +#define A_WMI_GPIO_ACK_RX() \ + ar6000_gpio_ack_rx() + +#endif + +#ifdef SEND_EVENT_TO_APP + +#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) \ + ar6000_send_event_to_app((ar), (eventId), (datap), (len)) + +#define A_WMI_SEND_GENERIC_EVENT_TO_APP(ar, eventId, datap, len) \ + ar6000_send_generic_event_to_app((ar), (eventId), (datap), (len)) + +#else + +#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) +#define A_WMI_SEND_GENERIC_EVENT_TO_APP(ar, eventId, datap, len) + +#endif + +#ifdef CONFIG_HOST_TCMD_SUPPORT +#define A_WMI_TCMD_RX_REPORT_EVENT(devt, results, len) \ + ar6000_tcmd_rx_report_event((devt), (results), (len)) +#endif + +#define A_WMI_HBCHALLENGERESP_EVENT(devt, cookie, source) \ + ar6000_hbChallengeResp_event((devt), (cookie), (source)) + +#define A_WMI_TX_RETRY_ERR_EVENT(devt) \ + ar6000_tx_retry_err_event((devt)) + +#define A_WMI_SNR_THRESHOLD_EVENT_RX(devt, newThreshold, snr) \ + ar6000_snrThresholdEvent_rx((devt), (newThreshold), (snr)) + +#define A_WMI_LQ_THRESHOLD_EVENT_RX(devt, range, lqVal) \ + ar6000_lqThresholdEvent_rx((devt), (range), (lqVal)) + +#define A_WMI_RATEMASK_RX(devt, ratemask) \ + ar6000_ratemask_rx((devt), (ratemask)) + +#define A_WMI_KEEPALIVE_RX(devt, configured) \ + ar6000_keepalive_rx((devt), (configured)) + +#define A_WMI_BSSINFO_EVENT_RX(ar, datp, len) \ + ar6000_bssInfo_event_rx((ar), (datap), (len)) + +#define A_WMI_DBGLOG_EVENT(ar, dropped, buffer, length) \ + ar6000_dbglog_event((ar), (dropped), (buffer), (length)); + +#define A_WMI_STREAM_TX_ACTIVE(devt,trafficClass) \ + ar6000_indicate_tx_activity((devt),(trafficClass), TRUE) + +#define A_WMI_STREAM_TX_INACTIVE(devt,trafficClass) \ + ar6000_indicate_tx_activity((devt),(trafficClass), FALSE) +#define A_WMI_Ac2EndpointID(devht, ac)\ + ar6000_ac2_endpoint_id((devht), (ac)) + +#define A_WMI_Endpoint2Ac(devt, ep) \ + ar6000_endpoint_id2_ac((devt), (ep)) +/****************************************************************************/ +/****************************************************************************/ +/** **/ +/** HTC related hooks **/ +/** **/ +/****************************************************************************/ +/****************************************************************************/ + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +#define A_WMI_PROF_COUNT_RX(addr, count) prof_count_rx((addr), (count)) +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + +#ifdef __cplusplus +} +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/a_osapi.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/a_osapi.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/a_osapi.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/a_osapi.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,56 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions of the basic atheros data types. +// It is used to map the data types in atheros files to a platform specific +// type. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_OSAPI_H_ +#define _A_OSAPI_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "osapi_linux.h" +#endif + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/osapi_wince.h" +#include "../os/windows/common/include/netbuf.h" +#if defined __cplusplus || defined __STDC__ +extern "C" +#endif +A_UINT32 a_copy_from_user(void *to, const void *from, A_UINT32 n); +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/osapi_wince.h" +#include "../os/wince/include/netbuf.h" +#if defined __cplusplus || defined __STDC__ +extern "C" +#endif +A_UINT32 a_copy_from_user(void *to, const void *from, A_UINT32 n); +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/osapi_rexos.h" +#endif + +#endif /* _OSAPI_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/a_pyxis.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/a_pyxis.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/a_pyxis.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/a_pyxis.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,59 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the Pyxis definitions for host +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_PYXIS_H_ +#define _A_PYXIS_H_ +/* + * Copyright (c) 2004-2005 Atheros Communications Inc. + * All rights reserved. + * + * +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +/* + * This file contains software key stream pyxis adhoc mode options that enables + * specific software "features" + */ +#ifdef UNDER_CE +#include "../os/wince/include/ks_custom_ndis.h" +#endif + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#endif + +#ifdef REXOS +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/a_types.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/a_types.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/a_types.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/a_types.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,46 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions of the basic atheros data types. +// It is used to map the data types in atheros files to a platform specific +// type. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_TYPES_H_ +#define _A_TYPES_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "athtypes_linux.h" +#endif + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/athtypes_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/athtypes_wince.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/athtypes_rexos.h" +#endif + +#endif /* _ATHTYPES_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/addrs.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/addrs.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/addrs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/addrs.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,85 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __ADDRS_H__ +#define __ADDRS_H__ + +/* + * Special AR6002 Addresses that may be needed by special + * applications (e.g. ART) on the Host as well as Target. + */ + +#if defined(AR6002_REV2) +#define AR6K_RAM_START 0x00500000 +#define TARG_RAM_OFFSET(vaddr) ((A_UINT32)(vaddr) & 0xfffff) +#define TARG_RAM_SZ (184*1024) +#define TARG_ROM_SZ (80*1024) +#endif +#if defined(AR6002_REV4) || defined(AR6003) +#define AR6K_RAM_START 0x00540000 +#define TARG_RAM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0xfffff) - 0x40000) +#define TARG_RAM_SZ (256*1024) +#define TARG_ROM_SZ (256*1024) +#endif + +#define AR6002_BOARD_DATA_SZ 768 +#define AR6003_BOARD_DATA_SZ 1504 + +#define AR6K_RAM_ADDR(byte_offset) (AR6K_RAM_START+(byte_offset)) +#define TARG_RAM_ADDRS(byte_offset) AR6K_RAM_ADDR(byte_offset) + +#define AR6K_ROM_START 0x004e0000 +#define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset)) +#define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset) + +/* + * At this ROM address is a pointer to the start of the ROM DataSet Index. + * If there are no ROM DataSets, there's a 0 at this address. + */ +#define ROM_DATASET_INDEX_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-8) +#define ROM_MBIST_CKSUM_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-4) + +/* + * The API A_BOARD_DATA_ADDR() is the proper way to get a read pointer to + * board data. + */ + +/* Size of Board Data, in bytes */ +#if defined(AR6002_REV4) || defined(AR6003) +#define BOARD_DATA_SZ AR6003_BOARD_DATA_SZ +#else +#define BOARD_DATA_SZ AR6002_BOARD_DATA_SZ +#endif + + +/* + * Constants used by ASM code to access fields of host_interest_s, + * which is at a fixed location in RAM. + */ +#define HOST_INTEREST_FLASH_IS_PRESENT_ADDR (AR6K_RAM_START + 0x40c) +#define FLASH_IS_PRESENT_TARGADDR HOST_INTEREST_FLASH_IS_PRESENT_ADDR + +/* override REV2 ROM's app start address */ +#define AR6002_REV2_APP_START_OVERRIDE 0x913950 + +#endif /* __ADDRS_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/analog_intf_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/analog_intf_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/analog_intf_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/analog_intf_reg.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,87 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _ANALOG_INTF_REG_REG_H_ +#define _ANALOG_INTF_REG_REG_H_ + +#define SW_OVERRIDE_ADDRESS 0x00000080 +#define SW_OVERRIDE_OFFSET 0x00000080 +#define SW_OVERRIDE_SUPDATE_DELAY_MSB 1 +#define SW_OVERRIDE_SUPDATE_DELAY_LSB 1 +#define SW_OVERRIDE_SUPDATE_DELAY_MASK 0x00000002 +#define SW_OVERRIDE_SUPDATE_DELAY_GET(x) (((x) & SW_OVERRIDE_SUPDATE_DELAY_MASK) >> SW_OVERRIDE_SUPDATE_DELAY_LSB) +#define SW_OVERRIDE_SUPDATE_DELAY_SET(x) (((x) << SW_OVERRIDE_SUPDATE_DELAY_LSB) & SW_OVERRIDE_SUPDATE_DELAY_MASK) +#define SW_OVERRIDE_ENABLE_MSB 0 +#define SW_OVERRIDE_ENABLE_LSB 0 +#define SW_OVERRIDE_ENABLE_MASK 0x00000001 +#define SW_OVERRIDE_ENABLE_GET(x) (((x) & SW_OVERRIDE_ENABLE_MASK) >> SW_OVERRIDE_ENABLE_LSB) +#define SW_OVERRIDE_ENABLE_SET(x) (((x) << SW_OVERRIDE_ENABLE_LSB) & SW_OVERRIDE_ENABLE_MASK) + +#define SIN_VAL_ADDRESS 0x00000084 +#define SIN_VAL_OFFSET 0x00000084 +#define SIN_VAL_SIN_MSB 0 +#define SIN_VAL_SIN_LSB 0 +#define SIN_VAL_SIN_MASK 0x00000001 +#define SIN_VAL_SIN_GET(x) (((x) & SIN_VAL_SIN_MASK) >> SIN_VAL_SIN_LSB) +#define SIN_VAL_SIN_SET(x) (((x) << SIN_VAL_SIN_LSB) & SIN_VAL_SIN_MASK) + +#define SW_SCLK_ADDRESS 0x00000088 +#define SW_SCLK_OFFSET 0x00000088 +#define SW_SCLK_SW_SCLK_MSB 0 +#define SW_SCLK_SW_SCLK_LSB 0 +#define SW_SCLK_SW_SCLK_MASK 0x00000001 +#define SW_SCLK_SW_SCLK_GET(x) (((x) & SW_SCLK_SW_SCLK_MASK) >> SW_SCLK_SW_SCLK_LSB) +#define SW_SCLK_SW_SCLK_SET(x) (((x) << SW_SCLK_SW_SCLK_LSB) & SW_SCLK_SW_SCLK_MASK) + +#define SW_CNTL_ADDRESS 0x0000008c +#define SW_CNTL_OFFSET 0x0000008c +#define SW_CNTL_SW_SCAPTURE_MSB 2 +#define SW_CNTL_SW_SCAPTURE_LSB 2 +#define SW_CNTL_SW_SCAPTURE_MASK 0x00000004 +#define SW_CNTL_SW_SCAPTURE_GET(x) (((x) & SW_CNTL_SW_SCAPTURE_MASK) >> SW_CNTL_SW_SCAPTURE_LSB) +#define SW_CNTL_SW_SCAPTURE_SET(x) (((x) << SW_CNTL_SW_SCAPTURE_LSB) & SW_CNTL_SW_SCAPTURE_MASK) +#define SW_CNTL_SW_SUPDATE_MSB 1 +#define SW_CNTL_SW_SUPDATE_LSB 1 +#define SW_CNTL_SW_SUPDATE_MASK 0x00000002 +#define SW_CNTL_SW_SUPDATE_GET(x) (((x) & SW_CNTL_SW_SUPDATE_MASK) >> SW_CNTL_SW_SUPDATE_LSB) +#define SW_CNTL_SW_SUPDATE_SET(x) (((x) << SW_CNTL_SW_SUPDATE_LSB) & SW_CNTL_SW_SUPDATE_MASK) +#define SW_CNTL_SW_SOUT_MSB 0 +#define SW_CNTL_SW_SOUT_LSB 0 +#define SW_CNTL_SW_SOUT_MASK 0x00000001 +#define SW_CNTL_SW_SOUT_GET(x) (((x) & SW_CNTL_SW_SOUT_MASK) >> SW_CNTL_SW_SOUT_LSB) +#define SW_CNTL_SW_SOUT_SET(x) (((x) << SW_CNTL_SW_SOUT_LSB) & SW_CNTL_SW_SOUT_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct analog_intf_reg_reg_s { + unsigned char pad0[128]; /* pad to 0x80 */ + volatile unsigned int sw_override; + volatile unsigned int sin_val; + volatile unsigned int sw_sclk; + volatile unsigned int sw_cntl; +} analog_intf_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _ANALOG_INTF_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/analog_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/analog_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/analog_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/analog_reg.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,1955 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _ANALOG_REG_REG_H_ +#define _ANALOG_REG_REG_H_ + +#define SYNTH_SYNTH1_ADDRESS 0x00000000 +#define SYNTH_SYNTH1_OFFSET 0x00000000 +#define SYNTH_SYNTH1_PWD_BIAS_MSB 31 +#define SYNTH_SYNTH1_PWD_BIAS_LSB 31 +#define SYNTH_SYNTH1_PWD_BIAS_MASK 0x80000000 +#define SYNTH_SYNTH1_PWD_BIAS_GET(x) (((x) & SYNTH_SYNTH1_PWD_BIAS_MASK) >> SYNTH_SYNTH1_PWD_BIAS_LSB) +#define SYNTH_SYNTH1_PWD_BIAS_SET(x) (((x) << SYNTH_SYNTH1_PWD_BIAS_LSB) & SYNTH_SYNTH1_PWD_BIAS_MASK) +#define SYNTH_SYNTH1_PWD_CP_MSB 30 +#define SYNTH_SYNTH1_PWD_CP_LSB 30 +#define SYNTH_SYNTH1_PWD_CP_MASK 0x40000000 +#define SYNTH_SYNTH1_PWD_CP_GET(x) (((x) & SYNTH_SYNTH1_PWD_CP_MASK) >> SYNTH_SYNTH1_PWD_CP_LSB) +#define SYNTH_SYNTH1_PWD_CP_SET(x) (((x) << SYNTH_SYNTH1_PWD_CP_LSB) & SYNTH_SYNTH1_PWD_CP_MASK) +#define SYNTH_SYNTH1_PWD_VCMON_MSB 29 +#define SYNTH_SYNTH1_PWD_VCMON_LSB 29 +#define SYNTH_SYNTH1_PWD_VCMON_MASK 0x20000000 +#define SYNTH_SYNTH1_PWD_VCMON_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCMON_MASK) >> SYNTH_SYNTH1_PWD_VCMON_LSB) +#define SYNTH_SYNTH1_PWD_VCMON_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCMON_LSB) & SYNTH_SYNTH1_PWD_VCMON_MASK) +#define SYNTH_SYNTH1_PWD_VCO_MSB 28 +#define SYNTH_SYNTH1_PWD_VCO_LSB 28 +#define SYNTH_SYNTH1_PWD_VCO_MASK 0x10000000 +#define SYNTH_SYNTH1_PWD_VCO_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCO_MASK) >> SYNTH_SYNTH1_PWD_VCO_LSB) +#define SYNTH_SYNTH1_PWD_VCO_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCO_LSB) & SYNTH_SYNTH1_PWD_VCO_MASK) +#define SYNTH_SYNTH1_PWD_PRESC_MSB 27 +#define SYNTH_SYNTH1_PWD_PRESC_LSB 27 +#define SYNTH_SYNTH1_PWD_PRESC_MASK 0x08000000 +#define SYNTH_SYNTH1_PWD_PRESC_GET(x) (((x) & SYNTH_SYNTH1_PWD_PRESC_MASK) >> SYNTH_SYNTH1_PWD_PRESC_LSB) +#define SYNTH_SYNTH1_PWD_PRESC_SET(x) (((x) << SYNTH_SYNTH1_PWD_PRESC_LSB) & SYNTH_SYNTH1_PWD_PRESC_MASK) +#define SYNTH_SYNTH1_PWD_LODIV_MSB 26 +#define SYNTH_SYNTH1_PWD_LODIV_LSB 26 +#define SYNTH_SYNTH1_PWD_LODIV_MASK 0x04000000 +#define SYNTH_SYNTH1_PWD_LODIV_GET(x) (((x) & SYNTH_SYNTH1_PWD_LODIV_MASK) >> SYNTH_SYNTH1_PWD_LODIV_LSB) +#define SYNTH_SYNTH1_PWD_LODIV_SET(x) (((x) << SYNTH_SYNTH1_PWD_LODIV_LSB) & SYNTH_SYNTH1_PWD_LODIV_MASK) +#define SYNTH_SYNTH1_PWD_LOMIX_MSB 25 +#define SYNTH_SYNTH1_PWD_LOMIX_LSB 25 +#define SYNTH_SYNTH1_PWD_LOMIX_MASK 0x02000000 +#define SYNTH_SYNTH1_PWD_LOMIX_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOMIX_MASK) >> SYNTH_SYNTH1_PWD_LOMIX_LSB) +#define SYNTH_SYNTH1_PWD_LOMIX_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOMIX_LSB) & SYNTH_SYNTH1_PWD_LOMIX_MASK) +#define SYNTH_SYNTH1_FORCE_LO_ON_MSB 24 +#define SYNTH_SYNTH1_FORCE_LO_ON_LSB 24 +#define SYNTH_SYNTH1_FORCE_LO_ON_MASK 0x01000000 +#define SYNTH_SYNTH1_FORCE_LO_ON_GET(x) (((x) & SYNTH_SYNTH1_FORCE_LO_ON_MASK) >> SYNTH_SYNTH1_FORCE_LO_ON_LSB) +#define SYNTH_SYNTH1_FORCE_LO_ON_SET(x) (((x) << SYNTH_SYNTH1_FORCE_LO_ON_LSB) & SYNTH_SYNTH1_FORCE_LO_ON_MASK) +#define SYNTH_SYNTH1_PWD_LOBUF5G_MSB 23 +#define SYNTH_SYNTH1_PWD_LOBUF5G_LSB 23 +#define SYNTH_SYNTH1_PWD_LOBUF5G_MASK 0x00800000 +#define SYNTH_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK) >> SYNTH_SYNTH1_PWD_LOBUF5G_LSB) +#define SYNTH_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOBUF5G_LSB) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK) +#define SYNTH_SYNTH1_VCOREGBYPASS_MSB 22 +#define SYNTH_SYNTH1_VCOREGBYPASS_LSB 22 +#define SYNTH_SYNTH1_VCOREGBYPASS_MASK 0x00400000 +#define SYNTH_SYNTH1_VCOREGBYPASS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBYPASS_MASK) >> SYNTH_SYNTH1_VCOREGBYPASS_LSB) +#define SYNTH_SYNTH1_VCOREGBYPASS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBYPASS_LSB) & SYNTH_SYNTH1_VCOREGBYPASS_MASK) +#define SYNTH_SYNTH1_VCOREGLEVEL_MSB 21 +#define SYNTH_SYNTH1_VCOREGLEVEL_LSB 20 +#define SYNTH_SYNTH1_VCOREGLEVEL_MASK 0x00300000 +#define SYNTH_SYNTH1_VCOREGLEVEL_GET(x) (((x) & SYNTH_SYNTH1_VCOREGLEVEL_MASK) >> SYNTH_SYNTH1_VCOREGLEVEL_LSB) +#define SYNTH_SYNTH1_VCOREGLEVEL_SET(x) (((x) << SYNTH_SYNTH1_VCOREGLEVEL_LSB) & SYNTH_SYNTH1_VCOREGLEVEL_MASK) +#define SYNTH_SYNTH1_VCOREGBIAS_MSB 19 +#define SYNTH_SYNTH1_VCOREGBIAS_LSB 18 +#define SYNTH_SYNTH1_VCOREGBIAS_MASK 0x000c0000 +#define SYNTH_SYNTH1_VCOREGBIAS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBIAS_MASK) >> SYNTH_SYNTH1_VCOREGBIAS_LSB) +#define SYNTH_SYNTH1_VCOREGBIAS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBIAS_LSB) & SYNTH_SYNTH1_VCOREGBIAS_MASK) +#define SYNTH_SYNTH1_SLIDINGIF_MSB 17 +#define SYNTH_SYNTH1_SLIDINGIF_LSB 17 +#define SYNTH_SYNTH1_SLIDINGIF_MASK 0x00020000 +#define SYNTH_SYNTH1_SLIDINGIF_GET(x) (((x) & SYNTH_SYNTH1_SLIDINGIF_MASK) >> SYNTH_SYNTH1_SLIDINGIF_LSB) +#define SYNTH_SYNTH1_SLIDINGIF_SET(x) (((x) << SYNTH_SYNTH1_SLIDINGIF_LSB) & SYNTH_SYNTH1_SLIDINGIF_MASK) +#define SYNTH_SYNTH1_SPARE_PWD_MSB 16 +#define SYNTH_SYNTH1_SPARE_PWD_LSB 16 +#define SYNTH_SYNTH1_SPARE_PWD_MASK 0x00010000 +#define SYNTH_SYNTH1_SPARE_PWD_GET(x) (((x) & SYNTH_SYNTH1_SPARE_PWD_MASK) >> SYNTH_SYNTH1_SPARE_PWD_LSB) +#define SYNTH_SYNTH1_SPARE_PWD_SET(x) (((x) << SYNTH_SYNTH1_SPARE_PWD_LSB) & SYNTH_SYNTH1_SPARE_PWD_MASK) +#define SYNTH_SYNTH1_CON_VDDVCOREG_MSB 15 +#define SYNTH_SYNTH1_CON_VDDVCOREG_LSB 15 +#define SYNTH_SYNTH1_CON_VDDVCOREG_MASK 0x00008000 +#define SYNTH_SYNTH1_CON_VDDVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK) >> SYNTH_SYNTH1_CON_VDDVCOREG_LSB) +#define SYNTH_SYNTH1_CON_VDDVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_VDDVCOREG_LSB) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK) +#define SYNTH_SYNTH1_CON_IVCOREG_MSB 14 +#define SYNTH_SYNTH1_CON_IVCOREG_LSB 14 +#define SYNTH_SYNTH1_CON_IVCOREG_MASK 0x00004000 +#define SYNTH_SYNTH1_CON_IVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCOREG_MASK) >> SYNTH_SYNTH1_CON_IVCOREG_LSB) +#define SYNTH_SYNTH1_CON_IVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOREG_LSB) & SYNTH_SYNTH1_CON_IVCOREG_MASK) +#define SYNTH_SYNTH1_CON_IVCOBUF_MSB 13 +#define SYNTH_SYNTH1_CON_IVCOBUF_LSB 13 +#define SYNTH_SYNTH1_CON_IVCOBUF_MASK 0x00002000 +#define SYNTH_SYNTH1_CON_IVCOBUF_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCOBUF_MASK) >> SYNTH_SYNTH1_CON_IVCOBUF_LSB) +#define SYNTH_SYNTH1_CON_IVCOBUF_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOBUF_LSB) & SYNTH_SYNTH1_CON_IVCOBUF_MASK) +#define SYNTH_SYNTH1_SEL_VCMONABUS_MSB 12 +#define SYNTH_SYNTH1_SEL_VCMONABUS_LSB 10 +#define SYNTH_SYNTH1_SEL_VCMONABUS_MASK 0x00001c00 +#define SYNTH_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK) >> SYNTH_SYNTH1_SEL_VCMONABUS_LSB) +#define SYNTH_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << SYNTH_SYNTH1_SEL_VCMONABUS_LSB) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK) +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MSB 9 +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB 9 +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK 0x00000200 +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK) >> SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB) +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK) +#define SYNTH_SYNTH1_PWUP_LODIV_PD_MSB 8 +#define SYNTH_SYNTH1_PWUP_LODIV_PD_LSB 8 +#define SYNTH_SYNTH1_PWUP_LODIV_PD_MASK 0x00000100 +#define SYNTH_SYNTH1_PWUP_LODIV_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK) >> SYNTH_SYNTH1_PWUP_LODIV_PD_LSB) +#define SYNTH_SYNTH1_PWUP_LODIV_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LODIV_PD_LSB) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK) +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MSB 7 +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB 7 +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK 0x00000080 +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB) +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK) +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MSB 6 +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB 6 +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK 0x00000040 +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB) +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK) +#define SYNTH_SYNTH1_MONITOR_FB_MSB 5 +#define SYNTH_SYNTH1_MONITOR_FB_LSB 5 +#define SYNTH_SYNTH1_MONITOR_FB_MASK 0x00000020 +#define SYNTH_SYNTH1_MONITOR_FB_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB_MASK) >> SYNTH_SYNTH1_MONITOR_FB_LSB) +#define SYNTH_SYNTH1_MONITOR_FB_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_FB_LSB) & SYNTH_SYNTH1_MONITOR_FB_MASK) +#define SYNTH_SYNTH1_MONITOR_REF_MSB 4 +#define SYNTH_SYNTH1_MONITOR_REF_LSB 4 +#define SYNTH_SYNTH1_MONITOR_REF_MASK 0x00000010 +#define SYNTH_SYNTH1_MONITOR_REF_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_REF_MASK) >> SYNTH_SYNTH1_MONITOR_REF_LSB) +#define SYNTH_SYNTH1_MONITOR_REF_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_REF_LSB) & SYNTH_SYNTH1_MONITOR_REF_MASK) +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MSB 3 +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB 3 +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000008 +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK) >> SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB) +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK) +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MSB 2 +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB 2 +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000004 +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK) >> SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB) +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK) +#define SYNTH_SYNTH1_MONITOR_VC2LOW_MSB 1 +#define SYNTH_SYNTH1_MONITOR_VC2LOW_LSB 1 +#define SYNTH_SYNTH1_MONITOR_VC2LOW_MASK 0x00000002 +#define SYNTH_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK) >> SYNTH_SYNTH1_MONITOR_VC2LOW_LSB) +#define SYNTH_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_VC2LOW_LSB) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK) +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 0 +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 0 +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000001 +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK) >> SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB) +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK) + +#define SYNTH_SYNTH2_ADDRESS 0x00000004 +#define SYNTH_SYNTH2_OFFSET 0x00000004 +#define SYNTH_SYNTH2_VC_CAL_REF_MSB 31 +#define SYNTH_SYNTH2_VC_CAL_REF_LSB 29 +#define SYNTH_SYNTH2_VC_CAL_REF_MASK 0xe0000000 +#define SYNTH_SYNTH2_VC_CAL_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_CAL_REF_MASK) >> SYNTH_SYNTH2_VC_CAL_REF_LSB) +#define SYNTH_SYNTH2_VC_CAL_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_CAL_REF_LSB) & SYNTH_SYNTH2_VC_CAL_REF_MASK) +#define SYNTH_SYNTH2_VC_HI_REF_MSB 28 +#define SYNTH_SYNTH2_VC_HI_REF_LSB 26 +#define SYNTH_SYNTH2_VC_HI_REF_MASK 0x1c000000 +#define SYNTH_SYNTH2_VC_HI_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_HI_REF_MASK) >> SYNTH_SYNTH2_VC_HI_REF_LSB) +#define SYNTH_SYNTH2_VC_HI_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_HI_REF_LSB) & SYNTH_SYNTH2_VC_HI_REF_MASK) +#define SYNTH_SYNTH2_VC_MID_REF_MSB 25 +#define SYNTH_SYNTH2_VC_MID_REF_LSB 23 +#define SYNTH_SYNTH2_VC_MID_REF_MASK 0x03800000 +#define SYNTH_SYNTH2_VC_MID_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_MID_REF_MASK) >> SYNTH_SYNTH2_VC_MID_REF_LSB) +#define SYNTH_SYNTH2_VC_MID_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_MID_REF_LSB) & SYNTH_SYNTH2_VC_MID_REF_MASK) +#define SYNTH_SYNTH2_VC_LOW_REF_MSB 22 +#define SYNTH_SYNTH2_VC_LOW_REF_LSB 20 +#define SYNTH_SYNTH2_VC_LOW_REF_MASK 0x00700000 +#define SYNTH_SYNTH2_VC_LOW_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_LOW_REF_MASK) >> SYNTH_SYNTH2_VC_LOW_REF_LSB) +#define SYNTH_SYNTH2_VC_LOW_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_LOW_REF_LSB) & SYNTH_SYNTH2_VC_LOW_REF_MASK) +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MSB 19 +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB 15 +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK 0x000f8000 +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_GET(x) (((x) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK) >> SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB) +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_SET(x) (((x) << SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK) +#define SYNTH_SYNTH2_LOOP_CP_MSB 14 +#define SYNTH_SYNTH2_LOOP_CP_LSB 10 +#define SYNTH_SYNTH2_LOOP_CP_MASK 0x00007c00 +#define SYNTH_SYNTH2_LOOP_CP_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CP_MASK) >> SYNTH_SYNTH2_LOOP_CP_LSB) +#define SYNTH_SYNTH2_LOOP_CP_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CP_LSB) & SYNTH_SYNTH2_LOOP_CP_MASK) +#define SYNTH_SYNTH2_LOOP_RS_MSB 9 +#define SYNTH_SYNTH2_LOOP_RS_LSB 5 +#define SYNTH_SYNTH2_LOOP_RS_MASK 0x000003e0 +#define SYNTH_SYNTH2_LOOP_RS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_RS_MASK) >> SYNTH_SYNTH2_LOOP_RS_LSB) +#define SYNTH_SYNTH2_LOOP_RS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_RS_LSB) & SYNTH_SYNTH2_LOOP_RS_MASK) +#define SYNTH_SYNTH2_LOOP_CS_MSB 4 +#define SYNTH_SYNTH2_LOOP_CS_LSB 3 +#define SYNTH_SYNTH2_LOOP_CS_MASK 0x00000018 +#define SYNTH_SYNTH2_LOOP_CS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CS_MASK) >> SYNTH_SYNTH2_LOOP_CS_LSB) +#define SYNTH_SYNTH2_LOOP_CS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CS_LSB) & SYNTH_SYNTH2_LOOP_CS_MASK) +#define SYNTH_SYNTH2_SPARE_BITS_MSB 2 +#define SYNTH_SYNTH2_SPARE_BITS_LSB 0 +#define SYNTH_SYNTH2_SPARE_BITS_MASK 0x00000007 +#define SYNTH_SYNTH2_SPARE_BITS_GET(x) (((x) & SYNTH_SYNTH2_SPARE_BITS_MASK) >> SYNTH_SYNTH2_SPARE_BITS_LSB) +#define SYNTH_SYNTH2_SPARE_BITS_SET(x) (((x) << SYNTH_SYNTH2_SPARE_BITS_LSB) & SYNTH_SYNTH2_SPARE_BITS_MASK) + +#define SYNTH_SYNTH3_ADDRESS 0x00000008 +#define SYNTH_SYNTH3_OFFSET 0x00000008 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_MSB 31 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_LSB 31 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK) >> SYNTH_SYNTH3_DIS_CLK_XTAL_LSB) +#define SYNTH_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << SYNTH_SYNTH3_DIS_CLK_XTAL_LSB) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK) +#define SYNTH_SYNTH3_SEL_CLK_DIV2_MSB 30 +#define SYNTH_SYNTH3_SEL_CLK_DIV2_LSB 30 +#define SYNTH_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000 +#define SYNTH_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK) >> SYNTH_SYNTH3_SEL_CLK_DIV2_LSB) +#define SYNTH_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << SYNTH_SYNTH3_SEL_CLK_DIV2_LSB) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK) +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29 +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24 +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000 +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB) +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK) +#define SYNTH_SYNTH3_WAIT_PWRUP_MSB 23 +#define SYNTH_SYNTH3_WAIT_PWRUP_LSB 18 +#define SYNTH_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000 +#define SYNTH_SYNTH3_WAIT_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_PWRUP_LSB) +#define SYNTH_SYNTH3_WAIT_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_PWRUP_MASK) +#define SYNTH_SYNTH3_WAIT_CAL_BIN_MSB 17 +#define SYNTH_SYNTH3_WAIT_CAL_BIN_LSB 12 +#define SYNTH_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000 +#define SYNTH_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_BIN_LSB) +#define SYNTH_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_BIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK) +#define SYNTH_SYNTH3_WAIT_CAL_LIN_MSB 11 +#define SYNTH_SYNTH3_WAIT_CAL_LIN_LSB 6 +#define SYNTH_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0 +#define SYNTH_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_LIN_LSB) +#define SYNTH_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_LIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK) +#define SYNTH_SYNTH3_WAIT_VC_CHECK_MSB 5 +#define SYNTH_SYNTH3_WAIT_VC_CHECK_LSB 0 +#define SYNTH_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f +#define SYNTH_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK) >> SYNTH_SYNTH3_WAIT_VC_CHECK_LSB) +#define SYNTH_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << SYNTH_SYNTH3_WAIT_VC_CHECK_LSB) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK) + +#define SYNTH_SYNTH4_ADDRESS 0x0000000c +#define SYNTH_SYNTH4_OFFSET 0x0000000c +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31 +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31 +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000 +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK) >> SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB) +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK) +#define SYNTH_SYNTH4_DIS_LOSTVC_MSB 30 +#define SYNTH_SYNTH4_DIS_LOSTVC_LSB 30 +#define SYNTH_SYNTH4_DIS_LOSTVC_MASK 0x40000000 +#define SYNTH_SYNTH4_DIS_LOSTVC_GET(x) (((x) & SYNTH_SYNTH4_DIS_LOSTVC_MASK) >> SYNTH_SYNTH4_DIS_LOSTVC_LSB) +#define SYNTH_SYNTH4_DIS_LOSTVC_SET(x) (((x) << SYNTH_SYNTH4_DIS_LOSTVC_LSB) & SYNTH_SYNTH4_DIS_LOSTVC_MASK) +#define SYNTH_SYNTH4_ALWAYS_SHORTR_MSB 29 +#define SYNTH_SYNTH4_ALWAYS_SHORTR_LSB 29 +#define SYNTH_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000 +#define SYNTH_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK) >> SYNTH_SYNTH4_ALWAYS_SHORTR_LSB) +#define SYNTH_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << SYNTH_SYNTH4_ALWAYS_SHORTR_LSB) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK) +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28 +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28 +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000 +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK) >> SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB) +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK) +#define SYNTH_SYNTH4_FORCE_PINVC_MSB 27 +#define SYNTH_SYNTH4_FORCE_PINVC_LSB 27 +#define SYNTH_SYNTH4_FORCE_PINVC_MASK 0x08000000 +#define SYNTH_SYNTH4_FORCE_PINVC_GET(x) (((x) & SYNTH_SYNTH4_FORCE_PINVC_MASK) >> SYNTH_SYNTH4_FORCE_PINVC_LSB) +#define SYNTH_SYNTH4_FORCE_PINVC_SET(x) (((x) << SYNTH_SYNTH4_FORCE_PINVC_LSB) & SYNTH_SYNTH4_FORCE_PINVC_MASK) +#define SYNTH_SYNTH4_FORCE_VCOCAP_MSB 26 +#define SYNTH_SYNTH4_FORCE_VCOCAP_LSB 26 +#define SYNTH_SYNTH4_FORCE_VCOCAP_MASK 0x04000000 +#define SYNTH_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK) >> SYNTH_SYNTH4_FORCE_VCOCAP_LSB) +#define SYNTH_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << SYNTH_SYNTH4_FORCE_VCOCAP_LSB) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK) +#define SYNTH_SYNTH4_VCOCAP_OVR_MSB 25 +#define SYNTH_SYNTH4_VCOCAP_OVR_LSB 18 +#define SYNTH_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000 +#define SYNTH_SYNTH4_VCOCAP_OVR_GET(x) (((x) & SYNTH_SYNTH4_VCOCAP_OVR_MASK) >> SYNTH_SYNTH4_VCOCAP_OVR_LSB) +#define SYNTH_SYNTH4_VCOCAP_OVR_SET(x) (((x) << SYNTH_SYNTH4_VCOCAP_OVR_LSB) & SYNTH_SYNTH4_VCOCAP_OVR_MASK) +#define SYNTH_SYNTH4_VCOCAPPULLUP_MSB 17 +#define SYNTH_SYNTH4_VCOCAPPULLUP_LSB 17 +#define SYNTH_SYNTH4_VCOCAPPULLUP_MASK 0x00020000 +#define SYNTH_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK) >> SYNTH_SYNTH4_VCOCAPPULLUP_LSB) +#define SYNTH_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << SYNTH_SYNTH4_VCOCAPPULLUP_LSB) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK) +#define SYNTH_SYNTH4_REFDIVSEL_MSB 16 +#define SYNTH_SYNTH4_REFDIVSEL_LSB 15 +#define SYNTH_SYNTH4_REFDIVSEL_MASK 0x00018000 +#define SYNTH_SYNTH4_REFDIVSEL_GET(x) (((x) & SYNTH_SYNTH4_REFDIVSEL_MASK) >> SYNTH_SYNTH4_REFDIVSEL_LSB) +#define SYNTH_SYNTH4_REFDIVSEL_SET(x) (((x) << SYNTH_SYNTH4_REFDIVSEL_LSB) & SYNTH_SYNTH4_REFDIVSEL_MASK) +#define SYNTH_SYNTH4_PFDDELAY_MSB 14 +#define SYNTH_SYNTH4_PFDDELAY_LSB 14 +#define SYNTH_SYNTH4_PFDDELAY_MASK 0x00004000 +#define SYNTH_SYNTH4_PFDDELAY_GET(x) (((x) & SYNTH_SYNTH4_PFDDELAY_MASK) >> SYNTH_SYNTH4_PFDDELAY_LSB) +#define SYNTH_SYNTH4_PFDDELAY_SET(x) (((x) << SYNTH_SYNTH4_PFDDELAY_LSB) & SYNTH_SYNTH4_PFDDELAY_MASK) +#define SYNTH_SYNTH4_PFD_DISABLE_MSB 13 +#define SYNTH_SYNTH4_PFD_DISABLE_LSB 13 +#define SYNTH_SYNTH4_PFD_DISABLE_MASK 0x00002000 +#define SYNTH_SYNTH4_PFD_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_PFD_DISABLE_MASK) >> SYNTH_SYNTH4_PFD_DISABLE_LSB) +#define SYNTH_SYNTH4_PFD_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_PFD_DISABLE_LSB) & SYNTH_SYNTH4_PFD_DISABLE_MASK) +#define SYNTH_SYNTH4_PRESCSEL_MSB 12 +#define SYNTH_SYNTH4_PRESCSEL_LSB 11 +#define SYNTH_SYNTH4_PRESCSEL_MASK 0x00001800 +#define SYNTH_SYNTH4_PRESCSEL_GET(x) (((x) & SYNTH_SYNTH4_PRESCSEL_MASK) >> SYNTH_SYNTH4_PRESCSEL_LSB) +#define SYNTH_SYNTH4_PRESCSEL_SET(x) (((x) << SYNTH_SYNTH4_PRESCSEL_LSB) & SYNTH_SYNTH4_PRESCSEL_MASK) +#define SYNTH_SYNTH4_RESET_PRESC_MSB 10 +#define SYNTH_SYNTH4_RESET_PRESC_LSB 10 +#define SYNTH_SYNTH4_RESET_PRESC_MASK 0x00000400 +#define SYNTH_SYNTH4_RESET_PRESC_GET(x) (((x) & SYNTH_SYNTH4_RESET_PRESC_MASK) >> SYNTH_SYNTH4_RESET_PRESC_LSB) +#define SYNTH_SYNTH4_RESET_PRESC_SET(x) (((x) << SYNTH_SYNTH4_RESET_PRESC_LSB) & SYNTH_SYNTH4_RESET_PRESC_MASK) +#define SYNTH_SYNTH4_SDM_DISABLE_MSB 9 +#define SYNTH_SYNTH4_SDM_DISABLE_LSB 9 +#define SYNTH_SYNTH4_SDM_DISABLE_MASK 0x00000200 +#define SYNTH_SYNTH4_SDM_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_SDM_DISABLE_MASK) >> SYNTH_SYNTH4_SDM_DISABLE_LSB) +#define SYNTH_SYNTH4_SDM_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_SDM_DISABLE_LSB) & SYNTH_SYNTH4_SDM_DISABLE_MASK) +#define SYNTH_SYNTH4_SDM_MODE_MSB 8 +#define SYNTH_SYNTH4_SDM_MODE_LSB 8 +#define SYNTH_SYNTH4_SDM_MODE_MASK 0x00000100 +#define SYNTH_SYNTH4_SDM_MODE_GET(x) (((x) & SYNTH_SYNTH4_SDM_MODE_MASK) >> SYNTH_SYNTH4_SDM_MODE_LSB) +#define SYNTH_SYNTH4_SDM_MODE_SET(x) (((x) << SYNTH_SYNTH4_SDM_MODE_LSB) & SYNTH_SYNTH4_SDM_MODE_MASK) +#define SYNTH_SYNTH4_SDM_DITHER_MSB 7 +#define SYNTH_SYNTH4_SDM_DITHER_LSB 6 +#define SYNTH_SYNTH4_SDM_DITHER_MASK 0x000000c0 +#define SYNTH_SYNTH4_SDM_DITHER_GET(x) (((x) & SYNTH_SYNTH4_SDM_DITHER_MASK) >> SYNTH_SYNTH4_SDM_DITHER_LSB) +#define SYNTH_SYNTH4_SDM_DITHER_SET(x) (((x) << SYNTH_SYNTH4_SDM_DITHER_LSB) & SYNTH_SYNTH4_SDM_DITHER_MASK) +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MSB 5 +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB 5 +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020 +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK) >> SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB) +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK) +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MSB 4 +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB 4 +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK 0x00000010 +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_GET(x) (((x) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK) >> SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB) +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_SET(x) (((x) << SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK) +#define SYNTH_SYNTH4_SPARE_MISC_MSB 3 +#define SYNTH_SYNTH4_SPARE_MISC_LSB 2 +#define SYNTH_SYNTH4_SPARE_MISC_MASK 0x0000000c +#define SYNTH_SYNTH4_SPARE_MISC_GET(x) (((x) & SYNTH_SYNTH4_SPARE_MISC_MASK) >> SYNTH_SYNTH4_SPARE_MISC_LSB) +#define SYNTH_SYNTH4_SPARE_MISC_SET(x) (((x) << SYNTH_SYNTH4_SPARE_MISC_LSB) & SYNTH_SYNTH4_SPARE_MISC_MASK) +#define SYNTH_SYNTH4_LONGSHIFTSEL_MSB 1 +#define SYNTH_SYNTH4_LONGSHIFTSEL_LSB 1 +#define SYNTH_SYNTH4_LONGSHIFTSEL_MASK 0x00000002 +#define SYNTH_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK) >> SYNTH_SYNTH4_LONGSHIFTSEL_LSB) +#define SYNTH_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << SYNTH_SYNTH4_LONGSHIFTSEL_LSB) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK) +#define SYNTH_SYNTH4_FORCE_SHIFTREG_MSB 0 +#define SYNTH_SYNTH4_FORCE_SHIFTREG_LSB 0 +#define SYNTH_SYNTH4_FORCE_SHIFTREG_MASK 0x00000001 +#define SYNTH_SYNTH4_FORCE_SHIFTREG_GET(x) (((x) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK) >> SYNTH_SYNTH4_FORCE_SHIFTREG_LSB) +#define SYNTH_SYNTH4_FORCE_SHIFTREG_SET(x) (((x) << SYNTH_SYNTH4_FORCE_SHIFTREG_LSB) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK) + +#define SYNTH_SYNTH5_ADDRESS 0x00000010 +#define SYNTH_SYNTH5_OFFSET 0x00000010 +#define SYNTH_SYNTH5_LOOP_IP0_MSB 31 +#define SYNTH_SYNTH5_LOOP_IP0_LSB 28 +#define SYNTH_SYNTH5_LOOP_IP0_MASK 0xf0000000 +#define SYNTH_SYNTH5_LOOP_IP0_GET(x) (((x) & SYNTH_SYNTH5_LOOP_IP0_MASK) >> SYNTH_SYNTH5_LOOP_IP0_LSB) +#define SYNTH_SYNTH5_LOOP_IP0_SET(x) (((x) << SYNTH_SYNTH5_LOOP_IP0_LSB) & SYNTH_SYNTH5_LOOP_IP0_MASK) +#define SYNTH_SYNTH5_SLOPE_IP_MSB 27 +#define SYNTH_SYNTH5_SLOPE_IP_LSB 25 +#define SYNTH_SYNTH5_SLOPE_IP_MASK 0x0e000000 +#define SYNTH_SYNTH5_SLOPE_IP_GET(x) (((x) & SYNTH_SYNTH5_SLOPE_IP_MASK) >> SYNTH_SYNTH5_SLOPE_IP_LSB) +#define SYNTH_SYNTH5_SLOPE_IP_SET(x) (((x) << SYNTH_SYNTH5_SLOPE_IP_LSB) & SYNTH_SYNTH5_SLOPE_IP_MASK) +#define SYNTH_SYNTH5_CPBIAS_MSB 24 +#define SYNTH_SYNTH5_CPBIAS_LSB 23 +#define SYNTH_SYNTH5_CPBIAS_MASK 0x01800000 +#define SYNTH_SYNTH5_CPBIAS_GET(x) (((x) & SYNTH_SYNTH5_CPBIAS_MASK) >> SYNTH_SYNTH5_CPBIAS_LSB) +#define SYNTH_SYNTH5_CPBIAS_SET(x) (((x) << SYNTH_SYNTH5_CPBIAS_LSB) & SYNTH_SYNTH5_CPBIAS_MASK) +#define SYNTH_SYNTH5_CPSTEERING_EN_MSB 22 +#define SYNTH_SYNTH5_CPSTEERING_EN_LSB 22 +#define SYNTH_SYNTH5_CPSTEERING_EN_MASK 0x00400000 +#define SYNTH_SYNTH5_CPSTEERING_EN_GET(x) (((x) & SYNTH_SYNTH5_CPSTEERING_EN_MASK) >> SYNTH_SYNTH5_CPSTEERING_EN_LSB) +#define SYNTH_SYNTH5_CPSTEERING_EN_SET(x) (((x) << SYNTH_SYNTH5_CPSTEERING_EN_LSB) & SYNTH_SYNTH5_CPSTEERING_EN_MASK) +#define SYNTH_SYNTH5_CPLOWLK_MSB 21 +#define SYNTH_SYNTH5_CPLOWLK_LSB 21 +#define SYNTH_SYNTH5_CPLOWLK_MASK 0x00200000 +#define SYNTH_SYNTH5_CPLOWLK_GET(x) (((x) & SYNTH_SYNTH5_CPLOWLK_MASK) >> SYNTH_SYNTH5_CPLOWLK_LSB) +#define SYNTH_SYNTH5_CPLOWLK_SET(x) (((x) << SYNTH_SYNTH5_CPLOWLK_LSB) & SYNTH_SYNTH5_CPLOWLK_MASK) +#define SYNTH_SYNTH5_LOOPLEAKCUR_MSB 20 +#define SYNTH_SYNTH5_LOOPLEAKCUR_LSB 17 +#define SYNTH_SYNTH5_LOOPLEAKCUR_MASK 0x001e0000 +#define SYNTH_SYNTH5_LOOPLEAKCUR_GET(x) (((x) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK) >> SYNTH_SYNTH5_LOOPLEAKCUR_LSB) +#define SYNTH_SYNTH5_LOOPLEAKCUR_SET(x) (((x) << SYNTH_SYNTH5_LOOPLEAKCUR_LSB) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK) +#define SYNTH_SYNTH5_CAPRANGE1_MSB 16 +#define SYNTH_SYNTH5_CAPRANGE1_LSB 13 +#define SYNTH_SYNTH5_CAPRANGE1_MASK 0x0001e000 +#define SYNTH_SYNTH5_CAPRANGE1_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE1_MASK) >> SYNTH_SYNTH5_CAPRANGE1_LSB) +#define SYNTH_SYNTH5_CAPRANGE1_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE1_LSB) & SYNTH_SYNTH5_CAPRANGE1_MASK) +#define SYNTH_SYNTH5_CAPRANGE2_MSB 12 +#define SYNTH_SYNTH5_CAPRANGE2_LSB 9 +#define SYNTH_SYNTH5_CAPRANGE2_MASK 0x00001e00 +#define SYNTH_SYNTH5_CAPRANGE2_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE2_MASK) >> SYNTH_SYNTH5_CAPRANGE2_LSB) +#define SYNTH_SYNTH5_CAPRANGE2_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE2_LSB) & SYNTH_SYNTH5_CAPRANGE2_MASK) +#define SYNTH_SYNTH5_CAPRANGE3_MSB 8 +#define SYNTH_SYNTH5_CAPRANGE3_LSB 5 +#define SYNTH_SYNTH5_CAPRANGE3_MASK 0x000001e0 +#define SYNTH_SYNTH5_CAPRANGE3_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE3_MASK) >> SYNTH_SYNTH5_CAPRANGE3_LSB) +#define SYNTH_SYNTH5_CAPRANGE3_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE3_LSB) & SYNTH_SYNTH5_CAPRANGE3_MASK) +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MSB 4 +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB 4 +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK 0x00000010 +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB) +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK) +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MSB 3 +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB 2 +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK 0x0000000c +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_GET(x) (((x) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK) >> SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB) +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_SET(x) (((x) << SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK) +#define SYNTH_SYNTH5_SPARE_MSB 1 +#define SYNTH_SYNTH5_SPARE_LSB 0 +#define SYNTH_SYNTH5_SPARE_MASK 0x00000003 +#define SYNTH_SYNTH5_SPARE_GET(x) (((x) & SYNTH_SYNTH5_SPARE_MASK) >> SYNTH_SYNTH5_SPARE_LSB) +#define SYNTH_SYNTH5_SPARE_SET(x) (((x) << SYNTH_SYNTH5_SPARE_LSB) & SYNTH_SYNTH5_SPARE_MASK) + +#define SYNTH_SYNTH6_ADDRESS 0x00000014 +#define SYNTH_SYNTH6_OFFSET 0x00000014 +#define SYNTH_SYNTH6_IRCP_MSB 31 +#define SYNTH_SYNTH6_IRCP_LSB 29 +#define SYNTH_SYNTH6_IRCP_MASK 0xe0000000 +#define SYNTH_SYNTH6_IRCP_GET(x) (((x) & SYNTH_SYNTH6_IRCP_MASK) >> SYNTH_SYNTH6_IRCP_LSB) +#define SYNTH_SYNTH6_IRCP_SET(x) (((x) << SYNTH_SYNTH6_IRCP_LSB) & SYNTH_SYNTH6_IRCP_MASK) +#define SYNTH_SYNTH6_IRVCMON_MSB 28 +#define SYNTH_SYNTH6_IRVCMON_LSB 26 +#define SYNTH_SYNTH6_IRVCMON_MASK 0x1c000000 +#define SYNTH_SYNTH6_IRVCMON_GET(x) (((x) & SYNTH_SYNTH6_IRVCMON_MASK) >> SYNTH_SYNTH6_IRVCMON_LSB) +#define SYNTH_SYNTH6_IRVCMON_SET(x) (((x) << SYNTH_SYNTH6_IRVCMON_LSB) & SYNTH_SYNTH6_IRVCMON_MASK) +#define SYNTH_SYNTH6_IRSPARE_MSB 25 +#define SYNTH_SYNTH6_IRSPARE_LSB 23 +#define SYNTH_SYNTH6_IRSPARE_MASK 0x03800000 +#define SYNTH_SYNTH6_IRSPARE_GET(x) (((x) & SYNTH_SYNTH6_IRSPARE_MASK) >> SYNTH_SYNTH6_IRSPARE_LSB) +#define SYNTH_SYNTH6_IRSPARE_SET(x) (((x) << SYNTH_SYNTH6_IRSPARE_LSB) & SYNTH_SYNTH6_IRSPARE_MASK) +#define SYNTH_SYNTH6_ICPRESC_MSB 22 +#define SYNTH_SYNTH6_ICPRESC_LSB 20 +#define SYNTH_SYNTH6_ICPRESC_MASK 0x00700000 +#define SYNTH_SYNTH6_ICPRESC_GET(x) (((x) & SYNTH_SYNTH6_ICPRESC_MASK) >> SYNTH_SYNTH6_ICPRESC_LSB) +#define SYNTH_SYNTH6_ICPRESC_SET(x) (((x) << SYNTH_SYNTH6_ICPRESC_LSB) & SYNTH_SYNTH6_ICPRESC_MASK) +#define SYNTH_SYNTH6_ICLODIV_MSB 19 +#define SYNTH_SYNTH6_ICLODIV_LSB 17 +#define SYNTH_SYNTH6_ICLODIV_MASK 0x000e0000 +#define SYNTH_SYNTH6_ICLODIV_GET(x) (((x) & SYNTH_SYNTH6_ICLODIV_MASK) >> SYNTH_SYNTH6_ICLODIV_LSB) +#define SYNTH_SYNTH6_ICLODIV_SET(x) (((x) << SYNTH_SYNTH6_ICLODIV_LSB) & SYNTH_SYNTH6_ICLODIV_MASK) +#define SYNTH_SYNTH6_ICLOMIX_MSB 16 +#define SYNTH_SYNTH6_ICLOMIX_LSB 14 +#define SYNTH_SYNTH6_ICLOMIX_MASK 0x0001c000 +#define SYNTH_SYNTH6_ICLOMIX_GET(x) (((x) & SYNTH_SYNTH6_ICLOMIX_MASK) >> SYNTH_SYNTH6_ICLOMIX_LSB) +#define SYNTH_SYNTH6_ICLOMIX_SET(x) (((x) << SYNTH_SYNTH6_ICLOMIX_LSB) & SYNTH_SYNTH6_ICLOMIX_MASK) +#define SYNTH_SYNTH6_ICSPAREA_MSB 13 +#define SYNTH_SYNTH6_ICSPAREA_LSB 11 +#define SYNTH_SYNTH6_ICSPAREA_MASK 0x00003800 +#define SYNTH_SYNTH6_ICSPAREA_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREA_MASK) >> SYNTH_SYNTH6_ICSPAREA_LSB) +#define SYNTH_SYNTH6_ICSPAREA_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREA_LSB) & SYNTH_SYNTH6_ICSPAREA_MASK) +#define SYNTH_SYNTH6_ICSPAREB_MSB 10 +#define SYNTH_SYNTH6_ICSPAREB_LSB 8 +#define SYNTH_SYNTH6_ICSPAREB_MASK 0x00000700 +#define SYNTH_SYNTH6_ICSPAREB_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREB_MASK) >> SYNTH_SYNTH6_ICSPAREB_LSB) +#define SYNTH_SYNTH6_ICSPAREB_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREB_LSB) & SYNTH_SYNTH6_ICSPAREB_MASK) +#define SYNTH_SYNTH6_ICVCO_MSB 7 +#define SYNTH_SYNTH6_ICVCO_LSB 5 +#define SYNTH_SYNTH6_ICVCO_MASK 0x000000e0 +#define SYNTH_SYNTH6_ICVCO_GET(x) (((x) & SYNTH_SYNTH6_ICVCO_MASK) >> SYNTH_SYNTH6_ICVCO_LSB) +#define SYNTH_SYNTH6_ICVCO_SET(x) (((x) << SYNTH_SYNTH6_ICVCO_LSB) & SYNTH_SYNTH6_ICVCO_MASK) +#define SYNTH_SYNTH6_VCOBUFBIAS_MSB 4 +#define SYNTH_SYNTH6_VCOBUFBIAS_LSB 3 +#define SYNTH_SYNTH6_VCOBUFBIAS_MASK 0x00000018 +#define SYNTH_SYNTH6_VCOBUFBIAS_GET(x) (((x) & SYNTH_SYNTH6_VCOBUFBIAS_MASK) >> SYNTH_SYNTH6_VCOBUFBIAS_LSB) +#define SYNTH_SYNTH6_VCOBUFBIAS_SET(x) (((x) << SYNTH_SYNTH6_VCOBUFBIAS_LSB) & SYNTH_SYNTH6_VCOBUFBIAS_MASK) +#define SYNTH_SYNTH6_SPARE_BIAS_MSB 2 +#define SYNTH_SYNTH6_SPARE_BIAS_LSB 0 +#define SYNTH_SYNTH6_SPARE_BIAS_MASK 0x00000007 +#define SYNTH_SYNTH6_SPARE_BIAS_GET(x) (((x) & SYNTH_SYNTH6_SPARE_BIAS_MASK) >> SYNTH_SYNTH6_SPARE_BIAS_LSB) +#define SYNTH_SYNTH6_SPARE_BIAS_SET(x) (((x) << SYNTH_SYNTH6_SPARE_BIAS_LSB) & SYNTH_SYNTH6_SPARE_BIAS_MASK) + +#define SYNTH_SYNTH7_ADDRESS 0x00000018 +#define SYNTH_SYNTH7_OFFSET 0x00000018 +#define SYNTH_SYNTH7_SYNTH_ON_MSB 31 +#define SYNTH_SYNTH7_SYNTH_ON_LSB 31 +#define SYNTH_SYNTH7_SYNTH_ON_MASK 0x80000000 +#define SYNTH_SYNTH7_SYNTH_ON_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_ON_MASK) >> SYNTH_SYNTH7_SYNTH_ON_LSB) +#define SYNTH_SYNTH7_SYNTH_ON_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_ON_LSB) & SYNTH_SYNTH7_SYNTH_ON_MASK) +#define SYNTH_SYNTH7_SYNTH_SM_STATE_MSB 30 +#define SYNTH_SYNTH7_SYNTH_SM_STATE_LSB 27 +#define SYNTH_SYNTH7_SYNTH_SM_STATE_MASK 0x78000000 +#define SYNTH_SYNTH7_SYNTH_SM_STATE_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK) >> SYNTH_SYNTH7_SYNTH_SM_STATE_LSB) +#define SYNTH_SYNTH7_SYNTH_SM_STATE_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_SM_STATE_LSB) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK) +#define SYNTH_SYNTH7_CAP_SEARCH_MSB 26 +#define SYNTH_SYNTH7_CAP_SEARCH_LSB 26 +#define SYNTH_SYNTH7_CAP_SEARCH_MASK 0x04000000 +#define SYNTH_SYNTH7_CAP_SEARCH_GET(x) (((x) & SYNTH_SYNTH7_CAP_SEARCH_MASK) >> SYNTH_SYNTH7_CAP_SEARCH_LSB) +#define SYNTH_SYNTH7_CAP_SEARCH_SET(x) (((x) << SYNTH_SYNTH7_CAP_SEARCH_LSB) & SYNTH_SYNTH7_CAP_SEARCH_MASK) +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MSB 25 +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB 25 +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK 0x02000000 +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK) >> SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB) +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK) +#define SYNTH_SYNTH7_PIN_VC_MSB 24 +#define SYNTH_SYNTH7_PIN_VC_LSB 24 +#define SYNTH_SYNTH7_PIN_VC_MASK 0x01000000 +#define SYNTH_SYNTH7_PIN_VC_GET(x) (((x) & SYNTH_SYNTH7_PIN_VC_MASK) >> SYNTH_SYNTH7_PIN_VC_LSB) +#define SYNTH_SYNTH7_PIN_VC_SET(x) (((x) << SYNTH_SYNTH7_PIN_VC_LSB) & SYNTH_SYNTH7_PIN_VC_MASK) +#define SYNTH_SYNTH7_VCO_CAP_ST_MSB 23 +#define SYNTH_SYNTH7_VCO_CAP_ST_LSB 16 +#define SYNTH_SYNTH7_VCO_CAP_ST_MASK 0x00ff0000 +#define SYNTH_SYNTH7_VCO_CAP_ST_GET(x) (((x) & SYNTH_SYNTH7_VCO_CAP_ST_MASK) >> SYNTH_SYNTH7_VCO_CAP_ST_LSB) +#define SYNTH_SYNTH7_VCO_CAP_ST_SET(x) (((x) << SYNTH_SYNTH7_VCO_CAP_ST_LSB) & SYNTH_SYNTH7_VCO_CAP_ST_MASK) +#define SYNTH_SYNTH7_SHORT_R_MSB 15 +#define SYNTH_SYNTH7_SHORT_R_LSB 15 +#define SYNTH_SYNTH7_SHORT_R_MASK 0x00008000 +#define SYNTH_SYNTH7_SHORT_R_GET(x) (((x) & SYNTH_SYNTH7_SHORT_R_MASK) >> SYNTH_SYNTH7_SHORT_R_LSB) +#define SYNTH_SYNTH7_SHORT_R_SET(x) (((x) << SYNTH_SYNTH7_SHORT_R_LSB) & SYNTH_SYNTH7_SHORT_R_MASK) +#define SYNTH_SYNTH7_RESET_RFD_MSB 14 +#define SYNTH_SYNTH7_RESET_RFD_LSB 14 +#define SYNTH_SYNTH7_RESET_RFD_MASK 0x00004000 +#define SYNTH_SYNTH7_RESET_RFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_RFD_MASK) >> SYNTH_SYNTH7_RESET_RFD_LSB) +#define SYNTH_SYNTH7_RESET_RFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_RFD_LSB) & SYNTH_SYNTH7_RESET_RFD_MASK) +#define SYNTH_SYNTH7_RESET_PFD_MSB 13 +#define SYNTH_SYNTH7_RESET_PFD_LSB 13 +#define SYNTH_SYNTH7_RESET_PFD_MASK 0x00002000 +#define SYNTH_SYNTH7_RESET_PFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_PFD_MASK) >> SYNTH_SYNTH7_RESET_PFD_LSB) +#define SYNTH_SYNTH7_RESET_PFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_PFD_LSB) & SYNTH_SYNTH7_RESET_PFD_MASK) +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MSB 12 +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB 12 +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK 0x00001000 +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_GET(x) (((x) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK) >> SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB) +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_SET(x) (((x) << SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK) +#define SYNTH_SYNTH7_RESET_SDM_B_MSB 11 +#define SYNTH_SYNTH7_RESET_SDM_B_LSB 11 +#define SYNTH_SYNTH7_RESET_SDM_B_MASK 0x00000800 +#define SYNTH_SYNTH7_RESET_SDM_B_GET(x) (((x) & SYNTH_SYNTH7_RESET_SDM_B_MASK) >> SYNTH_SYNTH7_RESET_SDM_B_LSB) +#define SYNTH_SYNTH7_RESET_SDM_B_SET(x) (((x) << SYNTH_SYNTH7_RESET_SDM_B_LSB) & SYNTH_SYNTH7_RESET_SDM_B_MASK) +#define SYNTH_SYNTH7_VC2HIGH_MSB 10 +#define SYNTH_SYNTH7_VC2HIGH_LSB 10 +#define SYNTH_SYNTH7_VC2HIGH_MASK 0x00000400 +#define SYNTH_SYNTH7_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH7_VC2HIGH_MASK) >> SYNTH_SYNTH7_VC2HIGH_LSB) +#define SYNTH_SYNTH7_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH7_VC2HIGH_LSB) & SYNTH_SYNTH7_VC2HIGH_MASK) +#define SYNTH_SYNTH7_VC2LOW_MSB 9 +#define SYNTH_SYNTH7_VC2LOW_LSB 9 +#define SYNTH_SYNTH7_VC2LOW_MASK 0x00000200 +#define SYNTH_SYNTH7_VC2LOW_GET(x) (((x) & SYNTH_SYNTH7_VC2LOW_MASK) >> SYNTH_SYNTH7_VC2LOW_LSB) +#define SYNTH_SYNTH7_VC2LOW_SET(x) (((x) << SYNTH_SYNTH7_VC2LOW_LSB) & SYNTH_SYNTH7_VC2LOW_MASK) +#define SYNTH_SYNTH7_LOOP_IP_MSB 8 +#define SYNTH_SYNTH7_LOOP_IP_LSB 5 +#define SYNTH_SYNTH7_LOOP_IP_MASK 0x000001e0 +#define SYNTH_SYNTH7_LOOP_IP_GET(x) (((x) & SYNTH_SYNTH7_LOOP_IP_MASK) >> SYNTH_SYNTH7_LOOP_IP_LSB) +#define SYNTH_SYNTH7_LOOP_IP_SET(x) (((x) << SYNTH_SYNTH7_LOOP_IP_LSB) & SYNTH_SYNTH7_LOOP_IP_MASK) +#define SYNTH_SYNTH7_LOBUF5GTUNE_MSB 4 +#define SYNTH_SYNTH7_LOBUF5GTUNE_LSB 3 +#define SYNTH_SYNTH7_LOBUF5GTUNE_MASK 0x00000018 +#define SYNTH_SYNTH7_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH7_LOBUF5GTUNE_LSB) +#define SYNTH_SYNTH7_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH7_LOBUF5GTUNE_LSB) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK) +#define SYNTH_SYNTH7_SPARE_READ_MSB 2 +#define SYNTH_SYNTH7_SPARE_READ_LSB 0 +#define SYNTH_SYNTH7_SPARE_READ_MASK 0x00000007 +#define SYNTH_SYNTH7_SPARE_READ_GET(x) (((x) & SYNTH_SYNTH7_SPARE_READ_MASK) >> SYNTH_SYNTH7_SPARE_READ_LSB) +#define SYNTH_SYNTH7_SPARE_READ_SET(x) (((x) << SYNTH_SYNTH7_SPARE_READ_LSB) & SYNTH_SYNTH7_SPARE_READ_MASK) + +#define SYNTH_SYNTH8_ADDRESS 0x0000001c +#define SYNTH_SYNTH8_OFFSET 0x0000001c +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MSB 31 +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB 31 +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK 0x80000000 +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_GET(x) (((x) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK) >> SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB) +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_SET(x) (((x) << SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK) +#define SYNTH_SYNTH8_FRACMODE_MSB 30 +#define SYNTH_SYNTH8_FRACMODE_LSB 30 +#define SYNTH_SYNTH8_FRACMODE_MASK 0x40000000 +#define SYNTH_SYNTH8_FRACMODE_GET(x) (((x) & SYNTH_SYNTH8_FRACMODE_MASK) >> SYNTH_SYNTH8_FRACMODE_LSB) +#define SYNTH_SYNTH8_FRACMODE_SET(x) (((x) << SYNTH_SYNTH8_FRACMODE_LSB) & SYNTH_SYNTH8_FRACMODE_MASK) +#define SYNTH_SYNTH8_AMODEREFSEL_MSB 29 +#define SYNTH_SYNTH8_AMODEREFSEL_LSB 28 +#define SYNTH_SYNTH8_AMODEREFSEL_MASK 0x30000000 +#define SYNTH_SYNTH8_AMODEREFSEL_GET(x) (((x) & SYNTH_SYNTH8_AMODEREFSEL_MASK) >> SYNTH_SYNTH8_AMODEREFSEL_LSB) +#define SYNTH_SYNTH8_AMODEREFSEL_SET(x) (((x) << SYNTH_SYNTH8_AMODEREFSEL_LSB) & SYNTH_SYNTH8_AMODEREFSEL_MASK) +#define SYNTH_SYNTH8_SPARE_MSB 27 +#define SYNTH_SYNTH8_SPARE_LSB 27 +#define SYNTH_SYNTH8_SPARE_MASK 0x08000000 +#define SYNTH_SYNTH8_SPARE_GET(x) (((x) & SYNTH_SYNTH8_SPARE_MASK) >> SYNTH_SYNTH8_SPARE_LSB) +#define SYNTH_SYNTH8_SPARE_SET(x) (((x) << SYNTH_SYNTH8_SPARE_LSB) & SYNTH_SYNTH8_SPARE_MASK) +#define SYNTH_SYNTH8_CHANSEL_MSB 26 +#define SYNTH_SYNTH8_CHANSEL_LSB 18 +#define SYNTH_SYNTH8_CHANSEL_MASK 0x07fc0000 +#define SYNTH_SYNTH8_CHANSEL_GET(x) (((x) & SYNTH_SYNTH8_CHANSEL_MASK) >> SYNTH_SYNTH8_CHANSEL_LSB) +#define SYNTH_SYNTH8_CHANSEL_SET(x) (((x) << SYNTH_SYNTH8_CHANSEL_LSB) & SYNTH_SYNTH8_CHANSEL_MASK) +#define SYNTH_SYNTH8_CHANFRAC_MSB 17 +#define SYNTH_SYNTH8_CHANFRAC_LSB 1 +#define SYNTH_SYNTH8_CHANFRAC_MASK 0x0003fffe +#define SYNTH_SYNTH8_CHANFRAC_GET(x) (((x) & SYNTH_SYNTH8_CHANFRAC_MASK) >> SYNTH_SYNTH8_CHANFRAC_LSB) +#define SYNTH_SYNTH8_CHANFRAC_SET(x) (((x) << SYNTH_SYNTH8_CHANFRAC_LSB) & SYNTH_SYNTH8_CHANFRAC_MASK) +#define SYNTH_SYNTH8_FORCE_FRACLSB_MSB 0 +#define SYNTH_SYNTH8_FORCE_FRACLSB_LSB 0 +#define SYNTH_SYNTH8_FORCE_FRACLSB_MASK 0x00000001 +#define SYNTH_SYNTH8_FORCE_FRACLSB_GET(x) (((x) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK) >> SYNTH_SYNTH8_FORCE_FRACLSB_LSB) +#define SYNTH_SYNTH8_FORCE_FRACLSB_SET(x) (((x) << SYNTH_SYNTH8_FORCE_FRACLSB_LSB) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK) + +#define RF5G_RF5G1_ADDRESS 0x00000020 +#define RF5G_RF5G1_OFFSET 0x00000020 +#define RF5G_RF5G1_PDTXLO5_MSB 31 +#define RF5G_RF5G1_PDTXLO5_LSB 31 +#define RF5G_RF5G1_PDTXLO5_MASK 0x80000000 +#define RF5G_RF5G1_PDTXLO5_GET(x) (((x) & RF5G_RF5G1_PDTXLO5_MASK) >> RF5G_RF5G1_PDTXLO5_LSB) +#define RF5G_RF5G1_PDTXLO5_SET(x) (((x) << RF5G_RF5G1_PDTXLO5_LSB) & RF5G_RF5G1_PDTXLO5_MASK) +#define RF5G_RF5G1_PDTXMIX5_MSB 30 +#define RF5G_RF5G1_PDTXMIX5_LSB 30 +#define RF5G_RF5G1_PDTXMIX5_MASK 0x40000000 +#define RF5G_RF5G1_PDTXMIX5_GET(x) (((x) & RF5G_RF5G1_PDTXMIX5_MASK) >> RF5G_RF5G1_PDTXMIX5_LSB) +#define RF5G_RF5G1_PDTXMIX5_SET(x) (((x) << RF5G_RF5G1_PDTXMIX5_LSB) & RF5G_RF5G1_PDTXMIX5_MASK) +#define RF5G_RF5G1_PDTXBUF5_MSB 29 +#define RF5G_RF5G1_PDTXBUF5_LSB 29 +#define RF5G_RF5G1_PDTXBUF5_MASK 0x20000000 +#define RF5G_RF5G1_PDTXBUF5_GET(x) (((x) & RF5G_RF5G1_PDTXBUF5_MASK) >> RF5G_RF5G1_PDTXBUF5_LSB) +#define RF5G_RF5G1_PDTXBUF5_SET(x) (((x) << RF5G_RF5G1_PDTXBUF5_LSB) & RF5G_RF5G1_PDTXBUF5_MASK) +#define RF5G_RF5G1_PDPADRV5_MSB 28 +#define RF5G_RF5G1_PDPADRV5_LSB 28 +#define RF5G_RF5G1_PDPADRV5_MASK 0x10000000 +#define RF5G_RF5G1_PDPADRV5_GET(x) (((x) & RF5G_RF5G1_PDPADRV5_MASK) >> RF5G_RF5G1_PDPADRV5_LSB) +#define RF5G_RF5G1_PDPADRV5_SET(x) (((x) << RF5G_RF5G1_PDPADRV5_LSB) & RF5G_RF5G1_PDPADRV5_MASK) +#define RF5G_RF5G1_PDPAOUT5_MSB 27 +#define RF5G_RF5G1_PDPAOUT5_LSB 27 +#define RF5G_RF5G1_PDPAOUT5_MASK 0x08000000 +#define RF5G_RF5G1_PDPAOUT5_GET(x) (((x) & RF5G_RF5G1_PDPAOUT5_MASK) >> RF5G_RF5G1_PDPAOUT5_LSB) +#define RF5G_RF5G1_PDPAOUT5_SET(x) (((x) << RF5G_RF5G1_PDPAOUT5_LSB) & RF5G_RF5G1_PDPAOUT5_MASK) +#define RF5G_RF5G1_TUNE_PADRV5_MSB 26 +#define RF5G_RF5G1_TUNE_PADRV5_LSB 24 +#define RF5G_RF5G1_TUNE_PADRV5_MASK 0x07000000 +#define RF5G_RF5G1_TUNE_PADRV5_GET(x) (((x) & RF5G_RF5G1_TUNE_PADRV5_MASK) >> RF5G_RF5G1_TUNE_PADRV5_LSB) +#define RF5G_RF5G1_TUNE_PADRV5_SET(x) (((x) << RF5G_RF5G1_TUNE_PADRV5_LSB) & RF5G_RF5G1_TUNE_PADRV5_MASK) +#define RF5G_RF5G1_PWDTXPKD_MSB 23 +#define RF5G_RF5G1_PWDTXPKD_LSB 21 +#define RF5G_RF5G1_PWDTXPKD_MASK 0x00e00000 +#define RF5G_RF5G1_PWDTXPKD_GET(x) (((x) & RF5G_RF5G1_PWDTXPKD_MASK) >> RF5G_RF5G1_PWDTXPKD_LSB) +#define RF5G_RF5G1_PWDTXPKD_SET(x) (((x) << RF5G_RF5G1_PWDTXPKD_LSB) & RF5G_RF5G1_PWDTXPKD_MASK) +#define RF5G_RF5G1_DB5_MSB 20 +#define RF5G_RF5G1_DB5_LSB 18 +#define RF5G_RF5G1_DB5_MASK 0x001c0000 +#define RF5G_RF5G1_DB5_GET(x) (((x) & RF5G_RF5G1_DB5_MASK) >> RF5G_RF5G1_DB5_LSB) +#define RF5G_RF5G1_DB5_SET(x) (((x) << RF5G_RF5G1_DB5_LSB) & RF5G_RF5G1_DB5_MASK) +#define RF5G_RF5G1_OB5_MSB 17 +#define RF5G_RF5G1_OB5_LSB 15 +#define RF5G_RF5G1_OB5_MASK 0x00038000 +#define RF5G_RF5G1_OB5_GET(x) (((x) & RF5G_RF5G1_OB5_MASK) >> RF5G_RF5G1_OB5_LSB) +#define RF5G_RF5G1_OB5_SET(x) (((x) << RF5G_RF5G1_OB5_LSB) & RF5G_RF5G1_OB5_MASK) +#define RF5G_RF5G1_TX5_ATB_SEL_MSB 14 +#define RF5G_RF5G1_TX5_ATB_SEL_LSB 12 +#define RF5G_RF5G1_TX5_ATB_SEL_MASK 0x00007000 +#define RF5G_RF5G1_TX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_TX5_ATB_SEL_MASK) >> RF5G_RF5G1_TX5_ATB_SEL_LSB) +#define RF5G_RF5G1_TX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_TX5_ATB_SEL_LSB) & RF5G_RF5G1_TX5_ATB_SEL_MASK) +#define RF5G_RF5G1_PDLO5DIV_MSB 11 +#define RF5G_RF5G1_PDLO5DIV_LSB 11 +#define RF5G_RF5G1_PDLO5DIV_MASK 0x00000800 +#define RF5G_RF5G1_PDLO5DIV_GET(x) (((x) & RF5G_RF5G1_PDLO5DIV_MASK) >> RF5G_RF5G1_PDLO5DIV_LSB) +#define RF5G_RF5G1_PDLO5DIV_SET(x) (((x) << RF5G_RF5G1_PDLO5DIV_LSB) & RF5G_RF5G1_PDLO5DIV_MASK) +#define RF5G_RF5G1_PDLO5MIX_MSB 10 +#define RF5G_RF5G1_PDLO5MIX_LSB 10 +#define RF5G_RF5G1_PDLO5MIX_MASK 0x00000400 +#define RF5G_RF5G1_PDLO5MIX_GET(x) (((x) & RF5G_RF5G1_PDLO5MIX_MASK) >> RF5G_RF5G1_PDLO5MIX_LSB) +#define RF5G_RF5G1_PDLO5MIX_SET(x) (((x) << RF5G_RF5G1_PDLO5MIX_LSB) & RF5G_RF5G1_PDLO5MIX_MASK) +#define RF5G_RF5G1_PDQBUF5_MSB 9 +#define RF5G_RF5G1_PDQBUF5_LSB 9 +#define RF5G_RF5G1_PDQBUF5_MASK 0x00000200 +#define RF5G_RF5G1_PDQBUF5_GET(x) (((x) & RF5G_RF5G1_PDQBUF5_MASK) >> RF5G_RF5G1_PDQBUF5_LSB) +#define RF5G_RF5G1_PDQBUF5_SET(x) (((x) << RF5G_RF5G1_PDQBUF5_LSB) & RF5G_RF5G1_PDQBUF5_MASK) +#define RF5G_RF5G1_PDLO5AGC_MSB 8 +#define RF5G_RF5G1_PDLO5AGC_LSB 8 +#define RF5G_RF5G1_PDLO5AGC_MASK 0x00000100 +#define RF5G_RF5G1_PDLO5AGC_GET(x) (((x) & RF5G_RF5G1_PDLO5AGC_MASK) >> RF5G_RF5G1_PDLO5AGC_LSB) +#define RF5G_RF5G1_PDLO5AGC_SET(x) (((x) << RF5G_RF5G1_PDLO5AGC_LSB) & RF5G_RF5G1_PDLO5AGC_MASK) +#define RF5G_RF5G1_PDREGLO5_MSB 7 +#define RF5G_RF5G1_PDREGLO5_LSB 7 +#define RF5G_RF5G1_PDREGLO5_MASK 0x00000080 +#define RF5G_RF5G1_PDREGLO5_GET(x) (((x) & RF5G_RF5G1_PDREGLO5_MASK) >> RF5G_RF5G1_PDREGLO5_LSB) +#define RF5G_RF5G1_PDREGLO5_SET(x) (((x) << RF5G_RF5G1_PDREGLO5_LSB) & RF5G_RF5G1_PDREGLO5_MASK) +#define RF5G_RF5G1_LO5_ATB_SEL_MSB 6 +#define RF5G_RF5G1_LO5_ATB_SEL_LSB 4 +#define RF5G_RF5G1_LO5_ATB_SEL_MASK 0x00000070 +#define RF5G_RF5G1_LO5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_LO5_ATB_SEL_MASK) >> RF5G_RF5G1_LO5_ATB_SEL_LSB) +#define RF5G_RF5G1_LO5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_LO5_ATB_SEL_LSB) & RF5G_RF5G1_LO5_ATB_SEL_MASK) +#define RF5G_RF5G1_LO5CONTROL_MSB 3 +#define RF5G_RF5G1_LO5CONTROL_LSB 3 +#define RF5G_RF5G1_LO5CONTROL_MASK 0x00000008 +#define RF5G_RF5G1_LO5CONTROL_GET(x) (((x) & RF5G_RF5G1_LO5CONTROL_MASK) >> RF5G_RF5G1_LO5CONTROL_LSB) +#define RF5G_RF5G1_LO5CONTROL_SET(x) (((x) << RF5G_RF5G1_LO5CONTROL_LSB) & RF5G_RF5G1_LO5CONTROL_MASK) +#define RF5G_RF5G1_REGLO_BYPASS5_MSB 2 +#define RF5G_RF5G1_REGLO_BYPASS5_LSB 2 +#define RF5G_RF5G1_REGLO_BYPASS5_MASK 0x00000004 +#define RF5G_RF5G1_REGLO_BYPASS5_GET(x) (((x) & RF5G_RF5G1_REGLO_BYPASS5_MASK) >> RF5G_RF5G1_REGLO_BYPASS5_LSB) +#define RF5G_RF5G1_REGLO_BYPASS5_SET(x) (((x) << RF5G_RF5G1_REGLO_BYPASS5_LSB) & RF5G_RF5G1_REGLO_BYPASS5_MASK) +#define RF5G_RF5G1_SPARE_MSB 1 +#define RF5G_RF5G1_SPARE_LSB 0 +#define RF5G_RF5G1_SPARE_MASK 0x00000003 +#define RF5G_RF5G1_SPARE_GET(x) (((x) & RF5G_RF5G1_SPARE_MASK) >> RF5G_RF5G1_SPARE_LSB) +#define RF5G_RF5G1_SPARE_SET(x) (((x) << RF5G_RF5G1_SPARE_LSB) & RF5G_RF5G1_SPARE_MASK) + +#define RF5G_RF5G2_ADDRESS 0x00000024 +#define RF5G_RF5G2_OFFSET 0x00000024 +#define RF5G_RF5G2_AGCLO_B_MSB 31 +#define RF5G_RF5G2_AGCLO_B_LSB 29 +#define RF5G_RF5G2_AGCLO_B_MASK 0xe0000000 +#define RF5G_RF5G2_AGCLO_B_GET(x) (((x) & RF5G_RF5G2_AGCLO_B_MASK) >> RF5G_RF5G2_AGCLO_B_LSB) +#define RF5G_RF5G2_AGCLO_B_SET(x) (((x) << RF5G_RF5G2_AGCLO_B_LSB) & RF5G_RF5G2_AGCLO_B_MASK) +#define RF5G_RF5G2_RX5_ATB_SEL_MSB 28 +#define RF5G_RF5G2_RX5_ATB_SEL_LSB 26 +#define RF5G_RF5G2_RX5_ATB_SEL_MASK 0x1c000000 +#define RF5G_RF5G2_RX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G2_RX5_ATB_SEL_MASK) >> RF5G_RF5G2_RX5_ATB_SEL_LSB) +#define RF5G_RF5G2_RX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G2_RX5_ATB_SEL_LSB) & RF5G_RF5G2_RX5_ATB_SEL_MASK) +#define RF5G_RF5G2_PDCMOSLO5_MSB 25 +#define RF5G_RF5G2_PDCMOSLO5_LSB 25 +#define RF5G_RF5G2_PDCMOSLO5_MASK 0x02000000 +#define RF5G_RF5G2_PDCMOSLO5_GET(x) (((x) & RF5G_RF5G2_PDCMOSLO5_MASK) >> RF5G_RF5G2_PDCMOSLO5_LSB) +#define RF5G_RF5G2_PDCMOSLO5_SET(x) (((x) << RF5G_RF5G2_PDCMOSLO5_LSB) & RF5G_RF5G2_PDCMOSLO5_MASK) +#define RF5G_RF5G2_PDVGM5_MSB 24 +#define RF5G_RF5G2_PDVGM5_LSB 24 +#define RF5G_RF5G2_PDVGM5_MASK 0x01000000 +#define RF5G_RF5G2_PDVGM5_GET(x) (((x) & RF5G_RF5G2_PDVGM5_MASK) >> RF5G_RF5G2_PDVGM5_LSB) +#define RF5G_RF5G2_PDVGM5_SET(x) (((x) << RF5G_RF5G2_PDVGM5_LSB) & RF5G_RF5G2_PDVGM5_MASK) +#define RF5G_RF5G2_PDCSLNA5_MSB 23 +#define RF5G_RF5G2_PDCSLNA5_LSB 23 +#define RF5G_RF5G2_PDCSLNA5_MASK 0x00800000 +#define RF5G_RF5G2_PDCSLNA5_GET(x) (((x) & RF5G_RF5G2_PDCSLNA5_MASK) >> RF5G_RF5G2_PDCSLNA5_LSB) +#define RF5G_RF5G2_PDCSLNA5_SET(x) (((x) << RF5G_RF5G2_PDCSLNA5_LSB) & RF5G_RF5G2_PDCSLNA5_MASK) +#define RF5G_RF5G2_PDRFVGA5_MSB 22 +#define RF5G_RF5G2_PDRFVGA5_LSB 22 +#define RF5G_RF5G2_PDRFVGA5_MASK 0x00400000 +#define RF5G_RF5G2_PDRFVGA5_GET(x) (((x) & RF5G_RF5G2_PDRFVGA5_MASK) >> RF5G_RF5G2_PDRFVGA5_LSB) +#define RF5G_RF5G2_PDRFVGA5_SET(x) (((x) << RF5G_RF5G2_PDRFVGA5_LSB) & RF5G_RF5G2_PDRFVGA5_MASK) +#define RF5G_RF5G2_PDREGFE5_MSB 21 +#define RF5G_RF5G2_PDREGFE5_LSB 21 +#define RF5G_RF5G2_PDREGFE5_MASK 0x00200000 +#define RF5G_RF5G2_PDREGFE5_GET(x) (((x) & RF5G_RF5G2_PDREGFE5_MASK) >> RF5G_RF5G2_PDREGFE5_LSB) +#define RF5G_RF5G2_PDREGFE5_SET(x) (((x) << RF5G_RF5G2_PDREGFE5_LSB) & RF5G_RF5G2_PDREGFE5_MASK) +#define RF5G_RF5G2_TUNE_RFVGA5_MSB 20 +#define RF5G_RF5G2_TUNE_RFVGA5_LSB 18 +#define RF5G_RF5G2_TUNE_RFVGA5_MASK 0x001c0000 +#define RF5G_RF5G2_TUNE_RFVGA5_GET(x) (((x) & RF5G_RF5G2_TUNE_RFVGA5_MASK) >> RF5G_RF5G2_TUNE_RFVGA5_LSB) +#define RF5G_RF5G2_TUNE_RFVGA5_SET(x) (((x) << RF5G_RF5G2_TUNE_RFVGA5_LSB) & RF5G_RF5G2_TUNE_RFVGA5_MASK) +#define RF5G_RF5G2_BRFVGA5_MSB 17 +#define RF5G_RF5G2_BRFVGA5_LSB 15 +#define RF5G_RF5G2_BRFVGA5_MASK 0x00038000 +#define RF5G_RF5G2_BRFVGA5_GET(x) (((x) & RF5G_RF5G2_BRFVGA5_MASK) >> RF5G_RF5G2_BRFVGA5_LSB) +#define RF5G_RF5G2_BRFVGA5_SET(x) (((x) << RF5G_RF5G2_BRFVGA5_LSB) & RF5G_RF5G2_BRFVGA5_MASK) +#define RF5G_RF5G2_BCSLNA5_MSB 14 +#define RF5G_RF5G2_BCSLNA5_LSB 12 +#define RF5G_RF5G2_BCSLNA5_MASK 0x00007000 +#define RF5G_RF5G2_BCSLNA5_GET(x) (((x) & RF5G_RF5G2_BCSLNA5_MASK) >> RF5G_RF5G2_BCSLNA5_LSB) +#define RF5G_RF5G2_BCSLNA5_SET(x) (((x) << RF5G_RF5G2_BCSLNA5_LSB) & RF5G_RF5G2_BCSLNA5_MASK) +#define RF5G_RF5G2_BVGM5_MSB 11 +#define RF5G_RF5G2_BVGM5_LSB 9 +#define RF5G_RF5G2_BVGM5_MASK 0x00000e00 +#define RF5G_RF5G2_BVGM5_GET(x) (((x) & RF5G_RF5G2_BVGM5_MASK) >> RF5G_RF5G2_BVGM5_LSB) +#define RF5G_RF5G2_BVGM5_SET(x) (((x) << RF5G_RF5G2_BVGM5_LSB) & RF5G_RF5G2_BVGM5_MASK) +#define RF5G_RF5G2_REGFE_BYPASS5_MSB 8 +#define RF5G_RF5G2_REGFE_BYPASS5_LSB 8 +#define RF5G_RF5G2_REGFE_BYPASS5_MASK 0x00000100 +#define RF5G_RF5G2_REGFE_BYPASS5_GET(x) (((x) & RF5G_RF5G2_REGFE_BYPASS5_MASK) >> RF5G_RF5G2_REGFE_BYPASS5_LSB) +#define RF5G_RF5G2_REGFE_BYPASS5_SET(x) (((x) << RF5G_RF5G2_REGFE_BYPASS5_LSB) & RF5G_RF5G2_REGFE_BYPASS5_MASK) +#define RF5G_RF5G2_LNA5_ATTENMODE_MSB 7 +#define RF5G_RF5G2_LNA5_ATTENMODE_LSB 6 +#define RF5G_RF5G2_LNA5_ATTENMODE_MASK 0x000000c0 +#define RF5G_RF5G2_LNA5_ATTENMODE_GET(x) (((x) & RF5G_RF5G2_LNA5_ATTENMODE_MASK) >> RF5G_RF5G2_LNA5_ATTENMODE_LSB) +#define RF5G_RF5G2_LNA5_ATTENMODE_SET(x) (((x) << RF5G_RF5G2_LNA5_ATTENMODE_LSB) & RF5G_RF5G2_LNA5_ATTENMODE_MASK) +#define RF5G_RF5G2_ENABLE_PCA_MSB 5 +#define RF5G_RF5G2_ENABLE_PCA_LSB 5 +#define RF5G_RF5G2_ENABLE_PCA_MASK 0x00000020 +#define RF5G_RF5G2_ENABLE_PCA_GET(x) (((x) & RF5G_RF5G2_ENABLE_PCA_MASK) >> RF5G_RF5G2_ENABLE_PCA_LSB) +#define RF5G_RF5G2_ENABLE_PCA_SET(x) (((x) << RF5G_RF5G2_ENABLE_PCA_LSB) & RF5G_RF5G2_ENABLE_PCA_MASK) +#define RF5G_RF5G2_TUNE_LO_MSB 4 +#define RF5G_RF5G2_TUNE_LO_LSB 2 +#define RF5G_RF5G2_TUNE_LO_MASK 0x0000001c +#define RF5G_RF5G2_TUNE_LO_GET(x) (((x) & RF5G_RF5G2_TUNE_LO_MASK) >> RF5G_RF5G2_TUNE_LO_LSB) +#define RF5G_RF5G2_TUNE_LO_SET(x) (((x) << RF5G_RF5G2_TUNE_LO_LSB) & RF5G_RF5G2_TUNE_LO_MASK) +#define RF5G_RF5G2_SPARE_MSB 1 +#define RF5G_RF5G2_SPARE_LSB 0 +#define RF5G_RF5G2_SPARE_MASK 0x00000003 +#define RF5G_RF5G2_SPARE_GET(x) (((x) & RF5G_RF5G2_SPARE_MASK) >> RF5G_RF5G2_SPARE_LSB) +#define RF5G_RF5G2_SPARE_SET(x) (((x) << RF5G_RF5G2_SPARE_LSB) & RF5G_RF5G2_SPARE_MASK) + +#define RF2G_RF2G1_ADDRESS 0x00000028 +#define RF2G_RF2G1_OFFSET 0x00000028 +#define RF2G_RF2G1_BLNA1_MSB 31 +#define RF2G_RF2G1_BLNA1_LSB 29 +#define RF2G_RF2G1_BLNA1_MASK 0xe0000000 +#define RF2G_RF2G1_BLNA1_GET(x) (((x) & RF2G_RF2G1_BLNA1_MASK) >> RF2G_RF2G1_BLNA1_LSB) +#define RF2G_RF2G1_BLNA1_SET(x) (((x) << RF2G_RF2G1_BLNA1_LSB) & RF2G_RF2G1_BLNA1_MASK) +#define RF2G_RF2G1_BLNA1F_MSB 28 +#define RF2G_RF2G1_BLNA1F_LSB 26 +#define RF2G_RF2G1_BLNA1F_MASK 0x1c000000 +#define RF2G_RF2G1_BLNA1F_GET(x) (((x) & RF2G_RF2G1_BLNA1F_MASK) >> RF2G_RF2G1_BLNA1F_LSB) +#define RF2G_RF2G1_BLNA1F_SET(x) (((x) << RF2G_RF2G1_BLNA1F_LSB) & RF2G_RF2G1_BLNA1F_MASK) +#define RF2G_RF2G1_BLNA1BUF_MSB 25 +#define RF2G_RF2G1_BLNA1BUF_LSB 23 +#define RF2G_RF2G1_BLNA1BUF_MASK 0x03800000 +#define RF2G_RF2G1_BLNA1BUF_GET(x) (((x) & RF2G_RF2G1_BLNA1BUF_MASK) >> RF2G_RF2G1_BLNA1BUF_LSB) +#define RF2G_RF2G1_BLNA1BUF_SET(x) (((x) << RF2G_RF2G1_BLNA1BUF_LSB) & RF2G_RF2G1_BLNA1BUF_MASK) +#define RF2G_RF2G1_BLNA2_MSB 22 +#define RF2G_RF2G1_BLNA2_LSB 20 +#define RF2G_RF2G1_BLNA2_MASK 0x00700000 +#define RF2G_RF2G1_BLNA2_GET(x) (((x) & RF2G_RF2G1_BLNA2_MASK) >> RF2G_RF2G1_BLNA2_LSB) +#define RF2G_RF2G1_BLNA2_SET(x) (((x) << RF2G_RF2G1_BLNA2_LSB) & RF2G_RF2G1_BLNA2_MASK) +#define RF2G_RF2G1_DB_MSB 19 +#define RF2G_RF2G1_DB_LSB 17 +#define RF2G_RF2G1_DB_MASK 0x000e0000 +#define RF2G_RF2G1_DB_GET(x) (((x) & RF2G_RF2G1_DB_MASK) >> RF2G_RF2G1_DB_LSB) +#define RF2G_RF2G1_DB_SET(x) (((x) << RF2G_RF2G1_DB_LSB) & RF2G_RF2G1_DB_MASK) +#define RF2G_RF2G1_OB_MSB 16 +#define RF2G_RF2G1_OB_LSB 14 +#define RF2G_RF2G1_OB_MASK 0x0001c000 +#define RF2G_RF2G1_OB_GET(x) (((x) & RF2G_RF2G1_OB_MASK) >> RF2G_RF2G1_OB_LSB) +#define RF2G_RF2G1_OB_SET(x) (((x) << RF2G_RF2G1_OB_LSB) & RF2G_RF2G1_OB_MASK) +#define RF2G_RF2G1_FE_ATB_SEL_MSB 13 +#define RF2G_RF2G1_FE_ATB_SEL_LSB 11 +#define RF2G_RF2G1_FE_ATB_SEL_MASK 0x00003800 +#define RF2G_RF2G1_FE_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_FE_ATB_SEL_MASK) >> RF2G_RF2G1_FE_ATB_SEL_LSB) +#define RF2G_RF2G1_FE_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_FE_ATB_SEL_LSB) & RF2G_RF2G1_FE_ATB_SEL_MASK) +#define RF2G_RF2G1_RF_ATB_SEL_MSB 10 +#define RF2G_RF2G1_RF_ATB_SEL_LSB 8 +#define RF2G_RF2G1_RF_ATB_SEL_MASK 0x00000700 +#define RF2G_RF2G1_RF_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_RF_ATB_SEL_MASK) >> RF2G_RF2G1_RF_ATB_SEL_LSB) +#define RF2G_RF2G1_RF_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_RF_ATB_SEL_LSB) & RF2G_RF2G1_RF_ATB_SEL_MASK) +#define RF2G_RF2G1_SELLNA_MSB 7 +#define RF2G_RF2G1_SELLNA_LSB 7 +#define RF2G_RF2G1_SELLNA_MASK 0x00000080 +#define RF2G_RF2G1_SELLNA_GET(x) (((x) & RF2G_RF2G1_SELLNA_MASK) >> RF2G_RF2G1_SELLNA_LSB) +#define RF2G_RF2G1_SELLNA_SET(x) (((x) << RF2G_RF2G1_SELLNA_LSB) & RF2G_RF2G1_SELLNA_MASK) +#define RF2G_RF2G1_LOCONTROL_MSB 6 +#define RF2G_RF2G1_LOCONTROL_LSB 6 +#define RF2G_RF2G1_LOCONTROL_MASK 0x00000040 +#define RF2G_RF2G1_LOCONTROL_GET(x) (((x) & RF2G_RF2G1_LOCONTROL_MASK) >> RF2G_RF2G1_LOCONTROL_LSB) +#define RF2G_RF2G1_LOCONTROL_SET(x) (((x) << RF2G_RF2G1_LOCONTROL_LSB) & RF2G_RF2G1_LOCONTROL_MASK) +#define RF2G_RF2G1_SHORTLNA2_MSB 5 +#define RF2G_RF2G1_SHORTLNA2_LSB 5 +#define RF2G_RF2G1_SHORTLNA2_MASK 0x00000020 +#define RF2G_RF2G1_SHORTLNA2_GET(x) (((x) & RF2G_RF2G1_SHORTLNA2_MASK) >> RF2G_RF2G1_SHORTLNA2_LSB) +#define RF2G_RF2G1_SHORTLNA2_SET(x) (((x) << RF2G_RF2G1_SHORTLNA2_LSB) & RF2G_RF2G1_SHORTLNA2_MASK) +#define RF2G_RF2G1_SPARE_MSB 4 +#define RF2G_RF2G1_SPARE_LSB 0 +#define RF2G_RF2G1_SPARE_MASK 0x0000001f +#define RF2G_RF2G1_SPARE_GET(x) (((x) & RF2G_RF2G1_SPARE_MASK) >> RF2G_RF2G1_SPARE_LSB) +#define RF2G_RF2G1_SPARE_SET(x) (((x) << RF2G_RF2G1_SPARE_LSB) & RF2G_RF2G1_SPARE_MASK) + +#define RF2G_RF2G2_ADDRESS 0x0000002c +#define RF2G_RF2G2_OFFSET 0x0000002c +#define RF2G_RF2G2_PDCGLNA_MSB 31 +#define RF2G_RF2G2_PDCGLNA_LSB 31 +#define RF2G_RF2G2_PDCGLNA_MASK 0x80000000 +#define RF2G_RF2G2_PDCGLNA_GET(x) (((x) & RF2G_RF2G2_PDCGLNA_MASK) >> RF2G_RF2G2_PDCGLNA_LSB) +#define RF2G_RF2G2_PDCGLNA_SET(x) (((x) << RF2G_RF2G2_PDCGLNA_LSB) & RF2G_RF2G2_PDCGLNA_MASK) +#define RF2G_RF2G2_PDCGLNABUF_MSB 30 +#define RF2G_RF2G2_PDCGLNABUF_LSB 30 +#define RF2G_RF2G2_PDCGLNABUF_MASK 0x40000000 +#define RF2G_RF2G2_PDCGLNABUF_GET(x) (((x) & RF2G_RF2G2_PDCGLNABUF_MASK) >> RF2G_RF2G2_PDCGLNABUF_LSB) +#define RF2G_RF2G2_PDCGLNABUF_SET(x) (((x) << RF2G_RF2G2_PDCGLNABUF_LSB) & RF2G_RF2G2_PDCGLNABUF_MASK) +#define RF2G_RF2G2_PDCSLNA_MSB 29 +#define RF2G_RF2G2_PDCSLNA_LSB 29 +#define RF2G_RF2G2_PDCSLNA_MASK 0x20000000 +#define RF2G_RF2G2_PDCSLNA_GET(x) (((x) & RF2G_RF2G2_PDCSLNA_MASK) >> RF2G_RF2G2_PDCSLNA_LSB) +#define RF2G_RF2G2_PDCSLNA_SET(x) (((x) << RF2G_RF2G2_PDCSLNA_LSB) & RF2G_RF2G2_PDCSLNA_MASK) +#define RF2G_RF2G2_PDDIV_MSB 28 +#define RF2G_RF2G2_PDDIV_LSB 28 +#define RF2G_RF2G2_PDDIV_MASK 0x10000000 +#define RF2G_RF2G2_PDDIV_GET(x) (((x) & RF2G_RF2G2_PDDIV_MASK) >> RF2G_RF2G2_PDDIV_LSB) +#define RF2G_RF2G2_PDDIV_SET(x) (((x) << RF2G_RF2G2_PDDIV_LSB) & RF2G_RF2G2_PDDIV_MASK) +#define RF2G_RF2G2_PDPADRV_MSB 27 +#define RF2G_RF2G2_PDPADRV_LSB 27 +#define RF2G_RF2G2_PDPADRV_MASK 0x08000000 +#define RF2G_RF2G2_PDPADRV_GET(x) (((x) & RF2G_RF2G2_PDPADRV_MASK) >> RF2G_RF2G2_PDPADRV_LSB) +#define RF2G_RF2G2_PDPADRV_SET(x) (((x) << RF2G_RF2G2_PDPADRV_LSB) & RF2G_RF2G2_PDPADRV_MASK) +#define RF2G_RF2G2_PDPAOUT_MSB 26 +#define RF2G_RF2G2_PDPAOUT_LSB 26 +#define RF2G_RF2G2_PDPAOUT_MASK 0x04000000 +#define RF2G_RF2G2_PDPAOUT_GET(x) (((x) & RF2G_RF2G2_PDPAOUT_MASK) >> RF2G_RF2G2_PDPAOUT_LSB) +#define RF2G_RF2G2_PDPAOUT_SET(x) (((x) << RF2G_RF2G2_PDPAOUT_LSB) & RF2G_RF2G2_PDPAOUT_MASK) +#define RF2G_RF2G2_PDREGLNA_MSB 25 +#define RF2G_RF2G2_PDREGLNA_LSB 25 +#define RF2G_RF2G2_PDREGLNA_MASK 0x02000000 +#define RF2G_RF2G2_PDREGLNA_GET(x) (((x) & RF2G_RF2G2_PDREGLNA_MASK) >> RF2G_RF2G2_PDREGLNA_LSB) +#define RF2G_RF2G2_PDREGLNA_SET(x) (((x) << RF2G_RF2G2_PDREGLNA_LSB) & RF2G_RF2G2_PDREGLNA_MASK) +#define RF2G_RF2G2_PDREGLO_MSB 24 +#define RF2G_RF2G2_PDREGLO_LSB 24 +#define RF2G_RF2G2_PDREGLO_MASK 0x01000000 +#define RF2G_RF2G2_PDREGLO_GET(x) (((x) & RF2G_RF2G2_PDREGLO_MASK) >> RF2G_RF2G2_PDREGLO_LSB) +#define RF2G_RF2G2_PDREGLO_SET(x) (((x) << RF2G_RF2G2_PDREGLO_LSB) & RF2G_RF2G2_PDREGLO_MASK) +#define RF2G_RF2G2_PDRFGM_MSB 23 +#define RF2G_RF2G2_PDRFGM_LSB 23 +#define RF2G_RF2G2_PDRFGM_MASK 0x00800000 +#define RF2G_RF2G2_PDRFGM_GET(x) (((x) & RF2G_RF2G2_PDRFGM_MASK) >> RF2G_RF2G2_PDRFGM_LSB) +#define RF2G_RF2G2_PDRFGM_SET(x) (((x) << RF2G_RF2G2_PDRFGM_LSB) & RF2G_RF2G2_PDRFGM_MASK) +#define RF2G_RF2G2_PDRXLO_MSB 22 +#define RF2G_RF2G2_PDRXLO_LSB 22 +#define RF2G_RF2G2_PDRXLO_MASK 0x00400000 +#define RF2G_RF2G2_PDRXLO_GET(x) (((x) & RF2G_RF2G2_PDRXLO_MASK) >> RF2G_RF2G2_PDRXLO_LSB) +#define RF2G_RF2G2_PDRXLO_SET(x) (((x) << RF2G_RF2G2_PDRXLO_LSB) & RF2G_RF2G2_PDRXLO_MASK) +#define RF2G_RF2G2_PDTXLO_MSB 21 +#define RF2G_RF2G2_PDTXLO_LSB 21 +#define RF2G_RF2G2_PDTXLO_MASK 0x00200000 +#define RF2G_RF2G2_PDTXLO_GET(x) (((x) & RF2G_RF2G2_PDTXLO_MASK) >> RF2G_RF2G2_PDTXLO_LSB) +#define RF2G_RF2G2_PDTXLO_SET(x) (((x) << RF2G_RF2G2_PDTXLO_LSB) & RF2G_RF2G2_PDTXLO_MASK) +#define RF2G_RF2G2_PDTXMIX_MSB 20 +#define RF2G_RF2G2_PDTXMIX_LSB 20 +#define RF2G_RF2G2_PDTXMIX_MASK 0x00100000 +#define RF2G_RF2G2_PDTXMIX_GET(x) (((x) & RF2G_RF2G2_PDTXMIX_MASK) >> RF2G_RF2G2_PDTXMIX_LSB) +#define RF2G_RF2G2_PDTXMIX_SET(x) (((x) << RF2G_RF2G2_PDTXMIX_LSB) & RF2G_RF2G2_PDTXMIX_MASK) +#define RF2G_RF2G2_REGLNA_BYPASS_MSB 19 +#define RF2G_RF2G2_REGLNA_BYPASS_LSB 19 +#define RF2G_RF2G2_REGLNA_BYPASS_MASK 0x00080000 +#define RF2G_RF2G2_REGLNA_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLNA_BYPASS_MASK) >> RF2G_RF2G2_REGLNA_BYPASS_LSB) +#define RF2G_RF2G2_REGLNA_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLNA_BYPASS_LSB) & RF2G_RF2G2_REGLNA_BYPASS_MASK) +#define RF2G_RF2G2_REGLO_BYPASS_MSB 18 +#define RF2G_RF2G2_REGLO_BYPASS_LSB 18 +#define RF2G_RF2G2_REGLO_BYPASS_MASK 0x00040000 +#define RF2G_RF2G2_REGLO_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLO_BYPASS_MASK) >> RF2G_RF2G2_REGLO_BYPASS_LSB) +#define RF2G_RF2G2_REGLO_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLO_BYPASS_LSB) & RF2G_RF2G2_REGLO_BYPASS_MASK) +#define RF2G_RF2G2_ENABLE_PCB_MSB 17 +#define RF2G_RF2G2_ENABLE_PCB_LSB 17 +#define RF2G_RF2G2_ENABLE_PCB_MASK 0x00020000 +#define RF2G_RF2G2_ENABLE_PCB_GET(x) (((x) & RF2G_RF2G2_ENABLE_PCB_MASK) >> RF2G_RF2G2_ENABLE_PCB_LSB) +#define RF2G_RF2G2_ENABLE_PCB_SET(x) (((x) << RF2G_RF2G2_ENABLE_PCB_LSB) & RF2G_RF2G2_ENABLE_PCB_MASK) +#define RF2G_RF2G2_SPARE_MSB 16 +#define RF2G_RF2G2_SPARE_LSB 0 +#define RF2G_RF2G2_SPARE_MASK 0x0001ffff +#define RF2G_RF2G2_SPARE_GET(x) (((x) & RF2G_RF2G2_SPARE_MASK) >> RF2G_RF2G2_SPARE_LSB) +#define RF2G_RF2G2_SPARE_SET(x) (((x) << RF2G_RF2G2_SPARE_LSB) & RF2G_RF2G2_SPARE_MASK) + +#define TOP_GAIN_ADDRESS 0x00000030 +#define TOP_GAIN_OFFSET 0x00000030 +#define TOP_GAIN_TX6DBLOQGAIN_MSB 31 +#define TOP_GAIN_TX6DBLOQGAIN_LSB 30 +#define TOP_GAIN_TX6DBLOQGAIN_MASK 0xc0000000 +#define TOP_GAIN_TX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX6DBLOQGAIN_MASK) >> TOP_GAIN_TX6DBLOQGAIN_LSB) +#define TOP_GAIN_TX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX6DBLOQGAIN_LSB) & TOP_GAIN_TX6DBLOQGAIN_MASK) +#define TOP_GAIN_TX1DBLOQGAIN_MSB 29 +#define TOP_GAIN_TX1DBLOQGAIN_LSB 27 +#define TOP_GAIN_TX1DBLOQGAIN_MASK 0x38000000 +#define TOP_GAIN_TX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX1DBLOQGAIN_MASK) >> TOP_GAIN_TX1DBLOQGAIN_LSB) +#define TOP_GAIN_TX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX1DBLOQGAIN_LSB) & TOP_GAIN_TX1DBLOQGAIN_MASK) +#define TOP_GAIN_TXV2IGAIN_MSB 26 +#define TOP_GAIN_TXV2IGAIN_LSB 25 +#define TOP_GAIN_TXV2IGAIN_MASK 0x06000000 +#define TOP_GAIN_TXV2IGAIN_GET(x) (((x) & TOP_GAIN_TXV2IGAIN_MASK) >> TOP_GAIN_TXV2IGAIN_LSB) +#define TOP_GAIN_TXV2IGAIN_SET(x) (((x) << TOP_GAIN_TXV2IGAIN_LSB) & TOP_GAIN_TXV2IGAIN_MASK) +#define TOP_GAIN_PABUF5GN_MSB 24 +#define TOP_GAIN_PABUF5GN_LSB 24 +#define TOP_GAIN_PABUF5GN_MASK 0x01000000 +#define TOP_GAIN_PABUF5GN_GET(x) (((x) & TOP_GAIN_PABUF5GN_MASK) >> TOP_GAIN_PABUF5GN_LSB) +#define TOP_GAIN_PABUF5GN_SET(x) (((x) << TOP_GAIN_PABUF5GN_LSB) & TOP_GAIN_PABUF5GN_MASK) +#define TOP_GAIN_PADRVGN_MSB 23 +#define TOP_GAIN_PADRVGN_LSB 21 +#define TOP_GAIN_PADRVGN_MASK 0x00e00000 +#define TOP_GAIN_PADRVGN_GET(x) (((x) & TOP_GAIN_PADRVGN_MASK) >> TOP_GAIN_PADRVGN_LSB) +#define TOP_GAIN_PADRVGN_SET(x) (((x) << TOP_GAIN_PADRVGN_LSB) & TOP_GAIN_PADRVGN_MASK) +#define TOP_GAIN_PAOUT2GN_MSB 20 +#define TOP_GAIN_PAOUT2GN_LSB 18 +#define TOP_GAIN_PAOUT2GN_MASK 0x001c0000 +#define TOP_GAIN_PAOUT2GN_GET(x) (((x) & TOP_GAIN_PAOUT2GN_MASK) >> TOP_GAIN_PAOUT2GN_LSB) +#define TOP_GAIN_PAOUT2GN_SET(x) (((x) << TOP_GAIN_PAOUT2GN_LSB) & TOP_GAIN_PAOUT2GN_MASK) +#define TOP_GAIN_LNAON_MSB 17 +#define TOP_GAIN_LNAON_LSB 17 +#define TOP_GAIN_LNAON_MASK 0x00020000 +#define TOP_GAIN_LNAON_GET(x) (((x) & TOP_GAIN_LNAON_MASK) >> TOP_GAIN_LNAON_LSB) +#define TOP_GAIN_LNAON_SET(x) (((x) << TOP_GAIN_LNAON_LSB) & TOP_GAIN_LNAON_MASK) +#define TOP_GAIN_LNAGAIN_MSB 16 +#define TOP_GAIN_LNAGAIN_LSB 13 +#define TOP_GAIN_LNAGAIN_MASK 0x0001e000 +#define TOP_GAIN_LNAGAIN_GET(x) (((x) & TOP_GAIN_LNAGAIN_MASK) >> TOP_GAIN_LNAGAIN_LSB) +#define TOP_GAIN_LNAGAIN_SET(x) (((x) << TOP_GAIN_LNAGAIN_LSB) & TOP_GAIN_LNAGAIN_MASK) +#define TOP_GAIN_RFVGA5GAIN_MSB 12 +#define TOP_GAIN_RFVGA5GAIN_LSB 11 +#define TOP_GAIN_RFVGA5GAIN_MASK 0x00001800 +#define TOP_GAIN_RFVGA5GAIN_GET(x) (((x) & TOP_GAIN_RFVGA5GAIN_MASK) >> TOP_GAIN_RFVGA5GAIN_LSB) +#define TOP_GAIN_RFVGA5GAIN_SET(x) (((x) << TOP_GAIN_RFVGA5GAIN_LSB) & TOP_GAIN_RFVGA5GAIN_MASK) +#define TOP_GAIN_RFGMGN_MSB 10 +#define TOP_GAIN_RFGMGN_LSB 8 +#define TOP_GAIN_RFGMGN_MASK 0x00000700 +#define TOP_GAIN_RFGMGN_GET(x) (((x) & TOP_GAIN_RFGMGN_MASK) >> TOP_GAIN_RFGMGN_LSB) +#define TOP_GAIN_RFGMGN_SET(x) (((x) << TOP_GAIN_RFGMGN_LSB) & TOP_GAIN_RFGMGN_MASK) +#define TOP_GAIN_RX6DBLOQGAIN_MSB 7 +#define TOP_GAIN_RX6DBLOQGAIN_LSB 6 +#define TOP_GAIN_RX6DBLOQGAIN_MASK 0x000000c0 +#define TOP_GAIN_RX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBLOQGAIN_MASK) >> TOP_GAIN_RX6DBLOQGAIN_LSB) +#define TOP_GAIN_RX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBLOQGAIN_LSB) & TOP_GAIN_RX6DBLOQGAIN_MASK) +#define TOP_GAIN_RX1DBLOQGAIN_MSB 5 +#define TOP_GAIN_RX1DBLOQGAIN_LSB 3 +#define TOP_GAIN_RX1DBLOQGAIN_MASK 0x00000038 +#define TOP_GAIN_RX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX1DBLOQGAIN_MASK) >> TOP_GAIN_RX1DBLOQGAIN_LSB) +#define TOP_GAIN_RX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX1DBLOQGAIN_LSB) & TOP_GAIN_RX1DBLOQGAIN_MASK) +#define TOP_GAIN_RX6DBHIQGAIN_MSB 2 +#define TOP_GAIN_RX6DBHIQGAIN_LSB 1 +#define TOP_GAIN_RX6DBHIQGAIN_MASK 0x00000006 +#define TOP_GAIN_RX6DBHIQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBHIQGAIN_MASK) >> TOP_GAIN_RX6DBHIQGAIN_LSB) +#define TOP_GAIN_RX6DBHIQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBHIQGAIN_LSB) & TOP_GAIN_RX6DBHIQGAIN_MASK) +#define TOP_GAIN_SPARE_MSB 0 +#define TOP_GAIN_SPARE_LSB 0 +#define TOP_GAIN_SPARE_MASK 0x00000001 +#define TOP_GAIN_SPARE_GET(x) (((x) & TOP_GAIN_SPARE_MASK) >> TOP_GAIN_SPARE_LSB) +#define TOP_GAIN_SPARE_SET(x) (((x) << TOP_GAIN_SPARE_LSB) & TOP_GAIN_SPARE_MASK) + +#define TOP_TOP_ADDRESS 0x00000034 +#define TOP_TOP_OFFSET 0x00000034 +#define TOP_TOP_LOCALTXGAIN_MSB 31 +#define TOP_TOP_LOCALTXGAIN_LSB 31 +#define TOP_TOP_LOCALTXGAIN_MASK 0x80000000 +#define TOP_TOP_LOCALTXGAIN_GET(x) (((x) & TOP_TOP_LOCALTXGAIN_MASK) >> TOP_TOP_LOCALTXGAIN_LSB) +#define TOP_TOP_LOCALTXGAIN_SET(x) (((x) << TOP_TOP_LOCALTXGAIN_LSB) & TOP_TOP_LOCALTXGAIN_MASK) +#define TOP_TOP_LOCALRXGAIN_MSB 30 +#define TOP_TOP_LOCALRXGAIN_LSB 30 +#define TOP_TOP_LOCALRXGAIN_MASK 0x40000000 +#define TOP_TOP_LOCALRXGAIN_GET(x) (((x) & TOP_TOP_LOCALRXGAIN_MASK) >> TOP_TOP_LOCALRXGAIN_LSB) +#define TOP_TOP_LOCALRXGAIN_SET(x) (((x) << TOP_TOP_LOCALRXGAIN_LSB) & TOP_TOP_LOCALRXGAIN_MASK) +#define TOP_TOP_LOCALMODE_MSB 29 +#define TOP_TOP_LOCALMODE_LSB 29 +#define TOP_TOP_LOCALMODE_MASK 0x20000000 +#define TOP_TOP_LOCALMODE_GET(x) (((x) & TOP_TOP_LOCALMODE_MASK) >> TOP_TOP_LOCALMODE_LSB) +#define TOP_TOP_LOCALMODE_SET(x) (((x) << TOP_TOP_LOCALMODE_LSB) & TOP_TOP_LOCALMODE_MASK) +#define TOP_TOP_CALFC_MSB 28 +#define TOP_TOP_CALFC_LSB 28 +#define TOP_TOP_CALFC_MASK 0x10000000 +#define TOP_TOP_CALFC_GET(x) (((x) & TOP_TOP_CALFC_MASK) >> TOP_TOP_CALFC_LSB) +#define TOP_TOP_CALFC_SET(x) (((x) << TOP_TOP_CALFC_LSB) & TOP_TOP_CALFC_MASK) +#define TOP_TOP_CALDC_MSB 27 +#define TOP_TOP_CALDC_LSB 27 +#define TOP_TOP_CALDC_MASK 0x08000000 +#define TOP_TOP_CALDC_GET(x) (((x) & TOP_TOP_CALDC_MASK) >> TOP_TOP_CALDC_LSB) +#define TOP_TOP_CALDC_SET(x) (((x) << TOP_TOP_CALDC_LSB) & TOP_TOP_CALDC_MASK) +#define TOP_TOP_CAL_RESIDUE_MSB 26 +#define TOP_TOP_CAL_RESIDUE_LSB 26 +#define TOP_TOP_CAL_RESIDUE_MASK 0x04000000 +#define TOP_TOP_CAL_RESIDUE_GET(x) (((x) & TOP_TOP_CAL_RESIDUE_MASK) >> TOP_TOP_CAL_RESIDUE_LSB) +#define TOP_TOP_CAL_RESIDUE_SET(x) (((x) << TOP_TOP_CAL_RESIDUE_LSB) & TOP_TOP_CAL_RESIDUE_MASK) +#define TOP_TOP_BMODE_MSB 25 +#define TOP_TOP_BMODE_LSB 25 +#define TOP_TOP_BMODE_MASK 0x02000000 +#define TOP_TOP_BMODE_GET(x) (((x) & TOP_TOP_BMODE_MASK) >> TOP_TOP_BMODE_LSB) +#define TOP_TOP_BMODE_SET(x) (((x) << TOP_TOP_BMODE_LSB) & TOP_TOP_BMODE_MASK) +#define TOP_TOP_SYNTHON_MSB 24 +#define TOP_TOP_SYNTHON_LSB 24 +#define TOP_TOP_SYNTHON_MASK 0x01000000 +#define TOP_TOP_SYNTHON_GET(x) (((x) & TOP_TOP_SYNTHON_MASK) >> TOP_TOP_SYNTHON_LSB) +#define TOP_TOP_SYNTHON_SET(x) (((x) << TOP_TOP_SYNTHON_LSB) & TOP_TOP_SYNTHON_MASK) +#define TOP_TOP_RXON_MSB 23 +#define TOP_TOP_RXON_LSB 23 +#define TOP_TOP_RXON_MASK 0x00800000 +#define TOP_TOP_RXON_GET(x) (((x) & TOP_TOP_RXON_MASK) >> TOP_TOP_RXON_LSB) +#define TOP_TOP_RXON_SET(x) (((x) << TOP_TOP_RXON_LSB) & TOP_TOP_RXON_MASK) +#define TOP_TOP_TXON_MSB 22 +#define TOP_TOP_TXON_LSB 22 +#define TOP_TOP_TXON_MASK 0x00400000 +#define TOP_TOP_TXON_GET(x) (((x) & TOP_TOP_TXON_MASK) >> TOP_TOP_TXON_LSB) +#define TOP_TOP_TXON_SET(x) (((x) << TOP_TOP_TXON_LSB) & TOP_TOP_TXON_MASK) +#define TOP_TOP_PAON_MSB 21 +#define TOP_TOP_PAON_LSB 21 +#define TOP_TOP_PAON_MASK 0x00200000 +#define TOP_TOP_PAON_GET(x) (((x) & TOP_TOP_PAON_MASK) >> TOP_TOP_PAON_LSB) +#define TOP_TOP_PAON_SET(x) (((x) << TOP_TOP_PAON_LSB) & TOP_TOP_PAON_MASK) +#define TOP_TOP_CALTX_MSB 20 +#define TOP_TOP_CALTX_LSB 20 +#define TOP_TOP_CALTX_MASK 0x00100000 +#define TOP_TOP_CALTX_GET(x) (((x) & TOP_TOP_CALTX_MASK) >> TOP_TOP_CALTX_LSB) +#define TOP_TOP_CALTX_SET(x) (((x) << TOP_TOP_CALTX_LSB) & TOP_TOP_CALTX_MASK) +#define TOP_TOP_LOCALADDAC_MSB 19 +#define TOP_TOP_LOCALADDAC_LSB 19 +#define TOP_TOP_LOCALADDAC_MASK 0x00080000 +#define TOP_TOP_LOCALADDAC_GET(x) (((x) & TOP_TOP_LOCALADDAC_MASK) >> TOP_TOP_LOCALADDAC_LSB) +#define TOP_TOP_LOCALADDAC_SET(x) (((x) << TOP_TOP_LOCALADDAC_LSB) & TOP_TOP_LOCALADDAC_MASK) +#define TOP_TOP_PWDPLL_MSB 18 +#define TOP_TOP_PWDPLL_LSB 18 +#define TOP_TOP_PWDPLL_MASK 0x00040000 +#define TOP_TOP_PWDPLL_GET(x) (((x) & TOP_TOP_PWDPLL_MASK) >> TOP_TOP_PWDPLL_LSB) +#define TOP_TOP_PWDPLL_SET(x) (((x) << TOP_TOP_PWDPLL_LSB) & TOP_TOP_PWDPLL_MASK) +#define TOP_TOP_PWDADC_MSB 17 +#define TOP_TOP_PWDADC_LSB 17 +#define TOP_TOP_PWDADC_MASK 0x00020000 +#define TOP_TOP_PWDADC_GET(x) (((x) & TOP_TOP_PWDADC_MASK) >> TOP_TOP_PWDADC_LSB) +#define TOP_TOP_PWDADC_SET(x) (((x) << TOP_TOP_PWDADC_LSB) & TOP_TOP_PWDADC_MASK) +#define TOP_TOP_PWDDAC_MSB 16 +#define TOP_TOP_PWDDAC_LSB 16 +#define TOP_TOP_PWDDAC_MASK 0x00010000 +#define TOP_TOP_PWDDAC_GET(x) (((x) & TOP_TOP_PWDDAC_MASK) >> TOP_TOP_PWDDAC_LSB) +#define TOP_TOP_PWDDAC_SET(x) (((x) << TOP_TOP_PWDDAC_LSB) & TOP_TOP_PWDDAC_MASK) +#define TOP_TOP_LOCALXTAL_MSB 15 +#define TOP_TOP_LOCALXTAL_LSB 15 +#define TOP_TOP_LOCALXTAL_MASK 0x00008000 +#define TOP_TOP_LOCALXTAL_GET(x) (((x) & TOP_TOP_LOCALXTAL_MASK) >> TOP_TOP_LOCALXTAL_LSB) +#define TOP_TOP_LOCALXTAL_SET(x) (((x) << TOP_TOP_LOCALXTAL_LSB) & TOP_TOP_LOCALXTAL_MASK) +#define TOP_TOP_PWDCLKIN_MSB 14 +#define TOP_TOP_PWDCLKIN_LSB 14 +#define TOP_TOP_PWDCLKIN_MASK 0x00004000 +#define TOP_TOP_PWDCLKIN_GET(x) (((x) & TOP_TOP_PWDCLKIN_MASK) >> TOP_TOP_PWDCLKIN_LSB) +#define TOP_TOP_PWDCLKIN_SET(x) (((x) << TOP_TOP_PWDCLKIN_LSB) & TOP_TOP_PWDCLKIN_MASK) +#define TOP_TOP_OSCON_MSB 13 +#define TOP_TOP_OSCON_LSB 13 +#define TOP_TOP_OSCON_MASK 0x00002000 +#define TOP_TOP_OSCON_GET(x) (((x) & TOP_TOP_OSCON_MASK) >> TOP_TOP_OSCON_LSB) +#define TOP_TOP_OSCON_SET(x) (((x) << TOP_TOP_OSCON_LSB) & TOP_TOP_OSCON_MASK) +#define TOP_TOP_SCLKEN_FORCE_MSB 12 +#define TOP_TOP_SCLKEN_FORCE_LSB 12 +#define TOP_TOP_SCLKEN_FORCE_MASK 0x00001000 +#define TOP_TOP_SCLKEN_FORCE_GET(x) (((x) & TOP_TOP_SCLKEN_FORCE_MASK) >> TOP_TOP_SCLKEN_FORCE_LSB) +#define TOP_TOP_SCLKEN_FORCE_SET(x) (((x) << TOP_TOP_SCLKEN_FORCE_LSB) & TOP_TOP_SCLKEN_FORCE_MASK) +#define TOP_TOP_SYNTHON_FORCE_MSB 11 +#define TOP_TOP_SYNTHON_FORCE_LSB 11 +#define TOP_TOP_SYNTHON_FORCE_MASK 0x00000800 +#define TOP_TOP_SYNTHON_FORCE_GET(x) (((x) & TOP_TOP_SYNTHON_FORCE_MASK) >> TOP_TOP_SYNTHON_FORCE_LSB) +#define TOP_TOP_SYNTHON_FORCE_SET(x) (((x) << TOP_TOP_SYNTHON_FORCE_LSB) & TOP_TOP_SYNTHON_FORCE_MASK) +#define TOP_TOP_PDBIAS_MSB 10 +#define TOP_TOP_PDBIAS_LSB 10 +#define TOP_TOP_PDBIAS_MASK 0x00000400 +#define TOP_TOP_PDBIAS_GET(x) (((x) & TOP_TOP_PDBIAS_MASK) >> TOP_TOP_PDBIAS_LSB) +#define TOP_TOP_PDBIAS_SET(x) (((x) << TOP_TOP_PDBIAS_LSB) & TOP_TOP_PDBIAS_MASK) +#define TOP_TOP_DATAOUTSEL_MSB 9 +#define TOP_TOP_DATAOUTSEL_LSB 8 +#define TOP_TOP_DATAOUTSEL_MASK 0x00000300 +#define TOP_TOP_DATAOUTSEL_GET(x) (((x) & TOP_TOP_DATAOUTSEL_MASK) >> TOP_TOP_DATAOUTSEL_LSB) +#define TOP_TOP_DATAOUTSEL_SET(x) (((x) << TOP_TOP_DATAOUTSEL_LSB) & TOP_TOP_DATAOUTSEL_MASK) +#define TOP_TOP_REVID_MSB 7 +#define TOP_TOP_REVID_LSB 5 +#define TOP_TOP_REVID_MASK 0x000000e0 +#define TOP_TOP_REVID_GET(x) (((x) & TOP_TOP_REVID_MASK) >> TOP_TOP_REVID_LSB) +#define TOP_TOP_REVID_SET(x) (((x) << TOP_TOP_REVID_LSB) & TOP_TOP_REVID_MASK) +#define TOP_TOP_INT2PAD_MSB 4 +#define TOP_TOP_INT2PAD_LSB 4 +#define TOP_TOP_INT2PAD_MASK 0x00000010 +#define TOP_TOP_INT2PAD_GET(x) (((x) & TOP_TOP_INT2PAD_MASK) >> TOP_TOP_INT2PAD_LSB) +#define TOP_TOP_INT2PAD_SET(x) (((x) << TOP_TOP_INT2PAD_LSB) & TOP_TOP_INT2PAD_MASK) +#define TOP_TOP_INTH2PAD_MSB 3 +#define TOP_TOP_INTH2PAD_LSB 3 +#define TOP_TOP_INTH2PAD_MASK 0x00000008 +#define TOP_TOP_INTH2PAD_GET(x) (((x) & TOP_TOP_INTH2PAD_MASK) >> TOP_TOP_INTH2PAD_LSB) +#define TOP_TOP_INTH2PAD_SET(x) (((x) << TOP_TOP_INTH2PAD_LSB) & TOP_TOP_INTH2PAD_MASK) +#define TOP_TOP_PAD2GND_MSB 2 +#define TOP_TOP_PAD2GND_LSB 2 +#define TOP_TOP_PAD2GND_MASK 0x00000004 +#define TOP_TOP_PAD2GND_GET(x) (((x) & TOP_TOP_PAD2GND_MASK) >> TOP_TOP_PAD2GND_LSB) +#define TOP_TOP_PAD2GND_SET(x) (((x) << TOP_TOP_PAD2GND_LSB) & TOP_TOP_PAD2GND_MASK) +#define TOP_TOP_INT2GND_MSB 1 +#define TOP_TOP_INT2GND_LSB 1 +#define TOP_TOP_INT2GND_MASK 0x00000002 +#define TOP_TOP_INT2GND_GET(x) (((x) & TOP_TOP_INT2GND_MASK) >> TOP_TOP_INT2GND_LSB) +#define TOP_TOP_INT2GND_SET(x) (((x) << TOP_TOP_INT2GND_LSB) & TOP_TOP_INT2GND_MASK) +#define TOP_TOP_FORCE_XPAON_MSB 0 +#define TOP_TOP_FORCE_XPAON_LSB 0 +#define TOP_TOP_FORCE_XPAON_MASK 0x00000001 +#define TOP_TOP_FORCE_XPAON_GET(x) (((x) & TOP_TOP_FORCE_XPAON_MASK) >> TOP_TOP_FORCE_XPAON_LSB) +#define TOP_TOP_FORCE_XPAON_SET(x) (((x) << TOP_TOP_FORCE_XPAON_LSB) & TOP_TOP_FORCE_XPAON_MASK) + +#define BIAS_BIAS_SEL_ADDRESS 0x00000038 +#define BIAS_BIAS_SEL_OFFSET 0x00000038 +#define BIAS_BIAS_SEL_PADON_MSB 31 +#define BIAS_BIAS_SEL_PADON_LSB 31 +#define BIAS_BIAS_SEL_PADON_MASK 0x80000000 +#define BIAS_BIAS_SEL_PADON_GET(x) (((x) & BIAS_BIAS_SEL_PADON_MASK) >> BIAS_BIAS_SEL_PADON_LSB) +#define BIAS_BIAS_SEL_PADON_SET(x) (((x) << BIAS_BIAS_SEL_PADON_LSB) & BIAS_BIAS_SEL_PADON_MASK) +#define BIAS_BIAS_SEL_SEL_BIAS_MSB 30 +#define BIAS_BIAS_SEL_SEL_BIAS_LSB 25 +#define BIAS_BIAS_SEL_SEL_BIAS_MASK 0x7e000000 +#define BIAS_BIAS_SEL_SEL_BIAS_GET(x) (((x) & BIAS_BIAS_SEL_SEL_BIAS_MASK) >> BIAS_BIAS_SEL_SEL_BIAS_LSB) +#define BIAS_BIAS_SEL_SEL_BIAS_SET(x) (((x) << BIAS_BIAS_SEL_SEL_BIAS_LSB) & BIAS_BIAS_SEL_SEL_BIAS_MASK) +#define BIAS_BIAS_SEL_SEL_SPARE_MSB 24 +#define BIAS_BIAS_SEL_SEL_SPARE_LSB 21 +#define BIAS_BIAS_SEL_SEL_SPARE_MASK 0x01e00000 +#define BIAS_BIAS_SEL_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SEL_SPARE_LSB) +#define BIAS_BIAS_SEL_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SEL_SPARE_MASK) +#define BIAS_BIAS_SEL_SPARE_MSB 20 +#define BIAS_BIAS_SEL_SPARE_LSB 20 +#define BIAS_BIAS_SEL_SPARE_MASK 0x00100000 +#define BIAS_BIAS_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SPARE_LSB) +#define BIAS_BIAS_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SPARE_MASK) +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MSB 19 +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB 17 +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK 0x000e0000 +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB) +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK) +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MSB 16 +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB 16 +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK 0x00010000 +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB) +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK) +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MSB 15 +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB 15 +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK 0x00008000 +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB) +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK) +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MSB 14 +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB 14 +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK 0x00004000 +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB) +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK) +#define BIAS_BIAS_SEL_PWD_ICCPLL25_MSB 13 +#define BIAS_BIAS_SEL_PWD_ICCPLL25_LSB 13 +#define BIAS_BIAS_SEL_PWD_ICCPLL25_MASK 0x00002000 +#define BIAS_BIAS_SEL_PWD_ICCPLL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK) >> BIAS_BIAS_SEL_PWD_ICCPLL25_LSB) +#define BIAS_BIAS_SEL_PWD_ICCPLL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCPLL25_LSB) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK) +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MSB 12 +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB 10 +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK 0x00001c00 +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB) +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK) +#define BIAS_BIAS_SEL_PWD_ICXTAL25_MSB 9 +#define BIAS_BIAS_SEL_PWD_ICXTAL25_LSB 7 +#define BIAS_BIAS_SEL_PWD_ICXTAL25_MASK 0x00000380 +#define BIAS_BIAS_SEL_PWD_ICXTAL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK) >> BIAS_BIAS_SEL_PWD_ICXTAL25_LSB) +#define BIAS_BIAS_SEL_PWD_ICXTAL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICXTAL25_LSB) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK) +#define BIAS_BIAS_SEL_PWD_ICTSENS25_MSB 6 +#define BIAS_BIAS_SEL_PWD_ICTSENS25_LSB 4 +#define BIAS_BIAS_SEL_PWD_ICTSENS25_MASK 0x00000070 +#define BIAS_BIAS_SEL_PWD_ICTSENS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK) >> BIAS_BIAS_SEL_PWD_ICTSENS25_LSB) +#define BIAS_BIAS_SEL_PWD_ICTSENS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTSENS25_LSB) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK) +#define BIAS_BIAS_SEL_PWD_ICTXPC25_MSB 3 +#define BIAS_BIAS_SEL_PWD_ICTXPC25_LSB 1 +#define BIAS_BIAS_SEL_PWD_ICTXPC25_MASK 0x0000000e +#define BIAS_BIAS_SEL_PWD_ICTXPC25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK) >> BIAS_BIAS_SEL_PWD_ICTXPC25_LSB) +#define BIAS_BIAS_SEL_PWD_ICTXPC25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTXPC25_LSB) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK) +#define BIAS_BIAS_SEL_PWD_ICLDO25_MSB 0 +#define BIAS_BIAS_SEL_PWD_ICLDO25_LSB 0 +#define BIAS_BIAS_SEL_PWD_ICLDO25_MASK 0x00000001 +#define BIAS_BIAS_SEL_PWD_ICLDO25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK) >> BIAS_BIAS_SEL_PWD_ICLDO25_LSB) +#define BIAS_BIAS_SEL_PWD_ICLDO25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICLDO25_LSB) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK) + +#define BIAS_BIAS1_ADDRESS 0x0000003c +#define BIAS_BIAS1_OFFSET 0x0000003c +#define BIAS_BIAS1_PWD_ICDAC2BB25_MSB 31 +#define BIAS_BIAS1_PWD_ICDAC2BB25_LSB 29 +#define BIAS_BIAS1_PWD_ICDAC2BB25_MASK 0xe0000000 +#define BIAS_BIAS1_PWD_ICDAC2BB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK) >> BIAS_BIAS1_PWD_ICDAC2BB25_LSB) +#define BIAS_BIAS1_PWD_ICDAC2BB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDAC2BB25_LSB) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK) +#define BIAS_BIAS1_PWD_IC2GVGM25_MSB 28 +#define BIAS_BIAS1_PWD_IC2GVGM25_LSB 26 +#define BIAS_BIAS1_PWD_IC2GVGM25_MASK 0x1c000000 +#define BIAS_BIAS1_PWD_IC2GVGM25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GVGM25_MASK) >> BIAS_BIAS1_PWD_IC2GVGM25_LSB) +#define BIAS_BIAS1_PWD_IC2GVGM25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GVGM25_LSB) & BIAS_BIAS1_PWD_IC2GVGM25_MASK) +#define BIAS_BIAS1_PWD_IC2GRFFE25_MSB 25 +#define BIAS_BIAS1_PWD_IC2GRFFE25_LSB 23 +#define BIAS_BIAS1_PWD_IC2GRFFE25_MASK 0x03800000 +#define BIAS_BIAS1_PWD_IC2GRFFE25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK) >> BIAS_BIAS1_PWD_IC2GRFFE25_LSB) +#define BIAS_BIAS1_PWD_IC2GRFFE25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GRFFE25_LSB) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK) +#define BIAS_BIAS1_PWD_IC2GLOREG25_MSB 22 +#define BIAS_BIAS1_PWD_IC2GLOREG25_LSB 20 +#define BIAS_BIAS1_PWD_IC2GLOREG25_MASK 0x00700000 +#define BIAS_BIAS1_PWD_IC2GLOREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLOREG25_LSB) +#define BIAS_BIAS1_PWD_IC2GLOREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLOREG25_LSB) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK) +#define BIAS_BIAS1_PWD_IC2GLNAREG25_MSB 19 +#define BIAS_BIAS1_PWD_IC2GLNAREG25_LSB 17 +#define BIAS_BIAS1_PWD_IC2GLNAREG25_MASK 0x000e0000 +#define BIAS_BIAS1_PWD_IC2GLNAREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLNAREG25_LSB) +#define BIAS_BIAS1_PWD_IC2GLNAREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLNAREG25_LSB) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK) +#define BIAS_BIAS1_PWD_ICDETECTORB25_MSB 16 +#define BIAS_BIAS1_PWD_ICDETECTORB25_LSB 16 +#define BIAS_BIAS1_PWD_ICDETECTORB25_MASK 0x00010000 +#define BIAS_BIAS1_PWD_ICDETECTORB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORB25_LSB) +#define BIAS_BIAS1_PWD_ICDETECTORB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETECTORB25_LSB) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK) +#define BIAS_BIAS1_PWD_ICDETECTORA25_MSB 15 +#define BIAS_BIAS1_PWD_ICDETECTORA25_LSB 15 +#define BIAS_BIAS1_PWD_ICDETECTORA25_MASK 0x00008000 +#define BIAS_BIAS1_PWD_ICDETECTORA25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORA25_LSB) +#define BIAS_BIAS1_PWD_ICDETECTORA25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETECTORA25_LSB) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK) +#define BIAS_BIAS1_PWD_IC5GRXRF25_MSB 14 +#define BIAS_BIAS1_PWD_IC5GRXRF25_LSB 14 +#define BIAS_BIAS1_PWD_IC5GRXRF25_MASK 0x00004000 +#define BIAS_BIAS1_PWD_IC5GRXRF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK) >> BIAS_BIAS1_PWD_IC5GRXRF25_LSB) +#define BIAS_BIAS1_PWD_IC5GRXRF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GRXRF25_LSB) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK) +#define BIAS_BIAS1_PWD_IC5GTXPA25_MSB 13 +#define BIAS_BIAS1_PWD_IC5GTXPA25_LSB 11 +#define BIAS_BIAS1_PWD_IC5GTXPA25_MASK 0x00003800 +#define BIAS_BIAS1_PWD_IC5GTXPA25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK) >> BIAS_BIAS1_PWD_IC5GTXPA25_LSB) +#define BIAS_BIAS1_PWD_IC5GTXPA25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXPA25_LSB) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK) +#define BIAS_BIAS1_PWD_IC5GTXBUF25_MSB 10 +#define BIAS_BIAS1_PWD_IC5GTXBUF25_LSB 8 +#define BIAS_BIAS1_PWD_IC5GTXBUF25_MASK 0x00000700 +#define BIAS_BIAS1_PWD_IC5GTXBUF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK) >> BIAS_BIAS1_PWD_IC5GTXBUF25_LSB) +#define BIAS_BIAS1_PWD_IC5GTXBUF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXBUF25_LSB) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK) +#define BIAS_BIAS1_PWD_IC5GQB25_MSB 7 +#define BIAS_BIAS1_PWD_IC5GQB25_LSB 5 +#define BIAS_BIAS1_PWD_IC5GQB25_MASK 0x000000e0 +#define BIAS_BIAS1_PWD_IC5GQB25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GQB25_MASK) >> BIAS_BIAS1_PWD_IC5GQB25_LSB) +#define BIAS_BIAS1_PWD_IC5GQB25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GQB25_LSB) & BIAS_BIAS1_PWD_IC5GQB25_MASK) +#define BIAS_BIAS1_PWD_IC5GMIXQ25_MSB 4 +#define BIAS_BIAS1_PWD_IC5GMIXQ25_LSB 2 +#define BIAS_BIAS1_PWD_IC5GMIXQ25_MASK 0x0000001c +#define BIAS_BIAS1_PWD_IC5GMIXQ25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK) >> BIAS_BIAS1_PWD_IC5GMIXQ25_LSB) +#define BIAS_BIAS1_PWD_IC5GMIXQ25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GMIXQ25_LSB) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK) +#define BIAS_BIAS1_SPARE_MSB 1 +#define BIAS_BIAS1_SPARE_LSB 0 +#define BIAS_BIAS1_SPARE_MASK 0x00000003 +#define BIAS_BIAS1_SPARE_GET(x) (((x) & BIAS_BIAS1_SPARE_MASK) >> BIAS_BIAS1_SPARE_LSB) +#define BIAS_BIAS1_SPARE_SET(x) (((x) << BIAS_BIAS1_SPARE_LSB) & BIAS_BIAS1_SPARE_MASK) + +#define BIAS_BIAS2_ADDRESS 0x00000040 +#define BIAS_BIAS2_OFFSET 0x00000040 +#define BIAS_BIAS2_PWD_IC5GMIXI25_MSB 31 +#define BIAS_BIAS2_PWD_IC5GMIXI25_LSB 29 +#define BIAS_BIAS2_PWD_IC5GMIXI25_MASK 0xe0000000 +#define BIAS_BIAS2_PWD_IC5GMIXI25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK) >> BIAS_BIAS2_PWD_IC5GMIXI25_LSB) +#define BIAS_BIAS2_PWD_IC5GMIXI25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GMIXI25_LSB) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK) +#define BIAS_BIAS2_PWD_IC5GDIV25_MSB 28 +#define BIAS_BIAS2_PWD_IC5GDIV25_LSB 26 +#define BIAS_BIAS2_PWD_IC5GDIV25_MASK 0x1c000000 +#define BIAS_BIAS2_PWD_IC5GDIV25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GDIV25_MASK) >> BIAS_BIAS2_PWD_IC5GDIV25_LSB) +#define BIAS_BIAS2_PWD_IC5GDIV25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GDIV25_LSB) & BIAS_BIAS2_PWD_IC5GDIV25_MASK) +#define BIAS_BIAS2_PWD_IC5GLOREG25_MSB 25 +#define BIAS_BIAS2_PWD_IC5GLOREG25_LSB 23 +#define BIAS_BIAS2_PWD_IC5GLOREG25_MASK 0x03800000 +#define BIAS_BIAS2_PWD_IC5GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK) >> BIAS_BIAS2_PWD_IC5GLOREG25_LSB) +#define BIAS_BIAS2_PWD_IC5GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GLOREG25_LSB) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK) +#define BIAS_BIAS2_PWD_IRPLL25_MSB 22 +#define BIAS_BIAS2_PWD_IRPLL25_LSB 22 +#define BIAS_BIAS2_PWD_IRPLL25_MASK 0x00400000 +#define BIAS_BIAS2_PWD_IRPLL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRPLL25_MASK) >> BIAS_BIAS2_PWD_IRPLL25_LSB) +#define BIAS_BIAS2_PWD_IRPLL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRPLL25_LSB) & BIAS_BIAS2_PWD_IRPLL25_MASK) +#define BIAS_BIAS2_PWD_IRXTAL25_MSB 21 +#define BIAS_BIAS2_PWD_IRXTAL25_LSB 19 +#define BIAS_BIAS2_PWD_IRXTAL25_MASK 0x00380000 +#define BIAS_BIAS2_PWD_IRXTAL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRXTAL25_MASK) >> BIAS_BIAS2_PWD_IRXTAL25_LSB) +#define BIAS_BIAS2_PWD_IRXTAL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRXTAL25_LSB) & BIAS_BIAS2_PWD_IRXTAL25_MASK) +#define BIAS_BIAS2_PWD_IRTSENS25_MSB 18 +#define BIAS_BIAS2_PWD_IRTSENS25_LSB 16 +#define BIAS_BIAS2_PWD_IRTSENS25_MASK 0x00070000 +#define BIAS_BIAS2_PWD_IRTSENS25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTSENS25_MASK) >> BIAS_BIAS2_PWD_IRTSENS25_LSB) +#define BIAS_BIAS2_PWD_IRTSENS25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTSENS25_LSB) & BIAS_BIAS2_PWD_IRTSENS25_MASK) +#define BIAS_BIAS2_PWD_IRTXPC25_MSB 15 +#define BIAS_BIAS2_PWD_IRTXPC25_LSB 13 +#define BIAS_BIAS2_PWD_IRTXPC25_MASK 0x0000e000 +#define BIAS_BIAS2_PWD_IRTXPC25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTXPC25_MASK) >> BIAS_BIAS2_PWD_IRTXPC25_LSB) +#define BIAS_BIAS2_PWD_IRTXPC25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTXPC25_LSB) & BIAS_BIAS2_PWD_IRTXPC25_MASK) +#define BIAS_BIAS2_PWD_IRLDO25_MSB 12 +#define BIAS_BIAS2_PWD_IRLDO25_LSB 12 +#define BIAS_BIAS2_PWD_IRLDO25_MASK 0x00001000 +#define BIAS_BIAS2_PWD_IRLDO25_GET(x) (((x) & BIAS_BIAS2_PWD_IRLDO25_MASK) >> BIAS_BIAS2_PWD_IRLDO25_LSB) +#define BIAS_BIAS2_PWD_IRLDO25_SET(x) (((x) << BIAS_BIAS2_PWD_IRLDO25_LSB) & BIAS_BIAS2_PWD_IRLDO25_MASK) +#define BIAS_BIAS2_PWD_IR2GTXMIX25_MSB 11 +#define BIAS_BIAS2_PWD_IR2GTXMIX25_LSB 9 +#define BIAS_BIAS2_PWD_IR2GTXMIX25_MASK 0x00000e00 +#define BIAS_BIAS2_PWD_IR2GTXMIX25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK) >> BIAS_BIAS2_PWD_IR2GTXMIX25_LSB) +#define BIAS_BIAS2_PWD_IR2GTXMIX25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GTXMIX25_LSB) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK) +#define BIAS_BIAS2_PWD_IR2GLOREG25_MSB 8 +#define BIAS_BIAS2_PWD_IR2GLOREG25_LSB 6 +#define BIAS_BIAS2_PWD_IR2GLOREG25_MASK 0x000001c0 +#define BIAS_BIAS2_PWD_IR2GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLOREG25_LSB) +#define BIAS_BIAS2_PWD_IR2GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLOREG25_LSB) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK) +#define BIAS_BIAS2_PWD_IR2GLNAREG25_MSB 5 +#define BIAS_BIAS2_PWD_IR2GLNAREG25_LSB 3 +#define BIAS_BIAS2_PWD_IR2GLNAREG25_MASK 0x00000038 +#define BIAS_BIAS2_PWD_IR2GLNAREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLNAREG25_LSB) +#define BIAS_BIAS2_PWD_IR2GLNAREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLNAREG25_LSB) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK) +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MSB 2 +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB 0 +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK 0x00000007 +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_GET(x) (((x) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK) >> BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB) +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_SET(x) (((x) << BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK) + +#define BIAS_BIAS3_ADDRESS 0x00000044 +#define BIAS_BIAS3_OFFSET 0x00000044 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_MSB 31 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_LSB 29 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_MASK 0xe0000000 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK) >> BIAS_BIAS3_PWD_IR5GTXMIX25_LSB) +#define BIAS_BIAS3_PWD_IR5GTXMIX25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GTXMIX25_LSB) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK) +#define BIAS_BIAS3_PWD_IR5GAGC25_MSB 28 +#define BIAS_BIAS3_PWD_IR5GAGC25_LSB 26 +#define BIAS_BIAS3_PWD_IR5GAGC25_MASK 0x1c000000 +#define BIAS_BIAS3_PWD_IR5GAGC25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GAGC25_MASK) >> BIAS_BIAS3_PWD_IR5GAGC25_LSB) +#define BIAS_BIAS3_PWD_IR5GAGC25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GAGC25_LSB) & BIAS_BIAS3_PWD_IR5GAGC25_MASK) +#define BIAS_BIAS3_PWD_ICDAC50_MSB 25 +#define BIAS_BIAS3_PWD_ICDAC50_LSB 23 +#define BIAS_BIAS3_PWD_ICDAC50_MASK 0x03800000 +#define BIAS_BIAS3_PWD_ICDAC50_GET(x) (((x) & BIAS_BIAS3_PWD_ICDAC50_MASK) >> BIAS_BIAS3_PWD_ICDAC50_LSB) +#define BIAS_BIAS3_PWD_ICDAC50_SET(x) (((x) << BIAS_BIAS3_PWD_ICDAC50_LSB) & BIAS_BIAS3_PWD_ICDAC50_MASK) +#define BIAS_BIAS3_PWD_ICSYNTH50_MSB 22 +#define BIAS_BIAS3_PWD_ICSYNTH50_LSB 22 +#define BIAS_BIAS3_PWD_ICSYNTH50_MASK 0x00400000 +#define BIAS_BIAS3_PWD_ICSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_ICSYNTH50_MASK) >> BIAS_BIAS3_PWD_ICSYNTH50_LSB) +#define BIAS_BIAS3_PWD_ICSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_ICSYNTH50_LSB) & BIAS_BIAS3_PWD_ICSYNTH50_MASK) +#define BIAS_BIAS3_PWD_ICBB50_MSB 21 +#define BIAS_BIAS3_PWD_ICBB50_LSB 21 +#define BIAS_BIAS3_PWD_ICBB50_MASK 0x00200000 +#define BIAS_BIAS3_PWD_ICBB50_GET(x) (((x) & BIAS_BIAS3_PWD_ICBB50_MASK) >> BIAS_BIAS3_PWD_ICBB50_LSB) +#define BIAS_BIAS3_PWD_ICBB50_SET(x) (((x) << BIAS_BIAS3_PWD_ICBB50_LSB) & BIAS_BIAS3_PWD_ICBB50_MASK) +#define BIAS_BIAS3_PWD_IC2GDIV50_MSB 20 +#define BIAS_BIAS3_PWD_IC2GDIV50_LSB 18 +#define BIAS_BIAS3_PWD_IC2GDIV50_MASK 0x001c0000 +#define BIAS_BIAS3_PWD_IC2GDIV50_GET(x) (((x) & BIAS_BIAS3_PWD_IC2GDIV50_MASK) >> BIAS_BIAS3_PWD_IC2GDIV50_LSB) +#define BIAS_BIAS3_PWD_IC2GDIV50_SET(x) (((x) << BIAS_BIAS3_PWD_IC2GDIV50_LSB) & BIAS_BIAS3_PWD_IC2GDIV50_MASK) +#define BIAS_BIAS3_PWD_IRSYNTH50_MSB 17 +#define BIAS_BIAS3_PWD_IRSYNTH50_LSB 17 +#define BIAS_BIAS3_PWD_IRSYNTH50_MASK 0x00020000 +#define BIAS_BIAS3_PWD_IRSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_IRSYNTH50_MASK) >> BIAS_BIAS3_PWD_IRSYNTH50_LSB) +#define BIAS_BIAS3_PWD_IRSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_IRSYNTH50_LSB) & BIAS_BIAS3_PWD_IRSYNTH50_MASK) +#define BIAS_BIAS3_PWD_IRBB50_MSB 16 +#define BIAS_BIAS3_PWD_IRBB50_LSB 16 +#define BIAS_BIAS3_PWD_IRBB50_MASK 0x00010000 +#define BIAS_BIAS3_PWD_IRBB50_GET(x) (((x) & BIAS_BIAS3_PWD_IRBB50_MASK) >> BIAS_BIAS3_PWD_IRBB50_LSB) +#define BIAS_BIAS3_PWD_IRBB50_SET(x) (((x) << BIAS_BIAS3_PWD_IRBB50_LSB) & BIAS_BIAS3_PWD_IRBB50_MASK) +#define BIAS_BIAS3_PWD_IC25SPARE1_MSB 15 +#define BIAS_BIAS3_PWD_IC25SPARE1_LSB 13 +#define BIAS_BIAS3_PWD_IC25SPARE1_MASK 0x0000e000 +#define BIAS_BIAS3_PWD_IC25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPARE1_MASK) >> BIAS_BIAS3_PWD_IC25SPARE1_LSB) +#define BIAS_BIAS3_PWD_IC25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPARE1_LSB) & BIAS_BIAS3_PWD_IC25SPARE1_MASK) +#define BIAS_BIAS3_PWD_IC25SPARE2_MSB 12 +#define BIAS_BIAS3_PWD_IC25SPARE2_LSB 10 +#define BIAS_BIAS3_PWD_IC25SPARE2_MASK 0x00001c00 +#define BIAS_BIAS3_PWD_IC25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPARE2_MASK) >> BIAS_BIAS3_PWD_IC25SPARE2_LSB) +#define BIAS_BIAS3_PWD_IC25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPARE2_LSB) & BIAS_BIAS3_PWD_IC25SPARE2_MASK) +#define BIAS_BIAS3_PWD_IR25SPARE1_MSB 9 +#define BIAS_BIAS3_PWD_IR25SPARE1_LSB 7 +#define BIAS_BIAS3_PWD_IR25SPARE1_MASK 0x00000380 +#define BIAS_BIAS3_PWD_IR25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPARE1_MASK) >> BIAS_BIAS3_PWD_IR25SPARE1_LSB) +#define BIAS_BIAS3_PWD_IR25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPARE1_LSB) & BIAS_BIAS3_PWD_IR25SPARE1_MASK) +#define BIAS_BIAS3_PWD_IR25SPARE2_MSB 6 +#define BIAS_BIAS3_PWD_IR25SPARE2_LSB 4 +#define BIAS_BIAS3_PWD_IR25SPARE2_MASK 0x00000070 +#define BIAS_BIAS3_PWD_IR25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPARE2_MASK) >> BIAS_BIAS3_PWD_IR25SPARE2_LSB) +#define BIAS_BIAS3_PWD_IR25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPARE2_LSB) & BIAS_BIAS3_PWD_IR25SPARE2_MASK) +#define BIAS_BIAS3_PWD_ICDACREG12P5_MSB 3 +#define BIAS_BIAS3_PWD_ICDACREG12P5_LSB 1 +#define BIAS_BIAS3_PWD_ICDACREG12P5_MASK 0x0000000e +#define BIAS_BIAS3_PWD_ICDACREG12P5_GET(x) (((x) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK) >> BIAS_BIAS3_PWD_ICDACREG12P5_LSB) +#define BIAS_BIAS3_PWD_ICDACREG12P5_SET(x) (((x) << BIAS_BIAS3_PWD_ICDACREG12P5_LSB) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK) +#define BIAS_BIAS3_SPARE_MSB 0 +#define BIAS_BIAS3_SPARE_LSB 0 +#define BIAS_BIAS3_SPARE_MASK 0x00000001 +#define BIAS_BIAS3_SPARE_GET(x) (((x) & BIAS_BIAS3_SPARE_MASK) >> BIAS_BIAS3_SPARE_LSB) +#define BIAS_BIAS3_SPARE_SET(x) (((x) << BIAS_BIAS3_SPARE_LSB) & BIAS_BIAS3_SPARE_MASK) + +#define TXPC_TXPC_ADDRESS 0x00000048 +#define TXPC_TXPC_OFFSET 0x00000048 +#define TXPC_TXPC_SELINTPD_MSB 31 +#define TXPC_TXPC_SELINTPD_LSB 31 +#define TXPC_TXPC_SELINTPD_MASK 0x80000000 +#define TXPC_TXPC_SELINTPD_GET(x) (((x) & TXPC_TXPC_SELINTPD_MASK) >> TXPC_TXPC_SELINTPD_LSB) +#define TXPC_TXPC_SELINTPD_SET(x) (((x) << TXPC_TXPC_SELINTPD_LSB) & TXPC_TXPC_SELINTPD_MASK) +#define TXPC_TXPC_TEST_MSB 30 +#define TXPC_TXPC_TEST_LSB 30 +#define TXPC_TXPC_TEST_MASK 0x40000000 +#define TXPC_TXPC_TEST_GET(x) (((x) & TXPC_TXPC_TEST_MASK) >> TXPC_TXPC_TEST_LSB) +#define TXPC_TXPC_TEST_SET(x) (((x) << TXPC_TXPC_TEST_LSB) & TXPC_TXPC_TEST_MASK) +#define TXPC_TXPC_TESTGAIN_MSB 29 +#define TXPC_TXPC_TESTGAIN_LSB 28 +#define TXPC_TXPC_TESTGAIN_MASK 0x30000000 +#define TXPC_TXPC_TESTGAIN_GET(x) (((x) & TXPC_TXPC_TESTGAIN_MASK) >> TXPC_TXPC_TESTGAIN_LSB) +#define TXPC_TXPC_TESTGAIN_SET(x) (((x) << TXPC_TXPC_TESTGAIN_LSB) & TXPC_TXPC_TESTGAIN_MASK) +#define TXPC_TXPC_TESTDAC_MSB 27 +#define TXPC_TXPC_TESTDAC_LSB 22 +#define TXPC_TXPC_TESTDAC_MASK 0x0fc00000 +#define TXPC_TXPC_TESTDAC_GET(x) (((x) & TXPC_TXPC_TESTDAC_MASK) >> TXPC_TXPC_TESTDAC_LSB) +#define TXPC_TXPC_TESTDAC_SET(x) (((x) << TXPC_TXPC_TESTDAC_LSB) & TXPC_TXPC_TESTDAC_MASK) +#define TXPC_TXPC_TESTPWDPC_MSB 21 +#define TXPC_TXPC_TESTPWDPC_LSB 21 +#define TXPC_TXPC_TESTPWDPC_MASK 0x00200000 +#define TXPC_TXPC_TESTPWDPC_GET(x) (((x) & TXPC_TXPC_TESTPWDPC_MASK) >> TXPC_TXPC_TESTPWDPC_LSB) +#define TXPC_TXPC_TESTPWDPC_SET(x) (((x) << TXPC_TXPC_TESTPWDPC_LSB) & TXPC_TXPC_TESTPWDPC_MASK) +#define TXPC_TXPC_CURHALF_MSB 20 +#define TXPC_TXPC_CURHALF_LSB 20 +#define TXPC_TXPC_CURHALF_MASK 0x00100000 +#define TXPC_TXPC_CURHALF_GET(x) (((x) & TXPC_TXPC_CURHALF_MASK) >> TXPC_TXPC_CURHALF_LSB) +#define TXPC_TXPC_CURHALF_SET(x) (((x) << TXPC_TXPC_CURHALF_LSB) & TXPC_TXPC_CURHALF_MASK) +#define TXPC_TXPC_NEGOUT_MSB 19 +#define TXPC_TXPC_NEGOUT_LSB 19 +#define TXPC_TXPC_NEGOUT_MASK 0x00080000 +#define TXPC_TXPC_NEGOUT_GET(x) (((x) & TXPC_TXPC_NEGOUT_MASK) >> TXPC_TXPC_NEGOUT_LSB) +#define TXPC_TXPC_NEGOUT_SET(x) (((x) << TXPC_TXPC_NEGOUT_LSB) & TXPC_TXPC_NEGOUT_MASK) +#define TXPC_TXPC_CLKDELAY_MSB 18 +#define TXPC_TXPC_CLKDELAY_LSB 18 +#define TXPC_TXPC_CLKDELAY_MASK 0x00040000 +#define TXPC_TXPC_CLKDELAY_GET(x) (((x) & TXPC_TXPC_CLKDELAY_MASK) >> TXPC_TXPC_CLKDELAY_LSB) +#define TXPC_TXPC_CLKDELAY_SET(x) (((x) << TXPC_TXPC_CLKDELAY_LSB) & TXPC_TXPC_CLKDELAY_MASK) +#define TXPC_TXPC_SELMODREF_MSB 17 +#define TXPC_TXPC_SELMODREF_LSB 17 +#define TXPC_TXPC_SELMODREF_MASK 0x00020000 +#define TXPC_TXPC_SELMODREF_GET(x) (((x) & TXPC_TXPC_SELMODREF_MASK) >> TXPC_TXPC_SELMODREF_LSB) +#define TXPC_TXPC_SELMODREF_SET(x) (((x) << TXPC_TXPC_SELMODREF_LSB) & TXPC_TXPC_SELMODREF_MASK) +#define TXPC_TXPC_SELCMOUT_MSB 16 +#define TXPC_TXPC_SELCMOUT_LSB 16 +#define TXPC_TXPC_SELCMOUT_MASK 0x00010000 +#define TXPC_TXPC_SELCMOUT_GET(x) (((x) & TXPC_TXPC_SELCMOUT_MASK) >> TXPC_TXPC_SELCMOUT_LSB) +#define TXPC_TXPC_SELCMOUT_SET(x) (((x) << TXPC_TXPC_SELCMOUT_LSB) & TXPC_TXPC_SELCMOUT_MASK) +#define TXPC_TXPC_TSMODE_MSB 15 +#define TXPC_TXPC_TSMODE_LSB 14 +#define TXPC_TXPC_TSMODE_MASK 0x0000c000 +#define TXPC_TXPC_TSMODE_GET(x) (((x) & TXPC_TXPC_TSMODE_MASK) >> TXPC_TXPC_TSMODE_LSB) +#define TXPC_TXPC_TSMODE_SET(x) (((x) << TXPC_TXPC_TSMODE_LSB) & TXPC_TXPC_TSMODE_MASK) +#define TXPC_TXPC_N_MSB 13 +#define TXPC_TXPC_N_LSB 6 +#define TXPC_TXPC_N_MASK 0x00003fc0 +#define TXPC_TXPC_N_GET(x) (((x) & TXPC_TXPC_N_MASK) >> TXPC_TXPC_N_LSB) +#define TXPC_TXPC_N_SET(x) (((x) << TXPC_TXPC_N_LSB) & TXPC_TXPC_N_MASK) +#define TXPC_TXPC_ON1STSYNTHON_MSB 5 +#define TXPC_TXPC_ON1STSYNTHON_LSB 5 +#define TXPC_TXPC_ON1STSYNTHON_MASK 0x00000020 +#define TXPC_TXPC_ON1STSYNTHON_GET(x) (((x) & TXPC_TXPC_ON1STSYNTHON_MASK) >> TXPC_TXPC_ON1STSYNTHON_LSB) +#define TXPC_TXPC_ON1STSYNTHON_SET(x) (((x) << TXPC_TXPC_ON1STSYNTHON_LSB) & TXPC_TXPC_ON1STSYNTHON_MASK) +#define TXPC_TXPC_SELINIT_MSB 4 +#define TXPC_TXPC_SELINIT_LSB 3 +#define TXPC_TXPC_SELINIT_MASK 0x00000018 +#define TXPC_TXPC_SELINIT_GET(x) (((x) & TXPC_TXPC_SELINIT_MASK) >> TXPC_TXPC_SELINIT_LSB) +#define TXPC_TXPC_SELINIT_SET(x) (((x) << TXPC_TXPC_SELINIT_LSB) & TXPC_TXPC_SELINIT_MASK) +#define TXPC_TXPC_SELCOUNT_MSB 2 +#define TXPC_TXPC_SELCOUNT_LSB 2 +#define TXPC_TXPC_SELCOUNT_MASK 0x00000004 +#define TXPC_TXPC_SELCOUNT_GET(x) (((x) & TXPC_TXPC_SELCOUNT_MASK) >> TXPC_TXPC_SELCOUNT_LSB) +#define TXPC_TXPC_SELCOUNT_SET(x) (((x) << TXPC_TXPC_SELCOUNT_LSB) & TXPC_TXPC_SELCOUNT_MASK) +#define TXPC_TXPC_ATBSEL_MSB 1 +#define TXPC_TXPC_ATBSEL_LSB 0 +#define TXPC_TXPC_ATBSEL_MASK 0x00000003 +#define TXPC_TXPC_ATBSEL_GET(x) (((x) & TXPC_TXPC_ATBSEL_MASK) >> TXPC_TXPC_ATBSEL_LSB) +#define TXPC_TXPC_ATBSEL_SET(x) (((x) << TXPC_TXPC_ATBSEL_LSB) & TXPC_TXPC_ATBSEL_MASK) + +#define TXPC_MISC_ADDRESS 0x0000004c +#define TXPC_MISC_OFFSET 0x0000004c +#define TXPC_MISC_FLIPBMODE_MSB 31 +#define TXPC_MISC_FLIPBMODE_LSB 31 +#define TXPC_MISC_FLIPBMODE_MASK 0x80000000 +#define TXPC_MISC_FLIPBMODE_GET(x) (((x) & TXPC_MISC_FLIPBMODE_MASK) >> TXPC_MISC_FLIPBMODE_LSB) +#define TXPC_MISC_FLIPBMODE_SET(x) (((x) << TXPC_MISC_FLIPBMODE_LSB) & TXPC_MISC_FLIPBMODE_MASK) +#define TXPC_MISC_LEVEL_MSB 30 +#define TXPC_MISC_LEVEL_LSB 29 +#define TXPC_MISC_LEVEL_MASK 0x60000000 +#define TXPC_MISC_LEVEL_GET(x) (((x) & TXPC_MISC_LEVEL_MASK) >> TXPC_MISC_LEVEL_LSB) +#define TXPC_MISC_LEVEL_SET(x) (((x) << TXPC_MISC_LEVEL_LSB) & TXPC_MISC_LEVEL_MASK) +#define TXPC_MISC_LDO_TEST_MODE_MSB 28 +#define TXPC_MISC_LDO_TEST_MODE_LSB 28 +#define TXPC_MISC_LDO_TEST_MODE_MASK 0x10000000 +#define TXPC_MISC_LDO_TEST_MODE_GET(x) (((x) & TXPC_MISC_LDO_TEST_MODE_MASK) >> TXPC_MISC_LDO_TEST_MODE_LSB) +#define TXPC_MISC_LDO_TEST_MODE_SET(x) (((x) << TXPC_MISC_LDO_TEST_MODE_LSB) & TXPC_MISC_LDO_TEST_MODE_MASK) +#define TXPC_MISC_NOTCXODET_MSB 27 +#define TXPC_MISC_NOTCXODET_LSB 27 +#define TXPC_MISC_NOTCXODET_MASK 0x08000000 +#define TXPC_MISC_NOTCXODET_GET(x) (((x) & TXPC_MISC_NOTCXODET_MASK) >> TXPC_MISC_NOTCXODET_LSB) +#define TXPC_MISC_NOTCXODET_SET(x) (((x) << TXPC_MISC_NOTCXODET_LSB) & TXPC_MISC_NOTCXODET_MASK) +#define TXPC_MISC_PWDCLKIND_MSB 26 +#define TXPC_MISC_PWDCLKIND_LSB 26 +#define TXPC_MISC_PWDCLKIND_MASK 0x04000000 +#define TXPC_MISC_PWDCLKIND_GET(x) (((x) & TXPC_MISC_PWDCLKIND_MASK) >> TXPC_MISC_PWDCLKIND_LSB) +#define TXPC_MISC_PWDCLKIND_SET(x) (((x) << TXPC_MISC_PWDCLKIND_LSB) & TXPC_MISC_PWDCLKIND_MASK) +#define TXPC_MISC_PWDXINPAD_MSB 25 +#define TXPC_MISC_PWDXINPAD_LSB 25 +#define TXPC_MISC_PWDXINPAD_MASK 0x02000000 +#define TXPC_MISC_PWDXINPAD_GET(x) (((x) & TXPC_MISC_PWDXINPAD_MASK) >> TXPC_MISC_PWDXINPAD_LSB) +#define TXPC_MISC_PWDXINPAD_SET(x) (((x) << TXPC_MISC_PWDXINPAD_LSB) & TXPC_MISC_PWDXINPAD_MASK) +#define TXPC_MISC_LOCALBIAS_MSB 24 +#define TXPC_MISC_LOCALBIAS_LSB 24 +#define TXPC_MISC_LOCALBIAS_MASK 0x01000000 +#define TXPC_MISC_LOCALBIAS_GET(x) (((x) & TXPC_MISC_LOCALBIAS_MASK) >> TXPC_MISC_LOCALBIAS_LSB) +#define TXPC_MISC_LOCALBIAS_SET(x) (((x) << TXPC_MISC_LOCALBIAS_LSB) & TXPC_MISC_LOCALBIAS_MASK) +#define TXPC_MISC_LOCALBIAS2X_MSB 23 +#define TXPC_MISC_LOCALBIAS2X_LSB 23 +#define TXPC_MISC_LOCALBIAS2X_MASK 0x00800000 +#define TXPC_MISC_LOCALBIAS2X_GET(x) (((x) & TXPC_MISC_LOCALBIAS2X_MASK) >> TXPC_MISC_LOCALBIAS2X_LSB) +#define TXPC_MISC_LOCALBIAS2X_SET(x) (((x) << TXPC_MISC_LOCALBIAS2X_LSB) & TXPC_MISC_LOCALBIAS2X_MASK) +#define TXPC_MISC_SELTSP_MSB 22 +#define TXPC_MISC_SELTSP_LSB 22 +#define TXPC_MISC_SELTSP_MASK 0x00400000 +#define TXPC_MISC_SELTSP_GET(x) (((x) & TXPC_MISC_SELTSP_MASK) >> TXPC_MISC_SELTSP_LSB) +#define TXPC_MISC_SELTSP_SET(x) (((x) << TXPC_MISC_SELTSP_LSB) & TXPC_MISC_SELTSP_MASK) +#define TXPC_MISC_SELTSN_MSB 21 +#define TXPC_MISC_SELTSN_LSB 21 +#define TXPC_MISC_SELTSN_MASK 0x00200000 +#define TXPC_MISC_SELTSN_GET(x) (((x) & TXPC_MISC_SELTSN_MASK) >> TXPC_MISC_SELTSN_LSB) +#define TXPC_MISC_SELTSN_SET(x) (((x) << TXPC_MISC_SELTSN_LSB) & TXPC_MISC_SELTSN_MASK) +#define TXPC_MISC_SPARE_A_MSB 20 +#define TXPC_MISC_SPARE_A_LSB 18 +#define TXPC_MISC_SPARE_A_MASK 0x001c0000 +#define TXPC_MISC_SPARE_A_GET(x) (((x) & TXPC_MISC_SPARE_A_MASK) >> TXPC_MISC_SPARE_A_LSB) +#define TXPC_MISC_SPARE_A_SET(x) (((x) << TXPC_MISC_SPARE_A_LSB) & TXPC_MISC_SPARE_A_MASK) +#define TXPC_MISC_DECOUT_MSB 17 +#define TXPC_MISC_DECOUT_LSB 8 +#define TXPC_MISC_DECOUT_MASK 0x0003ff00 +#define TXPC_MISC_DECOUT_GET(x) (((x) & TXPC_MISC_DECOUT_MASK) >> TXPC_MISC_DECOUT_LSB) +#define TXPC_MISC_DECOUT_SET(x) (((x) << TXPC_MISC_DECOUT_LSB) & TXPC_MISC_DECOUT_MASK) +#define TXPC_MISC_XTALDIV_MSB 7 +#define TXPC_MISC_XTALDIV_LSB 6 +#define TXPC_MISC_XTALDIV_MASK 0x000000c0 +#define TXPC_MISC_XTALDIV_GET(x) (((x) & TXPC_MISC_XTALDIV_MASK) >> TXPC_MISC_XTALDIV_LSB) +#define TXPC_MISC_XTALDIV_SET(x) (((x) << TXPC_MISC_XTALDIV_LSB) & TXPC_MISC_XTALDIV_MASK) +#define TXPC_MISC_SPARE_MSB 5 +#define TXPC_MISC_SPARE_LSB 0 +#define TXPC_MISC_SPARE_MASK 0x0000003f +#define TXPC_MISC_SPARE_GET(x) (((x) & TXPC_MISC_SPARE_MASK) >> TXPC_MISC_SPARE_LSB) +#define TXPC_MISC_SPARE_SET(x) (((x) << TXPC_MISC_SPARE_LSB) & TXPC_MISC_SPARE_MASK) + +#define RXTXBB_RXTXBB1_ADDRESS 0x00000050 +#define RXTXBB_RXTXBB1_OFFSET 0x00000050 +#define RXTXBB_RXTXBB1_SPARE_MSB 31 +#define RXTXBB_RXTXBB1_SPARE_LSB 19 +#define RXTXBB_RXTXBB1_SPARE_MASK 0xfff80000 +#define RXTXBB_RXTXBB1_SPARE_GET(x) (((x) & RXTXBB_RXTXBB1_SPARE_MASK) >> RXTXBB_RXTXBB1_SPARE_LSB) +#define RXTXBB_RXTXBB1_SPARE_SET(x) (((x) << RXTXBB_RXTXBB1_SPARE_LSB) & RXTXBB_RXTXBB1_SPARE_MASK) +#define RXTXBB_RXTXBB1_FNOTCH_MSB 18 +#define RXTXBB_RXTXBB1_FNOTCH_LSB 17 +#define RXTXBB_RXTXBB1_FNOTCH_MASK 0x00060000 +#define RXTXBB_RXTXBB1_FNOTCH_GET(x) (((x) & RXTXBB_RXTXBB1_FNOTCH_MASK) >> RXTXBB_RXTXBB1_FNOTCH_LSB) +#define RXTXBB_RXTXBB1_FNOTCH_SET(x) (((x) << RXTXBB_RXTXBB1_FNOTCH_LSB) & RXTXBB_RXTXBB1_FNOTCH_MASK) +#define RXTXBB_RXTXBB1_SEL_ATB_MSB 16 +#define RXTXBB_RXTXBB1_SEL_ATB_LSB 9 +#define RXTXBB_RXTXBB1_SEL_ATB_MASK 0x0001fe00 +#define RXTXBB_RXTXBB1_SEL_ATB_GET(x) (((x) & RXTXBB_RXTXBB1_SEL_ATB_MASK) >> RXTXBB_RXTXBB1_SEL_ATB_LSB) +#define RXTXBB_RXTXBB1_SEL_ATB_SET(x) (((x) << RXTXBB_RXTXBB1_SEL_ATB_LSB) & RXTXBB_RXTXBB1_SEL_ATB_MASK) +#define RXTXBB_RXTXBB1_PDDACINTERFACE_MSB 8 +#define RXTXBB_RXTXBB1_PDDACINTERFACE_LSB 8 +#define RXTXBB_RXTXBB1_PDDACINTERFACE_MASK 0x00000100 +#define RXTXBB_RXTXBB1_PDDACINTERFACE_GET(x) (((x) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK) >> RXTXBB_RXTXBB1_PDDACINTERFACE_LSB) +#define RXTXBB_RXTXBB1_PDDACINTERFACE_SET(x) (((x) << RXTXBB_RXTXBB1_PDDACINTERFACE_LSB) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK) +#define RXTXBB_RXTXBB1_PDV2I_MSB 7 +#define RXTXBB_RXTXBB1_PDV2I_LSB 7 +#define RXTXBB_RXTXBB1_PDV2I_MASK 0x00000080 +#define RXTXBB_RXTXBB1_PDV2I_GET(x) (((x) & RXTXBB_RXTXBB1_PDV2I_MASK) >> RXTXBB_RXTXBB1_PDV2I_LSB) +#define RXTXBB_RXTXBB1_PDV2I_SET(x) (((x) << RXTXBB_RXTXBB1_PDV2I_LSB) & RXTXBB_RXTXBB1_PDV2I_MASK) +#define RXTXBB_RXTXBB1_PDI2V_MSB 6 +#define RXTXBB_RXTXBB1_PDI2V_LSB 6 +#define RXTXBB_RXTXBB1_PDI2V_MASK 0x00000040 +#define RXTXBB_RXTXBB1_PDI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDI2V_MASK) >> RXTXBB_RXTXBB1_PDI2V_LSB) +#define RXTXBB_RXTXBB1_PDI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDI2V_LSB) & RXTXBB_RXTXBB1_PDI2V_MASK) +#define RXTXBB_RXTXBB1_PDRXTXBB_MSB 5 +#define RXTXBB_RXTXBB1_PDRXTXBB_LSB 5 +#define RXTXBB_RXTXBB1_PDRXTXBB_MASK 0x00000020 +#define RXTXBB_RXTXBB1_PDRXTXBB_GET(x) (((x) & RXTXBB_RXTXBB1_PDRXTXBB_MASK) >> RXTXBB_RXTXBB1_PDRXTXBB_LSB) +#define RXTXBB_RXTXBB1_PDRXTXBB_SET(x) (((x) << RXTXBB_RXTXBB1_PDRXTXBB_LSB) & RXTXBB_RXTXBB1_PDRXTXBB_MASK) +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MSB 4 +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB 4 +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK 0x00000010 +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB) +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK) +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MSB 3 +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB 3 +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK 0x00000008 +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB) +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK) +#define RXTXBB_RXTXBB1_PDOFFSETI2V_MSB 2 +#define RXTXBB_RXTXBB1_PDOFFSETI2V_LSB 2 +#define RXTXBB_RXTXBB1_PDOFFSETI2V_MASK 0x00000004 +#define RXTXBB_RXTXBB1_PDOFFSETI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK) >> RXTXBB_RXTXBB1_PDOFFSETI2V_LSB) +#define RXTXBB_RXTXBB1_PDOFFSETI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETI2V_LSB) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK) +#define RXTXBB_RXTXBB1_PDLOQ_MSB 1 +#define RXTXBB_RXTXBB1_PDLOQ_LSB 1 +#define RXTXBB_RXTXBB1_PDLOQ_MASK 0x00000002 +#define RXTXBB_RXTXBB1_PDLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDLOQ_MASK) >> RXTXBB_RXTXBB1_PDLOQ_LSB) +#define RXTXBB_RXTXBB1_PDLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDLOQ_LSB) & RXTXBB_RXTXBB1_PDLOQ_MASK) +#define RXTXBB_RXTXBB1_PDHIQ_MSB 0 +#define RXTXBB_RXTXBB1_PDHIQ_LSB 0 +#define RXTXBB_RXTXBB1_PDHIQ_MASK 0x00000001 +#define RXTXBB_RXTXBB1_PDHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDHIQ_MASK) >> RXTXBB_RXTXBB1_PDHIQ_LSB) +#define RXTXBB_RXTXBB1_PDHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDHIQ_LSB) & RXTXBB_RXTXBB1_PDHIQ_MASK) + +#define RXTXBB_RXTXBB2_ADDRESS 0x00000054 +#define RXTXBB_RXTXBB2_OFFSET 0x00000054 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MSB 31 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB 29 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK 0xe0000000 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB) +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK) +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MSB 28 +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB 26 +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK 0x1c000000 +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB) +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK) +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MSB 25 +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB 23 +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK 0x03800000 +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB) +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK) +#define RXTXBB_RXTXBB2_SPARE_MSB 22 +#define RXTXBB_RXTXBB2_SPARE_LSB 21 +#define RXTXBB_RXTXBB2_SPARE_MASK 0x00600000 +#define RXTXBB_RXTXBB2_SPARE_GET(x) (((x) & RXTXBB_RXTXBB2_SPARE_MASK) >> RXTXBB_RXTXBB2_SPARE_LSB) +#define RXTXBB_RXTXBB2_SPARE_SET(x) (((x) << RXTXBB_RXTXBB2_SPARE_LSB) & RXTXBB_RXTXBB2_SPARE_MASK) +#define RXTXBB_RXTXBB2_SHORTBUFFER_MSB 20 +#define RXTXBB_RXTXBB2_SHORTBUFFER_LSB 20 +#define RXTXBB_RXTXBB2_SHORTBUFFER_MASK 0x00100000 +#define RXTXBB_RXTXBB2_SHORTBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK) >> RXTXBB_RXTXBB2_SHORTBUFFER_LSB) +#define RXTXBB_RXTXBB2_SHORTBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SHORTBUFFER_LSB) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK) +#define RXTXBB_RXTXBB2_SELBUFFER_MSB 19 +#define RXTXBB_RXTXBB2_SELBUFFER_LSB 19 +#define RXTXBB_RXTXBB2_SELBUFFER_MASK 0x00080000 +#define RXTXBB_RXTXBB2_SELBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SELBUFFER_MASK) >> RXTXBB_RXTXBB2_SELBUFFER_LSB) +#define RXTXBB_RXTXBB2_SELBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SELBUFFER_LSB) & RXTXBB_RXTXBB2_SELBUFFER_MASK) +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MSB 18 +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB 18 +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK 0x00040000 +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK) +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MSB 17 +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB 17 +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK 0x00020000 +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK) +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MSB 16 +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB 16 +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK 0x00010000 +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK) +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MSB 15 +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB 15 +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK 0x00008000 +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK) +#define RXTXBB_RXTXBB2_CMSEL_MSB 14 +#define RXTXBB_RXTXBB2_CMSEL_LSB 13 +#define RXTXBB_RXTXBB2_CMSEL_MASK 0x00006000 +#define RXTXBB_RXTXBB2_CMSEL_GET(x) (((x) & RXTXBB_RXTXBB2_CMSEL_MASK) >> RXTXBB_RXTXBB2_CMSEL_LSB) +#define RXTXBB_RXTXBB2_CMSEL_SET(x) (((x) << RXTXBB_RXTXBB2_CMSEL_LSB) & RXTXBB_RXTXBB2_CMSEL_MASK) +#define RXTXBB_RXTXBB2_FILTERFC_MSB 12 +#define RXTXBB_RXTXBB2_FILTERFC_LSB 8 +#define RXTXBB_RXTXBB2_FILTERFC_MASK 0x00001f00 +#define RXTXBB_RXTXBB2_FILTERFC_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERFC_MASK) >> RXTXBB_RXTXBB2_FILTERFC_LSB) +#define RXTXBB_RXTXBB2_FILTERFC_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERFC_LSB) & RXTXBB_RXTXBB2_FILTERFC_MASK) +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MSB 7 +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB 7 +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK 0x00000080 +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_GET(x) (((x) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK) >> RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB) +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_SET(x) (((x) << RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK) +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MSB 6 +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB 6 +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK 0x00000040 +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK) >> RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB) +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK) +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MSB 5 +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB 5 +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK 0x00000020 +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MSB 4 +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB 4 +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK 0x00000010 +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MSB 3 +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB 3 +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK 0x00000008 +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MSB 2 +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB 2 +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK 0x00000004 +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MSB 1 +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB 1 +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK 0x00000002 +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MSB 0 +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB 0 +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK 0x00000001 +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_GET(x) (((x) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK) >> RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB) +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_SET(x) (((x) << RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK) + +#define RXTXBB_RXTXBB3_ADDRESS 0x00000058 +#define RXTXBB_RXTXBB3_OFFSET 0x00000058 +#define RXTXBB_RXTXBB3_SPARE_MSB 31 +#define RXTXBB_RXTXBB3_SPARE_LSB 27 +#define RXTXBB_RXTXBB3_SPARE_MASK 0xf8000000 +#define RXTXBB_RXTXBB3_SPARE_GET(x) (((x) & RXTXBB_RXTXBB3_SPARE_MASK) >> RXTXBB_RXTXBB3_SPARE_LSB) +#define RXTXBB_RXTXBB3_SPARE_SET(x) (((x) << RXTXBB_RXTXBB3_SPARE_LSB) & RXTXBB_RXTXBB3_SPARE_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MSB 26 +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB 24 +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK 0x07000000 +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MSB 23 +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB 21 +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK 0x00e00000 +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MSB 20 +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB 18 +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK 0x001c0000 +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MSB 17 +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB 15 +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK 0x00038000 +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MSB 14 +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB 12 +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK 0x00007000 +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MSB 11 +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB 9 +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK 0x00000e00 +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MSB 8 +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB 6 +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK 0x000001c0 +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MSB 5 +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB 3 +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK 0x00000038 +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK) >> RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MSB 2 +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB 0 +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK 0x00000007 +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK) + +#define RXTXBB_RXTXBB4_ADDRESS 0x0000005c +#define RXTXBB_RXTXBB4_OFFSET 0x0000005c +#define RXTXBB_RXTXBB4_SPARE_MSB 31 +#define RXTXBB_RXTXBB4_SPARE_LSB 31 +#define RXTXBB_RXTXBB4_SPARE_MASK 0x80000000 +#define RXTXBB_RXTXBB4_SPARE_GET(x) (((x) & RXTXBB_RXTXBB4_SPARE_MASK) >> RXTXBB_RXTXBB4_SPARE_LSB) +#define RXTXBB_RXTXBB4_SPARE_SET(x) (((x) << RXTXBB_RXTXBB4_SPARE_LSB) & RXTXBB_RXTXBB4_SPARE_MASK) +#define RXTXBB_RXTXBB4_LOCALOFFSET_MSB 30 +#define RXTXBB_RXTXBB4_LOCALOFFSET_LSB 30 +#define RXTXBB_RXTXBB4_LOCALOFFSET_MASK 0x40000000 +#define RXTXBB_RXTXBB4_LOCALOFFSET_GET(x) (((x) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK) >> RXTXBB_RXTXBB4_LOCALOFFSET_LSB) +#define RXTXBB_RXTXBB4_LOCALOFFSET_SET(x) (((x) << RXTXBB_RXTXBB4_LOCALOFFSET_LSB) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRHII_MSB 29 +#define RXTXBB_RXTXBB4_OFSTCORRHII_LSB 25 +#define RXTXBB_RXTXBB4_OFSTCORRHII_MASK 0x3e000000 +#define RXTXBB_RXTXBB4_OFSTCORRHII_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHII_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRHII_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRHII_LSB) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MSB 24 +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB 20 +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK 0x01f00000 +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRLOI_MSB 19 +#define RXTXBB_RXTXBB4_OFSTCORRLOI_LSB 15 +#define RXTXBB_RXTXBB4_OFSTCORRLOI_MASK 0x000f8000 +#define RXTXBB_RXTXBB4_OFSTCORRLOI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOI_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRLOI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRLOI_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MSB 14 +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB 10 +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK 0x00007c00 +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MSB 9 +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB 5 +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK 0x000003e0 +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MSB 4 +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB 0 +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK 0x0000001f +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK) + +#define ADDAC_ADDAC1_ADDRESS 0x00000060 +#define ADDAC_ADDAC1_OFFSET 0x00000060 +#define ADDAC_ADDAC1_PLL_SVREG_MSB 31 +#define ADDAC_ADDAC1_PLL_SVREG_LSB 31 +#define ADDAC_ADDAC1_PLL_SVREG_MASK 0x80000000 +#define ADDAC_ADDAC1_PLL_SVREG_GET(x) (((x) & ADDAC_ADDAC1_PLL_SVREG_MASK) >> ADDAC_ADDAC1_PLL_SVREG_LSB) +#define ADDAC_ADDAC1_PLL_SVREG_SET(x) (((x) << ADDAC_ADDAC1_PLL_SVREG_LSB) & ADDAC_ADDAC1_PLL_SVREG_MASK) +#define ADDAC_ADDAC1_PLL_SCLAMP_MSB 30 +#define ADDAC_ADDAC1_PLL_SCLAMP_LSB 28 +#define ADDAC_ADDAC1_PLL_SCLAMP_MASK 0x70000000 +#define ADDAC_ADDAC1_PLL_SCLAMP_GET(x) (((x) & ADDAC_ADDAC1_PLL_SCLAMP_MASK) >> ADDAC_ADDAC1_PLL_SCLAMP_LSB) +#define ADDAC_ADDAC1_PLL_SCLAMP_SET(x) (((x) << ADDAC_ADDAC1_PLL_SCLAMP_LSB) & ADDAC_ADDAC1_PLL_SCLAMP_MASK) +#define ADDAC_ADDAC1_PLL_ATB_MSB 27 +#define ADDAC_ADDAC1_PLL_ATB_LSB 26 +#define ADDAC_ADDAC1_PLL_ATB_MASK 0x0c000000 +#define ADDAC_ADDAC1_PLL_ATB_GET(x) (((x) & ADDAC_ADDAC1_PLL_ATB_MASK) >> ADDAC_ADDAC1_PLL_ATB_LSB) +#define ADDAC_ADDAC1_PLL_ATB_SET(x) (((x) << ADDAC_ADDAC1_PLL_ATB_LSB) & ADDAC_ADDAC1_PLL_ATB_MASK) +#define ADDAC_ADDAC1_PLL_ICP_MSB 25 +#define ADDAC_ADDAC1_PLL_ICP_LSB 23 +#define ADDAC_ADDAC1_PLL_ICP_MASK 0x03800000 +#define ADDAC_ADDAC1_PLL_ICP_GET(x) (((x) & ADDAC_ADDAC1_PLL_ICP_MASK) >> ADDAC_ADDAC1_PLL_ICP_LSB) +#define ADDAC_ADDAC1_PLL_ICP_SET(x) (((x) << ADDAC_ADDAC1_PLL_ICP_LSB) & ADDAC_ADDAC1_PLL_ICP_MASK) +#define ADDAC_ADDAC1_PLL_FILTER_MSB 22 +#define ADDAC_ADDAC1_PLL_FILTER_LSB 15 +#define ADDAC_ADDAC1_PLL_FILTER_MASK 0x007f8000 +#define ADDAC_ADDAC1_PLL_FILTER_GET(x) (((x) & ADDAC_ADDAC1_PLL_FILTER_MASK) >> ADDAC_ADDAC1_PLL_FILTER_LSB) +#define ADDAC_ADDAC1_PLL_FILTER_SET(x) (((x) << ADDAC_ADDAC1_PLL_FILTER_LSB) & ADDAC_ADDAC1_PLL_FILTER_MASK) +#define ADDAC_ADDAC1_PWDPLL_MSB 14 +#define ADDAC_ADDAC1_PWDPLL_LSB 14 +#define ADDAC_ADDAC1_PWDPLL_MASK 0x00004000 +#define ADDAC_ADDAC1_PWDPLL_GET(x) (((x) & ADDAC_ADDAC1_PWDPLL_MASK) >> ADDAC_ADDAC1_PWDPLL_LSB) +#define ADDAC_ADDAC1_PWDPLL_SET(x) (((x) << ADDAC_ADDAC1_PWDPLL_LSB) & ADDAC_ADDAC1_PWDPLL_MASK) +#define ADDAC_ADDAC1_PWDADC_MSB 13 +#define ADDAC_ADDAC1_PWDADC_LSB 13 +#define ADDAC_ADDAC1_PWDADC_MASK 0x00002000 +#define ADDAC_ADDAC1_PWDADC_GET(x) (((x) & ADDAC_ADDAC1_PWDADC_MASK) >> ADDAC_ADDAC1_PWDADC_LSB) +#define ADDAC_ADDAC1_PWDADC_SET(x) (((x) << ADDAC_ADDAC1_PWDADC_LSB) & ADDAC_ADDAC1_PWDADC_MASK) +#define ADDAC_ADDAC1_PWDDAC_MSB 12 +#define ADDAC_ADDAC1_PWDDAC_LSB 12 +#define ADDAC_ADDAC1_PWDDAC_MASK 0x00001000 +#define ADDAC_ADDAC1_PWDDAC_GET(x) (((x) & ADDAC_ADDAC1_PWDDAC_MASK) >> ADDAC_ADDAC1_PWDDAC_LSB) +#define ADDAC_ADDAC1_PWDDAC_SET(x) (((x) << ADDAC_ADDAC1_PWDDAC_LSB) & ADDAC_ADDAC1_PWDDAC_MASK) +#define ADDAC_ADDAC1_FORCEMSBLOW_MSB 11 +#define ADDAC_ADDAC1_FORCEMSBLOW_LSB 11 +#define ADDAC_ADDAC1_FORCEMSBLOW_MASK 0x00000800 +#define ADDAC_ADDAC1_FORCEMSBLOW_GET(x) (((x) & ADDAC_ADDAC1_FORCEMSBLOW_MASK) >> ADDAC_ADDAC1_FORCEMSBLOW_LSB) +#define ADDAC_ADDAC1_FORCEMSBLOW_SET(x) (((x) << ADDAC_ADDAC1_FORCEMSBLOW_LSB) & ADDAC_ADDAC1_FORCEMSBLOW_MASK) +#define ADDAC_ADDAC1_SELMANPWDS_MSB 10 +#define ADDAC_ADDAC1_SELMANPWDS_LSB 10 +#define ADDAC_ADDAC1_SELMANPWDS_MASK 0x00000400 +#define ADDAC_ADDAC1_SELMANPWDS_GET(x) (((x) & ADDAC_ADDAC1_SELMANPWDS_MASK) >> ADDAC_ADDAC1_SELMANPWDS_LSB) +#define ADDAC_ADDAC1_SELMANPWDS_SET(x) (((x) << ADDAC_ADDAC1_SELMANPWDS_LSB) & ADDAC_ADDAC1_SELMANPWDS_MASK) +#define ADDAC_ADDAC1_INV_CLK160_ADC_MSB 9 +#define ADDAC_ADDAC1_INV_CLK160_ADC_LSB 9 +#define ADDAC_ADDAC1_INV_CLK160_ADC_MASK 0x00000200 +#define ADDAC_ADDAC1_INV_CLK160_ADC_GET(x) (((x) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK) >> ADDAC_ADDAC1_INV_CLK160_ADC_LSB) +#define ADDAC_ADDAC1_INV_CLK160_ADC_SET(x) (((x) << ADDAC_ADDAC1_INV_CLK160_ADC_LSB) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK) +#define ADDAC_ADDAC1_CM_SEL_MSB 8 +#define ADDAC_ADDAC1_CM_SEL_LSB 7 +#define ADDAC_ADDAC1_CM_SEL_MASK 0x00000180 +#define ADDAC_ADDAC1_CM_SEL_GET(x) (((x) & ADDAC_ADDAC1_CM_SEL_MASK) >> ADDAC_ADDAC1_CM_SEL_LSB) +#define ADDAC_ADDAC1_CM_SEL_SET(x) (((x) << ADDAC_ADDAC1_CM_SEL_LSB) & ADDAC_ADDAC1_CM_SEL_MASK) +#define ADDAC_ADDAC1_DISABLE_DAC_REG_MSB 6 +#define ADDAC_ADDAC1_DISABLE_DAC_REG_LSB 6 +#define ADDAC_ADDAC1_DISABLE_DAC_REG_MASK 0x00000040 +#define ADDAC_ADDAC1_DISABLE_DAC_REG_GET(x) (((x) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK) >> ADDAC_ADDAC1_DISABLE_DAC_REG_LSB) +#define ADDAC_ADDAC1_DISABLE_DAC_REG_SET(x) (((x) << ADDAC_ADDAC1_DISABLE_DAC_REG_LSB) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK) +#define ADDAC_ADDAC1_SPARE_MSB 5 +#define ADDAC_ADDAC1_SPARE_LSB 0 +#define ADDAC_ADDAC1_SPARE_MASK 0x0000003f +#define ADDAC_ADDAC1_SPARE_GET(x) (((x) & ADDAC_ADDAC1_SPARE_MASK) >> ADDAC_ADDAC1_SPARE_LSB) +#define ADDAC_ADDAC1_SPARE_SET(x) (((x) << ADDAC_ADDAC1_SPARE_LSB) & ADDAC_ADDAC1_SPARE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct analog_reg_reg_s { + volatile unsigned int synth_synth1; + volatile unsigned int synth_synth2; + volatile unsigned int synth_synth3; + volatile unsigned int synth_synth4; + volatile unsigned int synth_synth5; + volatile unsigned int synth_synth6; + volatile unsigned int synth_synth7; + volatile unsigned int synth_synth8; + volatile unsigned int rf5g_rf5g1; + volatile unsigned int rf5g_rf5g2; + volatile unsigned int rf2g_rf2g1; + volatile unsigned int rf2g_rf2g2; + volatile unsigned int top_gain; + volatile unsigned int top_top; + volatile unsigned int bias_bias_sel; + volatile unsigned int bias_bias1; + volatile unsigned int bias_bias2; + volatile unsigned int bias_bias3; + volatile unsigned int txpc_txpc; + volatile unsigned int txpc_misc; + volatile unsigned int rxtxbb_rxtxbb1; + volatile unsigned int rxtxbb_rxtxbb2; + volatile unsigned int rxtxbb_rxtxbb3; + volatile unsigned int rxtxbb_rxtxbb4; + volatile unsigned int addac_addac1; +} analog_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _ANALOG_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/apb_map.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/apb_map.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/apb_map.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/apb_map.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,36 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _APB_MAP_H_ +#define _APB_MAP_H_ + +#define RTC_BASE_ADDRESS 0x00004000 +#define VMC_BASE_ADDRESS 0x00008000 +#define UART_BASE_ADDRESS 0x0000c000 +#define SI_BASE_ADDRESS 0x00010000 +#define GPIO_BASE_ADDRESS 0x00014000 +#define MBOX_BASE_ADDRESS 0x00018000 +#define ANALOG_INTF_BASE_ADDRESS 0x0001c000 +#define MAC_BASE_ADDRESS 0x00020000 + +#endif /* _APB_MAP_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6000_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6000_api.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6000_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6000_api.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,46 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the API to access the OS dependent atheros host driver +// by the WMI or WLAN generic modules. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _AR6000_API_H_ +#define _AR6000_API_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "ar6xapi_linux.h" +#endif + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/ar6xapi_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/ar6xapi_wince.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/ar6xapi_rexos.h" +#endif + +#endif /* _AR6000_API_H */ + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6000_diag.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6000_diag.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6000_diag.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6000_diag.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,42 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef AR6000_DIAG_H_ +#define AR6000_DIAG_H_ + + +A_STATUS +ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS +ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS +ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length); + +A_STATUS +ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length); + +#endif /*AR6000_DIAG_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6000_drv.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6000_drv.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6000_drv.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6000_drv.c 2010-09-02 21:21:01.000000000 -0400 @@ -0,0 +1,4917 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +/* + * This driver is a pseudo ethernet driver to access the Atheros AR6000 + * WLAN Device + */ +static const char athId[] __attribute__ ((unused)) = "$Id: //depot/sw/releases/olca2.2.0/host/os/linux/ar6000_drv.c#1 $"; + +/* ATHENV */ +#include +/* ATHENV */ + +#include "ar6000_drv.h" +#include "htc.h" +#include "engine.h" +#include "wmi_filter_linux.h" + +#define IS_MAC_NULL(mac) (mac[0]==0 && mac[1]==0 && mac[2]==0 && mac[3]==0 && mac[4]==0 && mac[5]==0) + +MODULE_LICENSE("GPL and additional rights"); + +#ifndef REORG_APTC_HEURISTICS +#undef ADAPTIVE_POWER_THROUGHPUT_CONTROL +#endif /* REORG_APTC_HEURISTICS */ + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +#define APTC_TRAFFIC_SAMPLING_INTERVAL 100 /* msec */ +#define APTC_UPPER_THROUGHPUT_THRESHOLD 3000 /* Kbps */ +#define APTC_LOWER_THROUGHPUT_THRESHOLD 2000 /* Kbps */ + +typedef struct aptc_traffic_record { + A_BOOL timerScheduled; + struct timeval samplingTS; + unsigned long bytesReceived; + unsigned long bytesTransmitted; +} APTC_TRAFFIC_RECORD; + +A_TIMER aptcTimer; +APTC_TRAFFIC_RECORD aptcTR; +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +AR_SOFTC_T *gAr; + +unsigned int processDot11Hdr = 0; +/* ATHENV */ +#ifdef ANDROID_ENV +int bmienable = 1; +#else +int bmienable = 0; +#endif +/* ATHENV */ + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +char ifname[IFNAMSIZ] = {0,}; +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) */ + +int fwloadenable = 0; +unsigned int bypasswmi = 0; +unsigned int debuglevel = 0; +int tspecCompliance = ATHEROS_COMPLIANCE; +unsigned int busspeedlow = 0; +unsigned int onebitmode = 0; +unsigned int skipflash = 0; +unsigned int wmitimeout = 2; +unsigned int wlanNodeCaching = 1; +unsigned int enableuartprint = 0; +unsigned int logWmiRawMsgs = 0; +unsigned int enabletimerwar = 0; +unsigned int fwmode = 1; +unsigned int mbox_yield_limit = 99; +int reduce_credit_dribble = 1 + HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF; +int allow_trace_signal = 0; +/* ATHENV */ +#ifdef ANDROID_ENV +int work_mode = 0; +char *tgt_fw = "/system/wifi/athwlan.bin.z77"; +char *tgt_patch = "/system/wifi/data.patch.hw2_0.bin"; +char *tcmd_fw = "/system/wifi/athtcmd_ram.bin"; +static char *art_fw = "/system/wifi/device.bin"; +char *eeprom_bin = "/system/wifi/eeprom.bin"; +#ifdef FAKE_EEPROM_USED +char *eeprom_data = "/system/wifi/fakeBoardData_AR6002.bin"; +#else +char *eeprom_data = "/system/wifi/eeprom.data"; +#endif +#endif /* ANDROID_ENV */ +char *fm_path=NULL; +/* ATHENV */ +#ifdef CONFIG_HOST_TCMD_SUPPORT +unsigned int testmode =0; +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param_string(ifname, ifname, sizeof(ifname), 0644); +module_param(fwloadenable, int, 0644); +module_param(bmienable, int, 0644); +module_param(bypasswmi, int, 0644); +module_param(debuglevel, int, 0644); +module_param(tspecCompliance, int, 0644); +module_param(onebitmode, int, 0644); +module_param(busspeedlow, int, 0644); +module_param(skipflash, int, 0644); +module_param(wmitimeout, int, 0644); +module_param(wlanNodeCaching, int, 0644); +module_param(logWmiRawMsgs, int, 0644); +module_param(enableuartprint, int, 0644); +module_param(enabletimerwar, int, 0644); +module_param(fwmode, int, 0644); +module_param(mbox_yield_limit, int, 0644); +module_param(reduce_credit_dribble, int, 0644); +module_param(allow_trace_signal, int, 0644); +module_param(processDot11Hdr, int, 0644); +/* ATHENV */ +#ifdef ANDROID_ENV +module_param(work_mode, int, 0644); +module_param(tgt_fw, charp, S_IRUGO); +module_param(tgt_patch, charp, S_IRUGO); +module_param(eeprom_bin, charp, S_IRUGO); +module_param(eeprom_data, charp, S_IRUGO); +#endif +module_param(fm_path,charp,S_IRUGO); +/* ATHENV */ +#ifdef CONFIG_HOST_TCMD_SUPPORT +module_param(testmode, int, 0644); +#endif +#else + +#define __user +/* for linux 2.4 and lower */ +MODULE_PARM(bmienable,"i"); +MODULE_PARM(fwloadenable,"i"); +MODULE_PARM(bypasswmi,"i"); +MODULE_PARM(debuglevel, "i"); +MODULE_PARM(onebitmode,"i"); +MODULE_PARM(busspeedlow, "i"); +MODULE_PARM(skipflash, "i"); +MODULE_PARM(wmitimeout, "i"); +MODULE_PARM(wlanNodeCaching, "i"); +MODULE_PARM(enableuartprint,"i"); +MODULE_PARM(logWmiRawMsgs, "i"); +MODULE_PARM(enabletimerwar,"i"); +MODULE_PARM(fwmode,"i"); +MODULE_PARM(mbox_yield_limit,"i"); +MODULE_PARM(reduce_credit_dribble,"i"); +MODULE_PARM(allow_trace_signal,"i"); +MODULE_PARM(processDot11Hdr,"i"); +#ifdef CONFIG_HOST_TCMD_SUPPORT +MODULE_PARM(testmode, "i"); +#endif +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10) +/* in 2.6.10 and later this is now a pointer to a uint */ +unsigned int _mboxnum = HTC_MAILBOX_NUM_MAX; +#define mboxnum &_mboxnum +#else +unsigned int mboxnum = HTC_MAILBOX_NUM_MAX; +#endif + +#ifdef DEBUG +A_UINT32 g_dbg_flags = DBG_DEFAULTS; +unsigned int debugflags = 0; +int debugdriver = 1; +unsigned int debughtc = 128; +unsigned int debugbmi = 1; +unsigned int debughif = 2; +unsigned int txcreditsavailable[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int txcreditsconsumed[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int txcreditintrenable[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int txcreditintrenableaggregate[HTC_MAILBOX_NUM_MAX] = {0}; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param(debugflags, int, 0644); +module_param(debugdriver, int, 0644); +module_param(debughtc, int, 0644); +module_param(debugbmi, int, 0644); +module_param(debughif, int, 0644); +module_param_array(txcreditsavailable, int, mboxnum, 0644); +module_param_array(txcreditsconsumed, int, mboxnum, 0644); +module_param_array(txcreditintrenable, int, mboxnum, 0644); +module_param_array(txcreditintrenableaggregate, int, mboxnum, 0644); +#else +/* linux 2.4 and lower */ +MODULE_PARM(debugflags,"i"); +MODULE_PARM(debugdriver, "i"); +MODULE_PARM(debughtc, "i"); +MODULE_PARM(debugbmi, "i"); +MODULE_PARM(debughif, "i"); +MODULE_PARM(txcreditsavailable, "0-3i"); +MODULE_PARM(txcreditsconsumed, "0-3i"); +MODULE_PARM(txcreditintrenable, "0-3i"); +MODULE_PARM(txcreditintrenableaggregate, "0-3i"); +#endif + +#endif /* DEBUG */ + +unsigned int resetok = 1; +unsigned int tx_attempt[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int tx_post[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int tx_complete[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int hifBusRequestNumMax = 40; +unsigned int war23838_disabled = 0; +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +unsigned int enableAPTCHeuristics = 1; +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param_array(tx_attempt, int, mboxnum, 0644); +module_param_array(tx_post, int, mboxnum, 0644); +module_param_array(tx_complete, int, mboxnum, 0644); +module_param(hifBusRequestNumMax, int, 0644); +module_param(war23838_disabled, int, 0644); +module_param(resetok, int, 0644); +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +module_param(enableAPTCHeuristics, int, 0644); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ +#else +MODULE_PARM(tx_attempt, "0-3i"); +MODULE_PARM(tx_post, "0-3i"); +MODULE_PARM(tx_complete, "0-3i"); +MODULE_PARM(hifBusRequestNumMax, "i"); +MODULE_PARM(war23838_disabled, "i"); +MODULE_PARM(resetok, "i"); +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +MODULE_PARM(enableAPTCHeuristics, "i"); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ +#endif + +#ifdef BLOCK_TX_PATH_FLAG +int blocktx = 0; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param(blocktx, int, 0644); +#else +MODULE_PARM(blocktx, "i"); +#endif +#endif /* BLOCK_TX_PATH_FLAG */ + + +int reconnect_flag = 0; + +char tgt_fw_path[100]; +char tgt_patch_path[100]; +char eeprom_bin_path[100]; +char eeprom_data_path[100]; + +/* Function declarations */ +static int ar6000_init_module(void); +static void ar6000_cleanup_module(void); + +int ar6000_init(struct net_device *dev); +static int ar6000_open(struct net_device *dev); +static int ar6000_close(struct net_device *dev); +static void ar6000_init_control_info(AR_SOFTC_T *ar); +static int ar6000_data_tx(struct sk_buff *skb, struct net_device *dev); + +static void ar6000_destroy(struct net_device *dev, unsigned int unregister); +static void ar6000_detect_error(unsigned long ptr); +static struct net_device_stats *ar6000_get_stats(struct net_device *dev); +static struct iw_statistics *ar6000_get_iwstats(struct net_device * dev); + +static void disconnect_timer_handler(unsigned long ptr); + +/* + * HTC service connection handlers + */ +static A_STATUS ar6000_avail_ev(void *context, void *hif_handle); + +static A_STATUS ar6000_unavail_ev(void *context, void *hif_handle); + +static void ar6000_target_failure(void *Instance, A_STATUS Status); + +static void ar6000_rx(void *Context, HTC_PACKET *pPacket); + +static void ar6000_rx_refill(void *Context,HTC_ENDPOINT_ID Endpoint); + +static void ar6000_tx_complete(void *Context, HTC_PACKET *pPacket); + +static HTC_SEND_FULL_ACTION ar6000_tx_queue_full(void *Context, HTC_PACKET *pPacket); + +static void deliver_frames_to_nw_stack(struct sk_buff *skb); + +/* + * Static variables + */ + +static struct net_device *ar6000_devices[MAX_AR6000]; +extern struct iw_handler_def ath_iw_handler_def; +DECLARE_WAIT_QUEUE_HEAD(arEvent); +DECLARE_WAIT_QUEUE_HEAD(ar6000_scan_queue); +static void ar6000_cookie_init(AR_SOFTC_T *ar); +static void ar6000_cookie_cleanup(AR_SOFTC_T *ar); +static void ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie); +static struct ar_cookie *ar6000_alloc_cookie(AR_SOFTC_T *ar); + +#ifdef USER_KEYS +static A_STATUS ar6000_reinstall_keys(AR_SOFTC_T *ar,A_UINT8 key_op_ctrl); +#endif + + +static struct ar_cookie s_ar_cookie_mem[MAX_COOKIE_NUM]; + +#define HOST_INTEREST_ITEM_ADDRESS(ar, item) \ + (((ar)->arTargetType == TARGET_TYPE_AR6001) ? AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((ar)->arTargetType == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((ar)->arTargetType == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : 0))) + + +/* Debug log support */ + +/* + * Flag to govern whether the debug logs should be parsed in the kernel + * or reported to the application. + */ +#define REPORT_DEBUG_LOGS_TO_APP + +A_STATUS +ar6000_set_host_app_area(AR_SOFTC_T *ar) +{ + A_UINT32 address, data; + struct host_app_area_s host_app_area; + + /* Fetch the address of the host_app_area_s instance in the host interest area */ + address = TARG_VTOP(ar->arTargetType, HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest)); + if (ar6000_ReadRegDiag(ar->arHifDevice, &address, &data) != A_OK) { + return A_ERROR; + } + address = TARG_VTOP(ar->arTargetType, data); + host_app_area.wmi_protocol_ver = WMI_PROTOCOL_VERSION; + if (ar6000_WriteDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&host_app_area, + sizeof(struct host_app_area_s)) != A_OK) + { + return A_ERROR; + } + + return A_OK; +} + +A_UINT32 +dbglog_get_debug_hdr_ptr(AR_SOFTC_T *ar) +{ + A_UINT32 param; + A_UINT32 address; + A_STATUS status; + + address = TARG_VTOP(ar->arTargetType, HOST_INTEREST_ITEM_ADDRESS(ar, hi_dbglog_hdr)); + if ((status = ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)¶m, 4)) != A_OK) + { + param = 0; + } + + return param; +} + +/* + * The dbglog module has been initialized. Its ok to access the relevant + * data stuctures over the diagnostic window. + */ +void +ar6000_dbglog_init_done(AR_SOFTC_T *ar) +{ + ar->dbglog_init_done = TRUE; +} + +A_UINT32 +dbglog_get_debug_fragment(A_INT8 *datap, A_UINT32 len, A_UINT32 limit) +{ + A_INT32 *buffer; + A_UINT32 count; + A_UINT32 numargs; + A_UINT32 length; + A_UINT32 fraglen; + + count = fraglen = 0; + buffer = (A_INT32 *)datap; + length = (limit >> 2); + + if (len <= limit) { + fraglen = len; + } else { + while (count < length) { + numargs = DBGLOG_GET_NUMARGS(buffer[count]); + fraglen = (count << 2); + count += numargs + 1; + } + } + + return fraglen; +} + +void +dbglog_parse_debug_logs(A_INT8 *datap, A_UINT32 len) +{ + A_INT32 *buffer; + A_UINT32 count; + A_UINT32 timestamp; + A_UINT32 debugid; + A_UINT32 moduleid; + A_UINT32 numargs; + A_UINT32 length; + + count = 0; + buffer = (A_INT32 *)datap; + length = (len >> 2); + while (count < length) { + debugid = DBGLOG_GET_DBGID(buffer[count]); + moduleid = DBGLOG_GET_MODULEID(buffer[count]); + numargs = DBGLOG_GET_NUMARGS(buffer[count]); + timestamp = DBGLOG_GET_TIMESTAMP(buffer[count]); + switch (numargs) { + case 0: + AR_DEBUG_PRINTF("%d %d (%d)\n", moduleid, debugid, timestamp); + break; + + case 1: + AR_DEBUG_PRINTF("%d %d (%d): 0x%x\n", moduleid, debugid, + timestamp, buffer[count+1]); + break; + + case 2: + AR_DEBUG_PRINTF("%d %d (%d): 0x%x, 0x%x\n", moduleid, debugid, + timestamp, buffer[count+1], buffer[count+2]); + break; + + default: + AR_DEBUG_PRINTF("Invalid args: %d\n", numargs); + } + count += numargs + 1; + } +} + +int +ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar) +{ + struct dbglog_hdr_s debug_hdr; + struct dbglog_buf_s debug_buf; + A_UINT32 address; + A_UINT32 length; + A_UINT32 dropped; + A_UINT32 firstbuf; + A_UINT32 debug_hdr_ptr; + + if (!ar->dbglog_init_done) return A_ERROR; + + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + if (ar->dbgLogFetchInProgress) { + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + return A_EBUSY; + } + + /* block out others */ + ar->dbgLogFetchInProgress = TRUE; + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + debug_hdr_ptr = dbglog_get_debug_hdr_ptr(ar); + printk("debug_hdr_ptr: 0x%x\n", debug_hdr_ptr); + + /* Get the contents of the ring buffer */ + if (debug_hdr_ptr) { + address = TARG_VTOP(ar->arTargetType, debug_hdr_ptr); + length = sizeof(struct dbglog_hdr_s); + ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&debug_hdr, length); + address = TARG_VTOP(ar->arTargetType, (A_UINT32)debug_hdr.dbuf); + firstbuf = address; + dropped = debug_hdr.dropped; + length = sizeof(struct dbglog_buf_s); + ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&debug_buf, length); + + do { + address = TARG_VTOP(ar->arTargetType, (A_UINT32)debug_buf.buffer); + length = debug_buf.length; + if ((length) && (debug_buf.length <= debug_buf.bufsize)) { + /* Rewind the index if it is about to overrun the buffer */ + if (ar->log_cnt > (DBGLOG_HOST_LOG_BUFFER_SIZE - length)) { + ar->log_cnt = 0; + } + if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&ar->log_buffer[ar->log_cnt], length)) + { + break; + } + ar6000_dbglog_event(ar, dropped, &ar->log_buffer[ar->log_cnt], length); + ar->log_cnt += length; + } else { + AR_DEBUG_PRINTF("Length: %d (Total size: %d)\n", + debug_buf.length, debug_buf.bufsize); + } + + address = TARG_VTOP(ar->arTargetType, (A_UINT32)debug_buf.next); + length = sizeof(struct dbglog_buf_s); + if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&debug_buf, length)) + { + break; + } + + } while (address != firstbuf); + } + + ar->dbgLogFetchInProgress = FALSE; + + return A_OK; +} + +void +ar6000_dbglog_event(AR_SOFTC_T *ar, A_UINT32 dropped, + A_INT8 *buffer, A_UINT32 length) +{ +#ifdef REPORT_DEBUG_LOGS_TO_APP + #define MAX_WIRELESS_EVENT_SIZE 252 + /* + * Break it up into chunks of MAX_WIRELESS_EVENT_SIZE bytes of messages. + * There seems to be a limitation on the length of message that could be + * transmitted to the user app via this mechanism. + */ + A_UINT32 send, sent; + + if (!buffer) + return; + + sent = 0; + send = dbglog_get_debug_fragment(&buffer[sent], length - sent, + MAX_WIRELESS_EVENT_SIZE); + while (send) { + ar6000_send_event_to_app(ar, WMIX_DBGLOG_EVENTID, &buffer[sent], send); + sent += send; + send = dbglog_get_debug_fragment(&buffer[sent], length - sent, + MAX_WIRELESS_EVENT_SIZE); + } +#else + AR_DEBUG_PRINTF("Dropped logs: 0x%x\nDebug info length: %d\n", + dropped, length); + + if (!buffer) + return; + + /* Interpret the debug logs */ + dbglog_parse_debug_logs(buffer, length); +#endif /* REPORT_DEBUG_LOGS_TO_APP */ +} + +extern void sdhci_touch_mmc1_clk(int enable); + +/* PM code for MMC1 clock management */ +static void ar6000_enable_clock(int enable) +{ + sdhci_touch_mmc1_clk(enable); +} + +extern void sdhci_reset_sdio(void); +extern void gpio_wifi_power_enable(int enable); + +extern atomic_t sdio_removed; +extern void mxc_kernel_uptime(void); + +static int ar6000_probe(struct platform_device *pdev) +{ + static int probed = 0; + A_STATUS status; + OSDRV_CALLBACKS osdrvCallbacks; + + printk(KERN_INFO "%s: initializing!\n", __func__); + + ar6000_enable_clock(1); + mdelay(20); + + if (atomic_read(&sdio_removed)) { + /* Power up the chip */ + gpio_wifi_power_enable(1); + mdelay(20); + sdhci_reset_sdio(); + mdelay(20); + atomic_set(&sdio_removed, 0); + } + +/* ATHENV */ +#ifdef ANDROID_ENV + if (work_mode == 1) { + printk("TCMD mode.\n"); + testmode = 1; + tgt_fw = tcmd_fw; + } else if (work_mode == 2) { + printk("ART mode.\n"); + enableuartprint = 1; + resetok = 0; + bypasswmi = 1; + tgt_fw = art_fw; + }else { + if(fm_path) { + strcat(tgt_fw_path,fm_path); + tgt_fw=strcat(tgt_fw_path,"/target/AR6002/hw2.0/bin/athwlan.bin.z77"); + strcat(tgt_patch_path,fm_path); + tgt_patch=strcat(tgt_patch_path,"/target/AR6002/hw2.0/bin/data.patch.hw2_0.bin"); + strcat(eeprom_bin_path,fm_path); + eeprom_bin=strcat(eeprom_bin_path,"/target/AR6002/hw2.0/bin/eeprom.bin"); + strcat(eeprom_data_path,fm_path); + eeprom_data=strcat(eeprom_data_path,"/target/AR6002/hw2.0/bin/eeprom.data"); + }else{ + tgt_fw = NULL; /* Indicate Avail routine to load fw from bmi loader */ + } + } +#endif +/* ATHENV */ + + A_MEMZERO(&osdrvCallbacks,sizeof(osdrvCallbacks)); + osdrvCallbacks.deviceInsertedHandler = ar6000_avail_ev; + osdrvCallbacks.deviceRemovedHandler = ar6000_unavail_ev; + +#ifdef DEBUG + /* Set the debug flags if specified at load time */ + if(debugflags != 0) + { + g_dbg_flags = debugflags; + } +#endif + + if (probed) { + return -ENODEV; + } + probed++; + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + memset(&aptcTR, 0, sizeof(APTC_TRAFFIC_RECORD)); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +#ifdef CONFIG_HOST_GPIO_SUPPORT + ar6000_gpio_init(); +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + + status = HIFInit(&osdrvCallbacks); + if(status != A_OK) + return -ENODEV; + + printk(KERN_INFO "kernel: I perf:wifi:wifi_driver_loaded="); + mxc_kernel_uptime(); + + return 0; +} + +static int ar6000_remove(struct platform_device *pdev) +{ +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + /* Delete the Adaptive Power Control timer */ + if (timer_pending(&aptcTimer)) { + del_timer_sync(&aptcTimer); + } +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + + AR_DEBUG_PRINTF("ar6000_cleanup: success\n"); + + ar6000_enable_clock(0); + + /* Power down the chip */ + gpio_wifi_power_enable(0); + + atomic_set(&sdio_removed, 1); + return 0; +} + +#ifdef CONFIG_PM + +static A_STATUS +ar6000_configure_target(AR_SOFTC_T *ar) +{ + A_UINT32 param; + BMIInit(); + { + struct bmi_target_info targ_info; + + if (BMIGetTargetInfo(ar->arHifDevice, &targ_info) != A_OK) { + return A_ERROR; + } + + ar->arVersion.target_ver = targ_info.target_ver; + ar->arTargetType = targ_info.target_type; + + /* do any target-specific preparation that can be done through BMI */ + if (ar6000_prepare_target(ar->arHifDevice, + targ_info.target_type, + targ_info.target_ver) != A_OK) { + return A_ERROR; + } + + } + + if (enableuartprint) { + param = 1; + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_serial_enable), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for enableuartprint failed \n"); + return A_ERROR; + } + AR_DEBUG_PRINTF("Serial console prints enabled\n"); + } + + /* Tell target which HTC version it is used*/ + param = HTC_PROTOCOL_VERSION; + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for htc version failed \n"); + return A_ERROR; + } +#ifdef CONFIG_HOST_TCMD_SUPPORT + if(testmode) { + ar->arTargetMode = AR6000_TCMD_MODE; + }else { + ar->arTargetMode = AR6000_WLAN_MODE; + } +#endif + if (enabletimerwar) { + A_UINT32 param; + + if (BMIReadMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIReadMemory for enabletimerwar failed \n"); + return A_ERROR; + } + + param |= HI_OPTION_TIMER_WAR; + + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for enabletimerwar failed \n"); + return A_ERROR; + } + AR_DEBUG_PRINTF("Timer WAR enabled\n"); + } + + /* set the firmware mode to STA/IBSS/AP */ + { + A_UINT32 param; + + if (BMIReadMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIReadMemory for setting fwmode failed \n"); + return A_ERROR; + } + + param |= (fwmode << HI_OPTION_FW_MODE_SHIFT); + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for setting fwmode failed \n"); + return A_ERROR; + } + AR_DEBUG_PRINTF("Firmware mode set\n"); + } + + if (processDot11Hdr) { + A_UINT32 param; + + if (BMIReadMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIReadMemory for processDot11Hdr failed \n"); + return A_ERROR; + } + + param |= HI_OPTION_RELAY_DOT11_HDR; + + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for processDot11Hdr failed \n"); + return A_ERROR; + } + AR_DEBUG_PRINTF("processDot11Hdr enabled\n"); + } + + + /* No need to reserve RAM space for patch as olca/dragon is flash based */ + if (ar->arTargetType == TARGET_TYPE_AR6001) { + param = 0; + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_end_RAM_reserve_sz), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for hi_end_RAM_reserve_sz failed \n"); + return A_ERROR; + } + } + + + /* since BMIInit is called in the driver layer, we have to set the block + * size here for the target */ + + if (A_FAILED(ar6000_set_htc_params(ar->arHifDevice, + ar->arTargetType, + mbox_yield_limit, + 0 /* use default number of control buffers */ + ))) { + return A_ERROR; + } + return A_OK; +} + +static void +ar6000_restart_endpoint(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T*)netdev_priv(dev); + BMIInit(); + do { + if (ar6000_configure_target(ar)!=A_OK) + break; + ar->arWlanState = WLAN_ENABLED; + return; + } while (0); + + ar6000_devices[ar->arDeviceIndex] = NULL; + ar6000_destroy(ar->arNetDev, 1); +} + +static void +ar6000_stop_endpoint(struct net_device *dev, A_BOOL keepprofile) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T*)netdev_priv(dev); + /* Stop the transmit queues */ + netif_stop_queue(dev); + + if (ar->arWmiReady == TRUE) + { + if (!bypasswmi) + { + if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) + { + if (keepprofile) { + wmi_disconnect_cmd(ar->arWmi); + } else { + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar6000_init_profile_info(ar); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + wmi_disconnect_cmd(ar->arWmi); + } + } + + A_UNTIMEOUT(&ar->disconnect_timer); + ar->arWmiReady = FALSE; + ar->arConnected = FALSE; + ar->arConnectPending = FALSE; + wmi_shutdown(ar->arWmi); + ar->arWmiEnabled = FALSE; + ar->arWmi = NULL; + ar->arWlanState = WLAN_DISABLED; +#ifdef USER_KEYS + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT; + ar->user_key_ctrl = 0; +#endif + } + + AR_DEBUG_PRINTF("%s(): WMI stopped\n", __func__); + } + else + { + AR_DEBUG_PRINTF("%s(): WMI not ready 0x%08x 0x%08x\n", + __func__, (unsigned int) ar, (unsigned int) ar->arWmi); + + /* Shut down WMI if we have started it */ + if(ar->arWmiEnabled == TRUE) + { + AR_DEBUG_PRINTF("%s(): Shut down WMI\n", __func__); + wmi_shutdown(ar->arWmi); + ar->arWmiEnabled = FALSE; + ar->arWmi = NULL; + } + } + + if (ar->arHtcTarget != NULL) { + AR_DEBUG_PRINTF(" Shuting down HTC .... \n"); + /* stop HTC */ + HTCStop(ar->arHtcTarget); + } + + if (resetok) { + /* try to reset the device if we can + * The driver may have been configure NOT to reset the target during + * a debug session */ + AR_DEBUG_PRINTF(" Attempting to reset target on instance destroy.... \n"); + if (ar->arHifDevice != NULL) { + A_STATUS status; + if (0 /* cutoffenable */) { + /* platform going to cut the power. Don't wait for completion */ + status = ar6000_reset_device(ar->arHifDevice, ar->arTargetType, FALSE); + } else { + status = ar6000_reset_device(ar->arHifDevice, ar->arTargetType, TRUE); + } + printk("Reset target ret %d\n", status); + } + } else { + AR_DEBUG_PRINTF(" Host does not want target reset. \n"); + } + ar6000_cookie_cleanup(ar); +} + +static int ar6000_suspend(struct platform_device *pdev, pm_message_t state) +{ + printk(KERN_ERR "ar6000_suspend: This should never be called!\n"); + return -EBUSY; + + ar6000_stop_endpoint(gAr->arNetDev, FALSE); + return 0; +} + +static int ar6000_resume(struct platform_device *pdev) +{ + ar6000_restart_endpoint(gAr->arNetDev); + return 0; +} + +#else /* CONFIG_PM */ + +#define ar6000_suspend NULL +#define ar6000_resume NULL + +#endif /* CONFIG_PM */ + +static struct platform_driver ar6000_pdev_driver = { + .driver = { + .name = DRIVER_NAME, + }, + .probe = ar6000_probe, + .remove = ar6000_remove, + .suspend = ar6000_suspend, + .resume = ar6000_resume, +}; + +static void ar6000_nop_release(struct device *dev) +{ + /* Do Nothing */ +} + +static struct platform_device ar6000_dummy_device = { + .name = DRIVER_NAME, + .id = 0, + .dev = { + .release = ar6000_nop_release, + }, +}; + +static int __init ar6000_init_module(void) +{ + printk(KERN_INFO DRIVER_NAME + ": Shasta Atheros Ar6000 WiFi Driver\n"); + (void)platform_device_register(&ar6000_dummy_device); + return platform_driver_register(&ar6000_pdev_driver); +} + +static void __exit ar6000_cleanup_module(void) +{ + int i = 0; + struct net_device *ar6000_netdev; + + printk(KERN_INFO "ar6000_cleanup_module\n"); + + for (i=0; i < MAX_AR6000; i++) { + if (ar6000_devices[i] != NULL) { + ar6000_netdev = ar6000_devices[i]; + ar6000_devices[i] = NULL; + ar6000_destroy(ar6000_netdev, 1); + } + } + + printk(KERN_INFO "ar6000_destroy\n"); + + HIFShutDownDevice(NULL); + + printk(KERN_INFO "HIFShutDownDevice\n"); + + platform_driver_unregister(&ar6000_pdev_driver); + (void)platform_device_unregister(&ar6000_dummy_device); +} + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +void +aptcTimerHandler(unsigned long arg) +{ + A_UINT32 numbytes; + A_UINT32 throughput; + AR_SOFTC_T *ar; + A_STATUS status; + + ar = (AR_SOFTC_T *)arg; + A_ASSERT(ar != NULL); + A_ASSERT(!timer_pending(&aptcTimer)); + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + /* Get the number of bytes transferred */ + numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived; + aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0; + + /* Calculate and decide based on throughput thresholds */ + throughput = ((numbytes * 8)/APTC_TRAFFIC_SAMPLING_INTERVAL); /* Kbps */ + if (throughput < APTC_LOWER_THROUGHPUT_THRESHOLD) { + /* Enable Sleep and delete the timer */ + A_ASSERT(ar->arWmiReady == TRUE); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + status = wmi_powermode_cmd(ar->arWmi, REC_POWER); + AR6000_SPIN_LOCK(&ar->arLock, 0); + A_ASSERT(status == A_OK); + aptcTR.timerScheduled = FALSE; + } else { + A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0); + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); +} +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +/* ATHENV */ + +/* ATHENV */ +#ifdef ANDROID_ENV +extern void eeprom_ar6000_transfer(HIF_DEVICE *device, char *fake_file); +#endif +/* ATHENV */ + +#define MAX_BUF (8*1024) +/* #define A_ROUND_UP(x, y) ((((x)+((y)-1))/(y))*(y)) */ /* already defined in wmi_api.h */ + +/* ATHENV */ +#ifdef ANDROID_ENV +char * fw_buf; +static void firmware_transfer(HIF_DEVICE *device, char* filename, A_UINT32 address, A_BOOL isCompressed) +{ + struct file *filp; + struct inode *inode = NULL; + int length, remaining; + int length1; + A_STATUS ret; + mm_segment_t oldfs; + + + printk("%s: Enter, filename=%s\n", __FUNCTION__, filename); + + // Open file + oldfs = get_fs(); + set_fs(KERNEL_DS); + + filp = filp_open(filename, O_RDONLY, S_IRUSR); + if ( IS_ERR(filp) ) { + printk("%s: file %s filp_open error\n", __FUNCTION__, filename); + return; + } + if (!filp->f_op) { + printk("%s: File Operation Method Error\n", __FUNCTION__); + return; + } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + inode = filp->f_path.dentry->d_inode; +#else + inode = filp->f_dentry->d_inode; +#endif + + if (!inode) { + printk("%s: Get inode from filp failed\n", __FUNCTION__); + filp_close(filp, NULL); + return; + } + + printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos); + + fw_buf = (char*)kmalloc((MAX_BUF+12), GFP_KERNEL); + if (fw_buf==NULL) { + printk("%s: kernel memory alloc error\n", __FUNCTION__); + filp_close(filp, NULL); + return; + } + + length = i_size_read(inode->i_mapping->host); + if (length==0 ) { + printk("%s: Try to get file size error\n", __FUNCTION__); + goto Transfer_DONE; + } + printk("%s: length=%d, address=0x%x\n", __FUNCTION__, length, address); + + if ( isCompressed) { + ret = BMILZStreamStart(device, address); + if (ret != A_OK) { + printk("%s: BMILZStreamStart failed, ret=%d\n", __FUNCTION__, ret); + goto Transfer_DONE; + } + } + + remaining = length; + + while (remaining>0) { + length = (remaining > MAX_BUF)? MAX_BUF : remaining; + + if ( isCompressed ) { + ((A_UINT32 *)fw_buf)[((length-1)/4)] = 0; + } + + if (filp->f_op->read(filp, fw_buf, length, &filp->f_pos) != length) { + printk("%s: file read error, remaining=%d\n", __FUNCTION__, remaining); + goto Transfer_DONE; + } + + length1 = A_ROUND_UP(length, 4); + + if ( isCompressed ) { + printk("%s: BMILZData: len=%d, org_len=%d\n", __FUNCTION__, length1, length); + ret = BMILZData(device, fw_buf, length1); + if (ret != A_OK) { + printk("%s: BMILZData failed, ret=%d\n", __FUNCTION__, ret); + goto Transfer_DONE; + } + } else { + ret = BMIWriteMemory(device, address, fw_buf, length1); + if (ret != A_OK) { + printk("%s: BMIWriteMemory failed, ret=%d\n", __FUNCTION__, ret); + goto Transfer_DONE; + } + } + + remaining -= length; + address += length; + } + +Transfer_DONE: + kfree(fw_buf); + filp_close(filp, NULL); + set_fs(oldfs); +} + +#endif +/* ATHENV */ + + +#ifdef FW_AUTOLOAD +extern int fwengine( unsigned char *img, int size, void *ar); +extern int ar6k_reg_preload( int reg, unsigned int value ); + +/* Linux driver dependent utilities for fwengine */ +int load_binary( unsigned int addr, unsigned char *cp, void *arg ) +{ + int size = 0; + int adv = 5; + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + + cp++; + size |= ( *cp & 0xFF ); cp++; + size |= ( *cp & 0xFF ) << 8; cp++; + size |= ( *cp & 0xFF ) << 16; cp++; + size |= ( *cp & 0xFF ) << 24; cp++; + + if (BMIWriteMemory(ar->arHifDevice, addr, cp, size) != A_OK) + return(-1); + + adv += size; + return(adv); +} + +int execute_on_target( unsigned int address, unsigned int parm, void *arg ) +{ + int ret ; + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + ret = BMIExecute(ar->arHifDevice, address, &parm); + + return(ret); +} + +unsigned int get_target_reg( unsigned address, void *arg ) +{ + int ret ; + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + if (BMIReadMemory(ar->arHifDevice, address, (A_UCHAR *)&ret, 4)!= A_OK) { + /* And what am I supposed to do? */; + return( -1 ); + } + return( ret ); + +} + +int write_target_reg( unsigned address, unsigned value, void *arg ) +{ + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + if (BMIWriteMemory(ar->arHifDevice, address, (A_UCHAR *)&value, 4) != A_OK) + return(-1); + return(0); +} + +void bmidone( void *arg ) +{ + AR_SOFTC_T *ar; + + ar = (AR_SOFTC_T *)arg; + BMIDone(ar->arHifDevice); +} +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) +static struct device ar6kfwdev = { + .bus_id = "sdio0", +}; +#endif +#endif /* FW_AUTOLOAD */ + +#ifdef HTC_RAW_INTERFACE +static void free_raw_buffers(AR_SOFTC_T *ar) +{ + int i, j; + + for (i = 0; i != HTC_RAW_STREAM_NUM_MAX; i++) { + for (j = 0; j != RAW_HTC_READ_BUFFERS_NUM; j++) + kfree(ar->raw_htc_read_buffer[i][j]); + for (j = 0; j != RAW_HTC_WRITE_BUFFERS_NUM; j++) + kfree(ar->raw_htc_write_buffer[i][j]); + } +} + +static int alloc_raw_buffers(AR_SOFTC_T *ar) +{ + int i, j; + raw_htc_buffer *b; + + for (i = 0; i != HTC_RAW_STREAM_NUM_MAX; i++) { + for (j = 0; j != RAW_HTC_READ_BUFFERS_NUM; j++) { + b = kzalloc(sizeof(*b), GFP_KERNEL); + if (!b) + return -ENOMEM; + ar->raw_htc_read_buffer[i][j] = b; + } + for (j = 0; j != RAW_HTC_WRITE_BUFFERS_NUM; j++) { + b = kzalloc(sizeof(*b), GFP_KERNEL); + if (!b) + return -ENOMEM; + ar->raw_htc_write_buffer[i][j] = b; + } + } + return 0; +} +#endif + +/* + * HTC Event handlers + */ +static A_STATUS +ar6000_avail_ev(void *context, void *hif_handle) +{ + int i; + struct net_device *dev; + void *ar_netif; + AR_SOFTC_T *ar; + int device_index = 0; + A_UINT32 param; + HTC_INIT_INFO htcInfo; + + AR_DEBUG_PRINTF("ar6000_available\n"); + + for (i=0; i < MAX_AR6000; i++) { + if (ar6000_devices[i] == NULL) { + break; + } + } + + if (i == MAX_AR6000) { + AR_DEBUG_PRINTF("ar6000_available: max devices reached\n"); + return A_ERROR; + } + + /* Save this. It gives a bit better readability especially since */ + /* we use another local "i" variable below. */ + device_index = i; + +#ifdef CONFIG_MACH_LUIGI_LAB126 + dev = alloc_etherdev_ar6000(sizeof(AR_SOFTC_T)); +#else + dev = alloc_etherdev_(sizeof(AR_SOFTC_T)); +#endif + + if (dev == NULL) { + AR_DEBUG_PRINTF("ar6000_available: can't alloc etherdev\n"); + return A_ERROR; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + if (ifname[0]) + { + strcpy(dev->name, ifname); + } +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) */ + +#ifdef SET_MODULE_OWNER + SET_MODULE_OWNER(dev); +#endif + ether_setup(dev); + + ar_netif = netdev_priv(dev); + if (ar_netif == NULL) { + printk(KERN_CRIT "ar6000_available: Could not allocate memory\n"); + return A_ERROR; + } + + A_MEMZERO(ar_netif, sizeof(AR_SOFTC_T)); + + ar = (AR_SOFTC_T *)ar_netif; + gAr = ar; + ar->arNetDev = dev; + ar->arHifDevice = hif_handle; + ar->arWlanState = WLAN_ENABLED; + ar->arDeviceIndex = device_index; + + A_INIT_TIMER(&ar->arHBChallengeResp.timer, ar6000_detect_error, dev); + ar->arHBChallengeResp.seqNum = 0; + ar->arHBChallengeResp.outstanding = FALSE; + ar->arHBChallengeResp.missCnt = 0; + ar->arHBChallengeResp.frequency = AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT; + ar->arHBChallengeResp.missThres = AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT; + + ar6000_init_control_info(ar); + init_waitqueue_head(&arEvent); + sema_init(&ar->arSem, 1); +#ifdef HTC_RAW_INTERFACE + if (alloc_raw_buffers(ar)) { + free_raw_buffers(ar); + /* + * Clean up our own mess, but for anything else, cheerfully mimick + * the beautiful error non-handling of the rest of this function. + */ + return A_ERROR; + } +#endif + + ar->bIsDestroyProgress = FALSE; + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + A_INIT_TIMER(&aptcTimer, aptcTimerHandler, ar); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + + A_INIT_TIMER(&ar->disconnect_timer, disconnect_timer_handler, dev); + + /* + * If requested, perform some magic which requires no cooperation from + * the Target. It causes the Target to ignore flash and execute to the + * OS from ROM. + * + * This is intended to support recovery from a corrupted flash on Targets + * that support flash. + */ + if (skipflash) + { + AR_DEBUG_PRINTF("Skip flash feature not supported\n"); + return A_ERROR; + } + + BMIInit(); + { + struct bmi_target_info targ_info; + + if (BMIGetTargetInfo(ar->arHifDevice, &targ_info) != A_OK) { + return A_ERROR; + } + + ar->arVersion.target_ver = targ_info.target_ver; + ar->arTargetType = targ_info.target_type; + + /* do any target-specific preparation that can be done through BMI */ + if (ar6000_prepare_target(ar->arHifDevice, + targ_info.target_type, + targ_info.target_ver) != A_OK) { + return A_ERROR; + } + + } + + if (enableuartprint) { + param = 1; + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_serial_enable), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for enableuartprint failed \n"); + return A_ERROR; + } + AR_DEBUG_PRINTF("Serial console prints enabled\n"); + } + + /* Tell target which HTC version it is used*/ + param = HTC_PROTOCOL_VERSION; + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for htc version failed \n"); + return A_ERROR; + } + +#ifdef CONFIG_HOST_TCMD_SUPPORT + if(testmode) { + ar->arTargetMode = AR6000_TCMD_MODE; + }else { + ar->arTargetMode = AR6000_WLAN_MODE; + } +#endif + if (enabletimerwar) { + A_UINT32 param; + + if (BMIReadMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIReadMemory for enabletimerwar failed \n"); + return A_ERROR; + } + + param |= HI_OPTION_TIMER_WAR; + + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for enabletimerwar failed \n"); + return A_ERROR; + } + AR_DEBUG_PRINTF("Timer WAR enabled\n"); + } + + /* set the firmware mode to STA/IBSS/AP */ + { + A_UINT32 param; + + if (BMIReadMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIReadMemory for setting fwmode failed \n"); + return A_ERROR; + } + + param |= (fwmode << HI_OPTION_FW_MODE_SHIFT); + + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for setting fwmode failed \n"); + return A_ERROR; + } + AR_DEBUG_PRINTF("Firmware mode set\n"); + } + + if (processDot11Hdr) { + A_UINT32 param; + + if (BMIReadMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF("BMIReadMemory for processDot11Hdr failed \n"); + return A_ERROR; + } + + param |= HI_OPTION_RELAY_DOT11_HDR; + + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for processDot11Hdr failed \n"); + return A_ERROR; + } + AR_DEBUG_PRINTF("processDot11Hdr enabled\n"); + } + + + // No need to reserve RAM space for patch as olca/dragon is flash based + if (ar->arTargetType == TARGET_TYPE_AR6001) { + param = 0; + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_end_RAM_reserve_sz), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF("BMIWriteMemory for hi_end_RAM_reserve_sz failed \n"); + return A_ERROR; + } + } + + + /* since BMIInit is called in the driver layer, we have to set the block + * size here for the target */ + + if (A_FAILED(ar6000_set_htc_params(ar->arHifDevice, + ar->arTargetType, + mbox_yield_limit, + 0 /* use default number of control buffers */ + ))) { + return A_ERROR; + } + + A_MEMZERO(&htcInfo,sizeof(htcInfo)); + htcInfo.pContext = ar; + htcInfo.TargetFailure = ar6000_target_failure; + + ar->arHtcTarget = HTCCreate(ar->arHifDevice,&htcInfo); + + if (ar->arHtcTarget == NULL) { + return A_ERROR; + } + + spin_lock_init(&ar->arLock); + + /* Don't install the init function if BMI is requested */ + if(!bmienable) + { + dev->init = ar6000_init; + } else { + AR_DEBUG_PRINTF(" BMI enabled \n"); + } + + dev->open = &ar6000_open; + dev->stop = &ar6000_close; + dev->hard_start_xmit = &ar6000_data_tx; + dev->get_stats = &ar6000_get_stats; + + /* dev->tx_timeout = ar6000_tx_timeout; */ + dev->do_ioctl = &ar6000_ioctl; + dev->watchdog_timeo = AR6000_TX_TIMEOUT; + dev->wireless_handlers = &ath_iw_handler_def; + dev->features = NETIF_F_LLTX; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) + dev->get_wireless_stats = ar6000_get_iwstats; /*Displayed via proc fs */ +#else + ath_iw_handler_def.get_wireless_stats = ar6000_get_iwstats; /*Displayed via proc fs */ +#endif + + if (processDot11Hdr) { + dev->hard_header_len = sizeof(struct ieee80211_qosframe) + sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN; + } else { + /* + * We need the OS to provide us with more headroom in order to + * perform dix to 802.3, WMI header encap, and the HTC header + */ + dev->hard_header_len = ETH_HLEN + sizeof(ATH_LLC_SNAP_HDR) + + sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN; + } + + /* This runs the init function */ + if (register_netdev(dev)) { + AR_DEBUG_PRINTF("ar6000_avail: register_netdev failed\n"); + ar6000_destroy(dev, 0); + return A_ERROR; + } + + HIFClaimDevice(ar->arHifDevice, ar); + + /* We only register the device in the global list if we succeed. */ + /* If the device is in the global list, it will be destroyed */ + /* when the module is unloaded. */ + ar6000_devices[device_index] = dev; + + AR_DEBUG_PRINTF("ar6000_avail: name=%s hifdevice=0x%x, dev=0x%x (%d), ar=0x%x\n", + dev->name, (A_UINT32)ar->arHifDevice, (A_UINT32)dev, device_index, + (A_UINT32)ar); +/* ATHENV */ +#ifdef ANDROID_ENV + if (tgt_fw != NULL) { + A_UINT32 value, old_options, old_sleep; + A_STATUS ret; + + /* temporarily disable system sleep */ + value = 0; + BMIReadSOCRegister(ar->arHifDevice, 0x180c0, &value); + old_options = value; + value |= 0x08; + BMIWriteSOCRegister(ar->arHifDevice, 0x180c0, value); + value = 0; + BMIReadSOCRegister(ar->arHifDevice, 0x40c4, &value); + old_sleep = value; + value |= 0x01; + BMIWriteSOCRegister(ar->arHifDevice, 0x40c4, value); + printk("old options [%d] old sleep [%d]\n", old_options, old_sleep); + + /* run at 40/44MHz by default */ + value = 0; + BMIWriteSOCRegister(ar->arHifDevice, 0x4020, value); + + /* use internal clock? */ + BMIReadSOCRegister(ar->arHifDevice, 0x50047c, &value); + if (value == 0) { + printk("use internal clock\n"); + value = 0x100000; + BMIWriteSOCRegister(ar->arHifDevice, 0x40e0, value); + } + + /* eeprom */ +#ifdef FAKE_EEPROM_USED + printk("AR6000: download fake eeprom\n"); + eeprom_ar6000_transfer(ar->arHifDevice, eeprom_data, NULL); +#else + printk("AR6000: eeprom transfer\n"); + firmware_transfer(ar->arHifDevice, eeprom_data, 0x502070, FALSE); + firmware_transfer(ar->arHifDevice, eeprom_bin, 0x513950, FALSE); + value = 1; + printk("AR6000: BMIExecute\n"); + BMIExecute(ar->arHifDevice, 0x913950, &value); +#endif + printk("AR6000: BMISetAppStart\n"); + BMISetAppStart(ar->arHifDevice, 0x913950); + + /* enable HI_OPTION_TIMER_WAR */ + printk("AR6000: enable HI_OPTION_TIMER_WAR\n"); + value = 0; + BMIReadSOCRegister(ar->arHifDevice, 0x500410, &value); + value |= 0x01; + BMIWriteSOCRegister(ar->arHifDevice, 0x500410, value); + + /* fw */ + printk("AR6000: firmware_transfer\n"); + if ((tgt_fw[strlen(tgt_fw) - 3] == 'z') + && (tgt_fw[strlen(tgt_fw) - 2] == '7') + && (tgt_fw[strlen(tgt_fw) - 1] == '7')) { + firmware_transfer(ar->arHifDevice, tgt_fw, 0x502070, TRUE); + } else { + firmware_transfer(ar->arHifDevice, tgt_fw, 0x502070, FALSE); + } + + /* WLAN patch DataSets */ + firmware_transfer(ar->arHifDevice, tgt_patch, 0x52d6c8, FALSE); + BMIWriteSOCRegister(ar->arHifDevice, 0x500418, 0x52d6c8); + + /* restore system sleep */ + BMIWriteSOCRegister(ar->arHifDevice, 0x40c4, old_sleep); + BMIWriteSOCRegister(ar->arHifDevice, 0x180c0, old_options); + + if (work_mode == 2) { + /* art mode */ + BMIWriteSOCRegister(ar->arHifDevice, 0x500478, 26000000); + BMIWriteSOCRegister(ar->arHifDevice, 0x500458, 0x1); + } else { + /* normal WIFI or TCMD mode, done */ + ret = ar6000_init(dev); + if ( ret!= A_OK ) { + printk("%s: ar6000_init failed, ret=%d\n", __FUNCTION__, ret); + } + } + } +#endif +/* ATHENV */ + +#ifdef FW_AUTOLOAD + if( fwloadenable ) { + /* To compile firmware into driver the following struct should + * be declared static, it's field 'data' initialised with ptr to + * image and field 'size' with image size. 'request_firmware call + * in that case should be bypassed. TODO: #ifdef that + */ + const struct firmware *fw_entry; + int ret; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) + if(request_firmware(&fw_entry, "ar6k_firmware", &ar6kfwdev)!=0) { +#else + if(request_firmware(&fw_entry, "ar6k_firmware", &dev->dev)!=0) { +#endif +// if(request_firmware(NULL, "ar6k_firmware", &dev->dev)!=0) { + printk(KERN_ERR "ar6000_fwload: ar6k_firmware not available\n"); + ar6000_destroy(dev, 0); + return A_ERROR; + } else { + ar6k_reg_preload( 14, ar->arTargetType ); + ar6k_reg_preload( 15, ar->arVersion.target_ver ); + ret = fwengine(fw_entry->data, fw_entry->size, (void *)ar); + release_firmware(fw_entry); + if( ret ) { + printk(KERN_ERR "ar600_fwload: error loading firmware\n"); + ar6000_destroy(dev, 0); + return A_ERROR; + } + } + } +#endif /* FW_AUTOLOAD */ + + return A_OK; +} + +static void ar6000_target_failure(void *Instance, A_STATUS Status) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Instance; + WMI_TARGET_ERROR_REPORT_EVENT errEvent; + static A_BOOL sip = FALSE; + char buf[WMI_CONTROL_MSG_MAX_LEN]; + union iwreq_data wrqu; + + if (Status != A_OK) { + + printk(KERN_ERR "ar6000_target_failure: target asserted \n"); + + if (timer_pending(&ar->arHBChallengeResp.timer)) { + A_UNTIMEOUT(&ar->arHBChallengeResp.timer); + } + + /* try dumping target assertion information (if any) */ + ar6000_dump_target_assert_info(ar->arHifDevice,ar->arTargetType); + + /* + * Fetch the logs from the target via the diagnostic + * window. + */ + ar6000_dbglog_get_debug_logs(ar); + + /* Report the error only once */ + if (!sip) { + sip = TRUE; + errEvent.errorVal = WMI_TARGET_COM_ERR | + WMI_TARGET_FATAL_ERR; + + /* + * Send a generic event to supplicant. + */ + A_MEMZERO(buf, sizeof(buf)); + A_MEMZERO(&wrqu, sizeof(wrqu)); + sprintf(buf, "Driver Fatal Error= %d\n", errEvent.errorVal); + wrqu.data.length= strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + + /* + * This sends an AR600 specific event to the atheros debug app + */ + ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID, + (A_UINT8 *)&errEvent, + sizeof(WMI_TARGET_ERROR_REPORT_EVENT)); + } + } +} + +static A_STATUS +ar6000_unavail_ev(void *context, void *hif_handle) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)context; + /* NULL out it's entry in the global list */ + ar6000_devices[ar->arDeviceIndex] = NULL; + ar6000_destroy(ar->arNetDev, 1); + + return A_OK; +} + +/* + * We need to differentiate between the surprise and planned removal of the + * device because of the following consideration: + * - In case of surprise removal, the hcd already frees up the pending + * for the device and hence there is no need to unregister the function + * driver inorder to get these requests. For planned removal, the function + * driver has to explictly unregister itself to have the hcd return all the + * pending requests before the data structures for the devices are freed up. + * Note that as per the current implementation, the function driver will + * end up releasing all the devices since there is no API to selectively + * release a particular device. + * - Certain commands issued to the target can be skipped for surprise + * removal since they will anyway not go through. + */ +static void +ar6000_destroy(struct net_device *dev, unsigned int unregister) +{ + AR_SOFTC_T *ar; + + AR_DEBUG_PRINTF("+ar6000_destroy \n"); + + if((dev == NULL) || ((ar = netdev_priv(dev)) == NULL)) + { + AR_DEBUG_PRINTF("%s(): Failed to get device structure.\n", __func__); + return; + } + + ar->bIsDestroyProgress = TRUE; + + if (down_interruptible(&ar->arSem)) { + AR_DEBUG_PRINTF("%s(): down_interruptible failed \n", __func__); + return; + } + + /* Stop the transmit queues */ + netif_stop_queue(dev); + + /* Disable the target and the interrupts associated with it */ + if (ar->arWmiReady == TRUE) + { + if (!bypasswmi) + { + if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) + { + AR_DEBUG_PRINTF("%s(): Disconnect\n", __func__); + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar6000_init_profile_info(ar); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + wmi_disconnect_cmd(ar->arWmi); + } + + ar6000_dbglog_get_debug_logs(ar); + ar->arWmiReady = FALSE; + ar->arConnected = FALSE; + ar->arConnectPending = FALSE; + wmi_shutdown(ar->arWmi); + ar->arWmiEnabled = FALSE; + ar->arWmi = NULL; + ar->arWlanState = WLAN_ENABLED; +#ifdef USER_KEYS + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT; + ar->user_key_ctrl = 0; +#endif + } + + AR_DEBUG_PRINTF("%s(): WMI stopped\n", __func__); + } + else + { + AR_DEBUG_PRINTF("%s(): WMI not ready 0x%08x 0x%08x\n", + __func__, (unsigned int) ar, (unsigned int) ar->arWmi); + + /* Shut down WMI if we have started it */ + if(ar->arWmiEnabled == TRUE) + { + AR_DEBUG_PRINTF("%s(): Shut down WMI\n", __func__); + wmi_shutdown(ar->arWmi); + ar->arWmiEnabled = FALSE; + ar->arWmi = NULL; + } + } + + if (ar->arHtcTarget != NULL) { + AR_DEBUG_PRINTF(" Shuting down HTC .... \n"); + /* stop HTC */ + HTCStop(ar->arHtcTarget); + /* destroy HTC */ + HTCDestroy(ar->arHtcTarget); + } + + if (resetok) { + /* try to reset the device if we can + * The driver may have been configure NOT to reset the target during + * a debug session */ + AR_DEBUG_PRINTF(" Attempting to reset target on instance destroy.... \n"); + if (ar->arHifDevice != NULL) { + ar6000_reset_device(ar->arHifDevice, ar->arTargetType, TRUE); + } + } else { + AR_DEBUG_PRINTF(" Host does not want target reset. \n"); + } + + if (ar->arHifDevice != NULL) { + /*release the device so we do not get called back on remove incase we + * we're explicity destroyed by module unload */ + HIFReleaseDevice(ar->arHifDevice); + HIFShutDownDevice(ar->arHifDevice); + } + + /* Done with cookies */ + ar6000_cookie_cleanup(ar); + + /* Cleanup BMI */ + BMIInit(); + + /* Clear the tx counters */ + memset(tx_attempt, 0, sizeof(tx_attempt)); + memset(tx_post, 0, sizeof(tx_post)); + memset(tx_complete, 0, sizeof(tx_complete)); + + + /* Free up the device data structure */ + if( unregister ) + unregister_netdev(dev); + +#ifdef HTC_RAW_INTERFACE + free_raw_buffers(ar); +#endif + +#ifndef free_netdev + kfree(dev); +#else + free_netdev(dev); +#endif + + AR_DEBUG_PRINTF("-ar6000_destroy \n"); +} + +static void disconnect_timer_handler(unsigned long ptr) +{ + struct net_device *dev = (struct net_device *)ptr; + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + A_UNTIMEOUT(&ar->disconnect_timer); + + ar6000_init_profile_info(ar); + wmi_disconnect_cmd(ar->arWmi); +} + +static void ar6000_detect_error(unsigned long ptr) +{ + struct net_device *dev = (struct net_device *)ptr; + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_TARGET_ERROR_REPORT_EVENT errEvent; + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + if (ar->arHBChallengeResp.outstanding) { + ar->arHBChallengeResp.missCnt++; + } else { + ar->arHBChallengeResp.missCnt = 0; + } + + if (ar->arHBChallengeResp.missCnt > ar->arHBChallengeResp.missThres) { + /* Send Error Detect event to the application layer and do not reschedule the error detection module timer */ + ar->arHBChallengeResp.missCnt = 0; + ar->arHBChallengeResp.seqNum = 0; + errEvent.errorVal = WMI_TARGET_COM_ERR | WMI_TARGET_FATAL_ERR; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID, + (A_UINT8 *)&errEvent, + sizeof(WMI_TARGET_ERROR_REPORT_EVENT)); + return; + } + + /* Generate the sequence number for the next challenge */ + ar->arHBChallengeResp.seqNum++; + ar->arHBChallengeResp.outstanding = TRUE; + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + /* Send the challenge on the control channel */ + if (wmi_get_challenge_resp_cmd(ar->arWmi, ar->arHBChallengeResp.seqNum, DRV_HB_CHALLENGE) != A_OK) { + AR_DEBUG_PRINTF("Unable to send heart beat challenge\n"); + } + + + /* Reschedule the timer for the next challenge */ + A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0); +} + +void ar6000_init_profile_info(AR_SOFTC_T *ar) +{ + ar->arSsidLen = 0; + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + + switch(fwmode) { + case HI_OPTION_FW_MODE_IBSS: + ar->arNetworkType = ar->arNextMode = ADHOC_NETWORK; + break; + case HI_OPTION_FW_MODE_BSS_STA: + ar->arNetworkType = ar->arNextMode = INFRA_NETWORK; + break; + case HI_OPTION_FW_MODE_AP: + ar->arNetworkType = ar->arNextMode = AP_NETWORK; + break; + } + + ar->arDot11AuthMode = OPEN_AUTH; + ar->arAuthMode = NONE_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arPairwiseCryptoLen = 0; + ar->arGroupCrypto = NONE_CRYPT; + ar->arGroupCryptoLen = 0; + A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList)); + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + A_MEMZERO(ar->arBssid, sizeof(ar->arBssid)); + ar->arBssChannel = 0; +} + +static void +ar6000_init_control_info(AR_SOFTC_T *ar) +{ + ar->arWmiEnabled = FALSE; + ar6000_init_profile_info(ar); + ar->arDefTxKeyIndex = 0; + A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList)); + ar->arChannelHint = 0; + ar->arListenInterval = MAX_LISTEN_INTERVAL; + ar->arVersion.host_ver = AR6K_SW_VERSION; + ar->arRssi = 0; + ar->arTxPwr = 0; + ar->arTxPwrSet = FALSE; + ar->arSkipScan = 0; + ar->arBeaconInterval = 0; + ar->arBitRate = 0; + ar->arMaxRetries = 0; + ar->arWmmEnabled = TRUE; + ar->intra_bss = 1; + + /* Initialize the AP mode state info */ + { + A_UINT8 ctr; + A_MEMZERO((A_UINT8 *)ar->sta_list, AP_MAX_NUM_STA * sizeof(sta_t)); + + /* init the Mutexes */ + A_MUTEX_INIT(&ar->mcastpsqLock); + + /* Init the PS queues */ + for (ctr=0; ctr < AP_MAX_NUM_STA ; ctr++) { + A_MUTEX_INIT(&ar->sta_list[ctr].psqLock); + A_NETBUF_QUEUE_INIT(&ar->sta_list[ctr].psq); + } + + ar->ap_profile_flag = 0; + A_NETBUF_QUEUE_INIT(&ar->mcastpsq); + } +} + +static int +ar6000_open(struct net_device *dev) +{ + unsigned long flags; + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + spin_lock_irqsave(&ar->arLock, flags); + if( ar->arConnected || bypasswmi) { + netif_carrier_on(dev); + /* Wake up the queues */ + netif_wake_queue(dev); + } + else + netif_carrier_off(dev); + + spin_unlock_irqrestore(&ar->arLock, flags); + return 0; +} + +static int +ar6000_close(struct net_device *dev) +{ + netif_stop_queue(dev); + + return 0; +} + +/* connect to a service */ +static A_STATUS ar6000_connectservice(AR_SOFTC_T *ar, + HTC_SERVICE_CONNECT_REQ *pConnect, + char *pDesc) +{ + A_STATUS status; + HTC_SERVICE_CONNECT_RESP response; + + do { + + A_MEMZERO(&response,sizeof(response)); + + status = HTCConnectService(ar->arHtcTarget, + pConnect, + &response); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(" Failed to connect to %s service status:%d \n", + pDesc, status); + break; + } + switch (pConnect->ServiceID) { + case WMI_CONTROL_SVC : + if (ar->arWmiEnabled) { + /* set control endpoint for WMI use */ + wmi_set_control_ep(ar->arWmi, response.Endpoint); + } + /* save EP for fast lookup */ + ar->arControlEp = response.Endpoint; + break; + case WMI_DATA_BE_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_BE, response.Endpoint); + break; + case WMI_DATA_BK_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_BK, response.Endpoint); + break; + case WMI_DATA_VI_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_VI, response.Endpoint); + break; + case WMI_DATA_VO_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_VO, response.Endpoint); + break; + default: + AR_DEBUG_PRINTF("ServiceID not mapped %d\n", pConnect->ServiceID); + status = A_EINVAL; + break; + } + + } while (FALSE); + + return status; +} + +void ar6000_TxDataCleanup(AR_SOFTC_T *ar) +{ + /* flush all the data (non-control) streams + * we only flush packets that are tagged as data, we leave any control packets that + * were in the TX queues alone */ + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_BE), + AR6K_DATA_PKT_TAG); + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_BK), + AR6K_DATA_PKT_TAG); + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_VI), + AR6K_DATA_PKT_TAG); + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_VO), + AR6K_DATA_PKT_TAG); +} + +HTC_ENDPOINT_ID +ar6000_ac2_endpoint_id ( void * devt, A_UINT8 ac) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *) devt; + return(arAc2EndpointID(ar, ac)); +} + +A_UINT8 +ar6000_endpoint_id2_ac(void * devt, HTC_ENDPOINT_ID ep ) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *) devt; + return(arEndpoint2Ac(ar, ep )); +} + +/* This function does one time initialization for the lifetime of the device */ +int ar6000_init(struct net_device *dev) +{ + AR_SOFTC_T *ar; + A_STATUS status; + A_INT32 timeleft; + + if((ar = netdev_priv(dev)) == NULL) + { + return(-EIO); + } + + /* Do we need to finish the BMI phase */ + if(BMIDone(ar->arHifDevice) != A_OK) + { + return -EIO; + } + + if (!bypasswmi) + { +#if 0 /* TBDXXX */ + if (ar->arVersion.host_ver != ar->arVersion.target_ver) { + A_PRINTF("WARNING: Host version 0x%x does not match Target " + " version 0x%x!\n", + ar->arVersion.host_ver, ar->arVersion.target_ver); + } +#endif + + /* Indicate that WMI is enabled (although not ready yet) */ + ar->arWmiEnabled = TRUE; + if ((ar->arWmi = wmi_init((void *) ar)) == NULL) + { + AR_DEBUG_PRINTF("%s() Failed to initialize WMI.\n", __func__); + return(-EIO); + } + + AR_DEBUG_PRINTF("%s() Got WMI @ 0x%08x.\n", __func__, + (unsigned int) ar->arWmi); + } + + do { + HTC_SERVICE_CONNECT_REQ connect; + + /* the reason we have to wait for the target here is that the driver layer + * has to init BMI in order to set the host block size, + */ + status = HTCWaitTarget(ar->arHtcTarget); + + if (A_FAILED(status)) { + break; + } + + A_MEMZERO(&connect,sizeof(connect)); + /* meta data is unused for now */ + connect.pMetaData = NULL; + connect.MetaDataLength = 0; + /* these fields are the same for all service endpoints */ + connect.EpCallbacks.pContext = ar; + connect.EpCallbacks.EpTxComplete = ar6000_tx_complete; + connect.EpCallbacks.EpRecv = ar6000_rx; + connect.EpCallbacks.EpRecvRefill = ar6000_rx_refill; + connect.EpCallbacks.EpSendFull = ar6000_tx_queue_full; + /* set the max queue depth so that our ar6000_tx_queue_full handler gets called. + * Linux has the peculiarity of not providing flow control between the + * NIC and the network stack. There is no API to indicate that a TX packet + * was sent which could provide some back pressure to the network stack. + * Under linux you would have to wait till the network stack consumed all sk_buffs + * before any back-flow kicked in. Which isn't very friendly. + * So we have to manage this ourselves */ + connect.MaxSendQueueDepth = 32; + + /* connect to control service */ + connect.ServiceID = WMI_CONTROL_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI CONTROL"); + if (A_FAILED(status)) { + break; + } + + /* for the remaining data services set the connection flag to reduce dribbling, + * if configured to do so */ + if (reduce_credit_dribble) { + connect.ConnectionFlags |= HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE; + /* the credit dribble trigger threshold is (reduce_credit_dribble - 1) for a value + * of 0-3 */ + connect.ConnectionFlags &= ~HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK; + connect.ConnectionFlags |= + ((A_UINT16)reduce_credit_dribble - 1) & HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK; + } + /* connect to best-effort service */ + connect.ServiceID = WMI_DATA_BE_SVC; + + status = ar6000_connectservice(ar, + &connect, + "WMI DATA BE"); + if (A_FAILED(status)) { + break; + } + + /* connect to back-ground + * map this to WMI LOW_PRI */ + connect.ServiceID = WMI_DATA_BK_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI DATA BK"); + if (A_FAILED(status)) { + break; + } + + /* connect to Video service, map this to + * to HI PRI */ + connect.ServiceID = WMI_DATA_VI_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI DATA VI"); + if (A_FAILED(status)) { + break; + } + + /* connect to VO service, this is currently not + * mapped to a WMI priority stream due to historical reasons. + * WMI originally defined 3 priorities over 3 mailboxes + * We can change this when WMI is reworked so that priorities are not + * dependent on mailboxes */ + connect.ServiceID = WMI_DATA_VO_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI DATA VO"); + if (A_FAILED(status)) { + break; + } + + A_ASSERT(arAc2EndpointID(ar,WMM_AC_BE) != 0); + A_ASSERT(arAc2EndpointID(ar,WMM_AC_BK) != 0); + A_ASSERT(arAc2EndpointID(ar,WMM_AC_VI) != 0); + A_ASSERT(arAc2EndpointID(ar,WMM_AC_VO) != 0); + + /* setup access class priority mappings */ + ar->arAcStreamPriMap[WMM_AC_BK] = 0; /* lowest */ + ar->arAcStreamPriMap[WMM_AC_BE] = 1; /* */ + ar->arAcStreamPriMap[WMM_AC_VI] = 2; /* */ + ar->arAcStreamPriMap[WMM_AC_VO] = 3; /* highest */ + + } while (FALSE); + + if (A_FAILED(status)) { + return (-EIO); + } + + /* + * give our connected endpoints some buffers + */ + + ar6000_rx_refill(ar, ar->arControlEp); + ar6000_rx_refill(ar, arAc2EndpointID(ar,WMM_AC_BE)); + + /* + * We will post the receive buffers only for SPE or endpoint ping testing so we are + * making it conditional on the 'bypasswmi' flag. + */ + if (bypasswmi) { + ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_BK)); + ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_VI)); + ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_VO)); + } + + /* setup credit distribution */ + ar6000_setup_credit_dist(ar->arHtcTarget, &ar->arCreditStateInfo); + + /* Since cookies are used for HTC transports, they should be */ + /* initialized prior to enabling HTC. */ + ar6000_cookie_init(ar); + + /* start HTC */ + status = HTCStart(ar->arHtcTarget); + + if (status != A_OK) { + if (ar->arWmiEnabled == TRUE) { + wmi_shutdown(ar->arWmi); + ar->arWmiEnabled = FALSE; + ar->arWmi = NULL; + } + ar6000_cookie_cleanup(ar); + return -EIO; + } + + if (!bypasswmi) { + /* Wait for Wmi event to be ready */ + timeleft = wait_event_interruptible_timeout(arEvent, + (ar->arWmiReady == TRUE), wmitimeout * HZ); + + if(!timeleft || signal_pending(current)) + { + AR_DEBUG_PRINTF("WMI is not ready or wait was interrupted\n"); + return -EIO; + } + + AR_DEBUG_PRINTF("%s() WMI is ready\n", __func__); + + /* Communicate the wmi protocol verision to the target */ + if ((ar6000_set_host_app_area(ar)) != A_OK) { + AR_DEBUG_PRINTF("Unable to set the host app area\n"); + } + } + + ar->arNumDataEndPts = 1; + + if (bypasswmi) { + /* for tests like endpoint ping, the MAC address needs to be non-zero otherwise + * the data path through a raw socket is disabled */ + dev->dev_addr[0] = 0x00; + dev->dev_addr[1] = 0x01; + dev->dev_addr[2] = 0x02; + dev->dev_addr[3] = 0xAA; + dev->dev_addr[4] = 0xBB; + dev->dev_addr[5] = 0xCC; + } + + return(0); +} + + +void +ar6000_bitrate_rx(void *devt, A_INT32 rateKbps) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arBitRate = rateKbps; + wake_up(&arEvent); +} + +void +ar6000_ratemask_rx(void *devt, A_UINT16 ratemask) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arRateMask = ratemask; + wake_up(&arEvent); +} + +void +ar6000_txPwr_rx(void *devt, A_UINT8 txPwr) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arTxPwr = txPwr; + wake_up(&arEvent); +} + + +void +ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + A_MEMCPY(ar->arChannelList, chanList, numChan * sizeof (A_UINT16)); + ar->arNumChannels = numChan; + + wake_up(&arEvent); +} + +A_UINT8 +ar6000_ibss_map_epid(struct sk_buff *skb, struct net_device *dev, A_UINT32 * mapNo) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_UINT8 *datap; + ATH_MAC_HDR *macHdr; + A_UINT32 i, eptMap; + + (*mapNo) = 0; + datap = A_NETBUF_DATA(skb); + macHdr = (ATH_MAC_HDR *)(datap + sizeof(WMI_DATA_HDR)); + if (IEEE80211_IS_MULTICAST(macHdr->dstMac)) { + return ENDPOINT_2; + } + + eptMap = -1; + for (i = 0; i < ar->arNodeNum; i ++) { + if (IEEE80211_ADDR_EQ(macHdr->dstMac, ar->arNodeMap[i].macAddress)) { + (*mapNo) = i + 1; + ar->arNodeMap[i].txPending ++; + return ar->arNodeMap[i].epId; + } + + if ((eptMap == -1) && !ar->arNodeMap[i].txPending) { + eptMap = i; + } + } + + if (eptMap == -1) { + eptMap = ar->arNodeNum; + ar->arNodeNum ++; + A_ASSERT(ar->arNodeNum <= MAX_NODE_NUM); + } + + A_MEMCPY(ar->arNodeMap[eptMap].macAddress, macHdr->dstMac, IEEE80211_ADDR_LEN); + + for (i = ENDPOINT_2; i <= ENDPOINT_5; i ++) { + if (!ar->arTxPending[i]) { + ar->arNodeMap[eptMap].epId = i; + break; + } + // No free endpoint is available, start redistribution on the inuse endpoints. + if (i == ENDPOINT_5) { + ar->arNodeMap[eptMap].epId = ar->arNexEpId; + ar->arNexEpId ++; + if (ar->arNexEpId > ENDPOINT_5) { + ar->arNexEpId = ENDPOINT_2; + } + } + } + + (*mapNo) = eptMap + 1; + ar->arNodeMap[eptMap].txPending ++; + + return ar->arNodeMap[eptMap].epId; +} + +#ifdef DEBUG +static void ar6000_dump_skb(struct sk_buff *skb) +{ + u_char *ch; + for (ch = A_NETBUF_DATA(skb); + (A_UINT32)ch < ((A_UINT32)A_NETBUF_DATA(skb) + + A_NETBUF_LEN(skb)); ch++) + { + AR_DEBUG_PRINTF("%2.2x ", *ch); + } + AR_DEBUG_PRINTF("\n"); +} +#endif + +static int +ar6000_data_tx(struct sk_buff *skb, struct net_device *dev) +{ +#define AC_NOT_MAPPED 99 + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_UINT8 ac = AC_NOT_MAPPED; + HTC_ENDPOINT_ID eid = ENDPOINT_UNUSED; + A_UINT32 mapNo = 0; + int len; + struct ar_cookie *cookie; + A_BOOL checkAdHocPsMapping = FALSE,bMoreData = FALSE; + +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,13) + skb->list = NULL; +#endif + + AR_DEBUG2_PRINTF("ar6000_data_tx start - skb=0x%x, data=0x%x, len=0x%x\n", + (A_UINT32)skb, (A_UINT32)A_NETBUF_DATA(skb), + A_NETBUF_LEN(skb)); + + /* If target is not associated */ + if( (!ar->arConnected && !bypasswmi) +#ifdef CONFIG_HOST_TCMD_SUPPORT + /* TCMD doesnt support any data, free the buf and return */ + || (ar->arTargetMode == AR6000_TCMD_MODE) +#endif + ) { + A_NETBUF_FREE(skb); + return 0; + } + + do { + + if (ar->arWmiReady == FALSE && bypasswmi == 0) { + break; + } + +#ifdef BLOCK_TX_PATH_FLAG + if (blocktx) { + break; + } +#endif /* BLOCK_TX_PATH_FLAG */ + + /* AP mode Power save processing */ + /* If the dst STA is in sleep state, queue the pkt in its PS queue */ + + if (ar->arNetworkType == AP_NETWORK) { + ATH_MAC_HDR *datap = (ATH_MAC_HDR *)A_NETBUF_DATA(skb); + sta_t *conn = NULL; + + /* If the dstMac is a Multicast address & atleast one of the + * associated STA is in PS mode, then queue the pkt to the + * mcastq + */ + if (IEEE80211_IS_MULTICAST(datap->dstMac)) { + A_UINT8 ctr=0; + A_BOOL qMcast=FALSE; + + for (ctr=0; ctrsta_list[ctr]))) { + qMcast = TRUE; + } + } + if(qMcast) { + /* If this transmit is not because of a Dtim Expiry q it */ + if (ar->DTIMExpired == FALSE) { + A_BOOL isMcastqEmpty = FALSE; + + A_MUTEX_LOCK(&ar->mcastpsqLock); + isMcastqEmpty = A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq); + A_NETBUF_ENQUEUE(&ar->mcastpsq, skb); + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + + /* If this is the first Mcast pkt getting queued + * indicate to the target to set the BitmapControl LSB + * of the TIM IE. + */ + if (isMcastqEmpty) { + wmi_set_pvb_cmd(ar->arWmi, MCAST_AID, 1); + } + return 0; + } else { + /* This transmit is because of Dtim expiry. Determine if + * MoreData bit has to be set. + */ + A_MUTEX_LOCK(&ar->mcastpsqLock); + if(!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) { + bMoreData = TRUE; + } + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + } + } + } else { + conn = ieee80211_find_conn(ar, datap->dstMac); + if (conn) { + if (STA_IS_PWR_SLEEP(conn)) { + /* If this transmit is not because of a PsPoll q it*/ + if (!STA_IS_PS_POLLED(conn)) { + A_BOOL isPsqEmpty = FALSE; + /* Queue the frames if the STA is sleeping */ + A_MUTEX_LOCK(&conn->psqLock); + isPsqEmpty = A_NETBUF_QUEUE_EMPTY(&conn->psq); + A_NETBUF_ENQUEUE(&conn->psq, skb); + A_MUTEX_UNLOCK(&conn->psqLock); + + /* If this is the first pkt getting queued + * for this STA, update the PVB for this STA + */ + if (isPsqEmpty) { + wmi_set_pvb_cmd(ar->arWmi, conn->aid, 1); + } + + return 0; + } else { + /* This tx is because of a PsPoll. Determine if + * MoreData bit has to be set + */ + A_MUTEX_LOCK(&conn->psqLock); + if (!A_NETBUF_QUEUE_EMPTY(&conn->psq)) { + bMoreData = TRUE; + } + A_MUTEX_UNLOCK(&conn->psqLock); + } + } + } else { + + /* non existent STA. drop the frame */ + A_NETBUF_FREE(skb); + return 0; + } + } + } + + if (ar->arWmiEnabled) { + if (A_NETBUF_HEADROOM(skb) < dev->hard_header_len) { + struct sk_buff *newbuf; + + /* + * We really should have gotten enough headroom but sometimes + * we still get packets with not enough headroom. Copy the packet. + */ + len = A_NETBUF_LEN(skb); + newbuf = A_NETBUF_ALLOC(len); + if (newbuf == NULL) { + break; + } + A_NETBUF_PUT(newbuf, len); + A_MEMCPY(A_NETBUF_DATA(newbuf), A_NETBUF_DATA(skb), len); + A_NETBUF_FREE(skb); + skb = newbuf; + /* fall through and assemble header */ + } + + if (processDot11Hdr) { + if (wmi_dot11_hdr_add(ar->arWmi,skb,ar->arNetworkType) != A_OK) { + AR_DEBUG_PRINTF("ar6000_data_tx-wmi_dot11_hdr_add failed\n"); + break; + } + } else { + if (wmi_dix_2_dot3(ar->arWmi, skb) != A_OK) { + AR_DEBUG_PRINTF("ar6000_data_tx - wmi_dix_2_dot3 failed\n"); + break; + } + } + + if (wmi_data_hdr_add(ar->arWmi, skb, DATA_MSGTYPE, bMoreData) != A_OK) { + AR_DEBUG_PRINTF("ar6000_data_tx - wmi_data_hdr_add failed\n"); + break; + } + + if ((ar->arNetworkType == ADHOC_NETWORK) && + ar->arIbssPsEnable && ar->arConnected) { + /* flag to check adhoc mapping once we take the lock below: */ + checkAdHocPsMapping = TRUE; + + } else { + /* get the stream mapping */ + ac = wmi_implicit_create_pstream(ar->arWmi, skb, 0, ar->arWmmEnabled); + } + + } else { + struct iphdr *ipHdr; + /* + * the endpoint is directly based on the TOS field in the IP + * header **** only for testing ****** + */ + ipHdr = A_NETBUF_DATA(skb) + sizeof(ATH_MAC_HDR); + /* here we map the TOS field to an access class, this is for + * the endpointping test application. The application uses 0,1,2,3 + * for the TOS field to emulate writing to mailboxes. The number is + * used to map directly to an access class */ + ac = (ipHdr->tos >> 1) & 0x3; + } + + } while (FALSE); + + /* did we succeed ? */ + if ((ac == AC_NOT_MAPPED) && !checkAdHocPsMapping) { + /* cleanup and exit */ + A_NETBUF_FREE(skb); + AR6000_STAT_INC(ar, tx_dropped); + AR6000_STAT_INC(ar, tx_aborted_errors); + return 0; + } + + cookie = NULL; + + /* take the lock to protect driver data */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + do { + + if (checkAdHocPsMapping) { + eid = ar6000_ibss_map_epid(skb, dev, &mapNo); + }else { + eid = arAc2EndpointID (ar, ac); + } + /* validate that the endpoint is connected */ + if (eid == 0 || eid == ENDPOINT_UNUSED ) { + AR_DEBUG_PRINTF(" eid %d is NOT mapped!\n", eid); + break; + } + /* allocate resource for this packet */ + cookie = ar6000_alloc_cookie(ar); + + if (cookie != NULL) { + /* update counts while the lock is held */ + ar->arTxPending[eid]++; + ar->arTotalTxDataPending++; + } + + } while (FALSE); + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + if (cookie != NULL) { + cookie->arc_bp[0] = (A_UINT32)skb; + cookie->arc_bp[1] = mapNo; + SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt, + cookie, + A_NETBUF_DATA(skb), + A_NETBUF_LEN(skb), + eid, + AR6K_DATA_PKT_TAG); + +#ifdef DEBUG + if (debugdriver >= 3) { + ar6000_dump_skb(skb); + } +#endif + /* HTC interface is asynchronous, if this fails, cleanup will happen in + * the ar6000_tx_complete callback */ + HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt); + } else { + /* no packet to send, cleanup */ + A_NETBUF_FREE(skb); + AR6000_STAT_INC(ar, tx_dropped); + AR6000_STAT_INC(ar, tx_aborted_errors); + } + + return 0; +} + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +static void +tvsub(register struct timeval *out, register struct timeval *in) +{ + if((out->tv_usec -= in->tv_usec) < 0) { + out->tv_sec--; + out->tv_usec += 1000000; + } + out->tv_sec -= in->tv_sec; +} + +void +applyAPTCHeuristics(AR_SOFTC_T *ar) +{ + A_UINT32 duration; + A_UINT32 numbytes; + A_UINT32 throughput; + struct timeval ts; + A_STATUS status; + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + if ((enableAPTCHeuristics) && (!aptcTR.timerScheduled)) { + do_gettimeofday(&ts); + tvsub(&ts, &aptcTR.samplingTS); + duration = ts.tv_sec * 1000 + ts.tv_usec / 1000; /* ms */ + numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived; + + if (duration > APTC_TRAFFIC_SAMPLING_INTERVAL) { + /* Initialize the time stamp and byte count */ + aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0; + do_gettimeofday(&aptcTR.samplingTS); + + /* Calculate and decide based on throughput thresholds */ + throughput = ((numbytes * 8) / duration); + if (throughput > APTC_UPPER_THROUGHPUT_THRESHOLD) { + /* Disable Sleep and schedule a timer */ + A_ASSERT(ar->arWmiReady == TRUE); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + status = wmi_powermode_cmd(ar->arWmi, MAX_PERF_POWER); + AR6000_SPIN_LOCK(&ar->arLock, 0); + A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0); + aptcTR.timerScheduled = TRUE; + } + } + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); +} +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +static HTC_SEND_FULL_ACTION ar6000_tx_queue_full(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + HTC_SEND_FULL_ACTION action = HTC_SEND_FULL_KEEP; + A_BOOL stopNet = FALSE; + HTC_ENDPOINT_ID Endpoint = HTC_GET_ENDPOINT_FROM_PKT(pPacket); + + do { + + if (bypasswmi) { + /* for endpointping testing no other checks need to be made + * we can however still allow the network to stop */ + stopNet = TRUE; + break; + } + + if (Endpoint == ar->arControlEp) { + /* under normal WMI if this is getting full, then something is running rampant + * the host should not be exhausting the WMI queue with too many commands + * the only exception to this is during testing using endpointping */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + /* set flag to handle subsequent messages */ + ar->arWMIControlEpFull = TRUE; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + A_PRINTF("AR6000:WMI Control Endpoint is FULL!!! \n"); + /* no need to stop the network */ + stopNet = FALSE; + /* + * target is stuck - treat it as a target assert + */ + ar6000_target_failure(ar, A_ERROR); + + break; + } + + /* if we get here, we are dealing with data endpoints getting full */ + + if (HTC_GET_TAG_FROM_PKT(pPacket) == AR6K_CONTROL_PKT_TAG) { + /* don't drop control packets issued on ANY data endpoint */ + break; + } + + if (ar->arNetworkType == ADHOC_NETWORK) { + /* in adhoc mode, we cannot differentiate traffic priorities so there is no need to + * continue, however we should stop the network */ + stopNet = TRUE; + break; + } + + if (ar->arAcStreamPriMap[arEndpoint2Ac(ar,Endpoint)] < ar->arHiAcStreamActivePri) { + /* this stream's priority is less than the highest active priority, we + * give preference to the highest priority stream by directing + * HTC to drop the packet that overflowed */ + action = HTC_SEND_FULL_DROP; + /* since we are dropping packets, no need to stop the network */ + stopNet = FALSE; + break; + } + + } while (FALSE); + + if (stopNet) { + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arNetQueueStopped = TRUE; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + /* one of the data endpoints queues is getting full..need to stop network stack + * the queue will resume in ar6000_tx_complete() */ + netif_stop_queue(ar->arNetDev); + } + + return action; +} + + +static void +ar6000_tx_complete(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + void *cookie = (void *)pPacket->pPktContext; + struct sk_buff *skb = NULL; + A_UINT32 mapNo = 0; + A_STATUS status; + struct ar_cookie * ar_cookie; + HTC_ENDPOINT_ID eid; + A_BOOL wakeEvent = FALSE; + + status = pPacket->Status; + ar_cookie = (struct ar_cookie *)cookie; + skb = (struct sk_buff *)ar_cookie->arc_bp[0]; + eid = pPacket->Endpoint ; + mapNo = ar_cookie->arc_bp[1]; + + A_ASSERT(skb); + A_ASSERT(pPacket->pBuffer == A_NETBUF_DATA(skb)); + + if (A_SUCCESS(status)) { + A_ASSERT(pPacket->ActualLength == A_NETBUF_LEN(skb)); + } + + AR_DEBUG2_PRINTF("ar6000_tx_complete skb=0x%x data=0x%x len=0x%x eid=%d ", + (A_UINT32)skb, (A_UINT32)pPacket->pBuffer, + pPacket->ActualLength, + eid); + + /* lock the driver as we update internal state */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + ar->arTxPending[eid]--; + + if ((eid != ar->arControlEp) || bypasswmi) { + ar->arTotalTxDataPending--; + } + + if (eid == ar->arControlEp) + { + if (ar->arWMIControlEpFull) { + /* since this packet completed, the WMI EP is no longer full */ + ar->arWMIControlEpFull = FALSE; + } + + if (ar->arTxPending[eid] == 0) { + wakeEvent = TRUE; + } + } + + if (A_FAILED(status)) { + AR6000_STAT_INC(ar, tx_errors); + if (status != A_NO_RESOURCE) { + AR_DEBUG_PRINTF("%s() -TX ERROR, status: 0x%x\n", __func__, + status); + } + } else { + AR_DEBUG2_PRINTF("OK\n"); + AR6000_STAT_INC(ar, tx_packets); + ar->arNetStats.tx_bytes += A_NETBUF_LEN(skb); +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + aptcTR.bytesTransmitted += a_netbuf_to_len(skb); + applyAPTCHeuristics(ar); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + } + + // TODO this needs to be looked at + if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable + && (eid != ar->arControlEp) && mapNo) + { + mapNo --; + ar->arNodeMap[mapNo].txPending --; + + if (!ar->arNodeMap[mapNo].txPending && (mapNo == (ar->arNodeNum - 1))) { + A_UINT32 i; + for (i = ar->arNodeNum; i > 0; i --) { + if (!ar->arNodeMap[i - 1].txPending) { + A_MEMZERO(&ar->arNodeMap[i - 1], sizeof(struct ar_node_mapping)); + ar->arNodeNum --; + } else { + break; + } + } + } + } + + /* Freeing a cookie should not be contingent on either of */ + /* these flags, just if we have a cookie or not. */ + /* Can we even get here without a cookie? Fix later. */ + if (ar->arWmiReady == TRUE || (bypasswmi)) + { + ar6000_free_cookie(ar, cookie); + } + + if (ar->arNetQueueStopped) { + ar->arNetQueueStopped = FALSE; + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + /* lock is released, we can freely call other kernel APIs */ + + A_NETBUF_FREE(skb); + + if ((ar->arConnected == TRUE) || (bypasswmi)) { + if (status != A_ECANCELED) { + /* don't wake the queue if we are flushing, other wise it will just + * keep queueing packets, which will keep failing */ + netif_wake_queue(ar->arNetDev); + } + } + + if (wakeEvent) { + wake_up(&arEvent); + } + +} + +sta_t * +ieee80211_find_conn(AR_SOFTC_T *ar, A_UINT8 *node_addr) +{ + sta_t *conn = NULL; + A_UINT8 i, max_conn; + + switch(ar->arNetworkType) { + case AP_NETWORK: + max_conn = AP_MAX_NUM_STA; + break; + default: + max_conn=0; + break; + } + + for (i = 0; i < max_conn; i++) { + if (IEEE80211_ADDR_EQ(node_addr, ar->sta_list[i].mac)) { + conn = &ar->sta_list[i]; + break; + } + } + + return conn; +} + +sta_t *ieee80211_find_conn_for_aid(AR_SOFTC_T *ar, A_UINT8 aid) +{ + sta_t *conn = NULL; + A_UINT8 ctr; + + for (ctr = 0; ctr < AP_MAX_NUM_STA; ctr++) { + if (ar->sta_list[ctr].aid == aid) { + conn = &ar->sta_list[ctr]; + break; + } + } + return conn; +} + +/* + * Receive event handler. This is called by HTC when a packet is received + */ +int pktcount; +static void +ar6000_rx(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + struct sk_buff *skb = (struct sk_buff *)pPacket->pPktContext; + int minHdrLen; + A_STATUS status = pPacket->Status; + HTC_ENDPOINT_ID ept = pPacket->Endpoint; + + A_ASSERT((status != A_OK) || + (pPacket->pBuffer == (A_NETBUF_DATA(skb) + HTC_HEADER_LEN))); + + AR_DEBUG2_PRINTF("ar6000_rx ar=0x%x eid=%d, skb=0x%x, data=0x%x, len=0x%x ", + (A_UINT32)ar, ept, (A_UINT32)skb, (A_UINT32)pPacket->pBuffer, + pPacket->ActualLength); + if (status != A_OK) { + AR_DEBUG2_PRINTF("ERR\n"); + } else { + AR_DEBUG2_PRINTF("OK\n"); + } + + /* take lock to protect buffer counts + * and adaptive power throughput state */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + ar->arRxBuffers[ept]--; + + if (A_SUCCESS(status)) { + AR6000_STAT_INC(ar, rx_packets); + ar->arNetStats.rx_bytes += pPacket->ActualLength; +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + aptcTR.bytesReceived += a_netbuf_to_len(skb); + applyAPTCHeuristics(ar); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + + A_NETBUF_PUT(skb, pPacket->ActualLength + HTC_HEADER_LEN); + A_NETBUF_PULL(skb, HTC_HEADER_LEN); + +#ifdef DEBUG + if (debugdriver >= 2) { + ar6000_dump_skb(skb); + } +#endif /* DEBUG */ + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + skb->dev = ar->arNetDev; + if (status != A_OK) { + AR6000_STAT_INC(ar, rx_errors); + A_NETBUF_FREE(skb); + } else if (ar->arWmiEnabled == TRUE) { + if (ept == ar->arControlEp) { + /* + * this is a wmi control msg + */ + wmi_control_rx(ar->arWmi, skb); + } else { + /* + * this is a wmi data packet + */ + // NWF + + if (processDot11Hdr) { + minHdrLen = sizeof(WMI_DATA_HDR) + sizeof(struct ieee80211_frame) + sizeof(ATH_LLC_SNAP_HDR); + } else { + minHdrLen = sizeof (WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + + sizeof(ATH_LLC_SNAP_HDR); + } + + /* In the case of AP mode we may receive NULL data frames + * that do not have LLC hdr. They are 16 bytes in size. + * Allow these frames in the AP mode. + */ + if (ar->arNetworkType != AP_NETWORK && ((pPacket->ActualLength < minHdrLen) || + (pPacket->ActualLength > AR6000_BUFFER_SIZE))) + { + /* + * packet is too short or too long + */ + AR_DEBUG_PRINTF("TOO SHORT or TOO LONG\n"); + AR6000_STAT_INC(ar, rx_errors); + AR6000_STAT_INC(ar, rx_length_errors); + A_NETBUF_FREE(skb); + } else { +#if 0 + /* Access RSSI values here */ + AR_DEBUG_PRINTF("RSSI %d\n", + ((WMI_DATA_HDR *) A_NETBUF_DATA(skb))->rssi); +#endif + /* Get the Power save state of the STA */ + if (ar->arNetworkType == AP_NETWORK) { + sta_t *conn = NULL; + A_UINT8 psState=0,prevPsState; + ATH_MAC_HDR *datap=NULL; + + psState = (((WMI_DATA_HDR *)A_NETBUF_DATA(skb))->info + >> WMI_DATA_HDR_PS_SHIFT) & WMI_DATA_HDR_PS_MASK; + datap = (ATH_MAC_HDR *)(A_NETBUF_DATA(skb)+sizeof(WMI_DATA_HDR)); + conn = ieee80211_find_conn(ar, datap->srcMac); + + + if (conn) { + /* if there is a change in PS state of the STA, + * take appropriate steps. + * 1. If Sleep-->Awake, flush the psq for the STA + * Clear the PVB for the STA. + * 2. If Awake-->Sleep, Starting queueing frames + * the STA. + */ + prevPsState = STA_IS_PWR_SLEEP(conn); + if (psState) { + STA_SET_PWR_SLEEP(conn); + } else { + STA_CLR_PWR_SLEEP(conn); + } + + if (prevPsState ^ STA_IS_PWR_SLEEP(conn)) { + + if (!STA_IS_PWR_SLEEP(conn)) { + + A_MUTEX_LOCK(&conn->psqLock); + while (!A_NETBUF_QUEUE_EMPTY(&conn->psq)) { + struct sk_buff *skb=NULL; + + skb = A_NETBUF_DEQUEUE(&conn->psq); + A_MUTEX_UNLOCK(&conn->psqLock); + ar6000_data_tx(skb,ar->arNetDev); + A_MUTEX_LOCK(&conn->psqLock); + } + A_MUTEX_UNLOCK(&conn->psqLock); + /* Clear the PVB for this STA */ + wmi_set_pvb_cmd(ar->arWmi, conn->aid, 0); + } + } + } else { + /* This frame is from a STA that is not associated*/ + A_ASSERT(FALSE); + } + + /* Drop NULL data frames here */ + if((pPacket->ActualLength < minHdrLen) || + (pPacket->ActualLength > AR6000_BUFFER_SIZE)) { + A_NETBUF_FREE(skb); + goto refill; + } + } + + wmi_data_hdr_remove(ar->arWmi, skb); + /* NWF: print the 802.11 hdr bytes */ + if(processDot11Hdr) { + wmi_dot11_hdr_remove(ar->arWmi,skb); + } else { + wmi_dot3_2_dix(ar->arWmi, skb); + } + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + /* + * extra push and memcpy, for eth_type_trans() of 2.4 kernel + * will pull out hard_header_len bytes of the skb. + */ + A_NETBUF_PUSH(skb, sizeof(WMI_DATA_HDR) + sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN); + A_MEMCPY(A_NETBUF_DATA(skb), A_NETBUF_DATA(skb) + sizeof(WMI_DATA_HDR) + + sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN, sizeof(ATH_MAC_HDR)); +#endif + if ((ar->arNetDev->flags & IFF_UP) == IFF_UP) { + if (ar->arNetworkType == AP_NETWORK) { + struct sk_buff *skb1 = NULL; + ATH_MAC_HDR *datap; + + datap = (ATH_MAC_HDR *)A_NETBUF_DATA(skb); + if (IEEE80211_IS_MULTICAST(datap->dstMac)) { + /* Bcast/Mcast frames should be sent to the OS + * stack as well as on the air. + */ + skb1 = skb_copy(skb,GFP_ATOMIC); + } else { + /* Search for a connected STA with dstMac as + * the Mac address. If found send the frame to + * it on the air else send the frame up the + * stack + */ + sta_t *conn = NULL; + conn = ieee80211_find_conn(ar, datap->dstMac); + + if (conn && ar->intra_bss) { + skb1 = skb; + skb = NULL; + } else if(conn && !ar->intra_bss) { + A_NETBUF_FREE(skb); + skb = NULL; + } + } + if (skb1) { + ar6000_data_tx(skb1, ar->arNetDev); + } + } + } + deliver_frames_to_nw_stack(skb); + } + } + } else { + deliver_frames_to_nw_stack(skb); + } +refill: + if (status != A_ECANCELED) { + /* + * HTC provides A_ECANCELED status when it doesn't want to be refilled + * (probably due to a shutdown) + */ + ar6000_rx_refill(Context, ept); + } + + +} + +static void +deliver_frames_to_nw_stack(struct sk_buff *skb) +{ + if(skb) { + if ((skb->dev->flags & IFF_UP) == IFF_UP) { + skb->protocol = eth_type_trans(skb, skb->dev); + netif_rx(skb); + } else { + A_NETBUF_FREE(skb); + } + } +} + + +static void +ar6000_rx_refill(void *Context, HTC_ENDPOINT_ID Endpoint) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + void *osBuf; + int RxBuffers; + int buffersToRefill; + HTC_PACKET *pPacket; + + buffersToRefill = (int)AR6000_MAX_RX_BUFFERS - + (int)ar->arRxBuffers[Endpoint]; + + if (buffersToRefill <= 0) { + /* fast return, nothing to fill */ + return; + } + + AR_DEBUG2_PRINTF("ar6000_rx_refill: providing htc with %d buffers at eid=%d\n", + buffersToRefill, Endpoint); + + for (RxBuffers = 0; RxBuffers < buffersToRefill; RxBuffers++) { + osBuf = A_NETBUF_ALLOC(AR6000_BUFFER_SIZE); + if (NULL == osBuf) { + break; + } + /* the HTC packet wrapper is at the head of the reserved area + * in the skb */ + pPacket = (HTC_PACKET *)(A_NETBUF_HEAD(osBuf)); + /* set re-fill info */ + SET_HTC_PACKET_INFO_RX_REFILL(pPacket,osBuf,A_NETBUF_DATA(osBuf),AR6000_BUFFER_SIZE,Endpoint); + /* add this packet */ + HTCAddReceivePkt(ar->arHtcTarget, pPacket); + } + + /* update count */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arRxBuffers[Endpoint] += RxBuffers; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); +} + +static struct net_device_stats * +ar6000_get_stats(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + return &ar->arNetStats; +} + +static struct iw_statistics * +ar6000_get_iwstats(struct net_device * dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + TARGET_STATS *pStats = &ar->arTargetStats; + struct iw_statistics * pIwStats = &ar->arIwStats; + + if (ar->bIsDestroyProgress || ar->arWmiReady == FALSE) + { + pIwStats->status = 0; + pIwStats->qual.qual = 0; + pIwStats->qual.level =0; + pIwStats->qual.noise = 0; + pIwStats->discard.code =0; + pIwStats->discard.retries=0; + pIwStats->miss.beacon =0; + return pIwStats; + } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + /* + * The in_atomic function is used to determine if the scheduling is + * allowed in the current context or not. This was introduced in 2.6 + * From what I have read on the differences between 2.4 and 2.6, the + * 2.4 kernel did not support preemption and so this check might not + * be required for 2.4 kernels. + */ + if (in_atomic()) + { + wmi_get_stats_cmd(ar->arWmi); + + pIwStats->status = 1 ; + pIwStats->qual.qual = pStats->cs_aveBeacon_rssi - 161; + pIwStats->qual.level =pStats->cs_aveBeacon_rssi; /* noise is -95 dBm */ + pIwStats->qual.noise = pStats->noise_floor_calibation; + pIwStats->discard.code = pStats->rx_decrypt_err; + pIwStats->discard.retries = pStats->tx_retry_cnt; + pIwStats->miss.beacon = pStats->cs_bmiss_cnt; + return pIwStats; + } +#endif /* LINUX_VERSION_CODE */ + + if (down_interruptible(&ar->arSem)) { + pIwStats->status = 0; + return pIwStats; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + pIwStats->status = 0; + return pIwStats; + } + + ar->statsUpdatePending = TRUE; + + if(wmi_get_stats_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + pIwStats->status = 0; + return pIwStats; + } + + wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ); + + if (signal_pending(current)) { + AR_DEBUG_PRINTF("ar6000 : WMI get stats timeout \n"); + up(&ar->arSem); + pIwStats->status = 0; + return pIwStats; + } + pIwStats->status = 1 ; + pIwStats->qual.qual = pStats->cs_aveBeacon_rssi - 161; + pIwStats->qual.level =pStats->cs_aveBeacon_rssi; /* noise is -95 dBm */ + pIwStats->qual.noise = pStats->noise_floor_calibation; + pIwStats->discard.code = pStats->rx_decrypt_err; + pIwStats->discard.retries = pStats->tx_retry_cnt; + pIwStats->miss.beacon = pStats->cs_bmiss_cnt; + up(&ar->arSem); + return pIwStats; +} + +void +ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap, A_UINT32 vers) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + struct net_device *dev = ar->arNetDev; + + ar->arWmiReady = TRUE; + wake_up(&arEvent); + A_MEMCPY(dev->dev_addr, datap, AR6000_ETH_ADDR_LEN); + AR_DEBUG_PRINTF("mac address = %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", + dev->dev_addr[0], dev->dev_addr[1], + dev->dev_addr[2], dev->dev_addr[3], + dev->dev_addr[4], dev->dev_addr[5]); + + ar->arPhyCapability = phyCap; + ar->arVersion.wlan_ver = vers; + +#define LAB126_DISCONNECT_TIMEOUT 5 /* default is 10 sec */ + wmi_disctimeout_cmd(ar->arWmi, LAB126_DISCONNECT_TIMEOUT); +} + +A_UINT8 +add_new_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 aid, A_UINT8 *wpaie, A_UINT8 ielen) +{ + A_INT8 free_slot=-1, i; + + for(i=0; i < AP_MAX_NUM_STA; i++) { + if(A_MEMCMP(ar->sta_list[i].mac, mac, ATH_MAC_LEN)==0) { + /* it is already available */ + return 0; + } + + if(!((1 << i) & ar->sta_list_index)) { + free_slot = i; + break; + } + } + + if(free_slot >= 0) { + A_MEMCPY(ar->sta_list[free_slot].mac, mac, ATH_MAC_LEN); + A_MEMCPY(ar->sta_list[free_slot].wpa_ie, wpaie, ielen); + ar->sta_list[free_slot].aid = aid; + ar->sta_list_index = ar->sta_list_index | (1 << free_slot); + return 1; + } + return 0; /* not added */ +} + +void +ar6000_connect_event(AR_SOFTC_T *ar, A_UINT16 channel, A_UINT8 *bssid, + A_UINT16 listenInterval, A_UINT16 beaconInterval, + NETWORK_TYPE networkType, A_UINT8 beaconIeLen, + A_UINT8 assocReqLen, A_UINT8 assocRespLen, + A_UINT8 *assocInfo) +{ + union iwreq_data wrqu; + int i, beacon_ie_pos, assoc_resp_ie_pos, assoc_req_ie_pos; + static const char *tag1 = "ASSOCINFO(ReqIEs="; + static const char *tag2 = "ASSOCRESPIE="; + static const char *beaconIetag = "BEACONIE="; + char buf[WMI_CONTROL_MSG_MAX_LEN * 2 + strlen(tag1) + 1]; + char *pos; + A_UINT8 key_op_ctrl; + unsigned long flags; + + if(ar->arNetworkType & AP_NETWORK) { + A_PRINTF("NEW STA %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x " + " aid=%d WPAIE=%d\n", bssid[0], bssid[1], bssid[2], + bssid[3], bssid[4], bssid[5], channel, assocRespLen); + add_new_sta(ar, bssid, channel /*aid*/, + assocInfo /* WPA IE */, assocRespLen /* IE len */); + + /* Send event to application */ + A_MEMZERO(&wrqu, sizeof(wrqu)); + A_MEMCPY(wrqu.addr.sa_data, bssid, ATH_MAC_LEN); + wireless_send_event(ar->arNetDev, IWEVREGISTERED, &wrqu, NULL); + /* In case the queue is stopped when we switch modes, this will + * wake it up + */ + netif_wake_queue(ar->arNetDev); + return; + } + + if (FALSE == ar->arConnected && + ((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode))) + { + A_TIMEOUT_MS(&ar->disconnect_timer, A_DISCONNECT_TIMER_INTERVAL, 0); + } + + A_MEMCPY(ar->arBssid, bssid, sizeof(ar->arBssid)); + ar->arBssChannel = channel; + + AR_DEBUG_PRINTF("AR6000 connected event on freq %d ", channel); + AR_DEBUG_PRINTF("with bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x " + " listenInterval=%d, beaconInterval = %d, beaconIeLen = %d assocReqLen=%d" + " assocRespLen =%d\n", + bssid[0], bssid[1], bssid[2], + bssid[3], bssid[4], bssid[5], + listenInterval, beaconInterval, + beaconIeLen, assocReqLen, assocRespLen); + if (networkType & ADHOC_NETWORK) { + if (networkType & ADHOC_CREATOR) { + A_PRINTF("Network: Adhoc (Creator)\n"); + } else { + A_PRINTF("Network: Adhoc (Joiner)\n"); + } + } + + if (beaconIeLen && (sizeof(buf) > (9 + beaconIeLen * 2))) { + AR_DEBUG_PRINTF("\nBeaconIEs= "); + + beacon_ie_pos = 0; + A_MEMZERO(buf, sizeof(buf)); + sprintf(buf, "%s", beaconIetag); + pos = buf + 9; + for (i = beacon_ie_pos; i < beacon_ie_pos + beaconIeLen; i++) { + AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]); + sprintf(pos, "%2.2x", assocInfo[i]); + pos += 2; + } + AR_DEBUG_PRINTF("\n"); + + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + } + + if (assocRespLen && (sizeof(buf) > (12 + (assocRespLen * 2)))) + { + assoc_resp_ie_pos = beaconIeLen + assocReqLen + + sizeof(A_UINT16) + /* capinfo*/ + sizeof(A_UINT16) + /* status Code */ + sizeof(A_UINT16) ; /* associd */ + A_MEMZERO(buf, sizeof(buf)); + sprintf(buf, "%s", tag2); + pos = buf + 12; + AR_DEBUG_PRINTF("\nAssocRespIEs= "); + /* + * The Association Response Frame w.o. the WLAN header is delivered to + * the host, so skip over to the IEs + */ + for (i = assoc_resp_ie_pos; i < assoc_resp_ie_pos + assocRespLen - 6; i++) + { + AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]); + sprintf(pos, "%2.2x", assocInfo[i]); + pos += 2; + } + AR_DEBUG_PRINTF("\n"); + + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + } + + if (assocReqLen && (sizeof(buf) > (17 + (assocReqLen * 2)))) { + /* + * assoc Request includes capability and listen interval. Skip these. + */ + assoc_req_ie_pos = beaconIeLen + + sizeof(A_UINT16) + /* capinfo*/ + sizeof(A_UINT16); /* listen interval */ + + A_MEMZERO(buf, sizeof(buf)); + sprintf(buf, "%s", tag1); + pos = buf + 17; + AR_DEBUG_PRINTF("AssocReqIEs= "); + for (i = assoc_req_ie_pos; i < assoc_req_ie_pos + assocReqLen - 4; i++) { + AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]); + sprintf(pos, "%2.2x", assocInfo[i]); + pos += 2;; + } + AR_DEBUG_PRINTF("\n"); + + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + } + +#ifdef USER_KEYS + if (ar->user_savedkeys_stat == USER_SAVEDKEYS_STAT_RUN && + ar->user_saved_keys.keyOk == TRUE) + { + key_op_ctrl = KEY_OP_VALID_MASK & ~KEY_OP_INIT_TSC; + + if (ar->user_key_ctrl & AR6000_USER_SETKEYS_RSC_UNCHANGED) { + key_op_ctrl &= ~KEY_OP_INIT_RSC; + } else { + key_op_ctrl |= KEY_OP_INIT_RSC; + } + ar6000_reinstall_keys(ar, key_op_ctrl); + } +#endif /* USER_KEYS */ + + netif_wake_queue(ar->arNetDev); + + if ((networkType & ADHOC_NETWORK) && + (OPEN_AUTH == ar->arDot11AuthMode) && + (NONE_AUTH == ar->arAuthMode) && + (WEP_CRYPT == ar->arPairwiseCrypto)) + { + if (!ar->arConnected) { + wmi_addKey_cmd(ar->arWmi, + ar->arDefTxKeyIndex, + WEP_CRYPT, + GROUP_USAGE | TX_USAGE, + ar->arWepKeyList[ar->arDefTxKeyIndex].arKeyLen, + NULL, + ar->arWepKeyList[ar->arDefTxKeyIndex].arKey, KEY_OP_INIT_VAL, NULL, + NO_SYNC_WMIFLAG); + } + } + + /* Update connect & link status atomically */ + spin_lock_irqsave(&ar->arLock, flags); + ar->arConnected = TRUE; + ar->arConnectPending = FALSE; + netif_carrier_on(ar->arNetDev); + spin_unlock_irqrestore(&ar->arLock, flags); + + reconnect_flag = 0; + + A_MEMZERO(&wrqu, sizeof(wrqu)); + A_MEMCPY(wrqu.addr.sa_data, bssid, IEEE80211_ADDR_LEN); + wrqu.addr.sa_family = ARPHRD_ETHER; + wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL); + if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable) { + A_MEMZERO(ar->arNodeMap, sizeof(ar->arNodeMap)); + ar->arNodeNum = 0; + ar->arNexEpId = ENDPOINT_2; + } +} + +void ar6000_set_numdataendpts(AR_SOFTC_T *ar, A_UINT32 num) +{ + A_ASSERT(num <= (HTC_MAILBOX_NUM_MAX - 1)); + ar->arNumDataEndPts = num; +} + +A_UINT8 +remove_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 reason) +{ + A_INT8 i; + struct sk_buff *skb; + + if(IS_MAC_NULL(mac)) { + return 0; + } + + for(i=0; i < AP_MAX_NUM_STA; i++) { + if(A_MEMCMP(ar->sta_list[i].mac, mac, ATH_MAC_LEN)==0) { + + /* empty the queued pkts in the PS queue if any */ + A_MUTEX_LOCK(&ar->sta_list[i].psqLock); + while (!A_NETBUF_QUEUE_EMPTY(&ar->sta_list[i].psq)) { + skb = A_NETBUF_DEQUEUE(&ar->sta_list[i].psq); + A_NETBUF_FREE(skb); + } + A_MUTEX_UNLOCK(&ar->sta_list[i].psqLock); + + A_PRINTF("DEL STA %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x " + " aid=%d REASON=%d\n", mac[0], mac[1], mac[2], + mac[3], mac[4], mac[5], ar->sta_list[i].aid, reason); + + /* Zero out the state fields */ + A_MEMZERO(&ar->sta_list[i].mac, ATH_MAC_LEN); + A_MEMZERO(&ar->sta_list[i].wpa_ie, IEEE80211_MAX_IE); + ar->sta_list[i].aid = 0; + ar->sta_list[i].flags = 0; + + ar->sta_list_index = ar->sta_list_index & ~(1 << i); + return 1; + } + } + + return 0; /* not removed */ +} + +void +ar6000_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason, A_UINT8 *bssid, + A_UINT8 assocRespLen, A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus) +{ + A_UINT8 i; + unsigned long flags; + + if(ar->arNetworkType & AP_NETWORK) { + union iwreq_data wrqu; + struct sk_buff *skb; + + if(!remove_sta(ar, bssid, protocolReasonStatus)) { + return; + } + + /* If there are no more associated STAs, empty the mcast PS q */ + if (ar->sta_list_index == 0) { + A_MUTEX_LOCK(&ar->mcastpsqLock); + while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) { + skb = A_NETBUF_DEQUEUE(&ar->mcastpsq); + A_NETBUF_FREE(skb); + } + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + } + + /* Send event to application */ + A_MEMZERO(&wrqu, sizeof(wrqu)); + A_MEMCPY(wrqu.addr.sa_data, bssid, ATH_MAC_LEN); + wireless_send_event(ar->arNetDev, IWEVEXPIRED, &wrqu, NULL); + return; + } +/* + * Atheros driver is not sending disconnect for some reason when it gets + * a NO_NETWORK_AVAIL. We have asked why + * if (NO_NETWORK_AVAIL != reason) + */ + { + union iwreq_data wrqu; + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.addr.sa_family = ARPHRD_ETHER; + A_MEMCPY(wrqu.addr.sa_data, bssid, IEEE80211_ADDR_LEN); + /* + * We use the higuest byte in sockaddr ([13]) to indicate that this is a disconnect and + * the reason of the disconnect + */ + wrqu.addr.sa_data[13] = (!reason)? NO_NETWORK_AVAIL:reason; + + /* Send disconnect event to supplicant */ + wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL); + } + + A_UNTIMEOUT(&ar->disconnect_timer); + + AR_DEBUG_PRINTF("AR6000 disconnected"); + if (bssid[0] || bssid[1] || bssid[2] || bssid[3] || bssid[4] || bssid[5]) { + AR_DEBUG_PRINTF(" from %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", + bssid[0], bssid[1], bssid[2], bssid[3], bssid[4], bssid[5]); + } + + AR_DEBUG_PRINTF("\nDisconnect Reason is %d", reason); + AR_DEBUG_PRINTF("\nProtocol Reason/Status Code is %d", protocolReasonStatus); + AR_DEBUG_PRINTF("\nAssocResp Frame = %s", + assocRespLen ? " " : "NULL"); + for (i = 0; i < assocRespLen; i++) { + if (!(i % 0x10)) { + AR_DEBUG_PRINTF("\n"); + } + AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]); + } + AR_DEBUG_PRINTF("\n"); + /* + * If the event is due to disconnect cmd from the host, only they the target + * would stop trying to connect. Under any other condition, target would + * keep trying to connect. + * + */ + if( reason == DISCONNECT_CMD) + { + ar->arConnectPending = FALSE; + } else { + ar->arConnectPending = TRUE; + if (((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x11)) || + ((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x0) && (reconnect_flag == 1))) { + ar->arConnected = TRUE; + return; + } + } + + if (reason == NO_NETWORK_AVAIL) + { + bss_t *pWmiSsidnode = NULL; + + /* remove the current associated bssid node */ + wmi_free_node (ar->arWmi, bssid); + + /* + * In case any other same SSID nodes are present + * remove it, since those nodes also not available now + */ + do + { + /* + * Find the nodes based on SSID and remove it + * NOTE :: This case will not work out for Hidden-SSID + */ + pWmiSsidnode = wmi_find_Ssidnode (ar->arWmi, ar->arSsid, ar->arSsidLen, FALSE, TRUE); + + if (pWmiSsidnode) + { + wmi_free_node (ar->arWmi, pWmiSsidnode->ni_macaddr); + } + + }while (pWmiSsidnode); + + ar6000_init_profile_info(ar); + wmi_disconnect_cmd(ar->arWmi); + } + + /* Update connect & link status atomically */ + spin_lock_irqsave(&ar->arLock, flags); + ar->arConnected = FALSE; + netif_carrier_off(ar->arNetDev); + spin_unlock_irqrestore(&ar->arLock, flags); + + if( (reason != CSERV_DISCONNECT) || (reconnect_flag != 1) ) { + reconnect_flag = 0; + } + +#ifdef USER_KEYS + if (reason != CSERV_DISCONNECT) + { + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT; + ar->user_key_ctrl = 0; + } +#endif /* USER_KEYS */ + + netif_stop_queue(ar->arNetDev); + A_MEMZERO(ar->arBssid, sizeof(ar->arBssid)); + ar->arBssChannel = 0; + ar->arBeaconInterval = 0; + + ar6000_TxDataCleanup(ar); +} + +void +ar6000_regDomain_event(AR_SOFTC_T *ar, A_UINT32 regCode) +{ + A_PRINTF("AR6000 Reg Code = 0x%x\n", regCode); + ar->arRegCode = regCode; +} + +void +ar6000_neighborReport_event(AR_SOFTC_T *ar, int numAps, WMI_NEIGHBOR_INFO *info) +{ + static const char *tag = "PRE-AUTH"; + char buf[128]; + union iwreq_data wrqu; + int i; + + AR_DEBUG_PRINTF("AR6000 Neighbor Report Event\n"); + for (i=0; i < numAps; info++, i++) { + AR_DEBUG_PRINTF("bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", + info->bssid[0], info->bssid[1], info->bssid[2], + info->bssid[3], info->bssid[4], info->bssid[5]); + if (info->bssFlags & WMI_PREAUTH_CAPABLE_BSS) { + AR_DEBUG_PRINTF("preauth-cap"); + } + if (info->bssFlags & WMI_PMKID_VALID_BSS) { + AR_DEBUG_PRINTF(" pmkid-valid\n"); + continue; /* we skip bss if the pmkid is already valid */ + } + AR_DEBUG_PRINTF("\n"); + snprintf(buf, sizeof(buf), "%s%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x", + tag, + info->bssid[0], info->bssid[1], info->bssid[2], + info->bssid[3], info->bssid[4], info->bssid[5], + i, info->bssFlags); + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + } +} + +void +ar6000_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast) +{ + static const char *tag = "MLME-MICHAELMICFAILURE.indication"; + char buf[128]; + union iwreq_data wrqu; + + /* + * For AP case, keyid will have aid of STA which sent pkt with + * MIC error. Use this aid to get MAC & send it to hostapd. + */ + if (ar->arNetworkType == AP_NETWORK) { + sta_t *s = ieee80211_find_conn_for_aid(ar, keyid); + A_PRINTF("AP TKIP MIC error received from aid=%d\n", keyid); + snprintf(buf,sizeof(buf), "%s addr=%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x", + tag, s->mac[0],s->mac[1],s->mac[2],s->mac[3],s->mac[4],s->mac[5]); + } else { + A_PRINTF("AR6000 TKIP MIC error received for keyid %d %scast\n", + keyid, ismcast ? "multi": "uni"); + snprintf(buf, sizeof(buf), "%s(keyid=%d %sicast)", tag, keyid, + ismcast ? "mult" : "un"); + } + + memset(&wrqu, 0, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); +} + +void +ar6000_scanComplete_event(AR_SOFTC_T *ar, A_STATUS status) +{ + union iwreq_data wrqu; + + AR_DEBUG_PRINTF("AR6000 scan complete: %d\n", status); + ar->scan_complete = 1; + wake_up_interruptible(&ar6000_scan_queue); + + memset(&wrqu, 0, sizeof(wrqu)); + wrqu.data.flags = status; + wireless_send_event(ar->arNetDev, SIOCGIWSCAN, &wrqu, NULL); +} + +void +ar6000_targetStats_event(AR_SOFTC_T *ar, WMI_TARGET_STATS *pTarget) +{ + TARGET_STATS *pStats = &ar->arTargetStats; + A_UINT8 ac; + + pStats->tx_packets += pTarget->txrxStats.tx_stats.tx_packets; + pStats->tx_bytes += pTarget->txrxStats.tx_stats.tx_bytes; + pStats->tx_unicast_pkts += pTarget->txrxStats.tx_stats.tx_unicast_pkts; + pStats->tx_unicast_bytes += pTarget->txrxStats.tx_stats.tx_unicast_bytes; + pStats->tx_multicast_pkts += pTarget->txrxStats.tx_stats.tx_multicast_pkts; + pStats->tx_multicast_bytes += pTarget->txrxStats.tx_stats.tx_multicast_bytes; + pStats->tx_broadcast_pkts += pTarget->txrxStats.tx_stats.tx_broadcast_pkts; + pStats->tx_broadcast_bytes += pTarget->txrxStats.tx_stats.tx_broadcast_bytes; + pStats->tx_rts_success_cnt += pTarget->txrxStats.tx_stats.tx_rts_success_cnt; + for(ac = 0; ac < WMM_NUM_AC; ac++) + pStats->tx_packet_per_ac[ac] += pTarget->txrxStats.tx_stats.tx_packet_per_ac[ac]; + pStats->tx_errors += pTarget->txrxStats.tx_stats.tx_errors; + pStats->tx_failed_cnt += pTarget->txrxStats.tx_stats.tx_failed_cnt; + pStats->tx_retry_cnt += pTarget->txrxStats.tx_stats.tx_retry_cnt; + pStats->tx_mult_retry_cnt += pTarget->txrxStats.tx_stats.tx_mult_retry_cnt; + pStats->tx_rts_fail_cnt += pTarget->txrxStats.tx_stats.tx_rts_fail_cnt; + pStats->tx_unicast_rate = wmi_get_rate(pTarget->txrxStats.tx_stats.tx_unicast_rate); + + pStats->rx_packets += pTarget->txrxStats.rx_stats.rx_packets; + pStats->rx_bytes += pTarget->txrxStats.rx_stats.rx_bytes; + pStats->rx_unicast_pkts += pTarget->txrxStats.rx_stats.rx_unicast_pkts; + pStats->rx_unicast_bytes += pTarget->txrxStats.rx_stats.rx_unicast_bytes; + pStats->rx_multicast_pkts += pTarget->txrxStats.rx_stats.rx_multicast_pkts; + pStats->rx_multicast_bytes += pTarget->txrxStats.rx_stats.rx_multicast_bytes; + pStats->rx_broadcast_pkts += pTarget->txrxStats.rx_stats.rx_broadcast_pkts; + pStats->rx_broadcast_bytes += pTarget->txrxStats.rx_stats.rx_broadcast_bytes; + pStats->rx_fragment_pkt += pTarget->txrxStats.rx_stats.rx_fragment_pkt; + pStats->rx_errors += pTarget->txrxStats.rx_stats.rx_errors; + pStats->rx_crcerr += pTarget->txrxStats.rx_stats.rx_crcerr; + pStats->rx_key_cache_miss += pTarget->txrxStats.rx_stats.rx_key_cache_miss; + pStats->rx_decrypt_err += pTarget->txrxStats.rx_stats.rx_decrypt_err; + pStats->rx_duplicate_frames += pTarget->txrxStats.rx_stats.rx_duplicate_frames; + pStats->rx_unicast_rate = wmi_get_rate(pTarget->txrxStats.rx_stats.rx_unicast_rate); + + + pStats->tkip_local_mic_failure + += pTarget->txrxStats.tkipCcmpStats.tkip_local_mic_failure; + pStats->tkip_counter_measures_invoked + += pTarget->txrxStats.tkipCcmpStats.tkip_counter_measures_invoked; + pStats->tkip_replays += pTarget->txrxStats.tkipCcmpStats.tkip_replays; + pStats->tkip_format_errors += pTarget->txrxStats.tkipCcmpStats.tkip_format_errors; + pStats->ccmp_format_errors += pTarget->txrxStats.tkipCcmpStats.ccmp_format_errors; + pStats->ccmp_replays += pTarget->txrxStats.tkipCcmpStats.ccmp_replays; + + + pStats->power_save_failure_cnt += pTarget->pmStats.power_save_failure_cnt; + pStats->noise_floor_calibation = pTarget->noise_floor_calibation; + + pStats->cs_bmiss_cnt += pTarget->cservStats.cs_bmiss_cnt; + pStats->cs_lowRssi_cnt += pTarget->cservStats.cs_lowRssi_cnt; + pStats->cs_connect_cnt += pTarget->cservStats.cs_connect_cnt; + pStats->cs_disconnect_cnt += pTarget->cservStats.cs_disconnect_cnt; + pStats->cs_aveBeacon_snr = pTarget->cservStats.cs_aveBeacon_snr; + pStats->cs_aveBeacon_rssi = pTarget->cservStats.cs_aveBeacon_rssi; + pStats->cs_lastRoam_msec = pTarget->cservStats.cs_lastRoam_msec; + pStats->cs_snr = pTarget->cservStats.cs_snr; + pStats->cs_rssi = pTarget->cservStats.cs_rssi; + + pStats->lq_val = pTarget->lqVal; + + pStats->wow_num_pkts_dropped += pTarget->wowStats.wow_num_pkts_dropped; + pStats->wow_num_host_pkt_wakeups += pTarget->wowStats.wow_num_host_pkt_wakeups; + pStats->wow_num_host_event_wakeups += pTarget->wowStats.wow_num_host_event_wakeups; + pStats->wow_num_events_discarded += pTarget->wowStats.wow_num_events_discarded; + + pStats->arp_received += pTarget->arpStats.arp_received; + pStats->arp_matched += pTarget->arpStats.arp_matched; + pStats->arp_replied += pTarget->arpStats.arp_replied; + + ar->statsUpdatePending = FALSE; + wake_up(&arEvent); +} + +void +ar6000_rssiThreshold_event(AR_SOFTC_T *ar, WMI_RSSI_THRESHOLD_VAL newThreshold, A_INT16 rssi) +{ + USER_RSSI_THOLD userRssiThold; + + /* Send an event to the app */ + userRssiThold.tag = ar->rssi_map[newThreshold].tag; + userRssiThold.rssi = rssi + SIGNAL_QUALITY_NOISE_FLOOR; + A_PRINTF("rssi Threshold range = %d tag = %d rssi = %d\n", newThreshold, + userRssiThold.tag, userRssiThold.rssi); + + ar6000_send_event_to_app(ar, WMI_RSSI_THRESHOLD_EVENTID,(A_UINT8 *)&userRssiThold, sizeof(USER_RSSI_THOLD)); +} + + +void +ar6000_hbChallengeResp_event(AR_SOFTC_T *ar, A_UINT32 cookie, A_UINT32 source) +{ + if (source == APP_HB_CHALLENGE) { + /* Report it to the app in case it wants a positive acknowledgement */ + ar6000_send_event_to_app(ar, WMIX_HB_CHALLENGE_RESP_EVENTID, + (A_UINT8 *)&cookie, sizeof(cookie)); + } else { + /* This would ignore the replys that come in after their due time */ + if (cookie == ar->arHBChallengeResp.seqNum) { + ar->arHBChallengeResp.outstanding = FALSE; + } + } +} + + +void +ar6000_reportError_event(AR_SOFTC_T *ar, WMI_TARGET_ERROR_VAL errorVal) +{ + char *errString[] = { + [WMI_TARGET_PM_ERR_FAIL] "WMI_TARGET_PM_ERR_FAIL", + [WMI_TARGET_KEY_NOT_FOUND] "WMI_TARGET_KEY_NOT_FOUND", + [WMI_TARGET_DECRYPTION_ERR] "WMI_TARGET_DECRYPTION_ERR", + [WMI_TARGET_BMISS] "WMI_TARGET_BMISS", + [WMI_PSDISABLE_NODE_JOIN] "WMI_PSDISABLE_NODE_JOIN" + }; + + A_PRINTF("AR6000 Error on Target. Error = 0x%x\n", errorVal); + + /* One error is reported at a time, and errorval is a bitmask */ + if(errorVal & (errorVal - 1)) + return; + + A_PRINTF("AR6000 Error type = "); + switch(errorVal) + { + case WMI_TARGET_PM_ERR_FAIL: + case WMI_TARGET_KEY_NOT_FOUND: + case WMI_TARGET_DECRYPTION_ERR: + case WMI_TARGET_BMISS: + case WMI_PSDISABLE_NODE_JOIN: + A_PRINTF("%s\n", errString[errorVal]); + break; + default: + A_PRINTF("INVALID\n"); + break; + } + +} + + +void +ar6000_cac_event(AR_SOFTC_T *ar, A_UINT8 ac, A_UINT8 cacIndication, + A_UINT8 statusCode, A_UINT8 *tspecSuggestion) +{ + WMM_TSPEC_IE *tspecIe; + + /* + * This is the TSPEC IE suggestion from AP. + * Suggestion provided by AP under some error + * cases, could be helpful for the host app. + * Check documentation. + */ + tspecIe = (WMM_TSPEC_IE *)tspecSuggestion; + + /* + * What do we do, if we get TSPEC rejection? One thought + * that comes to mind is implictly delete the pstream... + */ + A_PRINTF("AR6000 CAC notification. " + "AC = %d, cacIndication = 0x%x, statusCode = 0x%x\n", + ac, cacIndication, statusCode); +} + +void +ar6000_channel_change_event(AR_SOFTC_T *ar, A_UINT16 oldChannel, + A_UINT16 newChannel) +{ + A_PRINTF("Channel Change notification\nOld Channel: %d, New Channel: %d\n", + oldChannel, newChannel); +} + +#define AR6000_PRINT_BSSID(_pBss) do { \ + A_PRINTF("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",\ + (_pBss)[0],(_pBss)[1],(_pBss)[2],(_pBss)[3],\ + (_pBss)[4],(_pBss)[5]); \ +} while(0) + +void +ar6000_roam_tbl_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_TBL *pTbl) +{ + A_UINT8 i; + + A_PRINTF("ROAM TABLE NO OF ENTRIES is %d ROAM MODE is %d\n", + pTbl->numEntries, pTbl->roamMode); + for (i= 0; i < pTbl->numEntries; i++) { + A_PRINTF("[%d]bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", i, + pTbl->bssRoamInfo[i].bssid[0], pTbl->bssRoamInfo[i].bssid[1], + pTbl->bssRoamInfo[i].bssid[2], + pTbl->bssRoamInfo[i].bssid[3], + pTbl->bssRoamInfo[i].bssid[4], + pTbl->bssRoamInfo[i].bssid[5]); + A_PRINTF("RSSI %d RSSIDT %d LAST RSSI %d UTIL %d ROAM_UTIL %d" + " BIAS %d\n", + pTbl->bssRoamInfo[i].rssi, + pTbl->bssRoamInfo[i].rssidt, + pTbl->bssRoamInfo[i].last_rssi, + pTbl->bssRoamInfo[i].util, + pTbl->bssRoamInfo[i].roam_util, + pTbl->bssRoamInfo[i].bias); + } +} + +void +ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters, WMI_GET_WOW_LIST_REPLY *wow_reply) +{ + A_UINT8 i,j; + + /*Each event now contains exactly one filter, see bug 26613*/ + A_PRINTF("WOW pattern %d of %d patterns\n", wow_reply->this_filter_num, wow_reply->num_filters); + A_PRINTF("wow mode = %s host mode = %s\n", + (wow_reply->wow_mode == 0? "disabled":"enabled"), + (wow_reply->host_mode == 1 ? "awake":"asleep")); + + + /*If there are no patterns, the reply will only contain generic + WoW information. Pattern information will exist only if there are + patterns present. Bug 26716*/ + + /* If this event contains pattern information, display it*/ + if (wow_reply->this_filter_num) { + i=0; + A_PRINTF("id=%d size=%d offset=%d\n", + wow_reply->wow_filters[i].wow_filter_id, + wow_reply->wow_filters[i].wow_filter_size, + wow_reply->wow_filters[i].wow_filter_offset); + A_PRINTF("wow pattern = "); + for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) { + A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_pattern[j]); + } + + A_PRINTF("\nwow mask = "); + for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) { + A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_mask[j]); + } + A_PRINTF("\n"); + } +} + +/* + * Report the Roaming related data collected on the target + */ +void +ar6000_display_roam_time(WMI_TARGET_ROAM_TIME *p) +{ + A_PRINTF("Disconnect Data : BSSID: "); + AR6000_PRINT_BSSID(p->disassoc_bssid); + A_PRINTF(" RSSI %d DISASSOC Time %d NO_TXRX_TIME %d\n", + p->disassoc_bss_rssi,p->disassoc_time, + p->no_txrx_time); + A_PRINTF("Connect Data: BSSID: "); + AR6000_PRINT_BSSID(p->assoc_bssid); + A_PRINTF(" RSSI %d ASSOC Time %d TXRX_TIME %d\n", + p->assoc_bss_rssi,p->assoc_time, + p->allow_txrx_time); + A_PRINTF("Last Data Tx Time (b4 Disassoc) %d "\ + "First Data Tx Time (after Assoc) %d\n", + p->last_data_txrx_time, p->first_data_txrx_time); +} + +void +ar6000_roam_data_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_DATA *p) +{ + switch (p->roamDataType) { + case ROAM_DATA_TIME: + ar6000_display_roam_time(&p->u.roamTime); + break; + default: + break; + } +} + +void +ar6000_bssInfo_event_rx(AR_SOFTC_T *ar, A_UINT8 *datap, int len) +{ + struct sk_buff *skb; + WMI_BSS_INFO_HDR *bih = (WMI_BSS_INFO_HDR *)datap; + + + if (!ar->arMgmtFilter) { + return; + } + if (((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_BEACON) && + (bih->frameType != BEACON_FTYPE)) || + ((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_PROBE_RESP) && + (bih->frameType != PROBERESP_FTYPE))) + { + return; + } + + if ((skb = A_NETBUF_ALLOC_RAW(len)) != NULL) { + + A_NETBUF_PUT(skb, len); + A_MEMCPY(A_NETBUF_DATA(skb), datap, len); + skb->dev = ar->arNetDev; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) + A_MEMCPY(skb_mac_header(skb), A_NETBUF_DATA(skb), 6); +#else + skb->mac.raw = A_NETBUF_DATA(skb); +#endif + skb->ip_summed = CHECKSUM_NONE; + skb->pkt_type = PACKET_OTHERHOST; + skb->protocol = __constant_htons(0x0019); + netif_rx(skb); + } +} + +A_UINT32 wmiSendCmdNum; + +A_STATUS +ar6000_control_tx(void *devt, void *osbuf, HTC_ENDPOINT_ID eid) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + A_STATUS status = A_OK; + struct ar_cookie *cookie = NULL; + int i; + + /* take lock to protect ar6000_alloc_cookie() */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + do { + + AR_DEBUG2_PRINTF("ar_contrstatus = ol_tx: skb=0x%x, len=0x%x eid =%d\n", + (A_UINT32)osbuf, A_NETBUF_LEN(osbuf), eid); + + if (ar->arWMIControlEpFull && (eid == ar->arControlEp)) { + /* control endpoint is full, don't allocate resources, we + * are just going to drop this packet */ + cookie = NULL; + AR_DEBUG_PRINTF(" WMI Control EP full, dropping packet : 0x%X, len:%d \n", + (A_UINT32)osbuf, A_NETBUF_LEN(osbuf)); + } else { + cookie = ar6000_alloc_cookie(ar); + } + + if (cookie == NULL) { + status = A_NO_MEMORY; + break; + } + + if(logWmiRawMsgs) { + A_PRINTF("WMI cmd send, msgNo %d :", wmiSendCmdNum); + for(i = 0; i < a_netbuf_to_len(osbuf); i++) + A_PRINTF("%x ", ((A_UINT8 *)a_netbuf_to_data(osbuf))[i]); + A_PRINTF("\n"); + } + + wmiSendCmdNum++; + + } while (FALSE); + + if (cookie != NULL) { + /* got a structure to send it out on */ + ar->arTxPending[eid]++; + + if (eid != ar->arControlEp) { + ar->arTotalTxDataPending++; + } + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + if (cookie != NULL) { + cookie->arc_bp[0] = (A_UINT32)osbuf; + cookie->arc_bp[1] = 0; + SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt, + cookie, + A_NETBUF_DATA(osbuf), + A_NETBUF_LEN(osbuf), + eid, + AR6K_CONTROL_PKT_TAG); + /* this interface is asynchronous, if there is an error, cleanup will happen in the + * TX completion callback */ + HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt); + status = A_OK; + } + + return status; +} + +/* indicate tx activity or inactivity on a WMI stream */ +void ar6000_indicate_tx_activity(void *devt, A_UINT8 TrafficClass, A_BOOL Active) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + HTC_ENDPOINT_ID eid ; + int i; + + if (ar->arWmiEnabled) { + eid = arAc2EndpointID(ar, TrafficClass); + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + ar->arAcStreamActive[TrafficClass] = Active; + + if (Active) { + /* when a stream goes active, keep track of the active stream with the highest priority */ + + if (ar->arAcStreamPriMap[TrafficClass] > ar->arHiAcStreamActivePri) { + /* set the new highest active priority */ + ar->arHiAcStreamActivePri = ar->arAcStreamPriMap[TrafficClass]; + } + + } else { + /* when a stream goes inactive, we may have to search for the next active stream + * that is the highest priority */ + + if (ar->arHiAcStreamActivePri == ar->arAcStreamPriMap[TrafficClass]) { + + /* the highest priority stream just went inactive */ + + /* reset and search for the "next" highest "active" priority stream */ + ar->arHiAcStreamActivePri = 0; + for (i = 0; i < WMM_NUM_AC; i++) { + if (ar->arAcStreamActive[i]) { + if (ar->arAcStreamPriMap[i] > ar->arHiAcStreamActivePri) { + /* set the new highest active priority */ + ar->arHiAcStreamActivePri = ar->arAcStreamPriMap[i]; + } + } + } + } + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + } else { + /* for mbox ping testing, the traffic class is mapped directly as a stream ID, + * see handling of AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE in ioctl.c */ + eid = (HTC_ENDPOINT_ID)TrafficClass; + } + + /* notify HTC, this may cause credit distribution changes */ + + HTCIndicateActivityChange(ar->arHtcTarget, + eid, + Active); + +} + +module_init(ar6000_init_module); +module_exit(ar6000_cleanup_module); + +/* Init cookie queue */ +static void +ar6000_cookie_init(AR_SOFTC_T *ar) +{ + A_UINT32 i; + + ar->arCookieList = NULL; + A_MEMZERO(s_ar_cookie_mem, sizeof(s_ar_cookie_mem)); + + for (i = 0; i < MAX_COOKIE_NUM; i++) { + ar6000_free_cookie(ar, &s_ar_cookie_mem[i]); + } +} + +/* cleanup cookie queue */ +static void +ar6000_cookie_cleanup(AR_SOFTC_T *ar) +{ + /* It is gone .... */ + ar->arCookieList = NULL; +} + +/* Init cookie queue */ +static void +ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie) +{ + /* Insert first */ + A_ASSERT(ar != NULL); + A_ASSERT(cookie != NULL); + cookie->arc_list_next = ar->arCookieList; + ar->arCookieList = cookie; +} + +/* cleanup cookie queue */ +static struct ar_cookie * +ar6000_alloc_cookie(AR_SOFTC_T *ar) +{ + struct ar_cookie *cookie; + + cookie = ar->arCookieList; + if(cookie != NULL) + { + ar->arCookieList = cookie->arc_list_next; + } + + return cookie; +} + +#ifdef SEND_EVENT_TO_APP +/* + * This function is used to send event which come from taget to + * the application. The buf which send to application is include + * the event ID and event content. + */ +#define EVENT_ID_LEN 2 +void ar6000_send_event_to_app(AR_SOFTC_T *ar, A_UINT16 eventId, + A_UINT8 *datap, int len) +{ + +#if (WIRELESS_EXT >= 15) + +/* note: IWEVCUSTOM only exists in wireless extensions after version 15 */ + + char *buf; + A_UINT16 size; + union iwreq_data wrqu; + + if (!datap) + return; + + size = len + EVENT_ID_LEN; + + if (size > IW_CUSTOM_MAX) { + AR_DEBUG_PRINTF("WMI event ID : 0x%4.4X, len = %d too big for IWEVCUSTOM (max=%d) \n", + eventId, size, IW_CUSTOM_MAX); + return; + } + + buf = A_MALLOC_NOWAIT(size); + if (NULL == buf){ + AR_DEBUG_PRINTF("%s: failed to allocate %d bytes\n", __func__, size); + return; + } + + A_MEMZERO(buf, size); + A_MEMCPY(buf, &eventId, EVENT_ID_LEN); + A_MEMCPY(buf+EVENT_ID_LEN, datap, len); + + //AR_DEBUG_PRINTF("event ID = %d,len = %d\n",*(A_UINT16*)buf, size); + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = size; + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + + A_FREE(buf); +#endif + + +} + +/* + * This function is used to send events larger than 256 bytes + * to the application. The buf which is sent to application + * includes the event ID and event content. + */ +void ar6000_send_generic_event_to_app(AR_SOFTC_T *ar, A_UINT16 eventId, + A_UINT8 *datap, int len) +{ + +#if (WIRELESS_EXT >= 18) + +/* IWEVGENIE exists in wireless extensions version 18 onwards */ + + char *buf; + A_UINT16 size; + union iwreq_data wrqu; + + size = len + EVENT_ID_LEN; + + if (size > IW_GENERIC_IE_MAX) { + AR_DEBUG_PRINTF("WMI event ID : 0x%4.4X, len = %d too big for IWEVGENIE (max=%d) \n", + eventId, size, IW_GENERIC_IE_MAX); + return; + } + + buf = A_MALLOC_NOWAIT(size); + if (NULL == buf){ + AR_DEBUG_PRINTF("%s: failed to allocate %d bytes\n", __func__, size); + return; + } + + A_MEMZERO(buf, size); + A_MEMCPY(buf, &eventId, EVENT_ID_LEN); + A_MEMCPY(buf+EVENT_ID_LEN, datap, len); + + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = size; + wireless_send_event(ar->arNetDev, IWEVGENIE, &wrqu, buf); + + A_FREE(buf); + +#endif /* (WIRELESS_EXT >= 18) */ + +} +#endif /* SEND_EVENT_TO_APP */ + + +void +ar6000_tx_retry_err_event(void *devt) +{ + AR_DEBUG2_PRINTF("Tx retries reach maximum!\n"); +} + +void +ar6000_snrThresholdEvent_rx(void *devt, WMI_SNR_THRESHOLD_VAL newThreshold, A_UINT8 snr) +{ + WMI_SNR_THRESHOLD_EVENT event; + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + event.range = newThreshold; + event.snr = snr; + + ar6000_send_event_to_app(ar, WMI_SNR_THRESHOLD_EVENTID, (A_UINT8 *)&event, + sizeof(WMI_SNR_THRESHOLD_EVENT)); +} + +void +ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL newThreshold, A_UINT8 lq) +{ + AR_DEBUG2_PRINTF("lq threshold range %d, lq %d\n", newThreshold, lq); +} + + + +A_UINT32 +a_copy_to_user(void *to, const void *from, A_UINT32 n) +{ + return(copy_to_user(to, from, n)); +} + +A_UINT32 +a_copy_from_user(void *to, const void *from, A_UINT32 n) +{ + return(copy_from_user(to, from, n)); +} + + +A_STATUS +ar6000_get_driver_cfg(struct net_device *dev, + A_UINT16 cfgParam, + void *result) +{ + + A_STATUS ret = 0; + + switch(cfgParam) + { + case AR6000_DRIVER_CFG_GET_WLANNODECACHING: + *((A_UINT32 *)result) = wlanNodeCaching; + break; + case AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS: + *((A_UINT32 *)result) = logWmiRawMsgs; + break; + default: + ret = EINVAL; + break; + } + + return ret; +} + +void +ar6000_keepalive_rx(void *devt, A_UINT8 configured) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arKeepaliveConfigured = configured; + wake_up(&arEvent); +} + +void +ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID, WMI_PMKID *pmkidList, + A_UINT8 *bssidList) +{ + A_UINT8 i, j; + + A_PRINTF("Number of Cached PMKIDs is %d\n", numPMKID); + + for (i = 0; i < numPMKID; i++) { + A_PRINTF("\nBSSID %d ", i); + for (j = 0; j < ATH_MAC_LEN; j++) { + A_PRINTF("%2.2x", bssidList[j]); + } + bssidList += (ATH_MAC_LEN + WMI_PMKID_LEN); + A_PRINTF("\nPMKID %d ", i); + for (j = 0; j < WMI_PMKID_LEN; j++) { + A_PRINTF("%2.2x", pmkidList->pmkid[j]); + } + pmkidList = (WMI_PMKID *)((A_UINT8 *)pmkidList + ATH_MAC_LEN + + WMI_PMKID_LEN); + } +} + +void ar6000_pspoll_event(AR_SOFTC_T *ar,A_UINT8 aid) +{ + sta_t *conn=NULL; + A_BOOL isPsqEmpty = FALSE; + + conn = ieee80211_find_conn_for_aid(ar, aid); + + /* If the PS q for this STA is not empty, dequeue and send a pkt from + * the head of the q. Also update the More data bit in the WMI_DATA_HDR + * if there are more pkts for this STA in the PS q. If there are no more + * pkts for this STA, update the PVB for this STA. + */ + A_MUTEX_LOCK(&conn->psqLock); + isPsqEmpty = A_NETBUF_QUEUE_EMPTY(&conn->psq); + A_MUTEX_UNLOCK(&conn->psqLock); + + if (isPsqEmpty) { + /* TODO:No buffered pkts for this STA. Send out a NULL data frame */ + } else { + struct sk_buff *skb = NULL; + + A_MUTEX_LOCK(&conn->psqLock); + skb = A_NETBUF_DEQUEUE(&conn->psq); + A_MUTEX_UNLOCK(&conn->psqLock); + /* Set the STA flag to PSPolled, so that the frame will go out */ + STA_SET_PS_POLLED(conn); + ar6000_data_tx(skb, ar->arNetDev); + STA_CLR_PS_POLLED(conn); + + /* Clear the PVB for this STA if the queue has become empty */ + A_MUTEX_LOCK(&conn->psqLock); + isPsqEmpty = A_NETBUF_QUEUE_EMPTY(&conn->psq); + A_MUTEX_UNLOCK(&conn->psqLock); + + if (isPsqEmpty) { + wmi_set_pvb_cmd(ar->arWmi, conn->aid, 0); + } + } +} + +void ar6000_dtimexpiry_event(AR_SOFTC_T *ar) +{ + A_BOOL isMcastQueued = FALSE; + struct sk_buff *skb = NULL; + + A_MUTEX_LOCK(&ar->mcastpsqLock); + isMcastQueued = A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq); + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + + A_ASSERT(isMcastQueued == FALSE); + + /* Flush the mcast psq to the target */ + /* Set the STA flag to DTIMExpired, so that the frame will go out */ + ar->DTIMExpired = TRUE; + + A_MUTEX_LOCK(&ar->mcastpsqLock); + while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) { + skb = A_NETBUF_DEQUEUE(&ar->mcastpsq); + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + + ar6000_data_tx(skb, ar->arNetDev); + + A_MUTEX_LOCK(&ar->mcastpsqLock); + } + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + + /* Reset the DTIMExpired flag back to 0 */ + ar->DTIMExpired = FALSE; + + /* Clear the LSB of the BitMapCtl field of the TIM IE */ + wmi_set_pvb_cmd(ar->arWmi, MCAST_AID, 0); +} + +#ifdef USER_KEYS +static A_STATUS + +ar6000_reinstall_keys(AR_SOFTC_T *ar, A_UINT8 key_op_ctrl) +{ + A_STATUS status = A_OK; + struct ieee80211req_key *uik = &ar->user_saved_keys.ucast_ik; + struct ieee80211req_key *bik = &ar->user_saved_keys.bcast_ik; + CRYPTO_TYPE keyType = ar->user_saved_keys.keyType; + + if (IEEE80211_CIPHER_CCKM_KRK != uik->ik_type) { + if (NONE_CRYPT == keyType) { + goto _reinstall_keys_out; + } + + if (uik->ik_keylen) { + status = wmi_addKey_cmd(ar->arWmi, uik->ik_keyix, + ar->user_saved_keys.keyType, PAIRWISE_USAGE, + uik->ik_keylen, (A_UINT8 *)&uik->ik_keyrsc, + uik->ik_keydata, key_op_ctrl, uik->ik_macaddr, SYNC_BEFORE_WMIFLAG); + } + + } else { + status = wmi_add_krk_cmd(ar->arWmi, uik->ik_keydata); + } + + if (IEEE80211_CIPHER_CCKM_KRK != bik->ik_type) { + if (NONE_CRYPT == keyType) { + goto _reinstall_keys_out; + } + + if (bik->ik_keylen) { + status = wmi_addKey_cmd(ar->arWmi, bik->ik_keyix, + ar->user_saved_keys.keyType, GROUP_USAGE, + bik->ik_keylen, (A_UINT8 *)&bik->ik_keyrsc, + bik->ik_keydata, key_op_ctrl, bik->ik_macaddr, NO_SYNC_WMIFLAG); + } + } else { + status = wmi_add_krk_cmd(ar->arWmi, bik->ik_keydata); + } + +_reinstall_keys_out: + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT; + ar->user_key_ctrl = 0; + + return status; +} +#endif /* USER_KEYS */ + + +void +ar6000_dset_open_req( + void *context, + A_UINT32 id, + A_UINT32 targHandle, + A_UINT32 targReplyFn, + A_UINT32 targReplyArg) +{ +} + +void +ar6000_dset_close( + void *context, + A_UINT32 access_cookie) +{ + return; +} + +void +ar6000_dset_data_req( + void *context, + A_UINT32 accessCookie, + A_UINT32 offset, + A_UINT32 length, + A_UINT32 targBuf, + A_UINT32 targReplyFn, + A_UINT32 targReplyArg) +{ +} + +int +ar6000_ap_mode_profile_commit(struct ar6_softc *ar) +{ + WMI_CONNECT_CMD p; + struct ieee80211req_key *ik; + CRYPTO_TYPE keyType = NONE_CRYPT; + + /* No change in AP's profile configuration */ + if(ar->ap_profile_flag==0) { + A_PRINTF("COMMIT: No change in profile!!!\n"); + return -ENODATA; + } + + if(!ar->arSsidLen) { + A_PRINTF("SSID not set!!!\n"); + return -ECHRNG; + } + + if(!ar->arChannelHint) { + /* Without channel info, can't start AP */ + A_PRINTF("Channel not set!!!\n"); + return -ECHRNG; + } + + if(ar->arPairwiseCrypto != ar->arGroupCrypto) { + A_PRINTF("Mixed cipher not supported in AP mode\n"); + return -EOPNOTSUPP; + } + + switch(ar->arAuthMode) { + case NONE_AUTH: + if((ar->arPairwiseCrypto != NONE_CRYPT) && + (ar->arPairwiseCrypto != WEP_CRYPT)) { + A_PRINTF("Cipher not supported in AP mode Open auth\n"); + return -EOPNOTSUPP; + } + break; + case WPA_PSK_AUTH: + if(ar->arPairwiseCrypto != TKIP_CRYPT) { + A_PRINTF("Cipher not supported in AP mode WPA\n"); + return -EOPNOTSUPP; + } + break; + case WPA2_PSK_AUTH: + if(ar->arPairwiseCrypto != AES_CRYPT) { + A_PRINTF("Cipher not supported in AP mode WPA2\n"); + return -EOPNOTSUPP; + } + break; + case WPA_AUTH: + case WPA2_AUTH: + case WPA_AUTH_CCKM: + case WPA2_AUTH_CCKM: + A_PRINTF("This key mgmt type not supported in AP mode\n"); + return -EOPNOTSUPP; + } + + /* Update the arNetworkType */ + ar->arNetworkType = ar->arNextMode; + + A_MEMZERO(&p,sizeof(p)); + p.ssidLength = ar->arSsidLen; + A_MEMCPY(p.ssid,ar->arSsid,p.ssidLength); + p.channel = ar->arChannelHint; + p.networkType = ar->arNetworkType; + + p.dot11AuthMode = ar->arDot11AuthMode; + p.authMode = ar->arAuthMode; + p.pairwiseCryptoType = ar->arPairwiseCrypto; + p.pairwiseCryptoLen = ar->arPairwiseCryptoLen; + p.groupCryptoType = ar->arGroupCrypto; + p.groupCryptoLen = ar->arGroupCryptoLen; + p.ctrl_flags = ar->arConnectCtrlFlags; + + wmi_ap_profile_commit(ar->arWmi, &p); + ar->arConnected = TRUE; + ar->ap_profile_flag = 0; + + switch(ar->arAuthMode) { + case NONE_AUTH: + if(ar->arPairwiseCrypto == WEP_CRYPT) { + ar6000_install_static_wep_keys(ar); + } + break; + case WPA_PSK_AUTH: + case WPA2_PSK_AUTH: + ik = &ar->ap_mode_bkey; + switch (ik->ik_type) { + case IEEE80211_CIPHER_TKIP: + keyType = TKIP_CRYPT; + break; + case IEEE80211_CIPHER_AES_CCM: + keyType = AES_CRYPT; + break; + default: + goto skip_key; + } + wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, GROUP_USAGE, + ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc, + ik->ik_keydata, KEY_OP_INIT_VAL, ik->ik_macaddr, + SYNC_BOTH_WMIFLAG); + + break; + } + +skip_key: + return 0; +} + +A_STATUS +ar6000_ap_mode_get_wpa_ie(struct ar6_softc *ar, struct ieee80211req_wpaie *wpaie) +{ + sta_t *conn = NULL; + conn = ieee80211_find_conn(ar, wpaie->wpa_macaddr); + + A_MEMZERO(wpaie->wpa_ie, IEEE80211_MAX_IE); + A_MEMZERO(wpaie->rsn_ie, IEEE80211_MAX_IE); + + if(conn) { + A_MEMCPY(wpaie->wpa_ie, conn->wpa_ie, IEEE80211_MAX_IE); + } + + return 0; +} + +A_STATUS +is_iwioctl_allowed(A_UINT8 mode, A_UINT16 cmd) +{ + if(cmd >= SIOCSIWCOMMIT && cmd <= SIOCGIWPOWER) { + cmd -= SIOCSIWCOMMIT; + if(sioctl_filter[cmd] == 0xFF) return A_OK; + if(sioctl_filter[cmd] & mode) return A_OK; + } else if(cmd >= SIOCIWFIRSTPRIV && cmd <= (SIOCIWFIRSTPRIV+30)) { + cmd -= SIOCIWFIRSTPRIV; + if(pioctl_filter[cmd] == 0xFF) return A_OK; + if(pioctl_filter[cmd] & mode) return A_OK; + } else { + return A_ERROR; + } + return A_ENOTSUP; +} + +A_STATUS +is_xioctl_allowed(A_UINT8 mode, int cmd) +{ + if(sizeof(xioctl_filter)-1 < cmd) { + A_PRINTF("Filter for this cmd=%d not defined\n",cmd); + return 0; + } + if(xioctl_filter[cmd] == 0xFF) return A_OK; + if(xioctl_filter[cmd] & mode) return A_OK; + return A_ERROR; +} +void ar6000_peer_event( + void *context, + A_UINT8 eventCode, + A_UINT8 *macAddr) +{ + A_UINT8 pos; + + for (pos=0;pos<6;pos++) + printk("%02x: ",*(macAddr+pos)); + printk("\n"); +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6000_drv.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6000_drv.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6000_drv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6000_drv.h 2010-08-11 00:35:01.000000000 -0400 @@ -0,0 +1,451 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _AR6000_H_ +#define _AR6000_H_ + +#include + + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,17) +#include +#else +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) +#include +#else +#include +#endif +#include +#include +#include + +#include +#include +#include "a_types.h" +#include "a_osapi.h" +#include "htc_api.h" +#include "wmi.h" +#include "a_drv.h" +#include "bmi.h" +#include +#include +#include +#include +#include "gpio_api.h" +#include "gpio.h" +#include +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +#include +#else +#include +#include +#endif +#include "mbox_host_reg.h" +#include "mbox_reg.h" +#include "rtc_reg.h" +#include "ar6000_api.h" +#ifdef CONFIG_HOST_TCMD_SUPPORT +#include +#endif + +#include "targaddrs.h" +#include "dbglog_api.h" +#include "ar6000_diag.h" +#include "common_drv.h" +#include "roaming.h" + +#ifndef __dev_put +#define __dev_put(dev) dev_put(dev) +#endif + + +#define DRIVER_NAME "ar6000" + +#ifdef USER_KEYS + +#define USER_SAVEDKEYS_STAT_INIT 0 +#define USER_SAVEDKEYS_STAT_RUN 1 + +// TODO this needs to move into the AR_SOFTC struct +struct USER_SAVEDKEYS { + struct ieee80211req_key ucast_ik; + struct ieee80211req_key bcast_ik; + CRYPTO_TYPE keyType; + A_BOOL keyOk; +}; +#endif + +#define DBG_INFO 0x00000001 +#define DBG_ERROR 0x00000002 +#define DBG_WARNING 0x00000004 +#define DBG_SDIO 0x00000008 +#define DBG_HIF 0x00000010 +#define DBG_HTC 0x00000020 +#define DBG_WMI 0x00000040 +#define DBG_WMI2 0x00000080 +#define DBG_DRIVER 0x00000100 + +#define DBG_DEFAULTS (DBG_ERROR|DBG_WARNING) + + +#ifdef DEBUG +#define AR_DEBUG_PRINTF(args...) if (debugdriver) A_PRINTF(args); +#define AR_DEBUG2_PRINTF(args...) if (debugdriver >= 2) A_PRINTF(args); +extern int debugdriver; +#else +#define AR_DEBUG_PRINTF(args...) +#define AR_DEBUG2_PRINTF(args...) +#endif + +A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); +A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAX_AR6000 1 +#define AR6000_MAX_RX_BUFFERS 16 +#define AR6000_BUFFER_SIZE 1664 +#define AR6000_TX_TIMEOUT 10 +#define AR6000_ETH_ADDR_LEN 6 +#define AR6000_MAX_ENDPOINTS 4 +#define MAX_NODE_NUM 15 +#define MAX_COOKIE_NUM 150 +#define AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT 1 +#define AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT 1 +#define A_DISCONNECT_TIMER_INTERVAL 5 * 1000 + +enum { + DRV_HB_CHALLENGE = 0, + APP_HB_CHALLENGE +}; + +/* HTC RAW streams */ +typedef enum _HTC_RAW_STREAM_ID { + HTC_RAW_STREAM_NOT_MAPPED = -1, + HTC_RAW_STREAM_0 = 0, + HTC_RAW_STREAM_1 = 1, + HTC_RAW_STREAM_2 = 2, + HTC_RAW_STREAM_3 = 3, + HTC_RAW_STREAM_NUM_MAX +} HTC_RAW_STREAM_ID; + +#define RAW_HTC_READ_BUFFERS_NUM 4 +#define RAW_HTC_WRITE_BUFFERS_NUM 4 + +typedef struct { + int currPtr; + int length; + unsigned char data[AR6000_BUFFER_SIZE]; + HTC_PACKET HTCPacket; +} raw_htc_buffer; + +#ifdef CONFIG_HOST_TCMD_SUPPORT +/* + * add TCMD_MODE besides wmi and bypasswmi + * in TCMD_MODE, only few TCMD releated wmi commands + * counld be hanlder + */ +enum { + AR6000_WMI_MODE = 0, + AR6000_BYPASS_MODE, + AR6000_TCMD_MODE, + AR6000_WLAN_MODE +}; +#endif /* CONFIG_HOST_TCMD_SUPPORT */ + +struct ar_wep_key { + A_UINT8 arKeyIndex; + A_UINT8 arKeyLen; + A_UINT8 arKey[64]; +} ; + +struct ar_node_mapping { + A_UINT8 macAddress[6]; + A_UINT8 epId; + A_UINT8 txPending; +}; + +struct ar_cookie { + A_UINT32 arc_bp[2]; /* Must be first field */ + HTC_PACKET HtcPkt; /* HTC packet wrapper */ + struct ar_cookie *arc_list_next; +}; + +struct ar_hb_chlng_resp { + A_TIMER timer; + A_UINT32 frequency; + A_UINT32 seqNum; + A_BOOL outstanding; + A_UINT8 missCnt; + A_UINT8 missThres; +}; + +/* Per STA data, used in AP mode */ +/*TODO: All this should move to OS independent dir */ + +#define STA_PWR_MGMT_MASK 0x1 +#define STA_PWR_MGMT_SHIFT 0x0 +#define STA_PWR_MGMT_AWAKE 0x0 +#define STA_PWR_MGMT_SLEEP 0x1 + +#define STA_SET_PWR_SLEEP(sta) (sta->flags |= (STA_PWR_MGMT_MASK << STA_PWR_MGMT_SHIFT)) +#define STA_CLR_PWR_SLEEP(sta) (sta->flags &= ~(STA_PWR_MGMT_MASK << STA_PWR_MGMT_SHIFT)) +#define STA_IS_PWR_SLEEP(sta) ((sta->flags >> STA_PWR_MGMT_SHIFT) & STA_PWR_MGMT_MASK) + +#define STA_PS_POLLED_MASK 0x1 +#define STA_PS_POLLED_SHIFT 0x1 +#define STA_SET_PS_POLLED(sta) (sta->flags |= (STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT)) +#define STA_CLR_PS_POLLED(sta) (sta->flags &= ~(STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT)) +#define STA_IS_PS_POLLED(sta) (sta->flags & (STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT)) + +typedef struct { + A_UINT16 flags; + A_UINT8 mac[ATH_MAC_LEN]; + A_UINT8 aid; + A_UINT8 wpa_ie[IEEE80211_MAX_IE]; + A_NETBUF_QUEUE_T psq; /* power save q */ + A_MUTEX_T psqLock; +} sta_t; + +typedef struct ar6_softc { + struct net_device *arNetDev; /* net_device pointer */ + void *arWmi; + int arTxPending[ENDPOINT_MAX]; + int arTotalTxDataPending; + A_UINT8 arNumDataEndPts; + A_BOOL arWmiEnabled; + A_BOOL arWmiReady; + A_BOOL arConnected; + HTC_HANDLE arHtcTarget; + void *arHifDevice; + spinlock_t arLock; + struct semaphore arSem; + int arRxBuffers[ENDPOINT_MAX]; + int arSsidLen; + u_char arSsid[32]; + A_UINT8 arNextMode; + A_UINT8 arNetworkType; + A_UINT8 arDot11AuthMode; + A_UINT8 arAuthMode; + A_UINT8 arPairwiseCrypto; + A_UINT8 arPairwiseCryptoLen; + A_UINT8 arGroupCrypto; + A_UINT8 arGroupCryptoLen; + A_UINT8 arDefTxKeyIndex; + struct ar_wep_key arWepKeyList[WMI_MAX_KEY_INDEX + 1]; + A_UINT8 arBssid[6]; + A_UINT8 arReqBssid[6]; + A_UINT16 arChannelHint; + A_UINT16 arBssChannel; + A_UINT16 arListenInterval; + struct ar6000_version arVersion; + A_UINT32 arTargetType; + A_INT8 arRssi; + A_UINT8 arTxPwr; + A_BOOL arTxPwrSet; + A_INT32 arBitRate; + struct net_device_stats arNetStats; + struct iw_statistics arIwStats; + A_INT8 arNumChannels; + A_UINT16 arChannelList[32]; + A_UINT32 arRegCode; + A_BOOL statsUpdatePending; + TARGET_STATS arTargetStats; + A_INT8 arMaxRetries; + A_UINT8 arPhyCapability; +#ifdef CONFIG_HOST_TCMD_SUPPORT + A_UINT8 tcmdRxReport; + A_UINT32 tcmdRxTotalPkt; + A_INT32 tcmdRxRssi; + A_UINT32 tcmdPm; + A_UINT32 arTargetMode; + A_UINT32 tcmdRxcrcErrPkt; + A_UINT32 tcmdRxsecErrPkt; +#endif + AR6000_WLAN_STATE arWlanState; + struct ar_node_mapping arNodeMap[MAX_NODE_NUM]; + A_UINT8 arIbssPsEnable; + A_UINT8 arNodeNum; + A_UINT8 arNexEpId; + struct ar_cookie *arCookieList; + A_UINT16 arRateMask; + A_UINT8 arSkipScan; + A_UINT16 arBeaconInterval; + A_BOOL arConnectPending; + A_BOOL arWmmEnabled; + struct ar_hb_chlng_resp arHBChallengeResp; + A_UINT8 arKeepaliveConfigured; + A_UINT32 arMgmtFilter; + HTC_ENDPOINT_ID arAc2EpMapping[WMM_NUM_AC]; + A_BOOL arAcStreamActive[WMM_NUM_AC]; + A_UINT8 arAcStreamPriMap[WMM_NUM_AC]; + A_UINT8 arHiAcStreamActivePri; + A_UINT8 arEp2AcMapping[ENDPOINT_MAX]; + HTC_ENDPOINT_ID arControlEp; +#ifdef HTC_RAW_INTERFACE + HTC_ENDPOINT_ID arRaw2EpMapping[HTC_RAW_STREAM_NUM_MAX]; + HTC_RAW_STREAM_ID arEp2RawMapping[ENDPOINT_MAX]; + // does not need for synchronous sdio request anymore + struct semaphore raw_htc_read_sem[HTC_RAW_STREAM_NUM_MAX]; + struct semaphore raw_htc_write_sem[HTC_RAW_STREAM_NUM_MAX]; + wait_queue_head_t raw_htc_read_queue[HTC_RAW_STREAM_NUM_MAX]; + wait_queue_head_t raw_htc_write_queue[HTC_RAW_STREAM_NUM_MAX]; + raw_htc_buffer *raw_htc_read_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_READ_BUFFERS_NUM]; + raw_htc_buffer *raw_htc_write_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_WRITE_BUFFERS_NUM]; + A_BOOL write_buffer_available[HTC_RAW_STREAM_NUM_MAX]; + A_BOOL read_buffer_available[HTC_RAW_STREAM_NUM_MAX]; +#endif + A_BOOL arNetQueueStopped; + A_BOOL arRawIfInit; + int arDeviceIndex; + COMMON_CREDIT_STATE_INFO arCreditStateInfo; + A_BOOL arWMIControlEpFull; + A_BOOL dbgLogFetchInProgress; + A_UCHAR log_buffer[DBGLOG_HOST_LOG_BUFFER_SIZE]; + A_UINT32 log_cnt; + A_UINT32 dbglog_init_done; + A_UINT32 arConnectCtrlFlags; +#ifdef USER_KEYS + A_INT32 user_savedkeys_stat; + A_UINT32 user_key_ctrl; + struct USER_SAVEDKEYS user_saved_keys; +#endif + A_UINT32 scan_complete; + USER_RSSI_THOLD rssi_map[12]; + A_UINT16 ap_profile_flag; /* AP mode */ + WMI_AP_ACL g_acl; /* AP mode */ + sta_t sta_list[AP_MAX_NUM_STA]; /* AP mode */ + A_UINT8 sta_list_index; /* AP mode */ + struct ieee80211req_key ap_mode_bkey; /* AP mode */ + A_NETBUF_QUEUE_T mcastpsq; /* power save q for Mcast frames */ + A_MUTEX_T mcastpsqLock; + A_BOOL DTIMExpired; /* flag to indicate DTIM expired */ + A_UINT8 intra_bss; /* enable/disable intra bss data forward */ + A_BOOL bIsDestroyProgress; /* flag to indicate ar6k destroy is in progress */ + A_TIMER disconnect_timer; +} AR_SOFTC_T; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +/* Looks like we need this for 2.4 kernels */ +static inline void *netdev_priv(struct net_device *dev) +{ + return(dev->priv); +} +#endif + +#define arAc2EndpointID(ar,ac) (ar)->arAc2EpMapping[(ac)] +#define arSetAc2EndpointIDMap(ar,ac,ep) \ +{ (ar)->arAc2EpMapping[(ac)] = (ep); \ + (ar)->arEp2AcMapping[(ep)] = (ac); } +#define arEndpoint2Ac(ar,ep) (ar)->arEp2AcMapping[(ep)] + +#define arRawIfEnabled(ar) (ar)->arRawIfInit +#define arRawStream2EndpointID(ar,raw) (ar)->arRaw2EpMapping[(raw)] +#define arSetRawStream2EndpointIDMap(ar,raw,ep) \ +{ (ar)->arRaw2EpMapping[(raw)] = (ep); \ + (ar)->arEp2RawMapping[(ep)] = (raw); } +#define arEndpoint2RawStreamID(ar,ep) (ar)->arEp2RawMapping[(ep)] + +struct ar_giwscan_param { + char *current_ev; + char *end_buf; + A_UINT32 bytes_needed; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + struct iw_request_info *info; +#endif +}; + +#define AR6000_STAT_INC(ar, stat) (ar->arNetStats.stat++) + +#define AR6000_SPIN_LOCK(lock, param) do { \ + if (irqs_disabled()) { \ + AR_DEBUG_PRINTF("IRQs disabled:AR6000_LOCK\n"); \ + } \ + spin_lock_bh(lock); \ +} while (0) + +#define AR6000_SPIN_UNLOCK(lock, param) do { \ + if (irqs_disabled()) { \ + AR_DEBUG_PRINTF("IRQs disabled: AR6000_UNLOCK\n"); \ + } \ + spin_unlock_bh(lock); \ +} while (0) + +int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); +int ar6000_ioctl_dispatcher(struct net_device *dev, struct ifreq *rq, int cmd); +void ar6000_gpio_init(void); +void ar6000_init_profile_info(AR_SOFTC_T *ar); +void ar6000_install_static_wep_keys(AR_SOFTC_T *ar); +int ar6000_init(struct net_device *dev); +int ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar); +void ar6000_TxDataCleanup(AR_SOFTC_T *ar); + +#ifdef HTC_RAW_INTERFACE + +#ifndef __user +#define __user +#endif + +int ar6000_htc_raw_open(AR_SOFTC_T *ar); +int ar6000_htc_raw_close(AR_SOFTC_T *ar); +ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar, + HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t count); +ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar, + HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t count); + +#endif /* HTC_RAW_INTERFACE */ + +/* AP mode */ +/*TODO: These routines should be moved to a file that is common across OS */ +sta_t * +ieee80211_find_conn(AR_SOFTC_T *ar, A_UINT8 *node_addr); + +sta_t * +ieee80211_find_conn_for_aid(AR_SOFTC_T *ar, A_UINT8 aid); + +A_UINT8 +remove_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 reason); + +#ifdef __cplusplus +} +#endif + +#endif /* _AR6000_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6000_raw_if.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6000_raw_if.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6000_raw_if.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6000_raw_if.c 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,442 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation; + + * Software distributed under the License is distributed on an "AS + * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or + * implied. See the License for the specific language governing + * rights and limitations under the License. + * + * + * + * Wifi driver for AR6002 + * + * + * + */ + +#include "ar6000_drv.h" + +#ifdef HTC_RAW_INTERFACE + +static void +ar6000_htc_raw_read_cb(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + raw_htc_buffer *busy; + HTC_RAW_STREAM_ID streamID; + + busy = (raw_htc_buffer *)pPacket->pPktContext; + A_ASSERT(busy != NULL); + + if (pPacket->Status == A_ECANCELED) { + /* + * HTC provides A_ECANCELED status when it doesn't want to be refilled + * (probably due to a shutdown) + */ + return; + } + + streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint); + A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED); + +#ifdef CF + if (down_trylock(&ar->raw_htc_read_sem[streamID])) { +#else + if (down_interruptible(&ar->raw_htc_read_sem[streamID])) { +#endif /* CF */ + AR_DEBUG2_PRINTF("Unable to down the semaphore\n"); + } + + A_ASSERT((pPacket->Status != A_OK) || + (pPacket->pBuffer == (busy->data + HTC_HEADER_LEN))); + + busy->length = pPacket->ActualLength + HTC_HEADER_LEN; + busy->currPtr = HTC_HEADER_LEN; + ar->read_buffer_available[streamID] = TRUE; + + up(&ar->raw_htc_read_sem[streamID]); + + /* Signal the waiting process */ + AR_DEBUG2_PRINTF("Waking up the StreamID(%d) read process\n", streamID); + wake_up_interruptible(&ar->raw_htc_read_queue[streamID]); +} + +static void +ar6000_htc_raw_write_cb(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + raw_htc_buffer *free; + HTC_RAW_STREAM_ID streamID; + + free = (raw_htc_buffer *)pPacket->pPktContext; + A_ASSERT(free != NULL); + + if (pPacket->Status == A_ECANCELED) { + /* + * HTC provides A_ECANCELED status when it doesn't want to be refilled + * (probably due to a shutdown) + */ + return; + } + + streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint); + A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED); + +#ifdef CF + if (down_trylock(&ar->raw_htc_write_sem[streamID])) { +#else + if (down_interruptible(&ar->raw_htc_write_sem[streamID])) { +#endif + AR_DEBUG2_PRINTF("Unable to down the semaphore\n"); + } + + A_ASSERT(pPacket->pBuffer == (free->data + HTC_HEADER_LEN)); + + free->length = 0; + ar->write_buffer_available[streamID] = TRUE; + up(&ar->raw_htc_write_sem[streamID]); + + /* Signal the waiting process */ + AR_DEBUG2_PRINTF("Waking up the StreamID(%d) write process\n", streamID); + wake_up_interruptible(&ar->raw_htc_write_queue[streamID]); +} + +/* connect to a service */ +static A_STATUS ar6000_connect_raw_service(AR_SOFTC_T *ar, + HTC_RAW_STREAM_ID StreamID) +{ + A_STATUS status; + HTC_SERVICE_CONNECT_RESP response; + A_UINT8 streamNo; + HTC_SERVICE_CONNECT_REQ connect; + + do { + + A_MEMZERO(&connect,sizeof(connect)); + /* pass the stream ID as meta data to the RAW streams service */ + streamNo = (A_UINT8)StreamID; + connect.pMetaData = &streamNo; + connect.MetaDataLength = sizeof(A_UINT8); + /* these fields are the same for all endpoints */ + connect.EpCallbacks.pContext = ar; + connect.EpCallbacks.EpTxComplete = ar6000_htc_raw_write_cb; + connect.EpCallbacks.EpRecv = ar6000_htc_raw_read_cb; + /* simple interface, we don't need these optional callbacks */ + connect.EpCallbacks.EpRecvRefill = NULL; + connect.EpCallbacks.EpSendFull = NULL; + connect.MaxSendQueueDepth = RAW_HTC_WRITE_BUFFERS_NUM; + + /* connect to the raw streams service, we may be able to get 1 or more + * connections, depending on WHAT is running on the target */ + connect.ServiceID = HTC_RAW_STREAMS_SVC; + + A_MEMZERO(&response,sizeof(response)); + + /* try to connect to the raw stream, it is okay if this fails with + * status HTC_SERVICE_NO_MORE_EP */ + status = HTCConnectService(ar->arHtcTarget, + &connect, + &response); + + if (A_FAILED(status)) { + if (response.ConnectRespCode == HTC_SERVICE_NO_MORE_EP) { + AR_DEBUG_PRINTF("HTC RAW , No more streams allowed \n"); + status = A_OK; + } + break; + } + + /* set endpoint mapping for the RAW HTC streams */ + arSetRawStream2EndpointIDMap(ar,StreamID,response.Endpoint); + + AR_DEBUG_PRINTF("HTC RAW : stream ID: %d, endpoint: %d\n", + StreamID, arRawStream2EndpointID(ar,StreamID)); + + } while (FALSE); + + return status; +} + +int ar6000_htc_raw_open(AR_SOFTC_T *ar) +{ + A_STATUS status; + int streamID, endPt, count2; + raw_htc_buffer *buffer; + HTC_SERVICE_ID servicepriority; + + A_ASSERT(ar->arHtcTarget != NULL); + + /* wait for target */ + status = HTCWaitTarget(ar->arHtcTarget); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF("HTCWaitTarget failed (%d)\n", status); + return -ENODEV; + } + + for (endPt = 0; endPt < ENDPOINT_MAX; endPt++) { + ar->arEp2RawMapping[endPt] = HTC_RAW_STREAM_NOT_MAPPED; + } + + for (streamID = HTC_RAW_STREAM_0; streamID < HTC_RAW_STREAM_NUM_MAX; streamID++) { + /* Initialize the data structures */ + init_MUTEX(&ar->raw_htc_read_sem[streamID]); + init_MUTEX(&ar->raw_htc_write_sem[streamID]); + init_waitqueue_head(&ar->raw_htc_read_queue[streamID]); + init_waitqueue_head(&ar->raw_htc_write_queue[streamID]); + + /* try to connect to the raw service */ + status = ar6000_connect_raw_service(ar,streamID); + + if (A_FAILED(status)) { + break; + } + + if (arRawStream2EndpointID(ar,streamID) == 0) { + break; + } + + for (count2 = 0; count2 < RAW_HTC_READ_BUFFERS_NUM; count2 ++) { + /* Initialize the receive buffers */ + buffer = ar->raw_htc_write_buffer[streamID][count2]; + memset(buffer, 0, sizeof(raw_htc_buffer)); + buffer = ar->raw_htc_read_buffer[streamID][count2]; + memset(buffer, 0, sizeof(raw_htc_buffer)); + + SET_HTC_PACKET_INFO_RX_REFILL(&buffer->HTCPacket, + buffer, + buffer->data, + AR6000_BUFFER_SIZE, + arRawStream2EndpointID(ar,streamID)); + + /* Queue buffers to HTC for receive */ + if ((status = HTCAddReceivePkt(ar->arHtcTarget, &buffer->HTCPacket)) != A_OK) + { + BMIInit(); + return -EIO; + } + } + + for (count2 = 0; count2 < RAW_HTC_WRITE_BUFFERS_NUM; count2 ++) { + /* Initialize the receive buffers */ + buffer = ar->raw_htc_write_buffer[streamID][count2]; + memset(buffer, 0, sizeof(raw_htc_buffer)); + } + + ar->read_buffer_available[streamID] = FALSE; + ar->write_buffer_available[streamID] = TRUE; + } + + if (A_FAILED(status)) { + return -EIO; + } + + AR_DEBUG_PRINTF("HTC RAW, number of streams the target supports: %d \n", streamID); + + servicepriority = HTC_RAW_STREAMS_SVC; /* only 1 */ + + /* set callbacks and priority list */ + HTCSetCreditDistribution(ar->arHtcTarget, + ar, + NULL, /* use default */ + NULL, /* use default */ + &servicepriority, + 1); + + /* Start the HTC component */ + if ((status = HTCStart(ar->arHtcTarget)) != A_OK) { + BMIInit(); + return -EIO; + } + + (ar)->arRawIfInit = TRUE; + + return 0; +} + +int ar6000_htc_raw_close(AR_SOFTC_T *ar) +{ + A_PRINTF("ar6000_htc_raw_close called \n"); + + /* reset the device */ + ar6000_reset_device(ar->arHifDevice, ar->arTargetType, TRUE); + /* Initialize the BMI component */ + BMIInit(); + + HTCStop(ar->arHtcTarget); + + return 0; +} + +raw_htc_buffer * +get_filled_buffer(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID) +{ + int count; + raw_htc_buffer *busy; + + /* Check for data */ + for (count = 0; count < RAW_HTC_READ_BUFFERS_NUM; count ++) { + busy = ar->raw_htc_read_buffer[StreamID][count]; + if (busy->length) { + break; + } + } + if (busy->length) { + ar->read_buffer_available[StreamID] = TRUE; + } else { + ar->read_buffer_available[StreamID] = FALSE; + } + + return busy; +} + +ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t length) +{ + int readPtr; + raw_htc_buffer *busy; + + if (arRawStream2EndpointID(ar,StreamID) == 0) { + AR_DEBUG_PRINTF("StreamID(%d) not connected! \n", StreamID); + return -EFAULT; + } + + if (down_interruptible(&ar->raw_htc_read_sem[StreamID])) { + return -ERESTARTSYS; + } + + busy = get_filled_buffer(ar,StreamID); + while (!ar->read_buffer_available[StreamID]) { + up(&ar->raw_htc_read_sem[StreamID]); + + /* Wait for the data */ + AR_DEBUG2_PRINTF("Sleeping StreamID(%d) read process\n", StreamID); + if (wait_event_interruptible(ar->raw_htc_read_queue[StreamID], + ar->read_buffer_available[StreamID])) + { + return -EINTR; + } + if (down_interruptible(&ar->raw_htc_read_sem[StreamID])) { + return -ERESTARTSYS; + } + busy = get_filled_buffer(ar,StreamID); + } + + /* Read the data */ + readPtr = busy->currPtr; + if (length > busy->length - HTC_HEADER_LEN) { + length = busy->length - HTC_HEADER_LEN; + } + if (copy_to_user(buffer, &busy->data[readPtr], length)) { + up(&ar->raw_htc_read_sem[StreamID]); + return -EFAULT; + } + + busy->currPtr += length; + + up(&ar->raw_htc_read_sem[StreamID]); + + if (busy->currPtr == busy->length) + { + busy->currPtr = 0; + busy->length = 0; + HTC_PACKET_RESET_RX(&busy->HTCPacket); + //AR_DEBUG_PRINTF("raw read ioctl: ep for packet:%d \n", busy->HTCPacket.Endpoint); + HTCAddReceivePkt(ar->arHtcTarget, &busy->HTCPacket); + } + ar->read_buffer_available[StreamID] = FALSE; + + return length; +} + +static raw_htc_buffer * +get_free_buffer(AR_SOFTC_T *ar, HTC_ENDPOINT_ID StreamID) +{ + int count; + raw_htc_buffer *free; + + free = NULL; + for (count = 0; count < RAW_HTC_WRITE_BUFFERS_NUM; count ++) { + free = ar->raw_htc_write_buffer[StreamID][count]; + if (free->length == 0) { + break; + } + } + if (!free->length) { + ar->write_buffer_available[StreamID] = TRUE; + } else { + ar->write_buffer_available[StreamID] = FALSE; + } + + return free; +} + +ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t length) +{ + int writePtr; + raw_htc_buffer *free; + + if (arRawStream2EndpointID(ar,StreamID) == 0) { + AR_DEBUG_PRINTF("StreamID(%d) not connected! \n", StreamID); + return -EFAULT; + } + + if (down_interruptible(&ar->raw_htc_write_sem[StreamID])) { + return -ERESTARTSYS; + } + + /* Search for a free buffer */ + free = get_free_buffer(ar,StreamID); + + /* Check if there is space to write else wait */ + while (!ar->write_buffer_available[StreamID]) { + up(&ar->raw_htc_write_sem[StreamID]); + + /* Wait for buffer to become free */ + AR_DEBUG2_PRINTF("Sleeping StreamID(%d) write process\n", StreamID); + if (wait_event_interruptible(ar->raw_htc_write_queue[StreamID], + ar->write_buffer_available[StreamID])) + { + return -EINTR; + } + if (down_interruptible(&ar->raw_htc_write_sem[StreamID])) { + return -ERESTARTSYS; + } + free = get_free_buffer(ar,StreamID); + } + + /* Send the data */ + writePtr = HTC_HEADER_LEN; + if (length > (AR6000_BUFFER_SIZE - HTC_HEADER_LEN)) { + length = AR6000_BUFFER_SIZE - HTC_HEADER_LEN; + } + + if (copy_from_user(&free->data[writePtr], buffer, length)) { + up(&ar->raw_htc_read_sem[StreamID]); + return -EFAULT; + } + + free->length = length; + + up(&ar->raw_htc_write_sem[StreamID]); + + SET_HTC_PACKET_INFO_TX(&free->HTCPacket, + free, + &free->data[writePtr], + length, + arRawStream2EndpointID(ar,StreamID), + AR6K_DATA_PKT_TAG); + + HTCSendPkt(ar->arHtcTarget,&free->HTCPacket); + + + return length; +} +#endif /* HTC_RAW_INTERFACE */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6k.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6k.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6k.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6k.c 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,1033 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// AR6K device layer that handles register level I/O +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "mbox_host_reg.h" +#include "a_osapi.h" +#include "a_debug.h" +#include "hif.h" +#include "htc_packet.h" +#include "ar6k.h" + +#define MAILBOX_FOR_BLOCK_SIZE 1 + +extern A_UINT32 resetok; + +A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev); + +#define LOCK_AR6K(p) A_MUTEX_LOCK(&(p)->Lock); +#define UNLOCK_AR6K(p) A_MUTEX_UNLOCK(&(p)->Lock); + +void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket) +{ + LOCK_AR6K(pDev); + HTC_PACKET_ENQUEUE(&pDev->RegisterIOList,pPacket); + UNLOCK_AR6K(pDev); +} + +HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev) +{ + HTC_PACKET *pPacket; + + LOCK_AR6K(pDev); + pPacket = HTC_PACKET_DEQUEUE(&pDev->RegisterIOList); + UNLOCK_AR6K(pDev); + + return pPacket; +} + +void DevCleanup(AR6K_DEVICE *pDev) +{ + if (A_IS_MUTEX_VALID(&pDev->Lock)) { + A_MUTEX_DELETE(&pDev->Lock); + } + + if (pDev->HifAttached) { + HIFDetachHTC(pDev->HIFDevice); + pDev->HifAttached = FALSE; + } + +} + +A_STATUS DevSetup(AR6K_DEVICE *pDev) +{ + A_UINT32 mailboxaddrs[AR6K_MAILBOXES]; + A_UINT32 blocksizes[AR6K_MAILBOXES]; + A_STATUS status = A_OK; + int i; + HTC_CALLBACKS htcCallbacks; + + AR_DEBUG_ASSERT(AR6K_IRQ_PROC_REGS_SIZE == 16); + AR_DEBUG_ASSERT(AR6K_IRQ_ENABLE_REGS_SIZE == 4); + + do { + + A_MEMZERO(&htcCallbacks, sizeof(HTC_CALLBACKS)); + /* the device layer handles these */ + htcCallbacks.rwCompletionHandler = DevRWCompletionHandler; + htcCallbacks.dsrHandler = DevDsrHandler; + htcCallbacks.context = pDev; + + status = HIFAttachHTC(pDev->HIFDevice, &htcCallbacks); + + if (A_FAILED(status)) { + break; + } + + pDev->HifAttached = TRUE; + + /* initialize our free list of IO packets */ + INIT_HTC_PACKET_QUEUE(&pDev->RegisterIOList); + A_MUTEX_INIT(&pDev->Lock); + + /* get the addresses for all 4 mailboxes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR, + mailboxaddrs, sizeof(mailboxaddrs)); + + if (status != A_OK) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* carve up register I/O packets (these are for ASYNC register I/O ) */ + for (i = 0; i < AR6K_MAX_REG_IO_BUFFERS; i++) { + HTC_PACKET *pIOPacket; + pIOPacket = &pDev->RegIOBuffers[i].HtcPacket; + SET_HTC_PACKET_INFO_RX_REFILL(pIOPacket, + pDev, + pDev->RegIOBuffers[i].Buffer, + AR6K_REG_IO_BUFFER_SIZE, + 0); /* don't care */ + AR6KFreeIOPacket(pDev,pIOPacket); + } + + /* get the address of the mailbox we are using */ + pDev->MailboxAddress = mailboxaddrs[HTC_MAILBOX]; + + /* get the block sizes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + blocksizes, sizeof(blocksizes)); + + if (status != A_OK) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* note: we actually get the block size of a mailbox other than 0, for SDIO the block + * size on mailbox 0 is artificially set to 1. So we use the block size that is set + * for the other 3 mailboxes */ + pDev->BlockSize = blocksizes[MAILBOX_FOR_BLOCK_SIZE]; + /* must be a power of 2 */ + AR_DEBUG_ASSERT((pDev->BlockSize & (pDev->BlockSize - 1)) == 0); + + /* assemble mask, used for padding to a block */ + pDev->BlockMask = pDev->BlockSize - 1; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("BlockSize: %d, MailboxAddress:0x%X \n", + pDev->BlockSize, pDev->MailboxAddress)); + + pDev->GetPendingEventsFunc = NULL; + /* see if the HIF layer implements the get pending events function */ + HIFConfigureDevice(pDev->HIFDevice, + HIF_DEVICE_GET_PENDING_EVENTS_FUNC, + &pDev->GetPendingEventsFunc, + sizeof(pDev->GetPendingEventsFunc)); + + /* assume we can process HIF interrupt events asynchronously */ + pDev->HifIRQProcessingMode = HIF_DEVICE_IRQ_ASYNC_SYNC; + + /* see if the HIF layer overrides this assumption */ + HIFConfigureDevice(pDev->HIFDevice, + HIF_DEVICE_GET_IRQ_PROC_MODE, + &pDev->HifIRQProcessingMode, + sizeof(pDev->HifIRQProcessingMode)); + + switch (pDev->HifIRQProcessingMode) { + case HIF_DEVICE_IRQ_SYNC_ONLY: + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is SYNC ONLY\n")); + break; + case HIF_DEVICE_IRQ_ASYNC_SYNC: + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is ASYNC and SYNC\n")); + break; + default: + AR_DEBUG_ASSERT(FALSE); + } + + pDev->HifMaskUmaskRecvEvent = NULL; + + /* see if the HIF layer implements the mask/unmask recv events function */ + HIFConfigureDevice(pDev->HIFDevice, + HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC, + &pDev->HifMaskUmaskRecvEvent, + sizeof(pDev->HifMaskUmaskRecvEvent)); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF special overrides : 0x%X , 0x%X\n", + (A_UINT32)pDev->GetPendingEventsFunc, (A_UINT32)pDev->HifMaskUmaskRecvEvent)); + + status = DevDisableInterrupts(pDev); + + } while (FALSE); + + if (A_FAILED(status)) { + if (pDev->HifAttached) { + HIFDetachHTC(pDev->HIFDevice); + pDev->HifAttached = FALSE; + } + } + + return status; + +} + +A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev) +{ + A_STATUS status; + AR6K_IRQ_ENABLE_REGISTERS regs; + + LOCK_AR6K(pDev); + + /* Enable all the interrupts except for the internal AR6000 CPU interrupt */ + pDev->IrqEnableRegisters.int_status_enable = INT_STATUS_ENABLE_ERROR_SET(0x01) | + INT_STATUS_ENABLE_CPU_SET(0x01) | + INT_STATUS_ENABLE_COUNTER_SET(0x01); + + if (NULL == pDev->GetPendingEventsFunc) { + pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } else { + /* The HIF layer provided us with a pending events function which means that + * the detection of pending mbox messages is handled in the HIF layer. + * This is the case for the SPI2 interface. + * In the normal case we enable MBOX interrupts, for the case + * with HIFs that offer this mechanism, we keep these interrupts + * masked */ + pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } + + + /* Set up the CPU Interrupt Status Register */ + pDev->IrqEnableRegisters.cpu_int_status_enable = CPU_INT_STATUS_ENABLE_BIT_SET(0x00); + + /* Set up the Error Interrupt Status Register */ + pDev->IrqEnableRegisters.error_status_enable = + ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(0x01) | + ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(0x01); + + /* Set up the Counter Interrupt Status Register (only for debug interrupt to catch fatal errors) */ + pDev->IrqEnableRegisters.counter_int_status_enable = + COUNTER_INT_STATUS_ENABLE_BIT_SET(AR6K_TARGET_DEBUG_INTR_MASK); + + /* copy into our temp area */ + A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE); + + UNLOCK_AR6K(pDev); + +/* ATHENV */ +#ifdef ANDROID_ENV + mdelay(100); +#endif +/* ATHENV */ + /* always synchronous */ + status = HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + ®s.int_status_enable, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + /* Can't write it for some reason */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Failed to update interrupt control registers err: %d\n", status)); + + } + + return status; +} + +A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev) +{ + AR6K_IRQ_ENABLE_REGISTERS regs; + + LOCK_AR6K(pDev); + /* Disable all interrupts */ + pDev->IrqEnableRegisters.int_status_enable = 0; + pDev->IrqEnableRegisters.cpu_int_status_enable = 0; + pDev->IrqEnableRegisters.error_status_enable = 0; + pDev->IrqEnableRegisters.counter_int_status_enable = 0; + /* copy into our temp area */ + A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE); + + UNLOCK_AR6K(pDev); + + /* always synchronous */ + return HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + ®s.int_status_enable, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_SYNC_BYTE_INC, + NULL); +} + +/* enable device interrupts */ +A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev) +{ + /* for good measure, make sure interrupt are disabled before unmasking at the HIF + * layer. + * The rationale here is that between device insertion (where we clear the interrupts the first time) + * and when HTC is finally ready to handle interrupts, other software can perform target "soft" resets. + * The AR6K interrupt enables reset back to an "enabled" state when this happens. + * */ + DevDisableInterrupts(pDev); + + /* Unmask the host controller interrupts */ + HIFUnMaskInterrupt(pDev->HIFDevice); + + return DevEnableInterrupts(pDev); +} + +/* disable all device interrupts */ +A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev) +{ + /* mask the interrupt at the HIF layer, we don't want a stray interrupt taken while + * we zero out our shadow registers in DevDisableInterrupts()*/ + HIFMaskInterrupt(pDev->HIFDevice); + + return DevDisableInterrupts(pDev); +} + +/* callback when our fetch to enable/disable completes */ +static void DevDoEnableDisableRecvAsyncHandler(void *Context, HTC_PACKET *pPacket) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDoEnableDisableRecvAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); + + if (A_FAILED(pPacket->Status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" Failed to disable receiver, status:%d \n", pPacket->Status)); + } + /* free this IO packet */ + AR6KFreeIOPacket(pDev,pPacket); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDoEnableDisableRecvAsyncHandler \n")); +} + +/* disable packet reception (used in case the host runs out of buffers) + * this is the "override" method when the HIF reports another methods to + * disable recv events */ +static A_STATUS DevDoEnableDisableRecvOverride(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode) +{ + A_STATUS status = A_OK; + HTC_PACKET *pIOPacket = NULL; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("DevDoEnableDisableRecvOverride: Enable:%d Mode:%d\n", + EnableRecv,AsyncMode)); + + do { + + if (AsyncMode) { + + pIOPacket = AR6KAllocIOPacket(pDev); + + if (NULL == pIOPacket) { + status = A_NO_MEMORY; + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* stick in our completion routine when the I/O operation completes */ + pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler; + pIOPacket->pContext = pDev; + + /* call the HIF layer override and do this asynchronously */ + status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice, + EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV, + pIOPacket); + break; + } + + /* if we get here we are doing it synchronously */ + status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice, + EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV, + NULL); + + } while (FALSE); + + if (A_FAILED(status) && (pIOPacket != NULL)) { + AR6KFreeIOPacket(pDev,pIOPacket); + } + + return status; +} + +/* disable packet reception (used in case the host runs out of buffers) + * this is the "normal" method using the interrupt enable registers through + * the host I/F */ +static A_STATUS DevDoEnableDisableRecvNormal(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode) +{ + A_STATUS status = A_OK; + HTC_PACKET *pIOPacket = NULL; + AR6K_IRQ_ENABLE_REGISTERS regs; + + /* take the lock to protect interrupt enable shadows */ + LOCK_AR6K(pDev); + + if (EnableRecv) { + pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } else { + pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } + + /* copy into our temp area */ + A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE); + UNLOCK_AR6K(pDev); + + do { + + if (AsyncMode) { + + pIOPacket = AR6KAllocIOPacket(pDev); + + if (NULL == pIOPacket) { + status = A_NO_MEMORY; + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* copy values to write to our async I/O buffer */ + A_MEMCPY(pIOPacket->pBuffer,®s,AR6K_IRQ_ENABLE_REGS_SIZE); + + /* stick in our completion routine when the I/O operation completes */ + pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler; + pIOPacket->pContext = pDev; + + /* write it out asynchronously */ + HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + pIOPacket->pBuffer, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_ASYNC_BYTE_INC, + pIOPacket); + break; + } + + /* if we get here we are doing it synchronously */ + + status = HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + ®s.int_status_enable, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_SYNC_BYTE_INC, + NULL); + + } while (FALSE); + + if (A_FAILED(status) && (pIOPacket != NULL)) { + AR6KFreeIOPacket(pDev,pIOPacket); + } + + return status; +} + + +A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode) +{ + if (NULL == pDev->HifMaskUmaskRecvEvent) { + return DevDoEnableDisableRecvNormal(pDev,FALSE,AsyncMode); + } else { + return DevDoEnableDisableRecvOverride(pDev,FALSE,AsyncMode); + } +} + +A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode) +{ + if (NULL == pDev->HifMaskUmaskRecvEvent) { + return DevDoEnableDisableRecvNormal(pDev,TRUE,AsyncMode); + } else { + return DevDoEnableDisableRecvOverride(pDev,TRUE,AsyncMode); + } +} + +void DevDumpRegisters(AR6K_IRQ_PROC_REGISTERS *pIrqProcRegs, + AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs) +{ + + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("\n<------- Register Table -------->\n")); + + if (pIrqProcRegs != NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Int Status: 0x%x\n",pIrqProcRegs->host_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("CPU Int Status: 0x%x\n",pIrqProcRegs->cpu_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Error Int Status: 0x%x\n",pIrqProcRegs->error_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Counter Int Status: 0x%x\n",pIrqProcRegs->counter_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Mbox Frame: 0x%x\n",pIrqProcRegs->mbox_frame)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Rx Lookahead Valid: 0x%x\n",pIrqProcRegs->rx_lookahead_valid)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Rx Lookahead 0: 0x%x\n",pIrqProcRegs->rx_lookahead[0])); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Rx Lookahead 1: 0x%x\n",pIrqProcRegs->rx_lookahead[1])); + } + + if (pIrqEnableRegs != NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Int Status Enable: 0x%x\n",pIrqEnableRegs->int_status_enable)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, + ("Counter Int Status Enable: 0x%x\n",pIrqEnableRegs->counter_int_status_enable)); + AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("<------------------------------->\n")); + } +} + + +#ifdef MBOXHW_UNIT_TEST + + +/* This is a mailbox hardware unit test that must be called in a schedulable context + * This test is very simple, it will send a list of buffers with a counting pattern + * and the target will invert the data and send the message back + * + * the unit test has the following constraints: + * + * The target has at least 8 buffers of 256 bytes each. The host will send + * the following pattern of buffers in rapid succession : + * + * 1 buffer - 128 bytes + * 1 buffer - 256 bytes + * 1 buffer - 512 bytes + * 1 buffer - 1024 bytes + * + * The host will send the buffers to one mailbox and wait for buffers to be reflected + * back from the same mailbox. The target sends the buffers FIFO order. + * Once the final buffer has been received for a mailbox, the next mailbox is tested. + * + * + * Note: To simplifythe test , we assume that the chosen buffer sizes + * will fall on a nice block pad + * + * It is expected that higher-order tests will be written to stress the mailboxes using + * a message-based protocol (with some performance timming) that can create more + * randomness in the packets sent over mailboxes. + * + * */ + +#define A_ROUND_UP_PWR2(x, align) (((int) (x) + ((align)-1)) & ~((align)-1)) + +#define BUFFER_BLOCK_PAD 128 + +#if 0 +#define BUFFER1 128 +#define BUFFER2 256 +#define BUFFER3 512 +#define BUFFER4 1024 +#endif + +#if 1 +#define BUFFER1 80 +#define BUFFER2 200 +#define BUFFER3 444 +#define BUFFER4 800 +#endif + +#define TOTAL_BYTES (A_ROUND_UP_PWR2(BUFFER1,BUFFER_BLOCK_PAD) + \ + A_ROUND_UP_PWR2(BUFFER2,BUFFER_BLOCK_PAD) + \ + A_ROUND_UP_PWR2(BUFFER3,BUFFER_BLOCK_PAD) + \ + A_ROUND_UP_PWR2(BUFFER4,BUFFER_BLOCK_PAD) ) + +#define TEST_BYTES (BUFFER1 + BUFFER2 + BUFFER3 + BUFFER4) + +#define TEST_CREDITS_RECV_TIMEOUT 100 + +static A_UINT8 g_Buffer[TOTAL_BYTES]; +static A_UINT32 g_MailboxAddrs[AR6K_MAILBOXES]; +static A_UINT32 g_BlockSizes[AR6K_MAILBOXES]; + +#define BUFFER_PROC_LIST_DEPTH 4 + +typedef struct _BUFFER_PROC_LIST{ + A_UINT8 *pBuffer; + A_UINT32 length; +}BUFFER_PROC_LIST; + + +#define PUSH_BUFF_PROC_ENTRY(pList,len,pCurrpos) \ +{ \ + (pList)->pBuffer = (pCurrpos); \ + (pList)->length = (len); \ + (pCurrpos) += (len); \ + (pList)++; \ +} + +/* a simple and crude way to send different "message" sizes */ +static void AssembleBufferList(BUFFER_PROC_LIST *pList) +{ + A_UINT8 *pBuffer = g_Buffer; + +#if BUFFER_PROC_LIST_DEPTH < 4 +#error "Buffer processing list depth is not deep enough!!" +#endif + + PUSH_BUFF_PROC_ENTRY(pList,BUFFER1,pBuffer); + PUSH_BUFF_PROC_ENTRY(pList,BUFFER2,pBuffer); + PUSH_BUFF_PROC_ENTRY(pList,BUFFER3,pBuffer); + PUSH_BUFF_PROC_ENTRY(pList,BUFFER4,pBuffer); + +} + +#define FILL_ZERO TRUE +#define FILL_COUNTING FALSE +static void InitBuffers(A_BOOL Zero) +{ + A_UINT16 *pBuffer16 = (A_UINT16 *)g_Buffer; + int i; + + /* fill buffer with 16 bit counting pattern or zeros */ + for (i = 0; i < (TOTAL_BYTES / 2) ; i++) { + if (!Zero) { + pBuffer16[i] = (A_UINT16)i; + } else { + pBuffer16[i] = 0; + } + } +} + + +static A_BOOL CheckOneBuffer(A_UINT16 *pBuffer16, int Length) +{ + int i; + A_UINT16 startCount; + A_BOOL success = TRUE; + + /* get the starting count */ + startCount = pBuffer16[0]; + /* invert it, this is the expected value */ + startCount = ~startCount; + /* scan the buffer and verify */ + for (i = 0; i < (Length / 2) ; i++,startCount++) { + /* target will invert all the data */ + if ((A_UINT16)pBuffer16[i] != (A_UINT16)~startCount) { + success = FALSE; + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Invalid Data Got:0x%X, Expecting:0x%X (offset:%d, total:%d) \n", + pBuffer16[i], ((A_UINT16)~startCount), i, Length)); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("0x%X 0x%X 0x%X 0x%X \n", + pBuffer16[i], pBuffer16[i + 1], pBuffer16[i + 2],pBuffer16[i+3])); + break; + } + } + + return success; +} + +static A_BOOL CheckBuffers(void) +{ + int i; + A_BOOL success = TRUE; + BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH]; + + /* assemble the list */ + AssembleBufferList(checkList); + + /* scan the buffers and verify */ + for (i = 0; i < BUFFER_PROC_LIST_DEPTH ; i++) { + success = CheckOneBuffer((A_UINT16 *)checkList[i].pBuffer, checkList[i].length); + if (!success) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer : 0x%X, Length:%d failed verify \n", + (A_UINT32)checkList[i].pBuffer, checkList[i].length)); + break; + } + } + + return success; +} + + /* find the end marker for the last buffer we will be sending */ +static A_UINT16 GetEndMarker(void) +{ + A_UINT8 *pBuffer; + BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH]; + + /* fill up buffers with the normal counting pattern */ + InitBuffers(FILL_COUNTING); + + /* assemble the list we will be sending down */ + AssembleBufferList(checkList); + /* point to the last 2 bytes of the last buffer */ + pBuffer = &(checkList[BUFFER_PROC_LIST_DEPTH - 1].pBuffer[(checkList[BUFFER_PROC_LIST_DEPTH - 1].length) - 2]); + + /* the last count in the last buffer is the marker */ + return (A_UINT16)pBuffer[0] | ((A_UINT16)pBuffer[1] << 8); +} + +#define ATH_PRINT_OUT_ZONE ATH_DEBUG_ERR + +/* send the ordered buffers to the target */ +static A_STATUS SendBuffers(AR6K_DEVICE *pDev, int mbox) +{ + A_STATUS status = A_OK; + A_UINT32 request = HIF_WR_SYNC_BLOCK_INC; + BUFFER_PROC_LIST sendList[BUFFER_PROC_LIST_DEPTH]; + int i; + int totalBytes = 0; + int paddedLength; + int totalwPadding = 0; + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sending buffers on mailbox : %d \n",mbox)); + + /* fill buffer with counting pattern */ + InitBuffers(FILL_COUNTING); + + /* assemble the order in which we send */ + AssembleBufferList(sendList); + + for (i = 0; i < BUFFER_PROC_LIST_DEPTH; i++) { + + /* we are doing block transfers, so we need to pad everything to a block size */ + paddedLength = (sendList[i].length + (g_BlockSizes[mbox] - 1)) & + (~(g_BlockSizes[mbox] - 1)); + + /* send each buffer synchronously */ + status = HIFReadWrite(pDev->HIFDevice, + g_MailboxAddrs[mbox], + sendList[i].pBuffer, + paddedLength, + request, + NULL); + if (status != A_OK) { + break; + } + totalBytes += sendList[i].length; + totalwPadding += paddedLength; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sent %d bytes (%d padded bytes) to mailbox : %d \n",totalBytes,totalwPadding,mbox)); + + return status; +} + +/* poll the mailbox credit counter until we get a credit or timeout */ +static A_STATUS GetCredits(AR6K_DEVICE *pDev, int mbox, int *pCredits) +{ + A_STATUS status = A_OK; + int timeout = TEST_CREDITS_RECV_TIMEOUT; + A_UINT8 credits = 0; + A_UINT32 address; + + while (TRUE) { + + /* Read the counter register to get credits, this auto-decrements */ + address = COUNT_DEC_ADDRESS + (AR6K_MAILBOXES + mbox) * 4; + status = HIFReadWrite(pDev->HIFDevice, address, &credits, sizeof(credits), + HIF_RD_SYNC_BYTE_FIX, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Unable to decrement the command credit count register (mbox=%d)\n",mbox)); + status = A_ERROR; + break; + } + + if (credits) { + break; + } + + timeout--; + + if (timeout <= 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" Timeout reading credit registers (mbox=%d, address:0x%X) \n",mbox,address)); + status = A_ERROR; + break; + } + + /* delay a little, target may not be ready */ + A_MDELAY(1000); + + } + + if (status == A_OK) { + *pCredits = credits; + } + + return status; +} + + +/* wait for the buffers to come back */ +static A_STATUS RecvBuffers(AR6K_DEVICE *pDev, int mbox) +{ + A_STATUS status = A_OK; + A_UINT32 request = HIF_RD_SYNC_BLOCK_INC; + BUFFER_PROC_LIST recvList[BUFFER_PROC_LIST_DEPTH]; + int curBuffer; + int credits; + int i; + int totalBytes = 0; + int paddedLength; + int totalwPadding = 0; + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for buffers on mailbox : %d \n",mbox)); + + /* zero the buffers */ + InitBuffers(FILL_ZERO); + + /* assemble the order in which we should receive */ + AssembleBufferList(recvList); + + curBuffer = 0; + + while (curBuffer < BUFFER_PROC_LIST_DEPTH) { + + /* get number of buffers that have been completed, this blocks + * until we get at least 1 credit or it times out */ + status = GetCredits(pDev, mbox, &credits); + + if (status != A_OK) { + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got %d messages on mailbox : %d \n",credits, mbox)); + + /* get all the buffers that are sitting on the queue */ + for (i = 0; i < credits; i++) { + AR_DEBUG_ASSERT(curBuffer < BUFFER_PROC_LIST_DEPTH); + /* recv the current buffer synchronously, the buffers should come back in + * order... with padding applied by the target */ + paddedLength = (recvList[curBuffer].length + (g_BlockSizes[mbox] - 1)) & + (~(g_BlockSizes[mbox] - 1)); + + status = HIFReadWrite(pDev->HIFDevice, + g_MailboxAddrs[mbox], + recvList[curBuffer].pBuffer, + paddedLength, + request, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to read %d bytes on mailbox:%d : address:0x%X \n", + recvList[curBuffer].length, mbox, g_MailboxAddrs[mbox])); + break; + } + + totalwPadding += paddedLength; + totalBytes += recvList[curBuffer].length; + curBuffer++; + } + + if (status != A_OK) { + break; + } + /* go back and get some more */ + credits = 0; + } + + if (totalBytes != TEST_BYTES) { + AR_DEBUG_ASSERT(FALSE); + } else { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got all buffers on mbox:%d total recv :%d (w/Padding : %d) \n", + mbox, totalBytes, totalwPadding)); + } + + return status; + + +} + +static A_STATUS DoOneMboxHWTest(AR6K_DEVICE *pDev, int mbox) +{ + A_STATUS status; + + do { + /* send out buffers */ + status = SendBuffers(pDev,mbox); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Sending buffers Failed : %d mbox:%d\n",status,mbox)); + break; + } + + /* go get them, this will block */ + status = RecvBuffers(pDev, mbox); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Recv buffers Failed : %d mbox:%d\n",status,mbox)); + break; + } + + /* check the returned data patterns */ + if (!CheckBuffers()) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer Verify Failed : mbox:%d\n",mbox)); + status = A_ERROR; + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" Send/Recv success! mailbox : %d \n",mbox)); + + } while (FALSE); + + return status; +} + +/* here is where the test starts */ +A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev) +{ + int i; + A_STATUS status; + int credits = 0; + A_UINT8 params[4]; + int numBufs; + int bufferSize; + A_UINT16 temp; + + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest START - \n")); + + do { + /* get the addresses for all 4 mailboxes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR, + g_MailboxAddrs, sizeof(g_MailboxAddrs)); + + if (status != A_OK) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* get the block sizes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + g_BlockSizes, sizeof(g_BlockSizes)); + + if (status != A_OK) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* note, the HIF layer usually reports mbox 0 to have a block size of + * 1, but our test wants to run in block-mode for all mailboxes, so we treat all mailboxes + * the same. */ + g_BlockSizes[0] = g_BlockSizes[1]; + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Block Size to use: %d \n",g_BlockSizes[0])); + + if (g_BlockSizes[1] > BUFFER_BLOCK_PAD) { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("%d Block size is too large for buffer pad %d\n", + g_BlockSizes[1], BUFFER_BLOCK_PAD)); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for target.... \n")); + + /* the target lets us know it is ready by giving us 1 credit on + * mailbox 0 */ + status = GetCredits(pDev, 0, &credits); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait for target ready \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Target is ready ...\n")); + + /* read the first 4 scratch registers */ + status = HIFReadWrite(pDev->HIFDevice, + SCRATCH_ADDRESS, + params, + 4, + HIF_RD_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait get parameters \n")); + break; + } + + numBufs = params[0]; + bufferSize = (int)(((A_UINT16)params[2] << 8) | (A_UINT16)params[1]); + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, + ("Target parameters: bufs per mailbox:%d, buffer size:%d bytes (total space: %d, minimum required space (w/padding): %d) \n", + numBufs, bufferSize, (numBufs * bufferSize), TOTAL_BYTES)); + + if ((numBufs * bufferSize) < TOTAL_BYTES) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Not Enough buffer space to run test! need:%d, got:%d \n", + TOTAL_BYTES, (numBufs*bufferSize))); + status = A_ERROR; + break; + } + + temp = GetEndMarker(); + + status = HIFReadWrite(pDev->HIFDevice, + SCRATCH_ADDRESS + 4, + (A_UINT8 *)&temp, + 2, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write end marker \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("End Marker: 0x%X \n",temp)); + + temp = (A_UINT16)g_BlockSizes[1]; + /* convert to a mask */ + temp = temp - 1; + status = HIFReadWrite(pDev->HIFDevice, + SCRATCH_ADDRESS + 6, + (A_UINT8 *)&temp, + 2, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write block mask \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Set Block Mask: 0x%X \n",temp)); + + /* execute the test on each mailbox */ + for (i = 0; i < AR6K_MAILBOXES; i++) { + status = DoOneMboxHWTest(pDev, i); + if (status != A_OK) { + break; + } + } + + } while (FALSE); + + if (status == A_OK) { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - SUCCESS! - \n")); + } else { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - FAILED! - \n")); + } + /* don't let HTC_Start continue, the target is actually not running any HTC code */ + return A_ERROR; +} +#endif + + + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6k.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6k.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6k.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6k.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,206 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// AR6K device layer that handles register level I/O +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef AR6K_H_ +#define AR6K_H_ + +#define AR6K_MAILBOXES 4 + +/* HTC runs over mailbox 0 */ +#define HTC_MAILBOX 0 + +#define AR6K_TARGET_DEBUG_INTR_MASK 0x01 + +#define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK | \ + INT_STATUS_ENABLE_CPU_MASK | \ + INT_STATUS_ENABLE_COUNTER_MASK) + +//#define MBOXHW_UNIT_TEST 1 + +#include "athstartpack.h" +typedef PREPACK struct _AR6K_IRQ_PROC_REGISTERS { + A_UINT8 host_int_status; + A_UINT8 cpu_int_status; + A_UINT8 error_int_status; + A_UINT8 counter_int_status; + A_UINT8 mbox_frame; + A_UINT8 rx_lookahead_valid; + A_UINT8 hole[2]; + A_UINT32 rx_lookahead[2]; +} POSTPACK AR6K_IRQ_PROC_REGISTERS; + +#define AR6K_IRQ_PROC_REGS_SIZE sizeof(AR6K_IRQ_PROC_REGISTERS) + + + +typedef PREPACK struct _AR6K_IRQ_ENABLE_REGISTERS { + A_UINT8 int_status_enable; + A_UINT8 cpu_int_status_enable; + A_UINT8 error_status_enable; + A_UINT8 counter_int_status_enable; +} POSTPACK AR6K_IRQ_ENABLE_REGISTERS; + +#include "athendpack.h" + +#define AR6K_IRQ_ENABLE_REGS_SIZE sizeof(AR6K_IRQ_ENABLE_REGISTERS) + +#define AR6K_REG_IO_BUFFER_SIZE 32 +#define AR6K_MAX_REG_IO_BUFFERS 8 + +/* buffers for ASYNC I/O */ +typedef struct _AR6K_ASYNC_REG_IO_BUFFER { + HTC_PACKET HtcPacket; /* we use an HTC packet as a wrapper for our async register-based I/O */ + A_UINT8 Buffer[AR6K_REG_IO_BUFFER_SIZE]; +} AR6K_ASYNC_REG_IO_BUFFER; + +typedef enum _AR6K_TARGET_FAILURE_TYPE { + AR6K_TARGET_ASSERT = 1, + AR6K_TARGET_RX_ERROR, + AR6K_TARGET_TX_ERROR +} AR6K_TARGET_FAILURE_TYPE; + +typedef struct _AR6K_DEVICE { + A_MUTEX_T Lock; + AR6K_IRQ_PROC_REGISTERS IrqProcRegisters; + AR6K_IRQ_ENABLE_REGISTERS IrqEnableRegisters; + void *HIFDevice; + A_UINT32 BlockSize; + A_UINT32 BlockMask; + A_UINT32 MailboxAddress; + HIF_PENDING_EVENTS_FUNC GetPendingEventsFunc; + void *HTCContext; + HTC_PACKET_QUEUE RegisterIOList; + AR6K_ASYNC_REG_IO_BUFFER RegIOBuffers[AR6K_MAX_REG_IO_BUFFERS]; + void (*TargetFailureCallback)(void *Context, AR6K_TARGET_FAILURE_TYPE Type); + A_STATUS (*MessagePendingCallback)(void *Context, A_UINT32 *LookAhead, A_BOOL *pAsyncProc); + HIF_DEVICE_IRQ_PROCESSING_MODE HifIRQProcessingMode; + HIF_MASK_UNMASK_RECV_EVENT HifMaskUmaskRecvEvent; + A_BOOL HifAttached; +} AR6K_DEVICE; + +#define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) ((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY) + +A_STATUS DevSetup(AR6K_DEVICE *pDev); +void DevCleanup(AR6K_DEVICE *pDev); +A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev, + A_UINT32 *pLookAhead, + int TimeoutMS); +A_STATUS DevRWCompletionHandler(void *context, A_STATUS status); +A_STATUS DevDsrHandler(void *context); +A_STATUS DevCheckPendingRecvMsgsAsync(void *context); +void DevDumpRegisters(AR6K_IRQ_PROC_REGISTERS *pIrqProcRegs, + AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs); + +#define DEV_STOP_RECV_ASYNC TRUE +#define DEV_STOP_RECV_SYNC FALSE +#define DEV_ENABLE_RECV_ASYNC TRUE +#define DEV_ENABLE_RECV_SYNC FALSE +A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode); +A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode); +A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev); + +static INLINE A_STATUS DevSendPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 SendLength) { + A_UINT32 paddedLength; + A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE; + A_STATUS status; + + /* adjust the length to be a multiple of block size if appropriate */ + paddedLength = (SendLength + (pDev->BlockMask)) & + (~(pDev->BlockMask)); +#if 0 // BufferLength may not be set in , fix this... + if (paddedLength > pPacket->BufferLength) { + AR_DEBUG_ASSERT(FALSE); + if (pPacket->Completion != NULL) { + COMPLETE_HTC_PACKET(pPacket,A_EINVAL); + } + return A_EINVAL; + } +#endif + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("DevSendPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n", + paddedLength, + pDev->MailboxAddress, + sync ? "SYNC" : "ASYNC")); + + status = HIFReadWrite(pDev->HIFDevice, + pDev->MailboxAddress, + pPacket->pBuffer, + paddedLength, /* the padded length */ + sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC, + sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */ + + if (sync) { + pPacket->Status = status; + } + + return status; +} + +static INLINE A_STATUS DevRecvPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 RecvLength) { + A_UINT32 paddedLength; + A_STATUS status; + A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE; + + /* adjust the length to be a multiple of block size if appropriate */ + paddedLength = (RecvLength + (pDev->BlockMask)) & + (~(pDev->BlockMask)); + if (paddedLength > pPacket->BufferLength) { + AR_DEBUG_ASSERT(FALSE); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("DevRecvPacket, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n", + paddedLength,RecvLength,pPacket->BufferLength)); + if (pPacket->Completion != NULL) { + COMPLETE_HTC_PACKET(pPacket,A_EINVAL); + } + return A_EINVAL; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("DevRecvPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n", + paddedLength, + pDev->MailboxAddress, + sync ? "SYNC" : "ASYNC")); + + status = HIFReadWrite(pDev->HIFDevice, + pDev->MailboxAddress, + pPacket->pBuffer, + paddedLength, + sync ? HIF_RD_SYNC_BLOCK_INC : HIF_RD_ASYNC_BLOCK_INC, + sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */ + + if (sync) { + pPacket->Status = status; + } + + return status; +} + +#ifdef MBOXHW_UNIT_TEST +A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev); +#endif + +#endif /*AR6K_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6k_events.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6k_events.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6k_events.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6k_events.c 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,665 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// AR6K Driver layer event handling (i.e. interrupts, message polling) +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" + +#include "mbox_host_reg.h" +#include "rtc_reg.h" + +#include "a_osapi.h" +#include "a_debug.h" +#include "hif.h" +#include "htc_packet.h" +#include "ar6k.h" + + +extern void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket); +extern HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev); + +static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev); + +#define DELAY_PER_INTERVAL_MS 10 /* 10 MS delay per polling interval */ + +/* completion routine for ALL HIF layer async I/O */ +A_STATUS DevRWCompletionHandler(void *context, A_STATUS status) +{ + HTC_PACKET *pPacket = (HTC_PACKET *)context; + + COMPLETE_HTC_PACKET(pPacket,status); + + return A_OK; +} + +/* mailbox recv message polling */ +A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev, + A_UINT32 *pLookAhead, + int TimeoutMS) +{ + A_STATUS status = A_OK; + int timeout = TimeoutMS/DELAY_PER_INTERVAL_MS; + + AR_DEBUG_ASSERT(timeout > 0); + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevPollMboxMsgRecv \n")); + + while (TRUE) { + + if (pDev->GetPendingEventsFunc != NULL) + { + + HIF_PENDING_EVENTS_INFO events; + + /* the HIF layer uses a special mechanism to get events, do this + * synchronously */ + status = pDev->GetPendingEventsFunc(pDev->HIFDevice, + &events, + NULL); + if (A_FAILED(status)) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get pending events \n")); + break; + } + + if (events.Events & HIF_RECV_MSG_AVAIL) + { + /* there is a message available, the lookahead should be valid now */ + *pLookAhead = events.LookAhead; + + break; + } + } + else + { + + /* this is the standard HIF way.... */ + /* load the register table */ + status = HIFReadWrite(pDev->HIFDevice, + HOST_INT_STATUS_ADDRESS, + (A_UINT8 *)&pDev->IrqProcRegisters, + AR6K_IRQ_PROC_REGS_SIZE, + HIF_RD_SYNC_BYTE_INC, + NULL); + + if (A_FAILED(status)) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to read register table \n")); + break; + } + + /* check for MBOX data and valid lookahead */ + if (pDev->IrqProcRegisters.host_int_status & (1 << HTC_MAILBOX)) + { + if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) + { + /* mailbox has a message and the look ahead is valid */ + *pLookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX]; + break; + } + } + + } + + timeout--; + + if (timeout <= 0) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Timeout waiting for recv message \n")); + status = A_ERROR; + + /* check if the target asserted */ + if ( pDev->IrqProcRegisters.counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) { + /* target signaled an assert, process this pending interrupt + * this will call the target failure handler */ + DevServiceDebugInterrupt(pDev); + } + + break; + } + + /* delay a little */ + A_MDELAY(DELAY_PER_INTERVAL_MS); + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Retry Mbox Poll : %d \n",timeout)); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevPollMboxMsgRecv \n")); + + return status; +} + +static A_STATUS DevServiceCPUInterrupt(AR6K_DEVICE *pDev) +{ + A_STATUS status; + A_UINT8 cpu_int_status; + A_UINT8 regBuffer[4]; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("CPU Interrupt\n")); + cpu_int_status = pDev->IrqProcRegisters.cpu_int_status & + pDev->IrqEnableRegisters.cpu_int_status_enable; + AR_DEBUG_ASSERT(cpu_int_status); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + ("Valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n", + cpu_int_status)); + + /* Clear the interrupt */ + pDev->IrqProcRegisters.cpu_int_status &= ~cpu_int_status; /* W1C */ + + /* set up the register transfer buffer to hit the register 4 times , this is done + * to make the access 4-byte aligned to mitigate issues with host bus interconnects that + * restrict bus transfer lengths to be a multiple of 4-bytes */ + + /* set W1C value to clear the interrupt, this hits the register first */ + regBuffer[0] = cpu_int_status; + /* the remaining 4 values are set to zero which have no-effect */ + regBuffer[1] = 0; + regBuffer[2] = 0; + regBuffer[3] = 0; + + status = HIFReadWrite(pDev->HIFDevice, + CPU_INT_STATUS_ADDRESS, + regBuffer, + 4, + HIF_WR_SYNC_BYTE_FIX, + NULL); + + AR_DEBUG_ASSERT(status == A_OK); + return status; +} + + +static A_STATUS DevServiceErrorInterrupt(AR6K_DEVICE *pDev) +{ + A_STATUS status; + A_UINT8 error_int_status; + A_UINT8 regBuffer[4]; + + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error Interrupt\n")); + error_int_status = pDev->IrqProcRegisters.error_int_status & 0x0F; + AR_DEBUG_ASSERT(error_int_status); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n", + error_int_status)); + + if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) { + /* Wakeup */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error : Wakeup\n")); + } + + if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) { + /* Rx Underflow */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Rx Underflow\n")); + if (pDev->TargetFailureCallback != NULL) { + pDev->TargetFailureCallback(pDev->HTCContext, AR6K_TARGET_RX_ERROR); + } + } + + if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) { + /* Tx Overflow */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Tx Overflow\n")); + if (pDev->TargetFailureCallback != NULL) { + pDev->TargetFailureCallback(pDev->HTCContext, AR6K_TARGET_TX_ERROR); + } + } + + /* Clear the interrupt */ + pDev->IrqProcRegisters.error_int_status &= ~error_int_status; /* W1C */ + + /* set up the register transfer buffer to hit the register 4 times , this is done + * to make the access 4-byte aligned to mitigate issues with host bus interconnects that + * restrict bus transfer lengths to be a multiple of 4-bytes */ + + /* set W1C value to clear the interrupt, this hits the register first */ + regBuffer[0] = error_int_status; + /* the remaining 4 values are set to zero which have no-effect */ + regBuffer[1] = 0; + regBuffer[2] = 0; + regBuffer[3] = 0; + + status = HIFReadWrite(pDev->HIFDevice, + ERROR_INT_STATUS_ADDRESS, + regBuffer, + 4, + HIF_WR_SYNC_BYTE_FIX, + NULL); + + AR_DEBUG_ASSERT(status == A_OK); + return status; +} + +static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev) +{ + A_UINT32 dummy; + A_STATUS status; + + /* Send a target failure event to the application */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Target debug interrupt\n")); + + if (pDev->TargetFailureCallback != NULL) { + pDev->TargetFailureCallback(pDev->HTCContext, AR6K_TARGET_ASSERT); + } + + /* clear the interrupt , the debug error interrupt is + * counter 0 */ + /* read counter to clear interrupt */ + status = HIFReadWrite(pDev->HIFDevice, + COUNT_DEC_ADDRESS, + (A_UINT8 *)&dummy, + 4, + HIF_RD_SYNC_BYTE_INC, + NULL); + + AR_DEBUG_ASSERT(status == A_OK); + return status; +} + +static A_STATUS DevServiceCounterInterrupt(AR6K_DEVICE *pDev) +{ + A_UINT8 counter_int_status; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Counter Interrupt\n")); + + counter_int_status = pDev->IrqProcRegisters.counter_int_status & + pDev->IrqEnableRegisters.counter_int_status_enable; + + AR_DEBUG_ASSERT(counter_int_status); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + ("Valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n", + counter_int_status)); + + /* Check if the debug interrupt is pending */ + if (counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) { + return DevServiceDebugInterrupt(pDev); + } + + return A_OK; +} + +/* callback when our fetch to get interrupt status registers completes */ +static void DevGetEventAsyncHandler(void *Context, HTC_PACKET *pPacket) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context; + A_UINT32 lookAhead = 0; + A_BOOL otherInts = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGetEventAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); + + do { + + if (A_FAILED(pPacket->Status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" GetEvents I/O request failed, status:%d \n", pPacket->Status)); + /* bail out, don't unmask HIF interrupt */ + break; + } + + if (pDev->GetPendingEventsFunc != NULL) { + /* the HIF layer collected the information for us */ + HIF_PENDING_EVENTS_INFO *pEvents = (HIF_PENDING_EVENTS_INFO *)pPacket->pBuffer; + if (pEvents->Events & HIF_RECV_MSG_AVAIL) { + lookAhead = pEvents->LookAhead; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler1, lookAhead is zero! \n")); + } + } + if (pEvents->Events & HIF_OTHER_EVENTS) { + otherInts = TRUE; + } + } else { + /* standard interrupt table handling.... */ + AR6K_IRQ_PROC_REGISTERS *pReg = (AR6K_IRQ_PROC_REGISTERS *)pPacket->pBuffer; + A_UINT8 host_int_status; + + host_int_status = pReg->host_int_status & pDev->IrqEnableRegisters.int_status_enable; + + if (host_int_status & (1 << HTC_MAILBOX)) { + host_int_status &= ~(1 << HTC_MAILBOX); + if (pReg->rx_lookahead_valid & (1 << HTC_MAILBOX)) { + /* mailbox has a message and the look ahead is valid */ + lookAhead = pReg->rx_lookahead[HTC_MAILBOX]; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler2, lookAhead is zero! \n")); + } + } + } + + if (host_int_status) { + /* there are other interrupts to handle */ + otherInts = TRUE; + } + } + + if (otherInts || (lookAhead == 0)) { + /* if there are other interrupts to process, we cannot do this in the async handler so + * ack the interrupt which will cause our sync handler to run again + * if however there are no more messages, we can now ack the interrupt */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + (" Acking interrupt from DevGetEventAsyncHandler (otherints:%d, lookahead:0x%X)\n", + otherInts, lookAhead)); + HIFAckInterrupt(pDev->HIFDevice); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + (" DevGetEventAsyncHandler : detected another message, lookahead :0x%X \n", + lookAhead)); + /* lookahead is non-zero and there are no other interrupts to service, + * go get the next message */ + pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, NULL); + } + + } while (FALSE); + + /* free this IO packet */ + AR6KFreeIOPacket(pDev,pPacket); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGetEventAsyncHandler \n")); +} + +/* called by the HTC layer when it wants us to check if the device has any more pending + * recv messages, this starts off a series of async requests to read interrupt registers */ +A_STATUS DevCheckPendingRecvMsgsAsync(void *context) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)context; + A_STATUS status = A_OK; + HTC_PACKET *pIOPacket; + + /* this is called in an ASYNC only context, we may NOT block, sleep or call any apis that can + * cause us to switch contexts */ + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevCheckPendingRecvMsgsAsync: (dev: 0x%X)\n", (A_UINT32)pDev)); + + do { + + if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) { + /* break the async processing chain right here, no need to continue. + * The DevDsrHandler() will handle things in a loop when things are driven + * synchronously */ + break; + } + /* first allocate one of our HTC packets we created for async I/O + * we reuse HTC packet definitions so that we can use the completion mechanism + * in DevRWCompletionHandler() */ + pIOPacket = AR6KAllocIOPacket(pDev); + + if (NULL == pIOPacket) { + /* there should be only 1 asynchronous request out at a time to read these registers + * so this should actually never happen */ + status = A_NO_MEMORY; + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* stick in our completion routine when the I/O operation completes */ + pIOPacket->Completion = DevGetEventAsyncHandler; + pIOPacket->pContext = pDev; + + if (pDev->GetPendingEventsFunc) { + /* HIF layer has it's own mechanism, pass the IO to it.. */ + status = pDev->GetPendingEventsFunc(pDev->HIFDevice, + (HIF_PENDING_EVENTS_INFO *)pIOPacket->pBuffer, + pIOPacket); + + } else { + /* standard way, read the interrupt register table asynchronously again */ + status = HIFReadWrite(pDev->HIFDevice, + HOST_INT_STATUS_ADDRESS, + pIOPacket->pBuffer, + AR6K_IRQ_PROC_REGS_SIZE, + HIF_RD_ASYNC_BYTE_INC, + pIOPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Async IO issued to get interrupt status...\n")); + } while (FALSE); + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevCheckPendingRecvMsgsAsync \n")); + + return status; +} + +/* process pending interrupts synchronously */ +static A_STATUS ProcessPendingIRQs(AR6K_DEVICE *pDev, A_BOOL *pDone, A_BOOL *pASyncProcessing) +{ + A_STATUS status = A_OK; + A_UINT8 host_int_status = 0; + A_UINT32 lookAhead = 0; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+ProcessPendingIRQs: (dev: 0x%X)\n", (A_UINT32)pDev)); + + /*** NOTE: the HIF implementation guarantees that the context of this call allows + * us to perform SYNCHRONOUS I/O, that is we can block, sleep or call any API that + * can block or switch thread/task ontexts. + * This is a fully schedulable context. + * */ + do { + + if (pDev->IrqEnableRegisters.int_status_enable == 0) { + /* interrupt enables have been cleared, do not try to process any pending interrupts that + * may result in more bus transactions. The target may be unresponsive at this + * point. */ + break; + } + + if (pDev->GetPendingEventsFunc != NULL) { + HIF_PENDING_EVENTS_INFO events; + + /* the HIF layer uses a special mechanism to get events + * get this synchronously */ + status = pDev->GetPendingEventsFunc(pDev->HIFDevice, + &events, + NULL); + + if (A_FAILED(status)) { + break; + } + + if (events.Events & HIF_RECV_MSG_AVAIL) { + lookAhead = events.LookAhead; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs1 lookAhead is zero! \n")); + } + } + + if (!(events.Events & HIF_OTHER_EVENTS) || + !(pDev->IrqEnableRegisters.int_status_enable & OTHER_INTS_ENABLED)) { + /* no need to read the register table, no other interesting interrupts. + * Some interfaces (like SPI) can shadow interrupt sources without + * requiring the host to do a full table read */ + break; + } + + /* otherwise fall through and read the register table */ + } + + /* + * Read the first 28 bytes of the HTC register table. This will yield us + * the value of different int status registers and the lookahead + * registers. + * length = sizeof(int_status) + sizeof(cpu_int_status) + + * sizeof(error_int_status) + sizeof(counter_int_status) + + * sizeof(mbox_frame) + sizeof(rx_lookahead_valid) + + * sizeof(hole) + sizeof(rx_lookahead) + + * sizeof(int_status_enable) + sizeof(cpu_int_status_enable) + + * sizeof(error_status_enable) + + * sizeof(counter_int_status_enable); + * + */ + status = HIFReadWrite(pDev->HIFDevice, + HOST_INT_STATUS_ADDRESS, + (A_UINT8 *)&pDev->IrqProcRegisters, + AR6K_IRQ_PROC_REGS_SIZE, + HIF_RD_SYNC_BYTE_INC, + NULL); + + if (A_FAILED(status)) { + break; + } + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_IRQ)) { + DevDumpRegisters(&pDev->IrqProcRegisters, + &pDev->IrqEnableRegisters); + } + + /* Update only those registers that are enabled */ + host_int_status = pDev->IrqProcRegisters.host_int_status & + pDev->IrqEnableRegisters.int_status_enable; + + if (NULL == pDev->GetPendingEventsFunc) { + /* only look at mailbox status if the HIF layer did not provide this function, + * on some HIF interfaces reading the RX lookahead is not valid to do */ + if (host_int_status & (1 << HTC_MAILBOX)) { + /* mask out pending mailbox value, we use "lookAhead" as the real flag for + * mailbox processing below */ + host_int_status &= ~(1 << HTC_MAILBOX); + if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) { + /* mailbox has a message and the look ahead is valid */ + lookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX]; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs2, lookAhead is zero! \n")); + } + } + } + } else { + /* not valid to check if the HIF has another mechanism for reading mailbox pending status*/ + host_int_status &= ~(1 << HTC_MAILBOX); + } + + } while (FALSE); + + + do { + + /* did the interrupt status fetches succeed? */ + if (A_FAILED(status)) { + break; + } + + if ((0 == host_int_status) && (0 == lookAhead)) { + /* nothing to process, the caller can use this to break out of a loop */ + *pDone = TRUE; + break; + } + + if (lookAhead != 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Pending mailbox message, LookAhead: 0x%X\n",lookAhead)); + /* Mailbox Interrupt, the HTC layer may issue async requests to empty the + * mailbox... + * When emptying the recv mailbox we use the async handler above called from the + * completion routine of the callers read request. This can improve performance + * by reducing context switching when we rapidly pull packets */ + status = pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, pASyncProcessing); + if (A_FAILED(status)) { + break; + } + /* if sync processing of Rx packets is enabled and lookahead of last packet is 0, then + * we can avoid extra CMD53 16-byte read above by setting pDone = TRUE */ + if ((lookAhead == 0) && (*pASyncProcessing == FALSE)) { + *pDone = TRUE; + } + } + + /* now handle the rest of them */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + (" Valid interrupt source(s) for OTHER interrupts: 0x%x\n", + host_int_status)); + + if (HOST_INT_STATUS_CPU_GET(host_int_status)) { + /* CPU Interrupt */ + status = DevServiceCPUInterrupt(pDev); + if (A_FAILED(status)){ + break; + } + } + + if (HOST_INT_STATUS_ERROR_GET(host_int_status)) { + /* Error Interrupt */ + status = DevServiceErrorInterrupt(pDev); + if (A_FAILED(status)){ + break; + } + } + + if (HOST_INT_STATUS_COUNTER_GET(host_int_status)) { + /* Counter Interrupt */ + status = DevServiceCounterInterrupt(pDev); + if (A_FAILED(status)){ + break; + } + } + + } while (FALSE); + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-ProcessPendingIRQs: (done:%d, async:%d) status=%d \n", + *pDone, *pASyncProcessing, status)); + + return status; +} + + +/* Synchronousinterrupt handler, this handler kicks off all interrupt processing.*/ +A_STATUS DevDsrHandler(void *context) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)context; + A_STATUS status = A_OK; + A_BOOL done = FALSE; + A_BOOL asyncProc = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDsrHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); + + + while (!done) { + status = ProcessPendingIRQs(pDev, &done, &asyncProc); + if (A_FAILED(status)) { + break; + } + + if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) { + /* the HIF layer does not allow async IRQ processing, override the asyncProc flag */ + asyncProc = FALSE; + /* this will cause us to re-enter ProcessPendingIRQ() and re-read interrupt status registers. + * this has a nice side effect of blocking us until all async read requests are completed. + * This behavior is required on some HIF implementations that do not allow ASYNC + * processing in interrupt handlers (like Windows CE) */ + } + + if (asyncProc) { + /* the function performed some async I/O for performance, we + need to exit the ISR immediately, the check below will prevent the interrupt from being + Ack'd while we handle it asynchronously */ + break; + } + + } + + if (A_SUCCESS(status) && !asyncProc) { + /* Ack the interrupt only if : + * 1. we did not get any errors in processing interrupts + * 2. there are no outstanding async processing requests */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Acking interrupt from DevDsrHandler \n")); + HIFAckInterrupt(pDev->HIFDevice); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDsrHandler \n")); + return status; +} + + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6kap_common.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6kap_common.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6kap_common.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6kap_common.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,40 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions of common AP mode data structures. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _AR6KAP_COMMON_H_ +#define _AR6KAP_COMMON_H_ + +/* + * Used with AR6000_XIOCTL_AP_GET_STA_LIST + */ +typedef struct { + A_UINT8 mac[ATH_MAC_LEN]; + A_UINT8 aid; +} station_t; + +typedef struct { + station_t sta[AP_MAX_NUM_STA]; +} ap_get_sta_t; + +#endif /* _AR6KAP_COMMON_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6xapi_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6xapi_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/ar6xapi_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ar6xapi_linux.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,159 @@ +#ifndef _AR6XAPI_LINUX_H +#define _AR6XAPI_LINUX_H +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifdef __cplusplus +extern "C" { +#endif + +struct ar6_softc; + +void ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap, + A_UINT32 ver); +A_STATUS ar6000_control_tx(void *devt, void *osbuf, HTC_ENDPOINT_ID eid); +void ar6000_connect_event(struct ar6_softc *ar, A_UINT16 channel, + A_UINT8 *bssid, A_UINT16 listenInterval, + A_UINT16 beaconInterval, NETWORK_TYPE networkType, + A_UINT8 beaconIeLen, A_UINT8 assocReqLen, + A_UINT8 assocRespLen,A_UINT8 *assocInfo); +void ar6000_disconnect_event(struct ar6_softc *ar, A_UINT8 reason, + A_UINT8 *bssid, A_UINT8 assocRespLen, + A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus); +void ar6000_tkip_micerr_event(struct ar6_softc *ar, A_UINT8 keyid, + A_BOOL ismcast); +void ar6000_bitrate_rx(void *devt, A_INT32 rateKbps); +void ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList); +void ar6000_regDomain_event(struct ar6_softc *ar, A_UINT32 regCode); +void ar6000_txPwr_rx(void *devt, A_UINT8 txPwr); +void ar6000_keepalive_rx(void *devt, A_UINT8 configured); +void ar6000_neighborReport_event(struct ar6_softc *ar, int numAps, + WMI_NEIGHBOR_INFO *info); +void ar6000_set_numdataendpts(struct ar6_softc *ar, A_UINT32 num); +void ar6000_scanComplete_event(struct ar6_softc *ar, A_STATUS status); +void ar6000_targetStats_event(struct ar6_softc *ar, WMI_TARGET_STATS *pStats); +void ar6000_rssiThreshold_event(struct ar6_softc *ar, + WMI_RSSI_THRESHOLD_VAL newThreshold, + A_INT16 rssi); +void ar6000_reportError_event(struct ar6_softc *, WMI_TARGET_ERROR_VAL errorVal); +void ar6000_cac_event(struct ar6_softc *ar, A_UINT8 ac, A_UINT8 cac_indication, + A_UINT8 statusCode, A_UINT8 *tspecSuggestion); +void ar6000_channel_change_event(struct ar6_softc *ar, A_UINT16 oldChannel, A_UINT16 newChannel); +void ar6000_hbChallengeResp_event(struct ar6_softc *, A_UINT32 cookie, A_UINT32 source); +void +ar6000_roam_tbl_event(struct ar6_softc *ar, WMI_TARGET_ROAM_TBL *pTbl); + +void +ar6000_roam_data_event(struct ar6_softc *ar, WMI_TARGET_ROAM_DATA *p); + +void +ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters, + WMI_GET_WOW_LIST_REPLY *wow_reply); + +void ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID, + WMI_PMKID *pmkidList, A_UINT8 *bssidList); + +void ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values); +void ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value); +void ar6000_gpio_ack_rx(void); + +void ar6000_dbglog_init_done(struct ar6_softc *ar); + +#ifdef SEND_EVENT_TO_APP +void ar6000_send_event_to_app(struct ar6_softc *ar, A_UINT16 eventId, A_UINT8 *datap, int len); +void ar6000_send_generic_event_to_app(struct ar6_softc *ar, A_UINT16 eventId, A_UINT8 *datap, int len); +#endif + +#ifdef CONFIG_HOST_TCMD_SUPPORT +void ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len); +#endif + +void ar6000_tx_retry_err_event(void *devt); + +void ar6000_snrThresholdEvent_rx(void *devt, + WMI_SNR_THRESHOLD_VAL newThreshold, + A_UINT8 snr); + +void ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL range, A_UINT8 lqVal); + + +void ar6000_ratemask_rx(void *devt, A_UINT16 ratemask); + +A_STATUS ar6000_get_driver_cfg(struct net_device *dev, + A_UINT16 cfgParam, + void *result); +void ar6000_bssInfo_event_rx(struct ar6_softc *ar, A_UINT8 *data, int len); + +void ar6000_dbglog_event(struct ar6_softc *ar, A_UINT32 dropped, + A_INT8 *buffer, A_UINT32 length); + +int ar6000_dbglog_get_debug_logs(struct ar6_softc *ar); + +void ar6000_peer_event(void *devt, A_UINT8 eventCode, A_UINT8 *bssid); + +void ar6000_indicate_tx_activity(void *devt, A_UINT8 trafficClass, A_BOOL Active); +HTC_ENDPOINT_ID ar6000_ac2_endpoint_id ( void * devt, A_UINT8 ac); +A_UINT8 ar6000_endpoint_id2_ac (void * devt, HTC_ENDPOINT_ID ep ); + +void ar6000_dset_open_req(void *devt, + A_UINT32 id, + A_UINT32 targ_handle, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); +void ar6000_dset_close(void *devt, A_UINT32 access_cookie); +void ar6000_dset_data_req(void *devt, + A_UINT32 access_cookie, + A_UINT32 offset, + A_UINT32 length, + A_UINT32 targ_buf, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); + + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +void prof_count_rx(unsigned int addr, unsigned int count); +#endif + +A_UINT32 ar6000_getnodeAge (void); + +A_UINT32 ar6000_getclkfreq (void); + +int ar6000_ap_mode_profile_commit(struct ar6_softc *ar); + +struct ieee80211req_wpaie; +A_STATUS +ar6000_ap_mode_get_wpa_ie(struct ar6_softc *ar, struct ieee80211req_wpaie *wpaie); + +A_STATUS is_iwioctl_allowed(A_UINT8 mode, A_UINT16 cmd); + +A_STATUS is_xioctl_allowed(A_UINT8 mode, int cmd); + +void ar6000_pspoll_event(struct ar6_softc *ar,A_UINT8 aid); + +void ar6000_dtimexpiry_event(struct ar6_softc *ar); + +#ifdef __cplusplus +} +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/athbtfilter.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/athbtfilter.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/athbtfilter.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/athbtfilter.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,131 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Public Bluetooth filter APIs +// Author(s): ="Atheros" +//============================================================================== +#ifndef ATHBTFILTER_H_ +#define ATHBTFILTER_H_ + + +typedef enum _ATHBT_HCI_CTRL_TYPE { + ATHBT_HCI_COMMAND = 0, + ATHBT_HCI_EVENT = 1, +} ATHBT_HCI_CTRL_TYPE; + +typedef enum _ATHBT_STATE_INDICATION { + ATH_BT_NOOP = 0, + ATH_BT_INQUIRY = 1, + ATH_BT_CONNECT = 2, + ATH_BT_SCO = 3, + ATH_BT_ACL = 4, + ATH_BT_A2DP = 5, + ATH_BT_ESCO = 6, + /* new states go here.. */ + + ATH_BT_MAX_STATE_INDICATION +} ATHBT_STATE_INDICATION; + + /* filter function for OUTGOING commands and INCOMMING events */ +typedef void (*ATHBT_FILTER_CMD_EVENTS_FN)(void *pContext, ATHBT_HCI_CTRL_TYPE Type, unsigned char *pBuffer, int Length); + + /* filter function for OUTGOING data HCI packets */ +typedef void (*ATHBT_FILTER_DATA_FN)(void *pContext, unsigned char *pBuffer, int Length); + +typedef enum _ATHBT_STATE { + STATE_OFF = 0, + STATE_ON = 1, + STATE_MAX +} ATHBT_STATE; + + /* BT state indication (when filter functions are not used) */ + +typedef void (*ATHBT_INDICATE_STATE_FN)(void *pContext, ATHBT_STATE_INDICATION Indication, ATHBT_STATE State, unsigned char LMPVersion); + +typedef struct _ATHBT_FILTER_INSTANCE { +#ifdef UNDER_CE + WCHAR *pWlanAdapterName; /* filled in by user */ +#endif + int FilterEnabled; /* filtering is enabled */ + int Attached; /* filter library is attached */ + void *pContext; /* private context for filter library */ + ATHBT_FILTER_CMD_EVENTS_FN pFilterCmdEvents; /* function ptr to filter a command or event */ + ATHBT_FILTER_DATA_FN pFilterAclDataOut; /* function ptr to filter ACL data out (to radio) */ + ATHBT_FILTER_DATA_FN pFilterAclDataIn; /* function ptr to filter ACL data in (from radio) */ + ATHBT_INDICATE_STATE_FN pIndicateState; /* function ptr to indicate a state */ +} ATH_BT_FILTER_INSTANCE; + + +/* API MACROS */ + +#define AthBtFilterHciCommand(instance,packet,length) \ + if ((instance)->FilterEnabled) { \ + (instance)->pFilterCmdEvents((instance)->pContext, \ + ATHBT_HCI_COMMAND, \ + (unsigned char *)(packet), \ + (length)); \ + } + +#define AthBtFilterHciEvent(instance,packet,length) \ + if ((instance)->FilterEnabled) { \ + (instance)->pFilterCmdEvents((instance)->pContext, \ + ATHBT_HCI_EVENT, \ + (unsigned char *)(packet), \ + (length)); \ + } + +#define AthBtFilterHciAclDataOut(instance,packet,length) \ + if ((instance)->FilterEnabled) { \ + (instance)->pFilterAclDataOut((instance)->pContext, \ + (unsigned char *)(packet), \ + (length)); \ + } + +#define AthBtFilterHciAclDataIn(instance,packet,length) \ + if ((instance)->FilterEnabled) { \ + (instance)->pFilterAclDataIn((instance)->pContext, \ + (unsigned char *)(packet), \ + (length)); \ + } + +/* if filtering is not desired, the application can indicate the state directly using this + * macro: + */ +#define AthBtIndicateState(instance,indication,state) \ + if ((instance)->FilterEnabled) { \ + (instance)->pIndicateState((instance)->pContext, \ + (indication), \ + (state), \ + 0); \ + } + +#ifdef __cplusplus +extern "C" { +#endif + +/* API prototypes */ +int AthBtFilter_Attach(ATH_BT_FILTER_INSTANCE *pInstance); +void AthBtFilter_Detach(ATH_BT_FILTER_INSTANCE *pInstance); + +#ifdef __cplusplus +} +#endif + +#endif /*ATHBTFILTER_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/athdefs.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/athdefs.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/athdefs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/athdefs.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,84 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef __ATHDEFS_H__ +#define __ATHDEFS_H__ + +/* + * This file contains definitions that may be used across both + * Host and Target software. Nothing here is module-dependent + * or platform-dependent. + */ + +/* + * Generic error codes that can be used by hw, sta, ap, sim, dk + * and any other environments. Since these are enums, feel free to + * add any more codes that you need. + */ + +typedef enum { + A_ERROR = -1, /* Generic error return */ + A_OK = 0, /* success */ + /* Following values start at 1 */ + A_DEVICE_NOT_FOUND, /* not able to find PCI device */ + A_NO_MEMORY, /* not able to allocate memory, not available */ + A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */ + A_NO_FREE_DESC, /* no free descriptors available */ + A_BAD_ADDRESS, /* address does not match descriptor */ + A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */ + A_REGS_NOT_MAPPED, /* registers not correctly mapped */ + A_EPERM, /* Not superuser */ + A_EACCES, /* Access denied */ + A_ENOENT, /* No such entry, search failed, etc. */ + A_EEXIST, /* The object already exists (can't create) */ + A_EFAULT, /* Bad address fault */ + A_EBUSY, /* Object is busy */ + A_EINVAL, /* Invalid parameter */ + A_EMSGSIZE, /* Inappropriate message buffer length */ + A_ECANCELED, /* Operation canceled */ + A_ENOTSUP, /* Operation not supported */ + A_ECOMM, /* Communication error on send */ + A_EPROTO, /* Protocol error */ + A_ENODEV, /* No such device */ + A_EDEVNOTUP, /* device is not UP */ + A_NO_RESOURCE, /* No resources for requested operation */ + A_HARDWARE, /* Hardware failure */ + A_PENDING, /* Asynchronous routine; will send up results la +ter (typically in callback) */ + A_EBADCHANNEL, /* The channel cannot be used */ + A_DECRYPT_ERROR, /* Decryption error */ + A_PHY_ERROR, /* RX PHY error */ + A_CONSUMED /* Object was consumed */ +} A_STATUS; + +#define A_SUCCESS(x) (x == A_OK) +#define A_FAILED(x) (!A_SUCCESS(x)) + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#endif /* __ATHDEFS_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/athdrv.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/athdrv.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/athdrv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/athdrv.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,35 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _ATHDRV_H_ +#define _ATHDRV_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* _ATHDRV_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/athdrv_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/athdrv_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/athdrv_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/athdrv_linux.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,1089 @@ +/* + * Copyright (c) 2004-2006 Atheros Communications Inc. + * All rights reserved. + * + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _ATHDRV_LINUX_H +#define _ATHDRV_LINUX_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* + * There are two types of ioctl's here: Standard ioctls and + * eXtended ioctls. All extended ioctls (XIOCTL) are multiplexed + * off of the single ioctl command, AR6000_IOCTL_EXTENDED. The + * arguments for every XIOCTL starts with a 32-bit command word + * that is used to select which extended ioctl is in use. After + * the command word are command-specific arguments. + */ + +/* Linux standard Wireless Extensions, private ioctl interfaces */ +#define IEEE80211_IOCTL_SETPARAM (SIOCIWFIRSTPRIV+0) +#define IEEE80211_IOCTL_SETKEY (SIOCIWFIRSTPRIV+1) +#define IEEE80211_IOCTL_DELKEY (SIOCIWFIRSTPRIV+2) +#define IEEE80211_IOCTL_SETMLME (SIOCIWFIRSTPRIV+3) +#define IEEE80211_IOCTL_ADDPMKID (SIOCIWFIRSTPRIV+4) +#define IEEE80211_IOCTL_SETOPTIE (SIOCIWFIRSTPRIV+5) +//#define IEEE80211_IOCTL_GETPARAM (SIOCIWFIRSTPRIV+6) +//#define IEEE80211_IOCTL_SETWMMPARAMS (SIOCIWFIRSTPRIV+7) +//#define IEEE80211_IOCTL_GETWMMPARAMS (SIOCIWFIRSTPRIV+8) +//#define IEEE80211_IOCTL_GETOPTIE (SIOCIWFIRSTPRIV+9) +//#define IEEE80211_IOCTL_SETAUTHALG (SIOCIWFIRSTPRIV+10) +#define IEEE80211_IOCTL_LASTONE (SIOCIWFIRSTPRIV+10) + + + +/* ====WMI Ioctls==== */ +/* + * + * Many ioctls simply provide WMI services to application code: + * an application makes such an ioctl call with a set of arguments + * that are packaged into the corresponding WMI message, and sent + * to the Target. + */ + +#define AR6000_IOCTL_WMI_GETREV (SIOCIWFIRSTPRIV+11) +/* + * arguments: + * ar6000_version *revision + */ + +#define AR6000_IOCTL_WMI_SETPWR (SIOCIWFIRSTPRIV+12) +/* + * arguments: + * WMI_POWER_MODE_CMD pwrModeCmd (see include/wmi.h) + * uses: WMI_SET_POWER_MODE_CMDID + */ + +#define AR6000_IOCTL_WMI_SETSCAN (SIOCIWFIRSTPRIV+13) +/* + * arguments: + * WMI_SCAN_PARAMS_CMD scanParams (see include/wmi.h) + * uses: WMI_SET_SCAN_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SETLISTENINT (SIOCIWFIRSTPRIV+14) +/* + * arguments: + * UINT32 listenInterval + * uses: WMI_SET_LISTEN_INT_CMDID + */ + +#define AR6000_IOCTL_WMI_SETBSSFILTER (SIOCIWFIRSTPRIV+15) +/* + * arguments: + * WMI_BSS_FILTER filter (see include/wmi.h) + * uses: WMI_SET_BSS_FILTER_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_CHANNELPARAMS (SIOCIWFIRSTPRIV+16) +/* + * arguments: + * WMI_CHANNEL_PARAMS_CMD chParams + * uses: WMI_SET_CHANNEL_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_PROBEDSSID (SIOCIWFIRSTPRIV+17) +/* + * arguments: + * WMI_PROBED_SSID_CMD probedSsids (see include/wmi.h) + * uses: WMI_SETPROBED_SSID_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_PMPARAMS (SIOCIWFIRSTPRIV+18) +/* + * arguments: + * WMI_POWER_PARAMS_CMD powerParams (see include/wmi.h) + * uses: WMI_SET_POWER_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_BADAP (SIOCIWFIRSTPRIV+19) +/* + * arguments: + * WMI_ADD_BAD_AP_CMD badAPs (see include/wmi.h) + * uses: WMI_ADD_BAD_AP_CMDID + */ + +#define AR6000_IOCTL_WMI_GET_QOS_QUEUE (SIOCIWFIRSTPRIV+20) +/* + * arguments: + * ar6000_queuereq queueRequest (see below) + */ + +#define AR6000_IOCTL_WMI_CREATE_QOS (SIOCIWFIRSTPRIV+21) +/* + * arguments: + * WMI_CREATE_PSTREAM createPstreamCmd (see include/wmi.h) + * uses: WMI_CREATE_PSTREAM_CMDID + */ + +#define AR6000_IOCTL_WMI_DELETE_QOS (SIOCIWFIRSTPRIV+22) +/* + * arguments: + * WMI_DELETE_PSTREAM_CMD deletePstreamCmd (see include/wmi.h) + * uses: WMI_DELETE_PSTREAM_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_SNRTHRESHOLD (SIOCIWFIRSTPRIV+23) +/* + * arguments: + * WMI_SNR_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h) + * uses: WMI_SNR_THRESHOLD_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24) +/* + * arguments: + * WMI_TARGET_ERROR_REPORT_BITMASK errorReportBitMask (see include/wmi.h) + * uses: WMI_TARGET_ERROR_REPORT_BITMASK_CMDID + */ + +#define AR6000_IOCTL_WMI_GET_TARGET_STATS (SIOCIWFIRSTPRIV+25) +/* + * arguments: + * TARGET_STATS *targetStats (see below) + * uses: WMI_GET_STATISTICS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_ASSOC_INFO (SIOCIWFIRSTPRIV+26) +/* + * arguments: + * WMI_SET_ASSOC_INFO_CMD setAssocInfoCmd + * uses: WMI_SET_ASSOC_INFO_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_ACCESS_PARAMS (SIOCIWFIRSTPRIV+27) +/* + * arguments: + * WMI_SET_ACCESS_PARAMS_CMD setAccessParams (see include/wmi.h) + * uses: WMI_SET_ACCESS_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_BMISS_TIME (SIOCIWFIRSTPRIV+28) +/* + * arguments: + * UINT32 beaconMissTime + * uses: WMI_SET_BMISS_TIME_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_DISC_TIMEOUT (SIOCIWFIRSTPRIV+29) +/* + * arguments: + * WMI_DISC_TIMEOUT_CMD disconnectTimeoutCmd (see include/wmi.h) + * uses: WMI_SET_DISC_TIMEOUT_CMDID + */ + +#define AR6000_IOCTL_WMI_FORCE_ASSERT (SIOCIWFIRSTPRIV+30) +/* + * Force Firmware to Assert + */ + +/* + * There is a very small space available for driver-private + * wireless ioctls. In order to circumvent this limitation, + * we multiplex a bunch of ioctls (XIOCTLs) on top of a + * single AR6000_IOCTL_EXTENDED ioctl. + */ +#define AR6000_IOCTL_EXTENDED (SIOCIWFIRSTPRIV+31) + + +/* ====BMI Extended Ioctls==== */ + +#define AR6000_XIOCTL_BMI_DONE 1 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_DONE) + * uses: BMI_DONE + */ + +#define AR6000_XIOCTL_BMI_READ_MEMORY 2 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_READ_MEMORY) + * UINT32 address + * UINT32 length + * } + * char results[length] + * } + * uses: BMI_READ_MEMORY + */ + +#define AR6000_XIOCTL_BMI_WRITE_MEMORY 3 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_MEMORY) + * UINT32 address + * UINT32 length + * char data[length] + * uses: BMI_WRITE_MEMORY + */ + +#define AR6000_XIOCTL_BMI_EXECUTE 4 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_EXECUTE) + * UINT32 TargetAddress + * UINT32 parameter + * uses: BMI_EXECUTE + */ + +#define AR6000_XIOCTL_BMI_SET_APP_START 5 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_SET_APP_START) + * UINT32 TargetAddress + * uses: BMI_SET_APP_START + */ + +#define AR6000_XIOCTL_BMI_READ_SOC_REGISTER 6 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_READ_SOC_REGISTER) + * UINT32 TargetAddress, 32-bit aligned + * } + * UINT32 result + * } + * uses: BMI_READ_SOC_REGISTER + */ + +#define AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER 7 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER) + * UINT32 TargetAddress, 32-bit aligned + * UINT32 newValue + * } + * uses: BMI_WRITE_SOC_REGISTER + */ + +#define AR6000_XIOCTL_BMI_TEST 8 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_TEST) + * UINT32 address + * UINT32 length + * UINT32 count + */ + + + +/* Historical Host-side DataSet support */ +#define AR6000_XIOCTL_UNUSED9 9 +#define AR6000_XIOCTL_UNUSED10 10 +#define AR6000_XIOCTL_UNUSED11 11 + +/* ====Misc Extended Ioctls==== */ + +#define AR6000_XIOCTL_FORCE_TARGET_RESET 12 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_FORCE_TARGET_RESET) + */ + + +#ifdef HTC_RAW_INTERFACE +/* HTC Raw Interface Ioctls */ +#define AR6000_XIOCTL_HTC_RAW_OPEN 13 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_OPEN) + */ + +#define AR6000_XIOCTL_HTC_RAW_CLOSE 14 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_CLOSE) + */ + +#define AR6000_XIOCTL_HTC_RAW_READ 15 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_READ) + * UINT32 mailboxID + * UINT32 length + * } + * results[length] + * } + */ + +#define AR6000_XIOCTL_HTC_RAW_WRITE 16 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_WRITE) + * UINT32 mailboxID + * UINT32 length + * char buffer[length] + */ +#endif /* HTC_RAW_INTERFACE */ + +#define AR6000_XIOCTL_CHECK_TARGET_READY 17 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_CHECK_TARGET_READY) + */ + + + +/* ====GPIO (General Purpose I/O) Extended Ioctls==== */ + +#define AR6000_XIOCTL_GPIO_OUTPUT_SET 18 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_OUTPUT_SET) + * ar6000_gpio_output_set_cmd_s (see below) + * uses: WMIX_GPIO_OUTPUT_SET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_INPUT_GET 19 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_INPUT_GET) + * uses: WMIX_GPIO_INPUT_GET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_REGISTER_SET 20 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_SET) + * ar6000_gpio_register_cmd_s (see below) + * uses: WMIX_GPIO_REGISTER_SET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_REGISTER_GET 21 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_GET) + * ar6000_gpio_register_cmd_s (see below) + * uses: WMIX_GPIO_REGISTER_GET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_INTR_ACK 22 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_ACK) + * ar6000_cpio_intr_ack_cmd_s (see below) + * uses: WMIX_GPIO_INTR_ACK_CMDID + */ + +#define AR6000_XIOCTL_GPIO_INTR_WAIT 23 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_WAIT) + */ + + + +/* ====more wireless commands==== */ + +#define AR6000_XIOCTL_SET_ADHOC_BSSID 24 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_ADHOC_BSSID) + * WMI_SET_ADHOC_BSSID_CMD setAdHocBssidCmd (see include/wmi.h) + */ + +#define AR6000_XIOCTL_SET_OPT_MODE 25 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_OPT_MODE) + * WMI_SET_OPT_MODE_CMD setOptModeCmd (see include/wmi.h) + * uses: WMI_SET_OPT_MODE_CMDID + */ + +#define AR6000_XIOCTL_OPT_SEND_FRAME 26 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_OPT_SEND_FRAME) + * WMI_OPT_TX_FRAME_CMD optTxFrameCmd (see include/wmi.h) + * uses: WMI_OPT_TX_FRAME_CMDID + */ + +#define AR6000_XIOCTL_SET_BEACON_INTVAL 27 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_BEACON_INTVAL) + * WMI_BEACON_INT_CMD beaconIntCmd (see include/wmi.h) + * uses: WMI_SET_BEACON_INT_CMDID + */ + + +#define IEEE80211_IOCTL_SETAUTHALG 28 + + +#define AR6000_XIOCTL_SET_VOICE_PKT_SIZE 29 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_VOICE_PKT_SIZE) + * WMI_SET_VOICE_PKT_SIZE_CMD setVoicePktSizeCmd (see include/wmi.h) + * uses: WMI_SET_VOICE_PKT_SIZE_CMDID + */ + + +#define AR6000_XIOCTL_SET_MAX_SP 30 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_MAX_SP) + * WMI_SET_MAX_SP_LEN_CMD maxSPLen(see include/wmi.h) + * uses: WMI_SET_MAX_SP_LEN_CMDID + */ + +#define AR6000_XIOCTL_WMI_GET_ROAM_TBL 31 + +#define AR6000_XIOCTL_WMI_SET_ROAM_CTRL 32 + +#define AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS 33 + + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS) + * WMI_SET_POWERSAVE_TIMERS_CMD powerSaveTimers(see include/wmi.h) + * WMI_SET_POWERSAVE_TIMERS_CMDID + */ + +#define AR6000_XIOCTRL_WMI_GET_POWER_MODE 34 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTRL_WMI_GET_POWER_MODE) + */ + +#define AR6000_XIOCTRL_WMI_SET_WLAN_STATE 35 +typedef enum { + WLAN_DISABLED, + WLAN_ENABLED +} AR6000_WLAN_STATE; +/* + * arguments: + * enable/disable + */ + +#define AR6000_XIOCTL_WMI_GET_ROAM_DATA 36 + +#define AR6000_XIOCTL_WMI_SETRETRYLIMITS 37 +/* + * arguments: + * WMI_SET_RETRY_LIMITS_CMD ibssSetRetryLimitsCmd + * uses: WMI_SET_RETRY_LIMITS_CMDID + */ + +#ifdef CONFIG_HOST_TCMD_SUPPORT +/* ====extended commands for radio test ==== */ + +#define AR6000_XIOCTL_TCMD_CONT_TX 38 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_TX) + * WMI_TCMD_CONT_TX_CMD contTxCmd (see include/wmi.h) + * uses: WMI_TCMD_CONT_TX_CMDID + */ + +#define AR6000_XIOCTL_TCMD_CONT_RX 39 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_RX) + * WMI_TCMD_CONT_RX_CMD rxCmd (see include/wmi.h) + * uses: WMI_TCMD_CONT_RX_CMDID + */ + +#define AR6000_XIOCTL_TCMD_PM 40 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TCMD_PM) + * WMI_TCMD_PM_CMD pmCmd (see include/wmi.h) + * uses: WMI_TCMD_PM_CMDID + */ + +#endif /* CONFIG_HOST_TCMD_SUPPORT */ + +#define AR6000_XIOCTL_WMI_STARTSCAN 41 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_STARTSCAN) + * UINT8 scanType + * UINT8 scanConnected + * A_BOOL forceFgScan + * uses: WMI_START_SCAN_CMDID + */ + +#define AR6000_XIOCTL_WMI_SETFIXRATES 42 + +#define AR6000_XIOCTL_WMI_GETFIXRATES 43 + + +#define AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD 44 +/* + * arguments: + * WMI_RSSI_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h) + * uses: WMI_RSSI_THRESHOLD_PARAMS_CMDID + */ + +#define AR6000_XIOCTL_WMI_CLR_RSSISNR 45 +/* + * arguments: + * WMI_CLR_RSSISNR_CMD thresholdParams (see include/wmi.h) + * uses: WMI_CLR_RSSISNR_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_LQTHRESHOLD 46 +/* + * arguments: + * WMI_LQ_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h) + * uses: WMI_LQ_THRESHOLD_PARAMS_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_RTS 47 +/* + * arguments: + * WMI_SET_RTS_MODE_CMD (see include/wmi.h) + * uses: WMI_SET_RTS_MODE_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_LPREAMBLE 48 + +#define AR6000_XIOCTL_WMI_SET_AUTHMODE 49 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_AUTHMODE) + * UINT8 mode + * uses: WMI_SET_RECONNECT_AUTH_MODE_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_REASSOCMODE 50 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_WMM) + * UINT8 mode + * uses: WMI_SET_WMM_CMDID + */ +#define AR6000_XIOCTL_WMI_SET_WMM 51 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS) + * UINT32 frequency + * UINT8 threshold + */ +#define AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS 52 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP) + * UINT32 cookie + */ +#define AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP 53 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_GET_RD) + * UINT32 regDomain + */ +#define AR6000_XIOCTL_WMI_GET_RD 54 + +#define AR6000_XIOCTL_DIAG_READ 55 + +#define AR6000_XIOCTL_DIAG_WRITE 56 + +/* + * arguments cmd (AR6000_XIOCTL_SET_TXOP) + * WMI_TXOP_CFG txopEnable + */ +#define AR6000_XIOCTL_WMI_SET_TXOP 57 + +#ifdef USER_KEYS +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_USER_SETKEYS) + * UINT32 keyOpCtrl + * uses AR6000_USER_SETKEYS_INFO + */ +#define AR6000_XIOCTL_USER_SETKEYS 58 +#endif /* USER_KEYS */ + +#define AR6000_XIOCTL_WMI_SET_KEEPALIVE 59 +/* + * arguments: + * UINT8 cmd (AR6000_XIOCTL_WMI_SET_KEEPALIVE) + * UINT8 keepaliveInterval + * uses: WMI_SET_KEEPALIVE_CMDID + */ + +#define AR6000_XIOCTL_WMI_GET_KEEPALIVE 60 +/* + * arguments: + * UINT8 cmd (AR6000_XIOCTL_WMI_GET_KEEPALIVE) + * UINT8 keepaliveInterval + * A_BOOL configured + * uses: WMI_GET_KEEPALIVE_CMDID + */ + +/* ====ROM Patching Extended Ioctls==== */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_INSTALL 61 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_INSTALL) + * UINT32 ROM Address + * UINT32 RAM Address + * UINT32 number of bytes + * UINT32 activate? (0 or 1) + * } + * A_UINT32 resulting rompatch ID + * } + * uses: BMI_ROMPATCH_INSTALL + */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL 62 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL) + * UINT32 rompatch ID + * } + * uses: BMI_ROMPATCH_UNINSTALL + */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE 63 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE) + * UINT32 rompatch count + * UINT32 rompatch IDs[rompatch count] + * } + * uses: BMI_ROMPATCH_ACTIVATE + */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE 64 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE) + * UINT32 rompatch count + * UINT32 rompatch IDs[rompatch count] + * } + * uses: BMI_ROMPATCH_DEACTIVATE + */ + +#define AR6000_XIOCTL_WMI_SET_APPIE 65 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_APPIE) + * UINT32 app_frmtype; + * UINT32 app_buflen; + * UINT8 app_buf[]; + * } + */ +#define AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER 66 +/* + * arguments: + * A_UINT32 filter_type; + */ + +#define AR6000_XIOCTL_DBGLOG_CFG_MODULE 67 + +#define AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS 68 + +#define AR6000_XIOCTL_WMI_SET_WSC_STATUS 70 +/* + * arguments: + * A_UINT32 wsc_status; + * (WSC_REG_INACTIVE or WSC_REG_ACTIVE) + */ + +/* + * arguments: + * struct { + * A_UINT8 streamType; + * A_UINT8 status; + * } + * uses: WMI_SET_BT_STATUS_CMDID + */ +#define AR6000_XIOCTL_WMI_SET_BT_STATUS 71 + +/* + * arguments: + * struct { + * A_UINT8 paramType; + * union { + * A_UINT8 noSCOPkts; + * BT_PARAMS_A2DP a2dpParams; + * BT_COEX_REGS regs; + * }; + * } + * uses: WMI_SET_BT_PARAM_CMDID + */ +#define AR6000_XIOCTL_WMI_SET_BT_PARAMS 72 + +#define AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE 73 +#define AR6000_XIOCTL_WMI_SET_WOW_MODE 74 +#define AR6000_XIOCTL_WMI_GET_WOW_LIST 75 +#define AR6000_XIOCTL_WMI_ADD_WOW_PATTERN 76 +#define AR6000_XIOCTL_WMI_DEL_WOW_PATTERN 77 + + + +#define AR6000_XIOCTL_TARGET_INFO 78 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TARGET_INFO) + * A_UINT32 TargetVersion (returned) + * A_UINT32 TargetType (returned) + * (See also bmi_msg.h target_ver and target_type) + */ + +#define AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE 79 +/* + * arguments: + * none + */ + +#define AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE 80 +/* + * This ioctl is used to emulate traffic activity + * timeouts. Activity/inactivity will trigger the driver + * to re-balance credits. + * + * arguments: + * ar6000_traffic_activity_change + */ + +#define AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS 81 +/* + * This ioctl is used to set the connect control flags + * + * arguments: + * A_UINT32 connectCtrlFlags + */ + +#define AR6000_XIOCTL_WMI_SET_AKMP_PARAMS 82 +/* + * This IOCTL sets any Authentication,Key Management and Protection + * related parameters. This is used along with the information set in + * Connect Command. + * Currently this enables Multiple PMKIDs to an AP. + * + * arguments: + * struct { + * A_UINT32 akmpInfo; + * } + * uses: WMI_SET_AKMP_PARAMS_CMD + */ + +#define AR6000_XIOCTL_WMI_GET_PMKID_LIST 83 + +#define AR6000_XIOCTL_WMI_SET_PMKID_LIST 84 +/* + * This IOCTL is used to set a list of PMKIDs. This list of + * PMKIDs is used in the [Re]AssocReq Frame. This list is used + * only if the MultiPMKID option is enabled via the + * AR6000_XIOCTL_WMI_SET_AKMP_PARAMS IOCTL. + * + * arguments: + * struct { + * A_UINT32 numPMKID; + * WMI_PMKID pmkidList[WMI_MAX_PMKID_CACHE]; + * } + * uses: WMI_SET_PMKIDLIST_CMD + */ + +#define AR6000_XIOCTL_WMI_SET_PARAMS 85 +#define AR6000_XIOCTL_WMI_SET_MCAST_FILTER 86 +#define AR6000_XIOCTL_WMI_DEL_MCAST_FILTER 87 + + +/* Historical DSETPATCH support for INI patches */ +#define AR6000_XIOCTL_UNUSED90 90 + + +/* Support LZ-compressed firmware download */ +#define AR6000_XIOCTL_BMI_LZ_STREAM_START 91 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_LZ_STREAM_START) + * UINT32 address + * uses: BMI_LZ_STREAM_START + */ + +#define AR6000_XIOCTL_BMI_LZ_DATA 92 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_LZ_DATA) + * UINT32 length + * char data[length] + * uses: BMI_LZ_DATA + */ + +#define AR6000_XIOCTL_PROF_CFG 93 +/* + * arguments: + * A_UINT32 period + * A_UINT32 nbins + */ + +#define AR6000_XIOCTL_PROF_ADDR_SET 94 +/* + * arguments: + * A_UINT32 Target address + */ + +#define AR6000_XIOCTL_PROF_START 95 + +#define AR6000_XIOCTL_PROF_STOP 96 + +#define AR6000_XIOCTL_PROF_COUNT_GET 97 + +#define AR6000_XIOCTL_WMI_ABORT_SCAN 98 + +/* + * AP mode + */ +#define AR6000_XIOCTL_AP_GET_STA_LIST 99 + +#define AR6000_XIOCTL_AP_HIDDEN_SSID 100 + +#define AR6000_XIOCTL_AP_SET_NUM_STA 101 + +#define AR6000_XIOCTL_AP_SET_ACL_MAC 102 + +#define AR6000_XIOCTL_AP_GET_ACL_LIST 103 + +#define AR6000_XIOCTL_AP_COMMIT_CONFIG 104 + +#define IEEE80211_IOCTL_GETWPAIE 105 + +#define AR6000_XIOCTL_AP_CONN_INACT_TIME 106 + +#define AR6000_XIOCTL_AP_PROT_SCAN_TIME 107 + +#define AR6000_XIOCTL_AP_SET_COUNTRY 108 + +#define AR6000_XIOCTL_AP_SET_DTIM 109 + + + + +#define AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT 110 + +#define AR6000_XIOCTL_SET_IP 111 + +#define AR6000_XIOCTL_AP_SET_ACL_POLICY 112 + +#define AR6000_XIOCTL_AP_INTRA_BSS_COMM 113 + +/* used by AR6000_IOCTL_WMI_GETREV */ +struct ar6000_version { + A_UINT32 host_ver; + A_UINT32 target_ver; + A_UINT32 wlan_ver; +}; + +/* used by AR6000_IOCTL_WMI_GET_QOS_QUEUE */ +struct ar6000_queuereq { + A_UINT8 trafficClass; + A_UINT16 activeTsids; +}; + +/* used by AR6000_IOCTL_WMI_GET_TARGET_STATS */ +typedef struct targetStats_t { + A_UINT64 tx_packets; + A_UINT64 tx_bytes; + A_UINT64 tx_unicast_pkts; + A_UINT64 tx_unicast_bytes; + A_UINT64 tx_multicast_pkts; + A_UINT64 tx_multicast_bytes; + A_UINT64 tx_broadcast_pkts; + A_UINT64 tx_broadcast_bytes; + A_UINT64 tx_rts_success_cnt; + A_UINT64 tx_packet_per_ac[4]; + + A_UINT64 tx_errors; + A_UINT64 tx_failed_cnt; + A_UINT64 tx_retry_cnt; + A_UINT64 tx_mult_retry_cnt; + A_UINT64 tx_rts_fail_cnt; + + A_UINT64 rx_packets; + A_UINT64 rx_bytes; + A_UINT64 rx_unicast_pkts; + A_UINT64 rx_unicast_bytes; + A_UINT64 rx_multicast_pkts; + A_UINT64 rx_multicast_bytes; + A_UINT64 rx_broadcast_pkts; + A_UINT64 rx_broadcast_bytes; + A_UINT64 rx_fragment_pkt; + + A_UINT64 rx_errors; + A_UINT64 rx_crcerr; + A_UINT64 rx_key_cache_miss; + A_UINT64 rx_decrypt_err; + A_UINT64 rx_duplicate_frames; + + A_UINT64 tkip_local_mic_failure; + A_UINT64 tkip_counter_measures_invoked; + A_UINT64 tkip_replays; + A_UINT64 tkip_format_errors; + A_UINT64 ccmp_format_errors; + A_UINT64 ccmp_replays; + + A_UINT64 power_save_failure_cnt; + + A_UINT64 cs_bmiss_cnt; + A_UINT64 cs_lowRssi_cnt; + A_UINT64 cs_connect_cnt; + A_UINT64 cs_disconnect_cnt; + + A_INT32 tx_unicast_rate; + A_INT32 rx_unicast_rate; + + A_UINT32 lq_val; + + A_UINT32 wow_num_pkts_dropped; + A_UINT16 wow_num_events_discarded; + + A_INT16 noise_floor_calibation; + A_INT16 cs_rssi; + A_INT16 cs_aveBeacon_rssi; + A_UINT8 cs_aveBeacon_snr; + A_UINT8 cs_lastRoam_msec; + A_UINT8 cs_snr; + + A_UINT8 wow_num_host_pkt_wakeups; + A_UINT8 wow_num_host_event_wakeups; + + A_UINT32 arp_received; + A_UINT32 arp_matched; + A_UINT32 arp_replied; +}TARGET_STATS; + +typedef struct targetStats_cmd_t { + TARGET_STATS targetStats; + int clearStats; +} TARGET_STATS_CMD; + +/* used by AR6000_XIOCTL_USER_SETKEYS */ + +/* + * Setting this bit to 1 doesnot initialize the RSC on the firmware + */ +#define AR6000_XIOCTL_USER_SETKEYS_RSC_CTRL 1 +#define AR6000_USER_SETKEYS_RSC_UNCHANGED 0x00000002 + +typedef struct { + A_UINT32 keyOpCtrl; /* Bit Map of Key Mgmt Ctrl Flags */ +} AR6000_USER_SETKEYS_INFO; + + +/* used by AR6000_XIOCTL_GPIO_OUTPUT_SET */ +struct ar6000_gpio_output_set_cmd_s { + A_UINT32 set_mask; + A_UINT32 clear_mask; + A_UINT32 enable_mask; + A_UINT32 disable_mask; +}; + +/* + * used by AR6000_XIOCTL_GPIO_REGISTER_GET and AR6000_XIOCTL_GPIO_REGISTER_SET + */ +struct ar6000_gpio_register_cmd_s { + A_UINT32 gpioreg_id; + A_UINT32 value; +}; + +/* used by AR6000_XIOCTL_GPIO_INTR_ACK */ +struct ar6000_gpio_intr_ack_cmd_s { + A_UINT32 ack_mask; +}; + +/* used by AR6000_XIOCTL_GPIO_INTR_WAIT */ +struct ar6000_gpio_intr_wait_cmd_s { + A_UINT32 intr_mask; + A_UINT32 input_values; +}; + +/* used by the AR6000_XIOCTL_DBGLOG_CFG_MODULE */ +typedef struct ar6000_dbglog_module_config_s { + A_UINT32 valid; + A_UINT16 mmask; + A_UINT16 tsr; + A_BOOL rep; + A_UINT16 size; +} DBGLOG_MODULE_CONFIG; + +typedef struct user_rssi_thold_t { + A_INT16 tag; + A_INT16 rssi; +} USER_RSSI_THOLD; + +typedef struct user_rssi_params_t { + A_UINT8 weight; + A_UINT32 pollTime; + USER_RSSI_THOLD tholds[12]; +} USER_RSSI_PARAMS; + +/* + * Host driver may have some config parameters. Typically, these + * config params are one time config parameters. These could + * correspond to any of the underlying modules. Host driver exposes + * an api for the underlying modules to get this config. + */ +#define AR6000_DRIVER_CFG_BASE 0x8000 + +/* Should driver perform wlan node caching? */ +#define AR6000_DRIVER_CFG_GET_WLANNODECACHING 0x8001 +/*Should we log raw WMI msgs */ +#define AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS 0x8002 + +/* used by AR6000_XIOCTL_DIAG_READ & AR6000_XIOCTL_DIAG_WRITE */ +struct ar6000_diag_window_cmd_s { + unsigned int addr; + unsigned int value; +}; + + +struct ar6000_traffic_activity_change { + A_UINT32 StreamID; /* stream ID to indicate activity change */ + A_UINT32 Active; /* active (1) or inactive (0) */ +}; + +/* Used with AR6000_XIOCTL_PROF_COUNT_GET */ +struct prof_count_s { + A_UINT32 addr; /* bin start address */ + A_UINT32 count; /* hit count */ +}; + +#ifdef __cplusplus +} +#endif +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/athendpack.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/athendpack.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/athendpack.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/athendpack.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,49 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// end compiler-specific structure packing +// +// Author(s): ="Atheros" +//============================================================================== +#ifdef VXWORKS +#endif /* VXWORKS */ + +#if defined(LINUX) || defined(__linux__) +#endif /* LINUX */ + +#ifdef QNX +#endif /* QNX */ + +#ifdef INTEGRITY +#include "integrity/athendpack_integrity.h" +#endif /* INTEGRITY */ + +#ifdef NUCLEUS +#endif /* NUCLEUS */ + + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/athendpack_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/athendpack_wince.h" +#endif /* WINCE */ + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/athstartpack.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/athstartpack.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/athstartpack.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/athstartpack.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,48 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// start compiler-specific structure packing +// +// Author(s): ="Atheros" +//============================================================================== +#ifdef VXWORKS +#endif /* VXWORKS */ + +#if defined(LINUX) || defined(__linux__) +#endif /* LINUX */ + +#ifdef QNX +#endif /* QNX */ + +#ifdef INTEGRITY +#include "integrity/athstartpack_integrity.h" +#endif /* INTEGRITY */ + +#ifdef NUCLEUS +#endif /* NUCLEUS */ + +#ifdef UNDER_NWIFI +#include "../os/windows/common/include/athstartpack_wince.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/wince/include/athstartpack_wince.h" +#endif /* WINCE */ + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/athtypes_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/athtypes_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/athtypes_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/athtypes_linux.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,56 @@ +/* + * $Id: //depot/sw/releases/olca2.2.0/host/os/linux/include/athtypes_linux.h#1 $ + * + * This file contains the definitions of the basic atheros data types. + * It is used to map the data types in atheros files to a platform specific + * type. + * + * Copyright 2003-2005 Atheros Communications, Inc., All Rights Reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _ATHTYPES_LINUX_H_ +#define _ATHTYPES_LINUX_H_ + +#ifdef ANDROID +#include +#include +#else +#ifdef __KERNEL__ +#include +#endif +#endif + +typedef int8_t A_INT8; +typedef int16_t A_INT16; +typedef int32_t A_INT32; +typedef int64_t A_INT64; + +typedef u_int8_t A_UINT8; +typedef u_int16_t A_UINT16; +typedef u_int32_t A_UINT32; +typedef u_int64_t A_UINT64; + +typedef int A_BOOL; +typedef char A_CHAR; +typedef unsigned char A_UCHAR; +typedef unsigned long A_ATH_TIMER; + + +#endif /* _ATHTYPES_LINUX_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/bmi.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/bmi.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/bmi.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/bmi.c 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,879 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// +// Author(s): ="Atheros" +//============================================================================== + +#include "hif.h" +#include "bmi.h" +#include "htc_api.h" +#include "bmi_internal.h" + +/* +Although we had envisioned BMI to run on top of HTC, this is not how the +final implementation ended up. On the Target side, BMI is a part of the BSP +and does not use the HTC protocol nor even DMA -- it is intentionally kept +very simple. +*/ + +static A_BOOL pendingEventsFuncCheck = FALSE; + +/* APIs visible to the driver */ +void +BMIInit(void) +{ + bmiDone = FALSE; + pendingEventsFuncCheck = FALSE; +} + +A_STATUS +BMIDone(HIF_DEVICE *device) +{ + A_STATUS status; + A_UINT32 cid; + + if (bmiDone) { + AR_DEBUG_PRINTF (ATH_DEBUG_BMI, ("BMIDone skipped\n")); + return A_OK; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Enter (device: 0x%p)\n", device)); + bmiDone = TRUE; + cid = BMI_DONE; + + status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid)); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Exit\n")); + + return A_OK; +} + +A_STATUS +BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info) +{ + A_STATUS status; + A_UINT32 cid; + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Enter (device: 0x%p)\n", device)); + cid = BMI_GET_TARGET_INFO; + + status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid)); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_ver, + sizeof(targ_info->target_ver), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Version from the device\n")); + return A_ERROR; + } + + if (targ_info->target_ver == TARGET_VERSION_SENTINAL) { + /* Determine how many bytes are in the Target's targ_info */ + status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_info_byte_count, + sizeof(targ_info->target_info_byte_count), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info Byte Count from the device\n")); + return A_ERROR; + } + + /* + * The Target's targ_info doesn't match the Host's targ_info. + * We need to do some backwards compatibility work to make this OK. + */ + A_ASSERT(targ_info->target_info_byte_count == sizeof(*targ_info)); + + /* Read the remainder of the targ_info */ + status = bmiBufferReceive(device, + ((A_UCHAR *)targ_info)+sizeof(targ_info->target_info_byte_count), + sizeof(*targ_info)-sizeof(targ_info->target_info_byte_count), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info (%d bytes) from the device\n", + targ_info->target_info_byte_count)); + return A_ERROR; + } + } else { + /* + * Target must be an AR6001 whose firmware does not + * support BMI_GET_TARGET_INFO. Construct the data + * that it would have sent. + */ + targ_info->target_info_byte_count=sizeof(*targ_info); + targ_info->target_type=TARGET_TYPE_AR6001; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Exit (ver: 0x%x type: 0x%x)\n", + targ_info->target_ver, targ_info->target_type)); + + return A_OK; +} + +A_STATUS +BMIReadMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + A_UINT32 remaining, rxlen; + static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)]; + memset (&data, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Read Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n", + device, address, length)); + + cid = BMI_READ_MEMORY; + + remaining = length; + + while (remaining) + { + rxlen = (remaining < BMI_DATASZ_MAX) ? remaining : BMI_DATASZ_MAX; + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&data[offset], &rxlen, sizeof(rxlen)); + offset += sizeof(length); + + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + status = bmiBufferReceive(device, data, rxlen, TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + A_MEMCPY(&buffer[length - remaining], data, rxlen); + remaining -= rxlen; address += rxlen; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read Memory: Exit\n")); + return A_OK; +} + +A_STATUS +BMIWriteMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + A_UINT32 remaining, txlen; + const A_UINT32 header = sizeof(cid) + sizeof(address) + sizeof(length); + static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)]; + memset (&data, 0, BMI_DATASZ_MAX+header); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Write Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n", + device, address, length)); + + cid = BMI_WRITE_MEMORY; + + remaining = length; + while (remaining) + { + txlen = (remaining < (BMI_DATASZ_MAX - header)) ? + remaining : (BMI_DATASZ_MAX - header); + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&data[offset], &txlen, sizeof(txlen)); + offset += sizeof(txlen); + A_MEMCPY(&data[offset], &buffer[length - remaining], txlen); + offset += txlen; + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + remaining -= txlen; address += txlen; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Write Memory: Exit\n")); + + return A_OK; +} + +A_STATUS +BMIExecute(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address) + sizeof(*param)]; + memset (&data, 0, sizeof(cid) + sizeof(address) + sizeof(*param)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Execute: Enter (device: 0x%p, address: 0x%x, param: %d)\n", + device, address, *param)); + + cid = BMI_EXECUTE; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&data[offset], param, sizeof(*param)); + offset += sizeof(*param); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, data, sizeof(*param), FALSE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + + A_MEMCPY(param, data, sizeof(*param)); + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Execute: Exit (param: %d)\n", *param)); + return A_OK; +} + +A_STATUS +BMISetAppStart(HIF_DEVICE *device, + A_UINT32 address) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address)]; + memset (&data, 0, sizeof(cid) + sizeof(address)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Set App Start: Enter (device: 0x%p, address: 0x%x)\n", + device, address)); + + cid = BMI_SET_APP_START; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Set App Start: Exit\n")); + return A_OK; +} + +A_STATUS +BMIReadSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address)]; + memset (&data, 0, sizeof(cid) + sizeof(address)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Read SOC Register: Enter (device: 0x%p, address: 0x%x)\n", + device, address)); + + cid = BMI_READ_SOC_REGISTER; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, data, sizeof(*param), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + A_MEMCPY(param, data, sizeof(*param)); + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit (value: %d)\n", *param)); + return A_OK; +} + +A_STATUS +BMIWriteSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 param) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address) + sizeof(param)]; + + memset (&data, 0, sizeof(cid) + sizeof(address) + sizeof(param)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Write SOC Register: Enter (device: 0x%p, address: 0x%x, param: %d)\n", + device, address, param)); + + cid = BMI_WRITE_SOC_REGISTER; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&data[offset], ¶m, sizeof(param)); + offset += sizeof(param); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit\n")); + return A_OK; +} + +A_STATUS +BMIrompatchInstall(HIF_DEVICE *device, + A_UINT32 ROM_addr, + A_UINT32 RAM_addr, + A_UINT32 nbytes, + A_UINT32 do_activate, + A_UINT32 *rompatch_id) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) + + sizeof(nbytes) + sizeof(do_activate)]; + + memset (&data, 0, sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) + + sizeof(nbytes) + sizeof(do_activate)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI rompatch Install: Enter (device: 0x%p, ROMaddr: 0x%x, RAMaddr: 0x%x length: %d activate: %d)\n", + device, ROM_addr, RAM_addr, nbytes, do_activate)); + + cid = BMI_ROMPATCH_INSTALL; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &ROM_addr, sizeof(ROM_addr)); + offset += sizeof(ROM_addr); + A_MEMCPY(&data[offset], &RAM_addr, sizeof(RAM_addr)); + offset += sizeof(RAM_addr); + A_MEMCPY(&data[offset], &nbytes, sizeof(nbytes)); + offset += sizeof(nbytes); + A_MEMCPY(&data[offset], &do_activate, sizeof(do_activate)); + offset += sizeof(do_activate); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, (A_UCHAR *)rompatch_id, sizeof(*rompatch_id), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch Install: (rompatch_id=%d)\n", *rompatch_id)); + return A_OK; +} + +A_STATUS +BMIrompatchUninstall(HIF_DEVICE *device, + A_UINT32 rompatch_id) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(rompatch_id)]; + memset (&data, 0, sizeof(cid) + sizeof(rompatch_id)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI rompatch Uninstall: Enter (device: 0x%p, rompatch_id: %d)\n", + device, rompatch_id)); + + cid = BMI_ROMPATCH_UNINSTALL; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &rompatch_id, sizeof(rompatch_id)); + offset += sizeof(rompatch_id); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch UNinstall: (rompatch_id=0x%x)\n", rompatch_id)); + return A_OK; +} + +static A_STATUS +_BMIrompatchChangeActivation(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list, + A_UINT32 do_activate) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count)]; + A_UINT32 length; + + memset (&data, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Change rompatch Activation: Enter (device: 0x%p, count: %d)\n", + device, rompatch_count)); + + cid = do_activate ? BMI_ROMPATCH_ACTIVATE : BMI_ROMPATCH_DEACTIVATE; + + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &rompatch_count, sizeof(rompatch_count)); + offset += sizeof(rompatch_count); + length = rompatch_count * sizeof(*rompatch_list); + A_MEMCPY(&data[offset], rompatch_list, length); + offset += length; + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Change rompatch Activation: Exit\n")); + + return A_OK; +} + +A_STATUS +BMIrompatchActivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list) +{ + return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 1); +} + +A_STATUS +BMIrompatchDeactivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list) +{ + return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 0); +} + +A_STATUS +BMILZData(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + A_UINT32 remaining, txlen; + const A_UINT32 header = sizeof(cid) + sizeof(length); + static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(length)]; + + memset (&data, 0, BMI_DATASZ_MAX+header); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Send LZ Data: Enter (device: 0x%p, length: %d)\n", + device, length)); + + cid = BMI_LZ_DATA; + + remaining = length; + while (remaining) + { + txlen = (remaining < (BMI_DATASZ_MAX - header)) ? + remaining : (BMI_DATASZ_MAX - header); + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &txlen, sizeof(txlen)); + offset += sizeof(txlen); + A_MEMCPY(&data[offset], &buffer[length - remaining], txlen); + offset += txlen; + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + remaining -= txlen; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI LZ Data: Exit\n")); + + return A_OK; +} + +A_STATUS +BMILZStreamStart(HIF_DEVICE *device, + A_UINT32 address) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + static A_UCHAR data[sizeof(cid) + sizeof(address)]; + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI LZ Stream Start: Enter (device: 0x%p, address: 0x%x)\n", + device, address)); + + cid = BMI_LZ_STREAM_START; + offset = 0; + A_MEMCPY(&data[offset], &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&data[offset], &address, sizeof(address)); + offset += sizeof(address); + status = bmiBufferSend(device, data, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to Start LZ Stream to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI LZ Stream Start: Exit\n")); + + return A_OK; +} + +/* BMI Access routines */ +A_STATUS +bmiBufferSend(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_STATUS status; + A_UINT32 timeout; + A_UINT32 address; + static A_UINT32 cmdCredits; + A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX]; + + HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR, + &mboxAddress[0], sizeof(mboxAddress)); + + cmdCredits = 0; + timeout = BMI_COMMUNICATION_TIMEOUT; + + while(timeout-- && !cmdCredits) { + /* Read the counter register to get the command credits */ + address = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4; + /* hit the credit counter with a 4-byte access, the first byte read will hit the counter and cause + * a decrement, while the remaining 3 bytes has no effect. The rationale behind this is to + * make all HIF accesses 4-byte aligned */ + status = HIFReadWrite(device, address, (A_UINT8 *)&cmdCredits, 4, + HIF_RD_SYNC_BYTE_INC, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to decrement the command credit count register\n")); + return A_ERROR; + } + /* the counter is only 8=bits, ignore anything in the upper 3 bytes */ + cmdCredits &= 0xFF; + } + + if (cmdCredits) { + address = mboxAddress[ENDPOINT1]; + status = HIFReadWrite(device, address, buffer, length, + HIF_WR_SYNC_BYTE_INC, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to send the BMI data to the device\n")); + return A_ERROR; + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout - bmiBufferSend\n")); + return A_ERROR; + } + + return status; +} + +A_STATUS +bmiBufferReceive(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length, + A_BOOL want_timeout) +{ + A_STATUS status; + A_UINT32 address; + A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX]; + HIF_PENDING_EVENTS_INFO hifPendingEvents; + static HIF_PENDING_EVENTS_FUNC getPendingEventsFunc = NULL; + + if (!pendingEventsFuncCheck) { + /* see if the HIF layer implements an alternative function to get pending events + * do this only once! */ + HIFConfigureDevice(device, + HIF_DEVICE_GET_PENDING_EVENTS_FUNC, + &getPendingEventsFunc, + sizeof(getPendingEventsFunc)); + pendingEventsFuncCheck = TRUE; + } + + HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR, + &mboxAddress[0], sizeof(mboxAddress)); + + /* + * During normal bootup, small reads may be required. + * Rather than issue an HIF Read and then wait as the Target + * adds successive bytes to the FIFO, we wait here until + * we know that response data is available. + * + * This allows us to cleanly timeout on an unexpected + * Target failure rather than risk problems at the HIF level. In + * particular, this avoids SDIO timeouts and possibly garbage + * data on some host controllers. And on an interconnect + * such as Compact Flash (as well as some SDIO masters) which + * does not provide any indication on data timeout, it avoids + * a potential hang or garbage response. + * + * Synchronization is more difficult for reads larger than the + * size of the MBOX FIFO (128B), because the Target is unable + * to push the 129th byte of data until AFTER the Host posts an + * HIF Read and removes some FIFO data. So for large reads the + * Host proceeds to post an HIF Read BEFORE all the data is + * actually available to read. Fortunately, large BMI reads do + * not occur in practice -- they're supported for debug/development. + * + * So Host/Target BMI synchronization is divided into these cases: + * CASE 1: length < 4 + * Should not happen + * + * CASE 2: 4 <= length <= 128 + * Wait for first 4 bytes to be in FIFO + * If CONSERVATIVE_BMI_READ is enabled, also wait for + * a BMI command credit, which indicates that the ENTIRE + * response is available in the the FIFO + * + * CASE 3: length > 128 + * Wait for the first 4 bytes to be in FIFO + * + * For most uses, a small timeout should be sufficient and we will + * usually see a response quickly; but there may be some unusual + * (debug) cases of BMI_EXECUTE where we want an larger timeout. + * For now, we use an unbounded busy loop while waiting for + * BMI_EXECUTE. + * + * If BMI_EXECUTE ever needs to support longer-latency execution, + * especially in production, this code needs to be enhanced to sleep + * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently + * a function of Host processor speed. + */ + if (length >= 4) { /* NB: Currently, always true */ + /* + * NB: word_available is declared static for esoteric reasons + * having to do with protection on some OSes. + */ + static A_UINT32 word_available; + A_UINT32 timeout; + + word_available = 0; + timeout = BMI_COMMUNICATION_TIMEOUT; + while((!want_timeout || timeout--) && !word_available) { + + if (getPendingEventsFunc != NULL) { + status = getPendingEventsFunc(device, + &hifPendingEvents, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMI: Failed to get pending events \n")); + break; + } + + if (hifPendingEvents.AvailableRecvBytes >= sizeof(A_UINT32)) { + word_available = 1; + } + continue; + } + + status = HIFReadWrite(device, RX_LOOKAHEAD_VALID_ADDRESS, (A_UINT8 *)&word_available, + sizeof(word_available), HIF_RD_SYNC_BYTE_INC, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read RX_LOOKAHEAD_VALID register\n")); + return A_ERROR; + } + /* We did a 4-byte read to the same register; all we really want is one bit */ + word_available &= (1 << ENDPOINT1); + } + + if (!word_available) { + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Communication timeout - bmiBufferReceive FIFO empty\n")); + return A_ERROR; + } + } + +#define CONSERVATIVE_BMI_READ 0 +#if CONSERVATIVE_BMI_READ + /* + * This is an extra-conservative CREDIT check. It guarantees + * that ALL data is available in the FIFO before we start to + * read from the interconnect. + * + * This credit check is useless when firmware chooses to + * allow multiple outstanding BMI Command Credits, since the next + * credit will already be present. To restrict the Target to one + * BMI Command Credit, see HI_OPTION_BMI_CRED_LIMIT. + * + * And for large reads (when HI_OPTION_BMI_CRED_LIMIT is set) + * we cannot wait for the next credit because the Target's FIFO + * will not hold the entire response. So we need the Host to + * start to empty the FIFO sooner. (And again, large reads are + * not used in practice; they are for debug/development only.) + * + * For a more conservative Host implementation (which would be + * safer for a Compact Flash interconnect): + * Set CONSERVATIVE_BMI_READ (above) to 1 + * Set HI_OPTION_BMI_CRED_LIMIT and + * reduce BMI_DATASZ_MAX to 32 or 64 + */ + if ((length > 4) && (length < 128)) { /* check against MBOX FIFO size */ + /* + * NB: cmdCredits is declared static for esoteric reasons + * having to do with protection on some OSes. + */ + static A_UINT32 cmdCredits; + A_UINT32 timeout; + + cmdCredits = 0; + timeout = BMI_COMMUNICATION_TIMEOUT; + while((!want_timeout || timeout--) && !cmdCredits) { + /* Read the counter register to get the command credits */ + address = COUNT_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 1; + /* read the counter using a 4-byte read. Since the counter is NOT auto-decrementing, + * we can read this counter multiple times using a non-incrementing address mode. + * The rationale here is to make all HIF accesses a multiple of 4 bytes */ + status = HIFReadWrite(device, address, (A_UINT8 *)&cmdCredits, sizeof(cmdCredits), + HIF_RD_SYNC_BYTE_FIX, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the command credit count register\n")); + return A_ERROR; + } + /* we did a 4-byte read to the same count register so mask off upper bytes */ + cmdCredits &= 0xFF; + } + + if (!cmdCredits) { + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Communication timeout- bmiBufferReceive no credit\n")); + return A_ERROR; + } + } +#endif + + address = mboxAddress[ENDPOINT1]; + status = HIFReadWrite(device, address, buffer, length, HIF_RD_SYNC_BYTE_INC, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the BMI data from the device\n")); + return A_ERROR; + } + + return A_OK; +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/bmi.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/bmi.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/bmi.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/bmi.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,115 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// BMI declarations and prototypes +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _BMI_H_ +#define _BMI_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Header files */ +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "hif.h" +#include "a_osapi.h" +#include "bmi_msg.h" + +void +BMIInit(void); + +A_STATUS +BMIDone(HIF_DEVICE *device); + +A_STATUS +BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info); + +A_STATUS +BMIReadMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length); + +A_STATUS +BMIWriteMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length); + +A_STATUS +BMIExecute(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param); + +A_STATUS +BMISetAppStart(HIF_DEVICE *device, + A_UINT32 address); + +A_STATUS +BMIReadSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param); + +A_STATUS +BMIWriteSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 param); + +A_STATUS +BMIrompatchInstall(HIF_DEVICE *device, + A_UINT32 ROM_addr, + A_UINT32 RAM_addr, + A_UINT32 nbytes, + A_UINT32 do_activate, + A_UINT32 *patch_id); + +A_STATUS +BMIrompatchUninstall(HIF_DEVICE *device, + A_UINT32 rompatch_id); + +A_STATUS +BMIrompatchActivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list); + +A_STATUS +BMIrompatchDeactivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list); + +A_STATUS +BMILZStreamStart(HIF_DEVICE *device, + A_UINT32 address); + +A_STATUS +BMILZData(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length); + +#ifdef __cplusplus +} +#endif + +#endif /* _BMI_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/bmi_internal.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/bmi_internal.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/bmi_internal.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/bmi_internal.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,51 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef BMI_INTERNAL_H +#define BMI_INTERNAL_H + +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "a_debug.h" +#include "mbox_host_reg.h" +#include "bmi_msg.h" + +#define BMI_COMMUNICATION_TIMEOUT 100000 + +/* ------ Global Variable Declarations ------- */ +A_BOOL bmiDone; + +A_STATUS +bmiBufferSend(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length); + +A_STATUS +bmiBufferReceive(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length, + A_BOOL want_timeout); + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/bmi_msg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/bmi_msg.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/bmi_msg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/bmi_msg.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,235 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __BMI_MSG_H__ +#define __BMI_MSG_H__ + +/* + * Bootloader Messaging Interface (BMI) + * + * BMI is a very simple messaging interface used during initialization + * to read memory, write memory, execute code, and to define an + * application entry PC. + * + * It is used to download an application to AR6K, to provide + * patches to code that is already resident on AR6K, and generally + * to examine and modify state. The Host has an opportunity to use + * BMI only once during bootup. Once the Host issues a BMI_DONE + * command, this opportunity ends. + * + * The Host writes BMI requests to mailbox0, and reads BMI responses + * from mailbox0. BMI requests all begin with a command + * (see below for specific commands), and are followed by + * command-specific data. + * + * Flow control: + * The Host can only issue a command once the Target gives it a + * "BMI Command Credit", using AR6K Counter #4. As soon as the + * Target has completed a command, it issues another BMI Command + * Credit (so the Host can issue the next command). + * + * BMI handles all required Target-side cache flushing. + */ + + +/* Maximum data size used for BMI transfers */ +#define BMI_DATASZ_MAX 256 + +/* BMI Commands */ + +#define BMI_NO_COMMAND 0 + +#define BMI_DONE 1 + /* + * Semantics: Host is done using BMI + * Request format: + * A_UINT32 command (BMI_DONE) + * Response format: none + */ + +#define BMI_READ_MEMORY 2 + /* + * Semantics: Host reads AR6K memory + * Request format: + * A_UINT32 command (BMI_READ_MEMORY) + * A_UINT32 address + * A_UINT32 length, at most BMI_DATASZ_MAX + * Response format: + * A_UINT8 data[length] + */ + +#define BMI_WRITE_MEMORY 3 + /* + * Semantics: Host writes AR6K memory + * Request format: + * A_UINT32 command (BMI_WRITE_MEMORY) + * A_UINT32 address + * A_UINT32 length, at most BMI_DATASZ_MAX + * A_UINT8 data[length] + * Response format: none + */ + +#define BMI_EXECUTE 4 + /* + * Semantics: Causes AR6K to execute code + * Request format: + * A_UINT32 command (BMI_EXECUTE) + * A_UINT32 address + * A_UINT32 parameter + * Response format: + * A_UINT32 return value + */ + +#define BMI_SET_APP_START 5 + /* + * Semantics: Set Target application starting address + * Request format: + * A_UINT32 command (BMI_SET_APP_START) + * A_UINT32 address + * Response format: none + */ + +#define BMI_READ_SOC_REGISTER 6 + /* + * Semantics: Read a 32-bit Target SOC register. + * Request format: + * A_UINT32 command (BMI_READ_REGISTER) + * A_UINT32 address + * Response format: + * A_UINT32 value + */ + +#define BMI_WRITE_SOC_REGISTER 7 + /* + * Semantics: Write a 32-bit Target SOC register. + * Request format: + * A_UINT32 command (BMI_WRITE_REGISTER) + * A_UINT32 address + * A_UINT32 value + * + * Response format: none + */ + +#define BMI_GET_TARGET_ID 8 +#define BMI_GET_TARGET_INFO 8 + /* + * Semantics: Fetch the 4-byte Target information + * Request format: + * A_UINT32 command (BMI_GET_TARGET_ID/INFO) + * Response format1 (old firmware): + * A_UINT32 TargetVersionID + * Response format2 (newer firmware): + * A_UINT32 TARGET_VERSION_SENTINAL + * struct bmi_target_info; + */ + +struct bmi_target_info { + A_UINT32 target_info_byte_count; /* size of this structure */ + A_UINT32 target_ver; /* Target Version ID */ + A_UINT32 target_type; /* Target type */ +}; +#define TARGET_VERSION_SENTINAL 0xffffffff +#define TARGET_TYPE_AR6001 1 +#define TARGET_TYPE_AR6002 2 +#define TARGET_TYPE_AR6003 3 + + +#define BMI_ROMPATCH_INSTALL 9 + /* + * Semantics: Install a ROM Patch. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_INSTALL) + * A_UINT32 Target ROM Address + * A_UINT32 Target RAM Address + * A_UINT32 Size, in bytes + * A_UINT32 Activate? 1-->activate; + * 0-->install but do not activate + * Response format: + * A_UINT32 PatchID + */ + +#define BMI_ROMPATCH_UNINSTALL 10 + /* + * Semantics: Uninstall a previously-installed ROM Patch, + * automatically deactivating, if necessary. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_UNINSTALL) + * A_UINT32 PatchID + * + * Response format: none + */ + +#define BMI_ROMPATCH_ACTIVATE 11 + /* + * Semantics: Activate a list of previously-installed ROM Patches. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_ACTIVATE) + * A_UINT32 rompatch_count + * A_UINT32 PatchID[rompatch_count] + * + * Response format: none + */ + +#define BMI_ROMPATCH_DEACTIVATE 12 + /* + * Semantics: Deactivate a list of active ROM Patches. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_DEACTIVATE) + * A_UINT32 rompatch_count + * A_UINT32 PatchID[rompatch_count] + * + * Response format: none + */ + + +#define BMI_LZ_STREAM_START 13 + /* + * Semantics: Begin an LZ-compressed stream of input + * which is to be uncompressed by the Target to an + * output buffer at address. The output buffer must + * be sufficiently large to hold the uncompressed + * output from the compressed input stream. This BMI + * command should be followed by a series of 1 or more + * BMI_LZ_DATA commands. + * A_UINT32 command (BMI_LZ_STREAM_START) + * A_UINT32 address + * Note: Not supported on all versions of ROM firmware. + */ + +#define BMI_LZ_DATA 14 + /* + * Semantics: Host writes AR6K memory with LZ-compressed + * data which is uncompressed by the Target. This command + * must be preceded by a BMI_LZ_STREAM_START command. A series + * of BMI_LZ_DATA commands are considered part of a single + * input stream until another BMI_LZ_STREAM_START is issued. + * Request format: + * A_UINT32 command (BMI_LZ_DATA) + * A_UINT32 length (of compressed data), + * at most BMI_DATASZ_MAX + * A_UINT8 CompressedData[length] + * Response format: none + * Note: Not supported on all versions of ROM firmware. + */ + +#endif /* __BMI_MSG_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/cnxmgmt.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/cnxmgmt.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/cnxmgmt.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/cnxmgmt.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,33 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _CNXMGMT_H_ +#define _CNXMGMT_H_ + +typedef enum { + CM_CONNECT_WITHOUT_SCAN = 0x0001, + CM_CONNECT_ASSOC_POLICY_USER = 0x0002, + CM_CONNECT_SEND_REASSOC = 0x0004, + CM_CONNECT_NO_ROAMSCAN = 0x0008, +} CM_CONNECT_TYPE; + +#endif /* _CNXMGMT_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/common_drv.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/common_drv.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/common_drv.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/common_drv.c 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,663 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" + +#include "mbox_host_reg.h" +#include "apb_map.h" +#include "si_reg.h" +#include "gpio_reg.h" +#include "rtc_reg.h" +#include "vmc_reg.h" +#include "mbox_reg.h" + +#include "targaddrs.h" +#include "a_osapi.h" +#include "hif.h" +#include "htc_api.h" +#include "wmi.h" +#include "bmi.h" +#include "bmi_msg.h" +#include "common_drv.h" +#include "a_debug.h" + +#define HOST_INTEREST_ITEM_ADDRESS(target, item) \ + (((target) == TARGET_TYPE_AR6001) ? AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((target) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((target) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : 0))) + + +#define AR6001_LOCAL_COUNT_ADDRESS 0x0c014080 +#define AR6002_LOCAL_COUNT_ADDRESS 0x00018080 +#define AR6003_LOCAL_COUNT_ADDRESS 0x00018080 + +/* Compile the 4BYTE version of the window register setup routine, + * This mitigates host interconnect issues with non-4byte aligned bus requests, some + * interconnects use bus adapters that impose strict limitations. + * Since diag window access is not intended for performance critical operations, the 4byte mode should + * be satisfactory even though it generates 4X the bus activity. */ + +#ifdef USE_4BYTE_REGISTER_ACCESS + + /* set the window address register (using 4-byte register access ). */ +A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address) +{ + A_STATUS status; + A_UINT8 addrValue[4]; + A_INT32 i; + + /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written + * last to initiate the access cycle */ + + for (i = 1; i <= 3; i++) { + /* fill the buffer with the address byte value we want to hit 4 times*/ + addrValue[0] = ((A_UINT8 *)&Address)[i]; + addrValue[1] = addrValue[0]; + addrValue[2] = addrValue[0]; + addrValue[3] = addrValue[0]; + + /* hit each byte of the register address with a 4-byte write operation to the same address, + * this is a harmless operation */ + status = HIFReadWrite(hifDevice, + RegisterAddr+i, + addrValue, + 4, + HIF_WR_SYNC_BYTE_FIX, + NULL); + if (status != A_OK) { + break; + } + } + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n", + RegisterAddr, Address)); + return status; + } + + /* write the address register again, this time write the whole 4-byte value. + * The effect here is that the LSB write causes the cycle to start, the extra + * 3 byte write to bytes 1,2,3 has no effect since we are writing the same values again */ + status = HIFReadWrite(hifDevice, + RegisterAddr, + (A_UCHAR *)(&Address), + 4, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n", + RegisterAddr, Address)); + return status; + } + + return A_OK; + + + +} + + +#else + + /* set the window address register */ +A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address) +{ + A_STATUS status; + + /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written + * last to initiate the access cycle */ + status = HIFReadWrite(hifDevice, + RegisterAddr+1, /* write upper 3 bytes */ + ((A_UCHAR *)(&Address))+1, + sizeof(A_UINT32)-1, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n", + RegisterAddr, Address)); + return status; + } + + /* write the LSB of the register, this initiates the operation */ + status = HIFReadWrite(hifDevice, + RegisterAddr, + (A_UCHAR *)(&Address), + sizeof(A_UINT8), + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n", + RegisterAddr, Address)); + return status; + } + + return A_OK; +} + +#endif + +/* + * Read from the AR6000 through its diagnostic window. + * No cooperation from the Target is required for this. + */ +A_STATUS +ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data) +{ + A_STATUS status; + + /* set window register to start read cycle */ + status = ar6000_SetAddressWindowRegister(hifDevice, + WINDOW_READ_ADDR_ADDRESS, + *address); + + if (status != A_OK) { + return status; + } + + /* read the data */ + status = HIFReadWrite(hifDevice, + WINDOW_DATA_ADDRESS, + (A_UCHAR *)data, + sizeof(A_UINT32), + HIF_RD_SYNC_BYTE_INC, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from WINDOW_DATA_ADDRESS\n")); + return status; + } + + return status; +} + + +/* + * Write to the AR6000 through its diagnostic window. + * No cooperation from the Target is required for this. + */ +A_STATUS +ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data) +{ + A_STATUS status; + + /* set write data */ + status = HIFReadWrite(hifDevice, + WINDOW_DATA_ADDRESS, + (A_UCHAR *)data, + sizeof(A_UINT32), + HIF_WR_SYNC_BYTE_INC, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to WINDOW_DATA_ADDRESS\n", *data)); + return status; + } + + /* set window register, which starts the write cycle */ + return ar6000_SetAddressWindowRegister(hifDevice, + WINDOW_WRITE_ADDR_ADDRESS, + *address); + } + +A_STATUS +ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length) +{ + A_UINT32 count; + A_STATUS status = A_OK; + + for (count = 0; count < length; count += 4, address += 4) { + if ((status = ar6000_ReadRegDiag(hifDevice, &address, + (A_UINT32 *)&data[count])) != A_OK) + { + break; + } + } + + return status; +} + +A_STATUS +ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length) +{ + A_UINT32 count; + A_STATUS status = A_OK; + + for (count = 0; count < length; count += 4, address += 4) { + if ((status = ar6000_WriteRegDiag(hifDevice, &address, + (A_UINT32 *)&data[count])) != A_OK) + { + break; + } + } + + return status; +} + +#if 0 +static A_STATUS +_do_write_diag(HIF_DEVICE *hifDevice, A_UINT32 addr, A_UINT32 value) +{ + A_STATUS status; + + status = ar6000_WriteRegDiag(hifDevice, &addr, &value); + if (status != A_OK) + { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot force Target to execute ROM!\n")); + } + + return status; +} +#endif + + +/* + * Delay up to wait_msecs millisecs to allow Target to enter BMI phase, + * which is a good sign that it's alive and well. This is used after + * explicitly forcing the Target to reset. + * + * The wait_msecs time should be sufficiently long to cover any reasonable + * boot-time delay. For instance, AR6001 firmware allow one second for a + * low frequency crystal to settle before it calibrates the refclk frequency. + * + * TBD: Might want to add special handling for AR6K_OPTION_BMI_DISABLE. + */ +static A_STATUS +_delay_until_target_alive(HIF_DEVICE *hifDevice, A_INT32 wait_msecs, A_UINT32 TargetType) +{ + A_INT32 actual_wait; + A_INT32 i; + A_UINT32 address; + + actual_wait = 0; + + /* Hardcode the address of LOCAL_COUNT_ADDRESS based on the target type */ + if (TargetType == TARGET_TYPE_AR6001) { + address = AR6001_LOCAL_COUNT_ADDRESS; + } else if (TargetType == TARGET_TYPE_AR6002) { + address = AR6002_LOCAL_COUNT_ADDRESS; + } else if (TargetType == TARGET_TYPE_AR6003) { + address = AR6003_LOCAL_COUNT_ADDRESS; + } else { + A_ASSERT(0); + } + address += 0x10; + for (i=0; actual_wait < wait_msecs; i++) { + A_UINT32 data; + + A_MDELAY(100); + actual_wait += 100; + + data = 0; + if (ar6000_ReadRegDiag(hifDevice, &address, &data) != A_OK) { + return A_ERROR; + } + + if (data != 0) { + /* No need to wait longer -- we have a BMI credit */ + return A_OK; + } + } + return A_ERROR; /* timed out */ +} + +#define AR6001_RESET_CONTROL_ADDRESS 0x0C000000 +#define AR6002_RESET_CONTROL_ADDRESS 0x00004000 +#define AR6003_RESET_CONTROL_ADDRESS 0x00004000 +/* reset device */ +A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType, A_BOOL waitForCompletion) +{ + A_STATUS status = A_OK; + A_UINT32 address; + A_UINT32 data; + + do { + + // address = RESET_CONTROL_ADDRESS; + data = RESET_CONTROL_COLD_RST_MASK; + + /* Hardcode the address of RESET_CONTROL_ADDRESS based on the target type */ + if (TargetType == TARGET_TYPE_AR6001) { + address = AR6001_RESET_CONTROL_ADDRESS; + } else if (TargetType == TARGET_TYPE_AR6002) { + address = AR6002_RESET_CONTROL_ADDRESS; + } else if (TargetType == TARGET_TYPE_AR6003) { + address = AR6003_RESET_CONTROL_ADDRESS; + } else { + A_ASSERT(0); + } + + + status = ar6000_WriteRegDiag(hifDevice, &address, &data); + + if (A_FAILED(status)) { + break; + } + + if (!waitForCompletion) { + break; + } + + + /* Up to 2 second delay to allow things to settle down */ + (void)_delay_until_target_alive(hifDevice, 2000, TargetType); + + /* + * Read back the RESET CAUSE register to ensure that the cold reset + * went through. + */ + + // address = RESET_CAUSE_ADDRESS; + /* Hardcode the address of RESET_CAUSE_ADDRESS based on the target type */ + if (TargetType == TARGET_TYPE_AR6001) { + address = 0x0C0000CC; + } else if (TargetType == TARGET_TYPE_AR6002) { + address = 0x000040C0; + } else if (TargetType == TARGET_TYPE_AR6003) { + address = 0x000040C0; + } else { + A_ASSERT(0); + } + + data = 0; + status = ar6000_ReadRegDiag(hifDevice, &address, &data); + + if (A_FAILED(status)) { + break; + } + + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Reset Cause readback: 0x%X \n",data)); + data &= RESET_CAUSE_LAST_MASK; + if (data != 2) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Unable to cold reset the target \n")); + } + + } while (FALSE); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Failed to reset target \n")); + } + + return A_OK; +} + +#define REG_DUMP_COUNT_AR6001 38 /* WORDs, derived from AR600x_regdump.h */ +#define REG_DUMP_COUNT_AR6002 32 +#define REG_DUMP_COUNT_AR6003 32 +#define REGISTER_DUMP_LEN_MAX 38 +#if REG_DUMP_COUNT_AR6001 > REGISTER_DUMP_LEN_MAX +#error "REG_DUMP_COUNT_AR6001 too large" +#endif +#if REG_DUMP_COUNT_AR6002 > REGISTER_DUMP_LEN_MAX +#error "REG_DUMP_COUNT_AR6002 too large" +#endif +#if REG_DUMP_COUNT_AR6003 > REGISTER_DUMP_LEN_MAX +#error "REG_DUMP_COUNT_AR6003 too large" +#endif + + +void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType) +{ + A_UINT32 address; + A_UINT32 regDumpArea = 0; + A_STATUS status; + A_UINT32 regDumpValues[REGISTER_DUMP_LEN_MAX]; + A_UINT32 regDumpCount = 0; + A_UINT32 i; + + do { + + /* the reg dump pointer is copied to the host interest area */ + address = HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_failure_state); + address = TARG_VTOP(TargetType, address); + + if (TargetType == TARGET_TYPE_AR6001) { + /* for AR6001, this is a fixed location because the ptr is actually stuck in cache, + * this may be fixed in later firmware versions */ + address = 0x18a0; + regDumpCount = REG_DUMP_COUNT_AR6001; + } else if (TargetType == TARGET_TYPE_AR6002) { + regDumpCount = REG_DUMP_COUNT_AR6002; + } else if (TargetType == TARGET_TYPE_AR6003) { + regDumpCount = REG_DUMP_COUNT_AR6003; + } else { + A_ASSERT(0); + } + + /* read RAM location through diagnostic window */ + status = ar6000_ReadRegDiag(hifDevice, &address, ®DumpArea); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get ptr to register dump area \n")); + break; + } + + A_PRINTF("AR6K: Location of register dump data: 0x%X \n",regDumpArea); + + if (regDumpArea == 0) { + /* no reg dump */ + break; + } + + regDumpArea = TARG_VTOP(TargetType, regDumpArea); + + /* fetch register dump data */ + status = ar6000_ReadDataDiag(hifDevice, + regDumpArea, + (A_UCHAR *)®DumpValues[0], + regDumpCount * (sizeof(A_UINT32))); + + if (A_FAILED(status)) { + A_PRINTF("AR6K: Failed to get register dump \n"); + break; + } + A_PRINTF("AR6K: Register Dump: \n"); + + for (i = 0; i < regDumpCount; i++) { + A_PRINTF(" %d : 0x%8.8X \n",i, regDumpValues[i]); +#ifdef UNDER_CE + logPrintf(ATH_DEBUG_ERR," %d: 0x%8.8X \n",i, regDumpValues[i]); +#endif + } + + } while (FALSE); + +} + +/* set HTC/Mbox operational parameters, this can only be called when the target is in the + * BMI phase */ +A_STATUS ar6000_set_htc_params(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 MboxIsrYieldValue, + A_UINT8 HtcControlBuffers) +{ + A_STATUS status; + A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX]; + + do { + /* get the block sizes */ + status = HIFConfigureDevice(hifDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + blocksizes, sizeof(blocksizes)); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_LOG_ERR,("Failed to get block size info from HIF layer...\n")); + break; + } + /* note: we actually get the block size for mailbox 1, for SDIO the block + * size on mailbox 0 is artificially set to 1 */ + /* must be a power of 2 */ + A_ASSERT((blocksizes[1] & (blocksizes[1] - 1)) == 0); + + if (HtcControlBuffers != 0) { + /* set override for number of control buffers to use */ + blocksizes[1] |= ((A_UINT32)HtcControlBuffers) << 16; + } + + /* set the host interest area for the block size */ + status = BMIWriteMemory(hifDevice, + HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz), + (A_UCHAR *)&blocksizes[1], + 4); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for IO block size failed \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_LOG_INF,("Block Size Set: %d (target address:0x%X)\n", + blocksizes[1], HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz))); + + if (MboxIsrYieldValue != 0) { + /* set the host interest area for the mbox ISR yield limit */ + status = BMIWriteMemory(hifDevice, + HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_isr_yield_limit), + (A_UCHAR *)&MboxIsrYieldValue, + 4); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for yield limit failed \n")); + break; + } + } + + } while (FALSE); + + return status; +} + + +static A_STATUS prepare_ar6002(HIF_DEVICE *hifDevice, A_UINT32 TargetVersion) +{ + A_STATUS status = A_OK; + + /* placeholder */ + + return status; +} + +static A_STATUS prepare_ar6003(HIF_DEVICE *hifDevice, A_UINT32 TargetVersion) +{ + A_STATUS status = A_OK; + + /* placeholder */ + + return status; +} + +/* this function assumes the caller has already initialized the BMI APIs */ +A_STATUS ar6000_prepare_target(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 TargetVersion) +{ + if (TargetType == TARGET_TYPE_AR6002) { + /* do any preparations for AR6002 devices */ + return prepare_ar6002(hifDevice,TargetVersion); + } else if (TargetType == TARGET_TYPE_AR6003) { + return prepare_ar6003(hifDevice,TargetVersion); + } + + return A_OK; +} + +#if defined(CONFIG_AR6002_REV1_FORCE_HOST) +/* + * Call this function just before the call to BMIInit + * in order to force* AR6002 rev 1.x firmware to detect a Host. + * THIS IS FOR USE ONLY WITH AR6002 REV 1.x. + * TBDXXX: Remove this function when REV 1.x is desupported. + */ +A_STATUS +ar6002_REV1_reset_force_host (HIF_DEVICE *hifDevice) +{ + A_INT32 i; + struct forceROM_s { + A_UINT32 addr; + A_UINT32 data; + }; + struct forceROM_s *ForceROM; + A_INT32 szForceROM; + A_STATUS status = A_OK; + A_UINT32 address; + A_UINT32 data; + + /* Force AR6002 REV1.x to recognize Host presence. + * + * Note: Use RAM at 0x52df80..0x52dfa0 with ROM Remap entry 0 + * so that this workaround functions with AR6002.war1.sh. We + * could fold that entire workaround into this one, but it's not + * worth the effort at this point. This workaround cannot be + * merged into the other workaround because this must be done + * before BMI. + */ + + static struct forceROM_s ForceROM_NEW[] = { + {0x52df80, 0x20f31c07}, + {0x52df84, 0x92374420}, + {0x52df88, 0x1d120c03}, + {0x52df8c, 0xff8216f0}, + {0x52df90, 0xf01d120c}, + {0x52df94, 0x81004136}, + {0x52df98, 0xbc9100bd}, + {0x52df9c, 0x00bba100}, + + {0x00008000|MC_TCAM_TARGET_ADDRESS, 0x0012dfe0}, /* Use remap entry 0 */ + {0x00008000|MC_TCAM_COMPARE_ADDRESS, 0x000e2380}, + {0x00008000|MC_TCAM_MASK_ADDRESS, 0x00000000}, + {0x00008000|MC_TCAM_VALID_ADDRESS, 0x00000001}, + + {0x00018000|(LOCAL_COUNT_ADDRESS+0x10), 0}, /* clear BMI credit counter */ + + {0x00004000|AR6002_RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK}, + }; + + address = 0x004ed4b0; /* REV1 target software ID is stored here */ + status = ar6000_ReadRegDiag(hifDevice, &address, &data); + if (A_FAILED(status) || (data != AR6002_VERSION_REV1)) { + return A_ERROR; /* Not AR6002 REV1 */ + } + + ForceROM = ForceROM_NEW; + szForceROM = sizeof(ForceROM_NEW)/sizeof(*ForceROM); + + ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Force Target to recognize Host....\n")); + for (i = 0; i < szForceROM; i++) + { + if (ar6000_WriteRegDiag(hifDevice, + &ForceROM[i].addr, + &ForceROM[i].data) != A_OK) + { + ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Cannot force Target to recognize Host!\n")); + return A_ERROR; + } + } + + A_MDELAY(1000); + + return A_OK; +} +#endif /* CONFIG_AR6002_REV1_FORCE_HOST */ + + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/common_drv.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/common_drv.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/common_drv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/common_drv.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,79 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef COMMON_DRV_H_ +#define COMMON_DRV_H_ + +#include "hif.h" +#include "htc_packet.h" + +/* structure that is the state information for the default credit distribution callback + * drivers should instantiate (zero-init as well) this structure in their driver instance + * and pass it as a context to the HTC credit distribution functions */ +typedef struct _COMMON_CREDIT_STATE_INFO { + int TotalAvailableCredits; /* total credits in the system at startup */ + int CurrentFreeCredits; /* credits available in the pool that have not been + given out to endpoints */ + HTC_ENDPOINT_CREDIT_DIST *pLowestPriEpDist; /* pointer to the lowest priority endpoint dist struct */ +} COMMON_CREDIT_STATE_INFO; + + +/* HTC TX packet tagging definitions */ +#define AR6K_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED +#define AR6K_DATA_PKT_TAG (AR6K_CONTROL_PKT_TAG + 1) + +#define AR6002_VERSION_REV1 0x20000086 +#define AR6002_VERSION_REV2 0x20000188 + +#ifdef __cplusplus +extern "C" { +#endif + +/* OS-independent APIs */ +A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo); + +A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, A_UCHAR *data, A_UINT32 length); + +A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType, A_BOOL waitForCompletion); + +void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType); + +A_STATUS ar6000_reset_device_skipflash(HIF_DEVICE *hifDevice); + +A_STATUS ar6000_set_htc_params(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 MboxIsrYieldValue, + A_UINT8 HtcControlBuffers); + +A_STATUS ar6000_prepare_target(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 TargetVersion); + +#ifdef __cplusplus +} +#endif + +#endif /*COMMON_DRV_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/config_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/config_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/config_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/config_linux.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _CONFIG_LINUX_H_ +#define _CONFIG_LINUX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Host-side GPIO support is optional. + * If run-time access to GPIO pins is not required, then + * this should be changed to #undef. + */ +#define CONFIG_HOST_GPIO_SUPPORT + +/* + * Host side Test Command support + */ +#define CONFIG_HOST_TCMD_SUPPORT + +#define USE_4BYTE_REGISTER_ACCESS + +/* Host-side support for Target-side profiling */ +#undef CONFIG_TARGET_PROFILE_SUPPORT + +#ifdef __cplusplus +} +#endif + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/credit_dist.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/credit_dist.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/credit_dist.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/credit_dist.c 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,373 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "a_debug.h" +#include "htc_api.h" +#include "common_drv.h" + +/********* CREDIT DISTRIBUTION FUNCTIONS ******************************************/ + +#define NO_VO_SERVICE 1 /* currently WMI only uses 3 data streams, so we leave VO service inactive */ + +#ifdef NO_VO_SERVICE +#define DATA_SVCS_USED 3 +#else +#define DATA_SVCS_USED 4 +#endif + +static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList); + +static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList); + +/* reduce an ep's credits back to a set limit */ +static INLINE void ReduceCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEpDist, + int Limit) +{ + int credits; + + /* set the new limit */ + pEpDist->TxCreditsAssigned = Limit; + + if (pEpDist->TxCredits <= Limit) { + return; + } + + /* figure out how much to take away */ + credits = pEpDist->TxCredits - Limit; + /* take them away */ + pEpDist->TxCredits -= credits; + pCredInfo->CurrentFreeCredits += credits; +} + +/* give an endpoint some credits from the free credit pool */ +#define GiveCredits(pCredInfo,pEpDist,credits) \ +{ \ + (pEpDist)->TxCredits += (credits); \ + (pEpDist)->TxCreditsAssigned += (credits); \ + (pCredInfo)->CurrentFreeCredits -= (credits); \ +} + + +/* default credit init callback. + * This function is called in the context of HTCStart() to setup initial (application-specific) + * credit distributions */ +static void ar6000_credit_init(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + int TotalCredits) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + int count; + COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context; + + pCredInfo->CurrentFreeCredits = TotalCredits; + pCredInfo->TotalAvailableCredits = TotalCredits; + + pCurEpDist = pEPList; + + /* run through the list and initialize */ + while (pCurEpDist != NULL) { + + /* set minimums for each endpoint */ + pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg; + + if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) { + /* give control service some credits */ + GiveCredits(pCredInfo,pCurEpDist,pCurEpDist->TxCreditsMin); + /* control service is always marked active, it never goes inactive EVER */ + SET_EP_ACTIVE(pCurEpDist); + } else if (pCurEpDist->ServiceID == WMI_DATA_BK_SVC) { + /* this is the lowest priority data endpoint, save this off for easy access */ + pCredInfo->pLowestPriEpDist = pCurEpDist; + } + + /* Streams have to be created (explicit | implicit)for all kinds + * of traffic. BE endpoints are also inactive in the beginning. + * When BE traffic starts it creates implicit streams that + * redistributes credits. + */ + + /* note, all other endpoints have minimums set but are initially given NO credits. + * Credits will be distributed as traffic activity demands */ + pCurEpDist = pCurEpDist->pNext; + } + + if (pCredInfo->CurrentFreeCredits <= 0) { + AR_DEBUG_PRINTF(ATH_LOG_INF, ("Not enough credits (%d) to do credit distributions \n", TotalCredits)); + A_ASSERT(FALSE); + return; + } + + /* reset list */ + pCurEpDist = pEPList; + /* now run through the list and set max operating credit limits for everyone */ + while (pCurEpDist != NULL) { + if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) { + /* control service max is just 1 max message */ + pCurEpDist->TxCreditsNorm = pCurEpDist->TxCreditsPerMaxMsg; + } else { + /* for the remaining data endpoints, we assume that each TxCreditsPerMaxMsg are + * the same. + * We use a simple calculation here, we take the remaining credits and + * determine how many max messages this can cover and then set each endpoint's + * normal value equal to 3/4 this amount. + * */ + count = (pCredInfo->CurrentFreeCredits/pCurEpDist->TxCreditsPerMaxMsg) * pCurEpDist->TxCreditsPerMaxMsg; + count = (count * 3) >> 2; + count = max(count,pCurEpDist->TxCreditsPerMaxMsg); + /* set normal */ + pCurEpDist->TxCreditsNorm = count; + + } + pCurEpDist = pCurEpDist->pNext; + } + +} + + +/* default credit distribution callback + * This callback is invoked whenever endpoints require credit distributions. + * A lock is held while this function is invoked, this function shall NOT block. + * The pEPDistList is a list of distribution structures in prioritized order as + * defined by the call to the HTCSetCreditDistribution() api. + * + */ +static void ar6000_credit_distribute(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList, + HTC_CREDIT_DIST_REASON Reason) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context; + + switch (Reason) { + case HTC_CREDIT_DIST_SEND_COMPLETE : + pCurEpDist = pEPDistList; + /* we are given the start of the endpoint distribution list. + * There may be one or more endpoints to service. + * Run through the list and distribute credits */ + while (pCurEpDist != NULL) { + + if (pCurEpDist->TxCreditsToDist > 0) { + /* return the credits back to the endpoint */ + pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist; + /* always zero out when we are done */ + pCurEpDist->TxCreditsToDist = 0; + + if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsAssigned) { + /* reduce to the assigned limit, previous credit reductions + * could have caused the limit to change */ + ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsAssigned); + } + + if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsNorm) { + /* oversubscribed endpoints need to reduce back to normal */ + ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsNorm); + } + + if (!IS_EP_ACTIVE(pCurEpDist)) { + /* endpoint is inactive, now check for messages waiting for credits */ + if (pCurEpDist->TxQueueDepth == 0) { + /* EP is inactive and there are no pending messages, + * reduce credits back to zero to recover credits */ + ReduceCredits(pCredInfo, pCurEpDist, 0); + } + } + } + + pCurEpDist = pCurEpDist->pNext; + } + + break; + + case HTC_CREDIT_DIST_ACTIVITY_CHANGE : + RedistributeCredits(pCredInfo,pEPDistList); + break; + case HTC_CREDIT_DIST_SEEK_CREDITS : + SeekCredits(pCredInfo,pEPDistList); + break; + case HTC_DUMP_CREDIT_STATE : + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Credit Distribution, total : %d, free : %d\n", + pCredInfo->TotalAvailableCredits, pCredInfo->CurrentFreeCredits)); + break; + default: + break; + + } + + /* sanity checks done after each distribution action */ + A_ASSERT(pCredInfo->CurrentFreeCredits <= pCredInfo->TotalAvailableCredits); + A_ASSERT(pCredInfo->CurrentFreeCredits >= 0); + +} + +/* redistribute credits based on activity change */ +static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist = pEPDistList; + + /* walk through the list and remove credits from inactive endpoints */ + while (pCurEpDist != NULL) { + + if (pCurEpDist->ServiceID != WMI_CONTROL_SVC) { + if (!IS_EP_ACTIVE(pCurEpDist)) { + if (pCurEpDist->TxQueueDepth == 0) { + /* EP is inactive and there are no pending messages, reduce credits back to zero */ + ReduceCredits(pCredInfo, pCurEpDist, 0); + } else { + /* we cannot zero the credits assigned to this EP, but to keep + * the credits available for these leftover packets, reduce to + * a minimum */ + ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsMin); + } + } + } + + /* NOTE in the active case, we do not need to do anything further, + * when an EP goes active and needs credits, HTC will call into + * our distribution function using a reason code of HTC_CREDIT_DIST_SEEK_CREDITS */ + + pCurEpDist = pCurEpDist->pNext; + } + +} + +/* HTC has an endpoint that needs credits, pEPDist is the endpoint in question */ +static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDist) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + int credits = 0; + int need; + + do { + + if (pEPDist->ServiceID == WMI_CONTROL_SVC) { + /* we never oversubscribe on the control service, this is not + * a high performance path and the target never holds onto control + * credits for too long */ + break; + } + + if (pEPDist->ServiceID == WMI_DATA_VI_SVC) { + if (pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm) { + /* limit VI service from oversubscribing */ + break; + } + } + + if (pEPDist->ServiceID == WMI_DATA_VO_SVC) { + if (pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm) { + /* limit VO service from oversubscribing */ + break; + } + } + + /* for all other services, we follow a simple algorithm of + * 1. checking the free pool for credits + * 2. checking lower priority endpoints for credits to take */ + + /* give what we can */ + credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek); + + if (credits >= pEPDist->TxCreditsSeek) { + /* we found some to fullfill the seek request */ + break; + } + + /* we don't have enough in the free pool, try taking away from lower priority services + * + * The rule for taking away credits: + * 1. Only take from lower priority endpoints + * 2. Only take what is allocated above the minimum (never starve an endpoint completely) + * 3. Only take what you need. + * + * */ + + /* starting at the lowest priority */ + pCurEpDist = pCredInfo->pLowestPriEpDist; + + /* work backwards until we hit the endpoint again */ + while (pCurEpDist != pEPDist) { + /* calculate how many we need so far */ + need = pEPDist->TxCreditsSeek - pCredInfo->CurrentFreeCredits; + + if ((pCurEpDist->TxCreditsAssigned - need) >= pCurEpDist->TxCreditsMin) { + /* the current one has been allocated more than it's minimum and it + * has enough credits assigned above it's minimum to fullfill our need + * try to take away just enough to fullfill our need */ + ReduceCredits(pCredInfo, + pCurEpDist, + pCurEpDist->TxCreditsAssigned - need); + + if (pCredInfo->CurrentFreeCredits >= pEPDist->TxCreditsSeek) { + /* we have enough */ + break; + } + } + + pCurEpDist = pCurEpDist->pPrev; + } + + /* return what we can get */ + credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek); + + } while (FALSE); + + /* did we find some credits? */ + if (credits) { + /* give what we can */ + GiveCredits(pCredInfo, pEPDist, credits); + } + +} + +/* initialize and setup credit distribution */ +A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo) +{ + HTC_SERVICE_ID servicepriority[5]; + + A_MEMZERO(pCredInfo,sizeof(COMMON_CREDIT_STATE_INFO)); + + servicepriority[0] = WMI_CONTROL_SVC; /* highest */ + servicepriority[1] = WMI_DATA_VO_SVC; + servicepriority[2] = WMI_DATA_VI_SVC; + servicepriority[3] = WMI_DATA_BE_SVC; + servicepriority[4] = WMI_DATA_BK_SVC; /* lowest */ + + /* set callbacks and priority list */ + HTCSetCreditDistribution(HTCHandle, + pCredInfo, + ar6000_credit_distribute, + ar6000_credit_init, + servicepriority, + 5); + + return A_OK; +} + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/dbglog.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/dbglog.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/dbglog.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/dbglog.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,126 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _DBGLOG_H_ +#define _DBGLOG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define DBGLOG_TIMESTAMP_OFFSET 0 +#define DBGLOG_TIMESTAMP_MASK 0x0000FFFF /* Bit 0-15. Contains bit + 8-23 of the LF0 timer */ +#define DBGLOG_DBGID_OFFSET 16 +#define DBGLOG_DBGID_MASK 0x03FF0000 /* Bit 16-25 */ +#define DBGLOG_DBGID_NUM_MAX 256 /* Upper limit is width of mask */ + +#define DBGLOG_MODULEID_OFFSET 26 +#define DBGLOG_MODULEID_MASK 0x3C000000 /* Bit 26-29 */ +#define DBGLOG_MODULEID_NUM_MAX 16 /* Upper limit is width of mask */ + +/* + * Please ensure that the definition of any new module intrduced is captured + * between the DBGLOG_MODULEID_START and DBGLOG_MODULEID_END defines. The + * structure is required for the parser to correctly pick up the values for + * different modules. + */ +#define DBGLOG_MODULEID_START +#define DBGLOG_MODULEID_INF 0 +#define DBGLOG_MODULEID_WMI 1 +#define DBGLOG_MODULEID_CSERV 2 +#define DBGLOG_MODULEID_PM 3 +#define DBGLOG_MODULEID_TXRX_MGMTBUF 4 +#define DBGLOG_MODULEID_TXRX_TXBUF 5 +#define DBGLOG_MODULEID_TXRX_RXBUF 6 +#define DBGLOG_MODULEID_WOW 7 +#define DBGLOG_MODULEID_WHAL 8 +#define DBGLOG_MODULEID_DC 9 +#define DBGLOG_MODULEID_CO 10 +#define DBGLOG_MODULEID_RO 11 +#define DBGLOG_MODULEID_CM 12 +#define DBGLOG_MODULEID_PY 13 +#define DBGLOG_MODULEID_TMR 14 +#define DBGLOG_MODULEID_BTCOEX 15 +#define DBGLOG_MODULEID_END + +#define DBGLOG_NUM_ARGS_OFFSET 30 +#define DBGLOG_NUM_ARGS_MASK 0xC0000000 /* Bit 30-31 */ +#define DBGLOG_NUM_ARGS_MAX 2 /* Upper limit is width of mask */ + +#define DBGLOG_MODULE_LOG_ENABLE_OFFSET 0 +#define DBGLOG_MODULE_LOG_ENABLE_MASK 0x0000FFFF + +#define DBGLOG_REPORTING_ENABLED_OFFSET 16 +#define DBGLOG_REPORTING_ENABLED_MASK 0x00010000 + +#define DBGLOG_TIMESTAMP_RESOLUTION_OFFSET 17 +#define DBGLOG_TIMESTAMP_RESOLUTION_MASK 0x000E0000 + +#define DBGLOG_REPORT_SIZE_OFFSET 20 +#define DBGLOG_REPORT_SIZE_MASK 0x3FF00000 + +#define DBGLOG_LOG_BUFFER_SIZE 1500 +#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90 + +struct dbglog_buf_s { + struct dbglog_buf_s *next; + A_INT8 *buffer; + A_UINT32 bufsize; + A_UINT32 length; + A_UINT32 count; + A_UINT32 free; +}; + +struct dbglog_hdr_s { + struct dbglog_buf_s *dbuf; + A_UINT32 dropped; +}; + +struct dbglog_config_s { + A_UINT32 cfgvalid; /* Mask with valid config bits */ + union { + /* TODO: Take care of endianness */ + struct { + A_UINT32 mmask:16; /* Mask of modules with logging on */ + A_UINT32 rep:1; /* Reporting enabled or not */ + A_UINT32 tsr:3; /* Time stamp resolution. Def: 1 ms */ + A_UINT32 size:10; /* Report size in number of messages */ + A_UINT32 reserved:2; + } dbglog_config; + + A_UINT32 value; + } u; +}; + +#define cfgmmask u.dbglog_config.mmask +#define cfgrep u.dbglog_config.rep +#define cfgtsr u.dbglog_config.tsr +#define cfgsize u.dbglog_config.size +#define cfgvalue u.value + +#ifdef __cplusplus +} +#endif + +#endif /* _DBGLOG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/dbglog_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/dbglog_api.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/dbglog_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/dbglog_api.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains host side debug primitives. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _DBGLOG_API_H_ +#define _DBGLOG_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbglog.h" + +#define DBGLOG_HOST_LOG_BUFFER_SIZE DBGLOG_LOG_BUFFER_SIZE + +#define DBGLOG_GET_DBGID(arg) \ + ((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET) + +#define DBGLOG_GET_MODULEID(arg) \ + ((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET) + +#define DBGLOG_GET_NUMARGS(arg) \ + ((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET) + +#define DBGLOG_GET_TIMESTAMP(arg) \ + ((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET) + +#ifdef __cplusplus +} +#endif + +#endif /* _DBGLOG_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/dbglog_id.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/dbglog_id.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/dbglog_id.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/dbglog_id.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,505 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _DBGLOG_ID_H_ +#define _DBGLOG_ID_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * The nomenclature for the debug identifiers is MODULE_DESCRIPTION. + * Please ensure that the definition of any new debugid introduced is captured + * between the _DBGID_DEFINITION_START and + * _DBGID_DEFINITION_END defines. The structure is required for the + * parser to correctly pick up the values for different debug identifiers. + */ + +/* INF debug identifier definitions */ +#define INF_DBGID_DEFINITION_START +#define INF_ASSERTION_FAILED 1 +#define INF_TARGET_ID 2 +#define INF_DBGID_DEFINITION_END + +/* WMI debug identifier definitions */ +#define WMI_DBGID_DEFINITION_START +#define WMI_CMD_RX_XTND_PKT_TOO_SHORT 1 +#define WMI_EXTENDED_CMD_NOT_HANDLED 2 +#define WMI_CMD_RX_PKT_TOO_SHORT 3 +#define WMI_CALLING_WMI_EXTENSION_FN 4 +#define WMI_CMD_NOT_HANDLED 5 +#define WMI_IN_SYNC 6 +#define WMI_TARGET_WMI_SYNC_CMD 7 +#define WMI_SET_SNR_THRESHOLD_PARAMS 8 +#define WMI_SET_RSSI_THRESHOLD_PARAMS 9 +#define WMI_SET_LQ_TRESHOLD_PARAMS 10 +#define WMI_TARGET_CREATE_PSTREAM_CMD 11 +#define WMI_WI_DTM_INUSE 12 +#define WMI_TARGET_DELETE_PSTREAM_CMD 13 +#define WMI_TARGET_IMPLICIT_DELETE_PSTREAM_CMD 14 +#define WMI_TARGET_GET_BIT_RATE_CMD 15 +#define WMI_GET_RATE_MASK_CMD_FIX_RATE_MASK_IS 16 +#define WMI_TARGET_GET_AVAILABLE_CHANNELS_CMD 17 +#define WMI_TARGET_GET_TX_PWR_CMD 18 +#define WMI_FREE_EVBUF_WMIBUF 19 +#define WMI_FREE_EVBUF_DATABUF 20 +#define WMI_FREE_EVBUF_BADFLAG 21 +#define WMI_HTC_RX_ERROR_DATA_PACKET 22 +#define WMI_HTC_RX_SYNC_PAUSING_FOR_MBOX 23 +#define WMI_INCORRECT_WMI_DATA_HDR_DROPPING_PKT 24 +#define WMI_SENDING_READY_EVENT 25 +#define WMI_SETPOWER_MDOE_TO_MAXPERF 26 +#define WMI_SETPOWER_MDOE_TO_REC 27 +#define WMI_BSSINFO_EVENT_FROM 28 +#define WMI_TARGET_GET_STATS_CMD 29 +#define WMI_SENDING_SCAN_COMPLETE_EVENT 30 +#define WMI_SENDING_RSSI_INDB_THRESHOLD_EVENT 31 +#define WMI_SENDING_RSSI_INDBM_THRESHOLD_EVENT 32 +#define WMI_SENDING_LINK_QUALITY_THRESHOLD_EVENT 33 +#define WMI_SENDING_ERROR_REPORT_EVENT 34 +#define WMI_SENDING_CAC_EVENT 35 +#define WMI_TARGET_GET_ROAM_TABLE_CMD 36 +#define WMI_TARGET_GET_ROAM_DATA_CMD 37 +#define WMI_SENDING_GPIO_INTR_EVENT 38 +#define WMI_SENDING_GPIO_ACK_EVENT 39 +#define WMI_SENDING_GPIO_DATA_EVENT 40 +#define WMI_CMD_RX 41 +#define WMI_CMD_RX_XTND 42 +#define WMI_EVENT_SEND 43 +#define WMI_EVENT_SEND_XTND 44 +#define WMI_CMD_PARAMS_DUMP_START 45 +#define WMI_CMD_PARAMS_DUMP_END 46 +#define WMI_CMD_PARAMS 47 +#define WMI_DBGID_DEFINITION_END + +/* CSERV debug identifier definitions */ +#define CSERV_DBGID_DEFINITION_START +#define CSERV_BEGIN_SCAN1 1 +#define CSERV_BEGIN_SCAN2 2 +#define CSERV_END_SCAN1 3 +#define CSERV_END_SCAN2 4 +#define CSERV_CHAN_SCAN_START 5 +#define CSERV_CHAN_SCAN_STOP 6 +#define CSERV_CHANNEL_OPPPORTUNITY 7 +#define CSERV_NC_TIMEOUT 8 +#define CSERV_BACK_HOME 10 +#define CSERV_CHMGR_CH_CALLBACK1 11 +#define CSERV_CHMGR_CH_CALLBACK2 12 +#define CSERV_CHMGR_CH_CALLBACK3 13 +#define CSERV_SET_SCAN_PARAMS1 14 +#define CSERV_SET_SCAN_PARAMS2 15 +#define CSERV_SET_SCAN_PARAMS3 16 +#define CSERV_SET_SCAN_PARAMS4 17 +#define CSERV_ABORT_SCAN 18 +#define CSERV_NEWSTATE 19 +#define CSERV_MINCHMGR_OP_END 20 +#define CSERV_CHMGR_OP_END 21 +#define CSERV_DISCONNECT_TIMEOUT 22 +#define CSERV_ROAM_TIMEOUT 23 +#define CSERV_FORCE_SCAN1 24 +#define CSERV_FORCE_SCAN2 25 +#define CSERV_FORCE_SCAN3 26 +#define CSERV_UTIL_TIMEOUT 27 +#define CSERV_RSSIPOLLER 28 +#define CSERV_RETRY_CONNECT_TIMEOUT 29 +#define CSERV_RSSIINDBMPOLLER 30 +#define CSERV_BGSCAN_ENABLE 31 +#define CSERV_BGSCAN_DISABLE 32 +#define CSERV_WLAN_START_SCAN_CMD1 33 +#define CSERV_WLAN_START_SCAN_CMD2 34 +#define CSERV_WLAN_START_SCAN_CMD3 35 +#define CSERV_START_SCAN_CMD 36 +#define CSERV_START_FORCE_SCAN 37 +#define CSERV_NEXT_CHAN 38 +#define CSERV_SET_REGCODE 39 +#define CSERV_START_ADHOC 40 +#define CSERV_ADHOC_AT_HOME 41 +#define CSERV_OPT_AT_HOME 42 +#define CSERV_WLAN_CONNECT_CMD 43 +#define CSERV_WLAN_RECONNECT_CMD 44 +#define CSERV_WLAN_DISCONNECT_CMD 45 +#define CSERV_BSS_CHANGE_CHANNEL 46 +#define CSERV_BEACON_RX 47 +#define CSERV_KEEPALIVE_CHECK 48 +#define CSERV_RC_BEGIN_SCAN 49 +#define CSERV_RC_SCAN_START 50 +#define CSERV_RC_SCAN_STOP 51 +#define CSERV_RC_NEXT 52 +#define CSERV_RC_SCAN_END 53 +#define CSERV_PROBE_CALLBACK 54 +#define CSERV_ROAM1 55 +#define CSERV_ROAM2 56 +#define CSERV_ROAM3 57 +#define CSERV_CONNECT_EVENT 58 +#define CSERV_DISCONNECT_EVENT 59 +#define CSERV_BMISS_HANDLER1 60 +#define CSERV_BMISS_HANDLER2 61 +#define CSERV_BMISS_HANDLER3 62 +#define CSERV_LOWRSSI_HANDLER 63 +#define CSERV_WLAN_SET_PMKID_CMD 64 +#define CSERV_RECONNECT_REQUEST 65 +#define CSERV_KEYSPLUMBED_EVENT 66 +#define CSERV_NEW_REG 67 +#define CSERV_SET_RSSI_THOLD 68 +#define CSERV_RSSITHRESHOLDCHECK 69 +#define CSERV_RSSIINDBMTHRESHOLDCHECK 70 +#define CSERV_WLAN_SET_OPT_CMD1 71 +#define CSERV_WLAN_SET_OPT_CMD2 72 +#define CSERV_WLAN_SET_OPT_CMD3 73 +#define CSERV_WLAN_SET_OPT_CMD4 74 +#define CSERV_SCAN_CONNECT_STOP 75 +#define CSERV_BMISS_HANDLER4 76 +#define CSERV_INITIALIZE_TIMER 77 +#define CSERV_ARM_TIMER 78 +#define CSERV_DISARM_TIMER 79 +#define CSERV_UNINITIALIZE_TIMER 80 +#define CSERV_DISCONNECT_EVENT2 81 +#define CSERV_SCAN_CONNECT_START 82 +#define CSERV_BSSINFO_MEMORY_ALLOC_FAILED 83 +#define CSERV_SET_SCAN_PARAMS5 84 +#define CSERV_DBGID_DEFINITION_END + +/* TXRX debug identifier definitions */ +#define TXRX_TXBUF_DBGID_DEFINITION_START +#define TXRX_TXBUF_ALLOCATE_BUF 1 +#define TXRX_TXBUF_QUEUE_BUF_TO_MBOX 2 +#define TXRX_TXBUF_QUEUE_BUF_TO_TXQ 3 +#define TXRX_TXBUF_TXQ_DEPTH 4 +#define TXRX_TXBUF_IBSS_QUEUE_TO_SFQ 5 +#define TXRX_TXBUF_IBSS_QUEUE_TO_TXQ_FRM_SFQ 6 +#define TXRX_TXBUF_INITIALIZE_TIMER 7 +#define TXRX_TXBUF_ARM_TIMER 8 +#define TXRX_TXBUF_DISARM_TIMER 9 +#define TXRX_TXBUF_UNINITIALIZE_TIMER 10 +#define TXRX_TXBUF_DBGID_DEFINITION_END + +#define TXRX_RXBUF_DBGID_DEFINITION_START +#define TXRX_RXBUF_ALLOCATE_BUF 1 +#define TXRX_RXBUF_QUEUE_TO_HOST 2 +#define TXRX_RXBUF_QUEUE_TO_WLAN 3 +#define TXRX_RXBUF_ZERO_LEN_BUF 4 +#define TXRX_RXBUF_QUEUE_TO_HOST_LASTBUF_IN_RXCHAIN 5 +#define TXRX_RXBUF_LASTBUF_IN_RXCHAIN_ZEROBUF 6 +#define TXRX_RXBUF_QUEUE_EMPTY_QUEUE_TO_WLAN 7 +#define TXRX_RXBUF_SEND_TO_RECV_MGMT 8 +#define TXRX_RXBUF_SEND_TO_IEEE_LAYER 9 +#define TXRX_RXBUF_DBGID_DEFINITION_END + +#define TXRX_MGMTBUF_DBGID_DEFINITION_START +#define TXRX_MGMTBUF_ALLOCATE_BUF 1 +#define TXRX_MGMTBUF_ALLOCATE_SM_BUF 2 +#define TXRX_MGMTBUF_ALLOCATE_RMBUF 3 +#define TXRX_MGMTBUF_GET_BUF 4 +#define TXRX_MGMTBUF_GET_SM_BUF 5 +#define TXRX_MGMTBUF_QUEUE_BUF_TO_TXQ 6 +#define TXRX_MGMTBUF_REAPED_BUF 7 +#define TXRX_MGMTBUF_REAPED_SM_BUF 8 +#define TXRX_MGMTBUF_WAIT_FOR_TXQ_DRAIN 9 +#define TXRX_MGMTBUF_WAIT_FOR_TXQ_SFQ_DRAIN 10 +#define TXRX_MGMTBUF_ENQUEUE_INTO_DATA_SFQ 11 +#define TXRX_MGMTBUF_DEQUEUE_FROM_DATA_SFQ 12 +#define TXRX_MGMTBUF_PAUSE_DATA_TXQ 13 +#define TXRX_MGMTBUF_RESUME_DATA_TXQ 14 +#define TXRX_MGMTBUF_WAIT_FORTXQ_DRAIN_TIMEOUT 15 +#define TXRX_MGMTBUF_DRAINQ 16 +#define TXRX_MGMTBUF_INDICATE_Q_DRAINED 17 +#define TXRX_MGMTBUF_ENQUEUE_INTO_HW_SFQ 18 +#define TXRX_MGMTBUF_DEQUEUE_FROM_HW_SFQ 19 +#define TXRX_MGMTBUF_PAUSE_HW_TXQ 20 +#define TXRX_MGMTBUF_RESUME_HW_TXQ 21 +#define TXRX_MGMTBUF_DBGID_DEFINITION_END + +/* PM (Power Module) debug identifier definitions */ +#define PM_DBGID_DEFINITION_START +#define PM_INIT 1 +#define PM_ENABLE 2 +#define PM_SET_STATE 3 +#define PM_SET_POWERMODE 4 +#define PM_CONN_NOTIFY 5 +#define PM_REF_COUNT_NEGATIVE 6 +#define PM_APSD_ENABLE 7 +#define PM_UPDATE_APSD_STATE 8 +#define PM_CHAN_OP_REQ 9 +#define PM_SET_MY_BEACON_POLICY 10 +#define PM_SET_ALL_BEACON_POLICY 11 +#define PM_SET_PM_PARAMS1 12 +#define PM_SET_PM_PARAMS2 13 +#define PM_ADHOC_SET_PM_CAPS_FAIL 14 +#define PM_ADHOC_UNKNOWN_IBSS_ATTRIB_ID 15 +#define PM_DBGID_DEFINITION_END + +/* Wake on Wireless debug identifier definitions */ +#define WOW_DBGID_DEFINITION_START +#define WOW_INIT 1 +#define WOW_GET_CONFIG_DSET 2 +#define WOW_NO_CONFIG_DSET 3 +#define WOW_INVALID_CONFIG_DSET 4 +#define WOW_USE_DEFAULT_CONFIG 5 +#define WOW_SETUP_GPIO 6 +#define WOW_INIT_DONE 7 +#define WOW_SET_GPIO_PIN 8 +#define WOW_CLEAR_GPIO_PIN 9 +#define WOW_SET_WOW_MODE_CMD 10 +#define WOW_SET_HOST_MODE_CMD 11 +#define WOW_ADD_WOW_PATTERN_CMD 12 +#define WOW_NEW_WOW_PATTERN_AT_INDEX 13 +#define WOW_DEL_WOW_PATTERN_CMD 14 +#define WOW_LIST_CONTAINS_PATTERNS 15 +#define WOW_GET_WOW_LIST_CMD 16 +#define WOW_INVALID_FILTER_ID 17 +#define WOW_INVALID_FILTER_LISTID 18 +#define WOW_NO_VALID_FILTER_AT_ID 19 +#define WOW_NO_VALID_LIST_AT_ID 20 +#define WOW_NUM_PATTERNS_EXCEEDED 21 +#define WOW_NUM_LISTS_EXCEEDED 22 +#define WOW_GET_WOW_STATS 23 +#define WOW_CLEAR_WOW_STATS 24 +#define WOW_WAKEUP_HOST 25 +#define WOW_EVENT_WAKEUP_HOST 26 +#define WOW_EVENT_DISCARD 27 +#define WOW_PATTERN_MATCH 28 +#define WOW_PATTERN_NOT_MATCH 29 +#define WOW_PATTERN_NOT_MATCH_OFFSET 30 +#define WOW_DISABLED_HOST_ASLEEP 31 +#define WOW_ENABLED_HOST_ASLEEP_NO_PATTERNS 32 +#define WOW_ENABLED_HOST_ASLEEP_NO_MATCH_FOUND 33 +#define WOW_DBGID_DEFINITION_END + +/* WHAL debug identifier definitions */ +#define WHAL_DBGID_DEFINITION_START +#define WHAL_ERROR_ANI_CONTROL 1 +#define WHAL_ERROR_CHIP_TEST1 2 +#define WHAL_ERROR_CHIP_TEST2 3 +#define WHAL_ERROR_EEPROM_CHECKSUM 4 +#define WHAL_ERROR_EEPROM_MACADDR 5 +#define WHAL_ERROR_INTERRUPT_HIU 6 +#define WHAL_ERROR_KEYCACHE_RESET 7 +#define WHAL_ERROR_KEYCACHE_SET 8 +#define WHAL_ERROR_KEYCACHE_TYPE 9 +#define WHAL_ERROR_KEYCACHE_TKIPENTRY 10 +#define WHAL_ERROR_KEYCACHE_WEPLENGTH 11 +#define WHAL_ERROR_PHY_INVALID_CHANNEL 12 +#define WHAL_ERROR_POWER_AWAKE 13 +#define WHAL_ERROR_POWER_SET 14 +#define WHAL_ERROR_RECV_STOPDMA 15 +#define WHAL_ERROR_RECV_STOPPCU 16 +#define WHAL_ERROR_RESET_CHANNF1 17 +#define WHAL_ERROR_RESET_CHANNF2 18 +#define WHAL_ERROR_RESET_PM 19 +#define WHAL_ERROR_RESET_OFFSETCAL 20 +#define WHAL_ERROR_RESET_RFGRANT 21 +#define WHAL_ERROR_RESET_RXFRAME 22 +#define WHAL_ERROR_RESET_STOPDMA 23 +#define WHAL_ERROR_RESET_RECOVER 24 +#define WHAL_ERROR_XMIT_COMPUTE 25 +#define WHAL_ERROR_XMIT_NOQUEUE 26 +#define WHAL_ERROR_XMIT_ACTIVEQUEUE 27 +#define WHAL_ERROR_XMIT_BADTYPE 28 +#define WHAL_DBGID_DEFINITION_END + +/* DC debug identifier definitions */ +#define DC_DBGID_DEFINITION_START +#define DC_SCAN_CHAN_START 1 +#define DC_SCAN_CHAN_FINISH 2 +#define DC_BEACON_RECEIVE7 3 +#define DC_SSID_PROBE_CB 4 +#define DC_SEND_NEXT_SSID_PROBE 5 +#define DC_START_SEARCH 6 +#define DC_CANCEL_SEARCH_CB 7 +#define DC_STOP_SEARCH 8 +#define DC_END_SEARCH 9 +#define DC_MIN_CHDWELL_TIMEOUT 10 +#define DC_START_SEARCH_CANCELED 11 +#define DC_SET_POWER_MODE 12 +#define DC_INIT 13 +#define DC_SEARCH_OPPORTUNITY 14 +#define DC_RECEIVED_ANY_BEACON 15 +#define DC_RECEIVED_MY_BEACON 16 +#define DC_PROFILE_IS_ADHOC_BUT_BSS_IS_INFRA 17 +#define DC_PS_ENABLED_BUT_ATHEROS_IE_ABSENT 18 +#define DC_BSS_ADHOC_CHANNEL_NOT_ALLOWED 19 +#define DC_SET_BEACON_UPDATE 20 +#define DC_BEACON_UPDATE_COMPLETE 21 +#define DC_END_SEARCH_BEACON_UPDATE_COMP_CB 22 +#define DC_BSSINFO_EVENT_DROPPED 23 +#define DC_DBGID_DEFINITION_END + +/* CO debug identifier definitions */ +#define CO_DBGID_DEFINITION_START +#define CO_INIT 1 +#define CO_ACQUIRE_LOCK 2 +#define CO_START_OP1 3 +#define CO_START_OP2 4 +#define CO_DRAIN_TX_COMPLETE_CB 5 +#define CO_CHANGE_CHANNEL_CB 6 +#define CO_RETURN_TO_HOME_CHANNEL 7 +#define CO_FINISH_OP_TIMEOUT 8 +#define CO_OP_END 9 +#define CO_CANCEL_OP 10 +#define CO_CHANGE_CHANNEL 11 +#define CO_RELEASE_LOCK 12 +#define CO_CHANGE_STATE 13 +#define CO_DBGID_DEFINITION_END + +/* RO debug identifier definitions */ +#define RO_DBGID_DEFINITION_START +#define RO_REFRESH_ROAM_TABLE 1 +#define RO_UPDATE_ROAM_CANDIDATE 2 +#define RO_UPDATE_ROAM_CANDIDATE_CB 3 +#define RO_UPDATE_ROAM_CANDIDATE_FINISH 4 +#define RO_REFRESH_ROAM_TABLE_DONE 5 +#define RO_PERIODIC_SEARCH_CB 6 +#define RO_PERIODIC_SEARCH_TIMEOUT 7 +#define RO_INIT 8 +#define RO_BMISS_STATE1 9 +#define RO_BMISS_STATE2 10 +#define RO_SET_PERIODIC_SEARCH_ENABLE 11 +#define RO_SET_PERIODIC_SEARCH_DISABLE 12 +#define RO_ENABLE_SQ_THRESHOLD 13 +#define RO_DISABLE_SQ_THRESHOLD 14 +#define RO_ADD_BSS_TO_ROAM_TABLE 15 +#define RO_SET_PERIODIC_SEARCH_MODE 16 +#define RO_CONFIGURE_SQ_THRESHOLD1 17 +#define RO_CONFIGURE_SQ_THRESHOLD2 18 +#define RO_CONFIGURE_SQ_PARAMS 19 +#define RO_LOW_SIGNAL_QUALITY_EVENT 20 +#define RO_HIGH_SIGNAL_QUALITY_EVENT 21 +#define RO_REMOVE_BSS_FROM_ROAM_TABLE 22 +#define RO_UPDATE_CONNECTION_STATE_METRIC 23 +#define RO_LOWRSSI_SCAN_PARAMS 24 +#define RO_LOWRSSI_SCAN_START 25 +#define RO_LOWRSSI_SCAN_END 26 +#define RO_LOWRSSI_SCAN_CANCEL 27 +#define RO_LOWRSSI_ROAM_CANCEL 28 +#define RO_DBGID_DEFINITION_END + +/* CM debug identifier definitions */ +#define CM_DBGID_DEFINITION_START +#define CM_INITIATE_HANDOFF 1 +#define CM_INITIATE_HANDOFF_CB 2 +#define CM_CONNECT_EVENT 3 +#define CM_DISCONNECT_EVENT 4 +#define CM_INIT 5 +#define CM_HANDOFF_SOURCE 6 +#define CM_SET_HANDOFF_TRIGGERS 7 +#define CM_CONNECT_REQUEST 8 +#define CM_CONNECT_REQUEST_CB 9 +#define CM_CONTINUE_SCAN_CB 10 +#define CM_DBGID_DEFINITION_END + +/* PY debug identifier definitions */ +#define PY_DBGID_DEFINITION_START +#define PY_DEVICE_DISCOVER 1 +#define PY_DEVICE_CONNECT 2 +#define PY_DEVICE_DISCONNECT 3 +#define PY_CONNECT_NOTIFY 4 +#define PY_DATA_WINDOW_NOTIFY 5 +#define PY_CANCEL_OP 6 +#define PY_DISCOVERY_WINDOW_NOTIFY 7 +#define PY_PROCESS_PYXIS_MSGTYPE 8 +#define PY_SEND_PYXIS_MSGTYPE 9 +#define PY_DBGID_DEFINITION_END + +/* TMR debug identifier definitions */ +#define TMR_DBGID_DEFINITION_START +#define TMR_HANG_DETECTED 1 +#define TMR_WDT_TRIGGERED 2 +#define TMR_WDT_RESET 3 +#define TMR_HANDLER_ENTRY 4 +#define TMR_HANDLER_EXIT 5 +#define TMR_SAVED_START 6 +#define TMR_SAVED_END 7 +#define TMR_DBGID_DEFINITION_END + +/* BTCOEX debug identifier definitions */ +#define BTCOEX_DBGID_DEFINITION_START +#define BTCOEX_STATUS_CMD 1 +#define BTCOEX_PARAMS_CMD 2 +#define BTCOEX_ANT_CONFIG 3 +#define BTCOEX_COLOCATED_BT_DEVICE 4 +#define BTCOEX_CLOSE_RANGE_SCO_ON 5 +#define BTCOEX_CLOSE_RANGE_SCO_OFF 6 +#define BTCOEX_CLOSE_RANGE_A2DP_ON 7 +#define BTCOEX_CLOSE_RANGE_A2DP_OFF 8 +#define BTCOEX_A2DP_PROTECT_ON 9 +#define BTCOEX_A2DP_PROTECT_OFF 10 +#define BTCOEX_SCO_PROTECT_ON 11 +#define BTCOEX_SCO_PROTECT_OFF 12 +#define BTCOEX_CLOSE_RANGE_DETECTOR_START 13 +#define BTCOEX_CLOSE_RANGE_DETECTOR_STOP 14 +#define BTCOEX_CLOSE_RANGE_TOGGLE 15 +#define BTCOEX_CLOSE_RANGE_TOGGLE_RSSI_LRCNT 16 +#define BTCOEX_CLOSE_RANGE_RSSI_THRESH 17 +#define BTCOEX_CLOSE_RANGE_LOW_RATE_THRESH 18 +#define BTCOEX_WEIGHTS 19 +#define BTCOEX_A2DP_DWNLINK 20 +#define BTCOEX_BMISS_PROTECT 21 +#define BTCOEX_BMISS_PROTECT_OFF 22 +#define BTCOEX_DATA_RES_TIMEOUT 23 +#define BTCOEX_DATA_ACTIVITY_TIMEOUT_HANDLER 24 +#define BTCOEX_BCN_INTRVL_TIMEOUT 25 +#define BTCOEX_A2DP_TRIGGER 26 +#define BTCOEX_OBS_REG 27 +#define BTCOEX_PHY_REG 28 +#define BTCOEX_RESET_RADIO 29 +#define BTCOEX_BMISS_NOTIFY 30 +#define BTCOEX_PSPOLL_CALLBACK 31 +#define BTCOEX_WLAN_STATE 32 +#define BTCOEX_CONNECT_START 33 +#define BTCOEX_SCAN_START 34 +#define BTCOEX_SCAN_END 35 +#define BTCOEX_RESET_WHAL 36 +#define BTCOEX_RX_FRAME_COUNTER 37 +#define BTCOEX_RX_FRAME_CLR_CNTR 38 +#define BTCOEX_RX_DP 39 +#define BTCOEX_RX_ABRT 40 +#define BTCOEX_RX_FRAME_SET_CNT 41 +#define BTCOEX_AGCCCA_REG 42 +#define BTCOEX_RSSI_REG 43 +#define BTCOEX_A2DP_PARAM_VAL 44 +#define BTCOEX_MODE 45 +#define BTCOEX_SEND_PSPOLL 46 +#define BTCOEX_SET_UPLINK_RATE 47 +#define BTCOEX_SLEEP_STATUS 48 +#define BTCOEX_RECONNECT_REQ 49 +#define BTCOEX_RECEIVE_NOTIFY 50 +#define BTCOEX_PACKET_COUNT 51 +#define BTCOEX_A2DP_START_WLAN_TRIG 52 +#define BTCOEX_A2DP_HANDLER_TRIG 53 +#define BTCOEX_PM_AWAKE_CNT 54 +#define BTCOEX_PM_SLEEP_CNT 55 +#define BTCOEX_BB_REG 56 +#define BTCOEX_MAC_REG 57 +#define BTCOEX_ACL_PARAM_VAL 58 +#define BTCOEX_SCO_HOST_BOUNDS 60 +#define BTCOEX_A2DP_HOST_BOUNDS 61 +#define BTCOEX_CLOSE_RANGE_BOUNDS 62 +#define BTCOEX_TOGGLE_VALUES 63 +#define BTCOEX_DBGID_DEFINITION_END + +#ifdef __cplusplus +} +#endif + +#endif /* _DBGLOG_ID_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/debug_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/debug_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/debug_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/debug_linux.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2004-2006 Atheros Communications Inc. + * All rights reserved. + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _DEBUG_LINUX_H_ +#define _DEBUG_LINUX_H_ + +#define DBG_DEFAULTS (DBG_ERROR|DBG_WARNING) + +extern A_UINT32 g_dbg_flags; + +#define DBGFMT "%s() : " +#define DBGARG __func__ +#define DBGFN A_PRINTF + +#define ATHR_DISPLAY_MSG printk +#define _T(x) x + +/* ------- Debug related stuff ------- */ +enum { + ATH_DEBUG_SEND = 0x0001, + ATH_DEBUG_RECV = 0x0002, + ATH_DEBUG_SYNC = 0x0004, + ATH_DEBUG_DUMP = 0x0008, + ATH_DEBUG_IRQ = 0x0010, + ATH_DEBUG_TRC = 0x0020, + ATH_DEBUG_WARN = 0x0040, + ATH_DEBUG_ERR = 0x0080, + ATH_LOG_INF = 0x0100, + ATH_DEBUG_BMI = 0x0110, + ATH_DEBUG_WMI = 0x0120, + ATH_DEBUG_HIF = 0x0140, + ATH_DEBUG_HTC = 0x0180, + ATH_DEBUG_WLAN = 0x1000, + ATH_LOG_ERR = 0x1010, + ATH_DEBUG_ANY = 0xFFFF, +}; + +#ifdef DEBUG +#define A_DPRINTF(f, a) \ + if(g_dbg_flags & (f)) \ + { \ + DBGFN a ; \ + } + + +// TODO FIX usage of A_PRINTF! +#define AR_DEBUG_LVL_CHECK(lvl) (debughtc & (lvl)) +#define AR_DEBUG_PRINTBUF(buffer, length, desc) do { \ + if (debughtc & ATH_DEBUG_DUMP) { \ + DebugDumpBytes(buffer, length,desc); \ + } \ +} while(0) +#define PRINTX_ARG(arg...) arg +#define AR_DEBUG_PRINTF(flags, args) do { \ + if (debughtc & (flags)) { \ + A_PRINTF(KERN_ALERT PRINTX_ARG args); \ + } \ +} while (0) +#define AR_DEBUG_ASSERT(test) do { \ + if (!(test)) { \ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test)); \ + } \ +} while(0) +extern int debughtc; +#else +#define AR_DEBUG_PRINTF(flags, args) +#define AR_DEBUG_PRINTBUF(buffer, length, desc) +#define AR_DEBUG_ASSERT(test) +#define AR_DEBUG_LVL_CHECK(lvl) 0 +#define A_DPRINTF(f, a) +#endif + +#endif /* _DEBUG_LINUX_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/discovery.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/discovery.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/discovery.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/discovery.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,74 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _DISCOVERY_H_ +#define _DISCOVERY_H_ + +/* + * DC_SCAN_PRIORITY is an 8-bit bitmap of the scan priority of a channel + */ +typedef enum { + DEFAULT_SCPRI = 0x01, + POPULAR_SCPRI = 0x02, + SSIDS_SCPRI = 0x04, + PROF_SCPRI = 0x08, +} DC_SCAN_PRIORITY; + +/* The following search type construct can be used to manipulate the behavior of the search module based on different bits set */ +typedef enum { + SCAN_RESET = 0, + SCAN_ALL = (DEFAULT_SCPRI | POPULAR_SCPRI | \ + SSIDS_SCPRI | PROF_SCPRI), + + SCAN_POPULAR = (POPULAR_SCPRI | SSIDS_SCPRI | PROF_SCPRI), + SCAN_SSIDS = (SSIDS_SCPRI | PROF_SCPRI), + SCAN_PROF_MASK = (PROF_SCPRI), + SCAN_MULTI_CHANNEL = 0x000100, + SCAN_DETERMINISTIC = 0x000200, + SCAN_PROFILE_MATCH_TERMINATED = 0x000400, + SCAN_HOME_CHANNEL_SKIP = 0x000800, + SCAN_CHANNEL_LIST_CONTINUE = 0x001000, + SCAN_CURRENT_SSID_SKIP = 0x002000, + SCAN_ACTIVE_PROBE_DISABLE = 0x004000, + SCAN_CHANNEL_HINT_ONLY = 0x008000, + SCAN_ACTIVE_CHANNELS_ONLY = 0x010000, + SCAN_PYXIS_DISCOVERY = 0x020000, + SCAN_PERIODIC = 0x040200, + SCAN_FIXED_DURATION = 0x080000, +} DC_SCAN_TYPE; + +typedef enum { + BSS_REPORTING_DEFAULT = 0x0, + EXCLUDE_NON_SCAN_RESULTS = 0x1, /* Exclude results outside of scan */ +} DC_BSS_REPORTING_POLICY; + +typedef enum { + DC_IGNORE_WPAx_GROUP_CIPHER = 0x01, + DC_PROFILE_MATCH_DONE = 0x02, + DC_IGNORE_AAC_BEACON = 0x04, + DC_CSA_FOLLOW_BSS = 0x08, +} DC_PROFILE_FILTER; + +#define DEFAULT_DC_PROFILE_FILTER (DC_CSA_FOLLOW_BSS) + +#endif /* _DISCOVERY_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/dl_list.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/dl_list.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/dl_list.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/dl_list.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,119 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Double-link list definitions (adapted from Atheros SDIO stack) +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef __DL_LIST_H___ +#define __DL_LIST_H___ + + +#define A_CONTAINING_STRUCT(address, struct_type, field_name)\ + ((struct_type *)((A_UINT32)(address) - (A_UINT32)(&((struct_type *)0)->field_name))) + +/* list functions */ +/* pointers for the list */ +typedef struct _DL_LIST { + struct _DL_LIST *pPrev; + struct _DL_LIST *pNext; +}DL_LIST, *PDL_LIST; +/* + * DL_LIST_INIT , initialize doubly linked list +*/ +#define DL_LIST_INIT(pList)\ + {(pList)->pPrev = pList; (pList)->pNext = pList;} + +#define DL_LIST_IS_EMPTY(pList) (((pList)->pPrev == (pList)) && ((pList)->pNext == (pList))) +#define DL_LIST_GET_ITEM_AT_HEAD(pList) (pList)->pNext +#define DL_LIST_GET_ITEM_AT_TAIL(pList) (pList)->pPrev +/* + * ITERATE_OVER_LIST pStart is the list, pTemp is a temp list member + * NOT: do not use this function if the items in the list are deleted inside the + * iteration loop +*/ +#define ITERATE_OVER_LIST(pStart, pTemp) \ + for((pTemp) =(pStart)->pNext; pTemp != (pStart); (pTemp) = (pTemp)->pNext) + + +/* safe iterate macro that allows the item to be removed from the list + * the iteration continues to the next item in the list + */ +#define ITERATE_OVER_LIST_ALLOW_REMOVE(pStart,pItem,st,offset) \ +{ \ + PDL_LIST pTemp; \ + pTemp = (pStart)->pNext; \ + while (pTemp != (pStart)) { \ + (pItem) = A_CONTAINING_STRUCT(pTemp,st,offset); \ + pTemp = pTemp->pNext; \ + +#define ITERATE_END }} + +/* + * DL_ListInsertTail - insert pAdd to the end of the list +*/ +static INLINE PDL_LIST DL_ListInsertTail(PDL_LIST pList, PDL_LIST pAdd) { + /* insert at tail */ + pAdd->pPrev = pList->pPrev; + pAdd->pNext = pList; + pList->pPrev->pNext = pAdd; + pList->pPrev = pAdd; + return pAdd; +} + +/* + * DL_ListInsertHead - insert pAdd into the head of the list +*/ +static INLINE PDL_LIST DL_ListInsertHead(PDL_LIST pList, PDL_LIST pAdd) { + /* insert at head */ + pAdd->pPrev = pList; + pAdd->pNext = pList->pNext; + pList->pNext->pPrev = pAdd; + pList->pNext = pAdd; + return pAdd; +} + +#define DL_ListAdd(pList,pItem) DL_ListInsertHead((pList),(pItem)) +/* + * DL_ListRemove - remove pDel from list +*/ +static INLINE PDL_LIST DL_ListRemove(PDL_LIST pDel) { + pDel->pNext->pPrev = pDel->pPrev; + pDel->pPrev->pNext = pDel->pNext; + /* point back to itself just to be safe, incase remove is called again */ + pDel->pNext = pDel; + pDel->pPrev = pDel; + return pDel; +} + +/* + * DL_ListRemoveItemFromHead - get a list item from the head +*/ +static INLINE PDL_LIST DL_ListRemoveItemFromHead(PDL_LIST pList) { + PDL_LIST pItem = NULL; + if (pList->pNext != pList) { + pItem = pList->pNext; + /* remove the first item from head */ + DL_ListRemove(pItem); + } + return pItem; +} + +#endif /* __DL_LIST_H___ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/dset_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/dset_api.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/dset_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/dset_api.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,65 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Host-side DataSet API. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _DSET_API_H_ +#define _DSET_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* + * Host-side DataSet support is optional, and is not + * currently required for correct operation. To disable + * Host-side DataSet support, set this to 0. + */ +#ifndef CONFIG_HOST_DSET_SUPPORT +#define CONFIG_HOST_DSET_SUPPORT 1 +#endif + +/* Called to send a DataSet Open Reply back to the Target. */ +A_STATUS wmi_dset_open_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT32 access_cookie, + A_UINT32 size, + A_UINT32 version, + A_UINT32 targ_handle, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); + +/* Called to send a DataSet Data Reply back to the Target. */ +A_STATUS wmi_dset_data_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT8 *host_buf, + A_UINT32 length, + A_UINT32 targ_buf, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* _DSET_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/dset_internal.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/dset_internal.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/dset_internal.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/dset_internal.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,55 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + + +#ifndef __DSET_INTERNAL_H__ +#define __DSET_INTERNAL_H__ + +/* + * Internal dset definitions, common for DataSet layer. + */ + +#define DSET_TYPE_STANDARD 0 +#define DSET_TYPE_BPATCHED 1 +#define DSET_TYPE_COMPRESSED 2 + +/* Dataset descriptor */ + +typedef struct dset_descriptor_s { + struct dset_descriptor_s *next; /* List link. NULL only at the last + descriptor */ + A_UINT16 id; /* Dset ID */ + A_UINT16 size; /* Dset size. */ + void *DataPtr; /* Pointer to raw data for standard + DataSet or pointer to original + dset_descriptor for patched + DataSet */ + A_UINT32 data_type; /* DSET_TYPE_*, above */ + + void *AuxPtr; /* Additional data that might + needed for data_type. For + example, pointer to patch + Dataset descriptor for BPatch. */ +} dset_descriptor_t; + +#endif /* __DSET_INTERNAL_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/dsetid.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/dsetid.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/dsetid.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/dsetid.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,126 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + + +#ifndef __DSETID_H__ +#define __DSETID_H__ + +/* Well-known DataSet IDs */ +#define DSETID_UNUSED 0x00000000 +#define DSETID_BOARD_DATA 0x00000001 /* Cal and board data */ +#define DSETID_REGDB 0x00000002 /* Regulatory Database */ +#define DSETID_POWER_CONTROL 0x00000003 /* TX Pwr Lim & Ant Gain */ +#define DSETID_USER_CONFIG 0x00000004 /* User Configuration */ + +#define DSETID_ANALOG_CONTROL_DATA_START 0x00000005 +#define DSETID_ANALOG_CONTROL_DATA_END 0x00000025 +/* + * Get DSETID for various reference clock speeds. + * For each speed there are three DataSets that correspond + * to the three columns of bank6 data (addr, 11a, 11b/g). + * This macro returns the dsetid of the first of those + * three DataSets. + */ +#define ANALOG_CONTROL_DATA_DSETID(refclk) \ + (DSETID_ANALOG_CONTROL_DATA_START + 3*refclk) + +/* + * There are TWO STARTUP_PATCH DataSets. + * DSETID_STARTUP_PATCH is historical, and was applied before BMI on + * earlier systems. On AR6002, it is applied after BMI, just like + * DSETID_STARTUP_PATCH2. + */ +#define DSETID_STARTUP_PATCH 0x00000026 +#define DSETID_GPIO_CONFIG_PATCH 0x00000027 +#define DSETID_WLANREGS 0x00000028 /* override wlan regs */ +#define DSETID_STARTUP_PATCH2 0x00000029 + +#define DSETID_WOW_CONFIG 0x00000090 /* WoW Configuration */ + +/* Add WHAL_INI_DATA_ID to DSETID_INI_DATA for a specific WHAL INI table. */ +#define DSETID_INI_DATA 0x00000100 +/* Reserved for WHAL INI Tables: 0x100..0x11f */ +#define DSETID_INI_DATA_END 0x0000011f + +#define DSETID_VENDOR_START 0x00010000 /* Vendor-defined DataSets */ + +#define DSETID_INDEX_END 0xfffffffe /* Reserved to indicate the + end of a memory-based + DataSet Index */ +#define DSETID_INDEX_FREE 0xffffffff /* An unused index entry */ + +/* + * PATCH DataSet format: + * A list of patches, terminated by a patch with + * address=PATCH_END. + * + * This allows for patches to be stored in flash. + */ +struct patch_s { + A_UINT32 *address; + A_UINT32 data; +}; + +/* + * Skip some patches. Can be used to erase a single patch in a + * patch DataSet without having to re-write the DataSet. May + * also be used to embed information for use by subsequent + * patch code. The "data" in a PATCH_SKIP tells how many + * bytes of length "patch_s" to skip. + */ +#define PATCH_SKIP ((A_UINT32 *)0x00000000) + +/* + * Execute code at the address specified by "data". + * The address of the patch structure is passed as + * the one parameter. + */ +#define PATCH_CODE_ABS ((A_UINT32 *)0x00000001) + +/* + * Same as PATCH_CODE_ABS, but treat "data" as an + * offset from the start of the patch word. + */ +#define PATCH_CODE_REL ((A_UINT32 *)0x00000002) + +/* Mark the end of this patch DataSet. */ +#define PATCH_END ((A_UINT32 *)0xffffffff) + +/* + * A DataSet which contains a Binary Patch to some other DataSet + * uses the original dsetid with the DSETID_BPATCH_FLAG bit set. + * Such a BPatch DataSet consists of BPatch metadata followed by + * the bdiff bytes. BPatch metadata consists of a single 32-bit + * word that contains the size of the BPatched final image. + * + * To create a suitable bdiff DataSet, use bdiff in host/tools/bdiff + * to create "diffs": + * bdiff -q -O -nooldmd5 -nonewmd5 -d ORIGfile NEWfile diffs + * Then add BPatch metadata to the start of "diffs". + * + * NB: There are some implementation-induced restrictions + * on which DataSets can be BPatched. + */ +#define DSETID_BPATCH_FLAG 0x80000000 + +#endif /* __DSETID_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/eeprom.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/eeprom.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/eeprom.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/eeprom.c 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,588 @@ +/* + * Copyright (c) 2006 Atheros Communications, Inc. + * All rights reserved. + * + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#include "ar6000_drv.h" +#include "htc.h" +#include + +#include "apb_map.h" +#include "gpio_reg.h" +#ifndef ANDROID_ENV +#include "rtc_reg.h" +#endif +#include "si_reg.h" + +// +// defines +// + +#define MAX_FILENAME 1023 +#define EEPROM_WAIT_LIMIT 16 + +#define HOST_INTEREST_ITEM_ADDRESS(item) \ + (AR6002_HOST_INTEREST_ITEM_ADDRESS(item)) + +#define EEPROM_SZ 768 + +/* soft mac */ +#define ATH_MAC_LEN 6 +#define ATH_SOFT_MAC_TMP_BUF_LEN 64 +unsigned char mac_addr[ATH_MAC_LEN]; +unsigned char soft_mac_tmp_buf[ATH_SOFT_MAC_TMP_BUF_LEN]; +char *p_mac = NULL; +/* soft mac */ + +// +// static variables +// + +static A_UCHAR eeprom_data[EEPROM_SZ]; +static A_UINT32 sys_sleep_reg; +static HIF_DEVICE *p_bmi_device; + +// +// Functions +// + +/* soft mac */ +static int +wmic_ether_aton(const char *orig, A_UINT8 *eth) +{ + const char *bufp; + int i; + + i = 0; + for(bufp = orig; *bufp != '\0'; ++bufp) { + unsigned int val; + unsigned char c = *bufp++; + if (c >= '0' && c <= '9') val = c - '0'; + else if (c >= 'a' && c <= 'f') val = c - 'a' + 10; + else if (c >= 'A' && c <= 'F') val = c - 'A' + 10; + else { + printk("%s: MAC value is invalid\n", __FUNCTION__); + break; + } + + val <<= 4; + c = *bufp++; + if (c >= '0' && c <= '9') val |= c - '0'; + else if (c >= 'a' && c <= 'f') val |= c - 'a' + 10; + else if (c >= 'A' && c <= 'F') val |= c - 'A' + 10; + else { + printk("%s: MAC value is invalid\n", __FUNCTION__); + break; + } + + eth[i] = (unsigned char) (val & 0377); + if(++i == ATH_MAC_LEN) { + /* That's it. Any trailing junk? */ + if (*bufp != '\0') { + return 0; + } + return 1; + } + if (*bufp != ':') + break; + } + return 0; +} + +static void +update_mac(unsigned char* eeprom, int size, unsigned char* macaddr) +{ + int i; + A_UINT16* ptr = (A_UINT16*)(eeprom+4); + A_UINT16 checksum = 0; + + memcpy(eeprom+10,macaddr,6); + + *ptr = 0; + ptr = (A_UINT16*)eeprom; + + for (i=0; i>7)); + + BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval); + + regval = SI_CS_START_SET(1) | + SI_CS_RX_CNT_SET(8) | + SI_CS_TX_CNT_SET(3); + BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval); +} + +/* + * Tell the Target to start a 4-byte write to EEPROM, + * writing values from Target TX_DATA registers. + */ +static void +request_4byte_write(int offset, A_UINT32 data) +{ + A_UINT32 regval; + + printk("%s: request_4byte_write (0x%x) to offset 0x%x\n", __FUNCTION__, data, offset); + + /* SI_TX_DATA0 = write data to offset */ + regval = ((data & 0xffff) <<16) | + ((offset & 0xff)<<8) | + (0xa0 | ((offset & 0xff00)>>7)); + BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval); + + regval = data >> 16; + BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA1_OFFSET, regval); + + regval = SI_CS_START_SET(1) | + SI_CS_RX_CNT_SET(0) | + SI_CS_TX_CNT_SET(6); + BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval); +} + +/* + * Check whether or not an EEPROM request that was started + * earlier has completed yet. + */ +static A_BOOL +request_in_progress(void) +{ + A_UINT32 regval; + + /* Wait for DONE_INT in SI_CS */ + BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, ®val); + +// printk("%s: request in progress SI_CS=0x%x\n", __FUNCTION__, regval); + if (regval & SI_CS_DONE_ERR_MASK) { + printk("%s: EEPROM signaled ERROR (0x%x)\n", __FUNCTION__, regval); + } + + return (!(regval & SI_CS_DONE_INT_MASK)); +} + +/* + * try to detect the type of EEPROM,16bit address or 8bit address + */ + +static void eeprom_type_detect(void) +{ + A_UINT32 regval; + A_UINT8 i = 0; + + request_8byte_read(0x100); + /* Wait for DONE_INT in SI_CS */ + do{ + BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, ®val); + if (regval & SI_CS_DONE_ERR_MASK) { + printk("%s: ERROR : address type was wrongly set\n", __FUNCTION__); + break; + } + if (i++ == EEPROM_WAIT_LIMIT) { + printk("%s: EEPROM not responding\n", __FUNCTION__); + } + } while(!(regval & SI_CS_DONE_INT_MASK)); +} + +/* + * Extract the results of a completed EEPROM Read request + * and return them to the caller. + */ +inline void +read_8byte_results(A_UINT32 *data) +{ + /* Read SI_RX_DATA0 and SI_RX_DATA1 */ + BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA0_OFFSET, &data[0]); + BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA1_OFFSET, &data[1]); +} + + +/* + * Wait for a previously started command to complete. + * Timeout if the command is takes "too long". + */ +static void +wait_for_eeprom_completion(void) +{ + int i=0; + + while (request_in_progress()) { + if (i++ == EEPROM_WAIT_LIMIT) { + printk("%s: EEPROM not responding\n", __FUNCTION__); + } + } +} + +/* + * High-level function which starts an 8-byte read, + * waits for it to complete, and returns the result. + */ +static void +fetch_8bytes(int offset, A_UINT32 *data) +{ + request_8byte_read(offset); + wait_for_eeprom_completion(); + read_8byte_results(data); + + /* Clear any pending intr */ + BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, SI_CS_DONE_INT_MASK); +} + +/* + * High-level function which starts a 4-byte write, + * and waits for it to complete. + */ +inline void +commit_4bytes(int offset, A_UINT32 data) +{ + request_4byte_write(offset, data); + wait_for_eeprom_completion(); +} +/* ATHENV */ +#ifdef ANDROID_ENV +void eeprom_ar6000_transfer(HIF_DEVICE *device, char *fake_file, char *p_mac) +{ + A_UINT32 first_word; + A_UINT32 board_data_addr; + int i; + + printk("%s: Enter\n", __FUNCTION__); + + enable_SI(device); + eeprom_type_detect(); + + if (fake_file) { + /* + * Transfer from file to Target RAM. + * Fetch source data from file. + */ + mm_segment_t oldfs; + struct file *filp; + struct inode *inode = NULL; + int length; + + /* open file */ + oldfs = get_fs(); + set_fs(KERNEL_DS); + filp = filp_open(fake_file, O_RDONLY, S_IRUSR); + + if (IS_ERR(filp)) { + printk("%s: file %s filp_open error\n", __FUNCTION__, fake_file); + set_fs(oldfs); + return; + } + + if (!filp->f_op) { + printk("%s: File Operation Method Error\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + inode = filp->f_path.dentry->d_inode; +#else + inode = filp->f_dentry->d_inode; +#endif + + if (!inode) { + printk("%s: Get inode from filp failed\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos); + + /* file's size */ + length = i_size_read(inode->i_mapping->host); + printk("%s: length=%d\n", __FUNCTION__, length); + if (length != EEPROM_SZ) { + printk("%s: The file's size is not as expected\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + /* read data */ + if (filp->f_op->read(filp, eeprom_data, length, &filp->f_pos) != length) { + printk("%s: file read error\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + /* read data out successfully */ + filp_close(filp, NULL); + set_fs(oldfs); + } else { + /* + * Read from EEPROM to file OR transfer from EEPROM to Target RAM. + * Fetch EEPROM_SZ Bytes of Board Data, 8 bytes at a time. + */ + + fetch_8bytes(0, (A_UINT32 *)(&eeprom_data[0])); + + /* Check the first word of EEPROM for validity */ + first_word = *((A_UINT32 *)eeprom_data); + + if ((first_word == 0) || (first_word == 0xffffffff)) { + printk("Did not find EEPROM with valid Board Data.\n"); + } + + for (i=8; if_op) { + printk("%s: File Operation Method Error\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + inode = filp->f_path.dentry->d_inode; +#else + inode = filp->f_dentry->d_inode; +#endif + if (!inode) { + printk("%s: Get inode from filp failed\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos); + + /* file's size */ + length = i_size_read(inode->i_mapping->host); + printk("%s: length=%d\n", __FUNCTION__, length); + if (length > ATH_SOFT_MAC_TMP_BUF_LEN) { + printk("%s: MAC file's size is not as expected\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + /* read data */ + if (filp->f_op->read(filp, soft_mac_tmp_buf, length, &filp->f_pos) != length) { + printk("%s: file read error\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + +#if 0 + /* the data we just read */ + printk("%s: mac address from the file:\n", __FUNCTION__); + for (i = 0; i < length; i++) + printk("[%c(0x%x)],", soft_mac_tmp_buf[i], soft_mac_tmp_buf[i]); + printk("\n"); +#endif + + /* read data out successfully */ + filp_close(filp, NULL); + set_fs(oldfs); + + /* convert mac address */ + if (!wmic_ether_aton(soft_mac_tmp_buf, mac_addr)) { + printk("%s: convert mac value fail\n", __FUNCTION__); + return; + } + +#if 0 + /* the converted mac address */ + printk("%s: the converted mac value\n", __FUNCTION__); + for (i = 0; i < ATH_MAC_LEN; i++) + printk("[0x%x],", mac_addr[i]); + printk("\n"); +#endif + } + /* soft mac */ + + /* Determine where in Target RAM to write Board Data */ + BMI_read_mem( HOST_INTEREST_ITEM_ADDRESS(hi_board_data), &board_data_addr); + if (board_data_addr == 0) { + printk("hi_board_data is zero\n"); + } + + /* soft mac */ +#if 1 + /* Update MAC address in RAM */ + if (p_mac) { + update_mac(eeprom_data, EEPROM_SZ, mac_addr); + } +#endif +#if 0 + /* mac address in eeprom array */ + printk("%s: mac values in eeprom array\n", __FUNCTION__); + for (i = 10; i < 10 + 6; i++) + printk("[0x%x],", eeprom_data[i]); + printk("\n"); +#endif + /* soft mac */ + + /* Write EEPROM data to Target RAM */ + BMI_write_mem(board_data_addr, ((A_UINT8 *)eeprom_data), EEPROM_SZ); + + /* Record the fact that Board Data IS initialized */ + { + A_UINT32 one = 1; + BMI_write_mem(HOST_INTEREST_ITEM_ADDRESS(hi_board_data_initialized), + (A_UINT8 *)&one, sizeof(A_UINT32)); + } + + disable_SI(); +} +#endif +/* ATHENV */ + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/engine.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/engine.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/engine.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/engine.c 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,278 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ +#include "engine.h" + +#define ACC regs[0] + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +static unsigned int regs[16]; +static int offset; +static unsigned char *cp; + +int ar6k_reg_preload( int reg, unsigned int value ) +{ + if( (reg < 0) || (reg > 16) ) + return(-1); /* Illegal register */ + + regs[ reg ] = value; + return(0); +} + +static int getoffset( void ) +{ + int i = 0; + + cp++; + offset++; + + i |= (*cp & 0xFF); cp++; offset++; + i |= (*cp & 0xFF) << 8; cp++; offset++; + i |= (*cp & 0xFF) << 16; cp++; offset++; + i |= (*cp & 0xFF) << 24; cp++; offset++; + + return(i); +} + +static int getarg( void ) +{ + int i; + + if( *cp & 0x0F ) + { + i = regs[ *cp & 0xF ]; + cp++; offset++; + return(i); + } + return( getoffset() ); +} + +static void dumpregs( void ) +{ + int i; + + sysprint("Acc: 0x%X\n", ACC); + + for(i=1; i<16; i++) + sysprint("r%x : 0x%X\n", i, regs[ i ]); + +} + +int fwengine( unsigned char *img, int size, void *ar) +{ + unsigned int crc; + int i; + + /* 14 is the minimal size of an empty image */ + if( ! (*img) || (*img != 0xFF) || (size <14) ) + { + syserr("Wrong image or no image\n"); + return -1; + } + + /* Check crc32 */ + cp = img + size - 4; + + *cp = ~(*cp) & 0xFF ; cp++; + *cp = ~(*cp) & 0xFF ; cp++; + *cp = ~(*cp) & 0xFF ; cp++; + *cp = ~(*cp) & 0xFF ; + + crc = crc32( ~0, img, size ); + + if( crc ) + { + syserr("Image CRC error\n"); + return -1; + } + + if( *(img+1) > VERSION ) + { + syserr("Image version is newer than the driver\n"); + return -1; + } + + /* Basic checks complete, we can print greeting and FW_ID here if desired */ + + /* Get to the first opcode */ + + cp = img + 2; /* Skip magic and version */ + offset = 2; + + while( (offset < size) && (*cp) ) + { + cp++; /* Skip build host name */ + offset++; + } + + cp += 6; /* Skip build date */ + offset += 6; + + while( (cp > img) && (cp < (img+size-4)) ) /* just an additional bounds check */ + { + /* First, find out opcode class */ + switch( (*cp & 0xF0) ) + { + case RLoad : + ACC = getarg( ); + break; + case Ror : + ACC |= getarg( ); + break; + case Rand : + ACC &= getarg( ); + break; + case Add : + ACC += getarg( ); + break; + case Rstor : + regs[ *cp & 0xF ] = ACC; + cp++; + offset++; + break; + case Shift : + i = getarg( ); + if(i < 0) + ACC >>= -i; + else + ACC <<= i; + break; + case Nneg : + if( *cp & 0xF ) + regs[ *cp & 0xF ] = ~regs[ *cp & 0xF ]; + else + ACC = -ACC; + cp++; + offset++; + break; + case Trr : + ACC = get_target_reg( getarg(), ar ); + break; + case Trw : + write_target_reg( getarg(), ACC , ar ); + break; + case Trx : + ACC = execute_on_target( getarg(), ACC, ar ); + break; + case Exit : + if( *cp & 0xF ) /* abort with code */ + return( regs[ *cp & 0xF ] ); + else{ /* clean exit */ + bmidone( ar ); + return(0); + } + break; + case Cmp : + ACC -= getarg(); + break; + case Ldprn : + if( ! (*cp & 0xF) ) /* register dump */ + dumpregs(); + else + { + int ret; + + ret = load_binary(ACC, cp, ar); + if( ret < 0 ) + return( -1 ); /* Error */ + cp += ret; + offset += ret; + } + break; + case Jump : + if( !(*cp & 0xF) || + ((*cp == 0xE1) && (ACC)) || + ((*cp == 0xE2) && !(ACC)) ) + + offset = getoffset(); + cp = img + offset; + + break; + default: + syserr("Image format error\n"); + break; + + } + } + return(0); +} +#ifdef UNIT_TEST +#include + +unsigned char fwbuf[ 4 * 1024 * 1024 ]; + +void bmidone( void *ar ) +{ + printf("BMI done.\n"); +} +int load_binary( unsigned int addr, unsigned char *cp, void *ar ) +{ + int size = 0; + int adv = 5; + + cp++; + size |= ( *cp & 0xFF ); cp++; + size |= ( *cp & 0xFF ) << 8; cp++; + size |= ( *cp & 0xFF ) << 16; cp++; + size |= ( *cp & 0xFF ) << 24; cp++; + + printf("Loading binary to address 0x%X, size %d\n", addr, size); + adv += size; + return(adv); +} + +int execute_on_target( unsigned address, unsigned arg, void *ar ) +{ + printf("Start target execution at address 0x%X with argument 0x%X\n", address, arg); + return(0); +} + +int write_target_reg( unsigned address, unsigned value, void *ar ) +{ + printf("Writing target register 0x%X with 0x%X\n", address, value); + return(0); +} + +unsigned int get_target_reg( unsigned address, void *ar ) +{ + unsigned int ret = 1; + + printf("Reading target register 0x%X, returning 0x%X\n", address, ret ); + return (ret); +} +int main() +{ + int ch, ret; + unsigned char *bufptr = fwbuf; + + init_crc32(); + + printf("Reading firmware image\n"); + while( (ch = getchar()) != EOF) + *bufptr++ = ch; + + printf("Calling firmware engine for image size: %d\n", bufptr - fwbuf + 1); + ret = engine( fwbuf, bufptr - fwbuf, NULL ); + printf("Engine returned with code %d\n", ret); +} +#endif /* UNIT_TEST */ +#endif /* KERNEL_VERSION 2.6 only */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/engine.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/engine.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/engine.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/engine.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,75 @@ +/* + * athloader.h - definitions for atheros firmware loader. + * + * Firmware image format: + * + * unsigned char 0xFF // "magic" + * unsigned char version // fw loader / tool version, not fw version major/minor 4 bits each + * char hostname[variable] // zero delimited hostname where the image was built + * unsigned char month // + * unsigned char day // Date and time when the image was built + * unsigned char year // year is a number of years after 2008, i.e. 2008 is coided as 0 + * unsigned char hour // + * unsigned char min // + * // the rest are optional blocks that may be repeated and/or mixed + * unsigned char instruction + * unsigned char argument[4] // optional constant, mask or offset + * unsigned char image[variable] // optional loadable image + * // repeated as necessary + * unsigned char crc32[4] // inverted crc32 + * + */ +#ifndef ATHLOADER_IS_SEEN +#define ATHLOADER_IS_SEEN + +#include + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +#define FW_AUTOLOAD +/* Uncomment the following to build standalone application for testing + +#define UNIT_TEST +#define syserr printf +#define sysprint printf +#include "crc32.h" +#include + */ + +#ifndef UNIT_TEST +#if defined(__linux__) || defined(LINUX) +#include +#include +#include +#include +#include +#include +#define syserr(arg...) printk( KERN_ERR arg) +#define sysprint(arg...) printk( KERN_INFO arg) +#endif /* __linux__ */ +#endif /* UNIT_TEST */ + +#define VERSION (0x01) + +/* Opcodes */ +#define RLoad (0x10) +#define Ror (0x20) +#define Rand (0x30) +#define Add (0x40) +#define Rstor (0x50) +#define Shift (0x60) +#define Nneg (0x70) +#define Trr (0x80) +#define Trw (0x90) +#define Trx (0xA0) +#define Exit (0xB0) +#define Cmp (0xC0) +#define Ldprn (0xD0) +#define Jump (0xE0) + +extern unsigned int get_target_reg( unsigned address, void *ar ); +extern int write_target_reg( unsigned address, unsigned value, void *ar ); +extern int execute_on_target( unsigned int address, unsigned int arg, void *ar ); +extern int load_binary(unsigned int addr, unsigned char *data, void *ar ); +extern void bmidone( void *ar ); +#endif /* KERNEL 2.6 only */ +#endif /* ATHLOADER_IS_SEEN */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/gpio.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/gpio.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/gpio.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/gpio.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,49 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2005 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#if defined(AR6001) +#define GPIO_PIN_COUNT 18 +#else +#define GPIO_PIN_COUNT 18 +#endif + +/* + * Possible values for WMIX_GPIO_SET_REGISTER_CMDID. + * NB: These match hardware order, so that addresses can + * easily be computed. + */ +#define GPIO_ID_OUT 0x00000000 +#define GPIO_ID_OUT_W1TS 0x00000001 +#define GPIO_ID_OUT_W1TC 0x00000002 +#define GPIO_ID_ENABLE 0x00000003 +#define GPIO_ID_ENABLE_W1TS 0x00000004 +#define GPIO_ID_ENABLE_W1TC 0x00000005 +#define GPIO_ID_IN 0x00000006 +#define GPIO_ID_STATUS 0x00000007 +#define GPIO_ID_STATUS_W1TS 0x00000008 +#define GPIO_ID_STATUS_W1TC 0x00000009 +#define GPIO_ID_PIN0 0x0000000a +#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) + +#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(17) +#define GPIO_ID_NONE 0xffffffff diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/gpio_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/gpio_api.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/gpio_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/gpio_api.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,59 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Host-side General Purpose I/O API. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _GPIO_API_H_ +#define _GPIO_API_H_ + +/* + * Send a command to the Target in order to change output on GPIO pins. + */ +A_STATUS wmi_gpio_output_set(struct wmi_t *wmip, + A_UINT32 set_mask, + A_UINT32 clear_mask, + A_UINT32 enable_mask, + A_UINT32 disable_mask); + +/* + * Send a command to the Target requesting input state of GPIO pins. + */ +A_STATUS wmi_gpio_input_get(struct wmi_t *wmip); + +/* + * Send a command to the Target to change the value of a GPIO register. + */ +A_STATUS wmi_gpio_register_set(struct wmi_t *wmip, + A_UINT32 gpioreg_id, + A_UINT32 value); + +/* + * Send a command to the Target to fetch the value of a GPIO register. + */ +A_STATUS wmi_gpio_register_get(struct wmi_t *wmip, A_UINT32 gpioreg_id); + +/* + * Send a command to the Target, acknowledging some GPIO interrupts. + */ +A_STATUS wmi_gpio_intr_ack(struct wmi_t *wmip, A_UINT32 ack_mask); + +#endif /* _GPIO_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/gpio_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/gpio_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/gpio_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/gpio_reg.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,1000 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _GPIO_REG_REG_H_ +#define _GPIO_REG_REG_H_ + +#define GPIO_OUT_ADDRESS 0x00000000 +#define GPIO_OUT_OFFSET 0x00000000 +#define GPIO_OUT_DATA_MSB 17 +#define GPIO_OUT_DATA_LSB 0 +#define GPIO_OUT_DATA_MASK 0x0003ffff +#define GPIO_OUT_DATA_GET(x) (((x) & GPIO_OUT_DATA_MASK) >> GPIO_OUT_DATA_LSB) +#define GPIO_OUT_DATA_SET(x) (((x) << GPIO_OUT_DATA_LSB) & GPIO_OUT_DATA_MASK) + +#define GPIO_OUT_W1TS_ADDRESS 0x00000004 +#define GPIO_OUT_W1TS_OFFSET 0x00000004 +#define GPIO_OUT_W1TS_DATA_MSB 17 +#define GPIO_OUT_W1TS_DATA_LSB 0 +#define GPIO_OUT_W1TS_DATA_MASK 0x0003ffff +#define GPIO_OUT_W1TS_DATA_GET(x) (((x) & GPIO_OUT_W1TS_DATA_MASK) >> GPIO_OUT_W1TS_DATA_LSB) +#define GPIO_OUT_W1TS_DATA_SET(x) (((x) << GPIO_OUT_W1TS_DATA_LSB) & GPIO_OUT_W1TS_DATA_MASK) + +#define GPIO_OUT_W1TC_ADDRESS 0x00000008 +#define GPIO_OUT_W1TC_OFFSET 0x00000008 +#define GPIO_OUT_W1TC_DATA_MSB 17 +#define GPIO_OUT_W1TC_DATA_LSB 0 +#define GPIO_OUT_W1TC_DATA_MASK 0x0003ffff +#define GPIO_OUT_W1TC_DATA_GET(x) (((x) & GPIO_OUT_W1TC_DATA_MASK) >> GPIO_OUT_W1TC_DATA_LSB) +#define GPIO_OUT_W1TC_DATA_SET(x) (((x) << GPIO_OUT_W1TC_DATA_LSB) & GPIO_OUT_W1TC_DATA_MASK) + +#define GPIO_ENABLE_ADDRESS 0x0000000c +#define GPIO_ENABLE_OFFSET 0x0000000c +#define GPIO_ENABLE_DATA_MSB 17 +#define GPIO_ENABLE_DATA_LSB 0 +#define GPIO_ENABLE_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_DATA_GET(x) (((x) & GPIO_ENABLE_DATA_MASK) >> GPIO_ENABLE_DATA_LSB) +#define GPIO_ENABLE_DATA_SET(x) (((x) << GPIO_ENABLE_DATA_LSB) & GPIO_ENABLE_DATA_MASK) + +#define GPIO_ENABLE_W1TS_ADDRESS 0x00000010 +#define GPIO_ENABLE_W1TS_OFFSET 0x00000010 +#define GPIO_ENABLE_W1TS_DATA_MSB 17 +#define GPIO_ENABLE_W1TS_DATA_LSB 0 +#define GPIO_ENABLE_W1TS_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_W1TS_DATA_GET(x) (((x) & GPIO_ENABLE_W1TS_DATA_MASK) >> GPIO_ENABLE_W1TS_DATA_LSB) +#define GPIO_ENABLE_W1TS_DATA_SET(x) (((x) << GPIO_ENABLE_W1TS_DATA_LSB) & GPIO_ENABLE_W1TS_DATA_MASK) + +#define GPIO_ENABLE_W1TC_ADDRESS 0x00000014 +#define GPIO_ENABLE_W1TC_OFFSET 0x00000014 +#define GPIO_ENABLE_W1TC_DATA_MSB 17 +#define GPIO_ENABLE_W1TC_DATA_LSB 0 +#define GPIO_ENABLE_W1TC_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_W1TC_DATA_GET(x) (((x) & GPIO_ENABLE_W1TC_DATA_MASK) >> GPIO_ENABLE_W1TC_DATA_LSB) +#define GPIO_ENABLE_W1TC_DATA_SET(x) (((x) << GPIO_ENABLE_W1TC_DATA_LSB) & GPIO_ENABLE_W1TC_DATA_MASK) + +#define GPIO_IN_ADDRESS 0x00000018 +#define GPIO_IN_OFFSET 0x00000018 +#define GPIO_IN_DATA_MSB 17 +#define GPIO_IN_DATA_LSB 0 +#define GPIO_IN_DATA_MASK 0x0003ffff +#define GPIO_IN_DATA_GET(x) (((x) & GPIO_IN_DATA_MASK) >> GPIO_IN_DATA_LSB) +#define GPIO_IN_DATA_SET(x) (((x) << GPIO_IN_DATA_LSB) & GPIO_IN_DATA_MASK) + +#define GPIO_STATUS_ADDRESS 0x0000001c +#define GPIO_STATUS_OFFSET 0x0000001c +#define GPIO_STATUS_INTERRUPT_MSB 17 +#define GPIO_STATUS_INTERRUPT_LSB 0 +#define GPIO_STATUS_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_INTERRUPT_MASK) >> GPIO_STATUS_INTERRUPT_LSB) +#define GPIO_STATUS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_INTERRUPT_LSB) & GPIO_STATUS_INTERRUPT_MASK) + +#define GPIO_STATUS_W1TS_ADDRESS 0x00000020 +#define GPIO_STATUS_W1TS_OFFSET 0x00000020 +#define GPIO_STATUS_W1TS_INTERRUPT_MSB 17 +#define GPIO_STATUS_W1TS_INTERRUPT_LSB 0 +#define GPIO_STATUS_W1TS_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_W1TS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TS_INTERRUPT_MASK) >> GPIO_STATUS_W1TS_INTERRUPT_LSB) +#define GPIO_STATUS_W1TS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TS_INTERRUPT_LSB) & GPIO_STATUS_W1TS_INTERRUPT_MASK) + +#define GPIO_STATUS_W1TC_ADDRESS 0x00000024 +#define GPIO_STATUS_W1TC_OFFSET 0x00000024 +#define GPIO_STATUS_W1TC_INTERRUPT_MSB 17 +#define GPIO_STATUS_W1TC_INTERRUPT_LSB 0 +#define GPIO_STATUS_W1TC_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_W1TC_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TC_INTERRUPT_MASK) >> GPIO_STATUS_W1TC_INTERRUPT_LSB) +#define GPIO_STATUS_W1TC_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TC_INTERRUPT_LSB) & GPIO_STATUS_W1TC_INTERRUPT_MASK) + +#define GPIO_PIN0_ADDRESS 0x00000028 +#define GPIO_PIN0_OFFSET 0x00000028 +#define GPIO_PIN0_CONFIG_MSB 12 +#define GPIO_PIN0_CONFIG_LSB 11 +#define GPIO_PIN0_CONFIG_MASK 0x00001800 +#define GPIO_PIN0_CONFIG_GET(x) (((x) & GPIO_PIN0_CONFIG_MASK) >> GPIO_PIN0_CONFIG_LSB) +#define GPIO_PIN0_CONFIG_SET(x) (((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK) +#define GPIO_PIN0_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN0_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN0_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN0_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN0_WAKEUP_ENABLE_MASK) >> GPIO_PIN0_WAKEUP_ENABLE_LSB) +#define GPIO_PIN0_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN0_WAKEUP_ENABLE_LSB) & GPIO_PIN0_WAKEUP_ENABLE_MASK) +#define GPIO_PIN0_INT_TYPE_MSB 9 +#define GPIO_PIN0_INT_TYPE_LSB 7 +#define GPIO_PIN0_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN0_INT_TYPE_GET(x) (((x) & GPIO_PIN0_INT_TYPE_MASK) >> GPIO_PIN0_INT_TYPE_LSB) +#define GPIO_PIN0_INT_TYPE_SET(x) (((x) << GPIO_PIN0_INT_TYPE_LSB) & GPIO_PIN0_INT_TYPE_MASK) +#define GPIO_PIN0_PAD_DRIVER_MSB 2 +#define GPIO_PIN0_PAD_DRIVER_LSB 2 +#define GPIO_PIN0_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN0_PAD_DRIVER_GET(x) (((x) & GPIO_PIN0_PAD_DRIVER_MASK) >> GPIO_PIN0_PAD_DRIVER_LSB) +#define GPIO_PIN0_PAD_DRIVER_SET(x) (((x) << GPIO_PIN0_PAD_DRIVER_LSB) & GPIO_PIN0_PAD_DRIVER_MASK) +#define GPIO_PIN0_SOURCE_MSB 0 +#define GPIO_PIN0_SOURCE_LSB 0 +#define GPIO_PIN0_SOURCE_MASK 0x00000001 +#define GPIO_PIN0_SOURCE_GET(x) (((x) & GPIO_PIN0_SOURCE_MASK) >> GPIO_PIN0_SOURCE_LSB) +#define GPIO_PIN0_SOURCE_SET(x) (((x) << GPIO_PIN0_SOURCE_LSB) & GPIO_PIN0_SOURCE_MASK) + +#define GPIO_PIN1_ADDRESS 0x0000002c +#define GPIO_PIN1_OFFSET 0x0000002c +#define GPIO_PIN1_CONFIG_MSB 12 +#define GPIO_PIN1_CONFIG_LSB 11 +#define GPIO_PIN1_CONFIG_MASK 0x00001800 +#define GPIO_PIN1_CONFIG_GET(x) (((x) & GPIO_PIN1_CONFIG_MASK) >> GPIO_PIN1_CONFIG_LSB) +#define GPIO_PIN1_CONFIG_SET(x) (((x) << GPIO_PIN1_CONFIG_LSB) & GPIO_PIN1_CONFIG_MASK) +#define GPIO_PIN1_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN1_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN1_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN1_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN1_WAKEUP_ENABLE_MASK) >> GPIO_PIN1_WAKEUP_ENABLE_LSB) +#define GPIO_PIN1_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN1_WAKEUP_ENABLE_LSB) & GPIO_PIN1_WAKEUP_ENABLE_MASK) +#define GPIO_PIN1_INT_TYPE_MSB 9 +#define GPIO_PIN1_INT_TYPE_LSB 7 +#define GPIO_PIN1_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN1_INT_TYPE_GET(x) (((x) & GPIO_PIN1_INT_TYPE_MASK) >> GPIO_PIN1_INT_TYPE_LSB) +#define GPIO_PIN1_INT_TYPE_SET(x) (((x) << GPIO_PIN1_INT_TYPE_LSB) & GPIO_PIN1_INT_TYPE_MASK) +#define GPIO_PIN1_PAD_DRIVER_MSB 2 +#define GPIO_PIN1_PAD_DRIVER_LSB 2 +#define GPIO_PIN1_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN1_PAD_DRIVER_GET(x) (((x) & GPIO_PIN1_PAD_DRIVER_MASK) >> GPIO_PIN1_PAD_DRIVER_LSB) +#define GPIO_PIN1_PAD_DRIVER_SET(x) (((x) << GPIO_PIN1_PAD_DRIVER_LSB) & GPIO_PIN1_PAD_DRIVER_MASK) +#define GPIO_PIN1_SOURCE_MSB 0 +#define GPIO_PIN1_SOURCE_LSB 0 +#define GPIO_PIN1_SOURCE_MASK 0x00000001 +#define GPIO_PIN1_SOURCE_GET(x) (((x) & GPIO_PIN1_SOURCE_MASK) >> GPIO_PIN1_SOURCE_LSB) +#define GPIO_PIN1_SOURCE_SET(x) (((x) << GPIO_PIN1_SOURCE_LSB) & GPIO_PIN1_SOURCE_MASK) + +#define GPIO_PIN2_ADDRESS 0x00000030 +#define GPIO_PIN2_OFFSET 0x00000030 +#define GPIO_PIN2_CONFIG_MSB 12 +#define GPIO_PIN2_CONFIG_LSB 11 +#define GPIO_PIN2_CONFIG_MASK 0x00001800 +#define GPIO_PIN2_CONFIG_GET(x) (((x) & GPIO_PIN2_CONFIG_MASK) >> GPIO_PIN2_CONFIG_LSB) +#define GPIO_PIN2_CONFIG_SET(x) (((x) << GPIO_PIN2_CONFIG_LSB) & GPIO_PIN2_CONFIG_MASK) +#define GPIO_PIN2_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN2_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN2_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN2_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN2_WAKEUP_ENABLE_MASK) >> GPIO_PIN2_WAKEUP_ENABLE_LSB) +#define GPIO_PIN2_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN2_WAKEUP_ENABLE_LSB) & GPIO_PIN2_WAKEUP_ENABLE_MASK) +#define GPIO_PIN2_INT_TYPE_MSB 9 +#define GPIO_PIN2_INT_TYPE_LSB 7 +#define GPIO_PIN2_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN2_INT_TYPE_GET(x) (((x) & GPIO_PIN2_INT_TYPE_MASK) >> GPIO_PIN2_INT_TYPE_LSB) +#define GPIO_PIN2_INT_TYPE_SET(x) (((x) << GPIO_PIN2_INT_TYPE_LSB) & GPIO_PIN2_INT_TYPE_MASK) +#define GPIO_PIN2_PAD_DRIVER_MSB 2 +#define GPIO_PIN2_PAD_DRIVER_LSB 2 +#define GPIO_PIN2_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN2_PAD_DRIVER_GET(x) (((x) & GPIO_PIN2_PAD_DRIVER_MASK) >> GPIO_PIN2_PAD_DRIVER_LSB) +#define GPIO_PIN2_PAD_DRIVER_SET(x) (((x) << GPIO_PIN2_PAD_DRIVER_LSB) & GPIO_PIN2_PAD_DRIVER_MASK) +#define GPIO_PIN2_SOURCE_MSB 0 +#define GPIO_PIN2_SOURCE_LSB 0 +#define GPIO_PIN2_SOURCE_MASK 0x00000001 +#define GPIO_PIN2_SOURCE_GET(x) (((x) & GPIO_PIN2_SOURCE_MASK) >> GPIO_PIN2_SOURCE_LSB) +#define GPIO_PIN2_SOURCE_SET(x) (((x) << GPIO_PIN2_SOURCE_LSB) & GPIO_PIN2_SOURCE_MASK) + +#define GPIO_PIN3_ADDRESS 0x00000034 +#define GPIO_PIN3_OFFSET 0x00000034 +#define GPIO_PIN3_CONFIG_MSB 12 +#define GPIO_PIN3_CONFIG_LSB 11 +#define GPIO_PIN3_CONFIG_MASK 0x00001800 +#define GPIO_PIN3_CONFIG_GET(x) (((x) & GPIO_PIN3_CONFIG_MASK) >> GPIO_PIN3_CONFIG_LSB) +#define GPIO_PIN3_CONFIG_SET(x) (((x) << GPIO_PIN3_CONFIG_LSB) & GPIO_PIN3_CONFIG_MASK) +#define GPIO_PIN3_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN3_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN3_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN3_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN3_WAKEUP_ENABLE_MASK) >> GPIO_PIN3_WAKEUP_ENABLE_LSB) +#define GPIO_PIN3_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN3_WAKEUP_ENABLE_LSB) & GPIO_PIN3_WAKEUP_ENABLE_MASK) +#define GPIO_PIN3_INT_TYPE_MSB 9 +#define GPIO_PIN3_INT_TYPE_LSB 7 +#define GPIO_PIN3_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN3_INT_TYPE_GET(x) (((x) & GPIO_PIN3_INT_TYPE_MASK) >> GPIO_PIN3_INT_TYPE_LSB) +#define GPIO_PIN3_INT_TYPE_SET(x) (((x) << GPIO_PIN3_INT_TYPE_LSB) & GPIO_PIN3_INT_TYPE_MASK) +#define GPIO_PIN3_PAD_DRIVER_MSB 2 +#define GPIO_PIN3_PAD_DRIVER_LSB 2 +#define GPIO_PIN3_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN3_PAD_DRIVER_GET(x) (((x) & GPIO_PIN3_PAD_DRIVER_MASK) >> GPIO_PIN3_PAD_DRIVER_LSB) +#define GPIO_PIN3_PAD_DRIVER_SET(x) (((x) << GPIO_PIN3_PAD_DRIVER_LSB) & GPIO_PIN3_PAD_DRIVER_MASK) +#define GPIO_PIN3_SOURCE_MSB 0 +#define GPIO_PIN3_SOURCE_LSB 0 +#define GPIO_PIN3_SOURCE_MASK 0x00000001 +#define GPIO_PIN3_SOURCE_GET(x) (((x) & GPIO_PIN3_SOURCE_MASK) >> GPIO_PIN3_SOURCE_LSB) +#define GPIO_PIN3_SOURCE_SET(x) (((x) << GPIO_PIN3_SOURCE_LSB) & GPIO_PIN3_SOURCE_MASK) + +#define GPIO_PIN4_ADDRESS 0x00000038 +#define GPIO_PIN4_OFFSET 0x00000038 +#define GPIO_PIN4_CONFIG_MSB 12 +#define GPIO_PIN4_CONFIG_LSB 11 +#define GPIO_PIN4_CONFIG_MASK 0x00001800 +#define GPIO_PIN4_CONFIG_GET(x) (((x) & GPIO_PIN4_CONFIG_MASK) >> GPIO_PIN4_CONFIG_LSB) +#define GPIO_PIN4_CONFIG_SET(x) (((x) << GPIO_PIN4_CONFIG_LSB) & GPIO_PIN4_CONFIG_MASK) +#define GPIO_PIN4_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN4_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN4_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN4_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN4_WAKEUP_ENABLE_MASK) >> GPIO_PIN4_WAKEUP_ENABLE_LSB) +#define GPIO_PIN4_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN4_WAKEUP_ENABLE_LSB) & GPIO_PIN4_WAKEUP_ENABLE_MASK) +#define GPIO_PIN4_INT_TYPE_MSB 9 +#define GPIO_PIN4_INT_TYPE_LSB 7 +#define GPIO_PIN4_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN4_INT_TYPE_GET(x) (((x) & GPIO_PIN4_INT_TYPE_MASK) >> GPIO_PIN4_INT_TYPE_LSB) +#define GPIO_PIN4_INT_TYPE_SET(x) (((x) << GPIO_PIN4_INT_TYPE_LSB) & GPIO_PIN4_INT_TYPE_MASK) +#define GPIO_PIN4_PAD_DRIVER_MSB 2 +#define GPIO_PIN4_PAD_DRIVER_LSB 2 +#define GPIO_PIN4_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN4_PAD_DRIVER_GET(x) (((x) & GPIO_PIN4_PAD_DRIVER_MASK) >> GPIO_PIN4_PAD_DRIVER_LSB) +#define GPIO_PIN4_PAD_DRIVER_SET(x) (((x) << GPIO_PIN4_PAD_DRIVER_LSB) & GPIO_PIN4_PAD_DRIVER_MASK) +#define GPIO_PIN4_SOURCE_MSB 0 +#define GPIO_PIN4_SOURCE_LSB 0 +#define GPIO_PIN4_SOURCE_MASK 0x00000001 +#define GPIO_PIN4_SOURCE_GET(x) (((x) & GPIO_PIN4_SOURCE_MASK) >> GPIO_PIN4_SOURCE_LSB) +#define GPIO_PIN4_SOURCE_SET(x) (((x) << GPIO_PIN4_SOURCE_LSB) & GPIO_PIN4_SOURCE_MASK) + +#define GPIO_PIN5_ADDRESS 0x0000003c +#define GPIO_PIN5_OFFSET 0x0000003c +#define GPIO_PIN5_CONFIG_MSB 12 +#define GPIO_PIN5_CONFIG_LSB 11 +#define GPIO_PIN5_CONFIG_MASK 0x00001800 +#define GPIO_PIN5_CONFIG_GET(x) (((x) & GPIO_PIN5_CONFIG_MASK) >> GPIO_PIN5_CONFIG_LSB) +#define GPIO_PIN5_CONFIG_SET(x) (((x) << GPIO_PIN5_CONFIG_LSB) & GPIO_PIN5_CONFIG_MASK) +#define GPIO_PIN5_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN5_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN5_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN5_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN5_WAKEUP_ENABLE_MASK) >> GPIO_PIN5_WAKEUP_ENABLE_LSB) +#define GPIO_PIN5_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN5_WAKEUP_ENABLE_LSB) & GPIO_PIN5_WAKEUP_ENABLE_MASK) +#define GPIO_PIN5_INT_TYPE_MSB 9 +#define GPIO_PIN5_INT_TYPE_LSB 7 +#define GPIO_PIN5_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN5_INT_TYPE_GET(x) (((x) & GPIO_PIN5_INT_TYPE_MASK) >> GPIO_PIN5_INT_TYPE_LSB) +#define GPIO_PIN5_INT_TYPE_SET(x) (((x) << GPIO_PIN5_INT_TYPE_LSB) & GPIO_PIN5_INT_TYPE_MASK) +#define GPIO_PIN5_PAD_DRIVER_MSB 2 +#define GPIO_PIN5_PAD_DRIVER_LSB 2 +#define GPIO_PIN5_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN5_PAD_DRIVER_GET(x) (((x) & GPIO_PIN5_PAD_DRIVER_MASK) >> GPIO_PIN5_PAD_DRIVER_LSB) +#define GPIO_PIN5_PAD_DRIVER_SET(x) (((x) << GPIO_PIN5_PAD_DRIVER_LSB) & GPIO_PIN5_PAD_DRIVER_MASK) +#define GPIO_PIN5_SOURCE_MSB 0 +#define GPIO_PIN5_SOURCE_LSB 0 +#define GPIO_PIN5_SOURCE_MASK 0x00000001 +#define GPIO_PIN5_SOURCE_GET(x) (((x) & GPIO_PIN5_SOURCE_MASK) >> GPIO_PIN5_SOURCE_LSB) +#define GPIO_PIN5_SOURCE_SET(x) (((x) << GPIO_PIN5_SOURCE_LSB) & GPIO_PIN5_SOURCE_MASK) + +#define GPIO_PIN6_ADDRESS 0x00000040 +#define GPIO_PIN6_OFFSET 0x00000040 +#define GPIO_PIN6_CONFIG_MSB 12 +#define GPIO_PIN6_CONFIG_LSB 11 +#define GPIO_PIN6_CONFIG_MASK 0x00001800 +#define GPIO_PIN6_CONFIG_GET(x) (((x) & GPIO_PIN6_CONFIG_MASK) >> GPIO_PIN6_CONFIG_LSB) +#define GPIO_PIN6_CONFIG_SET(x) (((x) << GPIO_PIN6_CONFIG_LSB) & GPIO_PIN6_CONFIG_MASK) +#define GPIO_PIN6_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN6_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN6_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN6_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN6_WAKEUP_ENABLE_MASK) >> GPIO_PIN6_WAKEUP_ENABLE_LSB) +#define GPIO_PIN6_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN6_WAKEUP_ENABLE_LSB) & GPIO_PIN6_WAKEUP_ENABLE_MASK) +#define GPIO_PIN6_INT_TYPE_MSB 9 +#define GPIO_PIN6_INT_TYPE_LSB 7 +#define GPIO_PIN6_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN6_INT_TYPE_GET(x) (((x) & GPIO_PIN6_INT_TYPE_MASK) >> GPIO_PIN6_INT_TYPE_LSB) +#define GPIO_PIN6_INT_TYPE_SET(x) (((x) << GPIO_PIN6_INT_TYPE_LSB) & GPIO_PIN6_INT_TYPE_MASK) +#define GPIO_PIN6_PAD_DRIVER_MSB 2 +#define GPIO_PIN6_PAD_DRIVER_LSB 2 +#define GPIO_PIN6_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN6_PAD_DRIVER_GET(x) (((x) & GPIO_PIN6_PAD_DRIVER_MASK) >> GPIO_PIN6_PAD_DRIVER_LSB) +#define GPIO_PIN6_PAD_DRIVER_SET(x) (((x) << GPIO_PIN6_PAD_DRIVER_LSB) & GPIO_PIN6_PAD_DRIVER_MASK) +#define GPIO_PIN6_SOURCE_MSB 0 +#define GPIO_PIN6_SOURCE_LSB 0 +#define GPIO_PIN6_SOURCE_MASK 0x00000001 +#define GPIO_PIN6_SOURCE_GET(x) (((x) & GPIO_PIN6_SOURCE_MASK) >> GPIO_PIN6_SOURCE_LSB) +#define GPIO_PIN6_SOURCE_SET(x) (((x) << GPIO_PIN6_SOURCE_LSB) & GPIO_PIN6_SOURCE_MASK) + +#define GPIO_PIN7_ADDRESS 0x00000044 +#define GPIO_PIN7_OFFSET 0x00000044 +#define GPIO_PIN7_CONFIG_MSB 12 +#define GPIO_PIN7_CONFIG_LSB 11 +#define GPIO_PIN7_CONFIG_MASK 0x00001800 +#define GPIO_PIN7_CONFIG_GET(x) (((x) & GPIO_PIN7_CONFIG_MASK) >> GPIO_PIN7_CONFIG_LSB) +#define GPIO_PIN7_CONFIG_SET(x) (((x) << GPIO_PIN7_CONFIG_LSB) & GPIO_PIN7_CONFIG_MASK) +#define GPIO_PIN7_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN7_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN7_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN7_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN7_WAKEUP_ENABLE_MASK) >> GPIO_PIN7_WAKEUP_ENABLE_LSB) +#define GPIO_PIN7_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN7_WAKEUP_ENABLE_LSB) & GPIO_PIN7_WAKEUP_ENABLE_MASK) +#define GPIO_PIN7_INT_TYPE_MSB 9 +#define GPIO_PIN7_INT_TYPE_LSB 7 +#define GPIO_PIN7_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN7_INT_TYPE_GET(x) (((x) & GPIO_PIN7_INT_TYPE_MASK) >> GPIO_PIN7_INT_TYPE_LSB) +#define GPIO_PIN7_INT_TYPE_SET(x) (((x) << GPIO_PIN7_INT_TYPE_LSB) & GPIO_PIN7_INT_TYPE_MASK) +#define GPIO_PIN7_PAD_DRIVER_MSB 2 +#define GPIO_PIN7_PAD_DRIVER_LSB 2 +#define GPIO_PIN7_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN7_PAD_DRIVER_GET(x) (((x) & GPIO_PIN7_PAD_DRIVER_MASK) >> GPIO_PIN7_PAD_DRIVER_LSB) +#define GPIO_PIN7_PAD_DRIVER_SET(x) (((x) << GPIO_PIN7_PAD_DRIVER_LSB) & GPIO_PIN7_PAD_DRIVER_MASK) +#define GPIO_PIN7_SOURCE_MSB 0 +#define GPIO_PIN7_SOURCE_LSB 0 +#define GPIO_PIN7_SOURCE_MASK 0x00000001 +#define GPIO_PIN7_SOURCE_GET(x) (((x) & GPIO_PIN7_SOURCE_MASK) >> GPIO_PIN7_SOURCE_LSB) +#define GPIO_PIN7_SOURCE_SET(x) (((x) << GPIO_PIN7_SOURCE_LSB) & GPIO_PIN7_SOURCE_MASK) + +#define GPIO_PIN8_ADDRESS 0x00000048 +#define GPIO_PIN8_OFFSET 0x00000048 +#define GPIO_PIN8_CONFIG_MSB 12 +#define GPIO_PIN8_CONFIG_LSB 11 +#define GPIO_PIN8_CONFIG_MASK 0x00001800 +#define GPIO_PIN8_CONFIG_GET(x) (((x) & GPIO_PIN8_CONFIG_MASK) >> GPIO_PIN8_CONFIG_LSB) +#define GPIO_PIN8_CONFIG_SET(x) (((x) << GPIO_PIN8_CONFIG_LSB) & GPIO_PIN8_CONFIG_MASK) +#define GPIO_PIN8_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN8_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN8_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN8_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN8_WAKEUP_ENABLE_MASK) >> GPIO_PIN8_WAKEUP_ENABLE_LSB) +#define GPIO_PIN8_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN8_WAKEUP_ENABLE_LSB) & GPIO_PIN8_WAKEUP_ENABLE_MASK) +#define GPIO_PIN8_INT_TYPE_MSB 9 +#define GPIO_PIN8_INT_TYPE_LSB 7 +#define GPIO_PIN8_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN8_INT_TYPE_GET(x) (((x) & GPIO_PIN8_INT_TYPE_MASK) >> GPIO_PIN8_INT_TYPE_LSB) +#define GPIO_PIN8_INT_TYPE_SET(x) (((x) << GPIO_PIN8_INT_TYPE_LSB) & GPIO_PIN8_INT_TYPE_MASK) +#define GPIO_PIN8_PAD_DRIVER_MSB 2 +#define GPIO_PIN8_PAD_DRIVER_LSB 2 +#define GPIO_PIN8_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN8_PAD_DRIVER_GET(x) (((x) & GPIO_PIN8_PAD_DRIVER_MASK) >> GPIO_PIN8_PAD_DRIVER_LSB) +#define GPIO_PIN8_PAD_DRIVER_SET(x) (((x) << GPIO_PIN8_PAD_DRIVER_LSB) & GPIO_PIN8_PAD_DRIVER_MASK) +#define GPIO_PIN8_SOURCE_MSB 0 +#define GPIO_PIN8_SOURCE_LSB 0 +#define GPIO_PIN8_SOURCE_MASK 0x00000001 +#define GPIO_PIN8_SOURCE_GET(x) (((x) & GPIO_PIN8_SOURCE_MASK) >> GPIO_PIN8_SOURCE_LSB) +#define GPIO_PIN8_SOURCE_SET(x) (((x) << GPIO_PIN8_SOURCE_LSB) & GPIO_PIN8_SOURCE_MASK) + +#define GPIO_PIN9_ADDRESS 0x0000004c +#define GPIO_PIN9_OFFSET 0x0000004c +#define GPIO_PIN9_CONFIG_MSB 12 +#define GPIO_PIN9_CONFIG_LSB 11 +#define GPIO_PIN9_CONFIG_MASK 0x00001800 +#define GPIO_PIN9_CONFIG_GET(x) (((x) & GPIO_PIN9_CONFIG_MASK) >> GPIO_PIN9_CONFIG_LSB) +#define GPIO_PIN9_CONFIG_SET(x) (((x) << GPIO_PIN9_CONFIG_LSB) & GPIO_PIN9_CONFIG_MASK) +#define GPIO_PIN9_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN9_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN9_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN9_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN9_WAKEUP_ENABLE_MASK) >> GPIO_PIN9_WAKEUP_ENABLE_LSB) +#define GPIO_PIN9_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN9_WAKEUP_ENABLE_LSB) & GPIO_PIN9_WAKEUP_ENABLE_MASK) +#define GPIO_PIN9_INT_TYPE_MSB 9 +#define GPIO_PIN9_INT_TYPE_LSB 7 +#define GPIO_PIN9_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN9_INT_TYPE_GET(x) (((x) & GPIO_PIN9_INT_TYPE_MASK) >> GPIO_PIN9_INT_TYPE_LSB) +#define GPIO_PIN9_INT_TYPE_SET(x) (((x) << GPIO_PIN9_INT_TYPE_LSB) & GPIO_PIN9_INT_TYPE_MASK) +#define GPIO_PIN9_PAD_DRIVER_MSB 2 +#define GPIO_PIN9_PAD_DRIVER_LSB 2 +#define GPIO_PIN9_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN9_PAD_DRIVER_GET(x) (((x) & GPIO_PIN9_PAD_DRIVER_MASK) >> GPIO_PIN9_PAD_DRIVER_LSB) +#define GPIO_PIN9_PAD_DRIVER_SET(x) (((x) << GPIO_PIN9_PAD_DRIVER_LSB) & GPIO_PIN9_PAD_DRIVER_MASK) +#define GPIO_PIN9_SOURCE_MSB 0 +#define GPIO_PIN9_SOURCE_LSB 0 +#define GPIO_PIN9_SOURCE_MASK 0x00000001 +#define GPIO_PIN9_SOURCE_GET(x) (((x) & GPIO_PIN9_SOURCE_MASK) >> GPIO_PIN9_SOURCE_LSB) +#define GPIO_PIN9_SOURCE_SET(x) (((x) << GPIO_PIN9_SOURCE_LSB) & GPIO_PIN9_SOURCE_MASK) + +#define GPIO_PIN10_ADDRESS 0x00000050 +#define GPIO_PIN10_OFFSET 0x00000050 +#define GPIO_PIN10_CONFIG_MSB 12 +#define GPIO_PIN10_CONFIG_LSB 11 +#define GPIO_PIN10_CONFIG_MASK 0x00001800 +#define GPIO_PIN10_CONFIG_GET(x) (((x) & GPIO_PIN10_CONFIG_MASK) >> GPIO_PIN10_CONFIG_LSB) +#define GPIO_PIN10_CONFIG_SET(x) (((x) << GPIO_PIN10_CONFIG_LSB) & GPIO_PIN10_CONFIG_MASK) +#define GPIO_PIN10_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN10_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN10_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN10_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN10_WAKEUP_ENABLE_MASK) >> GPIO_PIN10_WAKEUP_ENABLE_LSB) +#define GPIO_PIN10_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN10_WAKEUP_ENABLE_LSB) & GPIO_PIN10_WAKEUP_ENABLE_MASK) +#define GPIO_PIN10_INT_TYPE_MSB 9 +#define GPIO_PIN10_INT_TYPE_LSB 7 +#define GPIO_PIN10_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN10_INT_TYPE_GET(x) (((x) & GPIO_PIN10_INT_TYPE_MASK) >> GPIO_PIN10_INT_TYPE_LSB) +#define GPIO_PIN10_INT_TYPE_SET(x) (((x) << GPIO_PIN10_INT_TYPE_LSB) & GPIO_PIN10_INT_TYPE_MASK) +#define GPIO_PIN10_PAD_DRIVER_MSB 2 +#define GPIO_PIN10_PAD_DRIVER_LSB 2 +#define GPIO_PIN10_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN10_PAD_DRIVER_GET(x) (((x) & GPIO_PIN10_PAD_DRIVER_MASK) >> GPIO_PIN10_PAD_DRIVER_LSB) +#define GPIO_PIN10_PAD_DRIVER_SET(x) (((x) << GPIO_PIN10_PAD_DRIVER_LSB) & GPIO_PIN10_PAD_DRIVER_MASK) +#define GPIO_PIN10_SOURCE_MSB 0 +#define GPIO_PIN10_SOURCE_LSB 0 +#define GPIO_PIN10_SOURCE_MASK 0x00000001 +#define GPIO_PIN10_SOURCE_GET(x) (((x) & GPIO_PIN10_SOURCE_MASK) >> GPIO_PIN10_SOURCE_LSB) +#define GPIO_PIN10_SOURCE_SET(x) (((x) << GPIO_PIN10_SOURCE_LSB) & GPIO_PIN10_SOURCE_MASK) + +#define GPIO_PIN11_ADDRESS 0x00000054 +#define GPIO_PIN11_OFFSET 0x00000054 +#define GPIO_PIN11_CONFIG_MSB 12 +#define GPIO_PIN11_CONFIG_LSB 11 +#define GPIO_PIN11_CONFIG_MASK 0x00001800 +#define GPIO_PIN11_CONFIG_GET(x) (((x) & GPIO_PIN11_CONFIG_MASK) >> GPIO_PIN11_CONFIG_LSB) +#define GPIO_PIN11_CONFIG_SET(x) (((x) << GPIO_PIN11_CONFIG_LSB) & GPIO_PIN11_CONFIG_MASK) +#define GPIO_PIN11_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN11_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN11_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN11_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN11_WAKEUP_ENABLE_MASK) >> GPIO_PIN11_WAKEUP_ENABLE_LSB) +#define GPIO_PIN11_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN11_WAKEUP_ENABLE_LSB) & GPIO_PIN11_WAKEUP_ENABLE_MASK) +#define GPIO_PIN11_INT_TYPE_MSB 9 +#define GPIO_PIN11_INT_TYPE_LSB 7 +#define GPIO_PIN11_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN11_INT_TYPE_GET(x) (((x) & GPIO_PIN11_INT_TYPE_MASK) >> GPIO_PIN11_INT_TYPE_LSB) +#define GPIO_PIN11_INT_TYPE_SET(x) (((x) << GPIO_PIN11_INT_TYPE_LSB) & GPIO_PIN11_INT_TYPE_MASK) +#define GPIO_PIN11_PAD_DRIVER_MSB 2 +#define GPIO_PIN11_PAD_DRIVER_LSB 2 +#define GPIO_PIN11_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN11_PAD_DRIVER_GET(x) (((x) & GPIO_PIN11_PAD_DRIVER_MASK) >> GPIO_PIN11_PAD_DRIVER_LSB) +#define GPIO_PIN11_PAD_DRIVER_SET(x) (((x) << GPIO_PIN11_PAD_DRIVER_LSB) & GPIO_PIN11_PAD_DRIVER_MASK) +#define GPIO_PIN11_SOURCE_MSB 0 +#define GPIO_PIN11_SOURCE_LSB 0 +#define GPIO_PIN11_SOURCE_MASK 0x00000001 +#define GPIO_PIN11_SOURCE_GET(x) (((x) & GPIO_PIN11_SOURCE_MASK) >> GPIO_PIN11_SOURCE_LSB) +#define GPIO_PIN11_SOURCE_SET(x) (((x) << GPIO_PIN11_SOURCE_LSB) & GPIO_PIN11_SOURCE_MASK) + +#define GPIO_PIN12_ADDRESS 0x00000058 +#define GPIO_PIN12_OFFSET 0x00000058 +#define GPIO_PIN12_CONFIG_MSB 12 +#define GPIO_PIN12_CONFIG_LSB 11 +#define GPIO_PIN12_CONFIG_MASK 0x00001800 +#define GPIO_PIN12_CONFIG_GET(x) (((x) & GPIO_PIN12_CONFIG_MASK) >> GPIO_PIN12_CONFIG_LSB) +#define GPIO_PIN12_CONFIG_SET(x) (((x) << GPIO_PIN12_CONFIG_LSB) & GPIO_PIN12_CONFIG_MASK) +#define GPIO_PIN12_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN12_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN12_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN12_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN12_WAKEUP_ENABLE_MASK) >> GPIO_PIN12_WAKEUP_ENABLE_LSB) +#define GPIO_PIN12_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN12_WAKEUP_ENABLE_LSB) & GPIO_PIN12_WAKEUP_ENABLE_MASK) +#define GPIO_PIN12_INT_TYPE_MSB 9 +#define GPIO_PIN12_INT_TYPE_LSB 7 +#define GPIO_PIN12_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN12_INT_TYPE_GET(x) (((x) & GPIO_PIN12_INT_TYPE_MASK) >> GPIO_PIN12_INT_TYPE_LSB) +#define GPIO_PIN12_INT_TYPE_SET(x) (((x) << GPIO_PIN12_INT_TYPE_LSB) & GPIO_PIN12_INT_TYPE_MASK) +#define GPIO_PIN12_PAD_DRIVER_MSB 2 +#define GPIO_PIN12_PAD_DRIVER_LSB 2 +#define GPIO_PIN12_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN12_PAD_DRIVER_GET(x) (((x) & GPIO_PIN12_PAD_DRIVER_MASK) >> GPIO_PIN12_PAD_DRIVER_LSB) +#define GPIO_PIN12_PAD_DRIVER_SET(x) (((x) << GPIO_PIN12_PAD_DRIVER_LSB) & GPIO_PIN12_PAD_DRIVER_MASK) +#define GPIO_PIN12_SOURCE_MSB 0 +#define GPIO_PIN12_SOURCE_LSB 0 +#define GPIO_PIN12_SOURCE_MASK 0x00000001 +#define GPIO_PIN12_SOURCE_GET(x) (((x) & GPIO_PIN12_SOURCE_MASK) >> GPIO_PIN12_SOURCE_LSB) +#define GPIO_PIN12_SOURCE_SET(x) (((x) << GPIO_PIN12_SOURCE_LSB) & GPIO_PIN12_SOURCE_MASK) + +#define GPIO_PIN13_ADDRESS 0x0000005c +#define GPIO_PIN13_OFFSET 0x0000005c +#define GPIO_PIN13_CONFIG_MSB 12 +#define GPIO_PIN13_CONFIG_LSB 11 +#define GPIO_PIN13_CONFIG_MASK 0x00001800 +#define GPIO_PIN13_CONFIG_GET(x) (((x) & GPIO_PIN13_CONFIG_MASK) >> GPIO_PIN13_CONFIG_LSB) +#define GPIO_PIN13_CONFIG_SET(x) (((x) << GPIO_PIN13_CONFIG_LSB) & GPIO_PIN13_CONFIG_MASK) +#define GPIO_PIN13_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN13_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN13_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN13_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN13_WAKEUP_ENABLE_MASK) >> GPIO_PIN13_WAKEUP_ENABLE_LSB) +#define GPIO_PIN13_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN13_WAKEUP_ENABLE_LSB) & GPIO_PIN13_WAKEUP_ENABLE_MASK) +#define GPIO_PIN13_INT_TYPE_MSB 9 +#define GPIO_PIN13_INT_TYPE_LSB 7 +#define GPIO_PIN13_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN13_INT_TYPE_GET(x) (((x) & GPIO_PIN13_INT_TYPE_MASK) >> GPIO_PIN13_INT_TYPE_LSB) +#define GPIO_PIN13_INT_TYPE_SET(x) (((x) << GPIO_PIN13_INT_TYPE_LSB) & GPIO_PIN13_INT_TYPE_MASK) +#define GPIO_PIN13_PAD_DRIVER_MSB 2 +#define GPIO_PIN13_PAD_DRIVER_LSB 2 +#define GPIO_PIN13_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN13_PAD_DRIVER_GET(x) (((x) & GPIO_PIN13_PAD_DRIVER_MASK) >> GPIO_PIN13_PAD_DRIVER_LSB) +#define GPIO_PIN13_PAD_DRIVER_SET(x) (((x) << GPIO_PIN13_PAD_DRIVER_LSB) & GPIO_PIN13_PAD_DRIVER_MASK) +#define GPIO_PIN13_SOURCE_MSB 0 +#define GPIO_PIN13_SOURCE_LSB 0 +#define GPIO_PIN13_SOURCE_MASK 0x00000001 +#define GPIO_PIN13_SOURCE_GET(x) (((x) & GPIO_PIN13_SOURCE_MASK) >> GPIO_PIN13_SOURCE_LSB) +#define GPIO_PIN13_SOURCE_SET(x) (((x) << GPIO_PIN13_SOURCE_LSB) & GPIO_PIN13_SOURCE_MASK) + +#define GPIO_PIN14_ADDRESS 0x00000060 +#define GPIO_PIN14_OFFSET 0x00000060 +#define GPIO_PIN14_CONFIG_MSB 12 +#define GPIO_PIN14_CONFIG_LSB 11 +#define GPIO_PIN14_CONFIG_MASK 0x00001800 +#define GPIO_PIN14_CONFIG_GET(x) (((x) & GPIO_PIN14_CONFIG_MASK) >> GPIO_PIN14_CONFIG_LSB) +#define GPIO_PIN14_CONFIG_SET(x) (((x) << GPIO_PIN14_CONFIG_LSB) & GPIO_PIN14_CONFIG_MASK) +#define GPIO_PIN14_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN14_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN14_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN14_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN14_WAKEUP_ENABLE_MASK) >> GPIO_PIN14_WAKEUP_ENABLE_LSB) +#define GPIO_PIN14_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN14_WAKEUP_ENABLE_LSB) & GPIO_PIN14_WAKEUP_ENABLE_MASK) +#define GPIO_PIN14_INT_TYPE_MSB 9 +#define GPIO_PIN14_INT_TYPE_LSB 7 +#define GPIO_PIN14_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN14_INT_TYPE_GET(x) (((x) & GPIO_PIN14_INT_TYPE_MASK) >> GPIO_PIN14_INT_TYPE_LSB) +#define GPIO_PIN14_INT_TYPE_SET(x) (((x) << GPIO_PIN14_INT_TYPE_LSB) & GPIO_PIN14_INT_TYPE_MASK) +#define GPIO_PIN14_PAD_DRIVER_MSB 2 +#define GPIO_PIN14_PAD_DRIVER_LSB 2 +#define GPIO_PIN14_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN14_PAD_DRIVER_GET(x) (((x) & GPIO_PIN14_PAD_DRIVER_MASK) >> GPIO_PIN14_PAD_DRIVER_LSB) +#define GPIO_PIN14_PAD_DRIVER_SET(x) (((x) << GPIO_PIN14_PAD_DRIVER_LSB) & GPIO_PIN14_PAD_DRIVER_MASK) +#define GPIO_PIN14_SOURCE_MSB 0 +#define GPIO_PIN14_SOURCE_LSB 0 +#define GPIO_PIN14_SOURCE_MASK 0x00000001 +#define GPIO_PIN14_SOURCE_GET(x) (((x) & GPIO_PIN14_SOURCE_MASK) >> GPIO_PIN14_SOURCE_LSB) +#define GPIO_PIN14_SOURCE_SET(x) (((x) << GPIO_PIN14_SOURCE_LSB) & GPIO_PIN14_SOURCE_MASK) + +#define GPIO_PIN15_ADDRESS 0x00000064 +#define GPIO_PIN15_OFFSET 0x00000064 +#define GPIO_PIN15_CONFIG_MSB 12 +#define GPIO_PIN15_CONFIG_LSB 11 +#define GPIO_PIN15_CONFIG_MASK 0x00001800 +#define GPIO_PIN15_CONFIG_GET(x) (((x) & GPIO_PIN15_CONFIG_MASK) >> GPIO_PIN15_CONFIG_LSB) +#define GPIO_PIN15_CONFIG_SET(x) (((x) << GPIO_PIN15_CONFIG_LSB) & GPIO_PIN15_CONFIG_MASK) +#define GPIO_PIN15_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN15_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN15_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN15_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN15_WAKEUP_ENABLE_MASK) >> GPIO_PIN15_WAKEUP_ENABLE_LSB) +#define GPIO_PIN15_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN15_WAKEUP_ENABLE_LSB) & GPIO_PIN15_WAKEUP_ENABLE_MASK) +#define GPIO_PIN15_INT_TYPE_MSB 9 +#define GPIO_PIN15_INT_TYPE_LSB 7 +#define GPIO_PIN15_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN15_INT_TYPE_GET(x) (((x) & GPIO_PIN15_INT_TYPE_MASK) >> GPIO_PIN15_INT_TYPE_LSB) +#define GPIO_PIN15_INT_TYPE_SET(x) (((x) << GPIO_PIN15_INT_TYPE_LSB) & GPIO_PIN15_INT_TYPE_MASK) +#define GPIO_PIN15_PAD_DRIVER_MSB 2 +#define GPIO_PIN15_PAD_DRIVER_LSB 2 +#define GPIO_PIN15_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN15_PAD_DRIVER_GET(x) (((x) & GPIO_PIN15_PAD_DRIVER_MASK) >> GPIO_PIN15_PAD_DRIVER_LSB) +#define GPIO_PIN15_PAD_DRIVER_SET(x) (((x) << GPIO_PIN15_PAD_DRIVER_LSB) & GPIO_PIN15_PAD_DRIVER_MASK) +#define GPIO_PIN15_SOURCE_MSB 0 +#define GPIO_PIN15_SOURCE_LSB 0 +#define GPIO_PIN15_SOURCE_MASK 0x00000001 +#define GPIO_PIN15_SOURCE_GET(x) (((x) & GPIO_PIN15_SOURCE_MASK) >> GPIO_PIN15_SOURCE_LSB) +#define GPIO_PIN15_SOURCE_SET(x) (((x) << GPIO_PIN15_SOURCE_LSB) & GPIO_PIN15_SOURCE_MASK) + +#define GPIO_PIN16_ADDRESS 0x00000068 +#define GPIO_PIN16_OFFSET 0x00000068 +#define GPIO_PIN16_CONFIG_MSB 12 +#define GPIO_PIN16_CONFIG_LSB 11 +#define GPIO_PIN16_CONFIG_MASK 0x00001800 +#define GPIO_PIN16_CONFIG_GET(x) (((x) & GPIO_PIN16_CONFIG_MASK) >> GPIO_PIN16_CONFIG_LSB) +#define GPIO_PIN16_CONFIG_SET(x) (((x) << GPIO_PIN16_CONFIG_LSB) & GPIO_PIN16_CONFIG_MASK) +#define GPIO_PIN16_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN16_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN16_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN16_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN16_WAKEUP_ENABLE_MASK) >> GPIO_PIN16_WAKEUP_ENABLE_LSB) +#define GPIO_PIN16_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN16_WAKEUP_ENABLE_LSB) & GPIO_PIN16_WAKEUP_ENABLE_MASK) +#define GPIO_PIN16_INT_TYPE_MSB 9 +#define GPIO_PIN16_INT_TYPE_LSB 7 +#define GPIO_PIN16_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN16_INT_TYPE_GET(x) (((x) & GPIO_PIN16_INT_TYPE_MASK) >> GPIO_PIN16_INT_TYPE_LSB) +#define GPIO_PIN16_INT_TYPE_SET(x) (((x) << GPIO_PIN16_INT_TYPE_LSB) & GPIO_PIN16_INT_TYPE_MASK) +#define GPIO_PIN16_PAD_DRIVER_MSB 2 +#define GPIO_PIN16_PAD_DRIVER_LSB 2 +#define GPIO_PIN16_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN16_PAD_DRIVER_GET(x) (((x) & GPIO_PIN16_PAD_DRIVER_MASK) >> GPIO_PIN16_PAD_DRIVER_LSB) +#define GPIO_PIN16_PAD_DRIVER_SET(x) (((x) << GPIO_PIN16_PAD_DRIVER_LSB) & GPIO_PIN16_PAD_DRIVER_MASK) +#define GPIO_PIN16_SOURCE_MSB 0 +#define GPIO_PIN16_SOURCE_LSB 0 +#define GPIO_PIN16_SOURCE_MASK 0x00000001 +#define GPIO_PIN16_SOURCE_GET(x) (((x) & GPIO_PIN16_SOURCE_MASK) >> GPIO_PIN16_SOURCE_LSB) +#define GPIO_PIN16_SOURCE_SET(x) (((x) << GPIO_PIN16_SOURCE_LSB) & GPIO_PIN16_SOURCE_MASK) + +#define GPIO_PIN17_ADDRESS 0x0000006c +#define GPIO_PIN17_OFFSET 0x0000006c +#define GPIO_PIN17_CONFIG_MSB 12 +#define GPIO_PIN17_CONFIG_LSB 11 +#define GPIO_PIN17_CONFIG_MASK 0x00001800 +#define GPIO_PIN17_CONFIG_GET(x) (((x) & GPIO_PIN17_CONFIG_MASK) >> GPIO_PIN17_CONFIG_LSB) +#define GPIO_PIN17_CONFIG_SET(x) (((x) << GPIO_PIN17_CONFIG_LSB) & GPIO_PIN17_CONFIG_MASK) +#define GPIO_PIN17_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN17_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN17_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN17_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN17_WAKEUP_ENABLE_MASK) >> GPIO_PIN17_WAKEUP_ENABLE_LSB) +#define GPIO_PIN17_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN17_WAKEUP_ENABLE_LSB) & GPIO_PIN17_WAKEUP_ENABLE_MASK) +#define GPIO_PIN17_INT_TYPE_MSB 9 +#define GPIO_PIN17_INT_TYPE_LSB 7 +#define GPIO_PIN17_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN17_INT_TYPE_GET(x) (((x) & GPIO_PIN17_INT_TYPE_MASK) >> GPIO_PIN17_INT_TYPE_LSB) +#define GPIO_PIN17_INT_TYPE_SET(x) (((x) << GPIO_PIN17_INT_TYPE_LSB) & GPIO_PIN17_INT_TYPE_MASK) +#define GPIO_PIN17_PAD_DRIVER_MSB 2 +#define GPIO_PIN17_PAD_DRIVER_LSB 2 +#define GPIO_PIN17_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN17_PAD_DRIVER_GET(x) (((x) & GPIO_PIN17_PAD_DRIVER_MASK) >> GPIO_PIN17_PAD_DRIVER_LSB) +#define GPIO_PIN17_PAD_DRIVER_SET(x) (((x) << GPIO_PIN17_PAD_DRIVER_LSB) & GPIO_PIN17_PAD_DRIVER_MASK) +#define GPIO_PIN17_SOURCE_MSB 0 +#define GPIO_PIN17_SOURCE_LSB 0 +#define GPIO_PIN17_SOURCE_MASK 0x00000001 +#define GPIO_PIN17_SOURCE_GET(x) (((x) & GPIO_PIN17_SOURCE_MASK) >> GPIO_PIN17_SOURCE_LSB) +#define GPIO_PIN17_SOURCE_SET(x) (((x) << GPIO_PIN17_SOURCE_LSB) & GPIO_PIN17_SOURCE_MASK) + +#define SDIO_PIN_ADDRESS 0x00000070 +#define SDIO_PIN_OFFSET 0x00000070 +#define SDIO_PIN_PAD_PULL_MSB 3 +#define SDIO_PIN_PAD_PULL_LSB 2 +#define SDIO_PIN_PAD_PULL_MASK 0x0000000c +#define SDIO_PIN_PAD_PULL_GET(x) (((x) & SDIO_PIN_PAD_PULL_MASK) >> SDIO_PIN_PAD_PULL_LSB) +#define SDIO_PIN_PAD_PULL_SET(x) (((x) << SDIO_PIN_PAD_PULL_LSB) & SDIO_PIN_PAD_PULL_MASK) +#define SDIO_PIN_PAD_STRENGTH_MSB 1 +#define SDIO_PIN_PAD_STRENGTH_LSB 0 +#define SDIO_PIN_PAD_STRENGTH_MASK 0x00000003 +#define SDIO_PIN_PAD_STRENGTH_GET(x) (((x) & SDIO_PIN_PAD_STRENGTH_MASK) >> SDIO_PIN_PAD_STRENGTH_LSB) +#define SDIO_PIN_PAD_STRENGTH_SET(x) (((x) << SDIO_PIN_PAD_STRENGTH_LSB) & SDIO_PIN_PAD_STRENGTH_MASK) + +#define CLK_REQ_PIN_ADDRESS 0x00000074 +#define CLK_REQ_PIN_OFFSET 0x00000074 +#define CLK_REQ_PIN_ATE_OE_L_MSB 4 +#define CLK_REQ_PIN_ATE_OE_L_LSB 4 +#define CLK_REQ_PIN_ATE_OE_L_MASK 0x00000010 +#define CLK_REQ_PIN_ATE_OE_L_GET(x) (((x) & CLK_REQ_PIN_ATE_OE_L_MASK) >> CLK_REQ_PIN_ATE_OE_L_LSB) +#define CLK_REQ_PIN_ATE_OE_L_SET(x) (((x) << CLK_REQ_PIN_ATE_OE_L_LSB) & CLK_REQ_PIN_ATE_OE_L_MASK) +#define CLK_REQ_PIN_PAD_PULL_MSB 3 +#define CLK_REQ_PIN_PAD_PULL_LSB 2 +#define CLK_REQ_PIN_PAD_PULL_MASK 0x0000000c +#define CLK_REQ_PIN_PAD_PULL_GET(x) (((x) & CLK_REQ_PIN_PAD_PULL_MASK) >> CLK_REQ_PIN_PAD_PULL_LSB) +#define CLK_REQ_PIN_PAD_PULL_SET(x) (((x) << CLK_REQ_PIN_PAD_PULL_LSB) & CLK_REQ_PIN_PAD_PULL_MASK) +#define CLK_REQ_PIN_PAD_STRENGTH_MSB 1 +#define CLK_REQ_PIN_PAD_STRENGTH_LSB 0 +#define CLK_REQ_PIN_PAD_STRENGTH_MASK 0x00000003 +#define CLK_REQ_PIN_PAD_STRENGTH_GET(x) (((x) & CLK_REQ_PIN_PAD_STRENGTH_MASK) >> CLK_REQ_PIN_PAD_STRENGTH_LSB) +#define CLK_REQ_PIN_PAD_STRENGTH_SET(x) (((x) << CLK_REQ_PIN_PAD_STRENGTH_LSB) & CLK_REQ_PIN_PAD_STRENGTH_MASK) + +#define SIGMA_DELTA_ADDRESS 0x00000078 +#define SIGMA_DELTA_OFFSET 0x00000078 +#define SIGMA_DELTA_ENABLE_MSB 16 +#define SIGMA_DELTA_ENABLE_LSB 16 +#define SIGMA_DELTA_ENABLE_MASK 0x00010000 +#define SIGMA_DELTA_ENABLE_GET(x) (((x) & SIGMA_DELTA_ENABLE_MASK) >> SIGMA_DELTA_ENABLE_LSB) +#define SIGMA_DELTA_ENABLE_SET(x) (((x) << SIGMA_DELTA_ENABLE_LSB) & SIGMA_DELTA_ENABLE_MASK) +#define SIGMA_DELTA_PRESCALAR_MSB 15 +#define SIGMA_DELTA_PRESCALAR_LSB 8 +#define SIGMA_DELTA_PRESCALAR_MASK 0x0000ff00 +#define SIGMA_DELTA_PRESCALAR_GET(x) (((x) & SIGMA_DELTA_PRESCALAR_MASK) >> SIGMA_DELTA_PRESCALAR_LSB) +#define SIGMA_DELTA_PRESCALAR_SET(x) (((x) << SIGMA_DELTA_PRESCALAR_LSB) & SIGMA_DELTA_PRESCALAR_MASK) +#define SIGMA_DELTA_TARGET_MSB 7 +#define SIGMA_DELTA_TARGET_LSB 0 +#define SIGMA_DELTA_TARGET_MASK 0x000000ff +#define SIGMA_DELTA_TARGET_GET(x) (((x) & SIGMA_DELTA_TARGET_MASK) >> SIGMA_DELTA_TARGET_LSB) +#define SIGMA_DELTA_TARGET_SET(x) (((x) << SIGMA_DELTA_TARGET_LSB) & SIGMA_DELTA_TARGET_MASK) + +#define DEBUG_CONTROL_ADDRESS 0x0000007c +#define DEBUG_CONTROL_OFFSET 0x0000007c +#define DEBUG_CONTROL_OBS_OE_L_MSB 1 +#define DEBUG_CONTROL_OBS_OE_L_LSB 1 +#define DEBUG_CONTROL_OBS_OE_L_MASK 0x00000002 +#define DEBUG_CONTROL_OBS_OE_L_GET(x) (((x) & DEBUG_CONTROL_OBS_OE_L_MASK) >> DEBUG_CONTROL_OBS_OE_L_LSB) +#define DEBUG_CONTROL_OBS_OE_L_SET(x) (((x) << DEBUG_CONTROL_OBS_OE_L_LSB) & DEBUG_CONTROL_OBS_OE_L_MASK) +#define DEBUG_CONTROL_ENABLE_MSB 0 +#define DEBUG_CONTROL_ENABLE_LSB 0 +#define DEBUG_CONTROL_ENABLE_MASK 0x00000001 +#define DEBUG_CONTROL_ENABLE_GET(x) (((x) & DEBUG_CONTROL_ENABLE_MASK) >> DEBUG_CONTROL_ENABLE_LSB) +#define DEBUG_CONTROL_ENABLE_SET(x) (((x) << DEBUG_CONTROL_ENABLE_LSB) & DEBUG_CONTROL_ENABLE_MASK) + +#define DEBUG_INPUT_SEL_ADDRESS 0x00000080 +#define DEBUG_INPUT_SEL_OFFSET 0x00000080 +#define DEBUG_INPUT_SEL_SRC_MSB 3 +#define DEBUG_INPUT_SEL_SRC_LSB 0 +#define DEBUG_INPUT_SEL_SRC_MASK 0x0000000f +#define DEBUG_INPUT_SEL_SRC_GET(x) (((x) & DEBUG_INPUT_SEL_SRC_MASK) >> DEBUG_INPUT_SEL_SRC_LSB) +#define DEBUG_INPUT_SEL_SRC_SET(x) (((x) << DEBUG_INPUT_SEL_SRC_LSB) & DEBUG_INPUT_SEL_SRC_MASK) + +#define DEBUG_OUT_ADDRESS 0x00000084 +#define DEBUG_OUT_OFFSET 0x00000084 +#define DEBUG_OUT_DATA_MSB 17 +#define DEBUG_OUT_DATA_LSB 0 +#define DEBUG_OUT_DATA_MASK 0x0003ffff +#define DEBUG_OUT_DATA_GET(x) (((x) & DEBUG_OUT_DATA_MASK) >> DEBUG_OUT_DATA_LSB) +#define DEBUG_OUT_DATA_SET(x) (((x) << DEBUG_OUT_DATA_LSB) & DEBUG_OUT_DATA_MASK) + +#define LA_CONTROL_ADDRESS 0x00000088 +#define LA_CONTROL_OFFSET 0x00000088 +#define LA_CONTROL_RUN_MSB 1 +#define LA_CONTROL_RUN_LSB 1 +#define LA_CONTROL_RUN_MASK 0x00000002 +#define LA_CONTROL_RUN_GET(x) (((x) & LA_CONTROL_RUN_MASK) >> LA_CONTROL_RUN_LSB) +#define LA_CONTROL_RUN_SET(x) (((x) << LA_CONTROL_RUN_LSB) & LA_CONTROL_RUN_MASK) +#define LA_CONTROL_TRIGGERED_MSB 0 +#define LA_CONTROL_TRIGGERED_LSB 0 +#define LA_CONTROL_TRIGGERED_MASK 0x00000001 +#define LA_CONTROL_TRIGGERED_GET(x) (((x) & LA_CONTROL_TRIGGERED_MASK) >> LA_CONTROL_TRIGGERED_LSB) +#define LA_CONTROL_TRIGGERED_SET(x) (((x) << LA_CONTROL_TRIGGERED_LSB) & LA_CONTROL_TRIGGERED_MASK) + +#define LA_CLOCK_ADDRESS 0x0000008c +#define LA_CLOCK_OFFSET 0x0000008c +#define LA_CLOCK_DIV_MSB 7 +#define LA_CLOCK_DIV_LSB 0 +#define LA_CLOCK_DIV_MASK 0x000000ff +#define LA_CLOCK_DIV_GET(x) (((x) & LA_CLOCK_DIV_MASK) >> LA_CLOCK_DIV_LSB) +#define LA_CLOCK_DIV_SET(x) (((x) << LA_CLOCK_DIV_LSB) & LA_CLOCK_DIV_MASK) + +#define LA_STATUS_ADDRESS 0x00000090 +#define LA_STATUS_OFFSET 0x00000090 +#define LA_STATUS_INTERRUPT_MSB 0 +#define LA_STATUS_INTERRUPT_LSB 0 +#define LA_STATUS_INTERRUPT_MASK 0x00000001 +#define LA_STATUS_INTERRUPT_GET(x) (((x) & LA_STATUS_INTERRUPT_MASK) >> LA_STATUS_INTERRUPT_LSB) +#define LA_STATUS_INTERRUPT_SET(x) (((x) << LA_STATUS_INTERRUPT_LSB) & LA_STATUS_INTERRUPT_MASK) + +#define LA_TRIGGER_SAMPLE_ADDRESS 0x00000094 +#define LA_TRIGGER_SAMPLE_OFFSET 0x00000094 +#define LA_TRIGGER_SAMPLE_COUNT_MSB 15 +#define LA_TRIGGER_SAMPLE_COUNT_LSB 0 +#define LA_TRIGGER_SAMPLE_COUNT_MASK 0x0000ffff +#define LA_TRIGGER_SAMPLE_COUNT_GET(x) (((x) & LA_TRIGGER_SAMPLE_COUNT_MASK) >> LA_TRIGGER_SAMPLE_COUNT_LSB) +#define LA_TRIGGER_SAMPLE_COUNT_SET(x) (((x) << LA_TRIGGER_SAMPLE_COUNT_LSB) & LA_TRIGGER_SAMPLE_COUNT_MASK) + +#define LA_TRIGGER_POSITION_ADDRESS 0x00000098 +#define LA_TRIGGER_POSITION_OFFSET 0x00000098 +#define LA_TRIGGER_POSITION_VALUE_MSB 15 +#define LA_TRIGGER_POSITION_VALUE_LSB 0 +#define LA_TRIGGER_POSITION_VALUE_MASK 0x0000ffff +#define LA_TRIGGER_POSITION_VALUE_GET(x) (((x) & LA_TRIGGER_POSITION_VALUE_MASK) >> LA_TRIGGER_POSITION_VALUE_LSB) +#define LA_TRIGGER_POSITION_VALUE_SET(x) (((x) << LA_TRIGGER_POSITION_VALUE_LSB) & LA_TRIGGER_POSITION_VALUE_MASK) + +#define LA_PRE_TRIGGER_ADDRESS 0x0000009c +#define LA_PRE_TRIGGER_OFFSET 0x0000009c +#define LA_PRE_TRIGGER_COUNT_MSB 15 +#define LA_PRE_TRIGGER_COUNT_LSB 0 +#define LA_PRE_TRIGGER_COUNT_MASK 0x0000ffff +#define LA_PRE_TRIGGER_COUNT_GET(x) (((x) & LA_PRE_TRIGGER_COUNT_MASK) >> LA_PRE_TRIGGER_COUNT_LSB) +#define LA_PRE_TRIGGER_COUNT_SET(x) (((x) << LA_PRE_TRIGGER_COUNT_LSB) & LA_PRE_TRIGGER_COUNT_MASK) + +#define LA_POST_TRIGGER_ADDRESS 0x000000a0 +#define LA_POST_TRIGGER_OFFSET 0x000000a0 +#define LA_POST_TRIGGER_COUNT_MSB 15 +#define LA_POST_TRIGGER_COUNT_LSB 0 +#define LA_POST_TRIGGER_COUNT_MASK 0x0000ffff +#define LA_POST_TRIGGER_COUNT_GET(x) (((x) & LA_POST_TRIGGER_COUNT_MASK) >> LA_POST_TRIGGER_COUNT_LSB) +#define LA_POST_TRIGGER_COUNT_SET(x) (((x) << LA_POST_TRIGGER_COUNT_LSB) & LA_POST_TRIGGER_COUNT_MASK) + +#define LA_FILTER_CONTROL_ADDRESS 0x000000a4 +#define LA_FILTER_CONTROL_OFFSET 0x000000a4 +#define LA_FILTER_CONTROL_DELTA_MSB 0 +#define LA_FILTER_CONTROL_DELTA_LSB 0 +#define LA_FILTER_CONTROL_DELTA_MASK 0x00000001 +#define LA_FILTER_CONTROL_DELTA_GET(x) (((x) & LA_FILTER_CONTROL_DELTA_MASK) >> LA_FILTER_CONTROL_DELTA_LSB) +#define LA_FILTER_CONTROL_DELTA_SET(x) (((x) << LA_FILTER_CONTROL_DELTA_LSB) & LA_FILTER_CONTROL_DELTA_MASK) + +#define LA_FILTER_DATA_ADDRESS 0x000000a8 +#define LA_FILTER_DATA_OFFSET 0x000000a8 +#define LA_FILTER_DATA_MATCH_MSB 17 +#define LA_FILTER_DATA_MATCH_LSB 0 +#define LA_FILTER_DATA_MATCH_MASK 0x0003ffff +#define LA_FILTER_DATA_MATCH_GET(x) (((x) & LA_FILTER_DATA_MATCH_MASK) >> LA_FILTER_DATA_MATCH_LSB) +#define LA_FILTER_DATA_MATCH_SET(x) (((x) << LA_FILTER_DATA_MATCH_LSB) & LA_FILTER_DATA_MATCH_MASK) + +#define LA_FILTER_WILDCARD_ADDRESS 0x000000ac +#define LA_FILTER_WILDCARD_OFFSET 0x000000ac +#define LA_FILTER_WILDCARD_MATCH_MSB 17 +#define LA_FILTER_WILDCARD_MATCH_LSB 0 +#define LA_FILTER_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_FILTER_WILDCARD_MATCH_GET(x) (((x) & LA_FILTER_WILDCARD_MATCH_MASK) >> LA_FILTER_WILDCARD_MATCH_LSB) +#define LA_FILTER_WILDCARD_MATCH_SET(x) (((x) << LA_FILTER_WILDCARD_MATCH_LSB) & LA_FILTER_WILDCARD_MATCH_MASK) + +#define LA_TRIGGERA_DATA_ADDRESS 0x000000b0 +#define LA_TRIGGERA_DATA_OFFSET 0x000000b0 +#define LA_TRIGGERA_DATA_MATCH_MSB 17 +#define LA_TRIGGERA_DATA_MATCH_LSB 0 +#define LA_TRIGGERA_DATA_MATCH_MASK 0x0003ffff +#define LA_TRIGGERA_DATA_MATCH_GET(x) (((x) & LA_TRIGGERA_DATA_MATCH_MASK) >> LA_TRIGGERA_DATA_MATCH_LSB) +#define LA_TRIGGERA_DATA_MATCH_SET(x) (((x) << LA_TRIGGERA_DATA_MATCH_LSB) & LA_TRIGGERA_DATA_MATCH_MASK) + +#define LA_TRIGGERA_WILDCARD_ADDRESS 0x000000b4 +#define LA_TRIGGERA_WILDCARD_OFFSET 0x000000b4 +#define LA_TRIGGERA_WILDCARD_MATCH_MSB 17 +#define LA_TRIGGERA_WILDCARD_MATCH_LSB 0 +#define LA_TRIGGERA_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_TRIGGERA_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERA_WILDCARD_MATCH_MASK) >> LA_TRIGGERA_WILDCARD_MATCH_LSB) +#define LA_TRIGGERA_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERA_WILDCARD_MATCH_LSB) & LA_TRIGGERA_WILDCARD_MATCH_MASK) + +#define LA_TRIGGERB_DATA_ADDRESS 0x000000b8 +#define LA_TRIGGERB_DATA_OFFSET 0x000000b8 +#define LA_TRIGGERB_DATA_MATCH_MSB 17 +#define LA_TRIGGERB_DATA_MATCH_LSB 0 +#define LA_TRIGGERB_DATA_MATCH_MASK 0x0003ffff +#define LA_TRIGGERB_DATA_MATCH_GET(x) (((x) & LA_TRIGGERB_DATA_MATCH_MASK) >> LA_TRIGGERB_DATA_MATCH_LSB) +#define LA_TRIGGERB_DATA_MATCH_SET(x) (((x) << LA_TRIGGERB_DATA_MATCH_LSB) & LA_TRIGGERB_DATA_MATCH_MASK) + +#define LA_TRIGGERB_WILDCARD_ADDRESS 0x000000bc +#define LA_TRIGGERB_WILDCARD_OFFSET 0x000000bc +#define LA_TRIGGERB_WILDCARD_MATCH_MSB 17 +#define LA_TRIGGERB_WILDCARD_MATCH_LSB 0 +#define LA_TRIGGERB_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_TRIGGERB_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERB_WILDCARD_MATCH_MASK) >> LA_TRIGGERB_WILDCARD_MATCH_LSB) +#define LA_TRIGGERB_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERB_WILDCARD_MATCH_LSB) & LA_TRIGGERB_WILDCARD_MATCH_MASK) + +#define LA_TRIGGER_ADDRESS 0x000000c0 +#define LA_TRIGGER_OFFSET 0x000000c0 +#define LA_TRIGGER_EVENT_MSB 2 +#define LA_TRIGGER_EVENT_LSB 0 +#define LA_TRIGGER_EVENT_MASK 0x00000007 +#define LA_TRIGGER_EVENT_GET(x) (((x) & LA_TRIGGER_EVENT_MASK) >> LA_TRIGGER_EVENT_LSB) +#define LA_TRIGGER_EVENT_SET(x) (((x) << LA_TRIGGER_EVENT_LSB) & LA_TRIGGER_EVENT_MASK) + +#define LA_FIFO_ADDRESS 0x000000c4 +#define LA_FIFO_OFFSET 0x000000c4 +#define LA_FIFO_FULL_MSB 1 +#define LA_FIFO_FULL_LSB 1 +#define LA_FIFO_FULL_MASK 0x00000002 +#define LA_FIFO_FULL_GET(x) (((x) & LA_FIFO_FULL_MASK) >> LA_FIFO_FULL_LSB) +#define LA_FIFO_FULL_SET(x) (((x) << LA_FIFO_FULL_LSB) & LA_FIFO_FULL_MASK) +#define LA_FIFO_EMPTY_MSB 0 +#define LA_FIFO_EMPTY_LSB 0 +#define LA_FIFO_EMPTY_MASK 0x00000001 +#define LA_FIFO_EMPTY_GET(x) (((x) & LA_FIFO_EMPTY_MASK) >> LA_FIFO_EMPTY_LSB) +#define LA_FIFO_EMPTY_SET(x) (((x) << LA_FIFO_EMPTY_LSB) & LA_FIFO_EMPTY_MASK) + +#define LA_ADDRESS 0x000000c8 +#define LA_OFFSET 0x000000c8 +#define LA_DATA_MSB 17 +#define LA_DATA_LSB 0 +#define LA_DATA_MASK 0x0003ffff +#define LA_DATA_GET(x) (((x) & LA_DATA_MASK) >> LA_DATA_LSB) +#define LA_DATA_SET(x) (((x) << LA_DATA_LSB) & LA_DATA_MASK) + +#define ANT_PIN_ADDRESS 0x000000d0 +#define ANT_PIN_OFFSET 0x000000d0 +#define ANT_PIN_PAD_PULL_MSB 3 +#define ANT_PIN_PAD_PULL_LSB 2 +#define ANT_PIN_PAD_PULL_MASK 0x0000000c +#define ANT_PIN_PAD_PULL_GET(x) (((x) & ANT_PIN_PAD_PULL_MASK) >> ANT_PIN_PAD_PULL_LSB) +#define ANT_PIN_PAD_PULL_SET(x) (((x) << ANT_PIN_PAD_PULL_LSB) & ANT_PIN_PAD_PULL_MASK) +#define ANT_PIN_PAD_STRENGTH_MSB 1 +#define ANT_PIN_PAD_STRENGTH_LSB 0 +#define ANT_PIN_PAD_STRENGTH_MASK 0x00000003 +#define ANT_PIN_PAD_STRENGTH_GET(x) (((x) & ANT_PIN_PAD_STRENGTH_MASK) >> ANT_PIN_PAD_STRENGTH_LSB) +#define ANT_PIN_PAD_STRENGTH_SET(x) (((x) << ANT_PIN_PAD_STRENGTH_LSB) & ANT_PIN_PAD_STRENGTH_MASK) + +#define ANTD_PIN_ADDRESS 0x000000d4 +#define ANTD_PIN_OFFSET 0x000000d4 +#define ANTD_PIN_PAD_PULL_MSB 1 +#define ANTD_PIN_PAD_PULL_LSB 0 +#define ANTD_PIN_PAD_PULL_MASK 0x00000003 +#define ANTD_PIN_PAD_PULL_GET(x) (((x) & ANTD_PIN_PAD_PULL_MASK) >> ANTD_PIN_PAD_PULL_LSB) +#define ANTD_PIN_PAD_PULL_SET(x) (((x) << ANTD_PIN_PAD_PULL_LSB) & ANTD_PIN_PAD_PULL_MASK) + +#define GPIO_PIN_ADDRESS 0x000000d8 +#define GPIO_PIN_OFFSET 0x000000d8 +#define GPIO_PIN_PAD_PULL_MSB 3 +#define GPIO_PIN_PAD_PULL_LSB 2 +#define GPIO_PIN_PAD_PULL_MASK 0x0000000c +#define GPIO_PIN_PAD_PULL_GET(x) (((x) & GPIO_PIN_PAD_PULL_MASK) >> GPIO_PIN_PAD_PULL_LSB) +#define GPIO_PIN_PAD_PULL_SET(x) (((x) << GPIO_PIN_PAD_PULL_LSB) & GPIO_PIN_PAD_PULL_MASK) +#define GPIO_PIN_PAD_STRENGTH_MSB 1 +#define GPIO_PIN_PAD_STRENGTH_LSB 0 +#define GPIO_PIN_PAD_STRENGTH_MASK 0x00000003 +#define GPIO_PIN_PAD_STRENGTH_GET(x) (((x) & GPIO_PIN_PAD_STRENGTH_MASK) >> GPIO_PIN_PAD_STRENGTH_LSB) +#define GPIO_PIN_PAD_STRENGTH_SET(x) (((x) << GPIO_PIN_PAD_STRENGTH_LSB) & GPIO_PIN_PAD_STRENGTH_MASK) + +#define GPIO_H_PIN_ADDRESS 0x000000dc +#define GPIO_H_PIN_OFFSET 0x000000dc +#define GPIO_H_PIN_PAD_PULL_MSB 1 +#define GPIO_H_PIN_PAD_PULL_LSB 0 +#define GPIO_H_PIN_PAD_PULL_MASK 0x00000003 +#define GPIO_H_PIN_PAD_PULL_GET(x) (((x) & GPIO_H_PIN_PAD_PULL_MASK) >> GPIO_H_PIN_PAD_PULL_LSB) +#define GPIO_H_PIN_PAD_PULL_SET(x) (((x) << GPIO_H_PIN_PAD_PULL_LSB) & GPIO_H_PIN_PAD_PULL_MASK) + +#define BT_PIN_ADDRESS 0x000000e0 +#define BT_PIN_OFFSET 0x000000e0 +#define BT_PIN_PAD_PULL_MSB 3 +#define BT_PIN_PAD_PULL_LSB 2 +#define BT_PIN_PAD_PULL_MASK 0x0000000c +#define BT_PIN_PAD_PULL_GET(x) (((x) & BT_PIN_PAD_PULL_MASK) >> BT_PIN_PAD_PULL_LSB) +#define BT_PIN_PAD_PULL_SET(x) (((x) << BT_PIN_PAD_PULL_LSB) & BT_PIN_PAD_PULL_MASK) +#define BT_PIN_PAD_STRENGTH_MSB 1 +#define BT_PIN_PAD_STRENGTH_LSB 0 +#define BT_PIN_PAD_STRENGTH_MASK 0x00000003 +#define BT_PIN_PAD_STRENGTH_GET(x) (((x) & BT_PIN_PAD_STRENGTH_MASK) >> BT_PIN_PAD_STRENGTH_LSB) +#define BT_PIN_PAD_STRENGTH_SET(x) (((x) << BT_PIN_PAD_STRENGTH_LSB) & BT_PIN_PAD_STRENGTH_MASK) + +#define BT_WLAN_PIN_ADDRESS 0x000000e4 +#define BT_WLAN_PIN_OFFSET 0x000000e4 +#define BT_WLAN_PIN_PAD_PULL_MSB 1 +#define BT_WLAN_PIN_PAD_PULL_LSB 0 +#define BT_WLAN_PIN_PAD_PULL_MASK 0x00000003 +#define BT_WLAN_PIN_PAD_PULL_GET(x) (((x) & BT_WLAN_PIN_PAD_PULL_MASK) >> BT_WLAN_PIN_PAD_PULL_LSB) +#define BT_WLAN_PIN_PAD_PULL_SET(x) (((x) << BT_WLAN_PIN_PAD_PULL_LSB) & BT_WLAN_PIN_PAD_PULL_MASK) + +#define SI_UART_PIN_ADDRESS 0x000000e8 +#define SI_UART_PIN_OFFSET 0x000000e8 +#define SI_UART_PIN_PAD_PULL_MSB 3 +#define SI_UART_PIN_PAD_PULL_LSB 2 +#define SI_UART_PIN_PAD_PULL_MASK 0x0000000c +#define SI_UART_PIN_PAD_PULL_GET(x) (((x) & SI_UART_PIN_PAD_PULL_MASK) >> SI_UART_PIN_PAD_PULL_LSB) +#define SI_UART_PIN_PAD_PULL_SET(x) (((x) << SI_UART_PIN_PAD_PULL_LSB) & SI_UART_PIN_PAD_PULL_MASK) +#define SI_UART_PIN_PAD_STRENGTH_MSB 1 +#define SI_UART_PIN_PAD_STRENGTH_LSB 0 +#define SI_UART_PIN_PAD_STRENGTH_MASK 0x00000003 +#define SI_UART_PIN_PAD_STRENGTH_GET(x) (((x) & SI_UART_PIN_PAD_STRENGTH_MASK) >> SI_UART_PIN_PAD_STRENGTH_LSB) +#define SI_UART_PIN_PAD_STRENGTH_SET(x) (((x) << SI_UART_PIN_PAD_STRENGTH_LSB) & SI_UART_PIN_PAD_STRENGTH_MASK) + +#define CLK32K_PIN_ADDRESS 0x000000ec +#define CLK32K_PIN_OFFSET 0x000000ec +#define CLK32K_PIN_PAD_PULL_MSB 1 +#define CLK32K_PIN_PAD_PULL_LSB 0 +#define CLK32K_PIN_PAD_PULL_MASK 0x00000003 +#define CLK32K_PIN_PAD_PULL_GET(x) (((x) & CLK32K_PIN_PAD_PULL_MASK) >> CLK32K_PIN_PAD_PULL_LSB) +#define CLK32K_PIN_PAD_PULL_SET(x) (((x) << CLK32K_PIN_PAD_PULL_LSB) & CLK32K_PIN_PAD_PULL_MASK) + +#define RESET_TUPLE_STATUS_ADDRESS 0x000000f0 +#define RESET_TUPLE_STATUS_OFFSET 0x000000f0 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7 +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0 +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct gpio_reg_reg_s { + volatile unsigned int gpio_out; + volatile unsigned int gpio_out_w1ts; + volatile unsigned int gpio_out_w1tc; + volatile unsigned int gpio_enable; + volatile unsigned int gpio_enable_w1ts; + volatile unsigned int gpio_enable_w1tc; + volatile unsigned int gpio_in; + volatile unsigned int gpio_status; + volatile unsigned int gpio_status_w1ts; + volatile unsigned int gpio_status_w1tc; + volatile unsigned int gpio_pin0; + volatile unsigned int gpio_pin1; + volatile unsigned int gpio_pin2; + volatile unsigned int gpio_pin3; + volatile unsigned int gpio_pin4; + volatile unsigned int gpio_pin5; + volatile unsigned int gpio_pin6; + volatile unsigned int gpio_pin7; + volatile unsigned int gpio_pin8; + volatile unsigned int gpio_pin9; + volatile unsigned int gpio_pin10; + volatile unsigned int gpio_pin11; + volatile unsigned int gpio_pin12; + volatile unsigned int gpio_pin13; + volatile unsigned int gpio_pin14; + volatile unsigned int gpio_pin15; + volatile unsigned int gpio_pin16; + volatile unsigned int gpio_pin17; + volatile unsigned int sdio_pin; + volatile unsigned int clk_req_pin; + volatile unsigned int sigma_delta; + volatile unsigned int debug_control; + volatile unsigned int debug_input_sel; + volatile unsigned int debug_out; + volatile unsigned int la_control; + volatile unsigned int la_clock; + volatile unsigned int la_status; + volatile unsigned int la_trigger_sample; + volatile unsigned int la_trigger_position; + volatile unsigned int la_pre_trigger; + volatile unsigned int la_post_trigger; + volatile unsigned int la_filter_control; + volatile unsigned int la_filter_data; + volatile unsigned int la_filter_wildcard; + volatile unsigned int la_triggera_data; + volatile unsigned int la_triggera_wildcard; + volatile unsigned int la_triggerb_data; + volatile unsigned int la_triggerb_wildcard; + volatile unsigned int la_trigger; + volatile unsigned int la_fifo; + volatile unsigned int la[2]; + volatile unsigned int ant_pin; + volatile unsigned int antd_pin; + volatile unsigned int gpio_pin; + volatile unsigned int gpio_h_pin; + volatile unsigned int bt_pin; + volatile unsigned int bt_wlan_pin; + volatile unsigned int si_uart_pin; + volatile unsigned int clk32k_pin; + volatile unsigned int reset_tuple_status; +} gpio_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _GPIO_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/hif.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/hif.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/hif.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/hif.c 2010-08-11 00:35:01.000000000 -0400 @@ -0,0 +1,753 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// The software source and binaries included in this development package are +// licensed, not sold. You, or your company, received the package under one +// or more license agreements. The rights granted to you are specifically +// listed in these license agreement(s). All other rights remain with Atheros +// Communications, Inc., its subsidiaries, or the respective owner including +// those listed on the included copyright notices. Distribution of any +// portion of this package must be in strict compliance with the license +// agreement(s) terms. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// HIF layer reference implementation for Linux Native MMC stack +// +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include +/* by default setup a bounce buffer for the data packets, if the underlying host controller driver + does not use DMA you may be able to skip this step and save the memory allocation and transfer time */ +#define HIF_USE_DMA_BOUNCE_BUFFER 1 +#include "hif_internal.h" + + +static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id); +static void hifDeviceRemoved(struct sdio_func *func); +static HIF_DEVICE *addHifDevice(struct sdio_func *func); +static HIF_DEVICE *getHifDevice(struct sdio_func *func); +static void delHifDevice(HIF_DEVICE * device); + + + +/* ------ Static Variables ------ */ +static const struct sdio_device_id ar6k_id_table[] = { + { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x0)) }, + { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x1)) }, + { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0)) }, + { /* null */ }, +}; +MODULE_DEVICE_TABLE(sdio, ar6k_id_table); + +static struct sdio_driver ar6k_driver = { + .name = "ar6k_wlan", + .id_table = ar6k_id_table, + .probe = hifDeviceInserted, + .remove = hifDeviceRemoved, +}; +/* make sure we only unregister when registered. */ +static int registered = 0; + +OSDRV_CALLBACKS osdrvCallbacks; +extern A_UINT32 onebitmode; +extern A_UINT32 busspeedlow; +extern A_UINT32 debughif; + +#ifdef DEBUG +#define ATH_DEBUG_ERROR 1 +#define ATH_DEBUG_WARN 2 +#define ATH_DEBUG_TRACE 3 +#define _AR_DEBUG_PRINTX_ARG(arg...) arg +#define AR_DEBUG_PRINTF(lvl, args)\ + {if (lvl <= debughif)\ + A_PRINTF(KERN_ALERT _AR_DEBUG_PRINTX_ARG args);\ + } +#define AR_DEBUG_ASSERT(test) do { \ + if (!(test)) { \ + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test)); \ + } \ +} while(0) +#else +#define AR_DEBUG_PRINTF(lvl, args) +#define AR_DEBUG_ASSERT(test) +#endif + +static BUS_REQUEST *hifAllocateBusRequest(HIF_DEVICE *device); +static void hifFreeBusRequest(HIF_DEVICE *device, BUS_REQUEST *busrequest); +static void ResetAllCards(void); + +/* ------ Functions ------ */ +A_STATUS HIFInit(OSDRV_CALLBACKS *callbacks) +{ + int status; + AR_DEBUG_ASSERT(callbacks != NULL); + + /* store the callback handlers */ + osdrvCallbacks = *callbacks; + + /* Register with bus driver core */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFInit registering\n")); + registered = 1; + status = sdio_register_driver(&ar6k_driver); + AR_DEBUG_ASSERT(status==0); + + if (status != 0) { + return A_ERROR; + } + + return A_OK; + +} + +static A_STATUS +__HIFReadWrite(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length, + A_UINT32 request, + void *context) +{ + A_UINT8 opcode; + A_STATUS status = A_OK; + int ret; + A_UINT8 *tbuffer; + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device: 0x%p, buffer:0x%p\n", device, buffer)); + + do { + if (request & HIF_EXTENDED_IO) { + //AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Command type: CMD53\n")); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid command type: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + + if (request & HIF_BLOCK_BASIS) { + /* round to whole block length size */ + length = (length / HIF_MBOX_BLOCK_SIZE) * HIF_MBOX_BLOCK_SIZE; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Block mode (BlockLen: %d)\n", + length)); + } else if (request & HIF_BYTE_BASIS) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Byte mode (BlockLen: %d)\n", + length)); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid data mode: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + +#if 0 + /* useful for checking register accesses */ + if (length & 0x3) { + A_PRINTF(KERN_ALERT"AR6000: HIF (%s) is not a multiple of 4 bytes, addr:0x%X, len:%d\n", + request & HIF_WRITE ? "write":"read", address, length); + } +#endif + + if ((address >= HIF_MBOX_START_ADDR(0)) && + (address <= HIF_MBOX_END_ADDR(3))) + { + + AR_DEBUG_ASSERT(length <= HIF_MBOX_WIDTH); + + /* + * Mailbox write. Adjust the address so that the last byte + * falls on the EOM address. + */ + address += (HIF_MBOX_WIDTH - length); + } + + if (request & HIF_FIXED_ADDRESS) { + opcode = CMD53_FIXED_ADDRESS; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Address mode: Fixed 0x%X\n", address)); + } else if (request & HIF_INCREMENTAL_ADDRESS) { + opcode = CMD53_INCR_ADDRESS; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Address mode: Incremental 0x%X\n", address)); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid address mode: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + + if (request & HIF_WRITE) { +#if HIF_USE_DMA_BOUNCE_BUFFER + AR_DEBUG_ASSERT(device->dma_buffer != NULL); + tbuffer = device->dma_buffer; + /* copy the write data to the dma buffer */ + AR_DEBUG_ASSERT(length <= HIF_DMA_BUFFER_SIZE); + memcpy(tbuffer, buffer, length); +#else + tbuffer = buffer; +#endif + if (opcode == CMD53_FIXED_ADDRESS) { + ret = sdio_writesb(device->func, address, tbuffer, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: writesb ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } else { + ret = sdio_memcpy_toio(device->func, address, tbuffer, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: writeio ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } + } else if (request & HIF_READ) { +#if HIF_USE_DMA_BOUNCE_BUFFER + AR_DEBUG_ASSERT(device->dma_buffer != NULL); + AR_DEBUG_ASSERT(length <= HIF_DMA_BUFFER_SIZE); + tbuffer = device->dma_buffer; +#else + tbuffer = buffer; +#endif + if (opcode == CMD53_FIXED_ADDRESS) { + ret = sdio_readsb(device->func, tbuffer, address, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: readsb ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } else { + ret = sdio_memcpy_fromio(device->func, tbuffer, address, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: readio ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } +#if HIF_USE_DMA_BOUNCE_BUFFER + /* copy the read data from the dma buffer */ + memcpy(buffer, tbuffer, length); +#endif + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid direction: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + + if (ret) { + status = A_ERROR; + } + } while (FALSE); + + return status; +} + +/* queue a read/write request */ +A_STATUS +HIFReadWrite(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length, + A_UINT32 request, + void *context) +{ + A_STATUS status = A_OK; + unsigned long flags; + BUS_REQUEST *busrequest; + BUS_REQUEST *async; + BUS_REQUEST *active; + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device: %p\n", device)); + + do { + if ((request & HIF_ASYNCHRONOUS) || (request & HIF_SYNCHRONOUS)){ + /* serialize all requests through the async thread */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Execution mode: %s\n", (request & HIF_ASYNCHRONOUS)?"Async":"Synch")); + busrequest = hifAllocateBusRequest(device); + if (busrequest == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: no async bus requests available\n")); + return A_ERROR; + } + spin_lock_irqsave(&device->asynclock, flags); + busrequest->address = address; + busrequest->buffer = buffer; + busrequest->length = length; + busrequest->request = request; + busrequest->context = context; + /* add to async list */ + active = device->asyncreq; + if (active == NULL) { + device->asyncreq = busrequest; + device->asyncreq->inusenext = NULL; + } else { + for (async = device->asyncreq; + async != NULL; + async = async->inusenext) { + active = async; + } + active->inusenext = busrequest; + busrequest->inusenext = NULL; + } + spin_unlock_irqrestore(&device->asynclock, flags); + if (request & HIF_SYNCHRONOUS) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: queued sync req: 0x%X\n", (unsigned int)busrequest)); + + /* wait for completion */ + up(&device->sem_async); + if (down_interruptible(&busrequest->sem_req) != 0) { + /* interrupted, exit */ + return A_ERROR; + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: sync return freeing 0x%X: 0x%X\n", + (unsigned int)busrequest, busrequest->status)); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: freeing req: 0x%X\n", (unsigned int)request)); + hifFreeBusRequest(device, busrequest); + return busrequest->status; + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: queued async req: 0x%X\n", (unsigned int)busrequest)); + up(&device->sem_async); + return A_PENDING; + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid execution mode: 0x%08x\n", (unsigned int)request)); + status = A_EINVAL; + break; + } + } while(0); + + return status; +} + +/* LAB126: this starts off as 0, meaning that we haven't displayed the + * bad_hif_readwrite message. Once we display it a few times, we + * suppress further printouts, log avoid flooding the logs. + */ +static atomic_t showed_hif_readwrite_msg; + +/* thread to serialize all requests, both sync and async */ +static int async_task(void *param) + { + HIF_DEVICE *device; + BUS_REQUEST *request; + A_STATUS status; + unsigned long flags; + + device = (HIF_DEVICE *)param; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task\n")); + set_current_state(TASK_INTERRUPTIBLE); + while(!device->async_shutdown) { + /* wait for work */ + if (down_interruptible(&device->sem_async) != 0) { + /* interrupted, exit */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task interrupted\n")); + break; + } + if (device->async_shutdown) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task stopping\n")); + break; + } + /* we want to hold the host over multiple cmds if possible, but holding the host blocks card interrupts */ + sdio_claim_host(device->func); + spin_lock_irqsave(&device->asynclock, flags); + /* pull the request to work on */ + while (device->asyncreq != NULL) { + request = device->asyncreq; + if (request->inusenext != NULL) { + device->asyncreq = request->inusenext; + } else { + device->asyncreq = NULL; + } + spin_unlock_irqrestore(&device->asynclock, flags); + /* call HIFReadWrite in sync mode to do the work */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task processing req: 0x%X\n", (unsigned int)request)); + status = __HIFReadWrite(device, request->address, request->buffer, + request->length, request->request & ~HIF_SYNCHRONOUS, NULL); + if (status != A_OK) { + /* Lab126 addition */ + if (atomic_add_unless(&showed_hif_readwrite_msg, 1, 3)) { + printk(KERN_WARNING "ath6k: E async_task:" + "bad_hif_readwrite:__HIFReadWrite failed\n"); + } + } + if (request->request & HIF_ASYNCHRONOUS) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task completion routine req: 0x%X\n", (unsigned int)request)); + device->htcCallbacks.rwCompletionHandler(request->context, status); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task freeing req: 0x%X\n", (unsigned int)request)); + hifFreeBusRequest(device, request); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task upping req: 0x%X\n", (unsigned int)request)); + request->status = status; + up(&request->sem_req); + } + spin_lock_irqsave(&device->asynclock, flags); + } + spin_unlock_irqrestore(&device->asynclock, flags); + sdio_release_host(device->func); + } + + complete_and_exit(&device->async_completion, 0); + return 0; + } + +A_STATUS +HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode, + void *config, A_UINT32 configLen) +{ + A_UINT32 count; + + switch(opcode) { + case HIF_DEVICE_GET_MBOX_BLOCK_SIZE: + ((A_UINT32 *)config)[0] = HIF_MBOX0_BLOCK_SIZE; + ((A_UINT32 *)config)[1] = HIF_MBOX1_BLOCK_SIZE; + ((A_UINT32 *)config)[2] = HIF_MBOX2_BLOCK_SIZE; + ((A_UINT32 *)config)[3] = HIF_MBOX3_BLOCK_SIZE; + break; + + case HIF_DEVICE_GET_MBOX_ADDR: + for (count = 0; count < 4; count ++) { + ((A_UINT32 *)config)[count] = HIF_MBOX_START_ADDR(count); + } + break; + case HIF_DEVICE_GET_IRQ_PROC_MODE: + *((HIF_DEVICE_IRQ_PROCESSING_MODE *)config) = HIF_DEVICE_IRQ_SYNC_ONLY; + break; + default: + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, + ("AR6000: Unsupported configuration opcode: %d\n", opcode)); + return A_ERROR; + } + + return A_OK; +} + +void +HIFShutDownDevice(HIF_DEVICE *device) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +HIFShutDownDevice\n")); + if (device != NULL) { + AR_DEBUG_ASSERT(device->func != NULL); + } else { + /* since we are unloading the driver anyways, reset all cards in case the SDIO card + * is externally powered and we are unloading the SDIO stack. This avoids the problem when + * the SDIO stack is reloaded and attempts are made to re-enumerate a card that is already + * enumerated */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFShutDownDevice, resetting\n")); + ResetAllCards(); + + /* Unregister with bus driver core */ + if (registered) { + registered = 0; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Unregistering with the bus driver\n")); + sdio_unregister_driver(&ar6k_driver); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Unregistered\n")); + } + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -HIFShutDownDevice\n")); +} + +static void +hifIRQHandler(struct sdio_func *func) +{ + A_STATUS status; + HIF_DEVICE *device; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifIRQHandler\n")); + + device = getHifDevice(func); + /* release the host during ints so we can pick it back up when we process cmds */ + sdio_release_host(device->func); + status = device->htcCallbacks.dsrHandler(device->htcCallbacks.context); + sdio_claim_host(device->func); + AR_DEBUG_ASSERT(status == A_OK); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifIRQHandler\n")); +} + +/* handle HTC startup via thread*/ +static int startup_task(void *param) +{ + HIF_DEVICE *device; + + device = (HIF_DEVICE *)param; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: call HTC from startup_task\n")); + /* start up inform DRV layer */ + if ((osdrvCallbacks.deviceInsertedHandler(osdrvCallbacks.context,device)) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device rejected\n")); + } + return 0; +} + +static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id) +{ + int ret; + HIF_DEVICE * device; + int count; + struct task_struct* startup_task_struct; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: hifDeviceInserted, Function: 0x%X, Vendor ID: 0x%X, Device ID: 0x%X, block size: 0x%X/0x%X\n", + func->num, func->vendor, func->device, func->max_blksize, func->cur_blksize)); + + addHifDevice(func); + device = getHifDevice(func); + + spin_lock_init(&device->lock); + + spin_lock_init(&device->asynclock); + + /* enable the SDIO function */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: claim\n")); + sdio_claim_host(func); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: enable\n")); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + /* give us some time to enable, in ms */ + func->enable_timeout = 100; +#endif + + ret = sdio_enable_func(func); + if (ret) { + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to enable AR6K: 0x%X, timeout: %d\n", + __FUNCTION__, ret, func->enable_timeout)); +#else + + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to enable AR6K: 0x%X\n", + __FUNCTION__, ret)); +#endif + sdio_release_host(func); + return ret; + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: set block size 0x%X\n", HIF_MBOX_BLOCK_SIZE)); + ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE); + sdio_release_host(func); + if (ret) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to set block size 0x%x AR6K: 0x%X\n", + __FUNCTION__, HIF_MBOX_BLOCK_SIZE, ret)); + sdio_release_host(func); + return ret; + } + /* Initialize the bus requests to be used later */ + A_MEMZERO(device->busRequest, sizeof(device->busRequest)); + for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) { + sema_init(&device->busRequest[count].sem_req, 0); + hifFreeBusRequest(device, &device->busRequest[count]); + } + + /* create async I/O thread */ + device->async_shutdown = 0; + device->async_task = kthread_create(async_task, + (void *)device, + "AR6K Async"); + if (device->async_task == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create async task\n", __FUNCTION__)); + sdio_release_host(func); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start async task\n")); + sema_init(&device->sem_async, 0); + wake_up_process(device->async_task ); + + /* create startup thread */ + startup_task_struct = kthread_create(startup_task, + (void *)device, + "AR6K startup"); + if (startup_task_struct == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create startup task\n", __FUNCTION__)); + sdio_release_host(func); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start startup task\n")); + wake_up_process(startup_task_struct); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: return %d\n", ret)); + return ret; +} + + +void +HIFAckInterrupt(HIF_DEVICE *device) +{ + AR_DEBUG_ASSERT(device != NULL); + + /* Acknowledge our function IRQ */ +} + +void +HIFUnMaskInterrupt(HIF_DEVICE *device) +{ + int ret;; + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFUnMaskInterrupt\n")); + + /* Register the IRQ Handler */ + sdio_claim_host(device->func); + ret = sdio_claim_irq(device->func, hifIRQHandler); + sdio_release_host(device->func); + AR_DEBUG_ASSERT(ret == 0); +} + +void HIFMaskInterrupt(HIF_DEVICE *device) +{ + int ret;; + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFMaskInterrupt\n")); + + /* Mask our function IRQ */ + sdio_claim_host(device->func); + ret = sdio_release_irq(device->func); + sdio_release_host(device->func); + AR_DEBUG_ASSERT(ret == 0); +} + +static BUS_REQUEST *hifAllocateBusRequest(HIF_DEVICE *device) +{ + BUS_REQUEST *busrequest; + unsigned long flag; + + /* Acquire lock */ + spin_lock_irqsave(&device->lock, flag); + + /* Remove first in list */ + if((busrequest = device->s_busRequestFreeQueue) != NULL) + { + device->s_busRequestFreeQueue = busrequest->next; + } + + /* Release lock */ + spin_unlock_irqrestore(&device->lock, flag); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: hifAllocateBusRequest: 0x%p\n", busrequest)); + return busrequest; +} + +static void +hifFreeBusRequest(HIF_DEVICE *device, BUS_REQUEST *busrequest) +{ + unsigned long flag; + + AR_DEBUG_ASSERT(busrequest != NULL); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: hifFreeBusRequest: 0x%p\n", busrequest)); + /* Acquire lock */ + spin_lock_irqsave(&device->lock, flag); + + + /* Insert first in list */ + busrequest->next = device->s_busRequestFreeQueue; + busrequest->inusenext = NULL; + device->s_busRequestFreeQueue = busrequest; + + /* Release lock */ + spin_unlock_irqrestore(&device->lock, flag); +} + +static void hifDeviceRemoved(struct sdio_func *func) +{ + A_STATUS status = A_OK; + HIF_DEVICE *device; + int ret; + AR_DEBUG_ASSERT(func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDeviceRemoved\n")); + device = getHifDevice(func); + if (device->claimedContext != NULL) { + status = osdrvCallbacks.deviceRemovedHandler(device->claimedContext, device); + } + + if (device->async_task != NULL) { + init_completion(&device->async_completion); + device->async_shutdown = 1; + up(&device->sem_async); + wait_for_completion(&device->async_completion); + device->async_task = NULL; + } + /* Disable the card */ + sdio_claim_host(device->func); + ret = sdio_disable_func(device->func); + sdio_release_host(device->func); + delHifDevice(device); + AR_DEBUG_ASSERT(status == A_OK); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifDeviceRemoved\n")); +} + + +static HIF_DEVICE * +addHifDevice(struct sdio_func *func) +{ + HIF_DEVICE *hifdevice; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice\n")); + AR_DEBUG_ASSERT(func != NULL); + hifdevice = (HIF_DEVICE *)kzalloc(sizeof(HIF_DEVICE), GFP_KERNEL); + AR_DEBUG_ASSERT(hifdevice != NULL); +#if HIF_USE_DMA_BOUNCE_BUFFER + hifdevice->dma_buffer = kmalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL); + AR_DEBUG_ASSERT(hifdevice->dma_buffer != NULL); +#endif + hifdevice->func = func; + sdio_set_drvdata(func, hifdevice); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice; 0x%p\n", hifdevice)); + return hifdevice; +} + +static HIF_DEVICE * +getHifDevice(struct sdio_func *func) +{ + AR_DEBUG_ASSERT(func != NULL); + return (HIF_DEVICE *)sdio_get_drvdata(func); +} + +static void +delHifDevice(HIF_DEVICE * device) +{ + AR_DEBUG_ASSERT(device!= NULL); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: delHifDevice; 0x%p\n", device)); + if (device->dma_buffer != NULL) { + kfree(device->dma_buffer); + } + kfree(device); +} + +static void ResetAllCards(void) +{ +} + +void HIFClaimDevice(HIF_DEVICE *device, void *context) +{ + device->claimedContext = context; +} + +void HIFReleaseDevice(HIF_DEVICE *device) +{ + device->claimedContext = NULL; +} + +A_STATUS HIFAttachHTC(HIF_DEVICE *device, HTC_CALLBACKS *callbacks) +{ + if (device->htcCallbacks.context != NULL) { + /* already in use! */ + return A_ERROR; + } + device->htcCallbacks = *callbacks; + return A_OK; +} + +void HIFDetachHTC(HIF_DEVICE *device) +{ + A_MEMZERO(&device->htcCallbacks,sizeof(device->htcCallbacks)); +} + + + + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/hif.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/hif.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/hif.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/hif.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,323 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// HIF specific declarations and prototypes +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HIF_H_ +#define _HIF_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Header files */ +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" + + +typedef struct htc_callbacks HTC_CALLBACKS; +typedef struct hif_device HIF_DEVICE; + +/* + * direction - Direction of transfer (HIF_READ/HIF_WRITE). + */ +#define HIF_READ 0x00000001 +#define HIF_WRITE 0x00000002 +#define HIF_DIR_MASK (HIF_READ | HIF_WRITE) + +/* + * type - An interface may support different kind of read/write commands. + * For example: SDIO supports CMD52/CMD53s. In case of MSIO it + * translates to using different kinds of TPCs. The command type + * is thus divided into a basic and an extended command and can + * be specified using HIF_BASIC_IO/HIF_EXTENDED_IO. + */ +#define HIF_BASIC_IO 0x00000004 +#define HIF_EXTENDED_IO 0x00000008 +#define HIF_TYPE_MASK (HIF_BASIC_IO | HIF_EXTENDED_IO) + +/* + * emode - This indicates the whether the command is to be executed in a + * blocking or non-blocking fashion (HIF_SYNCHRONOUS/ + * HIF_ASYNCHRONOUS). The read/write data paths in HTC have been + * implemented using the asynchronous mode allowing the the bus + * driver to indicate the completion of operation through the + * registered callback routine. The requirement primarily comes + * from the contexts these operations get called from (a driver's + * transmit context or the ISR context in case of receive). + * Support for both of these modes is essential. + */ +#define HIF_SYNCHRONOUS 0x00000010 +#define HIF_ASYNCHRONOUS 0x00000020 +#define HIF_EMODE_MASK (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS) + +/* + * dmode - An interface may support different kinds of commands based on + * the tradeoff between the amount of data it can carry and the + * setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/ + * HIF_BLOCK_BASIS). In case of latter, the data is rounded off + * to the nearest block size by padding. The size of the block is + * configurable at compile time using the HIF_BLOCK_SIZE and is + * negotiated with the target during initialization after the + * AR6000 interrupts are enabled. + */ +#define HIF_BYTE_BASIS 0x00000040 +#define HIF_BLOCK_BASIS 0x00000080 +#define HIF_DMODE_MASK (HIF_BYTE_BASIS | HIF_BLOCK_BASIS) + +/* + * amode - This indicates if the address has to be incremented on AR6000 + * after every read/write operation (HIF?FIXED_ADDRESS/ + * HIF_INCREMENTAL_ADDRESS). + */ +#define HIF_FIXED_ADDRESS 0x00000100 +#define HIF_INCREMENTAL_ADDRESS 0x00000200 +#define HIF_AMODE_MASK (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS) + +#define HIF_WR_ASYNC_BYTE_FIX \ + (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_WR_ASYNC_BYTE_INC \ + (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_WR_ASYNC_BLOCK_INC \ + (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_WR_SYNC_BYTE_FIX \ + (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_WR_SYNC_BYTE_INC \ + (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_WR_SYNC_BLOCK_INC \ + (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_SYNC_BYTE_INC \ + (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_SYNC_BYTE_FIX \ + (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_RD_ASYNC_BYTE_FIX \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_RD_ASYNC_BLOCK_FIX \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS) +#define HIF_RD_ASYNC_BYTE_INC \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_ASYNC_BLOCK_INC \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_SYNC_BLOCK_INC \ + (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) + + +typedef enum { + HIF_DEVICE_POWER_STATE = 0, + HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + HIF_DEVICE_GET_MBOX_ADDR, + HIF_DEVICE_GET_PENDING_EVENTS_FUNC, + HIF_DEVICE_GET_IRQ_PROC_MODE, + HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC, + HIF_DEVICE_POWER_STATE_CHANGE, +} HIF_DEVICE_CONFIG_OPCODE; + +/* + * HIF CONFIGURE definitions: + * + * HIF_DEVICE_GET_MBOX_BLOCK_SIZE + * input : none + * output : array of 4 A_UINT32s + * notes: block size is returned for each mailbox (4) + * + * HIF_DEVICE_GET_MBOX_ADDR + * input : none + * output : array of 4 A_UINT32 + * notes: address is returned for each mailbox (4) in the array + * + * HIF_DEVICE_GET_PENDING_EVENTS_FUNC + * input : none + * output: HIF_PENDING_EVENTS_FUNC function pointer + * notes: this is optional for the HIF layer, if the request is + * not handled then it indicates that the upper layer can use + * the standard device methods to get pending events (IRQs, mailbox messages etc..) + * otherwise it can call the function pointer to check pending events. + * + * HIF_DEVICE_GET_IRQ_PROC_MODE + * input : none + * output : HIF_DEVICE_IRQ_PROCESSING_MODE (interrupt processing mode) + * note: the hif layer interfaces with the underlying OS-specific bus driver. The HIF + * layer can report whether IRQ processing is requires synchronous behavior or + * can be processed using asynchronous bus requests (typically faster). + * + * HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC + * input : + * output : HIF_MASK_UNMASK_RECV_EVENT function pointer + * notes: this is optional for the HIF layer. The HIF layer may require a special mechanism + * to mask receive message events. The upper layer can call this pointer when it needs + * to mask/unmask receive events (in case it runs out of buffers). + * + * HIF_DEVICE_POWER_STATE_CHANGE + * + * input : HIF_DEVICE_POWER_CHANGE_TYPE + * output : none + * note: this is optional for the HIF layer. The HIF layer can handle power on/off state change + * requests in an interconnect specific way. This is highly OS and bus driver dependent. + * The caller must guarantee that no HIF read/write requests will be made after the device + * is powered down. + * + * + * + */ + +typedef enum { + HIF_DEVICE_IRQ_SYNC_ONLY, /* for HIF implementations that require the DSR to process all + interrupts before returning */ + HIF_DEVICE_IRQ_ASYNC_SYNC, /* for HIF implementations that allow DSR to process interrupts + using ASYNC I/O (that is HIFAckInterrupt can be called at a + later time */ +} HIF_DEVICE_IRQ_PROCESSING_MODE; + +typedef enum { + HIF_DEVICE_POWER_UP, /* HIF layer should power up interface and/or module */ + HIF_DEVICE_POWER_DOWN, /* HIF layer should initiate bus-specific measures to minimize power */ + HIF_DEVICE_POWER_CUT /* HIF layer should initiate bus-specific AND/OR platform-specific measures + to completely power-off the module and associated hardware (i.e. cut power supplies) + */ +} HIF_DEVICE_POWER_CHANGE_TYPE; + +#define HIF_MAX_DEVICES 1 + +struct htc_callbacks { + void *context; /* context to pass to the dsrhandler + note : rwCompletionHandler is provided the context passed to HIFReadWrite */ + A_STATUS (* rwCompletionHandler)(void *rwContext, A_STATUS status); + A_STATUS (* dsrHandler)(void *context); +}; + +typedef struct osdrv_callbacks { + void *context; /* context to pass for all callbacks except deviceRemovedHandler + the deviceRemovedHandler is only called if the device is claimed */ + A_STATUS (* deviceInsertedHandler)(void *context, void *hif_handle); + A_STATUS (* deviceRemovedHandler)(void *claimedContext, void *hif_handle); + A_STATUS (* deviceSuspendHandler)(void *context); + A_STATUS (* deviceResumeHandler)(void *context); + A_STATUS (* deviceWakeupHandler)(void *context); +} OSDRV_CALLBACKS; + +#define HIF_OTHER_EVENTS (1 << 0) /* other interrupts (non-Recv) are pending, host + needs to read the register table to figure out what */ +#define HIF_RECV_MSG_AVAIL (1 << 1) /* pending recv packet */ + +typedef struct _HIF_PENDING_EVENTS_INFO { + A_UINT32 Events; + A_UINT32 LookAhead; + A_UINT32 AvailableRecvBytes; +} HIF_PENDING_EVENTS_INFO; + + /* function to get pending events , some HIF modules use special mechanisms + * to detect packet available and other interrupts */ +typedef A_STATUS ( *HIF_PENDING_EVENTS_FUNC)(HIF_DEVICE *device, + HIF_PENDING_EVENTS_INFO *pEvents, + void *AsyncContext); + +#define HIF_MASK_RECV TRUE +#define HIF_UNMASK_RECV FALSE + /* function to mask recv events */ +typedef A_STATUS ( *HIF_MASK_UNMASK_RECV_EVENT)(HIF_DEVICE *device, + A_BOOL Mask, + void *AsyncContext); + + +/* + * This API is used to perform any global initialization of the HIF layer + * and to set OS driver callbacks (i.e. insertion/removal) to the HIF layer + * + */ +A_STATUS HIFInit(OSDRV_CALLBACKS *callbacks); + +/* This API claims the HIF device and provides a context for handling removal. + * The device removal callback is only called when the OSDRV layer claims + * a device. The claimed context must be non-NULL */ +void HIFClaimDevice(HIF_DEVICE *device, void *claimedContext); +/* release the claimed device */ +void HIFReleaseDevice(HIF_DEVICE *device); + +/* This API allows the HTC layer to attach to the HIF device */ +A_STATUS HIFAttachHTC(HIF_DEVICE *device, HTC_CALLBACKS *callbacks); +/* This API detaches the HTC layer from the HIF device */ +void HIFDetachHTC(HIF_DEVICE *device); + +/* + * This API is used to provide the read/write interface over the specific bus + * interface. + * address - Starting address in the AR6000's address space. For mailbox + * writes, it refers to the start of the mbox boundary. It should + * be ensured that the last byte falls on the mailbox's EOM. For + * mailbox reads, it refers to the end of the mbox boundary. + * buffer - Pointer to the buffer containg the data to be transmitted or + * received. + * length - Amount of data to be transmitted or received. + * request - Characterizes the attributes of the command. + */ +A_STATUS +HIFReadWrite(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length, + A_UINT32 request, + void *context); + +/* + * This can be initiated from the unload driver context when the OSDRV layer has no more use for + * the device. + */ +void HIFShutDownDevice(HIF_DEVICE *device); + +/* + * This should translate to an acknowledgment to the bus driver indicating that + * the previous interrupt request has been serviced and the all the relevant + * sources have been cleared. HTC is ready to process more interrupts. + * This should prevent the bus driver from raising an interrupt unless the + * previous one has been serviced and acknowledged using the previous API. + */ +void HIFAckInterrupt(HIF_DEVICE *device); + +void HIFMaskInterrupt(HIF_DEVICE *device); + +void HIFUnMaskInterrupt(HIF_DEVICE *device); + +/* + * This set of functions are to be used by the bus driver to notify + * the HIF module about various events. + * These are not implemented if the bus driver provides an alternative + * way for this notification though callbacks for instance. + */ +int HIFInsertEventNotify(void); + +int HIFRemoveEventNotify(void); + +int HIFIRQEventNotify(void); + +int HIFRWCompleteEventNotify(void); + +A_STATUS +HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode, + void *config, A_UINT32 configLen); + +#ifdef __cplusplus +} +#endif + +#endif /* _HIF_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/hif_internal.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/hif_internal.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/hif_internal.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/hif_internal.h 2010-08-11 00:35:01.000000000 -0400 @@ -0,0 +1,90 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// internal header file for hif layer +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "hif.h" + +#define MANUFACTURER_ID_AR6001_BASE 0x100 +#define MANUFACTURER_ID_AR6002_BASE 0x200 +#define MANUFACTURER_ID_AR6003_BASE 0x300 +#define FUNCTION_CLASS 0x0 +#define MANUFACTURER_CODE 0x271 + +#define BUS_REQUEST_MAX_NUM 64 + +#define SDIO_CLOCK_FREQUENCY_DEFAULT 25000000 +#define SDWLAN_ENABLE_DISABLE_TIMEOUT 20 +#define FLAGS_CARD_ENAB 0x02 +#define FLAGS_CARD_IRQ_UNMSK 0x04 + +#define HIF_MBOX_BLOCK_SIZE 128 +#define HIF_MBOX_BASE_ADDR 0x800 +#define HIF_MBOX_WIDTH 0x800 +#define HIF_MBOX0_BLOCK_SIZE 1 +#define HIF_MBOX1_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE +#define HIF_MBOX2_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE +#define HIF_MBOX3_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE + +#define HIF_MBOX_START_ADDR(mbox) \ + HIF_MBOX_BASE_ADDR + mbox * HIF_MBOX_WIDTH + +#define HIF_MBOX_END_ADDR(mbox) \ + HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1 + +typedef struct bus_request { + struct bus_request *next; /* link list of available requests */ + struct bus_request *inusenext; /* link list of in use requests */ + struct semaphore sem_req; + A_UINT32 address; /* request data */ + A_UCHAR *buffer; + A_UINT32 length; + A_UINT32 request; + void *context; + A_STATUS status; +} BUS_REQUEST; + +struct hif_device { + struct sdio_func *func; + spinlock_t asynclock; + struct task_struct* async_task; /* task to handle async commands */ + struct semaphore sem_async; + int async_shutdown; /* stop the async task */ + struct completion async_completion; /* thread completion */ + BUS_REQUEST *asyncreq; /* request for async tasklet */ + BUS_REQUEST *taskreq; /* async tasklet data */ + spinlock_t lock; + BUS_REQUEST *s_busRequestFreeQueue; /* free list */ + BUS_REQUEST busRequest[BUS_REQUEST_MAX_NUM]; /* available bus requests */ + void *claimedContext; + HTC_CALLBACKS htcCallbacks; + A_UINT8 *dma_buffer; + wait_queue_head_t wait; +}; + +#define HIF_DMA_BUFFER_SIZE (32 * 1024) +#define CMD53_FIXED_ADDRESS 1 +#define CMD53_INCR_ADDRESS 2 diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/host_version.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/host_version.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/host_version.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/host_version.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains version information for the sample host driver for the +// AR6000 chip +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HOST_VERSION_H_ +#define _HOST_VERSION_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "AR6K_version.h" + +/* + * The version number is made up of major, minor, patch and build + * numbers. These are 16 bit numbers. The build and release script will + * set the build number using a Perforce counter. Here the build number is + * set to 9999 so that builds done without the build-release script are easily + * identifiable. + */ + +#define ATH_SW_VER_MAJOR __VER_MAJOR_ +#define ATH_SW_VER_MINOR __VER_MINOR_ +#define ATH_SW_VER_PATCH __VER_PATCH_ +#define ATH_SW_VER_BUILD __BUILD_NUMBER_ + +#ifdef __cplusplus +} +#endif + +#endif /* _HOST_VERSION_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/htc.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/htc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc.c 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,525 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + + +static void HTCReportFailure(void *Context, AR6K_TARGET_FAILURE_TYPE Type); + + +void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList) +{ + LOCK_HTC(target); + HTC_PACKET_ENQUEUE(pList,pPacket); + UNLOCK_HTC(target); +} + +HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList) +{ + HTC_PACKET *pPacket; + + LOCK_HTC(target); + pPacket = HTC_PACKET_DEQUEUE(pList); + UNLOCK_HTC(target); + + return pPacket; +} + +/* cleanup the HTC instance */ +static void HTCCleanup(HTC_TARGET *target) +{ + A_INT32 i; + + DevCleanup(&target->Device); + + for (i = 0;i < NUM_CONTROL_BUFFERS;i++) { + if (target->HTCControlBuffers[i].Buffer) { + A_FREE(target->HTCControlBuffers[i].Buffer); + } + } + + if (A_IS_MUTEX_VALID(&target->HTCLock)) { + A_MUTEX_DELETE(&target->HTCLock); + } + + if (A_IS_MUTEX_VALID(&target->HTCRxLock)) { + A_MUTEX_DELETE(&target->HTCRxLock); + } + + if (A_IS_MUTEX_VALID(&target->HTCTxLock)) { + A_MUTEX_DELETE(&target->HTCTxLock); + } + /* free our instance */ + A_FREE(target); +} + +/* registered target arrival callback from the HIF layer */ +HTC_HANDLE HTCCreate(void *hif_handle, HTC_INIT_INFO *pInfo) +{ + HTC_TARGET *target = NULL; + A_STATUS status = A_OK; + int i; + A_UINT32 ctrl_bufsz; + A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX]; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Enter\n")); + + do { + + /* allocate target memory */ + if ((target = (HTC_TARGET *)A_MALLOC(sizeof(HTC_TARGET))) == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n")); + status = A_ERROR; + break; + } + + A_MEMZERO(target, sizeof(HTC_TARGET)); + A_MUTEX_INIT(&target->HTCLock); + A_MUTEX_INIT(&target->HTCRxLock); + A_MUTEX_INIT(&target->HTCTxLock); + INIT_HTC_PACKET_QUEUE(&target->ControlBufferTXFreeList); + INIT_HTC_PACKET_QUEUE(&target->ControlBufferRXFreeList); + + /* give device layer the hif device handle */ + target->Device.HIFDevice = hif_handle; + /* give the device layer our context (for event processing) + * the device layer will register it's own context with HIF + * so we need to set this so we can fetch it in the target remove handler */ + target->Device.HTCContext = target; + /* set device layer target failure callback */ + target->Device.TargetFailureCallback = HTCReportFailure; + /* set device layer recv message pending callback */ + target->Device.MessagePendingCallback = HTCRecvMessagePendingHandler; + target->EpWaitingForBuffers = ENDPOINT_MAX; + + A_MEMCPY(&target->HTCInitInfo,pInfo,sizeof(HTC_INIT_INFO)); + + /* setup device layer */ + status = DevSetup(&target->Device); + + if (A_FAILED(status)) { + break; + } + + + /* get the block sizes */ + status = HIFConfigureDevice(hif_handle, HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + blocksizes, sizeof(blocksizes)); + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get block size info from HIF layer...\n")); + break; + } + + /* Set the control buffer size based on the block size */ + if (blocksizes[1] > HTC_MAX_CONTROL_MESSAGE_LENGTH) { + ctrl_bufsz = blocksizes[1] + HTC_HDR_LENGTH; + } else { + ctrl_bufsz = HTC_MAX_CONTROL_MESSAGE_LENGTH + HTC_HDR_LENGTH; + } + for (i = 0;i < NUM_CONTROL_BUFFERS;i++) { + target->HTCControlBuffers[i].Buffer = A_MALLOC(ctrl_bufsz); + if (target->HTCControlBuffers[i].Buffer == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n")); + status = A_ERROR; + break; + } + } + + if (A_FAILED(status)) { + break; + } + + /* carve up buffers/packets for control messages */ + for (i = 0; i < NUM_CONTROL_RX_BUFFERS; i++) { + HTC_PACKET *pControlPacket; + pControlPacket = &target->HTCControlBuffers[i].HtcPacket; + SET_HTC_PACKET_INFO_RX_REFILL(pControlPacket, + target, + target->HTCControlBuffers[i].Buffer, + ctrl_bufsz, + ENDPOINT_0); + HTC_FREE_CONTROL_RX(target,pControlPacket); + } + + for (;i < NUM_CONTROL_BUFFERS;i++) { + HTC_PACKET *pControlPacket; + pControlPacket = &target->HTCControlBuffers[i].HtcPacket; + INIT_HTC_PACKET_INFO(pControlPacket, + target->HTCControlBuffers[i].Buffer, + ctrl_bufsz); + HTC_FREE_CONTROL_TX(target,pControlPacket); + } + + } while (FALSE); + + if (A_FAILED(status)) { + if (target != NULL) { + HTCCleanup(target); + target = NULL; + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Exit\n")); + + return target; +} + +void HTCDestroy(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCDestroy .. Destroying :0x%X \n",(A_UINT32)target)); + HTCCleanup(target); + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCDestroy \n")); +} + +/* get the low level HIF device for the caller , the caller may wish to do low level + * HIF requests */ +void *HTCGetHifDevice(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + return target->Device.HIFDevice; +} + +/* wait for the target to arrive (sends HTC Ready message) + * this operation is fully synchronous and the message is polled for */ +A_STATUS HTCWaitTarget(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_STATUS status; + HTC_PACKET *pPacket = NULL; + HTC_READY_MSG *pRdyMsg; + HTC_SERVICE_CONNECT_REQ connect; + HTC_SERVICE_CONNECT_RESP resp; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Enter (target:0x%X) \n", (A_UINT32)target)); + + do { + +#ifdef MBOXHW_UNIT_TEST + + status = DoMboxHWTest(&target->Device); + + if (status != A_OK) { + break; + } + +#endif + + /* we should be getting 1 control message that the target is ready */ + status = HTCWaitforControlMessage(target, &pPacket); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Target Not Available!!\n")); + break; + } + + /* we controlled the buffer creation so it has to be properly aligned */ + pRdyMsg = (HTC_READY_MSG *)pPacket->pBuffer; + + if ((pRdyMsg->MessageID != HTC_MSG_READY_ID) || + (pPacket->ActualLength < sizeof(HTC_READY_MSG))) { + /* this message is not valid */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + if (pRdyMsg->CreditCount == 0 || pRdyMsg->CreditSize == 0) { + /* this message is not valid */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + target->TargetCredits = pRdyMsg->CreditCount; + target->TargetCreditSize = pRdyMsg->CreditSize; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" Target Ready: credits: %d credit size: %d\n", + target->TargetCredits, target->TargetCreditSize)); + + /* setup our pseudo HTC control endpoint connection */ + A_MEMZERO(&connect,sizeof(connect)); + A_MEMZERO(&resp,sizeof(resp)); + connect.EpCallbacks.pContext = target; + connect.EpCallbacks.EpTxComplete = HTCControlTxComplete; + connect.EpCallbacks.EpRecv = HTCControlRecv; + connect.EpCallbacks.EpRecvRefill = NULL; /* not needed */ + connect.EpCallbacks.EpSendFull = NULL; /* not nedded */ + connect.MaxSendQueueDepth = NUM_CONTROL_BUFFERS; + connect.ServiceID = HTC_CTRL_RSVD_SVC; + + /* connect fake service */ + status = HTCConnectService((HTC_HANDLE)target, + &connect, + &resp); + + if (!A_FAILED(status)) { + break; + } + + } while (FALSE); + + if (pPacket != NULL) { + HTC_FREE_CONTROL_RX(target,pPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Exit\n")); + + return status; +} + + + +/* Start HTC, enable interrupts and let the target know host has finished setup */ +A_STATUS HTCStart(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_PACKET *pPacket; + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Enter\n")); + + /* make sure interrupts are disabled at the chip level, + * this function can be called again from a reboot of the target without shutting down HTC */ + DevDisableInterrupts(&target->Device); + /* make sure state is cleared again */ + target->HTCStateFlags = 0; + + /* now that we are starting, push control receive buffers into the + * HTC control endpoint */ + + while (1) { + pPacket = HTC_ALLOC_CONTROL_RX(target); + if (NULL == pPacket) { + break; + } + HTCAddReceivePkt((HTC_HANDLE)target,pPacket); + } + + do { + + AR_DEBUG_ASSERT(target->InitCredits != NULL); + AR_DEBUG_ASSERT(target->EpCreditDistributionListHead != NULL); + AR_DEBUG_ASSERT(target->EpCreditDistributionListHead->pNext != NULL); + + /* call init credits callback to do the distribution , + * NOTE: the first entry in the distribution list is ENDPOINT_0, so + * we pass the start of the list after this one. */ + target->InitCredits(target->pCredDistContext, + target->EpCreditDistributionListHead->pNext, + target->TargetCredits); + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_TRC)) { + DumpCreditDistStates(target); + } + + /* the caller is done connecting to services, so we can indicate to the + * target that the setup phase is complete */ + status = HTCSendSetupComplete(target); + + if (A_FAILED(status)) { + break; + } + + /* unmask interrupts */ + status = DevUnmaskInterrupts(&target->Device); + + if (A_FAILED(status)) { + HTCStop(target); + } + + } while (FALSE); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Exit\n")); + return status; +} + +static void ResetEndpointStates(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + int i; + + for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) { + pEndpoint = &target->EndPoint[i]; + + A_MEMZERO(&pEndpoint->CreditDist, sizeof(pEndpoint->CreditDist)); + pEndpoint->ServiceID = 0; + pEndpoint->CurrentTxQueueDepth = 0; + pEndpoint->MaxMsgLength = 0; + pEndpoint->MaxTxQueueDepth = 0; +#ifdef HTC_EP_STAT_PROFILING + A_MEMZERO(&pEndpoint->EndPointStats,sizeof(pEndpoint->EndPointStats)); +#endif + INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBuffers); + INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue); + } + /* reset distribution list */ + target->EpCreditDistributionListHead = NULL; +} + +/* stop HTC communications, i.e. stop interrupt reception, and flush all queued buffers */ +void HTCStop(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCStop \n")); + + LOCK_HTC_RX(target); + /* mark that we are shutting down .. */ + target->HTCStateFlags |= HTC_STATE_STOPPING; + UNLOCK_HTC_RX(target); + + /* Masking interrupts is a synchronous operation, when this function returns + * all pending HIF I/O has completed, we can safely flush the queues */ + DevMaskInterrupts(&target->Device); + + /* flush all send packets */ + HTCFlushSendPkts(target); + /* flush all recv buffers */ + HTCFlushRecvBuffers(target); + + ResetEndpointStates(target); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCStop \n")); +} + +void HTCDumpCreditStates(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + + LOCK_HTC_TX(target); + + DumpCreditDistStates(target); + + UNLOCK_HTC_TX(target); +} + +/* report a target failure from the device, this is a callback from the device layer + * which uses a mechanism to report errors from the target (i.e. special interrupts) */ +static void HTCReportFailure(void *Context, AR6K_TARGET_FAILURE_TYPE Type) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + + target->TargetFailure = TRUE; + + switch (Type) { + + case AR6K_TARGET_TX_ERROR: + /* could be a credit problem */ + DumpCreditDistStates(target); + break; + case AR6K_TARGET_RX_ERROR: + + break; + case AR6K_TARGET_ASSERT: + if (target->HTCInitInfo.TargetFailure != NULL) { + /* let upper layer know, it needs to call HTCStop() */ + target->HTCInitInfo.TargetFailure(target->HTCInitInfo.pContext, A_ERROR); + } + break; + default: + break; + + } + +} + +void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription) +{ + A_CHAR stream[60]; + A_UINT32 i; + A_UINT16 offset, count; + + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("<---------Dumping %d Bytes : %s ------>\n", length, pDescription)); + + count = 0; + offset = 0; + for(i = 0; i < length; i++) { + A_SPRINTF(stream + offset, "%2.2X ", buffer[i]); + count ++; + offset += 3; + + if(count == 16) { + count = 0; + offset = 0; + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("[H]: %s\n", stream)); + A_MEMZERO(stream, 60); + } + } + + if(offset != 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("[H]: %s\n", stream)); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("<------------------------------------------------->\n")); +} + +A_BOOL HTCGetEndpointStatistics(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + HTC_ENDPOINT_STAT_ACTION Action, + HTC_ENDPOINT_STATS *pStats) +{ + +#ifdef HTC_EP_STAT_PROFILING + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_BOOL clearStats = FALSE; + A_BOOL sample = FALSE; + + switch (Action) { + case HTC_EP_STAT_SAMPLE : + sample = TRUE; + break; + case HTC_EP_STAT_SAMPLE_AND_CLEAR : + sample = TRUE; + clearStats = TRUE; + break; + case HTC_EP_STAT_CLEAR : + clearStats = TRUE; + break; + default: + break; + } + + A_ASSERT(Endpoint < ENDPOINT_MAX); + + /* lock out TX and RX while we sample and/or clear */ + LOCK_HTC_TX(target); + LOCK_HTC_RX(target); + + if (sample) { + A_ASSERT(pStats != NULL); + /* return the stats to the caller */ + A_MEMCPY(pStats, &target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS)); + } + + if (clearStats) { + /* reset stats */ + A_MEMZERO(&target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS)); + } + + UNLOCK_HTC_RX(target); + UNLOCK_HTC_TX(target); + + return TRUE; +#else + return FALSE; +#endif +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/htc.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/htc.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,204 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __HTC_H__ +#define __HTC_H__ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field)) + +#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \ + (((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)])) + +/* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a + * structure using only the type and field name. + * Use these macros if there is the potential for unaligned buffer accesses. */ +#define A_GET_UINT16_FIELD(p,type,field) \ + ASSEMBLE_UNALIGNED_UINT16(p,\ + A_OFFSETOF(type,field) + 1, \ + A_OFFSETOF(type,field)) + +#define A_SET_UINT16_FIELD(p,type,field,value) \ +{ \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (A_UINT8)(value); \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field) + 1] = (A_UINT8)((value) >> 8); \ +} + +#define A_GET_UINT8_FIELD(p,type,field) \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] + +#define A_SET_UINT8_FIELD(p,type,field,value) \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (value) + +/****** DANGER DANGER *************** + * + * The frame header length and message formats defined herein were + * selected to accommodate optimal alignment for target processing. This reduces code + * size and improves performance. + * + * Any changes to the header length may alter the alignment and cause exceptions + * on the target. When adding to the message structures insure that fields are + * properly aligned. + * + */ + +/* HTC frame header */ +typedef PREPACK struct _HTC_FRAME_HDR{ + /* do not remove or re-arrange these fields, these are minimally required + * to take advantage of 4-byte lookaheads in some hardware implementations */ + A_UINT8 EndpointID; + A_UINT8 Flags; + A_UINT16 PayloadLen; /* length of data (including trailer) that follows the header */ + + /***** end of 4-byte lookahead ****/ + + A_UINT8 ControlBytes[2]; + + /* message payload starts after the header */ + +} POSTPACK HTC_FRAME_HDR; + +/* frame header flags */ +#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0) +#define HTC_FLAGS_RECV_TRAILER (1 << 1) + + +#define HTC_HDR_LENGTH (sizeof(HTC_FRAME_HDR)) +#define HTC_MAX_TRAILER_LENGTH 255 +#define HTC_MAX_PAYLOAD_LENGTH (2048 - sizeof(HTC_FRAME_HDR)) + +/* HTC control message IDs */ +typedef enum { + HTC_MSG_READY_ID = 1, + HTC_MSG_CONNECT_SERVICE_ID = 2, + HTC_MSG_CONNECT_SERVICE_RESPONSE_ID = 3, + HTC_MSG_SETUP_COMPLETE_ID = 4, +} HTC_MSG_IDS; + +#define HTC_MAX_CONTROL_MESSAGE_LENGTH 256 + +/* base message ID header */ +typedef PREPACK struct { + A_UINT16 MessageID; +} POSTPACK HTC_UNKNOWN_MSG; + +/* HTC ready message + * direction : target-to-host */ +typedef PREPACK struct { + A_UINT16 MessageID; /* ID */ + A_UINT16 CreditCount; /* number of credits the target can offer */ + A_UINT16 CreditSize; /* size of each credit */ + A_UINT8 MaxEndpoints; /* maximum number of endpoints the target has resources for */ + A_UINT8 _Pad1; +} POSTPACK HTC_READY_MSG; + +#define HTC_SERVICE_META_DATA_MAX_LENGTH 128 + +/* connect service + * direction : host-to-target */ +typedef PREPACK struct { + A_UINT16 MessageID; + A_UINT16 ServiceID; /* service ID of the service to connect to */ + A_UINT16 ConnectionFlags; /* connection flags */ + +#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) /* reduce credit dribbling when + the host needs credits */ +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3) +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3 + + A_UINT8 ServiceMetaLength; /* length of meta data that follows */ + A_UINT8 _Pad1; + + /* service-specific meta data starts after the header */ + +} POSTPACK HTC_CONNECT_SERVICE_MSG; + +/* connect response + * direction : target-to-host */ +typedef PREPACK struct { + A_UINT16 MessageID; + A_UINT16 ServiceID; /* service ID that the connection request was made */ + A_UINT8 Status; /* service connection status */ + A_UINT8 EndpointID; /* assigned endpoint ID */ + A_UINT16 MaxMsgSize; /* maximum expected message size on this endpoint */ + A_UINT8 ServiceMetaLength; /* length of meta data that follows */ + A_UINT8 _Pad1; + + /* service-specific meta data starts after the header */ + +} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG; + +typedef PREPACK struct { + A_UINT16 MessageID; + /* currently, no other fields */ +} POSTPACK HTC_SETUP_COMPLETE_MSG; + + +/* connect response status codes */ +#define HTC_SERVICE_SUCCESS 0 /* success */ +#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */ +#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */ +#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */ +#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more + endpoints */ + +/* report record IDs */ +typedef enum { + HTC_RECORD_NULL = 0, + HTC_RECORD_CREDITS = 1, + HTC_RECORD_LOOKAHEAD = 2, +} HTC_RPT_IDS; + +typedef PREPACK struct { + A_UINT8 RecordID; /* Record ID */ + A_UINT8 Length; /* Length of record */ +} POSTPACK HTC_RECORD_HDR; + +typedef PREPACK struct { + A_UINT8 EndpointID; /* Endpoint that owns these credits */ + A_UINT8 Credits; /* credits to report since last report */ +} POSTPACK HTC_CREDIT_REPORT; + +typedef PREPACK struct { + A_UINT8 PreValid; /* pre valid guard */ + A_UINT8 LookAhead[4]; /* 4 byte lookahead */ + A_UINT8 PostValid; /* post valid guard */ + + /* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes. + * The PreValid bytes must equal the inverse of the PostValid byte */ + +} POSTPACK HTC_LOOKAHEAD_REPORT; + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + + +#endif /* __HTC_H__ */ + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/htc_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc_api.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/htc_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc_api.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,463 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HTC_API_H_ +#define _HTC_API_H_ + +#include "htc.h" +#include "htc_services.h" +#include "htc_packet.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* TODO.. for BMI */ +#define ENDPOINT1 0 +// TODO -remove me, but we have to fix BMI first +#define HTC_MAILBOX_NUM_MAX 4 + +/* this is the amount of header room required by users of HTC */ +#define HTC_HEADER_LEN HTC_HDR_LENGTH + +typedef void *HTC_HANDLE; + +typedef A_UINT16 HTC_SERVICE_ID; + +typedef struct _HTC_INIT_INFO { + void *pContext; /* context for target failure notification */ + void (*TargetFailure)(void *Instance, A_STATUS Status); +} HTC_INIT_INFO; + +/* per service connection send completion */ +typedef void (*HTC_EP_SEND_PKT_COMPLETE)(void *,HTC_PACKET *); +/* per service connection pkt received */ +typedef void (*HTC_EP_RECV_PKT)(void *,HTC_PACKET *); + +/* Optional per service connection receive buffer re-fill callback, + * On some OSes (like Linux) packets are allocated from a global pool and indicated up + * to the network stack. The driver never gets the packets back from the OS. For these OSes + * a refill callback can be used to allocate and re-queue buffers into HTC. + * + * On other OSes, the network stack can call into the driver's OS-specifc "return_packet" handler and + * the driver can re-queue these buffers into HTC. In this regard a refill callback is + * unnecessary */ +typedef void (*HTC_EP_RECV_REFILL)(void *, HTC_ENDPOINT_ID Endpoint); + +/* Optional per service connection receive buffer allocation callback. + * On some systems packet buffers are an extremely limited resource. Rather than + * queue largest-possible-sized buffers to HTC, some systems would rather + * allocate a specific size as the packet is received. The trade off is + * slightly more processing (callback invoked for each RX packet) + * for the benefit of committing fewer buffer resources into HTC. + * + * The callback is provided the length of the pending packet to fetch. This includes the + * HTC header length plus the length of payload. The callback can return a pointer to + * the allocated HTC packet for immediate use. + * + * NOTE*** This callback is mutually exclusive with the the refill callback above. + * + * */ +typedef HTC_PACKET *(*HTC_EP_RECV_ALLOC)(void *, HTC_ENDPOINT_ID Endpoint, int Length); + +typedef enum _HTC_SEND_FULL_ACTION { + HTC_SEND_FULL_KEEP = 0, /* packet that overflowed should be kept in the queue */ + HTC_SEND_FULL_DROP = 1, /* packet that overflowed should be dropped */ +} HTC_SEND_FULL_ACTION; + +/* Optional per service connection callback when a send queue is full. This can occur if the + * host continues queueing up TX packets faster than credits can arrive + * To prevent the host (on some Oses like Linux) from continuously queueing packets + * and consuming resources, this callback is provided so that that the host + * can disable TX in the subsystem (i.e. network stack). + * This callback is invoked for each packet that "overflows" the HTC queue. The callback can + * determine whether the new packet that overflowed the queue can be kept (HTC_SEND_FULL_KEEP) or + * dropped (HTC_SEND_FULL_DROP). If a packet is dropped, the EpTxComplete handler will be called + * and the packet's status field will be set to A_NO_RESOURCE. + * Other OSes require a "per-packet" indication for each completed TX packet, this + * closed loop mechanism will prevent the network stack from overunning the NIC + * The packet to keep or drop is passed for inspection to the registered handler the handler + * must ONLY inspect the packet, it may not free or reclaim the packet. */ +typedef HTC_SEND_FULL_ACTION (*HTC_EP_SEND_QUEUE_FULL)(void *, HTC_PACKET *pPacket); + +typedef struct _HTC_EP_CALLBACKS { + void *pContext; /* context for each callback */ + HTC_EP_SEND_PKT_COMPLETE EpTxComplete; /* tx completion callback for connected endpoint */ + HTC_EP_RECV_PKT EpRecv; /* receive callback for connected endpoint */ + HTC_EP_RECV_REFILL EpRecvRefill; /* OPTIONAL receive re-fill callback for connected endpoint */ + HTC_EP_SEND_QUEUE_FULL EpSendFull; /* OPTIONAL send full callback */ + HTC_EP_RECV_ALLOC EpRecvAlloc; /* OPTIONAL recv allocation callback */ +} HTC_EP_CALLBACKS; + +/* service connection information */ +typedef struct _HTC_SERVICE_CONNECT_REQ { + HTC_SERVICE_ID ServiceID; /* service ID to connect to */ + A_UINT16 ConnectionFlags; /* connection flags, see htc protocol definition */ + A_UINT8 *pMetaData; /* ptr to optional service-specific meta-data */ + A_UINT8 MetaDataLength; /* optional meta data length */ + HTC_EP_CALLBACKS EpCallbacks; /* endpoint callbacks */ + int MaxSendQueueDepth; /* maximum depth of any send queue */ +} HTC_SERVICE_CONNECT_REQ; + +/* service connection response information */ +typedef struct _HTC_SERVICE_CONNECT_RESP { + A_UINT8 *pMetaData; /* caller supplied buffer to optional meta-data */ + A_UINT8 BufferLength; /* length of caller supplied buffer */ + A_UINT8 ActualLength; /* actual length of meta data */ + HTC_ENDPOINT_ID Endpoint; /* endpoint to communicate over */ + int MaxMsgLength; /* max length of all messages over this endpoint */ + A_UINT8 ConnectRespCode; /* connect response code from target */ +} HTC_SERVICE_CONNECT_RESP; + +/* endpoint distribution structure */ +typedef struct _HTC_ENDPOINT_CREDIT_DIST { + struct _HTC_ENDPOINT_CREDIT_DIST *pNext; + struct _HTC_ENDPOINT_CREDIT_DIST *pPrev; + HTC_SERVICE_ID ServiceID; /* Service ID (set by HTC) */ + HTC_ENDPOINT_ID Endpoint; /* endpoint for this distribution struct (set by HTC) */ + A_UINT32 DistFlags; /* distribution flags, distribution function can + set default activity using SET_EP_ACTIVE() macro */ + int TxCreditsNorm; /* credits for normal operation, anything above this + indicates the endpoint is over-subscribed, this field + is only relevant to the credit distribution function */ + int TxCreditsMin; /* floor for credit distribution, this field is + only relevant to the credit distribution function */ + int TxCreditsAssigned; /* number of credits assigned to this EP, this field + is only relevant to the credit dist function */ + int TxCredits; /* current credits available, this field is used by + HTC to determine whether a message can be sent or + must be queued */ + int TxCreditsToDist; /* pending credits to distribute on this endpoint, this + is set by HTC when credit reports arrive. + The credit distribution functions sets this to zero + when it distributes the credits */ + int TxCreditsSeek; /* this is the number of credits that the current pending TX + packet needs to transmit. This is set by HTC when + and endpoint needs credits in order to transmit */ + int TxCreditSize; /* size in bytes of each credit (set by HTC) */ + int TxCreditsPerMaxMsg; /* credits required for a maximum sized messages (set by HTC) */ + void *pHTCReserved; /* reserved for HTC use */ + int TxQueueDepth; /* current depth of TX queue , i.e. messages waiting for credits + This field is valid only when HTC_CREDIT_DIST_ACTIVITY_CHANGE + or HTC_CREDIT_DIST_SEND_COMPLETE is indicated on an endpoint + that has non-zero credits to recover + */ +} HTC_ENDPOINT_CREDIT_DIST; + +#define HTC_EP_ACTIVE ((A_UINT32) (((A_UINT32) 1) << 31)) + +/* macro to check if an endpoint has gone active, useful for credit + * distributions */ +#define IS_EP_ACTIVE(epDist) ((epDist)->DistFlags & HTC_EP_ACTIVE) +#define SET_EP_ACTIVE(epDist) (epDist)->DistFlags |= HTC_EP_ACTIVE + + /* credit distibution code that is passed into the distrbution function, + * there are mandatory and optional codes that must be handled */ +typedef enum _HTC_CREDIT_DIST_REASON { + HTC_CREDIT_DIST_SEND_COMPLETE = 0, /* credits available as a result of completed + send operations (MANDATORY) resulting in credit reports */ + HTC_CREDIT_DIST_ACTIVITY_CHANGE = 1, /* a change in endpoint activity occured (OPTIONAL) */ + HTC_CREDIT_DIST_SEEK_CREDITS, /* an endpoint needs to "seek" credits (OPTIONAL) */ + HTC_DUMP_CREDIT_STATE /* for debugging, dump any state information that is kept by + the distribution function */ +} HTC_CREDIT_DIST_REASON; + +typedef void (*HTC_CREDIT_DIST_CALLBACK)(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + HTC_CREDIT_DIST_REASON Reason); + +typedef void (*HTC_CREDIT_INIT_CALLBACK)(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + int TotalCredits); + + /* endpoint statistics action */ +typedef enum _HTC_ENDPOINT_STAT_ACTION { + HTC_EP_STAT_SAMPLE = 0, /* only read statistics */ + HTC_EP_STAT_SAMPLE_AND_CLEAR = 1, /* sample and immediately clear statistics */ + HTC_EP_STAT_CLEAR /* clear only */ +} HTC_ENDPOINT_STAT_ACTION; + + /* endpoint statistics */ +typedef struct _HTC_ENDPOINT_STATS { + A_UINT32 TxCreditLowIndications; /* number of times the host set the credit-low flag in a send message on + this endpoint */ + A_UINT32 TxIssued; /* running count of TX packets issued */ + A_UINT32 TxDropped; /* tx packets that were dropped */ + A_UINT32 TxCreditRpts; /* running count of total credit reports received for this endpoint */ + A_UINT32 TxCreditRptsFromRx; /* credit reports received from this endpoint's RX packets */ + A_UINT32 TxCreditRptsFromOther; /* credit reports received from RX packets of other endpoints */ + A_UINT32 TxCreditRptsFromEp0; /* credit reports received from endpoint 0 RX packets */ + A_UINT32 TxCreditsFromRx; /* count of credits received via Rx packets on this endpoint */ + A_UINT32 TxCreditsFromOther; /* count of credits received via another endpoint */ + A_UINT32 TxCreditsFromEp0; /* count of credits received via another endpoint */ + A_UINT32 TxCreditsConsummed; /* count of consummed credits */ + A_UINT32 TxCreditsReturned; /* count of credits returned */ + A_UINT32 RxReceived; /* count of RX packets received */ + A_UINT32 RxLookAheads; /* count of lookahead records + found in messages received on this endpoint */ +} HTC_ENDPOINT_STATS; + +/* ------ Function Prototypes ------ */ +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Create an instance of HTC over the underlying HIF device + @function name: HTCCreate + @input: HifDevice - hif device handle, + pInfo - initialization information + @output: + @return: HTC_HANDLE on success, NULL on failure + @notes: + @example: + @see also: HTCDestroy ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +HTC_HANDLE HTCCreate(void *HifDevice, HTC_INIT_INFO *pInfo); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Get the underlying HIF device handle + @function name: HTCGetHifDevice + @input: HTCHandle - handle passed into the AddInstance callback + @output: + @return: opaque HIF device handle usable in HIF API calls. + @notes: + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void *HTCGetHifDevice(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Set credit distribution parameters + @function name: HTCSetCreditDistribution + @input: HTCHandle - HTC handle + pCreditDistCont - caller supplied context to pass into distribution functions + CreditDistFunc - Distribution function callback + CreditDistInit - Credit Distribution initialization callback + ServicePriorityOrder - Array containing list of service IDs, lowest index is highest + priority + ListLength - number of elements in ServicePriorityOrder + @output: + @return: + @notes: The user can set a custom credit distribution function to handle special requirements + for each endpoint. A default credit distribution routine can be used by setting + CreditInitFunc to NULL. The default credit distribution is only provided for simple + "fair" credit distribution without regard to any prioritization. + + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCSetCreditDistribution(HTC_HANDLE HTCHandle, + void *pCreditDistContext, + HTC_CREDIT_DIST_CALLBACK CreditDistFunc, + HTC_CREDIT_INIT_CALLBACK CreditInitFunc, + HTC_SERVICE_ID ServicePriorityOrder[], + int ListLength); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Wait for the target to indicate the HTC layer is ready + @function name: HTCWaitTarget + @input: HTCHandle - HTC handle + @output: + @return: + @notes: This API blocks until the target responds with an HTC ready message. + The caller should not connect services until the target has indicated it is + ready. + @example: + @see also: HTCConnectService ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCWaitTarget(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Start target service communications + @function name: HTCStart + @input: HTCHandle - HTC handle + @output: + @return: + @notes: This API indicates to the target that the service connection phase is complete + and the target can freely start all connected services. This API should only be + called AFTER all service connections have been made. TCStart will issue a + SETUP_COMPLETE message to the target to indicate that all service connections + have been made and the target can start communicating over the endpoints. + @example: + @see also: HTCConnectService ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCStart(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Add receive packet to HTC + @function name: HTCAddReceivePkt + @input: HTCHandle - HTC handle + pPacket - HTC receive packet to add + @output: + @return: A_OK on success + @notes: user must supply HTC packets for capturing incomming HTC frames. The caller + must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL() + macro. + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Connect to an HTC service + @function name: HTCConnectService + @input: HTCHandle - HTC handle + pReq - connection details + @output: pResp - connection response + @return: + @notes: Service connections must be performed before HTCStart. User provides callback handlers + for various endpoint events. + @example: + @see also: HTCStart ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCConnectService(HTC_HANDLE HTCHandle, + HTC_SERVICE_CONNECT_REQ *pReq, + HTC_SERVICE_CONNECT_RESP *pResp); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Send an HTC packet + @function name: HTCSendPkt + @input: HTCHandle - HTC handle + pPacket - packet to send + @output: + @return: A_OK + @notes: Caller must initialize packet using SET_HTC_PACKET_INFO_TX() macro. + This interface is fully asynchronous. On error, HTC SendPkt will + call the registered Endpoint callback to cleanup the packet. + @example: + @see also: HTCFlushEndpoint ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Stop HTC service communications + @function name: HTCStop + @input: HTCHandle - HTC handle + @output: + @return: + @notes: HTC communications is halted. All receive and pending TX packets will + be flushed. + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCStop(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Destory HTC service + @function name: HTCDestroy + @input: HTCHandle + @output: + @return: + @notes: This cleans up all resources allocated by HTCCreate(). + @example: + @see also: HTCCreate ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCDestroy(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Flush pending TX packets + @function name: HTCFlushEndpoint + @input: HTCHandle - HTC handle + Endpoint - Endpoint to flush + Tag - flush tag + @output: + @return: + @notes: The Tag parameter is used to selectively flush packets with matching tags. + The value of 0 forces all packets to be flush regardless of tag. + @example: + @see also: HTCSendPkt ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Dump credit distribution state + @function name: HTCDumpCreditStates + @input: HTCHandle - HTC handle + @output: + @return: + @notes: This dumps all credit distribution information to the debugger + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCDumpCreditStates(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Indicate a traffic activity change on an endpoint + @function name: HTCIndicateActivityChange + @input: HTCHandle - HTC handle + Endpoint - endpoint in which activity has changed + Active - TRUE if active, FALSE if it has become inactive + @output: + @return: + @notes: This triggers the registered credit distribution function to + re-adjust credits for active/inactive endpoints. + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCIndicateActivityChange(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + A_BOOL Active); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Get endpoint statistics + @function name: HTCGetEndpointStatistics + @input: HTCHandle - HTC handle + Endpoint - Endpoint identifier + Action - action to take with statistics + @output: + pStats - statistics that were sampled (can be NULL if Action is HTC_EP_STAT_CLEAR) + + @return: TRUE if statistics profiling is enabled, otherwise FALSE. + + @notes: Statistics is a compile-time option and this function may return FALSE + if HTC is not compiled with profiling. + + The caller can specify the statistic "action" to take when sampling + the statistics. This includes: + + HTC_EP_STAT_SAMPLE: The pStats structure is filled with the current values. + HTC_EP_STAT_SAMPLE_AND_CLEAR: The structure is filled and the current statistics + are cleared. + HTC_EP_STAT_CLEA : the statistics are cleared, the called can pass a NULL value for + pStats + + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_BOOL HTCGetEndpointStatistics(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + HTC_ENDPOINT_STAT_ACTION Action, + HTC_ENDPOINT_STATS *pStats); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Unblock HTC message reception + @function name: HTCUnblockRecv + @input: HTCHandle - HTC handle + @output: + @return: + @notes: + HTC will block the receiver if the EpRecvAlloc callback fails to provide a packet. + The caller can use this API to indicate to HTC when resources (buffers) are available + such that the receiver can be unblocked and HTC may re-attempt fetching the pending message. + + This API is not required if the user uses the EpRecvRefill callback or uses the HTCAddReceivePacket() + API to recycle or provide receive packets to HTC. + + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCUnblockRecv(HTC_HANDLE HTCHandle); + +/* internally used functions for testing... */ +void HTCEnableRecv(HTC_HANDLE HTCHandle); +void HTCDisableRecv(HTC_HANDLE HTCHandle); + +#ifdef __cplusplus +} +#endif + +#endif /* _HTC_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/htc_debug.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc_debug.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/htc_debug.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc_debug.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,69 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef HTC_DEBUG_H_ +#define HTC_DEBUG_H_ + +/* ------- Debug related stuff ------- */ +enum { + ATH_DEBUG_SEND = 0x0001, + ATH_DEBUG_RECV = 0x0002, + ATH_DEBUG_SYNC = 0x0004, + ATH_DEBUG_DUMP = 0x0008, + ATH_DEBUG_IRQ = 0x0010, + ATH_DEBUG_TRC = 0x0020, + ATH_DEBUG_WARN = 0x0040, + ATH_DEBUG_ERR = 0x0080, + ATH_DEBUG_ANY = 0xFFFF, +}; + +#ifdef DEBUG + +// TODO FIX usage of A_PRINTF! +#define AR_DEBUG_LVL_CHECK(lvl) (debughtc & (lvl)) +#define AR_DEBUG_PRINTBUF(buffer, length, desc) do { \ + if (debughtc & ATH_DEBUG_DUMP) { \ + DebugDumpBytes(buffer, length,desc); \ + } \ +} while(0) +#define PRINTX_ARG(arg...) arg +#define AR_DEBUG_PRINTF(flags, args) do { \ + if (debughtc & (flags)) { \ + A_PRINTF(KERN_ALERT PRINTX_ARG args); \ + } \ +} while (0) +//#define AR_DEBUG_ASSERT(test) do { \ + //if (!(test)) { \ + //AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test)); \ + //} \ +//} while(0) +extern int debughtc; +#else +#define AR_DEBUG_PRINTF(flags, args) +#define AR_DEBUG_PRINTBUF(buffer, length, desc) +#define AR_DEBUG_ASSERT(test) +#define AR_DEBUG_LVL_CHECK(lvl) 0 +#endif + +void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription); + +#endif /*HTC_DEBUG_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/htc_internal.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc_internal.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/htc_internal.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc_internal.h 2010-08-11 00:35:01.000000000 -0400 @@ -0,0 +1,179 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HTC_INTERNAL_H_ +#define _HTC_INTERNAL_H_ + +/* for debugging, uncomment this to capture the last frame header, on frame header + * processing errors, the last frame header is dump for comparison */ +//#define HTC_CAPTURE_LAST_FRAME + +//#define HTC_EP_STAT_PROFILING + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Header files */ +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "a_debug.h" +#include "htc.h" +#include "htc_api.h" +#include "bmi_msg.h" +#include "hif.h" +#include "ar6k.h" + +/* HTC operational parameters */ +#define HTC_TARGET_RESPONSE_TIMEOUT 2000 /* in ms */ +#define HTC_TARGET_DEBUG_INTR_MASK 0x01 +#define HTC_TARGET_CREDIT_INTR_MASK 0xF0 + +typedef struct _HTC_ENDPOINT { + HTC_SERVICE_ID ServiceID; /* service ID this endpoint is bound to + non-zero value means this endpoint is in use */ + HTC_PACKET_QUEUE TxQueue; /* HTC frame buffer TX queue */ + HTC_PACKET_QUEUE RxBuffers; /* HTC frame buffer RX list */ + HTC_ENDPOINT_CREDIT_DIST CreditDist; /* credit distribution structure (exposed to driver layer) */ + HTC_EP_CALLBACKS EpCallBacks; /* callbacks associated with this endpoint */ + int MaxTxQueueDepth; /* max depth of the TX queue before we need to + call driver's full handler */ + int CurrentTxQueueDepth; /* current TX queue depth */ + int MaxMsgLength; /* max length of endpoint message */ +#ifdef HTC_EP_STAT_PROFILING + HTC_ENDPOINT_STATS EndPointStats; /* endpoint statistics */ +#endif + int TxProcessCount; +} HTC_ENDPOINT; + +#ifdef HTC_EP_STAT_PROFILING +#define INC_HTC_EP_STAT(p,stat,count) (p)->EndPointStats.stat += (count); +#else +#define INC_HTC_EP_STAT(p,stat,count) +#endif + +#define HTC_SERVICE_TX_PACKET_TAG HTC_TX_PACKET_TAG_INTERNAL + +#define NUM_CONTROL_BUFFERS 8 +#define NUM_CONTROL_TX_BUFFERS 2 +#define NUM_CONTROL_RX_BUFFERS (NUM_CONTROL_BUFFERS - NUM_CONTROL_TX_BUFFERS) + +typedef struct HTC_CONTROL_BUFFER { + HTC_PACKET HtcPacket; + A_UINT8 *Buffer; +} HTC_CONTROL_BUFFER; + +/* our HTC target state */ +typedef struct _HTC_TARGET { + HTC_ENDPOINT EndPoint[ENDPOINT_MAX]; + HTC_CONTROL_BUFFER HTCControlBuffers[NUM_CONTROL_BUFFERS]; + HTC_ENDPOINT_CREDIT_DIST *EpCreditDistributionListHead; + HTC_PACKET_QUEUE ControlBufferTXFreeList; + HTC_PACKET_QUEUE ControlBufferRXFreeList; + HTC_CREDIT_DIST_CALLBACK DistributeCredits; + HTC_CREDIT_INIT_CALLBACK InitCredits; + void *pCredDistContext; + int TargetCredits; + int TargetCreditSize; + /* LAB126: changed A_MUTEX_T (spinlock) to raw_spinlock_t */ + spinlock_t HTCLock; + spinlock_t HTCRxLock; + spinlock_t HTCTxLock; + + AR6K_DEVICE Device; /* AR6K - specific state */ + A_UINT32 HTCStateFlags; + HTC_ENDPOINT_ID EpWaitingForBuffers; + A_BOOL TargetFailure; +#define HTC_STATE_WAIT_BUFFERS (1 << 0) +#define HTC_STATE_STOPPING (1 << 1) +#ifdef HTC_CAPTURE_LAST_FRAME + HTC_FRAME_HDR LastFrameHdr; /* useful for debugging */ + A_UINT8 LastTrailer[256]; + A_UINT8 LastTrailerLength; +#endif + HTC_INIT_INFO HTCInitInfo; +} HTC_TARGET; + +#define HTC_STOPPING(t) ((t)->HTCStateFlags & HTC_STATE_STOPPING) +#define LOCK_HTC(t) A_MUTEX_LOCK(&(t)->HTCLock); +#define UNLOCK_HTC(t) A_MUTEX_UNLOCK(&(t)->HTCLock); +#define LOCK_HTC_RX(t) A_MUTEX_LOCK(&(t)->HTCRxLock); +#define UNLOCK_HTC_RX(t) A_MUTEX_UNLOCK(&(t)->HTCRxLock); +#define LOCK_HTC_TX(t) A_MUTEX_LOCK(&(t)->HTCTxLock); +#define UNLOCK_HTC_TX(t) A_MUTEX_UNLOCK(&(t)->HTCTxLock); + +#define GET_HTC_TARGET_FROM_HANDLE(hnd) ((HTC_TARGET *)(hnd)) +#define HTC_RECYCLE_RX_PKT(target,p,e) \ +{ \ + if ((e)->EpCallBacks.EpRecvAlloc != NULL) { \ + HTC_PACKET_RESET_RX(pPacket); \ + pPacket->Status = A_ECANCELED; \ + (e)->EpCallBacks.EpRecv((e)->EpCallBacks.pContext, \ + (p)); \ + } else { \ + HTC_PACKET_RESET_RX(pPacket); \ + HTCAddReceivePkt((HTC_HANDLE)(target),(p)); \ + } \ +} + +/* internal HTC functions */ +void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket); +void HTCControlRecv(void *Context, HTC_PACKET *pPacket); +A_STATUS HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket); +HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList); +void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList); +A_STATUS HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT8 Flags); +A_STATUS HTCIssueRecv(HTC_TARGET *target, HTC_PACKET *pPacket); +void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket); +A_STATUS HTCRecvMessagePendingHandler(void *Context, A_UINT32* LookAhead, A_BOOL *pAsyncProc); +void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint); +A_STATUS HTCSendSetupComplete(HTC_TARGET *target); +void HTCFlushRecvBuffers(HTC_TARGET *target); +void HTCFlushSendPkts(HTC_TARGET *target); +void DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist); +void DumpCreditDistStates(HTC_TARGET *target); +void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription); + +static INLINE HTC_PACKET *HTC_ALLOC_CONTROL_TX(HTC_TARGET *target) { + HTC_PACKET *pPacket = HTCAllocControlBuffer(target,&target->ControlBufferTXFreeList); + if (pPacket != NULL) { + /* set payload pointer area with some headroom */ + pPacket->pBuffer = pPacket->pBufferStart + HTC_HDR_LENGTH; + } + return pPacket; +} + +#define HTC_FREE_CONTROL_TX(t,p) HTCFreeControlBuffer((t),(p),&(t)->ControlBufferTXFreeList) +#define HTC_ALLOC_CONTROL_RX(t) HTCAllocControlBuffer((t),&(t)->ControlBufferRXFreeList) +#define HTC_FREE_CONTROL_RX(t,p) \ +{ \ + HTC_PACKET_RESET_RX(p); \ + HTCFreeControlBuffer((t),(p),&(t)->ControlBufferRXFreeList); \ +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HTC_INTERNAL_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/htc_packet.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc_packet.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/htc_packet.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc_packet.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,162 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef HTC_PACKET_H_ +#define HTC_PACKET_H_ + + +#include "dl_list.h" + +/* ------ Endpoint IDS ------ */ +typedef enum +{ + ENDPOINT_UNUSED = -1, + ENDPOINT_0 = 0, + ENDPOINT_1 = 1, + ENDPOINT_2 = 2, + ENDPOINT_3, + ENDPOINT_4, + ENDPOINT_5, + ENDPOINT_6, + ENDPOINT_7, + ENDPOINT_8, + ENDPOINT_MAX, +} HTC_ENDPOINT_ID; + +struct _HTC_PACKET; + +typedef void (* HTC_PACKET_COMPLETION)(void *,struct _HTC_PACKET *); + +typedef A_UINT16 HTC_TX_TAG; + +typedef struct _HTC_TX_PACKET_INFO { + HTC_TX_TAG Tag; /* tag used to selective flush packets */ +} HTC_TX_PACKET_INFO; + +#define HTC_TX_PACKET_TAG_ALL 0 /* a tag of zero is reserved and used to flush ALL packets */ +#define HTC_TX_PACKET_TAG_INTERNAL 1 /* internal tags start here */ +#define HTC_TX_PACKET_TAG_USER_DEFINED (HTC_TX_PACKET_TAG_INTERNAL + 9) /* user-defined tags start here */ + +typedef struct _HTC_RX_PACKET_INFO { + A_UINT32 IndicationFlags; +} HTC_RX_PACKET_INFO; + +#define HTC_RX_FLAGS_INDICATE_MORE_PKTS (1 << 0) + +/* wrapper around endpoint-specific packets */ +typedef struct _HTC_PACKET { + DL_LIST ListLink; /* double link */ + void *pPktContext; /* caller's per packet specific context */ + + A_UINT8 *pBufferStart; /* the true buffer start , the caller can + store the real buffer start here. In + receive callbacks, the HTC layer sets pBuffer + to the start of the payload past the header. This + field allows the caller to reset pBuffer when it + recycles receive packets back to HTC */ + /* + * Pointer to the start of the buffer. In the transmit + * direction this points to the start of the payload. In the + * receive direction, however, the buffer when queued up + * points to the start of the HTC header but when returned + * to the caller points to the start of the payload + */ + A_UINT8 *pBuffer; /* payload start (RX/TX) */ + A_UINT32 BufferLength; /* length of buffer */ + A_UINT32 ActualLength; /* actual length of payload */ + HTC_ENDPOINT_ID Endpoint; /* endpoint that this packet was sent/recv'd from */ + A_STATUS Status; /* completion status */ + union { + HTC_TX_PACKET_INFO AsTx; /* Tx Packet specific info */ + HTC_RX_PACKET_INFO AsRx; /* Rx Packet specific info */ + } PktInfo; + + /* the following fields are for internal HTC use */ + HTC_PACKET_COMPLETION Completion; /* completion */ + void *pContext; /* HTC private completion context */ + A_UINT32 HTCReserved; /* reserved */ +} HTC_PACKET; + + + +#define COMPLETE_HTC_PACKET(p,status) \ +{ \ + (p)->Status = (status); \ + (p)->Completion((p)->pContext,(p)); \ +} + +#define INIT_HTC_PACKET_INFO(p,b,len) \ +{ \ + (p)->pBufferStart = (b); \ + (p)->BufferLength = (len); \ +} + +/* macro to set an initial RX packet for refilling HTC */ +#define SET_HTC_PACKET_INFO_RX_REFILL(p,c,b,len,ep) \ +{ \ + (p)->pPktContext = (c); \ + (p)->pBuffer = (b); \ + (p)->pBufferStart = (b); \ + (p)->BufferLength = (len); \ + (p)->Endpoint = (ep); \ +} + +/* fast macro to recycle an RX packet that will be re-queued to HTC */ +#define HTC_PACKET_RESET_RX(p) \ + (p)->pBuffer = (p)->pBufferStart + +/* macro to set packet parameters for TX */ +#define SET_HTC_PACKET_INFO_TX(p,c,b,len,ep,tag) \ +{ \ + (p)->pPktContext = (c); \ + (p)->pBuffer = (b); \ + (p)->ActualLength = (len); \ + (p)->Endpoint = (ep); \ + (p)->PktInfo.AsTx.Tag = (tag); \ +} + +/* HTC Packet Queueing Macros */ +typedef DL_LIST HTC_PACKET_QUEUE; +/* initialize queue */ +#define INIT_HTC_PACKET_QUEUE(pQ) DL_LIST_INIT((pQ)) +/* enqueue HTC packet to the tail of the queue */ +#define HTC_PACKET_ENQUEUE(pQ,p) DL_ListInsertTail((pQ),&(p)->ListLink) +/* test if a queue is empty */ +#define HTC_QUEUE_EMPTY(pQ) DL_LIST_IS_EMPTY((pQ)) +/* get packet at head without removing it */ +#define HTC_GET_PKT_AT_HEAD(pQ) A_CONTAINING_STRUCT((DL_LIST_GET_ITEM_AT_HEAD(pQ)),HTC_PACKET,ListLink); +/* remove a packet from the current list it is linked to */ +#define HTC_PACKET_REMOVE(p) DL_ListRemove(&(p)->ListLink) + +/* dequeue an HTC packet from the head of the queue */ +static INLINE HTC_PACKET *HTC_PACKET_DEQUEUE(HTC_PACKET_QUEUE *queue) { + DL_LIST *pItem = DL_ListRemoveItemFromHead(queue); + if (pItem != NULL) { + return A_CONTAINING_STRUCT(pItem, HTC_PACKET, ListLink); + } + return NULL; +} + +#define HTC_GET_ENDPOINT_FROM_PKT(p) (p)->Endpoint +#define HTC_GET_TAG_FROM_PKT(p) (p)->PktInfo.AsTx.Tag + +#endif /*HTC_PACKET_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/htc_recv.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc_recv.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/htc_recv.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc_recv.c 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,785 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + +#define HTCIssueRecv(t, p) \ + DevRecvPacket(&(t)->Device, \ + (p), \ + (p)->ActualLength) + +#define DO_RCV_COMPLETION(t,p,e) \ +{ \ + if ((p)->ActualLength > 0) { \ + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" completing packet 0x%X (%d bytes) on ep : %d \n", \ + (A_UINT32)(p), (p)->ActualLength, (p)->Endpoint)); \ + (e)->EpCallBacks.EpRecv((e)->EpCallBacks.pContext, \ + (p)); \ + } else { \ + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" recycling empty packet \n")); \ + HTC_RECYCLE_RX_PKT((t), (p), (e)); \ + } \ +} + +#ifdef HTC_EP_STAT_PROFILING +#define HTC_RX_STAT_PROFILE(t,ep,lookAhead) \ +{ \ + LOCK_HTC_RX((t)); \ + INC_HTC_EP_STAT((ep), RxReceived, 1); \ + if ((lookAhead) != 0) { \ + INC_HTC_EP_STAT((ep), RxLookAheads, 1); \ + } \ + UNLOCK_HTC_RX((t)); \ +} +#else +#define HTC_RX_STAT_PROFILE(t,ep,lookAhead) +#endif + +static INLINE A_STATUS HTCProcessTrailer(HTC_TARGET *target, + A_UINT8 *pBuffer, + int Length, + A_UINT32 *pNextLookAhead, + HTC_ENDPOINT_ID FromEndpoint) +{ + HTC_RECORD_HDR *pRecord; + A_UINT8 *pRecordBuf; + HTC_LOOKAHEAD_REPORT *pLookAhead; + A_UINT8 *pOrigBuffer; + int origLength; + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessTrailer (length:%d) \n", Length)); + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + AR_DEBUG_PRINTBUF(pBuffer,Length,"Recv Trailer"); + } + + pOrigBuffer = pBuffer; + origLength = Length; + status = A_OK; + + while (Length > 0) { + + if (Length < sizeof(HTC_RECORD_HDR)) { + status = A_EPROTO; + break; + } + /* these are byte aligned structs */ + pRecord = (HTC_RECORD_HDR *)pBuffer; + Length -= sizeof(HTC_RECORD_HDR); + pBuffer += sizeof(HTC_RECORD_HDR); + + if (pRecord->Length > Length) { + /* no room left in buffer for record */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" invalid record length: %d (id:%d) buffer has: %d bytes left \n", + pRecord->Length, pRecord->RecordID, Length)); + status = A_EPROTO; + break; + } + /* start of record follows the header */ + pRecordBuf = pBuffer; + + switch (pRecord->RecordID) { + case HTC_RECORD_CREDITS: + AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_CREDIT_REPORT)); + HTCProcessCreditRpt(target, + (HTC_CREDIT_REPORT *)pRecordBuf, + pRecord->Length / (sizeof(HTC_CREDIT_REPORT)), + FromEndpoint); + break; + case HTC_RECORD_LOOKAHEAD: + AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_LOOKAHEAD_REPORT)); + pLookAhead = (HTC_LOOKAHEAD_REPORT *)pRecordBuf; + if ((pLookAhead->PreValid == ((~pLookAhead->PostValid) & 0xFF)) && + (pNextLookAhead != NULL)) { + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + (" LookAhead Report Found (pre valid:0x%X, post valid:0x%X) \n", + pLookAhead->PreValid, + pLookAhead->PostValid)); + + /* look ahead bytes are valid, copy them over */ + ((A_UINT8 *)pNextLookAhead)[0] = pLookAhead->LookAhead[0]; + ((A_UINT8 *)pNextLookAhead)[1] = pLookAhead->LookAhead[1]; + ((A_UINT8 *)pNextLookAhead)[2] = pLookAhead->LookAhead[2]; + ((A_UINT8 *)pNextLookAhead)[3] = pLookAhead->LookAhead[3]; + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + DebugDumpBytes((A_UINT8 *)pNextLookAhead,4,"Next Look Ahead"); + } + } + break; + default: + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" unhandled record: id:%d length:%d \n", + pRecord->RecordID, pRecord->Length)); + break; + } + + if (A_FAILED(status)) { + break; + } + + /* advance buffer past this record for next time around */ + pBuffer += pRecord->Length; + Length -= pRecord->Length; + } + + if (A_FAILED(status)) { + DebugDumpBytes(pOrigBuffer,origLength,"BAD Recv Trailer"); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessTrailer \n")); + return status; + +} + +/* process a received message (i.e. strip off header, process any trailer data) + * note : locks must be released when this function is called */ +static A_STATUS HTCProcessRecvHeader(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT32 *pNextLookAhead) +{ + A_UINT8 temp; + A_UINT8 *pBuf; + A_STATUS status = A_OK; + A_UINT16 payloadLen; + A_UINT32 lookAhead; + + pBuf = pPacket->pBuffer; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessRecvHeader \n")); + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + AR_DEBUG_PRINTBUF(pBuf,pPacket->ActualLength,"HTC Recv PKT"); + } + + do { + /* note, we cannot assume the alignment of pBuffer, so we use the safe macros to + * retrieve 16 bit fields */ + payloadLen = A_GET_UINT16_FIELD(pBuf, HTC_FRAME_HDR, PayloadLen); + + ((A_UINT8 *)&lookAhead)[0] = pBuf[0]; + ((A_UINT8 *)&lookAhead)[1] = pBuf[1]; + ((A_UINT8 *)&lookAhead)[2] = pBuf[2]; + ((A_UINT8 *)&lookAhead)[3] = pBuf[3]; + + if (lookAhead != pPacket->HTCReserved) { + /* somehow the lookahead that gave us the full read length did not + * reflect the actual header in the pending message */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCProcessRecvHeader, lookahead mismatch! \n")); + DebugDumpBytes((A_UINT8 *)&pPacket->HTCReserved,4,"Expected Message LookAhead"); + DebugDumpBytes(pBuf,sizeof(HTC_FRAME_HDR),"Current Frame Header"); +#ifdef HTC_CAPTURE_LAST_FRAME + DebugDumpBytes((A_UINT8 *)&target->LastFrameHdr,sizeof(HTC_FRAME_HDR),"Last Frame Header"); + if (target->LastTrailerLength != 0) { + DebugDumpBytes(target->LastTrailer, + target->LastTrailerLength, + "Last trailer"); + } +#endif + status = A_EPROTO; + break; + } + + /* get flags */ + temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, Flags); + + if (temp & HTC_FLAGS_RECV_TRAILER) { + /* this packet has a trailer */ + + /* extract the trailer length in control byte 0 */ + temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, ControlBytes[0]); + + if ((temp < sizeof(HTC_RECORD_HDR)) || (temp > payloadLen)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCProcessRecvHeader, invalid header (payloadlength should be :%d, CB[0] is:%d) \n", + payloadLen, temp)); + status = A_EPROTO; + break; + } + + /* process trailer data that follows HDR + application payload */ + status = HTCProcessTrailer(target, + (pBuf + HTC_HDR_LENGTH + payloadLen - temp), + temp, + pNextLookAhead, + pPacket->Endpoint); + + if (A_FAILED(status)) { + break; + } + +#ifdef HTC_CAPTURE_LAST_FRAME + A_MEMCPY(target->LastTrailer, (pBuf + HTC_HDR_LENGTH + payloadLen - temp), temp); + target->LastTrailerLength = temp; +#endif + /* trim length by trailer bytes */ + pPacket->ActualLength -= temp; + } +#ifdef HTC_CAPTURE_LAST_FRAME + else { + target->LastTrailerLength = 0; + } +#endif + + /* if we get to this point, the packet is good */ + /* remove header and adjust length */ + pPacket->pBuffer += HTC_HDR_LENGTH; + pPacket->ActualLength -= HTC_HDR_LENGTH; + + } while (FALSE); + + if (A_FAILED(status)) { + /* dump the whole packet */ + DebugDumpBytes(pBuf,pPacket->ActualLength,"BAD HTC Recv PKT"); + } else { +#ifdef HTC_CAPTURE_LAST_FRAME + A_MEMCPY(&target->LastFrameHdr,pBuf,sizeof(HTC_FRAME_HDR)); +#endif + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + if (pPacket->ActualLength > 0) { + AR_DEBUG_PRINTBUF(pPacket->pBuffer,pPacket->ActualLength,"HTC - Application Msg"); + } + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessRecvHeader \n")); + return status; +} + +/* asynchronous completion handler for recv packet fetching, when the device layer + * completes a read request, it will call this completion handler */ +void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + HTC_ENDPOINT *pEndpoint; + A_UINT32 nextLookAhead = 0; + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCRecvCompleteHandler (status:%d, ep:%d) \n", + pPacket->Status, pPacket->Endpoint)); + + AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX); + pEndpoint = &target->EndPoint[pPacket->Endpoint]; + pPacket->Completion = NULL; + + /* get completion status */ + status = pPacket->Status; + + do { + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HTCRecvCompleteHandler: request failed (status:%d, ep:%d) \n", + pPacket->Status, pPacket->Endpoint)); + break; + } + /* process the header for any trailer data */ + status = HTCProcessRecvHeader(target,pPacket,&nextLookAhead); + + if (A_FAILED(status)) { + break; + } + /* was there a lookahead for the next packet? */ + if (nextLookAhead != 0) { + A_STATUS nextStatus; + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("HTCRecvCompleteHandler - next look ahead was non-zero : 0x%X \n", + nextLookAhead)); + /* we have another packet, get the next packet fetch started (pipelined) before + * we call into the endpoint's callback, this will start another async request */ + nextStatus = HTCRecvMessagePendingHandler(target,&nextLookAhead,NULL); + if (A_EPROTO == nextStatus) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Next look ahead from recv header was INVALID\n")); + DebugDumpBytes((A_UINT8 *)&nextLookAhead, + 4, + "BAD lookahead from lookahead report"); + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("HTCRecvCompleteHandler - rechecking for more messages...\n")); + /* if we did not get anything on the look-ahead, + * call device layer to asynchronously re-check for messages. If we can keep the async + * processing going we get better performance. If there is a pending message we will keep processing + * messages asynchronously which should pipeline things nicely */ + DevCheckPendingRecvMsgsAsync(&target->Device); + } + + HTC_RX_STAT_PROFILE(target,pEndpoint,nextLookAhead); + DO_RCV_COMPLETION(target,pPacket,pEndpoint); + + } while (FALSE); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCRecvCompleteHandler , message fetch failed (status = %d) \n", + status)); + /* recyle this packet */ + HTC_RECYCLE_RX_PKT(target, pPacket, pEndpoint); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCRecvCompleteHandler\n")); +} + +/* synchronously wait for a control message from the target, + * This function is used at initialization time ONLY. At init messages + * on ENDPOINT 0 are expected. */ +A_STATUS HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket) +{ + A_STATUS status; + A_UINT32 lookAhead; + HTC_PACKET *pPacket = NULL; + HTC_FRAME_HDR *pHdr; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCWaitforControlMessage \n")); + + do { + + *ppControlPacket = NULL; + + /* call the polling function to see if we have a message */ + status = DevPollMboxMsgRecv(&target->Device, + &lookAhead, + HTC_TARGET_RESPONSE_TIMEOUT); + + if (A_FAILED(status)) { + break; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("HTCWaitforControlMessage : lookAhead : 0x%X \n", lookAhead)); + + /* check the lookahead */ + pHdr = (HTC_FRAME_HDR *)&lookAhead; + + if (pHdr->EndpointID != ENDPOINT_0) { + /* unexpected endpoint number, should be zero */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + if (A_FAILED(status)) { + /* bad message */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + pPacket = HTC_ALLOC_CONTROL_RX(target); + + if (pPacket == NULL) { + AR_DEBUG_ASSERT(FALSE); + status = A_NO_MEMORY; + break; + } + + pPacket->HTCReserved = lookAhead; + pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH; + + if (pPacket->ActualLength > pPacket->BufferLength) { + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + /* we want synchronous operation */ + pPacket->Completion = NULL; + + /* get the message from the device, this will block */ + status = HTCIssueRecv(target, pPacket); + + if (A_FAILED(status)) { + break; + } + + /* process receive header */ + status = HTCProcessRecvHeader(target,pPacket,NULL); + + pPacket->Status = status; + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCWaitforControlMessage, HTCProcessRecvHeader failed (status = %d) \n", + status)); + break; + } + + /* give the caller this control message packet, they are responsible to free */ + *ppControlPacket = pPacket; + + } while (FALSE); + + if (A_FAILED(status)) { + if (pPacket != NULL) { + /* cleanup buffer on error */ + HTC_FREE_CONTROL_RX(target,pPacket); + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCWaitforControlMessage \n")); + + return status; +} + +/* callback when device layer or lookahead report parsing detects a pending message */ +A_STATUS HTCRecvMessagePendingHandler(void *Context, A_UINT32 *LookAhead, A_BOOL *pAsyncProc) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + A_STATUS status = A_OK; + HTC_PACKET *pPacket = NULL; + HTC_FRAME_HDR *pHdr = NULL; + HTC_ENDPOINT *pEndpoint = NULL; + A_BOOL asyncProc = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCRecvMessagePendingHandler LookAhead:0x%X \n", *LookAhead)); + + if (IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(&target->Device)) { + /* We use async mode to get the packets if the device layer supports it. + * The device layer interfaces with HIF in which HIF may have restrictions on + * how interrupts are processed */ + asyncProc = TRUE; + } + + if (pAsyncProc != NULL) { + /* indicate to caller how we decided to process this */ + *pAsyncProc = asyncProc; + } + + while (TRUE) { + pHdr = (HTC_FRAME_HDR *)LookAhead; + + if (pHdr->EndpointID >= ENDPOINT_MAX) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Endpoint in look-ahead: %d \n",pHdr->EndpointID)); + /* invalid endpoint */ + status = A_EPROTO; + break; + } + + if (pHdr->PayloadLen > HTC_MAX_PAYLOAD_LENGTH) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Payload length %d exceeds max HTC : %d !\n", + pHdr->PayloadLen, HTC_MAX_PAYLOAD_LENGTH)); + status = A_EPROTO; + break; + } + + pEndpoint = &target->EndPoint[pHdr->EndpointID]; + + if (0 == pEndpoint->ServiceID) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Endpoint %d is not connected !\n",pHdr->EndpointID)); + /* endpoint isn't even connected */ + status = A_EPROTO; + break; + } + + if (pEndpoint->EpCallBacks.EpRecvAlloc != NULL) { + /* user is using a per-packet allocation callback */ + pPacket = pEndpoint->EpCallBacks.EpRecvAlloc(pEndpoint->EpCallBacks.pContext, + (HTC_ENDPOINT_ID) pHdr->EndpointID, + pHdr->PayloadLen + sizeof(HTC_FRAME_HDR)); + + /* lock RX, in case this allocation fails, we need to update internal state below */ + + LOCK_HTC_RX(target); + + } else { + /* user is using a refill handler that can refill multiple HTC buffers */ + /* lock RX to get a buffer */ + LOCK_HTC_RX(target); + + /* get a packet from the endpoint recv queue */ + pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers); + + if (NULL == pPacket) { + /* check for refill handler */ + if (pEndpoint->EpCallBacks.EpRecvRefill != NULL) { + UNLOCK_HTC_RX(target); + /* call the re-fill handler */ + pEndpoint->EpCallBacks.EpRecvRefill(pEndpoint->EpCallBacks.pContext, + (HTC_ENDPOINT_ID) pHdr->EndpointID); + LOCK_HTC_RX(target); + /* check if we have more buffers */ + pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers); + /* fall through */ + } + } + } + + if (NULL == pPacket) { + /* this is not an error, we simply need to mark that we are waiting for buffers.*/ + target->HTCStateFlags |= HTC_STATE_WAIT_BUFFERS; + target->EpWaitingForBuffers = (HTC_ENDPOINT_ID) pHdr->EndpointID; + status = A_NO_MEMORY; + } + + if (HTC_STOPPING(target)) { + status = A_ECANCELED; + } + + UNLOCK_HTC_RX(target); + + if (A_FAILED(status)) { + /* no buffers or stopping */ + break; + } + + pPacket->PktInfo.AsRx.IndicationFlags = 0; + + AR_DEBUG_ASSERT(pPacket->Endpoint == pHdr->EndpointID); + + /* make sure this message can fit in the endpoint buffer */ + if ((pHdr->PayloadLen + HTC_HDR_LENGTH) > pPacket->BufferLength) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Payload Length Error : header reports payload of: %d, endpoint buffer size: %d \n", + pHdr->PayloadLen, pPacket->BufferLength)); + status = A_EPROTO; + break; + } + + pPacket->HTCReserved = *LookAhead; /* set expected look ahead */ + /* set the amount of data to fetch */ + pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH; + + if (asyncProc) { + /* we use async mode to get the packet if the device layer supports it + * set our callback and context */ + pPacket->Completion = HTCRecvCompleteHandler; + pPacket->pContext = target; + } else { + /* fully synchronous */ + pPacket->Completion = NULL; + } + + /* go fetch the packet */ + status = HTCIssueRecv(target, pPacket); + + if (A_FAILED(status)) { + break; + } + + if (asyncProc) { + /* we did this asynchronously so we can get out of the loop, the asynch processing + * creates a chain of requests to continue processing pending messages in the + * context of callbacks */ + break; + } + + /* in the sync case, we process the packet, check lookaheads and then repeat */ + + *LookAhead = 0; + status = HTCProcessRecvHeader(target,pPacket,LookAhead); + + if (A_FAILED(status)) { + break; + } + + HTC_RX_STAT_PROFILE(target,pEndpoint,*LookAhead); + + /* check lookahead to see if we can indicate next packet hint to recv callback */ + if (LookAhead != 0) { + pHdr = (HTC_FRAME_HDR *)&LookAhead; + /* check to see if the "next" packet is from the same endpoint of the + completing packet */ + if (pHdr->EndpointID == pPacket->Endpoint) { + /* check that there is a buffer available to actually fetch it + * NOTE: no need to lock RX here , since we are synchronously processing RX + * and we are only looking at the queue (not modifying it) */ + if (!HTC_QUEUE_EMPTY(&pEndpoint->RxBuffers)) { + /* provide a hint that there are more RX packets to fetch */ + pPacket->PktInfo.AsRx.IndicationFlags |= HTC_RX_FLAGS_INDICATE_MORE_PKTS; + } + } + } + + DO_RCV_COMPLETION(target,pPacket,pEndpoint); + + pPacket = NULL; + + if (0 == *LookAhead) { + break; + } + + /* check whether other OS contexts have queued any WMI command/data for WLAN. + * This check is needed only if WLAN Tx and Rx happens in same thread context */ + A_CHECK_DRV_TX(); + } + + if (A_NO_MEMORY == status) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" Endpoint :%d has no buffers, blocking receiver to prevent overrun.. \n", + (pHdr != NULL) ? pHdr->EndpointID : 0xFFFF)); + /* try to stop receive at the device layer */ + DevStopRecv(&target->Device, asyncProc ? DEV_STOP_RECV_ASYNC : DEV_STOP_RECV_SYNC); + status = A_OK; + } else if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Failed to get pending message : LookAhead Value: 0x%X (status = %d) \n", + *LookAhead, status)); + if (pPacket != NULL) { + /* clean up packet on error */ + HTC_RECYCLE_RX_PKT(target, pPacket, pEndpoint); + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCRecvMessagePendingHandler \n")); + + return status; +} + +/* Makes a buffer available to the HTC module */ +A_STATUS HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint; + A_BOOL unblockRecv = FALSE; + A_STATUS status = A_OK; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("+- HTCAddReceivePkt: endPointId: %d, buffer: 0x%X, length: %d\n", + pPacket->Endpoint, (A_UINT32)pPacket->pBuffer, pPacket->BufferLength)); + + do { + AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX); + + pEndpoint = &target->EndPoint[pPacket->Endpoint]; + + LOCK_HTC_RX(target); + + if (HTC_STOPPING(target)) { + pPacket->Status = A_ECANCELED; + status = A_ECANCELED; + UNLOCK_HTC_RX(target); + pEndpoint->EpCallBacks.EpRecv(pEndpoint->EpCallBacks.pContext, pPacket); + break; + } + + /* store receive packet */ + HTC_PACKET_ENQUEUE(&pEndpoint->RxBuffers, pPacket); + + /* check if we are blocked waiting for a new buffer */ + if (target->HTCStateFlags & HTC_STATE_WAIT_BUFFERS) { + if (target->EpWaitingForBuffers == pPacket->Endpoint) { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" receiver was blocked on ep:%d, unblocking.. \n", + target->EpWaitingForBuffers)); + target->HTCStateFlags &= ~HTC_STATE_WAIT_BUFFERS; + target->EpWaitingForBuffers = ENDPOINT_MAX; + unblockRecv = TRUE; + } + } + + UNLOCK_HTC_RX(target); + + if (unblockRecv && !HTC_STOPPING(target)) { + /* TODO : implement a buffer threshold count? */ + DevEnableRecv(&target->Device,DEV_ENABLE_RECV_SYNC); + } + + } while (FALSE); + + return status; +} + +void HTCUnblockRecv(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_BOOL unblockRecv = FALSE; + + LOCK_HTC_RX(target); + + /* check if we are blocked waiting for a new buffer */ + if (target->HTCStateFlags & HTC_STATE_WAIT_BUFFERS) { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HTCUnblockRx : receiver was blocked on ep:%d, unblocking.. \n", + target->EpWaitingForBuffers)); + target->HTCStateFlags &= ~HTC_STATE_WAIT_BUFFERS; + target->EpWaitingForBuffers = ENDPOINT_MAX; + unblockRecv = TRUE; + } + + UNLOCK_HTC_RX(target); + + if (unblockRecv && !HTC_STOPPING(target)) { + /* re-enable */ + DevEnableRecv(&target->Device,DEV_ENABLE_RECV_ASYNC); + } +} + +static void HTCFlushEndpointRX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint) +{ + HTC_PACKET *pPacket; + + LOCK_HTC_RX(target); + + while (1) { + pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers); + if (NULL == pPacket) { + break; + } + UNLOCK_HTC_RX(target); + pPacket->Status = A_ECANCELED; + pPacket->ActualLength = 0; + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" Flushing RX packet:0x%X, length:%d, ep:%d \n", + (A_UINT32)pPacket, pPacket->BufferLength, pPacket->Endpoint)); + /* give the packet back */ + pEndpoint->EpCallBacks.EpRecv(pEndpoint->EpCallBacks.pContext, + pPacket); + LOCK_HTC_RX(target); + } + + UNLOCK_HTC_RX(target); + + +} + +void HTCFlushRecvBuffers(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + int i; + + for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) { + pEndpoint = &target->EndPoint[i]; + if (pEndpoint->ServiceID == 0) { + /* not in use.. */ + continue; + } + HTCFlushEndpointRX(target,pEndpoint); + } +} + + +void HTCEnableRecv(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + + if (!HTC_STOPPING(target)) { + /* re-enable */ + DevEnableRecv(&target->Device,DEV_ENABLE_RECV_SYNC); + } +} + +void HTCDisableRecv(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + + if (!HTC_STOPPING(target)) { + /* disable */ + DevStopRecv(&target->Device,DEV_ENABLE_RECV_SYNC); + } +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/htc_send.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc_send.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/htc_send.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc_send.c 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,612 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + +typedef enum _HTC_SEND_QUEUE_RESULT { + HTC_SEND_QUEUE_OK = 0, /* packet was queued */ + HTC_SEND_QUEUE_DROP = 1, /* this packet should be dropped */ +} HTC_SEND_QUEUE_RESULT; + +#define DO_EP_TX_COMPLETION(ep,p) \ +{ \ + (p)->Completion = NULL; \ + (ep)->EpCallBacks.EpTxComplete((ep)->EpCallBacks.pContext,(p)); \ +} + + +/* call the distribute credits callback with the distribution */ +#define DO_DISTRIBUTION(t,reason,description,pList) \ +{ \ + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, \ + (" calling distribute function (%s) (dfn:0x%X, ctxt:0x%X, dist:0x%X) \n", \ + (description), \ + (A_UINT32)(t)->DistributeCredits, \ + (A_UINT32)(t)->pCredDistContext, \ + (A_UINT32)pList)); \ + (t)->DistributeCredits((t)->pCredDistContext, \ + (pList), \ + (reason)); \ +} + +/* our internal send packet completion handler when packets are submited to the AR6K device + * layer */ +static void HTCSendPktCompletionHandler(void *Context, HTC_PACKET *pPacket) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + HTC_ENDPOINT *pEndpoint = &target->EndPoint[pPacket->Endpoint]; + + + if (A_FAILED(pPacket->Status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCSendPktCompletionHandler: request failed (status:%d, ep:%d) \n", + pPacket->Status, pPacket->Endpoint)); + } + /* first, fixup the head room we allocated */ + pPacket->pBuffer += HTC_HDR_LENGTH; + /* do completion */ + DO_EP_TX_COMPLETION(pEndpoint,pPacket); +} + +A_STATUS HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT8 SendFlags) +{ + A_STATUS status; + A_UINT8 *pHdrBuf; + A_BOOL sync = FALSE; + + /* caller always provides headrooom */ + pPacket->pBuffer -= HTC_HDR_LENGTH; + pHdrBuf = pPacket->pBuffer; + /* setup frame header */ + A_SET_UINT16_FIELD(pHdrBuf,HTC_FRAME_HDR,PayloadLen,(A_UINT16)pPacket->ActualLength); + A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,Flags,SendFlags); + A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,EndpointID, (A_UINT8)pPacket->Endpoint); + + if (pPacket->Completion == NULL) { + /* mark that this request was synchronously issued */ + sync = TRUE; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("+-HTCIssueSend: transmit length : %d (%s) \n", + pPacket->ActualLength + HTC_HDR_LENGTH, + sync ? "SYNC" : "ASYNC" )); + + /* send message to device */ + status = DevSendPacket(&target->Device, + pPacket, + pPacket->ActualLength + HTC_HDR_LENGTH); + + if (sync) { + /* use local sync variable. If this was issued asynchronously, pPacket is no longer + * safe to access. */ + pPacket->pBuffer += HTC_HDR_LENGTH; + } + + /* if this request was asynchronous, the packet completion routine will be invoked by + * the device layer when the HIF layer completes the request */ + + return status; +} + +/* try to send the current packet or a packet at the head of the TX queue, + * if there are no credits, the packet remains in the queue. + * this function returns the result of the attempt to send the HTC packet */ +static HTC_SEND_QUEUE_RESULT HTCTrySend(HTC_TARGET *target, + HTC_ENDPOINT *pEndpoint, + HTC_PACKET *pPacketToSend) +{ + HTC_PACKET *pPacket; + int creditsRequired; + int remainder; + A_UINT8 sendFlags; + HTC_SEND_QUEUE_RESULT result; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HTCTrySend (pPkt:0x%X)\n",(A_UINT32)pPacketToSend)); + + if (pPacketToSend != NULL) { + /* see if adding this packet hits the max depth */ + if ((pEndpoint->CurrentTxQueueDepth + 1) >= pEndpoint->MaxTxQueueDepth) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d, TX queue is full, Depth:%d, Max:%d \n", + pPacketToSend->Endpoint, pEndpoint->CurrentTxQueueDepth, pEndpoint->MaxTxQueueDepth)); + /* queue will be full, invoke any callbacks to determine what action to take */ + if (pEndpoint->EpCallBacks.EpSendFull != NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Calling driver's send full callback.... \n")); + if (pEndpoint->EpCallBacks.EpSendFull(pEndpoint->EpCallBacks.pContext, + pPacketToSend) == HTC_SEND_FULL_DROP) { + /* callback wants the packet dropped */ + INC_HTC_EP_STAT(pEndpoint, TxDropped, 1); + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend: \n")); + return HTC_SEND_QUEUE_DROP; + } + } + } + } + + LOCK_HTC_TX(target); + + result = HTC_SEND_QUEUE_OK; + + if (pPacketToSend != NULL) { + /* packet was supplied to be queued */ + HTC_PACKET_ENQUEUE(&pEndpoint->TxQueue,pPacketToSend); + pEndpoint->CurrentTxQueueDepth++; + } + + pEndpoint->TxProcessCount++; + if (pEndpoint->TxProcessCount > 1) { + /* another thread is draining the queues, get out */ + pEndpoint->TxProcessCount--; + UNLOCK_HTC_TX(target); + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend: \n")); + return HTC_SEND_QUEUE_OK; + } + + /* at this point, only 1 thread may enter to drain this endpoint queue */ + + /* now drain the TX queue for transmission as long as we have enough + * credits */ + + while (1) { + + if (HTC_QUEUE_EMPTY(&pEndpoint->TxQueue)) { + /* nothing in the queue */ + break; + } + + if (HTC_STOPPING(target)) { + if (pPacketToSend != NULL) { + HTC_PACKET_REMOVE(pPacketToSend); + pEndpoint->CurrentTxQueueDepth--; + result = HTC_SEND_QUEUE_DROP; + } + break; + } + + sendFlags = 0; + + /* get packet at head, but don't remove it */ + pPacket = HTC_GET_PKT_AT_HEAD(&pEndpoint->TxQueue); + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Got head packet:0x%X , Queue Depth: %d\n", + (A_UINT32)pPacket, pEndpoint->CurrentTxQueueDepth)); + + /* figure out how many credits this message requires */ + creditsRequired = (pPacket->ActualLength + HTC_HDR_LENGTH) / target->TargetCreditSize; + remainder = (pPacket->ActualLength + HTC_HDR_LENGTH) % target->TargetCreditSize; + + if (remainder) { + creditsRequired++; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Creds Required:%d Got:%d\n", + creditsRequired, pEndpoint->CreditDist.TxCredits)); + + if (pEndpoint->CreditDist.TxCredits < creditsRequired) { + + /* not enough credits */ + + if (pPacket->Endpoint == ENDPOINT_0) { + /* leave it in the queue */ + break; + } + /* invoke the registered distribution function only if this is not + * endpoint 0, we let the driver layer provide more credits if it can. + * We pass the credit distribution list starting at the endpoint in question + * */ + + /* set how many credits we need */ + pEndpoint->CreditDist.TxCreditsSeek = + creditsRequired - pEndpoint->CreditDist.TxCredits; + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_SEEK_CREDITS, + "Seek Credits", + &pEndpoint->CreditDist); + pEndpoint->CreditDist.TxCreditsSeek = 0; + + if (pEndpoint->CreditDist.TxCredits < creditsRequired) { + /* still not enough credits to send, leave packet in the queue */ + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + (" Not enough credits for ep %d leaving packet in queue..\n", + pPacket->Endpoint)); + break; + } + + } + + pEndpoint->CreditDist.TxCredits -= creditsRequired; + INC_HTC_EP_STAT(pEndpoint, TxCreditsConsummed, creditsRequired); + + /* check if we need credits back from the target */ + if (pEndpoint->CreditDist.TxCredits < pEndpoint->CreditDist.TxCreditsPerMaxMsg) { + /* we are getting low on credits, see if we can ask for more from the distribution function */ + pEndpoint->CreditDist.TxCreditsSeek = + pEndpoint->CreditDist.TxCreditsPerMaxMsg - pEndpoint->CreditDist.TxCredits; + + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_SEEK_CREDITS, + "Seek Credits", + &pEndpoint->CreditDist); + + pEndpoint->CreditDist.TxCreditsSeek = 0; + /* see if we were successful in getting more */ + if (pEndpoint->CreditDist.TxCredits < pEndpoint->CreditDist.TxCreditsPerMaxMsg) { + /* tell the target we need credits ASAP! */ + sendFlags |= HTC_FLAGS_NEED_CREDIT_UPDATE; + INC_HTC_EP_STAT(pEndpoint, TxCreditLowIndications, 1); + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Host Needs Credits \n")); + } + } + + /* now we can fully dequeue */ + pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->TxQueue); + pEndpoint->CurrentTxQueueDepth--; + + INC_HTC_EP_STAT(pEndpoint, TxIssued, 1); + + UNLOCK_HTC_TX(target); + + HTCIssueSend(target, pPacket, sendFlags); + + LOCK_HTC_TX(target); + + /* go back and check for more messages */ + } + + /* we're done, clear count */ + pEndpoint->TxProcessCount = 0; + UNLOCK_HTC_TX(target); + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend: \n")); + + return result; +} + +/* HTC API - HTCSendPkt */ +A_STATUS HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint; + HTC_ENDPOINT_ID ep; + A_STATUS status = A_OK; + HTC_SEND_QUEUE_RESULT result; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("+HTCSendPkt: Enter endPointId: %d, buffer: 0x%X, length: %d \n", + pPacket->Endpoint, (A_UINT32)pPacket->pBuffer, pPacket->ActualLength)); + + ep = pPacket->Endpoint; + AR_DEBUG_ASSERT(ep < ENDPOINT_MAX); + pEndpoint = &target->EndPoint[ep]; + + do { + + /* everything sent through this interface is asynchronous */ + /* fill in HTC completion routines */ + pPacket->Completion = HTCSendPktCompletionHandler; + pPacket->pContext = target; + + result = HTCTrySend(target, pEndpoint, pPacket); + + if (HTC_SEND_QUEUE_DROP == result) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d, TX packet dropped \n", ep)); + if (HTC_STOPPING(target)) { + status = A_ECANCELED; + } else { + status = A_NO_RESOURCE; + } + } + + } while (FALSE); + + if (A_FAILED(status)) { + pPacket->Status = status; + DO_EP_TX_COMPLETION(pEndpoint,pPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCSendPkt \n")); + + return status; +} + + +/* check TX queues to drain because of credit distribution update */ +static INLINE void HTCCheckEndpointTxQueues(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + HTC_ENDPOINT_CREDIT_DIST *pDistItem; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCCheckEndpointTxQueues \n")); + pDistItem = target->EpCreditDistributionListHead; + + /* run through the credit distribution list to see + * if there are packets queued + * NOTE: no locks need to be taken since the distribution list + * is not dynamic (cannot be re-ordered) and we are not modifying any state */ + while (pDistItem != NULL) { + pEndpoint = (HTC_ENDPOINT *)pDistItem->pHTCReserved; + + if (pEndpoint->CurrentTxQueueDepth > 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Ep %d has %d credits and %d Packets in TX Queue \n", + pDistItem->Endpoint, pEndpoint->CreditDist.TxCredits, pEndpoint->CurrentTxQueueDepth)); + /* try to start the stalled queue, this list is ordered by priority. + * Highest priority queue get's processed first, if there are credits available the + * highest priority queue will get a chance to reclaim credits from lower priority + * ones */ + HTCTrySend(target, pEndpoint, NULL); + } + + pDistItem = pDistItem->pNext; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCCheckEndpointTxQueues \n")); +} + +/* process credit reports and call distribution function */ +void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint) +{ + int i; + HTC_ENDPOINT *pEndpoint; + int totalCredits = 0; + A_BOOL doDist = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCProcessCreditRpt, Credit Report Entries:%d \n", NumEntries)); + + /* lock out TX while we update credits */ + LOCK_HTC_TX(target); + + for (i = 0; i < NumEntries; i++, pRpt++) { + if (pRpt->EndpointID >= ENDPOINT_MAX) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + pEndpoint = &target->EndPoint[pRpt->EndpointID]; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d got %d credits \n", + pRpt->EndpointID, pRpt->Credits)); + + +#ifdef HTC_EP_STAT_PROFILING + + INC_HTC_EP_STAT(pEndpoint, TxCreditRpts, 1); + INC_HTC_EP_STAT(pEndpoint, TxCreditsReturned, pRpt->Credits); + + if (FromEndpoint == pRpt->EndpointID) { + /* this credit report arrived on the same endpoint indicating it arrived in an RX + * packet */ + INC_HTC_EP_STAT(pEndpoint, TxCreditsFromRx, pRpt->Credits); + INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromRx, 1); + } else if (FromEndpoint == ENDPOINT_0) { + /* this credit arrived on endpoint 0 as a NULL message */ + INC_HTC_EP_STAT(pEndpoint, TxCreditsFromEp0, pRpt->Credits); + INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromEp0, 1); + } else { + /* arrived on another endpoint */ + INC_HTC_EP_STAT(pEndpoint, TxCreditsFromOther, pRpt->Credits); + INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromOther, 1); + } + +#endif + + if (ENDPOINT_0 == pRpt->EndpointID) { + /* always give endpoint 0 credits back */ + pEndpoint->CreditDist.TxCredits += pRpt->Credits; + } else { + /* for all other endpoints, update credits to distribute, the distribution function + * will handle giving out credits back to the endpoints */ + pEndpoint->CreditDist.TxCreditsToDist += pRpt->Credits; + /* flag that we have to do the distribution */ + doDist = TRUE; + } + + /* refresh tx depth for distribution function that will recover these credits + * NOTE: this is only valid when there are credits to recover! */ + pEndpoint->CreditDist.TxQueueDepth = pEndpoint->CurrentTxQueueDepth; + + totalCredits += pRpt->Credits; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Report indicated %d credits to distribute \n", totalCredits)); + + if (doDist) { + /* this was a credit return based on a completed send operations + * note, this is done with the lock held */ + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_SEND_COMPLETE, + "Send Complete", + target->EpCreditDistributionListHead->pNext); + } + + UNLOCK_HTC_TX(target); + + if (totalCredits) { + HTCCheckEndpointTxQueues(target); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCProcessCreditRpt \n")); +} + +/* flush endpoint TX queue */ +static void HTCFlushEndpointTX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint, HTC_TX_TAG Tag) +{ + HTC_PACKET *pPacket; + HTC_PACKET_QUEUE discardQueue; + + /* initialize the discard queue */ + INIT_HTC_PACKET_QUEUE(&discardQueue); + + LOCK_HTC_TX(target); + + /* interate from the front of the TX queue and flush out packets */ + ITERATE_OVER_LIST_ALLOW_REMOVE(&pEndpoint->TxQueue, pPacket, HTC_PACKET, ListLink) { + + /* check for removal */ + if ((HTC_TX_PACKET_TAG_ALL == Tag) || (Tag == pPacket->PktInfo.AsTx.Tag)) { + /* remove from queue */ + HTC_PACKET_REMOVE(pPacket); + /* add it to the discard pile */ + HTC_PACKET_ENQUEUE(&discardQueue, pPacket); + pEndpoint->CurrentTxQueueDepth--; + } + + } ITERATE_END; + + UNLOCK_HTC_TX(target); + + /* empty the discard queue */ + while (1) { + pPacket = HTC_PACKET_DEQUEUE(&discardQueue); + if (NULL == pPacket) { + break; + } + pPacket->Status = A_ECANCELED; + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" Flushing TX packet:0x%X, length:%d, ep:%d tag:0x%X \n", + (A_UINT32)pPacket, pPacket->ActualLength, pPacket->Endpoint, pPacket->PktInfo.AsTx.Tag)); + DO_EP_TX_COMPLETION(pEndpoint,pPacket); + } + +} + +void DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("--- EP : %d ServiceID: 0x%X --------------\n", + pEPDist->Endpoint, pEPDist->ServiceID)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" this:0x%X next:0x%X prev:0x%X\n", + (A_UINT32)pEPDist, (A_UINT32)pEPDist->pNext, (A_UINT32)pEPDist->pPrev)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" DistFlags : 0x%X \n", pEPDist->DistFlags)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsNorm : %d \n", pEPDist->TxCreditsNorm)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsMin : %d \n", pEPDist->TxCreditsMin)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCredits : %d \n", pEPDist->TxCredits)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsAssigned : %d \n", pEPDist->TxCreditsAssigned)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsSeek : %d \n", pEPDist->TxCreditsSeek)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditSize : %d \n", pEPDist->TxCreditSize)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsPerMaxMsg : %d \n", pEPDist->TxCreditsPerMaxMsg)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsToDist : %d \n", pEPDist->TxCreditsToDist)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxQueueDepth : %d \n", + ((HTC_ENDPOINT *) pEPDist->pHTCReserved)->CurrentTxQueueDepth)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("----------------------------------------------------\n")); +} + +void DumpCreditDistStates(HTC_TARGET *target) +{ + HTC_ENDPOINT_CREDIT_DIST *pEPList = target->EpCreditDistributionListHead; + + while (pEPList != NULL) { + DumpCreditDist(pEPList); + pEPList = pEPList->pNext; + } + + if (target->DistributeCredits != NULL) { + DO_DISTRIBUTION(target, + HTC_DUMP_CREDIT_STATE, + "Dump State", + NULL); + } +} + +/* flush all send packets from all endpoint queues */ +void HTCFlushSendPkts(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + int i; + + DumpCreditDistStates(target); + + for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) { + pEndpoint = &target->EndPoint[i]; + if (pEndpoint->ServiceID == 0) { + /* not in use.. */ + continue; + } + HTCFlushEndpointTX(target,pEndpoint,HTC_TX_PACKET_TAG_ALL); + } + + +} + +/* HTC API to flush an endpoint's TX queue*/ +void HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint = &target->EndPoint[Endpoint]; + + if (pEndpoint->ServiceID == 0) { + AR_DEBUG_ASSERT(FALSE); + /* not in use.. */ + return; + } + + HTCFlushEndpointTX(target, pEndpoint, Tag); +} + +/* HTC API to indicate activity to the credit distribution function */ +void HTCIndicateActivityChange(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + A_BOOL Active) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint = &target->EndPoint[Endpoint]; + A_BOOL doDist = FALSE; + + if (pEndpoint->ServiceID == 0) { + AR_DEBUG_ASSERT(FALSE); + /* not in use.. */ + return; + } + + LOCK_HTC_TX(target); + + if (Active) { + if (!(pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE)) { + /* mark active now */ + pEndpoint->CreditDist.DistFlags |= HTC_EP_ACTIVE; + doDist = TRUE; + } + } else { + if (pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE) { + /* mark inactive now */ + pEndpoint->CreditDist.DistFlags &= ~HTC_EP_ACTIVE; + doDist = TRUE; + } + } + + if (doDist) { + /* indicate current Tx Queue depth to the credit distribution function */ + pEndpoint->CreditDist.TxQueueDepth = pEndpoint->CurrentTxQueueDepth; + /* do distribution again based on activity change + * note, this is done with the lock held */ + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_ACTIVITY_CHANGE, + "Activity Change", + target->EpCreditDistributionListHead->pNext); + } + + UNLOCK_HTC_TX(target); + + if (doDist && !Active) { + /* if a stream went inactive and this resulted in a credit distribution change, + * some credits may now be available for HTC packets that are stuck in + * HTC queues */ + HTCCheckEndpointTxQueues(target); + } +} + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/htc_services.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc_services.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/htc_services.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc_services.c 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,412 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + +void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket) +{ + /* not implemented + * we do not send control TX frames during normal runtime, only during setup */ + AR_DEBUG_ASSERT(FALSE); +} + + /* callback when a control message arrives on this endpoint */ +void HTCControlRecv(void *Context, HTC_PACKET *pPacket) +{ + AR_DEBUG_ASSERT(pPacket->Endpoint == ENDPOINT_0); + + if (pPacket->Status == A_ECANCELED) { + /* this is a flush operation, return the control packet back to the pool */ + HTC_FREE_CONTROL_RX((HTC_TARGET*)Context,pPacket); + return; + } + + /* the only control messages we are expecting are NULL messages (credit resports), which should + * never get here */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCControlRecv, got message with length:%d \n", + pPacket->ActualLength + HTC_HDR_LENGTH)); + + /* dump header and message */ + DebugDumpBytes(pPacket->pBuffer - HTC_HDR_LENGTH, + pPacket->ActualLength + HTC_HDR_LENGTH, + "Unexpected ENDPOINT 0 Message"); + + HTC_RECYCLE_RX_PKT((HTC_TARGET*)Context,pPacket,&((HTC_TARGET*)Context)->EndPoint[0]); +} + +A_STATUS HTCSendSetupComplete(HTC_TARGET *target) +{ + HTC_PACKET *pSendPacket = NULL; + A_STATUS status; + HTC_SETUP_COMPLETE_MSG *pSetupComplete; + + do { + /* allocate a packet to send to the target */ + pSendPacket = HTC_ALLOC_CONTROL_TX(target); + + if (NULL == pSendPacket) { + status = A_NO_MEMORY; + break; + } + + /* assemble setup complete message */ + pSetupComplete = (HTC_SETUP_COMPLETE_MSG *)pSendPacket->pBuffer; + A_MEMZERO(pSetupComplete,sizeof(HTC_SETUP_COMPLETE_MSG)); + pSetupComplete->MessageID = HTC_MSG_SETUP_COMPLETE_ID; + + SET_HTC_PACKET_INFO_TX(pSendPacket, + NULL, + (A_UINT8 *)pSetupComplete, + sizeof(HTC_SETUP_COMPLETE_MSG), + ENDPOINT_0, + HTC_SERVICE_TX_PACKET_TAG); + + /* we want synchronous operation */ + pSendPacket->Completion = NULL; + /* send the message */ + status = HTCIssueSend(target,pSendPacket,0); + + } while (FALSE); + + if (pSendPacket != NULL) { + HTC_FREE_CONTROL_TX(target,pSendPacket); + } + + return status; +} + + +A_STATUS HTCConnectService(HTC_HANDLE HTCHandle, + HTC_SERVICE_CONNECT_REQ *pConnectReq, + HTC_SERVICE_CONNECT_RESP *pConnectResp) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_STATUS status = A_OK; + HTC_PACKET *pRecvPacket = NULL; + HTC_PACKET *pSendPacket = NULL; + HTC_CONNECT_SERVICE_RESPONSE_MSG *pResponseMsg; + HTC_CONNECT_SERVICE_MSG *pConnectMsg; + HTC_ENDPOINT_ID assignedEndpoint = ENDPOINT_MAX; + HTC_ENDPOINT *pEndpoint; + int maxMsgSize = 0; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCConnectService, target:0x%X SvcID:0x%X \n", + (A_UINT32)target, pConnectReq->ServiceID)); + + do { + + AR_DEBUG_ASSERT(pConnectReq->ServiceID != 0); + + if (HTC_CTRL_RSVD_SVC == pConnectReq->ServiceID) { + /* special case for pseudo control service */ + assignedEndpoint = ENDPOINT_0; + maxMsgSize = HTC_MAX_CONTROL_MESSAGE_LENGTH; + } else { + /* allocate a packet to send to the target */ + pSendPacket = HTC_ALLOC_CONTROL_TX(target); + + if (NULL == pSendPacket) { + AR_DEBUG_ASSERT(FALSE); + status = A_NO_MEMORY; + break; + } + /* assemble connect service message */ + pConnectMsg = (HTC_CONNECT_SERVICE_MSG *)pSendPacket->pBuffer; + AR_DEBUG_ASSERT(pConnectMsg != NULL); + A_MEMZERO(pConnectMsg,sizeof(HTC_CONNECT_SERVICE_MSG)); + pConnectMsg->MessageID = HTC_MSG_CONNECT_SERVICE_ID; + pConnectMsg->ServiceID = pConnectReq->ServiceID; + pConnectMsg->ConnectionFlags = pConnectReq->ConnectionFlags; + /* check caller if it wants to transfer meta data */ + if ((pConnectReq->pMetaData != NULL) && + (pConnectReq->MetaDataLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) { + /* copy meta data into message buffer (after header ) */ + A_MEMCPY((A_UINT8 *)pConnectMsg + sizeof(HTC_CONNECT_SERVICE_MSG), + pConnectReq->pMetaData, + pConnectReq->MetaDataLength); + pConnectMsg->ServiceMetaLength = pConnectReq->MetaDataLength; + } + + SET_HTC_PACKET_INFO_TX(pSendPacket, + NULL, + (A_UINT8 *)pConnectMsg, + sizeof(HTC_CONNECT_SERVICE_MSG) + pConnectMsg->ServiceMetaLength, + ENDPOINT_0, + HTC_SERVICE_TX_PACKET_TAG); + + /* we want synchronous operation */ + pSendPacket->Completion = NULL; + + status = HTCIssueSend(target,pSendPacket,0); + + if (A_FAILED(status)) { + break; + } + + /* wait for response */ + status = HTCWaitforControlMessage(target, &pRecvPacket); + + if (A_FAILED(status)) { + break; + } + /* we controlled the buffer creation so it has to be properly aligned */ + pResponseMsg = (HTC_CONNECT_SERVICE_RESPONSE_MSG *)pRecvPacket->pBuffer; + + if ((pResponseMsg->MessageID != HTC_MSG_CONNECT_SERVICE_RESPONSE_ID) || + (pRecvPacket->ActualLength < sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG))) { + /* this message is not valid */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + pConnectResp->ConnectRespCode = pResponseMsg->Status; + /* check response status */ + if (pResponseMsg->Status != HTC_SERVICE_SUCCESS) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" Target failed service 0x%X connect request (status:%d)\n", + pResponseMsg->ServiceID, pResponseMsg->Status)); + status = A_EPROTO; + break; + } + + assignedEndpoint = (HTC_ENDPOINT_ID) pResponseMsg->EndpointID; + maxMsgSize = pResponseMsg->MaxMsgSize; + + if ((pConnectResp->pMetaData != NULL) && + (pResponseMsg->ServiceMetaLength > 0) && + (pResponseMsg->ServiceMetaLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) { + /* caller supplied a buffer and the target responded with data */ + int copyLength = min((int)pConnectResp->BufferLength, (int)pResponseMsg->ServiceMetaLength); + /* copy the meta data */ + A_MEMCPY(pConnectResp->pMetaData, + ((A_UINT8 *)pResponseMsg) + sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG), + copyLength); + pConnectResp->ActualLength = copyLength; + } + + } + + /* the rest of these are parameter checks so set the error status */ + status = A_EPROTO; + + if (assignedEndpoint >= ENDPOINT_MAX) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + if (0 == maxMsgSize) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + pEndpoint = &target->EndPoint[assignedEndpoint]; + + if (pEndpoint->ServiceID != 0) { + /* endpoint already in use! */ + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* return assigned endpoint to caller */ + pConnectResp->Endpoint = assignedEndpoint; + pConnectResp->MaxMsgLength = maxMsgSize; + + /* setup the endpoint */ + pEndpoint->ServiceID = pConnectReq->ServiceID; /* this marks the endpoint in use */ + pEndpoint->MaxTxQueueDepth = pConnectReq->MaxSendQueueDepth; + pEndpoint->MaxMsgLength = maxMsgSize; + /* copy all the callbacks */ + pEndpoint->EpCallBacks = pConnectReq->EpCallbacks; + INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBuffers); + INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue); + /* set the credit distribution info for this endpoint, this information is + * passed back to the credit distribution callback function */ + pEndpoint->CreditDist.ServiceID = pConnectReq->ServiceID; + pEndpoint->CreditDist.pHTCReserved = pEndpoint; + pEndpoint->CreditDist.Endpoint = assignedEndpoint; + pEndpoint->CreditDist.TxCreditSize = target->TargetCreditSize; + pEndpoint->CreditDist.TxCreditsPerMaxMsg = maxMsgSize / target->TargetCreditSize; + + if (0 == pEndpoint->CreditDist.TxCreditsPerMaxMsg) { + pEndpoint->CreditDist.TxCreditsPerMaxMsg = 1; + } + + status = A_OK; + + } while (FALSE); + + if (pSendPacket != NULL) { + HTC_FREE_CONTROL_TX(target,pSendPacket); + } + + if (pRecvPacket != NULL) { + HTC_FREE_CONTROL_RX(target,pRecvPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCConnectService \n")); + + return status; +} + +static void AddToEndpointDistList(HTC_TARGET *target, HTC_ENDPOINT_CREDIT_DIST *pEpDist) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEntry,*pLastEntry; + + if (NULL == target->EpCreditDistributionListHead) { + target->EpCreditDistributionListHead = pEpDist; + pEpDist->pNext = NULL; + pEpDist->pPrev = NULL; + return; + } + + /* queue to the end of the list, this does not have to be very + * fast since this list is built at startup time */ + pCurEntry = target->EpCreditDistributionListHead; + + while (pCurEntry) { + pLastEntry = pCurEntry; + pCurEntry = pCurEntry->pNext; + } + + pLastEntry->pNext = pEpDist; + pEpDist->pPrev = pLastEntry; + pEpDist->pNext = NULL; +} + + + +/* default credit init callback */ +static void HTCDefaultCreditInit(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + int TotalCredits) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + int totalEps = 0; + int creditsPerEndpoint; + + pCurEpDist = pEPList; + /* first run through the list and figure out how many endpoints we are dealing with */ + while (pCurEpDist != NULL) { + pCurEpDist = pCurEpDist->pNext; + totalEps++; + } + + /* even distribution */ + creditsPerEndpoint = TotalCredits/totalEps; + + pCurEpDist = pEPList; + /* run through the list and set minimum and normal credits and + * provide the endpoint with some credits to start */ + while (pCurEpDist != NULL) { + + if (creditsPerEndpoint < pCurEpDist->TxCreditsPerMaxMsg) { + /* too many endpoints and not enough credits */ + AR_DEBUG_ASSERT(FALSE); + break; + } + /* our minimum is set for at least 1 max message */ + pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg; + /* this value is ignored by our credit alg, since we do + * not dynamically adjust credits, this is the policy of + * the "default" credit distribution, something simple and easy */ + pCurEpDist->TxCreditsNorm = 0xFFFF; + /* give the endpoint minimum credits */ + pCurEpDist->TxCredits = creditsPerEndpoint; + pCurEpDist->TxCreditsAssigned = creditsPerEndpoint; + pCurEpDist = pCurEpDist->pNext; + } + +} + +/* default credit distribution callback, NOTE, this callback holds the TX lock */ +void HTCDefaultCreditDist(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList, + HTC_CREDIT_DIST_REASON Reason) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + + if (Reason == HTC_CREDIT_DIST_SEND_COMPLETE) { + pCurEpDist = pEPDistList; + /* simple distribution */ + while (pCurEpDist != NULL) { + if (pCurEpDist->TxCreditsToDist > 0) { + /* just give the endpoint back the credits */ + pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist; + pCurEpDist->TxCreditsToDist = 0; + } + pCurEpDist = pCurEpDist->pNext; + } + } + + /* note we do not need to handle the other reason codes as this is a very + * simple distribution scheme, no need to seek for more credits or handle inactivity */ +} + +void HTCSetCreditDistribution(HTC_HANDLE HTCHandle, + void *pCreditDistContext, + HTC_CREDIT_DIST_CALLBACK CreditDistFunc, + HTC_CREDIT_INIT_CALLBACK CreditInitFunc, + HTC_SERVICE_ID ServicePriorityOrder[], + int ListLength) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + int i; + int ep; + + if (CreditInitFunc != NULL) { + /* caller has supplied their own distribution functions */ + target->InitCredits = CreditInitFunc; + AR_DEBUG_ASSERT(CreditDistFunc != NULL); + target->DistributeCredits = CreditDistFunc; + target->pCredDistContext = pCreditDistContext; + } else { + /* caller wants HTC to do distribution */ + /* if caller wants service to handle distributions then + * it must set both of these to NULL! */ + AR_DEBUG_ASSERT(CreditDistFunc == NULL); + target->InitCredits = HTCDefaultCreditInit; + target->DistributeCredits = HTCDefaultCreditDist; + target->pCredDistContext = target; + } + + /* always add HTC control endpoint first, we only expose the list after the + * first one, this is added for TX queue checking */ + AddToEndpointDistList(target, &target->EndPoint[ENDPOINT_0].CreditDist); + + /* build the list of credit distribution structures in priority order + * supplied by the caller, these will follow endpoint 0 */ + for (i = 0; i < ListLength; i++) { + /* match services with endpoints and add the endpoints to the distribution list + * in FIFO order */ + for (ep = ENDPOINT_1; ep < ENDPOINT_MAX; ep++) { + if (target->EndPoint[ep].ServiceID == ServicePriorityOrder[i]) { + /* queue this one to the list */ + AddToEndpointDistList(target, &target->EndPoint[ep].CreditDist); + break; + } + } + AR_DEBUG_ASSERT(ep < ENDPOINT_MAX); + } + +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/htc_services.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc_services.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/htc_services.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/htc_services.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __HTC_SERVICES_H__ +#define __HTC_SERVICES_H__ + +/* Current service IDs */ + +typedef enum { + RSVD_SERVICE_GROUP = 0, + WMI_SERVICE_GROUP = 1, + + HTC_TEST_GROUP = 254, + HTC_SERVICE_GROUP_LAST = 255 +}HTC_SERVICE_GROUP_IDS; + +#define MAKE_SERVICE_ID(group,index) \ + (int)(((int)group << 8) | (int)(index)) + +/* NOTE: service ID of 0x0000 is reserved and should never be used */ +#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1) +#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0) +#define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1) +#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2) +#define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3) +#define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4) +#define WMI_MAX_SERVICES 5 + +/* raw stream service (i.e. flash, tcmd, calibration apps) */ +#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0) + +#endif /*HTC_SERVICES_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/ieee80211.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ieee80211.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/ieee80211.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ieee80211.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,405 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _NET80211_IEEE80211_H_ +#define _NET80211_IEEE80211_H_ + +#include "athstartpack.h" + +/* + * 802.11 protocol definitions. + */ +#define IEEE80211_WEP_KEYLEN 5 /* 40bit */ +#define IEEE80211_WEP104_KEYLEN 13 /* 40bit */ +#define IEEE80211_WEP_IVLEN 3 /* 24bit */ +#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ +#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ +#define IEEE80211_WEP_NKID 4 /* number of key ids */ + +/* + * 802.11i defines an extended IV for use with non-WEP ciphers. + * When the EXTIV bit is set in the key id byte an additional + * 4 bytes immediately follow the IV for TKIP. For CCMP the + * EXTIV bit is likewise set but the 8 bytes represent the + * CCMP header rather than IV+extended-IV. + */ +#define IEEE80211_WEP_EXTIV 0x20 +#define IEEE80211_WEP_EXTIVLEN 4 /* extended IV length */ +#define IEEE80211_WEP_MICLEN 8 /* trailing MIC */ + +#define IEEE80211_CRC_LEN 4 + +#ifdef WAPI_ENABLE +#define IEEE80211_WAPI_EXTIVLEN 10 /* extended IV length */ +#endif /* WAPI ENABLE */ + + +#define IEEE80211_ADDR_LEN 6 /* size of 802.11 address */ +/* is 802.11 address multicast/broadcast? */ +#define IEEE80211_IS_MULTICAST(_a) (*(_a) & 0x01) +#define IEEE80211_IS_BROADCAST(_a) (*(_a) == 0xFF) +#define WEP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN) +#define WEP_TRAILER IEEE80211_WEP_CRCLEN +#define CCMP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + \ + IEEE80211_WEP_EXTIVLEN) +#define CCMP_TRAILER IEEE80211_WEP_MICLEN +#define TKIP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + \ + IEEE80211_WEP_EXTIVLEN) +#define TKIP_TRAILER IEEE80211_WEP_CRCLEN +#define TKIP_MICLEN IEEE80211_WEP_MICLEN + + +#define IEEE80211_ADDR_EQ(addr1, addr2) \ + (A_MEMCMP(addr1, addr2, IEEE80211_ADDR_LEN) == 0) + +#define IEEE80211_ADDR_COPY(dst,src) A_MEMCPY(dst,src,IEEE80211_ADDR_LEN) + +#define IEEE80211_KEYBUF_SIZE 16 +#define IEEE80211_MICBUF_SIZE (8+8) /* space for both tx and rx */ + +/* + * NB: these values are ordered carefully; there are lots of + * of implications in any reordering. In particular beware + * that 4 is not used to avoid conflicting with IEEE80211_F_PRIVACY. + */ +#define IEEE80211_CIPHER_WEP 0 +#define IEEE80211_CIPHER_TKIP 1 +#define IEEE80211_CIPHER_AES_OCB 2 +#define IEEE80211_CIPHER_AES_CCM 3 +#define IEEE80211_CIPHER_CKIP 5 +#define IEEE80211_CIPHER_CCKM_KRK 6 +#define IEEE80211_CIPHER_NONE 7 /* pseudo value */ + +#define IEEE80211_CIPHER_MAX (IEEE80211_CIPHER_NONE+1) + +#define IEEE80211_IS_VALID_WEP_CIPHER_LEN(len) \ + (((len) == 5) || ((len) == 13) || ((len) == 16)) + + + +/* + * generic definitions for IEEE 802.11 frames + */ +PREPACK struct ieee80211_frame { + A_UINT8 i_fc[2]; + A_UINT8 i_dur[2]; + A_UINT8 i_addr1[IEEE80211_ADDR_LEN]; + A_UINT8 i_addr2[IEEE80211_ADDR_LEN]; + A_UINT8 i_addr3[IEEE80211_ADDR_LEN]; + A_UINT8 i_seq[2]; + /* possibly followed by addr4[IEEE80211_ADDR_LEN]; */ + /* see below */ +} POSTPACK; + +PREPACK struct ieee80211_qosframe { + A_UINT8 i_fc[2]; + A_UINT8 i_dur[2]; + A_UINT8 i_addr1[IEEE80211_ADDR_LEN]; + A_UINT8 i_addr2[IEEE80211_ADDR_LEN]; + A_UINT8 i_addr3[IEEE80211_ADDR_LEN]; + A_UINT8 i_seq[2]; + A_UINT8 i_qos[2]; +} POSTPACK; + +#define IEEE80211_FC0_VERSION_MASK 0x03 +#define IEEE80211_FC0_VERSION_SHIFT 0 +#define IEEE80211_FC0_VERSION_0 0x00 +#define IEEE80211_FC0_TYPE_MASK 0x0c +#define IEEE80211_FC0_TYPE_SHIFT 2 +#define IEEE80211_FC0_TYPE_MGT 0x00 +#define IEEE80211_FC0_TYPE_CTL 0x04 +#define IEEE80211_FC0_TYPE_DATA 0x08 + +#define IEEE80211_FC0_SUBTYPE_MASK 0xf0 +#define IEEE80211_FC0_SUBTYPE_SHIFT 4 +/* for TYPE_MGT */ +#define IEEE80211_FC0_SUBTYPE_ASSOC_REQ 0x00 +#define IEEE80211_FC0_SUBTYPE_ASSOC_RESP 0x10 +#define IEEE80211_FC0_SUBTYPE_REASSOC_REQ 0x20 +#define IEEE80211_FC0_SUBTYPE_REASSOC_RESP 0x30 +#define IEEE80211_FC0_SUBTYPE_PROBE_REQ 0x40 +#define IEEE80211_FC0_SUBTYPE_PROBE_RESP 0x50 +#define IEEE80211_FC0_SUBTYPE_BEACON 0x80 +#define IEEE80211_FC0_SUBTYPE_ATIM 0x90 +#define IEEE80211_FC0_SUBTYPE_DISASSOC 0xa0 +#define IEEE80211_FC0_SUBTYPE_AUTH 0xb0 +#define IEEE80211_FC0_SUBTYPE_DEAUTH 0xc0 +/* for TYPE_CTL */ +#define IEEE80211_FC0_SUBTYPE_PS_POLL 0xa0 +#define IEEE80211_FC0_SUBTYPE_RTS 0xb0 +#define IEEE80211_FC0_SUBTYPE_CTS 0xc0 +#define IEEE80211_FC0_SUBTYPE_ACK 0xd0 +#define IEEE80211_FC0_SUBTYPE_CF_END 0xe0 +#define IEEE80211_FC0_SUBTYPE_CF_END_ACK 0xf0 +/* for TYPE_DATA (bit combination) */ +#define IEEE80211_FC0_SUBTYPE_DATA 0x00 +#define IEEE80211_FC0_SUBTYPE_CF_ACK 0x10 +#define IEEE80211_FC0_SUBTYPE_CF_POLL 0x20 +#define IEEE80211_FC0_SUBTYPE_CF_ACPL 0x30 +#define IEEE80211_FC0_SUBTYPE_NODATA 0x40 +#define IEEE80211_FC0_SUBTYPE_CFACK 0x50 +#define IEEE80211_FC0_SUBTYPE_CFPOLL 0x60 +#define IEEE80211_FC0_SUBTYPE_CF_ACK_CF_ACK 0x70 +#define IEEE80211_FC0_SUBTYPE_QOS 0x80 +#define IEEE80211_FC0_SUBTYPE_QOS_NULL 0xc0 + +#define IEEE80211_FC1_DIR_MASK 0x03 +#define IEEE80211_FC1_DIR_NODS 0x00 /* STA->STA */ +#define IEEE80211_FC1_DIR_TODS 0x01 /* STA->AP */ +#define IEEE80211_FC1_DIR_FROMDS 0x02 /* AP ->STA */ +#define IEEE80211_FC1_DIR_DSTODS 0x03 /* AP ->AP */ + +#define IEEE80211_FC1_MORE_FRAG 0x04 +#define IEEE80211_FC1_RETRY 0x08 +#define IEEE80211_FC1_PWR_MGT 0x10 +#define IEEE80211_FC1_MORE_DATA 0x20 +#define IEEE80211_FC1_WEP 0x40 +#define IEEE80211_FC1_ORDER 0x80 + +#define IEEE80211_SEQ_FRAG_MASK 0x000f +#define IEEE80211_SEQ_FRAG_SHIFT 0 +#define IEEE80211_SEQ_SEQ_MASK 0xfff0 +#define IEEE80211_SEQ_SEQ_SHIFT 4 + +#define IEEE80211_NWID_LEN 32 + +/* + * 802.11 rate set. + */ +#define IEEE80211_RATE_SIZE 8 /* 802.11 standard */ +#define IEEE80211_RATE_MAXSIZE 15 /* max rates we'll handle */ + +#define WMM_NUM_AC 4 /* 4 AC categories */ + +#define WMM_PARAM_ACI_M 0x60 /* Mask for ACI field */ +#define WMM_PARAM_ACI_S 5 /* Shift for ACI field */ +#define WMM_PARAM_ACM_M 0x10 /* Mask for ACM bit */ +#define WMM_PARAM_ACM_S 4 /* Shift for ACM bit */ +#define WMM_PARAM_AIFSN_M 0x0f /* Mask for aifsn field */ +#define WMM_PARAM_LOGCWMIN_M 0x0f /* Mask for CwMin field (in log) */ +#define WMM_PARAM_LOGCWMAX_M 0xf0 /* Mask for CwMax field (in log) */ +#define WMM_PARAM_LOGCWMAX_S 4 /* Shift for CwMax field */ + +#define WMM_AC_TO_TID(_ac) ( \ + ((_ac) == WMM_AC_VO) ? 6 : \ + ((_ac) == WMM_AC_VI) ? 5 : \ + ((_ac) == WMM_AC_BK) ? 1 : \ + 0) + +#define TID_TO_WMM_AC(_tid) ( \ + ((_tid) < 1) ? WMM_AC_BE : \ + ((_tid) < 3) ? WMM_AC_BK : \ + ((_tid) < 6) ? WMM_AC_VI : \ + WMM_AC_VO) +/* + * Management information element payloads. + */ + +enum { + IEEE80211_ELEMID_SSID = 0, + IEEE80211_ELEMID_RATES = 1, + IEEE80211_ELEMID_FHPARMS = 2, + IEEE80211_ELEMID_DSPARMS = 3, + IEEE80211_ELEMID_CFPARMS = 4, + IEEE80211_ELEMID_TIM = 5, + IEEE80211_ELEMID_IBSSPARMS = 6, + IEEE80211_ELEMID_COUNTRY = 7, + IEEE80211_ELEMID_CHALLENGE = 16, + /* 17-31 reserved for challenge text extension */ + IEEE80211_ELEMID_PWRCNSTR = 32, + IEEE80211_ELEMID_PWRCAP = 33, + IEEE80211_ELEMID_TPCREQ = 34, + IEEE80211_ELEMID_TPCREP = 35, + IEEE80211_ELEMID_SUPPCHAN = 36, + IEEE80211_ELEMID_CHANSWITCH = 37, + IEEE80211_ELEMID_MEASREQ = 38, + IEEE80211_ELEMID_MEASREP = 39, + IEEE80211_ELEMID_QUIET = 40, + IEEE80211_ELEMID_IBSSDFS = 41, + IEEE80211_ELEMID_ERP = 42, + IEEE80211_ELEMID_RSN = 48, + IEEE80211_ELEMID_XRATES = 50, +#ifdef WAPI_ENABLE + IEEE80211_ELEMID_WAPI = 68, +#endif + IEEE80211_ELEMID_TPC = 150, + IEEE80211_ELEMID_CCKM = 156, + IEEE80211_ELEMID_VENDOR = 221, /* vendor private */ +}; + +#define ATH_OUI 0x7f0300 /* Atheros OUI */ +#define ATH_OUI_TYPE 0x01 +#define ATH_OUI_SUBTYPE 0x01 +#define ATH_OUI_VERSION 0x00 + +#define WPA_OUI 0xf25000 +#define WPA_OUI_TYPE 0x01 +#define WPA_VERSION 1 /* current supported version */ + +#define WPA_CSE_NULL 0x00 +#define WPA_CSE_WEP40 0x01 +#define WPA_CSE_TKIP 0x02 +#define WPA_CSE_CCMP 0x04 +#define WPA_CSE_WEP104 0x05 + +#define WPA_ASE_NONE 0x00 +#define WPA_ASE_8021X_UNSPEC 0x01 +#define WPA_ASE_8021X_PSK 0x02 + +#define RSN_OUI 0xac0f00 +#define RSN_VERSION 1 /* current supported version */ + +#define RSN_CSE_NULL 0x00 +#define RSN_CSE_WEP40 0x01 +#define RSN_CSE_TKIP 0x02 +#define RSN_CSE_WRAP 0x03 +#define RSN_CSE_CCMP 0x04 +#define RSN_CSE_WEP104 0x05 + +#define RSN_ASE_NONE 0x00 +#define RSN_ASE_8021X_UNSPEC 0x01 +#define RSN_ASE_8021X_PSK 0x02 + +#define RSN_CAP_PREAUTH 0x01 + +#define WMM_OUI 0xf25000 +#define WMM_OUI_TYPE 0x02 +#define WMM_INFO_OUI_SUBTYPE 0x00 +#define WMM_PARAM_OUI_SUBTYPE 0x01 +#define WMM_VERSION 1 + +#ifdef PYXIS_ADHOC +#define PYXIS_OUI 0xf25000 /* Pyxis OUI 00-50-F2*/ +#define PYXIS_OUI_TYPE 0x06 +#endif + +/* WMM stream classes */ +#define WMM_NUM_AC 4 +#define WMM_AC_BE 0 /* best effort */ +#define WMM_AC_BK 1 /* background */ +#define WMM_AC_VI 2 /* video */ +#define WMM_AC_VO 3 /* voice */ + +/* TSPEC related */ +#define ACTION_CATEGORY_CODE_TSPEC 17 +#define ACTION_CODE_TSPEC_ADDTS 0 +#define ACTION_CODE_TSPEC_ADDTS_RESP 1 +#define ACTION_CODE_TSPEC_DELTS 2 + +typedef enum { + TSPEC_STATUS_CODE_ADMISSION_ACCEPTED = 0, + TSPEC_STATUS_CODE_ADDTS_INVALID_PARAMS = 0x1, + TSPEC_STATUS_CODE_ADDTS_REQUEST_REFUSED = 0x3, + TSPEC_STATUS_CODE_UNSPECIFIED_QOS_RELATED_FAILURE = 0xC8, + TSPEC_STATUS_CODE_REQUESTED_REFUSED_POLICY_CONFIGURATION = 0xC9, + TSPEC_STATUS_CODE_INSUFFCIENT_BANDWIDTH = 0xCA, + TSPEC_STATUS_CODE_INVALID_PARAMS = 0xCB, + TSPEC_STATUS_CODE_DELTS_SENT = 0x30, + TSPEC_STATUS_CODE_DELTS_RECV = 0x31, +} TSPEC_STATUS_CODE; + +#define TSPEC_TSID_MASK 0xF +#define TSPEC_TSID_S 1 + +/* + * WMM/802.11e Tspec Element + */ +typedef PREPACK struct wmm_tspec_ie_t { + A_UINT8 elementId; + A_UINT8 len; + A_UINT8 oui[3]; + A_UINT8 ouiType; + A_UINT8 ouiSubType; + A_UINT8 version; + A_UINT16 tsInfo_info; + A_UINT8 tsInfo_reserved; + A_UINT16 nominalMSDU; + A_UINT16 maxMSDU; + A_UINT32 minServiceInt; + A_UINT32 maxServiceInt; + A_UINT32 inactivityInt; + A_UINT32 suspensionInt; + A_UINT32 serviceStartTime; + A_UINT32 minDataRate; + A_UINT32 meanDataRate; + A_UINT32 peakDataRate; + A_UINT32 maxBurstSize; + A_UINT32 delayBound; + A_UINT32 minPhyRate; + A_UINT16 sba; + A_UINT16 mediumTime; +} POSTPACK WMM_TSPEC_IE; + + +/* + * BEACON management packets + * + * octet timestamp[8] + * octet beacon interval[2] + * octet capability information[2] + * information element + * octet elemid + * octet length + * octet information[length] + */ + +#define IEEE80211_BEACON_INTERVAL(beacon) \ + ((beacon)[8] | ((beacon)[9] << 8)) +#define IEEE80211_BEACON_CAPABILITY(beacon) \ + ((beacon)[10] | ((beacon)[11] << 8)) + +#define IEEE80211_CAPINFO_ESS 0x0001 +#define IEEE80211_CAPINFO_IBSS 0x0002 +#define IEEE80211_CAPINFO_CF_POLLABLE 0x0004 +#define IEEE80211_CAPINFO_CF_POLLREQ 0x0008 +#define IEEE80211_CAPINFO_PRIVACY 0x0010 +#define IEEE80211_CAPINFO_SHORT_PREAMBLE 0x0020 +#define IEEE80211_CAPINFO_PBCC 0x0040 +#define IEEE80211_CAPINFO_CHNL_AGILITY 0x0080 +/* bits 8-9 are reserved */ +#define IEEE80211_CAPINFO_SHORT_SLOTTIME 0x0400 +#define IEEE80211_CAPINFO_APSD 0x0800 +/* bit 12 is reserved */ +#define IEEE80211_CAPINFO_DSSSOFDM 0x2000 +/* bits 14-15 are reserved */ + +/* + * Authentication Modes + */ + +enum ieee80211_authmode { + IEEE80211_AUTH_NONE = 0, + IEEE80211_AUTH_OPEN = 1, + IEEE80211_AUTH_SHARED = 2, + IEEE80211_AUTH_8021X = 3, + IEEE80211_AUTH_AUTO = 4, /* auto-select/accept */ + /* NB: these are used only for ioctls */ + IEEE80211_AUTH_WPA = 5, /* WPA/RSN w/ 802.1x */ + IEEE80211_AUTH_WPA_PSK = 6, /* WPA/RSN w/ PSK */ + IEEE80211_AUTH_WPA_CCKM = 7, /* WPA/RSN IE w/ CCKM */ +}; + +#define IEEE80211_PS_MAX_QUEUE 50 /*Maximum no of buffers that can be queues for PS*/ + +#include "athendpack.h" + +#endif /* _NET80211_IEEE80211_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/ieee80211_ioctl.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ieee80211_ioctl.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/ieee80211_ioctl.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ieee80211_ioctl.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2004-2005 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// + * + * + * $Id: //depot/sw/releases/olca2.2.0/host/os/linux/include/ieee80211_ioctl.h#1 $ + */ + +#ifndef _IEEE80211_IOCTL_H_ +#define _IEEE80211_IOCTL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Extracted from the MADWIFI net80211/ieee80211_ioctl.h + */ + +/* + * WPA/RSN get/set key request. Specify the key/cipher + * type and whether the key is to be used for sending and/or + * receiving. The key index should be set only when working + * with global keys (use IEEE80211_KEYIX_NONE for ``no index''). + * Otherwise a unicast/pairwise key is specified by the bssid + * (on a station) or mac address (on an ap). They key length + * must include any MIC key data; otherwise it should be no + more than IEEE80211_KEYBUF_SIZE. + */ +struct ieee80211req_key { + u_int8_t ik_type; /* key/cipher type */ + u_int8_t ik_pad; + u_int16_t ik_keyix; /* key index */ + u_int8_t ik_keylen; /* key length in bytes */ + u_int8_t ik_flags; +#define IEEE80211_KEY_XMIT 0x01 +#define IEEE80211_KEY_RECV 0x02 +#define IEEE80211_KEY_DEFAULT 0x80 /* default xmit key */ + u_int8_t ik_macaddr[IEEE80211_ADDR_LEN]; + u_int64_t ik_keyrsc; /* key receive sequence counter */ + u_int64_t ik_keytsc; /* key transmit sequence counter */ + u_int8_t ik_keydata[IEEE80211_KEYBUF_SIZE+IEEE80211_MICBUF_SIZE]; +}; +/* + * Delete a key either by index or address. Set the index + * to IEEE80211_KEYIX_NONE when deleting a unicast key. + */ +struct ieee80211req_del_key { + u_int8_t idk_keyix; /* key index */ + u_int8_t idk_macaddr[IEEE80211_ADDR_LEN]; +}; +/* + * MLME state manipulation request. IEEE80211_MLME_ASSOC + * only makes sense when operating as a station. The other + * requests can be used when operating as a station or an + * ap (to effect a station). + */ +struct ieee80211req_mlme { + u_int8_t im_op; /* operation to perform */ +#define IEEE80211_MLME_ASSOC 1 /* associate station */ +#define IEEE80211_MLME_DISASSOC 2 /* disassociate station */ +#define IEEE80211_MLME_DEAUTH 3 /* deauthenticate station */ +#define IEEE80211_MLME_AUTHORIZE 4 /* authorize station */ +#define IEEE80211_MLME_UNAUTHORIZE 5 /* unauthorize station */ + u_int16_t im_reason; /* 802.11 reason code */ + u_int8_t im_macaddr[IEEE80211_ADDR_LEN]; +}; + +struct ieee80211req_addpmkid { + u_int8_t pi_bssid[IEEE80211_ADDR_LEN]; + u_int8_t pi_enable; + u_int8_t pi_pmkid[16]; +}; + +#define AUTH_ALG_OPEN_SYSTEM 0x01 +#define AUTH_ALG_SHARED_KEY 0x02 +#define AUTH_ALG_LEAP 0x04 + +struct ieee80211req_authalg { + u_int8_t auth_alg; +}; + +/* + * Request to add an IE to a Management Frame + */ +enum{ + IEEE80211_APPIE_FRAME_BEACON = 0, + IEEE80211_APPIE_FRAME_PROBE_REQ = 1, + IEEE80211_APPIE_FRAME_PROBE_RESP = 2, + IEEE80211_APPIE_FRAME_ASSOC_REQ = 3, + IEEE80211_APPIE_FRAME_ASSOC_RESP = 4, + IEEE80211_APPIE_NUM_OF_FRAME = 5 +}; + +/* + * The Maximum length of the IE that can be added to a Management frame + */ +#define IEEE80211_APPIE_FRAME_MAX_LEN 200 + +struct ieee80211req_getset_appiebuf { + u_int32_t app_frmtype; /* management frame type for which buffer is added */ + u_int32_t app_buflen; /*application supplied buffer length */ + u_int8_t app_buf[]; +}; + +/* + * The following definitions are used by an application to set filter + * for receiving management frames + */ +enum { + IEEE80211_FILTER_TYPE_BEACON = 0x1, + IEEE80211_FILTER_TYPE_PROBE_REQ = 0x2, + IEEE80211_FILTER_TYPE_PROBE_RESP = 0x4, + IEEE80211_FILTER_TYPE_ASSOC_REQ = 0x8, + IEEE80211_FILTER_TYPE_ASSOC_RESP = 0x10, + IEEE80211_FILTER_TYPE_AUTH = 0x20, + IEEE80211_FILTER_TYPE_DEAUTH = 0x40, + IEEE80211_FILTER_TYPE_DISASSOC = 0x80, + IEEE80211_FILTER_TYPE_ALL = 0xFF /* used to check the valid filter bits */ +}; + +struct ieee80211req_set_filter { + u_int32_t app_filterype; /* management frame filter type */ +}; + +enum { + IEEE80211_PARAM_AUTHMODE = 3, /* Authentication Mode */ + IEEE80211_PARAM_MCASTCIPHER = 5, + IEEE80211_PARAM_MCASTKEYLEN = 6, /* multicast key length */ + IEEE80211_PARAM_UCASTCIPHER = 8, + IEEE80211_PARAM_UCASTKEYLEN = 9, /* unicast key length */ + IEEE80211_PARAM_WPA = 10, /* WPA mode (0,1,2) */ + IEEE80211_PARAM_ROAMING = 12, /* roaming mode */ + IEEE80211_PARAM_PRIVACY = 13, /* privacy invoked */ + IEEE80211_PARAM_COUNTERMEASURES = 14, /* WPA/TKIP countermeasures */ + IEEE80211_PARAM_DROPUNENCRYPTED = 15, /* discard unencrypted frames */ +}; + +/* + * Values for IEEE80211_PARAM_WPA + */ +#define WPA_MODE_WPA1 1 +#define WPA_MODE_WPA2 2 +#define WPA_MODE_AUTO 3 +#define WPA_MODE_NONE 4 + +struct ieee80211req_wpaie { + u_int8_t wpa_macaddr[IEEE80211_ADDR_LEN]; + u_int8_t wpa_ie[IEEE80211_MAX_IE]; + u_int8_t rsn_ie[IEEE80211_MAX_IE]; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* _IEEE80211_IOCTL_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/ieee80211_node.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ieee80211_node.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/ieee80211_node.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ieee80211_node.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,90 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _IEEE80211_NODE_H_ +#define _IEEE80211_NODE_H_ + +/* + * Node locking definitions. + */ +#define IEEE80211_NODE_LOCK_INIT(_nt) A_MUTEX_INIT(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_LOCK_DESTROY(_nt) if (A_IS_MUTEX_VALID(&(_nt)->nt_nodelock)) { \ + A_MUTEX_DELETE(&(_nt)->nt_nodelock); } + +#define IEEE80211_NODE_LOCK(_nt) A_MUTEX_LOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_UNLOCK(_nt) A_MUTEX_UNLOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_LOCK_BH(_nt) A_MUTEX_LOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_UNLOCK_BH(_nt) A_MUTEX_UNLOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_LOCK_ASSERT(_nt) + +/* + * Node reference counting definitions. + * + * ieee80211_node_initref initialize the reference count to 1 + * ieee80211_node_incref add a reference + * ieee80211_node_decref remove a reference + * ieee80211_node_dectestref remove a reference and return 1 if this + * is the last reference, otherwise 0 + * ieee80211_node_refcnt reference count for printing (only) + */ +#define ieee80211_node_initref(_ni) ((_ni)->ni_refcnt = 1) +#define ieee80211_node_incref(_ni) ((_ni)->ni_refcnt++) +#define ieee80211_node_decref(_ni) ((_ni)->ni_refcnt--) +#define ieee80211_node_dectestref(_ni) (((_ni)->ni_refcnt--) == 1) +#define ieee80211_node_refcnt(_ni) ((_ni)->ni_refcnt) + +#define IEEE80211_NODE_HASHSIZE 32 +/* simple hash is enough for variation of macaddr */ +#define IEEE80211_NODE_HASH(addr) \ + (((const A_UINT8 *)(addr))[IEEE80211_ADDR_LEN - 1] % \ + IEEE80211_NODE_HASHSIZE) + +/* + * Table of ieee80211_node instances. Each ieee80211com + * has at least one for holding the scan candidates. + * When operating as an access point or in ibss mode there + * is a second table for associated stations or neighbors. + */ +struct ieee80211_node_table { + void *nt_wmip; /* back reference */ + A_MUTEX_T nt_nodelock; /* on node table */ + struct bss *nt_node_first; /* information of all nodes */ + struct bss *nt_node_last; /* information of all nodes */ + struct bss *nt_hash[IEEE80211_NODE_HASHSIZE]; + const char *nt_name; /* for debugging */ + A_UINT32 nt_scangen; /* gen# for timeout scan */ + A_TIMER nt_inact_timer; + A_UINT8 isTimerArmed; /* is the node timer armed */ + A_UINT32 nt_nodeAge; /* node aging time */ +#ifdef OS_ROAM_MANAGEMENT + A_UINT32 nt_si_gen; /* gen# for scan indication*/ +#endif +}; + +/* + * Our scan parameters should lead to more reliable scans so we don't need + * to keep around the host cache for very long. It leads to having too many + * old networks. + */ +#define WLAN_NODE_INACT_TIMEOUT_MSEC 45000 + +#endif /* _IEEE80211_NODE_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/ini_dset.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ini_dset.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/ini_dset.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ini_dset.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,90 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _INI_DSET_H_ +#define _INI_DSET_H_ + +/* + * Each of these represents a WHAL INI table, which consists + * of an "address column" followed by 1 or more "value columns". + * + * Software uses the base WHAL_INI_DATA_ID+column to access a + * DataSet that holds a particular column of data. + */ +typedef enum { +#if defined(AR6002_REV4) || defined(AR6003) +#ifdef FPGA + WHAL_INI_DATA_ID_NULL =0, + WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3,4,5 */ + WHAL_INI_DATA_ID_COMMON =6, /* 7 */ + WHAL_INI_DATA_ID_BB_RFGAIN =8, /* 9,10 */ +/* Only one LNA for FPGA */ +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 WHAL_INI_DATA_ID_BB_RFGAIN + WHAL_INI_DATA_ID_ANALOG_BANK0 =11, /* 12 */ + WHAL_INI_DATA_ID_ANALOG_BANK1 =13, /* 14 */ + WHAL_INI_DATA_ID_ANALOG_BANK2 =15, /* 16 */ + WHAL_INI_DATA_ID_ANALOG_BANK3 =17, /* 18, 19 */ + WHAL_INI_DATA_ID_ANALOG_BANK6 =20, /* 21,22 */ + WHAL_INI_DATA_ID_ANALOG_BANK7 =23, /* 24 */ +#else + WHAL_INI_DATA_ID_NULL =0, + WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3,4,5 */ + WHAL_INI_DATA_ID_COMMON =6, /* 7 */ + WHAL_INI_DATA_ID_BB_RFGAIN =8, /* 9,10 */ +/* Add these definitions for compatability */ +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 WHAL_INI_DATA_ID_BB_RFGAIN + WHAL_INI_DATA_ID_ANALOG_COMMON =11, /* 12 */ + WHAL_INI_DATA_ID_ANALOG_MODE_SPECIFIC=13, /* 14,15 */ + WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17,18 */ + WHAL_INI_DATA_ID_MODE_OVERRIDES =19, /* 20,21 */ + WHAL_INI_DATA_ID_COMMON_OVERRIDES =22, /* 23 */ + WHAL_INI_DATA_ID_ANALOG_OVERRIDES =24, /* 25,26 */ +#endif +#else + WHAL_INI_DATA_ID_NULL =0, + WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3 */ + WHAL_INI_DATA_ID_COMMON =4, /* 5 */ + WHAL_INI_DATA_ID_BB_RFGAIN =6, /* 7,8 */ +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN + WHAL_INI_DATA_ID_ANALOG_BANK1 =9, /* 10 */ + WHAL_INI_DATA_ID_ANALOG_BANK2 =11, /* 12 */ + WHAL_INI_DATA_ID_ANALOG_BANK3 =13, /* 14, 15 */ + WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17, 18 */ + WHAL_INI_DATA_ID_ANALOG_BANK7 =19, /* 20 */ + WHAL_INI_DATA_ID_MODE_OVERRIDES =21, /* 22,23 */ + WHAL_INI_DATA_ID_COMMON_OVERRIDES =24, /* 25 */ + WHAL_INI_DATA_ID_ANALOG_OVERRIDES =26, /* 27,28 */ + WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 =29, /* 30,31 */ +#endif + WHAL_INI_DATA_ID_MAX =31 +} WHAL_INI_DATA_ID; + +typedef PREPACK struct { + A_UINT16 freqIndex; // 1 - A mode 2 - B or G mode 0 - common + A_UINT16 offset; + A_UINT32 newValue; +} POSTPACK INI_DSET_REG_OVERRIDE; + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/ioctl.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ioctl.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/ioctl.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/ioctl.c 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,3484 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#include "ar6000_drv.h" +#include "ieee80211_ioctl.h" +#include "ar6kap_common.h" +#include "wlan_defs.h" +#include "reg_dbvalues.h" +#include "reg_dbschema.h" +#include "regTableData.h" + +static A_UINT8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; +static A_UINT8 null_mac[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; +extern unsigned int wmitimeout; +extern A_WAITQUEUE_HEAD arEvent; +extern int tspecCompliance; +extern int bmienable; +extern int bypasswmi; + +static int +ar6000_ioctl_get_roam_tbl(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if(wmi_get_roam_tbl_cmd(ar->arWmi) != A_OK) { + return -EIO; + } + + return 0; +} + +static int +ar6000_ioctl_get_roam_data(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + /* currently assume only roam times are required */ + if(wmi_get_roam_data_cmd(ar->arWmi, ROAM_DATA_TIME) != A_OK) { + return -EIO; + } + + + return 0; +} + +static int +ar6000_ioctl_set_roam_ctrl(struct net_device *dev, char *userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_ROAM_CTRL_CMD cmd; + A_UINT8 size = sizeof(cmd); + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if (cmd.roamCtrlType == WMI_SET_HOST_BIAS) { + if (cmd.info.bssBiasInfo.numBss > 1) { + size += (cmd.info.bssBiasInfo.numBss - 1) * sizeof(WMI_BSS_BIAS); + } + } + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if(wmi_set_roam_ctrl_cmd(ar->arWmi, &cmd, size) != A_OK) { + return -EIO; + } + + return 0; +} + +static int +ar6000_ioctl_set_powersave_timers(struct net_device *dev, char *userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_POWERSAVE_TIMERS_POLICY_CMD cmd; + A_UINT8 size = sizeof(cmd); + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if(wmi_set_powersave_timers_cmd(ar->arWmi, &cmd, size) != A_OK) { + return -EIO; + } + + return 0; +} + +static int +ar6000_ioctl_set_wmm(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_WMM_CMD cmd; + A_STATUS ret; + + if ((dev->flags & IFF_UP) != IFF_UP) { + return -EIO; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1), + sizeof(cmd))) + { + return -EFAULT; + } + + if (cmd.status == WMI_WMM_ENABLED) { + ar->arWmmEnabled = TRUE; + } else { + ar->arWmmEnabled = FALSE; + } + + ret = wmi_set_wmm_cmd(ar->arWmi, cmd.status); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_set_txop(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_WMM_TXOP_CMD cmd; + A_STATUS ret; + + if ((dev->flags & IFF_UP) != IFF_UP) { + return -EIO; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1), + sizeof(cmd))) + { + return -EFAULT; + } + + ret = wmi_set_wmm_txop(ar->arWmi, cmd.txopEnable); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_get_rd(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_STATUS ret = 0; + A_UINT8 buf[8]; + A_UINT32 countryCode; + COUNTRY_CODE_TO_ENUM_RD *reg; + void *endTable = (void *)allCountries + sizeof(allCountries); + + if ((dev->flags & IFF_UP) != IFF_UP || ar->arWmiReady == FALSE) { + return -EIO; + } + + A_MEMZERO(buf, sizeof(buf)); + A_MEMCPY(buf, &ar->arRegCode, sizeof(ar->arRegCode)); +#define REGCODE_COUNTRY_BIT 0x80000000 + if (ar->arRegCode & REGCODE_COUNTRY_BIT) + { + /* + * if we have a country code then get iso3166-1 alpha2 code + */ + countryCode = ar->arRegCode & ~REGCODE_COUNTRY_BIT; + for (reg = &allCountries[0]; (void *)reg < endTable; reg++) + { + if (reg->countryCode == countryCode) + { + /* + A_PRINTF("%s: found country code=0x%x, abbrev=%c%c\n", __FUNCTION__, + countryCode, reg->isoName[0], reg->isoName[1]); + */ + A_MEMCPY(buf+sizeof(ar->arRegCode), reg->isoName, sizeof(reg->isoName)); + } + } + } + + if(copy_to_user((char *)((unsigned int*)rq->ifr_data + 1), + buf, sizeof(buf))) + ret = -EFAULT; + + return ret; +} + +static int +ar6000_ioctl_set_country(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_AP_SET_COUNTRY_CMD cmd; + A_STATUS ret; + + if ((dev->flags & IFF_UP) != IFF_UP) { + return -EIO; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1), + sizeof(cmd))) + { + return -EFAULT; + } + + ar->ap_profile_flag = 1; /* There is a change in profile */ + + ret = wmi_set_country(ar->arWmi, cmd.countryCode); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + + +/* Get power mode command */ +static int +ar6000_ioctl_get_power_mode(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_POWER_MODE_CMD power_mode; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + power_mode.powerMode = wmi_get_power_mode_cmd(ar->arWmi); + if (copy_to_user(rq->ifr_data, &power_mode, sizeof(WMI_POWER_MODE_CMD))) { + ret = -EFAULT; + } + + return ret; +} + + +static int +ar6000_ioctl_set_channelParams(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_CHANNEL_PARAMS_CMD cmd, *cmdp; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if( (ar->arNextMode == AP_NETWORK) && (cmd.numChannels || cmd.scanParam) ) { + A_PRINTF("ERROR: Only wmode is allowed in AP mode\n"); + return -EIO; + } + + if (cmd.numChannels > 1) { + cmdp = A_MALLOC(130); + if (copy_from_user(cmdp, rq->ifr_data, + sizeof (*cmdp) + + ((cmd.numChannels - 1) * sizeof(A_UINT16)))) + { + kfree(cmdp); + return -EFAULT; + } + } else { + cmdp = &cmd; + } + + if ((ar->arPhyCapability == WMI_11G_CAPABILITY) && + ((cmdp->phyMode == WMI_11A_MODE) || (cmdp->phyMode == WMI_11AG_MODE))) + { + ret = -EINVAL; + } + + if (!ret && + (wmi_set_channelParams_cmd(ar->arWmi, cmdp->scanParam, cmdp->phyMode, + cmdp->numChannels, cmdp->channelList) + != A_OK)) + { + ret = -EIO; + } + + if (cmd.numChannels > 1) { + kfree(cmdp); + } + + /* Set the profile change flag to allow a commit cmd */ + ar->ap_profile_flag = 1; + + return ret; +} + + +static int +ar6000_ioctl_set_snr_threshold(struct net_device *dev, struct ifreq *rq) +{ + + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SNR_THRESHOLD_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if( wmi_set_snr_threshold_params(ar->arWmi, &cmd) != A_OK ) { + ret = -EIO; + } + + return ret; +} + +static int +ar6000_ioctl_set_rssi_threshold(struct net_device *dev, struct ifreq *rq) +{ +#define SWAP_THOLD(thold1, thold2) do { \ + USER_RSSI_THOLD tmpThold; \ + tmpThold.tag = thold1.tag; \ + tmpThold.rssi = thold1.rssi; \ + thold1.tag = thold2.tag; \ + thold1.rssi = thold2.rssi; \ + thold2.tag = tmpThold.tag; \ + thold2.rssi = tmpThold.rssi; \ +} while (0) + + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_RSSI_THRESHOLD_PARAMS_CMD cmd; + USER_RSSI_PARAMS rssiParams; + A_INT32 i, j; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user((char *)&rssiParams, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(USER_RSSI_PARAMS))) { + return -EFAULT; + } + cmd.weight = rssiParams.weight; + cmd.pollTime = rssiParams.pollTime; + + A_MEMCPY(ar->rssi_map, &rssiParams.tholds, sizeof(ar->rssi_map)); + /* + * only 6 elements, so use bubble sorting, in ascending order + */ + for (i = 5; i > 0; i--) { + for (j = 0; j < i; j++) { /* above tholds */ + if (ar->rssi_map[j+1].rssi < ar->rssi_map[j].rssi) { + SWAP_THOLD(ar->rssi_map[j+1], ar->rssi_map[j]); + } else if (ar->rssi_map[j+1].rssi == ar->rssi_map[j].rssi) { + return EFAULT; + } + } + } + for (i = 11; i > 6; i--) { + for (j = 6; j < i; j++) { /* below tholds */ + if (ar->rssi_map[j+1].rssi < ar->rssi_map[j].rssi) { + SWAP_THOLD(ar->rssi_map[j+1], ar->rssi_map[j]); + } else if (ar->rssi_map[j+1].rssi == ar->rssi_map[j].rssi) { + return EFAULT; + } + } + } + +#ifdef DEBUG + for (i = 0; i < 12; i++) { + AR_DEBUG2_PRINTF("thold[%d].tag: %d, thold[%d].rssi: %d \n", + i, ar->rssi_map[i].tag, i, ar->rssi_map[i].rssi); + } +#endif + cmd.thresholdAbove1_Val = ar->rssi_map[0].rssi; + cmd.thresholdAbove2_Val = ar->rssi_map[1].rssi; + cmd.thresholdAbove3_Val = ar->rssi_map[2].rssi; + cmd.thresholdAbove4_Val = ar->rssi_map[3].rssi; + cmd.thresholdAbove5_Val = ar->rssi_map[4].rssi; + cmd.thresholdAbove6_Val = ar->rssi_map[5].rssi; + cmd.thresholdBelow1_Val = ar->rssi_map[6].rssi; + cmd.thresholdBelow2_Val = ar->rssi_map[7].rssi; + cmd.thresholdBelow3_Val = ar->rssi_map[8].rssi; + cmd.thresholdBelow4_Val = ar->rssi_map[9].rssi; + cmd.thresholdBelow5_Val = ar->rssi_map[10].rssi; + cmd.thresholdBelow6_Val = ar->rssi_map[11].rssi; + + if( wmi_set_rssi_threshold_params(ar->arWmi, &cmd) != A_OK ) { + ret = -EIO; + } + + return ret; +} + +static int +ar6000_ioctl_set_lq_threshold(struct net_device *dev, struct ifreq *rq) +{ + + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_LQ_THRESHOLD_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(cmd))) { + return -EFAULT; + } + + if( wmi_set_lq_threshold_params(ar->arWmi, &cmd) != A_OK ) { + ret = -EIO; + } + + return ret; +} + + +static int +ar6000_ioctl_set_probedSsid(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_PROBED_SSID_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_probedSsid_cmd(ar->arWmi, cmd.entryIndex, cmd.flag, cmd.ssidLength, + cmd.ssid) != A_OK) + { + ret = -EIO; + } + + return ret; +} + +static int +ar6000_ioctl_set_badAp(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_ADD_BAD_AP_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (cmd.badApIndex > WMI_MAX_BAD_AP_INDEX) { + return -EIO; + } + + if (A_MEMCMP(cmd.bssid, null_mac, AR6000_ETH_ADDR_LEN) == 0) { + /* + * This is a delete badAP. + */ + if (wmi_deleteBadAp_cmd(ar->arWmi, cmd.badApIndex) != A_OK) { + ret = -EIO; + } + } else { + if (wmi_addBadAp_cmd(ar->arWmi, cmd.badApIndex, cmd.bssid) != A_OK) { + ret = -EIO; + } + } + + return ret; +} + +static int +ar6000_ioctl_create_qos(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_CREATE_PSTREAM_CMD cmd; + A_STATUS ret; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + ret = wmi_verify_tspec_params(&cmd, tspecCompliance); + if (ret == A_OK) + ret = wmi_create_pstream_cmd(ar->arWmi, &cmd); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_delete_qos(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_DELETE_PSTREAM_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + ret = wmi_delete_pstream_cmd(ar->arWmi, cmd.trafficClass, cmd.tsid); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_get_qos_queue(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + struct ar6000_queuereq qreq; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if( copy_from_user(&qreq, rq->ifr_data, + sizeof(struct ar6000_queuereq))) + return -EFAULT; + + qreq.activeTsids = wmi_get_mapped_qos_queue(ar->arWmi, qreq.trafficClass); + + if (copy_to_user(rq->ifr_data, &qreq, + sizeof(struct ar6000_queuereq))) + { + ret = -EFAULT; + } + + return ret; +} + +#ifdef CONFIG_HOST_TCMD_SUPPORT +static A_STATUS +ar6000_ioctl_tcmd_get_rx_report(struct net_device *dev, + struct ifreq *rq, A_UINT8 *data, A_UINT32 len) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_UINT32 buf[4]; + int ret = 0; + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + ar->tcmdRxReport = 0; + if (wmi_test_cmd(ar->arWmi, data, len) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->tcmdRxReport != 0, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + + buf[0] = ar->tcmdRxTotalPkt; + buf[1] = ar->tcmdRxRssi; + buf[2] = ar->tcmdRxcrcErrPkt; + buf[3] = ar->tcmdRxsecErrPkt; + if (!ret && copy_to_user(rq->ifr_data, buf, sizeof(buf))) { + ret = -EFAULT; + } + + up(&ar->arSem); + + return ret; +} + +void +ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + TCMD_CONT_RX * rx_rep = (TCMD_CONT_RX *)results; + + ar->tcmdRxTotalPkt = rx_rep->u.report.totalPkt; + ar->tcmdRxRssi = rx_rep->u.report.rssiInDBm; + ar->tcmdRxcrcErrPkt = rx_rep->u.report.crcErrPkt; + ar->tcmdRxsecErrPkt = rx_rep->u.report.secErrPkt; + ar->tcmdRxReport = 1; + + wake_up(&arEvent); +} +#endif /* CONFIG_HOST_TCMD_SUPPORT*/ + +static int +ar6000_ioctl_set_error_report_bitmask(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_TARGET_ERROR_REPORT_BITMASK cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + ret = wmi_set_error_report_bitmask(ar->arWmi, cmd.bitmask); + + return (ret==0 ? ret : -EINVAL); +} + +static int +ar6000_clear_target_stats(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + TARGET_STATS *pStats = &ar->arTargetStats; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + AR6000_SPIN_LOCK(&ar->arLock, 0); + A_MEMZERO(pStats, sizeof(TARGET_STATS)); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + return ret; +} + +static int +ar6000_ioctl_get_target_stats(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + TARGET_STATS_CMD cmd; + TARGET_STATS *pStats = &ar->arTargetStats; + int ret = 0; + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + ar->statsUpdatePending = TRUE; + + if(wmi_get_stats_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + + if (!ret && copy_to_user(rq->ifr_data, pStats, sizeof(*pStats))) { + ret = -EFAULT; + } + + if (cmd.clearStats == 1) { + ret = ar6000_clear_target_stats(dev); + } + + up(&ar->arSem); + + return ret; +} + +static int +ar6000_ioctl_set_access_params(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_ACCESS_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_access_params_cmd(ar->arWmi, cmd.txop, cmd.eCWmin, cmd.eCWmax, + cmd.aifsn) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +static int +ar6000_ioctl_set_disconnect_timeout(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_DISC_TIMEOUT_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_disctimeout_cmd(ar->arWmi, cmd.disconnectTimeout) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +static int +ar6000_xioctl_set_voice_pkt_size(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_VOICE_PKT_SIZE_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_voice_pkt_size_cmd(ar->arWmi, cmd.voicePktSize) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + + return (ret); +} + +static int +ar6000_xioctl_set_max_sp_len(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_MAX_SP_LEN_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_max_sp_len_cmd(ar->arWmi, cmd.maxSPLen) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + + +static int +ar6000_xioctl_set_bt_status_cmd(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_BT_STATUS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_bt_status_cmd(ar->arWmi, cmd.streamType, cmd.status) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +static int +ar6000_xioctl_set_bt_params_cmd(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_SET_BT_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_bt_params_cmd(ar->arWmi, &cmd) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +#ifdef CONFIG_HOST_GPIO_SUPPORT +struct ar6000_gpio_intr_wait_cmd_s gpio_intr_results; +/* gpio_reg_results and gpio_data_available are protected by arSem */ +static struct ar6000_gpio_register_cmd_s gpio_reg_results; +static A_BOOL gpio_data_available; /* Requested GPIO data available */ +static A_BOOL gpio_intr_available; /* GPIO interrupt info available */ +static A_BOOL gpio_ack_received; /* GPIO ack was received */ + +/* Host-side initialization for General Purpose I/O support */ +void ar6000_gpio_init(void) +{ + gpio_intr_available = FALSE; + gpio_data_available = FALSE; + gpio_ack_received = FALSE; +} + +/* + * Called when a GPIO interrupt is received from the Target. + * intr_values shows which GPIO pins have interrupted. + * input_values shows a recent value of GPIO pins. + */ +void +ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values) +{ + gpio_intr_results.intr_mask = intr_mask; + gpio_intr_results.input_values = input_values; + *((volatile A_BOOL *)&gpio_intr_available) = TRUE; + wake_up(&arEvent); +} + +/* + * This is called when a response is received from the Target + * for a previous or ar6000_gpio_input_get or ar6000_gpio_register_get + * call. + */ +void +ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value) +{ + gpio_reg_results.gpioreg_id = reg_id; + gpio_reg_results.value = value; + *((volatile A_BOOL *)&gpio_data_available) = TRUE; + wake_up(&arEvent); +} + +/* + * This is called when an acknowledgement is received from the Target + * for a previous or ar6000_gpio_output_set or ar6000_gpio_register_set + * call. + */ +void +ar6000_gpio_ack_rx(void) +{ + gpio_ack_received = TRUE; + wake_up(&arEvent); +} + +A_STATUS +ar6000_gpio_output_set(struct net_device *dev, + A_UINT32 set_mask, + A_UINT32 clear_mask, + A_UINT32 enable_mask, + A_UINT32 disable_mask) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + gpio_ack_received = FALSE; + return wmi_gpio_output_set(ar->arWmi, + set_mask, clear_mask, enable_mask, disable_mask); +} + +static A_STATUS +ar6000_gpio_input_get(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + *((volatile A_BOOL *)&gpio_data_available) = FALSE; + return wmi_gpio_input_get(ar->arWmi); +} + +static A_STATUS +ar6000_gpio_register_set(struct net_device *dev, + A_UINT32 gpioreg_id, + A_UINT32 value) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + gpio_ack_received = FALSE; + return wmi_gpio_register_set(ar->arWmi, gpioreg_id, value); +} + +static A_STATUS +ar6000_gpio_register_get(struct net_device *dev, + A_UINT32 gpioreg_id) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + *((volatile A_BOOL *)&gpio_data_available) = FALSE; + return wmi_gpio_register_get(ar->arWmi, gpioreg_id); +} + +static A_STATUS +ar6000_gpio_intr_ack(struct net_device *dev, + A_UINT32 ack_mask) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + gpio_intr_available = FALSE; + return wmi_gpio_intr_ack(ar->arWmi, ack_mask); +} +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +static struct prof_count_s prof_count_results; +static A_BOOL prof_count_available; /* Requested GPIO data available */ + +static A_STATUS +prof_count_get(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + *((volatile A_BOOL *)&prof_count_available) = FALSE; + return wmi_prof_count_get_cmd(ar->arWmi); +} + +/* + * This is called when a response is received from the Target + * for a previous prof_count_get call. + */ +void +prof_count_rx(A_UINT32 addr, A_UINT32 count) +{ + prof_count_results.addr = addr; + prof_count_results.count = count; + *((volatile A_BOOL *)&prof_count_available) = TRUE; + wake_up(&arEvent); +} +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + +int +ar6000_ioctl_setparam(AR_SOFTC_T *ar, int param, int value) +{ + A_BOOL profChanged = FALSE; + int ret=0; + + switch (param) { + case IEEE80211_PARAM_WPA: + switch (value) { + case WPA_MODE_WPA1: + ar->arAuthMode = WPA_AUTH; + profChanged = TRUE; + break; + case WPA_MODE_WPA2: + ar->arAuthMode = WPA2_AUTH; + profChanged = TRUE; + break; + case WPA_MODE_NONE: + ar->arAuthMode = NONE_AUTH; + profChanged = TRUE; + break; + } + break; + case IEEE80211_PARAM_AUTHMODE: + switch(value) { + case IEEE80211_AUTH_WPA_PSK: + if (WPA_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA_PSK_AUTH; + profChanged = TRUE; + } else if (WPA2_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA2_PSK_AUTH; + profChanged = TRUE; + } else { + AR_DEBUG_PRINTF("Error - Setting PSK "\ + "mode when WPA param was set to %d\n", + ar->arAuthMode); + ret = -EIO; + } + break; + case IEEE80211_AUTH_WPA_CCKM: + if (WPA2_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA2_AUTH_CCKM; + } else { + ar->arAuthMode = WPA_AUTH_CCKM; + } + break; + default: + break; + } + break; + case IEEE80211_PARAM_UCASTCIPHER: + switch (value) { + case IEEE80211_CIPHER_AES_CCM: + ar->arPairwiseCrypto = AES_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_TKIP: + ar->arPairwiseCrypto = TKIP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_WEP: + ar->arPairwiseCrypto = WEP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_NONE: + ar->arPairwiseCrypto = NONE_CRYPT; + profChanged = TRUE; + break; + } + break; + case IEEE80211_PARAM_UCASTKEYLEN: + if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) { + ret = -EIO; + } else { + ar->arPairwiseCryptoLen = value; + } + break; + case IEEE80211_PARAM_MCASTCIPHER: + switch (value) { + case IEEE80211_CIPHER_AES_CCM: + ar->arGroupCrypto = AES_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_TKIP: + ar->arGroupCrypto = TKIP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_WEP: + ar->arGroupCrypto = WEP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_NONE: + ar->arGroupCrypto = NONE_CRYPT; + profChanged = TRUE; + break; + } + break; + case IEEE80211_PARAM_MCASTKEYLEN: + if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) { + ret = -EIO; + } else { + ar->arGroupCryptoLen = value; + } + break; + case IEEE80211_PARAM_COUNTERMEASURES: + if (ar->arWmiReady == FALSE) { + return -EIO; + } + wmi_set_tkip_countermeasures_cmd(ar->arWmi, value); + break; + default: + break; + } + if ((ar->arNextMode != AP_NETWORK) && (profChanged == TRUE)) { + /* + * profile has changed. Erase ssid to signal change + */ + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + } + ar->ap_profile_flag = 1; /* There is a change in profile */ + + return ret; +} + +int +ar6000_ioctl_setkey(AR_SOFTC_T *ar, struct ieee80211req_key *ik) +{ + KEY_USAGE keyUsage; + A_STATUS status; + CRYPTO_TYPE keyType = NONE_CRYPT; + A_UINT8 null_addr[]={0x0,0x0,0x0,0x0,0x0,0x0}; + A_UINT8 bcast_addr[]={0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}; + +#ifdef USER_KEYS + ar->user_saved_keys.keyOk = FALSE; +#endif + if ( (0 == memcmp(ik->ik_macaddr, null_addr, IEEE80211_ADDR_LEN)) || + (0 == memcmp(ik->ik_macaddr, bcast_addr, IEEE80211_ADDR_LEN)) ) { + keyUsage = GROUP_USAGE; + if(ar->arNextMode == AP_NETWORK) { + A_MEMCPY(&ar->ap_mode_bkey, ik, + sizeof(struct ieee80211req_key)); + } +#ifdef USER_KEYS + A_MEMCPY(&ar->user_saved_keys.bcast_ik, ik, + sizeof(struct ieee80211req_key)); +#endif + } else { + keyUsage = PAIRWISE_USAGE; +#ifdef USER_KEYS + A_MEMCPY(&ar->user_saved_keys.ucast_ik, ik, + sizeof(struct ieee80211req_key)); +#endif + } + + switch (ik->ik_type) { + case IEEE80211_CIPHER_WEP: + keyType = WEP_CRYPT; + break; + case IEEE80211_CIPHER_TKIP: + keyType = TKIP_CRYPT; + break; + case IEEE80211_CIPHER_AES_CCM: + keyType = AES_CRYPT; + break; + default: + break; + } + + if (ik->ik_flags & IEEE80211_KEY_XMIT) + { + keyUsage |= TX_USAGE; + } + +#ifdef USER_KEYS + ar->user_saved_keys.keyType = keyType; +#endif + if (IEEE80211_CIPHER_CCKM_KRK != ik->ik_type) { + if (NONE_CRYPT == keyType) { + return -EIO; + } + + if (((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)) && + (GROUP_USAGE == keyUsage)) + { + A_UNTIMEOUT(&ar->disconnect_timer); + } + + status = wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, keyUsage, + ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc, + ik->ik_keydata, KEY_OP_INIT_VAL, ik->ik_macaddr, + SYNC_BOTH_WMIFLAG); + + if (status != A_OK) { + return -EIO; + } + } else { + status = wmi_add_krk_cmd(ar->arWmi, ik->ik_keydata); + } + +#ifdef USER_KEYS + ar->user_saved_keys.keyOk = TRUE; +#endif + + return 0; +} + +int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + HIF_DEVICE *hifDevice = ar->arHifDevice; + int ret, param; + unsigned int address = 0; + unsigned int length = 0; + unsigned char *buffer; + char *userdata; + A_UINT32 connectCtrlFlags; + + + static WMI_SCAN_PARAMS_CMD scParams = {0, 0, 0, 0, 0, + WMI_SHORTSCANRATIO_DEFAULT, + DEFAULT_SCAN_CTRL_FLAGS, + 0}; + WMI_SET_AKMP_PARAMS_CMD akmpParams; + WMI_SET_PMKID_LIST_CMD pmkidInfo; + + if (cmd == AR6000_IOCTL_EXTENDED) { + /* + * This allows for many more wireless ioctls than would otherwise + * be available. Applications embed the actual ioctl command in + * the first word of the parameter block, and use the command + * AR6000_IOCTL_EXTENDED_CMD on the ioctl call. + */ + get_user(cmd, (int *)rq->ifr_data); + userdata = (char *)(((unsigned int *)rq->ifr_data)+1); + + if(is_xioctl_allowed(ar->arNextMode, cmd) != A_OK) { + A_PRINTF("xioctl: cmd=%d not allowed in this mode\n",cmd); + return -EOPNOTSUPP; + } + } else { + A_STATUS ret = is_iwioctl_allowed(ar->arNextMode, cmd); + if(ret == A_ENOTSUP) { + A_PRINTF("iwioctl: cmd=0x%x not allowed in this mode\n", cmd); + return -EOPNOTSUPP; + } else if (ret == A_ERROR) { + /* It is not our ioctl (out of range ioctl) */ + return -EOPNOTSUPP; + } + userdata = (char *)rq->ifr_data; + } + + if ((ar->arWlanState == WLAN_DISABLED) && + ((cmd != AR6000_XIOCTRL_WMI_SET_WLAN_STATE) && + (cmd != AR6000_XIOCTL_DIAG_READ) && + (cmd != AR6000_XIOCTL_DIAG_WRITE))) + { + return -EIO; + } + + ret = 0; + switch(cmd) + { + case IEEE80211_IOCTL_SETPARAM: + { + int param, value; + int *ptr = (int *)rq->ifr_ifru.ifru_newname; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + param = *ptr++; + value = *ptr; + ret = ar6000_ioctl_setparam(ar,param,value); + } + break; + } + case IEEE80211_IOCTL_SETKEY: + { + struct ieee80211req_key keydata; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&keydata, userdata, + sizeof(struct ieee80211req_key))) { + ret = -EFAULT; + } else { + ar6000_ioctl_setkey(ar, &keydata); + } + break; + } + case IEEE80211_IOCTL_DELKEY: + case IEEE80211_IOCTL_SETOPTIE: + { + //ret = -EIO; + break; + } + case IEEE80211_IOCTL_SETMLME: + { + struct ieee80211req_mlme mlme; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&mlme, userdata, + sizeof(struct ieee80211req_mlme))) { + ret = -EFAULT; + } else { + switch (mlme.im_op) { + case IEEE80211_MLME_AUTHORIZE: + A_PRINTF("setmlme AUTHORIZE %02X:%02X\n", + mlme.im_macaddr[4], mlme.im_macaddr[5]); + break; + case IEEE80211_MLME_UNAUTHORIZE: + A_PRINTF("setmlme UNAUTHORIZE %02X:%02X\n", + mlme.im_macaddr[4], mlme.im_macaddr[5]); + break; + case IEEE80211_MLME_DEAUTH: + A_PRINTF("setmlme DEAUTH %02X:%02X\n", + mlme.im_macaddr[4], mlme.im_macaddr[5]); + //remove_sta(ar, mlme.im_macaddr); + break; + case IEEE80211_MLME_DISASSOC: + A_PRINTF("setmlme DISASSOC %02X:%02X\n", + mlme.im_macaddr[4], mlme.im_macaddr[5]); + //remove_sta(ar, mlme.im_macaddr); + break; + default: + return 0; + } + + wmi_ap_set_mlme(ar->arWmi, mlme.im_op, mlme.im_macaddr, + mlme.im_reason); + } + break; + } + case IEEE80211_IOCTL_ADDPMKID: + { + struct ieee80211req_addpmkid req; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&req, userdata, sizeof(struct ieee80211req_addpmkid))) { + ret = -EFAULT; + } else { + A_STATUS status; + + AR_DEBUG_PRINTF("Add pmkid for %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x en=%d\n", + req.pi_bssid[0], req.pi_bssid[1], req.pi_bssid[2], + req.pi_bssid[3], req.pi_bssid[4], req.pi_bssid[5], + req.pi_enable); + + status = wmi_setPmkid_cmd(ar->arWmi, req.pi_bssid, req.pi_pmkid, + req.pi_enable); + + if (status != A_OK) { + return -EIO; + } + } + break; + } +#ifdef CONFIG_HOST_TCMD_SUPPORT + case AR6000_XIOCTL_TCMD_CONT_TX: + { + TCMD_CONT_TX txCmd; + + if (ar->tcmdPm == TCMD_PM_SLEEP) { + A_PRINTF("Can NOT send tx tcmd when target is asleep! \n"); + return -EFAULT; + } + + if(copy_from_user(&txCmd, userdata, sizeof(TCMD_CONT_TX))) + return -EFAULT; + wmi_test_cmd(ar->arWmi,(A_UINT8 *)&txCmd, sizeof(TCMD_CONT_TX)); + } + break; + case AR6000_XIOCTL_TCMD_CONT_RX: + { + TCMD_CONT_RX rxCmd; + + if (ar->tcmdPm == TCMD_PM_SLEEP) { + A_PRINTF("Can NOT send rx tcmd when target is asleep! \n"); + return -EFAULT; + } + if(copy_from_user(&rxCmd, userdata, sizeof(TCMD_CONT_RX))) + return -EFAULT; + switch(rxCmd.act) + { + case TCMD_CONT_RX_PROMIS: + case TCMD_CONT_RX_FILTER: + case TCMD_CONT_RX_SETMAC: + case TCMD_CONT_RX_SET_ANT_SWITCH_TABLE: + wmi_test_cmd(ar->arWmi,(A_UINT8 *)&rxCmd, + sizeof(TCMD_CONT_RX)); + break; + case TCMD_CONT_RX_REPORT: + ar6000_ioctl_tcmd_get_rx_report(dev, rq, + (A_UINT8 *)&rxCmd, sizeof(TCMD_CONT_RX)); + break; + default: + A_PRINTF("Unknown Cont Rx mode: %d\n",rxCmd.act); + return -EINVAL; + } + } + break; + case AR6000_XIOCTL_TCMD_PM: + { + TCMD_PM pmCmd; + + if(copy_from_user(&pmCmd, userdata, sizeof(TCMD_PM))) + return -EFAULT; + ar->tcmdPm = pmCmd.mode; + wmi_test_cmd(ar->arWmi, (A_UINT8*)&pmCmd, sizeof(TCMD_PM)); + } + break; +#endif /* CONFIG_HOST_TCMD_SUPPORT */ + + case AR6000_XIOCTL_BMI_DONE: + if(bmienable) + { + ret = ar6000_init(dev); + } + else + { + ret = BMIDone(hifDevice); + } + break; + + case AR6000_XIOCTL_BMI_READ_MEMORY: + get_user(address, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + AR_DEBUG_PRINTF("Read Memory (address: 0x%x, length: %d)\n", + address, length); + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + ret = BMIReadMemory(hifDevice, address, buffer, length); + if (copy_to_user(rq->ifr_data, buffer, length)) { + ret = -EFAULT; + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + break; + + case AR6000_XIOCTL_BMI_WRITE_MEMORY: + get_user(address, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + AR_DEBUG_PRINTF("Write Memory (address: 0x%x, length: %d)\n", + address, length); + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + if (copy_from_user(buffer, &userdata[sizeof(address) + + sizeof(length)], length)) + { + ret = -EFAULT; + } else { + ret = BMIWriteMemory(hifDevice, address, buffer, length); + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + break; + + case AR6000_XIOCTL_BMI_TEST: + AR_DEBUG_PRINTF("No longer supported\n"); + ret = -EOPNOTSUPP; + break; + + case AR6000_XIOCTL_BMI_EXECUTE: + get_user(address, (unsigned int *)userdata); + get_user(param, (unsigned int *)userdata + 1); + AR_DEBUG_PRINTF("Execute (address: 0x%x, param: %d)\n", + address, param); + ret = BMIExecute(hifDevice, address, ¶m); + put_user(param, (unsigned int *)rq->ifr_data); /* return value */ + break; + + case AR6000_XIOCTL_BMI_SET_APP_START: + get_user(address, (unsigned int *)userdata); + AR_DEBUG_PRINTF("Set App Start (address: 0x%x)\n", address); + ret = BMISetAppStart(hifDevice, address); + break; + + case AR6000_XIOCTL_BMI_READ_SOC_REGISTER: + get_user(address, (unsigned int *)userdata); + ret = BMIReadSOCRegister(hifDevice, address, ¶m); + put_user(param, (unsigned int *)rq->ifr_data); /* return value */ + break; + + case AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER: + get_user(address, (unsigned int *)userdata); + get_user(param, (unsigned int *)userdata + 1); + ret = BMIWriteSOCRegister(hifDevice, address, param); + break; + +#ifdef HTC_RAW_INTERFACE + case AR6000_XIOCTL_HTC_RAW_OPEN: + ret = A_OK; + if (!arRawIfEnabled(ar)) { + /* make sure block size is set in case the target was reset since last + * BMI phase (i.e. flashup downloads) */ + ret = ar6000_set_htc_params(ar->arHifDevice, + ar->arTargetType, + 0, /* use default yield */ + 0 /* use default number of HTC ctrl buffers */ + ); + if (A_FAILED(ret)) { + break; + } + /* Terminate the BMI phase */ + ret = BMIDone(hifDevice); + if (ret == A_OK) { + ret = ar6000_htc_raw_open(ar); + } + } + break; + + case AR6000_XIOCTL_HTC_RAW_CLOSE: + if (arRawIfEnabled(ar)) { + ret = ar6000_htc_raw_close(ar); + arRawIfEnabled(ar) = FALSE; + } else { + ret = A_ERROR; + } + break; + + case AR6000_XIOCTL_HTC_RAW_READ: + if (arRawIfEnabled(ar)) { + unsigned int streamID; + get_user(streamID, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + mb(); /* Memory barrier */ + buffer = rq->ifr_data + sizeof(length); + ret = ar6000_htc_raw_read(ar, (HTC_RAW_STREAM_ID)streamID, + buffer, length); + put_user(ret, (unsigned int *)rq->ifr_data); + } else { + ret = A_ERROR; + } + break; + + case AR6000_XIOCTL_HTC_RAW_WRITE: + if (arRawIfEnabled(ar)) { + unsigned int streamID; + get_user(streamID, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + mb(); /* Memory barrier */ + buffer = userdata + sizeof(streamID) + sizeof(length); + ret = ar6000_htc_raw_write(ar, (HTC_RAW_STREAM_ID)streamID, + buffer, length); + put_user(ret, (unsigned int *)rq->ifr_data); + } else { + ret = A_ERROR; + } + break; +#endif /* HTC_RAW_INTERFACE */ + + case AR6000_XIOCTL_BMI_LZ_STREAM_START: + get_user(address, (unsigned int *)userdata); + AR_DEBUG_PRINTF("Start Compressed Stream (address: 0x%x)\n", address); + ret = BMILZStreamStart(hifDevice, address); + break; + + case AR6000_XIOCTL_BMI_LZ_DATA: + get_user(length, (unsigned int *)userdata); + AR_DEBUG_PRINTF("Send Compressed Data (length: %d)\n", length); + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + if (copy_from_user(buffer, &userdata[sizeof(length)], length)) + { + ret = -EFAULT; + } else { + ret = BMILZData(hifDevice, buffer, length); + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + break; + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) + /* + * Optional support for Target-side profiling. + * Not needed in production. + */ + + /* Configure Target-side profiling */ + case AR6000_XIOCTL_PROF_CFG: + { + A_UINT32 period; + A_UINT32 nbins; + get_user(period, (unsigned int *)userdata); + get_user(nbins, (unsigned int *)userdata + 1); + + if (wmi_prof_cfg_cmd(ar->arWmi, period, nbins) != A_OK) { + ret = -EIO; + } + + break; + } + + /* Start a profiling bucket/bin at the specified address */ + case AR6000_XIOCTL_PROF_ADDR_SET: + { + A_UINT32 addr; + get_user(addr, (unsigned int *)userdata); + + if (wmi_prof_addr_set_cmd(ar->arWmi, addr) != A_OK) { + ret = -EIO; + } + + break; + } + + /* START Target-side profiling */ + case AR6000_XIOCTL_PROF_START: + wmi_prof_start_cmd(ar->arWmi); + break; + + /* STOP Target-side profiling */ + case AR6000_XIOCTL_PROF_STOP: + wmi_prof_stop_cmd(ar->arWmi); + break; + case AR6000_XIOCTL_PROF_COUNT_GET: + { + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + prof_count_available = FALSE; + ret = prof_count_get(dev); + if (ret != A_OK) { + up(&ar->arSem); + return -EIO; + } + + /* Wait for Target to respond. */ + wait_event_interruptible(arEvent, prof_count_available); + if (signal_pending(current)) { + ret = -EINTR; + } else { + if (copy_to_user(userdata, &prof_count_results, + sizeof(prof_count_results))) + { + ret = -EFAULT; + } + } + up(&ar->arSem); + break; + } +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + + case AR6000_IOCTL_WMI_GETREV: + { + if (copy_to_user(rq->ifr_data, &ar->arVersion, + sizeof(ar->arVersion))) + { + ret = -EFAULT; + } + break; + } + case AR6000_IOCTL_WMI_SETPWR: + { + WMI_POWER_MODE_CMD pwrModeCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&pwrModeCmd, userdata, + sizeof(pwrModeCmd))) + { + ret = -EFAULT; + } else { + if (wmi_powermode_cmd(ar->arWmi, pwrModeCmd.powerMode) + != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_FORCE_ASSERT: + { + if (wmi_force_target_assert(ar->arWmi) != A_OK) + { + ret = -EIO; + } + break; + } + case AR6000_IOCTL_WMI_SET_PMPARAMS: + { + WMI_POWER_PARAMS_CMD pmParams; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&pmParams, userdata, + sizeof(pmParams))) + { + ret = -EFAULT; + } else { + if (wmi_pmparams_cmd(ar->arWmi, pmParams.idle_period, + pmParams.pspoll_number, + pmParams.dtim_policy) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SETSCAN: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&scParams, userdata, + sizeof(scParams))) + { + ret = -EFAULT; + } else { + if (CAN_SCAN_IN_CONNECT(scParams.scanCtrlFlags)) { + ar->arSkipScan = FALSE; + } else { + ar->arSkipScan = TRUE; + } + + if (wmi_scanparams_cmd(ar->arWmi, scParams.fg_start_period, + scParams.fg_end_period, + scParams.bg_period, + scParams.minact_chdwell_time, + scParams.maxact_chdwell_time, + scParams.pas_chdwell_time, + scParams.shortScanRatio, + scParams.scanCtrlFlags, + scParams.max_dfsch_act_time, + scParams.maxact_scan_per_ssid) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SETLISTENINT: + { + WMI_LISTEN_INT_CMD listenCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&listenCmd, userdata, + sizeof(listenCmd))) + { + ret = -EFAULT; + } else { + if (wmi_listeninterval_cmd(ar->arWmi, listenCmd.listenInterval, listenCmd.numBeacons) != A_OK) { + ret = -EIO; + } else { + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arListenInterval = param; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + + } + break; + } + case AR6000_IOCTL_WMI_SET_BMISS_TIME: + { + WMI_BMISS_TIME_CMD bmissCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&bmissCmd, userdata, + sizeof(bmissCmd))) + { + ret = -EFAULT; + } else { + if (wmi_bmisstime_cmd(ar->arWmi, bmissCmd.bmissTime, bmissCmd.numBeacons) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SETBSSFILTER: + { + WMI_BSS_FILTER_CMD filt; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&filt, userdata, + sizeof(filt))) + { + ret = -EFAULT; + } else { + if (wmi_bssfilter_cmd(ar->arWmi, filt.bssFilter, filt.ieMask) + != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SET_SNRTHRESHOLD: + { + ret = ar6000_ioctl_set_snr_threshold(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD: + { + ret = ar6000_ioctl_set_rssi_threshold(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_CLR_RSSISNR: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } + ret = wmi_clr_rssi_snr(ar->arWmi); + break; + } + case AR6000_XIOCTL_WMI_SET_LQTHRESHOLD: + { + ret = ar6000_ioctl_set_lq_threshold(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_SET_LPREAMBLE: + { + WMI_SET_LPREAMBLE_CMD setLpreambleCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setLpreambleCmd, userdata, + sizeof(setLpreambleCmd))) + { + ret = -EFAULT; + } else { + if (wmi_set_lpreamble_cmd(ar->arWmi, setLpreambleCmd.status) + != A_OK) + { + ret = -EIO; + } + } + + break; + } + case AR6000_XIOCTL_WMI_SET_RTS: + { + WMI_SET_RTS_CMD rtsCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&rtsCmd, userdata, + sizeof(rtsCmd))) + { + ret = -EFAULT; + } else { + if (wmi_set_rts_cmd(ar->arWmi, rtsCmd.threshold) + != A_OK) + { + ret = -EIO; + } + } + + break; + } + case AR6000_XIOCTL_WMI_SET_WMM: + { + ret = ar6000_ioctl_set_wmm(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_SET_TXOP: + { + ret = ar6000_ioctl_set_txop(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_GET_RD: + { + ret = ar6000_ioctl_get_rd(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_CHANNELPARAMS: + { + ret = ar6000_ioctl_set_channelParams(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_PROBEDSSID: + { + ret = ar6000_ioctl_set_probedSsid(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_BADAP: + { + ret = ar6000_ioctl_set_badAp(dev, rq); + break; + } + case AR6000_IOCTL_WMI_CREATE_QOS: + { + ret = ar6000_ioctl_create_qos(dev, rq); + break; + } + case AR6000_IOCTL_WMI_DELETE_QOS: + { + ret = ar6000_ioctl_delete_qos(dev, rq); + break; + } + case AR6000_IOCTL_WMI_GET_QOS_QUEUE: + { + ret = ar6000_ioctl_get_qos_queue(dev, rq); + break; + } + case AR6000_IOCTL_WMI_GET_TARGET_STATS: + { + ret = ar6000_ioctl_get_target_stats(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK: + { + ret = ar6000_ioctl_set_error_report_bitmask(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_ASSOC_INFO: + { + WMI_SET_ASSOC_INFO_CMD cmd; + A_UINT8 assocInfo[WMI_MAX_ASSOC_INFO_LEN]; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + get_user(cmd.ieType, userdata); + if (cmd.ieType >= WMI_MAX_ASSOC_INFO_TYPE) { + ret = -EIO; + } else { + get_user(cmd.bufferSize, userdata + 1); + if (cmd.bufferSize > WMI_MAX_ASSOC_INFO_LEN) { + ret = -EFAULT; + break; + } + if (copy_from_user(assocInfo, userdata + 2, + cmd.bufferSize)) + { + ret = -EFAULT; + } else { + if (wmi_associnfo_cmd(ar->arWmi, cmd.ieType, + cmd.bufferSize, + assocInfo) != A_OK) + { + ret = -EIO; + } + } + } + } + break; + } + case AR6000_IOCTL_WMI_SET_ACCESS_PARAMS: + { + ret = ar6000_ioctl_set_access_params(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_DISC_TIMEOUT: + { + ret = ar6000_ioctl_set_disconnect_timeout(dev, rq); + break; + } + case AR6000_XIOCTL_FORCE_TARGET_RESET: + { + if (ar->arHtcTarget) + { +// HTCForceReset(htcTarget); + } + else + { + AR_DEBUG_PRINTF("ar6000_ioctl cannot attempt reset.\n"); + } + break; + } + case AR6000_XIOCTL_TARGET_INFO: + case AR6000_XIOCTL_CHECK_TARGET_READY: /* backwards compatibility */ + { + /* If we made it to here, then the Target exists and is ready. */ + + if (cmd == AR6000_XIOCTL_TARGET_INFO) { + if (copy_to_user((A_UINT32 *)rq->ifr_data, &ar->arVersion.target_ver, + sizeof(ar->arVersion.target_ver))) + { + ret = -EFAULT; + } + if (copy_to_user(((A_UINT32 *)rq->ifr_data)+1, &ar->arTargetType, + sizeof(ar->arTargetType))) + { + ret = -EFAULT; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS: + { + WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD hbparam; + + if (copy_from_user(&hbparam, userdata, sizeof(hbparam))) + { + ret = -EFAULT; + } else { + AR6000_SPIN_LOCK(&ar->arLock, 0); + /* Start a cyclic timer with the parameters provided. */ + if (hbparam.frequency) { + ar->arHBChallengeResp.frequency = hbparam.frequency; + } + if (hbparam.threshold) { + ar->arHBChallengeResp.missThres = hbparam.threshold; + } + + /* Delete the pending timer and start a new one */ + if (timer_pending(&ar->arHBChallengeResp.timer)) { + A_UNTIMEOUT(&ar->arHBChallengeResp.timer); + } + A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + break; + } + case AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP: + { + A_UINT32 cookie; + + if (copy_from_user(&cookie, userdata, sizeof(cookie))) { + return -EFAULT; + } + + /* Send the challenge on the control channel */ + if (wmi_get_challenge_resp_cmd(ar->arWmi, cookie, APP_HB_CHALLENGE) != A_OK) { + return -EIO; + } + break; + } +#ifdef USER_KEYS + case AR6000_XIOCTL_USER_SETKEYS: + { + + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_RUN; + + if (copy_from_user(&ar->user_key_ctrl, userdata, + sizeof(ar->user_key_ctrl))) + { + return -EFAULT; + } + + A_PRINTF("ar6000 USER set key %x\n", ar->user_key_ctrl); + break; + } +#endif /* USER_KEYS */ + +#ifdef CONFIG_HOST_GPIO_SUPPORT + case AR6000_XIOCTL_GPIO_OUTPUT_SET: + { + struct ar6000_gpio_output_set_cmd_s gpio_output_set_cmd; + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + if (copy_from_user(&gpio_output_set_cmd, userdata, + sizeof(gpio_output_set_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_output_set(dev, + gpio_output_set_cmd.set_mask, + gpio_output_set_cmd.clear_mask, + gpio_output_set_cmd.enable_mask, + gpio_output_set_cmd.disable_mask); + if (ret != A_OK) { + ret = EIO; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_INPUT_GET: + { + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + ret = ar6000_gpio_input_get(dev); + if (ret != A_OK) { + up(&ar->arSem); + return -EIO; + } + + /* Wait for Target to respond. */ + wait_event_interruptible(arEvent, gpio_data_available); + if (signal_pending(current)) { + ret = -EINTR; + } else { + A_ASSERT(gpio_reg_results.gpioreg_id == GPIO_ID_NONE); + + if (copy_to_user(userdata, &gpio_reg_results.value, + sizeof(gpio_reg_results.value))) + { + ret = -EFAULT; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_REGISTER_SET: + { + struct ar6000_gpio_register_cmd_s gpio_register_cmd; + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + if (copy_from_user(&gpio_register_cmd, userdata, + sizeof(gpio_register_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_register_set(dev, + gpio_register_cmd.gpioreg_id, + gpio_register_cmd.value); + if (ret != A_OK) { + ret = EIO; + } + + /* Wait for acknowledgement from Target */ + wait_event_interruptible(arEvent, gpio_ack_received); + if (signal_pending(current)) { + ret = -EINTR; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_REGISTER_GET: + { + struct ar6000_gpio_register_cmd_s gpio_register_cmd; + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + if (copy_from_user(&gpio_register_cmd, userdata, + sizeof(gpio_register_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_register_get(dev, gpio_register_cmd.gpioreg_id); + if (ret != A_OK) { + up(&ar->arSem); + return -EIO; + } + + /* Wait for Target to respond. */ + wait_event_interruptible(arEvent, gpio_data_available); + if (signal_pending(current)) { + ret = -EINTR; + } else { + A_ASSERT(gpio_register_cmd.gpioreg_id == gpio_reg_results.gpioreg_id); + if (copy_to_user(userdata, &gpio_reg_results, + sizeof(gpio_reg_results))) + { + ret = -EFAULT; + } + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_INTR_ACK: + { + struct ar6000_gpio_intr_ack_cmd_s gpio_intr_ack_cmd; + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + if (copy_from_user(&gpio_intr_ack_cmd, userdata, + sizeof(gpio_intr_ack_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_intr_ack(dev, gpio_intr_ack_cmd.ack_mask); + if (ret != A_OK) { + ret = EIO; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_INTR_WAIT: + { + /* Wait for Target to report an interrupt. */ + dev_hold(dev); + rtnl_unlock(); + wait_event_interruptible(arEvent, gpio_intr_available); + rtnl_lock(); + __dev_put(dev); + + if (signal_pending(current)) { + ret = -EINTR; + } else { + if (copy_to_user(userdata, &gpio_intr_results, + sizeof(gpio_intr_results))) + { + ret = -EFAULT; + } + } + break; + } +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + + case AR6000_XIOCTL_DBGLOG_CFG_MODULE: + { + struct ar6000_dbglog_module_config_s config; + + if (copy_from_user(&config, userdata, sizeof(config))) { + return -EFAULT; + } + + /* Send the challenge on the control channel */ + if (wmi_config_debug_module_cmd(ar->arWmi, config.mmask, + config.tsr, config.rep, + config.size, config.valid) != A_OK) + { + return -EIO; + } + break; + } + + case AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS: + { + /* Send the challenge on the control channel */ + if (ar6000_dbglog_get_debug_logs(ar) != A_OK) + { + return -EIO; + } + break; + } + + case AR6000_XIOCTL_SET_ADHOC_BSSID: + { + WMI_SET_ADHOC_BSSID_CMD adhocBssid; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&adhocBssid, userdata, + sizeof(adhocBssid))) + { + ret = -EFAULT; + } else if (A_MEMCMP(adhocBssid.bssid, bcast_mac, + AR6000_ETH_ADDR_LEN) == 0) + { + ret = -EFAULT; + } else { + + A_MEMCPY(ar->arReqBssid, adhocBssid.bssid, sizeof(ar->arReqBssid)); + } + break; + } + + case AR6000_XIOCTL_SET_OPT_MODE: + { + WMI_SET_OPT_MODE_CMD optModeCmd; + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&optModeCmd, userdata, + sizeof(optModeCmd))) + { + ret = -EFAULT; + } else if (ar->arConnected && optModeCmd.optMode == SPECIAL_ON) { + ret = -EFAULT; + + } else if (wmi_set_opt_mode_cmd(ar->arWmi, optModeCmd.optMode) + != A_OK) + { + ret = -EIO; + } + break; + } + + case AR6000_XIOCTL_OPT_SEND_FRAME: + { + WMI_OPT_TX_FRAME_CMD optTxFrmCmd; + A_UINT8 data[MAX_OPT_DATA_LEN]; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&optTxFrmCmd, userdata, + sizeof(optTxFrmCmd))) + { + ret = -EFAULT; + } else if (copy_from_user(data, + userdata+sizeof(WMI_OPT_TX_FRAME_CMD)-1, + optTxFrmCmd.optIEDataLen)) + { + ret = -EFAULT; + } else { + ret = wmi_opt_tx_frame_cmd(ar->arWmi, + optTxFrmCmd.frmType, + optTxFrmCmd.dstAddr, + optTxFrmCmd.bssid, + optTxFrmCmd.optIEDataLen, + data); + } + + break; + } + case AR6000_XIOCTL_WMI_SETRETRYLIMITS: + { + WMI_SET_RETRY_LIMITS_CMD setRetryParams; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setRetryParams, userdata, + sizeof(setRetryParams))) + { + ret = -EFAULT; + } else { + if (wmi_set_retry_limits_cmd(ar->arWmi, setRetryParams.frameType, + setRetryParams.trafficClass, + setRetryParams.maxRetries, + setRetryParams.enableNotify) != A_OK) + { + ret = -EIO; + } + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arMaxRetries = setRetryParams.maxRetries; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + break; + } + + case AR6000_XIOCTL_SET_BEACON_INTVAL: + { + WMI_BEACON_INT_CMD bIntvlCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&bIntvlCmd, userdata, + sizeof(bIntvlCmd))) + { + ret = -EFAULT; + } else if (wmi_set_adhoc_bconIntvl_cmd(ar->arWmi, bIntvlCmd.beaconInterval) + != A_OK) + { + ret = -EIO; + } + if(ret == 0) { + ar->ap_profile_flag = 1; /* There is a change in profile */ + } + break; + } + case IEEE80211_IOCTL_SETAUTHALG: + { + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + struct ieee80211req_authalg req; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&req, userdata, + sizeof(struct ieee80211req_authalg))) + { + ret = -EFAULT; + } else { + if (req.auth_alg & AUTH_ALG_OPEN_SYSTEM) { + ar->arDot11AuthMode |= OPEN_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arGroupCrypto = NONE_CRYPT; + } + if (req.auth_alg & AUTH_ALG_SHARED_KEY) { + ar->arDot11AuthMode |= SHARED_AUTH; + ar->arPairwiseCrypto = WEP_CRYPT; + ar->arGroupCrypto = WEP_CRYPT; + } + if (req.auth_alg == AUTH_ALG_LEAP) { + ar->arDot11AuthMode = LEAP_AUTH; + } + } + break; + } + + case AR6000_XIOCTL_SET_VOICE_PKT_SIZE: + ret = ar6000_xioctl_set_voice_pkt_size(dev, userdata); + break; + + case AR6000_XIOCTL_SET_MAX_SP: + ret = ar6000_xioctl_set_max_sp_len(dev, userdata); + break; + + case AR6000_XIOCTL_WMI_GET_ROAM_TBL: + ret = ar6000_ioctl_get_roam_tbl(dev, rq); + break; + case AR6000_XIOCTL_WMI_SET_ROAM_CTRL: + ret = ar6000_ioctl_set_roam_ctrl(dev, userdata); + break; + case AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS: + ret = ar6000_ioctl_set_powersave_timers(dev, userdata); + break; + case AR6000_XIOCTRL_WMI_GET_POWER_MODE: + ret = ar6000_ioctl_get_power_mode(dev, rq); + break; + case AR6000_XIOCTRL_WMI_SET_WLAN_STATE: + get_user(ar->arWlanState, (unsigned int *)userdata); + if (ar->arWmiReady == FALSE) { + ret = -EIO; + break; + } + + if (ar->arWlanState == WLAN_ENABLED) { + /* Enable foreground scanning */ + if (wmi_scanparams_cmd(ar->arWmi, scParams.fg_start_period, + scParams.fg_end_period, + scParams.bg_period, + scParams.minact_chdwell_time, + scParams.maxact_chdwell_time, + scParams.pas_chdwell_time, + scParams.shortScanRatio, + scParams.scanCtrlFlags, + scParams.max_dfsch_act_time, + scParams.maxact_scan_per_ssid) != A_OK) + { + ret = -EIO; + } + if (ar->arSsidLen) { + ar->arConnectPending = TRUE; + if (wmi_connect_cmd(ar->arWmi, ar->arNetworkType, + ar->arDot11AuthMode, ar->arAuthMode, + ar->arPairwiseCrypto, + ar->arPairwiseCryptoLen, + ar->arGroupCrypto, ar->arGroupCryptoLen, + ar->arSsidLen, ar->arSsid, + ar->arReqBssid, ar->arChannelHint, + ar->arConnectCtrlFlags) != A_OK) + { + ret = -EIO; + ar->arConnectPending = FALSE; + } + } + } else { + /* Disconnect from the AP and disable foreground scanning */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) { + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + wmi_disconnect_cmd(ar->arWmi); + } else { + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + + if (wmi_scanparams_cmd(ar->arWmi, 0xFFFF, 0, 0, 0, 0, 0, 0, 0xFF, 0, 0) != A_OK) + { + ret = -EIO; + } + } + break; + case AR6000_XIOCTL_WMI_GET_ROAM_DATA: + ret = ar6000_ioctl_get_roam_data(dev, rq); + break; + case AR6000_XIOCTL_WMI_SET_BT_STATUS: + ret = ar6000_xioctl_set_bt_status_cmd(dev, userdata); + break; + case AR6000_XIOCTL_WMI_SET_BT_PARAMS: + ret = ar6000_xioctl_set_bt_params_cmd(dev, userdata); + break; + case AR6000_XIOCTL_WMI_STARTSCAN: + { + WMI_START_SCAN_CMD setStartScanCmd, *cmdp; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setStartScanCmd, userdata, + sizeof(setStartScanCmd))) + { + ret = -EFAULT; + } else { + if (setStartScanCmd.numChannels > 1) { + cmdp = A_MALLOC(130); + if (copy_from_user(cmdp, userdata, + sizeof (*cmdp) + + ((setStartScanCmd.numChannels - 1) * + sizeof(A_UINT16)))) + { + kfree(cmdp); + return -EFAULT; + } + } else { + cmdp = &setStartScanCmd; + } + + if (wmi_startscan_cmd(ar->arWmi, cmdp->scanType, + cmdp->forceFgScan, + cmdp->isLegacy, + cmdp->homeDwellTime, + cmdp->forceScanInterval, + cmdp->numChannels, + cmdp->channelList) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SETFIXRATES: + { + WMI_FIX_RATES_CMD setFixRatesCmd; + A_STATUS returnStatus; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setFixRatesCmd, userdata, + sizeof(setFixRatesCmd))) + { + ret = -EFAULT; + } else { + returnStatus = wmi_set_fixrates_cmd(ar->arWmi, setFixRatesCmd.fixRateMask); + if (returnStatus == A_EINVAL) { + ret = -EINVAL; + } else if(returnStatus != A_OK) { + ret = -EIO; + } else { + ar->ap_profile_flag = 1; /* There is a change in profile */ + } + } + break; + } + + case AR6000_XIOCTL_WMI_GETFIXRATES: + { + WMI_FIX_RATES_CMD getFixRatesCmd; + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + int ret = 0; + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + /* Used copy_from_user/copy_to_user to access user space data */ + if (copy_from_user(&getFixRatesCmd, userdata, sizeof(getFixRatesCmd))) { + ret = -EFAULT; + } else { + ar->arRateMask = 0xFFFF; + + if (wmi_get_ratemask_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->arRateMask != 0xFFFF, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + + if (!ret) { + getFixRatesCmd.fixRateMask = ar->arRateMask; + } + + if(copy_to_user(userdata, &getFixRatesCmd, sizeof(getFixRatesCmd))) { + ret = -EFAULT; + } + + up(&ar->arSem); + } + break; + } + case AR6000_XIOCTL_WMI_SET_AUTHMODE: + { + WMI_SET_AUTH_MODE_CMD setAuthMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setAuthMode, userdata, + sizeof(setAuthMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_authmode_cmd(ar->arWmi, setAuthMode.mode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_REASSOCMODE: + { + WMI_SET_REASSOC_MODE_CMD setReassocMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setReassocMode, userdata, + sizeof(setReassocMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_reassocmode_cmd(ar->arWmi, setReassocMode.mode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_DIAG_READ: + { + A_UINT32 addr, data; + get_user(addr, (unsigned int *)userdata); + addr = TARG_VTOP(ar->arTargetType, addr); + if (ar6000_ReadRegDiag(ar->arHifDevice, &addr, &data) != A_OK) { + ret = -EIO; + } + put_user(data, (unsigned int *)userdata + 1); + break; + } + case AR6000_XIOCTL_DIAG_WRITE: + { + A_UINT32 addr, data; + get_user(addr, (unsigned int *)userdata); + get_user(data, (unsigned int *)userdata + 1); + addr = TARG_VTOP(ar->arTargetType, addr); + if (ar6000_WriteRegDiag(ar->arHifDevice, &addr, &data) != A_OK) { + ret = -EIO; + } + break; + } + case AR6000_XIOCTL_WMI_SET_KEEPALIVE: + { + WMI_SET_KEEPALIVE_CMD setKeepAlive; + if (ar->arWmiReady == FALSE) { + return -EIO; + } else if (copy_from_user(&setKeepAlive, userdata, + sizeof(setKeepAlive))){ + ret = -EFAULT; + } else { + if (wmi_set_keepalive_cmd(ar->arWmi, setKeepAlive.keepaliveInterval) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_PARAMS: + { + WMI_SET_PARAMS_CMD cmd; + if (ar->arWmiReady == FALSE) { + return -EIO; + } else if (copy_from_user(&cmd, userdata, + sizeof(cmd))){ + ret = -EFAULT; + } else if (copy_from_user(&cmd, userdata, + sizeof(cmd) + cmd.length)) + { + ret = -EFAULT; + } else { + if (wmi_set_params_cmd(ar->arWmi, cmd.opcode, cmd.length, cmd.buffer) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_MCAST_FILTER: + { + WMI_SET_MCAST_FILTER_CMD cmd; + if (ar->arWmiReady == FALSE) { + return -EIO; + } else if (copy_from_user(&cmd, userdata, + sizeof(cmd))){ + ret = -EFAULT; + } else { + if (wmi_set_mcast_filter_cmd(ar->arWmi, cmd.multicast_mac[0], + cmd.multicast_mac[1], + cmd.multicast_mac[2], + cmd.multicast_mac[3]) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_DEL_MCAST_FILTER: + { + WMI_SET_MCAST_FILTER_CMD cmd; + if (ar->arWmiReady == FALSE) { + return -EIO; + } else if (copy_from_user(&cmd, userdata, + sizeof(cmd))){ + ret = -EFAULT; + } else { + if (wmi_del_mcast_filter_cmd(ar->arWmi, cmd.multicast_mac[0], + cmd.multicast_mac[1], + cmd.multicast_mac[2], + cmd.multicast_mac[3]) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_GET_KEEPALIVE: + { + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_GET_KEEPALIVE_CMD getKeepAlive; + int ret = 0; + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + if (copy_from_user(&getKeepAlive, userdata,sizeof(getKeepAlive))) { + ret = -EFAULT; + } else { + getKeepAlive.keepaliveInterval = wmi_get_keepalive_cmd(ar->arWmi); + ar->arKeepaliveConfigured = 0xFF; + if (wmi_get_keepalive_configured(ar->arWmi) != A_OK){ + up(&ar->arSem); + return -EIO; + } + wait_event_interruptible_timeout(arEvent, ar->arKeepaliveConfigured != 0xFF, wmitimeout * HZ); + if (signal_pending(current)) { + ret = -EINTR; + } + + if (!ret) { + getKeepAlive.configured = ar->arKeepaliveConfigured; + } + if (copy_to_user(userdata, &getKeepAlive, sizeof(getKeepAlive))) { + ret = -EFAULT; + } + up(&ar->arSem); + } + break; + } + case AR6000_XIOCTL_WMI_SET_APPIE: + { + WMI_SET_APPIE_CMD appIEcmd; + A_UINT8 appIeInfo[IEEE80211_APPIE_FRAME_MAX_LEN]; + A_UINT32 fType,ieLen; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + get_user(fType, (A_UINT32 *)userdata); + appIEcmd.mgmtFrmType = fType; + if (appIEcmd.mgmtFrmType >= IEEE80211_APPIE_NUM_OF_FRAME) { + ret = -EIO; + } else { + get_user(ieLen, (A_UINT32 *)(userdata + 4)); + appIEcmd.ieLen = ieLen; + if (appIEcmd.ieLen > IEEE80211_APPIE_FRAME_MAX_LEN) { + ret = -EIO; + break; + } + if (copy_from_user(appIeInfo, userdata + 8, appIEcmd.ieLen)) { + ret = -EFAULT; + } else { + if (wmi_set_appie_cmd(ar->arWmi, appIEcmd.mgmtFrmType, + appIEcmd.ieLen, appIeInfo) != A_OK) + { + ret = -EIO; + } + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER: + { + WMI_BSS_FILTER_CMD cmd; + A_UINT32 filterType; + + if (copy_from_user(&filterType, userdata, sizeof(A_UINT32))) + { + return -EFAULT; + } + if (filterType & (IEEE80211_FILTER_TYPE_BEACON | + IEEE80211_FILTER_TYPE_PROBE_RESP)) + { + cmd.bssFilter = ALL_BSS_FILTER; + } else { + cmd.bssFilter = NONE_BSS_FILTER; + } + if (wmi_bssfilter_cmd(ar->arWmi, cmd.bssFilter, 0) != A_OK) { + ret = -EIO; + } + + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arMgmtFilter = filterType; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + break; + } + case AR6000_XIOCTL_WMI_SET_WSC_STATUS: + { + A_UINT32 wsc_status; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } else if (copy_from_user(&wsc_status, userdata, sizeof(A_UINT32))) + { + return -EFAULT; + } + if (wmi_set_wsc_status_cmd(ar->arWmi, wsc_status) != A_OK) { + ret = -EIO; + } + break; + } + case AR6000_XIOCTL_BMI_ROMPATCH_INSTALL: + { + A_UINT32 ROM_addr; + A_UINT32 RAM_addr; + A_UINT32 nbytes; + A_UINT32 do_activate; + A_UINT32 rompatch_id; + + get_user(ROM_addr, (A_UINT32 *)userdata); + get_user(RAM_addr, (A_UINT32 *)userdata + 1); + get_user(nbytes, (A_UINT32 *)userdata + 2); + get_user(do_activate, (A_UINT32 *)userdata + 3); + AR_DEBUG_PRINTF("Install rompatch from ROM: 0x%x to RAM: 0x%x length: %d\n", + ROM_addr, RAM_addr, nbytes); + ret = BMIrompatchInstall(hifDevice, ROM_addr, RAM_addr, + nbytes, do_activate, &rompatch_id); + if (ret == A_OK) { + put_user(rompatch_id, (unsigned int *)rq->ifr_data); /* return value */ + } + break; + } + + case AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL: + { + A_UINT32 rompatch_id; + + get_user(rompatch_id, (A_UINT32 *)userdata); + AR_DEBUG_PRINTF("UNinstall rompatch_id %d\n", rompatch_id); + ret = BMIrompatchUninstall(hifDevice, rompatch_id); + break; + } + + case AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE: + case AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE: + { + A_UINT32 rompatch_count; + + get_user(rompatch_count, (A_UINT32 *)userdata); + AR_DEBUG_PRINTF("Change rompatch activation count=%d\n", rompatch_count); + length = sizeof(A_UINT32) * rompatch_count; + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + if (copy_from_user(buffer, &userdata[sizeof(rompatch_count)], length)) + { + ret = -EFAULT; + } else { + if (cmd == AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE) { + ret = BMIrompatchActivate(hifDevice, rompatch_count, (A_UINT32 *)buffer); + } else { + ret = BMIrompatchDeactivate(hifDevice, rompatch_count, (A_UINT32 *)buffer); + } + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + + break; + } + case AR6000_XIOCTL_SET_IP: + { + WMI_SET_IP_CMD setIP; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setIP, userdata, + sizeof(setIP))) + { + ret = -EFAULT; + } else { + if (wmi_set_ip_cmd(ar->arWmi, + &setIP) != A_OK) + { + ret = -EIO; + } + } + break; + } + + case AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE: + { + WMI_SET_HOST_SLEEP_MODE_CMD setHostSleepMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setHostSleepMode, userdata, + sizeof(setHostSleepMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_host_sleep_mode_cmd(ar->arWmi, + &setHostSleepMode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_WOW_MODE: + { + WMI_SET_WOW_MODE_CMD setWowMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setWowMode, userdata, + sizeof(setWowMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_wow_mode_cmd(ar->arWmi, + &setWowMode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_GET_WOW_LIST: + { + WMI_GET_WOW_LIST_CMD getWowList; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&getWowList, userdata, + sizeof(getWowList))) + { + ret = -EFAULT; + } else { + if (wmi_get_wow_list_cmd(ar->arWmi, + &getWowList) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_ADD_WOW_PATTERN: + { +#define WOW_PATTERN_SIZE 64 +#define WOW_MASK_SIZE 64 + + WMI_ADD_WOW_PATTERN_CMD cmd; + A_UINT8 mask_data[WOW_PATTERN_SIZE]={0}; + A_UINT8 pattern_data[WOW_PATTERN_SIZE]={0}; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + + if(copy_from_user(&cmd, userdata, + sizeof(WMI_ADD_WOW_PATTERN_CMD))) + return -EFAULT; + if (copy_from_user(pattern_data, + userdata + 3, + cmd.filter_size)){ + ret = -EFAULT; + break; + } + if (copy_from_user(mask_data, + (userdata + 3 + cmd.filter_size), + cmd.filter_size)){ + ret = -EFAULT; + break; + } else { + if (wmi_add_wow_pattern_cmd(ar->arWmi, + &cmd, pattern_data, mask_data, cmd.filter_size) != A_OK){ + ret = -EIO; + } + } + } +#undef WOW_PATTERN_SIZE +#undef WOW_MASK_SIZE + break; + } + case AR6000_XIOCTL_WMI_DEL_WOW_PATTERN: + { + WMI_DEL_WOW_PATTERN_CMD delWowPattern; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&delWowPattern, userdata, + sizeof(delWowPattern))) + { + ret = -EFAULT; + } else { + if (wmi_del_wow_pattern_cmd(ar->arWmi, + &delWowPattern) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE: + if (ar->arHtcTarget != NULL) { + HTCDumpCreditStates(ar->arHtcTarget); + } + break; + case AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE: + if (ar->arHtcTarget != NULL) { + struct ar6000_traffic_activity_change data; + + if (copy_from_user(&data, userdata, sizeof(data))) + { + return -EFAULT; + } + /* note, this is used for testing (mbox ping testing), indicate activity + * change using the stream ID as the traffic class */ + ar6000_indicate_tx_activity(ar, + (A_UINT8)data.StreamID, + data.Active ? TRUE : FALSE); + } + break; + case AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&connectCtrlFlags, userdata, + sizeof(connectCtrlFlags))) + { + ret = -EFAULT; + } else { + ar->arConnectCtrlFlags = connectCtrlFlags; + } + break; + case AR6000_XIOCTL_WMI_SET_AKMP_PARAMS: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&akmpParams, userdata, + sizeof(WMI_SET_AKMP_PARAMS_CMD))) + { + ret = -EFAULT; + } else { + if (wmi_set_akmp_params_cmd(ar->arWmi, &akmpParams) != A_OK) { + ret = -EIO; + } + } + break; + case AR6000_XIOCTL_WMI_SET_PMKID_LIST: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + if (copy_from_user(&pmkidInfo.numPMKID, userdata, + sizeof(pmkidInfo.numPMKID))) + { + ret = -EFAULT; + break; + } + if (copy_from_user(&pmkidInfo.pmkidList, + userdata + sizeof(pmkidInfo.numPMKID), + pmkidInfo.numPMKID * sizeof(WMI_PMKID))) + { + ret = -EFAULT; + break; + } + if (wmi_set_pmkid_list_cmd(ar->arWmi, &pmkidInfo) != A_OK) { + ret = -EIO; + } + } + break; + case AR6000_XIOCTL_WMI_GET_PMKID_LIST: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + if (wmi_get_pmkid_list_cmd(ar->arWmi) != A_OK) { + ret = -EIO; + } + } + break; + case AR6000_XIOCTL_WMI_ABORT_SCAN: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } + ret = wmi_abort_scan_cmd(ar->arWmi); + break; + case AR6000_XIOCTL_AP_HIDDEN_SSID: + { + A_UINT8 hidden_ssid; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&hidden_ssid, userdata, sizeof(hidden_ssid))) { + ret = -EFAULT; + } else { + wmi_ap_set_hidden_ssid(ar->arWmi, hidden_ssid); + ar->ap_profile_flag = 1; /* There is a change in profile */ + } + break; + } + case AR6000_XIOCTL_AP_GET_STA_LIST: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + A_UINT8 i; + ap_get_sta_t temp; + A_MEMZERO(&temp, sizeof(temp)); + for(i=0;ista_list[i].mac, ATH_MAC_LEN); + temp.sta[i].aid = ar->sta_list[i].aid; + } + if(copy_to_user((ap_get_sta_t *)rq->ifr_data, &temp, + sizeof(ar->sta_list))) { + ret = -EFAULT; + } + } + break; + } + case AR6000_XIOCTL_AP_SET_NUM_STA: + { + A_UINT8 num_sta; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&num_sta, userdata, sizeof(num_sta))) { + ret = -EFAULT; + } else if(num_sta > AP_MAX_NUM_STA) { + /* value out of range */ + ret = -EINVAL; + } else { + wmi_ap_set_num_sta(ar->arWmi, num_sta); + } + break; + } + case AR6000_XIOCTL_AP_SET_ACL_POLICY: + { + A_UINT8 policy; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&policy, userdata, sizeof(policy))) { + ret = -EFAULT; + } else if(policy == ar->g_acl.policy) { + /* No change in policy */ + } else { + if(!(policy & AP_ACL_RETAIN_LIST_MASK)) { + /* clear ACL list */ + memset(&ar->g_acl,0,sizeof(WMI_AP_ACL)); + } + ar->g_acl.policy = policy; + wmi_ap_set_acl_policy(ar->arWmi, policy); + } + break; + } + case AR6000_XIOCTL_AP_SET_ACL_MAC: + { + WMI_AP_ACL_MAC_CMD acl; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&acl, userdata, sizeof(acl))) { + ret = -EFAULT; + } else { + if(acl_add_del_mac(&ar->g_acl, &acl)) { + wmi_ap_acl_mac_list(ar->arWmi, &acl); + } else { + A_PRINTF("ACL list error\n"); + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_AP_GET_ACL_LIST: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if(copy_to_user((WMI_AP_ACL *)rq->ifr_data, &ar->g_acl, + sizeof(WMI_AP_ACL))) { + ret = -EFAULT; + } + break; + } + case AR6000_XIOCTL_AP_COMMIT_CONFIG: + { + ret = ar6000_ap_mode_profile_commit(ar); + break; + } + case IEEE80211_IOCTL_GETWPAIE: + { + struct ieee80211req_wpaie wpaie; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&wpaie, userdata, sizeof(wpaie))) { + ret = -EFAULT; + } else if (ar6000_ap_mode_get_wpa_ie(ar, &wpaie)) { + ret = -EFAULT; + } else if(copy_to_user(userdata, &wpaie, sizeof(wpaie))) { + ret = -EFAULT; + } + break; + } + case AR6000_XIOCTL_AP_CONN_INACT_TIME: + { + A_UINT32 period; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&period, userdata, sizeof(period))) { + ret = -EFAULT; + } else { + wmi_ap_conn_inact_time(ar->arWmi, period); + } + break; + } + case AR6000_XIOCTL_AP_PROT_SCAN_TIME: + { + WMI_AP_PROT_SCAN_TIME_CMD bgscan; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&bgscan, userdata, sizeof(bgscan))) { + ret = -EFAULT; + } else { + wmi_ap_bgscan_time(ar->arWmi, bgscan.period_min, bgscan.dwell_ms); + } + break; + } + case AR6000_XIOCTL_AP_SET_COUNTRY: + { + ret = ar6000_ioctl_set_country(dev, rq); + break; + } + case AR6000_XIOCTL_AP_SET_DTIM: + { + WMI_AP_SET_DTIM_CMD d; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&d, userdata, sizeof(d))) { + ret = -EFAULT; + } else { + if(d.dtim > 0 && d.dtim < 11) { + wmi_ap_set_dtim(ar->arWmi, d.dtim); + ar->ap_profile_flag = 1; /* There is a change in profile */ + } else { + A_PRINTF("DTIM out of range. Valid range is [1-10]\n"); + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT: + { + WMI_SET_TARGET_EVENT_REPORT_CMD evtCfgCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } + if (copy_from_user(&evtCfgCmd, userdata, + sizeof(evtCfgCmd))) { + ret = -EFAULT; + break; + } + ret = wmi_set_target_event_report_cmd(ar->arWmi, &evtCfgCmd); + break; + } + case AR6000_XIOCTL_AP_INTRA_BSS_COMM: + { + A_UINT8 intra=0; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&intra, userdata, sizeof(intra))) { + ret = -EFAULT; + } else { + ar->intra_bss = (intra?1:0); + } + break; + } + default: + ret = -EOPNOTSUPP; + } + return ret; +} + +A_UINT8 mac_cmp_wild(A_UINT8 *mac, A_UINT8 *new_mac, A_UINT8 wild, A_UINT8 new_wild) +{ + A_UINT8 i; + + for(i=0;i=0;i--) + { + if(mac_cmp_wild(a->acl_mac[i], acl->mac, a->wildcard[i], + acl->wildcard)==0) + already_avail = i; + + if(!((1 << i) & a->index)) + free_slot = i; + } + + if(acl->action == ADD_MAC_ADDR) + { + /* Dont add mac if it is already available */ + if((already_avail >= 0) || (free_slot == -1)) + return 0; + + A_MEMCPY(a->acl_mac[free_slot], acl->mac, ATH_MAC_LEN); + a->index = a->index | (1 << free_slot); + acl->index = free_slot; + a->wildcard[free_slot] = acl->wildcard; + return 1; + } + else if(acl->action == DEL_MAC_ADDR) + { + if(acl->index > AP_ACL_SIZE) + return 0; + + if(!(a->index & (1 << acl->index))) + return 0; + + A_MEMZERO(a->acl_mac[acl->index],ATH_MAC_LEN); + a->index = a->index & ~(1 << acl->index); + a->wildcard[acl->index] = 0; + return 1; + } + + return 0; +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/mbox_host_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/mbox_host_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/mbox_host_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/mbox_host_reg.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,409 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MBOX_HOST_REG_REG_H_ +#define _MBOX_HOST_REG_REG_H_ + +#define HOST_INT_STATUS_ADDRESS 0x00000400 +#define HOST_INT_STATUS_OFFSET 0x00000400 +#define HOST_INT_STATUS_ERROR_MSB 7 +#define HOST_INT_STATUS_ERROR_LSB 7 +#define HOST_INT_STATUS_ERROR_MASK 0x00000080 +#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB) +#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK) +#define HOST_INT_STATUS_CPU_MSB 6 +#define HOST_INT_STATUS_CPU_LSB 6 +#define HOST_INT_STATUS_CPU_MASK 0x00000040 +#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB) +#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK) +#define HOST_INT_STATUS_DRAGON_INT_MSB 5 +#define HOST_INT_STATUS_DRAGON_INT_LSB 5 +#define HOST_INT_STATUS_DRAGON_INT_MASK 0x00000020 +#define HOST_INT_STATUS_DRAGON_INT_GET(x) (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB) +#define HOST_INT_STATUS_DRAGON_INT_SET(x) (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK) +#define HOST_INT_STATUS_COUNTER_MSB 4 +#define HOST_INT_STATUS_COUNTER_LSB 4 +#define HOST_INT_STATUS_COUNTER_MASK 0x00000010 +#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB) +#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK) +#define HOST_INT_STATUS_MBOX_DATA_MSB 3 +#define HOST_INT_STATUS_MBOX_DATA_LSB 0 +#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f +#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB) +#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ADDRESS 0x00000401 +#define CPU_INT_STATUS_OFFSET 0x00000401 +#define CPU_INT_STATUS_BIT_MSB 7 +#define CPU_INT_STATUS_BIT_LSB 0 +#define CPU_INT_STATUS_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB) +#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK) + +#define ERROR_INT_STATUS_ADDRESS 0x00000402 +#define ERROR_INT_STATUS_OFFSET 0x00000402 +#define ERROR_INT_STATUS_SPI_MSB 3 +#define ERROR_INT_STATUS_SPI_LSB 3 +#define ERROR_INT_STATUS_SPI_MASK 0x00000008 +#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB) +#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK) +#define ERROR_INT_STATUS_WAKEUP_MSB 2 +#define ERROR_INT_STATUS_WAKEUP_LSB 2 +#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 +#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB) +#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK) +#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB) +#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) +#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB) +#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ADDRESS 0x00000403 +#define COUNTER_INT_STATUS_OFFSET 0x00000403 +#define COUNTER_INT_STATUS_COUNTER_MSB 7 +#define COUNTER_INT_STATUS_COUNTER_LSB 0 +#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff +#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB) +#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK) + +#define MBOX_FRAME_ADDRESS 0x00000404 +#define MBOX_FRAME_OFFSET 0x00000404 +#define MBOX_FRAME_RX_EOM_MSB 7 +#define MBOX_FRAME_RX_EOM_LSB 4 +#define MBOX_FRAME_RX_EOM_MASK 0x000000f0 +#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB) +#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK) +#define MBOX_FRAME_RX_SOM_MSB 3 +#define MBOX_FRAME_RX_SOM_LSB 0 +#define MBOX_FRAME_RX_SOM_MASK 0x0000000f +#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB) +#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK) + +#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405 +#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405 +#define RX_LOOKAHEAD_VALID_MBOX_MSB 3 +#define RX_LOOKAHEAD_VALID_MBOX_LSB 0 +#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f +#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB) +#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK) + +#define RX_LOOKAHEAD0_ADDRESS 0x00000408 +#define RX_LOOKAHEAD0_OFFSET 0x00000408 +#define RX_LOOKAHEAD0_DATA_MSB 7 +#define RX_LOOKAHEAD0_DATA_LSB 0 +#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB) +#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK) + +#define RX_LOOKAHEAD1_ADDRESS 0x0000040c +#define RX_LOOKAHEAD1_OFFSET 0x0000040c +#define RX_LOOKAHEAD1_DATA_MSB 7 +#define RX_LOOKAHEAD1_DATA_LSB 0 +#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB) +#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK) + +#define RX_LOOKAHEAD2_ADDRESS 0x00000410 +#define RX_LOOKAHEAD2_OFFSET 0x00000410 +#define RX_LOOKAHEAD2_DATA_MSB 7 +#define RX_LOOKAHEAD2_DATA_LSB 0 +#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB) +#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK) + +#define RX_LOOKAHEAD3_ADDRESS 0x00000414 +#define RX_LOOKAHEAD3_OFFSET 0x00000414 +#define RX_LOOKAHEAD3_DATA_MSB 7 +#define RX_LOOKAHEAD3_DATA_LSB 0 +#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB) +#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK) + +#define INT_STATUS_ENABLE_ADDRESS 0x00000418 +#define INT_STATUS_ENABLE_OFFSET 0x00000418 +#define INT_STATUS_ENABLE_ERROR_MSB 7 +#define INT_STATUS_ENABLE_ERROR_LSB 7 +#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080 +#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB) +#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK) +#define INT_STATUS_ENABLE_CPU_MSB 6 +#define INT_STATUS_ENABLE_CPU_LSB 6 +#define INT_STATUS_ENABLE_CPU_MASK 0x00000040 +#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB) +#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK) +#define INT_STATUS_ENABLE_DRAGON_INT_MSB 5 +#define INT_STATUS_ENABLE_DRAGON_INT_LSB 5 +#define INT_STATUS_ENABLE_DRAGON_INT_MASK 0x00000020 +#define INT_STATUS_ENABLE_DRAGON_INT_GET(x) (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB) +#define INT_STATUS_ENABLE_DRAGON_INT_SET(x) (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK) +#define INT_STATUS_ENABLE_COUNTER_MSB 4 +#define INT_STATUS_ENABLE_COUNTER_LSB 4 +#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 +#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB) +#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK) +#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3 +#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0 +#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f +#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB) +#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 +#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419 +#define CPU_INT_STATUS_ENABLE_BIT_MSB 7 +#define CPU_INT_STATUS_ENABLE_BIT_LSB 0 +#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB) +#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK) + +#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a +#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a +#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004 +#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB) +#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7 +#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 +#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB) +#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) + +#define COUNT_ADDRESS 0x00000420 +#define COUNT_OFFSET 0x00000420 +#define COUNT_VALUE_MSB 7 +#define COUNT_VALUE_LSB 0 +#define COUNT_VALUE_MASK 0x000000ff +#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB) +#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK) + +#define COUNT_DEC_ADDRESS 0x00000440 +#define COUNT_DEC_OFFSET 0x00000440 +#define COUNT_DEC_VALUE_MSB 7 +#define COUNT_DEC_VALUE_LSB 0 +#define COUNT_DEC_VALUE_MASK 0x000000ff +#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB) +#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK) + +#define SCRATCH_ADDRESS 0x00000460 +#define SCRATCH_OFFSET 0x00000460 +#define SCRATCH_VALUE_MSB 7 +#define SCRATCH_VALUE_LSB 0 +#define SCRATCH_VALUE_MASK 0x000000ff +#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB) +#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK) + +#define FIFO_TIMEOUT_ADDRESS 0x00000468 +#define FIFO_TIMEOUT_OFFSET 0x00000468 +#define FIFO_TIMEOUT_VALUE_MSB 7 +#define FIFO_TIMEOUT_VALUE_LSB 0 +#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff +#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB) +#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK) + +#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469 +#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469 +#define FIFO_TIMEOUT_ENABLE_SET_MSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_LSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001 +#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB) +#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK) + +#define DISABLE_SLEEP_ADDRESS 0x0000046a +#define DISABLE_SLEEP_OFFSET 0x0000046a +#define DISABLE_SLEEP_FOR_INT_MSB 1 +#define DISABLE_SLEEP_FOR_INT_LSB 1 +#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002 +#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB) +#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK) +#define DISABLE_SLEEP_ON_MSB 0 +#define DISABLE_SLEEP_ON_LSB 0 +#define DISABLE_SLEEP_ON_MASK 0x00000001 +#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB) +#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK) + +#define LOCAL_BUS_ADDRESS 0x00000470 +#define LOCAL_BUS_OFFSET 0x00000470 +#define LOCAL_BUS_STATE_MSB 1 +#define LOCAL_BUS_STATE_LSB 0 +#define LOCAL_BUS_STATE_MASK 0x00000003 +#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB) +#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK) + +#define INT_WLAN_ADDRESS 0x00000472 +#define INT_WLAN_OFFSET 0x00000472 +#define INT_WLAN_VECTOR_MSB 7 +#define INT_WLAN_VECTOR_LSB 0 +#define INT_WLAN_VECTOR_MASK 0x000000ff +#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB) +#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK) + +#define WINDOW_DATA_ADDRESS 0x00000474 +#define WINDOW_DATA_OFFSET 0x00000474 +#define WINDOW_DATA_DATA_MSB 7 +#define WINDOW_DATA_DATA_LSB 0 +#define WINDOW_DATA_DATA_MASK 0x000000ff +#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB) +#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK) + +#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 +#define WINDOW_WRITE_ADDR_OFFSET 0x00000478 +#define WINDOW_WRITE_ADDR_ADDR_MSB 7 +#define WINDOW_WRITE_ADDR_ADDR_LSB 0 +#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB) +#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK) + +#define WINDOW_READ_ADDR_ADDRESS 0x0000047c +#define WINDOW_READ_ADDR_OFFSET 0x0000047c +#define WINDOW_READ_ADDR_ADDR_MSB 7 +#define WINDOW_READ_ADDR_ADDR_LSB 0 +#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB) +#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK) + +#define SPI_CONFIG_ADDRESS 0x00000480 +#define SPI_CONFIG_OFFSET 0x00000480 +#define SPI_CONFIG_SPI_RESET_MSB 4 +#define SPI_CONFIG_SPI_RESET_LSB 4 +#define SPI_CONFIG_SPI_RESET_MASK 0x00000010 +#define SPI_CONFIG_SPI_RESET_GET(x) (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB) +#define SPI_CONFIG_SPI_RESET_SET(x) (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK) +#define SPI_CONFIG_INTERRUPT_ENABLE_MSB 3 +#define SPI_CONFIG_INTERRUPT_ENABLE_LSB 3 +#define SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008 +#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB) +#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) +#define SPI_CONFIG_TEST_MODE_MSB 2 +#define SPI_CONFIG_TEST_MODE_LSB 2 +#define SPI_CONFIG_TEST_MODE_MASK 0x00000004 +#define SPI_CONFIG_TEST_MODE_GET(x) (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB) +#define SPI_CONFIG_TEST_MODE_SET(x) (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK) +#define SPI_CONFIG_DATA_SIZE_MSB 1 +#define SPI_CONFIG_DATA_SIZE_LSB 0 +#define SPI_CONFIG_DATA_SIZE_MASK 0x00000003 +#define SPI_CONFIG_DATA_SIZE_GET(x) (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB) +#define SPI_CONFIG_DATA_SIZE_SET(x) (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK) + +#define SPI_STATUS_ADDRESS 0x00000481 +#define SPI_STATUS_OFFSET 0x00000481 +#define SPI_STATUS_ADDR_ERR_MSB 3 +#define SPI_STATUS_ADDR_ERR_LSB 3 +#define SPI_STATUS_ADDR_ERR_MASK 0x00000008 +#define SPI_STATUS_ADDR_ERR_GET(x) (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB) +#define SPI_STATUS_ADDR_ERR_SET(x) (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK) +#define SPI_STATUS_RD_ERR_MSB 2 +#define SPI_STATUS_RD_ERR_LSB 2 +#define SPI_STATUS_RD_ERR_MASK 0x00000004 +#define SPI_STATUS_RD_ERR_GET(x) (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB) +#define SPI_STATUS_RD_ERR_SET(x) (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK) +#define SPI_STATUS_WR_ERR_MSB 1 +#define SPI_STATUS_WR_ERR_LSB 1 +#define SPI_STATUS_WR_ERR_MASK 0x00000002 +#define SPI_STATUS_WR_ERR_GET(x) (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB) +#define SPI_STATUS_WR_ERR_SET(x) (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK) +#define SPI_STATUS_READY_MSB 0 +#define SPI_STATUS_READY_LSB 0 +#define SPI_STATUS_READY_MASK 0x00000001 +#define SPI_STATUS_READY_GET(x) (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB) +#define SPI_STATUS_READY_SET(x) (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK) + +#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482 +#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482 +#define NON_ASSOC_SLEEP_EN_BIT_MSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_LSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001 +#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB) +#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK) + +#define CIS_WINDOW_ADDRESS 0x00000600 +#define CIS_WINDOW_OFFSET 0x00000600 +#define CIS_WINDOW_DATA_MSB 7 +#define CIS_WINDOW_DATA_LSB 0 +#define CIS_WINDOW_DATA_MASK 0x000000ff +#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB) +#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mbox_host_reg_reg_s { + unsigned char pad0[1024]; /* pad to 0x400 */ + volatile unsigned char host_int_status; + volatile unsigned char cpu_int_status; + volatile unsigned char error_int_status; + volatile unsigned char counter_int_status; + volatile unsigned char mbox_frame; + volatile unsigned char rx_lookahead_valid; + unsigned char pad1[2]; /* pad to 0x408 */ + volatile unsigned char rx_lookahead0[4]; + volatile unsigned char rx_lookahead1[4]; + volatile unsigned char rx_lookahead2[4]; + volatile unsigned char rx_lookahead3[4]; + volatile unsigned char int_status_enable; + volatile unsigned char cpu_int_status_enable; + volatile unsigned char error_status_enable; + volatile unsigned char counter_int_status_enable; + unsigned char pad2[4]; /* pad to 0x420 */ + volatile unsigned char count[8]; + unsigned char pad3[24]; /* pad to 0x440 */ + volatile unsigned char count_dec[32]; + volatile unsigned char scratch[8]; + volatile unsigned char fifo_timeout; + volatile unsigned char fifo_timeout_enable; + volatile unsigned char disable_sleep; + unsigned char pad4[5]; /* pad to 0x470 */ + volatile unsigned char local_bus; + unsigned char pad5[1]; /* pad to 0x472 */ + volatile unsigned char int_wlan; + unsigned char pad6[1]; /* pad to 0x474 */ + volatile unsigned char window_data[4]; + volatile unsigned char window_write_addr[4]; + volatile unsigned char window_read_addr[4]; + volatile unsigned char spi_config; + volatile unsigned char spi_status; + volatile unsigned char non_assoc_sleep_en; + unsigned char pad7[381]; /* pad to 0x600 */ + volatile unsigned char cis_window[512]; +} mbox_host_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_HOST_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/mbox_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/mbox_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/mbox_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/mbox_reg.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,504 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MBOX_REG_REG_H_ +#define _MBOX_REG_REG_H_ + +#define MBOX_FIFO_ADDRESS 0x00000000 +#define MBOX_FIFO_OFFSET 0x00000000 +#define MBOX_FIFO_DATA_MSB 19 +#define MBOX_FIFO_DATA_LSB 0 +#define MBOX_FIFO_DATA_MASK 0x000fffff +#define MBOX_FIFO_DATA_GET(x) (((x) & MBOX_FIFO_DATA_MASK) >> MBOX_FIFO_DATA_LSB) +#define MBOX_FIFO_DATA_SET(x) (((x) << MBOX_FIFO_DATA_LSB) & MBOX_FIFO_DATA_MASK) + +#define MBOX_FIFO_STATUS_ADDRESS 0x00000010 +#define MBOX_FIFO_STATUS_OFFSET 0x00000010 +#define MBOX_FIFO_STATUS_EMPTY_MSB 19 +#define MBOX_FIFO_STATUS_EMPTY_LSB 16 +#define MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000 +#define MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & MBOX_FIFO_STATUS_EMPTY_MASK) >> MBOX_FIFO_STATUS_EMPTY_LSB) +#define MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << MBOX_FIFO_STATUS_EMPTY_LSB) & MBOX_FIFO_STATUS_EMPTY_MASK) +#define MBOX_FIFO_STATUS_FULL_MSB 15 +#define MBOX_FIFO_STATUS_FULL_LSB 12 +#define MBOX_FIFO_STATUS_FULL_MASK 0x0000f000 +#define MBOX_FIFO_STATUS_FULL_GET(x) (((x) & MBOX_FIFO_STATUS_FULL_MASK) >> MBOX_FIFO_STATUS_FULL_LSB) +#define MBOX_FIFO_STATUS_FULL_SET(x) (((x) << MBOX_FIFO_STATUS_FULL_LSB) & MBOX_FIFO_STATUS_FULL_MASK) + +#define MBOX_DMA_POLICY_ADDRESS 0x00000014 +#define MBOX_DMA_POLICY_OFFSET 0x00000014 +#define MBOX_DMA_POLICY_TX_QUANTUM_MSB 3 +#define MBOX_DMA_POLICY_TX_QUANTUM_LSB 3 +#define MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008 +#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> MBOX_DMA_POLICY_TX_QUANTUM_LSB) +#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_TX_QUANTUM_LSB) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) +#define MBOX_DMA_POLICY_TX_ORDER_MSB 2 +#define MBOX_DMA_POLICY_TX_ORDER_LSB 2 +#define MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004 +#define MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_TX_ORDER_MASK) >> MBOX_DMA_POLICY_TX_ORDER_LSB) +#define MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_TX_ORDER_LSB) & MBOX_DMA_POLICY_TX_ORDER_MASK) +#define MBOX_DMA_POLICY_RX_QUANTUM_MSB 1 +#define MBOX_DMA_POLICY_RX_QUANTUM_LSB 1 +#define MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002 +#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> MBOX_DMA_POLICY_RX_QUANTUM_LSB) +#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_RX_QUANTUM_LSB) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) +#define MBOX_DMA_POLICY_RX_ORDER_MSB 0 +#define MBOX_DMA_POLICY_RX_ORDER_LSB 0 +#define MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001 +#define MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_RX_ORDER_MASK) >> MBOX_DMA_POLICY_RX_ORDER_LSB) +#define MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_RX_ORDER_LSB) & MBOX_DMA_POLICY_RX_ORDER_MASK) + +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c +#define MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c +#define MBOX0_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX0_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> MBOX0_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_RESUME_LSB) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX0_DMA_RX_CONTROL_START_MSB 1 +#define MBOX0_DMA_RX_CONTROL_START_LSB 1 +#define MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_START_MASK) >> MBOX0_DMA_RX_CONTROL_START_LSB) +#define MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_START_LSB) & MBOX0_DMA_RX_CONTROL_START_MASK) +#define MBOX0_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX0_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_STOP_MASK) >> MBOX0_DMA_RX_CONTROL_STOP_LSB) +#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_STOP_LSB) & MBOX0_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024 +#define MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024 +#define MBOX0_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX0_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> MBOX0_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_RESUME_LSB) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX0_DMA_TX_CONTROL_START_MSB 1 +#define MBOX0_DMA_TX_CONTROL_START_LSB 1 +#define MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_START_MASK) >> MBOX0_DMA_TX_CONTROL_START_LSB) +#define MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_START_LSB) & MBOX0_DMA_TX_CONTROL_START_MASK) +#define MBOX0_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX0_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_STOP_MASK) >> MBOX0_DMA_TX_CONTROL_STOP_LSB) +#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_STOP_LSB) & MBOX0_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c +#define MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c +#define MBOX1_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX1_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> MBOX1_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_RESUME_LSB) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX1_DMA_RX_CONTROL_START_MSB 1 +#define MBOX1_DMA_RX_CONTROL_START_LSB 1 +#define MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_START_MASK) >> MBOX1_DMA_RX_CONTROL_START_LSB) +#define MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_START_LSB) & MBOX1_DMA_RX_CONTROL_START_MASK) +#define MBOX1_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX1_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_STOP_MASK) >> MBOX1_DMA_RX_CONTROL_STOP_LSB) +#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_STOP_LSB) & MBOX1_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034 +#define MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034 +#define MBOX1_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX1_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> MBOX1_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_RESUME_LSB) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX1_DMA_TX_CONTROL_START_MSB 1 +#define MBOX1_DMA_TX_CONTROL_START_LSB 1 +#define MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_START_MASK) >> MBOX1_DMA_TX_CONTROL_START_LSB) +#define MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_START_LSB) & MBOX1_DMA_TX_CONTROL_START_MASK) +#define MBOX1_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX1_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_STOP_MASK) >> MBOX1_DMA_TX_CONTROL_STOP_LSB) +#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_STOP_LSB) & MBOX1_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c +#define MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c +#define MBOX2_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX2_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> MBOX2_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_RESUME_LSB) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX2_DMA_RX_CONTROL_START_MSB 1 +#define MBOX2_DMA_RX_CONTROL_START_LSB 1 +#define MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_START_MASK) >> MBOX2_DMA_RX_CONTROL_START_LSB) +#define MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_START_LSB) & MBOX2_DMA_RX_CONTROL_START_MASK) +#define MBOX2_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX2_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_STOP_MASK) >> MBOX2_DMA_RX_CONTROL_STOP_LSB) +#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_STOP_LSB) & MBOX2_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044 +#define MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044 +#define MBOX2_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX2_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> MBOX2_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_RESUME_LSB) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX2_DMA_TX_CONTROL_START_MSB 1 +#define MBOX2_DMA_TX_CONTROL_START_LSB 1 +#define MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_START_MASK) >> MBOX2_DMA_TX_CONTROL_START_LSB) +#define MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_START_LSB) & MBOX2_DMA_TX_CONTROL_START_MASK) +#define MBOX2_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX2_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_STOP_MASK) >> MBOX2_DMA_TX_CONTROL_STOP_LSB) +#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_STOP_LSB) & MBOX2_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c +#define MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c +#define MBOX3_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX3_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> MBOX3_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_RESUME_LSB) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX3_DMA_RX_CONTROL_START_MSB 1 +#define MBOX3_DMA_RX_CONTROL_START_LSB 1 +#define MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_START_MASK) >> MBOX3_DMA_RX_CONTROL_START_LSB) +#define MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_START_LSB) & MBOX3_DMA_RX_CONTROL_START_MASK) +#define MBOX3_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX3_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_STOP_MASK) >> MBOX3_DMA_RX_CONTROL_STOP_LSB) +#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_STOP_LSB) & MBOX3_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054 +#define MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054 +#define MBOX3_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX3_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> MBOX3_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_RESUME_LSB) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX3_DMA_TX_CONTROL_START_MSB 1 +#define MBOX3_DMA_TX_CONTROL_START_LSB 1 +#define MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_START_MASK) >> MBOX3_DMA_TX_CONTROL_START_LSB) +#define MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_START_LSB) & MBOX3_DMA_TX_CONTROL_START_MASK) +#define MBOX3_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX3_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_STOP_MASK) >> MBOX3_DMA_TX_CONTROL_STOP_LSB) +#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_STOP_LSB) & MBOX3_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX_INT_STATUS_ADDRESS 0x00000058 +#define MBOX_INT_STATUS_OFFSET 0x00000058 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_OVERFLOW_MSB 17 +#define MBOX_INT_STATUS_TX_OVERFLOW_LSB 17 +#define MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000 +#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> MBOX_INT_STATUS_TX_OVERFLOW_LSB) +#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_STATUS_TX_OVERFLOW_LSB) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) +#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16 +#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16 +#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000 +#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> MBOX_INT_STATUS_RX_UNDERFLOW_LSB) +#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) +#define MBOX_INT_STATUS_RX_NOT_FULL_MSB 11 +#define MBOX_INT_STATUS_RX_NOT_FULL_LSB 8 +#define MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00 +#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> MBOX_INT_STATUS_RX_NOT_FULL_LSB) +#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_STATUS_RX_NOT_FULL_LSB) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) +#define MBOX_INT_STATUS_HOST_MSB 7 +#define MBOX_INT_STATUS_HOST_LSB 0 +#define MBOX_INT_STATUS_HOST_MASK 0x000000ff +#define MBOX_INT_STATUS_HOST_GET(x) (((x) & MBOX_INT_STATUS_HOST_MASK) >> MBOX_INT_STATUS_HOST_LSB) +#define MBOX_INT_STATUS_HOST_SET(x) (((x) << MBOX_INT_STATUS_HOST_LSB) & MBOX_INT_STATUS_HOST_MASK) + +#define MBOX_INT_ENABLE_ADDRESS 0x0000005c +#define MBOX_INT_ENABLE_OFFSET 0x0000005c +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17 +#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17 +#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000 +#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> MBOX_INT_ENABLE_TX_OVERFLOW_LSB) +#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) +#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11 +#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8 +#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00 +#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> MBOX_INT_ENABLE_RX_NOT_FULL_LSB) +#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) +#define MBOX_INT_ENABLE_HOST_MSB 7 +#define MBOX_INT_ENABLE_HOST_LSB 0 +#define MBOX_INT_ENABLE_HOST_MASK 0x000000ff +#define MBOX_INT_ENABLE_HOST_GET(x) (((x) & MBOX_INT_ENABLE_HOST_MASK) >> MBOX_INT_ENABLE_HOST_LSB) +#define MBOX_INT_ENABLE_HOST_SET(x) (((x) << MBOX_INT_ENABLE_HOST_LSB) & MBOX_INT_ENABLE_HOST_MASK) + +#define INT_HOST_ADDRESS 0x00000060 +#define INT_HOST_OFFSET 0x00000060 +#define INT_HOST_VECTOR_MSB 7 +#define INT_HOST_VECTOR_LSB 0 +#define INT_HOST_VECTOR_MASK 0x000000ff +#define INT_HOST_VECTOR_GET(x) (((x) & INT_HOST_VECTOR_MASK) >> INT_HOST_VECTOR_LSB) +#define INT_HOST_VECTOR_SET(x) (((x) << INT_HOST_VECTOR_LSB) & INT_HOST_VECTOR_MASK) + +#define LOCAL_COUNT_ADDRESS 0x00000080 +#define LOCAL_COUNT_OFFSET 0x00000080 +#define LOCAL_COUNT_VALUE_MSB 7 +#define LOCAL_COUNT_VALUE_LSB 0 +#define LOCAL_COUNT_VALUE_MASK 0x000000ff +#define LOCAL_COUNT_VALUE_GET(x) (((x) & LOCAL_COUNT_VALUE_MASK) >> LOCAL_COUNT_VALUE_LSB) +#define LOCAL_COUNT_VALUE_SET(x) (((x) << LOCAL_COUNT_VALUE_LSB) & LOCAL_COUNT_VALUE_MASK) + +#define COUNT_INC_ADDRESS 0x000000a0 +#define COUNT_INC_OFFSET 0x000000a0 +#define COUNT_INC_VALUE_MSB 7 +#define COUNT_INC_VALUE_LSB 0 +#define COUNT_INC_VALUE_MASK 0x000000ff +#define COUNT_INC_VALUE_GET(x) (((x) & COUNT_INC_VALUE_MASK) >> COUNT_INC_VALUE_LSB) +#define COUNT_INC_VALUE_SET(x) (((x) << COUNT_INC_VALUE_LSB) & COUNT_INC_VALUE_MASK) + +#define LOCAL_SCRATCH_ADDRESS 0x000000c0 +#define LOCAL_SCRATCH_OFFSET 0x000000c0 +#define LOCAL_SCRATCH_VALUE_MSB 7 +#define LOCAL_SCRATCH_VALUE_LSB 0 +#define LOCAL_SCRATCH_VALUE_MASK 0x000000ff +#define LOCAL_SCRATCH_VALUE_GET(x) (((x) & LOCAL_SCRATCH_VALUE_MASK) >> LOCAL_SCRATCH_VALUE_LSB) +#define LOCAL_SCRATCH_VALUE_SET(x) (((x) << LOCAL_SCRATCH_VALUE_LSB) & LOCAL_SCRATCH_VALUE_MASK) + +#define USE_LOCAL_BUS_ADDRESS 0x000000e0 +#define USE_LOCAL_BUS_OFFSET 0x000000e0 +#define USE_LOCAL_BUS_PIN_INIT_MSB 0 +#define USE_LOCAL_BUS_PIN_INIT_LSB 0 +#define USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001 +#define USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & USE_LOCAL_BUS_PIN_INIT_MASK) >> USE_LOCAL_BUS_PIN_INIT_LSB) +#define USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << USE_LOCAL_BUS_PIN_INIT_LSB) & USE_LOCAL_BUS_PIN_INIT_MASK) + +#define SDIO_CONFIG_ADDRESS 0x000000e4 +#define SDIO_CONFIG_OFFSET 0x000000e4 +#define SDIO_CONFIG_CCCR_IOR1_MSB 0 +#define SDIO_CONFIG_CCCR_IOR1_LSB 0 +#define SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001 +#define SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & SDIO_CONFIG_CCCR_IOR1_MASK) >> SDIO_CONFIG_CCCR_IOR1_LSB) +#define SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << SDIO_CONFIG_CCCR_IOR1_LSB) & SDIO_CONFIG_CCCR_IOR1_MASK) + +#define MBOX_DEBUG_ADDRESS 0x000000e8 +#define MBOX_DEBUG_OFFSET 0x000000e8 +#define MBOX_DEBUG_SEL_MSB 2 +#define MBOX_DEBUG_SEL_LSB 0 +#define MBOX_DEBUG_SEL_MASK 0x00000007 +#define MBOX_DEBUG_SEL_GET(x) (((x) & MBOX_DEBUG_SEL_MASK) >> MBOX_DEBUG_SEL_LSB) +#define MBOX_DEBUG_SEL_SET(x) (((x) << MBOX_DEBUG_SEL_LSB) & MBOX_DEBUG_SEL_MASK) + +#define MBOX_FIFO_RESET_ADDRESS 0x000000ec +#define MBOX_FIFO_RESET_OFFSET 0x000000ec +#define MBOX_FIFO_RESET_INIT_MSB 0 +#define MBOX_FIFO_RESET_INIT_LSB 0 +#define MBOX_FIFO_RESET_INIT_MASK 0x00000001 +#define MBOX_FIFO_RESET_INIT_GET(x) (((x) & MBOX_FIFO_RESET_INIT_MASK) >> MBOX_FIFO_RESET_INIT_LSB) +#define MBOX_FIFO_RESET_INIT_SET(x) (((x) << MBOX_FIFO_RESET_INIT_LSB) & MBOX_FIFO_RESET_INIT_MASK) + +#define MBOX_TXFIFO_POP_ADDRESS 0x000000f0 +#define MBOX_TXFIFO_POP_OFFSET 0x000000f0 +#define MBOX_TXFIFO_POP_DATA_MSB 0 +#define MBOX_TXFIFO_POP_DATA_LSB 0 +#define MBOX_TXFIFO_POP_DATA_MASK 0x00000001 +#define MBOX_TXFIFO_POP_DATA_GET(x) (((x) & MBOX_TXFIFO_POP_DATA_MASK) >> MBOX_TXFIFO_POP_DATA_LSB) +#define MBOX_TXFIFO_POP_DATA_SET(x) (((x) << MBOX_TXFIFO_POP_DATA_LSB) & MBOX_TXFIFO_POP_DATA_MASK) + +#define MBOX_RXFIFO_POP_ADDRESS 0x00000100 +#define MBOX_RXFIFO_POP_OFFSET 0x00000100 +#define MBOX_RXFIFO_POP_DATA_MSB 0 +#define MBOX_RXFIFO_POP_DATA_LSB 0 +#define MBOX_RXFIFO_POP_DATA_MASK 0x00000001 +#define MBOX_RXFIFO_POP_DATA_GET(x) (((x) & MBOX_RXFIFO_POP_DATA_MASK) >> MBOX_RXFIFO_POP_DATA_LSB) +#define MBOX_RXFIFO_POP_DATA_SET(x) (((x) << MBOX_RXFIFO_POP_DATA_LSB) & MBOX_RXFIFO_POP_DATA_MASK) + +#define SDIO_DEBUG_ADDRESS 0x00000110 +#define SDIO_DEBUG_OFFSET 0x00000110 +#define SDIO_DEBUG_SEL_MSB 3 +#define SDIO_DEBUG_SEL_LSB 0 +#define SDIO_DEBUG_SEL_MASK 0x0000000f +#define SDIO_DEBUG_SEL_GET(x) (((x) & SDIO_DEBUG_SEL_MASK) >> SDIO_DEBUG_SEL_LSB) +#define SDIO_DEBUG_SEL_SET(x) (((x) << SDIO_DEBUG_SEL_LSB) & SDIO_DEBUG_SEL_MASK) + +#define HOST_IF_WINDOW_ADDRESS 0x00002000 +#define HOST_IF_WINDOW_OFFSET 0x00002000 +#define HOST_IF_WINDOW_DATA_MSB 7 +#define HOST_IF_WINDOW_DATA_LSB 0 +#define HOST_IF_WINDOW_DATA_MASK 0x000000ff +#define HOST_IF_WINDOW_DATA_GET(x) (((x) & HOST_IF_WINDOW_DATA_MASK) >> HOST_IF_WINDOW_DATA_LSB) +#define HOST_IF_WINDOW_DATA_SET(x) (((x) << HOST_IF_WINDOW_DATA_LSB) & HOST_IF_WINDOW_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mbox_reg_reg_s { + volatile unsigned int mbox_fifo[4]; + volatile unsigned int mbox_fifo_status; + volatile unsigned int mbox_dma_policy; + volatile unsigned int mbox0_dma_rx_descriptor_base; + volatile unsigned int mbox0_dma_rx_control; + volatile unsigned int mbox0_dma_tx_descriptor_base; + volatile unsigned int mbox0_dma_tx_control; + volatile unsigned int mbox1_dma_rx_descriptor_base; + volatile unsigned int mbox1_dma_rx_control; + volatile unsigned int mbox1_dma_tx_descriptor_base; + volatile unsigned int mbox1_dma_tx_control; + volatile unsigned int mbox2_dma_rx_descriptor_base; + volatile unsigned int mbox2_dma_rx_control; + volatile unsigned int mbox2_dma_tx_descriptor_base; + volatile unsigned int mbox2_dma_tx_control; + volatile unsigned int mbox3_dma_rx_descriptor_base; + volatile unsigned int mbox3_dma_rx_control; + volatile unsigned int mbox3_dma_tx_descriptor_base; + volatile unsigned int mbox3_dma_tx_control; + volatile unsigned int mbox_int_status; + volatile unsigned int mbox_int_enable; + volatile unsigned int int_host; + unsigned char pad0[28]; /* pad to 0x80 */ + volatile unsigned int local_count[8]; + volatile unsigned int count_inc[8]; + volatile unsigned int local_scratch[8]; + volatile unsigned int use_local_bus; + volatile unsigned int sdio_config; + volatile unsigned int mbox_debug; + volatile unsigned int mbox_fifo_reset; + volatile unsigned int mbox_txfifo_pop[4]; + volatile unsigned int mbox_rxfifo_pop[4]; + volatile unsigned int sdio_debug; + unsigned char pad1[7916]; /* pad to 0x2000 */ + volatile unsigned int host_if_window[2048]; +} mbox_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/miscdrv.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/miscdrv.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/miscdrv.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/miscdrv.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,44 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _MISCDRV_H +#define _MISCDRV_H + + +#define HOST_INTEREST_ITEM_ADDRESS(target, item) \ +(((target) == TARGET_TYPE_AR6001) ? \ + AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \ + AR6002_HOST_INTEREST_ITEM_ADDRESS(item)) + +A_UINT32 ar6kRev2Array[][128] = { + {0xFFFF, 0xFFFF}, // No Patches + }; + +#define CFG_REV2_ITEMS 0 // no patches so far +#define AR6K_RESET_ADDR 0x4000 +#define AR6K_RESET_VAL 0x100 + +#define EEPROM_SZ 768 +#define EEPROM_WAIT_LIMIT 4 + +#endif + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/netbuf.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/netbuf.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/netbuf.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/netbuf.c 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,229 @@ + +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ +#include +#include +#include +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "htc_packet.h" + +#define AR6000_DATA_OFFSET 64 + +void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt) +{ + skb_queue_tail((struct sk_buff_head *) q, (struct sk_buff *) pkt); +} + +void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt) +{ + skb_queue_head((struct sk_buff_head *) q, (struct sk_buff *) pkt); +} + +void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q) +{ + return((void *) skb_dequeue((struct sk_buff_head *) q)); +} + +int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q) +{ + return(skb_queue_len((struct sk_buff_head *) q)); +} + +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q) +{ + return(skb_queue_empty((struct sk_buff_head *) q)); +} + +void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q) +{ + skb_queue_head_init((struct sk_buff_head *) q); +} + +void * +a_netbuf_alloc(int size) +{ + struct sk_buff *skb; + skb = dev_alloc_skb(AR6000_DATA_OFFSET + sizeof(HTC_PACKET) + size); + skb_reserve(skb, AR6000_DATA_OFFSET + sizeof(HTC_PACKET)); + return ((void *)skb); +} + +/* + * Allocate an SKB w.o. any encapsulation requirement. + */ +void * +a_netbuf_alloc_raw(int size) +{ + struct sk_buff *skb; + + skb = dev_alloc_skb(size); + + return ((void *)skb); +} + +void +a_netbuf_free(void *bufPtr) +{ + struct sk_buff *skb = (struct sk_buff *)bufPtr; + + dev_kfree_skb(skb); +} + +A_UINT32 +a_netbuf_to_len(void *bufPtr) +{ + return (((struct sk_buff *)bufPtr)->len); +} + +void * +a_netbuf_to_data(void *bufPtr) +{ + return (((struct sk_buff *)bufPtr)->data); +} + +/* + * Add len # of bytes to the beginning of the network buffer + * pointed to by bufPtr + */ +A_STATUS +a_netbuf_push(void *bufPtr, A_INT32 len) +{ + skb_push((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Add len # of bytes to the beginning of the network buffer + * pointed to by bufPtr and also fill with data + */ +A_STATUS +a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len) +{ + skb_push((struct sk_buff *) bufPtr, len); + A_MEMCPY(((struct sk_buff *)bufPtr)->data, srcPtr, len); + + return A_OK; +} + +/* + * Add len # of bytes to the end of the network buffer + * pointed to by bufPtr + */ +A_STATUS +a_netbuf_put(void *bufPtr, A_INT32 len) +{ + skb_put((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Add len # of bytes to the end of the network buffer + * pointed to by bufPtr and also fill with data + */ +A_STATUS +a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len) +{ + char *start = ((struct sk_buff *)bufPtr)->data + + ((struct sk_buff *)bufPtr)->len; + skb_put((struct sk_buff *)bufPtr, len); + A_MEMCPY(start, srcPtr, len); + + return A_OK; +} + + +/* + * Trim the network buffer pointed to by bufPtr to len # of bytes + */ +A_STATUS +a_netbuf_setlen(void *bufPtr, A_INT32 len) +{ + skb_trim((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Chop of len # of bytes from the end of the buffer. + */ +A_STATUS +a_netbuf_trim(void *bufPtr, A_INT32 len) +{ + skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len); + + return A_OK; +} + +/* + * Chop of len # of bytes from the end of the buffer and return the data. + */ +A_STATUS +a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len) +{ + char *start = ((struct sk_buff *)bufPtr)->data + + (((struct sk_buff *)bufPtr)->len - len); + + A_MEMCPY(dstPtr, start, len); + skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len); + + return A_OK; +} + + +/* + * Returns the number of bytes available to a a_netbuf_push() + */ +A_INT32 +a_netbuf_headroom(void *bufPtr) +{ + return (skb_headroom((struct sk_buff *)bufPtr)); +} + +/* + * Removes specified number of bytes from the beginning of the buffer + */ +A_STATUS +a_netbuf_pull(void *bufPtr, A_INT32 len) +{ + skb_pull((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Removes specified number of bytes from the beginning of the buffer + * and return the data + */ +A_STATUS +a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len) +{ + A_MEMCPY(dstPtr, ((struct sk_buff *)bufPtr)->data, len); + skb_pull((struct sk_buff *)bufPtr, len); + + return A_OK; +} + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/osapi_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/osapi_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/osapi_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/osapi_linux.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,333 @@ +/* + * $Id: //depot/sw/releases/olca2.2.0/host/os/linux/include/osapi_linux.h#1 $ + * + * This file contains the definitions of the basic atheros data types. + * It is used to map the data types in atheros files to a platform specific + * type. + * + * Copyright 2003-2005 Atheros Communications, Inc., All Rights Reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#ifndef _OSAPI_LINUX_H_ +#define _OSAPI_LINUX_H_ + +#ifdef __KERNEL__ + +#include +#include +#include +#include +#include +#include +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +#include +#endif +#include +#include +#include +#ifdef KERNEL_2_4 +#include +#include +#endif + +#ifdef __GNUC__ +#define __ATTRIB_PACK __attribute__ ((packed)) +#define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2))) +#define __ATTRIB_NORETURN __attribute__ ((noreturn)) +#ifndef INLINE +#define INLINE __inline__ +#endif +#else /* Not GCC */ +#define __ATTRIB_PACK +#define __ATTRIB_PRINTF +#define __ATTRIB_NORETURN +#ifndef INLINE +#define INLINE __inline +#endif +#endif /* End __GNUC__ */ + +#define PREPACK +#define POSTPACK __ATTRIB_PACK + +/* + * Endianes macros + */ +#define A_BE2CPU8(x) ntohb(x) +#define A_BE2CPU16(x) ntohs(x) +#define A_BE2CPU32(x) ntohl(x) + +#define A_LE2CPU8(x) (x) +#define A_LE2CPU16(x) (x) +#define A_LE2CPU32(x) (x) + +#define A_CPU2BE8(x) htonb(x) +#define A_CPU2BE16(x) htons(x) +#define A_CPU2BE32(x) htonl(x) + +#define A_MEMCPY(dst, src, len) memcpy((A_UINT8 *)(dst), (src), (len)) +#define A_MEMZERO(addr, len) memset(addr, 0, len) +#define A_MEMCMP(addr1, addr2, len) memcmp((addr1), (addr2), (len)) +#define A_MALLOC(size) kmalloc((size), GFP_KERNEL) +#define A_MALLOC_NOWAIT(size) kmalloc((size), GFP_ATOMIC) +#define A_FREE(addr) kfree(addr) +#define A_PRINTF(args...) printk(args) +#define A_SPRINTF(buf, args...) sprintf (buf, args) + +/* Mutual Exclusion */ +typedef spinlock_t A_MUTEX_T; +#define A_MUTEX_INIT(mutex) spin_lock_init(mutex) +#define A_MUTEX_LOCK(mutex) spin_lock_bh(mutex) +#define A_MUTEX_UNLOCK(mutex) spin_unlock_bh(mutex) +#define A_IS_MUTEX_VALID(mutex) TRUE /* okay to return true, since A_MUTEX_DELETE does nothing */ +#define A_MUTEX_DELETE(mutex) /* spin locks are not kernel resources so nothing to free.. */ + +/* Get current time in ms adding a constant offset (in ms) */ +#define A_GET_MS(offset) \ + (jiffies + ((offset) / 1000) * HZ) + +/* + * Timer Functions + */ +#define A_MDELAY(msecs) mdelay(msecs) +typedef struct timer_list A_TIMER; + +#define A_INIT_TIMER(pTimer, pFunction, pArg) do { \ + init_timer(pTimer); \ + (pTimer)->function = (pFunction); \ + (pTimer)->data = (unsigned long)(pArg); \ +} while (0) + +/* + * Start a Timer that elapses after 'periodMSec' milli-seconds + * Support is provided for a one-shot timer. The 'repeatFlag' is + * ignored. + */ +#define A_TIMEOUT_MS(pTimer, periodMSec, repeatFlag) do { \ + if (repeatFlag) { \ + printk("\n" __FILE__ ":%d: Timer Repeat requested\n",__LINE__); \ + panic("Timer Repeat"); \ + } \ + mod_timer((pTimer), jiffies + HZ * (periodMSec) / 1000); \ +} while (0) + +/* + * Cancel the Timer. + */ +#define A_UNTIMEOUT(pTimer) do { \ + del_timer((pTimer)); \ +} while (0) + +#define A_DELETE_TIMER(pTimer) do { \ +} while (0) + +/* + * Wait Queue related functions + */ +typedef wait_queue_head_t A_WAITQUEUE_HEAD; +#define A_INIT_WAITQUEUE_HEAD(head) init_waitqueue_head(head) +#ifndef wait_event_interruptible_timeout +#define __wait_event_interruptible_timeout(wq, condition, ret) \ +do { \ + wait_queue_t __wait; \ + init_waitqueue_entry(&__wait, current); \ + \ + add_wait_queue(&wq, &__wait); \ + for (;;) { \ + set_current_state(TASK_INTERRUPTIBLE); \ + if (condition) \ + break; \ + if (!signal_pending(current)) { \ + ret = schedule_timeout(ret); \ + if (!ret) \ + break; \ + continue; \ + } \ + ret = -ERESTARTSYS; \ + break; \ + } \ + current->state = TASK_RUNNING; \ + remove_wait_queue(&wq, &__wait); \ +} while (0) + +#define wait_event_interruptible_timeout(wq, condition, timeout) \ +({ \ + long __ret = timeout; \ + if (!(condition)) \ + __wait_event_interruptible_timeout(wq, condition, __ret); \ + __ret; \ +}) +#endif /* wait_event_interruptible_timeout */ + +#define A_WAIT_EVENT_INTERRUPTIBLE_TIMEOUT(head, condition, timeout) do { \ + wait_event_interruptible_timeout(head, condition, timeout); \ +} while (0) + +#define A_WAKE_UP(head) wake_up(head) + +#ifdef DEBUG +#define A_ASSERT(expr) \ + if (!(expr)) { \ + printk(KERN_ALERT "\n" __FILE__ ":%d: Assertion " #expr " failed!\n",__LINE__); \ + panic(#expr); \ + } + +#else +#define A_ASSERT(expr) +#endif /* DEBUG */ + +/* + * Initialization of the network buffer subsystem + */ +#define A_NETBUF_INIT() + +/* + * Network buffer queue support + */ +typedef struct sk_buff_head A_NETBUF_QUEUE_T; + +#define A_NETBUF_QUEUE_INIT(q) \ + a_netbuf_queue_init(q) + +#define A_NETBUF_ENQUEUE(q, pkt) \ + a_netbuf_enqueue((q), (pkt)) +#define A_NETBUF_PREQUEUE(q, pkt) \ + a_netbuf_prequeue((q), (pkt)) +#define A_NETBUF_DEQUEUE(q) \ + (a_netbuf_dequeue(q)) +#define A_NETBUF_QUEUE_SIZE(q) \ + a_netbuf_queue_size(q) +#define A_NETBUF_QUEUE_EMPTY(q) \ + a_netbuf_queue_empty(q) + +/* + * Network buffer support + */ +#define A_NETBUF_ALLOC(size) \ + a_netbuf_alloc(size) +#define A_NETBUF_ALLOC_RAW(size) \ + a_netbuf_alloc_raw(size) +#define A_NETBUF_FREE(bufPtr) \ + a_netbuf_free(bufPtr) +#define A_NETBUF_DATA(bufPtr) \ + a_netbuf_to_data(bufPtr) +#define A_NETBUF_LEN(bufPtr) \ + a_netbuf_to_len(bufPtr) +#define A_NETBUF_PUSH(bufPtr, len) \ + a_netbuf_push(bufPtr, len) +#define A_NETBUF_PUT(bufPtr, len) \ + a_netbuf_put(bufPtr, len) +#define A_NETBUF_TRIM(bufPtr,len) \ + a_netbuf_trim(bufPtr, len) +#define A_NETBUF_PULL(bufPtr, len) \ + a_netbuf_pull(bufPtr, len) +#define A_NETBUF_HEADROOM(bufPtr)\ + a_netbuf_headroom(bufPtr) +#define A_NETBUF_SETLEN(bufPtr,len) \ + a_netbuf_setlen(bufPtr, len) + +/* Add data to end of a buffer */ +#define A_NETBUF_PUT_DATA(bufPtr, srcPtr, len) \ + a_netbuf_put_data(bufPtr, srcPtr, len) + +/* Add data to start of the buffer */ +#define A_NETBUF_PUSH_DATA(bufPtr, srcPtr, len) \ + a_netbuf_push_data(bufPtr, srcPtr, len) + +/* Remove data at start of the buffer */ +#define A_NETBUF_PULL_DATA(bufPtr, dstPtr, len) \ + a_netbuf_pull_data(bufPtr, dstPtr, len) + +/* Remove data from the end of the buffer */ +#define A_NETBUF_TRIM_DATA(bufPtr, dstPtr, len) \ + a_netbuf_trim_data(bufPtr, dstPtr, len) + +/* View data as "size" contiguous bytes of type "t" */ +#define A_NETBUF_VIEW_DATA(bufPtr, t, size) \ + (t )( ((struct skbuf *)(bufPtr))->data) + +/* return the beginning of the headroom for the buffer */ +#define A_NETBUF_HEAD(bufPtr) \ + ((((struct sk_buff *)(bufPtr))->head)) + +/* + * OS specific network buffer access routines + */ +void *a_netbuf_alloc(int size); +void *a_netbuf_alloc_raw(int size); +void a_netbuf_free(void *bufPtr); +void *a_netbuf_to_data(void *bufPtr); +A_UINT32 a_netbuf_to_len(void *bufPtr); +A_STATUS a_netbuf_push(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len); +A_STATUS a_netbuf_put(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len); +A_STATUS a_netbuf_pull(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len); +A_STATUS a_netbuf_trim(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len); +A_STATUS a_netbuf_setlen(void *bufPtr, A_INT32 len); +A_INT32 a_netbuf_headroom(void *bufPtr); +void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt); +void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt); +void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q); +int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q); +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q); +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q); +void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q); + +/* + * Kernel v.s User space functions + */ +A_UINT32 a_copy_to_user(void *to, const void *from, A_UINT32 n); +A_UINT32 a_copy_from_user(void *to, const void *from, A_UINT32 n); + +/* In linux, WLAN Rx and Tx run in different contexts, so no need to check + * for any commands/data queued for WLAN */ +#define A_CHECK_DRV_TX() + +#else /* __KERNEL__ */ + +#ifdef __GNUC__ +#define __ATTRIB_PACK __attribute__ ((packed)) +#define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2))) +#define __ATTRIB_NORETURN __attribute__ ((noreturn)) +#ifndef INLINE +#define INLINE __inline__ +#endif +#else /* Not GCC */ +#define __ATTRIB_PACK +#define __ATTRIB_PRINTF +#define __ATTRIB_NORETURN +#ifndef INLINE +#define INLINE __inline +#endif +#endif /* End __GNUC__ */ + +#define PREPACK +#define POSTPACK __ATTRIB_PACK + +#define A_MEMCPY(dst, src, len) memcpy((dst), (src), (len)) +#define A_MEMZERO(addr, len) memset((addr), 0, (len)) +#define A_MEMCMP(addr1, addr2, len) memcmp((addr1), (addr2), (len)) +#define A_MALLOC(size) malloc(size) +#define A_FREE(addr) free(addr) +#endif /* __KERNEL__ */ + +#endif /* _OSAPI_LINUX_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/regDb.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/regDb.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/regDb.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/regDb.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,30 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2005 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __REG_DB_H__ +#define __REG_DB_H__ + +#include "reg_dbschema.h" +#include "reg_dbvalues.h" + +#endif /* __REG_DB_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/regTableData.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/regTableData.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/regTableData.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/regTableData.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,456 @@ +/* + * Copyright (c) 2004-2005 Atheros Communications Inc. + * All rights reserved. + * + * + * This file contains the actual Regulatory domain data. Use the + * DB schema from etna/include/regulatory/reg_dbschema.h and + * values from etna/include/regulatory/reg_dbvalues.h + * These Data definations are used by both generator and parser! + * + */ + +#ifndef __AH_REG_TABLE_DATA_H__ +#define __AH_REG_TABLE_DATA_H__ + +static REG_DMN_PAIR_MAPPING regDomainPairs[] = { + {NO_ENUMRD, DEBUG_REG_DMN, DEBUG_REG_DMN, NO_REQ, NO_REQ, PSCAN_DEFER}, + {NULL1_WORLD, NULL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + {NULL1_ETSIB, NULL1, ETSIB, NO_REQ, NO_REQ, PSCAN_DEFER}, + {NULL1_ETSIC, NULL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER}, + + {FCC2_FCCA, FCC2, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER}, + {FCC2_WORLD, FCC2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + {FCC2_ETSIC, FCC2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER}, + {FCC3_FCCA, FCC3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER}, + {FCC3_WORLD, FCC3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + {FCC5_FCCA, FCC5, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER}, + + {ETSI1_WORLD, ETSI1, WORLD, DISALLOW_ADHOC_11A, NO_REQ, PSCAN_DEFER}, + {ETSI2_WORLD, ETSI2, WORLD, DISALLOW_ADHOC_11A, NO_REQ, PSCAN_DEFER}, + {ETSI3_WORLD, ETSI3, WORLD, DISALLOW_ADHOC_11A, NO_REQ, PSCAN_DEFER}, + {ETSI4_WORLD, ETSI4, WORLD, DISALLOW_ADHOC_11A, NO_REQ, PSCAN_DEFER}, + {ETSI5_WORLD, ETSI5, WORLD, DISALLOW_ADHOC_11A, NO_REQ, PSCAN_DEFER}, + {ETSI6_WORLD, ETSI6, WORLD, DISALLOW_ADHOC_11A, NO_REQ, PSCAN_DEFER}, + + {FRANCE_RES, ETSI3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + + {FCC1_WORLD, FCC1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + {FCC1_FCCA, FCC1, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER}, + {APL1_WORLD, APL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + {APL2_WORLD, APL2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + {APL3_WORLD, APL3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + {APL7_FCCA, APL7, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER}, + {APL4_WORLD, APL4, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + {APL5_WORLD, APL5, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + {APL6_WORLD, APL6, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + {APL10_WORLD, APL10, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + {APL9_WORLD, APL9, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + + {APL1_ETSIC, APL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER}, + {APL2_ETSIC, APL2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER}, + {APL2_APLD, APL2, APLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + + {MKK5_MKKA, MKK5, MKKA, NO_REQ, NO_REQ, PSCAN_DEFER}, + {MKK5_FCCA, MKK5, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER}, + {MKK5_MKKC, MKK5, MKKC, NO_REQ, NO_REQ, PSCAN_DEFER}, + {MKK11_MKKA, MKK11, MKKA, NO_REQ, NO_REQ, PSCAN_DEFER}, + {MKK11_FCCA, MKK11, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER}, + {MKK11_MKKC, MKK11, MKKC, NO_REQ, NO_REQ, PSCAN_DEFER}, + + /* These are super domains */ + {WOR0_WORLD, WOR0_WORLD, WOR0_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + {WOR1_WORLD, WOR1_WORLD, WOR1_WORLD, DISALLOW_ADHOC_11A, NO_REQ, PSCAN_DEFER}, + {WOR2_WORLD, WOR2_WORLD, WOR2_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + {WOR3_WORLD, WOR3_WORLD, WOR3_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + {WOR4_WORLD, WOR4_WORLD, WOR4_WORLD, DISALLOW_ADHOC_11A, NO_REQ, PSCAN_DEFER}, + {WOR5_ETSIC, WOR5_ETSIC, WOR5_ETSIC, DISALLOW_ADHOC_11A, NO_REQ, PSCAN_DEFER}, + {WOR01_WORLD, WOR01_WORLD, WOR01_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + {WOR02_WORLD, WOR02_WORLD, WOR02_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + {EU1_WORLD, EU1_WORLD, EU1_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER}, + {WOR9_WORLD, WOR9_WORLD, WOR9_WORLD, DISALLOW_ADHOC_11A, NO_REQ, PSCAN_DEFER}, + {WORA_WORLD, WORA_WORLD, WORA_WORLD, DISALLOW_ADHOC_11A, NO_REQ, PSCAN_DEFER} +}; + + +static COUNTRY_CODE_TO_ENUM_RD allCountries[] = { + {CTRY_DEBUG, NO_ENUMRD, "DB", REGDB_YES}, + {CTRY_DEFAULT, DEF_REGDMN, "NA", REGDB_YES}, + {CTRY_ALBANIA, NULL1_WORLD, "AL", REGDB_YES}, + {CTRY_ALGERIA, NULL1_WORLD, "DZ", REGDB_YES}, + {CTRY_ARGENTINA, APL3_WORLD, "AR", REGDB_YES}, + {CTRY_ARMENIA, ETSI4_WORLD, "AM", REGDB_YES}, + {CTRY_AUSTRALIA, FCC3_WORLD, "AU", REGDB_YES}, + {CTRY_AUSTRIA, ETSI1_WORLD, "AT", REGDB_YES}, + {CTRY_AZERBAIJAN, ETSI4_WORLD, "AZ", REGDB_YES}, + {CTRY_BAHRAIN, APL6_WORLD, "BH", REGDB_YES}, + {CTRY_BELARUS, ETSI1_WORLD, "BY", REGDB_YES}, + {CTRY_BELGIUM, ETSI1_WORLD, "BE", REGDB_YES}, + {CTRY_BELIZE, APL1_ETSIC, "BZ", REGDB_YES}, + {CTRY_BOLIVIA, APL1_ETSIC, "BO", REGDB_YES}, + {CTRY_BOSNIA_HERZEGOWANIA, + ETSI1_WORLD, "BA", REGDB_YES}, + {CTRY_BRAZIL, FCC3_WORLD, "BR", REGDB_YES}, + {CTRY_BRUNEI_DARUSSALAM,APL6_WORLD,"BN", REGDB_YES}, + {CTRY_BULGARIA, ETSI1_WORLD, "BG", REGDB_YES}, + {CTRY_CANADA, FCC2_FCCA, "CA", REGDB_YES}, + {CTRY_CHILE, APL6_WORLD, "CL", REGDB_YES}, + {CTRY_CHINA, APL1_WORLD, "CN", REGDB_YES}, + {CTRY_COLOMBIA, FCC1_FCCA, "CO", REGDB_YES}, + {CTRY_COSTA_RICA, FCC1_WORLD, "CR", REGDB_YES}, + {CTRY_CROATIA, ETSI3_WORLD, "HR", REGDB_YES}, + {CTRY_CYPRUS, ETSI1_WORLD, "CY", REGDB_YES}, + {CTRY_CZECH, ETSI1_WORLD, "CZ", REGDB_YES}, + {CTRY_DENMARK, ETSI1_WORLD, "DK", REGDB_YES}, + {CTRY_DOMINICAN_REPUBLIC,FCC1_FCCA,"DO", REGDB_YES}, + {CTRY_ECUADOR, FCC1_WORLD, "EC", REGDB_YES}, + {CTRY_EGYPT, ETSI3_WORLD, "EG", REGDB_YES}, + {CTRY_EL_SALVADOR, FCC1_WORLD, "SV", REGDB_YES}, + {CTRY_ESTONIA, ETSI1_WORLD, "EE", REGDB_YES}, + {CTRY_FINLAND, ETSI1_WORLD, "FI", REGDB_YES}, + {CTRY_FRANCE, ETSI1_WORLD, "FR", REGDB_YES}, + {CTRY_FRANCE2, ETSI3_WORLD, "F2", REGDB_YES}, + {CTRY_GEORGIA, ETSI4_WORLD, "GE", REGDB_YES}, + {CTRY_GERMANY, ETSI1_WORLD, "DE", REGDB_YES}, + {CTRY_GREECE, ETSI1_WORLD, "GR", REGDB_YES}, + {CTRY_GUATEMALA, FCC1_FCCA, "GT", REGDB_YES}, + {CTRY_HONDURAS, FCC3_WORLD, "HN", REGDB_YES}, + {CTRY_HONG_KONG, FCC2_WORLD, "HK", REGDB_YES}, + {CTRY_HUNGARY, ETSI1_WORLD, "HU", REGDB_YES}, + {CTRY_ICELAND, ETSI1_WORLD, "IS", REGDB_YES}, + {CTRY_INDIA, APL6_WORLD, "IN", REGDB_YES}, + {CTRY_INDONESIA, APL1_WORLD, "ID", REGDB_YES}, + {CTRY_IRAN, APL1_WORLD, "IR", REGDB_YES}, + {CTRY_IRELAND, ETSI1_WORLD, "IE", REGDB_YES}, + {CTRY_ISRAEL, ETSI3_WORLD, "IL", REGDB_YES}, + {CTRY_ITALY, ETSI1_WORLD, "IT", REGDB_YES}, + {CTRY_JAMAICA, ETSI1_WORLD, "JM", REGDB_YES}, + {CTRY_JAPAN, MKK5_MKKC, "JP", REGDB_YES}, + {CTRY_JORDAN, ETSI2_WORLD, "JO", REGDB_YES}, + {CTRY_KAZAKHSTAN, NULL1_WORLD, "KZ", REGDB_YES}, + {CTRY_KENYA, NULL1_WORLD, "KE", REGDB_YES}, + {CTRY_KOREA_NORTH, APL9_WORLD, "KP", REGDB_YES}, + {CTRY_KOREA_ROC, APL10_WORLD, "KR", REGDB_YES}, + {CTRY_KOREA_ROC2, APL2_APLD, "K2", REGDB_YES}, + {CTRY_KOREA_ROC3, APL9_WORLD, "K3", REGDB_YES}, + {CTRY_KUWAIT, NULL1_WORLD, "KW", REGDB_YES}, + {CTRY_LATVIA, ETSI1_WORLD, "LV", REGDB_YES}, + {CTRY_LEBANON, APL1_WORLD, "LB", REGDB_YES}, + {CTRY_LIECHTENSTEIN,ETSI1_WORLD, "LI", REGDB_YES}, + {CTRY_LITHUANIA, ETSI1_WORLD, "LT", REGDB_YES}, + {CTRY_LUXEMBOURG, ETSI1_WORLD, "LU", REGDB_YES}, + {CTRY_MACAU, FCC2_WORLD, "MO", REGDB_YES}, + {CTRY_MACEDONIA, ETSI1_WORLD, "MK", REGDB_YES}, + {CTRY_MALAYSIA, FCC1_WORLD, "MY", REGDB_NO}, + {CTRY_MALTA, ETSI1_WORLD, "MT", REGDB_YES}, + {CTRY_MEXICO, FCC1_FCCA, "MX", REGDB_YES}, + {CTRY_MONACO, ETSI4_WORLD, "MC", REGDB_YES}, + {CTRY_MOROCCO, APL4_WORLD, "MA", REGDB_YES}, + {CTRY_NEW_ZEALAND, FCC2_ETSIC, "NZ", REGDB_YES}, + {CTRY_NETHERLANDS, ETSI1_WORLD, "NL", REGDB_YES}, + {CTRY_NETHERLAND_ANTILLES, + ETSI1_WORLD, "AN", REGDB_YES}, + {CTRY_NORWAY, ETSI1_WORLD, "NO", REGDB_YES}, + {CTRY_OMAN, APL6_WORLD, "OM", REGDB_YES}, + {CTRY_PAKISTAN, APL1_WORLD, "PK", REGDB_YES}, + {CTRY_PANAMA, FCC1_FCCA, "PA", REGDB_YES}, + {CTRY_PERU, FCC3_WORLD, "PE", REGDB_YES}, + {CTRY_PHILIPPINES, FCC3_WORLD, "PH", REGDB_YES}, + {CTRY_POLAND, ETSI1_WORLD, "PL", REGDB_YES}, + {CTRY_PORTUGAL, ETSI1_WORLD, "PT", REGDB_YES}, + {CTRY_PUERTO_RICO, FCC1_FCCA, "PR", REGDB_YES}, + {CTRY_QATAR, NULL1_WORLD, "QA", REGDB_YES}, + {CTRY_ROMANIA, ETSI1_WORLD, "RO", REGDB_YES}, + {CTRY_RUSSIA, FCC3_WORLD, "RU", REGDB_YES}, + {CTRY_SAUDI_ARABIA,FCC2_WORLD, "SA", REGDB_YES}, + {CTRY_MONTENEGRO, ETSI1_WORLD, "CS", REGDB_YES}, + {CTRY_SINGAPORE, APL6_WORLD, "SG", REGDB_YES}, + {CTRY_SLOVAKIA, ETSI1_WORLD, "SK", REGDB_YES}, + {CTRY_SLOVENIA, ETSI1_WORLD, "SI", REGDB_YES}, + {CTRY_SOUTH_AFRICA,FCC3_WORLD, "ZA", REGDB_YES}, + {CTRY_SPAIN, ETSI1_WORLD, "ES", REGDB_YES}, + {CTRY_SRILANKA, FCC3_WORLD, "LK", REGDB_YES}, + {CTRY_SWEDEN, ETSI1_WORLD, "SE", REGDB_YES}, + {CTRY_SWITZERLAND, ETSI1_WORLD, "CH", REGDB_YES}, + {CTRY_SYRIA, NULL1_WORLD, "SY", REGDB_YES}, + {CTRY_TAIWAN, APL7_FCCA, "TW", REGDB_YES}, + {CTRY_THAILAND, FCC3_WORLD, "TH", REGDB_YES}, + {CTRY_TRINIDAD_Y_TOBAGO,ETSI4_WORLD,"TT", REGDB_YES}, + {CTRY_TUNISIA, ETSI3_WORLD, "TN", REGDB_YES}, + {CTRY_TURKEY, ETSI3_WORLD, "TR", REGDB_YES}, + {CTRY_UKRAINE, NULL1_WORLD, "UA", REGDB_YES}, + {CTRY_UAE, ETSI1_WORLD, "AE", REGDB_YES}, + {CTRY_UNITED_KINGDOM, ETSI1_WORLD,"GB", REGDB_YES}, + {CTRY_UNITED_STATES, FCC3_FCCA, "US", REGDB_YES}, + {CTRY_URUGUAY, FCC1_WORLD, "UY", REGDB_YES}, + {CTRY_UZBEKISTAN, FCC3_FCCA, "UZ", REGDB_YES}, + {CTRY_VENEZUELA, FCC1_WORLD, "VE", REGDB_YES}, + {CTRY_VIET_NAM, NULL1_WORLD, "VN", REGDB_YES}, + {CTRY_YEMEN, NULL1_WORLD, "YE", REGDB_YES}, + {CTRY_ZIMBABWE, NULL1_WORLD, "ZW", REGDB_YES} +}; + + +static REG_DMN_FREQ_BAND regDmn5GhzFreq[] = { + { 4920, 4980, 20, 20, NO_DFS, MODE_11A, NO_PSCAN}, /* F1_4920_4980 */ + { 5040, 5080, 20, 20, NO_DFS, MODE_11A, NO_PSCAN}, /* F1_5040_5080 */ + + { 5120, 5240, 5, 20, NO_DFS, MODE_11A, NO_PSCAN}, /* F1_5120_5240 */ + + { 5180, 5240, 15, 20, DFS_ETSI, MODE_11A, PSCAN_FCC | PSCAN_ETSI}, /* F1_5180_5240 */ + { 5180, 5240, 17, 20, NO_DFS, MODE_11A, NO_PSCAN}, /* F2_5180_5240 */ + { 5180, 5240, 18, 20, NO_DFS, MODE_11A, PSCAN_FCC}, /* F3_5180_5240 */ + { 5180, 5240, 20, 20, NO_DFS, MODE_11A, NO_PSCAN}, /* F4_5180_5240 */ + { 5180, 5240, 20, 20, DFS_ETSI, MODE_11A, PSCAN_FCC | PSCAN_ETSI}, /* F5_5180_5240 */ + { 5180, 5240, 23, 20, NO_DFS, MODE_11A, PSCAN_ETSI}, /* F6_5180_5240 */ + { 5260, 5280, 23, 20, DFS_FCC3 | DFS_ETSI, MODE_11A, PSCAN_FCC | PSCAN_ETSI}, /* F1_5260_5280 */ + + { 5260, 5320, 18, 20, DFS_FCC3 | DFS_ETSI, MODE_11A, PSCAN_FCC | PSCAN_ETSI}, /* F1_5260_5320 */ + + { 5260, 5320, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK, MODE_11A, + PSCAN_FCC | PSCAN_ETSI | PSCAN_MKK}, /* F2_5260_5320 */ + + { 5260, 5320, 30, 20, DFS_FCC3 | DFS_ETSI, MODE_11A, PSCAN_FCC}, /* F3_5260_5320 */ + { 5260, 5320, 23, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK, MODE_11A, PSCAN_FCC}, /* F4_5260_5320 */ + + { 5260, 5700, 5, 20, DFS_FCC3 | DFS_ETSI, MODE_11A, NO_PSCAN}, /* F1_5260_5700 */ + + { 5280, 5320, 17, 20, DFS_FCC3 | DFS_ETSI, MODE_11A, PSCAN_FCC}, /* F1_5280_5320 */ + + { 5500, 5620, 30, 20, DFS_FCC3 | DFS_ETSI, MODE_11A, PSCAN_FCC}, /* F1_5500_5620 */ + + { 5500, 5700, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK, MODE_11A, PSCAN_FCC | PSCAN_MKK}, /* F1_5500_5700 */ + { 5500, 5700, 27, 20, DFS_FCC3 | DFS_ETSI, MODE_11A, PSCAN_FCC | PSCAN_ETSI}, /* F2_5500_5700 */ + { 5500, 5700, 30, 20, DFS_FCC3 | DFS_ETSI, MODE_11A, PSCAN_FCC | PSCAN_ETSI}, /* F3_5500_5700 */ + { 5500, 5700, 23, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK, MODE_11A, PSCAN_FCC}, + /* F4_5500_5700 */ + { 5500, 5700, 17, 20, DFS_FCC3 | DFS_ETSI, MODE_11A, PSCAN_FCC}, /* F5_5500_5700 */ + + + { 5745, 5805, 23, 20, NO_DFS, MODE_11A, NO_PSCAN}, /* F1_5745_5805 */ + { 5745, 5805, 30, 20, NO_DFS, MODE_11A, NO_PSCAN}, /* F2_5745_5805 */ + + { 5745, 5825, 5, 20, NO_DFS, MODE_11A, NO_PSCAN}, /* F1_5745_5825 */ + { 5745, 5825, 17, 20, NO_DFS, MODE_11A, NO_PSCAN}, /* F2_5745_5825 */ + { 5745, 5825, 20, 20, NO_DFS, MODE_11A, NO_PSCAN}, /* F3_5745_5825 */ + { 5745, 5825, 30, 20, NO_DFS, MODE_11A, NO_PSCAN}, /* F4_5745_5825 */ + { 5745, 5825, 30, 20, NO_DFS, MODE_11A, NO_PSCAN}, /* F5_5745_5825 */ + + /* Below are the world roaming channels */ + + { 4920, 4980, 17, 20, NO_DFS, MODE_11A, PSCAN_WWR}, /* W1_4920_4980 */ + { 5040, 5080, 17, 20, NO_DFS, MODE_11A, PSCAN_WWR}, /* W1_5040_5080 */ + { 5170, 5230, 15, 20, DFS_FCC3 | DFS_ETSI, MODE_11A, PSCAN_WWR}, /* W1_5170_5230 */ + { 5180, 5240, 15, 20, DFS_FCC3 | DFS_ETSI, MODE_11A, PSCAN_WWR}, /* W1_5180_5240 */ + { 5260, 5320, 18, 20, DFS_FCC3 | DFS_ETSI, MODE_11A, PSCAN_WWR}, /* W1_5260_5320 */ + { 5745, 5825, 20, 20, NO_DFS, MODE_11A, PSCAN_WWR}, /* W1_5745_5825 */ + { 5500, 5700, 20, 20, DFS_FCC3 | DFS_ETSI, MODE_11A, PSCAN_WWR}, /* W1_5500_5700 */ +}; + +static REG_DMN_FREQ_BAND regDmn2Ghz_BG_Freq[] = { + { 2312, 2372, 5, 5, NO_DFS, MODE_11G, NO_PSCAN}, /* BG1_2312_2372 */ + { 2312, 2372, 20, 5, NO_DFS, MODE_11G, NO_PSCAN}, /* BG2_2312_2372 */ + + { 2412, 2472, 5, 5, NO_DFS, MODE_11G, NO_PSCAN}, /* BG1_2412_2472 */ + { 2412, 2472, 20, 5, NO_DFS, MODE_11G, NO_PSCAN}, /* BG2_2412_2472 */ + { 2412, 2472, 30, 5, NO_DFS, MODE_11G, NO_PSCAN}, /* BG3_2412_2472 */ + + { 2412, 2462, 27, 5, NO_DFS, MODE_11G, NO_PSCAN}, /* BG1_2412_2462 */ + { 2412, 2462, 20, 5, NO_DFS, MODE_11G, NO_PSCAN}, /* BG2_2412_2462 */ + + { 2432, 2442, 20, 5, NO_DFS, MODE_11G, NO_PSCAN}, /* BG1_2432_2442 */ + + { 2457, 2472, 20, 5, NO_DFS, MODE_11G, NO_PSCAN}, /* BG1_2457_2472 */ + + { 2467, 2472, 20, 5, NO_DFS, MODE_11G, NO_PSCAN}, /* BG1_2467_2472 */ + + { 2484, 2484, 5, 5, NO_DFS, MODE_11B, NO_PSCAN}, /* BG1_2484_2484 */ + { 2484, 2484, 20, 5, NO_DFS, MODE_11B, NO_PSCAN}, /* BG2_2484_2484 */ + + { 2512, 2732, 5, 5, NO_DFS, MODE_11G, NO_PSCAN}, /* BG1_2512_2732 */ + + { 2312, 2372, 18, 5, NO_DFS, MODE_11G, NO_PSCAN}, /* WBG1_2312_2372 */ + { 2412, 2412, 18, 5, NO_DFS, MODE_11G, NO_PSCAN}, /* WBG1_2412_2412 */ + { 2417, 2432, 18, 5, NO_DFS, MODE_11G, NO_PSCAN}, /* WBG1_2417_2432 */ + { 2437, 2442, 18, 5, NO_DFS, MODE_11G, NO_PSCAN}, /* WBG1_2437_2442 */ + { 2447, 2457, 18, 5, NO_DFS, MODE_11G, NO_PSCAN}, /* WBG1_2447_2457 */ + { 2462, 2462, 18, 5, NO_DFS, MODE_11G, NO_PSCAN}, /* WBG1_2462_2462 */ + { 2467, 2467, 18, 5, NO_DFS, MODE_11G, PSCAN_WWR}, /* WBG1_2467_2467 */ + { 2467, 2467, 18, 5, NO_DFS, MODE_11G, NO_PSCAN}, /* WBG2_2467_2467 */ + { 2472, 2472, 18, 5, NO_DFS, MODE_11G, PSCAN_WWR}, /* WBG1_2472_2472 */ + { 2472, 2472, 18, 5, NO_DFS, MODE_11G, NO_PSCAN}, /* WBG2_2472_2472 */ + { 2484, 2484, 18, 5, NO_DFS, MODE_11B, PSCAN_WWR}, /* WBG1_2484_2484 */ + { 2484, 2484, 18, 5, NO_DFS, MODE_11B, NO_PSCAN}, /* WBG2_2484_2484 */ +}; + + + +static REG_DOMAIN regDomains[] = { + + {DEBUG_REG_DMN, FCC, 6, DFS_FCC3, NO_REQ, 0, NO_PSCAN, + BM(F1_5120_5240, F1_5260_5700, F1_5745_5825, -1, -1, -1, -1, -1), + BM(BG1_2312_2372, BG1_2412_2472, BG1_2484_2484, -1, -1, -1, -1, -1)}, + + {APL1, ETSI, 6, NO_DFS, NO_REQ, 0, NO_PSCAN, + BM(F4_5745_5825, -1, -1, -1, -1, -1, -1, -1), + BMZERO}, + + {APL2, ETSI, 6, NO_DFS, NO_REQ, 0, NO_PSCAN, + BM(F1_5745_5805, -1, -1, -1, -1, -1, -1, -1), + BMZERO}, + + {APL3, FCC, 6, DFS_FCC3, NO_REQ, 0, PSCAN_FCC, + BM(F1_5280_5320, F4_5745_5825, -1, -1, -1, -1, -1, -1), + BMZERO}, + + {APL4, ETSI, 6, NO_DFS, NO_REQ, 0, NO_PSCAN, + BM(F4_5180_5240, F3_5745_5825, -1, -1, -1, -1, -1, -1), + BMZERO}, + + {APL5, ETSI, 6, NO_DFS, NO_REQ, 0, NO_PSCAN, + BM(F2_5745_5825, -1, -1, -1, -1, -1, -1, -1), + BMZERO}, + + {APL6, ETSI, 0, DFS_ETSI, NO_REQ, 0, PSCAN_ETSI, + BM(F4_5180_5240, F2_5260_5320, F3_5745_5825, -1, -1, -1, -1, -1), + BMZERO}, + + {APL7, FCC, 0, DFS_ETSI, NO_REQ, 0, PSCAN_FCC, + BM(F1_5280_5320, F3_5500_5700, F2_5745_5805, -1, -1, -1, -1, -1), + BMZERO}, + + {APL10, ETSI, 0, DFS_ETSI, NO_REQ, 0, PSCAN_FCC, + BM(F4_5180_5240, F2_5260_5320, F3_5500_5700, F2_5745_5805, -1, -1, -1, -1), + BMZERO}, + + {APL9, ETSI, 0, DFS_ETSI, NO_REQ, 0, PSCAN_FCC, + BM(F4_5180_5240, F2_5260_5320, F1_5500_5620, F2_5745_5805, -1, -1, -1, -1), + BMZERO}, + + {ETSI1, ETSI, 0, DFS_ETSI, DISALLOW_ADHOC_11A, 0, PSCAN_ETSI, + BM(F4_5180_5240, F2_5260_5320, F2_5500_5700, -1, -1, -1, -1, -1), + BMZERO}, + + {ETSI2, ETSI, 0, DFS_ETSI, DISALLOW_ADHOC_11A, 0, PSCAN_ETSI, + BM(F3_5180_5240, -1, -1, -1, -1, -1, -1, -1), + BMZERO}, + + {ETSI3, ETSI, 0, DFS_ETSI, DISALLOW_ADHOC_11A, 0, PSCAN_ETSI, + BM(F4_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1), + BMZERO}, + + {ETSI4, ETSI, 0, DFS_ETSI, DISALLOW_ADHOC_11A, 0, PSCAN_ETSI, + BM(F3_5180_5240, F1_5260_5320, -1, -1, -1, -1, -1, -1), + BMZERO}, + + {ETSI5, ETSI, 0, DFS_ETSI, DISALLOW_ADHOC_11A, 0, PSCAN_ETSI, + BM(F1_5180_5240, -1, -1, -1, -1, -1, -1, -1), + BMZERO}, + + {ETSI6, ETSI, 0, DFS_ETSI, DISALLOW_ADHOC_11A, 0, PSCAN_ETSI, + BM(F6_5180_5240,F1_5260_5280, F3_5500_5700, -1, -1, -1, -1, -1), + BMZERO}, + + {FCC1, FCC, 6, DFS_FCC3, NO_REQ, 0, PSCAN_FCC, + BM(F2_5180_5240,F4_5260_5320,F5_5745_5825, -1, -1, -1, -1, -1), + BMZERO}, + + {FCC2, FCC, 6, DFS_FCC3, NO_REQ, 0, PSCAN_FCC, + BM(F6_5180_5240,F4_5260_5320,F5_5745_5825, -1, -1, -1, -1, -1), + BMZERO}, + + {FCC3, FCC, 6, DFS_FCC3, NO_REQ, 0, PSCAN_FCC, + BM(F2_5180_5240, F2_5260_5320, F1_5500_5700, F5_5745_5825, -1, -1, -1, -1), + BMZERO}, + + {FCC5, FCC, 6, NO_DFS, NO_REQ, 0, NO_PSCAN, + BM(F2_5180_5240, F5_5745_5825, -1, -1, -1, -1, -1, -1), + BMZERO}, + + {MKK5, MKK, 3, DFS_MKK, NO_REQ, 0, PSCAN_MKK, + BM(F4_5180_5240, F2_5260_5320, F1_5500_5700, -1, -1, -1, -1, -1), + BMZERO}, + + {MKK11, MKK, 3, DFS_MKK, NO_REQ, 0, PSCAN_MKK, + BM(F1_4920_4980, F1_5040_5080, F4_5180_5240, F2_5260_5320, F1_5500_5700, -1, -1, -1), + BMZERO}, + + {APLD, NO_CTL, 3, NO_DFS, NO_REQ, 0, NO_PSCAN, + BMZERO, + BM(BG2_2312_2372, BG2_2412_2472, -1, -1, -1, -1, -1, -1)}, + + {ETSIB, ETSI, 0, NO_DFS, DISALLOW_ADHOC_11A, 0, PSCAN_ETSIB, + BMZERO, + BM(BG1_2432_2442,-1,-1,-1,-1,-1,-1,-1)}, + + {ETSIC, ETSI, 0, NO_DFS, DISALLOW_ADHOC_11A, 0, PSCAN_ETSIC, + BMZERO, + BM(BG3_2412_2472,-1,-1,-1,-1,-1,-1,-1)}, + + {FCCA, FCC, 6, NO_DFS, NO_REQ, 0, NO_PSCAN, + BMZERO, + BM(BG1_2412_2462,-1,-1,-1,-1,-1,-1,-1)}, + + {MKKA, MKK, 3, NO_DFS, NO_REQ, 0, NO_PSCAN, + BMZERO, + BM(BG2_2412_2462, BG1_2467_2472, BG2_2484_2484, -1, -1, -1, -1, -1)}, + + {MKKC, MKK, 3, NO_DFS, NO_REQ, 0, NO_PSCAN, + BMZERO, + BM(BG2_2412_2472,-1,-1,-1,-1,-1,-1,-1)}, + + {WORLD, ETSI, 0, NO_DFS, NO_REQ, 0, NO_PSCAN, + BMZERO, + BM(BG2_2412_2472,-1,-1,-1,-1,-1,-1,-1)}, + + {WOR0_WORLD, NO_CTL, 0, DFS_FCC3 | DFS_ETSI, ADHOC_PER_11D, 0, PSCAN_WWR, + BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1), + BM(WBG1_2412_2412,WBG1_2437_2442,WBG1_2462_2462,WBG1_2472_2472,WBG1_2417_2432, WBG1_2447_2457, WBG1_2467_2467, WBG1_2484_2484)}, + + {WOR01_WORLD, NO_CTL, 0, DFS_FCC3 | DFS_ETSI, ADHOC_PER_11D, 0, PSCAN_WWR, + BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1), + BM(WBG1_2412_2412, WBG1_2437_2442, WBG1_2462_2462, WBG1_2417_2432, WBG1_2447_2457, -1, -1, -1)}, + + {WOR02_WORLD, NO_CTL, 0, DFS_FCC3 | DFS_ETSI, ADHOC_PER_11D, 0, PSCAN_WWR, + BM(W1_5260_5320, W1_5180_5240,W1_5170_5230,W1_5745_5825,W1_5500_5700, -1, -1, -1), + BM(WBG1_2412_2412,WBG1_2437_2442,WBG1_2462_2462, WBG1_2472_2472,WBG1_2417_2432, WBG1_2447_2457, WBG1_2467_2467, -1)}, + + {EU1_WORLD, NO_CTL, 0, DFS_FCC3 | DFS_ETSI, ADHOC_PER_11D, 0, PSCAN_WWR, + BM(W1_5260_5320, W1_5180_5240,W1_5170_5230,W1_5745_5825,W1_5500_5700, -1, -1, -1), + BM(WBG1_2412_2412,WBG1_2437_2442,WBG1_2462_2462, WBG2_2472_2472,WBG1_2417_2432, WBG1_2447_2457, WBG2_2467_2467, -1)}, + + {WOR1_WORLD, NO_CTL, 0, DFS_FCC3 | DFS_ETSI, ADHOC_NO_11A, 0, PSCAN_WWR, + BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1), + BM(WBG1_2412_2412,WBG1_2437_2442,WBG1_2462_2462,WBG1_2472_2472,WBG1_2417_2432, WBG1_2447_2457, WBG1_2467_2467, WBG1_2484_2484)}, + + {WOR2_WORLD, NO_CTL, 0, DFS_FCC3 | DFS_ETSI, ADHOC_NO_11A, 0, PSCAN_WWR, + BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1), + BM(WBG1_2412_2412,WBG1_2437_2442,WBG1_2462_2462,WBG2_2472_2472,WBG1_2417_2432, WBG1_2447_2457, WBG2_2467_2467, WBG2_2484_2484)}, + + {WOR3_WORLD, NO_CTL, 0, DFS_FCC3 | DFS_ETSI, ADHOC_PER_11D, 0, PSCAN_WWR, + BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, -1, -1, -1, -1), + BM(WBG1_2412_2412,WBG1_2437_2442,WBG1_2462_2462,WBG2_2472_2472,WBG1_2417_2432, WBG1_2447_2457, WBG2_2467_2467, -1)}, + + {WOR4_WORLD, NO_CTL, 0, DFS_FCC3 | DFS_ETSI, ADHOC_NO_11A, 0, PSCAN_WWR, + BM(W1_5260_5320, W1_5180_5240,W1_5745_5825, -1, -1, -1, -1, -1), + BM(WBG1_2412_2412,WBG1_2437_2442,WBG1_2462_2462, WBG1_2417_2432,WBG1_2447_2457,-1, -1, -1)}, + + {WOR5_ETSIC, NO_CTL, 0, DFS_FCC3 | DFS_ETSI, ADHOC_NO_11A, 0, PSCAN_WWR, + BM(W1_5260_5320, W1_5180_5240,W1_5745_5825, -1, -1, -1, -1, -1), + BM(WBG1_2412_2412, WBG1_2437_2442, WBG1_2462_2462, WBG1_2472_2472, WBG1_2417_2432, WBG1_2447_2457, WBG1_2467_2467, -1)}, + + + {WOR9_WORLD, NO_CTL, 0, DFS_FCC3 | DFS_ETSI, ADHOC_NO_11A, 0, PSCAN_WWR, + BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1), + BM(WBG1_2412_2412, WBG1_2437_2442, WBG1_2462_2462, WBG1_2417_2432, WBG1_2447_2457, -1, -1, -1)}, + + {WORA_WORLD, NO_CTL, 0, DFS_FCC3 | DFS_ETSI, ADHOC_NO_11A, 0, PSCAN_WWR, + BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1), + BM(WBG1_2412_2412, WBG1_2437_2442, WBG1_2462_2462, WBG1_2472_2472, WBG1_2417_2432, WBG1_2447_2457, WBG1_2467_2467, -1)}, + + {NULL1, NO_CTL, 0, NO_DFS, NO_REQ, 0, NO_PSCAN, + BMZERO, + BMZERO} +}; + +#endif /* __AH_REG_TABLE_DATA_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/reg_dbschema.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/reg_dbschema.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/reg_dbschema.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/reg_dbschema.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,211 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2005 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __REG_DBSCHEMA_H__ +#define __REG_DBSCHEMA_H__ + +/* + * This file describes the regulatory DB schema, which is common between the + * 'generator' and 'parser'. The 'generator' runs on a host(typically a x86 + * Linux) and spits outs two binary files, which follow the DB file + * format(described below). The resultant output "regulatoryData_AG.bin" + * is binary file which has information regarding A and G regulatory + * information, while the "regulatoryData_G.bin" consists of G-ONLY regulatory + * information. This binary file is parsed in the target for extracting + * regulatory information. + * + * The DB values used to populate the regulatory DB are defined in + * reg_dbvalues.h + * + */ + +/* Binary data file - Representation of Regulatory DB*/ +#define REG_DATA_FILE_AG "./regulatoryData_AG.bin" +#define REG_DATA_FILE_G "./regulatoryData_G.bin" + + +/* Table tags used to encode different tables in the database */ +enum data_tags_t{ + REG_DMN_PAIR_MAPPING_TAG = 0, + REG_COUNTRY_CODE_TO_ENUM_RD_TAG, + REG_DMN_FREQ_BAND_regDmn5GhzFreq_TAG, + REG_DMN_FREQ_BAND_regDmn2Ghz11_BG_Freq_TAG, + REG_DOMAIN_TAG, + MAX_DB_TABLE_TAGS + }; + + + +/* + **************************************************************************** + * Regulatory DB file format : + * 4-bytes : "RGDB" (Magic Key) + * 4-bytes : version (Default is 5379(my extn)) + * 4-bytes : length of file + * dbType(4) + * TAG(4) + * Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data.... + * TAG(4) + * Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data.... + * TAG(4) + * Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data.... + * ... + * ... + **************************************************************************** + * + */ + +/* + * Length of the file would be filled in when the file is created and + * it would include the header size. + */ + +#define REG_DB_KEY "RGDB" /* Should be EXACTLY 4-bytes */ +#define REG_DB_VER 5379 /* Between 0-9999 */ + +#define MAGIC_KEY_OFFSET 0 +#define VERSION_OFFSET 4 +#define FILE_SZ_OFFSET 8 +#define DB_TYPE_OFFSET 12 + +#define MAGIC_KEY_SZ 4 +#define VERSION_SZ 4 +#define FILE_SZ_SZ 4 +#define DB_TYPE_SZ 4 +#define DB_TAG_SZ 4 + +#define REGDB_GET_MAGICKEY(x) ((char *)x + MAGIC_KEY_OFFSET) +#define REGDB_GET_VERSION(x) ((char *)x + VERSION_OFFSET) +#define REGDB_GET_FILESIZE(x) *((unsigned int *)((char *)x + FILE_SZ_OFFSET)) +#define REGDB_GET_DBTYPE(x) *((char *)x + DB_TYPE_OFFSET) + +#define REGDB_SET_FILESIZE(x, sz_) *((unsigned int *)((char *)x + FILE_SZ_OFFSET)) = (sz_) +#define REGDB_IS_EOF(cur, begin) ( REGDB_GET_FILESIZE(begin) > ((cur) - (begin)) ) + + +/* A Table can be search based on key as a parameter or accessed directly + * by giving its index in to the table. + */ +enum searchType { + KEY_BASED_TABLE_SEARCH = 1, + INDEX_BASED_TABLE_ACCESS + }; + + +/* Data is organised as different tables. There is a Master table, which + * holds information regarding all the tables. It does not have any + * knowledge about the attributes of the table it is holding + * but has external view of the same(for ex, how many entries, record size, + * how to search the table, total table size and reference to the data + * instance of table). + */ +typedef PREPACK struct dbMasterTable_t { /* Hold ptrs to Table data structures */ + A_UCHAR numOfEntries; /* NB: For AR6002_REV2, be aware of wreg_patch.c */ + A_CHAR entrySize; /* Entry size per table row */ + A_CHAR searchType; /* Index based access or key based */ + A_CHAR reserved[3]; /* for alignment */ + A_UINT16 tableSize; /* Size of this table */ + A_CHAR *dataPtr; /* Ptr to the actual Table */ +} POSTPACK dbMasterTable; /* Master table - table of tables */ + + +/* used to get the number of rows in a table */ +#define REGDB_NUM_OF_ROWS(a) (sizeof (a) / sizeof (a[0])) + +/* + * Used to set the RegDomain bitmask which chooses which frequency + * band specs are used. + */ + +#define BMLEN 2 /* Use 2 32-bit uint for channel bitmask */ +#define BMZERO {0,0} /* BMLEN zeros */ + +#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh) \ + {((((_fa >= 0) && (_fa < 32)) ? (((A_UINT32) 1) << _fa) : 0) | \ + (((_fb >= 0) && (_fb < 32)) ? (((A_UINT32) 1) << _fb) : 0) | \ + (((_fc >= 0) && (_fc < 32)) ? (((A_UINT32) 1) << _fc) : 0) | \ + (((_fd >= 0) && (_fd < 32)) ? (((A_UINT32) 1) << _fd) : 0) | \ + (((_fe >= 0) && (_fe < 32)) ? (((A_UINT32) 1) << _fe) : 0) | \ + (((_ff >= 0) && (_ff < 32)) ? (((A_UINT32) 1) << _ff) : 0) | \ + (((_fg >= 0) && (_fg < 32)) ? (((A_UINT32) 1) << _fg) : 0) | \ + (((_fh >= 0) && (_fh < 32)) ? (((A_UINT32) 1) << _fh) : 0)), \ + ((((_fa > 31) && (_fa < 64)) ? (((A_UINT32) 1) << (_fa - 32)) : 0) | \ + (((_fb > 31) && (_fb < 64)) ? (((A_UINT32) 1) << (_fb - 32)) : 0) | \ + (((_fc > 31) && (_fc < 64)) ? (((A_UINT32) 1) << (_fc - 32)) : 0) | \ + (((_fd > 31) && (_fd < 64)) ? (((A_UINT32) 1) << (_fd - 32)) : 0) | \ + (((_fe > 31) && (_fe < 64)) ? (((A_UINT32) 1) << (_fe - 32)) : 0) | \ + (((_ff > 31) && (_ff < 64)) ? (((A_UINT32) 1) << (_ff - 32)) : 0) | \ + (((_fg > 31) && (_fg < 64)) ? (((A_UINT32) 1) << (_fg - 32)) : 0) | \ + (((_fh > 31) && (_fh < 64)) ? (((A_UINT32) 1) << (_fh - 32)) : 0))} + + +/* + * THE following table is the mapping of regdomain pairs specified by + * a regdomain value to the individual unitary reg domains + */ + +typedef PREPACK struct reg_dmn_pair_mapping { + A_UINT16 regDmnEnum; /* 16 bit reg domain pair */ + A_UINT16 regDmn5GHz; /* 5GHz reg domain */ + A_UINT16 regDmn2GHz; /* 2GHz reg domain */ + A_UINT8 flags5GHz; /* Requirements flags (AdHoc disallow etc) */ + A_UINT8 flags2GHz; /* Requirements flags (AdHoc disallow etc) */ + A_UINT32 pscanMask; /* Passive Scan flags which can override unitary domain passive scan + flags. This value is used as a mask on the unitary flags*/ +} POSTPACK REG_DMN_PAIR_MAPPING; + +#define REGDB_YES 1 +#define REGDB_NO 0 + +typedef PREPACK struct { + A_UINT16 countryCode; + A_UINT16 regDmnEnum; + A_CHAR isoName[3]; + A_CHAR allow11g; +} POSTPACK COUNTRY_CODE_TO_ENUM_RD; + +typedef PREPACK struct RegDmnFreqBand { + A_UINT16 lowChannel; /* Low channel center in MHz */ + A_UINT16 highChannel; /* High Channel center in MHz */ + A_UINT8 power; /* Max power (dBm) for channel range */ + A_UINT8 channelSep; /* Channel separation within the band */ + A_UINT8 useDfs; /* Use DFS in the RegDomain if corresponding bit is set */ + A_UINT8 mode; /* Mode of operation */ + A_UINT32 usePassScan; /* Use Passive Scan in the RegDomain if corresponding bit is set */ +} POSTPACK REG_DMN_FREQ_BAND; + + + +typedef PREPACK struct regDomain { + A_UINT16 regDmnEnum; /* value from EnumRd table */ + A_UINT8 rdCTL; + A_UINT8 maxAntGain; + A_UINT8 dfsMask; /* DFS bitmask for 5Ghz tables */ + A_UINT8 flags; /* Requirement flags (AdHoc disallow etc) */ + A_UINT16 reserved; /* for alignment */ + A_UINT32 pscan; /* Bitmask for passive scan */ + A_UINT32 chan11a[BMLEN]; /* 64 bit bitmask for channel/band selection */ + A_UINT32 chan11bg[BMLEN];/* 64 bit bitmask for channel/band selection */ +} POSTPACK REG_DOMAIN; + +#endif /* __REG_DBSCHEMA_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/reg_dbvalues.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/reg_dbvalues.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/reg_dbvalues.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/reg_dbvalues.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,477 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2005 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + + +#ifndef __REG_DBVALUE_H__ +#define __REG_DBVALUE_H__ + +/* + * Numbering from ISO 3166 + */ +enum CountryCode { + CTRY_ALBANIA = 8, /* Albania */ + CTRY_ALGERIA = 12, /* Algeria */ + CTRY_ARGENTINA = 32, /* Argentina */ + CTRY_ARMENIA = 51, /* Armenia */ + CTRY_AUSTRALIA = 36, /* Australia */ + CTRY_AUSTRIA = 40, /* Austria */ + CTRY_AZERBAIJAN = 31, /* Azerbaijan */ + CTRY_BAHRAIN = 48, /* Bahrain */ + CTRY_BELARUS = 112, /* Belarus */ + CTRY_BELGIUM = 56, /* Belgium */ + CTRY_BELIZE = 84, /* Belize */ + CTRY_BOLIVIA = 68, /* Bolivia */ + CTRY_BOSNIA_HERZEGOWANIA = 70, /* Bosnia & Herzegowania */ + CTRY_BRAZIL = 76, /* Brazil */ + CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */ + CTRY_BULGARIA = 100, /* Bulgaria */ + CTRY_CANADA = 124, /* Canada */ + CTRY_CHILE = 152, /* Chile */ + CTRY_CHINA = 156, /* People's Republic of China */ + CTRY_COLOMBIA = 170, /* Colombia */ + CTRY_COSTA_RICA = 188, /* Costa Rica */ + CTRY_CROATIA = 191, /* Croatia */ + CTRY_CYPRUS = 196, + CTRY_CZECH = 203, /* Czech Republic */ + CTRY_DENMARK = 208, /* Denmark */ + CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */ + CTRY_ECUADOR = 218, /* Ecuador */ + CTRY_EGYPT = 818, /* Egypt */ + CTRY_EL_SALVADOR = 222, /* El Salvador */ + CTRY_ESTONIA = 233, /* Estonia */ + CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */ + CTRY_FINLAND = 246, /* Finland */ + CTRY_FRANCE = 250, /* France */ + CTRY_FRANCE2 = 255, /* France2 */ + CTRY_GEORGIA = 268, /* Georgia */ + CTRY_GERMANY = 276, /* Germany */ + CTRY_GREECE = 300, /* Greece */ + CTRY_GUATEMALA = 320, /* Guatemala */ + CTRY_HONDURAS = 340, /* Honduras */ + CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */ + CTRY_HUNGARY = 348, /* Hungary */ + CTRY_ICELAND = 352, /* Iceland */ + CTRY_INDIA = 356, /* India */ + CTRY_INDONESIA = 360, /* Indonesia */ + CTRY_IRAN = 364, /* Iran */ + CTRY_IRAQ = 368, /* Iraq */ + CTRY_IRELAND = 372, /* Ireland */ + CTRY_ISRAEL = 376, /* Israel */ + CTRY_ITALY = 380, /* Italy */ + CTRY_JAMAICA = 388, /* Jamaica */ + CTRY_JAPAN = 392, /* Japan */ + CTRY_JAPAN1 = 393, /* Japan (JP1) */ + CTRY_JAPAN2 = 394, /* Japan (JP0) */ + CTRY_JAPAN3 = 395, /* Japan (JP1-1) */ + CTRY_JAPAN4 = 396, /* Japan (JE1) */ + CTRY_JAPAN5 = 397, /* Japan (JE2) */ + CTRY_JAPAN6 = 399, /* Japan (JP6) */ + CTRY_JORDAN = 400, /* Jordan */ + CTRY_KAZAKHSTAN = 398, /* Kazakhstan */ + CTRY_KENYA = 404, /* Kenya */ + CTRY_KOREA_NORTH = 408, /* North Korea */ + CTRY_KOREA_ROC = 410, /* South Korea */ + CTRY_KOREA_ROC2 = 411, /* South Korea */ + CTRY_KOREA_ROC3 = 412, /* South Korea */ + CTRY_KUWAIT = 414, /* Kuwait */ + CTRY_LATVIA = 428, /* Latvia */ + CTRY_LEBANON = 422, /* Lebanon */ + CTRY_LIBYA = 434, /* Libya */ + CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */ + CTRY_LITHUANIA = 440, /* Lithuania */ + CTRY_LUXEMBOURG = 442, /* Luxembourg */ + CTRY_MACAU = 446, /* Macau */ + CTRY_MACEDONIA = 807, /* the Former Yugoslav Republic of Macedonia */ + CTRY_MALAYSIA = 458, /* Malaysia */ + CTRY_MALTA = 470, /* Malta */ + CTRY_MEXICO = 484, /* Mexico */ + CTRY_MONACO = 492, /* Principality of Monaco */ + CTRY_MOROCCO = 504, /* Morocco */ + CTRY_NETHERLANDS = 528, /* Netherlands */ + CTRY_NETHERLAND_ANTILLES = 530, /* Netherlands-Antilles */ + CTRY_NEW_ZEALAND = 554, /* New Zealand */ + CTRY_NICARAGUA = 558, /* Nicaragua */ + CTRY_NORWAY = 578, /* Norway */ + CTRY_OMAN = 512, /* Oman */ + CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */ + CTRY_PANAMA = 591, /* Panama */ + CTRY_PARAGUAY = 600, /* Paraguay */ + CTRY_PERU = 604, /* Peru */ + CTRY_PHILIPPINES = 608, /* Republic of the Philippines */ + CTRY_POLAND = 616, /* Poland */ + CTRY_PORTUGAL = 620, /* Portugal */ + CTRY_PUERTO_RICO = 630, /* Puerto Rico */ + CTRY_QATAR = 634, /* Qatar */ + CTRY_ROMANIA = 642, /* Romania */ + CTRY_RUSSIA = 643, /* Russia */ + CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */ + CTRY_MONTENEGRO = 891, /* Montenegro */ + CTRY_SINGAPORE = 702, /* Singapore */ + CTRY_SLOVAKIA = 703, /* Slovak Republic */ + CTRY_SLOVENIA = 705, /* Slovenia */ + CTRY_SOUTH_AFRICA = 710, /* South Africa */ + CTRY_SPAIN = 724, /* Spain */ + CTRY_SRILANKA = 144, /* Sri Lanka */ + CTRY_SWEDEN = 752, /* Sweden */ + CTRY_SWITZERLAND = 756, /* Switzerland */ + CTRY_SYRIA = 760, /* Syria */ + CTRY_TAIWAN = 158, /* Taiwan */ + CTRY_THAILAND = 764, /* Thailand */ + CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */ + CTRY_TUNISIA = 788, /* Tunisia */ + CTRY_TURKEY = 792, /* Turkey */ + CTRY_UAE = 784, /* U.A.E. */ + CTRY_UKRAINE = 804, /* Ukraine */ + CTRY_UNITED_KINGDOM = 826, /* United Kingdom */ + CTRY_UNITED_STATES = 840, /* United States */ + CTRY_UNITED_STATES_PS = 842, /* United States - public safety */ + CTRY_URUGUAY = 858, /* Uruguay */ + CTRY_UZBEKISTAN = 860, /* Uzbekistan */ + CTRY_VENEZUELA = 862, /* Venezuela */ + CTRY_VIET_NAM = 704, /* Viet Nam */ + CTRY_YEMEN = 887, /* Yemen */ + CTRY_ZIMBABWE = 716 /* Zimbabwe */ +}; + +#define CTRY_DEBUG 0 +#define CTRY_DEFAULT 0x1ff + +/* + * The following regulatory domain definitions are + * found in the EEPROM. Each regulatory domain + * can operate in either a 5GHz or 2.4GHz wireless mode or + * both 5GHz and 2.4GHz wireless modes. + * In general, the value holds no special + * meaning and is used to decode into either specific + * 2.4GHz or 5GHz wireless mode for that particular + * regulatory domain. + * + * Enumerated Regulatory Domain Information 8 bit values indicate that + * the regdomain is really a pair of unitary regdomains. 12 bit values + * are the real unitary regdomains and are the only ones which have the + * frequency bitmasks and flags set. + */ + +enum EnumRd { + NO_ENUMRD = 0x00, + NULL1_WORLD = 0x03, /* For 11b-only countries (no 11a allowed) */ + NULL1_ETSIB = 0x07, /* Israel */ + NULL1_ETSIC = 0x08, + + FCC1_FCCA = 0x10, /* USA */ + FCC1_WORLD = 0x11, /* Hong Kong */ + FCC2_FCCA = 0x20, /* Canada */ + FCC2_WORLD = 0x21, /* Australia & HK */ + FCC2_ETSIC = 0x22, + FCC3_FCCA = 0x3A, /* USA & Canada w/5470 band, 11h, DFS enabled */ + FCC3_WORLD = 0x3B, /* USA & Canada w/5470 band, 11h, DFS enabled */ + FCC4_FCCA = 0x12, /* FCC public safety plus UNII bands */ + FCC5_FCCA = 0x13, /* US with no DFS */ + + ETSI1_WORLD = 0x37, + + ETSI2_WORLD = 0x35, /* Hungary & others */ + ETSI3_WORLD = 0x36, /* France & others */ + ETSI4_WORLD = 0x30, + ETSI4_ETSIC = 0x38, + ETSI5_WORLD = 0x39, + ETSI6_WORLD = 0x34, /* Bulgaria */ + ETSI_RESERVED = 0x33, /* Reserved (Do not used) */ + FRANCE_RES = 0x31, /* Legacy France for OEM */ + + APL6_WORLD = 0x5B, /* Singapore */ + APL4_WORLD = 0x42, /* Singapore */ + APL3_FCCA = 0x50, + APL_RESERVED = 0x44, /* Reserved (Do not used) */ + APL2_WORLD = 0x45, /* Korea */ + APL2_APLC = 0x46, + APL3_WORLD = 0x47, + APL2_APLD = 0x49, /* Korea with 2.3G channels */ + APL1_WORLD = 0x52, /* Latin America */ + APL1_FCCA = 0x53, + APL1_ETSIC = 0x55, + APL2_ETSIC = 0x56, /* Venezuela */ + APL5_WORLD = 0x58, /* Chile */ + APL7_FCCA = 0x5C, + APL8_WORLD = 0x5D, + APL9_WORLD = 0x5E, + APL10_WORLD = 0x5F, + + MKK5_MKKA = 0x99, /* This is a temporary value. MG and DQ have to give official one */ + MKK5_FCCA = 0x9A, /* This is a temporary value. MG and DQ have to give official one */ + MKK5_MKKC = 0x88, + MKK11_MKKA = 0xD4, + MKK11_FCCA = 0xD5, + MKK11_MKKC = 0xD7, + + /* + * World mode SKUs + */ + WOR0_WORLD = 0x60, /* World0 (WO0 SKU) */ + WOR1_WORLD = 0x61, /* World1 (WO1 SKU) */ + WOR2_WORLD = 0x62, /* World2 (WO2 SKU) */ + WOR3_WORLD = 0x63, /* World3 (WO3 SKU) */ + WOR4_WORLD = 0x64, /* World4 (WO4 SKU) */ + WOR5_ETSIC = 0x65, /* World5 (WO5 SKU) */ + + WOR01_WORLD = 0x66, /* World0-1 (WW0-1 SKU) */ + WOR02_WORLD = 0x67, /* World0-2 (WW0-2 SKU) */ + EU1_WORLD = 0x68, /* Same as World0-2 (WW0-2 SKU), except active scan ch1-13. No ch14 */ + + WOR9_WORLD = 0x69, /* World9 (WO9 SKU) */ + WORA_WORLD = 0x6A, /* WorldA (WOA SKU) */ + + /* + * Regulator domains ending in a number (e.g. APL1, + * MK1, ETSI4, etc) apply to 5GHz channel and power + * information. Regulator domains ending in a letter + * (e.g. APLA, FCCA, etc) apply to 2.4GHz channel and + * power information. + */ + APL1 = 0x0150, /* LAT & Asia */ + APL2 = 0x0250, /* LAT & Asia */ + APL3 = 0x0350, /* Taiwan */ + APL4 = 0x0450, /* Jordan */ + APL5 = 0x0550, /* Chile */ + APL6 = 0x0650, /* Singapore */ + APL7 = 0x0750, /* Taiwan */ + APL8 = 0x0850, /* Malaysia */ + APL9 = 0x0950, /* Korea - Before 11/2007. Now used only by APs */ + APL10 = 0x1050, /* Korea ROC south - After 11/2007. For STAs only*/ + + ETSI1 = 0x0130, /* Europe & others */ + ETSI2 = 0x0230, /* Europe & others */ + ETSI3 = 0x0330, /* Europe & others */ + ETSI4 = 0x0430, /* Europe & others */ + ETSI5 = 0x0530, /* Europe & others */ + ETSI6 = 0x0630, /* Europe & others */ + ETSIB = 0x0B30, /* Israel */ + ETSIC = 0x0C30, /* Latin America */ + + FCC1 = 0x0110, /* US & others */ + FCC2 = 0x0120, /* Canada, Australia & New Zealand */ + FCC3 = 0x0160, /* US w/new middle band & DFS */ + FCC5 = 0x0180, + FCCA = 0x0A10, + + APLD = 0x0D50, /* South Korea */ + + MKK1 = 0x0140, /* Japan */ + MKK2 = 0x0240, /* Japan Extended */ + MKK3 = 0x0340, /* Japan new 5GHz */ + MKK4 = 0x0440, /* Japan new 5GHz */ + MKK5 = 0x0540, /* Japan new 5GHz */ + MKK6 = 0x0640, /* Japan new 5GHz */ + MKK7 = 0x0740, /* Japan new 5GHz */ + MKK8 = 0x0840, /* Japan new 5GHz */ + MKK9 = 0x0940, /* Japan new 5GHz */ + MKK10 = 0x1040, /* Japan new 5GHz */ + MKK11 = 0x1140, /* Japan new 5GHz */ + MKK12 = 0x1240, /* Japan new 5GHz */ + + MKKA = 0x0A40, /* Japan */ + MKKC = 0x0A50, + + NULL1 = 0x0198, + WORLD = 0x0199, + DEBUG_REG_DMN = 0x01ff, + UNINIT_REG_DMN = 0x0fff, +}; + +enum { /* conformance test limits */ + FCC = 0x10, + MKK = 0x40, + ETSI = 0x30, + NO_CTL = 0xff, + CTL_11B = 1, + CTL_11G = 2 +}; + + +/* + * The following are flags for different requirements per reg domain. + * These requirements are either inhereted from the reg domain pair or + * from the unitary reg domain if the reg domain pair flags value is + * 0 + */ + +enum { + NO_REQ = 0x00, + DISALLOW_ADHOC_11A = 0x01, + ADHOC_PER_11D = 0x02, + ADHOC_NO_11A = 0x04, + DISALLOW_ADHOC_11G = 0x08 +}; + + + + +/* + * The following describe the bit masks for different passive scan + * capability/requirements per regdomain. + */ +#define NO_PSCAN 0x00000000 +#define PSCAN_FCC 0x00000001 +#define PSCAN_ETSI 0x00000002 +#define PSCAN_MKK 0x00000004 +#define PSCAN_ETSIB 0x00000008 +#define PSCAN_ETSIC 0x00000010 +#define PSCAN_WWR 0x00000020 +#define PSCAN_DEFER 0xFFFFFFFF + +/* Bit masks for DFS per regdomain */ + +enum { + NO_DFS = 0x00, + DFS_FCC3 = 0x01, + DFS_ETSI = 0x02, + DFS_MKK = 0x04 +}; + + +#define DEF_REGDMN FCC1_FCCA + +/* + * The following table is the master list for all different freqeuncy + * bands with the complete matrix of all possible flags and settings + * for each band if it is used in ANY reg domain. + * + * The table of frequency bands is indexed by a bitmask. The ordering + * must be consistent with the enum below. When adding a new + * frequency band, be sure to match the location in the enum with the + * comments + */ + +/* + * These frequency values are as per channel tags and regulatory domain + * info. Please update them as database is updated. + */ +#define A_FREQ_MIN 4920 +#define A_FREQ_MAX 5825 + +#define A_CHAN0_FREQ 5000 +#define A_CHAN_MAX ((A_FREQ_MAX - A_CHAN0_FREQ)/5) + +#define BG_FREQ_MIN 2412 +#define BG_FREQ_MAX 2484 + +#define BG_CHAN0_FREQ 2407 +#define BG_CHAN_MIN ((BG_FREQ_MIN - BG_CHAN0_FREQ)/5) +#define BG_CHAN_MAX 14 /* corresponding to 2484 MHz */ + +#define A_20MHZ_BAND_FREQ_MAX 5000 + + +/* + * 5GHz 11A channel tags + */ + +enum { + F1_4920_4980, + F1_5040_5080, + + F1_5120_5240, + + F1_5180_5240, + F2_5180_5240, + F3_5180_5240, + F4_5180_5240, + F5_5180_5240, + F6_5180_5240, + + F1_5260_5280, + + F1_5260_5320, + F2_5260_5320, + F3_5260_5320, + F4_5260_5320, + + F1_5260_5700, + + F1_5280_5320, + + F1_5500_5620, + + F1_5500_5700, + F2_5500_5700, + F3_5500_5700, + F4_5500_5700, + F5_5500_5700, + + F1_5745_5805, + F2_5745_5805, + + F1_5745_5825, + F2_5745_5825, + F3_5745_5825, + F4_5745_5825, + F5_5745_5825, + + W1_4920_4980, + W1_5040_5080, + W1_5170_5230, + W1_5180_5240, + W1_5260_5320, + W1_5745_5825, + W1_5500_5700, +}; + + +/* 2.4 GHz table - for 11b and 11g info */ +enum { + BG1_2312_2372, + BG2_2312_2372, + + BG1_2412_2472, + BG2_2412_2472, + BG3_2412_2472, + + BG1_2412_2462, + BG2_2412_2462, + + BG1_2432_2442, + + BG1_2457_2472, + + BG1_2467_2472, + + BG1_2484_2484, /* No G */ + BG2_2484_2484, /* No G */ + + BG1_2512_2732, + + WBG1_2312_2372, + WBG1_2412_2412, + WBG1_2417_2432, + WBG1_2437_2442, + WBG1_2447_2457, + WBG1_2462_2462, + WBG1_2467_2467, + WBG2_2467_2467, + WBG1_2472_2472, + WBG2_2472_2472, + WBG1_2484_2484, /* No G */ + WBG2_2484_2484 /* No G */ +}; + +#endif /* __REG_DBVALUE_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/regdump.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/regdump.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/regdump.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/regdump.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,49 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __REGDUMP_H__ +#define __REGDUMP_H__ +#if defined(AR6001) +#include "AR6001_regdump.h" +#endif +#if defined(AR6002) +#include "AR6002_regdump.h" +#endif + +#if !defined(__ASSEMBLER__) +/* + * Target CPU state at the time of failure is reflected + * in a register dump, which the Host can fetch through + * the diagnostic window. + */ +struct register_dump_s { + A_UINT32 target_id; /* Target ID */ + A_UINT32 assline; /* Line number (if assertion failure) */ + A_UINT32 pc; /* Program Counter at time of exception */ + A_UINT32 badvaddr; /* Virtual address causing exception */ + CPU_exception_frame_t exc_frame; /* CPU-specific exception info */ + + /* Could copy top of stack here, too.... */ +}; +#endif /* __ASSEMBLER__ */ +#endif /* __REGDUMP_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/roaming.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/roaming.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/roaming.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/roaming.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,41 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _ROAMING_H_ +#define _ROAMING_H_ + +/* + * The signal quality could be in terms of either snr or rssi. We should + * have an enum for both of them. For the time being, we are going to move + * it to wmi.h that is shared by both host and the target, since we are + * repartitioning the code to the host + */ +#define SIGNAL_QUALITY_NOISE_FLOOR -96 +#define SIGNAL_QUALITY_METRICS_NUM_MAX 2 +typedef enum { + SIGNAL_QUALITY_METRICS_SNR = 0, + SIGNAL_QUALITY_METRICS_RSSI, + SIGNAL_QUALITY_METRICS_ALL, +} SIGNAL_QUALITY_METRICS_TYPE; + +#endif /* _ROAMING_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/rtc_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/rtc_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/rtc_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/rtc_reg.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,1186 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _RTC_REG_REG_H_ +#define _RTC_REG_REG_H_ + +#define RESET_CONTROL_ADDRESS 0x00000000 +#define RESET_CONTROL_OFFSET 0x00000000 +#define RESET_CONTROL_CPU_INIT_RESET_MSB 11 +#define RESET_CONTROL_CPU_INIT_RESET_LSB 11 +#define RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800 +#define RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & RESET_CONTROL_CPU_INIT_RESET_MASK) >> RESET_CONTROL_CPU_INIT_RESET_LSB) +#define RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << RESET_CONTROL_CPU_INIT_RESET_LSB) & RESET_CONTROL_CPU_INIT_RESET_MASK) +#define RESET_CONTROL_VMC_REMAP_RESET_MSB 10 +#define RESET_CONTROL_VMC_REMAP_RESET_LSB 10 +#define RESET_CONTROL_VMC_REMAP_RESET_MASK 0x00000400 +#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) (((x) & RESET_CONTROL_VMC_REMAP_RESET_MASK) >> RESET_CONTROL_VMC_REMAP_RESET_LSB) +#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) (((x) << RESET_CONTROL_VMC_REMAP_RESET_LSB) & RESET_CONTROL_VMC_REMAP_RESET_MASK) +#define RESET_CONTROL_RST_OUT_MSB 9 +#define RESET_CONTROL_RST_OUT_LSB 9 +#define RESET_CONTROL_RST_OUT_MASK 0x00000200 +#define RESET_CONTROL_RST_OUT_GET(x) (((x) & RESET_CONTROL_RST_OUT_MASK) >> RESET_CONTROL_RST_OUT_LSB) +#define RESET_CONTROL_RST_OUT_SET(x) (((x) << RESET_CONTROL_RST_OUT_LSB) & RESET_CONTROL_RST_OUT_MASK) +#define RESET_CONTROL_COLD_RST_MSB 8 +#define RESET_CONTROL_COLD_RST_LSB 8 +#define RESET_CONTROL_COLD_RST_MASK 0x00000100 +#define RESET_CONTROL_COLD_RST_GET(x) (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB) +#define RESET_CONTROL_COLD_RST_SET(x) (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK) +#define RESET_CONTROL_WARM_RST_MSB 7 +#define RESET_CONTROL_WARM_RST_LSB 7 +#define RESET_CONTROL_WARM_RST_MASK 0x00000080 +#define RESET_CONTROL_WARM_RST_GET(x) (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB) +#define RESET_CONTROL_WARM_RST_SET(x) (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK) +#define RESET_CONTROL_CPU_WARM_RST_MSB 6 +#define RESET_CONTROL_CPU_WARM_RST_LSB 6 +#define RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 +#define RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & RESET_CONTROL_CPU_WARM_RST_MASK) >> RESET_CONTROL_CPU_WARM_RST_LSB) +#define RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << RESET_CONTROL_CPU_WARM_RST_LSB) & RESET_CONTROL_CPU_WARM_RST_MASK) +#define RESET_CONTROL_MAC_COLD_RST_MSB 5 +#define RESET_CONTROL_MAC_COLD_RST_LSB 5 +#define RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020 +#define RESET_CONTROL_MAC_COLD_RST_GET(x) (((x) & RESET_CONTROL_MAC_COLD_RST_MASK) >> RESET_CONTROL_MAC_COLD_RST_LSB) +#define RESET_CONTROL_MAC_COLD_RST_SET(x) (((x) << RESET_CONTROL_MAC_COLD_RST_LSB) & RESET_CONTROL_MAC_COLD_RST_MASK) +#define RESET_CONTROL_MAC_WARM_RST_MSB 4 +#define RESET_CONTROL_MAC_WARM_RST_LSB 4 +#define RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010 +#define RESET_CONTROL_MAC_WARM_RST_GET(x) (((x) & RESET_CONTROL_MAC_WARM_RST_MASK) >> RESET_CONTROL_MAC_WARM_RST_LSB) +#define RESET_CONTROL_MAC_WARM_RST_SET(x) (((x) << RESET_CONTROL_MAC_WARM_RST_LSB) & RESET_CONTROL_MAC_WARM_RST_MASK) +#define RESET_CONTROL_MBOX_RST_MSB 2 +#define RESET_CONTROL_MBOX_RST_LSB 2 +#define RESET_CONTROL_MBOX_RST_MASK 0x00000004 +#define RESET_CONTROL_MBOX_RST_GET(x) (((x) & RESET_CONTROL_MBOX_RST_MASK) >> RESET_CONTROL_MBOX_RST_LSB) +#define RESET_CONTROL_MBOX_RST_SET(x) (((x) << RESET_CONTROL_MBOX_RST_LSB) & RESET_CONTROL_MBOX_RST_MASK) +#define RESET_CONTROL_UART_RST_MSB 1 +#define RESET_CONTROL_UART_RST_LSB 1 +#define RESET_CONTROL_UART_RST_MASK 0x00000002 +#define RESET_CONTROL_UART_RST_GET(x) (((x) & RESET_CONTROL_UART_RST_MASK) >> RESET_CONTROL_UART_RST_LSB) +#define RESET_CONTROL_UART_RST_SET(x) (((x) << RESET_CONTROL_UART_RST_LSB) & RESET_CONTROL_UART_RST_MASK) +#define RESET_CONTROL_SI0_RST_MSB 0 +#define RESET_CONTROL_SI0_RST_LSB 0 +#define RESET_CONTROL_SI0_RST_MASK 0x00000001 +#define RESET_CONTROL_SI0_RST_GET(x) (((x) & RESET_CONTROL_SI0_RST_MASK) >> RESET_CONTROL_SI0_RST_LSB) +#define RESET_CONTROL_SI0_RST_SET(x) (((x) << RESET_CONTROL_SI0_RST_LSB) & RESET_CONTROL_SI0_RST_MASK) + +#define XTAL_CONTROL_ADDRESS 0x00000004 +#define XTAL_CONTROL_OFFSET 0x00000004 +#define XTAL_CONTROL_TCXO_MSB 0 +#define XTAL_CONTROL_TCXO_LSB 0 +#define XTAL_CONTROL_TCXO_MASK 0x00000001 +#define XTAL_CONTROL_TCXO_GET(x) (((x) & XTAL_CONTROL_TCXO_MASK) >> XTAL_CONTROL_TCXO_LSB) +#define XTAL_CONTROL_TCXO_SET(x) (((x) << XTAL_CONTROL_TCXO_LSB) & XTAL_CONTROL_TCXO_MASK) + +#define TCXO_DETECT_ADDRESS 0x00000008 +#define TCXO_DETECT_OFFSET 0x00000008 +#define TCXO_DETECT_PRESENT_MSB 0 +#define TCXO_DETECT_PRESENT_LSB 0 +#define TCXO_DETECT_PRESENT_MASK 0x00000001 +#define TCXO_DETECT_PRESENT_GET(x) (((x) & TCXO_DETECT_PRESENT_MASK) >> TCXO_DETECT_PRESENT_LSB) +#define TCXO_DETECT_PRESENT_SET(x) (((x) << TCXO_DETECT_PRESENT_LSB) & TCXO_DETECT_PRESENT_MASK) + +#define XTAL_TEST_ADDRESS 0x0000000c +#define XTAL_TEST_OFFSET 0x0000000c +#define XTAL_TEST_NOTCXODET_MSB 0 +#define XTAL_TEST_NOTCXODET_LSB 0 +#define XTAL_TEST_NOTCXODET_MASK 0x00000001 +#define XTAL_TEST_NOTCXODET_GET(x) (((x) & XTAL_TEST_NOTCXODET_MASK) >> XTAL_TEST_NOTCXODET_LSB) +#define XTAL_TEST_NOTCXODET_SET(x) (((x) << XTAL_TEST_NOTCXODET_LSB) & XTAL_TEST_NOTCXODET_MASK) + +#define QUADRATURE_ADDRESS 0x00000010 +#define QUADRATURE_OFFSET 0x00000010 +#define QUADRATURE_ADC_MSB 5 +#define QUADRATURE_ADC_LSB 4 +#define QUADRATURE_ADC_MASK 0x00000030 +#define QUADRATURE_ADC_GET(x) (((x) & QUADRATURE_ADC_MASK) >> QUADRATURE_ADC_LSB) +#define QUADRATURE_ADC_SET(x) (((x) << QUADRATURE_ADC_LSB) & QUADRATURE_ADC_MASK) +#define QUADRATURE_SEL_MSB 2 +#define QUADRATURE_SEL_LSB 2 +#define QUADRATURE_SEL_MASK 0x00000004 +#define QUADRATURE_SEL_GET(x) (((x) & QUADRATURE_SEL_MASK) >> QUADRATURE_SEL_LSB) +#define QUADRATURE_SEL_SET(x) (((x) << QUADRATURE_SEL_LSB) & QUADRATURE_SEL_MASK) +#define QUADRATURE_DAC_MSB 1 +#define QUADRATURE_DAC_LSB 0 +#define QUADRATURE_DAC_MASK 0x00000003 +#define QUADRATURE_DAC_GET(x) (((x) & QUADRATURE_DAC_MASK) >> QUADRATURE_DAC_LSB) +#define QUADRATURE_DAC_SET(x) (((x) << QUADRATURE_DAC_LSB) & QUADRATURE_DAC_MASK) + +#define PLL_CONTROL_ADDRESS 0x00000014 +#define PLL_CONTROL_OFFSET 0x00000014 +#define PLL_CONTROL_DIG_TEST_CLK_MSB 20 +#define PLL_CONTROL_DIG_TEST_CLK_LSB 20 +#define PLL_CONTROL_DIG_TEST_CLK_MASK 0x00100000 +#define PLL_CONTROL_DIG_TEST_CLK_GET(x) (((x) & PLL_CONTROL_DIG_TEST_CLK_MASK) >> PLL_CONTROL_DIG_TEST_CLK_LSB) +#define PLL_CONTROL_DIG_TEST_CLK_SET(x) (((x) << PLL_CONTROL_DIG_TEST_CLK_LSB) & PLL_CONTROL_DIG_TEST_CLK_MASK) +#define PLL_CONTROL_MAC_OVERRIDE_MSB 19 +#define PLL_CONTROL_MAC_OVERRIDE_LSB 19 +#define PLL_CONTROL_MAC_OVERRIDE_MASK 0x00080000 +#define PLL_CONTROL_MAC_OVERRIDE_GET(x) (((x) & PLL_CONTROL_MAC_OVERRIDE_MASK) >> PLL_CONTROL_MAC_OVERRIDE_LSB) +#define PLL_CONTROL_MAC_OVERRIDE_SET(x) (((x) << PLL_CONTROL_MAC_OVERRIDE_LSB) & PLL_CONTROL_MAC_OVERRIDE_MASK) +#define PLL_CONTROL_NOPWD_MSB 18 +#define PLL_CONTROL_NOPWD_LSB 18 +#define PLL_CONTROL_NOPWD_MASK 0x00040000 +#define PLL_CONTROL_NOPWD_GET(x) (((x) & PLL_CONTROL_NOPWD_MASK) >> PLL_CONTROL_NOPWD_LSB) +#define PLL_CONTROL_NOPWD_SET(x) (((x) << PLL_CONTROL_NOPWD_LSB) & PLL_CONTROL_NOPWD_MASK) +#define PLL_CONTROL_UPDATING_MSB 17 +#define PLL_CONTROL_UPDATING_LSB 17 +#define PLL_CONTROL_UPDATING_MASK 0x00020000 +#define PLL_CONTROL_UPDATING_GET(x) (((x) & PLL_CONTROL_UPDATING_MASK) >> PLL_CONTROL_UPDATING_LSB) +#define PLL_CONTROL_UPDATING_SET(x) (((x) << PLL_CONTROL_UPDATING_LSB) & PLL_CONTROL_UPDATING_MASK) +#define PLL_CONTROL_BYPASS_MSB 16 +#define PLL_CONTROL_BYPASS_LSB 16 +#define PLL_CONTROL_BYPASS_MASK 0x00010000 +#define PLL_CONTROL_BYPASS_GET(x) (((x) & PLL_CONTROL_BYPASS_MASK) >> PLL_CONTROL_BYPASS_LSB) +#define PLL_CONTROL_BYPASS_SET(x) (((x) << PLL_CONTROL_BYPASS_LSB) & PLL_CONTROL_BYPASS_MASK) +#define PLL_CONTROL_REFDIV_MSB 15 +#define PLL_CONTROL_REFDIV_LSB 12 +#define PLL_CONTROL_REFDIV_MASK 0x0000f000 +#define PLL_CONTROL_REFDIV_GET(x) (((x) & PLL_CONTROL_REFDIV_MASK) >> PLL_CONTROL_REFDIV_LSB) +#define PLL_CONTROL_REFDIV_SET(x) (((x) << PLL_CONTROL_REFDIV_LSB) & PLL_CONTROL_REFDIV_MASK) +#define PLL_CONTROL_DIV_MSB 9 +#define PLL_CONTROL_DIV_LSB 0 +#define PLL_CONTROL_DIV_MASK 0x000003ff +#define PLL_CONTROL_DIV_GET(x) (((x) & PLL_CONTROL_DIV_MASK) >> PLL_CONTROL_DIV_LSB) +#define PLL_CONTROL_DIV_SET(x) (((x) << PLL_CONTROL_DIV_LSB) & PLL_CONTROL_DIV_MASK) + +#define PLL_SETTLE_ADDRESS 0x00000018 +#define PLL_SETTLE_OFFSET 0x00000018 +#define PLL_SETTLE_TIME_MSB 11 +#define PLL_SETTLE_TIME_LSB 0 +#define PLL_SETTLE_TIME_MASK 0x00000fff +#define PLL_SETTLE_TIME_GET(x) (((x) & PLL_SETTLE_TIME_MASK) >> PLL_SETTLE_TIME_LSB) +#define PLL_SETTLE_TIME_SET(x) (((x) << PLL_SETTLE_TIME_LSB) & PLL_SETTLE_TIME_MASK) + +#define XTAL_SETTLE_ADDRESS 0x0000001c +#define XTAL_SETTLE_OFFSET 0x0000001c +#define XTAL_SETTLE_TIME_MSB 7 +#define XTAL_SETTLE_TIME_LSB 0 +#define XTAL_SETTLE_TIME_MASK 0x000000ff +#define XTAL_SETTLE_TIME_GET(x) (((x) & XTAL_SETTLE_TIME_MASK) >> XTAL_SETTLE_TIME_LSB) +#define XTAL_SETTLE_TIME_SET(x) (((x) << XTAL_SETTLE_TIME_LSB) & XTAL_SETTLE_TIME_MASK) + +#define CPU_CLOCK_ADDRESS 0x00000020 +#define CPU_CLOCK_OFFSET 0x00000020 +#define CPU_CLOCK_STANDARD_MSB 1 +#define CPU_CLOCK_STANDARD_LSB 0 +#define CPU_CLOCK_STANDARD_MASK 0x00000003 +#define CPU_CLOCK_STANDARD_GET(x) (((x) & CPU_CLOCK_STANDARD_MASK) >> CPU_CLOCK_STANDARD_LSB) +#define CPU_CLOCK_STANDARD_SET(x) (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK) + +#define CLOCK_OUT_ADDRESS 0x00000024 +#define CLOCK_OUT_OFFSET 0x00000024 +#define CLOCK_OUT_SELECT_MSB 3 +#define CLOCK_OUT_SELECT_LSB 0 +#define CLOCK_OUT_SELECT_MASK 0x0000000f +#define CLOCK_OUT_SELECT_GET(x) (((x) & CLOCK_OUT_SELECT_MASK) >> CLOCK_OUT_SELECT_LSB) +#define CLOCK_OUT_SELECT_SET(x) (((x) << CLOCK_OUT_SELECT_LSB) & CLOCK_OUT_SELECT_MASK) + +#define CLOCK_CONTROL_ADDRESS 0x00000028 +#define CLOCK_CONTROL_OFFSET 0x00000028 +#define CLOCK_CONTROL_LF_CLK32_MSB 2 +#define CLOCK_CONTROL_LF_CLK32_LSB 2 +#define CLOCK_CONTROL_LF_CLK32_MASK 0x00000004 +#define CLOCK_CONTROL_LF_CLK32_GET(x) (((x) & CLOCK_CONTROL_LF_CLK32_MASK) >> CLOCK_CONTROL_LF_CLK32_LSB) +#define CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << CLOCK_CONTROL_LF_CLK32_LSB) & CLOCK_CONTROL_LF_CLK32_MASK) +#define CLOCK_CONTROL_UART_CLK_MSB 1 +#define CLOCK_CONTROL_UART_CLK_LSB 1 +#define CLOCK_CONTROL_UART_CLK_MASK 0x00000002 +#define CLOCK_CONTROL_UART_CLK_GET(x) (((x) & CLOCK_CONTROL_UART_CLK_MASK) >> CLOCK_CONTROL_UART_CLK_LSB) +#define CLOCK_CONTROL_UART_CLK_SET(x) (((x) << CLOCK_CONTROL_UART_CLK_LSB) & CLOCK_CONTROL_UART_CLK_MASK) +#define CLOCK_CONTROL_SI0_CLK_MSB 0 +#define CLOCK_CONTROL_SI0_CLK_LSB 0 +#define CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 +#define CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & CLOCK_CONTROL_SI0_CLK_MASK) >> CLOCK_CONTROL_SI0_CLK_LSB) +#define CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << CLOCK_CONTROL_SI0_CLK_LSB) & CLOCK_CONTROL_SI0_CLK_MASK) + +#define BIAS_OVERRIDE_ADDRESS 0x0000002c +#define BIAS_OVERRIDE_OFFSET 0x0000002c +#define BIAS_OVERRIDE_ON_MSB 0 +#define BIAS_OVERRIDE_ON_LSB 0 +#define BIAS_OVERRIDE_ON_MASK 0x00000001 +#define BIAS_OVERRIDE_ON_GET(x) (((x) & BIAS_OVERRIDE_ON_MASK) >> BIAS_OVERRIDE_ON_LSB) +#define BIAS_OVERRIDE_ON_SET(x) (((x) << BIAS_OVERRIDE_ON_LSB) & BIAS_OVERRIDE_ON_MASK) + +#define WDT_CONTROL_ADDRESS 0x00000030 +#define WDT_CONTROL_OFFSET 0x00000030 +#define WDT_CONTROL_ACTION_MSB 2 +#define WDT_CONTROL_ACTION_LSB 0 +#define WDT_CONTROL_ACTION_MASK 0x00000007 +#define WDT_CONTROL_ACTION_GET(x) (((x) & WDT_CONTROL_ACTION_MASK) >> WDT_CONTROL_ACTION_LSB) +#define WDT_CONTROL_ACTION_SET(x) (((x) << WDT_CONTROL_ACTION_LSB) & WDT_CONTROL_ACTION_MASK) + +#define WDT_STATUS_ADDRESS 0x00000034 +#define WDT_STATUS_OFFSET 0x00000034 +#define WDT_STATUS_INTERRUPT_MSB 0 +#define WDT_STATUS_INTERRUPT_LSB 0 +#define WDT_STATUS_INTERRUPT_MASK 0x00000001 +#define WDT_STATUS_INTERRUPT_GET(x) (((x) & WDT_STATUS_INTERRUPT_MASK) >> WDT_STATUS_INTERRUPT_LSB) +#define WDT_STATUS_INTERRUPT_SET(x) (((x) << WDT_STATUS_INTERRUPT_LSB) & WDT_STATUS_INTERRUPT_MASK) + +#define WDT_ADDRESS 0x00000038 +#define WDT_OFFSET 0x00000038 +#define WDT_TARGET_MSB 21 +#define WDT_TARGET_LSB 0 +#define WDT_TARGET_MASK 0x003fffff +#define WDT_TARGET_GET(x) (((x) & WDT_TARGET_MASK) >> WDT_TARGET_LSB) +#define WDT_TARGET_SET(x) (((x) << WDT_TARGET_LSB) & WDT_TARGET_MASK) + +#define WDT_COUNT_ADDRESS 0x0000003c +#define WDT_COUNT_OFFSET 0x0000003c +#define WDT_COUNT_VALUE_MSB 21 +#define WDT_COUNT_VALUE_LSB 0 +#define WDT_COUNT_VALUE_MASK 0x003fffff +#define WDT_COUNT_VALUE_GET(x) (((x) & WDT_COUNT_VALUE_MASK) >> WDT_COUNT_VALUE_LSB) +#define WDT_COUNT_VALUE_SET(x) (((x) << WDT_COUNT_VALUE_LSB) & WDT_COUNT_VALUE_MASK) + +#define WDT_RESET_ADDRESS 0x00000040 +#define WDT_RESET_OFFSET 0x00000040 +#define WDT_RESET_VALUE_MSB 0 +#define WDT_RESET_VALUE_LSB 0 +#define WDT_RESET_VALUE_MASK 0x00000001 +#define WDT_RESET_VALUE_GET(x) (((x) & WDT_RESET_VALUE_MASK) >> WDT_RESET_VALUE_LSB) +#define WDT_RESET_VALUE_SET(x) (((x) << WDT_RESET_VALUE_LSB) & WDT_RESET_VALUE_MASK) + +#define INT_STATUS_ADDRESS 0x00000044 +#define INT_STATUS_OFFSET 0x00000044 +#define INT_STATUS_RTC_POWER_MSB 14 +#define INT_STATUS_RTC_POWER_LSB 14 +#define INT_STATUS_RTC_POWER_MASK 0x00004000 +#define INT_STATUS_RTC_POWER_GET(x) (((x) & INT_STATUS_RTC_POWER_MASK) >> INT_STATUS_RTC_POWER_LSB) +#define INT_STATUS_RTC_POWER_SET(x) (((x) << INT_STATUS_RTC_POWER_LSB) & INT_STATUS_RTC_POWER_MASK) +#define INT_STATUS_MAC_MSB 13 +#define INT_STATUS_MAC_LSB 13 +#define INT_STATUS_MAC_MASK 0x00002000 +#define INT_STATUS_MAC_GET(x) (((x) & INT_STATUS_MAC_MASK) >> INT_STATUS_MAC_LSB) +#define INT_STATUS_MAC_SET(x) (((x) << INT_STATUS_MAC_LSB) & INT_STATUS_MAC_MASK) +#define INT_STATUS_MAILBOX_MSB 12 +#define INT_STATUS_MAILBOX_LSB 12 +#define INT_STATUS_MAILBOX_MASK 0x00001000 +#define INT_STATUS_MAILBOX_GET(x) (((x) & INT_STATUS_MAILBOX_MASK) >> INT_STATUS_MAILBOX_LSB) +#define INT_STATUS_MAILBOX_SET(x) (((x) << INT_STATUS_MAILBOX_LSB) & INT_STATUS_MAILBOX_MASK) +#define INT_STATUS_RTC_ALARM_MSB 11 +#define INT_STATUS_RTC_ALARM_LSB 11 +#define INT_STATUS_RTC_ALARM_MASK 0x00000800 +#define INT_STATUS_RTC_ALARM_GET(x) (((x) & INT_STATUS_RTC_ALARM_MASK) >> INT_STATUS_RTC_ALARM_LSB) +#define INT_STATUS_RTC_ALARM_SET(x) (((x) << INT_STATUS_RTC_ALARM_LSB) & INT_STATUS_RTC_ALARM_MASK) +#define INT_STATUS_HF_TIMER_MSB 10 +#define INT_STATUS_HF_TIMER_LSB 10 +#define INT_STATUS_HF_TIMER_MASK 0x00000400 +#define INT_STATUS_HF_TIMER_GET(x) (((x) & INT_STATUS_HF_TIMER_MASK) >> INT_STATUS_HF_TIMER_LSB) +#define INT_STATUS_HF_TIMER_SET(x) (((x) << INT_STATUS_HF_TIMER_LSB) & INT_STATUS_HF_TIMER_MASK) +#define INT_STATUS_LF_TIMER3_MSB 9 +#define INT_STATUS_LF_TIMER3_LSB 9 +#define INT_STATUS_LF_TIMER3_MASK 0x00000200 +#define INT_STATUS_LF_TIMER3_GET(x) (((x) & INT_STATUS_LF_TIMER3_MASK) >> INT_STATUS_LF_TIMER3_LSB) +#define INT_STATUS_LF_TIMER3_SET(x) (((x) << INT_STATUS_LF_TIMER3_LSB) & INT_STATUS_LF_TIMER3_MASK) +#define INT_STATUS_LF_TIMER2_MSB 8 +#define INT_STATUS_LF_TIMER2_LSB 8 +#define INT_STATUS_LF_TIMER2_MASK 0x00000100 +#define INT_STATUS_LF_TIMER2_GET(x) (((x) & INT_STATUS_LF_TIMER2_MASK) >> INT_STATUS_LF_TIMER2_LSB) +#define INT_STATUS_LF_TIMER2_SET(x) (((x) << INT_STATUS_LF_TIMER2_LSB) & INT_STATUS_LF_TIMER2_MASK) +#define INT_STATUS_LF_TIMER1_MSB 7 +#define INT_STATUS_LF_TIMER1_LSB 7 +#define INT_STATUS_LF_TIMER1_MASK 0x00000080 +#define INT_STATUS_LF_TIMER1_GET(x) (((x) & INT_STATUS_LF_TIMER1_MASK) >> INT_STATUS_LF_TIMER1_LSB) +#define INT_STATUS_LF_TIMER1_SET(x) (((x) << INT_STATUS_LF_TIMER1_LSB) & INT_STATUS_LF_TIMER1_MASK) +#define INT_STATUS_LF_TIMER0_MSB 6 +#define INT_STATUS_LF_TIMER0_LSB 6 +#define INT_STATUS_LF_TIMER0_MASK 0x00000040 +#define INT_STATUS_LF_TIMER0_GET(x) (((x) & INT_STATUS_LF_TIMER0_MASK) >> INT_STATUS_LF_TIMER0_LSB) +#define INT_STATUS_LF_TIMER0_SET(x) (((x) << INT_STATUS_LF_TIMER0_LSB) & INT_STATUS_LF_TIMER0_MASK) +#define INT_STATUS_KEYPAD_MSB 5 +#define INT_STATUS_KEYPAD_LSB 5 +#define INT_STATUS_KEYPAD_MASK 0x00000020 +#define INT_STATUS_KEYPAD_GET(x) (((x) & INT_STATUS_KEYPAD_MASK) >> INT_STATUS_KEYPAD_LSB) +#define INT_STATUS_KEYPAD_SET(x) (((x) << INT_STATUS_KEYPAD_LSB) & INT_STATUS_KEYPAD_MASK) +#define INT_STATUS_SI_MSB 4 +#define INT_STATUS_SI_LSB 4 +#define INT_STATUS_SI_MASK 0x00000010 +#define INT_STATUS_SI_GET(x) (((x) & INT_STATUS_SI_MASK) >> INT_STATUS_SI_LSB) +#define INT_STATUS_SI_SET(x) (((x) << INT_STATUS_SI_LSB) & INT_STATUS_SI_MASK) +#define INT_STATUS_GPIO_MSB 3 +#define INT_STATUS_GPIO_LSB 3 +#define INT_STATUS_GPIO_MASK 0x00000008 +#define INT_STATUS_GPIO_GET(x) (((x) & INT_STATUS_GPIO_MASK) >> INT_STATUS_GPIO_LSB) +#define INT_STATUS_GPIO_SET(x) (((x) << INT_STATUS_GPIO_LSB) & INT_STATUS_GPIO_MASK) +#define INT_STATUS_UART_MSB 2 +#define INT_STATUS_UART_LSB 2 +#define INT_STATUS_UART_MASK 0x00000004 +#define INT_STATUS_UART_GET(x) (((x) & INT_STATUS_UART_MASK) >> INT_STATUS_UART_LSB) +#define INT_STATUS_UART_SET(x) (((x) << INT_STATUS_UART_LSB) & INT_STATUS_UART_MASK) +#define INT_STATUS_ERROR_MSB 1 +#define INT_STATUS_ERROR_LSB 1 +#define INT_STATUS_ERROR_MASK 0x00000002 +#define INT_STATUS_ERROR_GET(x) (((x) & INT_STATUS_ERROR_MASK) >> INT_STATUS_ERROR_LSB) +#define INT_STATUS_ERROR_SET(x) (((x) << INT_STATUS_ERROR_LSB) & INT_STATUS_ERROR_MASK) +#define INT_STATUS_WDT_INT_MSB 0 +#define INT_STATUS_WDT_INT_LSB 0 +#define INT_STATUS_WDT_INT_MASK 0x00000001 +#define INT_STATUS_WDT_INT_GET(x) (((x) & INT_STATUS_WDT_INT_MASK) >> INT_STATUS_WDT_INT_LSB) +#define INT_STATUS_WDT_INT_SET(x) (((x) << INT_STATUS_WDT_INT_LSB) & INT_STATUS_WDT_INT_MASK) + +#define LF_TIMER0_ADDRESS 0x00000048 +#define LF_TIMER0_OFFSET 0x00000048 +#define LF_TIMER0_TARGET_MSB 31 +#define LF_TIMER0_TARGET_LSB 0 +#define LF_TIMER0_TARGET_MASK 0xffffffff +#define LF_TIMER0_TARGET_GET(x) (((x) & LF_TIMER0_TARGET_MASK) >> LF_TIMER0_TARGET_LSB) +#define LF_TIMER0_TARGET_SET(x) (((x) << LF_TIMER0_TARGET_LSB) & LF_TIMER0_TARGET_MASK) + +#define LF_TIMER_COUNT0_ADDRESS 0x0000004c +#define LF_TIMER_COUNT0_OFFSET 0x0000004c +#define LF_TIMER_COUNT0_VALUE_MSB 31 +#define LF_TIMER_COUNT0_VALUE_LSB 0 +#define LF_TIMER_COUNT0_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT0_VALUE_GET(x) (((x) & LF_TIMER_COUNT0_VALUE_MASK) >> LF_TIMER_COUNT0_VALUE_LSB) +#define LF_TIMER_COUNT0_VALUE_SET(x) (((x) << LF_TIMER_COUNT0_VALUE_LSB) & LF_TIMER_COUNT0_VALUE_MASK) + +#define LF_TIMER_CONTROL0_ADDRESS 0x00000050 +#define LF_TIMER_CONTROL0_OFFSET 0x00000050 +#define LF_TIMER_CONTROL0_ENABLE_MSB 2 +#define LF_TIMER_CONTROL0_ENABLE_LSB 2 +#define LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL0_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL0_ENABLE_MASK) >> LF_TIMER_CONTROL0_ENABLE_LSB) +#define LF_TIMER_CONTROL0_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL0_ENABLE_LSB) & LF_TIMER_CONTROL0_ENABLE_MASK) +#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL0_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL0_RESET_MSB 0 +#define LF_TIMER_CONTROL0_RESET_LSB 0 +#define LF_TIMER_CONTROL0_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL0_RESET_GET(x) (((x) & LF_TIMER_CONTROL0_RESET_MASK) >> LF_TIMER_CONTROL0_RESET_LSB) +#define LF_TIMER_CONTROL0_RESET_SET(x) (((x) << LF_TIMER_CONTROL0_RESET_LSB) & LF_TIMER_CONTROL0_RESET_MASK) + +#define LF_TIMER_STATUS0_ADDRESS 0x00000054 +#define LF_TIMER_STATUS0_OFFSET 0x00000054 +#define LF_TIMER_STATUS0_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS0_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS0_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS0_INTERRUPT_MASK) >> LF_TIMER_STATUS0_INTERRUPT_LSB) +#define LF_TIMER_STATUS0_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS0_INTERRUPT_LSB) & LF_TIMER_STATUS0_INTERRUPT_MASK) + +#define LF_TIMER1_ADDRESS 0x00000058 +#define LF_TIMER1_OFFSET 0x00000058 +#define LF_TIMER1_TARGET_MSB 31 +#define LF_TIMER1_TARGET_LSB 0 +#define LF_TIMER1_TARGET_MASK 0xffffffff +#define LF_TIMER1_TARGET_GET(x) (((x) & LF_TIMER1_TARGET_MASK) >> LF_TIMER1_TARGET_LSB) +#define LF_TIMER1_TARGET_SET(x) (((x) << LF_TIMER1_TARGET_LSB) & LF_TIMER1_TARGET_MASK) + +#define LF_TIMER_COUNT1_ADDRESS 0x0000005c +#define LF_TIMER_COUNT1_OFFSET 0x0000005c +#define LF_TIMER_COUNT1_VALUE_MSB 31 +#define LF_TIMER_COUNT1_VALUE_LSB 0 +#define LF_TIMER_COUNT1_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT1_VALUE_GET(x) (((x) & LF_TIMER_COUNT1_VALUE_MASK) >> LF_TIMER_COUNT1_VALUE_LSB) +#define LF_TIMER_COUNT1_VALUE_SET(x) (((x) << LF_TIMER_COUNT1_VALUE_LSB) & LF_TIMER_COUNT1_VALUE_MASK) + +#define LF_TIMER_CONTROL1_ADDRESS 0x00000060 +#define LF_TIMER_CONTROL1_OFFSET 0x00000060 +#define LF_TIMER_CONTROL1_ENABLE_MSB 2 +#define LF_TIMER_CONTROL1_ENABLE_LSB 2 +#define LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL1_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL1_ENABLE_MASK) >> LF_TIMER_CONTROL1_ENABLE_LSB) +#define LF_TIMER_CONTROL1_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL1_ENABLE_LSB) & LF_TIMER_CONTROL1_ENABLE_MASK) +#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL1_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL1_RESET_MSB 0 +#define LF_TIMER_CONTROL1_RESET_LSB 0 +#define LF_TIMER_CONTROL1_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL1_RESET_GET(x) (((x) & LF_TIMER_CONTROL1_RESET_MASK) >> LF_TIMER_CONTROL1_RESET_LSB) +#define LF_TIMER_CONTROL1_RESET_SET(x) (((x) << LF_TIMER_CONTROL1_RESET_LSB) & LF_TIMER_CONTROL1_RESET_MASK) + +#define LF_TIMER_STATUS1_ADDRESS 0x00000064 +#define LF_TIMER_STATUS1_OFFSET 0x00000064 +#define LF_TIMER_STATUS1_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS1_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS1_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS1_INTERRUPT_MASK) >> LF_TIMER_STATUS1_INTERRUPT_LSB) +#define LF_TIMER_STATUS1_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS1_INTERRUPT_LSB) & LF_TIMER_STATUS1_INTERRUPT_MASK) + +#define LF_TIMER2_ADDRESS 0x00000068 +#define LF_TIMER2_OFFSET 0x00000068 +#define LF_TIMER2_TARGET_MSB 31 +#define LF_TIMER2_TARGET_LSB 0 +#define LF_TIMER2_TARGET_MASK 0xffffffff +#define LF_TIMER2_TARGET_GET(x) (((x) & LF_TIMER2_TARGET_MASK) >> LF_TIMER2_TARGET_LSB) +#define LF_TIMER2_TARGET_SET(x) (((x) << LF_TIMER2_TARGET_LSB) & LF_TIMER2_TARGET_MASK) + +#define LF_TIMER_COUNT2_ADDRESS 0x0000006c +#define LF_TIMER_COUNT2_OFFSET 0x0000006c +#define LF_TIMER_COUNT2_VALUE_MSB 31 +#define LF_TIMER_COUNT2_VALUE_LSB 0 +#define LF_TIMER_COUNT2_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT2_VALUE_GET(x) (((x) & LF_TIMER_COUNT2_VALUE_MASK) >> LF_TIMER_COUNT2_VALUE_LSB) +#define LF_TIMER_COUNT2_VALUE_SET(x) (((x) << LF_TIMER_COUNT2_VALUE_LSB) & LF_TIMER_COUNT2_VALUE_MASK) + +#define LF_TIMER_CONTROL2_ADDRESS 0x00000070 +#define LF_TIMER_CONTROL2_OFFSET 0x00000070 +#define LF_TIMER_CONTROL2_ENABLE_MSB 2 +#define LF_TIMER_CONTROL2_ENABLE_LSB 2 +#define LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL2_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL2_ENABLE_MASK) >> LF_TIMER_CONTROL2_ENABLE_LSB) +#define LF_TIMER_CONTROL2_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL2_ENABLE_LSB) & LF_TIMER_CONTROL2_ENABLE_MASK) +#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL2_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL2_RESET_MSB 0 +#define LF_TIMER_CONTROL2_RESET_LSB 0 +#define LF_TIMER_CONTROL2_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL2_RESET_GET(x) (((x) & LF_TIMER_CONTROL2_RESET_MASK) >> LF_TIMER_CONTROL2_RESET_LSB) +#define LF_TIMER_CONTROL2_RESET_SET(x) (((x) << LF_TIMER_CONTROL2_RESET_LSB) & LF_TIMER_CONTROL2_RESET_MASK) + +#define LF_TIMER_STATUS2_ADDRESS 0x00000074 +#define LF_TIMER_STATUS2_OFFSET 0x00000074 +#define LF_TIMER_STATUS2_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS2_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS2_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS2_INTERRUPT_MASK) >> LF_TIMER_STATUS2_INTERRUPT_LSB) +#define LF_TIMER_STATUS2_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS2_INTERRUPT_LSB) & LF_TIMER_STATUS2_INTERRUPT_MASK) + +#define LF_TIMER3_ADDRESS 0x00000078 +#define LF_TIMER3_OFFSET 0x00000078 +#define LF_TIMER3_TARGET_MSB 31 +#define LF_TIMER3_TARGET_LSB 0 +#define LF_TIMER3_TARGET_MASK 0xffffffff +#define LF_TIMER3_TARGET_GET(x) (((x) & LF_TIMER3_TARGET_MASK) >> LF_TIMER3_TARGET_LSB) +#define LF_TIMER3_TARGET_SET(x) (((x) << LF_TIMER3_TARGET_LSB) & LF_TIMER3_TARGET_MASK) + +#define LF_TIMER_COUNT3_ADDRESS 0x0000007c +#define LF_TIMER_COUNT3_OFFSET 0x0000007c +#define LF_TIMER_COUNT3_VALUE_MSB 31 +#define LF_TIMER_COUNT3_VALUE_LSB 0 +#define LF_TIMER_COUNT3_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT3_VALUE_GET(x) (((x) & LF_TIMER_COUNT3_VALUE_MASK) >> LF_TIMER_COUNT3_VALUE_LSB) +#define LF_TIMER_COUNT3_VALUE_SET(x) (((x) << LF_TIMER_COUNT3_VALUE_LSB) & LF_TIMER_COUNT3_VALUE_MASK) + +#define LF_TIMER_CONTROL3_ADDRESS 0x00000080 +#define LF_TIMER_CONTROL3_OFFSET 0x00000080 +#define LF_TIMER_CONTROL3_ENABLE_MSB 2 +#define LF_TIMER_CONTROL3_ENABLE_LSB 2 +#define LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL3_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL3_ENABLE_MASK) >> LF_TIMER_CONTROL3_ENABLE_LSB) +#define LF_TIMER_CONTROL3_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL3_ENABLE_LSB) & LF_TIMER_CONTROL3_ENABLE_MASK) +#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL3_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL3_RESET_MSB 0 +#define LF_TIMER_CONTROL3_RESET_LSB 0 +#define LF_TIMER_CONTROL3_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL3_RESET_GET(x) (((x) & LF_TIMER_CONTROL3_RESET_MASK) >> LF_TIMER_CONTROL3_RESET_LSB) +#define LF_TIMER_CONTROL3_RESET_SET(x) (((x) << LF_TIMER_CONTROL3_RESET_LSB) & LF_TIMER_CONTROL3_RESET_MASK) + +#define LF_TIMER_STATUS3_ADDRESS 0x00000084 +#define LF_TIMER_STATUS3_OFFSET 0x00000084 +#define LF_TIMER_STATUS3_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS3_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS3_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS3_INTERRUPT_MASK) >> LF_TIMER_STATUS3_INTERRUPT_LSB) +#define LF_TIMER_STATUS3_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS3_INTERRUPT_LSB) & LF_TIMER_STATUS3_INTERRUPT_MASK) + +#define HF_TIMER_ADDRESS 0x00000088 +#define HF_TIMER_OFFSET 0x00000088 +#define HF_TIMER_TARGET_MSB 31 +#define HF_TIMER_TARGET_LSB 12 +#define HF_TIMER_TARGET_MASK 0xfffff000 +#define HF_TIMER_TARGET_GET(x) (((x) & HF_TIMER_TARGET_MASK) >> HF_TIMER_TARGET_LSB) +#define HF_TIMER_TARGET_SET(x) (((x) << HF_TIMER_TARGET_LSB) & HF_TIMER_TARGET_MASK) + +#define HF_TIMER_COUNT_ADDRESS 0x0000008c +#define HF_TIMER_COUNT_OFFSET 0x0000008c +#define HF_TIMER_COUNT_VALUE_MSB 31 +#define HF_TIMER_COUNT_VALUE_LSB 12 +#define HF_TIMER_COUNT_VALUE_MASK 0xfffff000 +#define HF_TIMER_COUNT_VALUE_GET(x) (((x) & HF_TIMER_COUNT_VALUE_MASK) >> HF_TIMER_COUNT_VALUE_LSB) +#define HF_TIMER_COUNT_VALUE_SET(x) (((x) << HF_TIMER_COUNT_VALUE_LSB) & HF_TIMER_COUNT_VALUE_MASK) + +#define HF_LF_COUNT_ADDRESS 0x00000090 +#define HF_LF_COUNT_OFFSET 0x00000090 +#define HF_LF_COUNT_VALUE_MSB 31 +#define HF_LF_COUNT_VALUE_LSB 0 +#define HF_LF_COUNT_VALUE_MASK 0xffffffff +#define HF_LF_COUNT_VALUE_GET(x) (((x) & HF_LF_COUNT_VALUE_MASK) >> HF_LF_COUNT_VALUE_LSB) +#define HF_LF_COUNT_VALUE_SET(x) (((x) << HF_LF_COUNT_VALUE_LSB) & HF_LF_COUNT_VALUE_MASK) + +#define HF_TIMER_CONTROL_ADDRESS 0x00000094 +#define HF_TIMER_CONTROL_OFFSET 0x00000094 +#define HF_TIMER_CONTROL_ENABLE_MSB 3 +#define HF_TIMER_CONTROL_ENABLE_LSB 3 +#define HF_TIMER_CONTROL_ENABLE_MASK 0x00000008 +#define HF_TIMER_CONTROL_ENABLE_GET(x) (((x) & HF_TIMER_CONTROL_ENABLE_MASK) >> HF_TIMER_CONTROL_ENABLE_LSB) +#define HF_TIMER_CONTROL_ENABLE_SET(x) (((x) << HF_TIMER_CONTROL_ENABLE_LSB) & HF_TIMER_CONTROL_ENABLE_MASK) +#define HF_TIMER_CONTROL_ON_MSB 2 +#define HF_TIMER_CONTROL_ON_LSB 2 +#define HF_TIMER_CONTROL_ON_MASK 0x00000004 +#define HF_TIMER_CONTROL_ON_GET(x) (((x) & HF_TIMER_CONTROL_ON_MASK) >> HF_TIMER_CONTROL_ON_LSB) +#define HF_TIMER_CONTROL_ON_SET(x) (((x) << HF_TIMER_CONTROL_ON_LSB) & HF_TIMER_CONTROL_ON_MASK) +#define HF_TIMER_CONTROL_AUTO_RESTART_MSB 1 +#define HF_TIMER_CONTROL_AUTO_RESTART_LSB 1 +#define HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002 +#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> HF_TIMER_CONTROL_AUTO_RESTART_LSB) +#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << HF_TIMER_CONTROL_AUTO_RESTART_LSB) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) +#define HF_TIMER_CONTROL_RESET_MSB 0 +#define HF_TIMER_CONTROL_RESET_LSB 0 +#define HF_TIMER_CONTROL_RESET_MASK 0x00000001 +#define HF_TIMER_CONTROL_RESET_GET(x) (((x) & HF_TIMER_CONTROL_RESET_MASK) >> HF_TIMER_CONTROL_RESET_LSB) +#define HF_TIMER_CONTROL_RESET_SET(x) (((x) << HF_TIMER_CONTROL_RESET_LSB) & HF_TIMER_CONTROL_RESET_MASK) + +#define HF_TIMER_STATUS_ADDRESS 0x00000098 +#define HF_TIMER_STATUS_OFFSET 0x00000098 +#define HF_TIMER_STATUS_INTERRUPT_MSB 0 +#define HF_TIMER_STATUS_INTERRUPT_LSB 0 +#define HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001 +#define HF_TIMER_STATUS_INTERRUPT_GET(x) (((x) & HF_TIMER_STATUS_INTERRUPT_MASK) >> HF_TIMER_STATUS_INTERRUPT_LSB) +#define HF_TIMER_STATUS_INTERRUPT_SET(x) (((x) << HF_TIMER_STATUS_INTERRUPT_LSB) & HF_TIMER_STATUS_INTERRUPT_MASK) + +#define RTC_CONTROL_ADDRESS 0x0000009c +#define RTC_CONTROL_OFFSET 0x0000009c +#define RTC_CONTROL_ENABLE_MSB 2 +#define RTC_CONTROL_ENABLE_LSB 2 +#define RTC_CONTROL_ENABLE_MASK 0x00000004 +#define RTC_CONTROL_ENABLE_GET(x) (((x) & RTC_CONTROL_ENABLE_MASK) >> RTC_CONTROL_ENABLE_LSB) +#define RTC_CONTROL_ENABLE_SET(x) (((x) << RTC_CONTROL_ENABLE_LSB) & RTC_CONTROL_ENABLE_MASK) +#define RTC_CONTROL_LOAD_RTC_MSB 1 +#define RTC_CONTROL_LOAD_RTC_LSB 1 +#define RTC_CONTROL_LOAD_RTC_MASK 0x00000002 +#define RTC_CONTROL_LOAD_RTC_GET(x) (((x) & RTC_CONTROL_LOAD_RTC_MASK) >> RTC_CONTROL_LOAD_RTC_LSB) +#define RTC_CONTROL_LOAD_RTC_SET(x) (((x) << RTC_CONTROL_LOAD_RTC_LSB) & RTC_CONTROL_LOAD_RTC_MASK) +#define RTC_CONTROL_LOAD_ALARM_MSB 0 +#define RTC_CONTROL_LOAD_ALARM_LSB 0 +#define RTC_CONTROL_LOAD_ALARM_MASK 0x00000001 +#define RTC_CONTROL_LOAD_ALARM_GET(x) (((x) & RTC_CONTROL_LOAD_ALARM_MASK) >> RTC_CONTROL_LOAD_ALARM_LSB) +#define RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << RTC_CONTROL_LOAD_ALARM_LSB) & RTC_CONTROL_LOAD_ALARM_MASK) + +#define RTC_TIME_ADDRESS 0x000000a0 +#define RTC_TIME_OFFSET 0x000000a0 +#define RTC_TIME_WEEK_DAY_MSB 26 +#define RTC_TIME_WEEK_DAY_LSB 24 +#define RTC_TIME_WEEK_DAY_MASK 0x07000000 +#define RTC_TIME_WEEK_DAY_GET(x) (((x) & RTC_TIME_WEEK_DAY_MASK) >> RTC_TIME_WEEK_DAY_LSB) +#define RTC_TIME_WEEK_DAY_SET(x) (((x) << RTC_TIME_WEEK_DAY_LSB) & RTC_TIME_WEEK_DAY_MASK) +#define RTC_TIME_HOUR_MSB 21 +#define RTC_TIME_HOUR_LSB 16 +#define RTC_TIME_HOUR_MASK 0x003f0000 +#define RTC_TIME_HOUR_GET(x) (((x) & RTC_TIME_HOUR_MASK) >> RTC_TIME_HOUR_LSB) +#define RTC_TIME_HOUR_SET(x) (((x) << RTC_TIME_HOUR_LSB) & RTC_TIME_HOUR_MASK) +#define RTC_TIME_MINUTE_MSB 14 +#define RTC_TIME_MINUTE_LSB 8 +#define RTC_TIME_MINUTE_MASK 0x00007f00 +#define RTC_TIME_MINUTE_GET(x) (((x) & RTC_TIME_MINUTE_MASK) >> RTC_TIME_MINUTE_LSB) +#define RTC_TIME_MINUTE_SET(x) (((x) << RTC_TIME_MINUTE_LSB) & RTC_TIME_MINUTE_MASK) +#define RTC_TIME_SECOND_MSB 6 +#define RTC_TIME_SECOND_LSB 0 +#define RTC_TIME_SECOND_MASK 0x0000007f +#define RTC_TIME_SECOND_GET(x) (((x) & RTC_TIME_SECOND_MASK) >> RTC_TIME_SECOND_LSB) +#define RTC_TIME_SECOND_SET(x) (((x) << RTC_TIME_SECOND_LSB) & RTC_TIME_SECOND_MASK) + +#define RTC_DATE_ADDRESS 0x000000a4 +#define RTC_DATE_OFFSET 0x000000a4 +#define RTC_DATE_YEAR_MSB 23 +#define RTC_DATE_YEAR_LSB 16 +#define RTC_DATE_YEAR_MASK 0x00ff0000 +#define RTC_DATE_YEAR_GET(x) (((x) & RTC_DATE_YEAR_MASK) >> RTC_DATE_YEAR_LSB) +#define RTC_DATE_YEAR_SET(x) (((x) << RTC_DATE_YEAR_LSB) & RTC_DATE_YEAR_MASK) +#define RTC_DATE_MONTH_MSB 12 +#define RTC_DATE_MONTH_LSB 8 +#define RTC_DATE_MONTH_MASK 0x00001f00 +#define RTC_DATE_MONTH_GET(x) (((x) & RTC_DATE_MONTH_MASK) >> RTC_DATE_MONTH_LSB) +#define RTC_DATE_MONTH_SET(x) (((x) << RTC_DATE_MONTH_LSB) & RTC_DATE_MONTH_MASK) +#define RTC_DATE_MONTH_DAY_MSB 5 +#define RTC_DATE_MONTH_DAY_LSB 0 +#define RTC_DATE_MONTH_DAY_MASK 0x0000003f +#define RTC_DATE_MONTH_DAY_GET(x) (((x) & RTC_DATE_MONTH_DAY_MASK) >> RTC_DATE_MONTH_DAY_LSB) +#define RTC_DATE_MONTH_DAY_SET(x) (((x) << RTC_DATE_MONTH_DAY_LSB) & RTC_DATE_MONTH_DAY_MASK) + +#define RTC_SET_TIME_ADDRESS 0x000000a8 +#define RTC_SET_TIME_OFFSET 0x000000a8 +#define RTC_SET_TIME_WEEK_DAY_MSB 26 +#define RTC_SET_TIME_WEEK_DAY_LSB 24 +#define RTC_SET_TIME_WEEK_DAY_MASK 0x07000000 +#define RTC_SET_TIME_WEEK_DAY_GET(x) (((x) & RTC_SET_TIME_WEEK_DAY_MASK) >> RTC_SET_TIME_WEEK_DAY_LSB) +#define RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << RTC_SET_TIME_WEEK_DAY_LSB) & RTC_SET_TIME_WEEK_DAY_MASK) +#define RTC_SET_TIME_HOUR_MSB 21 +#define RTC_SET_TIME_HOUR_LSB 16 +#define RTC_SET_TIME_HOUR_MASK 0x003f0000 +#define RTC_SET_TIME_HOUR_GET(x) (((x) & RTC_SET_TIME_HOUR_MASK) >> RTC_SET_TIME_HOUR_LSB) +#define RTC_SET_TIME_HOUR_SET(x) (((x) << RTC_SET_TIME_HOUR_LSB) & RTC_SET_TIME_HOUR_MASK) +#define RTC_SET_TIME_MINUTE_MSB 14 +#define RTC_SET_TIME_MINUTE_LSB 8 +#define RTC_SET_TIME_MINUTE_MASK 0x00007f00 +#define RTC_SET_TIME_MINUTE_GET(x) (((x) & RTC_SET_TIME_MINUTE_MASK) >> RTC_SET_TIME_MINUTE_LSB) +#define RTC_SET_TIME_MINUTE_SET(x) (((x) << RTC_SET_TIME_MINUTE_LSB) & RTC_SET_TIME_MINUTE_MASK) +#define RTC_SET_TIME_SECOND_MSB 6 +#define RTC_SET_TIME_SECOND_LSB 0 +#define RTC_SET_TIME_SECOND_MASK 0x0000007f +#define RTC_SET_TIME_SECOND_GET(x) (((x) & RTC_SET_TIME_SECOND_MASK) >> RTC_SET_TIME_SECOND_LSB) +#define RTC_SET_TIME_SECOND_SET(x) (((x) << RTC_SET_TIME_SECOND_LSB) & RTC_SET_TIME_SECOND_MASK) + +#define RTC_SET_DATE_ADDRESS 0x000000ac +#define RTC_SET_DATE_OFFSET 0x000000ac +#define RTC_SET_DATE_YEAR_MSB 23 +#define RTC_SET_DATE_YEAR_LSB 16 +#define RTC_SET_DATE_YEAR_MASK 0x00ff0000 +#define RTC_SET_DATE_YEAR_GET(x) (((x) & RTC_SET_DATE_YEAR_MASK) >> RTC_SET_DATE_YEAR_LSB) +#define RTC_SET_DATE_YEAR_SET(x) (((x) << RTC_SET_DATE_YEAR_LSB) & RTC_SET_DATE_YEAR_MASK) +#define RTC_SET_DATE_MONTH_MSB 12 +#define RTC_SET_DATE_MONTH_LSB 8 +#define RTC_SET_DATE_MONTH_MASK 0x00001f00 +#define RTC_SET_DATE_MONTH_GET(x) (((x) & RTC_SET_DATE_MONTH_MASK) >> RTC_SET_DATE_MONTH_LSB) +#define RTC_SET_DATE_MONTH_SET(x) (((x) << RTC_SET_DATE_MONTH_LSB) & RTC_SET_DATE_MONTH_MASK) +#define RTC_SET_DATE_MONTH_DAY_MSB 5 +#define RTC_SET_DATE_MONTH_DAY_LSB 0 +#define RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f +#define RTC_SET_DATE_MONTH_DAY_GET(x) (((x) & RTC_SET_DATE_MONTH_DAY_MASK) >> RTC_SET_DATE_MONTH_DAY_LSB) +#define RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << RTC_SET_DATE_MONTH_DAY_LSB) & RTC_SET_DATE_MONTH_DAY_MASK) + +#define RTC_SET_ALARM_ADDRESS 0x000000b0 +#define RTC_SET_ALARM_OFFSET 0x000000b0 +#define RTC_SET_ALARM_HOUR_MSB 21 +#define RTC_SET_ALARM_HOUR_LSB 16 +#define RTC_SET_ALARM_HOUR_MASK 0x003f0000 +#define RTC_SET_ALARM_HOUR_GET(x) (((x) & RTC_SET_ALARM_HOUR_MASK) >> RTC_SET_ALARM_HOUR_LSB) +#define RTC_SET_ALARM_HOUR_SET(x) (((x) << RTC_SET_ALARM_HOUR_LSB) & RTC_SET_ALARM_HOUR_MASK) +#define RTC_SET_ALARM_MINUTE_MSB 14 +#define RTC_SET_ALARM_MINUTE_LSB 8 +#define RTC_SET_ALARM_MINUTE_MASK 0x00007f00 +#define RTC_SET_ALARM_MINUTE_GET(x) (((x) & RTC_SET_ALARM_MINUTE_MASK) >> RTC_SET_ALARM_MINUTE_LSB) +#define RTC_SET_ALARM_MINUTE_SET(x) (((x) << RTC_SET_ALARM_MINUTE_LSB) & RTC_SET_ALARM_MINUTE_MASK) +#define RTC_SET_ALARM_SECOND_MSB 6 +#define RTC_SET_ALARM_SECOND_LSB 0 +#define RTC_SET_ALARM_SECOND_MASK 0x0000007f +#define RTC_SET_ALARM_SECOND_GET(x) (((x) & RTC_SET_ALARM_SECOND_MASK) >> RTC_SET_ALARM_SECOND_LSB) +#define RTC_SET_ALARM_SECOND_SET(x) (((x) << RTC_SET_ALARM_SECOND_LSB) & RTC_SET_ALARM_SECOND_MASK) + +#define RTC_CONFIG_ADDRESS 0x000000b4 +#define RTC_CONFIG_OFFSET 0x000000b4 +#define RTC_CONFIG_BCD_MSB 2 +#define RTC_CONFIG_BCD_LSB 2 +#define RTC_CONFIG_BCD_MASK 0x00000004 +#define RTC_CONFIG_BCD_GET(x) (((x) & RTC_CONFIG_BCD_MASK) >> RTC_CONFIG_BCD_LSB) +#define RTC_CONFIG_BCD_SET(x) (((x) << RTC_CONFIG_BCD_LSB) & RTC_CONFIG_BCD_MASK) +#define RTC_CONFIG_TWELVE_HOUR_MSB 1 +#define RTC_CONFIG_TWELVE_HOUR_LSB 1 +#define RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002 +#define RTC_CONFIG_TWELVE_HOUR_GET(x) (((x) & RTC_CONFIG_TWELVE_HOUR_MASK) >> RTC_CONFIG_TWELVE_HOUR_LSB) +#define RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << RTC_CONFIG_TWELVE_HOUR_LSB) & RTC_CONFIG_TWELVE_HOUR_MASK) +#define RTC_CONFIG_DSE_MSB 0 +#define RTC_CONFIG_DSE_LSB 0 +#define RTC_CONFIG_DSE_MASK 0x00000001 +#define RTC_CONFIG_DSE_GET(x) (((x) & RTC_CONFIG_DSE_MASK) >> RTC_CONFIG_DSE_LSB) +#define RTC_CONFIG_DSE_SET(x) (((x) << RTC_CONFIG_DSE_LSB) & RTC_CONFIG_DSE_MASK) + +#define RTC_ALARM_STATUS_ADDRESS 0x000000b8 +#define RTC_ALARM_STATUS_OFFSET 0x000000b8 +#define RTC_ALARM_STATUS_ENABLE_MSB 1 +#define RTC_ALARM_STATUS_ENABLE_LSB 1 +#define RTC_ALARM_STATUS_ENABLE_MASK 0x00000002 +#define RTC_ALARM_STATUS_ENABLE_GET(x) (((x) & RTC_ALARM_STATUS_ENABLE_MASK) >> RTC_ALARM_STATUS_ENABLE_LSB) +#define RTC_ALARM_STATUS_ENABLE_SET(x) (((x) << RTC_ALARM_STATUS_ENABLE_LSB) & RTC_ALARM_STATUS_ENABLE_MASK) +#define RTC_ALARM_STATUS_INTERRUPT_MSB 0 +#define RTC_ALARM_STATUS_INTERRUPT_LSB 0 +#define RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001 +#define RTC_ALARM_STATUS_INTERRUPT_GET(x) (((x) & RTC_ALARM_STATUS_INTERRUPT_MASK) >> RTC_ALARM_STATUS_INTERRUPT_LSB) +#define RTC_ALARM_STATUS_INTERRUPT_SET(x) (((x) << RTC_ALARM_STATUS_INTERRUPT_LSB) & RTC_ALARM_STATUS_INTERRUPT_MASK) + +#define UART_WAKEUP_ADDRESS 0x000000bc +#define UART_WAKEUP_OFFSET 0x000000bc +#define UART_WAKEUP_ENABLE_MSB 0 +#define UART_WAKEUP_ENABLE_LSB 0 +#define UART_WAKEUP_ENABLE_MASK 0x00000001 +#define UART_WAKEUP_ENABLE_GET(x) (((x) & UART_WAKEUP_ENABLE_MASK) >> UART_WAKEUP_ENABLE_LSB) +#define UART_WAKEUP_ENABLE_SET(x) (((x) << UART_WAKEUP_ENABLE_LSB) & UART_WAKEUP_ENABLE_MASK) + +#define RESET_CAUSE_ADDRESS 0x000000c0 +#define RESET_CAUSE_OFFSET 0x000000c0 +#define RESET_CAUSE_LAST_MSB 2 +#define RESET_CAUSE_LAST_LSB 0 +#define RESET_CAUSE_LAST_MASK 0x00000007 +#define RESET_CAUSE_LAST_GET(x) (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB) +#define RESET_CAUSE_LAST_SET(x) (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK) + +#define SYSTEM_SLEEP_ADDRESS 0x000000c4 +#define SYSTEM_SLEEP_OFFSET 0x000000c4 +#define SYSTEM_SLEEP_HOST_IF_MSB 4 +#define SYSTEM_SLEEP_HOST_IF_LSB 4 +#define SYSTEM_SLEEP_HOST_IF_MASK 0x00000010 +#define SYSTEM_SLEEP_HOST_IF_GET(x) (((x) & SYSTEM_SLEEP_HOST_IF_MASK) >> SYSTEM_SLEEP_HOST_IF_LSB) +#define SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << SYSTEM_SLEEP_HOST_IF_LSB) & SYSTEM_SLEEP_HOST_IF_MASK) +#define SYSTEM_SLEEP_MBOX_MSB 3 +#define SYSTEM_SLEEP_MBOX_LSB 3 +#define SYSTEM_SLEEP_MBOX_MASK 0x00000008 +#define SYSTEM_SLEEP_MBOX_GET(x) (((x) & SYSTEM_SLEEP_MBOX_MASK) >> SYSTEM_SLEEP_MBOX_LSB) +#define SYSTEM_SLEEP_MBOX_SET(x) (((x) << SYSTEM_SLEEP_MBOX_LSB) & SYSTEM_SLEEP_MBOX_MASK) +#define SYSTEM_SLEEP_MAC_IF_MSB 2 +#define SYSTEM_SLEEP_MAC_IF_LSB 2 +#define SYSTEM_SLEEP_MAC_IF_MASK 0x00000004 +#define SYSTEM_SLEEP_MAC_IF_GET(x) (((x) & SYSTEM_SLEEP_MAC_IF_MASK) >> SYSTEM_SLEEP_MAC_IF_LSB) +#define SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << SYSTEM_SLEEP_MAC_IF_LSB) & SYSTEM_SLEEP_MAC_IF_MASK) +#define SYSTEM_SLEEP_LIGHT_MSB 1 +#define SYSTEM_SLEEP_LIGHT_LSB 1 +#define SYSTEM_SLEEP_LIGHT_MASK 0x00000002 +#define SYSTEM_SLEEP_LIGHT_GET(x) (((x) & SYSTEM_SLEEP_LIGHT_MASK) >> SYSTEM_SLEEP_LIGHT_LSB) +#define SYSTEM_SLEEP_LIGHT_SET(x) (((x) << SYSTEM_SLEEP_LIGHT_LSB) & SYSTEM_SLEEP_LIGHT_MASK) +#define SYSTEM_SLEEP_DISABLE_MSB 0 +#define SYSTEM_SLEEP_DISABLE_LSB 0 +#define SYSTEM_SLEEP_DISABLE_MASK 0x00000001 +#define SYSTEM_SLEEP_DISABLE_GET(x) (((x) & SYSTEM_SLEEP_DISABLE_MASK) >> SYSTEM_SLEEP_DISABLE_LSB) +#define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK) + +#define SDIO_WRAPPER_ADDRESS 0x000000c8 +#define SDIO_WRAPPER_OFFSET 0x000000c8 +#define SDIO_WRAPPER_SLEEP_MSB 3 +#define SDIO_WRAPPER_SLEEP_LSB 3 +#define SDIO_WRAPPER_SLEEP_MASK 0x00000008 +#define SDIO_WRAPPER_SLEEP_GET(x) (((x) & SDIO_WRAPPER_SLEEP_MASK) >> SDIO_WRAPPER_SLEEP_LSB) +#define SDIO_WRAPPER_SLEEP_SET(x) (((x) << SDIO_WRAPPER_SLEEP_LSB) & SDIO_WRAPPER_SLEEP_MASK) +#define SDIO_WRAPPER_WAKEUP_MSB 2 +#define SDIO_WRAPPER_WAKEUP_LSB 2 +#define SDIO_WRAPPER_WAKEUP_MASK 0x00000004 +#define SDIO_WRAPPER_WAKEUP_GET(x) (((x) & SDIO_WRAPPER_WAKEUP_MASK) >> SDIO_WRAPPER_WAKEUP_LSB) +#define SDIO_WRAPPER_WAKEUP_SET(x) (((x) << SDIO_WRAPPER_WAKEUP_LSB) & SDIO_WRAPPER_WAKEUP_MASK) +#define SDIO_WRAPPER_SOC_ON_MSB 1 +#define SDIO_WRAPPER_SOC_ON_LSB 1 +#define SDIO_WRAPPER_SOC_ON_MASK 0x00000002 +#define SDIO_WRAPPER_SOC_ON_GET(x) (((x) & SDIO_WRAPPER_SOC_ON_MASK) >> SDIO_WRAPPER_SOC_ON_LSB) +#define SDIO_WRAPPER_SOC_ON_SET(x) (((x) << SDIO_WRAPPER_SOC_ON_LSB) & SDIO_WRAPPER_SOC_ON_MASK) +#define SDIO_WRAPPER_ON_MSB 0 +#define SDIO_WRAPPER_ON_LSB 0 +#define SDIO_WRAPPER_ON_MASK 0x00000001 +#define SDIO_WRAPPER_ON_GET(x) (((x) & SDIO_WRAPPER_ON_MASK) >> SDIO_WRAPPER_ON_LSB) +#define SDIO_WRAPPER_ON_SET(x) (((x) << SDIO_WRAPPER_ON_LSB) & SDIO_WRAPPER_ON_MASK) + +#define MAC_SLEEP_CONTROL_ADDRESS 0x000000cc +#define MAC_SLEEP_CONTROL_OFFSET 0x000000cc +#define MAC_SLEEP_CONTROL_ENABLE_MSB 1 +#define MAC_SLEEP_CONTROL_ENABLE_LSB 0 +#define MAC_SLEEP_CONTROL_ENABLE_MASK 0x00000003 +#define MAC_SLEEP_CONTROL_ENABLE_GET(x) (((x) & MAC_SLEEP_CONTROL_ENABLE_MASK) >> MAC_SLEEP_CONTROL_ENABLE_LSB) +#define MAC_SLEEP_CONTROL_ENABLE_SET(x) (((x) << MAC_SLEEP_CONTROL_ENABLE_LSB) & MAC_SLEEP_CONTROL_ENABLE_MASK) + +#define KEEP_AWAKE_ADDRESS 0x000000d0 +#define KEEP_AWAKE_OFFSET 0x000000d0 +#define KEEP_AWAKE_COUNT_MSB 7 +#define KEEP_AWAKE_COUNT_LSB 0 +#define KEEP_AWAKE_COUNT_MASK 0x000000ff +#define KEEP_AWAKE_COUNT_GET(x) (((x) & KEEP_AWAKE_COUNT_MASK) >> KEEP_AWAKE_COUNT_LSB) +#define KEEP_AWAKE_COUNT_SET(x) (((x) << KEEP_AWAKE_COUNT_LSB) & KEEP_AWAKE_COUNT_MASK) + +#define LPO_CAL_TIME_ADDRESS 0x000000d4 +#define LPO_CAL_TIME_OFFSET 0x000000d4 +#define LPO_CAL_TIME_LENGTH_MSB 13 +#define LPO_CAL_TIME_LENGTH_LSB 0 +#define LPO_CAL_TIME_LENGTH_MASK 0x00003fff +#define LPO_CAL_TIME_LENGTH_GET(x) (((x) & LPO_CAL_TIME_LENGTH_MASK) >> LPO_CAL_TIME_LENGTH_LSB) +#define LPO_CAL_TIME_LENGTH_SET(x) (((x) << LPO_CAL_TIME_LENGTH_LSB) & LPO_CAL_TIME_LENGTH_MASK) + +#define LPO_INIT_DIVIDEND_INT_ADDRESS 0x000000d8 +#define LPO_INIT_DIVIDEND_INT_OFFSET 0x000000d8 +#define LPO_INIT_DIVIDEND_INT_VALUE_MSB 23 +#define LPO_INIT_DIVIDEND_INT_VALUE_LSB 0 +#define LPO_INIT_DIVIDEND_INT_VALUE_MASK 0x00ffffff +#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> LPO_INIT_DIVIDEND_INT_VALUE_LSB) +#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_INT_VALUE_LSB) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) + +#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS 0x000000dc +#define LPO_INIT_DIVIDEND_FRACTION_OFFSET 0x000000dc +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10 +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0 +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) + +#define LPO_CAL_ADDRESS 0x000000e0 +#define LPO_CAL_OFFSET 0x000000e0 +#define LPO_CAL_ENABLE_MSB 20 +#define LPO_CAL_ENABLE_LSB 20 +#define LPO_CAL_ENABLE_MASK 0x00100000 +#define LPO_CAL_ENABLE_GET(x) (((x) & LPO_CAL_ENABLE_MASK) >> LPO_CAL_ENABLE_LSB) +#define LPO_CAL_ENABLE_SET(x) (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK) +#define LPO_CAL_COUNT_MSB 19 +#define LPO_CAL_COUNT_LSB 0 +#define LPO_CAL_COUNT_MASK 0x000fffff +#define LPO_CAL_COUNT_GET(x) (((x) & LPO_CAL_COUNT_MASK) >> LPO_CAL_COUNT_LSB) +#define LPO_CAL_COUNT_SET(x) (((x) << LPO_CAL_COUNT_LSB) & LPO_CAL_COUNT_MASK) + +#define LPO_CAL_TEST_CONTROL_ADDRESS 0x000000e4 +#define LPO_CAL_TEST_CONTROL_OFFSET 0x000000e4 +#define LPO_CAL_TEST_CONTROL_ENABLE_MSB 5 +#define LPO_CAL_TEST_CONTROL_ENABLE_LSB 5 +#define LPO_CAL_TEST_CONTROL_ENABLE_MASK 0x00000020 +#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) (((x) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> LPO_CAL_TEST_CONTROL_ENABLE_LSB) +#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) (((x) << LPO_CAL_TEST_CONTROL_ENABLE_LSB) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4 +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0 +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) + +#define LPO_CAL_TEST_STATUS_ADDRESS 0x000000e8 +#define LPO_CAL_TEST_STATUS_OFFSET 0x000000e8 +#define LPO_CAL_TEST_STATUS_READY_MSB 16 +#define LPO_CAL_TEST_STATUS_READY_LSB 16 +#define LPO_CAL_TEST_STATUS_READY_MASK 0x00010000 +#define LPO_CAL_TEST_STATUS_READY_GET(x) (((x) & LPO_CAL_TEST_STATUS_READY_MASK) >> LPO_CAL_TEST_STATUS_READY_LSB) +#define LPO_CAL_TEST_STATUS_READY_SET(x) (((x) << LPO_CAL_TEST_STATUS_READY_LSB) & LPO_CAL_TEST_STATUS_READY_MASK) +#define LPO_CAL_TEST_STATUS_COUNT_MSB 15 +#define LPO_CAL_TEST_STATUS_COUNT_LSB 0 +#define LPO_CAL_TEST_STATUS_COUNT_MASK 0x0000ffff +#define LPO_CAL_TEST_STATUS_COUNT_GET(x) (((x) & LPO_CAL_TEST_STATUS_COUNT_MASK) >> LPO_CAL_TEST_STATUS_COUNT_LSB) +#define LPO_CAL_TEST_STATUS_COUNT_SET(x) (((x) << LPO_CAL_TEST_STATUS_COUNT_LSB) & LPO_CAL_TEST_STATUS_COUNT_MASK) + +#define CHIP_ID_ADDRESS 0x000000ec +#define CHIP_ID_OFFSET 0x000000ec +#define CHIP_ID_DEVICE_ID_MSB 31 +#define CHIP_ID_DEVICE_ID_LSB 16 +#define CHIP_ID_DEVICE_ID_MASK 0xffff0000 +#define CHIP_ID_DEVICE_ID_GET(x) (((x) & CHIP_ID_DEVICE_ID_MASK) >> CHIP_ID_DEVICE_ID_LSB) +#define CHIP_ID_DEVICE_ID_SET(x) (((x) << CHIP_ID_DEVICE_ID_LSB) & CHIP_ID_DEVICE_ID_MASK) +#define CHIP_ID_CONFIG_ID_MSB 15 +#define CHIP_ID_CONFIG_ID_LSB 4 +#define CHIP_ID_CONFIG_ID_MASK 0x0000fff0 +#define CHIP_ID_CONFIG_ID_GET(x) (((x) & CHIP_ID_CONFIG_ID_MASK) >> CHIP_ID_CONFIG_ID_LSB) +#define CHIP_ID_CONFIG_ID_SET(x) (((x) << CHIP_ID_CONFIG_ID_LSB) & CHIP_ID_CONFIG_ID_MASK) +#define CHIP_ID_VERSION_ID_MSB 3 +#define CHIP_ID_VERSION_ID_LSB 0 +#define CHIP_ID_VERSION_ID_MASK 0x0000000f +#define CHIP_ID_VERSION_ID_GET(x) (((x) & CHIP_ID_VERSION_ID_MASK) >> CHIP_ID_VERSION_ID_LSB) +#define CHIP_ID_VERSION_ID_SET(x) (((x) << CHIP_ID_VERSION_ID_LSB) & CHIP_ID_VERSION_ID_MASK) + +#define DERIVED_RTC_CLK_ADDRESS 0x000000f0 +#define DERIVED_RTC_CLK_OFFSET 0x000000f0 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) +#define DERIVED_RTC_CLK_FORCE_MSB 17 +#define DERIVED_RTC_CLK_FORCE_LSB 16 +#define DERIVED_RTC_CLK_FORCE_MASK 0x00030000 +#define DERIVED_RTC_CLK_FORCE_GET(x) (((x) & DERIVED_RTC_CLK_FORCE_MASK) >> DERIVED_RTC_CLK_FORCE_LSB) +#define DERIVED_RTC_CLK_FORCE_SET(x) (((x) << DERIVED_RTC_CLK_FORCE_LSB) & DERIVED_RTC_CLK_FORCE_MASK) +#define DERIVED_RTC_CLK_PERIOD_MSB 15 +#define DERIVED_RTC_CLK_PERIOD_LSB 1 +#define DERIVED_RTC_CLK_PERIOD_MASK 0x0000fffe +#define DERIVED_RTC_CLK_PERIOD_GET(x) (((x) & DERIVED_RTC_CLK_PERIOD_MASK) >> DERIVED_RTC_CLK_PERIOD_LSB) +#define DERIVED_RTC_CLK_PERIOD_SET(x) (((x) << DERIVED_RTC_CLK_PERIOD_LSB) & DERIVED_RTC_CLK_PERIOD_MASK) + +#define MAC_PCU_SLP32_MODE_ADDRESS 0x000000f4 +#define MAC_PCU_SLP32_MODE_OFFSET 0x000000f4 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK 0x00200000 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB 19 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB 0 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) + +#define MAC_PCU_SLP32_WAKE_ADDRESS 0x000000f8 +#define MAC_PCU_SLP32_WAKE_OFFSET 0x000000f8 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB 15 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB 0 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK 0x0000ffff +#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x) (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) +#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x) (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) + +#define MAC_PCU_SLP32_INC_ADDRESS 0x000000fc +#define MAC_PCU_SLP32_INC_OFFSET 0x000000fc +#define MAC_PCU_SLP32_INC_TSF_INC_MSB 19 +#define MAC_PCU_SLP32_INC_TSF_INC_LSB 0 +#define MAC_PCU_SLP32_INC_TSF_INC_MASK 0x000fffff +#define MAC_PCU_SLP32_INC_TSF_INC_GET(x) (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB) +#define MAC_PCU_SLP32_INC_TSF_INC_SET(x) (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK) + +#define MAC_PCU_SLP_MIB1_ADDRESS 0x00000100 +#define MAC_PCU_SLP_MIB1_OFFSET 0x00000100 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB 31 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB 0 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) + +#define MAC_PCU_SLP_MIB2_ADDRESS 0x00000104 +#define MAC_PCU_SLP_MIB2_OFFSET 0x00000104 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB 31 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB 0 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) + +#define MAC_PCU_SLP_MIB3_ADDRESS 0x00000108 +#define MAC_PCU_SLP_MIB3_OFFSET 0x00000108 +#define MAC_PCU_SLP_MIB3_PENDING_MSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_LSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_MASK 0x00000002 +#define MAC_PCU_SLP_MIB3_PENDING_GET(x) (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB) +#define MAC_PCU_SLP_MIB3_PENDING_SET(x) (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK) +#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK 0x00000001 +#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB) +#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) + +#define MAC_PCU_SLP_BEACON_ADDRESS 0x0000010c +#define MAC_PCU_SLP_BEACON_OFFSET 0x0000010c +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MSB 24 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB 24 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK 0x01000000 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MSB 23 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB 0 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK 0x00ffffff +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) + +#define POWER_REG_ADDRESS 0x00000110 +#define POWER_REG_OFFSET 0x00000110 +#define POWER_REG_VLVL_MSB 11 +#define POWER_REG_VLVL_LSB 8 +#define POWER_REG_VLVL_MASK 0x00000f00 +#define POWER_REG_VLVL_GET(x) (((x) & POWER_REG_VLVL_MASK) >> POWER_REG_VLVL_LSB) +#define POWER_REG_VLVL_SET(x) (((x) << POWER_REG_VLVL_LSB) & POWER_REG_VLVL_MASK) +#define POWER_REG_CPU_INT_ENABLE_MSB 7 +#define POWER_REG_CPU_INT_ENABLE_LSB 7 +#define POWER_REG_CPU_INT_ENABLE_MASK 0x00000080 +#define POWER_REG_CPU_INT_ENABLE_GET(x) (((x) & POWER_REG_CPU_INT_ENABLE_MASK) >> POWER_REG_CPU_INT_ENABLE_LSB) +#define POWER_REG_CPU_INT_ENABLE_SET(x) (((x) << POWER_REG_CPU_INT_ENABLE_LSB) & POWER_REG_CPU_INT_ENABLE_MASK) +#define POWER_REG_WLAN_ISO_DIS_MSB 6 +#define POWER_REG_WLAN_ISO_DIS_LSB 6 +#define POWER_REG_WLAN_ISO_DIS_MASK 0x00000040 +#define POWER_REG_WLAN_ISO_DIS_GET(x) (((x) & POWER_REG_WLAN_ISO_DIS_MASK) >> POWER_REG_WLAN_ISO_DIS_LSB) +#define POWER_REG_WLAN_ISO_DIS_SET(x) (((x) << POWER_REG_WLAN_ISO_DIS_LSB) & POWER_REG_WLAN_ISO_DIS_MASK) +#define POWER_REG_WLAN_ISO_CNTL_MSB 5 +#define POWER_REG_WLAN_ISO_CNTL_LSB 5 +#define POWER_REG_WLAN_ISO_CNTL_MASK 0x00000020 +#define POWER_REG_WLAN_ISO_CNTL_GET(x) (((x) & POWER_REG_WLAN_ISO_CNTL_MASK) >> POWER_REG_WLAN_ISO_CNTL_LSB) +#define POWER_REG_WLAN_ISO_CNTL_SET(x) (((x) << POWER_REG_WLAN_ISO_CNTL_LSB) & POWER_REG_WLAN_ISO_CNTL_MASK) +#define POWER_REG_RADIO_PWD_EN_MSB 4 +#define POWER_REG_RADIO_PWD_EN_LSB 4 +#define POWER_REG_RADIO_PWD_EN_MASK 0x00000010 +#define POWER_REG_RADIO_PWD_EN_GET(x) (((x) & POWER_REG_RADIO_PWD_EN_MASK) >> POWER_REG_RADIO_PWD_EN_LSB) +#define POWER_REG_RADIO_PWD_EN_SET(x) (((x) << POWER_REG_RADIO_PWD_EN_LSB) & POWER_REG_RADIO_PWD_EN_MASK) +#define POWER_REG_SOC_SCALE_EN_MSB 3 +#define POWER_REG_SOC_SCALE_EN_LSB 3 +#define POWER_REG_SOC_SCALE_EN_MASK 0x00000008 +#define POWER_REG_SOC_SCALE_EN_GET(x) (((x) & POWER_REG_SOC_SCALE_EN_MASK) >> POWER_REG_SOC_SCALE_EN_LSB) +#define POWER_REG_SOC_SCALE_EN_SET(x) (((x) << POWER_REG_SOC_SCALE_EN_LSB) & POWER_REG_SOC_SCALE_EN_MASK) +#define POWER_REG_WLAN_SCALE_EN_MSB 2 +#define POWER_REG_WLAN_SCALE_EN_LSB 2 +#define POWER_REG_WLAN_SCALE_EN_MASK 0x00000004 +#define POWER_REG_WLAN_SCALE_EN_GET(x) (((x) & POWER_REG_WLAN_SCALE_EN_MASK) >> POWER_REG_WLAN_SCALE_EN_LSB) +#define POWER_REG_WLAN_SCALE_EN_SET(x) (((x) << POWER_REG_WLAN_SCALE_EN_LSB) & POWER_REG_WLAN_SCALE_EN_MASK) +#define POWER_REG_WLAN_PWD_EN_MSB 1 +#define POWER_REG_WLAN_PWD_EN_LSB 1 +#define POWER_REG_WLAN_PWD_EN_MASK 0x00000002 +#define POWER_REG_WLAN_PWD_EN_GET(x) (((x) & POWER_REG_WLAN_PWD_EN_MASK) >> POWER_REG_WLAN_PWD_EN_LSB) +#define POWER_REG_WLAN_PWD_EN_SET(x) (((x) << POWER_REG_WLAN_PWD_EN_LSB) & POWER_REG_WLAN_PWD_EN_MASK) +#define POWER_REG_POWER_EN_MSB 0 +#define POWER_REG_POWER_EN_LSB 0 +#define POWER_REG_POWER_EN_MASK 0x00000001 +#define POWER_REG_POWER_EN_GET(x) (((x) & POWER_REG_POWER_EN_MASK) >> POWER_REG_POWER_EN_LSB) +#define POWER_REG_POWER_EN_SET(x) (((x) << POWER_REG_POWER_EN_LSB) & POWER_REG_POWER_EN_MASK) + +#define CORE_CLK_CTRL_ADDRESS 0x00000114 +#define CORE_CLK_CTRL_OFFSET 0x00000114 +#define CORE_CLK_CTRL_DIV_MSB 2 +#define CORE_CLK_CTRL_DIV_LSB 0 +#define CORE_CLK_CTRL_DIV_MASK 0x00000007 +#define CORE_CLK_CTRL_DIV_GET(x) (((x) & CORE_CLK_CTRL_DIV_MASK) >> CORE_CLK_CTRL_DIV_LSB) +#define CORE_CLK_CTRL_DIV_SET(x) (((x) << CORE_CLK_CTRL_DIV_LSB) & CORE_CLK_CTRL_DIV_MASK) + +#define SDIO_SETUP_CIRCUIT_ADDRESS 0x00000120 +#define SDIO_SETUP_CIRCUIT_OFFSET 0x00000120 +#define SDIO_SETUP_CIRCUIT_VECTOR_MSB 7 +#define SDIO_SETUP_CIRCUIT_VECTOR_LSB 0 +#define SDIO_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define SDIO_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) >> SDIO_SETUP_CIRCUIT_VECTOR_LSB) +#define SDIO_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << SDIO_SETUP_CIRCUIT_VECTOR_LSB) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) + +#define SDIO_SETUP_CONFIG_ADDRESS 0x00000140 +#define SDIO_SETUP_CONFIG_OFFSET 0x00000140 +#define SDIO_SETUP_CONFIG_ENABLE_MSB 1 +#define SDIO_SETUP_CONFIG_ENABLE_LSB 1 +#define SDIO_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define SDIO_SETUP_CONFIG_ENABLE_GET(x) (((x) & SDIO_SETUP_CONFIG_ENABLE_MASK) >> SDIO_SETUP_CONFIG_ENABLE_LSB) +#define SDIO_SETUP_CONFIG_ENABLE_SET(x) (((x) << SDIO_SETUP_CONFIG_ENABLE_LSB) & SDIO_SETUP_CONFIG_ENABLE_MASK) +#define SDIO_SETUP_CONFIG_CLEAR_MSB 0 +#define SDIO_SETUP_CONFIG_CLEAR_LSB 0 +#define SDIO_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define SDIO_SETUP_CONFIG_CLEAR_GET(x) (((x) & SDIO_SETUP_CONFIG_CLEAR_MASK) >> SDIO_SETUP_CONFIG_CLEAR_LSB) +#define SDIO_SETUP_CONFIG_CLEAR_SET(x) (((x) << SDIO_SETUP_CONFIG_CLEAR_LSB) & SDIO_SETUP_CONFIG_CLEAR_MASK) + +#define CPU_SETUP_CONFIG_ADDRESS 0x00000144 +#define CPU_SETUP_CONFIG_OFFSET 0x00000144 +#define CPU_SETUP_CONFIG_ENABLE_MSB 1 +#define CPU_SETUP_CONFIG_ENABLE_LSB 1 +#define CPU_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define CPU_SETUP_CONFIG_ENABLE_GET(x) (((x) & CPU_SETUP_CONFIG_ENABLE_MASK) >> CPU_SETUP_CONFIG_ENABLE_LSB) +#define CPU_SETUP_CONFIG_ENABLE_SET(x) (((x) << CPU_SETUP_CONFIG_ENABLE_LSB) & CPU_SETUP_CONFIG_ENABLE_MASK) +#define CPU_SETUP_CONFIG_CLEAR_MSB 0 +#define CPU_SETUP_CONFIG_CLEAR_LSB 0 +#define CPU_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define CPU_SETUP_CONFIG_CLEAR_GET(x) (((x) & CPU_SETUP_CONFIG_CLEAR_MASK) >> CPU_SETUP_CONFIG_CLEAR_LSB) +#define CPU_SETUP_CONFIG_CLEAR_SET(x) (((x) << CPU_SETUP_CONFIG_CLEAR_LSB) & CPU_SETUP_CONFIG_CLEAR_MASK) + +#define CPU_SETUP_CIRCUIT_ADDRESS 0x00000160 +#define CPU_SETUP_CIRCUIT_OFFSET 0x00000160 +#define CPU_SETUP_CIRCUIT_VECTOR_MSB 7 +#define CPU_SETUP_CIRCUIT_VECTOR_LSB 0 +#define CPU_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define CPU_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & CPU_SETUP_CIRCUIT_VECTOR_MASK) >> CPU_SETUP_CIRCUIT_VECTOR_LSB) +#define CPU_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << CPU_SETUP_CIRCUIT_VECTOR_LSB) & CPU_SETUP_CIRCUIT_VECTOR_MASK) + +#define BB_SETUP_CONFIG_ADDRESS 0x00000180 +#define BB_SETUP_CONFIG_OFFSET 0x00000180 +#define BB_SETUP_CONFIG_ENABLE_MSB 1 +#define BB_SETUP_CONFIG_ENABLE_LSB 1 +#define BB_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define BB_SETUP_CONFIG_ENABLE_GET(x) (((x) & BB_SETUP_CONFIG_ENABLE_MASK) >> BB_SETUP_CONFIG_ENABLE_LSB) +#define BB_SETUP_CONFIG_ENABLE_SET(x) (((x) << BB_SETUP_CONFIG_ENABLE_LSB) & BB_SETUP_CONFIG_ENABLE_MASK) +#define BB_SETUP_CONFIG_CLEAR_MSB 0 +#define BB_SETUP_CONFIG_CLEAR_LSB 0 +#define BB_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define BB_SETUP_CONFIG_CLEAR_GET(x) (((x) & BB_SETUP_CONFIG_CLEAR_MASK) >> BB_SETUP_CONFIG_CLEAR_LSB) +#define BB_SETUP_CONFIG_CLEAR_SET(x) (((x) << BB_SETUP_CONFIG_CLEAR_LSB) & BB_SETUP_CONFIG_CLEAR_MASK) + +#define BB_SETUP_CIRCUIT_ADDRESS 0x000001a0 +#define BB_SETUP_CIRCUIT_OFFSET 0x000001a0 +#define BB_SETUP_CIRCUIT_VECTOR_MSB 7 +#define BB_SETUP_CIRCUIT_VECTOR_LSB 0 +#define BB_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define BB_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & BB_SETUP_CIRCUIT_VECTOR_MASK) >> BB_SETUP_CIRCUIT_VECTOR_LSB) +#define BB_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << BB_SETUP_CIRCUIT_VECTOR_LSB) & BB_SETUP_CIRCUIT_VECTOR_MASK) + +#define GPIO_WAKEUP_CONTROL_ADDRESS 0x000001c0 +#define GPIO_WAKEUP_CONTROL_OFFSET 0x000001c0 +#define GPIO_WAKEUP_CONTROL_ENABLE_MSB 0 +#define GPIO_WAKEUP_CONTROL_ENABLE_LSB 0 +#define GPIO_WAKEUP_CONTROL_ENABLE_MASK 0x00000001 +#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) (((x) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> GPIO_WAKEUP_CONTROL_ENABLE_LSB) +#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) (((x) << GPIO_WAKEUP_CONTROL_ENABLE_LSB) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct rtc_reg_reg_s { + volatile unsigned int reset_control; + volatile unsigned int xtal_control; + volatile unsigned int tcxo_detect; + volatile unsigned int xtal_test; + volatile unsigned int quadrature; + volatile unsigned int pll_control; + volatile unsigned int pll_settle; + volatile unsigned int xtal_settle; + volatile unsigned int cpu_clock; + volatile unsigned int clock_out; + volatile unsigned int clock_control; + volatile unsigned int bias_override; + volatile unsigned int wdt_control; + volatile unsigned int wdt_status; + volatile unsigned int wdt; + volatile unsigned int wdt_count; + volatile unsigned int wdt_reset; + volatile unsigned int int_status; + volatile unsigned int lf_timer0; + volatile unsigned int lf_timer_count0; + volatile unsigned int lf_timer_control0; + volatile unsigned int lf_timer_status0; + volatile unsigned int lf_timer1; + volatile unsigned int lf_timer_count1; + volatile unsigned int lf_timer_control1; + volatile unsigned int lf_timer_status1; + volatile unsigned int lf_timer2; + volatile unsigned int lf_timer_count2; + volatile unsigned int lf_timer_control2; + volatile unsigned int lf_timer_status2; + volatile unsigned int lf_timer3; + volatile unsigned int lf_timer_count3; + volatile unsigned int lf_timer_control3; + volatile unsigned int lf_timer_status3; + volatile unsigned int hf_timer; + volatile unsigned int hf_timer_count; + volatile unsigned int hf_lf_count; + volatile unsigned int hf_timer_control; + volatile unsigned int hf_timer_status; + volatile unsigned int rtc_control; + volatile unsigned int rtc_time; + volatile unsigned int rtc_date; + volatile unsigned int rtc_set_time; + volatile unsigned int rtc_set_date; + volatile unsigned int rtc_set_alarm; + volatile unsigned int rtc_config; + volatile unsigned int rtc_alarm_status; + volatile unsigned int uart_wakeup; + volatile unsigned int reset_cause; + volatile unsigned int system_sleep; + volatile unsigned int sdio_wrapper; + volatile unsigned int mac_sleep_control; + volatile unsigned int keep_awake; + volatile unsigned int lpo_cal_time; + volatile unsigned int lpo_init_dividend_int; + volatile unsigned int lpo_init_dividend_fraction; + volatile unsigned int lpo_cal; + volatile unsigned int lpo_cal_test_control; + volatile unsigned int lpo_cal_test_status; + volatile unsigned int chip_id; + volatile unsigned int derived_rtc_clk; + volatile unsigned int mac_pcu_slp32_mode; + volatile unsigned int mac_pcu_slp32_wake; + volatile unsigned int mac_pcu_slp32_inc; + volatile unsigned int mac_pcu_slp_mib1; + volatile unsigned int mac_pcu_slp_mib2; + volatile unsigned int mac_pcu_slp_mib3; + volatile unsigned int mac_pcu_slp_beacon; + volatile unsigned int power_reg; + volatile unsigned int core_clk_ctrl; + unsigned char pad0[8]; /* pad to 0x120 */ + volatile unsigned int sdio_setup_circuit[8]; + volatile unsigned int sdio_setup_config; + volatile unsigned int cpu_setup_config; + unsigned char pad1[24]; /* pad to 0x160 */ + volatile unsigned int cpu_setup_circuit[8]; + volatile unsigned int bb_setup_config; + unsigned char pad2[28]; /* pad to 0x1a0 */ + volatile unsigned int bb_setup_circuit[8]; + volatile unsigned int gpio_wakeup_control; +} rtc_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _RTC_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/si_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/si_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/si_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/si_reg.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,209 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _SI_REG_REG_H_ +#define _SI_REG_REG_H_ + +#define SI_CONFIG_ADDRESS 0x00000000 +#define SI_CONFIG_OFFSET 0x00000000 +#define SI_CONFIG_ERR_INT_MSB 19 +#define SI_CONFIG_ERR_INT_LSB 19 +#define SI_CONFIG_ERR_INT_MASK 0x00080000 +#define SI_CONFIG_ERR_INT_GET(x) (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB) +#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK) +#define SI_CONFIG_BIDIR_OD_DATA_MSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_LSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 +#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB) +#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK) +#define SI_CONFIG_I2C_MSB 16 +#define SI_CONFIG_I2C_LSB 16 +#define SI_CONFIG_I2C_MASK 0x00010000 +#define SI_CONFIG_I2C_GET(x) (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB) +#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) +#define SI_CONFIG_POS_SAMPLE_MSB 7 +#define SI_CONFIG_POS_SAMPLE_LSB 7 +#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 +#define SI_CONFIG_POS_SAMPLE_GET(x) (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB) +#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK) +#define SI_CONFIG_POS_DRIVE_MSB 6 +#define SI_CONFIG_POS_DRIVE_LSB 6 +#define SI_CONFIG_POS_DRIVE_MASK 0x00000040 +#define SI_CONFIG_POS_DRIVE_GET(x) (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB) +#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK) +#define SI_CONFIG_INACTIVE_DATA_MSB 5 +#define SI_CONFIG_INACTIVE_DATA_LSB 5 +#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 +#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB) +#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK) +#define SI_CONFIG_INACTIVE_CLK_MSB 4 +#define SI_CONFIG_INACTIVE_CLK_LSB 4 +#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 +#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB) +#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK) +#define SI_CONFIG_DIVIDER_MSB 3 +#define SI_CONFIG_DIVIDER_LSB 0 +#define SI_CONFIG_DIVIDER_MASK 0x0000000f +#define SI_CONFIG_DIVIDER_GET(x) (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB) +#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) + +#define SI_CS_ADDRESS 0x00000004 +#define SI_CS_OFFSET 0x00000004 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) +#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) +#define SI_CS_DONE_ERR_MSB 10 +#define SI_CS_DONE_ERR_LSB 10 +#define SI_CS_DONE_ERR_MASK 0x00000400 +#define SI_CS_DONE_ERR_GET(x) (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB) +#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK) +#define SI_CS_DONE_INT_MSB 9 +#define SI_CS_DONE_INT_LSB 9 +#define SI_CS_DONE_INT_MASK 0x00000200 +#define SI_CS_DONE_INT_GET(x) (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB) +#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK) +#define SI_CS_START_MSB 8 +#define SI_CS_START_LSB 8 +#define SI_CS_START_MASK 0x00000100 +#define SI_CS_START_GET(x) (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB) +#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) +#define SI_CS_RX_CNT_MSB 7 +#define SI_CS_RX_CNT_LSB 4 +#define SI_CS_RX_CNT_MASK 0x000000f0 +#define SI_CS_RX_CNT_GET(x) (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB) +#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) +#define SI_CS_TX_CNT_MSB 3 +#define SI_CS_TX_CNT_LSB 0 +#define SI_CS_TX_CNT_MASK 0x0000000f +#define SI_CS_TX_CNT_GET(x) (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB) +#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) + +#define SI_TX_DATA0_ADDRESS 0x00000008 +#define SI_TX_DATA0_OFFSET 0x00000008 +#define SI_TX_DATA0_DATA3_MSB 31 +#define SI_TX_DATA0_DATA3_LSB 24 +#define SI_TX_DATA0_DATA3_MASK 0xff000000 +#define SI_TX_DATA0_DATA3_GET(x) (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB) +#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK) +#define SI_TX_DATA0_DATA2_MSB 23 +#define SI_TX_DATA0_DATA2_LSB 16 +#define SI_TX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_TX_DATA0_DATA2_GET(x) (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB) +#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK) +#define SI_TX_DATA0_DATA1_MSB 15 +#define SI_TX_DATA0_DATA1_LSB 8 +#define SI_TX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_TX_DATA0_DATA1_GET(x) (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB) +#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK) +#define SI_TX_DATA0_DATA0_MSB 7 +#define SI_TX_DATA0_DATA0_LSB 0 +#define SI_TX_DATA0_DATA0_MASK 0x000000ff +#define SI_TX_DATA0_DATA0_GET(x) (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB) +#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK) + +#define SI_TX_DATA1_ADDRESS 0x0000000c +#define SI_TX_DATA1_OFFSET 0x0000000c +#define SI_TX_DATA1_DATA7_MSB 31 +#define SI_TX_DATA1_DATA7_LSB 24 +#define SI_TX_DATA1_DATA7_MASK 0xff000000 +#define SI_TX_DATA1_DATA7_GET(x) (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB) +#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK) +#define SI_TX_DATA1_DATA6_MSB 23 +#define SI_TX_DATA1_DATA6_LSB 16 +#define SI_TX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_TX_DATA1_DATA6_GET(x) (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB) +#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK) +#define SI_TX_DATA1_DATA5_MSB 15 +#define SI_TX_DATA1_DATA5_LSB 8 +#define SI_TX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_TX_DATA1_DATA5_GET(x) (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB) +#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK) +#define SI_TX_DATA1_DATA4_MSB 7 +#define SI_TX_DATA1_DATA4_LSB 0 +#define SI_TX_DATA1_DATA4_MASK 0x000000ff +#define SI_TX_DATA1_DATA4_GET(x) (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB) +#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK) + +#define SI_RX_DATA0_ADDRESS 0x00000010 +#define SI_RX_DATA0_OFFSET 0x00000010 +#define SI_RX_DATA0_DATA3_MSB 31 +#define SI_RX_DATA0_DATA3_LSB 24 +#define SI_RX_DATA0_DATA3_MASK 0xff000000 +#define SI_RX_DATA0_DATA3_GET(x) (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB) +#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK) +#define SI_RX_DATA0_DATA2_MSB 23 +#define SI_RX_DATA0_DATA2_LSB 16 +#define SI_RX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_RX_DATA0_DATA2_GET(x) (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB) +#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK) +#define SI_RX_DATA0_DATA1_MSB 15 +#define SI_RX_DATA0_DATA1_LSB 8 +#define SI_RX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_RX_DATA0_DATA1_GET(x) (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB) +#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK) +#define SI_RX_DATA0_DATA0_MSB 7 +#define SI_RX_DATA0_DATA0_LSB 0 +#define SI_RX_DATA0_DATA0_MASK 0x000000ff +#define SI_RX_DATA0_DATA0_GET(x) (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB) +#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK) + +#define SI_RX_DATA1_ADDRESS 0x00000014 +#define SI_RX_DATA1_OFFSET 0x00000014 +#define SI_RX_DATA1_DATA7_MSB 31 +#define SI_RX_DATA1_DATA7_LSB 24 +#define SI_RX_DATA1_DATA7_MASK 0xff000000 +#define SI_RX_DATA1_DATA7_GET(x) (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB) +#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK) +#define SI_RX_DATA1_DATA6_MSB 23 +#define SI_RX_DATA1_DATA6_LSB 16 +#define SI_RX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_RX_DATA1_DATA6_GET(x) (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB) +#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK) +#define SI_RX_DATA1_DATA5_MSB 15 +#define SI_RX_DATA1_DATA5_LSB 8 +#define SI_RX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_RX_DATA1_DATA5_GET(x) (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB) +#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK) +#define SI_RX_DATA1_DATA4_MSB 7 +#define SI_RX_DATA1_DATA4_LSB 0 +#define SI_RX_DATA1_DATA4_MASK 0x000000ff +#define SI_RX_DATA1_DATA4_GET(x) (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB) +#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct si_reg_reg_s { + volatile unsigned int si_config; + volatile unsigned int si_cs; + volatile unsigned int si_tx_data0; + volatile unsigned int si_tx_data1; + volatile unsigned int si_rx_data0; + volatile unsigned int si_rx_data1; +} si_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _SI_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/targaddrs.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/targaddrs.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/targaddrs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/targaddrs.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,202 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __TARGADDRS_H__ +#define __TARGADDRS_H__ +#if defined(AR6001) +#include "addrs.h" +#endif +#if defined(AR6002) +#include "addrs.h" +#endif + +/* + * AR6K option bits, to enable/disable various features. + * By default, all option bits are 0. + * These bits can be set in LOCAL_SCRATCH register 0. + */ +#define AR6K_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */ +#define AR6K_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */ +#define AR6K_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */ +#define AR6K_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */ +#define AR6K_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */ +#define AR6K_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */ +#define AR6K_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */ +#define AR6K_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */ + +/* + * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the + * host_interest structure. It must match the address of the _host_interest + * symbol (see linker script). + * + * Host Interest is shared between Host and Target in order to coordinate + * between the two, and is intended to remain constant (with additions only + * at the end) across software releases. + * + * All addresses are available here so that it's possible to + * write a single binary that works with all Target Types. + * May be used in assembler code as well as C. + */ +#define AR6001_HOST_INTEREST_ADDRESS 0x80000600 +#define AR6002_HOST_INTEREST_ADDRESS 0x00500400 +#define AR6003_HOST_INTEREST_ADDRESS 0x00540400 + + +#define HOST_INTEREST_MAX_SIZE 0x100 + +#if !defined(__ASSEMBLER__) +struct register_dump_s; +struct dbglog_hdr_s; + +/* + * These are items that the Host may need to access + * via BMI or via the Diagnostic Window. The position + * of items in this structure must remain constant + * across firmware revisions! + * + * Types for each item must be fixed size across + * target and host platforms. + * + * More items may be added at the end. + */ +struct host_interest_s { + /* + * Pointer to application-defined area, if any. + * Set by Target application during startup. + */ + A_UINT32 hi_app_host_interest; /* 0x00 */ + + /* Pointer to register dump area, valid after Target crash. */ + A_UINT32 hi_failure_state; /* 0x04 */ + + /* Pointer to debug logging header */ + A_UINT32 hi_dbglog_hdr; /* 0x08 */ + + /* Indicates whether or not flash is present on Target. + * NB: flash_is_present indicator is here not just + * because it might be of interest to the Host; but + * also because it's set early on by Target's startup + * asm code and we need it to have a special RAM address + * so that it doesn't get reinitialized with the rest + * of data. + */ + A_UINT32 hi_flash_is_present; /* 0x0c */ + + /* + * General-purpose flag bits, similar to AR6000_OPTION_* flags. + * Can be used by application rather than by OS. + */ + A_UINT32 hi_option_flag; /* 0x10 */ + + /* + * Boolean that determines whether or not to + * display messages on the serial port. + */ + A_UINT32 hi_serial_enable; /* 0x14 */ + + /* Start address of Flash DataSet index, if any */ + A_UINT32 hi_dset_list_head; /* 0x18 */ + + /* Override Target application start address */ + A_UINT32 hi_app_start; /* 0x1c */ + + /* Clock and voltage tuning */ + A_UINT32 hi_skip_clock_init; /* 0x20 */ + A_UINT32 hi_core_clock_setting; /* 0x24 */ + A_UINT32 hi_cpu_clock_setting; /* 0x28 */ + A_UINT32 hi_system_sleep_setting; /* 0x2c */ + A_UINT32 hi_xtal_control_setting; /* 0x30 */ + A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ + A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ + A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */ + A_UINT32 hi_clock_info; /* 0x40 */ + + /* + * Flash configuration overrides, used only + * when firmware is not executing from flash. + * (When using flash, modify the global variables + * with equivalent names.) + */ + A_UINT32 hi_bank0_addr_value; /* 0x44 */ + A_UINT32 hi_bank0_read_value; /* 0x48 */ + A_UINT32 hi_bank0_write_value; /* 0x4c */ + A_UINT32 hi_bank0_config_value; /* 0x50 */ + + /* Pointer to Board Data */ + A_UINT32 hi_board_data; /* 0x54 */ + A_UINT32 hi_board_data_initialized; /* 0x58 */ + + A_UINT32 hi_dset_RAM_index_table; /* 0x5c */ + + A_UINT32 hi_desired_baud_rate; /* 0x60 */ + A_UINT32 hi_dbglog_config; /* 0x64 */ + A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */ + A_UINT32 hi_mbox_io_block_sz; /* 0x6c */ + + A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */ + A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */ + + A_UINT32 hi_refclk_hz; /* 0x78 */ + A_UINT32 hi_ext_clk_detected; /* 0x7c */ +}; + +/* Bits defined in hi_option_flag */ +#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */ +#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */ +#define HI_OPTION_RELAY_DOT11_HDR 0x04 /*Relay Dot11 hdr to/from host */ + +/* 2 bits of hi_option_flag are used to represent 3 modes */ +#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */ +#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */ +#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */ + +/* Fw Mode Mask */ +#define HI_OPTION_FW_MODE_MASK 0x3 +#define HI_OPTION_FW_MODE_SHIFT 0x3 + +/* + * Intended for use by Host software, this macro returns the Target RAM + * address of any item in the host_interest structure. + * Example: target_addr = AR6001_HOST_INTEREST_ITEM_ADDRESS(hi_board_data); + */ +#define AR6001_HOST_INTEREST_ITEM_ADDRESS(item) \ + ((A_UINT32)&((((struct host_interest_s *)(AR6001_HOST_INTEREST_ADDRESS))->item))) + +#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \ + ((A_UINT32)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item))) + +#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \ + ((A_UINT32)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item))) + +/* Convert a Target virtual address into a Target physical address */ +#define AR6001_VTOP(vaddr) ((vaddr) & 0x0fffffff) +#define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff) +#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff) +#define TARG_VTOP(TargetType, vaddr) \ + (((TargetType) == TARGET_TYPE_AR6001) ? AR6001_VTOP(vaddr) : \ + (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : AR6003_VTOP(vaddr))) + + +#endif /* !__ASSEMBLER__ */ + +#endif /* __TARGADDRS_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/testcmd.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/testcmd.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/testcmd.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/testcmd.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,165 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2005 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef TESTCMD_H_ +#define TESTCMD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ZEROES_PATTERN = 0, + ONES_PATTERN, + REPEATING_10, + PN7_PATTERN, + PN9_PATTERN, + PN15_PATTERN +}TX_DATA_PATTERN; + +/* Continous tx + mode : TCMD_CONT_TX_OFF - Disabling continous tx + TCMD_CONT_TX_SINE - Enable continuous unmodulated tx + TCMD_CONT_TX_FRAME- Enable continuous modulated tx + freq : Channel freq in Mhz. (e.g 2412 for channel 1 in 11 g) +dataRate: 0 - 1 Mbps + 1 - 2 Mbps + 2 - 5.5 Mbps + 3 - 11 Mbps + 4 - 6 Mbps + 5 - 9 Mbps + 6 - 12 Mbps + 7 - 18 Mbps + 8 - 24 Mbps + 9 - 36 Mbps + 10 - 28 Mbps + 11 - 54 Mbps + txPwr: Tx power in dBm[5 -11] for unmod Tx, [5-14] for mod Tx +antenna: 1 - one antenna + 2 - two antenna +Note : Enable/disable continuous tx test cmd works only when target is awake. +*/ + +typedef enum { + TCMD_CONT_TX_OFF = 0, + TCMD_CONT_TX_SINE, + TCMD_CONT_TX_FRAME, + TCMD_CONT_TX_TX99, + TCMD_CONT_TX_TX100 +} TCMD_CONT_TX_MODE; + +typedef PREPACK struct { + A_UINT32 testCmdId; + A_UINT32 mode; + A_UINT32 freq; + A_UINT32 dataRate; + A_INT32 txPwr; + A_UINT32 antenna; + A_UINT32 enANI; + A_UINT32 scramblerOff; + A_UINT32 aifsn; + A_UINT16 pktSz; + A_UINT16 txPattern; +} POSTPACK TCMD_CONT_TX; + +#define TCMD_TXPATTERN_ZERONE 0x1 +#define TCMD_TXPATTERN_ZERONE_DIS_SCRAMBLE 0x2 + +/* Continuous Rx + act: TCMD_CONT_RX_PROMIS - promiscuous mode (accept all incoming frames) + TCMD_CONT_RX_FILTER - filter mode (accept only frames with dest + address equal specified + mac address (set via act =3) + TCMD_CONT_RX_REPORT off mode (disable cont rx mode and get the + report from the last cont + Rx test) + + TCMD_CONT_RX_SETMAC - set MacAddr mode (sets the MAC address for the + target. This Overrides + the default MAC address.) + +*/ +typedef enum { + TCMD_CONT_RX_PROMIS =0, + TCMD_CONT_RX_FILTER, + TCMD_CONT_RX_REPORT, + TCMD_CONT_RX_SETMAC, + TCMD_CONT_RX_SET_ANT_SWITCH_TABLE +} TCMD_CONT_RX_ACT; + +typedef PREPACK struct { + A_UINT32 testCmdId; + A_UINT32 act; + A_UINT32 enANI; + PREPACK union { + struct PREPACK TCMD_CONT_RX_PARA { + A_UINT32 freq; + A_UINT32 antenna; + } POSTPACK para; + struct PREPACK TCMD_CONT_RX_REPORT { + A_UINT32 totalPkt; + A_INT32 rssiInDBm; + A_UINT32 crcErrPkt; + A_UINT32 secErrPkt; + } POSTPACK report; + struct PREPACK TCMD_CONT_RX_MAC { + A_UCHAR addr[ATH_MAC_LEN]; + } POSTPACK mac; + struct PREPACK TCMD_CONT_RX_ANT_SWITCH_TABLE { + A_UINT32 antswitch1; + A_UINT32 antswitch2; + }POSTPACK antswitchtable; + } POSTPACK u; +} POSTPACK TCMD_CONT_RX; + +/* Force sleep/wake test cmd + mode: TCMD_PM_WAKEUP - Wakeup the target + TCMD_PM_SLEEP - Force the target to sleep. + */ +typedef enum { + TCMD_PM_WAKEUP = 1, /* be consistent with target */ + TCMD_PM_SLEEP +} TCMD_PM_MODE; + +typedef PREPACK struct { + A_UINT32 testCmdId; + A_UINT32 mode; +} POSTPACK TCMD_PM; + +typedef enum { + TCMD_CONT_TX_ID, + TCMD_CONT_RX_ID, + TCMD_PM_ID +} TCMD_ID; + +typedef PREPACK union { + TCMD_CONT_TX contTx; + TCMD_CONT_RX contRx; + TCMD_PM pm; +} POSTPACK TEST_CMD; + +#ifdef __cplusplus +} +#endif + +#endif /* TESTCMD_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/uart_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/uart_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/uart_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/uart_reg.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,350 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _UART_REG_REG_H_ +#define _UART_REG_REG_H_ + +#define RBR_ADDRESS 0x00000000 +#define RBR_OFFSET 0x00000000 +#define RBR_RBR_MSB 7 +#define RBR_RBR_LSB 0 +#define RBR_RBR_MASK 0x000000ff +#define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB) +#define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK) + +#define THR_ADDRESS 0x00000000 +#define THR_OFFSET 0x00000000 +#define THR_THR_MSB 7 +#define THR_THR_LSB 0 +#define THR_THR_MASK 0x000000ff +#define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_THR_LSB) +#define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK) + +#define DLL_ADDRESS 0x00000000 +#define DLL_OFFSET 0x00000000 +#define DLL_DLL_MSB 7 +#define DLL_DLL_LSB 0 +#define DLL_DLL_MASK 0x000000ff +#define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB) +#define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK) + +#define DLH_ADDRESS 0x00000004 +#define DLH_OFFSET 0x00000004 +#define DLH_DLH_MSB 7 +#define DLH_DLH_LSB 0 +#define DLH_DLH_MASK 0x000000ff +#define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB) +#define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK) + +#define IER_ADDRESS 0x00000004 +#define IER_OFFSET 0x00000004 +#define IER_EDDSI_MSB 3 +#define IER_EDDSI_LSB 3 +#define IER_EDDSI_MASK 0x00000008 +#define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB) +#define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK) +#define IER_ELSI_MSB 2 +#define IER_ELSI_LSB 2 +#define IER_ELSI_MASK 0x00000004 +#define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB) +#define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK) +#define IER_ETBEI_MSB 1 +#define IER_ETBEI_LSB 1 +#define IER_ETBEI_MASK 0x00000002 +#define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB) +#define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK) +#define IER_ERBFI_MSB 0 +#define IER_ERBFI_LSB 0 +#define IER_ERBFI_MASK 0x00000001 +#define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB) +#define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK) + +#define IIR_ADDRESS 0x00000008 +#define IIR_OFFSET 0x00000008 +#define IIR_FIFO_STATUS_MSB 7 +#define IIR_FIFO_STATUS_LSB 6 +#define IIR_FIFO_STATUS_MASK 0x000000c0 +#define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB) +#define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK) +#define IIR_IID_MSB 3 +#define IIR_IID_LSB 0 +#define IIR_IID_MASK 0x0000000f +#define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_IID_LSB) +#define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK) + +#define FCR_ADDRESS 0x00000008 +#define FCR_OFFSET 0x00000008 +#define FCR_RCVR_TRIG_MSB 7 +#define FCR_RCVR_TRIG_LSB 6 +#define FCR_RCVR_TRIG_MASK 0x000000c0 +#define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB) +#define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK) +#define FCR_DMA_MODE_MSB 3 +#define FCR_DMA_MODE_LSB 3 +#define FCR_DMA_MODE_MASK 0x00000008 +#define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB) +#define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK) +#define FCR_XMIT_FIFO_RST_MSB 2 +#define FCR_XMIT_FIFO_RST_LSB 2 +#define FCR_XMIT_FIFO_RST_MASK 0x00000004 +#define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB) +#define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK) +#define FCR_RCVR_FIFO_RST_MSB 1 +#define FCR_RCVR_FIFO_RST_LSB 1 +#define FCR_RCVR_FIFO_RST_MASK 0x00000002 +#define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB) +#define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK) +#define FCR_FIFO_EN_MSB 0 +#define FCR_FIFO_EN_LSB 0 +#define FCR_FIFO_EN_MASK 0x00000001 +#define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB) +#define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK) + +#define LCR_ADDRESS 0x0000000c +#define LCR_OFFSET 0x0000000c +#define LCR_DLAB_MSB 7 +#define LCR_DLAB_LSB 7 +#define LCR_DLAB_MASK 0x00000080 +#define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB) +#define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK) +#define LCR_BREAK_MSB 6 +#define LCR_BREAK_LSB 6 +#define LCR_BREAK_MASK 0x00000040 +#define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB) +#define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK) +#define LCR_EPS_MSB 4 +#define LCR_EPS_LSB 4 +#define LCR_EPS_MASK 0x00000010 +#define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB) +#define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK) +#define LCR_PEN_MSB 3 +#define LCR_PEN_LSB 3 +#define LCR_PEN_MASK 0x00000008 +#define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB) +#define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK) +#define LCR_STOP_MSB 2 +#define LCR_STOP_LSB 2 +#define LCR_STOP_MASK 0x00000004 +#define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB) +#define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK) +#define LCR_CLS_MSB 1 +#define LCR_CLS_LSB 0 +#define LCR_CLS_MASK 0x00000003 +#define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB) +#define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK) + +#define MCR_ADDRESS 0x00000010 +#define MCR_OFFSET 0x00000010 +#define MCR_LOOPBACK_MSB 5 +#define MCR_LOOPBACK_LSB 5 +#define MCR_LOOPBACK_MASK 0x00000020 +#define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB) +#define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK) +#define MCR_OUT2_MSB 3 +#define MCR_OUT2_LSB 3 +#define MCR_OUT2_MASK 0x00000008 +#define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB) +#define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK) +#define MCR_OUT1_MSB 2 +#define MCR_OUT1_LSB 2 +#define MCR_OUT1_MASK 0x00000004 +#define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB) +#define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK) +#define MCR_RTS_MSB 1 +#define MCR_RTS_LSB 1 +#define MCR_RTS_MASK 0x00000002 +#define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB) +#define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK) +#define MCR_DTR_MSB 0 +#define MCR_DTR_LSB 0 +#define MCR_DTR_MASK 0x00000001 +#define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB) +#define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK) + +#define LSR_ADDRESS 0x00000014 +#define LSR_OFFSET 0x00000014 +#define LSR_FERR_MSB 7 +#define LSR_FERR_LSB 7 +#define LSR_FERR_MASK 0x00000080 +#define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB) +#define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK) +#define LSR_TEMT_MSB 6 +#define LSR_TEMT_LSB 6 +#define LSR_TEMT_MASK 0x00000040 +#define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB) +#define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK) +#define LSR_THRE_MSB 5 +#define LSR_THRE_LSB 5 +#define LSR_THRE_MASK 0x00000020 +#define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB) +#define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK) +#define LSR_BI_MSB 4 +#define LSR_BI_LSB 4 +#define LSR_BI_MASK 0x00000010 +#define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_LSB) +#define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK) +#define LSR_FE_MSB 3 +#define LSR_FE_LSB 3 +#define LSR_FE_MASK 0x00000008 +#define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_LSB) +#define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK) +#define LSR_PE_MSB 2 +#define LSR_PE_LSB 2 +#define LSR_PE_MASK 0x00000004 +#define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_LSB) +#define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK) +#define LSR_OE_MSB 1 +#define LSR_OE_LSB 1 +#define LSR_OE_MASK 0x00000002 +#define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_LSB) +#define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK) +#define LSR_DR_MSB 0 +#define LSR_DR_LSB 0 +#define LSR_DR_MASK 0x00000001 +#define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_LSB) +#define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK) + +#define MSR_ADDRESS 0x00000018 +#define MSR_OFFSET 0x00000018 +#define MSR_DCD_MSB 7 +#define MSR_DCD_LSB 7 +#define MSR_DCD_MASK 0x00000080 +#define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB) +#define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK) +#define MSR_RI_MSB 6 +#define MSR_RI_LSB 6 +#define MSR_RI_MASK 0x00000040 +#define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_LSB) +#define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK) +#define MSR_DSR_MSB 5 +#define MSR_DSR_LSB 5 +#define MSR_DSR_MASK 0x00000020 +#define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB) +#define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK) +#define MSR_CTS_MSB 4 +#define MSR_CTS_LSB 4 +#define MSR_CTS_MASK 0x00000010 +#define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB) +#define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK) +#define MSR_DDCD_MSB 3 +#define MSR_DDCD_LSB 3 +#define MSR_DDCD_MASK 0x00000008 +#define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB) +#define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK) +#define MSR_TERI_MSB 2 +#define MSR_TERI_LSB 2 +#define MSR_TERI_MASK 0x00000004 +#define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB) +#define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK) +#define MSR_DDSR_MSB 1 +#define MSR_DDSR_LSB 1 +#define MSR_DDSR_MASK 0x00000002 +#define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB) +#define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK) +#define MSR_DCTS_MSB 0 +#define MSR_DCTS_LSB 0 +#define MSR_DCTS_MASK 0x00000001 +#define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB) +#define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK) + +#define SCR_ADDRESS 0x0000001c +#define SCR_OFFSET 0x0000001c +#define SCR_SCR_MSB 7 +#define SCR_SCR_LSB 0 +#define SCR_SCR_MASK 0x000000ff +#define SCR_SCR_GET(x) (((x) & SCR_SCR_MASK) >> SCR_SCR_LSB) +#define SCR_SCR_SET(x) (((x) << SCR_SCR_LSB) & SCR_SCR_MASK) + +#define SRBR_ADDRESS 0x00000020 +#define SRBR_OFFSET 0x00000020 +#define SRBR_SRBR_MSB 7 +#define SRBR_SRBR_LSB 0 +#define SRBR_SRBR_MASK 0x000000ff +#define SRBR_SRBR_GET(x) (((x) & SRBR_SRBR_MASK) >> SRBR_SRBR_LSB) +#define SRBR_SRBR_SET(x) (((x) << SRBR_SRBR_LSB) & SRBR_SRBR_MASK) + +#define SIIR_ADDRESS 0x00000028 +#define SIIR_OFFSET 0x00000028 +#define SIIR_SIIR_MSB 7 +#define SIIR_SIIR_LSB 0 +#define SIIR_SIIR_MASK 0x000000ff +#define SIIR_SIIR_GET(x) (((x) & SIIR_SIIR_MASK) >> SIIR_SIIR_LSB) +#define SIIR_SIIR_SET(x) (((x) << SIIR_SIIR_LSB) & SIIR_SIIR_MASK) + +#define MWR_ADDRESS 0x0000002c +#define MWR_OFFSET 0x0000002c +#define MWR_MWR_MSB 31 +#define MWR_MWR_LSB 0 +#define MWR_MWR_MASK 0xffffffff +#define MWR_MWR_GET(x) (((x) & MWR_MWR_MASK) >> MWR_MWR_LSB) +#define MWR_MWR_SET(x) (((x) << MWR_MWR_LSB) & MWR_MWR_MASK) + +#define SLSR_ADDRESS 0x00000034 +#define SLSR_OFFSET 0x00000034 +#define SLSR_SLSR_MSB 7 +#define SLSR_SLSR_LSB 0 +#define SLSR_SLSR_MASK 0x000000ff +#define SLSR_SLSR_GET(x) (((x) & SLSR_SLSR_MASK) >> SLSR_SLSR_LSB) +#define SLSR_SLSR_SET(x) (((x) << SLSR_SLSR_LSB) & SLSR_SLSR_MASK) + +#define SMSR_ADDRESS 0x00000038 +#define SMSR_OFFSET 0x00000038 +#define SMSR_SMSR_MSB 7 +#define SMSR_SMSR_LSB 0 +#define SMSR_SMSR_MASK 0x000000ff +#define SMSR_SMSR_GET(x) (((x) & SMSR_SMSR_MASK) >> SMSR_SMSR_LSB) +#define SMSR_SMSR_SET(x) (((x) << SMSR_SMSR_LSB) & SMSR_SMSR_MASK) + +#define MRR_ADDRESS 0x0000003c +#define MRR_OFFSET 0x0000003c +#define MRR_MRR_MSB 31 +#define MRR_MRR_LSB 0 +#define MRR_MRR_MASK 0xffffffff +#define MRR_MRR_GET(x) (((x) & MRR_MRR_MASK) >> MRR_MRR_LSB) +#define MRR_MRR_SET(x) (((x) << MRR_MRR_LSB) & MRR_MRR_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct uart_reg_reg_s { + volatile unsigned int rbr; + volatile unsigned int dlh; + volatile unsigned int iir; + volatile unsigned int lcr; + volatile unsigned int mcr; + volatile unsigned int lsr; + volatile unsigned int msr; + volatile unsigned int scr; + volatile unsigned int srbr; + unsigned char pad0[4]; /* pad to 0x28 */ + volatile unsigned int siir; + volatile unsigned int mwr; + unsigned char pad1[4]; /* pad to 0x34 */ + volatile unsigned int slsr; + volatile unsigned int smsr; + volatile unsigned int mrr; +} uart_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _UART_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/vmc_reg.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/vmc_reg.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/vmc_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/vmc_reg.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,99 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _VMC_REG_REG_H_ +#define _VMC_REG_REG_H_ + +#define MC_TCAM_VALID_ADDRESS 0x00000000 +#define MC_TCAM_VALID_OFFSET 0x00000000 +#define MC_TCAM_VALID_BIT_MSB 0 +#define MC_TCAM_VALID_BIT_LSB 0 +#define MC_TCAM_VALID_BIT_MASK 0x00000001 +#define MC_TCAM_VALID_BIT_GET(x) (((x) & MC_TCAM_VALID_BIT_MASK) >> MC_TCAM_VALID_BIT_LSB) +#define MC_TCAM_VALID_BIT_SET(x) (((x) << MC_TCAM_VALID_BIT_LSB) & MC_TCAM_VALID_BIT_MASK) + +#define MC_TCAM_MASK_ADDRESS 0x00000080 +#define MC_TCAM_MASK_OFFSET 0x00000080 +#define MC_TCAM_MASK_SIZE_MSB 2 +#define MC_TCAM_MASK_SIZE_LSB 0 +#define MC_TCAM_MASK_SIZE_MASK 0x00000007 +#define MC_TCAM_MASK_SIZE_GET(x) (((x) & MC_TCAM_MASK_SIZE_MASK) >> MC_TCAM_MASK_SIZE_LSB) +#define MC_TCAM_MASK_SIZE_SET(x) (((x) << MC_TCAM_MASK_SIZE_LSB) & MC_TCAM_MASK_SIZE_MASK) + +#define MC_TCAM_COMPARE_ADDRESS 0x00000100 +#define MC_TCAM_COMPARE_OFFSET 0x00000100 +#define MC_TCAM_COMPARE_KEY_MSB 21 +#define MC_TCAM_COMPARE_KEY_LSB 5 +#define MC_TCAM_COMPARE_KEY_MASK 0x003fffe0 +#define MC_TCAM_COMPARE_KEY_GET(x) (((x) & MC_TCAM_COMPARE_KEY_MASK) >> MC_TCAM_COMPARE_KEY_LSB) +#define MC_TCAM_COMPARE_KEY_SET(x) (((x) << MC_TCAM_COMPARE_KEY_LSB) & MC_TCAM_COMPARE_KEY_MASK) + +#define MC_TCAM_TARGET_ADDRESS 0x00000180 +#define MC_TCAM_TARGET_OFFSET 0x00000180 +#define MC_TCAM_TARGET_ADDR_MSB 21 +#define MC_TCAM_TARGET_ADDR_LSB 5 +#define MC_TCAM_TARGET_ADDR_MASK 0x003fffe0 +#define MC_TCAM_TARGET_ADDR_GET(x) (((x) & MC_TCAM_TARGET_ADDR_MASK) >> MC_TCAM_TARGET_ADDR_LSB) +#define MC_TCAM_TARGET_ADDR_SET(x) (((x) << MC_TCAM_TARGET_ADDR_LSB) & MC_TCAM_TARGET_ADDR_MASK) + +#define ADDR_ERROR_CONTROL_ADDRESS 0x00000200 +#define ADDR_ERROR_CONTROL_OFFSET 0x00000200 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) +#define ADDR_ERROR_CONTROL_ENABLE_MSB 0 +#define ADDR_ERROR_CONTROL_ENABLE_LSB 0 +#define ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001 +#define ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_ENABLE_LSB) +#define ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_ENABLE_LSB) & ADDR_ERROR_CONTROL_ENABLE_MASK) + +#define ADDR_ERROR_STATUS_ADDRESS 0x00000204 +#define ADDR_ERROR_STATUS_OFFSET 0x00000204 +#define ADDR_ERROR_STATUS_WRITE_MSB 25 +#define ADDR_ERROR_STATUS_WRITE_LSB 25 +#define ADDR_ERROR_STATUS_WRITE_MASK 0x02000000 +#define ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & ADDR_ERROR_STATUS_WRITE_MASK) >> ADDR_ERROR_STATUS_WRITE_LSB) +#define ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << ADDR_ERROR_STATUS_WRITE_LSB) & ADDR_ERROR_STATUS_WRITE_MASK) +#define ADDR_ERROR_STATUS_ADDRESS_MSB 24 +#define ADDR_ERROR_STATUS_ADDRESS_LSB 0 +#define ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff +#define ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & ADDR_ERROR_STATUS_ADDRESS_MASK) >> ADDR_ERROR_STATUS_ADDRESS_LSB) +#define ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << ADDR_ERROR_STATUS_ADDRESS_LSB) & ADDR_ERROR_STATUS_ADDRESS_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct vmc_reg_reg_s { + volatile unsigned int mc_tcam_valid[32]; + volatile unsigned int mc_tcam_mask[32]; + volatile unsigned int mc_tcam_compare[32]; + volatile unsigned int mc_tcam_target[32]; + volatile unsigned int addr_error_control; + volatile unsigned int addr_error_status; +} vmc_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _VMC_REG_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/wireless_ext.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wireless_ext.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/wireless_ext.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wireless_ext.c 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,2340 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// + * + */ + +#include "ar6000_drv.h" + +static A_UINT8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; +static void ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi); +extern unsigned int wmitimeout; +extern A_WAITQUEUE_HEAD arEvent; + + +#if WIRELESS_EXT > 14 +/* + * Encode a WPA or RSN information element as a custom + * element using the hostap format. + */ +static u_int +encode_ie(void *buf, size_t bufsize, + const u_int8_t *ie, size_t ielen, + const char *leader, size_t leader_len) +{ + u_int8_t *p; + int i; + + if (bufsize < leader_len) + return 0; + p = buf; + memcpy(p, leader, leader_len); + bufsize -= leader_len; + p += leader_len; + for (i = 0; i < ielen && bufsize > 2; i++) + { + p += sprintf(p, "%02x", ie[i]); + bufsize -= 2; + } + return (i == ielen ? p - (u_int8_t *)buf : 0); +} +#endif /* WIRELESS_EXT > 14 */ + +void +ar6000_scan_node(void *arg, bss_t *ni) +{ + struct iw_event iwe; +#if WIRELESS_EXT > 14 + char buf[600]; +#endif + struct ar_giwscan_param *param; + A_CHAR *current_ev; + A_CHAR *end_buf; + struct ieee80211_common_ie *cie; + A_CHAR *current_val; + A_INT32 j; + A_UINT32 rate_len, data_len = 0; + + param = (struct ar_giwscan_param *)arg; + + current_ev = param->current_ev; + end_buf = param->end_buf; + + cie = &ni->ni_cie; + + if ((end_buf - current_ev) > IW_EV_ADDR_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWAP; + iwe.u.ap_addr.sa_family = ARPHRD_ETHER; + A_MEMCPY(iwe.u.ap_addr.sa_data, ni->ni_macaddr, 6); + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + IW_EV_ADDR_LEN); + } + param->bytes_needed += IW_EV_ADDR_LEN; + + data_len = cie->ie_ssid[1] + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWESSID; + iwe.u.data.flags = 1; + iwe.u.data.length = cie->ie_ssid[1]; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + &cie->ie_ssid[2]); + } + param->bytes_needed += data_len; + + if (cie->ie_capInfo & (IEEE80211_CAPINFO_ESS|IEEE80211_CAPINFO_IBSS)) { + if ((end_buf - current_ev) > IW_EV_UINT_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWMODE; + iwe.u.mode = cie->ie_capInfo & IEEE80211_CAPINFO_ESS ? + IW_MODE_MASTER : IW_MODE_ADHOC; + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + IW_EV_UINT_LEN); + } + param->bytes_needed += IW_EV_UINT_LEN; + } + + if ((end_buf - current_ev) > IW_EV_FREQ_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWFREQ; + iwe.u.freq.m = cie->ie_chan * 100000; + iwe.u.freq.e = 1; + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + IW_EV_FREQ_LEN); + } + param->bytes_needed += IW_EV_FREQ_LEN; + + if ((end_buf - current_ev) > IW_EV_QUAL_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVQUAL; + ar6000_set_quality(&iwe.u.qual, ni->ni_snr); + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + IW_EV_QUAL_LEN); + } + param->bytes_needed += IW_EV_QUAL_LEN; + + if ((end_buf - current_ev) > IW_EV_POINT_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWENCODE; + if (cie->ie_capInfo & IEEE80211_CAPINFO_PRIVACY) { + iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; + } else { + iwe.u.data.flags = IW_ENCODE_DISABLED; + } + iwe.u.data.length = 0; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, ""); + } + param->bytes_needed += IW_EV_POINT_LEN; + + /* supported bit rate */ + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWRATE; + iwe.u.bitrate.fixed = 0; + iwe.u.bitrate.disabled = 0; + iwe.u.bitrate.value = 0; + current_val = current_ev + IW_EV_LCP_LEN; + param->bytes_needed += IW_EV_LCP_LEN; + + if (cie->ie_rates != NULL) { + rate_len = cie->ie_rates[1]; + data_len = (rate_len * (IW_EV_PARAM_LEN - IW_EV_LCP_LEN)); + if ((end_buf - current_ev) > data_len) + { + for (j = 0; j < rate_len; j++) { + unsigned char val; + val = cie->ie_rates[2 + j]; + iwe.u.bitrate.value = + (val >= 0x80)? ((val - 0x80) * 500000): (val * 500000); + current_val = iwe_stream_add_value( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, + current_val, + end_buf, + &iwe, + IW_EV_PARAM_LEN); + } + } + param->bytes_needed += data_len; + } + + if (cie->ie_xrates != NULL) { + rate_len = cie->ie_xrates[1]; + data_len = (rate_len * (IW_EV_PARAM_LEN - IW_EV_LCP_LEN)); + if ((end_buf - current_ev) > data_len) + { + for (j = 0; j < rate_len; j++) { + unsigned char val; + val = cie->ie_xrates[2 + j]; + iwe.u.bitrate.value = + (val >= 0x80)? ((val - 0x80) * 500000): (val * 500000); + current_val = iwe_stream_add_value( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, + current_val, + end_buf, + &iwe, + IW_EV_PARAM_LEN); + } + } + param->bytes_needed += data_len; + } + /* remove fixed header if no rates were added */ + if ((current_val - current_ev) > IW_EV_LCP_LEN) + current_ev = current_val; + +#if WIRELESS_EXT >= 18 + /* IE */ + if (cie->ie_wpa != NULL) { + data_len = cie->ie_wpa[1] + 2 + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVGENIE; + iwe.u.data.length = cie->ie_wpa[1] + 2; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, cie->ie_wpa); + } + param->bytes_needed += data_len; + } + + if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) { + data_len = cie->ie_rsn[1] + 2 + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVGENIE; + iwe.u.data.length = cie->ie_rsn[1] + 2; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, cie->ie_rsn); + } + param->bytes_needed += data_len; + } + +#endif /* WIRELESS_EXT >= 18 */ + + if ((end_buf - current_ev) > IW_EV_CHAR_LEN) + { + /* protocol */ + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWNAME; +#define CHAN_IS_11A(x) (!((x >= 2412) && (x <= 2484))) + if (CHAN_IS_11A(cie->ie_chan)) { + /* 11a */ + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11a"); + } else if ((cie->ie_erp) || (cie->ie_xrates)) { + /* 11g */ + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11g"); + } else { + /* 11b */ + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11b"); + } + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, IW_EV_CHAR_LEN); + } + param->bytes_needed += IW_EV_CHAR_LEN; + +#if WIRELESS_EXT > 14 + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = snprintf(buf, sizeof(buf), "bcn_int=%d", cie->ie_beaconInt); + data_len = iwe.u.data.length + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + param->bytes_needed += data_len; + +#if WIRELESS_EXT < 18 + if (cie->ie_wpa != NULL) { + static const char wpa_leader[] = "wpa_ie="; + data_len = (sizeof(wpa_leader) - 1) + ((cie->ie_wpa[1]+2) * 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wpa, + cie->ie_wpa[1]+2, + wpa_leader, sizeof(wpa_leader)-1); + + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + } + param->bytes_needed += data_len; + } + + if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) { + static const char rsn_leader[] = "rsn_ie="; + data_len = (sizeof(rsn_leader) - 1) + ((cie->ie_rsn[1]+2) * 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_rsn, + cie->ie_rsn[1]+2, + rsn_leader, sizeof(rsn_leader)-1); + + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + } + param->bytes_needed += data_len; + } +#endif /* WIRELESS_EXT < 18 */ + + if (cie->ie_wmm != NULL) { + static const char wmm_leader[] = "wmm_ie="; + data_len = (sizeof(wmm_leader) - 1) + ((cie->ie_wmm[1]+2) * 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wmm, + cie->ie_wmm[1]+2, + wmm_leader, sizeof(wmm_leader)-1); + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + } + param->bytes_needed += data_len; + } + + if (cie->ie_ath != NULL) { + static const char ath_leader[] = "ath_ie="; + data_len = (sizeof(ath_leader) - 1) + ((cie->ie_ath[1]+2) * 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_ath, + cie->ie_ath[1]+2, + ath_leader, sizeof(ath_leader)-1); + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + } + param->bytes_needed += data_len; + } + +#endif /* WIRELESS_EXT > 14 */ + +#if WIRELESS_EXT >= 18 + if (cie->ie_wsc != NULL) { + data_len = (cie->ie_wsc[1] + 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVGENIE; + iwe.u.data.length = cie->ie_wsc[1] + 2; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, cie->ie_wsc); + } + param->bytes_needed += data_len; + } +#endif /* WIRELESS_EXT >= 18 */ + + param->current_ev = current_ev; +} + +int +ar6000_ioctl_giwscan(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + struct ar_giwscan_param param; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + param.current_ev = extra; + param.end_buf = extra + data->length; + param.bytes_needed = 0; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param.info = info; +#endif + + /* Translate data to WE format */ + wmi_iterate_nodes(ar->arWmi, ar6000_scan_node, ¶m); + + /* check if bytes needed is greater than bytes consumed */ + if (param.bytes_needed > (param.current_ev - extra)) + { + /* Request one byte more than needed, because when "data->length" equals bytes_needed, + it is not possible to add the last event data as all iwe_stream_add_xxxxx() functions + checks whether (cur_ptr + ev_len) < end_ptr, due to this one more retry would happen*/ + data->length = param.bytes_needed + 1; + + return -E2BIG; + } + + return 0; +} + +extern int reconnect_flag; +/* SIOCSIWESSID */ +static int +ar6000_ioctl_siwessid(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *ssid) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_STATUS status; + A_UINT8 arNetworkType; + A_UINT8 prevMode = ar->arNetworkType; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + +#if defined(WIRELESS_EXT) + if (WIRELESS_EXT >= 20) { + data->length += 1; + } +#endif + + /* + * iwconfig passes a null terminated string with length including this + * so we need to account for this + */ + if (data->flags && (!data->length || (data->length == 1) || + ((data->length - 1) > sizeof(ar->arSsid)))) + { + /* + * ssid is invalid + */ + return -EINVAL; + } + + if (ar->arNextMode == AP_NETWORK) { + /* SSID change for AP network - Will take effect on commit */ + if(A_MEMCMP(ar->arSsid,ssid,32) != 0) { + ar->arSsidLen = data->length - 1; + A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen); + ar->ap_profile_flag = 1; /* There is a change in profile */ + } + return 0; + } else if(ar->arNetworkType == AP_NETWORK) { + A_UINT8 ctr; + struct sk_buff *skb; + + /* We are switching from AP to STA | IBSS mode, cleanup the AP state */ + for (ctr=0; ctr < AP_MAX_NUM_STA; ctr++) { + remove_sta(ar, ar->sta_list[ctr].mac, 0); + } + A_MUTEX_LOCK(&ar->mcastpsqLock); + while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) { + skb = A_NETBUF_DEQUEUE(&ar->mcastpsq); + A_NETBUF_FREE(skb); + } + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + } + + /* Added for bug 25178, return an IOCTL error instead of target returning + Illegal parameter error when either the BSSID or channel is missing + and we cannot scan during connect. + */ + if (data->flags) { + if (ar->arSkipScan == TRUE && + (ar->arChannelHint == 0 || + (!ar->arReqBssid[0] && !ar->arReqBssid[1] && !ar->arReqBssid[2] && + !ar->arReqBssid[3] && !ar->arReqBssid[4] && !ar->arReqBssid[5]))) + { + return -EINVAL; + } + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + if (ar->arTxPending[wmi_get_control_ep(ar->arWmi)]) { + /* + * sleep until the command queue drains + */ + wait_event_interruptible_timeout(arEvent, + ar->arTxPending[wmi_get_control_ep(ar->arWmi)] == 0, wmitimeout * HZ); + if (signal_pending(current)) { + return -EINTR; + } + } + + if (!data->flags) { + arNetworkType = ar->arNetworkType; + ar6000_init_profile_info(ar); + ar->arNetworkType = arNetworkType; + } + + /* Update the arNetworkType */ + ar->arNetworkType = ar->arNextMode; + + + if ((prevMode != AP_NETWORK) && ((ar->arSsidLen) || (!data->flags))) + { + if ((!data->flags) || + (A_MEMCMP(ar->arSsid, ssid, ar->arSsidLen) != 0) || + (ar->arSsidLen != (data->length - 1))) + { + /* + * SSID set previously or essid off has been issued. + * + * Disconnect Command is issued in two cases after wmi is ready + * (1) ssid is different from the previous setting + * (2) essid off has been issued + * + */ + if (ar->arWmiReady == TRUE) { + reconnect_flag = 0; + status = wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0); + status = wmi_disconnect_cmd(ar->arWmi); + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = 0; + if (ar->arSkipScan == FALSE) { + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + } + if (!data->flags) { + up(&ar->arSem); + return 0; + } + } else { + up(&ar->arSem); + } + } + else + { + /* + * SSID is same, so we assume profile hasn't changed. + * If the interface is up and wmi is ready, we issue + * a reconnect cmd. Issue a reconnect only we are already + * connected. + */ + if((ar->arConnected == TRUE) && (ar->arWmiReady == TRUE)) + { + reconnect_flag = TRUE; + status = wmi_reconnect_cmd(ar->arWmi,ar->arReqBssid, + ar->arChannelHint); + up(&ar->arSem); + if (status != A_OK) { + return -EIO; + } + return 0; + } + else{ + /* + * Dont return if connect is pending. + */ + if(!(ar->arConnectPending)) { + up(&ar->arSem); + return 0; + } + } + } + } + + ar->arSsidLen = data->length - 1; + A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen); + + /* The ssid length check prevents second "essid off" from the user, + to be treated as a connect cmd. The second "essid off" is ignored. + */ + if((ar->arWmiReady == TRUE) && (ar->arSsidLen > 0) ) + { + if((ADHOC_NETWORK != ar->arNetworkType) && + (NONE_AUTH==ar->arAuthMode) && + (WEP_CRYPT==ar->arPairwiseCrypto)) { + ar6000_install_static_wep_keys(ar); + } + + AR_DEBUG_PRINTF("Connect called with authmode %d dot11 auth %d"\ + " PW crypto %d PW crypto Len %d GRP crypto %d"\ + " GRP crypto Len %d\n", + ar->arAuthMode, ar->arDot11AuthMode, + ar->arPairwiseCrypto, ar->arPairwiseCryptoLen, + ar->arGroupCrypto, ar->arGroupCryptoLen); + reconnect_flag = 0; + status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType, + ar->arDot11AuthMode, ar->arAuthMode, + ar->arPairwiseCrypto, ar->arPairwiseCryptoLen, + ar->arGroupCrypto,ar->arGroupCryptoLen, + ar->arSsidLen, ar->arSsid, + ar->arReqBssid, ar->arChannelHint, + ar->arConnectCtrlFlags | CONNECT_IGNORE_WPAx_GROUP_CIPHER); + + + up(&ar->arSem); + + if (status != A_OK) { + return -EIO; + } + ar->arConnectPending = TRUE; + }else{ + up(&ar->arSem); + } + return 0; +} + +/* SIOCGIWESSID */ +static int +ar6000_ioctl_giwessid(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *essid) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (!ar->arSsidLen) { + return -EINVAL; + } + + data->flags = 1; + data->length = ar->arSsidLen; + A_MEMCPY(essid, ar->arSsid, ar->arSsidLen); + + return 0; +} + + +void ar6000_install_static_wep_keys(AR_SOFTC_T *ar) +{ + A_UINT8 index; + A_UINT8 keyUsage; + + for (index = WMI_MIN_KEY_INDEX; index <= WMI_MAX_KEY_INDEX; index++) { + if (ar->arWepKeyList[index].arKeyLen) { + keyUsage = GROUP_USAGE; + if (index == ar->arDefTxKeyIndex) { + keyUsage |= TX_USAGE; + } + wmi_addKey_cmd(ar->arWmi, + index, + WEP_CRYPT, + keyUsage, + ar->arWepKeyList[index].arKeyLen, + NULL, + ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL, NULL, + NO_SYNC_WMIFLAG); + } + } +} + +/* + * SIOCSIWRATE + */ +int +ar6000_ioctl_siwrate(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_UINT32 kbps; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (rrq->fixed) { + kbps = rrq->value / 1000; /* rrq->value is in bps */ + } else { + kbps = -1; /* -1 indicates auto rate */ + } + if(kbps != -1 && wmi_validate_bitrate(ar->arWmi, kbps) == A_EINVAL) + { + AR_DEBUG_PRINTF("BitRate is not Valid %d\n", kbps); + return -EINVAL; + } + ar->arBitRate = kbps; + if(ar->arWmiReady == TRUE) + { + if (wmi_set_bitrate_cmd(ar->arWmi, kbps, -1, -1) != A_OK) { + return -EINVAL; + } + } + return 0; +} + +/* + * SIOCGIWRATE + */ +int +ar6000_ioctl_giwrate(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + int ret = 0; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + if(ar->arWmiReady == TRUE) + { + ar->arBitRate = 0xFFFF; + if (wmi_get_bitrate_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + wait_event_interruptible_timeout(arEvent, ar->arBitRate != 0xFFFF, wmitimeout * HZ); + if (signal_pending(current)) { + ret = -EINTR; + } + } + /* If the interface is down or wmi is not ready or the target is not + connected - return the value stored in the device structure */ + if (!ret) { + if (ar->arBitRate == -1) { + rrq->fixed = TRUE; + rrq->value = 0; + } else { + rrq->value = ar->arBitRate * 1000; + } + } + + up(&ar->arSem); + + return ret; +} + +/* + * SIOCSIWTXPOW + */ +static int +ar6000_ioctl_siwtxpow(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_UINT8 dbM; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (rrq->disabled) { + return -EOPNOTSUPP; + } + + if (rrq->fixed) { + if (rrq->flags != IW_TXPOW_DBM) { + return -EOPNOTSUPP; + } + ar->arTxPwr= dbM = rrq->value; + ar->arTxPwrSet = TRUE; + } else { + ar->arTxPwr = dbM = 0; + ar->arTxPwrSet = FALSE; + } + if(ar->arWmiReady == TRUE) + { + AR_DEBUG_PRINTF("Set tx pwr cmd %d dbM\n", dbM); + wmi_set_txPwr_cmd(ar->arWmi, dbM); + } + return 0; +} + +/* + * SIOCGIWTXPOW + */ +int +ar6000_ioctl_giwtxpow(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + int ret = 0; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + if((ar->arWmiReady == TRUE) && (ar->arConnected == TRUE)) + { + ar->arTxPwr = 0; + + if (wmi_get_txPwr_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->arTxPwr != 0, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + } + /* If the interace is down or wmi is not ready or target is not connected + then return value stored in the device structure */ + + if (!ret) { + if (ar->arTxPwrSet == TRUE) { + rrq->fixed = TRUE; + } + rrq->value = ar->arTxPwr; + rrq->flags = IW_TXPOW_DBM; + // + // IWLIST need this flag to get TxPower + // + rrq->disabled = 0; + } + + up(&ar->arSem); + + return ret; +} + +/* + * SIOCSIWRETRY + * since iwconfig only provides us with one max retry value, we use it + * to apply to data frames of the BE traffic class. + */ +static int +ar6000_ioctl_siwretry(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (rrq->disabled) { + return -EOPNOTSUPP; + } + + if ((rrq->flags & IW_RETRY_TYPE) != IW_RETRY_LIMIT) { + return -EOPNOTSUPP; + } + + if ( !(rrq->value >= WMI_MIN_RETRIES) || !(rrq->value <= WMI_MAX_RETRIES)) { + return - EINVAL; + } + if(ar->arWmiReady == TRUE) + { + if (wmi_set_retry_limits_cmd(ar->arWmi, DATA_FRAMETYPE, WMM_AC_BE, + rrq->value, 0) != A_OK){ + return -EINVAL; + } + } + ar->arMaxRetries = rrq->value; + return 0; +} + +/* + * SIOCGIWRETRY + */ +static int +ar6000_ioctl_giwretry(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + rrq->disabled = 0; + switch (rrq->flags & IW_RETRY_TYPE) { + case IW_RETRY_LIFETIME: + return -EOPNOTSUPP; + break; + case IW_RETRY_LIMIT: + rrq->flags = IW_RETRY_LIMIT; + switch (rrq->flags & IW_RETRY_MODIFIER) { + case IW_RETRY_MIN: + rrq->flags |= IW_RETRY_MIN; + rrq->value = WMI_MIN_RETRIES; + break; + case IW_RETRY_MAX: + rrq->flags |= IW_RETRY_MAX; + rrq->value = ar->arMaxRetries; + break; + } + break; + } + return 0; +} + +/* + * SIOCSIWENCODE + */ +static int +ar6000_ioctl_siwencode(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, char *keybuf) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + int index; + A_INT32 auth = 0; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if(ar->arNextMode != AP_NETWORK) { + /* + * Static WEP Keys should be configured before setting the SSID + */ + if (ar->arSsid[0] && erq->length) { + return -EIO; + } + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + index = erq->flags & IW_ENCODE_INDEX; + + if (index && (((index - 1) < WMI_MIN_KEY_INDEX) || + ((index - 1) > WMI_MAX_KEY_INDEX))) + { + return -EIO; + } + + if (erq->flags & IW_ENCODE_DISABLED) { + /* + * Encryption disabled + */ + if (index) { + /* + * If key index was specified then clear the specified key + */ + index--; + A_MEMZERO(ar->arWepKeyList[index].arKey, + sizeof(ar->arWepKeyList[index].arKey)); + ar->arWepKeyList[index].arKeyLen = 0; + } + ar->arDot11AuthMode = OPEN_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arGroupCrypto = NONE_CRYPT; + ar->arAuthMode = NONE_AUTH; + } else { + /* + * Enabling WEP encryption + */ + if (index) { + index--; /* keyindex is off base 1 in iwconfig */ + } + + if (erq->flags & IW_ENCODE_OPEN) { + auth |= OPEN_AUTH; + ar->arDefTxKeyIndex = index; + } + if (erq->flags & IW_ENCODE_RESTRICTED) { + auth |= SHARED_AUTH; + } + + if(!auth) { + auth = ar->arDot11AuthMode; + } + + if (erq->length) { + if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(erq->length)) { + return -EIO; + } + + A_MEMZERO(ar->arWepKeyList[index].arKey, + sizeof(ar->arWepKeyList[index].arKey)); + A_MEMCPY(ar->arWepKeyList[index].arKey, keybuf, erq->length); + ar->arWepKeyList[index].arKeyLen = erq->length; + } else { + if (ar->arWepKeyList[index].arKeyLen == 0) { + return -EIO; + } + ar->arDefTxKeyIndex = index; + + if(ar->arSsidLen && ar->arWepKeyList[index].arKeyLen) { + wmi_addKey_cmd(ar->arWmi, + index, + WEP_CRYPT, + GROUP_USAGE | TX_USAGE, + ar->arWepKeyList[index].arKeyLen, + NULL, + ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL, NULL, + NO_SYNC_WMIFLAG); + } + } + + ar->arPairwiseCrypto = WEP_CRYPT; + ar->arGroupCrypto = WEP_CRYPT; + ar->arDot11AuthMode = auth; + ar->arAuthMode = NONE_AUTH; + } + + if(ar->arNextMode != AP_NETWORK) { + /* + * profile has changed. Erase ssid to signal change + */ + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + } + ar->ap_profile_flag = 1; /* There is a change in profile */ + return 0; +} + +static int +ar6000_ioctl_giwencode(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, char *key) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_UINT8 keyIndex; + struct ar_wep_key *wk; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arPairwiseCrypto == NONE_CRYPT) { + erq->length = 0; + erq->flags = IW_ENCODE_DISABLED; + } else { + /* get the keyIndex */ + keyIndex = erq->flags & IW_ENCODE_INDEX; + if (0 == keyIndex) { + keyIndex = ar->arDefTxKeyIndex; + } else if ((keyIndex - 1 < WMI_MIN_KEY_INDEX) || + (keyIndex - 1 > WMI_MAX_KEY_INDEX)) + { + keyIndex = WMI_MIN_KEY_INDEX; + } else { + keyIndex--; + } + erq->flags = keyIndex + 1; + erq->flags |= IW_ENCODE_ENABLED; + wk = &ar->arWepKeyList[keyIndex]; + if (erq->length > wk->arKeyLen) { + erq->length = wk->arKeyLen; + } + if (wk->arKeyLen) { + A_MEMCPY(key, wk->arKey, erq->length); + } + if (ar->arDot11AuthMode & OPEN_AUTH) { + erq->flags |= IW_ENCODE_OPEN; + } + if (ar->arDot11AuthMode & SHARED_AUTH) { + erq->flags |= IW_ENCODE_RESTRICTED; + } + } + + return 0; +} + +static int ar6000_ioctl_siwpower(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ +#if defined(WIRELESS_EXT) && WIRELESS_EXT > 20 + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + WMI_POWER_MODE power_mode; + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (wrqu->power.disabled) + power_mode = MAX_PERF_POWER; + else + power_mode = REC_POWER; + + if (wmi_powermode_cmd(ar->arWmi, power_mode) < 0) + return -EIO; +#endif + return 0; +} + +static int ar6000_ioctl_giwpower(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ +#if defined(WIRELESS_EXT) && WIRELESS_EXT > 20 + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + if(!ar->arWmi){ + return -EIO; + } + return wmi_get_power_mode_cmd(ar->arWmi); +#else + return 0; +#endif +} + +static int ar6000_ioctl_siwgenie(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *dwrq, + char *extra) +{ + /* The target does that for us */ + return 0; +} + +static int ar6000_ioctl_giwgenie(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *dwrq, + char *extra) +{ + return 0; +} + +static int ar6000_ioctl_siwauth(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *param, + char *extra) +{ +#if defined(WIRELESS_EXT) && WIRELESS_EXT > 20 + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + int reset = 0; + + switch (param->flags & IW_AUTH_INDEX) { + case IW_AUTH_WPA_VERSION: + if (param->value & IW_AUTH_WPA_VERSION_DISABLED) { + ar->arAuthMode = NONE_AUTH; + } + if (param->value & IW_AUTH_WPA_VERSION_WPA) { + ar->arAuthMode = WPA_AUTH; + } + if (param->value & IW_AUTH_WPA_VERSION_WPA2) { + ar->arAuthMode = WPA2_AUTH; + } + + reset = 1; + break; + case IW_AUTH_CIPHER_PAIRWISE: + if (param->value & IW_AUTH_CIPHER_NONE) { + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arPairwiseCryptoLen = 0; + } + if (param->value & IW_AUTH_CIPHER_WEP40) { + ar->arPairwiseCrypto = WEP_CRYPT; + ar->arPairwiseCryptoLen = IEEE80211_WEP_KEYLEN; + } + if (param->value & IW_AUTH_CIPHER_TKIP) { + ar->arPairwiseCrypto = TKIP_CRYPT; + ar->arPairwiseCryptoLen = 0; + } + if (param->value & IW_AUTH_CIPHER_CCMP) { + ar->arPairwiseCrypto = AES_CRYPT; + ar->arPairwiseCryptoLen = 0; + } + if (param->value & IW_AUTH_CIPHER_WEP104) { + ar->arPairwiseCrypto = WEP_CRYPT; + ar->arPairwiseCryptoLen = IEEE80211_WEP104_KEYLEN; + } + + reset = 1; + break; + case IW_AUTH_CIPHER_GROUP: + if (param->value & IW_AUTH_CIPHER_NONE) { + ar->arGroupCrypto = NONE_CRYPT; + ar->arGroupCryptoLen = 0; + } + if (param->value & IW_AUTH_CIPHER_WEP40) { + ar->arGroupCrypto = WEP_CRYPT; + ar->arGroupCryptoLen = IEEE80211_WEP_KEYLEN; + } + if (param->value & IW_AUTH_CIPHER_TKIP) { + ar->arGroupCrypto = TKIP_CRYPT; + ar->arGroupCryptoLen = 0; + } + if (param->value & IW_AUTH_CIPHER_CCMP) { + ar->arGroupCrypto = AES_CRYPT; + ar->arGroupCryptoLen = 0; + } + if (param->value & IW_AUTH_CIPHER_WEP104) { + ar->arGroupCrypto = WEP_CRYPT; + ar->arGroupCryptoLen = IEEE80211_WEP104_KEYLEN; + } + + reset = 1; + break; + case IW_AUTH_KEY_MGMT: + if (param->value & IW_AUTH_KEY_MGMT_PSK) { + if (ar->arAuthMode == WPA_AUTH) { + ar->arAuthMode = WPA_PSK_AUTH; + } else if (ar->arAuthMode == WPA2_AUTH) { + ar->arAuthMode = WPA2_PSK_AUTH; + } + + reset = 1; + } else if (!(param->value & IW_AUTH_KEY_MGMT_802_1X)) { + ar->arAuthMode = NONE_AUTH; + } + break; + + case IW_AUTH_TKIP_COUNTERMEASURES: + if (ar->arWmiReady == FALSE) { + return -EIO; + } + wmi_set_tkip_countermeasures_cmd(ar->arWmi, param->value); + break; + + case IW_AUTH_DROP_UNENCRYPTED: + break; + + case IW_AUTH_80211_AUTH_ALG: + ar->arDot11AuthMode = 0; + if (param->value & IW_AUTH_ALG_OPEN_SYSTEM) { + ar->arDot11AuthMode |= OPEN_AUTH; + } + if (param->value & IW_AUTH_ALG_SHARED_KEY) { + ar->arDot11AuthMode |= SHARED_AUTH; + } + if (param->value & IW_AUTH_ALG_LEAP) { + ar->arDot11AuthMode = LEAP_AUTH; + ar->arPairwiseCrypto = WEP_CRYPT; + ar->arGroupCrypto = WEP_CRYPT; + } + reset = 1; + break; + + case IW_AUTH_WPA_ENABLED: + reset = 1; + break; + + case IW_AUTH_RX_UNENCRYPTED_EAPOL: + break; + + case IW_AUTH_PRIVACY_INVOKED: + break; + + default: + printk("%s(): Unknown flag 0x%x\n", __FUNCTION__, param->flags); + return -EOPNOTSUPP; + } + + if (reset) + memset(ar->arSsid, 0, sizeof(ar->arSsid)); +#endif + return 0; +} + +static int ar6000_ioctl_giwauth(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *dwrq, + char *extra) +{ + return 0; +} + +static int ar6000_ioctl_siwencodeext(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, + char *extra) +{ + +#if defined(WIRELESS_EXT) && WIRELESS_EXT > 20 + + struct iw_point *erq = &wrqu->encoding; + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + A_INT32 index; + struct iw_encode_ext *ext; + KEY_USAGE keyUsage; + A_INT32 keyLen; + A_UINT8 *keyData; + A_UINT8 keyRsc[8]; + A_STATUS status; + CRYPTO_TYPE keyType; +#ifdef USER_KEYS + struct ieee80211req_key ik; +#endif /* USER_KEYS */ + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + +#ifdef USER_KEYS + ar->user_saved_keys.keyOk = FALSE; +#endif /* USER_KEYS */ + + index = erq->flags & IW_ENCODE_INDEX; + + if (index && (((index - 1) < WMI_MIN_KEY_INDEX) || + ((index - 1) > WMI_MAX_KEY_INDEX))) + { + return -EIO; + } + + ext = (struct iw_encode_ext *)extra; + if (erq->flags & IW_ENCODE_DISABLED) { + /* + * Encryption disabled + */ + if (index) { + /* + * If key index was specified then clear the specified key + */ + index--; + A_MEMZERO(ar->arWepKeyList[index].arKey, + sizeof(ar->arWepKeyList[index].arKey)); + ar->arWepKeyList[index].arKeyLen = 0; + } + } else { + /* + * Enabling WEP encryption + */ + if (index) { + index--; /* keyindex is off base 1 in iwconfig */ + } + + keyUsage = 0; + keyLen = erq->length - sizeof(struct iw_encode_ext); + + if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) { + keyUsage = TX_USAGE; + ar->arDefTxKeyIndex = index; + // Just setting the key index + if (keyLen == 0) { + return 0; + } + } + + if (keyLen <= 0) { + return -EIO; + } + + /* key follows iw_encode_ext */ + keyData = (A_UINT8 *)(ext + 1); + + switch (ext->alg) { + case IW_ENCODE_ALG_WEP: + keyType = WEP_CRYPT; +#ifdef USER_KEYS + ik.ik_type = IEEE80211_CIPHER_WEP; +#endif /* USER_KEYS */ + if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(keyLen)) { + return -EIO; + } + + /* Check whether it is static wep. + * Allow to set if we called wmi_disconnect() */ + if (!ar->arSsid[0] && ar->arSsidLen==0) { + A_MEMZERO(ar->arWepKeyList[index].arKey, + sizeof(ar->arWepKeyList[index].arKey)); + A_MEMCPY(ar->arWepKeyList[index].arKey, keyData, keyLen); + ar->arWepKeyList[index].arKeyLen = keyLen; + + return 0; + } + break; + case IW_ENCODE_ALG_TKIP: + keyType = TKIP_CRYPT; +#ifdef USER_KEYS + ik.ik_type = IEEE80211_CIPHER_TKIP; +#endif /* USER_KEYS */ + break; + case IW_ENCODE_ALG_CCMP: + keyType = AES_CRYPT; +#ifdef USER_KEYS + ik.ik_type = IEEE80211_CIPHER_AES_CCM; +#endif /* USER_KEYS */ + break; +#ifdef WAPI_ENABLE + case IW_ENCODE_ALG_SM4: + if (ar->arWapiEnable) { + return ar6000_set_wapi_key(dev, info, erq, extra); + } else { + return -EIO; + } +#endif + default: + return -EIO; + } + + + if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) { + keyUsage |= GROUP_USAGE; + } else { + keyUsage |= PAIRWISE_USAGE; + } + + if (ext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) { + A_MEMCPY(keyRsc, ext->rx_seq, sizeof(keyRsc)); + } else { + A_MEMZERO(keyRsc, sizeof(keyRsc)); + } + + if (((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)) && + (GROUP_USAGE & keyUsage)) + { + A_UNTIMEOUT(&ar->disconnect_timer); + } +#if 0 + if(ar->arConnected == TRUE && ar->arPrevCrypto == NONE_CRYPT) + { + if(keyLen) + { + ar->arWepKeyList[index].arKeyLen = keyLen; + A_MEMZERO(ar->arWepKeyList[index].arKey,sizeof(ar->arWepKeyList[index].arKey)); + A_MEMCPY(ar->arWepKeyList[index].arKey, keyData, keyLen); + } + } +#endif + else + { + status = wmi_addKey_cmd(ar->arWmi, index, keyType, keyUsage, + keyLen, keyRsc, + keyData, KEY_OP_INIT_VAL, + ext->addr.sa_data, + SYNC_BOTH_WMIFLAG); + if (status != A_OK) { + return -EIO; + } + } + +#ifdef USER_KEYS + ik.ik_keyix = index; + ik.ik_keylen = keyLen; + memcpy(ik.ik_keydata, keyData, keyLen); + memcpy(&ik.ik_keyrsc, keyRsc, sizeof(keyRsc)); + memcpy(ik.ik_macaddr, ext->addr.sa_data, ETH_ALEN); + if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) { + memcpy(&ar->user_saved_keys.bcast_ik, &ik, + sizeof(struct ieee80211req_key)); + } else { + memcpy(&ar->user_saved_keys.ucast_ik, &ik, + sizeof(struct ieee80211req_key)); + } + ar->user_saved_keys.keyOk = TRUE; +#endif /* USER_KEYS */ + } +#endif + return 0; +} + + +static int ar6000_ioctl_giwencodeext(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *dwrq, + char *extra) +{ + return 0; +} + + +/* + * SIOCGIWNAME + */ +int +ar6000_ioctl_giwname(struct net_device *dev, + struct iw_request_info *info, + char *name, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + switch (ar->arPhyCapability) { + case (WMI_11A_CAPABILITY): + strncpy(name, "AR6000 802.11a", IFNAMSIZ); + break; + case (WMI_11G_CAPABILITY): + strncpy(name, "AR6000 802.11g", IFNAMSIZ); + break; + case (WMI_11AG_CAPABILITY): + strncpy(name, "AR6000 802.11ag", IFNAMSIZ); + break; + default: + strncpy(name, "AR6000 802.11", IFNAMSIZ); + break; + } + + return 0; +} + +/* + * SIOCSIWFREQ + */ +int +ar6000_ioctl_siwfreq(struct net_device *dev, + struct iw_request_info *info, + struct iw_freq *freq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + /* + * We support limiting the channels via wmiconfig. + * + * We use this command to configure the channel hint for the connect cmd + * so it is possible the target will end up connecting to a different + * channel. + */ + if (freq->e > 1) { + return -EINVAL; + } else if (freq->e == 1) { + ar->arChannelHint = freq->m / 100000; + } else { + ar->arChannelHint = wlan_ieee2freq(freq->m); + } + + ar->ap_profile_flag = 1; /* There is a change in profile */ + + A_PRINTF("channel hint set to %d\n", ar->arChannelHint); + return 0; +} + +/* + * SIOCGIWFREQ + */ +int +ar6000_ioctl_giwfreq(struct net_device *dev, + struct iw_request_info *info, + struct iw_freq *freq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arConnected != TRUE) { + return -EINVAL; + } + if (ar->arNetworkType == AP_NETWORK) { + freq->m = ar->arChannelHint * 100000; + } else { + freq->m = ar->arBssChannel * 100000; + } + + freq->e = 1; + + return 0; +} + +/* + * SIOCSIWMODE + */ +int +ar6000_ioctl_siwmode(struct net_device *dev, + struct iw_request_info *info, + __u32 *mode, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + switch (*mode) { + case IW_MODE_INFRA: + ar->arNextMode = INFRA_NETWORK; + break; + case IW_MODE_ADHOC: + ar->arNextMode = ADHOC_NETWORK; + break; + case IW_MODE_MASTER: + ar->arNextMode = AP_NETWORK; + break; + default: + return -EINVAL; + } + + /* clear all shared parameters between AP and STA|IBSS modes when we + * switch between them. Switch between STA & IBSS modes does'nt clear + * the shared profile. This is as per the original design for switching + * between STA & IBSS. + */ + if (ar->arNetworkType == AP_NETWORK || ar->arNextMode == AP_NETWORK) { + ar->arDot11AuthMode = OPEN_AUTH; + ar->arAuthMode = NONE_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arPairwiseCryptoLen = 0; + ar->arGroupCrypto = NONE_CRYPT; + ar->arGroupCryptoLen = 0; + ar->arChannelHint = 0; + ar->arBssChannel = 0; + A_MEMZERO(ar->arBssid, sizeof(ar->arBssid)); + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = 0; + } + + /* SSID has to be cleared to trigger a profile change while switching + * between STA & IBSS modes having the same SSID + */ + if (ar->arNetworkType != ar->arNextMode) { + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + } + + return 0; +} + +/* + * SIOCGIWMODE + */ +int +ar6000_ioctl_giwmode(struct net_device *dev, + struct iw_request_info *info, + __u32 *mode, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + switch (ar->arNetworkType) { + case INFRA_NETWORK: + *mode = IW_MODE_INFRA; + break; + case ADHOC_NETWORK: + *mode = IW_MODE_ADHOC; + break; + case AP_NETWORK: + *mode = IW_MODE_MASTER; + break; + default: + return -EIO; + } + return 0; +} + +/* + * SIOCSIWSENS + */ +int +ar6000_ioctl_siwsens(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *sens, char *extra) +{ + return 0; +} + +/* + * SIOCGIWSENS + */ +int +ar6000_ioctl_giwsens(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *sens, char *extra) +{ + sens->value = 0; + sens->fixed = 1; + + return 0; +} + +/* + * SIOCGIWRANGE + */ +int +ar6000_ioctl_giwrange(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + struct iw_range *range = (struct iw_range *) extra; + int i, ret = 0; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + ar->arNumChannels = -1; + A_MEMZERO(ar->arChannelList, sizeof (ar->arChannelList)); + + if (wmi_get_channelList_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->arNumChannels != -1, wmitimeout * HZ); + + if (signal_pending(current)) { + up(&ar->arSem); + return -EINTR; + } + + data->length = sizeof(struct iw_range); + A_MEMZERO(range, sizeof(struct iw_range)); + + range->txpower_capa = 0; + + range->min_pmp = 1 * 1024; + range->max_pmp = 65535 * 1024; + range->min_pmt = 1 * 1024; + range->max_pmt = 1000 * 1024; + range->pmp_flags = IW_POWER_PERIOD; + range->pmt_flags = IW_POWER_TIMEOUT; + range->pm_capa = 0; + + range->we_version_compiled = WIRELESS_EXT; + range->we_version_source = 13; + + range->retry_capa = IW_RETRY_LIMIT; + range->retry_flags = IW_RETRY_LIMIT; + range->min_retry = 0; + range->max_retry = 255; + + range->num_frequency = range->num_channels = ar->arNumChannels; + for (i = 0; i < ar->arNumChannels; i++) { + range->freq[i].i = wlan_freq2ieee(ar->arChannelList[i]); + range->freq[i].m = ar->arChannelList[i] * 100000; + range->freq[i].e = 1; + /* + * Linux supports max of 32 channels, bail out once you + * reach the max. + */ + if (i == IW_MAX_FREQUENCIES) { + break; + } + } + + /* Max quality is max field value minus noise floor */ + range->max_qual.qual = 0xff - 161; + + /* + * In order to use dBm measurements, 'level' must be lower + * than any possible measurement (see iw_print_stats() in + * wireless tools). It's unclear how this is meant to be + * done, but setting zero in these values forces dBm and + * the actual numbers are not used. + */ + range->max_qual.level = 0; + range->max_qual.noise = 0; + + range->sensitivity = 3; + + range->max_encoding_tokens = 4; + /* XXX query driver to find out supported key sizes */ + range->num_encoding_sizes = 3; + range->encoding_size[0] = 5; /* 40-bit */ + range->encoding_size[1] = 13; /* 104-bit */ + range->encoding_size[2] = 16; /* 128-bit */ + + range->num_bitrates = 0; + + /* estimated maximum TCP throughput values (bps) */ + range->throughput = 22000000; + + range->min_rts = 0; + range->max_rts = 2347; + range->min_frag = 256; + range->max_frag = 2346; + + up(&ar->arSem); + + return ret; +} + + +/* + * SIOCSIWAP + * This ioctl is used to set the desired bssid for the connect command. + */ +int +ar6000_ioctl_siwap(struct net_device *dev, + struct iw_request_info *info, + struct sockaddr *ap_addr, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ap_addr->sa_family != ARPHRD_ETHER) { + return -EIO; + } + + if (A_MEMCMP(&ap_addr->sa_data, bcast_mac, AR6000_ETH_ADDR_LEN) == 0) { + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + } else { + A_MEMCPY(ar->arReqBssid, &ap_addr->sa_data, sizeof(ar->arReqBssid)); + } + + return 0; +} + +/* + * SIOCGIWAP + */ +int +ar6000_ioctl_giwap(struct net_device *dev, + struct iw_request_info *info, + struct sockaddr *ap_addr, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arConnected != TRUE) { + return -EINVAL; + } + + if (ar->arNetworkType == AP_NETWORK) { + return -EINVAL; + } + + A_MEMCPY(&ap_addr->sa_data, ar->arBssid, sizeof(ar->arBssid)); + ap_addr->sa_family = ARPHRD_ETHER; + + return 0; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,13) +/* + * SIOCSIWMLME + */ +int +ar6000_ioctl_siwmlme(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arNetworkType == AP_NETWORK) { + return -EINVAL; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + if (data->pointer && data->length == sizeof(struct iw_mlme)) { + + A_UINT8 arNetworkType; + struct iw_mlme mlme; + + if (copy_from_user(&mlme, data->pointer, sizeof(struct iw_mlme))) + return -EIO; + + switch (mlme.cmd) { + + case IW_MLME_DEAUTH: + /* ignore it */ + break; + + case IW_MLME_DISASSOC: + /* + * Atheros code used to return EINVAL if it wasn't connected. + * This is broken because it is possible for us to be + * disconnected and the firmware is attempting to + * connect. We need to call the disconnect cmd to stop it + */ + wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0); + arNetworkType = ar->arNetworkType; + ar6000_init_profile_info(ar); + ar->arNetworkType = arNetworkType; + reconnect_flag = 0; + wmi_disconnect_cmd(ar->arWmi); + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = 0; + if (ar->arSkipScan == FALSE) { + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + } + break; + + case IW_MLME_AUTH: + /* fall through */ + case IW_MLME_ASSOC: + /* fall through */ + default: + up(&ar->arSem); + return -EOPNOTSUPP; + } + } + + up(&ar->arSem); + return 0; +} +#endif /* LINUX_VERSION_CODE */ + +/* + * SIOCGIWAPLIST + */ +int +ar6000_ioctl_iwaplist(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + return -EIO; /* for now */ +} + +/* + * SIOCSIWSCAN + */ +int +ar6000_ioctl_siwscan(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ +#define ACT_DWELLTIME_DEFAULT 105 +#define HOME_TXDRAIN_TIME 100 +#define SCAN_INT HOME_TXDRAIN_TIME + ACT_DWELLTIME_DEFAULT + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + int ret = 0; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + /* We ask for everything from the target */ + if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != A_OK) { + printk("Couldn't set filtering\n"); + ret = -EIO; + } + +#if WIRELESS_EXT >= 18 + if (data->pointer && (data->length == sizeof(struct iw_scan_req))) + { + if ((data->flags & IW_SCAN_THIS_ESSID) == IW_SCAN_THIS_ESSID) + { + struct iw_scan_req req; + if (copy_from_user(&req, data->pointer, sizeof(struct iw_scan_req))) + return -EIO; + if (wmi_probedSsid_cmd(ar->arWmi, 0, SPECIFIC_SSID_FLAG, req.essid_len, req.essid) != A_OK) + return -EIO; + } + else + { + if (wmi_probedSsid_cmd(ar->arWmi, 0, ANY_SSID_FLAG, 0, NULL) != A_OK) + return -EIO; + } + } + else + { + if (wmi_probedSsid_cmd(ar->arWmi, 0, ANY_SSID_FLAG, 0, NULL) != A_OK) + return -EIO; + } +#endif + +#define LAB126_FORCE_SCAN_INT 250 /* msec */ + if (wmi_startscan_cmd(ar->arWmi, WMI_LONG_SCAN, TRUE, FALSE, \ + 0, LAB126_FORCE_SCAN_INT, 0, NULL) != A_OK) { + ret = -EIO; + } + + return ret; +#undef ACT_DWELLTIME_DEFAULT +#undef HOME_TXDRAIN_TIME +#undef SCAN_INT +} + + +/* + * Units are in db above the noise floor. That means the + * rssi values reported in the tx/rx descriptors in the + * driver are the SNR expressed in db. + * + * If you assume that the noise floor is -95, which is an + * excellent assumption 99.5 % of the time, then you can + * derive the absolute signal level (i.e. -95 + rssi). + * There are some other slight factors to take into account + * depending on whether the rssi measurement is from 11b, + * 11g, or 11a. These differences are at most 2db and + * can be documented. + * + * NB: various calculations are based on the orinoco/wavelan + * drivers for compatibility + */ +static void +ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi) +{ + if (rssi < 0) { + iq->qual = 0; + } else { + iq->qual = rssi; + } + + /* NB: max is 94 because noise is hardcoded to 161 */ + if (iq->qual > 94) + iq->qual = 94; + + iq->noise = 161; /* -95dBm */ + iq->level = iq->noise + iq->qual; + iq->updated = 7; +} + + +int +ar6000_ioctl_siwcommit(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + AR_DEBUG_PRINTF("AP: SSID %s freq %d authmode %d dot11 auth %d"\ + " PW crypto %d GRP crypto %d\n", + ar->arSsid, ar->arChannelHint, + ar->arAuthMode, ar->arDot11AuthMode, + ar->arPairwiseCrypto, ar->arGroupCrypto); + + ar6000_ap_mode_profile_commit(ar); + + /* if there is a profile switch from STA|IBSS mode to AP mode, + * update the host driver association state for the STA|IBSS mode. + */ + if (ar->arNetworkType != AP_NETWORK && ar->arNextMode == AP_NETWORK) { + ar->arConnectPending = FALSE; + ar->arConnected = FALSE; + /* Stop getting pkts from upper stack */ + netif_stop_queue(ar->arNetDev); + A_MEMZERO(ar->arBssid, sizeof(ar->arBssid)); + ar->arBssChannel = 0; + ar->arBeaconInterval = 0; + + /* Flush the Tx queues */ + ar6000_TxDataCleanup(ar); + + /* Start getting pkts from upper stack */ + netif_wake_queue(ar->arNetDev); + } + + return 0; +} + +/* Structures to export the Wireless Handlers */ +static const iw_handler ath_handlers[] = { + (iw_handler) ar6000_ioctl_siwcommit, /* SIOCSIWCOMMIT */ + (iw_handler) ar6000_ioctl_giwname, /* SIOCGIWNAME */ + (iw_handler) NULL, /* SIOCSIWNWID */ + (iw_handler) NULL, /* SIOCGIWNWID */ + (iw_handler) ar6000_ioctl_siwfreq, /* SIOCSIWFREQ */ + (iw_handler) ar6000_ioctl_giwfreq, /* SIOCGIWFREQ */ + (iw_handler) ar6000_ioctl_siwmode, /* SIOCSIWMODE */ + (iw_handler) ar6000_ioctl_giwmode, /* SIOCGIWMODE */ + (iw_handler) ar6000_ioctl_siwsens, /* SIOCSIWSENS */ + (iw_handler) ar6000_ioctl_giwsens, /* SIOCGIWSENS */ + (iw_handler) NULL /* not _used */, /* SIOCSIWRANGE */ + (iw_handler) ar6000_ioctl_giwrange, /* SIOCGIWRANGE */ + (iw_handler) NULL /* not used */, /* SIOCSIWPRIV */ + (iw_handler) NULL /* kernel code */, /* SIOCGIWPRIV */ + (iw_handler) NULL /* not used */, /* SIOCSIWSTATS */ + (iw_handler) NULL /* kernel code */, /* SIOCGIWSTATS */ + (iw_handler) NULL, /* SIOCSIWSPY */ + (iw_handler) NULL, /* SIOCGIWSPY */ + (iw_handler) NULL, /* SIOCSIWTHRSPY */ + (iw_handler) NULL, /* SIOCGIWTHRSPY */ + (iw_handler) ar6000_ioctl_siwap, /* SIOCSIWAP */ + (iw_handler) ar6000_ioctl_giwap, /* SIOCGIWAP */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,13) + (iw_handler) ar6000_ioctl_siwmlme, /* SIOCSIWMLME */ +#else + (iw_handler) NULL, /* -- hole -- */ +#endif /* LINUX_VERSION_CODE */ + (iw_handler) ar6000_ioctl_iwaplist, /* SIOCGIWAPLIST */ + (iw_handler) ar6000_ioctl_siwscan, /* SIOCSIWSCAN */ + (iw_handler) ar6000_ioctl_giwscan, /* SIOCGIWSCAN */ + (iw_handler) ar6000_ioctl_siwessid, /* SIOCSIWESSID */ + (iw_handler) ar6000_ioctl_giwessid, /* SIOCGIWESSID */ + (iw_handler) NULL, /* SIOCSIWNICKN */ + (iw_handler) NULL, /* SIOCGIWNICKN */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) ar6000_ioctl_siwrate, /* SIOCSIWRATE */ + (iw_handler) ar6000_ioctl_giwrate, /* SIOCGIWRATE */ + (iw_handler) NULL, /* SIOCSIWRTS */ + (iw_handler) NULL, /* SIOCGIWRTS */ + (iw_handler) NULL, /* SIOCSIWFRAG */ + (iw_handler) NULL, /* SIOCGIWFRAG */ + (iw_handler) ar6000_ioctl_siwtxpow, /* SIOCSIWTXPOW */ + (iw_handler) ar6000_ioctl_giwtxpow, /* SIOCGIWTXPOW */ + (iw_handler) ar6000_ioctl_siwretry, /* SIOCSIWRETRY */ + (iw_handler) ar6000_ioctl_giwretry, /* SIOCGIWRETRY */ + (iw_handler) ar6000_ioctl_siwencode, /* SIOCSIWENCODE */ + (iw_handler) ar6000_ioctl_giwencode, /* SIOCGIWENCODE */ + (iw_handler) ar6000_ioctl_siwpower, /* SIOCSIWPOWER */ + (iw_handler) ar6000_ioctl_giwpower, /* SIOCGIWPOWER */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) ar6000_ioctl_siwgenie, /* SIOCSIWGENIE */ + (iw_handler) ar6000_ioctl_giwgenie, /* SIOCGIWGENIE */ + (iw_handler) ar6000_ioctl_siwauth, /* SIOCSIWAUTH */ + (iw_handler) ar6000_ioctl_giwauth, /* SIOCGIWAUTH */ + (iw_handler) ar6000_ioctl_siwencodeext,/* SIOCSIWENCODEEXT */ + (iw_handler) ar6000_ioctl_giwencodeext,/* SIOCGIWENCODEEXT */ + (iw_handler) NULL, /* SIOCSIWPMKSA */ +}; + +struct iw_handler_def ath_iw_handler_def = { + .standard = (iw_handler *)ath_handlers, + .num_standard = ARRAY_SIZE(ath_handlers), + .private = NULL, + .num_private = 0, +}; diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/wlan_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wlan_api.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/wlan_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wlan_api.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,119 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the API for the host wlan module +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HOST_WLAN_API_H_ +#define _HOST_WLAN_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +struct ieee80211_node_table; +struct ieee80211_frame; + +struct ieee80211_common_ie { + A_UINT16 ie_chan; + A_UINT8 *ie_tstamp; + A_UINT8 *ie_ssid; + A_UINT8 *ie_rates; + A_UINT8 *ie_xrates; + A_UINT8 *ie_country; + A_UINT8 *ie_wpa; + A_UINT8 *ie_rsn; + A_UINT8 *ie_wmm; + A_UINT8 *ie_ath; + A_UINT16 ie_capInfo; + A_UINT16 ie_beaconInt; + A_UINT8 *ie_tim; + A_UINT8 *ie_chswitch; + A_UINT8 ie_erp; + A_UINT8 *ie_wsc; +#ifdef PYXIS_ADHOC + A_UINT8 *ie_pyxis; +#endif +#ifdef WAPI_ENABLE + A_UINT8 *ie_wapi; +#endif +}; + +typedef struct bss { + A_UINT8 ni_macaddr[6]; + A_UINT8 ni_snr; + A_INT16 ni_rssi; + struct bss *ni_list_next; + struct bss *ni_list_prev; + struct bss *ni_hash_next; + struct bss *ni_hash_prev; + struct ieee80211_common_ie ni_cie; + A_UINT8 *ni_buf; + struct ieee80211_node_table *ni_table; + A_UINT32 ni_refcnt; + int ni_scangen; + + A_UINT32 ni_tstamp; +#ifdef OS_ROAM_MANAGEMENT + A_UINT32 ni_si_gen; +#endif +} bss_t; + +typedef void wlan_node_iter_func(void *arg, bss_t *); + +bss_t *wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size); +void wlan_node_free(bss_t *ni); +void wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni, + const A_UINT8 *macaddr); +bss_t *wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr); +void wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni); +void wlan_free_allnodes(struct ieee80211_node_table *nt); +void wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f, + void *arg); + +void wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt); +void wlan_node_table_reset(struct ieee80211_node_table *nt); +void wlan_node_table_cleanup(struct ieee80211_node_table *nt); + +A_STATUS wlan_parse_beacon(A_UINT8 *buf, int framelen, + struct ieee80211_common_ie *cie); + +A_UINT16 wlan_ieee2freq(int chan); +A_UINT32 wlan_freq2ieee(A_UINT16 freq); + +void wlan_set_nodeage(struct ieee80211_node_table *nt, A_UINT32 nodeAge); + + +bss_t * +wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID); + +void +wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni); + +bss_t *wlan_node_remove(struct ieee80211_node_table *nt, A_UINT8 *bssid); + +#ifdef __cplusplus +} +#endif + +#endif /* _HOST_WLAN_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/wlan_defs.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wlan_defs.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/wlan_defs.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wlan_defs.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,55 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef __WLAN_DEFS_H__ +#define __WLAN_DEFS_H__ + +/* + * This file contains WLAN definitions that may be used across both + * Host and Target software. + */ + +typedef enum { + MODE_11A = 0, /* 11a Mode */ + MODE_11G = 1, /* 11b/g Mode */ + MODE_11B = 2, /* 11b Mode */ + MODE_11GONLY = 3, /* 11g only Mode */ +#ifdef SUPPORT_11N + MODE_11A_HT20 = 4, /* 11a HT20 mode */ + MODE_11G_HT20 = 5, /* 11g HT20 mode */ + MODE_11A_HT40 = 6, /* 11a HT40 mode */ + MODE_11G_HT40 = 7, /* 11g HT40 mode */ + MODE_UNKNOWN = 8, + MODE_MAX = 8 +#else + MODE_UNKNOWN = 4, + MODE_MAX = 4 +#endif +} WLAN_PHY_MODE; + +typedef enum { + WLAN_11A_CAPABILITY = 1, + WLAN_11G_CAPABILITY = 2, + WLAN_11AG_CAPABILITY = 3, +}WLAN_CAPABILITY; + +#endif /* __ATHDEFS_H__ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/wlan_dset.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wlan_dset.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/wlan_dset.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wlan_dset.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,34 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __WLAN_DSET_H__ +#define __WKAN_DSET_H__ + +typedef PREPACK struct wow_config_dset { + + A_UINT8 valid_dset; + A_UINT8 gpio_enable; + A_UINT16 gpio_pin; +} POSTPACK WOW_CONFIG_DSET; + +#endif diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/wlan_node.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wlan_node.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/wlan_node.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wlan_node.c 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,470 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// IEEE 802.11 node handling support. +// +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include +#include +#include "htc.h" +#include "htc_api.h" +#include +#include +#include +#include +#include + +static void wlan_node_timeout(A_ATH_TIMER arg); + +static bss_t * _ieee80211_find_node (struct ieee80211_node_table *nt, + const A_UINT8 *macaddr); + +bss_t * +wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size) +{ + bss_t *ni; + + ni = A_MALLOC_NOWAIT(sizeof(bss_t)); + + if (ni != NULL) { + if (wh_size) + { + ni->ni_buf = A_MALLOC_NOWAIT(wh_size); + if (ni->ni_buf == NULL) { + A_FREE(ni); + ni = NULL; + return ni; + } + } + } else { + return ni; + } + + /* Make sure our lists are clean */ + ni->ni_list_next = NULL; + ni->ni_list_prev = NULL; + ni->ni_hash_next = NULL; + ni->ni_hash_prev = NULL; + + // + // ni_scangen never initialized before and during suspend/resume of winmobile, + // that some junk has been stored in this, due to this scan list didn't properly updated + // + ni->ni_scangen = 0; + +#ifdef OS_ROAM_MANAGEMENT + ni->ni_si_gen = 0; +#endif + + return ni; +} + +void +wlan_node_free(bss_t *ni) +{ + if (ni->ni_buf != NULL) { + A_FREE(ni->ni_buf); + } + A_FREE(ni); +} + +void +wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni, + const A_UINT8 *macaddr) +{ + int hash; + A_UINT32 timeoutValue = 0; + + A_MEMCPY(ni->ni_macaddr, macaddr, IEEE80211_ADDR_LEN); + hash = IEEE80211_NODE_HASH (macaddr); + ieee80211_node_initref (ni); /* mark referenced */ + + timeoutValue = nt->nt_nodeAge; + + ni->ni_tstamp = A_GET_MS (timeoutValue); + + IEEE80211_NODE_LOCK_BH(nt); + + /* Insert at the end of the node list */ + ni->ni_list_next = NULL; + ni->ni_list_prev = nt->nt_node_last; + if(nt->nt_node_last != NULL) + { + nt->nt_node_last->ni_list_next = ni; + } + nt->nt_node_last = ni; + if(nt->nt_node_first == NULL) + { + nt->nt_node_first = ni; + } + + /* Insert into the hash list i.e. the bucket */ + if((ni->ni_hash_next = nt->nt_hash[hash]) != NULL) + { + nt->nt_hash[hash]->ni_hash_prev = ni; + } + ni->ni_hash_prev = NULL; + nt->nt_hash[hash] = ni; + + if (!nt->isTimerArmed) { + A_TIMEOUT_MS(&nt->nt_inact_timer, timeoutValue, 0); + nt->isTimerArmed = TRUE; + } + + IEEE80211_NODE_UNLOCK_BH(nt); +} + +static bss_t * +_ieee80211_find_node(struct ieee80211_node_table *nt, + const A_UINT8 *macaddr) +{ + bss_t *ni; + int hash; + + IEEE80211_NODE_LOCK_ASSERT(nt); + + hash = IEEE80211_NODE_HASH(macaddr); + for(ni = nt->nt_hash[hash]; ni; ni = ni->ni_hash_next) { + if (IEEE80211_ADDR_EQ(ni->ni_macaddr, macaddr)) { + ieee80211_node_incref(ni); /* mark referenced */ + return ni; + } + } + return NULL; +} + +bss_t * +wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr) +{ + bss_t *ni; + + IEEE80211_NODE_LOCK(nt); + ni = _ieee80211_find_node(nt, macaddr); + IEEE80211_NODE_UNLOCK(nt); + return ni; +} + +/* + * Reclaim a node. If this is the last reference count then + * do the normal free work. Otherwise remove it from the node + * table and mark it gone by clearing the back-reference. + */ +void +wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni) +{ + IEEE80211_NODE_LOCK(nt); + + if(ni->ni_list_prev == NULL) + { + /* First in list so fix the list head */ + nt->nt_node_first = ni->ni_list_next; + } + else + { + ni->ni_list_prev->ni_list_next = ni->ni_list_next; + } + + if(ni->ni_list_next == NULL) + { + /* Last in list so fix list tail */ + nt->nt_node_last = ni->ni_list_prev; + } + else + { + ni->ni_list_next->ni_list_prev = ni->ni_list_prev; + } + + if(ni->ni_hash_prev == NULL) + { + /* First in list so fix the list head */ + int hash; + hash = IEEE80211_NODE_HASH(ni->ni_macaddr); + nt->nt_hash[hash] = ni->ni_hash_next; + } + else + { + ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next; + } + + if(ni->ni_hash_next != NULL) + { + ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev; + } + wlan_node_free(ni); + + IEEE80211_NODE_UNLOCK(nt); +} + +static void +wlan_node_dec_free(bss_t *ni) +{ + if (ieee80211_node_dectestref(ni)) { + wlan_node_free(ni); + } +} + +void +wlan_free_allnodes(struct ieee80211_node_table *nt) +{ + bss_t *ni; + + while ((ni = nt->nt_node_first) != NULL) { + wlan_node_reclaim(nt, ni); + } +} + +void +wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f, + void *arg) +{ + bss_t *ni; + A_UINT32 gen; + + gen = ++nt->nt_scangen; + + IEEE80211_NODE_LOCK(nt); + for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) { + if (ni->ni_scangen != gen) { + ni->ni_scangen = gen; + (void) ieee80211_node_incref(ni); + (*f)(arg, ni); + wlan_node_dec_free(ni); + } + } + IEEE80211_NODE_UNLOCK(nt); +} + +/* + * Node table support. + */ +void +wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt) +{ + int i; + + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN, ("node table = 0x%x\n", (A_UINT32)nt)); + IEEE80211_NODE_LOCK_INIT(nt); + + nt->nt_node_first = nt->nt_node_last = NULL; + for(i = 0; i < IEEE80211_NODE_HASHSIZE; i++) + { + nt->nt_hash[i] = NULL; + } + + A_INIT_TIMER(&nt->nt_inact_timer, wlan_node_timeout, nt); + nt->isTimerArmed = FALSE; + nt->nt_wmip = wmip; + nt->nt_nodeAge = WLAN_NODE_INACT_TIMEOUT_MSEC; + + // + // nt_scangen never initialized before and during suspend/resume of winmobile, + // that some junk has been stored in this, due to this scan list didn't properly updated + // + nt->nt_scangen = 0; + +#ifdef OS_ROAM_MANAGEMENT + nt->nt_si_gen = 0; +#endif +} + +void +wlan_set_nodeage(struct ieee80211_node_table *nt, A_UINT32 nodeAge) +{ + nt->nt_nodeAge = nodeAge; + return; +} +static void +wlan_node_timeout (A_ATH_TIMER arg) +{ + struct ieee80211_node_table *nt = (struct ieee80211_node_table *)arg; + bss_t *bss, *nextBss; + A_UINT8 myBssid[IEEE80211_ADDR_LEN], reArmTimer = FALSE; + A_UINT32 timeoutValue = 0; + + timeoutValue = nt->nt_nodeAge; + + wmi_get_current_bssid(nt->nt_wmip, myBssid); + + bss = nt->nt_node_first; + while (bss != NULL) + { + nextBss = bss->ni_list_next; + if (A_MEMCMP(myBssid, bss->ni_macaddr, sizeof(myBssid)) != 0) + { + + if (bss->ni_tstamp <= A_GET_MS(0)) + { + /* + * free up all but the current bss - if set + */ + wlan_node_reclaim(nt, bss); + } + else + { + /* + * Re-arm timer, only when we have a bss other than + * current bss AND it is not aged-out. + */ + reArmTimer = TRUE; + } + } + bss = nextBss; + } + + if (reArmTimer) + A_TIMEOUT_MS (&nt->nt_inact_timer, timeoutValue, 0); + + nt->isTimerArmed = reArmTimer; +} + +void +wlan_node_table_cleanup(struct ieee80211_node_table *nt) +{ + A_UNTIMEOUT(&nt->nt_inact_timer); + A_DELETE_TIMER(&nt->nt_inact_timer); + wlan_free_allnodes(nt); + IEEE80211_NODE_LOCK_DESTROY(nt); +} + +bss_t * +wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID) +{ + bss_t *ni = NULL; + A_UCHAR *pIESsid = NULL; + + IEEE80211_NODE_LOCK (nt); + + for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) { + pIESsid = ni->ni_cie.ie_ssid; + if (pIESsid[1] <= 32) { + + // Step 1 : Check SSID + if (0x00 == memcmp (pSsid, &pIESsid[2], ssidLength)) { + + // + // Step 2.1 : Check MatchSSID is TRUE, if so, return Matched SSID + // Profile, otherwise check whether WPA2 or WPA + // + if (TRUE == bMatchSSID) { + ieee80211_node_incref (ni); /* mark referenced */ + IEEE80211_NODE_UNLOCK (nt); + return ni; + } + + // Step 2 : if SSID matches, check WPA or WPA2 + if (TRUE == bIsWPA2 && NULL != ni->ni_cie.ie_rsn) { + ieee80211_node_incref (ni); /* mark referenced */ + IEEE80211_NODE_UNLOCK (nt); + return ni; + } + if (FALSE == bIsWPA2 && NULL != ni->ni_cie.ie_wpa) { + ieee80211_node_incref(ni); /* mark referenced */ + IEEE80211_NODE_UNLOCK (nt); + return ni; + } + } + } + } + + IEEE80211_NODE_UNLOCK (nt); + + return NULL; +} + +void +wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni) +{ + IEEE80211_NODE_LOCK (nt); + wlan_node_dec_free (ni); + IEEE80211_NODE_UNLOCK (nt); +} + +void +wlan_node_remove_core (struct ieee80211_node_table *nt, bss_t *ni) +{ + if(ni->ni_list_prev == NULL) + { + /* First in list so fix the list head */ + nt->nt_node_first = ni->ni_list_next; + } + else + { + ni->ni_list_prev->ni_list_next = ni->ni_list_next; + } + + if(ni->ni_list_next == NULL) + { + /* Last in list so fix list tail */ + nt->nt_node_last = ni->ni_list_prev; + } + else + { + ni->ni_list_next->ni_list_prev = ni->ni_list_prev; + } + + if(ni->ni_hash_prev == NULL) + { + /* First in list so fix the list head */ + int hash; + hash = IEEE80211_NODE_HASH(ni->ni_macaddr); + nt->nt_hash[hash] = ni->ni_hash_next; + } + else + { + ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next; + } + + if(ni->ni_hash_next != NULL) + { + ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev; + } +} + +bss_t * +wlan_node_remove(struct ieee80211_node_table *nt, A_UINT8 *bssid) +{ + bss_t *bss, *nextBss; + + IEEE80211_NODE_LOCK(nt); + + bss = nt->nt_node_first; + + while (bss != NULL) + { + nextBss = bss->ni_list_next; + + if (A_MEMCMP(bssid, bss->ni_macaddr, 6) == 0) + { + wlan_node_remove_core (nt, bss); + IEEE80211_NODE_UNLOCK(nt); + return bss; + } + + bss = nextBss; + } + + IEEE80211_NODE_UNLOCK(nt); + return NULL; +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/wlan_recv_beacon.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wlan_recv_beacon.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/wlan_recv_beacon.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wlan_recv_beacon.c 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,207 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// IEEE 802.11 input handling. +// +// Author(s): ="Atheros" +//============================================================================== + +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include +#include +#include + +#define IEEE80211_VERIFY_LENGTH(_len, _minlen) do { \ + if ((_len) < (_minlen)) { \ + return A_EINVAL; \ + } \ +} while (0) + +#define IEEE80211_VERIFY_ELEMENT(__elem, __maxlen) do { \ + if ((__elem) == NULL) { \ + return A_EINVAL; \ + } \ + if ((__elem)[1] > (__maxlen)) { \ + return A_EINVAL; \ + } \ +} while (0) + + +/* unaligned little endian access */ +#define LE_READ_2(p) \ + ((A_UINT16) \ + ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8))) + +#define LE_READ_4(p) \ + ((A_UINT32) \ + ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8) | \ + (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24))) + + +static int __inline +iswpaoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((WPA_OUI_TYPE<<24)|WPA_OUI); +} + +static int __inline +iswmmoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((WMM_OUI_TYPE<<24)|WMM_OUI); +} + +/* unused functions for now */ +#if 0 +static int __inline +iswmmparam(const A_UINT8 *frm) +{ + return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE; +} + +static int __inline +iswmminfo(const A_UINT8 *frm) +{ + return frm[1] > 5 && frm[6] == WMM_INFO_OUI_SUBTYPE; +} +#endif + +static int __inline +isatherosoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((ATH_OUI_TYPE<<24)|ATH_OUI); +} + +static int __inline +iswscoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((0x04<<24)|WPA_OUI); +} + +#ifdef PYXIS_ADHOC +static int __inline +ispyxisoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((PYXIS_OUI_TYPE<<24)|PYXIS_OUI); +} +#endif + +A_STATUS +wlan_parse_beacon(A_UINT8 *buf, int framelen, struct ieee80211_common_ie *cie) +{ + A_UINT8 *frm, *efrm; + A_UINT8 elemid_ssid = FALSE; + + frm = buf; + efrm = (A_UINT8 *) (frm + framelen); + + /* + * beacon/probe response frame format + * [8] time stamp + * [2] beacon interval + * [2] capability information + * [tlv] ssid + * [tlv] supported rates + * [tlv] country information + * [tlv] parameter set (FH/DS) + * [tlv] erp information + * [tlv] extended supported rates + * [tlv] WMM + * [tlv] WPA or RSN + * [tlv] Atheros Advanced Capabilities + */ + IEEE80211_VERIFY_LENGTH(efrm - frm, 12); + A_MEMZERO(cie, sizeof(*cie)); + + cie->ie_tstamp = frm; frm += 8; + cie->ie_beaconInt = A_LE2CPU16(*(A_UINT16 *)frm); frm += 2; + cie->ie_capInfo = A_LE2CPU16(*(A_UINT16 *)frm); frm += 2; + cie->ie_chan = 0; + + while (frm < efrm) { + switch (*frm) { + case IEEE80211_ELEMID_SSID: + if (!elemid_ssid) { + cie->ie_ssid = frm; + elemid_ssid = TRUE; + } + break; + case IEEE80211_ELEMID_RATES: + cie->ie_rates = frm; + break; + case IEEE80211_ELEMID_COUNTRY: + cie->ie_country = frm; + break; + case IEEE80211_ELEMID_FHPARMS: + break; + case IEEE80211_ELEMID_DSPARMS: + cie->ie_chan = frm[2]; + break; + case IEEE80211_ELEMID_TIM: + cie->ie_tim = frm; + break; + case IEEE80211_ELEMID_IBSSPARMS: + break; + case IEEE80211_ELEMID_XRATES: + cie->ie_xrates = frm; + break; + case IEEE80211_ELEMID_ERP: + if (frm[1] != 1) { + //A_PRINTF("Discarding ERP Element - Bad Len\n"); + return A_EINVAL; + } + cie->ie_erp = frm[2]; + break; + case IEEE80211_ELEMID_RSN: + cie->ie_rsn = frm; + break; +#ifdef WAPI_ENABLE + case IEEE80211_ELEMID_WAPI: + cie->ie_wapi = frm; + break; +#endif + case IEEE80211_ELEMID_VENDOR: + if (iswpaoui(frm)) { + cie->ie_wpa = frm; + } else if (iswmmoui(frm)) { + cie->ie_wmm = frm; + } else if (isatherosoui(frm)) { + cie->ie_ath = frm; + } else if(iswscoui(frm)) { + cie->ie_wsc = frm; + } +#ifdef PYXIS_ADHOC + else if(ispyxisoui(frm)) { + cie->ie_pyxis= frm; + } +#endif + break; + default: + break; + } + frm += frm[1] + 2; + } + IEEE80211_VERIFY_ELEMENT(cie->ie_rates, IEEE80211_RATE_MAXSIZE); + IEEE80211_VERIFY_ELEMENT(cie->ie_ssid, IEEE80211_NWID_LEN); + + return A_OK; +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/wlan_utils.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wlan_utils.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/wlan_utils.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wlan_utils.c 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,61 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This module implements frequently used wlan utilies +// +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include + +/* + * converts ieee channel number to frequency + */ +A_UINT16 +wlan_ieee2freq(int chan) +{ + if (chan == 14) { + return 2484; + } + if (chan < 14) { /* 0-13 */ + return (2407 + (chan*5)); + } + if (chan < 27) { /* 15-26 */ + return (2512 + ((chan-15)*20)); + } + return (5000 + (chan*5)); +} + +/* + * Converts MHz frequency to IEEE channel number. + */ +A_UINT32 +wlan_freq2ieee(A_UINT16 freq) +{ + if (freq == 2484) + return 14; + if (freq < 2484) + return (freq - 2407) / 5; + if (freq < 5000) + return 15 + ((freq - 2512) / 20); + return (freq - 5000) / 5; +} diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/wmi.c linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wmi.c --- linux-2.6.26/drivers/net/wireless/ath6k22.133/wmi.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wmi.c 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,5879 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This module implements the hardware independent layer of the +// Wireless Module Interface (WMI) protocol. +// +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include +#include "htc.h" +#include "htc_api.h" +#include "wmi.h" +#include +#include +#include +#include +#include "dset_api.h" +#include "gpio_api.h" +#include "wmi_host.h" +#include "a_drv.h" +#include "a_drv_api.h" +#include "a_debug.h" +#include "dbglog_api.h" +#include "roaming.h" + +static A_STATUS wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); + +static A_STATUS wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_sync_point(struct wmi_t *wmip); + +static A_STATUS wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); + +static A_STATUS wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +#ifdef CONFIG_HOST_DSET_SUPPORT +static A_STATUS wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +#endif /* CONFIG_HOST_DSET_SUPPORT */ + + +static A_STATUS wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_channel_change_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS +wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len); + +static A_STATUS +wmi_set_params_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len); + +#ifdef CONFIG_HOST_GPIO_SUPPORT +static A_STATUS wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +#ifdef CONFIG_HOST_TCMD_SUPPORT +static A_STATUS +wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +#endif + +static A_STATUS +wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS +wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS +wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_BOOL +wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_INT32 rateIndex); + +static A_STATUS +wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS +wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +A_STATUS wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMIX_COMMAND_ID cmdId, + WMI_SYNC_FLAG syncflag); + +A_UINT8 ar6000_get_upper_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, A_UINT32 size); +A_UINT8 ar6000_get_lower_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, A_UINT32 size); + +void wmi_cache_configure_rssithreshold(struct wmi_t *wmip, WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd); +void wmi_cache_configure_snrthreshold(struct wmi_t *wmip, WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd); +static A_STATUS wmi_send_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd); +static A_STATUS wmi_send_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd); +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +static A_STATUS +wmi_prof_count_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + +static A_STATUS wmi_pspoll_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_dtimexpiry_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); + +static A_STATUS wmi_peer_node_event_rx (struct wmi_t *wmip, A_UINT8 *datap, + int len); + +#if defined(UNDER_CE) +#if defined(NDIS51_MINIPORT) +unsigned int processDot11Hdr = 0; +#else +unsigned int processDot11Hdr = 1; +#endif +#else +extern unsigned int processDot11Hdr; +#endif + +static const A_INT32 wmi_rateTable[] = { + 1000, + 2000, + 5500, + 11000, + 6000, + 9000, + 12000, + 18000, + 24000, + 36000, + 48000, + 54000, + 0}; + +#define MODE_A_SUPPORT_RATE_START ((A_INT32) 4) +#define MODE_A_SUPPORT_RATE_STOP ((A_INT32) 11) + +#define MODE_GONLY_SUPPORT_RATE_START MODE_A_SUPPORT_RATE_START +#define MODE_GONLY_SUPPORT_RATE_STOP MODE_A_SUPPORT_RATE_STOP + +#define MODE_B_SUPPORT_RATE_START ((A_INT32) 0) +#define MODE_B_SUPPORT_RATE_STOP ((A_INT32) 3) + +#define MODE_G_SUPPORT_RATE_START ((A_INT32) 0) +#define MODE_G_SUPPORT_RATE_STOP ((A_INT32) 11) + +#define MAX_NUMBER_OF_SUPPORT_RATES (MODE_G_SUPPORT_RATE_STOP + 1) + +/* 802.1d to AC mapping. Refer pg 57 of WMM-test-plan-v1.2 */ +const A_UINT8 up_to_ac[]= { + WMM_AC_BE, + WMM_AC_BK, + WMM_AC_BK, + WMM_AC_BE, + WMM_AC_VI, + WMM_AC_VI, + WMM_AC_VO, + WMM_AC_VO, + }; + +#include "athstartpack.h" + +/* This stuff is used when we want a simple layer-3 visibility */ +typedef PREPACK struct _iphdr { + A_UINT8 ip_ver_hdrlen; /* version and hdr length */ + A_UINT8 ip_tos; /* type of service */ + A_UINT16 ip_len; /* total length */ + A_UINT16 ip_id; /* identification */ + A_INT16 ip_off; /* fragment offset field */ +#define IP_DF 0x4000 /* dont fragment flag */ +#define IP_MF 0x2000 /* more fragments flag */ +#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */ + A_UINT8 ip_ttl; /* time to live */ + A_UINT8 ip_p; /* protocol */ + A_UINT16 ip_sum; /* checksum */ + A_UINT8 ip_src[4]; /* source and dest address */ + A_UINT8 ip_dst[4]; +} POSTPACK iphdr; + +#include "athendpack.h" + +A_INT16 rssi_event_value = 0; +A_INT16 snr_event_value = 0; + +void * +wmi_init(void *devt) +{ + struct wmi_t *wmip; + + wmip = A_MALLOC (sizeof(struct wmi_t)); + if (wmip == NULL) { + return (NULL); + } + A_MEMZERO(wmip, sizeof(*wmip)); + A_MUTEX_INIT(&wmip->wmi_lock); + wmip->wmi_devt = devt; + wlan_node_table_init(wmip, &wmip->wmi_scan_table); + wmi_qos_state_init(wmip); + + wmip->wmi_powerMode = REC_POWER; + wmip->wmi_phyMode = WMI_11G_MODE; + + wmip->wmi_pair_crypto_type = NONE_CRYPT; + wmip->wmi_grp_crypto_type = NONE_CRYPT; + + return (wmip); +} + +void +wmi_qos_state_init(struct wmi_t *wmip) +{ + A_UINT8 i; + + if (wmip == NULL) { + return; + } + LOCK_WMI(wmip); + + /* Initialize QoS States */ + wmip->wmi_numQoSStream = 0; + + wmip->wmi_fatPipeExists = 0; + + for (i=0; i < WMM_NUM_AC; i++) { + wmip->wmi_streamExistsForAC[i]=0; + } + + UNLOCK_WMI(wmip); + + A_WMI_SET_NUMDATAENDPTS(wmip->wmi_devt, 1); +} + +void +wmi_set_control_ep(struct wmi_t * wmip, HTC_ENDPOINT_ID eid) +{ + A_ASSERT( eid != ENDPOINT_UNUSED); + wmip->wmi_endpoint_id = eid; +} + +HTC_ENDPOINT_ID +wmi_get_control_ep(struct wmi_t * wmip) +{ + return(wmip->wmi_endpoint_id); +} + +void +wmi_shutdown(struct wmi_t *wmip) +{ + if (wmip != NULL) { + wlan_node_table_cleanup(&wmip->wmi_scan_table); + if (A_IS_MUTEX_VALID(&wmip->wmi_lock)) { + A_MUTEX_DELETE(&wmip->wmi_lock); + } + A_FREE(wmip); + } +} + +/* + * performs DIX to 802.3 encapsulation for transmit packets. + * uses passed in buffer. Returns buffer or NULL if failed. + * Assumes the entire DIX header is contigous and that there is + * enough room in the buffer for a 802.3 mac header and LLC+SNAP headers. + */ +A_STATUS +wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf) +{ + A_UINT8 *datap; + A_UINT16 typeorlen; + ATH_MAC_HDR macHdr; + ATH_LLC_SNAP_HDR *llcHdr; + + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_HEADROOM(osbuf) < + (sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR))) + { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + typeorlen = *(A_UINT16 *)(datap + ATH_MAC_LEN + ATH_MAC_LEN); + + if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) { + /* + * packet is already in 802.3 format - return success + */ + A_DPRINTF(DBG_WMI, (DBGFMT "packet already 802.3\n", DBGARG)); + return (A_OK); + } + + /* + * Save mac fields and length to be inserted later + */ + A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN); + A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN); + macHdr.typeOrLen = A_CPU2BE16(A_NETBUF_LEN(osbuf) - sizeof(ATH_MAC_HDR) + + sizeof(ATH_LLC_SNAP_HDR)); + + /* + * Make room for LLC+SNAP headers + */ + if (A_NETBUF_PUSH(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR)); + + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR)); + llcHdr->dsap = 0xAA; + llcHdr->ssap = 0xAA; + llcHdr->cntl = 0x03; + llcHdr->orgCode[0] = 0x0; + llcHdr->orgCode[1] = 0x0; + llcHdr->orgCode[2] = 0x0; + llcHdr->etherType = typeorlen; + + return (A_OK); +} + +/* + * Adds a WMI data header + * Assumes there is enough room in the buffer to add header. + */ +A_STATUS +wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType, A_BOOL bMoreData) +{ + WMI_DATA_HDR *dtHdr; + + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf); + dtHdr->info = msgType; + if (bMoreData) { + WMI_DATA_HDR_SET_MORE_BIT(dtHdr); + } + dtHdr->rssi = 0; + + return (A_OK); +} + +A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT32 layer2Priority, A_BOOL wmmEnabled) +{ + A_UINT8 *datap; + A_UINT8 trafficClass = WMM_AC_BE; + A_UINT16 ipType = IP_ETHERTYPE; + WMI_DATA_HDR *dtHdr; + A_BOOL streamExists = FALSE; + A_UINT8 userPriority; + A_UINT32 hdrsize; + ATH_LLC_SNAP_HDR *llcHdr; + + WMI_CREATE_PSTREAM_CMD cmd; + + A_ASSERT(osbuf != NULL); + + // + // Initialize header size + // + hdrsize = 0; + + datap = A_NETBUF_DATA(osbuf); + + if (!wmmEnabled) + { + /* If WMM is disabled all traffic goes as BE traffic */ + userPriority = 0; + } + else + { + if (processDot11Hdr) + { + hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32)); + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) + + hdrsize); + } + else + { + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) + + sizeof(ATH_MAC_HDR)); + } + + if (llcHdr->etherType == A_CPU2BE16(ipType)) + { + /* Extract the endpoint info from the TOS field in the IP header */ + + userPriority = wmi_determine_userPriority (((A_UINT8 *)llcHdr) + sizeof(ATH_LLC_SNAP_HDR),layer2Priority); + } + else + { + userPriority = layer2Priority & 0x7; + } + } + + trafficClass = convert_userPriority_to_trafficClass(userPriority); + + dtHdr = (WMI_DATA_HDR *)datap; + dtHdr->info |= (userPriority & WMI_DATA_HDR_UP_MASK) << WMI_DATA_HDR_UP_SHIFT; /* lower 3-bits are 802.1d priority */ + + LOCK_WMI(wmip); + streamExists = wmip->wmi_fatPipeExists; + UNLOCK_WMI(wmip); + + if (!(streamExists & (1 << trafficClass))) + { + + A_MEMZERO (&cmd, sizeof(cmd)); + cmd.trafficClass = trafficClass; + cmd.userPriority = userPriority; + cmd.inactivityInt = WMI_IMPLICIT_PSTREAM_INACTIVITY_INT; + /* Implicit streams are created with TSID 0xFF */ + + cmd.tsid = WMI_IMPLICIT_PSTREAM; + wmi_create_pstream_cmd (wmip, &cmd); + } + + return trafficClass; +} + +A_STATUS +wmi_dot11_hdr_add (struct wmi_t *wmip, void *osbuf, NETWORK_TYPE mode) +{ + A_UINT8 *datap; + A_UINT16 typeorlen; + ATH_MAC_HDR macHdr; + ATH_LLC_SNAP_HDR *llcHdr; + struct ieee80211_frame *wh; + A_UINT32 hdrsize; + + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_HEADROOM(osbuf) < + (sizeof(struct ieee80211_qosframe) + sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR))) + { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + typeorlen = *(A_UINT16 *)(datap + ATH_MAC_LEN + ATH_MAC_LEN); + + if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) { + /* + * packet is already in 802.3 format - return success + */ + A_DPRINTF(DBG_WMI, (DBGFMT "packet already 802.3\n", DBGARG)); + goto AddDot11Hdr; + } + + /* + * Save mac fields and length to be inserted later + */ + A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN); + A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN); + macHdr.typeOrLen = A_CPU2BE16(A_NETBUF_LEN(osbuf) - sizeof(ATH_MAC_HDR) + + sizeof(ATH_LLC_SNAP_HDR)); + + // Remove the Ethernet hdr + A_NETBUF_PULL(osbuf, sizeof(ATH_MAC_HDR)); + + /* + * Make room for LLC+SNAP headers + */ + if (A_NETBUF_PUSH(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + llcHdr = (ATH_LLC_SNAP_HDR *)(datap); + llcHdr->dsap = 0xAA; + llcHdr->ssap = 0xAA; + llcHdr->cntl = 0x03; + llcHdr->orgCode[0] = 0x0; + llcHdr->orgCode[1] = 0x0; + llcHdr->orgCode[2] = 0x0; + llcHdr->etherType = typeorlen; + +AddDot11Hdr: + /* Make room for 802.11 hdr */ + if (wmip->wmi_is_wmm_enabled) + { + hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32)); + if (A_NETBUF_PUSH(osbuf, hdrsize) != A_OK) + { + return A_NO_MEMORY; + } + wh = (struct ieee80211_frame *) A_NETBUF_DATA(osbuf); + wh->i_fc[0] = IEEE80211_FC0_SUBTYPE_QOS; + } + else + { + hdrsize = A_ROUND_UP(sizeof(struct ieee80211_frame),sizeof(A_UINT32)); + if (A_NETBUF_PUSH(osbuf, hdrsize) != A_OK) + { + return A_NO_MEMORY; + } + wh = (struct ieee80211_frame *) A_NETBUF_DATA(osbuf); + wh->i_fc[0] = IEEE80211_FC0_SUBTYPE_DATA; + } + /* Setup the SA & DA */ + IEEE80211_ADDR_COPY(wh->i_addr2, macHdr.srcMac); + + if (mode == INFRA_NETWORK) { + IEEE80211_ADDR_COPY(wh->i_addr3, macHdr.dstMac); + } + else if (mode == ADHOC_NETWORK) { + IEEE80211_ADDR_COPY(wh->i_addr1, macHdr.dstMac); + } + + return (A_OK); +} + +A_STATUS +wmi_dot11_hdr_remove(struct wmi_t *wmip, void *osbuf) +{ + A_UINT8 *datap; + struct ieee80211_frame *pwh,wh; + A_UINT8 type,subtype; + ATH_LLC_SNAP_HDR *llcHdr; + ATH_MAC_HDR macHdr; + A_UINT32 hdrsize; + + A_ASSERT(osbuf != NULL); + datap = A_NETBUF_DATA(osbuf); + + pwh = (struct ieee80211_frame *)datap; + type = pwh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; + subtype = pwh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; + + A_MEMCPY((A_UINT8 *)&wh, datap, sizeof(struct ieee80211_frame)); + + /* strip off the 802.11 hdr*/ + if (subtype == IEEE80211_FC0_SUBTYPE_QOS) { + hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32)); + A_NETBUF_PULL(osbuf, hdrsize); + } else if (subtype == IEEE80211_FC0_SUBTYPE_DATA) { + A_NETBUF_PULL(osbuf, sizeof(struct ieee80211_frame)); + } + + datap = A_NETBUF_DATA(osbuf); + llcHdr = (ATH_LLC_SNAP_HDR *)(datap); + + macHdr.typeOrLen = llcHdr->etherType; + + switch (wh.i_fc[1] & IEEE80211_FC1_DIR_MASK) { + case IEEE80211_FC1_DIR_NODS: + IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr1); + IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr2); + break; + case IEEE80211_FC1_DIR_TODS: + IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr3); + IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr2); + break; + case IEEE80211_FC1_DIR_FROMDS: + IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr1); + IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr3); + break; + case IEEE80211_FC1_DIR_DSTODS: + break; + } + + // Remove the LLC Hdr. + A_NETBUF_PULL(osbuf, sizeof(ATH_LLC_SNAP_HDR)); + + // Insert the ATH MAC hdr. + + A_NETBUF_PUSH(osbuf, sizeof(ATH_MAC_HDR)); + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY (datap, &macHdr, sizeof(ATH_MAC_HDR)); + + return A_OK; +} + +/* + * performs 802.3 to DIX encapsulation for received packets. + * Assumes the entire 802.3 header is contigous. + */ +A_STATUS +wmi_dot3_2_dix(struct wmi_t *wmip, void *osbuf) +{ + A_UINT8 *datap; + ATH_MAC_HDR macHdr; + ATH_LLC_SNAP_HDR *llcHdr; + + A_ASSERT(osbuf != NULL); + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY(&macHdr, datap, sizeof(ATH_MAC_HDR)); + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR)); + macHdr.typeOrLen = llcHdr->etherType; + + if (A_NETBUF_PULL(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR)); + + return (A_OK); +} + +/* + * Removes a WMI data header + */ +A_STATUS +wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf) +{ + A_ASSERT(osbuf != NULL); + + return (A_NETBUF_PULL(osbuf, sizeof(WMI_DATA_HDR))); +} + +void +wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg) +{ + wlan_iterate_nodes(&wmip->wmi_scan_table, f, arg); +} + +/* + * WMI Extended Event received from Target. + */ +A_STATUS +wmi_control_rx_xtnd(struct wmi_t *wmip, void *osbuf) +{ + WMIX_CMD_HDR *cmd; + A_UINT16 id; + A_UINT8 *datap; + A_UINT32 len; + A_STATUS status = A_OK; + + if (A_NETBUF_LEN(osbuf) < sizeof(WMIX_CMD_HDR)) { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + A_NETBUF_FREE(osbuf); + return A_ERROR; + } + + cmd = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf); + id = cmd->commandId; + + if (A_NETBUF_PULL(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + A_NETBUF_FREE(osbuf); + return A_ERROR; + } + + datap = A_NETBUF_DATA(osbuf); + len = A_NETBUF_LEN(osbuf); + + switch (id) { + case (WMIX_DSETOPENREQ_EVENTID): + status = wmi_dset_open_req_rx(wmip, datap, len); + break; +#ifdef CONFIG_HOST_DSET_SUPPORT + case (WMIX_DSETCLOSE_EVENTID): + status = wmi_dset_close_rx(wmip, datap, len); + break; + case (WMIX_DSETDATAREQ_EVENTID): + status = wmi_dset_data_req_rx(wmip, datap, len); + break; +#endif /* CONFIG_HOST_DSET_SUPPORT */ +#ifdef CONFIG_HOST_GPIO_SUPPORT + case (WMIX_GPIO_INTR_EVENTID): + wmi_gpio_intr_rx(wmip, datap, len); + break; + case (WMIX_GPIO_DATA_EVENTID): + wmi_gpio_data_rx(wmip, datap, len); + break; + case (WMIX_GPIO_ACK_EVENTID): + wmi_gpio_ack_rx(wmip, datap, len); + break; +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + case (WMIX_HB_CHALLENGE_RESP_EVENTID): + wmi_hbChallengeResp_rx(wmip, datap, len); + break; + case (WMIX_DBGLOG_EVENTID): + wmi_dbglog_event_rx(wmip, datap, len); + break; +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) + case (WMIX_PROF_COUNT_EVENTID): + wmi_prof_count_rx(wmip, datap, len); + break; +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + default: + A_DPRINTF(DBG_WMI|DBG_ERROR, + (DBGFMT "Unknown id 0x%x\n", DBGARG, id)); + wmip->wmi_stats.cmd_id_err++; + status = A_ERROR; + break; + } + + return status; +} + +/* + * Control Path + */ +A_UINT32 cmdRecvNum; + +A_STATUS +wmi_control_rx(struct wmi_t *wmip, void *osbuf) +{ + WMI_CMD_HDR *cmd; + A_UINT16 id; + A_UINT8 *datap; + A_UINT32 len, i, loggingReq; + A_STATUS status = A_OK; + + A_ASSERT(osbuf != NULL); + if (A_NETBUF_LEN(osbuf) < sizeof(WMI_CMD_HDR)) { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + A_NETBUF_FREE(osbuf); + return A_ERROR; + } + + cmd = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf); + id = cmd->commandId; + + if (A_NETBUF_PULL(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + A_NETBUF_FREE(osbuf); + return A_ERROR; + } + + datap = A_NETBUF_DATA(osbuf); + len = A_NETBUF_LEN(osbuf); + + loggingReq = 0; + + ar6000_get_driver_cfg(wmip->wmi_devt, + AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS, + &loggingReq); + + if(loggingReq) { + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI %d \n",id)); + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI recv, MsgNo %d : ", cmdRecvNum)); + for(i = 0; i < len; i++) + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("%x ", datap[i])); + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("\n")); + } + + LOCK_WMI(wmip); + cmdRecvNum++; + UNLOCK_WMI(wmip); + + switch (id) { + case (WMI_GET_BITRATE_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_BITRATE_CMDID\n", DBGARG)); + status = wmi_bitrate_reply_rx(wmip, datap, len); + break; + case (WMI_GET_CHANNEL_LIST_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_CHANNEL_LIST_CMDID\n", DBGARG)); + status = wmi_channelList_reply_rx(wmip, datap, len); + break; + case (WMI_GET_TX_PWR_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_TX_PWR_CMDID\n", DBGARG)); + status = wmi_txPwr_reply_rx(wmip, datap, len); + break; + case (WMI_READY_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_READY_EVENTID\n", DBGARG)); + status = wmi_ready_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + A_WMI_DBGLOG_INIT_DONE(wmip->wmi_devt); + break; + case (WMI_CONNECT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CONNECT_EVENTID\n", DBGARG)); + status = wmi_connect_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_DISCONNECT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_DISCONNECT_EVENTID\n", DBGARG)); + status = wmi_disconnect_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_PEER_NODE_EVENTID): + A_DPRINTF (DBG_WMI, (DBGFMT "WMI_PEER_NODE_EVENTID\n", DBGARG)); + status = wmi_peer_node_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_TKIP_MICERR_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TKIP_MICERR_EVENTID\n", DBGARG)); + status = wmi_tkip_micerr_event_rx(wmip, datap, len); + break; + case (WMI_BSSINFO_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BSSINFO_EVENTID\n", DBGARG)); + status = wmi_bssInfo_event_rx(wmip, datap, len); + A_WMI_SEND_GENERIC_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_REGDOMAIN_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REGDOMAIN_EVENTID\n", DBGARG)); + status = wmi_regDomain_event_rx(wmip, datap, len); + break; + case (WMI_PSTREAM_TIMEOUT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_PSTREAM_TIMEOUT_EVENTID\n", DBGARG)); + status = wmi_pstream_timeout_event_rx(wmip, datap, len); + /* pstreams are fatpipe abstractions that get implicitly created. + * User apps only deal with thinstreams. creation of a thinstream + * by the user or data traffic flow in an AC triggers implicit + * pstream creation. Do we need to send this event to App..? + * no harm in sending it. + */ + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_NEIGHBOR_REPORT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_NEIGHBOR_REPORT_EVENTID\n", DBGARG)); + status = wmi_neighborReport_event_rx(wmip, datap, len); + break; + case (WMI_SCAN_COMPLETE_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SCAN_COMPLETE_EVENTID\n", DBGARG)); + status = wmi_scanComplete_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_CMDERROR_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CMDERROR_EVENTID\n", DBGARG)); + status = wmi_errorEvent_rx(wmip, datap, len); + break; + case (WMI_REPORT_STATISTICS_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_STATISTICS_EVENTID\n", DBGARG)); + status = wmi_statsEvent_rx(wmip, datap, len); + break; + case (WMI_RSSI_THRESHOLD_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_RSSI_THRESHOLD_EVENTID\n", DBGARG)); + status = wmi_rssiThresholdEvent_rx(wmip, datap, len); + break; + case (WMI_ERROR_REPORT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_ERROR_REPORT_EVENTID\n", DBGARG)); + status = wmi_reportErrorEvent_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_OPT_RX_FRAME_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_OPT_RX_FRAME_EVENTID\n", DBGARG)); + status = wmi_opt_frame_event_rx(wmip, datap, len); + break; + case (WMI_REPORT_ROAM_TBL_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_TBL_EVENTID\n", DBGARG)); + status = wmi_roam_tbl_event_rx(wmip, datap, len); + break; + case (WMI_EXTENSION_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_EXTENSION_EVENTID\n", DBGARG)); + status = wmi_control_rx_xtnd(wmip, osbuf); + break; + case (WMI_CAC_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CAC_EVENTID\n", DBGARG)); + status = wmi_cac_event_rx(wmip, datap, len); + break; + case (WMI_CHANNEL_CHANGE_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CHANNEL_CHANGE_EVENTID\n", DBGARG)); + status = wmi_channel_change_event_rx(wmip, datap, len); + break; + case (WMI_REPORT_ROAM_DATA_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_DATA_EVENTID\n", DBGARG)); + status = wmi_roam_data_event_rx(wmip, datap, len); + break; +#ifdef CONFIG_HOST_TCMD_SUPPORT + case (WMI_TEST_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TEST_EVENTID\n", DBGARG)); + status = wmi_tcmd_test_report_rx(wmip, datap, len); + break; +#endif + case (WMI_GET_FIXRATES_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_FIXRATES_CMDID\n", DBGARG)); + status = wmi_ratemask_reply_rx(wmip, datap, len); + break; + case (WMI_TX_RETRY_ERR_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TX_RETRY_ERR_EVENTID\n", DBGARG)); + status = wmi_txRetryErrEvent_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_SNR_THRESHOLD_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SNR_THRESHOLD_EVENTID\n", DBGARG)); + status = wmi_snrThresholdEvent_rx(wmip, datap, len); + break; + case (WMI_LQ_THRESHOLD_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_LQ_THRESHOLD_EVENTID\n", DBGARG)); + status = wmi_lqThresholdEvent_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_APLIST_EVENTID): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Received APLIST Event\n")); + status = wmi_aplistEvent_rx(wmip, datap, len); + break; + case (WMI_GET_KEEPALIVE_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_KEEPALIVE_CMDID\n", DBGARG)); + status = wmi_keepalive_reply_rx(wmip, datap, len); + break; + case (WMI_GET_WOW_LIST_EVENTID): + status = wmi_get_wow_list_event_rx(wmip, datap, len); + break; + case (WMI_GET_PMKID_LIST_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_PMKID_LIST Event\n", DBGARG)); + status = wmi_get_pmkid_list_event_rx(wmip, datap, len); + break; + case (WMI_PSPOLL_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_PSPOLL_EVENT\n", DBGARG)); + status = wmi_pspoll_event_rx(wmip, datap, len); + break; + case (WMI_DTIMEXPIRY_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_DTIMEXPIRY_EVENT\n", DBGARG)); + status = wmi_dtimexpiry_event_rx(wmip, datap, len); + break; + case (WMI_SET_PARAMS_REPLY_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SET_PARAMS_REPLY Event\n", DBGARG)); + status = wmi_set_params_event_rx(wmip, datap, len); + break; + default: + A_DPRINTF(DBG_WMI|DBG_ERROR, + (DBGFMT "Unknown id 0x%x\n", DBGARG, id)); + wmip->wmi_stats.cmd_id_err++; + status = A_ERROR; + break; + } + + A_NETBUF_FREE(osbuf); + + return status; +} + +/* Send a "simple" wmi command -- one with no arguments */ +static A_STATUS +wmi_simple_cmd(struct wmi_t *wmip, WMI_COMMAND_ID cmdid) +{ + void *osbuf; + + osbuf = A_NETBUF_ALLOC(0); + + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + return (wmi_cmd_send(wmip, osbuf, cmdid, NO_SYNC_WMIFLAG)); +} + +/* Send a "simple" extended wmi command -- one with no arguments. + Enabling this command only if GPIO or profiling support is enabled. + This is to suppress warnings on some platforms */ +#if defined(CONFIG_HOST_GPIO_SUPPORT) || defined(CONFIG_TARGET_PROFILE_SUPPORT) +static A_STATUS +wmi_simple_cmd_xtnd(struct wmi_t *wmip, WMIX_COMMAND_ID cmdid) +{ + void *osbuf; + + osbuf = A_NETBUF_ALLOC(0); + + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + return (wmi_cmd_send_xtnd(wmip, osbuf, cmdid, NO_SYNC_WMIFLAG)); +} +#endif + +static A_STATUS +wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_READY_EVENT *ev = (WMI_READY_EVENT *)datap; + + if (len < sizeof(WMI_READY_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + wmip->wmi_ready = TRUE; + A_WMI_READY_EVENT(wmip->wmi_devt, ev->macaddr, ev->phyCapability, + ev->version); + + return A_OK; +} + +#define LE_READ_4(p) \ + ((A_UINT32) \ + ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8) | \ + (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24))) + +static int __inline +iswmmoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((WMM_OUI_TYPE<<24)|WMM_OUI); +} + +static int __inline +iswmmparam(const A_UINT8 *frm) +{ + return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE; +} + + +static A_STATUS +wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CONNECT_EVENT *ev; + A_UINT8 *pie,*peie; + + if (len < sizeof(WMI_CONNECT_EVENT)) + { + return A_EINVAL; + } + ev = (WMI_CONNECT_EVENT *)datap; + + A_DPRINTF(DBG_WMI, + (DBGFMT "freq %d bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", + DBGARG, ev->channel, + ev->bssid[0], ev->bssid[1], ev->bssid[2], + ev->bssid[3], ev->bssid[4], ev->bssid[5])); + + A_MEMCPY(wmip->wmi_bssid, ev->bssid, ATH_MAC_LEN); + + /* initialize pointer to start of assoc rsp IEs */ + pie = ev->assocInfo + ev->beaconIeLen + ev->assocReqLen + + sizeof(A_UINT16) + /* capinfo*/ + sizeof(A_UINT16) + /* status Code */ + sizeof(A_UINT16) ; /* associd */ + + /* initialize pointer to end of assoc rsp IEs */ + peie = ev->assocInfo + ev->beaconIeLen + ev->assocReqLen + ev->assocRespLen; + + while (pie < peie) + { + switch (*pie) + { + case IEEE80211_ELEMID_VENDOR: + if (iswmmoui(pie)) + { + if(iswmmparam (pie)) + { + wmip->wmi_is_wmm_enabled = TRUE; + } + } + break; + } + + if (wmip->wmi_is_wmm_enabled) + { + break; + } + pie += pie[1] + 2; + } + + A_WMI_CONNECT_EVENT (wmip->wmi_devt, ev->channel, ev->bssid, + ev->listenInterval, ev->beaconInterval, + (NETWORK_TYPE) ev->networkType, ev->beaconIeLen, + ev->assocReqLen, ev->assocRespLen, + ev->assocInfo); + + return A_OK; +} + +static A_STATUS +wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_REG_DOMAIN_EVENT *ev; + + if (len < sizeof(*ev)) { + return A_EINVAL; + } + ev = (WMI_REG_DOMAIN_EVENT *)datap; + + A_WMI_REGDOMAIN_EVENT(wmip->wmi_devt, ev->regDomain); + + return A_OK; +} + +static A_STATUS +wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_NEIGHBOR_REPORT_EVENT *ev; + int numAps; + + if (len < sizeof(*ev)) { + return A_EINVAL; + } + ev = (WMI_NEIGHBOR_REPORT_EVENT *)datap; + numAps = ev->numberOfAps; + + if (len < (int)(sizeof(*ev) + ((numAps - 1) * sizeof(WMI_NEIGHBOR_INFO)))) { + return A_EINVAL; + } + + A_WMI_NEIGHBORREPORT_EVENT(wmip->wmi_devt, numAps, ev->neighbor); + + return A_OK; +} + +static A_STATUS +wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_DISCONNECT_EVENT *ev; + + if (len < sizeof(WMI_DISCONNECT_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + ev = (WMI_DISCONNECT_EVENT *)datap; + + A_MEMZERO(wmip->wmi_bssid, sizeof(wmip->wmi_bssid)); + + wmip->wmi_is_wmm_enabled = FALSE; + wmip->wmi_pair_crypto_type = NONE_CRYPT; + wmip->wmi_grp_crypto_type = NONE_CRYPT; + + A_WMI_DISCONNECT_EVENT(wmip->wmi_devt, ev->disconnectReason, ev->bssid, + ev->assocRespLen, ev->assocInfo, ev->protocolReasonStatus); + + return A_OK; +} + +static A_STATUS +wmi_peer_node_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_PEER_NODE_EVENT *ev; + + if (len < sizeof(WMI_PEER_NODE_EVENT)) { + return A_EINVAL; + } + ev = (WMI_PEER_NODE_EVENT *)datap; + if (ev->eventCode == PEER_NODE_JOIN_EVENT) { + A_DPRINTF (DBG_WMI, (DBGFMT "Joined node with Macaddr: ", DBGARG)); + } else if(ev->eventCode == PEER_NODE_LEAVE_EVENT) { + A_DPRINTF (DBG_WMI, (DBGFMT "left node with Macaddr: ", DBGARG)); + } + + A_WMI_PEER_EVENT (wmip->wmi_devt, ev->eventCode, ev->peerMacAddr); + + return A_OK; +} + +static A_STATUS +wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TKIP_MICERR_EVENT *ev; + + if (len < sizeof(*ev)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + ev = (WMI_TKIP_MICERR_EVENT *)datap; + A_WMI_TKIP_MICERR_EVENT(wmip->wmi_devt, ev->keyid, ev->ismcast); + + return A_OK; +} + +static A_STATUS +wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + bss_t *bss = NULL; + WMI_BSS_INFO_HDR *bih; + A_UINT8 *buf; + A_UINT32 nodeCachingAllowed = 1; + A_UCHAR cached_ssid_len = 0; + A_UCHAR cached_ssid_buf[IEEE80211_NWID_LEN] = {0}; + A_UINT8 beacon_ssid_len = 0; + + if (len <= sizeof(WMI_BSS_INFO_HDR)) { + return A_EINVAL; + } + + bih = (WMI_BSS_INFO_HDR *)datap; + bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid); + + if (bih->rssi > 0) { + if (NULL == bss) + return A_OK; //no node found in the table, just drop the node with incorrect RSSI + else + bih->rssi = bss->ni_rssi; //Adjust RSSI in datap in case it is used in A_WMI_BSSINFO_EVENT_RX + } + + A_WMI_BSSINFO_EVENT_RX(wmip->wmi_devt, datap, len); + /* What is driver config for wlan node caching? */ + if(ar6000_get_driver_cfg(wmip->wmi_devt, + AR6000_DRIVER_CFG_GET_WLANNODECACHING, + &nodeCachingAllowed) != A_OK) { + return A_EINVAL; + } + + if(!nodeCachingAllowed) { + return A_OK; + } + + buf = datap + sizeof(WMI_BSS_INFO_HDR); + len -= sizeof(WMI_BSS_INFO_HDR); + + A_DPRINTF(DBG_WMI2, (DBGFMT "bssInfo event - ch %u, rssi %02x, " + "bssid \"%02x:%02x:%02x:%02x:%02x:%02x\"\n", DBGARG, + bih->channel, (unsigned char) bih->rssi, bih->bssid[0], + bih->bssid[1], bih->bssid[2], bih->bssid[3], bih->bssid[4], + bih->bssid[5])); + + if (bss != NULL) { + /* + * Free up the node. Not the most efficient process given + * we are about to allocate a new node but it is simple and should be + * adequate. + */ + + /* In case of hidden AP, beacon will not have ssid, + * but a directed probe response will have it, + * so cache the probe-resp-ssid if already present. */ + if (BEACON_FTYPE == bih->frameType) + { + A_UCHAR *ie_ssid; + + ie_ssid = bss->ni_cie.ie_ssid; + if(ie_ssid && (ie_ssid[1] <= IEEE80211_NWID_LEN) && (ie_ssid[2] != 0)) + { + cached_ssid_len = ie_ssid[1]; + memcpy(cached_ssid_buf, ie_ssid + 2, cached_ssid_len); + } + } + + wlan_node_reclaim(&wmip->wmi_scan_table, bss); + } + + /* beacon/probe response frame format + * [8] time stamp + * [2] beacon interval + * [2] capability information + * [tlv] ssid */ + beacon_ssid_len = buf[SSID_IE_LEN_INDEX]; + + /* If ssid is cached for this hidden AP, then change buffer len accordingly. */ + if ((BEACON_FTYPE == bih->frameType) && + (0 != cached_ssid_len) && + (0 == beacon_ssid_len || (cached_ssid_len > beacon_ssid_len && 0 == buf[SSID_IE_LEN_INDEX + 1]))) + { + len += (cached_ssid_len - beacon_ssid_len); + } + + bss = wlan_node_alloc(&wmip->wmi_scan_table, len); + if (bss == NULL) { + return A_NO_MEMORY; + } + + bss->ni_snr = bih->snr; + bss->ni_rssi = bih->rssi; + A_ASSERT(bss->ni_buf != NULL); + + /* In case of hidden AP, beacon will not have ssid, + * but a directed probe response will have it, + * so place the cached-ssid(probe-resp) in the bssinfo. */ + if ((BEACON_FTYPE == bih->frameType) && + (0 != cached_ssid_len) && + (0 == beacon_ssid_len || (beacon_ssid_len && 0 == buf[SSID_IE_LEN_INDEX + 1]))) + { + A_UINT8 *ni_buf = bss->ni_buf; + int buf_len = len; + + /* copy the first 14 bytes such as + * time-stamp(8), beacon-interval(2), cap-info(2), ssid-id(1), ssid-len(1). */ + A_MEMCPY(ni_buf, buf, SSID_IE_LEN_INDEX + 1); + + ni_buf[SSID_IE_LEN_INDEX] = cached_ssid_len; + ni_buf += (SSID_IE_LEN_INDEX + 1); + + buf += (SSID_IE_LEN_INDEX + 1); + buf_len -= (SSID_IE_LEN_INDEX + 1); + + /* copy the cached ssid */ + A_MEMCPY(ni_buf, cached_ssid_buf, cached_ssid_len); + ni_buf += cached_ssid_len; + + buf += beacon_ssid_len; + buf_len -= beacon_ssid_len; + + if (cached_ssid_len > beacon_ssid_len) + buf_len -= (cached_ssid_len - beacon_ssid_len); + + /* now copy the rest of bytes */ + A_MEMCPY(ni_buf, buf, buf_len); + } + else + A_MEMCPY(bss->ni_buf, buf, len); + + if (wlan_parse_beacon(bss->ni_buf, len, &bss->ni_cie) != A_OK) { + wlan_node_free(bss); + return A_EINVAL; + } + + /* + * Update the frequency in ie_chan, overwriting of channel number + * which is done in wlan_parse_beacon + */ + bss->ni_cie.ie_chan = bih->channel; + wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid); + + return A_OK; +} + +static A_STATUS +wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + bss_t *bss; + WMI_OPT_RX_INFO_HDR *bih; + A_UINT8 *buf; + + if (len <= sizeof(WMI_OPT_RX_INFO_HDR)) { + return A_EINVAL; + } + + bih = (WMI_OPT_RX_INFO_HDR *)datap; + buf = datap + sizeof(WMI_OPT_RX_INFO_HDR); + len -= sizeof(WMI_OPT_RX_INFO_HDR); + + A_DPRINTF(DBG_WMI2, (DBGFMT "opt frame event %2.2x:%2.2x\n", DBGARG, + bih->bssid[4], bih->bssid[5])); + + bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid); + if (bss != NULL) { + /* + * Free up the node. Not the most efficient process given + * we are about to allocate a new node but it is simple and should be + * adequate. + */ + wlan_node_reclaim(&wmip->wmi_scan_table, bss); + } + + bss = wlan_node_alloc(&wmip->wmi_scan_table, len); + if (bss == NULL) { + return A_NO_MEMORY; + } + + bss->ni_snr = bih->snr; + bss->ni_cie.ie_chan = bih->channel; + A_ASSERT(bss->ni_buf != NULL); + A_MEMCPY(bss->ni_buf, buf, len); + wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid); + + return A_OK; +} + + /* This event indicates inactivity timeout of a fatpipe(pstream) + * at the target + */ +static A_STATUS +wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_PSTREAM_TIMEOUT_EVENT *ev; + + if (len < sizeof(WMI_PSTREAM_TIMEOUT_EVENT)) { + return A_EINVAL; + } + + A_DPRINTF(DBG_WMI, (DBGFMT "wmi_pstream_timeout_event_rx\n", DBGARG)); + + ev = (WMI_PSTREAM_TIMEOUT_EVENT *)datap; + + /* When the pstream (fat pipe == AC) timesout, it means there were no + * thinStreams within this pstream & it got implicitly created due to + * data flow on this AC. We start the inactivity timer only for + * implicitly created pstream. Just reset the host state. + */ + /* Set the activeTsids for this AC to 0 */ + LOCK_WMI(wmip); + wmip->wmi_streamExistsForAC[ev->trafficClass]=0; + wmip->wmi_fatPipeExists &= ~(1 << ev->trafficClass); + UNLOCK_WMI(wmip); + + /*Indicate inactivity to driver layer for this fatpipe (pstream)*/ + A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, ev->trafficClass); + + return A_OK; +} + +static A_STATUS +wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_BIT_RATE_REPLY *reply; + A_INT32 rate; + /* 54149: + * WMI_BIT_RATE_CMD structure is changed to WMI_BIT_RATE_REPLY. + * since there is difference in the length and to avoid returning + * error value. + */ + if (len < sizeof(WMI_BIT_RATE_REPLY)) { + return A_EINVAL; + } + reply = (WMI_BIT_RATE_REPLY *)datap; + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - rateindex %d\n", DBGARG, reply->rateIndex)); + + if (reply->rateIndex == (A_INT8) RATE_AUTO) { + rate = RATE_AUTO; + } else { + rate = wmi_rateTable[(A_UINT32) reply->rateIndex]; + } + + A_WMI_BITRATE_RX(wmip->wmi_devt, rate); + + return A_OK; +} + +static A_STATUS +wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_FIX_RATES_CMD *reply; + + if (len < sizeof(WMI_BIT_RATE_CMD)) { + return A_EINVAL; + } + reply = (WMI_FIX_RATES_CMD *)datap; + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - fixed rate mask %x\n", DBGARG, reply->fixRateMask)); + + A_WMI_RATEMASK_RX(wmip->wmi_devt, reply->fixRateMask); + + return A_OK; +} + +static A_STATUS +wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CHANNEL_LIST_REPLY *reply; + + if (len < sizeof(WMI_CHANNEL_LIST_REPLY)) { + return A_EINVAL; + } + reply = (WMI_CHANNEL_LIST_REPLY *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_CHANNELLIST_RX(wmip->wmi_devt, reply->numChannels, + reply->channelList); + + return A_OK; +} + +static A_STATUS +wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TX_PWR_REPLY *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TX_PWR_REPLY *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TXPWR_RX(wmip->wmi_devt, reply->dbM); + + return A_OK; +} +static A_STATUS +wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_GET_KEEPALIVE_CMD *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_GET_KEEPALIVE_CMD *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_KEEPALIVE_RX(wmip->wmi_devt, reply->configured); + + return A_OK; +} + + +static A_STATUS +wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_DSETOPENREQ_EVENT *dsetopenreq; + + if (len < sizeof(WMIX_DSETOPENREQ_EVENT)) { + return A_EINVAL; + } + dsetopenreq = (WMIX_DSETOPENREQ_EVENT *)datap; + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - dset_id=0x%x\n", DBGARG, dsetopenreq->dset_id)); + A_WMI_DSET_OPEN_REQ(wmip->wmi_devt, + dsetopenreq->dset_id, + dsetopenreq->targ_dset_handle, + dsetopenreq->targ_reply_fn, + dsetopenreq->targ_reply_arg); + + return A_OK; +} + +#ifdef CONFIG_HOST_DSET_SUPPORT +static A_STATUS +wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_DSETCLOSE_EVENT *dsetclose; + + if (len < sizeof(WMIX_DSETCLOSE_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + dsetclose = (WMIX_DSETCLOSE_EVENT *)datap; + A_WMI_DSET_CLOSE(wmip->wmi_devt, dsetclose->access_cookie); + + return A_OK; +} + +static A_STATUS +wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_DSETDATAREQ_EVENT *dsetdatareq; + + if (len < sizeof(WMIX_DSETDATAREQ_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + dsetdatareq = (WMIX_DSETDATAREQ_EVENT *)datap; + A_WMI_DSET_DATA_REQ(wmip->wmi_devt, + dsetdatareq->access_cookie, + dsetdatareq->offset, + dsetdatareq->length, + dsetdatareq->targ_buf, + dsetdatareq->targ_reply_fn, + dsetdatareq->targ_reply_arg); + + return A_OK; +} +#endif /* CONFIG_HOST_DSET_SUPPORT */ + +static A_STATUS +wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_SCAN_COMPLETE_EVENT *ev; + + ev = (WMI_SCAN_COMPLETE_EVENT *)datap; + A_WMI_SCANCOMPLETE_EVENT(wmip->wmi_devt, (A_STATUS) ev->status); + + return A_OK; +} + +/* + * Target is reporting a programming error. This is for + * developer aid only. Target only checks a few common violations + * and it is responsibility of host to do all error checking. + * Behavior of target after wmi error event is undefined. + * A reset is recommended. + */ +static A_STATUS +wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CMD_ERROR_EVENT *ev; + + ev = (WMI_CMD_ERROR_EVENT *)datap; + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Programming Error: cmd=%d ", ev->commandId)); + switch (ev->errorCode) { + case (INVALID_PARAM): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal Parameter\n")); + break; + case (ILLEGAL_STATE): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal State\n")); + break; + case (INTERNAL_ERROR): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Internal Error\n")); + break; + } + + return A_OK; +} + + +static A_STATUS +wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TARGET_STATS *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TARGET_STATS *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TARGETSTATS_EVENT(wmip->wmi_devt, reply); + + return A_OK; +} + +static A_STATUS +wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_RSSI_THRESHOLD_EVENT *reply; + WMI_RSSI_THRESHOLD_VAL newThreshold; + WMI_RSSI_THRESHOLD_PARAMS_CMD cmd; + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_RSSI]; + A_UINT8 upper_rssi_threshold, lower_rssi_threshold; + A_INT16 rssi; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_RSSI_THRESHOLD_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + newThreshold = (WMI_RSSI_THRESHOLD_VAL) reply->range; + rssi = reply->rssi; + + /* + * Identify the threshold breached and communicate that to the app. After + * that install a new set of thresholds based on the signal quality + * reported by the target + */ + if (newThreshold) { + /* Upper threshold breached */ + if (rssi < sq_thresh->upper_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious upper RSSI threshold event: " + " %d\n", DBGARG, rssi)); + } else if ((rssi < sq_thresh->upper_threshold[1]) && + (rssi >= sq_thresh->upper_threshold[0])) + { + newThreshold = WMI_RSSI_THRESHOLD1_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[2]) && + (rssi >= sq_thresh->upper_threshold[1])) + { + newThreshold = WMI_RSSI_THRESHOLD2_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[3]) && + (rssi >= sq_thresh->upper_threshold[2])) + { + newThreshold = WMI_RSSI_THRESHOLD3_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[4]) && + (rssi >= sq_thresh->upper_threshold[3])) + { + newThreshold = WMI_RSSI_THRESHOLD4_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[5]) && + (rssi >= sq_thresh->upper_threshold[4])) + { + newThreshold = WMI_RSSI_THRESHOLD5_ABOVE; + } else if (rssi >= sq_thresh->upper_threshold[5]) { + newThreshold = WMI_RSSI_THRESHOLD6_ABOVE; + } + } else { + /* Lower threshold breached */ + if (rssi > sq_thresh->lower_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious lower RSSI threshold event: " + "%d %d\n", DBGARG, rssi, sq_thresh->lower_threshold[0])); + } else if ((rssi > sq_thresh->lower_threshold[1]) && + (rssi <= sq_thresh->lower_threshold[0])) + { + newThreshold = WMI_RSSI_THRESHOLD6_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[2]) && + (rssi <= sq_thresh->lower_threshold[1])) + { + newThreshold = WMI_RSSI_THRESHOLD5_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[3]) && + (rssi <= sq_thresh->lower_threshold[2])) + { + newThreshold = WMI_RSSI_THRESHOLD4_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[4]) && + (rssi <= sq_thresh->lower_threshold[3])) + { + newThreshold = WMI_RSSI_THRESHOLD3_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[5]) && + (rssi <= sq_thresh->lower_threshold[4])) + { + newThreshold = WMI_RSSI_THRESHOLD2_BELOW; + } else if (rssi <= sq_thresh->lower_threshold[5]) { + newThreshold = WMI_RSSI_THRESHOLD1_BELOW; + } + } + /* Calculate and install the next set of thresholds */ + lower_rssi_threshold = ar6000_get_lower_threshold(rssi, sq_thresh, + sq_thresh->lower_threshold_valid_count); + upper_rssi_threshold = ar6000_get_upper_threshold(rssi, sq_thresh, + sq_thresh->upper_threshold_valid_count); + /* Issue a wmi command to install the thresholds */ + cmd.thresholdAbove1_Val = upper_rssi_threshold; + cmd.thresholdBelow1_Val = lower_rssi_threshold; + cmd.weight = sq_thresh->weight; + cmd.pollTime = sq_thresh->polling_interval; + + rssi_event_value = rssi; + + if (wmi_send_rssi_threshold_params(wmip, &cmd) != A_OK) { + A_DPRINTF(DBG_WMI, (DBGFMT "Unable to configure the RSSI thresholds\n", + DBGARG)); + } + + A_WMI_RSSI_THRESHOLD_EVENT(wmip->wmi_devt, newThreshold, reply->rssi); + + return A_OK; +} + + +static A_STATUS +wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TARGET_ERROR_REPORT_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TARGET_ERROR_REPORT_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_REPORT_ERROR_EVENT(wmip->wmi_devt, (WMI_TARGET_ERROR_VAL) reply->errorVal); + + return A_OK; +} + +static A_STATUS +wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CAC_EVENT *reply; + WMM_TSPEC_IE *tspec_ie; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_CAC_EVENT *)datap; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + if ((reply->cac_indication == CAC_INDICATION_ADMISSION_RESP) && + (reply->statusCode != TSPEC_STATUS_CODE_ADMISSION_ACCEPTED)) { + tspec_ie = (WMM_TSPEC_IE *) &(reply->tspecSuggestion); + + wmi_delete_pstream_cmd(wmip, reply->ac, + (tspec_ie->tsInfo_info >> TSPEC_TSID_S) & TSPEC_TSID_MASK); + } + else if (reply->cac_indication == CAC_INDICATION_NO_RESP) { + A_UINT16 activeTsids; + A_UINT8 i; + + /* following assumes that there is only one outstanding ADDTS request + when this event is received */ + LOCK_WMI(wmip); + activeTsids = wmip->wmi_streamExistsForAC[reply->ac]; + UNLOCK_WMI(wmip); + + for (i = 0; i < sizeof(activeTsids) * 8; i++) { + if ((activeTsids >> i) & 1) { + break; + } + } + if (i < (sizeof(activeTsids) * 8)) { + wmi_delete_pstream_cmd(wmip, reply->ac, i); + } + } + + A_WMI_CAC_EVENT(wmip->wmi_devt, reply->ac, + reply->cac_indication, reply->statusCode, + reply->tspecSuggestion); + + return A_OK; +} + +static A_STATUS +wmi_channel_change_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CHANNEL_CHANGE_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_CHANNEL_CHANGE_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_CHANNEL_CHANGE_EVENT(wmip->wmi_devt, reply->oldChannel, + reply->newChannel); + + return A_OK; +} + +static A_STATUS +wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_HB_CHALLENGE_RESP_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMIX_HB_CHALLENGE_RESP_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "wmi: challenge response event\n", DBGARG)); + + A_WMI_HBCHALLENGERESP_EVENT(wmip->wmi_devt, reply->cookie, reply->source); + + return A_OK; +} + +static A_STATUS +wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TARGET_ROAM_TBL *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TARGET_ROAM_TBL *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_ROAM_TABLE_EVENT(wmip->wmi_devt, reply); + + return A_OK; +} + +static A_STATUS +wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TARGET_ROAM_DATA *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TARGET_ROAM_DATA *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_ROAM_DATA_EVENT(wmip->wmi_devt, reply); + + return A_OK; +} + +static A_STATUS +wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + if (len < sizeof(WMI_TX_RETRY_ERR_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TX_RETRY_ERR_EVENT(wmip->wmi_devt); + + return A_OK; +} + +static A_STATUS +wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_SNR_THRESHOLD_EVENT *reply; + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_SNR]; + WMI_SNR_THRESHOLD_VAL newThreshold; + WMI_SNR_THRESHOLD_PARAMS_CMD cmd; + A_UINT8 upper_snr_threshold, lower_snr_threshold; + A_INT16 snr; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_SNR_THRESHOLD_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + newThreshold = (WMI_SNR_THRESHOLD_VAL) reply->range; + snr = reply->snr; + /* + * Identify the threshold breached and communicate that to the app. After + * that install a new set of thresholds based on the signal quality + * reported by the target + */ + if (newThreshold) { + /* Upper threshold breached */ + if (snr < sq_thresh->upper_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious upper SNR threshold event: " + "%d\n", DBGARG, snr)); + } else if ((snr < sq_thresh->upper_threshold[1]) && + (snr >= sq_thresh->upper_threshold[0])) + { + newThreshold = WMI_SNR_THRESHOLD1_ABOVE; + } else if ((snr < sq_thresh->upper_threshold[2]) && + (snr >= sq_thresh->upper_threshold[1])) + { + newThreshold = WMI_SNR_THRESHOLD2_ABOVE; + } else if ((snr < sq_thresh->upper_threshold[3]) && + (snr >= sq_thresh->upper_threshold[2])) + { + newThreshold = WMI_SNR_THRESHOLD3_ABOVE; + } else if (snr >= sq_thresh->upper_threshold[3]) { + newThreshold = WMI_SNR_THRESHOLD4_ABOVE; + } + } else { + /* Lower threshold breached */ + if (snr > sq_thresh->lower_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious lower SNR threshold event: " + "%d %d\n", DBGARG, snr, sq_thresh->lower_threshold[0])); + } else if ((snr > sq_thresh->lower_threshold[1]) && + (snr <= sq_thresh->lower_threshold[0])) + { + newThreshold = WMI_SNR_THRESHOLD4_BELOW; + } else if ((snr > sq_thresh->lower_threshold[2]) && + (snr <= sq_thresh->lower_threshold[1])) + { + newThreshold = WMI_SNR_THRESHOLD3_BELOW; + } else if ((snr > sq_thresh->lower_threshold[3]) && + (snr <= sq_thresh->lower_threshold[2])) + { + newThreshold = WMI_SNR_THRESHOLD2_BELOW; + } else if (snr <= sq_thresh->lower_threshold[3]) { + newThreshold = WMI_SNR_THRESHOLD1_BELOW; + } + } + + /* Calculate and install the next set of thresholds */ + lower_snr_threshold = ar6000_get_lower_threshold(snr, sq_thresh, + sq_thresh->lower_threshold_valid_count); + upper_snr_threshold = ar6000_get_upper_threshold(snr, sq_thresh, + sq_thresh->upper_threshold_valid_count); + + /* Issue a wmi command to install the thresholds */ + cmd.thresholdAbove1_Val = upper_snr_threshold; + cmd.thresholdBelow1_Val = lower_snr_threshold; + cmd.weight = sq_thresh->weight; + cmd.pollTime = sq_thresh->polling_interval; + + A_DPRINTF(DBG_WMI, (DBGFMT "snr: %d, threshold: %d, lower: %d, upper: %d\n" + ,DBGARG, snr, newThreshold, lower_snr_threshold, + upper_snr_threshold)); + + snr_event_value = snr; + + if (wmi_send_snr_threshold_params(wmip, &cmd) != A_OK) { + A_DPRINTF(DBG_WMI, (DBGFMT "Unable to configure the SNR thresholds\n", + DBGARG)); + } + A_WMI_SNR_THRESHOLD_EVENT_RX(wmip->wmi_devt, newThreshold, reply->snr); + + return A_OK; +} + +static A_STATUS +wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_LQ_THRESHOLD_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_LQ_THRESHOLD_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_LQ_THRESHOLD_EVENT_RX(wmip->wmi_devt, + (WMI_LQ_THRESHOLD_VAL) reply->range, + reply->lq); + + return A_OK; +} + +static A_STATUS +wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + A_UINT16 ap_info_entry_size; + WMI_APLIST_EVENT *ev = (WMI_APLIST_EVENT *)datap; + WMI_AP_INFO_V1 *ap_info_v1; + A_UINT8 i; + + if (len < sizeof(WMI_APLIST_EVENT)) { + return A_EINVAL; + } + + if (ev->apListVer == APLIST_VER1) { + ap_info_entry_size = sizeof(WMI_AP_INFO_V1); + ap_info_v1 = (WMI_AP_INFO_V1 *)ev->apList; + } else { + return A_EINVAL; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Number of APs in APLIST Event is %d\n", ev->numAP)); + if (len < (int)(sizeof(WMI_APLIST_EVENT) + + (ev->numAP - 1) * ap_info_entry_size)) + { + return A_EINVAL; + } + + /* + * AP List Ver1 Contents + */ + for (i = 0; i < ev->numAP; i++) { + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("AP#%d BSSID %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x "\ + "Channel %d\n", i, + ap_info_v1->bssid[0], ap_info_v1->bssid[1], + ap_info_v1->bssid[2], ap_info_v1->bssid[3], + ap_info_v1->bssid[4], ap_info_v1->bssid[5], + ap_info_v1->channel)); + ap_info_v1++; + } + return A_OK; +} + +static A_STATUS +wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + A_UINT32 dropped; + + dropped = *((A_UINT32 *)datap); + datap += sizeof(dropped); + len -= sizeof(dropped); + A_WMI_DBGLOG_EVENT(wmip->wmi_devt, dropped, datap, len); + return A_OK; +} + +#ifdef CONFIG_HOST_GPIO_SUPPORT +static A_STATUS +wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_GPIO_INTR_EVENT *gpio_intr = (WMIX_GPIO_INTR_EVENT *)datap; + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - intrmask=0x%x input=0x%x.\n", DBGARG, + gpio_intr->intr_mask, gpio_intr->input_values)); + + A_WMI_GPIO_INTR_RX(gpio_intr->intr_mask, gpio_intr->input_values); + + return A_OK; +} + +static A_STATUS +wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_GPIO_DATA_EVENT *gpio_data = (WMIX_GPIO_DATA_EVENT *)datap; + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG, + gpio_data->reg_id, gpio_data->value)); + + A_WMI_GPIO_DATA_RX(gpio_data->reg_id, gpio_data->value); + + return A_OK; +} + +static A_STATUS +wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_GPIO_ACK_RX(); + + return A_OK; +} +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +/* + * Called to send a wmi command. Command specific data is already built + * on osbuf and current osbuf->data points to it. + */ +A_STATUS +wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId, + WMI_SYNC_FLAG syncflag) +{ +#define IS_OPT_TX_CMD(cmdId) ((cmdId == WMI_OPT_TX_FRAME_CMDID)) + WMI_CMD_HDR *cHdr; + HTC_ENDPOINT_ID eid = wmip->wmi_endpoint_id; + + A_ASSERT(osbuf != NULL); + + if (syncflag >= END_WMIFLAG) { + return A_EINVAL; + } + + if ((syncflag == SYNC_BEFORE_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) { + /* + * We want to make sure all data currently queued is transmitted before + * the cmd execution. Establish a new sync point. + */ + wmi_sync_point(wmip); + } + + if (A_NETBUF_PUSH(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + cHdr = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf); + cHdr->commandId = (A_UINT16) cmdId; + + /* + * Only for OPT_TX_CMD, use BE endpoint. + */ + if (IS_OPT_TX_CMD(cmdId)) { + wmi_data_hdr_add(wmip, osbuf, OPT_MSGTYPE, FALSE); + eid = A_WMI_Ac2EndpointID(wmip->wmi_devt, WMM_AC_BE); + } + A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, eid); + + if ((syncflag == SYNC_AFTER_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) { + /* + * We want to make sure all new data queued waits for the command to + * execute. Establish a new sync point. + */ + wmi_sync_point(wmip); + } + return (A_OK); +#undef IS_OPT_TX_CMD +} + +A_STATUS +wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMIX_COMMAND_ID cmdId, + WMI_SYNC_FLAG syncflag) +{ + WMIX_CMD_HDR *cHdr; + + if (A_NETBUF_PUSH(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + cHdr = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf); + cHdr->commandId = (A_UINT32) cmdId; + + return wmi_cmd_send(wmip, osbuf, WMI_EXTENSION_CMDID, syncflag); +} + +A_STATUS +wmi_connect_cmd(struct wmi_t *wmip, NETWORK_TYPE netType, + DOT11_AUTH_MODE dot11AuthMode, AUTH_MODE authMode, + CRYPTO_TYPE pairwiseCrypto, A_UINT8 pairwiseCryptoLen, + CRYPTO_TYPE groupCrypto, A_UINT8 groupCryptoLen, + int ssidLength, A_UCHAR *ssid, + A_UINT8 *bssid, A_UINT16 channel, A_UINT32 ctrl_flags) +{ + void *osbuf; + WMI_CONNECT_CMD *cc; + + if ((pairwiseCrypto == NONE_CRYPT) && (groupCrypto != NONE_CRYPT)) { + return A_EINVAL; + } + if ((pairwiseCrypto != NONE_CRYPT) && (groupCrypto == NONE_CRYPT)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_CONNECT_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_CONNECT_CMD)); + + cc = (WMI_CONNECT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cc, sizeof(*cc)); + + if (ssidLength) + { + A_MEMCPY(cc->ssid, ssid, ssidLength); + } + + cc->ssidLength = ssidLength; + cc->networkType = netType; + cc->dot11AuthMode = dot11AuthMode; + cc->authMode = authMode; + cc->pairwiseCryptoType = pairwiseCrypto; + cc->pairwiseCryptoLen = pairwiseCryptoLen; + cc->groupCryptoType = groupCrypto; + cc->groupCryptoLen = groupCryptoLen; + cc->channel = channel; + cc->ctrl_flags = ctrl_flags; + + if (bssid != NULL) { + A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN); + } + if (wmi_set_keepalive_cmd(wmip, wmip->wmi_keepaliveInterval) != A_OK) { + return(A_ERROR); + } + + wmip->wmi_pair_crypto_type = pairwiseCrypto; + wmip->wmi_grp_crypto_type = groupCrypto; + + return (wmi_cmd_send(wmip, osbuf, WMI_CONNECT_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_reconnect_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT16 channel) +{ + void *osbuf; + WMI_RECONNECT_CMD *cc; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_RECONNECT_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_RECONNECT_CMD)); + + cc = (WMI_RECONNECT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cc, sizeof(*cc)); + + cc->channel = channel; + + if (bssid != NULL) { + A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_RECONNECT_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_disconnect_cmd(struct wmi_t *wmip) +{ + A_STATUS status; + + /* Bug fix for 24817(elevator bug) - the disconnect command does not + need to do a SYNC before.*/ + status = wmi_simple_cmd(wmip, WMI_DISCONNECT_CMDID); + + return status; +} + +A_STATUS +wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType, + A_BOOL forceFgScan, A_BOOL isLegacy, + A_UINT32 homeDwellTime, A_UINT32 forceScanInterval, + A_INT8 numChan, A_UINT16 *channelList) +{ + void *osbuf; + WMI_START_SCAN_CMD *sc; + A_INT8 size; + + size = sizeof (*sc); + + if ((scanType != WMI_LONG_SCAN) && (scanType != WMI_SHORT_SCAN)) { + return A_EINVAL; + } + + if (numChan) { + if (numChan > WMI_MAX_CHANNELS) { + return A_EINVAL; + } + size += sizeof(A_UINT16) * (numChan - 1); + } + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + sc = (WMI_START_SCAN_CMD *)(A_NETBUF_DATA(osbuf)); + sc->scanType = scanType; + sc->forceFgScan = forceFgScan; + sc->isLegacy = isLegacy; + sc->homeDwellTime = homeDwellTime; + sc->forceScanInterval = forceScanInterval; + sc->numChannels = numChan; + if (numChan) { + A_MEMCPY(sc->channelList, channelList, numChan * sizeof(A_UINT16)); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_START_SCAN_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec, + A_UINT16 fg_end_sec, A_UINT16 bg_sec, + A_UINT16 minact_chdw_msec, A_UINT16 maxact_chdw_msec, + A_UINT16 pas_chdw_msec, + A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags, + A_UINT32 max_dfsch_act_time, A_UINT16 maxact_scan_per_ssid) +{ + void *osbuf; + WMI_SCAN_PARAMS_CMD *sc; + + osbuf = A_NETBUF_ALLOC(sizeof(*sc)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*sc)); + + sc = (WMI_SCAN_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(sc, sizeof(*sc)); + sc->fg_start_period = fg_start_sec; + sc->fg_end_period = fg_end_sec; + sc->bg_period = bg_sec; + sc->minact_chdwell_time = minact_chdw_msec; + sc->maxact_chdwell_time = maxact_chdw_msec; + sc->pas_chdwell_time = pas_chdw_msec; + sc->shortScanRatio = shScanRatio; + sc->scanCtrlFlags = scanCtrlFlags; + sc->max_dfsch_act_time = max_dfsch_act_time; + sc->maxact_scan_per_ssid = maxact_scan_per_ssid; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_SCAN_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask) +{ + void *osbuf; + WMI_BSS_FILTER_CMD *cmd; + + if (filter >= LAST_BSS_FILTER) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_BSS_FILTER_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->bssFilter = filter; + cmd->ieMask = ieMask; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BSS_FILTER_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag, + A_UINT8 ssidLength, A_UCHAR *ssid) +{ + void *osbuf; + WMI_PROBED_SSID_CMD *cmd; + + if (index > MAX_PROBED_SSID_INDEX) { + return A_EINVAL; + } + if (ssidLength > sizeof(cmd->ssid)) { + return A_EINVAL; + } + if ((flag & (DISABLE_SSID_FLAG | ANY_SSID_FLAG)) && (ssidLength > 0)) { + return A_EINVAL; + } + if ((flag & SPECIFIC_SSID_FLAG) && !ssidLength) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_PROBED_SSID_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->entryIndex = index; + cmd->flag = flag; + cmd->ssidLength = ssidLength; + A_MEMCPY(cmd->ssid, ssid, ssidLength); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PROBED_SSID_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons) +{ + void *osbuf; + WMI_LISTEN_INT_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_LISTEN_INT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->listenInterval = listenInterval; + cmd->numBeacons = listenBeacons; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_LISTEN_INT_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmissTime, A_UINT16 bmissBeacons) +{ + void *osbuf; + WMI_BMISS_TIME_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_BMISS_TIME_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->bmissTime = bmissTime; + cmd->numBeacons = bmissBeacons; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BMISS_TIME_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType, + A_UINT8 ieLen, A_UINT8 *ieInfo) +{ + void *osbuf; + WMI_SET_ASSOC_INFO_CMD *cmd; + A_UINT16 cmdLen; + + cmdLen = sizeof(*cmd) + ieLen - 1; + osbuf = A_NETBUF_ALLOC(cmdLen); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, cmdLen); + + cmd = (WMI_SET_ASSOC_INFO_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + cmd->ieType = ieType; + cmd->bufferSize = ieLen; + A_MEMCPY(cmd->assocInfo, ieInfo, ieLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_ASSOC_INFO_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode) +{ + void *osbuf; + WMI_POWER_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_POWER_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->powerMode = powerMode; + wmip->wmi_powerMode = powerMode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl, + A_UINT16 atim_windows, A_UINT16 timeout_value) +{ + void *osbuf; + WMI_IBSS_PM_CAPS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_IBSS_PM_CAPS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->power_saving = pmEnable; + cmd->ttl = ttl; + cmd->atim_windows = atim_windows; + cmd->timeout_value = timeout_value; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_IBSS_PM_CAPS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod, + A_UINT16 psPollNum, A_UINT16 dtimPolicy) +{ + void *osbuf; + WMI_POWER_PARAMS_CMD *pm; + + osbuf = A_NETBUF_ALLOC(sizeof(*pm)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*pm)); + + pm = (WMI_POWER_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(pm, sizeof(*pm)); + pm->idle_period = idlePeriod; + pm->pspoll_number = psPollNum; + pm->dtim_policy = dtimPolicy; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_force_target_assert(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_FORCE_TARGET_ASSERT_CMDID); +} + +A_STATUS +wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout) +{ + void *osbuf; + WMI_DISC_TIMEOUT_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DISC_TIMEOUT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->disconnectTimeout = timeout; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_DISC_TIMEOUT_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex, CRYPTO_TYPE keyType, + A_UINT8 keyUsage, A_UINT8 keyLength, A_UINT8 *keyRSC, + A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl, A_UINT8 *macAddr, + WMI_SYNC_FLAG sync_flag) +{ + void *osbuf; + WMI_ADD_CIPHER_KEY_CMD *cmd; + + if ((keyIndex > WMI_MAX_KEY_INDEX) || (keyLength > WMI_MAX_KEY_LEN) || + (keyMaterial == NULL)) + { + return A_EINVAL; + } + + if ((WEP_CRYPT != keyType) && (NULL == keyRSC)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_ADD_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->keyIndex = keyIndex; + cmd->keyType = keyType; + cmd->keyUsage = keyUsage; + cmd->keyLength = keyLength; + A_MEMCPY(cmd->key, keyMaterial, keyLength); +#ifdef WAPI_ENABLE + if (NULL != keyRSC && key_op_ctrl != KEY_OP_INIT_WAPIPN) { +#else + if (NULL != keyRSC) { +#endif // WAPI_ENABLE + A_MEMCPY(cmd->keyRSC, keyRSC, sizeof(cmd->keyRSC)); + } + cmd->key_op_ctrl = key_op_ctrl; + + if(macAddr) { + A_MEMCPY(cmd->key_macaddr,macAddr,IEEE80211_ADDR_LEN); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_CIPHER_KEY_CMDID, sync_flag)); +} + +A_STATUS +wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk) +{ + void *osbuf; + WMI_ADD_KRK_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_ADD_KRK_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + A_MEMCPY(cmd->krk, krk, WMI_KRK_LEN); + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_KRK_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_delete_krk_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_DELETE_KRK_CMDID); +} + +A_STATUS +wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex) +{ + void *osbuf; + WMI_DELETE_CIPHER_KEY_CMD *cmd; + + if (keyIndex > WMI_MAX_KEY_INDEX) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DELETE_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->keyIndex = keyIndex; + + return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_CIPHER_KEY_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId, + A_BOOL set) +{ + void *osbuf; + WMI_SET_PMKID_CMD *cmd; + + if (bssid == NULL) { + return A_EINVAL; + } + + if ((set == TRUE) && (pmkId == NULL)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_PMKID_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid)); + if (set == TRUE) { + A_MEMCPY(cmd->pmkid, pmkId, sizeof(cmd->pmkid)); + cmd->enable = PMKID_ENABLE; + } else { + A_MEMZERO(cmd->pmkid, sizeof(cmd->pmkid)); + cmd->enable = PMKID_DISABLE; + } + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en) +{ + void *osbuf; + WMI_SET_TKIP_COUNTERMEASURES_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_TKIP_COUNTERMEASURES_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->cm_en = (en == TRUE)? WMI_TKIP_CM_ENABLE : WMI_TKIP_CM_DISABLE; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_TKIP_COUNTERMEASURES_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_akmp_params_cmd(struct wmi_t *wmip, + WMI_SET_AKMP_PARAMS_CMD *akmpParams) +{ + void *osbuf; + WMI_SET_AKMP_PARAMS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + cmd = (WMI_SET_AKMP_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->akmpInfo = akmpParams->akmpInfo; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_AKMP_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_pmkid_list_cmd(struct wmi_t *wmip, + WMI_SET_PMKID_LIST_CMD *pmkInfo) +{ + void *osbuf; + WMI_SET_PMKID_LIST_CMD *cmd; + A_UINT16 cmdLen; + A_UINT8 i; + + cmdLen = sizeof(pmkInfo->numPMKID) + + pmkInfo->numPMKID * sizeof(WMI_PMKID); + + osbuf = A_NETBUF_ALLOC(cmdLen); + + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, cmdLen); + cmd = (WMI_SET_PMKID_LIST_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->numPMKID = pmkInfo->numPMKID; + + for (i = 0; i < cmd->numPMKID; i++) { + A_MEMCPY(&cmd->pmkidList[i], &pmkInfo->pmkidList[i], + WMI_PMKID_LEN); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_LIST_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_pmkid_list_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_PMKID_LIST_CMDID); +} + +A_STATUS +wmi_dataSync_send(struct wmi_t *wmip, void *osbuf, HTC_ENDPOINT_ID eid) +{ + WMI_DATA_HDR *dtHdr; + + A_ASSERT( eid != wmip->wmi_endpoint_id); + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf); + dtHdr->info = + (SYNC_MSGTYPE & WMI_DATA_HDR_MSG_TYPE_MASK) << WMI_DATA_HDR_MSG_TYPE_SHIFT; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter - eid %d\n", DBGARG, eid)); + + return (A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, eid)); +} + +typedef struct _WMI_DATA_SYNC_BUFS { + A_UINT8 trafficClass; + void *osbuf; +}WMI_DATA_SYNC_BUFS; + +static A_STATUS +wmi_sync_point(struct wmi_t *wmip) +{ + void *cmd_osbuf; + WMI_SYNC_CMD *cmd; + WMI_DATA_SYNC_BUFS dataSyncBufs[WMM_NUM_AC]; + A_UINT8 i,numPriStreams=0; + A_STATUS status = A_OK; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + memset(dataSyncBufs,0,sizeof(dataSyncBufs)); + + /* lock out while we walk through the priority list and assemble our local array */ + LOCK_WMI(wmip); + + for (i=0; i < WMM_NUM_AC ; i++) { + if (wmip->wmi_fatPipeExists & (1 << i)) { + numPriStreams++; + dataSyncBufs[numPriStreams-1].trafficClass = i; + } + } + + UNLOCK_WMI(wmip); + + /* dataSyncBufs is now filled with entries (starting at index 0) containing valid streamIDs */ + + do { + /* + * We allocate all network buffers needed so we will be able to + * send all required frames. + */ + cmd_osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (cmd_osbuf == NULL) { + status = A_NO_MEMORY; + break; + } + + A_NETBUF_PUT(cmd_osbuf, sizeof(*cmd)); + + cmd = (WMI_SYNC_CMD *)(A_NETBUF_DATA(cmd_osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + /* In the SYNC cmd sent on the control Ep, send a bitmap of the data + * eps on which the Data Sync will be sent + */ + cmd->dataSyncMap = wmip->wmi_fatPipeExists; + + for (i=0; i < numPriStreams ; i++) { + dataSyncBufs[i].osbuf = A_NETBUF_ALLOC(0); + if (dataSyncBufs[i].osbuf == NULL) { + status = A_NO_MEMORY; + break; + } + } //end for + + /* if Buffer allocation for any of the dataSync fails, then do not + * send the Synchronize cmd on the control ep + */ + if (A_FAILED(status)) { + break; + } + + /* + * Send sync cmd followed by sync data messages on all endpoints being + * used + */ + status = wmi_cmd_send(wmip, cmd_osbuf, WMI_SYNCHRONIZE_CMDID, + NO_SYNC_WMIFLAG); + + if (A_FAILED(status)) { + break; + } + /* cmd buffer sent, we no longer own it */ + cmd_osbuf = NULL; + + for(i=0; i < numPriStreams; i++) { + A_ASSERT(dataSyncBufs[i].osbuf != NULL); + status = wmi_dataSync_send(wmip, + dataSyncBufs[i].osbuf, + A_WMI_Ac2EndpointID(wmip->wmi_devt, + dataSyncBufs[i]. + trafficClass) + ); + + if (A_FAILED(status)) { + break; + } + /* we don't own this buffer anymore, NULL it out of the array so it + * won't get cleaned up */ + dataSyncBufs[i].osbuf = NULL; + } //end for + + } while(FALSE); + + /* free up any resources left over (possibly due to an error) */ + + if (cmd_osbuf != NULL) { + A_NETBUF_FREE(cmd_osbuf); + } + + for (i = 0; i < numPriStreams; i++) { + if (dataSyncBufs[i].osbuf != NULL) { + A_NETBUF_FREE(dataSyncBufs[i].osbuf); + } + } + + return (status); +} + +A_STATUS +wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *params) +{ + void *osbuf; + WMI_CREATE_PSTREAM_CMD *cmd; + A_UINT8 fatPipeExistsForAC=0; + A_INT32 minimalPHY = 0; + A_INT32 nominalPHY = 0; + + /* Validate all the parameters. */ + if( !((params->userPriority < 8) && + (params->userPriority <= 0x7) && + (convert_userPriority_to_trafficClass(params->userPriority) == params->trafficClass) && + (params->trafficDirection == UPLINK_TRAFFIC || + params->trafficDirection == DNLINK_TRAFFIC || + params->trafficDirection == BIDIR_TRAFFIC) && + (params->trafficType == TRAFFIC_TYPE_APERIODIC || + params->trafficType == TRAFFIC_TYPE_PERIODIC ) && + (params->voicePSCapability == DISABLE_FOR_THIS_AC || + params->voicePSCapability == ENABLE_FOR_THIS_AC || + params->voicePSCapability == ENABLE_FOR_ALL_AC) && + (params->tsid == WMI_IMPLICIT_PSTREAM || params->tsid <= WMI_MAX_THINSTREAM)) ) + { + return A_EINVAL; + } + + // + // check nominal PHY rate is >= minimalPHY, so that DUT + // can allow TSRS IE + // + + // get the physical rate + minimalPHY = ((params->minPhyRate / 1000)/1000); // unit of bps + + // check minimal phy < nominal phy rate + // + if (params->nominalPHY >= minimalPHY) + { + nominalPHY = (params->nominalPHY * 1000)/500; // unit of 500 kbps + A_DPRINTF(DBG_WMI, + (DBGFMT "TSRS IE Enabled::MinPhy %x->NominalPhy ===> %x\n", DBGARG, + minimalPHY, nominalPHY)); + + params->nominalPHY = nominalPHY; + } + else + { + params->nominalPHY = 0; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + A_DPRINTF(DBG_WMI, + (DBGFMT "Sending create_pstream_cmd: ac=%d tsid:%d\n", DBGARG, + params->trafficClass, params->tsid)); + + cmd = (WMI_CREATE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + A_MEMCPY(cmd, params, sizeof(*cmd)); + + /* this is an implicitly created Fat pipe */ + if (params->tsid == WMI_IMPLICIT_PSTREAM) { + LOCK_WMI(wmip); + fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass)); + wmip->wmi_fatPipeExists |= (1<trafficClass); + UNLOCK_WMI(wmip); + } else { + /* this is an explicitly created thin stream within a fat pipe */ + LOCK_WMI(wmip); + fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass)); + wmip->wmi_streamExistsForAC[params->trafficClass] |= (1<tsid); + /* if a thinstream becomes active, the fat pipe automatically + * becomes active + */ + wmip->wmi_fatPipeExists |= (1<trafficClass); + UNLOCK_WMI(wmip); + } + + /* Indicate activty change to driver layer only if this is the + * first TSID to get created in this AC explicitly or an implicit + * fat pipe is getting created. + */ + if (!fatPipeExistsForAC) { + A_WMI_STREAM_TX_ACTIVE(wmip->wmi_devt, params->trafficClass); + } + + /* mike: should be SYNC_BEFORE_WMIFLAG */ + return (wmi_cmd_send(wmip, osbuf, WMI_CREATE_PSTREAM_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 tsid) +{ + void *osbuf; + WMI_DELETE_PSTREAM_CMD *cmd; + A_STATUS status; + A_UINT16 activeTsids=0; + + /* validate the parameters */ + if (trafficClass > 3) { + A_DPRINTF(DBG_WMI, (DBGFMT "Invalid trafficClass: %d\n", DBGARG, trafficClass)); + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DELETE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->trafficClass = trafficClass; + cmd->tsid = tsid; + + LOCK_WMI(wmip); + activeTsids = wmip->wmi_streamExistsForAC[trafficClass]; + UNLOCK_WMI(wmip); + + /* Check if the tsid was created & exists */ + if (!(activeTsids & (1<wmi_streamExistsForAC[trafficClass] &= ~(1<wmi_streamExistsForAC[trafficClass]; + UNLOCK_WMI(wmip); + + + /* Indicate stream inactivity to driver layer only if all tsids + * within this AC are deleted. + */ + if(!activeTsids) { + A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, trafficClass); + wmip->wmi_fatPipeExists &= ~(1< 15)){ + + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_FRAME_RATES_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + frameType = (A_UINT8)((subType << 4) | type); + + cmd->bEnableMask = bEnable; + cmd->frameType = frameType; + cmd->frameRateMask = rateMask; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_FRAMERATES_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * used to set the bit rate. rate is in Kbps. If rate == -1 + * then auto selection is used. + */ +A_STATUS +wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 dataRate, A_INT32 mgmtRate, A_INT32 ctlRate) +{ + void *osbuf; + WMI_BIT_RATE_CMD *cmd; + A_INT8 drix, mrix, crix; + + if (dataRate != -1) { + drix = wmi_validate_bitrate(wmip, dataRate); + if(drix == A_EINVAL){ + return A_EINVAL; + } + } else { + drix = (A_INT8) -1; + } + + if (mgmtRate != -1) { + mrix = wmi_validate_bitrate(wmip, mgmtRate); + if(mrix == A_EINVAL){ + return A_EINVAL; + } + } else { + mrix = (A_INT8) -1; + } + if (ctlRate != -1) { + crix = wmi_validate_bitrate(wmip, ctlRate); + if(crix == A_EINVAL){ + return A_EINVAL; + } + } else { + crix = (A_INT8) -1; + } + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_BIT_RATE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->rateIndex = drix; + cmd->mgmtRateIndex = mrix; + cmd->ctlRateIndex = crix; + + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BITRATE_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_bitrate_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_BITRATE_CMDID); +} + +/* + * Returns TRUE iff the given rate index is legal in the current PHY mode. + */ +A_BOOL +wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_INT32 rateIndex) +{ + WMI_PHY_MODE phyMode = (WMI_PHY_MODE) wmip->wmi_phyMode; + A_BOOL isValid = TRUE; + switch(phyMode) { + case WMI_11A_MODE: + if ((rateIndex < MODE_A_SUPPORT_RATE_START) || (rateIndex > MODE_A_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + + case WMI_11B_MODE: + if ((rateIndex < MODE_B_SUPPORT_RATE_START) || (rateIndex > MODE_B_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + + case WMI_11GONLY_MODE: + if ((rateIndex < MODE_GONLY_SUPPORT_RATE_START) || (rateIndex > MODE_GONLY_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + + case WMI_11G_MODE: + case WMI_11AG_MODE: + if ((rateIndex < MODE_G_SUPPORT_RATE_START) || (rateIndex > MODE_G_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + + default: + A_ASSERT(FALSE); + break; + } + + return isValid; +} + +A_INT8 +wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate) +{ + A_INT8 i; + if (rate != -1) + { + for (i=0;;i++) + { + if (wmi_rateTable[(A_UINT32) i] == 0) { + return A_EINVAL; + } + if (wmi_rateTable[(A_UINT32) i] == rate) { + break; + } + } + } + else{ + i = -1; + } + + if(wmi_is_bitrate_index_valid(wmip, (A_INT32) i) != TRUE) { + return A_EINVAL; + } + + return i; +} + +A_STATUS +wmi_set_fixrates_cmd(struct wmi_t *wmip, A_INT16 fixRatesMask) +{ + void *osbuf; + WMI_FIX_RATES_CMD *cmd; + A_INT32 rateIndex; + + /* Make sure all rates in the mask are valid in the current PHY mode */ + for(rateIndex = 0; rateIndex < MAX_NUMBER_OF_SUPPORT_RATES; rateIndex++) { + if((1 << rateIndex) & (A_UINT32)fixRatesMask) { + if(wmi_is_bitrate_index_valid(wmip, rateIndex) != TRUE) { + A_DPRINTF(DBG_WMI, (DBGFMT "Set Fix Rates command failed: Given rate is illegal in current PHY mode\n", DBGARG)); + return A_EINVAL; + } + } + } + + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_FIX_RATES_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->fixRateMask = fixRatesMask; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_FIXRATES_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_ratemask_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_FIXRATES_CMDID); +} + +A_STATUS +wmi_get_channelList_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_CHANNEL_LIST_CMDID); +} + +/* + * used to generate a wmi sey channel Parameters cmd. + * mode should always be specified and corresponds to the phy mode of the + * wlan. + * numChan should alway sbe specified. If zero indicates that all available + * channels should be used. + * channelList is an array of channel frequencies (in Mhz) which the radio + * should limit its operation to. It should be NULL if numChan == 0. Size of + * array should correspond to numChan entries. + */ +A_STATUS +wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam, + WMI_PHY_MODE mode, A_INT8 numChan, + A_UINT16 *channelList) +{ + void *osbuf; + WMI_CHANNEL_PARAMS_CMD *cmd; + A_INT8 size; + + size = sizeof (*cmd); + + if (numChan) { + if (numChan > WMI_MAX_CHANNELS) { + return A_EINVAL; + } + size += sizeof(A_UINT16) * (numChan - 1); + } + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_CHANNEL_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + wmip->wmi_phyMode = mode; + cmd->scanParam = scanParam; + cmd->phyMode = mode; + cmd->numChannels = numChan; + A_MEMCPY(cmd->channelList, channelList, numChan * sizeof(A_UINT16)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_CHANNEL_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +void +wmi_cache_configure_rssithreshold(struct wmi_t *wmip, WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd) +{ + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_RSSI]; + /* + * Parse the command and store the threshold values here. The checks + * for valid values can be put here + */ + sq_thresh->weight = rssiCmd->weight; + sq_thresh->polling_interval = rssiCmd->pollTime; + + sq_thresh->upper_threshold[0] = rssiCmd->thresholdAbove1_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[1] = rssiCmd->thresholdAbove2_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[2] = rssiCmd->thresholdAbove3_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[3] = rssiCmd->thresholdAbove4_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[4] = rssiCmd->thresholdAbove5_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[5] = rssiCmd->thresholdAbove6_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold_valid_count = 6; + + /* List sorted in descending order */ + sq_thresh->lower_threshold[0] = rssiCmd->thresholdBelow6_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[1] = rssiCmd->thresholdBelow5_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[2] = rssiCmd->thresholdBelow4_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[3] = rssiCmd->thresholdBelow3_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[4] = rssiCmd->thresholdBelow2_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[5] = rssiCmd->thresholdBelow1_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold_valid_count = 6; + + if (!rssi_event_value) { + /* + * Configuring the thresholds to their extremes allows the host to get an + * event from the target which is used for the configuring the correct + * thresholds + */ + rssiCmd->thresholdAbove1_Val = sq_thresh->upper_threshold[0]; + rssiCmd->thresholdBelow1_Val = sq_thresh->lower_threshold[0]; + } else { + /* + * In case the user issues multiple times of rssi_threshold_setting, + * we should not use the extreames anymore, the target does not expect that. + */ + rssiCmd->thresholdAbove1_Val = ar6000_get_upper_threshold(rssi_event_value, sq_thresh, + sq_thresh->upper_threshold_valid_count); + rssiCmd->thresholdBelow1_Val = ar6000_get_lower_threshold(rssi_event_value, sq_thresh, + sq_thresh->lower_threshold_valid_count); + } +} + +A_STATUS +wmi_set_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd) +{ + + /* Check these values are in ascending order */ + if( rssiCmd->thresholdAbove6_Val <= rssiCmd->thresholdAbove5_Val || + rssiCmd->thresholdAbove5_Val <= rssiCmd->thresholdAbove4_Val || + rssiCmd->thresholdAbove4_Val <= rssiCmd->thresholdAbove3_Val || + rssiCmd->thresholdAbove3_Val <= rssiCmd->thresholdAbove2_Val || + rssiCmd->thresholdAbove2_Val <= rssiCmd->thresholdAbove1_Val || + rssiCmd->thresholdBelow6_Val <= rssiCmd->thresholdBelow5_Val || + rssiCmd->thresholdBelow5_Val <= rssiCmd->thresholdBelow4_Val || + rssiCmd->thresholdBelow4_Val <= rssiCmd->thresholdBelow3_Val || + rssiCmd->thresholdBelow3_Val <= rssiCmd->thresholdBelow2_Val || + rssiCmd->thresholdBelow2_Val <= rssiCmd->thresholdBelow1_Val) + { + return A_EINVAL; + } + + wmi_cache_configure_rssithreshold(wmip, rssiCmd); + + return (wmi_send_rssi_threshold_params(wmip, rssiCmd)); +} + +A_STATUS +wmi_set_ip_cmd(struct wmi_t *wmip, WMI_SET_IP_CMD *ipCmd) +{ + void *osbuf; + WMI_SET_IP_CMD *cmd; + + /* Multicast address are not valid */ + if((*((A_UINT8*)&ipCmd->ips[0]) >= 0xE0) || + (*((A_UINT8*)&ipCmd->ips[1]) >= 0xE0)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_SET_IP_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_SET_IP_CMD)); + cmd = (WMI_SET_IP_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMCPY(cmd, ipCmd, sizeof(WMI_SET_IP_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_IP_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip, + WMI_SET_HOST_SLEEP_MODE_CMD *hostModeCmd) +{ + void *osbuf; + A_INT8 size; + WMI_SET_HOST_SLEEP_MODE_CMD *cmd; + A_UINT16 activeTsids=0; + A_UINT8 streamExists=0; + A_UINT8 i; + + if( hostModeCmd->awake == hostModeCmd->asleep) { + return A_EINVAL; + } + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_SET_HOST_SLEEP_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, hostModeCmd, sizeof(WMI_SET_HOST_SLEEP_MODE_CMD)); + + if(hostModeCmd->asleep) { + /* + * Relinquish credits from all implicitly created pstreams since when we + * go to sleep. If user created explicit thinstreams exists with in a + * fatpipe leave them intact for the user to delete + */ + LOCK_WMI(wmip); + streamExists = wmip->wmi_fatPipeExists; + UNLOCK_WMI(wmip); + + for(i=0;i< WMM_NUM_AC;i++) { + if (streamExists & (1<wmi_streamExistsForAC[i]; + UNLOCK_WMI(wmip); + /* If there are no user created thin streams delete the fatpipe */ + if(!activeTsids) { + streamExists &= ~(1<wmi_devt,i); + } + } + } + + /* Update the fatpipes that exists*/ + LOCK_WMI(wmip); + wmip->wmi_fatPipeExists = streamExists; + UNLOCK_WMI(wmip); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_HOST_SLEEP_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_wow_mode_cmd(struct wmi_t *wmip, + WMI_SET_WOW_MODE_CMD *wowModeCmd) +{ + void *osbuf; + A_INT8 size; + WMI_SET_WOW_MODE_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_SET_WOW_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, wowModeCmd, sizeof(WMI_SET_WOW_MODE_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WOW_MODE_CMDID, + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_get_wow_list_cmd(struct wmi_t *wmip, + WMI_GET_WOW_LIST_CMD *wowListCmd) +{ + void *osbuf; + A_INT8 size; + WMI_GET_WOW_LIST_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_GET_WOW_LIST_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, wowListCmd, sizeof(WMI_GET_WOW_LIST_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_GET_WOW_LIST_CMDID, + NO_SYNC_WMIFLAG)); + +} + +static A_STATUS +wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_GET_WOW_LIST_REPLY *reply; + + if (len < sizeof(WMI_GET_WOW_LIST_REPLY)) { + return A_EINVAL; + } + reply = (WMI_GET_WOW_LIST_REPLY *)datap; + + A_WMI_WOW_LIST_EVENT(wmip->wmi_devt, reply->num_filters, + reply); + + return A_OK; +} + +A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip, + WMI_ADD_WOW_PATTERN_CMD *addWowCmd, + A_UINT8* pattern, A_UINT8* mask, + A_UINT8 pattern_size) +{ + void *osbuf; + A_INT8 size; + WMI_ADD_WOW_PATTERN_CMD *cmd; + A_UINT8 *filter_mask = NULL; + + size = sizeof (*cmd); + + size += ((2 * addWowCmd->filter_size)* sizeof(A_UINT8)); + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_ADD_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->filter_list_id = addWowCmd->filter_list_id; + cmd->filter_offset = addWowCmd->filter_offset; + cmd->filter_size = addWowCmd->filter_size; + + A_MEMCPY(cmd->filter, pattern, addWowCmd->filter_size); + + filter_mask = (A_UINT8*)(cmd->filter + cmd->filter_size); + A_MEMCPY(filter_mask, mask, addWowCmd->filter_size); + + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_WOW_PATTERN_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_del_wow_pattern_cmd(struct wmi_t *wmip, + WMI_DEL_WOW_PATTERN_CMD *delWowCmd) +{ + void *osbuf; + A_INT8 size; + WMI_DEL_WOW_PATTERN_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_DEL_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, delWowCmd, sizeof(WMI_DEL_WOW_PATTERN_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_DEL_WOW_PATTERN_CMDID, + NO_SYNC_WMIFLAG)); + +} + +void +wmi_cache_configure_snrthreshold(struct wmi_t *wmip, WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd) +{ + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_SNR]; + /* + * Parse the command and store the threshold values here. The checks + * for valid values can be put here + */ + sq_thresh->weight = snrCmd->weight; + sq_thresh->polling_interval = snrCmd->pollTime; + + sq_thresh->upper_threshold[0] = snrCmd->thresholdAbove1_Val; + sq_thresh->upper_threshold[1] = snrCmd->thresholdAbove2_Val; + sq_thresh->upper_threshold[2] = snrCmd->thresholdAbove3_Val; + sq_thresh->upper_threshold[3] = snrCmd->thresholdAbove4_Val; + sq_thresh->upper_threshold_valid_count = 4; + + /* List sorted in descending order */ + sq_thresh->lower_threshold[0] = snrCmd->thresholdBelow4_Val; + sq_thresh->lower_threshold[1] = snrCmd->thresholdBelow3_Val; + sq_thresh->lower_threshold[2] = snrCmd->thresholdBelow2_Val; + sq_thresh->lower_threshold[3] = snrCmd->thresholdBelow1_Val; + sq_thresh->lower_threshold_valid_count = 4; + + if (!snr_event_value) { + /* + * Configuring the thresholds to their extremes allows the host to get an + * event from the target which is used for the configuring the correct + * thresholds + */ + snrCmd->thresholdAbove1_Val = (A_UINT8)sq_thresh->upper_threshold[0]; + snrCmd->thresholdBelow1_Val = (A_UINT8)sq_thresh->lower_threshold[0]; + } else { + /* + * In case the user issues multiple times of snr_threshold_setting, + * we should not use the extreames anymore, the target does not expect that. + */ + snrCmd->thresholdAbove1_Val = ar6000_get_upper_threshold(snr_event_value, sq_thresh, + sq_thresh->upper_threshold_valid_count); + snrCmd->thresholdBelow1_Val = ar6000_get_lower_threshold(snr_event_value, sq_thresh, + sq_thresh->lower_threshold_valid_count); + } + +} +A_STATUS +wmi_set_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd) +{ + if( snrCmd->thresholdAbove4_Val <= snrCmd->thresholdAbove3_Val || + snrCmd->thresholdAbove3_Val <= snrCmd->thresholdAbove2_Val || + snrCmd->thresholdAbove2_Val <= snrCmd->thresholdAbove1_Val || + snrCmd->thresholdBelow4_Val <= snrCmd->thresholdBelow3_Val || + snrCmd->thresholdBelow3_Val <= snrCmd->thresholdBelow2_Val || + snrCmd->thresholdBelow2_Val <= snrCmd->thresholdBelow1_Val) + { + return A_EINVAL; + } + wmi_cache_configure_snrthreshold(wmip, snrCmd); + return (wmi_send_snr_threshold_params(wmip, snrCmd)); +} + +A_STATUS +wmi_clr_rssi_snr(struct wmi_t *wmip) +{ + void *osbuf; + + osbuf = A_NETBUF_ALLOC(sizeof(int)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + return (wmi_cmd_send(wmip, osbuf, WMI_CLR_RSSI_SNR_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_lq_threshold_params(struct wmi_t *wmip, + WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd) +{ + void *osbuf; + A_INT8 size; + WMI_LQ_THRESHOLD_PARAMS_CMD *cmd; + /* These values are in ascending order */ + if( lqCmd->thresholdAbove4_Val <= lqCmd->thresholdAbove3_Val || + lqCmd->thresholdAbove3_Val <= lqCmd->thresholdAbove2_Val || + lqCmd->thresholdAbove2_Val <= lqCmd->thresholdAbove1_Val || + lqCmd->thresholdBelow4_Val <= lqCmd->thresholdBelow3_Val || + lqCmd->thresholdBelow3_Val <= lqCmd->thresholdBelow2_Val || + lqCmd->thresholdBelow2_Val <= lqCmd->thresholdBelow1_Val ) { + + return A_EINVAL; + } + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_LQ_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, lqCmd, sizeof(WMI_LQ_THRESHOLD_PARAMS_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_LQ_THRESHOLD_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 mask) +{ + void *osbuf; + A_INT8 size; + WMI_TARGET_ERROR_REPORT_BITMASK *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_TARGET_ERROR_REPORT_BITMASK *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + cmd->bitmask = mask; + + return (wmi_cmd_send(wmip, osbuf, WMI_TARGET_ERROR_REPORT_BITMASK_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie, A_UINT32 source) +{ + void *osbuf; + WMIX_HB_CHALLENGE_RESP_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_HB_CHALLENGE_RESP_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->cookie = cookie; + cmd->source = source; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_HB_CHALLENGE_RESP_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask, + A_UINT16 tsr, A_BOOL rep, A_UINT16 size, + A_UINT32 valid) +{ + void *osbuf; + WMIX_DBGLOG_CFG_MODULE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_DBGLOG_CFG_MODULE_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->config.cfgmmask = mmask; + cmd->config.cfgtsr = tsr; + cmd->config.cfgrep = rep; + cmd->config.cfgsize = size; + cmd->config.cfgvalid = valid; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DBGLOG_CFG_MODULE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_stats_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_STATISTICS_CMDID); +} + +A_STATUS +wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid) +{ + void *osbuf; + WMI_ADD_BAD_AP_CMD *cmd; + + if ((bssid == NULL) || (apIndex > WMI_MAX_BAD_AP_INDEX)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_ADD_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->badApIndex = apIndex; + A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid)); + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_BAD_AP_CMDID, SYNC_BEFORE_WMIFLAG)); +} + +A_STATUS +wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex) +{ + void *osbuf; + WMI_DELETE_BAD_AP_CMD *cmd; + + if (apIndex > WMI_MAX_BAD_AP_INDEX) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DELETE_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->badApIndex = apIndex; + + return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_BAD_AP_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_abort_scan_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_ABORT_SCAN_CMDID); +} + +A_STATUS +wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM) +{ + void *osbuf; + WMI_SET_TX_PWR_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_TX_PWR_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->dbM = dbM; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_TX_PWR_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_txPwr_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_TX_PWR_CMDID); +} + +A_UINT16 +wmi_get_mapped_qos_queue(struct wmi_t *wmip, A_UINT8 trafficClass) +{ + A_UINT16 activeTsids=0; + + LOCK_WMI(wmip); + activeTsids = wmip->wmi_streamExistsForAC[trafficClass]; + UNLOCK_WMI(wmip); + + return activeTsids; +} + +A_STATUS +wmi_get_roam_tbl_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_ROAM_TBL_CMDID); +} + +A_STATUS +wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType) +{ + void *osbuf; + A_UINT32 size = sizeof(A_UINT8); + WMI_TARGET_ROAM_DATA *cmd; + + osbuf = A_NETBUF_ALLOC(size); /* no payload */ + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_TARGET_ROAM_DATA *)(A_NETBUF_DATA(osbuf)); + cmd->roamDataType = roamDataType; + + return (wmi_cmd_send(wmip, osbuf, WMI_GET_ROAM_DATA_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p, + A_UINT8 size) +{ + void *osbuf; + WMI_SET_ROAM_CTRL_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_SET_ROAM_CTRL_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + A_MEMCPY(cmd, p, size); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_ROAM_CTRL_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_powersave_timers_cmd(struct wmi_t *wmip, + WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd, + A_UINT8 size) +{ + void *osbuf; + WMI_POWERSAVE_TIMERS_POLICY_CMD *cmd; + + /* These timers can't be zero */ + if(!pCmd->psPollTimeout || !pCmd->triggerTimeout || + !(pCmd->apsdTimPolicy == IGNORE_TIM_ALL_QUEUES_APSD || + pCmd->apsdTimPolicy == PROCESS_TIM_ALL_QUEUES_APSD) || + !(pCmd->simulatedAPSDTimPolicy == IGNORE_TIM_SIMULATED_APSD || + pCmd->simulatedAPSDTimPolicy == PROCESS_TIM_SIMULATED_APSD)) + return A_EINVAL; + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_POWERSAVE_TIMERS_POLICY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + A_MEMCPY(cmd, pCmd, size); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID, + NO_SYNC_WMIFLAG)); +} + +#ifdef CONFIG_HOST_GPIO_SUPPORT +/* Send a command to Target to change GPIO output pins. */ +A_STATUS +wmi_gpio_output_set(struct wmi_t *wmip, + A_UINT32 set_mask, + A_UINT32 clear_mask, + A_UINT32 enable_mask, + A_UINT32 disable_mask) +{ + void *osbuf; + WMIX_GPIO_OUTPUT_SET_CMD *output_set; + int size; + + size = sizeof(*output_set); + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - set=0x%x clear=0x%x enb=0x%x dis=0x%x\n", DBGARG, + set_mask, clear_mask, enable_mask, disable_mask)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + output_set = (WMIX_GPIO_OUTPUT_SET_CMD *)(A_NETBUF_DATA(osbuf)); + + output_set->set_mask = set_mask; + output_set->clear_mask = clear_mask; + output_set->enable_mask = enable_mask; + output_set->disable_mask = disable_mask; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_OUTPUT_SET_CMDID, + NO_SYNC_WMIFLAG)); +} + +/* Send a command to the Target requesting state of the GPIO input pins */ +A_STATUS +wmi_gpio_input_get(struct wmi_t *wmip) +{ + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + return wmi_simple_cmd_xtnd(wmip, WMIX_GPIO_INPUT_GET_CMDID); +} + +/* Send a command to the Target that changes the value of a GPIO register. */ +A_STATUS +wmi_gpio_register_set(struct wmi_t *wmip, + A_UINT32 gpioreg_id, + A_UINT32 value) +{ + void *osbuf; + WMIX_GPIO_REGISTER_SET_CMD *register_set; + int size; + + size = sizeof(*register_set); + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG, gpioreg_id, value)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + register_set = (WMIX_GPIO_REGISTER_SET_CMD *)(A_NETBUF_DATA(osbuf)); + + register_set->gpioreg_id = gpioreg_id; + register_set->value = value; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_SET_CMDID, + NO_SYNC_WMIFLAG)); +} + +/* Send a command to the Target to fetch the value of a GPIO register. */ +A_STATUS +wmi_gpio_register_get(struct wmi_t *wmip, + A_UINT32 gpioreg_id) +{ + void *osbuf; + WMIX_GPIO_REGISTER_GET_CMD *register_get; + int size; + + size = sizeof(*register_get); + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter - reg=%d\n", DBGARG, gpioreg_id)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + register_get = (WMIX_GPIO_REGISTER_GET_CMD *)(A_NETBUF_DATA(osbuf)); + + register_get->gpioreg_id = gpioreg_id; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_GET_CMDID, + NO_SYNC_WMIFLAG)); +} + +/* Send a command to the Target acknowledging some GPIO interrupts. */ +A_STATUS +wmi_gpio_intr_ack(struct wmi_t *wmip, + A_UINT32 ack_mask) +{ + void *osbuf; + WMIX_GPIO_INTR_ACK_CMD *intr_ack; + int size; + + size = sizeof(*intr_ack); + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter ack_mask=0x%x\n", DBGARG, ack_mask)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + intr_ack = (WMIX_GPIO_INTR_ACK_CMD *)(A_NETBUF_DATA(osbuf)); + + intr_ack->ack_mask = ack_mask; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_INTR_ACK_CMDID, + NO_SYNC_WMIFLAG)); +} +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +A_STATUS +wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT16 txop, A_UINT8 eCWmin, + A_UINT8 eCWmax, A_UINT8 aifsn) +{ + void *osbuf; + WMI_SET_ACCESS_PARAMS_CMD *cmd; + + if ((eCWmin > WMI_MAX_CW_ACPARAM) || (eCWmax > WMI_MAX_CW_ACPARAM) || + (aifsn > WMI_MAX_AIFSN_ACPARAM)) + { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_ACCESS_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->txop = txop; + cmd->eCWmin = eCWmin; + cmd->eCWmax = eCWmax; + cmd->aifsn = aifsn; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_ACCESS_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType, + A_UINT8 trafficClass, A_UINT8 maxRetries, + A_UINT8 enableNotify) +{ + void *osbuf; + WMI_SET_RETRY_LIMITS_CMD *cmd; + + if ((frameType != MGMT_FRAMETYPE) && (frameType != CONTROL_FRAMETYPE) && + (frameType != DATA_FRAMETYPE)) + { + return A_EINVAL; + } + + if (maxRetries > WMI_MAX_RETRIES) { + return A_EINVAL; + } + + if (frameType != DATA_FRAMETYPE) { + trafficClass = 0; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_RETRY_LIMITS_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->frameType = frameType; + cmd->trafficClass = trafficClass; + cmd->maxRetries = maxRetries; + cmd->enableNotify = enableNotify; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_RETRY_LIMITS_CMDID, + NO_SYNC_WMIFLAG)); +} + +void +wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid) +{ + if (bssid != NULL) { + A_MEMCPY(bssid, wmip->wmi_bssid, ATH_MAC_LEN); + } +} + +A_STATUS +wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode) +{ + void *osbuf; + WMI_SET_OPT_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_OPT_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->optMode = optMode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_OPT_MODE_CMDID, + SYNC_BOTH_WMIFLAG)); +} + +A_STATUS +wmi_opt_tx_frame_cmd(struct wmi_t *wmip, + A_UINT8 frmType, + A_UINT8 *dstMacAddr, + A_UINT8 *bssid, + A_UINT16 optIEDataLen, + A_UINT8 *optIEData) +{ + void *osbuf; + WMI_OPT_TX_FRAME_CMD *cmd; + osbuf = A_NETBUF_ALLOC(optIEDataLen + sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, (optIEDataLen + sizeof(*cmd))); + + cmd = (WMI_OPT_TX_FRAME_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, (optIEDataLen + sizeof(*cmd)-1)); + + cmd->frmType = frmType; + cmd->optIEDataLen = optIEDataLen; + //cmd->optIEData = (A_UINT8 *)((int)cmd + sizeof(*cmd)); + A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid)); + A_MEMCPY(cmd->dstAddr, dstMacAddr, sizeof(cmd->dstAddr)); + A_MEMCPY(&cmd->optIEData[0], optIEData, optIEDataLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_OPT_TX_FRAME_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl) +{ + void *osbuf; + WMI_BEACON_INT_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_BEACON_INT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->beaconInterval = intvl; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BEACON_INT_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize) +{ + void *osbuf; + WMI_SET_VOICE_PKT_SIZE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_VOICE_PKT_SIZE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->voicePktSize = voicePktSize; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_VOICE_PKT_SIZE_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSPLen) +{ + void *osbuf; + WMI_SET_MAX_SP_LEN_CMD *cmd; + + /* maxSPLen is a two-bit value. If user trys to set anything + * other than this, then its invalid + */ + if(maxSPLen & ~0x03) + return A_EINVAL; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_MAX_SP_LEN_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->maxSPLen = maxSPLen; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_MAX_SP_LEN_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_UINT8 +wmi_determine_userPriority( + A_UINT8 *pkt, + A_UINT32 layer2Pri) +{ + A_UINT8 ipPri; + iphdr *ipHdr = (iphdr *)pkt; + + /* Determine IPTOS priority */ + /* + * IP Tos format : + * (Refer Pg 57 WMM-test-plan-v1.2) + * IP-TOS - 8bits + * : DSCP(6-bits) ECN(2-bits) + * : DSCP - P2 P1 P0 X X X + * where (P2 P1 P0) form 802.1D + */ + ipPri = ipHdr->ip_tos >> 5; + ipPri &= 0x7; + + if ((layer2Pri & 0x7) > ipPri) + return ((A_UINT8)layer2Pri & 0x7); + else + return ipPri; +} + +A_UINT8 +convert_userPriority_to_trafficClass(A_UINT8 userPriority) +{ + return (up_to_ac[userPriority & 0x7]); +} + +A_UINT8 +wmi_get_power_mode_cmd(struct wmi_t *wmip) +{ + return wmip->wmi_powerMode; +} + +A_STATUS +wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance) +{ + A_STATUS ret = A_OK; + +#define TSPEC_SUSPENSION_INTERVAL_ATHEROS_DEF (~0) +#define TSPEC_SERVICE_START_TIME_ATHEROS_DEF 0 +#define TSPEC_MAX_BURST_SIZE_ATHEROS_DEF 0 +#define TSPEC_DELAY_BOUND_ATHEROS_DEF 0 +#define TSPEC_MEDIUM_TIME_ATHEROS_DEF 0 +#define TSPEC_SBA_ATHEROS_DEF 0x2000 /* factor is 1 */ + + /* Verify TSPEC params for ATHEROS compliance */ + if(tspecCompliance == ATHEROS_COMPLIANCE) { + if ((pCmd->suspensionInt != TSPEC_SUSPENSION_INTERVAL_ATHEROS_DEF) || + (pCmd->serviceStartTime != TSPEC_SERVICE_START_TIME_ATHEROS_DEF) || + (pCmd->minDataRate != pCmd->meanDataRate) || + (pCmd->minDataRate != pCmd->peakDataRate) || + (pCmd->maxBurstSize != TSPEC_MAX_BURST_SIZE_ATHEROS_DEF) || + (pCmd->delayBound != TSPEC_DELAY_BOUND_ATHEROS_DEF) || + (pCmd->sba != TSPEC_SBA_ATHEROS_DEF) || + (pCmd->mediumTime != TSPEC_MEDIUM_TIME_ATHEROS_DEF)) { + + A_DPRINTF(DBG_WMI, (DBGFMT "Invalid TSPEC params\n", DBGARG)); + //A_PRINTF("%s: Invalid TSPEC params\n", __func__); + ret = A_EINVAL; + } + } + + return ret; +} + +#ifdef CONFIG_HOST_TCMD_SUPPORT +static A_STATUS +wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TCMD_RX_REPORT_EVENT(wmip->wmi_devt, datap, len); + + return A_OK; +} + +#endif /* CONFIG_HOST_TCMD_SUPPORT*/ + +A_STATUS +wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode) +{ + void *osbuf; + WMI_SET_AUTH_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_AUTH_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->mode = mode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_AUTH_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode) +{ + void *osbuf; + WMI_SET_REASSOC_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_REASSOC_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->mode = mode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_REASSOC_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status) +{ + void *osbuf; + WMI_SET_LPREAMBLE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_LPREAMBLE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->status = status; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_LPREAMBLE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold) +{ + void *osbuf; + WMI_SET_RTS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_RTS_CMD*)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->threshold = threshold; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_RTS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status) +{ + void *osbuf; + WMI_SET_WMM_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_WMM_CMD*)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->status = status; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_CMDID, + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG cfg) +{ + void *osbuf; + WMI_SET_WMM_TXOP_CMD *cmd; + + if( !((cfg == WMI_TXOP_DISABLED) || (cfg == WMI_TXOP_ENABLED)) ) + return A_EINVAL; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_WMM_TXOP_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->txopEnable = cfg; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_TXOP_CMDID, + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_set_country(struct wmi_t *wmip, A_UCHAR *countryCode) +{ + void *osbuf; + WMI_AP_SET_COUNTRY_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_AP_SET_COUNTRY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + A_MEMCPY(cmd->countryCode,countryCode,3); + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_COUNTRY_CMDID, + NO_SYNC_WMIFLAG)); +} + +#ifdef CONFIG_HOST_TCMD_SUPPORT +/* WMI layer doesn't need to know the data type of the test cmd. + This would be beneficial for customers like Qualcomm, who might + have different test command requirements from differnt manufacturers + */ +A_STATUS +wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32 len) +{ + void *osbuf; + char *data; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + osbuf= A_NETBUF_ALLOC(len); + if(osbuf == NULL) + { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, len); + data = A_NETBUF_DATA(osbuf); + A_MEMCPY(data, buf, len); + + return(wmi_cmd_send(wmip, osbuf, WMI_TEST_CMDID, + NO_SYNC_WMIFLAG)); +} + +#endif + +A_STATUS +wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status) +{ + void *osbuf; + WMI_SET_BT_STATUS_CMD *cmd; + + ATHR_DISPLAY_MSG (_T("Enter - streamType=%d, status=%d\n"), streamType, status); + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_BT_STATUS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->streamType = streamType; + cmd->status = status; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_STATUS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd) +{ + void *osbuf; + WMI_SET_BT_PARAMS_CMD* alloc_cmd; + + ATHR_DISPLAY_MSG (_T("cmd params is %d\n"), cmd->paramType); + + if (cmd->paramType == BT_PARAM_SCO) { + ATHR_DISPLAY_MSG (_T("sco params %d %d %d %d %d %d %d %d %d %d %d %d\n"), + cmd->info.scoParams.numScoCyclesForceTrigger, + cmd->info.scoParams.dataResponseTimeout, + cmd->info.scoParams.stompScoRules, + cmd->info.scoParams.scoOptFlags, + cmd->info.scoParams.p2lrpOptModeBound, + cmd->info.scoParams.p2lrpNonOptModeBound, + cmd->info.scoParams.stompDutyCyleVal, + cmd->info.scoParams.stompDutyCyleMaxVal, + cmd->info.scoParams.psPollLatencyFraction, + cmd->info.scoParams.noSCOSlots, + cmd->info.scoParams.noIdleSlots, + cmd->info.scoParams.reserved8); + } + else if (cmd->paramType == BT_PARAM_A2DP) { + ATHR_DISPLAY_MSG (_T("A2DP params %d %d %d %d %d %d %d %d %d\n"), + cmd->info.a2dpParams.a2dpWlanUsageLimit, + cmd->info.a2dpParams.a2dpBurstCntMin, + cmd->info.a2dpParams.a2dpDataRespTimeout, + cmd->info.a2dpParams.a2dpOptFlags, + cmd->info.a2dpParams.p2lrpOptModeBound, + cmd->info.a2dpParams.p2lrpNonOptModeBound, + cmd->info.a2dpParams.reserved16, + cmd->info.a2dpParams.isCoLocatedBtRoleMaster, + cmd->info.a2dpParams.reserved8); + } + else if (cmd->paramType == BT_PARAM_ANTENNA_CONFIG) { + ATHR_DISPLAY_MSG (_T("Ant config %d\n"), cmd->info.antType); + } + else if (cmd->paramType == BT_PARAM_COLOCATED_BT_DEVICE) { + ATHR_DISPLAY_MSG (_T("co-located BT %d\n"), cmd->info.coLocatedBtDev); + } + else if (cmd->paramType == BT_PARAM_ACLCOEX) { + ATHR_DISPLAY_MSG (_T("ACL params %d %d %d\n"), cmd->info.aclCoexParams.aclWlanMediumUsageTime, + cmd->info.aclCoexParams.aclBtMediumUsageTime, + cmd->info.aclCoexParams.aclDataRespTimeout); + } + else if (cmd->paramType == BT_PARAM_11A_SEPARATE_ANT) { + A_DPRINTF(DBG_WMI, (DBGFMT "11A ant\n", DBGARG)); + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + alloc_cmd = (WMI_SET_BT_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(alloc_cmd, sizeof(*cmd)); + A_MEMCPY(alloc_cmd, cmd, sizeof(*cmd)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_keepalive_configured(struct wmi_t *wmip) +{ + void *osbuf; + WMI_GET_KEEPALIVE_CMD *cmd; + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + cmd = (WMI_GET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + return (wmi_cmd_send(wmip, osbuf, WMI_GET_KEEPALIVE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_UINT8 +wmi_get_keepalive_cmd(struct wmi_t *wmip) +{ + return wmip->wmi_keepaliveInterval; +} + +A_STATUS +wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval) +{ + void *osbuf; + WMI_SET_KEEPALIVE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->keepaliveInterval = keepaliveInterval; + wmip->wmi_keepaliveInterval = keepaliveInterval; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_KEEPALIVE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_params_cmd(struct wmi_t *wmip, A_UINT32 opcode, A_UINT32 length, A_CHAR* buffer) +{ + void *osbuf; + WMI_SET_PARAMS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd) + length); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd) + length); + + cmd = (WMI_SET_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->opcode = opcode; + cmd->length = length; + A_MEMCPY(cmd->buffer, buffer, length); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4) +{ + void *osbuf; + WMI_SET_MCAST_FILTER_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->multicast_mac[0] = 0x01; + cmd->multicast_mac[1] = 0x00; + cmd->multicast_mac[2] = 0x5e; + cmd->multicast_mac[3] = dot2&0x7F; + cmd->multicast_mac[4] = dot3; + cmd->multicast_mac[5] = dot4; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_MCAST_FILTER_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_del_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4) +{ + void *osbuf; + WMI_SET_MCAST_FILTER_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->multicast_mac[0] = 0x01; + cmd->multicast_mac[1] = 0x00; + cmd->multicast_mac[2] = 0x5e; + cmd->multicast_mac[3] = dot2&0x7F; + cmd->multicast_mac[4] = dot3; + cmd->multicast_mac[5] = dot4; + + return (wmi_cmd_send(wmip, osbuf, WMI_DEL_MCAST_FILTER_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType, A_UINT8 ieLen, + A_UINT8 *ieInfo) +{ + void *osbuf; + WMI_SET_APPIE_CMD *cmd; + A_UINT16 cmdLen; + + cmdLen = sizeof(*cmd) + ieLen - 1; + osbuf = A_NETBUF_ALLOC(cmdLen); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, cmdLen); + + cmd = (WMI_SET_APPIE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + + cmd->mgmtFrmType = mgmtFrmType; + cmd->ieLen = ieLen; + A_MEMCPY(cmd->ieInfo, ieInfo, ieLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_APPIE_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen) +{ + void *osbuf; + A_UINT8 *data; + + osbuf = A_NETBUF_ALLOC(dataLen); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, dataLen); + + data = A_NETBUF_DATA(osbuf); + + A_MEMCPY(data, cmd, dataLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WHALPARAM_CMDID, NO_SYNC_WMIFLAG)); +} + +A_INT32 +wmi_get_rate(A_INT8 rateindex) +{ + if (rateindex == RATE_AUTO) { + return 0; + } else { + return(wmi_rateTable[(A_UINT32) rateindex]); + } +} + +void +wmi_node_return (struct wmi_t *wmip, bss_t *bss) +{ + if (NULL != bss) + { + wlan_node_return (&wmip->wmi_scan_table, bss); + } +} + +void +wmi_set_nodeage(struct wmi_t *wmip, A_UINT32 nodeAge) +{ + wlan_set_nodeage(&wmip->wmi_scan_table,nodeAge); +} + +bss_t * +wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID) +{ + bss_t *node = NULL; + node = wlan_find_Ssidnode (&wmip->wmi_scan_table, pSsid, + ssidLength, bIsWPA2, bMatchSSID); + return node; +} + + +void +wmi_free_allnodes(struct wmi_t *wmip) +{ + wlan_free_allnodes(&wmip->wmi_scan_table); +} + +bss_t * +wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr) +{ + bss_t *ni=NULL; + ni=wlan_find_node(&wmip->wmi_scan_table,macaddr); + return ni; +} + +void +wmi_free_node(struct wmi_t *wmip, const A_UINT8 *macaddr) +{ + bss_t *ni=NULL; + + ni=wlan_find_node(&wmip->wmi_scan_table,macaddr); + if (ni != NULL) { + wlan_node_reclaim(&wmip->wmi_scan_table, ni); + } + + return; +} + +A_STATUS +wmi_dset_open_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT32 access_cookie, + A_UINT32 dset_size, + A_UINT32 dset_version, + A_UINT32 targ_handle, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg) +{ + void *osbuf; + WMIX_DSETOPEN_REPLY_CMD *open_reply; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter - wmip=0x%x\n", DBGARG, (int)wmip)); + + osbuf = A_NETBUF_ALLOC(sizeof(*open_reply)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*open_reply)); + open_reply = (WMIX_DSETOPEN_REPLY_CMD *)(A_NETBUF_DATA(osbuf)); + + open_reply->status = status; + open_reply->targ_dset_handle = targ_handle; + open_reply->targ_reply_fn = targ_reply_fn; + open_reply->targ_reply_arg = targ_reply_arg; + open_reply->access_cookie = access_cookie; + open_reply->size = dset_size; + open_reply->version = dset_version; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETOPEN_REPLY_CMDID, + NO_SYNC_WMIFLAG)); +} + +static A_STATUS +wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len) +{ + WMI_PMKID_LIST_REPLY *reply; + A_UINT32 expected_len; + + if (len < sizeof(WMI_PMKID_LIST_REPLY)) { + return A_EINVAL; + } + reply = (WMI_PMKID_LIST_REPLY *)datap; + expected_len = sizeof(reply->numPMKID) + reply->numPMKID * WMI_PMKID_LEN; + + if (len < expected_len) { + return A_EINVAL; + } + + A_WMI_PMKID_LIST_EVENT(wmip->wmi_devt, reply->numPMKID, + reply->pmkidList, reply->bssidList[0]); + + return A_OK; +} + + +static A_STATUS +wmi_set_params_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len) +{ + WMI_SET_PARAMS_REPLY *reply; + + if (len < sizeof(WMI_SET_PARAMS_REPLY)) { + return A_EINVAL; + } + reply = (WMI_SET_PARAMS_REPLY *)datap; + + if (A_OK == reply->status) + { + + } + else + { + + } + + return A_OK; +} + + + +#ifdef CONFIG_HOST_DSET_SUPPORT +A_STATUS +wmi_dset_data_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT8 *user_buf, + A_UINT32 length, + A_UINT32 targ_buf, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg) +{ + void *osbuf; + WMIX_DSETDATA_REPLY_CMD *data_reply; + int size; + + size = sizeof(*data_reply) + length; + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - length=%d status=%d\n", DBGARG, length, status)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + data_reply = (WMIX_DSETDATA_REPLY_CMD *)(A_NETBUF_DATA(osbuf)); + + data_reply->status = status; + data_reply->targ_buf = targ_buf; + data_reply->targ_reply_fn = targ_reply_fn; + data_reply->targ_reply_arg = targ_reply_arg; + data_reply->length = length; + + if (status == A_OK) { + if (a_copy_from_user(data_reply->buf, user_buf, length)) { + return A_ERROR; + } + } + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETDATA_REPLY_CMDID, + NO_SYNC_WMIFLAG)); +} +#endif /* CONFIG_HOST_DSET_SUPPORT */ + +A_STATUS +wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status) +{ + void *osbuf; + char *cmd; + + osbuf = a_netbuf_alloc(sizeof(1)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + a_netbuf_put(osbuf, sizeof(1)); + + cmd = (char *)(a_netbuf_to_data(osbuf)); + + A_MEMZERO(cmd, sizeof(*cmd)); + cmd[0] = (status?1:0); + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WSC_STATUS_CMDID, + NO_SYNC_WMIFLAG)); +} + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +A_STATUS +wmi_prof_cfg_cmd(struct wmi_t *wmip, + A_UINT32 period, + A_UINT32 nbins) +{ + void *osbuf; + WMIX_PROF_CFG_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_PROF_CFG_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->period = period; + cmd->nbins = nbins; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_PROF_CFG_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_prof_addr_set_cmd(struct wmi_t *wmip, A_UINT32 addr) +{ + void *osbuf; + WMIX_PROF_ADDR_SET_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_PROF_ADDR_SET_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->addr = addr; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_PROF_ADDR_SET_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_prof_start_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_START_CMDID); +} + +A_STATUS +wmi_prof_stop_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_STOP_CMDID); +} + +A_STATUS +wmi_prof_count_get_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_COUNT_GET_CMDID); +} + +/* Called to handle WMIX_PROF_CONT_EVENTID */ +static A_STATUS +wmi_prof_count_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_PROF_COUNT_EVENT *prof_data = (WMIX_PROF_COUNT_EVENT *)datap; + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - addr=0x%x count=%d\n", DBGARG, + prof_data->addr, prof_data->count)); + + A_WMI_PROF_COUNT_RX(prof_data->addr, prof_data->count); + + return A_OK; +} +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + +#ifdef OS_ROAM_MANAGEMENT + +#define ETHERNET_MAC_ADDRESS_LENGTH 6 + +void +wmi_scan_indication (struct wmi_t *wmip) +{ + struct ieee80211_node_table *nt; + A_UINT32 gen; + A_UINT32 size; + A_UINT32 bsssize; + bss_t *bss; + A_UINT32 numbss; + PNDIS_802_11_BSSID_SCAN_INFO psi; + PBYTE pie; + NDIS_802_11_FIXED_IEs *pFixed; + NDIS_802_11_VARIABLE_IEs *pVar; + A_UINT32 RateSize; + + struct ar6kScanIndication + { + NDIS_802_11_STATUS_INDICATION ind; + NDIS_802_11_BSSID_SCAN_INFO_LIST slist; + } *pAr6kScanIndEvent; + + nt = &wmip->wmi_scan_table; + + ++nt->nt_si_gen; + + + gen = nt->nt_si_gen; + + size = offsetof(struct ar6kScanIndication, slist) + + offsetof(NDIS_802_11_BSSID_SCAN_INFO_LIST, BssidScanInfo); + + numbss = 0; + + IEEE80211_NODE_LOCK(nt); + + //calc size + for (bss = nt->nt_node_first; bss; bss = bss->ni_list_next) { + if (bss->ni_si_gen != gen) { + bsssize = offsetof(NDIS_802_11_BSSID_SCAN_INFO, Bssid) + offsetof(NDIS_WLAN_BSSID_EX, IEs); + bsssize = bsssize + sizeof(NDIS_802_11_FIXED_IEs); + +#ifdef SUPPORT_WPA2 + if (bss->ni_cie.ie_rsn) { + bsssize = bsssize + bss->ni_cie.ie_rsn[1] + 2; + } +#endif + if (bss->ni_cie.ie_wpa) { + bsssize = bsssize + bss->ni_cie.ie_wpa[1] + 2; + } + + // bsssize must be a multiple of 4 to maintain alignment. + bsssize = (bsssize + 3) & ~3; + + size += bsssize; + + numbss++; + } + } + + if (0 == numbss) + { +// RETAILMSG(1, (L"AR6K: scan indication: 0 bss\n")); + ar6000_scan_indication (wmip->wmi_devt, NULL, 0); + IEEE80211_NODE_UNLOCK (nt); + return; + } + + pAr6kScanIndEvent = A_MALLOC(size); + + if (NULL == pAr6kScanIndEvent) + { + IEEE80211_NODE_UNLOCK(nt); + return; + } + + A_MEMZERO(pAr6kScanIndEvent, size); + + //copy data + pAr6kScanIndEvent->ind.StatusType = Ndis802_11StatusType_BssidScanInfoList; + pAr6kScanIndEvent->slist.Version = 1; + pAr6kScanIndEvent->slist.NumItems = numbss; + + psi = &pAr6kScanIndEvent->slist.BssidScanInfo[0]; + + for (bss = nt->nt_node_first; bss; bss = bss->ni_list_next) { + if (bss->ni_si_gen != gen) { + + bss->ni_si_gen = gen; + + //Set scan time + psi->ScanTime = bss->ni_tstamp - WLAN_NODE_INACT_TIMEOUT_MSEC; + + // Copy data to bssid_ex + bsssize = offsetof(NDIS_WLAN_BSSID_EX, IEs); + bsssize = bsssize + sizeof(NDIS_802_11_FIXED_IEs); + +#ifdef SUPPORT_WPA2 + if (bss->ni_cie.ie_rsn) { + bsssize = bsssize + bss->ni_cie.ie_rsn[1] + 2; + } +#endif + if (bss->ni_cie.ie_wpa) { + bsssize = bsssize + bss->ni_cie.ie_wpa[1] + 2; + } + + // bsssize must be a multiple of 4 to maintain alignment. + bsssize = (bsssize + 3) & ~3; + + psi->Bssid.Length = bsssize; + + memcpy (psi->Bssid.MacAddress, bss->ni_macaddr, ETHERNET_MAC_ADDRESS_LENGTH); + + +//if (((bss->ni_macaddr[3] == 0xCE) && (bss->ni_macaddr[4] == 0xF0) && (bss->ni_macaddr[5] == 0xE7)) || +// ((bss->ni_macaddr[3] == 0x03) && (bss->ni_macaddr[4] == 0xE2) && (bss->ni_macaddr[5] == 0x70))) +// RETAILMSG (1, (L"%x\n",bss->ni_macaddr[5])); + + psi->Bssid.Ssid.SsidLength = 0; + pie = bss->ni_cie.ie_ssid; + + if (pie) { + // Format of SSID IE is: + // Type (1 octet) + // Length (1 octet) + // SSID (Length octets) + // + // Validation of the IE should have occurred within WMI. + // + if (pie[1] <= 32) { + psi->Bssid.Ssid.SsidLength = pie[1]; + memcpy(psi->Bssid.Ssid.Ssid, &pie[2], psi->Bssid.Ssid.SsidLength); + } + } + psi->Bssid.Privacy = (bss->ni_cie.ie_capInfo & 0x10) ? 1 : 0; + + //Post the RSSI value relative to the Standard Noise floor value. + psi->Bssid.Rssi = bss->ni_rssi; + + if (bss->ni_cie.ie_chan >= 2412 && bss->ni_cie.ie_chan <= 2484) { + + if (bss->ni_cie.ie_rates && bss->ni_cie.ie_xrates) { + psi->Bssid.NetworkTypeInUse = Ndis802_11OFDM24; + } + else { + psi->Bssid.NetworkTypeInUse = Ndis802_11DS; + } + } + else { + psi->Bssid.NetworkTypeInUse = Ndis802_11OFDM5; + } + + psi->Bssid.Configuration.Length = sizeof(psi->Bssid.Configuration); + psi->Bssid.Configuration.BeaconPeriod = bss->ni_cie.ie_beaconInt; // Units are Kmicroseconds (1024 us) + psi->Bssid.Configuration.ATIMWindow = 0; + psi->Bssid.Configuration.DSConfig = bss->ni_cie.ie_chan * 1000; + psi->Bssid.InfrastructureMode = ((bss->ni_cie.ie_capInfo & 0x03) == 0x01 ) ? Ndis802_11Infrastructure : Ndis802_11IBSS; + + RateSize = 0; + pie = bss->ni_cie.ie_rates; + if (pie) { + RateSize = (pie[1] < NDIS_802_11_LENGTH_RATES_EX) ? pie[1] : NDIS_802_11_LENGTH_RATES_EX; + memcpy(psi->Bssid.SupportedRates, &pie[2], RateSize); + } + pie = bss->ni_cie.ie_xrates; + if (pie && RateSize < NDIS_802_11_LENGTH_RATES_EX) { + memcpy(psi->Bssid.SupportedRates + RateSize, &pie[2], + (pie[1] < (NDIS_802_11_LENGTH_RATES_EX - RateSize)) ? pie[1] : (NDIS_802_11_LENGTH_RATES_EX - RateSize)); + } + + // Copy the fixed IEs + psi->Bssid.IELength = sizeof(NDIS_802_11_FIXED_IEs); + + pFixed = (NDIS_802_11_FIXED_IEs *)psi->Bssid.IEs; + memcpy(pFixed->Timestamp, bss->ni_cie.ie_tstamp, sizeof(pFixed->Timestamp)); + pFixed->BeaconInterval = bss->ni_cie.ie_beaconInt; + pFixed->Capabilities = bss->ni_cie.ie_capInfo; + + // Copy selected variable IEs + + pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pFixed + sizeof(NDIS_802_11_FIXED_IEs)); + +#ifdef SUPPORT_WPA2 + // Copy the WPAv2 IE + if (bss->ni_cie.ie_rsn) { + pie = bss->ni_cie.ie_rsn; + psi->Bssid.IELength += pie[1] + 2; + memcpy(pVar, pie, pie[1] + 2); + pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pVar + pie[1] + 2); + } +#endif + // Copy the WPAv1 IE + if (bss->ni_cie.ie_wpa) { + pie = bss->ni_cie.ie_wpa; + psi->Bssid.IELength += pie[1] + 2; + memcpy(pVar, pie, pie[1] + 2); + pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pVar + pie[1] + 2); + } + + // Advance buffer pointer + psi = (PNDIS_802_11_BSSID_SCAN_INFO)((BYTE*)psi + bsssize + FIELD_OFFSET(NDIS_802_11_BSSID_SCAN_INFO, Bssid)); + } + } + + IEEE80211_NODE_UNLOCK(nt); + +// wmi_free_allnodes(wmip); + +// RETAILMSG(1, (L"AR6K: scan indication: %u bss\n", numbss)); + + ar6000_scan_indication (wmip->wmi_devt, pAr6kScanIndEvent, size); + + A_FREE(pAr6kScanIndEvent); +} +#endif + +A_UINT8 +ar6000_get_upper_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, + A_UINT32 size) +{ + A_UINT32 index; + A_UINT8 threshold = (A_UINT8)sq_thresh->upper_threshold[size - 1]; + + /* The list is already in sorted order. Get the next lower value */ + for (index = 0; index < size; index ++) { + if (rssi < sq_thresh->upper_threshold[index]) { + threshold = (A_UINT8)sq_thresh->upper_threshold[index]; + break; + } + } + + return threshold; +} + +A_UINT8 +ar6000_get_lower_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, + A_UINT32 size) +{ + A_UINT32 index; + A_UINT8 threshold = (A_UINT8)sq_thresh->lower_threshold[size - 1]; + + /* The list is already in sorted order. Get the next lower value */ + for (index = 0; index < size; index ++) { + if (rssi > sq_thresh->lower_threshold[index]) { + threshold = (A_UINT8)sq_thresh->lower_threshold[index]; + break; + } + } + + return threshold; +} +static A_STATUS +wmi_send_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd) +{ + void *osbuf; + A_INT8 size; + WMI_RSSI_THRESHOLD_PARAMS_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_RSSI_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, rssiCmd, sizeof(WMI_RSSI_THRESHOLD_PARAMS_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_RSSI_THRESHOLD_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} +static A_STATUS +wmi_send_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd) +{ + void *osbuf; + A_INT8 size; + WMI_SNR_THRESHOLD_PARAMS_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + cmd = (WMI_SNR_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, snrCmd, sizeof(WMI_SNR_THRESHOLD_PARAMS_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SNR_THRESHOLD_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_target_event_report_cmd(struct wmi_t *wmip, WMI_SET_TARGET_EVENT_REPORT_CMD* cmd) +{ + void *osbuf; + WMI_SET_TARGET_EVENT_REPORT_CMD* alloc_cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + alloc_cmd = (WMI_SET_TARGET_EVENT_REPORT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(alloc_cmd, sizeof(*cmd)); + A_MEMCPY(alloc_cmd, cmd, sizeof(*cmd)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_TARGET_EVENT_REPORT_CMDID, + NO_SYNC_WMIFLAG)); +} + +#ifdef PYXIS_ADHOC +A_STATUS +wmi_set_pyxis_gen_config (struct wmi_t *wmip, A_UINT32 dataWindowSizeMin, A_UINT32 dataWindowSizeMax, A_UINT8 maxJoiners) +{ + void *osbuf; + WMI_PYXIS_GEN_CONFIG *cmd = NULL; + A_UINT16 cmdLen; + + cmdLen = sizeof (WMI_PYXIS_CONFIG_HDR) + sizeof (dataWindowSizeMin) + sizeof (dataWindowSizeMax) + sizeof (maxJoiners); + + osbuf = A_NETBUF_ALLOC (cmdLen); + + if (osbuf == NULL) + { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, cmdLen); + + cmd = (WMI_PYXIS_GEN_CONFIG *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + + cmd->hdr.pyxisConfigType = WMI_PYXIS_GEN_PARAMS; + cmd->hdr.pyxisConfigLen = sizeof (dataWindowSizeMin) + sizeof (dataWindowSizeMax) + sizeof (maxJoiners); + cmd->dataWindowSizeMin = dataWindowSizeMin; + cmd->dataWindowSizeMax = dataWindowSizeMax; + cmd->maxJoiners = maxJoiners; + + return (wmi_cmd_send (wmip, osbuf, WMI_PYXIS_CONFIG_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_pyxis_dscvr_config (struct wmi_t *wmip, A_UINT32 dscvrWindow, A_UINT32 dscvrInterval, + A_UINT32 probeInterval, A_UINT32 probePeriod, A_UINT16 dscvrChannel) +{ + void *osbuf; + WMI_PYXIS_DSCVR_CONFIG *cmd = NULL; + A_UINT16 cmdLen; + + cmdLen = sizeof (WMI_PYXIS_DSCVR_CONFIG); + + osbuf = A_NETBUF_ALLOC (cmdLen); + + if (osbuf == NULL) + { + return A_NO_MEMORY; + } + + A_NETBUF_PUT (osbuf, cmdLen); + + cmd = (WMI_PYXIS_DSCVR_CONFIG *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + + cmd->hdr.pyxisConfigType = WMI_PYXIS_DSCVR_PARAMS; + cmd->hdr.pyxisConfigLen = sizeof (WMI_PYXIS_DSCVR_CONFIG) - sizeof (WMI_PYXIS_CONFIG_HDR); + cmd->dscvrWindow = dscvrWindow; + cmd->dscvrInterval = dscvrInterval; + cmd->dscvrLife = 0; // to be defined + cmd->probeInterval = probeInterval; + cmd->probePeriod = probePeriod; + cmd->dscvrChannel = dscvrChannel; + + return (wmi_cmd_send(wmip, osbuf, WMI_PYXIS_CONFIG_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_pyxis_join_cmd (struct wmi_t *wmip, NETWORK_TYPE wmiNetworkType, + DOT11_AUTH_MODE dot11AuthMode, AUTH_MODE authMode, + CRYPTO_TYPE pairwiseCrypto, A_UINT8 pairwiseCryptoLen, + CRYPTO_TYPE groupCrypto, A_UINT8 groupCryptoLen, + A_UINT8 *bssid, A_UINT8 *nwBSSID, A_UINT16 channel, A_UINT32 ctrl_flags + ) +{ + void *osbuf; + WMI_PYXIS_JOIN_CMD *cmd = NULL; + A_UINT16 cmdLen; + + if ((pairwiseCrypto == NONE_CRYPT) && (groupCrypto != NONE_CRYPT)) { + return A_EINVAL; + } + + if ((pairwiseCrypto != NONE_CRYPT) && (groupCrypto == NONE_CRYPT)) { + return A_EINVAL; + } + + cmdLen = sizeof (WMI_PYXIS_JOIN_CMD); + + osbuf = A_NETBUF_ALLOC (cmdLen); + + if (osbuf == NULL) + { + return A_NO_MEMORY; + } + + A_NETBUF_PUT (osbuf, cmdLen); + + cmd = (WMI_PYXIS_JOIN_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + + cmd->hdr.pyxisCmd = WMI_PYXIS_JOIN_PEER; + cmd->hdr.pyxisCmdLen = sizeof (WMI_PYXIS_JOIN_CMD) - sizeof (WMI_PYXIS_CMD_HDR); + + if (NULL != cmd->peerMacAddr) + { + memcpy (cmd->peerMacAddr, bssid, ATH_MAC_LEN); + } + if (NULL != cmd->nwBSSID) + { + memcpy (cmd->nwBSSID, nwBSSID, ATH_MAC_LEN); + } + + cmd->networkType = wmiNetworkType; + cmd->dot11AuthMode = dot11AuthMode; + cmd->authMode = authMode; + cmd->pairwiseCryptoType = pairwiseCrypto; + cmd->pairwiseCryptoLen = pairwiseCryptoLen; + cmd->groupCryptoType = groupCrypto; + cmd->groupCryptoLen = groupCryptoLen; + cmd->channel = channel; + cmd->ctrl_flags = ctrl_flags; + + if (wmi_set_keepalive_cmd(wmip, wmip->wmi_keepaliveInterval) != A_OK) { + return(A_ERROR); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_PYXIS_OPERATION_CMDID, NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_pyxis_disconnect_cmd (struct wmi_t *wmip, A_UINT8 *bssid) +{ + void *osbuf; + WMI_PYXIS_DISCONNECT_CMD *cmd = NULL; + A_UINT16 cmdLen; + + cmdLen = sizeof (WMI_PYXIS_DISCONNECT_CMD); + + osbuf = A_NETBUF_ALLOC (cmdLen); + + if (osbuf == NULL) + { + return A_NO_MEMORY; + } + + A_NETBUF_PUT (osbuf, cmdLen); + + cmd = (WMI_PYXIS_DISCONNECT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + + cmd->hdr.pyxisCmd = WMI_PYXIS_DISC_PEER; + cmd->hdr.pyxisCmdLen = ATH_MAC_LEN; + memcpy (cmd->peerMacAddr, bssid, ATH_MAC_LEN); + + return (wmi_cmd_send (wmip, osbuf, WMI_PYXIS_OPERATION_CMDID, NO_SYNC_WMIFLAG)); +} + +#endif +bss_t *wmi_rm_current_bss (struct wmi_t *wmip, A_UINT8 *id) +{ + wmi_get_current_bssid (wmip, id); + return wlan_node_remove (&wmip->wmi_scan_table, id); +} + +A_STATUS wmi_add_current_bss (struct wmi_t *wmip, A_UINT8 *id, bss_t *bss) +{ + wlan_setup_node (&wmip->wmi_scan_table, bss, id); + return A_OK; +} + +//////////////////////////////////////////////////////////////////////////////// +//// //// +//// AP mode functions //// +//// //// +//////////////////////////////////////////////////////////////////////////////// +/* + * IOCTL: AR6000_XIOCTL_AP_COMMIT_CONFIG + * + * When AR6K in AP mode, This command will be called after + * changing ssid, channel etc. It will pass the profile to + * target with a flag which will indicate which parameter changed, + * also if this flag is 0, there was no change in parametes, so + * commit cmd will not be sent to target. Without calling this IOCTL + * the changes will not take effect. + */ +A_STATUS +wmi_ap_profile_commit(struct wmi_t *wmip, WMI_CONNECT_CMD *p) +{ + void *osbuf; + WMI_CONNECT_CMD *cm; + + osbuf = A_NETBUF_ALLOC(sizeof(*cm)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cm)); + cm = (WMI_CONNECT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cm, sizeof(*cm)); + + A_MEMCPY(cm,p,sizeof(*cm)); + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_CONFIG_COMMIT_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_HIDDEN_SSID + * + * This command will be used to enable/disable hidden ssid functioanlity of + * beacon. If it is enabled, ssid will be NULL in beacon. + */ +A_STATUS +wmi_ap_set_hidden_ssid(struct wmi_t *wmip, A_UINT8 hidden_ssid) +{ + void *osbuf; + WMI_AP_HIDDEN_SSID_CMD *hs; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_HIDDEN_SSID_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_HIDDEN_SSID_CMD)); + hs = (WMI_AP_HIDDEN_SSID_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(hs, sizeof(*hs)); + + hs->hidden_ssid = hidden_ssid; + + A_DPRINTF(DBG_WMI, (DBGFMT "AR6000_XIOCTL_AP_HIDDEN_SSID %d\n", DBGARG , hidden_ssid)); + return (wmi_cmd_send(wmip, osbuf, WMI_AP_HIDDEN_SSID_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_SET_MAX_NUM_STA + * + * This command is used to limit max num of STA that can connect + * with this AP. This value should not exceed AP_MAX_NUM_STA (this + * is max num of STA supported by AP). Value was already validated + * in ioctl.c + */ +A_STATUS +wmi_ap_set_num_sta(struct wmi_t *wmip, A_UINT8 num_sta) +{ + void *osbuf; + WMI_AP_SET_NUM_STA_CMD *ns; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_NUM_STA_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_NUM_STA_CMD)); + ns = (WMI_AP_SET_NUM_STA_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(ns, sizeof(*ns)); + + ns->num_sta = num_sta; + + A_DPRINTF(DBG_WMI, (DBGFMT "AR6000_XIOCTL_AP_SET_MAX_NUM_STA %d\n", DBGARG , num_sta)); + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_NUM_STA_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_SET_ACL_MAC + * + * This command is used to send list of mac of STAs which will + * be allowed to connect with this AP. When this list is empty + * firware will allow all STAs till the count reaches AP_MAX_NUM_STA. + */ +A_STATUS +wmi_ap_acl_mac_list(struct wmi_t *wmip, WMI_AP_ACL_MAC_CMD *acl) +{ + void *osbuf; + WMI_AP_ACL_MAC_CMD *a; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_ACL_MAC_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_ACL_MAC_CMD)); + a = (WMI_AP_ACL_MAC_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(a, sizeof(*a)); + A_MEMCPY(a,acl,sizeof(*acl)); + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_ACL_MAC_LIST_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_SET_MLME + * + * This command is used to send list of mac of STAs which will + * be allowed to connect with this AP. When this list is empty + * firware will allow all STAs till the count reaches AP_MAX_NUM_STA. + */ +A_STATUS +wmi_ap_set_mlme(struct wmi_t *wmip, A_UINT8 cmd, A_UINT8 *mac, A_UINT16 reason) +{ + void *osbuf; + WMI_AP_SET_MLME_CMD *mlme; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_MLME_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_MLME_CMD)); + mlme = (WMI_AP_SET_MLME_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(mlme, sizeof(*mlme)); + + mlme->cmd = cmd; + A_MEMCPY(mlme->mac, mac, ATH_MAC_LEN); + mlme->reason = reason; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_MLME_CMDID, NO_SYNC_WMIFLAG)); +} + +static A_STATUS +wmi_pspoll_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_PSPOLL_EVENT *ev; + + if (len < sizeof(WMI_PSPOLL_EVENT)) { + return A_EINVAL; + } + ev = (WMI_PSPOLL_EVENT *)datap; + + A_WMI_PSPOLL_EVENT(wmip->wmi_devt, ev->aid); + return A_OK; +} + +static A_STATUS +wmi_dtimexpiry_event_rx(struct wmi_t *wmip, A_UINT8 *datap,int len) +{ + A_WMI_DTIMEXPIRY_EVENT(wmip->wmi_devt); + return A_OK; +} + +A_STATUS +wmi_set_pvb_cmd(struct wmi_t *wmip, A_UINT16 aid, A_BOOL flag) +{ + WMI_AP_SET_PVB_CMD *cmd; + void *osbuf = NULL; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_PVB_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_PVB_CMD)); + cmd = (WMI_AP_SET_PVB_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->aid = aid; + cmd->flag = flag; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_PVB_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_ap_conn_inact_time(struct wmi_t *wmip, A_UINT32 period) +{ + WMI_AP_CONN_INACT_CMD *cmd; + void *osbuf = NULL; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_CONN_INACT_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_CONN_INACT_CMD)); + cmd = (WMI_AP_CONN_INACT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->period = period; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_CONN_INACT_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_ap_bgscan_time(struct wmi_t *wmip, A_UINT32 period, A_UINT32 dwell) +{ + WMI_AP_PROT_SCAN_TIME_CMD *cmd; + void *osbuf = NULL; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_PROT_SCAN_TIME_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_PROT_SCAN_TIME_CMD)); + cmd = (WMI_AP_PROT_SCAN_TIME_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->period_min = period; + cmd->dwell_ms = dwell; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_PROT_SCAN_TIME_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_ap_set_dtim(struct wmi_t *wmip, A_UINT8 dtim) +{ + WMI_AP_SET_DTIM_CMD *cmd; + void *osbuf = NULL; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_DTIM_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_DTIM_CMD)); + cmd = (WMI_AP_SET_DTIM_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->dtim = dtim; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_DTIM_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_SET_ACL_POLICY + * + * This command is used to set ACL policay. While changing policy, if you + * want to retain the existing MAC addresses in the ACL list, policy should be + * OR with AP_ACL_RETAIN_LIST_MASK, else the existing list will be cleared. + * If there is no chage in policy, the list will be intact. + */ +A_STATUS +wmi_ap_set_acl_policy(struct wmi_t *wmip, A_UINT8 policy) +{ + void *osbuf; + WMI_AP_ACL_POLICY_CMD *po; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_ACL_POLICY_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_ACL_POLICY_CMD)); + po = (WMI_AP_ACL_POLICY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(po, sizeof(*po)); + + po->policy = policy; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_ACL_POLICY_CMDID, NO_SYNC_WMIFLAG)); +} + diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/wmi.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wmi.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/wmi.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wmi.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,2256 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +/* + * This file contains the definitions of the WMI protocol specified in the + * Wireless Module Interface (WMI). It includes definitions of all the + * commands and events. Commands are messages from the host to the WM. + * Events and Replies are messages from the WM to the host. + * + * Ownership of correctness in regards to WMI commands + * belongs to the host driver and the WM is not required to validate + * parameters for value, proper range, or any other checking. + * + */ + +#ifndef _WMI_H_ +#define _WMI_H_ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#include "wmix.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HTC_PROTOCOL_VERSION 0x0002 +#define HTC_PROTOCOL_REVISION 0x0000 + +#define WMI_PROTOCOL_VERSION 0x0002 +#define WMI_PROTOCOL_REVISION 0x0000 + +#define ATH_MAC_LEN 6 /* length of mac in bytes */ +#define WMI_CMD_MAX_LEN 100 +#define WMI_CONTROL_MSG_MAX_LEN 256 +#define WMI_OPT_CONTROL_MSG_MAX_LEN 1536 +#define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600) +#define RFC1042OUI {0x00, 0x00, 0x00} + +#define IP_ETHERTYPE 0x0800 + +#define WMI_IMPLICIT_PSTREAM 0xFF +#define WMI_MAX_THINSTREAM 15 + +struct host_app_area_s { + A_UINT32 wmi_protocol_ver; +}; + +/* + * Data Path + */ +typedef PREPACK struct { + A_UINT8 dstMac[ATH_MAC_LEN]; + A_UINT8 srcMac[ATH_MAC_LEN]; + A_UINT16 typeOrLen; +} POSTPACK ATH_MAC_HDR; + +typedef PREPACK struct { + A_UINT8 dsap; + A_UINT8 ssap; + A_UINT8 cntl; + A_UINT8 orgCode[3]; + A_UINT16 etherType; +} POSTPACK ATH_LLC_SNAP_HDR; + +typedef enum { + DATA_MSGTYPE = 0x0, + CNTL_MSGTYPE, + SYNC_MSGTYPE, + OPT_MSGTYPE, +} WMI_MSG_TYPE; + + +typedef PREPACK struct { + A_INT8 rssi; + A_UINT8 info; /* WMI_MSG_TYPE in lower 2 bits - b1b0 */ + /* UP in next 3 bits - b4b3b2 */ +#define WMI_DATA_HDR_MSG_TYPE_MASK 0x03 +#define WMI_DATA_HDR_MSG_TYPE_SHIFT 0 +#define WMI_DATA_HDR_UP_MASK 0x07 +#define WMI_DATA_HDR_UP_SHIFT 2 +#define WMI_DATA_HDR_IS_MSG_TYPE(h, t) (((h)->info & (WMI_DATA_HDR_MSG_TYPE_MASK)) == (t)) +/* In AP mode, the same bit (b5) is used to indicate Power save state in + * the Rx dir and More data bit state in the tx direction. + */ +#define WMI_DATA_HDR_PS_MASK 0x1 +#define WMI_DATA_HDR_PS_SHIFT 5 + +#define WMI_DATA_HDR_MORE_MASK 0x1 +#define WMI_DATA_HDR_MORE_SHIFT 5 + +#define WMI_DATA_HDR_SET_MORE_BIT(h) ((h)->info |= (WMI_DATA_HDR_MORE_MASK << WMI_DATA_HDR_MORE_SHIFT)) + +} POSTPACK WMI_DATA_HDR; + + +#define WMI_DATA_HDR_SET_MSG_TYPE(h, t) (h)->info = (((h)->info & ~(WMI_DATA_HDR_MSG_TYPE_MASK << WMI_DATA_HDR_MSG_TYPE_SHIFT)) | (t << WMI_DATA_HDR_MSG_TYPE_SHIFT)) +#define WMI_DATA_HDR_SET_UP(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_UP_MASK << WMI_DATA_HDR_UP_SHIFT)) | (p << WMI_DATA_HDR_UP_SHIFT)) + +/* + * Control Path + */ +typedef PREPACK struct { + A_UINT16 commandId; +} POSTPACK WMI_CMD_HDR; /* used for commands and events */ + +/* + * List of Commnands + */ +typedef enum { + WMI_CONNECT_CMDID = 0x0001, + WMI_RECONNECT_CMDID, + WMI_DISCONNECT_CMDID, + WMI_SYNCHRONIZE_CMDID, + WMI_CREATE_PSTREAM_CMDID, + WMI_DELETE_PSTREAM_CMDID, + WMI_START_SCAN_CMDID, + WMI_SET_SCAN_PARAMS_CMDID, + WMI_SET_BSS_FILTER_CMDID, + WMI_SET_PROBED_SSID_CMDID, /* 10 */ + WMI_SET_LISTEN_INT_CMDID, + WMI_SET_BMISS_TIME_CMDID, + WMI_SET_DISC_TIMEOUT_CMDID, + WMI_GET_CHANNEL_LIST_CMDID, + WMI_SET_BEACON_INT_CMDID, + WMI_GET_STATISTICS_CMDID, + WMI_SET_CHANNEL_PARAMS_CMDID, + WMI_SET_POWER_MODE_CMDID, + WMI_SET_IBSS_PM_CAPS_CMDID, + WMI_SET_POWER_PARAMS_CMDID, /* 20 */ + WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID, + WMI_ADD_CIPHER_KEY_CMDID, + WMI_DELETE_CIPHER_KEY_CMDID, + WMI_ADD_KRK_CMDID, + WMI_DELETE_KRK_CMDID, + WMI_SET_PMKID_CMDID, + WMI_SET_TX_PWR_CMDID, + WMI_GET_TX_PWR_CMDID, + WMI_SET_ASSOC_INFO_CMDID, + WMI_ADD_BAD_AP_CMDID, /* 30 */ + WMI_DELETE_BAD_AP_CMDID, + WMI_SET_TKIP_COUNTERMEASURES_CMDID, + WMI_RSSI_THRESHOLD_PARAMS_CMDID, + WMI_TARGET_ERROR_REPORT_BITMASK_CMDID, + WMI_SET_ACCESS_PARAMS_CMDID, + WMI_SET_RETRY_LIMITS_CMDID, + WMI_SET_OPT_MODE_CMDID, + WMI_OPT_TX_FRAME_CMDID, + WMI_SET_VOICE_PKT_SIZE_CMDID, + WMI_SET_MAX_SP_LEN_CMDID, /* 40 */ + WMI_SET_ROAM_CTRL_CMDID, + WMI_GET_ROAM_TBL_CMDID, + WMI_GET_ROAM_DATA_CMDID, + WMI_ENABLE_RM_CMDID, + WMI_SET_MAX_OFFHOME_DURATION_CMDID, + WMI_EXTENSION_CMDID, /* Non-wireless extensions */ + WMI_SNR_THRESHOLD_PARAMS_CMDID, + WMI_LQ_THRESHOLD_PARAMS_CMDID, + WMI_SET_LPREAMBLE_CMDID, + WMI_SET_RTS_CMDID, /* 50 */ + WMI_CLR_RSSI_SNR_CMDID, + WMI_SET_FIXRATES_CMDID, + WMI_GET_FIXRATES_CMDID, + WMI_SET_AUTH_MODE_CMDID, + WMI_SET_REASSOC_MODE_CMDID, + WMI_SET_WMM_CMDID, + WMI_SET_WMM_TXOP_CMDID, + WMI_TEST_CMDID, + WMI_SET_BT_STATUS_CMDID, + WMI_SET_BT_PARAMS_CMDID, /* 60 */ + + WMI_SET_KEEPALIVE_CMDID, + WMI_GET_KEEPALIVE_CMDID, + WMI_SET_APPIE_CMDID, + WMI_GET_APPIE_CMDID, + WMI_SET_WSC_STATUS_CMDID, + + /* Wake on Wireless */ + WMI_SET_HOST_SLEEP_MODE_CMDID, + WMI_SET_WOW_MODE_CMDID, + WMI_GET_WOW_LIST_CMDID, + WMI_ADD_WOW_PATTERN_CMDID, + WMI_DEL_WOW_PATTERN_CMDID, /* 70 */ + + WMI_SET_FRAMERATES_CMDID, + /* + * Developer commands starts at 0xF000 + */ + WMI_SET_BITRATE_CMDID = 0xF000, + WMI_GET_BITRATE_CMDID, + WMI_SET_WHALPARAM_CMDID, + + + /*Should add the new command to the tail for compatible with + * etna. + */ + WMI_SET_MAC_ADDRESS_CMDID, + WMI_SET_AKMP_PARAMS_CMDID, + WMI_SET_PMKID_LIST_CMDID, + WMI_GET_PMKID_LIST_CMDID, + WMI_ABORT_SCAN_CMDID, + WMI_SET_TARGET_EVENT_REPORT_CMDID, + + // Pyxis specific Command IDs + WMI_PYXIS_CONFIG_CMDID, + WMI_PYXIS_OPERATION_CMDID, /* 0xF00A */ + + /* + * AP mode commands + */ + WMI_AP_HIDDEN_SSID_CMDID, + WMI_AP_SET_NUM_STA_CMDID, + WMI_AP_ACL_POLICY_CMDID, + WMI_AP_ACL_MAC_LIST_CMDID, + WMI_AP_CONFIG_COMMIT_CMDID, + WMI_AP_SET_MLME_CMDID, + WMI_AP_SET_PVB_CMDID, + WMI_AP_CONN_INACT_CMDID, + WMI_AP_PROT_SCAN_TIME_CMDID, + WMI_AP_SET_COUNTRY_CMDID, /* 0xF014 */ + WMI_AP_SET_DTIM_CMDID, + + WMI_SET_IP_CMDID, + WMI_SET_PARAMS_CMDID, + WMI_SET_MCAST_FILTER_CMDID, + WMI_DEL_MCAST_FILTER_CMDID, + WMI_FORCE_TARGET_ASSERT_CMDID +} WMI_COMMAND_ID; + +/* + * Frame Types + */ +typedef enum { + WMI_FRAME_BEACON = 0, + WMI_FRAME_PROBE_REQ, + WMI_FRAME_PROBE_RESP, + WMI_FRAME_ASSOC_REQ, + WMI_FRAME_ASSOC_RESP, + WMI_NUM_MGMT_FRAME +} WMI_MGMT_FRAME_TYPE; + +/* + * Connect Command + */ +typedef enum { + INFRA_NETWORK = 0x01, + ADHOC_NETWORK = 0x02, + ADHOC_CREATOR = 0x04, + OPT_NETWORK = 0x08, + AP_NETWORK = 0x10, +} NETWORK_TYPE; + +typedef enum { + OPEN_AUTH = 0x01, + SHARED_AUTH = 0x02, + LEAP_AUTH = 0x04, /* different from IEEE_AUTH_MODE definitions */ +} DOT11_AUTH_MODE; + +typedef enum { + NONE_AUTH = 0x01, + WPA_AUTH = 0x02, + WPA_PSK_AUTH = 0x03, + WPA2_AUTH = 0x04, + WPA2_PSK_AUTH = 0x05, + WPA_AUTH_CCKM = 0x06, + WPA2_AUTH_CCKM = 0x07, +} AUTH_MODE; + +typedef enum { + NONE_CRYPT = 0x01, + WEP_CRYPT = 0x02, + TKIP_CRYPT = 0x03, + AES_CRYPT = 0x04, +#ifdef WAPI_ENABLE + WAPI_CRYPT = 0x05, +#endif /* WAPI_ENABLE */ +} CRYPTO_TYPE; + +#define WMI_MIN_CRYPTO_TYPE NONE_CRYPT +#ifndef WAPI_ENABLE +#define WMI_MAX_CRYPTO_TYPE (AES_CRYPT + 1) +#else +#define WMI_MAX_CRYPTO_TYPE (WAPI_CRYPT + 1) +#endif /* WAPI_ENABLE */ + +#define WMI_MIN_KEY_INDEX 0 +#ifndef WAPI_ENABLE +#define WMI_MAX_KEY_INDEX 3 +#else +#define WMI_MAX_KEY_INDEX 7 /* wapi grpKey 0-3, prwKey 4-7 */ +#endif + +#define WMI_MAX_KEY_LEN 32 + +#define WMI_MAX_SSID_LEN 32 + +typedef enum { + CONNECT_ASSOC_POLICY_USER = 0x0001, + CONNECT_SEND_REASSOC = 0x0002, + CONNECT_IGNORE_WPAx_GROUP_CIPHER = 0x0004, + CONNECT_PROFILE_MATCH_DONE = 0x0008, + CONNECT_IGNORE_AAC_BEACON = 0x0010, + CONNECT_CSA_FOLLOW_BSS = 0x0020, + CONNECT_PYXIS_REMOTE = 0x0040, +} WMI_CONNECT_CTRL_FLAGS_BITS; + +#define DEFAULT_CONNECT_CTRL_FLAGS (CONNECT_CSA_FOLLOW_BSS) + +typedef PREPACK struct { + A_UINT8 networkType; + A_UINT8 dot11AuthMode; + A_UINT8 authMode; + A_UINT8 pairwiseCryptoType; + A_UINT8 pairwiseCryptoLen; + A_UINT8 groupCryptoType; + A_UINT8 groupCryptoLen; + A_UINT8 ssidLength; + A_UCHAR ssid[WMI_MAX_SSID_LEN]; + A_UINT16 channel; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT32 ctrl_flags; +} POSTPACK WMI_CONNECT_CMD; + +/* + * WMI_RECONNECT_CMDID + */ +typedef PREPACK struct { + A_UINT16 channel; /* hint */ + A_UINT8 bssid[ATH_MAC_LEN]; /* mandatory if set */ +} POSTPACK WMI_RECONNECT_CMD; + +/* + * WMI_ADD_CIPHER_KEY_CMDID + */ +typedef enum { + PAIRWISE_USAGE = 0x00, + GROUP_USAGE = 0x01, + TX_USAGE = 0x02, /* default Tx Key - Static WEP only */ +} KEY_USAGE; + +/* + * Bit Flag + * Bit 0 - Initialise TSC - default is Initialize + */ +#define KEY_OP_INIT_TSC 0x01 +#define KEY_OP_INIT_RSC 0x02 +#ifdef WAPI_ENABLE +#define KEY_OP_INIT_WAPIPN 0x10 +#endif + +#define KEY_OP_INIT_VAL 0x03 /* Default Initialise the TSC & RSC */ +#define KEY_OP_VALID_MASK 0x03 + +typedef PREPACK struct { + A_UINT8 keyIndex; + A_UINT8 keyType; + A_UINT8 keyUsage; /* KEY_USAGE */ + A_UINT8 keyLength; + A_UINT8 keyRSC[8]; /* key replay sequence counter */ + A_UINT8 key[WMI_MAX_KEY_LEN]; + A_UINT8 key_op_ctrl; /* Additional Key Control information */ + A_UINT8 key_macaddr[ATH_MAC_LEN]; +} POSTPACK WMI_ADD_CIPHER_KEY_CMD; + +/* + * WMI_DELETE_CIPHER_KEY_CMDID + */ +typedef PREPACK struct { + A_UINT8 keyIndex; +} POSTPACK WMI_DELETE_CIPHER_KEY_CMD; + +#define WMI_KRK_LEN 16 +/* + * WMI_ADD_KRK_CMDID + */ +typedef PREPACK struct { + A_UINT8 krk[WMI_KRK_LEN]; +} POSTPACK WMI_ADD_KRK_CMD; + +/* + * WMI_SET_TKIP_COUNTERMEASURES_CMDID + */ +typedef enum { + WMI_TKIP_CM_DISABLE = 0x0, + WMI_TKIP_CM_ENABLE = 0x1, +} WMI_TKIP_CM_CONTROL; + +typedef PREPACK struct { + A_UINT8 cm_en; /* WMI_TKIP_CM_CONTROL */ +} POSTPACK WMI_SET_TKIP_COUNTERMEASURES_CMD; + +/* + * WMI_SET_PMKID_CMDID + */ + +#define WMI_PMKID_LEN 16 + +typedef enum { + PMKID_DISABLE = 0, + PMKID_ENABLE = 1, +} PMKID_ENABLE_FLG; + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT8 enable; /* PMKID_ENABLE_FLG */ + A_UINT8 pmkid[WMI_PMKID_LEN]; +} POSTPACK WMI_SET_PMKID_CMD; + +/* + * WMI_START_SCAN_CMD + */ +typedef enum { + WMI_LONG_SCAN = 0, + WMI_SHORT_SCAN = 1, + WMI_PYXIS_PAS_DSCVR = 0, + WMI_PYXIS_ACT_DSCVR = 1, +} WMI_SCAN_TYPE; + +typedef PREPACK struct { + A_BOOL forceFgScan; + A_BOOL isLegacy; /* For Legacy Cisco AP compatibility */ + A_UINT32 homeDwellTime; /* Maximum duration in the home channel(milliseconds) */ + A_UINT32 forceScanInterval; /* Time interval between scans (milliseconds)*/ + A_UINT8 scanType; /* WMI_SCAN_TYPE */ + A_UINT8 numChannels; /* how many channels follow */ + A_UINT16 channelList[1]; /* channels in Mhz */ +} POSTPACK WMI_START_SCAN_CMD; + +/* + * WMI_SET_SCAN_PARAMS_CMDID + */ +#define WMI_SHORTSCANRATIO_DEFAULT 3 +typedef enum { + CONNECT_SCAN_CTRL_FLAGS = 0x01, /* set if can scan in the Connect cmd */ + SCAN_CONNECTED_CTRL_FLAGS = 0x02, /* set if scan for the SSID it is */ + /* already connected to */ + ACTIVE_SCAN_CTRL_FLAGS = 0x04, /* set if enable active scan */ + ROAM_SCAN_CTRL_FLAGS = 0x08, /* set if enable roam scan when bmiss and lowrssi */ + REPORT_BSSINFO_CTRL_FLAGS = 0x10, /* set if follows customer BSSINFO reporting rule */ + ENABLE_AUTO_CTRL_FLAGS = 0x20, /* if disabled, target doesn't + scan after a disconnect event */ + ENABLE_SCAN_ABORT_EVENT = 0x40 /* Scan complete event with canceled status will be generated when a scan is prempted before it gets completed */ + +} WMI_SCAN_CTRL_FLAGS_BITS; + +#define CAN_SCAN_IN_CONNECT(flags) (flags & CONNECT_SCAN_CTRL_FLAGS) +#define CAN_SCAN_CONNECTED(flags) (flags & SCAN_CONNECTED_CTRL_FLAGS) +#define ENABLE_ACTIVE_SCAN(flags) (flags & ACTIVE_SCAN_CTRL_FLAGS) +#define ENABLE_ROAM_SCAN(flags) (flags & ROAM_SCAN_CTRL_FLAGS) +#define CONFIG_REPORT_BSSINFO(flags) (flags & REPORT_BSSINFO_CTRL_FLAGS) +#define IS_AUTO_SCAN_ENABLED(flags) (flags & ENABLE_AUTO_CTRL_FLAGS) +#define SCAN_ABORT_EVENT_ENABLED(flags) (flags & ENABLE_SCAN_ABORT_EVENT) + +#define DEFAULT_SCAN_CTRL_FLAGS (CONNECT_SCAN_CTRL_FLAGS| SCAN_CONNECTED_CTRL_FLAGS| ACTIVE_SCAN_CTRL_FLAGS| ROAM_SCAN_CTRL_FLAGS | ENABLE_AUTO_CTRL_FLAGS) + + +typedef PREPACK struct { + A_UINT16 fg_start_period; /* seconds */ + A_UINT16 fg_end_period; /* seconds */ + A_UINT16 bg_period; /* seconds */ + A_UINT16 maxact_chdwell_time; /* msec */ + A_UINT16 pas_chdwell_time; /* msec */ + A_UINT8 shortScanRatio; /* how many shorts scan for one long */ + A_UINT8 scanCtrlFlags; + A_UINT16 minact_chdwell_time; /* msec */ + A_UINT16 maxact_scan_per_ssid; /* max active scans per ssid */ + A_UINT32 max_dfsch_act_time; /* msecs */ +} POSTPACK WMI_SCAN_PARAMS_CMD; + +/* + * WMI_SET_BSS_FILTER_CMDID + */ +typedef enum { + NONE_BSS_FILTER = 0x0, /* no beacons forwarded */ + ALL_BSS_FILTER, /* all beacons forwarded */ + PROFILE_FILTER, /* only beacons matching profile */ + ALL_BUT_PROFILE_FILTER, /* all but beacons matching profile */ + CURRENT_BSS_FILTER, /* only beacons matching current BSS */ + ALL_BUT_BSS_FILTER, /* all but beacons matching BSS */ + PROBED_SSID_FILTER, /* beacons matching probed ssid */ + LAST_BSS_FILTER, /* marker only */ +} WMI_BSS_FILTER; + +typedef PREPACK struct { + A_UINT8 bssFilter; /* see WMI_BSS_FILTER */ + A_UINT8 reserved1; /* For alignment */ + A_UINT16 reserved2; /* For alignment */ + A_UINT32 ieMask; +} POSTPACK WMI_BSS_FILTER_CMD; + +/* + * WMI_SET_PROBED_SSID_CMDID + */ +#define MAX_PROBED_SSID_INDEX 5 + +typedef enum { + DISABLE_SSID_FLAG = 0, /* disables entry */ + SPECIFIC_SSID_FLAG = 0x01, /* probes specified ssid */ + ANY_SSID_FLAG = 0x02, /* probes for any ssid */ +} WMI_SSID_FLAG; + +typedef PREPACK struct { + A_UINT8 entryIndex; /* 0 to MAX_PROBED_SSID_INDEX */ + A_UINT8 flag; /* WMI_SSID_FLG */ + A_UINT8 ssidLength; + A_UINT8 ssid[32]; +} POSTPACK WMI_PROBED_SSID_CMD; + +/* + * WMI_SET_LISTEN_INT_CMDID + * The Listen interval is between 15 and 3000 TUs + */ +#define MIN_LISTEN_INTERVAL 15 +#define MAX_LISTEN_INTERVAL 5000 +#define MIN_LISTEN_BEACONS 1 +#define MAX_LISTEN_BEACONS 50 + +typedef PREPACK struct { + A_UINT16 listenInterval; + A_UINT16 numBeacons; +} POSTPACK WMI_LISTEN_INT_CMD; + +/* + * WMI_SET_BEACON_INT_CMDID + */ +typedef PREPACK struct { + A_UINT16 beaconInterval; +} POSTPACK WMI_BEACON_INT_CMD; + +/* + * WMI_SET_BMISS_TIME_CMDID + * valid values are between 1000 and 5000 TUs + */ + +#define MIN_BMISS_TIME 1000 +#define MAX_BMISS_TIME 5000 +#define MIN_BMISS_BEACONS 1 +#define MAX_BMISS_BEACONS 50 + +typedef PREPACK struct { + A_UINT16 bmissTime; + A_UINT16 numBeacons; +} POSTPACK WMI_BMISS_TIME_CMD; + +/* + * WMI_SET_POWER_MODE_CMDID + */ +typedef enum { + REC_POWER = 0x01, + MAX_PERF_POWER, +} WMI_POWER_MODE; + +typedef PREPACK struct { + A_UINT8 powerMode; /* WMI_POWER_MODE */ +} POSTPACK WMI_POWER_MODE_CMD; + +typedef PREPACK struct { + A_INT8 status; /* WMI_SET_PARAMS_REPLY */ +} POSTPACK WMI_SET_PARAMS_REPLY; + +typedef PREPACK struct { + A_UINT32 opcode; + A_UINT32 length; + A_CHAR buffer[1]; /* WMI_SET_PARAMS */ +} POSTPACK WMI_SET_PARAMS_CMD; + +typedef PREPACK struct { + A_UINT8 multicast_mac[ATH_MAC_LEN]; /* WMI_SET_MCAST_FILTER */ +} POSTPACK WMI_SET_MCAST_FILTER_CMD; + +/* + * WMI_SET_POWER_PARAMS_CMDID + */ +typedef enum { + IGNORE_DTIM = 0x01, + NORMAL_DTIM = 0x02, + STICK_DTIM = 0x03, +} WMI_DTIM_POLICY; + +typedef PREPACK struct { + A_UINT16 idle_period; /* msec */ + A_UINT16 pspoll_number; + A_UINT16 dtim_policy; +} POSTPACK WMI_POWER_PARAMS_CMD; + +typedef PREPACK struct { + A_UINT8 power_saving; + A_UINT8 ttl; /* number of beacon periods */ + A_UINT16 atim_windows; /* msec */ + A_UINT16 timeout_value; /* msec */ +} POSTPACK WMI_IBSS_PM_CAPS_CMD; + +/* + * WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID + */ +typedef enum { + IGNORE_TIM_ALL_QUEUES_APSD = 0, + PROCESS_TIM_ALL_QUEUES_APSD = 1, + IGNORE_TIM_SIMULATED_APSD = 2, + PROCESS_TIM_SIMULATED_APSD = 3, +} APSD_TIM_POLICY; + +typedef PREPACK struct { + A_UINT16 psPollTimeout; /* msec */ + A_UINT16 triggerTimeout; /* msec */ + A_UINT32 apsdTimPolicy; /* TIM behavior with ques APSD enabled. Default is IGNORE_TIM_ALL_QUEUES_APSD */ + A_UINT32 simulatedAPSDTimPolicy; /* TIM behavior with simulated APSD enabled. Default is PROCESS_TIM_SIMULATED_APSD */ +} POSTPACK WMI_POWERSAVE_TIMERS_POLICY_CMD; + +/* + * WMI_SET_VOICE_PKT_SIZE_CMDID + */ +typedef PREPACK struct { + A_UINT16 voicePktSize; +} POSTPACK WMI_SET_VOICE_PKT_SIZE_CMD; + +/* + * WMI_SET_MAX_SP_LEN_CMDID + */ +typedef enum { + DELIVER_ALL_PKT = 0x0, + DELIVER_2_PKT = 0x1, + DELIVER_4_PKT = 0x2, + DELIVER_6_PKT = 0x3, +} APSD_SP_LEN_TYPE; + +typedef PREPACK struct { + A_UINT8 maxSPLen; +} POSTPACK WMI_SET_MAX_SP_LEN_CMD; + +/* + * WMI_SET_DISC_TIMEOUT_CMDID + */ +typedef PREPACK struct { + A_UINT8 disconnectTimeout; /* seconds */ +} POSTPACK WMI_DISC_TIMEOUT_CMD; + +typedef enum { + UPLINK_TRAFFIC = 0, + DNLINK_TRAFFIC = 1, + BIDIR_TRAFFIC = 2, +} DIR_TYPE; + +typedef enum { + DISABLE_FOR_THIS_AC = 0, + ENABLE_FOR_THIS_AC = 1, + ENABLE_FOR_ALL_AC = 2, +} VOICEPS_CAP_TYPE; + +typedef enum { + TRAFFIC_TYPE_APERIODIC = 0, + TRAFFIC_TYPE_PERIODIC = 1, +}TRAFFIC_TYPE; + +/* + * WMI_SYNCHRONIZE_CMDID + */ +typedef PREPACK struct { + A_UINT8 dataSyncMap; +} POSTPACK WMI_SYNC_CMD; + +/* + * WMI_CREATE_PSTREAM_CMDID + */ +typedef PREPACK struct { + A_UINT32 minServiceInt; /* in milli-sec */ + A_UINT32 maxServiceInt; /* in milli-sec */ + A_UINT32 inactivityInt; /* in milli-sec */ + A_UINT32 suspensionInt; /* in milli-sec */ + A_UINT32 serviceStartTime; + A_UINT32 minDataRate; /* in bps */ + A_UINT32 meanDataRate; /* in bps */ + A_UINT32 peakDataRate; /* in bps */ + A_UINT32 maxBurstSize; + A_UINT32 delayBound; + A_UINT32 minPhyRate; /* in bps */ + A_UINT32 sba; + A_UINT32 mediumTime; + A_UINT16 nominalMSDU; /* in octects */ + A_UINT16 maxMSDU; /* in octects */ + A_UINT8 trafficClass; + A_UINT8 trafficDirection; /* DIR_TYPE */ + A_UINT8 rxQueueNum; + A_UINT8 trafficType; /* TRAFFIC_TYPE */ + A_UINT8 voicePSCapability; /* VOICEPS_CAP_TYPE */ + A_UINT8 tsid; + A_UINT8 userPriority; /* 802.1D user priority */ + A_UINT8 nominalPHY; /* nominal phy rate */ +} POSTPACK WMI_CREATE_PSTREAM_CMD; + +/* + * WMI_DELETE_PSTREAM_CMDID + */ +typedef PREPACK struct { + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficDirection; + A_UINT8 trafficClass; + A_UINT8 tsid; +} POSTPACK WMI_DELETE_PSTREAM_CMD; + +/* + * WMI_SET_CHANNEL_PARAMS_CMDID + */ +typedef enum { + WMI_11A_MODE = 0x1, + WMI_11G_MODE = 0x2, + WMI_11AG_MODE = 0x3, + WMI_11B_MODE = 0x4, + WMI_11GONLY_MODE = 0x5, +} WMI_PHY_MODE; + +#define WMI_MAX_CHANNELS 32 + +typedef PREPACK struct { + A_UINT8 reserved1; + A_UINT8 scanParam; /* set if enable scan */ + A_UINT8 phyMode; /* see WMI_PHY_MODE */ + A_UINT8 numChannels; /* how many channels follow */ + A_UINT16 channelList[1]; /* channels in Mhz */ +} POSTPACK WMI_CHANNEL_PARAMS_CMD; + + +/* + * WMI_RSSI_THRESHOLD_PARAMS_CMDID + * Setting the polltime to 0 would disable polling. + * Threshold values are in the ascending order, and should agree to: + * (lowThreshold_lowerVal < lowThreshold_upperVal < highThreshold_lowerVal + * < highThreshold_upperVal) + */ + +typedef PREPACK struct WMI_RSSI_THRESHOLD_PARAMS{ + A_UINT32 pollTime; /* Polling time as a factor of LI */ + A_INT16 thresholdAbove1_Val; /* lowest of upper */ + A_INT16 thresholdAbove2_Val; + A_INT16 thresholdAbove3_Val; + A_INT16 thresholdAbove4_Val; + A_INT16 thresholdAbove5_Val; + A_INT16 thresholdAbove6_Val; /* highest of upper */ + A_INT16 thresholdBelow1_Val; /* lowest of bellow */ + A_INT16 thresholdBelow2_Val; + A_INT16 thresholdBelow3_Val; + A_INT16 thresholdBelow4_Val; + A_INT16 thresholdBelow5_Val; + A_INT16 thresholdBelow6_Val; /* highest of bellow */ + A_UINT8 weight; /* "alpha" */ + A_UINT8 reserved[3]; +} POSTPACK WMI_RSSI_THRESHOLD_PARAMS_CMD; + +/* + * WMI_SNR_THRESHOLD_PARAMS_CMDID + * Setting the polltime to 0 would disable polling. + */ + +typedef PREPACK struct WMI_SNR_THRESHOLD_PARAMS{ + A_UINT32 pollTime; /* Polling time as a factor of LI */ + A_UINT8 weight; /* "alpha" */ + A_UINT8 thresholdAbove1_Val; /* lowest of uppper*/ + A_UINT8 thresholdAbove2_Val; + A_UINT8 thresholdAbove3_Val; + A_UINT8 thresholdAbove4_Val; /* highest of upper */ + A_UINT8 thresholdBelow1_Val; /* lowest of bellow */ + A_UINT8 thresholdBelow2_Val; + A_UINT8 thresholdBelow3_Val; + A_UINT8 thresholdBelow4_Val; /* highest of bellow */ + A_UINT8 reserved[3]; +} POSTPACK WMI_SNR_THRESHOLD_PARAMS_CMD; + +/* + * WMI_LQ_THRESHOLD_PARAMS_CMDID + */ +typedef PREPACK struct WMI_LQ_THRESHOLD_PARAMS { + A_UINT8 enable; + A_UINT8 thresholdAbove1_Val; + A_UINT8 thresholdAbove2_Val; + A_UINT8 thresholdAbove3_Val; + A_UINT8 thresholdAbove4_Val; + A_UINT8 thresholdBelow1_Val; + A_UINT8 thresholdBelow2_Val; + A_UINT8 thresholdBelow3_Val; + A_UINT8 thresholdBelow4_Val; + A_UINT8 reserved[3]; +} POSTPACK WMI_LQ_THRESHOLD_PARAMS_CMD; + +typedef enum { + WMI_LPREAMBLE_DISABLED = 0, + WMI_LPREAMBLE_ENABLED +} WMI_LPREAMBLE_STATUS; + +typedef PREPACK struct { + A_UINT8 status; +}POSTPACK WMI_SET_LPREAMBLE_CMD; + +typedef PREPACK struct { + A_UINT16 threshold; +}POSTPACK WMI_SET_RTS_CMD; + +/* + * WMI_TARGET_ERROR_REPORT_BITMASK_CMDID + * Sets the error reporting event bitmask in target. Target clears it + * upon an error. Subsequent errors are counted, but not reported + * via event, unless the bitmask is set again. + */ +typedef PREPACK struct { + A_UINT32 bitmask; +} POSTPACK WMI_TARGET_ERROR_REPORT_BITMASK; + +/* + * WMI_SET_TX_PWR_CMDID + */ +typedef PREPACK struct { + A_UINT8 dbM; /* in dbM units */ +} POSTPACK WMI_SET_TX_PWR_CMD, WMI_TX_PWR_REPLY; + +/* + * WMI_SET_ASSOC_INFO_CMDID + * + * A maximum of 2 private IEs can be sent in the [Re]Assoc request. + * A 3rd one, the CCX version IE can also be set from the host. + */ +#define WMI_MAX_ASSOC_INFO_TYPE 2 +#define WMI_CCX_VER_IE 2 /* ieType to set CCX Version IE */ + +#define WMI_MAX_ASSOC_INFO_LEN 240 + +typedef PREPACK struct { + A_UINT8 ieType; + A_UINT8 bufferSize; + A_UINT8 assocInfo[1]; /* up to WMI_MAX_ASSOC_INFO_LEN */ +} POSTPACK WMI_SET_ASSOC_INFO_CMD; + + +/* + * WMI_GET_TX_PWR_CMDID does not take any parameters + */ + +/* + * WMI_ADD_BAD_AP_CMDID + */ +#define WMI_MAX_BAD_AP_INDEX 1 + +typedef PREPACK struct { + A_UINT8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */ + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_ADD_BAD_AP_CMD; + +/* + * WMI_DELETE_BAD_AP_CMDID + */ +typedef PREPACK struct { + A_UINT8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */ +} POSTPACK WMI_DELETE_BAD_AP_CMD; + +/* + * WMI_SET_ACCESS_PARAMS_CMDID + */ +#define WMI_DEFAULT_TXOP_ACPARAM 0 /* implies one MSDU */ +#define WMI_DEFAULT_ECWMIN_ACPARAM 4 /* corresponds to CWmin of 15 */ +#define WMI_DEFAULT_ECWMAX_ACPARAM 10 /* corresponds to CWmax of 1023 */ +#define WMI_MAX_CW_ACPARAM 15 /* maximum eCWmin or eCWmax */ +#define WMI_DEFAULT_AIFSN_ACPARAM 2 +#define WMI_MAX_AIFSN_ACPARAM 15 +typedef PREPACK struct { + A_UINT16 txop; /* in units of 32 usec */ + A_UINT8 eCWmin; + A_UINT8 eCWmax; + A_UINT8 aifsn; +} POSTPACK WMI_SET_ACCESS_PARAMS_CMD; + + +/* + * WMI_SET_RETRY_LIMITS_CMDID + * + * This command is used to customize the number of retries the + * wlan device will perform on a given frame. + */ +#define WMI_MIN_RETRIES 2 +#define WMI_MAX_RETRIES 13 +typedef enum { + MGMT_FRAMETYPE = 0, + CONTROL_FRAMETYPE = 1, + DATA_FRAMETYPE = 2 +} WMI_FRAMETYPE; + +typedef PREPACK struct { + A_UINT8 frameType; /* WMI_FRAMETYPE */ + A_UINT8 trafficClass; /* applies only to DATA_FRAMETYPE */ + A_UINT8 maxRetries; + A_UINT8 enableNotify; +} POSTPACK WMI_SET_RETRY_LIMITS_CMD; + +/* + * WMI_SET_ROAM_CTRL_CMDID + * + * This command is used to influence the Roaming behaviour + * Set the host biases of the BSSs before setting the roam mode as bias + * based. + */ + +/* + * Different types of Roam Control + */ + +typedef enum { + WMI_FORCE_ROAM = 1, /* Roam to the specified BSSID */ + WMI_SET_ROAM_MODE = 2, /* default ,progd bias, no roam */ + WMI_SET_HOST_BIAS = 3, /* Set the Host Bias */ + WMI_SET_LOWRSSI_SCAN_PARAMS = 4, /* Set lowrssi Scan parameters */ +} WMI_ROAM_CTRL_TYPE; + +#define WMI_MIN_ROAM_CTRL_TYPE WMI_FORCE_ROAM +#define WMI_MAX_ROAM_CTRL_TYPE WMI_SET_LOWRSSI_SCAN_PARAMS + +/* + * ROAM MODES + */ + +typedef enum { + WMI_DEFAULT_ROAM_MODE = 1, /* RSSI based ROAM */ + WMI_HOST_BIAS_ROAM_MODE = 2, /* HOST BIAS based ROAM */ + WMI_LOCK_BSS_MODE = 3 /* Lock to the Current BSS - no Roam */ +} WMI_ROAM_MODE; + +/* + * BSS HOST BIAS INFO + */ + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_INT8 bias; +} POSTPACK WMI_BSS_BIAS; + +typedef PREPACK struct { + A_UINT8 numBss; + WMI_BSS_BIAS bssBias[1]; +} POSTPACK WMI_BSS_BIAS_INFO; + +typedef PREPACK struct WMI_LOWRSSI_SCAN_PARAMS { + A_UINT16 lowrssi_scan_period; + A_INT16 lowrssi_scan_threshold; + A_INT16 lowrssi_roam_threshold; + A_UINT8 roam_rssi_floor; + A_UINT8 reserved[1]; /* For alignment */ +} POSTPACK WMI_LOWRSSI_SCAN_PARAMS; + +typedef PREPACK struct { + PREPACK union { + A_UINT8 bssid[ATH_MAC_LEN]; /* WMI_FORCE_ROAM */ + A_UINT8 roamMode; /* WMI_SET_ROAM_MODE */ + WMI_BSS_BIAS_INFO bssBiasInfo; /* WMI_SET_HOST_BIAS */ + WMI_LOWRSSI_SCAN_PARAMS lrScanParams; + } POSTPACK info; + A_UINT8 roamCtrlType ; +} POSTPACK WMI_SET_ROAM_CTRL_CMD; + +/* + * WMI_ENABLE_RM_CMDID + */ +typedef PREPACK struct { + A_BOOL enable_radio_measurements; +} POSTPACK WMI_ENABLE_RM_CMD; + +/* + * WMI_SET_MAX_OFFHOME_DURATION_CMDID + */ +typedef PREPACK struct { + A_UINT8 max_offhome_duration; +} POSTPACK WMI_SET_MAX_OFFHOME_DURATION_CMD; + +typedef PREPACK struct { + A_UINT32 frequency; + A_UINT8 threshold; +} POSTPACK WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD; + +typedef enum { + BT_STREAM_UNDEF = 0, + BT_STREAM_SCO, /* SCO stream */ + BT_STREAM_A2DP, /* A2DP stream */ + BT_STREAM_SCAN, /* BT Discovery or Page */ + BT_STREAM_ESCO, + BT_STREAM_MAX +} BT_STREAM_TYPE; + +typedef enum { + BT_PARAM_SCO = 1, /* SCO stream parameters */ + BT_PARAM_A2DP , + BT_PARAM_ANTENNA_CONFIG, + BT_PARAM_COLOCATED_BT_DEVICE, + BT_PARAM_ACLCOEX, + BT_PARAM_11A_SEPARATE_ANT, + BT_PARAM_MAX +} BT_PARAM_TYPE; + +typedef enum { + BT_PARAM_SCO_PSPOLL_LATENCY_ONE_FOURTH =1, + BT_PARAM_SCO_PSPOLL_LATENCY_HALF, + BT_PARAM_SCO_PSPOLL_LATENCY_THREE_FOURTH, +} BT_PARAMS_SCO_PSPOLL_LATENCY; + +typedef enum { + BT_PARAMS_SCO_STOMP_SCO_NEVER =1, + BT_PARAMS_SCO_STOMP_SCO_ALWAYS, + BT_PARAMS_SCO_STOMP_SCO_IN_LOWRSSI, +} BT_PARAMS_SCO_STOMP_RULES; + +typedef enum { + BT_STATUS_UNDEF = 0, + BT_STATUS_START, + BT_STATUS_STOP, + BT_STATUS_RESUME, + BT_STATUS_SUSPEND, + BT_STATUS_MAX +} BT_STREAM_STATUS; + +typedef PREPACK struct { + A_UINT8 streamType; + A_UINT8 status; +} POSTPACK WMI_SET_BT_STATUS_CMD; + +typedef enum { + BT_ANT_TYPE_UNDEF=0, + BT_ANT_TYPE_DUAL, + BT_ANT_TYPE_SPLITTER, + BT_ANT_TYPE_SWITCH +} BT_ANT_FRONTEND_CONFIG; + +typedef enum { + BT_COLOCATED_DEV_BTS4020=0, + BT_COLCATED_DEV_CSR , + BT_COLOCATED_DEV_VALKYRIE +} BT_COLOCATED_DEV_TYPE; + +#define BT_SCO_ALLOW_CLOSE_RANGE_OPT (1 << 0) +#define BT_SCO_FORCE_AWAKE_OPT (1 << 1) +#define BT_SCO_SET_DEFAULT_OVERRIDE(flags) ((flags) |= (1 << 2)) +#define BT_SCO_GET_DEFAULT_OVERRIDE(flags) (((flags) >> 2) & 0x1) +typedef PREPACK struct { + A_UINT32 numScoCyclesForceTrigger; /* Number SCO cycles after which + force a pspoll. default = 10 */ + A_UINT32 dataResponseTimeout; /* Timeout Waiting for Downlink pkt + in response for ps-poll, + default = 10 msecs */ + A_UINT32 stompScoRules; + A_UINT32 scoOptFlags; /* SCO Options Flags : + bits: meaning: + 0 Allow Close Range Optimization + 1 Force awake during close range + 2 If set use host supplied threshold + 3 Unused + 4..7 Unused + 8..15 Unused + 16..23 Unused + */ + A_UINT32 p2lrpOptModeBound; /*p2lrp=packetToLowRatePacketRatio. In opt mode + minimum ratio required to continue in opt mode*/ + A_UINT32 p2lrpNonOptModeBound; /*In Non opt mode minimum ratio required to switch + to opt mode*/ + A_UINT8 stompDutyCyleVal; /* Sco cycles to limit ps-poll queuing + if stomped */ + A_UINT8 stompDutyCyleMaxVal; /*firm ware increases stomp duty cycle + gradually uptill this value on need basis*/ + A_UINT8 psPollLatencyFraction; /* Fraction of idle + period, within which + additional ps-polls + can be queued */ + A_UINT8 noSCOSlots; /* Number of SCO Tx/Rx slots. + HVx, EV3, 2EV3 = 2 */ + A_UINT8 noIdleSlots; /* Number of Bluetooth idle slots between + consecutive SCO Tx/Rx slots + HVx, EV3 = 4 + 2EV3 = 10 */ + A_UINT8 reserved8; /* maintain word algnment*/ +} POSTPACK BT_PARAMS_SCO; + +#define BT_A2DP_ALLOW_CLOSE_RANGE_OPT (1 << 0) +#define BT_A2DP_FORCE_AWAKE_OPT (1 << 1) +#define BT_A2DP_SET_DEFAULT_OVERRIDE(flags) ((flags) |= (1 << 2)) +#define BT_A2DP_GET_DEFAULT_OVERRIDE(flags) (((flags) >> 2) & 0x1) +typedef PREPACK struct { + A_UINT32 a2dpWlanUsageLimit; /* MAX time firmware uses the medium for + wlan, after it identifies the idle time + default (30 msecs) */ + A_UINT32 a2dpBurstCntMin; /* Minimum number of bluetooth data frames + to replenish Wlan Usage limit (default 3) */ + A_UINT32 a2dpDataRespTimeout; + A_UINT32 a2dpOptFlags; /* A2DP Option flags: + bits: meaning: + 0 Allow Close Range Optimization + 1 Force awake during close range + 2 If set use host threshold + 3 Unused + 4..7 Unused + 8..15 Unused + 16..23 Unused + */ + A_UINT32 p2lrpOptModeBound; /*p2lrp=packetToLowRatePacketRatio. In opt mode + minimum ratio required to continue in opt mode*/ + A_UINT32 p2lrpNonOptModeBound; /*In Non opt mode minimum ratio required to switch + to opt mode*/ + A_UINT16 reserved16; /*maintain word alignment*/ + A_UINT8 isCoLocatedBtRoleMaster; + A_UINT8 reserved8; /*maintain word alignment*/ +}POSTPACK BT_PARAMS_A2DP; + +/* During BT ftp/ BT OPP or any another data based acl profile on bluetooth + (non a2dp).*/ +typedef PREPACK struct { + A_UINT32 aclWlanMediumUsageTime; /* Wlan usage time during Acl (non-a2dp) + coexistence (default 30 msecs) */ + A_UINT32 aclBtMediumUsageTime; /* Bt usage time during acl coexistence + (default 30 msecs)*/ + A_UINT32 aclDataRespTimeout; + A_UINT32 aclDetectTimeout; /* ACL coexistence enabled if we get + 10 Pkts in X msec(default 100 msecs) */ + A_UINT32 aclmaxPktCnt; /* No of ACL pkts to receive before + enabling ACL coex */ + +}POSTPACK BT_PARAMS_ACLCOEX; + +typedef PREPACK struct { + A_UINT32 mode; + A_UINT32 scoWghts; + A_UINT32 a2dpWghts; + A_UINT32 genWghts; + A_UINT32 mode2; + A_UINT8 setVal; +} POSTPACK BT_COEX_REGS; + +typedef enum { + WLAN_PROTECT_POLICY = 1, + WLAN_COEX_CTRL_FLAGS +} BT_PARAMS_MISC_TYPE; + +typedef enum { + WLAN_PROTECT_PER_STREAM = 0x01, /* default */ + WLAN_PROTECT_ANY_TX = 0x02 +} WLAN_PROTECT_FLAGS; + + +#define WLAN_DISABLE_COEX_IN_DISCONNECT 0x01 /* default */ +#define WLAN_KEEP_COEX_IN_DISCONNECT 0x02 +#define WLAN_STOMPBT_IN_DISCONNECT 0x04 + +#define WLAN_DISABLE_COEX_IN_ROAM 0x10 /* default */ +#define WLAN_KEEP_COEX_IN_ROAM 0x20 +#define WLAN_STOMPBT_IN_ROAM 0x40 + +#define WLAN_DISABLE_COEX_IN_SCAN 0x100 /* default */ +#define WLAN_KEEP_COEX_IN_SCAN 0x200 +#define WLAN_STOMPBT_IN_SCAN 0x400 + +#define WLAN_DISABLE_COEX_BT_OFF 0x1000 /* default */ +#define WLAN_KEEP_COEX_BT_OFF 0x2000 +#define WLAN_STOMPBT_BT_OFF 0x4000 + +typedef PREPACK struct { + A_UINT32 period; + A_UINT32 dutycycle; + A_UINT8 stompbt; + A_UINT8 policy; +} POSTPACK WLAN_PROTECT_POLICY_TYPE; + +typedef PREPACK struct { + PREPACK union { + WLAN_PROTECT_POLICY_TYPE protectParams; + A_UINT16 configCtrlFlags; + } POSTPACK info; + A_UINT8 paramType; +} POSTPACK BT_PARAMS_MISC; + +typedef PREPACK struct { + PREPACK union { + BT_PARAMS_SCO scoParams; + BT_PARAMS_A2DP a2dpParams; + BT_PARAMS_ACLCOEX aclCoexParams; + A_UINT8 antType; /* 0 -Disabled (default) + 1 - BT_ANT_TYPE_DUAL + 2 - BT_ANT_TYPE_SPLITTER + 3 - BT_ANT_TYPE_SWITCH */ + A_UINT8 coLocatedBtDev; /* 0 - BT_COLOCATED_DEV_BTS4020 (default) + 1 - BT_COLCATED_DEV_CSR + 2 - BT_COLOCATED_DEV_VALKYRIe + */ + } POSTPACK info; + A_UINT8 paramType ; +} POSTPACK WMI_SET_BT_PARAMS_CMD; + +typedef enum { + DISCONN_EVT_IN_RECONN = 0, /* default */ + NO_DISCONN_EVT_IN_RECONN +} TARGET_EVENT_REPORT_CONFIG; + +typedef PREPACK struct { + A_UINT32 evtConfig; +} POSTPACK WMI_SET_TARGET_EVENT_REPORT_CMD; + + +/* + * Command Replies + */ + +/* + * WMI_GET_CHANNEL_LIST_CMDID reply + */ +typedef PREPACK struct { + A_UINT8 reserved1; + A_UINT8 numChannels; /* number of channels in reply */ + A_UINT16 channelList[1]; /* channel in Mhz */ +} POSTPACK WMI_CHANNEL_LIST_REPLY; + +typedef enum { + A_SUCCEEDED = A_OK, + A_FAILED_DELETE_STREAM_DOESNOT_EXIST=250, + A_SUCCEEDED_MODIFY_STREAM=251, + A_FAILED_INVALID_STREAM = 252, + A_FAILED_MAX_THINSTREAMS = 253, + A_FAILED_CREATE_REMOVE_PSTREAM_FIRST = 254, +} PSTREAM_REPLY_STATUS; + +typedef PREPACK struct { + A_UINT8 status; /* PSTREAM_REPLY_STATUS */ + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficClass; + A_UINT8 trafficDirection; /* DIR_TYPE */ +} POSTPACK WMI_CRE_PRIORITY_STREAM_REPLY; + +typedef PREPACK struct { + A_UINT8 status; /* PSTREAM_REPLY_STATUS */ + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficDirection; /* DIR_TYPE */ + A_UINT8 trafficClass; +} POSTPACK WMI_DEL_PRIORITY_STREAM_REPLY; + +/* + * List of Events (target to host) + */ +typedef enum { + WMI_READY_EVENTID = 0x1001, + WMI_CONNECT_EVENTID, + WMI_DISCONNECT_EVENTID, + WMI_BSSINFO_EVENTID, + WMI_CMDERROR_EVENTID, + WMI_REGDOMAIN_EVENTID, + WMI_PSTREAM_TIMEOUT_EVENTID, + WMI_NEIGHBOR_REPORT_EVENTID, + WMI_TKIP_MICERR_EVENTID, + WMI_SCAN_COMPLETE_EVENTID, /* 0x100a */ + WMI_REPORT_STATISTICS_EVENTID, + WMI_RSSI_THRESHOLD_EVENTID, + WMI_ERROR_REPORT_EVENTID, + WMI_OPT_RX_FRAME_EVENTID, + WMI_REPORT_ROAM_TBL_EVENTID, + WMI_EXTENSION_EVENTID, + WMI_CAC_EVENTID, + WMI_SNR_THRESHOLD_EVENTID, + WMI_LQ_THRESHOLD_EVENTID, + WMI_TX_RETRY_ERR_EVENTID, /* 0x1014 */ + WMI_REPORT_ROAM_DATA_EVENTID, + WMI_TEST_EVENTID, + WMI_APLIST_EVENTID, + WMI_GET_WOW_LIST_EVENTID, + WMI_GET_PMKID_LIST_EVENTID, + WMI_CHANNEL_CHANGE_EVENTID, + WMI_PEER_NODE_EVENTID, + WMI_PSPOLL_EVENTID, + WMI_DTIMEXPIRY_EVENTID, + WMI_WLAN_VERSION_EVENTID, + WMI_SET_PARAMS_REPLY_EVENTID +} WMI_EVENT_ID; + +typedef enum { + WMI_11A_CAPABILITY = 1, + WMI_11G_CAPABILITY = 2, + WMI_11AG_CAPABILITY = 3, +} WMI_PHY_CAPABILITY; + +typedef PREPACK struct { + A_UINT8 macaddr[ATH_MAC_LEN]; + A_UINT8 phyCapability; /* WMI_PHY_CAPABILITY */ +} POSTPACK WMI_READY_EVENT_1; + +typedef PREPACK struct { + A_UINT32 version; + A_UINT8 macaddr[ATH_MAC_LEN]; + A_UINT8 phyCapability; /* WMI_PHY_CAPABILITY */ +} POSTPACK WMI_READY_EVENT_2; + +#if defined(ATH_TARGET) +#ifdef AR6002_REV2 +#define WMI_READY_EVENT WMI_READY_EVENT_1 /* AR6002_REV2 target code */ +#else +#define WMI_READY_EVENT WMI_READY_EVENT_2 /* AR6002_REV4 and AR6001 */ +#endif +#else +#define WMI_READY_EVENT WMI_READY_EVENT_2 /* host code */ +#endif + + +/* + * Connect Event + */ +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT16 listenInterval; + A_UINT16 beaconInterval; + A_UINT32 networkType; + A_UINT8 beaconIeLen; + A_UINT8 assocReqLen; + A_UINT8 assocRespLen; + A_UINT8 assocInfo[1]; +} POSTPACK WMI_CONNECT_EVENT; + +/* + * Disconnect Event + */ +typedef enum { + NO_NETWORK_AVAIL = 0x01, + LOST_LINK = 0x02, /* bmiss */ + DISCONNECT_CMD = 0x03, + BSS_DISCONNECTED = 0x04, + AUTH_FAILED = 0x05, + ASSOC_FAILED = 0x06, + NO_RESOURCES_AVAIL = 0x07, + CSERV_DISCONNECT = 0x08, + INVALID_PROFILE = 0x0a, + DOT11H_CHANNEL_SWITCH = 0x0b, + PROFILE_MISMATCH = 0x0c, + PYXIS_VIRT_ADHOC_DISC = 0x0d, +} WMI_DISCONNECT_REASON; + +typedef PREPACK struct { + A_UINT16 protocolReasonStatus; /* reason code, see 802.11 spec. */ + A_UINT8 bssid[ATH_MAC_LEN]; /* set if known */ + A_UINT8 disconnectReason ; /* see WMI_DISCONNECT_REASON */ + A_UINT8 assocRespLen; + A_UINT8 assocInfo[1]; +} POSTPACK WMI_DISCONNECT_EVENT; + +/* + * BSS Info Event. + * Mechanism used to inform host of the presence and characteristic of + * wireless networks present. Consists of bss info header followed by + * the beacon or probe-response frame body. The 802.11 header is not included. + */ +typedef enum { + BEACON_FTYPE = 0x1, + PROBERESP_FTYPE, + ACTION_MGMT_FTYPE, + PROBEREQ_FTYPE, +} WMI_BI_FTYPE; + +enum { + BSS_ELEMID_CHANSWITCH = 0x01, + BSS_ELEMID_ATHEROS = 0x02, +}; + +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 frameType; /* see WMI_BI_FTYPE */ + A_UINT8 snr; + A_INT16 rssi; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT32 ieMask; +} POSTPACK WMI_BSS_INFO_HDR; + +/* + * Command Error Event + */ +typedef enum { + INVALID_PARAM = 0x01, + ILLEGAL_STATE = 0x02, + INTERNAL_ERROR = 0x03, +} WMI_ERROR_CODE; + +typedef PREPACK struct { + A_UINT16 commandId; + A_UINT8 errorCode; +} POSTPACK WMI_CMD_ERROR_EVENT; + +/* + * New Regulatory Domain Event + */ +typedef PREPACK struct { + A_UINT32 regDomain; +} POSTPACK WMI_REG_DOMAIN_EVENT; + +typedef PREPACK struct { + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficDirection; + A_UINT8 trafficClass; +} POSTPACK WMI_PSTREAM_TIMEOUT_EVENT; + +/* + * The WMI_NEIGHBOR_REPORT Event is generated by the target to inform + * the host of BSS's it has found that matches the current profile. + * It can be used by the host to cache PMKs and/to initiate pre-authentication + * if the BSS supports it. The first bssid is always the current associated + * BSS. + * The bssid and bssFlags information repeats according to the number + * or APs reported. + */ +typedef enum { + WMI_DEFAULT_BSS_FLAGS = 0x00, + WMI_PREAUTH_CAPABLE_BSS = 0x01, + WMI_PMKID_VALID_BSS = 0x02, +} WMI_BSS_FLAGS; + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT8 bssFlags; /* see WMI_BSS_FLAGS */ +} POSTPACK WMI_NEIGHBOR_INFO; + +typedef PREPACK struct { + A_INT8 numberOfAps; + WMI_NEIGHBOR_INFO neighbor[1]; +} POSTPACK WMI_NEIGHBOR_REPORT_EVENT; + +/* + * TKIP MIC Error Event + */ +typedef PREPACK struct { + A_UINT8 keyid; + A_UINT8 ismcast; +} POSTPACK WMI_TKIP_MICERR_EVENT; + +/* + * WMI_SCAN_COMPLETE_EVENTID - no parameters (old), staus parameter (new) + */ +typedef PREPACK struct { + A_INT32 status; +} POSTPACK WMI_SCAN_COMPLETE_EVENT; + +#define MAX_OPT_DATA_LEN 1400 + +/* + * WMI_SET_ADHOC_BSSID_CMDID + */ +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_SET_ADHOC_BSSID_CMD; + +/* + * WMI_SET_OPT_MODE_CMDID + */ +typedef enum { + SPECIAL_OFF, + SPECIAL_ON, + PYXIS_ADHOC_ON, + PYXIS_ADHOC_OFF, +} OPT_MODE_TYPE; + +typedef PREPACK struct { + A_UINT8 optMode; +} POSTPACK WMI_SET_OPT_MODE_CMD; + +/* + * WMI_TX_OPT_FRAME_CMDID + */ +typedef enum { + OPT_PROBE_REQ = 0x01, + OPT_PROBE_RESP = 0x02, + OPT_CPPP_START = 0x03, + OPT_CPPP_STOP = 0x04, +} WMI_OPT_FTYPE; + +typedef PREPACK struct { + A_UINT16 optIEDataLen; + A_UINT8 frmType; + A_UINT8 dstAddr[ATH_MAC_LEN]; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT8 reserved; /* For alignment */ + A_UINT8 optIEData[1]; +} POSTPACK WMI_OPT_TX_FRAME_CMD; + +/* + * Special frame receive Event. + * Mechanism used to inform host of the receiption of the special frames. + * Consists of special frame info header followed by special frame body. + * The 802.11 header is not included. + */ +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 frameType; /* see WMI_OPT_FTYPE */ + A_INT8 snr; + A_UINT8 srcAddr[ATH_MAC_LEN]; + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_OPT_RX_INFO_HDR; + +/* + * Reporting statistics. + */ +typedef PREPACK struct { + A_UINT32 tx_packets; + A_UINT32 tx_bytes; + A_UINT32 tx_unicast_pkts; + A_UINT32 tx_unicast_bytes; + A_UINT32 tx_multicast_pkts; + A_UINT32 tx_multicast_bytes; + A_UINT32 tx_broadcast_pkts; + A_UINT32 tx_broadcast_bytes; + A_UINT32 tx_rts_success_cnt; + A_UINT32 tx_packet_per_ac[4]; + A_UINT32 tx_errors_per_ac[4]; + + A_UINT32 tx_errors; + A_UINT32 tx_failed_cnt; + A_UINT32 tx_retry_cnt; + A_UINT32 tx_mult_retry_cnt; + A_UINT32 tx_rts_fail_cnt; + A_INT32 tx_unicast_rate; +}POSTPACK tx_stats_t; + +typedef PREPACK struct { + A_UINT32 rx_packets; + A_UINT32 rx_bytes; + A_UINT32 rx_unicast_pkts; + A_UINT32 rx_unicast_bytes; + A_UINT32 rx_multicast_pkts; + A_UINT32 rx_multicast_bytes; + A_UINT32 rx_broadcast_pkts; + A_UINT32 rx_broadcast_bytes; + A_UINT32 rx_fragment_pkt; + + A_UINT32 rx_errors; + A_UINT32 rx_crcerr; + A_UINT32 rx_key_cache_miss; + A_UINT32 rx_decrypt_err; + A_UINT32 rx_duplicate_frames; + A_INT32 rx_unicast_rate; +}POSTPACK rx_stats_t; + +typedef PREPACK struct { + A_UINT32 tkip_local_mic_failure; + A_UINT32 tkip_counter_measures_invoked; + A_UINT32 tkip_replays; + A_UINT32 tkip_format_errors; + A_UINT32 ccmp_format_errors; + A_UINT32 ccmp_replays; +}POSTPACK tkip_ccmp_stats_t; + +typedef PREPACK struct { + A_UINT32 power_save_failure_cnt; +}POSTPACK pm_stats_t; + +typedef PREPACK struct { + A_UINT32 cs_bmiss_cnt; + A_UINT32 cs_lowRssi_cnt; + A_UINT16 cs_connect_cnt; + A_UINT16 cs_disconnect_cnt; + A_INT16 cs_aveBeacon_rssi; + A_UINT16 cs_roam_count; + A_INT16 cs_rssi; + A_UINT8 cs_snr; + A_UINT8 cs_aveBeacon_snr; + A_UINT8 cs_lastRoam_msec; +} POSTPACK cserv_stats_t; + +typedef PREPACK struct { + tx_stats_t tx_stats; + rx_stats_t rx_stats; + tkip_ccmp_stats_t tkipCcmpStats; +}POSTPACK wlan_net_stats_t; + +typedef PREPACK struct { + A_UINT32 arp_received; + A_UINT32 arp_matched; + A_UINT32 arp_replied; +} POSTPACK arp_stats_t; + +typedef PREPACK struct { + A_UINT32 wow_num_pkts_dropped; + A_UINT16 wow_num_events_discarded; + A_UINT8 wow_num_host_pkt_wakeups; + A_UINT8 wow_num_host_event_wakeups; +} POSTPACK wlan_wow_stats_t; + +typedef PREPACK struct { + A_UINT32 lqVal; + A_INT32 noise_floor_calibation; + pm_stats_t pmStats; + wlan_net_stats_t txrxStats; + wlan_wow_stats_t wowStats; + arp_stats_t arpStats; + cserv_stats_t cservStats; +} POSTPACK WMI_TARGET_STATS; + +/* + * WMI_RSSI_THRESHOLD_EVENTID. + * Indicate the RSSI events to host. Events are indicated when we breach a + * thresold value. + */ +typedef enum{ + WMI_RSSI_THRESHOLD1_ABOVE = 0, + WMI_RSSI_THRESHOLD2_ABOVE, + WMI_RSSI_THRESHOLD3_ABOVE, + WMI_RSSI_THRESHOLD4_ABOVE, + WMI_RSSI_THRESHOLD5_ABOVE, + WMI_RSSI_THRESHOLD6_ABOVE, + WMI_RSSI_THRESHOLD1_BELOW, + WMI_RSSI_THRESHOLD2_BELOW, + WMI_RSSI_THRESHOLD3_BELOW, + WMI_RSSI_THRESHOLD4_BELOW, + WMI_RSSI_THRESHOLD5_BELOW, + WMI_RSSI_THRESHOLD6_BELOW +}WMI_RSSI_THRESHOLD_VAL; + +typedef PREPACK struct { + A_INT16 rssi; + A_UINT8 range; +}POSTPACK WMI_RSSI_THRESHOLD_EVENT; + +/* + * WMI_ERROR_REPORT_EVENTID + */ +typedef enum{ + WMI_TARGET_PM_ERR_FAIL = 0x00000001, + WMI_TARGET_KEY_NOT_FOUND = 0x00000002, + WMI_TARGET_DECRYPTION_ERR = 0x00000004, + WMI_TARGET_BMISS = 0x00000008, + WMI_PSDISABLE_NODE_JOIN = 0x00000010, + WMI_TARGET_COM_ERR = 0x00000020, + WMI_TARGET_FATAL_ERR = 0x00000040 +} WMI_TARGET_ERROR_VAL; + +typedef PREPACK struct { + A_UINT32 errorVal; +}POSTPACK WMI_TARGET_ERROR_REPORT_EVENT; + +typedef PREPACK struct { + A_UINT8 retrys; +}POSTPACK WMI_TX_RETRY_ERR_EVENT; + +typedef enum{ + WMI_SNR_THRESHOLD1_ABOVE = 1, + WMI_SNR_THRESHOLD1_BELOW, + WMI_SNR_THRESHOLD2_ABOVE, + WMI_SNR_THRESHOLD2_BELOW, + WMI_SNR_THRESHOLD3_ABOVE, + WMI_SNR_THRESHOLD3_BELOW, + WMI_SNR_THRESHOLD4_ABOVE, + WMI_SNR_THRESHOLD4_BELOW +} WMI_SNR_THRESHOLD_VAL; + +typedef PREPACK struct { + A_UINT8 range; /* WMI_SNR_THRESHOLD_VAL */ + A_UINT8 snr; +}POSTPACK WMI_SNR_THRESHOLD_EVENT; + +typedef enum{ + WMI_LQ_THRESHOLD1_ABOVE = 1, + WMI_LQ_THRESHOLD1_BELOW, + WMI_LQ_THRESHOLD2_ABOVE, + WMI_LQ_THRESHOLD2_BELOW, + WMI_LQ_THRESHOLD3_ABOVE, + WMI_LQ_THRESHOLD3_BELOW, + WMI_LQ_THRESHOLD4_ABOVE, + WMI_LQ_THRESHOLD4_BELOW +} WMI_LQ_THRESHOLD_VAL; + +typedef PREPACK struct { + A_INT32 lq; + A_UINT8 range; /* WMI_LQ_THRESHOLD_VAL */ +}POSTPACK WMI_LQ_THRESHOLD_EVENT; +/* + * WMI_REPORT_ROAM_TBL_EVENTID + */ +#define MAX_ROAM_TBL_CAND 5 + +typedef PREPACK struct { + A_INT32 roam_util; + A_UINT8 bssid[ATH_MAC_LEN]; + A_INT8 rssi; + A_INT8 rssidt; + A_INT8 last_rssi; + A_INT8 util; + A_INT8 bias; + A_UINT8 reserved; /* For alignment */ +} POSTPACK WMI_BSS_ROAM_INFO; + + +typedef PREPACK struct { + A_UINT16 roamMode; + A_UINT16 numEntries; + WMI_BSS_ROAM_INFO bssRoamInfo[1]; +} POSTPACK WMI_TARGET_ROAM_TBL; + +/* + * WMI_CAC_EVENTID + */ +typedef enum { + CAC_INDICATION_ADMISSION = 0x00, + CAC_INDICATION_ADMISSION_RESP = 0x01, + CAC_INDICATION_DELETE = 0x02, + CAC_INDICATION_NO_RESP = 0x03, +}CAC_INDICATION; + +#define WMM_TSPEC_IE_LEN 63 + +typedef PREPACK struct { + A_UINT8 ac; + A_UINT8 cac_indication; + A_UINT8 statusCode; + A_UINT8 tspecSuggestion[WMM_TSPEC_IE_LEN]; +}POSTPACK WMI_CAC_EVENT; + +/* + * WMI_APLIST_EVENTID + */ + +typedef enum { + APLIST_VER1 = 1, +} APLIST_VER; + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT16 channel; +} POSTPACK WMI_AP_INFO_V1; + +typedef PREPACK union { + WMI_AP_INFO_V1 apInfoV1; +} POSTPACK WMI_AP_INFO; + +typedef PREPACK struct { + A_UINT8 apListVer; + A_UINT8 numAP; + WMI_AP_INFO apList[1]; +} POSTPACK WMI_APLIST_EVENT; + +/* + * developer commands + */ + +/* + * WMI_SET_BITRATE_CMDID + * + * Get bit rate cmd uses same definition as set bit rate cmd + */ +typedef enum { + RATE_AUTO = -1, + RATE_1Mb = 0, + RATE_2Mb = 1, + RATE_5_5Mb = 2, + RATE_11Mb = 3, + RATE_6Mb = 4, + RATE_9Mb = 5, + RATE_12Mb = 6, + RATE_18Mb = 7, + RATE_24Mb = 8, + RATE_36Mb = 9, + RATE_48Mb = 10, + RATE_54Mb = 11, +} WMI_BIT_RATE; + +typedef PREPACK struct { + A_INT8 rateIndex; /* see WMI_BIT_RATE */ + A_INT8 mgmtRateIndex; + A_INT8 ctlRateIndex; +} POSTPACK WMI_BIT_RATE_CMD; + + +typedef PREPACK struct { + A_INT8 rateIndex; /* see WMI_BIT_RATE */ +} POSTPACK WMI_BIT_RATE_REPLY; + + +/* + * WMI_SET_FIXRATES_CMDID + * + * Get fix rates cmd uses same definition as set fix rates cmd + */ +typedef enum { + FIX_RATE_1Mb = 0x1, + FIX_RATE_2Mb = 0x2, + FIX_RATE_5_5Mb = 0x4, + FIX_RATE_11Mb = 0x8, + FIX_RATE_6Mb = 0x10, + FIX_RATE_9Mb = 0x20, + FIX_RATE_12Mb = 0x40, + FIX_RATE_18Mb = 0x80, + FIX_RATE_24Mb = 0x100, + FIX_RATE_36Mb = 0x200, + FIX_RATE_48Mb = 0x400, + FIX_RATE_54Mb = 0x800, +} WMI_FIX_RATES_MASK; + +typedef PREPACK struct { + A_UINT16 fixRateMask; /* see WMI_BIT_RATE */ +} POSTPACK WMI_FIX_RATES_CMD, WMI_FIX_RATES_REPLY; + +typedef PREPACK struct { + A_UINT8 bEnableMask; + A_UINT8 frameType; /*type and subtype*/ + A_UINT16 frameRateMask; /* see WMI_BIT_RATE */ +} POSTPACK WMI_FRAME_RATES_CMD, WMI_FRAME_RATES_REPLY; + +/* + * WMI_SET_RECONNECT_AUTH_MODE_CMDID + * + * Set authentication mode + */ +typedef enum { + RECONN_DO_AUTH = 0x00, + RECONN_NOT_AUTH = 0x01 +} WMI_AUTH_MODE; + +typedef PREPACK struct { + A_UINT8 mode; +} POSTPACK WMI_SET_AUTH_MODE_CMD; + +/* + * WMI_SET_REASSOC_MODE_CMDID + * + * Set authentication mode + */ +typedef enum { + REASSOC_DO_DISASSOC = 0x00, + REASSOC_DONOT_DISASSOC = 0x01 +} WMI_REASSOC_MODE; + +typedef PREPACK struct { + A_UINT8 mode; +}POSTPACK WMI_SET_REASSOC_MODE_CMD; + +typedef enum { + ROAM_DATA_TIME = 1, /* Get The Roam Time Data */ +} ROAM_DATA_TYPE; + +typedef PREPACK struct { + A_UINT32 disassoc_time; + A_UINT32 no_txrx_time; + A_UINT32 assoc_time; + A_UINT32 allow_txrx_time; + A_UINT32 last_data_txrx_time; + A_UINT32 first_data_txrx_time; + A_UINT8 disassoc_bssid[ATH_MAC_LEN]; + A_INT8 disassoc_bss_rssi; + A_UINT8 assoc_bssid[ATH_MAC_LEN]; + A_INT8 assoc_bss_rssi; +} POSTPACK WMI_TARGET_ROAM_TIME; + +typedef PREPACK struct { + PREPACK union { + WMI_TARGET_ROAM_TIME roamTime; + } POSTPACK u; + A_UINT8 roamDataType ; +} POSTPACK WMI_TARGET_ROAM_DATA; + +typedef enum { + WMI_WMM_DISABLED = 0, + WMI_WMM_ENABLED +} WMI_WMM_STATUS; + +typedef PREPACK struct { + A_UINT8 status; +}POSTPACK WMI_SET_WMM_CMD; + +typedef enum { + WMI_TXOP_DISABLED = 0, + WMI_TXOP_ENABLED +} WMI_TXOP_CFG; + +typedef PREPACK struct { + A_UINT8 txopEnable; +}POSTPACK WMI_SET_WMM_TXOP_CMD; + +typedef PREPACK struct { + A_UINT8 keepaliveInterval; +} POSTPACK WMI_SET_KEEPALIVE_CMD; + +typedef PREPACK struct { + A_BOOL configured; + A_UINT8 keepaliveInterval; +} POSTPACK WMI_GET_KEEPALIVE_CMD; + +/* + * Add Application specified IE to a management frame + */ +#define WMI_MAX_IE_LEN 255 + +typedef PREPACK struct { + A_UINT8 mgmtFrmType; /* one of WMI_MGMT_FRAME_TYPE */ + A_UINT8 ieLen; /* Length of the IE that should be added to the MGMT frame */ + A_UINT8 ieInfo[1]; +} POSTPACK WMI_SET_APPIE_CMD; + +/* + * Notify the WSC registration status to the target + */ +#define WSC_REG_ACTIVE 1 +#define WSC_REG_INACTIVE 0 +/* Generic Hal Interface for setting hal paramters. */ +/* Add new Set HAL Param cmdIds here for newer params */ +typedef enum { + WHAL_SETCABTO_CMDID = 1, +}WHAL_CMDID; + +typedef PREPACK struct { + A_UINT8 cabTimeOut; +} POSTPACK WHAL_SETCABTO_PARAM; + +typedef PREPACK struct { + A_UINT8 whalCmdId; + A_UINT8 data[1]; +} POSTPACK WHAL_PARAMCMD; + + +#define WOW_MAX_FILTER_LISTS 1 /*4*/ +#define WOW_MAX_FILTERS_PER_LIST 4 +#define WOW_PATTERN_SIZE 64 +#define WOW_MASK_SIZE 64 + +#define MAC_MAX_FILTERS_PER_LIST 4 + +typedef PREPACK struct { + A_UINT8 wow_valid_filter; + A_UINT8 wow_filter_id; + A_UINT8 wow_filter_size; + A_UINT8 wow_filter_offset; + A_UINT8 wow_filter_mask[WOW_MASK_SIZE]; + A_UINT8 wow_filter_pattern[WOW_PATTERN_SIZE]; +} POSTPACK WOW_FILTER; + + +typedef PREPACK struct { + A_UINT8 wow_valid_list; + A_UINT8 wow_list_id; + A_UINT8 wow_num_filters; + A_UINT8 wow_total_list_size; + WOW_FILTER list[WOW_MAX_FILTERS_PER_LIST]; +} POSTPACK WOW_FILTER_LIST; + +typedef PREPACK struct { + A_UINT8 valid_filter; + A_UINT8 mac_addr[ATH_MAC_LEN]; +} POSTPACK MAC_FILTER; + + +typedef PREPACK struct { + A_UINT8 total_list_size; + MAC_FILTER list[MAC_MAX_FILTERS_PER_LIST]; +} POSTPACK MAC_FILTER_LIST; + +#define MAX_IP_ADDRS 2 +typedef PREPACK struct { + A_UINT32 ips[MAX_IP_ADDRS]; /* IP in Network Byte Order */ +} POSTPACK WMI_SET_IP_CMD; + +typedef PREPACK struct { + A_BOOL awake; + A_BOOL asleep; +} POSTPACK WMI_SET_HOST_SLEEP_MODE_CMD; + +typedef PREPACK struct { + A_BOOL enable_wow; +} POSTPACK WMI_SET_WOW_MODE_CMD; + +typedef PREPACK struct { + A_UINT8 filter_list_id; +} POSTPACK WMI_GET_WOW_LIST_CMD; + +/* + * WMI_GET_WOW_LIST_CMD reply + */ +typedef PREPACK struct { + A_UINT8 num_filters; /* number of patterns in reply */ + A_UINT8 this_filter_num; /* this is filter # x of total num_filters */ + A_UINT8 wow_mode; + A_UINT8 host_mode; + WOW_FILTER wow_filters[1]; +} POSTPACK WMI_GET_WOW_LIST_REPLY; + +typedef PREPACK struct { + A_UINT8 filter_list_id; + A_UINT8 filter_size; + A_UINT8 filter_offset; + A_UINT8 filter[1]; +} POSTPACK WMI_ADD_WOW_PATTERN_CMD; + +typedef PREPACK struct { + A_UINT16 filter_list_id; + A_UINT16 filter_id; +} POSTPACK WMI_DEL_WOW_PATTERN_CMD; + +typedef PREPACK struct { + A_UINT8 macaddr[ATH_MAC_LEN]; +} POSTPACK WMI_SET_MAC_ADDRESS_CMD; + +/* + * WMI_SET_AKMP_PARAMS_CMD + */ + +#define WMI_AKMP_MULTI_PMKID_EN 0x000001 + +typedef PREPACK struct { + A_UINT32 akmpInfo; +} POSTPACK WMI_SET_AKMP_PARAMS_CMD; + +typedef PREPACK struct { + A_UINT8 pmkid[WMI_PMKID_LEN]; +} POSTPACK WMI_PMKID; + +/* + * WMI_SET_PMKID_LIST_CMD + */ +#define WMI_MAX_PMKID_CACHE 8 + +typedef PREPACK struct { + A_UINT32 numPMKID; + WMI_PMKID pmkidList[WMI_MAX_PMKID_CACHE]; +} POSTPACK WMI_SET_PMKID_LIST_CMD; + +/* + * WMI_GET_PMKID_LIST_CMD Reply + * Following the Number of PMKIDs is the list of PMKIDs + */ +typedef PREPACK struct { + A_UINT32 numPMKID; + A_UINT8 bssidList[ATH_MAC_LEN][1]; + WMI_PMKID pmkidList[1]; +} POSTPACK WMI_PMKID_LIST_REPLY; + +typedef PREPACK struct { + A_UINT16 oldChannel; + A_UINT32 newChannel; +} POSTPACK WMI_CHANNEL_CHANGE_EVENT; + +typedef PREPACK struct { + A_UINT32 version; +} POSTPACK WMI_WLAN_VERSION_EVENT; + +#define PEER_NODE_JOIN_EVENT 0x00 +#define PEER_NODE_LEAVE_EVENT 0x01 +#define PEER_FIRST_NODE_JOIN_EVENT 0x10 +#define PEER_LAST_NODE_LEAVE_EVENT 0x11 +typedef PREPACK struct { + A_UINT8 eventCode; + A_UINT8 peerMacAddr[ATH_MAC_LEN]; +} POSTPACK WMI_PEER_NODE_EVENT; + +#define IEEE80211_FRAME_TYPE_MGT 0x00 +#define IEEE80211_FRAME_TYPE_CTL 0x04 + + +typedef enum { + WMI_PYXIS_GEN_PARAMS = 0, + WMI_PYXIS_DSCVR_PARAMS, + WMI_PYXIS_SET_TX_MODE, +} WMI_PYXIS_CONFIG_TYPE; + +typedef PREPACK struct { + A_UINT16 pyxisConfigType; // One of WMI_PYXIS_CONFIG_TYPE + A_UINT16 pyxisConfigLen; // Length in Bytes of Information that follows +} POSTPACK WMI_PYXIS_CONFIG_HDR; + +typedef PREPACK struct { + WMI_PYXIS_CONFIG_HDR hdr; + A_UINT32 dscvrWindow; + A_UINT32 dscvrInterval; + A_UINT32 dscvrLife; + A_UINT32 probeInterval; + A_UINT32 probePeriod; + A_UINT16 dscvrChannel; +} POSTPACK WMI_PYXIS_DSCVR_CONFIG; + +typedef PREPACK struct { + WMI_PYXIS_CONFIG_HDR hdr; + A_UINT32 dataWindowSizeMin; + A_UINT32 dataWindowSizeMax; + A_UINT8 maxJoiners; +} POSTPACK WMI_PYXIS_GEN_CONFIG; + +typedef PREPACK struct { + WMI_PYXIS_CONFIG_HDR hdr; + A_BOOL mode; +} POSTPACK WMI_PYXIS_TX_MODE; + +typedef enum { + WMI_PYXIS_DISC_PEER = 0, + WMI_PYXIS_JOIN_PEER, +} WMI_PYXIS_CMD_TYPE; + +typedef PREPACK struct { + A_UINT16 pyxisCmd; + A_UINT16 pyxisCmdLen; // Length following this header +} POSTPACK WMI_PYXIS_CMD_HDR; + +typedef PREPACK struct { + WMI_PYXIS_CMD_HDR hdr; + A_UINT8 peerMacAddr[ATH_MAC_LEN]; +} POSTPACK WMI_PYXIS_DISCONNECT_CMD; + +typedef PREPACK struct { + WMI_PYXIS_CMD_HDR hdr; + A_UINT32 ctrl_flags; /* One of the Bits determines if it + * is Virt Adhoc/the device is to + * join a BSS */ + A_UINT16 channel; /* Data Channel */ + A_UINT8 networkType; /* network type */ + A_UINT8 dot11AuthMode; /* OPEN_AUTH */ + A_UINT8 authMode; /* NONE_AUTH */ + A_UINT8 pairwiseCryptoType; /* One of NONE_CRYPT, AES_CRYPT */ + A_UINT8 pairwiseCryptoLen; /* 0 since ADD_KEY passes the length */ + A_UINT8 groupCryptoType; /* One of NONE_CRYPT, AES_CRYPT */ + A_UINT8 groupCryptoLen; /* 0 since ADD_KEY passes the length */ + A_UINT8 peerMacAddr[ATH_MAC_LEN]; /* BSSID of peer network*/ + A_UINT8 nwBSSID[ATH_MAC_LEN]; /* BSSID of the Pyxis Adhoc Network */ +} POSTPACK WMI_PYXIS_JOIN_CMD; + +typedef PREPACK struct { + WMI_PYXIS_CMD_HDR hdr; + A_BOOL mode; +} POSTPACK WMI_PYXIS_SET_TX_MODE_CMD; + +/* + * ------- AP Mode definitions -------------- + */ + +#define AP_MAX_NUM_STA 8 +#define AP_ACL_SIZE 10 +#define IEEE80211_MAX_IE 256 +#define MCAST_AID 0xFF /* Spl. AID used to set DTIM flag in the beacons */ + +/* AP mode disconnect reasons */ +#define AP_DISCONNECT_STA_LEFT 101 +#define AP_DISCONNECT_FROM_HOST 102 +#define AP_DISCONNECT_COMM_TIMEOUT 103 + +/* + * Used with WMI_AP_HIDDEN_SSID_CMDID + */ +#define HIDDEN_SSID_FALSE 0 +#define HIDDEN_SSID_TRUE 1 +typedef PREPACK struct { + A_UINT8 hidden_ssid; +} POSTPACK WMI_AP_HIDDEN_SSID_CMD; + +/* + * Used with WMI_AP_ACL_POLICY_CMDID + */ +#define AP_ACL_DISABLE 0x00 +#define AP_ACL_ALLOW_MAC 0x01 +#define AP_ACL_DENY_MAC 0x02 +#define AP_ACL_RETAIN_LIST_MASK 0x80 +typedef PREPACK struct { + A_UINT8 policy; +} POSTPACK WMI_AP_ACL_POLICY_CMD; + +/* + * Used with WMI_AP_ACL_MAC_LIST_CMDID + */ +#define ADD_MAC_ADDR 1 +#define DEL_MAC_ADDR 2 +typedef PREPACK struct { + A_UINT8 action; + A_UINT8 index; + A_UINT8 mac[ATH_MAC_LEN]; + A_UINT8 wildcard; +} POSTPACK WMI_AP_ACL_MAC_CMD; + +typedef PREPACK struct { + A_UINT16 index; + A_UINT8 acl_mac[AP_ACL_SIZE][ATH_MAC_LEN]; + A_UINT8 wildcard[AP_ACL_SIZE]; + A_UINT8 policy; +} POSTPACK WMI_AP_ACL; + +/* + * Used with WMI_AP_SET_NUM_STA_CMDID + */ +typedef PREPACK struct { + A_UINT8 num_sta; +} POSTPACK WMI_AP_SET_NUM_STA_CMD; + +/* + * Used with WMI_AP_SET_MLME_CMDID + */ +typedef PREPACK struct { + A_UINT8 mac[ATH_MAC_LEN]; + A_UINT16 reason; /* 802.11 reason code */ + A_UINT8 cmd; /* operation to perform */ +#define WMI_AP_MLME_ASSOC 1 /* associate station */ +#define WMI_AP_DISASSOC 2 /* disassociate station */ +#define WMI_AP_DEAUTH 3 /* deauthenticate station */ +#define WMI_AP_MLME_AUTHORIZE 4 /* authorize station */ +#define WMI_AP_MLME_UNAUTHORIZE 5 /* unauthorize station */ +} POSTPACK WMI_AP_SET_MLME_CMD; + +typedef PREPACK struct { + A_UINT32 period; +} POSTPACK WMI_AP_CONN_INACT_CMD; + +typedef PREPACK struct { + A_UINT32 period_min; + A_UINT32 dwell_ms; +} POSTPACK WMI_AP_PROT_SCAN_TIME_CMD; + +typedef PREPACK struct { + A_BOOL flag; + A_UINT16 aid; +} POSTPACK WMI_AP_SET_PVB_CMD; + +#define WMI_DISABLE_REGULATORY_CODE "FF" + +typedef PREPACK struct { + A_UCHAR countryCode[3]; +} POSTPACK WMI_AP_SET_COUNTRY_CMD; + +typedef PREPACK struct { + A_UINT8 dtim; +} POSTPACK WMI_AP_SET_DTIM_CMD; + +/* AP mode events */ +/* WMI_PS_POLL_EVENT */ +typedef PREPACK struct { + A_UINT16 aid; +} POSTPACK WMI_PSPOLL_EVENT; + +/* + * End of AP mode definitions + */ + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/wmi_api.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wmi_api.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/wmi_api.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wmi_api.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,368 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions for the Wireless Module Interface (WMI). +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _WMI_API_H_ +#define _WMI_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * IP QoS Field definitions according to 802.1p + */ +#define BEST_EFFORT_PRI 0 +#define BACKGROUND_PRI 1 +#define EXCELLENT_EFFORT_PRI 3 +#define CONTROLLED_LOAD_PRI 4 +#define VIDEO_PRI 5 +#define VOICE_PRI 6 +#define NETWORK_CONTROL_PRI 7 +#define MAX_NUM_PRI 8 + +#define UNDEFINED_PRI (0xff) + +#define WMI_IMPLICIT_PSTREAM_INACTIVITY_INT 5000 /* 5 seconds */ + +#define A_ROUND_UP(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) + +typedef enum { + ATHEROS_COMPLIANCE = 0x1, +}TSPEC_PARAM_COMPLIANCE; + +struct wmi_t; + +void *wmi_init(void *devt); + +void wmi_qos_state_init(struct wmi_t *wmip); +void wmi_shutdown(struct wmi_t *wmip); +HTC_ENDPOINT_ID wmi_get_control_ep(struct wmi_t * wmip); +void wmi_set_control_ep(struct wmi_t * wmip, HTC_ENDPOINT_ID eid); +A_UINT16 wmi_get_mapped_qos_queue(struct wmi_t *, A_UINT8); +A_STATUS wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf); +A_STATUS wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType, A_BOOL bMoreData); +A_STATUS wmi_dot3_2_dix(struct wmi_t *wmip, void *osbuf); + +A_STATUS wmi_dot11_hdr_remove (struct wmi_t *wmip, void *osbuf); +A_STATUS wmi_dot11_hdr_add(struct wmi_t *wmip, void *osbuf, NETWORK_TYPE mode); + +A_STATUS wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf); +A_STATUS wmi_syncpoint(struct wmi_t *wmip); +A_STATUS wmi_syncpoint_reset(struct wmi_t *wmip); +A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT32 layer2Priority, A_BOOL wmmEnabled); + +A_UINT8 wmi_determine_userPriority (A_UINT8 *pkt, A_UINT32 layer2Pri); + +A_STATUS wmi_control_rx(struct wmi_t *wmip, void *osbuf); +void wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg); +void wmi_free_allnodes(struct wmi_t *wmip); +bss_t *wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr); +void wmi_free_node(struct wmi_t *wmip, const A_UINT8 *macaddr); + + +typedef enum { + NO_SYNC_WMIFLAG = 0, + SYNC_BEFORE_WMIFLAG, /* transmit all queued data before cmd */ + SYNC_AFTER_WMIFLAG, /* any new data waits until cmd execs */ + SYNC_BOTH_WMIFLAG, + END_WMIFLAG /* end marker */ +} WMI_SYNC_FLAG; + +A_STATUS wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId, + WMI_SYNC_FLAG flag); + +A_STATUS wmi_connect_cmd(struct wmi_t *wmip, + NETWORK_TYPE netType, + DOT11_AUTH_MODE dot11AuthMode, + AUTH_MODE authMode, + CRYPTO_TYPE pairwiseCrypto, + A_UINT8 pairwiseCryptoLen, + CRYPTO_TYPE groupCrypto, + A_UINT8 groupCryptoLen, + int ssidLength, + A_UCHAR *ssid, + A_UINT8 *bssid, + A_UINT16 channel, + A_UINT32 ctrl_flags); + +A_STATUS wmi_reconnect_cmd(struct wmi_t *wmip, + A_UINT8 *bssid, + A_UINT16 channel); +A_STATUS wmi_disconnect_cmd(struct wmi_t *wmip); +A_STATUS wmi_getrev_cmd(struct wmi_t *wmip); +A_STATUS wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType, + A_BOOL forceFgScan, A_BOOL isLegacy, + A_UINT32 homeDwellTime, A_UINT32 forceScanInterval, + A_INT8 numChan, A_UINT16 *channelList); +A_STATUS wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec, + A_UINT16 fg_end_sec, A_UINT16 bg_sec, + A_UINT16 minact_chdw_msec, + A_UINT16 maxact_chdw_msec, A_UINT16 pas_chdw_msec, + A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags, + A_UINT32 max_dfsch_act_time, + A_UINT16 maxact_scan_per_ssid); +A_STATUS wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask); +A_STATUS wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag, + A_UINT8 ssidLength, A_UCHAR *ssid); +A_STATUS wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons); +A_STATUS wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmisstime, A_UINT16 bmissbeacons); +A_STATUS wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType, + A_UINT8 ieLen, A_UINT8 *ieInfo); +A_STATUS wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode); +A_STATUS wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl, + A_UINT16 atim_windows, A_UINT16 timeout_value); +A_STATUS wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod, + A_UINT16 psPollNum, A_UINT16 dtimPolicy); +A_STATUS wmi_force_target_assert(struct wmi_t *wmip); +A_STATUS wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout); +A_STATUS wmi_sync_cmd(struct wmi_t *wmip, A_UINT8 syncNumber); +A_STATUS wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *pstream); +A_STATUS wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 streamID); +A_STATUS wmi_set_framerate_cmd(struct wmi_t *wmip, A_UINT8 bEnable, A_UINT8 type, A_UINT8 subType, A_UINT16 rateMask); +A_STATUS wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 dataRate, A_INT32 mgmtRate, A_INT32 ctlRate); +A_STATUS wmi_get_bitrate_cmd(struct wmi_t *wmip); +A_INT8 wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate); +A_STATUS wmi_get_regDomain_cmd(struct wmi_t *wmip); +A_STATUS wmi_get_channelList_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam, + WMI_PHY_MODE mode, A_INT8 numChan, + A_UINT16 *channelList); + +A_STATUS wmi_set_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd); +A_STATUS wmi_set_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd); +A_STATUS wmi_clr_rssi_snr(struct wmi_t *wmip); +A_STATUS wmi_set_lq_threshold_params(struct wmi_t *wmip, + WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd); +A_STATUS wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold); +A_STATUS wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status); + +A_STATUS wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 bitmask); + +A_STATUS wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie, + A_UINT32 source); + +A_STATUS wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask, + A_UINT16 tsr, A_BOOL rep, A_UINT16 size, + A_UINT32 valid); + +A_STATUS wmi_get_stats_cmd (struct wmi_t *wmip); + +A_STATUS wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex, + CRYPTO_TYPE keyType, A_UINT8 keyUsage, + A_UINT8 keyLength,A_UINT8 *keyRSC, + A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl, A_UINT8 *mac, + WMI_SYNC_FLAG sync_flag); +A_STATUS wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk); +A_STATUS wmi_delete_krk_cmd(struct wmi_t *wmip); +A_STATUS wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex); +A_STATUS wmi_set_akmp_params_cmd(struct wmi_t *wmip, + WMI_SET_AKMP_PARAMS_CMD *akmpParams); +A_STATUS wmi_get_pmkid_list_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_pmkid_list_cmd(struct wmi_t *wmip, + WMI_SET_PMKID_LIST_CMD *pmkInfo); +A_STATUS wmi_abort_scan_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM); +A_STATUS wmi_get_txPwr_cmd(struct wmi_t *wmip); +A_STATUS wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid); +A_STATUS wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex); +A_STATUS wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en); +A_STATUS wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId, + A_BOOL set); +A_STATUS wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT16 txop, + A_UINT8 eCWmin, A_UINT8 eCWmax, + A_UINT8 aifsn); +A_STATUS wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType, + A_UINT8 trafficClass, A_UINT8 maxRetries, + A_UINT8 enableNotify); + +void wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid); + +A_STATUS wmi_get_roam_tbl_cmd(struct wmi_t *wmip); +A_STATUS wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType); +A_STATUS wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p, + A_UINT8 size); +A_STATUS wmi_set_powersave_timers_cmd(struct wmi_t *wmip, + WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd, + A_UINT8 size); + +A_STATUS wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode); +A_STATUS wmi_opt_tx_frame_cmd(struct wmi_t *wmip, + A_UINT8 frmType, + A_UINT8 *dstMacAddr, + A_UINT8 *bssid, + A_UINT16 optIEDataLen, + A_UINT8 *optIEData); + +A_STATUS wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl); +A_STATUS wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize); +A_STATUS wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSpLen); +A_UINT8 convert_userPriority_to_trafficClass(A_UINT8 userPriority); +A_UINT8 wmi_get_power_mode_cmd(struct wmi_t *wmip); +A_STATUS wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance); + +#ifdef CONFIG_HOST_TCMD_SUPPORT +A_STATUS wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32 len); +#endif + +A_STATUS wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status); +A_STATUS wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd); + + +/* + * This function is used to configure the fix rates mask to the target. + */ +A_STATUS wmi_set_fixrates_cmd(struct wmi_t *wmip, A_INT16 fixRatesMask); +A_STATUS wmi_get_ratemask_cmd(struct wmi_t *wmip); + +A_STATUS wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode); + +A_STATUS wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode); + +A_STATUS wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status); +A_STATUS wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG txEnable); +A_STATUS wmi_set_country(struct wmi_t *wmip, A_UCHAR *countryCode); + +A_STATUS wmi_get_keepalive_configured(struct wmi_t *wmip); +A_UINT8 wmi_get_keepalive_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval); + +A_STATUS wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType, + A_UINT8 ieLen,A_UINT8 *ieInfo); + +A_STATUS wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen); + +A_INT32 wmi_get_rate(A_INT8 rateindex); + +A_STATUS wmi_set_ip_cmd(struct wmi_t *wmip, WMI_SET_IP_CMD *cmd); + +/*Wake on Wireless WMI commands*/ +A_STATUS wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip, WMI_SET_HOST_SLEEP_MODE_CMD *cmd); +A_STATUS wmi_set_wow_mode_cmd(struct wmi_t *wmip, WMI_SET_WOW_MODE_CMD *cmd); +A_STATUS wmi_get_wow_list_cmd(struct wmi_t *wmip, WMI_GET_WOW_LIST_CMD *cmd); +A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip, + WMI_ADD_WOW_PATTERN_CMD *cmd, A_UINT8* pattern, A_UINT8* mask, A_UINT8 pattern_size); +A_STATUS wmi_del_wow_pattern_cmd(struct wmi_t *wmip, + WMI_DEL_WOW_PATTERN_CMD *cmd); +A_STATUS wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status); + +A_STATUS +wmi_set_params_cmd(struct wmi_t *wmip, A_UINT32 opcode, A_UINT32 length, A_CHAR* buffer); + +A_STATUS +wmi_set_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4); + +A_STATUS +wmi_del_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4); + +bss_t * +wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID); + + +void +wmi_node_return (struct wmi_t *wmip, bss_t *bss); + +void +wmi_set_nodeage(struct wmi_t *wmip, A_UINT32 nodeAge); + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +A_STATUS wmi_prof_cfg_cmd(struct wmi_t *wmip, A_UINT32 period, A_UINT32 nbins); +A_STATUS wmi_prof_addr_set_cmd(struct wmi_t *wmip, A_UINT32 addr); +A_STATUS wmi_prof_start_cmd(struct wmi_t *wmip); +A_STATUS wmi_prof_stop_cmd(struct wmi_t *wmip); +A_STATUS wmi_prof_count_get_cmd(struct wmi_t *wmip); +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ +#ifdef OS_ROAM_MANAGEMENT +void wmi_scan_indication (struct wmi_t *wmip); +#endif + +A_STATUS +wmi_set_target_event_report_cmd(struct wmi_t *wmip, WMI_SET_TARGET_EVENT_REPORT_CMD* cmd); + +#ifdef PYXIS_ADHOC +A_STATUS +wmi_set_pyxis_gen_config (struct wmi_t *wmip, A_UINT32 dataWindowSizeMin, A_UINT32 dataWindowSizeMax, A_UINT8 maxJoiners); + +A_STATUS +wmi_set_pyxis_dscvr_config (struct wmi_t *wmip, A_UINT32 dscvrWindow, A_UINT32 dscvrInterval, + A_UINT32 probeInterval, A_UINT32 probePeriod, A_UINT16 dscvrChannel); +A_STATUS +wmi_pyxis_disconnect_cmd (struct wmi_t *wmip, A_UINT8 *bssid); + +A_STATUS +wmi_pyxis_join_cmd (struct wmi_t *wmip, NETWORK_TYPE wmiNetworkType, + DOT11_AUTH_MODE dot11AuthMode, AUTH_MODE authMode, + CRYPTO_TYPE pairwiseCrypto, A_UINT8 pairwiseCryptoLen, + CRYPTO_TYPE groupCrypto, A_UINT8 groupCryptoLen, + A_UINT8 *bssid, A_UINT8 *nwBSSID, A_UINT16 channel, A_UINT32 ctrl_flags + ); +#endif + +bss_t *wmi_rm_current_bss (struct wmi_t *wmip, A_UINT8 *id); +A_STATUS wmi_add_current_bss (struct wmi_t *wmip, A_UINT8 *id, bss_t *bss); + + +/* + * AP mode + */ +A_STATUS +wmi_ap_profile_commit(struct wmi_t *wmip, WMI_CONNECT_CMD *p); + +A_STATUS +wmi_ap_set_hidden_ssid(struct wmi_t *wmip, A_UINT8 hidden_ssid); + +A_STATUS +wmi_ap_set_num_sta(struct wmi_t *wmip, A_UINT8 num_sta); + +A_STATUS +wmi_ap_set_acl_policy(struct wmi_t *wmip, A_UINT8 policy); + +A_STATUS +wmi_ap_acl_mac_list(struct wmi_t *wmip, WMI_AP_ACL_MAC_CMD *a); + +A_UINT8 +acl_add_del_mac(WMI_AP_ACL *a, WMI_AP_ACL_MAC_CMD *acl); + +A_STATUS +wmi_ap_set_mlme(struct wmi_t *wmip, A_UINT8 cmd, A_UINT8 *mac, A_UINT16 reason); + +A_STATUS +wmi_set_pvb_cmd(struct wmi_t *wmip, A_UINT16 aid, A_BOOL flag); + +A_STATUS +wmi_ap_conn_inact_time(struct wmi_t *wmip, A_UINT32 period); + +A_STATUS +wmi_ap_bgscan_time(struct wmi_t *wmip, A_UINT32 period, A_UINT32 dwell); + +A_STATUS +wmi_ap_set_dtim(struct wmi_t *wmip, A_UINT8 dtim); + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_API_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/wmi_filter_linux.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wmi_filter_linux.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/wmi_filter_linux.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wmi_filter_linux.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// + */ + +#ifndef _WMI_FILTER_LINUX_H_ +#define _WMI_FILTER_LINUX_H_ + +/* + * sioctl_filter - Standard ioctl + * pioctl_filter - Priv ioctl + * xioctl_filter - eXtended ioctl + * + * ---- Possible values for the WMI filter --------------- + * (0) - Block this cmd always (or) not implemented + * (INFRA_NETWORK) - Allow this cmd only in STA mode + * (ADHOC_NETWORK) - Allow this cmd only in IBSS mode + * (AP_NETWORK) - Allow this cmd only in AP mode + * (INFRA_NETWORK | ADHOC_NETWORK) - Block this cmd in AP mode + * (ADHOC_NETWORK | AP_NETWORK) - Block this cmd in STA mode + * (INFRA_NETWORK | AP_NETWORK) - Block this cmd in IBSS mode + * (INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK)- allow only when mode is set + * (0xFF) - Allow this cmd always irrespective of mode + */ + +A_UINT8 sioctl_filter[] = { +(AP_NETWORK), /* SIOCSIWCOMMIT 0x8B00 */ +(0xFF), /* SIOCGIWNAME 0x8B01 */ +(0), /* SIOCSIWNWID 0x8B02 */ +(0), /* SIOCGIWNWID 0x8B03 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWFREQ 0x8B04 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWFREQ 0x8B05 */ +(0xFF), /* SIOCSIWMODE 0x8B06 */ +(0xFF), /* SIOCGIWMODE 0x8B07 */ +(0), /* SIOCSIWSENS 0x8B08 */ +(0), /* SIOCGIWSENS 0x8B09 */ +(0), /* SIOCSIWRANGE 0x8B0A */ +(0xFF), /* SIOCGIWRANGE 0x8B0B */ +(0), /* SIOCSIWPRIV 0x8B0C */ +(0), /* SIOCGIWPRIV 0x8B0D */ +(0), /* SIOCSIWSTATS 0x8B0E */ +(0), /* SIOCGIWSTATS 0x8B0F */ +(0), /* SIOCSIWSPY 0x8B10 */ +(0), /* SIOCGIWSPY 0x8B11 */ +(0), /* SIOCSIWTHRSPY 0x8B12 */ +(0), /* SIOCGIWTHRSPY 0x8B13 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWAP 0x8B14 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWAP 0x8B15 */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,13) +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCSIWMLME 0X8B16 */ +#else +(0), /* Dummy 0 */ +#endif /* LINUX_VERSION_CODE */ +(0), /* SIOCGIWAPLIST 0x8B17 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCSIWSCAN 0x8B18 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCGIWSCAN 0x8B19 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWESSID 0x8B1A */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWESSID 0x8B1B */ +(0), /* SIOCSIWNICKN 0x8B1C */ +(0), /* SIOCGIWNICKN 0x8B1D */ +(0), /* Dummy 0 */ +(0), /* Dummy 0 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWRATE 0x8B20 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWRATE 0x8B21 */ +(0), /* SIOCSIWRTS 0x8B22 */ +(0), /* SIOCGIWRTS 0x8B23 */ +(0), /* SIOCSIWFRAG 0x8B24 */ +(0), /* SIOCGIWFRAG 0x8B25 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWTXPOW 0x8B26 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWTXPOW 0x8B27 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCSIWRETRY 0x8B28 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCGIWRETRY 0x8B29 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWENCODE 0x8B2A */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWENCODE 0x8B2B */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCSIWPOWER 0x8B2C */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCGIWPOWER 0x8B2D */ +}; + + + +A_UINT8 pioctl_filter[] = { +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_SETPARAM (SIOCIWFIRSTPRIV+0) */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_SETKEY (SIOCIWFIRSTPRIV+1) */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_DELKEY (SIOCIWFIRSTPRIV+2) */ +(AP_NETWORK), /* IEEE80211_IOCTL_SETMLME (SIOCIWFIRSTPRIV+3) */ +(INFRA_NETWORK), /* IEEE80211_IOCTL_ADDPMKID (SIOCIWFIRSTPRIV+4) */ +(0), /* IEEE80211_IOCTL_SETOPTIE (SIOCIWFIRSTPRIV+5) */ +(0), /* (SIOCIWFIRSTPRIV+6) */ +(0), /* (SIOCIWFIRSTPRIV+7) */ +(0), /* (SIOCIWFIRSTPRIV+8) */ +(0), /* (SIOCIWFIRSTPRIV+9) */ +(0), /* IEEE80211_IOCTL_LASTONE (SIOCIWFIRSTPRIV+10) */ +(0xFF), /* AR6000_IOCTL_WMI_GETREV (SIOCIWFIRSTPRIV+11) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SETPWR (SIOCIWFIRSTPRIV+12) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SETSCAN (SIOCIWFIRSTPRIV+13) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SETLISTENINT (SIOCIWFIRSTPRIV+14) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SETBSSFILTER (SIOCIWFIRSTPRIV+15) */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_IOCTL_WMI_SET_CHANNELPARAMS (SIOCIWFIRSTPRIV+16) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_PROBEDSSID (SIOCIWFIRSTPRIV+17) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_PMPARAMS (SIOCIWFIRSTPRIV+18) */ +(INFRA_NETWORK), /* AR6000_IOCTL_WMI_SET_BADAP (SIOCIWFIRSTPRIV+19) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_GET_QOS_QUEUE (SIOCIWFIRSTPRIV+20) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_CREATE_QOS (SIOCIWFIRSTPRIV+21) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_DELETE_QOS (SIOCIWFIRSTPRIV+22) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_SNRTHRESHOLD (SIOCIWFIRSTPRIV+23) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24)*/ +(0xFF), /* AR6000_IOCTL_WMI_GET_TARGET_STATS (SIOCIWFIRSTPRIV+25) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_ASSOC_INFO (SIOCIWFIRSTPRIV+26) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_ACCESS_PARAMS (SIOCIWFIRSTPRIV+27) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_BMISS_TIME (SIOCIWFIRSTPRIV+28) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_DISC_TIMEOUT (SIOCIWFIRSTPRIV+29) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_FORCE_ASSERT (SIOCIWFIRSTPRIV+30) */ +}; + + + +A_UINT8 xioctl_filter[] = { +(0xFF), /* Dummy 0 */ +(0xFF), /* AR6000_XIOCTL_BMI_DONE 1 */ +(0xFF), /* AR6000_XIOCTL_BMI_READ_MEMORY 2 */ +(0xFF), /* AR6000_XIOCTL_BMI_WRITE_MEMORY 3 */ +(0xFF), /* AR6000_XIOCTL_BMI_EXECUTE 4 */ +(0xFF), /* AR6000_XIOCTL_BMI_SET_APP_START 5 */ +(0xFF), /* AR6000_XIOCTL_BMI_READ_SOC_REGISTER 6 */ +(0xFF), /* AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER 7 */ +(0xFF), /* AR6000_XIOCTL_BMI_TEST 8 */ +(0xFF), /* AR6000_XIOCTL_UNUSED9 9 */ +(0xFF), /* AR6000_XIOCTL_UNUSED10 10 */ +(0xFF), /* AR6000_XIOCTL_UNUSED11 11 */ +(0xFF), /* AR6000_XIOCTL_FORCE_TARGET_RESET 12 */ +(0xFF), /* AR6000_XIOCTL_HTC_RAW_OPEN 13 */ +(0xFF), /* AR6000_XIOCTL_HTC_RAW_CLOSE 14 */ +(0xFF), /* AR6000_XIOCTL_HTC_RAW_READ 15 */ +(0xFF), /* AR6000_XIOCTL_HTC_RAW_WRITE 16 */ +(0xFF), /* AR6000_XIOCTL_CHECK_TARGET_READY 17 */ +(0xFF), /* AR6000_XIOCTL_GPIO_OUTPUT_SET 18 */ +(0xFF), /* AR6000_XIOCTL_GPIO_INPUT_GET 19 */ +(0xFF), /* AR6000_XIOCTL_GPIO_REGISTER_SET 20 */ +(0xFF), /* AR6000_XIOCTL_GPIO_REGISTER_GET 21 */ +(0xFF), /* AR6000_XIOCTL_GPIO_INTR_ACK 22 */ +(0xFF), /* AR6000_XIOCTL_GPIO_INTR_WAIT 23 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_ADHOC_BSSID 24 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_OPT_MODE 25 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_OPT_SEND_FRAME 26 */ +(ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_SET_BEACON_INTVAL 27 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_SETAUTHALG 28 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_VOICE_PKT_SIZE 29 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_MAX_SP 30 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_ROAM_TBL 31 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_ROAM_CTRL 32 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS 33 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTRL_WMI_GET_POWER_MODE 34 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTRL_WMI_SET_WLAN_STATE 35 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_ROAM_DATA 36 */ +(0xFF), /* AR6000_XIOCTL_WMI_SETRETRYLIMITS 37 */ +(0xFF), /* AR6000_XIOCTL_TCMD_CONT_TX 38 */ +(0xFF), /* AR6000_XIOCTL_TCMD_CONT_RX 39 */ +(0xFF), /* AR6000_XIOCTL_TCMD_PM 40 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_STARTSCAN 41 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SETFIXRATES 42 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_GETFIXRATES 43 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD 44 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_CLR_RSSISNR 45 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_LQTHRESHOLD 46 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_RTS 47 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_LPREAMBLE 48 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_AUTHMODE 49 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_REASSOCMODE 50 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_WMM 51 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS 52 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP 53 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_GET_RD 54 */ +(0xFF), /* AR6000_XIOCTL_DIAG_READ 55 */ +(0xFF), /* AR6000_XIOCTL_DIAG_WRITE 56 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_TXOP 57 */ +(INFRA_NETWORK), /* AR6000_XIOCTL_USER_SETKEYS 58 */ +(INFRA_NETWORK), /* AR6000_XIOCTL_WMI_SET_KEEPALIVE 59 */ +(INFRA_NETWORK), /* AR6000_XIOCTL_WMI_GET_KEEPALIVE 60 */ +(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_INSTALL 61 */ +(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL 62 */ +(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE 63 */ +(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE 64 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_APPIE 65 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER 66 */ +(0xFF), /* AR6000_XIOCTL_DBGLOG_CFG_MODULE 67 */ +(0xFF), /* AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS 68 */ +(0xFF), /* Dummy 69 */ +(INFRA_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_WSC_STATUS 70 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BT_STATUS 71 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BT_PARAMS 72 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE 73 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_WOW_MODE 74 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_WOW_LIST 75 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_ADD_WOW_PATTERN 76 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_DEL_WOW_PATTERN 77 */ +(0xFF), /* AR6000_XIOCTL_TARGET_INFO 78 */ +(0xFF), /* AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE 79 */ +(0xFF), /* AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE 80 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS 81 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_AKMP_PARAMS 82 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_PMKID_LIST 83 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_PMKID_LIST 84 */ +(0xFF), /* Dummy 85 */ +(0xFF), /* Dummy 86 */ +(0xFF), /* Dummy 87 */ +(0xFF), /* Dummy 88 */ +(0xFF), /* Dummy 89 */ +(0xFF), /* AR6000_XIOCTL_UNUSED90 90 */ +(0xFF), /* AR6000_XIOCTL_BMI_LZ_STREAM_START 91 */ +(0xFF), /* AR6000_XIOCTL_BMI_LZ_DATA 92 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_CFG 93 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_ADDR_SET 94 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_START 95 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_STOP 96 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_COUNT_GET 97 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_ABORT_SCAN 98 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_STA_LIST 99 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_HIDDEN_SSID 100 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_NUM_STA 101 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_ACL_MAC 102 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_ACL_LIST 103 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_COMMIT_CONFIG 104 */ +(AP_NETWORK), /* IEEE80211_IOCTL_GETWPAIE 105 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_CONN_INACT_TIME 106 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_PROT_SCAN_TIME 107 */ +(AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_COUNTRY 108 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_DTIM 109 */ +(0xFF), /* AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT 110 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_IP 111 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_ACL_POLICY 112 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_INTRA_BSS_COMM 113 */ +}; + +#endif /*_WMI_FILTER_LINUX_H_*/ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/wmi_host.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wmi_host.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/wmi_host.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wmi_host.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,82 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains local definitios for the wmi host module. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _WMI_HOST_H_ +#define _WMI_HOST_H_ + +#include "roaming.h" +#ifdef __cplusplus +extern "C" { +#endif + +struct wmi_stats { + A_UINT32 cmd_len_err; + A_UINT32 cmd_id_err; +}; + +#define SSID_IE_LEN_INDEX 13 + +/* Host side link management data structures */ +#define SIGNAL_QUALITY_THRESHOLD_LEVELS 6 +#define SIGNAL_QUALITY_UPPER_THRESHOLD_LEVELS SIGNAL_QUALITY_THRESHOLD_LEVELS +#define SIGNAL_QUALITY_LOWER_THRESHOLD_LEVELS SIGNAL_QUALITY_THRESHOLD_LEVELS +typedef struct sq_threshold_params_s { + A_INT16 upper_threshold[SIGNAL_QUALITY_UPPER_THRESHOLD_LEVELS]; + A_INT16 lower_threshold[SIGNAL_QUALITY_LOWER_THRESHOLD_LEVELS]; + A_UINT32 upper_threshold_valid_count; + A_UINT32 lower_threshold_valid_count; + A_UINT32 polling_interval; + A_UINT8 weight; + A_UINT8 last_rssi; //normally you would expect this to be bss specific but we keep only one instance because its only valid when the device is in a connected state. Not sure if it belongs to host or target. + A_UINT8 last_rssi_poll_event; //Not sure if it belongs to host or target +} SQ_THRESHOLD_PARAMS; +struct wmi_t { + A_BOOL wmi_ready; + A_BOOL wmi_numQoSStream; + A_UINT16 wmi_streamExistsForAC[WMM_NUM_AC]; + A_UINT8 wmi_fatPipeExists; + void *wmi_devt; + struct wmi_stats wmi_stats; + struct ieee80211_node_table wmi_scan_table; + A_UINT8 wmi_bssid[ATH_MAC_LEN]; + A_UINT8 wmi_powerMode; + A_UINT8 wmi_phyMode; + A_UINT8 wmi_keepaliveInterval; + A_MUTEX_T wmi_lock; + HTC_ENDPOINT_ID wmi_endpoint_id; + SQ_THRESHOLD_PARAMS wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_NUM_MAX]; + CRYPTO_TYPE wmi_pair_crypto_type; + CRYPTO_TYPE wmi_grp_crypto_type; + A_BOOL wmi_is_wmm_enabled; +}; + + +#define LOCK_WMI(w) A_MUTEX_LOCK(&(w)->wmi_lock); +#define UNLOCK_WMI(w) A_MUTEX_UNLOCK(&(w)->wmi_lock); + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_HOST_H_ */ diff -urN linux-2.6.26/drivers/net/wireless/ath6k22.133/wmix.h linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wmix.h --- linux-2.6.26/drivers/net/wireless/ath6k22.133/wmix.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/net/wireless/ath6k22.133/wmix.h 2010-08-10 04:16:44.000000000 -0400 @@ -0,0 +1,279 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// +// Wifi driver for AR6002 +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +/* + * This file contains extensions of the WMI protocol specified in the + * Wireless Module Interface (WMI). It includes definitions of all + * extended commands and events. Extensions include useful commands + * that are not directly related to wireless activities. They may + * be hardware-specific, and they might not be supported on all + * implementations. + * + * Extended WMIX commands are encapsulated in a WMI message with + * cmd=WMI_EXTENSION_CMD. + */ + +#ifndef _WMIX_H_ +#define _WMIX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#include "dbglog.h" + +/* + * Extended WMI commands are those that are needed during wireless + * operation, but which are not really wireless commands. This allows, + * for instance, platform-specific commands. Extended WMI commands are + * embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID. + * Extended WMI events are similarly embedded in a WMI event message with + * WMI_EVENT_ID=WMI_EXTENSION_EVENTID. + */ +typedef PREPACK struct { + A_UINT32 commandId; +} POSTPACK WMIX_CMD_HDR; + +typedef enum { + WMIX_DSETOPEN_REPLY_CMDID = 0x2001, + WMIX_DSETDATA_REPLY_CMDID, + WMIX_GPIO_OUTPUT_SET_CMDID, + WMIX_GPIO_INPUT_GET_CMDID, + WMIX_GPIO_REGISTER_SET_CMDID, + WMIX_GPIO_REGISTER_GET_CMDID, + WMIX_GPIO_INTR_ACK_CMDID, + WMIX_HB_CHALLENGE_RESP_CMDID, + WMIX_DBGLOG_CFG_MODULE_CMDID, + WMIX_PROF_CFG_CMDID, /* 0x200a */ + WMIX_PROF_ADDR_SET_CMDID, + WMIX_PROF_START_CMDID, + WMIX_PROF_STOP_CMDID, + WMIX_PROF_COUNT_GET_CMDID, +} WMIX_COMMAND_ID; + +typedef enum { + WMIX_DSETOPENREQ_EVENTID = 0x3001, + WMIX_DSETCLOSE_EVENTID, + WMIX_DSETDATAREQ_EVENTID, + WMIX_GPIO_INTR_EVENTID, + WMIX_GPIO_DATA_EVENTID, + WMIX_GPIO_ACK_EVENTID, + WMIX_HB_CHALLENGE_RESP_EVENTID, + WMIX_DBGLOG_EVENTID, + WMIX_PROF_COUNT_EVENTID, +} WMIX_EVENT_ID; + +/* + * =============DataSet support================= + */ + +/* + * WMIX_DSETOPENREQ_EVENTID + * DataSet Open Request Event + */ +typedef PREPACK struct { + A_UINT32 dset_id; + A_UINT32 targ_dset_handle; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */ +} POSTPACK WMIX_DSETOPENREQ_EVENT; + +/* + * WMIX_DSETCLOSE_EVENTID + * DataSet Close Event + */ +typedef PREPACK struct { + A_UINT32 access_cookie; +} POSTPACK WMIX_DSETCLOSE_EVENT; + +/* + * WMIX_DSETDATAREQ_EVENTID + * DataSet Data Request Event + */ +typedef PREPACK struct { + A_UINT32 access_cookie; + A_UINT32 offset; + A_UINT32 length; + A_UINT32 targ_buf; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */ +} POSTPACK WMIX_DSETDATAREQ_EVENT; + +typedef PREPACK struct { + A_UINT32 status; + A_UINT32 targ_dset_handle; + A_UINT32 targ_reply_fn; + A_UINT32 targ_reply_arg; + A_UINT32 access_cookie; + A_UINT32 size; + A_UINT32 version; +} POSTPACK WMIX_DSETOPEN_REPLY_CMD; + +typedef PREPACK struct { + A_UINT32 status; + A_UINT32 targ_buf; + A_UINT32 targ_reply_fn; + A_UINT32 targ_reply_arg; + A_UINT32 length; + A_UINT8 buf[1]; +} POSTPACK WMIX_DSETDATA_REPLY_CMD; + + +/* + * =============GPIO support================= + * All masks are 18-bit masks with bit N operating on GPIO pin N. + */ + +#include "gpio.h" + +/* + * Set GPIO pin output state. + * In order for output to be driven, a pin must be enabled for output. + * This can be done during initialization through the GPIO Configuration + * DataSet, or during operation with the enable_mask. + * + * If a request is made to simultaneously set/clear or set/disable or + * clear/disable or disable/enable, results are undefined. + */ +typedef PREPACK struct { + A_UINT32 set_mask; /* pins to set */ + A_UINT32 clear_mask; /* pins to clear */ + A_UINT32 enable_mask; /* pins to enable for output */ + A_UINT32 disable_mask; /* pins to disable/tristate */ +} POSTPACK WMIX_GPIO_OUTPUT_SET_CMD; + +/* + * Set a GPIO register. For debug/exceptional cases. + * Values for gpioreg_id are GPIO_REGISTER_IDs, defined in a + * platform-dependent header. + */ +typedef PREPACK struct { + A_UINT32 gpioreg_id; /* GPIO register ID */ + A_UINT32 value; /* value to write */ +} POSTPACK WMIX_GPIO_REGISTER_SET_CMD; + +/* Get a GPIO register. For debug/exceptional cases. */ +typedef PREPACK struct { + A_UINT32 gpioreg_id; /* GPIO register to read */ +} POSTPACK WMIX_GPIO_REGISTER_GET_CMD; + +/* + * Host acknowledges and re-arms GPIO interrupts. A single + * message should be used to acknowledge all interrupts that + * were delivered in an earlier WMIX_GPIO_INTR_EVENT message. + */ +typedef PREPACK struct { + A_UINT32 ack_mask; /* interrupts to acknowledge */ +} POSTPACK WMIX_GPIO_INTR_ACK_CMD; + +/* + * Target informs Host of GPIO interrupts that have ocurred since the + * last WMIX_GIPO_INTR_ACK_CMD was received. Additional information -- + * the current GPIO input values is provided -- in order to support + * use of a GPIO interrupt as a Data Valid signal for other GPIO pins. + */ +typedef PREPACK struct { + A_UINT32 intr_mask; /* pending GPIO interrupts */ + A_UINT32 input_values; /* recent GPIO input values */ +} POSTPACK WMIX_GPIO_INTR_EVENT; + +/* + * Target responds to Host's earlier WMIX_GPIO_INPUT_GET_CMDID request + * using a GPIO_DATA_EVENT with + * value set to the mask of GPIO pin inputs and + * reg_id set to GPIO_ID_NONE + * + * + * Target responds to Hosts's earlier WMIX_GPIO_REGISTER_GET_CMDID request + * using a GPIO_DATA_EVENT with + * value set to the value of the requested register and + * reg_id identifying the register (reflects the original request) + * NB: reg_id supports the future possibility of unsolicited + * WMIX_GPIO_DATA_EVENTs (for polling GPIO input), and it may + * simplify Host GPIO support. + */ +typedef PREPACK struct { + A_UINT32 value; + A_UINT32 reg_id; +} POSTPACK WMIX_GPIO_DATA_EVENT; + +/* + * =============Error Detection support================= + */ + +/* + * WMIX_HB_CHALLENGE_RESP_CMDID + * Heartbeat Challenge Response command + */ +typedef PREPACK struct { + A_UINT32 cookie; + A_UINT32 source; +} POSTPACK WMIX_HB_CHALLENGE_RESP_CMD; + +/* + * WMIX_HB_CHALLENGE_RESP_EVENTID + * Heartbeat Challenge Response Event + */ +#define WMIX_HB_CHALLENGE_RESP_EVENT WMIX_HB_CHALLENGE_RESP_CMD + +typedef PREPACK struct { + struct dbglog_config_s config; +} POSTPACK WMIX_DBGLOG_CFG_MODULE_CMD; + +/* + * =============Target Profiling support================= + */ + +typedef PREPACK struct { + A_UINT32 period; /* Time (in 30.5us ticks) between samples */ + A_UINT32 nbins; +} POSTPACK WMIX_PROF_CFG_CMD; + +typedef PREPACK struct { + A_UINT32 addr; +} POSTPACK WMIX_PROF_ADDR_SET_CMD; + +/* + * Target responds to Hosts's earlier WMIX_PROF_COUNT_GET_CMDID request + * using a WMIX_PROF_COUNT_EVENT with + * addr set to the next address + * count set to the corresponding count + */ +typedef PREPACK struct { + A_UINT32 addr; + A_UINT32 count; +} POSTPACK WMIX_PROF_COUNT_EVENT; + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _WMIX_H_ */ diff -urN linux-2.6.26/drivers/of/base.c linux-2.6.26-lab126/drivers/of/base.c --- linux-2.6.26/drivers/of/base.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/of/base.c 2010-08-10 04:16:07.000000000 -0400 @@ -25,7 +25,7 @@ /* use when traversing tree through the allnext, child, sibling, * or parent members of struct device_node. */ -DEFINE_RWLOCK(devtree_lock); +DEFINE_RAW_RWLOCK(devtree_lock); int of_n_addr_cells(struct device_node *np) { diff -urN linux-2.6.26/drivers/oprofile/oprofilefs.c linux-2.6.26-lab126/drivers/oprofile/oprofilefs.c --- linux-2.6.26/drivers/oprofile/oprofilefs.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/oprofile/oprofilefs.c 2010-08-10 04:16:11.000000000 -0400 @@ -21,7 +21,7 @@ #define OPROFILEFS_MAGIC 0x6f70726f -DEFINE_SPINLOCK(oprofilefs_lock); +DEFINE_RAW_SPINLOCK(oprofilefs_lock); static struct inode * oprofilefs_get_inode(struct super_block * sb, int mode) { diff -urN linux-2.6.26/drivers/pci/.gitignore linux-2.6.26-lab126/drivers/pci/.gitignore --- linux-2.6.26/drivers/pci/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/pci/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,4 +0,0 @@ -classlist.h -devlist.h -gen-devlist - diff -urN linux-2.6.26/drivers/pci/access.c linux-2.6.26-lab126/drivers/pci/access.c --- linux-2.6.26/drivers/pci/access.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/pci/access.c 2010-08-10 04:15:58.000000000 -0400 @@ -12,7 +12,7 @@ * configuration space. */ -static DEFINE_SPINLOCK(pci_lock); +static DEFINE_RAW_SPINLOCK(pci_lock); /* * Wrappers for all PCI configuration access functions. They just check diff -urN linux-2.6.26/drivers/pci/hotplug/ibmphp_hpc.c linux-2.6.26-lab126/drivers/pci/hotplug/ibmphp_hpc.c --- linux-2.6.26/drivers/pci/hotplug/ibmphp_hpc.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/pci/hotplug/ibmphp_hpc.c 2010-08-10 04:15:58.000000000 -0400 @@ -104,7 +104,7 @@ static struct mutex sem_hpcaccess; // lock access to HPC static struct semaphore semOperations; // lock all operations and // access to data structures -static struct semaphore sem_exit; // make sure polling thread goes away +static struct compat_semaphore sem_exit; // make sure polling thread goes away static struct task_struct *ibmphp_poll_thread; //---------------------------------------------------------------------------- // local function prototypes diff -urN linux-2.6.26/drivers/pci/msi.c linux-2.6.26-lab126/drivers/pci/msi.c --- linux-2.6.26/drivers/pci/msi.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/pci/msi.c 2010-08-10 04:15:58.000000000 -0400 @@ -75,7 +75,7 @@ int pos; u16 control; - pos = pci_find_capability(dev, PCI_CAP_ID_MSI); + pos = pci_find_capability_cached(dev, PCI_CAP_ID_MSI); if (pos) { pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); control &= ~PCI_MSI_FLAGS_ENABLE; @@ -90,7 +90,7 @@ int pos; u16 control; - pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); + pos = pci_find_capability_cached(dev, PCI_CAP_ID_MSIX); if (pos) { pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); control &= ~PCI_MSIX_FLAGS_ENABLE; @@ -285,6 +285,10 @@ return; entry = get_irq_msi(dev->irq); + if (!entry) { + WARN_ON(1); + return; + } pos = entry->msi_attrib.pos; pci_intx_for_msi(dev, 0); @@ -352,7 +356,7 @@ msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */ - pos = pci_find_capability(dev, PCI_CAP_ID_MSI); + pos = pci_find_capability_cached(dev, PCI_CAP_ID_MSI); pci_read_config_word(dev, msi_control_reg(pos), &control); /* MSI Entry Initialization */ entry = alloc_msi_entry(); @@ -426,7 +430,7 @@ msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ - pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); + pos = pci_find_capability_cached(dev, PCI_CAP_ID_MSIX); /* Request & Map MSI-X table region */ pci_read_config_word(dev, msi_control_reg(pos), &control); nr_entries = multi_msix_capable(control); @@ -533,7 +537,7 @@ if (ret) return ret; - if (!pci_find_capability(dev, type)) + if (!pci_find_capability_cached(dev, type)) return -EINVAL; return 0; @@ -667,7 +671,7 @@ if (status) return status; - pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); + pos = pci_find_capability_cached(dev, PCI_CAP_ID_MSIX); pci_read_config_word(dev, msi_control_reg(pos), &control); nr_entries = multi_msix_capable(control); if (nvec > nr_entries) diff -urN linux-2.6.26/drivers/pci/pci.c linux-2.6.26-lab126/drivers/pci/pci.c --- linux-2.6.26/drivers/pci/pci.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/pci/pci.c 2010-08-10 04:15:58.000000000 -0400 @@ -171,6 +171,42 @@ } /** + * pci_find_capability_cached - query for devices' capabilities, cached version + * @dev: PCI device to query + * @cap: capability code + * + * Tell if a device supports a given PCI capability. + * Returns the address of the requested capability structure within the + * device's PCI configuration space or 0 in case the device does not + * support it. Possible values for @cap: + * + * %PCI_CAP_ID_PM Power Management + * %PCI_CAP_ID_AGP Accelerated Graphics Port + * %PCI_CAP_ID_VPD Vital Product Data + * %PCI_CAP_ID_SLOTID Slot Identification + * %PCI_CAP_ID_MSI Message Signalled Interrupts + * %PCI_CAP_ID_CHSWP CompactPCI HotSwap + * %PCI_CAP_ID_PCIX PCI-X + * %PCI_CAP_ID_EXP PCI Express + */ +int pci_find_capability_cached(struct pci_dev *dev, int cap) +{ + int pos = 0; + + WARN_ON_ONCE(cap <= 0 || cap > PCI_CAP_LIST_NR_ENTRIES); + + if (cap <= PCI_CAP_LIST_NR_ENTRIES) { + const int i = cap - 1; + if (dev->cached_capabilities[i] == -1) + dev->cached_capabilities[i] = pci_find_capability(dev, cap); + + pos = dev->cached_capabilities[i]; + } + + return pos; +} + +/** * pci_bus_find_capability - query for devices' capabilities * @bus: the PCI bus to query * @devfn: PCI device to query diff -urN linux-2.6.26/drivers/pci/probe.c linux-2.6.26-lab126/drivers/pci/probe.c --- linux-2.6.26/drivers/pci/probe.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/pci/probe.c 2010-08-10 04:15:58.000000000 -0400 @@ -886,6 +886,7 @@ struct pci_dev *alloc_pci_dev(void) { + int i; struct pci_dev *dev; dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); @@ -894,6 +895,9 @@ INIT_LIST_HEAD(&dev->bus_list); + for (i = 0; i < ARRAY_SIZE(dev->cached_capabilities); ++i) + dev->cached_capabilities[i] = -1; + pci_msi_init_pci_dev(dev); return dev; diff -urN linux-2.6.26/drivers/pcmcia/Kconfig linux-2.6.26-lab126/drivers/pcmcia/Kconfig --- linux-2.6.26/drivers/pcmcia/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/pcmcia/Kconfig 2010-08-10 04:16:04.000000000 -0400 @@ -270,6 +270,14 @@ Say Y here to support the CompactFlash controller on AT91 chips. Or choose M to compile the driver as a module named "at91_cf". +config PCMCIA_MX31ADS + tristate "MX31ADS PCMCIA support" + depends on ARM && MACH_MX31ADS && PCMCIA + help + Say Y here to include support for the Freescale i.MX31 PCMCIA controller. + + This driver is also available as a module called mx31ads_pcmcia. + config ELECTRA_CF tristate "Electra CompactFlash Controller" depends on PCMCIA && PPC_PASEMI diff -urN linux-2.6.26/drivers/pcmcia/Makefile linux-2.6.26-lab126/drivers/pcmcia/Makefile --- linux-2.6.26/drivers/pcmcia/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/pcmcia/Makefile 2010-08-10 04:16:04.000000000 -0400 @@ -38,6 +38,7 @@ obj-$(CONFIG_OMAP_CF) += omap_cf.o obj-$(CONFIG_AT91_CF) += at91_cf.o obj-$(CONFIG_ELECTRA_CF) += electra_cf.o +obj-$(CONFIG_PCMCIA_MX31ADS) += mx31ads-pcmcia.o sa11xx_core-y += soc_common.o sa11xx_base.o pxa2xx_core-y += soc_common.o pxa2xx_base.o diff -urN linux-2.6.26/drivers/pcmcia/mx31ads-pcmcia.c linux-2.6.26-lab126/drivers/pcmcia/mx31ads-pcmcia.c --- linux-2.6.26/drivers/pcmcia/mx31ads-pcmcia.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/pcmcia/mx31ads-pcmcia.c 2010-08-10 04:16:04.000000000 -0400 @@ -0,0 +1,1293 @@ +/*====================================================================== + drivers/pcmcia/mx31ads-pcmica.c + + Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + + Device driver for the PCMCIA control functionality of i.Mx31 + microprocessors. + + The contents of this file are subject to the Mozilla Public + License Version 1.1 (the "License"); you may not use this file + except in compliance with the License. You may obtain a copy of + the License at http://www.mozilla.org/MPL/ + + Software distributed under the License is distributed on an "AS + IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or + implied. See the License for the specific language governing + rights and limitations under the License. + + The initial developer of the original code is John G. Dorsey + . Portions created by John G. Dorsey are + Copyright (C) 1999 John G. Dorsey. All Rights Reserved. + + Alternatively, the contents of this file may be used under the + terms of the GNU Public License version 2 (the "GPL"), in which + case the provisions of the GPL are applicable instead of the + above. If you wish to allow the use of your version of this file + only under the terms of the GPL and not to allow others to use + your version of this file under the MPL, indicate your decision + by deleting the provisions above and replace them with the notice + and other provisions required by the GPL. If you do not delete + the provisions above, a recipient may use your version of this + file under either the MPL or the GPL. + +======================================================================*/ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "mx31ads-pcmcia.h" +#include + +#define MX31ADS_PCMCIA_IRQ MXC_INT_PCMCIA + +/* + * The mapping of window size to bank size value + */ +static bsize_map_t bsize_map[] = { + /* Window size Bank size */ + {POR_1, POR_BSIZE_1}, + {POR_2, POR_BSIZE_2}, + {POR_4, POR_BSIZE_4}, + {POR_8, POR_BSIZE_8}, + {POR_16, POR_BSIZE_16}, + {POR_32, POR_BSIZE_32}, + {POR_64, POR_BSIZE_64}, + {POR_128, POR_BSIZE_128}, + {POR_256, POR_BSIZE_256}, + {POR_512, POR_BSIZE_512}, + + {POR_1K, POR_BSIZE_1K}, + {POR_2K, POR_BSIZE_2K}, + {POR_4K, POR_BSIZE_4K}, + {POR_8K, POR_BSIZE_8K}, + {POR_16K, POR_BSIZE_16K}, + {POR_32K, POR_BSIZE_32K}, + {POR_64K, POR_BSIZE_64K}, + {POR_128K, POR_BSIZE_128K}, + {POR_256K, POR_BSIZE_256K}, + {POR_512K, POR_BSIZE_512K}, + + {POR_1M, POR_BSIZE_1M}, + {POR_2M, POR_BSIZE_2M}, + {POR_4M, POR_BSIZE_4M}, + {POR_8M, POR_BSIZE_8M}, + {POR_16M, POR_BSIZE_16M}, + {POR_32M, POR_BSIZE_32M}, + {POR_64M, POR_BSIZE_64M} +}; + +#define to_mx31ads_pcmcia_socket(x) container_of(x, struct mx31ads_pcmcia_socket, socket) + +/* mx31ads_pcmcia_find_bsize() + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + * + * Find the bsize according to the window size passed in + * + * Return: + */ +static int mx31ads_pcmcia_find_bsize(unsigned long win_size) +{ + int i, nr = sizeof(bsize_map) / sizeof(bsize_map_t); + int bsize = -1; + + for (i = 0; i < nr; i++) { + if (bsize_map[i].win_size == win_size) { + bsize = bsize_map[i].bsize; + break; + } + } + + pr_debug(KERN_INFO "nr = %d bsize = 0x%0x\n", nr, bsize); + if (bsize < 0 || i > nr) { + pr_debug(KERN_INFO "No such bsize\n"); + return -ENODEV; + } + + return bsize; +} + +/* mx31ads_common_pcmcia_sock_init() + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + * + * (Re-)Initialise the socket, turning on status interrupts + * and PCMCIA bus. This must wait for power to stabilise + * so that the card status signals report correctly. + * + * Returns: 0 + */ +static int mx31ads_common_pcmcia_sock_init(struct pcmcia_socket *sock) +{ + struct mx31ads_pcmcia_socket *skt = to_mx31ads_pcmcia_socket(sock); + + pr_debug(KERN_INFO "initializing socket\n"); + + skt->ops->socket_init(skt); + return 0; +} + +/* + * mx31ads_common_pcmcia_config_skt + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + * + * Convert PCMCIA socket state to our socket configure structure. + */ +static int +mx31ads_common_pcmcia_config_skt(struct mx31ads_pcmcia_socket *skt, + socket_state_t * state) +{ + int ret; + + ret = skt->ops->configure_socket(skt, state); + if (ret == 0) { + /* + * This really needs a better solution. The IRQ + * may or may not be claimed by the driver. + */ + if (skt->irq_state != 1 && state->io_irq) { + skt->irq_state = 1; + set_irq_type(skt->irq, IRQF_TRIGGER_FALLING); + } else if (skt->irq_state == 1 && state->io_irq == 0) { + skt->irq_state = 0; + set_irq_type(skt->irq, IRQF_TRIGGER_RISING); + } + + skt->cs_state = *state; + } + + if (ret < 0) + pr_debug(KERN_ERR "mx31ads_common_pcmcia: unable to configure" + " socket\n"); + + return ret; +} + +/* + * mx31ads_common_pcmcia_suspend() + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^ + * + * Remove power on the socket, disable IRQs from the card. + * Turn off status interrupts, and disable the PCMCIA bus. + * + * Returns: 0 + */ +static int mx31ads_common_pcmcia_suspend(struct pcmcia_socket *sock) +{ + struct mx31ads_pcmcia_socket *skt = to_mx31ads_pcmcia_socket(sock); + int ret; + + pr_debug(KERN_INFO "suspending socket\n"); + + ret = mx31ads_common_pcmcia_config_skt(skt, &dead_socket); + if (ret == 0) + skt->ops->socket_suspend(skt); + + return ret; +} + +static unsigned int mx31ads_common_pcmcia_skt_state(struct mx31ads_pcmcia_socket + *skt) +{ + struct pcmcia_state state; + unsigned int stat; + + memset(&state, 0, sizeof(struct pcmcia_state)); + + skt->ops->socket_state(skt, &state); + + stat = state.detect ? SS_DETECT : 0; + stat |= state.ready ? SS_READY : 0; + stat |= state.wrprot ? SS_WRPROT : 0; + stat |= state.vs_3v ? SS_3VCARD : 0; + stat |= state.vs_Xv ? SS_XVCARD : 0; + + /* The power status of individual sockets is not available + * explicitly from the hardware, so we just remember the state + * and regurgitate it upon request: + */ + stat |= skt->cs_state.Vcc ? SS_POWERON : 0; + + if (skt->cs_state.flags & SS_IOCARD) + stat |= state.bvd1 ? SS_STSCHG : 0; + else { + if (state.bvd1 == 0) + stat |= SS_BATDEAD; + else if (state.bvd2 == 0) + stat |= SS_BATWARN; + } + + pr_debug(KERN_INFO "stat = 0x%08x\n", stat); + + return stat; +} + +/* + * Implements the get_status() operation for the in-kernel PCMCIA + * service (formerly SS_GetStatus in Card Services). Essentially just + * fills in bits in `status' according to internal driver state or + * the value of the voltage detect chipselect register. + * + * As a debugging note, during card startup, the PCMCIA core issues + * three set_socket() commands in a row the first with RESET deasserted, + * the second with RESET asserted, and the last with RESET deasserted + * again. Following the third set_socket(), a get_status() command will + * be issued. The kernel is looking for the SS_READY flag (see + * setup_socket(), reset_socket(), and unreset_socket() in cs.c). + * + * Returns: 0 + */ +static int mx31ads_common_pcmcia_get_status(struct pcmcia_socket *sock, + unsigned int *status) +{ + struct mx31ads_pcmcia_socket *skt = to_mx31ads_pcmcia_socket(sock); + + skt->status = mx31ads_common_pcmcia_skt_state(skt); + *status = skt->status; + + return 0; +} + +/* + * Implements the set_socket() operation for the in-kernel PCMCIA + * service (formerly SS_SetSocket in Card Services). We more or + * less punt all of this work and let the kernel handle the details + * of power configuration, reset, &c. We also record the value of + * `state' in order to regurgitate it to the PCMCIA core later. + * + * Returns: 0 + */ +static int mx31ads_common_pcmcia_set_socket(struct pcmcia_socket *sock, + socket_state_t * state) +{ + struct mx31ads_pcmcia_socket *skt = to_mx31ads_pcmcia_socket(sock); + + pr_debug(KERN_INFO + "mask: %s%s%s%s%s%sflags: %s%s%s%s%s%sVcc %d Vpp %d irq %d\n", + (state->csc_mask == 0) ? " " : "", + (state->csc_mask & SS_DETECT) ? "DETECT " : "", + (state->csc_mask & SS_READY) ? "READY " : "", + (state->csc_mask & SS_BATDEAD) ? "BATDEAD " : "", + (state->csc_mask & SS_BATWARN) ? "BATWARN " : "", + (state->csc_mask & SS_STSCHG) ? "STSCHG " : "", + (state->flags == 0) ? " " : "", + (state->flags & SS_PWR_AUTO) ? "PWR_AUTO " : "", + (state->flags & SS_IOCARD) ? "IOCARD " : "", + (state->flags & SS_RESET) ? "RESET " : "", + (state->flags & SS_SPKR_ENA) ? "SPKR_ENA " : "", + (state->flags & SS_OUTPUT_ENA) ? "OUTPUT_ENA " : "", + state->Vcc, state->Vpp, state->io_irq); + + pr_debug(KERN_INFO + "csc_mask: %08x flags: %08x Vcc: %d Vpp: %d io_irq: %d\n", + state->csc_mask, state->flags, state->Vcc, state->Vpp, + state->io_irq); + + return mx31ads_common_pcmcia_config_skt(skt, state); +} + +/* + * Set address and profile to window registers PBR, POR, POFR + */ +static int mx31ads_pcmcia_set_window_reg(ulong start, ulong end, u_int window) +{ + int bsize; + ulong size = end - start + 1; + + bsize = mx31ads_pcmcia_find_bsize(size); + if (bsize < 0) { + pr_debug("Cannot set the window register\n"); + return -1; + } + /* Disable the window */ + _reg_PCMCIA_POR(window) &= ~PCMCIA_POR_PV; + + /* Set PBR, POR, POFR */ + _reg_PCMCIA_PBR(window) = start; + _reg_PCMCIA_POR(window) &= ~(PCMCIA_POR_PRS_MASK + | PCMCIA_POR_WPEN + | PCMCIA_POR_WP + | PCMCIA_POR_BSIZE_MASK + | PCMCIA_POR_PPS_8); + _reg_PCMCIA_POR(window) |= bsize | PCMCIA_POR_PPS_16; + + switch (window) { + case IO_WINDOW: + _reg_PCMCIA_POR(window) |= PCMCIA_POR_PRS(PCMCIA_POR_PRS_IO); + break; + + case ATTRIBUTE_MEMORY_WINDOW: + _reg_PCMCIA_POR(window) |= + PCMCIA_POR_PRS(PCMCIA_POR_PRS_ATTRIBUTE); + break; + + case COMMON_MEMORY_WINDOW: + _reg_PCMCIA_POR(window) |= + PCMCIA_POR_PRS(PCMCIA_POR_PRS_COMMON); + break; + + default: + pr_debug("Window %d is not support\n", window); + return -1; + } + _reg_PCMCIA_POFR(window) = 0; + + /* Enable the window */ + _reg_PCMCIA_POR(window) |= PCMCIA_POR_PV; + + return 0; +} + +/* + * Implements the set_io_map() operation for the in-kernel PCMCIA + * service (formerly SS_SetIOMap in Card Services). We configure + * the map speed as requested, but override the address ranges + * supplied by Card Services. + * + * Returns: 0 on success, -1 on error + */ +static int +mx31ads_common_pcmcia_set_io_map(struct pcmcia_socket *sock, + struct pccard_io_map *map) +{ + struct mx31ads_pcmcia_socket *skt = to_mx31ads_pcmcia_socket(sock); + unsigned short speed = map->speed; + + pr_debug("map %u speed %u start 0x%08lx stop 0x%08lx\n", + map->map, map->speed, map->start, map->stop); + pr_debug("flags: %s%s%s%s%s%s%s%s\n", + (map->flags == 0) ? "" : "", + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "", + (map->flags & MAP_16BIT) ? "16BIT " : "", + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "", + (map->flags & MAP_0WS) ? "0WS " : "", + (map->flags & MAP_WRPROT) ? "WRPROT " : "", + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "", + (map->flags & MAP_PREFETCH) ? "PREFETCH " : ""); + + if (map->map >= MAX_IO_WIN) { + pr_debug(KERN_ERR "%s(): map (%d) out of range\n", __FUNCTION__, + map->map); + return -1; + } + + if (map->flags & MAP_ACTIVE) { + if (speed == 0) + speed = PCMCIA_IO_ACCESS; + } else { + speed = 0; + } + + skt->spd_io[map->map] = speed; + skt->ops->set_timing(skt); + + if (map->stop == 1) + map->stop = PAGE_SIZE - 1; + + skt->socket.io_offset = (unsigned long)skt->virt_io; + map->stop -= map->start; + map->stop += (unsigned long)skt->virt_io; + map->start = (unsigned long)skt->virt_io; + + mx31ads_pcmcia_set_window_reg(skt->res_io.start, skt->res_io.end, + IO_WINDOW); + + pr_debug(KERN_ERR "IO window: _reg_PCMCIA_PBR(%d) = %08x\n", + IO_WINDOW, _reg_PCMCIA_PBR(IO_WINDOW)); + pr_debug(KERN_ERR "IO window: _reg_PCMCIA_POR(%d) = %08x\n", + IO_WINDOW, _reg_PCMCIA_POR(IO_WINDOW)); + + return 0; +} + +/* + * Implements the set_mem_map() operation for the in-kernel PCMCIA + * service (formerly SS_SetMemMap in Card Services). We configure + * the map speed as requested, but override the address ranges + * supplied by Card Services. + * + * Returns: 0 on success, -1 on error + */ +static int +mx31ads_common_pcmcia_set_mem_map(struct pcmcia_socket *sock, + struct pccard_mem_map *map) +{ + struct mx31ads_pcmcia_socket *skt = to_mx31ads_pcmcia_socket(sock); + struct resource *res; + unsigned short speed = map->speed; + + pr_debug + (KERN_INFO + "map %u speed %u card_start %08x flags%08x static_start %08lx\n", + map->map, map->speed, map->card_start, map->flags, + map->static_start); + pr_debug(KERN_INFO "flags: %s%s%s%s%s%s%s%s\n", + (map->flags == 0) ? "" : "", + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "", + (map->flags & MAP_16BIT) ? "16BIT " : "", + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "", + (map->flags & MAP_0WS) ? "0WS " : "", + (map->flags & MAP_WRPROT) ? "WRPROT " : "", + (map->flags & MAP_ATTRIB) ? "ATTRIB " : "", + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : ""); + + if (map->map >= MAX_WIN) + return -EINVAL; + + if (map->flags & MAP_ACTIVE) { + if (speed == 0) + speed = 300; + } else { + speed = 0; + } + + if (map->flags & MAP_ATTRIB) { + res = &skt->res_attr; + skt->spd_attr[map->map] = speed; + skt->spd_mem[map->map] = 0; + mx31ads_pcmcia_set_window_reg(res->start, res->end, + ATTRIBUTE_MEMORY_WINDOW); + + pr_debug(KERN_INFO "Attr window: _reg_PCMCIA_PBR(%d) = %08x\n", + ATTRIBUTE_MEMORY_WINDOW, + _reg_PCMCIA_PBR(ATTRIBUTE_MEMORY_WINDOW)); + pr_debug(KERN_INFO "_reg_PCMCIA_POR(%d) = %08x\n", + ATTRIBUTE_MEMORY_WINDOW, + _reg_PCMCIA_POR(ATTRIBUTE_MEMORY_WINDOW)); + + } else { + res = &skt->res_mem; + skt->spd_attr[map->map] = 0; + skt->spd_mem[map->map] = speed; + mx31ads_pcmcia_set_window_reg(res->start, res->end, + COMMON_MEMORY_WINDOW); + + pr_debug(KERN_INFO "Com window: _reg_PCMCIA_PBR(%d) = %08x\n", + COMMON_MEMORY_WINDOW, + _reg_PCMCIA_PBR(COMMON_MEMORY_WINDOW)); + pr_debug(KERN_INFO "Com window: _reg_PCMCIA_POR(%d) = %08x\n", + COMMON_MEMORY_WINDOW, + _reg_PCMCIA_POR(COMMON_MEMORY_WINDOW)); + } + + skt->ops->set_timing(skt); + + map->static_start = res->start + map->card_start; + + return 0; +} + +static struct pccard_operations mx31ads_common_pcmcia_operations = { + .init = mx31ads_common_pcmcia_sock_init, + .suspend = mx31ads_common_pcmcia_suspend, + .get_status = mx31ads_common_pcmcia_get_status, + .set_socket = mx31ads_common_pcmcia_set_socket, + .set_io_map = mx31ads_common_pcmcia_set_io_map, + .set_mem_map = mx31ads_common_pcmcia_set_mem_map, +}; + +/* ============================================================================== */ + +static inline void mx31ads_pcmcia_irq_config(void) +{ + /* Setup irq */ + _reg_PCMCIA_PER = + (PCMCIA_PER_RDYLE | PCMCIA_PER_CDE1 | PCMCIA_PER_CDE2); +} + +static inline void mx31ads_pcmcia_invalidate_windows(void) +{ + int i; + + for (i = 0; i < PCMCIA_WINDOWS; i++) { + _reg_PCMCIA_PBR(i) = 0; + _reg_PCMCIA_POR(i) = 0; + _reg_PCMCIA_POFR(i) = 0; + } +} + +extern void gpio_pcmcia_active(void); +extern void gpio_pcmcia_inactive(void); + +static int mx31ads_pcmcia_hw_init(struct mx31ads_pcmcia_socket *skt) +{ + /* Configure the pins for PCMCIA */ + gpio_pcmcia_active(); + + /* + * enabling interrupts at this time causes a flood of interrupts + * if a card is present, so wait for configure_socket + * to enable them when requested. + * + * mx31ads_pcmcia_irq_config(); + */ + mx31ads_pcmcia_invalidate_windows(); + + /* Register interrupt. */ + skt->irq = MX31ADS_PCMCIA_IRQ; + + return 0; +} + +static void mx31ads_pcmcia_free_irq(struct mx31ads_pcmcia_socket *skt, + unsigned int irq) +{ + free_irq(irq, skt); +} + +static void mx31ads_pcmcia_hw_shutdown(struct mx31ads_pcmcia_socket *skt) +{ + mx31ads_pcmcia_invalidate_windows(); + mx31ads_pcmcia_free_irq(skt, MX31ADS_PCMCIA_IRQ); + + /* Disable the pins */ + gpio_pcmcia_inactive(); +} + +/* + * Get the socket state + */ +static void +mx31ads_pcmcia_socket_state(struct mx31ads_pcmcia_socket *skt, + struct pcmcia_state *state) +{ + unsigned long pins; + + pins = _reg_PCMCIA_PIPR; + pr_debug(KERN_INFO "_reg_PCMCIA_PIPR = 0x%08lx\n", pins); + + state->ready = (pins & PCMCIA_PIPR_RDY) ? 1 : 0; + state->bvd2 = (pins & PCMCIA_PIPR_BVD2) ? 1 : 0; + state->bvd1 = (pins & PCMCIA_PIPR_BVD1) ? 1 : 0; + + if ((pins & PCMCIA_PIPR_CD) == PCMCIA_PIPR_CD) { + state->detect = 0; + skt->cs_state.csc_mask |= SS_INSERTION; + } else { + state->detect = 1; + } + state->detect = (pins & PCMCIA_PIPR_CD) ? 0 : 1; + state->wrprot = (pins & PCMCIA_PIPR_WP) ? 1 : 0; + state->poweron = (pins & PCMCIA_PIPR_POWERON) ? 1 : 0; +#if 0 + if ((pins & PCMCIA_PIPR_CD) == PCMCIA_PIPR_CD) { + state->detect = 0; + skt->cs_state.csc_mask |= SS_INSERTION; + } else { + state->detect = 1; + } + if (pins & PCMCIA_PIPR_VS_5V) { + state->vs_3v = 0; + skt->cs_state.Vcc = 33; + } else { + state->vs_3v = 1; + skt->cs_state.Vcc = 50; + } +#endif + state->vs_3v = (pins & PCMCIA_PIPR_VS_5V) ? 0 : 1; + state->vs_Xv = 0; +} + +static __inline__ void mx31ads_pcmcia_low_power(bool enable) +{ + if (enable) + _reg_PCMCIA_PGCR |= PCMCIA_PGCR_LPMEN; + else + _reg_PCMCIA_PGCR &= ~PCMCIA_PGCR_LPMEN; +} + +static __inline__ void mx31ads_pcmcia_soft_reset(void) +{ + _reg_PCMCIA_PGCR |= PCMCIA_PGCR_RESET; + msleep(2); + + _reg_PCMCIA_PGCR &= ~(PCMCIA_PGCR_RESET | PCMCIA_PGCR_LPMEN); + _reg_PCMCIA_PGCR |= PCMCIA_PGCR_POE; + msleep(2); + pr_debug(KERN_INFO "_reg_PCMCIA_PGCR = %08x\n", _reg_PCMCIA_PGCR); +} + +static int +mx31ads_pcmcia_configure_socket(struct mx31ads_pcmcia_socket *skt, + const socket_state_t * state) +{ + int ret = 0; + + if (state->Vcc != 0 && state->Vcc != 33 && state->Vcc != 50) { + pr_debug(KERN_ERR "mx31ads-pcmcia: unrecognized Vcc %d\n", + state->Vcc); + return -1; + } + + pr_debug(KERN_INFO "PIPR = %x, desired Vcc = %d.%dV\n", + _reg_PCMCIA_PIPR, state->Vcc / 10, state->Vcc % 10); + + if (!(skt->socket.state & SOCKET_PRESENT) && (skt->pre_stat == 1)) { + pr_debug(KERN_INFO "Socket enter low power mode\n"); + skt->pre_stat = 0; + mx31ads_pcmcia_low_power(1); + } + + if (state->flags & SS_RESET) { + mx31ads_pcmcia_soft_reset(); + + /* clean out previous tenant's trash */ + _reg_PCMCIA_PGSR = (PCMCIA_PGSR_NWINE + | PCMCIA_PGSR_LPE + | PCMCIA_PGSR_SE + | PCMCIA_PGSR_CDE | PCMCIA_PGSR_WPE); + } + /* enable interrupts if requested, else turn 'em off */ + if (skt->irq) + mx31ads_pcmcia_irq_config(); + else + _reg_PCMCIA_PER = 0; + + if (skt->socket.state & SOCKET_PRESENT) { + skt->pre_stat = 1; + } + return ret; +} + +static void mx31ads_pcmcia_enable_irq(struct mx31ads_pcmcia_socket *skt, + unsigned int irq) +{ + set_irq_type(irq, IRQF_TRIGGER_RISING); + set_irq_type(irq, IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING); +} + +static void mx31ads_pcmcia_disable_irq(struct mx31ads_pcmcia_socket *skt, + unsigned int irq) +{ + set_irq_type(irq, IRQF_TRIGGER_NONE); +} + +/* + * Enable card status IRQs on (re-)initialisation. This can + * be called at initialisation, power management event, or + * pcmcia event. + */ +static void mx31ads_pcmcia_socket_init(struct mx31ads_pcmcia_socket *skt) +{ + mx31ads_pcmcia_soft_reset(); + + mx31ads_pcmcia_enable_irq(skt, MX31ADS_PCMCIA_IRQ); +} + +/* + * Disable card status IRQ on suspend. + */ +static void mx31ads_pcmcia_socket_suspend(struct mx31ads_pcmcia_socket *skt) +{ + mx31ads_pcmcia_disable_irq(skt, MX31ADS_PCMCIA_IRQ); + mx31ads_pcmcia_low_power(1); +} + +/* ==================================================================================== */ + +/* + * PCMCIA strobe hold time + */ +static inline u_int mx31ads_pcmcia_por_psht(u_int pcmcia_cycle_ns, + u_int hclk_cycle_ns) +{ + u_int psht; + + return psht = pcmcia_cycle_ns / hclk_cycle_ns; +} + +/* + * PCMCIA strobe set up time + */ +static inline u_int mx31ads_pcmcia_por_psst(u_int pcmcia_cycle_ns, + u_int hclk_cycle_ns) +{ + u_int psst; + + return psst = pcmcia_cycle_ns / hclk_cycle_ns; +} + +/* + * PCMCIA strobe length time + */ +static inline u_int mx31ads_pcmcia_por_pslt(u_int pcmcia_cycle_ns, + u_int hclk_cycle_ns) +{ + u_int pslt; + + return pslt = pcmcia_cycle_ns / hclk_cycle_ns + 2; +} + +/* + * mx31ads_pcmcia_default_mecr_timing + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + * + * Calculate MECR clock wait states for given CPU clock + * speed and command wait state. This function can be over- + * written by a board specific version. + * + * The default is to simply calculate the BS values as specified in + * the INTEL SA1100 development manual + * "Expansion Memory (PCMCIA) Configuration Register (MECR)" + * that's section 10.2.5 in _my_ version of the manual ;) + */ +static unsigned int mx31ads_pcmcia_default_mecr_timing(struct + mx31ads_pcmcia_socket + *skt, + unsigned int cpu_speed, + unsigned int cmd_time) +{ + return 0; +} + +/* + * Calculate the timing code + */ +static u_int mx31ads_pcmcia_cal_code(u_int speed_ns, u_int clk_ns) +{ + u_int code; + + code = PCMCIA_POR_PSHT(mx31ads_pcmcia_por_psht(speed_ns, clk_ns)) + | PCMCIA_POR_PSST(mx31ads_pcmcia_por_psst(speed_ns, clk_ns)) + | PCMCIA_POR_PSL(mx31ads_pcmcia_por_pslt(speed_ns, clk_ns)); + + return code; +} + +/* + * set MECR value for socket based on this sockets + * io, mem and attribute space access speed. + * Call board specific BS value calculation to allow boards + * to tweak the BS values. + */ +static int mx31ads_pcmcia_set_window_timing(u_int speed_ns, u_int window, + u_int clk_ns) +{ + u_int code = 0; + + switch (window) { + case IO_WINDOW: + code = mx31ads_pcmcia_cal_code(speed_ns, clk_ns); + break; + case COMMON_MEMORY_WINDOW: + code = mx31ads_pcmcia_cal_code(speed_ns, clk_ns); + break; + case ATTRIBUTE_MEMORY_WINDOW: + code = mx31ads_pcmcia_cal_code(speed_ns, clk_ns); + break; + default: + break; + } + + /* Disable the window */ + _reg_PCMCIA_POR(window) &= ~PCMCIA_POR_PV; + + /* Clear the register fisrt */ + _reg_PCMCIA_POR(window) &= ~(PCMCIA_POR_PSST_MASK + | PCMCIA_POR_PSL_MASK + | PCMCIA_POR_PSHT_MASK); + /* And then set the register */ + _reg_PCMCIA_POR(window) |= code; + + /* Enable the window */ + _reg_PCMCIA_POR(window) |= PCMCIA_POR_PV; + + return 0; +} + +static unsigned short calc_speed(unsigned short *spds, int num, + unsigned short dflt) +{ + unsigned short speed = 0; + int i; + + for (i = 0; i < num; i++) + if (speed < spds[i]) + speed = spds[i]; + if (speed == 0) + speed = dflt; + + return speed; +} + +static void +mx31ads_common_pcmcia_get_timing(struct mx31ads_pcmcia_socket *skt, + struct mx31ads_pcmcia_timing *timing) +{ + timing->io = calc_speed(skt->spd_io, MAX_IO_WIN, PCMCIA_IO_ACCESS); + timing->mem = calc_speed(skt->spd_mem, MAX_WIN, PCMCIA_3V_MEM_ACCESS); + timing->attr = + calc_speed(skt->spd_attr, MAX_WIN, PCMCIA_ATTR_MEM_ACCESS); +} + +static int mx31ads_pcmcia_set_timing(struct mx31ads_pcmcia_socket *skt) +{ + u_int clk_ns; + struct mx31ads_pcmcia_timing timing; + + /* How many nanoseconds */ + clk_ns = (1000 * 1000 * 1000) / clk_get_rate(skt->clk); + pr_debug(KERN_INFO "clk_ns = %d\n", clk_ns); + + mx31ads_common_pcmcia_get_timing(skt, &timing); + pr_debug(KERN_INFO "timing: io %d, mem %d, attr %d\n", timing.io, + timing.mem, timing.attr); + + mx31ads_pcmcia_set_window_timing(timing.io, IO_WINDOW, clk_ns); + mx31ads_pcmcia_set_window_timing(timing.mem, COMMON_MEMORY_WINDOW, + clk_ns); + mx31ads_pcmcia_set_window_timing(timing.attr, ATTRIBUTE_MEMORY_WINDOW, + clk_ns); + + return 0; +} + +static int mx31ads_pcmcia_show_timing(struct mx31ads_pcmcia_socket *skt, + char *buf) +{ + return 0; +} + +static struct pcmcia_low_level mx31ads_pcmcia_ops = { + .owner = THIS_MODULE, + .hw_init = mx31ads_pcmcia_hw_init, + .hw_shutdown = mx31ads_pcmcia_hw_shutdown, + .socket_state = mx31ads_pcmcia_socket_state, + .configure_socket = mx31ads_pcmcia_configure_socket, + + .socket_init = mx31ads_pcmcia_socket_init, + .socket_suspend = mx31ads_pcmcia_socket_suspend, + + .get_timing = mx31ads_pcmcia_default_mecr_timing, + .set_timing = mx31ads_pcmcia_set_timing, + .show_timing = mx31ads_pcmcia_show_timing, +}; + +/* =================================================================================== */ + +LIST_HEAD(mx31ads_pcmcia_sockets); +DECLARE_MUTEX(mx31ads_pcmcia_sockets_lock); + +static DEFINE_SPINLOCK(status_lock); + +struct bittbl { + unsigned int mask; + const char *name; +}; + +static struct bittbl status_bits[] = { + {SS_WRPROT, "SS_WRPROT"}, + {SS_BATDEAD, "SS_BATDEAD"}, + {SS_BATWARN, "SS_BATWARN"}, + {SS_READY, "SS_READY"}, + {SS_DETECT, "SS_DETECT"}, + {SS_POWERON, "SS_POWERON"}, + {SS_STSCHG, "SS_STSCHG"}, + {SS_3VCARD, "SS_3VCARD"}, + {SS_XVCARD, "SS_XVCARD"}, +}; + +static struct bittbl conf_bits[] = { + {SS_PWR_AUTO, "SS_PWR_AUTO"}, + {SS_IOCARD, "SS_IOCARD"}, + {SS_RESET, "SS_RESET"}, + {SS_DMA_MODE, "SS_DMA_MODE"}, + {SS_SPKR_ENA, "SS_SPKR_ENA"}, + {SS_OUTPUT_ENA, "SS_OUTPUT_ENA"}, +}; + +static void +dump_bits(char **p, const char *prefix, unsigned int val, struct bittbl *bits, + int sz) +{ + char *b = *p; + int i; + + b += sprintf(b, "%-9s:", prefix); + for (i = 0; i < sz; i++) + if (val & bits[i].mask) + b += sprintf(b, " %s", bits[i].name); + *b++ = '\n'; + *p = b; +} + +/* + * Implements the /sys/class/pcmcia_socket/??/status file. + * + * Returns: the number of characters added to the buffer + */ +static ssize_t show_status(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct mx31ads_pcmcia_socket *skt = + container_of(dev, struct mx31ads_pcmcia_socket, socket.dev); + char *p = buf; + + p += sprintf(p, "slot : %d\n", skt->nr); + + dump_bits(&p, "status", skt->status, + status_bits, ARRAY_SIZE(status_bits)); + dump_bits(&p, "csc_mask", skt->cs_state.csc_mask, + status_bits, ARRAY_SIZE(status_bits)); + dump_bits(&p, "cs_flags", skt->cs_state.flags, + conf_bits, ARRAY_SIZE(conf_bits)); + + p += sprintf(p, "Vcc : %d\n", skt->cs_state.Vcc); + p += sprintf(p, "Vpp : %d\n", skt->cs_state.Vpp); + p += sprintf(p, "IRQ : %d (%d)\n", skt->cs_state.io_irq, skt->irq); + if (skt->ops->show_timing) + p += skt->ops->show_timing(skt, p); + + return p - buf; +} + +static DEVICE_ATTR(status, S_IRUGO, show_status, NULL); + +static void mx31ads_common_check_status(struct mx31ads_pcmcia_socket *skt) +{ + unsigned int events; + + pr_debug(KERN_INFO "entering PCMCIA monitoring thread\n"); + + do { + unsigned int status; + unsigned long flags; + + status = mx31ads_common_pcmcia_skt_state(skt); + + spin_lock_irqsave(&status_lock, flags); + events = (status ^ skt->status) & skt->cs_state.csc_mask; + skt->status = status; + spin_unlock_irqrestore(&status_lock, flags); + + pr_debug(KERN_INFO "events: %s%s%s%s%s%s\n", + events == 0 ? "" : "", + events & SS_DETECT ? "DETECT " : "", + events & SS_READY ? "READY " : "", + events & SS_BATDEAD ? "BATDEAD " : "", + events & SS_BATWARN ? "BATWARN " : "", + events & SS_STSCHG ? "STSCHG " : ""); + + if (events) + pcmcia_parse_events(&skt->socket, events); + } while (events); +} + +/* + * Service routine for socket driver interrupts (requested by the + * low-level PCMCIA init() operation via mx31ads_common_pcmcia_thread()). + * The actual interrupt-servicing work is performed by + * mx31ads_common_pcmcia_thread(), largely because the Card Services event- + * handling code performs scheduling operations which cannot be + * executed from within an interrupt context. + */ +static irqreturn_t mx31ads_common_pcmcia_interrupt(int irq, void *dev) +{ + struct mx31ads_pcmcia_socket *skt = dev; + volatile u32 pscr, pgsr; + + dev_dbg(dev, "servicing IRQ %d\n", irq); + + /* clear interrupt states */ + pscr = _reg_PCMCIA_PSCR; + _reg_PCMCIA_PSCR = pscr; + + pgsr = _reg_PCMCIA_PGSR; + _reg_PCMCIA_PGSR = pgsr; + + mx31ads_common_check_status(skt); + + return IRQ_HANDLED; +} + +/* Let's poll for events in addition to IRQs since IRQ only is unreliable... */ +static void mx31ads_common_pcmcia_poll_event(unsigned long dummy) +{ + struct mx31ads_pcmcia_socket *skt = + (struct mx31ads_pcmcia_socket *)dummy; + pr_debug(KERN_INFO "polling for events\n"); + + mod_timer(&skt->poll_timer, jiffies + PCMCIA_POLL_PERIOD); + + mx31ads_common_check_status(skt); +} + +#define mx31ads_pcmcia_cpufreq_register() +#define mx31ads_pcmcia_cpufreq_unregister() + +static int mx31ads_common_drv_pcmcia_probe(struct platform_device *pdev, + struct pcmcia_low_level *ops) +{ + struct mx31ads_pcmcia_socket *skt; + int vs, value, ret; + struct pccard_io_map map; + + down(&mx31ads_pcmcia_sockets_lock); + + skt = kzalloc(sizeof(struct mx31ads_pcmcia_socket), GFP_KERNEL); + if (!skt) { + ret = -ENOMEM; + goto out; + } + + /* + * Initialise the socket structure. + */ + skt->socket.ops = &mx31ads_common_pcmcia_operations; + skt->socket.owner = ops->owner; + skt->socket.driver_data = skt; + + init_timer(&skt->poll_timer); + skt->poll_timer.function = mx31ads_common_pcmcia_poll_event; + skt->poll_timer.data = (unsigned long)skt; + skt->poll_timer.expires = jiffies + PCMCIA_POLL_PERIOD; + + skt->irq = MX31ADS_PCMCIA_IRQ; + skt->socket.dev.parent = &pdev->dev; + skt->ops = ops; + + skt->clk = clk_get(NULL, "ahb_clk"); + + skt->res_skt.start = _PCMCIA(0); + skt->res_skt.end = _PCMCIA(0) + PCMCIASp - 1; + skt->res_skt.name = MX31ADS_PCMCIA; + skt->res_skt.flags = IORESOURCE_MEM; + + ret = request_resource(&iomem_resource, &skt->res_skt); + if (ret) + goto out_err_1; + + skt->res_io.start = _PCMCIAIO(0); + skt->res_io.end = _PCMCIAIO(0) + PCMCIAIOSp - 1; + skt->res_io.name = "io"; + skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY; + + ret = request_resource(&skt->res_skt, &skt->res_io); + if (ret) + goto out_err_2; + + skt->res_mem.start = _PCMCIAMem(0); + skt->res_mem.end = _PCMCIAMem(0) + PCMCIAMemSp - 1; + skt->res_mem.name = "memory"; + skt->res_mem.flags = IORESOURCE_MEM; + + ret = request_resource(&skt->res_skt, &skt->res_mem); + if (ret) + goto out_err_3; + + skt->res_attr.start = _PCMCIAAttr(0); + skt->res_attr.end = _PCMCIAAttr(0) + PCMCIAAttrSp - 1; + skt->res_attr.name = "attribute"; + skt->res_attr.flags = IORESOURCE_MEM; + + ret = request_resource(&skt->res_skt, &skt->res_attr); + if (ret) + goto out_err_4; + + skt->virt_io = ioremap(skt->res_io.start, 0x10000); + if (skt->virt_io == NULL) { + ret = -ENOMEM; + goto out_err_5; + } + + if (list_empty(&mx31ads_pcmcia_sockets)) + mx31ads_pcmcia_cpufreq_register(); + + list_add(&skt->node, &mx31ads_pcmcia_sockets); + + /* + * We initialize default socket timing here, because + * we are not guaranteed to see a SetIOMap operation at + * runtime. + */ + ops->set_timing(skt); + + ret = ops->hw_init(skt); + if (ret) + goto out_err_6; + + ret = request_irq(skt->irq, mx31ads_common_pcmcia_interrupt, + IRQF_SHARED | IRQF_DISABLED, "PCMCIA IRQ", skt); + if (ret) + goto out_err_6; + set_irq_type(skt->irq, IRQT_NOEDGE); + + skt->socket.features = SS_CAP_STATIC_MAP | SS_CAP_PCCARD; + skt->socket.resource_ops = &pccard_static_ops; + skt->socket.irq_mask = 0; + skt->socket.map_size = PCMCIAPrtSp; + skt->socket.pci_irq = skt->irq; + skt->socket.io_offset = (unsigned long)skt->virt_io; + + skt->status = mx31ads_common_pcmcia_skt_state(skt); + skt->pre_stat = 0; + ret = pcmcia_register_socket(&skt->socket); + if (ret) + goto out_err_7; + /* FIXED ME workaround for binding with ide-cs. ide usage io port 0x100~0x107 and 0x10e */ + map.map = 0; + map.flags = MAP_ACTIVE | MAP_16BIT; + map.start = 0; + map.stop = PCMCIAIOSp - 1; + map.speed = 0; + mx31ads_common_pcmcia_set_io_map(&skt->socket, &map); + + vs = _reg_PCMCIA_PIPR & PCMCIA_PIPR_VS; + value = vs & PCMCIA_PIPR_VS_5V ? 50 : 33; + dev_dbg(&pdev->dev, "PCMCIA: Voltage the card supports: %d.%dV\n", + value / 10, value % 10); + + add_timer(&skt->poll_timer); + + ret = device_create_file(&skt->socket.dev, &dev_attr_status); + if (ret < 0) + goto out_err_8; + + platform_set_drvdata(pdev, skt); + ret = 0; + goto out; + + out_err_8: + del_timer_sync(&skt->poll_timer); + pcmcia_unregister_socket(&skt->socket); + + out_err_7: + flush_scheduled_work(); + free_irq(skt->irq, skt); + ops->hw_shutdown(skt); + out_err_6: + list_del(&skt->node); + iounmap(skt->virt_io); + out_err_5: + release_resource(&skt->res_attr); + out_err_4: + release_resource(&skt->res_mem); + out_err_3: + release_resource(&skt->res_io); + out_err_2: + release_resource(&skt->res_skt); + out_err_1: + + kfree(skt); + out: + up(&mx31ads_pcmcia_sockets_lock); + return ret; +} + +static int mx31ads_drv_pcmcia_remove(struct platform_device *pdev) +{ + struct mx31ads_pcmcia_socket *skt = platform_get_drvdata(pdev); + + platform_set_drvdata(pdev, NULL); + + down(&mx31ads_pcmcia_sockets_lock); + + del_timer_sync(&skt->poll_timer); + + pcmcia_unregister_socket(&skt->socket); + + flush_scheduled_work(); + + skt->ops->hw_shutdown(skt); + + mx31ads_common_pcmcia_config_skt(skt, &dead_socket); + + list_del(&skt->node); + iounmap(skt->virt_io); + skt->virt_io = NULL; + release_resource(&skt->res_attr); + release_resource(&skt->res_mem); + release_resource(&skt->res_io); + release_resource(&skt->res_skt); + + if (list_empty(&mx31ads_pcmcia_sockets)) + mx31ads_pcmcia_cpufreq_unregister(); + + up(&mx31ads_pcmcia_sockets_lock); + + kfree(skt); + + return 0; +} + +static int mx31ads_drv_pcmcia_probe(struct platform_device *pdev) +{ + if (!machine_is_mx31ads()) + return -ENODEV; + + return mx31ads_common_drv_pcmcia_probe(pdev, &mx31ads_pcmcia_ops); +} + +static int mx31ads_drv_pcmcia_suspend(struct platform_device *pdev, + pm_message_t state) +{ + return pcmcia_socket_dev_suspend(&pdev->dev, state); +} + +static int mx31ads_drv_pcmcia_resume(struct platform_device *pdev) +{ + return pcmcia_socket_dev_resume(&pdev->dev); +} + +/* + * Low level functions + */ +static struct platform_driver mx31ads_pcmcia_driver = { + .driver = { + .name = MX31ADS_PCMCIA, + }, + .probe = mx31ads_drv_pcmcia_probe, + .remove = mx31ads_drv_pcmcia_remove, + .suspend = mx31ads_drv_pcmcia_suspend, + .resume = mx31ads_drv_pcmcia_resume, +}; + +/* mx31ads_pcmcia_init() + * + */ +static int __init mx31ads_pcmcia_init(void) +{ + int ret; + + if ((ret = platform_driver_register(&mx31ads_pcmcia_driver))) + return ret; + pr_debug(KERN_INFO "PCMCIA: Initialize i.Mx31 pcmcia socket\n"); + + return ret; +} + +/* mx31ads_pcmcia_exit() + * + */ +static void __exit mx31ads_pcmcia_exit(void) +{ + platform_driver_unregister(&mx31ads_pcmcia_driver); +} + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("i.MX31 PCMCIA Socket Controller"); +MODULE_LICENSE("GPL"); + +module_init(mx31ads_pcmcia_init); +module_exit(mx31ads_pcmcia_exit); diff -urN linux-2.6.26/drivers/pcmcia/mx31ads-pcmcia.h linux-2.6.26-lab126/drivers/pcmcia/mx31ads-pcmcia.h --- linux-2.6.26/drivers/pcmcia/mx31ads-pcmcia.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/pcmcia/mx31ads-pcmcia.h 2010-08-10 04:16:04.000000000 -0400 @@ -0,0 +1,157 @@ +/* + * linux/drivers/pcmcia/mx31ads-pcmcia.h + * + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This file contains definitions for the PCMCIA support code common to + * integrated SOCs like the i.Mx31 microprocessors. + */ +#ifndef _ASM_ARCH_PCMCIA +#define _ASM_ARCH_PCMCIA + +/* include the world */ +#include +#include +#include +#include +#include +#include +#include +#include "cs_internal.h" + +#define MX31ADS_PCMCIA "Mx31ads_pcmcia_socket" + +struct device; +struct pcmcia_low_level; + +/* + * This structure encapsulates per-socket state which we might need to + * use when responding to a Card Services query of some kind. + */ +struct mx31ads_pcmcia_socket { + struct pcmcia_socket socket; + + /* + * Info from low level handler + */ + struct device *dev; + unsigned int nr; + unsigned int irq; + + struct clk *clk; + + /* + * Core PCMCIA state + */ + struct pcmcia_low_level *ops; + + unsigned int status; + unsigned int pre_stat; + socket_state_t cs_state; + + unsigned short spd_io[MAX_IO_WIN]; + unsigned short spd_mem[MAX_WIN]; + unsigned short spd_attr[MAX_WIN]; + + struct resource res_skt; + struct resource res_io; + struct resource res_mem; + struct resource res_attr; + void *virt_io; + + unsigned int irq_state; + + struct timer_list poll_timer; + struct list_head node; +}; + +struct pcmcia_state { + unsigned detect:1, + ready:1, bvd1:1, bvd2:1, wrprot:1, vs_3v:1, vs_Xv:1, poweron:1; +}; + +struct pcmcia_low_level { + struct module *owner; + + /* first socket in system */ + int first; + /* nr of sockets */ + int nr; + + int (*hw_init) (struct mx31ads_pcmcia_socket *); + void (*hw_shutdown) (struct mx31ads_pcmcia_socket *); + + void (*socket_state) (struct mx31ads_pcmcia_socket *, + struct pcmcia_state *); + int (*configure_socket) (struct mx31ads_pcmcia_socket *, + const socket_state_t *); + + /* + * Enable card status IRQs on (re-)initialisation. This can + * be called at initialisation, power management event, or + * pcmcia event. + */ + void (*socket_init) (struct mx31ads_pcmcia_socket *); + + /* + * Disable card status IRQs and PCMCIA bus on suspend. + */ + void (*socket_suspend) (struct mx31ads_pcmcia_socket *); + + /* + * Hardware specific timing routines. + * If provided, the get_timing routine overrides the SOC default. + */ + unsigned int (*get_timing) (struct mx31ads_pcmcia_socket *, + unsigned int, unsigned int); + int (*set_timing) (struct mx31ads_pcmcia_socket *); + int (*show_timing) (struct mx31ads_pcmcia_socket *, char *); + +#ifdef CONFIG_CPU_FREQ + /* + * CPUFREQ support. + */ + int (*frequency_change) (struct mx31ads_pcmcia_socket *, unsigned long, + struct cpufreq_freqs *); +#endif +}; + +struct mx31ads_pcmcia_timing { + unsigned short io; + unsigned short mem; + unsigned short attr; +}; + +typedef struct { + ulong win_size; + int bsize; +} bsize_map_t; + +/* + * The PC Card Standard, Release 7, section 4.13.4, says that twIORD + * has a minimum value of 165ns. Section 4.13.5 says that twIOWR has + * a minimum value of 165ns, as well. Section 4.7.2 (describing + * common and attribute memory write timing) says that twWE has a + * minimum value of 150ns for a 250ns cycle time (for 5V operation; + * see section 4.7.4), or 300ns for a 600ns cycle time (for 3.3V + * operation, also section 4.7.4). Section 4.7.3 says that taOE + * has a maximum value of 150ns for a 300ns cycle time (for 5V + * operation), or 300ns for a 600ns cycle time (for 3.3V operation). + * + * When configuring memory maps, Card Services appears to adopt the policy + * that a memory access time of "0" means "use the default." The default + * PCMCIA I/O command width time is 165ns. The default PCMCIA 5V attribute + * and memory command width time is 150ns; the PCMCIA 3.3V attribute and + * memory command width time is 300ns. + */ +#define PCMCIA_IO_ACCESS (165) +#define PCMCIA_5V_MEM_ACCESS (150) +#define PCMCIA_3V_MEM_ACCESS (300) +#define PCMCIA_ATTR_MEM_ACCESS (300) + +/* + * The socket driver actually works nicely in interrupt-driven form, + * so the (relatively infrequent) polling is "just to be sure." + */ +#define PCMCIA_POLL_PERIOD (2*HZ) +#endif diff -urN linux-2.6.26/drivers/power/Kconfig linux-2.6.26-lab126/drivers/power/Kconfig --- linux-2.6.26/drivers/power/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/power/Kconfig 2010-08-10 04:16:03.000000000 -0400 @@ -36,6 +36,11 @@ help Say Y here to enable support for batteries with ds2760 chip. +config BATTERY_LUIGI + tristate "MX35 Luigi Battery Driver" + help + Say Y to enable support for reading the MX35 Luigi Battery + config BATTERY_PMU tristate "Apple PMU battery" depends on PPC32 && ADB_PMU diff -urN linux-2.6.26/drivers/power/Makefile linux-2.6.26-lab126/drivers/power/Makefile --- linux-2.6.26/drivers/power/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/power/Makefile 2010-08-10 04:16:03.000000000 -0400 @@ -20,3 +20,4 @@ obj-$(CONFIG_BATTERY_DS2760) += ds2760_battery.o obj-$(CONFIG_BATTERY_PMU) += pmu_battery.o obj-$(CONFIG_BATTERY_OLPC) += olpc_battery.o +obj-$(CONFIG_BATTERY_LUIGI) += luigi_battery.o diff -urN linux-2.6.26/drivers/power/luigi_battery.c linux-2.6.26-lab126/drivers/power/luigi_battery.c --- linux-2.6.26/drivers/power/luigi_battery.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/power/luigi_battery.c 2010-08-11 00:35:01.000000000 -0400 @@ -0,0 +1,754 @@ +/* + * luigi_battery.c + * Battery driver for MX35 Luigi Board + * + * Copyright (C) Amazon Technologies Inc. All rights reserved. + * Manish Lachwani (lachwani@lab126.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +/* + * I2C registers that need to be read + */ +#define LUIGI_TEMP_LOW 0x06 +#define LUIGI_TEMP_HI 0x07 +#define LUIGI_VOLTAGE_LOW 0x08 +#define LUIGI_VOLTAGE_HI 0x09 +#define LUIGI_BATTERY_ID 0x7E +#define LUIGI_AI_LO 0x14 /* Average Current */ +#define LUIGI_AI_HI 0x15 +#define LUIGI_FLAGS 0x0a +#define LUIGI_BATTERY_RESISTANCE 20 +#define LUIGI_CSOC 0x2c /* Compensated state of charge */ +#define LUIGI_CAC_L 0x10 /* milliamp-hour */ +#define LUIGI_CAC_H 0x11 +#define LUIGI_CYCL_H 0x29 +#define LUIGI_CYCL_L 0x28 +#define LUIGI_LMD_H 0x0F +#define LUIGI_LMD_L 0x0E +#define LUIGI_CYCT_L 0x2A +#define LUIGI_CYCT_H 0x2B + +#define LUIGI_I2C_ADDRESS 0x55 /* Battery I2C address on the bus */ +#define LUIGI_TEMP_LOW_THRESHOLD 37 +#define LUIGI_TEMP_HI_THRESHOLD 113 +#define LUIGI_VOLT_LOW_THRESHOLD 2500 +#define LUIGI_VOLT_HI_THRESHOLD 4350 +#define LUIGI_BATTERY_INTERVAL 20000 /* 20 second duration */ +#define LUIGI_BATTERY_INTERVAL_START 5000 /* 5 second timer on startup */ +#define LUIGI_BATTERY_INTERVAL_ERROR 10000 /* 10 second timer after an error */ + +#define DRIVER_NAME "Luigi Battery" +#define DRIVER_VERSION "1.0" +#define DRIVER_AUTHOR "Manish Lachwani" + +#define GENERAL_ERROR 0x0001 +#define ID_ERROR 0x0002 +#define TEMP_RANGE_ERROR 0x0004 +#define VOLTAGE_ERROR 0x0008 + +#define LUIGI_BATTERY_RETRY_THRESHOLD 100 /* Failed retry case - 100 */ + +#define LUIGI_ERROR_THRESHOLD 4 /* Max of 5 errors at most before sending to userspace */ + +#define LUIGI_BATTERY_RELAXED_THRESH 1800 /* Every 10 hours or 36000 seconds */ +static int luigi_battery_no_stats = 1; + +unsigned int luigi_battery_error_flags = 0; +EXPORT_SYMBOL(luigi_battery_error_flags); + +static int luigi_lmd_counter = LUIGI_BATTERY_RELAXED_THRESH; + +int luigi_battery_id = 0; +int luigi_voltage = 0; +int luigi_temperature = 0; +int luigi_battery_current = 0; +int luigi_battery_capacity = 0; +int luigi_battery_mAH = 0; + +EXPORT_SYMBOL(luigi_battery_id); +EXPORT_SYMBOL(luigi_voltage); +EXPORT_SYMBOL(luigi_temperature); +EXPORT_SYMBOL(luigi_battery_current); +EXPORT_SYMBOL(luigi_battery_capacity); +EXPORT_SYMBOL(luigi_battery_mAH); + +static int luigi_battery_lmd = 0; +static int luigi_battery_cycl = 0; +static int luigi_battery_cyct = 0; + +extern int mxc_i2c_suspended; +static int i2c_error_counter = 0; /* Retry counter */ +static int battery_driver_stopped = 0; /* Battery stop/start flag */ +static int last_suspend_current = 0; /* Last suspend gasguage reading */ + +static int temp_error_counter = 0; +static int volt_error_counter = 0; + +static int battery_curr_diags = 0; +static int battery_suspend_curr_diags = 0; + +/* + * Create the sysfs entries + */ + +static ssize_t +battery_id_show(struct sys_device *dev, char *buf) +{ + return sprintf(buf, "%d\n", luigi_battery_id); +} +static SYSDEV_ATTR(battery_id, 0644, battery_id_show, NULL); + +static ssize_t +battery_current_show(struct sys_device *dev, char *buf) +{ + return sprintf(buf, "%d\n", luigi_battery_current); +} +static SYSDEV_ATTR(battery_current, 0644, battery_current_show, NULL); + +static ssize_t +battery_suspend_current_show(struct sys_device *dev, char *buf) +{ + return sprintf(buf, "%d\n", last_suspend_current); +} +static SYSDEV_ATTR(battery_suspend_current, 0644, battery_suspend_current_show, NULL); + +static ssize_t +battery_voltage_show(struct sys_device *dev, char *buf) +{ + return sprintf(buf, "%d\n", luigi_voltage); +} +static SYSDEV_ATTR(battery_voltage, 0644, battery_voltage_show, NULL); + +static ssize_t +battery_temperature_show(struct sys_device *dev, char *buf) +{ + return sprintf(buf, "%d\n", luigi_temperature); +} +static SYSDEV_ATTR(battery_temperature, 0644, battery_temperature_show, NULL); + +static ssize_t +battery_capacity_show(struct sys_device *dev, char *buf) +{ + return sprintf(buf, "%d%%\n", luigi_battery_capacity); +} +static SYSDEV_ATTR(battery_capacity, 0644, battery_capacity_show, NULL); + +static ssize_t +battery_mAH_show(struct sys_device *dev, char *buf) +{ + return sprintf(buf, "%d\n", luigi_battery_mAH); +} +static SYSDEV_ATTR(battery_mAH, 0644, battery_mAH_show, NULL); + +static ssize_t +battery_error_show(struct sys_device *dev, char *buf) +{ + return sprintf(buf, "%d\n", luigi_battery_error_flags); +} +static SYSDEV_ATTR(battery_error, 0644, battery_error_show, NULL); + +static ssize_t +battery_current_diags_show(struct sys_device *dev, char *buf) +{ + return sprintf(buf, "%d\n", battery_curr_diags); +} +static SYSDEV_ATTR(battery_current_diags, 0644, battery_current_diags_show, NULL); + +static ssize_t +battery_suspend_current_diags_show(struct sys_device *dev, char *buf) +{ + return sprintf(buf, "%d\n", battery_suspend_curr_diags); +} +static SYSDEV_ATTR(battery_suspend_current_diags, 0644, battery_suspend_current_diags_show, NULL); + +/* This is useful for runtime debugging */ + +static ssize_t +battery_show_temp_thresholds(struct sys_device *dev, char *buf) +{ + return sprintf(buf, "Hi-%dF, Lo-%dF\n", LUIGI_TEMP_LOW_THRESHOLD, LUIGI_TEMP_HI_THRESHOLD); +} +static SYSDEV_ATTR(battery_temp_thresholds, 0644, battery_show_temp_thresholds, NULL); + +static ssize_t +battery_show_voltage_thresholds(struct sys_device *dev, char *buf) +{ + return sprintf(buf, "Hi-%dmV, Lo-%dmV\n", LUIGI_VOLT_LOW_THRESHOLD, LUIGI_VOLT_HI_THRESHOLD); +} +static SYSDEV_ATTR(battery_voltage_thresholds, 0644, battery_show_voltage_thresholds, NULL); + +static ssize_t +battery_show_lmd(struct sys_device *dev, char *buf) +{ + return sprintf(buf, "%d\n", luigi_battery_lmd); +} +static SYSDEV_ATTR(battery_lmd, 0644, battery_show_lmd, NULL); + +static ssize_t +battery_show_cycl(struct sys_device *dev, char *buf) +{ + return sprintf(buf, "0x%x\n", luigi_battery_cycl); +} +static SYSDEV_ATTR(battery_cycl, 0644, battery_show_cycl, NULL); + +static ssize_t +battery_show_cyct(struct sys_device *dev, char *buf) +{ + return sprintf(buf, "0x%x\n", luigi_battery_cyct); +} +static SYSDEV_ATTR(battery_cyct, 0644, battery_show_cyct, NULL); + +static ssize_t +battery_show_polling_intervals(struct sys_device *dev, char *buf) +{ + return sprintf(buf, "Regular-%dms, Bootup-%dms\n", + LUIGI_BATTERY_INTERVAL, LUIGI_BATTERY_INTERVAL_START); +} +static SYSDEV_ATTR(battery_polling_intervals, 0644, battery_show_polling_intervals, NULL); + +static ssize_t +battery_show_i2c_address(struct sys_device *dev, char *buf) +{ + return sprintf(buf, "i2c address-0x%x\n", LUIGI_I2C_ADDRESS); +} +static SYSDEV_ATTR(battery_i2c_address, 0644, battery_show_i2c_address, NULL); + +static ssize_t +battery_show_resume_stats(struct sys_device *dev, char *buf) +{ + return sprintf(buf, "%d\n", luigi_battery_no_stats); +} + +static ssize_t +battery_store_resume_stats(struct sys_device *dev, const char *buf, size_t count) +{ + int value; + + if ((sscanf(buf, "%d", &value) > 0) && + ((value == 0) || (value == 1))) { + luigi_battery_no_stats = value; + return strlen(buf); + } + + return -EINVAL; +} +static SYSDEV_ATTR(resume_stats, S_IRUGO|S_IWUSR, battery_show_resume_stats, battery_store_resume_stats); + +static struct sysdev_class luigi_battery_sysclass = { + .name = "luigi_battery", +}; + +static struct sys_device luigi_battery_device = { + .id = 0, + .cls = &luigi_battery_sysclass, +}; + +static int luigi_battery_sysdev_ctrl_init(void) +{ + int err = 0; + + err = sysdev_class_register(&luigi_battery_sysclass); + if (!err) + err = sysdev_register(&luigi_battery_device); + if (!err) { + sysdev_create_file(&luigi_battery_device, &attr_battery_id); + sysdev_create_file(&luigi_battery_device, &attr_battery_current); + sysdev_create_file(&luigi_battery_device, &attr_battery_voltage); + sysdev_create_file(&luigi_battery_device, &attr_battery_temperature); + sysdev_create_file(&luigi_battery_device, &attr_battery_capacity); + sysdev_create_file(&luigi_battery_device, &attr_battery_mAH); + sysdev_create_file(&luigi_battery_device, &attr_battery_voltage_thresholds); + sysdev_create_file(&luigi_battery_device, &attr_battery_polling_intervals); + sysdev_create_file(&luigi_battery_device, &attr_battery_temp_thresholds); + sysdev_create_file(&luigi_battery_device, &attr_battery_i2c_address); + sysdev_create_file(&luigi_battery_device, &attr_battery_error); + sysdev_create_file(&luigi_battery_device, &attr_battery_suspend_current); + sysdev_create_file(&luigi_battery_device, &attr_battery_current_diags); + sysdev_create_file(&luigi_battery_device, &attr_battery_suspend_current_diags); + sysdev_create_file(&luigi_battery_device, &attr_battery_cycl); + sysdev_create_file(&luigi_battery_device, &attr_battery_lmd); + sysdev_create_file(&luigi_battery_device, &attr_battery_cyct); + sysdev_create_file(&luigi_battery_device, &attr_resume_stats); + } + + return err; +} + +static void luigi_battery_sysdev_ctrl_exit(void) +{ + sysdev_remove_file(&luigi_battery_device, &attr_battery_id); + sysdev_remove_file(&luigi_battery_device, &attr_battery_current); + sysdev_remove_file(&luigi_battery_device, &attr_battery_voltage); + sysdev_remove_file(&luigi_battery_device, &attr_battery_temperature); + sysdev_remove_file(&luigi_battery_device, &attr_battery_capacity); + sysdev_remove_file(&luigi_battery_device, &attr_battery_mAH); + sysdev_remove_file(&luigi_battery_device, &attr_battery_voltage_thresholds); + sysdev_remove_file(&luigi_battery_device, &attr_battery_polling_intervals); + sysdev_remove_file(&luigi_battery_device, &attr_battery_temp_thresholds); + sysdev_remove_file(&luigi_battery_device, &attr_battery_i2c_address); + sysdev_remove_file(&luigi_battery_device, &attr_battery_error); + sysdev_remove_file(&luigi_battery_device, &attr_battery_suspend_current); + sysdev_remove_file(&luigi_battery_device, &attr_battery_current_diags); + sysdev_remove_file(&luigi_battery_device, &attr_battery_suspend_current_diags); + sysdev_remove_file(&luigi_battery_device, &attr_battery_cycl); + sysdev_remove_file(&luigi_battery_device, &attr_battery_lmd); + sysdev_remove_file(&luigi_battery_device, &attr_battery_cyct); + sysdev_remove_file(&luigi_battery_device, &attr_resume_stats); + + sysdev_unregister(&luigi_battery_device); + sysdev_class_unregister(&luigi_battery_sysclass); +} + +static int luigi_battery_detect(struct i2c_adapter *adapter, int address, int type); +static int luigi_battery_attach_adapter(struct i2c_adapter *adapter); +static int luigi_battery_detach_client(struct i2c_client *client); +static struct i2c_client luigi_battery_i2c_client; + +int luigi_battery_present = 0; +EXPORT_SYMBOL(luigi_battery_present); + +static int luigi_i2c_read(unsigned char reg_num, unsigned char *value) +{ + s32 error; + + error = i2c_smbus_read_byte_data(&luigi_battery_i2c_client, reg_num); + if (error < 0) { + printk(KERN_INFO "luigi_battery: i2c read retry\n"); + return -EIO; + } + + *value = (unsigned char) (error & 0xFF); + return 0; +} + +static int luigi_battery_read_voltage(int *voltage) +{ + unsigned char hi, lo; + int volts; + int err1 = 0, err2 = 0; + int error = 0; + + err1 = luigi_i2c_read(LUIGI_VOLTAGE_LOW, &lo); + err2 = luigi_i2c_read(LUIGI_VOLTAGE_HI, &hi); + + error = err1 | err2; + + if (!error) { + volts = (hi << 8) | lo; + *voltage = volts; + } + + return error; +} + +static int luigi_battery_read_current(int *curr) +{ + unsigned char hi, lo, flags; + int c; + int err1 = 0, err2 = 0, err3 = 0; + int sign = 1; + int error = 0; + + err1 = luigi_i2c_read(LUIGI_AI_LO, &lo); + err2 = luigi_i2c_read(LUIGI_AI_HI, &hi); + err3 = luigi_i2c_read(LUIGI_FLAGS, &flags); + + error = err1 | err2 | err3; + + if (!error) { + if (flags & 0x80) + sign = 1; + else + sign = -1; + + battery_curr_diags = sign * (((hi << 8) | lo) * 357); + + if (!battery_suspend_curr_diags) + battery_suspend_curr_diags = battery_curr_diags; + + c = sign * ((((hi << 8) | lo) * 357) / (100 * LUIGI_BATTERY_RESISTANCE)); + *curr = c; + } + + return error; +} + +static int luigi_battery_read_capacity(int *capacity) +{ + unsigned char tmp; + int err = 0; + + err = luigi_i2c_read(LUIGI_CSOC, &tmp); + if (!err) + *capacity = tmp; + + return err; +} + +static int luigi_battery_read_mAH(int *mAH) +{ + unsigned char hi, lo; + int err1 = 0, err2 = 0; + int error = 0; + + err1 = luigi_i2c_read(LUIGI_CAC_L, &lo); + err2 = luigi_i2c_read(LUIGI_CAC_H, &hi); + + error = err1 | err2; + + if (!error) + *mAH = ((((hi << 8) | lo) * 357) / (100 * LUIGI_BATTERY_RESISTANCE)); + + return error; +} + +/* Read Last Measured Discharge and Learning count */ +static void luigi_battery_read_lmd_cyc(int *lmd, int *cycl, int *cyct) +{ + unsigned char hi, lo; + int err1 = 0, err2 = 0; + int error = 0; + + err1 = luigi_i2c_read(LUIGI_CYCL_L, &lo); + err2 = luigi_i2c_read(LUIGI_CYCL_H, &hi); + + error = err1 | err2; + + if (!error) + *cycl = (hi << 8) | lo; + + /* Clear out hi, lo for next reading */ + hi = lo = 0; + + err1 = luigi_i2c_read(LUIGI_LMD_L, &lo); + err2 = luigi_i2c_read(LUIGI_LMD_H, &hi); + + error = err1 | err2; + + if (!error) + *lmd = ((((hi << 8) | lo) * 357) / (100 * LUIGI_BATTERY_RESISTANCE)); + + /* Clear out hi, lo for next reading */ + hi = lo = 0; + + err1 = luigi_i2c_read(LUIGI_CYCT_L, &lo); + err2 = luigi_i2c_read(LUIGI_CYCT_H, &hi); + + error = err1 | err2; + + if (!error) + *cyct = (hi << 8) | lo; +} + +static int luigi_battery_read_temperature(int *temperature) +{ + unsigned char temp_hi, temp_lo; + int err1 = 0, err2 = 0; + int celsius, fahrenheit; + int error = 0; + + err1 = luigi_i2c_read(LUIGI_TEMP_LOW, &temp_lo); + err2 = luigi_i2c_read(LUIGI_TEMP_HI, &temp_hi); + + error = err1 | err2; + + if (!error) { + celsius = ((((temp_hi << 8) | temp_lo) + 2) / 4) - 273; + fahrenheit = ((celsius * 9) / 5) + 32; + *temperature = fahrenheit; + } + + return error; +} + +static int luigi_battery_read_id(int *id) +{ + int error = 0; + unsigned char value = 0xFF; + + error = luigi_i2c_read(LUIGI_BATTERY_ID, &value); + + if (!error) { + *id = value; + } + + return error; +} + +static void battery_handle_work(struct work_struct *work); +static DECLARE_DELAYED_WORK(battery_work, battery_handle_work); + +/* Main battery timer task */ +static void battery_handle_work(struct work_struct *work) +{ + int err = 0; + int batt_err_flag = 0; + + /* Is the battery driver stopped? */ + if (battery_driver_stopped) + return; + + /* Is i2c bus suspended? */ + if (mxc_i2c_suspended) + goto out_done; + + err = luigi_battery_read_id(&luigi_battery_id); + if (err) { + batt_err_flag |= GENERAL_ERROR; + goto out; + } + else + i2c_error_counter = 0; + + err = luigi_battery_read_temperature(&luigi_temperature); + if (err) { + batt_err_flag |= GENERAL_ERROR; + goto out; + } + else + i2c_error_counter = 0; + + /* + * Check for the temperature range violation + */ + if ( (luigi_temperature <= LUIGI_TEMP_LOW_THRESHOLD) || + (luigi_temperature >= LUIGI_TEMP_HI_THRESHOLD) ) { + temp_error_counter++; + } + else { + temp_error_counter = 0; + luigi_battery_error_flags &= ~TEMP_RANGE_ERROR; + } + + if (temp_error_counter > LUIGI_ERROR_THRESHOLD) { + luigi_battery_error_flags |= TEMP_RANGE_ERROR; + printk(KERN_ERR "battery driver temp - %d\n", luigi_temperature); + temp_error_counter = 0; + } + + err = luigi_battery_read_voltage(&luigi_voltage); + if (err) { + batt_err_flag |= GENERAL_ERROR; + goto out; + } + else + i2c_error_counter = 0; + + /* + * Check for the battery voltage range violation + */ + if ( (luigi_voltage <= LUIGI_VOLT_LOW_THRESHOLD) || + (luigi_voltage >= LUIGI_VOLT_HI_THRESHOLD) ) { + volt_error_counter++; + } + else { + volt_error_counter = 0; + luigi_battery_error_flags &= ~VOLTAGE_ERROR; + } + + if (volt_error_counter > LUIGI_ERROR_THRESHOLD) { + printk(KERN_ERR "battery driver voltage - %dmV\n", luigi_voltage); + luigi_battery_error_flags |= VOLTAGE_ERROR; + volt_error_counter = 0; + } + + /* + * Check for the battery current + */ + err = luigi_battery_read_current(&luigi_battery_current); + if (err) { + batt_err_flag |= GENERAL_ERROR; + goto out; + } + else + i2c_error_counter = 0; + + /* + * Read the gasguage capacity + */ + err = luigi_battery_read_capacity(&luigi_battery_capacity); + if (err) { + batt_err_flag |= GENERAL_ERROR; + goto out; + } + else + i2c_error_counter = 0; + + /* + * Read the battery mAH + */ + err = luigi_battery_read_mAH(&luigi_battery_mAH); + if (err) { + batt_err_flag |= GENERAL_ERROR; + goto out; + } + else + i2c_error_counter = 0; + + /* Take these readings every 10 hours */ + if (luigi_lmd_counter == LUIGI_BATTERY_RELAXED_THRESH) { + luigi_lmd_counter = 0; + luigi_battery_read_lmd_cyc(&luigi_battery_lmd, &luigi_battery_cycl, &luigi_battery_cyct); + } + else { + luigi_lmd_counter++; + } + +out: + if (batt_err_flag) { + i2c_error_counter++; + if (i2c_error_counter == LUIGI_BATTERY_RETRY_THRESHOLD) { + luigi_battery_error_flags |= GENERAL_ERROR; + printk(KERN_ERR "Luigi battery: i2c read error, retry exceeded\n"); + i2c_error_counter = 0; + } + } + else { + luigi_battery_error_flags &= ~GENERAL_ERROR; + i2c_error_counter = 0; + } + + pr_debug("temp: %d, volt: %d, current: %d, capacity: %d%%, mAH: %d\n", + luigi_temperature, luigi_voltage, luigi_battery_current, + luigi_battery_capacity, luigi_battery_mAH); +out_done: + if (batt_err_flag & GENERAL_ERROR) + schedule_delayed_work(&battery_work, msecs_to_jiffies(LUIGI_BATTERY_INTERVAL_ERROR)); + else + schedule_delayed_work(&battery_work, msecs_to_jiffies(LUIGI_BATTERY_INTERVAL)); + return; +} + +static struct i2c_driver luigi_i2c_driver = { + .driver = { + .name = DRIVER_NAME, + }, + .attach_adapter = luigi_battery_attach_adapter, + .detach_client = luigi_battery_detach_client, +}; + +static struct i2c_client luigi_battery_i2c_client = { + .name = DRIVER_NAME, + .addr = LUIGI_I2C_ADDRESS, + .driver = &luigi_i2c_driver, +}; + +static unsigned short normal_i2c[] = { LUIGI_I2C_ADDRESS, I2C_CLIENT_END }; +I2C_CLIENT_INSMOD; + +int luigi_battery_suspend(void) +{ + if (luigi_battery_present) { + battery_driver_stopped = 1; + cancel_rearming_delayed_work(&battery_work); + i2c_error_counter = 0; + } + + return 0; +} +EXPORT_SYMBOL(luigi_battery_suspend); + +int luigi_battery_resume(void) +{ + battery_driver_stopped = 0; + + return 0; +} +EXPORT_SYMBOL(luigi_battery_resume); + +void luigi_battery_resume_stats(void) +{ + int batt_current = 0; + int batt_voltage = 0; + int batt_capacity = 0; + + if (luigi_battery_present && !mxc_i2c_suspended && !battery_driver_stopped && !luigi_battery_no_stats) { + if (!luigi_battery_read_voltage(&batt_voltage)) { + luigi_voltage = batt_voltage; + } + + if (!luigi_battery_read_capacity(&batt_capacity)) { + luigi_battery_capacity = batt_capacity; + } + + battery_suspend_curr_diags = 0; + + /* + * Take a reading now and dump into logs. Usually accurate suspend current + * if taken with a few seconds of resume. + */ + if (!luigi_battery_read_current(&batt_current)) { + printk(KERN_INFO "battery: I def:sus:device_suspend_current=%dmA:\n", batt_current); + last_suspend_current = batt_current; + } + else { + printk(KERN_ERR "Battery suspend current could not be obtained\n"); + batt_current = 0; + } + } + schedule_delayed_work(&battery_work, msecs_to_jiffies(LUIGI_BATTERY_INTERVAL)); +} +EXPORT_SYMBOL(luigi_battery_resume_stats); + +static int luigi_battery_detect(struct i2c_adapter *adapter, int address, int type) +{ + luigi_battery_i2c_client.adapter = adapter; + luigi_battery_present = 1; + + if (luigi_battery_sysdev_ctrl_init() < 0) + printk(KERN_ERR "luigi battery: could not create sysfs entries\n"); + + battery_handle_work((struct work_struct *)0); + return 0; +} + +static int luigi_battery_attach_adapter(struct i2c_adapter *adapter) +{ + return i2c_probe(adapter, &addr_data, luigi_battery_detect); +} + +static int luigi_battery_detach_client(struct i2c_client *client) +{ + return i2c_detach_client(client); +} + +static int __init luigi_battery_init(void) +{ + int ret = 0; + + ret = i2c_add_driver(&luigi_i2c_driver); + + if (ret) { + printk(KERN_ERR "Luigi battery: Could not add driver\n"); + return ret; + } + return 0; +} + + +static void __exit luigi_battery_exit(void) +{ + if (luigi_battery_present) { + battery_driver_stopped = 1; + cancel_rearming_delayed_work(&battery_work); + luigi_battery_sysdev_ctrl_exit(); + } + i2c_del_driver(&luigi_i2c_driver); +} + +module_init(luigi_battery_init); +module_exit(luigi_battery_exit); + +MODULE_DESCRIPTION("MX35 Luigi Battery Driver"); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/regulator/Kconfig linux-2.6.26-lab126/drivers/regulator/Kconfig --- linux-2.6.26/drivers/regulator/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/regulator/Kconfig 2010-08-10 04:16:18.000000000 -0400 @@ -0,0 +1,77 @@ +menu "Voltage and Current regulators" + +config REGULATOR_API + bool + +config REGULATOR + tristate "Voltage and Current Regulator Support" + depends on EXPERIMENTAL + select REGULATOR_API + default n + help + Generic Voltage and Current Regulator support. + +config REGULATOR_DEBUG + bool "Regulator debug support" + depends on REGULATOR + help + Say yes here to enable debugging support. + +config REGULATOR_MC13783 + tristate "MC13783 Regulator Support" + depends on REGULATOR + depends on MXC_PMIC_MC13783 + default y + +config REGULATOR_MC13892 + tristate "MC13892 Regulator Support" + depends on REGULATOR + depends on MXC_PMIC_MC13892 + default y + +config REGULATOR_MC34704 + tristate "MC34704 Regulator Support" + depends on REGULATOR + depends on MXC_PMIC_MC34704 + default y + +config REGULATOR_MAX8660 + tristate "MAX8660 Regulator Support" + depends on REGULATOR + depends on MXC_PMIC_MC9SDZ60 + default y + +config REGULATOR_MC9SDZ60 + tristate "mc9sdz60 Regulator Support" + depends on REGULATOR + depends on MXC_PMIC_MC9SDZ60 + default y + +config REGULATOR_WM8350 + tristate "WM8350 Regulator Support" + depends on REGULATOR + +menu "WM8350 Config Mode" +depends on REGULATOR_WM8350 + +choice + prompt "WM8350 Configuration Mode" + default PMIC_WM8350_MODE_0 + +config PMIC_WM8350_MODE_0 + bool "Mode 0" + +config PMIC_WM8350_MODE_1 + bool "Mode 1" + +config PMIC_WM8350_MODE_2 + bool "Mode 2" + +config PMIC_WM8350_MODE_3 + bool "Mode 3" + +endchoice + +endmenu + +endmenu diff -urN linux-2.6.26/drivers/regulator/Makefile linux-2.6.26-lab126/drivers/regulator/Makefile --- linux-2.6.26/drivers/regulator/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/regulator/Makefile 2010-08-10 04:16:18.000000000 -0400 @@ -0,0 +1,16 @@ +# +# Makefile for regulator drivers. +# + +obj-$(CONFIG_REGULATOR) += reg-core.o + +ifeq ($(CONFIG_REGULATOR_DEBUG),y) + EXTRA_CFLAGS += -DDEBUG +endif + +obj-$(CONFIG_REGULATOR_MC13783) += mc13783/ +obj-$(CONFIG_REGULATOR_WM8350) += wm8350/ +obj-$(CONFIG_REGULATOR_MAX8660) += max8660/ +obj-$(CONFIG_REGULATOR_MC13892) += mc13892/ +obj-$(CONFIG_REGULATOR_MC34704) += mc34704/ +obj-$(CONFIG_REGULATOR_MC9SDZ60) += mc9sdz60/ diff -urN linux-2.6.26/drivers/regulator/max8660/Makefile linux-2.6.26-lab126/drivers/regulator/max8660/Makefile --- linux-2.6.26/drivers/regulator/max8660/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/regulator/max8660/Makefile 2010-08-10 04:16:18.000000000 -0400 @@ -0,0 +1 @@ +obj-$(CONFIG_REGULATOR_MAX8660) += reg-max8660.o diff -urN linux-2.6.26/drivers/regulator/max8660/reg-max8660.c linux-2.6.26-lab126/drivers/regulator/max8660/reg-max8660.c --- linux-2.6.26/drivers/regulator/max8660/reg-max8660.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/regulator/max8660/reg-max8660.c 2010-08-10 04:16:18.000000000 -0400 @@ -0,0 +1,899 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*! + * brief PMIC regulators. + */ + +enum { + MCU_SW1, + MCU_SW2, + MCU_SW3, + MCU_SW4, + MCU_LDO5, + MCU_LDO6, + MCU_LDO7, + MCU_LCD, + MCU_WIFI, + MCU_HDD, + MCU_GPS, + MCU_CMOS, + MCU_PLL +} MAX8660_regulator; + +/*! + * @enum t_pmic_regulator_voltage_mcu_sw34 + * @brief MCU PMIC Switch mode regulator SW34 output voltages. + */ +enum { + MCU_SW34_0_725V = 0, + MCU_SW34_0_75V, + MCU_SW34_0_775V, + MCU_SW34_0_8V, + MCU_SW34_0_825V, + MCU_SW34_0_85V, + MCU_SW34_0_875V, + MCU_SW34_0_9V, + MCU_SW34_0_925V, + MCU_SW34_0_95V, + MCU_SW34_0_975V, + MCU_SW34_1_0V, + MCU_SW34_1_025V, + MCU_SW34_1_05V, + MCU_SW34_1_075V, + MCU_SW34_1_1V, + MCU_SW34_1_125V, + MCU_SW34_1_15V, + MCU_SW34_1_175V, + MCU_SW34_1_2V, + MCU_SW34_1_225V, + MCU_SW34_1_25V, + MCU_SW34_1_275V, + MCU_SW34_1_3V, + MCU_SW34_1_325V, + MCU_SW34_1_35V, + MCU_SW34_1_375V, + MCU_SW34_1_4V, + MCU_SW34_1_425V, + MCU_SW34_1_45V, + MCU_SW34_1_475V, + MCU_SW34_1_5V, + MCU_SW34_1_525V, + MCU_SW34_1_55V, + MCU_SW34_1_575V, + MCU_SW34_1_6V, + MCU_SW34_1_625V, + MCU_SW34_1_65V, + MCU_SW34_1_675V, + MCU_SW34_1_7V, + MCU_SW34_1_725V, + MCU_SW34_1_75V, + MCU_SW34_1_775V, + MCU_SW34_1_8V +} t_pmic_regulator_voltage_mcu_sw34; + +enum { + MCU_LDO5_1_7V, + MCU_LDO5_1_725V, + MCU_LDO5_1_75V, + MCU_LDO5_1_775V, + MCU_LDO5_1_8V, + MCU_LDO5_1_825V, + MCU_LDO5_1_85V, + MCU_LDO5_1_875V, + MCU_LDO5_1_9V, + MCU_LDO5_1_925V, + MCU_LDO5_1_95V, + MCU_LDO5_1_975V, + MCU_LDO5_2_0V +} t_pmic_regulator_voltage_mcu_ldo5; + +enum { + MCU_LDO67_1_8V, + MCU_LDO67_1_9V, + MCU_LDO67_2_0V, + MCU_LDO67_2_1V, + MCU_LDO67_2_2V, + MCU_LDO67_2_3V, + MCU_LDO67_2_4V, + MCU_LDO67_2_5V, + MCU_LDO67_2_6V, + MCU_LDO67_2_7V, + MCU_LDO67_2_8V, + MCU_LDO67_2_9V, + MCU_LDO67_3_0V, + MCU_LDO67_3_1V, + MCU_LDO67_3_2V, + MCU_LDO67_3_3V +} t_pmic_regulator_voltage_mcu_ldo67; + +#define NUM_MAX8660_REGULATORS 7 +#define NUM_MAX8660_CHILDREN_REGULATORS 6 + +#define SET_BIT_IN_BYTE(byte, pos) (byte |= (0x01 << pos)) +#define CLEAR_BIT_IN_BYTE(byte, pos) (byte &= ~(0x01 << pos)) + +static int max8660_regulator_on(int regulator) +{ + u8 reg_mask = 0; + int reg_num; + + if (regulator > MCU_LDO7 || regulator < MCU_SW1) + return -1; + + switch (regulator) { + case MCU_SW1: + SET_BIT_IN_BYTE(reg_mask, 0); + reg_num = REG_MCU_POWER_CTL; + break; + case MCU_SW2: + SET_BIT_IN_BYTE(reg_mask, 1); + reg_num = REG_MCU_POWER_CTL; + break; + case MCU_SW3: + SET_BIT_IN_BYTE(reg_mask, 0); + reg_num = REG_MAX8660_OUTPUT_ENABLE_1; + break; + case MCU_SW4: + SET_BIT_IN_BYTE(reg_mask, 2); + reg_num = REG_MAX8660_OUTPUT_ENABLE_1; + break; + case MCU_LDO5: + SET_BIT_IN_BYTE(reg_mask, 3); + reg_num = REG_MCU_POWER_CTL; + break; + case MCU_LDO6: + SET_BIT_IN_BYTE(reg_mask, 1); + reg_num = REG_MAX8660_OUTPUT_ENABLE_2; + break; + case MCU_LDO7: + SET_BIT_IN_BYTE(reg_mask, 2); + reg_num = REG_MAX8660_OUTPUT_ENABLE_2; + break; + + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(mcu_pmic_write_reg(reg_num, reg_mask, reg_mask)); + + return 0; +} + +static int max8660_regulator_off(int regulator) +{ + u8 reg_mask = 0; + unsigned int reg_read = 0; + int reg_num; + + if (regulator > MCU_LDO7 || regulator < MCU_SW1) + return PMIC_NOT_SUPPORTED; + + switch (regulator) { + case MCU_SW1: + SET_BIT_IN_BYTE(reg_mask, 0); + reg_num = REG_MCU_POWER_CTL; + break; + case MCU_SW2: + SET_BIT_IN_BYTE(reg_mask, 1); + reg_num = REG_MCU_POWER_CTL; + break; + case MCU_SW3: + SET_BIT_IN_BYTE(reg_mask, 0); + reg_num = REG_MAX8660_OUTPUT_ENABLE_1; + break; + case MCU_SW4: + SET_BIT_IN_BYTE(reg_mask, 2); + reg_num = REG_MAX8660_OUTPUT_ENABLE_1; + break; + case MCU_LDO5: + SET_BIT_IN_BYTE(reg_mask, 3); + reg_num = REG_MCU_POWER_CTL; + break; + case MCU_LDO6: + SET_BIT_IN_BYTE(reg_mask, 1); + reg_num = REG_MAX8660_OUTPUT_ENABLE_2; + break; + case MCU_LDO7: + SET_BIT_IN_BYTE(reg_mask, 2); + reg_num = REG_MAX8660_OUTPUT_ENABLE_2; + break; + + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(mcu_pmic_write_reg(reg_num, 0, reg_mask)); + + /* handle sw3,4 */ + switch (regulator) { + case MCU_SW3: + reg_mask = 0; + SET_BIT_IN_BYTE(reg_mask, 2); + CHECK_ERROR(mcu_pmic_read_reg + (REG_MCU_POWER_CTL, ®_read, reg_mask)); + + /* check if hw pin enable sw34 */ + if (0 != reg_read) { + + /* keep sw4 on */ + reg_mask = 0; + SET_BIT_IN_BYTE(reg_mask, 2); + CHECK_ERROR(mcu_pmic_write_reg + (REG_MAX8660_OUTPUT_ENABLE_1, reg_mask, + reg_mask)); + + /* disable hw pin to actually turn off sw3 */ + reg_mask = 0; + SET_BIT_IN_BYTE(reg_mask, 2); + CHECK_ERROR(mcu_pmic_write_reg + (REG_MCU_POWER_CTL, 0, reg_mask)); + } + break; + case MCU_SW4: + reg_mask = 0; + SET_BIT_IN_BYTE(reg_mask, 2); + CHECK_ERROR(mcu_pmic_read_reg + (REG_MCU_POWER_CTL, ®_read, reg_mask)); + + /* check if hw pin enable sw34 */ + if (0 != reg_read) { + + /* keep sw3 on */ + reg_mask = 0; + SET_BIT_IN_BYTE(reg_mask, 0); + CHECK_ERROR(mcu_pmic_write_reg + (REG_MAX8660_OUTPUT_ENABLE_1, reg_mask, + reg_mask)); + + /* disable hw pin to actually turn off sw4 */ + reg_mask = 0; + SET_BIT_IN_BYTE(reg_mask, 2); + CHECK_ERROR(mcu_pmic_write_reg + (REG_MCU_POWER_CTL, 0, reg_mask)); + } + break; + default: + break; + } + return 0; +} + +static int max8660_sw1_enable(struct regulator *reg) +{ + return max8660_regulator_on(MCU_SW1); +} + +static int max8660_sw1_disable(struct regulator *reg) +{ + return max8660_regulator_off(MCU_SW1); +} + +static int max8660_sw2_enable(struct regulator *reg) +{ + return max8660_regulator_on(MCU_SW2); +} + +static int max8660_sw2_disable(struct regulator *reg) +{ + return max8660_regulator_off(MCU_SW2); +} + +static int max8660_sw3_enable(struct regulator *reg) +{ + return max8660_regulator_on(MCU_SW3); +} + +static int max8660_sw3_disable(struct regulator *reg) +{ + return max8660_regulator_off(MCU_SW3); +} + +static int max8660_sw3_set_voltage(struct regulator *reg, int uV) +{ + u8 reg_mask = 0; + int mV = uV / 1000; + int volt; + + if (mV < 725 || mV > 1800) + return -1; + + /* convert to reg value */ + volt = (mV - 725) / 25; + + /* hold on */ + SET_BIT_IN_BYTE(reg_mask, 0); + CHECK_ERROR(mcu_pmic_write_reg + (REG_MAX8660_VOLT_CHANGE_CONTROL_1, 0, reg_mask)); + + /* set volt */ + CHECK_ERROR( + mcu_pmic_write_reg(REG_MAX8660_V3_TARGET_VOLT_1, volt, 0xff)); + + /* start ramp */ + SET_BIT_IN_BYTE(reg_mask, 0); + CHECK_ERROR(mcu_pmic_write_reg + (REG_MAX8660_VOLT_CHANGE_CONTROL_1, reg_mask, reg_mask)); + + return 0; +} + +static int max8660_sw3_get_voltage(struct regulator *reg) +{ + int uV; + unsigned int reg_val = 0; + + CHECK_ERROR(mcu_pmic_read_reg + (REG_MAX8660_V3_TARGET_VOLT_1, ®_val, 0xff)); + + uV = 1000 * (reg_val * 25 + 725); + + return uV; +} + +static int max8660_sw4_enable(struct regulator *reg) +{ + return max8660_regulator_on(MCU_SW4); +} + +static int max8660_sw4_disable(struct regulator *reg) +{ + return max8660_regulator_off(MCU_SW4); +} + +static int max8660_sw4_set_voltage(struct regulator *reg, int uV) +{ + u8 reg_mask = 0; + int mV = uV / 1000; + int volt; + + if (mV < 725 || mV > 1800) + return -1; + + /* convert to reg value */ + volt = (mV - 725) / 25; + + /* hold on */ + SET_BIT_IN_BYTE(reg_mask, 4); + CHECK_ERROR(mcu_pmic_write_reg + (REG_MAX8660_VOLT_CHANGE_CONTROL_1, 0, reg_mask)); + + /* set volt */ + CHECK_ERROR( + mcu_pmic_write_reg(REG_MAX8660_V4_TARGET_VOLT_1, volt, 0xff)); + + /* start ramp */ + SET_BIT_IN_BYTE(reg_mask, 4); + CHECK_ERROR(mcu_pmic_write_reg + (REG_MAX8660_VOLT_CHANGE_CONTROL_1, reg_mask, reg_mask)); + + return 0; +} + +static int max8660_sw4_get_voltage(struct regulator *reg) +{ + int uV; + unsigned int reg_val = 0; + + CHECK_ERROR(mcu_pmic_read_reg + (REG_MAX8660_V4_TARGET_VOLT_1, ®_val, 0xff)); + + uV = 1000 * (reg_val * 25 + 725); + + return uV; +} + +static int max8660_ldo5_enable(struct regulator *reg) +{ + return max8660_regulator_on(MCU_LDO5); +} + +static int max8660_ldo5_disable(struct regulator *reg) +{ + return max8660_regulator_off(MCU_LDO5); +} + +static int max8660_ldo5_set_voltage(struct regulator *reg, int uV) +{ + u8 reg_mask = 0; + int mV = uV / 1000; + int volt; + + if (mV < 1700 || mV > 2000) + return -1; + + /* convert to reg value */ + volt = (mV - 1700) / 25; + + /* hold on */ + SET_BIT_IN_BYTE(reg_mask, 6); + CHECK_ERROR(mcu_pmic_write_reg + (REG_MAX8660_VOLT_CHANGE_CONTROL_1, 0, reg_mask)); + + /* set volt */ + CHECK_ERROR( + mcu_pmic_write_reg(REG_MAX8660_V5_TARGET_VOLT_1, volt, 0xff)); + + /* start ramp */ + SET_BIT_IN_BYTE(reg_mask, 6); + CHECK_ERROR(mcu_pmic_write_reg + (REG_MAX8660_VOLT_CHANGE_CONTROL_1, reg_mask, reg_mask)); + + return 0; +} + +static int max8660_ldo5_get_voltage(struct regulator *reg) +{ + int uV; + unsigned int reg_val = 0; + + CHECK_ERROR(mcu_pmic_read_reg + (REG_MAX8660_V5_TARGET_VOLT_1, ®_val, 0xff)); + + uV = 1000 * (reg_val * 25 + 1700); + + return uV; + +} + +static int max8660_ldo6_enable(struct regulator *reg) +{ + return max8660_regulator_on(MCU_LDO6); +} + +static int max8660_ldo6_disable(struct regulator *reg) +{ + return max8660_regulator_off(MCU_LDO6); +} + +static int max8660_ldo6_set_voltage(struct regulator *reg, int uV) +{ + int mV = uV / 1000; + int volt; + + if (mV < 1800 || mV > 3300) + return -1; + + /* convert to reg value */ + volt = (mV - 1800) / 100; + + /* set volt */ + CHECK_ERROR( + mcu_pmic_write_reg(REG_MAX8660_V6V7_TARGET_VOLT, volt, 0x0f)); + + return 0; +} + +static int max8660_ldo6_get_voltage(struct regulator *reg) +{ + int uV; + unsigned int reg_val = 0; + + CHECK_ERROR(mcu_pmic_read_reg + (REG_MAX8660_V6V7_TARGET_VOLT, ®_val, 0x0f)); + + uV = 1000 * (reg_val * 100 + 1800); + + return uV; +} + +static int max8660_ldo7_enable(struct regulator *reg) +{ + return max8660_regulator_on(MCU_LDO7); +} + +static int max8660_ldo7_disable(struct regulator *reg) +{ + return max8660_regulator_off(MCU_LDO7); +} + +static int max8660_ldo7_set_voltage(struct regulator *reg, int uV) +{ + int mV = uV / 1000; + int volt; + + if (mV < 1800 || mV > 3300) + return -1; + + /* convert to reg value */ + volt = (mV - 1800) / 100; + + /* set volt */ + CHECK_ERROR(mcu_pmic_write_reg + (REG_MAX8660_V6V7_TARGET_VOLT, (volt << 4), 0xf0)); + + return 0; +} + +static int max8660_ldo7_get_voltage(struct regulator *reg) +{ + int uV; + unsigned int reg_val = 0; + + CHECK_ERROR(mcu_pmic_read_reg + (REG_MAX8660_V6V7_TARGET_VOLT, ®_val, 0x0f)); + reg_val = (reg_val >> 4) & 0xf; + + uV = 1000 * (reg_val * 100 + 1800); + + return uV; +} + +static struct regulator_ops max8660_sw1_ops = { + .enable = max8660_sw1_enable, + .disable = max8660_sw1_disable, +}; + +static struct regulator_ops max8660_sw2_ops = { + .enable = max8660_sw2_enable, + .disable = max8660_sw2_disable, +}; + +static struct regulator_ops max8660_sw3_ops = { + .set_voltage = max8660_sw3_set_voltage, + .get_voltage = max8660_sw3_get_voltage, + .enable = max8660_sw3_enable, + .disable = max8660_sw3_disable, +}; + +static struct regulator_ops max8660_sw4_ops = { + .set_voltage = max8660_sw4_set_voltage, + .get_voltage = max8660_sw4_get_voltage, + .enable = max8660_sw4_enable, + .disable = max8660_sw4_disable, +}; + +static struct regulator_ops max8660_ldo5_ops = { + .set_voltage = max8660_ldo5_set_voltage, + .get_voltage = max8660_ldo5_get_voltage, + .enable = max8660_ldo5_enable, + .disable = max8660_ldo5_disable, +}; + +static struct regulator_ops max8660_ldo6_ops = { + .set_voltage = max8660_ldo6_set_voltage, + .get_voltage = max8660_ldo6_get_voltage, + .enable = max8660_ldo6_enable, + .disable = max8660_ldo6_disable, +}; + +static struct regulator_ops max8660_ldo7_ops = { + .set_voltage = max8660_ldo7_set_voltage, + .get_voltage = max8660_ldo7_get_voltage, + .enable = max8660_ldo7_enable, + .disable = max8660_ldo7_disable, +}; + +struct regulation_constraints max8660_sw3_regulation_constraints = { + .min_uV = mV_to_uV(725), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +struct regulation_constraints max8660_sw4_regulation_constraints = { + .min_uV = mV_to_uV(725), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +struct regulation_constraints max8660_ldo5_regulation_constraints = { + .min_uV = mV_to_uV(1700), + .max_uV = mV_to_uV(2000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +struct regulation_constraints max8660_ldo6_regulation_constraints = { + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(3300), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +struct regulation_constraints max8660_ldo7_regulation_constraints = { + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(3300), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +struct max8660_regulator { + struct regulator regulator; +}; + +static struct max8660_regulator reg_max8660[NUM_MAX8660_REGULATORS] = { + { + .regulator = { + .name = "SW1", + .id = MCU_SW1, + .ops = &max8660_sw1_ops, + .use_count = 1, + }, + }, + { + .regulator = { + .name = "SW2", + .id = MCU_SW2, + .ops = &max8660_sw2_ops, + .use_count = 1, + }, + }, + { + .regulator = { + .name = "SW3", + .id = MCU_SW3, + .ops = &max8660_sw3_ops, + .constraints = &max8660_sw3_regulation_constraints, + .use_count = 1, + }, + }, + { + .regulator = { + .name = "SW4", + .id = MCU_SW4, + .ops = &max8660_sw4_ops, + .constraints = &max8660_sw4_regulation_constraints, + .use_count = 1, + }, + }, + { + .regulator = { + .name = "LDO5", + .id = MCU_LDO5, + .ops = &max8660_ldo5_ops, + .constraints = &max8660_ldo5_regulation_constraints, + }, + }, + { + .regulator = { + .name = "LDO6", + .id = MCU_LDO6, + .ops = &max8660_ldo6_ops, + .constraints = &max8660_ldo6_regulation_constraints, + }, + }, + { + .regulator = { + .name = "LDO7", + .id = MCU_LDO7, + .ops = &max8660_ldo7_ops, + .constraints = &max8660_ldo7_regulation_constraints, + }, + }, +}; + +/* children regulator ops*/ + +/* lcd */ +static int max8660_lcd_enable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 6, 1); +} + +static int max8660_lcd_disable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 6, 0); +} + +static struct regulator_ops max8660_lcd_ops = { + .enable = max8660_lcd_enable, + .disable = max8660_lcd_disable, +}; + +/* wifi */ +static int max8660_wifi_enable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 5, 1); +} + +static int max8660_wifi_disable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 5, 0); +} + +static struct regulator_ops max8660_wifi_ops = { + .enable = max8660_wifi_enable, + .disable = max8660_wifi_disable, +}; + +/* hdd */ +static int max8660_hdd_enable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 4, 1); +} + +static int max8660_hdd_disable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 4, 0); +} + +static struct regulator_ops max8660_hdd_ops = { + .enable = max8660_hdd_enable, + .disable = max8660_hdd_disable, +}; + +/* gps */ +static int max8660_gps_enable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 0, 1); +} + +static int max8660_gps_disable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 0, 0); +} + +static struct regulator_ops max8660_gps_ops = { + .enable = max8660_gps_enable, + .disable = max8660_gps_disable, +}; + +/* cmos */ +static int max8660_cmos_enable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 4, 1); +} + +static int max8660_cmos_disable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 4, 0); +} + +static struct regulator_ops max8660_cmos_ops = { + .enable = max8660_cmos_enable, + .disable = max8660_cmos_disable, +}; + +/* pll */ +static int max8660_pll_enable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 5, 1); +} + +static int max8660_pll_disable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 5, 0); +} + +static struct regulator_ops max8660_pll_ops = { + .enable = max8660_pll_enable, + .disable = max8660_pll_disable, +}; + +static struct max8660_regulator + reg_max8660_children[NUM_MAX8660_CHILDREN_REGULATORS] = { + { + .regulator = { + .name = "LCD", + .id = MCU_LCD, + .ops = &max8660_lcd_ops, + .parent = ®_max8660[0].regulator, /*SW1 */ + }, + }, + { + .regulator = { + .name = "WIFI", + .id = MCU_WIFI, + .ops = &max8660_wifi_ops, + .parent = ®_max8660[3].regulator, /*SW4 */ + }, + }, + { + .regulator = { + .name = "HDD", + .id = MCU_HDD, + .ops = &max8660_hdd_ops, + }, + }, + { + .regulator = { + .name = "GPS", + .id = MCU_GPS, + .ops = &max8660_gps_ops, + .parent = ®_max8660[0].regulator, /*SW1 */ + }, + + }, + /* hw not finished!! */ + { + .regulator = { + .name = "CMOS", + .id = MCU_CMOS, + .ops = &max8660_cmos_ops, + }, + + }, + /* hw not finished!! */ + { + .regulator = { + .name = "PLL", + .id = MCU_PLL, + .ops = &max8660_pll_ops, + }, + + }, + +}; + +/* + * Init and Exit + */ +int reg_max8660_probe(void) +{ + int ret11 = 0; + int i = 0; + + for (i = 0; i < ARRAY_SIZE(reg_max8660); i++) { + ret11 = regulator_register(®_max8660[i].regulator); + regulator_set_platform_constraints(reg_max8660[i].regulator. + name, + reg_max8660[i].regulator. + constraints); + if (ret11 < 0) { + i--; + for (; i >= 0; i--) + regulator_unregister(®_max8660[i].regulator); + + return ret11; + } + + } + + /* for child regulators */ + for (i = 0; i < ARRAY_SIZE(reg_max8660_children); i++) { + ret11 = regulator_register(®_max8660_children[i].regulator); + regulator_set_platform_source(®_max8660_children[i]. + regulator, + reg_max8660[i].regulator.parent); + if (ret11 < 0) { + i--; + for (; i >= 0; i--) + regulator_unregister(®_max8660_children[i]. + regulator); + + return ret11; + } + + } + + return 0; +} +EXPORT_SYMBOL(reg_max8660_probe); + +int reg_max8660_remove(void) +{ + int i; + for (i = 0; i < ARRAY_SIZE(reg_max8660_children); i++) + regulator_unregister(®_max8660_children[i].regulator); + + for (i = 0; i < ARRAY_SIZE(reg_max8660); i++) + regulator_unregister(®_max8660[i].regulator); + return 0; +} +EXPORT_SYMBOL(reg_max8660_remove); + +/* Module information */ +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MAX8660 Regulator driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/regulator/mc13783/Makefile linux-2.6.26-lab126/drivers/regulator/mc13783/Makefile --- linux-2.6.26/drivers/regulator/mc13783/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/regulator/mc13783/Makefile 2010-08-10 04:16:18.000000000 -0400 @@ -0,0 +1,5 @@ +# +# Makefile for regulator driver for MC13783. +# + +obj-$(CONFIG_REGULATOR_MC13783) += reg-mc13783.o diff -urN linux-2.6.26/drivers/regulator/mc13783/reg-mc13783.c linux-2.6.26-lab126/drivers/regulator/mc13783/reg-mc13783.c --- linux-2.6.26/drivers/regulator/mc13783/reg-mc13783.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/regulator/mc13783/reg-mc13783.c 2010-08-10 04:16:18.000000000 -0400 @@ -0,0 +1,3235 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*! + * brief PMIC regulators. + */ + +enum { + MC13783_SW1A = 0, /*!< SW1A or SW1 */ + MC13783_SW1B, /*!< SW1B */ + MC13783_SW2A, /*!< SW2A or SW2 */ + MC13783_SW2B, /*!< SW2B */ + MC13783_SW3, /*!< SW3 */ + MC13783_VAUDIO, /*!< VAUDIO */ + MC13783_VIOHI, /*!< VIOHI */ + MC13783_VIOLO, /*!< VIOLO */ + MC13783_VDIG, /*!< VDIG */ + MC13783_VGEN, /*!< VGEN */ + MC13783_VRFDIG, /*!< VRFDIG */ + MC13783_VRFREF, /*!< VRFREF */ + MC13783_VRFCP, /*!< VRFCP */ + MC13783_VSIM, /*!< VSIM */ + MC13783_VESIM, /*!< VESIM */ + MC13783_VCAM, /*!< VCAM */ + MC13783_VRFBG, /*!< VRFBG */ + MC13783_VVIB, /*!< VVIB */ + MC13783_VRF1, /*!< VRF1 */ + MC13783_VRF2, /*!< VRF2 */ + MC13783_VMMC1, /*!< VMMC1 or VMMC */ + MC13783_VMMC2, /*!< VMMC2 */ + MC13783_GPO1, /*!< GPIO1 */ + MC13783_GPO2, /*!< GPO2 */ + MC13783_GPO3, /*!< GPO3 */ + MC13783_GPO4, /*!< GPO4 */ +} MC13783_regulator; + +/*! + * @enum regulator_voltage_sw + * @brief PMIC regulator SW output voltage. + */ +enum { + SW_0_9V = 0, /*!< 0.900 V */ + SW_0_925V, /*!< 0.925 V */ + SW_0_95V, /*!< 0.950 V */ + SW_0_975V, /*!< 0.975 V */ + SW_1V, /*!< 1.000 V */ + SW_1_025V, /*!< 1.025 V */ + SW_1_05V, /*!< 1.050 V */ + SW_1_075V, /*!< 1.075 V */ + SW_1_1V, /*!< 1.100 V */ + SW_1_125V, /*!< 1.125 V */ + SW_1_15V, /*!< 1.150 V */ + SW_1_175V, /*!< 1.175 V */ + SW_1_2V, /*!< 1.200 V */ + SW_1_225V, /*!< 1.225 V */ + SW_1_25V, /*!< 1.250 V */ + SW_1_275V, /*!< 1.275 V */ + SW_1_3V, /*!< 1.300 V */ + SW_1_325V, /*!< 1.325 V */ + SW_1_35V, /*!< 1.350 V */ + SW_1_375V, /*!< 1.375 V */ + SW_1_4V, /*!< 1.400 V */ + SW_1_425V, /*!< 1.425 V */ + SW_1_45V, /*!< 1.450 V */ + SW_1_475V, /*!< 1.475 V */ + SW_1_5V, /*!< 1.500 V */ + SW_1_525V, /*!< 1.525 V */ + SW_1_55V, /*!< 1.550 V */ + SW_1_575V, /*!< 1.575 V */ + SW_1_6V, /*!< 1.600 V */ + SW_1_625V, /*!< 1.625 V */ + SW_1_65V, /*!< 1.650 V */ + SW_1_675V, /*!< 1.675 V */ + SW_1_7V, /*!< 1.700 V */ + SW_1_8V = 36, /*!< 1.800 V */ + SW_1_85V = 40, /*!< 1.850 V */ + SW_2V = 44, /*!< 2_000 V */ + SW_2_1V = 48, /*!< 2_100 V */ + SW_2_2V = 52, /*!< 2_200 V */ +} regulator_voltage_sw; + +/*! + * @enum regulator_voltage_violo + * @brief PMIC regulator VIOLO output voltage. + */ +enum { + VIOLO_1_2V = 0, /*!< 1.2 V */ + VIOLO_1_3V, /*!< 1.3 V */ + VIOLO_1_5V, /*!< 1.5 V */ + VIOLO_1_8V, /*!< 1.8 V */ +} regulator_voltage_violo; + +/*! + * @enum regulator_voltage_vdig + * @brief PMIC regulator VDIG output voltage. + */ +enum { + VDIG_1_2V = 0, /*!< 1.2 V */ + VDIG_1_3V, /*!< 1.3 V */ + VDIG_1_5V, /*!< 1.5 V */ + VDIG_1_8V, /*!< 1.8 V */ +} regulator_voltage_vdig; + +/*! + * @enum regulator_voltage_vgen + * @brief PMIC regulator VGEN output voltage. + */ +enum { + VGEN_1_2V = 0, /*!< 1.2 V */ + VGEN_1_3V, /*!< 1.3 V */ + VGEN_1_5V, /*!< 1.5 V */ + VGEN_1_8V, /*!< 1.8 V */ + VGEN_1_1V, /*!< 1.1 V */ + VGEN_2V, /*!< 2 V */ + VGEN_2_775V, /*!< 2.775 V */ + VGEN_2_4V, /*!< 2.4 V */ +} regulator_voltage_vgen; + +/*! + * @enum regulator_voltage_vrfdig + * @brief PMIC regulator VRFDIG output voltage. + */ +enum { + VRFDIG_1_2V = 0, /*!< 1.2 V */ + VRFDIG_1_5V, /*!< 1.5 V */ + VRFDIG_1_8V, /*!< 1.8 V */ + VRFDIG_1_875V, /*!< 1.875 V */ +} regulator_voltage_vrfdig; + +/*! + * @enum regulator_voltage_vrfref + * @brief PMIC regulator VRFREF output voltage. + */ +enum { + VRFREF_2_475V = 0, /*!< 2.475 V */ + VRFREF_2_6V, /*!< 2.600 V */ + VRFREF_2_7V, /*!< 2.700 V */ + VRFREF_2_775V, /*!< 2.775 V */ +} regulator_voltage_vrfref; + +/*! + * @enum regulator_voltage_vrfcp + * @brief PMIC regulator VRFCP output voltage. + */ +enum { + VRFCP_2_7V = 0, /*!< 2.700 V */ + VRFCP_2_775V, /*!< 2.775 V */ +} regulator_voltage_vrfcp; + +/*! + * @enum regulator_voltage_vsim + * @brief PMIC linear regulator VSIM output voltage. + */ +enum { + VSIM_1_8V = 0, /*!< 1.8 V */ + VSIM_2_9V, /*!< 2.90 V */ + VSIM_3V = 1, /*!< 3 V */ +} regulator_voltage_vsim; + +/*! + * @enum regulator_voltage_vesim + * @brief PMIC regulator VESIM output voltage. + */ +enum { + VESIM_1_8V = 0, /*!< 1.80 V */ + VESIM_2_9V, /*!< 2.90 V */ +} regulator_voltage_vesim; + +/*! + * @enum regulator_voltage_vcam + * @brief PMIC regulator VCAM output voltage. + */ +enum { + VCAM_1_5V = 0, /*!< 1.50 V */ + VCAM_1_8V, /*!< 1.80 V */ + VCAM_2_5V, /*!< 2.50 V */ + VCAM_2_55V, /*!< 2.55 V */ + VCAM_2_6V, /*!< 2.60 V */ + VCAM_2_75V, /*!< 2.75 V */ + VCAM_2_8V, /*!< 2.80 V */ + VCAM_3V, /*!< 3.00 V */ +} regulator_voltage_vcam; + +/*! + * @enum regulator_voltage_vvib + * @brief PMIC linear regulator V_VIB output voltage. + */ +enum { + VVIB_1_3V = 0, /*!< 1.30 V */ + VVIB_1_8V, /*!< 1.80 V */ + VVIB_2V, /*!< 2 V */ + VVIB_3V, /*!< 3 V */ +} regulator_voltage_vvib; + +/*! + * @enum regulator_voltage_vmmc + * @brief MC13783 PMIC regulator VMMC output voltage. + */ +enum { + VMMC_1_6V = 0, /*!< 1.60 V */ + VMMC_1_8V, /*!< 1.80 V */ + VMMC_2V, /*!< 2.00 V */ + VMMC_2_6V, /*!< 2.60 V */ + VMMC_2_7V, /*!< 2.70 V */ + VMMC_2_8V, /*!< 2.80 V */ + VMMC_2_9V, /*!< 2.90 V */ + VMMC_3V, /*!< 3.00 V */ +} regulator_voltage_vmmc; + +/*! + * @enum regulator_voltage_vrf + * @brief PMIC regulator VRF output voltage. + */ +enum { + VRF_1_5V = 0, /*!< 1.500 V */ + VRF_1_875V, /*!< 1.875 V */ + VRF_2_7V, /*!< 2.700 V */ + VRF_2_775V, /*!< 2.775 V */ +} regulator_voltage_vrf; + +/*! + * @enum regulator_voltage_sw3 + * @brief PMIC Switch mode regulator SW3 output voltages. + */ +enum { + SW3_5V = 0, /*!< 5.0 V */ + SW3_5_5V = 3, /*!< 5.5 V */ +} regulator_voltage_sw3; + +/*! + * The \b TPmicDVSTransitionSpeed enum defines the rate with which the + * voltage transition occurs. + */ +enum { + ESysDependent, + E25mVEach4us, + E25mVEach8us, + E25mvEach16us +} DVS_transition_speed; + +/* + * Reg Regulator Mode 0 + */ +#define VAUDIO_EN_LSH 0 +#define VAUDIO_EN_WID 1 +#define VAUDIO_EN_ENABLE 1 +#define VAUDIO_EN_DISABLE 0 +#define VIOHI_EN_LSH 3 +#define VIOHI_EN_WID 1 +#define VIOHI_EN_ENABLE 1 +#define VIOHI_EN_DISABLE 0 +#define VIOLO_EN_LSH 6 +#define VIOLO_EN_WID 1 +#define VIOLO_EN_ENABLE 1 +#define VIOLO_EN_DISABLE 0 +#define VDIG_EN_LSH 9 +#define VDIG_EN_WID 1 +#define VDIG_EN_ENABLE 1 +#define VDIG_EN_DISABLE 0 +#define VGEN_EN_LSH 12 +#define VGEN_EN_WID 1 +#define VGEN_EN_ENABLE 1 +#define VGEN_EN_DISABLE 0 +#define VRFDIG_EN_LSH 15 +#define VRFDIG_EN_WID 1 +#define VRFDIG_EN_ENABLE 1 +#define VRFDIG_EN_DISABLE 0 +#define VRFREF_EN_LSH 18 +#define VRFREF_EN_WID 1 +#define VRFREF_EN_ENABLE 1 +#define VRFREF_EN_DISABLE 0 +#define VRFCP_EN_LSH 21 +#define VRFCP_EN_WID 1 +#define VRFCP_EN_ENABLE 1 +#define VRFCP_EN_DISABLE 0 + +/* + * Reg Regulator Mode 1 + */ +#define VSIM_EN_LSH 0 +#define VSIM_EN_WID 1 +#define VSIM_EN_ENABLE 1 +#define VSIM_EN_DISABLE 0 +#define VESIM_EN_LSH 3 +#define VESIM_EN_WID 1 +#define VESIM_EN_ENABLE 1 +#define VESIM_EN_DISABLE 0 +#define VCAM_EN_LSH 6 +#define VCAM_EN_WID 1 +#define VCAM_EN_ENABLE 1 +#define VCAM_EN_DISABLE 0 +#define VRFBG_EN_LSH 9 +#define VRFBG_EN_WID 1 +#define VRFBG_EN_ENABLE 1 +#define VRFBG_EN_DISABLE 0 +#define VVIB_EN_LSH 11 +#define VVIB_EN_WID 1 +#define VVIB_EN_ENABLE 1 +#define VVIB_EN_DISABLE 0 +#define VRF1_EN_LSH 12 +#define VRF1_EN_WID 1 +#define VRF1_EN_ENABLE 1 +#define VRF1_EN_DISABLE 0 +#define VRF2_EN_LSH 15 +#define VRF2_EN_WID 1 +#define VRF2_EN_ENABLE 1 +#define VRF2_EN_DISABLE 0 +#define VMMC1_EN_LSH 18 +#define VMMC1_EN_WID 1 +#define VMMC1_EN_ENABLE 1 +#define VMMC1_EN_DISABLE 0 +#define VMMC2_EN_LSH 21 +#define VMMC2_EN_WID 1 +#define VMMC2_EN_ENABLE 1 +#define VMMC2_EN_DISABLE 0 + +/* + * Reg Regulator Setting 0 + */ +#define VIOLO_LSH 2 +#define VIOLO_WID 2 +#define VDIG_LSH 4 +#define VDIG_WID 2 +#define VGEN_LSH 6 +#define VGEN_WID 3 +#define VRFDIG_LSH 9 +#define VRFDIG_WID 2 +#define VRFREF_LSH 11 +#define VRFREF_WID 2 +#define VRFCP_LSH 13 +#define VRFCP_WID 1 +#define VSIM_LSH 14 +#define VSIM_WID 1 +#define VESIM_LSH 15 +#define VESIM_WID 1 +#define VCAM_LSH 16 +#define VCAM_WID 3 + +/* + * Reg Regulator Setting 1 + */ +#define VVIB_LSH 0 +#define VVIB_WID 2 +#define VRF1_LSH 2 +#define VRF1_WID 2 +#define VRF2_LSH 4 +#define VRF2_WID 2 +#define VMMC1_LSH 6 +#define VMMC1_WID 3 +#define VMMC2_LSH 9 +#define VMMC2_WID 3 + +/* + * Reg Switcher 0 + */ +#define SW1A_LSH 0 +#define SW1A_WID 6 +#define SW1A_DVS_LSH 6 +#define SW1A_DVS_WID 6 +#define SW1A_STDBY_LSH 12 +#define SW1A_STDBY_WID 6 + +/* + * Reg Switcher 1 + */ +#define SW1B_LSH 0 +#define SW1B_WID 6 +#define SW1B_DVS_LSH 6 +#define SW1B_DVS_WID 6 +#define SW1B_STDBY_LSH 12 +#define SW1B_STDBY_WID 6 + +/* + * Reg Switcher 2 + */ +#define SW2A_LSH 0 +#define SW2A_WID 6 +#define SW2A_DVS_LSH 6 +#define SW2A_DVS_WID 6 +#define SW2A_STDBY_LSH 12 +#define SW2A_STDBY_WID 6 + +/* + * Reg Switcher 3 + */ +#define SW2B_LSH 0 +#define SW2B_WID 6 +#define SW2B_DVS_LSH 6 +#define SW2B_DVS_WID 6 +#define SW2B_STDBY_LSH 12 +#define SW2B_STDBY_WID 6 + +/* + * Reg Switcher 4 + */ +#define SW1A_MODE_LSH 0 +#define SW1A_MODE_WID 2 +#define SW1A_STBY_MODE_LSH 2 +#define SW1A_STBY_MODE_WID 2 +#define SW1A_DVS_SPEED_LSH 6 +#define SW1A_DVS_SPEED_WID 2 +#define SW1B_MODE_LSH 10 +#define SW1B_MODE_WID 2 +#define SW1B_STBY_MODE_LSH 12 +#define SW1B_STBY_MODE_WID 2 +#define SW1B_DVS_SPEED_LSH 14 +#define SW1B_DVS_SPEED_WID 2 + +/* + * Reg Switcher 5 + */ +#define SW2A_MODE_LSH 0 +#define SW2A_MODE_WID 2 +#define SW2A_STBY_MODE_LSH 2 +#define SW2A_STBY_MODE_WID 2 +#define SW2A_DVS_SPEED_LSH 6 +#define SW2A_DVS_SPEED_WID 2 +#define SW2B_MODE_LSH 10 +#define SW2B_MODE_WID 2 +#define SW2B_STBY_MODE_LSH 12 +#define SW2B_STBY_MODE_WID 2 +#define SW2B_DVS_SPEED_LSH 14 +#define SW2B_DVS_SPEED_WID 2 +#define SW3_LSH 18 +#define SW3_WID 2 +#define SW3_EN_LSH 20 +#define SW3_EN_WID 2 +#define SW3_EN_ENABLE 1 +#define SW3_EN_DISABLE 0 + +/* + * Reg Regulator Misc. + */ +#define GPO1_EN_LSH 6 +#define GPO1_EN_WID 1 +#define GPO1_EN_ENABLE 1 +#define GPO1_EN_DISABLE 0 +#define GPO2_EN_LSH 8 +#define GPO2_EN_WID 1 +#define GPO2_EN_ENABLE 1 +#define GPO2_EN_DISABLE 0 +#define GPO3_EN_LSH 10 +#define GPO3_EN_WID 1 +#define GPO3_EN_ENABLE 1 +#define GPO3_EN_DISABLE 0 +#define GPO4_EN_LSH 12 +#define GPO4_EN_WID 1 +#define GPO4_EN_ENABLE 1 +#define GPO4_EN_DISABLE 0 + +/* + * Switcher mode configuration + */ +#define SW_MODE_SYNC_RECT_EN 0 +#define SW_MODE_PULSE_NO_SKIP_EN 1 +#define SW_MODE_PULSE_SKIP_EN 2 +#define SW_MODE_LOW_POWER_EN 3 + +#define NUM_MC13783_REGULATORS 33 +#define dvs_speed E25mvEach16us + +static int mc13783_vaudio_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VAUDIO_EN, VAUDIO_EN_ENABLE); + register_mask = BITFMASK(VAUDIO_EN); + register1 = REG_REGULATOR_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vaudio_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VAUDIO_EN, VAUDIO_EN_DISABLE); + register_mask = BITFMASK(VAUDIO_EN); + register1 = REG_REGULATOR_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_viohi_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VIOHI_EN, VIOHI_EN_ENABLE); + register_mask = BITFMASK(VIOHI_EN); + register1 = REG_REGULATOR_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_viohi_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VIOHI_EN, VIOHI_EN_DISABLE); + register_mask = BITFMASK(VIOHI_EN); + register1 = REG_REGULATOR_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_violo_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0, register1 = 0; + int voltage, mV = uV / 1000; + + if ((mV >= 1200) && (mV < 1300)) + voltage = VIOLO_1_2V; + else if ((mV >= 1300) && (mV < 1500)) + voltage = VIOLO_1_3V; + else if ((mV >= 1500) && (mV < 1800)) + voltage = VIOLO_1_5V; + else + voltage = VIOLO_1_8V; + + register_val = BITFVAL(VIOLO, voltage); + register_mask = BITFMASK(VIOLO); + register1 = REG_REGULATOR_SETTING_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_violo_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VIOLO); + + switch (voltage) { + case VIOLO_1_2V: + mV = 1200; + break; + case VIOLO_1_3V: + mV = 1300; + break; + case VIOLO_1_5V: + mV = 1500; + break; + case VIOLO_1_8V: + mV = 1800; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_violo_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VIOLO_EN, VIOLO_EN_ENABLE); + register_mask = BITFMASK(VIOLO_EN); + register1 = REG_REGULATOR_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_violo_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VIOLO_EN, VIOLO_EN_DISABLE); + register_mask = BITFMASK(VIOLO_EN); + register1 = REG_REGULATOR_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vdig_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1200) && (mV < 1300)) + voltage = VDIG_1_2V; + else if ((mV >= 1300) && (mV < 1500)) + voltage = VDIG_1_3V; + else if ((mV >= 1500) && (mV < 1800)) + voltage = VDIG_1_5V; + else + voltage = VDIG_1_8V; + + register_val = BITFVAL(VDIG, voltage); + register_mask = BITFMASK(VDIG); + register1 = REG_REGULATOR_SETTING_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vdig_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VDIG); + + switch (voltage) { + case VDIG_1_2V: + mV = 1200; + break; + case VDIG_1_3V: + mV = 1300; + break; + case VDIG_1_5V: + mV = 1500; + break; + case VDIG_1_8V: + mV = 1800; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vdig_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VDIG_EN, VDIG_EN_ENABLE); + register_mask = BITFMASK(VDIG_EN); + register1 = REG_REGULATOR_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vdig_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VDIG_EN, VDIG_EN_DISABLE); + register_mask = BITFMASK(VDIG_EN); + register1 = REG_REGULATOR_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vgen_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + int vgenid = reg->id; + + printk(KERN_INFO "VGEN ID is %d\n", vgenid); + + if ((mV >= 1100) && (mV < 1200)) + voltage = VGEN_1_1V; + else if ((mV >= 1200) && (mV < 1300)) + voltage = VGEN_1_2V; + else if ((mV >= 1300) && (mV < 1500)) + voltage = VGEN_1_3V; + else if ((mV >= 1500) && (mV < 1800)) + voltage = VGEN_1_5V; + else if ((mV >= 1800) && (mV < 2000)) + voltage = VGEN_1_8V; + else if ((mV >= 2000) && (mV < 2400)) + voltage = VGEN_2V; + else if ((mV >= 2400) && (mV < 2775)) + voltage = VGEN_2_4V; + else + voltage = VGEN_2_775V; + + register_val = BITFVAL(VGEN, voltage); + register_mask = BITFMASK(VGEN); + register1 = REG_REGULATOR_SETTING_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vgen_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VGEN); + + switch (voltage) { + case VGEN_1_2V: + mV = 1200; + break; + case VGEN_1_3V: + mV = 1300; + break; + case VGEN_1_5V: + mV = 1500; + break; + case VGEN_1_8V: + mV = 1800; + break; + case VGEN_1_1V: + mV = 1100; + break; + case VGEN_2V: + mV = 2000; + break; + case VGEN_2_775V: + mV = 2775; + break; + case VGEN_2_4V: + mV = 2400; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vgen_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VGEN_EN, VGEN_EN_ENABLE); + register_mask = BITFMASK(VGEN_EN); + register1 = REG_REGULATOR_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vgen_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VGEN_EN, VGEN_EN_DISABLE); + register_mask = BITFMASK(VGEN_EN); + register1 = REG_REGULATOR_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vrfdig_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1200) && (mV < 1500)) + voltage = VRFDIG_1_2V; + else if ((mV >= 1500) && (mV < 1300)) + voltage = VRFDIG_1_5V; + else if ((mV >= 1800) && (mV < 1875)) + voltage = VRFDIG_1_8V; + else + voltage = VRFDIG_1_875V; + + register_val = BITFVAL(VRFDIG, voltage); + register_mask = BITFMASK(VRFDIG); + register1 = REG_REGULATOR_SETTING_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vrfdig_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VRFDIG); + + switch (voltage) { + case VRFDIG_1_2V: + mV = 1200; + break; + case VRFDIG_1_5V: + mV = 1500; + break; + case VRFDIG_1_8V: + mV = 1800; + break; + case VRFDIG_1_875V: + mV = 1875; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vrfdig_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VRFDIG_EN, VRFDIG_EN_ENABLE); + register_mask = BITFMASK(VRFDIG_EN); + register1 = REG_REGULATOR_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vrfdig_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VRFDIG_EN, VRFDIG_EN_DISABLE); + register_mask = BITFMASK(VRFDIG_EN); + register1 = REG_REGULATOR_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vrfref_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 2475) && (mV < 2600)) + voltage = VRFREF_2_475V; + else if ((mV >= 2600) && (mV < 2700)) + voltage = VRFREF_2_6V; + else if ((mV >= 2700) && (mV < 2775)) + voltage = VRFREF_2_7V; + else + voltage = VRFREF_2_775V; + + register_val = BITFVAL(VRFREF, voltage); + register_mask = BITFMASK(VRFREF); + register1 = REG_REGULATOR_SETTING_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vrfref_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VRFREF); + + switch (voltage) { + case VRFREF_2_475V: + mV = 2475; + break; + case VRFREF_2_6V: + mV = 2600; + break; + case VRFREF_2_7V: + mV = 2700; + break; + case VRFREF_2_775V: + mV = 2775; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vrfref_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VRFREF_EN, VRFREF_EN_ENABLE); + register_mask = BITFMASK(VRFREF_EN); + register1 = REG_REGULATOR_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vrfref_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VRFREF_EN, VRFREF_EN_DISABLE); + register_mask = BITFMASK(VRFREF_EN); + register1 = REG_REGULATOR_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vrfcp_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 2700) && (mV < 2775)) + voltage = VRFCP_2_7V; + else + voltage = VRFCP_2_775V; + + register_val = BITFVAL(VRFCP, voltage); + register_mask = BITFMASK(VRFCP); + register1 = REG_REGULATOR_SETTING_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vrfcp_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VRFCP); + + switch (voltage) { + case VRFCP_2_7V: + mV = 2700; + break; + case VRFCP_2_775V: + mV = 2775; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vrfcp_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VRFCP_EN, VRFCP_EN_ENABLE); + register_mask = BITFMASK(VRFCP_EN); + register1 = REG_REGULATOR_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vrfcp_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VRFCP_EN, VRFCP_EN_DISABLE); + register_mask = BITFMASK(VRFCP_EN); + register1 = REG_REGULATOR_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vsim_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1800) && (mV < 2900)) + voltage = VSIM_1_8V; + else + voltage = VSIM_2_9V; + + register_val = BITFVAL(VSIM, voltage); + register_mask = BITFMASK(VSIM); + register1 = REG_REGULATOR_SETTING_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vsim_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VSIM); + + switch (voltage) { + case VSIM_1_8V: + mV = 1800; + break; + case VSIM_2_9V: + mV = 1900; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vsim_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VSIM_EN, VSIM_EN_ENABLE); + register_mask = BITFMASK(VSIM_EN); + register1 = REG_REGULATOR_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vsim_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VSIM_EN, VSIM_EN_DISABLE); + register_mask = BITFMASK(VSIM_EN); + register1 = REG_REGULATOR_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vesim_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1800) && (mV < 2900)) + voltage = VESIM_1_8V; + else + voltage = VESIM_2_9V; + + register_val = BITFVAL(VESIM, voltage); + register_mask = BITFMASK(VESIM); + register1 = REG_REGULATOR_SETTING_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vesim_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VESIM); + + switch (voltage) { + case VESIM_1_8V: + mV = 1800; + break; + case VESIM_2_9V: + mV = 1900; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vesim_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VESIM_EN, VESIM_EN_ENABLE); + register_mask = BITFMASK(VESIM_EN); + register1 = REG_REGULATOR_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vesim_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VESIM_EN, VESIM_EN_DISABLE); + register_mask = BITFMASK(VESIM_EN); + register1 = REG_REGULATOR_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vcam_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1500) && (mV < 1800)) + voltage = VCAM_1_5V; + else if ((mV >= 1800) && (mV < 2500)) + voltage = VCAM_1_8V; + else if ((mV >= 2500) && (mV < 2550)) + voltage = VCAM_2_5V; + else if ((mV >= 2550) && (mV < 2600)) + voltage = VCAM_2_55V; + if ((mV >= 2600) && (mV < 2750)) + voltage = VCAM_2_6V; + else if ((mV >= 2750) && (mV < 2800)) + voltage = VCAM_2_75V; + else if ((mV >= 2800) && (mV < 3000)) + voltage = VCAM_2_8V; + else + voltage = VCAM_3V; + + register_val = BITFVAL(VCAM, voltage); + register_mask = BITFMASK(VCAM); + register1 = REG_REGULATOR_SETTING_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vcam_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VCAM); + + switch (voltage) { + case VCAM_1_5V: + mV = 1500; + break; + case VCAM_1_8V: + mV = 1800; + break; + case VCAM_2_5V: + mV = 2500; + break; + case VCAM_2_55V: + mV = 2550; + break; + case VCAM_2_6V: + mV = 2600; + break; + case VCAM_2_75V: + mV = 2750; + break; + case VCAM_2_8V: + mV = 2800; + break; + case VCAM_3V: + mV = 3000; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vcam_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VCAM_EN, VCAM_EN_ENABLE); + register_mask = BITFMASK(VCAM_EN); + register1 = REG_REGULATOR_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vcam_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VCAM_EN, VCAM_EN_DISABLE); + register_mask = BITFMASK(VCAM_EN); + register1 = REG_REGULATOR_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vvib_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1300) && (mV < 1800)) + voltage = VVIB_1_3V; + else if ((mV >= 1800) && (mV < 2000)) + voltage = VVIB_1_8V; + else if ((mV >= 2000) && (mV < 3000)) + voltage = VVIB_2V; + else + voltage = VVIB_3V; + + register_val = BITFVAL(VVIB, voltage); + register_mask = BITFMASK(VVIB); + register1 = REG_REGULATOR_SETTING_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vvib_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_1, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VVIB); + + switch (voltage) { + case VVIB_1_3V: + mV = 1300; + break; + case VVIB_1_8V: + mV = 1800; + break; + case VVIB_2V: + mV = 2000; + break; + case VVIB_3V: + mV = 3000; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vvib_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VVIB_EN, VVIB_EN_ENABLE); + register_mask = BITFMASK(VVIB_EN); + register1 = REG_REGULATOR_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vvib_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VVIB_EN, VVIB_EN_DISABLE); + register_mask = BITFMASK(VVIB_EN); + register1 = REG_REGULATOR_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vrf_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, rf = reg->id, mV = uV / 1000; + + if ((mV >= 1500) && (mV < 1875)) + voltage = VRF_1_5V; + else if ((mV >= 1875) && (mV < 2700)) + voltage = VRF_1_875V; + else if ((mV >= 2700) && (mV < 2775)) + voltage = VRF_2_7V; + else + voltage = VRF_2_775V; + + switch (rf) { + case MC13783_VRF1: + register_val = BITFVAL(VRF1, voltage); + register_mask = BITFMASK(VRF1); + break; + case MC13783_VRF2: + register_val = BITFVAL(VRF2, voltage); + register_mask = BITFMASK(VRF2); + break; + default: + return -EINVAL; + } + + register1 = REG_REGULATOR_SETTING_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vrf_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, rf = reg->id, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_1, + ®ister_val, PMIC_ALL_BITS)); + + switch (rf) { + case MC13783_VRF1: + voltage = BITFEXT(register_val, VRF1); + break; + case MC13783_VRF2: + voltage = BITFEXT(register_val, VRF2); + break; + default: + return -EINVAL; + }; + + switch (voltage) { + case VRF_1_5V: + mV = 1500; + break; + case VRF_1_875V: + mV = 1875; + break; + case VRF_2_7V: + mV = 2700; + break; + case VRF_2_775V: + mV = 2775; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vrf_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int vrf = reg->id; + + switch (vrf) { + case MC13783_VRF1: + register_val = BITFVAL(VRF1_EN, VRF1_EN_ENABLE); + register_mask = BITFMASK(VRF1_EN); + break; + case MC13783_VRF2: + register_val = BITFVAL(VRF2_EN, VRF2_EN_ENABLE); + register_mask = BITFMASK(VRF2_EN); + break; + default: + return -EINVAL; + }; + + register1 = REG_REGULATOR_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vrf_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int vrf = reg->id; + + switch (vrf) { + case MC13783_VRF1: + register_val = BITFVAL(VRF1_EN, VRF1_EN_DISABLE); + register_mask = BITFMASK(VRF1_EN); + break; + case MC13783_VRF2: + register_val = BITFVAL(VRF2_EN, VRF2_EN_DISABLE); + register_mask = BITFMASK(VRF2_EN); + break; + default: + return -EINVAL; + }; + + register1 = REG_REGULATOR_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vmmc_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mmc = reg->id, mV = uV / 1000; + + printk(KERN_INFO "VMMC ID is %d\n", mmc); + + if ((mV >= 1600) && (mV < 1800)) + voltage = VMMC_1_6V; + else if ((mV >= 1800) && (mV < 2000)) + voltage = VMMC_1_8V; + else if ((mV >= 2000) && (mV < 2600)) + voltage = VMMC_2V; + else if ((mV >= 2600) && (mV < 2700)) + voltage = VMMC_2_6V; + else if ((mV >= 2700) && (mV < 2800)) + voltage = VMMC_2_7V; + else if ((mV >= 2800) && (mV < 2900)) + voltage = VMMC_2_8V; + else if ((mV >= 2900) && (mV < 3000)) + voltage = VMMC_2_9V; + else + voltage = VMMC_3V; + + switch (mmc) { + case MC13783_VMMC1: + register_val = BITFVAL(VMMC1, voltage); + register_mask = BITFMASK(VMMC1); + break; + case MC13783_VMMC2: + register_val = BITFVAL(VMMC2, voltage); + register_mask = BITFMASK(VMMC2); + break; + default: + return -EINVAL; + } + + register1 = REG_REGULATOR_SETTING_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vmmc_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mmc = reg->id, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_1, + ®ister_val, PMIC_ALL_BITS)); + + switch (mmc) { + case MC13783_VMMC1: + voltage = BITFEXT(register_val, VMMC1); + break; + case MC13783_VMMC2: + voltage = BITFEXT(register_val, VMMC2); + break; + default: + return -EINVAL; + } + + switch (voltage) { + case VMMC_1_6V: + mV = 1600; + break; + case VMMC_1_8V: + mV = 1800; + break; + case VMMC_2V: + mV = 2000; + break; + case VMMC_2_6V: + mV = 2600; + break; + case VMMC_2_7V: + mV = 2700; + break; + case VMMC_2_8V: + mV = 2800; + break; + case VMMC_2_9V: + mV = 2900; + break; + case VMMC_3V: + mV = 3000; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vmmc_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int vmmc = reg->id; + + switch (vmmc) { + case MC13783_VMMC1: + register_val = BITFVAL(VMMC1_EN, VMMC1_EN_ENABLE); + register_mask = BITFMASK(VMMC1_EN); + break; + case MC13783_VMMC2: + register_val = BITFVAL(VMMC2_EN, VMMC2_EN_ENABLE); + register_mask = BITFMASK(VMMC2_EN); + break; + default: + return -EINVAL; + }; + + register1 = REG_REGULATOR_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_vmmc_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int vmmc = reg->id; + + switch (vmmc) { + case MC13783_VMMC1: + register_val = BITFVAL(VMMC1_EN, VMMC1_EN_DISABLE); + register_mask = BITFMASK(VMMC1_EN); + break; + case MC13783_VMMC2: + register_val = BITFVAL(VMMC2_EN, VMMC2_EN_DISABLE); + register_mask = BITFMASK(VMMC2_EN); + break; + default: + return -EINVAL; + }; + + register1 = REG_REGULATOR_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_gpo_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int gpo = reg->id; + + switch (gpo) { + case MC13783_GPO1: + register_val = BITFVAL(GPO1_EN, GPO1_EN_ENABLE); + register_mask = BITFMASK(GPO1_EN); + break; + case MC13783_GPO2: + register_val = BITFVAL(GPO2_EN, GPO2_EN_ENABLE); + register_mask = BITFMASK(GPO2_EN); + break; + case MC13783_GPO3: + register_val = BITFVAL(GPO3_EN, GPO3_EN_ENABLE); + register_mask = BITFMASK(GPO3_EN); + break; + case MC13783_GPO4: + register_val = BITFVAL(GPO4_EN, GPO4_EN_ENABLE); + register_mask = BITFMASK(GPO4_EN); + break; + default: + return -EINVAL; + }; + + register1 = REG_POWER_MISCELLANEOUS; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_gpo_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int gpo = reg->id; + + switch (gpo) { + case MC13783_GPO1: + register_val = BITFVAL(GPO1_EN, GPO1_EN_DISABLE); + register_mask = BITFMASK(GPO1_EN); + break; + case MC13783_GPO2: + register_val = BITFVAL(GPO2_EN, GPO2_EN_DISABLE); + register_mask = BITFMASK(GPO2_EN); + break; + case MC13783_GPO3: + register_val = BITFVAL(GPO3_EN, GPO3_EN_DISABLE); + register_mask = BITFMASK(GPO3_EN); + break; + case MC13783_GPO4: + register_val = BITFVAL(GPO4_EN, GPO4_EN_DISABLE); + register_mask = BITFMASK(GPO4_EN); + break; + default: + return -EINVAL; + }; + + register1 = REG_POWER_MISCELLANEOUS; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_sw3_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0, register1 = 0; + int voltage, mV = uV / 1000; + + if ((mV >= 5000) && (mV < 5500)) + voltage = SW3_5V; + else + voltage = SW3_5_5V; + + register_val = BITFVAL(SW3, voltage); + register_mask = BITFMASK(SW3); + register1 = REG_SWITCHERS_5; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_sw3_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_5, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW3); + + if (voltage == SW3_5_5V) + mV = 5500; + else + mV = 5000; + + return mV * 1000; +} + +static int mc13783_sw3_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(SW3_EN, SW3_EN_ENABLE); + register_mask = BITFMASK(SW3_EN); + register1 = REG_SWITCHERS_5; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_sw3_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(SW3_EN, SW3_EN_DISABLE); + register_mask = BITFMASK(SW3_EN); + register1 = REG_SWITCHERS_5; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_sw_set_normal_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1 = 0; + int voltage, sw = reg->id, mV = uV / 1000; + + if ((mV >= 900) && (mV < 925)) + voltage = SW_0_9V; + else if ((mV >= 925) && (mV < 950)) + voltage = SW_0_925V; + else if ((mV >= 950) && (mV < 975)) + voltage = SW_0_95V; + else if ((mV >= 975) && (mV < 1000)) + voltage = SW_0_975V; + else if ((mV >= 1000) && (mV < 1025)) + voltage = SW_1V; + else if ((mV >= 1025) && (mV < 1050)) + voltage = SW_1_025V; + else if ((mV >= 1050) && (mV < 1075)) + voltage = SW_1_05V; + else if ((mV >= 1075) && (mV < 1100)) + voltage = SW_1_075V; + else if ((mV >= 1100) && (mV < 1125)) + voltage = SW_1_1V; + else if ((mV >= 1125) && (mV < 1150)) + voltage = SW_1_125V; + else if ((mV >= 1150) && (mV < 1175)) + voltage = SW_1_15V; + else if ((mV >= 1175) && (mV < 1200)) + voltage = SW_1_175V; + else if ((mV >= 1200) && (mV < 1225)) + voltage = SW_1_2V; + else if ((mV >= 1225) && (mV < 1250)) + voltage = SW_1_225V; + else if ((mV >= 1250) && (mV < 1275)) + voltage = SW_1_25V; + else if ((mV >= 1275) && (mV < 1300)) + voltage = SW_1_275V; + else if ((mV >= 1300) && (mV < 1325)) + voltage = SW_1_3V; + else if ((mV >= 1325) && (mV < 1350)) + voltage = SW_1_325V; + else if ((mV >= 1350) && (mV < 1375)) + voltage = SW_1_35V; + else if ((mV >= 1375) && (mV < 1400)) + voltage = SW_1_375V; + else if ((mV >= 1400) && (mV < 1425)) + voltage = SW_1_4V; + else if ((mV >= 1425) && (mV < 1450)) + voltage = SW_1_425V; + else if ((mV >= 1450) && (mV < 1475)) + voltage = SW_1_45V; + else if ((mV >= 1475) && (mV < 1500)) + voltage = SW_1_475V; + else if ((mV >= 1500) && (mV < 1525)) + voltage = SW_1_5V; + else if ((mV >= 1525) && (mV < 1550)) + voltage = SW_1_525V; + else if ((mV >= 1550) && (mV < 1575)) + voltage = SW_1_55V; + else if ((mV >= 1575) && (mV < 1600)) + voltage = SW_1_575V; + else if ((mV >= 1600) && (mV < 1625)) + voltage = SW_1_6V; + else if ((mV >= 1625) && (mV < 1650)) + voltage = SW_1_625V; + else if ((mV >= 1650) && (mV < 1675)) + voltage = SW_1_65V; + else if ((mV >= 1675) && (mV < 1700)) + voltage = SW_1_675V; + else if ((mV >= 1700) && (mV < 1800)) + voltage = SW_1_7V; + else if ((mV >= 1800) && (mV < 1850)) + voltage = SW_1_8V; + else if ((mV >= 1850) && (mV < 2000)) + voltage = SW_1_85V; + else if ((mV >= 2000) && (mV < 2100)) + voltage = SW_2V; + else if ((mV >= 2100) && (mV < 2200)) + voltage = SW_2_1V; + else + voltage = SW_2_2V; + + switch (sw) { + case MC13783_SW1A: + register1 = REG_SWITCHERS_0; + register_val = BITFVAL(SW1A, voltage); + register_mask = BITFMASK(SW1A); + break; + case MC13783_SW1B: + register1 = REG_SWITCHERS_1; + register_val = BITFVAL(SW1B, voltage); + register_mask = BITFMASK(SW1B); + break; + case MC13783_SW2A: + register1 = REG_SWITCHERS_2; + register_val = BITFVAL(SW2A, voltage); + register_mask = BITFMASK(SW2A); + break; + case MC13783_SW2B: + register1 = REG_SWITCHERS_3; + register_val = BITFVAL(SW2B, voltage); + register_mask = BITFMASK(SW2B); + break; + default: + return -EINVAL; + } + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_sw_get_normal_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0, sw = reg->id; + + switch (sw) { + case MC13783_SW1A: + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW1A); + break; + case MC13783_SW1B: + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_1, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW1B); + break; + case MC13783_SW2A: + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_2, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW2A); + break; + case MC13783_SW2B: + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_3, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW2B); + break; + default: + return -EINVAL; + } + + switch (voltage) { + case SW_0_9V: + mV = 900; + break; + case SW_0_925V: + mV = 925; + break; + case SW_0_95V: + mV = 950; + break; + case SW_0_975V: + mV = 975; + break; + case SW_1V: + mV = 1000; + break; + case SW_1_025V: + mV = 1025; + break; + case SW_1_05V: + mV = 1050; + break; + case SW_1_075V: + mV = 1075; + break; + case SW_1_1V: + mV = 1100; + break; + case SW_1_125V: + mV = 1125; + break; + case SW_1_15V: + mV = 1150; + break; + case SW_1_175V: + mV = 1175; + break; + case SW_1_2V: + mV = 1200; + break; + case SW_1_225V: + mV = 1225; + break; + case SW_1_25V: + mV = 1250; + break; + case SW_1_275V: + mV = 1275; + break; + case SW_1_3V: + mV = 1300; + break; + case SW_1_325V: + mV = 1325; + break; + case SW_1_35V: + mV = 1350; + break; + case SW_1_375V: + mV = 1375; + break; + case SW_1_4V: + mV = 1400; + break; + case SW_1_425V: + mV = 1425; + break; + case SW_1_45V: + mV = 1450; + break; + case SW_1_475V: + mV = 1475; + break; + case SW_1_5V: + mV = 1500; + break; + case SW_1_525V: + mV = 1525; + break; + case SW_1_55V: + mV = 1550; + break; + case SW_1_575V: + mV = 1575; + break; + case SW_1_6V: + mV = 1600; + break; + case SW_1_625V: + mV = 1625; + break; + case SW_1_65V: + mV = 1650; + break; + case SW_1_675V: + mV = 1675; + break; + case SW_1_7V: + mV = 1700; + break; + case SW_1_8V: + mV = 1800; + break; + case SW_1_85V: + mV = 1850; + break; + case SW_2V: + mV = 2000; + break; + case SW_2_1V: + mV = 2100; + break; + case SW_2_2V: + mV = 2200; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_sw_set_dvs_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0, register2_val = + 0, register2_mask = 0; + unsigned int register1 = 0, register2 = 0; + int voltage, sw = reg->id, mV = uV / 1000; + + if ((mV >= 900) && (mV < 925)) + voltage = SW_0_9V; + else if ((mV >= 925) && (mV < 950)) + voltage = SW_0_925V; + else if ((mV >= 950) && (mV < 975)) + voltage = SW_0_95V; + else if ((mV >= 975) && (mV < 1000)) + voltage = SW_0_975V; + else if ((mV >= 1000) && (mV < 1025)) + voltage = SW_1V; + else if ((mV >= 1025) && (mV < 1050)) + voltage = SW_1_025V; + else if ((mV >= 1050) && (mV < 1075)) + voltage = SW_1_05V; + else if ((mV >= 1075) && (mV < 1100)) + voltage = SW_1_075V; + else if ((mV >= 1100) && (mV < 1125)) + voltage = SW_1_1V; + else if ((mV >= 1125) && (mV < 1150)) + voltage = SW_1_125V; + else if ((mV >= 1150) && (mV < 1175)) + voltage = SW_1_15V; + else if ((mV >= 1175) && (mV < 1200)) + voltage = SW_1_175V; + else if ((mV >= 1200) && (mV < 1225)) + voltage = SW_1_2V; + else if ((mV >= 1225) && (mV < 1250)) + voltage = SW_1_225V; + else if ((mV >= 1250) && (mV < 1275)) + voltage = SW_1_25V; + else if ((mV >= 1275) && (mV < 1300)) + voltage = SW_1_275V; + else if ((mV >= 1300) && (mV < 1325)) + voltage = SW_1_3V; + else if ((mV >= 1325) && (mV < 1350)) + voltage = SW_1_325V; + else if ((mV >= 1350) && (mV < 1375)) + voltage = SW_1_35V; + else if ((mV >= 1375) && (mV < 1400)) + voltage = SW_1_375V; + else if ((mV >= 1400) && (mV < 1425)) + voltage = SW_1_4V; + else if ((mV >= 1425) && (mV < 1450)) + voltage = SW_1_425V; + else if ((mV >= 1450) && (mV < 1475)) + voltage = SW_1_45V; + else if ((mV >= 1475) && (mV < 1500)) + voltage = SW_1_475V; + else if ((mV >= 1500) && (mV < 1525)) + voltage = SW_1_5V; + else if ((mV >= 1525) && (mV < 1550)) + voltage = SW_1_525V; + else if ((mV >= 1550) && (mV < 1575)) + voltage = SW_1_55V; + else if ((mV >= 1575) && (mV < 1600)) + voltage = SW_1_575V; + else if ((mV >= 1600) && (mV < 1625)) + voltage = SW_1_6V; + else if ((mV >= 1625) && (mV < 1650)) + voltage = SW_1_625V; + else if ((mV >= 1650) && (mV < 1675)) + voltage = SW_1_65V; + else if ((mV >= 1675) && (mV < 1700)) + voltage = SW_1_675V; + else if ((mV >= 1700) && (mV < 1800)) + voltage = SW_1_7V; + else if ((mV >= 1800) && (mV < 1850)) + voltage = SW_1_8V; + else if ((mV >= 1850) && (mV < 2000)) + voltage = SW_1_85V; + else if ((mV >= 2000) && (mV < 2100)) + voltage = SW_2V; + else if ((mV >= 2100) && (mV < 2200)) + voltage = SW_2_1V; + else + voltage = SW_2_2V; + + switch (sw) { + case MC13783_SW1A: + register1 = REG_SWITCHERS_0; + register_val = BITFVAL(SW1A_DVS, voltage); + register_mask = BITFMASK(SW1A_DVS); + register2 = REG_SWITCHERS_4; + register2_val = BITFVAL(SW1A_DVS_SPEED, dvs_speed); + register2_mask = BITFMASK(SW1A_DVS_SPEED); + break; + case MC13783_SW1B: + register1 = REG_SWITCHERS_1; + register_val = BITFVAL(SW1B_DVS, voltage); + register_mask = BITFMASK(SW1B_DVS); + register2 = REG_SWITCHERS_4; + register2_val = BITFVAL(SW1B_DVS_SPEED, dvs_speed); + register2_mask = BITFMASK(SW1B_DVS_SPEED); + break; + case MC13783_SW2A: + register1 = REG_SWITCHERS_2; + register_val = BITFVAL(SW2A_DVS, voltage); + register_mask = BITFMASK(SW2A_DVS); + register2 = REG_SWITCHERS_5; + register2_val = BITFVAL(SW2A_DVS_SPEED, dvs_speed); + register2_mask = BITFMASK(SW2A_DVS_SPEED); + break; + case MC13783_SW2B: + register1 = REG_SWITCHERS_3; + register_val = BITFVAL(SW2B_DVS, voltage); + register_mask = BITFMASK(SW2B_DVS); + register2 = REG_SWITCHERS_5; + register2_val = BITFVAL(SW2B_DVS_SPEED, dvs_speed); + register2_mask = BITFMASK(SW2B_DVS_SPEED); + break; + default: + return -EINVAL; + } + + CHECK_ERROR(pmic_write_reg(register1, register_val, register_mask)); + CHECK_ERROR(pmic_write_reg(register2, register2_val, register2_mask)); + + return 0; +} + +static int mc13783_sw_get_dvs_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0, sw = reg->id; + + switch (sw) { + case MC13783_SW1A: + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW1A_DVS); + break; + case MC13783_SW1B: + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_1, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW1B_DVS); + break; + case MC13783_SW2A: + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_2, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW2A_DVS); + break; + case MC13783_SW2B: + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_3, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW2B_DVS); + break; + default: + return -EINVAL; + } + + switch (voltage) { + case SW_0_9V: + mV = 900; + break; + case SW_0_925V: + mV = 925; + break; + case SW_0_95V: + mV = 950; + break; + case SW_0_975V: + mV = 975; + break; + case SW_1V: + mV = 1000; + break; + case SW_1_025V: + mV = 1025; + break; + case SW_1_05V: + mV = 1050; + break; + case SW_1_075V: + mV = 1075; + break; + case SW_1_1V: + mV = 1100; + break; + case SW_1_125V: + mV = 1125; + break; + case SW_1_15V: + mV = 1150; + break; + case SW_1_175V: + mV = 1175; + break; + case SW_1_2V: + mV = 1200; + break; + case SW_1_225V: + mV = 1225; + break; + case SW_1_25V: + mV = 1250; + break; + case SW_1_275V: + mV = 1275; + break; + case SW_1_3V: + mV = 1300; + break; + case SW_1_325V: + mV = 1325; + break; + case SW_1_35V: + mV = 1350; + break; + case SW_1_375V: + mV = 1375; + break; + case SW_1_4V: + mV = 1400; + break; + case SW_1_425V: + mV = 1425; + break; + case SW_1_45V: + mV = 1450; + break; + case SW_1_475V: + mV = 1475; + break; + case SW_1_5V: + mV = 1500; + break; + case SW_1_525V: + mV = 1525; + break; + case SW_1_55V: + mV = 1550; + break; + case SW_1_575V: + mV = 1575; + break; + case SW_1_6V: + mV = 1600; + break; + case SW_1_625V: + mV = 1625; + break; + case SW_1_65V: + mV = 1650; + break; + case SW_1_675V: + mV = 1675; + break; + case SW_1_7V: + mV = 1700; + break; + case SW_1_8V: + mV = 1800; + break; + case SW_1_85V: + mV = 1850; + break; + case SW_2V: + mV = 2000; + break; + case SW_2_1V: + mV = 2100; + break; + case SW_2_2V: + mV = 2200; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_sw_set_stby_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1 = 0; + int voltage, sw = reg->id, mV = uV / 1000; + + if ((mV >= 900) && (mV < 925)) + voltage = SW_0_9V; + else if ((mV >= 925) && (mV < 950)) + voltage = SW_0_925V; + else if ((mV >= 950) && (mV < 975)) + voltage = SW_0_95V; + else if ((mV >= 975) && (mV < 1000)) + voltage = SW_0_975V; + else if ((mV >= 1000) && (mV < 1025)) + voltage = SW_1V; + else if ((mV >= 1025) && (mV < 1050)) + voltage = SW_1_025V; + else if ((mV >= 1050) && (mV < 1075)) + voltage = SW_1_05V; + else if ((mV >= 1075) && (mV < 1100)) + voltage = SW_1_075V; + else if ((mV >= 1100) && (mV < 1125)) + voltage = SW_1_1V; + else if ((mV >= 1125) && (mV < 1150)) + voltage = SW_1_125V; + else if ((mV >= 1150) && (mV < 1175)) + voltage = SW_1_15V; + else if ((mV >= 1175) && (mV < 1200)) + voltage = SW_1_175V; + else if ((mV >= 1200) && (mV < 1225)) + voltage = SW_1_2V; + else if ((mV >= 1225) && (mV < 1250)) + voltage = SW_1_225V; + else if ((mV >= 1250) && (mV < 1275)) + voltage = SW_1_25V; + else if ((mV >= 1275) && (mV < 1300)) + voltage = SW_1_275V; + else if ((mV >= 1300) && (mV < 1325)) + voltage = SW_1_3V; + else if ((mV >= 1325) && (mV < 1350)) + voltage = SW_1_325V; + else if ((mV >= 1350) && (mV < 1375)) + voltage = SW_1_35V; + else if ((mV >= 1375) && (mV < 1400)) + voltage = SW_1_375V; + else if ((mV >= 1400) && (mV < 1425)) + voltage = SW_1_4V; + else if ((mV >= 1425) && (mV < 1450)) + voltage = SW_1_425V; + else if ((mV >= 1450) && (mV < 1475)) + voltage = SW_1_45V; + else if ((mV >= 1475) && (mV < 1500)) + voltage = SW_1_475V; + else if ((mV >= 1500) && (mV < 1525)) + voltage = SW_1_5V; + else if ((mV >= 1525) && (mV < 1550)) + voltage = SW_1_525V; + else if ((mV >= 1550) && (mV < 1575)) + voltage = SW_1_55V; + else if ((mV >= 1575) && (mV < 1600)) + voltage = SW_1_575V; + else if ((mV >= 1600) && (mV < 1625)) + voltage = SW_1_6V; + else if ((mV >= 1625) && (mV < 1650)) + voltage = SW_1_625V; + else if ((mV >= 1650) && (mV < 1675)) + voltage = SW_1_65V; + else if ((mV >= 1675) && (mV < 1700)) + voltage = SW_1_675V; + else if ((mV >= 1700) && (mV < 1800)) + voltage = SW_1_7V; + else if ((mV >= 1800) && (mV < 1850)) + voltage = SW_1_8V; + else if ((mV >= 1850) && (mV < 2000)) + voltage = SW_1_85V; + else if ((mV >= 2000) && (mV < 2100)) + voltage = SW_2V; + else if ((mV >= 2100) && (mV < 2200)) + voltage = SW_2_1V; + else + voltage = SW_2_2V; + + switch (sw) { + case MC13783_SW1A: + register1 = REG_SWITCHERS_0; + register_val = BITFVAL(SW1A_STDBY, voltage); + register_mask = BITFMASK(SW1A_STDBY); + break; + case MC13783_SW1B: + register1 = REG_SWITCHERS_1; + register_val = BITFVAL(SW1B_STDBY, voltage); + register_mask = BITFMASK(SW1B_STDBY); + break; + case MC13783_SW2A: + register1 = REG_SWITCHERS_2; + register_val = BITFVAL(SW2A_STDBY, voltage); + register_mask = BITFMASK(SW2A_STDBY); + break; + case MC13783_SW2B: + register1 = REG_SWITCHERS_3; + register_val = BITFVAL(SW2B_STDBY, voltage); + register_mask = BITFMASK(SW2B_STDBY); + break; + default: + return -EINVAL; + } + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13783_sw_get_stby_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0, sw = reg->id; + + switch (sw) { + case MC13783_SW1A: + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW1A_STDBY); + break; + case MC13783_SW1B: + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_1, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW1B_STDBY); + break; + case MC13783_SW2A: + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_2, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW2A_STDBY); + break; + case MC13783_SW2B: + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_3, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW2B_STDBY); + break; + default: + return -EINVAL; + } + + switch (voltage) { + case SW_0_9V: + mV = 900; + break; + case SW_0_925V: + mV = 925; + break; + case SW_0_95V: + mV = 950; + break; + case SW_0_975V: + mV = 975; + break; + case SW_1V: + mV = 1000; + break; + case SW_1_025V: + mV = 1025; + break; + case SW_1_05V: + mV = 1050; + break; + case SW_1_075V: + mV = 1075; + break; + case SW_1_1V: + mV = 1100; + break; + case SW_1_125V: + mV = 1125; + break; + case SW_1_15V: + mV = 1150; + break; + case SW_1_175V: + mV = 1175; + break; + case SW_1_2V: + mV = 1200; + break; + case SW_1_225V: + mV = 1225; + break; + case SW_1_25V: + mV = 1250; + break; + case SW_1_275V: + mV = 1275; + break; + case SW_1_3V: + mV = 1300; + break; + case SW_1_325V: + mV = 1325; + break; + case SW_1_35V: + mV = 1350; + break; + case SW_1_375V: + mV = 1375; + break; + case SW_1_4V: + mV = 1400; + break; + case SW_1_425V: + mV = 1425; + break; + case SW_1_45V: + mV = 1450; + break; + case SW_1_475V: + mV = 1475; + break; + case SW_1_5V: + mV = 1500; + break; + case SW_1_525V: + mV = 1525; + break; + case SW_1_55V: + mV = 1550; + break; + case SW_1_575V: + mV = 1575; + break; + case SW_1_6V: + mV = 1600; + break; + case SW_1_625V: + mV = 1625; + break; + case SW_1_65V: + mV = 1650; + break; + case SW_1_675V: + mV = 1675; + break; + case SW_1_7V: + mV = 1700; + break; + case SW_1_8V: + mV = 1800; + break; + case SW_1_85V: + mV = 1850; + break; + case SW_2V: + mV = 2000; + break; + case SW_2_1V: + mV = 2100; + break; + case SW_2_2V: + mV = 2200; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_sw_set_normal_mode(struct regulator *reg, unsigned int mode) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int register1 = 0; + unsigned int l_mode; + int sw = reg->id; + + switch (mode) { + case REGULATOR_MODE_FAST: + /* SYNC RECT mode */ + l_mode = SW_MODE_SYNC_RECT_EN; + break; + case REGULATOR_MODE_NORMAL: + /* PULSE SKIP mode */ + l_mode = SW_MODE_PULSE_SKIP_EN; + break; + case REGULATOR_MODE_IDLE: + /* LOW POWER mode */ + l_mode = SW_MODE_LOW_POWER_EN; + break; + case REGULATOR_MODE_STANDBY: + /* NO PULSE SKIP mode */ + l_mode = SW_MODE_PULSE_NO_SKIP_EN; + break; + default: + return -EINVAL; + } + + switch (sw) { + case MC13783_SW1A: + reg_val = BITFVAL(SW1A_MODE, l_mode); + reg_mask = BITFMASK(SW1A_MODE); + register1 = REG_SWITCHERS_4; + break; + case MC13783_SW1B: + reg_val = BITFVAL(SW1B_MODE, l_mode); + reg_mask = BITFMASK(SW1B_MODE); + register1 = REG_SWITCHERS_4; + break; + case MC13783_SW2A: + reg_val = BITFVAL(SW2A_MODE, l_mode); + reg_mask = BITFMASK(SW2A_MODE); + register1 = REG_SWITCHERS_5; + break; + case MC13783_SW2B: + reg_val = BITFVAL(SW2B_MODE, l_mode); + reg_mask = BITFMASK(SW2B_MODE); + register1 = REG_SWITCHERS_5; + break; + default: + return -EINVAL; + } + + return (pmic_write_reg(register1, reg_val, reg_mask)); +} + +static unsigned int mc13783_sw_get_normal_mode(struct regulator *reg) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int register1 = 0; + unsigned int l_mode = 0; + int sw = reg->id; + int ret = 0; + + switch (sw) { + case MC13783_SW1A: + reg_mask = BITFMASK(SW1A_MODE); + register1 = REG_SWITCHERS_4; + break; + case MC13783_SW1B: + reg_mask = BITFMASK(SW1B_MODE); + register1 = REG_SWITCHERS_4; + break; + case MC13783_SW2A: + reg_mask = BITFMASK(SW2A_MODE); + register1 = REG_SWITCHERS_5; + break; + case MC13783_SW2B: + reg_mask = BITFMASK(SW2B_MODE); + register1 = REG_SWITCHERS_5; + break; + default: + return -EINVAL; + } + + ret = (pmic_read_reg(register1, ®_val, reg_mask)); + if (ret != 0) + return ret; + + switch (sw) { + case MC13783_SW1A: + l_mode = BITFEXT(reg_val, SW1A_MODE); + break; + case MC13783_SW1B: + l_mode = BITFEXT(reg_val, SW1B_MODE); + break; + case MC13783_SW2A: + l_mode = BITFEXT(reg_val, SW2A_MODE); + break; + case MC13783_SW2B: + l_mode = BITFEXT(reg_val, SW2B_MODE); + break; + default: + return -EINVAL; + } + + if (l_mode == SW_MODE_SYNC_RECT_EN) { + return REGULATOR_MODE_FAST; + } else if (l_mode == SW_MODE_PULSE_NO_SKIP_EN) { + return REGULATOR_MODE_STANDBY; + } else if (l_mode == SW_MODE_PULSE_SKIP_EN) { + return REGULATOR_MODE_NORMAL; + } else if (l_mode == SW_MODE_LOW_POWER_EN) { + return REGULATOR_MODE_IDLE; + } else { + return -EINVAL; + } +} + +static int mc13783_sw_set_stby_mode(struct regulator *reg, unsigned int mode) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int register1 = 0; + unsigned int l_mode; + int sw = reg->id; + + switch (mode) { + case REGULATOR_MODE_FAST: + /* SYNC RECT mode */ + l_mode = SW_MODE_SYNC_RECT_EN; + break; + case REGULATOR_MODE_NORMAL: + /* PULSE SKIP mode */ + l_mode = SW_MODE_PULSE_SKIP_EN; + break; + case REGULATOR_MODE_IDLE: + /* LOW POWER mode */ + l_mode = SW_MODE_LOW_POWER_EN; + break; + case REGULATOR_MODE_STANDBY: + /* NO PULSE SKIP mode */ + l_mode = SW_MODE_PULSE_NO_SKIP_EN; + break; + default: + return -EINVAL; + } + + switch (sw) { + case MC13783_SW1A: + reg_val = BITFVAL(SW1A_STBY_MODE, l_mode); + reg_mask = BITFMASK(SW1A_STBY_MODE); + register1 = REG_SWITCHERS_4; + break; + case MC13783_SW1B: + reg_val = BITFVAL(SW1B_STBY_MODE, l_mode); + reg_mask = BITFMASK(SW1B_STBY_MODE); + register1 = REG_SWITCHERS_4; + break; + case MC13783_SW2A: + reg_val = BITFVAL(SW2A_STBY_MODE, l_mode); + reg_mask = BITFMASK(SW2A_STBY_MODE); + register1 = REG_SWITCHERS_5; + break; + case MC13783_SW2B: + reg_val = BITFVAL(SW2B_STBY_MODE, l_mode); + reg_mask = BITFMASK(SW2B_STBY_MODE); + register1 = REG_SWITCHERS_5; + break; + default: + return -EINVAL; + } + + return (pmic_write_reg(register1, reg_val, reg_mask)); +} + +static unsigned int mc13783_sw_get_stby_mode(struct regulator *reg) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int register1 = 0; + unsigned int l_mode = 0; + int sw = reg->id; + int ret = 0; + + switch (sw) { + case MC13783_SW1A: + reg_mask = BITFMASK(SW1A_STBY_MODE); + register1 = REG_SWITCHERS_4; + break; + case MC13783_SW1B: + reg_mask = BITFMASK(SW1B_STBY_MODE); + register1 = REG_SWITCHERS_4; + break; + case MC13783_SW2A: + reg_mask = BITFMASK(SW2A_STBY_MODE); + register1 = REG_SWITCHERS_5; + break; + case MC13783_SW2B: + reg_mask = BITFMASK(SW2B_STBY_MODE); + register1 = REG_SWITCHERS_5; + break; + default: + return -EINVAL; + } + + ret = (pmic_read_reg(register1, ®_val, reg_mask)); + if (ret != 0) + return ret; + + switch (sw) { + case MC13783_SW1A: + l_mode = BITFEXT(reg_val, SW1A_STBY_MODE); + break; + case MC13783_SW1B: + l_mode = BITFEXT(reg_val, SW1B_STBY_MODE); + break; + case MC13783_SW2A: + l_mode = BITFEXT(reg_val, SW2A_STBY_MODE); + break; + case MC13783_SW2B: + l_mode = BITFEXT(reg_val, SW2B_STBY_MODE); + break; + default: + return -EINVAL; + } + + if (l_mode == SW_MODE_SYNC_RECT_EN) { + return REGULATOR_MODE_FAST; + } else if (l_mode == SW_MODE_PULSE_NO_SKIP_EN) { + return REGULATOR_MODE_STANDBY; + } else if (l_mode == SW_MODE_PULSE_SKIP_EN) { + return REGULATOR_MODE_NORMAL; + } else if (l_mode == SW_MODE_LOW_POWER_EN) { + return REGULATOR_MODE_IDLE; + } else { + return -EINVAL; + } +} + +static struct regulator_ops mc13783_vaudio_ops = { + .enable = mc13783_vaudio_enable, + .disable = mc13783_vaudio_disable, +}; + +static struct regulator_ops mc13783_viohi_ops = { + .enable = mc13783_viohi_enable, + .disable = mc13783_viohi_disable, +}; + +static struct regulator_ops mc13783_violo_ops = { + .set_voltage = mc13783_violo_set_voltage, + .get_voltage = mc13783_violo_get_voltage, + .enable = mc13783_violo_enable, + .disable = mc13783_violo_disable, +}; + +static struct regulator_ops mc13783_vdig_ops = { + .set_voltage = mc13783_vdig_set_voltage, + .get_voltage = mc13783_vdig_get_voltage, + .enable = mc13783_vdig_enable, + .disable = mc13783_vdig_disable, +}; + +static struct regulator_ops mc13783_vgen_ops = { + .set_voltage = mc13783_vgen_set_voltage, + .get_voltage = mc13783_vgen_get_voltage, + .enable = mc13783_vgen_enable, + .disable = mc13783_vgen_disable, +}; + +static struct regulator_ops mc13783_vrfdig_ops = { + .set_voltage = mc13783_vrfdig_set_voltage, + .get_voltage = mc13783_vrfdig_get_voltage, + .enable = mc13783_vrfdig_enable, + .disable = mc13783_vrfdig_disable, +}; + +static struct regulator_ops mc13783_vrfref_ops = { + .set_voltage = mc13783_vrfref_set_voltage, + .get_voltage = mc13783_vrfref_get_voltage, + .enable = mc13783_vrfref_enable, + .disable = mc13783_vrfref_disable, +}; + +static struct regulator_ops mc13783_vrfcp_ops = { + .set_voltage = mc13783_vrfcp_set_voltage, + .get_voltage = mc13783_vrfcp_get_voltage, + .enable = mc13783_vrfcp_enable, + .disable = mc13783_vrfcp_disable, +}; + +static struct regulator_ops mc13783_vsim_ops = { + .set_voltage = mc13783_vsim_set_voltage, + .get_voltage = mc13783_vsim_get_voltage, + .enable = mc13783_vsim_enable, + .disable = mc13783_vsim_disable, +}; + +static struct regulator_ops mc13783_vesim_ops = { + .set_voltage = mc13783_vesim_set_voltage, + .get_voltage = mc13783_vesim_get_voltage, + .enable = mc13783_vesim_enable, + .disable = mc13783_vesim_disable, +}; + +static struct regulator_ops mc13783_vcam_ops = { + .set_voltage = mc13783_vcam_set_voltage, + .get_voltage = mc13783_vcam_get_voltage, + .enable = mc13783_vcam_enable, + .disable = mc13783_vcam_disable, +}; + +static struct regulator_ops mc13783_vvib_ops = { + .set_voltage = mc13783_vvib_set_voltage, + .get_voltage = mc13783_vvib_get_voltage, + .enable = mc13783_vvib_enable, + .disable = mc13783_vvib_disable, +}; + +static struct regulator_ops mc13783_vrf_ops = { + .set_voltage = mc13783_vrf_set_voltage, + .get_voltage = mc13783_vrf_get_voltage, + .enable = mc13783_vrf_enable, + .disable = mc13783_vrf_disable, +}; + +static struct regulator_ops mc13783_vmmc_ops = { + .set_voltage = mc13783_vmmc_set_voltage, + .get_voltage = mc13783_vmmc_get_voltage, + .enable = mc13783_vmmc_enable, + .disable = mc13783_vmmc_disable, +}; + +static struct regulator_ops mc13783_gpo_ops = { + .enable = mc13783_gpo_enable, + .disable = mc13783_gpo_disable, +}; + +static struct regulator_ops mc13783_sw3_ops = { + .set_voltage = mc13783_sw3_set_voltage, + .get_voltage = mc13783_sw3_get_voltage, + .enable = mc13783_sw3_enable, + .disable = mc13783_sw3_disable, +}; + +static struct regulator_ops mc13783_sw_normal_ops = { + .set_voltage = mc13783_sw_set_normal_voltage, + .get_voltage = mc13783_sw_get_normal_voltage, + .get_mode = mc13783_sw_get_normal_mode, + .set_mode = mc13783_sw_set_normal_mode, +}; + +static struct regulator_ops mc13783_sw_dvs_ops = { + .set_voltage = mc13783_sw_set_dvs_voltage, + .get_voltage = mc13783_sw_get_dvs_voltage, +}; + +static struct regulator_ops mc13783_sw_stby_ops = { + .set_voltage = mc13783_sw_set_stby_voltage, + .get_voltage = mc13783_sw_get_stby_voltage, + .get_mode = mc13783_sw_get_stby_mode, + .set_mode = mc13783_sw_set_stby_mode, +}; + +struct regulation_constraints violo_regulation_constraints = { + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +struct regulation_constraints vdig_regulation_constraints = { + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +struct regulation_constraints vgen_regulation_constraints = { + .min_uV = mV_to_uV(1100), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +struct regulation_constraints vrfdig_regulation_constraints = { + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(1875), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +struct regulation_constraints vrfref_regulation_constraints = { + .min_uV = mV_to_uV(2475), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +struct regulation_constraints vrfcp_regulation_constraints = { + .min_uV = mV_to_uV(2700), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +struct regulation_constraints vsim_regulation_constraints = { + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(2900), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +struct regulation_constraints vesim_regulation_constraints = { + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(2900), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +struct regulation_constraints vcam_regulation_constraints = { + .min_uV = mV_to_uV(1500), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +struct regulation_constraints vvib_regulation_constraints = { + .min_uV = mV_to_uV(1300), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +struct regulation_constraints vrf_regulation_constraints = { + .min_uV = mV_to_uV(1500), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +struct regulation_constraints vmmc_regulation_constraints = { + .min_uV = mV_to_uV(1600), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +struct regulation_constraints sw3_regulation_constraints = { + .min_uV = mV_to_uV(5000), + .max_uV = mV_to_uV(5500), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +struct regulation_constraints sw_regulation_constraints = { + .min_uV = mV_to_uV(900), + .max_uV = mV_to_uV(2200), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE, + .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL | + REGULATOR_MODE_IDLE | REGULATOR_MODE_STANDBY, +}; + +struct mc13783_regulator { + struct regulator regulator; +}; + +static struct mc13783_regulator reg_mc13783[NUM_MC13783_REGULATORS] = { + { + .regulator = { + .name = "VAUDIO", + .id = MC13783_VAUDIO, + .ops = &mc13783_vaudio_ops, + }, + }, + { + .regulator = { + .name = "VIOHI", + .id = MC13783_VIOHI, + .ops = &mc13783_viohi_ops, + }, + }, + { + .regulator = { + .name = "VIOLO", + .id = MC13783_VIOLO, + .ops = &mc13783_violo_ops, + .constraints = &violo_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VDIG", + .id = MC13783_VDIG, + .ops = &mc13783_vdig_ops, + .constraints = &vdig_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VGEN", + .id = MC13783_VGEN, + .ops = &mc13783_vgen_ops, + .constraints = &vgen_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VRFDIG", + .id = MC13783_VRFDIG, + .ops = &mc13783_vrfdig_ops, + .constraints = &vrfdig_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VRFREF", + .id = MC13783_VRFREF, + .ops = &mc13783_vrfref_ops, + .constraints = &vrfref_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VRFCP", + .id = MC13783_VRFCP, + .ops = &mc13783_vrfcp_ops, + .constraints = &vrfcp_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VSIM", + .id = MC13783_VSIM, + .ops = &mc13783_vsim_ops, + .constraints = &vsim_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VESIM", + .id = MC13783_VESIM, + .ops = &mc13783_vesim_ops, + .constraints = &vesim_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VCAM", + .id = MC13783_VCAM, + .ops = &mc13783_vcam_ops, + .constraints = &vcam_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VVIB", + .id = MC13783_VVIB, + .ops = &mc13783_vvib_ops, + .constraints = &vvib_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VRF1", + .id = MC13783_VRF1, + .ops = &mc13783_vrf_ops, + .constraints = &vrf_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VRF2", + .id = MC13783_VRF2, + .ops = &mc13783_vrf_ops, + .constraints = &vrf_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VMMC1", + .id = MC13783_VMMC1, + .ops = &mc13783_vmmc_ops, + .constraints = &vmmc_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VMMC2", + .id = MC13783_VMMC2, + .ops = &mc13783_vmmc_ops, + .constraints = &vmmc_regulation_constraints, + }, + }, + { + .regulator = { + .name = "GPO1", + .id = MC13783_GPO1, + .ops = &mc13783_gpo_ops, + }, + }, + { + .regulator = { + .name = "GPO2", + .id = MC13783_GPO2, + .ops = &mc13783_gpo_ops, + }, + }, + { + .regulator = { + .name = "GPO3", + .id = MC13783_GPO3, + .ops = &mc13783_gpo_ops, + }, + }, + { + .regulator = { + .name = "GPO4", + .id = MC13783_GPO4, + .ops = &mc13783_gpo_ops, + }, + }, + { + .regulator = { + .name = "SW3", + .id = MC13783_SW3, + .ops = &mc13783_sw3_ops, + .constraints = &sw3_regulation_constraints, + }, + }, + { + .regulator = { + .name = "SW1A_NORMAL", + .id = MC13783_SW1A, + .ops = &mc13783_sw_normal_ops, + .constraints = &sw_regulation_constraints, + }, + }, + { + .regulator = { + .name = "SW1B_NORMAL", + .id = MC13783_SW1B, + .ops = &mc13783_sw_normal_ops, + .constraints = &sw_regulation_constraints, + }, + }, + { + .regulator = { + .name = "SW2A_NORMAL", + .id = MC13783_SW2A, + .ops = &mc13783_sw_normal_ops, + .constraints = &sw_regulation_constraints, + }, + }, + { + .regulator = { + .name = "SW2B_NORMAL", + .id = MC13783_SW2B, + .ops = &mc13783_sw_normal_ops, + .constraints = &sw_regulation_constraints, + }, + }, + { + .regulator = { + .name = "SW1A_DVS", + .id = MC13783_SW1A, + .ops = &mc13783_sw_dvs_ops, + .constraints = &sw_regulation_constraints, + }, + }, + { + .regulator = { + .name = "SW1B_DVS", + .id = MC13783_SW1B, + .ops = &mc13783_sw_dvs_ops, + .constraints = &sw_regulation_constraints, + }, + }, + { + .regulator = { + .name = "SW2A_DVS", + .id = MC13783_SW2A, + .ops = &mc13783_sw_dvs_ops, + .constraints = &sw_regulation_constraints, + }, + }, + { + .regulator = { + .name = "SW2B_DVS", + .id = MC13783_SW2B, + .ops = &mc13783_sw_dvs_ops, + .constraints = &sw_regulation_constraints, + }, + }, + { + .regulator = { + .name = "SW1A_STBY", + .id = MC13783_SW1A, + .ops = &mc13783_sw_stby_ops, + .constraints = &sw_regulation_constraints, + }, + }, + { + .regulator = { + .name = "SW1B_STBY", + .id = MC13783_SW1B, + .ops = &mc13783_sw_stby_ops, + .constraints = &sw_regulation_constraints, + }, + }, + { + .regulator = { + .name = "SW2A_STBY", + .id = MC13783_SW2A, + .ops = &mc13783_sw_stby_ops, + .constraints = &sw_regulation_constraints, + }, + }, + { + .regulator = { + .name = "SW2B_STBY", + .id = MC13783_SW2B, + .ops = &mc13783_sw_stby_ops, + .constraints = &sw_regulation_constraints, + }, + }, +}; + +/* + * Init and Exit + */ + +int reg_mc13783_probe(void) +{ + int ret11 = 0; + int i = 0; + + for (i = 0; i < ARRAY_SIZE(reg_mc13783); i++) { + ret11 = regulator_register(®_mc13783[i].regulator); + regulator_set_platform_constraints(reg_mc13783[i].regulator. + name, + reg_mc13783[i].regulator. + constraints); + if (ret11 < 0) { + printk(KERN_ERR "%s: failed to register %s err %d\n", + __func__, reg_mc13783[i].regulator.name, ret11); + i--; + for (; i >= 0; i--) + regulator_unregister(®_mc13783[i].regulator); + + return ret11; + } + } + + printk(KERN_INFO "MC13783 regulator successfully probed\n"); + + return 0; +} + +EXPORT_SYMBOL(reg_mc13783_probe); + +/* Module information */ +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MC13783 Regulator driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/regulator/mc13892/Makefile linux-2.6.26-lab126/drivers/regulator/mc13892/Makefile --- linux-2.6.26/drivers/regulator/mc13892/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/regulator/mc13892/Makefile 2010-08-10 04:16:18.000000000 -0400 @@ -0,0 +1,5 @@ +# +# Makefile for regulator driver for MC13892. +# + +obj-$(CONFIG_REGULATOR_MC13892) += reg-mc13892.o diff -urN linux-2.6.26/drivers/regulator/mc13892/reg-mc13892.c linux-2.6.26-lab126/drivers/regulator/mc13892/reg-mc13892.c --- linux-2.6.26/drivers/regulator/mc13892/reg-mc13892.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/regulator/mc13892/reg-mc13892.c 2010-08-10 04:16:18.000000000 -0400 @@ -0,0 +1,2025 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum { + MC13892_SW1 = 0, + MC13892_SW2, + MC13892_SW3, + MC13892_SW4, + MC13892_SWBST, + MC13892_VIOHI, + MC13892_VPLL, + MC13892_VDIG, + MC13892_VSD, + MC13892_VUSB2, + MC13892_VVIDEO, + MC13892_VAUDIO, + MC13892_VCAM, + MC13892_VGEN1, + MC13892_VGEN2, + MC13892_VGEN3, + MC13892_VUSB, + MC13892_GPO1, + MC13892_GPO2, + MC13892_GPO3, + MC13892_GPO4, + MC13892_PWGT1, + MC13892_PWGT2, + MC13892_REG_NUM, +} MC13892_regulator; + +enum { + VDIG_1_05V = 0, + VDIG_1_25V, + VDIG_1_65V, + VDIG_1_80V, +} regulator_voltage_vdig; + +enum { + VPLL_1_05V = 0, + VPLL_1_25V, + VPLL_1_50V_1_65V, + VPLL_1_80V, +} regulator_voltage_vpll; + +enum { + VGEN1_1_2V = 0, + VGEN1_1_5V, + VGEN1_2_775V, + VGEN1_3_15V, +} regulator_voltage_vgen1; + +enum { + VGEN2_1_2V = 0, + VGEN2_1_5V, + VGEN2_1_6V, + VGEN2_1_8V, + VGEN2_2_7V, + VGEN2_2_8V, + VGEN2_3_0V, + VGEN2_3_15V, +} regulator_voltage_vgen2; + +enum { + VGEN3_1_8V = 0, + VGEN3_2_9V, +} regulator_voltage_vgen3; + +enum { + VSD_1_8V = 0, + VSD_2_0V, + VSD_2_6V, + VSD_2_7V, + VSD_2_8V, + VSD_2_9V, + VSD_3_0V, + VSD_3_15V, +} regulator_voltage_vsd; + +enum { + VCAM_2_5V, + VCAM_2_6V, + VCAM_2_75V, + VCAM_3_0V, +} regulator_voltage_vcam; + +enum { + VAUDIO_2_3V, + VAUDIO_2_5V, + VAUDIO_2_775V, + VAUDIO_3V, +} regulator_voltage_vaudio; + +enum { + VUSB2_2_4V, + VUSB2_2_6V, + VUSB2_2_7V, + VUSB2_2_775V, +} regulator_voltage_vusb2; + +enum { + VVIDEO_2_7V, + VVIDEO_2_775V, + VVIDEO_2_5V, + VVIDEO_2_6V, +} regulator_voltage_vvideo; + +#define STANDBYSECINV_LSH 11 +#define STANDBYSECINV_WID 1 + +#define VAUDIO_LSH 4 +#define VAUDIO_WID 2 +#define VAUDIO_EN_LSH 15 +#define VAUDIO_EN_WID 1 +#define VAUDIO_EN_ENABLE 1 +#define VAUDIO_EN_DISABLE 0 + +#define VUSB2_LSH 11 +#define VUSB2_WID 2 +#define VUSB2_EN_LSH 18 +#define VUSB2_EN_WID 1 +#define VUSB2_EN_ENABLE 1 +#define VUSB2_EN_DISABLE 0 + +#define VVIDEO_LSH 2 +#define VVIDEO_WID 2 +#define VVIDEO_EN_LSH 12 +#define VVIDEO_EN_WID 1 +#define VVIDEO_EN_ENABLE 1 +#define VVIDEO_EN_DISABLE 0 + +#define SWBST_EN_LSH 20 +#define SWBST_EN_WID 1 +#define SWBST_EN_ENABLE 1 +#define SWBST_EN_DISABLE 0 + +#define VIOHI_EN_LSH 3 +#define VIOHI_EN_WID 1 +#define VIOHI_EN_ENABLE 1 +#define VIOHI_EN_DISABLE 0 + +#define VDIG_LSH 4 +#define VDIG_WID 2 +#define VDIG_EN_LSH 9 +#define VDIG_EN_WID 1 +#define VDIG_EN_ENABLE 1 +#define VDIG_EN_DISABLE 0 + +#define VPLL_LSH 9 +#define VPLL_WID 2 +#define VPLL_EN_LSH 15 +#define VPLL_EN_WID 1 +#define VPLL_EN_ENABLE 1 +#define VPLL_EN_DISABLE 0 + +#define VGEN1_LSH 0 +#define VGEN1_WID 2 +#define VGEN1_EN_LSH 0 +#define VGEN1_EN_WID 1 +#define VGEN1_EN_ENABLE 1 +#define VGEN1_EN_DISABLE 0 + +#define VGEN2_LSH 6 +#define VGEN2_WID 3 +#define VGEN2_EN_LSH 12 +#define VGEN2_EN_WID 1 +#define VGEN2_EN_ENABLE 1 +#define VGEN2_EN_DISABLE 0 + +#define VGEN3_LSH 14 +#define VGEN3_WID 1 +#define VGEN3_EN_LSH 0 +#define VGEN3_EN_WID 1 +#define VGEN3_EN_ENABLE 1 +#define VGEN3_EN_DISABLE 0 + +#define VSD_LSH 6 +#define VSD_WID 3 +#define VSD_EN_LSH 18 +#define VSD_EN_WID 1 +#define VSD_EN_ENABLE 1 +#define VSD_EN_DISABLE 0 + +#define VCAM_LSH 16 +#define VCAM_WID 2 +#define VCAM_EN_LSH 6 +#define VCAM_EN_WID 1 +#define VCAM_EN_ENABLE 1 +#define VCAM_EN_DISABLE 0 +#define VCAM_CONFIG_LSH 9 +#define VCAM_CONFIG_WID 1 +#define VCAM_CONFIG_EXT 1 +#define VCAM_CONFIG_INT 0 + +#define SW1_LSH 0 +#define SW1_WID 5 +#define SW1_DVS_LSH 5 +#define SW1_DVS_WID 5 +#define SW1_STDBY_LSH 10 +#define SW1_STDBY_WID 5 + +#define SW2_LSH 0 +#define SW2_WID 5 +#define SW2_DVS_LSH 5 +#define SW2_DVS_WID 5 +#define SW2_STDBY_LSH 10 +#define SW2_STDBY_WID 5 + +#define SW3_LSH 0 +#define SW3_WID 5 +#define SW3_STDBY_LSH 10 +#define SW3_STDBY_WID 5 + +#define SW4_LSH 0 +#define SW4_WID 5 +#define SW4_STDBY_LSH 10 +#define SW4_STDBY_WID 5 + +#define VUSB_EN_LSH 3 +#define VUSB_EN_WID 1 +#define VUSB_EN_ENABLE 1 +#define VUSB_EN_DISABLE 0 + +#define GPO1_EN_LSH 6 +#define GPO1_EN_WID 1 +#define GPO1_EN_ENABLE 1 +#define GPO1_EN_DISABLE 0 + +#define GPO2_EN_LSH 8 +#define GPO2_EN_WID 1 +#define GPO2_EN_ENABLE 1 +#define GPO2_EN_DISABLE 0 + +#define GPO3_EN_LSH 10 +#define GPO3_EN_WID 1 +#define GPO3_EN_ENABLE 1 +#define GPO3_EN_DISABLE 0 + +#define GPO4_EN_LSH 12 +#define GPO4_EN_WID 1 +#define GPO4_EN_ENABLE 1 +#define GPO4_EN_DISABLE 0 + +#define GPO4_ADIN_LSH 21 +#define GPO4_ADIN_WID 1 +#define GPO4_ADIN_ENABLE 1 +#define GPO4_ADIN_DISABLE 0 + +#define PWGT1SPI_EN_LSH 15 +#define PWGT1SPI_EN_WID 1 +#define PWGT1SPI_EN_ENABLE 0 +#define PWGT1SPI_EN_DISABLE 1 + +#define PWGT2SPI_EN_LSH 16 +#define PWGT2SPI_EN_WID 1 +#define PWGT2SPI_EN_ENABLE 0 +#define PWGT2SPI_EN_DISABLE 1 + +#define SWXHI_LSH 23 +#define SWXHI_WID 1 +#define SWXHI_ON 1 +#define SWXHI_OFF 0 + +void pmic_get_revision(pmic_version_t *ver); +static unsigned int mc13892_revision; + +static int mc13892_get_sw_hi_bit(int sw) +{ + unsigned int register_val = 0; + unsigned int reg = 0; + + switch (sw) { + case MC13892_SW1: + reg = REG_SW_0; + break; + case MC13892_SW2: + reg = REG_SW_1; + break; + case MC13892_SW3: + reg = REG_SW_2; + break; + case MC13892_SW4: + reg = REG_SW_3; + break; + default: + return -EINVAL; + } + + CHECK_ERROR(pmic_read_reg(reg, ®ister_val, PMIC_ALL_BITS)); + return ((register_val & 0x800000) >> SWXHI_LSH); +} + +static int mc13892_get_voltage_value(int *hi, int mV) +{ + int voltage; + + if (mV < 600) + mV = 600; + if (mV > 1850) + mV = 1850; + + if (mV > 1375) + *hi = 1; + if (mV < 1100) + *hi = 0; + + if (*hi == 0) + voltage = (mV - 600) / 25; + else + voltage = (mV - 1100) / 25; + + return voltage; +} + +static int mc13892_get_voltage_mV(int hi, int voltage) +{ + int mV; + + if (hi == 0) + mV = voltage * 25 + 600; + else + mV = voltage * 25 + 1100; + + return mV; +} + +static int mc13892_sw_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1 = 0; + int voltage, sw = reg->id, mV = uV / 1000, hi; + + hi = mc13892_get_sw_hi_bit(sw); + voltage = mc13892_get_voltage_value(&hi, mV); + + switch (sw) { + case MC13892_SW1: + register1 = REG_SW_0; + register_val = BITFVAL(SW1, voltage); + register_mask = BITFMASK(SW1); + break; + case MC13892_SW2: + register1 = REG_SW_1; + register_val = BITFVAL(SW2, voltage); + register_mask = BITFMASK(SW2); + break; + case MC13892_SW3: + register1 = REG_SW_2; + register_val = BITFVAL(SW3, voltage); + register_mask = BITFMASK(SW3); + break; + case MC13892_SW4: + register1 = REG_SW_3; + register_val = BITFVAL(SW4, voltage); + register_mask = BITFMASK(SW4); + break; + default: + return -EINVAL; + } + + register_val |= (hi << SWXHI_LSH); + register_mask |= (1 << SWXHI_LSH); + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_sw_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0, sw = reg->id, hi; + + switch (sw) { + case MC13892_SW1: + CHECK_ERROR(pmic_read_reg(REG_SW_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW1); + break; + case MC13892_SW2: + CHECK_ERROR(pmic_read_reg(REG_SW_1, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW2); + break; + case MC13892_SW3: + CHECK_ERROR(pmic_read_reg(REG_SW_2, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW3); + break; + case MC13892_SW4: + CHECK_ERROR(pmic_read_reg(REG_SW_3, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW4); + break; + default: + return -EINVAL; + } + + hi = mc13892_get_sw_hi_bit(sw); + mV = mc13892_get_voltage_mV(hi, voltage); + + return mV; +} + +static int mc13892_sw_stby_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1 = 0; + int voltage, sw = reg->id, mV = uV / 1000, hi; + hi = mc13892_get_sw_hi_bit(sw); + voltage = mc13892_get_voltage_value(&hi, mV); + switch (sw) { + case MC13892_SW1: + register1 = REG_SW_0; + register_val = BITFVAL(SW1_STDBY, voltage); + register_mask = BITFMASK(SW1_STDBY); + break; + case MC13892_SW2: + register1 = REG_SW_1; + register_val = BITFVAL(SW2_STDBY, voltage); + register_mask = BITFMASK(SW2_STDBY); + break; + case MC13892_SW3: + register1 = REG_SW_2; + register_val = BITFVAL(SW3_STDBY, voltage); + register_mask = BITFMASK(SW3_STDBY); + break; + case MC13892_SW4: + register1 = REG_SW_3; + register_val = BITFVAL(SW4_STDBY, voltage); + register_mask = BITFMASK(SW4_STDBY); + break; + default: + return -EINVAL; + } + register_val |= (hi << SWXHI_LSH); + register_mask |= (1 << SWXHI_LSH); + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_sw_stby_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0, sw = reg->id, hi; + + switch (sw) { + case MC13892_SW1: + CHECK_ERROR(pmic_read_reg(REG_SW_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW1_STDBY); + break; + case MC13892_SW2: + CHECK_ERROR(pmic_read_reg(REG_SW_1, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW2_STDBY); + break; + case MC13892_SW3: + CHECK_ERROR(pmic_read_reg(REG_SW_2, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW3_STDBY); + break; + case MC13892_SW4: + CHECK_ERROR(pmic_read_reg(REG_SW_3, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW4_STDBY); + break; + default: + return -EINVAL; + } + + hi = mc13892_get_sw_hi_bit(sw); + mV = mc13892_get_voltage_mV(hi, voltage); + + return mV; +} + +static int mc13892_sw_dvs_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1 = 0; + int voltage, sw = reg->id, mV = uV / 1000, hi; + + hi = mc13892_get_sw_hi_bit(sw); + voltage = mc13892_get_voltage_value(&hi, mV); + + switch (sw) { + case MC13892_SW1: + register1 = REG_SW_0; + register_val = BITFVAL(SW1_DVS, voltage); + register_mask = BITFMASK(SW1_DVS); + break; + case MC13892_SW2: + register1 = REG_SW_1; + register_val = BITFVAL(SW2_DVS, voltage); + register_mask = BITFMASK(SW2_DVS); + break; + default: + return -EINVAL; + } + + register_val |= (hi << SWXHI_LSH); + register_mask |= (1 << SWXHI_LSH); + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_sw_dvs_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0, sw = reg->id, hi; + + switch (sw) { + case MC13892_SW1: + CHECK_ERROR(pmic_read_reg(REG_SW_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW1_DVS); + break; + case MC13892_SW2: + CHECK_ERROR(pmic_read_reg(REG_SW_1, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW2_DVS); + break; + default: + return -EINVAL; + } + + hi = mc13892_get_sw_hi_bit(sw); + mV = mc13892_get_voltage_mV(hi, voltage); + + return mV; +} + +static int mc13892_swbst_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(SWBST_EN, SWBST_EN_ENABLE); + register_mask = BITFMASK(SWBST_EN); + register1 = REG_SW_5; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_swbst_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(SWBST_EN, SWBST_EN_DISABLE); + register_mask = BITFMASK(SWBST_EN); + register1 = REG_SW_5; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_viohi_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VIOHI_EN, VIOHI_EN_ENABLE); + register_mask = BITFMASK(VIOHI_EN); + register1 = REG_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_viohi_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VIOHI_EN, VIOHI_EN_DISABLE); + register_mask = BITFMASK(VIOHI_EN); + register1 = REG_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vusb_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VUSB_EN, VUSB_EN_ENABLE); + register_mask = BITFMASK(VUSB_EN); + register1 = REG_USB1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vusb_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VUSB_EN, VUSB_EN_DISABLE); + register_mask = BITFMASK(VUSB_EN); + register1 = REG_USB1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vdig_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1050) && (mV < 1250)) + voltage = VDIG_1_05V; + else if ((mV >= 1250) && (mV < 1650)) + voltage = VDIG_1_25V; + else if ((mV >= 1650) && (mV < 1800)) + voltage = VDIG_1_65V; + else + voltage = VDIG_1_80V; + + register_val = BITFVAL(VDIG, voltage); + register_mask = BITFMASK(VDIG); + register1 = REG_SETTING_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vdig_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_0, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VDIG); + + switch (voltage) { + case VDIG_1_05V: + mV = 1050; + break; + case VDIG_1_25V: + mV = 1250; + break; + case VDIG_1_65V: + mV = 1650; + break; + case VDIG_1_80V: + mV = 1800; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vdig_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VDIG_EN, VDIG_EN_ENABLE); + register_mask = BITFMASK(VDIG_EN); + register1 = REG_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vdig_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VDIG_EN, VDIG_EN_DISABLE); + register_mask = BITFMASK(VDIG_EN); + register1 = REG_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vpll_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, volt_rev, mV = uV / 1000; + + if (mc13892_revision >= 20) + volt_rev = 1500; + else + volt_rev = 1650; + + if ((mV >= 1050) && (mV < 1250)) + voltage = VPLL_1_05V; + else if ((mV >= 1250) && (mV < volt_rev)) + voltage = VPLL_1_25V; + else if ((mV >= volt_rev) && (mV < 1800)) + voltage = VPLL_1_50V_1_65V; + else + voltage = VPLL_1_80V; + + register_val = BITFVAL(VPLL, voltage); + register_mask = BITFMASK(VPLL); + register1 = REG_SETTING_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vpll_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int volt_rev, voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_0, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VPLL); + + if (mc13892_revision >= 20) + volt_rev = 1500; + else + volt_rev = 1650; + + switch (voltage) { + case VPLL_1_05V: + mV = 1050; + break; + case VPLL_1_25V: + mV = 1250; + break; + case VPLL_1_50V_1_65V: + mV = volt_rev; + break; + case VPLL_1_80V: + mV = 1800; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vpll_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VPLL_EN, VPLL_EN_ENABLE); + register_mask = BITFMASK(VPLL_EN); + register1 = REG_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vpll_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VPLL_EN, VPLL_EN_DISABLE); + register_mask = BITFMASK(VPLL_EN); + register1 = REG_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vaudio_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 2300) && (mV < 2500)) + voltage = VAUDIO_2_3V; + else if ((mV >= 2500) && (mV < 2775)) + voltage = VAUDIO_2_5V; + else if ((mV >= 2775) && (mV < 3000)) + voltage = VAUDIO_2_775V; + else + voltage = VAUDIO_3V; + + register_val = BITFVAL(VAUDIO, voltage); + register_mask = BITFMASK(VAUDIO); + register1 = REG_SETTING_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vaudio_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_1, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VAUDIO); + + switch (voltage) { + case VAUDIO_2_3V: + mV = 2300; + break; + case VAUDIO_2_5V: + mV = 2500; + break; + case VAUDIO_2_775V: + mV = 2775; + break; + case VAUDIO_3V: + mV = 3000; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vaudio_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VAUDIO_EN, VAUDIO_EN_ENABLE); + register_mask = BITFMASK(VAUDIO_EN); + register1 = REG_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vaudio_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VAUDIO_EN, VAUDIO_EN_DISABLE); + register_mask = BITFMASK(VAUDIO_EN); + register1 = REG_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vusb2_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 2400) && (mV < 2600)) + voltage = VUSB2_2_4V; + else if ((mV >= 2600) && (mV < 2700)) + voltage = VUSB2_2_6V; + else if ((mV >= 2700) && (mV < 2775)) + voltage = VUSB2_2_7V; + else + voltage = VUSB2_2_775V; + + register_val = BITFVAL(VUSB2, voltage); + register_mask = BITFMASK(VUSB2); + register1 = REG_SETTING_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vusb2_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_0, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VUSB2); + + switch (voltage) { + case VUSB2_2_4V: + mV = 2400; + break; + case VUSB2_2_6V: + mV = 2600; + break; + case VUSB2_2_7V: + mV = 2700; + break; + case VUSB2_2_775V: + mV = 2775; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vusb2_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VUSB2_EN, VUSB2_EN_ENABLE); + register_mask = BITFMASK(VUSB2_EN); + register1 = REG_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vusb2_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VUSB2_EN, VUSB2_EN_DISABLE); + register_mask = BITFMASK(VUSB2_EN); + register1 = REG_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vvideo_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 2500) && (mV < 2600)) + voltage = VVIDEO_2_5V; + else if ((mV >= 2600) && (mV < 2700)) + voltage = VVIDEO_2_6V; + else if ((mV >= 2700) && (mV < 2775)) + voltage = VVIDEO_2_7V; + else + voltage = VVIDEO_2_775V; + + register_val = BITFVAL(VVIDEO, voltage); + register_mask = BITFMASK(VVIDEO); + register1 = REG_SETTING_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vvideo_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_1, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VVIDEO); + + switch (voltage) { + case VVIDEO_2_5V: + mV = 2500; + break; + case VVIDEO_2_6V: + mV = 2600; + break; + case VVIDEO_2_7V: + mV = 2700; + break; + case VVIDEO_2_775V: + mV = 2775; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vvideo_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VVIDEO_EN, VVIDEO_EN_ENABLE); + register_mask = BITFMASK(VVIDEO_EN); + register1 = REG_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vvideo_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VVIDEO_EN, VVIDEO_EN_DISABLE); + register_mask = BITFMASK(VVIDEO_EN); + register1 = REG_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vsd_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1800) && (mV < 2000)) + voltage = VSD_1_8V; + else if ((mV >= 2000) && (mV < 2600)) + voltage = VSD_2_0V; + else if ((mV >= 2600) && (mV < 2700)) + voltage = VSD_2_6V; + else if ((mV >= 2700) && (mV < 2800)) + voltage = VSD_2_7V; + else if ((mV >= 2800) && (mV < 2900)) + voltage = VSD_2_8V; + else if ((mV >= 2900) && (mV < 3000)) + voltage = VSD_2_9V; + else if ((mV >= 3000) && (mV < 3150)) + voltage = VSD_3_0V; + else + voltage = VSD_3_15V; + + register_val = BITFVAL(VSD, voltage); + register_mask = BITFMASK(VSD); + register1 = REG_SETTING_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vsd_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_1, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VSD); + + switch (voltage) { + case VSD_1_8V: + mV = 1800; + break; + case VSD_2_0V: + mV = 2000; + break; + case VSD_2_6V: + mV = 2600; + break; + case VSD_2_7V: + mV = 2700; + break; + case VSD_2_8V: + mV = 2800; + break; + case VSD_2_9V: + mV = 2900; + break; + case VSD_3_0V: + mV = 3000; + break; + case VSD_3_15V: + mV = 3150; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vsd_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VSD_EN, VSD_EN_ENABLE); + register_mask = BITFMASK(VSD_EN); + register1 = REG_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vsd_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VSD_EN, VSD_EN_DISABLE); + register_mask = BITFMASK(VSD_EN); + register1 = REG_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vcam_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 2500) && (mV < 2600)) + voltage = VCAM_2_5V; + else if ((mV >= 2600) && (mV < 2750)) + voltage = VCAM_2_6V; + else if ((mV >= 2750) && (mV < 3000)) + voltage = VCAM_2_75V; + else + voltage = VCAM_3_0V; + + register_val = BITFVAL(VCAM, voltage); + register_mask = BITFMASK(VCAM); + register1 = REG_SETTING_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vcam_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_0, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VCAM); + + switch (voltage) { + case VCAM_2_5V: + mV = 2500; + break; + case VCAM_2_6V: + mV = 2600; + break; + case VCAM_2_75V: + mV = 2750; + break; + case VCAM_3_0V: + mV = 3000; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vcam_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VCAM_EN, VCAM_EN_ENABLE); + register_mask = BITFMASK(VCAM_EN); + register1 = REG_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vcam_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VCAM_EN, VCAM_EN_DISABLE); + register_mask = BITFMASK(VCAM_EN); + register1 = REG_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vcam_set_mode(struct regulator *reg, unsigned int mode) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + switch (mode) { + case REGULATOR_MODE_FAST: + register_val = BITFVAL(VCAM_CONFIG, VCAM_CONFIG_EXT); + break; + case REGULATOR_MODE_NORMAL: + register_val = BITFVAL(VCAM_CONFIG, VCAM_CONFIG_INT); + break; + default: + return -EINVAL; + } + register_mask = BITFMASK(VCAM_CONFIG); + register1 = REG_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +unsigned int mc13892_vcam_get_mode(struct regulator *reg) +{ + unsigned int register_val = 0; + int config = 0, mode = VCAM_CONFIG_INT; + + CHECK_ERROR(pmic_read_reg(REG_MODE_1, ®ister_val, PMIC_ALL_BITS)); + config = BITFEXT(register_val, VCAM_CONFIG); + + switch (config) { + case VCAM_CONFIG_EXT: + mode = REGULATOR_MODE_FAST; + break; + case VCAM_CONFIG_INT: + mode = REGULATOR_MODE_NORMAL; + break; + default: + return -EINVAL; + } + return mode; +} + +static int mc13892_vgen1_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1200) && (mV < 1500)) + voltage = VGEN1_1_2V; + else if ((mV >= 1500) && (mV < 2775)) + voltage = VGEN1_1_5V; + else if ((mV >= 2775) && (mV < 3150)) + voltage = VGEN1_2_775V; + else + voltage = VGEN1_3_15V; + + register_val = BITFVAL(VGEN1, voltage); + register_mask = BITFMASK(VGEN1); + register1 = REG_SETTING_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vgen1_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_0, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VGEN1); + + switch (voltage) { + case VGEN1_1_2V: + mV = 1200; + break; + case VGEN1_1_5V: + mV = 1500; + break; + case VGEN1_2_775V: + mV = 2775; + break; + case VGEN1_3_15V: + mV = 3150; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vgen1_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VGEN1_EN, VGEN1_EN_ENABLE); + register_mask = BITFMASK(VGEN1_EN); + register1 = REG_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vgen1_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VGEN1_EN, VGEN1_EN_DISABLE); + register_mask = BITFMASK(VGEN1_EN); + register1 = REG_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vgen2_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1200) && (mV < 1500)) + voltage = VGEN2_1_2V; + else if ((mV >= 1500) && (mV < 1600)) + voltage = VGEN2_1_5V; + else if ((mV >= 1600) && (mV < 1800)) + voltage = VGEN2_1_6V; + else if ((mV >= 1800) && (mV < 2700)) + voltage = VGEN2_1_8V; + else if ((mV >= 2700) && (mV < 2800)) + voltage = VGEN2_2_7V; + else if ((mV >= 2800) && (mV < 3000)) + voltage = VGEN2_2_8V; + else if ((mV >= 3000) && (mV < 3150)) + voltage = VGEN2_3_0V; + else + voltage = VGEN2_3_15V; + + register_val = BITFVAL(VGEN2, voltage); + register_mask = BITFMASK(VGEN2); + register1 = REG_SETTING_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vgen2_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_0, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VGEN2); + + switch (voltage) { + case VGEN2_1_2V: + mV = 1200; + break; + case VGEN2_1_5V: + mV = 1500; + break; + case VGEN2_1_6V: + mV = 1600; + break; + case VGEN2_1_8V: + mV = 1800; + break; + case VGEN2_2_7V: + mV = 2700; + break; + case VGEN2_2_8V: + mV = 2800; + break; + case VGEN2_3_0V: + mV = 3000; + break; + case VGEN2_3_15V: + mV = 3150; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vgen2_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VGEN2_EN, VGEN2_EN_ENABLE); + register_mask = BITFMASK(VGEN2_EN); + register1 = REG_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vgen2_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VGEN2_EN, VGEN2_EN_DISABLE); + register_mask = BITFMASK(VGEN2_EN); + register1 = REG_MODE_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vgen3_set_voltage(struct regulator *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1800) && (mV < 2900)) + voltage = VGEN3_1_8V; + else + voltage = VGEN3_2_9V; + + register_val = BITFVAL(VGEN3, voltage); + register_mask = BITFMASK(VGEN3); + register1 = REG_SETTING_0; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vgen3_get_voltage(struct regulator *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_0, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VGEN3); + + switch (voltage) { + case VGEN3_1_8V: + mV = 1800; + break; + case VGEN3_2_9V: + mV = 2900; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vgen3_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VGEN3_EN, VGEN3_EN_ENABLE); + register_mask = BITFMASK(VGEN3_EN); + register1 = REG_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_vgen3_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VGEN3_EN, VGEN3_EN_DISABLE); + register_mask = BITFMASK(VGEN3_EN); + register1 = REG_MODE_1; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_gpo_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int gpo = reg->id; + + switch (gpo) { + case MC13892_GPO1: + register_val = BITFVAL(GPO1_EN, GPO1_EN_ENABLE); + register_mask = BITFMASK(GPO1_EN); + break; + case MC13892_GPO2: + register_val = BITFVAL(GPO2_EN, GPO2_EN_ENABLE); + register_mask = BITFMASK(GPO2_EN); + break; + case MC13892_GPO3: + register_val = BITFVAL(GPO3_EN, GPO3_EN_ENABLE); + register_mask = BITFMASK(GPO3_EN); + break; + case MC13892_GPO4: + register_val = BITFVAL(GPO4_EN, GPO4_EN_ENABLE) + + BITFVAL(GPO4_ADIN, GPO4_ADIN_DISABLE); + register_mask = BITFMASK(GPO4_EN) + BITFMASK(GPO4_ADIN); + break; + default: + return -EINVAL; + }; + + register1 = REG_POWER_MISC; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_gpo_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int gpo = reg->id; + + switch (gpo) { + case MC13892_GPO1: + register_val = BITFVAL(GPO1_EN, GPO1_EN_DISABLE); + register_mask = BITFMASK(GPO1_EN); + break; + case MC13892_GPO2: + register_val = BITFVAL(GPO2_EN, GPO2_EN_DISABLE); + register_mask = BITFMASK(GPO2_EN); + break; + case MC13892_GPO3: + register_val = BITFVAL(GPO3_EN, GPO3_EN_DISABLE); + register_mask = BITFMASK(GPO3_EN); + break; + case MC13892_GPO4: + register_val = BITFVAL(GPO4_EN, GPO4_EN_DISABLE); + register_mask = BITFMASK(GPO4_EN); + break; + default: + return -EINVAL; + }; + + register1 = REG_POWER_MISC; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_power_gating_enable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int gpo = reg->id; + + switch (gpo) { + case MC13892_PWGT1: + register_val = BITFVAL(PWGT1SPI_EN, PWGT1SPI_EN_ENABLE); + register_mask = BITFMASK(PWGT1SPI_EN); + break; + case MC13892_PWGT2: + register_val = BITFVAL(PWGT2SPI_EN, PWGT2SPI_EN_ENABLE); + register_mask = BITFMASK(PWGT2SPI_EN); + break; + default: + return -EINVAL; + }; + + register1 = REG_POWER_MISC; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static int mc13892_power_gating_disable(struct regulator *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int gpo = reg->id; + + switch (gpo) { + case MC13892_PWGT1: + register_val = BITFVAL(PWGT1SPI_EN, PWGT1SPI_EN_DISABLE); + register_mask = BITFMASK(PWGT1SPI_EN); + break; + case MC13892_PWGT2: + register_val = BITFVAL(PWGT2SPI_EN, PWGT2SPI_EN_DISABLE); + register_mask = BITFMASK(PWGT2SPI_EN); + break; + default: + return -EINVAL; + }; + + register1 = REG_POWER_MISC; + + return (pmic_write_reg(register1, register_val, register_mask)); +} + +static struct regulator_ops mc13892_sw_ops = { + .set_voltage = mc13892_sw_set_voltage, + .get_voltage = mc13892_sw_get_voltage, +}; + +struct regulation_constraints sw1_constraints = { + .min_uV = mV_to_uV(600), + .max_uV = mV_to_uV(1375), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +struct regulation_constraints sw_constraints = { + .min_uV = mV_to_uV(1100), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +static struct regulator_ops mc13892_sw_stby_ops = { + .set_voltage = mc13892_sw_stby_set_voltage, + .get_voltage = mc13892_sw_stby_get_voltage, +}; + +struct regulation_constraints sw_stby_constraints = { + .min_uV = mV_to_uV(600), + .max_uV = mV_to_uV(1375), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +static struct regulator_ops mc13892_sw_dvs_ops = { + .set_voltage = mc13892_sw_dvs_set_voltage, + .get_voltage = mc13892_sw_dvs_get_voltage, +}; + +static struct regulator_ops mc13892_swbst_ops = { + .enable = mc13892_swbst_enable, + .disable = mc13892_swbst_disable, +}; + +static struct regulator_ops mc13892_viohi_ops = { + .enable = mc13892_viohi_enable, + .disable = mc13892_viohi_disable, +}; + +static struct regulator_ops mc13892_vusb_ops = { + .enable = mc13892_vusb_enable, + .disable = mc13892_vusb_disable, +}; + +static struct regulator_ops mc13892_vdig_ops = { + .set_voltage = mc13892_vdig_set_voltage, + .get_voltage = mc13892_vdig_get_voltage, + .enable = mc13892_vdig_enable, + .disable = mc13892_vdig_disable, +}; + +struct regulation_constraints vdig_regulation_constraints = { + .min_uV = mV_to_uV(1050), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +static struct regulator_ops mc13892_vpll_ops = { + .set_voltage = mc13892_vpll_set_voltage, + .get_voltage = mc13892_vpll_get_voltage, + .enable = mc13892_vpll_enable, + .disable = mc13892_vpll_disable, +}; + +struct regulation_constraints vpll_regulation_constraints = { + .min_uV = mV_to_uV(1050), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +static struct regulator_ops mc13892_vusb2_ops = { + .set_voltage = mc13892_vusb2_set_voltage, + .get_voltage = mc13892_vusb2_get_voltage, + .enable = mc13892_vusb2_enable, + .disable = mc13892_vusb2_disable, +}; + +struct regulation_constraints vusb2_regulation_constraints = { + .min_uV = mV_to_uV(2400), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +static struct regulator_ops mc13892_vvideo_ops = { + .set_voltage = mc13892_vvideo_set_voltage, + .get_voltage = mc13892_vvideo_get_voltage, + .enable = mc13892_vvideo_enable, + .disable = mc13892_vvideo_disable, +}; + +struct regulation_constraints vvideo_regulation_constraints = { + .min_uV = mV_to_uV(2500), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +static struct regulator_ops mc13892_vaudio_ops = { + .set_voltage = mc13892_vaudio_set_voltage, + .get_voltage = mc13892_vaudio_get_voltage, + .enable = mc13892_vaudio_enable, + .disable = mc13892_vaudio_disable, +}; + +struct regulation_constraints vaudio_regulation_constraints = { + .min_uV = mV_to_uV(2300), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +static struct regulator_ops mc13892_vsd_ops = { + .set_voltage = mc13892_vsd_set_voltage, + .get_voltage = mc13892_vsd_get_voltage, + .enable = mc13892_vsd_enable, + .disable = mc13892_vsd_disable, +}; + +struct regulation_constraints vsd_regulation_constraints = { + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +static struct regulator_ops mc13892_vcam_ops = { + .set_voltage = mc13892_vcam_set_voltage, + .get_voltage = mc13892_vcam_get_voltage, + .enable = mc13892_vcam_enable, + .disable = mc13892_vcam_disable, + .set_mode = mc13892_vcam_set_mode, + .get_mode = mc13892_vcam_get_mode, +}; + +struct regulation_constraints vcam_regulation_constraints = { + .min_uV = mV_to_uV(2500), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE, + .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, +}; + +static struct regulator_ops mc13892_vgen1_ops = { + .set_voltage = mc13892_vgen1_set_voltage, + .get_voltage = mc13892_vgen1_get_voltage, + .enable = mc13892_vgen1_enable, + .disable = mc13892_vgen1_disable, +}; + +struct regulation_constraints vgen1_regulation_constraints = { + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +static struct regulator_ops mc13892_vgen2_ops = { + .set_voltage = mc13892_vgen2_set_voltage, + .get_voltage = mc13892_vgen2_get_voltage, + .enable = mc13892_vgen2_enable, + .disable = mc13892_vgen2_disable, +}; + +struct regulation_constraints vgen2_regulation_constraints = { + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +static struct regulator_ops mc13892_vgen3_ops = { + .set_voltage = mc13892_vgen3_set_voltage, + .get_voltage = mc13892_vgen3_get_voltage, + .enable = mc13892_vgen3_enable, + .disable = mc13892_vgen3_disable, +}; + +struct regulation_constraints vgen3_regulation_constraints = { + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(2900), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +static struct regulator_ops mc13892_gpo_ops = { + .enable = mc13892_gpo_enable, + .disable = mc13892_gpo_disable, +}; + +static struct regulator_ops mc13892_power_gating_ops = { + .enable = mc13892_power_gating_enable, + .disable = mc13892_power_gating_disable, + +}; +struct mc13892_regulator { + struct regulator regulator; +}; + +static struct mc13892_regulator reg_mc13892[] = { + { + .regulator = { + .name = "SW1", + .id = MC13892_SW1, + .ops = &mc13892_sw_ops, + .constraints = &sw1_constraints, + }, + }, + { + .regulator = { + .name = "SW2", + .id = MC13892_SW2, + .ops = &mc13892_sw_ops, + .constraints = &sw_constraints, + }, + }, + { + .regulator = { + .name = "SW3", + .id = MC13892_SW3, + .ops = &mc13892_sw_ops, + .constraints = &sw_constraints, + }, + }, + { + .regulator = { + .name = "SW4", + .id = MC13892_SW4, + .ops = &mc13892_sw_ops, + .constraints = &sw_constraints, + }, + }, + { + .regulator = { + .name = "SW1_STBY", + .id = MC13892_SW1, + .ops = &mc13892_sw_stby_ops, + .constraints = &sw_stby_constraints, + }, + }, + { + .regulator = { + .name = "SW2_STBY", + .id = MC13892_SW2, + .ops = &mc13892_sw_stby_ops, + .constraints = &sw_stby_constraints, + }, + }, + { + .regulator = { + .name = "SW3_STBY", + .id = MC13892_SW3, + .ops = &mc13892_sw_stby_ops, + .constraints = &sw_stby_constraints, + }, + }, + { + .regulator = { + .name = "SW4_STBY", + .id = MC13892_SW4, + .ops = &mc13892_sw_stby_ops, + .constraints = &sw_stby_constraints, + }, + }, + { + .regulator = { + .name = "SW1_DVS", + .id = MC13892_SW1, + .ops = &mc13892_sw_dvs_ops, + .constraints = &sw_constraints, + }, + }, + { + .regulator = { + .name = "SW2_DVS", + .id = MC13892_SW2, + .ops = &mc13892_sw_dvs_ops, + .constraints = &sw_constraints, + }, + }, + { + .regulator = { + .name = "SWBST", + .id = MC13892_SWBST, + .ops = &mc13892_swbst_ops, + }, + }, + { + .regulator = { + .name = "VIOHI", + .id = MC13892_VIOHI, + .ops = &mc13892_viohi_ops, + }, + }, + { + .regulator = { + .name = "VPLL", + .id = MC13892_VPLL, + .ops = &mc13892_vpll_ops, + .constraints = &vpll_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VDIG", + .id = MC13892_VDIG, + .ops = &mc13892_vdig_ops, + .constraints = &vdig_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VSD", + .id = MC13892_VSD, + .ops = &mc13892_vsd_ops, + .constraints = &vsd_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VUSB2", + .id = MC13892_VUSB2, + .ops = &mc13892_vusb2_ops, + .constraints = &vusb2_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VVIDEO", + .id = MC13892_VVIDEO, + .ops = &mc13892_vvideo_ops, + .constraints = &vvideo_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VAUDIO", + .id = MC13892_VAUDIO, + .ops = &mc13892_vaudio_ops, + .constraints = &vaudio_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VCAM", + .id = MC13892_VCAM, + .ops = &mc13892_vcam_ops, + .constraints = &vcam_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VGEN1", + .id = MC13892_VGEN1, + .ops = &mc13892_vgen1_ops, + .constraints = &vgen1_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VGEN2", + .id = MC13892_VGEN2, + .ops = &mc13892_vgen2_ops, + .constraints = &vgen2_regulation_constraints, + }, + }, + { + .regulator = { + .name = "VGEN3", + .id = MC13892_VGEN3, + .ops = &mc13892_vgen3_ops, + .constraints = &vgen3_regulation_constraints, + }, + }, + { + .regulator = { + .name = "USB", + .id = MC13892_VUSB, + .ops = &mc13892_vusb_ops, + }, + }, + { + .regulator = { + .name = "GPO1", + .id = MC13892_GPO1, + .ops = &mc13892_gpo_ops, + }, + }, + { + .regulator = { + .name = "GPO2", + .id = MC13892_GPO2, + .ops = &mc13892_gpo_ops, + }, + }, + { + .regulator = { + .name = "GPO3", + .id = MC13892_GPO3, + .ops = &mc13892_gpo_ops, + }, + }, + { + .regulator = { + .name = "GPO4", + .id = MC13892_GPO4, + .ops = &mc13892_gpo_ops, + }, + }, + { + .regulator = { + .name = "PWGT1", + .id = MC13892_PWGT1, + .ops = &mc13892_power_gating_ops, + }, + }, + { + .regulator = { + .name = "PWGT2", + .id = MC13892_PWGT2, + .ops = &mc13892_power_gating_ops, + }, + }, +}; + +int reg_mc13892_probe(void) +{ + pmic_version_t ver; + int ret11 = 0; + int i = 0; + int register_val = 0, register_mask = 0; + + for (i = 0; i < ARRAY_SIZE(reg_mc13892); i++) { + ret11 = regulator_register(®_mc13892[i].regulator); + regulator_set_platform_constraints(reg_mc13892[i].regulator. + name, + reg_mc13892[i].regulator. + constraints); + + if (ret11 < 0) { + printk(KERN_ERR "%s: failed to register %s err %d\n", + __func__, reg_mc13892[i].regulator.name, ret11); + i--; + for (; i >= 0; i--) + regulator_unregister(®_mc13892[i].regulator); + + return ret11; + } + } + + pmic_get_revision(&ver); + mc13892_revision = ver.revision; + + /* Set the STANDBYSECINV bit, so that STANDBY pin is + * interpreted as active low. + */ + register_val = BITFVAL(STANDBYSECINV, 1); + register_mask = BITFMASK(STANDBYSECINV); + pmic_write_reg(REG_POWER_CTL2, register_val, register_mask); + printk(KERN_INFO "MC13892 regulator successfully probed\n"); + + return 0; +} + +EXPORT_SYMBOL(reg_mc13892_probe); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MC13892 Regulator driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/regulator/mc34704/Makefile linux-2.6.26-lab126/drivers/regulator/mc34704/Makefile --- linux-2.6.26/drivers/regulator/mc34704/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/regulator/mc34704/Makefile 2010-08-10 04:16:18.000000000 -0400 @@ -0,0 +1,5 @@ +# +# Makefile for regulator driver for MC34704. +# + +obj-$(CONFIG_REGULATOR_MC34704) += reg-mc34704.o diff -urN linux-2.6.26/drivers/regulator/mc34704/reg-mc34704.c linux-2.6.26-lab126/drivers/regulator/mc34704/reg-mc34704.c --- linux-2.6.26/drivers/regulator/mc34704/reg-mc34704.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/regulator/mc34704/reg-mc34704.c 2010-08-10 04:16:18.000000000 -0400 @@ -0,0 +1,291 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MC34704_ONOFFA 0x8 +#define MC34704_ONOFFC 0x4 +#define MC34704_ONOFFD 0x2 +#define MC34704_ONOFFE 0x1 + +enum { + MC34704_BKLT, /* REG1 5V for Backlight */ + MC34704_CPU, /* REG2 3.3V for CPU & CPU board peripherals */ + MC34704_CORE, /* REG3 1.45V for CPU Core */ + MC34704_DDR, /* REG4 1.8V for DDR */ + MC34704_PERS, /* REG5 3.3V for Personality board */ + MC34704_REG6, /* REG6 not used */ + MC34704_REG7, /* REG7 not used */ + MC34704_REG8, /* REG8 not used */ +} MC34704_regulator; + +/* Regulator voltages in mV and dynamic voltage scaling limits in percent */ + +#define REG1_V_MV 5000 +#define REG1_DVS_MIN_PCT (-10) +#define REG1_DVS_MAX_PCT 10 + +#define REG2_V_MV 3300 +#define REG2_DVS_MIN_PCT (-20) +#define REG2_DVS_MAX_PCT 17.5 + +#define REG3_V_MV 1450 +#define REG3_DVS_MIN_PCT (-20) +#define REG3_DVS_MAX_PCT 17.5 + +#define REG4_V_MV 1800 +#define REG4_DVS_MIN_PCT (-20) +#define REG4_DVS_MAX_PCT 17.5 + +#define REG5_V_MV 3300 +#define REG5_DVS_MIN_PCT (-20) +#define REG5_DVS_MAX_PCT 17.5 + +/* Private data for MC34704 regulators */ + +struct reg_mc34704_priv { + short enable; /* enable bit, if available */ + short v_default; /* default regulator voltage in mV */ + int dvs_min; /* minimum voltage change in units of 2.5% */ + int dvs_max; /* maximum voltage change in units of 2.5% */ + char i2c_dvs; /* i2c DVS register number */ + char i2c_stat; /* i2c status register number */ +}; +struct reg_mc34704_priv mc34704_reg1_bklt_priv = { + .v_default = REG1_V_MV, + .dvs_min = REG1_DVS_MIN_PCT / 2.5, + .dvs_max = REG1_DVS_MAX_PCT / 2.5, + .i2c_dvs = 0x4, + .i2c_stat = 0x5, + .enable = MC34704_ONOFFA, +}; +struct reg_mc34704_priv mc34704_reg2_cpu_priv = { + .v_default = REG2_V_MV, + .dvs_min = REG2_DVS_MIN_PCT / 2.5, + .dvs_max = REG2_DVS_MAX_PCT / 2.5, + .i2c_dvs = 0x6, + .i2c_stat = 0x7, +}; +struct reg_mc34704_priv mc34704_reg3_core_priv = { + .v_default = REG3_V_MV, + .dvs_min = REG3_DVS_MIN_PCT / 2.5, + .dvs_max = REG3_DVS_MAX_PCT / 2.5, + .i2c_dvs = 0x8, + .i2c_stat = 0x9, +}; +struct reg_mc34704_priv mc34704_reg4_ddr_priv = { + .v_default = REG4_V_MV, + .dvs_min = REG4_DVS_MIN_PCT / 2.5, + .dvs_max = REG4_DVS_MAX_PCT / 2.5, + .i2c_dvs = 0xA, + .i2c_stat = 0xB, +}; +struct reg_mc34704_priv mc34704_reg5_pers_priv = { + .v_default = REG5_V_MV, + .dvs_min = REG5_DVS_MIN_PCT / 2.5, + .dvs_max = REG5_DVS_MAX_PCT / 2.5, + .i2c_dvs = 0xC, + .i2c_stat = 0xE, + .enable = MC34704_ONOFFE, +}; + +static int mc34704_set_voltage(struct regulator *reg, int uV) +{ + struct reg_mc34704_priv *priv = regulator_get_drvdata(reg); + int mV = uV / 1000; + int dV = mV - priv->v_default; + + /* compute dynamic voltage scaling value */ + int dvs = 1000 * dV / priv->v_default / 25; + + /* clip to regulator limits */ + if (dvs > priv->dvs_max) + dvs = priv->dvs_max; + if (dvs < priv->dvs_min) + dvs = priv->dvs_min; + + return pmic_write_reg(priv->i2c_dvs, dvs << 1, 0x1E); +} + +static int mc34704_get_voltage(struct regulator *reg) +{ + int mV; + struct reg_mc34704_priv *priv = regulator_get_drvdata(reg); + int val, dvs; + + CHECK_ERROR(pmic_read_reg(priv->i2c_dvs, &val, 0xF)); + + dvs = (val >> 1) & 0xF; + + /* dvs is 4-bit 2's complement; sign-extend it */ + if (dvs & 8) + dvs |= -1 & ~0xF; + + /* Regulator voltage is adjusted by (dvs * 2.5%) */ + mV = priv->v_default * (1000 + 25 * dvs) / 1000; + + return 1000 * mV; +} + +static int mc34704_enable_reg(struct regulator *reg) +{ + struct reg_mc34704_priv *priv = regulator_get_drvdata(reg); + + if (priv->enable) + return pmic_write_reg(REG_MC34704_GENERAL2, -1, priv->enable); + + return PMIC_ERROR; +} + +static int mc34704_disable_reg(struct regulator *reg) +{ + struct reg_mc34704_priv *priv = regulator_get_drvdata(reg); + + if (priv->enable) + return pmic_write_reg(REG_MC34704_GENERAL2, 0, priv->enable); + + return PMIC_ERROR; +} + +static int mc34704_is_reg_enabled(struct regulator *reg) +{ + struct reg_mc34704_priv *priv = regulator_get_drvdata(reg); + int val; + + if (priv->enable) { + CHECK_ERROR(pmic_read_reg(REG_MC34704_GENERAL2, &val, + priv->enable)); + return val ? 1 : 0; + } else { + return PMIC_ERROR; + } +} + +static struct regulator_ops mc34704_full_ops = { + .set_voltage = mc34704_set_voltage, + .get_voltage = mc34704_get_voltage, + .enable = mc34704_enable_reg, + .disable = mc34704_disable_reg, + .is_enabled = mc34704_is_reg_enabled, +}; + +static struct regulator_ops mc34704_partial_ops = { + .set_voltage = mc34704_set_voltage, + .get_voltage = mc34704_get_voltage, +}; + +struct regulation_constraints mc34704_reg1_bklt_constraints = { + .min_uV = mV_to_uV(REG1_V_MV * (1000 + REG1_DVS_MIN_PCT * 10) / 1000), + .max_uV = mV_to_uV(REG1_V_MV * (1000 + REG1_DVS_MAX_PCT * 10) / 1000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; +struct regulation_constraints mc34704_reg2_cpu_constraints = { + .min_uV = mV_to_uV(REG2_V_MV * (1000 + REG2_DVS_MIN_PCT * 10) / 1000), + .max_uV = mV_to_uV(REG2_V_MV * (1000 + REG2_DVS_MAX_PCT * 10) / 1000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; +struct regulation_constraints mc34704_reg3_core_constraints = { + .min_uV = mV_to_uV(REG3_V_MV * (1000 + REG3_DVS_MIN_PCT * 10) / 1000), + .max_uV = mV_to_uV(REG3_V_MV * (1000 + REG3_DVS_MAX_PCT * 10) / 1000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; +struct regulation_constraints mc34704_reg4_ddr_constraints = { + .min_uV = mV_to_uV(REG4_V_MV * (1000 + REG4_DVS_MIN_PCT * 10) / 1000), + .max_uV = mV_to_uV(REG4_V_MV * (1000 + REG4_DVS_MAX_PCT * 10) / 1000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; +struct regulation_constraints mc34704_reg5_pers_constraints = { + .min_uV = mV_to_uV(REG5_V_MV * (1000 + REG5_DVS_MIN_PCT * 10) / 1000), + .max_uV = mV_to_uV(REG5_V_MV * (1000 + REG5_DVS_MAX_PCT * 10) / 1000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, +}; + +static struct regulator reg_mc34704[] = { + { + .name = "REG1_BKLT", + .id = MC34704_BKLT, + .ops = &mc34704_full_ops, + .constraints = &mc34704_reg1_bklt_constraints, + .use_count = 1, + .reg_data = &mc34704_reg1_bklt_priv, + }, { + .name = "REG2_CPU", + .id = MC34704_CPU, + .ops = &mc34704_partial_ops, + .constraints = &mc34704_reg2_cpu_constraints, + .use_count = 1, + .reg_data = &mc34704_reg2_cpu_priv, + }, { + .name = "REG3_CORE", + .id = MC34704_CORE, + .ops = &mc34704_partial_ops, + .constraints = &mc34704_reg3_core_constraints, + .use_count = 1, + .reg_data = &mc34704_reg3_core_priv, + }, { + .name = "REG4_DDR", + .id = MC34704_DDR, + .ops = &mc34704_partial_ops, + .constraints = &mc34704_reg4_ddr_constraints, + .reg_data = &mc34704_reg4_ddr_priv, + }, { + .name = "REG5_PERS", + .id = MC34704_PERS, + .ops = &mc34704_full_ops, + .constraints = &mc34704_reg5_pers_constraints, + .use_count = 1, + .reg_data = &mc34704_reg5_pers_priv, + }, +}; + +int reg_mc34704_probe(void) +{ + int ret; + int i; + + for (i = 0; i < ARRAY_SIZE(reg_mc34704); i++) { + ret = regulator_register(reg_mc34704 + i); + regulator_set_platform_constraints(reg_mc34704[i].name, + reg_mc34704[i].constraints); + if (ret < 0) { + printk(KERN_ERR "%s: failed to register %s err %d\n", + __func__, reg_mc34704[i].name, ret); + i--; + for (; i >= 0; i--) + regulator_unregister(reg_mc34704 + i); + + return ret; + } + } + + printk(KERN_INFO "MC34704 regulator successfully probed\n"); + + return 0; +} +EXPORT_SYMBOL(reg_mc34704_probe); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MC34704 Regulator Driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/regulator/mc9sdz60/Makefile linux-2.6.26-lab126/drivers/regulator/mc9sdz60/Makefile --- linux-2.6.26/drivers/regulator/mc9sdz60/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/regulator/mc9sdz60/Makefile 2010-08-10 04:16:18.000000000 -0400 @@ -0,0 +1 @@ +obj-$(CONFIG_REGULATOR_MC9SDZ60) += reg-mc9sdz60.o diff -urN linux-2.6.26/drivers/regulator/mc9sdz60/reg-mc9sdz60.c linux-2.6.26-lab126/drivers/regulator/mc9sdz60/reg-mc9sdz60.c --- linux-2.6.26/drivers/regulator/mc9sdz60/reg-mc9sdz60.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/regulator/mc9sdz60/reg-mc9sdz60.c 2010-08-10 04:16:18.000000000 -0400 @@ -0,0 +1,203 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum { + MC9SDZ60_LCD, + MC9SDZ60_WIFI, + MC9SDZ60_HDD, + MC9SDZ60_GPS, + MC9SDZ60_SPKR, +} MC9SDZ60_regulator; + +#define NUM_MC9SDZ60_REGULATORS 5 + +/* lcd */ +static int mc9sdz60_lcd_enable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 6, 1); +} + +static int mc9sdz60_lcd_disable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 6, 0); +} + +static struct regulator_ops mc9sdz60_lcd_ops = { + .enable = mc9sdz60_lcd_enable, + .disable = mc9sdz60_lcd_disable, +}; + +/* wifi */ +static int mc9sdz60_wifi_enable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 5, 1); +} + +static int mc9sdz60_wifi_disable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 5, 0); +} + +static struct regulator_ops mc9sdz60_wifi_ops = { + .enable = mc9sdz60_wifi_enable, + .disable = mc9sdz60_wifi_disable, +}; + +/* hdd */ +static int mc9sdz60_hdd_enable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 4, 1); +} + +static int mc9sdz60_hdd_disable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 4, 0); +} + +static struct regulator_ops mc9sdz60_hdd_ops = { + .enable = mc9sdz60_hdd_enable, + .disable = mc9sdz60_hdd_disable, +}; + +/* gps */ +static int mc9sdz60_gps_enable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 0, 1); +} + +static int mc9sdz60_gps_disable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 0, 0); +} + +static struct regulator_ops mc9sdz60_gps_ops = { + .enable = mc9sdz60_gps_enable, + .disable = mc9sdz60_gps_disable, +}; + +/* speaker */ +static int mc9sdz60_speaker_enable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 0, 1); +} + +static int mc9sdz60_speaker_disable(struct regulator *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 0, 0); +} + +static struct regulator_ops mc9sdz60_speaker_ops = { + .enable = mc9sdz60_speaker_enable, + .disable = mc9sdz60_speaker_disable, +}; + +struct mc9sdz60_regulator { + struct regulator regulator; +}; + +static struct mc9sdz60_regulator + reg_mc9sdz60[NUM_MC9SDZ60_REGULATORS] = { + { + .regulator = { + .name = "LCD", + .id = MC9SDZ60_LCD, + .ops = &mc9sdz60_lcd_ops, + }, + }, + { + .regulator = { + .name = "WIFI", + .id = MC9SDZ60_WIFI, + .ops = &mc9sdz60_wifi_ops, + }, + }, + { + .regulator = { + .name = "HDD", + .id = MC9SDZ60_HDD, + .ops = &mc9sdz60_hdd_ops, + }, + }, + { + .regulator = { + .name = "GPS", + .id = MC9SDZ60_GPS, + .ops = &mc9sdz60_gps_ops, + }, + + }, + { + .regulator = { + .name = "SPKR", + .id = MC9SDZ60_SPKR, + .ops = &mc9sdz60_speaker_ops, + }, + + }, + +}; + + +/* + * Init and Exit + */ +int reg_mc9sdz60_probe(void) +{ + int ret11 = 0; + int i = 0; + + for (i = 0; i < ARRAY_SIZE(reg_mc9sdz60); i++) { + ret11 = regulator_register(®_mc9sdz60[i].regulator); + regulator_set_platform_constraints(reg_mc9sdz60[i].regulator. + name, + reg_mc9sdz60[i].regulator. + constraints); + if (ret11 < 0) { + i--; + for (; i >= 0; i--) + regulator_unregister( + ®_mc9sdz60[i].regulator); + + return ret11; + } + + } + return 0; +} +EXPORT_SYMBOL(reg_mc9sdz60_probe); + +int reg_mc9sdz60_remove(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(reg_mc9sdz60); i++) + regulator_unregister(®_mc9sdz60[i].regulator); + return 0; +} +EXPORT_SYMBOL(reg_mc9sdz60_remove); + + diff -urN linux-2.6.26/drivers/regulator/reg-core.c linux-2.6.26-lab126/drivers/regulator/reg-core.c --- linux-2.6.26/drivers/regulator/reg-core.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/regulator/reg-core.c 2010-08-10 04:16:18.000000000 -0400 @@ -0,0 +1,844 @@ +/* + * regulator.c -- Voltage/Current Regulator framework. + * + * Copyright 2007 Wolfson Microelectronics PLC. + * + * Author: Liam Girdwood + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static DEFINE_MUTEX(list_mutex); +static LIST_HEAD(regulators); + +struct regulator_load { + struct device *dev; + struct list_head list; + int uA_load; + struct device_attribute dev_attr; +}; + +#define to_regulator(cd) \ + container_of(cd, struct regulator, cdev) + +static struct regulator_load *get_regulator_load(struct device *dev) +{ + struct regulator_load *load = NULL; + struct regulator *regulator; + + list_for_each_entry(regulator, ®ulators, list) { + list_for_each_entry(load, ®ulator->user_list, list) { + if (load->dev == dev) + return load; + } + } + return NULL; +} + +#if 0 +static int constraint_check_state(struct regulator *regulator) +{ + if (!regulator->constraints) + return -ENODEV; + if (!regulator->constraints->valid_ops_mask & REGULATOR_CHANGE_STATUS) + return -EPERM; + return 0; +} +#endif + +static int constraint_check_voltage(struct regulator *regulator, int uV) +{ + if (!regulator->constraints) + return -ENODEV; + if (!regulator->constraints->valid_ops_mask & REGULATOR_CHANGE_VOLTAGE) + return -EPERM; + if (uV > regulator->constraints->max_uV || + uV < regulator->constraints->min_uV) + return -EINVAL; + return 0; +} + +static int constraint_check_current(struct regulator *regulator, int uA) +{ + if (!regulator->constraints) + return -ENODEV; + if (!regulator->constraints->valid_ops_mask & REGULATOR_CHANGE_CURRENT) + return -EPERM; + if (uA > regulator->constraints->max_uA || + uA < regulator->constraints->min_uA) + return -EINVAL; + return 0; +} + +static int constraint_check_mode(struct regulator *regulator, int mode) +{ + if (!regulator->constraints) + return -ENODEV; + if (!regulator->constraints->valid_ops_mask & REGULATOR_CHANGE_MODE) + return -EPERM; + if (!regulator->constraints->valid_modes_mask & mode) + return -EINVAL; + return 0; +} + +static int constraint_check_drms(struct regulator *regulator) +{ + if (!regulator->constraints) + return -ENODEV; + if (!regulator->constraints->valid_ops_mask & REGULATOR_CHANGE_DRMS) + return -EPERM; + return 0; +} + +static ssize_t dev_load_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct regulator_load *load; + + load = get_regulator_load(dev); + if (load == NULL) + return 0; + + return sprintf(buf, "%d\n", load->uA_load); +} + +static ssize_t regulator_uV_show(struct device *cdev, struct device_attribute *attr, char *buf) +{ + struct regulator *regulator = to_regulator(cdev); + + return sprintf(buf, "%d\n", regulator_get_voltage(regulator)); +} + +static ssize_t regulator_uV_store(struct device *cdev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct regulator *regulator = to_regulator(cdev); + int mV, ret; + + mV = simple_strtoul(buf, NULL, 10); + + ret = regulator_set_voltage(regulator, mV * 1000); + if (ret == 0) + printk(KERN_INFO "set voltage %d mV\n", mV); + else + printk(KERN_INFO "set voltage failed\n"); + + return count; +} + +static ssize_t regulator_uA_show(struct device *cdev, struct device_attribute *attr, char *buf) +{ + struct regulator *regulator = to_regulator(cdev); + + return sprintf(buf, "%d\n", regulator_get_current(regulator)); +} + +static ssize_t regulator_mode_show(struct device *cdev, struct device_attribute *attr, char *buf) +{ + struct regulator *regulator = to_regulator(cdev); + int mode = regulator_get_mode(regulator); + + switch (mode) { + case REGULATOR_MODE_FAST: + return sprintf(buf, "fast\n"); + case REGULATOR_MODE_NORMAL: + return sprintf(buf, "normal\n"); + case REGULATOR_MODE_IDLE: + return sprintf(buf, "idle\n"); + case REGULATOR_MODE_STANDBY: + return sprintf(buf, "standby\n"); + } + return sprintf(buf, "unknown\n"); +} + +static ssize_t regulator_state_show(struct device *cdev, struct device_attribute *attr, char *buf) +{ + struct regulator *regulator = to_regulator(cdev); + int state = regulator_is_enabled(regulator); + + if (state > 0) + return sprintf(buf, "enabled\n"); + else if (state == 0) + return sprintf(buf, "disabled\n"); + else + return sprintf(buf, "unknown\n"); +} + +static ssize_t +regulator_constraint_uA_show(struct device *cdev, struct device_attribute *attr, char *buf) +{ + struct regulator *regulator = to_regulator(cdev); + + if (!regulator->constraints) + return sprintf(buf, "no constraints\n"); + + return sprintf(buf, "%d %d\n", regulator->constraints->min_uA, + regulator->constraints->max_uA); +} + +static ssize_t +regulator_constraint_uV_show(struct device *cdev, struct device_attribute *attr, char *buf) +{ + struct regulator *regulator = to_regulator(cdev); + + if (!regulator->constraints) + return sprintf(buf, "no constraints\n"); + + return sprintf(buf, "%d %d\n", regulator->constraints->min_uV, + regulator->constraints->max_uV); +} + +static ssize_t +regulator_constraint_modes_show(struct device *cdev, struct device_attribute *attr, char *buf) +{ + struct regulator *regulator = to_regulator(cdev); + int count = 0; + + if (!regulator->constraints) + return sprintf(buf, "no constraints\n"); + + if (regulator->constraints->valid_modes_mask & REGULATOR_MODE_FAST) + count = sprintf(buf, "fast "); + if (regulator->constraints->valid_modes_mask & REGULATOR_MODE_NORMAL) + count += sprintf(buf + count, "normal "); + if (regulator->constraints->valid_modes_mask & REGULATOR_MODE_IDLE) + count += sprintf(buf + count, "idle "); + if (regulator->constraints->valid_modes_mask & REGULATOR_MODE_STANDBY) + count += sprintf(buf + count, "standby"); + count += sprintf(buf + count, "\n"); + return count; +} + +static ssize_t regulator_total_dev_load(struct device *cdev, struct device_attribute *attr, char *buf) +{ + struct regulator *regulator = to_regulator(cdev); + struct regulator_load *load; + int uA = 0; + + list_for_each_entry(load, ®ulator->user_list, list) { + uA += load->uA_load; + } + return sprintf(buf, "%d\n", uA); +} + +static ssize_t regulator_enabled_use_count(struct device *cdev, struct device_attribute *attr, char *buf) +{ + struct regulator *regulator = to_regulator(cdev); + return sprintf(buf, "%d\n", regulator->use_count); +} + +static ssize_t regulator_ctl(struct device *cdev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct regulator *regulator = to_regulator(cdev); + if (buf[0] == '0') { + printk(KERN_WARNING "disable regulator.\n"); + if (regulator_disable(regulator)) + printk(KERN_ERR "disable regulator failed.\n"); + } else { + printk(KERN_WARNING "enable regulator.\n"); + if (regulator_enable(regulator)) + printk(KERN_ERR "enable regulator failed.\n"); + } + return count; +} + +static struct device_attribute regulator_dev_attrs[] = { + __ATTR(uV, 0666, regulator_uV_show, regulator_uV_store), + __ATTR(uA, 0444, regulator_uA_show, NULL), + __ATTR(mode, 0444, regulator_mode_show, NULL), + __ATTR(state, 0444, regulator_state_show, NULL), + __ATTR(uA_limits, 0444, regulator_constraint_uA_show, NULL), + __ATTR(uV_limits, 0444, regulator_constraint_uV_show, NULL), + __ATTR(valid_modes, 0444, regulator_constraint_modes_show, NULL), + __ATTR(total_uA_load, 0444, regulator_total_dev_load, NULL), + __ATTR(enabled_count, 0444, regulator_enabled_use_count, NULL), + __ATTR(ctl, 0666, NULL, regulator_ctl), + __ATTR_NULL, +}; + +struct class regulator_class = { + .name = "regulator", + .dev_attrs = regulator_dev_attrs, +}; + +static struct regulator_load *create_load_dev(struct regulator *regulator, + struct device *dev) +{ + struct regulator_load *load; + char buf[32]; + int err; + + load = kzalloc(sizeof(*load), GFP_KERNEL); + if (load == NULL) + return NULL; + + sprintf(buf, "uA_load-%s", regulator->name); + list_add(&load->list, ®ulator->user_list); + load->dev = dev; + load->dev_attr.attr.name = kstrdup(buf, GFP_KERNEL); + load->dev_attr.attr.owner = THIS_MODULE; + load->dev_attr.attr.mode = 0444; + load->dev_attr.show = dev_load_show; + err = device_create_file(dev, &load->dev_attr); + if (err < 0) { + printk(KERN_WARNING "%s: could not add regulator load" + " sysfs\n", __func__); + goto err_out; + } + err = sysfs_create_link(®ulator->cdev.kobj, &dev->kobj, + kobject_name(&dev->kobj)); + if (err) { + printk + (KERN_WARNING "%s : could not add device link %s err %d\n", + __func__, kobject_name(&dev->kobj), err); + goto err_out; + } + return load; + err_out: + kfree(load->dev_attr.attr.name); + kfree(load); + return NULL; +} + +struct regulator *regulator_get(struct device *dev, const char *id) +{ + struct regulator *r, *regulator = ERR_PTR(-ENOENT); + struct regulator_load *load = NULL; + + if (id == NULL) + return regulator; + + mutex_lock(&list_mutex); + + list_for_each_entry(r, ®ulators, list) { + if (strcmp(id, r->name) == 0 && try_module_get(r->owner)) { + regulator = r; + goto found; + } + } + printk + (KERN_WARNING "regulator: Unable to get requested regulator: %s\n", + id); + mutex_unlock(&list_mutex); + return regulator; + found: + if (dev) { + load = create_load_dev(regulator, dev); + if (load == NULL) { + regulator = ERR_PTR(-ENOMEM); + module_put(regulator->owner); + } + } + + mutex_unlock(&list_mutex); + return regulator; +} + +EXPORT_SYMBOL_GPL(regulator_get); + +void regulator_put(struct regulator *regulator, struct device *dev) +{ + struct regulator_load *load, *l; + + if (regulator == NULL || IS_ERR(regulator)) + return; + + if (!dev) + goto put; + + sysfs_remove_link(®ulator->cdev.kobj, kobject_name(&dev->kobj)); + list_for_each_entry_safe(load, l, ®ulator->user_list, list) { + device_remove_file(dev, &load->dev_attr); + list_del(&load->list); + kfree(load->dev_attr.attr.name); + kfree(load); + goto put; + } + put: + module_put(regulator->owner); + mutex_unlock(&list_mutex); +} + +EXPORT_SYMBOL_GPL(regulator_put); + +static int __regulator_disable(struct regulator *regulator); + +static int __regulator_enable(struct regulator *regulator) +{ + int ret = 0; + + if (regulator->use_count == 0) { + + if (regulator->parent) { + ret = __regulator_enable(regulator->parent); + + if (ret < 0) { + __regulator_disable(regulator->parent); + goto out; + } + } + + if (regulator->ops->enable) { + ret = regulator->ops->enable(regulator); + if (ret < 0) { + __regulator_disable(regulator); + goto out; + } + } + } + regulator->use_count++; + out: + return ret; +} + +int regulator_enable(struct regulator *regulator) +{ + int ret; + + mutex_lock(®ulator->mutex); + ret = __regulator_enable(regulator); + mutex_unlock(®ulator->mutex); + return ret; +} + +EXPORT_SYMBOL_GPL(regulator_enable); + +static int __regulator_disable(struct regulator *regulator) +{ + int ret = 0; + + if (regulator->use_count > 0 && !(--regulator->use_count)) { + if (regulator->ops->disable) { + ret = regulator->ops->disable(regulator); + if (ret < 0) + goto out; + } + if (regulator->parent) + __regulator_disable(regulator->parent); + } + out: + return ret; +} + +int regulator_disable(struct regulator *regulator) +{ + int ret; + + mutex_lock(®ulator->mutex); + ret = __regulator_disable(regulator); + mutex_unlock(®ulator->mutex); + return ret; +} + +EXPORT_SYMBOL_GPL(regulator_disable); + +int regulator_is_enabled(struct regulator *regulator) +{ + int ret; + + mutex_lock(®ulator->mutex); + + /* sanity check */ + if (!regulator->ops->is_enabled) { + ret = -EINVAL; + goto out; + } + + ret = regulator->ops->is_enabled(regulator); + out: + mutex_unlock(®ulator->mutex); + return ret; +} + +EXPORT_SYMBOL_GPL(regulator_is_enabled); + +int regulator_set_voltage(struct regulator *regulator, int uV) +{ + int ret; + + mutex_lock(®ulator->mutex); + + /* sanity check */ + if (!regulator->ops->set_voltage) { + ret = -EINVAL; + goto out; + } + + /* constraints check */ + ret = constraint_check_voltage(regulator, uV); + if (ret < 0) + goto out; + + ret = regulator->ops->set_voltage(regulator, uV); + out: + mutex_unlock(®ulator->mutex); + return ret; +} + +EXPORT_SYMBOL_GPL(regulator_set_voltage); + +int regulator_get_voltage(struct regulator *regulator) +{ + int ret; + + mutex_lock(®ulator->mutex); + + /* sanity check */ + if (!regulator->ops->get_voltage) { + ret = -EINVAL; + goto out; + } + + ret = regulator->ops->get_voltage(regulator); + out: + mutex_unlock(®ulator->mutex); + return ret; +} + +EXPORT_SYMBOL_GPL(regulator_get_voltage); + +int regulator_set_current(struct regulator *regulator, int uA) +{ + int ret; + + mutex_lock(®ulator->mutex); + + /* sanity check */ + if (!regulator->ops->set_current) { + ret = -EINVAL; + goto out; + } + + /* constraints check */ + ret = constraint_check_current(regulator, uA); + if (ret < 0) + goto out; + + ret = regulator->ops->set_current(regulator, uA); + out: + mutex_unlock(®ulator->mutex); + return ret; +} + +EXPORT_SYMBOL_GPL(regulator_set_current); + +int regulator_get_current(struct regulator *regulator) +{ + int ret; + + mutex_lock(®ulator->mutex); + + /* sanity check */ + if (!regulator->ops->get_current) { + ret = -EINVAL; + goto out; + } + + ret = regulator->ops->get_current(regulator); + out: + mutex_unlock(®ulator->mutex); + return ret; +} + +EXPORT_SYMBOL_GPL(regulator_get_current); + +int regulator_set_mode(struct regulator *regulator, unsigned int mode) +{ + int ret; + + mutex_lock(®ulator->mutex); + + /* sanity check */ + if (!regulator->ops->set_mode) { + ret = -EINVAL; + goto out; + } + + /* constraints check */ + ret = constraint_check_mode(regulator, mode); + if (ret < 0) + goto out; + + ret = regulator->ops->set_mode(regulator, mode); + out: + mutex_unlock(®ulator->mutex); + return ret; +} + +EXPORT_SYMBOL_GPL(regulator_set_mode); + +unsigned int regulator_get_mode(struct regulator *regulator) +{ + int ret; + + mutex_lock(®ulator->mutex); + + /* sanity check */ + if (!regulator->ops->get_mode) { + ret = -EINVAL; + goto out; + } + + ret = regulator->ops->get_mode(regulator); + out: + mutex_unlock(®ulator->mutex); + return ret; +} + +EXPORT_SYMBOL_GPL(regulator_get_mode); + +unsigned int regulator_get_optimum_mode(struct regulator *regulator, + int input_uV, int output_uV, + int load_uA) +{ + int ret; + + mutex_lock(®ulator->mutex); + + /* sanity check */ + if (!regulator->ops->get_optimum_mode) { + ret = -EINVAL; + goto out; + } + + ret = regulator->ops->get_optimum_mode(regulator, + input_uV, output_uV, load_uA); + out: + mutex_unlock(®ulator->mutex); + return ret; +} + +EXPORT_SYMBOL_GPL(regulator_get_optimum_mode); + +int regulator_register_client(struct regulator *regulator, + struct notifier_block *nb) +{ + return blocking_notifier_chain_register(®ulator->notifier, nb); +} + +EXPORT_SYMBOL_GPL(regulator_register_client); + +int regulator_unregister_client(struct regulator *regulator, + struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(®ulator->notifier, nb); +} + +EXPORT_SYMBOL_GPL(regulator_unregister_client); + +int regulator_notifier_call_chain(struct regulator *regulator, + unsigned long event, void *data) +{ + return blocking_notifier_call_chain(®ulator->notifier, event, data); +} + +EXPORT_SYMBOL_GPL(regulator_notifier_call_chain); + +int regulator_register(struct regulator *regulator) +{ + static atomic_t regulator_no = ATOMIC_INIT(0); + int ret; + + if (regulator == NULL || IS_ERR(regulator)) + return -EINVAL; + + if (regulator->name == NULL || regulator->ops == NULL) + return -EINVAL; + + mutex_lock(&list_mutex); + + mutex_init(®ulator->mutex); + regulator->parent = NULL; + INIT_LIST_HEAD(®ulator->user_list); + BLOCKING_INIT_NOTIFIER_HEAD(®ulator->notifier); + + regulator->cdev.class = ®ulator_class; + device_initialize(®ulator->cdev); + snprintf(regulator->cdev.bus_id, sizeof(regulator->cdev.bus_id), + "regulator_%ld_%s", + (unsigned long)atomic_inc_return(®ulator_no) - 1, + regulator->name); + + ret = device_add(®ulator->cdev); + if (ret == 0) + list_add(®ulator->list, ®ulators); + mutex_unlock(&list_mutex); + return ret; +} + +EXPORT_SYMBOL_GPL(regulator_register); + +void regulator_unregister(struct regulator *regulator) +{ + if (regulator == NULL || IS_ERR(regulator)) + return; + + mutex_lock(&list_mutex); + list_del(®ulator->list); + if (regulator->parent) + sysfs_remove_link(®ulator->cdev.kobj, "source"); + device_unregister(®ulator->cdev); + mutex_unlock(&list_mutex); +} + +EXPORT_SYMBOL_GPL(regulator_unregister); + +int regulator_set_platform_source(struct regulator *regulator, + struct regulator *parent) +{ + int err; + + if (regulator == NULL || IS_ERR(regulator)) + return -EINVAL; + + if (parent == NULL || IS_ERR(parent)) + return -EINVAL; + + mutex_lock(&list_mutex); + regulator->parent = parent; + err = sysfs_create_link(®ulator->cdev.kobj, &parent->cdev.kobj, + "source"); + if (err) + printk(KERN_WARNING + "%s : could not add device link %s err %d\n", __func__, + kobject_name(&parent->cdev.kobj), err); + mutex_unlock(&list_mutex); + + return 0; +} + +EXPORT_SYMBOL_GPL(regulator_set_platform_source); + +struct regulator *regulator_get_platform_source(struct regulator *regulator) +{ + if (regulator == NULL || IS_ERR(regulator)) + return ERR_PTR(-EINVAL); + return regulator->parent; +} + +EXPORT_SYMBOL_GPL(regulator_get_platform_source); + +int regulator_set_platform_constraints(const char *regulator_name, + struct regulation_constraints + *constraints) +{ + struct regulator *regulator; + + if (regulator_name == NULL) + return -EINVAL; + + mutex_lock(&list_mutex); + list_for_each_entry(regulator, ®ulators, list) { + if (!strcmp(regulator_name, regulator->name)) { + mutex_lock(®ulator->mutex); + regulator->constraints = constraints; + mutex_unlock(®ulator->mutex); + mutex_unlock(&list_mutex); + return 0; + } + } + mutex_unlock(&list_mutex); + return -ENODEV; +} + +EXPORT_SYMBOL_GPL(regulator_set_platform_constraints); + +static void load_change(struct regulator *regulator, + struct regulator_load *load, int uA) +{ + struct regulator_load *l; + int current_uA = 0, output_uV, input_uV, err; + unsigned int mode; + + load->uA_load = uA; + err = constraint_check_drms(regulator); + if (err < 0 || !regulator->ops->get_optimum_mode || + !regulator->ops->get_voltage || !regulator->ops->set_mode) + return; + + /* get output voltage */ + output_uV = regulator->ops->get_voltage(regulator); + + /* get input voltage */ + if (regulator->parent && regulator->parent->ops->get_voltage) + input_uV = + regulator->parent->ops->get_voltage(regulator->parent); + else + input_uV = regulator->constraints->input_uV; + + /* calc total requested load */ + list_for_each_entry(l, ®ulator->user_list, list) + current_uA += l->uA_load; + + mode = regulator->ops->get_optimum_mode(regulator, input_uV, + output_uV, current_uA); + err = constraint_check_mode(regulator, mode); + if (err < 0) + return; + + regulator->ops->set_mode(regulator, mode); +} + +void regulator_drms_notify_load(struct regulator *regulator, + struct device *dev, int uA) +{ + struct regulator_load *load; + + mutex_lock(®ulator->mutex); + list_for_each_entry(load, ®ulator->user_list, list) { + if (load->dev == dev) { + load_change(regulator, load, uA); + break; + } + } + mutex_unlock(®ulator->mutex); +} + +EXPORT_SYMBOL_GPL(regulator_drms_notify_load); + +void *regulator_get_drvdata(struct regulator *regulator) +{ + return regulator->reg_data; +} + +EXPORT_SYMBOL_GPL(regulator_get_drvdata); + +void regulator_set_drvdata(struct regulator *regulator, void *data) +{ + regulator->reg_data = data; +} + +EXPORT_SYMBOL_GPL(regulator_set_drvdata); + +static int __init regulator_init(void) +{ + return class_register(®ulator_class); +} + +static void __exit regulator_exit(void) +{ + class_unregister(®ulator_class); +} + +subsys_initcall(regulator_init); +module_exit(regulator_exit); + +MODULE_AUTHOR("Liam Girdwood, liam.girdwood@wolfsonmicro.com, \ + www.wolfsonmicro.com "); +MODULE_DESCRIPTION("Regulator Interface"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/regulator/wm8350/Makefile linux-2.6.26-lab126/drivers/regulator/wm8350/Makefile --- linux-2.6.26/drivers/regulator/wm8350/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/regulator/wm8350/Makefile 2010-08-10 04:16:18.000000000 -0400 @@ -0,0 +1,5 @@ +# +# Makefile for regulator driver for WM8350. +# + +obj-$(CONFIG_REGULATOR_WM8350) += reg-wm8350.o reg-wm8350-bus.o reg-wm8350-i2c.o diff -urN linux-2.6.26/drivers/regulator/wm8350/reg-wm8350-bus.c linux-2.6.26-lab126/drivers/regulator/wm8350/reg-wm8350-bus.c --- linux-2.6.26/drivers/regulator/wm8350/reg-wm8350-bus.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/regulator/wm8350/reg-wm8350-bus.c 2010-08-10 04:16:18.000000000 -0400 @@ -0,0 +1,1525 @@ +/* + * wm8350_bus.c -- Power Management Driver for Wolfson WM8350 PMIC + * + * Copyright 2007 Wolfson Microelectronics PLC. + * Copyright 2009 Freescale Semiconductor Inc. + * + * Author: Liam Girdwood + * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Revision history + * 23rd Jan 2007 Initial version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define WM8350_BUS_VERSION "0.4" +#define WM8350_UNLOCK_KEY 0x0013 +#define WM8350_LOCK_KEY 0x0000 + +#define WM8350_CLOCK_CONTROL_1 0x28 +#define WM8350_AIF_TEST 0x74 + +/* debug */ +#define WM8350_BUS_DEBUG 0 +#if WM8350_BUS_DEBUG +#define dbg(format, arg...) printk(format, ## arg) +#define dump(regs, src) do { \ + int i; \ + u16 *src_ = src; \ + for (i = 0; i < regs; i++) \ + dbg(" 0x%4.4x", *src_++); \ + dbg("\n"); \ +} while (0); +#else +#define dbg(format, arg...) +#define dump(bytes, src) +#endif + +#define WM8350_LOCK_DEBUG 0 +#if WM8350_LOCK_DEBUG +#define ldbg(format, arg...) printk(format, ## arg) +#else +#define ldbg(format, arg...) +#endif + +#define BYTE_SWAP16(x) (x >> 8 | x << 8) // lg replace with generic + +/* + * WM8350 can run in 1 of 4 configuration modes. + * Each mode has different default register values. + */ +#if defined(CONFIG_PMIC_WM8350_MODE_0) +static const u16 wm8350_reg_map[] = WM8350_REGISTER_DEFAULTS_0; +#elif defined(CONFIG_PMIC_WM8350_MODE_1) +static const u16 wm8350_reg_map[] = WM8350_REGISTER_DEFAULTS_1; +#elif defined(CONFIG_PMIC_WM8350_MODE_2) +static const u16 wm8350_reg_map[] = WM8350_REGISTER_DEFAULTS_2; +#elif defined(CONFIG_PMIC_WM8350_MODE_3) +static const u16 wm8350_reg_map[] = WM8350_REGISTER_DEFAULTS_3; +#else +#error Invalid WM8350 configuration +#endif + +static int wm8350_in_suspend; + +/* + * WM8350 Register IO access map + */ +static const struct wm8350_reg_access wm8350_reg_io_map[] = WM8350_ACCESS; + +/* + * WM8350 Device IO + */ +static DEFINE_MUTEX(io_mutex); +static DEFINE_MUTEX(reg_lock_mutex); +static DEFINE_MUTEX(auxadc_mutex); + +#ifdef CONFIG_I2C +static int wm8350_read_i2c_device(struct wm8350 *wm8350, char reg, + int bytes, char *dest) +{ + int ret; + + ret = i2c_master_send(wm8350->i2c_client, ®, 1); + if (ret < 0) + return ret; + ret = i2c_master_recv(wm8350->i2c_client, dest, bytes); + return ret < 0 ? ret : 0; +} + +static int wm8350_write_i2c_device(struct wm8350 *wm8350, char reg, + int bytes, char *src) +{ + int ret; + + /* we add 1 byte for device register */ + u8 msg[(WM8350_MAX_REGISTER << 1) + 1]; + + if (bytes > ((WM8350_MAX_REGISTER << 1) + 1)) + return -EINVAL; + + msg[0] = reg; + memcpy(&msg[1], src, bytes); + ret = i2c_master_send(wm8350->i2c_client, msg, bytes + 1); + return ret < 0 ? ret : 0; +} +#endif + +#ifdef CONFIG_SPI +static int wm8350_read_spi_device(struct wm8350 *wm8350, char reg, + int bytes, char *dest) +{ + int ret; + u8 tx_msg[4], rx_msg[4]; + + /* don't support incremental write with SPI */ + if (bytes != 2) + return -EIO; + + tx_msg[0] = 0x80; + tx_msg[1] = reg; + tx_msg[2] = 0; + tx_msg[3] = 0; + + ret = spi_write_then_read(wm8350->spi_device, tx_msg, 4, rx_msg, 4); + if (ret < 0) { + printk(KERN_ERR "%s: io failure %d\n", __func__, ret); + return 0; + } + + *dest++ = rx_msg[2]; + *dest = rx_msg[3]; + return 0; +} + +static int wm8350_write_spi_device(struct wm8350 *wm8350, char reg, + int bytes, char *src) +{ + u8 msg[4]; + + /* don't support incremental write with SPI */ + if (bytes != 2) + return -EIO; + + msg[0] = 0; + msg[1] = reg; + msg[2] = *src++; + msg[3] = *src; + return spi_write(wm8350->spi_device, msg, 4); +} +#endif + +/* mask in WM8350 read bits */ +static inline void wm8350_mask_read(u8 reg, int bytes, u16 *buf) +{ + int i; + + for (i = reg; i < reg + (bytes >> 1); i++) + *buf++ &= wm8350_reg_io_map[i].readable; +} + +/* mask in WM8350 write bits */ +static inline void wm8350_mask_write(u8 reg, int bytes, u16 *buf) +{ + int i; + + for (i = reg; i < reg + (bytes >> 1); i++) + *buf++ &= wm8350_reg_io_map[i].writable; +} + +/* WM8350 is big endian, swap if necessary */ +static inline void wm8350_endian_swap(u8 reg, int bytes, u16 *buf) +{ +#ifdef __LITTLE_ENDIAN + int i; + u16 tmp; + + for (i = reg; i < reg + (bytes >> 1); i++) { + tmp = BYTE_SWAP16(*buf); + *buf++ = tmp; + } +#endif +} + +static inline void wm8350_cache_mask(struct wm8350 *wm8350, u8 reg, + int bytes, u16 *dest) +{ + int i; + u16 mask; + + for (i = reg; i < reg + (bytes >> 1); i++) { + *dest &= wm8350_reg_io_map[i].vol; + mask = wm8350->reg_cache[reg] & ~wm8350_reg_io_map[i].vol; + *dest |= mask; + dest++; + } +} + +static int wm8350_read(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *dest) +{ + int i, end = reg + num_regs, ret = 0, bytes = num_regs << 1; + + if (wm8350->read_dev == NULL) + return -ENODEV; + + if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) { + printk(KERN_ERR "wm8350: invalid reg %x\n", reg + num_regs - 1); + return -EINVAL; + } + + dbg("%s R%d(0x%2.2x) %d regs ", __FUNCTION__, reg, reg, num_regs); + +#if WM8350_BUS_DEBUG + /* we can _safely_ read any register, but warn if read not supported */ + for (i = reg; i < end; i++) { + if (!wm8350_reg_io_map[i].readable) + printk(KERN_WARNING "wm8350: reg R%d is not readable\n", i); + } +#endif + /* if any volatile registers are required, then read back all */ + for (i = reg; i < end; i++) { + if (wm8350_reg_io_map[i].vol) { + dbg("volatile read "); + ret = wm8350->read_dev(wm8350, reg, + bytes, (char*)dest); + wm8350_endian_swap(reg, bytes, dest); + wm8350_cache_mask(wm8350, reg, bytes, dest); + wm8350_mask_read(reg, bytes, dest); + dump(num_regs, dest); + return ret; + } + } + + /* no volatiles, then cache is good */ + dbg("cache read "); + memcpy(dest, &wm8350->reg_cache[reg], bytes); + dump(num_regs, dest); + return ret; +} + +static inline int is_reg_locked(struct wm8350 *wm8350, u8 reg) +{ + if (reg == WM8350_SECURITY || + wm8350->reg_cache[WM8350_SECURITY] == WM8350_UNLOCK_KEY) + return 0; + + if ((reg == WM8350_GPIO_CONFIGURATION_I_O) || + (reg >= WM8350_GPIO_FUNCTION_SELECT_1 && + reg <= WM8350_GPIO_FUNCTION_SELECT_4) || + (reg >= WM8350_BATTERY_CHARGER_CONTROL_1 && + reg <= WM8350_BATTERY_CHARGER_CONTROL_3)) + return 1; + return 0; +} + +static int wm8350_write(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *src) +{ + int ret, i, end = reg + num_regs, bytes = num_regs << 1; + + if (wm8350->write_dev == NULL) + return -ENODEV; + + if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) { + printk(KERN_ERR "wm8350: invalid reg %x\n", reg + num_regs - 1); + return -EINVAL; + } + + wm8350_mask_write(reg, bytes, src); + memcpy(&wm8350->reg_cache[reg], src, bytes); + dbg("%s R%d(0x%2.2x) %d regs ", __FUNCTION__, reg, reg, num_regs); + dump(num_regs, src); + + wm8350_endian_swap(reg, bytes, src); + + /* it's generally not a good idea to write to RO or locked registers */ + for (i = reg; i < end; i++) { + if (!wm8350_reg_io_map[i].writable) { + printk(KERN_ERR "wm8350: attempted write to read only reg R%d\n", i); + return -EINVAL; + } + + if (is_reg_locked(wm8350, i)) { + printk(KERN_ERR "wm8350: attempted write to locked reg R%d\n", i); + return -EINVAL; + } + } + + /* write registers and update cache if successful */ + ret = wm8350->write_dev(wm8350, reg, bytes, (char*)src); + return ret; +} + +/* + * Safe read, modify, write methods + */ +int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask) +{ + u16 data; + int err; + + mutex_lock(&io_mutex); + err = wm8350_read(wm8350, reg, 1, &data); + if (err) { + printk(KERN_ERR "wm8350: read from reg R%d failed\n", reg); + goto out; + } + + data &= ~mask; + err = wm8350_write(wm8350, reg, 1, &data); + if (err) + printk(KERN_ERR "wm8350: write to reg R%d failed\n", reg); +out: + mutex_unlock(&io_mutex); + return err; +} +EXPORT_SYMBOL_GPL(wm8350_clear_bits); + +int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask) +{ + u16 data; + int err; + + mutex_lock(&io_mutex); + err = wm8350_read(wm8350, reg, 1, &data); + if (err) { + printk(KERN_ERR "wm8350: read from reg R%d failed\n", reg); + goto out; + } + + data |= mask; + err = wm8350_write(wm8350, reg, 1, &data); + if (err) + printk(KERN_ERR "wm8350: write to reg R%d failed\n", reg); +out: + mutex_unlock(&io_mutex); + return err; +} +EXPORT_SYMBOL_GPL(wm8350_set_bits); + +u16 wm8350_reg_read(struct wm8350 *wm8350, int reg) +{ + u16 data; + int err; + + mutex_lock(&io_mutex); + err = wm8350_read(wm8350, reg, 1, &data); + if (err) + printk(KERN_ERR "wm8350: read from reg R%d failed\n", reg); + + mutex_unlock(&io_mutex); + return data; +} +EXPORT_SYMBOL_GPL(wm8350_reg_read); + +int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val) +{ + int ret; + u16 data = val; + + mutex_lock(&io_mutex); + ret = wm8350_write(wm8350, reg, 1, &data); + if (ret) + printk(KERN_ERR "wm8350: write to reg R%d failed\n", reg); + mutex_unlock(&io_mutex); + return ret; +} +EXPORT_SYMBOL_GPL(wm8350_reg_write); + +int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs, + u16 *dest) +{ + int err = 0; + + mutex_lock(&io_mutex); + err = wm8350_read(wm8350, start_reg, regs, dest); + if (err) + printk(KERN_ERR "wm8350: block read starting from R%d failed\n", + start_reg); + mutex_unlock(&io_mutex); + return err; +} +EXPORT_SYMBOL_GPL(wm8350_block_read); + +int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs, + u16 *src) +{ + int ret = 0; + + mutex_lock(&io_mutex); + ret = wm8350_write(wm8350, start_reg, regs, src); + if (ret) + printk(KERN_ERR "wm8350: block write starting at R%d failed\n", + start_reg); + mutex_unlock(&io_mutex); + return ret; +} +EXPORT_SYMBOL_GPL(wm8350_block_write); + +int wm8350_reg_lock(struct wm8350 *wm8350) +{ + u16 key = WM8350_LOCK_KEY; + int ret; + + ldbg ("%s\n", __FUNCTION__); + mutex_lock(&io_mutex); + ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key); + if (ret) + printk(KERN_ERR "wm8350: lock failed\n"); + mutex_unlock(&io_mutex); + return ret; +} +EXPORT_SYMBOL_GPL(wm8350_reg_lock); + +int wm8350_reg_unlock(struct wm8350 *wm8350) +{ + u16 key = WM8350_UNLOCK_KEY; + int ret; + + ldbg ("%s\n", __FUNCTION__); + mutex_lock(&io_mutex); + ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key); + if (ret) + printk(KERN_ERR "wm8350: unlock failed\n"); + mutex_unlock(&io_mutex); + return ret; +} +EXPORT_SYMBOL_GPL(wm8350_reg_unlock); + +/* + * For Switching between SPI and I2C IO + */ +int wm8350_set_io(struct wm8350 *wm8350, int io, wm8350_hw_read_t read_dev, + wm8350_hw_write_t write_dev) +{ + mutex_lock(&io_mutex); + switch (io) { + case WM8350_IO_I2C: +#ifdef CONFIG_I2C + wm8350->read_dev = wm8350_read_i2c_device; + wm8350->write_dev = wm8350_write_i2c_device; + break; +#else + printk(KERN_ERR "wm8350: I2C not selected.\n"); + wm8350->read_dev = NULL; + wm8350->write_dev = NULL; + mutex_unlock(&io_mutex); + return -EINVAL; +#endif + case WM8350_IO_SPI: +#ifdef CONFIG_SPI + wm8350->read_dev = wm8350_read_spi_device; + wm8350->write_dev = wm8350_write_spi_device; + break; +#else + printk(KERN_ERR "wm8350: SPI not selected.\n"); + wm8350->read_dev = NULL; + wm8350->write_dev = NULL; + mutex_unlock(&io_mutex); + return -EINVAL; +#endif + default: + printk(KERN_ERR "wm8350: invalid IO mechanism\n"); + wm8350->read_dev = NULL; + wm8350->write_dev = NULL; + mutex_unlock(&io_mutex); + return -EINVAL; + } + mutex_unlock(&io_mutex); + return 0; +} +EXPORT_SYMBOL_GPL(wm8350_set_io); + +/* + * Cache is always host endian. + */ +int wm8350_create_cache(struct wm8350 *wm8350) +{ + int i, ret = 0; + u16 value; + + if (wm8350->read_dev == NULL) + return -ENODEV; + + wm8350->reg_cache = + kzalloc(sizeof(u16) * (WM8350_MAX_REGISTER + 1), GFP_KERNEL); + if (wm8350->reg_cache == NULL) + return -ENOMEM; + + /* TODO: check if we are virgin state so we don't have to do this */ + /* refresh cache with chip regs as some registers can survive reboot */ + for (i = 0; i < WM8350_MAX_REGISTER; i++) { + /* audio register range */ + if (wm8350_reg_io_map[i].readable && + (i < WM8350_CLOCK_CONTROL_1 || i > WM8350_AIF_TEST)) { + ret = wm8350->read_dev(wm8350, i, 2, (char*)&value); + if (ret < 0) { + printk(KERN_ERR + "wm8350: failed to create cache\n"); + goto out; + } + wm8350_endian_swap(i, 2, &value); + wm8350_mask_read(i, 2, &value); + wm8350->reg_cache[i] = value; + } else + wm8350->reg_cache[i] = wm8350_reg_map[i]; + } + +out: + return ret; +} +EXPORT_SYMBOL_GPL(wm8350_create_cache); + + +static void wm8350_irq_call_worker(struct wm8350 *wm8350, int irq) +{ + mutex_lock(&wm8350->work_mutex); + + if (wm8350->irq[irq].handler) + wm8350->irq[irq].handler(wm8350, irq, wm8350->irq[irq].data); + else { + mutex_unlock(&wm8350->work_mutex); + printk(KERN_ERR "wm8350: irq %d nobody cared. now masked.\n", + irq); + wm8350_mask_irq(wm8350, irq); + return; + } + mutex_unlock(&wm8350->work_mutex); +} + +void wm8350_irq_worker(struct work_struct *work) +{ + u16 level_one, status1, status2, comp, oc, gpio, uv; + struct wm8350 *wm8350 = + container_of(work, struct wm8350, work); + + if (wm8350_in_suspend) { + wm8350_in_suspend = 0; + return; + } + + /* read this in 1 block read */ + /* read 1st level irq sources and then read required 2nd sources */ + level_one = wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS) + & ~wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK); + uv = wm8350_reg_read(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS) + & ~wm8350_reg_read(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK); + oc = wm8350_reg_read(wm8350, WM8350_OVER_CURRENT_INTERRUPT_STATUS) + & ~wm8350_reg_read(wm8350, WM8350_OVER_CURRENT_INTERRUPT_STATUS_MASK); + status1 = wm8350_reg_read(wm8350, WM8350_INTERRUPT_STATUS_1) + & ~wm8350_reg_read(wm8350, WM8350_INTERRUPT_STATUS_1_MASK); + status2 = wm8350_reg_read(wm8350, WM8350_INTERRUPT_STATUS_2) + & ~wm8350_reg_read(wm8350, WM8350_INTERRUPT_STATUS_2_MASK); + comp = wm8350_reg_read(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS) + & ~wm8350_reg_read(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK); + gpio = wm8350_reg_read(wm8350, WM8350_GPIO_INTERRUPT_STATUS) + & ~wm8350_reg_read(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK); + + /* over current */ + if (level_one & WM8350_OC_INT) { + if (oc & WM8350_OC_LS_EINT) /* limit switch */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_OC_LS); + } + + /* under voltage */ + if (level_one & WM8350_UV_INT) { + if (uv & WM8350_UV_DC1_EINT) /* DCDC1 */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_UV_DC1); + if (uv & WM8350_UV_DC2_EINT) /* DCDC2 */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_UV_DC2); + if (uv & WM8350_UV_DC3_EINT) /* DCDC3 */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_UV_DC3); + if (uv & WM8350_UV_DC4_EINT) /* DCDC4 */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_UV_DC4); + if (uv & WM8350_UV_DC5_EINT) /* DCDC5 */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_UV_DC5); + if (uv & WM8350_UV_DC6_EINT) /* DCDC6 */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_UV_DC6); + if (uv & WM8350_UV_LDO1_EINT) /* LDO1 */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_UV_LDO1); + if (uv & WM8350_UV_LDO2_EINT) /* LDO2 */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_UV_LDO2); + if (uv & WM8350_UV_LDO3_EINT) /* LDO3 */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_UV_LDO3); + if (uv & WM8350_UV_LDO4_EINT) /* LDO4 */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_UV_LDO4); + } + + /* charger, RTC */ + if (status1) { + if (status1 & WM8350_CHG_BAT_HOT_EINT) /* battery too hot */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_CHG_BAT_HOT); + if (status1 & WM8350_CHG_BAT_COLD_EINT) /* battery too cold */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_CHG_BAT_COLD); + if (status1 & WM8350_CHG_BAT_FAIL_EINT) /* battery fail */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_CHG_BAT_FAIL); + if (status1 & WM8350_CHG_TO_EINT) /* charger timeout */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_CHG_TO); + if (status1 & WM8350_CHG_END_EINT) /* fast charge current */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_CHG_END); + if (status1 & WM8350_CHG_START_EINT) /* charging started */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_CHG_START); + if (status1 & WM8350_CHG_FAST_RDY_EINT) /* fast charge ready */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_CHG_FAST_RDY); + if (status1 & WM8350_CHG_VBATT_LT_3P9_EINT) /* battery voltage < 3.9 */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_CHG_VBATT_LT_3P9); + if (status1 & WM8350_CHG_VBATT_LT_3P1_EINT) /* battery voltage < 3.1 */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_CHG_VBATT_LT_3P1); + if (status1 & WM8350_CHG_VBATT_LT_2P85_EINT) /* battery voltage < 2.85 */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_CHG_VBATT_LT_2P85); + + if (status1 & WM8350_RTC_ALM_EINT) /* alarm */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_RTC_ALM); + if (status1 & WM8350_RTC_SEC_EINT) /* second rollover */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_RTC_SEC); + if (status1 & WM8350_RTC_PER_EINT) /* periodic */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_RTC_PER); + } + + /* current sink, system, aux adc */ + if (status2) { + if (status2 & WM8350_CS1_EINT) /* current sink 1 */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_CS1); + if (status2 & WM8350_CS2_EINT) /* current sink 2 */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_CS2); + + if (status2 & WM8350_SYS_HYST_COMP_FAIL_EINT) /* comp fail */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_SYS_HYST_COMP_FAIL); + if (status2 & WM8350_SYS_CHIP_GT115_EINT) /* chip > 115 C */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_SYS_CHIP_GT115); + if (status2 & WM8350_SYS_CHIP_GT140_EINT) /* chip > 140 C */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_SYS_CHIP_GT140); + if (status2 & WM8350_SYS_WDOG_TO_EINT) /* heartbeat missed */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_SYS_WDOG_TO); + + if (status2 & WM8350_AUXADC_DATARDY_EINT) /* data ready */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_AUXADC_DATARDY); + if (status2 & WM8350_AUXADC_DCOMP4_EINT) /* exceeds comp 4 */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_AUXADC_DCOMP4); + if (status2 & WM8350_AUXADC_DCOMP3_EINT) /* exceeds comp 3 */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_AUXADC_DCOMP3); + if (status2 & WM8350_AUXADC_DCOMP2_EINT) /* exceeds comp 2 */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_AUXADC_DCOMP2); + if (status2 & WM8350_AUXADC_DCOMP1_EINT) /* exceeds comp 1 */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_AUXADC_DCOMP1); + + if (status2 & WM8350_USB_LIMIT_EINT) /* usb limit */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_USB_LIMIT); + } + + /* wake, codec, ext */ + if (comp) { + if (comp & WM8350_WKUP_OFF_STATE_EINT) /* wake from off */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_WKUP_OFF_STATE); + if (comp & WM8350_WKUP_HIB_STATE_EINT) /* wake from hibernate */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_WKUP_HIB_STATE); + if (comp & WM8350_WKUP_CONV_FAULT_EINT) /* wake from fault */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_WKUP_CONV_FAULT); + if (comp & WM8350_WKUP_WDOG_RST_EINT) /* wake from reset */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_WKUP_WDOG_RST); + if (comp & WM8350_WKUP_GP_PWR_ON_EINT) /* power on changed */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_WKUP_GP_PWR_ON); + if (comp & WM8350_WKUP_ONKEY_EINT) /* on key > specified time */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_WKUP_ONKEY); + if (comp & WM8350_WKUP_GP_WAKEUP_EINT) /* wake from GPIO */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_WKUP_GP_WAKEUP); + + if (comp & WM8350_CODEC_JCK_DET_L_EINT) /* left chn Jack detect */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_CODEC_JCK_DET_L); + if (comp & WM8350_CODEC_JCK_DET_R_EINT) /* right chn Jack detect */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_CODEC_JCK_DET_R); + if (comp & WM8350_CODEC_MICSCD_EINT) /* mic detect */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_CODEC_MICSCD); + if (comp & WM8350_CODEC_MICD_EINT) /* mic short circuit */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_CODEC_MICD); + + if (comp & WM8350_EXT_USB_FB_EINT) /* usb connect */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_EXT_USB_FB); + if (comp & WM8350_EXT_WALL_FB_EINT) /* wall adaptor connect */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_EXT_WALL_FB); + if (comp & WM8350_EXT_BAT_FB_EINT) /* battery insertion */ + wm8350_irq_call_worker(wm8350, WM8350_IRQ_EXT_BAT_FB); + } + + if (level_one & WM8350_GP_INT) { /* gpio */ + int i; + + for (i = 0; i < 12; i++) { + if (gpio & (1 << i)) + wm8350_irq_call_worker(wm8350, WM8350_IRQ_GPIO(i)); + } + } +} +EXPORT_SYMBOL_GPL(wm8350_irq_worker); + +int wm8350_register_irq(struct wm8350 *wm8350, int irq, + void (*handler)(struct wm8350 *, int, void*), void *data) +{ + if (irq < 0 || irq > WM8350_NUM_IRQ || !handler) + return -EINVAL; + + if (wm8350->irq[irq].handler) + return -EBUSY; + + mutex_lock(&wm8350->work_mutex); + wm8350->irq[irq].handler = handler; + wm8350->irq[irq].data = data; + mutex_unlock(&wm8350->work_mutex); + return 0; +} +EXPORT_SYMBOL_GPL(wm8350_register_irq); + +int wm8350_free_irq(struct wm8350 *wm8350, int irq) +{ + if (irq < 0 || irq > WM8350_NUM_IRQ) + return -EINVAL; + + mutex_lock(&wm8350->work_mutex); + wm8350->irq[irq].handler = NULL; + mutex_unlock(&wm8350->work_mutex); + return 0; +} +EXPORT_SYMBOL_GPL(wm8350_free_irq); + +int wm8350_mask_irq(struct wm8350 *wm8350, int irq) +{ + switch (irq) { + case WM8350_IRQ_CHG_BAT_HOT: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_BAT_HOT_EINT); + case WM8350_IRQ_CHG_BAT_COLD: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_BAT_COLD_EINT); + case WM8350_IRQ_CHG_BAT_FAIL: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_BAT_FAIL_EINT); + case WM8350_IRQ_CHG_TO: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_TO_EINT); + case WM8350_IRQ_CHG_END: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_END_EINT); + case WM8350_IRQ_CHG_START: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_START_EINT); + case WM8350_IRQ_CHG_FAST_RDY: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_FAST_RDY_EINT); + case WM8350_IRQ_RTC_PER: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_RTC_PER_EINT); + case WM8350_IRQ_RTC_SEC: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_RTC_SEC_EINT); + case WM8350_IRQ_RTC_ALM: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_RTC_ALM_EINT); + case WM8350_IRQ_CHG_VBATT_LT_3P9: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_VBATT_LT_3P9_EINT); + case WM8350_IRQ_CHG_VBATT_LT_3P1: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_VBATT_LT_3P1_EINT); + case WM8350_IRQ_CHG_VBATT_LT_2P85: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_VBATT_LT_2P85_EINT); + case WM8350_IRQ_CS1: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_CS1_EINT); + case WM8350_IRQ_CS2: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_CS2_EINT); + case WM8350_IRQ_USB_LIMIT: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_USB_LIMIT_EINT); + case WM8350_IRQ_AUXADC_DATARDY: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_AUXADC_DATARDY_EINT); + case WM8350_IRQ_AUXADC_DCOMP4: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_AUXADC_DCOMP4_EINT); + case WM8350_IRQ_AUXADC_DCOMP3: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_AUXADC_DCOMP3_EINT); + case WM8350_IRQ_AUXADC_DCOMP2: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_AUXADC_DCOMP2_EINT); + case WM8350_IRQ_AUXADC_DCOMP1: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_AUXADC_DCOMP1_EINT); + case WM8350_IRQ_SYS_HYST_COMP_FAIL: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_SYS_HYST_COMP_FAIL_EINT); + case WM8350_IRQ_SYS_CHIP_GT115: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_SYS_CHIP_GT115_EINT); + case WM8350_IRQ_SYS_CHIP_GT140: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_SYS_CHIP_GT140_EINT); + case WM8350_IRQ_SYS_WDOG_TO: + return wm8350_set_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_SYS_WDOG_TO_EINT); + case WM8350_IRQ_UV_LDO4: + return wm8350_set_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_LDO4_EINT); + case WM8350_IRQ_UV_LDO3: + return wm8350_set_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_LDO3_EINT); + case WM8350_IRQ_UV_LDO2: + return wm8350_set_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_LDO2_EINT); + case WM8350_IRQ_UV_LDO1: + return wm8350_set_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_LDO1_EINT); + case WM8350_IRQ_UV_DC6: + return wm8350_set_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_DC6_EINT); + case WM8350_IRQ_UV_DC5: + return wm8350_set_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_DC5_EINT); + case WM8350_IRQ_UV_DC4: + return wm8350_set_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_DC4_EINT); + case WM8350_IRQ_UV_DC3: + return wm8350_set_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_DC3_EINT); + case WM8350_IRQ_UV_DC2: + return wm8350_set_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_DC2_EINT); + case WM8350_IRQ_UV_DC1: + return wm8350_set_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_DC1_EINT); + case WM8350_IRQ_OC_LS: + return wm8350_set_bits(wm8350, WM8350_OVER_CURRENT_INTERRUPT_STATUS_MASK, + WM8350_IM_OC_LS_EINT); + case WM8350_IRQ_EXT_USB_FB: + return wm8350_set_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_EXT_USB_FB_EINT); + case WM8350_IRQ_EXT_WALL_FB: + return wm8350_set_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_EXT_WALL_FB_EINT); + case WM8350_IRQ_EXT_BAT_FB: + return wm8350_set_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_EXT_BAT_FB_EINT); + case WM8350_IRQ_CODEC_JCK_DET_L: + return wm8350_set_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_CODEC_JCK_DET_L_EINT); + case WM8350_IRQ_CODEC_JCK_DET_R: + return wm8350_set_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_CODEC_JCK_DET_R_EINT); + case WM8350_IRQ_CODEC_MICSCD: + return wm8350_set_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_CODEC_MICSCD_EINT); + case WM8350_IRQ_CODEC_MICD: + return wm8350_set_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_CODEC_MICD_EINT); + case WM8350_IRQ_WKUP_OFF_STATE: + return wm8350_set_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_WKUP_OFF_STATE_EINT); + case WM8350_IRQ_WKUP_HIB_STATE: + return wm8350_set_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_WKUP_HIB_STATE_EINT); + case WM8350_IRQ_WKUP_CONV_FAULT: + return wm8350_set_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_WKUP_CONV_FAULT_EINT); + case WM8350_IRQ_WKUP_WDOG_RST: + return wm8350_set_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_WKUP_OFF_STATE_EINT); + case WM8350_IRQ_WKUP_GP_PWR_ON: + return wm8350_set_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_WKUP_GP_PWR_ON_EINT); + case WM8350_IRQ_WKUP_ONKEY: + return wm8350_set_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_WKUP_ONKEY_EINT); + case WM8350_IRQ_WKUP_GP_WAKEUP: + return wm8350_set_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_WKUP_GP_WAKEUP_EINT); + case WM8350_IRQ_GPIO(0): + return wm8350_set_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP0_EINT); + case WM8350_IRQ_GPIO(1): + return wm8350_set_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP1_EINT); + case WM8350_IRQ_GPIO(2): + return wm8350_set_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP2_EINT); + case WM8350_IRQ_GPIO(3): + return wm8350_set_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP3_EINT); + case WM8350_IRQ_GPIO(4): + return wm8350_set_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP4_EINT); + case WM8350_IRQ_GPIO(5): + return wm8350_set_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP5_EINT); + case WM8350_IRQ_GPIO(6): + return wm8350_set_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP6_EINT); + case WM8350_IRQ_GPIO(7): + return wm8350_set_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP7_EINT); + case WM8350_IRQ_GPIO(8): + return wm8350_set_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP8_EINT); + case WM8350_IRQ_GPIO(9): + return wm8350_set_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP9_EINT); + case WM8350_IRQ_GPIO(10): + return wm8350_set_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP10_EINT); + case WM8350_IRQ_GPIO(11): + return wm8350_set_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP11_EINT); + case WM8350_IRQ_GPIO(12): + return wm8350_set_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP12_EINT); + default: + return -EINVAL; + } + return 0; +} +EXPORT_SYMBOL_GPL(wm8350_mask_irq); + +int wm8350_unmask_irq(struct wm8350 *wm8350, int irq) +{ + switch (irq) { + case WM8350_IRQ_CHG_BAT_HOT: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_BAT_HOT_EINT); + case WM8350_IRQ_CHG_BAT_COLD: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_BAT_COLD_EINT); + case WM8350_IRQ_CHG_BAT_FAIL: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_BAT_FAIL_EINT); + case WM8350_IRQ_CHG_TO: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_TO_EINT); + case WM8350_IRQ_CHG_END: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_END_EINT); + case WM8350_IRQ_CHG_START: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_START_EINT); + case WM8350_IRQ_CHG_FAST_RDY: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_FAST_RDY_EINT); + case WM8350_IRQ_RTC_PER: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_RTC_PER_EINT); + case WM8350_IRQ_RTC_SEC: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_RTC_SEC_EINT); + case WM8350_IRQ_RTC_ALM: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_RTC_ALM_EINT); + case WM8350_IRQ_CHG_VBATT_LT_3P9: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_VBATT_LT_3P9_EINT); + case WM8350_IRQ_CHG_VBATT_LT_3P1: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_VBATT_LT_3P1_EINT); + case WM8350_IRQ_CHG_VBATT_LT_2P85: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_1_MASK, + WM8350_IM_CHG_VBATT_LT_2P85_EINT); + case WM8350_IRQ_CS1: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_CS1_EINT); + case WM8350_IRQ_CS2: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_CS2_EINT); + case WM8350_IRQ_USB_LIMIT: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_USB_LIMIT_EINT); + case WM8350_IRQ_AUXADC_DATARDY: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_AUXADC_DATARDY_EINT); + case WM8350_IRQ_AUXADC_DCOMP4: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_AUXADC_DCOMP4_EINT); + case WM8350_IRQ_AUXADC_DCOMP3: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_AUXADC_DCOMP3_EINT); + case WM8350_IRQ_AUXADC_DCOMP2: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_AUXADC_DCOMP2_EINT); + case WM8350_IRQ_AUXADC_DCOMP1: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_AUXADC_DCOMP1_EINT); + case WM8350_IRQ_SYS_HYST_COMP_FAIL: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_SYS_HYST_COMP_FAIL_EINT); + case WM8350_IRQ_SYS_CHIP_GT115: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_SYS_CHIP_GT115_EINT); + case WM8350_IRQ_SYS_CHIP_GT140: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_SYS_CHIP_GT140_EINT); + case WM8350_IRQ_SYS_WDOG_TO: + return wm8350_clear_bits(wm8350, WM8350_INTERRUPT_STATUS_2_MASK, + WM8350_IM_SYS_WDOG_TO_EINT); + case WM8350_IRQ_UV_LDO4: + return wm8350_clear_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_LDO4_EINT); + case WM8350_IRQ_UV_LDO3: + return wm8350_clear_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_LDO3_EINT); + case WM8350_IRQ_UV_LDO2: + return wm8350_clear_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_LDO2_EINT); + case WM8350_IRQ_UV_LDO1: + return wm8350_clear_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_LDO1_EINT); + case WM8350_IRQ_UV_DC6: + return wm8350_clear_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_DC6_EINT); + case WM8350_IRQ_UV_DC5: + return wm8350_clear_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_DC5_EINT); + case WM8350_IRQ_UV_DC4: + return wm8350_clear_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_DC4_EINT); + case WM8350_IRQ_UV_DC3: + return wm8350_clear_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_DC3_EINT); + case WM8350_IRQ_UV_DC2: + return wm8350_clear_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_DC2_EINT); + case WM8350_IRQ_UV_DC1: + return wm8350_clear_bits(wm8350, WM8350_UNDER_VOLTAGE_INTERRUPT_STATUS_MASK, + WM8350_IM_UV_DC1_EINT); + case WM8350_IRQ_OC_LS: + return wm8350_clear_bits(wm8350, WM8350_OVER_CURRENT_INTERRUPT_STATUS_MASK, + WM8350_IM_OC_LS_EINT); + case WM8350_IRQ_EXT_USB_FB: + return wm8350_clear_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_EXT_USB_FB_EINT); + case WM8350_IRQ_EXT_WALL_FB: + return wm8350_clear_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_EXT_WALL_FB_EINT); + case WM8350_IRQ_EXT_BAT_FB: + return wm8350_clear_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_EXT_BAT_FB_EINT); + case WM8350_IRQ_CODEC_JCK_DET_L: + return wm8350_clear_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_CODEC_JCK_DET_L_EINT); + case WM8350_IRQ_CODEC_JCK_DET_R: + return wm8350_clear_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_CODEC_JCK_DET_R_EINT); + case WM8350_IRQ_CODEC_MICSCD: + return wm8350_clear_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_CODEC_MICSCD_EINT); + case WM8350_IRQ_CODEC_MICD: + return wm8350_clear_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_CODEC_MICD_EINT); + case WM8350_IRQ_WKUP_OFF_STATE: + return wm8350_clear_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_WKUP_OFF_STATE_EINT); + case WM8350_IRQ_WKUP_HIB_STATE: + return wm8350_clear_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_WKUP_HIB_STATE_EINT); + case WM8350_IRQ_WKUP_CONV_FAULT: + return wm8350_clear_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_WKUP_CONV_FAULT_EINT); + case WM8350_IRQ_WKUP_WDOG_RST: + return wm8350_clear_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_WKUP_OFF_STATE_EINT); + case WM8350_IRQ_WKUP_GP_PWR_ON: + return wm8350_clear_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_WKUP_GP_PWR_ON_EINT); + case WM8350_IRQ_WKUP_ONKEY: + return wm8350_clear_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_WKUP_ONKEY_EINT); + case WM8350_IRQ_WKUP_GP_WAKEUP: + return wm8350_clear_bits(wm8350, WM8350_COMPARATOR_INTERRUPT_STATUS_MASK, + WM8350_IM_WKUP_GP_WAKEUP_EINT); + case WM8350_IRQ_GPIO(0): + return wm8350_clear_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP0_EINT); + case WM8350_IRQ_GPIO(1): + return wm8350_clear_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP1_EINT); + case WM8350_IRQ_GPIO(2): + return wm8350_clear_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP2_EINT); + case WM8350_IRQ_GPIO(3): + return wm8350_clear_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP3_EINT); + case WM8350_IRQ_GPIO(4): + return wm8350_clear_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP4_EINT); + case WM8350_IRQ_GPIO(5): + return wm8350_clear_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP5_EINT); + case WM8350_IRQ_GPIO(6): + return wm8350_clear_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP6_EINT); + case WM8350_IRQ_GPIO(7): + return wm8350_clear_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP7_EINT); + case WM8350_IRQ_GPIO(8): + return wm8350_clear_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP8_EINT); + case WM8350_IRQ_GPIO(9): + return wm8350_clear_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP9_EINT); + case WM8350_IRQ_GPIO(10): + return wm8350_clear_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP10_EINT); + case WM8350_IRQ_GPIO(11): + return wm8350_clear_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP11_EINT); + case WM8350_IRQ_GPIO(12): + return wm8350_clear_bits(wm8350, WM8350_GPIO_INTERRUPT_STATUS_MASK, + WM8350_IM_GP12_EINT); + default: + return -EINVAL; + } + return 0; +} +EXPORT_SYMBOL_GPL(wm8350_unmask_irq); + +static int gpio_set_dir(struct wm8350 *wm8350, int gpio, int dir) +{ + int ret; + + wm8350_reg_unlock(wm8350); + if (dir == WM8350_GPIO_DIR_OUT) + ret = wm8350_clear_bits(wm8350, + WM8350_GPIO_CONFIGURATION_I_O, 1 << gpio); + else + ret = wm8350_set_bits(wm8350, + WM8350_GPIO_CONFIGURATION_I_O, 1 << gpio); + wm8350_reg_lock(wm8350); + return ret; +} + +static int gpio_set_debounce(struct wm8350 *wm8350, int gpio, int db) +{ + if (db == WM8350_GPIO_DEBOUNCE_ON) + return wm8350_set_bits(wm8350, + WM8350_GPIO_DEBOUNCE, 1 << gpio); + else + return wm8350_clear_bits(wm8350, + WM8350_GPIO_DEBOUNCE, 1 << gpio); +} + +static int gpio_set_func(struct wm8350 *wm8350, int gpio, int func) +{ + u16 reg; + + wm8350_reg_unlock(wm8350); + switch (gpio) { + case 0: + reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1) + & ~WM8350_GP0_FN_MASK; + wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_1, + reg | ((func & 0xf) << 0)); + break; + case 1: + reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1) + & ~WM8350_GP1_FN_MASK; + wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_1, + reg | ((func & 0xf) << 4)); + break; + case 2: + reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1) + & ~WM8350_GP2_FN_MASK; + wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_1, + reg | ((func & 0xf) << 8)); + break; + case 3: + reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1) + & ~WM8350_GP3_FN_MASK; + wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_1, + reg | ((func & 0xf) << 12)); + break; + case 4: + reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2) + & ~WM8350_GP4_FN_MASK; + wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_2, + reg | ((func & 0xf) << 0)); + break; + case 5: + reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2) + & ~WM8350_GP5_FN_MASK; + wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_2, + reg | ((func & 0xf) << 4)); + break; + case 6: + reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2) + & ~WM8350_GP6_FN_MASK; + wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_2, + reg | ((func & 0xf) << 8)); + break; + case 7: + reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2) + & ~WM8350_GP7_FN_MASK; + wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_2, + reg | ((func & 0xf) << 12)); + break; + case 8: + reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3) + & ~WM8350_GP8_FN_MASK; + wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_3, + reg | ((func & 0xf) << 0)); + break; + case 9: + reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3) + & ~WM8350_GP9_FN_MASK; + wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_3, + reg | ((func & 0xf) << 4)); + break; + case 10: + reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3) + & ~WM8350_GP10_FN_MASK; + wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_3, + reg | ((func & 0xf) << 8)); + break; + case 11: + reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3) + & ~WM8350_GP11_FN_MASK; + wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_3, + reg | ((func & 0xf) << 12)); + break; + case 12: + reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_4) + & ~WM8350_GP12_FN_MASK; + wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_4, + reg | ((func & 0xf) << 0)); + break; + default: + wm8350_reg_lock(wm8350); + return -EINVAL; + } + + wm8350_reg_lock(wm8350); + return 0; +} + +int wm8350_gpio_set_status(struct wm8350 *wm8350, int gpio, int status) +{ + if (status) + return wm8350_set_bits(wm8350, + WM8350_GPIO_PIN_STATUS, 1 << gpio); + else + return wm8350_clear_bits(wm8350, + WM8350_GPIO_PIN_STATUS, 1 << gpio); +} +EXPORT_SYMBOL_GPL(wm8350_gpio_set_status); + +int wm8350_gpio_get_status(struct wm8350 *wm8350, int gpio) +{ + return (wm8350_reg_read(wm8350, WM8350_GPIO_PIN_STATUS) & + (1 << gpio)) ? 1: 0; +} +EXPORT_SYMBOL_GPL(wm8350_gpio_get_status); + +static int gpio_set_pull_up(struct wm8350 *wm8350, int gpio, int up) +{ + if (up) + return wm8350_set_bits(wm8350, + WM8350_GPIO_PIN_PULL_UP_CONTROL, 1 << gpio); + else + return wm8350_clear_bits(wm8350, + WM8350_GPIO_PIN_PULL_UP_CONTROL, 1 << gpio); +} + +static int gpio_set_pull_down(struct wm8350 *wm8350, int gpio, int down) +{ + if (down) + return wm8350_set_bits(wm8350, + WM8350_GPIO_PULL_DOWN_CONTROL, 1 << gpio); + else + return wm8350_clear_bits(wm8350, + WM8350_GPIO_PULL_DOWN_CONTROL, 1 << gpio); +} + +static int gpio_set_polarity(struct wm8350 *wm8350, int gpio, int pol) +{ + if (pol == WM8350_GPIO_ACTIVE_HIGH) + return wm8350_set_bits(wm8350, + WM8350_GPIO_PIN_POLARITY_TYPE, 1 << gpio); + else + return wm8350_clear_bits(wm8350, + WM8350_GPIO_PIN_POLARITY_TYPE, 1 << gpio); +} + +static int gpio_set_invert(struct wm8350 *wm8350, int gpio, int invert) +{ + if (invert == WM8350_GPIO_INVERT_ON) + return wm8350_set_bits(wm8350, + WM8350_GPIO_INTERRUPT_MODE, 1 << gpio); + else + return wm8350_clear_bits(wm8350, + WM8350_GPIO_INTERRUPT_MODE, 1 << gpio); +} + +int wm8350_gpio_config(struct wm8350 *wm8350, int gpio, int dir, int func, + int pol, int pull, int invert, int debounce) +{ + /* make sure we never pull up and down at the same time */ + if (pull == WM8350_GPIO_PULL_NONE) { + if (gpio_set_pull_up(wm8350, gpio, 0)) + goto err; + if (gpio_set_pull_down(wm8350, gpio, 0)) + goto err; + } else if (pull == WM8350_GPIO_PULL_UP) { + if (gpio_set_pull_down(wm8350, gpio, 0)) + goto err; + if (gpio_set_pull_up(wm8350, gpio, 1)) + goto err; + } else if (pull == WM8350_GPIO_PULL_DOWN) { + if (gpio_set_pull_up(wm8350, gpio, 0)) + goto err; + if (gpio_set_pull_down(wm8350, gpio, 1)) + goto err; + } + + if (gpio_set_invert(wm8350, gpio, invert)) + goto err; + if (gpio_set_polarity(wm8350, gpio, pol)) + goto err; + if (gpio_set_debounce(wm8350, gpio, debounce)) + goto err; + if (gpio_set_dir(wm8350, gpio, dir)) + goto err; + return gpio_set_func(wm8350, gpio, func); + +err: + return -EIO; +} +EXPORT_SYMBOL_GPL(wm8350_gpio_config); + +int wm8350_read_auxadc(struct wm8350 *wm8350, int channel, int scale, int vref) +{ + u16 reg, result = 0; + int tries = 5; + + if (channel < WM8350_AUXADC_AUX1 || channel > WM8350_AUXADC_TEMP) + return -EINVAL; + if (channel >= WM8350_AUXADC_USB && channel <= WM8350_AUXADC_TEMP + && (scale != 0 || vref != 0)) + return -EINVAL; + + mutex_lock(&auxadc_mutex); + + /* Turn on the ADC */ + reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5); + wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5, reg | WM8350_AUXADC_ENA); + + if (scale || vref) { + reg = scale << 13; + reg |= vref << 12; + wm8350_reg_write(wm8350, WM8350_AUX1_READBACK + channel, reg); + } + + reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1); + reg |= 1 << channel | WM8350_AUXADC_POLL; + wm8350_reg_write(wm8350, WM8350_DIGITISER_CONTROL_1, reg); + + do { + schedule_timeout_interruptible(1); + reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1); + } while (tries-- && (reg & WM8350_AUXADC_POLL)); + + if (!tries) + printk (KERN_ERR "wm8350: adc chn %d read timeout\n", channel); + else + result = wm8350_reg_read(wm8350, + WM8350_AUX1_READBACK + channel); + + /* Turn off the ADC */ + reg=wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5); + wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5, reg & ~WM8350_AUXADC_ENA); + + mutex_unlock(&auxadc_mutex); + return result & WM8350_AUXADC_DATA1_MASK; +} +EXPORT_SYMBOL_GPL(wm8350_read_auxadc); + +static void wm8350_pmic_dev_release(struct device *dev){} + +int wm8350_device_register_pmic(struct wm8350 *wm8350) +{ + int ret; + + strcpy(wm8350->pmic.dev.bus_id, "wm8350-pmic"); + wm8350->pmic.dev.bus = &wm8350_bus_type; + wm8350->pmic.dev.parent = &wm8350->i2c_client->dev; + wm8350->pmic.dev.release = wm8350_pmic_dev_release; + + wm8350_in_suspend = 0; + + ret = device_register(&wm8350->pmic.dev); + if (ret < 0) + printk(KERN_ERR "failed to register WM8350 PMIC device\n"); + + return ret; +} +EXPORT_SYMBOL_GPL(wm8350_device_register_pmic); + +static void wm8350_rtc_dev_release(struct device *dev){} + +int wm8350_device_register_rtc(struct wm8350 *wm8350) +{ + int ret; + + strcpy(wm8350->rtc.dev.bus_id, "wm8350-rtc"); + wm8350->rtc.dev.bus = &wm8350_bus_type; + wm8350->rtc.dev.parent = &wm8350->i2c_client->dev; + wm8350->rtc.dev.release = wm8350_rtc_dev_release; + + ret = device_register(&wm8350->rtc.dev); + if (ret < 0) + printk(KERN_ERR "failed to register WM8350 RTC device\n"); + + return ret; +} +EXPORT_SYMBOL_GPL(wm8350_device_register_rtc); + +static void wm8350_wdg_dev_release(struct device *dev){} + +int wm8350_device_register_wdg(struct wm8350 *wm8350) +{ + int ret; + + strcpy(wm8350->wdg.dev.bus_id, "wm8350-wdt"); + wm8350->wdg.dev.bus = &wm8350_bus_type; + wm8350->wdg.dev.parent = &wm8350->i2c_client->dev; + wm8350->wdg.dev.release = wm8350_wdg_dev_release; + + ret = device_register(&wm8350->wdg.dev); + if (ret < 0) + printk(KERN_ERR "failed to register WM8350 Watchdog device\n"); + + return ret; +} +EXPORT_SYMBOL_GPL(wm8350_device_register_wdg); + +static void wm8350_power_dev_release(struct device *dev){} + +int wm8350_device_register_power(struct wm8350 *wm8350) +{ + int ret; + + strcpy(wm8350->power.dev.bus_id, "wm8350-power"); + wm8350->power.dev.bus = &wm8350_bus_type; + wm8350->power.dev.parent = &wm8350->i2c_client->dev; + wm8350->power.dev.release = wm8350_power_dev_release; + + ret = device_register(&wm8350->power.dev); + if (ret < 0) + printk(KERN_ERR "failed to register WM8350 Power device\n"); + + return ret; +} +EXPORT_SYMBOL_GPL(wm8350_device_register_power); + +static int wm8350_bus_match(struct device *dev, struct device_driver *drv) +{ + if(!strcmp(dev->bus_id, drv->name)) + return 1; + return 0; +} + +static int wm8350_bus_suspend(struct device *dev, pm_message_t state) +{ + int ret = 0; + + wm8350_in_suspend = 1; + + if (dev->driver && dev->driver->suspend) + ret = dev->driver->suspend(dev, state); + + return ret; +} + +static int wm8350_bus_resume(struct device *dev) +{ + int ret = 0; + + if (wm8350_in_suspend) + wm8350_in_suspend = 0; + else { + struct wm8350_pmic *wm8350_pmic = to_wm8350_pmic_device(dev); + struct wm8350 *wm8350 = to_wm8350_from_pmic(wm8350_pmic); + schedule_work(&wm8350->work); + } + + if (dev->driver && dev->driver->resume) + ret = dev->driver->resume(dev); + + return ret; +} + +struct bus_type wm8350_bus_type = { + .name = "wm8350", + .match = wm8350_bus_match, + .suspend = wm8350_bus_suspend, + .resume = wm8350_bus_resume, +}; +EXPORT_SYMBOL(wm8350_bus_type); + +MODULE_AUTHOR("Liam Girdwood, liam.girdwood@wolfsonmicro.com, www.wolfsonmicro.com"); +MODULE_DESCRIPTION("WM8350 PMIC Bus driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/regulator/wm8350/reg-wm8350-i2c.c linux-2.6.26-lab126/drivers/regulator/wm8350/reg-wm8350-i2c.c --- linux-2.6.26/drivers/regulator/wm8350/reg-wm8350-i2c.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/regulator/wm8350/reg-wm8350-i2c.c 2010-08-10 04:16:18.000000000 -0400 @@ -0,0 +1,185 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define WM8350_I2C_ADDR (0x34 >> 1) + +extern void wm8350_free(struct wm8350 *wm8350); +extern int wm8350_init(struct wm8350* wm8350); + + +static int wm8350_i2c_detach(struct i2c_client *client); + +void wm8350_irq_work(struct work_struct *work) +{ + wm8350_irq_worker(work); +} + +irqreturn_t wm8350_irq_handler(int irq, void *data) +{ + struct wm8350 *wm8350 = (struct wm8350*)data; + schedule_work(&wm8350->work); + return IRQ_HANDLED; +} + +/* + * WM8350 2 wire address + */ +static unsigned short normal_i2c[] = { WM8350_I2C_ADDR, I2C_CLIENT_END }; + +/* Magic definition of all other variables and things */ +I2C_CLIENT_INSMOD; + +extern int wm8350_pmu_init(void); +extern void wm8350_pmu_exit(void); + +static int wm8350_pmic_i2c_detect(struct i2c_adapter *adap, int addr, int kind) +{ + struct wm8350* wm8350; + struct i2c_client *i2c; + int ret = 0; + + if (addr != WM8350_I2C_ADDR) + return -ENODEV; + + i2c = kzalloc(sizeof(struct i2c_client), GFP_KERNEL); + if (i2c == NULL) + return -ENOMEM; + + wm8350 = kzalloc(sizeof(struct wm8350), GFP_KERNEL); + if (wm8350 == NULL) { + kfree(i2c); + return -ENOMEM; + } + + i2c->addr = addr; + i2c->adapter = adap; + + mutex_init(&wm8350->work_mutex); + i2c_set_clientdata(i2c, wm8350); + wm8350->i2c_client = i2c; + wm8350_set_io(wm8350, WM8350_IO_I2C, NULL, NULL); + + ret = i2c_attach_client(i2c); + if (ret < 0) { + printk(KERN_ERR "wm8350: failed to attach device at addr 0x%x\n", addr); + goto err; + } + + ret = wm8350_create_cache(wm8350); + if (ret < 0) { + printk(KERN_ERR "wm8350: failed to create register cache\n"); + goto err; + } + + if (wm8350_reg_read(wm8350, 0) == 0x0) + printk("wm8350: found Rev C device\n"); + else if (wm8350_reg_read(wm8350, 0) == 0x6143) + printk("wm8350: found Rev E device\n"); + else { + printk(KERN_ERR "wm8350: device is not a WM8350\n"); + ret = -ENODEV; + goto err; + } + + ret = bus_register(&wm8350_bus_type); + if (ret < 0) + goto err; + + wm8350_pmu_init(); + + ret = wm8350_init(wm8350); + if (ret == 0) + return ret; + +err: + wm8350_i2c_detach(i2c); + return ret; +} + +static int wm8350_i2c_attach(struct i2c_adapter *adap) +{ + return i2c_probe(adap, &addr_data, wm8350_pmic_i2c_detect); +} + +static int wm8350_i2c_detach(struct i2c_client *client) +{ + struct wm8350 *wm8350 = i2c_get_clientdata(client); + + wm8350_free(wm8350); + wm8350_pmu_exit(); + bus_unregister(&wm8350_bus_type); + i2c_detach_client(client); + kfree(client); + if (wm8350->reg_cache) + kfree(wm8350->reg_cache); + kfree(wm8350); + + return 0; +} + +#ifdef CONFIG_PM +static int wm8350_i2c_suspend(struct i2c_client *client, pm_message_t state) +{ + int ret = 0; + return ret; +} + +static int wm8350_i2c_resume(struct i2c_client *client) +{ + int ret = 0; + return ret; +} + +#else +#define wm8350_i2c_suspend NULL +#define wm8350_i2c_resume NULL +#endif + +static const struct i2c_device_id wm8350_id[] = { + { "WM8350", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, wm8350_id); + +static struct i2c_driver wm8350_i2c_driver = { + .driver = { + .name = "WM8350", + }, + .attach_adapter = wm8350_i2c_attach, + .detach_client = wm8350_i2c_detach, + .suspend = wm8350_i2c_suspend, + .resume = wm8350_i2c_resume, + .command = NULL, + .id_table = wm8350_id, +}; + + +static int __init wm8350_pmic_init(void) +{ + return i2c_add_driver(&wm8350_i2c_driver); +} + +static void __exit wm8350_pmic_exit(void) +{ + i2c_del_driver(&wm8350_i2c_driver); +} + +subsys_initcall(wm8350_pmic_init); +module_exit(wm8350_pmic_exit); + +MODULE_AUTHOR("Liam Girdwood"); +MODULE_DESCRIPTION("PMIC WM8350 Driver"); +MODULE_LICENSE("GPL"); + diff -urN linux-2.6.26/drivers/regulator/wm8350/reg-wm8350.c linux-2.6.26-lab126/drivers/regulator/wm8350/reg-wm8350.c --- linux-2.6.26/drivers/regulator/wm8350/reg-wm8350.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/regulator/wm8350/reg-wm8350.c 2010-08-10 04:16:18.000000000 -0400 @@ -0,0 +1,1014 @@ +/* + * wm8350_pmu.c -- Power Management Driver for Wolfson WM8350 PMIC + * + * Copyright 2007 Wolfson Microelectronics PLC. + * + * Author: Liam Girdwood + * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Revision history + * 23rd Jan 2007 Initial version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define WM8350_PMIC_VERSION "0.4" + +/* debug */ +#define WM8350_DEBUG 0 +#if WM8350_DEBUG +#define dbg(format, arg...) printk(format, ## arg) +#else +#define dbg(format, arg...) +#endif + +/* hundredths of uA, 405 = 4.05 uA */ +static const int isink_cur[] = { + 405, 482, 573, 681, 810, 963, 1146, 1362, 1620, 1927, 2291, 2725, + 3240, 3853, 4582, 5449, 6480, 7706, 9164, 10898, 12960, 15412, 18328, + 21796, 25920, 30824, 36656, 43592, 51840, 61648, 73313, 87184, + 103680, 123297, 146626, 174368, 207360, 246594, 293251, 348737, + 414720, 493188, 586503, 697473, 829440, 986376, 1173005, 1394946, + 1658880, 1972752, 2346011, 2789892, 3317760, 3945504, 4692021, + 5579785, 6635520, 7891008, 9384042, 11159570, 13271040, 15782015, + 18768085, 22319140 +}; + +static int get_isink_val(int uA) +{ + int i, huA = uA * 100; + + for (i = ARRAY_SIZE(isink_cur) - 1; i >= 0 ; i--) { + if (huA > isink_cur[i]) + return i; + } + return 0; +} + +static int wm8350_isink_set_current(struct regulator *reg, int uA) +{ + struct wm8350_pmic *pmic = (struct wm8350_pmic *)reg->reg_data; + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + int isink = reg->id; + u16 val; + + switch (isink) { + case WM8350_ISINK_A: + val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) & + ~WM8350_CS1_ISEL_MASK; + wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_A, val | + WM8350_CS1_ENABLE | get_isink_val(uA)); + break; + case WM8350_ISINK_B: + val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) & + ~WM8350_CS1_ISEL_MASK; + wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_B, val | + WM8350_CS2_ENABLE | get_isink_val(uA)); + break; + default: + return -EINVAL; + } + return 0; +} + +static int wm8350_isink_get_current(struct regulator *reg) +{ + struct wm8350_pmic *pmic = (struct wm8350_pmic *)reg->reg_data; + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + int isink = reg->id; + u16 val; + + switch (isink) { + case WM8350_ISINK_A: + val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) & + WM8350_CS1_ISEL_MASK; + break; + case WM8350_ISINK_B: + val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) & + WM8350_CS1_ISEL_MASK; + break; + default: + return 0; + } + + return val * 1000; +} + +/* turn on ISINK followed by DCDC */ +static int wm8350_isink_enable(struct regulator *reg) +{ + struct wm8350_pmic *pmic = (struct wm8350_pmic *)reg->reg_data; + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + int isink = reg->id; + + /* TODO: add ISINK's C,D,E */ + switch (isink) { + case WM8350_ISINK_A: + switch (pmic->isink_A_dcdc) { + case WM8350_DCDC_2: + case WM8350_DCDC_5: + wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7, + WM8350_CS1_ENA); + wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, + 1 << (pmic->isink_A_dcdc - WM8350_DCDC_1)); + break; + default: + return -EINVAL; + } + break; + case WM8350_ISINK_B: + switch (pmic->isink_B_dcdc) { + case WM8350_DCDC_2: + case WM8350_DCDC_5: + wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7, + WM8350_CS2_ENA); + wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, + 1 << (pmic->isink_B_dcdc - WM8350_DCDC_1)); + break; + default: + return -EINVAL; + } + break; + default: + return -EINVAL; + } + + return 0; +} + +static int wm8350_isink_disable(struct regulator *reg) +{ + struct wm8350_pmic *pmic = (struct wm8350_pmic *)reg->reg_data; + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + int isink = reg->id; + + /* TODO: add ISINK's C,D,E */ + switch (isink) { + case WM8350_ISINK_A: + switch (pmic->isink_A_dcdc) { + case WM8350_DCDC_2: + case WM8350_DCDC_5: + wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, + 1 << (pmic->isink_A_dcdc - WM8350_DCDC_1)); + wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7, + WM8350_CS1_ENA); + break; + default: + return -EINVAL; + } + break; + case WM8350_ISINK_B: + switch (pmic->isink_B_dcdc) { + case WM8350_DCDC_2: + case WM8350_DCDC_5: + wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, + 1 << (pmic->isink_B_dcdc - WM8350_DCDC_1)); + wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7, + WM8350_CS2_ENA); + break; + default: + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return -EINVAL; +} + +int wm8350_isink_set_flash(struct wm8350_pmic *pmic, int isink, u16 mode, + u16 trigger, u16 duration, u16 on_ramp, u16 off_ramp, u16 drive) +{ + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + + switch (isink) { + case WM8350_ISINK_A: + wm8350_reg_write(wm8350, WM8350_CSA_FLASH_CONTROL, + (mode ? WM8350_CS1_FLASH_MODE : 0) | + (trigger ? WM8350_CS1_TRIGSRC : 0) | + duration | on_ramp | off_ramp | drive); + break; + case WM8350_ISINK_B: + wm8350_reg_write(wm8350, WM8350_CSB_FLASH_CONTROL, + (mode ? WM8350_CS2_FLASH_MODE : 0) | + (trigger ? WM8350_CS2_TRIGSRC : 0) | + duration | on_ramp | off_ramp | drive); + break; + default: + return -EINVAL; + } + return 0; +} +EXPORT_SYMBOL_GPL(wm8350_isink_set_flash); + +int wm8350_isink_trigger_flash(struct wm8350_pmic *pmic, int isink) +{ + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + u16 val; + + switch (isink) { + case WM8350_ISINK_A: + val = wm8350_reg_read(wm8350, WM8350_CSA_FLASH_CONTROL) & + ~WM8350_CS1_DRIVE; + wm8350_reg_write(wm8350, WM8350_CSA_FLASH_CONTROL, val | + WM8350_CS1_DRIVE); + break; + case WM8350_ISINK_B: + val = wm8350_reg_read(wm8350, WM8350_CSA_FLASH_CONTROL) & + ~WM8350_CS2_DRIVE; + wm8350_reg_write(wm8350, WM8350_CSA_FLASH_CONTROL, val | + WM8350_CS2_DRIVE); + break; + default: + return -EINVAL; + } + return 0; +} + +static int wm8350_dcdc_set_voltage(struct regulator *reg, int uV) +{ + struct wm8350_pmic *pmic = (struct wm8350_pmic *)reg->reg_data; + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + int volt_reg, dcdc = reg->id, mV = uV / 1000; + u16 val; + + dbg("%s %d mV %d\n", __FUNCTION__, dcdc, mV); + + switch (dcdc) { + case WM8350_DCDC_1: + volt_reg = WM8350_DCDC1_CONTROL; + break; + case WM8350_DCDC_3: + volt_reg = WM8350_DCDC3_CONTROL; + break; + case WM8350_DCDC_4: + volt_reg = WM8350_DCDC4_CONTROL; + break; + case WM8350_DCDC_6: + volt_reg = WM8350_DCDC6_CONTROL; + break; + case WM8350_DCDC_2: + case WM8350_DCDC_5: + default: + return -EINVAL; + } + + /* all DCDC's have same mV bits */ + val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK; + wm8350_reg_write(wm8350, volt_reg, val | WM8350_DC1_VSEL(mV)); + return 0; +} + +static int wm8350_dcdc_get_voltage(struct regulator *reg) +{ + struct wm8350_pmic *pmic = (struct wm8350_pmic *)reg->reg_data; + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + int volt_reg, dcdc = reg->id; + u16 val; + + switch (dcdc) { + case WM8350_DCDC_1: + volt_reg = WM8350_DCDC1_CONTROL; + break; + case WM8350_DCDC_3: + volt_reg = WM8350_DCDC3_CONTROL; + break; + case WM8350_DCDC_4: + volt_reg = WM8350_DCDC4_CONTROL; + break; + case WM8350_DCDC_6: + volt_reg = WM8350_DCDC6_CONTROL; + break; + case WM8350_DCDC_2: + case WM8350_DCDC_5: + default: + return -EINVAL; + } + + /* all DCDC's have same mV bits */ + val = wm8350_reg_read(wm8350, volt_reg) & WM8350_DC1_VSEL_MASK; + return WM8350_DC6_VSEL_V(val) * 1000; +} + +int wm8350_dcdc_set_image_voltage(struct wm8350_pmic *pmic, int dcdc, int mV, + int mode, int signal) +{ + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + int volt_reg; + + dbg("%s %d mV %d\n", __FUNCTION__, dcdc, mV); + + switch (dcdc) { + case WM8350_DCDC_1: + volt_reg = WM8350_DCDC1_LOW_POWER; + break; + case WM8350_DCDC_3: + volt_reg = WM8350_DCDC3_LOW_POWER; + break; + case WM8350_DCDC_4: + volt_reg = WM8350_DCDC4_LOW_POWER; + break; + case WM8350_DCDC_6: + volt_reg = WM8350_DCDC6_LOW_POWER; + break; + case WM8350_DCDC_2: + case WM8350_DCDC_5: + default: + return -EINVAL; + } + + /* all DCDC's have same mV bits */ + wm8350_reg_write(wm8350, volt_reg, WM8350_DC1_VSEL(mV) | mode | signal); + return 0; +} +EXPORT_SYMBOL_GPL(wm8350_dcdc_set_image_voltage); + +static int wm8350_ldo_set_voltage(struct regulator *reg, int uV) +{ + struct wm8350_pmic *pmic = (struct wm8350_pmic *)reg->reg_data; + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + int volt_reg, ldo = reg->id, mV = uV / 1000; + u16 val; + + dbg("%s %d mV %d\n", __FUNCTION__, ldo, mV); + + switch (ldo) { + case WM8350_LDO_1: + volt_reg = WM8350_LDO1_CONTROL; + break; + case WM8350_LDO_2: + volt_reg = WM8350_LDO2_CONTROL; + break; + case WM8350_LDO_3: + volt_reg = WM8350_LDO3_CONTROL; + break; + case WM8350_LDO_4: + volt_reg = WM8350_LDO4_CONTROL; + break; + default: + return -EINVAL; + } + + /* all LDO's have same mV bits */ + val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK; + wm8350_reg_write(wm8350, volt_reg, val | WM8350_LDO1_VSEL(mV)); + return 0; +} + +static int wm8350_ldo_get_voltage(struct regulator *reg) +{ + struct wm8350_pmic *pmic = (struct wm8350_pmic *)reg->reg_data; + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + int volt_reg, ldo = reg->id; + u16 val; + + switch (ldo) { + case WM8350_LDO_1: + volt_reg = WM8350_LDO1_CONTROL; + break; + case WM8350_LDO_2: + volt_reg = WM8350_LDO2_CONTROL; + break; + case WM8350_LDO_3: + volt_reg = WM8350_LDO3_CONTROL; + break; + case WM8350_LDO_4: + volt_reg = WM8350_LDO4_CONTROL; + break; + default: + return -EINVAL; + } + + /* all LDO's have same mV bits */ + val = wm8350_reg_read(wm8350, volt_reg) & WM8350_LDO1_VSEL_MASK; + return WM8350_LDO1_VSEL_V(val) * 1000; +} + +int wm8350_ldo_set_image_voltage(struct wm8350_pmic *pmic, int ldo, int mV, + int mode, int signal) +{ + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + int volt_reg; + + dbg("%s %d mV %d\n", __FUNCTION__, ldo, mV); + + switch (ldo) { + case WM8350_LDO_1: + volt_reg = WM8350_LDO1_LOW_POWER; + break; + case WM8350_LDO_2: + volt_reg = WM8350_LDO2_LOW_POWER; + break; + case WM8350_LDO_3: + volt_reg = WM8350_LDO3_LOW_POWER; + break; + case WM8350_LDO_4: + volt_reg = WM8350_LDO4_LOW_POWER; + break; + default: + return -EINVAL; + } + + /* all LDO's have same mV bits */ + wm8350_reg_write(wm8350, volt_reg, WM8350_LDO1_VSEL(mV) | mode | + signal); + return 0; +} +EXPORT_SYMBOL_GPL(wm8350_ldo_set_image_voltage); + +int wm8350_dcdc_set_slot(struct wm8350_pmic *pmic, int dcdc, u16 start, + u16 stop, u16 fault) +{ + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + int slot_reg; + u16 val; + + dbg("%s %d start %d stop %d\n", __FUNCTION__, dcdc, start, stop); + + /* slot valid ? */ + if (start > 15 || stop > 15) + return -EINVAL; + + switch (dcdc) { + case WM8350_DCDC_1: + slot_reg = WM8350_DCDC1_TIMEOUTS; + break; + case WM8350_DCDC_2: + slot_reg = WM8350_DCDC2_TIMEOUTS; + break; + case WM8350_DCDC_3: + slot_reg = WM8350_DCDC3_TIMEOUTS; + break; + case WM8350_DCDC_4: + slot_reg = WM8350_DCDC4_TIMEOUTS; + break; + case WM8350_DCDC_5: + slot_reg = WM8350_DCDC5_TIMEOUTS; + break; + case WM8350_DCDC_6: + slot_reg = WM8350_DCDC6_TIMEOUTS; + break; + default: + return -EINVAL; + } + + val = wm8350_reg_read(wm8350, slot_reg) & + ~(WM8350_DC1_ENSLOT_MASK | WM8350_DC1_SDSLOT_MASK | + WM8350_DC1_ERRACT_MASK); + wm8350_reg_write(wm8350, slot_reg, + val | (start << WM8350_DC1_ENSLOT_SHIFT) | + (stop << WM8350_DC1_SDSLOT_SHIFT) | + (fault << WM8350_DC1_ERRACT_SHIFT)); + + return 0; +} +EXPORT_SYMBOL_GPL(wm8350_dcdc_set_slot); + +int wm8350_ldo_set_slot(struct wm8350_pmic *pmic, int ldo, u16 start, + u16 stop) +{ + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + int slot_reg; + u16 val; + + dbg("%s %d start %d stop %d\n", __FUNCTION__, ldo, start, stop); + + /* slot valid ? */ + if (start > 15 || stop > 15) + return -EINVAL; + + switch (ldo) { + case WM8350_LDO_1: + slot_reg = WM8350_LDO1_TIMEOUTS; + break; + case WM8350_LDO_2: + slot_reg = WM8350_LDO2_TIMEOUTS; + break; + case WM8350_LDO_3: + slot_reg = WM8350_LDO3_TIMEOUTS; + break; + case WM8350_LDO_4: + slot_reg = WM8350_LDO4_TIMEOUTS; + break; + default: + return -EINVAL; + } + + val = wm8350_reg_read(wm8350, slot_reg) & ~WM8350_LDO1_SDSLOT_MASK; + wm8350_reg_write(wm8350, slot_reg, val | ((start << 10) | (stop << 6))); + return 0; +} +EXPORT_SYMBOL_GPL(wm8350_ldo_set_slot); + +int wm8350_dcdc25_set_mode(struct wm8350_pmic *pmic, int dcdc, u16 mode, + u16 ilim, u16 ramp, u16 feedback) +{ + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + u16 val; + + dbg("%s %d mode: %s %s\n", __FUNCTION__, dcdc, + mode ? "normal" : "boost", ilim ? "low" : "normal"); + + switch (dcdc) { + case WM8350_DCDC_2: + val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL) + & ~(WM8350_DC2_MODE_MASK | WM8350_DC2_ILIM_MASK | + WM8350_DC2_RMP_MASK | WM8350_DC2_FBSRC_MASK); + wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val | + (mode << WM8350_DC2_MODE_SHIFT) | + (ilim << WM8350_DC2_ILIM_SHIFT) | + (ramp << WM8350_DC2_RMP_SHIFT) | + (feedback << WM8350_DC2_FBSRC_SHIFT)); + break; + case WM8350_DCDC_5: + val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL) + & ~(WM8350_DC5_MODE_MASK | WM8350_DC5_ILIM_MASK | + WM8350_DC5_RMP_MASK | WM8350_DC5_FBSRC_MASK); + wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val | + (mode << WM8350_DC5_MODE_SHIFT) | + (ilim << WM8350_DC5_ILIM_SHIFT) | + (ramp << WM8350_DC5_RMP_SHIFT) | + (feedback << WM8350_DC5_FBSRC_SHIFT)); + break; + default: + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL_GPL(wm8350_dcdc25_set_mode); + +static int wm8350_dcdc_enable(struct regulator *reg) +{ + struct wm8350_pmic *pmic = (struct wm8350_pmic *)reg->reg_data; + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + int dcdc = reg->id; + u16 shift; + + dbg("%s %d --> %s\n", __FUNCTION__, dcdc, enable ? "on" : "off"); + + if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6) + return -EINVAL; + + shift = dcdc - WM8350_DCDC_1; + wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift); + return 0; +} + +static int wm8350_dcdc_disable(struct regulator *reg) +{ + struct wm8350_pmic *pmic = (struct wm8350_pmic *)reg->reg_data; + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + int dcdc = reg->id; + u16 shift; + + dbg("%s %d --> %s\n", __FUNCTION__, dcdc, enable ? "on" : "off"); + + if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6) + return -EINVAL; + + shift = dcdc - WM8350_DCDC_1; + wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift); + + return 0; +} + +static int wm8350_ldo_enable(struct regulator *reg) +{ + struct wm8350_pmic *pmic = (struct wm8350_pmic *)reg->reg_data; + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + int ldo = reg->id; + u16 shift; + + dbg("%s %d --> %s\n", __FUNCTION__, ldo, enable ? "on" : "off"); + + if (ldo < WM8350_LDO_1 || ldo > WM8350_LDO_4) + return -EINVAL; + + shift = (ldo - WM8350_LDO_1) + 8; + wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift); + return 0; +} + +static int wm8350_ldo_disable(struct regulator *reg) +{ + struct wm8350_pmic *pmic = (struct wm8350_pmic *)reg->reg_data; + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + int ldo = reg->id; + u16 shift; + + dbg("%s %d --> %s\n", __FUNCTION__, ldo, enable ? "on" : "off"); + + if (ldo < WM8350_LDO_1 || ldo > WM8350_LDO_4) + return -EINVAL; + + shift = (ldo - WM8350_LDO_1) + 8; + wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift); + return 0; +} + +static int force_continuous_enable(struct wm8350 *wm8350, int dcdc, int enable) +{ + int reg = 0, ret; + + switch (dcdc) { + case WM8350_DCDC_1: + reg = WM8350_DCDC1_FORCE_PWM; + break; + case WM8350_DCDC_3: + reg = WM8350_DCDC3_FORCE_PWM; + break; + case WM8350_DCDC_4: + reg = WM8350_DCDC4_FORCE_PWM; + break; + case WM8350_DCDC_6: + reg = WM8350_DCDC6_FORCE_PWM; + break; + default: + return -EINVAL; + } + + /* LG FIXME - atm I can't seem to set the bits */ + return 0; + + wm8350_reg_unlock(wm8350); + if (enable) + ret = wm8350_set_bits(wm8350, reg, WM8350_DCDC1_FORCE_PWM_ENA); + else + ret = wm8350_clear_bits(wm8350, reg, + WM8350_DCDC1_FORCE_PWM_ENA); + wm8350_reg_lock(wm8350); + return ret; +} + +static int wm8350_dcdc_set_mode(struct regulator *reg, + unsigned int mode) +{ + struct wm8350_pmic *pmic = (struct wm8350_pmic *)reg->reg_data; + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + int dcdc = reg->id; + u16 val; + + if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6) + return -EINVAL; + + if (dcdc == WM8350_DCDC_2 || dcdc == WM8350_DCDC_5) + return -EINVAL; + + val = 1 << (dcdc - WM8350_DCDC_1); + + switch (mode) { + case REGULATOR_MODE_FAST: + /* force continuous mode */ + wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val); + wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val); + force_continuous_enable(wm8350, dcdc, 1); + break; + case REGULATOR_MODE_NORMAL: + /* active / pulse skipping */ + wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val); + wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val); + force_continuous_enable(wm8350, dcdc, 0); + break; + case REGULATOR_MODE_IDLE: + /* standby mode */ + force_continuous_enable(wm8350, dcdc, 0); + wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val); + wm8350_clear_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val); + break; + case REGULATOR_MODE_STANDBY: + /* LDO mode */ + force_continuous_enable(wm8350, dcdc, 0); + wm8350_set_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val); + break; + } + + return 0; +} + +static unsigned int wm8350_dcdc_get_mode(struct regulator *reg) +{ + struct wm8350_pmic *pmic = (struct wm8350_pmic *)reg->reg_data; + struct wm8350 *wm8350 = to_wm8350_from_pmic(pmic); + int dcdc = reg->id; + u16 mask, sleep, active, force; + int mode = REGULATOR_MODE_NORMAL; + + if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6) + return -EINVAL; + + if (dcdc == WM8350_DCDC_2 || dcdc == WM8350_DCDC_5) + return -EINVAL; + + mask = 1 << (dcdc - WM8350_DCDC_1); + active = wm8350_reg_read(wm8350, WM8350_DCDC_ACTIVE_OPTIONS) & mask; + sleep = wm8350_reg_read(wm8350, WM8350_DCDC_SLEEP_OPTIONS) & mask; + force = wm8350_reg_read(wm8350, WM8350_DCDC1_FORCE_PWM) + & WM8350_DCDC1_FORCE_PWM_ENA; + dbg("mask %x active %x sleep %x force %x", mask, active, sleep, force); + + if (active && !sleep) { + if (force) + mode = REGULATOR_MODE_FAST; + else + mode = REGULATOR_MODE_NORMAL; + } else if (!active && !sleep) + mode = REGULATOR_MODE_IDLE; + else if (!sleep) + mode = REGULATOR_MODE_STANDBY; + + return mode; +} + +struct wm8350_dcdc_efficiency { + int uA_load_min; + int uA_load_max; + unsigned int mode; +}; + +static const struct wm8350_dcdc_efficiency dcdc1_6_efficiency[] = { + {0, 10000, REGULATOR_MODE_STANDBY}, /* 0 - 10mA - LDO */ + {10000, 100000, REGULATOR_MODE_IDLE}, /* 10mA - 100mA - Standby */ + {100000, 1000000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */ + {-1, -1, REGULATOR_MODE_NORMAL}, +}; + +static const struct wm8350_dcdc_efficiency dcdc3_4_efficiency[] = { + {0, 10000, REGULATOR_MODE_STANDBY}, /* 0 - 10mA - LDO */ + {10000, 100000, REGULATOR_MODE_IDLE}, /* 10mA - 100mA - Standby */ + {100000, 800000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */ + {-1, -1, REGULATOR_MODE_NORMAL}, +}; + +static unsigned int get_mode(int uA, + const struct wm8350_dcdc_efficiency *eff) +{ + int i = 0; + + while (eff[i].uA_load_min != -1) { + if (uA >= eff[i].uA_load_min && uA <= eff[i].uA_load_max) + return eff[i].mode; + } + return REGULATOR_MODE_NORMAL; +} + +/* query the regulator for it's most efficient mode @ uV,uA + * WM8350 regulator efficiency is pretty similar over + * different input and output uV. + */ +static unsigned int wm8350_dcdc_get_optimum_mode(struct regulator *reg, + int input_uV, int output_uV, int output_uA) +{ + int dcdc = reg->id, mode; + + switch (dcdc) { + case WM8350_DCDC_1: + case WM8350_DCDC_6: + mode = get_mode(output_uA, dcdc1_6_efficiency); + break; + case WM8350_DCDC_3: + case WM8350_DCDC_4: + mode = get_mode(output_uA, dcdc3_4_efficiency); + break; + default: + mode = REGULATOR_MODE_NORMAL; + break; + } + return mode; +} + +static struct regulator_ops wm8350_dcdc_ops = { + .set_voltage = wm8350_dcdc_set_voltage, + .get_voltage = wm8350_dcdc_get_voltage, + .enable = wm8350_dcdc_enable, + .disable = wm8350_dcdc_disable, + .get_mode = wm8350_dcdc_get_mode, + .set_mode = wm8350_dcdc_set_mode, + .get_optimum_mode = wm8350_dcdc_get_optimum_mode, +}; + +static struct regulator_ops wm8350_dcdc2_5_ops = { + .enable = wm8350_dcdc_enable, + .disable = wm8350_dcdc_disable, +}; + +static struct regulator_ops wm8350_ldo_ops = { + .set_voltage = wm8350_ldo_set_voltage, + .get_voltage = wm8350_ldo_get_voltage, + .enable = wm8350_ldo_enable, + .disable = wm8350_ldo_disable, +}; + +static struct regulator_ops wm8350_isink_ops = { + .set_current = wm8350_isink_set_current, + .get_current = wm8350_isink_get_current, + .enable = wm8350_isink_enable, + .disable = wm8350_isink_disable, +}; + +struct wm8350_regulator { + struct regulator regulator; + int irq; +}; + +static struct wm8350_regulator wm8350_reg[NUM_WM8350_REGULATORS] = { +{ + .regulator = { + .name = "DCDC1", + .id = WM8350_DCDC_1, + .ops = &wm8350_dcdc_ops, + }, + .irq = WM8350_IRQ_UV_DC1, +}, +{ + .regulator = { + .name = "DCDC2", + .id = WM8350_DCDC_2, + .ops = &wm8350_dcdc2_5_ops, + }, + .irq = WM8350_IRQ_UV_DC2, +}, +{ + .regulator = { + .name = "DCDC3", + .id = WM8350_DCDC_3, + .ops = &wm8350_dcdc_ops, + }, + .irq = WM8350_IRQ_UV_DC3, +}, +{ + .regulator = { + .name = "DCDC4", + .id = WM8350_DCDC_4, + .ops = &wm8350_dcdc_ops, + }, + .irq = WM8350_IRQ_UV_DC4, +}, +{ + .regulator = { + .name = "DCDC5", + .id = WM8350_DCDC_5, + .ops = &wm8350_dcdc2_5_ops, + }, + .irq = WM8350_IRQ_UV_DC5, +}, +{ + .regulator = { + .name = "DCDC6", + .id = WM8350_DCDC_6, + .ops = &wm8350_dcdc_ops, + }, + .irq = WM8350_IRQ_UV_DC6, +}, +{ + .regulator = { + .name = "LDO1", + .id = WM8350_LDO_1, + .ops = &wm8350_ldo_ops, + }, + .irq = WM8350_IRQ_UV_LDO1, +}, +{ + .regulator = { + .name = "LDO2", + .id = WM8350_LDO_2, + .ops = &wm8350_ldo_ops, + }, + .irq = WM8350_IRQ_UV_LDO2, +}, +{ + .regulator = { + .name = "LDO3", + .id = WM8350_LDO_3, + .ops = &wm8350_ldo_ops, + }, + .irq = WM8350_IRQ_UV_LDO3, +}, +{ + .regulator = { + .name = "LDO4", + .id = WM8350_LDO_4, + .ops = &wm8350_ldo_ops, + }, + .irq = WM8350_IRQ_UV_LDO4, +}, +{ + .regulator = { + .name = "ISINKA", + .id = WM8350_ISINK_A, + .ops = &wm8350_isink_ops, + }, + .irq = WM8350_IRQ_CS1, +}, +{ + .regulator = { + .name = "ISINKB", + .id = WM8350_ISINK_B, + .ops = &wm8350_isink_ops, + }, + .irq = WM8350_IRQ_CS2, +},}; + +static void pmic_uv_handler(struct wm8350 *wm8350, int irq, void *data) +{ + struct regulator *regulator = (struct regulator *)data; + + if (irq == WM8350_IRQ_CS1 || irq == WM8350_IRQ_CS2) + regulator_notifier_call_chain(regulator, + REGULATOR_EVENT_REGULATION_OUT, wm8350); + else + regulator_notifier_call_chain(regulator, + REGULATOR_EVENT_UNDER_VOLTAGE, wm8350); +} + +static int wm8350_probe(struct device *dev) +{ + struct wm8350_pmic *wm8350_pmic = to_wm8350_pmic_device(dev); + struct wm8350 *wm8350 = to_wm8350_from_pmic(wm8350_pmic); + int ret, i; + + printk(KERN_INFO "WM8350 PMIC driver version %s\n", + WM8350_PMIC_VERSION); + + for (i = 0; i < ARRAY_SIZE(wm8350_reg); i++) { + ret = regulator_register(&wm8350_reg[i].regulator); + if (ret < 0) { + printk(KERN_ERR "%s: failed to register %s err %d\n", + __func__, wm8350_reg[i].regulator.name, ret); + goto unwind_reg; + } + regulator_set_drvdata(&wm8350_reg[i].regulator, wm8350_pmic); + ret = wm8350_register_irq(wm8350, wm8350_reg[i].irq, + pmic_uv_handler, &wm8350_reg[i].regulator); + if (ret < 0) + goto unwind_irq; + wm8350_unmask_irq(wm8350, wm8350_reg[i].irq); + } + return 0; +unwind_irq: + regulator_unregister(&wm8350_reg[i].regulator); +unwind_reg: + i--; + for (; i >= 0; i--) { + wm8350_mask_irq(wm8350, wm8350_reg[i].irq); + wm8350_free_irq(wm8350, wm8350_reg[i].irq); + regulator_unregister(&wm8350_reg[i].regulator); + } + return ret; +} + +static int wm8350_remove(struct device *dev) +{ + struct wm8350_pmic *wm8350_pmic = to_wm8350_pmic_device(dev); + struct wm8350 *wm8350 = to_wm8350_from_pmic(wm8350_pmic); + int i; + + for (i = ARRAY_SIZE(wm8350_reg) - 1; i >= 0; i--) { + wm8350_mask_irq(wm8350, wm8350_reg[i].irq); + wm8350_free_irq(wm8350, wm8350_reg[i].irq); + regulator_unregister(&wm8350_reg[i].regulator); + } + + return 0; +} + +struct device_driver wm8350_driver = { + .name = "wm8350-pmic", + .bus = &wm8350_bus_type, + .owner = THIS_MODULE, + .probe = wm8350_probe, + .remove = wm8350_remove, +}; + +int wm8350_pmu_init(void) +{ + return driver_register(&wm8350_driver); +} + +void wm8350_pmu_exit(void) +{ + driver_unregister(&wm8350_driver); +} + +/* Module information */ +MODULE_AUTHOR("Liam Girdwood, liam.girdwood@wolfsonmicro.com,\ +www.wolfsonmicro.com"); +MODULE_DESCRIPTION("WM8350 PMIC driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/rtc/Kconfig linux-2.6.26-lab126/drivers/rtc/Kconfig --- linux-2.6.26/drivers/rtc/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/rtc/Kconfig 2010-08-10 04:16:12.000000000 -0400 @@ -545,9 +545,38 @@ help If you say yes here you get support for the Ricoh RS5C313 RTC chips. +config RTC_MXC + tristate "Freescale MXC Real Time Clock" + depends on ARCH_MXC + depends on RTC_CLASS + help + Support for Freescale RTC MXC + +config RTC_DRV_MXC_V2 + tristate "Freescale MXC Secure Real Time Clock" + depends on ARCH_MXC + depends on RTC_CLASS + help + Support for Freescale SRTC MXC + +config RTC_DRV_IMXDI + tristate "Freescale IMX DryIce Real Time Clock" + depends on ARCH_MXC + depends on RTC_CLASS + help + Support for Freescale IMX DryIce RTC + +config RTC_MC13892 + tristate "Freescale MC13892 Real Time Clock" + depends on ARCH_MXC && MXC_PMIC_MC13892 + depends on RTC_CLASS + help + Support for Freescale MC13892 RTC + config RTC_DRV_PPC tristate "PowerPC machine dependent RTC support" depends on PPC_MERGE + depends on RTC_CLASS help The PowerPC kernel has machine-specific functions for accessing the RTC. This exposes that functionality through the generic RTC diff -urN linux-2.6.26/drivers/rtc/Makefile linux-2.6.26-lab126/drivers/rtc/Makefile --- linux-2.6.26/drivers/rtc/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/rtc/Makefile 2010-08-10 04:16:12.000000000 -0400 @@ -56,3 +56,7 @@ obj-$(CONFIG_RTC_DRV_V3020) += rtc-v3020.o obj-$(CONFIG_RTC_DRV_VR41XX) += rtc-vr41xx.o obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o +obj-$(CONFIG_RTC_MXC) += rtc-mxc.o +obj-$(CONFIG_RTC_DRV_MXC_V2) += rtc-mxc_v2.o +obj-$(CONFIG_RTC_DRV_IMXDI) += rtc-imxdi.o +obj-$(CONFIG_RTC_MC13892) += rtc-mc13892.o diff -urN linux-2.6.26/drivers/rtc/rtc-imxdi.c linux-2.6.26-lab126/drivers/rtc/rtc-imxdi.c --- linux-2.6.26/drivers/rtc/rtc-imxdi.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/rtc/rtc-imxdi.c 2010-08-10 04:16:12.000000000 -0400 @@ -0,0 +1,567 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* based on rtc-mc13892.c */ + +/* + * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block + * to implement a Linux RTC. Times and alarms are truncated to seconds. + * Since the RTC framework performs API locking via rtc->ops_lock the + * only simultaneous accesses we need to deal with is updating DryIce + * registers while servicing an alarm. + * + * Note that reading the DSR (DryIce Status Register) automatically clears + * the WCF (Write Complete Flag). All DryIce writes are synchronized to the + * LP (Low Power) domain and set the WCF upon completion. Writes to the + * DIER (DryIce Interrupt Enable Register) are the only exception. These + * occur at normal bus speeds and do not set WCF. Periodic interrupts are + * not supported by the hardware. + */ + +/* #define DEBUG */ +/* #define DI_DEBUG_REGIO */ + +#include +#include +#include +#include +#include +#include + +/* DryIce Register Definitions */ + +#define DTCMR 0x00 /* Time Counter MSB Reg */ +#define DTCLR 0x04 /* Time Counter LSB Reg */ + +#define DCAMR 0x08 /* Clock Alarm MSB Reg */ +#define DCALR 0x0c /* Clock Alarm LSB Reg */ +#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */ + +#define DCR 0x10 /* Control Reg */ +#define DCR_TCE (1 << 3) /* Time Counter Enable */ + +#define DSR 0x14 /* Status Reg */ +#define DSR_WBF (1 << 10) /* Write Busy Flag */ +#define DSR_WNF (1 << 9) /* Write Next Flag */ +#define DSR_WCF (1 << 8) /* Write Complete Flag */ +#define DSR_WEF (1 << 7) /* Write Error Flag */ +#define DSR_CAF (1 << 4) /* Clock Alarm Flag */ +#define DSR_NVF (1 << 1) /* Non-Valid Flag */ +#define DSR_SVF (1 << 0) /* Security Violation Flag */ + +#define DIER 0x18 /* Interrupt Enable Reg */ +#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */ +#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */ +#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */ +#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */ + +#ifndef DI_DEBUG_REGIO +/* dryice read register */ +#define di_read(pdata, reg) __raw_readl((pdata)->ioaddr + (reg)) + +/* dryice write register */ +#define di_write(pdata, val, reg) __raw_writel((val), (pdata)->ioaddr + (reg)) +#else +/* dryice read register - debug version */ +static inline u32 di_read(struct rtc_drv_data *pdata, int reg) +{ + u32 val = __raw_readl(pdata->ioaddr + reg); + pr_info("di_read(0x%02x) = 0x%08x\n", reg, val); + return val; +} + +/* dryice write register - debug version */ +static inline void di_write(struct rtc_drv_data *pdata, u32 val, int reg) +{ + printk(KERN_INFO "di_write(0x%08x, 0x%02x)\n", val, reg); + __raw_writel(val, pdata->ioaddr + reg); +} +#endif + +/* + * dryice write register with wait and error handling. + * all registers, except for DIER, should use this method. + */ +#define di_write_wait_err(pdata, val, reg, rc, label) \ + do { \ + if (di_write_wait((pdata), (val), (reg))) { \ + rc = -EIO; \ + goto label; \ + } \ + } while (0) + +struct rtc_drv_data { + struct platform_device *pdev; /* pointer to platform dev */ + struct rtc_device *rtc; /* pointer to rtc struct */ + unsigned long baseaddr; /* physical bass address */ + void __iomem *ioaddr; /* virtual base address */ + int size; /* size of register region */ + int irq; /* dryice normal irq */ + struct clk *clk; /* dryice clock control */ + u32 dsr; /* copy of dsr reg from isr */ + spinlock_t irq_lock; /* irq resource lock */ + wait_queue_head_t write_wait; /* write-complete queue */ + struct mutex write_mutex; /* force reg writes to be sequential */ + struct work_struct work; /* schedule alarm work */ +}; + +/* + * enable a dryice interrupt + */ +static inline void di_int_enable(struct rtc_drv_data *pdata, u32 intr) +{ + unsigned long flags; + + spin_lock_irqsave(&pdata->irq_lock, flags); + di_write(pdata, di_read(pdata, DIER) | intr, DIER); + spin_unlock_irqrestore(&pdata->irq_lock, flags); +} + +/* + * disable a dryice interrupt + */ +static inline void di_int_disable(struct rtc_drv_data *pdata, u32 intr) +{ + unsigned long flags; + + spin_lock_irqsave(&pdata->irq_lock, flags); + di_write(pdata, di_read(pdata, DIER) & ~intr, DIER); + spin_unlock_irqrestore(&pdata->irq_lock, flags); +} + +/* + * This function attempts to clear the dryice write-error flag. + * + * A dryice write error is similar to a bus fault and should not occur in + * normal operation. Clearing the flag requires another write, so the root + * cause of the problem may need to be fixed before the flag can be cleared. + */ +static void clear_write_error(struct rtc_drv_data *pdata) +{ + int cnt; + + dev_warn(&pdata->pdev->dev, "WARNING: Register write error!\n"); + + for (;;) { + /* clear the write error flag */ + di_write(pdata, DSR_WEF, DSR); + + /* wait for it to take effect */ + for (cnt = 0; cnt < 100; cnt++) { + if ((di_read(pdata, DSR) & DSR_WEF) == 0) + return; + udelay(10); + } + dev_err(&pdata->pdev->dev, + "ERROR: Cannot clear write-error flag!\n"); + } +} + +/* + * Write a dryice register and wait until it completes. + * + * This function uses interrupts to determine when the + * write has completed. + */ +static int di_write_wait(struct rtc_drv_data *pdata, u32 val, int reg) +{ + int ret; + int rc = 0; + + /* serialize register writes */ + mutex_lock(&pdata->write_mutex); + + /* enable the write-complete interrupt */ + di_int_enable(pdata, DIER_WCIE); + + pdata->dsr = 0; + + /* do the register write */ + di_write(pdata, val, reg); + + /* wait for the write to finish */ + ret = wait_event_interruptible_timeout(pdata->write_wait, + pdata->dsr & (DSR_WCF | DSR_WEF), + 1 * HZ); + if (ret == 0) + dev_warn(&pdata->pdev->dev, "Write-wait timeout\n"); + + /* check for write error */ + if (pdata->dsr & DSR_WEF) { + clear_write_error(pdata); + rc = -EIO; + } + mutex_unlock(&pdata->write_mutex); + return rc; +} + +/* + * rtc device ioctl + * + * The rtc framework handles the basic rtc ioctls on behalf + * of the driver by calling the functions registered in the + * rtc_ops structure. + */ +static int dryice_rtc_ioctl(struct device *dev, unsigned int cmd, + unsigned long arg) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + + dev_dbg(dev, "%s(0x%x)\n", __func__, cmd); + switch (cmd) { + case RTC_AIE_OFF: /* alarm disable */ + di_int_disable(pdata, DIER_CAIE); + return 0; + + case RTC_AIE_ON: /* alarm enable */ + di_int_enable(pdata, DIER_CAIE); + return 0; + } + return -ENOIOCTLCMD; +} + +/* + * read the seconds portion of the current time from the dryice time counter + */ +static int dryice_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + unsigned long now; + + dev_dbg(dev, "%s\n", __func__); + now = di_read(pdata, DTCMR); + rtc_time_to_tm(now, tm); + + return 0; +} + +/* + * set the seconds portion of dryice time counter and clear the + * fractional part. + */ +static int dryice_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + unsigned long now; + int rc; + + dev_dbg(dev, "%s\n", __func__); + rc = rtc_tm_to_time(tm, &now); + if (rc == 0) { + /* zero the fractional part first */ + di_write_wait_err(pdata, 0, DTCLR, rc, err); + di_write_wait_err(pdata, now, DTCMR, rc, err); + } +err: + return rc; +} + +/* + * read the seconds portion of the alarm register. + * the fractional part of the alarm register is always zero. + */ +static int dryice_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + u32 dcamr; + + dev_dbg(dev, "%s\n", __func__); + dcamr = di_read(pdata, DCAMR); + rtc_time_to_tm(dcamr, &alarm->time); + + /* alarm is enabled if the interrupt is enabled */ + alarm->enabled = (di_read(pdata, DIER) & DIER_CAIE) != 0; + + /* don't allow the DSR read to mess up DSR_WCF */ + mutex_lock(&pdata->write_mutex); + + /* alarm is pending if the alarm flag is set */ + alarm->pending = (di_read(pdata, DSR) & DSR_CAF) != 0; + + mutex_unlock(&pdata->write_mutex); + + return 0; +} + +/* + * set the seconds portion of dryice alarm register + */ +static int dryice_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + unsigned long now; + unsigned long alarm_time; + int rc; + + dev_dbg(dev, "%s\n", __func__); + rc = rtc_tm_to_time(&alarm->time, &alarm_time); + if (rc) + return rc; + + /* don't allow setting alarm in the past */ + now = di_read(pdata, DTCMR); + if (alarm_time < now) + return -EINVAL; + + /* write the new alarm time */ + di_write_wait_err(pdata, (u32)alarm_time, DCAMR, rc, err); + + if (alarm->enabled) + di_int_enable(pdata, DIER_CAIE); /* enable alarm intr */ + else + di_int_disable(pdata, DIER_CAIE); /* disable alarm intr */ +err: + return rc; +} + +static struct rtc_class_ops dryice_rtc_ops = { + .ioctl = dryice_rtc_ioctl, + .read_time = dryice_rtc_read_time, + .set_time = dryice_rtc_set_time, + .read_alarm = dryice_rtc_read_alarm, + .set_alarm = dryice_rtc_set_alarm, +}; + +/* + * dryice "normal" interrupt handler + */ +static irqreturn_t dryice_norm_irq(int irq, void *dev_id) +{ + struct rtc_drv_data *pdata = dev_id; + u32 dsr, dier; + irqreturn_t rc = IRQ_NONE; + + /* DSR_WCF clears itself on DSR read */ + dsr = di_read(pdata, DSR); + dier = di_read(pdata, DIER); + + /* handle write complete and write error cases */ + if ((dier & DIER_WCIE) && (dsr & (DSR_WCF | DSR_WEF))) { + /* mask the interrupt */ + di_int_disable(pdata, DIER_WCIE); + + /* save the dsr value for the wait queue */ + pdata->dsr |= dsr; + + wake_up_interruptible(&pdata->write_wait); + rc = IRQ_HANDLED; + } + + /* handle the alarm case */ + if ((dier & DIER_CAIE) && (dsr & DSR_CAF)) { + /* mask the interrupt */ + di_int_disable(pdata, DIER_CAIE); + + /* finish alarm in user context */ + schedule_work(&pdata->work); + rc = IRQ_HANDLED; + } + return rc; +} + +/* + * post the alarm event from user context so it can sleep + * on the write completion. + */ +static void dryice_work(struct work_struct *work) +{ + struct rtc_drv_data *pdata = container_of(work, struct rtc_drv_data, + work); + int rc; + + /* dismiss the interrupt (ignore error) */ + di_write_wait_err(pdata, DSR_CAF, DSR, rc, err); +err: + /* + * pass the alarm event to the rtc framework. note that + * rtc_update_irq expects to be called with interrupts off. + */ + local_irq_disable(); + rtc_update_irq(pdata->rtc, 1, RTC_AF | RTC_IRQF); + local_irq_enable(); +} + +/* + * probe for dryice rtc device + */ +static int dryice_rtc_probe(struct platform_device *pdev) +{ + struct rtc_device *rtc; + struct resource *res; + struct rtc_drv_data *pdata = NULL; + void __iomem *ioaddr = NULL; + int rc = 0; + + dev_dbg(&pdev->dev, "%s\n", __func__); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + pdata->pdev = pdev; + pdata->irq = -1; + pdata->size = res->end - res->start + 1; + + if (!request_mem_region(res->start, pdata->size, pdev->name)) { + rc = -EBUSY; + goto err; + } + pdata->baseaddr = res->start; + ioaddr = ioremap(pdata->baseaddr, pdata->size); + if (!ioaddr) { + rc = -ENOMEM; + goto err; + } + pdata->ioaddr = ioaddr; + pdata->irq = platform_get_irq(pdev, 0); + + init_waitqueue_head(&pdata->write_wait); + + INIT_WORK(&pdata->work, dryice_work); + + mutex_init(&pdata->write_mutex); + + pdata->clk = clk_get(NULL, "dryice_clk"); + clk_enable(pdata->clk); + + if (pdata->irq >= 0) { + if (request_irq(pdata->irq, dryice_norm_irq, IRQF_DISABLED, + pdev->name, pdata) < 0) { + dev_warn(&pdev->dev, "interrupt not available.\n"); + pdata->irq = -1; + goto err; + } + } + + /* + * Initialize dryice hardware + */ + + /* put dryice into valid state */ + if (di_read(pdata, DSR) & DSR_NVF) + di_write_wait_err(pdata, DSR_NVF | DSR_SVF, DSR, rc, err); + + /* mask alarm interrupt */ + di_int_disable(pdata, DIER_CAIE); + + /* initialize alarm */ + di_write_wait_err(pdata, DCAMR_UNSET, DCAMR, rc, err); + di_write_wait_err(pdata, 0, DCALR, rc, err); + + /* clear alarm flag */ + if (di_read(pdata, DSR) & DSR_CAF) + di_write_wait_err(pdata, DSR_CAF, DSR, rc, err); + + /* the timer won't count if it has never been written to */ + if (!di_read(pdata, DTCMR)) + di_write_wait_err(pdata, 0, DTCMR, rc, err); + + /* start keeping time */ + if (!(di_read(pdata, DCR) & DCR_TCE)) + di_write_wait_err(pdata, di_read(pdata, DCR) | DCR_TCE, DCR, + rc, err); + + rtc = rtc_device_register(pdev->name, &pdev->dev, + &dryice_rtc_ops, THIS_MODULE); + if (IS_ERR(rtc)) { + rc = PTR_ERR(rtc); + goto err; + } + pdata->rtc = rtc; + platform_set_drvdata(pdev, pdata); + + return 0; +err: + if (pdata->rtc) + rtc_device_unregister(pdata->rtc); + + if (pdata->irq >= 0) + free_irq(pdata->irq, pdata); + + if (pdata->clk) { + clk_disable(pdata->clk); + clk_put(pdata->clk); + } + + if (pdata->ioaddr) + iounmap(pdata->ioaddr); + + if (pdata->baseaddr) + release_mem_region(pdata->baseaddr, pdata->size); + + kfree(pdata); + + return rc; +} + +static int __exit dryice_rtc_remove(struct platform_device *pdev) +{ + struct rtc_drv_data *pdata = platform_get_drvdata(pdev); + + flush_scheduled_work(); + + if (pdata->rtc) + rtc_device_unregister(pdata->rtc); + + /* mask alarm interrupt */ + di_int_disable(pdata, DIER_CAIE); + + if (pdata->irq >= 0) + free_irq(pdata->irq, pdata); + + if (pdata->clk) { + clk_disable(pdata->clk); + clk_put(pdata->clk); + } + + if (pdata->ioaddr) + iounmap(pdata->ioaddr); + + if (pdata->baseaddr) + release_mem_region(pdata->baseaddr, pdata->size); + + kfree(pdata); + + return 0; +} + +static struct platform_driver dryice_rtc_driver = { + .driver = { + .name = "imxdi_rtc", + .owner = THIS_MODULE, + }, + .probe = dryice_rtc_probe, + .remove = __exit_p(dryice_rtc_remove), +}; + +static int __init dryice_rtc_init(void) +{ + pr_info("IMXDI Realtime Clock Driver (RTC)\n"); + return platform_driver_register(&dryice_rtc_driver); +} + +static void __exit dryice_rtc_exit(void) +{ + platform_driver_unregister(&dryice_rtc_driver); +} + +module_init(dryice_rtc_init); +module_exit(dryice_rtc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("IMXDI Realtime Clock Driver (RTC)"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/rtc/rtc-lib.c linux-2.6.26-lab126/drivers/rtc/rtc-lib.c --- linux-2.6.26/drivers/rtc/rtc-lib.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/rtc/rtc-lib.c 2010-08-10 04:16:12.000000000 -0400 @@ -51,10 +51,11 @@ */ void rtc_time_to_tm(unsigned long time, struct rtc_time *tm) { - unsigned int days, month, year; + unsigned int month, year; + int days; days = time / 86400; - time -= days * 86400; + time -= (unsigned int) days * 86400; /* day of the week, 1970-01-01 was a Thursday */ tm->tm_wday = (days + 4) % 7; diff -urN linux-2.6.26/drivers/rtc/rtc-mc13892.c linux-2.6.26-lab126/drivers/rtc/rtc-mc13892.c --- linux-2.6.26/drivers/rtc/rtc-mc13892.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/rtc/rtc-mc13892.c 2010-08-10 04:16:12.000000000 -0400 @@ -0,0 +1,266 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include + +#include +#include + +#define RTC_TIME_LSH 0 +#define RTC_DAY_LSH 0 +#define RTCALARM_TIME_LSH 0 +#define RTCALARM_DAY_LSH 0 + +#define RTC_TIME_WID 17 +#define RTC_DAY_WID 15 +#define RTCALARM_TIME_WID 17 +#define RTCALARM_DAY_WID 15 + +static unsigned long rtc_status; + +/* Has the PMIC RTC been detected yet? */ +static int pmic_rtc_detected = 0; + +int pmic_rtc_loaded(void) +{ + return pmic_rtc_detected; +} +EXPORT_SYMBOL(pmic_rtc_loaded); + +static int mxc_rtc_open(struct device *dev) +{ + if (test_and_set_bit(1, &rtc_status)) + return -EBUSY; + return 0; +} + +static void mxc_rtc_release(struct device *dev) +{ + clear_bit(1, &rtc_status); +} + +static int mxc_rtc_ioctl(struct device *dev, unsigned int cmd, + unsigned long arg) +{ + switch (cmd) { + case RTC_AIE_OFF: + pr_debug("alarm off\n"); + CHECK_ERROR(pmic_write_reg(REG_RTC_ALARM, 0x100000, 0x100000)); + return 0; + case RTC_AIE_ON: + pr_debug("alarm on\n"); + CHECK_ERROR(pmic_write_reg(REG_RTC_ALARM, 0, 0x100000)); + return 0; + } + + return -ENOIOCTLCMD; +} + +static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + unsigned int tod_reg_val = 0; + unsigned int day_reg_val = 0, day_reg_val2; + unsigned int mask, value; + unsigned long time; + + do { + mask = BITFMASK(RTC_DAY); + CHECK_ERROR(pmic_read_reg(REG_RTC_DAY, &value, mask)); + day_reg_val = BITFEXT(value, RTC_DAY); + + mask = BITFMASK(RTC_TIME); + CHECK_ERROR(pmic_read_reg(REG_RTC_TIME, &value, mask)); + tod_reg_val = BITFEXT(value, RTC_TIME); + + mask = BITFMASK(RTC_DAY); + CHECK_ERROR(pmic_read_reg(REG_RTC_DAY, &value, mask)); + day_reg_val2 = BITFEXT(value, RTC_DAY); + } while (day_reg_val != day_reg_val2); + + time = (unsigned long)((unsigned long)(tod_reg_val & + 0x0001FFFF) + + (unsigned long)(day_reg_val * 86400)); + + rtc_time_to_tm(time, tm); + + return 0; +} + +static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + unsigned int tod_reg_val = 0; + unsigned int day_reg_val, day_reg_val2 = 0; + unsigned int mask, value; + unsigned long time; + + if (rtc_valid_tm(tm)) + return -1; + + rtc_tm_to_time(tm, &time); + + tod_reg_val = time % 86400; + day_reg_val = time / 86400; + + do { + mask = BITFMASK(RTC_DAY); + value = BITFVAL(RTC_DAY, day_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_DAY, value, mask)); + + mask = BITFMASK(RTC_TIME); + value = BITFVAL(RTC_TIME, tod_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_TIME, value, mask)); + + mask = BITFMASK(RTC_DAY); + CHECK_ERROR(pmic_read_reg(REG_RTC_DAY, &value, mask)); + day_reg_val2 = BITFEXT(value, RTC_DAY); + } while (day_reg_val != day_reg_val2); + + return 0; +} + +static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + unsigned int tod_reg_val = 0; + unsigned int day_reg_val = 0; + unsigned int mask, value; + unsigned long time; + + mask = BITFMASK(RTCALARM_TIME); + CHECK_ERROR(pmic_read_reg(REG_RTC_ALARM, &value, mask)); + tod_reg_val = BITFEXT(value, RTCALARM_TIME); + + mask = BITFMASK(RTCALARM_DAY); + CHECK_ERROR(pmic_read_reg(REG_RTC_DAY_ALARM, &value, mask)); + day_reg_val = BITFEXT(value, RTCALARM_DAY); + + time = (unsigned long)((unsigned long)(tod_reg_val & + 0x0001FFFF) + + (unsigned long)(day_reg_val * 86400)); + rtc_time_to_tm(time, &(alrm->time)); + + return 0; +} + +static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + unsigned int tod_reg_val = 0; + unsigned int day_reg_val = 0; + unsigned int mask, value; + unsigned long time; + + if (rtc_valid_tm(&alrm->time)) + return -1; + + rtc_tm_to_time(&alrm->time, &time); + + tod_reg_val = time % 86400; + day_reg_val = time / 86400; + + mask = BITFMASK(RTCALARM_TIME); + value = BITFVAL(RTCALARM_TIME, tod_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_ALARM, value, mask)); + + mask = BITFMASK(RTCALARM_DAY); + value = BITFVAL(RTCALARM_DAY, day_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_DAY_ALARM, value, mask)); + + return 0; +} + +struct rtc_drv_data { + struct rtc_device *rtc; + pmic_event_callback_t event; +}; + +static struct rtc_class_ops mxc_rtc_ops = { + .open = mxc_rtc_open, + .release = mxc_rtc_release, + .ioctl = mxc_rtc_ioctl, + .read_time = mxc_rtc_read_time, + .set_time = mxc_rtc_set_time, + .read_alarm = mxc_rtc_read_alarm, + .set_alarm = mxc_rtc_set_alarm, +}; + +static void mxc_rtc_alarm_int(void *data) +{ + struct rtc_drv_data *pdata = data; + + rtc_update_irq(pdata->rtc, 1, RTC_AF | RTC_IRQF); +} + +static int mxc_rtc_probe(struct platform_device *pdev) +{ + struct rtc_drv_data *pdata = NULL; + + printk(KERN_INFO "mc13892 rtc probe start\n"); + + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + + if (!pdata) + return -ENOMEM; + + pdata->event.func = mxc_rtc_alarm_int; + pdata->event.param = pdata; + CHECK_ERROR(pmic_event_subscribe(EVENT_TODAI, pdata->event)); + + device_init_wakeup(&pdev->dev, 1); + pdata->rtc = rtc_device_register(pdev->name, &pdev->dev, + &mxc_rtc_ops, THIS_MODULE); + + platform_set_drvdata(pdev, pdata); + if (IS_ERR(pdata->rtc)) + return -1; + + printk(KERN_INFO "mc13892 rtc probe succeed\n"); + pmic_rtc_detected = 1; /* PMIC RTC successfully detected */ + return 0; +} + +static int __exit mxc_rtc_remove(struct platform_device *pdev) +{ + struct rtc_drv_data *pdata = platform_get_drvdata(pdev); + + rtc_device_unregister(pdata->rtc); + CHECK_ERROR(pmic_event_unsubscribe(EVENT_TODAI, pdata->event)); + + return 0; +} + +static struct platform_driver mxc_rtc_driver = { + .driver = { + .name = "pmic_rtc", + }, + .probe = mxc_rtc_probe, + .remove = __exit_p(mxc_rtc_remove), +}; + +static int __init mxc_rtc_init(void) +{ + return platform_driver_register(&mxc_rtc_driver); +} + +static void __exit mxc_rtc_exit(void) +{ + platform_driver_unregister(&mxc_rtc_driver); + +} + +module_init(mxc_rtc_init); +module_exit(mxc_rtc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MC13892 Realtime Clock Driver (RTC)"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/rtc/rtc-mxc.c linux-2.6.26-lab126/drivers/rtc/rtc-mxc.c --- linux-2.6.26/drivers/rtc/rtc-mxc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/rtc/rtc-mxc.c 2010-08-10 04:16:12.000000000 -0400 @@ -0,0 +1,989 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2009 Amazon Technologies, Inc. All Rights Reserved. + * Manish Lachwani (lachwani@lab126.com) + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/* + * Implementation based on rtc-ds1553.c + */ + +/*! + * @defgroup RTC Real Time Clock (RTC) Driver + */ +/*! + * @file rtc-mxc.c + * @brief Real Time Clock interface + * + * This file contains Real Time Clock interface for Linux. + * + * @ingroup RTC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#define RTC_INPUT_CLK_32768HZ (0x00 << 5) +#define RTC_INPUT_CLK_32000HZ (0x01 << 5) +#define RTC_INPUT_CLK_38400HZ (0x02 << 5) + +#define RTC_SW_BIT (1 << 0) +#define RTC_ALM_BIT (1 << 2) +#define RTC_1HZ_BIT (1 << 4) +#define RTC_2HZ_BIT (1 << 7) +#define RTC_SAM0_BIT (1 << 8) +#define RTC_SAM1_BIT (1 << 9) +#define RTC_SAM2_BIT (1 << 10) +#define RTC_SAM3_BIT (1 << 11) +#define RTC_SAM4_BIT (1 << 12) +#define RTC_SAM5_BIT (1 << 13) +#define RTC_SAM6_BIT (1 << 14) +#define RTC_SAM7_BIT (1 << 15) +#define PIT_ALL_ON (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \ + RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \ + RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT) + +#define RTC_ENABLE_BIT (1 << 7) + +#define MAX_PIE_NUM 9 +#define MAX_PIE_FREQ 512 +const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = { + {2, RTC_2HZ_BIT}, + {4, RTC_SAM0_BIT}, + {8, RTC_SAM1_BIT}, + {16, RTC_SAM2_BIT}, + {32, RTC_SAM3_BIT}, + {64, RTC_SAM4_BIT}, + {128, RTC_SAM5_BIT}, + {256, RTC_SAM6_BIT}, + {MAX_PIE_FREQ, RTC_SAM7_BIT}, +}; + +/* Those are the bits from a classic RTC we want to mimic */ +#define RTC_IRQF 0x80 /* any of the following 3 is active */ +#define RTC_PF 0x40 /* Periodic interrupt */ +#define RTC_AF 0x20 /* Alarm interrupt */ +#define RTC_UF 0x10 /* Update interrupt for 1Hz RTC */ + +#define MXC_RTC_TIME 0 +#define MXC_RTC_ALARM 1 + +#define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */ +#define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */ +#define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */ +#define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */ +#define RTC_RTCCTL 0x10 /* 32bit rtc control reg */ +#define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */ +#define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */ +#define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */ +#define RTC_DAYR 0x20 /* 32bit rtc days counter reg */ +#define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */ +#define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */ +#define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */ +#define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */ + +struct rtc_plat_data { + struct rtc_device *rtc; + void __iomem *ioaddr; + unsigned long baseaddr; + int irq; + struct clk *clk; + unsigned int irqen; + int alrm_sec; + int alrm_min; + int alrm_hour; + int alrm_mday; +}; + +/*! + * @defgroup RTC Real Time Clock (RTC) Driver + */ +/*! + * @file rtc-mxc.c + * @brief Real Time Clock interface + * + * This file contains Real Time Clock interface for Linux. + * + * @ingroup RTC + */ + +#if defined(CONFIG_MXC_MC13783_RTC) || defined(CONFIG_MXC_MC13892_RTC) +#include +#else +#define pmic_rtc_get_time(args) MXC_EXTERNAL_RTC_NONE +#define pmic_rtc_set_time(args) MXC_EXTERNAL_RTC_NONE +#define pmic_rtc_loaded() 0 +#endif + +#define RTC_VERSION "1.0" +#define MXC_EXTERNAL_RTC_OK 0 +#define MXC_EXTERNAL_RTC_ERR -1 +#define MXC_EXTERNAL_RTC_NONE -2 + +static struct device *mxc_rtc_dev; + +#define RTC_TIMER_THRESHOLD 30000 /* 30 seconds */ +static void do_rtc_work(struct work_struct *work); +static DECLARE_DELAYED_WORK(rtc_work, do_rtc_work); + +/* The last good value of the rtc time */ +extern u32 saved_last_seconds; + +/*! + * Early charging + */ +#define PMIC_ICHRG_DEFAULT_VALUE 0x3 /* Max current draw of 293mA */ +#define PMIC_ICHRG_MASK 0xf /* ICHRG is 4 bits */ +#define PMIC_ICHRG_LSH 3 /* Bits 3-6 are for ICHRG */ + +/*! + * Both MEMA and MEMB are 24-bit registers. The pmic rtc time is 32-bit. + * We save the top 8 bits in MEM_A and bottom 24 bits into MEM_B. + */ +static void do_rtc_work(struct work_struct *work) +{ + int ret = 0; + struct timeval tmp; + u32 seconds; + unsigned int regA = 0, regB = 0; + + if (!pmic_rtc_loaded()) { + goto out; + } + + ret = pmic_rtc_get_time(&tmp); + + if (!ret) { + seconds = tmp.tv_sec; + + if (seconds > saved_last_seconds) { + /* Mask out 24-bits and save the rtc value */ + regB = seconds & 0x00ffffff; + pmic_write_reg(REG_MEM_B, regB, 0x00ffffff); + + /* The upper 8-bits are stored in MEM_A begining at location 16 */ + regA = (seconds & 0xff000000) >> 24; + pmic_write_reg(REG_MEM_A, (regA << 16), (0xff << 16)); + } + } +out: + schedule_delayed_work(&rtc_work, msecs_to_jiffies(RTC_TIMER_THRESHOLD)); +} + +static int show_rtc_pmic_epoch_time(struct device *dev, struct device_attribute *attr, char *buf) +{ + u32 seconds; + unsigned int regA = 0, regB = 0; + + pmic_read_reg(REG_MEM_A, ®A, (0xff << 16)); + pmic_read_reg(REG_MEM_B, ®B, 0x00ffffff); + + regA &= 0x00ff0000; /* Clear out the remaining bits */ + + /* Extra shift the MEM_A value */ + seconds = (regA << 8) | regB; + return sprintf(buf, "%x\n", seconds); +} +static DEVICE_ATTR(rtc_pmic_epoch_time, 0666, show_rtc_pmic_epoch_time, NULL); + +static int show_rtc_saved_last_seconds(struct device *dev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%x\n", saved_last_seconds); +} +static DEVICE_ATTR(rtc_saved_last_seconds, 0666, show_rtc_saved_last_seconds, NULL); + +/*! + * This function reads the RTC value from some external source. + * + * @param second pointer to the returned value in second + * + * @return 0 if successful; non-zero otherwise + */ +int get_ext_rtc_time(u32 * second) +{ + int ret = 0; + struct timeval tmp; + if (!pmic_rtc_loaded()) { + return MXC_EXTERNAL_RTC_NONE; + } + + ret = pmic_rtc_get_time(&tmp); + + if (0 == ret) + *second = tmp.tv_sec; + else + ret = MXC_EXTERNAL_RTC_ERR; + + return ret; +} + +/*! + * This function sets external RTC + * + * @param second value in second to be set to external RTC + * + * @return 0 if successful; non-zero otherwise + */ +int set_ext_rtc_time(u32 second) +{ + int ret = 0; + struct timeval tmp; + + if (!pmic_rtc_loaded()) { + return MXC_EXTERNAL_RTC_NONE; + } + + tmp.tv_sec = second; + + ret = pmic_rtc_set_time(&tmp); + + if (0 != ret) + ret = MXC_EXTERNAL_RTC_ERR; + + return ret; +} + +static u32 rtc_freq = 2; /* minimun value for PIE */ +static unsigned long rtc_status; + +static struct rtc_time g_rtc_alarm = { + .tm_year = 0, + .tm_mon = 0, + .tm_mday = 0, + .tm_hour = 0, + .tm_mon = 0, + .tm_sec = 0, +}; + +static DEFINE_SPINLOCK(rtc_lock); + +/*! + * This function is used to obtain the RTC time or the alarm value in + * second. + * + * @param time_alarm use MXC_RTC_TIME for RTC time value; MXC_RTC_ALARM for alarm value + * + * @return The RTC time or alarm time in second. + */ +static u32 get_alarm_or_time(struct device *dev, int time_alarm) +{ + struct platform_device *pdev = to_platform_device(dev); + struct rtc_plat_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + u32 day, hr, min, sec, hr_min; + if (time_alarm == MXC_RTC_TIME) { + day = readw(ioaddr + RTC_DAYR); + hr_min = readw(ioaddr + RTC_HOURMIN); + sec = readw(ioaddr + RTC_SECOND); + } else if (time_alarm == MXC_RTC_ALARM) { + day = readw(ioaddr + RTC_DAYALARM); + hr_min = (0x0000FFFF) & readw(ioaddr + RTC_ALRM_HM); + sec = readw(ioaddr + RTC_ALRM_SEC); + } else { + panic("wrong value for time_alarm=%d\n", time_alarm); + } + + hr = hr_min >> 8; + min = hr_min & 0x00FF; + + return ((((day * 24 + hr) * 60) + min) * 60 + sec); +} + +/*! + * This function sets the RTC alarm value or the time value. + * + * @param time_alarm the new alarm value to be updated in the RTC + * @param time use MXC_RTC_TIME for RTC time value; MXC_RTC_ALARM for alarm value + */ +static void set_alarm_or_time(struct device *dev, int time_alarm, u32 time) +{ + u32 day, hr, min, sec, temp; + struct platform_device *pdev = to_platform_device(dev); + struct rtc_plat_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + day = time / 86400; + time -= day * 86400; + /* time is within a day now */ + hr = time / 3600; + time -= hr * 3600; + /* time is within an hour now */ + min = time / 60; + sec = time - min * 60; + + temp = (hr << 8) + min; + + if (time_alarm == MXC_RTC_TIME) { + writew(day, ioaddr + RTC_DAYR); + writew(sec, ioaddr + RTC_SECOND); + writew(temp, ioaddr + RTC_HOURMIN); + } else if (time_alarm == MXC_RTC_ALARM) { + writew(day, ioaddr + RTC_DAYALARM); + writew(sec, ioaddr + RTC_ALRM_SEC); + writew(temp, ioaddr + RTC_ALRM_HM); + } else { + panic("wrong value for time_alarm=%d\n", time_alarm); + } +} + +/*! + * This function updates the RTC alarm registers and then clears all the + * interrupt status bits. + * + * @param alrm the new alarm value to be updated in the RTC + * + * @return 0 if successful; non-zero otherwise. + */ +static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm) +{ + struct rtc_time alarm_tm, now_tm; + unsigned long now, time; + int ret; + struct platform_device *pdev = to_platform_device(dev); + struct rtc_plat_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + + now = get_alarm_or_time(dev, MXC_RTC_TIME); + rtc_time_to_tm(now, &now_tm); + alarm_tm.tm_year = now_tm.tm_year; + alarm_tm.tm_mon = now_tm.tm_mon; + alarm_tm.tm_mday = now_tm.tm_mday; + alarm_tm.tm_hour = alrm->tm_hour; + alarm_tm.tm_min = alrm->tm_min; + alarm_tm.tm_sec = alrm->tm_sec; + rtc_tm_to_time(&now_tm, &now); + rtc_tm_to_time(&alarm_tm, &time); + if (time < now) { + time += 60 * 60 * 24; + rtc_time_to_tm(time, &alarm_tm); + } + ret = rtc_tm_to_time(&alarm_tm, &time); + + /* clear all the interrupt status bits */ + writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR); + + set_alarm_or_time(dev, MXC_RTC_ALARM, time); + + return ret; +} + +/*! + * This function is the RTC interrupt service routine. + * + * @param irq RTC IRQ number + * @param dev_id device ID which is not used + * + * @return IRQ_HANDLED as defined in the include/linux/interrupt.h file. + */ +static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id) +{ + struct platform_device *pdev = dev_id; + struct rtc_plat_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + u32 status; + u32 events = 0; + spin_lock(&rtc_lock); + status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR); + /* clear interrupt sources */ + writew(status, ioaddr + RTC_RTCISR); + + /* clear alarm interrupt if it has occurred */ + if (status & RTC_ALM_BIT) { + status &= ~RTC_ALM_BIT; + } + + /* update irq data & counter */ + if (status & RTC_ALM_BIT) { + events |= (RTC_AF | RTC_IRQF); + } + if (status & RTC_1HZ_BIT) { + events |= (RTC_UF | RTC_IRQF); + } + if (status & PIT_ALL_ON) { + events |= (RTC_PF | RTC_IRQF); + } + + if ((status & RTC_ALM_BIT) && rtc_valid_tm(&g_rtc_alarm)) { + rtc_update_alarm(&pdev->dev, &g_rtc_alarm); + } + + spin_unlock(&rtc_lock); + rtc_update_irq(pdata->rtc, 1, events); + return IRQ_HANDLED; +} + +/*! + * This function is used to open the RTC driver by registering the RTC + * interrupt service routine. + * + * @return 0 if successful; non-zero otherwise. + */ +static int mxc_rtc_open(struct device *dev) +{ + if (test_and_set_bit(1, &rtc_status)) + return -EBUSY; + return 0; +} + +/*! + * clear all interrupts and release the IRQ + */ +static void mxc_rtc_release(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct rtc_plat_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + + spin_lock_irq(&rtc_lock); + writew(0, ioaddr + RTC_RTCIENR); /* Disable all rtc interrupts */ + writew(0xFFFFFFFF, ioaddr + RTC_RTCISR); /* Clear all interrupt status */ + spin_unlock_irq(&rtc_lock); + rtc_status = 0; +} + +/*! + * This function is used to support some ioctl calls directly. + * Other ioctl calls are supported indirectly through the + * arm/common/rtctime.c file. + * + * @param cmd ioctl command as defined in include/linux/rtc.h + * @param arg value for the ioctl command + * + * @return 0 if successful or negative value otherwise. + */ +static int mxc_rtc_ioctl(struct device *dev, unsigned int cmd, + unsigned long arg) +{ + struct platform_device *pdev = to_platform_device(dev); + struct rtc_plat_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + int i; + switch (cmd) { + case RTC_PIE_OFF: + writew((readw(ioaddr + RTC_RTCIENR) & ~PIT_ALL_ON), + ioaddr + RTC_RTCIENR); + return 0; + case RTC_IRQP_SET: + if (arg < 2 || arg > MAX_PIE_FREQ || (arg % 2) != 0) + return -EINVAL; /* Also make sure a power of 2Hz */ + if ((arg > 64) && (!capable(CAP_SYS_RESOURCE))) + return -EACCES; + rtc_freq = arg; + return 0; + case RTC_IRQP_READ: + return put_user(rtc_freq, (u32 *) arg); + case RTC_PIE_ON: + for (i = 0; i < MAX_PIE_NUM; i++) { + if (PIE_BIT_DEF[i][0] == rtc_freq) { + break; + } + } + if (i == MAX_PIE_NUM) { + return -EACCES; + } + spin_lock_irq(&rtc_lock); + writew((readw(ioaddr + RTC_RTCIENR) | PIE_BIT_DEF[i][1]), + ioaddr + RTC_RTCIENR); + spin_unlock_irq(&rtc_lock); + return 0; + case RTC_AIE_OFF: + spin_lock_irq(&rtc_lock); + writew((readw(ioaddr + RTC_RTCIENR) & ~RTC_ALM_BIT), + ioaddr + RTC_RTCIENR); + spin_unlock_irq(&rtc_lock); + return 0; + + case RTC_AIE_ON: + spin_lock_irq(&rtc_lock); + writew((readw(ioaddr + RTC_RTCIENR) | RTC_ALM_BIT), + ioaddr + RTC_RTCIENR); + spin_unlock_irq(&rtc_lock); + return 0; + + case RTC_UIE_OFF: /* UIE is for the 1Hz interrupt */ + spin_lock_irq(&rtc_lock); + writew((readw(ioaddr + RTC_RTCIENR) & ~RTC_1HZ_BIT), + ioaddr + RTC_RTCIENR); + spin_unlock_irq(&rtc_lock); + return 0; + + case RTC_UIE_ON: + spin_lock_irq(&rtc_lock); + writew((readw(ioaddr + RTC_RTCIENR) | RTC_1HZ_BIT), + ioaddr + RTC_RTCIENR); + spin_unlock_irq(&rtc_lock); + return 0; + } + return -ENOIOCTLCMD; +} + +/*! + * This function reads the current RTC time into tm in Gregorian date. + * + * @param tm contains the RTC time value upon return + * + * @return 0 if successful; non-zero otherwise. + */ +static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + u32 val; + + /* Avoid roll-over from reading the different registers */ + do { + val = get_alarm_or_time(dev, MXC_RTC_TIME); + } while (val != get_alarm_or_time(dev, MXC_RTC_TIME)); + + rtc_time_to_tm(val, tm); + return 0; +} + +/*! + * This function sets the internal RTC time based on tm in Gregorian date. + * + * @param tm the time value to be set in the RTC + * + * @return 0 if successful; non-zero otherwise. + */ +static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + unsigned long time; + int ret; + ret = rtc_tm_to_time(tm, &time); + if (ret != 0) { + return ret; + } + + /* Avoid roll-over from reading the different registers */ + do { + set_alarm_or_time(dev, MXC_RTC_TIME, time); + } while (time != get_alarm_or_time(dev, MXC_RTC_TIME)); + + ret = set_ext_rtc_time(time); + + if (ret != MXC_EXTERNAL_RTC_OK) { + if (ret == MXC_EXTERNAL_RTC_NONE) { + pr_info("No external RTC\n"); + ret = 0; + } else + pr_info("Failed to set external RTC\n"); + } + + return ret; +} + +/*! + * This function reads the current alarm value into the passed in \b alrm + * argument. It updates the \b alrm's pending field value based on the whether + * an alarm interrupt occurs or not. + * + * @param alrm contains the RTC alarm value upon return + * + * @return 0 if successful; non-zero otherwise. + */ +static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct platform_device *pdev = to_platform_device(dev); + struct rtc_plat_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + + rtc_time_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time); + alrm->pending = + ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT) != 0) ? 1 : 0; + + return 0; +} + +/*! + * This function sets the RTC alarm based on passed in alrm. + * + * @param alrm the alarm value to be set in the RTC + * + * @return 0 if successful; non-zero otherwise. + */ +static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct platform_device *pdev = to_platform_device(dev); + struct rtc_plat_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + int ret; + + spin_lock_irq(&rtc_lock); + if (rtc_valid_tm(&alrm->time)) { + if (alrm->time.tm_sec > 59 || + alrm->time.tm_hour > 23 || alrm->time.tm_min > 59) { + ret = -EINVAL; + goto out; + } + ret = rtc_update_alarm(dev, &alrm->time); + } else { + if ((ret = rtc_valid_tm(&alrm->time))) + goto out; + ret = rtc_update_alarm(dev, &alrm->time); + } + + if (ret == 0) { + memcpy(&g_rtc_alarm, &alrm->time, sizeof(struct rtc_time)); + + if (alrm->enabled) { + writew((readw(ioaddr + RTC_RTCIENR) | RTC_ALM_BIT), + ioaddr + RTC_RTCIENR); + } else { + writew((readw(ioaddr + RTC_RTCIENR) & ~RTC_ALM_BIT), + ioaddr + RTC_RTCIENR); + } + } + out: + spin_unlock_irq(&rtc_lock); + + return ret; +} + +/*! + * This function is used to provide the content for the /proc/driver/rtc + * file. + * + * @param buf the buffer to hold the information that the driver wants to write + * + * @return The number of bytes written into the rtc file. + */ +static int mxc_rtc_proc(struct device *dev, struct seq_file *sq) +{ + struct platform_device *pdev = to_platform_device(dev); + struct rtc_plat_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + char *p = sq->buf; + + p += sprintf(p, "alarm_IRQ\t: %s\n", + (((readw(ioaddr + RTC_RTCIENR)) & RTC_ALM_BIT) != + 0) ? "yes" : "no"); + p += sprintf(p, "update_IRQ\t: %s\n", + (((readw(ioaddr + RTC_RTCIENR)) & RTC_1HZ_BIT) != + 0) ? "yes" : "no"); + p += sprintf(p, "periodic_IRQ\t: %s\n", + (((readw(ioaddr + RTC_RTCIENR)) & PIT_ALL_ON) != + 0) ? "yes" : "no"); + p += sprintf(p, "periodic_freq\t: %d\n", rtc_freq); + + return p - (sq->buf); +} + +/*! + * The RTC driver structure + */ +static struct rtc_class_ops mxc_rtc_ops = { + .open = mxc_rtc_open, + .release = mxc_rtc_release, + .ioctl = mxc_rtc_ioctl, + .read_time = mxc_rtc_read_time, + .set_time = mxc_rtc_set_time, + .read_alarm = mxc_rtc_read_alarm, + .set_alarm = mxc_rtc_set_alarm, + .proc = mxc_rtc_proc, +}; + +static long wakeup_value = 0; + +static ssize_t wakeup_enable_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%ld\n", wakeup_value); +} + +static ssize_t wakeup_enable_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + int ret; + struct timeval tmp; + int value = 0; + + if (sscanf(buf, "%d", &value) <= 0) { + printk(KERN_ERR "Error setting the wakeup value in PMIC RTC\n"); + return -EINVAL; + } + + if (value != 0) { + ret = pmic_rtc_get_time(&tmp); + if (ret < 0) + printk (KERN_ERR "Failed reading time from RTC\n"); + + tmp.tv_sec += value; + + ret = pmic_rtc_set_time_alarm(&tmp); + + if (ret < 0) + printk (KERN_ERR "Failed setting ALARM for suspend wakeup\n"); + + /* Clear TODAI interrupt flag and unmask TODAM */ + pmic_write_reg(REG_INT_STATUS1, 0, 0x2); + pmic_write_reg(REG_INT_MASK1, 0, 0x2); + + wakeup_value = value; + } + + return size; +} + +static DEVICE_ATTR(wakeup_enable, 0644, wakeup_enable_show, wakeup_enable_store); + +/*! MXC RTC Power management control */ + +static struct timespec mxc_rtc_delta; + +static int mxc_rtc_probe(struct platform_device *pdev) +{ + struct clk *clk; + struct timespec tv; + struct resource *res; + struct rtc_time temp_time; + struct rtc_device *rtc; + struct rtc_plat_data *pdata = NULL; + u32 sec, reg; + int ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + pdata->clk = clk_get(&pdev->dev, "rtc_clk"); + clk_enable(pdata->clk); + + pdata->baseaddr = res->start; + pdata->ioaddr = ((void *)(IO_ADDRESS(pdata->baseaddr))); + /* Configure and enable the RTC */ + pdata->irq = platform_get_irq(pdev, 0); + if (pdata->irq >= 0) { + if (request_irq(pdata->irq, mxc_rtc_interrupt, IRQF_SHARED, + pdev->name, pdev) < 0) { + dev_warn(&pdev->dev, "interrupt not available.\n"); + pdata->irq = -1; + } + } + rtc = + rtc_device_register(pdev->name, &pdev->dev, &mxc_rtc_ops, + THIS_MODULE); + if (IS_ERR(rtc)) { + ret = PTR_ERR(rtc); + if (pdata->irq >= 0) + free_irq(pdata->irq, pdev); + kfree(pdata); + return ret; + } + pdata->rtc = rtc; + platform_set_drvdata(pdev, pdata); + ret = get_ext_rtc_time(&sec); + + /* + * If the current time is less than the saved time, use the saved time + */ + if (sec < saved_last_seconds) { + sec = saved_last_seconds; + set_ext_rtc_time(sec); + } + + if (ret == MXC_EXTERNAL_RTC_OK) { + rtc_time_to_tm(sec, &temp_time); + mxc_rtc_set_time(&pdev->dev, &temp_time); + + } else if (ret == MXC_EXTERNAL_RTC_NONE) { + pr_info("No external RTC clock\n"); + } else { + pr_info("Reading external RTC failed\n"); + } + tv.tv_nsec = 0; + tv.tv_sec = get_alarm_or_time(&pdev->dev, MXC_RTC_TIME); + clk = clk_get(NULL, "ckil"); + if (clk_get_rate(clk) == 32768) + reg = RTC_INPUT_CLK_32768HZ; + else if (clk_get_rate(clk) == 32000) + reg = RTC_INPUT_CLK_32000HZ; + else if (clk_get_rate(clk) == 38400) + reg = RTC_INPUT_CLK_38400HZ; + else { + printk(KERN_ALERT "rtc clock is not valid"); + return -EINVAL; + } + clk_put(clk); + reg |= RTC_ENABLE_BIT; + writew(reg, (pdata->ioaddr + RTC_RTCCTL)); + if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) { + printk(KERN_ALERT "rtc : hardware module can't be enabled!\n"); + return -EPERM; + } + printk("Real Time clock Driver v%s \n", RTC_VERSION); + + mxc_rtc_dev = &pdev->dev; + if (sysfs_create_file(&mxc_rtc_dev->kobj, &dev_attr_wakeup_enable.attr) < 0) + printk (KERN_ERR "Error - could not create RTC sysfs entry\n"); + + device_init_wakeup(&pdev->dev, 1); + schedule_delayed_work(&rtc_work, msecs_to_jiffies(RTC_TIMER_THRESHOLD)); + if (device_create_file(&pdev->dev, &dev_attr_rtc_pmic_epoch_time) < 0) + printk (KERN_ERR "mxc_rtc: error creating rtc_pmic_epoch_time entry\n"); + + if (device_create_file(&pdev->dev, &dev_attr_rtc_saved_last_seconds) < 0) + printk (KERN_ERR "mxc_rtc: error creating rtc_saved_last_seconds entry\n"); + + return ret; +} + +static int __exit mxc_rtc_remove(struct platform_device *pdev) +{ + struct rtc_plat_data *pdata = platform_get_drvdata(pdev); + rtc_device_unregister(pdata->rtc); + if (pdata->irq >= 0) { + free_irq(pdata->irq, pdev); + } + cancel_rearming_delayed_work(&rtc_work); + sysfs_remove_file(&mxc_rtc_dev->kobj, &dev_attr_wakeup_enable.attr); + device_remove_file(&pdev->dev, &dev_attr_rtc_pmic_epoch_time); + device_remove_file(&pdev->dev, &dev_attr_rtc_saved_last_seconds); + clk_disable(pdata->clk); + clk_put(pdata->clk); + kfree(pdata); + mxc_rtc_release(NULL); + return 0; +} + +unsigned long suspend_time = 0; +unsigned long last_suspend_time = 0; +unsigned long total_suspend_time = 0; + +/*! + * This function is called to save the system time delta relative to + * the MXC RTC when enterring a low power state. This time delta is + * then used on resume to adjust the system time to account for time + * loss while suspended. + * + * @param pdev not used + * @param state Power state to enter. + * + * @return The function always returns 0. + */ +static int mxc_rtc_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct timespec tv; + struct timeval tmp; + struct timespec now = current_kernel_time(); + + /* calculate time delta for suspend */ + /* RTC precision is 1 second; adjust delta for avg 1/2 sec err */ + tv.tv_nsec = NSEC_PER_SEC >> 1; + tv.tv_sec = get_alarm_or_time(&pdev->dev, MXC_RTC_TIME); + + pmic_rtc_get_time(&tmp); + suspend_time = tmp.tv_sec; + set_normalized_timespec(&mxc_rtc_delta, + now.tv_sec - tv.tv_sec, + now.tv_nsec - tv.tv_nsec); + + if (wakeup_value != 0) { + if (device_may_wakeup(&pdev->dev)) + enable_irq_wake(platform_get_irq(pdev, 0)); + } + + cancel_rearming_delayed_work(&rtc_work); + return 0; +} + +/*! + * This function is called to correct the system time based on the + * current MXC RTC time relative to the time delta saved during + * suspend. + * + * @param pdev not used + * + * @return The function always returns 0. + */ +static int mxc_rtc_resume(struct platform_device *pdev) +{ + struct timespec tv; + struct timespec ts; + struct timeval tmp; + unsigned long resume_time = 0; + + if (wakeup_value != 0) { + wakeup_value = 0; + if (device_may_wakeup(&pdev->dev)) + disable_irq_wake(platform_get_irq(pdev, 0)); + } + + tv.tv_nsec = 0; + tv.tv_sec = get_alarm_or_time(&pdev->dev, MXC_RTC_TIME); + + pmic_rtc_get_time(&tmp); + resume_time = tmp.tv_sec; + + /* restore wall clock using delta against this RTC; + * adjust again for avg 1/2 second RTC sampling error + */ + set_normalized_timespec(&ts, + tv.tv_sec + mxc_rtc_delta.tv_sec, + (NSEC_PER_SEC >> 1) + mxc_rtc_delta.tv_nsec); + do_settimeofday(&ts); + last_suspend_time = resume_time - suspend_time; + total_suspend_time += last_suspend_time; + schedule_delayed_work(&rtc_work, msecs_to_jiffies(RTC_TIMER_THRESHOLD)); + + return 0; +} + +/*! + * Contains pointers to the power management callback functions. + */ +static struct platform_driver mxc_rtc_driver = { + .driver = { + .name = "mxc_rtc", + }, + .probe = mxc_rtc_probe, + .remove = __exit_p(mxc_rtc_remove), + .suspend = mxc_rtc_suspend, + .resume = mxc_rtc_resume, +}; + +/*! + * This function creates the /proc/driver/rtc file and registers the device RTC + * in the /dev/misc directory. It also reads the RTC value from external source + * and setup the internal RTC properly. + * + * @return -1 if RTC is failed to initialize; 0 is successful. + */ +static int __init mxc_rtc_init(void) +{ + return platform_driver_register(&mxc_rtc_driver); +} + +/*! + * This function removes the /proc/driver/rtc file and un-registers the + * device RTC from the /dev/misc directory. + */ +static void __exit mxc_rtc_exit(void) +{ + platform_driver_unregister(&mxc_rtc_driver); + +} + +device_initcall_sync(mxc_rtc_init); +module_exit(mxc_rtc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Realtime Clock Driver (RTC)"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/rtc/rtc-mxc_v2.c linux-2.6.26-lab126/drivers/rtc/rtc-mxc_v2.c --- linux-2.6.26/drivers/rtc/rtc-mxc_v2.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/rtc/rtc-mxc_v2.c 2010-08-10 04:16:12.000000000 -0400 @@ -0,0 +1,762 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/* + * Implementation based on rtc-ds1553.c + */ + +/*! + * @defgroup RTC Real Time Clock (RTC) Driver + */ +/*! + * @file rtc-mxc_v2.c + * @brief Real Time Clock interface + * + * This file contains Real Time Clock interface for Linux. + * + * @ingroup RTC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SRTC_LPPDR_INIT 0x41736166 /* init for glitch detect */ + +#define SRTC_LPCR_SWR_LP (1 << 0) /* lp software reset */ +#define SRTC_LPCR_EN_LP (1 << 3) /* lp enable */ +#define SRTC_LPCR_WAE (1 << 4) /* lp wakeup alarm enable */ +#define SRTC_LPCR_SAE (1 << 5) /* lp security alarm enable */ +#define SRTC_LPCR_SI (1 << 6) /* lp security interrupt enable */ +#define SRTC_LPCR_ALP (1 << 7) /* lp alarm flag */ +#define SRTC_LPCR_LTC (1 << 8) /* lp lock time counter */ +#define SRTC_LPCR_LMC (1 << 9) /* lp lock monotonic counter */ +#define SRTC_LPCR_SV (1 << 10) /* lp security violation */ +#define SRTC_LPCR_NSA (1 << 11) /* lp non secure access */ +#define SRTC_LPCR_NVEIE (1 << 12) /* lp non valid state exit int en */ +#define SRTC_LPCR_IEIE (1 << 13) /* lp init state exit int enable */ +#define SRTC_LPCR_NVE (1 << 14) /* lp non valid state exit bit */ +#define SRTC_LPCR_IE (1 << 15) /* lp init state exit bit */ + +#define SRTC_LPCR_ALL_INT_EN (SRTC_LPCR_WAE | SRTC_LPCR_SAE | \ + SRTC_LPCR_SI | SRTC_LPCR_ALP | \ + SRTC_LPCR_NVEIE | SRTC_LPCR_IEIE) + +#define SRTC_LPSR_TRI (1 << 0) /* lp time read invalidate */ +#define SRTC_LPSR_PGD (1 << 1) /* lp power supply glitc detected */ +#define SRTC_LPSR_CTD (1 << 2) /* lp clock tampering detected */ +#define SRTC_LPSR_ALP (1 << 3) /* lp alarm flag */ +#define SRTC_LPSR_MR (1 << 4) /* lp monotonic counter rollover */ +#define SRTC_LPSR_TR (1 << 5) /* lp time rollover */ +#define SRTC_LPSR_EAD (1 << 6) /* lp external alarm detected */ +#define SRTC_LPSR_IT0 (1 << 7) /* lp IIM throttle */ +#define SRTC_LPSR_IT1 (1 << 8) +#define SRTC_LPSR_IT2 (1 << 9) +#define SRTC_LPSR_SM0 (1 << 10) /* lp security mode */ +#define SRTC_LPSR_SM1 (1 << 11) +#define SRTC_LPSR_STATE_LP0 (1 << 12) /* lp state */ +#define SRTC_LPSR_STATE_LP1 (1 << 13) +#define SRTC_LPSR_NVES (1 << 14) /* lp non-valid state exit status */ +#define SRTC_LPSR_IES (1 << 15) /* lp init state exit status */ + +#define MAX_PIE_NUM 15 +#define MAX_PIE_FREQ 32768 +#define MIN_PIE_FREQ 1 + +#define SRTC_PI0 (1 << 0) +#define SRTC_PI1 (1 << 1) +#define SRTC_PI2 (1 << 2) +#define SRTC_PI3 (1 << 3) +#define SRTC_PI4 (1 << 4) +#define SRTC_PI5 (1 << 5) +#define SRTC_PI6 (1 << 6) +#define SRTC_PI7 (1 << 7) +#define SRTC_PI8 (1 << 8) +#define SRTC_PI9 (1 << 9) +#define SRTC_PI10 (1 << 10) +#define SRTC_PI11 (1 << 11) +#define SRTC_PI12 (1 << 12) +#define SRTC_PI13 (1 << 13) +#define SRTC_PI14 (1 << 14) +#define SRTC_PI15 (1 << 15) + +#define PIT_ALL_ON (SRTC_PI1 | SRTC_PI2 | SRTC_PI3 | \ + SRTC_PI4 | SRTC_PI5 | SRTC_PI6 | SRTC_PI7 | \ + SRTC_PI8 | SRTC_PI9 | SRTC_PI10 | SRTC_PI11 | \ + SRTC_PI12 | SRTC_PI13 | SRTC_PI14 | SRTC_PI15) + +#define SRTC_SWR_HP (1 << 0) /* hp software reset */ +#define SRTC_EN_HP (1 << 3) /* hp enable */ +#define SRTC_TS (1 << 4) /* time syncronize hp with lp */ + +#define SRTC_IE_AHP (1 << 16) /* Alarm HP Interrupt Enable bit */ +#define SRTC_IE_WDHP (1 << 18) /* Write Done HP Interrupt Enable bit */ +#define SRTC_IE_WDLP (1 << 19) /* Write Done LP Interrupt Enable bit */ + +#define SRTC_ISR_AHP (1 << 16) /* interrupt status: alarm hp */ +#define SRTC_ISR_WDHP (1 << 18) /* interrupt status: write done hp */ +#define SRTC_ISR_WDLP (1 << 19) /* interrupt status: write done lp */ +#define SRTC_ISR_WPHP (1 << 20) /* interrupt status: write pending hp */ +#define SRTC_ISR_WPLP (1 << 21) /* interrupt status: write pending lp */ + +#define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */ +#define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */ +#define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */ +#define SRTC_LPSMCR 0x0C /* LP Secure Monotonic Counter Reg */ +#define SRTC_LPCR 0x10 /* LP Control Reg */ +#define SRTC_LPSR 0x14 /* LP Status Reg */ +#define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */ +#define SRTC_LPGR 0x1C /* LP General Purpose Reg */ +#define SRTC_HPCMR 0x20 /* HP Counter MSB Reg */ +#define SRTC_HPCLR 0x24 /* HP Counter LSB Reg */ +#define SRTC_HPAMR 0x28 /* HP Alarm MSB Reg */ +#define SRTC_HPALR 0x2C /* HP Alarm LSB Reg */ +#define SRTC_HPCR 0x30 /* HP Control Reg */ +#define SRTC_HPISR 0x34 /* HP Interrupt Status Reg */ +#define SRTC_HPIENR 0x38 /* HP Interrupt Enable Reg */ + +#define SRTC_SECMODE_MASK 0x3 /* the mask of SRTC security mode */ +#define SRTC_SECMODE_LOW 0x0 /* Low Security */ +#define SRTC_SECMODE_MED 0x1 /* Medium Security */ +#define SRTC_SECMODE_HIGH 0x2 /* High Security */ +#define SRTC_SECMODE_RESERVED 0x3 /* Reserved */ + +struct rtc_drv_data { + struct rtc_device *rtc; + void __iomem *ioaddr; + unsigned long baseaddr; + int irq; + struct clk *clk; + bool irq_enable; +}; + +/*! + * @defgroup RTC Real Time Clock (RTC) Driver + */ +/*! + * @file rtc-mxc.c + * @brief Real Time Clock interface + * + * This file contains Real Time Clock interface for Linux. + * + * @ingroup RTC + */ + +static unsigned long rtc_status; + +static DEFINE_SPINLOCK(rtc_lock); + +/*! + * This function does write synchronization for writes to the lp srtc block. + * To take care of the asynchronous CKIL clock, all writes from the IP domain + * will be synchronized to the CKIL domain. + */ +static inline void rtc_write_sync_lp(void __iomem *ioaddr) +{ + while ((__raw_readl(ioaddr + SRTC_HPISR) & SRTC_ISR_WPLP) != 0) + msleep(1); + while ((__raw_readl(ioaddr + SRTC_HPISR) & SRTC_ISR_WDLP) == 0) + msleep(1); + __raw_writel(SRTC_ISR_WDLP, ioaddr + SRTC_HPISR); + while ((__raw_readl(ioaddr + SRTC_HPISR) & SRTC_ISR_WPHP) != 0) + msleep(1); +} + +static inline void rtc_write_sync_lp_no_wait(void __iomem *ioaddr) +{ + while ((__raw_readl(ioaddr + SRTC_HPISR) & SRTC_ISR_WPLP) != 0); + while ((__raw_readl(ioaddr + SRTC_HPISR) & SRTC_ISR_WDLP) == 0); + __raw_writel(SRTC_ISR_WDLP, ioaddr + SRTC_HPISR); + while ((__raw_readl(ioaddr + SRTC_HPISR) & SRTC_ISR_WPHP) != 0); +} + +/*! + * This function updates the RTC alarm registers and then clears all the + * interrupt status bits. + * + * @param alrm the new alarm value to be updated in the RTC + * + * @return 0 if successful; non-zero otherwise. + */ +static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + void __iomem *ioaddr = pdata->ioaddr; + struct rtc_time alarm_tm, now_tm; + unsigned long now, time; + int ret; + + now = __raw_readl(ioaddr + SRTC_LPSCMR); + rtc_time_to_tm(now, &now_tm); + + alarm_tm.tm_year = now_tm.tm_year; + alarm_tm.tm_mon = now_tm.tm_mon; + alarm_tm.tm_mday = now_tm.tm_mday; + + alarm_tm.tm_hour = alrm->tm_hour; + alarm_tm.tm_min = alrm->tm_min; + alarm_tm.tm_sec = alrm->tm_sec; + + rtc_tm_to_time(&now_tm, &now); + rtc_tm_to_time(&alarm_tm, &time); + + if (time < now) { + time += 60 * 60 * 24; + rtc_time_to_tm(time, &alarm_tm); + } + ret = rtc_tm_to_time(&alarm_tm, &time); + + __raw_writel(time, ioaddr + SRTC_LPSAR); + + /* clear alarm interrupt status bit */ + __raw_writel(SRTC_LPSR_ALP, ioaddr + SRTC_LPSR); + + return ret; +} + +/*! + * This function is the RTC interrupt service routine. + * + * @param irq RTC IRQ number + * @param dev_id device ID which is not used + * + * @return IRQ_HANDLED as defined in the include/linux/interrupt.h file. + */ +static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id) +{ + struct platform_device *pdev = dev_id; + struct rtc_drv_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + u32 lp_status, lp_cr; + u32 events = 0; + + lp_status = __raw_readl(ioaddr + SRTC_LPSR); + lp_cr = __raw_readl(ioaddr + SRTC_LPCR); + + /* update irq data & counter */ + if (lp_status & SRTC_LPSR_ALP) { + if (lp_cr & SRTC_LPCR_ALP) + events |= (RTC_AF | RTC_IRQF); + + /* disable further lp alarm interrupts */ + lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE); + } + + /* Update interrupt enables */ + __raw_writel(lp_cr, ioaddr + SRTC_LPCR); + + /* If no interrupts are enabled, turn off interrupts in kernel */ + if (((lp_cr & SRTC_LPCR_ALL_INT_EN) == 0) && (pdata->irq_enable)) { + disable_irq(pdata->irq); + pdata->irq_enable = false; + } + + /* clear interrupt status */ + __raw_writel(lp_status, ioaddr + SRTC_LPSR); + + rtc_update_irq(pdata->rtc, 1, events); + return IRQ_HANDLED; +} + +/*! + * This function is used to open the RTC driver. + * + * @return 0 if successful; non-zero otherwise. + */ +static int mxc_rtc_open(struct device *dev) +{ + if (test_and_set_bit(1, &rtc_status)) + return -EBUSY; + return 0; +} + +/*! + * clear all interrupts and release the IRQ + */ +static void mxc_rtc_release(struct device *dev) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + void __iomem *ioaddr = pdata->ioaddr; + unsigned long lock_flags = 0; + + spin_lock_irqsave(&rtc_lock, lock_flags); + + /* Disable all rtc interrupts */ + __raw_writel(__raw_readl(ioaddr + SRTC_LPCR) & ~(SRTC_LPCR_ALL_INT_EN), + ioaddr + SRTC_LPCR); + + /* Clear all interrupt status */ + __raw_writel(0xFFFFFFFF, ioaddr + SRTC_LPSR); + + spin_unlock_irqrestore(&rtc_lock, lock_flags); + rtc_status = 0; +} + +/*! + * This function is used to support some ioctl calls directly. + * Other ioctl calls are supported indirectly through the + * arm/common/rtctime.c file. + * + * @param cmd ioctl command as defined in include/linux/rtc.h + * @param arg value for the ioctl command + * + * @return 0 if successful or negative value otherwise. + */ +static int mxc_rtc_ioctl(struct device *dev, unsigned int cmd, + unsigned long arg) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + void __iomem *ioaddr = pdata->ioaddr; + unsigned long lock_flags = 0; + u32 lp_cr; + + switch (cmd) { + case RTC_AIE_OFF: + spin_lock_irqsave(&rtc_lock, lock_flags); + lp_cr = __raw_readl(ioaddr + SRTC_LPCR); + lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE); + if (((lp_cr & SRTC_LPCR_ALL_INT_EN) == 0) + && (pdata->irq_enable)) { + disable_irq(pdata->irq); + pdata->irq_enable = false; + } + __raw_writel(lp_cr, ioaddr + SRTC_LPCR); + spin_unlock_irqrestore(&rtc_lock, lock_flags); + return 0; + + case RTC_AIE_ON: + spin_lock_irqsave(&rtc_lock, lock_flags); + if (!pdata->irq_enable) { + enable_irq(pdata->irq); + pdata->irq_enable = true; + } + lp_cr = __raw_readl(ioaddr + SRTC_LPCR); + lp_cr |= SRTC_LPCR_ALP | SRTC_LPCR_WAE; + __raw_writel(lp_cr, ioaddr + SRTC_LPCR); + spin_unlock_irqrestore(&rtc_lock, lock_flags); + return 0; + } + + return -ENOIOCTLCMD; +} + +/*! + * This function reads the current RTC time into tm in Gregorian date. + * + * @param tm contains the RTC time value upon return + * + * @return 0 if successful; non-zero otherwise. + */ +static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + void __iomem *ioaddr = pdata->ioaddr; + + rtc_time_to_tm(__raw_readl(ioaddr + SRTC_LPSCMR), tm); + return 0; +} + +/*! + * This function sets the internal RTC time based on tm in Gregorian date. + * + * @param tm the time value to be set in the RTC + * + * @return 0 if successful; non-zero otherwise. + */ +static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + void __iomem *ioaddr = pdata->ioaddr; + unsigned long time; + int ret; + ret = rtc_tm_to_time(tm, &time); + if (ret != 0) + return ret; + + __raw_writel(time, ioaddr + SRTC_LPSCMR); + rtc_write_sync_lp(ioaddr); + + return 0; +} + +/*! + * This function reads the current alarm value into the passed in \b alrm + * argument. It updates the \b alrm's pending field value based on the whether + * an alarm interrupt occurs or not. + * + * @param alrm contains the RTC alarm value upon return + * + * @return 0 if successful; non-zero otherwise. + */ +static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + void __iomem *ioaddr = pdata->ioaddr; + + rtc_time_to_tm(__raw_readl(ioaddr + SRTC_LPSAR), &alrm->time); + alrm->pending = + ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_ALP) != 0) ? 1 : 0; + + return 0; +} + +/*! + * This function sets the RTC alarm based on passed in alrm. + * + * @param alrm the alarm value to be set in the RTC + * + * @return 0 if successful; non-zero otherwise. + */ +static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + void __iomem *ioaddr = pdata->ioaddr; + unsigned long lock_flags = 0; + u32 lp_cr; + int ret; + + if (rtc_valid_tm(&alrm->time)) { + if (alrm->time.tm_sec > 59 || + alrm->time.tm_hour > 23 || alrm->time.tm_min > 59) { + return -EINVAL; + } + } + + spin_lock_irqsave(&rtc_lock, lock_flags); + lp_cr = __raw_readl(ioaddr + SRTC_LPCR); + + ret = rtc_update_alarm(dev, &alrm->time); + if (ret) + goto out; + + if (alrm->enabled) + lp_cr |= (SRTC_LPCR_ALP | SRTC_LPCR_WAE); + else + lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE); + + if (lp_cr & SRTC_LPCR_ALL_INT_EN) { + if (!pdata->irq_enable) { + enable_irq(pdata->irq); + pdata->irq_enable = true; + } + } else { + if (pdata->irq_enable) { + disable_irq(pdata->irq); + pdata->irq_enable = false; + } + } + + __raw_writel(lp_cr, ioaddr + SRTC_LPCR); + +out: + spin_unlock_irqrestore(&rtc_lock, lock_flags); + rtc_write_sync_lp(ioaddr); + return ret; +} + +/*! + * This function is used to provide the content for the /proc/driver/rtc + * file. + * + * @param seq buffer to hold the information that the driver wants to write + * + * @return The number of bytes written into the rtc file. + */ +static int mxc_rtc_proc(struct device *dev, struct seq_file *seq) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + void __iomem *ioaddr = pdata->ioaddr; + + seq_printf(seq, "alarm_IRQ\t: %s\n", + (((__raw_readl(ioaddr + SRTC_LPCR)) & SRTC_LPCR_ALP) != + 0) ? "yes" : "no"); + + return 0; +} + +/*! + * The RTC driver structure + */ +static struct rtc_class_ops mxc_rtc_ops = { + .open = mxc_rtc_open, + .release = mxc_rtc_release, + .ioctl = mxc_rtc_ioctl, + .read_time = mxc_rtc_read_time, + .set_time = mxc_rtc_set_time, + .read_alarm = mxc_rtc_read_alarm, + .set_alarm = mxc_rtc_set_alarm, + .proc = mxc_rtc_proc, +}; + +/*! MXC RTC Power management control */ + +static struct timespec mxc_rtc_delta; + +static int mxc_rtc_probe(struct platform_device *pdev) +{ + struct clk *clk; + struct timespec tv; + struct resource *res; + struct rtc_device *rtc; + struct rtc_drv_data *pdata = NULL; + struct mxc_srtc_platform_data *plat_data = NULL; + void __iomem *ioaddr; + void __iomem *srtc_secmode_addr; + int ret = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + pdata->clk = clk_get(&pdev->dev, "rtc_clk"); + clk_enable(pdata->clk); + pdata->baseaddr = res->start; + pdata->ioaddr = ioremap(pdata->baseaddr, 0x40); + ioaddr = pdata->ioaddr; + + /* Configure and enable the RTC */ + pdata->irq = platform_get_irq(pdev, 0); + if (pdata->irq >= 0) { + if (request_irq(pdata->irq, mxc_rtc_interrupt, IRQF_SHARED, + pdev->name, pdev) < 0) { + dev_warn(&pdev->dev, "interrupt not available.\n"); + pdata->irq = -1; + } else { + disable_irq(pdata->irq); + pdata->irq_enable = false; + } + } + + clk = clk_get(NULL, "rtc_clk"); + if (clk_get_rate(clk) != 32768) { + printk(KERN_ALERT "rtc clock is not valid"); + ret = -EINVAL; + clk_put(clk); + goto err_out; + } + clk_put(clk); + + /* initialize glitch detect */ + __raw_writel(SRTC_LPPDR_INIT, ioaddr + SRTC_LPPDR); + rtc_write_sync_lp_no_wait(ioaddr); + + /* clear lp interrupt status */ + __raw_writel(0xFFFFFFFF, ioaddr + SRTC_LPSR); + rtc_write_sync_lp_no_wait(ioaddr); + + plat_data = (struct mxc_srtc_platform_data *)pdev->dev.platform_data; + clk = clk_get(NULL, "iim_clk"); + clk_enable(clk); + srtc_secmode_addr = ioremap(plat_data->srtc_sec_mode_addr, 1); + + /* Check SRTC security mode */ + if (((__raw_readl(srtc_secmode_addr) & SRTC_SECMODE_MASK) == + SRTC_SECMODE_LOW) && (cpu_is_mx51_rev(CHIP_REV_1_0) == 1)) { + /* Workaround for MX51 TO1 due to inaccurate CKIL clock */ + __raw_writel(SRTC_LPCR_EN_LP, ioaddr + SRTC_LPCR); + rtc_write_sync_lp_no_wait(ioaddr); + } else { + /* move out of init state */ + __raw_writel((SRTC_LPCR_IE | SRTC_LPCR_NSA), + ioaddr + SRTC_LPCR); + + rtc_write_sync_lp_no_wait(ioaddr); + + while ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_IES) == 0); + + /* move out of non-valid state */ + __raw_writel((SRTC_LPCR_IE | SRTC_LPCR_NVE | SRTC_LPCR_NSA | + SRTC_LPCR_EN_LP), ioaddr + SRTC_LPCR); + + rtc_write_sync_lp_no_wait(ioaddr); + + while ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_NVES) == 0); + + __raw_writel(0xFFFFFFFF, ioaddr + SRTC_LPSR); + rtc_write_sync_lp_no_wait(ioaddr); + } + clk_disable(clk); + clk_put(clk); + + rtc = rtc_device_register(pdev->name, &pdev->dev, + &mxc_rtc_ops, THIS_MODULE); + if (IS_ERR(rtc)) { + ret = PTR_ERR(rtc); + goto err_out; + } + + pdata->rtc = rtc; + platform_set_drvdata(pdev, pdata); + + tv.tv_nsec = 0; + tv.tv_sec = __raw_readl(ioaddr + SRTC_LPSCMR); + + /* By default, devices should wakeup if they can */ + /* So srtc is set as "should wakeup" as it can */ + device_init_wakeup(&pdev->dev, 1); + + return ret; + +err_out: + clk_disable(pdata->clk); + iounmap(ioaddr); + if (pdata->irq >= 0) + free_irq(pdata->irq, pdev); + kfree(pdata); + return ret; +} + +static int __exit mxc_rtc_remove(struct platform_device *pdev) +{ + struct rtc_drv_data *pdata = platform_get_drvdata(pdev); + rtc_device_unregister(pdata->rtc); + if (pdata->irq >= 0) + free_irq(pdata->irq, pdev); + + clk_disable(pdata->clk); + clk_put(pdata->clk); + kfree(pdata); + mxc_rtc_release(NULL); + return 0; +} + +/*! + * This function is called to save the system time delta relative to + * the MXC RTC when enterring a low power state. This time delta is + * then used on resume to adjust the system time to account for time + * loss while suspended. + * + * @param pdev not used + * @param state Power state to enter. + * + * @return The function always returns 0. + */ +static int mxc_rtc_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct rtc_drv_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + struct timespec tv; + + if (device_may_wakeup(&pdev->dev)) { + enable_irq_wake(pdata->irq); + } else { + /* calculate time delta for suspend. RTC precision is + 1 second; adjust delta for avg 1/2 sec err */ + tv.tv_nsec = NSEC_PER_SEC >> 1; + tv.tv_sec = __raw_readl(ioaddr + SRTC_LPSCMR); + set_normalized_timespec(&mxc_rtc_delta, + xtime.tv_sec - tv.tv_sec, + xtime.tv_nsec - tv.tv_nsec); + + if (pdata->irq_enable) + disable_irq(pdata->irq); + } + + clk_disable(pdata->clk); + + return 0; +} + +/*! + * This function is called to correct the system time based on the + * current MXC RTC time relative to the time delta saved during + * suspend. + * + * @param pdev not used + * + * @return The function always returns 0. + */ +static int mxc_rtc_resume(struct platform_device *pdev) +{ + struct rtc_drv_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + struct timespec tv; + struct timespec ts; + + clk_enable(pdata->clk); + + if (device_may_wakeup(&pdev->dev)) { + disable_irq_wake(pdata->irq); + } else { + if (pdata->irq_enable) + enable_irq(pdata->irq); + + tv.tv_nsec = 0; + tv.tv_sec = __raw_readl(ioaddr + SRTC_LPSCMR); + + /* + * restore wall clock using delta against this RTC; + * adjust again for avg 1/2 second RTC sampling error + */ + set_normalized_timespec(&ts, + tv.tv_sec + mxc_rtc_delta.tv_sec, + (NSEC_PER_SEC >> 1) + + mxc_rtc_delta.tv_nsec); + do_settimeofday(&ts); + } + + return 0; +} + +/*! + * Contains pointers to the power management callback functions. + */ +static struct platform_driver mxc_rtc_driver = { + .driver = { + .name = "mxc_rtc", + }, + .probe = mxc_rtc_probe, + .remove = __exit_p(mxc_rtc_remove), + .suspend = mxc_rtc_suspend, + .resume = mxc_rtc_resume, +}; + +/*! + * This function creates the /proc/driver/rtc file and registers the device RTC + * in the /dev/misc directory. It also reads the RTC value from external source + * and setup the internal RTC properly. + * + * @return -1 if RTC is failed to initialize; 0 is successful. + */ +static int __init mxc_rtc_init(void) +{ + return platform_driver_register(&mxc_rtc_driver); +} + +/*! + * This function removes the /proc/driver/rtc file and un-registers the + * device RTC from the /dev/misc directory. + */ +static void __exit mxc_rtc_exit(void) +{ + platform_driver_unregister(&mxc_rtc_driver); + +} + +module_init(mxc_rtc_init); +module_exit(mxc_rtc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Realtime Clock Driver (RTC)"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/scsi/.gitignore linux-2.6.26-lab126/drivers/scsi/.gitignore --- linux-2.6.26/drivers/scsi/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/scsi/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1 +0,0 @@ -53c700_d.h diff -urN linux-2.6.26/drivers/scsi/aacraid/aacraid.h linux-2.6.26-lab126/drivers/scsi/aacraid/aacraid.h --- linux-2.6.26/drivers/scsi/aacraid/aacraid.h 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/scsi/aacraid/aacraid.h 2010-08-10 04:17:22.000000000 -0400 @@ -719,7 +719,7 @@ u32 unique; // unique value representing this context ulong jiffies; // used for cleanup - dmb changed to ulong struct list_head next; // used to link context's into a linked list - struct semaphore wait_sem; // this is used to wait for the next fib to arrive. + struct compat_semaphore wait_sem; // this is used to wait for the next fib to arrive. int wait; // Set to true when thread is in WaitForSingleObject unsigned long count; // total number of FIBs on FibList struct list_head fib_list; // this holds fibs and their attachd hw_fibs @@ -789,7 +789,7 @@ * This is the event the sendfib routine will wait on if the * caller did not pass one and this is synch io. */ - struct semaphore event_wait; + struct compat_semaphore event_wait; spinlock_t event_lock; u32 done; /* gets set to 1 when fib is complete */ diff -urN linux-2.6.26/drivers/scsi/aic7xxx/.gitignore linux-2.6.26-lab126/drivers/scsi/aic7xxx/.gitignore --- linux-2.6.26/drivers/scsi/aic7xxx/.gitignore 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/scsi/aic7xxx/.gitignore 1969-12-31 19:00:00.000000000 -0500 @@ -1,6 +0,0 @@ -aic79xx_reg.h -aic79xx_reg_print.c -aic79xx_seq.h -aic7xxx_reg.h -aic7xxx_reg_print.c -aic7xxx_seq.h diff -urN linux-2.6.26/drivers/serial/8250.c linux-2.6.26-lab126/drivers/serial/8250.c --- linux-2.6.26/drivers/serial/8250.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/serial/8250.c 2010-08-10 04:15:30.000000000 -0400 @@ -849,6 +849,10 @@ * Check for presence of the EFR when DLAB is set. * Only ST16C650V1 UARTs pass this test. */ +#ifndef CONFIG_ARCH_MXC + /* This test fails as EFR reads 0, but our uart requires LCR=0xBF + * to access EFR. + */ serial_outp(up, UART_LCR, UART_LCR_DLAB); if (serial_in(up, UART_EFR) == 0) { serial_outp(up, UART_EFR, 0xA8); @@ -862,6 +866,7 @@ serial_outp(up, UART_EFR, 0); return; } +#endif /* * Maybe it requires 0xbf to be written to the LCR. @@ -1373,7 +1378,12 @@ count = up->tx_loadsz; do { +#ifdef CONFIG_ARCH_MXC + /* Seems like back-to-back accesses are a problem */ + serial_out_sync(up, UART_TX, xmit->buf[xmit->tail]); +#else serial_out(up, UART_TX, xmit->buf[xmit->tail]); +#endif xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); up->port.icount.tx++; if (uart_circ_empty(xmit)) @@ -1454,7 +1464,10 @@ { struct irq_info *i = dev_id; struct list_head *l, *end = NULL; - int pass_counter = 0, handled = 0; +#ifndef CONFIG_PREEMPT_RT + int pass_counter = 0; +#endif + int handled = 0; DEBUG_INTR("serial8250_interrupt(%d)...", irq); @@ -1492,12 +1505,18 @@ l = l->next; + /* + * On preempt-rt we can be preempted and run in our + * own thread. + */ +#ifndef CONFIG_PREEMPT_RT if (l == i->head && pass_counter++ > PASS_LIMIT) { /* If we hit this, we're dead. */ printk(KERN_ERR "serial8250: too much work for " "irq%d\n", irq); break; } +#endif } while (l != end); spin_unlock(&i->lock); @@ -2536,14 +2555,10 @@ touch_nmi_watchdog(); - local_irq_save(flags); - if (up->port.sysrq) { - /* serial8250_handle_port() already took the lock */ - locked = 0; - } else if (oops_in_progress) { - locked = spin_trylock(&up->port.lock); - } else - spin_lock(&up->port.lock); + if (up->port.sysrq || oops_in_progress) + locked = spin_trylock_irqsave(&up->port.lock, flags); + else + spin_lock_irqsave(&up->port.lock, flags); /* * First save the IER then disable the interrupts @@ -2575,8 +2590,7 @@ check_modem_status(up); if (locked) - spin_unlock(&up->port.lock); - local_irq_restore(flags); + spin_unlock_irqrestore(&up->port.lock, flags); } static int __init serial8250_console_setup(struct console *co, char *options) diff -urN linux-2.6.26/drivers/serial/Kconfig linux-2.6.26-lab126/drivers/serial/Kconfig --- linux-2.6.26/drivers/serial/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/serial/Kconfig 2010-08-10 04:15:30.000000000 -0400 @@ -307,6 +307,31 @@ your boot loader (lilo or loadlin) about how to pass options to the kernel at boot time.) +config SERIAL_MXC + tristate "MXC Internal serial port support" + depends on ARCH_MXC + select SERIAL_CORE + help + This selects the Freescale Semiconductor MXC Internal UART driver. + If unsure, say N. + +config SERIAL_MXC_CONSOLE + bool "Support for console on a MXC/MX27/MX21 Internal serial port" + depends on SERIAL_MXC=y + select SERIAL_CORE_CONSOLE + help + Say Y here if you wish to use an MXC Internal UART as the system + console (the system console is the device which receives all kernel + messages and warnings and which allows logins in single user mode). + + Even if you say Y here, the currently visible framebuffer console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttymxc". (Try "man bootparam" or see the documentation of + your boot loader (lilo or loadlin) about how to pass options to the + kernel at boot time.) + + config SERIAL_AMBA_PL011 tristate "ARM AMBA PL011 serial port support" depends on ARM_AMBA diff -urN linux-2.6.26/drivers/serial/Makefile linux-2.6.26-lab126/drivers/serial/Makefile --- linux-2.6.26/drivers/serial/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/serial/Makefile 2010-08-10 04:15:30.000000000 -0400 @@ -64,6 +64,8 @@ obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o obj-$(CONFIG_SERIAL_NETX) += netx-serial.o +obj-$(CONFIG_SERIAL_MXC) += mxc_uart.o +obj-$(CONFIG_SERIAL_MXC_CONSOLE) += mxc_uart_early.o obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o diff -urN linux-2.6.26/drivers/serial/mcfserial.c linux-2.6.26-lab126/drivers/serial/mcfserial.c --- linux-2.6.26/drivers/serial/mcfserial.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/serial/mcfserial.c 2010-08-10 04:15:30.000000000 -0400 @@ -65,7 +65,8 @@ #define CONSOLE_BAUD_RATE 115200 #define DEFAULT_CBAUD B115200 #elif defined(CONFIG_ARNEWSH) || defined(CONFIG_FREESCALE) || \ - defined(CONFIG_senTec) || defined(CONFIG_SNEHA) || defined(CONFIG_AVNET) + defined(CONFIG_senTec) || defined(CONFIG_SNEHA) || defined(CONFIG_AVNET) || \ + defined(CONFIG_SAVANT) #define CONSOLE_BAUD_RATE 19200 #define DEFAULT_CBAUD B19200 #endif @@ -324,7 +325,7 @@ * ----------------------------------------------------------------------- */ -static inline void receive_chars(struct mcf_serial *info) +static noinline void receive_chars(struct mcf_serial *info) { volatile unsigned char *uartp; struct tty_struct *tty = info->tty; @@ -369,7 +370,7 @@ return; } -static inline void transmit_chars(struct mcf_serial *info) +static noinline void transmit_chars(struct mcf_serial *info) { volatile unsigned char *uartp; @@ -1479,14 +1480,28 @@ /* * Based on the line number set up the internal interrupt stuff. */ -static void mcfrs_irqinit(struct mcf_serial *info) +static int __init mcfrs_irqinit(struct mcf_serial *info) { + volatile unsigned char *uartp; + int ret; + + uartp = info->addr; + /* Clear mask, so no surprise interrupts. */ + uartp[MCFUART_UIMR] = 0; + + ret = request_irq(info->irq, mcfrs_interrupt, IRQF_DISABLED, + "ColdFire UART", NULL); + if (ret) { + printk("MCFRS: Unable to attach ColdFire UART %d interrupt " + "vector=%d, error: %d\n", info->line, + info->irq, ret); + return ret; + } + #if defined(CONFIG_M5272) volatile unsigned long *icrp; volatile unsigned long *portp; - volatile unsigned char *uartp; - uartp = info->addr; icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR2); switch (info->line) { @@ -1508,11 +1523,10 @@ portp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_PDCNT); *portp = (*portp & ~0x000003fc) | 0x000002a8; #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) - volatile unsigned char *icrp, *uartp; +#if !defined(CONFIG_M523x) + volatile unsigned char *icrp; volatile unsigned long *imrp; - uartp = info->addr; - icrp = (volatile unsigned char *) (MCF_MBAR + MCFICM_INTC0 + MCFINTC_ICR0 + MCFINT_UART0 + info->line); *icrp = 0x30 + info->line; /* level 6, line based priority */ @@ -1520,6 +1534,14 @@ imrp = (volatile unsigned long *) (MCF_MBAR + MCFICM_INTC0 + MCFINTC_IMRL); *imrp &= ~((1 << (info->irq - MCFINT_VECBASE)) | 1); +#endif +#if defined(CONFIG_M523x) + { + volatile unsigned short *par_uartp; + par_uartp = (volatile unsigned short *) (MCF_MBAR + MCF523x_GPIO_PAR_UART); + *par_uartp = 0x3FFF; /* setup GPIO for UART0, UART1 & UART2 */ + } +#endif #if defined(CONFIG_M527x) { /* @@ -1544,37 +1566,38 @@ } #endif #elif defined(CONFIG_M520x) - volatile unsigned char *icrp, *uartp; - volatile unsigned long *imrp; - - uartp = info->addr; - - icrp = (volatile unsigned char *) (MCF_MBAR + MCFICM_INTC0 + - MCFINTC_ICR0 + MCFINT_UART0 + info->line); - *icrp = 0x03; + { + volatile unsigned char *icrp; + volatile unsigned long *imrp; - imrp = (volatile unsigned long *) (MCF_MBAR + MCFICM_INTC0 + - MCFINTC_IMRL); - *imrp &= ~((1 << (info->irq - MCFINT_VECBASE)) | 1); - if (info->line < 2) { - unsigned short *uart_par; - uart_par = (unsigned short *)(MCF_IPSBAR + MCF_GPIO_PAR_UART); - if (info->line == 0) - *uart_par |= MCF_GPIO_PAR_UART_PAR_UTXD0 - | MCF_GPIO_PAR_UART_PAR_URXD0; - else if (info->line == 1) - *uart_par |= MCF_GPIO_PAR_UART_PAR_UTXD1 - | MCF_GPIO_PAR_UART_PAR_URXD1; + icrp = (volatile unsigned char *) (MCF_MBAR + MCFICM_INTC0 + + MCFINTC_ICR0 + MCFINT_UART0 + info->line); + *icrp = 0x03; + + imrp = (volatile unsigned long *) (MCF_MBAR + MCFICM_INTC0 + + MCFINTC_IMRL); + *imrp &= ~((1 << (info->irq - MCFINT_VECBASE)) | 1); + if (info->line < 2) { + unsigned short *uart_par; + uart_par = (unsigned short *)(MCF_IPSBAR + + MCF_GPIO_PAR_UART); + if (info->line == 0) + *uart_par |= MCF_GPIO_PAR_UART_PAR_UTXD0 + | MCF_GPIO_PAR_UART_PAR_URXD0; + else if (info->line == 1) + *uart_par |= MCF_GPIO_PAR_UART_PAR_UTXD1 + | MCF_GPIO_PAR_UART_PAR_URXD1; } else if (info->line == 2) { unsigned char *feci2c_par; - feci2c_par = (unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C); + feci2c_par = (unsigned char *)(MCF_IPSBAR + + MCF_GPIO_PAR_FECI2C); *feci2c_par &= ~0x0F; *feci2c_par |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 - | MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2; + | MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2; } + } #elif defined(CONFIG_M532x) - volatile unsigned char *uartp; - uartp = info->addr; + switch (info->line) { case 0: MCF_INTC0_ICR26 = 0x3; @@ -1595,7 +1618,6 @@ break; } #else - volatile unsigned char *icrp, *uartp; switch (info->line) { case 0: @@ -1613,23 +1635,12 @@ default: printk("MCFRS: don't know how to handle UART %d interrupt?\n", info->line); - return; + return -ENODEV; } - uartp = info->addr; uartp[MCFUART_UIVR] = info->irq; #endif - - /* Clear mask, so no surprise interrupts. */ - uartp[MCFUART_UIMR] = 0; - - if (request_irq(info->irq, mcfrs_interrupt, IRQF_DISABLED, - "ColdFire UART", NULL)) { - printk("MCFRS: Unable to attach ColdFire UART %d interrupt " - "vector=%d\n", info->line, info->irq); - } - - return; + return 0; } @@ -1719,7 +1730,6 @@ mcfrs_init(void) { struct mcf_serial *info; - unsigned long flags; int i; /* Setup base handler, and timer table. */ @@ -1759,12 +1769,12 @@ return(-EBUSY); } - local_irq_save(flags); - /* * Configure all the attached serial ports. */ for (i = 0, info = mcfrs_table; (i < NR_PORTS); i++, info++) { + int ret; + info->magic = SERIAL_MAGIC; info->line = i; info->tty = 0; @@ -1782,14 +1792,11 @@ info->imr = 0; mcfrs_setsignals(info, 0, 0); - mcfrs_irqinit(info); - - printk("ttyS%d at 0x%04x (irq = %d)", info->line, - (unsigned int) info->addr, info->irq); - printk(" is a builtin ColdFire UART\n"); + ret = mcfrs_irqinit(info); + if (!ret) + printk("ttyS%d at 0x%p (irq = %d) is a builtin " + "ColdFire UART\n", info->line, info->addr, info->irq); } - - local_irq_restore(flags); return 0; } diff -urN linux-2.6.26/drivers/serial/mxc_uart.c linux-2.6.26-lab126/drivers/serial/mxc_uart.c --- linux-2.6.26/drivers/serial/mxc_uart.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/serial/mxc_uart.c 2010-08-10 04:15:30.000000000 -0400 @@ -0,0 +1,2078 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2009 Amazon Technologies, Inc. All Rights Reserved. + * Manish Lachwani (lachwani@lab126.com) + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file drivers/serial/mxc_uart.c + * + * @brief Driver for the Freescale Semiconductor MXC serial ports based on + * drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. + * + * @ingroup UART + */ + +/* + * Include Files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_SERIAL_MXC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif +#define SERIAL_MXC_MAJOR 207 +#define SERIAL_MXC_MINOR 16 +#define MXC_ISR_PASS_LIMIT 256 +#define UART_CREAD_BIT 256 + +#define MXC_UART_IDLE_START 30000 /* Start off with a 30 second workqueue */ +#define MXC_UART_IDLE_THRESH 10000 /* Monitor UART activity every 10 seconds */ + +/* IRDA minimum pulse duration in micro seconds */ +#define MIN_PULSE_DUR 2 +/* + * Transmit DMA buffer size is set to 1024 bytes, this is limited + * by UART_XMIT_SIZE. + */ +#define TXDMA_BUFF_SIZE UART_XMIT_SIZE +/* + * Receive DMA sub-buffer size + */ +#define RXDMA_BUFF_SIZE 128 + +static int last_interrupt_count = 0; +static int new_interrupt_count = 0; + +static void mxcuart_low_power(struct work_struct *work); +static DECLARE_DELAYED_WORK(mxc_lp_work, mxcuart_low_power); +static int mxc_uart_clock_gate = 0; /* 1: Gate the uart_clk, 0: Do not gate */ + +/*! + * This structure is used to store the information for DMA data transfer. + */ +typedef struct { + /*! + * Holds the read channel number. + */ + int rd_channel; + /*! + * Holds the write channel number. + */ + int wr_channel; + /*! + * UART Transmit Event ID + */ + int tx_event_id; + /*! + * UART Receive Event ID + */ + int rx_event_id; + /*! + * DMA Transmit tasklet + */ + struct tasklet_struct dma_tx_tasklet; + /*! + * Flag indicates if the channel is in use + */ + int dma_txchnl_inuse; +} dma_info; + +/*! + * This is used to indicate if we want echo cancellation in the Irda mode. + */ +static int echo_cancel; +extern void gpio_uart_active(int port, int no_irda); +extern void gpio_uart_inactive(int port, int no_irda); +extern void config_uartdma_event(int port); + +static uart_mxc_port *mxc_ports[MXC_UART_NR]; + +/*! + * Function to enable the uart_clk + * + * Deal with only the port #0 for now since the Luigi boards support + * one UART only. + */ +void mxcuart_enable_clk(void) +{ + uart_mxc_port *umxc = mxc_ports[0]; + + /* Don't let the workqueue disable the clock immediately */ + new_interrupt_count++; + + if (clk_get_usecount(umxc->clk) == 0) + clk_enable(umxc->clk); +} +EXPORT_SYMBOL(mxcuart_enable_clk); + +/*! + * This array holds the DMA channel information for each MXC UART + */ +static dma_info dma_list[MXC_UART_NR]; + +static void mxcuart_low_power(struct work_struct *work) +{ + uart_mxc_port *umxc = mxc_ports[0]; + + if (last_interrupt_count == new_interrupt_count) { + if (clk_get_usecount(umxc->clk) && mxc_uart_clock_gate) + clk_disable(umxc->clk); + } + else + last_interrupt_count = new_interrupt_count; + + if (mxc_uart_clock_gate) + schedule_delayed_work(&mxc_lp_work, msecs_to_jiffies(MXC_UART_IDLE_THRESH)); +} + +/* Enable/disable the uart_clk gating */ +static ssize_t +show_uart_clk_state(struct device *_dev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", mxc_uart_clock_gate); +} + +static ssize_t +store_uart_clk_state(struct device *_dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int value; + + if (sscanf(buf, "%d", &value) > 0) { + if ( (value > 0) && !mxc_uart_clock_gate) { + schedule_delayed_work(&mxc_lp_work, msecs_to_jiffies(MXC_UART_IDLE_THRESH)); + mxc_uart_clock_gate = 1; + } + + if ( (value <= 0) && mxc_uart_clock_gate) { + mxc_uart_clock_gate = 0; + cancel_rearming_delayed_work(&mxc_lp_work); + } + + return strlen(buf); + } + + return -EINVAL; +} + +static DEVICE_ATTR(uart_clk_state, S_IRUGO|S_IWUSR, show_uart_clk_state, store_uart_clk_state); + +/* + * This function is called by the core driver to stop UART transmission. + * This might be due to the TTY layer indicating that the user wants to stop + * transmission. + * + * @param port the port structure for the UART passed in by the core + * driver + */ +static void mxcuart_stop_tx(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + volatile unsigned int cr1; + + cr1 = readl(port->membase + MXC_UARTUCR1); + /* Disable Transmitter rdy interrupt */ + if (umxc->dma_enabled == 1) { + cr1 &= ~MXC_UARTUCR1_TXDMAEN; + } else { + cr1 &= ~MXC_UARTUCR1_TRDYEN; + } + writel(cr1, port->membase + MXC_UARTUCR1); +} + +/*! + * DMA Transmit tasklet method is scheduled on completion of a DMA transmit + * to send out any more data that is available in the UART xmit buffer. + * + * @param arg driver private data + */ +static void dma_tx_do_tasklet(unsigned long arg) +{ + uart_mxc_port *umxc = (uart_mxc_port *) arg; + struct circ_buf *xmit = &umxc->port.info->xmit; + mxc_dma_requestbuf_t writechnl_request; + int tx_num; + unsigned long flags; + + spin_lock_irqsave(&umxc->port.lock, flags); + tx_num = uart_circ_chars_pending(xmit); + if (tx_num > 0) { + if (xmit->tail > xmit->head) { + memcpy(umxc->tx_buf, xmit->buf + xmit->tail, + UART_XMIT_SIZE - xmit->tail); + memcpy(umxc->tx_buf + (UART_XMIT_SIZE - xmit->tail), + xmit->buf, xmit->head); + } else { + memcpy(umxc->tx_buf, xmit->buf + xmit->tail, tx_num); + } + umxc->tx_handle = dma_map_single(umxc->port.dev, umxc->tx_buf, + TXDMA_BUFF_SIZE, + DMA_TO_DEVICE); + + writechnl_request.dst_addr = umxc->port.mapbase + MXC_UARTUTXD; + writechnl_request.src_addr = umxc->tx_handle; + writechnl_request.num_of_bytes = tx_num; + + if ((mxc_dma_config(dma_list[umxc->port.line].wr_channel, + &writechnl_request, 1, + MXC_DMA_MODE_WRITE)) == 0) { + mxc_dma_enable(dma_list[umxc->port.line].wr_channel); + } + } else { + /* No more data available in the xmit queue, clear the flag */ + dma_list[umxc->port.line].dma_txchnl_inuse = 0; + } + spin_unlock_irqrestore(&umxc->port.lock, flags); +} + +/*! + * DMA Write callback is called by the SDMA controller after it has sent out all + * the data from the user buffer. This function updates the xmit buffer pointers. + * + * @param arg driver private data + * @param error any DMA error + * @param count amount of data that was transferred + */ +static void mxcuart_dma_writecallback(void *arg, int error, unsigned int count) +{ + uart_mxc_port *umxc = arg; + struct circ_buf *xmit = &umxc->port.info->xmit; + int tx_num; + + if (error != MXC_DMA_TRANSFER_ERROR) { + tx_num = count; + umxc->port.icount.tx += tx_num; + xmit->tail = (xmit->tail + tx_num) & (UART_XMIT_SIZE - 1); + } + + dma_unmap_single(umxc->port.dev, umxc->tx_handle, TXDMA_BUFF_SIZE, + DMA_TO_DEVICE); + tx_num = uart_circ_chars_pending(xmit); + /* Schedule a tasklet to send out the pending characters */ + if (tx_num > 0) { + tasklet_schedule(&dma_list[umxc->port.line].dma_tx_tasklet); + } else { + dma_list[umxc->port.line].dma_txchnl_inuse = 0; + } + if (tx_num < WAKEUP_CHARS) { + uart_write_wakeup(&umxc->port); + } +} + +/*! + * This function is called by the core driver to start transmitting characters. + * This function enables the transmit interrupts. + * + * @param port the port structure for the UART passed in by the core + * driver + */ +static void mxcuart_start_tx(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + struct circ_buf *xmit = &umxc->port.info->xmit; + volatile unsigned int cr1; + mxc_dma_requestbuf_t writechnl_request; + int tx_num; + + mxcuart_enable_clk(); + + cr1 = readl(port->membase + MXC_UARTUCR1); + /* Enable Transmitter rdy interrupt */ + if (umxc->dma_enabled == 1) { + /* + * If the channel is in use then return immediately and use + * the dma_tx tasklet to transfer queued data when current DMA + * transfer is complete + */ + if (dma_list[umxc->port.line].dma_txchnl_inuse == 1) { + return; + } + tx_num = uart_circ_chars_pending(xmit); + if (tx_num > 0) { + dma_list[umxc->port.line].dma_txchnl_inuse = 1; + if (xmit->tail > xmit->head) { + memcpy(umxc->tx_buf, xmit->buf + xmit->tail, + UART_XMIT_SIZE - xmit->tail); + memcpy(umxc->tx_buf + + (UART_XMIT_SIZE - xmit->tail), xmit->buf, + xmit->head); + } else { + memcpy(umxc->tx_buf, xmit->buf + xmit->tail, + tx_num); + } + umxc->tx_handle = + dma_map_single(umxc->port.dev, umxc->tx_buf, + TXDMA_BUFF_SIZE, DMA_TO_DEVICE); + + writechnl_request.dst_addr = + umxc->port.mapbase + MXC_UARTUTXD; + writechnl_request.src_addr = umxc->tx_handle; + writechnl_request.num_of_bytes = tx_num; + if ((mxc_dma_config + (dma_list[umxc->port.line].wr_channel, + &writechnl_request, 1, + MXC_DMA_MODE_WRITE)) == 0) { + mxc_dma_enable(dma_list[umxc->port.line]. + wr_channel); + } + cr1 |= MXC_UARTUCR1_TXDMAEN; + } + } else { + cr1 |= MXC_UARTUCR1_TRDYEN; + } + writel(cr1, port->membase + MXC_UARTUCR1); +} + +/*! + * This function is called by the core driver to stop receiving characters; the + * port is in the process of being closed. + * + * @param port the port structure for the UART passed in by the core driver + */ +static void mxcuart_stop_rx(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + volatile unsigned int cr1; + + cr1 = readl(port->membase + MXC_UARTUCR1); + if (umxc->dma_enabled == 1) { + cr1 &= ~MXC_UARTUCR1_RXDMAEN; + } else { + cr1 &= ~MXC_UARTUCR1_RRDYEN; + } + writel(cr1, port->membase + MXC_UARTUCR1); +} + +/*! + * This function is called by the core driver to enable the modem status + * interrupts. If the port is configured to be in DTE mode then it enables the + * DCDDELT and RIDELT interrupts in addition to the DTRDEN interrupt. The RTSDEN + * interrupt is enabled only for interrupt-driven hardware flow control. + * + * @param port the port structure for the UART passed in by the core driver + */ +static void mxcuart_enable_ms(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + volatile unsigned int cr1, cr3; + + /* + * RTS interrupt is enabled only if we are using interrupt-driven + * software controlled hardware flow control + */ + if (umxc->hardware_flow == 0) { + cr1 = readl(umxc->port.membase + MXC_UARTUCR1); + cr1 |= MXC_UARTUCR1_RTSDEN; + writel(cr1, umxc->port.membase + MXC_UARTUCR1); + } + cr3 = readl(umxc->port.membase + MXC_UARTUCR3); + cr3 |= MXC_UARTUCR3_DTRDEN; + if (umxc->mode == MODE_DTE) { + cr3 |= MXC_UARTUCR3_DCD | MXC_UARTUCR3_RI; + } + writel(cr3, umxc->port.membase + MXC_UARTUCR3); +} + +/*! + * This function is called from the interrupt service routine if the status bit + * indicates that the receive fifo data level is above the set threshold. The + * function reads the character and queues them into the TTY layers read + * buffer. The function also looks for break characters, parity and framing + * errors in the received character and sets the appropriate flag in the TTY + * receive buffer. + * + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + */ +static void mxcuart_rx_chars(uart_mxc_port * umxc) +{ + struct tty_struct *tty = umxc->port.info->tty; + volatile unsigned int ch, sr2; + unsigned int status, flag, max_count = 256; + + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + while (((sr2 & MXC_UARTUSR2_RDR) == 1) && (max_count-- > 0)) { + ch = readl(umxc->port.membase + MXC_UARTURXD); + + flag = TTY_NORMAL; + status = ch | UART_CREAD_BIT; + ch &= 0xFF; /* Clear the upper bits */ + umxc->port.icount.rx++; + + /* + * Check to see if there is an error in the received + * character. Perform the appropriate actions based on the + * error bit that was set. + */ + if (status & MXC_UARTURXD_ERR) { + if (status & MXC_UARTURXD_BRK) { + /* + * Clear the frame and parity error bits + * as these always get set on receiving a + * break character + */ + status &= ~(MXC_UARTURXD_FRMERR | + MXC_UARTURXD_PRERR); + umxc->port.icount.brk++; + if (uart_handle_break(&umxc->port)) { + goto ignore_char; + } + } else if (status & MXC_UARTURXD_FRMERR) { + umxc->port.icount.frame++; + } else if (status & MXC_UARTURXD_PRERR) { + umxc->port.icount.parity++; + } + if (status & MXC_UARTURXD_OVRRUN) { + umxc->port.icount.overrun++; + } + + status &= umxc->port.read_status_mask; + + if (status & MXC_UARTURXD_BRK) { + flag = TTY_BREAK; + } else if (status & MXC_UARTURXD_FRMERR) { + flag = TTY_FRAME; + } else if (status & MXC_UARTURXD_PRERR) { + flag = TTY_PARITY; + } + } + + if (uart_handle_sysrq_char(&umxc->port, ch)) { + goto ignore_char; + } + + uart_insert_char(&umxc->port, status, MXC_UARTURXD_OVRRUN, ch, + flag); + ignore_char: + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + } + tty_flip_buffer_push(tty); +} + +/*! + * This function is called from the interrupt service routine if the status bit + * indicates that the transmit fifo is emptied below its set threshold and + * requires data. The function pulls characters from the TTY layers write + * buffer and writes it out to the UART transmit fifo. + * + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + */ +static void mxcuart_tx_chars(uart_mxc_port * umxc) +{ + struct circ_buf *xmit = &umxc->port.info->xmit; + int count; + + /* + * Transmit the XON/XOFF character if required + */ + if (umxc->port.x_char) { + writel(umxc->port.x_char, umxc->port.membase + MXC_UARTUTXD); + umxc->port.icount.tx++; + umxc->port.x_char = 0; + return; + } + + /* + * Check to see if there is any data to be sent and that the + * port has not been currently stopped by anything. + */ + if (uart_circ_empty(xmit) || uart_tx_stopped(&umxc->port)) { + mxcuart_stop_tx(&umxc->port); + return; + } + + count = umxc->port.fifosize - umxc->tx_threshold; + do { + writel(xmit->buf[xmit->tail], + umxc->port.membase + MXC_UARTUTXD); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + umxc->port.icount.tx++; + if (uart_circ_empty(xmit)) { + break; + } + } while (--count > 0); + + /* + * Check to see if we have flushed enough characters to ask for more + * to be sent to us, if so, we notify the user space that we can + * accept more data + */ + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) { + uart_write_wakeup(&umxc->port); + } + + if (uart_circ_empty(xmit)) { + mxcuart_stop_tx(&umxc->port); + } +} + +/*! + * This function is called from the interrupt service routine if there is a + * change in the modem signals. This function handles these signal changes and + * also clears the appropriate status register bits. + * + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + * @param sr1 contents of status register 1 + * @param sr2 contents of status register 2 + */ +static void mxcuart_modem_status(uart_mxc_port * umxc, unsigned int sr1, + unsigned int sr2) +{ + if (umxc->mode == MODE_DTE) { + if (sr2 & MXC_UARTUSR2_DCDDELT) { + uart_handle_dcd_change(&umxc->port, + !(sr2 & MXC_UARTUSR2_DCDIN)); + } + if (sr2 & MXC_UARTUSR2_RIDELT) { + umxc->port.icount.rng++; + } + } + if (sr1 & MXC_UARTUSR1_DTRD) { + umxc->port.icount.dsr++; + } + if ((umxc->hardware_flow == 0) && (sr1 & MXC_UARTUSR1_RTSD)) { + uart_handle_cts_change(&umxc->port, sr1 & MXC_UARTUSR1_RTSS); + } + + wake_up_interruptible(&umxc->port.info->delta_msr_wait); +} + +/*! + * Interrupt service routine registered to handle the muxed ANDed interrupts. + * This routine is registered only in the case where the UART interrupts are + * muxed. + * + * @param irq the interrupt number + * @param dev_id driver private data + * + * @return The function returns \b IRQ_RETVAL(1) if interrupt was handled, + * returns \b IRQ_RETVAL(0) if the interrupt was not handled. + * \b IRQ_RETVAL is defined in \b include/linux/interrupt.h. + */ +static irqreturn_t mxcuart_int(int irq, void *dev_id) +{ + uart_mxc_port *umxc = dev_id; + volatile unsigned int sr1, sr2, cr1, cr; + unsigned int pass_counter = MXC_ISR_PASS_LIMIT; + unsigned int term_cond = 0; + int handled = 0; + + mxcuart_enable_clk(); + + sr1 = readl(umxc->port.membase + MXC_UARTUSR1); + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + cr1 = readl(umxc->port.membase + MXC_UARTUCR1); + + do { + /* Clear the bits that triggered the interrupt */ + writel(sr1, umxc->port.membase + MXC_UARTUSR1); + writel(sr2, umxc->port.membase + MXC_UARTUSR2); + /* + * Read if there is data available + */ + if (sr2 & MXC_UARTUSR2_RDR) { + mxcuart_rx_chars(umxc); + } + + if ((sr1 & (MXC_UARTUSR1_RTSD | MXC_UARTUSR1_DTRD)) || + (sr2 & (MXC_UARTUSR2_DCDDELT | MXC_UARTUSR2_RIDELT))) { + mxcuart_modem_status(umxc, sr1, sr2); + } + + /* + * Send data if there is data to be sent + */ + if ((cr1 & MXC_UARTUCR1_TRDYEN) && (sr1 & MXC_UARTUSR1_TRDY)) { + /* Echo cancellation for IRDA Transmit chars */ + if (umxc->ir_mode == IRDA && echo_cancel) { + /* Disable the receiver */ + cr = readl(umxc->port.membase + MXC_UARTUCR2); + cr &= ~MXC_UARTUCR2_RXEN; + writel(cr, umxc->port.membase + MXC_UARTUCR2); + /* Enable Transmit complete intr to reenable RX */ + cr = readl(umxc->port.membase + MXC_UARTUCR4); + cr |= MXC_UARTUCR4_TCEN; + writel(cr, umxc->port.membase + MXC_UARTUCR4); + } + mxcuart_tx_chars(umxc); + } + + if (pass_counter-- == 0) { + break; + } + + sr1 = readl(umxc->port.membase + MXC_UARTUSR1); + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + + /* Is the transmit complete to reenable the receiver? */ + if (umxc->ir_mode == IRDA && echo_cancel) { + if (sr2 & MXC_UARTUSR2_TXDC) { + cr = readl(umxc->port.membase + MXC_UARTUCR2); + cr |= MXC_UARTUCR2_RXEN; + writel(cr, umxc->port.membase + MXC_UARTUCR2); + /* Disable the Transmit complete interrupt bit */ + cr = readl(umxc->port.membase + MXC_UARTUCR4); + cr &= ~MXC_UARTUCR4_TCEN; + writel(cr, umxc->port.membase + MXC_UARTUCR4); + } + } + + /* + * If there is no data to send or receive and if there is no + * change in the modem status signals then quit the routine + */ + term_cond = sr1 & (MXC_UARTUSR1_RTSD | MXC_UARTUSR1_DTRD); + term_cond |= sr2 & (MXC_UARTUSR2_RDR | MXC_UARTUSR2_DCDDELT); + term_cond |= !(sr2 & MXC_UARTUSR2_TXFE); + } while (term_cond > 0); + + handled = 1; + return IRQ_RETVAL(handled); +} + +/*! + * Interrupt service routine registered to handle the transmit interrupts. This + * routine is registered only in the case where the UART interrupts are not + * muxed. + * + * @param irq the interrupt number + * @param dev_id driver private data + * + * @return The function returns \b IRQ_RETVAL(1) if interrupt was handled, + * returns \b IRQ_RETVAL(0) if the interrupt was not handled. + * \b IRQ_RETVAL is defined in include/linux/interrupt.h. + */ +static irqreturn_t mxcuart_tx_int(int irq, void *dev_id) +{ + uart_mxc_port *umxc = dev_id; + int handled = 0; + volatile unsigned int sr2, cr; + + /* Echo cancellation for IRDA Transmit chars */ + if (umxc->ir_mode == IRDA && echo_cancel) { + /* Disable the receiver */ + cr = readl(umxc->port.membase + MXC_UARTUCR2); + cr &= ~MXC_UARTUCR2_RXEN; + writel(cr, umxc->port.membase + MXC_UARTUCR2); + /* Enable Transmit complete to reenable receiver */ + cr = readl(umxc->port.membase + MXC_UARTUCR4); + cr |= MXC_UARTUCR4_TCEN; + writel(cr, umxc->port.membase + MXC_UARTUCR4); + } + + mxcuart_tx_chars(umxc); + + /* Is the transmit complete to reenable the receiver? */ + if (umxc->ir_mode == IRDA && echo_cancel) { + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + if (sr2 & MXC_UARTUSR2_TXDC) { + cr = readl(umxc->port.membase + MXC_UARTUCR2); + cr |= MXC_UARTUCR2_RXEN; + writel(cr, umxc->port.membase + MXC_UARTUCR2); + /* Disable the Transmit complete interrupt bit */ + cr = readl(umxc->port.membase + MXC_UARTUCR4); + cr &= ~MXC_UARTUCR4_TCEN; + writel(cr, umxc->port.membase + MXC_UARTUCR4); + } + } + + handled = 1; + + return IRQ_RETVAL(handled); +} + +/*! + * Interrupt service routine registered to handle the receive interrupts. This + * routine is registered only in the case where the UART interrupts are not + * muxed. + * + * @param irq the interrupt number + * @param dev_id driver private data + * + * @return The function returns \b IRQ_RETVAL(1) if interrupt was handled, + * returns \b IRQ_RETVAL(0) if the interrupt was not handled. + * \b IRQ_RETVAL is defined in include/linux/interrupt.h. + */ +static irqreturn_t mxcuart_rx_int(int irq, void *dev_id) +{ + uart_mxc_port *umxc = dev_id; + int handled = 0; + + /* Clear the aging timer bit */ + writel(MXC_UARTUSR1_AGTIM, umxc->port.membase + MXC_UARTUSR1); + mxcuart_rx_chars(umxc); + handled = 1; + + return IRQ_RETVAL(handled); +} + +/*! + * Interrupt service routine registered to handle the master interrupts. This + * routine is registered only in the case where the UART interrupts are not + * muxed. + * + * @param irq the interrupt number + * @param dev_id driver private data + * + * @return The function returns \b IRQ_RETVAL(1) if interrupt was handled, + * returns \b IRQ_RETVAL(0) if the interrupt was not handled. + * \b IRQ_RETVAL is defined in include/linux/interrupt.h. + */ +static irqreturn_t mxcuart_mint_int(int irq, void *dev_id) +{ + uart_mxc_port *umxc = dev_id; + int handled = 0; + volatile unsigned int sr1, sr2; + + sr1 = readl(umxc->port.membase + MXC_UARTUSR1); + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + /* Clear the modem status interrupt bits */ + writel(MXC_UARTUSR1_RTSD | MXC_UARTUSR1_DTRD, + umxc->port.membase + MXC_UARTUSR1); + writel(MXC_UARTUSR2_DCDDELT | MXC_UARTUSR2_RIDELT, + umxc->port.membase + MXC_UARTUSR2); + mxcuart_modem_status(umxc, sr1, sr2); + handled = 1; + + return IRQ_RETVAL(handled); +} + +/*! + * This function is called by the core driver to test whether the transmitter + * fifo and shift register for the UART port are empty. + * + * @param port the port structure for the UART passed in by the core driver + * + * @return The function returns TIOCSER_TEMT if it is empty, else returns 0. + */ +static unsigned int mxcuart_tx_empty(struct uart_port *port) +{ + volatile unsigned int sr2; + unsigned long flags; + + spin_lock_irqsave(&port->lock, flags); + sr2 = readl(port->membase + MXC_UARTUSR2); + spin_unlock_irqrestore(&port->lock, flags); + + return sr2 & MXC_UARTUSR2_TXDC ? TIOCSER_TEMT : 0; +} + +/*! + * This function is called by the core driver to get the current status of the + * modem input signals. The state of the output signals is not collected. + * + * @param port the port structure for the UART passed in by the core driver + * + * @return The function returns an integer that contains the ORed value of the + * status of all the modem input signals or error. + */ +static unsigned int mxcuart_get_mctrl(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + unsigned int result = 0; + volatile unsigned int sr1, sr2; + + sr1 = readl(umxc->port.membase + MXC_UARTUSR1); + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + + if (sr1 & MXC_UARTUSR1_RTSS) { + result |= TIOCM_CTS; + } + if (umxc->mode == MODE_DTE) { + if (!(sr2 & MXC_UARTUSR2_DCDIN)) { + result |= TIOCM_CAR; + } + if (!(sr2 & MXC_UARTUSR2_RIIN)) { + result |= TIOCM_RI; + } + } + return result; +} + +/*! + * This function is called by the core driver to set the state of the modem + * control lines. + * + * @param port the port structure for the UART passed in by the core driver + * @param mctrl the state that the modem control lines should be changed to + */ +static void mxcuart_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + volatile unsigned int cr2 = 0, cr3 = 0, uts = 0; + + cr2 = readl(port->membase + MXC_UARTUCR2); + cr3 = readl(port->membase + MXC_UARTUCR3); + uts = readl(port->membase + MXC_UARTUTS); + + if (mctrl & TIOCM_RTS) { + /* + * Return to hardware-driven hardware flow control if the + * option is enabled + */ + if (umxc->hardware_flow == 1) { + cr2 |= MXC_UARTUCR2_CTSC; + } else { + cr2 |= MXC_UARTUCR2_CTS; + cr2 &= ~MXC_UARTUCR2_CTSC; + } + } else { + cr2 &= ~(MXC_UARTUCR2_CTS | MXC_UARTUCR2_CTSC); + } + writel(cr2, port->membase + MXC_UARTUCR2); + + if (mctrl & TIOCM_DTR) { + cr3 |= MXC_UARTUCR3_DSR; + } else { + cr3 &= ~MXC_UARTUCR3_DSR; + } + writel(cr3, port->membase + MXC_UARTUCR3); + + if (mctrl & TIOCM_LOOP) { + if (umxc->ir_mode == IRDA) { + echo_cancel = 0; + } else { + uts |= MXC_UARTUTS_LOOP; + } + } else { + if (umxc->ir_mode == IRDA) { + echo_cancel = 1; + } else { + uts &= ~MXC_UARTUTS_LOOP; + } + } + writel(uts, port->membase + MXC_UARTUTS); +} + +/*! + * This function is called by the core driver to control the transmission of + * the break signal. If break_state is non-zero, the break signal is + * transmitted, the signal is terminated when another call is made with + * break_state set to 0. + * + * @param port the port structure for the UART passed in by the core + * driver + * @param break_state the requested state of the break signal + */ +static void mxcuart_break_ctl(struct uart_port *port, int break_state) +{ + volatile unsigned int cr1; + unsigned long flags; + + mxcuart_enable_clk(); + + spin_lock_irqsave(&port->lock, flags); + cr1 = readl(port->membase + MXC_UARTUCR1); + if (break_state == -1) { + cr1 |= MXC_UARTUCR1_SNDBRK; + } else { + cr1 &= ~MXC_UARTUCR1_SNDBRK; + } + writel(cr1, port->membase + MXC_UARTUCR1); + spin_unlock_irqrestore(&port->lock, flags); +} + +#ifdef CONFIG_CONSOLE_POLL +/*! + * Support for KGDB serial + */ +static int mxcuart_get_poll_char(struct uart_port *port) +{ + unsigned int status; + + do { + status = readl(port->membase + MXC_UARTUSR1); + } while ((status & MXC_UARTUSR1_RRDY) == 0); + + return readb(port->membase + MXC_UARTURXD); +} + +static void mxcuart_put_poll_char(struct uart_port *port, unsigned char ch) +{ + unsigned int status; + + do { + status = readl(port->membase + MXC_UARTUSR1); + } while ((status & MXC_UARTUSR1_TRDY) == 0); + + writeb(ch, port->membase + MXC_UARTUTXD); +} +#endif /* CONFIG_CONSOLE_POLL */ + +/*! + * The read DMA callback, this method is called when the DMA buffer has received its + * data. This functions copies the data to the tty buffer and updates the tty buffer + * pointers. It also queues the DMA buffer back to the DMA system. + * + * @param arg driver private data + * @param error any DMA error + * @param cnt amount of data that was transferred + */ +static void mxcuart_dmaread_callback(void *arg, int error, unsigned int cnt) +{ + uart_mxc_port *umxc = arg; + struct tty_struct *tty = umxc->port.info->tty; + int buff_id, flip_cnt, num_bufs; + mxc_dma_requestbuf_t readchnl_request; + mxc_uart_rxdmamap *rx_buf_elem = NULL; + unsigned int sr1, sr2; + char flag; + + num_bufs = umxc->dma_rxbuf_size / RXDMA_BUFF_SIZE; + /* Clear the aging timer bit */ + writel(MXC_UARTUSR1_AGTIM, umxc->port.membase + MXC_UARTUSR1); + + buff_id = umxc->dma_rxbuf_id; + flag = TTY_NORMAL; + + if ((umxc->dma_rxbuf_id += 1) >= num_bufs) { + umxc->dma_rxbuf_id = 0; + } + + rx_buf_elem = (mxc_uart_rxdmamap *) (umxc->rx_dmamap + buff_id); + + if (error == MXC_DMA_TRANSFER_ERROR) { + + sr1 = __raw_readl(umxc->port.membase + MXC_UARTUSR1); + sr2 = __raw_readl(umxc->port.membase + MXC_UARTUSR2); + + if (sr2 & MXC_UARTUSR2_BRCD) { + umxc->port.icount.brk++; + if (uart_handle_break(&umxc->port)) { + goto drop_data; + } + } else if (sr1 & MXC_UARTUSR1_PARITYERR) { + umxc->port.icount.parity++; + } else if (sr1 & MXC_UARTUSR1_FRAMERR) { + umxc->port.icount.frame++; + } else if (sr2 & MXC_UARTUSR2_ORE) { + umxc->port.icount.overrun++; + + } + + if (umxc->port.read_status_mask & MXC_UARTURXD_BRK) { + if (sr2 & MXC_UARTUSR2_BRCD) + flag = TTY_BREAK; + } else if (umxc->port.read_status_mask & MXC_UARTURXD_PRERR) { + if (sr1 & MXC_UARTUSR1_PARITYERR) + flag = TTY_PARITY; + } else if (umxc->port.read_status_mask & MXC_UARTURXD_FRMERR) { + if (sr1 & MXC_UARTUSR1_FRAMERR) + flag = TTY_FRAME; + } else if (umxc->port.read_status_mask & MXC_UARTURXD_OVRRUN) { + if (sr2 & MXC_UARTUSR2_ORE) + flag = TTY_OVERRUN; + } +/* By default clearing all error bits in status reg */ + __raw_writel((MXC_UARTUSR2_BRCD | MXC_UARTUSR2_ORE), + umxc->port.membase + MXC_UARTUSR2); + __raw_writel((MXC_UARTUSR1_PARITYERR | MXC_UARTUSR1_FRAMERR), + umxc->port.membase + MXC_UARTUSR1); + } + + flip_cnt = tty_buffer_request_room(tty, cnt); + + /* Check for space availability in the TTY Flip buffer */ + if (flip_cnt <= 0) { + goto drop_data; + } + umxc->port.icount.rx += flip_cnt; + + tty_insert_flip_string(tty, rx_buf_elem->rx_buf, flip_cnt); + + if (flag != TTY_NORMAL) { + tty_insert_flip_char(tty, 0, flag); + } + + tty_flip_buffer_push(tty); + umxc->port.info->tty->real_raw = 1; + + drop_data: + readchnl_request.src_addr = umxc->port.mapbase; + readchnl_request.dst_addr = rx_buf_elem->rx_handle; + readchnl_request.num_of_bytes = RXDMA_BUFF_SIZE; + mxc_dma_config(dma_list[umxc->port.line].rd_channel, &readchnl_request, + 1, MXC_DMA_MODE_READ); + mxc_dma_enable(dma_list[umxc->port.line].rd_channel); +} + +/*! + * Allocates DMA read and write channels, creates DMA read and write buffers and + * sets the channel specific parameters. + * + * @param d_info the structure that holds all the DMA information for a + * particular MXC UART + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + * + * @return The function returns 0 on success and a non-zero value on failure. + */ +static int mxcuart_initdma(dma_info * d_info, uart_mxc_port * umxc) +{ + int ret = 0, rxbufs, i, j; + mxc_dma_requestbuf_t *readchnl_reqelem; + mxc_uart_rxdmamap *rx_buf_elem; + + /* Request for the read and write channels */ + d_info->rd_channel = mxc_dma_request(umxc->dma_rx_id, "MXC UART Read"); + if (d_info->rd_channel < 0) { + printk(KERN_ERR "MXC UART: Cannot allocate DMA read channel\n"); + return -1; + } else { + d_info->wr_channel = + mxc_dma_request(umxc->dma_tx_id, "MXC UART Write"); + if (d_info->wr_channel < 0) { + mxc_dma_free(d_info->rd_channel); + printk(KERN_ERR + "MXC UART: Cannot allocate DMA write channel\n"); + return -1; + } + } + + /* Allocate the DMA Transmit Buffer */ + if ((umxc->tx_buf = kmalloc(TXDMA_BUFF_SIZE, GFP_KERNEL)) == NULL) { + ret = -1; + goto err_dma_tx_buff; + } + rxbufs = umxc->dma_rxbuf_size / RXDMA_BUFF_SIZE; + /* Allocate the DMA Virtual Receive Buffer */ + if ((umxc->rx_dmamap = kmalloc(rxbufs * sizeof(mxc_uart_rxdmamap), + GFP_KERNEL)) == NULL) { + ret = -1; + goto err_dma_rx_buff; + } + + /* Allocate the DMA Receive Request structures */ + if ((readchnl_reqelem = + kmalloc(rxbufs * sizeof(mxc_dma_requestbuf_t), + GFP_KERNEL)) == NULL) { + ret = -1; + goto err_request; + } + + for (i = 0; i < rxbufs; i++) { + rx_buf_elem = (mxc_uart_rxdmamap *) (umxc->rx_dmamap + i); + rx_buf_elem->rx_buf = + dma_alloc_coherent(NULL, RXDMA_BUFF_SIZE, + &rx_buf_elem->rx_handle, GFP_DMA); + if (rx_buf_elem->rx_buf == NULL) { + for (j = 0; j < i; j++) { + rx_buf_elem = + (mxc_uart_rxdmamap *) (umxc->rx_dmamap + j); + dma_free_coherent(NULL, RXDMA_BUFF_SIZE, + rx_buf_elem->rx_buf, + rx_buf_elem->rx_handle); + } + ret = -1; + goto cleanup; + } + } + + umxc->dma_rxbuf_id = 0; + /* Setup the DMA read request structures */ + for (i = 0; i < rxbufs; i++) { + rx_buf_elem = (mxc_uart_rxdmamap *) (umxc->rx_dmamap + i); + (readchnl_reqelem + i)->src_addr = umxc->port.mapbase; + (readchnl_reqelem + i)->dst_addr = rx_buf_elem->rx_handle; + (readchnl_reqelem + i)->num_of_bytes = RXDMA_BUFF_SIZE; + } + mxc_dma_config(d_info->rd_channel, readchnl_reqelem, rxbufs, + MXC_DMA_MODE_READ); + mxc_dma_callback_set(d_info->rd_channel, mxcuart_dmaread_callback, + umxc); + mxc_dma_callback_set(d_info->wr_channel, mxcuart_dma_writecallback, + umxc); + + /* Start the read channel */ + mxc_dma_enable(d_info->rd_channel); + kfree(readchnl_reqelem); + tasklet_init(&d_info->dma_tx_tasklet, dma_tx_do_tasklet, + (unsigned long)umxc); + d_info->dma_txchnl_inuse = 0; + return ret; + cleanup: + kfree(readchnl_reqelem); + err_request: + kfree(umxc->rx_dmamap); + err_dma_rx_buff: + kfree(umxc->tx_buf); + err_dma_tx_buff: + mxc_dma_free(d_info->rd_channel); + mxc_dma_free(d_info->wr_channel); + + return ret; +} + +/*! + * Stops DMA and frees the DMA resources + * + * @param d_info the structure that holds all the DMA information for a + * particular MXC UART + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + */ +static void mxcuart_freedma(dma_info * d_info, uart_mxc_port * umxc) +{ + int i, rxbufs; + mxc_uart_rxdmamap *rx_buf_elem; + + rxbufs = umxc->dma_rxbuf_size / RXDMA_BUFF_SIZE; + + for (i = 0; i < rxbufs; i++) { + rx_buf_elem = (mxc_uart_rxdmamap *) (umxc->rx_dmamap + i); + dma_free_coherent(NULL, RXDMA_BUFF_SIZE, + rx_buf_elem->rx_buf, rx_buf_elem->rx_handle); + } + kfree(umxc->rx_dmamap); + kfree(umxc->tx_buf); + mxc_dma_free(d_info->rd_channel); + mxc_dma_free(d_info->wr_channel); +} + +/*! + * This function is called to free the interrupts. + * + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + */ +static void mxcuart_free_interrupts(uart_mxc_port * umxc) +{ + free_irq(umxc->port.irq, umxc); + if (umxc->ints_muxed == 0) { + free_irq(umxc->irqs[0], umxc); + free_irq(umxc->irqs[1], umxc); + } +} + +/*! + * Calculate and set the UART port clock value + * + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + * @param per_clk peripheral clock coming into the MXC UART module + * @param req_baud current baudrate requested + * @param div returns the reference frequency divider value + */ +static void mxcuart_set_ref_freq(uart_mxc_port * umxc, unsigned long per_clk, + unsigned int req_baud, int *div) +{ + unsigned int d = 1; + + /* + * Choose the smallest possible prescaler to maximize + * the chance of using integer scaling. Ensure that + * the calculation won't overflow. Limit the denom + * to 15 bits since a 16-bit denom doesn't work. + */ + if (req_baud < (1 << (31 - (4 + 15)))) + d = per_clk / (req_baud << (4 + 15)) + 1; + + umxc->port.uartclk = per_clk / d; + + /* + * Set the ONEMS register that is used by IR special case bit and + * the Escape character detect logic + */ + writel(umxc->port.uartclk / 1000, umxc->port.membase + MXC_UARTONEMS); + *div = d; +} + +/*! + * This function is called by the core driver to initialize the low-level + * driver. The function grabs the interrupt resources and registers its + * interrupt service routines. It then initializes the IOMUX registers to + * configure the pins for UART signals and finally initializes the various + * UART registers and enables the port for reception. + * + * @param port the port structure for the UART passed in by the core driver + * + * @return The function returns 0 on success and a non-zero value on failure. + */ +static int mxcuart_startup(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + int retval; + volatile unsigned int cr, cr1 = 0, cr2 = 0, ufcr = 0; + + /* + * Some UARTs need separate registrations for the interrupts as + * they do not take the muxed interrupt output to the ARM core + */ + if (umxc->ints_muxed == 1) { + retval = request_irq(umxc->port.irq, mxcuart_int, 0, + "mxcintuart", umxc); + if (retval != 0) { + return retval; + } + } else { + retval = request_irq(umxc->port.irq, mxcuart_tx_int, + 0, "mxcintuart", umxc); + if (retval != 0) { + return retval; + } else { + retval = request_irq(umxc->irqs[0], mxcuart_rx_int, + 0, "mxcintuart", umxc); + if (retval != 0) { + free_irq(umxc->port.irq, umxc); + return retval; + } else { + retval = + request_irq(umxc->irqs[1], mxcuart_mint_int, + 0, "mxcintuart", umxc); + if (retval != 0) { + free_irq(umxc->port.irq, umxc); + free_irq(umxc->irqs[0], umxc); + return retval; + } + } + } + } + + /* Initialize the DMA if we need SDMA data transfer */ + if (umxc->dma_enabled == 1) { + retval = mxcuart_initdma(dma_list + umxc->port.line, umxc); + if (retval != 0) { + printk + (KERN_ERR + "MXC UART: Failed to initialize DMA for UART %d\n", + umxc->port.line); + mxcuart_free_interrupts(umxc); + return retval; + } + /* Configure the GPR register to receive SDMA events */ + config_uartdma_event(umxc->port.line); + } + + /* + * Clear Status Registers 1 and 2 + */ + writel(0xFFFF, umxc->port.membase + MXC_UARTUSR1); + writel(0xFFFF, umxc->port.membase + MXC_UARTUSR2); + + /* Configure the IOMUX for the UART */ + gpio_uart_active(umxc->port.line, umxc->ir_mode); + + /* + * Set the transceiver invert bits if required + */ + if (umxc->ir_mode == IRDA) { + echo_cancel = 1; + writel(umxc->ir_rx_inv | MXC_UARTUCR4_IRSC, umxc->port.membase + + MXC_UARTUCR4); + writel(umxc->rxd_mux | umxc->ir_tx_inv, + umxc->port.membase + MXC_UARTUCR3); + } else { + writel(umxc->rxd_mux, umxc->port.membase + MXC_UARTUCR3); + } + + /* + * Initialize UCR1,2 and UFCR registers + */ + if (umxc->dma_enabled == 1) { + cr2 = (MXC_UARTUCR2_TXEN | MXC_UARTUCR2_RXEN); + } else { + cr2 = + (MXC_UARTUCR2_ATEN | MXC_UARTUCR2_TXEN | MXC_UARTUCR2_RXEN); + } + + writel(cr2, umxc->port.membase + MXC_UARTUCR2); + /* Wait till we are out of software reset */ + do { + cr = readl(umxc->port.membase + MXC_UARTUCR2); + } while (!(cr & MXC_UARTUCR2_SRST)); + + if (umxc->mode == MODE_DTE) { + ufcr |= ((umxc->tx_threshold << MXC_UARTUFCR_TXTL_OFFSET) | + MXC_UARTUFCR_DCEDTE | MXC_UARTUFCR_RFDIV | umxc-> + rx_threshold); + } else { + ufcr |= ((umxc->tx_threshold << MXC_UARTUFCR_TXTL_OFFSET) | + MXC_UARTUFCR_RFDIV | umxc->rx_threshold); + } + writel(ufcr, umxc->port.membase + MXC_UARTUFCR); + + /* + * Finally enable the UART and the Receive interrupts + */ + if (umxc->ir_mode == IRDA) { + cr1 |= MXC_UARTUCR1_IREN; + } + if (umxc->dma_enabled == 1) { + cr1 |= (MXC_UARTUCR1_RXDMAEN | MXC_UARTUCR1_ATDMAEN | + MXC_UARTUCR1_UARTEN); + } else { + cr1 |= (MXC_UARTUCR1_RRDYEN | MXC_UARTUCR1_UARTEN); + } + writel(cr1, umxc->port.membase + MXC_UARTUCR1); + + return 0; +} + +/*! + * This function is called by the core driver for the low-level driver to free + * its resources. The function frees all its interrupts and disables the UART. + * + * @param port the port structure for the UART passed in by the core driver + */ +static void mxcuart_shutdown(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + + /* Disable the IOMUX for the UART */ + gpio_uart_inactive(umxc->port.line, umxc->ir_mode); + mxcuart_free_interrupts(umxc); + /* Disable all interrupts, port and break condition */ + writel(0, umxc->port.membase + MXC_UARTUCR1); + writel(0, umxc->port.membase + MXC_UARTUCR3); + if (umxc->dma_enabled == 1) { + mxcuart_freedma(dma_list + umxc->port.line, umxc); + } +} + +/*! + * This function is called while changing the UART parameters. It is called to + * check if the Infrared special case bit (IRSC) in control register 4 should + * be set. + * + * @param baudrate the desired baudrate + * + * @return The functions returns 0 if the IRSC bit does not have to be set, + * else it returns a 1. + */ +/* +static int mxcuart_setir_special(u_int baudrate) +{ + u_int thresh_val; + + thresh_val = 1000000 / (8 * MIN_PULSE_DUR); + if (baudrate > thresh_val) { + return 0; + } + + return 1; +} +*/ + +/*! + * This function is called by the core driver to change the UART parameters, + * including baudrate, word length, parity, stop bits. The function also updates + * the port structures mask registers to indicate the types of events the user is + * interested in receiving. + * + * @param port the port structure for the UART passed in by the core driver + * @param termios the desired termios settings + * @param old old termios + */ +static void mxcuart_set_termios(struct uart_port *port, + struct ktermios *termios, struct ktermios *old) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + volatile unsigned int cr4 = 0, cr2 = 0, ufcr; + u_int num, denom, baud; + u_int cr2_mask; /* Used to add the changes to CR2 */ + unsigned long flags, per_clk; + int div; + + cr2_mask = ~(MXC_UARTUCR2_IRTS | MXC_UARTUCR2_CTSC | MXC_UARTUCR2_PREN | + MXC_UARTUCR2_PROE | MXC_UARTUCR2_STPB | MXC_UARTUCR2_WS); + + per_clk = clk_get_rate(umxc->clk); + + /* + * Ask the core to get the baudrate, if requested baudrate is not + * between max and min, then either use the baudrate in old termios + * setting. If it's still invalid, we try 9600 baud. + */ + baud = uart_get_baud_rate(&umxc->port, termios, old, 0, per_clk / 16); + /* Set the Reference frequency divider */ + mxcuart_set_ref_freq(umxc, per_clk, baud, &div); + + /* Byte size, default is 8-bit mode */ + switch (termios->c_cflag & CSIZE) { + case CS7: + cr2 = 0; + break; + default: + cr2 = MXC_UARTUCR2_WS; + break; + } + /* Check to see if we need 2 Stop bits */ + if (termios->c_cflag & CSTOPB) { + cr2 |= MXC_UARTUCR2_STPB; + } + + /* Check to see if we need Parity checking */ + if (termios->c_cflag & PARENB) { + cr2 |= MXC_UARTUCR2_PREN; + if (termios->c_cflag & PARODD) { + cr2 |= MXC_UARTUCR2_PROE; + } + } + spin_lock_irqsave(&umxc->port.lock, flags); + + ufcr = readl(umxc->port.membase + MXC_UARTUFCR); + ufcr = (ufcr & (~MXC_UARTUFCR_RFDIV_MASK)) | + ((6 - div) << MXC_UARTUFCR_RFDIV_OFFSET); + writel(ufcr, umxc->port.membase + MXC_UARTUFCR); + + /* + * Update the per-port timeout + */ + uart_update_timeout(&umxc->port, termios->c_cflag, baud); + + umxc->port.read_status_mask = MXC_UARTURXD_OVRRUN; + /* + * Enable appropriate events to be passed to the TTY layer + */ + if (termios->c_iflag & INPCK) { + umxc->port.read_status_mask |= MXC_UARTURXD_FRMERR | + MXC_UARTURXD_PRERR; + } + if (termios->c_iflag & (BRKINT | PARMRK)) { + umxc->port.read_status_mask |= MXC_UARTURXD_BRK; + } + + /* + * Characters to ignore + */ + umxc->port.ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) { + umxc->port.ignore_status_mask |= MXC_UARTURXD_FRMERR | + MXC_UARTURXD_PRERR; + } + if (termios->c_iflag & IGNBRK) { + umxc->port.ignore_status_mask |= MXC_UARTURXD_BRK; + /* + * If we are ignoring parity and break indicators, + * ignore overruns too (for real raw support) + */ + if (termios->c_iflag & IGNPAR) { + umxc->port.ignore_status_mask |= MXC_UARTURXD_OVRRUN; + } + } + + /* + * Ignore all characters if CREAD is not set, still receive characters + * from the port, but throw them away. + */ + if ((termios->c_cflag & CREAD) == 0) { + umxc->port.ignore_status_mask |= UART_CREAD_BIT; + } + + cr4 = readl(umxc->port.membase + MXC_UARTUCR4); + if (UART_ENABLE_MS(port, termios->c_cflag)) { + mxcuart_enable_ms(port); + if (umxc->hardware_flow == 1) { + cr4 = (cr4 & (~MXC_UARTUCR4_CTSTL_MASK)) | + (umxc->cts_threshold << MXC_UARTUCR4_CTSTL_OFFSET); + cr2 |= MXC_UARTUCR2_CTSC; + umxc->port.info->tty->hw_stopped = 0; + } else { + cr2 |= MXC_UARTUCR2_IRTS; + } + } else { + cr2 |= MXC_UARTUCR2_IRTS; + } + + /* Add Parity, character length and stop bits information */ + cr2 |= (readl(umxc->port.membase + MXC_UARTUCR2) & cr2_mask); + writel(cr2, umxc->port.membase + MXC_UARTUCR2); + /* + if (umxc->ir_mode == IRDA) { + ret = mxcuart_setir_special(baud); + if (ret == 0) { + cr4 &= ~MXC_UARTUCR4_IRSC; + } else { + cr4 |= MXC_UARTUCR4_IRSC; + } + } */ + writel(cr4, umxc->port.membase + MXC_UARTUCR4); + + /* + * Set baud rate + */ + + /* Use integer scaling, if possible. Limit the denom to 15 bits. */ + num = 0; + denom = (umxc->port.uartclk + 8 * baud) / (16 * baud) - 1; + + /* Use fractional scaling if needed to limit the max error to 0.5% */ + if (denom < 100) { + u64 n64 = (u64) 16 * 0x8000 * baud + (umxc->port.uartclk / 2); + do_div(n64, umxc->port.uartclk); + num = (u_int) n64 - 1; + denom = 0x7fff; + } + writel(num, umxc->port.membase + MXC_UARTUBIR); + writel(denom, umxc->port.membase + MXC_UARTUBMR); + + spin_unlock_irqrestore(&umxc->port.lock, flags); +} + +/*! + * This function is called by the core driver to know the UART type. + * + * @param port the port structure for the UART passed in by the core driver + * + * @return The function returns a pointer to a string describing the UART port. + */ +static const char *mxcuart_type(struct uart_port *port) +{ + return port->type == PORT_MXC ? "Freescale MXC" : NULL; +} + +/*! + * This function is called by the core driver to release the memory resources + * currently in use by the UART port. + * + * @param port the port structure for the UART passed in by the core driver + */ +static void mxcuart_release_port(struct uart_port *port) +{ + release_mem_region(port->mapbase, SZ_4K); +} + +/*! + * This function is called by the core driver to request memory resources for + * the UART port. + * + * @param port the port structure for the UART passed in by the core driver + * + * @return The function returns \b -EBUSY on failure, else it returns 0. + */ +static int mxcuart_request_port(struct uart_port *port) +{ + return request_mem_region(port->mapbase, SZ_4K, "serial_mxc") + != NULL ? 0 : -EBUSY; +} + +/*! + * This function is called by the core driver to perform any autoconfiguration + * steps required for the UART port. This function sets the port->type field. + * + * @param port the port structure for the UART passed in by the core driver + * @param flags bit mask of the required configuration + */ +static void mxcuart_config_port(struct uart_port *port, int flags) +{ + if ((flags & UART_CONFIG_TYPE) && (mxcuart_request_port(port) == 0)) { + port->type = PORT_MXC; + } +} + +/*! + * This function is called by the core driver to verify that the new serial + * port information contained within \a ser is suitable for this UART port type. + * The function checks to see if the UART port type specified by the user + * application while setting the UART port information matches what is stored + * in the define \b PORT_MXC found in the header file include/linux/serial_core.h + * + * @param port the port structure for the UART passed in by the core driver + * @param ser the new serial port information + * + * @return The function returns 0 on success or \b -EINVAL if the port type + * specified is not equal to \b PORT_MXC. + */ +static int mxcuart_verify_port(struct uart_port *port, + struct serial_struct *ser) +{ + int ret = 0; + if (ser->type != PORT_UNKNOWN && ser->type != PORT_MXC) { + ret = -EINVAL; + } + return ret; +} + +/*! + * This function is used to send a high priority XON/XOFF character + * + * @param port the port structure for the UART passed in by the core driver + * @param ch the character to send + */ +static void mxcuart_send_xchar(struct uart_port *port, char ch) +{ + unsigned long flags; + + port->x_char = ch; + if (port->info->tty->hw_stopped) { + return; + } + + if (ch) { + spin_lock_irqsave(&port->lock, flags); + port->ops->start_tx(port); + spin_unlock_irqrestore(&port->lock, flags); + } +} + +/*! + * This function is used enable/disable the MXC UART clocks + * + * @param port the port structure for the UART passed in by the core driver + * @param state New PM state + * @param oldstate Current PM state + */ +static void +mxcuart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + + if (state) { + cancel_rearming_delayed_work(&mxc_lp_work); + if (clk_get_usecount(umxc->clk)) + clk_disable(umxc->clk); + } + else { + schedule_delayed_work(&mxc_lp_work, msecs_to_jiffies(MXC_UART_IDLE_THRESH)); + if (!clk_get_usecount(umxc->clk)) + clk_enable(umxc->clk); + } +} + +/*! + * This structure contains the pointers to the control functions that are + * invoked by the core serial driver to access the UART hardware. The + * structure is passed to serial_core.c file during registration. + */ +static struct uart_ops mxc_ops = { + .tx_empty = mxcuart_tx_empty, + .set_mctrl = mxcuart_set_mctrl, + .get_mctrl = mxcuart_get_mctrl, + .stop_tx = mxcuart_stop_tx, + .start_tx = mxcuart_start_tx, + .stop_rx = mxcuart_stop_rx, + .enable_ms = mxcuart_enable_ms, + .break_ctl = mxcuart_break_ctl, + .startup = mxcuart_startup, + .shutdown = mxcuart_shutdown, + .set_termios = mxcuart_set_termios, + .type = mxcuart_type, + .pm = mxcuart_pm, + .release_port = mxcuart_release_port, + .request_port = mxcuart_request_port, + .config_port = mxcuart_config_port, + .verify_port = mxcuart_verify_port, + .send_xchar = mxcuart_send_xchar, +#ifdef CONFIG_CONSOLE_POLL + .poll_get_char = mxcuart_get_poll_char, + .poll_put_char = mxcuart_put_poll_char, +#endif +}; + +#ifdef CONFIG_SERIAL_MXC_CONSOLE + +/* + * Write out a character once the UART is ready + */ +static inline void mxcuart_console_write_char(struct uart_port *port, char ch) +{ + volatile unsigned int status; + + do { + status = readl(port->membase + MXC_UARTUSR1); + } while ((status & MXC_UARTUSR1_TRDY) == 0); + writel(ch, port->membase + MXC_UARTUTXD); +} + +/*! + * This function is called to write the console messages through the UART port. + * + * @param co the console structure + * @param s the log message to be written to the UART + * @param count length of the message + */ +static void mxcuart_console_write(struct console *co, const char *s, + u_int count) +{ + struct uart_port *port = &mxc_ports[co->index]->port; + volatile unsigned int status, oldcr1, oldcr2, oldcr3, cr2, cr3; + int i; + + /* + * First save the control registers and then disable the interrupts + */ + oldcr1 = readl(port->membase + MXC_UARTUCR1); + oldcr2 = readl(port->membase + MXC_UARTUCR2); + oldcr3 = readl(port->membase + MXC_UARTUCR3); + cr2 = + oldcr2 & ~(MXC_UARTUCR2_ATEN | MXC_UARTUCR2_RTSEN | + MXC_UARTUCR2_ESCI); + cr3 = + oldcr3 & ~(MXC_UARTUCR3_DCD | MXC_UARTUCR3_RI | + MXC_UARTUCR3_DTRDEN); + writel(MXC_UARTUCR1_UARTEN, port->membase + MXC_UARTUCR1); + writel(cr2, port->membase + MXC_UARTUCR2); + writel(cr3, port->membase + MXC_UARTUCR3); + /* + * Do each character + */ + for (i = 0; i < count; i++) { + mxcuart_console_write_char(port, s[i]); + if (s[i] == '\n') { + mxcuart_console_write_char(port, '\r'); + } + } + /* + * Finally, wait for the transmitter to become empty + */ + do { + status = readl(port->membase + MXC_UARTUSR2); + } while (!(status & MXC_UARTUSR2_TXDC)); + + /* + * Restore the control registers + */ + writel(oldcr1, port->membase + MXC_UARTUCR1); + writel(oldcr2, port->membase + MXC_UARTUCR2); + writel(oldcr3, port->membase + MXC_UARTUCR3); +} + +/*! + * Initializes the UART port to be used to print console message with the + * options specified. If no options are specified, then the function + * initializes the UART with the default options of baudrate=115200, 8 bit + * word size, no parity, no flow control. + * + * @param co The console structure + * @param options Any console options passed in from the command line + * + * @return The function returns 0 on success or error. + */ +static int __init mxcuart_console_setup(struct console *co, char *options) +{ + uart_mxc_port *umxc; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + volatile unsigned int cr = 0; + + /* + * Check whether an invalid uart number had been specified, and if + * so, search for the first available port that does have console + * support + */ + if (co->index >= MXC_UART_NR) { + co->index = 0; + } + umxc = mxc_ports[co->index]; + + if (umxc == NULL) { + return -ENODEV; + } + + /* initialize port.lock else oops */ + spin_lock_init(&umxc->port.lock); + + /* + * Initialize the UART registers + */ + writel(MXC_UARTUCR1_UARTEN, umxc->port.membase + MXC_UARTUCR1); + /* Enable the transmitter and do a software reset */ + writel(MXC_UARTUCR2_TXEN, umxc->port.membase + MXC_UARTUCR2); + /* Wait till we are out of software reset */ + do { + cr = readl(umxc->port.membase + MXC_UARTUCR2); + } while (!(cr & MXC_UARTUCR2_SRST)); + + writel(0x0, umxc->port.membase + MXC_UARTUCR3); + writel(0x0, umxc->port.membase + MXC_UARTUCR4); + /* Set TXTL to 2, RXTL to 1 and RFDIV to 2 */ + cr = 0x0800 | MXC_UARTUFCR_RFDIV | 0x1; + if (umxc->mode == MODE_DTE) { + cr |= MXC_UARTUFCR_DCEDTE; + } + writel(cr, umxc->port.membase + MXC_UARTUFCR); + writel(0xFFFF, umxc->port.membase + MXC_UARTUSR1); + writel(0xFFFF, umxc->port.membase + MXC_UARTUSR2); + + if (options != NULL) { + uart_parse_options(options, &baud, &parity, &bits, &flow); + } + gpio_uart_active(umxc->port.line, umxc->ir_mode); + return uart_set_options(&umxc->port, co, baud, parity, bits, flow); +} + +static struct uart_driver mxc_reg; + +/*! + * This structure contains the pointers to the UART console functions. It is + * passed as an argument when registering the console. + */ +static struct console mxc_console = { + .name = "ttymxc", + .write = mxcuart_console_write, + .device = uart_console_device, + .setup = mxcuart_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &mxc_reg, +}; + +/*! + * This function registers the console callback functions with the kernel. + */ +static int __init mxcuart_console_init(void) +{ + register_console(&mxc_console); + return 0; +} + +console_initcall(mxcuart_console_init); + +static int __init find_port(struct uart_port *p) +{ + int line; + struct uart_port *port; + for (line = 0; line < MXC_UART_NR; line++) { + if (!mxc_ports[line]) + continue; + port = &mxc_ports[line]->port; + if (uart_match_port(p, port)) + return line; + } + return -ENODEV; +} + +int __init mxc_uart_start_console(struct uart_port *port, char *options) +{ + int line; + line = find_port(port); + if (line < 0) + return -ENODEV; + + add_preferred_console("ttymxc", line, options); + printk("Switching Console to ttymxc%d at %s 0x%lx (options '%s')\n", + line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port", + port->iotype == + UPIO_MEM ? (unsigned long)port->mapbase : (unsigned long)port-> + iobase, options); + + if (!(mxc_console.flags & CON_ENABLED)) { + mxc_console.flags &= ~CON_PRINTBUFFER; + register_console(&mxc_console); + } + return 0; +} + +#define MXC_CONSOLE &mxc_console +#else +#define MXC_CONSOLE NULL +#endif /* CONFIG_SERIAL_MXC_CONSOLE */ + +/*! + * This structure contains the information such as the name of the UART driver + * that appears in the /dev folder, major and minor numbers etc. This structure + * is passed to the serial_core.c file. + */ +static struct uart_driver mxc_reg = { + .owner = THIS_MODULE, + .driver_name = "ttymxc", + .dev_name = "ttymxc", + .major = SERIAL_MXC_MAJOR, + .minor = SERIAL_MXC_MINOR, + .nr = MXC_UART_NR, + .cons = MXC_CONSOLE, +}; + +/*! + * This function is called to put the UART in a low power state. Refer to the + * document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which UART + * to suspend + * @param state the power state the device is entering + * + * @return The function returns 0 on success and -1 on failure + */ +static int mxcuart_suspend(struct platform_device *pdev, pm_message_t state) +{ + uart_mxc_port *umxc = platform_get_drvdata(pdev); + + if (umxc == NULL) + return 0; /* skip disabled ports */ + + if (umxc->port.info && umxc->port.info->flags & UIF_INITIALIZED) + uart_suspend_port(&mxc_reg, &umxc->port); + + if (umxc->port.info && umxc->port.info->flags & UIF_SUSPENDED) + umxc->port.info->tty->hw_stopped = 1; + + return 0; +} + +/*! + * This function is called to bring the UART back from a low power state. Refer + * to the document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which UART + * to resume + * + * @return The function returns 0 on success and -1 on failure + */ +static int mxcuart_resume(struct platform_device *pdev) +{ + uart_mxc_port *umxc = platform_get_drvdata(pdev); + + if (umxc == NULL) + return 0; /* skip disabled ports */ + + if (umxc->port.info && umxc->port.info->flags & UIF_SUSPENDED) { + umxc->port.info->tty->hw_stopped = 0; + uart_resume_port(&mxc_reg, &umxc->port); + } + + return 0; +} + +/*! + * This function is called during the driver binding process. Based on the UART + * that is being probed this function adds the appropriate UART port structure + * in the core driver. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions + * + * @return The function returns 0 if successful; -1 otherwise. + */ +static int mxcuart_probe(struct platform_device *pdev) +{ + int id = pdev->id; + + mxc_ports[id] = pdev->dev.platform_data; + mxc_ports[id]->port.ops = &mxc_ops; + + /* Do not use UARTs that are disabled during integration */ + if (mxc_ports[id]->enabled == 1) { + mxc_ports[id]->port.dev = &pdev->dev; + spin_lock_init(&mxc_ports[id]->port.lock); + /* Enable the low latency flag for DMA UART ports */ + if (mxc_ports[id]->dma_enabled == 1) { + mxc_ports[id]->port.flags |= UPF_LOW_LATENCY; + } + + mxc_ports[id]->clk = clk_get(&pdev->dev, "uart_clk"); + if (mxc_ports[id]->clk == NULL) + return -1; + + uart_add_one_port(&mxc_reg, &mxc_ports[id]->port); + platform_set_drvdata(pdev, mxc_ports[id]); + + if (id == 0) { + if (device_create_file(mxc_ports[id]->port.dev, + &dev_attr_uart_clk_state) < 0) + printk(KERN_ERR "MXC Uart: Error creating uart_clk_state file\n"); + } + } + return 0; +} + +/*! + * Dissociates the driver from the UART device. Removes the appropriate UART + * port structure from the core driver. + * + * @param pdev the device structure used to give information on which UART + * to remove + * + * @return The function always returns 0. + */ +static int mxcuart_remove(struct platform_device *pdev) +{ + uart_mxc_port *umxc = platform_get_drvdata(pdev); + + platform_set_drvdata(pdev, NULL); + + if (umxc) { + uart_remove_one_port(&mxc_reg, &umxc->port); + if (pdev->id == 0) + device_remove_file(umxc->port.dev, &dev_attr_uart_clk_state); + } + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxcuart_driver = { + .driver = { + .name = "mxcintuart", + }, + .probe = mxcuart_probe, + .remove = mxcuart_remove, + .suspend = mxcuart_suspend, + .resume = mxcuart_resume, +}; + +/*! + * This function is used to initialize the UART driver module. The function + * registers the power management callback functions with the kernel and also + * registers the UART callback functions with the core serial driver. + * + * @return The function returns 0 on success and a non-zero value on failure. + */ +static int __init mxcuart_init(void) +{ + int ret = 0; + + printk(KERN_INFO "Serial: MXC Internal UART driver\n"); + ret = uart_register_driver(&mxc_reg); + if (ret == 0) { + /* Register the device driver structure. */ + ret = platform_driver_register(&mxcuart_driver); + if (ret != 0) { + uart_unregister_driver(&mxc_reg); + } + } + mxc_uart_clock_gate = 1; /* Turn on clock gating by default */ + schedule_delayed_work(&mxc_lp_work, msecs_to_jiffies(MXC_UART_IDLE_START)); + return ret; +} + +/*! + * This function is used to cleanup all resources before the driver exits. + */ +static void __exit mxcuart_exit(void) +{ + platform_driver_unregister(&mxcuart_driver); + uart_unregister_driver(&mxc_reg); +} + +module_init(mxcuart_init); +module_exit(mxcuart_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC serial port driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/serial/mxc_uart_early.c linux-2.6.26-lab126/drivers/serial/mxc_uart_early.c --- linux-2.6.26/drivers/serial/mxc_uart_early.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/serial/mxc_uart_early.c 2010-08-10 04:15:30.000000000 -0400 @@ -0,0 +1,252 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file drivers/serial/mxc_uart_early.c + * + * @brief Driver for the Freescale Semiconductor MXC serial ports based on + * drivers/char/8250_early.c, Copyright 2004 Hewlett-Packard Development Company, + * L.P. by Bjorn Helgaasby. + * + * Early serial console for MXC UARTS. + * + * This is for use before the serial driver has initialized, in + * particular, before the UARTs have been discovered and named. + * Instead of specifying the console device as, e.g., "ttymxc0", + * we locate the device directly by its MMIO or I/O port address. + * + * The user can specify the device directly, e.g., + * console=mxcuart,0x43f90000,115200n8 + * or platform code can call early_uart_console_init() to set + * the early UART device. + * + * After the normal serial driver starts, we try to locate the + * matching ttymxc device and start a console there. + */ + +/* + * Include Files + */ + +#include +#include +#include +#include +#include +#include +#include + +struct mxc_early_uart_device { + struct uart_port port; + char options[16]; /* e.g., 115200n8 */ + unsigned int baud; +}; + +int __init mxc_uart_start_console(struct uart_port *, char *); +static struct mxc_early_uart_device mxc_early_device __initdata; +static int mxc_early_uart_registered __initdata; +static struct clk *clk; + +/* + * Write out a character once the UART is ready + */ +static void __init mxcuart_console_write_char(struct uart_port *port, int ch) +{ + unsigned int status; + + do { + status = readl(port->membase + MXC_UARTUSR1); + } while ((status & MXC_UARTUSR1_TRDY) == 0); + writel(ch, port->membase + MXC_UARTUTXD); +} + +/*! + * This function is called to write the console messages through the UART port. + * + * @param co the console structure + * @param s the log message to be written to the UART + * @param count length of the message + */ +void __init early_mxcuart_console_write(struct console *co, const char *s, + u_int count) +{ + struct uart_port *port = &mxc_early_device.port; + volatile unsigned int status, oldcr1, oldcr2, oldcr3, cr2, cr3; + + /* + * First save the control registers and then disable the interrupts + */ + oldcr1 = readl(port->membase + MXC_UARTUCR1); + oldcr2 = readl(port->membase + MXC_UARTUCR2); + oldcr3 = readl(port->membase + MXC_UARTUCR3); + cr2 = + oldcr2 & ~(MXC_UARTUCR2_ATEN | MXC_UARTUCR2_RTSEN | + MXC_UARTUCR2_ESCI); + cr3 = + oldcr3 & ~(MXC_UARTUCR3_DCD | MXC_UARTUCR3_RI | + MXC_UARTUCR3_DTRDEN); + writel(MXC_UARTUCR1_UARTEN, port->membase + MXC_UARTUCR1); + writel(cr2, port->membase + MXC_UARTUCR2); + writel(cr3, port->membase + MXC_UARTUCR3); + + /* Transmit string */ + uart_console_write(port, s, count, mxcuart_console_write_char); + + /* + * Finally, wait for the transmitter to become empty + */ + do { + status = readl(port->membase + MXC_UARTUSR2); + } while (!(status & MXC_UARTUSR2_TXDC)); + + /* + * Restore the control registers + */ + writel(oldcr1, port->membase + MXC_UARTUCR1); + writel(oldcr2, port->membase + MXC_UARTUCR2); + writel(oldcr3, port->membase + MXC_UARTUCR3); +} + +static unsigned int __init probe_baud(struct uart_port *port) +{ + /* FIXME Return Default Baud Rate */ + return 115200; +} + +static int __init parse_options(struct mxc_early_uart_device *device, + char *options) +{ + struct uart_port *port = &device->port; + int mapsize = 64; + int length; + + if (!options) + return -ENODEV; + + port->uartclk = 5600000; + port->iotype = UPIO_MEM; + port->mapbase = simple_strtoul(options, &options, 0); + port->membase = ioremap(port->mapbase, mapsize); + + if ((options = strchr(options, ','))) { + options++; + device->baud = simple_strtoul(options, NULL, 0); + length = min(strcspn(options, " "), sizeof(device->options)); + strncpy(device->options, options, length); + } else { + device->baud = probe_baud(port); + snprintf(device->options, sizeof(device->options), "%u", + device->baud); + } + printk(KERN_INFO + "MXC_Early serial console at MMIO 0x%x (options '%s')\n", + port->mapbase, device->options); + return 0; +} + +static int __init mxc_early_uart_setup(struct console *console, char *options) +{ + struct mxc_early_uart_device *device = &mxc_early_device; + int err; + if (device->port.membase || device->port.iobase) + return 0; + if ((err = parse_options(device, options)) < 0) + return err; + return 0; +} + +static struct console mxc_early_uart_console __initdata = { + .name = "mxcuart", + .write = early_mxcuart_console_write, + .setup = mxc_early_uart_setup, + .flags = CON_PRINTBUFFER, + .index = -1, +}; + +static int __init mxc_early_uart_console_init(void) +{ + + if (!mxc_early_uart_registered) { + register_console(&mxc_early_uart_console); + mxc_early_uart_registered = 1; + } + + return 0; +} + +int __init mxc_early_serial_console_init(char *cmdline) +{ + char *options; + int err; + int uart_paddr; + + options = strstr(cmdline, "console=mxcuart"); + if (!options) + return -ENODEV; + + /* Extracting MXC UART Uart Port Address from cmdline */ + options = strchr(cmdline, ',') + 1; + uart_paddr = simple_strtoul(options, NULL, 16); + +#ifdef UART1_BASE_ADDR + if (uart_paddr == UART1_BASE_ADDR) + clk = clk_get(NULL, "uart_clk.0"); +#endif +#ifdef UART2_BASE_ADDR + if (uart_paddr == UART2_BASE_ADDR) + clk = clk_get(NULL, "uart_clk.1"); +#endif +#ifdef UART3_BASE_ADDR + if (uart_paddr == UART3_BASE_ADDR) + clk = clk_get(NULL, "uart_clk.2"); +#endif + if (clk == NULL) + return -1; + + /* Enable Early MXC UART Clock */ + clk_enable(clk); + + options = strchr(cmdline, ',') + 1; + if ((err = mxc_early_uart_setup(NULL, options)) < 0) + return err; + return mxc_early_uart_console_init(); +} + +int __init mxc_early_uart_console_switch(void) +{ + struct mxc_early_uart_device *device = &mxc_early_device; + struct uart_port *port = &device->port; + int mmio, line; + + if (!(mxc_early_uart_console.flags & CON_ENABLED)) + return 0; + /* Try to start the normal driver on a matching line. */ + mmio = (port->iotype == UPIO_MEM); + line = mxc_uart_start_console(port, device->options); + + if (line < 0) + printk("No ttymxc device at %s 0x%lx for console\n", + mmio ? "MMIO" : "I/O port", + mmio ? port->mapbase : (unsigned long)port->iobase); + + unregister_console(&mxc_early_uart_console); + if (mmio) + iounmap(port->membase); + + clk_disable(clk); + clk_put(clk); + + return 0; +} + +late_initcall(mxc_early_uart_console_switch); diff -urN linux-2.6.26/drivers/serial/mxc_uart_reg.h linux-2.6.26-lab126/drivers/serial/mxc_uart_reg.h --- linux-2.6.26/drivers/serial/mxc_uart_reg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/serial/mxc_uart_reg.h 2010-08-10 04:15:30.000000000 -0400 @@ -0,0 +1,128 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MXC_UART_REG_H__ +#define __MXC_UART_REG_H__ + +/* Address offsets of the UART registers */ +#define MXC_UARTURXD 0x000 /* Receive reg */ +#define MXC_UARTUTXD 0x040 /* Transmitter reg */ +#define MXC_UARTUCR1 0x080 /* Control reg 1 */ +#define MXC_UARTUCR2 0x084 /* Control reg 2 */ +#define MXC_UARTUCR3 0x088 /* Control reg 3 */ +#define MXC_UARTUCR4 0x08C /* Control reg 4 */ +#define MXC_UARTUFCR 0x090 /* FIFO control reg */ +#define MXC_UARTUSR1 0x094 /* Status reg 1 */ +#define MXC_UARTUSR2 0x098 /* Status reg 2 */ +#define MXC_UARTUESC 0x09C /* Escape character reg */ +#define MXC_UARTUTIM 0x0A0 /* Escape timer reg */ +#define MXC_UARTUBIR 0x0A4 /* BRM incremental reg */ +#define MXC_UARTUBMR 0x0A8 /* BRM modulator reg */ +#define MXC_UARTUBRC 0x0AC /* Baud rate count reg */ +#define MXC_UARTONEMS 0x0B0 /* One millisecond reg */ +#define MXC_UARTUTS 0x0B4 /* Test reg */ + +/* Bit definations of UCR1 */ +#define MXC_UARTUCR1_ADEN 0x8000 +#define MXC_UARTUCR1_ADBR 0x4000 +#define MXC_UARTUCR1_TRDYEN 0x2000 +#define MXC_UARTUCR1_IDEN 0x1000 +#define MXC_UARTUCR1_RRDYEN 0x0200 +#define MXC_UARTUCR1_RXDMAEN 0x0100 +#define MXC_UARTUCR1_IREN 0x0080 +#define MXC_UARTUCR1_TXMPTYEN 0x0040 +#define MXC_UARTUCR1_RTSDEN 0x0020 +#define MXC_UARTUCR1_SNDBRK 0x0010 +#define MXC_UARTUCR1_TXDMAEN 0x0008 +#define MXC_UARTUCR1_ATDMAEN 0x0004 +#define MXC_UARTUCR1_DOZE 0x0002 +#define MXC_UARTUCR1_UARTEN 0x0001 + +/* Bit definations of UCR2 */ +#define MXC_UARTUCR2_ESCI 0x8000 +#define MXC_UARTUCR2_IRTS 0x4000 +#define MXC_UARTUCR2_CTSC 0x2000 +#define MXC_UARTUCR2_CTS 0x1000 +#define MXC_UARTUCR2_PREN 0x0100 +#define MXC_UARTUCR2_PROE 0x0080 +#define MXC_UARTUCR2_STPB 0x0040 +#define MXC_UARTUCR2_WS 0x0020 +#define MXC_UARTUCR2_RTSEN 0x0010 +#define MXC_UARTUCR2_ATEN 0x0008 +#define MXC_UARTUCR2_TXEN 0x0004 +#define MXC_UARTUCR2_RXEN 0x0002 +#define MXC_UARTUCR2_SRST 0x0001 + +/* Bit definations of UCR3 */ +#define MXC_UARTUCR3_DTREN 0x2000 +#define MXC_UARTUCR3_PARERREN 0x1000 +#define MXC_UARTUCR3_FRAERREN 0x0800 +#define MXC_UARTUCR3_DSR 0x0400 +#define MXC_UARTUCR3_DCD 0x0200 +#define MXC_UARTUCR3_RI 0x0100 +#define MXC_UARTUCR3_RXDSEN 0x0040 +#define MXC_UARTUCR3_AWAKEN 0x0010 +#define MXC_UARTUCR3_DTRDEN 0x0008 +#define MXC_UARTUCR3_RXDMUXSEL 0x0004 +#define MXC_UARTUCR3_INVT 0x0002 + +/* Bit definations of UCR4 */ +#define MXC_UARTUCR4_CTSTL_OFFSET 10 +#define MXC_UARTUCR4_CTSTL_MASK (0x3F << 10) +#define MXC_UARTUCR4_INVR 0x0200 +#define MXC_UARTUCR4_ENIRI 0x0100 +#define MXC_UARTUCR4_REF16 0x0040 +#define MXC_UARTUCR4_IRSC 0x0020 +#define MXC_UARTUCR4_TCEN 0x0008 +#define MXC_UARTUCR4_OREN 0x0002 +#define MXC_UARTUCR4_DREN 0x0001 + +/* Bit definations of UFCR */ +#define MXC_UARTUFCR_RFDIV 0x0200 /* Ref freq div is set to 2 */ +#define MXC_UARTUFCR_RFDIV_OFFSET 7 +#define MXC_UARTUFCR_RFDIV_MASK (0x7 << 7) +#define MXC_UARTUFCR_TXTL_OFFSET 10 +#define MXC_UARTUFCR_DCEDTE 0x0040 + +/* Bit definations of URXD */ +#define MXC_UARTURXD_ERR 0x4000 +#define MXC_UARTURXD_OVRRUN 0x2000 +#define MXC_UARTURXD_FRMERR 0x1000 +#define MXC_UARTURXD_BRK 0x0800 +#define MXC_UARTURXD_PRERR 0x0400 + +/* Bit definations of USR1 */ +#define MXC_UARTUSR1_PARITYERR 0x8000 +#define MXC_UARTUSR1_RTSS 0x4000 +#define MXC_UARTUSR1_TRDY 0x2000 +#define MXC_UARTUSR1_RTSD 0x1000 +#define MXC_UARTUSR1_FRAMERR 0x0400 +#define MXC_UARTUSR1_RRDY 0x0200 +#define MXC_UARTUSR1_AGTIM 0x0100 +#define MXC_UARTUSR1_DTRD 0x0080 +#define MXC_UARTUSR1_AWAKE 0x0010 + +/* Bit definations of USR2 */ +#define MXC_UARTUSR2_TXFE 0x4000 +#define MXC_UARTUSR2_IDLE 0x1000 +#define MXC_UARTUSR2_RIDELT 0x0400 +#define MXC_UARTUSR2_RIIN 0x0200 +#define MXC_UARTUSR2_DCDDELT 0x0040 +#define MXC_UARTUSR2_DCDIN 0x0020 +#define MXC_UARTUSR2_TXDC 0x0008 +#define MXC_UARTUSR2_ORE 0x0002 +#define MXC_UARTUSR2_RDR 0x0001 + +/* Bit definations of UTS */ +#define MXC_UARTUTS_LOOP 0x1000 + +#endif /* __MXC_UART_REG_H__ */ diff -urN linux-2.6.26/drivers/spi/Kconfig linux-2.6.26-lab126/drivers/spi/Kconfig --- linux-2.6.26/drivers/spi/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/spi/Kconfig 2010-08-10 04:15:39.000000000 -0400 @@ -198,6 +198,34 @@ See the "OPB Serial Peripheral Interface (SPI) (v1.00e)" Product Specification document (DS464) for hardware details. +config SPI_MXC + tristate "MXC CSPI controller as SPI Master" + depends on ARCH_MXC && SPI_MASTER + select SPI_BITBANG + help + This implements the SPI master mode using MXC CSPI. + +config SPI_MXC_TEST_LOOPBACK + bool "LOOPBACK Testing of CSPIs" + depends on SPI_MXC + select SPI_SPIDEV + default n + +config SPI_MXC_SELECT1 + bool "CSPI1" + depends on SPI_MXC + default y + +config SPI_MXC_SELECT2 + bool "CSPI2" + depends on SPI_MXC && (!ARCH_MXC91221) + default n + +config SPI_MXC_SELECT3 + bool "CSPI3" + depends on SPI_MXC && (ARCH_MX3 || ARCH_MX27 || ARCH_MX37 || ARCH_MX51) + default n + # # Add new SPI master controllers in alphabetical order above this line # diff -urN linux-2.6.26/drivers/spi/Makefile linux-2.6.26-lab126/drivers/spi/Makefile --- linux-2.6.26/drivers/spi/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/spi/Makefile 2010-08-10 04:15:39.000000000 -0400 @@ -26,6 +26,7 @@ obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx.o obj-$(CONFIG_SPI_TXX9) += spi_txx9.o +obj-$(CONFIG_SPI_MXC) += mxc_spi.o obj-$(CONFIG_SPI_XILINX) += xilinx_spi.o obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.o # ... add above this line ... diff -urN linux-2.6.26/drivers/spi/mxc_spi.c linux-2.6.26-lab126/drivers/spi/mxc_spi.c --- linux-2.6.26/drivers/spi/mxc_spi.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/spi/mxc_spi.c 2010-08-10 04:15:39.000000000 -0400 @@ -0,0 +1,1252 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-licensisr_locke.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup SPI Configurable Serial Peripheral Interface (CSPI) Driver + */ + +/*! + * @file mxc_spi.c + * @brief This file contains the implementation of the SPI master controller services + * + * + * @ingroup SPI + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MXC_CSPIRXDATA 0x00 +#define MXC_CSPITXDATA 0x04 +#define MXC_CSPICTRL 0x08 +#define MXC_CSPICONFIG 0x08 +#define MXC_CSPIINT 0x0C + +#define MXC_CSPICTRL_DISABLE 0x0 +#define MXC_CSPICTRL_SLAVE 0x0 +#define MXC_CSPICTRL_CSMASK 0x3 +#define MXC_CSPICTRL_SMC (1 << 3) + +#define MXC_CSPIINT_TEEN_SHIFT 0 +#define MXC_CSPIINT_THEN_SHIFT 1 +#define MXC_CSPIINT_TFEN_SHIFT 2 +#define MXC_CSPIINT_RREN_SHIFT 3 +#define MXC_CSPIINT_RHEN_SHIFT 4 +#define MXC_CSPIINT_RFEN_SHIFT 5 +#define MXC_CSPIINT_ROEN_SHIFT 6 + +#define MXC_HIGHPOL 0x0 +#define MXC_NOPHA 0x0 +#define MXC_LOWSSPOL 0x0 + +#define MXC_CSPISTAT_TE 0 +#define MXC_CSPISTAT_TH 1 +#define MXC_CSPISTAT_TF 2 +#define MXC_CSPISTAT_RR 3 +#define MXC_CSPISTAT_RH 4 +#define MXC_CSPISTAT_RF 5 +#define MXC_CSPISTAT_RO 6 + +#define MXC_CSPIPERIOD_32KHZ (1 << 15) + +/*! + * @struct mxc_spi_unique_def + * @brief This structure contains information that differs with + * SPI master controller hardware version + */ +struct mxc_spi_unique_def { + /* Width of valid bits in MXC_CSPIINT */ + unsigned int intr_bit_shift; + /* Chip Select shift */ + unsigned int cs_shift; + /* Bit count shift */ + unsigned int bc_shift; + /* Bit count mask */ + unsigned int bc_mask; + /* Data Control shift */ + unsigned int drctrl_shift; + /* Transfer Complete shift */ + unsigned int xfer_complete; + /* Bit counnter overflow shift */ + unsigned int bc_overflow; + /* FIFO Size */ + unsigned int fifo_size; + /* Control reg address */ + unsigned int ctrl_reg_addr; + /* Status reg address */ + unsigned int stat_reg_addr; + /* Period reg address */ + unsigned int period_reg_addr; + /* Test reg address */ + unsigned int test_reg_addr; + /* Reset reg address */ + unsigned int reset_reg_addr; + /* SPI mode mask */ + unsigned int mode_mask; + /* SPI enable */ + unsigned int spi_enable; + /* XCH bit */ + unsigned int xch; + /* Spi mode shift */ + unsigned int mode_shift; + /* Spi master mode enable */ + unsigned int master_enable; + /* TX interrupt enable diff */ + unsigned int tx_inten_dif; + /* RX interrupt enable bit diff */ + unsigned int rx_inten_dif; + /* Interrupt status diff */ + unsigned int int_status_dif; + /* Low pol shift */ + unsigned int low_pol_shift; + /* Phase shift */ + unsigned int pha_shift; + /* SS control shift */ + unsigned int ss_ctrl_shift; + /* SS pol shift */ + unsigned int ss_pol_shift; + /* Maximum data rate */ + unsigned int max_data_rate; + /* Data mask */ + unsigned int data_mask; + /* Data shift */ + unsigned int data_shift; + /* Loopback control */ + unsigned int lbc; + /* RX count off */ + unsigned int rx_cnt_off; + /* RX count mask */ + unsigned int rx_cnt_mask; + /* Reset start */ + unsigned int reset_start; + /* SCLK control inactive state shift */ + unsigned int sclk_ctl_shift; +}; + +struct mxc_spi; + +/*! + * Structure to group together all the data buffers and functions + * used in data transfers. + */ +struct mxc_spi_xfer { + /* Transmit buffer */ + const void *tx_buf; + /* Receive buffer */ + void *rx_buf; + /* Data transfered count */ + unsigned int count; + /* Data received count, descending sequence, zero means no more data to + be received */ + unsigned int rx_count; + /* Function to read the FIFO data to rx_buf */ + void (*rx_get) (struct mxc_spi *, u32 val); + /* Function to get the data to be written to FIFO */ + u32(*tx_get) (struct mxc_spi *); +}; + +/*! + * This structure is a way for the low level driver to define their own + * \b spi_master structure. This structure includes the core \b spi_master + * structure that is provided by Linux SPI Framework/driver as an + * element and has other elements that are specifically required by this + * low-level driver. + */ +struct mxc_spi { + /* SPI Master and a simple I/O queue runner */ + struct spi_bitbang mxc_bitbang; + /* Completion flags used in data transfers */ + struct completion xfer_done; + /* Data transfer structure */ + struct mxc_spi_xfer transfer; + /* Resource structure, which will maintain base addresses and IRQs */ + struct resource *res; + /* Base address of CSPI, used in readl and writel */ + void *base; + /* CSPI IRQ number */ + int irq; + /* CSPI Clock id */ + struct clk *clk; + /* CSPI input clock SCLK */ + unsigned long spi_ipg_clk; + /* CSPI registers' bit pattern */ + struct mxc_spi_unique_def *spi_ver_def; + /* Control reg address */ + void *ctrl_addr; + /* Status reg address */ + void *stat_addr; + /* Period reg address */ + void *period_addr; + /* Test reg address */ + void *test_addr; + /* Reset reg address */ + void *reset_addr; +}; + +#ifdef CONFIG_SPI_MXC_TEST_LOOPBACK +struct spi_chip_info { + int lb_enable; +}; + +static struct spi_chip_info lb_chip_info = { + .lb_enable = 1, +}; + +static struct spi_board_info loopback_info[] = { +#ifdef CONFIG_SPI_MXC_SELECT1 + { + .modalias = "spidev", + .controller_data = &lb_chip_info, + .irq = 0, + .max_speed_hz = 4000000, + .bus_num = 1, + .chip_select = 4, + }, +#endif +#ifdef CONFIG_SPI_MXC_SELECT2 + { + .modalias = "spidev", + .controller_data = &lb_chip_info, + .irq = 0, + .max_speed_hz = 4000000, + .bus_num = 2, + .chip_select = 4, + }, +#endif +#ifdef CONFIG_SPI_MXC_SELECT3 + { + .modalias = "spidev", + .controller_data = &lb_chip_info, + .irq = 0, + .max_speed_hz = 4000000, + .bus_num = 3, + .chip_select = 4, + }, +#endif +}; +#endif + +static struct mxc_spi_unique_def spi_ver_2_3 = { + .intr_bit_shift = 8, + .cs_shift = 18, + .bc_shift = 20, + .bc_mask = 0xFFF, + .drctrl_shift = 16, + .xfer_complete = (1 << 7), + .bc_overflow = 0, + .fifo_size = 64, + .ctrl_reg_addr = 4, + .stat_reg_addr = 0x18, + .period_reg_addr = 0x1C, + .test_reg_addr = 0x20, + .reset_reg_addr = 0x8, + .mode_mask = 0xF, + .spi_enable = 0x1, + .xch = (1 << 2), + .mode_shift = 4, + .master_enable = 0, + .tx_inten_dif = 0, + .rx_inten_dif = 0, + .int_status_dif = 0, + .low_pol_shift = 4, + .pha_shift = 0, + .ss_ctrl_shift = 8, + .ss_pol_shift = 12, + .max_data_rate = 0xF, + .data_mask = 0xFF, + .data_shift = 8, + .lbc = (1 << 31), + .rx_cnt_off = 8, + .rx_cnt_mask = (0x7F << 8), + .reset_start = 0, + .sclk_ctl_shift = 20, +}; + +static struct mxc_spi_unique_def spi_ver_0_7 = { + .intr_bit_shift = 8, + .cs_shift = 12, + .bc_shift = 20, + .bc_mask = 0xFFF, + .drctrl_shift = 8, + .xfer_complete = (1 << 7), + .bc_overflow = 0, + .fifo_size = 8, + .ctrl_reg_addr = 0, + .stat_reg_addr = 0x14, + .period_reg_addr = 0x18, + .test_reg_addr = 0x1C, + .reset_reg_addr = 0x0, + .mode_mask = 0x1, + .spi_enable = 0x1, + .xch = (1 << 2), + .mode_shift = 1, + .master_enable = 1 << 1, + .tx_inten_dif = 0, + .rx_inten_dif = 0, + .int_status_dif = 0, + .low_pol_shift = 4, + .pha_shift = 5, + .ss_ctrl_shift = 6, + .ss_pol_shift = 7, + .max_data_rate = 0x7, + .data_mask = 0x7, + .data_shift = 16, + .lbc = (1 << 14), + .rx_cnt_off = 4, + .rx_cnt_mask = (0xF << 4), + .reset_start = 1, +}; + +static struct mxc_spi_unique_def spi_ver_0_5 = { + .intr_bit_shift = 9, + .cs_shift = 12, + .bc_shift = 20, + .bc_mask = 0xFFF, + .drctrl_shift = 8, + .xfer_complete = (1 << 8), + .bc_overflow = (1 << 7), + .fifo_size = 8, + .ctrl_reg_addr = 0, + .stat_reg_addr = 0x14, + .period_reg_addr = 0x18, + .test_reg_addr = 0x1C, + .reset_reg_addr = 0x0, + .mode_mask = 0x1, + .spi_enable = 0x1, + .xch = (1 << 2), + .mode_shift = 1, + .master_enable = 1 << 1, + .tx_inten_dif = 0, + .rx_inten_dif = 0, + .int_status_dif = 0, + .low_pol_shift = 4, + .pha_shift = 5, + .ss_ctrl_shift = 6, + .ss_pol_shift = 7, + .max_data_rate = 0x7, + .data_mask = 0x7, + .data_shift = 16, + .lbc = (1 << 14), + .rx_cnt_off = 4, + .rx_cnt_mask = (0xF << 4), + .reset_start = 1, +}; + +static struct mxc_spi_unique_def spi_ver_0_4 = { + .intr_bit_shift = 9, + .cs_shift = 24, + .bc_shift = 8, + .bc_mask = 0x1F, + .drctrl_shift = 20, + .xfer_complete = (1 << 8), + .bc_overflow = (1 << 7), + .fifo_size = 8, + .ctrl_reg_addr = 0, + .stat_reg_addr = 0x14, + .period_reg_addr = 0x18, + .test_reg_addr = 0x1C, + .reset_reg_addr = 0x0, + .mode_mask = 0x1, + .spi_enable = 0x1, + .xch = (1 << 2), + .mode_shift = 1, + .master_enable = 1 << 1, + .tx_inten_dif = 0, + .rx_inten_dif = 0, + .int_status_dif = 0, + .low_pol_shift = 4, + .pha_shift = 5, + .ss_ctrl_shift = 6, + .ss_pol_shift = 7, + .max_data_rate = 0x7, + .data_mask = 0x7, + .data_shift = 16, + .lbc = (1 << 14), + .rx_cnt_off = 4, + .rx_cnt_mask = (0xF << 4), + .reset_start = 1, +}; + +static struct mxc_spi_unique_def spi_ver_0_0 = { + .intr_bit_shift = 18, + .cs_shift = 19, + .bc_shift = 0, + .bc_mask = 0x1F, + .drctrl_shift = 12, + .xfer_complete = (1 << 3), + .bc_overflow = (1 << 8), + .fifo_size = 8, + .ctrl_reg_addr = 0, + .stat_reg_addr = 0x0C, + .period_reg_addr = 0x14, + .test_reg_addr = 0x10, + .reset_reg_addr = 0x1C, + .mode_mask = 0x1, + .spi_enable = (1 << 10), + .xch = (1 << 9), + .mode_shift = 11, + .master_enable = 1 << 11, + .tx_inten_dif = 9, + .rx_inten_dif = 10, + .int_status_dif = 1, + .low_pol_shift = 5, + .pha_shift = 6, + .ss_ctrl_shift = 7, + .ss_pol_shift = 8, + .max_data_rate = 0x10, + .data_mask = 0x1F, + .data_shift = 14, + .lbc = (1 << 14), + .rx_cnt_off = 4, + .rx_cnt_mask = (0xF << 4), + .reset_start = 1, +}; + +extern void gpio_spi_active(int cspi_mod); +extern void gpio_spi_inactive(int cspi_mod); + +#define MXC_SPI_BUF_RX(type) \ +void mxc_spi_buf_rx_##type(struct mxc_spi *master_drv_data, u32 val)\ +{\ + type *rx = master_drv_data->transfer.rx_buf;\ + *rx++ = (type)val;\ + master_drv_data->transfer.rx_buf = rx;\ +} + +#define MXC_SPI_BUF_TX(type) \ +u32 mxc_spi_buf_tx_##type(struct mxc_spi *master_drv_data)\ +{\ + u32 val;\ + const type *tx = master_drv_data->transfer.tx_buf;\ + val = *tx++;\ + master_drv_data->transfer.tx_buf = tx;\ + return val;\ +} + +MXC_SPI_BUF_RX(u8) + MXC_SPI_BUF_TX(u8) + MXC_SPI_BUF_RX(u16) + MXC_SPI_BUF_TX(u16) + MXC_SPI_BUF_RX(u32) + MXC_SPI_BUF_TX(u32) + +int mxc_spi_suspended = 0; +EXPORT_SYMBOL(mxc_spi_suspended); + +/*! + * This function enables CSPI interrupt(s) + * + * @param master_data the pointer to mxc_spi structure + * @param irqs the irq(s) to set (can be a combination) + * + * @return This function returns 0 if successful, -1 otherwise. + */ +static int spi_enable_interrupt(struct mxc_spi *master_data, unsigned int irqs) +{ + if (irqs & ~((1 << master_data->spi_ver_def->intr_bit_shift) - 1)) { + return -1; + } + + __raw_writel((irqs | __raw_readl(MXC_CSPIINT + master_data->ctrl_addr)), + MXC_CSPIINT + master_data->ctrl_addr); + return 0; +} + +/*! + * This function disables CSPI interrupt(s) + * + * @param master_data the pointer to mxc_spi structure + * @param irqs the irq(s) to reset (can be a combination) + * + * @return This function returns 0 if successful, -1 otherwise. + */ +static int spi_disable_interrupt(struct mxc_spi *master_data, unsigned int irqs) +{ + if (irqs & ~((1 << master_data->spi_ver_def->intr_bit_shift) - 1)) { + return -1; + } + + __raw_writel((~irqs & + __raw_readl(MXC_CSPIINT + master_data->ctrl_addr)), + MXC_CSPIINT + master_data->ctrl_addr); + return 0; +} + +/*! + * This function sets the baud rate for the SPI module. + * + * @param master_data the pointer to mxc_spi structure + * @param baud the baud rate + * + * @return This function returns the baud rate divisor. + */ +static unsigned int spi_find_baudrate(struct mxc_spi *master_data, + unsigned int baud) +{ + unsigned int divisor; + unsigned int shift = 0; + + /* Calculate required divisor (rounded) */ + divisor = (master_data->spi_ipg_clk + baud / 2) / baud; + while (divisor >>= 1) + shift++; + + if (master_data->spi_ver_def == &spi_ver_0_0) { + shift = (shift - 1) * 2; + } else if (master_data->spi_ver_def == &spi_ver_2_3) { + shift = shift; + } else { + shift -= 2; + } + + if (shift > master_data->spi_ver_def->max_data_rate) + shift = master_data->spi_ver_def->max_data_rate; + + return (shift << master_data->spi_ver_def->data_shift); +} + +/*! + * This function loads the transmit fifo. + * + * @param base the CSPI base address + * @param count number of words to put in the TxFIFO + * @param master_drv_data spi master structure + */ +static void spi_put_tx_data(void *base, unsigned int count, + struct mxc_spi *master_drv_data) +{ + unsigned int ctrl_reg; + unsigned int data; + int i = 0; + + /* Perform Tx transaction */ + for (i = 0; i < count; i++) { + data = master_drv_data->transfer.tx_get(master_drv_data); + __raw_writel(data, base + MXC_CSPITXDATA); + } + + ctrl_reg = __raw_readl(base + MXC_CSPICTRL); + + ctrl_reg |= master_drv_data->spi_ver_def->xch; + + __raw_writel(ctrl_reg, base + MXC_CSPICTRL); + + return; +} + +/*! + * This function configures the hardware CSPI for the current SPI device. + * It sets the word size, transfer mode, data rate for this device. + * + * @param spi the current SPI device + * @param is_active indicates whether to active/deactivate the current device + */ +void mxc_spi_chipselect(struct spi_device *spi, int is_active) +{ + struct mxc_spi *master_drv_data; + struct mxc_spi_xfer *ptransfer; + struct mxc_spi_unique_def *spi_ver_def; + unsigned int ctrl_reg = 0; + unsigned int config_reg = 0; + unsigned int xfer_len; + + if (is_active == BITBANG_CS_INACTIVE) { + /*Need to deselect the slave */ + return; + } + + /* Get the master controller driver data from spi device's master */ + + master_drv_data = spi_master_get_devdata(spi->master); + clk_enable(master_drv_data->clk); + spi_ver_def = master_drv_data->spi_ver_def; + + xfer_len = spi->bits_per_word; + + if (spi_ver_def == &spi_ver_2_3) { + /* Control Register Settings for transfer to this slave */ + ctrl_reg = master_drv_data->spi_ver_def->spi_enable; + ctrl_reg |= + ((spi->chip_select & MXC_CSPICTRL_CSMASK) << spi_ver_def-> + cs_shift); + ctrl_reg |= + (((1 << (spi->chip_select & MXC_CSPICTRL_CSMASK)) & + spi_ver_def->mode_mask) << spi_ver_def->mode_shift); + ctrl_reg |= + spi_find_baudrate(master_drv_data, spi->max_speed_hz); + ctrl_reg |= + (((xfer_len - + 1) & spi_ver_def->bc_mask) << spi_ver_def->bc_shift); + + if (spi->mode & SPI_CPHA) + config_reg |= + (((1 << (spi->chip_select & MXC_CSPICTRL_CSMASK)) & + spi_ver_def->mode_mask) << + spi_ver_def->pha_shift); + + if ((spi->mode & SPI_CPOL)) { + config_reg |= + (((1 << (spi->chip_select & MXC_CSPICTRL_CSMASK)) & + spi_ver_def->mode_mask) << + spi_ver_def->low_pol_shift); + config_reg |= + (((1 << (spi->chip_select & MXC_CSPICTRL_CSMASK)) & + spi_ver_def->mode_mask) << + spi_ver_def->sclk_ctl_shift); + } + if (spi->mode & SPI_CS_HIGH) + config_reg |= + (((1 << (spi->chip_select & MXC_CSPICTRL_CSMASK)) & + spi_ver_def->mode_mask) << + spi_ver_def->ss_pol_shift); + config_reg |= + (((1 << (spi->chip_select & MXC_CSPICTRL_CSMASK)) & + spi_ver_def->mode_mask) << spi_ver_def->ss_ctrl_shift); + + __raw_writel(ctrl_reg, master_drv_data->base + MXC_CSPICTRL); + __raw_writel(config_reg, + MXC_CSPICONFIG + master_drv_data->ctrl_addr); + } else { + /* Control Register Settings for transfer to this slave */ + ctrl_reg = master_drv_data->spi_ver_def->spi_enable; + ctrl_reg |= + (((spi->chip_select & MXC_CSPICTRL_CSMASK) << spi_ver_def-> + cs_shift) | spi_ver_def->mode_mask << + spi_ver_def->mode_shift); + ctrl_reg |= + spi_find_baudrate(master_drv_data, spi->max_speed_hz); + ctrl_reg |= + (((xfer_len - + 1) & spi_ver_def->bc_mask) << spi_ver_def->bc_shift); + if (spi->mode & SPI_CPHA) + ctrl_reg |= + spi_ver_def->mode_mask << spi_ver_def->pha_shift; + if (!(spi->mode & SPI_CPOL)) + ctrl_reg |= + spi_ver_def->mode_mask << spi_ver_def-> + low_pol_shift; + if (spi->mode & SPI_CS_HIGH) + ctrl_reg |= + spi_ver_def->mode_mask << spi_ver_def->ss_pol_shift; + if (spi_ver_def == &spi_ver_0_7) + ctrl_reg |= + spi_ver_def->mode_mask << spi_ver_def-> + ss_ctrl_shift; + + __raw_writel(ctrl_reg, master_drv_data->base + MXC_CSPICTRL); + } + + /* Initialize the functions for transfer */ + ptransfer = &master_drv_data->transfer; + if (xfer_len <= 8) { + ptransfer->rx_get = mxc_spi_buf_rx_u8; + ptransfer->tx_get = mxc_spi_buf_tx_u8; + } else if (xfer_len <= 16) { + ptransfer->rx_get = mxc_spi_buf_rx_u16; + ptransfer->tx_get = mxc_spi_buf_tx_u16; + } else { + ptransfer->rx_get = mxc_spi_buf_rx_u32; + ptransfer->tx_get = mxc_spi_buf_tx_u32; + } +#ifdef CONFIG_SPI_MXC_TEST_LOOPBACK + { + struct spi_chip_info *lb_chip = + (struct spi_chip_info *)spi->controller_data; + if (!lb_chip) + __raw_writel(0, master_drv_data->test_addr); + else if (lb_chip->lb_enable) + __raw_writel(spi_ver_def->lbc, + master_drv_data->test_addr); + } +#endif + clk_disable(master_drv_data->clk); + return; +} + +/*! + * This function is called when an interrupt occurs on the SPI modules. + * It is the interrupt handler for the SPI modules. + * + * @param irq the irq number + * @param dev_id the pointer on the device + * + * @return The function returns IRQ_HANDLED when handled. + */ +static irqreturn_t mxc_spi_isr(int irq, void *dev_id) +{ + struct mxc_spi *master_drv_data = dev_id; + irqreturn_t ret = IRQ_NONE; + unsigned int status; + int fifo_size; + unsigned int pass_counter; + + fifo_size = master_drv_data->spi_ver_def->fifo_size; + pass_counter = fifo_size; + + /* Read the interrupt status register to determine the source */ + status = __raw_readl(master_drv_data->stat_addr); + do { + u32 rx_tmp = + __raw_readl(master_drv_data->base + MXC_CSPIRXDATA); + + if (master_drv_data->transfer.rx_buf) + master_drv_data->transfer.rx_get(master_drv_data, + rx_tmp); + (master_drv_data->transfer.count)--; + (master_drv_data->transfer.rx_count)--; + ret = IRQ_HANDLED; + if (pass_counter-- == 0) { + break; + } + status = __raw_readl(master_drv_data->stat_addr); + } while (status & + (1 << + (MXC_CSPISTAT_RR + + master_drv_data->spi_ver_def->int_status_dif))); + + if (master_drv_data->transfer.rx_count) + return ret; + + if (master_drv_data->transfer.count) { + if (master_drv_data->transfer.tx_buf) { + u32 count = (master_drv_data->transfer.count > + fifo_size) ? fifo_size : + master_drv_data->transfer.count; + master_drv_data->transfer.rx_count = count; + spi_put_tx_data(master_drv_data->base, count, + master_drv_data); + } + } else { + complete(&master_drv_data->xfer_done); + } + + return ret; +} + +/*! + * This function initialize the current SPI device. + * + * @param spi the current SPI device. + * + */ +int mxc_spi_setup(struct spi_device *spi) +{ + if (spi->max_speed_hz < 0) { + return -EINVAL; + } + + if (!spi->bits_per_word) + spi->bits_per_word = 8; + + pr_debug("%s: mode %d, %u bpw, %d hz\n", __FUNCTION__, + spi->mode, spi->bits_per_word, spi->max_speed_hz); + + return 0; +} + +/*! + * This function is called when the data has to transfer from/to the + * current SPI device in poll mode + * + * @param spi the current spi device + * @param t the transfer request - read/write buffer pairs + * + * @return Returns 0 on success. + */ +int mxc_spi_poll_transfer(struct spi_device *spi, struct spi_transfer *t) +{ + struct mxc_spi *master_drv_data = NULL; + int count, i; + volatile unsigned int status; + u32 rx_tmp; + u32 fifo_size; + + mxc_spi_chipselect(spi, BITBANG_CS_ACTIVE); + + /* Get the master controller driver data from spi device's master */ + master_drv_data = spi_master_get_devdata(spi->master); + + clk_enable(master_drv_data->clk); + + /* Modify the Tx, Rx, Count */ + master_drv_data->transfer.tx_buf = t->tx_buf; + master_drv_data->transfer.rx_buf = t->rx_buf; + master_drv_data->transfer.count = t->len; + fifo_size = master_drv_data->spi_ver_def->fifo_size; + + count = (t->len > fifo_size) ? fifo_size : t->len; + spi_put_tx_data(master_drv_data->base, count, master_drv_data); + + while ((((status = __raw_readl(master_drv_data->test_addr)) & + master_drv_data->spi_ver_def->rx_cnt_mask) >> master_drv_data-> + spi_ver_def->rx_cnt_off) != count) ; + + for (i = 0; i < count; i++) { + rx_tmp = __raw_readl(master_drv_data->base + MXC_CSPIRXDATA); + master_drv_data->transfer.rx_get(master_drv_data, rx_tmp); + } + + clk_disable(master_drv_data->clk); + + return 0; +} + +/*! + * This function is called when the data has to transfer from/to the + * current SPI device. It enables the Rx interrupt, initiates the transfer. + * When Rx interrupt occurs, the completion flag is set. It then disables + * the Rx interrupt. + * + * @param spi the current spi device + * @param t the transfer request - read/write buffer pairs + * + * @return Returns 0 on success -1 on failure. + */ +int mxc_spi_transfer(struct spi_device *spi, struct spi_transfer *t) +{ + struct mxc_spi *master_drv_data = NULL; + int count; + u32 fifo_size; + + /* Get the master controller driver data from spi device's master */ + + master_drv_data = spi_master_get_devdata(spi->master); + + clk_enable(master_drv_data->clk); + /* Modify the Tx, Rx, Count */ + master_drv_data->transfer.tx_buf = t->tx_buf; + master_drv_data->transfer.rx_buf = t->rx_buf; + master_drv_data->transfer.count = t->len; + fifo_size = master_drv_data->spi_ver_def->fifo_size; + INIT_COMPLETION(master_drv_data->xfer_done); + + /* Enable the Rx Interrupts */ + + spi_enable_interrupt(master_drv_data, + 1 << (MXC_CSPIINT_RREN_SHIFT + + master_drv_data->spi_ver_def->rx_inten_dif)); + count = (t->len > fifo_size) ? fifo_size : t->len; + + /* Perform Tx transaction */ + master_drv_data->transfer.rx_count = count; + spi_put_tx_data(master_drv_data->base, count, master_drv_data); + + /* Wait for transfer completion */ + wait_for_completion(&master_drv_data->xfer_done); + + /* Disable the Rx Interrupts */ + + spi_disable_interrupt(master_drv_data, + 1 << (MXC_CSPIINT_RREN_SHIFT + + master_drv_data->spi_ver_def-> + rx_inten_dif)); + + clk_disable(master_drv_data->clk); + return (t->len - master_drv_data->transfer.count); +} + +/*! + * This function releases the current SPI device's resources. + * + * @param spi the current SPI device. + * + */ +void mxc_spi_cleanup(struct spi_device *spi) +{ +} + +/*! + * This function is called during the driver binding process. Based on the CSPI + * hardware module that is being probed this function adds the appropriate SPI module + * structure in the SPI core driver. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions. + * + * @return The function returns 0 on successful registration and initialization + * of CSPI module. Otherwise returns specific error code. + */ +static int mxc_spi_probe(struct platform_device *pdev) +{ + struct mxc_spi_master *mxc_platform_info; + struct spi_master *master; + struct mxc_spi *master_drv_data = NULL; + unsigned int spi_ver; + int ret = -ENODEV; + + /* Get the platform specific data for this master device */ + + mxc_platform_info = (struct mxc_spi_master *)pdev->dev.platform_data; + if (!mxc_platform_info) { + dev_err(&pdev->dev, "can't get the platform data for CSPI\n"); + return -EINVAL; + } + + /* Allocate SPI master controller */ + + master = spi_alloc_master(&pdev->dev, sizeof(struct mxc_spi)); + if (!master) { + dev_err(&pdev->dev, "can't alloc for spi_master\n"); + return -ENOMEM; + } + + /* Set this device's driver data to master */ + + platform_set_drvdata(pdev, master); + + /* Set this master's data from platform_info */ + + master->bus_num = pdev->id + 1; + master->num_chipselect = mxc_platform_info->maxchipselect; +#ifdef CONFIG_SPI_MXC_TEST_LOOPBACK + master->num_chipselect += 1; +#endif + /* Set the master controller driver data for this master */ + + master_drv_data = spi_master_get_devdata(master); + master_drv_data->mxc_bitbang.master = spi_master_get(master); + + /* Identify SPI version */ + + spi_ver = mxc_platform_info->spi_version; + if (spi_ver == 7) { + master_drv_data->spi_ver_def = &spi_ver_0_7; + } else if (spi_ver == 5) { + master_drv_data->spi_ver_def = &spi_ver_0_5; + } else if (spi_ver == 4) { + master_drv_data->spi_ver_def = &spi_ver_0_4; + } else if (spi_ver == 0) { + master_drv_data->spi_ver_def = &spi_ver_0_0; + } else if (spi_ver == 23) { + master_drv_data->spi_ver_def = &spi_ver_2_3; + } + + dev_dbg(&pdev->dev, "SPI_REV 0.%d\n", spi_ver); + + /* Set the master bitbang data */ + + master_drv_data->mxc_bitbang.chipselect = mxc_spi_chipselect; + master_drv_data->mxc_bitbang.txrx_bufs = mxc_spi_transfer; + master_drv_data->mxc_bitbang.master->setup = mxc_spi_setup; + master_drv_data->mxc_bitbang.master->cleanup = mxc_spi_cleanup; + + /* Initialize the completion object */ + + init_completion(&master_drv_data->xfer_done); + + /* Set the master controller register addresses and irqs */ + + master_drv_data->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!master_drv_data->res) { + dev_err(&pdev->dev, "can't get platform resource for CSPI%d\n", + master->bus_num); + ret = -ENOMEM; + goto err; + } + + if (!request_mem_region(master_drv_data->res->start, + master_drv_data->res->end - + master_drv_data->res->start + 1, pdev->name)) { + dev_err(&pdev->dev, "request_mem_region failed for CSPI%d\n", + master->bus_num); + ret = -ENOMEM; + goto err; + } + + master_drv_data->base = (void *)IO_ADDRESS(master_drv_data->res->start); + if (!master_drv_data->base) { + dev_err(&pdev->dev, "invalid base address for CSPI%d\n", + master->bus_num); + ret = -EINVAL; + goto err1; + } + + master_drv_data->irq = platform_get_irq(pdev, 0); + if (!master_drv_data->irq) { + dev_err(&pdev->dev, "can't get IRQ for CSPI%d\n", + master->bus_num); + ret = -EINVAL; + goto err1; + } + + /* Register for SPI Interrupt */ + + ret = request_irq(master_drv_data->irq, mxc_spi_isr, + 0, "CSPI_IRQ", master_drv_data); + if (ret != 0) { + dev_err(&pdev->dev, "request_irq failed for CSPI%d\n", + master->bus_num); + goto err1; + } + + /* Setup any GPIO active */ + + gpio_spi_active(master->bus_num - 1); + + /* Enable the CSPI Clock, CSPI Module, set as a master */ + + master_drv_data->ctrl_addr = + master_drv_data->base + master_drv_data->spi_ver_def->ctrl_reg_addr; + master_drv_data->stat_addr = + master_drv_data->base + master_drv_data->spi_ver_def->stat_reg_addr; + master_drv_data->period_addr = + master_drv_data->base + + master_drv_data->spi_ver_def->period_reg_addr; + master_drv_data->test_addr = + master_drv_data->base + master_drv_data->spi_ver_def->test_reg_addr; + master_drv_data->reset_addr = + master_drv_data->base + + master_drv_data->spi_ver_def->reset_reg_addr; + + master_drv_data->clk = clk_get(&pdev->dev, "cspi_clk"); + clk_enable(master_drv_data->clk); + master_drv_data->spi_ipg_clk = clk_get_rate(master_drv_data->clk); + + __raw_writel(master_drv_data->spi_ver_def->reset_start, + master_drv_data->reset_addr); + udelay(1); + __raw_writel((master_drv_data->spi_ver_def->spi_enable + + master_drv_data->spi_ver_def->master_enable), + master_drv_data->base + MXC_CSPICTRL); + __raw_writel(MXC_CSPIPERIOD_32KHZ, master_drv_data->period_addr); + __raw_writel(0, MXC_CSPIINT + master_drv_data->ctrl_addr); + + /* Start the SPI Master Controller driver */ + + ret = spi_bitbang_start(&master_drv_data->mxc_bitbang); + + if (ret != 0) + goto err2; + + printk(KERN_INFO "CSPI: %s-%d probed\n", pdev->name, pdev->id); + +#ifdef CONFIG_SPI_MXC_TEST_LOOPBACK + { + int i; + struct spi_board_info *bi = &loopback_info[0]; + for (i = 0; i < ARRAY_SIZE(loopback_info); i++, bi++) { + if (bi->bus_num != master->bus_num) + continue; + + dev_info(&pdev->dev, + "registering loopback device '%s'\n", + bi->modalias); + + spi_new_device(master, bi); + } + } +#endif + clk_disable(master_drv_data->clk); + return ret; + + err2: + gpio_spi_inactive(master->bus_num - 1); + clk_disable(master_drv_data->clk); + clk_put(master_drv_data->clk); + free_irq(master_drv_data->irq, master_drv_data); + err1: + release_mem_region(pdev->resource[0].start, + pdev->resource[0].end - pdev->resource[0].start + 1); + err: + spi_master_put(master); + kfree(master); + platform_set_drvdata(pdev, NULL); + return ret; +} + +/*! + * Dissociates the driver from the SPI master controller. Disables the CSPI module. + * It handles the release of SPI resources like IRQ, memory,..etc. + * + * @param pdev the device structure used to give information on which SPI + * to remove + * + * @return The function always returns 0. + */ +static int mxc_spi_remove(struct platform_device *pdev) +{ + struct spi_master *master = platform_get_drvdata(pdev); + + if (master) { + struct mxc_spi *master_drv_data = + spi_master_get_devdata(master); + + gpio_spi_inactive(master->bus_num - 1); + + /* Disable the CSPI module */ + clk_enable(master_drv_data->clk); + __raw_writel(MXC_CSPICTRL_DISABLE, + master_drv_data->base + MXC_CSPICTRL); + clk_disable(master_drv_data->clk); + /* Unregister for SPI Interrupt */ + + free_irq(master_drv_data->irq, master_drv_data); + + release_mem_region(master_drv_data->res->start, + master_drv_data->res->end - + master_drv_data->res->start + 1); + + /* Stop the SPI Master Controller driver */ + + spi_bitbang_stop(&master_drv_data->mxc_bitbang); + + spi_master_put(master); + } + + printk(KERN_INFO "CSPI: %s-%d removed\n", pdev->name, pdev->id); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +#ifdef CONFIG_PM +static int spi_bitbang_suspend(struct spi_bitbang *bitbang) +{ + unsigned long flags; + unsigned limit = 500; + + spin_lock_irqsave(&bitbang->lock, flags); + while (!list_empty(&bitbang->queue) && limit--) { + spin_unlock_irqrestore(&bitbang->lock, flags); + + dev_dbg(&bitbang->master->dev, "wait for queue\n"); + msleep(10); + + spin_lock_irqsave(&bitbang->lock, flags); + } + if (!list_empty(&bitbang->queue)) { + dev_err(&bitbang->master->dev, "queue didn't empty\n"); + return -EBUSY; + } + spin_unlock_irqrestore(&bitbang->lock, flags); + + return 0; +} + +static void spi_bitbang_resume(struct spi_bitbang *bitbang) +{ + spin_lock_init(&bitbang->lock); + INIT_LIST_HEAD(&bitbang->queue); + + bitbang->busy = 0; +} + +/*! + * This function puts the SPI master controller in low-power mode/state. + * + * @param pdev the device structure used to give information on which SDHC + * to suspend + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int mxc_spi_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct spi_master *master = platform_get_drvdata(pdev); + struct mxc_spi *master_drv_data = spi_master_get_devdata(master); + int ret = 0; + + spi_bitbang_suspend(&master_drv_data->mxc_bitbang); + clk_enable(master_drv_data->clk); + __raw_writel(MXC_CSPICTRL_DISABLE, + master_drv_data->base + MXC_CSPICTRL); + clk_disable(master_drv_data->clk); + mxc_spi_suspended = 1; + + return ret; +} + +/*! + * This function brings the SPI master controller back from low-power state. + * + * @param pdev the device structure used to give information on which SDHC + * to resume + * + * @return The function always returns 0. + */ +static int mxc_spi_resume(struct platform_device *pdev) +{ + struct spi_master *master = platform_get_drvdata(pdev); + struct mxc_spi *master_drv_data = spi_master_get_devdata(master); + + spi_bitbang_resume(&master_drv_data->mxc_bitbang); + clk_enable(master_drv_data->clk); + __raw_writel(master_drv_data->spi_ver_def->spi_enable, + master_drv_data->base + MXC_CSPICTRL); + clk_disable(master_drv_data->clk); + mxc_spi_suspended = 0; + return 0; +} +#else +#define mxc_spi_suspend NULL +#define mxc_spi_resume NULL +#endif /* CONFIG_PM */ + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxc_spi_driver = { + .driver = { + .name = "mxc_spi", + .bus = &platform_bus_type, + .owner = THIS_MODULE, + }, + .probe = mxc_spi_probe, + .remove = mxc_spi_remove, + .suspend_late = mxc_spi_suspend, + .resume_early = mxc_spi_resume, +}; + +/*! + * This function implements the init function of the SPI device. + * It is called when the module is loaded. It enables the required + * clocks to CSPI module(if any) and activates necessary GPIO pins. + * + * @return This function returns 0. + */ +static int __init mxc_spi_init(void) +{ + pr_debug("Registering the SPI Controller Driver\n"); + return platform_driver_register(&mxc_spi_driver); +} + +/*! + * This function implements the exit function of the SPI device. + * It is called when the module is unloaded. It deactivates the + * the GPIO pin associated with CSPI hardware modules. + * + */ +static void __exit mxc_spi_exit(void) +{ + pr_debug("Unregistering the SPI Controller Driver\n"); + platform_driver_unregister(&mxc_spi_driver); +} + +subsys_initcall(mxc_spi_init); +module_exit(mxc_spi_exit); + +MODULE_DESCRIPTION("SPI Master Controller driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/usb/Kconfig linux-2.6.26-lab126/drivers/usb/Kconfig --- linux-2.6.26/drivers/usb/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/Kconfig 2010-08-10 04:17:12.000000000 -0400 @@ -105,6 +105,8 @@ source "drivers/usb/mon/Kconfig" +source "drivers/usb/usblan/Kconfig" + comment "USB port drivers" depends on USB diff -urN linux-2.6.26/drivers/usb/Makefile linux-2.6.26-lab126/drivers/usb/Makefile --- linux-2.6.26/drivers/usb/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/Makefile 2010-08-10 04:17:12.000000000 -0400 @@ -34,3 +34,6 @@ obj-$(CONFIG_USB_ATM) += atm/ obj-$(CONFIG_USB_SPEEDTOUCH) += atm/ + +obj-$(CONFIG_USB_OTG) += otg/ +obj-$(CONFIG_USB_USBLAN) += usblan/ diff -urN linux-2.6.26/drivers/usb/core/Kconfig linux-2.6.26-lab126/drivers/usb/core/Kconfig --- linux-2.6.26/drivers/usb/core/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/core/Kconfig 2010-08-10 04:17:08.000000000 -0400 @@ -103,11 +103,14 @@ If you are unsure about this, say N here. config USB_OTG - bool + bool "Enable host-side support for On-The-Go (OTG)" depends on USB && EXPERIMENTAL select USB_SUSPEND default n - + help + Say y here if you want support for the Host Negotiation Protocol + (HNP) and the Session Request Protocol (SRP), parts of the OTG + supplement to the USB protocol, to be included in the USB host core. config USB_OTG_WHITELIST bool "Rely on OTG Targeted Peripherals List" diff -urN linux-2.6.26/drivers/usb/core/devio.c linux-2.6.26-lab126/drivers/usb/core/devio.c --- linux-2.6.26/drivers/usb/core/devio.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/core/devio.c 2010-08-10 04:17:08.000000000 -0400 @@ -311,10 +311,11 @@ struct async *as = urb->context; struct dev_state *ps = as->ps; struct siginfo sinfo; + unsigned long flags; - spin_lock(&ps->lock); + spin_lock_irqsave(&ps->lock, flags); list_move_tail(&as->asynclist, &ps->async_completed); - spin_unlock(&ps->lock); + spin_unlock_irqrestore(&ps->lock, flags); as->status = urb->status; if (as->signr) { sinfo.si_signo = as->signr; diff -urN linux-2.6.26/drivers/usb/core/driver.c linux-2.6.26-lab126/drivers/usb/core/driver.c --- linux-2.6.26/drivers/usb/core/driver.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/core/driver.c 2010-08-10 04:17:08.000000000 -0400 @@ -26,9 +26,20 @@ #include #include #include +#include +#include + #include "hcd.h" #include "usb.h" +/* + * This is the usb_ahb_clk. If the clock is gated while a USB + * suspend is invoked, the controller will hang. + */ +struct clk *usb_clk; + +/* Track status of the usb_clk */ +static int clken = 0; #ifdef CONFIG_HOTPLUG @@ -790,6 +801,12 @@ udev->do_remote_wakeup = 0; udriver = &usb_generic_driver; } + + /* If the refcnt on the clock is > 0, then the clk is already enabled */ + if (!clk_get_usecount(usb_clk)) { + clk_enable(usb_clk); + clken++; + } status = udriver->suspend(udev, msg); done: @@ -814,6 +831,12 @@ goto done; } + /* Gate the usb_clk only if it was enabled on suspend */ + if (clken) { + clk_disable(usb_clk); + clken--; + } + if (udev->quirks & USB_QUIRK_RESET_RESUME) udev->reset_resume = 1; diff -urN linux-2.6.26/drivers/usb/core/hcd.c linux-2.6.26-lab126/drivers/usb/core/hcd.c --- linux-2.6.26/drivers/usb/core/hcd.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/core/hcd.c 2010-08-10 04:17:08.000000000 -0400 @@ -110,6 +110,11 @@ return (udev->parent == NULL); } +#if defined(CONFIG_USB_EHCI_ARC_H2_WAKE_UP) || \ + defined(CONFIG_USB_EHCI_ARC_OTG_WAKE_UP) +extern int usb_wakeup_irq(struct device *wkup_dev); +extern void usb_wakeup_set(struct device *wkup_dev, int para); +#endif /*-------------------------------------------------------------------------*/ /* @@ -1700,11 +1705,23 @@ * when the first handler doesn't use it. So let's just * assume it's never used. */ - local_irq_save(flags); - + local_irq_save_nort(flags); +#if defined(CONFIG_USB_EHCI_ARC_H2_WAKE_UP) || \ + defined(CONFIG_USB_EHCI_ARC_OTG_WAKE_UP) + /* if receive a remote wakeup interrrupt when suspend */ + if (usb_wakeup_irq(hcd->self.controller)) { + /* disable remote wake up irq */ + usb_wakeup_set(hcd->self.controller, 0); + set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + rc = hcd->driver->irq(hcd); + } else if (unlikely(hcd->state == HC_STATE_HALT || + !test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags))) { + rc = IRQ_NONE; +#else if (unlikely(hcd->state == HC_STATE_HALT || - !test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags))) { + !test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags))) { rc = IRQ_NONE; +#endif } else if (hcd->driver->irq(hcd) == IRQ_NONE) { rc = IRQ_NONE; } else { @@ -1715,7 +1732,7 @@ rc = IRQ_HANDLED; } - local_irq_restore(flags); + local_irq_restore_nort(flags); return rc; } diff -urN linux-2.6.26/drivers/usb/core/hub.c linux-2.6.26-lab126/drivers/usb/core/hub.c --- linux-2.6.26/drivers/usb/core/hub.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/core/hub.c 2010-08-10 04:17:08.000000000 -0400 @@ -1068,6 +1068,14 @@ desc = intf->cur_altsetting; hdev = interface_to_usbdev(intf); + /* With OTG enabled, suspending root hub results in gadget not + * working because gadget uses the same root hub. We disable + * this feature when OTG is selected. + */ +#if defined(CONFIG_PM) && defined(CONFIG_USB_EHCI_ARC_OTG) + hdev->autosuspend_disabled = 1; +#endif + #ifdef CONFIG_USB_OTG_BLACKLIST_HUB if (hdev->parent) { dev_warn(&intf->dev, "ignoring external hub\n"); diff -urN linux-2.6.26/drivers/usb/core/message.c linux-2.6.26-lab126/drivers/usb/core/message.c --- linux-2.6.26/drivers/usb/core/message.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/core/message.c 2010-08-10 04:17:08.000000000 -0400 @@ -266,8 +266,9 @@ { struct usb_sg_request *io = urb->context; int status = urb->status; + unsigned long flags; - spin_lock(&io->lock); + spin_lock_irqsave (&io->lock, flags); /* In 2.5 we require hcds' endpoint queues not to progress after fault * reports, until the completion callback (this!) returns. That lets @@ -301,7 +302,7 @@ * unlink pending urbs so they won't rx/tx bad data. * careful: unlink can sometimes be synchronous... */ - spin_unlock(&io->lock); + spin_unlock_irqrestore (&io->lock, flags); for (i = 0, found = 0; i < io->entries; i++) { if (!io->urbs [i] || !io->urbs [i]->dev) continue; @@ -316,7 +317,7 @@ } else if (urb == io->urbs [i]) found = 1; } - spin_lock(&io->lock); + spin_lock_irqsave (&io->lock, flags); } urb->dev = NULL; @@ -326,7 +327,7 @@ if (!io->count) complete(&io->complete); - spin_unlock(&io->lock); + spin_unlock_irqrestore (&io->lock, flags); } @@ -593,7 +594,7 @@ int i; io->status = -ECONNRESET; - spin_unlock(&io->lock); + spin_unlock_irqrestore(&io->lock, flags); for (i = 0; i < io->entries; i++) { int retval; @@ -604,7 +605,7 @@ dev_warn(&io->dev->dev, "%s, unlink --> %d\n", __func__, retval); } - spin_lock(&io->lock); + spin_lock_irqsave(&io->lock, flags); } spin_unlock_irqrestore(&io->lock, flags); } diff -urN linux-2.6.26/drivers/usb/gadget/Kconfig linux-2.6.26-lab126/drivers/usb/gadget/Kconfig --- linux-2.6.26/drivers/usb/gadget/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/gadget/Kconfig 2010-08-10 04:17:11.000000000 -0400 @@ -79,6 +79,23 @@ Enable these files by choosing "Y" here. If in doubt, or to conserve kernel memory, say "N". +config USB_GADGET_VBUS_DRAW + int "Maximum VBUS Power usage (2-500 mA)" + range 2 500 + default 500 + help + Some devices need to draw power from USB when they are + configured, perhaps to operate circuitry or to recharge + batteries. This is in addition to any local power supply, + such as an AC adapter or batteries. + + Enter the maximum power your device draws through USB, in + milliAmperes. The permitted range of values is 2 - 500 mA; + 0 mA would be legal, but can make some hosts misbehave. + + This value will be used except for system-specific gadget + drivers that have more specific information. + config USB_GADGET_SELECTED boolean @@ -305,16 +322,29 @@ default USB_GADGET select USB_GADGET_SELECTED -config USB_OTG - boolean "OTG Support" - depends on USB_GADGET_OMAP && ARCH_OMAP_OTG && USB_OHCI_HCD +config USB_GADGET_ARC + boolean "Freescale USB Device Controller" + depends on ARCH_MXC + select USB_GADGET_DUALSPEED if USB_GADGET_FSL_1504 || USB_GADGET_FSL_UTMI help - The most notable feature of USB OTG is support for a - "Dual-Role" device, which can act as either a device - or a host. The initial role choice can be changed - later, when two dual-role devices talk to each other. + Some Freescale processors have a USBOTG controller, + which supports device mode. - Select this only if your OMAP board has a Mini-AB connector. + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "arc_udc" and force all + gadget drivers to also be dynamically linked. + +config USB_STATIC_IRAM_PPH + bool "Apply static IRAM patch" + depends on USB_GADGET_ARC && (ARCH_MX37 || ARCH_MX3 || ARCH_MX35) + help + Apply static IRAM patch to peripheral driver. + +config USB_ARC + tristate + depends on USB_GADGET_ARC + default USB_GADGET + select USB_GADGET_SELECTED config USB_GADGET_S3C2410 boolean "S3C2410 USB Device Controller" @@ -389,6 +419,19 @@ endchoice +config USB_OTG + boolean "OTG Support" + depends on (USB_GADGET_OMAP && ARCH_OMAP_OTG && USB_OHCI_HCD) || \ + (USB_GADGET_ARC && (ARCH_MX3 || ARCH_MX27 || ARCH_MXC91221) && \ + USB_EHCI_HCD) + help + The most notable feature of USB OTG is support for a + "Dual-Role" device, which can act as either a device + or a host. The initial role choice can be changed + later, when two dual-role devices talk to each other. + + Select this only if your board has a Mini-AB connector. + config USB_GADGET_DUALSPEED bool depends on USB_GADGET @@ -397,6 +440,63 @@ Means that gadget drivers should include extra descriptors and code to handle dual-speed controllers. +config USB_GADGET_ARC_OTG + bool "Support for DR peripheral port on Freescale controller" + depends on USB_GADGET_ARC + default y + help + Enable support for the Freescale Dual Role port in peripheral mode. + +config USB_GADGET_WAKE_UP + bool "Support gadget wake up by DR port" + depends on USB_GADGET_ARC_OTG + default n + help + Enable system wake up from SR or DSM mode by connected host. +choice + prompt "Select transceiver for DR port" + depends on USB_GADGET_ARC_OTG + help + Choose the transceiver to use with the Freescale DR port. + +config USB_GADGET_FSL_MC13783 + bool "Freescale MC13783" + depends on !USB_EHCI_FSL_1301 && !USB_EHCI_FSL_1504 && !USB_EHCI_FSL_UTMI && !MACH_MX25_3DS + ---help--- + Enable support for the Full Speed Freescale MC13783 transceiver. + + The mx27ads, mx31ads and mx32ads boards require modifications + to support this transceiver. + +config USB_GADGET_FSL_1301 + bool "Philips ISP1301" + depends on !USB_EHCI_FSL_MC13783 && !USB_EHCI_FSL_1504 && !USB_EHCI_FSL_UTMI && !MACH_MX25_3DS + ---help--- + Enable support for the Full Speed Philips ISP1301 transceiver. + + This is the factory default for the mx27ads board. + The mx31ads and mx32ads boards require modifications + to support this transceiver. + +config USB_GADGET_FSL_1504 + bool "Philips ISP1504" + depends on !USB_EHCI_FSL_MC13783 && !USB_EHCI_FSL_1301 && !USB_EHCI_FSL_UTMI && !MACH_MX25_3DS + ---help--- + Enable support for the High Speed Philips ISP1504 transceiver. + + This is the factory default for the mx31ads and mx32ads boards. + The mx27ads board requires modifications to support this transceiver. + +config USB_GADGET_FSL_UTMI + bool "On-chip UTMI" + depends on !USB_EHCI_FSL_MC13783 && !USB_EHCI_FSL_1301 && !USB_EHCI_FSL_1504 + ---help--- + Enable support for the High Speed Philips ISP1504 transceiver. + + This is the factory default for the mx35 board. + +endchoice + # # USB Gadget Drivers # @@ -448,7 +548,7 @@ config USB_ZERO_HNPTEST boolean "HNP Test Device" - depends on USB_ZERO && USB_OTG + depends on USB_ZERO && USB_OTG2 help You can configure this device to enumerate using the device identifiers of the USB-OTG test device. That means that when diff -urN linux-2.6.26/drivers/usb/gadget/Makefile linux-2.6.26-lab126/drivers/usb/gadget/Makefile --- linux-2.6.26/drivers/usb/gadget/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/gadget/Makefile 2010-08-10 04:17:11.000000000 -0400 @@ -18,6 +18,7 @@ obj-$(CONFIG_USB_ATMEL_USBA) += atmel_usba_udc.o obj-$(CONFIG_USB_FSL_USB2) += fsl_usb2_udc.o obj-$(CONFIG_USB_M66592) += m66592-udc.o +obj-$(CONFIG_USB_ARC) += arcotg_udc.o # # USB gadget drivers @@ -27,8 +28,7 @@ g_serial-objs := serial.o usbstring.o config.o epautoconf.o g_midi-objs := gmidi.o usbstring.o config.o epautoconf.o gadgetfs-objs := inode.o -g_file_storage-objs := file_storage.o usbstring.o config.o \ - epautoconf.o +g_file_storage-objs := file_storage.o g_printer-objs := printer.o usbstring.o config.o \ epautoconf.o diff -urN linux-2.6.26/drivers/usb/gadget/arcotg_udc.c linux-2.6.26-lab126/drivers/usb/gadget/arcotg_udc.c --- linux-2.6.26/drivers/usb/gadget/arcotg_udc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/usb/gadget/arcotg_udc.c 2010-09-02 21:21:01.000000000 -0400 @@ -0,0 +1,4945 @@ +/* + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2009-2010 Amazon Technologies Inc. All Rights Reserved. + * Manish Lachwani (lachwani@lab126.com). + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#undef DEBUG +#undef VERBOSE + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "arcotg_udc.h" +#include +#include +#include +#include + +#define DRIVER_DESC "ARC USBOTG Device Controller driver" +#define DRIVER_AUTHOR "Manish Lachwani" +#define DRIVER_VERSION "10/08/2009" + +#ifdef CONFIG_PPC_MPC512x +#define BIG_ENDIAN_DESC +#endif + +#ifdef BIG_ENDIAN_DESC +#define cpu_to_hc32(x) (x) +#define hc32_to_cpu(x) (x) +#else +#define cpu_to_hc32(x) cpu_to_le32((x)) +#define hc32_to_cpu(x) le32_to_cpu((x)) +#endif + +#define DMA_ADDR_INVALID (~(dma_addr_t)0) + +static const char driver_name[] = "fsl-usb2-udc"; +static const char driver_desc[] = DRIVER_DESC; + +volatile static struct usb_dr_device *dr_regs; +volatile static struct usb_sys_interface *usb_sys_regs; + +/* it is initialized in probe() */ +static struct fsl_udc *udc_controller; + +extern int luigi_voltage; +extern int luigi_battery_current; +extern int luigi_battery_id; +extern int luigi_battery_capacity; +extern int luigi_battery_present; +extern int luigi_battery_mAH; + +/* SPI Suspended? */ +extern int mxc_spi_suspended; + +extern void gpio_chrgled_active(int enable); +static const struct usb_endpoint_descriptor +fsl_ep0_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0, + .bmAttributes = USB_ENDPOINT_XFER_CONTROL, + .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD, +}; + +static const struct usb_endpoint_descriptor +fsl_ep1_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 1, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = 512, +}; + +static const size_t g_iram_size = IRAM_TD_PPH_SIZE; +DEFINE_SPINLOCK(udc_pm_lock); + +static void resume_ctrl(void); +static int udc_suspend(struct fsl_udc *udc); +static int fsl_udc_suspend(struct device *dev, pm_message_t state); +static int fsl_udc_resume(struct device *dev); +static void fsl_ep_fifo_flush(struct usb_ep *_ep); +static int green_led_set = 0; +static int udc_detection = 0; +static int saved_ichrg_value = 0; +static int udc_stopped = 0; +static int lobat_condition = 0; +static int charger_timer_expiry_counter = 0; +static int fsl_vbus_done = 0; + +static int first_battery_reading = 0; +static int next_battery_reading = 0; +static struct timeval first_battery_time; + +/* port change work */ +static void port_change_work(struct work_struct *work); +DECLARE_DELAYED_WORK(pc_wq, port_change_work); + +/* PHY Low power work */ +static void phy_low_power_resume(struct work_struct *work); +static DECLARE_DELAYED_WORK(phy_resume_work, phy_low_power_resume); + +static void resume_ctrl(void); +static void suspend_ctrl(void); +static void fsl_udc_redo_enumerate(void); + +/* Accessory callbacks */ +extern void enable_accessory_gpo4(void); +extern void disable_accessory_gpo4(void); + +#if defined(CONFIG_CPU_FREQ) + +/* CPUFReq callbacks */ +extern void disable_cpufreq(void); +extern void enable_cpufreq(void); + +#endif + +#ifdef CONFIG_USB_OTG +/* Get platform resource from OTG driver */ +extern struct resource *otg_get_resources(void); +#endif + +#ifdef CONFIG_PPC32 +#define fsl_readl(addr) in_le32((addr)) +#define fsl_writel(addr, val32) out_le32((val32), (addr)) +#else +#define fsl_readl(addr) readl((addr)) +#define fsl_writel(addr, val32) writel((addr), (val32)) +#endif + +/* + * Charger + */ +static pmic_event_callback_t charger_detect; +static pmic_event_callback_t lobatli_event; +static pmic_event_callback_t lobathi_event; +static pmic_event_callback_t bpon_event; +static pmic_event_callback_t chgfaulti_event; + +static int pmic_set_chg_current(unsigned short curr); +static void pmic_enable_green_led(int enable); + +static struct clk *usb_ahb_clk; +static void fsl_idle_low_power_exit(struct fsl_udc *udc); +static void fsl_idle_low_power_enter(struct fsl_udc *udc); +static void fsl_detect_charger_type(void); +static int not_detected = 0; +static int host_detected = 0; /* Has a host been detected? */ +static void pmic_start_charging(int value); + +static int udc_suspended_mode = 0; /* gadget driver suspended state */ + +#define VBUSVALIDS 0x08 /* Sense bit for valid VBUS */ +#define CHGDETS 0x40 /* Sense bit for CHGDET */ +#define CHGCURRS 0x800 /* Bit #11 */ +#define CHGCURRS_THRESHOLD 4100 /* CHGCURRS Threshold */ +#define PC_WORK_THRESHOLD 30000 /* Port change threshold */ +#define ARCOTG_IRQ 37 +#define CHARGER_STARTUP 4000 /* Delayed workqueue that runs on startup */ +#define CHARGER_MISC 10000 /* Charger misc timer */ +#define CHARGER_TYPE 1000 /* Charger type detection after 1 second */ +#define CHARGER_TYPE_REMOVE 10000 /* After ejected */ +#define CHARGER_CHARGER_REMOVE 1000 /* Non-host */ +#define CHARGER_TYPE_SUSPEND 5000 /* Charger detection after a system resume */ +#define PHY_LPM_TIMER 20000 /* 20 seconds after resume */ +#define THIRD_PARTY_DETECT 30000 /* Third Party charger detect */ +#define HOST_ENU_DETECT 100 /* Host enumeration check */ +#define BATT_VOLTAGE_SCALE 4687 /* Scale the values from the ADC based on manual */ +#define BATT_CURRENT_SCALE 5865 /* Scale the current read from the ADC */ +#define CHARGE_VOLTAGE_SCALE 11700 /* Scale the charger voltage read from A/D */ +#define CHARGING_HOST 0x1 /* Host charging with PHY active */ +#define CHARGING_WALL 0xA /* Wall charging */ +#define CHARGING_THIRD_PARTY 0x5 /* Third party chargers */ +#define CHARGER_FULL 0x1 /* 80mA */ +#define BPSNS_VALUE 0x2 /* For LOBATHI and LOBATLI */ +#define BPSNS_VALUE_SUSPEND 0x3 /* Suspend - LOBATHI and LOBATLI */ +#define BPSNS_MASK 0x3 /* BPSNS Mask in PMIC reg 13 */ +#define BPSNS_VOLTAGE_THRESH 3600 /* 3.6V BPSNS threshold */ +#define PMIC_REG_PC_0 13 /* PMIC Register 13 */ +#define BPSNS_OFFSET 16 /* BPSNS OFFSET in Register 13 */ +#define GREEN_LED_THRESHOLD 90 /* Turn Charge LED to Green */ +#define BATTCYCL_THRESHOLD 4105 /* Restart charging if not done automatically */ +#define CHRGLEDEN 18 /* offset 18 in REG_CHARGE */ +#define CHRGCYCLB 22 /* BATTCYCL to restart charging at 95% full */ +#define CHRGRESTART 20 /* Restart charging */ +#define BPON_THRESHOLD 3800 +#define BPON_THRESHOLD_HI 3810 +#define CHARGING_BPON 0x3 /* 320mA charging */ +#define CHARGER_TURN_ON 3400 +#define CHRGRAW_THRESHOLD 6000 +#define CRAW_MON_THREHOLD 6 /* Every 60 seconds or so, monitor the chrgraw */ +#define CHRG_SUS_LOW_VOLTAGE 3420 /* 3.42V */ +#define CHARGER_BOOT_THRESHOLD 4 + +#define BIT_CHG_CURR_LSH 3 +#define BIT_CHG_CURR_WID 4 + +#define BIT_CHG_CURRS_LSH 11 +#define BIT_CHG_CURRS_WID 1 + +#define BAT_TH_CHECK_DIS_LSH 9 +#define BAT_TH_CHECK_DIS_WID 1 + +#define RESTART_CHG_STAT_LSH 20 +#define RESTART_CHG_STAT_WID 1 + +#define AUTO_CHG_DIS_LSH 21 +#define AUTO_CHG_DIS_WID 1 + +#define VI_PROGRAM_EN_LSH 23 +#define VI_PROGRAM_EN_WID 1 + +/* Battery current amplification from A/D */ +#define BAT_CURRENT_UNIT_UA 5870 + +enum chg_setting { + BAT_TH_CHECK_DIS, + RESTART_CHG_STAT, + AUTO_CHG_DIS, + VI_PROGRAM_EN +}; + +static int pmic_set_chg_misc(enum chg_setting type, unsigned short flag); + +#define LOW_VOLTAGE_THRESHOLD 3400 /* 3.4V */ +#define CRITICAL_VOLTAGE_THRESHOLD 3100 /* 3.1V */ +#define PMIC_IRQ 108 /* PMIC IRQ */ + +static int ichrg_value = 0; +static int charger_bpon = 0; +static int full_battery = 0; +static int crit_boot_flag = 0; + +/* Track multiple postings of lobat events to userspace */ +static int lobat_event_posted = 0; + +static atomic_t enumerated = ATOMIC_INIT(0); +static int wall_charger = 0; +static int third_party_charger = 0; /* Is it a non-Amazon charger? */ +static int charger_enumerated = 0; +static int charger_conn_probe = 0; /* Is charger connected on probe? */ +static int chrgraw_disable = 0; /* Is charging disabled due to chrgraw? */ +static int chrgraw_monitor = 0; /* Once every 60 seconds */ + +/* Configurable capacity threshold for Green LED */ +static int green_led_threshold = GREEN_LED_THRESHOLD; + +static int bpsns_value = BPSNS_VALUE; /* BPSNS = 0x3 at init */ + +/* Battery Error Flags */ +extern unsigned int luigi_battery_error_flags; + +static int read_supply_voltage(void); + +static void fsl_charger_type_detect(unsigned long data); + +static ssize_t +show_connected(struct device *dev, struct device_attribute *attr, char *buf); +static DEVICE_ATTR(connected, 0444, show_connected, NULL); + +static ssize_t +show_charging(struct device *dev, struct device_attribute *attr, char *buf); +static DEVICE_ATTR(charging, 0444, show_charging, NULL); + +static ssize_t +show_lobat_condition(struct device *dev, struct device_attribute *attr, char *buf); +static DEVICE_ATTR(lobat_condition, 0444, show_lobat_condition, NULL); + +static ssize_t +show_bpsns(struct device *dev, struct device_attribute *attr, char *buf); +static DEVICE_ATTR(bpsns, 0444, show_bpsns, NULL); + +static ssize_t +show_supply_voltage(struct device *dev, struct device_attribute *attr, char *buf); +static DEVICE_ATTR(supply_voltage, 0444, show_supply_voltage, NULL); + +static ssize_t +show_ichrg_setting(struct device *dev, struct device_attribute *attr, char *buf); +static DEVICE_ATTR(ichrg_setting, 0444, show_ichrg_setting, NULL); + +static ssize_t +show_voltage(struct device *dev, struct device_attribute *attr, char *buf); +static DEVICE_ATTR(voltage, 0444, show_voltage, NULL); + +static ssize_t +show_battery_current(struct device *dev, struct device_attribute *attr, char *buf); +static DEVICE_ATTR(battery_current, 0444, show_battery_current, NULL); + +static ssize_t +show_batt_error(struct device *dev, struct device_attribute *attr, char *buf); +static DEVICE_ATTR(batt_error, 0444, show_batt_error, NULL); + +static ssize_t +show_battery_id(struct device *dev, struct device_attribute *attr, char *buf); +static DEVICE_ATTR(battery_id, 0444, show_battery_id, NULL); + +static ssize_t +show_third_party(struct device *dev, struct device_attribute *attr, char *buf); +static DEVICE_ATTR(third_party, 0444, show_third_party, NULL); + +static ssize_t +show_charger_adc_voltage(struct device *dev, struct device_attribute *attr, char *buf); +static DEVICE_ATTR(charger_adc_voltage, 0444, show_charger_adc_voltage, NULL); + +static int read_charger_voltage(void); + +/******************************************************************** + * Internal Used Function +********************************************************************/ + +static void do_charger_detect_work(struct work_struct *work); + +#ifdef DUMP_QUEUES +static void dump_ep_queue(struct fsl_ep *ep) +{ + int ep_index; + struct fsl_req *req; + struct ep_td_struct *dtd; + + if (list_empty(&ep->queue)) { + pr_debug("udc: empty\n"); + return; + } + + ep_index = ep_index(ep) * 2 + ep_is_in(ep); + pr_debug("udc: ep=0x%p index=%d\n", ep, ep_index); + + list_for_each_entry(req, &ep->queue, queue) { + pr_debug("udc: req=0x%p dTD count=%d\n", req, req->dtd_count); + pr_debug("udc: dTD head=0x%p tail=0x%p\n", req->head, + req->tail); + + dtd = req->head; + + while (dtd) { + if (le32_to_cpu(dtd->next_td_ptr) & DTD_NEXT_TERMINATE) + break; /* end of dTD list */ + + dtd = dtd->next_td_virt; + } + } +} +#else +static inline void dump_ep_queue(struct fsl_ep *ep) +{ +} +#endif + +/* + * Is a charger connected? + */ +static int charger_connected(void) +{ + int sense_0 = 0; + int ret = 0; /* Default: no charger */ + + pmic_read_reg(REG_INT_SENSE0, &sense_0, 0xffffff); + if (sense_0 & CHGDETS) + ret = 1; + + return ret; +} + +/*! + * This function is used to determine if D+ and D- are floating + * or not. If the PORTSC1 is read for such a case, it will indicate + * that D+ and D- are shorted. + * + * In order to correctly determine this case, the UTMI PHY registers + * need to be accessed directly using the USB_PHY_CTR_FUNC register. + * Fields of interest: + * + * Vendor Control Address - VCTL_ADDR (bits 16-19) + * Vendor Control Data - VCTL_DATA (bits 8-15) + * Vendor Control Load - VCTL_LD (bit 20) + * Vendor Control Status - VSTS (bits 0-7) + * + * We want to access the UTMI PHY register 0x0 to enable the pullup on + * DP and then read the PORTSC1 register to determine the D+/D- float case. + * For such accesses to work, we will need to first make the controller operate + * in HOST mode and not DEVICE mode. To put the controller in HOST mode, stop + * the controller and reset it. Then, change the mode. + * + * Once the detection is finished, switch back to the original DEVICE mode. + */ +static int do_third_party_charger(void) +{ + unsigned int portsc1, tmp; + unsigned long timeout; + int charger = 0; + +#define FSL_UDC_RESET_TIMEOUT 1000 + + /* Stop and reset the usb controller */ + tmp = fsl_readl(&dr_regs->usbcmd); + tmp &= ~USB_CMD_RUN_STOP; + fsl_writel(tmp, &dr_regs->usbcmd); + + tmp = fsl_readl(&dr_regs->usbcmd); + tmp |= USB_CMD_CTRL_RESET; + fsl_writel(tmp, &dr_regs->usbcmd); + + /* Wait for reset to complete */ + timeout = jiffies + FSL_UDC_RESET_TIMEOUT; + while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) { + if (time_after(jiffies, timeout)) { + ERR("udc reset timeout! \n"); + return -ETIMEDOUT; + } + cpu_relax(); + } + + /* Set the controller as HOST mode */ + tmp = fsl_readl(&dr_regs->usbmode); + tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */ + tmp |= USB_MODE_CTRL_MODE_HOST; + + /* Disable Setup Lockout */ + tmp |= USB_MODE_SETUP_LOCK_OFF; + fsl_writel(tmp, &dr_regs->usbmode); + + /* Restart the controller */ + tmp = fsl_readl(&dr_regs->usbcmd); + tmp |= USB_CMD_RUN_STOP; + fsl_writel(tmp, &dr_regs->usbcmd); + + /* Let things settle down */ + mdelay(100); + + /* Disregard the clock accuracy */ + USB_PHY_CTR_FUNC2 = 0x02; + + /* + * The PHY that Freescale uses has the vendor control register + * at address 0x0, i.e. VCTL_ADDR=0x0 + */ + USB_PHY_CTR_FUNC &= 0xfff002ff; + + /* + * Put 0x2 in the vendor control register to enable pullup on + * DP, i.e. VCTL_DATA=0x2 + */ + USB_PHY_CTR_FUNC |= 0x00100200; + + /* + * Enable the load, i.e. VCTL_LOAD=0x0 + */ + USB_PHY_CTR_FUNC &= 0xfFE002ff; + + mdelay(100); + + /* + * Disable load, i.e. VCTL_LOAD=0x1 + */ + USB_PHY_CTR_FUNC |= 0xfff00200; + + /* Now read the PHY port register */ + portsc1 = fsl_readl(&dr_regs->portsc1); + + printk(KERN_INFO "do_third_party_charger: portsc1 = 0x%x\n", portsc1); + if ((portsc1 & PORTSCX_LINE_STATUS_BITS) == PORTSCX_LINE_STATUS_UNDEF) { + /* D+ and D- are shorted, hence charger */ + charger = 1; + } + + /* Clear Dp-pullup enable */ + USB_PHY_CTR_FUNC &= 0xfff000ff; + + /* Open latch */ + USB_PHY_CTR_FUNC &= 0xffe000ff; + + mdelay(10); + + /* Close latch */ + USB_PHY_CTR_FUNC |= 0x00100000; + + /* Re-enable the clock accuracy */ + USB_PHY_CTR_FUNC2 = 0x0; + + /* Stop and reset the usb controller */ + tmp = fsl_readl(&dr_regs->usbcmd); + tmp &= ~USB_CMD_RUN_STOP; + fsl_writel(tmp, &dr_regs->usbcmd); + + tmp = fsl_readl(&dr_regs->usbcmd); + tmp |= USB_CMD_CTRL_RESET; + fsl_writel(tmp, &dr_regs->usbcmd); + + /* Wait for reset to complete */ + timeout = jiffies + FSL_UDC_RESET_TIMEOUT; + while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) { + if (time_after(jiffies, timeout)) { + ERR("udc reset timeout! \n"); + return -ETIMEDOUT; + } + cpu_relax(); + } + + /* Set the controller as device mode */ + tmp = fsl_readl(&dr_regs->usbmode); + tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */ + tmp |= USB_MODE_CTRL_MODE_DEVICE; + + /* Disable Setup Lockout */ + tmp |= USB_MODE_SETUP_LOCK_OFF; + fsl_writel(tmp, &dr_regs->usbmode); + + tmp = fsl_readl(&dr_regs->usbcmd); + tmp |= USB_CMD_RUN_STOP; + fsl_writel(tmp, &dr_regs->usbcmd); + + mdelay(100); + + return charger; +} + +static void post_charger_work(int charger) +{ + if (charger) { + printk("Connected to a charger: %d\n", read_supply_voltage()); + pmic_start_charging(CHARGING_WALL); + wall_charger = 1; + } + else { + printk("Connected to a third-party: %d\n", read_supply_voltage()); + pmic_start_charging(CHARGING_THIRD_PARTY); + third_party_charger = 1; + } +} + +static int check_portsc_bits(void) +{ + unsigned int portsc1; + + resume_ctrl(); + mdelay(10); + + portsc1 = fsl_readl(&dr_regs->portsc1); + printk("check_portsc_bits: 0x%x\n", portsc1); + + if ((portsc1 & PORTSCX_LINE_STATUS_BITS) == PORTSCX_LINE_STATUS_UNDEF) { + /* Check if D+/D- are floating */ + post_charger_work(do_third_party_charger()); + + kobject_uevent_atomic(&udc_controller->gadget.dev.parent->kobj, KOBJ_ADD); + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_connected) < 0) + printk(KERN_ERR "Charger: Error creating device file\n"); + + return 1; + } + + return 0; +} + +/*! + * Unsubscribe charger events + */ +static void fsl_charger_unsub_events(int val) +{ + if (val) { + pmic_event_unsubscribe(EVENT_CHGDETI, charger_detect); + pmic_event_unsubscribe(EVENT_CHGFAULTI, chgfaulti_event); + } + else { + pmic_event_subscribe(EVENT_CHGDETI, charger_detect); + pmic_event_subscribe(EVENT_CHGFAULTI, chgfaulti_event); + } +} + +/* + * Kicked off only on startup to figure out whether a charger/host is + * connected or to enter low power idle mode. + */ +static void do_charger_detect_work(struct work_struct *work) +{ + struct fsl_udc *udc = + container_of(work, struct fsl_udc, charger_detect_work.work); + int charger_conn = charger_connected(); + + /* if module has been removed or suspended, do not do the detect */ + if (udc_suspended_mode) + return; + + if (!not_detected && charger_conn) { + if (charger_conn_probe == 1) { + charger_conn_probe = 0; + if (!check_portsc_bits()) + fsl_detect_charger_type(); + } + else + fsl_detect_charger_type(); + } + + if (!charger_conn) { + printk("No USB/Charger found ... entering low power idle\n"); + pmic_enable_green_led(0); + fsl_idle_low_power_enter(udc); + } +} + +static void pmic_green_led_disable(int flag) +{ + pmic_write_reg(REG_CHARGE, (flag << CHRGLEDEN), (1 << CHRGLEDEN)); +} + +static void pmic_enable_bpon_charging(void) +{ + /* Keep auto charging disabled */ + pmic_set_chg_misc(AUTO_CHG_DIS, 1); + + /* Turn on CHRGLED */ + pmic_write_reg(REG_CHARGE, (1 << 18), (1 << 18)); + + /* Yellow LED GPIO */ + gpio_chrgled_active(1); + + /* Turn on V & I programming */ + pmic_write_reg(REG_CHARGE, (1 << 23), (1 << 23)); + + /* Turn off TRICKLE CHARGE */ + pmic_write_reg(REG_CHARGE, (0 << 7), (1 << 7)); + + if (host_detected == 1) { + if (!atomic_read(&enumerated)) { + pmic_set_chg_current(CHARGING_HOST); + ichrg_value = CHARGING_HOST; + } + else { + pmic_set_chg_current(charger_enumerated); + ichrg_value = charger_enumerated; + } + } + else { + if (!wall_charger) { + pmic_set_chg_current(CHARGING_THIRD_PARTY); + ichrg_value = CHARGING_THIRD_PARTY; + } + else { + pmic_set_chg_current(CHARGING_WALL); + ichrg_value = CHARGING_WALL; + } + } + + /* PLIM: bits 15 and 16 */ + pmic_write_reg(REG_CHARGE, (0x2 << 15), (0x3 << 15)); + + /* PLIMDIS: bit 17 */ + pmic_write_reg(REG_CHARGE, (0 << 17), (1 << 17)); + + /* Restart charging */ + pmic_write_reg(REG_CHARGE, (1 << 20), (1 << 20)); +} + +static void pmic_restart_charging(void) +{ + /* Restart the charging process */ + pmic_write_reg(REG_CHARGE, (1 << CHRGRESTART), (1 << CHRGRESTART)); +} + +/*! + * Post a low battery or a critical battery event to the userspace + */ +static void post_lobat_event(int crit_level) +{ + /* If lobat has been already posted, don't repost */ + if (lobat_event_posted) { + return; + } + + /* First time posting */ + lobat_event_posted = 1; + + if (!crit_level) { + char *envp[] = { "BATTERY=low", NULL }; + printk(KERN_ERR "Charger: low battery event sent to userspace\n"); + + /* Relay the lobath event to userspace */ + kobject_uevent_env(&udc_controller->gadget.dev.parent->kobj, KOBJ_CHANGE, envp); + } + else { + char *envp[] = { "BATTERY=critical", NULL }; + printk(KERN_ERR "Charger: critical battery event sent to userspace\n"); + + /* Relay the lobatl event to userspace */ + kobject_uevent_env(&udc_controller->gadget.dev.parent->kobj, KOBJ_CHANGE, envp); + } + + printk(KERN_ERR "Charger: gasguage reported voltage: %dmV, Capacity: %d\n", + luigi_voltage, luigi_battery_capacity); + + /* Update the /sys entry */ + lobat_condition = 1; +} + +static int read_lobat_supply_voltage(void); + +/*! + * This function checks the charger over-voltage condition + */ +static void fsl_check_overvoltage(int charger_conn) +{ + unsigned int chrgraw = 0; + + /* Clear out the chrgraw monitor */ + chrgraw_monitor = 0; + chrgraw = read_charger_voltage(); + + if (!chrgraw_disable) { + if (chrgraw >= CHRGRAW_THRESHOLD) { + pmic_set_chg_current(0); + saved_ichrg_value = ichrg_value; + ichrg_value = 0; /* Userspace can suspend */ + chrgraw_disable = 1; + } + } + else { + /* Check charger voltage and restart charging */ + if (chrgraw < CHRGRAW_THRESHOLD) { + if (saved_ichrg_value) { + ichrg_value = saved_ichrg_value; + + /* Charging was disabled earlier due to chrgraw > 6V */ + pmic_set_chg_current(saved_ichrg_value); + pmic_restart_charging(); + } + else + fsl_detect_charger_type(); + + chrgraw_disable = 0; + } + else { + /* Charger disable from callback with an ichrg value */ + if (ichrg_value) { + pmic_set_chg_current(0); + saved_ichrg_value = ichrg_value; + ichrg_value = 0; /* Userspace can suspend */ + chrgraw_disable = 1; + } + } + } +} + +static void dump_mAH_stats(void) +{ + struct timeval next_battery_time; + + if ( (first_battery_reading != 0) && + (first_battery_reading > next_battery_reading)) { + do_gettimeofday(&next_battery_time); + printk(KERN_INFO "battery: I def:avg:Average_mAH_usage=%dmAH, time=%luseconds:\n", + (first_battery_reading - next_battery_reading), + (next_battery_time.tv_sec - first_battery_time.tv_sec)); + first_battery_reading = 0; + } +} + +static void do_charger_misc_work(struct work_struct *work); +DECLARE_DELAYED_WORK(charger_misc_work, do_charger_misc_work); + +/* + * Do all the miscellaneous activities like lobat checking and led setting + */ +static void do_charger_misc_work(struct work_struct *work) +{ + int batt_voltage = read_supply_voltage(); + int charger_conn = charger_connected(); + int sense_0 = 0; + + if (udc_suspended_mode) + return; + + /* Increment the chrgraw monitor to track the 60 seconds expiry */ + chrgraw_monitor++; + + if (!charger_conn && (batt_voltage <= CRITICAL_VOLTAGE_THRESHOLD)) { + lobat_condition = 1; + post_lobat_event(1); + goto done; + } + + if (!charger_conn && (batt_voltage <= LOW_VOLTAGE_THRESHOLD)) { + lobat_condition = 1; + post_lobat_event(0); + goto done; + } + + if (charger_conn && lobat_condition) + lobat_condition = 0; + + if (!charger_conn) { + if (!first_battery_reading) { + first_battery_reading = luigi_battery_mAH; + next_battery_reading = first_battery_reading; + do_gettimeofday(&first_battery_time); + } + else { + next_battery_reading = luigi_battery_mAH; + if (first_battery_reading < next_battery_reading) { + first_battery_reading = next_battery_reading; + do_gettimeofday(&first_battery_time); + } + } + } + else { + dump_mAH_stats(); + } + + if (crit_boot_flag && (luigi_battery_capacity > CHARGER_BOOT_THRESHOLD)) { + crit_boot_flag = 0; + pmic_write_reg(REG_MEM_A, (0 << 4), (1 << 4)); + } + + if (luigi_battery_error_flags || !luigi_battery_present) { + pmic_set_chg_current(0); + ichrg_value = 0; + goto done; + } + + if ( (chrgraw_monitor == CRAW_MON_THREHOLD) && charger_conn) + fsl_check_overvoltage(charger_conn); + + if (chrgraw_disable) + goto done; + + if (charger_conn && fsl_vbus_done) { + fsl_vbus_done = 0; + pmic_set_chg_current(ichrg_value); + } + + if (charger_conn && (charger_timer_expiry_counter == 2) && + (batt_voltage < BATTCYCL_THRESHOLD)) { + charger_timer_expiry_counter = 0; + pmic_restart_charging(); + } + + if (charger_conn && (batt_voltage <= CHARGER_TURN_ON)) + pmic_restart_charging(); + + /* + * Keep BPSNS to the lowest value "00" for higher charge + * current. However, if charger is not connected, then + * we need BPSNS to be "11" for LOBATL and LOBATH + */ + if (charger_conn && (batt_voltage > BPSNS_VOLTAGE_THRESH)) { + /* Try to charge at higher current */ + if (bpsns_value != 0) { + bpsns_value = 0; + pmic_write_reg(PMIC_REG_PC_0, bpsns_value << BPSNS_OFFSET, + BPSNS_MASK << BPSNS_OFFSET); + } + } + else { + if (bpsns_value != BPSNS_VALUE) { + bpsns_value = BPSNS_VALUE; + pmic_write_reg(PMIC_REG_PC_0, bpsns_value << BPSNS_OFFSET, + BPSNS_MASK << BPSNS_OFFSET); + } + } + + if (charger_conn && (batt_voltage <= BPON_THRESHOLD)) { + if (!charger_bpon) { + printk(KERN_INFO "Battery voltage below BPON_THRESHOLD\n"); + /* BPON charging */ + pmic_enable_bpon_charging(); + charger_bpon = 1; + } + goto done; + } + + if (charger_bpon && (batt_voltage > BPON_THRESHOLD_HI)) { + printk(KERN_INFO "Battery voltage over BPON_THRESHOLD\n"); + if (host_detected == 0) { + if (!wall_charger) + pmic_start_charging(CHARGING_THIRD_PARTY); + else + pmic_start_charging(CHARGING_WALL); + } + else { + if (!atomic_read(&enumerated)) + pmic_start_charging(CHARGING_HOST); + else + pmic_start_charging(charger_enumerated); + } + + charger_bpon = 0; + } + + if (charger_conn) { + if (luigi_battery_capacity > green_led_threshold) { + if (!green_led_set) { + green_led_set = 1; + + /* set the green led parameters */ + pmic_enable_green_led(1); + + /* set the chrgleden to 0 */ + pmic_green_led_disable(0); + + /* turn off the charger led */ + gpio_chrgled_active(0); + } + } + else { + green_led_set = 0; + + /* turn off the green led */ + pmic_enable_green_led(0); + + /* now enable the chrgleden to turn on the yellow LED */ + pmic_green_led_disable(1); + + /* turn back the charger led */ + gpio_chrgled_active(1); + } + } + + /* Check for full battery conditions */ + if (!full_battery && charger_conn) { + pmic_read_reg(REG_INT_SENSE0, &sense_0, 0xffffff); + if (!(sense_0 & CHGCURRS) && (batt_voltage > CHGCURRS_THRESHOLD) ) { + full_battery = 1; + printk(KERN_INFO "charger: Stop charging as battery is full\n"); + saved_ichrg_value = ichrg_value; + /* 80mA charging to prevent PMIC spam */ + pmic_set_chg_current(CHARGER_FULL); + } + } + + if (full_battery && charger_conn) { + if (batt_voltage < BATTCYCL_THRESHOLD) { + pmic_set_chg_current(saved_ichrg_value); + pmic_restart_charging(); + full_battery = 0; + } + else { + pmic_read_reg(REG_INT_SENSE0, &sense_0, 0xffffff); + if (sense_0 & CHGCURRS) { + pmic_set_chg_current(saved_ichrg_value); + pmic_restart_charging(); + full_battery = 0; + } + } + } + +done: + if (!udc_suspended_mode) + schedule_delayed_work(&charger_misc_work, msecs_to_jiffies(CHARGER_MISC)); +} + +/*----------------------------------------------------------------- + * done() - retire a request; caller blocked irqs + * @status : request status to be set, only works when + * request is still in progress. + *--------------------------------------------------------------*/ +static void done(struct fsl_ep *ep, struct fsl_req *req, int status) +{ + struct fsl_udc *udc = NULL; + unsigned char stopped = ep->stopped; + struct ep_td_struct *curr_td, *next_td; + int j; + + udc = (struct fsl_udc *)ep->udc; + /* Removed the req from fsl_ep->queue */ + list_del_init(&req->queue); + + /* req.status should be set as -EINPROGRESS in ep_queue() */ + if (req->req.status == -EINPROGRESS) + req->req.status = status; + else + status = req->req.status; + + /* Free dtd for the request */ + next_td = req->head; + for (j = 0; j < req->dtd_count; j++) { + curr_td = next_td; + if (j != req->dtd_count - 1) + next_td = curr_td->next_td_virt; + + dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma); + } + + if (USE_MSC_WR(req->req.length)) { + req->req.dma -= 1; + memmove(req->req.buf, req->req.buf + 1, MSC_BULK_CB_WRAP_LEN); + } + + if (req->mapped) { + dma_unmap_single(ep->udc->gadget.dev.parent, + req->req.dma, req->req.length, + ep_is_in(ep) + ? DMA_TO_DEVICE + : DMA_FROM_DEVICE); + req->req.dma = DMA_ADDR_INVALID; + req->mapped = 0; + } else + dma_sync_single_for_cpu(ep->udc->gadget.dev.parent, + req->req.dma, req->req.length, + ep_is_in(ep) + ? DMA_TO_DEVICE + : DMA_FROM_DEVICE); + + if (status && (status != -ESHUTDOWN)) + VDBG("complete %s req %p stat %d len %u/%u", + ep->ep.name, &req->req, status, + req->req.actual, req->req.length); + + ep->stopped = 1; + + spin_unlock(&ep->udc->lock); + /* complete() is from gadget layer, + * eg fsg->bulk_in_complete() */ + if (req->req.complete) + req->req.complete(&ep->ep, &req->req); + + spin_lock(&ep->udc->lock); + ep->stopped = stopped; +} + +/*----------------------------------------------------------------- + * nuke(): delete all requests related to this ep + * called with spinlock held + *--------------------------------------------------------------*/ +static void nuke(struct fsl_ep *ep, int status) +{ + ep->stopped = 1; + + /* Flush fifo */ + fsl_ep_fifo_flush(&ep->ep); + + /* Whether this eq has request linked */ + while (!list_empty(&ep->queue)) { + struct fsl_req *req = NULL; + + req = list_entry(ep->queue.next, struct fsl_req, queue); + done(ep, req, status); + } + dump_ep_queue(ep); +} + +/*------------------------------------------------------------------ + Internal Hardware related function + ------------------------------------------------------------------*/ + +static int dr_controller_setup(struct fsl_udc *udc) +{ + unsigned int tmp = 0, portctrl = 0; + unsigned int __attribute((unused)) ctrl = 0; + unsigned long timeout; + struct fsl_usb2_platform_data *pdata; + +#define FSL_UDC_RESET_TIMEOUT 1000 + + /* before here, make sure dr_regs has been initialized */ + if (!udc) + return -EINVAL; + pdata = udc->pdata; + + /* Stop and reset the usb controller */ + tmp = fsl_readl(&dr_regs->usbcmd); + tmp &= ~USB_CMD_RUN_STOP; + fsl_writel(tmp, &dr_regs->usbcmd); + + tmp = fsl_readl(&dr_regs->usbcmd); + tmp |= USB_CMD_CTRL_RESET; + fsl_writel(tmp, &dr_regs->usbcmd); + + /* Wait for reset to complete */ + timeout = jiffies + FSL_UDC_RESET_TIMEOUT; + while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) { + if (time_after(jiffies, timeout)) { + ERR("udc reset timeout! \n"); + return -ETIMEDOUT; + } + cpu_relax(); + } + + /* Set the controller as device mode */ + tmp = fsl_readl(&dr_regs->usbmode); + tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */ + tmp |= USB_MODE_CTRL_MODE_DEVICE; + /* Disable Setup Lockout */ + tmp |= USB_MODE_SETUP_LOCK_OFF; + if (pdata->es) + tmp |= USB_MODE_ES; + fsl_writel(tmp, &dr_regs->usbmode); + + fsl_platform_set_device_mode(pdata); + + /* Clear the setup status */ + fsl_writel(0, &dr_regs->usbsts); + + tmp = udc->ep_qh_dma; + tmp &= USB_EP_LIST_ADDRESS_MASK; + fsl_writel(tmp, &dr_regs->endpointlistaddr); + + VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x", + (int)udc->ep_qh, (int)tmp, + fsl_readl(&dr_regs->endpointlistaddr)); + + /* Config PHY interface */ + portctrl = fsl_readl(&dr_regs->portsc1); + portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH); + switch (udc->phy_mode) { + case FSL_USB2_PHY_ULPI: + portctrl |= PORTSCX_PTS_ULPI; + break; + case FSL_USB2_PHY_UTMI_WIDE: + portctrl |= PORTSCX_PTW_16BIT; + /* fall through */ + case FSL_USB2_PHY_UTMI: + portctrl |= PORTSCX_PTS_UTMI; + break; + case FSL_USB2_PHY_SERIAL: + portctrl |= PORTSCX_PTS_FSLS; + break; + default: + return -EINVAL; + } + fsl_writel(portctrl, &dr_regs->portsc1); + + if (cpu_is_mx35()) { + /* AHB burst INCR mode if imx35 */ + tmp = fsl_readl(&dr_regs->sbuscfg); + tmp &= ~0x07; + fsl_writel(tmp, &dr_regs->sbuscfg); + } + + if (pdata->have_sysif_regs) { + /* Config control enable i/o output, cpu endian register */ + ctrl = __raw_readl(&usb_sys_regs->control); + ctrl |= USB_CTRL_IOENB; + __raw_writel(ctrl, &usb_sys_regs->control); + } + +#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) + /* Turn on cache snooping hardware, since some PowerPC platforms + * wholly rely on hardware to deal with cache coherent. */ + + if (pdata->have_sysif_regs) { + /* Setup Snooping for all the 4GB space */ + tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */ + __raw_writel(tmp, &usb_sys_regs->snoop1); + tmp |= 0x80000000; /* starts from 0x8000000, size 2G */ + __raw_writel(tmp, &usb_sys_regs->snoop2); + } +#endif + + return 0; +} + +/* Enable DR irq and set controller to run state */ +static void dr_controller_run(struct fsl_udc *udc) +{ + u32 temp; + + fsl_platform_pullup_enable(udc->pdata); + + /* Enable DR irq reg */ + temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN + | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN + | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN; + + fsl_writel(temp, &dr_regs->usbintr); + + /* Clear stopped bit */ + udc->stopped = 0; + + /* Set the controller as device mode */ + temp = fsl_readl(&dr_regs->usbmode); + temp |= USB_MODE_CTRL_MODE_DEVICE; + fsl_writel(temp, &dr_regs->usbmode); + + /* Set controller to Run */ + temp = fsl_readl(&dr_regs->usbcmd); + temp |= USB_CMD_RUN_STOP; + fsl_writel(temp, &dr_regs->usbcmd); + + return; +} + +static void dr_controller_stop(struct fsl_udc *udc) +{ + unsigned int tmp; + + pr_debug("%s\n", __func__); + + /* if we're in OTG mode, and the Host is currently using the port, + * stop now and don't rip the controller out from under the + * ehci driver + */ + if (udc->gadget.is_otg) { + if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) { + pr_debug("udc: Leaving early\n"); + return; + } + } + + /* disable all INTR */ + fsl_writel(0, &dr_regs->usbintr); + + /* Set stopped bit for isr */ + udc->stopped = 1; + + /* disable IO output */ +/* usb_sys_regs->control = 0; */ + + fsl_platform_pullup_disable(udc->pdata); + + /* set controller to Stop */ + tmp = fsl_readl(&dr_regs->usbcmd); + tmp &= ~USB_CMD_RUN_STOP; + fsl_writel(tmp, &dr_regs->usbcmd); + + return; +} + +void dr_ep_setup(unsigned char ep_num, unsigned char dir, unsigned char ep_type) +{ + unsigned int tmp_epctrl = 0; + + tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); + if (dir) { + if (ep_num) + tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST; + tmp_epctrl |= EPCTRL_TX_ENABLE; + tmp_epctrl |= ((unsigned int)(ep_type) + << EPCTRL_TX_EP_TYPE_SHIFT); + } else { + if (ep_num) + tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST; + tmp_epctrl |= EPCTRL_RX_ENABLE; + tmp_epctrl |= ((unsigned int)(ep_type) + << EPCTRL_RX_EP_TYPE_SHIFT); + } + + fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]); +} + +static void +dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value) +{ + u32 tmp_epctrl = 0; + + tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); + + if (value) { + /* set the stall bit */ + if (dir) + tmp_epctrl |= EPCTRL_TX_EP_STALL; + else + tmp_epctrl |= EPCTRL_RX_EP_STALL; + } else { + /* clear the stall bit and reset data toggle */ + if (dir) { + tmp_epctrl &= ~EPCTRL_TX_EP_STALL; + tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST; + } else { + tmp_epctrl &= ~EPCTRL_RX_EP_STALL; + tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST; + } + } + fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]); +} + +/* Get stall status of a specific ep + Return: 0: not stalled; 1:stalled */ +static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir) +{ + u32 epctrl; + + epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); + if (dir) + return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0; + else + return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0; +} + +/******************************************************************** + Internal Structure Build up functions +********************************************************************/ + +/*------------------------------------------------------------------ +* struct_ep_qh_setup(): set the Endpoint Capabilites field of QH + * @zlt: Zero Length Termination Select (1: disable; 0: enable) + * @mult: Mult field + ------------------------------------------------------------------*/ +static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num, + unsigned char dir, unsigned char ep_type, + unsigned int max_pkt_len, + unsigned int zlt, unsigned char mult) +{ + struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir]; + unsigned int tmp = 0; + + /* set the Endpoint Capabilites in QH */ + switch (ep_type) { + case USB_ENDPOINT_XFER_CONTROL: + /* Interrupt On Setup (IOS). for control ep */ + tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS) + | EP_QUEUE_HEAD_IOS; + break; + case USB_ENDPOINT_XFER_ISOC: + tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS) + | (mult << EP_QUEUE_HEAD_MULT_POS); + break; + case USB_ENDPOINT_XFER_BULK: + case USB_ENDPOINT_XFER_INT: + tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS; + break; + default: + VDBG("error ep type is %d", ep_type); + return; + } + if (zlt) + tmp |= EP_QUEUE_HEAD_ZLT_SEL; + p_QH->max_pkt_length = cpu_to_hc32(tmp); + p_QH->next_dtd_ptr = 1; + p_QH->size_ioc_int_sts = 0; + + return; +} + +/* Setup qh structure and ep register for ep0. */ +static void ep0_setup(struct fsl_udc *udc) +{ + /* the intialization of an ep includes: fields in QH, Regs, + * fsl_ep struct */ + struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL, + USB_MAX_CTRL_PAYLOAD, 0, 0); + struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL, + USB_MAX_CTRL_PAYLOAD, 0, 0); + dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL); + dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL); + + return; + +} + +/*********************************************************************** + Endpoint Management Functions +***********************************************************************/ + +/*------------------------------------------------------------------------- + * when configurations are set, or when interface settings change + * for example the do_set_interface() in gadget layer, + * the driver will enable or disable the relevant endpoints + * ep0 doesn't use this routine. It is always enabled. +-------------------------------------------------------------------------*/ +static int fsl_ep_enable(struct usb_ep *_ep, + const struct usb_endpoint_descriptor *desc) +{ + struct fsl_udc *udc = NULL; + struct fsl_ep *ep = NULL; + unsigned short max = 0; + unsigned char mult = 0, zlt; + int retval = -EINVAL; + unsigned long flags = 0; + + ep = container_of(_ep, struct fsl_ep, ep); + + pr_debug("udc: %s ep.name=%s %d\n", __func__, ep->ep.name, desc->bDescriptorType); + /* catch various bogus parameters */ + if (!_ep || !desc + || (desc->bDescriptorType != USB_DT_ENDPOINT)) + return -EINVAL; + + udc = ep->udc; + + if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN)) + return -ESHUTDOWN; + + max = le16_to_cpu(desc->wMaxPacketSize); + + /* Disable automatic zlp generation. Driver is reponsible to indicate + * explicitly through req->req.zero. This is needed to enable multi-td + * request. */ + zlt = 1; + + /* Assume the max packet size from gadget is always correct */ + switch (desc->bmAttributes & 0x03) { + case USB_ENDPOINT_XFER_CONTROL: + case USB_ENDPOINT_XFER_BULK: + case USB_ENDPOINT_XFER_INT: + /* mult = 0. Execute N Transactions as demonstrated by + * the USB variable length packet protocol where N is + * computed using the Maximum Packet Length (dQH) and + * the Total Bytes field (dTD) */ + mult = 0; + break; + case USB_ENDPOINT_XFER_ISOC: + /* Calculate transactions needed for high bandwidth iso */ + mult = (unsigned char)(1 + ((max >> 11) & 0x03)); + max = max & 0x8ff; /* bit 0~10 */ + /* 3 transactions at most */ + if (mult > 3) + goto en_done; + break; + default: + goto en_done; + } + + spin_lock_irqsave(&udc->lock, flags); + ep->ep.maxpacket = max; + ep->desc = desc; + ep->stopped = 0; + + /* Controller related setup */ + /* Init EPx Queue Head (Ep Capabilites field in QH + * according to max, zlt, mult) */ + struct_ep_qh_setup(udc, (unsigned char) ep_index(ep), + (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN) + ? USB_SEND : USB_RECV), + (unsigned char) (desc->bmAttributes + & USB_ENDPOINT_XFERTYPE_MASK), + max, zlt, mult); + + /* Init endpoint ctrl register */ + dr_ep_setup((unsigned char) ep_index(ep), + (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN) + ? USB_SEND : USB_RECV), + (unsigned char) (desc->bmAttributes + & USB_ENDPOINT_XFERTYPE_MASK)); + + spin_unlock_irqrestore(&udc->lock, flags); + retval = 0; + + VDBG("enabled %s (ep%d%s) maxpacket %d", ep->ep.name, + ep->desc->bEndpointAddress & 0x0f, + (desc->bEndpointAddress & USB_DIR_IN) + ? "in" : "out", max); +en_done: + return retval; +} + +/*--------------------------------------------------------------------- + * @ep : the ep being unconfigured. May not be ep0 + * Any pending and uncomplete req will complete with status (-ESHUTDOWN) +*---------------------------------------------------------------------*/ +static int fsl_ep_disable(struct usb_ep *_ep) +{ + struct fsl_udc *udc = NULL; + struct fsl_ep *ep = NULL; + u32 epctrl; + int ep_num; + + ep = container_of(_ep, struct fsl_ep, ep); + if (!_ep || !ep->desc) { + VDBG("%s not enabled", _ep ? ep->ep.name : NULL); + return -EINVAL; + } + + /* disable ep on controller */ + ep_num = ep_index(ep); + epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); + if (ep_is_in(ep)) + epctrl &= ~EPCTRL_TX_ENABLE; + else + epctrl &= ~EPCTRL_RX_ENABLE; + fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); + + udc = (struct fsl_udc *)ep->udc; + + /* nuke all pending requests (does flush) */ + nuke(ep, -ESHUTDOWN); + + ep->desc = 0; + ep->stopped = 1; + + VDBG("disabled %s OK", _ep->name); + return 0; +} + +/*--------------------------------------------------------------------- + * allocate a request object used by this endpoint + * the main operation is to insert the req->queue to the eq->queue + * Returns the request, or null if one could not be allocated +*---------------------------------------------------------------------*/ +static struct usb_request * +fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) +{ + struct fsl_req *req = NULL; + + req = kzalloc(sizeof *req, gfp_flags); + if (!req) + return NULL; + + req->req.dma = DMA_ADDR_INVALID; + pr_debug("udc: req=0x%p set req.dma=0x%x\n", req, req->req.dma); + INIT_LIST_HEAD(&req->queue); + + return &req->req; +} + +static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req) +{ + struct fsl_req *req = NULL; + + req = container_of(_req, struct fsl_req, req); + + if (_req) + kfree(req); +} + +static void update_qh(struct fsl_req *req) +{ + struct fsl_ep *ep = req->ep; + int i = ep_index(ep) * 2 + ep_is_in(ep); + u32 temp; + struct ep_queue_head *dQH = &ep->udc->ep_qh[i]; + + /* Write dQH next pointer and terminate bit to 0 */ + temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK; + if (NEED_IRAM(req->ep)) { + req->cur->next_td_ptr |= cpu_to_hc32(DTD_NEXT_TERMINATE); + temp = req->cur->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK; + } + dQH->next_dtd_ptr = cpu_to_hc32(temp); + temp = cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE + | EP_QUEUE_HEAD_STATUS_HALT)); + dQH->size_ioc_int_sts &= temp; + + temp = ep_is_in(ep) + ? (1 << (ep_index(ep) + 16)) + : (1 << (ep_index(ep))); + fsl_writel(temp, &dr_regs->endpointprime); +} + +/*-------------------------------------------------------------------------*/ +static int fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req) +{ + u32 temp, bitmask, tmp_stat; + + /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr); + VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */ + + bitmask = ep_is_in(ep) + ? (1 << (ep_index(ep) + 16)) + : (1 << (ep_index(ep))); + + /* check if the pipe is empty */ + if (!(list_empty(&ep->queue))) { + /* Add td to the end */ + struct fsl_req *lastreq; + lastreq = list_entry(ep->queue.prev, struct fsl_req, queue); + if (NEED_IRAM(ep)) { + lastreq->tail->next_td_ptr = + cpu_to_hc32(req->head->td_dma | DTD_NEXT_TERMINATE); + goto out; + } else { + lastreq->tail->next_td_ptr = + cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK); + } + /* Read prime bit, if 1 goto done */ + if (fsl_readl(&dr_regs->endpointprime) & bitmask) + goto out; + + do { + /* Set ATDTW bit in USBCMD */ + temp = fsl_readl(&dr_regs->usbcmd); + fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd); + + /* Read correct status bit */ + tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask; + + } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW)); + + /* Write ATDTW bit to 0 */ + temp = fsl_readl(&dr_regs->usbcmd); + fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd); + + if (tmp_stat) + goto out; + } + update_qh(req); +out: + return 0; +} + +/* Fill in the dTD structure + * @req: request that the transfer belongs to + * @length: return actually data length of the dTD + * @dma: return dma address of the dTD + * @is_last: return flag if it is the last dTD of the request + * return: pointer to the built dTD */ +static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length, + dma_addr_t *dma, int *is_last) +{ + u32 swap_temp; + struct ep_td_struct *dtd; + + /* how big will this transfer be? */ + *length = min(req->req.length - req->req.actual, + (unsigned)EP_MAX_LENGTH_TRANSFER); + + if (NEED_IRAM(req->ep)) + *length = min(*length, g_iram_size); + dtd = dma_pool_alloc(udc_controller->td_pool, GFP_KERNEL, dma); + if (dtd == NULL) + return dtd; + + dtd->td_dma = *dma; + /* Clear reserved field */ + swap_temp = hc32_to_cpu(dtd->size_ioc_sts); + if (NEED_IRAM(req->ep)) + swap_temp = (u32) (req->req.dma); + swap_temp &= ~DTD_RESERVED_FIELDS; + dtd->size_ioc_sts = cpu_to_hc32(swap_temp); + + /* Init all of buffer page pointers */ + swap_temp = (u32) (req->req.dma + req->req.actual); + dtd->buff_ptr0 = cpu_to_hc32(swap_temp); + dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000); + dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000); + dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000); + dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000); + + req->req.actual += *length; + + /* zlp is needed if req->req.zero is set */ + if (req->req.zero) { + if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0) + *is_last = 1; + else + *is_last = 0; + } else if (req->req.length == req->req.actual) + *is_last = 1; + else + *is_last = 0; + + if ((*is_last) == 0) + VDBG("multi-dtd request!\n"); + /* Fill in the transfer size; set active bit */ + swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE); + + /* Enable interrupt for the last dtd of a request */ + if (*is_last && !req->req.no_interrupt) + swap_temp |= DTD_IOC; + if (NEED_IRAM(req->ep)) + swap_temp |= DTD_IOC; + + dtd->size_ioc_sts = cpu_to_hc32(swap_temp); + + mb(); + + VDBG("length = %d address= 0x%x", *length, (int)*dma); + + return dtd; +} + +/* Generate dtd chain for a request */ +static int fsl_req_to_dtd(struct fsl_req *req) +{ + unsigned count; + int is_last; + int is_first = 1; + struct ep_td_struct *last_dtd = NULL, *dtd; + dma_addr_t dma; + + if (NEED_IRAM(req->ep)) { + req->oridma = req->req.dma; + if (ep_is_in(req->ep)) { + if ((list_empty(&req->ep->queue))) { + memcpy((char *)req->ep->udc->iram_buffer_v[1], + req->req.buf, min(req->req.length, g_iram_size)); + } + } + else { + req->req.dma = req->ep->udc->iram_buffer[0]; + } + } + + if (USE_MSC_WR(req->req.length)) + req->req.dma += 1; + + do { + dtd = fsl_build_dtd(req, &count, &dma, &is_last); + if (dtd == NULL) + return -ENOMEM; + + if (is_first) { + is_first = 0; + req->head = dtd; + } else { + last_dtd->next_td_ptr = cpu_to_hc32(dma); + last_dtd->next_td_virt = dtd; + } + last_dtd = dtd; + + req->dtd_count++; + } while (!is_last); + + dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE); + + req->tail = dtd; + + return 0; +} + +/* queues (submits) an I/O request to an endpoint */ +static int +fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) +{ + struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep); + struct fsl_req *req = container_of(_req, struct fsl_req, req); + struct fsl_udc *udc; + unsigned long flags; + int is_iso = 0; + + /* catch various bogus parameters */ + if (!_req || !req->req.complete || !req->req.buf + || !list_empty(&req->queue)) { + VDBG("%s, bad params\n", __func__); + return -EINVAL; + } + if (!_ep || (!ep->desc && ep_index(ep))) { + VDBG("%s, bad ep\n", __func__); + return -EINVAL; + } + if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { + if (req->req.length > ep->ep.maxpacket) + return -EMSGSIZE; + is_iso = 1; + } + + udc = ep->udc; + if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) + return -ESHUTDOWN; + + req->ep = ep; + + /* map virtual address to hardware */ + if (req->req.dma == DMA_ADDR_INVALID) { + req->req.dma = dma_map_single(ep->udc->gadget.dev.parent, + req->req.buf, + req->req.length, ep_is_in(ep) + ? DMA_TO_DEVICE + : DMA_FROM_DEVICE); + req->mapped = 1; + } else { + dma_sync_single_for_device(ep->udc->gadget.dev.parent, + req->req.dma, req->req.length, + ep_is_in(ep) + ? DMA_TO_DEVICE + : DMA_FROM_DEVICE); + req->mapped = 0; + } + + req->req.status = -EINPROGRESS; + req->req.actual = 0; + req->dtd_count = 0; + + if (NEED_IRAM(ep)) { + req->last_one = 0; + req->buffer_offset = 0; + } + spin_lock_irqsave(&udc->lock, flags); + + /* build dtds and push them to device queue */ + if (!fsl_req_to_dtd(req)) { + fsl_queue_td(ep, req); + } else { + spin_unlock_irqrestore(&udc->lock, flags); + return -ENOMEM; + } + + /* Update ep0 state */ + if ((ep_index(ep) == 0)) + udc->ep0_state = DATA_STATE_XMIT; + + /* irq handler advances the queue */ + if (req != NULL) + list_add_tail(&req->queue, &ep->queue); + spin_unlock_irqrestore(&udc->lock, flags); + + return 0; +} + +/* dequeues (cancels, unlinks) an I/O request from an endpoint */ +static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) +{ + struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep); + struct fsl_req *req; + unsigned long flags; + int ep_num, stopped, ret = 0; + u32 epctrl; + + if (!_ep || !_req) + return -EINVAL; + + spin_lock_irqsave(&ep->udc->lock, flags); + stopped = ep->stopped; + + /* Stop the ep before we deal with the queue */ + ep->stopped = 1; + ep_num = ep_index(ep); + epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); + if (ep_is_in(ep)) + epctrl &= ~EPCTRL_TX_ENABLE; + else + epctrl &= ~EPCTRL_RX_ENABLE; + fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); + + /* make sure it's actually queued on this endpoint */ + list_for_each_entry(req, &ep->queue, queue) { + if (&req->req == _req) + break; + } + if (&req->req != _req) { + ret = -EINVAL; + goto out; + } + + /* The request is in progress, or completed but not dequeued */ + if (ep->queue.next == &req->queue) { + _req->status = -ECONNRESET; + fsl_ep_fifo_flush(_ep); /* flush current transfer */ + + /* The request isn't the last request in this ep queue */ + if (req->queue.next != &ep->queue) { + struct ep_queue_head *qh; + struct fsl_req *next_req; + + qh = ep->qh; + next_req = list_entry(req->queue.next, struct fsl_req, + queue); + + /* Point the QH to the first TD of next request */ + fsl_writel((u32) next_req->head, &qh->curr_dtd_ptr); + } + + /* The request hasn't been processed, patch up the TD chain */ + } else { + struct fsl_req *prev_req; + + prev_req = list_entry(req->queue.prev, struct fsl_req, queue); + fsl_writel(fsl_readl(&req->tail->next_td_ptr), + &prev_req->tail->next_td_ptr); + + } + + done(ep, req, -ECONNRESET); + + /* Enable EP */ +out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); + if (ep_is_in(ep)) + epctrl |= EPCTRL_TX_ENABLE; + else + epctrl |= EPCTRL_RX_ENABLE; + fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); + ep->stopped = stopped; + + spin_unlock_irqrestore(&ep->udc->lock, flags); + return ret; +} + +/*-------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------- + * modify the endpoint halt feature + * @ep: the non-isochronous endpoint being stalled + * @value: 1--set halt 0--clear halt + * Returns zero, or a negative error code. +*----------------------------------------------------------------*/ +static int fsl_ep_set_halt(struct usb_ep *_ep, int value) +{ + struct fsl_ep *ep = NULL; + unsigned long flags = 0; + int status = -EOPNOTSUPP; /* operation not supported */ + unsigned char ep_dir = 0, ep_num = 0; + struct fsl_udc *udc = NULL; + + ep = container_of(_ep, struct fsl_ep, ep); + udc = ep->udc; + if (!_ep || !ep->desc) { + status = -EINVAL; + goto out; + } + + if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { + status = -EOPNOTSUPP; + goto out; + } + + /* Attempt to halt IN ep will fail if any transfer requests + * are still queue */ + if (value && ep_is_in(ep) && !list_empty(&ep->queue)) { + status = -EAGAIN; + goto out; + } + + status = 0; + ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV; + ep_num = (unsigned char)(ep_index(ep)); + spin_lock_irqsave(&ep->udc->lock, flags); + dr_ep_change_stall(ep_num, ep_dir, value); + spin_unlock_irqrestore(&ep->udc->lock, flags); + + if (ep_index(ep) == 0) { + udc->ep0_state = WAIT_FOR_SETUP; + udc->ep0_dir = 0; + } +out: + VDBG(" %s %s halt stat %d", ep->ep.name, + value ? "set" : "clear", status); + + return status; +} + +static int arcotg_fifo_status(struct usb_ep *_ep) +{ + struct fsl_ep *ep; + struct fsl_udc *udc; + int size = 0; + u32 bitmask; + struct ep_queue_head *d_qh; + + ep = container_of(_ep, struct fsl_ep, ep); + if (!_ep || (!ep->desc && ep_index(ep) != 0)) + return -ENODEV; + + udc = (struct fsl_udc *)ep->udc; + + if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) + return -ESHUTDOWN; + + d_qh = &ep->udc->ep_qh[ep_index(ep) * 2 + ep_is_in(ep)]; + + bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) : + (1 << (ep_index(ep))); + + if (fsl_readl(&dr_regs->endptstatus) & bitmask) + size = (d_qh->size_ioc_int_sts & DTD_PACKET_SIZE) + >> DTD_LENGTH_BIT_POS; + + pr_debug("%s %u\n", __func__, size); + return size; +} + +static void fsl_ep_fifo_flush(struct usb_ep *_ep) +{ + struct fsl_ep *ep; + int ep_num, ep_dir; + u32 bits; + unsigned long timeout; + int retry = 100; +#define FSL_UDC_FLUSH_TIMEOUT 1000 + + if (!_ep) { + return; + } else { + ep = container_of(_ep, struct fsl_ep, ep); + if (!ep->desc) + return; + } + ep_num = ep_index(ep); + ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV; + + if (ep_num == 0) + bits = (1 << 16) | 1; + else if (ep_dir == USB_SEND) + bits = 1 << (16 + ep_num); + else + bits = 1 << ep_num; + + timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT; + do { + fsl_writel(bits, &dr_regs->endptflush); + + /* Wait until flush complete */ + while (fsl_readl(&dr_regs->endptflush)) { + if (time_after(jiffies, timeout)) { + ERR("ep flush timeout\n"); + return; + } + cpu_relax(); + } + + retry--; + if (!retry) + break; + + /* See if we need to flush again */ + } while (fsl_readl(&dr_regs->endptstatus) & bits); +} + +static struct usb_ep_ops fsl_ep_ops = { + .enable = fsl_ep_enable, + .disable = fsl_ep_disable, + + .alloc_request = fsl_alloc_request, + .free_request = fsl_free_request, + + .queue = fsl_ep_queue, + .dequeue = fsl_ep_dequeue, + + .set_halt = fsl_ep_set_halt, + .fifo_status = arcotg_fifo_status, + .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */ +}; + +/*------------------------------------------------------------------------- + Gadget Driver Layer Operations +-------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------- + * Get the current frame number (from DR frame_index Reg ) + *----------------------------------------------------------------------*/ +static int fsl_get_frame(struct usb_gadget *gadget) +{ + return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS); +} + +/*----------------------------------------------------------------------- + * Tries to wake up the host connected to this gadget + -----------------------------------------------------------------------*/ +static int fsl_wakeup(struct usb_gadget *gadget) +{ + struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget); + u32 portsc; + + /* Remote wakeup feature not enabled by host */ + if (!udc->remote_wakeup) + return -ENOTSUPP; + + portsc = fsl_readl(&dr_regs->portsc1); + /* not suspended? */ + if (!(portsc & PORTSCX_PORT_SUSPEND)) + return 0; + /* trigger force resume */ + portsc |= PORTSCX_PORT_FORCE_RESUME; + fsl_writel(portsc, &dr_regs->portsc1); + return 0; +} + +static int can_pullup(struct fsl_udc *udc) +{ + return udc->driver && udc->softconnect && udc->vbus_active; +} + +/* Notify controller that VBUS is powered, Called by whatever + detects VBUS sessions */ +static int fsl_vbus_session(struct usb_gadget *gadget, int is_active) +{ + struct fsl_udc *udc; + unsigned long flags; + + udc = container_of(gadget, struct fsl_udc, gadget); + spin_lock_irqsave(&udc->lock, flags); + VDBG("VBUS %s\n", is_active ? "on" : "off"); + udc->vbus_active = (is_active != 0); + if (can_pullup(udc)) + fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP), + &dr_regs->usbcmd); + else + fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP), + &dr_regs->usbcmd); + spin_unlock_irqrestore(&udc->lock, flags); + return 0; +} + +/* constrain controller's VBUS power usage + * This call is used by gadget drivers during SET_CONFIGURATION calls, + * reporting how much power the device may consume. For example, this + * could affect how quickly batteries are recharged. + * + * Returns zero on success, else negative errno. + */ +static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA) +{ + struct fsl_udc *udc; + + udc = container_of(gadget, struct fsl_udc, gadget); + ichrg_value = mA; + atomic_set(&enumerated, 1); + charger_enumerated = mA; + third_party_charger = 0; + fsl_vbus_done = 1; + return 0; +} + +/* Change Data+ pullup status + * this func is used by usb_gadget_connect/disconnet + */ +static int fsl_pullup(struct usb_gadget *gadget, int is_on) +{ + struct fsl_udc *udc; + + udc = container_of(gadget, struct fsl_udc, gadget); + udc->softconnect = (is_on != 0); + if (can_pullup(udc)) + fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP), + &dr_regs->usbcmd); + else + fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP), + &dr_regs->usbcmd); + + return 0; +} + +/* defined in gadget.h */ +static struct usb_gadget_ops fsl_gadget_ops = { + .get_frame = fsl_get_frame, + .wakeup = fsl_wakeup, +/* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */ + .vbus_session = fsl_vbus_session, + .vbus_draw = fsl_vbus_draw, + .pullup = fsl_pullup, +}; + +/* Set protocol stall on ep0, protocol stall will automatically be cleared + on new transaction */ +static void ep0stall(struct fsl_udc *udc) +{ + u32 tmp; + + /* must set tx and rx to stall at the same time */ + tmp = fsl_readl(&dr_regs->endptctrl[0]); + tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL; + fsl_writel(tmp, &dr_regs->endptctrl[0]); + udc->ep0_state = WAIT_FOR_SETUP; + udc->ep0_dir = 0; +} + +/* Prime a status phase for ep0 */ +static int ep0_prime_status(struct fsl_udc *udc, int direction) +{ + struct fsl_req *req = udc->status_req; + struct fsl_ep *ep; + int status = 0; + + if (direction == EP_DIR_IN) + udc->ep0_dir = USB_DIR_IN; + else + udc->ep0_dir = USB_DIR_OUT; + + ep = &udc->eps[0]; + udc->ep0_state = WAIT_FOR_OUT_STATUS; + + req->ep = ep; + req->req.length = 0; + req->req.status = -EINPROGRESS; + req->req.actual = 0; + req->req.complete = NULL; + req->dtd_count = 0; + + if (fsl_req_to_dtd(req) == 0) + status = fsl_queue_td(ep, req); + else + return -ENOMEM; + + if (status) + ERR("Can't queue ep0 status request \n"); + list_add_tail(&req->queue, &ep->queue); + + return status; +} + +static inline int udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe) +{ + struct fsl_ep *ep = get_ep_by_pipe(udc, pipe); + + if (!ep->name) + return 0; + + nuke(ep, -ESHUTDOWN); + + return 0; +} + +/* + * ch9 Set address + */ +static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length) +{ + /* Save the new address to device struct */ + udc->device_address = (u8) value; + /* Update usb state */ + udc->usb_state = USB_STATE_ADDRESS; + /* Status phase */ + if (ep0_prime_status(udc, EP_DIR_IN)) + ep0stall(udc); +} + +/* + * ch9 Get status + */ +static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value, + u16 index, u16 length) +{ + u16 tmp = 0; /* Status, cpu endian */ + + struct fsl_req *req; + struct fsl_ep *ep; + int status = 0; + + ep = &udc->eps[0]; + + if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) { + /* Get device status */ + tmp = 1 << USB_DEVICE_SELF_POWERED; + tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP; + } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) { + /* Get interface status */ + /* We don't have interface information in udc driver */ + tmp = 0; + } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) { + /* Get endpoint status */ + struct fsl_ep *target_ep; + + target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index)); + + /* stall if endpoint doesn't exist */ + if (!target_ep->desc) + goto stall; + tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep)) + << USB_ENDPOINT_HALT; + } + + udc->ep0_dir = USB_DIR_IN; + /* Borrow the per device status_req */ + req = udc->status_req; + /* Fill in the reqest structure */ + *((u16 *) req->req.buf) = cpu_to_le16(tmp); + req->ep = ep; + req->req.length = 2; + req->req.status = -EINPROGRESS; + req->req.actual = 0; + req->req.complete = NULL; + req->dtd_count = 0; + + /* prime the data phase */ + if ((fsl_req_to_dtd(req) == 0)) + status = fsl_queue_td(ep, req); + else /* no mem */ + goto stall; + + if (status) { + ERR("Can't respond to getstatus request \n"); + goto stall; + } + list_add_tail(&req->queue, &ep->queue); + udc->ep0_state = DATA_STATE_XMIT; + return; +stall: + ep0stall(udc); +} + +/* + * Wait for the USB to get into test mode + */ +static void usbtest_workqueue_handler(struct work_struct *work) +{ + /* + * Rather than using mdelay(), use msleep() since it does not + * block the CPU. + */ + msleep(10); +} + +static void setup_received_irq(struct fsl_udc *udc, + struct usb_ctrlrequest *setup) +{ + u16 wValue = le16_to_cpu(setup->wValue); + u16 wIndex = le16_to_cpu(setup->wIndex); + u16 wLength = le16_to_cpu(setup->wLength); + + udc_reset_ep_queue(udc, 0); + + /* We process some stardard setup requests here */ + switch (setup->bRequest) { + case USB_REQ_GET_STATUS: + /* Data+Status phase from udc */ + if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK)) + != (USB_DIR_IN | USB_TYPE_STANDARD)) + break; + ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength); + return; + + case USB_REQ_SET_ADDRESS: + /* Status phase from udc */ + if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD + | USB_RECIP_DEVICE)) + break; + ch9setaddress(udc, wValue, wIndex, wLength); + return; + + case USB_REQ_CLEAR_FEATURE: + case USB_REQ_SET_FEATURE: + /* Status phase from udc */ + { + int rc = -EOPNOTSUPP; + u16 ptc = 0; + + if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK)) + == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) { + int pipe = get_pipe_by_windex(wIndex); + struct fsl_ep *ep; + + if (wValue != 0 || wLength != 0 || pipe > udc->max_ep) + break; + ep = get_ep_by_pipe(udc, pipe); + + spin_unlock(&udc->lock); + rc = fsl_ep_set_halt(&ep->ep, + (setup->bRequest == USB_REQ_SET_FEATURE) + ? 1 : 0); + spin_lock(&udc->lock); + + } else if ((setup->bRequestType & (USB_RECIP_MASK + | USB_TYPE_MASK)) == (USB_RECIP_DEVICE + | USB_TYPE_STANDARD)) { + /* Note: The driver has not include OTG support yet. + * This will be set when OTG support is added */ + if (setup->wValue == USB_DEVICE_TEST_MODE) + ptc = setup->wIndex >> 8; + else if (gadget_is_otg(&udc->gadget)) { + if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE) + udc->gadget.b_hnp_enable = 1; + else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT) + udc->gadget.a_hnp_support = 1; + else if (setup->bRequest == + USB_DEVICE_A_ALT_HNP_SUPPORT) + udc->gadget.a_alt_hnp_support = 1; + } + rc = 0; + } else + break; + + if (rc == 0) { + if (ep0_prime_status(udc, EP_DIR_IN)) + ep0stall(udc); + } + + if (ptc) { + u32 tmp; + + if (ep0_prime_status(udc, EP_DIR_IN)) + ep0stall(udc); + + /* + * Bits 16-19 are Port Test Control + */ + tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16); + fsl_writel(tmp, &dr_regs->portsc1); + + printk(KERN_INFO "arcotg_udc: switch to test mode %d.\n", ptc); + + /* + * We need a 10ms delay to wait for the USB to enter into + * test mode. However, we cannot mdelay() or msleep() here + * since this is an IRQ handler. So, we schedule a workqueue + */ + schedule_work(&udc->usbtest_work); + } + + return; + } + + default: + break; + } + + /* Requests handled by gadget */ + if (wLength) { + /* Data phase from gadget, status phase from udc */ + udc->ep0_dir = (setup->bRequestType & USB_DIR_IN) + ? USB_DIR_IN : USB_DIR_OUT; + spin_unlock(&udc->lock); + if (udc->driver->setup(&udc->gadget, + &udc->local_setup_buff) < 0) + ep0stall(udc); + spin_lock(&udc->lock); + udc->ep0_state = (setup->bRequestType & USB_DIR_IN) + ? DATA_STATE_XMIT : DATA_STATE_RECV; + } else { + /* No data phase, IN status from gadget */ + udc->ep0_dir = USB_DIR_IN; + spin_unlock(&udc->lock); + if (udc->driver->setup(&udc->gadget, + &udc->local_setup_buff) < 0) + ep0stall(udc); + spin_lock(&udc->lock); + udc->ep0_state = WAIT_FOR_OUT_STATUS; + } +} + +/* Process request for Data or Status phase of ep0 + * prime status phase if needed */ +static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0, + struct fsl_req *req) +{ + if (udc->usb_state == USB_STATE_ADDRESS) { + /* Set the new address */ + u32 new_address = (u32) udc->device_address; + fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS, + &dr_regs->deviceaddr); + } + + done(ep0, req, 0); + + switch (udc->ep0_state) { + case DATA_STATE_XMIT: + /* receive status phase */ + if (ep0_prime_status(udc, EP_DIR_OUT)) + ep0stall(udc); + break; + case DATA_STATE_RECV: + /* send status phase */ + if (ep0_prime_status(udc, EP_DIR_IN)) + ep0stall(udc); + break; + case WAIT_FOR_OUT_STATUS: + udc->ep0_state = WAIT_FOR_SETUP; + break; + case WAIT_FOR_SETUP: + ERR("Unexpect ep0 packets \n"); + break; + default: + ep0stall(udc); + break; + } +} + +static void iram_process_ep_complete(struct fsl_req *curr_req, + int cur_transfer) +{ + char *buf; + u32 len; + int in = ep_is_in(curr_req->ep); + + if (in) + buf = (char *)udc_controller->iram_buffer_v[1]; + else + buf = (char *)udc_controller->iram_buffer_v[0]; + + if (curr_req->cur->next_td_ptr == cpu_to_hc32(DTD_NEXT_TERMINATE) + || (cur_transfer < g_iram_size) + || (curr_req->req.length == curr_req->req.actual)) + curr_req->last_one = 1; + + if (curr_req->last_one) { + if (!in) { + memcpy(curr_req->req.buf + curr_req->buffer_offset, buf, + cur_transfer); + } + if (curr_req->tail->next_td_ptr != + cpu_to_hc32(DTD_NEXT_TERMINATE)) { + struct fsl_req *next_req; + next_req = + list_entry(curr_req->queue.next, + struct fsl_req, queue); + if (in) + memcpy(buf, next_req->req.buf, + min(g_iram_size, next_req->req.length)); + update_qh(next_req); + } + } + else { + curr_req->buffer_offset += g_iram_size; + curr_req->cur->next_td_ptr &= ~cpu_to_hc32(DTD_NEXT_TERMINATE); + curr_req->cur = curr_req->cur->next_td_virt; + if (in) { + len = + min(curr_req->req.length - curr_req->buffer_offset, + g_iram_size); + + memcpy(buf, curr_req->req.buf + curr_req->buffer_offset, + len); + } + else { + memcpy(curr_req->req.buf + curr_req->buffer_offset - + g_iram_size, buf, g_iram_size); + } + update_qh(curr_req); + } +} + +/* Tripwire mechanism to ensure a setup packet payload is extracted without + * being corrupted by another incoming setup packet */ +static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr) +{ + u32 temp; + struct ep_queue_head *qh; + struct fsl_usb2_platform_data *pdata = udc->pdata; + + qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT]; + + /* Clear bit in ENDPTSETUPSTAT */ + temp = fsl_readl(&dr_regs->endptsetupstat); + fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat); + + /* while a hazard exists when setup package arrives */ + do { + /* Set Setup Tripwire */ + temp = fsl_readl(&dr_regs->usbcmd); + fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd); + + /* Copy the setup packet to local buffer */ + if (pdata->le_setup_buf) { + u32 *p = (u32 *)buffer_ptr; + u32 *s = (u32 *)qh->setup_buffer; + + /* Convert little endian setup buffer to CPU endian */ + *p++ = le32_to_cpu(*s++); + *p = le32_to_cpu(*s); + } else { + memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8); + } + } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW)); + + /* Clear Setup Tripwire */ + temp = fsl_readl(&dr_regs->usbcmd); + fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd); +} + +/* process-ep_req(): free the completed Tds for this req */ +static int process_ep_req(struct fsl_udc *udc, int pipe, + struct fsl_req *curr_req) +{ + struct ep_td_struct *curr_td; + int td_complete, actual, remaining_length, j, tmp; + int status = 0; + int errors = 0; + struct ep_queue_head *curr_qh = &udc->ep_qh[pipe]; + int direction = pipe % 2; + int total = 0, real_len; + + curr_td = curr_req->head; + td_complete = 0; + actual = curr_req->req.length; + + for (j = 0; j < curr_req->dtd_count; j++) { + remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts) + & DTD_PACKET_SIZE) + >> DTD_LENGTH_BIT_POS; + if (NEED_IRAM(curr_req->ep)) { + if (real_len >= g_iram_size) { + actual = g_iram_size; + real_len -= g_iram_size; + } + else { + actual = real_len; + curr_req->last_one = 1; + } + } + actual -= remaining_length; + total += actual; + + errors = hc32_to_cpu(curr_td->size_ioc_sts) & DTD_ERROR_MASK; + if (errors) { + if (errors & DTD_STATUS_HALTED) { + ERR("dTD error %08x QH=%d\n", errors, pipe); + /* Clear the errors and Halt condition */ + tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts); + tmp &= ~errors; + curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp); + status = -EPIPE; + /* FIXME: continue with next queued TD? */ + + break; + } + if (errors & DTD_STATUS_DATA_BUFF_ERR) { + VDBG("Transfer overflow"); + status = -EPROTO; + break; + } else if (errors & DTD_STATUS_TRANSACTION_ERR) { + VDBG("ISO error"); + status = -EILSEQ; + break; + } else + ERR("Unknown error has occured (0x%x)!\r\n", + errors); + + } else if (hc32_to_cpu(curr_td->size_ioc_sts) + & DTD_STATUS_ACTIVE) { + VDBG("Request not complete"); + status = REQ_UNCOMPLETE; + return status; + } else if (remaining_length) { + if (direction) { + VDBG("Transmit dTD remaining length not zero"); + status = -EPROTO; + break; + } else { + td_complete++; + break; + } + } else { + td_complete++; + VDBG("dTD transmitted successful "); + } + + if (NEED_IRAM(curr_req->ep)) + if (curr_td-> + next_td_ptr & cpu_to_hc32(DTD_NEXT_TERMINATE)) + break; + + if (j != curr_req->dtd_count - 1) + curr_td = (struct ep_td_struct *)curr_td->next_td_virt; + } + + if (status) + return status; + + curr_req->req.actual = total; + if (NEED_IRAM(curr_req->ep)) + iram_process_ep_complete(curr_req, actual); + + return 0; +} + +/* Process a DTD completion interrupt */ +static void dtd_complete_irq(struct fsl_udc *udc) +{ + u32 bit_pos; + int i, ep_num, direction, bit_mask, status; + struct fsl_ep *curr_ep; + struct fsl_req *curr_req, *temp_req; + + /* Clear the bits in the register */ + bit_pos = fsl_readl(&dr_regs->endptcomplete); + fsl_writel(bit_pos, &dr_regs->endptcomplete); + + if (!bit_pos) + return; + + for (i = 0; i < udc->max_ep * 2; i++) { + ep_num = i >> 1; + direction = i % 2; + + bit_mask = 1 << (ep_num + 16 * direction); + + if (!(bit_pos & bit_mask)) + continue; + + curr_ep = get_ep_by_pipe(udc, i); + + /* If the ep is configured */ + if (curr_ep->name == NULL) { + WARN("Invalid EP?"); + continue; + } + + /* process the req queue until an uncomplete request */ + list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue, + queue) { + status = process_ep_req(udc, i, curr_req); + + VDBG("status of process_ep_req= %d, ep = %d", + status, ep_num); + if (status == REQ_UNCOMPLETE) + break; + /* write back status to req */ + curr_req->req.status = status; + + if (ep_num == 0) { + ep0_req_complete(udc, curr_ep, curr_req); + break; + } else { + if (NEED_IRAM(curr_ep)) { + if (curr_req->last_one) + done(curr_ep, curr_req, status); + break; + } + else { + done(curr_ep, curr_req, status); + } + } + } + + dump_ep_queue(curr_ep); + } +} + +/* Late check to make sure, the device got enumerated */ +static void port_change_work(struct work_struct *work) +{ + /* If device already enumerated, return. */ + if (charger_connected() && (udc_controller->gadget.speed != USB_SPEED_UNKNOWN) + && (udc_controller->gadget.configured) ) { + return; + } + + /* No charger, so return */ + if (!charger_connected()) + return; + + /* Re-enumerate */ + fsl_udc_redo_enumerate(); +} + +/* Process a port change interrupt */ +static void port_change_irq(struct fsl_udc *udc) +{ + u32 speed; + unsigned int portsc1; + + if (udc->bus_reset) + udc->bus_reset = 0; + + /* Bus resetting is finished */ + if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) { + /* Get the speed */ + speed = (fsl_readl(&dr_regs->portsc1) + & PORTSCX_PORT_SPEED_MASK); + switch (speed) { + case PORTSCX_PORT_SPEED_HIGH: + udc->gadget.speed = USB_SPEED_HIGH; + break; + case PORTSCX_PORT_SPEED_FULL: + udc->gadget.speed = USB_SPEED_FULL; + break; + case PORTSCX_PORT_SPEED_LOW: + udc->gadget.speed = USB_SPEED_LOW; + break; + default: + udc->gadget.speed = USB_SPEED_UNKNOWN; + break; + } + } + + portsc1 = fsl_readl(&dr_regs->portsc1); + /* Check the High Speed Port settings */ + if ((portsc1 & PORTSCX_CURRENT_CONNECT_STATUS) && + (portsc1 & PORTSCX_PORT_HSP)) { + udc->gadget.speed = USB_SPEED_HIGH; + } + + /* Update USB state */ + if (!udc->resume_state) + udc->usb_state = USB_STATE_DEFAULT; + + /* Late workqueue to check if re-enumeration needed */ + schedule_delayed_work(&pc_wq, msecs_to_jiffies(PC_WORK_THRESHOLD)); +} + +/* Process suspend interrupt */ +static void suspend_irq(struct fsl_udc *udc) +{ + pr_debug("%s\n", __func__); + + udc->resume_state = udc->usb_state; + udc->usb_state = USB_STATE_SUSPENDED; + + /* report suspend to the driver, serial.c does not support this */ + if (udc->driver && udc->driver->suspend) + udc->driver->suspend(&udc->gadget); +} + +static void bus_resume(struct fsl_udc *udc) +{ + udc->usb_state = udc->resume_state; + udc->resume_state = 0; + + /* report resume to the driver, serial.c does not support this */ + if (udc->driver && udc->driver->resume) + udc->driver->resume(&udc->gadget); +} + +/* Clear up all ep queues */ +static int reset_queues(struct fsl_udc *udc) +{ + u8 pipe; + + for (pipe = 0; pipe < udc->max_pipes; pipe++) + udc_reset_ep_queue(udc, pipe); + + /* report disconnect; the driver is already quiesced */ + if (udc->driver) + udc->driver->disconnect(&udc->gadget); + + return 0; +} + +/* Process reset interrupt */ +static void reset_irq(struct fsl_udc *udc) +{ + u32 temp; + unsigned long timeout; + + /* Clear the device address */ + temp = fsl_readl(&dr_regs->deviceaddr); + fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr); + + udc->device_address = 0; + + /* Clear usb state */ + udc->resume_state = 0; + udc->ep0_dir = 0; + udc->ep0_state = WAIT_FOR_SETUP; + udc->remote_wakeup = 0; /* default to 0 on reset */ + udc->gadget.b_hnp_enable = 0; + udc->gadget.a_hnp_support = 0; + udc->gadget.a_alt_hnp_support = 0; + + /* Clear all the setup token semaphores */ + temp = fsl_readl(&dr_regs->endptsetupstat); + fsl_writel(temp, &dr_regs->endptsetupstat); + + /* Clear all the endpoint complete status bits */ + temp = fsl_readl(&dr_regs->endptcomplete); + fsl_writel(temp, &dr_regs->endptcomplete); + + timeout = jiffies + 100; + while (fsl_readl(&dr_regs->endpointprime)) { + /* Wait until all endptprime bits cleared */ + if (time_after(jiffies, timeout)) { + ERR("Timeout for reset\n"); + break; + } + cpu_relax(); + } + + /* Write 1s to the flush register */ + fsl_writel(0xffffffff, &dr_regs->endptflush); + + if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) { + VDBG("Bus reset"); + /* Bus is reseting */ + udc->bus_reset = 1; + /* Reset all the queues, include XD, dTD, EP queue + * head and TR Queue */ + reset_queues(udc); + udc->usb_state = USB_STATE_DEFAULT; + } else { + VDBG("Controller reset"); + /* initialize usb hw reg except for regs for EP, not + * touch usbintr reg */ + dr_controller_setup(udc); + + /* Reset all internal used Queues */ + reset_queues(udc); + + ep0_setup(udc); + + /* Enable DR IRQ reg, Set Run bit, change udc state */ + dr_controller_run(udc); + udc->usb_state = USB_STATE_ATTACHED; + } +} + +/* + * USB device controller interrupt handler + */ +static irqreturn_t fsl_udc_irq(int irq, void *_udc) +{ + struct fsl_udc *udc = _udc; + u32 irq_src; + irqreturn_t status = IRQ_HANDLED; + unsigned long flags; + + /* Disable ISR for OTG host mode */ + if (udc->stopped) + return IRQ_NONE; + + spin_lock_irqsave(&udc->lock, flags); + irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr); + /* Clear notification bits */ + fsl_writel(irq_src, &dr_regs->usbsts); + + VDBG("irq_src [0x%8x]", irq_src); + + /* Need to resume? */ + if (udc->usb_state == USB_STATE_SUSPENDED) + if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0) + bus_resume(udc); + + /* USB Interrupt */ + if (irq_src & USB_STS_INT) { + VDBG("Packet int"); + /* Setup package, we only support ep0 as control ep */ + if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) { + if (udc_detection) { + tripwire_handler(udc, 0, + (u8 *) (&udc->local_setup_buff)); + setup_received_irq(udc, &udc->local_setup_buff); + } + /* Host detection */ + host_detected = 1; + status = IRQ_HANDLED; + } + + /* completion of dtd */ + if (fsl_readl(&dr_regs->endptcomplete)) { + dtd_complete_irq(udc); + status = IRQ_HANDLED; + } + } + + /* SOF (for ISO transfer) */ + if (irq_src & USB_STS_SOF) { + status = IRQ_HANDLED; + } + + /* Port Change */ + if (irq_src & USB_STS_PORT_CHANGE) { + port_change_irq(udc); + status = IRQ_HANDLED; + } + + /* Reset Received */ + if (irq_src & USB_STS_RESET) { + VDBG("reset int"); + reset_irq(udc); + status = IRQ_HANDLED; + } + + /* Sleep Enable (Suspend) */ + if (irq_src & USB_STS_SUSPEND) { + suspend_irq(udc); + status = IRQ_HANDLED; + } + + if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) { + VDBG("Error IRQ %x ", irq_src); + } + + spin_unlock_irqrestore(&udc->lock, flags); + return status; +} + +/*----------------------------------------------------------------* + * Hook to gadget drivers + * Called by initialization code of gadget drivers +*----------------------------------------------------------------*/ +int usb_gadget_register_driver(struct usb_gadget_driver *driver) +{ + int retval = -ENODEV; + unsigned long flags = 0; + + if (!udc_controller) + return -ENODEV; + + if (!driver || (driver->speed != USB_SPEED_FULL + && driver->speed != USB_SPEED_HIGH) + || !driver->bind || !driver->disconnect + || !driver->setup) + return -EINVAL; + + if (udc_controller->driver) + return -EBUSY; + + /* lock is needed but whether should use this lock or another */ + spin_lock_irqsave(&udc_controller->lock, flags); + + driver->driver.bus = 0; + /* hook up the driver */ + udc_controller->driver = driver; + udc_controller->gadget.dev.driver = &driver->driver; + spin_unlock_irqrestore(&udc_controller->lock, flags); + + /* bind udc driver to gadget driver */ + retval = driver->bind(&udc_controller->gadget); + if (retval) { + VDBG("bind to %s --> %d", driver->driver.name, retval); + udc_controller->gadget.dev.driver = 0; + udc_controller->driver = 0; + goto out; + } + + if (udc_controller->transceiver) { + /* Suspend the controller until OTG enable it */ + udc_suspend(udc_controller); + printk(KERN_INFO "Suspend udc for OTG auto detect\n"); + + /* export udc suspend/resume call to OTG */ + udc_controller->gadget.dev.driver->suspend = fsl_udc_suspend; + udc_controller->gadget.dev.driver->resume = fsl_udc_resume; + + /* connect to bus through transceiver */ + if (udc_controller->transceiver) { + retval = otg_set_peripheral(udc_controller->transceiver, + &udc_controller->gadget); + if (retval < 0) { + ERR("can't bind to transceiver\n"); + driver->unbind(&udc_controller->gadget); + udc_controller->gadget.dev.driver = 0; + udc_controller->driver = 0; + return retval; + } + } + } else { + /* Enable DR IRQ reg and Set usbcmd reg Run bit */ + dr_controller_run(udc_controller); + udc_controller->usb_state = USB_STATE_ATTACHED; + udc_controller->ep0_state = WAIT_FOR_SETUP; + udc_controller->ep0_dir = 0; + } + printk(KERN_INFO "%s: bind to driver %s \n", + udc_controller->gadget.name, driver->driver.name); + +out: + if (retval) + printk(KERN_DEBUG "retval %d \n", retval); + return retval; +} +EXPORT_SYMBOL(usb_gadget_register_driver); + +/* Disconnect from gadget driver */ +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) +{ + struct fsl_ep *loop_ep; + unsigned long flags; + + if (!udc_controller) + return -ENODEV; + + if (!driver || driver != udc_controller->driver || !driver->unbind) + return -EINVAL; + + fsl_idle_low_power_exit(udc_controller); + + if (udc_controller->transceiver) + (void)otg_set_peripheral(udc_controller->transceiver, 0); + + /* stop DR, disable intr */ + dr_controller_stop(udc_controller); + + /* in fact, no needed */ + udc_controller->usb_state = USB_STATE_ATTACHED; + udc_controller->ep0_state = WAIT_FOR_SETUP; + udc_controller->ep0_dir = 0; + + /* stand operation */ + spin_lock_irqsave(&udc_controller->lock, flags); + udc_controller->gadget.speed = USB_SPEED_UNKNOWN; + nuke(&udc_controller->eps[0], -ESHUTDOWN); + list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list, + ep.ep_list) + nuke(loop_ep, -ESHUTDOWN); + spin_unlock_irqrestore(&udc_controller->lock, flags); + + /* disconnect gadget before unbinding */ + if (driver->disconnect) + driver->disconnect(&udc_controller->gadget); + + /* unbind gadget and unhook driver. */ + driver->unbind(&udc_controller->gadget); + udc_controller->gadget.dev.driver = 0; + udc_controller->driver = 0; + + printk(KERN_INFO "unregistered gadget driver '%s'\r\n", + driver->driver.name); + return 0; +} +EXPORT_SYMBOL(usb_gadget_unregister_driver); + +#ifdef CONFIG_DEBUG_FS + +/*------------------------------------------------------------------------- + Debug filesystem +-------------------------------------------------------------------------*/ +#include +#include + +static int fsl_udc_show(struct seq_file *s, void *p) +{ + unsigned long flags; + int t, i; + u32 tmp_reg; + struct fsl_ep *ep = NULL; + struct fsl_req *req; + struct fsl_usb2_platform_data *pdata; + struct fsl_udc *udc = udc_controller; + + pdata = udc->pdata; + + spin_lock_irqsave(&udc->lock, flags); + + /* ------basic driver infomation ---- */ + t = seq_printf(s, + DRIVER_DESC "\n" + "%s version: %s\n" + "Driver Author: %s\n" + "Gadget driver: %s\n\n", + driver_name, DRIVER_VERSION, DRIVER_AUTHOR, + udc->driver ? udc->driver->driver.name : "(none)"); + + /* ------ DR Registers ----- */ + tmp_reg = fsl_readl(&dr_regs->usbcmd); + t += seq_printf(s, + "USBCMD reg: 0x%x\n" + "SetupTW: %d\n" + "Run/Stop: %s\n\n", + tmp_reg, + (tmp_reg & USB_CMD_SUTW) ? 1 : 0, + (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop"); + + tmp_reg = fsl_readl(&dr_regs->usbsts); + t += seq_printf(s, + "USB Status Reg: 0x%x\n" + "Dr Suspend: %d" "Reset Received: %d" "System Error: %s" + "USB Error Interrupt: %s\n\n", + tmp_reg, + (tmp_reg & USB_STS_SUSPEND) ? 1 : 0, + (tmp_reg & USB_STS_RESET) ? 1 : 0, + (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal", + (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err"); + + tmp_reg = fsl_readl(&dr_regs->usbintr); + t += seq_printf(s, + "USB Interrupt Enable Reg: 0x%x\n" + "Sleep Enable: %d" "SOF Received Enable: %d" + "Reset Enable: %d\n" + "System Error Enable: %d" + "Port Change Dectected Enable: %d\n" + "USB Error Intr Enable: %d" "USB Intr Enable: %d\n\n", + tmp_reg, + (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0, + (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0, + (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0, + (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0, + (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0, + (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0, + (tmp_reg & USB_INTR_INT_EN) ? 1 : 0); + + tmp_reg = fsl_readl(&dr_regs->frindex); + t += seq_printf(s, + "USB Frame Index Reg:" "Frame Number is 0x%x\n\n", + (tmp_reg & USB_FRINDEX_MASKS)); + + tmp_reg = fsl_readl(&dr_regs->deviceaddr); + t += seq_printf(s, + "USB Device Address Reg:" "Device Addr is 0x%x\n\n", + (tmp_reg & USB_DEVICE_ADDRESS_MASK)); + + tmp_reg = fsl_readl(&dr_regs->endpointlistaddr); + t += seq_printf(s, + "USB Endpoint List Address Reg:" + "Device Addr is 0x%x\n\n", + (tmp_reg & USB_EP_LIST_ADDRESS_MASK)); + + tmp_reg = fsl_readl(&dr_regs->portsc1); + t += seq_printf(s, + "USB Port Status&Control Reg: 0x%x\n" + "Port Transceiver Type : %s" "Port Speed: %s \n" + "PHY Low Power Suspend: %s" "Port Reset: %s" + "Port Suspend Mode: %s \n" "Over-current Change: %s" + "Port Enable/Disable Change: %s\n" + "Port Enabled/Disabled: %s" + "Current Connect Status: %s\n\n", tmp_reg, ({ + char *s; + switch (tmp_reg & PORTSCX_PTS_FSLS) { + case PORTSCX_PTS_UTMI: + s = "UTMI"; break; + case PORTSCX_PTS_ULPI: + s = "ULPI "; break; + case PORTSCX_PTS_FSLS: + s = "FS/LS Serial"; break; + default: + s = "None"; break; + } + s; }), ({ + char *s; + switch (tmp_reg & PORTSCX_PORT_SPEED_UNDEF) { + case PORTSCX_PORT_SPEED_FULL: + s = "Full Speed"; break; + case PORTSCX_PORT_SPEED_LOW: + s = "Low Speed"; break; + case PORTSCX_PORT_SPEED_HIGH: + s = "High Speed"; break; + default: + s = "Undefined"; break; + } + s; + }), + (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ? + "Normal PHY mode" : "Low power mode", + (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" : + "Not in Reset", + (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in", + (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" : + "No", + (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" : + "Not change", + (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" : + "Not correct", + (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ? + "Attached" : "Not-Att"); + + tmp_reg = fsl_readl(&dr_regs->usbmode); + t += seq_printf(s, + "USB Mode Reg:" "Controller Mode is : %s\n\n", ({ + char *s; + switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) { + case USB_MODE_CTRL_MODE_IDLE: + s = "Idle"; break; + case USB_MODE_CTRL_MODE_DEVICE: + s = "Device Controller"; break; + case USB_MODE_CTRL_MODE_HOST: + s = "Host Controller"; break; + default: + s = "None"; break; + } + s; + })); + + tmp_reg = fsl_readl(&dr_regs->endptsetupstat); + t += seq_printf(s, + "Endpoint Setup Status Reg:" "SETUP on ep 0x%x\n\n", + (tmp_reg & EP_SETUP_STATUS_MASK)); + + for (i = 0; i < udc->max_ep / 2; i++) { + tmp_reg = fsl_readl(&dr_regs->endptctrl[i]); + t += seq_printf(s, "EP Ctrl Reg [0x%x]: = [0x%x]\n", + i, tmp_reg); + } + tmp_reg = fsl_readl(&dr_regs->endpointprime); + t += seq_printf(s, "EP Prime Reg = [0x%x]\n", tmp_reg); + + if (pdata->have_sysif_regs) { + tmp_reg = usb_sys_regs->snoop1; + t += seq_printf(s, "\nSnoop1 Reg = [0x%x]\n\n", tmp_reg); + + tmp_reg = usb_sys_regs->control; + t += seq_printf(s, "General Control Reg = [0x%x]\n\n", + tmp_reg); + } + + /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */ + ep = &udc->eps[0]; + t += seq_printf(s, "For %s Maxpkt is 0x%x index is 0x%x\n", + ep->ep.name, ep_maxpacket(ep), ep_index(ep)); + + if (list_empty(&ep->queue)) { + t += seq_printf(s, "its req queue is empty\n\n"); + } else { + list_for_each_entry(req, &ep->queue, queue) { + t += seq_printf(s, + "req %p actual 0x%x length 0x%x buf %p\n", + &req->req, req->req.actual, + req->req.length, req->req.buf); + } + } + /* other gadget->eplist ep */ + list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) { + if (ep->desc) { + t += seq_printf(s, + "\nFor %s Maxpkt is 0x%x " + "index is 0x%x\n", + ep->ep.name, ep_maxpacket(ep), + ep_index(ep)); + + if (list_empty(&ep->queue)) { + t += seq_printf(s, + "its req queue is empty\n\n"); + } else { + list_for_each_entry(req, &ep->queue, queue) { + t += seq_printf(s, + "req %p actual 0x%x length" + "0x%x buf %p\n", + &req->req, req->req.actual, + req->req.length, req->req.buf); + } /* end for each_entry of ep req */ + } /* end for else */ + } /* end for if(ep->queue) */ + } /* end (ep->desc) */ + + spin_unlock_irqrestore(&udc->lock, flags); + + return 0; +} + +static int fsl_udc_open(struct inode *inode, struct file *file) +{ + return single_open(file, fsl_udc_show, inode->i_private); +} + +static const struct file_operations fsl_udc_dbg_fops = { + .owner = THIS_MODULE, + .open = fsl_udc_open, + .llseek = seq_lseek, + .read = seq_read, + .release = single_release, +}; + +static void fsl_udc_init_debugfs(struct fsl_udc *udc) +{ + struct dentry *root, *state; + + root = debugfs_create_dir(udc->gadget.name, NULL); + if (IS_ERR(root) || !root) + goto err_root; + + state = debugfs_create_file("udcstate", 0400, root, udc, + &fsl_udc_dbg_fops); + if (!state) + goto err_state; + + udc->debugfs_root = root; + udc->debugfs_state = state; + return; +err_state: + debugfs_remove(root); +err_root: + printk(KERN_ERR "udc: debugfs is not available\n"); +} + +static void fsl_udc_cleanup_debugfs(struct fsl_udc *udc) +{ + debugfs_remove(udc->debugfs_state); + debugfs_remove(udc->debugfs_root); + + udc->debugfs_state = NULL; + udc->debugfs_root = NULL; +} + +#else + +static void fsl_udc_init_debugfs(struct fsl_udc *udc) +{ +} + +static void fsl_udc_cleanup_debugfs(struct fsl_udc *udc) +{ +} + +#endif + +/*-------------------------------------------------------------------------*/ + +/* Release udc structures */ +static void fsl_udc_release(struct device *dev) +{ + complete(udc_controller->done); + dma_free_coherent(dev->parent, udc_controller->ep_qh_size, + udc_controller->ep_qh, udc_controller->ep_qh_dma); + kfree(udc_controller); +} + +/****************************************************************** + Internal structure setup functions +*******************************************************************/ +/*------------------------------------------------------------------ + * init resource for globle controller + * Return the udc handle on success or NULL on failure + ------------------------------------------------------------------*/ +static int __init struct_udc_setup(struct fsl_udc *udc, + struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata; + size_t size; + + pdata = pdev->dev.platform_data; + udc->phy_mode = pdata->phy_mode; + + udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL); + if (!udc->eps) { + ERR("malloc fsl_ep failed\n"); + return -1; + } + + /* initialized QHs, take care of alignment */ + size = udc->max_ep * sizeof(struct ep_queue_head); + if (size < QH_ALIGNMENT) + size = QH_ALIGNMENT; + else if ((size % QH_ALIGNMENT) != 0) { + size += QH_ALIGNMENT + 1; + size &= ~(QH_ALIGNMENT - 1); + } + udc->ep_qh = dma_alloc_coherent(&pdev->dev, size, + &udc->ep_qh_dma, GFP_KERNEL); + if (!udc->ep_qh) { + ERR("malloc QHs for udc failed\n"); + kfree(udc->eps); + return -1; + } + + udc->ep_qh_size = size; + + /* Initialize ep0 status request structure */ + /* FIXME: fsl_alloc_request() ignores ep argument */ + udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL), + struct fsl_req, req); + /* allocate a small amount of memory to get valid address */ + udc->status_req->req.buf = kmalloc(8, GFP_KERNEL); + udc->status_req->req.dma = virt_to_phys(udc->status_req->req.buf); + + udc->resume_state = USB_STATE_NOTATTACHED; + udc->usb_state = USB_STATE_POWERED; + udc->ep0_dir = 0; + udc->remote_wakeup = 0; /* default to 0 on reset */ + spin_lock_init(&udc->lock); + + return 0; +} + +static void suspend_port(void) +{ + unsigned int portctrl = 0; + + portctrl = fsl_readl(&dr_regs->portsc1); + portctrl |= PORTSCX_PHY_LOW_POWER_SPD; + fsl_writel(portctrl, &dr_regs->portsc1); +} + +static void resume_port(void) +{ + unsigned int portctrl = 0; + + if (portctrl & PORTSCX_PORT_SUSPEND) { + portctrl = fsl_readl(&dr_regs->portsc1); + portctrl |= PORTSCX_PORT_FORCE_RESUME; + fsl_writel(portctrl, &dr_regs->portsc1); + } + + portctrl = fsl_readl(&dr_regs->portsc1); + portctrl &= ~PORTSCX_PHY_LOW_POWER_SPD; + fsl_writel(portctrl, &dr_regs->portsc1); + + while ((portctrl & PORTSCX_PORT_SUSPEND)) { + udelay(100); + portctrl = fsl_readl(&dr_regs->portsc1); + } +} + +static void suspend_ctrl(void) +{ + unsigned int usbcmd; + + usbcmd = fsl_readl(&dr_regs->usbcmd); + usbcmd &= ~USB_CMD_RUN_STOP; + fsl_writel(usbcmd, &dr_regs->usbcmd); +} + +static void resume_ctrl(void) +{ + unsigned int usbcmd; + usbcmd = fsl_readl(&dr_regs->usbcmd); + usbcmd |= USB_CMD_RUN_STOP; + fsl_writel(usbcmd, &dr_regs->usbcmd); +} + +/* Redo a detach-attach event */ +static void fsl_udc_redo_enumerate(void) +{ + /* Don't read the USB controller registers if charger removed */ + if (udc_controller->suspended || !charger_connected()) + return; + + /* Pull D+ low */ + suspend_ctrl(); + + /* Settling time */ + mdelay(50); + + /* Attach event */ + resume_ctrl(); +} + +static ssize_t +show_connected(struct device *dev, struct device_attribute *attr, char *buf) +{ + if (charger_connected()) + return sprintf(buf, "1\n"); + else + return sprintf(buf, "0\n"); +} + +static ssize_t +show_supply_voltage(struct device *dev, struct device_attribute *attr, char *buf) +{ + int batt_voltage = read_supply_voltage(); + + if (batt_voltage < 0) + return sprintf(buf, "0\n"); + else + return sprintf(buf, "%d\n", batt_voltage); +} + +/* + * Battery Voltage + */ +static ssize_t +show_voltage(struct device *dev, struct device_attribute *attr, char *buf) +{ + int batt_voltage = read_supply_voltage(); + + if (batt_voltage < 0) + return sprintf(buf, "0\n"); + else + return sprintf(buf, "%d\n", batt_voltage); +} + +/* + * BPSNS value + */ +static ssize_t +show_bpsns(struct device *dev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", bpsns_value); +} + +/* + * this is the charging flag that indicates that the device is charging + */ +static ssize_t +show_charging(struct device *dev, struct device_attribute *attr, char *buf) +{ + if (charger_connected() && (ichrg_value > 1) ) + return sprintf(buf, "1\n"); + else + return sprintf(buf, "0\n"); +} + +static int pmic_get_batt_current(unsigned short *curr) +{ + t_channel channel; + unsigned short result[8]; + + channel = BATTERY_CURRENT; + CHECK_ERROR(pmic_adc_convert(channel, result)); + *curr = result[0]; + + return 0; +} + +/*! + * Indicates a lobat condition has been hit + */ +static ssize_t +show_lobat_condition(struct device *dev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", lobat_condition); +} + +/* + * Battery current + */ +static ssize_t +show_battery_current(struct device *dev, struct device_attribute *attr, char *buf) +{ + unsigned short current_raw = 0; + int current_uA = 0; + int status = pmic_get_batt_current(¤t_raw); + + if (status < 0) + return sprintf(buf, "0\n"); + else { + if (current_raw & 0x200) + current_uA = (0x1FF - (current_raw & 0x1FF)) * BAT_CURRENT_UNIT_UA * (-1); + else + current_uA = current_raw & 0x1FF * BAT_CURRENT_UNIT_UA; + + return sprintf(buf, "%d\n", current_uA); + } +} + +/* + * Fake battery error file till a battery driver is written + */ +static ssize_t +show_batt_error(struct device *dev, struct device_attribute *attr, char *buf) +{ + /* As per the latest spec, no more battery errors */ + return sprintf(buf, "%d\n", 0); +} + +/*! + * Battery ID + */ +static ssize_t +show_battery_id(struct device *dev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", luigi_battery_id); +} + +/*! + * Third party charger + */ +static ssize_t +show_third_party(struct device *dev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", third_party_charger); +} + +/*! + * Charger ADC voltage + */ +static ssize_t +show_charger_adc_voltage(struct device *dev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", read_charger_voltage()); +} + +/* + * Show current ichrg value + */ +static ssize_t +show_ichrg_setting(struct device *dev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", ichrg_value); +} + +static void pmic_enable_green_led(int enable) +{ + if (enable == 1) { + mc13892_bklit_set_current(LIT_GREEN, 0x7); + mc13892_bklit_set_ramp(LIT_GREEN, 0); + mc13892_bklit_set_dutycycle(LIT_GREEN, 0x3f); + } + else { + mc13892_bklit_set_current(LIT_GREEN, 0); + mc13892_bklit_set_dutycycle(LIT_GREEN, 0); + } +} + +static int pmic_set_chg_current(unsigned short curr) +{ + unsigned int mask; + unsigned int value; + + value = BITFVAL(BIT_CHG_CURR, curr); + mask = BITFMASK(BIT_CHG_CURR); + CHECK_ERROR(pmic_write_reg(REG_CHARGE, value, mask)); + + return 0; +} + +static int pmic_set_chg_misc(enum chg_setting type, unsigned short flag) +{ + unsigned int reg_value = 0; + unsigned int mask = 0; + + switch (type) { + case BAT_TH_CHECK_DIS: + reg_value = BITFVAL(BAT_TH_CHECK_DIS, flag); + mask = BITFMASK(BAT_TH_CHECK_DIS); + break; + case RESTART_CHG_STAT: + reg_value = BITFVAL(RESTART_CHG_STAT, flag); + mask = BITFMASK(RESTART_CHG_STAT); + break; + case AUTO_CHG_DIS: + reg_value = BITFVAL(AUTO_CHG_DIS, flag); + mask = BITFMASK(AUTO_CHG_DIS); + break; + case VI_PROGRAM_EN: + reg_value = BITFVAL(VI_PROGRAM_EN, flag); + mask = BITFMASK(VI_PROGRAM_EN); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(REG_CHARGE, reg_value, mask)); + return 0; +} + +static void pmic_start_charging(int value) +{ + /* Battery thermistor check disable */ + pmic_set_chg_misc(BAT_TH_CHECK_DIS, 1); + + /* Keep auto charging enabled */ + pmic_set_chg_misc(AUTO_CHG_DIS, 0); + + /* Allow programming of charge voltage and current */ + pmic_set_chg_misc(VI_PROGRAM_EN, 1); + + /* Set the ichrg */ + pmic_set_chg_current(value); + ichrg_value = value; + + /* Turn off CYCLB disable */ + pmic_write_reg(REG_CHARGE, (0 << CHRGCYCLB), (1 << CHRGCYCLB)); + + /* PLIM: bits 15 and 16 */ + pmic_write_reg(REG_CHARGE, (0x2 << 15), (0x3 << 15)); + + /* PLIMDIS: bit 17 */ + pmic_write_reg(REG_CHARGE, (0 << 17), (1 << 17)); + + /* Start the charger state machine */ + pmic_set_chg_misc(RESTART_CHG_STAT, 1); +} + +/* + * Dynamically enable/disable the charger even if the charge + * cable is connected. + */ +static void fsl_charger_enable(int enable) +{ + if (enable) { + /* + * Check if charger is connected and if ichrg is set to 0 + */ + if (charger_connected() && !ichrg_value) { + pmic_start_charging(CHARGING_WALL); + schedule_delayed_work(&charger_misc_work, msecs_to_jiffies(CHARGER_MISC)); + } + udc_suspended_mode = 0; + } + else { + /* Fake a suspended mode state so that timer does not run */ + udc_suspended_mode = 1; + + /* Shut off the miscellaneous charger timer function */ + cancel_rearming_delayed_work(&charger_misc_work); + + /* Set the ichrg to 0 */ + pmic_set_chg_current(0); + ichrg_value = 0; + + /* Clear the charger timer counter */ + charger_timer_expiry_counter = 0; + + /* Shut off the green LED */ + pmic_enable_green_led(0); + + /* Enable accessory charging */ + enable_accessory_gpo4(); + + /* Clear out saved ichrg value */ + saved_ichrg_value = 0; + + /* Shut off the CHRGLEDEN bit */ + pmic_green_led_disable(0); + + /* Clear the green LED flag */ + green_led_set = 0; + + atomic_set(&enumerated, 0); + + /* Clear out the variables */ + third_party_charger = 0; + charger_bpon = 0; + wall_charger = 0; + charger_conn_probe = 0; + charger_enumerated = 0; + } +} + +/* charger enable/disable on the fly */ +static ssize_t +show_charger_state(struct device *_dev, struct device_attribute *attr, char *buf) +{ + /* ichrg_value is 0 if not charging */ + return sprintf(buf, "%d\n", ichrg_value); +} + +static ssize_t +store_charger_state(struct device *_dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int value; + + if ((sscanf(buf, "%d", &value) > 0) && + ((value == 0) || (value == 1))) { + fsl_charger_enable(value); + return strlen(buf); + } + + return -EINVAL; +} +static DEVICE_ATTR (charger_state, S_IRUGO|S_IWUSR, show_charger_state, store_charger_state); + +/*! Configurable green led capacity */ +static ssize_t +show_green_led_threshold(struct device *_dev, struct device_attribute *attr, char *buf) +{ + /* Current green led threshold in capacity */ + return sprintf(buf, "%d\n", green_led_threshold); +} + +static ssize_t +store_green_led_threshold(struct device *_dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int value; + + if ((sscanf(buf, "%d", &value) > 0) && (value > 0)) { + green_led_threshold = value; + return strlen(buf); + } + + return -EINVAL; +} +static DEVICE_ATTR(green_led_threshold, S_IRUGO|S_IWUSR, show_green_led_threshold, store_green_led_threshold); + +static ssize_t +store_chrgled_state(struct device *_dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int value; + + if ((sscanf(buf, "%d", &value) > 0) && + ((value == 0) || (value == 1))) { + gpio_chrgled_active(value); + return strlen(buf); + } + + return -EINVAL; +} +static DEVICE_ATTR (chrgled_state, S_IRUGO|S_IWUSR, NULL, store_chrgled_state); + +static void fsl_charger_lobath_unsubscribe(int value) +{ + if (!value) { + pmic_event_subscribe(EVENT_LOBATLI, lobatli_event); + pmic_event_subscribe(EVENT_LOBATHI, lobathi_event); + } + else { + pmic_event_unsubscribe(EVENT_LOBATLI, lobatli_event); + pmic_event_unsubscribe(EVENT_LOBATHI, lobathi_event); + } +} + +static ssize_t +store_charger_lobath_unsub(struct device *_dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int value; + + if ((sscanf(buf, "%d", &value) > 0) && + ((value == 0) || (value == 1))) { + fsl_charger_lobath_unsubscribe(value); + return strlen(buf); + } + + return -EINVAL; +} + +static DEVICE_ATTR (charger_lobath_unsub, S_IRUGO|S_IWUSR, NULL, store_charger_lobath_unsub); + +/*! Third party charging */ +static void third_party_detect(struct work_struct *work) +{ + char *envp[] = { "CHARGER=thirdparty", NULL }; + + if (!atomic_read(&enumerated) && charger_connected() && !wall_charger) { + printk("Connected to a third party charger\n"); + pmic_start_charging(CHARGING_THIRD_PARTY); + third_party_charger = 1; + /* Relay the event to userspace */ + kobject_uevent_env(&udc_controller->gadget.dev.parent->kobj, KOBJ_CHANGE, envp); + } +} + +static DECLARE_DELAYED_WORK(third_party_work, third_party_detect); + +/*! Failure of enumeration should redo detach/attach event */ +static void host_enumeration_detect_fn(struct work_struct *work) +{ + /* If not enumerated and connected to a HOST */ + if (!atomic_read(&enumerated) && charger_connected()) + fsl_udc_redo_enumerate(); +} + +static DECLARE_DELAYED_WORK(host_enumeration_detect, host_enumeration_detect_fn); + +static void fsl_detect_charger_type(void) +{ + unsigned int portsc1; + + portsc1 = fsl_readl(&dr_regs->portsc1); + + if (charger_conn_probe) { + resume_ctrl(); + mdelay(10); + charger_conn_probe = 0; + if ((portsc1 & PORTSCX_LINE_STATUS_BITS) == PORTSCX_LINE_STATUS_UNDEF) { + post_charger_work(do_third_party_charger()); + + kobject_uevent_atomic(&udc_controller->gadget.dev.parent->kobj, KOBJ_ADD); + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_connected) < 0) + printk(KERN_ERR "Charger: Error creating device file\n"); + } + return; + } + + portsc1 = fsl_readl(&dr_regs->portsc1); + + if ((portsc1 & PORTSCX_LINE_STATUS_BITS) == PORTSCX_LINE_STATUS_UNDEF) { + post_charger_work(do_third_party_charger()); + + kobject_uevent_atomic(&udc_controller->gadget.dev.parent->kobj, KOBJ_ADD); + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_connected) < 0) + printk(KERN_ERR "Charger: Error creating device file\n"); + + goto out; + } + + if ((portsc1 & PORTSCX_LINE_STATUS_BITS) == PORTSCX_LINE_STATUS_KSTATE) { + pmic_start_charging(CHARGING_HOST); + + host_detected = 1; + + suspend_irq(udc_controller); + reset_irq(udc_controller); + + kobject_uevent_atomic(&udc_controller->gadget.dev.parent->kobj, KOBJ_ADD); + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_connected) < 0) + printk(KERN_ERR "Host: Error creating device file\n"); + + schedule_delayed_work(&third_party_work, msecs_to_jiffies(THIRD_PARTY_DETECT)); + goto out; + } + + if (portsc1 & PORTSCX_CURRENT_CONNECT_STATUS) { + /* Connect Status */ + if (portsc1 & PORTSCX_PORT_HSP) { + printk("Connected to a HIGH speed Host\n"); + udc_controller->gadget.speed = USB_SPEED_HIGH; + } + else { + printk("Connected to a non high speed Host\n"); + } + + if (!atomic_read(&enumerated)) + pmic_start_charging(CHARGING_HOST); + + kobject_uevent_atomic(&udc_controller->gadget.dev.parent->kobj, KOBJ_ADD); + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_connected) < 0) + printk(KERN_ERR "Host: Error creating device file\n"); + + schedule_delayed_work(&host_enumeration_detect, msecs_to_jiffies(HOST_ENU_DETECT)); + goto out; + } + + if (host_detected == 1) { + /* A host as already been detected */ + printk("Connected to a Host: %d\n", host_detected); + pmic_start_charging(CHARGING_HOST); + + kobject_uevent_atomic(&udc_controller->gadget.dev.parent->kobj, KOBJ_ADD); + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_connected) < 0) + printk(KERN_ERR "Host: Error creating device file\n"); + + goto out; + } + + if (!host_detected) { + post_charger_work(do_third_party_charger()); + + kobject_uevent_atomic(&udc_controller->gadget.dev.parent->kobj, KOBJ_ADD); + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_connected) < 0) + printk(KERN_ERR "Charger: Error creating device file\n"); + goto out; + } + + not_detected = 1; +out: + udc_detection = 1; +} + +static void do_charger_detect(struct work_struct *work) +{ + struct fsl_udc *udc = udc_controller; + unsigned int chrgraw = read_charger_voltage(); + + /* If already removed/suspended, exit */ + if (udc_suspended_mode) + return; + + if (charger_connected()) { + disable_accessory_gpo4(); + + /* Charging never started due to high input voltage */ + if (chrgraw >= CHRGRAW_THRESHOLD) { + printk(KERN_ERR "Charger not started due to over-voltage:%dmV\n", chrgraw); + chrgraw_disable = 1; + return; + } + + fsl_detect_charger_type(); + if (!green_led_set) + gpio_chrgled_active(1); + } + else { + fsl_idle_low_power_enter(udc); + ichrg_value = 0; + gpio_chrgled_active(0); + pmic_set_chg_current(0); + + /* Clear out bit #4 in MEMA */ + pmic_write_reg(REG_MEM_A, (0 << 4), (1 << 4)); + + /* Clear out saved ichrg value */ + saved_ichrg_value = 0; + + /* Clear out the variables */ + third_party_charger = 0; + wall_charger = 0; + + /* Clear the charger timer counter */ + charger_timer_expiry_counter = 0; + + /* Enable accessory charging */ + enable_accessory_gpo4(); + + /* Reset all the chrgraw counters */ + chrgraw_monitor = 0; + chrgraw_disable = 0; + } +} + +DECLARE_WORK(charger_detect_work, do_charger_detect); + +static void fsl_charger_type_detect(unsigned long data) +{ + schedule_work(&charger_detect_work); +} + +extern int usb_otg_gated_off; + +static void fsl_idle_low_power_exit(struct fsl_udc *udc) +{ + unsigned long flags; + + spin_lock_irqsave(&udc_pm_lock, flags); + + if (!udc->suspended) { + spin_unlock_irqrestore(&udc_pm_lock, flags); + return; + } + + usb_otg_gated_off = 0; + + /* First enable the clock */ + clk_enable(usb_ahb_clk); + udelay(1000); /* Propagation time after clock enable */ + + /* Enable the UTMI PHY - USBEN */ + USB_PHY_CTR_FUNC |= (0x1000000); + + /* Settling time */ + mdelay(100); + + /* Now reset the UTMI */ + USB_PHY_CTR_FUNC |= 0x2000000; + mdelay(20); + USB_PHY_CTR_FUNC &= ~(0x2000000); + mdelay(20); + + /* Next the port */ + resume_port(); + + /* Enable DR irq reg and set controller Run */ + if (udc_controller->stopped) { + dr_controller_setup(udc_controller); + dr_controller_run(udc_controller); + + udc_controller->stopped = 0; + udc_controller->usb_state = USB_STATE_ATTACHED; + udc_controller->ep0_state = WAIT_FOR_SETUP; + udc_controller->ep0_dir = 0; + } + + resume_ctrl(); + + udc->suspended = 0; + enable_irq(ARCOTG_IRQ); + bus_resume(udc); + + spin_unlock_irqrestore(&udc_pm_lock, flags); +} + +static void fsl_idle_low_power_enter(struct fsl_udc *udc) +{ + unsigned long flags; + + spin_lock_irqsave(&udc_pm_lock, flags); + + if (udc->suspended) { + spin_unlock_irqrestore(&udc_pm_lock, flags); + return; + } + + if (charger_connected()) { + spin_unlock_irqrestore(&udc_pm_lock, flags); + return; + } + + disable_irq(ARCOTG_IRQ); + udc->suspended = 1; + fsl_writel(0, &dr_regs->usbintr); + + /* Suspend PORT first */ + suspend_port(); + + /* Settling time */ + mdelay(20); + + /* Disable the UTMI PHY */ + USB_PHY_CTR_FUNC &= ~(0x1000000); + + /* Settling time */ + mdelay(100); + + /* Suspend Controller next */ + suspend_ctrl(); + + /* Settling time */ + mdelay(20); + + /* Tell upper stack that PHY suspended */ + clk_disable(usb_ahb_clk); + udc_detection = 0; + usb_otg_gated_off = 1; + udc->stopped = 1; + +#if defined(CONFIG_CPU_FREQ) + if (!charger_connected()) { + printk(KERN_INFO "Charger: Turning on CPUFreq\n"); + enable_cpufreq(); + } +#endif + spin_unlock_irqrestore(&udc_pm_lock, flags); +} + +/* + * Charger callback from Atlas + */ +static void callback_charger_detect(void *param) +{ + struct fsl_udc *udc = (struct fsl_udc *)param; + + /* + * Exit the low power mode before the detection is done + */ + if (charger_connected()) { + /* Do not charge if battery error is set - 1725 */ + if (luigi_battery_error_flags) + return; + +#if defined(CONFIG_CPU_FREQ) + printk(KERN_INFO "Charger: Setting CPU Frequeny to 512MHz\n"); + disable_cpufreq(); +#endif + fsl_idle_low_power_exit(udc); + } + else { + if (udc->driver && udc->driver->disconnect) + udc->driver->disconnect(&udc->gadget); + + udc_controller->gadget.configured = 0; + + device_remove_file(udc->gadget.dev.parent, &dev_attr_connected); + + kobject_uevent_atomic(&udc->gadget.dev.parent->kobj, KOBJ_REMOVE); + + pmic_enable_green_led(0); + green_led_set = 0; + pmic_set_chg_current(0); + + /* Clear out the variables */ + host_detected = 0; + atomic_set(&enumerated, 0); + charger_bpon = 0; + charger_conn_probe = 0; + charger_enumerated = 0; + + /* For HOST, make sure the FIFO Flush occurs */ + if (!udc_stopped) { + if (wall_charger || third_party_charger) + mod_timer(&udc->detect_timer, jiffies + (msecs_to_jiffies(CHARGER_CHARGER_REMOVE))); + else + mod_timer(&udc->detect_timer, jiffies + (msecs_to_jiffies(CHARGER_TYPE_REMOVE))); + + return; + } + } + + if (udc_stopped) { + udc_stopped = 0; + mod_timer(&udc->detect_timer, + jiffies + (msecs_to_jiffies(CHARGER_TYPE_SUSPEND))); + } + else + mod_timer(&udc->detect_timer, jiffies + (msecs_to_jiffies(CHARGER_TYPE))); +} + +static void callback_bpon_event(void *param) +{ + printk(KERN_INFO "callback_bpon_event\n"); + pmic_enable_bpon_charging(); +} + +/* + *! The charger timer is configured for 120 minutes in APLite. + * The charger is automatically turned off after 120 minutes of + * charging. Once this occurs, the APLite generates a CHGFAULT + * with the sense bits correctly set to "10" + */ +static void callback_faulti(void *param) +{ + int sense_0 = 0; + /* Bits 9 and 8 should be "10" to detect charger timer expiry */ + int charger_timer_mask = 0x200; + + /* + * According to the IEEE 1725 spec, the max charger timer + * should not exceed 6 hours or 360 minutes + */ + if (charger_timer_expiry_counter == 2) + return; + + pmic_read_reg(REG_INT_SENSE0, &sense_0, 0xffffff); + + printk(KERN_INFO "CHGFAULT occurred: 0x%x\n", sense_0); + + /* Restart charging if the charger timer has expired */ + if (sense_0 & charger_timer_mask) { + pmic_restart_charging(); + charger_timer_expiry_counter++; + } +} + +/*! + * The battery driver has already computed the voltage. So, do not redo + * this calculation as it unnecessary generates PMIC/SPI traffic every + * 10 seconds. Reuse the value unless battery error flags are set. + */ +static int read_supply_voltage(void) +{ + unsigned short bp = 0; + + if (!luigi_battery_error_flags) + return luigi_voltage; + + if (pmic_adc_convert(APPLICATION_SUPPLY, &bp)) { + printk(KERN_ERR "Charger: could not read APPLICATION_SUPPLY from adc\n"); + return -1; + } + + /* + * MC13892: Multiply the adc value by BATT_VOLTAGE_SCALE to get + * the battery value. This is from the Atlas Lite manual + */ + return bp*BATT_VOLTAGE_SCALE/1000; /* Return in mV */ +} + +/*! + * Read the PMIC A/D for Charger Voltage, i.e. CHGRAW + */ +static int read_charger_voltage(void) +{ + unsigned short bp = 0; + + if (pmic_adc_convert(CHARGE_VOLTAGE, &bp)) { + printk(KERN_ERR "Charger: could not read CHARGER_VOLTAGE from adc\n"); + return -1; + } + + return bp*CHARGE_VOLTAGE_SCALE/1000; /* Return in mV */ +} + +/*! + * Read the PMIC A/D for accurate LOBAT readings + */ +static int read_lobat_supply_voltage(void) +{ + unsigned short bp = 0; + + if (pmic_adc_convert(APPLICATION_SUPPLY, &bp)) { + printk(KERN_ERR "Charger: could not read APPLICATION_SUPPLY from adc\n"); + return -1; + } + + /* + * MC13892: Multiply the adc value by BATT_VOLTAGE_SCALE to get + * the battery value. This is from the Atlas Lite manual + */ + return bp*BATT_VOLTAGE_SCALE/1000; /* Return in mV */ +} + +static void lobat_work(void) +{ + int batt_voltage = read_supply_voltage(); + char *envp[] = { "BATTERY=wanon", NULL }; + + if (batt_voltage < 0) + return; + + if (udc_controller->lobathi == 1) { + udc_controller->lobathi = 0; + + if (batt_voltage > LOW_VOLTAGE_THRESHOLD) { + if (printk_ratelimit()) + printk(KERN_ERR "Charger: Atlas lobathi interrupt - %d\n", batt_voltage); + lobat_condition = 0; + //kobject_uevent_env(&udc_controller->gadget.dev.parent->kobj, KOBJ_CHANGE, envp); + goto out; + } + + post_lobat_event(0); + } + + if (udc_controller->lobatli == 1) { + udc_controller->lobatli = 0; + + if (batt_voltage > CRITICAL_VOLTAGE_THRESHOLD) { + if (printk_ratelimit()) + printk(KERN_ERR "Charger: Atlas lobatli interrupt - %d\n", batt_voltage); + lobat_condition = 0; + //kobject_uevent_env(&udc_controller->gadget.dev.parent->kobj, KOBJ_CHANGE, envp); + goto out; + } + + post_lobat_event(1); + } +out: + return; + +} + +/* + * LOBATHI event callback from Atlas + */ +static void callback_lobathi_event(void *param) +{ + udc_controller->lobathi = 1; + + lobat_work(); +} + +/* + * LOBATLI event callback from Atlas + */ +static void callback_lobatli_event(void *param) +{ + udc_controller->lobatli = 1; + + lobat_work(); +} + +/*---------------------------------------------------------------- + * Setup the fsl_ep struct for eps + * Link fsl_ep->ep to gadget->ep_list + * ep0out is not used so do nothing here + * ep0in should be taken care + *--------------------------------------------------------------*/ +static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index, + char *name, int link) +{ + struct fsl_ep *ep = &udc->eps[index]; + + ep->udc = udc; + strcpy(ep->name, name); + ep->ep.name = ep->name; + + ep->ep.ops = &fsl_ep_ops; + ep->stopped = 0; + + /* for ep0: maxP defined in desc + * for other eps, maxP is set by epautoconfig() called by gadget layer + */ + ep->ep.maxpacket = (unsigned short) ~0; + + /* the queue lists any req for this ep */ + INIT_LIST_HEAD(&ep->queue); + + /* gagdet.ep_list used for ep_autoconfig so no ep0 */ + if (link) + list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); + ep->gadget = &udc->gadget; + ep->qh = &udc->ep_qh[index]; + + return 0; +} + +extern void gpio_usbotg_oc_disable(int); +extern void mxc_kernel_uptime(void); + +/* Driver probe function + * all intialization operations implemented here except enabling usb_intr reg + * board setup should have been done in the platform code + */ +static int __init fsl_udc_probe(struct platform_device *pdev) +{ + struct resource *res; + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + int ret = -ENODEV; + unsigned int i; + u32 dccparams; + unsigned int reg_memory_a; + + if (strcmp(pdev->name, driver_name)) { + VDBG("Wrong device\n"); + return -ENODEV; + } + + udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL); + if (udc_controller == NULL) { + ERR("malloc udc failed\n"); + return -ENOMEM; + } + udc_controller->pdata = pdata; + +#ifdef CONFIG_USB_OTG + /* Memory and interrupt resources will be passed from OTG */ + udc_controller->transceiver = otg_get_transceiver(); + if (!udc_controller->transceiver) { + printk(KERN_ERR "Can't find OTG driver!\n"); + ret = -ENODEV; + goto err1a; + } + + res = otg_get_resources(); + if (!res) { + DBG("resource not registered!\n"); + return -ENODEV; + } +#else + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + ret = -ENXIO; + goto err1a; + } + + if (!request_mem_region(res->start, resource_size(res), + driver_name)) { + ERR("request mem region for %s failed \n", pdev->name); + ret = -EBUSY; + goto err1a; + } +#endif + dr_regs = ioremap(res->start, resource_size(res)); + if (!dr_regs) { + ret = -ENOMEM; + goto err1; + } + pdata->regs = (void *)dr_regs; + /* + * do platform specific init: check the clock, grab/config pins, etc. + */ + if (pdata->platform_init && pdata->platform_init(pdev)) { + ret = -ENODEV; + goto err2a; + } + + if (pdata->have_sysif_regs) + usb_sys_regs = (struct usb_sys_interface *) + ((u32)dr_regs + USB_DR_SYS_OFFSET); + + /* Read Device Controller Capability Parameters register */ + dccparams = fsl_readl(&dr_regs->dccparams); + if (!(dccparams & DCCPARAMS_DC)) { + ERR("This SOC doesn't support device role\n"); + ret = -ENODEV; + goto err2; + } + /* Get max device endpoints */ + /* DEN is bidirectional ep number, max_ep doubles the number */ + udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2; + +#ifdef CONFIG_USB_OTG + res++; + udc_controller->irq = res->start; +#else + udc_controller->irq = platform_get_irq(pdev, 0); +#endif + if (!udc_controller->irq) { + ret = -ENODEV; + goto err2; + } + + ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_DISABLED, + driver_name, udc_controller); + if (ret != 0) { + ERR("cannot request irq %d err %d \n", + udc_controller->irq, ret); + goto err2; + } + + /* Initialize the udc structure including QH member and other member */ + if (struct_udc_setup(udc_controller, pdev)) { + ERR("Can't initialize udc data structure\n"); + ret = -ENOMEM; + goto err3; + } + + if (!udc_controller->transceiver) { + /* initialize usb hw reg except for regs for EP, + * leave usbintr reg untouched */ + dr_controller_setup(udc_controller); + } + + INIT_DELAYED_WORK(&udc_controller->charger_detect_work, do_charger_detect_work); + schedule_delayed_work(&udc_controller->charger_detect_work, msecs_to_jiffies(CHARGER_STARTUP)); + usb_ahb_clk = clk_get(NULL, "usb_ahb_clk"); + + /* Setup gadget structure */ + udc_controller->gadget.ops = &fsl_gadget_ops; + udc_controller->gadget.is_dualspeed = 1; + udc_controller->gadget.ep0 = &udc_controller->eps[0].ep; + INIT_LIST_HEAD(&udc_controller->gadget.ep_list); + udc_controller->gadget.speed = USB_SPEED_UNKNOWN; + udc_controller->gadget.name = driver_name; + + /* Setup gadget.dev and register with kernel */ + strcpy(udc_controller->gadget.dev.bus_id, "gadget"); + udc_controller->gadget.dev.release = fsl_udc_release; + udc_controller->gadget.dev.parent = &pdev->dev; + ret = device_register(&udc_controller->gadget.dev); + if (ret < 0) + goto err3; + + if (udc_controller->transceiver) + udc_controller->gadget.is_otg = 1; + + /* setup QH and epctrl for ep0 */ + ep0_setup(udc_controller); + + /* setup udc->eps[] for ep0 */ + struct_ep_setup(udc_controller, 0, "ep0", 0); + /* for ep0: the desc defined here; + * for other eps, gadget layer called ep_enable with defined desc + */ + udc_controller->eps[0].desc = &fsl_ep0_desc; + udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD; + + /* setup the udc->eps[] for non-control endpoints and link + * to gadget.ep_list */ + for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) { + char name[14]; + + sprintf(name, "ep%dout", i); + struct_ep_setup(udc_controller, i * 2, name, 1); + udc_controller->eps[i*2].desc = &fsl_ep1_desc; + sprintf(name, "ep%din", i); + struct_ep_setup(udc_controller, i * 2 + 1, name, 1); + udc_controller->eps[i*2+1].desc=&fsl_ep1_desc; + } + + /* use dma_pool for TD management */ + udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev, + sizeof(struct ep_td_struct), + DTD_ALIGNMENT, UDC_DMA_BOUNDARY); + if (udc_controller->td_pool == NULL) { + ret = -ENOMEM; + goto err4; + } + + /* The charger detect work timer */ + init_timer(&udc_controller->detect_timer); + udc_controller->detect_timer.data = (unsigned long) udc_controller; + udc_controller->detect_timer.function = fsl_charger_type_detect; + + /* + * Charger + */ + charger_detect.param = (void *)udc_controller; + charger_detect.func = callback_charger_detect; + CHECK_ERROR(pmic_event_subscribe(EVENT_CHGDETI, charger_detect)); + + lobatli_event.param = (void *)udc_controller; + lobatli_event.func = callback_lobatli_event; + CHECK_ERROR(pmic_event_subscribe(EVENT_LOBATLI, lobatli_event)); + + lobathi_event.param = (void *)udc_controller; + lobathi_event.func = callback_lobathi_event; + CHECK_ERROR(pmic_event_subscribe(EVENT_LOBATHI, lobathi_event)); + + bpon_event.param = (void *)udc_controller; + bpon_event.func = callback_bpon_event; + CHECK_ERROR(pmic_event_subscribe(EVENT_BPONI, bpon_event)); + + chgfaulti_event.param = (void *)udc_controller; + chgfaulti_event.func = callback_faulti; + CHECK_ERROR(pmic_event_subscribe(EVENT_CHGFAULTI, chgfaulti_event)); + + /* Set the BPSNS */ + CHECK_ERROR(pmic_write_reg(PMIC_REG_PC_0, BPSNS_VALUE << BPSNS_OFFSET, + BPSNS_MASK << BPSNS_OFFSET)); + + /* If bit is already set, then it is a fall through */ + pmic_read_reg(REG_MEM_A, ®_memory_a, (0x1f << 0)); + if (reg_memory_a & 0x10) + printk(KERN_ERR "boot: I def:crit:Booting out of critical battery:\n"); + + /* Clear out bit #4 in MEMA */ + pmic_write_reg(REG_MEM_A, (0 << 4), (1 << 4)); + + if (charger_connected()) { + charger_conn_probe = 1; + printk("USB/Charger detected\n"); + /* + * The module is just loaded, check capacity. If <= 4%, + * then we are surely in recovery utils + */ + if (luigi_battery_capacity <= CHARGER_BOOT_THRESHOLD) { + /* Turn on bit #4 */ + pmic_write_reg(REG_MEM_A, (1 << 4), (1 << 4)); + crit_boot_flag = 1; + } + } + + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_charging) < 0) + printk(KERN_ERR "Charger: Error creating device charging file\n"); + + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_lobat_condition) < 0) + printk(KERN_ERR "Charger: Error creating device lobat_condition file\n"); + + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_supply_voltage) < 0) + printk(KERN_ERR "Charger: Error creating supply voltage file\n"); + + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_ichrg_setting) < 0) + printk(KERN_ERR "Charger: Error creating ichrg_setting file\n"); + + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_voltage) < 0) + printk(KERN_ERR "Charger: Error creating battery voltage file\n"); + + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_battery_current) < 0) + printk(KERN_ERR "Charger: Error creating battery current file\n"); + + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_batt_error) < 0) + printk(KERN_ERR "Charger: Error creating batt_error file\n"); + + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_charger_state) < 0) + printk(KERN_ERR "Charger: Error creating charger_state file\n"); + + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_chrgled_state) < 0) + printk(KERN_ERR "Charger: Error creating chrgled_state file\n"); + + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_battery_id) < 0) + printk(KERN_ERR "Charger: Error creating battery_id file\n"); + + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_third_party) < 0) + printk(KERN_ERR "Charger: Error creating third_party_charger file\n"); + + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_bpsns) < 0) + printk(KERN_ERR "Charger: Error creating bpsns file\n"); + + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_charger_lobath_unsub) < 0) + printk(KERN_ERR "Charger: Error creating charger_lobath_unsub file\n"); + + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_green_led_threshold) < 0) + printk(KERN_ERR "Charger: Error creating green_led_threshold file\n"); + + if (device_create_file(udc_controller->gadget.dev.parent, + &dev_attr_charger_adc_voltage) < 0) + printk(KERN_ERR "Charger: Error creating charger_adc_voltage file\n"); + + INIT_WORK(&udc_controller->usbtest_work, usbtest_workqueue_handler); + + schedule_delayed_work(&charger_misc_work, msecs_to_jiffies(CHARGER_MISC)); + + fsl_udc_init_debugfs(udc_controller); + + udc_controller->lobatli = 0; + udc_controller->lobathi = 0; + + gpio_usbotg_oc_disable(1); + + /* Now reset the UTMI */ + USB_PHY_CTR_FUNC |= 0x2000000; + msleep(20); + USB_PHY_CTR_FUNC &= ~(0x2000000); + msleep(20); + + printk(KERN_INFO "kernel: I perf:usb:usb_gadget_loaded="); + mxc_kernel_uptime(); + + return 0; + +err4: + device_unregister(&udc_controller->gadget.dev); +err3: + free_irq(udc_controller->irq, udc_controller); +err2: + if (pdata->platform_uninit) + pdata->platform_uninit(pdata); +err2a: + iounmap((u8 __iomem *)dr_regs); +err1: + if (!udc_controller->transceiver) + release_mem_region(res->start, resource_size(res)); +err1a: + kfree(udc_controller); + udc_controller = NULL; + return ret; +} + +/* Driver removal function + * Free resources and finish pending transactions + */ +static int __exit fsl_udc_remove(struct platform_device *pdev) +{ + struct resource *res; + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + DECLARE_COMPLETION(done); + + if (!udc_controller) + return -ENODEV; + + udc_suspended_mode = 1; + cancel_rearming_delayed_work(&charger_misc_work); + del_timer_sync(&udc_controller->detect_timer); + cancel_rearming_delayed_work(&udc_controller->charger_detect_work); + cancel_rearming_delayed_work(&pc_wq); + cancel_rearming_delayed_work(&third_party_work); + cancel_rearming_delayed_work(&host_enumeration_detect); + cancel_rearming_delayed_work(&phy_resume_work); + + udc_controller->done = &done; + + /* DR has been stopped in usb_gadget_unregister_driver() */ + + fsl_udc_cleanup_debugfs(udc_controller); + + /* Free allocated memory */ + kfree(udc_controller->status_req->req.buf); + kfree(udc_controller->status_req); + kfree(udc_controller->eps); + + dma_pool_destroy(udc_controller->td_pool); + free_irq(udc_controller->irq, udc_controller); + iounmap((u8 __iomem *)dr_regs); + + kobject_uevent(&udc_controller->gadget.dev.parent->kobj, KOBJ_REMOVE); + + device_remove_file(udc_controller->gadget.dev.parent, &dev_attr_connected); + device_remove_file(udc_controller->gadget.dev.parent, &dev_attr_charging); + device_remove_file(udc_controller->gadget.dev.parent, &dev_attr_lobat_condition); + device_remove_file(udc_controller->gadget.dev.parent, &dev_attr_supply_voltage); + device_remove_file(udc_controller->gadget.dev.parent, &dev_attr_ichrg_setting); + device_remove_file(udc_controller->gadget.dev.parent, &dev_attr_voltage); + device_remove_file(udc_controller->gadget.dev.parent, &dev_attr_battery_current); + device_remove_file(udc_controller->gadget.dev.parent, &dev_attr_batt_error); + device_remove_file(udc_controller->gadget.dev.parent, &dev_attr_charger_state); + device_remove_file(udc_controller->gadget.dev.parent, &dev_attr_chrgled_state); + device_remove_file(udc_controller->gadget.dev.parent, &dev_attr_battery_id); + device_remove_file(udc_controller->gadget.dev.parent, &dev_attr_third_party); + device_remove_file(udc_controller->gadget.dev.parent, &dev_attr_bpsns); + device_remove_file(udc_controller->gadget.dev.parent, &dev_attr_charger_lobath_unsub); + device_remove_file(udc_controller->gadget.dev.parent, &dev_attr_green_led_threshold); + device_remove_file(udc_controller->gadget.dev.parent, &dev_attr_charger_adc_voltage); + + /* Charger */ + CHECK_ERROR(pmic_event_unsubscribe(EVENT_CHGDETI, charger_detect)); + CHECK_ERROR(pmic_event_unsubscribe(EVENT_LOBATLI, lobatli_event)); + CHECK_ERROR(pmic_event_unsubscribe(EVENT_LOBATHI, lobathi_event)); + CHECK_ERROR(pmic_event_unsubscribe(EVENT_BPONI, bpon_event)); + CHECK_ERROR(pmic_event_unsubscribe(EVENT_CHGFAULTI, chgfaulti_event)); + + clk_put(usb_ahb_clk); + udc_controller->lobatli = 0; + udc_controller->lobathi = 0; + +#ifndef CONFIG_USB_OTG + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, resource_size(res)); +#endif + + device_unregister(&udc_controller->gadget.dev); + /* free udc --wait for the release() finished */ + wait_for_completion(&done); + + /* + * do platform specific un-initialization: + * release iomux pins, etc. + */ + if (pdata->platform_uninit) + pdata->platform_uninit(pdata); + + gpio_usbotg_oc_disable(0); + + return 0; +} + +static int udc_suspend(struct fsl_udc *udc) +{ + udc->stopped = 1; + return 0; +} + +/*----------------------------------------------------------------- + * Modify Power management attributes + * Used by OTG statemachine to disable gadget temporarily + -----------------------------------------------------------------*/ +static int fsl_udc_suspend(struct device *dev, pm_message_t state) +{ + cancel_rearming_delayed_work(&charger_misc_work); + return udc_suspend(udc_controller); +} + +/*----------------------------------------------------------------- + * Invoked on USB resume. May be called in_interrupt. + * Here we start the DR controller and enable the irq + *-----------------------------------------------------------------*/ +static int fsl_udc_resume(struct device *dev) +{ + /* Enable DR irq reg and set controller Run */ + if (udc_controller->stopped) { + dr_controller_setup(udc_controller); + dr_controller_run(udc_controller); + } + udc_controller->usb_state = USB_STATE_ATTACHED; + udc_controller->ep0_state = WAIT_FOR_SETUP; + udc_controller->ep0_dir = 0; + return 0; +} + +static int arcotg_suspend(struct platform_device *pdev, pm_message_t state) +{ + int batt_voltage = 0; + + pmic_write_reg(PMIC_REG_PC_0, BPSNS_VALUE_SUSPEND << BPSNS_OFFSET, + BPSNS_MASK << BPSNS_OFFSET); + + if (mxc_spi_suspended) + batt_voltage = read_supply_voltage(); + else + batt_voltage = read_lobat_supply_voltage(); + + if (batt_voltage && (batt_voltage <= CHRG_SUS_LOW_VOLTAGE)) + return -EBUSY; + + dump_mAH_stats(); + + udc_suspended_mode = 1; + cancel_rearming_delayed_work(&charger_misc_work); + udc_stopped = 1; + gpio_chrgled_active(0); + return 0; +} + +/*! Phy low power on resumw */ +static void phy_low_power_resume(struct work_struct *work) +{ + if (!charger_connected()) { + udc_stopped = 0; + printk(KERN_INFO "arcotg_udc: Putting Phy in low power mode\n"); + } + pmic_write_reg(PMIC_REG_PC_0, BPSNS_VALUE << BPSNS_OFFSET, + BPSNS_MASK << BPSNS_OFFSET); +} + +extern void arch_reset(char mode); +static void fsl_udc_shutdown(struct platform_device *pdev) +{ + printk(KERN_INFO "Charger shutdown\n"); + + /* See if lobat has been hit and charger is connected */ + if (lobat_event_posted && charger_connected()) + arch_reset((char)0); +} + +static int arcotg_resume(struct platform_device *pdev) +{ + udc_suspended_mode = 0; + schedule_delayed_work(&charger_misc_work, msecs_to_jiffies(CHARGER_MISC)); + schedule_delayed_work(&phy_resume_work, msecs_to_jiffies(PHY_LPM_TIMER)); + return 0; +} + +/*------------------------------------------------------------------------- + Register entry point for the peripheral controller driver +--------------------------------------------------------------------------*/ + +static struct platform_driver udc_driver = { + .remove = __exit_p(fsl_udc_remove), + /* these suspend and resume are not usb suspend and resume */ + .suspend = arcotg_suspend, + .resume = arcotg_resume, + .probe = fsl_udc_probe, + .shutdown = fsl_udc_shutdown, + .driver = { + .name = driver_name, + .owner = THIS_MODULE, + }, +}; + +static int __init udc_init(void) +{ + printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION); + return platform_driver_register(&udc_driver); +} + +module_init(udc_init); + +static void __exit udc_exit(void) +{ + platform_driver_unregister(&udc_driver); + printk(KERN_INFO "%s unregistered \n", driver_desc); +} + +module_exit(udc_exit); + +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/usb/gadget/arcotg_udc.h linux-2.6.26-lab126/drivers/usb/gadget/arcotg_udc.h --- linux-2.6.26/drivers/usb/gadget/arcotg_udc.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/usb/gadget/arcotg_udc.h 2010-08-10 04:17:11.000000000 -0400 @@ -0,0 +1,686 @@ +/* + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file arcotg_udc.h + * @brief Freescale USB device/endpoint management registers + * @ingroup USB + */ + +#ifndef __ARCOTG_UDC_H +#define __ARCOTG_UDC_H + +#define TRUE 1 +#define FALSE 0 + +#define MSC_BULK_CB_WRAP_LEN 31 +#define USE_MSC_WR(len) ((cpu_is_mx37_rev(CHIP_REV_1_0) == 1) && \ + ((len) == MSC_BULK_CB_WRAP_LEN)) + +#ifdef CONFIG_USB_STATIC_IRAM_PPH +#define IRAM_TD_PPH_SIZE (USB_IRAM_SIZE / 2) +#define IRAM_PPH_NTD 2 +#else +#define IRAM_TD_PPH_SIZE 0 +#define IRAM_PPH_NTD 0 +#endif + +#ifndef USB_IRAM_BASE_ADDR +#define USB_IRAM_BASE_ADDR 0 +#endif + +/* Don't use IRAM if it is already being used by Sound */ +#ifdef CONFIG_SND_MXC_SOC_IRAM +#define NEED_IRAM(ep) 0 +#else +#define NEED_IRAM(ep) ((g_iram_size) && \ + ((ep)->desc->bmAttributes == USB_ENDPOINT_XFER_BULK)) +#endif + +/* ### define USB registers here + */ +#define USB_MAX_ENDPOINTS 8 +#define USB_MAX_PIPES (USB_MAX_ENDPOINTS*2) +#define USB_MAX_CTRL_PAYLOAD 64 +#define USB_DR_SYS_OFFSET 0x400 + +#define USB_DR_OFFSET 0x3100 + +struct usb_dr_device { + /* Capability register */ + u32 id; + u32 res1[35]; + u32 sbuscfg; /* sbuscfg ahb burst */ + u32 res11[27]; + u16 caplength; /* Capability Register Length */ + u16 hciversion; /* Host Controller Interface Version */ + u32 hcsparams; /* Host Controller Structual Parameters */ + u32 hccparams; /* Host Controller Capability Parameters */ + u32 res2[5]; + u32 dciversion; /* Device Controller Interface Version */ + u32 dccparams; /* Device Controller Capability Parameters */ + u32 res3[6]; + /* Operation register */ + u32 usbcmd; /* USB Command Register */ + u32 usbsts; /* USB Status Register */ + u32 usbintr; /* USB Interrupt Enable Register */ + u32 frindex; /* Frame Index Register */ + u32 res4; + u32 deviceaddr; /* Device Address */ + u32 endpointlistaddr; /* Endpoint List Address Register */ + u32 res5; + u32 burstsize; /* Master Interface Data Burst Size Register */ + u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ + u32 res6[6]; + u32 configflag; /* Configure Flag Register */ + u32 portsc1; /* Port 1 Status and Control Register */ + u32 res7[7]; + u32 otgsc; /* On-The-Go Status and Control */ + u32 usbmode; /* USB Mode Register */ + u32 endptsetupstat; /* Endpoint Setup Status Register */ + u32 endpointprime; /* Endpoint Initialization Register */ + u32 endptflush; /* Endpoint Flush Register */ + u32 endptstatus; /* Endpoint Status Register */ + u32 endptcomplete; /* Endpoint Complete Register */ + u32 endptctrl[8 * 2]; /* Endpoint Control Registers */ +}; + + /* non-EHCI USB system interface registers (Big Endian) */ +struct usb_sys_interface { + u32 snoop1; + u32 snoop2; + u32 age_cnt_thresh; /* Age Count Threshold Register */ + u32 pri_ctrl; /* Priority Control Register */ + u32 si_ctrl; /* System Interface Control Register */ + u8 res[236]; + u32 control; /* General Purpose Control Register */ +}; + +/* ep0 transfer state */ +#define WAIT_FOR_SETUP 0 +#define DATA_STATE_XMIT 1 +#define DATA_STATE_NEED_ZLP 2 +#define WAIT_FOR_OUT_STATUS 3 +#define DATA_STATE_RECV 4 + +/* Device Controller Capability Parameter register */ +#define DCCPARAMS_DC 0x00000080 +#define DCCPARAMS_DEN_MASK 0x0000001f + +/* Frame Index Register Bit Masks */ +#define USB_FRINDEX_MASKS (0x3fff) +/* USB CMD Register Bit Masks */ +#define USB_CMD_RUN_STOP (0x00000001) +#define USB_CMD_CTRL_RESET (0x00000002) +#define USB_CMD_PERIODIC_SCHEDULE_EN (0x00000010) +#define USB_CMD_ASYNC_SCHEDULE_EN (0x00000020) +#define USB_CMD_INT_AA_DOORBELL (0x00000040) +#define USB_CMD_ASP (0x00000300) +#define USB_CMD_ASYNC_SCH_PARK_EN (0x00000800) +#define USB_CMD_SUTW (0x00002000) +#define USB_CMD_ATDTW (0x00004000) +#define USB_CMD_ITC (0x00FF0000) + +/* bit 15,3,2 are frame list size */ +#define USB_CMD_FRAME_SIZE_1024 (0x00000000) +#define USB_CMD_FRAME_SIZE_512 (0x00000004) +#define USB_CMD_FRAME_SIZE_256 (0x00000008) +#define USB_CMD_FRAME_SIZE_128 (0x0000000C) +#define USB_CMD_FRAME_SIZE_64 (0x00008000) +#define USB_CMD_FRAME_SIZE_32 (0x00008004) +#define USB_CMD_FRAME_SIZE_16 (0x00008008) +#define USB_CMD_FRAME_SIZE_8 (0x0000800C) + +/* bit 9-8 are async schedule park mode count */ +#define USB_CMD_ASP_00 (0x00000000) +#define USB_CMD_ASP_01 (0x00000100) +#define USB_CMD_ASP_10 (0x00000200) +#define USB_CMD_ASP_11 (0x00000300) +#define USB_CMD_ASP_BIT_POS (8) + +/* bit 23-16 are interrupt threshold control */ +#define USB_CMD_ITC_NO_THRESHOLD (0x00000000) +#define USB_CMD_ITC_1_MICRO_FRM (0x00010000) +#define USB_CMD_ITC_2_MICRO_FRM (0x00020000) +#define USB_CMD_ITC_4_MICRO_FRM (0x00040000) +#define USB_CMD_ITC_8_MICRO_FRM (0x00080000) +#define USB_CMD_ITC_16_MICRO_FRM (0x00100000) +#define USB_CMD_ITC_32_MICRO_FRM (0x00200000) +#define USB_CMD_ITC_64_MICRO_FRM (0x00400000) +#define USB_CMD_ITC_BIT_POS (16) + +/* USB STS Register Bit Masks */ +#define USB_STS_INT (0x00000001) +#define USB_STS_ERR (0x00000002) +#define USB_STS_PORT_CHANGE (0x00000004) +#define USB_STS_FRM_LST_ROLL (0x00000008) +#define USB_STS_SYS_ERR (0x00000010) +#define USB_STS_IAA (0x00000020) +#define USB_STS_RESET (0x00000040) +#define USB_STS_SOF (0x00000080) +#define USB_STS_SUSPEND (0x00000100) +#define USB_STS_HC_HALTED (0x00001000) +#define USB_STS_RCL (0x00002000) +#define USB_STS_PERIODIC_SCHEDULE (0x00004000) +#define USB_STS_ASYNC_SCHEDULE (0x00008000) + +/* USB INTR Register Bit Masks */ +#define USB_INTR_INT_EN (0x00000001) +#define USB_INTR_ERR_INT_EN (0x00000002) +#define USB_INTR_PTC_DETECT_EN (0x00000004) +#define USB_INTR_FRM_LST_ROLL_EN (0x00000008) +#define USB_INTR_SYS_ERR_EN (0x00000010) +#define USB_INTR_ASYN_ADV_EN (0x00000020) +#define USB_INTR_RESET_EN (0x00000040) +#define USB_INTR_SOF_EN (0x00000080) +#define USB_INTR_DEVICE_SUSPEND (0x00000100) + +/* Device Address bit masks */ +#define USB_DEVICE_ADDRESS_MASK (0xFE000000) +#define USB_DEVICE_ADDRESS_BIT_POS (25) + +/* endpoint list address bit masks */ +#define USB_EP_LIST_ADDRESS_MASK (0xfffff800) + +/* PORTSCX Register Bit Masks */ +#define PORTSCX_CURRENT_CONNECT_STATUS (0x00000001) +#define PORTSCX_CONNECT_STATUS_CHANGE (0x00000002) +#define PORTSCX_PORT_ENABLE (0x00000004) +#define PORTSCX_PORT_EN_DIS_CHANGE (0x00000008) +#define PORTSCX_OVER_CURRENT_ACT (0x00000010) +#define PORTSCX_OVER_CURRENT_CHG (0x00000020) +#define PORTSCX_PORT_FORCE_RESUME (0x00000040) +#define PORTSCX_PORT_SUSPEND (0x00000080) +#define PORTSCX_PORT_RESET (0x00000100) +#define PORTSCX_PORT_HSP (0x00000200) +#define PORTSCX_LINE_STATUS_BITS (0x00000C00) +#define PORTSCX_PORT_POWER (0x00001000) +#define PORTSCX_PORT_INDICTOR_CTRL (0x0000C000) +#define PORTSCX_PORT_TEST_CTRL (0x000F0000) +#define PORTSCX_WAKE_ON_CONNECT_EN (0x00100000) +#define PORTSCX_WAKE_ON_CONNECT_DIS (0x00200000) +#define PORTSCX_WAKE_ON_OVER_CURRENT (0x00400000) +#define PORTSCX_PHY_LOW_POWER_SPD (0x00800000) +#define PORTSCX_PORT_FORCE_FULL_SPEED (0x01000000) +#define PORTSCX_PORT_SPEED_MASK (0x0C000000) +#define PORTSCX_PORT_WIDTH (0x10000000) +#define PORTSCX_PHY_TYPE_SEL (0xC0000000) + +/* bit 11-10 are line status */ +#define PORTSCX_LINE_STATUS_SE0 (0x00000000) +#define PORTSCX_LINE_STATUS_JSTATE (0x00000400) +#define PORTSCX_LINE_STATUS_KSTATE (0x00000800) +#define PORTSCX_LINE_STATUS_UNDEF (0x00000C00) +#define PORTSCX_LINE_STATUS_BIT_POS (10) + +/* bit 15-14 are port indicator control */ +#define PORTSCX_PIC_OFF (0x00000000) +#define PORTSCX_PIC_AMBER (0x00004000) +#define PORTSCX_PIC_GREEN (0x00008000) +#define PORTSCX_PIC_UNDEF (0x0000C000) +#define PORTSCX_PIC_BIT_POS (14) + +/* bit 19-16 are port test control */ +#define PORTSCX_PTC_DISABLE (0x00000000) +#define PORTSCX_PTC_JSTATE (0x00010000) +#define PORTSCX_PTC_KSTATE (0x00020000) +#define PORTSCX_PTC_SEQNAK (0x00030000) +#define PORTSCX_PTC_PACKET (0x00040000) +#define PORTSCX_PTC_FORCE_EN (0x00050000) +#define PORTSCX_PTC_BIT_POS (16) + +/* bit 27-26 are port speed */ +#define PORTSCX_PORT_SPEED_FULL (0x00000000) +#define PORTSCX_PORT_SPEED_LOW (0x04000000) +#define PORTSCX_PORT_SPEED_HIGH (0x08000000) +#define PORTSCX_PORT_SPEED_UNDEF (0x0C000000) +#define PORTSCX_SPEED_BIT_POS (26) + +/* bit 28 is parallel transceiver width for UTMI interface */ +#define PORTSCX_PTW (0x10000000) +#define PORTSCX_PTW_8BIT (0x00000000) +#define PORTSCX_PTW_16BIT (0x10000000) + +/* bit 31-30 are port transceiver select */ +#define PORTSCX_PTS_UTMI (0x00000000) +#define PORTSCX_PTS_ULPI (0x80000000) +#define PORTSCX_PTS_FSLS (0xC0000000) +#define PORTSCX_PTS_BIT_POS (30) + +/* USB MODE Register Bit Masks */ +#define USB_MODE_CTRL_MODE_IDLE (0x00000000) +#define USB_MODE_CTRL_MODE_DEVICE (0x00000002) +#define USB_MODE_CTRL_MODE_HOST (0x00000003) +#define USB_MODE_CTRL_MODE_MASK 0x00000003 +#define USB_MODE_CTRL_MODE_RSV (0x00000001) +#define USB_MODE_ES 0x00000004 /* (big) Endian Sel */ +#define USB_MODE_SETUP_LOCK_OFF (0x00000008) +#define USB_MODE_STREAM_DISABLE (0x00000010) +/* Endpoint Flush Register */ +#define EPFLUSH_TX_OFFSET (0x00010000) +#define EPFLUSH_RX_OFFSET (0x00000000) + +/* Endpoint Setup Status bit masks */ +#define EP_SETUP_STATUS_MASK (0x0000003F) +#define EP_SETUP_STATUS_EP0 (0x00000001) + +/* ENDPOINTCTRLx Register Bit Masks */ +#define EPCTRL_TX_ENABLE (0x00800000) +#define EPCTRL_TX_DATA_TOGGLE_RST (0x00400000) /* Not EP0 */ +#define EPCTRL_TX_DATA_TOGGLE_INH (0x00200000) /* Not EP0 */ +#define EPCTRL_TX_TYPE (0x000C0000) +#define EPCTRL_TX_DATA_SOURCE (0x00020000) /* Not EP0 */ +#define EPCTRL_TX_EP_STALL (0x00010000) +#define EPCTRL_RX_ENABLE (0x00000080) +#define EPCTRL_RX_DATA_TOGGLE_RST (0x00000040) /* Not EP0 */ +#define EPCTRL_RX_DATA_TOGGLE_INH (0x00000020) /* Not EP0 */ +#define EPCTRL_RX_TYPE (0x0000000C) +#define EPCTRL_RX_DATA_SINK (0x00000002) /* Not EP0 */ +#define EPCTRL_RX_EP_STALL (0x00000001) + +/* bit 19-18 and 3-2 are endpoint type */ +#define EPCTRL_EP_TYPE_CONTROL (0) +#define EPCTRL_EP_TYPE_ISO (1) +#define EPCTRL_EP_TYPE_BULK (2) +#define EPCTRL_EP_TYPE_INTERRUPT (3) +#define EPCTRL_TX_EP_TYPE_SHIFT (18) +#define EPCTRL_RX_EP_TYPE_SHIFT (2) + +/* SNOOPn Register Bit Masks */ +#define SNOOP_ADDRESS_MASK (0xFFFFF000) +#define SNOOP_SIZE_ZERO (0x00) /* snooping disable */ +#define SNOOP_SIZE_4KB (0x0B) /* 4KB snoop size */ +#define SNOOP_SIZE_8KB (0x0C) +#define SNOOP_SIZE_16KB (0x0D) +#define SNOOP_SIZE_32KB (0x0E) +#define SNOOP_SIZE_64KB (0x0F) +#define SNOOP_SIZE_128KB (0x10) +#define SNOOP_SIZE_256KB (0x11) +#define SNOOP_SIZE_512KB (0x12) +#define SNOOP_SIZE_1MB (0x13) +#define SNOOP_SIZE_2MB (0x14) +#define SNOOP_SIZE_4MB (0x15) +#define SNOOP_SIZE_8MB (0x16) +#define SNOOP_SIZE_16MB (0x17) +#define SNOOP_SIZE_32MB (0x18) +#define SNOOP_SIZE_64MB (0x19) +#define SNOOP_SIZE_128MB (0x1A) +#define SNOOP_SIZE_256MB (0x1B) +#define SNOOP_SIZE_512MB (0x1C) +#define SNOOP_SIZE_1GB (0x1D) +#define SNOOP_SIZE_2GB (0x1E) /* 2GB snoop size */ + +/* pri_ctrl Register Bit Masks */ +#define PRI_CTRL_PRI_LVL1 (0x0000000C) +#define PRI_CTRL_PRI_LVL0 (0x00000003) + +/* si_ctrl Register Bit Masks */ +#define SI_CTRL_ERR_DISABLE (0x00000010) +#define SI_CTRL_IDRC_DISABLE (0x00000008) +#define SI_CTRL_RD_SAFE_EN (0x00000004) +#define SI_CTRL_RD_PREFETCH_DISABLE (0x00000002) +#define SI_CTRL_RD_PREFEFETCH_VAL (0x00000001) + +/* control Register Bit Masks */ +#define USB_CTRL_IOENB (0x00000004) +#define USB_CTRL_ULPI_INT0EN (0x00000001) + +/*! + * Endpoint Queue Head data struct + * Rem: all the variables of qh are LittleEndian Mode + * and NEXT_POINTER_MASK should operate on a LittleEndian, Phy Addr + */ +struct ep_queue_head { + /*! + * Mult(31-30) , Zlt(29) , Max Pkt len and IOS(15) + */ + u32 max_pkt_length; + + /*! + * Current dTD Pointer(31-5) + */ + u32 curr_dtd_ptr; + + /*! + * Next dTD Pointer(31-5), T(0) + */ + u32 next_dtd_ptr; + + /*! + * Total bytes (30-16), IOC (15), MultO(11-10), STS (7-0) + */ + u32 size_ioc_int_sts; + + /*! + * Buffer pointer Page 0 (31-12) + */ + u32 buff_ptr0; + + /*! + * Buffer pointer Page 1 (31-12) + */ + u32 buff_ptr1; + + /*! + * Buffer pointer Page 2 (31-12) + */ + u32 buff_ptr2; + + /*! + * Buffer pointer Page 3 (31-12) + */ + u32 buff_ptr3; + + /*! + * Buffer pointer Page 4 (31-12) + */ + u32 buff_ptr4; + + /*! + * reserved field 1 + */ + u32 res1; + /*! + * Setup data 8 bytes + */ + u8 setup_buffer[8]; /* Setup data 8 bytes */ + + /*! + * reserved field 2,pad out to 64 bytes + */ + u32 res2[4]; +}; + +/* Endpoint Queue Head Bit Masks */ +#define EP_QUEUE_HEAD_MULT_POS (30) +#define EP_QUEUE_HEAD_ZLT_SEL (0x20000000) +#define EP_QUEUE_HEAD_MAX_PKT_LEN_POS (16) +#define EP_QUEUE_HEAD_MAX_PKT_LEN(ep_info) (((ep_info)>>16)&0x07ff) +#define EP_QUEUE_HEAD_IOS (0x00008000) +#define EP_QUEUE_HEAD_NEXT_TERMINATE (0x00000001) +#define EP_QUEUE_HEAD_IOC (0x00008000) +#define EP_QUEUE_HEAD_MULTO (0x00000C00) +#define EP_QUEUE_HEAD_STATUS_HALT (0x00000040) +#define EP_QUEUE_HEAD_STATUS_ACTIVE (0x00000080) +#define EP_QUEUE_CURRENT_OFFSET_MASK (0x00000FFF) +#define EP_QUEUE_HEAD_NEXT_POINTER_MASK 0xFFFFFFE0 +#define EP_QUEUE_FRINDEX_MASK (0x000007FF) +#define EP_MAX_LENGTH_TRANSFER (0x4000) + +/*! + * Endpoint Transfer Descriptor data struct + * Rem: all the variables of td are LittleEndian Mode + * must be 32-byte aligned + */ +struct ep_td_struct { + /*! + * Next TD pointer(31-5), T(0) set indicate invalid + */ + u32 next_td_ptr; + + /*! + * Total bytes (30-16), IOC (15),MultO(11-10), STS (7-0) + */ + u32 size_ioc_sts; + + /*! + * Buffer pointer Page 0 + */ + u32 buff_ptr0; + + /*! + * Buffer pointer Page 1 + */ + u32 buff_ptr1; + + /*! + * Buffer pointer Page 2 + */ + u32 buff_ptr2; + + /*! + * Buffer pointer Page 3 + */ + u32 buff_ptr3; + + /*! + * Buffer pointer Page 4 + */ + u32 buff_ptr4; + + /*! + * dma address of this td + * */ + dma_addr_t td_dma; + + /*! + * virtual address of next td + * */ + struct ep_td_struct *next_td_virt; + + /*! + * make it an even 16 words + * */ + u32 res[7]; +}; + +/*! + * Endpoint Transfer Descriptor bit Masks + */ +#define DTD_NEXT_TERMINATE (0x00000001) +#define DTD_IOC (0x00008000) +#define DTD_STATUS_ACTIVE (0x00000080) +#define DTD_STATUS_HALTED (0x00000040) +#define DTD_STATUS_DATA_BUFF_ERR (0x00000020) +#define DTD_STATUS_TRANSACTION_ERR (0x00000008) +#define DTD_RESERVED_FIELDS (0x80007300) +#define DTD_ADDR_MASK 0xFFFFFFE0 +#define DTD_PACKET_SIZE (0x7FFF0000) +#define DTD_LENGTH_BIT_POS (16) +#define DTD_ERROR_MASK (DTD_STATUS_HALTED | \ + DTD_STATUS_DATA_BUFF_ERR | \ + DTD_STATUS_TRANSACTION_ERR) +/* Alignment requirements; must be a power of two */ +#define DTD_ALIGNMENT 0x20 +#define QH_ALIGNMENT 2048 + +/* Controller dma boundary */ +#define UDC_DMA_BOUNDARY 0x1000 + +/* -----------------------------------------------------------------------*/ +/* ##### enum data +*/ +typedef enum { + e_ULPI, + e_UTMI_8BIT, + e_UTMI_16BIT, + e_SERIAL +} e_PhyInterface; + +/*-------------------------------------------------------------------------*/ + +struct fsl_req { + struct usb_request req; + struct list_head queue; + /* ep_queue() func will add + a request->queue into a udc_ep->queue 'd tail */ + struct fsl_ep *ep; + unsigned mapped; + + struct ep_td_struct *head, *tail; /* For dTD List + this is a BigEndian Virtual addr */ + unsigned int dtd_count; + dma_addr_t oridma; /* original dma */ + size_t buffer_offset; /* offset of user buffer */ + int last_one; /* mark if reach to last packet */ + struct ep_td_struct *cur; /* current tranfer dtd */ +}; + +#define REQ_UNCOMPLETE (1) + +struct fsl_ep { + struct usb_ep ep; + struct list_head queue; + struct fsl_udc *udc; + struct ep_queue_head *qh; + const struct usb_endpoint_descriptor *desc; + struct usb_gadget *gadget; + + char name[14]; + unsigned stopped:1; +}; + +#define EP_DIR_IN 1 +#define EP_DIR_OUT 0 + +struct fsl_udc { + struct usb_gadget gadget; + struct usb_gadget_driver *driver; + struct fsl_usb2_platform_data *pdata; + struct fsl_ep *eps; + unsigned int max_ep; + unsigned int irq; + + struct usb_ctrlrequest local_setup_buff; + spinlock_t lock; + u32 xcvr_type; + struct otg_transceiver *transceiver; + unsigned softconnect:1; + unsigned vbus_active:1; + unsigned stopped:1; + unsigned remote_wakeup:1; + unsigned suspended:1; + + struct ep_queue_head *ep_qh; /* Endpoints Queue-Head */ + struct fsl_req *status_req; /* ep0 status request */ + struct dma_pool *td_pool; /* dma pool for DTD */ + enum fsl_usb2_phy_modes phy_mode; + + size_t ep_qh_size; /* size after alignment adjustment*/ + dma_addr_t ep_qh_dma; /* dma address of QH */ + + u32 max_pipes; /* Device max pipes */ + u32 max_use_endpts; /* Max endpointes to be used */ + u32 bus_reset; /* Device is bus reseting */ + u32 resume_state; /* USB state to resume */ + u32 usb_state; /* USB current state */ + u32 usb_next_state; /* USB next state */ + u32 ep0_state; /* Endpoint zero state */ + u32 ep0_dir; /* Endpoint zero direction: can be + USB_DIR_IN or USB_DIR_OUT */ + u32 usb_sof_count; /* SOF count */ + u32 errors; /* USB ERRORs count */ + u8 device_address; /* Device USB address */ + + struct completion *done; /* to make sure release() is done */ + struct delayed_work charger_detect_work; + + struct work_struct usbtest_work; /* USB test mode workqueue handler */ + struct timer_list timer; /* Main charger timer fn */ + struct timer_list detect_timer; /* Detect the charger type */ + + int lobathi; /*LOBATH event */ + int lobatli; /* LOBATL event */ + +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_root; + struct dentry *debugfs_state; +#endif + + u32 iram_buffer[IRAM_PPH_NTD]; + void *iram_buffer_v[IRAM_PPH_NTD]; +}; + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +#define DBG(fmt, args...) printk(KERN_DEBUG "[%s] " fmt "\n", \ + __func__, ## args) +#else +#define DBG(fmt, args...) do {} while (0) +#endif + +#if 0 +static void dump_msg(const char *label, const u8 * buf, unsigned int length) +{ + unsigned int start, num, i; + char line[52], *p; + + if (length >= 512) + return; + pr_debug("udc: %s, length %u:\n", label, length); + start = 0; + while (length > 0) { + num = min(length, 16u); + p = line; + for (i = 0; i < num; ++i) { + if (i == 8) + *p++ = ' '; + sprintf(p, " %02x", buf[i]); + p += 3; + } + *p = 0; + printk(KERN_DEBUG "%6x: %s\n", start, line); + buf += num; + start += num; + length -= num; + } +} +#endif + +#ifdef VERBOSE +#define VDBG DBG +#else +#define VDBG(stuff...) do {} while (0) +#endif + +#define ERR(stuff...) printk(KERN_ERR "udc: " stuff) +#define WARN(stuff...) printk(KERN_WARNING "udc: " stuff) +#define INFO(stuff...) printk(KERN_INFO "udc: " stuff) + +/*-------------------------------------------------------------------------*/ + +/* ### Add board specific defines here + */ + +/* + * ### pipe direction macro from device view + */ +#define USB_RECV (0) /* OUT EP */ +#define USB_SEND (1) /* IN EP */ + +/* + * ### internal used help routines. + */ +#define ep_index(EP) ((EP)->desc->bEndpointAddress&0xF) +#define ep_maxpacket(EP) ((EP)->ep.maxpacket) + +#define ep_is_in(EP) ( (ep_index(EP) == 0) ? (EP->udc->ep0_dir == \ + USB_DIR_IN ):((EP)->desc->bEndpointAddress \ + & USB_DIR_IN)==USB_DIR_IN) + +#define get_ep_by_pipe(udc, pipe) ((pipe == 1)? &udc->eps[0]: \ + &udc->eps[pipe]) +#define get_pipe_by_windex(windex) ((windex & USB_ENDPOINT_NUMBER_MASK) \ + * 2 + ((windex & USB_DIR_IN) ? 1 : 0)) + +/* Bulk only class request */ +#define USB_BULK_RESET_REQUEST 0xff + +#ifdef CONFIG_ARCH_MXC +#include +#elif CONFIG_PPC32 +#include +#endif + +#endif /* __ARCOTG_UDC_H */ diff -urN linux-2.6.26/drivers/usb/gadget/epautoconf.c linux-2.6.26-lab126/drivers/usb/gadget/epautoconf.c --- linux-2.6.26/drivers/usb/gadget/epautoconf.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/gadget/epautoconf.c 2010-08-10 04:17:11.000000000 -0400 @@ -161,7 +161,11 @@ /* report address */ if (isdigit (ep->name [2])) { u8 num = simple_strtol (&ep->name [2], NULL, 10); - desc->bEndpointAddress |= num; + if (desc->bEndpointAddress & 0x7) { + if (num != (desc->bEndpointAddress & 0x7)) + return 0; + } else + desc->bEndpointAddress |= num; #ifdef MANY_ENDPOINTS } else if (desc->bEndpointAddress & USB_DIR_IN) { if (++in_epnum > 15) diff -urN linux-2.6.26/drivers/usb/gadget/ether.c linux-2.6.26-lab126/drivers/usb/gadget/ether.c --- linux-2.6.26/drivers/usb/gadget/ether.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/gadget/ether.c 2010-08-10 04:17:11.000000000 -0400 @@ -235,6 +235,10 @@ #define DEV_CONFIG_CDC #endif +#ifdef CONFIG_USB_GADGET_ARC +#define DEV_CONFIG_CDC +#endif + #ifdef CONFIG_USB_GADGET_S3C2410 #define DEV_CONFIG_CDC #endif @@ -464,7 +468,7 @@ .bConfigurationValue = DEV_CONFIG_VALUE, .iConfiguration = STRING_CDC, .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER, - .bMaxPower = 50, + .bMaxPower = CONFIG_USB_GADGET_VBUS_DRAW / 2, }; #ifdef CONFIG_USB_ETH_RNDIS @@ -478,7 +482,7 @@ .bConfigurationValue = DEV_RNDIS_CONFIG_VALUE, .iConfiguration = STRING_RNDIS, .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER, - .bMaxPower = 50, + .bMaxPower = CONFIG_USB_GADGET_VBUS_DRAW / 2, }; #endif @@ -1188,6 +1192,7 @@ eth_reset_config (dev); usb_gadget_vbus_draw(dev->gadget, gadget_is_otg(dev->gadget) ? 8 : 100); + gadget->configured = 1; } else { char *speed; unsigned power; @@ -1204,6 +1209,7 @@ } dev->config = number; + gadget->configured = 1; INFO (dev, "%s speed config #%d: %d mA, %s, using %s\n", speed, number, power, driver_desc, rndis_active(dev) @@ -1604,6 +1610,8 @@ eth_reset_config (dev); spin_unlock_irqrestore (&dev->lock, flags); + gadget->configured = 0; + /* FIXME RNDIS should enter RNDIS_UNINITIALIZED */ /* next we may get setup() calls to enumerate new connections; @@ -2227,6 +2235,8 @@ /* assuming we used keventd, it must quiesce too */ flush_scheduled_work (); set_gadget_data (gadget, NULL); + + gadget->configured = 0; } static u8 __init nibble (unsigned char c) @@ -2606,6 +2616,7 @@ DEBUG (dev, "suspend\n"); dev->suspended = 1; + gadget->configured = 0; } static void diff -urN linux-2.6.26/drivers/usb/gadget/file_storage.c linux-2.6.26-lab126/drivers/usb/gadget/file_storage.c --- linux-2.6.26/drivers/usb/gadget/file_storage.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/gadget/file_storage.c 2010-08-10 04:17:11.000000000 -0400 @@ -242,8 +242,11 @@ #include #include -#include "gadget_chips.h" +#include +#include "usbstring.c" +#include "config.c" +#include "epautoconf.c" /*-------------------------------------------------------------------------*/ @@ -262,9 +265,25 @@ * * DO NOT REUSE THESE IDs with any other driver!! Ever!! * Instead: allocate your own, using normal USB-IF procedures. */ +#ifdef CONFIG_MACH_LUIGI_LAB126 + +#define DRIVER_VENDOR_ID 0x1949 // Lab126 +#define DRIVER_PRODUCT_ID 0x0004 // Shasta +#define DRIVER_BCD_DEVICE 0x0100 // FW version 01.00 + +#define DRIVER_MFG_STR "Amazon" +#define DRIVER_VENDOR_ID_STR "Kindle" +#define DRIVER_PROD_ID_STR "Internal Storage" +static const char productname[] = "Amazon Kindle"; +extern char mx35_serial_number[]; + +#else + #define DRIVER_VENDOR_ID 0x0525 // NetChip #define DRIVER_PRODUCT_ID 0xa4a5 // Linux-USB File-backed Storage Gadget +#endif + /* * This driver assumes self-powered hardware and has no way for users to @@ -313,6 +332,11 @@ #define INFO(d, fmt, args...) \ dev_info(&(d)->gadget->dev , fmt , ## args) +#ifdef CONFIG_MACH_LUIGI_LAB126 +#define ICHRG_VALUE_HIGH 5 /* As defined by Atlas - maps to 480mA */ +#define ICHRG_VALUE_FULL 1 /* maps to 80mA */ +#define FSG_THREAD_NICE_LEVEL (-20) +#endif /*-------------------------------------------------------------------------*/ @@ -345,11 +369,19 @@ } mod_data = { // Default values .transport_parm = "BBB", .protocol_parm = "SCSI", +#ifdef CONFIG_MACH_LUIGI_LAB126 + .removable = 1, +#else .removable = 0, +#endif .can_stall = 1, .vendor = DRIVER_VENDOR_ID, .product = DRIVER_PRODUCT_ID, +#ifdef CONFIG_MACH_LUIGI_LAB126 + .release = DRIVER_BCD_DEVICE, +#else .release = 0xffff, // Use controller chip type +#endif .buflen = 16384, }; @@ -646,6 +678,7 @@ #define REGISTERED 0 #define IGNORE_BULK_OUT 1 #define SUSPENDED 2 +#define ONLINE 3 struct usb_ep *bulk_in; struct usb_ep *bulk_out; @@ -700,6 +733,8 @@ if (rem > 0) length += fsg->bulk_out_maxpacket - rem; bh->outreq->length = length; + if (bh->bulk_out_intended_length == 31) + bh->outreq->length = 31; } static struct fsg_dev *the_fsg; @@ -821,7 +856,11 @@ /* The next three values can be overridden by module parameters */ .idVendor = __constant_cpu_to_le16(DRIVER_VENDOR_ID), .idProduct = __constant_cpu_to_le16(DRIVER_PRODUCT_ID), +#ifdef CONFIG_MACH_LUIGI_LAB126 + .bcdDevice = __constant_cpu_to_le16(DRIVER_BCD_DEVICE), +#else .bcdDevice = __constant_cpu_to_le16(0xffff), +#endif .iManufacturer = STRING_MANUFACTURER, .iProduct = STRING_PRODUCT, @@ -839,7 +878,7 @@ .bConfigurationValue = CONFIG_VALUE, .iConfiguration = STRING_CONFIG, .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER, - .bMaxPower = 1, // self-powered + .bMaxPower = CONFIG_USB_GADGET_VBUS_DRAW / 2, }; static struct usb_otg_descriptor @@ -984,12 +1023,20 @@ /* The CBI specification limits the serial string to 12 uppercase hexadecimal * characters. */ static char manufacturer[64]; +#ifdef CONFIG_MACH_LUIGI_LAB126 +static char serial[17]; +#else static char serial[13]; +#endif /* Static strings, in UTF-8 (for simplicity we use only ASCII characters) */ static struct usb_string strings[] = { {STRING_MANUFACTURER, manufacturer}, +#ifdef CONFIG_MACH_LUIGI_LAB126 + {STRING_PRODUCT, productname}, +#else {STRING_PRODUCT, longname}, +#endif {STRING_SERIAL, serial}, {STRING_CONFIG, "Self-powered"}, {STRING_INTERFACE, "Mass Storage"}, @@ -1392,6 +1439,14 @@ * state (queued bufs, etc) and set the new config. */ raise_exception(fsg, FSG_STATE_CONFIG_CHANGE); value = DELAYED_STATUS; +#ifdef CONFIG_MACH_LUIGI_LAB126 + if (w_value) { + if (fsg->gadget->speed == USB_SPEED_HIGH) + usb_gadget_vbus_draw(fsg->gadget, ICHRG_VALUE_HIGH); + else + usb_gadget_vbus_draw(fsg->gadget, ICHRG_VALUE_FULL); + } +#endif } break; case USB_REQ_GET_CONFIGURATION: @@ -1856,7 +1911,7 @@ if (curlun->ro || !filp) return 0; - if (!filp->f_op->fsync) + if (!filp->f_op || !filp->f_op->fsync) return -EINVAL; inode = filp->f_path.dentry->d_inode; @@ -2009,8 +2064,13 @@ { u8 *buf = (u8 *) bh->buf; +#ifdef CONFIG_MACH_LUIGI_LAB126 + static char vendor_id[] = DRIVER_VENDOR_ID_STR; + static char product_id[] = DRIVER_PROD_ID_STR; +#else static char vendor_id[] = "Linux "; static char product_id[] = "File-Stor Gadget"; +#endif if (!fsg->curlun) { // Unsupported LUNs are okay fsg->bad_lun_okay = 1; @@ -2218,9 +2278,25 @@ close_backing_file(curlun); up_write(&fsg->filesem); down_read(&fsg->filesem); + + if (test_and_clear_bit(ONLINE, &fsg->atomic_bitflags) && + kobject_uevent(&fsg->gadget->dev.parent->kobj, KOBJ_OFFLINE)) { + printk(KERN_ERR __FILE__ ", line %d: kobject_uevent failed\n", __LINE__); + } + else { + fsg->gadget->configured = 1; + } } } else { + if (!test_and_set_bit(ONLINE, &fsg->atomic_bitflags) && + kobject_uevent(&fsg->gadget->dev.parent->kobj, KOBJ_ONLINE)) { + printk(KERN_ERR __FILE__ ", line %d: kobject_uevent failed\n", __LINE__); + } + else { + fsg->gadget->configured = 1; + } + /* Our emulation doesn't support mounting; the medium is * available for use as soon as it is loaded. */ if (!backing_file_is_open(curlun)) { @@ -2228,6 +2304,7 @@ return -EINVAL; } } + set_drivemode_online(test_bit(ONLINE, &fsg->atomic_bitflags)); #endif return 0; } @@ -3236,6 +3313,15 @@ default: speed = "?"; break; } INFO(fsg, "%s speed config #%d\n", speed, fsg->config); + + if (!test_and_set_bit(ONLINE, &fsg->atomic_bitflags) && + kobject_uevent(&fsg->gadget->dev.parent->kobj, KOBJ_ONLINE)) { + printk(KERN_ERR __FILE__ ", line %d: kobject_uevent failed\n", __LINE__); + } + else { + fsg->gadget->configured = 1; + } + set_drivemode_online(test_bit(ONLINE, &fsg->atomic_bitflags)); } } return rc; @@ -3605,6 +3691,12 @@ return rc; } +static ssize_t +show_online(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct fsg_dev *fsg = dev_get_drvdata(dev); + return sprintf(buf, "%d\n", test_bit(ONLINE, &fsg->atomic_bitflags)); +} static ssize_t store_ro(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) @@ -3669,6 +3761,7 @@ /* The write permissions and store_xxx pointers are set in fsg_bind() */ static DEVICE_ATTR(ro, 0444, show_ro, NULL); static DEVICE_ATTR(file, 0444, show_file, NULL); +static DEVICE_ATTR(online, 0444, show_online, NULL); /*-------------------------------------------------------------------------*/ @@ -3709,6 +3802,14 @@ } } + if (test_and_clear_bit(ONLINE, &fsg->atomic_bitflags) && + kobject_uevent_atomic(&fsg->gadget->dev.parent->kobj, KOBJ_OFFLINE)) { + printk(KERN_ERR __FILE__ ", line %d: kobject_uevent failed\n", __LINE__); + } + else { + fsg->gadget->configured = 0; + } + /* If the thread isn't already dead, tell it to exit now */ if (fsg->state != FSG_STATE_TERMINATED) { raise_exception(fsg, FSG_STATE_EXIT); @@ -3877,7 +3978,9 @@ if ((rc = device_create_file(&curlun->dev, &dev_attr_ro)) != 0 || (rc = device_create_file(&curlun->dev, - &dev_attr_file)) != 0) { + &dev_attr_file)) != 0 || + (rc = device_create_file(&curlun->dev, + &dev_attr_online)) != 0) { device_unregister(&curlun->dev); goto out; } @@ -3975,6 +4078,21 @@ /* This should reflect the actual gadget power source */ usb_gadget_set_selfpowered(gadget); +#ifdef CONFIG_MACH_LUIGI_LAB126 + snprintf(manufacturer, sizeof manufacturer, DRIVER_MFG_STR); + + { + char *src = mx35_serial_number; + char *dst = serial; + + if (*src == 0) + src = "Empty"; + + strncpy(dst, src, sizeof(serial)); + dst[sizeof(serial)-1] = 0; + } + +#else snprintf(manufacturer, sizeof manufacturer, "%s %s with %s", init_utsname()->sysname, init_utsname()->release, gadget->name); @@ -3988,6 +4106,7 @@ break; sprintf(&serial[i], "%02X", c); } +#endif fsg->thread_task = kthread_create(fsg_main_thread, fsg, "file-storage-gadget"); @@ -3996,6 +4115,10 @@ goto out; } +#ifdef CONFIG_MACH_LUIGI_LAB126 + set_user_nice(fsg->thread_task, FSG_THREAD_NICE_LEVEL); +#endif + INFO(fsg, DRIVER_DESC ", version: " DRIVER_VERSION "\n"); INFO(fsg, "Number of LUNs=%d\n", fsg->nluns); @@ -4041,6 +4164,7 @@ fsg->state = FSG_STATE_TERMINATED; // The thread is dead fsg_unbind(gadget); close_all_backing_files(fsg); + complete(&fsg->thread_notifier); return rc; } @@ -4053,7 +4177,17 @@ DBG(fsg, "suspend\n"); set_bit(SUSPENDED, &fsg->atomic_bitflags); -} + + if (fsg->curlun != NULL) { + fsg->curlun->prevent_medium_removal = 0; + if (test_and_clear_bit(ONLINE, &fsg->atomic_bitflags) && + kobject_uevent_atomic(&fsg->gadget->dev.parent->kobj, KOBJ_OFFLINE)) { + printk(KERN_ERR __FILE__ ", line %d: kobject_uevent failed\n", __LINE__); + } + + set_drivemode_online(test_bit(ONLINE, &fsg->atomic_bitflags)); + } +}; static void fsg_resume(struct usb_gadget *gadget) { @@ -4112,6 +4246,9 @@ int rc; struct fsg_dev *fsg; +#ifdef CONFIG_MACH_LUIGI_LAB126 + set_drivemode_online(0); +#endif if ((rc = fsg_alloc()) != 0) return rc; fsg = the_fsg; diff -urN linux-2.6.26/drivers/usb/gadget/gadget_chips.h linux-2.6.26-lab126/drivers/usb/gadget/gadget_chips.h --- linux-2.6.26/drivers/usb/gadget/gadget_chips.h 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/gadget/gadget_chips.h 2010-08-10 04:17:11.000000000 -0400 @@ -88,6 +88,12 @@ #define gadget_is_pxa27x(g) 0 #endif +#ifdef CONFIG_USB_GADGET_ARC +#define gadget_is_arcotg(g) !strcmp("fsl-usb2-udc", (g)->name) +#else +#define gadget_is_arcotg(g) 0 +#endif + #ifdef CONFIG_USB_GADGET_ATMEL_USBA #define gadget_is_atmel_usba(g) !strcmp("atmel_usba_udc", (g)->name) #else @@ -212,5 +218,7 @@ return 0x20; else if (gadget_is_m66592(gadget)) return 0x21; + else if (gadget_is_arcotg(gadget)) + return 0x22; return -ENOENT; } diff -urN linux-2.6.26/drivers/usb/gadget/inode.c linux-2.6.26-lab126/drivers/usb/gadget/inode.c --- linux-2.6.26/drivers/usb/gadget/inode.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/gadget/inode.c 2010-08-10 04:17:11.000000000 -0400 @@ -39,6 +39,8 @@ #include #include +#include +#include /* * The gadgetfs API maps each endpoint to a file descriptor so that you @@ -80,6 +82,9 @@ MODULE_AUTHOR ("David Brownell"); MODULE_LICENSE ("GPL"); +/* Cancel IO, To store the bulkin and bulkout ep data. */ +static struct ep_data *gp_ep_bulkin_data; +static struct ep_data *gp_ep_bulkout_data; /*----------------------------------------------------------------------*/ @@ -266,6 +271,10 @@ #define INFO(dev,fmt,args...) \ xprintk(dev , KERN_INFO , fmt , ## args) +/* Cancel IO */ +static int mtp_ctrl_cmd; +static int gbCancelFlag; +static unsigned long mtptimestamp; /*----------------------------------------------------------------------*/ @@ -276,6 +285,17 @@ * precise FIFO status when recovering from cancellation. */ +/* Cancel IO */ +static void cancel_io_process(void *data) +{ + if (gp_ep_bulkout_data->req->status == -EINPROGRESS) + usb_ep_dequeue(gp_ep_bulkout_data->ep, gp_ep_bulkout_data->req); + + if (gp_ep_bulkin_data->req->status == -EINPROGRESS) + usb_ep_dequeue(gp_ep_bulkin_data->ep, gp_ep_bulkin_data->req); +} +static DECLARE_DELAYED_WORK(cancel_work, cancel_io_process); + static void epio_complete (struct usb_ep *ep, struct usb_request *req) { struct ep_data *epdata = ep->driver_data; @@ -872,10 +892,13 @@ { struct ep_data *data = inode->i_private; int value = -EBUSY; + char *epin = "ep1in"; + char *epout = "ep1out"; if (down_interruptible (&data->lock) != 0) return -EINTR; spin_lock_irq (&data->dev->lock); + if (data->dev->state == STATE_DEV_UNBOUND) value = -ENOENT; else if (data->state == STATE_EP_DISABLED) { @@ -884,9 +907,16 @@ get_ep (data); fd->private_data = data; VDEBUG (data->dev, "%s ready\n", data->name); + /* Cancel IO */ + if (0 == strcmp(data->name, epin)) + gp_ep_bulkin_data = fd->private_data; + + if (0 == strcmp(data->name, epout)) + gp_ep_bulkout_data = fd->private_data; } else DBG (data->dev, "%s state %d\n", data->name, data->state); + spin_unlock_irq (&data->dev->lock); up (&data->lock); return value; @@ -998,7 +1028,7 @@ retval = -EL2HLT; dev->state = STATE_DEV_CONNECTED; - } else if (len == 0) { /* ack SET_CONFIGURATION etc */ + } else if (len == 0) { /* ack SET_CONFIGURATION etc */ struct usb_ep *ep = dev->gadget->ep0; struct usb_request *req = dev->req; @@ -1019,7 +1049,7 @@ usb_gadget_vbus_draw(dev->gadget, 2 * power); } - } else { /* collect OUT data */ + } else { /* collect OUT data */ if ((fd->f_flags & O_NONBLOCK) != 0 && !dev->setup_out_ready) { retval = -EAGAIN; @@ -1044,11 +1074,15 @@ retval = -EIO; else { len = min (len, (size_t)dev->req->actual); -// FIXME don't call this with the spinlock held ... +/* FIXME don't call this with the spinlock held ... */ if (copy_to_user (buf, dev->req->buf, len)) retval = -EFAULT; + else + /* Bug of Cancel IO 6 bytes read. */ + retval = len; clean_req (dev->gadget->ep0, dev->req); /* NOTE userspace can't yet choose to stall */ + dev->state = STATE_DEV_CONNECTED; /* Cancel IO */ } } goto done; @@ -1062,6 +1096,12 @@ len -= len % sizeof (struct usb_gadgetfs_event); dev->usermode_setup = 1; + /* Cancel IO, signal abort blocked IO. */ + if (mtp_ctrl_cmd == 1) { + mtp_ctrl_cmd = 0; + schedule_delayed_work(&cancel_work, HZ / 100); + } + scan: /* return queued events right away */ if (dev->ev_next != 0) { @@ -1386,6 +1426,16 @@ struct usb_gadgetfs_event *event; u16 w_value = le16_to_cpu(ctrl->wValue); u16 w_length = le16_to_cpu(ctrl->wLength); + struct timeval tv; + + /* Cancel IO */ + if (0x67 == ctrl->bRequest && 1 == gbCancelFlag + && dev->state == STATE_DEV_SETUP) + dev->state = STATE_DEV_CONNECTED; + + if (0x67 == ctrl->bRequest && 2 == mtp_ctrl_cmd + && dev->state == STATE_DEV_SETUP) + dev->state = STATE_DEV_CONNECTED; spin_lock (&dev->lock); dev->setup_abort = 0; @@ -1413,6 +1463,11 @@ */ } else if (dev->state == STATE_DEV_SETUP) dev->setup_abort = 1; + /*Cancel IO */ + if (mtp_ctrl_cmd == 1 && gbCancelFlag == 1 && dev->setup_abort == 1) { + INFO(dev, "0x64->setup\n"); + dev->setup_abort = 0; + } req->buf = dev->rbuf; req->dma = DMA_ADDR_INVALID; @@ -1438,7 +1493,7 @@ make_qualifier (dev); break; case USB_DT_OTHER_SPEED_CONFIG: - // FALLTHROUGH + /* FALLTHROUGH */ #endif case USB_DT_CONFIG: value = config_buf (dev, @@ -1545,11 +1600,63 @@ /* we can't currently stall these */ dev->setup_can_stall = 0; } + /* Cancel IO */ + if (0x67 == ctrl->bRequest && 1 == gbCancelFlag) { + gbCancelFlag = 0; + + setup_req(gadget->ep0, dev->req, 4); + *(unsigned long *)dev->req->buf = 0x20190004; + usb_ep_queue(gadget->ep0, dev->req, GFP_ATOMIC); + + spin_unlock(&dev->lock); + return 0; + } + if (ctrl->bRequest == 0x67 && mtp_ctrl_cmd == 2) { + /* get status */ + mtp_ctrl_cmd = 0; + } /* state changes when reader collects event */ event = next_event (dev, GADGETFS_SETUP); event->u.setup = *ctrl; + /* Cancel IO */ + if (0x64 == ctrl->bRequest) { + mtp_ctrl_cmd = 1; + gbCancelFlag = 1; + + /* get the timestamp */ + do_gettimeofday(&tv); + mtptimestamp = tv.tv_usec; + event->u.setup.wValue = + (unsigned short)tv.tv_usec; + } + if (0x66 == ctrl->bRequest) { + /* get the timestamp */ + do_gettimeofday(&tv); + mtptimestamp = tv.tv_usec; + event->u.setup.wValue = + (unsigned short)tv.tv_usec; + } + ep0_readable (dev); + /* Reset request. */ + if (ctrl->bRequest == 0x66) { /* reset ,send ZLP */ + mtp_ctrl_cmd = 2; + + if (gp_ep_bulkout_data->req->status == + -EINPROGRESS) { + usb_ep_dequeue(gp_ep_bulkout_data->ep, + gp_ep_bulkout_data->req); + } + if (gp_ep_bulkin_data->req->status == + -EINPROGRESS) { + usb_ep_dequeue(gp_ep_bulkin_data->ep, + gp_ep_bulkin_data->req); + } + } + if (ctrl->bRequest == 0x65) + pr_debug("i:0x65,not supported\n"); + spin_unlock (&dev->lock); return 0; } diff -urN linux-2.6.26/drivers/usb/gadget/serial.c linux-2.6.26-lab126/drivers/usb/gadget/serial.c --- linux-2.6.26/drivers/usb/gadget/serial.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/gadget/serial.c 2010-08-10 04:17:11.000000000 -0400 @@ -1742,6 +1742,8 @@ &gs_fullspeed_notify_desc) : NULL; + gadget->configured = 1; + ret = usb_ep_enable(dev->dev_in_ep, in); if (ret == 0) { dev->dev_in_ep_desc = in; diff -urN linux-2.6.26/drivers/usb/host/Kconfig linux-2.6.26-lab126/drivers/usb/host/Kconfig --- linux-2.6.26/drivers/usb/host/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/host/Kconfig 2010-08-10 04:17:12.000000000 -0400 @@ -42,9 +42,116 @@ To compile this driver as a module, choose M here: the module will be called ehci-hcd. +config USB_EHCI_ARC + bool "Support for Freescale controller" + depends on USB_EHCI_HCD && ARCH_MXC + ---help--- + Some Freescale processors have an integrated High Speed + USBOTG controller, which supports EHCI host mode. + + Say "y" here to add support for this controller + to the EHCI HCD driver. + +config USB_EHCI_ARC_H1 + bool "Support for Host1 port on Freescale controller" + depends on USB_EHCI_ARC && (ARCH_MX27 || ARCH_MX3 || ARCH_MX51) + ---help--- + Enable support for the USB Host1 port. + +config USB_EHCI_ARC_H2 + bool "Support for Host2 port on Freescale controller" + depends on USB_EHCI_ARC && \ + (ARCH_MX25 || ARCH_MX27 || ARCH_MX3 || ARCH_MX35 || ARCH_MX51) + ---help--- + Enable support for the USB Host2 port. + +config USB_EHCI_ARC_H2_WAKE_UP + bool "Support wake up from Freescale Host2 port" + depends on PM && USB_EHCI_ARC_H2 + default n + ---help--- + Enable support system wake up from Host2 port usb device + connection and disconnection. + +config USB_EHCI_ARC_OTG + bool "Support for DR host port on Freescale controller" + depends on USB_EHCI_ARC + default y + ---help--- + Enable support for the USB OTG port in HS/FS Host mode. + +config USB_EHCI_ARC_OTG_WAKE_UP + bool "Support wake up from Freescale OTG port" + depends on PM && USB_EHCI_ARC_OTG + default n + ---help--- + Enable support system wake up from Host1 port usb device + connection and disconnection. + +config USB_STATIC_IRAM + bool "Use IRAM for USB" + depends on USB_EHCI_ARC + ---help--- + Enable this option to use IRAM instead of DRAM for USB + structures and buffers. This option will reduce bus + contention on systems with large (VGA+) framebuffer + devices and heavy USB activity. There are performance + penalties and usage restrictions when using this option. + + If in doubt, say N. + +choice + prompt "Select transceiver for DR port" + depends on USB_EHCI_ARC_OTG + default USB_EHCI_FSL_1504 if ARCH_MX3 + default USB_EHCI_FSL_1301 if ARCH_MX27 + default USB_EHCI_FSL_UTMI if (ARCH_MX25 || ARCH_MX35 || ARCH_MX37 || ARCH_MX51) + ---help--- + Choose the transceiver to use with the Freescale DR port. + +config USB_EHCI_FSL_MC13783 + bool "Freescale MC13783" + depends on !MACH_MX25_3DS + ---help--- + Enable support for the Full Speed Freescale MC13783 transceiver. + + The mx27ads, mx31ads and mx32ads boards require modifications + to support this transceiver. + +config USB_EHCI_FSL_1301 + bool "Philips ISP1301" + depends on !MACH_MX25_3DS + ---help--- + Enable support for the Full Speed Philips ISP1301 transceiver. + + This is the factory default for the mx27ads board. + The mx31ads and mx32ads boards require modifications + to support this transceiver. + +config USB_EHCI_FSL_1504 + bool "Philips ISP1504" + depends on MACH_MX27ADS || MACH_MX31ADS || MACH_MX32ADS ||MACH_MX31_3DS + ---help--- + Enable support for the High Speed Philips ISP1504 transceiver. + + This is the factory default for the mx31ads and mx32ads boards. + The mx27ads board requires modifications to support this transceiver. + +config USB_EHCI_FSL_UTMI + bool "Internal UTMI" + depends on (ARCH_MX25 || ARCH_MX35 || ARCH_MX37 || ARCH_MX51) + ---help--- + Enable support for the on-chip High Speed UTMI transceiver. + + This is the factory default for the mx35ads board. + +endchoice + + config USB_EHCI_ROOT_HUB_TT bool "Root Hub Transaction Translators" depends on USB_EHCI_HCD + default y if USB_EHCI_ARC ---help--- Some EHCI chips have vendor-specific extensions to integrate transaction translators, so that no OHCI or UHCI companion diff -urN linux-2.6.26/drivers/usb/host/ehci-arc.c linux-2.6.26-lab126/drivers/usb/host/ehci-arc.c --- linux-2.6.26/drivers/usb/host/ehci-arc.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/usb/host/ehci-arc.c 2010-09-02 21:21:01.000000000 -0400 @@ -0,0 +1,772 @@ +/* + * (C) Copyright David Brownell 2000-2002 + * Copyright (c) 2005 MontaVista Software + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Ported to 834x by Randy Vinson using code provided + * by Hunter Wu. + */ + +#include +#include +#include +#include +#include + +#include "ehci-fsl.h" + +extern struct resource *otg_get_resources(void); + +#undef EHCI_PROC_PTC +/* + * write a PORTSC:PTC value to /proc/driver/ehci-ptc + * to put the controller into test mode. + */ +#include +#include +#define EFPSL 3 /* ehci fsl proc string length */ + +#define EHCI_IDLE_SUSPEND_THRESHOLD 60000 /* Restart the idle thread 60 secs after resume */ +#define EHCI_ARC_TOGGLE_LPM 40000 /* Toggle the wakeup after 40 seconds */ +extern void ehci_hcd_recalc_work(void); +int wakeup_value = 0; + +static ssize_t +deep_idle_enable_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", deep_idle_enable_value); +} + +static ssize_t +deep_idle_enable_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + if (strstr(buf, "1") != NULL && wakeup_value == 1) { + deep_idle_enable_value = 1; + + /* The modem supports alternative USB wakeup */ + wan_set_usb_wake_callback(ehci_hcd_host_wake); + + /* Pull modem out of idle so it can go into deep idle */ + ehci_hcd_recalc_work(); + ehci_hcd_restart_idle(); + } + else { + /* Pull modem out of idle now */ + ehci_hcd_recalc_work(); + deep_idle_enable_value = 0; + } + + return size; +} +static DEVICE_ATTR(deep_idle_enable, 0644, deep_idle_enable_show, deep_idle_enable_store); + + +static ssize_t +wakeup_enable_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", wakeup_value); +} + +static ssize_t +wakeup_enable_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + if (strstr(buf, "1") != NULL) { + wakeup_value = 1; + /* Restart the workqueue */ + ehci_hcd_restart_idle(); + } + else { + ehci_hcd_recalc_work(); + deep_idle_enable_value = 0; + wakeup_value = 0; + } + + return size; +} +static DEVICE_ATTR(wakeup_enable, 0644, wakeup_enable_show, wakeup_enable_store); + +static ssize_t suspend_counter_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", suspend_count); +} +static DEVICE_ATTR(suspend_counter, 0644, suspend_counter_show, NULL); + +#ifdef EHCI_PROC_PTC + +static int ehci_fsl_proc_read(char *page, char **start, off_t off, int count, + int *eof, void *data) +{ + return 0; +} + +static int ehci_fsl_proc_write(struct file *file, const char __user *buffer, + unsigned long count, void *data) +{ + int ptc; + u32 portsc; + struct ehci_hcd *ehci = (struct ehci_hcd *) data; + char str[EFPSL] = {0}; + + if (count > EFPSL-1) + return -EINVAL; + + if (copy_from_user(str, buffer, count)) + return -EFAULT; + + str[count] = '\0'; + + ptc = simple_strtoul(str, NULL, 0); + + portsc = ehci_readl(ehci, &ehci->regs->port_status[0]); + portsc &= ~(0xf << 16); + portsc |= (ptc << 16); + printk(KERN_INFO "PTC %x portsc %08x\n", ptc, portsc); + + ehci_writel(ehci, portsc, &ehci->regs->port_status[0]); + + return count; +} + +static int ehci_testmode_init(struct ehci_hcd *ehci) +{ + struct proc_dir_entry *entry; + + entry = create_proc_read_entry("driver/ehci-ptc", 0644, NULL, + ehci_fsl_proc_read, ehci); + if (!entry) + return -ENODEV; + + entry->write_proc = ehci_fsl_proc_write; + return 0; +} +#else +static int ehci_testmode_init(struct ehci_hcd *ehci) +{ + return 0; +} +#endif /* /proc PORTSC:PTC support */ + + +/* PCI-based HCs are common, but plenty of non-PCI HCs are used too */ + +/* configure so an HC device and id are always provided */ +/* always called with process context; sleeping is OK */ + +extern int schedule_ehci_mask; + +/** + * usb_hcd_fsl_probe - initialize FSL-based HCDs + * @drvier: Driver to be used for this HCD + * @pdev: USB Host Controller being probed + * Context: !in_interrupt() + * + * Allocates basic resources for this USB host controller. + * + */ +static int usb_hcd_fsl_probe(const struct hc_driver *driver, + struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + struct usb_hcd *hcd; + struct resource *res; + int irq; + int retval; + unsigned int __maybe_unused temp; + struct device *ehci_arc_dev; + + pr_debug("initializing FSL-SOC USB Controller\n"); + + /* Need platform data for setup */ + if (!pdata) { + dev_err(&pdev->dev, + "No platform data for %s.\n", pdev->dev.bus_id); + return -ENODEV; + } + + /* + * This is a host mode driver, verify that we're supposed to be + * in host mode. + */ + if (!((pdata->operating_mode == FSL_USB2_DR_HOST) || + (pdata->operating_mode == FSL_USB2_MPH_HOST) || + (pdata->operating_mode == FSL_USB2_DR_OTG))) { + dev_err(&pdev->dev, + "Non Host Mode configured for %s. " + "Wrong driver linked.\n", pdev->dev.bus_id); + return -ENODEV; + } + + hcd = usb_create_hcd(driver, &pdev->dev, pdev->dev.bus_id); + if (!hcd) { + retval = -ENOMEM; + goto err1; + } + +#if defined(CONFIG_USB_OTG) + if (pdata->operating_mode == FSL_USB2_DR_OTG) { + res = otg_get_resources(); + if (!res) { + dev_err(&pdev->dev, + "Found HC with no IRQ. Check %s setup!\n", + pdev->dev.bus_id); + return -ENODEV; + } + irq = res[1].start; + hcd->rsrc_start = res[0].start; + hcd->rsrc_len = res[0].end - res[0].start + 1; + } else +#endif + { + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_err(&pdev->dev, + "Found HC with no IRQ. Check %s setup!\n", + pdev->dev.bus_id); + return -ENODEV; + } + irq = res->start; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, + driver->description)) { + dev_dbg(&pdev->dev, "controller already in use\n"); + retval = -EBUSY; + goto err2; + } + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + + if (hcd->regs == NULL) { + dev_dbg(&pdev->dev, "error mapping memory\n"); + retval = -EFAULT; + goto err3; + } + pdata->regs = hcd->regs; + + /* + * do platform specific init: check the clock, grab/config pins, etc. + */ + if (pdata->platform_init && pdata->platform_init(pdev)) { + retval = -ENODEV; + goto err3; + } + + fsl_platform_set_host_mode(hcd); + hcd->power_budget = pdata->power_budget; + + ehci_arc_dev = &pdev->dev; + if (device_create_file(ehci_arc_dev, &dev_attr_wakeup_enable) < 0) + dev_err(&pdev->dev, "ehci: could not create wakeup_value sysfs entry\n"); + + if (device_create_file(ehci_arc_dev, &dev_attr_suspend_counter) < 0) + dev_err(&pdev->dev, "ehci: could not create suspend_counter sysfs entry\n"); + + if (device_create_file(ehci_arc_dev, &dev_attr_deep_idle_enable) < 0) + dev_err(&pdev->dev, "ehci: could not create deep_idle_enable_value sysfs entry\n"); + + retval = usb_add_hcd(hcd, irq, IRQF_DISABLED); + if (retval != 0) + goto err4; + + fsl_platform_set_vbus_power(pdata, 1); + +#ifdef CONFIG_USB_OTG + if (pdata->operating_mode == FSL_USB2_DR_OTG) { + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + + dbg("pdev=0x%p hcd=0x%p ehci=0x%p\n", pdev, hcd, ehci); + + ehci->transceiver = otg_get_transceiver(); + dbg("ehci->transceiver=0x%p\n", ehci->transceiver); + + if (ehci->transceiver) { + retval = otg_set_host(ehci->transceiver, + &ehci_to_hcd(ehci)->self); + if (retval) { + if (ehci->transceiver) + put_device(ehci->transceiver->dev); + goto err4; + } + } else { + printk(KERN_ERR "can't find transceiver\n"); + retval = -ENODEV; + goto err4; + } + } +#endif + + fsl_platform_set_ahb_burst(hcd); + ehci_testmode_init(hcd_to_ehci(hcd)); + + schedule_ehci_mask = 0; + + return retval; + +err4: + iounmap(hcd->regs); +err3: + if (pdata->operating_mode != FSL_USB2_DR_OTG) + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err2: + usb_put_hcd(hcd); +err1: + dev_err(&pdev->dev, "init %s fail, %d\n", pdev->dev.bus_id, retval); + if (pdata->platform_uninit) + pdata->platform_uninit(pdata); + return retval; +} + +/* may be called without controller electrically present */ +/* may be called with controller, bus, and devices active */ + +/** + * usb_hcd_fsl_remove - shutdown processing for FSL-based HCDs + * @dev: USB Host Controller being removed + * Context: !in_interrupt() + * + * Reverses the effect of usb_hcd_fsl_probe(). + * + */ +static void usb_hcd_fsl_remove(struct usb_hcd *hcd, + struct platform_device *pdev) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + static struct device *ehci_arc_dev; + + /* DDD shouldn't we turn off the power here? */ + fsl_platform_set_vbus_power(pdata, 0); + + if (ehci->transceiver) { + (void)otg_set_host(ehci->transceiver, 0); + put_device(ehci->transceiver->dev); + } else { + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + } + + usb_remove_hcd(hcd); + usb_put_hcd(hcd); + + ehci_arc_dev = &pdev->dev; + device_remove_file(ehci_arc_dev, &dev_attr_wakeup_enable); + device_remove_file(ehci_arc_dev, &dev_attr_suspend_counter); + device_remove_file(ehci_arc_dev, &dev_attr_deep_idle_enable); + + /* + * do platform specific un-initialization: + * release iomux pins, etc. + */ + if (pdata->platform_uninit) + pdata->platform_uninit(pdata); + + iounmap(hcd->regs); + + schedule_ehci_mask = 0; +} + +static void fsl_setup_phy(struct ehci_hcd *ehci, + enum fsl_usb2_phy_modes phy_mode, int port_offset) +{ + u32 portsc; + + portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]); + portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW); + + switch (phy_mode) { + case FSL_USB2_PHY_ULPI: + portsc |= PORT_PTS_ULPI; + break; + case FSL_USB2_PHY_SERIAL: + portsc |= PORT_PTS_SERIAL; + break; + case FSL_USB2_PHY_UTMI_WIDE: + portsc |= PORT_PTS_PTW; + /* fall through */ + case FSL_USB2_PHY_UTMI: + portsc |= PORT_PTS_UTMI; + break; + case FSL_USB2_PHY_NONE: + break; + } + ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); +} + +/* called after powerup, by probe or system-pm "wakeup" */ +static int ehci_fsl_reinit(struct ehci_hcd *ehci) +{ + fsl_platform_usb_setup(ehci); + ehci_port_power(ehci, 0); + return 0; +} + +/* called during probe() after chip reset completes */ +static int ehci_fsl_setup(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + int retval; + struct fsl_usb2_platform_data *pdata; + pdata = hcd->self.controller->platform_data; + + ehci->big_endian_desc = pdata->big_endian_desc; + ehci->big_endian_mmio = pdata->big_endian_mmio; + + /* EHCI registers start at offset 0x100 */ + ehci->caps = hcd->regs + 0x100; + ehci->regs = hcd->regs + 0x100 + + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); + dbg_hcs_params(ehci, "reset"); + dbg_hcc_params(ehci, "reset"); + + /* cache this readonly data; minimize chip reads */ + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + + retval = ehci_halt(ehci); + + /* data structure init */ + retval = ehci_init(hcd); + if (retval) + return retval; + + hcd->has_tt = 1; + + ehci->sbrn = 0x20; + + ehci_reset(ehci); + + retval = ehci_fsl_reinit(ehci); + return retval; +} + +/* USB EHCI bus suspend */ +static int ehci_arc_bus_suspend(struct usb_hcd *hcd) +{ + /* + * Check if bus already suspended. If yes, then no need to redo suspend + */ + if (!wakeup_value) { + /* Call the hub suspend now */ + ehci_bus_suspend(hcd); + } + return 0; +} + +/* USB EHCI bus resume */ +static int ehci_arc_bus_resume(struct usb_hcd *hcd) +{ + /* Call the hub resume now */ + ehci_bus_resume(hcd); + return 0; + +} + +static const struct hc_driver ehci_fsl_hc_driver = { + .description = hcd_name, + .product_desc = "Freescale On-Chip EHCI Host Controller", + .hcd_priv_size = sizeof(struct ehci_hcd), + + /* + * generic hardware linkage + */ + .irq = ehci_irq, + .flags = FSL_PLATFORM_HC_FLAGS, + + /* + * basic lifecycle operations + */ + .reset = ehci_fsl_setup, + .start = ehci_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + + /* + * managing i/o requests and associated device resources + */ + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + + /* + * scheduling support + */ + .get_frame_number = ehci_get_frame, + + /* + * root hub support + */ + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, + .bus_suspend = ehci_arc_bus_suspend, + .bus_resume = ehci_arc_bus_resume, + .start_port_reset = ehci_start_port_reset, + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, +}; + +static int ehci_fsl_drv_probe(struct platform_device *pdev) +{ + if (usb_disabled()) + return -ENODEV; + + return usb_hcd_fsl_probe(&ehci_fsl_hc_driver, pdev); +} + +static void ehci_lpm_toggle(struct work_struct *unused); +static DECLARE_DELAYED_WORK(toggle_idle_lp, ehci_lpm_toggle); + +static int ehci_fsl_drv_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + + /* Cancel delayed work before exiting */ + cancel_rearming_delayed_work(&ehci->dwork); + cancel_rearming_delayed_work(&toggle_idle_lp); + + /* Clear low power mode */ + wakeup_value = 0; + + usb_hcd_fsl_remove(hcd, pdev); + return 0; +} + + +#ifdef CONFIG_PM +/* suspend/resume, section 4.3 */ + +/* These routines rely on the bus (pci, platform, etc) + * to handle powerdown and wakeup, and currently also on + * transceivers that don't need any software attention to set up + * the right sort of wakeup. + * + * They're also used for turning on/off the port when doing OTG. + */ +#if defined(CONFIG_USB_EHCI_ARC_H2_WAKE_UP) || \ + defined(CONFIG_USB_EHCI_ARC_OTG_WAKE_UP) +extern void usb_wakeup_set(struct device *wkup_dev, int para); +#endif + +extern int ehci_suspending; + +static int ehci_fsl_drv_suspend(struct platform_device *pdev, + pm_message_t message) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + u32 tmp; + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + +#ifdef DEBUG + u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE); + mode &= USBMODE_CM_MASK; + tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */ + + printk(KERN_DEBUG "%s('%s'): suspend=%d already_suspended=%d " + "mode=%d usbcmd %08x\n", __func__, pdata->name, + pdata->suspended, pdata->already_suspended, mode, tmp); +#endif + + /* + * If the controller is already suspended, then this must be a + * PM suspend. Remember this fact, so that we will leave the + * controller suspended at PM resume time. + */ + if (pdata->suspended) { + pr_debug("%s: already suspended, leaving early\n", __func__); + pdata->already_suspended = 1; + return 0; + } + + pr_debug("%s: suspending...\n", __func__); + + msleep(20); + + hcd->state = HC_STATE_SUSPENDED; + pdev->dev.power.power_state = PMSG_SUSPEND; + + /* EHCI is suspending */ + ehci_suspending = 1; + + /* Wakeup EHCI if it is in LPM again */ + ehci_hcd_recalc_work(); + + /* Clear the wakeup_value to stop idle */ + wakeup_value = 0; + + /* Cancel the low power idle workqueue */ + cancel_rearming_delayed_work(&ehci->dwork); + + /* ignore non-host interrupts */ + clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + + /* stop the controller */ + tmp = ehci_readl(ehci, &ehci->regs->command); + tmp &= ~CMD_RUN; + ehci_writel(ehci, tmp, &ehci->regs->command); + + /* save EHCI registers */ + pdata->pm_command = ehci_readl(ehci, &ehci->regs->command); + pdata->pm_command &= ~CMD_RUN; + pdata->pm_status = ehci_readl(ehci, &ehci->regs->status); + pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable); + pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index); + pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment); + pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list); + pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next); + pdata->pm_configured_flag = + ehci_readl(ehci, &ehci->regs->configured_flag); + pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]); + + /* clear the W1C bits */ + pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS); + + pdata->suspended = 1; +#if defined(CONFIG_USB_EHCI_ARC_H2_WAKE_UP) || \ + defined(CONFIG_USB_EHCI_ARC_OTG_WAKE_UP) + /* enable remote wake up irq */ + usb_wakeup_set(&(pdev->dev), 1); + + /* We CAN NOT enable wake up by connetion and disconnection + * concurrently */ + tmp = ehci_readl(ehci, &ehci->regs->port_status[0]); + /* if there is no usb device connectted */ + if (tmp & PORT_CONNECT) { + /* enable wake up by usb device disconnection */ + tmp |= PORT_WKDISC_E; + tmp &= ~(PORT_WKOC_E | PORT_WKCONN_E); + } else { + /* enable wake up by usb device insertion */ + tmp |= PORT_WKCONN_E; + tmp &= ~(PORT_WKOC_E | PORT_WKDISC_E); + } + ehci_writel(ehci, tmp, &ehci->regs->port_status[0]); + + /* Set the port into suspend */ + tmp = ehci_readl(ehci, &ehci->regs->port_status[0]); + tmp |= PORT_SUSPEND; + ehci_writel(ehci, tmp, &ehci->regs->port_status[0]); + + /* Disable PHY clock */ + tmp = ehci_readl(ehci, &ehci->regs->port_status[0]); + tmp |= PORT_PHCD; + ehci_writel(ehci, tmp, &ehci->regs->port_status[0]); +#else + /* clear PP to cut power to the port */ + tmp = ehci_readl(ehci, &ehci->regs->port_status[0]); + tmp &= ~PORT_POWER; + ehci_writel(ehci, tmp, &ehci->regs->port_status[0]); + + /* disable the PHY clock */ + tmp = ehci_readl(ehci, &ehci->regs->port_status[0]); + tmp |= PORT_PHCD; + ehci_writel(ehci, tmp, &ehci->regs->port_status[0]); +#endif + return 0; +} + +static void ehci_lpm_toggle(struct work_struct *unused) +{ + /* Enter low power IDLE now */ + wakeup_value = 1; + + /* Ehci is resuming */ + ehci_suspending = 0; +} + +static int ehci_fsl_drv_resume(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + u32 tmp; + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + + pr_debug("%s('%s'): suspend=%d already_suspended=%d\n", __func__, + pdata->name, pdata->suspended, pdata->already_suspended); + + /* + * If the controller was already suspended at suspend time, + * then don't resume it now. + */ + if (pdata->already_suspended) { + pr_debug("already suspended, leaving early\n"); + pdata->already_suspended = 0; + return 0; + } + + if (!pdata->suspended) { + pr_debug("not suspended, leaving early\n"); + return 0; + } + + pdata->suspended = 0; + + pr_debug("%s resuming...\n", __func__); + + /* Wakeup EHCI if it is in LPM again */ + ehci_hcd_recalc_work(); + + /* set host mode */ + fsl_platform_set_host_mode(hcd); + + /* restore EHCI registers */ + ehci_writel(ehci, pdata->pm_command, &ehci->regs->command); + ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable); + ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index); + ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment); + ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list); + ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next); + ehci_writel(ehci, pdata->pm_configured_flag, + &ehci->regs->configured_flag); + ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]); + + set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + pdev->dev.power.power_state = PMSG_ON; + + tmp = ehci_readl(ehci, &ehci->regs->command); + tmp |= CMD_RUN; + ehci_writel(ehci, tmp, &ehci->regs->command); + + usb_hcd_resume_root_hub(hcd); + + /* Restart the workqueue */ + schedule_delayed_work(&ehci->dwork, msecs_to_jiffies(EHCI_IDLE_SUSPEND_THRESHOLD)); + + schedule_delayed_work(&toggle_idle_lp, msecs_to_jiffies(EHCI_ARC_TOGGLE_LPM)); + + return 0; +} +#endif /* CONFIG_USB_OTG */ + +MODULE_ALIAS("fsl-ehci"); + +static struct platform_driver ehci_fsl_driver = { + .probe = ehci_fsl_drv_probe, + .remove = ehci_fsl_drv_remove, + .shutdown = usb_hcd_platform_shutdown, +#ifdef CONFIG_PM + .suspend = ehci_fsl_drv_suspend, + .resume = ehci_fsl_drv_resume, +#endif + .driver = { + .name = "fsl-ehci", + }, +}; diff -urN linux-2.6.26/drivers/usb/host/ehci-fsl.h linux-2.6.26-lab126/drivers/usb/host/ehci-fsl.h --- linux-2.6.26/drivers/usb/host/ehci-fsl.h 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/host/ehci-fsl.h 2010-08-10 04:17:12.000000000 -0400 @@ -19,6 +19,9 @@ #define _EHCI_FSL_H /* offsets for the non-ehci registers in the FSL SOC USB controller */ +#define FSL_SOC_USB_SBUSCFG 0x90 +#define FSL_SOC_USB_BURSTSIZE 0x160 +#define FSL_SOC_USB_TXFILLTUNING 0x164 #define FSL_SOC_USB_ULPIVP 0x170 #define FSL_SOC_USB_PORTSC1 0x184 #define PORT_PTS_MSK (3<<30) @@ -26,8 +29,12 @@ #define PORT_PTS_ULPI (2<<30) #define PORT_PTS_SERIAL (3<<30) #define PORT_PTS_PTW (1<<28) +#define PORT_PTS_PHCD (1<<23) #define FSL_SOC_USB_PORTSC2 0x188 #define FSL_SOC_USB_USBMODE 0x1a8 +#define USBMODE_CM_HOST (3 << 0) /* controller mode: host */ +#define USBMODE_ES (1 << 2) /* (Big) Endian Select */ + #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ @@ -35,4 +42,11 @@ #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */ #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */ #define SNOOP_SIZE_2GB 0x1e + +#ifdef CONFIG_ARCH_MXC +#include +#elif CONFIG_PPC32 +#include +#endif + #endif /* _EHCI_FSL_H */ diff -urN linux-2.6.26/drivers/usb/host/ehci-hcd.c linux-2.6.26-lab126/drivers/usb/host/ehci-hcd.c --- linux-2.6.26/drivers/usb/host/ehci-hcd.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/host/ehci-hcd.c 2010-09-02 21:21:01.000000000 -0400 @@ -34,6 +34,7 @@ #include #include #include +#include #include "../core/hcd.h" @@ -43,6 +44,11 @@ #include #include +#include +#include + +#include + /*-------------------------------------------------------------------------*/ /* @@ -110,6 +116,7 @@ /*-------------------------------------------------------------------------*/ + /* * handshake - spin reading hc until handshake completes or fails * @ptr: address of hc register to be read @@ -145,16 +152,6 @@ return -ETIMEDOUT; } -static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr, - u32 mask, u32 done, int usec) -{ - int error = handshake(ehci, ptr, mask, done, usec); - if (error) - ehci_to_hcd(ehci)->state = HC_STATE_HALT; - - return error; -} - /* force HC to halt state from unknown (EHCI spec section 2.3) */ static int ehci_halt (struct ehci_hcd *ehci) { @@ -173,6 +170,22 @@ STS_HALT, STS_HALT, 16 * 125); } +static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr, + u32 mask, u32 done, int usec) +{ + int error; + + error = handshake(ehci, ptr, mask, done, usec); + if (error) { + ehci_halt(ehci); + ehci_to_hcd(ehci)->state = HC_STATE_HALT; + ehci_err(ehci, "force halt; handhake %p %08x %08x -> %d\n", + ptr, mask, done, error); + } + + return error; +} + /* put TDI/ARC silicon into EHCI mode */ static void tdi_reset (struct ehci_hcd *ehci) { @@ -241,23 +254,594 @@ STS_ASS | STS_PSS, 0, 16 * 125); } +/* + * USB EHCI low power idle mode. + */ +extern int wakeup_value; /* Enter IDLE or not */ +#define EHCI_IDLE_SAMPLING_RATE 1000 /* time (ms) between idle loop iterations */ + +atomic_t ehci_irq_last_count = ATOMIC_INIT(0); +atomic_t ehci_irq_current_count = ATOMIC_INIT(0); +static int kick_off_delayed_work = 0; +struct ehci_hcd *ehci_low_power; + +static void ehci_idle_count(struct work_struct *unused); +atomic_t suspended = ATOMIC_INIT(0); +static struct clk *usb_ahb_clk; + +int suspend_count = 0; +EXPORT_SYMBOL(suspend_count); + /*-------------------------------------------------------------------------*/ static void end_unlink_async(struct ehci_hcd *ehci); static void ehci_work(struct ehci_hcd *ehci); #include "ehci-hub.c" +#ifdef CONFIG_USB_STATIC_IRAM +#include "ehci-mem-iram.c" +#include "ehci-q-iram.c" +#else #include "ehci-mem.c" #include "ehci-q.c" +#endif #include "ehci-sched.c" /*-------------------------------------------------------------------------*/ +/* + * Suspend the USB bus that is now idle + */ +static int ehci_idle_bus_suspend (struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci (hcd); + int port; + int mask; + + ehci_dbg(ehci, "suspend root hub\n"); + + if (time_before (jiffies, ehci->next_statechange)) + mdelay(15); + + del_timer_sync(&ehci->watchdog); + del_timer_sync(&ehci->iaa_watchdog); + + port = HCS_N_PORTS (ehci->hcs_params); + + /* stop schedules, clean any completed work */ + if (HC_IS_RUNNING(hcd->state)) { + ehci_quiesce (ehci); + hcd->state = HC_STATE_QUIESCING; + } + + ehci->command = ehci_readl(ehci, &ehci->regs->command); + + ehci_work(ehci); + + ehci->bus_suspended = 0; + ehci->owned_ports = 0; + while (port--) { + u32 __iomem *reg = &ehci->regs->port_status [port]; + u32 t1 = ehci_readl(ehci, reg) & ~PORT_RWC_BITS; + u32 t2 = t1; + + /* keep track of which ports we suspend */ + if (t1 & PORT_OWNER) + set_bit(port, &ehci->owned_ports); + else if ((t1 & PORT_PE) && !(t1 & PORT_SUSPEND)) { + t2 |= PORT_SUSPEND; + set_bit(port, &ehci->bus_suspended); + } + + /* enable remote wakeup on all ports */ + t2 &= ~PORT_WAKE_BITS; + + if (t1 != t2) { + ehci_vdbg (ehci, "port %d, %08x -> %08x\n", + port + 1, t1, t2); + ehci_writel(ehci, t2, reg); + } + } + + if (ehci->bus_suspended) + udelay(150); + + ehci_halt (ehci); + hcd->state = HC_STATE_SUSPENDED; + + if (ehci->reclaim) + end_unlink_async(ehci); + + mask = INTR_MASK; + mask &= ~STS_PCD; + + ehci_writel(ehci, mask, &ehci->regs->intr_enable); + ehci_readl(ehci, &ehci->regs->intr_enable); + + ehci->next_statechange = jiffies + msecs_to_jiffies(10); + del_timer_sync(&ehci->watchdog); + + mdelay(100); + return 0; +} + +/* caller has locked the root hub, and should reset/reinit on error */ +static int ehci_idle_bus_resume (struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci (hcd); + u32 temp; + u32 power_okay; + int i; + + ehci_dbg (ehci, "ehci_idle_bus_resume\n"); + + if (time_before (jiffies, ehci->next_statechange)) + mdelay(15); + + if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { + return -ESHUTDOWN; + } + + power_okay = ehci_readl(ehci, &ehci->regs->intr_enable); + ehci_dbg(ehci, "resume root hub%s\n", + power_okay ? "" : " after power loss"); + + ehci_writel(ehci, 0, &ehci->regs->intr_enable); + ehci_writel(ehci, 0, &ehci->regs->segment); + ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); + ehci_writel(ehci, (u32) ehci->async->qh_dma, &ehci->regs->async_next); + ehci_writel(ehci, ehci->command, &ehci->regs->command); + mdelay(100); + + i = HCS_N_PORTS (ehci->hcs_params); + while (i--) { + temp = ehci_readl(ehci, &ehci->regs->port_status [i]); + temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); + if (test_bit(i, &ehci->bus_suspended) && + (temp & PORT_SUSPEND)) { + ehci->reset_done [i] = jiffies + msecs_to_jiffies (20); + temp |= PORT_RESUME; + } + ehci_writel(ehci, temp, &ehci->regs->port_status [i]); + } + + mdelay(100); + + i = HCS_N_PORTS (ehci->hcs_params); + while (i--) { + temp = ehci_readl(ehci, &ehci->regs->port_status [i]); + if (test_bit(i, &ehci->bus_suspended) && + (temp & PORT_SUSPEND)) { + temp &= ~(PORT_RWC_BITS | PORT_RESUME); + ehci_writel(ehci, temp, &ehci->regs->port_status [i]); + ehci_vdbg (ehci, "resumed port %d\n", i + 1); + } + } + + (void) ehci_readl(ehci, &ehci->regs->command); + + temp = 0; + if (ehci->async->qh_next.qh) + temp |= CMD_ASE; + if (ehci->periodic_sched) + temp |= CMD_PSE; + if (temp) { + ehci->command |= temp; + ehci_writel(ehci, ehci->command, &ehci->regs->command); + } + + ehci->next_statechange = jiffies + msecs_to_jiffies(5); + hcd->state = HC_STATE_RUNNING; + ehci_writel(ehci, INTR_MASK, &ehci->regs->intr_enable); + mdelay(100); + return 0; +} + +static int ehci_idle_bus_suspend_nonatomic (struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci (hcd); + int port; + int mask; + + ehci_dbg(ehci, "suspend root hub\n"); + + if (time_before (jiffies, ehci->next_statechange)) + msleep(5); + + del_timer_sync(&ehci->watchdog); + del_timer_sync(&ehci->iaa_watchdog); + + port = HCS_N_PORTS (ehci->hcs_params); + spin_lock_irq (&ehci->lock); + + /* stop schedules, clean any completed work */ + if (HC_IS_RUNNING(hcd->state)) { + ehci_quiesce (ehci); + hcd->state = HC_STATE_QUIESCING; + } + + ehci->command = ehci_readl(ehci, &ehci->regs->command); + + ehci_work(ehci); + + ehci->bus_suspended = 0; + ehci->owned_ports = 0; + while (port--) { + u32 __iomem *reg = &ehci->regs->port_status [port]; + u32 t1 = ehci_readl(ehci, reg) & ~PORT_RWC_BITS; + u32 t2 = t1; + + /* keep track of which ports we suspend */ + if (t1 & PORT_OWNER) + set_bit(port, &ehci->owned_ports); + else if ((t1 & PORT_PE) && !(t1 & PORT_SUSPEND)) { + t2 |= PORT_SUSPEND; + set_bit(port, &ehci->bus_suspended); + } + + /* enable remote wakeup on all ports */ + if (hcd->self.root_hub->do_remote_wakeup) + t2 |= PORT_WAKE_BITS; + else + t2 &= ~PORT_WAKE_BITS; + + if (t1 != t2) { + ehci_vdbg (ehci, "port %d, %08x -> %08x\n", + port + 1, t1, t2); + ehci_writel(ehci, t2, reg); + } + } + + if (ehci->bus_suspended) + udelay(150); + + ehci_halt (ehci); + hcd->state = HC_STATE_SUSPENDED; + + if (ehci->reclaim) + end_unlink_async(ehci); + + mask = INTR_MASK; + if (!hcd->self.root_hub->do_remote_wakeup) + mask &= ~STS_PCD; + + ehci_writel(ehci, mask, &ehci->regs->intr_enable); + ehci_readl(ehci, &ehci->regs->intr_enable); + + ehci->next_statechange = jiffies + msecs_to_jiffies(10); + spin_unlock_irq (&ehci->lock); + del_timer_sync(&ehci->watchdog); + return 0; +} + +/* caller has locked the root hub, and should reset/reinit on error */ +static int ehci_idle_bus_resume_nonatomic (struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci (hcd); + u32 temp; + u32 power_okay; + int i; + u8 resume_needed = 0; + + if (time_before (jiffies, ehci->next_statechange)) + msleep(5); + + spin_lock_irq (&ehci->lock); + if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { + spin_unlock_irq(&ehci->lock); + return -ESHUTDOWN; + } + + power_okay = ehci_readl(ehci, &ehci->regs->intr_enable); + ehci_dbg(ehci, "resume root hub%s\n", + power_okay ? "" : " after power loss"); + + ehci_writel(ehci, 0, &ehci->regs->intr_enable); + + ehci_writel(ehci, 0, &ehci->regs->segment); + ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); + ehci_writel(ehci, (u32) ehci->async->qh_dma, &ehci->regs->async_next); + + ehci_writel(ehci, ehci->command, &ehci->regs->command); + spin_unlock_irq(&ehci->lock); + msleep(8); + spin_lock_irq(&ehci->lock); + + i = HCS_N_PORTS (ehci->hcs_params); + while (i--) { + temp = ehci_readl(ehci, &ehci->regs->port_status [i]); + temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); + if (test_bit(i, &ehci->bus_suspended) && + (temp & PORT_SUSPEND)) { + ehci->reset_done [i] = jiffies + msecs_to_jiffies (20); + temp |= PORT_RESUME; + resume_needed = 1; + } + ehci_writel(ehci, temp, &ehci->regs->port_status [i]); + } + + if (resume_needed) { + spin_unlock_irq(&ehci->lock); + msleep(20); + spin_lock_irq(&ehci->lock); + } + + i = HCS_N_PORTS (ehci->hcs_params); + while (i--) { + temp = ehci_readl(ehci, &ehci->regs->port_status [i]); + if (test_bit(i, &ehci->bus_suspended) && + (temp & PORT_SUSPEND)) { + temp &= ~(PORT_RWC_BITS | PORT_RESUME); + ehci_writel(ehci, temp, &ehci->regs->port_status [i]); + ehci_vdbg (ehci, "resumed port %d\n", i + 1); + } + } + + (void) ehci_readl(ehci, &ehci->regs->command); + + temp = 0; + if (ehci->async->qh_next.qh) + temp |= CMD_ASE; + if (ehci->periodic_sched) + temp |= CMD_PSE; + if (temp) { + ehci->command |= temp; + ehci_writel(ehci, ehci->command, &ehci->regs->command); + } + + ehci->next_statechange = jiffies + msecs_to_jiffies(5); + hcd->state = HC_STATE_RUNNING; + ehci_writel(ehci, INTR_MASK, &ehci->regs->intr_enable); + spin_unlock_irq (&ehci->lock); + ehci_handover_companion_ports(ehci); + return 0; +} + + +/* Flag that keeps track of USB HC1 in low power idle mode */ +extern int usb_hc1_gated; + +static int in_deep_idle = 0; +static int deep_idle_enable_value = 0; + +/* Ehci is ready to suspend */ +int ehci_suspending = 0; + +/* Audio playing flag */ +extern int mx35_luigi_audio_playing_flag; + +static void ehci_low_power_enter(struct ehci_hcd *ehci) +{ + if (atomic_read(&suspended) == 1) + return; + + /* Ehci is suspending, return */ + if (ehci_suspending) + return; + + if (mx35_luigi_audio_playing_flag) + return; + + if (wakeup_value == 1) { + ehci_dbg (ehci, "entering idle\n"); + spin_lock_irq(&ehci->lock); + + atomic_set(&suspended, 1); + + USBCTRL |= UCTRL_H2WIE; + + ehci_idle_bus_suspend(ehci_to_hcd(ehci)); + ehci_low_power = ehci; + + usb_hc1_gated = 1; + suspend_count++; + if (deep_idle_enable_value) { + ehci_dbg(ehci, "entering deep idle\n"); + clk_disable(usb_ahb_clk); + in_deep_idle = 1; + } + + spin_unlock_irq(&ehci->lock); + printk(KERN_DEBUG "ehci entering lpm\n"); + } +} + +static void ehci_low_power_exit(void) +{ + if (wakeup_value == 0) + return; + + if (atomic_read(&suspended) == 0) { + return; + } + + if (mx35_luigi_audio_playing_flag && !atomic_read(&suspended)) + return; + + spin_lock_irq(&ehci_low_power->lock); + + atomic_set(&suspended, 0); + + if (in_deep_idle) { + ehci_dbg(ehci_low_power, "leaving deep idle\n"); + clk_enable(usb_ahb_clk); + in_deep_idle = 0; + } + + usb_hc1_gated = 0; + + ehci_idle_bus_resume(ehci_to_hcd(ehci_low_power)); + + USBCTRL &= ~(UCTRL_H2WIE); + ehci_dbg (ehci_low_power, "left idle\n"); + spin_unlock_irq (&ehci_low_power->lock); + printk(KERN_DEBUG "ehci exiting lpm\n"); +} + +static void ehci_low_power_enter_nonatomic (struct ehci_hcd *ehci) +{ + if (atomic_read(&suspended) == 1) + return; + + /* Ehci is suspending, return */ + if (ehci_suspending) + return; + + if (mx35_luigi_audio_playing_flag) + return; + + if (wakeup_value == 1) { + ehci_dbg (ehci, "entering idle\n"); + spin_lock_irq(&ehci->lock); + ehci_low_power = ehci; + USBCTRL |= UCTRL_H2WIE; + + spin_unlock_irq(&ehci->lock); + ehci_idle_bus_suspend_nonatomic(ehci_to_hcd(ehci)); + spin_lock_irq(&ehci->lock); + + usb_hc1_gated = 1; + suspend_count++; + if (deep_idle_enable_value) { + ehci_dbg(ehci, "entering deep idle\n"); + clk_disable(usb_ahb_clk); + in_deep_idle = 1; + } + + atomic_set(&suspended, 1); + spin_unlock_irq(&ehci->lock); + + printk("Enter LPM\n"); + } + +} + +static void ehci_low_power_exit_nonatomic (void) +{ + if (wakeup_value == 0) + return; + + if (atomic_read(&suspended) == 0) { + return; + } + + if (mx35_luigi_audio_playing_flag && !atomic_read(&suspended)) + return; + + spin_lock_irq(&ehci_low_power->lock); + if (in_deep_idle) { + ehci_dbg(ehci_low_power, "leaving deep idle\n"); + clk_enable(usb_ahb_clk); + in_deep_idle = 0; + } + + usb_hc1_gated = 0; + + spin_unlock_irq(&ehci_low_power->lock); + ehci_idle_bus_resume_nonatomic(ehci_to_hcd(ehci_low_power)); + spin_lock_irq(&ehci_low_power->lock); + + USBCTRL &= ~(UCTRL_H2WIE); + atomic_set(&suspended, 0); + spin_unlock_irq(&ehci_low_power->lock); + ehci_dbg (ehci_low_power, "left idle\n"); + + printk("left idle\n"); +} + +/* time in seconds required for USB to sleep if there is no activity */ +#define EHCI_NORMAL_IDLE_THRESHOLD 3 /* normal case (seconds) */ +#define EHCI_HOST_WAKE_IDLE_THRESHOLD 30 /* after deep idle host wake */ +#define EHCI_IRQ_SAMPLING_RATE 1000 /* 1 seconds after the ehci IRQs begin */ + +atomic_t ehci_idle_counter = ATOMIC_INIT(0); +atomic_t ehci_idle_threshold = ATOMIC_INIT(EHCI_NORMAL_IDLE_THRESHOLD); + +static void ehci_idle_count(struct work_struct *work) +{ + struct ehci_hcd *ehci = container_of(work, struct ehci_hcd, dwork.work); + unsigned long temp; + + if (atomic_read(&ehci_irq_last_count) != + atomic_read(&ehci_irq_current_count)) { + temp = atomic_read(&ehci_irq_current_count); + atomic_set(&ehci_irq_last_count, temp); + atomic_set(&ehci_idle_counter, 0); + if (!ehci_suspending) { + schedule_delayed_work(&ehci->dwork, + msecs_to_jiffies(EHCI_IDLE_SAMPLING_RATE)); + } + } + else { + if (atomic_read(&ehci_idle_counter) >= + atomic_read(&ehci_idle_threshold)) { + atomic_set(&ehci_idle_threshold, EHCI_NORMAL_IDLE_THRESHOLD); + atomic_set(&ehci_idle_counter, 0); + ehci_low_power_enter_nonatomic(ehci); + kick_off_delayed_work = 0; + } + else { + atomic_inc(&ehci_idle_counter); + ehci_dbg(ehci, "no activity\n"); + if (!ehci_suspending) { + schedule_delayed_work(&ehci->dwork, + msecs_to_jiffies(EHCI_IDLE_SAMPLING_RATE)); + } + } + } +} + +void ehci_hcd_recalc_work(void) +{ + if (atomic_read(&suspended) == 0) { + return; + } + + atomic_set(&ehci_idle_counter, 0); + ehci_low_power_exit(); +} +EXPORT_SYMBOL(ehci_hcd_recalc_work); + +static void ehci_hcd_recalc_work_nonatomic(void) +{ + if (atomic_read(&suspended) == 0) { + return; + } + + atomic_set(&ehci_idle_counter, 0); + ehci_low_power_exit_nonatomic(); +} + +void ehci_hcd_restart_idle(void) +{ + if ((atomic_read(&suspended) == 0) && suspend_count) { + atomic_set(&ehci_idle_counter, 0); + schedule_delayed_work(&ehci_low_power->dwork, + msecs_to_jiffies(EHCI_IDLE_SAMPLING_RATE)); + } +} +EXPORT_SYMBOL(ehci_hcd_restart_idle); + +static void ehci_hcd_host_wake(void) +{ + /* if in deep idle, set long idle threshold */ + if (deep_idle_enable_value) { + atomic_set(&ehci_idle_threshold, EHCI_HOST_WAKE_IDLE_THRESHOLD); + } + ehci_hcd_recalc_work_nonatomic(); +} + static void ehci_iaa_watchdog(unsigned long param) { struct ehci_hcd *ehci = (struct ehci_hcd *) param; unsigned long flags; + /* + * If suspended, no need to run the timer and wakeup the bus + */ + if (atomic_read(&suspended) == 1) + return; + spin_lock_irqsave (&ehci->lock, flags); /* Lost IAA irqs wedge things badly; seen first with a vt8235. @@ -306,6 +890,12 @@ struct ehci_hcd *ehci = (struct ehci_hcd *) param; unsigned long flags; + /* + * If suspended, no need to run the timer and wakeup the bus + */ + if (atomic_read(&suspended) == 1) + return; + spin_lock_irqsave(&ehci->lock, flags); /* stop async processing after it's idled a bit */ @@ -378,7 +968,7 @@ port--, NULL, 0); /* Flush those writes */ ehci_readl(ehci, &ehci->regs->command); - msleep(20); + mdelay(20); } /*-------------------------------------------------------------------------*/ @@ -422,9 +1012,14 @@ ehci_dbg (ehci, "stop\n"); + /* prevent mwan from waking up USB because module */ + /* is no longer available to respond to callback */ + wan_set_usb_wake_callback(NULL); + /* no more interrupts ... */ del_timer_sync (&ehci->watchdog); del_timer_sync(&ehci->iaa_watchdog); + cancel_rearming_delayed_work(&ehci->dwork); spin_lock_irq(&ehci->lock); if (HC_IS_RUNNING (hcd->state)) @@ -474,6 +1069,8 @@ ehci->iaa_watchdog.function = ehci_iaa_watchdog; ehci->iaa_watchdog.data = (unsigned long) ehci; + usb_ahb_clk = clk_get(NULL, "usb_ahb_clk"); + /* * hw default: 1K periodic list heads, one per frame. * periodic_size can shrink by USBCMD update if hcc_params allows. @@ -507,6 +1104,8 @@ ehci->async->qh_state = QH_STATE_LINKED; ehci->async->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); + INIT_DELAYED_WORK(&ehci->dwork, ehci_idle_count); + /* clear interrupt enables, set irq latency */ if (log2_irq_thresh < 0 || log2_irq_thresh > 6) log2_irq_thresh = 0; @@ -538,6 +1137,11 @@ } } ehci->command = temp; + wakeup_value = 1; + + /* the ehci structure has been initialized */ + schedule_delayed_work (&ehci->dwork, + msecs_to_jiffies(EHCI_IDLE_SAMPLING_RATE)); return 0; } @@ -609,7 +1213,7 @@ hcd->state = HC_STATE_RUNNING; ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ - msleep(5); + mdelay(5); up_write(&ehci_cf_port_reset_rwsem); temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase)); @@ -642,6 +1246,20 @@ spin_lock (&ehci->lock); + atomic_inc(&ehci_irq_current_count); + if (kick_off_delayed_work == 0) { + kick_off_delayed_work = 1; + + /* Resume the USB if needed */ + spin_unlock (&ehci->lock); + ehci_hcd_recalc_work(); + spin_lock (&ehci->lock); + + /* Kick off the delayed workqueue */ + schedule_delayed_work(&ehci->dwork, + msecs_to_jiffies(EHCI_IRQ_SAMPLING_RATE)); + } + status = ehci_readl(ehci, &ehci->regs->status); /* e.g. cardbus physical eject */ @@ -653,7 +1271,7 @@ status &= INTR_MASK; if (!status) { /* irq sharing? */ spin_unlock(&ehci->lock); - return IRQ_NONE; + goto out; } /* clear (just) interrupts */ @@ -745,6 +1363,7 @@ spin_unlock (&ehci->lock); if (pcd_status) usb_hcd_poll_rh_status(hcd); +out: return IRQ_HANDLED; } @@ -1009,6 +1628,11 @@ #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver #endif +#ifdef CONFIG_USB_EHCI_ARC +#include "ehci-arc.c" +#define PLATFORM_DRIVER ehci_fsl_driver +#endif + #ifdef CONFIG_PPC_PS3 #include "ehci-ps3.c" #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver diff -urN linux-2.6.26/drivers/usb/host/ehci-hub.c linux-2.6.26-lab126/drivers/usb/host/ehci-hub.c --- linux-2.6.26/drivers/usb/host/ehci-hub.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/host/ehci-hub.c 2010-08-10 04:17:12.000000000 -0400 @@ -194,6 +194,7 @@ u32 temp; u32 power_okay; int i; + u8 resume_needed = 0; if (time_before (jiffies, ehci->next_statechange)) msleep(5); @@ -228,7 +229,9 @@ /* Some controller/firmware combinations need a delay during which * they set up the port statuses. See Bugzilla #8190. */ - mdelay(8); + spin_unlock_irq(&ehci->lock); + msleep(8); + spin_lock_irq(&ehci->lock); /* manually resume the ports we suspended during bus_suspend() */ i = HCS_N_PORTS (ehci->hcs_params); @@ -239,11 +242,19 @@ (temp & PORT_SUSPEND)) { ehci->reset_done [i] = jiffies + msecs_to_jiffies (20); temp |= PORT_RESUME; + resume_needed = 1; } ehci_writel(ehci, temp, &ehci->regs->port_status [i]); } + + /* msleep for 20ms only if code is trying to resume port */ + if (resume_needed) { + spin_unlock_irq(&ehci->lock); + msleep(20); + spin_lock_irq(&ehci->lock); + } + i = HCS_N_PORTS (ehci->hcs_params); - mdelay (20); while (i--) { temp = ehci_readl(ehci, &ehci->regs->port_status [i]); if (test_bit(i, &ehci->bus_suspended) && @@ -533,6 +544,37 @@ desc->wHubCharacteristics = cpu_to_le16(temp); } +#ifdef CONFIG_USB_OTG +static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + u32 status; + + if (!port) + return -EINVAL; + port--; + + /* start port reset before HNP protocol time out */ + status = readl(&ehci->regs->port_status[port]); + if (!(status & PORT_CONNECT)) + return -ENODEV; + + /* khubd will finish the reset later */ + if (ehci_is_TDI(ehci)) + writel(PORT_RESET | (status & ~(PORT_CSC | PORT_PEC + | PORT_OCC)), &ehci->regs->port_status[port]); + else + writel(PORT_RESET, &ehci->regs->port_status[port]); + + return 0; +} +#else +static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port) +{ + return 0; +} +#endif /* CONFIG_USB_OTG */ + /*-------------------------------------------------------------------------*/ static int ehci_hub_control ( diff -urN linux-2.6.26/drivers/usb/host/ehci-mem-iram.c linux-2.6.26-lab126/drivers/usb/host/ehci-mem-iram.c --- linux-2.6.26/drivers/usb/host/ehci-mem-iram.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/usb/host/ehci-mem-iram.c 2010-08-10 04:17:12.000000000 -0400 @@ -0,0 +1,506 @@ +/* + * Copyright (c) 2001 by David Brownell + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* this file is part of ehci-hcd.c */ + +/*-------------------------------------------------------------------------*/ + +/* + * There's basically three types of memory: + * - data used only by the HCD ... kmalloc is fine + * - async and periodic schedules, shared by HC and HCD ... these + * need to use dma_pool or dma_alloc_coherent + * - driver buffers, read/written by HC ... single shot DMA mapped + * + * There's also "register" data (e.g. PCI or SOC), which is memory mapped. + * No memory seen by this driver is pageable. + */ + +/*-------------------------------------------------------------------------*/ + +/* Allocate the key transfer structures from the previously allocated pool */ +#include + +bool use_iram_qtd; + +struct memDesc { + u32 start; + u32 end; + struct memDesc *next; +} ; + +static u32 g_usb_pool_start; +static s32 g_usb_pool_count; +static u32 g_total_pages; +static u32 g_alignment = 32; +struct memDesc *g_allocated_desc; +static spinlock_t g_usb_sema; +static u32 g_debug_qtd_allocated; +static u32 g_debug_qH_allocated; +static int g_alloc_map; + +/*! + * usb_pool_initialize + * + * @param memPool start address of the pool + * @param poolSize memory pool size + * @param alignment alignment for example page alignmnet will be 4K + * + * @return 0 for success -1 for errors + */ +static int usb_pool_initialize(u32 memPool, u32 poolSize, u32 alignment) +{ + if (g_usb_pool_count) { + printk(KERN_INFO "usb_pool_initialize : already initialzed.\n"); + return 0; + } + + g_alignment = alignment; + if (g_alignment == 0) { + printk(KERN_INFO + "usb_pool_initialize : g_alignment can not be zero.\n"); + g_alignment = 32; + } + + g_total_pages = poolSize / g_alignment; + g_usb_pool_start = (u32) memPool; + + g_allocated_desc = kmalloc(sizeof(struct memDesc), GFP_KERNEL); + if (!g_allocated_desc) { + printk(KERN_ALERT "usb_pool_initialize : kmalloc failed \n"); + return (-1); + } + + g_allocated_desc->start = 0; + g_allocated_desc->end = 0; + g_allocated_desc->next = NULL; + + spin_lock_init(&g_usb_sema); + g_usb_pool_count++; + return (0); +} + +static void usb_pool_deinit() +{ + if (--g_usb_pool_count < 0) + g_usb_pool_count = 0; +} + +/*! + * usb_malloc + * + * @param size memory pool size + * + * @return physical address, 0 for error + */ +static u32 usb_malloc(u32 size, gfp_t mem_flags) +{ + unsigned long flags; + struct memDesc *prevDesc = NULL; + struct memDesc *nextDesc = NULL; + struct memDesc *currentDesc = NULL; + u32 pages = (size + g_alignment - 1) / g_alignment; + + if ((size == 0) || (pages > g_total_pages)) + return 0; + + currentDesc = kmalloc(sizeof(struct memDesc), mem_flags); + if (!currentDesc) { + printk(KERN_ALERT "usb_malloc: kmalloc failed \n"); + return 0; + } + + spin_lock_irqsave(&g_usb_sema, flags); + + /* Create the first Allocated descriptor */ + if (!g_allocated_desc->next) { + g_allocated_desc->next = currentDesc; + currentDesc->start = 0; + currentDesc->end = pages; + currentDesc->next = NULL; + spin_unlock_irqrestore(&g_usb_sema, flags); + return (g_usb_pool_start + currentDesc->start * g_alignment); + } + + /* Find the free spot */ + prevDesc = g_allocated_desc; + while (prevDesc->next) { + nextDesc = prevDesc->next; + if (pages <= nextDesc->start - prevDesc->end) { + currentDesc->start = prevDesc->end; + currentDesc->end = currentDesc->start + pages; + currentDesc->next = nextDesc; + prevDesc->next = currentDesc; + break; + } + prevDesc = nextDesc; + } + + /* Do not find the free spot inside the chain, append to the end */ + if (!prevDesc->next) { + if (pages > (g_total_pages - prevDesc->end)) { + spin_unlock_irqrestore(&g_usb_sema, flags); + kfree(currentDesc); + return 0; + } else { + currentDesc->start = prevDesc->end; + currentDesc->end = currentDesc->start + pages; + currentDesc->next = NULL; + prevDesc->next = currentDesc; + } + } + + spin_unlock_irqrestore(&g_usb_sema, flags); + return (g_usb_pool_start + currentDesc->start * g_alignment); +} + +/*! + * usb_free + * + * @param physical physical address try to free + * + */ +static void usb_free(u32 physical) +{ + unsigned long flags; + struct memDesc *prevDesc = NULL; + struct memDesc *nextDesc = NULL; + u32 pages = (physical - g_usb_pool_start) / g_alignment; + + /* Protect the memory pool data structures. */ + spin_lock_irqsave(&g_usb_sema, flags); + + prevDesc = g_allocated_desc; + while (prevDesc->next) { + nextDesc = prevDesc->next; + if (nextDesc->start == pages) { + prevDesc->next = nextDesc->next; + kfree(nextDesc); + break; + } + prevDesc = prevDesc->next; + } + /* All done with memory pool data structures. */ + spin_unlock_irqrestore(&g_usb_sema, flags); +} + +static int address_to_buffer(struct ehci_hcd *ehci, int address) +{ + int i; + + for (i = 0; i < IRAM_NTD; i++) { + if (ehci->usb_address[i] == address) + return i; + } + return IRAM_NTD; +} + +static void use_buffer(struct ehci_hcd *ehci, int address) +{ + int i; + + for (i = 0; i < IRAM_NTD; i++) { + if (ehci->usb_address[i] == address) + return; + } + + if (ehci->usb_address[0] == 0) { + ehci->usb_address[0] = address; + printk(KERN_INFO "usb_address[0] %x\n", address); + return; + } else if (ehci->usb_address[1] == 0) { + ehci->usb_address[1] = address; + printk(KERN_INFO "usb_address[1] %x\n", address); + return; + } else + printk(KERN_ALERT "qh_make run out of iRAM, already be used"); +} + +static u32 alloc_iram_buf(void) +{ + int i; + + for (i = 0; i < IRAM_NTD; i++) { + if (!(g_alloc_map & (1 << i))) { + g_alloc_map |= (1 << i); + return USB_IRAM_BASE_ADDR + i * (IRAM_TD_SIZE * 2); + } + } + panic("Out of IRAM buffers\n"); +} + +void free_iram_buf(u32 buf) +{ + int i = (buf - USB_IRAM_BASE_ADDR) / (IRAM_TD_SIZE * 2); + + g_alloc_map &= ~(1 << i); +} + +static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd, + dma_addr_t dma) +{ + memset(qtd, 0, sizeof *qtd); + qtd->qtd_dma = dma; + qtd->hw_token = cpu_to_le32(QTD_STS_HALT); + qtd->hw_next = EHCI_LIST_END(ehci); + qtd->hw_alt_next = EHCI_LIST_END(ehci); + INIT_LIST_HEAD(&qtd->qtd_list); +} + +static struct ehci_qtd *ehci_qtd_alloc(struct ehci_hcd *ehci, gfp_t flags) +{ + struct ehci_qtd *qtd; + dma_addr_t dma; + + if (use_iram_qtd) { + dma = usb_malloc(sizeof(struct ehci_qtd), flags); + if (dma != 0) + qtd = (struct ehci_qtd *)IO_ADDRESS(dma); + else + qtd = dma_pool_alloc(ehci->qtd_pool, flags, &dma); + } + else + qtd = dma_pool_alloc(ehci->qtd_pool, flags, &dma); + + if (qtd != NULL) { + ehci_qtd_init(ehci, qtd, dma); + ++g_debug_qtd_allocated; + } else { + panic + ("out of i-ram for qtd allocation g_debug_qtd_allocated %d \ + size%d \n", g_debug_qtd_allocated, + sizeof(struct ehci_qtd)); + } + return qtd; +} + +static inline void ehci_qtd_free(struct ehci_hcd *ehci, struct ehci_qtd *qtd) +{ + if ((qtd->qtd_dma & (USB_IRAM_BASE_ADDR & 0xFFF00000)) == + (USB_IRAM_BASE_ADDR & 0xFFF00000)) + usb_free(qtd->qtd_dma); + else + dma_pool_free(ehci->qtd_pool, qtd, qtd->qtd_dma); + --g_debug_qtd_allocated; +} + +static void qh_destroy(struct ehci_qh *qh) +{ + struct ehci_hcd *ehci = qh->ehci; + + /* clean qtds first, and know this is not linked */ + if (!list_empty(&qh->qtd_list) || qh->qh_next.ptr) { + ehci_dbg(ehci, "unused qh not empty!\n"); + BUG(); + } + if (qh->dummy) + ehci_qtd_free(ehci, qh->dummy); + int i; + for (i = 0; i < IRAM_NTD; i++) { + if (ehci->usb_address[i] == (qh->hw_info1 & 0x7F)) + ehci->usb_address[i] = 0; + } + + if ((qh->qh_dma & (USB_IRAM_BASE_ADDR & 0xFFF00000)) == + (USB_IRAM_BASE_ADDR & 0xFFF00000)) + usb_free(qh->qh_dma); + else + dma_pool_free(ehci->qh_pool, qh, qh->qh_dma); + --g_debug_qH_allocated; +} + +static struct ehci_qh *ehci_qh_alloc(struct ehci_hcd *ehci, gfp_t flags) +{ + struct ehci_qh *qh; + dma_addr_t dma; + + dma = usb_malloc(sizeof(struct ehci_qh), flags); + if (dma != 0) + qh = (struct ehci_qh *)IO_ADDRESS(dma); + else + qh = (struct ehci_qh *) + dma_pool_alloc(ehci->qh_pool, flags, &dma); + ++g_debug_qH_allocated; + if (qh == NULL) { + panic("run out of i-ram for qH allocation\n"); + return qh; + } + + memset(qh, 0, sizeof *qh); + qh->refcount = 1; + qh->ehci = ehci; + qh->qh_dma = dma; + INIT_LIST_HEAD(&qh->qtd_list); + + /* dummy td enables safe urb queuing */ + qh->dummy = ehci_qtd_alloc(ehci, flags); + if (qh->dummy == NULL) { + ehci_dbg(ehci, "no dummy td\n"); + dma_pool_free(ehci->qh_pool, qh, qh->qh_dma); + qh = NULL; + } + return qh; +} + +/* to share a qh (cpu threads, or hc) */ +static inline struct ehci_qh *qh_get(struct ehci_qh *qh) +{ + WARN_ON(!qh->refcount); + qh->refcount++; + return qh; +} + +static inline void qh_put(struct ehci_qh *qh) +{ + if (!--qh->refcount) + qh_destroy(qh); +} + +/*-------------------------------------------------------------------------*/ + +/* The queue heads and transfer descriptors are managed from pools tied + * to each of the "per device" structures. + * This is the initialisation and cleanup code. + */ + +static void ehci_mem_cleanup(struct ehci_hcd *ehci) +{ + if (ehci->async) + qh_put(ehci->async); + ehci->async = NULL; + + /* DMA consistent memory and pools */ + if (ehci->qtd_pool) + dma_pool_destroy(ehci->qtd_pool); + ehci->qtd_pool = NULL; + + if (ehci->qh_pool) { + dma_pool_destroy(ehci->qh_pool); + ehci->qh_pool = NULL; + } + + if (ehci->itd_pool) + dma_pool_destroy(ehci->itd_pool); + ehci->itd_pool = NULL; + + if (ehci->sitd_pool) + dma_pool_destroy(ehci->sitd_pool); + ehci->sitd_pool = NULL; + + if (ehci->periodic) + dma_free_coherent(ehci_to_hcd(ehci)->self.controller, + ehci->periodic_size * sizeof(u32), + ehci->periodic, ehci->periodic_dma); + ehci->periodic = NULL; + + if (ehci->iram_buffer[0]) + free_iram_buf(ehci->iram_buffer[0]); + if (ehci->iram_buffer[1]) + free_iram_buf(ehci->iram_buffer[1]); + + /* shadow periodic table */ + kfree(ehci->pshadow); + ehci->pshadow = NULL; + usb_pool_deinit(); +} + +/* remember to add cleanup code (above) if you add anything here */ +static int ehci_mem_init(struct ehci_hcd *ehci, gfp_t flags) +{ + int i; + g_usb_pool_count = 0; + g_debug_qtd_allocated = 0; + g_debug_qH_allocated = 0; + g_alloc_map = 0; + + if (cpu_is_mx37()) + use_iram_qtd = 0; + else + use_iram_qtd = 1; + + usb_pool_initialize(USB_IRAM_BASE_ADDR + IRAM_TD_SIZE * IRAM_NTD * 2, + USB_IRAM_SIZE - IRAM_TD_SIZE * IRAM_NTD * 2, 32); + + if (!ehci->iram_buffer[0]) { + ehci->iram_buffer[0] = alloc_iram_buf(); + ehci->iram_buffer_v[0] = IO_ADDRESS(ehci->iram_buffer[0]); + ehci->iram_buffer[1] = alloc_iram_buf(); + ehci->iram_buffer_v[1] = IO_ADDRESS(ehci->iram_buffer[1]); + } + + /* QTDs for control/bulk/intr transfers */ + ehci->qtd_pool = dma_pool_create("ehci_qtd", + ehci_to_hcd(ehci)->self.controller, + sizeof(struct ehci_qtd), + 32/* byte alignment (for hw parts) */ + , 4096 /* can't cross 4K */); + if (!ehci->qtd_pool) + goto fail; + + /* QHs for control/bulk/intr transfers */ + ehci->qh_pool = dma_pool_create("ehci_qh", + ehci_to_hcd(ehci)->self.controller, + sizeof(struct ehci_qh), + 32 /* byte alignment (for hw parts) */ , + 4096 /* can't cross 4K */); + if (!ehci->qh_pool) + goto fail; + + ehci->async = ehci_qh_alloc(ehci, flags); + if (!ehci->async) + goto fail; + + /* ITD for high speed ISO transfers */ + ehci->itd_pool = dma_pool_create("ehci_itd", + ehci_to_hcd(ehci)->self.controller, + sizeof(struct ehci_itd), + 32/* byte alignment (for hw parts) */ + , 4096 /* can't cross 4K */); + if (!ehci->itd_pool) + goto fail; + + /* SITD for full/low speed split ISO transfers */ + ehci->sitd_pool = dma_pool_create("ehci_sitd", + ehci_to_hcd(ehci)->self.controller, + sizeof(struct ehci_sitd), + 32/* byte alignment (for hw parts) */ + , 4096 /* can't cross 4K */); + if (!ehci->sitd_pool) + goto fail; + + ehci->periodic = (__le32 *) + dma_alloc_coherent(ehci_to_hcd(ehci)->self.controller, + ehci->periodic_size * sizeof(__le32), + &ehci->periodic_dma, 0); + + if (ehci->periodic == NULL) + goto fail; + + for (i = 0; i < ehci->periodic_size; i++) + ehci->periodic[i] = EHCI_LIST_END(ehci); + + /* software shadow of hardware table */ + ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags); + if (ehci->pshadow != NULL) + return 0; + +fail: + ehci_dbg(ehci, "couldn't init memory\n"); + ehci_mem_cleanup(ehci); + return -ENOMEM; +} diff -urN linux-2.6.26/drivers/usb/host/ehci-q-iram.c linux-2.6.26-lab126/drivers/usb/host/ehci-q-iram.c --- linux-2.6.26/drivers/usb/host/ehci-q-iram.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/usb/host/ehci-q-iram.c 2010-08-10 04:17:12.000000000 -0400 @@ -0,0 +1,1345 @@ +/* + * Copyright (C) 2001-2004 by David Brownell + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#undef EHCI_NO_ERR_COUNT +static size_t g_iram_size = IRAM_TD_SIZE; + +/* this file is part of ehci-hcd.c */ + +/*-------------------------------------------------------------------------*/ + +/* + * EHCI hardware queue manipulation ... the core. QH/QTD manipulation. + * + * Control, bulk, and interrupt traffic all use "qh" lists. They list "qtd" + * entries describing USB transactions, max 16-20kB/entry (with 4kB-aligned + * buffers needed for the larger number). We use one QH per endpoint, queue + * multiple urbs (all three types) per endpoint. URBs may need several qtds. + * + * ISO traffic uses "ISO TD" (itd, and sitd) records, and (along with + * interrupts) needs careful scheduling. Performance improvements can be + * an ongoing challenge. That's in "ehci-sched.c". + * + * USB 1.1 devices are handled (a) by "companion" OHCI or UHCI root hubs, + * or otherwise through transaction translators (TTs) in USB 2.0 hubs using + * (b) special fields in qh entries or (c) split iso entries. TTs will + * buffer low/full speed data so the host collects it at high speed. + */ + +/*-------------------------------------------------------------------------*/ +/* fill a qtd, returning how much of the buffer we were able to queue up */ +static int qtd_fill(struct ehci_hcd *ehci, struct ehci_qtd *qtd, dma_addr_t buf, + size_t len, int token, int maxpacket) +{ + int i, count; + u64 addr = buf; + struct urb *urb = qtd->urb; + + if (usb_pipebulk(urb->pipe) && + (address_to_buffer(ehci, usb_pipedevice(urb->pipe)) != 2)) { + urb->use_iram = 1; + qtd->buffer_offset = (size_t) (buf - urb->transfer_dma); + token |= QTD_IOC; + if (usb_pipeout(urb->pipe)) { + addr = ehci->iram_buffer[address_to_buffer(ehci, + usb_pipedevice(urb->pipe))]; + } else if (usb_pipein(urb->pipe)) { + addr = ehci->iram_buffer[address_to_buffer(ehci, + usb_pipedevice(urb->pipe))] + + g_iram_size; + } + } else { + urb->use_iram = 0; + addr = buf; + } + len = min(g_iram_size, len); + + /* one buffer entry per 4K ... first might be short or unaligned */ + qtd->hw_buf[0] = cpu_to_hc32(ehci, (u32) addr); + qtd->hw_buf_hi[0] = cpu_to_hc32(ehci, (u32) (addr >> 32)); + count = 0x1000 - (buf & 0x0fff); /* rest of that page */ + if (likely(len < count)) /* ... iff needed */ + count = len; + else { + buf += 0x1000; + buf &= ~0x0fff; + + /* per-qtd limit: from 16K to 20K (best alignment) */ + for (i = 1; count < len && i < 5; i++) { + addr = buf; + qtd->hw_buf[i] = cpu_to_hc32(ehci, (u32) addr); + qtd->hw_buf_hi[i] = + cpu_to_hc32(ehci, (u32) (addr >> 32)); + buf += 0x1000; + if ((count + 0x1000) < len) + count += 0x1000; + else + count = len; + } + + /* short packets may only terminate transfers */ + if (count != len) + count -= (count % maxpacket); + } + qtd->hw_token = cpu_to_hc32(ehci, (count << 16) | token); + qtd->length = count; + + return count; +} + +/*-------------------------------------------------------------------------*/ + +static inline void +qh_update(struct ehci_hcd *ehci, struct ehci_qh *qh, struct ehci_qtd *qtd) +{ + /* writes to an active overlay are unsafe */ + BUG_ON(qh->qh_state != QH_STATE_IDLE); + + qh->hw_qtd_next = QTD_NEXT(ehci, qtd->qtd_dma); + qh->hw_alt_next = EHCI_LIST_END(ehci); + + /* Except for control endpoints, we make hardware maintain data + * toggle (like OHCI) ... here (re)initialize the toggle in the QH, + * and set the pseudo-toggle in udev. Only usb_clear_halt() will + * ever clear it. + */ + if (!(qh->hw_info1 & cpu_to_hc32(ehci, 1 << 14))) { + unsigned is_out, epnum; + + is_out = !(qtd->hw_token & cpu_to_hc32(ehci, 1 << 8)); + epnum = (hc32_to_cpup(ehci, &qh->hw_info1) >> 8) & 0x0f; + if (unlikely(!usb_gettoggle(qh->dev, epnum, is_out))) { + qh->hw_token &= ~cpu_to_hc32(ehci, QTD_TOGGLE); + usb_settoggle(qh->dev, epnum, is_out, 1); + } + } + + /* HC must see latest qtd and qh data before we clear ACTIVE+HALT */ + wmb(); + qh->hw_token &= cpu_to_hc32(ehci, QTD_TOGGLE | QTD_STS_PING); +} + +/* if it weren't for a common silicon quirk (writing the dummy into the qh + * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault + * recovery (including urb dequeue) would need software changes to a QH... + */ +static void qh_refresh(struct ehci_hcd *ehci, struct ehci_qh *qh) +{ + struct ehci_qtd *qtd; + + if (list_empty(&qh->qtd_list)) + qtd = qh->dummy; + else { + qtd = list_entry(qh->qtd_list.next, struct ehci_qtd, qtd_list); + /* first qtd may already be partially processed */ + if (cpu_to_hc32(ehci, qtd->qtd_dma) == qh->hw_current) + qtd = NULL; + } + + if (qtd) + qh_update(ehci, qh, qtd); +} + +/*-------------------------------------------------------------------------*/ + +static int qtd_copy_status(struct ehci_hcd *ehci, + struct urb *urb, size_t length, u32 token) +{ + int status = -EINPROGRESS; + + /* count IN/OUT bytes, not SETUP (even short packets) */ + if (likely(QTD_PID(token) != 2)) + urb->actual_length += length - QTD_LENGTH(token); + + /* don't modify error codes */ + if (unlikely(urb->unlinked)) + return status; + + /* force cleanup after short read; not always an error */ + if (unlikely(IS_SHORT_READ(token))) + status = -EREMOTEIO; + + /* serious "can't proceed" faults reported by the hardware */ + if (token & QTD_STS_HALT) { + if (token & QTD_STS_BABBLE) { + /* FIXME "must" disable babbling device's port too */ + status = -EOVERFLOW; + } else if (token & QTD_STS_MMF) { + /* fs/ls interrupt xfer missed the complete-split */ + status = -EPROTO; + } else if (token & QTD_STS_DBE) { + status = (QTD_PID(token) == 1) /* IN ? */ + ? -ENOSR /* hc couldn't read data */ + : -ECOMM; /* hc couldn't write data */ + } else if (token & QTD_STS_XACT) { + /* timeout, bad crc, wrong PID, etc; retried */ + if (QTD_CERR(token)) + status = -EPIPE; + else { + ehci_dbg(ehci, "devpath %s ep%d%s 3strikes\n", + urb->dev->devpath, + usb_pipeendpoint(urb->pipe), + usb_pipein(urb->pipe) ? "in" : "out"); + status = -EPROTO; + } + /* CERR nonzero + no errors + halt --> stall */ + } else if (QTD_CERR(token)) + status = -EPIPE; + else /* unknown */ + status = -EPROTO; + + ehci_vdbg(ehci, + "dev%d ep%d%s qtd token %08x --> status %d\n", + usb_pipedevice(urb->pipe), + usb_pipeendpoint(urb->pipe), + usb_pipein(urb->pipe) ? "in" : "out", token, status); + + /* if async CSPLIT failed, try cleaning out the TT buffer */ + if (status != -EPIPE && urb->dev->tt && !usb_pipeint(urb->pipe) + && ((token & QTD_STS_MMF) != 0 || QTD_CERR(token) == 0) + && (!ehci_is_TDI(ehci) + || urb->dev->tt->hub != + ehci_to_hcd(ehci)->self.root_hub)) { +#ifdef DEBUG + struct usb_device *tt = urb->dev->tt->hub; + dev_dbg(&tt->dev, + "clear tt buffer port %d, a%d ep%d t%08x\n", + urb->dev->ttport, urb->dev->devnum, + usb_pipeendpoint(urb->pipe), token); +#endif /* DEBUG */ + /* REVISIT ARC-derived cores don't clear the root + * hub TT buffer in this way... + */ + usb_hub_tt_clear_buffer(urb->dev, urb->pipe); + } + } + + return status; +} + +static void +ehci_urb_done(struct ehci_hcd *ehci, struct urb *urb, int status) +__releases(ehci->lock) __acquires(ehci->lock) +{ + if (likely(urb->hcpriv != NULL)) { + struct ehci_qh *qh = (struct ehci_qh *)urb->hcpriv; + + /* S-mask in a QH means it's an interrupt urb */ + if ((qh->hw_info2 & cpu_to_hc32(ehci, QH_SMASK)) != 0) { + + /* ... update hc-wide periodic stats (for usbfs) */ + ehci_to_hcd(ehci)->self.bandwidth_int_reqs--; + } + qh_put(qh); + } + + if (unlikely(urb->unlinked)) { + COUNT(ehci->stats.unlink); + } else { + /* report non-error and short read status as zero */ + if (status == -EINPROGRESS || status == -EREMOTEIO) + status = 0; + COUNT(ehci->stats.complete); + } + +#ifdef EHCI_URB_TRACE + ehci_dbg(ehci, + "%s %s urb %p ep%d%s status %d len %d/%d\n", + __func__, urb->dev->devpath, urb, + usb_pipeendpoint(urb->pipe), + usb_pipein(urb->pipe) ? "in" : "out", + status, urb->actual_length, urb->transfer_buffer_length); +#endif + + /* complete() can reenter this HCD */ + usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); + spin_unlock(&ehci->lock); + usb_hcd_giveback_urb(ehci_to_hcd(ehci), urb, status); + spin_lock(&ehci->lock); +} + +static void start_unlink_async(struct ehci_hcd *ehci, struct ehci_qh *qh); +static void unlink_async(struct ehci_hcd *ehci, struct ehci_qh *qh); + +static void intr_deschedule(struct ehci_hcd *ehci, struct ehci_qh *qh); +static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh); + +/* + * Process and free completed qtds for a qh, returning URBs to drivers. + * Chases up to qh->hw_current. Returns number of completions called, + * indicating how much "real" work we did. + */ +static unsigned qh_completions(struct ehci_hcd *ehci, struct ehci_qh *qh) +{ + struct ehci_qtd *last = NULL, *end = qh->dummy; + struct list_head *entry, *tmp; + int last_status = -EINPROGRESS; + int stopped; + unsigned count = 0; + u8 state; + __le32 halt = HALT_BIT(ehci); + __hc32 temp_hw_qtd_next = 0; + + if (unlikely(list_empty(&qh->qtd_list))) + return count; + + /* completions (or tasks on other cpus) must never clobber HALT + * till we've gone through and cleaned everything up, even when + * they add urbs to this qh's queue or mark them for unlinking. + * + * NOTE: unlinking expects to be done in queue order. + */ + state = qh->qh_state; + qh->qh_state = QH_STATE_COMPLETING; + stopped = (state == QH_STATE_IDLE); + + /* remove de-activated QTDs from front of queue. + * after faults (including short reads), cleanup this urb + * then let the queue advance. + * if queue is stopped, handles unlinks. + */ + list_for_each_safe(entry, tmp, &qh->qtd_list) { + struct ehci_qtd *qtd; + struct urb *urb; + struct ehci_qtd *qtd2; + struct urb *urb2; + + u32 token = 0; + + qtd = list_entry(entry, struct ehci_qtd, qtd_list); + urb = qtd->urb; + + /* clean up any state from previous QTD ... */ + if (last) { + if (likely(last->urb != urb)) { + ehci_urb_done(ehci, last->urb, last_status); + count++; + last_status = -EINPROGRESS; + } + ehci_qtd_free(ehci, last); + last = NULL; + } + + /* ignore urbs submitted during completions we reported */ + if (qtd == end) + break; + + /* hardware copies qtd out of qh overlay */ + rmb(); + token = hc32_to_cpu(ehci, qtd->hw_token); + + /* always clean up qtds the hc de-activated */ + if ((token & QTD_STS_ACTIVE) == 0) { + + /* on STALL, error, and short reads this urb must + * complete and all its qtds must be recycled. + */ + if ((token & QTD_STS_HALT) != 0) { + stopped = 1; + + /* magic dummy for some short reads; qh won't advance. + * that silicon quirk can kick in with this dummy too. + * + * other short reads won't stop the queue, including + * control transfers (status stage handles that) or + * most other single-qtd reads ... the queue stops if + * URB_SHORT_NOT_OK was set so the driver submitting + * the urbs could clean it up. + */ + } else if (IS_SHORT_READ(token) + && !(qtd->hw_alt_next & EHCI_LIST_END(ehci))) { + if (urb->use_iram && usb_pipein(urb->pipe)) { + if (urb->transfer_buffer == NULL) { + memcpy(phys_to_virt + (urb->transfer_dma) + + qtd->buffer_offset, + ehci-> + iram_buffer_v + [address_to_buffer + (ehci, + usb_pipedevice(urb-> + pipe))] + + g_iram_size, + min(g_iram_size, + qtd->length)); + } else { + memcpy(urb->transfer_buffer + + qtd->buffer_offset, + ehci-> + iram_buffer_v + [address_to_buffer + (ehci, + usb_pipedevice(urb-> + pipe))] + + g_iram_size, + min(g_iram_size, + qtd->length)); + } + } + stopped = 1; + goto halt; + } else if (urb->use_iram && (!qtd->last_one) + && usb_pipeout(urb->pipe)) { + ehci-> + iram_in_use[address_to_buffer + (ehci, + usb_pipedevice(urb->pipe))] = + 1; + qtd2 = + list_entry(tmp, struct ehci_qtd, qtd_list); + if (urb->transfer_buffer == NULL) { + memcpy(ehci-> + iram_buffer_v[address_to_buffer + (ehci, + usb_pipedevice + (urb->pipe))], + phys_to_virt(urb->transfer_dma) + + qtd->buffer_offset + qtd->length, + min(g_iram_size, qtd2->length)); + } else { + memcpy(ehci-> + iram_buffer_v[address_to_buffer + (ehci, + usb_pipedevice + (urb->pipe))], + urb->transfer_buffer + + qtd->buffer_offset + qtd->length, + min(g_iram_size, qtd2->length)); + } + temp_hw_qtd_next = + QTD_NEXT(ehci, qtd->hw_next) & 0xFFFFFFFE; + } else if (urb->use_iram && (qtd->last_one) + && usb_pipeout(urb->pipe)) { + urb->use_iram = 0; + qtd2 = + list_entry(tmp, struct ehci_qtd, qtd_list); + if (tmp != &qh->qtd_list) { + urb2 = qtd2->urb; + if (urb2 && urb2->use_iram == 1) { + ehci-> + iram_in_use + [address_to_buffer + (ehci, + usb_pipedevice(urb-> + pipe))] = + 1; + if (urb2->transfer_buffer == + NULL) { + memcpy(ehci-> + iram_buffer_v + [address_to_buffer + (ehci, + usb_pipedevice + (urb->pipe))], + phys_to_virt + (urb2-> + transfer_dma), + min(g_iram_size, + qtd2-> + length)); + } else { + memcpy(ehci-> + iram_buffer_v + [address_to_buffer + (ehci, + usb_pipedevice + (urb->pipe))], + urb2-> + transfer_buffer, + min(g_iram_size, + qtd2-> + length)); + } + } else { + ehci-> + iram_in_use + [address_to_buffer + (ehci, + usb_pipedevice(urb-> + pipe))] = + 0; + } + } else { + ehci-> + iram_in_use[address_to_buffer + (ehci, + usb_pipedevice(urb-> + pipe))] + = 0; + } + temp_hw_qtd_next = + QTD_NEXT(ehci, qtd->hw_next) & 0xFFFFFFFE; + } else if (urb->use_iram && usb_pipein(urb->pipe)) { + if (urb->transfer_buffer == NULL) { + memcpy(phys_to_virt(urb->transfer_dma) + + qtd->buffer_offset, + ehci-> + iram_buffer_v[address_to_buffer + (ehci, + usb_pipedevice + (urb->pipe))] + + g_iram_size, min(g_iram_size, + qtd->length)); + } else { + memcpy(urb->transfer_buffer + + qtd->buffer_offset, + ehci-> + iram_buffer_v[address_to_buffer + (ehci, + usb_pipedevice + (urb->pipe))] + + g_iram_size, min(g_iram_size, + qtd->length)); + } + temp_hw_qtd_next = + QTD_NEXT(ehci, qtd->hw_next) & 0xFFFFFFFE; + } + /* stop scanning when we reach qtds the hc is using */ + } else if (likely(!stopped + && HC_IS_RUNNING(ehci_to_hcd(ehci)->state))) { + break; + + /* scan the whole queue for unlinks whenever it stops */ + } else { + stopped = 1; + + /* cancel everything if we halt, suspend, etc */ + if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) + last_status = -ESHUTDOWN; + + /* this qtd is active; skip it unless a previous qtd + * for its urb faulted, or its urb was canceled. + */ + else if (last_status == -EINPROGRESS && !urb->unlinked) + continue; + + /* qh unlinked; token in overlay may be most current */ + if (state == QH_STATE_IDLE + && cpu_to_hc32(ehci, qtd->qtd_dma) + == qh->hw_current) + token = hc32_to_cpu(ehci, qh->hw_token); + + /* qh unlinked; token in overlay may be most current */ + if (state == QH_STATE_IDLE + && cpu_to_hc32(ehci, qtd->qtd_dma) + == qh->hw_current) + token = hc32_to_cpu(ehci, qh->hw_token); + + /* force halt for unlinked or blocked qh, so we'll + * patch the qh later and so that completions can't + * activate it while we "know" it's stopped. + */ + if ((halt & qh->hw_token) == 0) { +halt: + qh->hw_token |= halt; + wmb(); + } + } + + /* unless we already know the urb's status, collect qtd status + * and update count of bytes transferred. in common short read + * cases with only one data qtd (including control transfers), + * queue processing won't halt. but with two or more qtds (for + * example, with a 32 KB transfer), when the first qtd gets a + * short read the second must be removed by hand. + */ + if (last_status == -EINPROGRESS) { + last_status = qtd_copy_status(ehci, urb, + qtd->length, token); + if (last_status == -EREMOTEIO + && (qtd->hw_alt_next + & EHCI_LIST_END(ehci))) + last_status = -EINPROGRESS; + } + + /* if we're removing something not at the queue head, + * patch the hardware queue pointer. + */ + + if (stopped && qtd->qtd_list.prev != &qh->qtd_list) { + last = list_entry(qtd->qtd_list.prev, + struct ehci_qtd, qtd_list); + last->hw_next = qtd->hw_next; + } + +/* remove qtd; it's recycled after possible urb completion */ + list_del(&qtd->qtd_list); + last = qtd; + } + + /* last urb's completion might still need calling */ + if (likely(last != NULL)) { + ehci_urb_done(ehci, last->urb, last_status); + count++; + ehci_qtd_free(ehci, last); + } + + /* restore original state; caller must unlink or relink */ + qh->qh_state = state; + + /* be sure the hardware's done with the qh before refreshing + * it after fault cleanup, or recovering from silicon wrongly + * overlaying the dummy qtd (which reduces DMA chatter). + */ + if ((stopped != 0) || (qh->hw_qtd_next == EHCI_LIST_END(ehci)) + && (temp_hw_qtd_next == 0)) { + switch (state) { + case QH_STATE_IDLE: + qh_refresh(ehci, qh); + break; + case QH_STATE_LINKED: + /* We won't refresh a QH that's linked (after the HC + * stopped the queue). That avoids a race: + * - HC reads first part of QH; + * - CPU updates that first part and the token; + * - HC reads rest of that QH, including token + * Result: HC gets an inconsistent image, and then + * DMAs to/from the wrong memory (corrupting it). + * + * That should be rare for interrupt transfers, + * except maybe high bandwidth ... + */ + if ((cpu_to_hc32(ehci, QH_SMASK) + & qh->hw_info2) != 0) { + intr_deschedule(ehci, qh); + (void)qh_schedule(ehci, qh); + } else + unlink_async(ehci, qh); + break; + /* otherwise, unlink already started */ + } + } + if (temp_hw_qtd_next) + qh->hw_qtd_next = temp_hw_qtd_next; + + return count; +} + +/*-------------------------------------------------------------------------*/ + +/* high bandwidth multiplier, as encoded in highspeed endpoint descriptors */ +#define hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03)) +/* ... and packet size, for any kind of endpoint descriptor */ +#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) + +/* + * reverse of qh_urb_transaction: free a list of TDs. + * used for cleanup after errors, before HC sees an URB's TDs. + */ +static void qtd_list_free(struct ehci_hcd *ehci, + struct urb *urb, struct list_head *qtd_list) +{ + struct list_head *entry, *temp; + + list_for_each_safe(entry, temp, qtd_list) { + struct ehci_qtd *qtd; + + qtd = list_entry(entry, struct ehci_qtd, qtd_list); + list_del(&qtd->qtd_list); + ehci_qtd_free(ehci, qtd); + } +} + +/* + * create a list of filled qtds for this URB; won't link into qh. + */ +static struct list_head *qh_urb_transaction(struct ehci_hcd *ehci, + struct urb *urb, + struct list_head *head, gfp_t flags) +{ + struct ehci_qtd *qtd, *qtd_prev; + dma_addr_t buf; + int len, maxpacket; + int is_input; + u32 token; + + /* + * URBs map to sequences of QTDs: one logical transaction + */ + qtd = ehci_qtd_alloc(ehci, flags); + if (unlikely(!qtd)) + return NULL; + list_add_tail(&qtd->qtd_list, head); + qtd->urb = urb; + + token = QTD_STS_ACTIVE; + token |= (EHCI_TUNE_CERR << 10); + /* for split transactions, SplitXState initialized to zero */ + + len = urb->transfer_buffer_length; + is_input = usb_pipein(urb->pipe); + if (usb_pipecontrol(urb->pipe)) { + /* SETUP pid */ + qtd_fill(ehci, qtd, urb->setup_dma, + sizeof(struct usb_ctrlrequest), + token | (2 /* "setup" */ << 8), 8); + + /* ... and always at least one more pid */ + token ^= QTD_TOGGLE; + qtd_prev = qtd; + qtd = ehci_qtd_alloc(ehci, flags); + if (unlikely(!qtd)) + goto cleanup; + qtd->urb = urb; + qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma); + list_add_tail(&qtd->qtd_list, head); + + /* for zero length DATA stages, STATUS is always IN */ + if (len == 0) + token |= (1 /* "in" */ << 8); + } + + /* + * data transfer stage: buffer setup + */ + buf = urb->transfer_dma; + + if (is_input) + token |= (1 /* "in" */ << 8); + /* else it's already initted to "out" pid (0 << 8) */ + + maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input)); + + /* + * buffer gets wrapped in one or more qtds; + * last one may be "short" (including zero len) + * and may serve as a control status ack + */ + for (;;) { + int this_qtd_len; + this_qtd_len = qtd_fill(ehci, qtd, buf, len, token, maxpacket); + if (urb->use_iram && (!qtd->buffer_offset) + && usb_pipeout(urb->pipe) + && (ehci-> + iram_in_use[address_to_buffer + (ehci, usb_pipedevice(urb->pipe))] == 0)) { + ehci-> + iram_in_use[address_to_buffer + (ehci, usb_pipedevice(urb->pipe))] = 1; + if (urb->transfer_buffer == NULL) { + memcpy(ehci-> + iram_buffer_v[address_to_buffer + (ehci, + usb_pipedevice(urb-> + pipe))], + phys_to_virt(urb->transfer_dma), + min((int)g_iram_size, len)); + } else { + memcpy(ehci-> + iram_buffer_v[address_to_buffer + (ehci, + usb_pipedevice(urb-> + pipe))], + urb->transfer_buffer, + min((int)g_iram_size, len)); + } + } + len -= this_qtd_len; + buf += this_qtd_len; + + /* + * short reads advance to a "magic" dummy instead of the next + * qtd ... that forces the queue to stop, for manual cleanup. + * (this will usually be overridden later.) + */ + if (is_input) + qtd->hw_alt_next = ehci->async->hw_alt_next; + + /* qh makes control packets use qtd toggle; maybe switch it */ + if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0) + token ^= QTD_TOGGLE; + + if (likely(len <= 0)) { + qtd->last_one = 1; + break; + } + qtd_prev = qtd; + qtd = ehci_qtd_alloc(ehci, flags); + if (unlikely(!qtd)) + goto cleanup; + qtd->urb = urb; + if (urb->use_iram) + qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma) | 0x1; + else + qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma); + + list_add_tail(&qtd->qtd_list, head); + } + + /* + * unless the caller requires manual cleanup after short reads, + * have the alt_next mechanism keep the queue running after the + * last data qtd (the only one, for control and most other cases). + */ + if (likely((urb->transfer_flags & URB_SHORT_NOT_OK) == 0 + || usb_pipecontrol(urb->pipe))) + qtd->hw_alt_next = EHCI_LIST_END(ehci); + + /* + * control requests may need a terminating data "status" ack; + * bulk ones may need a terminating short packet (zero length). + */ + if (likely(urb->transfer_buffer_length != 0)) { + int one_more = 0; + + if (usb_pipecontrol(urb->pipe)) { + one_more = 1; + token ^= 0x0100; /* "in" <--> "out" */ + token |= QTD_TOGGLE; /* force DATA1 */ + } else if (usb_pipebulk(urb->pipe) + && (urb->transfer_flags & URB_ZERO_PACKET) + && !(urb->transfer_buffer_length % maxpacket)) + one_more = 1; + if (one_more) { + qtd_prev = qtd; + qtd = ehci_qtd_alloc(ehci, flags); + if (unlikely(!qtd)) + goto cleanup; + qtd->urb = urb; + qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma); + list_add_tail(&qtd->qtd_list, head); + + /* never any data in such packets */ + qtd_fill(ehci, qtd, 0, 0, token, 0); + } + } + + /* by default, enable interrupt on urb completion */ + if (likely(!(urb->transfer_flags & URB_NO_INTERRUPT))) + qtd->hw_token |= cpu_to_hc32(ehci, QTD_IOC); + return head; + +cleanup: + qtd_list_free(ehci, urb, head); + return NULL; +} + +/*-------------------------------------------------------------------------*/ + +/* Would be best to create all qh's from config descriptors, + * when each interface/altsetting is established. Unlink + * any previous qh and cancel its urbs first; endpoints are + * implicitly reset then (data toggle too). + * That'd mean updating how usbcore talks to HCDs. (2.7?) + */ + +/* + * Each QH holds a qtd list; a QH is used for everything except iso. + * + * For interrupt urbs, the scheduler must set the microframe scheduling + * mask(s) each time the QH gets scheduled. For highspeed, that's + * just one microframe in the s-mask. For split interrupt transactions + * there are additional complications: c-mask, maybe FSTNs. + */ +static struct ehci_qh *qh_make(struct ehci_hcd *ehci, + struct urb *urb, gfp_t flags) +{ + struct ehci_qh *qh = ehci_qh_alloc(ehci, flags); + u32 info1 = 0, info2 = 0; + int is_input, type; + int maxp = 0; + struct usb_tt *tt = urb->dev->tt; + + if (!qh) + return qh; + + /* + * init endpoint/device data for this QH + */ + info1 |= usb_pipeendpoint(urb->pipe) << 8; + info1 |= usb_pipedevice(urb->pipe) << 0; + + is_input = usb_pipein(urb->pipe); + type = usb_pipetype(urb->pipe); + maxp = usb_maxpacket(urb->dev, urb->pipe, !is_input); + + /* 1024 byte maxpacket is a hardware ceiling. High bandwidth + * acts like up to 3KB, but is built from smaller packets. + */ + if (max_packet(maxp) > 1024) { + ehci_dbg(ehci, "bogus qh maxpacket %d\n", max_packet(maxp)); + goto done; + } + + /* Compute interrupt scheduling parameters just once, and save. + * - allowing for high bandwidth, how many nsec/uframe are used? + * - split transactions need a second CSPLIT uframe; same question + * - splits also need a schedule gap (for full/low speed I/O) + * - qh has a polling interval + * + * For control/bulk requests, the HC or TT handles these. + */ + if (type == PIPE_INTERRUPT) { + qh->usecs = + NS_TO_US(usb_calc_bus_time + (USB_SPEED_HIGH, is_input, 0, + hb_mult(maxp) * max_packet(maxp))); + qh->start = NO_FRAME; + + if (urb->dev->speed == USB_SPEED_HIGH) { + qh->c_usecs = 0; + qh->gap_uf = 0; + + qh->period = urb->interval >> 3; + if (qh->period == 0 && urb->interval != 1) { + /* NOTE interval 2 or 4 uframes could work. + * But interval 1 scheduling is simpler, and + * includes high bandwidth. + */ + dbg("intr period %d uframes, NYET!", + urb->interval); + goto done; + } + } else { + int think_time; + + /* gap is f(FS/LS transfer times) */ + qh->gap_uf = 1 + usb_calc_bus_time(urb->dev->speed, + is_input, 0, + maxp) / (125 * 1000); + + /* FIXME this just approximates SPLIT/CSPLIT times */ + if (is_input) { + qh->c_usecs = qh->usecs + HS_USECS(0); + qh->usecs = HS_USECS(1); + } else { + qh->usecs += HS_USECS(1); + qh->c_usecs = HS_USECS(0); + } + + think_time = tt ? tt->think_time : 0; + qh->tt_usecs = NS_TO_US(think_time + + usb_calc_bus_time(urb->dev-> + speed, + is_input, 0, + max_packet + (maxp))); + qh->period = urb->interval; + } + } + + /* support for tt scheduling, and access to toggles */ + qh->dev = urb->dev; + + /* using TT? */ + switch (urb->dev->speed) { + case USB_SPEED_LOW: + info1 |= (1 << 12); /* EPS "low" */ + /* FALL THROUGH */ + + case USB_SPEED_FULL: + /* EPS 0 means "full" */ + if (type != PIPE_INTERRUPT) + info1 |= (EHCI_TUNE_RL_TT << 28); + if (type == PIPE_CONTROL) { + info1 |= (1 << 27); /* for TT */ + info1 |= 1 << 14; /* toggle from qtd */ + } + info1 |= maxp << 16; + + info2 |= (EHCI_TUNE_MULT_TT << 30); + + /* Some Freescale processors have an erratum in which the + * port number in the queue head was 0..N-1 instead of 1..N. + */ + if (ehci_has_fsl_portno_bug(ehci)) + info2 |= (urb->dev->ttport - 1) << 23; + else + info2 |= urb->dev->ttport << 23; + + /* set the address of the TT; for TDI's integrated + * root hub tt, leave it zeroed. + */ + if (tt && tt->hub != ehci_to_hcd(ehci)->self.root_hub) + info2 |= tt->hub->devnum << 16; + + /* NOTE: if (PIPE_INTERRUPT) { scheduler sets c-mask } */ + + break; + + case USB_SPEED_HIGH: /* no TT involved */ + info1 |= (2 << 12); /* EPS "high" */ + if (type == PIPE_CONTROL) { + info1 |= (EHCI_TUNE_RL_HS << 28); + info1 |= 64 << 16; /* usb2 fixed maxpacket */ + info1 |= 1 << 14; /* toggle from qtd */ + info2 |= (EHCI_TUNE_MULT_HS << 30); + } else if (type == PIPE_BULK) { + info1 |= (EHCI_TUNE_RL_HS << 28); + /* The USB spec says that high speed bulk endpoints + * always use 512 byte maxpacket. But some device + * vendors decided to ignore that, and MSFT is happy + * to help them do so. So now people expect to use + * such nonconformant devices with Linux too; sigh. + */ + info1 |= max_packet(maxp) << 16; + info2 |= (EHCI_TUNE_MULT_HS << 30); + use_buffer(ehci, usb_pipedevice(urb->pipe)); + } else { /* PIPE_INTERRUPT */ + info1 |= max_packet(maxp) << 16; + info2 |= hb_mult(maxp) << 30; + } + break; + default: + dbg("bogus dev %p speed %d", urb->dev, urb->dev->speed); +done: + qh_put(qh); + return NULL; + } + + /* NOTE: if (PIPE_INTERRUPT) { scheduler sets s-mask } */ + + /* init as live, toggle clear, advance to dummy */ + qh->qh_state = QH_STATE_IDLE; + qh->hw_info1 = cpu_to_hc32(ehci, info1); + qh->hw_info2 = cpu_to_hc32(ehci, info2); + usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, 1); + qh_refresh(ehci, qh); + return qh; +} + +/*-------------------------------------------------------------------------*/ + +/* move qh (and its qtds) onto async queue; maybe enable queue. */ + +static void qh_link_async(struct ehci_hcd *ehci, struct ehci_qh *qh) +{ + __hc32 dma = QH_NEXT(ehci, qh->qh_dma); + struct ehci_qh *head; + + /* (re)start the async schedule? */ + head = ehci->async; + timer_action_done(ehci, TIMER_ASYNC_OFF); + if (!head->qh_next.qh) { + u32 cmd = ehci_readl(ehci, &ehci->regs->command); + + if (!(cmd & CMD_ASE)) { + /* in case a clear of CMD_ASE didn't take yet */ + (void)handshake(ehci, &ehci->regs->status, + STS_ASS, 0, 150); + cmd |= CMD_ASE | CMD_RUN; + ehci_writel(ehci, cmd, &ehci->regs->command); + ehci_to_hcd(ehci)->state = HC_STATE_RUNNING; + /* posted write need not be known to HC yet ... */ + } + } + + /* clear halt and/or toggle; and maybe recover from silicon quirk */ + if (qh->qh_state == QH_STATE_IDLE) + qh_refresh(ehci, qh); + + /* splice right after start */ + qh->qh_next = head->qh_next; + qh->hw_next = head->hw_next; + wmb(); + + head->qh_next.qh = qh; + head->hw_next = dma; + + qh->qh_state = QH_STATE_LINKED; + /* qtd completions reported later by interrupt */ +} + +/*-------------------------------------------------------------------------*/ + +/* + * For control/bulk/interrupt, return QH with these TDs appended. + * Allocates and initializes the QH if necessary. + * Returns null if it can't allocate a QH it needs to. + * If the QH has TDs (urbs) already, that's great. + */ +static struct ehci_qh *qh_append_tds(struct ehci_hcd *ehci, + struct urb *urb, + struct list_head *qtd_list, + int epnum, void **ptr) +{ + struct ehci_qh *qh = NULL; + __hc32 qh_addr_mask = cpu_to_hc32(ehci, 0x7f); + + qh = (struct ehci_qh *)*ptr; + if (unlikely(qh == NULL)) { + /* can't sleep here, we have ehci->lock... */ + qh = qh_make(ehci, urb, GFP_ATOMIC); + *ptr = qh; + } + if (likely(qh != NULL)) { + struct ehci_qtd *qtd; + + if (unlikely(list_empty(qtd_list))) + qtd = NULL; + else + qtd = list_entry(qtd_list->next, struct ehci_qtd, + qtd_list); + + /* control qh may need patching ... */ + if (unlikely(epnum == 0)) { + + /* usb_reset_device() briefly reverts to address 0 */ + if (usb_pipedevice(urb->pipe) == 0) + qh->hw_info1 &= ~qh_addr_mask; + } + + /* just one way to queue requests: swap with the dummy qtd. + * only hc or qh_refresh() ever modify the overlay. + */ + if (likely(qtd != NULL)) { + struct ehci_qtd *dummy; + dma_addr_t dma; + __hc32 token; + + /* to avoid racing the HC, use the dummy td instead of + * the first td of our list (becomes new dummy). both + * tds stay deactivated until we're done, when the + * HC is allowed to fetch the old dummy (4.10.2). + */ + token = qtd->hw_token; + qtd->hw_token = HALT_BIT(ehci); + wmb(); + dummy = qh->dummy; + + dma = dummy->qtd_dma; + *dummy = *qtd; + dummy->qtd_dma = dma; + + list_del(&qtd->qtd_list); + list_add(&dummy->qtd_list, qtd_list); + __list_splice(qtd_list, qh->qtd_list.prev); + + ehci_qtd_init(ehci, qtd, qtd->qtd_dma); + qh->dummy = qtd; + + /* hc must see the new dummy at list end */ + dma = qtd->qtd_dma; + qtd = list_entry(qh->qtd_list.prev, + struct ehci_qtd, qtd_list); + if (urb->use_iram) + qtd->hw_next = QTD_NEXT(ehci, dma) | 0x1; + else + qtd->hw_next = QTD_NEXT(ehci, dma); + + /* let the hc process these next qtds */ + wmb(); + dummy->hw_token = token; + + urb->hcpriv = qh_get(qh); + } + } + return qh; +} + +/*-------------------------------------------------------------------------*/ + +static int +submit_async(struct ehci_hcd *ehci, + struct urb *urb, struct list_head *qtd_list, gfp_t mem_flags) +{ + struct ehci_qtd *qtd; + int epnum; + unsigned long flags; + struct ehci_qh *qh = NULL; + int rc; + + qtd = list_entry(qtd_list->next, struct ehci_qtd, qtd_list); + epnum = urb->ep->desc.bEndpointAddress; + +#ifdef EHCI_URB_TRACE + ehci_dbg(ehci, + "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n", + __func__, urb->dev->devpath, urb, + epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out", + urb->transfer_buffer_length, qtd, urb->ep->hcpriv); +#endif + + spin_lock_irqsave(&ehci->lock, flags); + if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE, + &ehci_to_hcd(ehci)->flags))) { + rc = -ESHUTDOWN; + goto done; + } + rc = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb); + if (unlikely(rc)) + goto done; + + qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv); + if (unlikely(qh == NULL)) { + usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); + rc = -ENOMEM; + goto done; + } + + /* Control/bulk operations through TTs don't need scheduling, + * the HC and TT handle it when the TT has a buffer ready. + */ + if (likely(qh->qh_state == QH_STATE_IDLE)) + qh_link_async(ehci, qh_get(qh)); +done: + spin_unlock_irqrestore(&ehci->lock, flags); + if (unlikely(qh == NULL)) + qtd_list_free(ehci, urb, qtd_list); + return rc; +} + +/*-------------------------------------------------------------------------*/ + +/* the async qh for the qtds being reclaimed are now unlinked from the HC */ + +static void end_unlink_async(struct ehci_hcd *ehci) +{ + struct ehci_qh *qh = ehci->reclaim; + struct ehci_qh *next; + + iaa_watchdog_done(ehci); + + qh->qh_state = QH_STATE_IDLE; + qh->qh_next.qh = NULL; + qh_put(qh); /* refcount from reclaim */ + + /* other unlink(s) may be pending (in QH_STATE_UNLINK_WAIT) */ + next = qh->reclaim; + ehci->reclaim = next; + qh->reclaim = NULL; + + qh_completions(ehci, qh); + + if (!list_empty(&qh->qtd_list) + && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) + qh_link_async(ehci, qh); + else { + qh_put(qh); /* refcount from async list */ + + /* it's not free to turn the async schedule on/off; leave it + * active but idle for a while once it empties. + */ + if (HC_IS_RUNNING(ehci_to_hcd(ehci)->state) + && ehci->async->qh_next.qh == NULL) + timer_action(ehci, TIMER_ASYNC_OFF); + } + + if (next) { + ehci->reclaim = NULL; + start_unlink_async(ehci, next); + } +} + +/* makes sure the async qh will become idle */ +/* caller must own ehci->lock */ + +static void start_unlink_async(struct ehci_hcd *ehci, struct ehci_qh *qh) +{ + int cmd = ehci_readl(ehci, &ehci->regs->command); + struct ehci_qh *prev; + +#ifdef DEBUG + assert_spin_locked(&ehci->lock); + if (ehci->reclaim + || (qh->qh_state != QH_STATE_LINKED + && qh->qh_state != QH_STATE_UNLINK_WAIT) + ) + BUG(); +#endif + + /* stop async schedule right now? */ + if (unlikely(qh == ehci->async)) { + /* can't get here without STS_ASS set */ + if (ehci_to_hcd(ehci)->state != HC_STATE_HALT && + !ehci->reclaim) { + /* ... and CMD_IAAD clear */ + ehci_writel(ehci, cmd & ~CMD_ASE, &ehci->regs->command); + wmb(); + /* handshake later, if we need to */ + timer_action_done(ehci, TIMER_ASYNC_OFF); + } + return; + } + + qh->qh_state = QH_STATE_UNLINK; + ehci->reclaim = qh = qh_get(qh); + + prev = ehci->async; + while (prev->qh_next.qh != qh) + prev = prev->qh_next.qh; + + prev->hw_next = qh->hw_next; + prev->qh_next = qh->qh_next; + wmb(); + + if (unlikely(ehci_to_hcd(ehci)->state == HC_STATE_HALT)) { + /* if (unlikely (qh->reclaim != 0)) + * this will recurse, probably not much + */ + end_unlink_async(ehci); + return; + } + + cmd |= CMD_IAAD; + ehci_writel(ehci, cmd, &ehci->regs->command); + (void)ehci_readl(ehci, &ehci->regs->command); + iaa_watchdog_start(ehci); +} + +/*-------------------------------------------------------------------------*/ + +static void scan_async(struct ehci_hcd *ehci) +{ + struct ehci_qh *qh; + enum ehci_timer_action action = TIMER_IO_WATCHDOG; + + if (!++(ehci->stamp)) + ehci->stamp++; + timer_action_done(ehci, TIMER_ASYNC_SHRINK); +rescan: + qh = ehci->async->qh_next.qh; + if (likely(qh != NULL)) { + do { + /* clean any finished work for this qh */ + if (!list_empty(&qh->qtd_list) + && qh->stamp != ehci->stamp) { + int temp; + + /* unlinks could happen here; completion + * reporting drops the lock. rescan using + * the latest schedule, but don't rescan + * qhs we already finished (no looping). + */ + qh = qh_get(qh); + qh->stamp = ehci->stamp; + temp = qh_completions(ehci, qh); + qh_put(qh); + if (temp != 0) + goto rescan; + } + + /* unlink idle entries, reducing HC PCI usage as well + * as HCD schedule-scanning costs. delay for any qh + * we just scanned, there's a not-unusual case that it + * doesn't stay idle for long. + * (plus, avoids some kind of re-activation race.) + */ + if (list_empty(&qh->qtd_list)) { + if (qh->stamp == ehci->stamp) + action = TIMER_ASYNC_SHRINK; + else if (!ehci->reclaim + && qh->qh_state == QH_STATE_LINKED) + start_unlink_async(ehci, qh); + } + + qh = qh->qh_next.qh; + } while (qh); + } + if (action == TIMER_ASYNC_SHRINK) + timer_action(ehci, TIMER_ASYNC_SHRINK); +} diff -urN linux-2.6.26/drivers/usb/host/ehci-q.c linux-2.6.26-lab126/drivers/usb/host/ehci-q.c --- linux-2.6.26/drivers/usb/host/ehci-q.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/host/ehci-q.c 2010-08-10 04:17:12.000000000 -0400 @@ -932,7 +932,7 @@ list_del (&qtd->qtd_list); list_add (&dummy->qtd_list, qtd_list); - __list_splice (qtd_list, qh->qtd_list.prev); + list_splice_tail (qtd_list, &qh->qtd_list); ehci_qtd_init(ehci, qtd, qtd->qtd_dma); qh->dummy = qtd; diff -urN linux-2.6.26/drivers/usb/host/ehci-sched.c linux-2.6.26-lab126/drivers/usb/host/ehci-sched.c --- linux-2.6.26/drivers/usb/host/ehci-sched.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/host/ehci-sched.c 2010-08-10 04:17:12.000000000 -0400 @@ -323,7 +323,7 @@ * already scheduled transactions */ if (125 < usecs) { - int ufs = (usecs / 125) - 1; + int ufs = (usecs / 125); int i; for (i = uframe; i < (uframe + ufs) && i < 8; i++) if (0 < tt_usecs[i]) { @@ -437,6 +437,9 @@ u32 cmd; int status; + if (ehci->periodic_sched++) + return 0; + /* did clearing PSE did take effect yet? * takes effect only at frame boundaries... */ @@ -461,6 +464,9 @@ u32 cmd; int status; + if (--ehci->periodic_sched) + return 0; + /* did setting PSE not take effect yet? * takes effect only at frame boundaries... */ @@ -544,13 +550,10 @@ : (qh->usecs * 8); /* maybe enable periodic schedule processing */ - if (!ehci->periodic_sched++) - return enable_periodic (ehci); - - return 0; + return enable_periodic(ehci); } -static void qh_unlink_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh) +static int qh_unlink_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh) { unsigned i; unsigned period; @@ -586,9 +589,7 @@ qh_put (qh); /* maybe turn off periodic schedule */ - ehci->periodic_sched--; - if (!ehci->periodic_sched) - (void) disable_periodic (ehci); + return disable_periodic(ehci); } static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh) @@ -759,8 +760,10 @@ if (status) { /* "normal" case, uframing flexible except with splits */ if (qh->period) { - frame = qh->period - 1; - do { + int i; + + for (i = qh->period; status && i > 0; --i) { + frame = ++ehci->random_frame % qh->period; for (uframe = 0; uframe < 8; uframe++) { status = check_intr_schedule (ehci, frame, uframe, qh, @@ -768,7 +771,7 @@ if (status == 0) break; } - } while (status && frame--); + } /* qh->period == 0 means every uframe */ } else { @@ -917,7 +920,7 @@ */ stream->usecs = HS_USECS_ISO (maxp); bandwidth = stream->usecs * 8; - bandwidth /= 1 << (interval - 1); + bandwidth /= 1 << interval; } else { u32 addr; @@ -950,7 +953,7 @@ } else stream->raw_mask = smask_out [hs_transfers - 1]; bandwidth = stream->usecs + stream->c_usecs; - bandwidth /= 1 << (interval + 2); + bandwidth /= 1 << interval << 3; /* stream->splits gets created from raw_mask later */ stream->address = cpu_to_hc32(ehci, addr); @@ -1534,7 +1537,7 @@ struct ehci_itd, itd_list); list_move_tail (&itd->itd_list, &stream->td_list); itd->stream = iso_stream_get (stream); - itd->urb = usb_get_urb (urb); + itd->urb = urb; itd_init (ehci, stream, itd); } @@ -1562,9 +1565,7 @@ urb->hcpriv = NULL; timer_action (ehci, TIMER_IO_WATCHDOG); - if (unlikely (!ehci->periodic_sched++)) - return enable_periodic (ehci); - return 0; + return enable_periodic(ehci); } #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR) @@ -1617,11 +1618,14 @@ desc->status = -EPROTO; /* HC need not update length with this error */ - if (!(t & EHCI_ISOC_BABBLE)) - desc->actual_length = EHCI_ITD_LENGTH (t); + if (!(t & EHCI_ISOC_BABBLE)) { + desc->actual_length = EHCI_ITD_LENGTH(t); + urb->actual_length += desc->actual_length; + } } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) { desc->status = 0; - desc->actual_length = EHCI_ITD_LENGTH (t); + desc->actual_length = EHCI_ITD_LENGTH(t); + urb->actual_length += desc->actual_length; } else { /* URB was too late */ desc->status = -EXDEV; @@ -1642,10 +1646,10 @@ ehci_urb_done(ehci, urb, 0); retval = true; urb = NULL; - ehci->periodic_sched--; + (void) disable_periodic(ehci); ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; - if (unlikely (list_empty (&stream->td_list))) { + if (unlikely(list_is_singular(&stream->td_list))) { ehci_to_hcd(ehci)->self.bandwidth_allocated -= stream->bandwidth; ehci_vdbg (ehci, @@ -1656,7 +1660,6 @@ iso_stream_put (ehci, stream); /* OK to recycle this ITD now that its completion callback ran. */ done: - usb_put_urb(urb); itd->urb = NULL; itd->stream = NULL; list_move(&itd->itd_list, &stream->free_list); @@ -1935,7 +1938,7 @@ struct ehci_sitd, sitd_list); list_move_tail (&sitd->sitd_list, &stream->td_list); sitd->stream = iso_stream_get (stream); - sitd->urb = usb_get_urb (urb); + sitd->urb = urb; sitd_patch(ehci, stream, sitd, sched, packet); sitd_link (ehci, (next_uframe >> 3) % ehci->periodic_size, @@ -1951,9 +1954,7 @@ urb->hcpriv = NULL; timer_action (ehci, TIMER_IO_WATCHDOG); - if (!ehci->periodic_sched++) - return enable_periodic (ehci); - return 0; + return enable_periodic(ehci); } /*-------------------------------------------------------------------------*/ @@ -2001,7 +2002,8 @@ desc->status = -EPROTO; } else { desc->status = 0; - desc->actual_length = desc->length - SITD_LENGTH (t); + desc->actual_length = desc->length - SITD_LENGTH(t); + urb->actual_length += desc->actual_length; } stream->depth -= stream->interval << 3; @@ -2019,10 +2021,10 @@ ehci_urb_done(ehci, urb, 0); retval = true; urb = NULL; - ehci->periodic_sched--; + (void) disable_periodic(ehci); ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; - if (list_empty (&stream->td_list)) { + if (list_is_singular(&stream->td_list)) { ehci_to_hcd(ehci)->self.bandwidth_allocated -= stream->bandwidth; ehci_vdbg (ehci, @@ -2033,7 +2035,6 @@ iso_stream_put (ehci, stream); /* OK to recycle this SITD now that its completion callback ran. */ done: - usb_put_urb(urb); sitd->urb = NULL; sitd->stream = NULL; list_move(&sitd->sitd_list, &stream->free_list); @@ -2243,8 +2244,7 @@ if (unlikely (modified)) { if (likely(ehci->periodic_sched > 0)) goto restart; - /* maybe we can short-circuit this scan! */ - disable_periodic(ehci); + /* short-circuit this scan */ now_uframe = clock; break; } diff -urN linux-2.6.26/drivers/usb/host/ehci.h linux-2.6.26-lab126/drivers/usb/host/ehci.h --- linux-2.6.26/drivers/usb/host/ehci.h 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/host/ehci.h 2010-08-10 04:17:12.000000000 -0400 @@ -110,6 +110,7 @@ struct timer_list watchdog; unsigned long actions; unsigned stamp; + unsigned random_frame; unsigned long next_statechange; u32 command; @@ -121,6 +122,18 @@ u8 sbrn; /* packed release number */ + /* + * OTG controllers and transceivers need software interaction; + * other external transceivers should be software-transparent + */ + struct otg_transceiver *transceiver; +#ifdef CONFIG_USB_STATIC_IRAM + u32 iram_buffer[2]; + u32 iram_buffer_v[2]; + int iram_in_use[2]; + int usb_address[2]; +#endif + /* irq statistics */ #ifdef EHCI_STATS struct ehci_stats stats; @@ -136,6 +149,8 @@ struct dentry *debug_periodic; struct dentry *debug_registers; #endif + + struct delayed_work dwork; }; /* convert between an HCD pointer and the corresponding EHCI_HCD */ @@ -289,6 +304,7 @@ /* PORTSC: offset 0x44 */ u32 port_status [0]; /* up to N_PORTS */ /* 31:23 reserved */ +#define PORT_PHCD (1<<23) /* PHY Low Power Suspend */ #define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ #define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ #define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ @@ -388,6 +404,10 @@ struct list_head qtd_list; /* sw qtd list */ struct urb *urb; /* qtd's urb */ size_t length; /* length of buffer */ +#ifdef CONFIG_USB_STATIC_IRAM + size_t buffer_offset; + int last_one; +#endif } __attribute__ ((aligned (32))); /* mask NakCnt+T in qh->hw_alt_next */ @@ -838,6 +858,10 @@ #define STUB_DEBUG_FILES #endif /* DEBUG */ +#ifdef CONFIG_USB_STATIC_IRAM +#define IRAM_TD_SIZE 1024 /* size of 1 qTD's buffer */ +#define IRAM_NTD 2 /* number of TDs in IRAM */ +#endif /*-------------------------------------------------------------------------*/ #endif /* __LINUX_EHCI_HCD_H */ diff -urN linux-2.6.26/drivers/usb/host/isp1760-hcd.c linux-2.6.26-lab126/drivers/usb/host/isp1760-hcd.c --- linux-2.6.26/drivers/usb/host/isp1760-hcd.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/host/isp1760-hcd.c 2010-08-10 04:17:12.000000000 -0400 @@ -1592,7 +1592,7 @@ struct inter_packet_info *ints; u32 i; u32 reg_base, or_reg, skip_reg; - int flags; + unsigned long flags; struct ptd ptd; switch (usb_pipetype(urb->pipe)) { @@ -2061,7 +2061,7 @@ struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); struct isp1760_qh *qh; struct isp1760_qtd *qtd; - u32 flags; + unsigned long flags; spin_lock_irqsave(&priv->lock, flags); qh = ep->hcpriv; diff -urN linux-2.6.26/drivers/usb/otg/Kconfig linux-2.6.26-lab126/drivers/usb/otg/Kconfig --- linux-2.6.26/drivers/usb/otg/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/usb/otg/Kconfig 2010-08-10 04:17:08.000000000 -0400 @@ -0,0 +1,5 @@ +config TRANSCEIVER_MXC_OTG + tristate "usb otg pin detect support" + depends on (MC13783_MXC || ISP1504_MXC) && USB_GADGET && USB_EHCI_HCD && USB_OTG + help + Support for USB OTG PIN detect on MXC platforms. diff -urN linux-2.6.26/drivers/usb/otg/Makefile linux-2.6.26-lab126/drivers/usb/otg/Makefile --- linux-2.6.26/drivers/usb/otg/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/usb/otg/Makefile 2010-08-10 04:17:08.000000000 -0400 @@ -0,0 +1,7 @@ +# +# Makefile for USB OTG controller driver +# +# USB transceiver +fsl_otg_arc-objs := fsl_otg.o otg_fsm.o +obj-$(CONFIG_ISP1504_MXC_OTG) += fsl_otg_arc.o +obj-$(CONFIG_UTMI_MXC_OTG) += fsl_otg_arc.o diff -urN linux-2.6.26/drivers/usb/otg/fsl_otg.c linux-2.6.26-lab126/drivers/usb/otg/fsl_otg.c --- linux-2.6.26/drivers/usb/otg/fsl_otg.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/usb/otg/fsl_otg.c 2010-08-10 04:17:08.000000000 -0400 @@ -0,0 +1,1200 @@ +/* + * Copyright (C) 2005-2008 Freescale semiconductor, Inc. + * + * Author: Li Yang + * Jerry Huang + * + * Initialization based on code from Shlomi Gridish. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "fsl_otg.h" + +#define CONFIG_USB_OTG_DEBUG_FILES +#define DRIVER_VERSION "$Revision: 1.55 $" +#define DRIVER_AUTHOR "Jerry Huang/Li Yang" +#define DRIVER_DESC "Freescale USB OTG Driver" +#define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC + +MODULE_DESCRIPTION("Freescale USB OTG Transceiver Driver"); + +static const char driver_name[] = "fsl-usb2-otg"; + +const pm_message_t otg_suspend_state = { + .event = 1, +}; + +#define HA_DATA_PULSE 1 + +volatile static struct usb_dr_mmap *usb_dr_regs; +static struct fsl_otg *fsl_otg_dev; +static int srp_wait_done; + +/* FSM timers */ +struct fsl_otg_timer *a_wait_vrise_tmr, *a_wait_bcon_tmr, *a_aidl_bdis_tmr, + *b_ase0_brst_tmr, *b_se0_srp_tmr; + +/* Driver specific timers */ +struct fsl_otg_timer *b_data_pulse_tmr, *b_vbus_pulse_tmr, *b_srp_fail_tmr, + *b_srp_wait_tmr, *a_wait_enum_tmr; + +static struct list_head active_timers; + +static struct fsl_otg_config fsl_otg_initdata = { + .otg_port = 1, +}; + +int write_ulpi(u8 addr, u8 data) +{ + u32 temp; + temp = 0x60000000 | (addr << 16) | data; + temp = cpu_to_le32(temp); + usb_dr_regs->ulpiview = temp; + return 0; +} + +/* prototype declaration */ +void fsl_otg_add_timer(void *timer); +void fsl_otg_del_timer(void *timer); + +/* -------------------------------------------------------------*/ +/* Operations that will be called from OTG Finite State Machine */ + +/* Charge vbus for vbus pulsing in SRP */ +void fsl_otg_chrg_vbus(int on) +{ + if (on) + usb_dr_regs->otgsc = + cpu_to_le32((le32_to_cpu(usb_dr_regs->otgsc) & + ~OTGSC_INTSTS_MASK & + ~OTGSC_CTRL_VBUS_DISCHARGE) | + OTGSC_CTRL_VBUS_CHARGE); + else + usb_dr_regs->otgsc = + cpu_to_le32((le32_to_cpu(usb_dr_regs->otgsc) & + ~OTGSC_INTSTS_MASK & ~OTGSC_CTRL_VBUS_CHARGE)); +} + +/* Discharge vbus through a resistor to ground */ +void fsl_otg_dischrg_vbus(int on) +{ + if (on) + usb_dr_regs->otgsc = + cpu_to_le32((le32_to_cpu(usb_dr_regs->otgsc) & + ~OTGSC_INTSTS_MASK) + | OTGSC_CTRL_VBUS_DISCHARGE); + else + usb_dr_regs->otgsc = + cpu_to_le32((le32_to_cpu(usb_dr_regs->otgsc) & + ~OTGSC_INTSTS_MASK & + ~OTGSC_CTRL_VBUS_DISCHARGE)); +} + +/* A-device driver vbus, controlled through PP bit in PORTSC */ +void fsl_otg_drv_vbus(int on) +{ +/* if (on) + usb_dr_regs->portsc = + cpu_to_le32((le32_to_cpu(usb_dr_regs->portsc) & + ~PORTSC_W1C_BITS) | PORTSC_PORT_POWER); + else + usb_dr_regs->portsc = + cpu_to_le32(le32_to_cpu(usb_dr_regs->portsc) & + ~PORTSC_W1C_BITS & ~PORTSC_PORT_POWER); +*/ +} + +/* + * Pull-up D+, signalling connect by periperal. Also used in + * data-line pulsing in SRP + */ +void fsl_otg_loc_conn(int on) +{ + if (on) + usb_dr_regs->otgsc = + cpu_to_le32((le32_to_cpu(usb_dr_regs->otgsc) & + ~OTGSC_INTSTS_MASK) | OTGSC_CTRL_DATA_PULSING); + else + usb_dr_regs->otgsc = + cpu_to_le32(le32_to_cpu(usb_dr_regs->otgsc) & + ~OTGSC_INTSTS_MASK & ~OTGSC_CTRL_DATA_PULSING); +} + +/* Generate SOF by host. This is controlled through suspend/resume the + * port. In host mode, controller will automatically send SOF. + * Suspend will block the data on the port. + */ +void fsl_otg_loc_sof(int on) +{ + u32 tmpval; + + tmpval = readl(&fsl_otg_dev->dr_mem_map->portsc) & ~PORTSC_W1C_BITS; + if (on) + tmpval |= PORTSC_PORT_FORCE_RESUME; + else + tmpval |= PORTSC_PORT_SUSPEND; + writel(tmpval, &fsl_otg_dev->dr_mem_map->portsc); + +} + +/* Start SRP pulsing by data-line pulsing, followed with v-bus pulsing. */ +void fsl_otg_start_pulse(void) +{ + srp_wait_done = 0; +#ifdef HA_DATA_PULSE + usb_dr_regs->otgsc = + cpu_to_le32((le32_to_cpu(usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK) + | OTGSC_HA_DATA_PULSE); +#else + fsl_otg_loc_conn(1); +#endif + + fsl_otg_add_timer(b_data_pulse_tmr); +} + +void fsl_otg_pulse_vbus(void); + +void b_data_pulse_end(unsigned long foo) +{ +#ifdef HA_DATA_PULSE +#else + fsl_otg_loc_conn(0); +#endif + + /* Do VBUS pulse after data pulse */ + fsl_otg_pulse_vbus(); +} + +void fsl_otg_pulse_vbus(void) +{ + srp_wait_done = 0; + fsl_otg_chrg_vbus(1); + /* start the timer to end vbus charge */ + fsl_otg_add_timer(b_vbus_pulse_tmr); +} + +void b_vbus_pulse_end(unsigned long foo) +{ + fsl_otg_chrg_vbus(0); + + /* As USB3300 using the same a_sess_vld and b_sess_vld voltage + * we need to discharge the bus for a while to distinguish + * residual voltage of vbus pulsing and A device pull up */ + fsl_otg_dischrg_vbus(1); + fsl_otg_add_timer(b_srp_wait_tmr); +} + +void b_srp_end(unsigned long foo) +{ + fsl_otg_dischrg_vbus(0); + srp_wait_done = 1; + + if ((fsl_otg_dev->otg.state == OTG_STATE_B_SRP_INIT) && + fsl_otg_dev->fsm.b_sess_vld) + fsl_otg_dev->fsm.b_srp_done = 1; +} + +/* Workaround for a_host suspending too fast. When a_bus_req=0, + * a_host will start by SRP. It needs to set b_hnp_enable before + * actually suspending to start HNP + */ +void a_wait_enum(unsigned long foo) +{ + VDBG("a_wait_enum timeout\n"); + if (!fsl_otg_dev->otg.host->b_hnp_enable) + fsl_otg_add_timer(a_wait_enum_tmr); + else + otg_statemachine(&fsl_otg_dev->fsm); +} + +/* ------------------------------------------------------*/ + +/* The timeout callback function to set time out bit */ +void set_tmout(unsigned long indicator) +{ + *(int *)indicator = 1; +} + +/* Initialize timers */ +int fsl_otg_init_timers(struct otg_fsm *fsm) +{ + /* FSM used timers */ + a_wait_vrise_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_VRISE, + (unsigned long)&fsm->a_wait_vrise_tmout); + if (a_wait_vrise_tmr == NULL) + return -ENOMEM; + + a_wait_bcon_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_BCON, + (unsigned long)&fsm->a_wait_bcon_tmout); + if (a_wait_bcon_tmr == NULL) + return -ENOMEM; + + a_aidl_bdis_tmr = otg_timer_initializer(&set_tmout, TA_AIDL_BDIS, + (unsigned long)&fsm->a_aidl_bdis_tmout); + if (a_aidl_bdis_tmr == NULL) + return -ENOMEM; + + b_ase0_brst_tmr = otg_timer_initializer(&set_tmout, TB_ASE0_BRST, + (unsigned long)&fsm->b_ase0_brst_tmout); + if (b_ase0_brst_tmr == NULL) + return -ENOMEM; + + b_se0_srp_tmr = otg_timer_initializer(&set_tmout, TB_SE0_SRP, + (unsigned long)&fsm->b_se0_srp); + if (b_se0_srp_tmr == NULL) + return -ENOMEM; + + b_srp_fail_tmr = otg_timer_initializer(&set_tmout, TB_SRP_FAIL, + (unsigned long)&fsm->b_srp_done); + if (b_srp_fail_tmr == NULL) + return -ENOMEM; + + a_wait_enum_tmr = otg_timer_initializer(&a_wait_enum, 10, + (unsigned long)&fsm); + if (a_wait_enum_tmr == NULL) + return -ENOMEM; + + /* device driver used timers */ + b_srp_wait_tmr = otg_timer_initializer(&b_srp_end, TB_SRP_WAIT, 0); + if (b_srp_wait_tmr == NULL) + return -ENOMEM; + + b_data_pulse_tmr = otg_timer_initializer(&b_data_pulse_end, + TB_DATA_PLS, 0); + if (b_data_pulse_tmr == NULL) + return -ENOMEM; + + b_vbus_pulse_tmr = otg_timer_initializer(&b_vbus_pulse_end, + TB_VBUS_PLS, 0); + if (b_vbus_pulse_tmr == NULL) + return -ENOMEM; + + return 0; +} + +/* Uninitialize timers */ +void fsl_otg_uninit_timers(void) +{ + /* FSM used timers */ + if (a_wait_vrise_tmr != NULL) + kfree(a_wait_vrise_tmr); + if (a_wait_bcon_tmr != NULL) + kfree(a_wait_bcon_tmr); + if (a_aidl_bdis_tmr != NULL) + kfree(a_aidl_bdis_tmr); + if (b_ase0_brst_tmr != NULL) + kfree(b_ase0_brst_tmr); + if (b_se0_srp_tmr != NULL) + kfree(b_se0_srp_tmr); + if (b_srp_fail_tmr != NULL) + kfree(b_srp_fail_tmr); + if (a_wait_enum_tmr != NULL) + kfree(a_wait_enum_tmr); + + /* device driver used timers */ + if (b_srp_wait_tmr != NULL) + kfree(b_srp_wait_tmr); + if (b_data_pulse_tmr != NULL) + kfree(b_data_pulse_tmr); + if (b_vbus_pulse_tmr != NULL) + kfree(b_vbus_pulse_tmr); +} + +/* Add timer to timer list */ +void fsl_otg_add_timer(void *gtimer) +{ + struct fsl_otg_timer *timer = (struct fsl_otg_timer *)gtimer; + struct fsl_otg_timer *tmp_timer; + + /* Check if the timer is already in the active list, + * if so update timer count + */ + list_for_each_entry(tmp_timer, &active_timers, list) + if (tmp_timer == timer) { + timer->count = timer->expires; + return; + } + timer->count = timer->expires; + list_add_tail(&timer->list, &active_timers); +} + +/* Remove timer from the timer list; clear timeout status */ +void fsl_otg_del_timer(void *gtimer) +{ + struct fsl_otg_timer *timer = (struct fsl_otg_timer *)gtimer; + struct fsl_otg_timer *tmp_timer, *del_tmp; + + list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) + if (tmp_timer == timer) + list_del(&timer->list); +} + +/* Reduce timer count by 1, and find timeout conditions. + * Called by fsl_otg 1ms timer interrupt + */ +int fsl_otg_tick_timer(void) +{ + struct fsl_otg_timer *tmp_timer, *del_tmp; + int expired = 0; + + list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) { + tmp_timer->count--; + /* check if timer expires */ + if (!tmp_timer->count) { + list_del(&tmp_timer->list); + tmp_timer->function(tmp_timer->data); + expired = 1; + } + } + + return expired; +} + +/* Reset controller, not reset the bus */ +void otg_reset_controller(void) +{ + u32 command; + + command = readl(&usb_dr_regs->usbcmd); + command |= (1 << 1); + writel(command, &usb_dr_regs->usbcmd); + while (readl(&usb_dr_regs->usbcmd) & (1 << 1)) ; +} + +/* Call suspend/resume routines in host driver */ +int fsl_otg_start_host(struct otg_fsm *fsm, int on) +{ + struct otg_transceiver *xceiv = fsm->transceiver; + struct device *dev; + struct fsl_otg *otg_dev = container_of(xceiv, struct fsl_otg, otg); + u32 retval = 0; + + if (!xceiv->host) + return -ENODEV; + dev = xceiv->host->controller; + + /* Update a_vbus_vld state as a_vbus_vld int is disabled + * in device mode + */ + fsm->a_vbus_vld = + (le32_to_cpu(usb_dr_regs->otgsc) & OTGSC_STS_A_VBUS_VALID) ? 1 : 0; + if (on) { + /* start fsl usb host controller */ + if (otg_dev->host_working) + goto end; + else { + otg_reset_controller(); + VDBG("host on......\n"); + if (dev->driver->resume) { + retval = dev->driver->resume(dev); + if (fsm->id) { + /* default-b */ + fsl_otg_drv_vbus(1); + /* Workaround: b_host can't driver + * vbus, but PP in PORTSC needs to + * be 1 for host to work. + * So we set drv_vbus bit in + * transceiver to 0 thru ULPI. */ +#if defined(CONFIG_ISP1504_MXC) + write_ulpi(0x0c, 0x20); +#endif + } + } + + otg_dev->host_working = 1; + } + } else { + /* stop fsl usb host controller */ + if (!otg_dev->host_working) + goto end; + else { + VDBG("host off......\n"); + if (dev && dev->driver) { + retval = dev->driver->suspend(dev, + otg_suspend_state); + if (fsm->id) + /* default-b */ + fsl_otg_drv_vbus(0); + } + otg_dev->host_working = 0; + } + } +end: + return retval; +} + +/* Call suspend and resume function in udc driver + * to stop and start udc driver. + */ +int fsl_otg_start_gadget(struct otg_fsm *fsm, int on) +{ + struct otg_transceiver *xceiv = fsm->transceiver; + struct device *dev; + + if (!xceiv->gadget || !xceiv->gadget->dev.parent) + return -ENODEV; + + VDBG("gadget %s \n", on ? "on" : "off"); + dev = xceiv->gadget->dev.parent; + + if (on) + dev->driver->resume(dev); + else + dev->driver->suspend(dev, otg_suspend_state); + + return 0; +} + +/* Called by initialization code of host driver. Register host controller + * to the OTG. Suspend host for OTG role detection. + */ +static int fsl_otg_set_host(struct otg_transceiver *otg_p, struct usb_bus *host) +{ + struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg); + + if (!otg_p || otg_dev != fsl_otg_dev) + return -ENODEV; + + otg_p->host = host; + + otg_dev->fsm.a_bus_drop = 0; + otg_dev->fsm.a_bus_req = 1; + + if (host) { + VDBG("host off......\n"); + + otg_p->host->otg_port = fsl_otg_initdata.otg_port; + otg_p->host->is_b_host = otg_dev->fsm.id; + /* must leave time for khubd to finish its thing + * before yanking the host driver out from under it, + * so suspend the host after a short delay. + */ + otg_dev->host_working = 1; + schedule_delayed_work(&otg_dev->otg_event, 100); + return 0; + } else { /* host driver going away */ + + if (!(le32_to_cpu(otg_dev->dr_mem_map->otgsc) & + OTGSC_STS_USB_ID)) { + /* Mini-A cable connected */ + struct otg_fsm *fsm = &otg_dev->fsm; + + otg_p->state = OTG_STATE_UNDEFINED; + fsm->protocol = PROTO_UNDEF; + } + } + + otg_dev->host_working = 0; + + otg_statemachine(&otg_dev->fsm); + + return 0; +} + +/* Called by initialization code of udc. Register udc to OTG.*/ +static int fsl_otg_set_peripheral(struct otg_transceiver *otg_p, + struct usb_gadget *gadget) +{ + struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg); + + VDBG("otg_dev 0x%x\n", (int)otg_dev); + VDBG("fsl_otg_dev 0x%x\n", (int)fsl_otg_dev); + + if (!otg_p || otg_dev != fsl_otg_dev) + return -ENODEV; + + if (!gadget) { + if (!otg_dev->otg.default_a) + otg_p->gadget->ops->vbus_draw(otg_p->gadget, 0); + usb_gadget_vbus_disconnect(otg_dev->otg.gadget); + otg_dev->otg.gadget = 0; + otg_dev->fsm.b_bus_req = 0; + otg_statemachine(&otg_dev->fsm); + return 0; + } +#ifdef DEBUG + /* + * debug the initial state of the ID pin when only + * the gadget driver is loaded and no cable is connected. + * sometimes, we get an ID irq right + * after the udc driver's otg_get_transceiver() call + * that indicates that IDpin=0, which means a Mini-A + * connector is attached. not good. + */ + DBG("before: fsm.id ID pin=%d", otg_dev->fsm.id); + otg_dev->fsm.id = (otg_dev->dr_mem_map->otgsc & OTGSC_STS_USB_ID) ? + 1 : 0; + DBG("after: fsm.id ID pin=%d", otg_dev->fsm.id); + /*if (!otg_dev->fsm.id) { + printk("OTG Control = 0x%x\n", + isp1504_read(ISP1504_OTGCTL, + &otg_dev->dr_mem_map->ulpiview)); + } */ +#endif + + otg_p->gadget = gadget; + otg_p->gadget->is_a_peripheral = !otg_dev->fsm.id; + + otg_dev->fsm.b_bus_req = 1; + + /* start the gadget right away if the ID pin says Mini-B */ + DBG("ID pin=%d\n", otg_dev->fsm.id); + if (otg_dev->fsm.id == 1) { + fsl_otg_start_host(&otg_dev->fsm, 0); + otg_drv_vbus(&otg_dev->fsm, 0); + fsl_otg_start_gadget(&otg_dev->fsm, 1); + } + + return 0; +} + +/* Set OTG port power, only for B-device */ +static int fsl_otg_set_power(struct otg_transceiver *otg_p, unsigned mA) +{ + if (!fsl_otg_dev) + return -ENODEV; + if (otg_p->state == OTG_STATE_B_PERIPHERAL) + printk(KERN_INFO "FSL OTG:Draw %d mA\n", mA); + + return 0; +} + +/* Delayed pin detect interrupt processing. + * + * When the Mini-A cable is disconnected from the board, + * the pin-detect interrupt happens before the disconnnect + * interrupts for the connected device(s). In order to + * process the disconnect interrupt(s) prior to switching + * roles, the pin-detect interrupts are delayed, and handled + * by this routine. + */ +static void fsl_otg_event(struct work_struct *work) +{ + struct fsl_otg *og = container_of(work, struct fsl_otg, otg_event.work); + struct otg_fsm *fsm = &og->fsm; + + if (fsm->id) { /* switch to gadget */ + fsl_otg_start_host(fsm, 0); + otg_drv_vbus(fsm, 0); + fsl_otg_start_gadget(fsm, 1); + } +} + +/* B-device start SRP */ +static int fsl_otg_start_srp(struct otg_transceiver *otg_p) +{ + struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg); + + if (!otg_p || otg_dev != fsl_otg_dev + || otg_p->state != OTG_STATE_B_IDLE) + return -ENODEV; + + otg_dev->fsm.b_bus_req = 1; + otg_statemachine(&otg_dev->fsm); + + return 0; +} + +/* A_host suspend will call this function to start hnp */ +static int fsl_otg_start_hnp(struct otg_transceiver *otg_p) +{ + struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg); + + if (!otg_p || otg_dev != fsl_otg_dev) + return -ENODEV; + + /* printk("start_hnp.............\n"); */ + /* clear a_bus_req to enter a_suspend state */ + otg_dev->fsm.a_bus_req = 0; + otg_statemachine(&otg_dev->fsm); + + return 0; +} + +/* Interrupt handler. OTG/host/peripheral share the same int line. + * OTG driver clears OTGSC interrupts and leaves USB interrupts + * intact. It needs to have knowledge of some USB interrupts + * such as port change. + */ +irqreturn_t fsl_otg_isr(int irq, void *dev_id) +{ + struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm; + struct otg_transceiver *otg = &((struct fsl_otg *)dev_id)->otg; + u32 otg_int_src, otg_sc; + + otg_sc = le32_to_cpu(usb_dr_regs->otgsc); + otg_int_src = otg_sc & OTGSC_INTSTS_MASK & (otg_sc >> 8); + + /* Only clear otg interrupts */ + usb_dr_regs->otgsc |= cpu_to_le32(otg_sc & OTGSC_INTSTS_MASK); + + /*FIXME: ID change not generate when init to 0 */ + fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0; + otg->default_a = (fsm->id == 0); + + /* process OTG interrupts */ + if (otg_int_src) { + if (otg_int_src & OTGSC_INTSTS_USB_ID) { + fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0; + otg->default_a = (fsm->id == 0); + /* clear conn information */ + if (fsm->id) + fsm->b_conn = 0; + else + fsm->a_conn = 0; + + if (otg->host) + otg->host->is_b_host = fsm->id; + if (otg->gadget) + otg->gadget->is_a_peripheral = !fsm->id; + VDBG("ID int (ID is %d)\n", fsm->id); + + if (fsm->id) { /* switch to gadget */ + schedule_delayed_work(&((struct fsl_otg *) + dev_id)->otg_event, + 100); + } else { /* switch to host */ + cancel_delayed_work(& + ((struct fsl_otg *)dev_id)-> + otg_event); + fsl_otg_start_gadget(fsm, 0); + otg_drv_vbus(fsm, 1); + fsl_otg_start_host(fsm, 1); + } + + return IRQ_HANDLED; + } + } + + return IRQ_NONE; +} + +static struct otg_fsm_ops fsl_otg_ops = { + .chrg_vbus = fsl_otg_chrg_vbus, + .drv_vbus = fsl_otg_drv_vbus, + .loc_conn = fsl_otg_loc_conn, + .loc_sof = fsl_otg_loc_sof, + .start_pulse = fsl_otg_start_pulse, + + .add_timer = fsl_otg_add_timer, + .del_timer = fsl_otg_del_timer, + + .start_host = fsl_otg_start_host, + .start_gadget = fsl_otg_start_gadget, +}; + +/* Initialize the global variable fsl_otg_dev and request IRQ for OTG */ +static int fsl_otg_conf(struct platform_device *pdev) +{ + int status; + struct fsl_otg *fsl_otg_tc; + struct fsl_usb2_platform_data *pdata; + + pdata = pdev->dev.platform_data; + + DBG(); + + if (fsl_otg_dev) + return 0; + + /* allocate space to fsl otg device */ + fsl_otg_tc = kzalloc(sizeof(struct fsl_otg), GFP_KERNEL); + if (!fsl_otg_tc) + return -ENODEV; + + INIT_DELAYED_WORK(&fsl_otg_tc->otg_event, fsl_otg_event); + + INIT_LIST_HEAD(&active_timers); + status = fsl_otg_init_timers(&fsl_otg_tc->fsm); + if (status) { + printk(KERN_INFO "Couldn't init OTG timers\n"); + fsl_otg_uninit_timers(); + kfree(fsl_otg_tc); + return status; + } + spin_lock_init(&fsl_otg_tc->fsm.lock); + + /* Set OTG state machine operations */ + fsl_otg_tc->fsm.ops = &fsl_otg_ops; + + /* initialize the otg structure */ + fsl_otg_tc->otg.label = DRIVER_DESC; + fsl_otg_tc->otg.set_host = fsl_otg_set_host; + fsl_otg_tc->otg.set_peripheral = fsl_otg_set_peripheral; + fsl_otg_tc->otg.set_power = fsl_otg_set_power; + fsl_otg_tc->otg.start_hnp = fsl_otg_start_hnp; + fsl_otg_tc->otg.start_srp = fsl_otg_start_srp; + + fsl_otg_dev = fsl_otg_tc; + + /* Store the otg transceiver */ + status = otg_set_transceiver(&fsl_otg_tc->otg); + if (status) { + printk(KERN_WARNING ": unable to register OTG transceiver.\n"); + return status; + } + + return 0; +} + +/* OTG Initialization*/ +int usb_otg_start(struct platform_device *pdev) +{ + struct fsl_otg *p_otg; + struct otg_transceiver *otg_trans = otg_get_transceiver(); + struct otg_fsm *fsm; + volatile unsigned long *p; + int status; + struct resource *res; + u32 temp; + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + + p_otg = container_of(otg_trans, struct fsl_otg, otg); + fsm = &p_otg->fsm; + + /* Initialize the state machine structure with default values */ + SET_OTG_STATE(otg_trans, OTG_STATE_UNDEFINED); + fsm->transceiver = &p_otg->otg; + + /* We don't require predefined MEM/IRQ resource index */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENXIO; + + /* We don't request_mem_region here to enable resource sharing + * with host/device */ + + usb_dr_regs = ioremap(res->start, sizeof(struct usb_dr_mmap)); + p_otg->dr_mem_map = (struct usb_dr_mmap *)usb_dr_regs; + pdata->regs = (void *)usb_dr_regs; + + /* request irq */ + p_otg->irq = platform_get_irq(pdev, 0); + status = request_irq(p_otg->irq, fsl_otg_isr, + IRQF_SHARED, driver_name, p_otg); + if (status) { + dev_dbg(p_otg->otg.dev, "can't get IRQ %d, error %d\n", + p_otg->irq, status); + iounmap(p_otg->dr_mem_map); + kfree(p_otg); + return status; + } + + if (pdata->platform_init && pdata->platform_init(pdev) != 0) + return -EINVAL; + + + /* Export DR controller resources */ + otg_set_resources(pdev->resource); + + /* stop the controller */ + temp = readl(&p_otg->dr_mem_map->usbcmd); + temp &= ~USB_CMD_RUN_STOP; + writel(temp, &p_otg->dr_mem_map->usbcmd); + + /* reset the controller */ + temp = readl(&p_otg->dr_mem_map->usbcmd); + temp |= USB_CMD_CTRL_RESET; + writel(temp, &p_otg->dr_mem_map->usbcmd); + + /* wait reset completed */ + while (readl(&p_otg->dr_mem_map->usbcmd) & USB_CMD_CTRL_RESET) ; + + /* configure the VBUSHS as IDLE(both host and device) */ + temp = USB_MODE_STREAM_DISABLE | (pdata->es ? USB_MODE_ES : 0); + writel(temp, &p_otg->dr_mem_map->usbmode); + + /* configure PHY interface */ + temp = readl(&p_otg->dr_mem_map->portsc); + temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW); + switch (pdata->phy_mode) { + case FSL_USB2_PHY_ULPI: + temp |= PORTSC_PTS_ULPI; + break; + case FSL_USB2_PHY_UTMI_WIDE: + temp |= PORTSC_PTW_16BIT; + /* fall through */ + case FSL_USB2_PHY_UTMI: + temp |= PORTSC_PTS_UTMI; + /* fall through */ + default: + break; + } + writel(temp, &p_otg->dr_mem_map->portsc); + + if (pdata->have_sysif_regs) { + /* configure control enable IO output, big endian register */ + p = (volatile unsigned long *)(&p_otg->dr_mem_map->control); + temp = *p; + temp |= USB_CTRL_IOENB; + *p = temp; + } + + /* disable all interrupt and clear all OTGSC status */ + temp = readl(&p_otg->dr_mem_map->otgsc); + temp &= ~OTGSC_INTERRUPT_ENABLE_BITS_MASK; + temp |= OTGSC_INTERRUPT_STATUS_BITS_MASK | OTGSC_CTRL_VBUS_DISCHARGE; + writel(temp, &p_otg->dr_mem_map->otgsc); + + + /* + * The identification (id) input is FALSE when a Mini-A plug is inserted + * in the devices Mini-AB receptacle. Otherwise, this input is TRUE. + * Also: record initial state of ID pin + */ + if (le32_to_cpu(p_otg->dr_mem_map->otgsc) & OTGSC_STS_USB_ID) { + p_otg->otg.state = OTG_STATE_UNDEFINED; + p_otg->fsm.id = 1; + } else { + p_otg->otg.state = OTG_STATE_A_IDLE; + p_otg->fsm.id = 0; + } + + DBG("initial ID pin=%d\n", p_otg->fsm.id); + + /* enable OTG ID pin interrupt */ + temp = readl(&p_otg->dr_mem_map->otgsc); + temp |= OTGSC_INTR_USB_ID_EN; + temp &= ~(OTGSC_CTRL_VBUS_DISCHARGE | OTGSC_INTR_1MS_TIMER_EN); + writel(temp, &p_otg->dr_mem_map->otgsc); + + return 0; +} + +/*------------------------------------------------------------------------- + PROC File System Support +-------------------------------------------------------------------------*/ +#ifdef CONFIG_USB_OTG_DEBUG_FILES + +#include + +static const char proc_filename[] = "driver/isp1504_otg"; + +static int otg_proc_read(char *page, char **start, off_t off, int count, + int *eof, void *_dev) +{ + struct otg_fsm *fsm = &fsl_otg_dev->fsm; + char *buf = page; + char *next = buf; + unsigned size = count; + unsigned long flags; + int t; + u32 tmp_reg; + + if (off != 0) + return 0; + + spin_lock_irqsave(&fsm->lock, flags); + + /* ------basic driver infomation ---- */ + t = scnprintf(next, size, + DRIVER_DESC "\n" "fsl_usb2_otg version: %s\n\n", + DRIVER_VERSION); + size -= t; + next += t; + + /* ------ Registers ----- */ + tmp_reg = le32_to_cpu(usb_dr_regs->otgsc); + t = scnprintf(next, size, "OTGSC reg: %08x\n", tmp_reg); + size -= t; + next += t; + + tmp_reg = le32_to_cpu(usb_dr_regs->portsc); + t = scnprintf(next, size, "PORTSC reg: %08x\n", tmp_reg); + size -= t; + next += t; + + tmp_reg = le32_to_cpu(usb_dr_regs->usbmode); + t = scnprintf(next, size, "USBMODE reg: %08x\n", tmp_reg); + size -= t; + next += t; + + tmp_reg = le32_to_cpu(usb_dr_regs->usbcmd); + t = scnprintf(next, size, "USBCMD reg: %08x\n", tmp_reg); + size -= t; + next += t; + + tmp_reg = le32_to_cpu(usb_dr_regs->usbsts); + t = scnprintf(next, size, "USBSTS reg: %08x\n", tmp_reg); + size -= t; + next += t; + + /* ------ State ----- */ + t = scnprintf(next, size, + "OTG state: %s\n\n", + state_string(fsl_otg_dev->otg.state)); + size -= t; + next += t; + +#if 1 || defined DEBUG + /* ------ State Machine Variables ----- */ + t = scnprintf(next, size, "a_bus_req: %d\n", fsm->a_bus_req); + size -= t; + next += t; + + t = scnprintf(next, size, "b_bus_req: %d\n", fsm->b_bus_req); + size -= t; + next += t; + + t = scnprintf(next, size, "a_bus_resume: %d\n", fsm->a_bus_resume); + size -= t; + next += t; + + t = scnprintf(next, size, "a_bus_suspend: %d\n", fsm->a_bus_suspend); + size -= t; + next += t; + + t = scnprintf(next, size, "a_conn: %d\n", fsm->a_conn); + size -= t; + next += t; + + t = scnprintf(next, size, "a_sess_vld: %d\n", fsm->a_sess_vld); + size -= t; + next += t; + + t = scnprintf(next, size, "a_srp_det: %d\n", fsm->a_srp_det); + size -= t; + next += t; + + t = scnprintf(next, size, "a_vbus_vld: %d\n", fsm->a_vbus_vld); + size -= t; + next += t; + + t = scnprintf(next, size, "b_bus_resume: %d\n", fsm->b_bus_resume); + size -= t; + next += t; + + t = scnprintf(next, size, "b_bus_suspend: %d\n", fsm->b_bus_suspend); + size -= t; + next += t; + + t = scnprintf(next, size, "b_conn: %d\n", fsm->b_conn); + size -= t; + next += t; + + t = scnprintf(next, size, "b_se0_srp: %d\n", fsm->b_se0_srp); + size -= t; + next += t; + + t = scnprintf(next, size, "b_sess_end: %d\n", fsm->b_sess_end); + size -= t; + next += t; + + t = scnprintf(next, size, "b_sess_vld: %d\n", fsm->b_sess_vld); + size -= t; + next += t; + + t = scnprintf(next, size, "id: %d\n", fsm->id); + size -= t; + next += t; +#endif + + spin_unlock_irqrestore(&fsm->lock, flags); + + *eof = 1; + return count - size; +} + +#define create_proc_file() create_proc_read_entry(proc_filename, \ + 0, NULL, otg_proc_read, NULL) + +#define remove_proc_file() remove_proc_entry(proc_filename, NULL) + +#else /* !CONFIG_USB_OTG_DEBUG_FILES */ + +#define create_proc_file() do {} while (0) +#define remove_proc_file() do {} while (0) + +#endif /*CONFIG_USB_OTG_DEBUG_FILES */ + +/*----------------------------------------------------------*/ +/* Char driver interface to control some OTG input */ + +/* This function handle some ioctl command,such as get otg + * status and set host suspend + */ +static int fsl_otg_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + u32 retval = 0; + + switch (cmd) { + case GET_OTG_STATUS: + retval = fsl_otg_dev->host_working; + break; + + case SET_A_SUSPEND_REQ: + fsl_otg_dev->fsm.a_suspend_req = arg; + break; + + case SET_A_BUS_DROP: + fsl_otg_dev->fsm.a_bus_drop = arg; + break; + + case SET_A_BUS_REQ: + fsl_otg_dev->fsm.a_bus_req = arg; + break; + + case SET_B_BUS_REQ: + fsl_otg_dev->fsm.b_bus_req = arg; + break; + + default: + break; + } + + otg_statemachine(&fsl_otg_dev->fsm); + + return retval; +} + +static int fsl_otg_open(struct inode *inode, struct file *file) +{ + + return 0; +} + +static int fsl_otg_release(struct inode *inode, struct file *file) +{ + + return 0; +} + +static struct file_operations otg_fops = { + .owner = THIS_MODULE, + .llseek = NULL, + .read = NULL, + .write = NULL, + .ioctl = fsl_otg_ioctl, + .open = fsl_otg_open, + .release = fsl_otg_release, +}; + +static int __init fsl_otg_probe(struct platform_device *pdev) +{ + int status; + struct fsl_usb2_platform_data *pdata; + + DBG("pdev=0x%p\n", pdev); + + if (!pdev) + return -ENODEV; + + if (!pdev->dev.platform_data) + return -ENOMEM; + + pdata = pdev->dev.platform_data; + + /* configure the OTG */ + status = fsl_otg_conf(pdev); + if (status) { + printk(KERN_INFO "Couldn't init OTG module\n"); + return -status; + } + + /* start OTG */ + status = usb_otg_start(pdev); + + if (register_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME, &otg_fops)) { + printk(KERN_WARNING FSL_OTG_NAME + ": unable to register FSL OTG device\n"); + return -EIO; + } + + create_proc_file(); + return status; +} + +static int __exit fsl_otg_remove(struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + + otg_set_transceiver(NULL); + free_irq(fsl_otg_dev->irq, fsl_otg_dev); + + iounmap((void *)usb_dr_regs); + + kfree(fsl_otg_dev); + + remove_proc_file(); + + unregister_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME); + + if (pdata->platform_uninit) + pdata->platform_uninit(pdata); + + return 0; +} + +struct platform_driver fsl_otg_driver = { + .probe = fsl_otg_probe, + .remove = fsl_otg_remove, + .driver = { + .name = driver_name, + .owner = THIS_MODULE, + }, +}; + +/*-------------------------------------------------------------------------*/ + +static int __init fsl_usb_otg_init(void) +{ + printk(KERN_INFO DRIVER_DESC " loaded, %s\n", DRIVER_VERSION); + return platform_driver_register(&fsl_otg_driver); +} + +static void __exit fsl_usb_otg_exit(void) +{ + platform_driver_unregister(&fsl_otg_driver); + printk(KERN_INFO DRIVER_DESC " unloaded\n"); +} + +module_init(fsl_usb_otg_init); +module_exit(fsl_usb_otg_exit); + +MODULE_DESCRIPTION(DRIVER_INFO); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/usb/otg/fsl_otg.h linux-2.6.26-lab126/drivers/usb/otg/fsl_otg.h --- linux-2.6.26/drivers/usb/otg/fsl_otg.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/usb/otg/fsl_otg.h 2010-08-10 04:17:08.000000000 -0400 @@ -0,0 +1,410 @@ +/* Copyright (C) 2005-2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "otg_fsm.h" +#include +#include + + /* USB Command Register Bit Masks */ +#define USB_CMD_RUN_STOP (0x1<<0 ) +#define USB_CMD_CTRL_RESET (0x1<<1 ) +#define USB_CMD_PERIODIC_SCHEDULE_EN (0x1<<4 ) +#define USB_CMD_ASYNC_SCHEDULE_EN (0x1<<5 ) +#define USB_CMD_INT_AA_DOORBELL (0x1<<6 ) +#define USB_CMD_ASP (0x3<<8 ) +#define USB_CMD_ASYNC_SCH_PARK_EN (0x1<<11 ) +#define USB_CMD_SUTW (0x1<<13 ) +#define USB_CMD_ATDTW (0x1<<14 ) +#define USB_CMD_ITC (0xFF<<16) + +/* bit 15,3,2 are frame list size */ +#define USB_CMD_FRAME_SIZE_1024 (0x0<<15 | 0x0<<2) +#define USB_CMD_FRAME_SIZE_512 (0x0<<15 | 0x1<<2) +#define USB_CMD_FRAME_SIZE_256 (0x0<<15 | 0x2<<2) +#define USB_CMD_FRAME_SIZE_128 (0x0<<15 | 0x3<<2) +#define USB_CMD_FRAME_SIZE_64 (0x1<<15 | 0x0<<2) +#define USB_CMD_FRAME_SIZE_32 (0x1<<15 | 0x1<<2) +#define USB_CMD_FRAME_SIZE_16 (0x1<<15 | 0x2<<2) +#define USB_CMD_FRAME_SIZE_8 (0x1<<15 | 0x3<<2) + +/* bit 9-8 are async schedule park mode count */ +#define USB_CMD_ASP_00 (0x0<<8) +#define USB_CMD_ASP_01 (0x1<<8) +#define USB_CMD_ASP_10 (0x2<<8) +#define USB_CMD_ASP_11 (0x3<<8) +#define USB_CMD_ASP_BIT_POS (8) + +/* bit 23-16 are interrupt threshold control */ +#define USB_CMD_ITC_NO_THRESHOLD (0x00<<16) +#define USB_CMD_ITC_1_MICRO_FRM (0x01<<16) +#define USB_CMD_ITC_2_MICRO_FRM (0x02<<16) +#define USB_CMD_ITC_4_MICRO_FRM (0x04<<16) +#define USB_CMD_ITC_8_MICRO_FRM (0x08<<16) +#define USB_CMD_ITC_16_MICRO_FRM (0x10<<16) +#define USB_CMD_ITC_32_MICRO_FRM (0x20<<16) +#define USB_CMD_ITC_64_MICRO_FRM (0x40<<16) +#define USB_CMD_ITC_BIT_POS (16) + +/* USB Status Register Bit Masks */ +#define USB_STS_INT (0x1<<0 ) +#define USB_STS_ERR (0x1<<1 ) +#define USB_STS_PORT_CHANGE (0x1<<2 ) +#define USB_STS_FRM_LST_ROLL (0x1<<3 ) +#define USB_STS_SYS_ERR (0x1<<4 ) +#define USB_STS_IAA (0x1<<5 ) +#define USB_STS_RESET_RECEIVED (0x1<<6 ) +#define USB_STS_SOF (0x1<<7 ) +#define USB_STS_DCSUSPEND (0x1<<8 ) +#define USB_STS_HC_HALTED (0x1<<12) +#define USB_STS_RCL (0x1<<13) +#define USB_STS_PERIODIC_SCHEDULE (0x1<<14) +#define USB_STS_ASYNC_SCHEDULE (0x1<<15) + +/* USB Interrupt Enable Register Bit Masks */ +#define USB_INTR_INT_EN (0x1<<0 ) +#define USB_INTR_ERR_INT_EN (0x1<<1 ) +#define USB_INTR_PC_DETECT_EN (0x1<<2 ) +#define USB_INTR_FRM_LST_ROLL_EN (0x1<<3 ) +#define USB_INTR_SYS_ERR_EN (0x1<<4 ) +#define USB_INTR_ASYN_ADV_EN (0x1<<5 ) +#define USB_INTR_RESET_EN (0x1<<6 ) +#define USB_INTR_SOF_EN (0x1<<7 ) +#define USB_INTR_DEVICE_SUSPEND (0x1<<8 ) + +/* Device Address bit masks */ +#define USB_DEVICE_ADDRESS_MASK (0x7F<<25) +#define USB_DEVICE_ADDRESS_BIT_POS (25) +/* PORTSC Register Bit Masks,Only one PORT in OTG mode*/ +#define PORTSC_CURRENT_CONNECT_STATUS (0x1<<0) +#define PORTSC_CONNECT_STATUS_CHANGE (0x1<<1) +#define PORTSC_PORT_ENABLE (0x1<<2) +#define PORTSC_PORT_EN_DIS_CHANGE (0x1<<3) +#define PORTSC_OVER_CURRENT_ACT (0x1<<4) +#define PORTSC_OVER_CUURENT_CHG (0x1<<5) +#define PORTSC_PORT_FORCE_RESUME (0x1<<6) +#define PORTSC_PORT_SUSPEND (0x1<<7) +#define PORTSC_PORT_RESET (0x1<<8) +#define PORTSC_LINE_STATUS_BITS (0x3<<10) +#define PORTSC_PORT_POWER (0x1<<12) +#define PORTSC_PORT_INDICTOR_CTRL (0x3<<14) +#define PORTSC_PORT_TEST_CTRL (0xF<<16) +#define PORTSC_WAKE_ON_CONNECT_EN (0x1<<20) +#define PORTSC_WAKE_ON_CONNECT_DIS (0x1<<21) +#define PORTSC_WAKE_ON_OVER_CURRENT (0x1<<22) +#define PORTSC_PHY_LOW_POWER_SPD (0x1<<23) +#define PORTSC_PORT_FORCE_FULL_SPEED (0x1<<24) +#define PORTSC_PORT_SPEED_MASK (0x3<<26) +#define PORTSC_TRANSCEIVER_WIDTH (0x1<<28) +#define PORTSC_PHY_TYPE_SEL (0x3<<30) +/* bit 11-10 are line status */ +#define PORTSC_LINE_STATUS_SE0 (0x0<<10) +#define PORTSC_LINE_STATUS_JSTATE (0x1<<10) +#define PORTSC_LINE_STATUS_KSTATE (0x2<<10) +#define PORTSC_LINE_STATUS_UNDEF (0x3<<10) +#define PORTSC_LINE_STATUS_BIT_POS (10) + +/* bit 15-14 are port indicator control */ +#define PORTSC_PIC_OFF (0x0<<14) +#define PORTSC_PIC_AMBER (0x1<<14) +#define PORTSC_PIC_GREEN (0x2<<14) +#define PORTSC_PIC_UNDEF (0x3<<14) +#define PORTSC_PIC_BIT_POS (14) + +/* bit 19-16 are port test control */ +#define PORTSC_PTC_DISABLE (0x0<<16) +#define PORTSC_PTC_JSTATE (0x1<<16) +#define PORTSC_PTC_KSTATE (0x2<<16) +#define PORTSC_PTC_SEQNAK (0x3<<16) +#define PORTSC_PTC_PACKET (0x4<<16) +#define PORTSC_PTC_FORCE_EN (0x5<<16) +#define PORTSC_PTC_BIT_POS (16) + +/* bit 27-26 are port speed */ +#define PORTSC_PORT_SPEED_FULL (0x0<<26) +#define PORTSC_PORT_SPEED_LOW (0x1<<26) +#define PORTSC_PORT_SPEED_HIGH (0x2<<26) +#define PORTSC_PORT_SPEED_UNDEF (0x3<<26) +#define PORTSC_SPEED_BIT_POS (26) + +/* bit 28 is parallel transceiver width for UTMI interface */ +#define PORTSC_PTW (0x1<<28) +#define PORTSC_PTW_8BIT (0x0<<28) +#define PORTSC_PTW_16BIT (0x1<<28) + +/* bit 31-30 are port transceiver select */ +#define PORTSC_PTS_UTMI (0x0<<30) +#define PORTSC_PTS_ULPI (0x2<<30) +#define PORTSC_PTS_FSLS_SERIAL (0x3<<30) +#define PORTSC_PTS_BIT_POS (30) + +#define PORTSC_W1C_BITS \ + (PORTSC_CONNECT_STATUS_CHANGE | \ + PORTSC_PORT_EN_DIS_CHANGE | \ + PORTSC_OVER_CUURENT_CHG) + +/* OTG Status Control Register Bit Masks */ +#define OTGSC_CTRL_VBUS_DISCHARGE (0x1<<0) +#define OTGSC_CTRL_VBUS_CHARGE (0x1<<1) +#define OTGSC_CTRL_OTG_TERMINATION (0x1<<3) +#define OTGSC_CTRL_DATA_PULSING (0x1<<4) +#define OTGSC_CTRL_ID_PULL_EN (0x1<<5) +#define OTGSC_HA_DATA_PULSE (0x1<<6) +#define OTGSC_HA_BA (0x1<<7) +#define OTGSC_STS_USB_ID (0x1<<8) +#define OTGSC_STS_A_VBUS_VALID (0x1<<9) +#define OTGSC_STS_A_SESSION_VALID (0x1<<10) +#define OTGSC_STS_B_SESSION_VALID (0x1<<11) +#define OTGSC_STS_B_SESSION_END (0x1<<12) +#define OTGSC_STS_1MS_TOGGLE (0x1<<13) +#define OTGSC_STS_DATA_PULSING (0x1<<14) +#define OTGSC_INTSTS_USB_ID (0x1<<16) +#define OTGSC_INTSTS_A_VBUS_VALID (0x1<<17) +#define OTGSC_INTSTS_A_SESSION_VALID (0x1<<18) +#define OTGSC_INTSTS_B_SESSION_VALID (0x1<<19) +#define OTGSC_INTSTS_B_SESSION_END (0x1<<20) +#define OTGSC_INTSTS_1MS (0x1<<21) +#define OTGSC_INTSTS_DATA_PULSING (0x1<<22) +#define OTGSC_INTR_USB_ID_EN (0x1<<24) +#define OTGSC_INTR_A_VBUS_VALID_EN (0x1<<25) +#define OTGSC_INTR_A_SESSION_VALID_EN (0x1<<26) +#define OTGSC_INTR_B_SESSION_VALID_EN (0x1<<27) +#define OTGSC_INTR_B_SESSION_END_EN (0x1<<28) +#define OTGSC_INTR_1MS_TIMER_EN (0x1<<29) +#define OTGSC_INTR_DATA_PULSING_EN (0x1<<30) +#define OTGSC_INTSTS_MASK (0x00ff0000) + +/* USB MODE Register Bit Masks */ +#define USB_MODE_CTRL_MODE_IDLE (0x0<<0) +#define USB_MODE_CTRL_MODE_DEVICE (0x2<<0) +#define USB_MODE_CTRL_MODE_HOST (0x3<<0) +#define USB_MODE_CTRL_MODE_RSV (0x1<<0) +#define USB_MODE_SETUP_LOCK_OFF (0x1<<3) +#define USB_MODE_STREAM_DISABLE (0x1<<4) +#define USB_MODE_ES (0x1<<2) /* (big) Endian Select */ + +#define MPC8349_OTG_IRQ (38) +#define CFG_IMMR_BASE (0xfe000000) +#define MPC83xx_USB_DR_BASE (CFG_IMMR_BASE + 0x23000) + +/* control Register Bit Masks */ +#define USB_CTRL_IOENB (0x1<<2) +#define USB_CTRL_ULPI_INT0EN (0x1<<0) + +/* BCSR5 */ +#define BCSR5_INT_USB (0x02) + +/* USB module clk cfg */ +#define SCCR_OFFS (0xA08) +#define SCCR_USB_CLK_DISABLE (0x00000000) /* USB clk disable */ +#define SCCR_USB_MPHCM_11 (0x00c00000) +#define SCCR_USB_MPHCM_01 (0x00400000) +#define SCCR_USB_MPHCM_10 (0x00800000) +#define SCCR_USB_DRCM_11 (0x00300000) +#define SCCR_USB_DRCM_01 (0x00100000) +#define SCCR_USB_DRCM_10 (0x00200000) + +#define SICRL_OFFS (0x114) +#define SICRL_USB0 (0x40000000) +#define SICRL_USB1 (0x20000000) + +#define SICRH_OFFS (0x118) +#define SICRH_USB_UTMI (0x00020000) + +/* OTG interrupt enable bit masks */ +#define OTGSC_INTERRUPT_ENABLE_BITS_MASK \ + (OTGSC_INTR_USB_ID_EN | \ + OTGSC_INTR_1MS_TIMER_EN | \ + OTGSC_INTR_A_VBUS_VALID_EN | \ + OTGSC_INTR_A_SESSION_VALID_EN | \ + OTGSC_INTR_B_SESSION_VALID_EN | \ + OTGSC_INTR_B_SESSION_END_EN | \ + OTGSC_INTR_DATA_PULSING_EN) + +/* OTG interrupt status bit masks */ +#define OTGSC_INTERRUPT_STATUS_BITS_MASK \ + (OTGSC_INTSTS_USB_ID | \ + OTGSC_INTR_1MS_TIMER_EN | \ + OTGSC_INTSTS_A_VBUS_VALID | \ + OTGSC_INTSTS_A_SESSION_VALID | \ + OTGSC_INTSTS_B_SESSION_VALID | \ + OTGSC_INTSTS_B_SESSION_END | \ + OTGSC_INTSTS_DATA_PULSING) + +/* + * A-DEVICE timing constants + */ + +/* Wait for VBUS Rise */ +#define TA_WAIT_VRISE (100) /* a_wait_vrise 100 ms, section: 6.6.5.1 */ + +/* Wait for B-Connect */ +#define TA_WAIT_BCON (10000) /* a_wait_bcon > 1 sec, section: 6.6.5.2 + * This is only used to get out of + * OTG_STATE_A_WAIT_BCON state if there was + * no connection for these many milliseconds + */ + +/* A-Idle to B-Disconnect */ +/* It is necessary for this timer to be more than 750 ms because of a bug in OPT + * test 5.4 in which B OPT disconnects after 750 ms instead of 75ms as stated + * in the test description + */ +#define TA_AIDL_BDIS (5000) /* a_suspend minimum 200 ms, section: 6.6.5.3 */ + +/* B-Idle to A-Disconnect */ +#define TA_BIDL_ADIS (12) /* 3 to 200 ms */ + +/* B-device timing constants */ + + +/* Data-Line Pulse Time*/ +#define TB_DATA_PLS (10) /* b_srp_init,continue 5~10ms, section:5.3.3 */ +#define TB_DATA_PLS_MIN (5) /* minimum 5 ms */ +#define TB_DATA_PLS_MAX (10) /* maximum 10 ms */ + +/* SRP Initiate Time */ +#define TB_SRP_INIT (100) /* b_srp_init,maximum 100 ms, section:5.3.8 */ + +/* SRP Fail Time */ +#define TB_SRP_FAIL (7000) /* b_srp_init,Fail time 5~30s, section:6.8.2.2*/ + +/* SRP result wait time */ +#define TB_SRP_WAIT (60) + +/* VBus time */ +#define TB_VBUS_PLS (30) /* time to keep vbus pulsing asserted */ + +/* Discharge time */ +/* This time should be less than 10ms. It varies from system to system. */ +#define TB_VBUS_DSCHRG (8) + +/* A-SE0 to B-Reset */ +#define TB_ASE0_BRST (20) /* b_wait_acon, mini 3.125 ms,section:6.8.2.4 */ + +/* A bus suspend timer before we can switch to b_wait_aconn */ +#define TB_A_SUSPEND (7) +#define TB_BUS_RESUME (12) + +/* SE0 Time Before SRP */ +#define TB_SE0_SRP (2) /* b_idle,minimum 2 ms, section:5.3.2 */ + + +#define SET_OTG_STATE(otg_ptr, newstate) ((otg_ptr)->state=newstate) + +struct usb_dr_mmap { + /* Capability register */ + u8 res1[256]; + u16 caplength; /* Capability Register Length */ + u16 hciversion; /* Host Controller Interface Version */ + u32 hcsparams; /* Host Controller Structual Parameters */ + u32 hccparams; /* Host Controller Capability Parameters */ + u8 res2[20]; + u32 dciversion; /* Device Controller Interface Version */ + u32 dccparams; /* Device Controller Capability Parameters */ + u8 res3[24]; + /* Operation register */ + u32 usbcmd; /* USB Command Register */ + u32 usbsts; /* USB Status Register */ + u32 usbintr; /* USB Interrupt Enable Register */ + u32 frindex; /* Frame Index Register */ + u8 res4[4]; + u32 deviceaddr; /* Device Address */ + u32 endpointlistaddr; /* Endpoint List Address Register */ + u8 res5[4]; + u32 burstsize; /* Master Interface Data Burst Size Register */ + u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ + u8 res6[8]; + u32 ulpiview; /* ULPI register access */ + u8 res7[12]; + u32 configflag; /* Configure Flag Register */ + u32 portsc; /* Port 1 Status and Control Register */ + u8 res8[28]; + u32 otgsc; /* On-The-Go Status and Control */ + u32 usbmode; /* USB Mode Register */ + u32 endptsetupstat; /* Endpoint Setup Status Register */ + u32 endpointprime; /* Endpoint Initialization Register */ + u32 endptflush; /* Endpoint Flush Register */ + u32 endptstatus; /* Endpoint Status Register */ + u32 endptcomplete; /* Endpoint Complete Register */ + u32 endptctrl[6]; /* Endpoint Control Registers */ + u8 res9[552]; + u32 snoop1; + u32 snoop2; + u32 age_cnt_thresh; /* Age Count Threshold Register */ + u32 pri_ctrl; /* Priority Control Register */ + u32 si_ctrl; /* System Interface Control Register */ + u8 res10[236]; + u32 control; /* General Purpose Control Register */ +}; + + +struct fsl_otg_timer { + unsigned long expires; /* Number of count increase to timeout */ + unsigned long count; /* Tick counter */ + void (*function)(unsigned long); /* Timeout function */ + unsigned long data; /* Data passed to function */ + struct list_head list; +}; + +struct fsl_otg_timer inline *otg_timer_initializer +(void (*function)(unsigned long), unsigned long expires, unsigned long data) +{ + struct fsl_otg_timer *timer; + timer = kmalloc(sizeof(struct fsl_otg_timer), GFP_KERNEL); + if (timer == NULL) + return NULL; + timer->function = function; + timer->expires = expires; + timer->data = data; + return timer; +} + +struct fsl_otg { + struct otg_transceiver otg; + struct otg_fsm fsm; + struct usb_dr_mmap *dr_mem_map; + struct delayed_work otg_event; + + /*used for usb host */ + struct work_struct work_wq; + u8 host_working; + + int irq; +}; + +struct fsl_otg_config { + u8 otg_port; +}; + +/*For SRP and HNP handle*/ +#define FSL_OTG_MAJOR 66 +#define FSL_OTG_NAME "fsl-usb2-otg" +/*Command to OTG driver(ioctl)*/ +#define OTG_IOCTL_MAGIC FSL_OTG_MAJOR +/*if otg work as host,it should return 1,otherwise it return 0*/ +#define GET_OTG_STATUS _IOR(OTG_IOCTL_MAGIC, 1, int) +#define SET_A_SUSPEND_REQ _IOW(OTG_IOCTL_MAGIC, 2, int) +#define SET_A_BUS_DROP _IOW(OTG_IOCTL_MAGIC, 3, int) +#define SET_A_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 4, int) +#define SET_B_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 5, int) +#define GET_A_SUSPEND_REQ _IOR(OTG_IOCTL_MAGIC, 6, int) +#define GET_A_BUS_DROP _IOR(OTG_IOCTL_MAGIC, 7, int) +#define GET_A_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 8, int) +#define GET_B_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 9, int) + +extern const char *state_string(enum usb_otg_state state); +extern int otg_set_resources(struct resource *resources); diff -urN linux-2.6.26/drivers/usb/otg/otg_fsm.c linux-2.6.26-lab126/drivers/usb/otg/otg_fsm.c --- linux-2.6.26/drivers/usb/otg/otg_fsm.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/usb/otg/otg_fsm.c 2010-08-10 04:17:08.000000000 -0400 @@ -0,0 +1,371 @@ +/* OTG Finite State Machine from OTG spec + * + * Copyright (C) 2006-2008 Freescale Semiconductor, Inc. + * + * Author: Li Yang + * Jerry Huang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include "otg_fsm.h" + + +/* Defined by device specific driver, for different timer implementation */ +extern void *a_wait_vrise_tmr, *a_wait_bcon_tmr, *a_aidl_bdis_tmr, + *b_ase0_brst_tmr, *b_se0_srp_tmr, *b_srp_fail_tmr, *a_wait_enum_tmr; + +const char *state_string(enum usb_otg_state state) +{ + switch (state) { + case OTG_STATE_A_IDLE: return "a_idle"; + case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise"; + case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon"; + case OTG_STATE_A_HOST: return "a_host"; + case OTG_STATE_A_SUSPEND: return "a_suspend"; + case OTG_STATE_A_PERIPHERAL: return "a_peripheral"; + case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall"; + case OTG_STATE_A_VBUS_ERR: return "a_vbus_err"; + case OTG_STATE_B_IDLE: return "b_idle"; + case OTG_STATE_B_SRP_INIT: return "b_srp_init"; + case OTG_STATE_B_PERIPHERAL: return "b_peripheral"; + case OTG_STATE_B_WAIT_ACON: return "b_wait_acon"; + case OTG_STATE_B_HOST: return "b_host"; + default: return "UNDEFINED"; + } +} + +/* Change USB protocol when there is a protocol change */ +static int otg_set_protocol(struct otg_fsm *fsm, int protocol) +{ + int ret = 0; + + if (fsm->protocol != protocol) { + VDBG("Changing role fsm->protocol= %d; new protocol= %d\n", + fsm->protocol, protocol); + /* stop old protocol */ + if (fsm->protocol == PROTO_HOST) + ret = fsm->ops->start_host(fsm, 0); + else if (fsm->protocol == PROTO_GADGET) + ret = fsm->ops->start_gadget(fsm, 0); + if (ret) + return ret; + + /* start new protocol */ + if (protocol == PROTO_HOST) + ret = fsm->ops->start_host(fsm, 1); + else if (protocol == PROTO_GADGET) + ret = fsm->ops->start_gadget(fsm, 1); + if (ret) + return ret; + + fsm->protocol = protocol; + return 0; + } + + return 0; +} + +static int state_changed; + +/* Called when leaving a state. Do state clean up jobs here */ +void otg_leave_state(struct otg_fsm *fsm, enum usb_otg_state old_state) +{ + switch (old_state) { + case OTG_STATE_B_IDLE: + otg_del_timer(fsm, b_se0_srp_tmr); + fsm->b_se0_srp = 0; + break; + case OTG_STATE_B_SRP_INIT: + fsm->b_srp_done = 0; + break; + case OTG_STATE_B_PERIPHERAL: + break; + case OTG_STATE_B_WAIT_ACON: + otg_del_timer(fsm, b_ase0_brst_tmr); + fsm->b_ase0_brst_tmout = 0; + break; + case OTG_STATE_B_HOST: + break; + case OTG_STATE_A_IDLE: + break; + case OTG_STATE_A_WAIT_VRISE: + otg_del_timer(fsm, a_wait_vrise_tmr); + fsm->a_wait_vrise_tmout = 0; + break; + case OTG_STATE_A_WAIT_BCON: + otg_del_timer(fsm, a_wait_bcon_tmr); + fsm->a_wait_bcon_tmout = 0; + break; + case OTG_STATE_A_HOST: + otg_del_timer(fsm, a_wait_enum_tmr); + break; + case OTG_STATE_A_SUSPEND: + otg_del_timer(fsm, a_aidl_bdis_tmr); + fsm->a_aidl_bdis_tmout = 0; + fsm->a_suspend_req = 0; + break; + case OTG_STATE_A_PERIPHERAL: + break; + case OTG_STATE_A_WAIT_VFALL: + otg_del_timer(fsm, a_wait_vrise_tmr); + break; + case OTG_STATE_A_VBUS_ERR: + break; + default: + break; + } +} + +/* Called when entering a state */ +int otg_set_state(struct otg_fsm *fsm, enum usb_otg_state new_state) +{ + state_changed = 1; + if (fsm->transceiver->state == new_state) + return 0; + VDBG("Set state: %s \n", state_string(new_state)); + otg_leave_state(fsm, fsm->transceiver->state); + switch (new_state) { + case OTG_STATE_B_IDLE: + otg_drv_vbus(fsm, 0); + otg_chrg_vbus(fsm, 0); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_UNDEF); + otg_add_timer(fsm, b_se0_srp_tmr); + break; + case OTG_STATE_B_SRP_INIT: + otg_start_pulse(fsm); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_UNDEF); + otg_add_timer(fsm, b_srp_fail_tmr); + break; + case OTG_STATE_B_PERIPHERAL: + otg_chrg_vbus(fsm, 0); + otg_loc_conn(fsm, 1); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_GADGET); + break; + case OTG_STATE_B_WAIT_ACON: + otg_chrg_vbus(fsm, 0); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_HOST); + otg_add_timer(fsm, b_ase0_brst_tmr); + fsm->a_bus_suspend = 0; + break; + case OTG_STATE_B_HOST: + otg_chrg_vbus(fsm, 0); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 1); + otg_set_protocol(fsm, PROTO_HOST); + usb_bus_start_enum(fsm->transceiver->host, + fsm->transceiver->host->otg_port); + break; + case OTG_STATE_A_IDLE: + otg_drv_vbus(fsm, 0); + otg_chrg_vbus(fsm, 0); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_HOST); + break; + case OTG_STATE_A_WAIT_VRISE: + otg_drv_vbus(fsm, 1); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_HOST); + otg_add_timer(fsm, a_wait_vrise_tmr); + break; + case OTG_STATE_A_WAIT_BCON: + otg_drv_vbus(fsm, 1); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_HOST); + otg_add_timer(fsm, a_wait_bcon_tmr); + break; + case OTG_STATE_A_HOST: + otg_drv_vbus(fsm, 1); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 1); + otg_set_protocol(fsm, PROTO_HOST); + /* When HNP is triggered while a_bus_req = 0, a_host will + * suspend too fast to complete a_set_b_hnp_en */ + if (!fsm->a_bus_req || fsm->a_suspend_req) + otg_add_timer(fsm, a_wait_enum_tmr); + break; + case OTG_STATE_A_SUSPEND: + otg_drv_vbus(fsm, 1); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_HOST); + otg_add_timer(fsm, a_aidl_bdis_tmr); + + break; + case OTG_STATE_A_PERIPHERAL: + otg_loc_conn(fsm, 1); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_GADGET); + otg_drv_vbus(fsm, 1); + break; + case OTG_STATE_A_WAIT_VFALL: + otg_drv_vbus(fsm, 0); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_HOST); + break; + case OTG_STATE_A_VBUS_ERR: + otg_drv_vbus(fsm, 0); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_UNDEF); + break; + default: + break; + } + + fsm->transceiver->state = new_state; + return 0; +} + +/* State change judgement */ +int otg_statemachine(struct otg_fsm *fsm) +{ + enum usb_otg_state state; + unsigned long flags; + + spin_lock_irqsave(&fsm->lock, flags); + + state = fsm->transceiver->state; + state_changed = 0; + /* State machine state change judgement */ + + switch (state) { + case OTG_STATE_UNDEFINED: + VDBG("fsm->id = %d \n", fsm->id); + if (fsm->id) + otg_set_state(fsm, OTG_STATE_B_IDLE); + else + otg_set_state(fsm, OTG_STATE_A_IDLE); + break; + case OTG_STATE_B_IDLE: + if (!fsm->id) + otg_set_state(fsm, OTG_STATE_A_IDLE); + else if (fsm->b_sess_vld && fsm->transceiver->gadget) + otg_set_state(fsm, OTG_STATE_B_PERIPHERAL); + else if (fsm->b_bus_req && fsm->b_sess_end && fsm->b_se0_srp) + otg_set_state(fsm, OTG_STATE_B_SRP_INIT); + break; + case OTG_STATE_B_SRP_INIT: + if (!fsm->id || fsm->b_srp_done) + otg_set_state(fsm, OTG_STATE_B_IDLE); + break; + case OTG_STATE_B_PERIPHERAL: + if (!fsm->id || !fsm->b_sess_vld) + otg_set_state(fsm, OTG_STATE_B_IDLE); + else if (fsm->b_bus_req && fsm->transceiver-> + gadget->b_hnp_enable && fsm->a_bus_suspend) + otg_set_state(fsm, OTG_STATE_B_WAIT_ACON); + break; + case OTG_STATE_B_WAIT_ACON: + if (fsm->a_conn) + otg_set_state(fsm, OTG_STATE_B_HOST); + else if (!fsm->id || !fsm->b_sess_vld) + otg_set_state(fsm, OTG_STATE_B_IDLE); + else if (fsm->a_bus_resume || fsm->b_ase0_brst_tmout) { + fsm->b_ase0_brst_tmout = 0; + otg_set_state(fsm, OTG_STATE_B_PERIPHERAL); + } + break; + case OTG_STATE_B_HOST: + if (!fsm->id || !fsm->b_sess_vld) + otg_set_state(fsm, OTG_STATE_B_IDLE); + else if (!fsm->b_bus_req || !fsm->a_conn) + otg_set_state(fsm, OTG_STATE_B_PERIPHERAL); + break; + case OTG_STATE_A_IDLE: + if (fsm->id) + otg_set_state(fsm, OTG_STATE_B_IDLE); + else if (!fsm->a_bus_drop && (fsm->a_bus_req || fsm->a_srp_det)) + otg_set_state(fsm, OTG_STATE_A_WAIT_VRISE); + break; + case OTG_STATE_A_WAIT_VRISE: + if (fsm->id || fsm->a_bus_drop || fsm->a_vbus_vld || + fsm->a_wait_vrise_tmout) { + otg_set_state(fsm, OTG_STATE_A_WAIT_BCON); + } + break; + case OTG_STATE_A_WAIT_BCON: + if (!fsm->a_vbus_vld) + otg_set_state(fsm, OTG_STATE_A_VBUS_ERR); + else if (fsm->b_conn) + otg_set_state(fsm, OTG_STATE_A_HOST); + else if (fsm->id | fsm->a_bus_drop | fsm->a_wait_bcon_tmout) + otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL); + break; + case OTG_STATE_A_HOST: + if ((!fsm->a_bus_req || fsm->a_suspend_req) && + fsm->transceiver->host->b_hnp_enable) + otg_set_state(fsm, OTG_STATE_A_SUSPEND); + else if (fsm->id || !fsm->b_conn || fsm->a_bus_drop) + otg_set_state(fsm, OTG_STATE_A_WAIT_BCON); + else if (!fsm->a_vbus_vld) + otg_set_state(fsm, OTG_STATE_A_VBUS_ERR); + break; + case OTG_STATE_A_SUSPEND: + if (!fsm->b_conn && fsm->transceiver->host->b_hnp_enable) + otg_set_state(fsm, OTG_STATE_A_PERIPHERAL); + else if (!fsm->b_conn && !fsm->transceiver->host->b_hnp_enable) + otg_set_state(fsm, OTG_STATE_A_WAIT_BCON); + else if (fsm->a_bus_req || fsm->b_bus_resume) + otg_set_state(fsm, OTG_STATE_A_HOST); + else if (fsm->id || fsm->a_bus_drop || fsm->a_aidl_bdis_tmout) + otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL); + else if (!fsm->a_vbus_vld) + otg_set_state(fsm, OTG_STATE_A_VBUS_ERR); + break; + case OTG_STATE_A_PERIPHERAL: + if (fsm->id || fsm->a_bus_drop) + otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL); + else if (fsm->b_bus_suspend) + otg_set_state(fsm, OTG_STATE_A_WAIT_BCON); + else if (!fsm->a_vbus_vld) + otg_set_state(fsm, OTG_STATE_A_VBUS_ERR); + break; + case OTG_STATE_A_WAIT_VFALL: + if (fsm->id || fsm->a_bus_req || (!fsm->a_sess_vld && + !fsm->b_conn)) + otg_set_state(fsm, OTG_STATE_A_IDLE); + break; + case OTG_STATE_A_VBUS_ERR: + if (fsm->id || fsm->a_bus_drop || fsm->a_clr_err) + otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL); + break; + default: + break; + } + spin_unlock_irqrestore(&fsm->lock, flags); + + /* VDBG("quit statemachine, changed = %d \n", state_changed); */ + return state_changed; +} diff -urN linux-2.6.26/drivers/usb/otg/otg_fsm.h linux-2.6.26-lab126/drivers/usb/otg/otg_fsm.h --- linux-2.6.26/drivers/usb/otg/otg_fsm.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/usb/otg/otg_fsm.h 2010-08-10 04:17:08.000000000 -0400 @@ -0,0 +1,151 @@ +/* Copyright (C) 2006-2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#if 0 +#define DEBUG 1 +#define VERBOSE 1 +#endif + +#ifdef DEBUG +#define DBG(fmt, args...) printk(KERN_DEBUG "j=%lu [%s] " fmt "\n", jiffies, \ + __func__, ## args) +#else +#define DBG(fmt, args...) do {} while (0) +#endif + +#ifdef VERBOSE +#define VDBG DBG +#else +#define VDBG(stuff...) do {} while (0) +#endif + +#ifdef VERBOSE +#define MPC_LOC printk("Current Location [%s]:[%d]\n", __FILE__, __LINE__) +#else +#define MPC_LOC do {} while (0) +#endif + +#define PROTO_UNDEF (0) +#define PROTO_HOST (1) +#define PROTO_GADGET (2) + +/* OTG state machine according to the OTG spec */ +struct otg_fsm { + /* Input */ + int a_bus_resume; + int a_bus_suspend; + int a_conn; + int a_sess_vld; + int a_srp_det; + int a_vbus_vld; + int b_bus_resume; + int b_bus_suspend; + int b_conn; + int b_se0_srp; + int b_sess_end; + int b_sess_vld; + int id; + + /* Internal variables */ + int a_set_b_hnp_en; + int b_srp_done; + int b_hnp_enable; + + /* Timeout indicator for timers */ + int a_wait_vrise_tmout; + int a_wait_bcon_tmout; + int a_aidl_bdis_tmout; + int b_ase0_brst_tmout; + + /* Informative variables */ + int a_bus_drop; + int a_bus_req; + int a_clr_err; + int a_suspend_req; + int b_bus_req; + + /* Output */ + int drv_vbus; + int loc_conn; + int loc_sof; + + struct otg_fsm_ops *ops; + struct otg_transceiver *transceiver; + + /* Current usb protocol used: 0:undefine; 1:host; 2:client */ + int protocol; + spinlock_t lock; +}; + +struct otg_fsm_ops { + void (*chrg_vbus)(int on); + void (*drv_vbus)(int on); + void (*loc_conn)(int on); + void (*loc_sof)(int on); + void (*start_pulse)(void); + void (*add_timer)(void *timer); + void (*del_timer)(void *timer); + int (*start_host)(struct otg_fsm *fsm, int on); + int (*start_gadget)(struct otg_fsm *fsm, int on); +}; + + +static inline void otg_chrg_vbus(struct otg_fsm *fsm, int on) +{ + fsm->ops->chrg_vbus(on); +} + +static inline void otg_drv_vbus(struct otg_fsm *fsm, int on) +{ + if (fsm->drv_vbus != on) { + fsm->drv_vbus = on; + fsm->ops->drv_vbus(on); + } +} + +static inline void otg_loc_conn(struct otg_fsm *fsm, int on) +{ + if (fsm->loc_conn != on) { + fsm->loc_conn = on; + fsm->ops->loc_conn(on); + } +} + +static inline void otg_loc_sof(struct otg_fsm *fsm, int on) +{ + if (fsm->loc_sof != on) { + fsm->loc_sof = on; + fsm->ops->loc_sof(on); + } +} + +static inline void otg_start_pulse(struct otg_fsm *fsm) +{ + fsm->ops->start_pulse(); +} + +static inline void otg_add_timer(struct otg_fsm *fsm, void *timer) +{ + fsm->ops->add_timer(timer); +} + +static inline void otg_del_timer(struct otg_fsm *fsm, void *timer) +{ + fsm->ops->del_timer(timer); +} + +int otg_statemachine(struct otg_fsm *fsm); diff -urN linux-2.6.26/drivers/usb/serial/option.c linux-2.6.26-lab126/drivers/usb/serial/option.c --- linux-2.6.26/drivers/usb/serial/option.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/serial/option.c 2010-08-10 04:17:06.000000000 -0400 @@ -1,6 +1,7 @@ /* USB Driver for GSM modems + Copyright (C) 2009 Manish Lachwani (lachwani@lab126.com) Copyright (C) 2005 Matthias Urlichs This driver is free software; you can redistribute it and/or modify @@ -66,6 +67,11 @@ static int option_tiocmset(struct usb_serial_port *port, struct file *file, unsigned int set, unsigned int clear); static int option_send_setup(struct usb_serial_port *port); +static int option_suspend(struct usb_serial *serial, pm_message_t message); +static int option_resume(struct usb_serial *serial); + +/* Wakeup the bus out of low power idle */ +extern void ehci_hcd_recalc_work(void); /* Vendor and product IDs */ #define OPTION_VENDOR_ID 0x0AF0 @@ -318,6 +324,8 @@ .name = "option", .probe = usb_serial_probe, .disconnect = usb_serial_disconnect, + .suspend = usb_serial_suspend, + .resume = usb_serial_resume, .id_table = option_ids, .no_dynamic_id = 1, }; @@ -350,6 +358,8 @@ .attach = option_startup, .shutdown = option_shutdown, .read_int_callback = option_instat_callback, + .suspend = option_suspend, + .resume = option_resume, }; #ifdef CONFIG_USB_DEBUG @@ -361,9 +371,9 @@ /* per port private data */ #define N_IN_URB 4 -#define N_OUT_URB 1 +#define N_OUT_URB 4 #define IN_BUFLEN 4096 -#define OUT_BUFLEN 128 +#define OUT_BUFLEN 4096 struct option_port_private { /* Input endpoints and buffer for this port */ @@ -396,6 +406,7 @@ if (retval) goto failed_driver_register; + ehci_hcd_recalc_work(); info(DRIVER_DESC ": " DRIVER_VERSION); return 0; @@ -417,23 +428,27 @@ static void option_rx_throttle(struct usb_serial_port *port) { + ehci_hcd_recalc_work(); dbg("%s", __func__); } static void option_rx_unthrottle(struct usb_serial_port *port) { + ehci_hcd_recalc_work(); dbg("%s", __func__); } static void option_break_ctl(struct usb_serial_port *port, int break_state) { /* Unfortunately, I don't know how to send a break */ + ehci_hcd_recalc_work(); dbg("%s", __func__); } static void option_set_termios(struct usb_serial_port *port, struct ktermios *old_termios) { + ehci_hcd_recalc_work(); dbg("%s", __func__); /* Doesn't support option setting */ tty_termios_copy_hw(port->tty->termios, old_termios); @@ -495,6 +510,7 @@ portdata = usb_get_serial_port_data(port); + ehci_hcd_recalc_work(); dbg("%s: write (%d chars)", __func__, count); i = 0; @@ -551,6 +567,7 @@ unsigned char *data = urb->transfer_buffer; int status = urb->status; + ehci_hcd_recalc_work(); dbg("%s: %p", __func__, urb); endpoint = usb_pipeendpoint(urb->pipe); @@ -586,6 +603,7 @@ struct option_port_private *portdata; int i; + ehci_hcd_recalc_work(); dbg("%s", __func__); port = urb->context; @@ -610,6 +628,7 @@ struct option_port_private *portdata = usb_get_serial_port_data(port); struct usb_serial *serial = port->serial; + ehci_hcd_recalc_work(); dbg("%s", __func__); dbg("%s: urb %p port %p has data %p", __func__,urb,port,portdata); @@ -672,6 +691,7 @@ data_len += OUT_BUFLEN; } + ehci_hcd_recalc_work(); dbg("%s: %d", __func__, data_len); return data_len; } @@ -692,6 +712,8 @@ if (this_urb && test_bit(i, &portdata->out_busy)) data_len += this_urb->transfer_buffer_length; } + + ehci_hcd_recalc_work(); dbg("%s: %d", __func__, data_len); return data_len; } @@ -705,6 +727,7 @@ portdata = usb_get_serial_port_data(port); + ehci_hcd_recalc_work(); dbg("%s", __func__); /* Set some sane defaults */ @@ -759,6 +782,7 @@ struct usb_serial *serial = port->serial; struct option_port_private *portdata; + ehci_hcd_recalc_work(); dbg("%s", __func__); portdata = usb_get_serial_port_data(port); @@ -790,6 +814,7 @@ if (endpoint == -1) return NULL; /* endpoint not needed */ + ehci_hcd_recalc_work(); urb = usb_alloc_urb(0, GFP_KERNEL); /* No ISO */ if (urb == NULL) { dbg("%s: alloc for endpoint %d failed.", __func__, endpoint); @@ -811,6 +836,7 @@ struct usb_serial_port *port; struct option_port_private *portdata; + ehci_hcd_recalc_work(); dbg("%s", __func__); for (i = 0; i < serial->num_ports; i++) { @@ -844,6 +870,9 @@ struct usb_serial *serial = port->serial; struct option_port_private *portdata; int ifNum = serial->interface->cur_altsetting->desc.bInterfaceNumber; + int status = 0; + + ehci_hcd_recalc_work(); dbg("%s", __func__); portdata = usb_get_serial_port_data(port); @@ -855,9 +884,17 @@ if (portdata->rts_state) val |= 0x02; - return usb_control_msg(serial->dev, + status = usb_control_msg(serial->dev, usb_rcvctrlpipe(serial->dev, 0), 0x22,0x21,val,ifNum,NULL,0,USB_CTRL_SET_TIMEOUT); + + (void) usb_control_msg(serial->dev, usb_sndctrlpipe(serial->dev, 0), + USB_REQ_SET_FEATURE, USB_RECIP_DEVICE, + USB_DEVICE_REMOTE_WAKEUP, 0, + NULL, 0, + USB_CTRL_SET_TIMEOUT); + + return status; } return 0; @@ -870,6 +907,7 @@ struct option_port_private *portdata; u8 *buffer; + ehci_hcd_recalc_work(); dbg("%s", __func__); /* Now setup per port private data */ @@ -921,15 +959,12 @@ return 1; } -static void option_shutdown(struct usb_serial *serial) +static void stop_read_write_urbs(struct usb_serial *serial) { int i, j; struct usb_serial_port *port; struct option_port_private *portdata; - dbg("%s", __func__); - - /* Stop reading/writing urbs */ for (i = 0; i < serial->num_ports; ++i) { port = serial->port[i]; portdata = usb_get_serial_port_data(port); @@ -938,6 +973,18 @@ for (j = 0; j < N_OUT_URB; j++) usb_kill_urb(portdata->out_urbs[j]); } +} + +static void option_shutdown(struct usb_serial *serial) +{ + int i, j; + struct usb_serial_port *port; + struct option_port_private *portdata; + + ehci_hcd_recalc_work(); + dbg("%s", __func__); + + stop_read_write_urbs(serial); /* Now free them */ for (i = 0; i < serial->num_ports; ++i) { @@ -967,6 +1014,67 @@ } } +static int option_suspend(struct usb_serial *serial, pm_message_t message) +{ + dbg("%s entered", __func__); + stop_read_write_urbs(serial); + + return 0; +} + +static int option_resume(struct usb_serial *serial) +{ + int err, i, j; + struct usb_serial_port *port; + struct urb *urb; + struct option_port_private *portdata; + + dbg("%s entered", __func__); + + /* get the interrupt URBs resubmitted unconditionally */ + for (i = 0; i < serial->num_ports; i++) { + port = serial->port[i]; + if (!port->interrupt_in_urb) { + dbg("%s: No interrupt URB for port %d\n", __func__, i); + continue; + } + port->interrupt_in_urb->dev = serial->dev; + err = usb_submit_urb(port->interrupt_in_urb, GFP_NOIO); + dbg("Submitted interrupt URB for port %d (result %d)", i, err); + if (err < 0) { + err("%s: Error %d for interrupt URB of port%d", + __func__, err, i); + return err; + } + } + + for (i = 0; i < serial->num_ports; i++) { + /* walk all ports */ + port = serial->port[i]; + portdata = usb_get_serial_port_data(port); + mutex_lock(&port->mutex); + + /* skip closed ports */ + if (!port->open_count) { + mutex_unlock(&port->mutex); + continue; + } + + for (j = 0; j < N_IN_URB; j++) { + urb = portdata->in_urbs[j]; + err = usb_submit_urb(urb, GFP_NOIO); + if (err < 0) { + mutex_unlock(&port->mutex); + err("%s: Error %d for bulk URB %d", + __func__, err, i); + return err; + } + } + mutex_unlock(&port->mutex); + } + return 0; +} + MODULE_AUTHOR(DRIVER_AUTHOR); MODULE_DESCRIPTION(DRIVER_DESC); MODULE_VERSION(DRIVER_VERSION); diff -urN linux-2.6.26/drivers/usb/serial/usb-serial.c linux-2.6.26-lab126/drivers/usb/serial/usb-serial.c --- linux-2.6.26/drivers/usb/serial/usb-serial.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/serial/usb-serial.c 2010-08-10 04:17:06.000000000 -0400 @@ -62,6 +62,7 @@ static struct usb_serial *serial_table[SERIAL_TTY_MINORS]; /* initially all NULL */ static DEFINE_MUTEX(table_lock); static LIST_HEAD(usb_serial_driver_list); +static ushort maxSize = 0; struct usb_serial *usb_serial_get_by_index(unsigned index) { @@ -812,7 +813,7 @@ dev_err(&interface->dev, "No free urbs available\n"); goto probe_error; } - buffer_size = le16_to_cpu(endpoint->wMaxPacketSize); + buffer_size = le16_to_cpu(endpoint->wMaxPacketSize > maxSize ? endpoint->wMaxPacketSize : maxSize); port->bulk_in_size = buffer_size; port->bulk_in_endpointAddress = endpoint->bEndpointAddress; port->bulk_in_buffer = kmalloc (buffer_size, GFP_KERNEL); @@ -836,7 +837,7 @@ dev_err(&interface->dev, "No free urbs available\n"); goto probe_error; } - buffer_size = le16_to_cpu(endpoint->wMaxPacketSize); + buffer_size = le16_to_cpu(endpoint->wMaxPacketSize > maxSize ? endpoint->wMaxPacketSize : maxSize); port->bulk_out_size = buffer_size; port->bulk_out_endpointAddress = endpoint->bEndpointAddress; port->bulk_out_buffer = kmalloc (buffer_size, GFP_KERNEL); @@ -861,7 +862,7 @@ dev_err(&interface->dev, "No free urbs available\n"); goto probe_error; } - buffer_size = le16_to_cpu(endpoint->wMaxPacketSize); + buffer_size = le16_to_cpu(endpoint->wMaxPacketSize > maxSize ? endpoint->wMaxPacketSize : maxSize); port->interrupt_in_endpointAddress = endpoint->bEndpointAddress; port->interrupt_in_buffer = kmalloc (buffer_size, GFP_KERNEL); if (!port->interrupt_in_buffer) { @@ -888,7 +889,7 @@ dev_err(&interface->dev, "No free urbs available\n"); goto probe_error; } - buffer_size = le16_to_cpu(endpoint->wMaxPacketSize); + buffer_size = le16_to_cpu(endpoint->wMaxPacketSize > maxSize ? endpoint->wMaxPacketSize : maxSize); port->interrupt_out_size = buffer_size; port->interrupt_out_endpointAddress = endpoint->bEndpointAddress; port->interrupt_out_buffer = kmalloc (buffer_size, GFP_KERNEL); @@ -1226,3 +1227,6 @@ module_param(debug, bool, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(debug, "Debug enabled or not"); +module_param(maxSize, ushort, 0); +MODULE_PARM_DESC(maxSize, "User specified USB endpoint size"); + diff -urN linux-2.6.26/drivers/usb/storage/usb.h linux-2.6.26-lab126/drivers/usb/storage/usb.h --- linux-2.6.26/drivers/usb/storage/usb.h 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/usb/storage/usb.h 2010-08-10 04:17:11.000000000 -0400 @@ -147,7 +147,7 @@ struct task_struct *ctl_thread; /* the control thread */ /* mutual exclusion and synchronization structures */ - struct semaphore sema; /* to sleep thread on */ + struct compat_semaphore sema; /* to sleep thread on */ struct completion notify; /* thread begin/end */ wait_queue_head_t delay_wait; /* wait during scan, reset */ struct completion scanning_done; /* wait for scan thread */ diff -urN linux-2.6.26/drivers/usb/usblan/Kconfig linux-2.6.26-lab126/drivers/usb/usblan/Kconfig --- linux-2.6.26/drivers/usb/usblan/Kconfig 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/usb/usblan/Kconfig 2010-08-10 04:17:07.000000000 -0400 @@ -0,0 +1,24 @@ +# +# USB Network devices configuration +# +comment "Belcarra USBLAN Networking for USB" + depends on USB && NET + +config USB_USBLAN + tristate "Support for Belcarra USBLAN Network Devices" + depends on USB && NET + +config USB_USBLAN_IDS + bool "Override built-in Vendor and Product ID's" + depends on USB && NET && USB_USBLAN + default "n" + +config USB_USBLAN_VENDORID + hex "USB Vendor ID for the USBLAN network device" + depends on USB_USBLAN && USB_USBLAN_IDS + default "0" + +config USB_USBLAN_PRODUCTID + hex "USB Product ID for the USBLAN network device" + depends on USB_USBLAN && USB_USBLAN_IDS + default "0" diff -urN linux-2.6.26/drivers/usb/usblan/Makefile linux-2.6.26-lab126/drivers/usb/usblan/Makefile --- linux-2.6.26/drivers/usb/usblan/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/usb/usblan/Makefile 2010-08-10 04:17:07.000000000 -0400 @@ -0,0 +1,8 @@ +# +# Makefile for USB Network drivers +# + +OTGDIR=$(srctree)/drivers/otg +EXTRA_CFLAGS += -I$(OTGDIR) +EXTRA_CFLAGS_nostdinc += -I$(OTGDIR) +obj-$(CONFIG_USB_USBLAN) += usblan.o diff -urN linux-2.6.26/drivers/usb/usblan/usblan-compat.h linux-2.6.26-lab126/drivers/usb/usblan/usblan-compat.h --- linux-2.6.26/drivers/usb/usblan/usblan-compat.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/usb/usblan/usblan-compat.h 2010-08-10 04:17:07.000000000 -0400 @@ -0,0 +1,286 @@ +/********************************************************************* + * A set of macros to cross-navigate Linux 2.4 and Linux 2.6 kernel + * facilities. + * Copyright (c) 2004, 2005 Belcarra Technologies Corp + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * By: + * Stuart Lynne , Bruce Balden + * + ***********************************************************************/ +#ifndef _USB_NET_USBLAN_COMPAT_H +#define _USB_NET_USBLAN_COMPAT_H 1 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,2) +#define LINUX26 +#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,4,5) +#define LINUX24 +#else /* LINUX_VERSION_CODE > KERNEL_VERSION(2,4,5) */ +#define LINUX24 +#define LINUX_OLD +#warning "Early unsupported release of Linux kernel" +#endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2,4,5) */ + + +/*! @{ */ +#undef PRAGMAPACK +#define PACKED __attribute__((packed)) +#define INLINE __inline__ + +/*! @} */ + +/*! @name Memory Allocation Primitives + * + * CKMALLOC() + * LSTRDUP() + * LKFREE() + * LIST_ENTRY() + * LIST_FOR_EACH() + */ + + /*! @{ */ + +#if defined(LINUX26) + #include +#define GET_KERNEL_PAGE() __get_free_page(GFP_KERNEL) + +#else /* LINUX26 */ + + #include + #define GET_KERNEL_PAGE() get_free_page(GFP_KERNEL) +#endif /* LINUX26 */ + + + +// Common to all supported versions of Linux ?? + +#define CKMALLOC(n,f) _ckmalloc(__FUNCTION__, __LINE__, n, f) +#define LSTRDUP(str) _lstrdup(__FUNCTION__, __LINE__, str) +#define LKFREE(p) _lkfree(__FUNCTION__, __LINE__, p) + +#define ckmalloc(n,f) _ckmalloc(__FUNCTION__, __LINE__, n, f) +#define lstrdup(str) _lstrdup(__FUNCTION__, __LINE__, str) +#define lkfree(p) _lkfree(__FUNCTION__, __LINE__, p) + +#define OTG_MALLOC_TEST +#undef OTG_MALLOC_DEBUG + +#ifdef OTG_MALLOC_TEST + extern int otg_mallocs; +#endif + + +static INLINE void *_ckmalloc (const char *func, int line, int n, int f) +{ + void *p; + if ((p = kmalloc (n, f)) == NULL) { + return NULL; + } + memset (p, 0, n); + #ifdef OTG_MALLOC_TEST + ++otg_mallocs; + #endif + #ifdef OTG_MALLOC_DEBUG + printk(KERN_INFO"%s: %p %s %d %d\n", __FUNCTION__, p, func, line, otg_mallocs); + #endif + return p; +} + +static INLINE char *_lstrdup (const char *func, int line, char *str) +{ + int n; + char *s; + if (str && (n = strlen (str) + 1) && (s = kmalloc (n, GFP_ATOMIC))) { +#ifdef OTG_MALLOC_TEST + ++otg_mallocs; +#endif +#ifdef OTG_MALLOC_DEBUG + printk(KERN_INFO"%s: %p %s %d %d\n", __FUNCTION__, s, func, line, otg_mallocs); +#endif + return strcpy (s, str); + } + return NULL; +} + +static INLINE void _lkfree (const char *func, int line, void *p) +{ + if (p) { +#ifdef OTG_MALLOC_TEST + --otg_mallocs; +#endif +#ifdef OTG_MALLOC_DEBUG + printk(KERN_INFO"%s: %p %s %d %d\n", __FUNCTION__, p, func, line, otg_mallocs); +#endif + kfree (p); +#ifdef MALLOC_TEST + if (otg_mallocs < 0) { + printk(KERN_INFO"%s: %p %s %d %d otg_mallocs less zero!\n", __FUNCTION__, p, func, line, otg_mallocs); + } +#endif +#ifdef OTG_MALLOC_DEBUG + else { + printk(KERN_INFO"%s: %s %d NULL\n", __FUNCTION__, func, line); + } +#endif + } +} + +#if 1 +#include +#define LIST_NODE struct list_head +#define LIST_NODE_INIT(name) struct list_head name = {&name, &name} +#define INIT_LIST_NODE(ptr) INIT_LIST_HEAD(ptr) +#define LIST_ENTRY(pointer, type, member) list_entry(pointer, type, member) +#define LIST_FOR_EACH(cursor, head) list_for_each(cursor, head) +#define LIST_ADD_TAIL(n,h) list_add_tail(n,h) +#define LIST_DEL(h) list_del(&(h)) +#else +#include +#endif + +/*! @} */ + + +/*! @name Atomic Operations + * + * atomic_post_inc() + * atomic_pre_dec() + */ +/*! @{ */ +static __inline__ int atomic_post_inc(volatile atomic_t *v) +{ + unsigned long flags; + int result; + local_irq_save(flags); + result = (v->counter)++; + local_irq_restore(flags); + return(result); +} + +static __inline__ int atomic_pre_dec(volatile atomic_t *v) +{ + unsigned long flags; + int result; + local_irq_save(flags); + result = --(v->counter); + local_irq_restore(flags); + return(result); +} +/*! @} */ + + + +/*!@name Scheduling Primitives + * + * WORK_STRUCT + * WORK_ITEM + * + * SCHEDULE_TIMEOUT()\n + * SET_WORK_ARG()\n + * SCHEDULE_WORK()\n + * SCHEDULE_IMMEDIATE_WORK()\n + * NO_WORK_DATA()\n + * MOD_DEC_USE_COUNT\n + * MOD_INC_USE_COUNT\n + */ + +/*! @{ */ + +static void inline SCHEDULE_TIMEOUT(int seconds){ + schedule_timeout( seconds * HZ ); +} + + +/* Separate Linux 2.4 and 2.6 versions of scheduling primitives */ +#if defined(LINUX26) + #include + + #define WORK_STRUCT work_struct + #define WORK_ITEM work_struct + typedef struct WORK_ITEM WORK_ITEM; + #if 0 + #define PREPARE_WORK_ITEM(__item,__routine,__data) INIT_WORK((__item),(__routine),(__data)) + #else + #include + #define PREPARE_WORK_ITEM(__item,__routine,__data) __prepare_work(&(__item),(__routine),(__data)) + static inline void __prepare_work(struct work_struct *_work, + void (*_routine), + void * _data){ + INIT_LIST_HEAD(&_work->entry); + _work->pending = 0; + _work->func = _routine; + _work->data = _data; + init_timer(&_work->timer); + } + #endif + #undef PREPARE_WORK + typedef void (* WORK_PROC)(void *); + + #define SET_WORK_ARG(__item, __data) (__item).data = __data + + #define SCHEDULE_WORK(item) schedule_work(&(item)) + #define SCHEDULE_IMMEDIATE_WORK(item) SCHEDULE_WORK((item)) + #define PENDING_WORK_ITEM(item) ((item).pending != 0) + #define NO_WORK_DATA(item) (!(item).data) + #define _MOD_DEC_USE_COUNT //Not used in 2.6 + #define _MOD_INC_USE_COUNT //Not used in 2.6 + +#else /* LINUX26 */ + + #define WORK_STRUCT tq_struct + #define WORK_ITEM tq_struct + typedef struct WORK_ITEM WORK_ITEM; + #define PREPARE_WORK_ITEM(item,work_routine,work_data) { item.routine = work_routine; item.data = work_data; } + #define SET_WORK_ARG(__item, __data) (__item).data = __data + #define NO_WORK_DATA(item) (!(item).data) + #define SCHEDULE_WORK(item) schedule_task(&(item)) + #define PENDING_WORK_ITEM(item) ((item).sync != 0) + #define _MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT + #define _MOD_INC_USE_COUNT MOD_INC_USE_COUNT + + typedef void (* WORK_PROC)(void *); + + #if !defined(IRQ_HANDLED) + // Irq's + typedef void irqreturn_t; + #define IRQ_NONE + #define IRQ_HANDLED + #define IRQ_RETVAL(x) + #endif +#endif /* LINUX26 */ + +/*! @} */ + +/*!@name Semaphores + * + * up() + * down() + */ +/*! @{ */ +#define UP(s) up(s) +#define DOWN(s) down(s) +/*! @} */ + +/*! @name Printk + * + * PRINTK() + */ +/*! @{ */ +#define PRINTK(s) printk(s) +/*! @} */ + +/*! + * Cache + * @{ + */ +#define CACHE_SYNC_RCV(buf, len) pci_map_single (NULL, (void *) buf, len, PCI_DMA_FROMDEVICE) +#define CACHE_SYNC_TX(buf, len) dma_cache_maint (buf, len, PCI_DMA_TODEVICE) + +/* @} */ + + + +#endif diff -urN linux-2.6.26/drivers/usb/usblan/usblan.c linux-2.6.26-lab126/drivers/usb/usblan/usblan.c --- linux-2.6.26/drivers/usb/usblan/usblan.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/usb/usblan/usblan.c 2010-08-10 04:17:07.000000000 -0400 @@ -0,0 +1,3045 @@ +/* + * USB Host to USB Device Network Function Driver + * + * Copyright (c) 2002, 2003 Belcarra + * Copyright (c) 2001 Lineo + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * By: + * Stuart Lynne , Bruce Balden + * + * Some algorithms adopted from usbnet.c: + * + * Copyright (C) 2000-2001 by David Brownell + * + */ + +#ifdef MODULE +#include +#endif +#include +#include +#include +#include +#include +#include +//#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + + + +//#include "linux-pch.h" + +#include + +#include +#include +#include +#include +#include "usblan-compat.h" +#include "usblan.h" + +#define PACKED_ENUM enum +#define PACKED_ENUM_EXTRA +#define PACKED1 __attribute__((packed)) +#define PACKED2 +#define PACKED0 + + +#if defined(USBLAN_LOCAL_CONFIG) +#include "./usblan-config.h" +#endif + +#define MIN(a,b) (((a) < (b))?(a):(b)) +#define MAX(a,b) (((a) > (b))?(a):(b)) + +#define UNLESS(x) if (!(x)) +#define THROW(x) goto x +#define CATCH(x) while(0) x: +#define THROW_IF(e, x) if (e) { goto x; } +#define THROW_UNLESS(e, x) UNLESS (e) { goto x; } +#define BREAK_IF(x) if (x) { break; } +#define CONTINUE_IF(x) if (x) { continue; } +#define RETURN_IF(x,y) if (y) { return x; } + + +#define mutex_lock(x) down(x) +#define mutex_unlock(x) up(x) + + +#define DRIVER_VERSION "2.0.0" +#define DRIVER_AUTHOR "sl@belcarra.com" +#define DRIVER_DESC "Linux USBLAN driver" + +#ifdef MODULE +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); + +// XXX This needs to be corrected down to the last version of the +// kernel that did NOT have MODULE_LICENSE +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,15) +MODULE_LICENSE("GPL"); +#endif +#endif + +#define STATIC + +/* Module Parameters ************************************************************************* */ + +#define MAX_INTERFACES 1 + +#define MAX_RCV_SKBS 10 +#define TIMEOUT_JIFFIES (4*HZ) +#define MAX_PACKET 32768 +#define MIN_PACKET sizeof(struct ethhdr) + + +#define TX_QLEN 2 +#define RX_QLEN 2 + +static DECLARE_MUTEX(usbd_mutex); // lock for global changes +static LIST_HEAD(usbd_list); // a list for all active devices + + +typedef enum usbdnet_device_type { + usbdnet_unknown, usbdnet_basic, usbdnet_cdc, usbdnet_safe, usbdnet_blan, usbdnet_rndis +} usbdnet_device_type_t; + +char * usbdnet_device_names[] = { + "UNKNOWN", "BASIC", "CDC", "SAFE", "BLAN", "RNDIS", +}; + + + +__u8 SAFE_VERSION[2] = { + 0x00, 0x01, /* BCD Version */ +}; +__u8 SAFE_GUID[16] = { + 0x5d, 0x34, 0xcf, 0x66, 0x11, 0x18, 0x11, 0xd6, /* bGUID */ + 0xa2, 0x1a, 0x00, 0x01, 0x02, 0xca, 0x9a, 0x7f, /* bGUID */ +}; + +__u8 BLAN_VERSION[2] = { + 0x00, 0x01, /* BCD Version */ +}; +__u8 BLAN_GUID[16] = { + 0x74, 0xf0, 0x3d, 0xbd, 0x1e, 0xc1, 0x44, 0x70, /* bGUID */ + 0xa3, 0x67, 0x71, 0x34, 0xc9, 0xf5, 0x54, 0x37, /* bGUID */ +}; + +// data detail +#define DATA_CRC 0x01 +#define DATA_PADBEFORE 0x02 +#define DATA_PADAFTER 0x04 +#define DATA_FERMAT 0x08 + +// cdc notifications +#define CDC_NOTIFICATION 0xa1 +#define CDC_NOTIFICATION_NETWORK 0x00 +#define CDC_NOTIFICATION_SPEEDCHANGE 0x2a + +#define USB_DT_CS_INTERFACE 0x24 + +#define MDLM_FUNCTIONAL 0x12 +#define MDLM_DETAIL 0x13 + +#define MDLM_SAFE_GUID 0x00 +#define MDLM_BLAN_GUID 0x01 + + +#if 0 +STATIC void usblan_test_kalloc(char *msg) +{ + struct urb *foo; + printk(KERN_INFO "%s: %s\n",__FUNCTION__,msg); + if (NULL != (foo = USB_ALLOC_URB(0,GFP_ATOMIC))) { + usb_free_urb(foo); + } + printk(KERN_INFO "%s: #%08x\n",__FUNCTION__,(u32)(void*)foo); +} +#endif + + + +/* struct private + * + * This structure contains the network interface and additional per USB device information. + * + * A pointer to this structure is used in two three places: + * + * net->priv + * urb->context + * skb->cb.priv + */ +struct private { + + // general + struct usb_device *usbdev; // usb core layer provides this for the probed device + struct semaphore mutex; // lock for changes to this structure + struct list_head list; // to maintain a list of these devices () + wait_queue_head_t *wait; + wait_queue_head_t *ctrl_wait; + + struct tasklet_struct bh; + struct WORK_STRUCT crc_task; + struct WORK_STRUCT ctrl_task; + struct WORK_STRUCT reset_task; + struct WORK_STRUCT unlink_task; + + int intf_count; + int intf_max; + + // network + struct net_device net; + struct net_device_stats stats; + unsigned char dev_addr[ETH_ALEN]; + + // queues + struct sk_buff_head rxq; + struct sk_buff_head txq; + struct sk_buff_head unlink; + struct sk_buff_head done; + + // + int crc32; // append and check for appended 32bit CRC + int padded; // pad bulk transfers such that (urb->transfer_buffer_length % data_ep_out_size) == 1 + int addr_set; // set_address + int sawCRC; + + int timeouts; + + usbdnet_device_type_t usbdnet_device_type; + + //struct usb_interface *data_interface; + //struct usb_interface *comm_interface; + + struct usb_ctrlrequest ctrl_request; + struct urb *ctrl_urb; + int configuration_number; + int bConfigurationValue; + + int comm_interface; + int comm_bInterfaceNumber; + int comm_bAlternateSetting; + int comm_ep_in; + int comm_ep_in_size; + + int data_interface; + + int data_bInterfaceNumber; + int data_bAlternateSetting; + + int nodata_bInterfaceNumber; + int nodata_bAlternateSetting; + + int data_ep_in; + int data_ep_out; + int data_ep_in_size; + int data_ep_out_size; + + u8 CRCInUse; + u8 CDC; + u8 bmNetworkCapabilities; + u8 bmDataCapabilities; + u8 bPad; +}; + +/* struct skb_cb + * + * This defines how we use the skb->cb data area. It allows us to get back to the private + * data structure and track the current state of skb in our done queue. There is a pointer + * to the active urb so that it can be cancelled (e.g. tx_timeout). + * + * skb->cb + */ +typedef enum skb_state { + unknown = 0, + tx_start, // an skb in priv->txq + tx_done, // a transmitted skb in priv->done + rx_start, // an skb in priv->rxq + rx_done, // a received skb in priv->done + rx_cleanup, // a received skb being thrown out due to an error condition +} skb_state_t; + +struct skb_cb { + struct private *priv; + struct urb *urb; + skb_state_t state; + unsigned long int jiffies; +}; + + +static struct usb_driver usblan_driver; + + +struct usb_mdlm_detail_descriptor { + u8 bLength; + u8 bDescriptorType; + u8 bDescriptorSubType; + u8 bGuidDescriptorType; +} __attribute__ ((packed)); + +struct usb_safe_detail_descriptor { + u8 bLength; + u8 bDescriptorType; + u8 bDescriptorSubType; + u8 bGuidDescriptorType; + u8 bmNetworkCapabilities; + u8 bmDataCapabilities; +} __attribute__ ((packed)); + +struct usb_blan_detail_descriptor { + u8 bLength; + u8 bDescriptorType; + u8 bDescriptorSubType; + u8 bGuidDescriptorType; + u8 bmNetworkCapabilities; + u8 bmDataCapabilities; + u8 bPad; +} __attribute__ ((packed)); + +struct usb_class_descriptor { + u8 bLength; + u8 bDescriptorType; + u8 bDescriptorSubType; + u8 data[0]; +} __attribute__ ((packed)); + +struct usb_guid_descriptor { + u8 bLength; + u8 bDescriptorType; + u8 bDescriptorSubType; + u8 bGuidDescriptorType; + u8 data[0]; +} __attribute__ ((packed)); + +struct usb_notification_descriptor { + u8 bmRequestType; + u8 bNotification; + u16 wValue; + u16 wIndex; + u16 wLength; + u8 data[2]; +} __attribute__ ((packed)); + +struct usb_speedchange_descriptor { + u8 bmRequestType; + u8 bNotification; + u16 wValue; + u16 wIndex; + u16 wLength; + u32 data[2]; +} __attribute__ ((packed)); + +struct usb_mdlm_functional_descriptor { + u8 bLength; + u8 bDescriptorType; + u8 bDescriptorSubType; + u16 bcdVersion; + u8 bGuid[16]; +} __attribute__ ((packed)); + + + +/* + * default MAC address to use + */ +static unsigned char default_addr[ETH_ALEN]; + +/* Module Parameters ************************************************************************* */ + +#define VENDOR_SPECIFIC_CLASS 0xff +#define VENDOR_SPECIFIC_SUBCLASS 0xff +#define VENDOR_SPECIFIC_PROTOCOL 0xff + +#define MTU 1500+100 + + +#if defined(CONFIG_USBD_USBLAN_VENDOR) && !defined(CONFIG_USBD_USBLAN_PRODUCT) +#abort "USBLAN_VENDOR defined without USBLAN_PRODUCT" +#endif + +#define CDC_DEVICE_CLASS 0x02 // Device descriptor Class + +#define CDC_INTERFACE_CLASS 0x02 // CDC interface descriptor Class +#define CDC_INTERFACE_SUBCLASS 0x06 // CDC interface descriptor SubClass +#define RNDIS_INTERFACE_SUBCLASS 0x02 // CDC interface descriptor SubClass +#define MDLM_INTERFACE_SUBCLASS 0x0a // CDC interface descriptor SubClass + +#define DATA_INTERFACE_CLASS 0x0a // Data interface descriptor Class + +#define DEFAULT_PROTOCOL 0x00 +#define VENDOR_SPECIFIC_PROTOCOL 0xff + +#define LINEO_INTERFACE_CLASS 0xff // Lineo private interface descriptor Class + +#define LINEO_INTERFACE_SUBCLASS_SAFENET 0x01 // Lineo private interface descriptor SubClass +#define LINEO_INTERFACE_SUBCLASS_SAFESERIAL 0x02 + +#define LINEO_SAFENET_CRC 0x01 // Lineo private interface descriptor Protocol +#define LINEO_SAFENET_CRC_PADDED 0x02 // Lineo private interface descriptor Protocol + +#define LINEO_SAFESERIAL_CRC 0x01 +#define LINEO_SAFESERIAL_CRC_PADDED 0x02 + + +#define NETWORK_ADDR_HOST 0xac100005 /* 172.16.0.0 */ +#define NETWORK_ADDR_CLIENT 0xac100006 /* 172.16.0.0 */ +#define NETWORK_MASK 0xfffffffc + + +static __u32 vendor_id; // no default +static __u32 product_id; // no default +static __u32 class = LINEO_INTERFACE_CLASS; +static __u32 subclass = LINEO_INTERFACE_SUBCLASS_SAFENET; + +static __u32 echo_fcs; // no default +static __u32 noisy_fcs; // no default +static __u32 echo_rx; // no default +static __u32 echo_tx; // no default + +#ifdef MODULE +MODULE_PARM_DESC(vendor_id, "User specified USB idVendor"); +MODULE_PARM_DESC(product_id, "User specified USB idProduct"); +MODULE_PARM_DESC(class, "User specified USB Class"); +MODULE_PARM_DESC(subclass, "User specified USB SubClass"); +MODULE_PARM(vendor_id, "i"); +MODULE_PARM(product_id, "i"); +MODULE_PARM(class, "i"); +MODULE_PARM(subclass, "i"); + +MODULE_PARM_DESC(echo_tx, "echo TX urbs"); +MODULE_PARM_DESC(echo_rx, "echo RCV urbs"); +MODULE_PARM_DESC(echo_fcs, "BAD FCS"); +MODULE_PARM_DESC(noisy_fcs, "BAD FCS info"); +MODULE_PARM(echo_tx, "i"); +MODULE_PARM(echo_rx, "i"); +MODULE_PARM(echo_fcs, "i"); +MODULE_PARM(noisy_fcs, "i"); +#endif + +//match_flags: DEVICE_ID_MATCH_DEVICE | USB_DEVICE_ID_MATCH_DEV_CLASS , + +#define MY_USB_DEVICE(vend,prod) \ +match_flags: USB_DEVICE_ID_MATCH_DEVICE , \ +idVendor: (vend), \ +idProduct: (prod),\ +bDeviceClass: (CDC_INTERFACE_CLASS), + +static __devinitdata struct usb_device_id id_table[] = { + + // RNDIS devices Vend Prod bDeviceClass bInterfaceClass bInterfaceSubClass + + {MY_USB_DEVICE(0x15ec, 0xf001)}, // Belcarra Network Demo + {MY_USB_DEVICE(0x12b9, 0xf001)}, // Belcarra Network Demo + + +#if 1 +#if defined(CONFIG_USB_USBLAN_VENDORID) && defined(CONFIG_USB_USBLAN_PRODUCTID) + // A configured driver + {MY_USB_DEVICE(CONFIG_USB_USBLAN_VENDORID, CONFIG_USB_USBLAN_PRODUCTID)}, +#endif +#endif + + // extra null entry for module vendor_id/produc parameters and terminating entry + {}, {}, +}; + + +#ifdef MODULE +MODULE_DEVICE_TABLE(usb, id_table); +#endif + +#define ECHO_FCS +#define ECHO_RCV + +#undef ECHO_TX_SKB +#define ECHO_TX_URB + +__u32 crc32_table[256] = { + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, + 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, + 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, + 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, + 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, + 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, + 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, + 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, + 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, + 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, + 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, + 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, + 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, + 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, + 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, + 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, + 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, + 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, + 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, + 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, + 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, + 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d +}; + +#define CRC32_INITFCS 0xffffffff // Initial FCS value +#define CRC32_GOODFCS 0xdebb20e3 // Good final FCS value + +#define CRC32_FCS(fcs, c) (((fcs) >> 8) ^ crc32_table[((fcs) ^ (c)) & 0xff]) + +/* fcs_memcpy32 - memcpy and calculate fcs + * Perform a memcpy and calculate fcs using ppp 32bit CRC algorithm. + */ +static __u32 __inline__ +fcs_memcpy32(unsigned char *dp, unsigned char *sp, int len, __u32 fcs) +{ + for (; len-- > 0; fcs = CRC32_FCS(fcs, *dp++ = *sp++)); + return fcs; +} + +/* fcs_pad32 - pad and calculate fcs + * Pad and calculate fcs using ppp 32bit CRC algorithm. + */ +static __u32 __inline__ +fcs_pad32(unsigned char *dp, int len, __u32 fcs) +{ + for (; len-- > 0; fcs = CRC32_FCS(fcs, *dp++ = '\0')); + return fcs; +} + +/* fcs_compute32 - memcpy and calculate fcs + * Perform a memcpy and calculate fcs using ppp 32bit CRC algorithm. + */ +static __u32 __inline__ +fcs_compute32(unsigned char *sp, int len, __u32 fcs) +{ + for (; len-- > 0; fcs = CRC32_FCS(fcs, *sp++)); + return fcs; +} + +void +wait_for_sync(struct WORK_STRUCT *tq) +{ + + // wait for pending bottom halfs to exit + while (PENDING_WORK_ITEM((*tq))){ + SCHEDULE_TIMEOUT(1); + } + + tq->data = 0; + + while (PENDING_WORK_ITEM((*tq))) { + SCHEDULE_TIMEOUT(1); + } +} + + +#define RETRYTIME 2 + +void +skb_bad_crc(struct sk_buff *skb, __u32 fcs) +{ +#ifdef ECHO_FCS + if (noisy_fcs) { + printk(KERN_INFO"%s: BAD FCS len: %4d crc: %08x last: %02x %02x %02x %02x\n", __FUNCTION__, + skb->len, fcs, skb->data[skb->len - 4], + skb->data[skb->len - 3], skb->data[skb->len - 2], skb->data[skb->len - 1] + ); + } + if (echo_fcs) { + int i; + unsigned char *cp = skb->data; + printk(KERN_INFO "%s: FAILED skb: %p head: %p data: %p tail: %p len: %d", __FUNCTION__, + skb, skb->head, skb->data, skb->tail, skb->len); + for (i = 0; i < skb->len; i++) { + if ((i % 32) == 0) { + printk("\nrcv[%02x]: ", i); + } + printk("%02x ", cp[i]); + } + printk("\n"); + } +#endif +} + +#if 0 +static void +dump_skb(struct sk_buff *skb, char *msg) +{ + int i; + unsigned char *cp = skb->data; + + printk(KERN_INFO "\n%s", msg); + for (i = 0; i < skb->len; i++) { + if (!(i % 32)) { + printk("\n[%02x] ", i); + } + printk("%02x ", cp[i]); + } + printk("\n"); +} +#endif + +/* ********************************************************************************************* */ +#if defined(LONG_STRING_OF_ZEROES_HACK) + +/* fermat + * + * This is a hack designed to help some broken hardware that cannot successfully + * transmit long strings of zero's without causing the host port to signal a + * status change and drop the connection. + * + */ + +typedef unsigned char BYTE; +typedef struct fermat { + int length; + BYTE power[256]; +} FERMAT; + +STATIC void fermat_init(void); +STATIC void fermat_encode(BYTE *data, int length); +STATIC void fermat_decode(BYTE *data, int length); + +STATIC int fermat_setup(FERMAT *p, int seed){ + int i = 0; + unsigned long x,y; + y = 1; + do{ + x = y; + p->power[i] = ( x == 256 ? 0 : x); + y = ( seed * x ) % 257; + i += 1; + }while( y != 1); + p->length = i; + return i; +} + +STATIC void fermat_xform(FERMAT *p, BYTE *data, int length){ + BYTE *pw = p->power; + int i, j; + BYTE * q ; + for(i = 0, j=0, q = data; i < length; i++, j++, q++){ + if(j>=p->length){ + j = 0; + } + *q ^= pw[j]; + } +} + +static FERMAT default_fermat; +static const int primitive_root = 5; +STATIC void fermat_init(){ + (void) fermat_setup(&default_fermat, primitive_root); +} + +// Here are the public official versions. +// Change the primitive_root above to another primitive root +// if you need better scatter. Possible values are 3 and 7 + + +STATIC void fermat_encode(BYTE *data, int length){ + fermat_xform(&default_fermat, data, length); +} + +STATIC void fermat_decode(BYTE *data, int length){ + fermat_xform(&default_fermat, data, length); +} +#endif + + +/* ********************************************************************************************* */ + +STATIC void defer_skb(struct private *priv, struct sk_buff *skb, struct skb_cb *cb, + skb_state_t state, struct sk_buff_head *list); +STATIC int unlink_urbs(struct sk_buff_head *q); +STATIC void urb_tx_complete(struct urb *urb); +STATIC void urb_rx_complete(struct urb *urb); +#if 0 +STATIC void urb_dead_complete(struct urb *urb); +#endif + + +/* Network Configuration *********************************************************************** */ + +/* sock_ioctl - perform an ioctl call to inet device + */ +static int sock_ioctl(u32 cmd, struct ifreq *ifreq) +{ + int rc = 0; + mm_segment_t save_get_fs = get_fs(); + //printk(KERN_INFO"%s: cmd: %x\n", __FUNCTION__, cmd); + set_fs(get_ds()); + rc = devinet_ioctl(cmd, ifreq); + set_fs(save_get_fs); + return rc; +} + +/* sock_addr - setup a socket address for specified interface + */ +static int sock_addr(char * ifname, u32 cmd, u32 s_addr) +{ + struct ifreq ifreq; + struct sockaddr_in *sin = (void *) &(ifreq.ifr_ifru.ifru_addr); + + //printk(KERN_INFO"%s: ifname: %s addr: %x\n", __FUNCTION__, ifname, ntohl(s_addr)); + + memset(&ifreq, 0, sizeof(ifreq)); + strcpy(ifreq.ifr_ifrn.ifrn_name, ifname); + + sin->sin_family = AF_INET; + sin->sin_addr.s_addr = s_addr; + + return sock_ioctl(cmd, &ifreq); +} + + +/* sock_flags - set flags for specified interface + */ +static int sock_flags(char * ifname, u16 oflags, u16 sflags, u16 rflags) +{ + int rc = 0; + struct ifreq ifreq; + + //printk(KERN_INFO"%s: ifname: %s oflags: %x s_flags: %x r_flags: %x\n", __FUNCTION__, ifname, oflags, sflags, rflags); + + memset(&ifreq, 0, sizeof(ifreq)); + strcpy(ifreq.ifr_ifrn.ifrn_name, ifname); + + oflags |= sflags; + oflags &= ~rflags; + ifreq.ifr_flags = oflags; + + //printk(KERN_INFO"%s: -> ifr_flags: %x \n", __FUNCTION__, ifreq.ifr_flags); + + THROW_IF ((rc = sock_ioctl(SIOCSIFFLAGS, &ifreq)), error); + + //printk(KERN_INFO"%s: <- ifr_flags: %x \n", __FUNCTION__, ifreq.ifr_flags); + + CATCH(error) { + printk(KERN_INFO"%s: ifconfig: cannot get/set interface flags (%d)\n", __FUNCTION__, rc); + return rc; + } + return rc; +} + +/* network_attach - configure interface + * + * This will use socket calls to configure the interface to the supplied + * ip address and make it active. + */ +STATIC int network_attach(struct net_device *net, u32 host_ip, u32 mask, int attach) +{ + int err = 0; + + //printk(KERN_INFO"%s: net: %p host_ip: %08x mask: %08x attach: %d\n", __FUNCTION__, net, host_ip, mask, attach); + if (attach) { + u16 oflags = net ? net->flags : 0; + + /* setup host_ip address, netwask, and broadcast address */ + if (host_ip) { + THROW_IF ((err = sock_addr(net->name, SIOCSIFADDR, htonl(host_ip))), error); + if (mask) { + THROW_IF ((err = sock_addr(net->name, SIOCSIFNETMASK, htonl(mask))), error); + THROW_IF ((err = sock_addr(net->name, SIOCSIFBRDADDR, htonl(host_ip | ~mask))), error); + } + /* bring the interface up */ + THROW_IF ((err = sock_flags(net->name, oflags, IFF_UP, 0)), error); + } + + + } + else { + u16 oflags = net ? net->flags : 0; + /* bring the interface down */ + THROW_IF ((err = sock_flags(net->name, oflags, 0, IFF_UP)), error); + } + + CATCH(error) { + printk(KERN_INFO"%s: ifconfig: cannot configure interface (%d)\n", __FUNCTION__, err); + return err; + } + return 0; +} + + +/* ********************************************************************************************* */ + +/* Network Support Functions - these are called by the network layer *************************** */ + +/* net_get_stats - network device get stats function + * Retreive network device stats structure. + */ +STATIC struct net_device_stats * +net_get_stats(struct net_device *net) +{ + struct private *priv = (struct private *) net->priv; + //printk(KERN_INFO "%s:\n", __FUNCTION__); + return &priv->stats; +} + +/* net_set_mac_addr - network device set mac address function + */ +STATIC int +net_set_mac_address(struct net_device *net, void *p) +{ + struct private *priv = (struct private *) net->priv; + struct sockaddr *addr = p; + + //printk(KERN_INFO "%s:\n", __FUNCTION__); + if (netif_running(net)) { + return -EBUSY; + } + memcpy(net->dev_addr, addr->sa_data, net->addr_len); + priv->addr_set = 1; + return 0; +} + +/* net_change_mtu - network device set config function + * Set MTU, if running we can only change it to something less + * than or equal to MTU when PVC opened. + */ +STATIC int +net_change_mtu(struct net_device *net, int mtu) +{ + //printk(KERN_INFO "%s:\n", __FUNCTION__); + if ((mtu < sizeof(struct ethhdr)) || (mtu > (MAX_PACKET - 4))) { + return -EINVAL; + } + if (netif_running(net)) { + if (mtu > net->mtu) { + return -EBUSY; + } + } + net->mtu = mtu; + return 0; +} + +/* net_open - called by network layer to open network interface + */ +STATIC int +net_open(struct net_device *net) +{ + struct private *priv = (struct private *) net->priv; + + //printk(KERN_INFO "%s: priv#%08x net#%08x\n",__FUNCTION__,(u32)(void*)priv,(u32)(void*)net); + mutex_lock(&priv->mutex); + //printk(KERN_INFO "%s: AAA usbdev#%08x dataIF=%d alt=%d\n",__FUNCTION__,(u32)(void*)priv->usbdev, priv->data_bInterfaceNumber, priv->data_bAlternateSetting); + + // enable traffic + //printk(KERN_INFO"%s: setting data interface bInterfaceNumber: %d bAlternateSetting: %d\n", __FUNCTION__, + // priv->data_bInterfaceNumber, priv->data_bAlternateSetting); + +#if defined(LINUX24) + if (usb_set_interface( priv->usbdev, priv->data_bInterfaceNumber, priv->data_bAlternateSetting)) { + err("usb_set_interface() failed"); + } +#endif + + // XXX find interface ip / netmask, if netmask is 255.255.255.252 + // then send ip and ip+1 to device as suggested addresses + + + + + //printk(KERN_INFO "%s: BBB\n",__FUNCTION__); + + // tell the network layer to enable transmit queue + netif_start_queue(net); + //printk(KERN_INFO "%s: BBB\n",__FUNCTION__); + + // call the bottom half to schedule some receive urbs + tasklet_schedule(&priv->bh); + //printk(KERN_INFO "%s: CCC\n",__FUNCTION__); + + mutex_unlock(&priv->mutex); + //printk(KERN_INFO "%s: DDD\n",__FUNCTION__); + return 0; +} + +/* net_stop - called by network layer to stop network interface + */ +STATIC int +net_stop(struct net_device *net) +{ + struct private *priv = (struct private *) net->priv; + + DECLARE_WAIT_QUEUE_HEAD(unlink_wakeup); + DECLARE_WAITQUEUE(wait, current); + + //printk(KERN_INFO "%s:\n",__FUNCTION__); + + mutex_lock(&priv->mutex); + + // tell the network layer to disable the transmit queue + netif_stop_queue(net); + + + // disable (if possible) network traffic + if (priv->nodata_bInterfaceNumber >= 0) { + + //printk(KERN_INFO"%s: setting nodata interface bInterfaceNumber: %d bAlternateSetting: %d\n", __FUNCTION__, + // priv->nodata_bInterfaceNumber, priv->nodata_bAlternateSetting); + + if (usb_set_interface( priv->usbdev, priv->nodata_bInterfaceNumber, priv->nodata_bAlternateSetting)) { + err("usb_set_interface() failed"); + } + } + + + // setup a wait queue - this also acts as a flag to prevent bottom half from allocating more urbs + add_wait_queue(&unlink_wakeup, &wait); + priv->wait = &unlink_wakeup; + + // move the tx and rx urbs into the done queue + unlink_urbs(&priv->txq); + unlink_urbs(&priv->rxq); + + // wait for done queue to empty + while (skb_queue_len(&priv->rxq) || skb_queue_len(&priv->txq) || skb_queue_len(&priv->done)) { + current->state = TASK_UNINTERRUPTIBLE; + schedule_timeout(TIMEOUT_JIFFIES * 1000); + } + priv->wait = 0; + + // cleanup + remove_wait_queue(&unlink_wakeup, &wait); + + mutex_unlock(&priv->mutex); + return 0; +} + + +/* net_tx_timeout - called by network layer to cancel outstanding skbs + */ +STATIC void +net_tx_timeout(struct net_device *net) +{ + //struct private *priv = (struct private *) net->priv; + //unsigned char *cp; + //struct urb *urb; + + //unsigned char deadbeef[] = "DEADBEEF"; + + //printk(KERN_INFO"%s:\n", __FUNCTION__); + //unlink_urbs(&priv->txq); + //tasklet_schedule(&priv->bh); + + //if (priv->unlink_task.sync == 0) { + // schedule_task(&priv->unlink_task); + //} + + return; +#if 0 + // Attempt to send a short usb packet to the device, this will ensure that + // any partially completed bulk transfer will be terminated. + + if (!(cp = kmalloc(sizeof(deadbeef), GFP_KERNEL))) { + return; + } + if (!(urb = USB_ALLOC_URB(0,GFP_ATOMIC))) { + kfree(cp); + return; + } + memcpy(cp, deadbeef, sizeof(deadbeef)); + + FILL_BULK_URB(urb, priv->usbdev, usb_sndbulkpipe(priv->usbdev, priv->data_ep_out), + cp, sizeof(deadbeef), urb_dead_complete, NULL); + + urb->transfer_flags = USB_QUEUE_BULK | USB_ASYNC_UNLINK | USB_NO_FSBR; + + //usb_endpoint_running(priv->usbdev, usb_pipeendpoint(priv->data_ep_out), usb_pipeout(priv->data_ep_out)); + //usb_settoggle(priv->usbdev, usb_pipeendpoint(priv->data_ep_out), usb_pipeout(priv->data_ep_out), 0); + + if (usb_submit_urb(urb)) { + kfree(cp); + urb->transfer_buffer = NULL; + usb_free_urb(urb); + } +#endif +} + +/* net_hard_start_xmit - called by network layer to transmit skb + */ +STATIC int +net_hard_start_xmit(struct sk_buff *skb, struct net_device *net) +{ + struct private *priv = (struct private *) net->priv; + struct urb *urb; + struct skb_cb *cb; + struct sk_buff *skb2; + int flags = in_interrupt()? GFP_ATOMIC : GFP_KERNEL; + __u32 fcs; + int length; + int pad; + + //printk(KERN_INFO "%s:\n",__FUNCTION__); + + echo_tx = 0; + // debug + if (echo_tx) { + int i; + unsigned char *cp = skb->data; + printk(KERN_INFO"%s: skb: %p %d\n", __FUNCTION__, skb, skb->len); + for (i = 0; i < skb->len; i++) { + if ((i % 32) == 0) { + printk("\ntx[%3x]: ", i); + } + printk("%02x ", cp[i]); + } + printk("\n"); + } + + // allocate urb + THROW_IF (priv->wait || !(urb = USB_ALLOC_URB(0,flags)), free_skb_only); + + // calculate length required + if (priv->bmDataCapabilities & (DATA_PADBEFORE | DATA_PADAFTER)) { + // we need to pad so that after appending the CRC we have a multiple of packetsize + length = priv->data_ep_out_size * (((skb->len + 4 + 1) / priv->data_ep_out_size) + 1); + } + else { + // require a minimum of one full packet + length = MAX(priv->data_ep_out_size, skb->len + 4 + 1); + } + + // allocate a new skb, copy data to it computing FCS, + // the extra bytes are for the CRC and optional pad byte + THROW_IF (!(skb2 = alloc_skb(length + 4, flags)), free_urb_and_skb); // XXX +4 ? + + if (priv->bmDataCapabilities & DATA_CRC) { + + fcs = fcs_memcpy32(skb_put(skb2, skb->len), skb->data, skb->len, CRC32_INITFCS); + + //dump_skb(skb, "skb"); + dev_kfree_skb_any(skb); + skb = skb2; + + if (priv->bmDataCapabilities & DATA_PADBEFORE) { + if ((pad = (length - skb->len - 4)) > 0) { + // pad to required length less four (CRC), copy fcs and append pad byte if required + fcs = fcs_pad32(skb_put(skb, pad), pad, fcs); + } + } + + fcs = ~fcs; + *skb_put(skb, 1) = fcs & 0xff; + *skb_put(skb, 1) = (fcs >> 8) & 0xff; + *skb_put(skb, 1) = (fcs >> 16) & 0xff; + *skb_put(skb, 1) = (fcs >> 24) & 0xff; + + if (priv->bmDataCapabilities & DATA_PADAFTER) { + while ((skb->len % priv->bPad) || !(skb->len % priv->data_ep_out_size)) skb_put(skb, 1); + } + + // append a byte if required, we overallocated by one to allow for this + else if (!(skb->len % priv->data_ep_out_size)) { + *skb_put(skb, 1) = 0; + } + + //dump_skb(skb, "skb with CRC"); + + } + else { + memcpy(skb_put(skb2, skb->len), skb->data, skb->len); + + //dump_skb(skb, "skb"); + dev_kfree_skb_any(skb); + skb = skb2; + + if (!(skb->len % priv->data_ep_out_size)) { + *skb_put(skb, 1) = 0; + } + } + + // hand urb off to usb layer + + cb = (struct skb_cb *) skb->cb; + cb->urb = urb; + cb->priv = priv; + cb->state = tx_start; + cb->jiffies = jiffies; + + // urb->context ends up with pointer to skb + FILL_BULK_URB(urb, priv->usbdev, usb_sndbulkpipe(priv->usbdev, priv->data_ep_out), skb->data, skb->len, + urb_tx_complete, skb); + + urb->transfer_flags = USB_QUEUE_BULK | USB_ASYNC_UNLINK | USB_NO_FSBR; +#if defined(LINUX24) + urb->timeout = 2; +#endif /* XXX FIX ME */ + + + // submit the urb and restart (or not) the network device queue + //printk(KERN_INFO"%s: skb: %p %d urb %p len: %d\n", __FUNCTION__, skb, skb->len, urb, urb->transfer_buffer_length); + + if (USB_SUBMIT_URB(urb)) { + netif_start_queue(net); + priv->stats.tx_dropped++; + usb_free_urb(urb); + THROW(free_urb_and_skb); + } + skb_queue_tail(&priv->txq, skb); + if (priv->txq.qlen < TX_QLEN) { + netif_start_queue(net); + } + else { + net->trans_start = jiffies; + } + CATCH(free_skb_only) { + CATCH(free_urb_and_skb) { + usb_free_urb(urb); + } + dev_kfree_skb_any(skb); + return NET_XMIT_DROP; + } + return NET_XMIT_SUCCESS; +} + + +/* Receive Related ***************************************************************************** */ + +/* rx_submit - queue an urb to receive data + */ +STATIC void +rx_submit(struct private *priv, struct urb *urb, int gpf) +{ + struct sk_buff *skb; + struct skb_cb *cb; + unsigned long flags; + int size; + + //printk(KERN_INFO "%s:\n",__FUNCTION__); + + //usblan_test_kalloc("AAA"); + size = ((priv->net.mtu + 14 + 4 + priv->data_ep_in_size) / priv->data_ep_in_size) * priv->data_ep_in_size; + + //printk(KERN_INFO"%s: ep_in: %d ep_in_size: %d size: %d urb#%08x\n", __FUNCTION__, + // priv->data_ep_in, priv->data_ep_in_size, size, (u32)(void*)urb); + + //TBR-32-bit if (!(skb = alloc_skb(size + 2, gpf))) { + if (!(skb = alloc_skb(size + 4, gpf))) { + //printk(KERN_INFO "%s: alloc_skb() failed.\n",__FUNCTION__); + dbg("no rx skb"); + tasklet_schedule(&priv->bh); + THROW(free_urb_only); + return; + } + //TBR-32-bit skb_reserve(skb, 2); + skb_reserve(skb, 4); + //usblan_test_kalloc("BBB"); + + cb = (struct skb_cb *) skb->cb; + cb->priv = priv; + cb->urb = urb; + cb->state = rx_start; + //usblan_test_kalloc("CCC"); + + //printk(KERN_INFO"%s: AAA\n", __FUNCTION__); + // urb->context ends up with pointer to skb + FILL_BULK_URB(urb, priv->usbdev, usb_rcvbulkpipe(priv->usbdev, priv->data_ep_in), skb->data, size, urb_rx_complete, skb); + //usblan_test_kalloc("DDD"); + + urb->transfer_flags |= USB_QUEUE_BULK; + + //printk(KERN_INFO"%s: BBB\n", __FUNCTION__); + spin_lock_irqsave(&priv->rxq.lock, flags); + //printk(KERN_INFO"%s: CCC\n", __FUNCTION__); + if (netif_running(&priv->net)) { + + //printk(KERN_INFO"%s: DDD urb %p\n", __FUNCTION__, urb); + //usblan_test_kalloc("EEE"); + + //printk(KERN_INFO "%s: starting URB #%08x\n",__FUNCTION__,(u32)(void*)urb); + + spin_unlock_irqrestore(&priv->rxq.lock, flags); + if (USB_SUBMIT_URB(urb)) { + //printk(KERN_INFO "%s: submit failed freeing URB: %p\n", __FUNCTION__, urb); + //usblan_test_kalloc("FFF"); + tasklet_schedule(&priv->bh); + THROW(free_urb_and_skb); + } + else { + //printk(KERN_INFO"%s: FFF skb %p\n", __FUNCTION__, skb); + __skb_queue_tail(&priv->rxq, skb); + } + //printk(KERN_INFO"%s: GGG urb %p\n", __FUNCTION__, urb); + //usblan_test_kalloc("GGG"); + } + else { + spin_unlock_irqrestore(&priv->rxq.lock, flags); + //printk(KERN_INFO "%s: network stopped, freeing urb: %p\n", __FUNCTION__, urb); + THROW(free_urb_and_skb); + } + + CATCH(free_urb_only) { + + CATCH(free_urb_and_skb) { + printk(KERN_INFO"%s: error freeing skb %p\n", __FUNCTION__, skb); + dev_kfree_skb_any(skb); + } + printk(KERN_INFO"%s: error freeing urb %p\n", __FUNCTION__, urb); + usb_free_urb(urb); + } +} + +/* urb_rx_complete - called by usb core layer when urb has been received + */ +STATIC void +urb_rx_complete(struct urb *urb) +{ + struct sk_buff *skb; + struct skb_cb *cb; + struct private *priv; + + //printk(KERN_INFO "%s: urb %p len: %d status=%d\n", __FUNCTION__, urb, urb->actual_length,urb->status); + + if (!(skb = (struct sk_buff *) urb->context)) { + printk(KERN_ERR "%s: skb NULL\n", __FUNCTION__); + } + if (!(cb = (struct skb_cb *) skb->cb)) { + printk(KERN_ERR "%s: cb NULL\n", __FUNCTION__); + } + if (!(priv = cb->priv)) { + printk(KERN_ERR "%s: priv NULL\n", __FUNCTION__); + } + + + switch (urb->status) { + case 0: + priv->timeouts = 0; + + if ((MIN_PACKET < urb->actual_length) && (urb->actual_length < MAX_PACKET)) { + cb->urb = NULL; + skb_put(skb, urb->actual_length); + defer_skb(priv, skb, cb, rx_done, &priv->rxq); + if (netif_running(&priv->net)) { + rx_submit(priv, urb, GFP_ATOMIC); + } + break; + } + + /* FALLTHROUGH */ + + case -EOVERFLOW: + priv->stats.rx_over_errors++; + case -EILSEQ: + case -ECONNABORTED: + case -ETIMEDOUT: + priv->timeouts++; + priv->stats.rx_dropped++; + //printk(KERN_INFO"%s: RX_CLEANUP urb->status: %d timeout: %d\n", __FUNCTION__, urb->status, priv->timeouts); + defer_skb(priv, skb, cb, rx_cleanup, &priv->rxq); + + // XXX provisional, this will attempt to force a reset for a device that + // there have been multiple receive timeouts. This is a host + // that is no longer responding to IN with a NAK. Typically this is + // due to a device that has stopped operation without dropping the + // usb control resistor to tell us. + + if (priv->timeouts > 20) { + priv->timeouts = 0; + //printk(KERN_INFO "%s: scheduling reset task\n", __FUNCTION__); + +#if 0 + if (priv->reset_task.sync == 0) { + schedule_task(&priv->reset_task); +#else + if(!PENDING_WORK_ITEM(priv->reset_task)){ + SCHEDULE_WORK(priv->reset_task); +#endif + } + } + break; + } +} + + +/* bh_rx_process - called by bottom half to process received skb + */ +STATIC inline void +bh_rx_process(struct private *priv, struct sk_buff *skb) +{ + __u32 fcs; + +#if 0 + if (skb->len > (priv->net.mtu + 16 + 4 + 1 + 100)) { + printk(KERN_INFO "%s: URB too large\n", __FUNCTION__); + priv->stats.rx_length_errors++; + THROW(crc_error); + dev_kfree_skb(skb); + priv->stats.rx_errors++; + return; + } +#endif +#if 0 + if (priv->bmDataCapabilities & DATA_FERMAT) { + fermat_decode(skb->data, skb->len); + } +#endif + //printk(KERN_INFO "%s:\n",__FUNCTION__); + if (priv->bmDataCapabilities & DATA_CRC) { + + // check if we need to check for extra byte + if ((skb->len % priv->data_ep_in_size) == 1) { + + // check fcs across length minus one bytes + if ((fcs = fcs_compute32(skb->data, skb->len - 1, CRC32_INITFCS)) == CRC32_GOODFCS) { + // success, trim extra byte and fall through + skb_trim(skb, skb->len - 1); + + priv->sawCRC = 1; + } + // failed, check additional byte + else if ((fcs = fcs_compute32(skb->data + skb->len - 1, 1, fcs)) != CRC32_GOODFCS) { + // failed + printk(KERN_INFO "%s: CRC fail on extra byte\n", __FUNCTION__); + THROW_IF(priv->sawCRC, crc_error); + return; + } + // success fall through, possibly with corrected length + } + // normal check across full frame + else if ((fcs = fcs_compute32(skb->data, skb->len, CRC32_INITFCS)) != CRC32_GOODFCS) { + printk(KERN_INFO "%s: CRC fail len: %d\n", __FUNCTION__, skb->len); + THROW_IF(priv->sawCRC, crc_error); + return; + } + + // trim fcs + skb_trim(skb, skb->len - 4); + } + + // debug + echo_rx = 0; + if (echo_rx) { + int i; + unsigned char *cp = skb->data; + + for (i = 0; i < skb->len; i++) { + if ((i % 32) == 0) { + printk("\nrx[%3x]: ", i); + } + printk("%02x ", cp[i]); + } + printk("\n"); + } + + // push the skb up + memset(skb->cb, 0, sizeof(struct skb_cb)); + skb->dev = &priv->net; + skb->protocol = eth_type_trans(skb, &priv->net); + skb->pkt_type = PACKET_HOST; + skb->ip_summed = CHECKSUM_UNNECESSARY; + priv->stats.rx_packets++; + priv->stats.rx_bytes += skb->len; + if (netif_rx(skb)) { + printk(KERN_INFO "%s: submitting skb failed\n", __FUNCTION__); + } + + CATCH(crc_error) { + dev_kfree_skb_any(skb); + priv->stats.rx_errors++; + } +} + + +/* Transmit Related **************************************************************************** */ + +/* This is a version of usb_clear_halt() that doesn't read the status from + * the device -- this is because some devices crash their internal firmware + * when the status is requested after a halt + */ +STATIC int +local_clear_halt(struct usb_device *dev, int pipe) +{ + int result; + int endp = usb_pipeendpoint(pipe) | (usb_pipein(pipe) << 7); + + if ((result = usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_CLEAR_FEATURE, USB_RECIP_ENDPOINT, 0, endp, NULL, 0, HZ * 3))) + { + return result; + } + + // reset the toggles and endpoint flags + // usb_endpoint_running(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); + // usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 0); + + return 0; +} + +/* ctrl_task - called as kernel task to send clear halt message + */ +STATIC void +ctrl_task(void *data) +{ + struct private *priv = (struct private *) data; + + local_clear_halt(priv->usbdev, usb_sndbulkpipe(priv->usbdev, priv->data_ep_out)); + netif_wake_queue(&priv->net); +} + +/* reset_task - called as kernel task to send reset the device + */ +STATIC void +reset_task(void *data) +{ + struct private *priv = (struct private *) data; + + if (usb_reset_device(priv->usbdev)) { + printk(KERN_INFO "%s: reset failed\n", __FUNCTION__); + } +} + +/* urb_tx_complete - called by usb core layer when network skb urb has been transmitted + */ +STATIC void +urb_tx_complete(struct urb *urb) +{ + struct sk_buff *skb; + + //printk(KERN_INFO"%s: urb: %p\n", __FUNCTION__, urb); + + if (urb->status) { + printk(KERN_INFO "%s: urb: %p status: %d\n", __FUNCTION__, urb, urb->status); + } + + urb->dev = 0; + + if ((skb = urb->context)) { + struct skb_cb *cb; + struct private *priv; + + if (!(cb = (struct skb_cb *) skb->cb)) { + printk(KERN_ERR "%s: cb NULL skb: %p\n", __FUNCTION__, skb); + } + if (!(priv = cb->priv)) { + printk(KERN_ERR "%s: priv NULL skb: %p cb: %p\n", __FUNCTION__, skb, cb); + } + + if (!cb->urb) { + printk(KERN_ERR "%s: urb NULL skb: %p cb: %p\n", __FUNCTION__, skb, cb); + } + + if (cb->urb != urb) { + printk(KERN_ERR "%s: urb not urb skb: %p cb: %p cb->urb: %p urb: %p\n", __FUNCTION__, + skb, cb, cb->urb, urb); + } + + if (urb->status == USB_ST_STALL) { + printk(KERN_ERR "%s: USB_ST_STALL\n", __FUNCTION__); +#if defined(LINUX24) + if (priv->ctrl_task.sync == 0) { + schedule_task(&priv->ctrl_task); + } +#else + if (!PENDING_WORK_ITEM(priv->ctrl_task)){ + SCHEDULE_WORK(priv->ctrl_task); + } +#endif + + } + defer_skb(priv, skb, cb, tx_done, &priv->txq); + } +} + +#if 0 +/* urb_dead_complete - called by usb core layer when deadbeef urb has been transmitted + */ +STATIC void +urb_dead_complete(struct urb *urb) +{ + urb->dev = 0; + + if (urb->transfer_buffer) { + kfree(urb->transfer_buffer); + urb->transfer_buffer = NULL; + } + usb_free_urb(urb); +} +#endif + + +/* Bottom Half ********************************************************************************* */ + +/* defer_skb - put an skb on done list and schedule bottom half if necessary + */ +STATIC void +defer_skb(struct private *priv, struct sk_buff *skb, struct skb_cb *cb, + skb_state_t state, struct sk_buff_head *list) +{ + unsigned long flags; + + if (!cb) { + printk(KERN_ERR "%s: cb is NULL!\n", __FUNCTION__); + } + + //if !(cb->urb) { + // printk(KERN_ERR"%s: urb is NULL!\n", __FUNCTION__); + //} + + cb->state = state; + + if (!skb) { + printk(KERN_ERR "%s: skb is NULL!\n", __FUNCTION__); + return; + } + + spin_lock_irqsave(&list->lock, flags); + __skb_unlink(skb, list); + spin_unlock(&list->lock); + + + // link to done queue + spin_lock(&priv->done.lock); + __skb_queue_tail(&priv->done, skb); + + if (priv->done.qlen == 1) { + tasklet_schedule(&priv->bh); + } + spin_unlock_irqrestore(&priv->done.lock, flags); +} + + +/* unlink_urbs - tell usb core layer that we want it to abandon attempts to send/receive urbs + */ +STATIC int +unlink_urbs(struct sk_buff_head *q) +{ + struct sk_buff *skb; + int count = 0; + + // move from the current queue to the unlink queue + while ((skb = skb_dequeue(q))) { + struct skb_cb *cb; + struct urb *urb; + struct private *priv; + int retval; + + if (!(cb = (struct skb_cb *) skb->cb)) { + printk(KERN_ERR "%s: cb NULL\n", __FUNCTION__); + continue; + } + + if (!(urb = cb->urb)) { + printk(KERN_ERR "%s: urb NULL\n", __FUNCTION__); + continue; + } + + if (!(priv = cb->priv)) { + printk(KERN_ERR "%s: priv NULL\n", __FUNCTION__); + continue; + } + + // place them here until they can be processed after unlinking + skb_queue_tail(&priv->unlink, skb); + + //printk(KERN_INFO "%s: unlinking skb: %p len: %d jiffs: %ld\n", __FUNCTION__, + // skb, skb->len, jiffies - cb->jiffies); + + // usb core layer will call rx_complete() with appropriate status so that we can remove + urb->transfer_flags |= USB_ASYNC_UNLINK; + if ((retval = usb_unlink_urb(urb)) < 0) { + dbg("unlink urb err, %d", retval); + } + else { + count++; + } + } + return count; +} + +/* unlink_task - called as kernel task to send crc message + */ +STATIC void +unlink_task(void *data) +{ + struct private *priv = (struct private *) data; + //printk(KERN_INFO"%s:\n", __FUNCTION__); + unlink_urbs(&priv->txq); + tasklet_schedule(&priv->bh); +} + + +/* bh - bottom half + */ +STATIC void +bh(unsigned long data) +{ + struct private *priv = (struct private *) data; + struct sk_buff *skb; + + //printk(KERN_INFO "%s: priv#%08x\n", __FUNCTION__, (u32)(void*)priv); + + if (!priv) { + printk(KERN_INFO "%s: priv NULL\n", __FUNCTION__); + return; + } + + // process all skb's on the done queue + while ((skb = skb_dequeue(&priv->done))) { + + struct skb_cb *cb; + + //printk(KERN_INFO "%s: skb#%08x\n", __FUNCTION__, (u32)(void*)skb); + + if (!(cb = (struct skb_cb *) skb->cb)) { + printk(KERN_INFO "%s: cb NULL skb: %p\n", __FUNCTION__, skb); + continue; + } + + switch (cb->state) { + case rx_done: + // printk(KERN_INFO"%s: rx_done skb: %p\n", __FUNCTION__, skb); + bh_rx_process(priv, skb); + break; + + case tx_done: + // printk(KERN_INFO"%s: tx_done skb: %p\n", __FUNCTION__, skb); + { + struct urb *urb; + if (!(urb = cb->urb)) { + printk(KERN_INFO "%s: urb NULL skb: %p cb: %p\n", __FUNCTION__, skb, cb); + dev_kfree_skb_any(skb); + continue; + } + + if (urb->status) { + priv->stats.tx_errors++; + //printk(KERN_INFO "%s: urb: %p skb: %p status: %d\n", __FUNCTION__, + // urb, skb, cb->urb->status); + urb->transfer_buffer_length = 0; + urb->transfer_buffer = NULL; + //usb_free_urb(urb); + //dev_kfree_skb_any(skb); + } + else { + priv->stats.tx_packets++; + priv->stats.tx_bytes += skb->len; + usb_free_urb(urb); + dev_kfree_skb_any(skb); + } + //usb_free_urb(urb); + //dev_kfree_skb_any(skb); + break; + } + case rx_cleanup: + //printk(KERN_INFO"%s: rx_cleanup skb: %p\n", __FUNCTION__, skb); + { + struct urb *urb; + if (!(urb = cb->urb)) { + printk(KERN_INFO "%s: urb NULL skb: %p cb: %p\n", __FUNCTION__, skb, cb); + dev_kfree_skb_any(skb); + continue; + } + + if (urb) { + usb_free_urb(urb); + } + dev_kfree_skb_any(skb); + break; + } + case unknown: + case tx_start: + case rx_start: + printk(KERN_INFO "%s: UNKNOWN\n", __FUNCTION__); + printk(KERN_INFO "%s: inconsistant cb state: %d\n", __FUNCTION__, cb->state); + break; + } + } + + //printk(KERN_INFO "%s: priv->wait#%08x\n", __FUNCTION__, (u32)(void*)priv->wait); + + // are we waiting for pending urbs to complete? + if (priv->wait) { + if (!(priv->txq.qlen + priv->rxq.qlen + priv->done.qlen + priv->unlink.qlen)) { + //printk(KERN_INFO "%s: wakeup\n", __FUNCTION__); + wake_up(priv->wait); + } + } + + // do we need to queue up receive urbs? + else if (netif_running(&priv->net)) { + + while ((priv->rxq.qlen < RX_QLEN) && (priv->timeouts < 4)) { + struct urb *urb; + + //usblan_test_kalloc("bhR0"); + //printk(KERN_INFO "%s: allocating receive urb ATOMIC#%08x KERNEL#%08x\n", __FUNCTION__, + // GFP_ATOMIC,GFP_KERNEL); + // allocate an urb and use rx_submit to prepare and add it to the rxq + if ((urb = USB_ALLOC_URB(0,GFP_ATOMIC))) { + //usblan_test_kalloc("bhR1"); + //printk(KERN_INFO "%s: allocated receive urb#%08x\n", __FUNCTION__,(u32)(void*)urb); + rx_submit(priv, urb, GFP_ATOMIC); + //usblan_test_kalloc("bhR2"); + } + else { + // we failed, schedule another run to try again + //printk(KERN_INFO "%s: allocating receive urb failed\n", __FUNCTION__); + tasklet_schedule(&priv->bh); + } + } + + if (priv->txq.qlen < TX_QLEN) { + //printk(KERN_INFO"%s: wake queue\n", __FUNCTION__); + netif_wake_queue(&priv->net); + } + } +} + + + + +/* USB Functions - Probe and Disconnect ******************************************************** */ + +#define BELCARRA_SETTIME 0x04 +#define BELCARRA_SETIP 0x05 +#define BELCARRA_SETMSK 0x06 +#define BELCARRA_SETROUTER 0x07 + + +static void vendor_callback(struct urb *urb) +{ + //printk(KERN_INFO"%s:\n", __FUNCTION__); + //wake_up(priv->ctrl_wait); + + usb_free_urb(urb); + //printk(KERN_INFO"%s: finish\n", __FUNCTION__); +} + + +int VendorOut(struct private *priv, u8 bRequest, u16 wValue, u16 wIndex) +{ + struct usb_ctrlrequest *ctrl_request = &priv->ctrl_request; + int rc = 0; + + //DECLARE_WAIT_QUEUE_HEAD(vendor_wakeup); + //DECLARE_WAITQUEUE(wait, current); + + //printk(KERN_INFO"%s: bRequest: %02x wValue: %04x wIndex: %04x\n", __FUNCTION__, bRequest, wValue, wIndex); + + // setup a wait queue - this also acts as a flag to prevent bottom half from allocating more urbs + //add_wait_queue(&vendor_wakeup, &wait); + //priv->ctrl_wait = &vendor_wakeup; + + mutex_lock(&priv->mutex); + + THROW_UNLESS((priv->ctrl_urb = USB_ALLOC_URB(0, GFP_ATOMIC)), error); + + // create urb + ctrl_request->bRequestType = USB_TYPE_VENDOR | USB_RECIP_DEVICE; + ctrl_request->bRequest = bRequest; + ctrl_request->wValue = wValue; + ctrl_request->wIndex = wIndex; + ctrl_request->wLength = 0; + + FILL_CONTROL_URB(priv->ctrl_urb, priv->usbdev, + usb_sndctrlpipe(priv->usbdev, 0), + (char *)&priv->ctrl_request, + NULL, 0, vendor_callback, priv + ); + + // submit urb + + THROW_IF(USB_SUBMIT_URB(priv->ctrl_urb), error); + + // sleep + //current->state = TASK_UNINTERRUPTIBLE; + //schedule_timeout(TIMEOUT_JIFFIES * 1000); + //priv->ctrl_wait = NULL; + + + CATCH(error) { + rc = -EINVAL; + } + + //if (priv->ctrl_urb) + // usb_free_urb(priv->ctrl_urb); + //priv->ctrl_urb = NULL; + + // cleanup + //remove_wait_queue(&vendor_wakeup, &wait); + mutex_unlock(&priv->mutex); + return rc; +} + +int VendorOutLong(struct private *priv, u16 bRequest, u32 data) +{ + //printk(KERN_INFO"%s: bRequest: %02x data: %04x\n", __FUNCTION__, bRequest, data); + data = ntohl(data); + return VendorOut(priv, bRequest, (u16)(data>>16), (u16)(data&0xffff)); +} + +void network_notify(struct private *priv, u32 host_ip, u32 mask, u32 client_ip) +{ + + + //printk(KERN_INFO"%s: client_ip: %08x mask: %08x host_ip: %x\n", __FUNCTION__, client_ip, mask, host_ip); + THROW_IF(VendorOutLong(priv, BELCARRA_SETIP, client_ip), error ); + THROW_IF(VendorOutLong(priv, BELCARRA_SETMSK, mask), error ); + THROW_IF(VendorOutLong(priv, BELCARRA_SETROUTER, host_ip), error ); + + //printk(KERN_INFO"%s: host_ip\n", __FUNCTION__); + //printk(KERN_INFO"%s: finished\n", __FUNCTION__); + + CATCH(error) { + } +} + + +#if 0 +/* This is a version of usb_clear_halt() that doesn't read the status from + * the device -- this is because some devices crash their internal firmware + * when the status is requested after a halt + */ +STATIC int +set_crc(struct usb_device *dev, int pipe) +{ + return usb_control_msg(dev, + usb_sndctrlpipe(dev, 0), + 0x3, + USB_TYPE_VENDOR | USB_RECIP_INTERFACE | USB_DIR_OUT, + 0, + usb_pipeendpoint(pipe) | (usb_pipein(pipe) << 7), + NULL, 0, HZ * 3); +} +#endif + +#if 0 +/* crc_task - called as kernel task to send crc message + */ +STATIC void +crc_task(void *data) +{ + struct private *priv = (struct private *) data; + set_crc(priv->usbdev, usb_sndctrlpipe(priv->usbdev, 0)); +} +#endif + + +/* create_private - create private data structure and initialize network interface + */ +STATIC struct private * +create_private(int devnum) +{ + struct private *priv; + struct net_device *net; + + if (!(priv = kmalloc(sizeof(struct private), GFP_KERNEL))) { + return NULL; + } + + memset(priv, 0, sizeof(struct private)); + + net = &priv->net; +#ifdef MODULE + SET_MODULE_OWNER(net); +#endif + net->priv = priv; + //printk(KERN_INFO "%s: priv#%08x net#%08x\n",__FUNCTION__,(u32)(void*)priv,(u32)(void*)net); + // XXX usbb vs usbl + + switch(priv->usbdnet_device_type) { + + case usbdnet_blan: + strcpy(net->name, "usbl%d"); + break; + default: + strcpy(net->name, "usb%d"); + break; + } + memcpy(priv->dev_addr, default_addr, ETH_ALEN); + + priv->dev_addr[ETH_ALEN - 1] = (unsigned char) devnum; + + memcpy(net->dev_addr, default_addr, sizeof(default_addr)); + net->dev_addr[ETH_ALEN - 1] = devnum; + + ether_setup(net); + + net->set_mac_address = net_set_mac_address; + net->hard_start_xmit = net_hard_start_xmit; + net->get_stats = net_get_stats; + net->change_mtu = net_change_mtu; + net->open = net_open; + net->stop = net_stop; + net->tx_timeout = net_tx_timeout; + net->watchdog_timeo = TIMEOUT_JIFFIES; + + //printk(KERN_INFO"%s: finis\n", __FUNCTION__); + return priv; +} + +STATIC struct usb_device_id * +idp_search(int idVendor, int idProduct) +{ + struct usb_device_id *idp; + + //printk(KERN_INFO "%s: look for idVendor: %04x idProduct: %04x\n", __FUNCTION__, idVendor, idProduct); + + // search id_table for a match + for (idp = id_table;; idp++) { + + //printk(KERN_INFO "%s: looking at idVendor: %04x idProduct: %04x\n", __FUNCTION__, + // idp->idVendor, idp->idProduct); + + // end of table + BREAK_IF (!idp->idVendor && !idp->idProduct); + + // check for match + if ((idp->idVendor == idVendor) && (idp->idProduct == idProduct)) { + //printk(KERN_INFO "%s: MATCH\n", __FUNCTION__); + return idp; + } + } + return NULL; +} + + + +/* + * See if we have a CDC style communications interface: + * + * 1. Must have specified class, subclass and protocol + * 2. May have an optional INTERRUPT endpoint. + * + */ +STATIC int find_interface_comm( + struct private *priv, + struct usb_interface *comm_interface, + int class, int subclass, int protocol) +{ + int alternate_number; + struct usb_interface_descriptor *interface_descriptor; + + //printk(KERN_INFO"%s: class: %x subclass: %x protocol: %x\n", __FUNCTION__, class, subclass, protocol ); + + // iterate across interface alternate descriptors looking for suitable one + for (alternate_number = 0; alternate_number < comm_interface->num_altsetting; alternate_number++) { + +// interface_descriptor = comm_interface->altsetting + alternate_number; + interface_descriptor = USB_ALTSETTING(comm_interface,alternate_number); + priv->comm_ep_in = 0; + + //printk(KERN_INFO"%s: alt: %x class: %x subclass: %x protocol: %x\n", __FUNCTION__, + // alternate_number, + // interface_descriptor->bInterfaceClass, + // interface_descriptor->bInterfaceSubClass, + // interface_descriptor->bInterfaceProtocol); + + // check for class, sub-class and too many endpoints (zero or one ok) + CONTINUE_IF ((interface_descriptor->bInterfaceClass != class) || + (interface_descriptor->bInterfaceSubClass != subclass) || + (interface_descriptor->bInterfaceProtocol != protocol) || + (1 < interface_descriptor->bNumEndpoints) ); + + // if we have an endpoint check for validity + if (interface_descriptor->bNumEndpoints) { + //struct usb_endpoint_descriptor *endpoint = interface_descriptor->endpoint; + struct usb_endpoint_descriptor *endpoint = USB_IFC2EP(interface_descriptor,0); + CONTINUE_IF (!(endpoint->bEndpointAddress & USB_DIR_IN) || + (endpoint->bmAttributes != USB_ENDPOINT_XFER_INT)); + priv->comm_ep_in = endpoint->bEndpointAddress & 0x7f; + priv->comm_ep_in_size = endpoint->wMaxPacketSize; + //printk(KERN_INFO"%s: ep found %d\n", __FUNCTION__, priv->comm_ep_in); + } + + priv->comm_bInterfaceNumber = interface_descriptor->bInterfaceNumber; + priv->comm_bAlternateSetting = interface_descriptor->bAlternateSetting; + + //printk(KERN_INFO"%s: found %d %d\n", __FUNCTION__, + // priv->comm_bInterfaceNumber, priv->comm_bAlternateSetting); + return 0; + } + return -1; +} + + +/* + * See if we can have a CDC style data interface: + * + * 1. Must have specified class, subclass and protocol + * 2. Must have (only) a BULK-IN and BULK-OUT endpoint. + * 3. Optionally May have INTERRUPT endpoint. + * + */ +STATIC int find_interface_data( + struct private *priv, + struct usb_interface *data_interface, + int class, int subclass, int protocol, + int allow_interrupt) +{ + int alternate_number; + struct usb_interface_descriptor *interface_descriptor; + + //printk(KERN_INFO"%s: class: %x subclass: %x protocol: %x\n", __FUNCTION__, class, subclass, protocol ); + + for (alternate_number = 0; alternate_number < data_interface->num_altsetting; alternate_number++) { + + //interface_descriptor = data_interface->altsetting + alternate_number; + interface_descriptor = USB_ALTSETTING(data_interface,alternate_number); + priv->data_ep_in = priv->data_ep_out = 0; + + //printk(KERN_INFO"%s: alt: %d class: %x subclass: %x protocol: %x endpoints: %d\n", __FUNCTION__, + // alternate_number, + // interface_descriptor->bInterfaceClass, + // interface_descriptor->bInterfaceSubClass, + // interface_descriptor->bInterfaceProtocol, + // interface_descriptor->bNumEndpoints); + + // check for class, sub-class and wrong number of endpoints (must be two) + CONTINUE_IF ((interface_descriptor->bInterfaceClass != class) || + (interface_descriptor->bInterfaceSubClass != subclass) || + (interface_descriptor->bInterfaceProtocol != protocol) ); + + CONTINUE_IF (allow_interrupt && !((1 < interface_descriptor->bNumEndpoints) + && (3 >= interface_descriptor->bNumEndpoints))); + + CONTINUE_IF (!allow_interrupt && (2 != interface_descriptor->bNumEndpoints)); + + // check endpoints for validity, must be BULK and we want one in each direction, no more, no less + if (interface_descriptor->bNumEndpoints) { + int endpoint_number; + for (endpoint_number = 0; endpoint_number < interface_descriptor->bNumEndpoints; endpoint_number++) { + //struct usb_endpoint_descriptor *endpoint = interface_descriptor->endpoint + endpoint_number; + struct usb_endpoint_descriptor *endpoint = USB_IFC2EP(interface_descriptor,endpoint_number); + + BREAK_IF (USB_ENDPOINT_XFER_BULK != endpoint->bmAttributes); + + if (endpoint->bEndpointAddress & USB_DIR_IN) { + priv->data_ep_in = endpoint->bEndpointAddress & 0x7f; + priv->data_ep_in_size = endpoint->wMaxPacketSize; + } + else { + priv->data_ep_out = endpoint->bEndpointAddress & 0x7f; + priv->data_ep_out_size = endpoint->wMaxPacketSize; + } + } + } + + CONTINUE_IF (!priv->data_ep_in || !priv->data_ep_out); + + //printk(KERN_INFO"%s: ep found %d %d\n", __FUNCTION__, priv->data_ep_in, priv->data_ep_out); + + priv->data_bInterfaceNumber = interface_descriptor->bInterfaceNumber; + priv->data_bAlternateSetting = interface_descriptor->bAlternateSetting; + + //printk(KERN_INFO"%s: found %d %d\n", __FUNCTION__, + // priv->data_bInterfaceNumber, priv->data_bAlternateSetting); + return 0; + } + //printk(KERN_INFO"%s: not found\n", __FUNCTION__); + return -1; +} + +/* + * See if we can have a CDC style no-data interface: + * + * 1. Must have specified class, subclass and protocol + * 2. Must have a zero endpoints. + */ +STATIC int find_interface_nodata( + struct private *priv, + struct usb_interface *data_interface, + int class, int subclass, int protocol) +{ + int alternate_number; + struct usb_interface_descriptor *interface_descriptor; + + for (alternate_number = 0; alternate_number < data_interface->num_altsetting; alternate_number++) { + + //interface_descriptor = data_interface->altsetting + alternate_number; + interface_descriptor = USB_ALTSETTING(data_interface,alternate_number); + + //printk(KERN_INFO"%s: alt: %d class: %d subclass: %d endpoints: %d\n", __FUNCTION__, alternate_number, + // interface_descriptor->bInterfaceClass, + // interface_descriptor->bInterfaceSubClass, + // interface_descriptor->bNumEndpoints); + + // check for class, sub-class, protocol and verify no endpoints + CONTINUE_IF ((interface_descriptor->bInterfaceClass != class) || + (interface_descriptor->bInterfaceSubClass != subclass) || + (interface_descriptor->bInterfaceProtocol != protocol) || + (interface_descriptor->bNumEndpoints)); + + priv->nodata_bInterfaceNumber = interface_descriptor->bInterfaceNumber; + priv->nodata_bAlternateSetting = interface_descriptor->bAlternateSetting; + + //printk(KERN_INFO"%s: found %d %d\n", __FUNCTION__, + // priv->nodata_bInterfaceNumber, priv->nodata_bAlternateSetting); + + return 0; + } + //printk(KERN_INFO"%s: not found\n", __FUNCTION__); + return -1; +} + +/* + * See if we can have a MDLM style no-data interface: + * + * 1. Must have specified class, subclass and protocol + * 2. Must have have BULK-IN and BULK-OUT endpoints + * 3. May have INTERRUPT endpoint + * + */ +STATIC int find_interface_mdlm( + struct private *priv, + struct usb_interface *mdlm_interface, + int class, + int subclass, + int protocol, + char *guid + ) +{ + struct usb_interface_descriptor *interface_descriptor; + struct usb_class_descriptor *extra; + int extralen; + + if (mdlm_interface->num_altsetting > 1) { + printk(KERN_INFO"%s: too many intefaces num_altsetting: %d\n", __FUNCTION__, mdlm_interface->num_altsetting); + return -1; + } + + //interface_descriptor = mdlm_interface->altsetting; + interface_descriptor = USB_ALTSETTING(mdlm_interface,0); + + //printk(KERN_INFO"%s: class: %d subclass: %d endpoints: %d\n", __FUNCTION__, + // interface_descriptor->bInterfaceClass, + // interface_descriptor->bInterfaceSubClass, + // interface_descriptor->bNumEndpoints + // ); + + // check for class, sub-class, protocol and correct number of endpoints (two or three ok) + if ((interface_descriptor->bInterfaceClass != class) || + (interface_descriptor->bInterfaceSubClass != subclass) || + (interface_descriptor->bInterfaceProtocol != protocol) || + !((1 < interface_descriptor->bNumEndpoints) && (3 >= interface_descriptor->bNumEndpoints)) + ) + { + return -1; + } + + if (interface_descriptor->bNumEndpoints) { + int endpoint_number; + priv->comm_ep_in = priv->data_ep_in = priv->data_ep_out = 0; + for (endpoint_number = 0; endpoint_number < interface_descriptor->bNumEndpoints; endpoint_number++) { + //struct usb_endpoint_descriptor *endpoint = interface_descriptor->endpoint + endpoint_number; + struct usb_endpoint_descriptor *endpoint = USB_IFC2EP(interface_descriptor,endpoint_number); + + if (USB_ENDPOINT_XFER_BULK == endpoint->bmAttributes) { + if (endpoint->bEndpointAddress & USB_DIR_IN) { + priv->data_ep_in = endpoint->bEndpointAddress & 0x7f; + priv->data_ep_in_size = endpoint->wMaxPacketSize; + } + else { + priv->data_ep_out = endpoint->bEndpointAddress & 0x7f; + priv->data_ep_out_size = endpoint->wMaxPacketSize; + } + } + else if ((USB_ENDPOINT_XFER_INT == endpoint->bmAttributes) && + (endpoint->bEndpointAddress & USB_DIR_IN)) + { + priv->comm_ep_in = endpoint->bEndpointAddress & 0x7f; + priv->comm_ep_in_size = endpoint->wMaxPacketSize; + } + else { + return -1; + } + } + } + + if (!priv->data_ep_in || !priv->data_ep_out) { + return -1; + } + + extra = (struct usb_class_descriptor *)USB_IFC2HOST(interface_descriptor)->extra; + extralen = USB_IFC2HOST(interface_descriptor)->extralen; + while (extra && (extralen > 0)) { + + u8 *cp = (u8 *) extra; + + //printk(KERN_INFO"%s: %p extralen: %02x bLength: %02x bDescriptorType: %02x bDescriptorSubType: %02x\n", + // __FUNCTION__, extra, extralen, + // extra->bLength, extra->bDescriptorType, extra->bDescriptorSubType); + + BREAK_IF(!extra->bLength); + + // check for CS descriptors (0x24) + switch(extra->bDescriptorType) { + + + case USB_DT_CS_INTERFACE: + + //printk(KERN_INFO"%s: CS bDescriptorSubType: %02x\n", __FUNCTION__, extra->bDescriptorSubType); + + // then check for MDLM Functional or Detail descriptors + switch (extra->bDescriptorSubType) { + + // check for bGuid match + case MDLM_FUNCTIONAL: + { + struct usb_mdlm_functional_descriptor *functional = + (struct usb_mdlm_functional_descriptor *) extra; + //u8 *bGuid = (u8 *)&functional->bGuid; + //printk(KERN_INFO"%s: FUNCTIONAL bGUID %02x %02x %02x %02x %02x %02x %02x %02x\n", + // __FUNCTION__, + // bGuid[0],bGuid[1],bGuid[2],bGuid[3], + // bGuid[4],bGuid[5],bGuid[6],bGuid[7] + // ); + + //printk(KERN_INFO"%s: FUNCTIONAL bGUID %02x %02x %02x %02x %02x %02x %02x %02x\n", + // __FUNCTION__, + // bGuid[8],bGuid[9],bGuid[10],bGuid[11], + // bGuid[12],bGuid[13],bGuid[14],bGuid[15] + // ); + + RETURN_IF( -1, memcmp(guid, functional->bGuid, sizeof(functional->bGuid) != 0 )); + break; + } + + // find details + case MDLM_DETAIL: + { + struct usb_mdlm_detail_descriptor *mdlm = (struct usb_mdlm_detail_descriptor *) extra; + + //printk(KERN_INFO"%s: DETAIL bGuidDescriptorType\n", __FUNCTION__); + + // figure out what type of detail record it is + switch (mdlm->bGuidDescriptorType) { + case MDLM_SAFE_GUID: + { + struct usb_safe_detail_descriptor *safe = + (struct usb_safe_detail_descriptor *) extra; + //printk(KERN_INFO"%s: SAFE bmDataCapabilities: %02x\n", + // __FUNCTION__, safe->bmDataCapabilities); + priv->bmNetworkCapabilities = safe->bmNetworkCapabilities; + priv->bmDataCapabilities = safe->bmDataCapabilities; + break; + } + case MDLM_BLAN_GUID: + { + struct usb_blan_detail_descriptor *blan = + (struct usb_blan_detail_descriptor *) extra; + + //printk(KERN_INFO"%s: BLAN bmDataCapabilities: %02x\n", + // __FUNCTION__, blan->bmDataCapabilities); + priv->bmNetworkCapabilities = blan->bmNetworkCapabilities; + priv->bmDataCapabilities = blan->bmDataCapabilities; + priv->bPad = blan->bPad; + break; + } + default: + break; + } + } + + default: + break; + } + + default: + break; + } + + extralen -= extra->bLength; + cp = cp + extra->bLength; + extra = (struct usb_class_descriptor *) cp; + } + + priv->data_bInterfaceNumber = interface_descriptor->bInterfaceNumber; + priv->data_bAlternateSetting = interface_descriptor->bAlternateSetting; + + //printk(KERN_INFO"%s: found %d %d\n", __FUNCTION__, priv->data_bInterfaceNumber, priv->data_bAlternateSetting); + return 0; +} + +/* + * See if we can have a CDC interface: + * + * 1. class CDC_INTERFACE_CLASS + * 2. subclass CDC_INTERFACE_SUBCLASS + * 3. protocol DEFAULT_PROTOCOL + * + */ +STATIC int verify_ethernet_comm_interface( + struct usb_device *device, + struct private *priv, + int comm_number, struct usb_interface *comm_interface, + int data_number, struct usb_interface *data_interface + ) +{ + //printk(KERN_INFO"verify_ethernet_comm_interface:\n"); + + if (find_interface_comm(priv, comm_interface, CDC_INTERFACE_CLASS, CDC_INTERFACE_SUBCLASS, DEFAULT_PROTOCOL)) { + //printk(KERN_INFO"verify_ethernet_comm_interface: no comm\n"); + return -1; + } + + if (find_interface_data(priv, data_interface, DATA_INTERFACE_CLASS, 0, DEFAULT_PROTOCOL, 0)) { + //printk(KERN_INFO"verify_ethernet_comm_interface: no data\n"); + return -1; + } + + if (find_interface_nodata(priv, data_interface, DATA_INTERFACE_CLASS, 0, DEFAULT_PROTOCOL)) { + //printk(KERN_INFO"verify_ethernet_comm_interface: no nodata\n"); + } + + //printk(KERN_INFO"verify_ethernet_comm_interface: found\n"); + + priv->comm_interface = comm_number; + priv->data_interface = data_number; + priv->usbdnet_device_type = usbdnet_cdc; + + return 0; +} + +/* + * See if we can have an RNDIS interface: + * + * 1. class CDC_INTERFACE_CLASS + * 2. subclass RNDIS_INTERFACE_SUBCLASS + * 3. protocol VENDOR_SPECIFIC_PROTOCOL + * + */ +STATIC int verify_rndis_comm_interface( + struct usb_device *device, + struct private *priv, + int comm_number, struct usb_interface *comm_interface, + int data_number, struct usb_interface *data_interface + ) +{ + + //printk(KERN_INFO"verify_rndis_comm_interface:\n"); + + if (find_interface_comm(priv, comm_interface, CDC_INTERFACE_CLASS, RNDIS_INTERFACE_SUBCLASS, VENDOR_SPECIFIC_PROTOCOL)) { + //printk(KERN_INFO"verify_rndis_comm_interface: no comm\n"); + return -1; + } + + if (find_interface_data(priv, data_interface, DATA_INTERFACE_CLASS, 0, DEFAULT_PROTOCOL, 0)) { + //printk(KERN_INFO"verify_rndis_comm_interface: no data\n"); + return -1; + } + + //if (find_interface_nodata(priv, data_interface, DATA_INTERFACE_CLASS, 0, DEFAULT_PROTOCOL)) { + // printk(KERN_INFO"verify_rndis_comm_interface: no nodata\n"); + //} + + //printk(KERN_INFO"verify_rndis_comm_interface: found\n"); + + priv->comm_interface = comm_number; + priv->data_interface = data_number; + priv->usbdnet_device_type = usbdnet_rndis; + + return 0; +} + + +/* + * See if we can have an MDLM-BLAN interface: + * + * 1. class CDC_INTERFACE_CLASS + * 2. subclass MDLM_INTERFACE_SUBCLASS + * 3. protocol DEFAULT_PROTOCOL + * + */ +STATIC int verify_blan_interface( + struct usb_device *device, + struct private *priv, + struct usb_interface *data_interface + ) +{ + if (find_interface_mdlm(priv, data_interface, + CDC_INTERFACE_CLASS, + MDLM_INTERFACE_SUBCLASS, + DEFAULT_PROTOCOL, + BLAN_GUID)) + { + printk(KERN_INFO"%s: not found\n", __FUNCTION__); + return -1; + } + + //printk(KERN_INFO"%s: found bmDataCapabilities: %02x bPad %02x\n", + // __FUNCTION__, priv->bmDataCapabilities, priv->bPad); + + priv->comm_interface = priv->data_interface = 0; + priv->usbdnet_device_type = usbdnet_blan; + return 0; +} + +/* + * See if we can have an MDLM-SAFE interface: + * + * 1. class CDC_INTERFACE_CLASS + * 2. subclass MDLM_INTERFACE_SUBCLASS + * 3. protocol DEFAULT_PROTOCOL + * + */ +STATIC int verify_safe_interface( + struct usb_device *device, + struct private *priv, + struct usb_interface *data_interface + ) +{ + if (find_interface_mdlm(priv, data_interface, + CDC_INTERFACE_CLASS, + MDLM_INTERFACE_SUBCLASS, + DEFAULT_PROTOCOL, + SAFE_GUID)) + { + printk(KERN_INFO"%s: not found\n", __FUNCTION__); + return -1; + } + + //printk(KERN_INFO"%s: found bmDataCapabilities: %02x\n", __FUNCTION__, priv->bmDataCapabilities); + + priv->comm_interface = priv->data_interface = 0; + priv->usbdnet_device_type = usbdnet_safe; + return 0; +} + +/* + * See if we can have a BASIC interface: + * + * 1. class VENDOR_SPECIFIC_CLASS + * 2. subclass LINEO_INTERFACE_SUBCLASS_SAFENET + * 3. protocol LINEO_SAFENET_CRC + * + */ +STATIC int verify_basic_interface( + struct usb_device *device, + struct private *priv, + struct usb_interface *data_interface + ) +{ + if (find_interface_data(priv, data_interface, + VENDOR_SPECIFIC_CLASS, + LINEO_INTERFACE_SUBCLASS_SAFENET, + LINEO_SAFENET_CRC, + 1)) + { + printk(KERN_INFO"%s: not found\n", __FUNCTION__); + return -1; + } + + //printk(KERN_INFO"%s: found\n", __FUNCTION__); + + priv->comm_interface = priv->data_interface = 0; + priv->usbdnet_device_type = usbdnet_basic; + return 0; +} + + +/* + * Iterate across configurations looking for one that we like. + */ +STATIC int find_valid_configuration(struct usb_device *usbdev, struct private *priv) +{ + int configuration_number; + + // We will try each and every possible configuration + for ( configuration_number = 0; + configuration_number < usbdev->descriptor.bNumConfigurations; + configuration_number++ ) + { + + //struct usb_config_descriptor *configuration = usbdev->config + configuration_number; + struct usb_config_descriptor *configuration = USB_DEV2CONFIG(usbdev,configuration_number); + + //printk(KERN_INFO"%s[%d] bConfigurationValue: %d bNumInterfaces: %d\n", __FUNCTION__, + // configuration_number, configuration->bConfigurationValue, configuration->bNumInterfaces); + + priv->configuration_number = configuration_number; + priv->bConfigurationValue = configuration->bConfigurationValue; + + priv->comm_bInterfaceNumber = priv->comm_bAlternateSetting = -1; + priv->data_bInterfaceNumber = priv->data_bAlternateSetting = -1; + priv->nodata_bInterfaceNumber = priv->nodata_bAlternateSetting = -1; + + /* + * CDC and RNDIS devices have two interfaces, + * MDLM and simple devices have a single interface, + * we don't handle any devices with more or less than one or two intefaces. + */ + //printk(KERN_INFO"%s: interface(s) %d\n", __FUNCTION__, configuration->bNumInterfaces); + switch(configuration->bNumInterfaces) { + + /* + * Tests for devices with two interfaces, e.g. CDC and RNDIS. + * + * We cannot guarantee which order the comm and data interfaces will be so we have to check for + * comm/data or data/comm. + */ + case 2: { + //struct usb_interface *int0 = configuration->interface + 0; + //struct usb_interface *int1 = configuration->interface + 1; + struct usb_interface *int0 = USB_CONFIG2IFC(configuration,0); + struct usb_interface *int1 = USB_CONFIG2IFC(configuration,1); + + if ( !verify_ethernet_comm_interface(usbdev, priv, 0, int0, 1, int1)) { + //printk(KERN_INFO"%s: cdc 0 1\n", __FUNCTION__); + return 0; + } + else if ( !verify_ethernet_comm_interface(usbdev, priv, 1, int1, 0, int0)) { + //printk(KERN_INFO"%s: cdc 1 0\n", __FUNCTION__); + return 0; + } + else if ( !verify_rndis_comm_interface(usbdev, priv, 0, int0, 1, int1)) { + //printk(KERN_INFO"%s: rndis 0 1\n", __FUNCTION__); + return 0; + } + else if ( !verify_rndis_comm_interface(usbdev, priv, 1, int1, 0, int0)) { + //printk(KERN_INFO"%s: rndis 1 0\n", __FUNCTION__); + return 0; + } + } + break; + + /* + * tests for devices with a single interface, e.g. MDLM-SAFE MDLM-BLAN or BASIC + */ + case 1: + + if ( !verify_blan_interface(usbdev, priv, USB_CONFIG2IFC(configuration,0))) { + //printk(KERN_INFO"%s[%d] bConfigurationValue: %d bNumInterfaces: %d\n", __FUNCTION__, + // configuration_number, priv->bConfigurationValue, configuration->bNumInterfaces); + //printk(KERN_INFO"%s: mdlm-blan\n", __FUNCTION__); + return 0; + } + else if ( !verify_safe_interface(usbdev, priv, USB_CONFIG2IFC(configuration,0))) { + //printk(KERN_INFO"%s[%d] bConfigurationValue: %d bNumInterfaces: %d\n", __FUNCTION__, + // configuration_number, priv->bConfigurationValue, configuration->bNumInterfaces); + //printk(KERN_INFO"%s: mdlm-safe\n", __FUNCTION__); + return 0; + } + else if ( !verify_basic_interface(usbdev, priv, USB_CONFIG2IFC(configuration,0))) { + //printk(KERN_INFO"%s: basic\n", __FUNCTION__); + return 0; + } + break; + + /* + * currently we have no support for devices with zero or more than + * two interfaces.... + */ + default: + break; + } + priv->configuration_number = priv->bConfigurationValue = 0; + } + + // None of the configurations suited us. + //printk(KERN_INFO"%s: nothing found\n", __FUNCTION__); + return -1; +} + +/* + * check the active configuration to see if there are any claimed interfaces + */ +STATIC int verify_no_claimed_interfaces(struct usb_config_descriptor *act_config) +{ + struct usb_interface *interface; + int interface_number; + + // Go through all the interfaces and make sure none are + // claimed by anybody else. + // + + //printk(KERN_INFO"%s:\n", __FUNCTION__); + if (!act_config) { + printk(KERN_INFO"%s: NULL\n", __FUNCTION__); + return 0; + } + + //printk(KERN_INFO"%s: bNumInterfaces: %d\n", __FUNCTION__, act_config->bNumInterfaces); + for (interface_number = 0; interface_number < act_config->bNumInterfaces; interface_number++) { + + + interface = USB_CONFIG2IFC(act_config,interface_number); + +#if 0 + if (usb_interface_claimed(interface)) { + printk(KERN_INFO"%s: failed\n", __FUNCTION__); + return -1; + } +#endif + } + //printk(KERN_INFO"%s: ok\n", __FUNCTION__); + return 0; +} + +#if defined(CONFIG_USB_USBLAN) || defined(CONFIG_USB_USBLAN_MODULE) +/******************************************************** + * In the 2.6 host system, the result of "probe" is a + * ERROR value, (0 for success, negative for failure) + * The actual value of priv is not passed to the caller + * of probe (usb_probe_interface) + *****************************************************/ +STATIC int usblan_probe_return(struct private *priv){ + return ((priv == 0) ? -1 : 0); +} + +#else + +#error +/******************************************************** + * In the 2.4 host system, the probe routine is called + * by usb_find_interface_driver. If probe() returns a + * non zero pointer, that value is passed along to + * usb_claim_interface() + *******************************************************/ +STATIC void * usblan_probe_return(struct private *priv){ + return priv; +} + +#error + +#endif + +#if defined(CONFIG_USB_USBLAN) || defined(CONFIG_USB_USBLAN_MODULE) +STATIC int usblan_probe(struct usb_interface * udev, const struct usb_device_id *id){ + struct private *priv = NULL; + struct usb_device_descriptor *device = NULL; + struct usb_device *usbdev; + + /* find the usb device for the usb_interface */ + usbdev = interface_to_usbdev(udev); + /* find the usb device descriptor */ + device = &usbdev->descriptor; + //We can now resume the old probe routine except when returning a value +#else +#error +STATIC void * +usblan_probe(struct usb_device *usbdev, unsigned int ifnum, const struct usb_device_id *id) +{ + struct private *priv = NULL; + struct usb_device_descriptor *device = &usbdev->descriptor; + +#endif + + /* Begin the common portion of the probe routine */ + //printk(KERN_INFO "%s: probe\n", __FUNCTION__); + + /* do we have a valid device structure, is the device a CDC device, is the product_id and + * vendor_id one that we are supposed to handle, has anyone else claimed any interfaces? + */ + THROW_IF (device->bDeviceClass != CDC_DEVICE_CLASS, error); + THROW_IF (!idp_search(device->idVendor, device->idProduct), error); +#if defined(LINUX24) + THROW_IF (verify_no_claimed_interfaces(USB_CONFIG2DESC(usbdev->actconfig)), error); +#endif + + /* create a private structure to save state information about this usb device. + */ + THROW_IF (!(priv = create_private(usbdev->devnum)), error); + THROW_IF (find_valid_configuration(usbdev, priv), error); + + /* + * There is a valid configuration. + */ + //printk(KERN_INFO"%s: configuration_number: %d bConfigurationValue: %d\n", __FUNCTION__, + // priv->configuration_number, priv->bConfigurationValue); + + THROW_IF (register_netdev(&priv->net), free_priv); + + +#if !defined(CONFIG_USB_USBLAN) && !defined(CONFIG_USB_USBLAN_MODULE) + // usb_set_config() is not available inside probe() for 2.6. + //printk(KERN_INFO"%s: setting configuration bConfigurationValue: %d\n", __FUNCTION__, priv->bConfigurationValue); + + THROW_IF ( usb_set_configuration( usbdev, priv->bConfigurationValue ), unregister ); +#else + // Claim the interfaces we want before starting to operate on them... + // manually claim the interfaces we want. + switch (priv->usbdnet_device_type ) { + case usbdnet_cdc: + case usbdnet_rndis: + //printk(KERN_INFO"%s: claiming comm interface: configuration: %d interface: %d\n", __FUNCTION__, + // priv->configuration_number, priv->comm_interface); + + usb_driver_claim_interface( &usblan_driver, + USB_CONFIG2IFC(USB_DEV2CONFIG(usbdev,priv->configuration_number),priv->comm_interface), priv); + priv->intf_count += 1; + + /* FALL THROUGH */ // In order to claim the data interface too. + case usbdnet_safe: + case usbdnet_basic: + case usbdnet_blan: + //printk(KERN_INFO"%s: claiming data interface: configuration: %d interface: %d\n", __FUNCTION__, + // priv->configuration_number, priv->data_interface); + + usb_driver_claim_interface( &usblan_driver, + USB_CONFIG2IFC(USB_DEV2CONFIG(usbdev,priv->configuration_number),priv->data_interface), + priv ); + priv->intf_count += 1; + + break; + case usbdnet_unknown: + THROW(unregister); + } + priv->intf_max = priv->intf_count; +#endif + + //printk(KERN_INFO"%s: %s\n", __FUNCTION__, usbdnet_device_names[priv->usbdnet_device_type]); + + /* + * If we have a nodata interface interface use it, otherwise use the normal data interface. + * MDLM and Safe devices never have a nodata interface. + */ + switch (priv->usbdnet_device_type ) { + case usbdnet_cdc: + case usbdnet_rndis: + + //printk(KERN_INFO"%s: setting comm interface bInterfaceNumber: %d bAlternateSetting: %d\n", __FUNCTION__, + // priv->comm_bInterfaceNumber, priv->comm_bAlternateSetting); + THROW_IF (usb_set_interface(usbdev, priv->comm_bInterfaceNumber, priv->comm_bAlternateSetting), unregister); + + if (priv->nodata_bInterfaceNumber >= 0) { + //printk(KERN_INFO"%s: setting nodata interface bInterfaceNumber: %d bAlternateSetting: %d\n", + // __FUNCTION__, priv->nodata_bInterfaceNumber, priv->nodata_bAlternateSetting); + THROW_IF (usb_set_interface( usbdev, priv->nodata_bInterfaceNumber, priv->nodata_bAlternateSetting), + unregister); + } + else { + /* FALL THROUGH */ + + //printk(KERN_INFO"%s: setting data interface bInterfaceNumber: %d bAlternateSetting: %d\n", + // __FUNCTION__, priv->data_bInterfaceNumber, priv->data_bAlternateSetting); + THROW_IF (usb_set_interface( usbdev, priv->data_bInterfaceNumber, priv->data_bAlternateSetting), + unregister); + } + break; + + case usbdnet_safe: + case usbdnet_blan: + case usbdnet_basic: + + break; + + case usbdnet_unknown: + THROW(unregister); + } + + +#if !defined(CONFIG_USB_USBLAN) && !defined(CONFIG_USB_USBLAN_MODULE) + // manually claim the interfaces we want. + switch (priv->usbdnet_device_type ) { + case usbdnet_cdc: + case usbdnet_rndis: + //printk(KERN_INFO"%s: claiming comm interface: configuration: %d interface: %d\n", __FUNCTION__, + // priv->configuration_number, priv->comm_interface); + + usb_driver_claim_interface( &usblan_driver, + USB_CONFIG2IFC(USB_DEV2CONFIG(usbdev,priv->configuration_number),priv->comm_interface), priv); + //&(usbdev->config[priv->configuration_number].interface[priv->comm_interface]), priv ); + priv->intf_count += 1; + + /* FALL THROUGH */ // In order to claim the data interface too. + case usbdnet_safe: + case usbdnet_basic: + case usbdnet_blan: + //printk(KERN_INFO"%s: claiming data interface: configuration: %d interface: %d\n", __FUNCTION__, + // priv->configuration_number, priv->data_interface); + + usb_driver_claim_interface( &usblan_driver, + //&(usbdev->config[priv->configuration_number].interface[priv->data_interface]), + USB_CONFIG2IFC(USB_DEV2CONFIG(usbdev,priv->configuration_number),priv->data_interface), + priv ); + priv->intf_count += 1; + + break; + case usbdnet_unknown: + THROW(unregister); + } + priv->intf_max = priv->intf_count; +#endif + + + skb_queue_head_init(&priv->rxq); + skb_queue_head_init(&priv->txq); + skb_queue_head_init(&priv->unlink); + skb_queue_head_init(&priv->done); + + //printk(KERN_INFO "%s: tx_size: %3d rx_size: %3d\n", __FUNCTION__, priv->data_ep_out_size, priv->data_ep_in_size); + //printk(KERN_INFO "%s: tx_ep : %3x rx_ep : %3x\n", __FUNCTION__, priv->data_ep_out, priv->data_ep_in); + + priv->usbdev = usbdev; + +#if defined(LINUX24) + // ctrl task for clear halt operation + priv->ctrl_task.routine = ctrl_task; + priv->ctrl_task.data = priv; + priv->ctrl_task.sync = 0; +#else + PREPARE_WORK_ITEM(priv->ctrl_task, ctrl_task, priv); +#endif + + // reset task for reseting device +#if defined(LINUX26) + PREPARE_WORK_ITEM(priv->reset_task, reset_task, priv); +#else + priv->reset_task.routine = reset_task; + priv->reset_task.data = priv; + priv->reset_task.sync = 0; +#endif + + // unlink task for reseting device +#if defined(LINUX26) + PREPARE_WORK_ITEM(priv->unlink_task, unlink_task, priv); +#else + priv->unlink_task.routine = unlink_task; + priv->unlink_task.data = priv; + priv->unlink_task.sync = 0; +#endif + + // bottom half processing tasklet + priv->bh.func = bh; + priv->bh.data = (unsigned long) priv; + + // init mutex and list, add to device list + init_MUTEX(&priv->mutex); + INIT_LIST_HEAD(&priv->list); + + mutex_lock(&usbd_mutex); + list_add(&priv->list, &usbd_list); + mutex_unlock(&usbd_mutex); + + //printk(KERN_INFO "%s: success %s\n", __FUNCTION__, DRIVER_VERSION); + + switch (priv->usbdnet_device_type ) { + case usbdnet_blan: + network_notify(priv, NETWORK_ADDR_HOST, NETWORK_MASK, NETWORK_ADDR_CLIENT); + network_attach(&priv->net, NETWORK_ADDR_HOST, NETWORK_MASK, 1); + break; + default: + break; + } + + + // start as if the link is up + netif_device_attach(&priv->net); + +//#define NETWORK_ADDR_HOST 0xac100005 /* 172.16.0.0 */ +//#define NETWORK_ADDR_CLIENT 0xac100006 /* 172.16.0.0 */ +//#define NETWORK_MASK 0xfffffffc + +#if defined(CONFIG_USB_USBLAN) || defined(CONFIG_USB_USBLAN_MODULE) + usb_get_dev(usbdev); +#else + usb_inc_dev_use(usbdev); +#endif + + usb_set_intfdata(udev, priv); + + CATCH(error) { + printk(KERN_ERR"%s: caught error\n", __FUNCTION__); + + CATCH(free_priv) { + + printk(KERN_ERR"%s: caught free_priv\n", __FUNCTION__); + + CATCH(unregister) { + + printk(KERN_ERR"%s: caught unregister\n", __FUNCTION__); + + printk(KERN_ERR"%s: unregister\n", __FUNCTION__); + unregister_netdev(&priv->net); + } + + printk(KERN_ERR"%s: free priv\n", __FUNCTION__); + kfree(priv); + } + printk(KERN_ERR"%s: return NULL\n", __FUNCTION__); + return usblan_probe_return(NULL); + } + //printk(KERN_ERR"%s: return %p\n", __FUNCTION__, priv); + return usblan_probe_return(priv); +} + +#if defined(CONFIG_USB_USBLAN) || defined(CONFIG_USB_USBLAN_MODULE) +STATIC void usblan_disconnect(struct usb_interface *intf) +{ + struct private *priv = (struct private *) usb_get_intfdata(intf); + struct usb_device *usbdev = interface_to_usbdev(intf); + + /* If we claimed more than one interface during probe, this will + be called more than once. */ + if (priv->intf_count == priv->intf_max) { + // This is the first interface to be disconnected, unregister the network interface + unregister_netdev(&priv->net); + + // remove from device list + mutex_lock(&usbd_mutex); + mutex_lock(&priv->mutex); + list_del(&priv->list); + mutex_unlock(&usbd_mutex); + } + // release interfaces + + //printk(KERN_INFO"%s: releasing interface: %p from configuration: %d\n", __FUNCTION__, intf, priv->configuration_number); + // XXX usb_driver_release_interface(&usblan_driver,intf); + //printk(KERN_INFO"%s: releasing interface: ok\n", __FUNCTION__); + priv->intf_count -= 1; + + if (priv->intf_count <= 0) { + // disable + usb_put_dev(usbdev); + + // destroy the network interface and free the private storage + kfree(priv); + } +} +#else +STATIC void usblan_disconnect(struct usb_device *usbdev, void *ptr) { + struct private *priv = (struct private *) ptr; + + // unregister the network interface + unregister_netdev(&priv->net); + + // remove from device list + mutex_lock(&usbd_mutex); + mutex_lock(&priv->mutex); + list_del(&priv->list); + mutex_unlock(&usbd_mutex); + + // release interfaces + + + switch (priv->usbdnet_device_type ) { + case usbdnet_cdc: + case usbdnet_rndis: + //printk(KERN_INFO"%s: releasing comm interface: configuration: %d interface: %d\n", __FUNCTION__, + // priv->configuration_number, priv->comm_interface); + usb_driver_release_interface( &usblan_driver, + USB_CONFIG2IFC(USB_DEV2CONFIG(usbdev,priv->configuration_number),priv->comm_interface)); +// &(usbdev->config[priv->configuration_number].interface[priv->comm_interface])); + /* FALL THROUGH */ + case usbdnet_safe: + case usbdnet_basic: + case usbdnet_blan: + //printk(KERN_INFO"%s: releasing data interface: configuration: %d interface: %d\n", __FUNCTION__, + // priv->configuration_number, priv->data_interface); + usb_driver_release_interface( &usblan_driver, + USB_CONFIG2IFC(USB_DEV2CONFIG(usbdev,priv->configuration_number),priv->data_interface)); +// &(usbdev->config[priv->configuration_number].interface[priv->data_interface])); + case usbdnet_unknown: + break; + } + + + // disable + usb_dec_dev_use(usbdev); // QQSV + + // destroy the network interface and free the private storage + kfree(priv); +} +#endif + + +static struct usb_driver usblan_driver = { + name: "usblan", + probe: usblan_probe, + disconnect: usblan_disconnect, // QQSV + id_table: id_table, +}; + + +/* Module loading functions - modinit and modexit*********************************************** */ + +/* + * usbdnet_modinit - module init + * + */ +STATIC int __init usbdnet_modinit(void) +{ + //USB_PROBE_SET(usblan_driver, probe); + //printk(KERN_INFO DRIVER_VERSION " " DRIVER_AUTHOR "XXX\n"); + + + info(DRIVER_DESC " " DRIVER_VERSION " " DRIVER_AUTHOR); + //info(DRIVER_DESC); + + get_random_bytes(default_addr, ETH_ALEN); + default_addr[0] = (default_addr[0] & 0xf0) | 0x02; + +#if defined(LONG_STRING_OF_ZEROES_HACK) + fermat_init(); +#endif + + // if we have vendor_id / product_id parameters patch them into id list + if (vendor_id && product_id) { + int i; + //printk(KERN_INFO "%s: vendor_id: %x product_id: %x\n", __FUNCTION__, vendor_id, product_id); + for (i = 0; i < (sizeof(id_table) / sizeof(struct usb_device_id) - 1); i++) { + + if (id_table[i].idVendor == vendor_id && id_table[i].idProduct == product_id) { + + //printk(KERN_INFO "%s: vendor_id: %x product_id: %x already in table\n", + // __FUNCTION__, vendor_id, product_id); + break; + } + if (!id_table[i].idVendor && !id_table[i].idProduct) { + //printk(KERN_INFO "%s: vendor_id: %x product_id: %x inserted into table\n", + // __FUNCTION__, vendor_id, product_id); + id_table[i].match_flags = USB_DEVICE_ID_MATCH_DEVICE; + id_table[i].idVendor = vendor_id; + id_table[i].idProduct = product_id; + id_table[i].bDeviceClass = class; + id_table[i].bDeviceSubClass = subclass; + break; + } + } + } + + // register us with the usb core layer + if (usb_register(&usblan_driver)) { + return -EINVAL; + } + + return 0; +} + + +/* + * function_exit - module cleanup + * + */ +STATIC void __exit usbdnet_modexit(void) { + // de-register from the usb core layer + usb_deregister(&usblan_driver); +} + +module_init(usbdnet_modinit); +module_exit(usbdnet_modexit); diff -urN linux-2.6.26/drivers/usb/usblan/usblan.h linux-2.6.26-lab126/drivers/usb/usblan/usblan.h --- linux-2.6.26/drivers/usb/usblan/usblan.h 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/usb/usblan/usblan.h 2010-08-10 04:17:07.000000000 -0400 @@ -0,0 +1,84 @@ +#ifndef _USB_NET_USBLAN_H +#define _USB_NET_USBLAN_H 1 + +#define USB_NEW_COMPLETE_T +//#define USB_ALLOC_URB(packets) usb_alloc_urb(packets, GFP_KERNEL) +#define USB_ALLOC_URB(packets,mem_flags) usb_alloc_urb(packets,mem_flags) + +#define FILL_BULK_URB(URB,DEV,PIPE,TRANSFER_BUFFER,BUFFER_LENGTH,COMPLETE,CONTEXT) \ + usb_fill_bulk_urb(URB,DEV,PIPE,TRANSFER_BUFFER,BUFFER_LENGTH,(usb_complete_t)COMPLETE,CONTEXT) + +#define FILL_CONTROL_URB(URB,DEV,PIPE,SETUP,TRANSFER_BUFFER,BUFFER_LENGTH,COMPLETE,CONTEXT) \ + usb_fill_control_urb(URB,DEV,PIPE,SETUP,TRANSFER_BUFFER,BUFFER_LENGTH,(usb_complete_t)COMPLETE,CONTEXT) + +#define USB_SUBMIT_URB(urb) usb_submit_urb(urb, 0) +#define USB_ALTSETTING(ifc,alt_index) &(ifc->altsetting[alt_index].desc) +#define USB_IFC2EP(ifc,index) &(container_of(ifc, struct usb_host_interface, desc)->endpoint[index].desc) +#define USB_IFC2HOST(ifc) container_of(ifc, struct usb_host_interface, desc) +#define USB_DEV2CONFIG(dev,index) &(dev->config[index].desc) +#define USB_CONFIG2IFC(cfg, index) (container_of(cfg, struct usb_host_config, desc)->interface[index]) +#define USB_CONFIG2DESC(cfg) &(cfg->desc) +#define USB_PROBE_DELAYED_SET NULL +#define USB_PROBE_ERROR -1 +#define USB_PROBE_SET(driver,proc) { \ + int __usb_probe_proc(struct usb_interface *intf, \ + const struct usb_device_id *id){\ + struct usb_device *usbdev = NULL;\ + if(!intf) { return USB_PROBE_ERROR; }\ + usbdev = interface_to_usbdev(intf); \ + return(!((*proc)(usbdev,0,id)) ? USB_PROBE_ERROR :0);\ + }\ + driver->probe = __usb_probe_proc; \ +} + + + +//Missing (obsolete??) XXX +//static void usb_inc_dev_use(struct usb_device * dev) {} +#define usb_inc_dev_use(dev) usb_get_dev(dev) +#define usb_dec_dev_use(dev) usb_put_dev(dev) +/*----------------------------------------------------------------------------* + * New USB Structures * + *----------------------------------------------------------------------------*/ + +/* + * urb->transfer_flags: + */ +#define USB_DISABLE_SPD 0x0001 +//#define URB_SHORT_NOT_OK USB_DISABLE_SPD +#define USB_ISO_ASAP 0x0002 +#define USB_ASYNC_UNLINK 0x0008 +#define USB_QUEUE_BULK 0x0010 +#define USB_NO_FSBR 0x0020 +#define USB_ZERO_PACKET 0x0040 // Finish bulk OUTs always with zero length packet +#define URB_NO_INTERRUPT 0x0080 /* HINT: no non-error interrupt needed */ + /* ... less overhead for QUEUE_BULK */ +#define USB_TIMEOUT_KILLED 0x1000 // only set by HCD! + +/* + * USB-status codes: + * USB_ST* maps to -E* and should go away in the future + */ + +#define USB_ST_NOERROR 0 +#define USB_ST_CRC (-EILSEQ) +#define USB_ST_BITSTUFF (-EPROTO) +#define USB_ST_NORESPONSE (-ETIMEDOUT) /* device not responding/handshaking */ +#define USB_ST_DATAOVERRUN (-EOVERFLOW) +#define USB_ST_DATAUNDERRUN (-EREMOTEIO) +#define USB_ST_BUFFEROVERRUN (-ECOMM) +#define USB_ST_BUFFERUNDERRUN (-ENOSR) +#define USB_ST_INTERNALERROR (-EPROTO) /* unknown error */ +#define USB_ST_SHORT_PACKET (-EREMOTEIO) +#define USB_ST_PARTIAL_ERROR (-EXDEV) /* ISO transfer only partially completed */ +#define USB_ST_URB_KILLED (-ENOENT) /* URB canceled by user */ +#define USB_ST_URB_PENDING (-EINPROGRESS) +#define USB_ST_REMOVED (-ENODEV) /* device not existing or removed */ +#define USB_ST_TIMEOUT (-ETIMEDOUT) /* communication timed out, also in urb->status**/ +#define USB_ST_NOTSUPPORTED (-ENOSYS) +#define USB_ST_BANDWIDTH_ERROR (-ENOSPC) /* too much bandwidth used */ +#define USB_ST_URB_INVALID_ERROR (-EINVAL) /* invalid value/transfer type */ +#define USB_ST_URB_REQUEST_ERROR (-ENXIO) /* invalid endpoint */ +#define USB_ST_STALL (-EPIPE) /* pipe stalled, also in urb->status*/ + +#endif diff -urN linux-2.6.26/drivers/video/Kconfig linux-2.6.26-lab126/drivers/video/Kconfig --- linux-2.6.26/drivers/video/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/video/Kconfig 2010-08-10 04:15:57.000000000 -0400 @@ -169,8 +169,9 @@ default n config FB_DEFERRED_IO - bool + bool "Enable Deferred IO" depends on FB + default n config FB_METRONOME tristate @@ -234,6 +235,8 @@ comment "Frame buffer hardware drivers" depends on FB +source "drivers/video/eink/Kconfig" + config FB_CIRRUS tristate "Cirrus Logic support" depends on FB && (ZORRO || PCI) @@ -370,6 +373,10 @@ Say Y to enable the Framebuffer driver for the CLPS7111 and EP7212 processors. +if ARCH_MXC +source "drivers/video/mxc/Kconfig" +endif + config FB_SA1100 bool "SA-1100 LCD support" depends on (FB = y) && ARM && ARCH_SA1100 diff -urN linux-2.6.26/drivers/video/Makefile linux-2.6.26-lab126/drivers/video/Makefile --- linux-2.6.26/drivers/video/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/video/Makefile 2010-08-10 04:15:57.000000000 -0400 @@ -111,11 +111,14 @@ obj-$(CONFIG_FB_FSL_DIU) += fsl-diu-fb.o obj-$(CONFIG_FB_PNX4008_DUM) += pnx4008/ obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnx4008/ +obj-$(CONFIG_FB_MXC) += mxc/ obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o obj-$(CONFIG_FB_PS3) += ps3fb.o obj-$(CONFIG_FB_SM501) += sm501fb.o obj-$(CONFIG_FB_XILINX) += xilinxfb.o obj-$(CONFIG_FB_OMAP) += omap/ +obj-$(CONFIG_FB_EINK) += eink/ +obj-$(CONFIG_FB_EINK_HAL_BUILTIN) += eink/ # only for testing! obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o # Platform or fallback drivers go here diff -urN linux-2.6.26/drivers/video/backlight/Kconfig linux-2.6.26-lab126/drivers/video/backlight/Kconfig --- linux-2.6.26/drivers/video/backlight/Kconfig 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/video/backlight/Kconfig 2010-08-10 04:15:55.000000000 -0400 @@ -112,3 +112,36 @@ help If you have a Intel LE80578 (Carillo Ranch) say Y to enable the backlight driver. + +menuconfig BACKLIGHT_MXC + bool "Freescale MXC/i.MX Backlight Drivers" + depends on BACKLIGHT_CLASS_DEVICE && ARCH_MXC + default y + help + If you have a Freescale MC13783 PMIC, say y to enable the + backlight driver. + +config BACKLIGHT_MXC_IPU + tristate "IPU PWM Backlight Driver" + depends on BACKLIGHT_MXC && MXC_IPU_V1 + default y + +config BACKLIGHT_MXC_LCDC + tristate "LCDC PWM Backlight Driver" + depends on BACKLIGHT_MXC && (ARCH_MX21 || ARCH_MX27 || ARCH_MX25) + default y + +config BACKLIGHT_MXC_PMIC + tristate "PMIC Backlight Driver" + depends on BACKLIGHT_MXC && MXC_MC13783_LIGHT && MXC_MC13783_POWER + default y + +config BACKLIGHT_MXC_MC13892 + tristate "Mc13892 Backlight Driver" + depends on BACKLIGHT_MXC && MXC_MC13892_LIGHT + default y + +config BACKLIGHT_WM8350 + tristate "WM8350 Backlight Driver" + depends on BACKLIGHT_MXC && REGULATOR_WM8350 + default y diff -urN linux-2.6.26/drivers/video/backlight/Makefile linux-2.6.26-lab126/drivers/video/backlight/Makefile --- linux-2.6.26/drivers/video/backlight/Makefile 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/video/backlight/Makefile 2010-08-10 04:15:55.000000000 -0400 @@ -10,3 +10,9 @@ obj-$(CONFIG_BACKLIGHT_OMAP1) += omap1_bl.o obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o obj-$(CONFIG_BACKLIGHT_CARILLO_RANCH) += cr_bllcd.o + +obj-$(CONFIG_BACKLIGHT_MXC_LCDC) += mxc_lcdc_bl.o +obj-$(CONFIG_BACKLIGHT_MXC_IPU) += mxc_ipu_bl.o +obj-$(CONFIG_BACKLIGHT_MXC_PMIC) += mxc_pmic_bl.o +obj-$(CONFIG_BACKLIGHT_WM8350) += wm8350_bl.o +obj-$(CONFIG_BACKLIGHT_MXC_MC13892) += mxc_mc13892_bl.o diff -urN linux-2.6.26/drivers/video/backlight/mxc_ipu_bl.c linux-2.6.26-lab126/drivers/video/backlight/mxc_ipu_bl.c --- linux-2.6.26/drivers/video/backlight/mxc_ipu_bl.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/video/backlight/mxc_ipu_bl.c 2010-08-10 04:15:55.000000000 -0400 @@ -0,0 +1,155 @@ +/* + * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @defgroup IPU_BL MXC IPU Backlight Driver + */ +/*! + * @file mxc_ipu_bl.c + * + * @brief Backlight Driver for IPU PWM on Freescale MXC/i.MX platforms. + * + * This file contains API defined in include/linux/clk.h for setting up and + * retrieving clocks. + * + * Based on Sharp's Corgi Backlight Driver + * + * @ingroup IPU_BL + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MXC_MAX_INTENSITY 255 +#define MXC_DEFAULT_INTENSITY 127 +#define MXC_INTENSITY_OFF 0 + +struct mxcbl_dev_data { + int intensity; +}; + +static int fb_id; + +static int mxcbl_send_intensity(struct backlight_device *bd) +{ + int intensity = bd->props.brightness; + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + + if (bd->props.power != FB_BLANK_UNBLANK) + intensity = 0; + if (bd->props.fb_blank != FB_BLANK_UNBLANK) + intensity = 0; + + ipu_sdc_set_brightness(intensity); + + devdata->intensity = intensity; + return 0; +} + +static int mxcbl_get_intensity(struct backlight_device *bd) +{ + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + return devdata->intensity; +} + +static int mxcbl_check_fb(struct fb_info *info) +{ + int id = info->fix.id[4] - '0'; + if (id == fb_id) { + if ((id == 3) && !strcmp(info->fix.id, "DISP3 FG")) { + return 0; + } + return 1; + } + return 0; +} + +static struct backlight_ops mxcbl_ops = { + .get_brightness = mxcbl_get_intensity, + .update_status = mxcbl_send_intensity, + .check_fb = mxcbl_check_fb, +}; + +static int __init mxcbl_probe(struct platform_device *pdev) +{ + struct backlight_device *bd; + struct mxcbl_dev_data *devdata; + int ret = 0; + + devdata = kzalloc(sizeof(struct mxcbl_dev_data), GFP_KERNEL); + if (!devdata) + return -ENOMEM; + fb_id = (int)pdev->dev.platform_data; + + bd = backlight_device_register(pdev->dev.bus_id, &pdev->dev, devdata, + &mxcbl_ops); + if (IS_ERR(bd)) { + ret = PTR_ERR(bd); + goto err0; + } + platform_set_drvdata(pdev, bd); + + bd->props.brightness = MXC_DEFAULT_INTENSITY; + bd->props.max_brightness = MXC_MAX_INTENSITY; + bd->props.power = FB_BLANK_UNBLANK; + bd->props.fb_blank = FB_BLANK_UNBLANK; + backlight_update_status(bd); + + printk("MXC Backlight Device %s Initialized.\n", pdev->dev.bus_id); + return 0; + err0: + kfree(devdata); + return ret; +} + +static int mxcbl_remove(struct platform_device *pdev) +{ + struct backlight_device *bd = platform_get_drvdata(pdev); + + bd->props.brightness = MXC_INTENSITY_OFF; + backlight_update_status(bd); + + backlight_device_unregister(bd); + + return 0; +} + +static struct platform_driver mxcbl_driver = { + .probe = mxcbl_probe, + .remove = mxcbl_remove, + .driver = { + .name = "mxc_ipu_bl", + }, +}; + +static int __init mxcbl_init(void) +{ + return platform_driver_register(&mxcbl_driver); +} + +static void __exit mxcbl_exit(void) +{ + platform_driver_unregister(&mxcbl_driver); +} + +late_initcall(mxcbl_init); +module_exit(mxcbl_exit); + +MODULE_DESCRIPTION("Freescale MXC/i.MX IPU PWM Backlight Driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/video/backlight/mxc_lcdc_bl.c linux-2.6.26-lab126/drivers/video/backlight/mxc_lcdc_bl.c --- linux-2.6.26/drivers/video/backlight/mxc_lcdc_bl.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/video/backlight/mxc_lcdc_bl.c 2010-08-10 04:15:55.000000000 -0400 @@ -0,0 +1,160 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @defgroup LCDC_BL MXC LCDC Backlight Driver + */ +/*! + * @file mxc_lcdc_bl.c + * + * @brief Backlight Driver for LCDC PWM on Freescale MXC/i.MX platforms. + * + * This file contains API defined in include/linux/clk.h for setting up and + * retrieving clocks. + * + * Based on Sharp's Corgi Backlight Driver + * + * @ingroup LCDC_BL + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MXC_MAX_INTENSITY 255 +#define MXC_DEFAULT_INTENSITY 127 +#define MXC_INTENSITY_OFF 0 + +extern void mx2fb_set_brightness(uint8_t); + +struct mxcbl_dev_data { + struct clk *clk; + int intensity; +}; + +static int mxcbl_send_intensity(struct backlight_device *bd) +{ + int intensity = bd->props.brightness; + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + + if (bd->props.power != FB_BLANK_UNBLANK) + intensity = 0; + if (bd->props.fb_blank != FB_BLANK_UNBLANK) + intensity = 0; + + if ((devdata->intensity == 0) && (intensity != 0)) + clk_enable(devdata->clk); + + /* PWM contrast control register */ + mx2fb_set_brightness(intensity); + + if ((devdata->intensity != 0) && (intensity == 0)) + clk_disable(devdata->clk); + + devdata->intensity = intensity; + return 0; +} + +static int mxcbl_get_intensity(struct backlight_device *bd) +{ + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + return devdata->intensity; +} + +static int mxcbl_check_fb(struct fb_info *info) +{ + if (strcmp(info->fix.id, "DISP0 BG") == 0) { + return 1; + } + return 0; +} + +static struct backlight_ops mxcbl_ops = { + .get_brightness = mxcbl_get_intensity, + .update_status = mxcbl_send_intensity, + .check_fb = mxcbl_check_fb, +}; + +static int __init mxcbl_probe(struct platform_device *pdev) +{ + struct backlight_device *bd; + struct mxcbl_dev_data *devdata; + int ret = 0; + + devdata = kzalloc(sizeof(struct mxcbl_dev_data), GFP_KERNEL); + if (!devdata) + return -ENOMEM; + + devdata->clk = clk_get(NULL, "lcdc_clk"); + + bd = backlight_device_register(pdev->dev.bus_id, &pdev->dev, devdata, + &mxcbl_ops); + if (IS_ERR(bd)) { + ret = PTR_ERR(bd); + goto err0; + } + platform_set_drvdata(pdev, bd); + + bd->props.brightness = MXC_DEFAULT_INTENSITY; + bd->props.max_brightness = MXC_MAX_INTENSITY; + bd->props.power = FB_BLANK_UNBLANK; + bd->props.fb_blank = FB_BLANK_UNBLANK; + mx2fb_set_brightness(MXC_DEFAULT_INTENSITY); + + printk("MXC Backlight Device %s Initialized.\n", pdev->dev.bus_id); + return 0; + err0: + kfree(devdata); + return ret; +} + +static int mxcbl_remove(struct platform_device *pdev) +{ + struct backlight_device *bd = platform_get_drvdata(pdev); + + bd->props.brightness = MXC_INTENSITY_OFF; + backlight_update_status(bd); + + backlight_device_unregister(bd); + + return 0; +} + +static struct platform_driver mxcbl_driver = { + .probe = mxcbl_probe, + .remove = mxcbl_remove, + .driver = { + .name = "mxc_lcdc_bl", + }, +}; + +static int __init mxcbl_init(void) +{ + return platform_driver_register(&mxcbl_driver); +} + +static void __exit mxcbl_exit(void) +{ + platform_driver_unregister(&mxcbl_driver); +} + +module_init(mxcbl_init); +module_exit(mxcbl_exit); + +MODULE_DESCRIPTION("Freescale MXC/i.MX LCDC PWM Backlight Driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/video/backlight/mxc_mc13892_bl.c linux-2.6.26-lab126/drivers/video/backlight/mxc_mc13892_bl.c --- linux-2.6.26/drivers/video/backlight/mxc_mc13892_bl.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/video/backlight/mxc_mc13892_bl.c 2010-08-10 04:15:55.000000000 -0400 @@ -0,0 +1,171 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +/* +#define MXC_MAX_INTENSITY 255 +#define MXC_DEFAULT_INTENSITY 127 +*/ +/* workaround for atlas hot issue */ +#define MXC_MAX_INTENSITY 128 +#define MXC_DEFAULT_INTENSITY 64 + +#define MXC_INTENSITY_OFF 0 + +struct mxcbl_dev_data { + int intensity; + int suspend; +}; + +static int mxcbl_set_intensity(struct backlight_device *bd) +{ + int brightness = bd->props.brightness; + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + + if (bd->props.power != FB_BLANK_UNBLANK) + brightness = 0; + if (bd->props.fb_blank != FB_BLANK_UNBLANK) + brightness = 0; + if (devdata->suspend) + brightness = 0; + + brightness = brightness / 4; + mc13892_bklit_set_dutycycle(LIT_MAIN, brightness); + devdata->intensity = brightness; + + return 0; +} + +static int mxcbl_get_intensity(struct backlight_device *bd) +{ + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + return devdata->intensity; +} + +static int mxcbl_check_fb(struct fb_info *info) +{ + char *id = info->fix.id; + + if (!strcmp(id, "DISP3 BG")) + return 1; + else + return 0; +} + +static struct backlight_ops bl_ops; + +static int __init mxcbl_probe(struct platform_device *pdev) +{ + int ret = 0; + struct backlight_device *bd; + struct mxcbl_dev_data *devdata; + + pr_debug("mc13892 backlight start probe\n"); + + devdata = kzalloc(sizeof(struct mxcbl_dev_data), GFP_KERNEL); + if (!devdata) + return -ENOMEM; + + bl_ops.check_fb = mxcbl_check_fb; + bl_ops.get_brightness = mxcbl_get_intensity; + bl_ops.update_status = mxcbl_set_intensity; + bd = backlight_device_register(pdev->dev.bus_id, &pdev->dev, devdata, + &bl_ops); + if (IS_ERR(bd)) { + ret = PTR_ERR(bd); + goto err0; + } + + platform_set_drvdata(pdev, bd); + + /* according to LCD spec, current should be 18mA */ + /* workaround for atlas hot issue, set current 15mA */ + mc13892_bklit_set_current(LIT_MAIN, LIT_CURR_15); + bd->props.brightness = MXC_DEFAULT_INTENSITY; + bd->props.max_brightness = MXC_MAX_INTENSITY; + bd->props.power = FB_BLANK_UNBLANK; + bd->props.fb_blank = FB_BLANK_UNBLANK; + backlight_update_status(bd); + pr_debug("mc13892 backlight probed successfully\n"); + return 0; + + err0: + kfree(devdata); + return ret; +} + +static int mxcbl_remove(struct platform_device *pdev) +{ + struct backlight_device *bd = platform_get_drvdata(pdev); + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + + kfree(devdata); + backlight_device_unregister(bd); + return 0; +} + +static int mxcbl_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct backlight_device *bd = platform_get_drvdata(pdev); + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + + devdata->suspend = 1; + backlight_update_status(bd); + return 0; +} + +static int mxcbl_resume(struct platform_device *pdev) +{ + struct backlight_device *bd = platform_get_drvdata(pdev); + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + + devdata->suspend = 0; + backlight_update_status(bd); + return 0; +} + +static struct platform_driver mxcbl_driver = { + .probe = mxcbl_probe, + .remove = mxcbl_remove, + .suspend = mxcbl_suspend, + .resume = mxcbl_resume, + .driver = { + .name = "mxc_mc13892_bl", + }, +}; + +static int __init mxcbl_init(void) +{ + return platform_driver_register(&mxcbl_driver); +} + +static void __exit mxcbl_exit(void) +{ + platform_driver_unregister(&mxcbl_driver); +} + +module_init(mxcbl_init); +module_exit(mxcbl_exit); + +MODULE_DESCRIPTION("Freescale MXC/i.MX PMIC Backlight Driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/video/backlight/mxc_pmic_bl.c linux-2.6.26-lab126/drivers/video/backlight/mxc_pmic_bl.c --- linux-2.6.26/drivers/video/backlight/mxc_pmic_bl.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/video/backlight/mxc_pmic_bl.c 2010-08-10 04:15:55.000000000 -0400 @@ -0,0 +1,197 @@ +/* + * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @defgroup PMIC_BL MXC PMIC Backlight Driver + */ +/*! + * @file mxc_pmic_bl.c + * + * @brief PMIC Backlight Driver for Freescale MXC/i.MX platforms. + * + * This file contains API defined in include/linux/clk.h for setting up and + * retrieving clocks. + * + * Based on Sharp's Corgi Backlight Driver + * + * @ingroup PMIC_BL + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define MXC_MAX_INTENSITY 255 +#define MXC_DEFAULT_INTENSITY 127 +#define MXC_INTENSITY_OFF 0 + +struct mxcbl_dev_data { + int bl_id; + int intensity; + struct backlight_ops bl_ops; +}; + +static int pmic_bl_use_count; +static int main_fb_id; +static int sec_fb_id; + +static int mxcbl_send_intensity(struct backlight_device *bd) +{ + int intensity = bd->props.brightness; + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + + if (bd->props.power != FB_BLANK_UNBLANK) + intensity = 0; + if (bd->props.fb_blank != FB_BLANK_UNBLANK) + intensity = 0; + + intensity = intensity / 16; + pmic_bklit_set_dutycycle(devdata->bl_id, intensity); + + devdata->intensity = intensity; + return 0; +} + +static int mxcbl_get_intensity(struct backlight_device *bd) +{ + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + return devdata->intensity; +} + +static int mxcbl_check_main_fb(struct fb_info *info) +{ + int id = info->fix.id[4] - '0'; + + if (id == main_fb_id) { + return 1; + } else { + return 0; + } +} + +static int mxcbl_check_sec_fb(struct fb_info *info) +{ + int id = info->fix.id[4] - '0'; + + if (id == sec_fb_id) { + return 1; + } else { + return 0; + } +} + +static int __init mxcbl_probe(struct platform_device *pdev) +{ + int ret = 0; + struct backlight_device *bd; + struct mxcbl_dev_data *devdata; + + devdata = kzalloc(sizeof(struct mxcbl_dev_data), GFP_KERNEL); + if (!devdata) + return -ENOMEM; + devdata->bl_id = pdev->id; + + if (pdev->id == 0) { + devdata->bl_ops.check_fb = mxcbl_check_main_fb; + main_fb_id = (int)pdev->dev.platform_data; + } else { + devdata->bl_ops.check_fb = mxcbl_check_sec_fb; + sec_fb_id = (int)pdev->dev.platform_data; + } + + devdata->bl_ops.get_brightness = mxcbl_get_intensity; + devdata->bl_ops.update_status = mxcbl_send_intensity, + bd = + backlight_device_register(pdev->dev.bus_id, &pdev->dev, devdata, + &devdata->bl_ops); + if (IS_ERR(bd)) { + ret = PTR_ERR(bd); + goto err0; + } + + platform_set_drvdata(pdev, bd); + + if (pmic_bl_use_count++ == 0) { + pmic_power_regulator_on(SW_SW3); + pmic_power_regulator_set_lp_mode(SW_SW3, LOW_POWER_CTRL_BY_PIN); + + pmic_bklit_tcled_master_enable(); + pmic_bklit_enable_edge_slow(); + pmic_bklit_set_cycle_time(0); + } + + pmic_bklit_set_current(devdata->bl_id, 7); + bd->props.brightness = MXC_DEFAULT_INTENSITY; + bd->props.max_brightness = MXC_MAX_INTENSITY; + bd->props.power = FB_BLANK_UNBLANK; + bd->props.fb_blank = FB_BLANK_UNBLANK; + backlight_update_status(bd); + + printk("MXC Backlight Device %s Initialized.\n", pdev->dev.bus_id); + return 0; + err0: + kfree(devdata); + return ret; +} + +static int mxcbl_remove(struct platform_device *pdev) +{ + struct backlight_device *bd = platform_get_drvdata(pdev); + + bd->props.brightness = MXC_INTENSITY_OFF; + backlight_update_status(bd); + + if (--pmic_bl_use_count == 0) { + pmic_bklit_tcled_master_disable(); + + pmic_power_regulator_off(SW_SW3); + pmic_power_regulator_set_lp_mode(SW_SW3, LOW_POWER_CTRL_BY_PIN); + } + + backlight_device_unregister(bd); + + printk("MXC Backlight Driver Unloaded\n"); + + return 0; +} + +static struct platform_driver mxcbl_driver = { + .probe = mxcbl_probe, + .remove = mxcbl_remove, + .driver = { + .name = "mxc_pmic_bl", + }, +}; + +static int __init mxcbl_init(void) +{ + return platform_driver_register(&mxcbl_driver); +} + +static void __exit mxcbl_exit(void) +{ + platform_driver_unregister(&mxcbl_driver); +} + +module_init(mxcbl_init); +module_exit(mxcbl_exit); + +MODULE_DESCRIPTION("Freescale MXC/i.MX PMIC Backlight Driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/video/backlight/wm8350_bl.c linux-2.6.26-lab126/drivers/video/backlight/wm8350_bl.c --- linux-2.6.26/drivers/video/backlight/wm8350_bl.c 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.26-lab126/drivers/video/backlight/wm8350_bl.c 2010-08-10 04:15:55.000000000 -0400 @@ -0,0 +1,303 @@ +/* + * Backlight driver for DCDC2 on i.MX32ADS board + * + * Copyright(C) 2007 Wolfson Microelectronics PLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct wm8350_backlight { + struct backlight_properties props; + struct backlight_device *device; + struct regulator *dcdc; + struct regulator *isink; + struct notifier_block notifier; + struct work_struct work; + struct mutex mutex; + int intensity; + int suspend; + int retries; +}; + +/* hundredths of uA, 405 = 4.05 uA */ +static const int intensity_huA[] = { + 405, 482, 573, 681, 810, 963, 1146, 1362, 1620, 1927, 2291, 2725, + 3240, 3853, 4582, 5449, 6480, 7706, 9164, 10898, 12960, 15412, 18328, + 21796, 25920, 30824, 36656, 43592, 51840, 61648, 73313, 87184, + 103680, 123297, 146626, 174368, 207360, 246594, 293251, 348737, + 414720, 493188, 586503, 697473, 829440, 986376, 1173005, 1394946, + 1658880, 1972752, 2346011, 2789892, 3317760, 3945504, 4692021, + 5579785, 6635520, 7891008, 9384042, 11159570, 13271040, 15782015, + 18768085, 22319140, +}; + +static void bl_work(struct work_struct *work) +{ + struct wm8350_backlight *bl = + container_of(work, struct wm8350_backlight, work); + struct regulator *isink = bl->isink; + + mutex_lock(&bl->mutex); + if (bl->intensity >= 0 && + bl->intensity < ARRAY_SIZE(intensity_huA)) { + bl->retries = 0; + regulator_set_current(isink, + intensity_huA[bl->intensity] / 100); + } else + printk(KERN_ERR "wm8350: Backlight intensity error\n"); + mutex_unlock(&bl->mutex); +} + +static int wm8350_bl_notifier(struct notifier_block *self, + unsigned long event, void *data) +{ + struct wm8350_backlight *bl = + container_of(self, struct wm8350_backlight, notifier); + struct regulator *isink = bl->isink; + + if (event & REGULATOR_EVENT_UNDER_VOLTAGE) + printk(KERN_ERR "wm8350: BL DCDC undervoltage\n"); + if (event & REGULATOR_EVENT_REGULATION_OUT) + printk(KERN_ERR "wm8350: BL ISINK out of regulation\n"); + + mutex_lock(&bl->mutex); + if (bl->retries) { + bl->retries--; + regulator_disable(isink); + regulator_set_current(isink, bl->intensity); + regulator_enable(isink); + } else { + printk(KERN_ERR + "wm8350: BL regulation retry failure - disable\n"); + bl->intensity = 0; + regulator_disable(isink); + } + mutex_unlock(&bl->mutex); + return 0; +} + +static int wm8350_bl_send_intensity(struct backlight_device *bd) +{ + struct wm8350_backlight *bl = + (struct wm8350_backlight *)dev_get_drvdata(&bd->dev); + int intensity = bd->props.brightness; + + if (bd->props.power != FB_BLANK_UNBLANK) + intensity = 0; + if (bd->props.fb_blank != FB_BLANK_UNBLANK) + intensity = 0; + if (bl->suspend) + intensity = 0; + + mutex_lock(&bl->mutex); + bl->intensity = intensity; + mutex_unlock(&bl->mutex); + schedule_work(&bl->work); + + return 0; +} + +#ifdef CONFIG_PM +static int wm8350_bl_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct wm8350_backlight *bl = + (struct wm8350_backlight *)platform_get_drvdata(pdev); + + bl->suspend = 1; + backlight_update_status(bl->device); + return 0; +} + +static int wm8350_bl_resume(struct platform_device *pdev) +{ + struct wm8350_backlight *bl = + (struct wm8350_backlight *)platform_get_drvdata(pdev); + + bl->suspend = 0; + backlight_update_status(bl->device); + return 0; +} +#else +#define wm8350_bl_suspend NULL +#define wm8350_bl_resume NULL +#endif + +static int wm8350_bl_get_intensity(struct backlight_device *bd) +{ + struct wm8350_backlight *bl = + (struct wm8350_backlight *)dev_get_drvdata(&bd->dev); + return bl->intensity; +} + +static struct backlight_ops wm8350_bl_ops = { + .get_brightness = wm8350_bl_get_intensity, + .update_status = wm8350_bl_send_intensity, +}; + +static int wm8350_bl_probe(struct platform_device *pdev) +{ + struct regulator *isink, *dcdc; + struct wm8350_backlight *bl; + struct wm8350_bl_platform_data *pdata = pdev->dev.platform_data; + struct wm8350_pmic *pmic; + int ret; + + if (pdata == NULL) { + printk(KERN_ERR "%s: no platform data\n", __func__); + return -ENODEV; + } + + if (pdata->isink != WM8350_ISINK_A && pdata->isink != WM8350_ISINK_B) { + printk(KERN_ERR "%s: invalid ISINK\n", __func__); + return -EINVAL; + } + if (pdata->dcdc != WM8350_DCDC_2 && pdata->dcdc != WM8350_DCDC_5) { + printk(KERN_ERR "%s: invalid DCDC\n", __func__); + return -EINVAL; + } + + printk(KERN_INFO "wm8350: backlight using %s and %s\n", + pdata->isink == WM8350_ISINK_A ? "ISINKA" : "ISINKB", + pdata->dcdc == WM8350_DCDC_2 ? "DCDC2" : "DCDC5"); + + isink = regulator_get(&pdev->dev, + pdata->isink == WM8350_ISINK_A ? "ISINKA" : "ISINKB"); + if (IS_ERR(isink) || isink == NULL) { + printk(KERN_ERR "%s: cant get ISINK\n", __func__); + return PTR_ERR(isink); + } + + dcdc = regulator_get(&pdev->dev, + pdata->dcdc == WM8350_DCDC_2 ? "DCDC2" : "DCDC5"); + if (IS_ERR(dcdc) || dcdc == NULL) { + printk(KERN_ERR "%s: cant get DCDC\n", __func__); + regulator_put(isink, &pdev->dev); + return PTR_ERR(dcdc); + } + + bl = kzalloc(sizeof(*bl), GFP_KERNEL); + if (bl == NULL) { + regulator_put(isink, &pdev->dev); + regulator_put(dcdc, &pdev->dev); + return -ENOMEM; + } + + mutex_init(&bl->mutex); + INIT_WORK(&bl->work, bl_work); + bl->props.max_brightness = pdata->max_brightness; + bl->props.power = pdata->power; + bl->props.brightness = pdata->brightness; + bl->retries = pdata->retries; + bl->dcdc = dcdc; + bl->isink = isink; + platform_set_drvdata(pdev, bl); + pmic = regulator_get_drvdata(bl->isink); + + wm8350_bl_ops.check_fb = pdata->check_fb; + + bl->device = backlight_device_register(pdev->dev.bus_id, &pdev->dev, + bl, &wm8350_bl_ops); + if (IS_ERR(bl->device)) { + ret = PTR_ERR(bl->device); + regulator_put(dcdc, &pdev->dev); + regulator_put(isink, &pdev->dev); + kfree(bl); + return ret; + } + + bl->notifier.notifier_call = wm8350_bl_notifier; + regulator_register_client(dcdc, &bl->notifier); + regulator_register_client(isink, &bl->notifier); + bl->device->props = bl->props; + + /* WM8350 ISINK & DCDC setup */ + if (pdata->isink == WM8350_ISINK_A) + pmic->isink_A_dcdc = pdata->dcdc; + else + pmic->isink_B_dcdc = pdata->dcdc; + + regulator_set_current(isink, 20000); + + wm8350_isink_set_flash(pmic, pdata->isink, + WM8350_ISINK_FLASH_DISABLE, + WM8350_ISINK_FLASH_TRIG_BIT, + WM8350_ISINK_FLASH_DUR_32MS, + WM8350_ISINK_FLASH_ON_1_00S, + WM8350_ISINK_FLASH_OFF_1_00S, + WM8350_ISINK_FLASH_MODE_EN); + + wm8350_dcdc25_set_mode(pmic, pdata->dcdc, + WM8350_ISINK_MODE_BOOST, WM8350_ISINK_ILIM_NORMAL, + pdata->voltage_ramp, pdata->isink == WM8350_ISINK_A ? + WM8350_DC5_FBSRC_ISINKA : WM8350_DC5_FBSRC_ISINKB); + + wm8350_dcdc_set_slot(pmic, pdata->dcdc, 15, 0, + pdata->dcdc == WM8350_DCDC_2 ? + WM8350_DC2_ERRACT_SHUTDOWN_CONV : WM8350_DC5_ERRACT_NONE); + + regulator_enable(isink); + backlight_update_status(bl->device); + return 0; +} + +static int wm8350_bl_remove(struct platform_device *pdev) +{ + struct wm8350_backlight *bl = + (struct wm8350_backlight *)platform_get_drvdata(pdev); + struct regulator *isink = bl->isink, *dcdc = bl->dcdc; + + bl->intensity = 0; + backlight_update_status(bl->device); + schedule_work(&bl->work); + flush_scheduled_work(); + backlight_device_unregister(bl->device); + + regulator_set_current(isink, 0); + regulator_disable(isink); + regulator_unregister_client(isink, &bl->notifier); + regulator_unregister_client(dcdc, &bl->notifier); + regulator_put(isink, &pdev->dev); + regulator_put(dcdc, &pdev->dev); + return 0; +} + +struct platform_driver imx32ads_backlight_driver = { + .driver = { + .name = "wm8350-bl", + .owner = THIS_MODULE, + }, + .probe = wm8350_bl_probe, + .remove = wm8350_bl_remove, + .suspend = wm8350_bl_suspend, + .resume = wm8350_bl_resume, +}; + +static int __devinit imx32ads_backlight_init(void) +{ + return platform_driver_register(&imx32ads_backlight_driver); +} + +static void imx32ads_backlight_exit(void) +{ + platform_driver_unregister(&imx32ads_backlight_driver); +} + +device_initcall_sync(imx32ads_backlight_init); +module_exit(imx32ads_backlight_exit); + +MODULE_AUTHOR("Liam Girdwood "); +MODULE_DESCRIPTION("WM8350 Backlight driver"); +MODULE_LICENSE("GPL"); diff -urN linux-2.6.26/drivers/video/console/fbcon.c linux-2.6.26-lab126/drivers/video/console/fbcon.c --- linux-2.6.26/drivers/video/console/fbcon.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/video/console/fbcon.c 2010-08-10 04:15:56.000000000 -0400 @@ -1302,7 +1302,6 @@ { struct fb_info *info = registered_fb[con2fb_map[vc->vc_num]]; struct fbcon_ops *ops = info->fbcon_par; - struct display *p = &fb_display[vc->vc_num]; u_int y_break; @@ -1331,10 +1330,11 @@ struct display *p = &fb_display[vc->vc_num]; struct fbcon_ops *ops = info->fbcon_par; - if (!fbcon_is_inactive(vc, info)) + if (!fbcon_is_inactive(vc, info)) { ops->putcs(vc, info, s, count, real_y(p, ypos), xpos, get_color(vc, info, scr_readw(s), 1), get_color(vc, info, scr_readw(s), 0)); + } } static void fbcon_putc(struct vc_data *vc, int c, int ypos, int xpos) @@ -3335,6 +3335,7 @@ .con_screen_pos = fbcon_screen_pos, .con_getxy = fbcon_getxy, .con_resize = fbcon_resize, + .con_preemptible = 1, }; static struct notifier_block fbcon_event_notifier = { diff -urN linux-2.6.26/drivers/video/console/vgacon.c linux-2.6.26-lab126/drivers/video/console/vgacon.c --- linux-2.6.26/drivers/video/console/vgacon.c 2008-07-13 17:51:29.000000000 -0400 +++ linux-2.6.26-lab126/drivers/video/console/vgacon.c 2010-08-10 04:15:56.000000000 -0400 @@ -51,7 +51,7 @@ #include